3622 files changed, 141502 insertions, 167081 deletions

diff --git a/.gitignore b/.gitignore
index a39bd54d38..cba5eac2a0 100644
--- a/.gitignore
+++ b/.gitignore
@@ -5,16 +5,20 @@
 #
 # Normal rules
 #
-
-*.rej
-*.orig
-*.a
+.*
 *.o
+*.o.*
+*.a
+*.s
 *.su
-*~
+*.mod.c
+*.i
+*.lst
+*.order
+*.elf
 *.swp
-*.patch
 *.bin
+*.patch
 *.cfgtmp
 *.dts.tmp
 
@@ -24,45 +28,36 @@
 #
 # Top-level generic files
 #
-
 /MLO*
 /SPL
 /System.map
-/u-boot
-/u-boot.hex
-/u-boot.imx
-/u-boot-with-spl.imx
-/u-boot-with-nand-spl.imx
-/u-boot.map
-/u-boot.srec
-/u-boot.ldr
-/u-boot.ldr.hex
-/u-boot.ldr.srec
-/u-boot.img
-/u-boot.kwb
-/u-boot.sha1
-/u-boot.dis
-/u-boot.lds
-/u-boot.ubl
-/u-boot.ais
-/u-boot.dtb
-/u-boot.sb
-/u-boot.bd
-/u-boot.geany
+/u-boot*
+
+#
+# git files that we don't want to ignore even it they are dot-files
+#
+!.gitignore
+!.mailmap
 
 #
 # Generated files
 #
 
-*.depend*
 /LOG
 /errlog
 /reloc_off
 
+!/spl/Makefile
+/spl/*
+/tpl/
+
+#
+# Generated include files
+#
+/include/config/
 /include/generated/
 /include/spl-autoconf.mk
 /include/tpl-autoconf.mk
-asm-offsets.s
 
 # stgit generated dirs
 patches-*
@@ -89,5 +84,6 @@ GRTAGS
 GSYMS
 GTAGS
 
-# spl ais files
-/spl/*.ais
+*.orig
+*~
+\#*#
diff --git a/CREDITS b/CREDITS
index 3b657e9005..52f289e06a 100644
--- a/CREDITS
+++ b/CREDITS
@@ -143,7 +143,7 @@ W: www.freescale.com
 
 N: Dr. Wolfgang Grandegger
 E: wg@denx.de
-D: Support for Interphase 4539 T1/E1/J1 PMC, PN62, CCM, SCM boards
+D: Support for Interphase 4539 T1/E1/J1 PMC, CCM, SCM boards
 W: www.denx.de
 
 N: Peter Figuli
diff --git a/Kbuild b/Kbuild
new file mode 100644
index 0000000000..6e1698c5bf
--- /dev/null
+++ b/Kbuild
@@ -0,0 +1,87 @@
+#
+# Kbuild for top-level directory of U-Boot
+# This file takes care of the following:
+# 1) Generate generic-asm-offsets.h
+# 2) Generate asm-offsets.h
+
+#####
+# 1) Generate generic-asm-offsets.h
+
+generic-offsets-file := include/generated/generic-asm-offsets.h
+
+always  := $(generic-offsets-file)
+targets := $(generic-offsets-file) lib/asm-offsets.s
+
+quiet_cmd_generic-offsets = GEN     $@
+define cmd_generic-offsets
+	(set -e; \
+	 echo "#ifndef __GENERIC_ASM_OFFSETS_H__"; \
+	 echo "#define __GENERIC_ASM_OFFSETS_H__"; \
+	 echo "/*"; \
+	 echo " * DO NOT MODIFY."; \
+	 echo " *"; \
+	 echo " * This file was generated by Kbuild"; \
+	 echo " *"; \
+	 echo " */"; \
+	 echo ""; \
+	 sed -ne $(sed-y) $<; \
+	 echo ""; \
+	 echo "#endif" ) > $@
+endef
+
+# We use internal kbuild rules to avoid the "is up to date" message from make
+lib/asm-offsets.s: lib/asm-offsets.c FORCE
+	$(Q)mkdir -p $(dir $@)
+	$(call if_changed_dep,cc_s_c)
+
+$(obj)/$(generic-offsets-file): lib/asm-offsets.s Kbuild
+	$(Q)mkdir -p $(dir $@)
+	$(call cmd,generic-offsets)
+
+#####
+# 2) Generate asm-offsets.h
+#
+
+ifneq ($(wildcard $(srctree)/arch/$(ARCH)/lib/asm-offsets.c),)
+offsets-file := include/generated/asm-offsets.h
+endif
+
+always  += $(offsets-file)
+targets += $(offsets-file)
+targets += arch/$(ARCH)/lib/asm-offsets.s
+
+
+# Default sed regexp - multiline due to syntax constraints
+define sed-y
+	"/^->/{s:->#\(.*\):/* \1 */:; \
+	s:^->\([^ ]*\) [\$$#]*\([-0-9]*\) \(.*\):#define \1 \2 /* \3 */:; \
+	s:^->\([^ ]*\) [\$$#]*\([^ ]*\) \(.*\):#define \1 \2 /* \3 */:; \
+	s:->::; p;}"
+endef
+
+CFLAGS_asm-offsets.o := -DDO_DEPS_ONLY
+
+quiet_cmd_offsets = GEN     $@
+define cmd_offsets
+	(set -e; \
+	 echo "#ifndef __ASM_OFFSETS_H__"; \
+	 echo "#define __ASM_OFFSETS_H__"; \
+	 echo "/*"; \
+	 echo " * DO NOT MODIFY."; \
+	 echo " *"; \
+	 echo " * This file was generated by Kbuild"; \
+	 echo " *"; \
+	 echo " */"; \
+	 echo ""; \
+	 sed -ne $(sed-y) $<; \
+	 echo ""; \
+	 echo "#endif" ) > $@
+endef
+
+# We use internal kbuild rules to avoid the "is up to date" message from make
+arch/$(ARCH)/lib/asm-offsets.s: arch/$(ARCH)/lib/asm-offsets.c FORCE
+	$(Q)mkdir -p $(dir $@)
+	$(call if_changed_dep,cc_s_c)
+
+$(obj)/$(offsets-file): arch/$(ARCH)/lib/asm-offsets.s Kbuild
+	$(call cmd,offsets)
diff --git a/MAKEALL b/MAKEALL
index a9253d3490..705a0bb5e1 100755
--- a/MAKEALL
+++ b/MAKEALL
@@ -18,6 +18,7 @@ usage()
 	  -c CPU,    --cpu CPU         Build all boards with cpu CPU
 	  -v VENDOR, --vendor VENDOR   Build all boards with vendor VENDOR
 	  -s SOC,    --soc SOC         Build all boards with soc SOC
+	  -b BOARD,  --board BOARD     Build all boards with board name BOARD
 	  -l,        --list            List all targets to be built
 	  -m,        --maintainers     List all targets and maintainer email
 	  -M,        --mails           List all targets and all affilated emails
@@ -59,8 +60,8 @@ usage()
 	exit ${ret}
 }
 
-SHORT_OPTS="ha:c:v:s:lmMCnr"
-LONG_OPTS="help,arch:,cpu:,vendor:,soc:,list,maintainers,mails,check,continue,rebuild-errors"
+SHORT_OPTS="ha:c:v:s:b:lmMCnr"
+LONG_OPTS="help,arch:,cpu:,vendor:,soc:,board:,list,maintainers,mails,check,continue,rebuild-errors"
 
 # Option processing based on util-linux-2.13/getopt-parse.bash
 
@@ -121,6 +122,17 @@ while true ; do
 		fi
 		SELECTED='y'
 		shift 2 ;;
+	-b|--board)
+		# echo "Option BOARD: argument \`$2'"
+		if [ "$opt_b" ] ; then
+			opt_b="${opt_b%)} || \$6 == \"$2\" || \$7 == \"$2\")"
+		else
+			# We need to check the 7th field too
+			# for boards whose 6th field is "-"
+			opt_b="(\$6 == \"$2\" || \$7 == \"$2\")"
+		fi
+		SELECTED='y'
+		shift 2 ;;
 	-C|--check)
 		CHECK='C=1'
 		shift ;;
@@ -158,6 +170,7 @@ FILTER="\$1 !~ /^#/"
 [ "$opt_c" ] && FILTER="${FILTER} && $opt_c"
 [ "$opt_s" ] && FILTER="${FILTER} && $opt_s"
 [ "$opt_v" ] && FILTER="${FILTER} && $opt_v"
+[ "$opt_b" ] && FILTER="${FILTER} && $opt_b"
 
 if [ "$SELECTED" ] ; then
 	SELECTED=$(awk '('"$FILTER"') { print $7 }' boards.cfg)
@@ -224,86 +237,84 @@ OLDEST_IDX=1
 RC=0
 
 # Helper funcs for parsing boards.cfg
-boards_by_field()
+targets_by_field()
 {
-	FS="[ \t]+"
-	[ -n "$3" ] && FS="$3"
-	awk \
-		-v field="$1" \
-		-v select="$2" \
-		-F "$FS" \
-		'($1 !~ /^#/ && $field == select) { print $7 }' \
-		boards.cfg
+	field=$1
+	regexp=$2
+
+	awk '($1 !~ /^#/ && $'"$field"' ~ /^'"$regexp"'$/) { print $7 }' \
+								boards.cfg
 }
-boards_by_arch() { boards_by_field 2 "$@" ; }
-boards_by_cpu()  { boards_by_field 3 "$@" "[: \t]+" ; }
-boards_by_soc()  { boards_by_field 4 "$@" ; }
+
+targets_by_arch() { targets_by_field 2 "$@" ; }
+targets_by_cpu()  { targets_by_field 3 "$@" ; targets_by_field 3 "$@:.*" ; }
+targets_by_soc()  { targets_by_field 4 "$@" ; }
 
 #########################################################################
 ## MPC5xx Systems
 #########################################################################
 
-LIST_5xx="$(boards_by_cpu mpc5xx)"
+LIST_5xx="$(targets_by_cpu mpc5xx)"
 
 #########################################################################
 ## MPC5xxx Systems
 #########################################################################
 
-LIST_5xxx="$(boards_by_cpu mpc5xxx)"
+LIST_5xxx="$(targets_by_cpu mpc5xxx)"
 
 #########################################################################
 ## MPC512x Systems
 #########################################################################
 
-LIST_512x="$(boards_by_cpu mpc512x)"
+LIST_512x="$(targets_by_cpu mpc512x)"
 
 #########################################################################
 ## MPC8xx Systems
 #########################################################################
 
-LIST_8xx="$(boards_by_cpu mpc8xx)"
+LIST_8xx="$(targets_by_cpu mpc8xx)"
 
 #########################################################################
 ## PPC4xx Systems
 #########################################################################
 
-LIST_4xx="$(boards_by_cpu ppc4xx)"
+LIST_4xx="$(targets_by_cpu ppc4xx)"
 
 #########################################################################
 ## MPC824x Systems
 #########################################################################
 
-LIST_824x="$(boards_by_cpu mpc824x)"
+LIST_824x="$(targets_by_cpu mpc824x)"
 
 #########################################################################
 ## MPC8260 Systems (includes 8250, 8255 etc.)
 #########################################################################
 
-LIST_8260="$(boards_by_cpu mpc8260)"
+LIST_8260="$(targets_by_cpu mpc8260)"
 
 #########################################################################
 ## MPC83xx Systems (includes 8349, etc.)
 #########################################################################
 
-LIST_83xx="$(boards_by_cpu mpc83xx)"
+LIST_83xx="$(targets_by_cpu mpc83xx)"
 
 #########################################################################
 ## MPC85xx Systems (includes 8540, 8560 etc.)
 #########################################################################
 
-LIST_85xx="$(boards_by_cpu mpc85xx)"
+LIST_85xx="$(targets_by_cpu mpc85xx)"
 
 #########################################################################
 ## MPC86xx Systems
 #########################################################################
 
-LIST_86xx="$(boards_by_cpu mpc86xx)"
+LIST_86xx="$(targets_by_cpu mpc86xx)"
 
 #########################################################################
 ## 74xx/7xx Systems
 #########################################################################
 
-LIST_74xx_7xx="$(boards_by_cpu 74xx_7xx)"
+LIST_74xx_7xx="$(targets_by_cpu 74xx_7xx)"
 
 #########################################################################
 ## PowerPC groups
@@ -339,61 +350,69 @@ LIST_ppc="		\
 ## StrongARM Systems
 #########################################################################
 
-LIST_SA="$(boards_by_cpu sa1100)"
+LIST_SA="$(targets_by_cpu sa1100)"
 
 #########################################################################
 ## ARM7 Systems
 #########################################################################
 
-LIST_ARM7="$(boards_by_cpu arm720t)"
+LIST_ARM7="$(targets_by_cpu arm720t)"
 
 #########################################################################
 ## ARM9 Systems
 #########################################################################
 
-LIST_ARM9="$(boards_by_cpu arm920t)	\
-	$(boards_by_cpu arm926ejs)	\
-	$(boards_by_cpu arm946es)	\
+LIST_ARM9="$(targets_by_cpu arm920t)	\
+	$(targets_by_cpu arm926ejs)	\
+	$(targets_by_cpu arm946es)	\
 "
 
 #########################################################################
 ## ARM11 Systems
 #########################################################################
-LIST_ARM11="$(boards_by_cpu arm1136)	\
-	$(boards_by_cpu arm1176)	\
+LIST_ARM11="$(targets_by_cpu arm1136)	\
+	$(targets_by_cpu arm1176)	\
 "
 
 #########################################################################
 ## ARMV7 Systems
 #########################################################################
 
-LIST_ARMV7="$(boards_by_cpu armv7)"
+LIST_ARMV7="$(targets_by_cpu armv7)"
+
+#########################################################################
+## ARMV8 Systems
+#########################################################################
+
+LIST_ARMV8="$(targets_by_cpu armv8)"
 
 #########################################################################
 ## AT91 Systems
 #########################################################################
 
-LIST_at91="$(boards_by_soc at91)"
+LIST_at91="$(targets_by_soc at91)"
 
 #########################################################################
 ## Xscale Systems
 #########################################################################
 
-LIST_pxa="$(boards_by_cpu pxa)"
-
-LIST_ixp="$(boards_by_cpu ixp)"
+LIST_pxa="$(targets_by_cpu pxa)"
 
 #########################################################################
 ## SPEAr Systems
 #########################################################################
 
-LIST_spear="$(boards_by_soc spear)"
+LIST_spear="$(targets_by_soc spear)"
 
 #########################################################################
 ## ARM groups
 #########################################################################
 
-LIST_arm="$(boards_by_arch arm)"
+LIST_arm="$(targets_by_arch arm |		\
+	for ARMV8_TARGET in $LIST_ARMV8;	\
+		do sed "/$ARMV8_TARGET/d";	\
+	done)					\
+"
 
 #########################################################################
 ## MIPS Systems		(default = big endian)
@@ -447,66 +466,72 @@ LIST_mips_el="			\
 ## OpenRISC Systems
 #########################################################################
 
-LIST_openrisc="$(boards_by_arch openrisc)"
+LIST_openrisc="$(targets_by_arch openrisc)"
 
 #########################################################################
 ## x86 Systems
 #########################################################################
 
-LIST_x86="$(boards_by_arch x86)"
+LIST_x86="$(targets_by_arch x86)"
 
 #########################################################################
 ## Nios-II Systems
 #########################################################################
 
-LIST_nios2="$(boards_by_arch nios2)"
+LIST_nios2="$(targets_by_arch nios2)"
 
 #########################################################################
 ## MicroBlaze Systems
 #########################################################################
 
-LIST_microblaze="$(boards_by_arch microblaze)"
+LIST_microblaze="$(targets_by_arch microblaze)"
 
 #########################################################################
 ## ColdFire Systems
 #########################################################################
 
-LIST_m68k="$(boards_by_arch m68k)"
+LIST_m68k="$(targets_by_arch m68k)"
 LIST_coldfire=${LIST_m68k}
 
 #########################################################################
 ## AVR32 Systems
 #########################################################################
 
-LIST_avr32="$(boards_by_arch avr32)"
+LIST_avr32="$(targets_by_arch avr32)"
 
 #########################################################################
 ## Blackfin Systems
 #########################################################################
 
-LIST_blackfin="$(boards_by_arch blackfin)"
+LIST_blackfin="$(targets_by_arch blackfin)"
 
 #########################################################################
 ## SH Systems
 #########################################################################
 
-LIST_sh2="$(boards_by_cpu sh2)"
-LIST_sh3="$(boards_by_cpu sh3)"
-LIST_sh4="$(boards_by_cpu sh4)"
+LIST_sh2="$(targets_by_cpu sh2)"
+LIST_sh3="$(targets_by_cpu sh3)"
+LIST_sh4="$(targets_by_cpu sh4)"
 
-LIST_sh="$(boards_by_arch sh)"
+LIST_sh="$(targets_by_arch sh)"
 
 #########################################################################
 ## SPARC Systems
 #########################################################################
 
-LIST_sparc="$(boards_by_arch sparc)"
+LIST_sparc="$(targets_by_arch sparc)"
 
 #########################################################################
 ## NDS32 Systems
 #########################################################################
 
-LIST_nds32="$(boards_by_arch nds32)"
+LIST_nds32="$(targets_by_arch nds32)"
+
+#########################################################################
+## ARC Systems
+#########################################################################
+
+LIST_arc="$(targets_by_arch arc)"
 
 #-----------------------------------------------------------------------
 
@@ -518,7 +543,7 @@ get_target_location() {
 	local vendor=""
 
 	# Automatic mode
-	local line=`awk -F '\ +' '\$7 == "'"$target"'" { print \$0 }' boards.cfg`
+	local line=`awk '\$7 == "'"$target"'" { print \$0 }' boards.cfg`
 	if [ -z "${line}" ] ; then echo "" ; return ; fi
 
 	set ${line}
@@ -556,7 +581,7 @@ get_target_location() {
 get_target_maintainers() {
 	local name=`echo $1 | cut -d : -f 3`
 
-	local line=`awk -F '\ +' '\$7 == "'"$target"'" { print \$0 }' boards.cfg`
+	local line=`awk '\$7 == "'"$target"'" { print \$0 }' boards.cfg`
 	if [ -z "${line}" ]; then
 		echo ""
 		return ;
@@ -571,7 +596,7 @@ get_target_arch() {
 	local target=$1
 
 	# Automatic mode
-	local line=`egrep -i "^[[:space:]]*${target}[[:space:]]" boards.cfg`
+	local line=`awk '\$7 == "'"$target"'" { print \$0 }' boards.cfg`
 
 	if [ -z "${line}" ] ; then echo "" ; return ; fi
 
@@ -647,8 +672,6 @@ build_target() {
 		output_dir="${OUTPUT_PREFIX}"
 	fi
 
-	export BUILD_DIR="${output_dir}"
-
 	target_arch=$(get_target_arch ${target})
 	eval cross_toolchain=\$CROSS_COMPILE_`echo $target_arch | tr '[:lower:]' '[:upper:]'`
 	if [ "${cross_toolchain}" ] ; then
@@ -659,6 +682,10 @@ build_target() {
 	    MAKE=make
 	fi
 
+	if [  "${output_dir}" != "." ] ; then
+		MAKE="${MAKE} O=${output_dir}"
+	fi
+
 	${MAKE} distclean >/dev/null
 	${MAKE} -s ${target}_config
 
@@ -673,7 +700,7 @@ build_target() {
 	if [ $BUILD_MANY == 1 ] ; then
 		trap - TERM
 
-		${MAKE} -s tidy
+		${MAKE} -s clean
 
 		if [ -s ${LOG_DIR}/${target}.ERR ] ; then
 			cp ${LOG_DIR}/${target}.ERR ${OUTPUT_PREFIX}/ERR/${target}
diff --git a/Makefile b/Makefile
index dc0417914e..63d79ba560 100644
--- a/Makefile
+++ b/Makefile
@@ -5,17 +5,174 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-VERSION = 2013
-PATCHLEVEL = 10
+VERSION = 2014
+PATCHLEVEL = 04
 SUBLEVEL =
 EXTRAVERSION =
-ifneq "$(SUBLEVEL)" ""
-U_BOOT_VERSION = $(VERSION).$(PATCHLEVEL).$(SUBLEVEL)$(EXTRAVERSION)
+NAME =
+
+# *DOCUMENTATION*
+# To see a list of typical targets execute "make help"
+# More info can be located in ./README
+# Comments in this file are targeted only to the developer, do not
+# expect to learn how to build the kernel reading this file.
+
+# Do not:
+# o  use make's built-in rules and variables
+#    (this increases performance and avoids hard-to-debug behaviour);
+# o  print "Entering directory ...";
+MAKEFLAGS += -rR --no-print-directory
+
+# Avoid funny character set dependencies
+unexport LC_ALL
+LC_COLLATE=C
+LC_NUMERIC=C
+export LC_COLLATE LC_NUMERIC
+
+# We are using a recursive build, so we need to do a little thinking
+# to get the ordering right.
+#
+# Most importantly: sub-Makefiles should only ever modify files in
+# their own directory. If in some directory we have a dependency on
+# a file in another dir (which doesn't happen often, but it's often
+# unavoidable when linking the built-in.o targets which finally
+# turn into vmlinux), we will call a sub make in that other dir, and
+# after that we are sure that everything which is in that other dir
+# is now up to date.
+#
+# The only cases where we need to modify files which have global
+# effects are thus separated out and done before the recursive
+# descending is started. They are now explicitly listed as the
+# prepare rule.
+
+# To put more focus on warnings, be less verbose as default
+# Use 'make V=1' to see the full commands
+
+ifeq ("$(origin V)", "command line")
+  KBUILD_VERBOSE = $(V)
+endif
+ifndef KBUILD_VERBOSE
+  KBUILD_VERBOSE = 0
+endif
+
+# Call a source code checker (by default, "sparse") as part of the
+# C compilation.
+#
+# Use 'make C=1' to enable checking of only re-compiled files.
+# Use 'make C=2' to enable checking of *all* source files, regardless
+# of whether they are re-compiled or not.
+#
+# See the file "Documentation/sparse.txt" for more details, including
+# where to get the "sparse" utility.
+
+ifeq ("$(origin C)", "command line")
+  KBUILD_CHECKSRC = $(C)
+endif
+ifndef KBUILD_CHECKSRC
+  KBUILD_CHECKSRC = 0
+endif
+
+# Use make M=dir to specify directory of external module to build
+# Old syntax make ... SUBDIRS=$PWD is still supported
+# Setting the environment variable KBUILD_EXTMOD take precedence
+ifdef SUBDIRS
+  KBUILD_EXTMOD ?= $(SUBDIRS)
+endif
+
+ifeq ("$(origin M)", "command line")
+  KBUILD_EXTMOD := $(M)
+endif
+
+# kbuild supports saving output files in a separate directory.
+# To locate output files in a separate directory two syntaxes are supported.
+# In both cases the working directory must be the root of the kernel src.
+# 1) O=
+# Use "make O=dir/to/store/output/files/"
+#
+# 2) Set KBUILD_OUTPUT
+# Set the environment variable KBUILD_OUTPUT to point to the directory
+# where the output files shall be placed.
+# export KBUILD_OUTPUT=dir/to/store/output/files/
+# make
+#
+# The O= assignment takes precedence over the KBUILD_OUTPUT environment
+# variable.
+
+
+# KBUILD_SRC is set on invocation of make in OBJ directory
+# KBUILD_SRC is not intended to be used by the regular user (for now)
+ifeq ($(KBUILD_SRC),)
+
+# OK, Make called in directory where kernel src resides
+# Do we want to locate output files in a separate directory?
+ifeq ("$(origin O)", "command line")
+  KBUILD_OUTPUT := $(O)
+endif
+
+ifeq ("$(origin W)", "command line")
+  export KBUILD_ENABLE_EXTRA_GCC_CHECKS := $(W)
+endif
+
+# That's our default target when none is given on the command line
+PHONY := _all
+_all:
+
+# Cancel implicit rules on top Makefile
+$(CURDIR)/Makefile Makefile: ;
+
+ifneq ($(KBUILD_OUTPUT),)
+# Invoke a second make in the output directory, passing relevant variables
+# check that the output directory actually exists
+saved-output := $(KBUILD_OUTPUT)
+KBUILD_OUTPUT := $(shell mkdir -p $(KBUILD_OUTPUT) && cd $(KBUILD_OUTPUT) \
+								&& /bin/pwd)
+$(if $(KBUILD_OUTPUT),, \
+     $(error output directory "$(saved-output)" does not exist))
+
+PHONY += $(MAKECMDGOALS) sub-make
+
+$(filter-out _all sub-make $(CURDIR)/Makefile, $(MAKECMDGOALS)) _all: sub-make
+	@:
+
+sub-make: FORCE
+	$(if $(KBUILD_VERBOSE:1=),@)$(MAKE) -C $(KBUILD_OUTPUT) \
+	KBUILD_SRC=$(CURDIR) \
+	KBUILD_EXTMOD="$(KBUILD_EXTMOD)" -f $(CURDIR)/Makefile \
+	$(filter-out _all sub-make,$(MAKECMDGOALS))
+
+# Leave processing to above invocation of make
+skip-makefile := 1
+endif # ifneq ($(KBUILD_OUTPUT),)
+endif # ifeq ($(KBUILD_SRC),)
+
+# We process the rest of the Makefile if this is the final invocation of make
+ifeq ($(skip-makefile),)
+
+# If building an external module we do not care about the all: rule
+# but instead _all depend on modules
+PHONY += all
+ifeq ($(KBUILD_EXTMOD),)
+_all: all
 else
-U_BOOT_VERSION = $(VERSION).$(PATCHLEVEL)$(EXTRAVERSION)
+_all: modules
 endif
-TIMESTAMP_FILE = $(obj)include/generated/timestamp_autogenerated.h
-VERSION_FILE = $(obj)include/generated/version_autogenerated.h
+
+srctree		:= $(if $(KBUILD_SRC),$(KBUILD_SRC),$(CURDIR))
+objtree		:= $(CURDIR)
+src		:= $(srctree)
+obj		:= $(objtree)
+
+VPATH		:= $(srctree)$(if $(KBUILD_EXTMOD),:$(KBUILD_EXTMOD))
+
+export srctree objtree VPATH
+
+MKCONFIG	:= $(srctree)/mkconfig
+export MKCONFIG
+
+# Make sure CDPATH settings don't interfere
+unexport CDPATH
+
+#########################################################################
 
 HOSTARCH := $(shell uname -m | \
 	sed -e s/i.86/x86/ \
@@ -36,329 +193,465 @@ export	HOSTARCH HOSTOS
 VENDOR=
 
 #########################################################################
-# Allow for silent builds
-ifeq (,$(findstring s,$(MAKEFLAGS)))
-XECHO = echo
-else
-XECHO = :
+
+# set default to nothing for native builds
+ifeq ($(HOSTARCH),$(ARCH))
+CROSS_COMPILE ?=
 endif
 
-#########################################################################
+# SHELL used by kbuild
+CONFIG_SHELL := $(shell if [ -x "$$BASH" ]; then echo $$BASH; \
+	  else if [ -x /bin/bash ]; then echo /bin/bash; \
+	  else echo sh; fi ; fi)
+
+HOSTCC       = gcc
+HOSTCFLAGS   = -Wall -Wstrict-prototypes -O2 -fomit-frame-pointer
+
+ifeq ($(HOSTOS),cygwin)
+HOSTCFLAGS	+= -ansi
+endif
+
+# Mac OS X / Darwin's C preprocessor is Apple specific.  It
+# generates numerous errors and warnings.  We want to bypass it
+# and use GNU C's cpp.	To do this we pass the -traditional-cpp
+# option to the compiler.  Note that the -traditional-cpp flag
+# DOES NOT have the same semantics as GNU C's flag, all it does
+# is invoke the GNU preprocessor in stock ANSI/ISO C fashion.
 #
-# U-boot build supports generating object files in a separate external
-# directory. Two use cases are supported:
+# Apple's linker is similar, thanks to the new 2 stage linking
+# multiple symbol definitions are treated as errors, hence the
+# -multiply_defined suppress option to turn off this error.
 #
-# 1) Add O= to the make command line
-# 'make O=/tmp/build all'
+ifeq ($(HOSTOS),darwin)
+# get major and minor product version (e.g. '10' and '6' for Snow Leopard)
+DARWIN_MAJOR_VERSION	= $(shell sw_vers -productVersion | cut -f 1 -d '.')
+DARWIN_MINOR_VERSION	= $(shell sw_vers -productVersion | cut -f 2 -d '.')
+
+os_x_before	= $(shell if [ $(DARWIN_MAJOR_VERSION) -le $(1) -a \
+	$(DARWIN_MINOR_VERSION) -le $(2) ] ; then echo "$(3)"; else echo "$(4)"; fi ;)
+
+# Snow Leopards build environment has no longer restrictions as described above
+HOSTCC       = $(call os_x_before, 10, 5, "cc", "gcc")
+HOSTCFLAGS  += $(call os_x_before, 10, 4, "-traditional-cpp")
+HOSTLDFLAGS += $(call os_x_before, 10, 5, "-multiply_defined suppress")
+endif
+
+# Decide whether to build built-in, modular, or both.
+# Normally, just do built-in.
+
+KBUILD_MODULES :=
+KBUILD_BUILTIN := 1
+
+#	If we have only "make modules", don't compile built-in objects.
+#	When we're building modules with modversions, we need to consider
+#	the built-in objects during the descend as well, in order to
+#	make sure the checksums are up to date before we record them.
+
+ifeq ($(MAKECMDGOALS),modules)
+  KBUILD_BUILTIN := $(if $(CONFIG_MODVERSIONS),1)
+endif
+
+#	If we have "make <whatever> modules", compile modules
+#	in addition to whatever we do anyway.
+#	Just "make" or "make all" shall build modules as well
+
+# U-Boot does not need modules
+#ifneq ($(filter all _all modules,$(MAKECMDGOALS)),)
+#  KBUILD_MODULES := 1
+#endif
+
+#ifeq ($(MAKECMDGOALS),)
+#  KBUILD_MODULES := 1
+#endif
+
+export KBUILD_MODULES KBUILD_BUILTIN
+export KBUILD_CHECKSRC KBUILD_SRC KBUILD_EXTMOD
+
+# Beautify output
+# ---------------------------------------------------------------------------
+#
+# Normally, we echo the whole command before executing it. By making
+# that echo $($(quiet)$(cmd)), we now have the possibility to set
+# $(quiet) to choose other forms of output instead, e.g.
 #
-# 2) Set environment variable BUILD_DIR to point to the desired location
-# 'export BUILD_DIR=/tmp/build'
-# 'make'
+#         quiet_cmd_cc_o_c = Compiling $(RELDIR)/$@
+#         cmd_cc_o_c       = $(CC) $(c_flags) -c -o $@ $<
 #
-# The second approach can also be used with a MAKEALL script
-# 'export BUILD_DIR=/tmp/build'
-# './MAKEALL'
+# If $(quiet) is empty, the whole command will be printed.
+# If it is set to "quiet_", only the short version will be printed. 
+# If it is set to "silent_", nothing will be printed at all, since
+# the variable $(silent_cmd_cc_o_c) doesn't exist.
 #
-# Command line 'O=' setting overrides BUILD_DIR environment variable.
+# A simple variant is to prefix commands with $(Q) - that's useful
+# for commands that shall be hidden in non-verbose mode.
 #
-# When none of the above methods is used the local build is performed and
-# the object files are placed in the source directory.
+#	$(Q)ln $@ :<
 #
+# If KBUILD_VERBOSE equals 0 then the above command will be hidden.
+# If KBUILD_VERBOSE equals 1 then the above command is displayed.
 
-ifdef O
-ifeq ("$(origin O)", "command line")
-BUILD_DIR := $(O)
-endif
+ifeq ($(KBUILD_VERBOSE),1)
+  quiet =
+  Q =
+else
+  quiet=quiet_
+  Q = @
 endif
 
-# Call a source code checker (by default, "sparse") as part of the
-# C compilation.
-#
-# Use 'make C=1' to enable checking of re-compiled files.
-#
-# See the linux kernel file "Documentation/sparse.txt" for more details,
-# including where to get the "sparse" utility.
+# If the user is running make -s (silent mode), suppress echoing of
+# commands
 
-ifdef C
-ifeq ("$(origin C)", "command line")
-CHECKSRC := $(C)
+ifneq ($(filter s% -s%,$(MAKEFLAGS)),)
+  quiet=silent_
 endif
+
+export quiet Q KBUILD_VERBOSE
+
+
+# Look for make include files relative to root of kernel src
+MAKEFLAGS += --include-dir=$(srctree)
+
+# We need some generic definitions (do not try to remake the file).
+$(srctree)/scripts/Kbuild.include: ;
+include $(srctree)/scripts/Kbuild.include
+
+# Make variables (CC, etc...)
+
+AS		= $(CROSS_COMPILE)as
+# Always use GNU ld
+ifneq ($(shell $(CROSS_COMPILE)ld.bfd -v 2> /dev/null),)
+LD		= $(CROSS_COMPILE)ld.bfd
+else
+LD		= $(CROSS_COMPILE)ld
 endif
-ifndef CHECKSRC
-  CHECKSRC = 0
+CC		= $(CROSS_COMPILE)gcc
+CPP		= $(CC) -E
+AR		= $(CROSS_COMPILE)ar
+NM		= $(CROSS_COMPILE)nm
+LDR		= $(CROSS_COMPILE)ldr
+STRIP		= $(CROSS_COMPILE)strip
+OBJCOPY		= $(CROSS_COMPILE)objcopy
+OBJDUMP		= $(CROSS_COMPILE)objdump
+AWK		= awk
+RANLIB		= $(CROSS_COMPILE)RANLIB
+DTC		= dtc
+CHECK		= sparse
+
+CHECKFLAGS     := -D__linux__ -Dlinux -D__STDC__ -Dunix -D__unix__ \
+		  -Wbitwise -Wno-return-void -D__CHECK_ENDIAN__ $(CF)
+
+KBUILD_CPPFLAGS := -D__KERNEL__
+
+KBUILD_CFLAGS   := -Wall -Wstrict-prototypes \
+		   -Wno-format-security \
+		   -fno-builtin -ffreestanding
+KBUILD_AFLAGS   := -D__ASSEMBLY__
+
+# Read UBOOTRELEASE from include/config/uboot.release (if it exists)
+UBOOTRELEASE = $(shell cat include/config/uboot.release 2> /dev/null)
+UBOOTVERSION = $(VERSION)$(if $(PATCHLEVEL),.$(PATCHLEVEL)$(if $(SUBLEVEL),.$(SUBLEVEL)))$(EXTRAVERSION)
+
+export VERSION PATCHLEVEL SUBLEVEL UBOOTRELEASE UBOOTVERSION
+export ARCH CPU BOARD VENDOR SOC CPUDIR BOARDDIR
+export CONFIG_SHELL HOSTCC HOSTCFLAGS HOSTLDFLAGS CROSS_COMPILE AS LD CC
+export CPP AR NM LDR STRIP OBJCOPY OBJDUMP
+export MAKE AWK
+export DTC CHECK CHECKFLAGS
+
+export KBUILD_CPPFLAGS NOSTDINC_FLAGS UBOOTINCLUDE OBJCOPYFLAGS LDFLAGS
+export KBUILD_CFLAGS KBUILD_AFLAGS
+
+# When compiling out-of-tree modules, put MODVERDIR in the module
+# tree rather than in the kernel tree. The kernel tree might
+# even be read-only.
+export MODVERDIR := $(if $(KBUILD_EXTMOD),$(firstword $(KBUILD_EXTMOD))/).tmp_versions
+
+# Files to ignore in find ... statements
+
+RCS_FIND_IGNORE := \( -name SCCS -o -name BitKeeper -o -name .svn -o -name CVS \
+		   -o -name .pc -o -name .hg -o -name .git \) -prune -o
+export RCS_TAR_IGNORE := --exclude SCCS --exclude BitKeeper --exclude .svn \
+			 --exclude CVS --exclude .pc --exclude .hg --exclude .git
+
+# ===========================================================================
+# Rules shared between *config targets and build targets
+
+# Basic helpers built in scripts/
+PHONY += scripts_basic
+scripts_basic:
+	$(Q)$(MAKE) $(build)=scripts/basic
+	$(Q)rm -f .tmp_quiet_recordmcount
+
+# To avoid any implicit rule to kick in, define an empty command.
+scripts/basic/%: scripts_basic ;
+
+PHONY += outputmakefile
+# outputmakefile generates a Makefile in the output directory, if using a
+# separate output directory. This allows convenient use of make in the
+# output directory.
+outputmakefile:
+ifneq ($(KBUILD_SRC),)
+	$(Q)ln -fsn $(srctree) source
+	$(Q)$(CONFIG_SHELL) $(srctree)/scripts/mkmakefile \
+	    $(srctree) $(objtree) $(VERSION) $(PATCHLEVEL)
 endif
-export CHECKSRC
 
-ifneq ($(BUILD_DIR),)
-saved-output := $(BUILD_DIR)
+# To make sure we do not include .config for any of the *config targets
+# catch them early, and hand them over to scripts/kconfig/Makefile
+# It is allowed to specify more targets when calling make, including
+# mixing *config targets and build targets.
+# For example 'make oldconfig all'.
+# Detect when mixed targets is specified, and make a second invocation
+# of make so .config is not included in this case either (for *config).
 
-# Attempt to create a output directory.
-$(shell [ -d ${BUILD_DIR} ] || mkdir -p ${BUILD_DIR})
+version_h := include/generated/version_autogenerated.h
+timestamp_h := include/generated/timestamp_autogenerated.h
 
-# Verify if it was successful.
-BUILD_DIR := $(shell cd $(BUILD_DIR) && /bin/pwd)
-$(if $(BUILD_DIR),,$(error output directory "$(saved-output)" does not exist))
-endif # ifneq ($(BUILD_DIR),)
+no-dot-config-targets := clean clobber mrproper distclean \
+			 help %docs check% coccicheck \
+			 ubootversion backup tools-only
 
-OBJTREE		:= $(if $(BUILD_DIR),$(BUILD_DIR),$(CURDIR))
-SPLTREE		:= $(OBJTREE)/spl
-TPLTREE		:= $(OBJTREE)/tpl
-SRCTREE		:= $(CURDIR)
-TOPDIR		:= $(SRCTREE)
-LNDIR		:= $(OBJTREE)
-export	TOPDIR SRCTREE OBJTREE SPLTREE TPLTREE
+config-targets := 0
+mixed-targets  := 0
+dot-config     := 1
 
-MKCONFIG	:= $(SRCTREE)/mkconfig
-export MKCONFIG
-
-ifneq ($(OBJTREE),$(SRCTREE))
-REMOTE_BUILD	:= 1
-export REMOTE_BUILD
+ifneq ($(filter $(no-dot-config-targets), $(MAKECMDGOALS)),)
+	ifeq ($(filter-out $(no-dot-config-targets), $(MAKECMDGOALS)),)
+		dot-config := 0
+	endif
 endif
 
-# $(obj) and (src) are defined in config.mk but here in main Makefile
-# we also need them before config.mk is included which is the case for
-# some targets like unconfig, clean, clobber, distclean, etc.
-ifneq ($(OBJTREE),$(SRCTREE))
-obj := $(OBJTREE)/
-src := $(SRCTREE)/
-else
-obj :=
-src :=
+ifeq ($(KBUILD_EXTMOD),)
+        ifneq ($(filter config %config,$(MAKECMDGOALS)),)
+                config-targets := 1
+                ifneq ($(filter-out config %config,$(MAKECMDGOALS)),)
+                        mixed-targets := 1
+                endif
+        endif
 endif
-export obj src
 
-# Make sure CDPATH settings don't interfere
-unexport CDPATH
+ifeq ($(mixed-targets),1)
+# ===========================================================================
+# We're called with mixed targets (*config and build targets).
+# Handle them one by one.
 
-#########################################################################
+PHONY += $(MAKECMDGOALS) build-one-by-one
 
-# The "tools" are needed early, so put this first
-# Don't include stuff already done in $(LIBS)
-# The "examples" conditionally depend on U-Boot (say, when USE_PRIVATE_LIBGCC
-# is "yes"), so compile examples after U-Boot is compiled.
-SUBDIR_TOOLS = tools
-SUBDIR_EXAMPLES = examples/standalone examples/api
-SUBDIRS = $(SUBDIR_TOOLS)
+$(MAKECMDGOALS): build-one-by-one
+	@:
 
-.PHONY : $(SUBDIRS) $(VERSION_FILE) $(TIMESTAMP_FILE)
+build-one-by-one:
+	$(Q)set -e; \
+	for i in $(MAKECMDGOALS); do \
+		$(MAKE) -f $(srctree)/Makefile $$i; \
+	done
 
-ifeq ($(obj)include/config.mk,$(wildcard $(obj)include/config.mk))
+else
+ifeq ($(config-targets),1)
+# ===========================================================================
+# *config targets only - make sure prerequisites are updated, and descend
+# in scripts/kconfig to make the *config target
 
-# Include autoconf.mk before config.mk so that the config options are available
-# to all top level build files.  We need the dummy all: target to prevent the
-# dependency target in autoconf.mk.dep from being the default.
-all:
-sinclude $(obj)include/autoconf.mk.dep
-sinclude $(obj)include/autoconf.mk
+# Read arch specific Makefile to set KBUILD_DEFCONFIG as needed.
+# KBUILD_DEFCONFIG may point out an alternative default configuration
+# used for 'make defconfig'
 
-ifndef CONFIG_SANDBOX
-SUBDIRS += $(SUBDIR_EXAMPLES)
-endif
+%_config:: outputmakefile
+	@$(MKCONFIG) -A $(@:_config=)
+
+else
+# ===========================================================================
+# Build targets only - this includes vmlinux, arch specific targets, clean
+# targets and others. In general all targets except *config targets.
 
 # load ARCH, BOARD, and CPU configuration
-include $(obj)include/config.mk
-export	ARCH CPU BOARD VENDOR SOC
+-include include/config.mk
 
-# set default to nothing for native builds
-ifeq ($(HOSTARCH),$(ARCH))
-CROSS_COMPILE ?=
-endif
+ifeq ($(dot-config),1)
+# Read in config
+-include include/autoconf.mk
+-include include/autoconf.mk.dep
 
 # load other configuration
-include $(TOPDIR)/config.mk
-
-# Targets which don't build the source code
-NON_BUILD_TARGETS = backup clean clobber distclean mkproper tidy unconfig
+include $(srctree)/config.mk
 
-# Only do the generic board check when actually building, not configuring
-ifeq ($(filter $(NON_BUILD_TARGETS),$(MAKECMDGOALS)),)
-ifeq ($(findstring _config,$(MAKECMDGOALS)),)
-$(CHECK_GENERIC_BOARD)
-endif
+ifeq ($(wildcard include/config.mk),)
+$(error "System not configured - see README")
 endif
 
 # If board code explicitly specified LDSCRIPT or CONFIG_SYS_LDSCRIPT, use
 # that (or fail if absent).  Otherwise, search for a linker script in a
 # standard location.
 
-LDSCRIPT_MAKEFILE_DIR = $(dir $(LDSCRIPT))
-
 ifndef LDSCRIPT
-	#LDSCRIPT := $(TOPDIR)/board/$(BOARDDIR)/u-boot.lds.debug
+	#LDSCRIPT := $(srctree)/board/$(BOARDDIR)/u-boot.lds.debug
 	ifdef CONFIG_SYS_LDSCRIPT
 		# need to strip off double quotes
-		LDSCRIPT := $(subst ",,$(CONFIG_SYS_LDSCRIPT))
+		LDSCRIPT := $(srctree)/$(CONFIG_SYS_LDSCRIPT:"%"=%)
 	endif
 endif
 
 # If there is no specified link script, we look in a number of places for it
 ifndef LDSCRIPT
 	ifeq ($(CONFIG_NAND_U_BOOT),y)
-		LDSCRIPT := $(TOPDIR)/board/$(BOARDDIR)/u-boot-nand.lds
+		LDSCRIPT := $(srctree)/board/$(BOARDDIR)/u-boot-nand.lds
 		ifeq ($(wildcard $(LDSCRIPT)),)
-			LDSCRIPT := $(TOPDIR)/$(CPUDIR)/u-boot-nand.lds
+			LDSCRIPT := $(srctree)/$(CPUDIR)/u-boot-nand.lds
 		endif
 	endif
 	ifeq ($(wildcard $(LDSCRIPT)),)
-		LDSCRIPT := $(TOPDIR)/board/$(BOARDDIR)/u-boot.lds
+		LDSCRIPT := $(srctree)/board/$(BOARDDIR)/u-boot.lds
 	endif
 	ifeq ($(wildcard $(LDSCRIPT)),)
-		LDSCRIPT := $(TOPDIR)/$(CPUDIR)/u-boot.lds
+		LDSCRIPT := $(srctree)/$(CPUDIR)/u-boot.lds
 	endif
 	ifeq ($(wildcard $(LDSCRIPT)),)
-		LDSCRIPT := $(TOPDIR)/arch/$(ARCH)/cpu/u-boot.lds
-		# We don't expect a Makefile here
-		LDSCRIPT_MAKEFILE_DIR =
-	endif
-	ifeq ($(wildcard $(LDSCRIPT)),)
-$(error could not find linker script)
+		LDSCRIPT := $(srctree)/arch/$(ARCH)/cpu/u-boot.lds
 	endif
 endif
 
-#########################################################################
-# U-Boot objects....order is important (i.e. start must be first)
+else
 
-OBJS  = $(CPUDIR)/start.o
-ifeq ($(CPU),ppc4xx)
-OBJS += $(CPUDIR)/resetvec.o
-endif
-ifeq ($(CPU),mpc85xx)
-OBJS += $(CPUDIR)/resetvec.o
+
+endif # $(dot-config)
+
+KBUILD_CFLAGS += -Os #-fomit-frame-pointer
+
+ifdef BUILD_TAG
+KBUILD_CFLAGS += -DBUILD_TAG='"$(BUILD_TAG)"'
 endif
 
-OBJS := $(addprefix $(obj),$(OBJS))
+KBUILD_CFLAGS += $(call cc-option,-fno-stack-protector)
 
-HAVE_VENDOR_COMMON_LIB = $(if $(wildcard board/$(VENDOR)/common/Makefile),y,n)
+KBUILD_CFLAGS	+= -g
+# $(KBUILD_AFLAGS) sets -g, which causes gcc to pass a suitable -g<format>
+# option to the assembler.
+KBUILD_AFLAGS	+= -g
 
-LIBS-y += lib/libgeneric.o
-LIBS-y += lib/rsa/librsa.o
-LIBS-y += lib/lzma/liblzma.o
-LIBS-y += lib/lzo/liblzo.o
-LIBS-y += lib/zlib/libz.o
-LIBS-$(CONFIG_TIZEN) += lib/tizen/libtizen.o
-LIBS-$(HAVE_VENDOR_COMMON_LIB) += board/$(VENDOR)/common/lib$(VENDOR).o
-LIBS-y += $(CPUDIR)/lib$(CPU).o
-ifdef SOC
-LIBS-y += $(CPUDIR)/$(SOC)/lib$(SOC).o
-endif
-ifeq ($(CPU),ixp)
-LIBS-y += drivers/net/npe/libnpe.o
-endif
-LIBS-$(CONFIG_OF_EMBED) += dts/libdts.o
-LIBS-y += arch/$(ARCH)/lib/lib$(ARCH).o
-LIBS-y += fs/libfs.o \
-	fs/cbfs/libcbfs.o \
-	fs/cramfs/libcramfs.o \
-	fs/ext4/libext4fs.o \
-	fs/fat/libfat.o \
-	fs/fdos/libfdos.o \
-	fs/jffs2/libjffs2.o \
-	fs/reiserfs/libreiserfs.o \
-	fs/sandbox/libsandboxfs.o \
-	fs/ubifs/libubifs.o \
-	fs/yaffs2/libyaffs2.o \
-	fs/zfs/libzfs.o
-LIBS-y += net/libnet.o
-LIBS-y += disk/libdisk.o
-LIBS-y += drivers/bios_emulator/libatibiosemu.o
-LIBS-y += drivers/block/libblock.o
-LIBS-$(CONFIG_BOOTCOUNT_LIMIT) += drivers/bootcount/libbootcount.o
-LIBS-y += drivers/crypto/libcrypto.o
-LIBS-y += drivers/dma/libdma.o
-LIBS-y += drivers/fpga/libfpga.o
-LIBS-y += drivers/gpio/libgpio.o
-LIBS-y += drivers/hwmon/libhwmon.o
-LIBS-y += drivers/i2c/libi2c.o
-LIBS-y += drivers/input/libinput.o
-LIBS-y += drivers/misc/libmisc.o
-LIBS-y += drivers/mmc/libmmc.o
-LIBS-y += drivers/mtd/libmtd.o
-LIBS-y += drivers/mtd/nand/libnand.o
-LIBS-y += drivers/mtd/onenand/libonenand.o
-LIBS-y += drivers/mtd/ubi/libubi.o
-LIBS-y += drivers/mtd/spi/libspi_flash.o
-LIBS-y += drivers/net/libnet.o
-LIBS-y += drivers/net/phy/libphy.o
-LIBS-y += drivers/pci/libpci.o
-LIBS-y += drivers/pcmcia/libpcmcia.o
-LIBS-y += drivers/power/libpower.o \
-	drivers/power/fuel_gauge/libfuel_gauge.o \
-	drivers/power/mfd/libmfd.o \
-	drivers/power/pmic/libpmic.o \
-	drivers/power/battery/libbattery.o
-LIBS-y += drivers/spi/libspi.o
-LIBS-y += drivers/dfu/libdfu.o
-ifeq ($(CPU),mpc83xx)
-LIBS-y += drivers/qe/libqe.o
-LIBS-y += arch/powerpc/cpu/mpc8xxx/ddr/libddr.o
-LIBS-y += arch/powerpc/cpu/mpc8xxx/lib8xxx.o
-endif
-ifeq ($(CPU),mpc85xx)
-LIBS-y += drivers/qe/libqe.o
-LIBS-y += drivers/net/fm/libfm.o
-LIBS-y += arch/powerpc/cpu/mpc8xxx/ddr/libddr.o
-LIBS-y += arch/powerpc/cpu/mpc8xxx/lib8xxx.o
-endif
-ifeq ($(CPU),mpc86xx)
-LIBS-y += arch/powerpc/cpu/mpc8xxx/ddr/libddr.o
-LIBS-y += arch/powerpc/cpu/mpc8xxx/lib8xxx.o
-endif
-LIBS-y += drivers/rtc/librtc.o
-LIBS-y += drivers/serial/libserial.o
-LIBS-y += drivers/sound/libsound.o
-LIBS-y += drivers/tpm/libtpm.o
-LIBS-y += drivers/twserial/libtws.o
-LIBS-y += drivers/usb/eth/libusb_eth.o
-LIBS-y += drivers/usb/gadget/libusb_gadget.o
-LIBS-y += drivers/usb/host/libusb_host.o
-LIBS-y += drivers/usb/musb/libusb_musb.o
-LIBS-y += drivers/usb/musb-new/libusb_musb-new.o
-LIBS-y += drivers/usb/phy/libusb_phy.o
-LIBS-y += drivers/usb/ulpi/libusb_ulpi.o
-LIBS-y += drivers/video/libvideo.o
-LIBS-y += drivers/watchdog/libwatchdog.o
-LIBS-y += common/libcommon.o
-LIBS-y += lib/libfdt/libfdt.o
-LIBS-y += api/libapi.o
-LIBS-y += post/libpost.o
-LIBS-y += test/libtest.o
-
-ifneq ($(CONFIG_OMAP_COMMON),)
-LIBS-y += $(CPUDIR)/omap-common/libomap-common.o
+# Report stack usage if supported
+ifeq ($(shell $(CONFIG_SHELL) $(srctree)/scripts/gcc-stack-usage.sh $(CC)),y)
+	KBUILD_CFLAGS += -fstack-usage
 endif
 
-ifneq (,$(filter $(SOC), mx25 mx27 mx5 mx6 mx31 mx35 mxs vf610))
-LIBS-y += arch/$(ARCH)/imx-common/libimx-common.o
+KBUILD_CFLAGS += $(call cc-option,-Wno-format-nonliteral)
+
+# turn jbsr into jsr for m68k
+ifeq ($(ARCH),m68k)
+ifeq ($(findstring 3.4,$(shell $(CC) --version)),3.4)
+KBUILD_AFLAGS += -Wa,-gstabs,-S
+endif
 endif
 
-ifeq ($(SOC),s5pc1xx)
-LIBS-y += $(CPUDIR)/s5p-common/libs5p-common.o
+ifneq ($(CONFIG_SYS_TEXT_BASE),)
+KBUILD_CPPFLAGS += -DCONFIG_SYS_TEXT_BASE=$(CONFIG_SYS_TEXT_BASE)
 endif
-ifeq ($(SOC),exynos)
-LIBS-y += $(CPUDIR)/s5p-common/libs5p-common.o
+
+export CONFIG_SYS_TEXT_BASE
+
+# Use UBOOTINCLUDE when you must reference the include/ directory.
+# Needed to be compatible with the O= option
+UBOOTINCLUDE    := \
+		-Iinclude \
+		$(if $(KBUILD_SRC), -I$(srctree)/include) \
+		-I$(srctree)/arch/$(ARCH)/include
+
+NOSTDINC_FLAGS += -nostdinc -isystem $(shell $(CC) -print-file-name=include)
+CHECKFLAGS     += $(NOSTDINC_FLAGS)
+
+# FIX ME
+cpp_flags := $(KBUILD_CPPFLAGS) $(PLATFORM_CPPFLAGS) $(UBOOTINCLUDE) \
+							$(NOSTDINC_FLAGS)
+c_flags := $(KBUILD_CFLAGS) $(cpp_flags)
+
+#########################################################################
+# U-Boot objects....order is important (i.e. start must be first)
+
+head-y := $(CPUDIR)/start.o
+head-$(CONFIG_4xx) += arch/powerpc/cpu/ppc4xx/resetvec.o
+head-$(CONFIG_MPC85xx) += arch/powerpc/cpu/mpc85xx/resetvec.o
+
+HAVE_VENDOR_COMMON_LIB = $(if $(wildcard $(srctree)/board/$(VENDOR)/common/Makefile),y,n)
+
+libs-y += lib/
+libs-$(HAVE_VENDOR_COMMON_LIB) += board/$(VENDOR)/common/
+libs-y += $(CPUDIR)/
+ifdef SOC
+libs-y += $(CPUDIR)/$(SOC)/
 endif
-ifneq ($(CONFIG_TEGRA),)
-LIBS-y += arch/$(ARCH)/cpu/$(SOC)-common/lib$(SOC)-common.o
-LIBS-y += arch/$(ARCH)/cpu/tegra-common/libcputegra-common.o
-LIBS-y += $(CPUDIR)/tegra-common/libtegra-common.o
+libs-$(CONFIG_OF_EMBED) += dts/
+libs-y += arch/$(ARCH)/lib/
+libs-y += fs/
+libs-y += net/
+libs-y += disk/
+libs-y += drivers/
+libs-$(CONFIG_DM) += drivers/core/
+libs-y += drivers/dma/
+libs-y += drivers/gpio/
+libs-y += drivers/i2c/
+libs-y += drivers/input/
+libs-y += drivers/mmc/
+libs-y += drivers/mtd/
+libs-$(CONFIG_CMD_NAND) += drivers/mtd/nand/
+libs-y += drivers/mtd/onenand/
+libs-$(CONFIG_CMD_UBI) += drivers/mtd/ubi/
+libs-y += drivers/mtd/spi/
+libs-y += drivers/net/
+libs-y += drivers/net/phy/
+libs-y += drivers/pci/
+libs-y += drivers/power/ \
+	drivers/power/fuel_gauge/ \
+	drivers/power/mfd/ \
+	drivers/power/pmic/ \
+	drivers/power/battery/
+libs-y += drivers/spi/
+libs-$(CONFIG_FMAN_ENET) += drivers/net/fm/
+libs-$(CONFIG_SYS_FSL_DDR) += drivers/ddr/fsl/
+libs-y += drivers/serial/
+libs-y += drivers/usb/eth/
+libs-y += drivers/usb/gadget/
+libs-y += drivers/usb/host/
+libs-y += drivers/usb/musb/
+libs-y += drivers/usb/musb-new/
+libs-y += drivers/usb/phy/
+libs-y += drivers/usb/ulpi/
+libs-y += common/
+libs-y += lib/libfdt/
+libs-$(CONFIG_API) += api/
+libs-$(CONFIG_HAS_POST) += post/
+libs-y += test/
+libs-y += test/dm/
+libs-$(CONFIG_DM_DEMO) += drivers/demo/
+
+ifneq (,$(filter $(SOC), mx25 mx27 mx5 mx6 mx31 mx35 mxs vf610))
+libs-y += arch/$(ARCH)/imx-common/
 endif
 
-LIBS := $(addprefix $(obj),$(sort $(LIBS-y)))
-.PHONY : $(LIBS)
+libs-$(CONFIG_ARM) += arch/arm/cpu/
+libs-$(CONFIG_PPC) += arch/powerpc/cpu/
+
+libs-y += $(if $(BOARDDIR),board/$(BOARDDIR)/)
+
+libs-y := $(sort $(libs-y))
+
+u-boot-dirs	:= $(patsubst %/,%,$(filter %/, $(libs-y))) tools examples
+
+u-boot-alldirs	:= $(sort $(u-boot-dirs) $(patsubst %/,%,$(filter %/, $(libs-))))
+
+libs-y		:= $(patsubst %/, %/built-in.o, $(libs-y))
+
+u-boot-init := $(head-y)
+u-boot-main := $(libs-y)
 
-LIBBOARD = board/$(BOARDDIR)/lib$(BOARD).o
-LIBBOARD := $(addprefix $(obj),$(LIBBOARD))
 
 # Add GCC lib
-ifdef USE_PRIVATE_LIBGCC
-ifeq ("$(USE_PRIVATE_LIBGCC)", "yes")
-PLATFORM_LIBGCC = $(OBJTREE)/arch/$(ARCH)/lib/libgcc.o
+ifdef CONFIG_USE_PRIVATE_LIBGCC
+ifeq ($(CONFIG_USE_PRIVATE_LIBGCC),y)
+PLATFORM_LIBGCC = arch/$(ARCH)/lib/lib.a
 else
-PLATFORM_LIBGCC = -L $(USE_PRIVATE_LIBGCC) -lgcc
+PLATFORM_LIBGCC = -L $(CONFIG_USE_PRIVATE_LIBGCC) -lgcc
 endif
 else
-PLATFORM_LIBGCC := -L $(shell dirname `$(CC) $(CFLAGS) -print-libgcc-file-name`) -lgcc
+PLATFORM_LIBGCC := -L $(shell dirname `$(CC) $(c_flags) -print-libgcc-file-name`) -lgcc
 endif
 PLATFORM_LIBS += $(PLATFORM_LIBGCC)
 export PLATFORM_LIBS
@@ -367,14 +660,11 @@ export PLATFORM_LIBS
 # Pass the version down so we can handle backwards compatibility
 # on the fly.
 LDPPFLAGS += \
-	-include $(TOPDIR)/include/u-boot/u-boot.lds.h \
+	-include $(srctree)/include/u-boot/u-boot.lds.h \
 	-DCPUDIR=$(CPUDIR) \
 	$(shell $(LD) --version | \
 	  sed -ne 's/GNU ld version \([0-9][0-9]*\)\.\([0-9][0-9]*\).*/-DLD_MAJOR=\1 -DLD_MINOR=\2/p')
 
-__OBJS := $(subst $(obj),,$(OBJS))
-__LIBS := $(subst $(obj),,$(LIBS)) $(subst $(obj),,$(LIBBOARD))
-
 #########################################################################
 #########################################################################
 
@@ -393,57 +683,110 @@ else
 BOARD_SIZE_CHECK =
 endif
 
+# Statically apply RELA-style relocations (currently arm64 only)
+ifneq ($(CONFIG_STATIC_RELA),)
+# $(1) is u-boot ELF, $(2) is u-boot bin, $(3) is text base
+DO_STATIC_RELA = \
+	start=$$($(NM) $(1) | grep __rel_dyn_start | cut -f 1 -d ' '); \
+	end=$$($(NM) $(1) | grep __rel_dyn_end | cut -f 1 -d ' '); \
+	tools/relocate-rela $(2) $(3) $$start $$end
+else
+DO_STATIC_RELA =
+endif
+
 # Always append ALL so that arch config.mk's can add custom ones
-ALL-y += $(obj)u-boot.srec $(obj)u-boot.bin $(obj)System.map
-
-ALL-$(CONFIG_NAND_U_BOOT) += $(obj)u-boot-nand.bin
-ALL-$(CONFIG_ONENAND_U_BOOT) += $(obj)u-boot-onenand.bin
-ALL-$(CONFIG_SPL) += $(obj)spl/u-boot-spl.bin
-ALL-$(CONFIG_SPL_FRAMEWORK) += $(obj)u-boot.img
-ALL-$(CONFIG_TPL) += $(obj)tpl/u-boot-tpl.bin
-ALL-$(CONFIG_OF_SEPARATE) += $(obj)u-boot.dtb $(obj)u-boot-dtb.bin
+ALL-y += u-boot.srec u-boot.bin System.map
+
+ALL-$(CONFIG_NAND_U_BOOT) += u-boot-nand.bin
+ALL-$(CONFIG_ONENAND_U_BOOT) += u-boot-onenand.bin
+ALL-$(CONFIG_RAMBOOT_PBL) += u-boot.pbl
+ALL-$(CONFIG_SPL) += spl/u-boot-spl.bin
+ALL-$(CONFIG_SPL_FRAMEWORK) += u-boot.img
+ALL-$(CONFIG_TPL) += tpl/u-boot-tpl.bin
+ALL-$(CONFIG_OF_SEPARATE) += u-boot.dtb u-boot-dtb.bin
+ALL-$(CONFIG_OF_HOSTFILE) += u-boot.dtb
 ifneq ($(CONFIG_SPL_TARGET),)
-ALL-$(CONFIG_SPL) += $(obj)$(subst ",,$(CONFIG_SPL_TARGET))
+ALL-$(CONFIG_SPL) += $(CONFIG_SPL_TARGET:"%"=%)
 endif
+ALL-$(CONFIG_REMAKE_ELF) += u-boot.elf
 
 # enable combined SPL/u-boot/dtb rules for tegra
 ifneq ($(CONFIG_TEGRA),)
+ifeq ($(CONFIG_SPL),y)
 ifeq ($(CONFIG_OF_SEPARATE),y)
-ALL-y += $(obj)u-boot-dtb-tegra.bin
+ALL-y += u-boot-dtb-tegra.bin
 else
-ALL-y += $(obj)u-boot-nodtb-tegra.bin
+ALL-y += u-boot-nodtb-tegra.bin
+endif
+endif
 endif
+
+LDFLAGS_u-boot += $(LDFLAGS_FINAL)
+ifneq ($(CONFIG_SYS_TEXT_BASE),)
+LDFLAGS_u-boot += -Ttext $(CONFIG_SYS_TEXT_BASE)
 endif
 
-all:		$(ALL-y) $(SUBDIR_EXAMPLES)
+quiet_cmd_objcopy = OBJCOPY $@
+cmd_objcopy = $(OBJCOPY) $(OBJCOPYFLAGS) $(OBJCOPYFLAGS_$(@F)) $< $@
 
-$(obj)u-boot.dtb:	checkdtc $(obj)u-boot
-		$(MAKE) -C dts binary
-		mv $(obj)dts/dt.dtb $@
+quiet_cmd_mkimage = MKIMAGE $@
+cmd_mkimage = $(objtree)/tools/mkimage $(MKIMAGEFLAGS_$(@F)) -d $< $@ \
+	$(if $(KBUILD_VERBOSE:1=), >/dev/null)
 
-$(obj)u-boot-dtb.bin:	$(obj)u-boot.bin $(obj)u-boot.dtb
-		cat $^ >$@
+quiet_cmd_cat = CAT     $@
+cmd_cat = cat $(filter-out $(PHONY), $^) > $@
 
-$(obj)u-boot.hex:	$(obj)u-boot
-		$(OBJCOPY) ${OBJCFLAGS} -O ihex $< $@
+append = cat $(filter-out $< $(PHONY), $^) >> $@
 
-$(obj)u-boot.srec:	$(obj)u-boot
-		$(OBJCOPY) -O srec $< $@
+quiet_cmd_pad_cat = CAT     $@
+cmd_pad_cat = $(cmd_objcopy) && $(append) || rm -f $@
 
-$(obj)u-boot.bin:	$(obj)u-boot
-		$(OBJCOPY) ${OBJCFLAGS} -O binary $< $@
-		$(BOARD_SIZE_CHECK)
+all:		$(ALL-y)
+
+PHONY += dtbs
+dtbs dts/dt.dtb: checkdtc u-boot
+	$(Q)$(MAKE) $(build)=dts dtbs
+
+u-boot-dtb.bin: u-boot.bin dts/dt.dtb FORCE
+	$(call if_changed,cat)
+
+%.imx: %.bin
+	$(Q)$(MAKE) $(build)=arch/arm/imx-common $@
+
+u-boot-nand.imx: u-boot.bin
+	$(Q)$(MAKE) $(build)=arch/arm/imx-common $@
+
+quiet_cmd_copy = COPY    $@
+      cmd_copy = cp $< $@
 
-$(obj)u-boot.ldr:	$(obj)u-boot
+u-boot.dtb: dts/dt.dtb
+	$(call cmd,copy)
+
+OBJCOPYFLAGS_u-boot.hex := -O ihex
+
+OBJCOPYFLAGS_u-boot.srec := -O srec
+
+u-boot.hex u-boot.srec: u-boot FORCE
+	$(call if_changed,objcopy)
+
+OBJCOPYFLAGS_u-boot.bin := -O binary
+
+u-boot.bin: u-boot FORCE
+	$(call if_changed,objcopy)
+	$(call DO_STATIC_RELA,$<,$@,$(CONFIG_SYS_TEXT_BASE))
+	$(BOARD_SIZE_CHECK)
+
+u-boot.ldr:	u-boot
 		$(CREATE_LDR_ENV)
 		$(LDR) -T $(CONFIG_BFIN_CPU) -c $@ $< $(LDR_FLAGS)
 		$(BOARD_SIZE_CHECK)
 
-$(obj)u-boot.ldr.hex:	$(obj)u-boot.ldr
-		$(OBJCOPY) ${OBJCFLAGS} -O ihex $< $@ -I binary
+OBJCOPYFLAGS_u-boot.ldr.hex := -I binary -O ihex
+
+OBJCOPYFLAGS_u-boot.ldr.srec := -I binary -O srec
 
-$(obj)u-boot.ldr.srec:	$(obj)u-boot.ldr
-		$(OBJCOPY) ${OBJCFLAGS} -O srec $< $@ -I binary
+u-boot.ldr.hex u-boot.ldr.srec: u-boot.ldr FORCE
+	$(call if_changed,objcopy)
 
 #
 # U-Boot entry point, needed for booting of full-blown U-Boot
@@ -453,79 +796,66 @@ ifndef CONFIG_SYS_UBOOT_START
 CONFIG_SYS_UBOOT_START := 0
 endif
 
-$(obj)u-boot.img:	$(obj)u-boot.bin
-		$(obj)tools/mkimage -A $(ARCH) -T firmware -C none \
-		-O u-boot -a $(CONFIG_SYS_TEXT_BASE) \
-		-e $(CONFIG_SYS_UBOOT_START) \
-		-n $(shell sed -n -e 's/.*U_BOOT_VERSION//p' $(VERSION_FILE) | \
-			sed -e 's/"[	 ]*$$/ for $(BOARD) board"/') \
-		-d $< $@
+MKIMAGEFLAGS_u-boot.img = -A $(ARCH) -T firmware -C none -O u-boot \
+	-a $(CONFIG_SYS_TEXT_BASE) -e $(CONFIG_SYS_UBOOT_START) \
+	-n "U-Boot $(UBOOTRELEASE) for $(BOARD) board"
 
-$(obj)u-boot.imx: $(obj)u-boot.bin depend
-		$(MAKE) -C $(SRCTREE)/arch/arm/imx-common $(OBJTREE)/u-boot.imx
+MKIMAGEFLAGS_u-boot.kwb = -n $(srctree)/$(CONFIG_SYS_KWD_CONFIG:"%"=%) \
+	-T kwbimage -a $(CONFIG_SYS_TEXT_BASE) -e $(CONFIG_SYS_TEXT_BASE)
 
-$(obj)u-boot.kwb:       $(obj)u-boot.bin
-		$(obj)tools/mkimage -n $(CONFIG_SYS_KWD_CONFIG) -T kwbimage \
-		-a $(CONFIG_SYS_TEXT_BASE) -e $(CONFIG_SYS_TEXT_BASE) -d $< $@
+MKIMAGEFLAGS_u-boot.pbl = -n $(srctree)/$(CONFIG_SYS_FSL_PBL_RCW:"%"=%) \
+		-R $(srctree)/$(CONFIG_SYS_FSL_PBL_PBI:"%"=%) -T pblimage
 
-$(obj)u-boot.pbl:	$(obj)u-boot.bin
-		$(obj)tools/mkimage -n $(CONFIG_PBLRCW_CONFIG) \
-		-R $(CONFIG_PBLPBI_CONFIG) -T pblimage \
-		-d $< $@
+u-boot.img u-boot.kwb u-boot.pbl: u-boot.bin FORCE
+	$(call if_changed,mkimage)
 
-$(obj)u-boot.sha1:	$(obj)u-boot.bin
-		$(obj)tools/ubsha1 $(obj)u-boot.bin
+u-boot.sha1:	u-boot.bin
+		tools/ubsha1 u-boot.bin
 
-$(obj)u-boot.dis:	$(obj)u-boot
+u-boot.dis:	u-boot
 		$(OBJDUMP) -d $< > $@
 
-# $@ is output, $(1) and $(2) are inputs, $(3) is padded intermediate,
-# $(4) is pad-to
-SPL_PAD_APPEND = \
-		$(OBJCOPY) ${OBJCFLAGS} --pad-to=$(4) -I binary -O binary \
-		$(1) $(obj)$(3); \
-		cat $(obj)$(3) $(2) > $@; \
-		rm $(obj)$(3)
-
 ifdef CONFIG_TPL
-SPL_PAYLOAD := $(obj)tpl/u-boot-with-tpl.bin
+SPL_PAYLOAD := tpl/u-boot-with-tpl.bin
 else
-SPL_PAYLOAD := $(obj)u-boot.bin
+SPL_PAYLOAD := u-boot.bin
 endif
 
-$(obj)u-boot-with-spl.bin: $(obj)spl/u-boot-spl.bin $(SPL_PAYLOAD)
-		$(call SPL_PAD_APPEND,$<,$(SPL_PAYLOAD),spl/u-boot-spl-pad.bin,$(CONFIG_SPL_PAD_TO))
+OBJCOPYFLAGS_u-boot-with-spl.bin = -I binary -O binary \
+				   --pad-to=$(CONFIG_SPL_PAD_TO)
+u-boot-with-spl.bin: spl/u-boot-spl.bin $(SPL_PAYLOAD) FORCE
+	$(call if_changed,pad_cat)
+
+OBJCOPYFLAGS_u-boot-with-tpl.bin = -I binary -O binary \
+				   --pad-to=$(CONFIG_TPL_PAD_TO)
+tpl/u-boot-with-tpl.bin: tpl/u-boot-tpl.bin u-boot.bin FORCE
+	$(call if_changed,pad_cat)
 
-$(obj)tpl/u-boot-with-tpl.bin: $(obj)tpl/u-boot-tpl.bin $(obj)u-boot.bin
-		$(call SPL_PAD_APPEND,$<,$(obj)u-boot.bin,tpl/u-boot-tpl-pad.bin,$(CONFIG_TPL_PAD_TO))
+SPL: spl/u-boot-spl.bin FORCE
+	$(Q)$(MAKE) $(build)=arch/arm/imx-common $@
 
-$(obj)u-boot-with-spl.imx: $(obj)spl/u-boot-spl.bin $(obj)u-boot.bin
-		$(MAKE) -C $(SRCTREE)/arch/arm/imx-common \
-			$(OBJTREE)/u-boot-with-spl.imx
+u-boot-with-spl.imx u-boot-with-nand-spl.imx: SPL u-boot.bin FORCE
+	$(Q)$(MAKE) $(build)=arch/arm/imx-common $@
 
-$(obj)u-boot-with-nand-spl.imx: $(obj)spl/u-boot-spl.bin $(obj)u-boot.bin
-		$(MAKE) -C $(SRCTREE)/arch/arm/imx-common \
-			$(OBJTREE)/u-boot-with-nand-spl.imx
+MKIMAGEFLAGS_u-boot.ubl = -n $(UBL_CONFIG) -T ublimage -e $(CONFIG_SYS_TEXT_BASE)
 
-$(obj)u-boot.ubl:       $(obj)u-boot-with-spl.bin
-		$(obj)tools/mkimage -n $(UBL_CONFIG) -T ublimage \
-		-e $(CONFIG_SYS_TEXT_BASE) -d $< $(obj)u-boot.ubl
+u-boot.ubl: u-boot-with-spl.bin FORCE
+	$(call if_changed,mkimage)
 
-$(obj)u-boot.ais:       $(obj)spl/u-boot-spl.bin $(obj)u-boot.img
-		$(obj)tools/mkimage -s -n $(if $(CONFIG_AIS_CONFIG_FILE),$(CONFIG_AIS_CONFIG_FILE),"/dev/null") \
-			-T aisimage \
-			-e $(CONFIG_SPL_TEXT_BASE) \
-			-d $(obj)spl/u-boot-spl.bin \
-			$(obj)spl/u-boot-spl.ais
-		$(OBJCOPY) ${OBJCFLAGS} -I binary \
-			--pad-to=$(CONFIG_SPL_MAX_SIZE) -O binary \
-			$(obj)spl/u-boot-spl.ais $(obj)spl/u-boot-spl-pad.ais
-		cat $(obj)spl/u-boot-spl-pad.ais $(obj)u-boot.img > \
-			$(obj)u-boot.ais
+MKIMAGEFLAGS_u-boot-spl.ais = -s -n $(if $(CONFIG_AIS_CONFIG_FILE), \
+	$(srctree)/$(CONFIG_AIS_CONFIG_FILE:"%"=%),"/dev/null") \
+	-T aisimage -e $(CONFIG_SPL_TEXT_BASE)
+spl/u-boot-spl.ais: spl/u-boot-spl.bin FORCE
+	$(call if_changed,mkimage)
 
+OBJCOPYFLAGS_u-boot.ais = -I binary -O binary --pad-to=$(CONFIG_SPL_MAX_SIZE)
+u-boot.ais: spl/u-boot-spl.ais u-boot.img FORCE
+	$(call if_changed,pad_cat)
 
-$(obj)u-boot.sb:       $(obj)u-boot.bin $(obj)spl/u-boot-spl.bin
-		$(MAKE) -C $(SRCTREE)/$(CPUDIR)/$(SOC)/ $(OBJTREE)/u-boot.sb
+u-boot-signed.sb: u-boot.bin spl/u-boot-spl.bin
+	$(Q)$(MAKE) $(build)=arch/arm/cpu/arm926ejs/mxs u-boot-signed.sb
+u-boot.sb: u-boot.bin spl/u-boot-spl.bin
+	$(Q)$(MAKE) $(build)=arch/arm/cpu/arm926ejs/mxs u-boot.sb
 
 # On x600 (SPEAr600) U-Boot is appended to U-Boot SPL.
 # Both images are created using mkimage (crc etc), so that the ROM
@@ -533,127 +863,237 @@ $(obj)u-boot.sb:       $(obj)u-boot.bin $(obj)spl/u-boot-spl.bin
 # SPL image (with mkimage header) and not the binary. Otherwise the resulting image
 # which is loaded/copied by the ROM bootloader to SRAM doesn't fit.
 # The resulting image containing both U-Boot images is called u-boot.spr
-$(obj)u-boot.spr:	$(obj)u-boot.img $(obj)spl/u-boot-spl.bin
-		$(obj)tools/mkimage -A $(ARCH) -T firmware -C none \
-		-a $(CONFIG_SPL_TEXT_BASE) -e $(CONFIG_SPL_TEXT_BASE) -n XLOADER \
-		-d $(obj)spl/u-boot-spl.bin $(obj)spl/u-boot-spl.img
-		tr "\000" "\377" < /dev/zero | dd ibs=1 count=$(CONFIG_SPL_PAD_TO) \
-			of=$(obj)spl/u-boot-spl-pad.img 2>/dev/null
-		dd if=$(obj)spl/u-boot-spl.img of=$(obj)spl/u-boot-spl-pad.img \
-			conv=notrunc 2>/dev/null
-		cat $(obj)spl/u-boot-spl-pad.img $(obj)u-boot.img > $@
+MKIMAGEFLAGS_u-boot-spl.img = -A $(ARCH) -T firmware -C none \
+	-a $(CONFIG_SPL_TEXT_BASE) -e $(CONFIG_SPL_TEXT_BASE) -n XLOADER
+spl/u-boot-spl.img: spl/u-boot-spl.bin FORCE
+	$(call if_changed,mkimage)
+
+OBJCOPYFLAGS_u-boot.spr = -I binary -O binary --pad-to=$(CONFIG_SPL_PAD_TO) \
+			  --gap-fill=0xff
+u-boot.spr: spl/u-boot-spl.img u-boot.img FORCE
+	$(call if_changed,pad_cat)
 
 ifneq ($(CONFIG_TEGRA),)
-$(obj)u-boot-nodtb-tegra.bin: $(obj)spl/u-boot-spl.bin $(obj)u-boot.bin
-		$(OBJCOPY) ${OBJCFLAGS} --pad-to=$(CONFIG_SYS_TEXT_BASE) -O binary $(obj)spl/u-boot-spl $(obj)spl/u-boot-spl-pad.bin
-		cat $(obj)spl/u-boot-spl-pad.bin $(obj)u-boot.bin > $@
-		rm $(obj)spl/u-boot-spl-pad.bin
+OBJCOPYFLAGS_u-boot-nodtb-tegra.bin = -O binary --pad-to=$(CONFIG_SYS_TEXT_BASE)
+u-boot-nodtb-tegra.bin: spl/u-boot-spl u-boot.bin FORCE
+	$(call if_changed,pad_cat)
 
 ifeq ($(CONFIG_OF_SEPARATE),y)
-$(obj)u-boot-dtb-tegra.bin: $(obj)u-boot-nodtb-tegra.bin $(obj)u-boot.dtb
-		cat $(obj)u-boot-nodtb-tegra.bin $(obj)u-boot.dtb > $@
+u-boot-dtb-tegra.bin: u-boot-nodtb-tegra.bin dts/dt.dtb FORCE
+	$(call if_changed,cat)
 endif
 endif
 
-$(obj)u-boot-img.bin: $(obj)spl/u-boot-spl.bin $(obj)u-boot.img
-		cat $(obj)spl/u-boot-spl.bin $(obj)u-boot.img > $@
+u-boot-img.bin: spl/u-boot-spl.bin u-boot.img FORCE
+	$(call if_changed,cat)
 
 # PPC4xx needs the SPL at the end of the image, since the reset vector
 # is located at 0xfffffffc. So we can't use the "u-boot-img.bin" target
 # and need to introduce a new build target with the full blown U-Boot
 # at the start padded up to the start of the SPL image. And then concat
 # the SPL image to the end.
-$(obj)u-boot-img-spl-at-end.bin: $(obj)spl/u-boot-spl.bin $(obj)u-boot.img
-		tr "\000" "\377" < /dev/zero | dd ibs=1 count=$(CONFIG_UBOOT_PAD_TO) \
-			of=$(obj)u-boot-pad.img 2>/dev/null
-		dd if=$(obj)u-boot.img of=$(obj)u-boot-pad.img \
-			conv=notrunc 2>/dev/null
-		cat $(obj)u-boot-pad.img $(obj)spl/u-boot-spl.bin > $@
-
-ifeq ($(CONFIG_SANDBOX),y)
-GEN_UBOOT = \
-		cd $(LNDIR) && $(CC) $(SYMS) -T $(obj)u-boot.lds \
-			-Wl,--start-group $(__LIBS) -Wl,--end-group \
-			$(PLATFORM_LIBS) -Wl,-Map -Wl,u-boot.map -o u-boot
-else
-GEN_UBOOT = \
-		cd $(LNDIR) && $(LD) $(LDFLAGS) $(LDFLAGS_$(@F)) \
-			$(__OBJS) \
-			--start-group $(__LIBS) --end-group $(PLATFORM_LIBS) \
-			-Map u-boot.map -o u-boot
-endif
 
-$(obj)u-boot:	depend \
-		$(SUBDIR_TOOLS) $(OBJS) $(LIBBOARD) $(LIBS) $(LDSCRIPT) $(obj)u-boot.lds
-		$(GEN_UBOOT)
+OBJCOPYFLAGS_u-boot-img-spl-at-end.bin := -I binary -O binary \
+	--pad-to=$(CONFIG_UBOOT_PAD_TO) --gap-fill=0xff
+u-boot-img-spl-at-end.bin: u-boot.img spl/u-boot-spl.bin FORCE
+	$(call if_changed,pad_cat)
+
+# Create a new ELF from a raw binary file.  This is useful for arm64
+# where static relocation needs to be performed on the raw binary,
+# but certain simulators only accept an ELF file (but don't do the
+# relocation).
+# FIXME refactor dts/Makefile to share target/arch detection
+u-boot.elf: u-boot.bin
+	@$(OBJCOPY)  -B aarch64 -I binary -O elf64-littleaarch64 \
+		$< u-boot-elf.o
+	@$(LD) u-boot-elf.o -o $@ \
+		--defsym=_start=$(CONFIG_SYS_TEXT_BASE) \
+		-Ttext=$(CONFIG_SYS_TEXT_BASE)
+
+# Rule to link u-boot
+# May be overridden by arch/$(ARCH)/config.mk
+quiet_cmd_u-boot__ ?= LD      $@
+      cmd_u-boot__ ?= $(LD) $(LDFLAGS) $(LDFLAGS_u-boot) -o $@ \
+      -T u-boot.lds $(u-boot-init)                             \
+      --start-group $(u-boot-main) --end-group                 \
+      $(PLATFORM_LIBS) -Map u-boot.map
+
+u-boot:	$(u-boot-init) $(u-boot-main) u-boot.lds
+	$(call if_changed,u-boot__)
 ifeq ($(CONFIG_KALLSYMS),y)
-		smap=`$(call SYSTEM_MAP,$(obj)u-boot) | \
-			awk '$$2 ~ /[tTwW]/ {printf $$1 $$3 "\\\\000"}'` ; \
-		$(CC) $(CFLAGS) -DSYSTEM_MAP="\"$${smap}\"" \
-			-c common/system_map.c -o $(obj)common/system_map.o
-		$(GEN_UBOOT) $(obj)common/system_map.o
+	smap=`$(call SYSTEM_MAP,u-boot) | \
+		awk '$$2 ~ /[tTwW]/ {printf $$1 $$3 "\\\\000"}'` ; \
+	$(CC) $(c_flags) -DSYSTEM_MAP="\"$${smap}\"" \
+		-c $(srctree)/common/system_map.c -o common/system_map.o
+	$(call cmd,u-boot__) common/system_map.o
+endif
+
+# The actual objects are generated when descending, 
+# make sure no implicit rule kicks in
+$(sort $(u-boot-init) $(u-boot-main)): $(u-boot-dirs) ;
+
+# Handle descending into subdirectories listed in $(vmlinux-dirs)
+# Preset locale variables to speed up the build process. Limit locale
+# tweaks to this spot to avoid wrong language settings when running
+# make menuconfig etc.
+# Error messages still appears in the original language
+
+PHONY += $(u-boot-dirs)
+$(u-boot-dirs): prepare scripts
+	$(Q)$(MAKE) $(build)=$@
+
+tools: prepare
+# The "tools" are needed early
+$(filter-out tools, $(u-boot-dirs)): tools
+# The "examples" conditionally depend on U-Boot (say, when USE_PRIVATE_LIBGCC
+# is "yes"), so compile examples after U-Boot is compiled.
+examples: $(filter-out examples, $(u-boot-dirs))
+
+define filechk_uboot.release
+	echo "$(UBOOTVERSION)$$($(CONFIG_SHELL) $(srctree)/scripts/setlocalversion $(srctree))"
+endef
+
+# Store (new) UBOOTRELEASE string in include/config/uboot.release
+include/config/uboot.release: Makefile FORCE
+	$(call filechk,uboot.release)
+
+
+# Things we need to do before we recursively start building the kernel
+# or the modules are listed in "prepare".
+# A multi level approach is used. prepareN is processed before prepareN-1.
+# archprepare is used in arch Makefiles and when processed asm symlink,
+# version.h and scripts_basic is processed / created.
+
+# Listed in dependency order
+PHONY += prepare archprepare prepare0 prepare1 prepare2 prepare3
+
+# prepare3 is used to check if we are building in a separate output directory,
+# and if so do:
+# 1) Check that make has not been executed in the kernel src $(srctree)
+prepare3: include/config/uboot.release
+ifneq ($(KBUILD_SRC),)
+	@$(kecho) '  Using $(srctree) as source for u-boot'
+	$(Q)if [ -f $(srctree)/include/config.mk ]; then \
+		echo >&2 "  $(srctree) is not clean, please run 'make mrproper'"; \
+		echo >&2 "  in the '$(srctree)' directory.";\
+		/bin/false; \
+	fi;
+endif
+
+# prepare2 creates a makefile if using a separate output directory
+prepare2: prepare3 outputmakefile
+
+prepare1: prepare2 $(version_h) $(timestamp_h)
+ifeq ($(__HAVE_ARCH_GENERIC_BOARD),)
+ifeq ($(CONFIG_SYS_GENERIC_BOARD),y)
+	@echo >&2 "  Your architecture does not support generic board."
+	@echo >&2 "  Please undefine CONFIG_SYS_GENERIC_BOARD in your board config file."
+	@/bin/false
+endif
 endif
+ifeq ($(wildcard $(LDSCRIPT)),)
+	@echo >&2 "  Could not find linker script."
+	@/bin/false
+endif
+
+archprepare: prepare1 scripts_basic
+
+prepare0: archprepare FORCE
+	$(Q)$(MAKE) $(build)=.
+
+# All the preparing..
+prepare: prepare0
+
+# Generate some files
+# ---------------------------------------------------------------------------
 
-$(OBJS):	depend
-		$(MAKE) -C $(CPUDIR) $(if $(REMOTE_BUILD),$@,$(notdir $@))
+define filechk_version.h
+	(echo \#define PLAIN_VERSION \"$(UBOOTRELEASE)\"; \
+	echo \#define U_BOOT_VERSION \"U-Boot \" PLAIN_VERSION; \
+	echo \#define CC_VERSION_STRING \"$$($(CC) --version | head -n 1)\"; \
+	echo \#define LD_VERSION_STRING \"$$($(LD) --version | head -n 1)\"; )
+endef
 
-$(LIBS):	depend $(SUBDIR_TOOLS)
-		$(MAKE) -C $(dir $(subst $(obj),,$@))
+define filechk_timestamp.h
+	(LC_ALL=C date +'#define U_BOOT_DATE "%b %d %C%y"'; \
+	LC_ALL=C date +'#define U_BOOT_TIME "%T"')
+endef
 
-$(LIBBOARD):	depend $(LIBS)
-		$(MAKE) -C $(dir $(subst $(obj),,$@))
+$(version_h): include/config/uboot.release FORCE
+	$(call filechk,version.h)
 
-$(SUBDIRS):	depend
-		$(MAKE) -C $@ all
+$(timestamp_h): $(srctree)/Makefile FORCE
+	$(call filechk,timestamp.h)
 
-$(SUBDIR_EXAMPLES): $(obj)u-boot
+#
+# Auto-generate the autoconf.mk file (which is included by all makefiles)
+#
+# This target actually generates 2 files; autoconf.mk and autoconf.mk.dep.
+# the dep file is only include in this top level makefile to determine when
+# to regenerate the autoconf.mk file.
+
+quiet_cmd_autoconf_dep = GEN     $@
+      cmd_autoconf_dep = $(CC) -x c -DDO_DEPS_ONLY -M $(c_flags) \
+	-MQ include/autoconf.mk $(srctree)/include/common.h > $@ || rm $@
+
+include/autoconf.mk.dep: include/config.h include/common.h
+	$(call cmd,autoconf_dep)
 
-$(LDSCRIPT):	depend
-		$(MAKE) -C $(dir $@) $(notdir $@)
+quiet_cmd_autoconf = GEN     $@
+      cmd_autoconf = \
+	$(CPP) $(c_flags) -DDO_DEPS_ONLY -dM $(srctree)/include/common.h > $@.tmp && \
+	sed -n -f $(srctree)/tools/scripts/define2mk.sed $@.tmp > $@; \
+	rm $@.tmp
 
-$(obj)u-boot.lds: $(LDSCRIPT)
-		$(CPP) $(CPPFLAGS) $(LDPPFLAGS) -ansi -D__ASSEMBLY__ -P - <$< >$@
+include/autoconf.mk: include/config.h
+	$(call cmd,autoconf)
 
-nand_spl:	$(TIMESTAMP_FILE) $(VERSION_FILE) depend
-		$(MAKE) -C nand_spl/board/$(BOARDDIR) all
+# ---------------------------------------------------------------------------
 
-$(obj)u-boot-nand.bin:	nand_spl $(obj)u-boot.bin
-		cat $(obj)nand_spl/u-boot-spl-16k.bin $(obj)u-boot.bin > $(obj)u-boot-nand.bin
+PHONY += depend dep
+depend dep:
+	@echo '*** Warning: make $@ is unnecessary now.'
 
-$(obj)spl/u-boot-spl.bin:	$(SUBDIR_TOOLS) depend
-		$(MAKE) -C spl all
+# ---------------------------------------------------------------------------
+quiet_cmd_cpp_lds = LDS     $@
+cmd_cpp_lds = $(CPP) -Wp,-MD,$(depfile) $(cpp_flags) $(LDPPFLAGS) -ansi \
+		-D__ASSEMBLY__ -x assembler-with-cpp -P -o $@ $<
 
-$(obj)tpl/u-boot-tpl.bin:	$(SUBDIR_TOOLS) depend
-		$(MAKE) -C spl all CONFIG_TPL_BUILD=y
+u-boot.lds: $(LDSCRIPT) prepare FORCE
+	$(call if_changed_dep,cpp_lds)
 
-updater:
-		$(MAKE) -C tools/updater all
+PHONY += nand_spl
+nand_spl: prepare
+	$(Q)$(MAKE) $(build)=nand_spl/board/$(BOARDDIR) all
+	@echo >&2
+	@echo >&2 "==================== WARNING ====================="
+	@echo >&2 "nand_spl will not be included in v2014.07 release."
+	@echo >&2 "Please switch over to SPL."
+	@echo >&2 "Otherwise, this board will be removed."
+	@echo >&2 "=================================================="
+	@echo >&2
 
-# Explicitly make _depend in subdirs containing multiple targets to prevent
-# parallel sub-makes creating .depend files simultaneously.
-depend dep:	$(TIMESTAMP_FILE) $(VERSION_FILE) \
-		$(obj)include/spl-autoconf.mk \
-		$(obj)include/tpl-autoconf.mk \
-		$(obj)include/autoconf.mk \
-		$(obj)include/generated/generic-asm-offsets.h \
-		$(obj)include/generated/asm-offsets.h
-		for dir in $(SUBDIRS) $(CPUDIR) $(LDSCRIPT_MAKEFILE_DIR) ; do \
-			$(MAKE) -C $$dir _depend ; done
+nand_spl/u-boot-spl-16k.bin: nand_spl
+	@:
 
-TAG_SUBDIRS = $(SUBDIRS)
-TAG_SUBDIRS += $(dir $(__LIBS))
-TAG_SUBDIRS += include
+u-boot-nand.bin: nand_spl/u-boot-spl-16k.bin u-boot.bin FORCE
+	$(call if_changed,cat)
+
+spl/u-boot-spl.bin: spl/u-boot-spl
+	@:
+spl/u-boot-spl: tools prepare
+	$(Q)$(MAKE) obj=spl -f $(srctree)/spl/Makefile all
+
+tpl/u-boot-tpl.bin: tools prepare
+	$(Q)$(MAKE) obj=tpl -f $(srctree)/spl/Makefile all CONFIG_TPL_BUILD=y
+
+TAG_SUBDIRS := $(u-boot-dirs) include
 
 FIND := find
 FINDFLAGS := -L
 
-checkstack:
-		$(CROSS_COMPILE)objdump -d $(obj)u-boot \
-			`$(FIND) $(obj) -name u-boot-spl -print` | \
-			perl $(src)tools/checkstack.pl $(ARCH)
-
 tags ctags:
-		ctags -w -o $(obj)ctags `$(FIND) $(FINDFLAGS) $(TAG_SUBDIRS) \
+		ctags -w -o ctags `$(FIND) $(FINDFLAGS) $(TAG_SUBDIRS) \
 						-name '*.[chS]' -print`
 
 etags:
@@ -668,25 +1108,8 @@ SYSTEM_MAP = \
 		$(NM) $1 | \
 		grep -v '\(compiled\)\|\(\.o$$\)\|\( [aUw] \)\|\(\.\.ng$$\)\|\(LASH[RL]DI\)' | \
 		LC_ALL=C sort
-$(obj)System.map:	$(obj)u-boot
-		@$(call SYSTEM_MAP,$<) > $(obj)System.map
-
-checkthumb:
-	@if test $(call cc-version) -lt 0404; then \
-		echo -n '*** Your GCC does not produce working '; \
-		echo 'binaries in THUMB mode.'; \
-		echo '*** Your board is configured for THUMB mode.'; \
-		false; \
-	fi
-
-# GCC 3.x is reported to have problems generating the type of relocation
-# that U-Boot wants.
-# See http://lists.denx.de/pipermail/u-boot/2012-September/135156.html
-checkgcc4:
-	@if test $(call cc-version) -lt 0400; then \
-		echo -n '*** Your GCC is too old, please upgrade to GCC 4.x or newer'; \
-		false; \
-	fi
+System.map:	u-boot
+		@$(call SYSTEM_MAP,$<) > $@
 
 checkdtc:
 	@if test $(call dtc-version) -lt 0104; then \
@@ -694,129 +1117,30 @@ checkdtc:
 		false; \
 	fi
 
-#
-# Auto-generate the autoconf.mk file (which is included by all makefiles)
-#
-# This target actually generates 2 files; autoconf.mk and autoconf.mk.dep.
-# the dep file is only include in this top level makefile to determine when
-# to regenerate the autoconf.mk file.
-$(obj)include/autoconf.mk.dep: $(obj)include/config.h include/common.h
-	@$(XECHO) Generating $@ ; \
-	set -e ; \
-	: Generate the dependancies ; \
-	$(CC) -x c -DDO_DEPS_ONLY -M $(CFLAGS) $(CPPFLAGS) \
-		-MQ $(obj)include/autoconf.mk include/common.h > $@
-
-$(obj)include/autoconf.mk: $(obj)include/config.h
-	@$(XECHO) Generating $@ ; \
-	set -e ; \
-	: Extract the config macros ; \
-	$(CPP) $(CFLAGS) -DDO_DEPS_ONLY -dM include/common.h | \
-		sed -n -f tools/scripts/define2mk.sed > $@.tmp && \
-	mv $@.tmp $@
-
-# Auto-generate the spl-autoconf.mk file (which is included by all makefiles for SPL)
-$(obj)include/tpl-autoconf.mk: $(obj)include/config.h
-	@$(XECHO) Generating $@ ; \
-	set -e ; \
-	: Extract the config macros ; \
-	$(CPP) $(CFLAGS) -DCONFIG_TPL_BUILD  -DCONFIG_SPL_BUILD\
-			-DDO_DEPS_ONLY -dM include/common.h | \
-	sed -n -f tools/scripts/define2mk.sed > $@.tmp && \
-	mv $@.tmp $@
-
-$(obj)include/spl-autoconf.mk: $(obj)include/config.h
-	@$(XECHO) Generating $@ ; \
-	set -e ; \
-	: Extract the config macros ; \
-	$(CPP) $(CFLAGS) -DCONFIG_SPL_BUILD -DDO_DEPS_ONLY -dM include/common.h | \
-	sed -n -f tools/scripts/define2mk.sed > $@.tmp && \
-	mv $@.tmp $@
-
-$(obj)include/generated/generic-asm-offsets.h:	$(obj)include/autoconf.mk.dep \
-	$(obj)include/spl-autoconf.mk \
-	$(obj)include/tpl-autoconf.mk \
-	$(obj)lib/asm-offsets.s
-	@$(XECHO) Generating $@
-	tools/scripts/make-asm-offsets $(obj)lib/asm-offsets.s $@
-
-$(obj)lib/asm-offsets.s:	$(obj)include/autoconf.mk.dep \
-	$(obj)include/spl-autoconf.mk \
-	$(obj)include/tpl-autoconf.mk \
-	$(src)lib/asm-offsets.c
-	@mkdir -p $(obj)lib
-	$(CC) -DDO_DEPS_ONLY \
-		$(CFLAGS) $(CFLAGS_$(BCURDIR)/$(@F)) $(CFLAGS_$(BCURDIR)) \
-		-o $@ $(src)lib/asm-offsets.c -c -S
-
-$(obj)include/generated/asm-offsets.h:	$(obj)include/autoconf.mk.dep \
-	$(obj)include/spl-autoconf.mk \
-	$(obj)include/tpl-autoconf.mk \
-	$(obj)$(CPUDIR)/$(SOC)/asm-offsets.s
-	@$(XECHO) Generating $@
-	tools/scripts/make-asm-offsets $(obj)$(CPUDIR)/$(SOC)/asm-offsets.s $@
-
-$(obj)$(CPUDIR)/$(SOC)/asm-offsets.s:	$(obj)include/autoconf.mk.dep \
-	$(obj)include/spl-autoconf.mk \
-	$(obj)include/tpl-autoconf.mk
-	@mkdir -p $(obj)$(CPUDIR)/$(SOC)
-	if [ -f $(src)$(CPUDIR)/$(SOC)/asm-offsets.c ];then \
-		$(CC) -DDO_DEPS_ONLY \
-		$(CFLAGS) $(CFLAGS_$(BCURDIR)/$(@F)) $(CFLAGS_$(BCURDIR)) \
-			-o $@ $(src)$(CPUDIR)/$(SOC)/asm-offsets.c -c -S; \
-	else \
-		touch $@; \
+#########################################################################
+
+# ARM relocations should all be R_ARM_RELATIVE (32-bit) or
+# R_AARCH64_RELATIVE (64-bit).
+checkarmreloc: u-boot
+	@RELOC="`$(CROSS_COMPILE)readelf -r -W $< | cut -d ' ' -f 4 | \
+		grep R_A | sort -u`"; \
+	if test "$$RELOC" != "R_ARM_RELATIVE" -a \
+		 "$$RELOC" != "R_AARCH64_RELATIVE"; then \
+		echo "$< contains unexpected relocations: $$RELOC"; \
+		false; \
 	fi
 
-#########################################################################
-else	# !config.mk
-all $(obj)u-boot.hex $(obj)u-boot.srec $(obj)u-boot.bin \
-$(obj)u-boot.img $(obj)u-boot.dis $(obj)u-boot \
-$(filter-out tools,$(SUBDIRS)) \
-updater depend dep tags ctags etags cscope $(obj)System.map:
-	@echo "System not configured - see README" >&2
-	@ exit 1
-
-tools: $(VERSION_FILE) $(TIMESTAMP_FILE)
-	$(MAKE) -C $@ all
-endif	# config.mk
-
-# ARM relocations should all be R_ARM_RELATIVE.
-checkarmreloc: $(obj)u-boot
-	@if test "R_ARM_RELATIVE" != \
-		"`$(CROSS_COMPILE)readelf -r $< | cut -d ' ' -f 4 | grep R_ARM | sort -u`"; \
-		then echo "$< contains relocations other than \
-		R_ARM_RELATIVE"; false; fi
-
-$(VERSION_FILE):
-		@mkdir -p $(dir $(VERSION_FILE))
-		@( localvers='$(shell $(TOPDIR)/tools/setlocalversion $(TOPDIR))' ; \
-		   printf '#define PLAIN_VERSION "%s%s"\n' \
-			"$(U_BOOT_VERSION)" "$${localvers}" ; \
-		   printf '#define U_BOOT_VERSION "U-Boot %s%s"\n' \
-			"$(U_BOOT_VERSION)" "$${localvers}" ; \
-		) > $@.tmp
-		@( printf '#define CC_VERSION_STRING "%s"\n' \
-		 '$(shell $(CC) --version | head -n 1)' )>>  $@.tmp
-		@( printf '#define LD_VERSION_STRING "%s"\n' \
-		 '$(shell $(LD) -v | head -n 1)' )>>  $@.tmp
-		@cmp -s $@ $@.tmp && rm -f $@.tmp || mv -f $@.tmp $@
-
-$(TIMESTAMP_FILE):
-		@mkdir -p $(dir $(TIMESTAMP_FILE))
-		@LC_ALL=C date +'#define U_BOOT_DATE "%b %d %C%y"' > $@.tmp
-		@LC_ALL=C date +'#define U_BOOT_TIME "%T"' >> $@.tmp
-		@cmp -s $@ $@.tmp && rm -f $@.tmp || mv -f $@.tmp $@
-
-easylogo env gdb:
-	$(MAKE) -C tools/$@ all MTD_VERSION=${MTD_VERSION}
-gdbtools: gdb
-
-xmldocs pdfdocs psdocs htmldocs mandocs: tools/kernel-doc/docproc
-	$(MAKE) U_BOOT_VERSION=$(U_BOOT_VERSION) -C doc/DocBook/ $@
-
-tools-all: easylogo env gdb $(VERSION_FILE) $(TIMESTAMP_FILE)
-	$(MAKE) -C tools HOST_TOOLS_ALL=y
+env: scripts_basic
+	$(Q)$(MAKE) $(build)=tools/$@
+
+tools-only: scripts_basic $(version_h) $(timestamp_h)
+	$(Q)$(MAKE) $(build)=tools
+
+tools-all: export HOST_TOOLS_ALL=y
+tools-all: env tools ;
+
+cross_tools: export CROSS_BUILD_TOOLS=y
+cross_tools: tools ;
 
 .PHONY : CHANGELOG
 CHANGELOG:
@@ -827,118 +1151,250 @@ include/license.h: tools/bin2header COPYING
 	cat COPYING | gzip -9 -c | ./tools/bin2header license_gzip > include/license.h
 #########################################################################
 
-unconfig:
-	@rm -f $(obj)include/config.h $(obj)include/config.mk \
-		$(obj)board/*/config.tmp $(obj)board/*/*/config.tmp \
-		$(obj)include/autoconf.mk $(obj)include/autoconf.mk.dep \
-		$(obj)include/spl-autoconf.mk \
-		$(obj)include/tpl-autoconf.mk
+###
+# Cleaning is done on three levels.
+# make clean     Delete most generated files
+#                Leave enough to build external modules
+# make mrproper  Delete the current configuration, and all generated files
+# make distclean Remove editor backup files, patch leftover files and the like
+
+# Directories & files removed with 'make clean'
+CLEAN_DIRS  += $(MODVERDIR)
+CLEAN_FILES += u-boot.lds include/bmp_logo.h include/bmp_logo_data.h \
+	       include/autoconf.mk* include/spl-autoconf.mk \
+	       include/tpl-autoconf.mk
+
+# Directories & files removed with 'make clobber'
+CLOBBER_DIRS  += $(patsubst %,spl/%, $(filter-out Makefile, \
+		 $(shell ls -1 spl 2>/dev/null))) \
+		 tpl
+CLOBBER_FILES += u-boot* MLO* SPL System.map nand_spl/u-boot*
+
+# Directories & files removed with 'make mrproper'
+MRPROPER_DIRS  += include/config include/generated
+MRPROPER_FILES += .config .config.old \
+		  tags TAGS cscope* GPATH GTAGS GRTAGS GSYMS \
+		  include/config.h include/config.mk
+
+# clean - Delete most, but leave enough to build external modules
+#
+clean: rm-dirs  := $(CLEAN_DIRS)
+clean: rm-files := $(CLEAN_FILES)
+
+clean-dirs	:= $(foreach f,$(u-boot-alldirs),$(if $(wildcard $(srctree)/$f/Makefile),$f))
+
+clean-dirs      := $(addprefix _clean_, $(clean-dirs) doc/DocBook)
+
+PHONY += $(clean-dirs) clean archclean
+$(clean-dirs):
+	$(Q)$(MAKE) $(clean)=$(patsubst _clean_%,%,$@)
+
+# TODO: Do not use *.cfgtmp
+clean: $(clean-dirs)
+	$(call cmd,rmdirs)
+	$(call cmd,rmfiles)
+	@find $(if $(KBUILD_EXTMOD), $(KBUILD_EXTMOD), .) $(RCS_FIND_IGNORE) \
+		\( -name '*.[oas]' -o -name '*.ko' -o -name '.*.cmd' \
+		-o -name '*.ko.*' -o -name '*.su' -o -name '*.cfgtmp' \
+		-o -name '.*.d' -o -name '.*.tmp' -o -name '*.mod.c' \
+		-o -name '*.symtypes' -o -name 'modules.order' \
+		-o -name modules.builtin -o -name '.tmp_*.o.*' \
+		-o -name '*.gcno' \) -type f -print | xargs rm -f
+	@find $(if $(KBUILD_EXTMOD), $(KBUILD_EXTMOD), .) $(RCS_FIND_IGNORE) \
+		-path './nand_spl/*' -type l -print | xargs rm -f
+
+# clobber
+#
+clobber: rm-dirs  := $(CLOBBER_DIRS)
+clobber: rm-files := $(CLOBBER_FILES)
 
-%_config::	unconfig
-	@$(MKCONFIG) -A $(@:_config=)
+PHONY += clobber
 
-sinclude $(obj).boards.depend
-$(obj).boards.depend:	boards.cfg
-	@awk '(NF && $$1 !~ /^#/) { print $$7 ": " $$7 "_config; $$(MAKE)" }' $< > $@
+clobber: clean
+	$(call cmd,rmdirs)
+	$(call cmd,rmfiles)
 
+# mrproper - Delete all generated files, including .config
 #
-# Functions to generate common board directory names
-#
-lcname	= $(shell echo $(1) | sed -e 's/\(.*\)_config/\L\1/')
-ucname	= $(shell echo $(1) | sed -e 's/\(.*\)_config/\U\1/')
+mrproper: rm-dirs  := $(wildcard $(MRPROPER_DIRS))
+mrproper: rm-files := $(wildcard $(MRPROPER_FILES))
+mrproper-dirs      := $(addprefix _mrproper_,scripts)
 
-#########################################################################
-#########################################################################
+PHONY += $(mrproper-dirs) mrproper archmrproper
+$(mrproper-dirs):
+	$(Q)$(MAKE) $(clean)=$(patsubst _mrproper_%,%,$@)
 
-clean:
-	@rm -f $(obj)examples/standalone/82559_eeprom			  \
-	       $(obj)examples/standalone/atmel_df_pow2			  \
-	       $(obj)examples/standalone/eepro100_eeprom		  \
-	       $(obj)examples/standalone/hello_world			  \
-	       $(obj)examples/standalone/interrupt			  \
-	       $(obj)examples/standalone/mem_to_mem_idma2intr		  \
-	       $(obj)examples/standalone/sched				  \
-	       $(obj)examples/standalone/smc911{11,x}_eeprom		  \
-	       $(obj)examples/standalone/test_burst			  \
-	       $(obj)examples/standalone/timer
-	@rm -f $(obj)examples/api/demo{,.bin}
-	@rm -f $(obj)tools/bmp_logo	   $(obj)tools/easylogo/easylogo  \
-	       $(obj)tools/env/{fw_printenv,fw_setenv}			  \
-	       $(obj)tools/envcrc					  \
-	       $(obj)tools/gdb/{astest,gdbcont,gdbsend}			  \
-	       $(obj)tools/gen_eth_addr    $(obj)tools/img2srec		  \
-	       $(obj)tools/mk{env,}image   $(obj)tools/mpc86x_clk	  \
-	       $(obj)tools/mk{$(BOARD),}spl				  \
-	       $(obj)tools/mxsboot					  \
-	       $(obj)tools/ncb		   $(obj)tools/ubsha1		  \
-	       $(obj)tools/kernel-doc/docproc				  \
-	       $(obj)tools/proftool
-	@rm -f $(obj)board/cray/L1/{bootscript.c,bootscript.image}	  \
-	       $(obj)board/matrix_vision/*/bootscript.img		  \
-	       $(obj)board/voiceblue/eeprom 				  \
-	       $(obj)u-boot.lds						  \
-	       $(obj)arch/blackfin/cpu/bootrom-asm-offsets.[chs]	  \
-	       $(obj)arch/blackfin/cpu/init.{lds,elf}
-	@rm -f $(obj)include/bmp_logo.h
-	@rm -f $(obj)include/bmp_logo_data.h
-	@rm -f $(obj)lib/asm-offsets.s
-	@rm -f $(obj)include/generated/asm-offsets.h
-	@rm -f $(obj)$(CPUDIR)/$(SOC)/asm-offsets.s
-	@rm -f $(TIMESTAMP_FILE) $(VERSION_FILE)
-	@$(MAKE) -s -C doc/DocBook/ cleandocs
-	@find $(OBJTREE) -type f \
-		\( -name 'core' -o -name '*.bak' -o -name '*~' -o -name '*.su' \
-		-o -name '*.o'	-o -name '*.a' -o -name '*.exe' \
-		-o -name '*.cfgtmp' \) -print \
-		| xargs rm -f
-
-# Removes everything not needed for testing u-boot
-tidy:	clean
-	@find $(OBJTREE) -type f \( -name '*.depend*' \) -print | xargs rm -f
-
-clobber:	tidy
-	@find $(OBJTREE) -type f \( -name '*.srec' \
-		-o -name '*.bin' -o -name u-boot.img \) \
-		-print0 | xargs -0 rm -f
-	@rm -f $(OBJS) $(obj)*.bak $(obj)ctags $(obj)etags $(obj)TAGS \
-		$(obj)cscope.* $(obj)*.*~
-	@rm -f $(obj)u-boot $(obj)u-boot.map $(obj)u-boot.hex $(ALL-y)
-	@rm -f $(obj)u-boot.kwb
-	@rm -f $(obj)u-boot.pbl
-	@rm -f $(obj)u-boot.imx
-	@rm -f $(obj)u-boot-with-spl.imx
-	@rm -f $(obj)u-boot-with-nand-spl.imx
-	@rm -f $(obj)u-boot.ubl
-	@rm -f $(obj)u-boot.ais
-	@rm -f $(obj)u-boot.dtb
-	@rm -f $(obj)u-boot.sb
-	@rm -f $(obj)u-boot.bd
-	@rm -f $(obj)u-boot.spr
-	@rm -f $(obj)nand_spl/{u-boot.{lds,lst},System.map}
-	@rm -f $(obj)nand_spl/{u-boot-nand_spl.lds,u-boot-spl,u-boot-spl.map}
-	@rm -f $(obj)spl/{u-boot-spl,u-boot-spl.bin,u-boot-spl.map}
-	@rm -f $(obj)spl/u-boot-spl.lds
-	@rm -f $(obj)tpl/{u-boot-tpl,u-boot-tpl.bin,u-boot-tpl.map}
-	@rm -f $(obj)tpl/u-boot-spl.lds
-	@rm -f $(obj)MLO MLO.byteswap
-	@rm -f $(obj)SPL
-	@rm -f $(obj)tools/xway-swap-bytes
-	@rm -f $(obj)arch/powerpc/cpu/mpc824x/bedbug_603e.c
-	@rm -f $(obj)arch/powerpc/cpu/mpc83xx/ddr-gen?.c
-	@rm -fr $(obj)include/asm/proc $(obj)include/asm/arch $(obj)include/asm
-	@rm -fr $(obj)include/generated
-	@[ ! -d $(obj)nand_spl ] || find $(obj)nand_spl -name "*" -type l -print | xargs rm -f
-	@rm -f $(obj)dts/*.tmp
-	@rm -f $(obj)spl/u-boot-spl{,-pad}.ais
-
-mrproper \
-distclean:	clobber unconfig
-ifneq ($(OBJTREE),$(SRCTREE))
-	rm -rf $(obj)*
-endif
+mrproper: clobber $(mrproper-dirs)
+	$(call cmd,rmdirs)
+	$(call cmd,rmfiles)
+	@rm -f arch/*/include/asm/arch arch/*/include/asm/proc
+
+# distclean
+#
+PHONY += distclean
+
+distclean: mrproper
+	@find $(srctree) $(RCS_FIND_IGNORE) \
+		\( -name '*.orig' -o -name '*.rej' -o -name '*~' \
+		-o -name '*.bak' -o -name '#*#' -o -name '.*.orig' \
+		-o -name '.*.rej' -o -name '*.pyc' \
+		-o -name '*%' -o -name '.*.cmd' -o -name 'core' \) \
+		-type f -print | xargs rm -f
 
 backup:
-	F=`basename $(TOPDIR)` ; cd .. ; \
+	F=`basename $(srctree)` ; cd .. ; \
 	gtar --force-local -zcvf `LC_ALL=C date "+$$F-%Y-%m-%d-%T.tar.gz"` $$F
 
-#########################################################################
+help:
+	@echo  'Cleaning targets:'
+	@echo  '  clean		  - Remove most generated files but keep the config and'
+	@echo  '                    necessities for testing u-boot'
+	@echo  '  clobber	  - Remove most generated files but keep the config'
+	@echo  '  mrproper	  - Remove all generated files + config + various backup files'
+	@echo  '  distclean	  - mrproper + remove editor backup and patch files'
+	@echo  ''
+# uncomment after adding Kconfig feature
+#	@echo  'Configuration targets:'
+#	@$(MAKE) -f $(srctree)/scripts/kconfig/Makefile help
+#	@echo  ''
+	@echo  'Other generic targets:'
+	@echo  '  all		  - Build all necessary images depending on configuration'
+	@echo  '  u-boot	  - Build the bare u-boot'
+	@echo  '  dir/            - Build all files in dir and below'
+	@echo  '  dir/file.[oisS] - Build specified target only'
+	@echo  '  dir/file.lst    - Build specified mixed source/assembly target only'
+	@echo  '                    (requires a recent binutils and recent build (System.map))'
+	@echo  '  tags/TAGS	  - Generate tags file for editors'
+	@echo  '  cscope	  - Generate cscope index'
+	@echo  '  ubootrelease	  - Output the release version string'
+	@echo  '  ubootversion	  - Output the version stored in Makefile'
+	@echo  ''
+	@echo  'Static analysers'
+	@echo  '  checkstack      - Generate a list of stack hogs'
+	@echo  ''
+	@echo  'Documentation targets:'
+	@$(MAKE) -f $(srctree)/doc/DocBook/Makefile dochelp
+	@echo  ''
+	@echo  '  make V=0|1 [targets] 0 => quiet build (default), 1 => verbose build'
+	@echo  '  make V=2   [targets] 2 => give reason for rebuild of target'
+	@echo  '  make O=dir [targets] Locate all output files in "dir", including .config'
+	@echo  '  make C=1   [targets] Check all c source with $$CHECK (sparse by default)'
+	@echo  '  make C=2   [targets] Force check of all c source with $$CHECK'
+	@echo  '  make RECORDMCOUNT_WARN=1 [targets] Warn about ignored mcount sections'
+	@echo  '  make W=n   [targets] Enable extra gcc checks, n=1,2,3 where'
+	@echo  '		1: warnings which may be relevant and do not occur too often'
+	@echo  '		2: warnings which occur quite often but may still be relevant'
+	@echo  '		3: more obscure warnings, can most likely be ignored'
+	@echo  '		Multiple levels can be combined with W=12 or W=123'
+	@echo  ''
+	@echo  'Execute "make" or "make all" to build all targets marked with [*] '
+	@echo  'For further info see the ./README file'
+
+
+# Documentation targets
+# ---------------------------------------------------------------------------
+%docs: scripts_basic FORCE
+	$(Q)$(MAKE) $(build)=scripts build_docproc
+	$(Q)$(MAKE) $(build)=doc/DocBook $@
+
+# Dummies...
+PHONY += prepare scripts
+prepare: ;
+scripts: ;
+
+endif #ifeq ($(config-targets),1)
+endif #ifeq ($(mixed-targets),1)
+
+PHONY += checkstack ubootrelease ubootversion
+
+checkstack:
+	$(OBJDUMP) -d u-boot $$(find . -name u-boot-spl) | \
+	$(PERL) $(src)/scripts/checkstack.pl $(ARCH)
+
+ubootrelease:
+	@echo "$(UBOOTVERSION)$$($(CONFIG_SHELL) $(srctree)/scripts/setlocalversion $(srctree))"
+
+ubootversion:
+	@echo $(UBOOTVERSION)
+
+# Single targets
+# ---------------------------------------------------------------------------
+# Single targets are compatible with:
+# - build with mixed source and output
+# - build with separate output dir 'make O=...'
+# - external modules
+#
+#  target-dir => where to store outputfile
+#  build-dir  => directory in kernel source tree to use
+
+ifeq ($(KBUILD_EXTMOD),)
+        build-dir  = $(patsubst %/,%,$(dir $@))
+        target-dir = $(dir $@)
+else
+        zap-slash=$(filter-out .,$(patsubst %/,%,$(dir $@)))
+        build-dir  = $(KBUILD_EXTMOD)$(if $(zap-slash),/$(zap-slash))
+        target-dir = $(if $(KBUILD_EXTMOD),$(dir $<),$(dir $@))
+endif
+
+%.s: %.c prepare scripts FORCE
+	$(Q)$(MAKE) $(build)=$(build-dir) $(target-dir)$(notdir $@)
+%.i: %.c prepare scripts FORCE
+	$(Q)$(MAKE) $(build)=$(build-dir) $(target-dir)$(notdir $@)
+%.o: %.c prepare scripts FORCE
+	$(Q)$(MAKE) $(build)=$(build-dir) $(target-dir)$(notdir $@)
+%.lst: %.c prepare scripts FORCE
+	$(Q)$(MAKE) $(build)=$(build-dir) $(target-dir)$(notdir $@)
+%.s: %.S prepare scripts FORCE
+	$(Q)$(MAKE) $(build)=$(build-dir) $(target-dir)$(notdir $@)
+%.o: %.S prepare scripts FORCE
+	$(Q)$(MAKE) $(build)=$(build-dir) $(target-dir)$(notdir $@)
+%.symtypes: %.c prepare scripts FORCE
+	$(Q)$(MAKE) $(build)=$(build-dir) $(target-dir)$(notdir $@)
+
+# Modules
+/: prepare scripts FORCE
+	$(cmd_crmodverdir)
+	$(Q)$(MAKE) KBUILD_MODULES=$(if $(CONFIG_MODULES),1) \
+	$(build)=$(build-dir)
+%/: prepare scripts FORCE
+	$(cmd_crmodverdir)
+	$(Q)$(MAKE) KBUILD_MODULES=$(if $(CONFIG_MODULES),1) \
+	$(build)=$(build-dir)
+%.ko: prepare scripts FORCE
+	$(cmd_crmodverdir)
+	$(Q)$(MAKE) KBUILD_MODULES=$(if $(CONFIG_MODULES),1)   \
+	$(build)=$(build-dir) $(@:.ko=.o)
+	$(Q)$(MAKE) -f $(srctree)/scripts/Makefile.modpost
+
+# FIXME Should go into a make.lib or something 
+# ===========================================================================
+
+quiet_cmd_rmdirs = $(if $(wildcard $(rm-dirs)),CLEAN   $(wildcard $(rm-dirs)))
+      cmd_rmdirs = rm -rf $(rm-dirs)
+
+quiet_cmd_rmfiles = $(if $(wildcard $(rm-files)),CLEAN   $(wildcard $(rm-files)))
+      cmd_rmfiles = rm -f $(rm-files)
+
+# read all saved command lines
+
+targets := $(wildcard $(sort $(targets)))
+cmd_files := $(wildcard .*.cmd $(foreach f,$(targets),$(dir $(f)).$(notdir $(f)).cmd))
+
+ifneq ($(cmd_files),)
+  $(cmd_files): ;	# Do not try to update included dependency files
+  include $(cmd_files)
+endif
+
+# Shorthand for $(Q)$(MAKE) -f scripts/Makefile.clean obj=dir
+# Usage:
+# $(Q)$(MAKE) $(clean)=dir
+clean := -f $(if $(KBUILD_SRC),$(srctree)/)scripts/Makefile.clean obj
+
+endif	# skip-makefile
+
+PHONY += FORCE
+FORCE:
+
+# Declare the contents of the .PHONY variable as phony.  We keep that
+# information in a variable so we can use it in if_changed and friends.
+.PHONY: $(PHONY)
diff --git a/README b/README
index 09662a4a03..39e05d333c 100644
--- a/README
+++ b/README
@@ -141,7 +141,6 @@ Directory Hierarchy:
 	/s3c24x0	Files specific to Samsung S3C24X0 CPUs
       /arm926ejs	Files specific to ARM 926 CPUs
       /arm1136		Files specific to ARM 1136 CPUs
-      /ixp		Files specific to Intel XScale IXP CPUs
       /pxa		Files specific to Intel XScale PXA CPUs
       /sa1100		Files specific to Intel StrongARM SA1100 CPUs
     /lib		Architecture specific library files
@@ -423,9 +422,10 @@ The following options need to be configured:
 		CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT
 		This value denotes start offset of DSP CCSR space.
 
-		CONFIG_SYS_FSL_DDR_EMU
-		Specify emulator support for DDR. Some DDR features such as
-		deskew training are not available.
+		CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
+		Single Source Clock is clocking mode present in some of FSL SoC's.
+		In this mode, a single differential clock is used to supply
+		clocks to the sysclock, ddrclock and usbclock.
 
 - Generic CPU options:
 		CONFIG_SYS_BIG_ENDIAN, CONFIG_SYS_LITTLE_ENDIAN
@@ -433,6 +433,75 @@ The following options need to be configured:
 		Defines the endianess of the CPU. Implementation of those
 		values is arch specific.
 
+		CONFIG_SYS_FSL_DDR
+		Freescale DDR driver in use. This type of DDR controller is
+		found in mpc83xx, mpc85xx, mpc86xx as well as some ARM core
+		SoCs.
+
+		CONFIG_SYS_FSL_DDR_ADDR
+		Freescale DDR memory-mapped register base.
+
+		CONFIG_SYS_FSL_DDR_EMU
+		Specify emulator support for DDR. Some DDR features such as
+		deskew training are not available.
+
+		CONFIG_SYS_FSL_DDRC_GEN1
+		Freescale DDR1 controller.
+
+		CONFIG_SYS_FSL_DDRC_GEN2
+		Freescale DDR2 controller.
+
+		CONFIG_SYS_FSL_DDRC_GEN3
+		Freescale DDR3 controller.
+
+		CONFIG_SYS_FSL_DDRC_ARM_GEN3
+		Freescale DDR3 controller for ARM-based SoCs.
+
+		CONFIG_SYS_FSL_DDR1
+		Board config to use DDR1. It can be enabled for SoCs with
+		Freescale DDR1 or DDR2 controllers, depending on the board
+		implemetation.
+
+		CONFIG_SYS_FSL_DDR2
+		Board config to use DDR2. It can be eanbeld for SoCs with
+		Freescale DDR2 or DDR3 controllers, depending on the board
+		implementation.
+
+		CONFIG_SYS_FSL_DDR3
+		Board config to use DDR3. It can be enabled for SoCs with
+		Freescale DDR3 controllers.
+
+		CONFIG_SYS_FSL_IFC_BE
+		Defines the IFC controller register space as Big Endian
+
+		CONFIG_SYS_FSL_IFC_LE
+		Defines the IFC controller register space as Little Endian
+
+		CONFIG_SYS_FSL_PBL_PBI
+		It enables addition of RCW (Power on reset configuration) in built image.
+		Please refer doc/README.pblimage for more details
+
+		CONFIG_SYS_FSL_PBL_RCW
+		It adds PBI(pre-boot instructions) commands in u-boot build image.
+		PBI commands can be used to configure SoC before it starts the execution.
+		Please refer doc/README.pblimage for more details
+
+		CONFIG_SYS_FSL_DDR_BE
+		Defines the DDR controller register space as Big Endian
+
+		CONFIG_SYS_FSL_DDR_LE
+		Defines the DDR controller register space as Little Endian
+
+		CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY
+		Physical address from the view of DDR controllers. It is the
+		same as CONFIG_SYS_DDR_SDRAM_BASE for  all Power SoCs. But
+		it could be different for ARM SoCs.
+
+		CONFIG_SYS_FSL_DDR_INTLV_256B
+		DDR controller interleaving on 256-byte. This is a special
+		interleaving mode, handled by Dickens for Freescale layerscape
+		SoCs with ARM core.
+
 - Intel Monahans options:
 		CONFIG_SYS_MONAHANS_RUN_MODE_OSC_RATIO
 
@@ -497,6 +566,8 @@ The following options need to be configured:
 		CONFIG_ARM_ERRATA_742230
 		CONFIG_ARM_ERRATA_743622
 		CONFIG_ARM_ERRATA_751472
+		CONFIG_ARM_ERRATA_794072
+		CONFIG_ARM_ERRATA_761320
 
 		If set, the workarounds for these ARM errata are applied early
 		during U-Boot startup. Note that these options force the
@@ -705,6 +776,11 @@ The following options need to be configured:
 		the "silent" environment variable. See
 		doc/README.silent for more information.
 
+		CONFIG_SYS_CONSOLE_BG_COL: define the backgroundcolor, default
+			is 0x00.
+		CONFIG_SYS_CONSOLE_FG_COL: define the foregroundcolor, default
+			is 0xa0.
+
 - Console Baudrate:
 		CONFIG_BAUDRATE - in bps
 		Select one of the baudrates listed in
@@ -779,6 +855,22 @@ The following options need to be configured:
 		as a convenience, when switching between booting from
 		RAM and NFS.
 
+- Bootcount:
+		CONFIG_BOOTCOUNT_LIMIT
+		Implements a mechanism for detecting a repeating reboot
+		cycle, see:
+		http://www.denx.de/wiki/view/DULG/UBootBootCountLimit
+
+		CONFIG_BOOTCOUNT_ENV
+		If no softreset save registers are found on the hardware
+		"bootcount" is stored in the environment. To prevent a
+		saveenv on all reboots, the environment variable
+		"upgrade_available" is used. If "upgrade_available" is
+		0, "bootcount" is always 0, if "upgrade_available" is
+		1 "bootcount" is incremented in the environment.
+		So the Userspace Applikation must set the "upgrade_available"
+		and "bootcount" variable to 0, if a boot was successfully.
+
 - Pre-Boot Commands:
 		CONFIG_PREBOOT
 
@@ -827,6 +919,7 @@ The following options need to be configured:
 		CONFIG_CMD_BSP		* Board specific commands
 		CONFIG_CMD_BOOTD	  bootd
 		CONFIG_CMD_CACHE	* icache, dcache
+		CONFIG_CMD_CLK   	* clock command support
 		CONFIG_CMD_CONSOLE	  coninfo
 		CONFIG_CMD_CRC32	* crc32
 		CONFIG_CMD_DATE		* support for RTC, date/time...
@@ -843,13 +936,15 @@ The following options need to be configured:
 		CONFIG_CMD_ELF		* bootelf, bootvx
 		CONFIG_CMD_ENV_CALLBACK	* display details about env callbacks
 		CONFIG_CMD_ENV_FLAGS	* display details about env flags
+		CONFIG_CMD_ENV_EXISTS	* check existence of env variable
 		CONFIG_CMD_EXPORTENV	* export the environment
 		CONFIG_CMD_EXT2		* ext2 command support
 		CONFIG_CMD_EXT4		* ext4 command support
+		CONFIG_CMD_FS_GENERIC	* filesystem commands (e.g. load, ls)
+					  that work for multiple fs types
 		CONFIG_CMD_SAVEENV	  saveenv
 		CONFIG_CMD_FDC		* Floppy Disk Support
 		CONFIG_CMD_FAT		* FAT command support
-		CONFIG_CMD_FDOS		* Dos diskette Support
 		CONFIG_CMD_FLASH	  flinfo, erase, protect
 		CONFIG_CMD_FPGA		  FPGA device initialization support
 		CONFIG_CMD_FUSE		* Device fuse support
@@ -919,7 +1014,7 @@ The following options need to be configured:
 		CONFIG_CMD_CDP		* Cisco Discover Protocol support
 		CONFIG_CMD_MFSL		* Microblaze FSL support
 		CONFIG_CMD_XIMG		  Load part of Multi Image
-
+		CONFIG_CMD_UUID		* Generate random UUID or GUID string
 
 		EXAMPLE: If you want all functions except of network
 		support you can write:
@@ -1027,7 +1122,6 @@ The following options need to be configured:
 
 - GPIO Support:
 		CONFIG_PCA953X		- use NXP's PCA953X series I2C GPIO
-		CONFIG_PCA953X_INFO	- enable pca953x info command
 
 		The CONFIG_SYS_I2C_PCA953X_WIDTH option specifies a list of
 		chip-ngpio pairs that tell the PCA953X driver the number of
@@ -1362,6 +1456,13 @@ The following options need to be configured:
 			for your device
 			- CONFIG_USBD_PRODUCTID 0xFFFF
 
+		Some USB device drivers may need to check USB cable attachment.
+		In this case you can enable following config in BoardName.h:
+			CONFIG_USB_CABLE_CHECK
+			This enables function definition:
+			- usb_cable_connected() in include/usb.h
+			Implementation of this function is board-specific.
+
 - ULPI Layer Support:
 		The ULPI (UTMI Low Pin (count) Interface) PHYs are supported via
 		the generic ULPI layer. The generic layer accesses the ULPI PHY
@@ -1426,6 +1527,16 @@ The following options need to be configured:
 		this to the maximum filesize (in bytes) for the buffer.
 		Default is 4 MiB if undefined.
 
+		DFU_DEFAULT_POLL_TIMEOUT
+		Poll timeout [ms], is the timeout a device can send to the
+		host. The host must wait for this timeout before sending
+		a subsequent DFU_GET_STATUS request to the device.
+
+		DFU_MANIFEST_POLL_TIMEOUT
+		Poll timeout [ms], which the device sends to the host when
+		entering dfuMANIFEST state. Host waits this timeout, before
+		sending again an USB request to the device.
+
 - Journaling Flash filesystem support:
 		CONFIG_JFFS2_NAND, CONFIG_JFFS2_NAND_OFF, CONFIG_JFFS2_NAND_SIZE,
 		CONFIG_JFFS2_NAND_DEV
@@ -1642,7 +1753,7 @@ CBFS (Coreboot Filesystem) support
 
 		If this option is set, then U-Boot will prevent the environment
 		variable "splashimage" from being set to a problematic address
-		(see README.displaying-bmps and README.arm-unaligned-accesses).
+		(see README.displaying-bmps).
 		This option is useful for targets where, due to alignment
 		restrictions, an improperly aligned BMP image will cause a data
 		abort. If you think you will not have problems with unaligned
@@ -1951,6 +2062,21 @@ CBFS (Coreboot Filesystem) support
 		kernel). Defining CONFIG_STATUS_LED enables this
 		feature in U-Boot.
 
+		Additional options:
+
+		CONFIG_GPIO_LED
+		The status LED can be connected to a GPIO pin.
+		In such cases, the gpio_led driver can be used as a
+		status LED backend implementation. Define CONFIG_GPIO_LED
+		to include the gpio_led driver in the U-Boot binary.
+
+		CONFIG_GPIO_LED_INVERTED_TABLE
+		Some GPIO connected LEDs may have inverted polarity in which
+		case the GPIO high value corresponds to LED off state and
+		GPIO low value corresponds to LED on state.
+		In such cases CONFIG_GPIO_LED_INVERTED_TABLE may be defined
+		with a list of GPIO LEDs that have inverted polarity.
+
 - CAN Support:	CONFIG_CAN_DRIVER
 
 		Defining CONFIG_CAN_DRIVER enables CAN driver support
@@ -1994,15 +2120,82 @@ CBFS (Coreboot Filesystem) support
 		    second bus.
 
 		- drivers/i2c/tegra_i2c.c:
-		 - activate this driver with CONFIG_SYS_I2C_TEGRA
-		 - This driver adds 4 i2c buses with a fix speed from
-		   100000 and the slave addr 0!
+		  - activate this driver with CONFIG_SYS_I2C_TEGRA
+		  - This driver adds 4 i2c buses with a fix speed from
+		    100000 and the slave addr 0!
 
 		- drivers/i2c/ppc4xx_i2c.c
 		  - activate this driver with CONFIG_SYS_I2C_PPC4XX
 		  - CONFIG_SYS_I2C_PPC4XX_CH0 activate hardware channel 0
 		  - CONFIG_SYS_I2C_PPC4XX_CH1 activate hardware channel 1
 
+		- drivers/i2c/i2c_mxc.c
+		  - activate this driver with CONFIG_SYS_I2C_MXC
+		  - define speed for bus 1 with CONFIG_SYS_MXC_I2C1_SPEED
+		  - define slave for bus 1 with CONFIG_SYS_MXC_I2C1_SLAVE
+		  - define speed for bus 2 with CONFIG_SYS_MXC_I2C2_SPEED
+		  - define slave for bus 2 with CONFIG_SYS_MXC_I2C2_SLAVE
+		  - define speed for bus 3 with CONFIG_SYS_MXC_I2C3_SPEED
+		  - define slave for bus 3 with CONFIG_SYS_MXC_I2C3_SLAVE
+		If thoses defines are not set, default value is 100000
+		for speed, and 0 for slave.
+
+		- drivers/i2c/rcar_i2c.c:
+		  - activate this driver with CONFIG_SYS_I2C_RCAR
+		  - This driver adds 4 i2c buses
+
+		  - CONFIG_SYS_RCAR_I2C0_BASE for setting the register channel 0
+		  - CONFIG_SYS_RCAR_I2C0_SPEED for for the speed channel 0
+		  - CONFIG_SYS_RCAR_I2C1_BASE for setting the register channel 1
+		  - CONFIG_SYS_RCAR_I2C1_SPEED for for the speed channel 1
+		  - CONFIG_SYS_RCAR_I2C2_BASE for setting the register channel 2
+		  - CONFIG_SYS_RCAR_I2C2_SPEED for for the speed channel 2
+		  - CONFIG_SYS_RCAR_I2C3_BASE for setting the register channel 3
+		  - CONFIG_SYS_RCAR_I2C3_SPEED for for the speed channel 3
+		  - CONFIF_SYS_RCAR_I2C_NUM_CONTROLLERS for number of i2c buses
+
+		- drivers/i2c/sh_i2c.c:
+		  - activate this driver with CONFIG_SYS_I2C_SH
+		  - This driver adds from 2 to 5 i2c buses
+
+		  - CONFIG_SYS_I2C_SH_BASE0 for setting the register channel 0
+		  - CONFIG_SYS_I2C_SH_SPEED0 for for the speed channel 0
+		  - CONFIG_SYS_I2C_SH_BASE1 for setting the register channel 1
+		  - CONFIG_SYS_I2C_SH_SPEED1 for for the speed channel 1
+		  - CONFIG_SYS_I2C_SH_BASE2 for setting the register channel 2
+		  - CONFIG_SYS_I2C_SH_SPEED2 for for the speed channel 2
+		  - CONFIG_SYS_I2C_SH_BASE3 for setting the register channel 3
+		  - CONFIG_SYS_I2C_SH_SPEED3 for for the speed channel 3
+		  - CONFIG_SYS_I2C_SH_BASE4 for setting the register channel 4
+		  - CONFIG_SYS_I2C_SH_SPEED4 for for the speed channel 4
+		  - CONFIG_SYS_I2C_SH_BASE5 for setting the register channel 5
+		  - CONFIG_SYS_I2C_SH_SPEED5 for for the speed channel 5
+		  - CONFIF_SYS_I2C_SH_NUM_CONTROLLERS for nummber of i2c buses
+
+		- drivers/i2c/omap24xx_i2c.c
+		  - activate this driver with CONFIG_SYS_I2C_OMAP24XX
+		  - CONFIG_SYS_OMAP24_I2C_SPEED speed channel 0
+		  - CONFIG_SYS_OMAP24_I2C_SLAVE slave addr channel 0
+		  - CONFIG_SYS_OMAP24_I2C_SPEED1 speed channel 1
+		  - CONFIG_SYS_OMAP24_I2C_SLAVE1 slave addr channel 1
+		  - CONFIG_SYS_OMAP24_I2C_SPEED2 speed channel 2
+		  - CONFIG_SYS_OMAP24_I2C_SLAVE2 slave addr channel 2
+		  - CONFIG_SYS_OMAP24_I2C_SPEED3 speed channel 3
+		  - CONFIG_SYS_OMAP24_I2C_SLAVE3 slave addr channel 3
+		  - CONFIG_SYS_OMAP24_I2C_SPEED4 speed channel 4
+		  - CONFIG_SYS_OMAP24_I2C_SLAVE4 slave addr channel 4
+
+		- drivers/i2c/zynq_i2c.c
+		  - activate this driver with CONFIG_SYS_I2C_ZYNQ
+		  - set CONFIG_SYS_I2C_ZYNQ_SPEED for speed setting
+		  - set CONFIG_SYS_I2C_ZYNQ_SLAVE for slave addr
+
+		- drivers/i2c/s3c24x0_i2c.c:
+		  - activate this driver with CONFIG_SYS_I2C_S3C24X0
+		  - This driver adds i2c buses (11 for Exynos5250, Exynos5420
+		    9 i2c buses for Exynos4 and 1 for S3C24X0 SoCs from Samsung)
+		    with a fix speed from 100000 and the slave addr 0!
+
 		additional defines:
 
 		CONFIG_SYS_NUM_I2C_BUSES
@@ -2607,6 +2800,12 @@ CBFS (Coreboot Filesystem) support
 		Define this option to use the Bank addr/Extended addr
 		support on SPI flashes which has size > 16Mbytes.
 
+		CONFIG_SF_DUAL_FLASH		Dual flash memories
+
+		Define this option to use dual flash support where two flash
+		memories can be connected with a given cs line.
+		currently Xilinx Zynq qspi support these type of connections.
+
 - SystemACE Support:
 		CONFIG_SYSTEMACE
 
@@ -2677,11 +2876,31 @@ CBFS (Coreboot Filesystem) support
 		CONFIG_RSA
 
 		This enables the RSA algorithm used for FIT image verification
-		in U-Boot. See doc/uImage/signature for more information.
+		in U-Boot. See doc/uImage.FIT/signature.txt for more information.
 
 		The signing part is build into mkimage regardless of this
 		option.
 
+- bootcount support:
+		CONFIG_BOOTCOUNT_LIMIT
+
+		This enables the bootcounter support, see:
+		http://www.denx.de/wiki/DULG/UBootBootCountLimit
+
+		CONFIG_AT91SAM9XE
+		enable special bootcounter support on at91sam9xe based boards.
+		CONFIG_BLACKFIN
+		enable special bootcounter support on blackfin based boards.
+		CONFIG_SOC_DA8XX
+		enable special bootcounter support on da850 based boards.
+		CONFIG_BOOTCOUNT_RAM
+		enable support for the bootcounter in RAM
+		CONFIG_BOOTCOUNT_I2C
+		enable support for the bootcounter on an i2c (like RTC) device.
+			CONFIG_SYS_I2C_RTC_ADDR = i2c chip address
+			CONFIG_SYS_BOOTCOUNT_ADDR = i2c addr which is used for
+						    the bootcounter.
+			CONFIG_BOOTCOUNT_ALEN = address len
 
 - Show boot progress:
 		CONFIG_SHOW_BOOT_PROGRESS
@@ -3109,7 +3328,7 @@ FIT uImage format:
 
 		CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
 		Set for the SPL on PPC mpc8xxx targets, support for
-		arch/powerpc/cpu/mpc8xxx/ddr/libddr.o in SPL binary.
+		drivers/ddr/fsl/libddr.o in SPL binary.
 
 		CONFIG_SPL_COMMON_INIT_DDR
 		Set for common ddr init with serial presence detect in
@@ -3123,6 +3342,9 @@ FIT uImage format:
 		Defines the size and behavior of the NAND that SPL uses
 		to read U-Boot
 
+		CONFIG_SPL_NAND_BOOT
+		Add support NAND boot
+
 		CONFIG_SYS_NAND_U_BOOT_OFFS
 		Location in NAND to read U-Boot from
 
@@ -3260,6 +3482,9 @@ typically in board_init_f() and board_init_r().
 Configuration Settings:
 -----------------------
 
+- CONFIG_SYS_SUPPORT_64BIT_DATA: Defined automatically if compiled as 64-bit.
+		Optionally it can be defined to support 64-bit memory commands.
+
 - CONFIG_SYS_LONGHELP: Defined when you want long help messages included;
 		undefine this when you're short of memory.
 
@@ -3532,12 +3757,6 @@ Configuration Settings:
 	its config.mk file). If you find problems enabling this option on
 	your board please report the problem and send patches!
 
-- CONFIG_SYS_SYM_OFFSETS
-	This is set by architectures that use offsets for link symbols
-	instead of absolute values. So bss_start is obtained using an
-	offset _bss_start_ofs from CONFIG_SYS_TEXT_BASE, rather than
-	directly. You should not need to touch this setting.
-
 - CONFIG_OMAP_PLATFORM_RESET_TIME_MAX_USEC (OMAP only)
 	This is set by OMAP boards for the max time that reset should
 	be asserted. See doc/README.omap-reset-time for details on how
@@ -4266,6 +4485,9 @@ Low Level (hardware related) configuration options:
 
 		NOTE : currently only supported on AM335x platforms.
 
+- CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC:
+		Enables the RTC32K OSC on AM33xx based plattforms
+
 Freescale QE/FMAN Firmware Support:
 -----------------------------------
 
@@ -5105,6 +5327,15 @@ when your kernel is intended to use an initial ramdisk:
 	Load Address: 0x00000000
 	Entry Point:  0x00000000
 
+The "dumpimage" is a tool to disassemble images built by mkimage. Its "-i"
+option performs the converse operation of the mkimage's second form (the "-d"
+option). Given an image built by mkimage, the dumpimage extracts a "data file"
+from the image:
+
+	tools/dumpimage -i image -p position data_file
+	  -i ==> extract from the 'image' a specific 'data_file', \
+	   indexed by 'position'
+
 
 Installing a Linux Image:
 -------------------------
diff --git a/api/Makefile b/api/Makefile
index 87b8eb2bb8..3c095eedb6 100644
--- a/api/Makefile
+++ b/api/Makefile
@@ -4,21 +4,6 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)libapi.o
-
-COBJS-$(CONFIG_API) += api.o api_display.o api_net.o api_storage.o \
-		       api_platform-$(ARCH).o
-
-COBJS	:= $(COBJS-y)
-SRCS	:= $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
+obj-y += api.o api_display.o api_net.o api_storage.o
+obj-$(CONFIG_ARM) += api_platform-arm.o
+obj-$(CONFIG_PPC) += api_platform-powerpc.o
diff --git a/api/api_platform-powerpc.c b/api/api_platform-powerpc.c
index eb421d642d..f23f17501f 100644
--- a/api/api_platform-powerpc.c
+++ b/api/api_platform-powerpc.c
@@ -30,7 +30,7 @@ int platform_sys_info(struct sys_info *si)
 	si->clk_bus = gd->bus_clk;
 	si->clk_cpu = gd->cpu_clk;
 
-#if defined(CONFIG_5xx) || defined(CONFIG_8xx) || defined(CONFIG_8260) || \
+#if defined(CONFIG_5xx) || defined(CONFIG_8xx) || defined(CONFIG_MPC8260) || \
     defined(CONFIG_E500) || defined(CONFIG_MPC86xx)
 #define bi_bar	bi_immr_base
 #elif defined(CONFIG_MPC5xxx)
diff --git a/arch/arc/config.mk b/arch/arc/config.mk
new file mode 100644
index 0000000000..a3b8df779e
--- /dev/null
+++ b/arch/arc/config.mk
@@ -0,0 +1,33 @@
+#
+# Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+ifndef CONFIG_SYS_BIG_ENDIAN
+CONFIG_SYS_LITTLE_ENDIAN = 1
+endif
+
+ifdef CONFIG_SYS_LITTLE_ENDIAN
+ARC_CROSS_COMPILE := arc-buildroot-linux-uclibc-
+endif
+
+ifdef CONFIG_SYS_BIG_ENDIAN
+ARC_CROSS_COMPILE := arceb-buildroot-linux-uclibc-
+PLATFORM_LDFLAGS += -EB
+endif
+
+ifeq ($(CROSS_COMPILE),)
+CROSS_COMPILE := $(ARC_CROSS_COMPILE)
+endif
+
+PLATFORM_CPPFLAGS += -ffixed-r25 -D__ARC__ -DCONFIG_ARC -gdwarf-2
+
+# Needed for relocation
+LDFLAGS_FINAL += -pie
+
+# Load address for standalone apps
+CONFIG_STANDALONE_LOAD_ADDR ?= 0x82000000
+
+# Support generic board on ARC
+__HAVE_ARCH_GENERIC_BOARD := y
diff --git a/arch/arc/cpu/arc700/Makefile b/arch/arc/cpu/arc700/Makefile
new file mode 100644
index 0000000000..cdc5002290
--- /dev/null
+++ b/arch/arc/cpu/arc700/Makefile
@@ -0,0 +1,13 @@
+#
+# Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+extra-y	+= start.o
+
+obj-y	+= cache.o
+obj-y	+= cpu.o
+obj-y	+= interrupts.o
+obj-y	+= reset.o
+obj-y	+= timer.o
diff --git a/arch/arc/cpu/arc700/cache.c b/arch/arc/cpu/arc700/cache.c
new file mode 100644
index 0000000000..39d522d22f
--- /dev/null
+++ b/arch/arc/cpu/arc700/cache.c
@@ -0,0 +1,138 @@
+/*
+ * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <config.h>
+#include <asm/arcregs.h>
+
+/* Bit values in IC_CTRL */
+#define IC_CTRL_CACHE_DISABLE	(1 << 0)
+
+/* Bit values in DC_CTRL */
+#define DC_CTRL_CACHE_DISABLE	(1 << 0)
+#define DC_CTRL_INV_MODE_FLUSH	(1 << 6)
+#define DC_CTRL_FLUSH_STATUS	(1 << 8)
+
+int icache_status(void)
+{
+	return (read_aux_reg(ARC_AUX_IC_CTRL) & IC_CTRL_CACHE_DISABLE) !=
+	       IC_CTRL_CACHE_DISABLE;
+}
+
+void icache_enable(void)
+{
+	write_aux_reg(ARC_AUX_IC_CTRL, read_aux_reg(ARC_AUX_IC_CTRL) &
+		      ~IC_CTRL_CACHE_DISABLE);
+}
+
+void icache_disable(void)
+{
+	write_aux_reg(ARC_AUX_IC_CTRL, read_aux_reg(ARC_AUX_IC_CTRL) |
+		      IC_CTRL_CACHE_DISABLE);
+}
+
+void invalidate_icache_all(void)
+{
+#ifndef CONFIG_SYS_ICACHE_OFF
+	/* Any write to IC_IVIC register triggers invalidation of entire I$ */
+	write_aux_reg(ARC_AUX_IC_IVIC, 1);
+#endif /* CONFIG_SYS_ICACHE_OFF */
+}
+
+int dcache_status(void)
+{
+	return (read_aux_reg(ARC_AUX_DC_CTRL) & DC_CTRL_CACHE_DISABLE) !=
+		DC_CTRL_CACHE_DISABLE;
+}
+
+void dcache_enable(void)
+{
+	write_aux_reg(ARC_AUX_DC_CTRL, read_aux_reg(ARC_AUX_DC_CTRL) &
+		      ~(DC_CTRL_INV_MODE_FLUSH | DC_CTRL_CACHE_DISABLE));
+}
+
+void dcache_disable(void)
+{
+	write_aux_reg(ARC_AUX_DC_CTRL, read_aux_reg(ARC_AUX_DC_CTRL) |
+		      DC_CTRL_CACHE_DISABLE);
+}
+
+void flush_dcache_all(void)
+{
+	/* Do flush of entire cache */
+	write_aux_reg(ARC_AUX_DC_FLSH, 1);
+
+	/* Wait flush end */
+	while (read_aux_reg(ARC_AUX_DC_CTRL) & DC_CTRL_FLUSH_STATUS)
+		;
+}
+
+#ifndef CONFIG_SYS_DCACHE_OFF
+static void dcache_flush_line(unsigned addr)
+{
+#if (CONFIG_ARC_MMU_VER > 2)
+	write_aux_reg(ARC_AUX_DC_PTAG, addr);
+#endif
+	write_aux_reg(ARC_AUX_DC_FLDL, addr);
+
+	/* Wait flush end */
+	while (read_aux_reg(ARC_AUX_DC_CTRL) & DC_CTRL_FLUSH_STATUS)
+		;
+
+#ifndef CONFIG_SYS_ICACHE_OFF
+	/*
+	 * Invalidate I$ for addresses range just flushed from D$.
+	 * If we try to execute data flushed above it will be valid/correct
+	 */
+#if (CONFIG_ARC_MMU_VER > 2)
+	write_aux_reg(ARC_AUX_IC_PTAG, addr);
+#endif
+	write_aux_reg(ARC_AUX_IC_IVIL, addr);
+#endif /* CONFIG_SYS_ICACHE_OFF */
+}
+#endif /* CONFIG_SYS_DCACHE_OFF */
+
+void flush_dcache_range(unsigned long start, unsigned long end)
+{
+#ifndef CONFIG_SYS_DCACHE_OFF
+	unsigned int addr;
+
+	start = start & (~(CONFIG_SYS_CACHELINE_SIZE - 1));
+	end = end & (~(CONFIG_SYS_CACHELINE_SIZE - 1));
+
+	for (addr = start; addr <= end; addr += CONFIG_SYS_CACHELINE_SIZE)
+		dcache_flush_line(addr);
+#endif /* CONFIG_SYS_DCACHE_OFF */
+}
+
+void invalidate_dcache_range(unsigned long start, unsigned long end)
+{
+#ifndef CONFIG_SYS_DCACHE_OFF
+	unsigned int addr;
+
+	start = start & (~(CONFIG_SYS_CACHELINE_SIZE - 1));
+	end = end & (~(CONFIG_SYS_CACHELINE_SIZE - 1));
+
+	for (addr = start; addr <= end; addr += CONFIG_SYS_CACHELINE_SIZE) {
+#if (CONFIG_ARC_MMU_VER > 2)
+		write_aux_reg(ARC_AUX_DC_PTAG, addr);
+#endif
+		write_aux_reg(ARC_AUX_DC_IVDL, addr);
+	}
+#endif /* CONFIG_SYS_DCACHE_OFF */
+}
+
+void invalidate_dcache_all(void)
+{
+#ifndef CONFIG_SYS_DCACHE_OFF
+	/* Write 1 to DC_IVDC register triggers invalidation of entire D$ */
+	write_aux_reg(ARC_AUX_DC_IVDC, 1);
+#endif /* CONFIG_SYS_DCACHE_OFF */
+}
+
+void flush_cache(unsigned long start, unsigned long size)
+{
+	flush_dcache_range(start, start + size);
+}
diff --git a/arch/arc/cpu/arc700/config.mk b/arch/arc/cpu/arc700/config.mk
new file mode 100644
index 0000000000..3206ff47e3
--- /dev/null
+++ b/arch/arc/cpu/arc700/config.mk
@@ -0,0 +1,7 @@
+#
+# Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+PLATFORM_CPPFLAGS += -mA7
diff --git a/arch/arc/cpu/arc700/cpu.c b/arch/arc/cpu/arc700/cpu.c
new file mode 100644
index 0000000000..50634b860f
--- /dev/null
+++ b/arch/arc/cpu/arc700/cpu.c
@@ -0,0 +1,47 @@
+/*
+ * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arcregs.h>
+#include <asm/cache.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int arch_cpu_init(void)
+{
+#ifdef CONFIG_SYS_ICACHE_OFF
+	icache_disable();
+#else
+	icache_enable();
+	invalidate_icache_all();
+#endif
+
+	flush_dcache_all();
+#ifdef CONFIG_SYS_DCACHE_OFF
+	dcache_disable();
+#else
+	dcache_enable();
+#endif
+	timer_init();
+
+/* In simulation (ISS) "CHIPID" and "ARCNUM" are all "ff" */
+	if ((read_aux_reg(ARC_AUX_IDENTITY) & 0xffffff00) == 0xffffff00)
+		gd->arch.running_on_hw = 0;
+	else
+		gd->arch.running_on_hw = 1;
+
+	gd->cpu_clk = CONFIG_SYS_CLK_FREQ;
+	gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
+
+	return 0;
+}
+
+int arch_early_init_r(void)
+{
+	gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE;
+	gd->bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE;
+	return 0;
+}
diff --git a/arch/arc/cpu/arc700/interrupts.c b/arch/arc/cpu/arc700/interrupts.c
new file mode 100644
index 0000000000..d93a6eb547
--- /dev/null
+++ b/arch/arc/cpu/arc700/interrupts.c
@@ -0,0 +1,142 @@
+/*
+ * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arcregs.h>
+#include <asm/ptrace.h>
+
+/* Bit values in STATUS32 */
+#define E1_MASK		(1 << 1)	/* Level 1 interrupts enable */
+#define E2_MASK		(1 << 2)	/* Level 2 interrupts enable */
+
+int interrupt_init(void)
+{
+	return 0;
+}
+
+/*
+ * returns true if interrupts had been enabled before we disabled them
+ */
+int disable_interrupts(void)
+{
+	int status = read_aux_reg(ARC_AUX_STATUS32);
+	int state = (status | E1_MASK | E2_MASK) ? 1 : 0;
+
+	status &= ~(E1_MASK | E2_MASK);
+	/* STATUS32 register is updated indirectly with "FLAG" instruction */
+	__asm__("flag %0" : : "r" (status));
+	return state;
+}
+
+void enable_interrupts(void)
+{
+	unsigned int status = read_aux_reg(ARC_AUX_STATUS32);
+
+	status |= E1_MASK | E2_MASK;
+	/* STATUS32 register is updated indirectly with "FLAG" instruction */
+	__asm__("flag %0" : : "r" (status));
+}
+
+static void print_reg_file(long *reg_rev, int start_num)
+{
+	unsigned int i;
+
+	/* Print 3 registers per line */
+	for (i = start_num; i < start_num + 25; i++) {
+		printf("r%02u: 0x%08lx\t", i, (unsigned long)*reg_rev);
+		if (((i + 1) % 3) == 0)
+			printf("\n");
+
+		/* Because pt_regs has registers reversed */
+		reg_rev--;
+	}
+
+	/* Add new-line if none was inserted in the end of loop above */
+	if (((i + 1) % 3) != 0)
+		printf("\n");
+}
+
+void show_regs(struct pt_regs *regs)
+{
+	printf("RET:\t0x%08lx\nBLINK:\t0x%08lx\nSTAT32:\t0x%08lx\n",
+	       regs->ret, regs->blink, regs->status32);
+	printf("GP: 0x%08lx\t r25: 0x%08lx\t\n", regs->r26, regs->r25);
+	printf("BTA: 0x%08lx\t SP: 0x%08lx\t FP: 0x%08lx\n", regs->bta,
+	       regs->sp, regs->fp);
+	printf("LPS: 0x%08lx\tLPE: 0x%08lx\tLPC: 0x%08lx\n", regs->lp_start,
+	       regs->lp_end, regs->lp_count);
+
+	print_reg_file(&(regs->r0), 0);
+}
+
+void bad_mode(struct pt_regs *regs)
+{
+	if (regs)
+		show_regs(regs);
+
+	panic("Resetting CPU ...\n");
+}
+
+void do_memory_error(unsigned long address, struct pt_regs *regs)
+{
+	printf("Memory error exception @ 0x%lx\n", address);
+	bad_mode(regs);
+}
+
+void do_instruction_error(unsigned long address, struct pt_regs *regs)
+{
+	printf("Instruction error exception @ 0x%lx\n", address);
+	bad_mode(regs);
+}
+
+void do_machine_check_fault(unsigned long address, struct pt_regs *regs)
+{
+	printf("Machine check exception @ 0x%lx\n", address);
+	bad_mode(regs);
+}
+
+void do_interrupt_handler(void)
+{
+	printf("Interrupt fired\n");
+	bad_mode(0);
+}
+
+void do_itlb_miss(struct pt_regs *regs)
+{
+	printf("I TLB miss exception\n");
+	bad_mode(regs);
+}
+
+void do_dtlb_miss(struct pt_regs *regs)
+{
+	printf("D TLB miss exception\n");
+	bad_mode(regs);
+}
+
+void do_tlb_prot_violation(unsigned long address, struct pt_regs *regs)
+{
+	printf("TLB protection violation or misaligned access @ 0x%lx\n",
+	       address);
+	bad_mode(regs);
+}
+
+void do_privilege_violation(struct pt_regs *regs)
+{
+	printf("Privilege violation exception\n");
+	bad_mode(regs);
+}
+
+void do_trap(struct pt_regs *regs)
+{
+	printf("Trap exception\n");
+	bad_mode(regs);
+}
+
+void do_extension(struct pt_regs *regs)
+{
+	printf("Extension instruction exception\n");
+	bad_mode(regs);
+}
diff --git a/arch/arc/cpu/arc700/reset.c b/arch/arc/cpu/arc700/reset.c
new file mode 100644
index 0000000000..98ebf1d445
--- /dev/null
+++ b/arch/arc/cpu/arc700/reset.c
@@ -0,0 +1,19 @@
+/*
+ * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <command.h>
+#include <common.h>
+
+int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
+{
+	printf("Put your restart handler here\n");
+
+#ifdef DEBUG
+	/* Stop debug session here */
+	__asm__("brk");
+#endif
+	return 0;
+}
diff --git a/arch/arc/cpu/arc700/start.S b/arch/arc/cpu/arc700/start.S
new file mode 100644
index 0000000000..563513b690
--- /dev/null
+++ b/arch/arc/cpu/arc700/start.S
@@ -0,0 +1,241 @@
+/*
+ * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <asm-offsets.h>
+#include <config.h>
+#include <asm/arcregs.h>
+
+/*
+ * Note on the LD/ST addressing modes with address register write-back
+ *
+ * LD.a same as LD.aw
+ *
+ * LD.a    reg1, [reg2, x]  => Pre Incr
+ *      Eff Addr for load = [reg2 + x]
+ *
+ * LD.ab   reg1, [reg2, x]  => Post Incr
+ *      Eff Addr for load = [reg2]
+ */
+
+.macro PUSH reg
+	st.a	\reg, [%sp, -4]
+.endm
+
+.macro PUSHAX aux
+	lr	%r9, [\aux]
+	PUSH	%r9
+.endm
+
+.macro  SAVE_R1_TO_R24
+	PUSH	%r1
+	PUSH	%r2
+	PUSH	%r3
+	PUSH	%r4
+	PUSH	%r5
+	PUSH	%r6
+	PUSH	%r7
+	PUSH	%r8
+	PUSH	%r9
+	PUSH	%r10
+	PUSH	%r11
+	PUSH	%r12
+	PUSH	%r13
+	PUSH	%r14
+	PUSH	%r15
+	PUSH	%r16
+	PUSH	%r17
+	PUSH	%r18
+	PUSH	%r19
+	PUSH	%r20
+	PUSH	%r21
+	PUSH	%r22
+	PUSH	%r23
+	PUSH	%r24
+.endm
+
+.macro SAVE_ALL_SYS
+
+	st	%r0, [%sp]
+	lr	%r0, [%ecr]
+	st	%r0, [%sp, 8]	/* ECR */
+	st	%sp, [%sp, 4]
+
+	SAVE_R1_TO_R24
+	PUSH	%r25
+	PUSH	%gp
+	PUSH	%fp
+	PUSH	%blink
+	PUSHAX	%eret
+	PUSHAX	%erstatus
+	PUSH	%lp_count
+	PUSHAX	%lp_end
+	PUSHAX	%lp_start
+	PUSHAX	%erbta
+.endm
+
+.align 4
+.globl _start
+_start:
+	/* Critical system events */
+	j	reset			/* 0 - 0x000 */
+	j	memory_error		/* 1 - 0x008 */
+	j	instruction_error	/* 2 - 0x010 */
+
+	/* Device interrupts */
+.rept	29
+	j	interrupt_handler	/* 3:31 - 0x018:0xF8 */
+.endr
+	/* Exceptions */
+	j	EV_MachineCheck		/* 0x100, Fatal Machine check  (0x20) */
+	j	EV_TLBMissI		/* 0x108, Intruction TLB miss  (0x21) */
+	j	EV_TLBMissD		/* 0x110, Data TLB miss        (0x22) */
+	j	EV_TLBProtV		/* 0x118, Protection Violation (0x23)
+							or Misaligned Access  */
+	j	EV_PrivilegeV		/* 0x120, Privilege Violation  (0x24) */
+	j	EV_Trap			/* 0x128, Trap exception       (0x25) */
+	j	EV_Extension		/* 0x130, Extn Intruction Excp (0x26) */
+
+memory_error:
+	SAVE_ALL_SYS
+	lr	%r0, [%efa]
+	mov	%r1, %sp
+	j	do_memory_error
+
+instruction_error:
+	SAVE_ALL_SYS
+	lr	%r0, [%efa]
+	mov	%r1, %sp
+	j	do_instruction_error
+
+interrupt_handler:
+	/* Todo - save and restore CPU context when interrupts will be in use */
+	bl	do_interrupt_handler
+	rtie
+
+EV_MachineCheck:
+	SAVE_ALL_SYS
+	lr	%r0, [%efa]
+	mov	%r1, %sp
+	j	do_machine_check_fault
+
+EV_TLBMissI:
+	SAVE_ALL_SYS
+	mov	%r0, %sp
+	j	do_itlb_miss
+
+EV_TLBMissD:
+	SAVE_ALL_SYS
+	mov	%r0, %sp
+	j	do_dtlb_miss
+
+EV_TLBProtV:
+	SAVE_ALL_SYS
+	lr	%r0, [%efa]
+	mov	%r1, %sp
+	j	do_tlb_prot_violation
+
+EV_PrivilegeV:
+	SAVE_ALL_SYS
+	mov	%r0, %sp
+	j	do_privilege_violation
+
+EV_Trap:
+	SAVE_ALL_SYS
+	mov	%r0, %sp
+	j	do_trap
+
+EV_Extension:
+	SAVE_ALL_SYS
+	mov	%r0, %sp
+	j	do_extension
+
+
+reset:
+	/* Setup interrupt vector base that matches "__text_start" */
+	sr	__text_start, [ARC_AUX_INTR_VEC_BASE]
+
+	/* Setup stack pointer */
+	mov	%sp, CONFIG_SYS_INIT_SP_ADDR
+	mov	%fp, %sp
+
+	/* Clear bss */
+	mov	%r0, __bss_start
+	mov	%r1, __bss_end
+
+clear_bss:
+	st.ab	0, [%r0, 4]
+	brlt	%r0, %r1, clear_bss
+
+	/* Zero the one and only argument of "board_init_f" */
+	mov_s	%r0, 0
+	j	board_init_f
+
+/*
+ * void relocate_code (addr_sp, gd, addr_moni)
+ *
+ * This "function" does not return, instead it continues in RAM
+ * after relocating the monitor code.
+ *
+ * r0 = start_addr_sp
+ * r1 = new__gd
+ * r2 = relocaddr
+ */
+.align 4
+.globl	relocate_code
+relocate_code:
+	/*
+	 * r0-r12 might be clobbered by C functions
+	 * so we use r13-r16 for storage here
+	 */
+	mov	%r13, %r0		/* save addr_sp */
+	mov	%r14, %r1		/* save addr of gd */
+	mov	%r15, %r2		/* save addr of destination */
+
+	mov	%r16, %r2		/* %r9 - relocation offset */
+	sub	%r16, %r16, __image_copy_start
+
+/* Set up the stack */
+stack_setup:
+	mov	%sp, %r13
+	mov	%fp, %sp
+
+/* Check if monitor is loaded right in place for relocation */
+	mov	%r0, __image_copy_start
+	cmp	%r0, %r15		/* skip relocation if code loaded */
+	bz	do_board_init_r		/* in target location already */
+
+/* Copy data (__image_copy_start - __image_copy_end) to new location */
+	mov	%r1, %r15
+	mov	%r2, __image_copy_end
+	sub	%r2, %r2, %r0		/* r3 <- amount of bytes to copy */
+	asr	%r2, %r2, 2		/* r3 <- amount of words to copy */
+	mov	%lp_count, %r2
+	lp	copy_end
+	ld.ab	%r2,[%r0,4]
+	st.ab	%r2,[%r1,4]
+copy_end:
+
+/* Fix relocations related issues */
+	bl	do_elf_reloc_fixups
+#ifndef CONFIG_SYS_ICACHE_OFF
+	bl	invalidate_icache_all
+#endif
+#ifndef CONFIG_SYS_DCACHE_OFF
+	bl	flush_dcache_all
+#endif
+
+/* Update position of intterupt vector table */
+	lr	%r0, [ARC_AUX_INTR_VEC_BASE]	/* Read current position */
+	add	%r0, %r0, %r16			/* Update address */
+	sr	%r0, [ARC_AUX_INTR_VEC_BASE]	/* Write new position */
+
+do_board_init_r:
+/* Prepare for exection of "board_init_r" in relocated monitor */
+	mov	%r2, board_init_r	/* old address of "board_init_r()" */
+	add	%r2, %r2, %r16		/* new address of "board_init_r()" */
+	mov	%r0, %r14		/* 1-st parameter: gd_t */
+	mov	%r1, %r15		/* 2-nd parameter: dest_addr */
+	j	[%r2]
diff --git a/arch/arc/cpu/arc700/timer.c b/arch/arc/cpu/arc700/timer.c
new file mode 100644
index 0000000000..a0acbbc01a
--- /dev/null
+++ b/arch/arc/cpu/arc700/timer.c
@@ -0,0 +1,24 @@
+/*
+ * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <asm/arcregs.h>
+
+#define NH_MODE	(1 << 1)	/* Disable timer if CPU is halted */
+
+int timer_init(void)
+{
+	write_aux_reg(ARC_AUX_TIMER0_CTRL, NH_MODE);
+	/* Set max value for counter/timer */
+	write_aux_reg(ARC_AUX_TIMER0_LIMIT, 0xffffffff);
+	/* Set initial count value and restart counter/timer */
+	write_aux_reg(ARC_AUX_TIMER0_CNT, 0);
+	return 0;
+}
+
+unsigned long timer_read_counter(void)
+{
+	return read_aux_reg(ARC_AUX_TIMER0_CNT);
+}
diff --git a/arch/arc/cpu/arc700/u-boot.lds b/arch/arc/cpu/arc700/u-boot.lds
new file mode 100644
index 0000000000..2d01b21b36
--- /dev/null
+++ b/arch/arc/cpu/arc700/u-boot.lds
@@ -0,0 +1,72 @@
+/*
+ * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+OUTPUT_FORMAT("elf32-littlearc", "elf32-littlearc", "elf32-littlearc")
+OUTPUT_ARCH(arc)
+ENTRY(_start)
+SECTIONS
+{
+	. = ALIGN(4);
+	.text :	{
+		*(.__text_start)
+		*(.__image_copy_start)
+		CPUDIR/start.o (.text*)
+		*(.text*)
+	}
+
+	. = ALIGN(4);
+	.text_end :
+	{
+		*(.__text_end)
+	}
+
+	. = ALIGN(4);
+	.rodata : {
+		*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
+	}
+
+	. = ALIGN(4);
+	.data : {
+		*(.data*)
+	}
+
+	. = ALIGN(4);
+	.u_boot_list : {
+		KEEP(*(SORT(.u_boot_list*)));
+	}
+
+	. = ALIGN(4);
+	.rel_dyn_start : {
+		*(.__rel_dyn_start)
+	}
+
+	.rela.dyn : {
+		*(.rela.dyn)
+	}
+
+	.rel_dyn_end : {
+		*(.__rel_dyn_end)
+	}
+
+	. = ALIGN(4);
+	.bss_start : {
+		*(.__bss_start);
+	}
+
+	.bss : {
+		*(.bss*)
+	}
+
+	.bss_end : {
+		*(.__bss_end);
+	}
+
+	. = ALIGN(4);
+	.image_copy_end : {
+		*(.__image_copy_end)
+		*(.__init_end)
+	}
+}
diff --git a/arch/arc/include/asm/arcregs.h b/arch/arc/include/asm/arcregs.h
new file mode 100644
index 0000000000..5d48d11bab
--- /dev/null
+++ b/arch/arc/include/asm/arcregs.h
@@ -0,0 +1,55 @@
+/*
+ * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _ASM_ARC_ARCREGS_H
+#define _ASM_ARC_ARCREGS_H
+
+/*
+ * ARC architecture has additional address space - auxiliary registers.
+ * These registers are mostly used for configuration purposes.
+ * These registers are not memory mapped and special commands are used for
+ * access: "lr"/"sr".
+ */
+
+#define ARC_AUX_IDENTITY	0x04
+#define ARC_AUX_STATUS32	0x0a
+
+/* Instruction cache related auxiliary registers */
+#define ARC_AUX_IC_IVIC		0x10
+#define ARC_AUX_IC_CTRL		0x11
+#define ARC_AUX_IC_IVIL		0x19
+#if (CONFIG_ARC_MMU_VER > 2)
+#define ARC_AUX_IC_PTAG		0x1E
+#endif
+
+/* Timer related auxiliary registers */
+#define ARC_AUX_TIMER0_CNT	0x21	/* Timer 0 count */
+#define ARC_AUX_TIMER0_CTRL	0x22	/* Timer 0 control */
+#define ARC_AUX_TIMER0_LIMIT	0x23	/* Timer 0 limit */
+
+#define ARC_AUX_INTR_VEC_BASE	0x25
+
+/* Data cache related auxiliary registers */
+#define ARC_AUX_DC_IVDC		0x47
+#define ARC_AUX_DC_CTRL		0x48
+
+#define ARC_AUX_DC_IVDL		0x4A
+#define ARC_AUX_DC_FLSH		0x4B
+#define ARC_AUX_DC_FLDL		0x4C
+#if (CONFIG_ARC_MMU_VER > 2)
+#define ARC_AUX_DC_PTAG		0x5C
+#endif
+
+#ifndef __ASSEMBLY__
+/* Accessors for auxiliary registers */
+#define read_aux_reg(reg)	__builtin_arc_lr(reg)
+
+/* gcc builtin sr needs reg param to be long immediate */
+#define write_aux_reg(reg_immed, val)		\
+		__builtin_arc_sr((unsigned int)val, reg_immed)
+#endif /* __ASSEMBLY__ */
+
+#endif /* _ASM_ARC_ARCREGS_H */
diff --git a/arch/arc/include/asm/bitops.h b/arch/arc/include/asm/bitops.h
new file mode 100644
index 0000000000..85721aaee3
--- /dev/null
+++ b/arch/arc/include/asm/bitops.h
@@ -0,0 +1,19 @@
+/*
+ * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __ASM_ARC_BITOPS_H
+#define __ASM_ARC_BITOPS_H
+
+/*
+ * hweightN: returns the hamming weight (i.e. the number
+ * of bits set) of a N-bit word
+ */
+
+#define hweight32(x) generic_hweight32(x)
+#define hweight16(x) generic_hweight16(x)
+#define hweight8(x) generic_hweight8(x)
+
+#endif /* __ASM_ARC_BITOPS_H */
diff --git a/arch/arc/include/asm/byteorder.h b/arch/arc/include/asm/byteorder.h
new file mode 100644
index 0000000000..2fa9776ca5
--- /dev/null
+++ b/arch/arc/include/asm/byteorder.h
@@ -0,0 +1,23 @@
+/*
+ * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __ASM_ARC_BYTEORDER_H
+#define __ASM_ARC_BYTEORDER_H
+
+#include <asm/types.h>
+
+#if defined(__GNUC__) && !defined(__STRICT_ANSI__)
+	#define __BYTEORDER_HAS_U64__
+	#define __SWAB_64_THRU_32__
+#endif
+
+#ifdef __LITTLE_ENDIAN__
+	#include <linux/byteorder/little_endian.h>
+#else
+	#include <linux/byteorder/big_endian.h>
+#endif	/* CONFIG_SYS_BIG_ENDIAN */
+
+#endif	/* ASM_ARC_BYTEORDER_H */
diff --git a/arch/arc/include/asm/cache.h b/arch/arc/include/asm/cache.h
new file mode 100644
index 0000000000..16e7568ef0
--- /dev/null
+++ b/arch/arc/include/asm/cache.h
@@ -0,0 +1,23 @@
+/*
+ * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __ASM_ARC_CACHE_H
+#define __ASM_ARC_CACHE_H
+
+#include <config.h>
+
+/*
+ * The current upper bound for ARC L1 data cache line sizes is 128 bytes.
+ * We use that value for aligning DMA buffers unless the board config has
+ * specified an alternate cache line size.
+ */
+#ifdef CONFIG_SYS_CACHELINE_SIZE
+#define ARCH_DMA_MINALIGN	CONFIG_SYS_CACHELINE_SIZE
+#else
+#define ARCH_DMA_MINALIGN	128
+#endif
+
+#endif /* __ASM_ARC_CACHE_H */
diff --git a/arch/arc/include/asm/config.h b/arch/arc/include/asm/config.h
new file mode 100644
index 0000000000..5761def1e7
--- /dev/null
+++ b/arch/arc/include/asm/config.h
@@ -0,0 +1,12 @@
+/*
+ * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __ASM_ARC_CONFIG_H_
+#define __ASM_ARC_CONFIG_H_
+
+#define CONFIG_LMB
+
+#endif /*__ASM_ARC_CONFIG_H_ */
diff --git a/arch/arc/include/asm/errno.h b/arch/arc/include/asm/errno.h
new file mode 100644
index 0000000000..4c82b503d9
--- /dev/null
+++ b/arch/arc/include/asm/errno.h
@@ -0,0 +1 @@
+#include <asm-generic/errno.h>
diff --git a/arch/arc/include/asm/global_data.h b/arch/arc/include/asm/global_data.h
new file mode 100644
index 0000000000..d644e80586
--- /dev/null
+++ b/arch/arc/include/asm/global_data.h
@@ -0,0 +1,19 @@
+/*
+ * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef	__ASM_ARC_GLOBAL_DATA_H
+#define __ASM_ARC_GLOBAL_DATA_H
+
+/* Architecture-specific global data */
+struct arch_global_data {
+	int running_on_hw;
+};
+
+#include <asm-generic/global_data.h>
+
+#define DECLARE_GLOBAL_DATA_PTR		register volatile gd_t *gd asm ("r25")
+
+#endif /* __ASM_ARC_GLOBAL_DATA_H */
diff --git a/arch/arc/include/asm/io.h b/arch/arc/include/asm/io.h
new file mode 100644
index 0000000000..24b7337308
--- /dev/null
+++ b/arch/arc/include/asm/io.h
@@ -0,0 +1,218 @@
+/*
+ * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __ASM_ARC_IO_H
+#define __ASM_ARC_IO_H
+
+#include <linux/types.h>
+#include <asm/byteorder.h>
+
+static inline void sync(void)
+{
+	/* Not yet implemented */
+}
+
+static inline u8 __raw_readb(const volatile void __iomem *addr)
+{
+	u8 b;
+
+	__asm__ __volatile__("ldb%U1	%0, %1\n"
+			     : "=r" (b)
+			     : "m" (*(volatile u8 __force *)addr)
+			     : "memory");
+	return b;
+}
+
+static inline u16 __raw_readw(const volatile void __iomem *addr)
+{
+	u16 s;
+
+	__asm__ __volatile__("ldw%U1	%0, %1\n"
+			     : "=r" (s)
+			     : "m" (*(volatile u16 __force *)addr)
+			     : "memory");
+	return s;
+}
+
+static inline u32 __raw_readl(const volatile void __iomem *addr)
+{
+	u32 w;
+
+	__asm__ __volatile__("ld%U1	%0, %1\n"
+			     : "=r" (w)
+			     : "m" (*(volatile u32 __force *)addr)
+			     : "memory");
+	return w;
+}
+
+#define readb __raw_readb
+
+static inline u16 readw(const volatile void __iomem *addr)
+{
+	return __le16_to_cpu(__raw_readw(addr));
+}
+
+static inline u32 readl(const volatile void __iomem *addr)
+{
+	return __le32_to_cpu(__raw_readl(addr));
+}
+
+static inline void __raw_writeb(u8 b, volatile void __iomem *addr)
+{
+	__asm__ __volatile__("stb%U1	%0, %1\n"
+			     :
+			     : "r" (b), "m" (*(volatile u8 __force *)addr)
+			     : "memory");
+}
+
+static inline void __raw_writew(u16 s, volatile void __iomem *addr)
+{
+	__asm__ __volatile__("stw%U1	%0, %1\n"
+			     :
+			     : "r" (s), "m" (*(volatile u16 __force *)addr)
+			     : "memory");
+}
+
+static inline void __raw_writel(u32 w, volatile void __iomem *addr)
+{
+	__asm__ __volatile__("st%U1	%0, %1\n"
+			     :
+			     : "r" (w), "m" (*(volatile u32 __force *)addr)
+			     : "memory");
+}
+
+#define writeb __raw_writeb
+#define writew(b, addr) __raw_writew(__cpu_to_le16(b), addr)
+#define writel(b, addr) __raw_writel(__cpu_to_le32(b), addr)
+
+static inline int __raw_readsb(unsigned int addr, void *data, int bytelen)
+{
+	__asm__ __volatile__ ("1:ld.di	r8, [r0]\n"
+			      "sub.f	r2, r2, 1\n"
+			      "bnz.d	1b\n"
+			      "stb.ab	r8, [r1, 1]\n"
+			      :
+			      : "r" (addr), "r" (data), "r" (bytelen)
+			      : "r8");
+	return bytelen;
+}
+
+static inline int __raw_readsw(unsigned int addr, void *data, int wordlen)
+{
+	__asm__ __volatile__ ("1:ld.di	r8, [r0]\n"
+			      "sub.f	r2, r2, 1\n"
+			      "bnz.d	1b\n"
+			      "stw.ab	r8, [r1, 2]\n"
+			      :
+			      : "r" (addr), "r" (data), "r" (wordlen)
+			      : "r8");
+	return wordlen;
+}
+
+static inline int __raw_readsl(unsigned int addr, void *data, int longlen)
+{
+	__asm__ __volatile__ ("1:ld.di	r8, [r0]\n"
+			      "sub.f	r2, r2, 1\n"
+			      "bnz.d	1b\n"
+			      "st.ab	r8, [r1, 4]\n"
+			      :
+			      : "r" (addr), "r" (data), "r" (longlen)
+			      : "r8");
+	return longlen;
+}
+
+static inline int __raw_writesb(unsigned int addr, void *data, int bytelen)
+{
+	__asm__ __volatile__ ("1:ldb.ab	r8, [r1, 1]\n"
+			      "sub.f	r2, r2, 1\n"
+			      "bnz.d	1b\n"
+			      "st.di	r8, [r0, 0]\n"
+			      :
+			      : "r" (addr), "r" (data), "r" (bytelen)
+			      : "r8");
+	return bytelen;
+}
+
+static inline int __raw_writesw(unsigned int addr, void *data, int wordlen)
+{
+	__asm__ __volatile__ ("1:ldw.ab	r8, [r1, 2]\n"
+			      "sub.f	r2, r2, 1\n"
+			      "bnz.d	1b\n"
+			      "st.ab.di	r8, [r0, 0]\n"
+			      :
+			      : "r" (addr), "r" (data), "r" (wordlen)
+			      : "r8");
+	return wordlen;
+}
+
+static inline int __raw_writesl(unsigned int addr, void *data, int longlen)
+{
+	__asm__ __volatile__ ("1:ld.ab	r8, [r1, 4]\n"
+			      "sub.f	r2, r2, 1\n"
+			      "bnz.d	1b\n"
+			      "st.ab.di	r8, [r0, 0]\n"
+			      :
+			      : "r" (addr), "r" (data), "r" (longlen)
+			      : "r8");
+	return longlen;
+}
+
+#define out_arch(type, endian, a, v)	__raw_write##type(cpu_to_##endian(v), a)
+#define in_arch(type, endian, a)	endian##_to_cpu(__raw_read##type(a))
+
+#define out_le32(a, v)	out_arch(l, le32, a, v)
+#define out_le16(a, v)	out_arch(w, le16, a, v)
+
+#define in_le32(a)	in_arch(l, le32, a)
+#define in_le16(a)	in_arch(w, le16, a)
+
+#define out_be32(a, v)	out_arch(l, be32, a, v)
+#define out_be16(a, v)	out_arch(w, be16, a, v)
+
+#define in_be32(a)	in_arch(l, be32, a)
+#define in_be16(a)	in_arch(w, be16, a)
+
+#define out_8(a, v)	__raw_writeb(v, a)
+#define in_8(a)		__raw_readb(a)
+
+/*
+ * Clear and set bits in one shot. These macros can be used to clear and
+ * set multiple bits in a register using a single call. These macros can
+ * also be used to set a multiple-bit bit pattern using a mask, by
+ * specifying the mask in the 'clear' parameter and the new bit pattern
+ * in the 'set' parameter.
+ */
+
+#define clrbits(type, addr, clear) \
+	out_##type((addr), in_##type(addr) & ~(clear))
+
+#define setbits(type, addr, set) \
+	out_##type((addr), in_##type(addr) | (set))
+
+#define clrsetbits(type, addr, clear, set) \
+	out_##type((addr), (in_##type(addr) & ~(clear)) | (set))
+
+#define clrbits_be32(addr, clear) clrbits(be32, addr, clear)
+#define setbits_be32(addr, set) setbits(be32, addr, set)
+#define clrsetbits_be32(addr, clear, set) clrsetbits(be32, addr, clear, set)
+
+#define clrbits_le32(addr, clear) clrbits(le32, addr, clear)
+#define setbits_le32(addr, set) setbits(le32, addr, set)
+#define clrsetbits_le32(addr, clear, set) clrsetbits(le32, addr, clear, set)
+
+#define clrbits_be16(addr, clear) clrbits(be16, addr, clear)
+#define setbits_be16(addr, set) setbits(be16, addr, set)
+#define clrsetbits_be16(addr, clear, set) clrsetbits(be16, addr, clear, set)
+
+#define clrbits_le16(addr, clear) clrbits(le16, addr, clear)
+#define setbits_le16(addr, set) setbits(le16, addr, set)
+#define clrsetbits_le16(addr, clear, set) clrsetbits(le16, addr, clear, set)
+
+#define clrbits_8(addr, clear) clrbits(8, addr, clear)
+#define setbits_8(addr, set) setbits(8, addr, set)
+#define clrsetbits_8(addr, clear, set) clrsetbits(8, addr, clear, set)
+
+#endif	/* __ASM_ARC_IO_H */
diff --git a/arch/arc/include/asm/posix_types.h b/arch/arc/include/asm/posix_types.h
new file mode 100644
index 0000000000..20415f0705
--- /dev/null
+++ b/arch/arc/include/asm/posix_types.h
@@ -0,0 +1,39 @@
+/*
+ * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __ASM_ARC_POSIX_TYPES_H
+#define __ASM_ARC_POSIX_TYPES_H
+
+typedef unsigned short		__kernel_dev_t;
+typedef unsigned long		__kernel_ino_t;
+typedef unsigned short		__kernel_mode_t;
+typedef unsigned short		__kernel_nlink_t;
+typedef long			__kernel_off_t;
+typedef int			__kernel_pid_t;
+typedef unsigned short		__kernel_ipc_pid_t;
+typedef unsigned short		__kernel_uid_t;
+typedef unsigned short		__kernel_gid_t;
+typedef unsigned int		__kernel_size_t;
+typedef int			__kernel_ssize_t;
+typedef int			__kernel_ptrdiff_t;
+typedef long			__kernel_time_t;
+typedef long			__kernel_suseconds_t;
+typedef long			__kernel_clock_t;
+typedef int			__kernel_daddr_t;
+typedef char			*__kernel_caddr_t;
+typedef unsigned short		__kernel_uid16_t;
+typedef unsigned short		__kernel_gid16_t;
+typedef unsigned int		__kernel_uid32_t;
+typedef unsigned int		__kernel_gid32_t;
+
+typedef unsigned short		__kernel_old_uid_t;
+typedef unsigned short		__kernel_old_gid_t;
+
+#ifdef __GNUC__
+typedef long long		__kernel_loff_t;
+#endif
+
+#endif	/* __ASM_ARC_POSIX_TYPES_H */
diff --git a/arch/arc/include/asm/ptrace.h b/arch/arc/include/asm/ptrace.h
new file mode 100644
index 0000000000..8f73b31c10
--- /dev/null
+++ b/arch/arc/include/asm/ptrace.h
@@ -0,0 +1,50 @@
+/*
+ * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __ASM_ARC_PTRACE_H
+#define __ASM_ARC_PTRACE_H
+
+struct pt_regs {
+	long bta;
+	long lp_start;
+	long lp_end;
+	long lp_count;
+	long status32;
+	long ret;
+	long blink;
+	long fp;
+	long r26;	/* gp */
+	long r25;
+	long r24;
+	long r23;
+	long r22;
+	long r21;
+	long r20;
+	long r19;
+	long r18;
+	long r17;
+	long r16;
+	long r15;
+	long r14;
+	long r13;
+	long r12;
+	long r11;
+	long r10;
+	long r9;
+	long r8;
+	long r7;
+	long r6;
+	long r5;
+	long r4;
+	long r3;
+	long r2;
+	long r1;
+	long r0;
+	long sp;
+	long ecr;
+};
+
+#endif /* __ASM_ARC_PTRACE_H */
diff --git a/arch/arc/include/asm/sections.h b/arch/arc/include/asm/sections.h
new file mode 100644
index 0000000000..18484a17f2
--- /dev/null
+++ b/arch/arc/include/asm/sections.h
@@ -0,0 +1,14 @@
+/*
+ * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __ASM_ARC_SECTIONS_H
+#define __ASM_ARC_SECTIONS_H
+
+#include <asm-generic/sections.h>
+
+extern ulong __text_end;
+
+#endif /* __ASM_ARC_SECTIONS_H */
diff --git a/arch/arc/include/asm/string.h b/arch/arc/include/asm/string.h
new file mode 100644
index 0000000000..909129c333
--- /dev/null
+++ b/arch/arc/include/asm/string.h
@@ -0,0 +1,27 @@
+/*
+ * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __ASM_ARC_STRING_H
+#define __ASM_ARC_STRING_H
+
+#define __HAVE_ARCH_MEMSET
+#define __HAVE_ARCH_MEMCPY
+#define __HAVE_ARCH_MEMCMP
+#define __HAVE_ARCH_STRCHR
+#define __HAVE_ARCH_STRCPY
+#define __HAVE_ARCH_STRCMP
+#define __HAVE_ARCH_STRLEN
+
+extern void *memset(void *ptr, int, __kernel_size_t);
+extern void *memcpy(void *, const void *, __kernel_size_t);
+extern void memzero(void *ptr, __kernel_size_t n);
+extern int memcmp(const void *, const void *, __kernel_size_t);
+extern char *strchr(const char *s, int c);
+extern char *strcpy(char *dest, const char *src);
+extern int strcmp(const char *cs, const char *ct);
+extern __kernel_size_t strlen(const char *);
+
+#endif /* __ASM_ARC_STRING_H */
diff --git a/arch/arc/include/asm/types.h b/arch/arc/include/asm/types.h
new file mode 100644
index 0000000000..24eeb76bd6
--- /dev/null
+++ b/arch/arc/include/asm/types.h
@@ -0,0 +1,55 @@
+/*
+ * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __ASM_ARC_TYPES_H
+#define __ASM_ARC_TYPES_H
+
+typedef unsigned short umode_t;
+
+/*
+ * __xx is ok: it doesn't pollute the POSIX namespace. Use these in the
+ * header files exported to user space
+ */
+
+typedef __signed__ char __s8;
+typedef unsigned char __u8;
+
+typedef __signed__ short __s16;
+typedef unsigned short __u16;
+
+typedef __signed__ int __s32;
+typedef unsigned int __u32;
+
+#if defined(__GNUC__) && !defined(__STRICT_ANSI__)
+typedef __signed__ long long __s64;
+typedef unsigned long long __u64;
+#endif
+
+/*
+ * These aren't exported outside the kernel to avoid name space clashes
+ */
+typedef signed char s8;
+typedef unsigned char u8;
+
+typedef signed short s16;
+typedef unsigned short u16;
+
+typedef signed int s32;
+typedef unsigned int u32;
+
+typedef signed long long s64;
+typedef unsigned long long u64;
+
+#define BITS_PER_LONG 32
+
+/* Dma addresses are 32-bits wide. */
+
+typedef u32 dma_addr_t;
+
+typedef unsigned long phys_addr_t;
+typedef unsigned long phys_size_t;
+
+#endif /* __ASM_ARC_TYPES_H */
diff --git a/arch/arc/include/asm/u-boot-arc.h b/arch/arc/include/asm/u-boot-arc.h
new file mode 100644
index 0000000000..0c0e8e661d
--- /dev/null
+++ b/arch/arc/include/asm/u-boot-arc.h
@@ -0,0 +1,12 @@
+/*
+ * Copyright (C) 2014 Synopsys, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __ASM_ARC_U_BOOT_ARC_H__
+#define __ASM_ARC_U_BOOT_ARC_H__
+
+int arch_early_init_r(void);
+
+#endif	/* __ASM_ARC_U_BOOT_ARC_H__ */
diff --git a/arch/arc/include/asm/u-boot.h b/arch/arc/include/asm/u-boot.h
new file mode 100644
index 0000000000..e354edf95d
--- /dev/null
+++ b/arch/arc/include/asm/u-boot.h
@@ -0,0 +1,15 @@
+/*
+ * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __ASM_ARC_U_BOOT_H__
+#define __ASM_ARC_U_BOOT_H__
+
+#include <asm-generic/u-boot.h>
+
+/* For image.h:image_check_target_arch() */
+#define IH_ARCH_DEFAULT IH_ARCH_ARC
+
+#endif	/* __ASM_ARC_U_BOOT_H__ */
diff --git a/arch/arc/include/asm/unaligned.h b/arch/arc/include/asm/unaligned.h
new file mode 100644
index 0000000000..6cecbbb211
--- /dev/null
+++ b/arch/arc/include/asm/unaligned.h
@@ -0,0 +1 @@
+#include <asm-generic/unaligned.h>
diff --git a/arch/arc/lib/Makefile b/arch/arc/lib/Makefile
new file mode 100644
index 0000000000..7675f855d5
--- /dev/null
+++ b/arch/arc/lib/Makefile
@@ -0,0 +1,16 @@
+#
+# Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y += sections.o
+obj-y += relocate.o
+obj-y += strchr-700.o
+obj-y += strcmp.o
+obj-y += strcpy-700.o
+obj-y += strlen.o
+obj-y += memcmp.o
+obj-y += memcpy-700.o
+obj-y += memset.o
+obj-$(CONFIG_CMD_BOOTM) += bootm.o
diff --git a/arch/arc/lib/bootm.c b/arch/arc/lib/bootm.c
new file mode 100644
index 0000000000..d185a50bd3
--- /dev/null
+++ b/arch/arc/lib/bootm.c
@@ -0,0 +1,106 @@
+/*
+ * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static ulong get_sp(void)
+{
+	ulong ret;
+
+	asm("mov %0, sp" : "=r"(ret) : );
+	return ret;
+}
+
+void arch_lmb_reserve(struct lmb *lmb)
+{
+	ulong sp;
+
+	/*
+	 * Booting a (Linux) kernel image
+	 *
+	 * Allocate space for command line and board info - the
+	 * address should be as high as possible within the reach of
+	 * the kernel (see CONFIG_SYS_BOOTMAPSZ settings), but in unused
+	 * memory, which means far enough below the current stack
+	 * pointer.
+	 */
+	sp = get_sp();
+	debug("## Current stack ends at 0x%08lx ", sp);
+
+	/* adjust sp by 4K to be safe */
+	sp -= 4096;
+	lmb_reserve(lmb, sp, (CONFIG_SYS_SDRAM_BASE + gd->ram_size - sp));
+}
+
+static int cleanup_before_linux(void)
+{
+	disable_interrupts();
+	flush_dcache_all();
+	invalidate_icache_all();
+
+	return 0;
+}
+
+/* Subcommand: PREP */
+static void boot_prep_linux(bootm_headers_t *images)
+{
+	if (image_setup_linux(images))
+		hang();
+}
+
+/* Subcommand: GO */
+static void boot_jump_linux(bootm_headers_t *images, int flag)
+{
+	void (*kernel_entry)(int zero, int arch, uint params);
+	unsigned int r0, r2;
+	int fake = (flag & BOOTM_STATE_OS_FAKE_GO);
+
+	kernel_entry = (void (*)(int, int, uint))images->ep;
+
+	debug("## Transferring control to Linux (at address %08lx)...\n",
+	      (ulong) kernel_entry);
+	bootstage_mark(BOOTSTAGE_ID_RUN_OS);
+
+	printf("\nStarting kernel ...%s\n\n", fake ?
+	       "(fake run for tracing)" : "");
+	bootstage_mark_name(BOOTSTAGE_ID_BOOTM_HANDOFF, "start_kernel");
+
+	cleanup_before_linux();
+
+	if (IMAGE_ENABLE_OF_LIBFDT && images->ft_len) {
+		r0 = 2;
+		r2 = (unsigned int)images->ft_addr;
+	} else {
+		r0 = 1;
+		r2 = (unsigned int)getenv("bootargs");
+	}
+
+	if (!fake)
+		kernel_entry(r0, 0, r2);
+}
+
+int do_bootm_linux(int flag, int argc, char *argv[], bootm_headers_t *images)
+{
+	/* No need for those on ARC */
+	if ((flag & BOOTM_STATE_OS_BD_T) || (flag & BOOTM_STATE_OS_CMDLINE))
+		return -1;
+
+	if (flag & BOOTM_STATE_OS_PREP) {
+		boot_prep_linux(images);
+		return 0;
+	}
+
+	if (flag & (BOOTM_STATE_OS_GO | BOOTM_STATE_OS_FAKE_GO)) {
+		boot_jump_linux(images, flag);
+		return 0;
+	}
+
+	boot_prep_linux(images);
+	boot_jump_linux(images, flag);
+	return 0;
+}
diff --git a/arch/arc/lib/memcmp.S b/arch/arc/lib/memcmp.S
new file mode 100644
index 0000000000..fa5aac5f67
--- /dev/null
+++ b/arch/arc/lib/memcmp.S
@@ -0,0 +1,121 @@
+/*
+ * Copyright (C) 2004, 2007-2010, 2011-2014 Synopsys, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifdef __LITTLE_ENDIAN__
+#define WORD2 r2
+#define SHIFT r3
+#else /* __BIG_ENDIAN__ */
+#define WORD2 r3
+#define SHIFT r2
+#endif /* _ENDIAN__ */
+
+.global memcmp
+.align 4
+memcmp:
+	or	%r12, %r0, %r1
+	asl_s	%r12, %r12, 30
+	sub	%r3, %r2, 1
+	brls	%r2, %r12, .Lbytewise
+	ld	%r4, [%r0, 0]
+	ld	%r5, [%r1, 0]
+	lsr.f	%lp_count, %r3, 3
+	lpne	.Loop_end
+	ld_s	WORD2, [%r0, 4]
+	ld_s	%r12, [%r1, 4]
+	brne	%r4, %r5, .Leven
+	ld.a	%r4, [%r0, 8]
+	ld.a	%r5, [%r1, 8]
+	brne	WORD2, %r12, .Lodd
+.Loop_end:
+	asl_s	SHIFT, SHIFT, 3
+	bhs_s	.Last_cmp
+	brne	%r4, %r5, .Leven
+	ld	%r4, [%r0, 4]
+	ld	%r5, [%r1, 4]
+#ifdef __LITTLE_ENDIAN__
+	nop_s
+	/* one more load latency cycle */
+.Last_cmp:
+	xor	%r0, %r4, %r5
+	bset	%r0, %r0, SHIFT
+	sub_s	%r1, %r0, 1
+	bic_s	%r1, %r1, %r0
+	norm	%r1, %r1
+	b.d	.Leven_cmp
+	and	%r1, %r1, 24
+.Leven:
+	xor	%r0, %r4, %r5
+	sub_s	%r1, %r0, 1
+	bic_s	%r1, %r1, %r0
+	norm	%r1, %r1
+	/* slow track insn */
+	and	%r1, %r1, 24
+.Leven_cmp:
+	asl	%r2, %r4, %r1
+	asl	%r12, %r5, %r1
+	lsr_s	%r2, %r2, 1
+	lsr_s	%r12, %r12, 1
+	j_s.d	[%blink]
+	sub	%r0, %r2, %r12
+	.balign	4
+.Lodd:
+	xor	%r0, WORD2, %r12
+	sub_s	%r1, %r0, 1
+	bic_s	%r1, %r1, %r0
+	norm	%r1, %r1
+	/* slow track insn */
+	and	%r1, %r1, 24
+	asl_s	%r2, %r2, %r1
+	asl_s	%r12, %r12, %r1
+	lsr_s	%r2, %r2, 1
+	lsr_s	%r12, %r12, 1
+	j_s.d	[%blink]
+	sub	%r0, %r2, %r12
+#else /* __BIG_ENDIAN__ */
+.Last_cmp:
+	neg_s	SHIFT, SHIFT
+	lsr	%r4, %r4, SHIFT
+	lsr	%r5, %r5, SHIFT
+	/* slow track insn */
+.Leven:
+	sub.f	%r0, %r4, %r5
+	mov.ne	%r0, 1
+	j_s.d	[%blink]
+	bset.cs	%r0, %r0, 31
+.Lodd:
+	cmp_s	WORD2, %r12
+
+	mov_s	%r0, 1
+	j_s.d	[%blink]
+	bset.cs	%r0, %r0, 31
+#endif /* _ENDIAN__ */
+	.balign	4
+.Lbytewise:
+	breq	%r2, 0, .Lnil
+	ldb	%r4, [%r0, 0]
+	ldb	%r5, [%r1, 0]
+	lsr.f	%lp_count, %r3
+	lpne	.Lbyte_end
+	ldb_s	%r3, [%r0, 1]
+	ldb	%r12, [%r1, 1]
+	brne	%r4, %r5, .Lbyte_even
+	ldb.a	%r4, [%r0, 2]
+	ldb.a	%r5, [%r1, 2]
+	brne	%r3, %r12, .Lbyte_odd
+.Lbyte_end:
+	bcc	.Lbyte_even
+	brne	%r4, %r5, .Lbyte_even
+	ldb_s	%r3, [%r0, 1]
+	ldb_s	%r12, [%r1, 1]
+.Lbyte_odd:
+	j_s.d	[%blink]
+	sub	%r0, %r3, %r12
+.Lbyte_even:
+	j_s.d	[%blink]
+	sub	%r0, %r4, %r5
+.Lnil:
+	j_s.d	[%blink]
+	mov	%r0, 0
diff --git a/arch/arc/lib/memcpy-700.S b/arch/arc/lib/memcpy-700.S
new file mode 100644
index 0000000000..51dd73ab8f
--- /dev/null
+++ b/arch/arc/lib/memcpy-700.S
@@ -0,0 +1,63 @@
+/*
+ * Copyright (C) 2004, 2007-2010, 2011-2014 Synopsys, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+.global memcpy
+.align 4
+memcpy:
+	or	%r3, %r0, %r1
+	asl_s	%r3, %r3, 30
+	mov_s	%r5, %r0
+	brls.d	%r2, %r3, .Lcopy_bytewise
+	sub.f	%r3, %r2, 1
+	ld_s	%r12, [%r1, 0]
+	asr.f	%lp_count, %r3, 3
+	bbit0.d	%r3, 2, .Lnox4
+	bmsk_s	%r2, %r2, 1
+	st.ab	%r12, [%r5, 4]
+	ld.a	%r12, [%r1, 4]
+.Lnox4:
+	lppnz	.Lendloop
+	ld_s	%r3, [%r1, 4]
+	st.ab	%r12, [%r5, 4]
+	ld.a	%r12, [%r1, 8]
+	st.ab	%r3, [%r5, 4]
+.Lendloop:
+	breq	%r2, 0, .Last_store
+	ld	%r3, [%r5, 0]
+#ifdef __LITTLE_ENDIAN__
+	add3	%r2, -1, %r2
+	/* uses long immediate */
+	xor_s	%r12, %r12, %r3
+	bmsk	%r12, %r12, %r2
+	xor_s	%r12, %r12, %r3
+#else /* __BIG_ENDIAN__ */
+	sub3	%r2, 31, %r2
+	/* uses long immediate */
+	xor_s	%r3, %r3, %r12
+	bmsk	%r3, %r3, %r2
+	xor_s	%r12, %r12, %r3
+#endif /* _ENDIAN__ */
+.Last_store:
+	j_s.d	[%blink]
+	st	%r12, [%r5, 0]
+
+	.balign	4
+.Lcopy_bytewise:
+	jcs	[%blink]
+	ldb_s	%r12, [%r1, 0]
+	lsr.f	%lp_count, %r3
+	bhs_s	.Lnox1
+	stb.ab	%r12, [%r5, 1]
+	ldb.a	%r12, [%r1, 1]
+.Lnox1:
+	lppnz	.Lendbloop
+	ldb_s	%r3, [%r1, 1]
+	stb.ab	%r12, [%r5, 1]
+	ldb.a	%r12, [%r1, 2]
+	stb.ab	%r3, [%r5, 1]
+.Lendbloop:
+	j_s.d	[%blink]
+	stb	%r12, [%r5, 0]
diff --git a/arch/arc/lib/memset.S b/arch/arc/lib/memset.S
new file mode 100644
index 0000000000..017e8af0e8
--- /dev/null
+++ b/arch/arc/lib/memset.S
@@ -0,0 +1,62 @@
+/*
+ * Copyright (C) 2004, 2007-2010, 2011-2014 Synopsys, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#define SMALL	7 /* Must be at least 6 to deal with alignment/loop issues.  */
+
+.global memset
+.align 4
+memset:
+	mov_s	%r4, %r0
+	or	%r12, %r0, %r2
+	bmsk.f	%r12, %r12, 1
+	extb_s	%r1, %r1
+	asl	%r3, %r1, 8
+	beq.d	.Laligned
+	or_s	%r1, %r1, %r3
+	brls	%r2, SMALL, .Ltiny
+	add	%r3, %r2, %r0
+	stb	%r1, [%r3, -1]
+	bclr_s	%r3, %r3, 0
+	stw	%r1, [%r3, -2]
+	bmsk.f	%r12, %r0, 1
+	add_s	%r2, %r2, %r12
+	sub.ne	%r2, %r2, 4
+	stb.ab	%r1, [%r4, 1]
+	and	%r4, %r4, -2
+	stw.ab	%r1, [%r4, 2]
+	and	%r4, %r4, -4
+
+	.balign	4
+.Laligned:
+	asl	%r3, %r1, 16
+	lsr.f	%lp_count, %r2, 2
+	or_s	%r1, %r1, %r3
+	lpne	.Loop_end
+	st.ab	%r1, [%r4, 4]
+.Loop_end:
+	j_s	[%blink]
+
+	.balign	4
+.Ltiny:
+	mov.f	%lp_count, %r2
+	lpne	.Ltiny_end
+	stb.ab	%r1, [%r4, 1]
+.Ltiny_end:
+	j_s	[%blink]
+
+/*
+ * memzero: @r0 = mem, @r1 = size_t
+ * memset:  @r0 = mem, @r1 = char, @r2 = size_t
+ */
+
+.global memzero
+.align 4
+memzero:
+	/* adjust bzero args to memset args */
+	mov	%r2, %r1
+	mov	%r1, 0
+	/* tail call so need to tinker with blink */
+	b	memset
diff --git a/arch/arc/lib/relocate.c b/arch/arc/lib/relocate.c
new file mode 100644
index 0000000000..2482bcdffc
--- /dev/null
+++ b/arch/arc/lib/relocate.c
@@ -0,0 +1,76 @@
+/*
+ * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <elf.h>
+#include <asm/sections.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * Base functionality is taken from x86 version with added ARC-specifics
+ */
+int do_elf_reloc_fixups(void)
+{
+	Elf32_Rela *re_src = (Elf32_Rela *)(&__rel_dyn_start);
+	Elf32_Rela *re_end = (Elf32_Rela *)(&__rel_dyn_end);
+
+	Elf32_Addr *offset_ptr_rom, *last_offset = NULL;
+	Elf32_Addr *offset_ptr_ram;
+
+	do {
+		/* Get the location from the relocation entry */
+		offset_ptr_rom = (Elf32_Addr *)re_src->r_offset;
+
+		/* Check that the location of the relocation is in .text */
+		if (offset_ptr_rom >= (Elf32_Addr *)CONFIG_SYS_TEXT_BASE &&
+		    offset_ptr_rom > last_offset) {
+			unsigned int val;
+			/* Switch to the in-RAM version */
+			offset_ptr_ram = (Elf32_Addr *)((ulong)offset_ptr_rom +
+							gd->reloc_off);
+
+			/*
+			 * Use "memcpy" because target location might be
+			 * 16-bit aligned on ARC so we may need to read
+			 * byte-by-byte. On attempt to read entire word by
+			 * CPU throws an exception
+			 */
+			memcpy(&val, offset_ptr_ram, sizeof(int));
+
+#ifdef __LITTLE_ENDIAN__
+			/* If location in ".text" section swap value */
+			if ((unsigned int)offset_ptr_rom <
+			    (unsigned int)&__text_end)
+				val = (val << 16) | (val >> 16);
+#endif
+
+			/* Check that the target points into .text */
+			if (val >= CONFIG_SYS_TEXT_BASE && val <=
+			    (unsigned int)&__bss_end) {
+				val += gd->reloc_off;
+#ifdef __LITTLE_ENDIAN__
+				/* If location in ".text" section swap value */
+				if ((unsigned int)offset_ptr_rom <
+				    (unsigned int)&__text_end)
+					val = (val << 16) | (val >> 16);
+#endif
+				memcpy(offset_ptr_ram, &val, sizeof(int));
+			} else {
+				debug("   %p: rom reloc %x, ram %p, value %x, limit %x\n",
+				      re_src, re_src->r_offset, offset_ptr_ram,
+				      val, (unsigned int)&__bss_end);
+			}
+		} else {
+			debug("   %p: rom reloc %x, last %p\n", re_src,
+			      re_src->r_offset, last_offset);
+		}
+		last_offset = offset_ptr_rom;
+
+	} while (++re_src < re_end);
+
+	return 0;
+}
diff --git a/arch/arc/lib/sections.c b/arch/arc/lib/sections.c
new file mode 100644
index 0000000000..b0b46a4e9a
--- /dev/null
+++ b/arch/arc/lib/sections.c
@@ -0,0 +1,21 @@
+/*
+ * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * For some reason linker sets linker-generated symbols to zero in PIE mode.
+ * A work-around is substitution of linker-generated symbols with
+ * compiler-generated symbols which are properly handled by linker in PAE mode.
+ */
+
+char __bss_start[0] __attribute__((section(".__bss_start")));
+char __bss_end[0] __attribute__((section(".__bss_end")));
+char __image_copy_start[0] __attribute__((section(".__image_copy_start")));
+char __image_copy_end[0] __attribute__((section(".__image_copy_end")));
+char __rel_dyn_start[0] __attribute__((section(".__rel_dyn_start")));
+char __rel_dyn_end[0] __attribute__((section(".__rel_dyn_end")));
+char __text_start[0] __attribute__((section(".__text_start")));
+char __text_end[0] __attribute__((section(".__text_end")));
+char __init_end[0] __attribute__((section(".__init_end")));
diff --git a/arch/arc/lib/strchr-700.S b/arch/arc/lib/strchr-700.S
new file mode 100644
index 0000000000..55fcc9fb00
--- /dev/null
+++ b/arch/arc/lib/strchr-700.S
@@ -0,0 +1,141 @@
+/*
+ * Copyright (C) 2004, 2007-2010, 2011-2014 Synopsys, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * ARC700 has a relatively long pipeline and branch prediction, so we want
+ * to avoid branches that are hard to predict.  On the other hand, the
+ * presence of the norm instruction makes it easier to operate on whole
+ * words branch-free.
+ */
+
+.global strchr
+.align 4
+strchr:
+	extb_s	%r1, %r1
+	asl	%r5, %r1, 8
+	bmsk	%r2, %r0, 1
+	or	%r5, %r5, %r1
+	mov_s	%r3, 0x01010101
+	breq.d	%r2, %r0, .Laligned
+	asl	%r4, %r5, 16
+	sub_s	%r0, %r0, %r2
+	asl	%r7, %r2, 3
+	ld_s	%r2, [%r0]
+#ifdef __LITTLE_ENDIAN__
+	asl	%r7, %r3, %r7
+#else /* __BIG_ENDIAN__ */
+	lsr	%r7, %r3, %r7
+#endif /* _ENDIAN__ */
+	or	%r5, %r5, %r4
+	ror	%r4, %r3
+	sub	%r12, %r2, %r7
+	bic_s	%r12, %r12, %r2
+	and	%r12, %r12, %r4
+	brne.d	%r12, 0, .Lfound0_ua
+	xor	%r6, %r2, %r5
+	ld.a	%r2, [%r0, 4]
+	sub	%r12, %r6, %r7
+	bic	%r12, %r12, %r6
+#ifdef __LITTLE_ENDIAN__
+	and	%r7, %r12, %r4
+	/* For speed, we want this branch to be unaligned. */
+	breq	%r7, 0, .Loop
+	/* Likewise this one */
+	b	.Lfound_char
+#else /* __BIG_ENDIAN__ */
+	and	%r12, %r12, %r4
+	/* For speed, we want this branch to be unaligned. */
+	breq	%r12, 0, .Loop
+	lsr_s	%r12, %r12, 7
+	bic 	%r2, %r7, %r6
+	b.d	.Lfound_char_b
+	and_s	%r2, %r2, %r12
+#endif /* _ENDIAN__ */
+	/* We require this code address to be unaligned for speed...  */
+.Laligned:
+	ld_s	%r2, [%r0]
+	or	%r5, %r5, %r4
+	ror	%r4, %r3
+	/* ... so that this code address is aligned, for itself and ...  */
+.Loop:
+	sub	%r12, %r2, %r3
+	bic_s	%r12, %r12, %r2
+	and	%r12, %r12, %r4
+	brne.d	%r12, 0, .Lfound0
+	xor	%r6, %r2, %r5
+	ld.a	%r2, [%r0, 4]
+	sub	%r12, %r6, %r3
+	bic	%r12, %r12, %r6
+	and	%r7, %r12, %r4
+	breq	%r7, 0, .Loop
+	/*
+	 *... so that this branch is unaligned.
+	 * Found searched-for character.
+	 * r0 has already advanced to next word.
+	 */
+#ifdef __LITTLE_ENDIAN__
+	/*
+	 * We only need the information about the first matching byte
+	 * (i.e. the least significant matching byte) to be exact,
+	 * hence there is no problem with carry effects.
+	 */
+.Lfound_char:
+	sub	%r3, %r7, 1
+	bic	%r3, %r3, %r7
+	norm	%r2, %r3
+	sub_s	%r0, %r0, 1
+	asr_s	%r2, %r2, 3
+	j.d	[%blink]
+	sub_s	%r0, %r0, %r2
+
+	.balign	4
+.Lfound0_ua:
+	mov	%r3, %r7
+.Lfound0:
+	sub	%r3, %r6, %r3
+	bic	%r3, %r3, %r6
+	and	%r2, %r3, %r4
+	or_s	%r12, %r12, %r2
+	sub_s	%r3, %r12, 1
+	bic_s	%r3, %r3, %r12
+	norm	%r3, %r3
+	add_s	%r0, %r0, 3
+	asr_s	%r12, %r3, 3
+	asl.f	0, %r2, %r3
+	sub_s	%r0, %r0, %r12
+	j_s.d	[%blink]
+	mov.pl	%r0, 0
+#else /* __BIG_ENDIAN__ */
+.Lfound_char:
+	lsr	%r7, %r7, 7
+
+	bic	%r2, %r7, %r6
+.Lfound_char_b:
+	norm	%r2, %r2
+	sub_s	%r0, %r0, 4
+	asr_s	%r2, %r2, 3
+	j.d	[%blink]
+	add_s	%r0, %r0, %r2
+
+.Lfound0_ua:
+	mov_s	%r3, %r7
+.Lfound0:
+	asl_s	%r2, %r2, 7
+	or	%r7, %r6, %r4
+	bic_s	%r12, %r12, %r2
+	sub	%r2, %r7, %r3
+	or	%r2, %r2, %r6
+	bic	%r12, %r2, %r12
+	bic.f	%r3, %r4, %r12
+	norm	%r3, %r3
+
+	add.pl	%r3, %r3, 1
+	asr_s	%r12, %r3, 3
+	asl.f	0, %r2, %r3
+	add_s	%r0, %r0, %r12
+	j_s.d	[%blink]
+	mov.mi	%r0, 0
+#endif /* _ENDIAN__ */
diff --git a/arch/arc/lib/strcmp.S b/arch/arc/lib/strcmp.S
new file mode 100644
index 0000000000..8cb7d2f18c
--- /dev/null
+++ b/arch/arc/lib/strcmp.S
@@ -0,0 +1,97 @@
+/*
+ * Copyright (C) 2004, 2007-2010, 2011-2014 Synopsys, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * This is optimized primarily for the ARC700.
+ * It would be possible to speed up the loops by one cycle / word
+ * respective one cycle / byte by forcing double source 1 alignment, unrolling
+ * by a factor of two, and speculatively loading the second word / byte of
+ * source 1; however, that would increase the overhead for loop setup / finish,
+ * and strcmp might often terminate early.
+ */
+
+.global strcmp
+.align 4
+strcmp:
+	or	%r2, %r0, %r1
+	bmsk_s	%r2, %r2, 1
+	brne	%r2, 0, .Lcharloop
+	mov_s	%r12, 0x01010101
+	ror	%r5, %r12
+.Lwordloop:
+	ld.ab	%r2, [%r0, 4]
+	ld.ab	%r3, [%r1, 4]
+	nop_s
+	sub	%r4, %r2, %r12
+	bic	%r4, %r4, %r2
+	and	%r4, %r4, %r5
+	brne	%r4, 0, .Lfound0
+	breq	%r2 ,%r3, .Lwordloop
+#ifdef	__LITTLE_ENDIAN__
+	xor	%r0, %r2, %r3	/* mask for difference */
+	sub_s	%r1, %r0, 1
+	bic_s	%r0, %r0, %r1	/* mask for least significant difference bit */
+	sub	%r1, %r5, %r0
+	xor	%r0, %r5, %r1	/* mask for least significant difference byte */
+	and_s	%r2, %r2, %r0
+	and_s	%r3, %r3, %r0
+#endif /* _ENDIAN__ */
+	cmp_s	%r2, %r3
+	mov_s	%r0, 1
+	j_s.d	[%blink]
+	bset.lo	%r0, %r0, 31
+
+	.balign	4
+#ifdef __LITTLE_ENDIAN__
+.Lfound0:
+	xor	%r0, %r2, %r3	/* mask for difference */
+	or	%r0, %r0, %r4	/* or in zero indicator */
+	sub_s	%r1, %r0, 1
+	bic_s	%r0, %r0, %r1	/* mask for least significant difference bit */
+	sub	%r1, %r5, %r0
+	xor	%r0, %r5, %r1	/* mask for least significant difference byte */
+	and_s	%r2, %r2, %r0
+	and_s	%r3, %r3, %r0
+	sub.f	%r0, %r2, %r3
+	mov.hi	%r0, 1
+	j_s.d	[%blink]
+	bset.lo	%r0, %r0, 31
+#else /* __BIG_ENDIAN__ */
+	/*
+	 * The zero-detection above can mis-detect 0x01 bytes as zeroes
+	 * because of carry-propagateion from a lower significant zero byte.
+	 * We can compensate for this by checking that bit0 is zero.
+	 * This compensation is not necessary in the step where we
+	 * get a low estimate for r2, because in any affected bytes
+	 * we already have 0x00 or 0x01, which will remain unchanged
+	 * when bit 7 is cleared.
+	 */
+	.balign	4
+.Lfound0:
+	lsr	%r0, %r4, 8
+	lsr_s	%r1, %r2
+	bic_s	%r2, %r2, %r0	/* get low estimate for r2 and get ... */
+	bic_s	%r0, %r0, %r1	/* <this is the adjusted mask for zeros> */
+	or_s	%r3, %r3, %r0	/* ... high estimate r3 so that r2 > r3 will */
+	cmp_s	%r3, %r2	/* ... be independent of trailing garbage */
+	or_s	%r2, %r2, %r0	/* likewise for r3 > r2 */
+	bic_s	%r3, %r3, %r0
+	rlc	%r0, 0		/* r0 := r2 > r3 ? 1 : 0 */
+	cmp_s	%r2, %r3
+	j_s.d	[%blink]
+	bset.lo	%r0, %r0, 31
+#endif /* _ENDIAN__ */
+
+	.balign	4
+.Lcharloop:
+	ldb.ab	%r2,[%r0,1]
+	ldb.ab	%r3,[%r1,1]
+	nop_s
+	breq	%r2, 0, .Lcmpend
+	breq	%r2, %r3, .Lcharloop
+.Lcmpend:
+	j_s.d	[%blink]
+	sub	%r0, %r2, %r3
diff --git a/arch/arc/lib/strcpy-700.S b/arch/arc/lib/strcpy-700.S
new file mode 100644
index 0000000000..41bb53e501
--- /dev/null
+++ b/arch/arc/lib/strcpy-700.S
@@ -0,0 +1,67 @@
+/*
+ * Copyright (C) 2004, 2007-2010, 2011-2014 Synopsys, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * If dst and src are 4 byte aligned, copy 8 bytes at a time.
+ * If the src is 4, but not 8 byte aligned, we first read 4 bytes to get
+ * it 8 byte aligned.  Thus, we can do a little read-ahead, without
+ * dereferencing a cache line that we should not touch.
+ * Note that short and long instructions have been scheduled to avoid
+ * branch stalls.
+ * The beq_s to r3z could be made unaligned & long to avoid a stall
+ * there, but it is not likely to be taken often, and it would also be likely
+ * to cost an unaligned mispredict at the next call.
+ */
+
+.global strcpy
+.align 4
+strcpy:
+	or	%r2, %r0, %r1
+	bmsk_s	%r2, %r2, 1
+	brne.d	%r2, 0, charloop
+	mov_s	%r10, %r0
+	ld_s	%r3, [%r1, 0]
+	mov	%r8, 0x01010101
+	bbit0.d	%r1, 2, loop_start
+	ror	%r12, %r8
+	sub	%r2, %r3, %r8
+	bic_s	%r2, %r2, %r3
+	tst_s	%r2,%r12
+	bne	r3z
+	mov_s	%r4,%r3
+	.balign 4
+loop:
+	ld.a	%r3, [%r1, 4]
+	st.ab	%r4, [%r10, 4]
+loop_start:
+	ld.a	%r4, [%r1, 4]
+	sub	%r2, %r3, %r8
+	bic_s	%r2, %r2, %r3
+	tst_s	%r2, %r12
+	bne_s	r3z
+	st.ab	%r3, [%r10, 4]
+	sub	%r2, %r4, %r8
+	bic	%r2, %r2, %r4
+	tst	%r2, %r12
+	beq	loop
+	mov_s	%r3, %r4
+#ifdef __LITTLE_ENDIAN__
+r3z:	bmsk.f	%r1, %r3, 7
+	lsr_s	%r3, %r3, 8
+#else /* __BIG_ENDIAN__ */
+r3z:	lsr.f	%r1, %r3, 24
+	asl_s	%r3, %r3, 8
+#endif /* _ENDIAN__ */
+	bne.d	r3z
+	stb.ab	%r1, [%r10, 1]
+	j_s	[%blink]
+
+	.balign	4
+charloop:
+	ldb.ab	%r3, [%r1, 1]
+	brne.d	%r3, 0, charloop
+	stb.ab	%r3, [%r10, 1]
+	j	[%blink]
diff --git a/arch/arc/lib/strlen.S b/arch/arc/lib/strlen.S
new file mode 100644
index 0000000000..666e22c0d5
--- /dev/null
+++ b/arch/arc/lib/strlen.S
@@ -0,0 +1,80 @@
+/*
+ * Copyright (C) 2004, 2007-2010, 2011-2014 Synopsys, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+.global strlen
+.align 4
+strlen:
+	or	%r3, %r0, 7
+	ld	%r2, [%r3, -7]
+	ld.a	%r6, [%r3, -3]
+	mov	%r4, 0x01010101
+	/* uses long immediate */
+#ifdef __LITTLE_ENDIAN__
+	asl_s	%r1, %r0, 3
+	btst_s	%r0, 2
+	asl	%r7, %r4, %r1
+	ror	%r5, %r4
+	sub	%r1, %r2, %r7
+	bic_s	%r1, %r1, %r2
+	mov.eq	%r7, %r4
+	sub	%r12, %r6, %r7
+	bic	%r12, %r12, %r6
+	or.eq	%r12, %r12, %r1
+	and	%r12, %r12, %r5
+	brne	%r12, 0, .Learly_end
+#else /* __BIG_ENDIAN__ */
+	ror	%r5, %r4
+	btst_s	%r0, 2
+	mov_s	%r1, 31
+	sub3	%r7, %r1, %r0
+	sub	%r1, %r2, %r4
+	bic_s	%r1, %r1, %r2
+	bmsk	%r1, %r1, %r7
+	sub	%r12, %r6, %r4
+	bic	%r12, %r12, %r6
+	bmsk.ne	%r12, %r12, %r7
+	or.eq	%r12, %r12, %r1
+	and	%r12, %r12, %r5
+	brne	%r12, 0, .Learly_end
+#endif /* _ENDIAN__ */
+
+.Loop:
+	ld_s	%r2, [%r3, 4]
+	ld.a	%r6, [%r3, 8]
+	/* stall for load result */
+	sub	%r1, %r2, %r4
+	bic_s	%r1, %r1, %r2
+	sub	%r12, %r6, %r4
+	bic	%r12, %r12, %r6
+	or	%r12, %r12, %r1
+	and	%r12, %r12, %r5
+	breq	%r12, 0, .Loop
+.Lend:
+	and.f	%r1, %r1, %r5
+	sub.ne	%r3, %r3, 4
+	mov.eq	%r1, %r12
+#ifdef __LITTLE_ENDIAN__
+	sub_s	%r2, %r1, 1
+	bic_s	%r2, %r2, %r1
+	norm	%r1, %r2
+	sub_s	%r0, %r0, 3
+	lsr_s	%r1, %r1, 3
+	sub	%r0, %r3, %r0
+	j_s.d	[%blink]
+	sub	%r0, %r0, %r1
+#else /* __BIG_ENDIAN__ */
+	lsr_s	%r1, %r1, 7
+	mov.eq	%r2, %r6
+	bic_s	%r1, %r1, %r2
+	norm	%r1, %r1
+	sub	%r0, %r3, %r0
+	lsr_s	%r1, %r1, 3
+	j_s.d	[%blink]
+	add	%r0, %r0, %r1
+#endif /* _ENDIAN */
+.Learly_end:
+	b.d	.Lend
+	sub_s.ne %r1, %r1, %r1
diff --git a/arch/arm/config.mk b/arch/arm/config.mk
index bdabcf407e..5f7cd3a610 100644
--- a/arch/arm/config.mk
+++ b/arch/arm/config.mk
@@ -5,8 +5,6 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-CROSS_COMPILE ?= arm-linux-
-
 ifndef CONFIG_STANDALONE_LOAD_ADDR
 ifneq ($(CONFIG_OMAP_COMMON),)
 CONFIG_STANDALONE_LOAD_ADDR = 0x80300000
@@ -17,7 +15,9 @@ endif
 
 LDFLAGS_FINAL += --gc-sections
 PLATFORM_RELFLAGS += -ffunction-sections -fdata-sections \
-		     -fno-common -ffixed-r9 -msoft-float
+		     -fno-common -ffixed-r9
+PLATFORM_RELFLAGS += $(call cc-option, -msoft-float) \
+      $(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,))
 
 # Support generic board on ARM
 __HAVE_ARCH_GENERIC_BOARD := y
@@ -37,7 +37,17 @@ endif
 
 # Only test once
 ifneq ($(CONFIG_SPL_BUILD),y)
-ALL-$(CONFIG_SYS_THUMB_BUILD)	+= checkthumb
+ifeq ($(CONFIG_SYS_THUMB_BUILD),y)
+archprepare: checkthumb
+
+checkthumb:
+	@if test "$(call cc-version)" -lt "0404"; then \
+		echo -n '*** Your GCC does not produce working '; \
+		echo 'binaries in THUMB mode.'; \
+		echo '*** Your board is configured for THUMB mode.'; \
+		false; \
+	fi
+endif
 endif
 
 # Try if EABI is supported, else fall back to old API,
@@ -65,13 +75,8 @@ ifneq (,$(findstring -mabi=aapcs-linux,$(PLATFORM_CPPFLAGS)))
 # times. Also, the prefix needs to be different based on whether
 # CONFIG_SPL_BUILD is defined or not. 'filter-out' the existing entry
 # before adding the correct one.
-ifdef CONFIG_SPL_BUILD
-PLATFORM_LIBS := $(SPLTREE)/arch/arm/lib/eabi_compat.o \
-	$(filter-out %/arch/arm/lib/eabi_compat.o, $(PLATFORM_LIBS))
-else
-PLATFORM_LIBS := $(OBJTREE)/arch/arm/lib/eabi_compat.o \
-	$(filter-out %/arch/arm/lib/eabi_compat.o, $(PLATFORM_LIBS))
-endif
+PLATFORM_LIBS := arch/arm/lib/eabi_compat.o \
+	$(filter-out arch/arm/lib/eabi_compat.o, $(PLATFORM_LIBS))
 endif
 
 # needed for relocation
@@ -103,3 +108,29 @@ ALL-y += checkarmreloc
 # such usage by requiring word relocations.
 PLATFORM_CPPFLAGS += $(call cc-option, -mword-relocations)
 endif
+
+# limit ourselves to the sections we want in the .bin.
+ifdef CONFIG_ARM64
+OBJCOPYFLAGS += -j .text -j .rodata -j .data -j .u_boot_list -j .rela.dyn
+else
+OBJCOPYFLAGS += -j .text -j .rodata -j .hash -j .data -j .got.plt -j .u_boot_list -j .rel.dyn
+endif
+
+ifneq ($(CONFIG_IMX_CONFIG),)
+ifdef CONFIG_SPL
+ifndef CONFIG_SPL_BUILD
+ALL-y += SPL
+endif
+else
+ifeq ($(CONFIG_OF_SEPARATE),y)
+ALL-y += u-boot-dtb.imx
+else
+ifeq ($(CONFIG_IMX_NAND),y)
+# u-boot-nand.imx builds u-boot.imx as well
+ALL-y += u-boot-nand.imx
+else
+ALL-y += u-boot.imx
+endif
+endif
+endif
+endif
diff --git a/arch/arm/cpu/Makefile b/arch/arm/cpu/Makefile
new file mode 100644
index 0000000000..b2d30b1a72
--- /dev/null
+++ b/arch/arm/cpu/Makefile
@@ -0,0 +1,3 @@
+obj-$(CONFIG_AT91FAMILY) += at91-common/
+obj-$(CONFIG_TEGRA) += $(SOC)-common/
+obj-$(CONFIG_TEGRA) += tegra-common/
diff --git a/arch/arm/cpu/arm1136/Makefile b/arch/arm/cpu/arm1136/Makefile
index cc516f744b..3279f125f6 100644
--- a/arch/arm/cpu/arm1136/Makefile
+++ b/arch/arm/cpu/arm1136/Makefile
@@ -5,27 +5,5 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(CPU).o
-
-START	= start.o
-COBJS	= cpu.o
-
-SRCS	:= $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS) $(SOBJS))
-START	:= $(addprefix $(obj),$(START))
-
-all:	$(obj).depend $(START) $(LIB)
-
-$(LIB):	$(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+extra-y	= start.o
+obj-y	= cpu.o
diff --git a/arch/arm/cpu/arm1136/config.mk b/arch/arm/cpu/arm1136/config.mk
index b4d396de84..a82c6cec9c 100644
--- a/arch/arm/cpu/arm1136/config.mk
+++ b/arch/arm/cpu/arm1136/config.mk
@@ -7,20 +7,3 @@
 
 # Make ARMv5 to allow more compilers to work, even though its v6.
 PLATFORM_CPPFLAGS += -march=armv5
-# =========================================================================
-#
-# Supply options according to compiler version
-#
-# =========================================================================
-PF_RELFLAGS_SLB_AT := $(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,))
-PLATFORM_RELFLAGS += $(PF_RELFLAGS_SLB_AT)
-
-ifneq ($(CONFIG_IMX_CONFIG),)
-ifdef CONFIG_SPL
-ifdef CONFIG_SPL_BUILD
-ALL-y	+= $(OBJTREE)/SPL
-endif
-else
-ALL-y	+= $(obj)u-boot.imx
-endif
-endif
diff --git a/arch/arm/cpu/arm1136/mx31/Makefile b/arch/arm/cpu/arm1136/mx31/Makefile
index c75adec6e9..9670ed9382 100644
--- a/arch/arm/cpu/arm1136/mx31/Makefile
+++ b/arch/arm/cpu/arm1136/mx31/Makefile
@@ -5,27 +5,6 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(SOC).o
-
-COBJS	+= generic.o
-COBJS	+= timer.o
-COBJS	+= devices.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS))
-
-all:	$(obj).depend $(LIB)
-
-$(LIB):	$(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	+= generic.o
+obj-y	+= timer.o
+obj-y	+= devices.o
diff --git a/arch/arm/cpu/arm1136/mx35/Makefile b/arch/arm/cpu/arm1136/mx35/Makefile
index ee534a92d3..c533215c3a 100644
--- a/arch/arm/cpu/arm1136/mx35/Makefile
+++ b/arch/arm/cpu/arm1136/mx35/Makefile
@@ -7,28 +7,6 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(SOC).o
-
-COBJS	+= generic.o
-COBJS	+= timer.o
-COBJS	+= mx35_sdram.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS))
-
-all:	$(obj).depend $(LIB)
-
-$(LIB):	$(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	+= generic.o
+obj-y	+= timer.o
+obj-y	+= mx35_sdram.o
diff --git a/arch/arm/cpu/arm1136/mx35/asm-offsets.c b/arch/arm/cpu/arm1136/mx35/asm-offsets.c
deleted file mode 100644
index ebd7575039..0000000000
--- a/arch/arm/cpu/arm1136/mx35/asm-offsets.c
+++ /dev/null
@@ -1,71 +0,0 @@
-/*
- * Adapted from Linux v2.6.36 kernel: arch/powerpc/kernel/asm-offsets.c
- *
- * This program is used to generate definitions needed by
- * assembly language modules.
- *
- * We use the technique used in the OSF Mach kernel code:
- * generate asm statements containing #defines,
- * compile this file to assembler, and then extract the
- * #defines from the assembly-language output.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/arch/imx-regs.h>
-
-#include <linux/kbuild.h>
-
-int main(void)
-{
-	/* Round up to make sure size gives nice stack alignment */
-	DEFINE(CLKCTL_CCMR, offsetof(struct ccm_regs, ccmr));
-	DEFINE(CLKCTL_PDR0, offsetof(struct ccm_regs, pdr0));
-	DEFINE(CLKCTL_PDR1, offsetof(struct ccm_regs, pdr1));
-	DEFINE(CLKCTL_PDR2, offsetof(struct ccm_regs, pdr2));
-	DEFINE(CLKCTL_PDR3, offsetof(struct ccm_regs, pdr3));
-	DEFINE(CLKCTL_PDR4, offsetof(struct ccm_regs, pdr4));
-	DEFINE(CLKCTL_RCSR, offsetof(struct ccm_regs, rcsr));
-	DEFINE(CLKCTL_MPCTL, offsetof(struct ccm_regs, mpctl));
-	DEFINE(CLKCTL_PPCTL, offsetof(struct ccm_regs, ppctl));
-	DEFINE(CLKCTL_ACMR, offsetof(struct ccm_regs, acmr));
-	DEFINE(CLKCTL_COSR, offsetof(struct ccm_regs, cosr));
-	DEFINE(CLKCTL_CGR0, offsetof(struct ccm_regs, cgr0));
-	DEFINE(CLKCTL_CGR1, offsetof(struct ccm_regs, cgr1));
-	DEFINE(CLKCTL_CGR2, offsetof(struct ccm_regs, cgr2));
-	DEFINE(CLKCTL_CGR3, offsetof(struct ccm_regs, cgr3));
-
-	/* Multi-Layer AHB Crossbar Switch */
-	DEFINE(MAX_MPR0, offsetof(struct max_regs, mpr0));
-	DEFINE(MAX_SGPCR0, offsetof(struct max_regs, sgpcr0));
-	DEFINE(MAX_MPR1, offsetof(struct max_regs, mpr1));
-	DEFINE(MAX_SGPCR1, offsetof(struct max_regs, sgpcr1));
-	DEFINE(MAX_MPR2, offsetof(struct max_regs, mpr2));
-	DEFINE(MAX_SGPCR2, offsetof(struct max_regs, sgpcr2));
-	DEFINE(MAX_MPR3, offsetof(struct max_regs, mpr3));
-	DEFINE(MAX_SGPCR3, offsetof(struct max_regs, sgpcr3));
-	DEFINE(MAX_MPR4, offsetof(struct max_regs, mpr4));
-	DEFINE(MAX_SGPCR4, offsetof(struct max_regs, sgpcr4));
-	DEFINE(MAX_MGPCR0, offsetof(struct max_regs, mgpcr0));
-	DEFINE(MAX_MGPCR1, offsetof(struct max_regs, mgpcr1));
-	DEFINE(MAX_MGPCR2, offsetof(struct max_regs, mgpcr2));
-	DEFINE(MAX_MGPCR3, offsetof(struct max_regs, mgpcr3));
-	DEFINE(MAX_MGPCR4, offsetof(struct max_regs, mgpcr4));
-	DEFINE(MAX_MGPCR5, offsetof(struct max_regs, mgpcr5));
-
-	/* AHB <-> IP-Bus Interface */
-	DEFINE(AIPS_MPR_0_7, offsetof(struct aips_regs, mpr_0_7));
-	DEFINE(AIPS_MPR_8_15, offsetof(struct aips_regs, mpr_8_15));
-	DEFINE(AIPS_PACR_0_7, offsetof(struct aips_regs, pacr_0_7));
-	DEFINE(AIPS_PACR_8_15, offsetof(struct aips_regs, pacr_8_15));
-	DEFINE(AIPS_PACR_16_23, offsetof(struct aips_regs, pacr_16_23));
-	DEFINE(AIPS_PACR_24_31, offsetof(struct aips_regs, pacr_24_31));
-	DEFINE(AIPS_OPACR_0_7, offsetof(struct aips_regs, opacr_0_7));
-	DEFINE(AIPS_OPACR_8_15, offsetof(struct aips_regs, opacr_8_15));
-	DEFINE(AIPS_OPACR_16_23, offsetof(struct aips_regs, opacr_16_23));
-	DEFINE(AIPS_OPACR_24_31, offsetof(struct aips_regs, opacr_24_31));
-	DEFINE(AIPS_OPACR_32_39, offsetof(struct aips_regs, opacr_32_39));
-
-	return 0;
-}
diff --git a/arch/arm/cpu/arm1136/start.S b/arch/arm/cpu/arm1136/start.S
index 00d1b30ba6..3e2358e132 100644
--- a/arch/arm/cpu/arm1136/start.S
+++ b/arch/arm/cpu/arm1136/start.S
@@ -70,32 +70,6 @@ _end_vect:
  *************************************************************************
  */
 
-.globl _TEXT_BASE
-_TEXT_BASE:
-#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_TEXT_BASE)
-	.word	CONFIG_SPL_TEXT_BASE
-#else
-	.word	CONFIG_SYS_TEXT_BASE
-#endif
-
-/*
- * These are defined in the board-specific linker script.
- * Subtracting _start from them lets the linker put their
- * relative position in the executable instead of leaving
- * them null.
- */
-.globl _bss_start_ofs
-_bss_start_ofs:
-	.word __bss_start - _start
-
-.globl _bss_end_ofs
-_bss_end_ofs:
-	.word __bss_end - _start
-
-.globl _end_ofs
-_end_ofs:
-	.word _end - _start
-
 #ifdef CONFIG_USE_IRQ
 /* IRQ stack memory (calculated at run-time) */
 .globl IRQ_STACK_START
@@ -295,7 +269,6 @@ cpu_init_crit:
 #ifdef CONFIG_SPL_BUILD
 	.align	5
 do_hang:
-	ldr	sp, _TEXT_BASE			/* use 32 words about stack */
 	bl	hang				/* hang and never return */
 #else	/* !CONFIG_SPL_BUILD */
 	.align	5
diff --git a/arch/arm/cpu/arm1136/u-boot-spl.lds b/arch/arm/cpu/arm1136/u-boot-spl.lds
index bccde73317..0299902f20 100644
--- a/arch/arm/cpu/arm1136/u-boot-spl.lds
+++ b/arch/arm/cpu/arm1136/u-boot-spl.lds
@@ -33,7 +33,11 @@ SECTIONS
 	.data : { *(SORT_BY_ALIGNMENT(.data*)) } >.sram
 	. = ALIGN(4);
 	__image_copy_end = .;
-	_end = .;
+
+	.end :
+	{
+		*(.__end)
+	}
 
 	.bss :
 	{
diff --git a/arch/arm/cpu/arm1176/Makefile b/arch/arm/cpu/arm1176/Makefile
index 5d451a78b6..deec427447 100644
--- a/arch/arm/cpu/arm1176/Makefile
+++ b/arch/arm/cpu/arm1176/Makefile
@@ -8,27 +8,5 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(CPU).o
-
-START	= start.o
-COBJS	= cpu.o
-
-SRCS	:= $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS) $(SOBJS))
-START	:= $(addprefix $(obj),$(START))
-
-all:	$(obj).depend $(START) $(LIB)
-
-$(LIB):	$(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+extra-y	= start.o
+obj-y	= cpu.o
diff --git a/arch/arm/cpu/arm1176/bcm2835/Makefile b/arch/arm/cpu/arm1176/bcm2835/Makefile
index 135de42d37..0ad36906df 100644
--- a/arch/arm/cpu/arm1176/bcm2835/Makefile
+++ b/arch/arm/cpu/arm1176/bcm2835/Makefile
@@ -12,26 +12,5 @@
 # GNU General Public License for more details.
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(SOC).o
-
-SOBJS	:= lowlevel_init.o
-COBJS	:= init.o reset.o timer.o mbox.o
-
-SRCS	:= $(SOBJS:.o=.c) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS))
-
-all:	$(obj).depend $(LIB)
-
-$(LIB):	$(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	:= lowlevel_init.o
+obj-y	+= init.o reset.o timer.o mbox.o
diff --git a/arch/arm/cpu/arm1176/bcm2835/config.mk b/arch/arm/cpu/arm1176/bcm2835/config.mk
deleted file mode 100644
index b87ce244c3..0000000000
--- a/arch/arm/cpu/arm1176/bcm2835/config.mk
+++ /dev/null
@@ -1,19 +0,0 @@
-#
-# (C) Copyright 2012 Stephen Warren
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License
-# version 2 as published by the Free Software Foundation.
-#
-# This program is distributed in the hope that it will be useful, but
-# WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-
-# Don't attempt to override the target CPU/ABI options;
-# the Raspberry Pi toolchain does the right thing by default.
-PLATFORM_RELFLAGS := $(filter-out -msoft-float,$(PLATFORM_RELFLAGS))
-PLATFORM_CPPFLAGS := $(filter-out -march=armv5t,$(PLATFORM_CPPFLAGS))
diff --git a/arch/arm/cpu/arm1176/bcm2835/mbox.c b/arch/arm/cpu/arm1176/bcm2835/mbox.c
index 4daf1e410c..3b17a31eac 100644
--- a/arch/arm/cpu/arm1176/bcm2835/mbox.c
+++ b/arch/arm/cpu/arm1176/bcm2835/mbox.c
@@ -8,7 +8,7 @@
 #include <asm/io.h>
 #include <asm/arch/mbox.h>
 
-#define TIMEOUT (100 * 1000) /* 100mS in uS */
+#define TIMEOUT 1000 /* ms */
 
 int bcm2835_mbox_call_raw(u32 chan, u32 send, u32 *recv)
 {
diff --git a/arch/arm/cpu/arm1176/bcm2835/timer.c b/arch/arm/cpu/arm1176/bcm2835/timer.c
index 2edd6711da..017907cfb8 100644
--- a/arch/arm/cpu/arm1176/bcm2835/timer.c
+++ b/arch/arm/cpu/arm1176/bcm2835/timer.c
@@ -18,11 +18,6 @@
 #include <asm/io.h>
 #include <asm/arch/timer.h>
 
-int timer_init(void)
-{
-	return 0;
-}
-
 ulong get_timer_us(ulong base)
 {
 	struct bcm2835_timer_regs *regs =
diff --git a/arch/arm/cpu/arm1176/config.mk b/arch/arm/cpu/arm1176/config.mk
index f4631cb777..5dc2ebb27b 100644
--- a/arch/arm/cpu/arm1176/config.mk
+++ b/arch/arm/cpu/arm1176/config.mk
@@ -7,11 +7,3 @@
 
 # Make ARMv5 to allow more compilers to work, even though its v6.
 PLATFORM_CPPFLAGS += -march=armv5t
-# =========================================================================
-#
-# Supply options according to compiler version
-#
-# =========================================================================
-PF_RELFLAGS_SLB_AT := $(call cc-option,-mshort-load-bytes,\
-			$(call cc-option,-malignment-traps,))
-PLATFORM_RELFLAGS += $(PF_RELFLAGS_SLB_AT)
diff --git a/arch/arm/cpu/arm1176/start.S b/arch/arm/cpu/arm1176/start.S
index ffd7dd0dcd..ce620115d4 100644
--- a/arch/arm/cpu/arm1176/start.S
+++ b/arch/arm/cpu/arm1176/start.S
@@ -77,33 +77,6 @@ _end_vect:
  *************************************************************************
  */
 
-.globl _TEXT_BASE
-_TEXT_BASE:
-#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_TEXT_BASE)
-	.word	CONFIG_SPL_TEXT_BASE
-#else
-	.word	CONFIG_SYS_TEXT_BASE
-#endif
-
-/*
- * These are defined in the board-specific linker script.
- * Subtracting _start from them lets the linker put their
- * relative position in the executable instead of leaving
- * them null.
- */
-
-.globl _bss_start_ofs
-_bss_start_ofs:
-	.word __bss_start - _start
-
-.globl _bss_end_ofs
-_bss_end_ofs:
-	.word __bss_end - _start
-
-.globl _end_ofs
-_end_ofs:
-	.word _end - _start
-
 /* IRQ stack memory (calculated at run-time) + 8 bytes */
 .globl IRQ_STACK_START_IN
 IRQ_STACK_START_IN:
diff --git a/arch/arm/cpu/arm1176/tnetv107x/Makefile b/arch/arm/cpu/arm1176/tnetv107x/Makefile
index 1eb27edbd8..a4c1edfc71 100644
--- a/arch/arm/cpu/arm1176/tnetv107x/Makefile
+++ b/arch/arm/cpu/arm1176/tnetv107x/Makefile
@@ -2,28 +2,5 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(SOC).o
-
-COBJS	+= aemif.o clock.o init.o mux.o timer.o
-SOBJS	+= lowlevel_init.o
-
-SRCS	:= $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
-
-OBJS	:= $(addprefix $(obj),$(COBJS) $(SOBJS))
-START	:= $(addprefix $(obj),$(START))
-
-all:	$(obj).depend $(LIB)
-
-$(LIB):	$(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	+= aemif.o clock.o init.o mux.o timer.o
+obj-y	+= lowlevel_init.o
diff --git a/arch/arm/cpu/arm720t/Makefile b/arch/arm/cpu/arm720t/Makefile
index 73e16354d0..6badb3bb84 100644
--- a/arch/arm/cpu/arm720t/Makefile
+++ b/arch/arm/cpu/arm720t/Makefile
@@ -5,27 +5,7 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
+extra-y	= start.o
+obj-y	= interrupts.o cpu.o
 
-LIB	= $(obj)lib$(CPU).o
-
-START	= start.o
-COBJS	= interrupts.o cpu.o
-
-SRCS	:= $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS) $(SOBJS))
-START	:= $(addprefix $(obj),$(START))
-
-all:	$(obj).depend $(START) $(LIB)
-
-$(LIB):	$(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-$(CONFIG_TEGRA) += tegra-common/
diff --git a/arch/arm/cpu/arm720t/config.mk b/arch/arm/cpu/arm720t/config.mk
index 2581f0ae67..772fb413e8 100644
--- a/arch/arm/cpu/arm720t/config.mk
+++ b/arch/arm/cpu/arm720t/config.mk
@@ -7,11 +7,3 @@
 #
 
 PLATFORM_CPPFLAGS += -march=armv4 -mtune=arm7tdmi
-# =========================================================================
-#
-# Supply options according to compiler version
-#
-# =========================================================================
-PF_RELFLAGS_SLB_AT := $(call cc-option,-mshort-load-bytes,\
-			$(call cc-option,-malignment-traps,))
-PLATFORM_RELFLAGS += $(PF_RELFLAGS_SLB_AT)
diff --git a/arch/arm/cpu/arm720t/start.S b/arch/arm/cpu/arm720t/start.S
index f180eb8aa6..1a34842690 100644
--- a/arch/arm/cpu/arm720t/start.S
+++ b/arch/arm/cpu/arm720t/start.S
@@ -67,32 +67,6 @@ _pad:			.word 0x12345678 /* now 16*4=64 */
  *************************************************************************
  */
 
-.globl _TEXT_BASE
-_TEXT_BASE:
-#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_TEXT_BASE)
-	.word	CONFIG_SPL_TEXT_BASE
-#else
-	.word	CONFIG_SYS_TEXT_BASE
-#endif
-
-/*
- * These are defined in the board-specific linker script.
- * Subtracting _start from them lets the linker put their
- * relative position in the executable instead of leaving
- * them null.
- */
-.globl _bss_start_ofs
-_bss_start_ofs:
-	.word __bss_start - _start
-
-.globl _bss_end_ofs
-_bss_end_ofs:
-	.word __bss_end - _start
-
-.globl _end_ofs
-_end_ofs:
-	.word _end - _start
-
 #ifdef CONFIG_USE_IRQ
 /* IRQ stack memory (calculated at run-time) */
 .globl IRQ_STACK_START
diff --git a/arch/arm/cpu/arm720t/tegra-common/Makefile b/arch/arm/cpu/arm720t/tegra-common/Makefile
index 37ec43f163..a9c2b675ae 100644
--- a/arch/arm/cpu/arm720t/tegra-common/Makefile
+++ b/arch/arm/cpu/arm720t/tegra-common/Makefile
@@ -7,26 +7,5 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)libtegra-common.o
-
-COBJS-$(CONFIG_SPL_BUILD) += spl.o
-COBJS-y	+= cpu.o
-
-SRCS	:= $(COBJS-y:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS-y))
-
-all:	$(obj).depend $(LIB)
-
-$(LIB):	$(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-$(CONFIG_SPL_BUILD) += spl.o
+obj-y	+= cpu.o
diff --git a/arch/arm/cpu/arm720t/tegra-common/cpu.c b/arch/arm/cpu/arm720t/tegra-common/cpu.c
index 9294611be8..168f525ec7 100644
--- a/arch/arm/cpu/arm720t/tegra-common/cpu.c
+++ b/arch/arm/cpu/arm720t/tegra-common/cpu.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2010-2012, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2010-2014, NVIDIA CORPORATION.  All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms and conditions of the GNU General Public License,
@@ -49,57 +49,107 @@ int get_num_cpus(void)
  * Timing tables for each SOC for all four oscillator options.
  */
 struct clk_pll_table tegra_pll_x_table[TEGRA_SOC_CNT][CLOCK_OSC_FREQ_COUNT] = {
-	/* T20: 1 GHz */
-	/*  n,  m, p, cpcon */
-	{{ 1000, 13, 0, 12},	/* OSC 13M */
-	 { 625,  12, 0, 8},	/* OSC 19.2M */
-	 { 1000, 12, 0, 12},	/* OSC 12M */
-	 { 1000, 26, 0, 12},	/* OSC 26M */
+	/*
+	 * T20: 1 GHz
+	 *
+	 * Register   Field  Bits   Width
+	 * ------------------------------
+	 * PLLX_BASE  p      22:20    3
+	 * PLLX_BASE  n      17: 8   10
+	 * PLLX_BASE  m       4: 0    5
+	 * PLLX_MISC  cpcon  11: 8    4
+	 */
+	{
+		{ .n = 1000, .m = 13, .p = 0, .cpcon = 12 }, /* OSC: 13.0 MHz */
+		{ .n =  625, .m = 12, .p = 0, .cpcon =  8 }, /* OSC: 19.2 MHz */
+		{ .n = 1000, .m = 12, .p = 0, .cpcon = 12 }, /* OSC: 12.0 MHz */
+		{ .n = 1000, .m = 26, .p = 0, .cpcon = 12 }, /* OSC: 26.0 MHz */
 	},
-
-	/* T25: 1.2 GHz */
-	{{ 923, 10, 0, 12},
-	 { 750, 12, 0, 8},
-	 { 600,  6, 0, 12},
-	 { 600, 13, 0, 12},
+	/*
+	 * T25: 1.2 GHz
+	 *
+	 * Register   Field  Bits   Width
+	 * ------------------------------
+	 * PLLX_BASE  p      22:20    3
+	 * PLLX_BASE  n      17: 8   10
+	 * PLLX_BASE  m       4: 0    5
+	 * PLLX_MISC  cpcon  11: 8    4
+	 */
+	{
+		{ .n = 923, .m = 10, .p = 0, .cpcon = 12 }, /* OSC: 13.0 MHz */
+		{ .n = 750, .m = 12, .p = 0, .cpcon =  8 }, /* OSC: 19.2 MHz */
+		{ .n = 600, .m =  6, .p = 0, .cpcon = 12 }, /* OSC: 12.0 MHz */
+		{ .n = 600, .m = 13, .p = 0, .cpcon = 12 }, /* OSC: 26.0 MHz */
 	},
-
-	/* T30: 1.4 GHz */
-	{{ 862, 8, 0, 8},
-	 { 583, 8, 0, 4},
-	 { 700, 6, 0, 8},
-	 { 700, 13, 0, 8},
+	/*
+	 * T30: 1.4 GHz
+	 *
+	 * Register   Field  Bits   Width
+	 * ------------------------------
+	 * PLLX_BASE  p      22:20    3
+	 * PLLX_BASE  n      17: 8   10
+	 * PLLX_BASE  m       4: 0    5
+	 * PLLX_MISC  cpcon  11: 8    4
+	 */
+	{
+		{ .n = 862, .m =  8, .p = 0, .cpcon = 8 }, /* OSC: 13.0 MHz */
+		{ .n = 583, .m =  8, .p = 0, .cpcon = 4 }, /* OSC: 19.2 MHz */
+		{ .n = 700, .m =  6, .p = 0, .cpcon = 8 }, /* OSC: 12.0 MHz */
+		{ .n = 700, .m = 13, .p = 0, .cpcon = 8 }, /* OSC: 26.0 MHz */
+	},
+	/*
+	 * T114: 700 MHz
+	 *
+	 * Register   Field  Bits   Width
+	 * ------------------------------
+	 * PLLX_BASE  p      23:20    4
+	 * PLLX_BASE  n      15: 8    8
+	 * PLLX_BASE  m       7: 0    8
+	 */
+	{
+		{ .n = 108, .m = 1, .p = 1 }, /* OSC: 13.0 MHz */
+		{ .n =  73, .m = 1, .p = 1 }, /* OSC: 19.2 MHz */
+		{ .n = 116, .m = 1, .p = 1 }, /* OSC: 12.0 MHz */
+		{ .n = 108, .m = 2, .p = 1 }, /* OSC: 26.0 MHz */
 	},
 
-	/* T114: 1.4 GHz */
-	{{ 862, 8, 0, 8},
-	 { 583, 8, 0, 4},
-	 { 696, 12, 0, 8},
-	 { 700, 13, 0, 8},
+	/*
+	 * T124: 700 MHz
+	 *
+	 * Register   Field  Bits   Width
+	 * ------------------------------
+	 * PLLX_BASE  p      23:20    4
+	 * PLLX_BASE  n      15: 8    8
+	 * PLLX_BASE  m       7: 0    8
+	 */
+	{
+		{ .n = 108, .m = 1, .p = 1 }, /* OSC: 13.0 MHz */
+		{ .n =  73, .m = 1, .p = 1 }, /* OSC: 19.2 MHz */
+		{ .n = 116, .m = 1, .p = 1 }, /* OSC: 12.0 MHz */
+		{ .n = 108, .m = 2, .p = 1 }, /* OSC: 26.0 MHz */
 	},
 };
 
-void adjust_pllp_out_freqs(void)
+static inline void pllx_set_iddq(void)
 {
+#if defined(CONFIG_TEGRA124)
 	struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
-	struct clk_pll *pll = &clkrst->crc_pll[CLOCK_ID_PERIPH];
 	u32 reg;
 
-	/* Set T30 PLLP_OUT1, 2, 3 & 4 freqs to 9.6, 48, 102 & 204MHz */
-	reg = readl(&pll->pll_out[0]);	/* OUTA, contains OUT2 / OUT1 */
-	reg |= (IN_408_OUT_48_DIVISOR << PLLP_OUT2_RATIO) | PLLP_OUT2_OVR
-		| (IN_408_OUT_9_6_DIVISOR << PLLP_OUT1_RATIO) | PLLP_OUT1_OVR;
-	writel(reg, &pll->pll_out[0]);
-
-	reg = readl(&pll->pll_out[1]);   /* OUTB, contains OUT4 / OUT3 */
-	reg |= (IN_408_OUT_204_DIVISOR << PLLP_OUT4_RATIO) | PLLP_OUT4_OVR
-		| (IN_408_OUT_102_DIVISOR << PLLP_OUT3_RATIO) | PLLP_OUT3_OVR;
-	writel(reg, &pll->pll_out[1]);
+	/* Disable IDDQ */
+	reg = readl(&clkrst->crc_pllx_misc3);
+	reg &= ~PLLX_IDDQ_MASK;
+	writel(reg, &clkrst->crc_pllx_misc3);
+	udelay(2);
+	debug("%s: IDDQ: PLLX IDDQ = 0x%08X\n", __func__,
+	      readl(&clkrst->crc_pllx_misc3));
+#endif
 }
 
 int pllx_set_rate(struct clk_pll_simple *pll , u32 divn, u32 divm,
 		u32 divp, u32 cpcon)
 {
+	int chip = tegra_get_chip();
 	u32 reg;
 
 	/* If PLLX is already enabled, just return */
@@ -110,31 +160,41 @@ int pllx_set_rate(struct clk_pll_simple *pll , u32 divn, u32 divm,
 
 	debug(" pllx_set_rate entry\n");
 
+	pllx_set_iddq();
+
 	/* Set BYPASS, m, n and p to PLLX_BASE */
 	reg = PLL_BYPASS_MASK | (divm << PLL_DIVM_SHIFT);
 	reg |= ((divn << PLL_DIVN_SHIFT) | (divp << PLL_DIVP_SHIFT));
 	writel(reg, &pll->pll_base);
 
 	/* Set cpcon to PLLX_MISC */
-	reg = (cpcon << PLL_CPCON_SHIFT);
+	if (chip == CHIPID_TEGRA20 || chip == CHIPID_TEGRA30)
+		reg = (cpcon << PLL_CPCON_SHIFT);
+	else
+		reg = 0;
 
 	/* Set dccon to PLLX_MISC if freq > 600MHz */
 	if (divn > 600)
 		reg |= (1 << PLL_DCCON_SHIFT);
 	writel(reg, &pll->pll_misc);
 
-	/* Enable PLLX */
-	reg = readl(&pll->pll_base);
-	reg |= PLL_ENABLE_MASK;
-
 	/* Disable BYPASS */
+	reg = readl(&pll->pll_base);
 	reg &= ~PLL_BYPASS_MASK;
 	writel(reg, &pll->pll_base);
+	debug("pllx_set_rate: base = 0x%08X\n", reg);
 
 	/* Set lock_enable to PLLX_MISC */
 	reg = readl(&pll->pll_misc);
 	reg |= PLL_LOCK_ENABLE_MASK;
 	writel(reg, &pll->pll_misc);
+	debug("pllx_set_rate: misc = 0x%08X\n", reg);
+
+	/* Enable PLLX last, once it's all configured */
+	reg = readl(&pll->pll_base);
+	reg |= PLL_ENABLE_MASK;
+	writel(reg, &pll->pll_base);
+	debug("pllx_set_rate: base final = 0x%08X\n", reg);
 
 	return 0;
 }
@@ -168,12 +228,6 @@ void init_pllx(void)
 	/* set pllx */
 	sel = &tegra_pll_x_table[chip_sku][osc];
 	pllx_set_rate(pll, sel->n, sel->m, sel->p, sel->cpcon);
-
-	/* adjust PLLP_out1-4 on T3x/T114 */
-	if (soc_type >= CHIPID_TEGRA30) {
-		debug("  init_pllx: adjusting PLLP out freqs\n");
-		adjust_pllp_out_freqs();
-	}
 }
 
 void enable_cpu_clock(int enable)
@@ -295,7 +349,6 @@ void reset_A9_cpu(int reset)
 void clock_enable_coresight(int enable)
 {
 	u32 rst, src = 2;
-	int soc_type;
 
 	debug("clock_enable_coresight entry\n");
 	clock_set_enable(PERIPH_ID_CORESIGHT, enable);
@@ -304,20 +357,11 @@ void clock_enable_coresight(int enable)
 	if (enable) {
 		/*
 		 * Put CoreSight on PLLP_OUT0 and divide it down as per
-		 * PLLP base frequency based on SoC type (T20/T30/T114).
+		 * PLLP base frequency based on SoC type (T20/T30+).
 		 * Clock divider request would setup CSITE clock as 144MHz
 		 * for PLLP base 216MHz and 204MHz for PLLP base 408MHz
 		 */
-
-		soc_type = tegra_get_chip();
-		if (soc_type == CHIPID_TEGRA30 || soc_type == CHIPID_TEGRA114)
-			src = CLK_DIVIDER(NVBL_PLLP_KHZ, 204000);
-		else if (soc_type == CHIPID_TEGRA20)
-			src = CLK_DIVIDER(NVBL_PLLP_KHZ, 144000);
-		else
-			printf("%s: Unknown SoC type %X!\n",
-				 __func__, soc_type);
-
+		src = CLK_DIVIDER(NVBL_PLLP_KHZ, CSITE_KHZ);
 		clock_ll_set_source_divisor(PERIPH_ID_CSI, 0, src);
 
 		/* Unlock the CPU CoreSight interfaces */
@@ -334,8 +378,7 @@ void clock_enable_coresight(int enable)
 void halt_avp(void)
 {
 	for (;;) {
-		writel((HALT_COP_EVENT_JTAG | HALT_COP_EVENT_IRQ_1 \
-			| HALT_COP_EVENT_FIQ_1 | (FLOW_MODE_STOP<<29)),
-			FLOW_CTLR_HALT_COP_EVENTS);
+		writel(HALT_COP_EVENT_JTAG | (FLOW_MODE_STOP << 29),
+		       FLOW_CTLR_HALT_COP_EVENTS);
 	}
 }
diff --git a/arch/arm/cpu/arm720t/tegra-common/cpu.h b/arch/arm/cpu/arm720t/tegra-common/cpu.h
index 60412c7f87..b4ca44fce1 100644
--- a/arch/arm/cpu/arm720t/tegra-common/cpu.h
+++ b/arch/arm/cpu/arm720t/tegra-common/cpu.h
@@ -1,5 +1,5 @@
 /*
- * (C) Copyright 2010-2011
+ * (C) Copyright 2010-2014
  * NVIDIA Corporation <www.nvidia.com>
  *
  * SPDX-License-Identifier:	GPL-2.0+
@@ -11,9 +11,12 @@
 #define IO_STABILIZATION_DELAY	(1000)
 
 #if defined(CONFIG_TEGRA20)
-#define NVBL_PLLP_KHZ	(216000)
-#elif defined(CONFIG_TEGRA30) || defined(CONFIG_TEGRA114)
-#define NVBL_PLLP_KHZ	(408000)
+#define NVBL_PLLP_KHZ	216000
+#define CSITE_KHZ	144000
+#elif defined(CONFIG_TEGRA30) || defined(CONFIG_TEGRA114) || \
+	defined(CONFIG_TEGRA124)
+#define NVBL_PLLP_KHZ	408000
+#define CSITE_KHZ	204000
 #else
 #error "Unknown Tegra chip!"
 #endif
@@ -68,3 +71,4 @@ int tegra_get_chip(void);
 int tegra_get_sku_info(void);
 int tegra_get_chip_sku(void);
 void adjust_pllp_out_freqs(void);
+void pmic_enable_cpu_vdd(void);
diff --git a/arch/arm/cpu/arm720t/tegra114/Makefile b/arch/arm/cpu/arm720t/tegra114/Makefile
index 6cf7fe9da9..ea3e55ea62 100644
--- a/arch/arm/cpu/arm720t/tegra114/Makefile
+++ b/arch/arm/cpu/arm720t/tegra114/Makefile
@@ -17,26 +17,5 @@
 # along with this program.  If not, see <http://www.gnu.org/licenses/>.
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(SOC).o
-
-#COBJS-y	+= cpu.o t11x.o
-COBJS-y	+= cpu.o
-
-SRCS	:= $(COBJS-y:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS-y))
-
-all:	$(obj).depend $(LIB)
-
-$(LIB):	$(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+#obj-y	+= cpu.o t11x.o
+obj-y	+= cpu.o
diff --git a/arch/arm/cpu/arm720t/tegra114/config.mk b/arch/arm/cpu/arm720t/tegra114/config.mk
deleted file mode 100644
index 7947b50fd0..0000000000
--- a/arch/arm/cpu/arm720t/tegra114/config.mk
+++ /dev/null
@@ -1,19 +0,0 @@
-#
-# Copyright (c) 2010-2013, NVIDIA CORPORATION.  All rights reserved.
-#
-# (C) Copyright 2002
-# Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
-#
-# This program is free software; you can redistribute it and/or modify it
-# under the terms and conditions of the GNU General Public License,
-# version 2, as published by the Free Software Foundation.
-#
-# This program is distributed in the hope it will be useful, but WITHOUT
-# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-# FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
-# more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program.  If not, see <http://www.gnu.org/licenses/>.
-#
-USE_PRIVATE_LIBGCC = yes
diff --git a/arch/arm/cpu/arm720t/tegra114/cpu.c b/arch/arm/cpu/arm720t/tegra114/cpu.c
index 51ecff794f..d10b96a1d4 100644
--- a/arch/arm/cpu/arm720t/tegra114/cpu.c
+++ b/arch/arm/cpu/arm720t/tegra114/cpu.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2010-2013, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2010-2014, NVIDIA CORPORATION.  All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms and conditions of the GNU General Public License,
@@ -68,7 +68,7 @@ static void enable_cpu_clocks(void)
 	/* Wait for PLL-X to lock */
 	do {
 		reg = readl(&clkrst->crc_pll_simple[SIMPLE_PLLX].pll_base);
-	} while ((reg & (1 << 27)) == 0);
+	} while ((reg & PLL_LOCK_MASK) == 0);
 
 	/* Wait until all clocks are stable */
 	udelay(PLL_STABILIZATION_DELAY);
@@ -126,18 +126,6 @@ void t114_init_clocks(void)
 	/* Set active CPU cluster to G */
 	clrbits_le32(&flow->cluster_control, 1);
 
-	/*
-	 * Switch system clock to PLLP_OUT4 (108 MHz), AVP will now run
-	 * at 108 MHz. This is glitch free as only the source is changed, no
-	 * special precaution needed.
-	 */
-	val = (SCLK_SOURCE_PLLP_OUT4 << SCLK_SWAKEUP_FIQ_SOURCE_SHIFT) |
-		(SCLK_SOURCE_PLLP_OUT4 << SCLK_SWAKEUP_IRQ_SOURCE_SHIFT) |
-		(SCLK_SOURCE_PLLP_OUT4 << SCLK_SWAKEUP_RUN_SOURCE_SHIFT) |
-		(SCLK_SOURCE_PLLP_OUT4 << SCLK_SWAKEUP_IDLE_SOURCE_SHIFT) |
-		(SCLK_SYS_STATE_RUN << SCLK_SYS_STATE_SHIFT);
-	writel(val, &clkrst->crc_sclk_brst_pol);
-
 	writel(SUPER_SCLK_ENB_MASK, &clkrst->crc_super_sclk_div);
 
 	debug("Setting up PLLX\n");
@@ -204,45 +192,43 @@ void t114_init_clocks(void)
 	debug("t114_init_clocks exit\n");
 }
 
-static int is_partition_powered(u32 mask)
+static bool is_partition_powered(u32 partid)
 {
 	struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
 	u32 reg;
 
 	/* Get power gate status */
 	reg = readl(&pmc->pmc_pwrgate_status);
-	return (reg & mask) == mask;
+	return !!(reg & (1 << partid));
 }
 
-static int is_clamp_enabled(u32 mask)
+static bool is_clamp_enabled(u32 partid)
 {
 	struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
 	u32 reg;
 
-	/* Get clamp status. TODO: Add pmc_clamp_status alias to pmc.h */
-	reg = readl(&pmc->pmc_pwrgate_timer_on);
-	return (reg & mask) == mask;
+	/* Get clamp status. */
+	reg = readl(&pmc->pmc_clamp_status);
+	return !!(reg & (1 << partid));
 }
 
-static void power_partition(u32 status, u32 partid)
+static void power_partition(u32 partid)
 {
 	struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
 
-	debug("%s: status = %08X, part ID = %08X\n", __func__, status, partid);
+	debug("%s: part ID = %08X\n", __func__, partid);
 	/* Is the partition already on? */
-	if (!is_partition_powered(status)) {
+	if (!is_partition_powered(partid)) {
 		/* No, toggle the partition power state (OFF -> ON) */
 		debug("power_partition, toggling state\n");
-		clrbits_le32(&pmc->pmc_pwrgate_toggle, 0x1F);
-		setbits_le32(&pmc->pmc_pwrgate_toggle, partid);
-		setbits_le32(&pmc->pmc_pwrgate_toggle, START_CP);
+		writel(START_CP | partid, &pmc->pmc_pwrgate_toggle);
 
 		/* Wait for the power to come up */
-		while (!is_partition_powered(status))
+		while (!is_partition_powered(partid))
 			;
 
 		/* Wait for the clamp status to be cleared */
-		while (is_clamp_enabled(status))
+		while (is_clamp_enabled(partid))
 			;
 
 		/* Give I/O signals time to stabilize */
@@ -257,13 +243,13 @@ void powerup_cpus(void)
 	/* We boot to the fast cluster */
 	debug("powerup_cpus entry: G cluster\n");
 	/* Power up the fast cluster rail partition */
-	power_partition(CRAIL, CRAILID);
+	power_partition(CRAIL);
 
 	/* Power up the fast cluster non-CPU partition */
-	power_partition(C0NC, C0NCID);
+	power_partition(C0NC);
 
 	/* Power up the fast cluster CPU0 partition */
-	power_partition(CE0, CE0ID);
+	power_partition(CE0);
 }
 
 void start_cpu(u32 reset_vector)
diff --git a/arch/arm/cpu/arm720t/tegra124/Makefile b/arch/arm/cpu/arm720t/tegra124/Makefile
new file mode 100644
index 0000000000..61abf45d3d
--- /dev/null
+++ b/arch/arm/cpu/arm720t/tegra124/Makefile
@@ -0,0 +1,8 @@
+#
+# (C) Copyright 2013-2014
+# NVIDIA Corporation <www.nvidia.com>
+#
+# SPDX-License-Identifier:     GPL-2.0+
+#
+
+obj-y	+= cpu.o
diff --git a/arch/arm/cpu/arm720t/tegra124/cpu.c b/arch/arm/cpu/arm720t/tegra124/cpu.c
new file mode 100644
index 0000000000..97f5928bd7
--- /dev/null
+++ b/arch/arm/cpu/arm720t/tegra124/cpu.c
@@ -0,0 +1,265 @@
+/*
+ * (C) Copyright 2013
+ * NVIDIA Corporation <www.nvidia.com>
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/ahb.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/flow.h>
+#include <asm/arch/pinmux.h>
+#include <asm/arch/tegra.h>
+#include <asm/arch-tegra/clk_rst.h>
+#include <asm/arch-tegra/pmc.h>
+#include <asm/arch-tegra/ap.h>
+#include "../tegra-common/cpu.h"
+
+/* Tegra124-specific CPU init code */
+
+static void enable_cpu_power_rail(void)
+{
+	struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
+
+	debug("enable_cpu_power_rail entry\n");
+
+	/* un-tristate PWR_I2C SCL/SDA, rest of the defaults are correct */
+	pinmux_tristate_disable(PINGRP_PWR_I2C_SCL);
+	pinmux_tristate_disable(PINGRP_PWR_I2C_SDA);
+
+	pmic_enable_cpu_vdd();
+
+	/*
+	 * Set CPUPWRGOOD_TIMER - APB clock is 1/2 of SCLK (102MHz),
+	 * set it for 5ms as per SysEng (102MHz*5ms = 510000 (7C830h).
+	 */
+	writel(0x7C830, &pmc->pmc_cpupwrgood_timer);
+
+	/* Set polarity to 0 (normal) and enable CPUPWRREQ_OE */
+	clrbits_le32(&pmc->pmc_cntrl, CPUPWRREQ_POL);
+	setbits_le32(&pmc->pmc_cntrl, CPUPWRREQ_OE);
+}
+
+static void enable_cpu_clocks(void)
+{
+	struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
+	u32 reg;
+
+	debug("enable_cpu_clocks entry\n");
+
+	/* Wait for PLL-X to lock */
+	do {
+		reg = readl(&clkrst->crc_pll_simple[SIMPLE_PLLX].pll_base);
+		debug("%s: PLLX base = 0x%08X\n", __func__, reg);
+	} while ((reg & PLL_LOCK_MASK) == 0);
+
+	debug("%s: PLLX locked, delay for stable clocks\n", __func__);
+	/* Wait until all clocks are stable */
+	udelay(PLL_STABILIZATION_DELAY);
+
+	debug("%s: Setting CCLK_BURST and DIVIDER\n", __func__);
+	writel(CCLK_BURST_POLICY, &clkrst->crc_cclk_brst_pol);
+	writel(SUPER_CCLK_DIVIDER, &clkrst->crc_super_cclk_div);
+
+	debug("%s: Enabling clock to all CPUs\n", __func__);
+	/* Enable the clock to all CPUs */
+	reg = CLR_CPU3_CLK_STP | CLR_CPU2_CLK_STP | CLR_CPU1_CLK_STP |
+		CLR_CPU0_CLK_STP;
+	writel(reg, &clkrst->crc_clk_cpu_cmplx_clr);
+
+	debug("%s: Enabling main CPU complex clocks\n", __func__);
+	/* Always enable the main CPU complex clocks */
+	clock_enable(PERIPH_ID_CPU);
+	clock_enable(PERIPH_ID_CPULP);
+	clock_enable(PERIPH_ID_CPUG);
+
+	debug("%s: Done\n", __func__);
+}
+
+static void remove_cpu_resets(void)
+{
+	struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
+	u32 reg;
+
+	debug("remove_cpu_resets entry\n");
+
+	/* Take the slow and fast partitions out of reset */
+	reg = CLR_NONCPURESET;
+	writel(reg, &clkrst->crc_rst_cpulp_cmplx_clr);
+	writel(reg, &clkrst->crc_rst_cpug_cmplx_clr);
+
+	/* Clear the SW-controlled reset of the slow cluster */
+	reg = CLR_CPURESET0 | CLR_DBGRESET0 | CLR_CORERESET0 | CLR_CXRESET0 |
+		CLR_L2RESET | CLR_PRESETDBG;
+	writel(reg, &clkrst->crc_rst_cpulp_cmplx_clr);
+
+	/* Clear the SW-controlled reset of the fast cluster */
+	reg = CLR_CPURESET0 | CLR_DBGRESET0 | CLR_CORERESET0 | CLR_CXRESET0 |
+		CLR_CPURESET1 | CLR_DBGRESET1 | CLR_CORERESET1 | CLR_CXRESET1 |
+		CLR_CPURESET2 | CLR_DBGRESET2 | CLR_CORERESET2 | CLR_CXRESET2 |
+		CLR_CPURESET3 | CLR_DBGRESET3 | CLR_CORERESET3 | CLR_CXRESET3 |
+		CLR_L2RESET | CLR_PRESETDBG;
+	writel(reg, &clkrst->crc_rst_cpug_cmplx_clr);
+}
+
+/**
+ * The Tegra124 requires some special clock initialization, including setting up
+ * the DVC I2C, turning on MSELECT and selecting the G CPU cluster
+ */
+void tegra124_init_clocks(void)
+{
+	struct flow_ctlr *flow = (struct flow_ctlr *)NV_PA_FLOW_BASE;
+	struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
+	struct clk_rst_ctlr *clkrst =
+			(struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
+	u32 val;
+
+	debug("tegra124_init_clocks entry\n");
+
+	/* Set active CPU cluster to G */
+	clrbits_le32(&flow->cluster_control, 1);
+
+	/* Change the oscillator drive strength */
+	val = readl(&clkrst->crc_osc_ctrl);
+	val &= ~OSC_XOFS_MASK;
+	val |= (OSC_DRIVE_STRENGTH << OSC_XOFS_SHIFT);
+	writel(val, &clkrst->crc_osc_ctrl);
+
+	/* Update same value in PMC_OSC_EDPD_OVER XOFS field for warmboot */
+	val = readl(&pmc->pmc_osc_edpd_over);
+	val &= ~PMC_XOFS_MASK;
+	val |= (OSC_DRIVE_STRENGTH << PMC_XOFS_SHIFT);
+	writel(val, &pmc->pmc_osc_edpd_over);
+
+	/* Set HOLD_CKE_LOW_EN to 1 */
+	setbits_le32(&pmc->pmc_cntrl2, HOLD_CKE_LOW_EN);
+
+	debug("Setting up PLLX\n");
+	init_pllx();
+
+	val = (1 << CLK_SYS_RATE_AHB_RATE_SHIFT);
+	writel(val, &clkrst->crc_clk_sys_rate);
+
+	/* Enable clocks to required peripherals. TBD - minimize this list */
+	debug("Enabling clocks\n");
+
+	clock_set_enable(PERIPH_ID_CACHE2, 1);
+	clock_set_enable(PERIPH_ID_GPIO, 1);
+	clock_set_enable(PERIPH_ID_TMR, 1);
+	clock_set_enable(PERIPH_ID_CPU, 1);
+	clock_set_enable(PERIPH_ID_EMC, 1);
+	clock_set_enable(PERIPH_ID_I2C5, 1);
+	clock_set_enable(PERIPH_ID_APBDMA, 1);
+	clock_set_enable(PERIPH_ID_MEM, 1);
+	clock_set_enable(PERIPH_ID_CORESIGHT, 1);
+	clock_set_enable(PERIPH_ID_MSELECT, 1);
+	clock_set_enable(PERIPH_ID_DVFS, 1);
+
+	/*
+	 * Set MSELECT clock source as PLLP (00), and ask for a clock
+	 * divider that would set the MSELECT clock at 102MHz for a
+	 * PLLP base of 408MHz.
+	 */
+	clock_ll_set_source_divisor(PERIPH_ID_MSELECT, 0,
+				    CLK_DIVIDER(NVBL_PLLP_KHZ, 102000));
+
+	/* Give clock time to stabilize */
+	udelay(IO_STABILIZATION_DELAY);
+
+	/* I2C5 (DVC) gets CLK_M and a divisor of 17 */
+	clock_ll_set_source_divisor(PERIPH_ID_I2C5, 3, 16);
+
+	/* Give clock time to stabilize */
+	udelay(IO_STABILIZATION_DELAY);
+
+	/* Take required peripherals out of reset */
+	debug("Taking periphs out of reset\n");
+	reset_set_enable(PERIPH_ID_CACHE2, 0);
+	reset_set_enable(PERIPH_ID_GPIO, 0);
+	reset_set_enable(PERIPH_ID_TMR, 0);
+	reset_set_enable(PERIPH_ID_COP, 0);
+	reset_set_enable(PERIPH_ID_EMC, 0);
+	reset_set_enable(PERIPH_ID_I2C5, 0);
+	reset_set_enable(PERIPH_ID_APBDMA, 0);
+	reset_set_enable(PERIPH_ID_MEM, 0);
+	reset_set_enable(PERIPH_ID_CORESIGHT, 0);
+	reset_set_enable(PERIPH_ID_MSELECT, 0);
+	reset_set_enable(PERIPH_ID_DVFS, 0);
+
+	debug("tegra124_init_clocks exit\n");
+}
+
+static bool is_partition_powered(u32 partid)
+{
+	struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
+	u32 reg;
+
+	/* Get power gate status */
+	reg = readl(&pmc->pmc_pwrgate_status);
+	return !!(reg & (1 << partid));
+}
+
+static void power_partition(u32 partid)
+{
+	struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
+
+	debug("%s: part ID = %08X\n", __func__, partid);
+	/* Is the partition already on? */
+	if (!is_partition_powered(partid)) {
+		/* No, toggle the partition power state (OFF -> ON) */
+		debug("power_partition, toggling state\n");
+		writel(START_CP | partid, &pmc->pmc_pwrgate_toggle);
+
+		/* Wait for the power to come up */
+		while (!is_partition_powered(partid))
+			;
+
+		/* Give I/O signals time to stabilize */
+		udelay(IO_STABILIZATION_DELAY);
+	}
+}
+
+void powerup_cpus(void)
+{
+	debug("powerup_cpus entry\n");
+
+	/* We boot to the fast cluster */
+	debug("powerup_cpus entry: G cluster\n");
+
+	/* Power up the fast cluster rail partition */
+	debug("powerup_cpus: CRAIL\n");
+	power_partition(CRAIL);
+
+	/* Power up the fast cluster non-CPU partition */
+	debug("powerup_cpus: C0NC\n");
+	power_partition(C0NC);
+
+	/* Power up the fast cluster CPU0 partition */
+	debug("powerup_cpus: CE0\n");
+	power_partition(CE0);
+
+	debug("powerup_cpus: done\n");
+}
+
+void start_cpu(u32 reset_vector)
+{
+	struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
+
+	debug("start_cpu entry, reset_vector = %x\n", reset_vector);
+
+	tegra124_init_clocks();
+
+	/* Set power-gating timer multiplier */
+	writel((MULT_8 << TIMER_MULT_SHIFT) | (MULT_8 << TIMER_MULT_CPU_SHIFT),
+	       &pmc->pmc_pwrgate_timer_mult);
+
+	enable_cpu_power_rail();
+	enable_cpu_clocks();
+	clock_enable_coresight(1);
+	remove_cpu_resets();
+	writel(reset_vector, EXCEP_VECTOR_CPU_RESET_VECTOR);
+	powerup_cpus();
+	debug("start_cpu exit, should continue @ reset_vector\n");
+}
diff --git a/arch/arm/cpu/arm720t/tegra20/Makefile b/arch/arm/cpu/arm720t/tegra20/Makefile
index eef5922da7..12243fa9be 100644
--- a/arch/arm/cpu/arm720t/tegra20/Makefile
+++ b/arch/arm/cpu/arm720t/tegra20/Makefile
@@ -7,25 +7,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(SOC).o
-
-COBJS-y	+= cpu.o
-
-SRCS	:= $(COBJS-y:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS-y))
-
-all:	$(obj).depend $(LIB)
-
-$(LIB):	$(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	+= cpu.o
diff --git a/arch/arm/cpu/arm720t/tegra20/config.mk b/arch/arm/cpu/arm720t/tegra20/config.mk
deleted file mode 100644
index e073345223..0000000000
--- a/arch/arm/cpu/arm720t/tegra20/config.mk
+++ /dev/null
@@ -1,10 +0,0 @@
-#
-# (C) Copyright 2010,2011
-# NVIDIA Corporation <www.nvidia.com>
-#
-# (C) Copyright 2002
-# Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-USE_PRIVATE_LIBGCC = yes
diff --git a/arch/arm/cpu/arm720t/tegra30/Makefile b/arch/arm/cpu/arm720t/tegra30/Makefile
index bd969976e9..6ff4c55213 100644
--- a/arch/arm/cpu/arm720t/tegra30/Makefile
+++ b/arch/arm/cpu/arm720t/tegra30/Makefile
@@ -17,25 +17,4 @@
 # along with this program.  If not, see <http://www.gnu.org/licenses/>.
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(SOC).o
-
-COBJS-y	+= cpu.o
-
-SRCS	:= $(COBJS-y:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS-y))
-
-all:	$(obj).depend $(LIB)
-
-$(LIB):	$(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	+= cpu.o
diff --git a/arch/arm/cpu/arm720t/tegra30/config.mk b/arch/arm/cpu/arm720t/tegra30/config.mk
deleted file mode 100644
index 2388c56db7..0000000000
--- a/arch/arm/cpu/arm720t/tegra30/config.mk
+++ /dev/null
@@ -1,19 +0,0 @@
-#
-# Copyright (c) 2010-2012, NVIDIA CORPORATION.  All rights reserved.
-#
-# (C) Copyright 2002
-# Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
-#
-# This program is free software; you can redistribute it and/or modify it
-# under the terms and conditions of the GNU General Public License,
-# version 2, as published by the Free Software Foundation.
-#
-# This program is distributed in the hope it will be useful, but WITHOUT
-# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-# FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
-# more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program.  If not, see <http://www.gnu.org/licenses/>.
-#
-USE_PRIVATE_LIBGCC = yes
diff --git a/arch/arm/cpu/arm720t/tegra30/cpu.c b/arch/arm/cpu/arm720t/tegra30/cpu.c
index e162357484..a80648389c 100644
--- a/arch/arm/cpu/arm720t/tegra30/cpu.c
+++ b/arch/arm/cpu/arm720t/tegra30/cpu.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2010-2012, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2010-2014, NVIDIA CORPORATION.  All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms and conditions of the GNU General Public License,
@@ -84,18 +84,6 @@ void t30_init_clocks(void)
 	/* Set active CPU cluster to G */
 	clrbits_le32(flow->cluster_control, 1 << 0);
 
-	/*
-	 * Switch system clock to PLLP_OUT4 (108 MHz), AVP will now run
-	 * at 108 MHz. This is glitch free as only the source is changed, no
-	 * special precaution needed.
-	 */
-	val = (SCLK_SOURCE_PLLP_OUT4 << SCLK_SWAKEUP_FIQ_SOURCE_SHIFT) |
-		(SCLK_SOURCE_PLLP_OUT4 << SCLK_SWAKEUP_IRQ_SOURCE_SHIFT) |
-		(SCLK_SOURCE_PLLP_OUT4 << SCLK_SWAKEUP_RUN_SOURCE_SHIFT) |
-		(SCLK_SOURCE_PLLP_OUT4 << SCLK_SWAKEUP_IDLE_SOURCE_SHIFT) |
-		(SCLK_SYS_STATE_RUN << SCLK_SYS_STATE_SHIFT);
-	writel(val, &clkrst->crc_sclk_brst_pol);
-
 	writel(SUPER_SCLK_ENB_MASK, &clkrst->crc_super_sclk_div);
 
 	val = (0 << CLK_SYS_RATE_HCLK_DISABLE_SHIFT) |
diff --git a/arch/arm/cpu/arm920t/Makefile b/arch/arm/cpu/arm920t/Makefile
index 4758f025a0..aac8043f6a 100644
--- a/arch/arm/cpu/arm920t/Makefile
+++ b/arch/arm/cpu/arm920t/Makefile
@@ -5,29 +5,7 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
+extra-y	= start.o
 
-LIB	= $(obj)lib$(CPU).o
-
-START	= start.o
-
-COBJS-y	+= cpu.o
-COBJS-$(CONFIG_USE_IRQ)	+= interrupts.o
-
-SRCS	:= $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS-y) $(SOBJS))
-START	:= $(addprefix $(obj),$(START))
-
-all:	$(obj).depend $(START) $(LIB)
-
-$(LIB):	$(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	+= cpu.o
+obj-$(CONFIG_USE_IRQ)	+= interrupts.o
diff --git a/arch/arm/cpu/arm920t/a320/Makefile b/arch/arm/cpu/arm920t/a320/Makefile
index 88c7d9bb71..bbdab588c5 100644
--- a/arch/arm/cpu/arm920t/a320/Makefile
+++ b/arch/arm/cpu/arm920t/a320/Makefile
@@ -5,26 +5,5 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(SOC).o
-
-SOBJS	+= reset.o
-COBJS	+= timer.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS))
-
-all:	$(obj).depend $(LIB)
-
-$(LIB):	$(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	+= reset.o
+obj-y	+= timer.o
diff --git a/arch/arm/cpu/arm920t/at91/Makefile b/arch/arm/cpu/arm920t/at91/Makefile
index b2b1e56a96..561b4b4cbb 100644
--- a/arch/arm/cpu/arm920t/at91/Makefile
+++ b/arch/arm/cpu/arm920t/at91/Makefile
@@ -5,30 +5,9 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(SOC).o
-
-SOBJS	+= lowlevel_init.o
-COBJS	+= reset.o
-COBJS	+= timer.o
-COBJS	+= clock.o
-COBJS	+= cpu.o
-COBJS	+= at91rm9200_devices.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS))
-
-all:	$(obj).depend $(LIB)
-
-$(LIB):	$(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	+= lowlevel_init.o
+obj-y	+= reset.o
+obj-y	+= timer.o
+obj-y	+= clock.o
+obj-y	+= cpu.o
+obj-y	+= at91rm9200_devices.o
diff --git a/arch/arm/cpu/arm920t/config.mk b/arch/arm/cpu/arm920t/config.mk
index 67537dcedc..799afff028 100644
--- a/arch/arm/cpu/arm920t/config.mk
+++ b/arch/arm/cpu/arm920t/config.mk
@@ -6,10 +6,3 @@
 #
 
 PLATFORM_CPPFLAGS += -march=armv4
-# =========================================================================
-#
-# Supply options according to compiler version
-#
-# =========================================================================
-PF_RELFLAGS_SLB_AT := $(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,))
-PLATFORM_RELFLAGS += $(PF_RELFLAGS_SLB_AT)
diff --git a/arch/arm/cpu/arm920t/ep93xx/Makefile b/arch/arm/cpu/arm920t/ep93xx/Makefile
index 7a75c86ae4..638333a484 100644
--- a/arch/arm/cpu/arm920t/ep93xx/Makefile
+++ b/arch/arm/cpu/arm920t/ep93xx/Makefile
@@ -16,26 +16,6 @@
 #
 # SPDX-License-Identifier:	GPL-2.0+
 #
-include $(TOPDIR)/config.mk
 
-LIB = $(obj)lib$(SOC).o
-
-COBJS   = cpu.o led.o speed.o timer.o
-SOBJS   = lowlevel_init.o
-
-SRCS    := $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS    := $(addprefix $(obj),$(SOBJS) $(COBJS))
-
-all:    $(obj).depend $(LIB)
-
-$(LIB): $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y   = cpu.o led.o speed.o timer.o
+obj-y   += lowlevel_init.o
diff --git a/arch/arm/cpu/arm920t/ep93xx/u-boot.lds b/arch/arm/cpu/arm920t/ep93xx/u-boot.lds
index 4bed4fcdd7..96994043e4 100644
--- a/arch/arm/cpu/arm920t/ep93xx/u-boot.lds
+++ b/arch/arm/cpu/arm920t/ep93xx/u-boot.lds
@@ -50,5 +50,8 @@ SECTIONS
 	.bss : { *(.bss*) }
 	__bss_end = .;
 
-	_end = .;
+	.end :
+	{
+		*(.__end)
+	}
 }
diff --git a/arch/arm/cpu/arm920t/imx/Makefile b/arch/arm/cpu/arm920t/imx/Makefile
index c9c85b8740..54ce646d97 100644
--- a/arch/arm/cpu/arm920t/imx/Makefile
+++ b/arch/arm/cpu/arm920t/imx/Makefile
@@ -5,27 +5,6 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(SOC).o
-
-COBJS	+= generic.o
-COBJS	+= speed.o
-COBJS	+= timer.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS))
-
-all:	$(obj).depend $(LIB)
-
-$(LIB):	$(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	+= generic.o
+obj-y	+= speed.o
+obj-y	+= timer.o
diff --git a/arch/arm/cpu/arm920t/ks8695/Makefile b/arch/arm/cpu/arm920t/ks8695/Makefile
index eef053050a..400aa89e99 100644
--- a/arch/arm/cpu/arm920t/ks8695/Makefile
+++ b/arch/arm/cpu/arm920t/ks8695/Makefile
@@ -5,27 +5,5 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(SOC).o
-
-SOBJS	= lowlevel_init.o
-
-COBJS	= timer.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS))
-
-all:	$(obj).depend $(LIB)
-
-$(LIB):	$(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	= lowlevel_init.o
+obj-y	+= timer.o
diff --git a/arch/arm/cpu/arm920t/s3c24x0/Makefile b/arch/arm/cpu/arm920t/s3c24x0/Makefile
index 97175330ec..e44c549ba0 100644
--- a/arch/arm/cpu/arm920t/s3c24x0/Makefile
+++ b/arch/arm/cpu/arm920t/s3c24x0/Makefile
@@ -5,28 +5,7 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(SOC).o
-
-COBJS-$(CONFIG_USE_IRQ) += interrupts.o
-COBJS-$(CONFIG_DISPLAY_CPUINFO)	+= cpu_info.o
-COBJS-y	+= speed.o
-COBJS-y	+= timer.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
-OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS-y))
-
-all:	$(obj).depend $(LIB)
-
-$(LIB):	$(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-$(CONFIG_USE_IRQ) += interrupts.o
+obj-$(CONFIG_DISPLAY_CPUINFO)	+= cpu_info.o
+obj-y	+= speed.o
+obj-y	+= timer.o
diff --git a/arch/arm/cpu/arm920t/start.S b/arch/arm/cpu/arm920t/start.S
index a67b659fd0..7bf094aec1 100644
--- a/arch/arm/cpu/arm920t/start.S
+++ b/arch/arm/cpu/arm920t/start.S
@@ -55,32 +55,6 @@ _fiq:			.word fiq
  *************************************************************************
  */
 
-.globl _TEXT_BASE
-_TEXT_BASE:
-#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_TEXT_BASE)
-	.word	CONFIG_SPL_TEXT_BASE
-#else
-	.word	CONFIG_SYS_TEXT_BASE
-#endif
-
-/*
- * These are defined in the board-specific linker script.
- * Subtracting _start from them lets the linker put their
- * relative position in the executable instead of leaving
- * them null.
- */
-.globl _bss_start_ofs
-_bss_start_ofs:
-	.word __bss_start - _start
-
-.globl _bss_end_ofs
-_bss_end_ofs:
-	.word __bss_end - _start
-
-.globl _end_ofs
-_end_ofs:
-	.word _end - _start
-
 #ifdef CONFIG_USE_IRQ
 /* IRQ stack memory (calculated at run-time) */
 .globl IRQ_STACK_START
diff --git a/arch/arm/cpu/arm926ejs/Makefile b/arch/arm/cpu/arm926ejs/Makefile
index b4c214c704..125299537f 100644
--- a/arch/arm/cpu/arm926ejs/Makefile
+++ b/arch/arm/cpu/arm926ejs/Makefile
@@ -5,33 +5,11 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(CPU).o
-
-START	= start.o
-COBJS	= cpu.o cache.o
+extra-y	= start.o
+obj-y	= cpu.o cache.o
 
 ifdef	CONFIG_SPL_BUILD
 ifdef	CONFIG_SPL_NO_CPU_SUPPORT_CODE
-START	:=
+extra-y	:=
 endif
 endif
-
-SRCS	:= $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS) $(SOBJS))
-START	:= $(addprefix $(obj),$(START))
-
-all:	$(obj).depend $(START) $(LIB)
-
-$(LIB):	$(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
diff --git a/arch/arm/cpu/arm926ejs/armada100/Makefile b/arch/arm/cpu/arm926ejs/armada100/Makefile
index a1a6df0bca..fca98ef42f 100644
--- a/arch/arm/cpu/arm926ejs/armada100/Makefile
+++ b/arch/arm/cpu/arm926ejs/armada100/Makefile
@@ -6,25 +6,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(SOC).o
-
-COBJS-y	= cpu.o timer.o dram.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
-OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS-y))
-
-all:	$(obj).depend $(LIB)
-
-$(LIB):	$(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	= cpu.o timer.o dram.o
diff --git a/arch/arm/cpu/arm926ejs/at91/Makefile b/arch/arm/cpu/arm926ejs/at91/Makefile
index 9faec912b4..698a28dc5d 100644
--- a/arch/arm/cpu/arm926ejs/at91/Makefile
+++ b/arch/arm/cpu/arm926ejs/at91/Makefile
@@ -5,46 +5,25 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(SOC).o
-
-COBJS-$(CONFIG_AT91CAP9)	+= at91cap9_devices.o
-COBJS-$(CONFIG_AT91SAM9260)	+= at91sam9260_devices.o
-COBJS-$(CONFIG_AT91SAM9G20)	+= at91sam9260_devices.o
-COBJS-$(CONFIG_AT91SAM9XE)	+= at91sam9260_devices.o
-COBJS-$(CONFIG_AT91SAM9261)	+= at91sam9261_devices.o
-COBJS-$(CONFIG_AT91SAM9G10)	+= at91sam9261_devices.o
-COBJS-$(CONFIG_AT91SAM9263)	+= at91sam9263_devices.o
-COBJS-$(CONFIG_AT91SAM9RL)	+= at91sam9rl_devices.o
-COBJS-$(CONFIG_AT91SAM9M10G45)	+= at91sam9m10g45_devices.o
-COBJS-$(CONFIG_AT91SAM9G45)	+= at91sam9m10g45_devices.o
-COBJS-$(CONFIG_AT91SAM9N12)	+= at91sam9n12_devices.o
-COBJS-$(CONFIG_AT91SAM9X5)	+= at91sam9x5_devices.o
-COBJS-$(CONFIG_AT91_EFLASH)	+= eflash.o
-COBJS-$(CONFIG_AT91_LED)	+= led.o
-COBJS-y += clock.o
-COBJS-y += cpu.o
-COBJS-y	+= reset.o
-COBJS-y	+= timer.o
+obj-$(CONFIG_AT91CAP9)	+= at91cap9_devices.o
+obj-$(CONFIG_AT91SAM9260)	+= at91sam9260_devices.o
+obj-$(CONFIG_AT91SAM9G20)	+= at91sam9260_devices.o
+obj-$(CONFIG_AT91SAM9XE)	+= at91sam9260_devices.o
+obj-$(CONFIG_AT91SAM9261)	+= at91sam9261_devices.o
+obj-$(CONFIG_AT91SAM9G10)	+= at91sam9261_devices.o
+obj-$(CONFIG_AT91SAM9263)	+= at91sam9263_devices.o
+obj-$(CONFIG_AT91SAM9RL)	+= at91sam9rl_devices.o
+obj-$(CONFIG_AT91SAM9M10G45)	+= at91sam9m10g45_devices.o
+obj-$(CONFIG_AT91SAM9G45)	+= at91sam9m10g45_devices.o
+obj-$(CONFIG_AT91SAM9N12)	+= at91sam9n12_devices.o
+obj-$(CONFIG_AT91SAM9X5)	+= at91sam9x5_devices.o
+obj-$(CONFIG_AT91_EFLASH)	+= eflash.o
+obj-$(CONFIG_AT91_LED)	+= led.o
+obj-y += clock.o
+obj-y += cpu.o
+obj-y	+= reset.o
+obj-y	+= timer.o
 
 ifndef CONFIG_SKIP_LOWLEVEL_INIT
-SOBJS-y	:= lowlevel_init.o
+obj-y	+= lowlevel_init.o
 endif
-
-SRCS    := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
-OBJS    := $(addprefix $(obj),$(SOBJS-y) $(COBJS-y))
-
-all:	$(obj).depend $(LIB)
-
-$(LIB):	$(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
diff --git a/arch/arm/cpu/arm926ejs/at91/at91sam9263_devices.c b/arch/arm/cpu/arm926ejs/at91/at91sam9263_devices.c
index 99a39134de..6b51d5f355 100644
--- a/arch/arm/cpu/arm926ejs/at91/at91sam9263_devices.c
+++ b/arch/arm/cpu/arm926ejs/at91/at91sam9263_devices.c
@@ -143,6 +143,31 @@ void at91_spi1_hw_init(unsigned long cs_mask)
 }
 #endif
 
+#if defined(CONFIG_GENERIC_ATMEL_MCI)
+void at91_mci_hw_init(void)
+{
+	/* Enable mci clock */
+	struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
+	writel(1 << ATMEL_ID_MCI1, &pmc->pcer);
+
+	at91_set_a_periph(AT91_PIO_PORTA, 6, PUP);	/* MCI1_CK */
+
+#if defined(CONFIG_ATMEL_MCI_PORTB)
+	at91_set_a_periph(AT91_PIO_PORTA, 21, PUP);	/* MCI1_CDB */
+	at91_set_a_periph(AT91_PIO_PORTA, 22, PUP);	/* MCI1_DB0 */
+	at91_set_a_periph(AT91_PIO_PORTA, 23, PUP);	/* MCI1_DB1 */
+	at91_set_a_periph(AT91_PIO_PORTA, 24, PUP);	/* MCI1_DB2 */
+	at91_set_a_periph(AT91_PIO_PORTA, 25, PUP);	/* MCI1_DB3 */
+#else
+	at91_set_a_periph(AT91_PIO_PORTA, 7, PUP);	/* MCI1_CDA */
+	at91_set_a_periph(AT91_PIO_PORTA, 8, PUP);	/* MCI1_DA0 */
+	at91_set_a_periph(AT91_PIO_PORTA, 9, PUP);	/* MCI1_DA1 */
+	at91_set_a_periph(AT91_PIO_PORTA, 10, PUP);	/* MCI1_DA2 */
+	at91_set_a_periph(AT91_PIO_PORTA, 11, PUP);	/* MCI1_DA3 */
+#endif
+}
+#endif
+
 #ifdef CONFIG_MACB
 void at91_macb_hw_init(void)
 {
diff --git a/arch/arm/cpu/arm926ejs/at91/led.c b/arch/arm/cpu/arm926ejs/at91/led.c
index 5dd90487ed..46ed055023 100644
--- a/arch/arm/cpu/arm926ejs/at91/led.c
+++ b/arch/arm/cpu/arm926ejs/at91/led.c
@@ -7,43 +7,41 @@
  */
 
 #include <common.h>
-#include <asm/io.h>
-#include <asm/arch/at91_pmc.h>
-#include <asm/arch/at91_pio.h>
+#include <asm/gpio.h>
 #include <asm/arch/gpio.h>
 
 #ifdef CONFIG_RED_LED
 void red_led_on(void)
 {
-	at91_set_gpio_value(CONFIG_RED_LED, 1);
+	gpio_set_value(CONFIG_RED_LED, 1);
 }
 
 void red_led_off(void)
 {
-	at91_set_gpio_value(CONFIG_RED_LED, 0);
+	gpio_set_value(CONFIG_RED_LED, 0);
 }
 #endif
 
 #ifdef CONFIG_GREEN_LED
 void green_led_on(void)
 {
-	at91_set_gpio_value(CONFIG_GREEN_LED, 0);
+	gpio_set_value(CONFIG_GREEN_LED, 0);
 }
 
 void green_led_off(void)
 {
-	at91_set_gpio_value(CONFIG_GREEN_LED, 1);
+	gpio_set_value(CONFIG_GREEN_LED, 1);
 }
 #endif
 
 #ifdef CONFIG_YELLOW_LED
 void yellow_led_on(void)
 {
-	at91_set_gpio_value(CONFIG_YELLOW_LED, 0);
+	gpio_set_value(CONFIG_YELLOW_LED, 0);
 }
 
 void yellow_led_off(void)
 {
-	at91_set_gpio_value(CONFIG_YELLOW_LED, 1);
+	gpio_set_value(CONFIG_YELLOW_LED, 1);
 }
 #endif
diff --git a/arch/arm/cpu/arm926ejs/at91/lowlevel_init.S b/arch/arm/cpu/arm926ejs/at91/lowlevel_init.S
index e83968fb7a..a9ec81a75c 100644
--- a/arch/arm/cpu/arm926ejs/at91/lowlevel_init.S
+++ b/arch/arm/cpu/arm926ejs/at91/lowlevel_init.S
@@ -26,27 +26,18 @@
 #define CONFIG_SYS_MATRIX_EBICSA_VAL CONFIG_SYS_MATRIX_EBI0CSA_VAL
 #endif
 
-_TEXT_BASE:
-	.word	CONFIG_SYS_TEXT_BASE
-
 .globl lowlevel_init
 .type lowlevel_init,function
 lowlevel_init:
 
-	mov	r5, pc		/* r5 = POS1 + 4 current */
 POS1:
+	adr	r5, POS1	/* r5 = POS1 run time */
 	ldr	r0, =POS1	/* r0 = POS1 compile */
-	ldr	r2, _TEXT_BASE
-	sub	r0, r0, r2	/* r0 = POS1-_TEXT_BASE (POS1 relative) */
 	sub	r5, r5, r0	/* r0 = CONFIG_SYS_TEXT_BASE-1 */
-	sub	r5, r5, #4	/* r1 = text base - current */
 
 	/* memory control configuration 1 */
 	ldr	r0, =SMRDATA
 	ldr	r2, =SMRDATA1
-	ldr	r1, _TEXT_BASE
-	sub	r0, r0, r1
-	sub	r2, r2, r1
 	add	r0, r0, r5
 	add	r2, r2, r5
 0:
@@ -149,9 +140,6 @@ PLL_setup_end:
 
 	ldr	r0, =SMRDATA1
 	ldr	r2, =SMRDATA2
-	ldr	r1, _TEXT_BASE
-	sub	r0, r0, r1
-	sub	r2, r2, r1
 	add	r0, r0, r5
 	add	r2, r2, r5
 2:
diff --git a/arch/arm/cpu/arm926ejs/config.mk b/arch/arm/cpu/arm926ejs/config.mk
index 12b0d09d37..bdb3da183e 100644
--- a/arch/arm/cpu/arm926ejs/config.mk
+++ b/arch/arm/cpu/arm926ejs/config.mk
@@ -6,20 +6,3 @@
 #
 
 PLATFORM_CPPFLAGS += -march=armv5te
-# =========================================================================
-#
-# Supply options according to compiler version
-#
-# =========================================================================
-PF_RELFLAGS_SLB_AT := $(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,))
-PLATFORM_RELFLAGS += $(PF_RELFLAGS_SLB_AT)
-
-ifneq ($(CONFIG_IMX_CONFIG),)
-ifdef CONFIG_SPL
-ifdef CONFIG_SPL_BUILD
-ALL-y	+= $(OBJTREE)/SPL
-endif
-else
-ALL-y	+= $(obj)u-boot.imx
-endif
-endif
diff --git a/arch/arm/cpu/arm926ejs/davinci/Makefile b/arch/arm/cpu/arm926ejs/davinci/Makefile
index b596818fec..7d67191de8 100644
--- a/arch/arm/cpu/arm926ejs/davinci/Makefile
+++ b/arch/arm/cpu/arm926ejs/davinci/Makefile
@@ -7,44 +7,22 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(SOC).o
-
-COBJS-y				+= cpu.o misc.o timer.o psc.o pinmux.o reset.o
-COBJS-$(CONFIG_DA850_LOWLEVEL)	+= da850_lowlevel.o
-COBJS-$(CONFIG_SOC_DM355)	+= dm355.o
-COBJS-$(CONFIG_SOC_DM365)	+= dm365.o
-COBJS-$(CONFIG_SOC_DM644X)	+= dm644x.o
-COBJS-$(CONFIG_SOC_DM646X)	+= dm646x.o
-COBJS-$(CONFIG_SOC_DA830)	+= da830_pinmux.o
-COBJS-$(CONFIG_SOC_DA850)	+= da850_pinmux.o
-COBJS-$(CONFIG_DRIVER_TI_EMAC)	+= lxt972.o dp83848.o et1011c.o ksz8873.o
+obj-y				+= cpu.o misc.o timer.o psc.o pinmux.o reset.o
+obj-$(CONFIG_DA850_LOWLEVEL)	+= da850_lowlevel.o
+obj-$(CONFIG_SOC_DM355)	+= dm355.o
+obj-$(CONFIG_SOC_DM365)	+= dm365.o
+obj-$(CONFIG_SOC_DM644X)	+= dm644x.o
+obj-$(CONFIG_SOC_DM646X)	+= dm646x.o
+obj-$(CONFIG_SOC_DA830)	+= da830_pinmux.o
+obj-$(CONFIG_SOC_DA850)	+= da850_pinmux.o
+obj-$(CONFIG_DRIVER_TI_EMAC)	+= lxt972.o dp83848.o et1011c.o ksz8873.o
 
 ifdef CONFIG_SPL_BUILD
-COBJS-$(CONFIG_SPL_FRAMEWORK)	+= spl.o
-COBJS-$(CONFIG_SOC_DM365)	+= dm365_lowlevel.o
-COBJS-$(CONFIG_SOC_DA8XX)	+= da850_lowlevel.o
+obj-$(CONFIG_SPL_FRAMEWORK)	+= spl.o
+obj-$(CONFIG_SOC_DM365)	+= dm365_lowlevel.o
+obj-$(CONFIG_SOC_DA8XX)	+= da850_lowlevel.o
 endif
 
 ifndef CONFIG_SKIP_LOWLEVEL_INIT
-SOBJS	+= lowlevel_init.o
+obj-y	+= lowlevel_init.o
 endif
-
-SRCS	:= $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS-y) $(SOBJS))
-START	:= $(addprefix $(obj),$(START))
-
-all:	$(obj).depend $(LIB)
-
-$(LIB):	$(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
diff --git a/arch/arm/cpu/arm926ejs/davinci/config.mk b/arch/arm/cpu/arm926ejs/davinci/config.mk
index d5c978b446..69e9d5ab21 100644
--- a/arch/arm/cpu/arm926ejs/davinci/config.mk
+++ b/arch/arm/cpu/arm926ejs/davinci/config.mk
@@ -4,5 +4,5 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 ifndef CONFIG_SPL_BUILD
-ALL-$(CONFIG_SPL_FRAMEWORK)	+= $(obj)u-boot.ais
+ALL-$(CONFIG_SPL_FRAMEWORK)	+= u-boot.ais
 endif
diff --git a/arch/arm/cpu/arm926ejs/kirkwood/Makefile b/arch/arm/cpu/arm926ejs/kirkwood/Makefile
index 20ccf201b7..c230ce8994 100644
--- a/arch/arm/cpu/arm926ejs/kirkwood/Makefile
+++ b/arch/arm/cpu/arm926ejs/kirkwood/Makefile
@@ -6,29 +6,8 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(SOC).o
-
-COBJS-y	= cpu.o
-COBJS-y	+= dram.o
-COBJS-y	+= mpp.o
-COBJS-y	+= timer.o
-COBJS-y	+= cache.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
-OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS-y))
-
-all:	$(obj).depend $(LIB)
-
-$(LIB):	$(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	= cpu.o
+obj-y	+= dram.o
+obj-y	+= mpp.o
+obj-y	+= timer.o
+obj-y	+= cache.o
diff --git a/arch/arm/cpu/arm926ejs/lpc32xx/Makefile b/arch/arm/cpu/arm926ejs/lpc32xx/Makefile
index 603051a64e..314f004eba 100644
--- a/arch/arm/cpu/arm926ejs/lpc32xx/Makefile
+++ b/arch/arm/cpu/arm926ejs/lpc32xx/Makefile
@@ -5,25 +5,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB     = $(obj)lib$(SOC).o
-
-COBJS   = cpu.o clk.o devices.o timer.o
-
-SRCS    := $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS    := $(addprefix $(obj),$(COBJS) $(SOBJS))
-
-all:    $(obj).depend $(LIB)
-
-$(LIB): $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y   = cpu.o clk.o devices.o timer.o
diff --git a/arch/arm/cpu/arm926ejs/mb86r0x/Makefile b/arch/arm/cpu/arm926ejs/mb86r0x/Makefile
index a780dfe3a2..365892c413 100644
--- a/arch/arm/cpu/arm926ejs/mb86r0x/Makefile
+++ b/arch/arm/cpu/arm926ejs/mb86r0x/Makefile
@@ -5,27 +5,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(SOC).o
-
-COBJS	= clock.o reset.o timer.o
-SOBJS	=
-
-SRCS	:= $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS) $(SOBJS))
-START	:= $(addprefix $(obj),$(START))
-
-all:	$(obj).depend $(LIB)
-
-$(LIB):	$(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	= clock.o reset.o timer.o
diff --git a/arch/arm/cpu/arm926ejs/mb86r0x/asm-offsets.c b/arch/arm/cpu/arm926ejs/mb86r0x/asm-offsets.c
deleted file mode 100644
index 5fe8fa204b..0000000000
--- a/arch/arm/cpu/arm926ejs/mb86r0x/asm-offsets.c
+++ /dev/null
@@ -1,62 +0,0 @@
-/*
- * Adapted from Linux v2.6.36 kernel: arch/powerpc/kernel/asm-offsets.c
- *
- * This program is used to generate definitions needed by
- * assembly language modules.
- *
- * We use the technique used in the OSF Mach kernel code:
- * generate asm statements containing #defines,
- * compile this file to assembler, and then extract the
- * #defines from the assembly-language output.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/arch/mb86r0x.h>
-
-#include <linux/kbuild.h>
-
-int main(void)
-{
-	/* ddr2 controller */
-	DEFINE(DDR2_DRIC, offsetof(struct mb86r0x_ddr2c, dric));
-	DEFINE(DDR2_DRIC1, offsetof(struct mb86r0x_ddr2c, dric1));
-	DEFINE(DDR2_DRIC2, offsetof(struct mb86r0x_ddr2c, dric2));
-	DEFINE(DDR2_DRCA, offsetof(struct mb86r0x_ddr2c, drca));
-	DEFINE(DDR2_DRCM, offsetof(struct mb86r0x_ddr2c, drcm));
-	DEFINE(DDR2_DRCST1, offsetof(struct mb86r0x_ddr2c, drcst1));
-	DEFINE(DDR2_DRCST2, offsetof(struct mb86r0x_ddr2c, drcst2));
-	DEFINE(DDR2_DRCR, offsetof(struct mb86r0x_ddr2c, drcr));
-	DEFINE(DDR2_DRCF, offsetof(struct mb86r0x_ddr2c, drcf));
-	DEFINE(DDR2_DRASR, offsetof(struct mb86r0x_ddr2c, drasr));
-	DEFINE(DDR2_DRIMS, offsetof(struct mb86r0x_ddr2c, drims));
-	DEFINE(DDR2_DROS, offsetof(struct mb86r0x_ddr2c, dros));
-	DEFINE(DDR2_DRIBSODT1, offsetof(struct mb86r0x_ddr2c, dribsodt1));
-	DEFINE(DDR2_DROABA, offsetof(struct mb86r0x_ddr2c, droaba));
-	DEFINE(DDR2_DROBS, offsetof(struct mb86r0x_ddr2c, drobs));
-
-	/* clock reset generator */
-	DEFINE(CRG_CRPR, offsetof(struct mb86r0x_crg, crpr));
-	DEFINE(CRG_CRHA, offsetof(struct mb86r0x_crg, crha));
-	DEFINE(CRG_CRPA, offsetof(struct mb86r0x_crg, crpa));
-	DEFINE(CRG_CRPB, offsetof(struct mb86r0x_crg, crpb));
-	DEFINE(CRG_CRHB, offsetof(struct mb86r0x_crg, crhb));
-	DEFINE(CRG_CRAM, offsetof(struct mb86r0x_crg, cram));
-
-	/* chip control module */
-	DEFINE(CCNT_CDCRC, offsetof(struct mb86r0x_ccnt, cdcrc));
-
-	/* external bus interface */
-	DEFINE(MEMC_MCFMODE0, offsetof(struct mb86r0x_memc, mcfmode[0]));
-	DEFINE(MEMC_MCFMODE2, offsetof(struct mb86r0x_memc, mcfmode[2]));
-	DEFINE(MEMC_MCFMODE4, offsetof(struct mb86r0x_memc, mcfmode[4]));
-	DEFINE(MEMC_MCFTIM0, offsetof(struct mb86r0x_memc, mcftim[0]));
-	DEFINE(MEMC_MCFTIM2, offsetof(struct mb86r0x_memc, mcftim[2]));
-	DEFINE(MEMC_MCFTIM4, offsetof(struct mb86r0x_memc, mcftim[4]));
-	DEFINE(MEMC_MCFAREA0, offsetof(struct mb86r0x_memc, mcfarea[0]));
-	DEFINE(MEMC_MCFAREA2, offsetof(struct mb86r0x_memc, mcfarea[2]));
-	DEFINE(MEMC_MCFAREA4, offsetof(struct mb86r0x_memc, mcfarea[4]));
-
-	return 0;
-}
diff --git a/arch/arm/cpu/arm926ejs/mx25/Makefile b/arch/arm/cpu/arm926ejs/mx25/Makefile
index 75a09ff54b..134c69d42d 100644
--- a/arch/arm/cpu/arm926ejs/mx25/Makefile
+++ b/arch/arm/cpu/arm926ejs/mx25/Makefile
@@ -4,25 +4,4 @@
 #
 # SPDX-License-Identifier:	GPL-2.0+
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(SOC).o
-
-COBJS	= generic.o timer.o reset.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS))
-
-all:	$(obj).depend $(LIB)
-
-$(LIB):	$(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	= generic.o timer.o reset.o
diff --git a/arch/arm/cpu/arm926ejs/mx25/asm-offsets.c b/arch/arm/cpu/arm926ejs/mx25/asm-offsets.c
deleted file mode 100644
index 0e2e8bf64e..0000000000
--- a/arch/arm/cpu/arm926ejs/mx25/asm-offsets.c
+++ /dev/null
@@ -1,57 +0,0 @@
-/*
- * Adapted from Linux v2.6.36 kernel: arch/powerpc/kernel/asm-offsets.c
- *
- * This program is used to generate definitions needed by
- * assembly language modules.
- *
- * We use the technique used in the OSF Mach kernel code:
- * generate asm statements containing #defines,
- * compile this file to assembler, and then extract the
- * #defines from the assembly-language output.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/arch/imx-regs.h>
-
-#include <linux/kbuild.h>
-
-int main(void)
-{
-	/* Clock Control Module */
-	DEFINE(CCM_CCTL, offsetof(struct ccm_regs, cctl));
-	DEFINE(CCM_CGCR0, offsetof(struct ccm_regs, cgr0));
-	DEFINE(CCM_CGCR1, offsetof(struct ccm_regs, cgr1));
-	DEFINE(CCM_CGCR2, offsetof(struct ccm_regs, cgr2));
-	DEFINE(CCM_PCDR2, offsetof(struct ccm_regs, pcdr[2]));
-	DEFINE(CCM_MCR, offsetof(struct ccm_regs, mcr));
-
-	/* Enhanced SDRAM Controller */
-	DEFINE(ESDRAMC_ESDCTL0, offsetof(struct esdramc_regs, ctl0));
-	DEFINE(ESDRAMC_ESDCFG0, offsetof(struct esdramc_regs, cfg0));
-	DEFINE(ESDRAMC_ESDMISC, offsetof(struct esdramc_regs, misc));
-
-	/* Multi-Layer AHB Crossbar Switch */
-	DEFINE(MAX_MPR0, offsetof(struct max_regs, mpr0));
-	DEFINE(MAX_SGPCR0, offsetof(struct max_regs, sgpcr0));
-	DEFINE(MAX_MPR1, offsetof(struct max_regs, mpr1));
-	DEFINE(MAX_SGPCR1, offsetof(struct max_regs, sgpcr1));
-	DEFINE(MAX_MPR2, offsetof(struct max_regs, mpr2));
-	DEFINE(MAX_SGPCR2, offsetof(struct max_regs, sgpcr2));
-	DEFINE(MAX_MPR3, offsetof(struct max_regs, mpr3));
-	DEFINE(MAX_SGPCR3, offsetof(struct max_regs, sgpcr3));
-	DEFINE(MAX_MPR4, offsetof(struct max_regs, mpr4));
-	DEFINE(MAX_SGPCR4, offsetof(struct max_regs, sgpcr4));
-	DEFINE(MAX_MGPCR0, offsetof(struct max_regs, mgpcr0));
-	DEFINE(MAX_MGPCR1, offsetof(struct max_regs, mgpcr1));
-	DEFINE(MAX_MGPCR2, offsetof(struct max_regs, mgpcr2));
-	DEFINE(MAX_MGPCR3, offsetof(struct max_regs, mgpcr3));
-	DEFINE(MAX_MGPCR4, offsetof(struct max_regs, mgpcr4));
-
-	/* AHB <-> IP-Bus Interface */
-	DEFINE(AIPS_MPR_0_7, offsetof(struct aips_regs, mpr_0_7));
-	DEFINE(AIPS_MPR_8_15, offsetof(struct aips_regs, mpr_8_15));
-
-	return 0;
-}
diff --git a/arch/arm/cpu/arm926ejs/mx25/timer.c b/arch/arm/cpu/arm926ejs/mx25/timer.c
index 42b6076c1f..7f19791736 100644
--- a/arch/arm/cpu/arm926ejs/mx25/timer.c
+++ b/arch/arm/cpu/arm926ejs/mx25/timer.c
@@ -21,65 +21,8 @@
  */
 
 #include <common.h>
-#include <div64.h>
 #include <asm/io.h>
 #include <asm/arch/imx-regs.h>
-#include <asm/arch/clock.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#define timestamp	(gd->arch.tbl)
-#define lastinc		(gd->arch.lastinc)
-
-/*
- * "time" is measured in 1 / CONFIG_SYS_HZ seconds,
- * "tick" is internal timer period
- */
-#ifdef CONFIG_MX25_TIMER_HIGH_PRECISION
-/* ~0.4% error - measured with stop-watch on 100s boot-delay */
-static inline unsigned long long tick_to_time(unsigned long long tick)
-{
-	tick *= CONFIG_SYS_HZ;
-	do_div(tick, MXC_CLK32);
-	return tick;
-}
-
-static inline unsigned long long time_to_tick(unsigned long long time)
-{
-	time *= MXC_CLK32;
-	do_div(time, CONFIG_SYS_HZ);
-	return time;
-}
-
-static inline unsigned long long us_to_tick(unsigned long long us)
-{
-	us = us * MXC_CLK32 + 999999;
-	do_div(us, 1000000);
-	return us;
-}
-#else
-/* ~2% error */
-#define TICK_PER_TIME	((MXC_CLK32 + CONFIG_SYS_HZ / 2) / CONFIG_SYS_HZ)
-#define US_PER_TICK	(1000000 / MXC_CLK32)
-
-static inline unsigned long long tick_to_time(unsigned long long tick)
-{
-	do_div(tick, TICK_PER_TIME);
-	return tick;
-}
-
-static inline unsigned long long time_to_tick(unsigned long long time)
-{
-	return time * TICK_PER_TIME;
-}
-
-static inline unsigned long long us_to_tick(unsigned long long us)
-{
-	us += US_PER_TICK - 1;
-	do_div(us, US_PER_TICK);
-	return us;
-}
-#endif
 
 /* nothing really to do with interrupts, just starts up a counter. */
 /* The 32KHz 32-bit timer overruns in 134217 seconds */
@@ -104,63 +47,3 @@ int timer_init(void)
 
 	return 0;
 }
-
-unsigned long long get_ticks(void)
-{
-	struct gpt_regs *gpt = (struct gpt_regs *)IMX_GPT1_BASE;
-	ulong now = readl(&gpt->counter); /* current tick value */
-
-	if (now >= lastinc) {
-		/*
-		 * normal mode (non roll)
-		 * move stamp forward with absolut diff ticks
-		 */
-		timestamp += (now - lastinc);
-	} else {
-		/* we have rollover of incrementer */
-		timestamp += (0xFFFFFFFF - lastinc) + now;
-	}
-	lastinc = now;
-	return timestamp;
-}
-
-ulong get_timer_masked(void)
-{
-	/*
-	 * get_ticks() returns a long long (64 bit), it wraps in
-	 * 2^64 / MXC_CLK32 = 2^64 / 2^15 = 2^49 ~ 5 * 10^14 (s) ~
-	 * 5 * 10^9 days... and get_ticks() * CONFIG_SYS_HZ wraps in
-	 * 5 * 10^6 days - long enough.
-	 */
-	return tick_to_time(get_ticks());
-}
-
-ulong get_timer(ulong base)
-{
-	return get_timer_masked() - base;
-}
-
-/* delay x useconds AND preserve advance timstamp value */
-void __udelay(unsigned long usec)
-{
-	unsigned long long tmp;
-	ulong tmo;
-
-	tmo = us_to_tick(usec);
-	tmp = get_ticks() + tmo;	/* get current timestamp */
-
-	while (get_ticks() < tmp)	/* loop till event */
-		 /*NOP*/;
-}
-
-/*
- * This function is derived from PowerPC code (timebase clock frequency).
- * On ARM it returns the number of timer ticks per second.
- */
-ulong get_tbclk(void)
-{
-	ulong tbclk;
-
-	tbclk = MXC_CLK32;
-	return tbclk;
-}
diff --git a/arch/arm/cpu/arm926ejs/mx27/Makefile b/arch/arm/cpu/arm926ejs/mx27/Makefile
index 53ffaf2856..4976bbb89b 100644
--- a/arch/arm/cpu/arm926ejs/mx27/Makefile
+++ b/arch/arm/cpu/arm926ejs/mx27/Makefile
@@ -4,25 +4,4 @@
 #
 # SPDX-License-Identifier:	GPL-2.0+
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(SOC).o
-
-COBJS	= generic.o reset.o timer.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS))
-
-all:	$(obj).depend $(LIB)
-
-$(LIB):	$(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	= generic.o reset.o timer.o
diff --git a/arch/arm/cpu/arm926ejs/mx27/asm-offsets.c b/arch/arm/cpu/arm926ejs/mx27/asm-offsets.c
deleted file mode 100644
index 629b727745..0000000000
--- a/arch/arm/cpu/arm926ejs/mx27/asm-offsets.c
+++ /dev/null
@@ -1,47 +0,0 @@
-/*
- * Adapted from Linux v2.6.36 kernel: arch/powerpc/kernel/asm-offsets.c
- *
- * This program is used to generate definitions needed by
- * assembly language modules.
- *
- * We use the technique used in the OSF Mach kernel code:
- * generate asm statements containing #defines,
- * compile this file to assembler, and then extract the
- * #defines from the assembly-language output.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/arch/imx-regs.h>
-
-#include <linux/kbuild.h>
-
-int main(void)
-{
-	DEFINE(AIPI1_PSR0, IMX_AIPI1_BASE + offsetof(struct aipi_regs, psr0));
-	DEFINE(AIPI1_PSR1, IMX_AIPI1_BASE + offsetof(struct aipi_regs, psr1));
-	DEFINE(AIPI2_PSR0, IMX_AIPI2_BASE + offsetof(struct aipi_regs, psr0));
-	DEFINE(AIPI2_PSR1, IMX_AIPI2_BASE + offsetof(struct aipi_regs, psr1));
-
-	DEFINE(CSCR, IMX_PLL_BASE + offsetof(struct pll_regs, cscr));
-	DEFINE(MPCTL0, IMX_PLL_BASE + offsetof(struct pll_regs, mpctl0));
-	DEFINE(SPCTL0, IMX_PLL_BASE + offsetof(struct pll_regs, spctl0));
-	DEFINE(PCDR0, IMX_PLL_BASE + offsetof(struct pll_regs, pcdr0));
-	DEFINE(PCDR1, IMX_PLL_BASE + offsetof(struct pll_regs, pcdr1));
-	DEFINE(PCCR0, IMX_PLL_BASE + offsetof(struct pll_regs, pccr0));
-	DEFINE(PCCR1, IMX_PLL_BASE + offsetof(struct pll_regs, pccr1));
-
-	DEFINE(ESDCTL0_ROF, offsetof(struct esdramc_regs, esdctl0));
-	DEFINE(ESDCFG0_ROF, offsetof(struct esdramc_regs, esdcfg0));
-	DEFINE(ESDCTL1_ROF, offsetof(struct esdramc_regs, esdctl1));
-	DEFINE(ESDCFG1_ROF, offsetof(struct esdramc_regs, esdcfg1));
-	DEFINE(ESDMISC_ROF, offsetof(struct esdramc_regs, esdmisc));
-
-	DEFINE(GPCR, IMX_SYSTEM_CTL_BASE +
-		offsetof(struct system_control_regs, gpcr));
-	DEFINE(FMCR, IMX_SYSTEM_CTL_BASE +
-		offsetof(struct system_control_regs, fmcr));
-
-	return 0;
-}
diff --git a/arch/arm/cpu/arm926ejs/mxs/Makefile b/arch/arm/cpu/arm926ejs/mxs/Makefile
index 3d6689252b..6c59494558 100644
--- a/arch/arm/cpu/arm926ejs/mxs/Makefile
+++ b/arch/arm/cpu/arm926ejs/mxs/Makefile
@@ -5,40 +5,81 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
+extra-$(CONFIG_SPL_BUILD) := start.o
 
-LIB	= $(obj)lib$(SOC).o
-
-COBJS	= clock.o mxs.o iomux.o timer.o
+obj-y	= clock.o mxs.o iomux.o timer.o
 
 ifdef	CONFIG_SPL_BUILD
-COBJS	+= spl_boot.o spl_lradc_init.o spl_mem_init.o spl_power_init.o
+obj-y	+= spl_boot.o spl_lradc_init.o spl_mem_init.o spl_power_init.o
 endif
 
-SRCS	:= $(START:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-START	:= $(addprefix $(obj),$(START))
+# Specify the target for use in elftosb call
+MKIMAGE_TARGET-$(CONFIG_MX23) = mxsimage.mx23.cfg
+MKIMAGE_TARGET-$(CONFIG_MX28) = mxsimage.mx28.cfg
+
+# Generate HAB-capable IVT
+#
+# Note on computing the post-IVT size field value for the U-Boot binary.
+# The value is the result of adding the following:
+#  -> The size of U-Boot binary aligned to 64B (u-boot.bin)
+#  -> The size of IVT block aligned to 64B (u-boot.ivt)
+#  -> The size of U-Boot signature (u-boot.sig), 3904 B
+#  -> The 64B hole in front of U-Boot binary for 'struct mxs_spl_data' passing
+#
+quiet_cmd_mkivt_mxs = MXSIVT  $@
+cmd_mkivt_mxs =								\
+	sz=`expr \`stat -c "%s" $^\` + 64 + 3904 + 128` ;		\
+	echo -n "0x402000d1 $2 0 0 0 $3 $4 0 $$sz 0 0 0 0 0 0 0" |	\
+	tr -s " " | xargs -d " " -i printf "%08x\n" "{}" | rev |	\
+	sed "s/\(.\)\(.\)/\\\\\\\\x\2\1\n/g" | xargs -i printf "{}" >$@
+
+# Align binary to 64B
+quiet_cmd_mkalign_mxs = MXSALGN $@
+cmd_mkalign_mxs =							\
+	dd if=$^ of=$@ ibs=64 conv=sync 2>/dev/null &&			\
+	mv $@ $^
 
-all:	$(obj).depend $(LIB)
+# Assemble the CSF file
+quiet_cmd_mkcsfreq_mxs = MXSCSFR $@
+cmd_mkcsfreq_mxs =							\
+	ivt=$(word 1,$^) ;						\
+	bin=$(word 2,$^) ;						\
+	csf=$(word 3,$^) ;						\
+	sed "s@VENDOR@$(VENDOR)@g;s@BOARD@$(BOARD)@g" "$$csf" |		\
+		sed '/^\#\#Blocks/ d' > $@ ;				\
+	echo "  Blocks = $2 0x0 `stat -c '%s' $$bin` \"$$bin\" , \\" >> $@ ; \
+	echo "           $3 0x0 0x40 \"$$ivt\"" >> $@
 
-$(LIB):	$(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
+# Sign files
+quiet_cmd_mkcst_mxs = MXSCST  $@
+cmd_mkcst_mxs = cst -o $@ < $^						\
+	$(if $(KBUILD_VERBOSE:1=), >/dev/null)
 
-# Specify the target for use in elftosb call
-ELFTOSB_TARGET-$(CONFIG_MX23) = imx23
-ELFTOSB_TARGET-$(CONFIG_MX28) = imx28
+spl/u-boot-spl.ivt: spl/u-boot-spl.bin
+	$(call if_changed,mkalign_mxs)
+	$(call if_changed,mkivt_mxs,$(CONFIG_SPL_TEXT_BASE),\
+		0x00008000,0x00008040)
+
+u-boot.ivt: u-boot.bin
+	$(call if_changed,mkalign_mxs)
+	$(call if_changed,mkivt_mxs,$(CONFIG_SYS_TEXT_BASE),\
+		0x40001000,0x40001040)
 
-$(OBJTREE)/u-boot.bd: $(SRCTREE)/$(CPUDIR)/$(SOC)/u-boot-$(ELFTOSB_TARGET-y).bd
-	sed "s@OBJTREE@$(OBJTREE)@g" $^ > $@
+spl/u-boot-spl.csf: spl/u-boot-spl.ivt spl/u-boot-spl.bin board/$(VENDOR)/$(BOARD)/sign/u-boot-spl.csf
+	$(call if_changed,mkcsfreq_mxs,$(CONFIG_SPL_TEXT_BASE),0x8000)
 
-$(OBJTREE)/u-boot.sb: $(OBJTREE)/u-boot.bin $(OBJTREE)/spl/u-boot-spl.bin $(OBJTREE)/u-boot.bd
-		elftosb -zf $(ELFTOSB_TARGET-y) -c $(OBJTREE)/u-boot.bd -o $(OBJTREE)/u-boot.sb
+u-boot.csf: u-boot.ivt u-boot.bin board/$(VENDOR)/$(BOARD)/sign/u-boot.csf
+	$(call if_changed,mkcsfreq_mxs,$(CONFIG_SYS_TEXT_BASE),0x40001000)
 
-#########################################################################
+%.sig: %.csf
+	$(call if_changed,mkcst_mxs)
 
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
+quiet_cmd_mkimage_mxs = MKIMAGE $@
+cmd_mkimage_mxs = $(objtree)/tools/mkimage -n $< -T mxsimage $@ \
+	$(if $(KBUILD_VERBOSE:1=), >/dev/null)
 
-sinclude $(obj).depend
+u-boot.sb: $(src)/$(MKIMAGE_TARGET-y) u-boot.bin spl/u-boot-spl.bin FORCE
+	$(call if_changed,mkimage_mxs)
 
-#########################################################################
+u-boot-signed.sb: $(src)/mxsimage-signed.cfg u-boot.ivt u-boot.sig spl/u-boot-spl.ivt spl/u-boot-spl.sig FORCE
+	$(call if_changed,mkimage_mxs)
diff --git a/arch/arm/cpu/arm926ejs/mxs/mxsimage-signed.cfg b/arch/arm/cpu/arm926ejs/mxs/mxsimage-signed.cfg
new file mode 100644
index 0000000000..1520bba3fb
--- /dev/null
+++ b/arch/arm/cpu/arm926ejs/mxs/mxsimage-signed.cfg
@@ -0,0 +1,10 @@
+SECTION 0x0 BOOTABLE
+ TAG LAST
+ LOAD     0x1000     spl/u-boot-spl.bin
+ LOAD     0x8000     spl/u-boot-spl.ivt
+ LOAD     0x8040     spl/u-boot-spl.sig
+ CALL HAB 0x8000     0x0
+ LOAD     0x40002000 u-boot.bin
+ LOAD     0x40001000 u-boot.ivt
+ LOAD     0x40001040 u-boot.sig
+ CALL HAB 0x40001000 0x0
diff --git a/arch/arm/cpu/arm926ejs/mxs/mxsimage.mx23.cfg b/arch/arm/cpu/arm926ejs/mxs/mxsimage.mx23.cfg
index 811876736c..55510e9cd8 100644
--- a/arch/arm/cpu/arm926ejs/mxs/mxsimage.mx23.cfg
+++ b/arch/arm/cpu/arm926ejs/mxs/mxsimage.mx23.cfg
@@ -1,6 +1,6 @@
 SECTION 0x0 BOOTABLE
  TAG LAST
- LOAD     0x0        spl/u-boot-spl.bin
- CALL     0x14       0x0
- LOAD     0x40000100 u-boot.bin
- CALL     0x40000100 0x0
+ LOAD     0x1000     spl/u-boot-spl.bin
+ CALL     0x1000     0x0
+ LOAD     0x40002000 u-boot.bin
+ CALL     0x40002000 0x0
diff --git a/arch/arm/cpu/arm926ejs/mxs/mxsimage.mx28.cfg b/arch/arm/cpu/arm926ejs/mxs/mxsimage.mx28.cfg
index ea772f0c86..bb78cb0c84 100644
--- a/arch/arm/cpu/arm926ejs/mxs/mxsimage.mx28.cfg
+++ b/arch/arm/cpu/arm926ejs/mxs/mxsimage.mx28.cfg
@@ -1,8 +1,8 @@
 SECTION 0x0 BOOTABLE
  TAG LAST
- LOAD     0x0        spl/u-boot-spl.bin
- LOAD IVT 0x8000     0x14
+ LOAD     0x1000     spl/u-boot-spl.bin
+ LOAD IVT 0x8000     0x1000
  CALL HAB 0x8000     0x0
- LOAD     0x40000100 u-boot.bin
- LOAD IVT 0x8000     0x40000100
+ LOAD     0x40002000 u-boot.bin
+ LOAD IVT 0x8000     0x40002000
  CALL HAB 0x8000     0x0
diff --git a/arch/arm/cpu/arm926ejs/mxs/spl_boot.c b/arch/arm/cpu/arm926ejs/mxs/spl_boot.c
index 68c30afc48..d3e136991a 100644
--- a/arch/arm/cpu/arm926ejs/mxs/spl_boot.c
+++ b/arch/arm/cpu/arm926ejs/mxs/spl_boot.c
@@ -13,9 +13,16 @@
 #include <asm/arch/imx-regs.h>
 #include <asm/arch/sys_proto.h>
 #include <asm/gpio.h>
+#include <linux/compiler.h>
 
 #include "mxs_init.h"
 
+DECLARE_GLOBAL_DATA_PTR;
+static gd_t gdata __section(".data");
+#ifdef CONFIG_SPL_SERIAL_SUPPORT
+static bd_t bdata __section(".data");
+#endif
+
 /*
  * This delay function is intended to be used only in early stage of boot, where
  * clock are not set up yet. The timer used here is reset on every boot and
@@ -102,6 +109,28 @@ static uint8_t mxs_get_bootmode_index(void)
 	return i;
 }
 
+static void mxs_spl_fixup_vectors(void)
+{
+	/*
+	 * Copy our vector table to 0x0, since due to HAB, we cannot
+	 * be loaded to 0x0. We want to have working vectoring though,
+	 * thus this fixup. Our vectoring table is PIC, so copying is
+	 * fine.
+	 */
+	extern uint32_t _start;
+	memcpy(0x0, &_start, 0x60);
+}
+
+static void mxs_spl_console_init(void)
+{
+#ifdef CONFIG_SPL_SERIAL_SUPPORT
+	gd->bd = &bdata;
+	gd->baudrate = CONFIG_BAUDRATE;
+	serial_init();
+	gd->have_console = 1;
+#endif
+}
+
 void mxs_common_spl_init(const uint32_t arg, const uint32_t *resptr,
 			 const iomux_cfg_t *iomux_setup,
 			 const unsigned int iomux_size)
@@ -109,8 +138,14 @@ void mxs_common_spl_init(const uint32_t arg, const uint32_t *resptr,
 	struct mxs_spl_data *data = (struct mxs_spl_data *)
 		((CONFIG_SYS_TEXT_BASE - sizeof(struct mxs_spl_data)) & ~0xf);
 	uint8_t bootmode = mxs_get_bootmode_index();
+	gd = &gdata;
+
+	mxs_spl_fixup_vectors();
 
 	mxs_iomux_setup_multiple_pads(iomux_setup, iomux_size);
+
+	mxs_spl_console_init();
+
 	mxs_power_init();
 
 	mxs_mem_init();
diff --git a/arch/arm/cpu/arm926ejs/mxs/spl_power_init.c b/arch/arm/cpu/arm926ejs/mxs/spl_power_init.c
index 8ea45be1d2..d25019a51e 100644
--- a/arch/arm/cpu/arm926ejs/mxs/spl_power_init.c
+++ b/arch/arm/cpu/arm926ejs/mxs/spl_power_init.c
@@ -654,6 +654,8 @@ static void mxs_batt_boot(void)
 	clrsetbits_le32(&power_regs->hw_power_5vctrl,
 		POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK,
 		0x8 << POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET);
+
+	mxs_power_enable_4p2();
 }
 
 /**
diff --git a/arch/arm/cpu/arm926ejs/mxs/start.S b/arch/arm/cpu/arm926ejs/mxs/start.S
index 3e454ae1bc..34a0fcb462 100644
--- a/arch/arm/cpu/arm926ejs/mxs/start.S
+++ b/arch/arm/cpu/arm926ejs/mxs/start.S
@@ -101,32 +101,6 @@ fiq:
  *************************************************************************
  */
 
-.globl _TEXT_BASE
-_TEXT_BASE:
-#ifdef CONFIG_SPL_TEXT_BASE
-	.word	CONFIG_SPL_TEXT_BASE
-#else
-	.word	CONFIG_SYS_TEXT_BASE
-#endif
-
-/*
- * These are defined in the board-specific linker script.
- * Subtracting _start from them lets the linker put their
- * relative position in the executable instead of leaving
- * them null.
- */
-.globl _bss_start_ofs
-_bss_start_ofs:
-	.word __bss_start - _start
-
-.globl _bss_end_ofs
-_bss_end_ofs:
-	.word __bss_end - _start
-
-.globl _end_ofs
-_end_ofs:
-	.word _end - _start
-
 #ifdef CONFIG_USE_IRQ
 /* IRQ stack memory (calculated at run-time) */
 .globl IRQ_STACK_START
@@ -150,6 +124,15 @@ IRQ_STACK_START_IN:
 
 _reset:
 	/*
+	 * If the CPU is configured in "Wait JTAG connection mode", the stack
+	 * pointer is not configured and is zero. This will cause crash when
+	 * trying to push data onto stack right below here. Load the SP and make
+	 * it point to the end of OCRAM if the SP is zero.
+	 */
+	cmp	sp, #0x00000000
+	ldreq	sp, =CONFIG_SYS_INIT_SP_ADDR
+
+	/*
 	 * Store all registers on old stack pointer, this will allow us later to
 	 * return to the BootROM and let the BootROM load U-Boot into RAM.
 	 *
@@ -198,6 +181,5 @@ _reset:
 	bx	lr
 
 _hang:
-	ldr	sp, _TEXT_BASE			/* switch to abort stack */
 1:
 	bl	1b				/* hang and never return */
diff --git a/arch/arm/cpu/arm926ejs/mxs/u-boot-imx23.bd b/arch/arm/cpu/arm926ejs/mxs/u-boot-imx23.bd
index 8b6c30e8e9..3a51879d5e 100644
--- a/arch/arm/cpu/arm926ejs/mxs/u-boot-imx23.bd
+++ b/arch/arm/cpu/arm926ejs/mxs/u-boot-imx23.bd
@@ -4,8 +4,8 @@ options {
 }
 
 sources {
-	u_boot_spl="OBJTREE/spl/u-boot-spl.bin";
-	u_boot="OBJTREE/u-boot.bin";
+	u_boot_spl="spl/u-boot-spl.bin";
+	u_boot="u-boot.bin";
 }
 
 section (0) {
diff --git a/arch/arm/cpu/arm926ejs/mxs/u-boot-imx28.bd b/arch/arm/cpu/arm926ejs/mxs/u-boot-imx28.bd
index a5fa6483a9..c60615a456 100644
--- a/arch/arm/cpu/arm926ejs/mxs/u-boot-imx28.bd
+++ b/arch/arm/cpu/arm926ejs/mxs/u-boot-imx28.bd
@@ -1,6 +1,6 @@
 sources {
-	u_boot_spl="OBJTREE/spl/u-boot-spl.bin";
-	u_boot="OBJTREE/u-boot.bin";
+	u_boot_spl="spl/u-boot-spl.bin";
+	u_boot="u-boot.bin";
 }
 
 section (0) {
diff --git a/arch/arm/cpu/arm926ejs/mxs/u-boot-spl.lds b/arch/arm/cpu/arm926ejs/mxs/u-boot-spl.lds
index 40bcc3132f..f4bf8ac1dd 100644
--- a/arch/arm/cpu/arm926ejs/mxs/u-boot-spl.lds
+++ b/arch/arm/cpu/arm926ejs/mxs/u-boot-spl.lds
@@ -16,7 +16,7 @@ OUTPUT_ARCH(arm)
 ENTRY(_start)
 SECTIONS
 {
-	. = 0x00000000;
+	. = CONFIG_SPL_TEXT_BASE;
 
 	. = ALIGN(4);
 	.text	:
@@ -49,13 +49,20 @@ SECTIONS
 		__bss_end = .;
 	}
 
-	_end = .;
+	.end :
+	{
+		*(.__end)
+	}
+
+	_image_binary_end = .;
 
-	/DISCARD/ : { *(.dynstr*) }
-	/DISCARD/ : { *(.dynsym*) }
-	/DISCARD/ : { *(.dynamic*) }
-	/DISCARD/ : { *(.hash*) }
-	/DISCARD/ : { *(.plt*) }
-	/DISCARD/ : { *(.interp*) }
-	/DISCARD/ : { *(.gnu*) }
+	.dynsym _image_binary_end : { *(.dynsym) }
+	.dynbss : { *(.dynbss) }
+	.dynstr : { *(.dynstr*) }
+	.dynamic : { *(.dynamic*) }
+	.hash : { *(.hash*) }
+	.plt : { *(.plt*) }
+	.interp : { *(.interp*) }
+	.gnu : { *(.gnu*) }
+	.ARM.exidx : { *(.ARM.exidx*) }
 }
diff --git a/arch/arm/cpu/arm926ejs/nomadik/Makefile b/arch/arm/cpu/arm926ejs/nomadik/Makefile
index 8896b0b106..cdf1345d58 100644
--- a/arch/arm/cpu/arm926ejs/nomadik/Makefile
+++ b/arch/arm/cpu/arm926ejs/nomadik/Makefile
@@ -5,26 +5,5 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(SOC).o
-
-COBJS	= timer.o gpio.o
-SOBJS	= reset.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS)) $(addprefix $(obj),$(SOBJS))
-
-all:	$(obj).depend $(LIB)
-
-$(LIB):	$(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	= timer.o gpio.o
+obj-y	+= reset.o
diff --git a/arch/arm/cpu/arm926ejs/omap/Makefile b/arch/arm/cpu/arm926ejs/omap/Makefile
index b519477c11..add923276c 100644
--- a/arch/arm/cpu/arm926ejs/omap/Makefile
+++ b/arch/arm/cpu/arm926ejs/omap/Makefile
@@ -5,27 +5,6 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(SOC).o
-
-COBJS	= timer.o cpuinfo.o
-SOBJS	= reset.o
-
-SRCS	:= $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS) $(SOBJS))
-START	:= $(addprefix $(obj),$(START))
-
-all:	$(obj).depend $(LIB)
-
-$(LIB):	$(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	= timer.o
+obj-$(CONFIG_DISPLAY_CPUINFO) += cpuinfo.o
+obj-y	+= reset.o
diff --git a/arch/arm/cpu/arm926ejs/omap/cpuinfo.c b/arch/arm/cpu/arm926ejs/omap/cpuinfo.c
index 02332eee0e..587d99a2bb 100644
--- a/arch/arm/cpu/arm926ejs/omap/cpuinfo.c
+++ b/arch/arm/cpu/arm926ejs/omap/cpuinfo.c
@@ -13,7 +13,7 @@
 #include <command.h>
 #include <linux/compiler.h>
 
-#if defined(CONFIG_DISPLAY_CPUINFO) && defined(CONFIG_OMAP)
+#if defined(CONFIG_OMAP)
 
 #define omap_readw(x)		*(volatile unsigned short *)(x)
 #define omap_readl(x)		*(volatile unsigned long *)(x)
@@ -239,4 +239,4 @@ int print_cpuinfo (void)
 	return 0;
 }
 
-#endif /* #if defined(CONFIG_DISPLAY_CPUINFO) && defined(CONFIG_OMAP) */
+#endif /* #if defined(CONFIG_OMAP) */
diff --git a/arch/arm/cpu/arm926ejs/orion5x/Makefile b/arch/arm/cpu/arm926ejs/orion5x/Makefile
index 8f36dc0a6d..546ebcb52e 100644
--- a/arch/arm/cpu/arm926ejs/orion5x/Makefile
+++ b/arch/arm/cpu/arm926ejs/orion5x/Makefile
@@ -9,31 +9,10 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(SOC).o
-
-COBJS-y	= cpu.o
-COBJS-y	+= dram.o
-COBJS-y	+= timer.o
+obj-y	= cpu.o
+obj-y	+= dram.o
+obj-y	+= timer.o
 
 ifndef CONFIG_SKIP_LOWLEVEL_INIT
-SOBJS	:= lowlevel_init.o
+obj-y	+= lowlevel_init.o
 endif
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
-OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS-y))
-
-all:	$(obj).depend $(LIB)
-
-$(LIB):	$(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
diff --git a/arch/arm/cpu/arm926ejs/pantheon/Makefile b/arch/arm/cpu/arm926ejs/pantheon/Makefile
index fb6bf63eed..988341f8fb 100644
--- a/arch/arm/cpu/arm926ejs/pantheon/Makefile
+++ b/arch/arm/cpu/arm926ejs/pantheon/Makefile
@@ -6,25 +6,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(SOC).o
-
-COBJS-y	= cpu.o timer.o dram.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
-OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS-y))
-
-all:	$(obj).depend $(LIB)
-
-$(LIB):	$(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	= cpu.o timer.o dram.o
diff --git a/arch/arm/cpu/arm926ejs/spear/Makefile b/arch/arm/cpu/arm926ejs/spear/Makefile
index 3006cd61e5..3f190bc0c0 100644
--- a/arch/arm/cpu/arm926ejs/spear/Makefile
+++ b/arch/arm/cpu/arm926ejs/spear/Makefile
@@ -5,37 +5,17 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(SOC).o
-
-COBJS-y	:= cpu.o \
+obj-y	:= cpu.o \
 	   reset.o \
 	   timer.o
 
 ifdef CONFIG_SPL_BUILD
-COBJS-y	+= spl.o spl_boot.o
-COBJS-$(CONFIG_SPEAR600) += spear600.o
-COBJS-$(CONFIG_DDR_MT47H64M16) += spr600_mt47h64m16_3_333_cl5_psync.o
-COBJS-$(CONFIG_DDR_MT47H32M16) += spr600_mt47h32m16_333_cl5_psync.o
-COBJS-$(CONFIG_DDR_MT47H32M16) += spr600_mt47h32m16_37e_166_cl4_sync.o
-COBJS-$(CONFIG_DDR_MT47H128M8) += spr600_mt47h128m8_3_266_cl5_async.o
+obj-y	+= spl.o spl_boot.o
+obj-$(CONFIG_SPEAR600) += spear600.o
+obj-$(CONFIG_DDR_MT47H64M16) += spr600_mt47h64m16_3_333_cl5_psync.o
+obj-$(CONFIG_DDR_MT47H32M16) += spr600_mt47h32m16_333_cl5_psync.o
+obj-$(CONFIG_DDR_MT47H32M16) += spr600_mt47h32m16_37e_166_cl4_sync.o
+obj-$(CONFIG_DDR_MT47H128M8) += spr600_mt47h128m8_3_266_cl5_async.o
 endif
 
-SRCS	:= $(START:.o=.S) $(COBJS-y:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS-y))
-START	:= $(addprefix $(obj),$(START))
-
-all:	$(obj).depend $(LIB)
-
-$(LIB):	$(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+extra-$(CONFIG_SPL_BUILD) := start.o
diff --git a/arch/arm/cpu/arm926ejs/spear/u-boot-spl.lds b/arch/arm/cpu/arm926ejs/spear/u-boot-spl.lds
index 4927736b9b..b6d0f65b66 100644
--- a/arch/arm/cpu/arm926ejs/spear/u-boot-spl.lds
+++ b/arch/arm/cpu/arm926ejs/spear/u-boot-spl.lds
@@ -49,13 +49,20 @@ SECTIONS
 		__bss_end = .;
 	}
 
-	_end = .;
-
-	/DISCARD/ : { *(.dynstr*) }
-	/DISCARD/ : { *(.dynsym*) }
-	/DISCARD/ : { *(.dynamic*) }
-	/DISCARD/ : { *(.hash*) }
-	/DISCARD/ : { *(.plt*) }
-	/DISCARD/ : { *(.interp*) }
-	/DISCARD/ : { *(.gnu*) }
+	.end :
+	{
+		*(.__end)
+	}
+
+	_image_binary_end = .;
+
+	.dynsym _image_binary_end : { *(.dynsym) }
+	.dynbss : { *(.dynbss) }
+	.dynstr : { *(.dynstr*) }
+	.dynamic : { *(.dynamic*) }
+	.hash : { *(.hash*) }
+	.plt : { *(.plt*) }
+	.interp : { *(.interp*) }
+	.gnu : { *(.gnu*) }
+	.ARM.exidx : { *(.ARM.exidx*) }
 }
diff --git a/arch/arm/cpu/arm926ejs/start.S b/arch/arm/cpu/arm926ejs/start.S
index 5360f55bc1..0717327050 100644
--- a/arch/arm/cpu/arm926ejs/start.S
+++ b/arch/arm/cpu/arm926ejs/start.S
@@ -102,32 +102,6 @@ _fiq:
  *************************************************************************
  */
 
-.globl _TEXT_BASE
-_TEXT_BASE:
-#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_TEXT_BASE)
-	.word	CONFIG_SPL_TEXT_BASE
-#else
-	.word	CONFIG_SYS_TEXT_BASE
-#endif
-
-/*
- * These are defined in the board-specific linker script.
- * Subtracting _start from them lets the linker put their
- * relative position in the executable instead of leaving
- * them null.
- */
-.globl _bss_start_ofs
-_bss_start_ofs:
-	.word __bss_start - _start
-
-.globl _bss_end_ofs
-_bss_end_ofs:
-	.word __bss_end - _start
-
-.globl _end_ofs
-_end_ofs:
-	.word _end - _start
-
 #ifdef CONFIG_USE_IRQ
 /* IRQ stack memory (calculated at run-time) */
 .globl IRQ_STACK_START
@@ -330,7 +304,6 @@ flush_dcache:
 #ifdef CONFIG_SPL_BUILD
 	.align	5
 do_hang:
-	ldr	sp, _TEXT_BASE			/* switch to abort stack */
 1:
 	bl	1b				/* hang and never return */
 #else	/* !CONFIG_SPL_BUILD */
diff --git a/arch/arm/cpu/arm926ejs/versatile/Makefile b/arch/arm/cpu/arm926ejs/versatile/Makefile
index d4659f9ce8..907f5161a8 100644
--- a/arch/arm/cpu/arm926ejs/versatile/Makefile
+++ b/arch/arm/cpu/arm926ejs/versatile/Makefile
@@ -5,27 +5,5 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(SOC).o
-
-COBJS	= timer.o
-SOBJS	= reset.o
-
-SRCS	:= $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS) $(SOBJS))
-START	:= $(addprefix $(obj),$(START))
-
-all:	$(obj).depend $(LIB)
-
-$(LIB):	$(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	= timer.o
+obj-y	+= reset.o
diff --git a/arch/arm/cpu/arm926ejs/versatile/timer.c b/arch/arm/cpu/arm926ejs/versatile/timer.c
index 870f927e5d..5d694d85ef 100644
--- a/arch/arm/cpu/arm926ejs/versatile/timer.c
+++ b/arch/arm/cpu/arm926ejs/versatile/timer.c
@@ -21,16 +21,6 @@
 
 #include <common.h>
 
-#define TIMER_LOAD_VAL 0xffffffff
-
-/* macro to read the 32 bit timer */
-#define READ_TIMER (*(volatile ulong *)(CONFIG_SYS_TIMERBASE+4))
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#define timestamp gd->arch.tbl
-#define lastdec gd->arch.lastinc
-
 #define TIMER_ENABLE	(1 << 7)
 #define TIMER_MODE_MSK	(1 << 6)
 #define TIMER_MODE_FR	(0 << 6)
@@ -69,112 +59,6 @@ int timer_init (void)
 
 	*(volatile ulong *)(CONFIG_SYS_TIMERBASE + 8) = tmr_ctrl_val;
 
-	/* init the timestamp and lastdec value */
-	reset_timer_masked();
-
 	return 0;
 }
 
-/*
- * timer without interrupts
- */
-ulong get_timer (ulong base)
-{
-	return get_timer_masked () - base;
-}
-
-/* delay x useconds AND preserve advance timestamp value */
-void __udelay (unsigned long usec)
-{
-	ulong tmo, tmp;
-
-	if(usec >= 1000){		/* if "big" number, spread normalization to seconds */
-		tmo = usec / 1000;	/* start to normalize for usec to ticks per sec */
-		tmo *= CONFIG_SYS_HZ;	/* find number of "ticks" to wait to achieve target */
-		tmo /= 1000;		/* finish normalize. */
-	}else{				/* else small number, don't kill it prior to HZ multiply */
-		tmo = usec * CONFIG_SYS_HZ;
-		tmo /= (1000*1000);
-	}
-
-	tmp = get_timer (0);		/* get current timestamp */
-	if( (tmo + tmp + 1) < tmp )	/* if setting this fordward will roll time stamp */
-		reset_timer_masked ();	/* reset "advancing" timestamp to 0, set lastdec value */
-	else
-		tmo += tmp;		/* else, set advancing stamp wake up time */
-
-	while (get_timer_masked () < tmo)/* loop till event */
-		/*NOP*/;
-}
-
-void reset_timer_masked (void)
-{
-	/* reset time */
-	lastdec = READ_TIMER;  /* capure current decrementer value time */
-	timestamp = 0;	       /* start "advancing" time stamp from 0 */
-}
-
-ulong get_timer_masked (void)
-{
-	ulong now = READ_TIMER;		/* current tick value */
-
-	if (lastdec >= now) {		/* normal mode (non roll) */
-		/* normal mode */
-		timestamp += lastdec - now; /* move stamp fordward with absoulte diff ticks */
-	} else {			/* we have overflow of the count down timer */
-		/* nts = ts + ld + (TLV - now)
-		 * ts=old stamp, ld=time that passed before passing through -1
-		 * (TLV-now) amount of time after passing though -1
-		 * nts = new "advancing time stamp"...it could also roll and cause problems.
-		 */
-		timestamp += lastdec + TIMER_LOAD_VAL - now;
-	}
-	lastdec = now;
-
-	return timestamp;
-}
-
-/* waits specified delay value and resets timestamp */
-void udelay_masked (unsigned long usec)
-{
-	ulong tmo;
-	ulong endtime;
-	signed long diff;
-
-	if (usec >= 1000) {		/* if "big" number, spread normalization to seconds */
-		tmo = usec / 1000;	/* start to normalize for usec to ticks per sec */
-		tmo *= CONFIG_SYS_HZ;		/* find number of "ticks" to wait to achieve target */
-		tmo /= 1000;		/* finish normalize. */
-	} else {			/* else small number, don't kill it prior to HZ multiply */
-		tmo = usec * CONFIG_SYS_HZ;
-		tmo /= (1000*1000);
-	}
-
-	endtime = get_timer_masked () + tmo;
-
-	do {
-		ulong now = get_timer_masked ();
-		diff = endtime - now;
-	} while (diff >= 0);
-}
-
-/*
- * This function is derived from PowerPC code (read timebase as long long).
- * On ARM it just returns the timer value.
- */
-unsigned long long get_ticks(void)
-{
-	return get_timer(0);
-}
-
-/*
- * This function is derived from PowerPC code (timebase clock frequency).
- * On ARM it returns the number of timer ticks per second.
- */
-ulong get_tbclk (void)
-{
-	ulong tbclk;
-
-	tbclk = CONFIG_SYS_HZ;
-	return tbclk;
-}
diff --git a/arch/arm/cpu/arm946es/Makefile b/arch/arm/cpu/arm946es/Makefile
index 87e6c65c7b..a44bddc2fb 100644
--- a/arch/arm/cpu/arm946es/Makefile
+++ b/arch/arm/cpu/arm946es/Makefile
@@ -5,28 +5,6 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
+extra-y	= start.o
 
-LIB	= $(obj)lib$(CPU).o
-
-START	= start.o
-
-COBJS	= cpu.o
-
-SRCS	:= $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS) $(SOBJS))
-START	:= $(addprefix $(obj),$(START))
-
-all:	$(obj).depend $(START) $(LIB)
-
-$(LIB):	$(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	= cpu.o
diff --git a/arch/arm/cpu/arm946es/config.mk b/arch/arm/cpu/arm946es/config.mk
index eb81a5708d..438668d6ff 100644
--- a/arch/arm/cpu/arm946es/config.mk
+++ b/arch/arm/cpu/arm946es/config.mk
@@ -6,10 +6,3 @@
 #
 
 PLATFORM_CPPFLAGS +=  -march=armv4
-# =========================================================================
-#
-# Supply options according to compiler version
-#
-# =========================================================================
-PF_RELFLAGS_SLB_AT := $(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,))
-PLATFORM_RELFLAGS += $(PF_RELFLAGS_SLB_AT)
diff --git a/arch/arm/cpu/arm946es/start.S b/arch/arm/cpu/arm946es/start.S
index e16b088141..7d50145836 100644
--- a/arch/arm/cpu/arm946es/start.S
+++ b/arch/arm/cpu/arm946es/start.S
@@ -71,32 +71,6 @@ _vectors_end:
  *************************************************************************
  */
 
-.globl _TEXT_BASE
-_TEXT_BASE:
-#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_TEXT_BASE)
-	.word	CONFIG_SPL_TEXT_BASE
-#else
-	.word	CONFIG_SYS_TEXT_BASE
-#endif
-
-/*
- * These are defined in the board-specific linker script.
- * Subtracting _start from them lets the linker put their
- * relative position in the executable instead of leaving
- * them null.
- */
-.globl _bss_start_ofs
-_bss_start_ofs:
-	.word __bss_start - _start
-
-.globl _bss_end_ofs
-_bss_end_ofs:
-	.word __bss_end - _start
-
-.globl _end_ofs
-_end_ofs:
-	.word _end - _start
-
 #ifdef CONFIG_USE_IRQ
 /* IRQ stack memory (calculated at run-time) */
 .globl IRQ_STACK_START
diff --git a/arch/arm/cpu/arm_intcm/Makefile b/arch/arm/cpu/arm_intcm/Makefile
index cc516f744b..3279f125f6 100644
--- a/arch/arm/cpu/arm_intcm/Makefile
+++ b/arch/arm/cpu/arm_intcm/Makefile
@@ -5,27 +5,5 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(CPU).o
-
-START	= start.o
-COBJS	= cpu.o
-
-SRCS	:= $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS) $(SOBJS))
-START	:= $(addprefix $(obj),$(START))
-
-all:	$(obj).depend $(START) $(LIB)
-
-$(LIB):	$(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+extra-y	= start.o
+obj-y	= cpu.o
diff --git a/arch/arm/cpu/arm_intcm/config.mk b/arch/arm/cpu/arm_intcm/config.mk
index eb81a5708d..438668d6ff 100644
--- a/arch/arm/cpu/arm_intcm/config.mk
+++ b/arch/arm/cpu/arm_intcm/config.mk
@@ -6,10 +6,3 @@
 #
 
 PLATFORM_CPPFLAGS +=  -march=armv4
-# =========================================================================
-#
-# Supply options according to compiler version
-#
-# =========================================================================
-PF_RELFLAGS_SLB_AT := $(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,))
-PLATFORM_RELFLAGS += $(PF_RELFLAGS_SLB_AT)
diff --git a/arch/arm/cpu/arm_intcm/start.S b/arch/arm/cpu/arm_intcm/start.S
index 5783df1ef2..7404ea7348 100644
--- a/arch/arm/cpu/arm_intcm/start.S
+++ b/arch/arm/cpu/arm_intcm/start.S
@@ -67,32 +67,6 @@ _fiq:
  *************************************************************************
  */
 
-.globl _TEXT_BASE
-_TEXT_BASE:
-#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_TEXT_BASE)
-	.word	CONFIG_SPL_TEXT_BASE
-#else
-	.word	CONFIG_SYS_TEXT_BASE
-#endif
-
-/*
- * These are defined in the board-specific linker script.
- * Subtracting _start from them lets the linker put their
- * relative position in the executable instead of leaving
- * them null.
- */
-.globl _bss_start_ofs
-_bss_start_ofs:
-	.word __bss_start - _start
-
-.globl _bss_end_ofs
-_bss_end_ofs:
-	.word __bss_end - _start
-
-.globl _end_ofs
-_end_ofs:
-	.word _end - _start
-
 #ifdef CONFIG_USE_IRQ
 /* IRQ stack memory (calculated at run-time) */
 .globl IRQ_STACK_START
diff --git a/arch/arm/cpu/armv7/Makefile b/arch/arm/cpu/armv7/Makefile
index ee4b02183a..119ebb3b22 100644
--- a/arch/arm/cpu/armv7/Makefile
+++ b/arch/arm/cpu/armv7/Makefile
@@ -5,40 +5,28 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
+extra-y	:= start.o
 
-LIB	= $(obj)lib$(CPU).o
+obj-y	+= cache_v7.o
 
-START	:= start.o
+obj-y	+= cpu.o
+obj-y	+= syslib.o
 
-COBJS	+= cache_v7.o
-
-COBJS	+= cpu.o
-COBJS	+= syslib.o
-
-ifneq ($(CONFIG_AM43XX)$(CONFIG_AM33XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX)$(CONFIG_TEGRA)$(CONFIG_MX6)$(CONFIG_TI81XX),)
-SOBJS	+= lowlevel_init.o
+ifneq ($(CONFIG_AM43XX)$(CONFIG_AM33XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX)$(CONFIG_TEGRA)$(CONFIG_MX6)$(CONFIG_TI81XX)$(CONFIG_AT91FAMILY),)
+ifneq ($(CONFIG_SKIP_LOWLEVEL_INIT),y)
+obj-y	+= lowlevel_init.o
+endif
 endif
 
 ifneq ($(CONFIG_ARMV7_NONSEC)$(CONFIG_ARMV7_VIRT),)
-SOBJS	+= nonsec_virt.o
-COBJS	+= virt-v7.o
+obj-y	+= nonsec_virt.o
+obj-y	+= virt-v7.o
 endif
 
-SRCS	:= $(START:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS) $(SOBJS))
-START	:= $(addprefix $(obj),$(START))
-
-all:	$(obj).depend $(START) $(LIB)
-
-$(LIB):	$(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
+obj-$(CONFIG_KONA) += kona-common/
+obj-$(CONFIG_OMAP_COMMON) += omap-common/
+obj-$(CONFIG_TEGRA) += tegra-common/
 
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+ifneq (,$(filter s5pc1xx exynos,$(SOC)))
+obj-y += s5p-common/
+endif
diff --git a/arch/arm/cpu/armv7/am33xx/Makefile b/arch/arm/cpu/armv7/am33xx/Makefile
index f6a297c9da..5566310d94 100644
--- a/arch/arm/cpu/armv7/am33xx/Makefile
+++ b/arch/arm/cpu/armv7/am33xx/Makefile
@@ -4,46 +4,18 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(SOC).o
-
-COBJS-$(CONFIG_AM33XX)	+= clock_am33xx.o
-COBJS-$(CONFIG_TI814X)	+= clock_ti814x.o
-COBJS-$(CONFIG_AM43XX)	+= clock_am43xx.o
+obj-$(CONFIG_AM33XX)	+= clock_am33xx.o
+obj-$(CONFIG_TI814X)	+= clock_ti814x.o
+obj-$(CONFIG_AM43XX)	+= clock_am43xx.o
 
 ifneq ($(CONFIG_AM43XX)$(CONFIG_AM33XX),)
-COBJS	+= clock.o
+obj-y	+= clock.o
 endif
 
-COBJS-$(CONFIG_TI816X)	+= clock_ti816x.o
-COBJS	+= sys_info.o
-COBJS	+= mem.o
-COBJS	+= ddr.o
-COBJS	+= emif4.o
-COBJS	+= board.o
-COBJS	+= mux.o
-COBJS-$(CONFIG_NAND_OMAP_GPMC)	+= elm.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS) $(COBJS-y) $(SOBJS))
-
-all:	$(obj).depend $(LIB)
-
-$(LIB):	$(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-clean:
-	rm -f $(SOBJS) $(OBJS)
-
-distclean:	clean
-	rm -f $(LIB) core *.bak .depend
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-$(CONFIG_TI816X)	+= clock_ti816x.o
+obj-y	+= sys_info.o
+obj-y	+= mem.o
+obj-y	+= ddr.o
+obj-y	+= emif4.o
+obj-y	+= board.o
+obj-y	+= mux.o
diff --git a/arch/arm/cpu/armv7/am33xx/board.c b/arch/arm/cpu/armv7/am33xx/board.c
index a31bf40e5b..fb44cc8290 100644
--- a/arch/arm/cpu/armv7/am33xx/board.c
+++ b/arch/arm/cpu/armv7/am33xx/board.c
@@ -32,14 +32,19 @@
 #include <linux/usb/gadget.h>
 #include <linux/usb/musb.h>
 #include <asm/omap_musb.h>
+#include <asm/davinci_rtc.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
-static const struct gpio_bank gpio_bank_am33xx[4] = {
+static const struct gpio_bank gpio_bank_am33xx[] = {
 	{ (void *)AM33XX_GPIO0_BASE, METHOD_GPIO_24XX },
 	{ (void *)AM33XX_GPIO1_BASE, METHOD_GPIO_24XX },
 	{ (void *)AM33XX_GPIO2_BASE, METHOD_GPIO_24XX },
 	{ (void *)AM33XX_GPIO3_BASE, METHOD_GPIO_24XX },
+#ifdef CONFIG_AM43XX
+	{ (void *)AM33XX_GPIO4_BASE, METHOD_GPIO_24XX },
+	{ (void *)AM33XX_GPIO5_BASE, METHOD_GPIO_24XX },
+#endif
 };
 
 const struct gpio_bank *const omap_gpio_bank = gpio_bank_am33xx;
@@ -148,21 +153,23 @@ __weak void am33xx_spl_board_init(void)
 	do_setup_dpll(&dpll_mpu_regs, &dpll_mpu_opp100);
 }
 
+#if defined(CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC)
 static void rtc32k_enable(void)
 {
-	struct rtc_regs *rtc = (struct rtc_regs *)RTC_BASE;
+	struct davinci_rtc *rtc = (struct davinci_rtc *)RTC_BASE;
 
 	/*
 	 * Unlock the RTC's registers.  For more details please see the
 	 * RTC_SS section of the TRM.  In order to unlock we need to
 	 * write these specific values (keys) in this order.
 	 */
-	writel(0x83e70b13, &rtc->kick0r);
-	writel(0x95a4f1e0, &rtc->kick1r);
+	writel(RTC_KICK0R_WE, &rtc->kick0r);
+	writel(RTC_KICK1R_WE, &rtc->kick1r);
 
 	/* Enable the RTC 32K OSC by setting bits 3 and 6. */
 	writel((1 << 3) | (1 << 6), &rtc->osc);
 }
+#endif
 
 static void uart_soft_reset(void)
 {
@@ -195,6 +202,7 @@ static void watchdog_disable(void)
 }
 #endif
 
+#if defined(CONFIG_SPL_BUILD) || defined(CONFIG_NOR_BOOT)
 void s_init(void)
 {
 	/*
@@ -213,26 +221,33 @@ void s_init(void)
 #ifdef CONFIG_SPL_BUILD
 	save_omap_boot_params();
 #endif
-#if defined(CONFIG_SPL_BUILD) || defined(CONFIG_NOR_BOOT)
 	watchdog_disable();
 	timer_init();
 	set_uart_mux_conf();
 	setup_clocks_for_console();
 	uart_soft_reset();
-#endif
 #ifdef CONFIG_NOR_BOOT
 	gd->baudrate = CONFIG_BAUDRATE;
 	serial_init();
 	gd->have_console = 1;
-#else
+#elif defined(CONFIG_SPL_BUILD)
 	gd = &gdata;
 	preloader_console_init();
 #endif
-#if defined(CONFIG_SPL_BUILD) || defined(CONFIG_NOR_BOOT)
 	prcm_init();
 	set_mux_conf_regs();
+#if defined(CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC)
 	/* Enable RTC32K clock */
 	rtc32k_enable();
+#endif
 	sdram_init();
+}
 #endif
+
+#ifndef CONFIG_SYS_DCACHE_OFF
+void enable_caches(void)
+{
+	/* Enable D-cache. I-cache is already enabled in start.S */
+	dcache_enable();
 }
+#endif /* !CONFIG_SYS_DCACHE_OFF */
diff --git a/arch/arm/cpu/armv7/am33xx/clock.c b/arch/arm/cpu/armv7/am33xx/clock.c
index 8e5f3c6715..0672798fe0 100644
--- a/arch/arm/cpu/armv7/am33xx/clock.c
+++ b/arch/arm/cpu/armv7/am33xx/clock.c
@@ -101,9 +101,15 @@ void do_setup_dpll(const struct dpll_regs *dpll_regs,
 static void setup_dplls(void)
 {
 	const struct dpll_params *params;
-	do_setup_dpll(&dpll_core_regs, &dpll_core);
-	do_setup_dpll(&dpll_mpu_regs, &dpll_mpu);
-	do_setup_dpll(&dpll_per_regs, &dpll_per);
+
+	params = get_dpll_core_params();
+	do_setup_dpll(&dpll_core_regs, params);
+
+	params = get_dpll_mpu_params();
+	do_setup_dpll(&dpll_mpu_regs, params);
+
+	params = get_dpll_per_params();
+	do_setup_dpll(&dpll_per_regs, params);
 	writel(0x300, &cmwkup->clkdcoldodpllper);
 
 	params = get_dpll_ddr_params();
diff --git a/arch/arm/cpu/armv7/am33xx/clock_am33xx.c b/arch/arm/cpu/armv7/am33xx/clock_am33xx.c
index fabe2595a3..92142c8934 100644
--- a/arch/arm/cpu/armv7/am33xx/clock_am33xx.c
+++ b/arch/arm/cpu/armv7/am33xx/clock_am33xx.c
@@ -62,6 +62,21 @@ const struct dpll_params dpll_core = {
 const struct dpll_params dpll_per = {
 		960, OSC-1, 5, -1, -1, -1, -1};
 
+const struct dpll_params *get_dpll_mpu_params(void)
+{
+	return &dpll_mpu;
+}
+
+const struct dpll_params *get_dpll_core_params(void)
+{
+	return &dpll_core;
+}
+
+const struct dpll_params *get_dpll_per_params(void)
+{
+	return &dpll_per;
+}
+
 void setup_clocks_for_console(void)
 {
 	clrsetbits_le32(&cmwkup->wkclkstctrl, CD_CLKCTRL_CLKTRCTRL_MASK,
diff --git a/arch/arm/cpu/armv7/am33xx/clock_am43xx.c b/arch/arm/cpu/armv7/am33xx/clock_am43xx.c
index c4890f2b43..d0bc2340c8 100644
--- a/arch/arm/cpu/armv7/am33xx/clock_am43xx.c
+++ b/arch/arm/cpu/armv7/am33xx/clock_am43xx.c
@@ -18,6 +18,7 @@
 
 struct cm_perpll *const cmper = (struct cm_perpll *)CM_PER;
 struct cm_wkuppll *const cmwkup = (struct cm_wkuppll *)CM_WKUP;
+struct cm_dpll *const cmdpll = (struct cm_dpll *)CM_DPLL;
 
 const struct dpll_regs dpll_mpu_regs = {
 	.cm_clkmode_dpll	= CM_WKUP + 0x560,
@@ -47,15 +48,9 @@ const struct dpll_regs dpll_ddr_regs = {
 	.cm_idlest_dpll		= CM_WKUP + 0x5A4,
 	.cm_clksel_dpll		= CM_WKUP + 0x5AC,
 	.cm_div_m2_dpll		= CM_WKUP + 0x5B0,
+	.cm_div_m4_dpll		= CM_WKUP + 0x5B8,
 };
 
-const struct dpll_params dpll_mpu = {
-		-1, -1, -1, -1, -1, -1, -1};
-const struct dpll_params dpll_core = {
-		-1, -1, -1, -1, -1, -1, -1};
-const struct dpll_params dpll_per = {
-		-1, -1, -1, -1, -1, -1, -1};
-
 void setup_clocks_for_console(void)
 {
 	/* Do not add any spl_debug prints in this function */
@@ -99,12 +94,19 @@ void enable_basic_clocks(void)
 		&cmper->gpio1clkctrl,
 		&cmper->gpio2clkctrl,
 		&cmper->gpio3clkctrl,
+		&cmper->gpio4clkctrl,
+		&cmper->gpio5clkctrl,
 		&cmper->i2c1clkctrl,
+		&cmper->cpgmac0clkctrl,
 		&cmper->emiffwclkctrl,
 		&cmper->emifclkctrl,
 		&cmper->otfaemifclkctrl,
+		&cmper->qspiclkctrl,
 		0
 	};
 
 	do_enable_clocks(clk_domains, clk_modules_explicit_en, 1);
+
+	/* Select the Master osc clk as Timer2 clock source */
+	writel(0x1, &cmdpll->clktimer2clk);
 }
diff --git a/arch/arm/cpu/armv7/am33xx/clock_ti814x.c b/arch/arm/cpu/armv7/am33xx/clock_ti814x.c
index ef14f47ebc..9b5a47b018 100644
--- a/arch/arm/cpu/armv7/am33xx/clock_ti814x.c
+++ b/arch/arm/cpu/armv7/am33xx/clock_ti814x.c
@@ -211,11 +211,8 @@ static u32 pll_dco_freq_sel(u32 clkout_dco)
 static u32 pll_sigma_delta_val(u32 clkout_dco)
 {
 	u32 sig_val = 0;
-	float frac_div;
 
-	frac_div = (float) clkout_dco / 250;
-	frac_div = frac_div + 0.90;
-	sig_val = (int)frac_div;
+	sig_val = (clkout_dco + 225) / 250;
 	sig_val = sig_val << 24;
 
 	return sig_val;
diff --git a/arch/arm/cpu/armv7/am33xx/config.mk b/arch/arm/cpu/armv7/am33xx/config.mk
index 8e3668f781..5294d16708 100644
--- a/arch/arm/cpu/armv7/am33xx/config.mk
+++ b/arch/arm/cpu/armv7/am33xx/config.mk
@@ -4,8 +4,8 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 ifdef CONFIG_SPL_BUILD
-ALL-y	+= $(OBJTREE)/MLO
-ALL-$(CONFIG_SPL_SPI_SUPPORT) += $(OBJTREE)/MLO.byteswap
+ALL-y	+= MLO
+ALL-$(CONFIG_SPL_SPI_SUPPORT) += MLO.byteswap
 else
-ALL-y	+= $(obj)u-boot.img
+ALL-y	+= u-boot.img
 endif
diff --git a/arch/arm/cpu/armv7/am33xx/ddr.c b/arch/arm/cpu/armv7/am33xx/ddr.c
index fa697c74ab..9a625c4661 100644
--- a/arch/arm/cpu/armv7/am33xx/ddr.c
+++ b/arch/arm/cpu/armv7/am33xx/ddr.c
@@ -36,6 +36,74 @@ static struct ddr_data_regs *ddr_data_reg[2] = {
 static struct ddr_cmdtctrl *ioctrl_reg = {
 			(struct ddr_cmdtctrl *)DDR_CONTROL_BASE_ADDR};
 
+static inline u32 get_mr(int nr, u32 cs, u32 mr_addr)
+{
+	u32 mr;
+
+	mr_addr |= cs << EMIF_REG_CS_SHIFT;
+	writel(mr_addr, &emif_reg[nr]->emif_lpddr2_mode_reg_cfg);
+
+	mr = readl(&emif_reg[nr]->emif_lpddr2_mode_reg_data);
+	debug("get_mr: EMIF1 cs %d mr %08x val 0x%x\n", cs, mr_addr, mr);
+	if (((mr & 0x0000ff00) >>  8) == (mr & 0xff) &&
+	    ((mr & 0x00ff0000) >> 16) == (mr & 0xff) &&
+	    ((mr & 0xff000000) >> 24) == (mr & 0xff))
+		return mr & 0xff;
+	else
+		return mr;
+}
+
+static inline void set_mr(int nr, u32 cs, u32 mr_addr, u32 mr_val)
+{
+	mr_addr |= cs << EMIF_REG_CS_SHIFT;
+	writel(mr_addr, &emif_reg[nr]->emif_lpddr2_mode_reg_cfg);
+	writel(mr_val, &emif_reg[nr]->emif_lpddr2_mode_reg_data);
+}
+
+static void configure_mr(int nr, u32 cs)
+{
+	u32 mr_addr;
+
+	while (get_mr(nr, cs, LPDDR2_MR0) & LPDDR2_MR0_DAI_MASK)
+		;
+	set_mr(nr, cs, LPDDR2_MR10, 0x56);
+
+	set_mr(nr, cs, LPDDR2_MR1, 0x43);
+	set_mr(nr, cs, LPDDR2_MR2, 0x2);
+
+	mr_addr = LPDDR2_MR2 | EMIF_REG_REFRESH_EN_MASK;
+	set_mr(nr, cs, mr_addr, 0x2);
+}
+
+/*
+ * Configure EMIF4D5 registers and MR registers
+ */
+void config_sdram_emif4d5(const struct emif_regs *regs, int nr)
+{
+	writel(0xA0, &emif_reg[nr]->emif_pwr_mgmt_ctrl);
+	writel(0xA0, &emif_reg[nr]->emif_pwr_mgmt_ctrl_shdw);
+	writel(0x1, &emif_reg[nr]->emif_iodft_tlgc);
+	writel(regs->zq_config, &emif_reg[nr]->emif_zq_config);
+
+	writel(regs->temp_alert_config, &emif_reg[nr]->emif_temp_alert_config);
+	writel(regs->emif_rd_wr_lvl_rmp_win,
+	       &emif_reg[nr]->emif_rd_wr_lvl_rmp_win);
+	writel(regs->emif_rd_wr_lvl_rmp_ctl,
+	       &emif_reg[nr]->emif_rd_wr_lvl_rmp_ctl);
+	writel(regs->emif_rd_wr_lvl_ctl, &emif_reg[nr]->emif_rd_wr_lvl_ctl);
+	writel(regs->emif_rd_wr_exec_thresh,
+	       &emif_reg[nr]->emif_rd_wr_exec_thresh);
+
+	writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl);
+	writel(regs->sdram_config, &emif_reg[nr]->emif_sdram_config);
+	writel(regs->sdram_config, &cstat->secure_emif_sdram_config);
+
+	if (emif_sdram_type() == EMIF_SDRAM_TYPE_LPDDR2) {
+		configure_mr(nr, 0);
+		configure_mr(nr, 1);
+	}
+}
+
 /**
  * Configure SDRAM
  */
@@ -72,15 +140,67 @@ void set_sdram_timings(const struct emif_regs *regs, int nr)
 	writel(regs->sdram_tim3, &emif_reg[nr]->emif_sdram_tim_3_shdw);
 }
 
+void __weak emif_get_ext_phy_ctrl_const_regs(const u32 **regs, u32 *size)
+{
+}
+
+/*
+ * Configure EXT PHY registers
+ */
+static void ext_phy_settings(const struct emif_regs *regs, int nr)
+{
+	u32 *ext_phy_ctrl_base = 0;
+	u32 *emif_ext_phy_ctrl_base = 0;
+	const u32 *ext_phy_ctrl_const_regs;
+	u32 i = 0;
+	u32 size;
+
+	ext_phy_ctrl_base = (u32 *)&(regs->emif_ddr_ext_phy_ctrl_1);
+	emif_ext_phy_ctrl_base =
+			(u32 *)&(emif_reg[nr]->emif_ddr_ext_phy_ctrl_1);
+
+	/* Configure external phy control timing registers */
+	for (i = 0; i < EMIF_EXT_PHY_CTRL_TIMING_REG; i++) {
+		writel(*ext_phy_ctrl_base, emif_ext_phy_ctrl_base++);
+		/* Update shadow registers */
+		writel(*ext_phy_ctrl_base++, emif_ext_phy_ctrl_base++);
+	}
+
+	/*
+	 * external phy 6-24 registers do not change with
+	 * ddr frequency
+	 */
+	emif_get_ext_phy_ctrl_const_regs(&ext_phy_ctrl_const_regs, &size);
+
+	if (!size)
+		return;
+
+	for (i = 0; i < size; i++) {
+		writel(ext_phy_ctrl_const_regs[i], emif_ext_phy_ctrl_base++);
+		/* Update shadow registers */
+		writel(ext_phy_ctrl_const_regs[i], emif_ext_phy_ctrl_base++);
+	}
+}
+
 /**
  * Configure DDR PHY
  */
 void config_ddr_phy(const struct emif_regs *regs, int nr)
 {
+	/*
+	 * disable initialization and refreshes for now until we
+	 * finish programming EMIF regs.
+	 */
+	setbits_le32(&emif_reg[nr]->emif_sdram_ref_ctrl,
+		     EMIF_REG_INITREF_DIS_MASK);
+
 	writel(regs->emif_ddr_phy_ctlr_1,
 		&emif_reg[nr]->emif_ddr_phy_ctrl_1);
 	writel(regs->emif_ddr_phy_ctlr_1,
 		&emif_reg[nr]->emif_ddr_phy_ctrl_1_shdw);
+
+	if (get_emif_rev((u32)emif_reg[nr]) == EMIF_4D5)
+		ext_phy_settings(regs, nr);
 }
 
 /**
@@ -88,16 +208,16 @@ void config_ddr_phy(const struct emif_regs *regs, int nr)
  */
 void config_cmd_ctrl(const struct cmd_control *cmd, int nr)
 {
+	if (!cmd)
+		return;
+
 	writel(cmd->cmd0csratio, &ddr_cmd_reg[nr]->cm0csratio);
-	writel(cmd->cmd0dldiff, &ddr_cmd_reg[nr]->cm0dldiff);
 	writel(cmd->cmd0iclkout, &ddr_cmd_reg[nr]->cm0iclkout);
 
 	writel(cmd->cmd1csratio, &ddr_cmd_reg[nr]->cm1csratio);
-	writel(cmd->cmd1dldiff, &ddr_cmd_reg[nr]->cm1dldiff);
 	writel(cmd->cmd1iclkout, &ddr_cmd_reg[nr]->cm1iclkout);
 
 	writel(cmd->cmd2csratio, &ddr_cmd_reg[nr]->cm2csratio);
-	writel(cmd->cmd2dldiff, &ddr_cmd_reg[nr]->cm2dldiff);
 	writel(cmd->cmd2iclkout, &ddr_cmd_reg[nr]->cm2iclkout);
 }
 
@@ -108,6 +228,9 @@ void config_ddr_data(const struct ddr_data *data, int nr)
 {
 	int i;
 
+	if (!data)
+		return;
+
 	for (i = 0; i < DDR_DATA_REGS_NR; i++) {
 		writel(data->datardsratio0,
 			&(ddr_data_reg[nr]+i)->dt0rdsratio0);
@@ -121,18 +244,23 @@ void config_ddr_data(const struct ddr_data *data, int nr)
 			&(ddr_data_reg[nr]+i)->dt0fwsratio0);
 		writel(data->datawrsratio0,
 			&(ddr_data_reg[nr]+i)->dt0wrsratio0);
-		writel(data->datauserank0delay,
-			&(ddr_data_reg[nr]+i)->dt0rdelays0);
-		writel(data->datadldiff0,
-			&(ddr_data_reg[nr]+i)->dt0dldiff0);
 	}
 }
 
-void config_io_ctrl(unsigned long val)
+void config_io_ctrl(const struct ctrl_ioregs *ioregs)
 {
-	writel(val, &ioctrl_reg->cm0ioctl);
-	writel(val, &ioctrl_reg->cm1ioctl);
-	writel(val, &ioctrl_reg->cm2ioctl);
-	writel(val, &ioctrl_reg->dt0ioctl);
-	writel(val, &ioctrl_reg->dt1ioctl);
+	if (!ioregs)
+		return;
+
+	writel(ioregs->cm0ioctl, &ioctrl_reg->cm0ioctl);
+	writel(ioregs->cm1ioctl, &ioctrl_reg->cm1ioctl);
+	writel(ioregs->cm2ioctl, &ioctrl_reg->cm2ioctl);
+	writel(ioregs->dt0ioctl, &ioctrl_reg->dt0ioctl);
+	writel(ioregs->dt1ioctl, &ioctrl_reg->dt1ioctl);
+#ifdef CONFIG_AM43XX
+	writel(ioregs->dt2ioctrl, &ioctrl_reg->dt2ioctrl);
+	writel(ioregs->dt3ioctrl, &ioctrl_reg->dt3ioctrl);
+	writel(ioregs->emif_sdram_config_ext,
+	       &ioctrl_reg->emif_sdram_config_ext);
+#endif
 }
diff --git a/arch/arm/cpu/armv7/am33xx/elm.c b/arch/arm/cpu/armv7/am33xx/elm.c
deleted file mode 100644
index 8f1d6afdd3..0000000000
--- a/arch/arm/cpu/armv7/am33xx/elm.c
+++ /dev/null
@@ -1,196 +0,0 @@
-/*
- * (C) Copyright 2010-2011 Texas Instruments, <www.ti.com>
- * Mansoor Ahamed <mansoor.ahamed@ti.com>
- *
- * BCH Error Location Module (ELM) support.
- *
- * NOTE:
- * 1. Supports only continuous mode. Dont see need for page mode in uboot
- * 2. Supports only syndrome polynomial 0. i.e. poly local variable is
- *    always set to ELM_DEFAULT_POLY. Dont see need for other polynomial
- *    sets in uboot
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/errno.h>
-#include <asm/arch/cpu.h>
-#include <asm/omap_gpmc.h>
-#include <asm/arch/elm.h>
-
-#define ELM_DEFAULT_POLY (0)
-
-struct elm *elm_cfg;
-
-/**
- * elm_load_syndromes - Load BCH syndromes based on nibble selection
- * @syndrome: BCH syndrome
- * @nibbles:
- * @poly: Syndrome Polynomial set to use
- *
- * Load BCH syndromes based on nibble selection
- */
-static void elm_load_syndromes(u8 *syndrome, u32 nibbles, u8 poly)
-{
-	u32 *ptr;
-	u32 val;
-
-	/* reg 0 */
-	ptr = &elm_cfg->syndrome_fragments[poly].syndrome_fragment_x[0];
-	val = syndrome[0] | (syndrome[1] << 8) | (syndrome[2] << 16) |
-				(syndrome[3] << 24);
-	writel(val, ptr);
-	/* reg 1 */
-	ptr = &elm_cfg->syndrome_fragments[poly].syndrome_fragment_x[1];
-	val = syndrome[4] | (syndrome[5] << 8) | (syndrome[6] << 16) |
-				(syndrome[7] << 24);
-	writel(val, ptr);
-
-	/* BCH 8-bit with 26 nibbles (4*8=32) */
-	if (nibbles > 13) {
-		/* reg 2 */
-		ptr = &elm_cfg->syndrome_fragments[poly].syndrome_fragment_x[2];
-		val = syndrome[8] | (syndrome[9] << 8) | (syndrome[10] << 16) |
-				(syndrome[11] << 24);
-		writel(val, ptr);
-		/* reg 3 */
-		ptr = &elm_cfg->syndrome_fragments[poly].syndrome_fragment_x[3];
-		val = syndrome[12] | (syndrome[13] << 8) |
-			(syndrome[14] << 16) | (syndrome[15] << 24);
-		writel(val, ptr);
-	}
-
-	/* BCH 16-bit with 52 nibbles (7*8=56) */
-	if (nibbles > 26) {
-		/* reg 4 */
-		ptr = &elm_cfg->syndrome_fragments[poly].syndrome_fragment_x[4];
-		val = syndrome[16] | (syndrome[17] << 8) |
-			(syndrome[18] << 16) | (syndrome[19] << 24);
-		writel(val, ptr);
-
-		/* reg 5 */
-		ptr = &elm_cfg->syndrome_fragments[poly].syndrome_fragment_x[5];
-		val = syndrome[20] | (syndrome[21] << 8) |
-			(syndrome[22] << 16) | (syndrome[23] << 24);
-		writel(val, ptr);
-
-		/* reg 6 */
-		ptr = &elm_cfg->syndrome_fragments[poly].syndrome_fragment_x[6];
-		val = syndrome[24] | (syndrome[25] << 8) |
-			(syndrome[26] << 16) | (syndrome[27] << 24);
-		writel(val, ptr);
-	}
-}
-
-/**
- * elm_check_errors - Check for BCH errors and return error locations
- * @syndrome: BCH syndrome
- * @nibbles:
- * @error_count: Returns number of errrors in the syndrome
- * @error_locations: Returns error locations (in decimal) in this array
- *
- * Check the provided syndrome for BCH errors and return error count
- * and locations in the array passed. Returns -1 if error is not correctable,
- * else returns 0
- */
-int elm_check_error(u8 *syndrome, u32 nibbles, u32 *error_count,
-		u32 *error_locations)
-{
-	u8 poly = ELM_DEFAULT_POLY;
-	s8 i;
-	u32 location_status;
-
-	elm_load_syndromes(syndrome, nibbles, poly);
-
-	/* start processing */
-	writel((readl(&elm_cfg->syndrome_fragments[poly].syndrome_fragment_x[6])
-				| ELM_SYNDROME_FRAGMENT_6_SYNDROME_VALID),
-		&elm_cfg->syndrome_fragments[poly].syndrome_fragment_x[6]);
-
-	/* wait for processing to complete */
-	while ((readl(&elm_cfg->irqstatus) & (0x1 << poly)) != 0x1)
-		;
-	/* clear status */
-	writel((readl(&elm_cfg->irqstatus) | (0x1 << poly)),
-			&elm_cfg->irqstatus);
-
-	/* check if correctable */
-	location_status = readl(&elm_cfg->error_location[poly].location_status);
-	if (!(location_status & ELM_LOCATION_STATUS_ECC_CORRECTABLE_MASK))
-		return -1;
-
-	/* get error count */
-	*error_count = readl(&elm_cfg->error_location[poly].location_status) &
-					ELM_LOCATION_STATUS_ECC_NB_ERRORS_MASK;
-
-	for (i = 0; i < *error_count; i++) {
-		error_locations[i] =
-			readl(&elm_cfg->error_location[poly].error_location_x[i]);
-	}
-
-	return 0;
-}
-
-
-/**
- * elm_config - Configure ELM module
- * @level: 4 / 8 / 16 bit BCH
- *
- * Configure ELM module based on BCH level.
- * Set mode as continuous mode.
- * Currently we are using only syndrome 0 and syndromes 1 to 6 are not used.
- * Also, the mode is set only for syndrome 0
- */
-int elm_config(enum bch_level level)
-{
-	u32 val;
-	u8 poly = ELM_DEFAULT_POLY;
-	u32 buffer_size = 0x7FF;
-
-	/* config size and level */
-	val = (u32)(level) & ELM_LOCATION_CONFIG_ECC_BCH_LEVEL_MASK;
-	val |= ((buffer_size << ELM_LOCATION_CONFIG_ECC_SIZE_POS) &
-				ELM_LOCATION_CONFIG_ECC_SIZE_MASK);
-	writel(val, &elm_cfg->location_config);
-
-	/* config continous mode */
-	/* enable interrupt generation for syndrome polynomial set */
-	writel((readl(&elm_cfg->irqenable) | (0x1 << poly)),
-			&elm_cfg->irqenable);
-	/* set continuous mode for the syndrome polynomial set */
-	writel((readl(&elm_cfg->page_ctrl) & ~(0x1 << poly)),
-			&elm_cfg->page_ctrl);
-
-	return 0;
-}
-
-/**
- * elm_reset - Do a soft reset of ELM
- *
- * Perform a soft reset of ELM and return after reset is done.
- */
-void elm_reset(void)
-{
-	/* initiate reset */
-	writel((readl(&elm_cfg->sysconfig) | ELM_SYSCONFIG_SOFTRESET),
-				&elm_cfg->sysconfig);
-
-	/* wait for reset complete and normal operation */
-	while ((readl(&elm_cfg->sysstatus) & ELM_SYSSTATUS_RESETDONE) !=
-		ELM_SYSSTATUS_RESETDONE)
-		;
-}
-
-/**
- * elm_init - Initialize ELM module
- *
- * Initialize ELM support. Currently it does only base address init
- * and ELM reset.
- */
-void elm_init(void)
-{
-	elm_cfg = (struct elm *)ELM_BASE;
-	elm_reset();
-}
diff --git a/arch/arm/cpu/armv7/am33xx/emif4.c b/arch/arm/cpu/armv7/am33xx/emif4.c
index 59ad25c5b0..3e39752380 100644
--- a/arch/arm/cpu/armv7/am33xx/emif4.c
+++ b/arch/arm/cpu/armv7/am33xx/emif4.c
@@ -48,6 +48,11 @@ static struct vtp_reg *vtpreg[2] = {
 #ifdef CONFIG_AM33XX
 static struct ddr_ctrl *ddrctrl = (struct ddr_ctrl *)DDR_CTRL_ADDR;
 #endif
+#ifdef CONFIG_AM43XX
+static struct ddr_ctrl *ddrctrl = (struct ddr_ctrl *)DDR_CTRL_ADDR;
+static struct cm_device_inst *cm_device =
+				(struct cm_device_inst *)CM_DEVICE_INST;
+#endif
 
 #ifdef CONFIG_TI81XX
 void config_dmm(const struct dmm_lisa_map_regs *regs)
@@ -87,7 +92,7 @@ void __weak ddr_pll_config(unsigned int ddrpll_m)
 {
 }
 
-void config_ddr(unsigned int pll, unsigned int ioctrl,
+void config_ddr(unsigned int pll, const struct ctrl_ioregs *ioregs,
 		const struct ddr_data *data, const struct cmd_control *ctrl,
 		const struct emif_regs *regs, int nr)
 {
@@ -99,7 +104,18 @@ void config_ddr(unsigned int pll, unsigned int ioctrl,
 
 	config_ddr_data(data, nr);
 #ifdef CONFIG_AM33XX
-	config_io_ctrl(ioctrl);
+	config_io_ctrl(ioregs);
+
+	/* Set CKE to be controlled by EMIF/DDR PHY */
+	writel(DDR_CKE_CTRL_NORMAL, &ddrctrl->ddrckectrl);
+#endif
+#ifdef CONFIG_AM43XX
+	writel(readl(&cm_device->cm_dll_ctrl) & ~0x1, &cm_device->cm_dll_ctrl);
+	while ((readl(&cm_device->cm_dll_ctrl) && CM_DLL_READYST) == 0)
+		;
+	writel(0x80000000, &ddrctrl->ddrioctrl);
+
+	config_io_ctrl(ioregs);
 
 	/* Set CKE to be controlled by EMIF/DDR PHY */
 	writel(DDR_CKE_CTRL_NORMAL, &ddrctrl->ddrckectrl);
@@ -108,6 +124,9 @@ void config_ddr(unsigned int pll, unsigned int ioctrl,
 	/* Program EMIF instance */
 	config_ddr_phy(regs, nr);
 	set_sdram_timings(regs, nr);
-	config_sdram(regs, nr);
+	if (get_emif_rev(EMIF1_BASE) == EMIF_4D5)
+		config_sdram_emif4d5(regs, nr);
+	else
+		config_sdram(regs, nr);
 }
 #endif
diff --git a/arch/arm/cpu/armv7/am33xx/mem.c b/arch/arm/cpu/armv7/am33xx/mem.c
index b6eb46678f..56c9e7dbce 100644
--- a/arch/arm/cpu/armv7/am33xx/mem.c
+++ b/arch/arm/cpu/armv7/am33xx/mem.c
@@ -22,17 +22,6 @@
 
 struct gpmc *gpmc_cfg;
 
-#if defined(CONFIG_CMD_NAND)
-static const u32 gpmc_m_nand[GPMC_MAX_REG] = {
-	M_NAND_GPMC_CONFIG1,
-	M_NAND_GPMC_CONFIG2,
-	M_NAND_GPMC_CONFIG3,
-	M_NAND_GPMC_CONFIG4,
-	M_NAND_GPMC_CONFIG5,
-	M_NAND_GPMC_CONFIG6, 0
-};
-#endif
-
 
 void enable_gpmc_cs_config(const u32 *gpmc_config, struct gpmc_cs *cs, u32 base,
 			u32 size)
@@ -61,11 +50,34 @@ void gpmc_init(void)
 {
 	/* putting a blanket check on GPMC based on ZeBu for now */
 	gpmc_cfg = (struct gpmc *)GPMC_BASE;
-
-#ifdef CONFIG_CMD_NAND
-	const u32 *gpmc_config = NULL;
-	u32 base = 0;
+#if defined(CONFIG_NOR)
+/* configure GPMC for NOR */
+	const u32 gpmc_regs[GPMC_MAX_REG] = {	STNOR_GPMC_CONFIG1,
+						STNOR_GPMC_CONFIG2,
+						STNOR_GPMC_CONFIG3,
+						STNOR_GPMC_CONFIG4,
+						STNOR_GPMC_CONFIG5,
+						STNOR_GPMC_CONFIG6,
+						STNOR_GPMC_CONFIG7
+						};
+	u32 size = GPMC_SIZE_16M;
+	u32 base = CONFIG_SYS_FLASH_BASE;
+#elif defined(CONFIG_NAND)
+/* configure GPMC for NAND */
+	const u32  gpmc_regs[GPMC_MAX_REG] = {	M_NAND_GPMC_CONFIG1,
+						M_NAND_GPMC_CONFIG2,
+						M_NAND_GPMC_CONFIG3,
+						M_NAND_GPMC_CONFIG4,
+						M_NAND_GPMC_CONFIG5,
+						M_NAND_GPMC_CONFIG6,
+						0
+						};
+	u32 size = GPMC_SIZE_256M;
+	u32 base = CONFIG_SYS_NAND_BASE;
+#else
+	const u32 gpmc_regs[GPMC_MAX_REG] = { 0, 0, 0, 0, 0, 0, 0 };
 	u32 size = 0;
+	u32 base = 0;
 #endif
 	/* global settings */
 	writel(0x00000008, &gpmc_cfg->sysconfig);
@@ -81,12 +93,6 @@ void gpmc_init(void)
 	 */
 	writel(0, &gpmc_cfg->cs[0].config7);
 	sdelay(1000);
-
-#ifdef CONFIG_CMD_NAND
-	gpmc_config = gpmc_m_nand;
-
-	base = PISMO1_NAND_BASE;
-	size = PISMO1_NAND_SIZE;
-	enable_gpmc_cs_config(gpmc_config, &gpmc_cfg->cs[0], base, size);
-#endif
+	/* enable chip-select specific configurations */
+	enable_gpmc_cs_config(gpmc_regs, &gpmc_cfg->cs[0], base, size);
 }
diff --git a/arch/arm/cpu/armv7/am33xx/u-boot-spl.lds b/arch/arm/cpu/armv7/am33xx/u-boot-spl.lds
index 9302856a95..b1c28c9442 100644
--- a/arch/arm/cpu/armv7/am33xx/u-boot-spl.lds
+++ b/arch/arm/cpu/armv7/am33xx/u-boot-spl.lds
@@ -38,7 +38,11 @@ SECTIONS
 
 	. = ALIGN(4);
 	__image_copy_end = .;
-	_end = .;
+
+	.end :
+	{
+		*(.__end)
+	} >.sram
 
 	.bss :
 	{
diff --git a/arch/arm/cpu/armv7/at91/Makefile b/arch/arm/cpu/armv7/at91/Makefile
index 90b9bd68d7..0a2e48d047 100644
--- a/arch/arm/cpu/armv7/at91/Makefile
+++ b/arch/arm/cpu/armv7/at91/Makefile
@@ -8,29 +8,8 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(SOC).o
-
-COBJS-$(CONFIG_SAMA5D3)	+= sama5d3_devices.o
-COBJS-y += clock.o
-COBJS-y += cpu.o
-COBJS-y += reset.o
-COBJS-y += timer.o
-
-SRCS    := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
-OBJS    := $(addprefix $(obj),$(SOBJS-y) $(COBJS-y))
-
-all:	$(obj).depend $(LIB)
-
-$(LIB):	$(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-$(CONFIG_SAMA5D3)	+= sama5d3_devices.o
+obj-y += clock.o
+obj-y += cpu.o
+obj-y += reset.o
+obj-y += timer.o
diff --git a/arch/arm/cpu/armv7/at91/sama5d3_devices.c b/arch/arm/cpu/armv7/at91/sama5d3_devices.c
index 51f0a6dff1..78ecfc882a 100644
--- a/arch/arm/cpu/armv7/at91/sama5d3_devices.c
+++ b/arch/arm/cpu/armv7/at91/sama5d3_devices.c
@@ -15,7 +15,7 @@
 
 unsigned int has_emac()
 {
-	return cpu_is_sama5d31() || cpu_is_sama5d35();
+	return cpu_is_sama5d31() || cpu_is_sama5d35() || cpu_is_sama5d36();
 }
 
 unsigned int has_gmac()
@@ -42,6 +42,8 @@ char *get_cpu_name()
 			return "SAMA5D34";
 		case ARCH_EXID_SAMA5D35:
 			return "SAMA5D35";
+		case ARCH_EXID_SAMA5D36:
+			return "SAMA5D36";
 		default:
 			return "Unknown CPU type";
 		}
@@ -82,7 +84,7 @@ void at91_seriald_hw_init(void)
 	at91_set_a_periph(AT91_PIO_PORTB, 30, 0);	/* DRXD */
 
 	/* Enable clock */
-	at91_periph_clk_enable(ATMEL_ID_SYS);
+	at91_periph_clk_enable(ATMEL_ID_DBGU);
 }
 
 #if defined(CONFIG_ATMEL_SPI)
diff --git a/arch/arm/cpu/armv7/at91/timer.c b/arch/arm/cpu/armv7/at91/timer.c
index 3808aedc79..e3ebfe0c52 100644
--- a/arch/arm/cpu/armv7/at91/timer.c
+++ b/arch/arm/cpu/armv7/at91/timer.c
@@ -60,7 +60,7 @@ int timer_init(void)
 	at91_pit_t *pit = (at91_pit_t *)ATMEL_BASE_PIT;
 
 	/* Enable PITC Clock */
-	at91_periph_clk_enable(ATMEL_ID_SYS);
+	at91_periph_clk_enable(ATMEL_ID_PIT);
 
 	/* Enable PITC */
 	writel(TIMER_LOAD_VAL | AT91_PIT_MR_EN , &pit->mr);
diff --git a/arch/arm/cpu/armv7/bcm281xx/Makefile b/arch/arm/cpu/armv7/bcm281xx/Makefile
new file mode 100644
index 0000000000..98f5aa59ca
--- /dev/null
+++ b/arch/arm/cpu/armv7/bcm281xx/Makefile
@@ -0,0 +1,11 @@
+#
+# Copyright 2013 Broadcom Corporation.
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y	+= reset.o
+obj-y	+= clk-core.o
+obj-y	+= clk-bcm281xx.o
+obj-y	+= clk-sdio.o
+obj-y	+= clk-bsc.o
diff --git a/arch/arm/cpu/armv7/bcm281xx/clk-bcm281xx.c b/arch/arm/cpu/armv7/bcm281xx/clk-bcm281xx.c
new file mode 100644
index 0000000000..bc8a170b40
--- /dev/null
+++ b/arch/arm/cpu/armv7/bcm281xx/clk-bcm281xx.c
@@ -0,0 +1,523 @@
+/*
+ * Copyright 2013 Broadcom Corporation.
+ *
+ * SPDX-License-Identifier:      GPL-2.0+
+ */
+
+/*
+ *
+ * bcm281xx-specific clock tables
+ *
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/errno.h>
+#include <asm/arch/sysmap.h>
+#include <asm/kona-common/clk.h>
+#include "clk-core.h"
+
+#define CLOCK_1K		1000
+#define CLOCK_1M		(CLOCK_1K * 1000)
+
+/* declare a reference clock */
+#define DECLARE_REF_CLK(clk_name, clk_parent, clk_rate, clk_div) \
+static struct refclk clk_name = { \
+	.clk    =       { \
+		.name   =       #clk_name, \
+		.parent =       clk_parent, \
+		.rate   =       clk_rate, \
+		.div    =       clk_div, \
+		.ops    =       &ref_clk_ops, \
+	}, \
+}
+
+/*
+ * Reference clocks
+ */
+
+/* Declare a list of reference clocks */
+DECLARE_REF_CLK(ref_crystal,	0,		26  * CLOCK_1M,	1);
+DECLARE_REF_CLK(var_96m,	0,		96  * CLOCK_1M,	1);
+DECLARE_REF_CLK(ref_96m,	0,		96  * CLOCK_1M,	1);
+DECLARE_REF_CLK(ref_312m,	0,		312 * CLOCK_1M,	0);
+DECLARE_REF_CLK(ref_104m,	&ref_312m.clk,	104 * CLOCK_1M,	3);
+DECLARE_REF_CLK(ref_52m,	&ref_104m.clk,	52  * CLOCK_1M,	2);
+DECLARE_REF_CLK(ref_13m,	&ref_52m.clk,	13  * CLOCK_1M,	4);
+DECLARE_REF_CLK(var_312m,	0,		312 * CLOCK_1M,	0);
+DECLARE_REF_CLK(var_104m,	&var_312m.clk,	104 * CLOCK_1M,	3);
+DECLARE_REF_CLK(var_52m,	&var_104m.clk,	52  * CLOCK_1M,	2);
+DECLARE_REF_CLK(var_13m,	&var_52m.clk,	13  * CLOCK_1M,	4);
+
+struct refclk_lkup {
+	struct refclk *procclk;
+	const char *name;
+};
+
+/* Lookup table for string to clk tranlation */
+#define MKSTR(x) {&x, #x}
+static struct refclk_lkup refclk_str_tbl[] = {
+	MKSTR(ref_crystal), MKSTR(var_96m), MKSTR(ref_96m),
+	MKSTR(ref_312m), MKSTR(ref_104m), MKSTR(ref_52m),
+	MKSTR(ref_13m), MKSTR(var_312m), MKSTR(var_104m),
+	MKSTR(var_52m), MKSTR(var_13m),
+};
+
+int refclk_entries = sizeof(refclk_str_tbl)/sizeof(refclk_str_tbl[0]);
+
+/* convert ref clock string to clock structure pointer */
+struct refclk *refclk_str_to_clk(const char *name)
+{
+	int i;
+	struct refclk_lkup *tblp = refclk_str_tbl;
+	for (i = 0; i < refclk_entries; i++, tblp++) {
+		if (!(strcmp(name, tblp->name)))
+			return tblp->procclk;
+	}
+	return NULL;
+}
+
+/* frequency tables indexed by freq_id */
+unsigned long master_axi_freq_tbl[8] = {
+	26 * CLOCK_1M,
+	52 * CLOCK_1M,
+	104 * CLOCK_1M,
+	156 * CLOCK_1M,
+	156 * CLOCK_1M,
+	208 * CLOCK_1M,
+	312 * CLOCK_1M,
+	312 * CLOCK_1M
+};
+
+unsigned long master_ahb_freq_tbl[8] = {
+	26 * CLOCK_1M,
+	52 * CLOCK_1M,
+	52 * CLOCK_1M,
+	52 * CLOCK_1M,
+	78 * CLOCK_1M,
+	104 * CLOCK_1M,
+	104 * CLOCK_1M,
+	156 * CLOCK_1M
+};
+
+unsigned long slave_axi_freq_tbl[8] = {
+	26 * CLOCK_1M,
+	52 * CLOCK_1M,
+	78 * CLOCK_1M,
+	104 * CLOCK_1M,
+	156 * CLOCK_1M,
+	156 * CLOCK_1M
+};
+
+unsigned long slave_apb_freq_tbl[8] = {
+	26 * CLOCK_1M,
+	26 * CLOCK_1M,
+	39 * CLOCK_1M,
+	52 * CLOCK_1M,
+	52 * CLOCK_1M,
+	78 * CLOCK_1M
+};
+
+static struct bus_clk_data bsc1_apb_data = {
+	.gate = HW_SW_GATE_AUTO(0x0458, 16, 0, 1),
+};
+
+static struct bus_clk_data bsc2_apb_data = {
+	.gate = HW_SW_GATE_AUTO(0x045c, 16, 0, 1),
+};
+
+static struct bus_clk_data bsc3_apb_data = {
+	.gate = HW_SW_GATE_AUTO(0x0484, 16, 0, 1),
+};
+
+/* * Master CCU clocks */
+static struct peri_clk_data sdio1_data = {
+	.gate		= HW_SW_GATE(0x0358, 18, 2, 3),
+	.clocks		= CLOCKS("ref_crystal",
+				 "var_52m",
+				 "ref_52m",
+				 "var_96m",
+				 "ref_96m"),
+	.sel		= SELECTOR(0x0a28, 0, 3),
+	.div		= DIVIDER(0x0a28, 4, 14),
+	.trig		= TRIGGER(0x0afc, 9),
+};
+
+static struct peri_clk_data sdio2_data = {
+	.gate		= HW_SW_GATE(0x035c, 18, 2, 3),
+	.clocks		= CLOCKS("ref_crystal",
+				 "var_52m",
+				 "ref_52m",
+				 "var_96m",
+				 "ref_96m"),
+	.sel		= SELECTOR(0x0a2c, 0, 3),
+	.div		= DIVIDER(0x0a2c, 4, 14),
+	.trig		= TRIGGER(0x0afc, 10),
+};
+
+static struct peri_clk_data sdio3_data = {
+	.gate		= HW_SW_GATE(0x0364, 18, 2, 3),
+	.clocks		= CLOCKS("ref_crystal",
+				 "var_52m",
+				 "ref_52m",
+				 "var_96m",
+				 "ref_96m"),
+	.sel		= SELECTOR(0x0a34, 0, 3),
+	.div		= DIVIDER(0x0a34, 4, 14),
+	.trig		= TRIGGER(0x0afc, 12),
+};
+
+static struct peri_clk_data sdio4_data = {
+	.gate		= HW_SW_GATE(0x0360, 18, 2, 3),
+	.clocks		= CLOCKS("ref_crystal",
+				 "var_52m",
+				 "ref_52m",
+				 "var_96m",
+				 "ref_96m"),
+	.sel		= SELECTOR(0x0a30, 0, 3),
+	.div		= DIVIDER(0x0a30, 4, 14),
+	.trig		= TRIGGER(0x0afc, 11),
+};
+
+static struct peri_clk_data sdio1_sleep_data = {
+	.clocks		= CLOCKS("ref_32k"),
+	.gate		= SW_ONLY_GATE(0x0358, 20, 4),
+};
+
+static struct peri_clk_data sdio2_sleep_data = {
+	.clocks		= CLOCKS("ref_32k"),
+	.gate		= SW_ONLY_GATE(0x035c, 20, 4),
+};
+
+static struct peri_clk_data sdio3_sleep_data = {
+	.clocks		= CLOCKS("ref_32k"),
+	.gate		= SW_ONLY_GATE(0x0364, 20, 4),
+};
+
+static struct peri_clk_data sdio4_sleep_data = {
+	.clocks		= CLOCKS("ref_32k"),
+	.gate		= SW_ONLY_GATE(0x0360, 20, 4),
+};
+
+static struct bus_clk_data sdio1_ahb_data = {
+	.gate		= HW_SW_GATE_AUTO(0x0358, 16, 0, 1),
+};
+
+static struct bus_clk_data sdio2_ahb_data = {
+	.gate		= HW_SW_GATE_AUTO(0x035c, 16, 0, 1),
+};
+
+static struct bus_clk_data sdio3_ahb_data = {
+	.gate		= HW_SW_GATE_AUTO(0x0364, 16, 0, 1),
+};
+
+static struct bus_clk_data sdio4_ahb_data = {
+	.gate		= HW_SW_GATE_AUTO(0x0360, 16, 0, 1),
+};
+
+/* * Slave CCU clocks */
+static struct peri_clk_data bsc1_data = {
+	.gate		= HW_SW_GATE(0x0458, 18, 2, 3),
+	.clocks		= CLOCKS("ref_crystal",
+				 "var_104m",
+				 "ref_104m",
+				 "var_13m",
+				 "ref_13m"),
+	.sel		= SELECTOR(0x0a64, 0, 3),
+	.trig		= TRIGGER(0x0afc, 23),
+};
+
+static struct peri_clk_data bsc2_data = {
+	.gate		= HW_SW_GATE(0x045c, 18, 2, 3),
+	.clocks		= CLOCKS("ref_crystal",
+				 "var_104m",
+				 "ref_104m",
+				 "var_13m",
+				 "ref_13m"),
+	.sel		= SELECTOR(0x0a68, 0, 3),
+	.trig		= TRIGGER(0x0afc, 24),
+};
+
+static struct peri_clk_data bsc3_data = {
+	.gate		= HW_SW_GATE(0x0484, 18, 2, 3),
+	.clocks		= CLOCKS("ref_crystal",
+				 "var_104m",
+				 "ref_104m",
+				 "var_13m",
+				 "ref_13m"),
+	.sel		= SELECTOR(0x0a84, 0, 3),
+	.trig		= TRIGGER(0x0b00, 2),
+};
+
+/*
+ * CCU clocks
+ */
+
+static struct ccu_clock kpm_ccu_clk = {
+	.clk = {
+		.name = "kpm_ccu_clk",
+		.ops = &ccu_clk_ops,
+		.ccu_clk_mgr_base = KONA_MST_CLK_BASE_ADDR,
+	},
+	.num_policy_masks = 1,
+	.policy_freq_offset = 0x00000008,
+	.freq_bit_shift = 8,
+	.policy_ctl_offset = 0x0000000c,
+	.policy0_mask_offset = 0x00000010,
+	.policy1_mask_offset = 0x00000014,
+	.policy2_mask_offset = 0x00000018,
+	.policy3_mask_offset = 0x0000001c,
+	.lvm_en_offset = 0x00000034,
+	.freq_id = 2,
+	.freq_tbl = master_axi_freq_tbl,
+};
+
+static struct ccu_clock kps_ccu_clk = {
+	.clk = {
+		.name = "kps_ccu_clk",
+		.ops = &ccu_clk_ops,
+		.ccu_clk_mgr_base = KONA_SLV_CLK_BASE_ADDR,
+	},
+	.num_policy_masks = 2,
+	.policy_freq_offset = 0x00000008,
+	.freq_bit_shift = 8,
+	.policy_ctl_offset = 0x0000000c,
+	.policy0_mask_offset = 0x00000010,
+	.policy1_mask_offset = 0x00000014,
+	.policy2_mask_offset = 0x00000018,
+	.policy3_mask_offset = 0x0000001c,
+	.policy0_mask2_offset = 0x00000048,
+	.policy1_mask2_offset = 0x0000004c,
+	.policy2_mask2_offset = 0x00000050,
+	.policy3_mask2_offset = 0x00000054,
+	.lvm_en_offset = 0x00000034,
+	.freq_id = 2,
+	.freq_tbl = slave_axi_freq_tbl,
+};
+
+/*
+ * Bus clocks
+ */
+
+/* KPM bus clocks */
+static struct bus_clock sdio1_ahb_clk = {
+	.clk = {
+		.name = "sdio1_ahb_clk",
+		.parent = &kpm_ccu_clk.clk,
+		.ops = &bus_clk_ops,
+		.ccu_clk_mgr_base = KONA_MST_CLK_BASE_ADDR,
+	},
+	.freq_tbl = master_ahb_freq_tbl,
+	.data = &sdio1_ahb_data,
+};
+
+static struct bus_clock sdio2_ahb_clk = {
+	.clk = {
+		.name = "sdio2_ahb_clk",
+		.parent = &kpm_ccu_clk.clk,
+		.ops = &bus_clk_ops,
+		.ccu_clk_mgr_base = KONA_MST_CLK_BASE_ADDR,
+	},
+	.freq_tbl = master_ahb_freq_tbl,
+	.data = &sdio2_ahb_data,
+};
+
+static struct bus_clock sdio3_ahb_clk = {
+	.clk = {
+		.name = "sdio3_ahb_clk",
+		.parent = &kpm_ccu_clk.clk,
+		.ops = &bus_clk_ops,
+		.ccu_clk_mgr_base = KONA_MST_CLK_BASE_ADDR,
+	},
+	.freq_tbl = master_ahb_freq_tbl,
+	.data = &sdio3_ahb_data,
+};
+
+static struct bus_clock sdio4_ahb_clk = {
+	.clk = {
+		.name = "sdio4_ahb_clk",
+		.parent = &kpm_ccu_clk.clk,
+		.ops = &bus_clk_ops,
+		.ccu_clk_mgr_base = KONA_MST_CLK_BASE_ADDR,
+	},
+	.freq_tbl = master_ahb_freq_tbl,
+	.data = &sdio4_ahb_data,
+};
+
+static struct bus_clock bsc1_apb_clk = {
+	.clk = {
+		.name = "bsc1_apb_clk",
+		.parent = &kps_ccu_clk.clk,
+		.ops = &bus_clk_ops,
+		.ccu_clk_mgr_base = KONA_SLV_CLK_BASE_ADDR,
+	},
+	.freq_tbl = slave_apb_freq_tbl,
+	.data = &bsc1_apb_data,
+};
+
+static struct bus_clock bsc2_apb_clk = {
+	.clk = {
+		.name = "bsc2_apb_clk",
+		.parent = &kps_ccu_clk.clk,
+		.ops = &bus_clk_ops,
+		.ccu_clk_mgr_base = KONA_SLV_CLK_BASE_ADDR,
+		},
+	.freq_tbl = slave_apb_freq_tbl,
+	.data = &bsc2_apb_data,
+};
+
+static struct bus_clock bsc3_apb_clk = {
+	.clk = {
+		.name = "bsc3_apb_clk",
+		.parent = &kps_ccu_clk.clk,
+		.ops = &bus_clk_ops,
+		.ccu_clk_mgr_base = KONA_SLV_CLK_BASE_ADDR,
+		},
+	.freq_tbl = slave_apb_freq_tbl,
+	.data = &bsc3_apb_data,
+};
+
+/* KPM peripheral */
+static struct peri_clock sdio1_clk = {
+	.clk = {
+		.name = "sdio1_clk",
+		.parent = &ref_52m.clk,
+		.ops = &peri_clk_ops,
+		.ccu_clk_mgr_base = KONA_MST_CLK_BASE_ADDR,
+	},
+	.data = &sdio1_data,
+};
+
+static struct peri_clock sdio2_clk = {
+	.clk = {
+		.name = "sdio2_clk",
+		.parent = &ref_52m.clk,
+		.ops = &peri_clk_ops,
+		.ccu_clk_mgr_base = KONA_MST_CLK_BASE_ADDR,
+	},
+	.data = &sdio2_data,
+};
+
+static struct peri_clock sdio3_clk = {
+	.clk = {
+		.name = "sdio3_clk",
+		.parent = &ref_52m.clk,
+		.ops = &peri_clk_ops,
+		.ccu_clk_mgr_base = KONA_MST_CLK_BASE_ADDR,
+	},
+	.data = &sdio3_data,
+};
+
+static struct peri_clock sdio4_clk = {
+	.clk = {
+		.name = "sdio4_clk",
+		.parent = &ref_52m.clk,
+		.ops = &peri_clk_ops,
+		.ccu_clk_mgr_base = KONA_MST_CLK_BASE_ADDR,
+	},
+	.data = &sdio4_data,
+};
+
+static struct peri_clock sdio1_sleep_clk = {
+	.clk = {
+		.name = "sdio1_sleep_clk",
+		.parent = &kpm_ccu_clk.clk,
+		.ops = &bus_clk_ops,
+		.ccu_clk_mgr_base = KONA_MST_CLK_BASE_ADDR,
+	},
+	.data = &sdio1_sleep_data,
+};
+
+static struct peri_clock sdio2_sleep_clk = {
+	.clk = {
+		.name = "sdio2_sleep_clk",
+		.parent = &kpm_ccu_clk.clk,
+		.ops = &bus_clk_ops,
+		.ccu_clk_mgr_base = KONA_MST_CLK_BASE_ADDR,
+	},
+	.data = &sdio2_sleep_data,
+};
+
+static struct peri_clock sdio3_sleep_clk = {
+	.clk = {
+		.name = "sdio3_sleep_clk",
+		.parent = &kpm_ccu_clk.clk,
+		.ops = &bus_clk_ops,
+		.ccu_clk_mgr_base = KONA_MST_CLK_BASE_ADDR,
+	},
+	.data = &sdio3_sleep_data,
+};
+
+static struct peri_clock sdio4_sleep_clk = {
+	.clk = {
+		.name = "sdio4_sleep_clk",
+		.parent = &kpm_ccu_clk.clk,
+		.ops = &bus_clk_ops,
+		.ccu_clk_mgr_base = KONA_MST_CLK_BASE_ADDR,
+	},
+	.data = &sdio4_sleep_data,
+};
+
+/* KPS peripheral clock */
+static struct peri_clock bsc1_clk = {
+	.clk = {
+		.name = "bsc1_clk",
+		.parent = &ref_13m.clk,
+		.rate = 13 * CLOCK_1M,
+		.div = 1,
+		.ops = &peri_clk_ops,
+		.ccu_clk_mgr_base = KONA_SLV_CLK_BASE_ADDR,
+	},
+	.data = &bsc1_data,
+};
+
+static struct peri_clock bsc2_clk = {
+	.clk = {
+		.name = "bsc2_clk",
+		.parent = &ref_13m.clk,
+		.rate = 13 * CLOCK_1M,
+		.div = 1,
+		.ops = &peri_clk_ops,
+		.ccu_clk_mgr_base = KONA_SLV_CLK_BASE_ADDR,
+	},
+	.data = &bsc2_data,
+};
+
+static struct peri_clock bsc3_clk = {
+	.clk = {
+		.name = "bsc3_clk",
+		.parent = &ref_13m.clk,
+		.rate = 13 * CLOCK_1M,
+		.div = 1,
+		.ops = &peri_clk_ops,
+		.ccu_clk_mgr_base = KONA_SLV_CLK_BASE_ADDR,
+	},
+	.data = &bsc3_data,
+};
+
+/* public table for registering clocks */
+struct clk_lookup arch_clk_tbl[] = {
+	/* Peripheral clocks */
+	CLK_LK(sdio1),
+	CLK_LK(sdio2),
+	CLK_LK(sdio3),
+	CLK_LK(sdio4),
+	CLK_LK(sdio1_sleep),
+	CLK_LK(sdio2_sleep),
+	CLK_LK(sdio3_sleep),
+	CLK_LK(sdio4_sleep),
+	CLK_LK(bsc1),
+	CLK_LK(bsc2),
+	CLK_LK(bsc3),
+	/* Bus clocks */
+	CLK_LK(sdio1_ahb),
+	CLK_LK(sdio2_ahb),
+	CLK_LK(sdio3_ahb),
+	CLK_LK(sdio4_ahb),
+	CLK_LK(bsc1_apb),
+	CLK_LK(bsc2_apb),
+	CLK_LK(bsc3_apb),
+};
+
+/* public array size */
+unsigned int arch_clk_tbl_array_size = ARRAY_SIZE(arch_clk_tbl);
diff --git a/arch/arm/cpu/armv7/bcm281xx/clk-bsc.c b/arch/arm/cpu/armv7/bcm281xx/clk-bsc.c
new file mode 100644
index 0000000000..ba55d0aeb1
--- /dev/null
+++ b/arch/arm/cpu/armv7/bcm281xx/clk-bsc.c
@@ -0,0 +1,52 @@
+/*
+ * Copyright 2013 Broadcom Corporation.
+ *
+ * SPDX-License-Identifier:      GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/errno.h>
+#include <asm/arch/sysmap.h>
+#include <asm/kona-common/clk.h>
+#include "clk-core.h"
+
+/* Enable appropriate clocks for a BSC/I2C port */
+int clk_bsc_enable(void *base)
+{
+	int ret;
+	char *bscstr, *apbstr;
+
+	switch ((u32) base) {
+	case PMU_BSC_BASE_ADDR:
+		/* PMU clock is always enabled */
+		return 0;
+	case BSC1_BASE_ADDR:
+		bscstr = "bsc1_clk";
+		apbstr = "bsc1_apb_clk";
+		break;
+	case BSC2_BASE_ADDR:
+		bscstr = "bsc2_clk";
+		apbstr = "bsc2_apb_clk";
+		break;
+	case BSC3_BASE_ADDR:
+		bscstr = "bsc3_clk";
+		apbstr = "bsc3_apb_clk";
+		break;
+	default:
+		printf("%s: base 0x%p not found\n", __func__, base);
+		return -EINVAL;
+	}
+
+	/* Note that the bus clock must be enabled first */
+
+	ret = clk_get_and_enable(apbstr);
+	if (ret)
+		return ret;
+
+	ret = clk_get_and_enable(bscstr);
+	if (ret)
+		return ret;
+
+	return 0;
+}
diff --git a/arch/arm/cpu/armv7/bcm281xx/clk-core.c b/arch/arm/cpu/armv7/bcm281xx/clk-core.c
new file mode 100644
index 0000000000..d4425835a1
--- /dev/null
+++ b/arch/arm/cpu/armv7/bcm281xx/clk-core.c
@@ -0,0 +1,513 @@
+/*
+ * Copyright 2013 Broadcom Corporation.
+ *
+ * SPDX-License-Identifier:      GPL-2.0+
+ */
+
+/*
+ *
+ * bcm281xx architecture clock framework
+ *
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/errno.h>
+#include <bitfield.h>
+#include <asm/arch/sysmap.h>
+#include <asm/kona-common/clk.h>
+#include "clk-core.h"
+
+#define CLK_WR_ACCESS_PASSWORD	0x00a5a501
+#define WR_ACCESS_OFFSET	0	/* common to all clock blocks */
+#define POLICY_CTL_GO		1	/* Load and refresh policy masks */
+#define POLICY_CTL_GO_ATL	4	/* Active Load */
+
+/* Helper function */
+int clk_get_and_enable(char *clkstr)
+{
+	int ret = 0;
+	struct clk *c;
+
+	debug("%s: %s\n", __func__, clkstr);
+
+	c = clk_get(clkstr);
+	if (c) {
+		ret = clk_enable(c);
+		if (ret)
+			return ret;
+	} else {
+		printf("%s: Couldn't find %s\n", __func__, clkstr);
+		return -EINVAL;
+	}
+	return ret;
+}
+
+/*
+ * Poll a register in a CCU's address space, returning when the
+ * specified bit in that register's value is set (or clear).  Delay
+ * a microsecond after each read of the register.  Returns true if
+ * successful, or false if we gave up trying.
+ *
+ * Caller must ensure the CCU lock is held.
+ */
+#define CLK_GATE_DELAY_USEC 2000
+static inline int wait_bit(void *base, u32 offset, u32 bit, bool want)
+{
+	unsigned int tries;
+	u32 bit_mask = 1 << bit;
+
+	for (tries = 0; tries < CLK_GATE_DELAY_USEC; tries++) {
+		u32 val;
+		bool bit_val;
+
+		val = readl(base + offset);
+		bit_val = (val & bit_mask) ? 1 : 0;
+		if (bit_val == want)
+			return 0;	/* success */
+		udelay(1);
+	}
+
+	debug("%s: timeout on addr 0x%p, waiting for bit %d to go to %d\n",
+	      __func__, base + offset, bit, want);
+
+	return -ETIMEDOUT;
+}
+
+/* Enable a peripheral clock */
+static int peri_clk_enable(struct clk *c, int enable)
+{
+	int ret = 0;
+	u32 reg;
+	struct peri_clock *peri_clk = to_peri_clk(c);
+	struct peri_clk_data *cd = peri_clk->data;
+	struct bcm_clk_gate *gate = &cd->gate;
+	void *base = (void *)c->ccu_clk_mgr_base;
+
+
+	debug("%s: %s\n", __func__, c->name);
+
+	clk_get_rate(c);	/* Make sure rate and sel are filled in */
+
+	/* enable access */
+	writel(CLK_WR_ACCESS_PASSWORD, base + WR_ACCESS_OFFSET);
+
+	if (enable) {
+		debug("%s %s set rate %lu div %lu sel %d parent %lu\n",
+		      __func__, c->name, c->rate, c->div, c->sel,
+		      c->parent->rate);
+
+		/*
+		 * clkgate - only software controllable gates are
+		 * supported by u-boot which includes all clocks
+		 * that matter. This avoids bringing in a lot of extra
+		 * complexity as done in the kernel framework.
+		 */
+		if (gate_exists(gate)) {
+			reg = readl(base + cd->gate.offset);
+			reg |= (1 << cd->gate.en_bit);
+			writel(reg, base + cd->gate.offset);
+		}
+
+		/* div and pll select */
+		if (divider_exists(&cd->div)) {
+			reg = readl(base + cd->div.offset);
+			bitfield_replace(reg, cd->div.shift, cd->div.width,
+					 c->div - 1);
+			writel(reg, base + cd->div.offset);
+		}
+
+		/* frequency selector */
+		if (selector_exists(&cd->sel)) {
+			reg = readl(base + cd->sel.offset);
+			bitfield_replace(reg, cd->sel.shift, cd->sel.width,
+					 c->sel);
+			writel(reg, base + cd->sel.offset);
+		}
+
+		/* trigger */
+		if (trigger_exists(&cd->trig)) {
+			writel((1 << cd->trig.bit), base + cd->trig.offset);
+
+			/* wait for trigger status bit to go to 0 */
+			ret = wait_bit(base, cd->trig.offset, cd->trig.bit, 0);
+			if (ret)
+				return ret;
+		}
+
+		/* wait for running (status_bit = 1) */
+		ret = wait_bit(base, cd->gate.offset, cd->gate.status_bit, 1);
+		if (ret)
+			return ret;
+	} else {
+		debug("%s disable clock %s\n", __func__, c->name);
+
+		/* clkgate */
+		reg = readl(base + cd->gate.offset);
+		reg &= ~(1 << cd->gate.en_bit);
+		writel(reg, base + cd->gate.offset);
+
+		/* wait for stop (status_bit = 0) */
+		ret = wait_bit(base, cd->gate.offset, cd->gate.status_bit, 0);
+	}
+
+	/* disable access */
+	writel(0, base + WR_ACCESS_OFFSET);
+
+	return ret;
+}
+
+/* Set the rate of a peripheral clock */
+static int peri_clk_set_rate(struct clk *c, unsigned long rate)
+{
+	int ret = 0;
+	int i;
+	unsigned long diff;
+	unsigned long new_rate = 0, div = 1;
+	struct peri_clock *peri_clk = to_peri_clk(c);
+	struct peri_clk_data *cd = peri_clk->data;
+	const char **clock;
+
+	debug("%s: %s\n", __func__, c->name);
+	diff = rate;
+
+	i = 0;
+	for (clock = cd->clocks; *clock; clock++, i++) {
+		struct refclk *ref = refclk_str_to_clk(*clock);
+		if (!ref) {
+			printf("%s: Lookup of %s failed\n", __func__, *clock);
+			return -EINVAL;
+		}
+
+		/* round to the new rate */
+		div = ref->clk.rate / rate;
+		if (div == 0)
+			div = 1;
+
+		new_rate = ref->clk.rate / div;
+
+		/* get the min diff */
+		if (abs(new_rate - rate) < diff) {
+			diff = abs(new_rate - rate);
+			c->sel = i;
+			c->parent = &ref->clk;
+			c->rate = new_rate;
+			c->div = div;
+		}
+	}
+
+	debug("%s %s set rate %lu div %lu sel %d parent %lu\n", __func__,
+	      c->name, c->rate, c->div, c->sel, c->parent->rate);
+	return ret;
+}
+
+/* Get the rate of a peripheral clock */
+static unsigned long peri_clk_get_rate(struct clk *c)
+{
+	struct peri_clock *peri_clk = to_peri_clk(c);
+	struct peri_clk_data *cd = peri_clk->data;
+	void *base = (void *)c->ccu_clk_mgr_base;
+	int div = 1;
+	const char **clock;
+	struct refclk *ref;
+	u32 reg;
+
+	debug("%s: %s\n", __func__, c->name);
+	if (selector_exists(&cd->sel)) {
+		reg = readl(base + cd->sel.offset);
+		c->sel = bitfield_extract(reg, cd->sel.shift, cd->sel.width);
+	} else {
+		/*
+		 * For peri clocks that don't have a selector, the single
+		 * reference clock will always exist at index 0.
+		 */
+		c->sel = 0;
+	}
+
+	if (divider_exists(&cd->div)) {
+		reg = readl(base + cd->div.offset);
+		div = bitfield_extract(reg, cd->div.shift, cd->div.width);
+		div += 1;
+	}
+
+	clock = cd->clocks;
+	ref = refclk_str_to_clk(clock[c->sel]);
+	if (!ref) {
+		printf("%s: Can't lookup %s\n", __func__, clock[c->sel]);
+		return 0;
+	}
+
+	c->parent = &ref->clk;
+	c->div = div;
+	c->rate = c->parent->rate / c->div;
+	debug("%s parent rate %lu div %d sel %d rate %lu\n", __func__,
+	      c->parent->rate, div, c->sel, c->rate);
+
+	return c->rate;
+}
+
+/* Peripheral clock operations */
+struct clk_ops peri_clk_ops = {
+	.enable = peri_clk_enable,
+	.set_rate = peri_clk_set_rate,
+	.get_rate = peri_clk_get_rate,
+};
+
+/* Enable a CCU clock */
+static int ccu_clk_enable(struct clk *c, int enable)
+{
+	struct ccu_clock *ccu_clk = to_ccu_clk(c);
+	void *base = (void *)c->ccu_clk_mgr_base;
+	int ret = 0;
+	u32 reg;
+
+	debug("%s: %s\n", __func__, c->name);
+	if (!enable)
+		return -EINVAL;	/* CCU clock cannot shutdown */
+
+	/* enable access */
+	writel(CLK_WR_ACCESS_PASSWORD, base + WR_ACCESS_OFFSET);
+
+	/* config enable for policy engine */
+	writel(1, base + ccu_clk->lvm_en_offset);
+
+	/* wait for bit to go to 0 */
+	ret = wait_bit(base, ccu_clk->lvm_en_offset, 0, 0);
+	if (ret)
+		return ret;
+
+	/* freq ID */
+	if (!ccu_clk->freq_bit_shift)
+		ccu_clk->freq_bit_shift = 8;
+
+	/* Set frequency id for each of the 4 policies */
+	reg = ccu_clk->freq_id |
+	    (ccu_clk->freq_id << (ccu_clk->freq_bit_shift)) |
+	    (ccu_clk->freq_id << (ccu_clk->freq_bit_shift * 2)) |
+	    (ccu_clk->freq_id << (ccu_clk->freq_bit_shift * 3));
+	writel(reg, base + ccu_clk->policy_freq_offset);
+
+	/* enable all clock mask */
+	writel(0x7fffffff, base + ccu_clk->policy0_mask_offset);
+	writel(0x7fffffff, base + ccu_clk->policy1_mask_offset);
+	writel(0x7fffffff, base + ccu_clk->policy2_mask_offset);
+	writel(0x7fffffff, base + ccu_clk->policy3_mask_offset);
+
+	if (ccu_clk->num_policy_masks == 2) {
+		writel(0x7fffffff, base + ccu_clk->policy0_mask2_offset);
+		writel(0x7fffffff, base + ccu_clk->policy1_mask2_offset);
+		writel(0x7fffffff, base + ccu_clk->policy2_mask2_offset);
+		writel(0x7fffffff, base + ccu_clk->policy3_mask2_offset);
+	}
+
+	/* start policy engine */
+	reg = readl(base + ccu_clk->policy_ctl_offset);
+	reg |= (POLICY_CTL_GO + POLICY_CTL_GO_ATL);
+	writel(reg, base + ccu_clk->policy_ctl_offset);
+
+	/* wait till started */
+	ret = wait_bit(base, ccu_clk->policy_ctl_offset, 0, 0);
+	if (ret)
+		return ret;
+
+	/* disable access */
+	writel(0, base + WR_ACCESS_OFFSET);
+
+	return ret;
+}
+
+/* Get the CCU clock rate */
+static unsigned long ccu_clk_get_rate(struct clk *c)
+{
+	struct ccu_clock *ccu_clk = to_ccu_clk(c);
+	debug("%s: %s\n", __func__, c->name);
+	c->rate = ccu_clk->freq_tbl[ccu_clk->freq_id];
+	return c->rate;
+}
+
+/* CCU clock operations */
+struct clk_ops ccu_clk_ops = {
+	.enable = ccu_clk_enable,
+	.get_rate = ccu_clk_get_rate,
+};
+
+/* Enable a bus clock */
+static int bus_clk_enable(struct clk *c, int enable)
+{
+	struct bus_clock *bus_clk = to_bus_clk(c);
+	struct bus_clk_data *cd = bus_clk->data;
+	void *base = (void *)c->ccu_clk_mgr_base;
+	int ret = 0;
+	u32 reg;
+
+	debug("%s: %s\n", __func__, c->name);
+	/* enable access */
+	writel(CLK_WR_ACCESS_PASSWORD, base + WR_ACCESS_OFFSET);
+
+	/* enable gating */
+	reg = readl(base + cd->gate.offset);
+	if (!!(reg & (1 << cd->gate.status_bit)) == !!enable)
+		debug("%s already %s\n", c->name,
+		      enable ? "enabled" : "disabled");
+	else {
+		int want = (enable) ? 1 : 0;
+		reg |= (1 << cd->gate.hw_sw_sel_bit);
+
+		if (enable)
+			reg |= (1 << cd->gate.en_bit);
+		else
+			reg &= ~(1 << cd->gate.en_bit);
+
+		writel(reg, base + cd->gate.offset);
+		ret = wait_bit(base, cd->gate.offset, cd->gate.status_bit,
+			       want);
+		if (ret)
+			return ret;
+	}
+
+	/* disable access */
+	writel(0, base + WR_ACCESS_OFFSET);
+
+	return ret;
+}
+
+/* Get the rate of a bus clock */
+static unsigned long bus_clk_get_rate(struct clk *c)
+{
+	struct bus_clock *bus_clk = to_bus_clk(c);
+	struct ccu_clock *ccu_clk;
+
+	debug("%s: %s\n", __func__, c->name);
+	ccu_clk = to_ccu_clk(c->parent);
+
+	c->rate = bus_clk->freq_tbl[ccu_clk->freq_id];
+	c->div = ccu_clk->freq_tbl[ccu_clk->freq_id] / c->rate;
+	return c->rate;
+}
+
+/* Bus clock operations */
+struct clk_ops bus_clk_ops = {
+	.enable = bus_clk_enable,
+	.get_rate = bus_clk_get_rate,
+};
+
+/* Enable a reference clock */
+static int ref_clk_enable(struct clk *c, int enable)
+{
+	debug("%s: %s\n", __func__, c->name);
+	return 0;
+}
+
+/* Reference clock operations */
+struct clk_ops ref_clk_ops = {
+	.enable = ref_clk_enable,
+};
+
+/*
+ * clk.h implementation follows
+ */
+
+/* Initialize the clock framework */
+int clk_init(void)
+{
+	debug("%s:\n", __func__);
+	return 0;
+}
+
+/* Get a clock handle, give a name string */
+struct clk *clk_get(const char *con_id)
+{
+	int i;
+	struct clk_lookup *clk_tblp;
+
+	debug("%s: %s\n", __func__, con_id);
+
+	clk_tblp = arch_clk_tbl;
+	for (i = 0; i < arch_clk_tbl_array_size; i++, clk_tblp++) {
+		if (clk_tblp->con_id) {
+			if (!con_id || strcmp(clk_tblp->con_id, con_id))
+				continue;
+			return clk_tblp->clk;
+		}
+	}
+	return NULL;
+}
+
+/* Enable a clock */
+int clk_enable(struct clk *c)
+{
+	int ret = 0;
+
+	debug("%s: %s\n", __func__, c->name);
+	if (!c->ops || !c->ops->enable)
+		return -1;
+
+	/* enable parent clock first */
+	if (c->parent)
+		ret = clk_enable(c->parent);
+
+	if (ret)
+		return ret;
+
+	if (!c->use_cnt) {
+		c->use_cnt++;
+		ret = c->ops->enable(c, 1);
+	}
+
+	return ret;
+}
+
+/* Disable a clock */
+void clk_disable(struct clk *c)
+{
+	debug("%s: %s\n", __func__, c->name);
+	if (!c->ops || !c->ops->enable)
+		return;
+
+	if (c->use_cnt) {
+		c->use_cnt--;
+		c->ops->enable(c, 0);
+	}
+
+	/* disable parent */
+	if (c->parent)
+		clk_disable(c->parent);
+}
+
+/* Get the clock rate */
+unsigned long clk_get_rate(struct clk *c)
+{
+	unsigned long rate;
+
+	debug("%s: %s\n", __func__, c->name);
+	if (!c || !c->ops || !c->ops->get_rate)
+		return 0;
+
+	rate = c->ops->get_rate(c);
+	debug("%s: rate = %ld\n", __func__, rate);
+	return rate;
+}
+
+/* Set the clock rate */
+int clk_set_rate(struct clk *c, unsigned long rate)
+{
+	int ret;
+
+	debug("%s: %s rate=%ld\n", __func__, c->name, rate);
+	if (!c || !c->ops || !c->ops->set_rate)
+		return -EINVAL;
+
+	if (c->use_cnt)
+		return -EINVAL;
+
+	ret = c->ops->set_rate(c, rate);
+
+	return ret;
+}
+
+/* Not required for this arch */
+/*
+long clk_round_rate(struct clk *clk, unsigned long rate);
+int clk_set_parent(struct clk *clk, struct clk *parent);
+struct clk *clk_get_parent(struct clk *clk);
+*/
diff --git a/arch/arm/cpu/armv7/bcm281xx/clk-core.h b/arch/arm/cpu/armv7/bcm281xx/clk-core.h
new file mode 100644
index 0000000000..882a297797
--- /dev/null
+++ b/arch/arm/cpu/armv7/bcm281xx/clk-core.h
@@ -0,0 +1,495 @@
+/*
+ * Copyright 2013 Broadcom Corporation.
+ *
+ * SPDX-License-Identifier:      GPL-2.0+
+ */
+
+#include <linux/stddef.h>
+
+#ifdef CONFIG_CLK_DEBUG
+#undef writel
+#undef readl
+static inline void writel(u32 val, void *addr)
+{
+	printf("Write [0x%p] = 0x%08x\n", addr, val);
+	*(u32 *)addr = val;
+}
+
+static inline u32 readl(void *addr)
+{
+	u32 val = *(u32 *)addr;
+	printf("Read  [0x%p] = 0x%08x\n", addr, val);
+	return val;
+}
+#endif
+
+struct clk;
+
+struct clk_lookup {
+	const char *dev_id;
+	const char *con_id;
+	struct clk *clk;
+};
+
+extern struct clk_lookup arch_clk_tbl[];
+extern unsigned int arch_clk_tbl_array_size;
+
+/**
+ * struct clk_ops - standard clock operations
+ * @enable: enable/disable clock, see clk_enable() and clk_disable()
+ * @set_rate: set the clock rate, see clk_set_rate().
+ * @get_rate: get the clock rate, see clk_get_rate().
+ * @round_rate: round a given clock rate, see clk_round_rate().
+ * @set_parent: set the clock's parent, see clk_set_parent().
+ *
+ * Group the common clock implementations together so that we
+ * don't have to keep setting the same fiels again. We leave
+ * enable in struct clk.
+ *
+ */
+struct clk_ops {
+	int (*enable) (struct clk *c, int enable);
+	int (*set_rate) (struct clk *c, unsigned long rate);
+	unsigned long (*get_rate) (struct clk *c);
+	unsigned long (*round_rate) (struct clk *c, unsigned long rate);
+	int (*set_parent) (struct clk *c, struct clk *parent);
+};
+
+struct clk {
+	struct clk *parent;
+	const char *name;
+	int use_cnt;
+	unsigned long rate;	/* in HZ */
+
+	/* programmable divider. 0 means fixed ratio to parent clock */
+	unsigned long div;
+
+	struct clk_src *src;
+	struct clk_ops *ops;
+
+	unsigned long ccu_clk_mgr_base;
+	int sel;
+};
+
+struct refclk *refclk_str_to_clk(const char *name);
+
+#define U8_MAX	((u8)~0U)
+#define U32_MAX	((u32)~0U)
+#define U64_MAX	((u64)~0U)
+
+/* The common clock framework uses u8 to represent a parent index */
+#define PARENT_COUNT_MAX	((u32)U8_MAX)
+
+#define BAD_CLK_INDEX		U8_MAX	/* Can't ever be valid */
+#define BAD_CLK_NAME		((const char *)-1)
+
+#define BAD_SCALED_DIV_VALUE	U64_MAX
+
+/*
+ * Utility macros for object flag management.  If possible, flags
+ * should be defined such that 0 is the desired default value.
+ */
+#define FLAG(type, flag)		BCM_CLK_ ## type ## _FLAGS_ ## flag
+#define FLAG_SET(obj, type, flag)	((obj)->flags |= FLAG(type, flag))
+#define FLAG_CLEAR(obj, type, flag)	((obj)->flags &= ~(FLAG(type, flag)))
+#define FLAG_FLIP(obj, type, flag)	((obj)->flags ^= FLAG(type, flag))
+#define FLAG_TEST(obj, type, flag)	(!!((obj)->flags & FLAG(type, flag)))
+
+/* Clock field state tests */
+
+#define gate_exists(gate)		FLAG_TEST(gate, GATE, EXISTS)
+#define gate_is_enabled(gate)		FLAG_TEST(gate, GATE, ENABLED)
+#define gate_is_hw_controllable(gate)	FLAG_TEST(gate, GATE, HW)
+#define gate_is_sw_controllable(gate)	FLAG_TEST(gate, GATE, SW)
+#define gate_is_sw_managed(gate)	FLAG_TEST(gate, GATE, SW_MANAGED)
+#define gate_is_no_disable(gate)	FLAG_TEST(gate, GATE, NO_DISABLE)
+
+#define gate_flip_enabled(gate)		FLAG_FLIP(gate, GATE, ENABLED)
+
+#define divider_exists(div)		FLAG_TEST(div, DIV, EXISTS)
+#define divider_is_fixed(div)		FLAG_TEST(div, DIV, FIXED)
+#define divider_has_fraction(div)	(!divider_is_fixed(div) && \
+						(div)->frac_width > 0)
+
+#define selector_exists(sel)		((sel)->width != 0)
+#define trigger_exists(trig)		FLAG_TEST(trig, TRIG, EXISTS)
+
+/* Clock type, used to tell common block what it's part of */
+enum bcm_clk_type {
+	bcm_clk_none,		/* undefined clock type */
+	bcm_clk_bus,
+	bcm_clk_core,
+	bcm_clk_peri
+};
+
+/*
+ * Gating control and status is managed by a 32-bit gate register.
+ *
+ * There are several types of gating available:
+ * - (no gate)
+ *     A clock with no gate is assumed to be always enabled.
+ * - hardware-only gating (auto-gating)
+ *     Enabling or disabling clocks with this type of gate is
+ *     managed automatically by the hardware.  Such clocks can be
+ *     considered by the software to be enabled.  The current status
+ *     of auto-gated clocks can be read from the gate status bit.
+ * - software-only gating
+ *     Auto-gating is not available for this type of clock.
+ *     Instead, software manages whether it's enabled by setting or
+ *     clearing the enable bit.  The current gate status of a gate
+ *     under software control can be read from the gate status bit.
+ *     To ensure a change to the gating status is complete, the
+ *     status bit can be polled to verify that the gate has entered
+ *     the desired state.
+ * - selectable hardware or software gating
+ *     Gating for this type of clock can be configured to be either
+ *     under software or hardware control.  Which type is in use is
+ *     determined by the hw_sw_sel bit of the gate register.
+ */
+struct bcm_clk_gate {
+	u32 offset;		/* gate register offset */
+	u32 status_bit;		/* 0: gate is disabled; 0: gatge is enabled */
+	u32 en_bit;		/* 0: disable; 1: enable */
+	u32 hw_sw_sel_bit;	/* 0: hardware gating; 1: software gating */
+	u32 flags;		/* BCM_CLK_GATE_FLAGS_* below */
+};
+
+/*
+ * Gate flags:
+ *   HW         means this gate can be auto-gated
+ *   SW         means the state of this gate can be software controlled
+ *   NO_DISABLE means this gate is (only) enabled if under software control
+ *   SW_MANAGED means the status of this gate is under software control
+ *   ENABLED    means this software-managed gate is *supposed* to be enabled
+ */
+#define BCM_CLK_GATE_FLAGS_EXISTS	((u32)1 << 0)	/* Gate is valid */
+#define BCM_CLK_GATE_FLAGS_HW		((u32)1 << 1)	/* Can auto-gate */
+#define BCM_CLK_GATE_FLAGS_SW		((u32)1 << 2)	/* Software control */
+#define BCM_CLK_GATE_FLAGS_NO_DISABLE	((u32)1 << 3)	/* HW or enabled */
+#define BCM_CLK_GATE_FLAGS_SW_MANAGED	((u32)1 << 4)	/* SW now in control */
+#define BCM_CLK_GATE_FLAGS_ENABLED	((u32)1 << 5)	/* If SW_MANAGED */
+
+/*
+ * Gate initialization macros.
+ *
+ * Any gate initially under software control will be enabled.
+ */
+
+/* A hardware/software gate initially under software control */
+#define HW_SW_GATE(_offset, _status_bit, _en_bit, _hw_sw_sel_bit)	\
+	{								\
+		.offset = (_offset),					\
+		.status_bit = (_status_bit),				\
+		.en_bit = (_en_bit),					\
+		.hw_sw_sel_bit = (_hw_sw_sel_bit),			\
+		.flags = FLAG(GATE, HW)|FLAG(GATE, SW)|			\
+			FLAG(GATE, SW_MANAGED)|FLAG(GATE, ENABLED)|	\
+			FLAG(GATE, EXISTS),				\
+	}
+
+/* A hardware/software gate initially under hardware control */
+#define HW_SW_GATE_AUTO(_offset, _status_bit, _en_bit, _hw_sw_sel_bit)	\
+	{								\
+		.offset = (_offset),					\
+		.status_bit = (_status_bit),				\
+		.en_bit = (_en_bit),					\
+		.hw_sw_sel_bit = (_hw_sw_sel_bit),			\
+		.flags = FLAG(GATE, HW)|FLAG(GATE, SW)|			\
+			FLAG(GATE, EXISTS),				\
+	}
+
+/* A hardware-or-enabled gate (enabled if not under hardware control) */
+#define HW_ENABLE_GATE(_offset, _status_bit, _en_bit, _hw_sw_sel_bit)	\
+	{								\
+		.offset = (_offset),					\
+		.status_bit = (_status_bit),				\
+		.en_bit = (_en_bit),					\
+		.hw_sw_sel_bit = (_hw_sw_sel_bit),			\
+		.flags = FLAG(GATE, HW)|FLAG(GATE, SW)|			\
+			FLAG(GATE, NO_DISABLE)|FLAG(GATE, EXISTS),	\
+	}
+
+/* A software-only gate */
+#define SW_ONLY_GATE(_offset, _status_bit, _en_bit)			\
+	{								\
+		.offset = (_offset),					\
+		.status_bit = (_status_bit),				\
+		.en_bit = (_en_bit),					\
+		.flags = FLAG(GATE, SW)|FLAG(GATE, SW_MANAGED)|		\
+			FLAG(GATE, ENABLED)|FLAG(GATE, EXISTS),		\
+	}
+
+/* A hardware-only gate */
+#define HW_ONLY_GATE(_offset, _status_bit)				\
+	{								\
+		.offset = (_offset),					\
+		.status_bit = (_status_bit),				\
+		.flags = FLAG(GATE, HW)|FLAG(GATE, EXISTS),		\
+	}
+
+/*
+ * Each clock can have zero, one, or two dividers which change the
+ * output rate of the clock.  Each divider can be either fixed or
+ * variable.  If there are two dividers, they are the "pre-divider"
+ * and the "regular" or "downstream" divider.  If there is only one,
+ * there is no pre-divider.
+ *
+ * A fixed divider is any non-zero (positive) value, and it
+ * indicates how the input rate is affected by the divider.
+ *
+ * The value of a variable divider is maintained in a sub-field of a
+ * 32-bit divider register.  The position of the field in the
+ * register is defined by its offset and width.  The value recorded
+ * in this field is always 1 less than the value it represents.
+ *
+ * In addition, a variable divider can indicate that some subset
+ * of its bits represent a "fractional" part of the divider.  Such
+ * bits comprise the low-order portion of the divider field, and can
+ * be viewed as representing the portion of the divider that lies to
+ * the right of the decimal point.  Most variable dividers have zero
+ * fractional bits.  Variable dividers with non-zero fraction width
+ * still record a value 1 less than the value they represent; the
+ * added 1 does *not* affect the low-order bit in this case, it
+ * affects the bits above the fractional part only.  (Often in this
+ * code a divider field value is distinguished from the value it
+ * represents by referring to the latter as a "divisor".)
+ *
+ * In order to avoid dealing with fractions, divider arithmetic is
+ * performed using "scaled" values.  A scaled value is one that's
+ * been left-shifted by the fractional width of a divider.  Dividing
+ * a scaled value by a scaled divisor produces the desired quotient
+ * without loss of precision and without any other special handling
+ * for fractions.
+ *
+ * The recorded value of a variable divider can be modified.  To
+ * modify either divider (or both), a clock must be enabled (i.e.,
+ * using its gate).  In addition, a trigger register (described
+ * below) must be used to commit the change, and polled to verify
+ * the change is complete.
+ */
+struct bcm_clk_div {
+	union {
+		struct {	/* variable divider */
+			u32 offset;	/* divider register offset */
+			u32 shift;	/* field shift */
+			u32 width;	/* field width */
+			u32 frac_width;	/* field fraction width */
+
+			u64 scaled_div;	/* scaled divider value */
+		};
+		u32 fixed;	/* non-zero fixed divider value */
+	};
+	u32 flags;		/* BCM_CLK_DIV_FLAGS_* below */
+};
+
+/*
+ * Divider flags:
+ *   EXISTS means this divider exists
+ *   FIXED means it is a fixed-rate divider
+ */
+#define BCM_CLK_DIV_FLAGS_EXISTS	((u32)1 << 0)	/* Divider is valid */
+#define BCM_CLK_DIV_FLAGS_FIXED		((u32)1 << 1)	/* Fixed-value */
+
+/* Divider initialization macros */
+
+/* A fixed (non-zero) divider */
+#define FIXED_DIVIDER(_value)						\
+	{								\
+		.fixed = (_value),					\
+		.flags = FLAG(DIV, EXISTS)|FLAG(DIV, FIXED),		\
+	}
+
+/* A divider with an integral divisor */
+#define DIVIDER(_offset, _shift, _width)				\
+	{								\
+		.offset = (_offset),					\
+		.shift = (_shift),					\
+		.width = (_width),					\
+		.scaled_div = BAD_SCALED_DIV_VALUE,			\
+		.flags = FLAG(DIV, EXISTS),				\
+	}
+
+/* A divider whose divisor has an integer and fractional part */
+#define FRAC_DIVIDER(_offset, _shift, _width, _frac_width)		\
+	{								\
+		.offset = (_offset),					\
+		.shift = (_shift),					\
+		.width = (_width),					\
+		.frac_width = (_frac_width),				\
+		.scaled_div = BAD_SCALED_DIV_VALUE,			\
+		.flags = FLAG(DIV, EXISTS),				\
+	}
+
+/*
+ * Clocks may have multiple "parent" clocks.  If there is more than
+ * one, a selector must be specified to define which of the parent
+ * clocks is currently in use.  The selected clock is indicated in a
+ * sub-field of a 32-bit selector register.  The range of
+ * representable selector values typically exceeds the number of
+ * available parent clocks.  Occasionally the reset value of a
+ * selector field is explicitly set to a (specific) value that does
+ * not correspond to a defined input clock.
+ *
+ * We register all known parent clocks with the common clock code
+ * using a packed array (i.e., no empty slots) of (parent) clock
+ * names, and refer to them later using indexes into that array.
+ * We maintain an array of selector values indexed by common clock
+ * index values in order to map between these common clock indexes
+ * and the selector values used by the hardware.
+ *
+ * Like dividers, a selector can be modified, but to do so a clock
+ * must be enabled, and a trigger must be used to commit the change.
+ */
+struct bcm_clk_sel {
+	u32 offset;		/* selector register offset */
+	u32 shift;		/* field shift */
+	u32 width;		/* field width */
+
+	u32 parent_count;	/* number of entries in parent_sel[] */
+	u32 *parent_sel;	/* array of parent selector values */
+	u8 clk_index;		/* current selected index in parent_sel[] */
+};
+
+/* Selector initialization macro */
+#define SELECTOR(_offset, _shift, _width)				\
+	{								\
+		.offset = (_offset),					\
+		.shift = (_shift),					\
+		.width = (_width),					\
+		.clk_index = BAD_CLK_INDEX,				\
+	}
+
+/*
+ * Making changes to a variable divider or a selector for a clock
+ * requires the use of a trigger.  A trigger is defined by a single
+ * bit within a register.  To signal a change, a 1 is written into
+ * that bit.  To determine when the change has been completed, that
+ * trigger bit is polled; the read value will be 1 while the change
+ * is in progress, and 0 when it is complete.
+ *
+ * Occasionally a clock will have more than one trigger.  In this
+ * case, the "pre-trigger" will be used when changing a clock's
+ * selector and/or its pre-divider.
+ */
+struct bcm_clk_trig {
+	u32 offset;		/* trigger register offset */
+	u32 bit;		/* trigger bit */
+	u32 flags;		/* BCM_CLK_TRIG_FLAGS_* below */
+};
+
+/*
+ * Trigger flags:
+ *   EXISTS means this trigger exists
+ */
+#define BCM_CLK_TRIG_FLAGS_EXISTS	((u32)1 << 0)	/* Trigger is valid */
+
+/* Trigger initialization macro */
+#define TRIGGER(_offset, _bit)						\
+	{								\
+		.offset = (_offset),					\
+		.bit = (_bit),						\
+		.flags = FLAG(TRIG, EXISTS),				\
+	}
+
+struct bus_clk_data {
+	struct bcm_clk_gate gate;
+};
+
+struct core_clk_data {
+	struct bcm_clk_gate gate;
+};
+
+struct peri_clk_data {
+	struct bcm_clk_gate gate;
+	struct bcm_clk_trig pre_trig;
+	struct bcm_clk_div pre_div;
+	struct bcm_clk_trig trig;
+	struct bcm_clk_div div;
+	struct bcm_clk_sel sel;
+	const char *clocks[];	/* must be last; use CLOCKS() to declare */
+};
+#define CLOCKS(...)	{ __VA_ARGS__, NULL, }
+#define NO_CLOCKS	{ NULL, }	/* Must use of no parent clocks */
+
+struct refclk {
+	struct clk clk;
+};
+
+struct peri_clock {
+	struct clk clk;
+	struct peri_clk_data *data;
+};
+
+struct ccu_clock {
+	struct clk clk;
+
+	int num_policy_masks;
+	unsigned long policy_freq_offset;
+	int freq_bit_shift;	/* 8 for most CCUs */
+	unsigned long policy_ctl_offset;
+	unsigned long policy0_mask_offset;
+	unsigned long policy1_mask_offset;
+	unsigned long policy2_mask_offset;
+	unsigned long policy3_mask_offset;
+	unsigned long policy0_mask2_offset;
+	unsigned long policy1_mask2_offset;
+	unsigned long policy2_mask2_offset;
+	unsigned long policy3_mask2_offset;
+	unsigned long lvm_en_offset;
+
+	int freq_id;
+	unsigned long *freq_tbl;
+};
+
+struct bus_clock {
+	struct clk clk;
+	struct bus_clk_data *data;
+	unsigned long *freq_tbl;
+};
+
+struct ref_clock {
+	struct clk clk;
+};
+
+static inline int is_same_clock(struct clk *a, struct clk *b)
+{
+	return (a == b);
+}
+
+#define to_clk(p) (&((p)->clk))
+#define name_to_clk(name) (&((name##_clk).clk))
+/* declare a struct clk_lookup */
+#define CLK_LK(name) \
+{.con_id = __stringify(name##_clk), .clk = name_to_clk(name),}
+
+static inline struct refclk *to_refclk(struct clk *clock)
+{
+	return container_of(clock, struct refclk, clk);
+}
+
+static inline struct peri_clock *to_peri_clk(struct clk *clock)
+{
+	return container_of(clock, struct peri_clock, clk);
+}
+
+static inline struct ccu_clock *to_ccu_clk(struct clk *clock)
+{
+	return container_of(clock, struct ccu_clock, clk);
+}
+
+static inline struct bus_clock *to_bus_clk(struct clk *clock)
+{
+	return container_of(clock, struct bus_clock, clk);
+}
+
+static inline struct ref_clock *to_ref_clk(struct clk *clock)
+{
+	return container_of(clock, struct ref_clock, clk);
+}
+
+extern struct clk_ops peri_clk_ops;
+extern struct clk_ops ccu_clk_ops;
+extern struct clk_ops bus_clk_ops;
+extern struct clk_ops ref_clk_ops;
+
+extern int clk_get_and_enable(char *clkstr);
diff --git a/arch/arm/cpu/armv7/bcm281xx/clk-sdio.c b/arch/arm/cpu/armv7/bcm281xx/clk-sdio.c
new file mode 100644
index 0000000000..49badcbaa7
--- /dev/null
+++ b/arch/arm/cpu/armv7/bcm281xx/clk-sdio.c
@@ -0,0 +1,73 @@
+/*
+ * Copyright 2013 Broadcom Corporation.
+ *
+ * SPDX-License-Identifier:      GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/errno.h>
+#include <asm/arch/sysmap.h>
+#include <asm/kona-common/clk.h>
+#include "clk-core.h"
+
+/* Enable appropriate clocks for an SDIO port */
+int clk_sdio_enable(void *base, u32 rate, u32 *actual_ratep)
+{
+	int ret;
+	struct clk *c;
+
+	char *clkstr;
+	char *slpstr;
+	char *ahbstr;
+
+	switch ((u32) base) {
+	case CONFIG_SYS_SDIO_BASE0:
+		clkstr = CONFIG_SYS_SDIO0 "_clk";
+		ahbstr = CONFIG_SYS_SDIO0 "_ahb_clk";
+		slpstr = CONFIG_SYS_SDIO0 "_sleep_clk";
+		break;
+	case CONFIG_SYS_SDIO_BASE1:
+		clkstr = CONFIG_SYS_SDIO1 "_clk";
+		ahbstr = CONFIG_SYS_SDIO1 "_ahb_clk";
+		slpstr = CONFIG_SYS_SDIO1 "_sleep_clk";
+		break;
+	case CONFIG_SYS_SDIO_BASE2:
+		clkstr = CONFIG_SYS_SDIO2 "_clk";
+		ahbstr = CONFIG_SYS_SDIO2 "_ahb_clk";
+		slpstr = CONFIG_SYS_SDIO2 "_sleep_clk";
+		break;
+	case CONFIG_SYS_SDIO_BASE3:
+		clkstr = CONFIG_SYS_SDIO3 "_clk";
+		ahbstr = CONFIG_SYS_SDIO3 "_ahb_clk";
+		slpstr = CONFIG_SYS_SDIO3 "_sleep_clk";
+		break;
+	default:
+		printf("%s: base 0x%p not found\n", __func__, base);
+		return -EINVAL;
+	}
+
+	ret = clk_get_and_enable(ahbstr);
+	if (ret)
+		return ret;
+
+	ret = clk_get_and_enable(slpstr);
+	if (ret)
+		return ret;
+
+	c = clk_get(clkstr);
+	if (c) {
+		ret = clk_set_rate(c, rate);
+		if (ret)
+			return ret;
+
+		ret = clk_enable(c);
+		if (ret)
+			return ret;
+	} else {
+		printf("%s: Couldn't find %s\n", __func__, clkstr);
+		return -EINVAL;
+	}
+	*actual_ratep = rate;
+	return 0;
+}
diff --git a/arch/arm/cpu/armv7/bcm281xx/reset.c b/arch/arm/cpu/armv7/bcm281xx/reset.c
new file mode 100644
index 0000000000..3beb0ed9c7
--- /dev/null
+++ b/arch/arm/cpu/armv7/bcm281xx/reset.c
@@ -0,0 +1,27 @@
+/*
+ * Copyright 2013 Broadcom Corporation.
+ *
+ * SPDX-License-Identifier:      GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/sysmap.h>
+
+#define EN_MASK		0x08000000	/* Enable timer */
+#define SRSTEN_MASK	0x04000000	/* Enable soft reset */
+#define CLKS_SHIFT	20		/* Clock period shift */
+#define LD_SHIFT	0		/* Reload value shift */
+
+void reset_cpu(ulong ignored)
+{
+	/*
+	 * Set WD enable, RST enable,
+	 * 3.9 msec clock period (8), reload value (8*3.9ms)
+	 */
+	u32 reg = EN_MASK + SRSTEN_MASK + (8 << CLKS_SHIFT) + (8 << LD_SHIFT);
+	writel(reg, SECWD2_BASE_ADDR);
+
+	while (1)
+		;	/* loop forever till reset */
+}
diff --git a/arch/arm/cpu/armv7/config.mk b/arch/arm/cpu/armv7/config.mk
index f0d9c04327..6c82c3b537 100644
--- a/arch/arm/cpu/armv7/config.mk
+++ b/arch/arm/cpu/armv7/config.mk
@@ -10,24 +10,9 @@
 PF_CPPFLAGS_ARMV7 := $(call cc-option, -march=armv7-a, -march=armv5)
 PLATFORM_CPPFLAGS += $(PF_CPPFLAGS_ARMV7)
 
-# =========================================================================
-#
-# Supply options according to compiler version
-#
-# =========================================================================
-PF_RELFLAGS_SLB_AT := $(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,))
-PLATFORM_RELFLAGS += $(PF_RELFLAGS_SLB_AT)
-
-# SEE README.arm-unaligned-accesses
+# On supported platforms we set the bit which causes us to trap on unaligned
+# memory access.  This is the opposite of what the compiler expects to be
+# the default so we must pass in -mno-unaligned-access so that it is aware
+# of our decision.
 PF_NO_UNALIGNED := $(call cc-option, -mno-unaligned-access,)
-PLATFORM_NO_UNALIGNED := $(PF_NO_UNALIGNED)
-
-ifneq ($(CONFIG_IMX_CONFIG),)
-ifdef CONFIG_SPL
-ifdef CONFIG_SPL_BUILD
-ALL-y	+= $(OBJTREE)/SPL
-endif
-else
-ALL-y	+= $(obj)u-boot.imx
-endif
-endif
+PLATFORM_CPPFLAGS += $(PF_NO_UNALIGNED)
diff --git a/arch/arm/cpu/armv7/exynos/Makefile b/arch/arm/cpu/armv7/exynos/Makefile
index eb1633fcfe..e207bd6af0 100644
--- a/arch/arm/cpu/armv7/exynos/Makefile
+++ b/arch/arm/cpu/armv7/exynos/Makefile
@@ -5,34 +5,12 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(SOC).o
-
-COBJS-y	+= clock.o power.o soc.o system.o pinmux.o tzpc.o
+obj-y	+= clock.o power.o soc.o system.o pinmux.o tzpc.o
 
 ifdef CONFIG_SPL_BUILD
-COBJS-$(CONFIG_EXYNOS5)	+= clock_init_exynos5.o
-COBJS-$(CONFIG_EXYNOS5)	+= dmc_common.o dmc_init_ddr3.o
-COBJS-$(CONFIG_EXYNOS4210)+= dmc_init_exynos4.o clock_init_exynos4.o
-COBJS-y	+= spl_boot.o
-COBJS-y	+= lowlevel_init.o
+obj-$(CONFIG_EXYNOS5)	+= clock_init_exynos5.o
+obj-$(CONFIG_EXYNOS5)	+= dmc_common.o dmc_init_ddr3.o
+obj-$(CONFIG_EXYNOS4210)+= dmc_init_exynos4.o clock_init_exynos4.o
+obj-y	+= spl_boot.o
+obj-y	+= lowlevel_init.o
 endif
-
-COBJS   := $(COBJS-y)
-SRCS	:= $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-
-all:	 $(obj).depend $(LIB)
-
-$(LIB):	$(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
diff --git a/arch/arm/cpu/armv7/exynos/clock.c b/arch/arm/cpu/armv7/exynos/clock.c
index 36fedd630c..1fea4d6663 100644
--- a/arch/arm/cpu/armv7/exynos/clock.c
+++ b/arch/arm/cpu/armv7/exynos/clock.c
@@ -26,7 +26,7 @@ struct clk_bit_info {
 };
 
 /* src_bit div_bit prediv_bit */
-static struct clk_bit_info clk_bit_info[PERIPH_ID_COUNT] = {
+static struct clk_bit_info clk_bit_info[] = {
 	{0,	0,	-1},
 	{4,	4,	-1},
 	{8,	8,	-1},
@@ -96,7 +96,7 @@ static int exynos_get_pll_clk(int pllreg, unsigned int r, unsigned int k)
 
 	freq = CONFIG_SYS_CLK_FREQ;
 
-	if (pllreg == EPLL) {
+	if (pllreg == EPLL || pllreg == RPLL) {
 		k = k & 0xffff;
 		/* FOUT = (MDIV + K / 65536) * FIN / (PDIV * 2^SDIV) */
 		fout = (m + k / PLL_DIV_65536) * (freq / (p * (1 << s)));
@@ -117,7 +117,7 @@ static int exynos_get_pll_clk(int pllreg, unsigned int r, unsigned int k)
 			div = PLL_DIV_1024;
 		else if (proid_is_exynos4412())
 			div = PLL_DIV_65535;
-		else if (proid_is_exynos5250())
+		else if (proid_is_exynos5250() || proid_is_exynos5420())
 			div = PLL_DIV_65536;
 		else
 			return 0;
@@ -362,6 +362,43 @@ unsigned long clock_get_periph_rate(int peripheral)
 		return 0;
 }
 
+/* exynos5420: return pll clock frequency */
+static unsigned long exynos5420_get_pll_clk(int pllreg)
+{
+	struct exynos5420_clock *clk =
+		(struct exynos5420_clock *)samsung_get_base_clock();
+	unsigned long r, k = 0;
+
+	switch (pllreg) {
+	case APLL:
+		r = readl(&clk->apll_con0);
+		break;
+	case MPLL:
+		r = readl(&clk->mpll_con0);
+		break;
+	case EPLL:
+		r = readl(&clk->epll_con0);
+		k = readl(&clk->epll_con1);
+		break;
+	case VPLL:
+		r = readl(&clk->vpll_con0);
+		k = readl(&clk->vpll_con1);
+		break;
+	case BPLL:
+		r = readl(&clk->bpll_con0);
+		break;
+	case RPLL:
+		r = readl(&clk->rpll_con0);
+		k = readl(&clk->rpll_con1);
+		break;
+	default:
+		printf("Unsupported PLL (%d)\n", pllreg);
+		return 0;
+	}
+
+	return exynos_get_pll_clk(pllreg, r, k);
+}
+
 /* exynos4: return ARM clock frequency */
 static unsigned long exynos4_get_arm_clk(void)
 {
@@ -485,6 +522,27 @@ static unsigned long exynos4x12_get_pwm_clk(void)
 	return pclk;
 }
 
+/* exynos5420: return pwm clock frequency */
+static unsigned long exynos5420_get_pwm_clk(void)
+{
+	struct exynos5420_clock *clk =
+		(struct exynos5420_clock *)samsung_get_base_clock();
+	unsigned long pclk, sclk;
+	unsigned int ratio;
+
+	/*
+	 * CLK_DIV_PERIC0
+	 * PWM_RATIO [31:28]
+	 */
+	ratio = readl(&clk->div_peric0);
+	ratio = (ratio >> 28) & 0xf;
+	sclk = get_pll_clk(MPLL);
+
+	pclk = sclk / (ratio + 1);
+
+	return pclk;
+}
+
 /* exynos4: return uart clock frequency */
 static unsigned long exynos4_get_uart_clk(int dev_index)
 {
@@ -624,6 +682,53 @@ static unsigned long exynos5_get_uart_clk(int dev_index)
 	return uclk;
 }
 
+/* exynos5420: return uart clock frequency */
+static unsigned long exynos5420_get_uart_clk(int dev_index)
+{
+	struct exynos5420_clock *clk =
+		(struct exynos5420_clock *)samsung_get_base_clock();
+	unsigned long uclk, sclk;
+	unsigned int sel;
+	unsigned int ratio;
+
+	/*
+	 * CLK_SRC_PERIC0
+	 * UART0_SEL [6:4]
+	 * UART1_SEL [10:8]
+	 * UART2_SEL [14:12]
+	 * UART3_SEL [18:16]
+	 * generalised calculation as follows
+	 * sel = (sel >> ((dev_index * 4) + 4)) & mask;
+	 */
+	sel = readl(&clk->src_peric0);
+	sel = (sel >> ((dev_index * 4) + 4)) & 0x7;
+
+	if (sel == 0x3)
+		sclk = get_pll_clk(MPLL);
+	else if (sel == 0x6)
+		sclk = get_pll_clk(EPLL);
+	else if (sel == 0x7)
+		sclk = get_pll_clk(RPLL);
+	else
+		return 0;
+
+	/*
+	 * CLK_DIV_PERIC0
+	 * UART0_RATIO [11:8]
+	 * UART1_RATIO [15:12]
+	 * UART2_RATIO [19:16]
+	 * UART3_RATIO [23:20]
+	 * generalised calculation as follows
+	 * ratio = (ratio >> ((dev_index * 4) + 8)) & mask;
+	 */
+	ratio = readl(&clk->div_peric0);
+	ratio = (ratio >> ((dev_index * 4) + 8)) & 0xf;
+
+	uclk = sclk / (ratio + 1);
+
+	return uclk;
+}
+
 static unsigned long exynos4_get_mmc_clk(int dev_index)
 {
 	struct exynos4_clock *clk =
@@ -718,13 +823,53 @@ static unsigned long exynos5_get_mmc_clk(int dev_index)
 	return uclk;
 }
 
+static unsigned long exynos5420_get_mmc_clk(int dev_index)
+{
+	struct exynos5420_clock *clk =
+		(struct exynos5420_clock *)samsung_get_base_clock();
+	unsigned long uclk, sclk;
+	unsigned int sel, ratio;
+
+	/*
+	 * CLK_SRC_FSYS
+	 * MMC0_SEL [10:8]
+	 * MMC1_SEL [14:12]
+	 * MMC2_SEL [18:16]
+	 * generalised calculation as follows
+	 * sel = (sel >> ((dev_index * 4) + 8)) & mask
+	 */
+	sel = readl(&clk->src_fsys);
+	sel = (sel >> ((dev_index * 4) + 8)) & 0x7;
+
+	if (sel == 0x3)
+		sclk = get_pll_clk(MPLL);
+	else if (sel == 0x6)
+		sclk = get_pll_clk(EPLL);
+	else
+		return 0;
+
+	/*
+	 * CLK_DIV_FSYS1
+	 * MMC0_RATIO [9:0]
+	 * MMC1_RATIO [19:10]
+	 * MMC2_RATIO [29:20]
+	 * generalised calculation as follows
+	 * ratio = (ratio >> (dev_index * 10)) & mask
+	 */
+	ratio = readl(&clk->div_fsys1);
+	ratio = (ratio >> (dev_index * 10)) & 0x3ff;
+
+	uclk = (sclk / (ratio + 1));
+
+	return uclk;
+}
+
 /* exynos4: set the mmc clock */
 static void exynos4_set_mmc_clk(int dev_index, unsigned int div)
 {
 	struct exynos4_clock *clk =
 		(struct exynos4_clock *)samsung_get_base_clock();
 	unsigned int addr;
-	unsigned int val;
 
 	/*
 	 * CLK_DIV_FSYS1
@@ -744,10 +889,8 @@ static void exynos4_set_mmc_clk(int dev_index, unsigned int div)
 		dev_index -= 2;
 	}
 
-	val = readl(addr);
-	val &= ~(0xff << ((dev_index << 4) + 8));
-	val |= (div & 0xff) << ((dev_index << 4) + 8);
-	writel(val, addr);
+	clrsetbits_le32(addr, 0xff << ((dev_index << 4) + 8),
+			(div & 0xff) << ((dev_index << 4) + 8));
 }
 
 /* exynos4x12: set the mmc clock */
@@ -756,7 +899,6 @@ static void exynos4x12_set_mmc_clk(int dev_index, unsigned int div)
 	struct exynos4x12_clock *clk =
 		(struct exynos4x12_clock *)samsung_get_base_clock();
 	unsigned int addr;
-	unsigned int val;
 
 	/*
 	 * CLK_DIV_FSYS1
@@ -771,10 +913,8 @@ static void exynos4x12_set_mmc_clk(int dev_index, unsigned int div)
 		dev_index -= 2;
 	}
 
-	val = readl(addr);
-	val &= ~(0xff << ((dev_index << 4) + 8));
-	val |= (div & 0xff) << ((dev_index << 4) + 8);
-	writel(val, addr);
+	clrsetbits_le32(addr, 0xff << ((dev_index << 4) + 8),
+			(div & 0xff) << ((dev_index << 4) + 8));
 }
 
 /* exynos5: set the mmc clock */
@@ -783,7 +923,6 @@ static void exynos5_set_mmc_clk(int dev_index, unsigned int div)
 	struct exynos5_clock *clk =
 		(struct exynos5_clock *)samsung_get_base_clock();
 	unsigned int addr;
-	unsigned int val;
 
 	/*
 	 * CLK_DIV_FSYS1
@@ -798,10 +937,28 @@ static void exynos5_set_mmc_clk(int dev_index, unsigned int div)
 		dev_index -= 2;
 	}
 
-	val = readl(addr);
-	val &= ~(0xff << ((dev_index << 4) + 8));
-	val |= (div & 0xff) << ((dev_index << 4) + 8);
-	writel(val, addr);
+	clrsetbits_le32(addr, 0xff << ((dev_index << 4) + 8),
+			(div & 0xff) << ((dev_index << 4) + 8));
+}
+
+/* exynos5: set the mmc clock */
+static void exynos5420_set_mmc_clk(int dev_index, unsigned int div)
+{
+	struct exynos5420_clock *clk =
+		(struct exynos5420_clock *)samsung_get_base_clock();
+	unsigned int addr;
+	unsigned int shift;
+
+	/*
+	 * CLK_DIV_FSYS1
+	 * MMC0_RATIO [9:0]
+	 * MMC1_RATIO [19:10]
+	 * MMC2_RATIO [29:20]
+	 */
+	addr = (unsigned int)&clk->div_fsys1;
+	shift = dev_index * 10;
+
+	clrsetbits_le32(addr, 0x3ff << shift, (div & 0x3ff) << shift);
 }
 
 /* get_lcd_clk: return lcd clock frequency */
@@ -892,7 +1049,6 @@ void exynos4_set_lcd_clk(void)
 {
 	struct exynos4_clock *clk =
 	    (struct exynos4_clock *)samsung_get_base_clock();
-	unsigned int cfg = 0;
 
 	/*
 	 * CLK_GATE_BLOCK
@@ -904,9 +1060,7 @@ void exynos4_set_lcd_clk(void)
 	 * CLK_LCD1	[5]
 	 * CLK_GPS	[7]
 	 */
-	cfg = readl(&clk->gate_block);
-	cfg |= 1 << 4;
-	writel(cfg, &clk->gate_block);
+	setbits_le32(&clk->gate_block, 1 << 4);
 
 	/*
 	 * CLK_SRC_LCD0
@@ -916,10 +1070,7 @@ void exynos4_set_lcd_clk(void)
 	 * MIPI0_SEL		[12:15]
 	 * set lcd0 src clock 0x6: SCLK_MPLL
 	 */
-	cfg = readl(&clk->src_lcd0);
-	cfg &= ~(0xf);
-	cfg |= 0x6;
-	writel(cfg, &clk->src_lcd0);
+	clrsetbits_le32(&clk->src_lcd0, 0xf, 0x6);
 
 	/*
 	 * CLK_GATE_IP_LCD0
@@ -931,9 +1082,7 @@ void exynos4_set_lcd_clk(void)
 	 * CLK_PPMULCD0		[5]
 	 * Gating all clocks for FIMD0
 	 */
-	cfg = readl(&clk->gate_ip_lcd0);
-	cfg |= 1 << 0;
-	writel(cfg, &clk->gate_ip_lcd0);
+	setbits_le32(&clk->gate_ip_lcd0, 1 << 0);
 
 	/*
 	 * CLK_DIV_LCD0
@@ -945,16 +1094,13 @@ void exynos4_set_lcd_clk(void)
 	 * MIPI0_PRE_RATIO	[23:20]
 	 * set fimd ratio
 	 */
-	cfg &= ~(0xf);
-	cfg |= 0x1;
-	writel(cfg, &clk->div_lcd0);
+	clrsetbits_le32(&clk->div_lcd0, 0xf, 0x1);
 }
 
 void exynos5_set_lcd_clk(void)
 {
 	struct exynos5_clock *clk =
 	    (struct exynos5_clock *)samsung_get_base_clock();
-	unsigned int cfg = 0;
 
 	/*
 	 * CLK_GATE_BLOCK
@@ -966,9 +1112,7 @@ void exynos5_set_lcd_clk(void)
 	 * CLK_LCD1	[5]
 	 * CLK_GPS	[7]
 	 */
-	cfg = readl(&clk->gate_block);
-	cfg |= 1 << 4;
-	writel(cfg, &clk->gate_block);
+	setbits_le32(&clk->gate_block, 1 << 4);
 
 	/*
 	 * CLK_SRC_LCD0
@@ -978,10 +1122,7 @@ void exynos5_set_lcd_clk(void)
 	 * MIPI0_SEL		[12:15]
 	 * set lcd0 src clock 0x6: SCLK_MPLL
 	 */
-	cfg = readl(&clk->src_disp1_0);
-	cfg &= ~(0xf);
-	cfg |= 0x6;
-	writel(cfg, &clk->src_disp1_0);
+	clrsetbits_le32(&clk->src_disp1_0, 0xf, 0x6);
 
 	/*
 	 * CLK_GATE_IP_LCD0
@@ -993,9 +1134,7 @@ void exynos5_set_lcd_clk(void)
 	 * CLK_PPMULCD0		[5]
 	 * Gating all clocks for FIMD0
 	 */
-	cfg = readl(&clk->gate_ip_disp1);
-	cfg |= 1 << 0;
-	writel(cfg, &clk->gate_ip_disp1);
+	setbits_le32(&clk->gate_ip_disp1, 1 << 0);
 
 	/*
 	 * CLK_DIV_LCD0
@@ -1007,16 +1146,13 @@ void exynos5_set_lcd_clk(void)
 	 * MIPI0_PRE_RATIO	[23:20]
 	 * set fimd ratio
 	 */
-	cfg &= ~(0xf);
-	cfg |= 0x0;
-	writel(cfg, &clk->div_disp1_0);
+	clrsetbits_le32(&clk->div_disp1_0, 0xf, 0x0);
 }
 
 void exynos4_set_mipi_clk(void)
 {
 	struct exynos4_clock *clk =
 	    (struct exynos4_clock *)samsung_get_base_clock();
-	unsigned int cfg = 0;
 
 	/*
 	 * CLK_SRC_LCD0
@@ -1026,10 +1162,7 @@ void exynos4_set_mipi_clk(void)
 	 * MIPI0_SEL		[12:15]
 	 * set mipi0 src clock 0x6: SCLK_MPLL
 	 */
-	cfg = readl(&clk->src_lcd0);
-	cfg &= ~(0xf << 12);
-	cfg |= (0x6 << 12);
-	writel(cfg, &clk->src_lcd0);
+	clrsetbits_le32(&clk->src_lcd0, 0xf << 12, 0x6 << 12);
 
 	/*
 	 * CLK_SRC_MASK_LCD0
@@ -1039,9 +1172,7 @@ void exynos4_set_mipi_clk(void)
 	 * MIPI0_MASK		[12]
 	 * set src mask mipi0 0x1: Unmask
 	 */
-	cfg = readl(&clk->src_mask_lcd0);
-	cfg |= (0x1 << 12);
-	writel(cfg, &clk->src_mask_lcd0);
+	setbits_le32(&clk->src_mask_lcd0, 0x1 << 12);
 
 	/*
 	 * CLK_GATE_IP_LCD0
@@ -1053,9 +1184,7 @@ void exynos4_set_mipi_clk(void)
 	 * CLK_PPMULCD0		[5]
 	 * Gating all clocks for MIPI0
 	 */
-	cfg = readl(&clk->gate_ip_lcd0);
-	cfg |= 1 << 3;
-	writel(cfg, &clk->gate_ip_lcd0);
+	setbits_le32(&clk->gate_ip_lcd0, 1 << 3);
 
 	/*
 	 * CLK_DIV_LCD0
@@ -1067,9 +1196,7 @@ void exynos4_set_mipi_clk(void)
 	 * MIPI0_PRE_RATIO	[23:20]
 	 * set mipi ratio
 	 */
-	cfg &= ~(0xf << 16);
-	cfg |= (0x1 << 16);
-	writel(cfg, &clk->div_lcd0);
+	clrsetbits_le32(&clk->div_lcd0, 0xf << 16, 0x1 << 16);
 }
 
 /*
@@ -1324,6 +1451,71 @@ static int exynos5_set_spi_clk(enum periph_id periph_id,
 	return 0;
 }
 
+static int exynos5420_set_spi_clk(enum periph_id periph_id,
+					unsigned int rate)
+{
+	struct exynos5420_clock *clk =
+		(struct exynos5420_clock *)samsung_get_base_clock();
+	int main;
+	unsigned int fine;
+	unsigned shift, pre_shift;
+	unsigned div_mask = 0xf, pre_div_mask = 0xff;
+	u32 *reg;
+	u32 *pre_reg;
+
+	main = clock_calc_best_scalar(4, 8, 400000000, rate, &fine);
+	if (main < 0) {
+		debug("%s: Cannot set clock rate for periph %d",
+		      __func__, periph_id);
+		return -1;
+	}
+	main = main - 1;
+	fine = fine - 1;
+
+	switch (periph_id) {
+	case PERIPH_ID_SPI0:
+		reg = &clk->div_peric1;
+		shift = 20;
+		pre_reg = &clk->div_peric4;
+		pre_shift = 8;
+		break;
+	case PERIPH_ID_SPI1:
+		reg = &clk->div_peric1;
+		shift = 24;
+		pre_reg = &clk->div_peric4;
+		pre_shift = 16;
+		break;
+	case PERIPH_ID_SPI2:
+		reg = &clk->div_peric1;
+		shift = 28;
+		pre_reg = &clk->div_peric4;
+		pre_shift = 24;
+		break;
+	case PERIPH_ID_SPI3:
+		reg = &clk->div_isp1;
+		shift = 16;
+		pre_reg = &clk->div_isp1;
+		pre_shift = 0;
+		break;
+	case PERIPH_ID_SPI4:
+		reg = &clk->div_isp1;
+		shift = 20;
+		pre_reg = &clk->div_isp1;
+		pre_shift = 8;
+		break;
+	default:
+		debug("%s: Unsupported peripheral ID %d\n", __func__,
+		      periph_id);
+		return -1;
+	}
+
+	clrsetbits_le32(reg, div_mask << shift, (main & div_mask) << shift);
+	clrsetbits_le32(pre_reg, pre_div_mask << pre_shift,
+			(fine & pre_div_mask) << pre_shift);
+
+	return 0;
+}
+
 static unsigned long exynos4_get_i2c_clk(void)
 {
 	struct exynos4_clock *clk =
@@ -1341,9 +1533,11 @@ static unsigned long exynos4_get_i2c_clk(void)
 
 unsigned long get_pll_clk(int pllreg)
 {
-	if (cpu_is_exynos5())
+	if (cpu_is_exynos5()) {
+		if (proid_is_exynos5420())
+			return exynos5420_get_pll_clk(pllreg);
 		return exynos5_get_pll_clk(pllreg);
-	else {
+	} else {
 		if (proid_is_exynos4412())
 			return exynos4x12_get_pll_clk(pllreg);
 		return exynos4_get_pll_clk(pllreg);
@@ -1375,9 +1569,11 @@ unsigned long get_i2c_clk(void)
 
 unsigned long get_pwm_clk(void)
 {
-	if (cpu_is_exynos5())
+	if (cpu_is_exynos5()) {
+		if (proid_is_exynos5420())
+			return exynos5420_get_pwm_clk();
 		return clock_get_periph_rate(PERIPH_ID_PWM0);
-	else {
+	} else {
 		if (proid_is_exynos4412())
 			return exynos4x12_get_pwm_clk();
 		return exynos4_get_pwm_clk();
@@ -1386,9 +1582,11 @@ unsigned long get_pwm_clk(void)
 
 unsigned long get_uart_clk(int dev_index)
 {
-	if (cpu_is_exynos5())
+	if (cpu_is_exynos5()) {
+		if (proid_is_exynos5420())
+			return exynos5420_get_uart_clk(dev_index);
 		return exynos5_get_uart_clk(dev_index);
-	else {
+	} else {
 		if (proid_is_exynos4412())
 			return exynos4x12_get_uart_clk(dev_index);
 		return exynos4_get_uart_clk(dev_index);
@@ -1397,20 +1595,27 @@ unsigned long get_uart_clk(int dev_index)
 
 unsigned long get_mmc_clk(int dev_index)
 {
-	if (cpu_is_exynos5())
+	if (cpu_is_exynos5()) {
+		if (proid_is_exynos5420())
+			return exynos5420_get_mmc_clk(dev_index);
 		return exynos5_get_mmc_clk(dev_index);
-	else
+	} else {
 		return exynos4_get_mmc_clk(dev_index);
+	}
 }
 
 void set_mmc_clk(int dev_index, unsigned int div)
 {
-	if (cpu_is_exynos5())
-		exynos5_set_mmc_clk(dev_index, div);
-	else {
+	if (cpu_is_exynos5()) {
+		if (proid_is_exynos5420())
+			exynos5420_set_mmc_clk(dev_index, div);
+		else
+			exynos5_set_mmc_clk(dev_index, div);
+	} else {
 		if (proid_is_exynos4412())
 			exynos4x12_set_mmc_clk(dev_index, div);
-		exynos4_set_mmc_clk(dev_index, div);
+		else
+			exynos4_set_mmc_clk(dev_index, div);
 	}
 }
 
@@ -1438,10 +1643,13 @@ void set_mipi_clk(void)
 
 int set_spi_clk(int periph_id, unsigned int rate)
 {
-	if (cpu_is_exynos5())
+	if (cpu_is_exynos5()) {
+		if (proid_is_exynos5420())
+			return exynos5420_set_spi_clk(periph_id, rate);
 		return exynos5_set_spi_clk(periph_id, rate);
-	else
+	} else {
 		return 0;
+	}
 }
 
 int set_i2s_clk_prescaler(unsigned int src_frq, unsigned int dst_frq,
diff --git a/arch/arm/cpu/armv7/exynos/clock_init.h b/arch/arm/cpu/armv7/exynos/clock_init.h
index c28ff3ab14..a875d0b48f 100644
--- a/arch/arm/cpu/armv7/exynos/clock_init.h
+++ b/arch/arm/cpu/armv7/exynos/clock_init.h
@@ -10,7 +10,11 @@
 #define __EXYNOS_CLOCK_INIT_H
 
 enum {
+#ifdef CONFIG_EXYNOS5420
+	MEM_TIMINGS_MSR_COUNT	= 5,
+#else
 	MEM_TIMINGS_MSR_COUNT	= 4,
+#endif
 };
 
 /* These are the ratio's for configuring ARM clock */
@@ -59,6 +63,18 @@ struct mem_timings {
 	unsigned bpll_mdiv;
 	unsigned bpll_pdiv;
 	unsigned bpll_sdiv;
+	unsigned kpll_mdiv;
+	unsigned kpll_pdiv;
+	unsigned kpll_sdiv;
+	unsigned dpll_mdiv;
+	unsigned dpll_pdiv;
+	unsigned dpll_sdiv;
+	unsigned ipll_mdiv;
+	unsigned ipll_pdiv;
+	unsigned ipll_sdiv;
+	unsigned spll_mdiv;
+	unsigned spll_pdiv;
+	unsigned spll_sdiv;
 	unsigned pclk_cdrex_ratio;
 	unsigned direct_cmd_msr[MEM_TIMINGS_MSR_COUNT];
 
@@ -115,6 +131,7 @@ struct mem_timings {
 	uint8_t send_zq_init;		/* 1 to send this command */
 	unsigned impedance;		/* drive strength impedeance */
 	uint8_t gate_leveling_enable;	/* check gate leveling is enabled */
+	uint8_t read_leveling_enable;	/* check h/w read leveling is enabled */
 };
 
 /**
diff --git a/arch/arm/cpu/armv7/exynos/clock_init_exynos5.c b/arch/arm/cpu/armv7/exynos/clock_init_exynos5.c
index a24c2f3875..1d6977fa43 100644
--- a/arch/arm/cpu/armv7/exynos/clock_init_exynos5.c
+++ b/arch/arm/cpu/armv7/exynos/clock_init_exynos5.c
@@ -24,6 +24,24 @@
 DECLARE_GLOBAL_DATA_PTR;
 
 struct arm_clk_ratios arm_clk_ratios[] = {
+#ifdef CONFIG_EXYNOS5420
+	{
+		.arm_freq_mhz = 900,
+
+		.apll_mdiv = 0x96,
+		.apll_pdiv = 0x2,
+		.apll_sdiv = 0x1,
+
+		.arm2_ratio = 0x0,
+		.apll_ratio = 0x3,
+		.pclk_dbg_ratio = 0x6,
+		.atb_ratio = 0x6,
+		.periph_ratio = 0x7,
+		.acp_ratio = 0x0,
+		.cpud_ratio = 0x2,
+		.arm_ratio = 0x0,
+	}
+#else
 	{
 		.arm_freq_mhz = 600,
 
@@ -115,8 +133,133 @@ struct arm_clk_ratios arm_clk_ratios[] = {
 		.cpud_ratio = 0x3,
 		.arm_ratio = 0x0,
 	}
+#endif
 };
+
 struct mem_timings mem_timings[] = {
+#ifdef CONFIG_EXYNOS5420
+	{
+		.mem_manuf = MEM_MANUF_SAMSUNG,
+		.mem_type = DDR_MODE_DDR3,
+		.frequency_mhz = 800,
+
+		/* MPLL @800MHz*/
+		.mpll_mdiv = 0xc8,
+		.mpll_pdiv = 0x3,
+		.mpll_sdiv = 0x1,
+		/* CPLL @666MHz */
+		.cpll_mdiv = 0xde,
+		.cpll_pdiv = 0x4,
+		.cpll_sdiv = 0x1,
+		/* EPLL @600MHz */
+		.epll_mdiv = 0x64,
+		.epll_pdiv = 0x2,
+		.epll_sdiv = 0x1,
+		/* VPLL @430MHz */
+		.vpll_mdiv = 0xd7,
+		.vpll_pdiv = 0x3,
+		.vpll_sdiv = 0x2,
+		/* BPLL @800MHz */
+		.bpll_mdiv = 0xc8,
+		.bpll_pdiv = 0x3,
+		.bpll_sdiv = 0x1,
+		/* KPLL @600MHz */
+		.kpll_mdiv = 0x190,
+		.kpll_pdiv = 0x4,
+		.kpll_sdiv = 0x2,
+		/* DPLL @600MHz */
+		.dpll_mdiv = 0x190,
+		.dpll_pdiv = 0x4,
+		.dpll_sdiv = 0x2,
+		/* IPLL @370MHz */
+		.ipll_mdiv = 0xb9,
+		.ipll_pdiv = 0x3,
+		.ipll_sdiv = 0x2,
+		/* SPLL @400MHz */
+		.spll_mdiv = 0xc8,
+		.spll_pdiv = 0x3,
+		.spll_sdiv = 0x2,
+
+		.direct_cmd_msr = {
+			0x00020018, 0x00030000, 0x00010046, 0x00000d70,
+			0x00000c70
+		},
+		.timing_ref = 0x000000bb,
+		.timing_row = 0x6836650f,
+		.timing_data = 0x3630580b,
+		.timing_power = 0x41000a26,
+		.phy0_dqs = 0x08080808,
+		.phy1_dqs = 0x08080808,
+		.phy0_dq = 0x08080808,
+		.phy1_dq = 0x08080808,
+		.phy0_tFS = 0x8,
+		.phy1_tFS = 0x8,
+		.phy0_pulld_dqs = 0xf,
+		.phy1_pulld_dqs = 0xf,
+
+		.lpddr3_ctrl_phy_reset = 0x1,
+		.ctrl_start_point = 0x10,
+		.ctrl_inc = 0x10,
+		.ctrl_start = 0x1,
+		.ctrl_dll_on = 0x1,
+		.ctrl_ref = 0x8,
+
+		.ctrl_force = 0x1a,
+		.ctrl_rdlat = 0x0b,
+		.ctrl_bstlen = 0x08,
+
+		.fp_resync = 0x8,
+		.iv_size = 0x7,
+		.dfi_init_start = 1,
+		.aref_en = 1,
+
+		.rd_fetch = 0x3,
+
+		.zq_mode_dds = 0x7,
+		.zq_mode_term = 0x1,
+		.zq_mode_noterm = 1,
+
+		/*
+		* Dynamic Clock: Always Running
+		* Memory Burst length: 8
+		* Number of chips: 1
+		* Memory Bus width: 32 bit
+		* Memory Type: DDR3
+		* Additional Latancy for PLL: 0 Cycle
+		*/
+		.memcontrol = DMC_MEMCONTROL_CLK_STOP_DISABLE |
+			DMC_MEMCONTROL_DPWRDN_DISABLE |
+			DMC_MEMCONTROL_DPWRDN_ACTIVE_PRECHARGE |
+			DMC_MEMCONTROL_TP_DISABLE |
+			DMC_MEMCONTROL_DSREF_DISABLE |
+			DMC_MEMCONTROL_ADD_LAT_PALL_CYCLE(0) |
+			DMC_MEMCONTROL_MEM_TYPE_DDR3 |
+			DMC_MEMCONTROL_MEM_WIDTH_32BIT |
+			DMC_MEMCONTROL_NUM_CHIP_1 |
+			DMC_MEMCONTROL_BL_8 |
+			DMC_MEMCONTROL_PZQ_DISABLE |
+			DMC_MEMCONTROL_MRR_BYTE_7_0,
+		.memconfig = DMC_MEMCONFIG_CHIP_MAP_SPLIT |
+			DMC_MEMCONFIGX_CHIP_COL_10 |
+			DMC_MEMCONFIGX_CHIP_ROW_15 |
+			DMC_MEMCONFIGX_CHIP_BANK_8,
+		.prechconfig_tp_cnt = 0xff,
+		.dpwrdn_cyc = 0xff,
+		.dsref_cyc = 0xffff,
+		.concontrol = DMC_CONCONTROL_DFI_INIT_START_DISABLE |
+			DMC_CONCONTROL_TIMEOUT_LEVEL0 |
+			DMC_CONCONTROL_RD_FETCH_DISABLE |
+			DMC_CONCONTROL_EMPTY_DISABLE |
+			DMC_CONCONTROL_AREF_EN_DISABLE |
+			DMC_CONCONTROL_IO_PD_CON_DISABLE,
+		.dmc_channels = 1,
+		.chips_per_channel = 1,
+		.chips_to_configure = 1,
+		.send_zq_init = 1,
+		.gate_leveling_enable = 1,
+		.read_leveling_enable = 0,
+	}
+#else
 	{
 		.mem_manuf = MEM_MANUF_ELPIDA,
 		.mem_type = DDR_MODE_DDR3,
@@ -324,6 +467,7 @@ struct mem_timings mem_timings[] = {
 		.impedance = IMP_OUTPUT_DRV_40_OHM,
 		.gate_leveling_enable = 1,
 	}
+#endif
 };
 
 /**
@@ -399,7 +543,7 @@ struct mem_timings *clock_get_mem_timings(void)
 	return NULL;
 }
 
-void system_clock_init()
+static void exynos5250_system_clock_init(void)
 {
 	struct exynos5_clock *clk =
 		(struct exynos5_clock *)samsung_get_base_clock();
@@ -436,19 +580,13 @@ void system_clock_init()
 	} while ((val | MUX_BPLL_SEL_MASK) != val);
 
 	/* PLL locktime */
-	writel(APLL_LOCK_VAL, &clk->apll_lock);
-
-	writel(MPLL_LOCK_VAL, &clk->mpll_lock);
-
-	writel(BPLL_LOCK_VAL, &clk->bpll_lock);
-
-	writel(CPLL_LOCK_VAL, &clk->cpll_lock);
-
-	writel(GPLL_LOCK_VAL, &clk->gpll_lock);
-
-	writel(EPLL_LOCK_VAL, &clk->epll_lock);
-
-	writel(VPLL_LOCK_VAL, &clk->vpll_lock);
+	writel(mem->apll_pdiv * PLL_LOCK_FACTOR, &clk->apll_lock);
+	writel(mem->mpll_pdiv * PLL_LOCK_FACTOR, &clk->mpll_lock);
+	writel(mem->bpll_pdiv * PLL_LOCK_FACTOR, &clk->bpll_lock);
+	writel(mem->cpll_pdiv * PLL_LOCK_FACTOR, &clk->cpll_lock);
+	writel(mem->gpll_pdiv * PLL_X_LOCK_FACTOR, &clk->gpll_lock);
+	writel(mem->epll_pdiv * PLL_X_LOCK_FACTOR, &clk->epll_lock);
+	writel(mem->vpll_pdiv * PLL_X_LOCK_FACTOR, &clk->vpll_lock);
 
 	writel(CLK_REG_DISABLE, &clk->pll_div2_sel);
 
@@ -640,6 +778,192 @@ void system_clock_init()
 	writel(val, &clk->div_fsys2);
 }
 
+static void exynos5420_system_clock_init(void)
+{
+	struct exynos5420_clock *clk =
+		(struct exynos5420_clock *)samsung_get_base_clock();
+	struct mem_timings *mem;
+	struct arm_clk_ratios *arm_clk_ratio;
+	u32 val;
+
+	mem = clock_get_mem_timings();
+	arm_clk_ratio = get_arm_ratios();
+
+	/* PLL locktime */
+	writel(arm_clk_ratio->apll_pdiv * PLL_LOCK_FACTOR, &clk->apll_lock);
+	writel(mem->mpll_pdiv * PLL_LOCK_FACTOR, &clk->mpll_lock);
+	writel(mem->bpll_pdiv * PLL_LOCK_FACTOR, &clk->bpll_lock);
+	writel(mem->cpll_pdiv * PLL_LOCK_FACTOR, &clk->cpll_lock);
+	writel(mem->dpll_pdiv * PLL_LOCK_FACTOR, &clk->dpll_lock);
+	writel(mem->epll_pdiv * PLL_X_LOCK_FACTOR, &clk->epll_lock);
+	writel(mem->vpll_pdiv * PLL_LOCK_FACTOR, &clk->vpll_lock);
+	writel(mem->ipll_pdiv * PLL_LOCK_FACTOR, &clk->ipll_lock);
+	writel(mem->spll_pdiv * PLL_LOCK_FACTOR, &clk->spll_lock);
+	writel(mem->kpll_pdiv * PLL_LOCK_FACTOR, &clk->kpll_lock);
+
+	setbits_le32(&clk->src_cpu, MUX_HPM_SEL_MASK);
+
+	writel(0, &clk->src_top6);
+
+	writel(0, &clk->src_cdrex);
+	writel(SRC_KFC_HPM_SEL, &clk->src_kfc);
+	writel(HPM_RATIO,  &clk->div_cpu1);
+	writel(CLK_DIV_CPU0_VAL,  &clk->div_cpu0);
+
+	/* switch A15 clock source to OSC clock before changing APLL */
+	clrbits_le32(&clk->src_cpu, APLL_FOUT);
+
+	/* Set APLL */
+	writel(APLL_CON1_VAL, &clk->apll_con1);
+	val = set_pll(arm_clk_ratio->apll_mdiv,
+		      arm_clk_ratio->apll_pdiv,
+		      arm_clk_ratio->apll_sdiv);
+	writel(val, &clk->apll_con0);
+	while ((readl(&clk->apll_con0) & PLL_LOCKED) == 0)
+		;
+
+	/* now it is safe to switch to APLL */
+	setbits_le32(&clk->src_cpu, APLL_FOUT);
+
+	writel(SRC_KFC_HPM_SEL, &clk->src_kfc);
+	writel(CLK_DIV_KFC_VAL, &clk->div_kfc0);
+
+	/* switch A7 clock source to OSC clock before changing KPLL */
+	clrbits_le32(&clk->src_kfc, KPLL_FOUT);
+
+	/* Set KPLL*/
+	writel(KPLL_CON1_VAL, &clk->kpll_con1);
+	val = set_pll(mem->kpll_mdiv, mem->kpll_pdiv, mem->kpll_sdiv);
+	writel(val, &clk->kpll_con0);
+	while ((readl(&clk->kpll_con0) & PLL_LOCKED) == 0)
+		;
+
+	/* now it is safe to switch to KPLL */
+	setbits_le32(&clk->src_kfc, KPLL_FOUT);
+
+	/* Set MPLL */
+	writel(MPLL_CON1_VAL, &clk->mpll_con1);
+	val = set_pll(mem->mpll_mdiv, mem->mpll_pdiv, mem->mpll_sdiv);
+	writel(val, &clk->mpll_con0);
+	while ((readl(&clk->mpll_con0) & PLL_LOCKED) == 0)
+		;
+
+	/* Set DPLL */
+	writel(DPLL_CON1_VAL, &clk->dpll_con1);
+	val = set_pll(mem->dpll_mdiv, mem->dpll_pdiv, mem->dpll_sdiv);
+	writel(val, &clk->dpll_con0);
+	while ((readl(&clk->dpll_con0) & PLL_LOCKED) == 0)
+		;
+
+	/* Set EPLL */
+	writel(EPLL_CON2_VAL, &clk->epll_con2);
+	writel(EPLL_CON1_VAL, &clk->epll_con1);
+	val = set_pll(mem->epll_mdiv, mem->epll_pdiv, mem->epll_sdiv);
+	writel(val, &clk->epll_con0);
+	while ((readl(&clk->epll_con0) & PLL_LOCKED) == 0)
+		;
+
+	/* Set CPLL */
+	writel(CPLL_CON1_VAL, &clk->cpll_con1);
+	val = set_pll(mem->cpll_mdiv, mem->cpll_pdiv, mem->cpll_sdiv);
+	writel(val, &clk->cpll_con0);
+	while ((readl(&clk->cpll_con0) & PLL_LOCKED) == 0)
+		;
+
+	/* Set IPLL */
+	writel(IPLL_CON1_VAL, &clk->ipll_con1);
+	val = set_pll(mem->ipll_mdiv, mem->ipll_pdiv, mem->ipll_sdiv);
+	writel(val, &clk->ipll_con0);
+	while ((readl(&clk->ipll_con0) & PLL_LOCKED) == 0)
+		;
+
+	/* Set VPLL */
+	writel(VPLL_CON1_VAL, &clk->vpll_con1);
+	val = set_pll(mem->vpll_mdiv, mem->vpll_pdiv, mem->vpll_sdiv);
+	writel(val, &clk->vpll_con0);
+	while ((readl(&clk->vpll_con0) & PLL_LOCKED) == 0)
+		;
+
+	/* Set BPLL */
+	writel(BPLL_CON1_VAL, &clk->bpll_con1);
+	val = set_pll(mem->bpll_mdiv, mem->bpll_pdiv, mem->bpll_sdiv);
+	writel(val, &clk->bpll_con0);
+	while ((readl(&clk->bpll_con0) & PLL_LOCKED) == 0)
+		;
+
+	/* Set SPLL */
+	writel(SPLL_CON1_VAL, &clk->spll_con1);
+	val = set_pll(mem->spll_mdiv, mem->spll_pdiv, mem->spll_sdiv);
+	writel(val, &clk->spll_con0);
+	while ((readl(&clk->spll_con0) & PLL_LOCKED) == 0)
+		;
+
+	writel(CLK_DIV_CDREX0_VAL, &clk->div_cdrex0);
+	writel(CLK_DIV_CDREX1_VAL, &clk->div_cdrex1);
+
+	writel(CLK_SRC_TOP0_VAL, &clk->src_top0);
+	writel(CLK_SRC_TOP1_VAL, &clk->src_top1);
+	writel(CLK_SRC_TOP2_VAL, &clk->src_top2);
+	writel(CLK_SRC_TOP7_VAL, &clk->src_top7);
+
+	writel(CLK_DIV_TOP0_VAL, &clk->div_top0);
+	writel(CLK_DIV_TOP1_VAL, &clk->div_top1);
+	writel(CLK_DIV_TOP2_VAL, &clk->div_top2);
+
+	writel(0, &clk->src_top10);
+	writel(0, &clk->src_top11);
+	writel(0, &clk->src_top12);
+
+	writel(CLK_SRC_TOP3_VAL, &clk->src_top3);
+	writel(CLK_SRC_TOP4_VAL, &clk->src_top4);
+	writel(CLK_SRC_TOP5_VAL, &clk->src_top5);
+
+	/* DISP1 BLK CLK SELECTION */
+	writel(CLK_SRC_DISP1_0_VAL, &clk->src_disp10);
+	writel(CLK_DIV_DISP1_0_VAL, &clk->div_disp10);
+
+	/* AUDIO BLK */
+	writel(AUDIO0_SEL_EPLL, &clk->src_mau);
+	writel(DIV_MAU_VAL, &clk->div_mau);
+
+	/* FSYS */
+	writel(CLK_SRC_FSYS0_VAL, &clk->src_fsys);
+	writel(CLK_DIV_FSYS0_VAL, &clk->div_fsys0);
+	writel(CLK_DIV_FSYS1_VAL, &clk->div_fsys1);
+	writel(CLK_DIV_FSYS2_VAL, &clk->div_fsys2);
+
+	writel(CLK_SRC_ISP_VAL, &clk->src_isp);
+	writel(CLK_DIV_ISP0_VAL, &clk->div_isp0);
+	writel(CLK_DIV_ISP1_VAL, &clk->div_isp1);
+
+	writel(CLK_SRC_PERIC0_VAL, &clk->src_peric0);
+	writel(CLK_SRC_PERIC1_VAL, &clk->src_peric1);
+
+	writel(CLK_DIV_PERIC0_VAL, &clk->div_peric0);
+	writel(CLK_DIV_PERIC1_VAL, &clk->div_peric1);
+	writel(CLK_DIV_PERIC2_VAL, &clk->div_peric2);
+	writel(CLK_DIV_PERIC3_VAL, &clk->div_peric3);
+	writel(CLK_DIV_PERIC4_VAL, &clk->div_peric4);
+
+	writel(CLK_DIV_CPERI1_VAL, &clk->div_cperi1);
+
+	writel(CLK_DIV2_RATIO, &clk->clkdiv2_ratio);
+	writel(CLK_DIV4_RATIO, &clk->clkdiv4_ratio);
+	writel(CLK_DIV_G2D, &clk->div_g2d);
+
+	writel(CLK_SRC_TOP6_VAL, &clk->src_top6);
+	writel(CLK_SRC_CDREX_VAL, &clk->src_cdrex);
+	writel(CLK_SRC_KFC_VAL, &clk->src_kfc);
+}
+
+void system_clock_init(void)
+{
+	if (proid_is_exynos5420())
+		exynos5420_system_clock_init();
+	else
+		exynos5250_system_clock_init();
+}
+
 void clock_init_dp_clock(void)
 {
 	struct exynos5_clock *clk =
diff --git a/arch/arm/cpu/armv7/exynos/config.mk b/arch/arm/cpu/armv7/exynos/config.mk
new file mode 100644
index 0000000000..ee0d2dab7b
--- /dev/null
+++ b/arch/arm/cpu/armv7/exynos/config.mk
@@ -0,0 +1,7 @@
+#
+# Copyright (C) Albert ARIBAUD <albert.u.boot@aribaud.net>
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+SPL_OBJCFLAGS += -j .machine_param
diff --git a/arch/arm/cpu/armv7/exynos/dmc_common.c b/arch/arm/cpu/armv7/exynos/dmc_common.c
index 53cfe6edb1..cca925e42c 100644
--- a/arch/arm/cpu/armv7/exynos/dmc_common.c
+++ b/arch/arm/cpu/armv7/exynos/dmc_common.c
@@ -1,5 +1,5 @@
 /*
- * Mem setup common file for different types of DDR present on SMDK5250 boards.
+ * Mem setup common file for different types of DDR present on Exynos boards.
  *
  * Copyright (C) 2012 Samsung Electronics
  *
@@ -15,9 +15,9 @@
 
 #define ZQ_INIT_TIMEOUT	10000
 
-int dmc_config_zq(struct mem_timings *mem,
-		  struct exynos5_phy_control *phy0_ctrl,
-		  struct exynos5_phy_control *phy1_ctrl)
+int dmc_config_zq(struct mem_timings *mem, uint32_t *phy0_con16,
+			uint32_t *phy1_con16, uint32_t *phy0_con17,
+			uint32_t *phy1_con17)
 {
 	unsigned long val = 0;
 	int i;
@@ -31,19 +31,19 @@ int dmc_config_zq(struct mem_timings *mem,
 	val |= mem->zq_mode_dds << PHY_CON16_ZQ_MODE_DDS_SHIFT;
 	val |= mem->zq_mode_term << PHY_CON16_ZQ_MODE_TERM_SHIFT;
 	val |= ZQ_CLK_DIV_EN;
-	writel(val, &phy0_ctrl->phy_con16);
-	writel(val, &phy1_ctrl->phy_con16);
+	writel(val, phy0_con16);
+	writel(val, phy1_con16);
 
 	/* Disable termination */
 	if (mem->zq_mode_noterm)
 		val |= PHY_CON16_ZQ_MODE_NOTERM_MASK;
-	writel(val, &phy0_ctrl->phy_con16);
-	writel(val, &phy1_ctrl->phy_con16);
+	writel(val, phy0_con16);
+	writel(val, phy1_con16);
 
 	/* ZQ_MANUAL_START: Enable */
 	val |= ZQ_MANUAL_STR;
-	writel(val, &phy0_ctrl->phy_con16);
-	writel(val, &phy1_ctrl->phy_con16);
+	writel(val, phy0_con16);
+	writel(val, phy1_con16);
 
 	/* ZQ_MANUAL_START: Disable */
 	val &= ~ZQ_MANUAL_STR;
@@ -53,47 +53,47 @@ int dmc_config_zq(struct mem_timings *mem,
 	 * we are looping for the ZQ_init to complete.
 	 */
 	i = ZQ_INIT_TIMEOUT;
-	while ((readl(&phy0_ctrl->phy_con17) & ZQ_DONE) != ZQ_DONE && i > 0) {
+	while ((readl(phy0_con17) & ZQ_DONE) != ZQ_DONE && i > 0) {
 		sdelay(100);
 		i--;
 	}
 	if (!i)
 		return -1;
-	writel(val, &phy0_ctrl->phy_con16);
+	writel(val, phy0_con16);
 
 	i = ZQ_INIT_TIMEOUT;
-	while ((readl(&phy1_ctrl->phy_con17) & ZQ_DONE) != ZQ_DONE && i > 0) {
+	while ((readl(phy1_con17) & ZQ_DONE) != ZQ_DONE && i > 0) {
 		sdelay(100);
 		i--;
 	}
 	if (!i)
 		return -1;
-	writel(val, &phy1_ctrl->phy_con16);
+	writel(val, phy1_con16);
 
 	return 0;
 }
 
-void update_reset_dll(struct exynos5_dmc *dmc, enum ddr_mode mode)
+void update_reset_dll(uint32_t *phycontrol0, enum ddr_mode mode)
 {
 	unsigned long val;
 
 	if (mode == DDR_MODE_DDR3) {
 		val = MEM_TERM_EN | PHY_TERM_EN | DMC_CTRL_SHGATE;
-		writel(val, &dmc->phycontrol0);
+		writel(val, phycontrol0);
 	}
 
 	/* Update DLL Information: Force DLL Resyncronization */
-	val = readl(&dmc->phycontrol0);
+	val = readl(phycontrol0);
 	val |= FP_RSYNC;
-	writel(val, &dmc->phycontrol0);
+	writel(val, phycontrol0);
 
 	/* Reset Force DLL Resyncronization */
-	val = readl(&dmc->phycontrol0);
+	val = readl(phycontrol0);
 	val &= ~FP_RSYNC;
-	writel(val, &dmc->phycontrol0);
+	writel(val, phycontrol0);
 }
 
-void dmc_config_mrs(struct mem_timings *mem, struct exynos5_dmc *dmc)
+void dmc_config_mrs(struct mem_timings *mem, uint32_t *directcmd)
 {
 	int channel, chip;
 
@@ -107,7 +107,7 @@ void dmc_config_mrs(struct mem_timings *mem, struct exynos5_dmc *dmc)
 			mask |= chip << DIRECT_CMD_CHIP_SHIFT;
 
 			/* Sending NOP command */
-			writel(DIRECT_CMD_NOP | mask, &dmc->directcmd);
+			writel(DIRECT_CMD_NOP | mask, directcmd);
 
 			/*
 			 * TODO(alim.akhtar@samsung.com): Do we need these
@@ -119,14 +119,14 @@ void dmc_config_mrs(struct mem_timings *mem, struct exynos5_dmc *dmc)
 			/* Sending EMRS/MRS commands */
 			for (i = 0; i < MEM_TIMINGS_MSR_COUNT; i++) {
 				writel(mem->direct_cmd_msr[i] | mask,
-				       &dmc->directcmd);
+				       directcmd);
 				sdelay(0x10000);
 			}
 
 			if (mem->send_zq_init) {
 				/* Sending ZQINIT command */
 				writel(DIRECT_CMD_ZQINIT | mask,
-				       &dmc->directcmd);
+				       directcmd);
 
 				sdelay(10000);
 			}
@@ -134,7 +134,7 @@ void dmc_config_mrs(struct mem_timings *mem, struct exynos5_dmc *dmc)
 	}
 }
 
-void dmc_config_prech(struct mem_timings *mem, struct exynos5_dmc *dmc)
+void dmc_config_prech(struct mem_timings *mem, uint32_t *directcmd)
 {
 	int channel, chip;
 
@@ -146,20 +146,12 @@ void dmc_config_prech(struct mem_timings *mem, struct exynos5_dmc *dmc)
 			mask |= chip << DIRECT_CMD_CHIP_SHIFT;
 
 			/* PALL (all banks precharge) CMD */
-			writel(DIRECT_CMD_PALL | mask, &dmc->directcmd);
+			writel(DIRECT_CMD_PALL | mask, directcmd);
 			sdelay(0x10000);
 		}
 	}
 }
 
-void dmc_config_memory(struct mem_timings *mem, struct exynos5_dmc *dmc)
-{
-	writel(mem->memconfig, &dmc->memconfig0);
-	writel(mem->memconfig, &dmc->memconfig1);
-	writel(DMC_MEMBASECONFIG0_VAL, &dmc->membaseconfig0);
-	writel(DMC_MEMBASECONFIG1_VAL, &dmc->membaseconfig1);
-}
-
 void mem_ctrl_init(int reset)
 {
 	struct spl_machine_param *param = spl_get_machine_params();
diff --git a/arch/arm/cpu/armv7/exynos/dmc_init_ddr3.c b/arch/arm/cpu/armv7/exynos/dmc_init_ddr3.c
index 5f5914ede8..487e6f423f 100644
--- a/arch/arm/cpu/armv7/exynos/dmc_init_ddr3.c
+++ b/arch/arm/cpu/armv7/exynos/dmc_init_ddr3.c
@@ -1,5 +1,5 @@
 /*
- * DDR3 mem setup file for SMDK5250 board based on EXYNOS5
+ * DDR3 mem setup file for board based on EXYNOS5
  *
  * Copyright (C) 2012 Samsung Electronics
  *
@@ -11,12 +11,14 @@
 #include <asm/arch/clock.h>
 #include <asm/arch/cpu.h>
 #include <asm/arch/dmc.h>
+#include <asm/arch/power.h>
 #include "common_setup.h"
 #include "exynos5_setup.h"
 #include "clock_init.h"
 
-#define RDLVL_COMPLETE_TIMEOUT	10000
+#define TIMEOUT	10000
 
+#ifdef CONFIG_EXYNOS5250
 static void reset_phy_ctrl(void)
 {
 	struct exynos5_clock *clk =
@@ -57,7 +59,8 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned long mem_iv_size,
 	writel(val, &phy1_ctrl->phy_con42);
 
 	/* ZQ Calibration */
-	if (dmc_config_zq(mem, phy0_ctrl, phy1_ctrl))
+	if (dmc_config_zq(mem, &phy0_ctrl->phy_con16, &phy1_ctrl->phy_con16,
+			  &phy0_ctrl->phy_con17, &phy1_ctrl->phy_con17))
 		return SETUP_ERR_ZQ_CALIBRATION_FAILURE;
 
 	/* DQ Signal */
@@ -68,7 +71,7 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned long mem_iv_size,
 		| (mem->dfi_init_start << CONCONTROL_DFI_INIT_START_SHIFT),
 		&dmc->concontrol);
 
-	update_reset_dll(dmc, DDR_MODE_DDR3);
+	update_reset_dll(&dmc->phycontrol0, DDR_MODE_DDR3);
 
 	/* DQS Signal */
 	writel(mem->phy0_dqs, &phy0_ctrl->phy_con4);
@@ -93,7 +96,7 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned long mem_iv_size,
 	writel(val | (mem->ctrl_start << PHY_CON12_CTRL_START_SHIFT),
 	       &phy1_ctrl->phy_con12);
 
-	update_reset_dll(dmc, DDR_MODE_DDR3);
+	update_reset_dll(&dmc->phycontrol0, DDR_MODE_DDR3);
 
 	writel(mem->concontrol | (mem->rd_fetch << CONCONTROL_RD_FETCH_SHIFT),
 	       &dmc->concontrol);
@@ -124,10 +127,10 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned long mem_iv_size,
 	writel(mem->timing_power, &dmc->timingpower);
 
 	/* Send PALL command */
-	dmc_config_prech(mem, dmc);
+	dmc_config_prech(mem, &dmc->directcmd);
 
 	/* Send NOP, MRS and ZQINIT commands */
-	dmc_config_mrs(mem, dmc);
+	dmc_config_mrs(mem, &dmc->directcmd);
 
 	if (mem->gate_leveling_enable) {
 		val = PHY_CON0_RESET_VAL;
@@ -174,7 +177,7 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned long mem_iv_size,
 		writel(val, &phy1_ctrl->phy_con1);
 
 		writel(CTRL_RDLVL_GATE_ENABLE, &dmc->rdlvl_config);
-		i = RDLVL_COMPLETE_TIMEOUT;
+		i = TIMEOUT;
 		while ((readl(&dmc->phystatus) &
 			(RDLVL_COMPLETE_CHO | RDLVL_COMPLETE_CH1)) !=
 			(RDLVL_COMPLETE_CHO | RDLVL_COMPLETE_CH1) && i > 0) {
@@ -202,11 +205,11 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned long mem_iv_size,
 		writel(val, &phy0_ctrl->phy_con12);
 		writel(val, &phy1_ctrl->phy_con12);
 
-		update_reset_dll(dmc, DDR_MODE_DDR3);
+		update_reset_dll(&dmc->phycontrol0, DDR_MODE_DDR3);
 	}
 
 	/* Send PALL command */
-	dmc_config_prech(mem, dmc);
+	dmc_config_prech(mem, &dmc->directcmd);
 
 	writel(mem->memcontrol, &dmc->memcontrol);
 
@@ -215,3 +218,419 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned long mem_iv_size,
 		| (mem->aref_en << CONCONTROL_AREF_EN_SHIFT), &dmc->concontrol);
 	return 0;
 }
+#endif
+
+#ifdef CONFIG_EXYNOS5420
+int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned long mem_iv_size,
+		       int reset)
+{
+	struct exynos5420_clock *clk =
+		(struct exynos5420_clock *)samsung_get_base_clock();
+	struct exynos5420_power *power =
+		(struct exynos5420_power *)samsung_get_base_power();
+	struct exynos5420_phy_control *phy0_ctrl, *phy1_ctrl;
+	struct exynos5420_dmc *drex0, *drex1;
+	struct exynos5420_tzasc *tzasc0, *tzasc1;
+	uint32_t val, n_lock_r, n_lock_w_phy0, n_lock_w_phy1;
+	int chip;
+	int i;
+
+	phy0_ctrl = (struct exynos5420_phy_control *)samsung_get_base_dmc_phy();
+	phy1_ctrl = (struct exynos5420_phy_control *)(samsung_get_base_dmc_phy()
+							+ DMC_OFFSET);
+	drex0 = (struct exynos5420_dmc *)samsung_get_base_dmc_ctrl();
+	drex1 = (struct exynos5420_dmc *)(samsung_get_base_dmc_ctrl()
+							+ DMC_OFFSET);
+	tzasc0 = (struct exynos5420_tzasc *)samsung_get_base_dmc_tzasc();
+	tzasc1 = (struct exynos5420_tzasc *)(samsung_get_base_dmc_tzasc()
+							+ DMC_OFFSET);
+
+	/* Enable PAUSE for DREX */
+	setbits_le32(&clk->pause, ENABLE_BIT);
+
+	/* Enable BYPASS mode */
+	setbits_le32(&clk->bpll_con1, BYPASS_EN);
+
+	writel(MUX_BPLL_SEL_FOUTBPLL, &clk->src_cdrex);
+	do {
+		val = readl(&clk->mux_stat_cdrex);
+		val &= BPLL_SEL_MASK;
+	} while (val != FOUTBPLL);
+
+	clrbits_le32(&clk->bpll_con1, BYPASS_EN);
+
+	/* Specify the DDR memory type as DDR3 */
+	val = readl(&phy0_ctrl->phy_con0);
+	val &= ~(PHY_CON0_CTRL_DDR_MODE_MASK << PHY_CON0_CTRL_DDR_MODE_SHIFT);
+	val |= (DDR_MODE_DDR3 << PHY_CON0_CTRL_DDR_MODE_SHIFT);
+	writel(val, &phy0_ctrl->phy_con0);
+
+	val = readl(&phy1_ctrl->phy_con0);
+	val &= ~(PHY_CON0_CTRL_DDR_MODE_MASK << PHY_CON0_CTRL_DDR_MODE_SHIFT);
+	val |= (DDR_MODE_DDR3 << PHY_CON0_CTRL_DDR_MODE_SHIFT);
+	writel(val, &phy1_ctrl->phy_con0);
+
+	/* Set Read Latency and Burst Length for PHY0 and PHY1 */
+	val = (mem->ctrl_bstlen << PHY_CON42_CTRL_BSTLEN_SHIFT) |
+		(mem->ctrl_rdlat << PHY_CON42_CTRL_RDLAT_SHIFT);
+	writel(val, &phy0_ctrl->phy_con42);
+	writel(val, &phy1_ctrl->phy_con42);
+
+	val = readl(&phy0_ctrl->phy_con26);
+	val &= ~(T_WRDATA_EN_MASK << T_WRDATA_EN_OFFSET);
+	val |= (T_WRDATA_EN_DDR3 << T_WRDATA_EN_OFFSET);
+	writel(val, &phy0_ctrl->phy_con26);
+
+	val = readl(&phy1_ctrl->phy_con26);
+	val &= ~(T_WRDATA_EN_MASK << T_WRDATA_EN_OFFSET);
+	val |= (T_WRDATA_EN_DDR3 << T_WRDATA_EN_OFFSET);
+	writel(val, &phy1_ctrl->phy_con26);
+
+	/*
+	 * Set Driver strength for CK, CKE, CS & CA to 0x7
+	 * Set Driver strength for Data Slice 0~3 to 0x7
+	 */
+	val = (0x7 << CA_CK_DRVR_DS_OFFSET) | (0x7 << CA_CKE_DRVR_DS_OFFSET) |
+		(0x7 << CA_CS_DRVR_DS_OFFSET) | (0x7 << CA_ADR_DRVR_DS_OFFSET);
+	val |= (0x7 << DA_3_DS_OFFSET) | (0x7 << DA_2_DS_OFFSET) |
+		(0x7 << DA_1_DS_OFFSET) | (0x7 << DA_0_DS_OFFSET);
+	writel(val, &phy0_ctrl->phy_con39);
+	writel(val, &phy1_ctrl->phy_con39);
+
+	/* ZQ Calibration */
+	if (dmc_config_zq(mem, &phy0_ctrl->phy_con16, &phy1_ctrl->phy_con16,
+			  &phy0_ctrl->phy_con17, &phy1_ctrl->phy_con17))
+		return SETUP_ERR_ZQ_CALIBRATION_FAILURE;
+
+	clrbits_le32(&phy0_ctrl->phy_con16, ZQ_CLK_DIV_EN);
+	clrbits_le32(&phy1_ctrl->phy_con16, ZQ_CLK_DIV_EN);
+
+	/* DQ Signal */
+	val = readl(&phy0_ctrl->phy_con14);
+	val |= mem->phy0_pulld_dqs;
+	writel(val, &phy0_ctrl->phy_con14);
+	val = readl(&phy1_ctrl->phy_con14);
+	val |= mem->phy1_pulld_dqs;
+	writel(val, &phy1_ctrl->phy_con14);
+
+	val = MEM_TERM_EN | PHY_TERM_EN;
+	writel(val, &drex0->phycontrol0);
+	writel(val, &drex1->phycontrol0);
+
+	writel(mem->concontrol |
+		(mem->dfi_init_start << CONCONTROL_DFI_INIT_START_SHIFT) |
+		(mem->rd_fetch << CONCONTROL_RD_FETCH_SHIFT),
+		&drex0->concontrol);
+	writel(mem->concontrol |
+		(mem->dfi_init_start << CONCONTROL_DFI_INIT_START_SHIFT) |
+		(mem->rd_fetch << CONCONTROL_RD_FETCH_SHIFT),
+		&drex1->concontrol);
+
+	do {
+		val = readl(&drex0->phystatus);
+	} while ((val & DFI_INIT_COMPLETE) != DFI_INIT_COMPLETE);
+	do {
+		val = readl(&drex1->phystatus);
+	} while ((val & DFI_INIT_COMPLETE) != DFI_INIT_COMPLETE);
+
+	clrbits_le32(&drex0->concontrol, DFI_INIT_START);
+	clrbits_le32(&drex1->concontrol, DFI_INIT_START);
+
+	update_reset_dll(&drex0->phycontrol0, DDR_MODE_DDR3);
+	update_reset_dll(&drex1->phycontrol0, DDR_MODE_DDR3);
+
+	/*
+	 * Set Base Address:
+	 * 0x2000_0000 ~ 0x5FFF_FFFF
+	 * 0x6000_0000 ~ 0x9FFF_FFFF
+	 */
+	/* MEMBASECONFIG0 */
+	val = DMC_MEMBASECONFIGX_CHIP_BASE(DMC_CHIP_BASE_0) |
+		DMC_MEMBASECONFIGX_CHIP_MASK(DMC_CHIP_MASK);
+	writel(val, &tzasc0->membaseconfig0);
+	writel(val, &tzasc1->membaseconfig0);
+
+	/* MEMBASECONFIG1 */
+	val = DMC_MEMBASECONFIGX_CHIP_BASE(DMC_CHIP_BASE_1) |
+		DMC_MEMBASECONFIGX_CHIP_MASK(DMC_CHIP_MASK);
+	writel(val, &tzasc0->membaseconfig1);
+	writel(val, &tzasc1->membaseconfig1);
+
+	/*
+	 * Memory Channel Inteleaving Size
+	 * Ares Channel interleaving = 128 bytes
+	 */
+	/* MEMCONFIG0/1 */
+	writel(mem->memconfig, &tzasc0->memconfig0);
+	writel(mem->memconfig, &tzasc1->memconfig0);
+	writel(mem->memconfig, &tzasc0->memconfig1);
+	writel(mem->memconfig, &tzasc1->memconfig1);
+
+	/* Precharge Configuration */
+	writel(mem->prechconfig_tp_cnt << PRECHCONFIG_TP_CNT_SHIFT,
+	       &drex0->prechconfig0);
+	writel(mem->prechconfig_tp_cnt << PRECHCONFIG_TP_CNT_SHIFT,
+	       &drex1->prechconfig0);
+
+	/*
+	 * TimingRow, TimingData, TimingPower and Timingaref
+	 * values as per Memory AC parameters
+	 */
+	writel(mem->timing_ref, &drex0->timingref);
+	writel(mem->timing_ref, &drex1->timingref);
+	writel(mem->timing_row, &drex0->timingrow0);
+	writel(mem->timing_row, &drex1->timingrow0);
+	writel(mem->timing_data, &drex0->timingdata0);
+	writel(mem->timing_data, &drex1->timingdata0);
+	writel(mem->timing_power, &drex0->timingpower0);
+	writel(mem->timing_power, &drex1->timingpower0);
+
+	if (reset) {
+		/*
+		 * Send NOP, MRS and ZQINIT commands
+		 * Sending MRS command will reset the DRAM. We should not be
+		 * reseting the DRAM after resume, this will lead to memory
+		 * corruption as DRAM content is lost after DRAM reset
+		 */
+		dmc_config_mrs(mem, &drex0->directcmd);
+		dmc_config_mrs(mem, &drex1->directcmd);
+	} else {
+		/*
+		 * During Suspend-Resume & S/W-Reset, as soon as PMU releases
+		 * pad retention, CKE goes high. This causes memory contents
+		 * not to be retained during DRAM initialization. Therfore,
+		 * there is a new control register(0x100431e8[28]) which lets us
+		 * release pad retention and retain the memory content until the
+		 * initialization is complete.
+		 */
+		writel(PAD_RETENTION_DRAM_COREBLK_VAL,
+		       &power->pad_retention_dram_coreblk_option);
+		do {
+			val = readl(&power->pad_retention_dram_status);
+		} while (val != 0x1);
+
+		/*
+		 * CKE PAD retention disables DRAM self-refresh mode.
+		 * Send auto refresh command for DRAM refresh.
+		 */
+		for (i = 0; i < 128; i++) {
+			for (chip = 0; chip < mem->chips_to_configure; chip++) {
+				writel(DIRECT_CMD_REFA |
+				       (chip << DIRECT_CMD_CHIP_SHIFT),
+				       &drex0->directcmd);
+				writel(DIRECT_CMD_REFA |
+				       (chip << DIRECT_CMD_CHIP_SHIFT),
+				       &drex1->directcmd);
+			}
+		}
+	}
+
+	if (mem->gate_leveling_enable) {
+		writel(PHY_CON0_RESET_VAL, &phy0_ctrl->phy_con0);
+		writel(PHY_CON0_RESET_VAL, &phy1_ctrl->phy_con0);
+
+		setbits_le32(&phy0_ctrl->phy_con0, P0_CMD_EN);
+		setbits_le32(&phy1_ctrl->phy_con0, P0_CMD_EN);
+
+		val = PHY_CON2_RESET_VAL;
+		val |= INIT_DESKEW_EN;
+		writel(val, &phy0_ctrl->phy_con2);
+		writel(val, &phy1_ctrl->phy_con2);
+
+		val =  readl(&phy0_ctrl->phy_con1);
+		val |= (RDLVL_PASS_ADJ_VAL << RDLVL_PASS_ADJ_OFFSET);
+		writel(val, &phy0_ctrl->phy_con1);
+
+		val =  readl(&phy1_ctrl->phy_con1);
+		val |= (RDLVL_PASS_ADJ_VAL << RDLVL_PASS_ADJ_OFFSET);
+		writel(val, &phy1_ctrl->phy_con1);
+
+		n_lock_r = readl(&phy0_ctrl->phy_con13);
+		n_lock_w_phy0 = (n_lock_r & CTRL_LOCK_COARSE_MASK) >> 2;
+		n_lock_r = readl(&phy0_ctrl->phy_con12);
+		n_lock_r &= ~CTRL_DLL_ON;
+		n_lock_r |= n_lock_w_phy0;
+		writel(n_lock_r, &phy0_ctrl->phy_con12);
+
+		n_lock_r = readl(&phy1_ctrl->phy_con13);
+		n_lock_w_phy1 = (n_lock_r & CTRL_LOCK_COARSE_MASK) >> 2;
+		n_lock_r = readl(&phy1_ctrl->phy_con12);
+		n_lock_r &= ~CTRL_DLL_ON;
+		n_lock_r |= n_lock_w_phy1;
+		writel(n_lock_r, &phy1_ctrl->phy_con12);
+
+		val = (0x3 << DIRECT_CMD_BANK_SHIFT) | 0x4;
+		for (chip = 0; chip < mem->chips_to_configure; chip++) {
+			writel(val | (chip << DIRECT_CMD_CHIP_SHIFT),
+			       &drex0->directcmd);
+			writel(val | (chip << DIRECT_CMD_CHIP_SHIFT),
+			       &drex1->directcmd);
+		}
+
+		setbits_le32(&phy0_ctrl->phy_con2, RDLVL_GATE_EN);
+		setbits_le32(&phy1_ctrl->phy_con2, RDLVL_GATE_EN);
+
+		setbits_le32(&phy0_ctrl->phy_con0, CTRL_SHGATE);
+		setbits_le32(&phy1_ctrl->phy_con0, CTRL_SHGATE);
+
+		val = readl(&phy0_ctrl->phy_con1);
+		val &= ~(CTRL_GATEDURADJ_MASK);
+		writel(val, &phy0_ctrl->phy_con1);
+
+		val = readl(&phy1_ctrl->phy_con1);
+		val &= ~(CTRL_GATEDURADJ_MASK);
+		writel(val, &phy1_ctrl->phy_con1);
+
+		writel(CTRL_RDLVL_GATE_ENABLE, &drex0->rdlvl_config);
+		i = TIMEOUT;
+		while (((readl(&drex0->phystatus) & RDLVL_COMPLETE_CHO) !=
+			RDLVL_COMPLETE_CHO) && (i > 0)) {
+			/*
+			 * TODO(waihong): Comment on how long this take to
+			 * timeout
+			 */
+			sdelay(100);
+			i--;
+		}
+		if (!i)
+			return SETUP_ERR_RDLV_COMPLETE_TIMEOUT;
+		writel(CTRL_RDLVL_GATE_DISABLE, &drex0->rdlvl_config);
+
+		writel(CTRL_RDLVL_GATE_ENABLE, &drex1->rdlvl_config);
+		i = TIMEOUT;
+		while (((readl(&drex1->phystatus) & RDLVL_COMPLETE_CHO) !=
+			RDLVL_COMPLETE_CHO) && (i > 0)) {
+			/*
+			 * TODO(waihong): Comment on how long this take to
+			 * timeout
+			 */
+			sdelay(100);
+			i--;
+		}
+		if (!i)
+			return SETUP_ERR_RDLV_COMPLETE_TIMEOUT;
+		writel(CTRL_RDLVL_GATE_DISABLE, &drex1->rdlvl_config);
+
+		writel(0, &phy0_ctrl->phy_con14);
+		writel(0, &phy1_ctrl->phy_con14);
+
+		val = (0x3 << DIRECT_CMD_BANK_SHIFT);
+		for (chip = 0; chip < mem->chips_to_configure; chip++) {
+			writel(val | (chip << DIRECT_CMD_CHIP_SHIFT),
+			       &drex0->directcmd);
+			writel(val | (chip << DIRECT_CMD_CHIP_SHIFT),
+			       &drex1->directcmd);
+		}
+
+		if (mem->read_leveling_enable) {
+			/* Set Read DQ Calibration */
+			val = (0x3 << DIRECT_CMD_BANK_SHIFT) | 0x4;
+			for (chip = 0; chip < mem->chips_to_configure; chip++) {
+				writel(val | (chip << DIRECT_CMD_CHIP_SHIFT),
+				       &drex0->directcmd);
+				writel(val | (chip << DIRECT_CMD_CHIP_SHIFT),
+				       &drex1->directcmd);
+			}
+
+			val = readl(&phy0_ctrl->phy_con1);
+			val |= READ_LEVELLING_DDR3;
+			writel(val, &phy0_ctrl->phy_con1);
+			val = readl(&phy1_ctrl->phy_con1);
+			val |= READ_LEVELLING_DDR3;
+			writel(val, &phy1_ctrl->phy_con1);
+
+			val = readl(&phy0_ctrl->phy_con2);
+			val |= (RDLVL_EN | RDLVL_INCR_ADJ);
+			writel(val, &phy0_ctrl->phy_con2);
+			val = readl(&phy1_ctrl->phy_con2);
+			val |= (RDLVL_EN | RDLVL_INCR_ADJ);
+			writel(val, &phy1_ctrl->phy_con2);
+
+			setbits_le32(&drex0->rdlvl_config,
+				     CTRL_RDLVL_DATA_ENABLE);
+			i = TIMEOUT;
+			while (((readl(&drex0->phystatus) & RDLVL_COMPLETE_CHO)
+				 != RDLVL_COMPLETE_CHO) && (i > 0)) {
+				/*
+				 * TODO(waihong): Comment on how long this take
+				 * to timeout
+				 */
+				sdelay(100);
+				i--;
+			}
+			if (!i)
+				return SETUP_ERR_RDLV_COMPLETE_TIMEOUT;
+
+			clrbits_le32(&drex0->rdlvl_config,
+				     CTRL_RDLVL_DATA_ENABLE);
+			setbits_le32(&drex1->rdlvl_config,
+				     CTRL_RDLVL_DATA_ENABLE);
+			i = TIMEOUT;
+			while (((readl(&drex1->phystatus) & RDLVL_COMPLETE_CHO)
+				 != RDLVL_COMPLETE_CHO) && (i > 0)) {
+				/*
+				 * TODO(waihong): Comment on how long this take
+				 * to timeout
+				 */
+				sdelay(100);
+				i--;
+			}
+			if (!i)
+				return SETUP_ERR_RDLV_COMPLETE_TIMEOUT;
+
+			clrbits_le32(&drex1->rdlvl_config,
+				     CTRL_RDLVL_DATA_ENABLE);
+
+			val = (0x3 << DIRECT_CMD_BANK_SHIFT);
+			for (chip = 0; chip < mem->chips_to_configure; chip++) {
+				writel(val | (chip << DIRECT_CMD_CHIP_SHIFT),
+				       &drex0->directcmd);
+				writel(val | (chip << DIRECT_CMD_CHIP_SHIFT),
+				       &drex1->directcmd);
+			}
+
+			update_reset_dll(&drex0->phycontrol0, DDR_MODE_DDR3);
+			update_reset_dll(&drex1->phycontrol0, DDR_MODE_DDR3);
+		}
+
+		/* Common Settings for Leveling */
+		val = PHY_CON12_RESET_VAL;
+		writel((val + n_lock_w_phy0), &phy0_ctrl->phy_con12);
+		writel((val + n_lock_w_phy1), &phy1_ctrl->phy_con12);
+
+		setbits_le32(&phy0_ctrl->phy_con2, DLL_DESKEW_EN);
+		setbits_le32(&phy1_ctrl->phy_con2, DLL_DESKEW_EN);
+	}
+
+	/* Send PALL command */
+	dmc_config_prech(mem, &drex0->directcmd);
+	dmc_config_prech(mem, &drex1->directcmd);
+
+	writel(mem->memcontrol, &drex0->memcontrol);
+	writel(mem->memcontrol, &drex1->memcontrol);
+
+	/*
+	 * Set DMC Concontrol: Enable auto-refresh counter, provide
+	 * read data fetch cycles and enable DREX auto set powerdown
+	 * for input buffer of I/O in none read memory state.
+	 */
+	writel(mem->concontrol | (mem->aref_en << CONCONTROL_AREF_EN_SHIFT) |
+		(mem->rd_fetch << CONCONTROL_RD_FETCH_SHIFT)|
+		DMC_CONCONTROL_IO_PD_CON(0x2),
+		&drex0->concontrol);
+	writel(mem->concontrol | (mem->aref_en << CONCONTROL_AREF_EN_SHIFT) |
+		(mem->rd_fetch << CONCONTROL_RD_FETCH_SHIFT)|
+		DMC_CONCONTROL_IO_PD_CON(0x2),
+		&drex1->concontrol);
+
+	/*
+	 * Enable Clock Gating Control for DMC
+	 * this saves around 25 mw dmc power as compared to the power
+	 * consumption without these bits enabled
+	 */
+	setbits_le32(&drex0->cgcontrol, DMC_INTERNAL_CG);
+	setbits_le32(&drex1->cgcontrol, DMC_INTERNAL_CG);
+
+	return 0;
+}
+#endif
diff --git a/arch/arm/cpu/armv7/exynos/exynos5_setup.h b/arch/arm/cpu/armv7/exynos/exynos5_setup.h
index 696b386759..53b0ace6e3 100644
--- a/arch/arm/cpu/armv7/exynos/exynos5_setup.h
+++ b/arch/arm/cpu/armv7/exynos/exynos5_setup.h
@@ -12,42 +12,16 @@
 #include <config.h>
 #include <asm/arch/dmc.h>
 
-/* APLL_CON1	*/
-#define APLL_CON1_VAL	(0x00203800)
-
-/* MPLL_CON1	*/
-#define MPLL_CON1_VAL   (0x00203800)
-
-/* CPLL_CON1	*/
-#define CPLL_CON1_VAL	(0x00203800)
-
-/* GPLL_CON1	*/
-#define GPLL_CON1_VAL	(0x00203800)
-
-/* EPLL_CON1, CON2	*/
-#define EPLL_CON1_VAL	0x00000000
-#define EPLL_CON2_VAL	0x00000080
-
-/* VPLL_CON1, CON2	*/
-#define VPLL_CON1_VAL	0x00000000
-#define VPLL_CON2_VAL	0x00000080
+#define NOT_AVAILABLE		0
+#define DATA_MASK		0xFFFFF
 
-/* BPLL_CON1	*/
-#define BPLL_CON1_VAL	0x00203800
+#define ENABLE_BIT		0x1
+#define DISABLE_BIT		0x0
+#define CA_SWAP_EN		(1 << 0)
 
 /* Set PLL */
 #define set_pll(mdiv, pdiv, sdiv)	(1<<31 | mdiv<<16 | pdiv<<8 | sdiv)
 
-/* CLK_SRC_CPU	*/
-/* 0 = MOUTAPLL,  1 = SCLKMPLL	*/
-#define MUX_HPM_SEL             0
-#define MUX_CPU_SEL             0
-#define MUX_APLL_SEL            1
-
-#define CLK_SRC_CPU_VAL		((MUX_HPM_SEL << 20)    \
-				| (MUX_CPU_SEL << 16)  \
-				| (MUX_APLL_SEL))
-
 /* MEMCONTROL register bit fields */
 #define DMC_MEMCONTROL_CLK_STOP_DISABLE	(0 << 0)
 #define DMC_MEMCONTROL_DPWRDN_DISABLE	(0 << 1)
@@ -78,6 +52,7 @@
 
 /* MEMCONFIG0 register bit fields */
 #define DMC_MEMCONFIGX_CHIP_MAP_INTERLEAVED     (1 << 12)
+#define DMC_MEMCONFIG_CHIP_MAP_SPLIT		(2 << 12)
 #define DMC_MEMCONFIGX_CHIP_COL_10              (3 << 8)
 #define DMC_MEMCONFIGX_CHIP_ROW_14              (2 << 4)
 #define DMC_MEMCONFIGX_CHIP_ROW_15              (3 << 4)
@@ -90,6 +65,17 @@
 	DMC_MEMBASECONFIGX_CHIP_MASK(0x780)     \
 )
 
+/*
+ * As we use channel interleaving, therefore value of the base address
+ * register must be set as half of the bus base address
+ * RAM start addess is 0x2000_0000 which means chip_base is 0x20, so
+ * we need to set half 0x10 to the membaseconfigx registers
+ * see exynos5420 UM section 17.17.3.21 for more.
+ */
+#define DMC_CHIP_BASE_0 0x10
+#define DMC_CHIP_BASE_1 0x50
+#define DMC_CHIP_MASK	0x7C0
+
 #define DMC_MEMBASECONFIG0_VAL  DMC_MEMBASECONFIG_VAL(0x40)
 #define DMC_MEMBASECONFIG1_VAL  DMC_MEMBASECONFIG_VAL(0x80)
 
@@ -113,29 +99,24 @@
 
 /* COJCONTROL register bit fields */
 #define DMC_CONCONTROL_IO_PD_CON_DISABLE	(0 << 3)
+#define DMC_CONCONTROL_IO_PD_CON_ENABLE		(1 << 3)
 #define DMC_CONCONTROL_AREF_EN_DISABLE		(0 << 5)
+#define DMC_CONCONTROL_AREF_EN_ENABLE		(1 << 5)
 #define DMC_CONCONTROL_EMPTY_DISABLE		(0 << 8)
 #define DMC_CONCONTROL_EMPTY_ENABLE		(1 << 8)
 #define DMC_CONCONTROL_RD_FETCH_DISABLE		(0x0 << 12)
 #define DMC_CONCONTROL_TIMEOUT_LEVEL0		(0xFFF << 16)
 #define DMC_CONCONTROL_DFI_INIT_START_DISABLE	(0 << 28)
 
-/* CLK_DIV_CPU0_VAL */
-#define CLK_DIV_CPU0_VAL	((ARM2_RATIO << 28)             \
-				| (APLL_RATIO << 24)            \
-				| (PCLK_DBG_RATIO << 20)        \
-				| (ATB_RATIO << 16)             \
-				| (PERIPH_RATIO << 12)          \
-				| (ACP_RATIO << 8)              \
-				| (CPUD_RATIO << 4)             \
-				| (ARM_RATIO))
+#define DMC_CONCONTROL_VAL	0x1FFF2101
 
+#define DREX_CONCONTROL_VAL	DMC_CONCONTROL_VAL			\
+				| DMC_CONCONTROL_AREF_EN_ENABLE		\
+				| DMC_CONCONTROL_IO_PD_CON_ENABLE
 
-/* CLK_FSYS */
-#define CLK_SRC_FSYS0_VAL              0x66666
-#define CLK_DIV_FSYS0_VAL	       0x0BB00000
+#define DMC_CONCONTROL_IO_PD_CON(x)		(x << 6)
 
-/* CLK_DIV_CPU1	*/
+/* CLK_DIV_CPU1 */
 #define HPM_RATIO               0x2
 #define COPY_RATIO              0x0
 
@@ -164,10 +145,367 @@
 /* CLK_DIV_SYSLFT */
 #define CLK_DIV_SYSLFT_VAL      0x00000311
 
+#define MUX_APLL_SEL_MASK	(1 << 0)
+#define MUX_MPLL_SEL_MASK	(1 << 8)
+#define MPLL_SEL_MOUT_MPLLFOUT	(2 << 8)
+#define MUX_CPLL_SEL_MASK	(1 << 8)
+#define MUX_EPLL_SEL_MASK	(1 << 12)
+#define MUX_VPLL_SEL_MASK	(1 << 16)
+#define MUX_GPLL_SEL_MASK	(1 << 28)
+#define MUX_BPLL_SEL_MASK	(1 << 0)
+#define MUX_HPM_SEL_MASK	(1 << 20)
+#define HPM_SEL_SCLK_MPLL	(1 << 21)
+#define PLL_LOCKED		(1 << 29)
+#define APLL_CON0_LOCKED	(1 << 29)
+#define MPLL_CON0_LOCKED	(1 << 29)
+#define BPLL_CON0_LOCKED	(1 << 29)
+#define CPLL_CON0_LOCKED	(1 << 29)
+#define EPLL_CON0_LOCKED	(1 << 29)
+#define GPLL_CON0_LOCKED	(1 << 29)
+#define VPLL_CON0_LOCKED	(1 << 29)
+#define CLK_REG_DISABLE		0x0
+#define TOP2_VAL		0x0110000
+
+/* SCLK_SRC_ISP - set SPI0/1 to 6 = SCLK_MPLL_USER */
+#define SPI0_ISP_SEL		6
+#define SPI1_ISP_SEL		6
+#define SCLK_SRC_ISP_VAL	(SPI1_ISP_SEL << 4) \
+				| (SPI0_ISP_SEL << 0)
+
+/* SCLK_DIV_ISP - set SPI0/1 to 0xf = divide by 16 */
+#define SPI0_ISP_RATIO		0xf
+#define SPI1_ISP_RATIO		0xf
+#define SCLK_DIV_ISP_VAL	(SPI1_ISP_RATIO << 12) \
+				| (SPI0_ISP_RATIO << 0)
+
+/* CLK_DIV_FSYS2 */
+#define MMC2_RATIO_MASK		0xf
+#define MMC2_RATIO_VAL		0x3
+#define MMC2_RATIO_OFFSET	0
+
+#define MMC2_PRE_RATIO_MASK	0xff
+#define MMC2_PRE_RATIO_VAL	0x9
+#define MMC2_PRE_RATIO_OFFSET	8
+
+#define MMC3_RATIO_MASK		0xf
+#define MMC3_RATIO_VAL		0x1
+#define MMC3_RATIO_OFFSET	16
+
+#define MMC3_PRE_RATIO_MASK	0xff
+#define MMC3_PRE_RATIO_VAL	0x0
+#define MMC3_PRE_RATIO_OFFSET	24
+
+/* CLK_SRC_LEX */
+#define CLK_SRC_LEX_VAL         0x0
+
+/* CLK_DIV_LEX */
+#define CLK_DIV_LEX_VAL         0x10
+
+/* CLK_DIV_R0X */
+#define CLK_DIV_R0X_VAL         0x10
+
+/* CLK_DIV_L0X */
+#define CLK_DIV_R1X_VAL         0x10
+
+/* CLK_DIV_ISP2 */
+#define CLK_DIV_ISP2_VAL        0x1
+
+/* CLK_SRC_KFC */
+#define SRC_KFC_HPM_SEL		(1 << 15)
+
+/* CLK_SRC_KFC */
+#define CLK_SRC_KFC_VAL		0x00008001
+
+/* CLK_DIV_KFC */
+#define CLK_DIV_KFC_VAL		0x03300110
+
+/* CLK_DIV2_RATIO */
+#define CLK_DIV2_RATIO		0x10111150
+
+/* CLK_DIV4_RATIO */
+#define CLK_DIV4_RATIO		0x00000003
+
+/* CLK_DIV_G2D */
+#define CLK_DIV_G2D		0x00000010
+
+/*
+ * DIV_DISP1_0
+ * For DP, divisor should be 2
+ */
+#define CLK_DIV_DISP1_0_FIMD1	(2 << 0)
+
+/* CLK_GATE_IP_DISP1 */
+#define CLK_GATE_DP1_ALLOW	(1 << 4)
+
+/* AUDIO CLK SEL */
+#define AUDIO0_SEL_EPLL		(0x6 << 28)
+#define AUDIO0_RATIO		0x5
+#define PCM0_RATIO		0x3
+#define DIV_MAU_VAL		(PCM0_RATIO << 24 | AUDIO0_RATIO << 20)
+
+/* CLK_SRC_CDREX */
+#define MUX_MCLK_CDR_MSPLL	(1 << 4)
+#define MUX_BPLL_SEL_FOUTBPLL   (1 << 0)
+#define BPLL_SEL_MASK   0x7
+#define FOUTBPLL        2
+
+#define DDR3PHY_CTRL_PHY_RESET	(1 << 0)
+#define DDR3PHY_CTRL_PHY_RESET_OFF	(0 << 0)
+
+#define PHY_CON0_RESET_VAL	0x17020a40
+#define P0_CMD_EN		(1 << 14)
+#define BYTE_RDLVL_EN		(1 << 13)
+#define CTRL_SHGATE		(1 << 8)
+
+#define PHY_CON1_RESET_VAL	0x09210100
+#define RDLVL_PASS_ADJ_VAL	0x6
+#define RDLVL_PASS_ADJ_OFFSET	16
+#define CTRL_GATEDURADJ_MASK	(0xf << 20)
+#define READ_LEVELLING_DDR3	0x0100
+
+#define PHY_CON2_RESET_VAL	0x00010004
+#define INIT_DESKEW_EN		(1 << 6)
+#define DLL_DESKEW_EN		(1 << 12)
+#define RDLVL_GATE_EN		(1 << 24)
+#define RDLVL_EN		(1 << 25)
+#define RDLVL_INCR_ADJ		(0x1 << 16)
+
+/* DREX_PAUSE */
+#define DREX_PAUSE_EN	(1 << 0)
+
+#define BYPASS_EN	(1 << 22)
+
+/* MEMMORY VAL */
+#define PHY_CON0_VAL	0x17021A00
+
+#define PHY_CON12_RESET_VAL	0x10100070
+#define PHY_CON12_VAL		0x10107F50
+#define CTRL_START		(1 << 6)
+#define CTRL_DLL_ON		(1 << 5)
+#define CTRL_FORCE_MASK		(0x7F << 8)
+#define CTRL_LOCK_COARSE_MASK	(0x7F << 10)
+
+#define CTRL_OFFSETD_RESET_VAL	0x8
+#define CTRL_OFFSETD_VAL	0x7F
+
+#define CTRL_OFFSETR0		0x7F
+#define CTRL_OFFSETR1		0x7F
+#define CTRL_OFFSETR2		0x7F
+#define CTRL_OFFSETR3		0x7F
+#define PHY_CON4_VAL	(CTRL_OFFSETR0 << 0 | \
+				CTRL_OFFSETR1 << 8 | \
+				CTRL_OFFSETR2 << 16 | \
+				CTRL_OFFSETR3 << 24)
+#define PHY_CON4_RESET_VAL	0x08080808
+
+#define CTRL_OFFSETW0		0x7F
+#define CTRL_OFFSETW1		0x7F
+#define CTRL_OFFSETW2		0x7F
+#define CTRL_OFFSETW3		0x7F
+#define PHY_CON6_VAL	(CTRL_OFFSETW0 << 0 | \
+				CTRL_OFFSETW1 << 8 | \
+				CTRL_OFFSETW2 << 16 | \
+				CTRL_OFFSETW3 << 24)
+#define PHY_CON6_RESET_VAL	0x08080808
+
+#define PHY_CON14_RESET_VAL	0x001F0000
+#define CTRL_PULLD_DQS		0xF
+#define CTRL_PULLD_DQS_OFFSET	0
+
+/* ZQ Configurations */
+#define PHY_CON16_RESET_VAL	0x08000304
+
+#define ZQ_CLK_EN		(1 << 27)
+#define ZQ_CLK_DIV_EN		(1 << 18)
+#define ZQ_MANUAL_STR		(1 << 1)
+#define ZQ_DONE			(1 << 0)
+#define ZQ_MODE_DDS_OFFSET	24
+
+#define CTRL_RDLVL_GATE_ENABLE	1
+#define CTRL_RDLVL_GATE_DISABLE	0
+#define CTRL_RDLVL_DATA_ENABLE	2
+
+/* Direct Command */
+#define DIRECT_CMD_NOP			0x07000000
+#define DIRECT_CMD_PALL			0x01000000
+#define DIRECT_CMD_ZQINIT		0x0a000000
+#define DIRECT_CMD_CHANNEL_SHIFT	28
+#define DIRECT_CMD_CHIP_SHIFT		20
+#define DIRECT_CMD_BANK_SHIFT		16
+#define DIRECT_CMD_REFA		(5 << 24)
+#define DIRECT_CMD_MRS1		0x71C00
+#define DIRECT_CMD_MRS2		0x10BFC
+#define DIRECT_CMD_MRS3		0x0050C
+#define DIRECT_CMD_MRS4		0x00868
+#define DIRECT_CMD_MRS5		0x00C04
+
+/* Drive Strength */
+#define IMPEDANCE_48_OHM	4
+#define IMPEDANCE_40_OHM	5
+#define IMPEDANCE_34_OHM	6
+#define IMPEDANCE_30_OHM	7
+#define PHY_CON39_VAL_48_OHM	0x09240924
+#define PHY_CON39_VAL_40_OHM	0x0B6D0B6D
+#define PHY_CON39_VAL_34_OHM	0x0DB60DB6
+#define PHY_CON39_VAL_30_OHM	0x0FFF0FFF
+
+#define CTRL_BSTLEN_OFFSET	8
+#define CTRL_RDLAT_OFFSET	0
+
+#define CMD_DEFAULT_LPDDR3	0xF
+#define CMD_DEFUALT_OFFSET	0
+#define T_WRDATA_EN		0x7
+#define T_WRDATA_EN_DDR3	0x8
+#define T_WRDATA_EN_OFFSET	16
+#define T_WRDATA_EN_MASK	0x1f
+
+#define PHY_CON31_VAL	0x0C183060
+#define PHY_CON32_VAL	0x60C18306
+#define PHY_CON33_VAL	0x00000030
+
+#define PHY_CON31_RESET_VAL	0x0
+#define PHY_CON32_RESET_VAL	0x0
+#define PHY_CON33_RESET_VAL	0x0
+
+#define SL_DLL_DYN_CON_EN	(1 << 1)
+#define FP_RESYNC	(1 << 3)
+#define CTRL_START	(1 << 6)
+
+#define DMC_AREF_EN		(1 << 5)
+#define DMC_CONCONTROL_EMPTY	(1 << 8)
+#define DFI_INIT_START		(1 << 28)
+
+#define DMC_MEMCONTROL_VAL	0x00312700
+#define CLK_STOP_EN		(1 << 0)
+#define DPWRDN_EN		(1 << 1)
+#define DSREF_EN		(1 << 5)
+
+#define MEMBASECONFIG_CHIP_MASK_VAL	0x7E0
+#define MEMBASECONFIG_CHIP_MASK_OFFSET	0
+#define MEMBASECONFIG0_CHIP_BASE_VAL	0x20
+#define MEMBASECONFIG1_CHIP_BASE_VAL	0x40
+#define CHIP_BASE_OFFSET		16
+
+#define MEMCONFIG_VAL	0x1323
+#define PRECHCONFIG_DEFAULT_VAL	0xFF000000
+#define PWRDNCONFIG_DEFAULT_VAL	0xFFFF00FF
+
+#define TIMINGAREF_VAL	0x5d
+#define TIMINGROW_VAL	0x345A8692
+#define TIMINGDATA_VAL	0x3630065C
+#define TIMINGPOWER_VAL	0x50380336
+#define DFI_INIT_COMPLETE	(1 << 3)
+
+#define BRBRSVCONTROL_VAL	0x00000033
+#define BRBRSVCONFIG_VAL	0x88778877
+
+/* Clock Gating Control (CGCONTROL) register */
+#define MEMIF_CG_EN	(1 << 3) /* Memory interface clock gating */
+#define SCG_CG_EN	(1 << 2) /* Scheduler clock gating */
+#define BUSIF_WR_CG_EN	(1 << 1) /* Bus interface write channel clock gating */
+#define BUSIF_RD_CG_EN	(1 << 0) /* Bus interface read channel clock gating */
+#define DMC_INTERNAL_CG	(MEMIF_CG_EN | SCG_CG_EN | \
+				 BUSIF_WR_CG_EN | BUSIF_RD_CG_EN)
+
+/* DMC PHY Control0 register */
+#define PHY_CONTROL0_RESET_VAL	0x0
+#define MEM_TERM_EN	(1 << 31)	/* Termination enable for memory */
+#define PHY_TERM_EN	(1 << 30)	/* Termination enable for PHY */
+#define DMC_CTRL_SHGATE	(1 << 29)	/* Duration of DQS gating signal */
+#define FP_RSYNC	(1 << 3)	/* Force DLL resyncronization */
+
+/* Driver strength for CK, CKE, CS & CA */
+#define IMP_OUTPUT_DRV_40_OHM	0x5
+#define IMP_OUTPUT_DRV_30_OHM	0x7
+#define DA_3_DS_OFFSET		25
+#define DA_2_DS_OFFSET		22
+#define DA_1_DS_OFFSET		19
+#define DA_0_DS_OFFSET		16
+#define CA_CK_DRVR_DS_OFFSET	9
+#define CA_CKE_DRVR_DS_OFFSET	6
+#define CA_CS_DRVR_DS_OFFSET	3
+#define CA_ADR_DRVR_DS_OFFSET	0
+
+#define PHY_CON42_CTRL_BSTLEN_SHIFT	8
+#define PHY_CON42_CTRL_RDLAT_SHIFT	0
+
+/*
+ * Definitions that differ with SoC's.
+ * Below is the part defining macros for smdk5250.
+ * Else part introduces macros for smdk5420.
+ */
+#ifndef CONFIG_SMDK5420
+
+/* APLL_CON1 */
+#define APLL_CON1_VAL	(0x00203800)
+
+/* MPLL_CON1 */
+#define MPLL_CON1_VAL   (0x00203800)
+
+/* CPLL_CON1 */
+#define CPLL_CON1_VAL	(0x00203800)
+
+/* DPLL_CON1 */
+#define DPLL_CON1_VAL	(NOT_AVAILABLE)
+
+/* GPLL_CON1 */
+#define GPLL_CON1_VAL	(0x00203800)
+
+/* EPLL_CON1, CON2 */
+#define EPLL_CON1_VAL	0x00000000
+#define EPLL_CON2_VAL	0x00000080
+
+/* VPLL_CON1, CON2 */
+#define VPLL_CON1_VAL	0x00000000
+#define VPLL_CON2_VAL	0x00000080
+
+/* RPLL_CON1, CON2 */
+#define RPLL_CON1_VAL	NOT_AVAILABLE
+#define RPLL_CON2_VAL	NOT_AVAILABLE
+
+/* BPLL_CON1 */
+#define BPLL_CON1_VAL	0x00203800
+
+/* SPLL_CON1 */
+#define SPLL_CON1_VAL	NOT_AVAILABLE
+
+/* IPLL_CON1 */
+#define IPLL_CON1_VAL	NOT_AVAILABLE
+
+/* KPLL_CON1 */
+#define KPLL_CON1_VAL	NOT_AVAILABLE
+
+/* CLK_SRC_ISP */
+#define CLK_SRC_ISP_VAL		NOT_AVAILABLE
+#define CLK_DIV_ISP0_VAL	0x31
+#define CLK_DIV_ISP1_VAL	0x0
+
+/* CLK_FSYS */
+#define CLK_SRC_FSYS0_VAL              0x66666
+#define CLK_DIV_FSYS0_VAL	       0x0BB00000
+#define CLK_DIV_FSYS1_VAL	       NOT_AVAILABLE
+#define CLK_DIV_FSYS2_VAL	       NOT_AVAILABLE
+
+/* CLK_SRC_CPU */
+/* 0 = MOUTAPLL,  1 = SCLKMPLL */
+#define MUX_HPM_SEL             0
+#define MUX_CPU_SEL             0
+#define MUX_APLL_SEL            1
+
+#define CLK_SRC_CPU_VAL		((MUX_HPM_SEL << 20)    \
+				| (MUX_CPU_SEL << 16)  \
+				| (MUX_APLL_SEL))
+
 /* CLK_SRC_CDREX */
 #define CLK_SRC_CDREX_VAL       0x1
 
 /* CLK_DIV_CDREX */
+#define CLK_DIV_CDREX0_VAL	NOT_AVAILABLE
+#define CLK_DIV_CDREX1_VAL	NOT_AVAILABLE
+
+/* CLK_DIV_CPU0_VAL */
+#define CLK_DIV_CPU0_VAL	NOT_AVAILABLE
+
 #define MCLK_CDREX2_RATIO       0x0
 #define ACLK_EFCON_RATIO        0x1
 #define MCLK_DPHY_RATIO		0x1
@@ -247,6 +585,11 @@
 				| (MUX_ACLK_300_DISP1_SUB_SEL << 6)     \
 				| (MUX_ACLK_200_DISP1_SUB_SEL << 4))
 
+#define CLK_SRC_TOP4_VAL	NOT_AVAILABLE
+#define CLK_SRC_TOP5_VAL	NOT_AVAILABLE
+#define CLK_SRC_TOP6_VAL	NOT_AVAILABLE
+#define CLK_SRC_TOP7_VAL	NOT_AVAILABLE
+
 /* CLK_DIV_TOP0	*/
 #define ACLK_300_DISP1_RATIO	0x2
 #define ACLK_400_G3D_RATIO	0x0
@@ -279,40 +622,11 @@
 				| (ACLK_400_IOP_RATIO << 16)		\
 				| (ACLK_300_GSCL_RATIO << 12))
 
-/* APLL_LOCK	*/
-#define APLL_LOCK_VAL	(0x546)
-/* MPLL_LOCK	*/
-#define MPLL_LOCK_VAL	(0x546)
-/* CPLL_LOCK	*/
-#define CPLL_LOCK_VAL	(0x546)
-/* GPLL_LOCK	*/
-#define GPLL_LOCK_VAL	(0x546)
-/* EPLL_LOCK	*/
-#define EPLL_LOCK_VAL	(0x3A98)
-/* VPLL_LOCK	*/
-#define VPLL_LOCK_VAL	(0x3A98)
-/* BPLL_LOCK	*/
-#define BPLL_LOCK_VAL	(0x546)
+#define CLK_DIV_TOP2_VAL	NOT_AVAILABLE
 
-#define MUX_APLL_SEL_MASK	(1 << 0)
-#define MUX_MPLL_SEL_MASK	(1 << 8)
-#define MPLL_SEL_MOUT_MPLLFOUT	(2 << 8)
-#define MUX_CPLL_SEL_MASK	(1 << 8)
-#define MUX_EPLL_SEL_MASK	(1 << 12)
-#define MUX_VPLL_SEL_MASK	(1 << 16)
-#define MUX_GPLL_SEL_MASK	(1 << 28)
-#define MUX_BPLL_SEL_MASK	(1 << 0)
-#define MUX_HPM_SEL_MASK	(1 << 20)
-#define HPM_SEL_SCLK_MPLL	(1 << 21)
-#define APLL_CON0_LOCKED	(1 << 29)
-#define MPLL_CON0_LOCKED	(1 << 29)
-#define BPLL_CON0_LOCKED	(1 << 29)
-#define CPLL_CON0_LOCKED	(1 << 29)
-#define EPLL_CON0_LOCKED	(1 << 29)
-#define GPLL_CON0_LOCKED	(1 << 29)
-#define VPLL_CON0_LOCKED	(1 << 29)
-#define CLK_REG_DISABLE		0x0
-#define TOP2_VAL		0x0110000
+/* PLL Lock Value Factor */
+#define PLL_LOCK_FACTOR		250
+#define PLL_X_LOCK_FACTOR	3000
 
 /* CLK_SRC_PERIC0 */
 #define PWM_SEL		6
@@ -336,18 +650,6 @@
 				| (SPI1_SEL << 20) \
 				| (SPI0_SEL << 16))
 
-/* SCLK_SRC_ISP - set SPI0/1 to 6 = SCLK_MPLL_USER */
-#define SPI0_ISP_SEL		6
-#define SPI1_ISP_SEL		6
-#define SCLK_SRC_ISP_VAL	(SPI1_ISP_SEL << 4) \
-				| (SPI0_ISP_SEL << 0)
-
-/* SCLK_DIV_ISP - set SPI0/1 to 0xf = divide by 16 */
-#define SPI0_ISP_RATIO		0xf
-#define SPI1_ISP_RATIO		0xf
-#define SCLK_DIV_ISP_VAL	(SPI1_ISP_RATIO << 12) \
-				| (SPI0_ISP_RATIO << 0)
-
 /* CLK_DIV_PERIL0	*/
 #define UART5_RATIO	7
 #define UART4_RATIO	7
@@ -380,105 +682,201 @@
 #define PWM_RATIO		8
 #define CLK_DIV_PERIC3_VAL	(PWM_RATIO << 0)
 
-/* CLK_DIV_FSYS2 */
-#define MMC2_RATIO_MASK		0xf
-#define MMC2_RATIO_VAL		0x3
-#define MMC2_RATIO_OFFSET	0
 
-#define MMC2_PRE_RATIO_MASK	0xff
-#define MMC2_PRE_RATIO_VAL	0x9
-#define MMC2_PRE_RATIO_OFFSET	8
+/* CLK_DIV_PERIC4 */
+#define CLK_DIV_PERIC4_VAL	NOT_AVAILABLE
 
-#define MMC3_RATIO_MASK		0xf
-#define MMC3_RATIO_VAL		0x1
-#define MMC3_RATIO_OFFSET	16
+/* CLK_SRC_DISP1_0 */
+#define CLK_SRC_DISP1_0_VAL	0x6
+#define CLK_DIV_DISP1_0_VAL	NOT_AVAILABLE
 
-#define MMC3_PRE_RATIO_MASK	0xff
-#define MMC3_PRE_RATIO_VAL	0x0
-#define MMC3_PRE_RATIO_OFFSET	24
+#define APLL_FOUT		(1 << 0)
+#define KPLL_FOUT		NOT_AVAILABLE
 
-/* CLK_SRC_LEX */
-#define CLK_SRC_LEX_VAL         0x0
+#define CLK_DIV_CPERI1_VAL	NOT_AVAILABLE
 
-/* CLK_DIV_LEX */
-#define CLK_DIV_LEX_VAL         0x10
+#else
+#define PAD_RETENTION_DRAM_COREBLK_VAL	0x10000000
 
-/* CLK_DIV_R0X */
-#define CLK_DIV_R0X_VAL         0x10
+/* APLL_CON1 */
+#define APLL_CON1_VAL	(0x0020F300)
 
-/* CLK_DIV_L0X */
-#define CLK_DIV_R1X_VAL         0x10
+/* MPLL_CON1 */
+#define MPLL_CON1_VAL   (0x0020F300)
 
-/* CLK_DIV_ISP0 */
-#define CLK_DIV_ISP0_VAL        0x31
 
-/* CLK_DIV_ISP1 */
-#define CLK_DIV_ISP1_VAL        0x0
+/* CPLL_CON1 */
+#define CPLL_CON1_VAL	0x0020f300
 
-/* CLK_DIV_ISP2 */
-#define CLK_DIV_ISP2_VAL        0x1
+/* DPLL_CON1 */
+#define DPLL_CON1_VAL	(0x0020F300)
 
-/* CLK_SRC_DISP1_0 */
-#define CLK_SRC_DISP1_0_VAL	0x6
+/* GPLL_CON1 */
+#define GPLL_CON1_VAL	(NOT_AVAILABLE)
 
-/*
- * DIV_DISP1_0
- * For DP, divisor should be 2
- */
-#define CLK_DIV_DISP1_0_FIMD1	(2 << 0)
 
-/* CLK_GATE_IP_DISP1 */
-#define CLK_GATE_DP1_ALLOW	(1 << 4)
+/* EPLL_CON1, CON2 */
+#define EPLL_CON1_VAL	0x00000000
+#define EPLL_CON2_VAL	0x00000080
 
-#define DDR3PHY_CTRL_PHY_RESET	(1 << 0)
-#define DDR3PHY_CTRL_PHY_RESET_OFF	(0 << 0)
+/* VPLL_CON1, CON2 */
+#define VPLL_CON1_VAL	0x0020f300
+#define VPLL_CON2_VAL	NOT_AVAILABLE
 
-#define PHY_CON0_RESET_VAL	0x17020a40
-#define P0_CMD_EN		(1 << 14)
-#define BYTE_RDLVL_EN		(1 << 13)
-#define CTRL_SHGATE		(1 << 8)
+/* RPLL_CON1, CON2 */
+#define RPLL_CON1_VAL	0x00000000
+#define RPLL_CON2_VAL	0x00000080
 
-#define PHY_CON1_RESET_VAL	0x09210100
-#define CTRL_GATEDURADJ_MASK	(0xf << 20)
+/* BPLL_CON1 */
+#define BPLL_CON1_VAL	0x0020f300
 
-#define PHY_CON2_RESET_VAL	0x00010004
-#define INIT_DESKEW_EN		(1 << 6)
-#define RDLVL_GATE_EN		(1 << 24)
+/* SPLL_CON1 */
+#define SPLL_CON1_VAL	0x0020f300
 
-/*ZQ Configurations */
-#define PHY_CON16_RESET_VAL	0x08000304
+/* IPLL_CON1 */
+#define IPLL_CON1_VAL	0x00000080
 
-#define ZQ_CLK_DIV_EN		(1 << 18)
-#define ZQ_MANUAL_STR		(1 << 1)
-#define ZQ_DONE			(1 << 0)
+/* KPLL_CON1 */
+#define KPLL_CON1_VAL	0x200000
 
-#define CTRL_RDLVL_GATE_ENABLE	1
-#define CTRL_RDLVL_GATE_DISABLE	1
+/* CLK_SRC_ISP */
+#define CLK_SRC_ISP_VAL		0x33366000
+#define CLK_DIV_ISP0_VAL	0x13131300
+#define CLK_DIV_ISP1_VAL	0xbb110202
 
-/* Direct Command */
-#define DIRECT_CMD_NOP			0x07000000
-#define DIRECT_CMD_PALL			0x01000000
-#define DIRECT_CMD_ZQINIT		0x0a000000
-#define DIRECT_CMD_CHANNEL_SHIFT	28
-#define DIRECT_CMD_CHIP_SHIFT		20
 
-/* DMC PHY Control0 register */
-#define PHY_CONTROL0_RESET_VAL	0x0
-#define MEM_TERM_EN	(1 << 31)	/* Termination enable for memory */
-#define PHY_TERM_EN	(1 << 30)	/* Termination enable for PHY */
-#define DMC_CTRL_SHGATE	(1 << 29)	/* Duration of DQS gating signal */
-#define FP_RSYNC	(1 << 3)	/* Force DLL resyncronization */
+/* CLK_FSYS */
+#define CLK_SRC_FSYS0_VAL              0x33033300
+#define CLK_DIV_FSYS0_VAL	       0x0
+#define CLK_DIV_FSYS1_VAL	       0x04f13c4f
+#define CLK_DIV_FSYS2_VAL	       0x041d0000
+
+/* CLK_SRC_CPU */
+/* 0 = MOUTAPLL,  1 = SCLKMPLL */
+#define MUX_HPM_SEL             1
+#define MUX_CPU_SEL             0
+#define MUX_APLL_SEL            1
 
-/* Driver strength for CK, CKE, CS & CA */
-#define IMP_OUTPUT_DRV_40_OHM	0x5
-#define IMP_OUTPUT_DRV_30_OHM	0x7
-#define CA_CK_DRVR_DS_OFFSET	9
-#define CA_CKE_DRVR_DS_OFFSET	6
-#define CA_CS_DRVR_DS_OFFSET	3
-#define CA_ADR_DRVR_DS_OFFSET	0
+#define CLK_SRC_CPU_VAL		((MUX_HPM_SEL << 20)    \
+				| (MUX_CPU_SEL << 16)  \
+				| (MUX_APLL_SEL))
 
-#define PHY_CON42_CTRL_BSTLEN_SHIFT	8
-#define PHY_CON42_CTRL_RDLAT_SHIFT	0
+/* CLK_SRC_CDREX */
+#define CLK_SRC_CDREX_VAL       0x00000011
+
+/* CLK_DIV_CDREX */
+#define CLK_DIV_CDREX0_VAL	0x30010100
+#define CLK_DIV_CDREX1_VAL	0x300
+
+#define CLK_DIV_CDREX_VAL       0x17010100
+
+/* CLK_DIV_CPU0_VAL */
+#define CLK_DIV_CPU0_VAL	0x01440020
+
+/* CLK_SRC_TOP */
+#define CLK_SRC_TOP0_VAL	0x12221222
+#define CLK_SRC_TOP1_VAL	0x00100200
+#define CLK_SRC_TOP2_VAL	0x11101000
+#define CLK_SRC_TOP3_VAL	0x11111111
+#define CLK_SRC_TOP4_VAL	0x11110111
+#define CLK_SRC_TOP5_VAL	0x11111100
+#define CLK_SRC_TOP6_VAL	0x11110111
+#define CLK_SRC_TOP7_VAL	0x00022200
+
+/* CLK_DIV_TOP */
+#define CLK_DIV_TOP0_VAL	0x23712311
+#define CLK_DIV_TOP1_VAL	0x13100B00
+#define CLK_DIV_TOP2_VAL	0x11101100
+
+/* PLL Lock Value Factor */
+#define PLL_LOCK_FACTOR		200
+#define PLL_X_LOCK_FACTOR	3000
+
+/* CLK_SRC_PERIC0 */
+#define SPDIF_SEL	1
+#define PWM_SEL		3
+#define UART4_SEL	3
+#define UART3_SEL	3
+#define UART2_SEL	3
+#define UART1_SEL	3
+#define UART0_SEL	3
+/* SRC_CLOCK = SCLK_RPLL */
+#define CLK_SRC_PERIC0_VAL	((SPDIF_SEL << 28)	\
+				| (PWM_SEL << 24)	\
+				| (UART4_SEL << 20)	\
+				| (UART3_SEL << 16)	\
+				| (UART2_SEL << 12)	\
+				| (UART1_SEL << 8)	\
+				| (UART0_SEL << 4))
+
+/* CLK_SRC_PERIC1 */
+/* SRC_CLOCK = SCLK_EPLL */
+#define SPI0_SEL		6
+#define SPI1_SEL		6
+#define SPI2_SEL		6
+#define AUDIO0_SEL		6
+#define AUDIO1_SEL		6
+#define AUDIO2_SEL		6
+#define CLK_SRC_PERIC1_VAL	((SPI2_SEL << 28)	\
+				| (SPI1_SEL << 24)	\
+				| (SPI0_SEL << 20)	\
+				| (AUDIO2_SEL << 16)	\
+				| (AUDIO2_SEL << 12)	\
+				| (AUDIO2_SEL << 8))
+
+/* CLK_DIV_PERIC0 */
+#define PWM_RATIO	8
+#define UART4_RATIO	9
+#define UART3_RATIO	9
+#define UART2_RATIO	9
+#define UART1_RATIO	9
+#define UART0_RATIO	9
+
+#define CLK_DIV_PERIC0_VAL	((PWM_RATIO << 28)	\
+				| (UART4_RATIO << 24)	\
+				| (UART3_RATIO << 20)    \
+				| (UART2_RATIO << 16)    \
+				| (UART1_RATIO << 12)    \
+				| (UART0_RATIO << 8))
+/* CLK_DIV_PERIC1 */
+#define SPI2_RATIO		0x1
+#define SPI1_RATIO		0x1
+#define SPI0_RATIO		0x1
+#define CLK_DIV_PERIC1_VAL	((SPI2_RATIO << 28)	\
+				| (SPI1_RATIO << 24)	\
+				| (SPI0_RATIO << 20))
+
+/* CLK_DIV_PERIC2 */
+#define PCM2_RATIO		0x3
+#define PCM1_RATIO		0x3
+#define CLK_DIV_PERIC2_VAL	((PCM2_RATIO << 24) \
+				| (PCM1_RATIO << 16))
+
+/* CLK_DIV_PERIC3 */
+#define AUDIO2_RATIO		0x5
+#define AUDIO1_RATIO		0x5
+#define AUDIO0_RATIO		0x5
+#define CLK_DIV_PERIC3_VAL	((AUDIO2_RATIO << 28)	\
+				| (AUDIO1_RATIO << 24)	\
+				| (AUDIO0_RATIO << 20))
+
+/* CLK_DIV_PERIC4 */
+#define SPI2_PRE_RATIO		0x2
+#define SPI1_PRE_RATIO		0x2
+#define SPI0_PRE_RATIO		0x2
+#define CLK_DIV_PERIC4_VAL	((SPI2_PRE_RATIO << 24)	\
+				| (SPI1_PRE_RATIO << 16) \
+				| (SPI0_PRE_RATIO << 8))
+
+/* CLK_SRC_DISP1_0 */
+#define CLK_SRC_DISP1_0_VAL	0x10666600
+#define CLK_DIV_DISP1_0_VAL	0x01050211
+
+#define APLL_FOUT		(1 << 0)
+#define KPLL_FOUT		(1 << 0)
+
+#define CLK_DIV_CPERI1_VAL	0x3f3f0000
+#endif
 
 struct mem_timings;
 
@@ -490,7 +888,7 @@ enum {
 };
 
 /*
- * Memory variant specific initialization code
+ * Memory variant specific initialization code for DDR3
  *
  * @param mem		Memory timings for this memory type.
  * @param mem_iv_size	Memory interleaving size is a configurable parameter
@@ -503,49 +901,45 @@ enum {
 int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned long mem_iv_size,
 			int reset);
 
+/* Memory variant specific initialization code for LPDDR3 */
+void lpddr3_mem_ctrl_init(void);
+
 /*
  * Configure ZQ I/O interface
  *
  * @param mem		Memory timings for this memory type.
- * @param phy0_ctrl	Pointer to struct containing PHY0 control reg
- * @param phy1_ctrl	Pointer to struct containing PHY1 control reg
+ * @param phy0_con16	Register address for dmc_phy0->phy_con16
+ * @param phy1_con16	Register address for dmc_phy1->phy_con16
+ * @param phy0_con17	Register address for dmc_phy0->phy_con17
+ * @param phy1_con17	Register address for dmc_phy1->phy_con17
  * @return 0 if ok, -1 on error
  */
-int dmc_config_zq(struct mem_timings *mem,
-		  struct exynos5_phy_control *phy0_ctrl,
-		  struct exynos5_phy_control *phy1_ctrl);
-
+int dmc_config_zq(struct mem_timings *mem, uint32_t *phy0_con16,
+			uint32_t *phy1_con16, uint32_t *phy0_con17,
+			uint32_t *phy1_con17);
 /*
  * Send NOP and MRS/EMRS Direct commands
  *
  * @param mem		Memory timings for this memory type.
- * @param dmc		Pointer to struct of DMC registers
+ * @param directcmd	Register address for dmc_phy->directcmd
  */
-void dmc_config_mrs(struct mem_timings *mem, struct exynos5_dmc *dmc);
+void dmc_config_mrs(struct mem_timings *mem, uint32_t *directcmd);
 
 /*
  * Send PALL Direct commands
  *
  * @param mem		Memory timings for this memory type.
- * @param dmc		Pointer to struct of DMC registers
- */
-void dmc_config_prech(struct mem_timings *mem, struct exynos5_dmc *dmc);
-
-/*
- * Configure the memconfig and membaseconfig registers
- *
- * @param mem		Memory timings for this memory type.
- * @param exynos5_dmc	Pointer to struct of DMC registers
+ * @param directcmd	Register address for dmc_phy->directcmd
  */
-void dmc_config_memory(struct mem_timings *mem, struct exynos5_dmc *dmc);
+void dmc_config_prech(struct mem_timings *mem, uint32_t *directcmd);
 
 /*
  * Reset the DLL. This function is common between DDR3 and LPDDR2.
  * However, the reset value is different. So we are passing a flag
  * ddr_mode to distinguish between LPDDR2 and DDR3.
  *
- * @param exynos5_dmc	Pointer to struct of DMC registers
+ * @param phycontrol0	Register address for dmc_phy->phycontrol0
  * @param ddr_mode	Type of DDR memory
  */
-void update_reset_dll(struct exynos5_dmc *, enum ddr_mode);
+void update_reset_dll(uint32_t *phycontrol0, enum ddr_mode);
 #endif
diff --git a/arch/arm/cpu/armv7/exynos/pinmux.c b/arch/arm/cpu/armv7/exynos/pinmux.c
index 8002bce79c..9edb47502c 100644
--- a/arch/arm/cpu/armv7/exynos/pinmux.c
+++ b/arch/arm/cpu/armv7/exynos/pinmux.c
@@ -39,7 +39,49 @@ static void exynos5_uart_config(int peripheral)
 		start = 4;
 		count = 2;
 		break;
+	default:
+		debug("%s: invalid peripheral %d", __func__, peripheral);
+		return;
+	}
+	for (i = start; i < start + count; i++) {
+		s5p_gpio_set_pull(bank, i, GPIO_PULL_NONE);
+		s5p_gpio_cfg_pin(bank, i, GPIO_FUNC(0x2));
+	}
+}
+
+static void exynos5420_uart_config(int peripheral)
+{
+	struct exynos5420_gpio_part1 *gpio1 =
+		(struct exynos5420_gpio_part1 *)samsung_get_base_gpio_part1();
+	struct s5p_gpio_bank *bank;
+	int i, start, count;
+
+	switch (peripheral) {
+	case PERIPH_ID_UART0:
+		bank = &gpio1->a0;
+		start = 0;
+		count = 4;
+		break;
+	case PERIPH_ID_UART1:
+		bank = &gpio1->a0;
+		start = 4;
+		count = 4;
+		break;
+	case PERIPH_ID_UART2:
+		bank = &gpio1->a1;
+		start = 0;
+		count = 4;
+		break;
+	case PERIPH_ID_UART3:
+		bank = &gpio1->a1;
+		start = 4;
+		count = 2;
+		break;
+	default:
+		debug("%s: invalid peripheral %d", __func__, peripheral);
+		return;
 	}
+
 	for (i = start; i < start + count; i++) {
 		s5p_gpio_set_pull(bank, i, GPIO_PULL_NONE);
 		s5p_gpio_cfg_pin(bank, i, GPIO_FUNC(0x2));
@@ -74,6 +116,9 @@ static int exynos5_mmc_config(int peripheral, int flags)
 		bank = &gpio1->c4;
 		bank_ext = NULL;
 		break;
+	default:
+		debug("%s: invalid peripheral %d", __func__, peripheral);
+		return -1;
 	}
 	if ((flags & PINMUX_FLAG_8BIT_MODE) && !bank_ext) {
 		debug("SDMMC device %d does not support 8bit mode",
@@ -101,6 +146,75 @@ static int exynos5_mmc_config(int peripheral, int flags)
 	return 0;
 }
 
+static int exynos5420_mmc_config(int peripheral, int flags)
+{
+	struct exynos5420_gpio_part3 *gpio3 =
+		(struct exynos5420_gpio_part3 *)samsung_get_base_gpio_part3();
+	struct s5p_gpio_bank *bank = NULL, *bank_ext = NULL;
+	int i, start;
+
+	switch (peripheral) {
+	case PERIPH_ID_SDMMC0:
+		bank = &gpio3->c0;
+		bank_ext = &gpio3->c3;
+		start = 0;
+		break;
+	case PERIPH_ID_SDMMC1:
+		bank = &gpio3->c1;
+		bank_ext = &gpio3->d1;
+		start = 4;
+		break;
+	case PERIPH_ID_SDMMC2:
+		bank = &gpio3->c2;
+		bank_ext = NULL;
+		start = 0;
+		break;
+	default:
+		start = 0;
+		debug("%s: invalid peripheral %d", __func__, peripheral);
+		return -1;
+	}
+
+	if ((flags & PINMUX_FLAG_8BIT_MODE) && !bank_ext) {
+		debug("SDMMC device %d does not support 8bit mode",
+		      peripheral);
+		return -1;
+	}
+
+	if (flags & PINMUX_FLAG_8BIT_MODE) {
+		for (i = start; i <= (start + 3); i++) {
+			s5p_gpio_cfg_pin(bank_ext, i, GPIO_FUNC(0x2));
+			s5p_gpio_set_pull(bank_ext, i, GPIO_PULL_UP);
+			s5p_gpio_set_drv(bank_ext, i, GPIO_DRV_4X);
+		}
+	}
+
+	for (i = 0; i < 3; i++) {
+		/*
+		 * MMC0 is intended to be used for eMMC. The
+		 * card detect pin is used as a VDDEN signal to
+		 * power on the eMMC. The 5420 iROM makes
+		 * this same assumption.
+		 */
+		if ((peripheral == PERIPH_ID_SDMMC0) && (i == 2)) {
+			s5p_gpio_set_value(bank, i, 1);
+			s5p_gpio_cfg_pin(bank, i, GPIO_OUTPUT);
+		} else {
+			s5p_gpio_cfg_pin(bank, i, GPIO_FUNC(0x2));
+		}
+		s5p_gpio_set_pull(bank, i, GPIO_PULL_NONE);
+		s5p_gpio_set_drv(bank, i, GPIO_DRV_4X);
+	}
+
+	for (i = 3; i <= 6; i++) {
+		s5p_gpio_cfg_pin(bank, i, GPIO_FUNC(0x2));
+		s5p_gpio_set_pull(bank, i, GPIO_PULL_UP);
+		s5p_gpio_set_drv(bank, i, GPIO_DRV_4X);
+	}
+
+	return 0;
+}
+
 static void exynos5_sromc_config(int flags)
 {
 	struct exynos5_gpio_part1 *gpio1 =
@@ -216,6 +330,59 @@ static void exynos5_i2c_config(int peripheral, int flags)
 	}
 }
 
+static void exynos5420_i2c_config(int peripheral)
+{
+	struct exynos5420_gpio_part1 *gpio1 =
+		(struct exynos5420_gpio_part1 *)samsung_get_base_gpio_part1();
+
+	switch (peripheral) {
+	case PERIPH_ID_I2C0:
+		s5p_gpio_cfg_pin(&gpio1->b3, 0, GPIO_FUNC(0x2));
+		s5p_gpio_cfg_pin(&gpio1->b3, 1, GPIO_FUNC(0x2));
+		break;
+	case PERIPH_ID_I2C1:
+		s5p_gpio_cfg_pin(&gpio1->b3, 2, GPIO_FUNC(0x2));
+		s5p_gpio_cfg_pin(&gpio1->b3, 3, GPIO_FUNC(0x2));
+		break;
+	case PERIPH_ID_I2C2:
+		s5p_gpio_cfg_pin(&gpio1->a0, 6, GPIO_FUNC(0x3));
+		s5p_gpio_cfg_pin(&gpio1->a0, 7, GPIO_FUNC(0x3));
+		break;
+	case PERIPH_ID_I2C3:
+		s5p_gpio_cfg_pin(&gpio1->a1, 2, GPIO_FUNC(0x3));
+		s5p_gpio_cfg_pin(&gpio1->a1, 3, GPIO_FUNC(0x3));
+		break;
+	case PERIPH_ID_I2C4:
+		s5p_gpio_cfg_pin(&gpio1->a2, 0, GPIO_FUNC(0x3));
+		s5p_gpio_cfg_pin(&gpio1->a2, 1, GPIO_FUNC(0x3));
+		break;
+	case PERIPH_ID_I2C5:
+		s5p_gpio_cfg_pin(&gpio1->a2, 2, GPIO_FUNC(0x3));
+		s5p_gpio_cfg_pin(&gpio1->a2, 3, GPIO_FUNC(0x3));
+		break;
+	case PERIPH_ID_I2C6:
+		s5p_gpio_cfg_pin(&gpio1->b1, 3, GPIO_FUNC(0x4));
+		s5p_gpio_cfg_pin(&gpio1->b1, 4, GPIO_FUNC(0x4));
+		break;
+	case PERIPH_ID_I2C7:
+		s5p_gpio_cfg_pin(&gpio1->b2, 2, GPIO_FUNC(0x3));
+		s5p_gpio_cfg_pin(&gpio1->b2, 3, GPIO_FUNC(0x3));
+		break;
+	case PERIPH_ID_I2C8:
+		s5p_gpio_cfg_pin(&gpio1->b3, 4, GPIO_FUNC(0x2));
+		s5p_gpio_cfg_pin(&gpio1->b3, 5, GPIO_FUNC(0x2));
+		break;
+	case PERIPH_ID_I2C9:
+		s5p_gpio_cfg_pin(&gpio1->b3, 6, GPIO_FUNC(0x2));
+		s5p_gpio_cfg_pin(&gpio1->b3, 7, GPIO_FUNC(0x2));
+		break;
+	case PERIPH_ID_I2C10:
+		s5p_gpio_cfg_pin(&gpio1->b4, 0, GPIO_FUNC(0x2));
+		s5p_gpio_cfg_pin(&gpio1->b4, 1, GPIO_FUNC(0x2));
+		break;
+	}
+}
+
 static void exynos5_i2s_config(int peripheral)
 {
 	int i;
@@ -279,6 +446,58 @@ void exynos5_spi_config(int peripheral)
 	}
 }
 
+void exynos5420_spi_config(int peripheral)
+{
+	int cfg, pin, i;
+	struct s5p_gpio_bank *bank = NULL;
+	struct exynos5420_gpio_part1 *gpio1 =
+		(struct exynos5420_gpio_part1 *)samsung_get_base_gpio_part1();
+	struct exynos5420_gpio_part4 *gpio4 =
+		(struct exynos5420_gpio_part4 *)samsung_get_base_gpio_part4();
+
+	switch (peripheral) {
+	case PERIPH_ID_SPI0:
+		bank = &gpio1->a2;
+		cfg = GPIO_FUNC(0x2);
+		pin = 0;
+		break;
+	case PERIPH_ID_SPI1:
+		bank = &gpio1->a2;
+		cfg = GPIO_FUNC(0x2);
+		pin = 4;
+		break;
+	case PERIPH_ID_SPI2:
+		bank = &gpio1->b1;
+		cfg = GPIO_FUNC(0x5);
+		pin = 1;
+		break;
+	case PERIPH_ID_SPI3:
+		bank = &gpio4->f1;
+		cfg = GPIO_FUNC(0x2);
+		pin = 0;
+		break;
+	case PERIPH_ID_SPI4:
+		cfg = 0;
+		pin = 0;
+		break;
+	default:
+		cfg = 0;
+		pin = 0;
+		debug("%s: invalid peripheral %d", __func__, peripheral);
+		return;
+	}
+
+	if (peripheral != PERIPH_ID_SPI4) {
+		for (i = pin; i < pin + 4; i++)
+			s5p_gpio_cfg_pin(bank, i, cfg);
+	} else {
+		for (i = 0; i < 2; i++) {
+			s5p_gpio_cfg_pin(&gpio4->f0, i + 2, GPIO_FUNC(0x4));
+			s5p_gpio_cfg_pin(&gpio4->e0, i + 4, GPIO_FUNC(0x4));
+		}
+	}
+}
+
 static int exynos5_pinmux_config(int peripheral, int flags)
 {
 	switch (peripheral) {
@@ -325,6 +544,48 @@ static int exynos5_pinmux_config(int peripheral, int flags)
 	return 0;
 }
 
+static int exynos5420_pinmux_config(int peripheral, int flags)
+{
+	switch (peripheral) {
+	case PERIPH_ID_UART0:
+	case PERIPH_ID_UART1:
+	case PERIPH_ID_UART2:
+	case PERIPH_ID_UART3:
+		exynos5420_uart_config(peripheral);
+		break;
+	case PERIPH_ID_SDMMC0:
+	case PERIPH_ID_SDMMC1:
+	case PERIPH_ID_SDMMC2:
+	case PERIPH_ID_SDMMC3:
+		return exynos5420_mmc_config(peripheral, flags);
+	case PERIPH_ID_SPI0:
+	case PERIPH_ID_SPI1:
+	case PERIPH_ID_SPI2:
+	case PERIPH_ID_SPI3:
+	case PERIPH_ID_SPI4:
+		exynos5420_spi_config(peripheral);
+		break;
+	case PERIPH_ID_I2C0:
+	case PERIPH_ID_I2C1:
+	case PERIPH_ID_I2C2:
+	case PERIPH_ID_I2C3:
+	case PERIPH_ID_I2C4:
+	case PERIPH_ID_I2C5:
+	case PERIPH_ID_I2C6:
+	case PERIPH_ID_I2C7:
+	case PERIPH_ID_I2C8:
+	case PERIPH_ID_I2C9:
+	case PERIPH_ID_I2C10:
+		exynos5420_i2c_config(peripheral);
+		break;
+	default:
+		debug("%s: invalid peripheral %d", __func__, peripheral);
+		return -1;
+	}
+
+	return 0;
+}
+
 static void exynos4_i2c_config(int peripheral, int flags)
 {
 	struct exynos4_gpio_part1 *gpio1 =
@@ -431,6 +692,9 @@ static void exynos4_uart_config(int peripheral)
 		start = 4;
 		count = 2;
 		break;
+	default:
+		debug("%s: invalid peripheral %d", __func__, peripheral);
+		return;
 	}
 	for (i = start; i < start + count; i++) {
 		s5p_gpio_set_pull(bank, i, GPIO_PULL_NONE);
@@ -462,7 +726,7 @@ static int exynos4_pinmux_config(int peripheral, int flags)
 	case PERIPH_ID_SDMMC1:
 	case PERIPH_ID_SDMMC3:
 	case PERIPH_ID_SDMMC4:
-		printf("SDMMC device %d not implemented\n", peripheral);
+		debug("SDMMC device %d not implemented\n", peripheral);
 		return -1;
 	default:
 		debug("%s: invalid peripheral %d", __func__, peripheral);
@@ -475,16 +739,35 @@ static int exynos4_pinmux_config(int peripheral, int flags)
 int exynos_pinmux_config(int peripheral, int flags)
 {
 	if (cpu_is_exynos5()) {
-		return exynos5_pinmux_config(peripheral, flags);
+		if (proid_is_exynos5420())
+			return exynos5420_pinmux_config(peripheral, flags);
+		else if (proid_is_exynos5250())
+			return exynos5_pinmux_config(peripheral, flags);
 	} else if (cpu_is_exynos4()) {
 		return exynos4_pinmux_config(peripheral, flags);
 	} else {
 		debug("pinmux functionality not supported\n");
-		return -1;
 	}
+
+	return -1;
 }
 
 #ifdef CONFIG_OF_CONTROL
+static int exynos4_pinmux_decode_periph_id(const void *blob, int node)
+{
+	int err;
+	u32 cell[3];
+
+	err = fdtdec_get_int_array(blob, node, "interrupts", cell,
+					ARRAY_SIZE(cell));
+	if (err) {
+		debug(" invalid peripheral id\n");
+		return PERIPH_ID_NONE;
+	}
+
+	return cell[1];
+}
+
 static int exynos5_pinmux_decode_periph_id(const void *blob, int node)
 {
 	int err;
@@ -495,18 +778,15 @@ static int exynos5_pinmux_decode_periph_id(const void *blob, int node)
 	if (err)
 		return PERIPH_ID_NONE;
 
-	/* check for invalid peripheral id */
-	if ((PERIPH_ID_SDMMC4 > cell[1]) || (cell[1] < PERIPH_ID_UART0))
-		return cell[1];
-
-	debug(" invalid peripheral id\n");
-	return PERIPH_ID_NONE;
+	return cell[1];
 }
 
 int pinmux_decode_periph_id(const void *blob, int node)
 {
 	if (cpu_is_exynos5())
 		return  exynos5_pinmux_decode_periph_id(blob, node);
+	else if (cpu_is_exynos4())
+		return  exynos4_pinmux_decode_periph_id(blob, node);
 	else
 		return PERIPH_ID_NONE;
 }
diff --git a/arch/arm/cpu/armv7/exynos/power.c b/arch/arm/cpu/armv7/exynos/power.c
index 517e804f34..563abd750f 100644
--- a/arch/arm/cpu/armv7/exynos/power.c
+++ b/arch/arm/cpu/armv7/exynos/power.c
@@ -59,6 +59,28 @@ void set_usbhost_phy_ctrl(unsigned int enable)
 		exynos5_set_usbhost_phy_ctrl(enable);
 }
 
+static void exynos5_set_usbdrd_phy_ctrl(unsigned int enable)
+{
+	struct exynos5_power *power =
+		(struct exynos5_power *)samsung_get_base_power();
+
+	if (enable) {
+		/* Enabling USBDRD_PHY */
+		setbits_le32(&power->usbdrd_phy_control,
+				POWER_USB_DRD_PHY_CTRL_EN);
+	} else {
+		/* Disabling USBDRD_PHY */
+		clrbits_le32(&power->usbdrd_phy_control,
+				POWER_USB_DRD_PHY_CTRL_EN);
+	}
+}
+
+void set_usbdrd_phy_ctrl(unsigned int enable)
+{
+	if (cpu_is_exynos5())
+		exynos5_set_usbdrd_phy_ctrl(enable);
+}
+
 static void exynos5_dp_phy_control(unsigned int enable)
 {
 	unsigned int cfg;
diff --git a/arch/arm/cpu/armv7/exynos/spl_boot.c b/arch/arm/cpu/armv7/exynos/spl_boot.c
index 3651c00859..ade45fd5d3 100644
--- a/arch/arm/cpu/armv7/exynos/spl_boot.c
+++ b/arch/arm/cpu/armv7/exynos/spl_boot.c
@@ -10,8 +10,11 @@
 #include <asm/arch/clock.h>
 #include <asm/arch/clk.h>
 #include <asm/arch/dmc.h>
+#include <asm/arch/periph.h>
+#include <asm/arch/pinmux.h>
 #include <asm/arch/power.h>
 #include <asm/arch/spl.h>
+#include <asm/arch/spi.h>
 
 #include "common_setup.h"
 #include "clock_init.h"
@@ -59,6 +62,121 @@ static int config_branch_prediction(int set_cr_z)
 }
 #endif
 
+#ifdef CONFIG_SPI_BOOTING
+static void spi_rx_tx(struct exynos_spi *regs, int todo,
+			void *dinp, void const *doutp, int i)
+{
+	uint *rxp = (uint *)(dinp + (i * (32 * 1024)));
+	int rx_lvl, tx_lvl;
+	uint out_bytes, in_bytes;
+
+	out_bytes = todo;
+	in_bytes = todo;
+	setbits_le32(&regs->ch_cfg, SPI_CH_RST);
+	clrbits_le32(&regs->ch_cfg, SPI_CH_RST);
+	writel(((todo * 8) / 32) | SPI_PACKET_CNT_EN, &regs->pkt_cnt);
+
+	while (in_bytes) {
+		uint32_t spi_sts;
+		int temp;
+
+		spi_sts = readl(&regs->spi_sts);
+		rx_lvl = ((spi_sts >> 15) & 0x7f);
+		tx_lvl = ((spi_sts >> 6) & 0x7f);
+		while (tx_lvl < 32 && out_bytes) {
+			temp = 0xffffffff;
+			writel(temp, &regs->tx_data);
+			out_bytes -= 4;
+			tx_lvl += 4;
+		}
+		while (rx_lvl >= 4 && in_bytes) {
+			temp = readl(&regs->rx_data);
+			if (rxp)
+				*rxp++ = temp;
+			in_bytes -= 4;
+			rx_lvl -= 4;
+		}
+	}
+}
+
+/*
+ * Copy uboot from spi flash to RAM
+ *
+ * @parma uboot_size	size of u-boot to copy
+ * @param uboot_addr	address in u-boot to copy
+ */
+static void exynos_spi_copy(unsigned int uboot_size, unsigned int uboot_addr)
+{
+	int upto, todo;
+	int i, timeout = 100;
+	struct exynos_spi *regs = (struct exynos_spi *)CONFIG_ENV_SPI_BASE;
+
+	set_spi_clk(PERIPH_ID_SPI1, 50000000); /* set spi clock to 50Mhz */
+	/* set the spi1 GPIO */
+	exynos_pinmux_config(PERIPH_ID_SPI1, PINMUX_FLAG_NONE);
+
+	/* set pktcnt and enable it */
+	writel(4 | SPI_PACKET_CNT_EN, &regs->pkt_cnt);
+	/* set FB_CLK_SEL */
+	writel(SPI_FB_DELAY_180, &regs->fb_clk);
+	/* set CH_WIDTH and BUS_WIDTH as word */
+	setbits_le32(&regs->mode_cfg, SPI_MODE_CH_WIDTH_WORD |
+					SPI_MODE_BUS_WIDTH_WORD);
+	clrbits_le32(&regs->ch_cfg, SPI_CH_CPOL_L); /* CPOL: active high */
+
+	/* clear rx and tx channel if set priveously */
+	clrbits_le32(&regs->ch_cfg, SPI_RX_CH_ON | SPI_TX_CH_ON);
+
+	setbits_le32(&regs->swap_cfg, SPI_RX_SWAP_EN |
+			SPI_RX_BYTE_SWAP |
+			SPI_RX_HWORD_SWAP);
+
+	/* do a soft reset */
+	setbits_le32(&regs->ch_cfg, SPI_CH_RST);
+	clrbits_le32(&regs->ch_cfg, SPI_CH_RST);
+
+	/* now set rx and tx channel ON */
+	setbits_le32(&regs->ch_cfg, SPI_RX_CH_ON | SPI_TX_CH_ON | SPI_CH_HS_EN);
+	clrbits_le32(&regs->cs_reg, SPI_SLAVE_SIG_INACT); /* CS low */
+
+	/* Send read instruction (0x3h) followed by a 24 bit addr */
+	writel((SF_READ_DATA_CMD << 24) | SPI_FLASH_UBOOT_POS, &regs->tx_data);
+
+	/* waiting for TX done */
+	while (!(readl(&regs->spi_sts) & SPI_ST_TX_DONE)) {
+		if (!timeout) {
+			debug("SPI TIMEOUT\n");
+			break;
+		}
+		timeout--;
+	}
+
+	for (upto = 0, i = 0; upto < uboot_size; upto += todo, i++) {
+		todo = min(uboot_size - upto, (1 << 15));
+		spi_rx_tx(regs, todo, (void *)(uboot_addr),
+			  (void *)(SPI_FLASH_UBOOT_POS), i);
+	}
+
+	setbits_le32(&regs->cs_reg, SPI_SLAVE_SIG_INACT);/* make the CS high */
+
+	/*
+	 * Let put controller mode to BYTE as
+	 * SPI driver does not support WORD mode yet
+	 */
+	clrbits_le32(&regs->mode_cfg, SPI_MODE_CH_WIDTH_WORD |
+					SPI_MODE_BUS_WIDTH_WORD);
+	writel(0, &regs->swap_cfg);
+
+	/*
+	 * Flush spi tx, rx fifos and reset the SPI controller
+	 * and clear rx/tx channel
+	 */
+	clrsetbits_le32(&regs->ch_cfg, SPI_CH_HS_EN, SPI_CH_RST);
+	clrbits_le32(&regs->ch_cfg, SPI_CH_RST);
+	clrbits_le32(&regs->ch_cfg, SPI_TX_CH_ON | SPI_RX_CH_ON);
+}
+#endif
+
 /*
 * Copy U-boot from mmc to RAM:
 * COPY_BL2_FNPTR_ADDR: Address in iRAM, which Contains
@@ -70,6 +188,9 @@ void copy_uboot_to_ram(void)
 
 	u32 (*copy_bl2)(u32 offset, u32 nblock, u32 dst) = NULL;
 	u32 offset = 0, size = 0;
+#ifdef CONFIG_SPI_BOOTING
+	struct spl_machine_param *param = spl_get_machine_params();
+#endif
 #ifdef CONFIG_SUPPORT_EMMC_BOOT
 	u32 (*copy_bl2_from_emmc)(u32 nblock, u32 dst);
 	void (*end_bootop_from_emmc)(void);
@@ -91,9 +212,8 @@ void copy_uboot_to_ram(void)
 	switch (bootmode) {
 #ifdef CONFIG_SPI_BOOTING
 	case BOOT_MODE_SERIAL:
-		offset = SPI_FLASH_UBOOT_POS;
-		size = CONFIG_BL2_SIZE;
-		copy_bl2 = get_irom_func(SPI_INDEX);
+		/* Customised function to copy u-boot from SF */
+		exynos_spi_copy(param->uboot_size, CONFIG_SYS_TEXT_BASE);
 		break;
 #endif
 	case BOOT_MODE_MMC:
diff --git a/arch/arm/cpu/armv7/highbank/Makefile b/arch/arm/cpu/armv7/highbank/Makefile
index 22e3b72c8b..876099d9a1 100644
--- a/arch/arm/cpu/armv7/highbank/Makefile
+++ b/arch/arm/cpu/armv7/highbank/Makefile
@@ -5,26 +5,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(SOC).o
-
-COBJS	:= timer.o
-SOBJS	:=
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS) $(SOBJS))
-
-all:	$(obj).depend $(LIB)
-
-$(LIB):	$(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	:= timer.o
diff --git a/arch/arm/cpu/armv7/highbank/timer.c b/arch/arm/cpu/armv7/highbank/timer.c
index b61cd69bc6..d56bf21133 100644
--- a/arch/arm/cpu/armv7/highbank/timer.c
+++ b/arch/arm/cpu/armv7/highbank/timer.c
@@ -7,18 +7,12 @@
  */
 
 #include <common.h>
-#include <div64.h>
-#include <linux/types.h>        /* for size_t */
-#include <linux/stddef.h>       /* for NULL */
 #include <asm/io.h>
 #include <asm/arch-armv7/systimer.h>
 
 #undef SYSTIMER_BASE
 #define SYSTIMER_BASE		0xFFF34000	/* Timer 0 and 1 base	*/
-#define SYSTIMER_RATE		(150000000 / 256)
 
-static ulong timestamp;
-static ulong lastinc;
 static struct systimer *systimer_base = (struct systimer *)SYSTIMER_BASE;
 
 /*
@@ -38,80 +32,3 @@ int timer_init(void)
 	return 0;
 
 }
-
-#define TICK_PER_TIME	((SYSTIMER_RATE + CONFIG_SYS_HZ / 2) / CONFIG_SYS_HZ)
-#define NS_PER_TICK	(1000000000 / SYSTIMER_RATE)
-
-static inline unsigned long long tick_to_time(unsigned long long tick)
-{
-	do_div(tick, TICK_PER_TIME);
-	return tick;
-}
-
-static inline unsigned long long time_to_tick(unsigned long long time)
-{
-	return time * TICK_PER_TIME;
-}
-
-static inline unsigned long long us_to_tick(unsigned long long us)
-{
-	unsigned long long tick = us * 1000;
-	tick += NS_PER_TICK - 1;
-	do_div(tick, NS_PER_TICK);
-	return tick;
-}
-
-unsigned long long get_ticks(void)
-{
-	ulong now = ~readl(&systimer_base->timer0value);
-
-	if (now >= lastinc)	/* normal mode (non roll) */
-		/* move stamp forward with absolut diff ticks */
-		timestamp += (now - lastinc);
-	else			/* we have rollover of incrementer */
-		timestamp += (0xFFFFFFFF - lastinc) + now;
-	lastinc = now;
-	return timestamp;
-}
-
-/*
- * Delay x useconds AND preserve advance timstamp value
- *     assumes timer is ticking at 1 msec
- */
-void __udelay(ulong usec)
-{
-	unsigned long long tmp;
-	ulong tmo;
-
-	tmo = us_to_tick(usec);
-	tmp = get_ticks() + tmo;	/* get current timestamp */
-
-	while (get_ticks() < tmp)	/* loop till event */
-		 /*NOP*/;
-}
-
-ulong get_timer(ulong base)
-{
-	return get_timer_masked() - base;
-}
-
-void reset_timer_masked(void)
-{
-	lastinc = ~readl(&systimer_base->timer0value);
-	timestamp = 0;
-}
-
-void reset_timer(void)
-{
-	reset_timer_masked();
-}
-
-ulong get_timer_masked(void)
-{
-	return tick_to_time(get_ticks());
-}
-
-ulong get_tbclk(void)
-{
-	return SYSTIMER_RATE;
-}
diff --git a/arch/arm/cpu/armv7/kona-common/Makefile b/arch/arm/cpu/armv7/kona-common/Makefile
new file mode 100644
index 0000000000..da225cb4f7
--- /dev/null
+++ b/arch/arm/cpu/armv7/kona-common/Makefile
@@ -0,0 +1,9 @@
+#
+# Copyright 2013 Broadcom Corporation.
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y	+= s_init.o
+obj-y	+= hwinit-common.o
+obj-y	+= clk-stubs.o
diff --git a/arch/arm/cpu/armv7/kona-common/clk-stubs.c b/arch/arm/cpu/armv7/kona-common/clk-stubs.c
new file mode 100644
index 0000000000..338e0e4962
--- /dev/null
+++ b/arch/arm/cpu/armv7/kona-common/clk-stubs.c
@@ -0,0 +1,21 @@
+/*
+ * Copyright 2013 Broadcom Corporation.
+ *
+ * SPDX-License-Identifier:      GPL-2.0+
+ */
+
+#include <common.h>
+
+/*
+ * These weak functions are available to kona architectures that don't
+ * require clock enables from the driver code.
+ */
+int __weak clk_sdio_enable(void *base, u32 rate, u32 *actual_ratep)
+{
+	return 0;
+}
+
+int __weak clk_bsc_enable(void *base, u32 rate, u32 *actual_ratep)
+{
+	return 0;
+}
diff --git a/arch/arm/cpu/armv7/kona-common/hwinit-common.c b/arch/arm/cpu/armv7/kona-common/hwinit-common.c
new file mode 100644
index 0000000000..2b3a84051c
--- /dev/null
+++ b/arch/arm/cpu/armv7/kona-common/hwinit-common.c
@@ -0,0 +1,16 @@
+/*
+ * Copyright 2013 Broadcom Corporation.
+ *
+ * SPDX-License-Identifier:      GPL-2.0+
+ */
+
+#include <common.h>
+#include <linux/sizes.h>
+
+#ifndef CONFIG_SYS_DCACHE_OFF
+void enable_caches(void)
+{
+	/* Enable D-cache. I-cache is already enabled in start.S */
+	dcache_enable();
+}
+#endif
diff --git a/arch/arm/cpu/armv7/kona-common/s_init.c b/arch/arm/cpu/armv7/kona-common/s_init.c
new file mode 100644
index 0000000000..6066a73c54
--- /dev/null
+++ b/arch/arm/cpu/armv7/kona-common/s_init.c
@@ -0,0 +1,12 @@
+/*
+ * Copyright 2014 Broadcom Corporation.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * Early system init. Currently empty.
+ */
+void s_init(void)
+{
+}
diff --git a/arch/arm/cpu/armv7/lowlevel_init.S b/arch/arm/cpu/armv7/lowlevel_init.S
index 69e3053a42..f1aea05c90 100644
--- a/arch/arm/cpu/armv7/lowlevel_init.S
+++ b/arch/arm/cpu/armv7/lowlevel_init.S
@@ -24,7 +24,7 @@ ENTRY(lowlevel_init)
 #ifdef CONFIG_SPL_BUILD
 	ldr	r9, =gdata
 #else
-	sub	sp, #GD_SIZE
+	sub	sp, sp, #GD_SIZE
 	bic	sp, sp, #7
 	mov	r9, sp
 #endif
diff --git a/arch/arm/cpu/armv7/mx5/Makefile b/arch/arm/cpu/armv7/mx5/Makefile
index 7c86ae3ea5..d021842f68 100644
--- a/arch/arm/cpu/armv7/mx5/Makefile
+++ b/arch/arm/cpu/armv7/mx5/Makefile
@@ -7,26 +7,5 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(SOC).o
-
-COBJS	= soc.o clock.o
-SOBJS = lowlevel_init.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS))
-
-all:	$(obj).depend $(LIB)
-
-$(LIB):	$(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y := soc.o clock.o
+obj-y += lowlevel_init.o
diff --git a/arch/arm/cpu/armv7/mx5/asm-offsets.c b/arch/arm/cpu/armv7/mx5/asm-offsets.c
deleted file mode 100644
index ddb1898f36..0000000000
--- a/arch/arm/cpu/armv7/mx5/asm-offsets.c
+++ /dev/null
@@ -1,73 +0,0 @@
-/*
- * Adapted from Linux v2.6.36 kernel: arch/powerpc/kernel/asm-offsets.c
- *
- * This program is used to generate definitions needed by
- * assembly language modules.
- *
- * We use the technique used in the OSF Mach kernel code:
- * generate asm statements containing #defines,
- * compile this file to assembler, and then extract the
- * #defines from the assembly-language output.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/arch/imx-regs.h>
-
-#include <linux/kbuild.h>
-
-int main(void)
-{
-
-	/* Round up to make sure size gives nice stack alignment */
-	DEFINE(CLKCTL_CCMR, offsetof(struct clkctl, ccr));
-	DEFINE(CLKCTL_CCDR, offsetof(struct clkctl, ccdr));
-	DEFINE(CLKCTL_CSR, offsetof(struct clkctl, csr));
-	DEFINE(CLKCTL_CCSR, offsetof(struct clkctl, ccsr));
-	DEFINE(CLKCTL_CACRR, offsetof(struct clkctl, cacrr));
-	DEFINE(CLKCTL_CBCDR, offsetof(struct clkctl, cbcdr));
-	DEFINE(CLKCTL_CBCMR, offsetof(struct clkctl, cbcmr));
-	DEFINE(CLKCTL_CSCMR1, offsetof(struct clkctl, cscmr1));
-	DEFINE(CLKCTL_CSCMR2, offsetof(struct clkctl, cscmr2));
-	DEFINE(CLKCTL_CSCDR1, offsetof(struct clkctl, cscdr1));
-	DEFINE(CLKCTL_CS1CDR, offsetof(struct clkctl, cs1cdr));
-	DEFINE(CLKCTL_CS2CDR, offsetof(struct clkctl, cs2cdr));
-	DEFINE(CLKCTL_CDCDR, offsetof(struct clkctl, cdcdr));
-	DEFINE(CLKCTL_CHSCCDR, offsetof(struct clkctl, chsccdr));
-	DEFINE(CLKCTL_CSCDR2, offsetof(struct clkctl, cscdr2));
-	DEFINE(CLKCTL_CSCDR3, offsetof(struct clkctl, cscdr3));
-	DEFINE(CLKCTL_CSCDR4, offsetof(struct clkctl, cscdr4));
-	DEFINE(CLKCTL_CWDR, offsetof(struct clkctl, cwdr));
-	DEFINE(CLKCTL_CDHIPR, offsetof(struct clkctl, cdhipr));
-	DEFINE(CLKCTL_CDCR, offsetof(struct clkctl, cdcr));
-	DEFINE(CLKCTL_CTOR, offsetof(struct clkctl, ctor));
-	DEFINE(CLKCTL_CLPCR, offsetof(struct clkctl, clpcr));
-	DEFINE(CLKCTL_CISR, offsetof(struct clkctl, cisr));
-	DEFINE(CLKCTL_CIMR, offsetof(struct clkctl, cimr));
-	DEFINE(CLKCTL_CCOSR, offsetof(struct clkctl, ccosr));
-	DEFINE(CLKCTL_CGPR, offsetof(struct clkctl, cgpr));
-	DEFINE(CLKCTL_CCGR0, offsetof(struct clkctl, ccgr0));
-	DEFINE(CLKCTL_CCGR1, offsetof(struct clkctl, ccgr1));
-	DEFINE(CLKCTL_CCGR2, offsetof(struct clkctl, ccgr2));
-	DEFINE(CLKCTL_CCGR3, offsetof(struct clkctl, ccgr3));
-	DEFINE(CLKCTL_CCGR4, offsetof(struct clkctl, ccgr4));
-	DEFINE(CLKCTL_CCGR5, offsetof(struct clkctl, ccgr5));
-	DEFINE(CLKCTL_CCGR6, offsetof(struct clkctl, ccgr6));
-	DEFINE(CLKCTL_CMEOR, offsetof(struct clkctl, cmeor));
-#if defined(CONFIG_MX53)
-	DEFINE(CLKCTL_CCGR7, offsetof(struct clkctl, ccgr7));
-#endif
-
-	/* DPLL */
-	DEFINE(PLL_DP_CTL, offsetof(struct dpll, dp_ctl));
-	DEFINE(PLL_DP_CONFIG, offsetof(struct dpll, dp_config));
-	DEFINE(PLL_DP_OP, offsetof(struct dpll, dp_op));
-	DEFINE(PLL_DP_MFD, offsetof(struct dpll, dp_mfd));
-	DEFINE(PLL_DP_MFN, offsetof(struct dpll, dp_mfn));
-	DEFINE(PLL_DP_HFS_OP, offsetof(struct dpll, dp_hfs_op));
-	DEFINE(PLL_DP_HFS_MFD, offsetof(struct dpll, dp_hfs_mfd));
-	DEFINE(PLL_DP_HFS_MFN, offsetof(struct dpll, dp_hfs_mfn));
-
-	return 0;
-}
diff --git a/arch/arm/cpu/armv7/mx5/clock.c b/arch/arm/cpu/armv7/mx5/clock.c
index 6bef254456..bf52f0d19e 100644
--- a/arch/arm/cpu/armv7/mx5/clock.c
+++ b/arch/arm/cpu/armv7/mx5/clock.c
@@ -94,7 +94,7 @@ void enable_usboh3_clk(bool enable)
 			MXC_CCM_CCGR2_USBOH3_60M(cg));
 }
 
-#ifdef CONFIG_I2C_MXC
+#ifdef CONFIG_SYS_I2C_MXC
 /* i2c_num can be from 0, to 1 for i.MX51 and 2 for i.MX53 */
 int enable_i2c_clk(unsigned char enable, unsigned i2c_num)
 {
@@ -749,6 +749,18 @@ void enable_nfc_clk(unsigned char enable)
 		MXC_CCM_CCGR5_EMI_ENFC(cg));
 }
 
+#ifdef CONFIG_FSL_IIM
+void enable_efuse_prog_supply(bool enable)
+{
+	if (enable)
+		setbits_le32(&mxc_ccm->cgpr,
+			     MXC_CCM_CGPR_EFUSE_PROG_SUPPLY_GATE);
+	else
+		clrbits_le32(&mxc_ccm->cgpr,
+			     MXC_CCM_CGPR_EFUSE_PROG_SUPPLY_GATE);
+}
+#endif
+
 /* Config main_bus_clock for periphs */
 static int config_periph_clk(u32 ref, u32 freq)
 {
diff --git a/arch/arm/cpu/armv7/mx5/lowlevel_init.S b/arch/arm/cpu/armv7/mx5/lowlevel_init.S
index 25fadf6487..f5bc6728b7 100644
--- a/arch/arm/cpu/armv7/mx5/lowlevel_init.S
+++ b/arch/arm/cpu/armv7/mx5/lowlevel_init.S
@@ -45,6 +45,12 @@
 #endif
 
 	mcr 15, 1, r0, c9, c0, 2
+
+	/* enable L2 cache */
+	mrc 15, 0, r0, c1, c0, 1
+	orr r0, r0, #2
+	mcr 15, 0, r0, c1, c0, 1
+
 .endm /* init_l2cc */
 
 /* AIPS setup - Only setup MPROTx registers.
@@ -369,12 +375,6 @@ setup_pll_func:
 #endif	/* CONFIG_MX53 */
 .endm
 
-.macro setup_wdog
-	ldr r0, =WDOG1_BASE_ADDR
-	mov r1, #0x30
-	strh r1, [r0]
-.endm
-
 ENTRY(lowlevel_init)
 	mov r10, lr
 	mov r4, #0	/* Fix R4 to 0 */
diff --git a/arch/arm/cpu/armv7/mx6/Makefile b/arch/arm/cpu/armv7/mx6/Makefile
index 6d736174db..d7285fc2cc 100644
--- a/arch/arm/cpu/armv7/mx6/Makefile
+++ b/arch/arm/cpu/armv7/mx6/Makefile
@@ -7,26 +7,5 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(SOC).o
-
-COBJS-y	= soc.o clock.o
-COBJS-$(CONFIG_SECURE_BOOT)	+= hab.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
-OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS-y))
-
-all:	$(obj).depend $(LIB)
-
-$(LIB):	$(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	:= soc.o clock.o
+obj-$(CONFIG_SECURE_BOOT)    += hab.o
diff --git a/arch/arm/cpu/armv7/mx6/clock.c b/arch/arm/cpu/armv7/mx6/clock.c
index df11678609..bd65a08ba2 100644
--- a/arch/arm/cpu/armv7/mx6/clock.c
+++ b/arch/arm/cpu/armv7/mx6/clock.c
@@ -5,6 +5,7 @@
  */
 
 #include <common.h>
+#include <div64.h>
 #include <asm/io.h>
 #include <asm/errno.h>
 #include <asm/arch/imx-regs.h>
@@ -48,7 +49,7 @@ void enable_usboh3_clk(unsigned char enable)
 
 }
 
-#ifdef CONFIG_I2C_MXC
+#ifdef CONFIG_SYS_I2C_MXC
 /* i2c_num can be from 0 - 2 */
 int enable_i2c_clk(unsigned char enable, unsigned i2c_num)
 {
@@ -94,12 +95,38 @@ static u32 decode_pll(enum pll_clocks pll, u32 infreq)
 		div = __raw_readl(&imx_ccm->analog_pll_enet);
 		div &= BM_ANADIG_PLL_ENET_DIV_SELECT;
 
-		return (div == 3 ? 125000000 : 25000000 * (div << 1));
+		return 25000000 * (div + (div >> 1) + 1);
 	default:
 		return 0;
 	}
 	/* NOTREACHED */
 }
+static u32 mxc_get_pll_pfd(enum pll_clocks pll, int pfd_num)
+{
+	u32 div;
+	u64 freq;
+
+	switch (pll) {
+	case PLL_BUS:
+		if (pfd_num == 3) {
+			/* No PFD3 on PPL2 */
+			return 0;
+		}
+		div = __raw_readl(&imx_ccm->analog_pfd_528);
+		freq = (u64)decode_pll(PLL_BUS, MXC_HCLK);
+		break;
+	case PLL_USBOTG:
+		div = __raw_readl(&imx_ccm->analog_pfd_480);
+		freq = (u64)decode_pll(PLL_USBOTG, MXC_HCLK);
+		break;
+	default:
+		/* No PFD on other PLL					     */
+		return 0;
+	}
+
+	return lldiv(freq * 18, (div & ANATOP_PFD_FRAC_MASK(pfd_num)) >>
+			      ANATOP_PFD_FRAC_SHIFT(pfd_num));
+}
 
 static u32 get_mcu_main_clk(void)
 {
@@ -144,13 +171,14 @@ u32 get_periph_clk(void)
 			freq = decode_pll(PLL_BUS, MXC_HCLK);
 			break;
 		case 1:
-			freq = PLL2_PFD2_FREQ;
+			freq = mxc_get_pll_pfd(PLL_BUS, 2);
 			break;
 		case 2:
-			freq = PLL2_PFD0_FREQ;
+			freq = mxc_get_pll_pfd(PLL_BUS, 0);
 			break;
 		case 3:
-			freq = PLL2_PFD2_DIV_FREQ;
+			/* static / 2 divider */
+			freq = mxc_get_pll_pfd(PLL_BUS, 2) / 2;
 			break;
 		default:
 			break;
@@ -184,7 +212,7 @@ static u32 get_ipg_per_clk(void)
 static u32 get_uart_clk(void)
 {
 	u32 reg, uart_podf;
-	u32 freq = PLL3_80M;
+	u32 freq = decode_pll(PLL_USBOTG, MXC_HCLK) / 6; /* static divider */
 	reg = __raw_readl(&imx_ccm->cscdr1);
 #ifdef CONFIG_MX6SL
 	if (reg & MXC_CCM_CSCDR1_UART_CLK_SEL)
@@ -204,7 +232,7 @@ static u32 get_cspi_clk(void)
 	reg &= MXC_CCM_CSCDR2_ECSPI_CLK_PODF_MASK;
 	cspi_podf = reg >> MXC_CCM_CSCDR2_ECSPI_CLK_PODF_OFFSET;
 
-	return	PLL3_60M / (cspi_podf + 1);
+	return	decode_pll(PLL_USBOTG, MXC_HCLK) / (8 * (cspi_podf + 1));
 }
 
 static u32 get_axi_clk(void)
@@ -217,9 +245,9 @@ static u32 get_axi_clk(void)
 
 	if (cbcdr & MXC_CCM_CBCDR_AXI_SEL) {
 		if (cbcdr & MXC_CCM_CBCDR_AXI_ALT_SEL)
-			root_freq = PLL2_PFD2_FREQ;
+			root_freq = mxc_get_pll_pfd(PLL_BUS, 2);
 		else
-			root_freq = PLL3_PFD1_FREQ;
+			root_freq = mxc_get_pll_pfd(PLL_USBOTG, 1);
 	} else
 		root_freq = get_periph_clk();
 
@@ -244,10 +272,10 @@ static u32 get_emi_slow_clk(void)
 		root_freq = decode_pll(PLL_USBOTG, MXC_HCLK);
 		break;
 	case 2:
-		root_freq = PLL2_PFD2_FREQ;
+		root_freq =  mxc_get_pll_pfd(PLL_BUS, 2);
 		break;
 	case 3:
-		root_freq = PLL2_PFD0_FREQ;
+		root_freq =  mxc_get_pll_pfd(PLL_BUS, 0);
 		break;
 	}
 
@@ -270,20 +298,32 @@ static u32 get_mmdc_ch0_clk(void)
 		freq = decode_pll(PLL_BUS, MXC_HCLK);
 		break;
 	case 1:
-		freq = PLL2_PFD2_FREQ;
+		freq = mxc_get_pll_pfd(PLL_BUS, 2);
 		break;
 	case 2:
-		freq = PLL2_PFD0_FREQ;
+		freq = mxc_get_pll_pfd(PLL_BUS, 0);
 		break;
 	case 3:
-		freq = PLL2_PFD2_DIV_FREQ;
+		/* static / 2 divider */
+		freq =  mxc_get_pll_pfd(PLL_BUS, 2) / 2;
 	}
 
 	return freq / (podf + 1);
 
 }
+#else
+static u32 get_mmdc_ch0_clk(void)
+{
+	u32 cbcdr = __raw_readl(&imx_ccm->cbcdr);
+	u32 mmdc_ch0_podf = (cbcdr & MXC_CCM_CBCDR_MMDC_CH0_PODF_MASK) >>
+				MXC_CCM_CBCDR_MMDC_CH0_PODF_OFFSET;
+
+	return get_periph_clk() / (mmdc_ch0_podf + 1);
+}
+#endif
 
-int enable_fec_anatop_clock(void)
+#ifdef CONFIG_FEC_MXC
+int enable_fec_anatop_clock(enum enet_freq freq)
 {
 	u32 reg = 0;
 	s32 timeout = 100000;
@@ -291,7 +331,13 @@ int enable_fec_anatop_clock(void)
 	struct anatop_regs __iomem *anatop =
 		(struct anatop_regs __iomem *)ANATOP_BASE_ADDR;
 
+	if (freq < ENET_25MHz || freq > ENET_125MHz)
+		return -EINVAL;
+
 	reg = readl(&anatop->pll_enet);
+	reg &= ~BM_ANADIG_PLL_ENET_DIV_SELECT;
+	reg |= freq;
+
 	if ((reg & BM_ANADIG_PLL_ENET_POWERDOWN) ||
 	    (!(reg & BM_ANADIG_PLL_ENET_LOCK))) {
 		reg &= ~BM_ANADIG_PLL_ENET_POWERDOWN;
@@ -311,16 +357,6 @@ int enable_fec_anatop_clock(void)
 
 	return 0;
 }
-
-#else
-static u32 get_mmdc_ch0_clk(void)
-{
-	u32 cbcdr = __raw_readl(&imx_ccm->cbcdr);
-	u32 mmdc_ch0_podf = (cbcdr & MXC_CCM_CBCDR_MMDC_CH0_PODF_MASK) >>
-				MXC_CCM_CBCDR_MMDC_CH0_PODF_OFFSET;
-
-	return get_periph_clk() / (mmdc_ch0_podf + 1);
-}
 #endif
 
 static u32 get_usdhc_clk(u32 port)
@@ -359,9 +395,9 @@ static u32 get_usdhc_clk(u32 port)
 	}
 
 	if (clk_sel)
-		root_freq = PLL2_PFD0_FREQ;
+		root_freq = mxc_get_pll_pfd(PLL_BUS, 0);
 	else
-		root_freq = PLL2_PFD2_FREQ;
+		root_freq = mxc_get_pll_pfd(PLL_BUS, 2);
 
 	return root_freq / (usdhc_podf + 1);
 }
@@ -373,20 +409,15 @@ u32 imx_get_uartclk(void)
 
 u32 imx_get_fecclk(void)
 {
-	return decode_pll(PLL_ENET, MXC_HCLK);
+	return mxc_get_clock(MXC_IPG_CLK);
 }
 
-int enable_sata_clock(void)
+static int enable_enet_pll(uint32_t en)
 {
-	u32 reg = 0;
-	s32 timeout = 100000;
 	struct mxc_ccm_reg *const imx_ccm
 		= (struct mxc_ccm_reg *) CCM_BASE_ADDR;
-
-	/* Enable sata clock */
-	reg = readl(&imx_ccm->CCGR5); /* CCGR5 */
-	reg |= MXC_CCM_CCGR5_SATA_MASK;
-	writel(reg, &imx_ccm->CCGR5);
+	s32 timeout = 100000;
+	u32 reg = 0;
 
 	/* Enable PLLs */
 	reg = readl(&imx_ccm->analog_pll_enet);
@@ -401,10 +432,70 @@ int enable_sata_clock(void)
 		return -EIO;
 	reg &= ~BM_ANADIG_PLL_SYS_BYPASS;
 	writel(reg, &imx_ccm->analog_pll_enet);
-	reg |= BM_ANADIG_PLL_ENET_ENABLE_SATA;
+	reg |= en;
 	writel(reg, &imx_ccm->analog_pll_enet);
+	return 0;
+}
+
+static void ungate_sata_clock(void)
+{
+	struct mxc_ccm_reg *const imx_ccm =
+		(struct mxc_ccm_reg *)CCM_BASE_ADDR;
+
+	/* Enable SATA clock. */
+	setbits_le32(&imx_ccm->CCGR5, MXC_CCM_CCGR5_SATA_MASK);
+}
+
+static void ungate_pcie_clock(void)
+{
+	struct mxc_ccm_reg *const imx_ccm =
+		(struct mxc_ccm_reg *)CCM_BASE_ADDR;
 
-	return 0 ;
+	/* Enable PCIe clock. */
+	setbits_le32(&imx_ccm->CCGR4, MXC_CCM_CCGR4_PCIE_MASK);
+}
+
+int enable_sata_clock(void)
+{
+	ungate_sata_clock();
+	return enable_enet_pll(BM_ANADIG_PLL_ENET_ENABLE_SATA);
+}
+
+int enable_pcie_clock(void)
+{
+	struct anatop_regs *anatop_regs =
+		(struct anatop_regs *)ANATOP_BASE_ADDR;
+	struct mxc_ccm_reg *ccm_regs = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+
+	/*
+	 * Here be dragons!
+	 *
+	 * The register ANATOP_MISC1 is not documented in the Freescale
+	 * MX6RM. The register that is mapped in the ANATOP space and
+	 * marked as ANATOP_MISC1 is actually documented in the PMU section
+	 * of the datasheet as PMU_MISC1.
+	 *
+	 * Switch LVDS clock source to SATA (0xb), disable clock INPUT and
+	 * enable clock OUTPUT. This is important for PCI express link that
+	 * is clocked from the i.MX6.
+	 */
+#define ANADIG_ANA_MISC1_LVDSCLK1_IBEN		(1 << 12)
+#define ANADIG_ANA_MISC1_LVDSCLK1_OBEN		(1 << 10)
+#define ANADIG_ANA_MISC1_LVDS1_CLK_SEL_MASK	0x0000001F
+	clrsetbits_le32(&anatop_regs->ana_misc1,
+			ANADIG_ANA_MISC1_LVDSCLK1_IBEN |
+			ANADIG_ANA_MISC1_LVDS1_CLK_SEL_MASK,
+			ANADIG_ANA_MISC1_LVDSCLK1_OBEN | 0xb);
+
+	/* PCIe reference clock sourced from AXI. */
+	clrbits_le32(&ccm_regs->cbcmr, MXC_CCM_CBCMR_PCIE_AXI_CLK_SEL);
+
+	/* Party time! Ungate the clock to the PCIe. */
+	ungate_sata_clock();
+	ungate_pcie_clock();
+
+	return enable_enet_pll(BM_ANADIG_PLL_ENET_ENABLE_SATA |
+			       BM_ANADIG_PLL_ENET_ENABLE_PCIE);
 }
 
 unsigned int mxc_get_clock(enum mxc_clock clk)
diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c
index a3902962b5..172527987d 100644
--- a/arch/arm/cpu/armv7/mx6/soc.c
+++ b/arch/arm/cpu/armv7/mx6/soc.c
@@ -8,6 +8,8 @@
  */
 
 #include <common.h>
+#include <asm/armv7.h>
+#include <asm/pl310.h>
 #include <asm/errno.h>
 #include <asm/io.h>
 #include <asm/arch/imx-regs.h>
@@ -19,6 +21,12 @@
 #include <asm/arch/mxc_hdmi.h>
 #include <asm/arch/crm_regs.h>
 
+enum ldo_reg {
+	LDO_ARM,
+	LDO_SOC,
+	LDO_PU,
+};
+
 struct scu_regs {
 	u32	ctrl;
 	u32	config;
@@ -35,14 +43,19 @@ u32 get_cpu_rev(void)
 
 	if (type != MXC_CPU_MX6SL) {
 		reg = readl(&anatop->digprog);
+		struct scu_regs *scu = (struct scu_regs *)SCU_BASE_ADDR;
+		u32 cfg = readl(&scu->config) & 3;
 		type = ((reg >> 16) & 0xff);
 		if (type == MXC_CPU_MX6DL) {
-			struct scu_regs *scu = (struct scu_regs *)SCU_BASE_ADDR;
-			u32 cfg = readl(&scu->config) & 3;
-
 			if (!cfg)
 				type = MXC_CPU_MX6SOLO;
 		}
+
+		if (type == MXC_CPU_MX6Q) {
+			if (cfg == 1)
+				type = MXC_CPU_MX6D;
+		}
+
 	}
 	reg &= 0xff;		/* mx6 silicon revision */
 	return (type << 12) | (reg + 0x10);
@@ -56,6 +69,9 @@ u32 __weak get_board_rev(void)
 	if (type == MXC_CPU_MX6SOLO)
 		cpurev = (MXC_CPU_MX6DL) << 12 | (cpurev & 0xFFF);
 
+	if (type == MXC_CPU_MX6D)
+		cpurev = (MXC_CPU_MX6Q) << 12 | (cpurev & 0xFFF);
+
 	return cpurev;
 }
 #endif
@@ -93,6 +109,20 @@ void init_aips(void)
 	writel(0x00000000, &aips2->opacr4);
 }
 
+static void clear_ldo_ramp(void)
+{
+	struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
+	int reg;
+
+	/* ROM may modify LDO ramp up time according to fuse setting, so in
+	 * order to be in the safe side we neeed to reset these settings to
+	 * match the reset value: 0'b00
+	 */
+	reg = readl(&anatop->ana_misc2);
+	reg &= ~(0x3f << 24);
+	writel(reg, &anatop->ana_misc2);
+}
+
 /*
  * Set the VDDSOC
  *
@@ -101,10 +131,11 @@ void init_aips(void)
  * Possible values are from 0.725V to 1.450V in steps of
  * 0.025V (25mV).
  */
-void set_vddsoc(u32 mv)
+static int set_ldo_voltage(enum ldo_reg ldo, u32 mv)
 {
 	struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
-	u32 val, reg = readl(&anatop->reg_core);
+	u32 val, step, old, reg = readl(&anatop->reg_core);
+	u8 shift;
 
 	if (mv < 725)
 		val = 0x00;	/* Power gated off */
@@ -113,12 +144,37 @@ void set_vddsoc(u32 mv)
 	else
 		val = (mv - 700) / 25;
 
+	clear_ldo_ramp();
+
+	switch (ldo) {
+	case LDO_SOC:
+		shift = 18;
+		break;
+	case LDO_PU:
+		shift = 9;
+		break;
+	case LDO_ARM:
+		shift = 0;
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	old = (reg & (0x1F << shift)) >> shift;
+	step = abs(val - old);
+	if (step == 0)
+		return 0;
+
+	reg = (reg & ~(0x1F << shift)) | (val << shift);
+	writel(reg, &anatop->reg_core);
+
 	/*
-	 * Mask out the REG_CORE[22:18] bits (REG2_TRIG)
-	 * and set them to the calculated value (0.7V + val * 0.25V)
+	 * The LDO ramp-up is based on 64 clock cycles of 24 MHz = 2.6 us per
+	 * step
 	 */
-	reg = (reg & ~(0x1F << 18)) | (val << 18);
-	writel(reg, &anatop->reg_core);
+	udelay(3 * step);
+
+	return 0;
 }
 
 static void imx_set_wdog_powerdown(bool enable)
@@ -131,11 +187,40 @@ static void imx_set_wdog_powerdown(bool enable)
 	writew(enable, &wdog2->wmcr);
 }
 
+static void set_ahb_rate(u32 val)
+{
+	struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+	u32 reg, div;
+
+	div = get_periph_clk() / val - 1;
+	reg = readl(&mxc_ccm->cbcdr);
+
+	writel((reg & (~MXC_CCM_CBCDR_AHB_PODF_MASK)) |
+		(div << MXC_CCM_CBCDR_AHB_PODF_OFFSET), &mxc_ccm->cbcdr);
+}
+
+static void clear_mmdc_ch_mask(void)
+{
+	struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+
+	/* Clear MMDC channel mask */
+	writel(0, &mxc_ccm->ccdr);
+}
+
 int arch_cpu_init(void)
 {
 	init_aips();
 
-	set_vddsoc(1200);	/* Set VDDSOC to 1.2V */
+	/* Need to clear MMDC_CHx_MASK to make warm reset work. */
+	clear_mmdc_ch_mask();
+
+	/*
+	 * When low freq boot is enabled, ROM will not set AHB
+	 * freq, so we need to ensure AHB freq is 132MHz in such
+	 * scenario.
+	 */
+	if (mxc_get_clock(MXC_ARM_CLK) == 396000000)
+		set_ahb_rate(132000000);
 
 	imx_set_wdog_powerdown(false); /* Disable PDE bit of WMCR register */
 
@@ -147,9 +232,18 @@ int arch_cpu_init(void)
 	return 0;
 }
 
+int board_postclk_init(void)
+{
+	set_ldo_voltage(LDO_SOC, 1175);	/* Set VDDSOC to 1.175V */
+
+	return 0;
+}
+
 #ifndef CONFIG_SYS_DCACHE_OFF
 void enable_caches(void)
 {
+	/* Avoid random hang when download by usb */
+	invalidate_dcache_all();
 	/* Enable D-cache. I-cache is already enabled in start.S */
 	dcache_enable();
 }
@@ -283,3 +377,59 @@ void imx_setup_hdmi(void)
 	writel(reg, &mxc_ccm->chsccdr);
 }
 #endif
+
+#ifndef CONFIG_SYS_L2CACHE_OFF
+#define IOMUXC_GPR11_L2CACHE_AS_OCRAM 0x00000002
+void v7_outer_cache_enable(void)
+{
+	struct pl310_regs *const pl310 = (struct pl310_regs *)L2_PL310_BASE;
+	unsigned int val;
+
+#if defined CONFIG_MX6SL
+	struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
+	val = readl(&iomux->gpr[11]);
+	if (val & IOMUXC_GPR11_L2CACHE_AS_OCRAM) {
+		/* L2 cache configured as OCRAM, reset it */
+		val &= ~IOMUXC_GPR11_L2CACHE_AS_OCRAM;
+		writel(val, &iomux->gpr[11]);
+	}
+#endif
+
+	writel(0x132, &pl310->pl310_tag_latency_ctrl);
+	writel(0x132, &pl310->pl310_data_latency_ctrl);
+
+	val = readl(&pl310->pl310_prefetch_ctrl);
+
+	/* Turn on the L2 I/D prefetch */
+	val |= 0x30000000;
+
+	/*
+	 * The L2 cache controller(PL310) version on the i.MX6D/Q is r3p1-50rel0
+	 * The L2 cache controller(PL310) version on the i.MX6DL/SOLO/SL is r3p2
+	 * But according to ARM PL310 errata: 752271
+	 * ID: 752271: Double linefill feature can cause data corruption
+	 * Fault Status: Present in: r3p0, r3p1, r3p1-50rel0. Fixed in r3p2
+	 * Workaround: The only workaround to this erratum is to disable the
+	 * double linefill feature. This is the default behavior.
+	 */
+
+#ifndef CONFIG_MX6Q
+	val |= 0x40800000;
+#endif
+	writel(val, &pl310->pl310_prefetch_ctrl);
+
+	val = readl(&pl310->pl310_power_ctrl);
+	val |= L2X0_DYNAMIC_CLK_GATING_EN;
+	val |= L2X0_STNDBY_MODE_EN;
+	writel(val, &pl310->pl310_power_ctrl);
+
+	setbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
+}
+
+void v7_outer_cache_disable(void)
+{
+	struct pl310_regs *const pl310 = (struct pl310_regs *)L2_PL310_BASE;
+
+	clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
+}
+#endif /* !CONFIG_SYS_L2CACHE_OFF */
diff --git a/arch/arm/cpu/armv7/nonsec_virt.S b/arch/arm/cpu/armv7/nonsec_virt.S
index 24b4c18bd4..6367e09612 100644
--- a/arch/arm/cpu/armv7/nonsec_virt.S
+++ b/arch/arm/cpu/armv7/nonsec_virt.S
@@ -14,6 +14,7 @@
 .arch_extension sec
 .arch_extension virt
 
+	.align	5
 /* the vector table for secure state and HYP mode */
 _monitor_vectors:
 	.word 0	/* reset */
@@ -32,7 +33,6 @@ _monitor_vectors:
  * to non-secure state.
  * We use only r0 and r1 here, due to constraints in the caller.
  */
-	.align	5
 _secure_monitor:
 	mrc	p15, 0, r1, c1, c1, 0		@ read SCR
 	bic	r1, r1, #0x4e			@ clear IRQ, FIQ, EA, nET bits
diff --git a/arch/arm/cpu/armv7/omap-common/Makefile b/arch/arm/cpu/armv7/omap-common/Makefile
index 75b3753260..59f5352b26 100644
--- a/arch/arm/cpu/armv7/omap-common/Makefile
+++ b/arch/arm/cpu/armv7/omap-common/Makefile
@@ -5,46 +5,30 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)libomap-common.o
-
-COBJS	:= reset.o
-COBJS	+= timer.o
-COBJS	+= utils.o
+obj-y	:= reset.o
+obj-y	+= timer.o
+obj-y	+= utils.o
 
 ifneq ($(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX),)
-COBJS	+= hwinit-common.o
-COBJS	+= clocks-common.o
-COBJS	+= emif-common.o
-COBJS	+= vc.o
-COBJS	+= abb.o
+obj-y	+= hwinit-common.o
+obj-y	+= clocks-common.o
+obj-y	+= emif-common.o
+obj-y	+= vc.o
+obj-y	+= abb.o
+endif
+
+ifneq ($(CONFIG_OMAP54XX),)
+obj-y	+= pipe3-phy.o
+obj-$(CONFIG_SCSI_AHCI_PLAT) += sata.o
 endif
 
 ifeq ($(CONFIG_OMAP34XX),)
-COBJS	+= boot-common.o
-SOBJS	+= lowlevel_init.o
+obj-y	+= boot-common.o
+obj-y	+= lowlevel_init.o
 endif
 
 ifndef CONFIG_SPL_BUILD
 ifneq ($(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX),)
-COBJS	+= mem-common.o
+obj-y	+= mem-common.o
 endif
 endif
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS))
-
-all:	$(obj).depend $(LIB)
-
-$(LIB):	$(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
diff --git a/arch/arm/cpu/armv7/omap-common/abb.c b/arch/arm/cpu/armv7/omap-common/abb.c
index a46783fae2..423aeb9807 100644
--- a/arch/arm/cpu/armv7/omap-common/abb.c
+++ b/arch/arm/cpu/armv7/omap-common/abb.c
@@ -11,6 +11,7 @@
 
 #include <common.h>
 #include <asm/omap_common.h>
+#include <asm/arch/clock.h>
 #include <asm/io.h>
 #include <asm/arch/sys_proto.h>
 
diff --git a/arch/arm/cpu/armv7/omap-common/boot-common.c b/arch/arm/cpu/armv7/omap-common/boot-common.c
index 0ffa03ac01..52e0f4a6cf 100644
--- a/arch/arm/cpu/armv7/omap-common/boot-common.c
+++ b/arch/arm/cpu/armv7/omap-common/boot-common.c
@@ -14,6 +14,7 @@
 #include <asm/arch/omap.h>
 #include <asm/arch/mmc_host_def.h>
 #include <asm/arch/sys_proto.h>
+#include <watchdog.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -65,7 +66,18 @@ u32 spl_boot_device(void)
 
 u32 spl_boot_mode(void)
 {
-	return gd->arch.omap_boot_params.omap_bootmode;
+	u32 val = gd->arch.omap_boot_params.omap_bootmode;
+
+	if (val == MMCSD_MODE_RAW)
+		return MMCSD_MODE_RAW;
+	else if (val == MMCSD_MODE_FAT)
+		return MMCSD_MODE_FAT;
+	else
+#ifdef CONFIG_SUPPORT_EMMC_BOOT
+		return MMCSD_MODE_EMMCBOOT;
+#else
+		return MMCSD_MODE_UNDEFINED;
+#endif
 }
 
 void spl_board_init(void)
@@ -76,6 +88,9 @@ void spl_board_init(void)
 #if defined(CONFIG_AM33XX) && defined(CONFIG_SPL_MUSB_NEW_SUPPORT)
 	arch_misc_init();
 #endif
+#if defined(CONFIG_HW_WATCHDOG)
+	hw_watchdog_init();
+#endif
 #ifdef CONFIG_AM33XX
 	am33xx_spl_board_init();
 #endif
diff --git a/arch/arm/cpu/armv7/omap-common/clocks-common.c b/arch/arm/cpu/armv7/omap-common/clocks-common.c
index ab0c5680f5..8e7411d437 100644
--- a/arch/arm/cpu/armv7/omap-common/clocks-common.c
+++ b/arch/arm/cpu/armv7/omap-common/clocks-common.c
@@ -339,7 +339,7 @@ void configure_mpu_dpll(void)
 	debug("MPU DPLL locked\n");
 }
 
-#ifdef CONFIG_USB_EHCI_OMAP
+#if defined(CONFIG_USB_EHCI_OMAP) || defined(CONFIG_USB_XHCI_OMAP)
 static void setup_usb_dpll(void)
 {
 	const struct dpll_params *params;
@@ -404,7 +404,7 @@ static void setup_dplls(void)
 	/* MPU dpll */
 	configure_mpu_dpll();
 
-#ifdef CONFIG_USB_EHCI_OMAP
+#if defined(CONFIG_USB_EHCI_OMAP) || defined(CONFIG_USB_XHCI_OMAP)
 	setup_usb_dpll();
 #endif
 	params = get_ddr_dpll_params(*dplls_data);
@@ -418,55 +418,6 @@ static void setup_dplls(void)
 #endif
 }
 
-#ifdef CONFIG_SYS_CLOCKS_ENABLE_ALL
-static void setup_non_essential_dplls(void)
-{
-	u32 abe_ref_clk;
-	const struct dpll_params *params;
-
-	/* IVA */
-	clrsetbits_le32((*prcm)->cm_bypclk_dpll_iva,
-		CM_BYPCLK_DPLL_IVA_CLKSEL_MASK, DPLL_IVA_CLKSEL_CORE_X2_DIV_2);
-
-	params = get_iva_dpll_params(*dplls_data);
-	do_setup_dpll((*prcm)->cm_clkmode_dpll_iva, params, DPLL_LOCK, "iva");
-
-	/* Configure ABE dpll */
-	params = get_abe_dpll_params(*dplls_data);
-#ifdef CONFIG_SYS_OMAP_ABE_SYSCK
-	abe_ref_clk = CM_ABE_PLL_REF_CLKSEL_CLKSEL_SYSCLK;
-
-	if (omap_revision() == DRA752_ES1_0)
-		/* Select the sys clk for dpll_abe */
-		clrsetbits_le32((*prcm)->cm_abe_pll_sys_clksel,
-				CM_CLKSEL_ABE_PLL_SYS_CLKSEL_MASK,
-				CM_ABE_PLL_SYS_CLKSEL_SYSCLK2);
-#else
-	abe_ref_clk = CM_ABE_PLL_REF_CLKSEL_CLKSEL_32KCLK;
-	/*
-	 * We need to enable some additional options to achieve
-	 * 196.608MHz from 32768 Hz
-	 */
-	setbits_le32((*prcm)->cm_clkmode_dpll_abe,
-			CM_CLKMODE_DPLL_DRIFTGUARD_EN_MASK|
-			CM_CLKMODE_DPLL_RELOCK_RAMP_EN_MASK|
-			CM_CLKMODE_DPLL_LPMODE_EN_MASK|
-			CM_CLKMODE_DPLL_REGM4XEN_MASK);
-	/* Spend 4 REFCLK cycles at each stage */
-	clrsetbits_le32((*prcm)->cm_clkmode_dpll_abe,
-			CM_CLKMODE_DPLL_RAMP_RATE_MASK,
-			1 << CM_CLKMODE_DPLL_RAMP_RATE_SHIFT);
-#endif
-
-	/* Select the right reference clk */
-	clrsetbits_le32((*prcm)->cm_abe_pll_ref_clksel,
-			CM_ABE_PLL_REF_CLKSEL_CLKSEL_MASK,
-			abe_ref_clk << CM_ABE_PLL_REF_CLKSEL_CLKSEL_SHIFT);
-	/* Lock the dpll */
-	do_setup_dpll((*prcm)->cm_clkmode_dpll_abe, params, DPLL_LOCK, "abe");
-}
-#endif
-
 u32 get_offset_code(u32 volt_offset, struct pmic_data *pmic)
 {
 	u32 offset_code;
@@ -760,10 +711,6 @@ void prcm_init(void)
 		timer_init();
 		scale_vcores(*omap_vcores);
 		setup_dplls();
-#ifdef CONFIG_SYS_CLOCKS_ENABLE_ALL
-		setup_non_essential_dplls();
-		enable_non_essential_clocks();
-#endif
 		setup_warmreset_time();
 		break;
 	default:
@@ -779,7 +726,8 @@ void gpi2c_init(void)
 	static int gpi2c = 1;
 
 	if (gpi2c) {
-		i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
+		i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED,
+			 CONFIG_SYS_OMAP24_I2C_SLAVE);
 		gpi2c = 0;
 	}
 }
diff --git a/arch/arm/cpu/armv7/omap-common/config.mk b/arch/arm/cpu/armv7/omap-common/config.mk
deleted file mode 100644
index 3a36ab65e1..0000000000
--- a/arch/arm/cpu/armv7/omap-common/config.mk
+++ /dev/null
@@ -1,9 +0,0 @@
-#
-# (C) Copyright 2002
-# Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-# Make ARMv5 to allow more compilers to work, even though its v7a.
-PLATFORM_CPPFLAGS += -march=armv5
diff --git a/arch/arm/cpu/armv7/omap-common/emif-common.c b/arch/arm/cpu/armv7/omap-common/emif-common.c
index b0e1caa356..429c4becf3 100644
--- a/arch/arm/cpu/armv7/omap-common/emif-common.c
+++ b/arch/arm/cpu/armv7/omap-common/emif-common.c
@@ -50,20 +50,6 @@ inline u32 emif_num(u32 base)
 		return 0;
 }
 
-/*
- * Get SDRAM type connected to EMIF.
- * Assuming similar SDRAM parts are connected to both EMIF's
- * which is typically the case. So it is sufficient to get
- * SDRAM type from EMIF1.
- */
-u32 emif_sdram_type()
-{
-	struct emif_reg_struct *emif = (struct emif_reg_struct *)EMIF1_BASE;
-
-	return (readl(&emif->emif_sdram_config) &
-		EMIF_REG_SDRAM_TYPE_MASK) >> EMIF_REG_SDRAM_TYPE_SHIFT;
-}
-
 static inline u32 get_mr(u32 base, u32 cs, u32 mr_addr)
 {
 	u32 mr;
@@ -193,8 +179,7 @@ void emif_update_timings(u32 base, const struct emif_regs *regs)
 	writel(regs->temp_alert_config, &emif->emif_temp_alert_config);
 	writel(regs->emif_ddr_phy_ctlr_1, &emif->emif_ddr_phy_ctrl_1_shdw);
 
-	if ((omap_revision() >= OMAP5430_ES1_0) ||
-				(omap_revision() == DRA752_ES1_0)) {
+	if ((omap_revision() >= OMAP5430_ES1_0) || is_dra7xx()) {
 		writel(EMIF_L3_CONFIG_VAL_SYS_10_MPU_5_LL_0,
 			&emif->emif_l3_config);
 	} else if (omap_revision() >= OMAP4460_ES1_0) {
@@ -206,7 +191,7 @@ void emif_update_timings(u32 base, const struct emif_regs *regs)
 	}
 }
 
-static void ddr3_leveling(u32 base, const struct emif_regs *regs)
+static void omap5_ddr3_leveling(u32 base, const struct emif_regs *regs)
 {
 	struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
 
@@ -217,47 +202,86 @@ static void ddr3_leveling(u32 base, const struct emif_regs *regs)
 
 	/*
 	 * Set invert_clkout (if activated)--DDR_PHYCTRL_1
-	 * Invert clock adds an additional half cycle delay on the command
-	 * interface.  The additional half cycle, is usually meant to enable
-	 * leveling in the situation that DQS is later than CK on the board.It
-	 * also helps provide some additional margin for leveling.
+	 * Invert clock adds an additional half cycle delay on the
+	 * command interface.  The additional half cycle, is usually
+	 * meant to enable leveling in the situation that DQS is later
+	 * than CK on the board.It also helps provide some additional
+	 * margin for leveling.
 	 */
-	writel(regs->emif_ddr_phy_ctlr_1, &emif->emif_ddr_phy_ctrl_1);
-	writel(regs->emif_ddr_phy_ctlr_1, &emif->emif_ddr_phy_ctrl_1_shdw);
+	writel(regs->emif_ddr_phy_ctlr_1,
+	       &emif->emif_ddr_phy_ctrl_1);
+
+	writel(regs->emif_ddr_phy_ctlr_1,
+	       &emif->emif_ddr_phy_ctrl_1_shdw);
 	__udelay(130);
 
 	writel(((LP_MODE_DISABLE << EMIF_REG_LP_MODE_SHIFT)
-		& EMIF_REG_LP_MODE_MASK), &emif->emif_pwr_mgmt_ctrl);
+	       & EMIF_REG_LP_MODE_MASK), &emif->emif_pwr_mgmt_ctrl);
 
 	/* Launch Full leveling */
 	writel(DDR3_FULL_LVL, &emif->emif_rd_wr_lvl_ctl);
 
 	/* Wait till full leveling is complete */
 	readl(&emif->emif_rd_wr_lvl_ctl);
-	__udelay(130);
+	      __udelay(130);
 
 	/* Read data eye leveling no of samples */
 	config_data_eye_leveling_samples(base);
 
-	/* Launch 8 incremental WR_LVL- to compensate for PHY limitation */
-	writel(0x2 << EMIF_REG_WRLVLINC_INT_SHIFT, &emif->emif_rd_wr_lvl_ctl);
+	/*
+	 * Launch 8 incremental WR_LVL- to compensate for
+	 * PHY limitation.
+	 */
+	writel(0x2 << EMIF_REG_WRLVLINC_INT_SHIFT,
+	       &emif->emif_rd_wr_lvl_ctl);
+
 	__udelay(130);
 
 	/* Launch Incremental leveling */
 	writel(DDR3_INC_LVL, &emif->emif_rd_wr_lvl_ctl);
-	__udelay(130);
+	       __udelay(130);
 }
 
-static void ddr3_sw_leveling(u32 base, const struct emif_regs *regs)
+static void dra7_ddr3_leveling(u32 base, const struct emif_regs *regs)
 {
 	struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
 
-	writel(regs->emif_ddr_phy_ctlr_1, &emif->emif_ddr_phy_ctrl_1);
-	writel(regs->emif_ddr_phy_ctlr_1, &emif->emif_ddr_phy_ctrl_1_shdw);
+	u32 fifo_reg;
+
+	fifo_reg = readl(&emif->emif_ddr_fifo_misaligned_clear_1);
+	writel(fifo_reg | 0x00000100,
+	       &emif->emif_ddr_fifo_misaligned_clear_1);
+
+	fifo_reg = readl(&emif->emif_ddr_fifo_misaligned_clear_2);
+	writel(fifo_reg | 0x00000100,
+	       &emif->emif_ddr_fifo_misaligned_clear_2);
+
+	/* Launch Full leveling */
+	writel(DDR3_FULL_LVL, &emif->emif_rd_wr_lvl_ctl);
+
+	/* Wait till full leveling is complete */
+	readl(&emif->emif_rd_wr_lvl_ctl);
+	      __udelay(130);
+
+	/* Read data eye leveling no of samples */
 	config_data_eye_leveling_samples(base);
 
-	writel(regs->emif_rd_wr_lvl_ctl, &emif->emif_rd_wr_lvl_ctl);
-	writel(regs->sdram_config, &emif->emif_sdram_config);
+	/*
+	 * Disable leveling. This is because if leveling is kept
+	 * enabled, then PHY triggers a false leveling during
+	 * EMIF-idle scenario which results in wrong delay
+	 * values getting updated. After this the EMIF becomes
+	 * unaccessible. So disable it after the first time
+	 */
+	writel(0x0, &emif->emif_rd_wr_lvl_rmp_ctl);
+}
+
+static void ddr3_leveling(u32 base, const struct emif_regs *regs)
+{
+	if (is_omap54xx())
+		omap5_ddr3_leveling(base, regs);
+	else
+		dra7_ddr3_leveling(base, regs);
 }
 
 static void ddr3_init(u32 base, const struct emif_regs *regs)
@@ -270,9 +294,6 @@ static void ddr3_init(u32 base, const struct emif_regs *regs)
 	 * defined, contents of mode Registers must be fully initialized.
 	 * H/W takes care of this initialization
 	 */
-	writel(regs->sdram_config2, &emif->emif_lpddr2_nvm_config);
-	writel(regs->sdram_config_init, &emif->emif_sdram_config);
-
 	writel(regs->emif_ddr_phy_ctlr_1_init, &emif->emif_ddr_phy_ctrl_1);
 
 	/* Update timing registers */
@@ -283,15 +304,24 @@ static void ddr3_init(u32 base, const struct emif_regs *regs)
 	writel(regs->ref_ctrl, &emif->emif_sdram_ref_ctrl);
 	writel(regs->read_idle_ctrl, &emif->emif_read_idlectrl);
 
-	do_ext_phy_settings(base, regs);
+	/*
+	 * The same sequence should work on OMAP5432 as well. But strange that
+	 * it is not working
+	 */
+	if (is_dra7xx()) {
+		do_ext_phy_settings(base, regs);
+		writel(regs->sdram_config2, &emif->emif_lpddr2_nvm_config);
+		writel(regs->sdram_config_init, &emif->emif_sdram_config);
+	} else {
+		writel(regs->sdram_config2, &emif->emif_lpddr2_nvm_config);
+		writel(regs->sdram_config_init, &emif->emif_sdram_config);
+		do_ext_phy_settings(base, regs);
+	}
 
 	/* enable leveling */
 	writel(regs->emif_rd_wr_lvl_rmp_ctl, &emif->emif_rd_wr_lvl_rmp_ctl);
 
-	if (omap_revision() == DRA752_ES1_0)
-		ddr3_sw_leveling(base, regs);
-	else
-		ddr3_leveling(base, regs);
+	ddr3_leveling(base, regs);
 }
 
 #ifndef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
@@ -1079,10 +1109,7 @@ static void do_sdram_init(u32 base)
 	if (warm_reset() && (emif_sdram_type() == EMIF_SDRAM_TYPE_DDR3)) {
 		set_lpmode_selfrefresh(base);
 		emif_reset_phy(base);
-		if (omap_revision() == DRA752_ES1_0)
-			ddr3_sw_leveling(base, regs);
-		else
-			ddr3_leveling(base, regs);
+		ddr3_leveling(base, regs);
 	}
 
 	/* Write to the shadow registers */
@@ -1244,6 +1271,42 @@ void dmm_init(u32 base)
 
 }
 
+static void do_bug0039_workaround(u32 base)
+{
+	u32 val, i, clkctrl;
+	struct emif_reg_struct *emif_base = (struct emif_reg_struct *)base;
+	const struct read_write_regs *bug_00339_regs;
+	u32 iterations;
+	u32 *phy_status_base = &emif_base->emif_ddr_phy_status[0];
+	u32 *phy_ctrl_base = &emif_base->emif_ddr_ext_phy_ctrl_1;
+
+	if (is_dra7xx())
+		phy_status_base++;
+
+	bug_00339_regs = get_bug_regs(&iterations);
+
+	/* Put EMIF in to idle */
+	clkctrl = __raw_readl((*prcm)->cm_memif_clkstctrl);
+	__raw_writel(0x0, (*prcm)->cm_memif_clkstctrl);
+
+	/* Copy the phy status registers in to phy ctrl shadow registers */
+	for (i = 0; i < iterations; i++) {
+		val = __raw_readl(phy_status_base +
+				  bug_00339_regs[i].read_reg - 1);
+
+		__raw_writel(val, phy_ctrl_base +
+			     ((bug_00339_regs[i].write_reg - 1) << 1));
+
+		__raw_writel(val, phy_ctrl_base +
+			     (bug_00339_regs[i].write_reg << 1) - 1);
+	}
+
+	/* Disable leveling */
+	writel(0x0, &emif_base->emif_rd_wr_lvl_rmp_ctl);
+
+	__raw_writel(clkctrl,  (*prcm)->cm_memif_clkstctrl);
+}
+
 /*
  * SDRAM initialization:
  * SDRAM initialization has two parts:
@@ -1319,5 +1382,11 @@ void sdram_init(void)
 			debug("get_ram_size() successful");
 	}
 
+	if (sdram_type == EMIF_SDRAM_TYPE_DDR3 &&
+	    (!in_sdram && !warm_reset())) {
+		do_bug0039_workaround(EMIF1_BASE);
+		do_bug0039_workaround(EMIF2_BASE);
+	}
+
 	debug("<<sdram_init()\n");
 }
diff --git a/arch/arm/cpu/armv7/omap-common/hwinit-common.c b/arch/arm/cpu/armv7/omap-common/hwinit-common.c
index 85d375432f..8ebc0ce251 100644
--- a/arch/arm/cpu/armv7/omap-common/hwinit-common.c
+++ b/arch/arm/cpu/armv7/omap-common/hwinit-common.c
@@ -14,7 +14,7 @@
 #include <common.h>
 #include <spl.h>
 #include <asm/arch/sys_proto.h>
-#include <asm/sizes.h>
+#include <linux/sizes.h>
 #include <asm/emif.h>
 #include <asm/omap_common.h>
 #include <linux/compiler.h>
@@ -43,16 +43,10 @@ static void set_mux_conf_regs(void)
 		set_muxconf_regs_essential();
 		break;
 	case OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL:
-#ifdef CONFIG_SYS_ENABLE_PADS_ALL
-		set_muxconf_regs_non_essential();
-#endif
 		break;
 	case OMAP_INIT_CONTEXT_UBOOT_FROM_NOR:
 	case OMAP_INIT_CONTEXT_UBOOT_AFTER_CH:
 		set_muxconf_regs_essential();
-#ifdef CONFIG_SYS_ENABLE_PADS_ALL
-		set_muxconf_regs_non_essential();
-#endif
 		break;
 	}
 }
@@ -254,6 +248,7 @@ u32 get_device_type(void)
 				      (DEVICE_TYPE_MASK)) >> DEVICE_TYPE_SHIFT;
 }
 
+#if defined(CONFIG_DISPLAY_CPUINFO)
 /*
  * Print CPU information
  */
@@ -264,6 +259,8 @@ int print_cpuinfo(void)
 
 	return 0;
 }
+#endif
+
 #ifndef CONFIG_SYS_DCACHE_OFF
 void enable_caches(void)
 {
diff --git a/arch/arm/cpu/armv7/omap-common/pipe3-phy.c b/arch/arm/cpu/armv7/omap-common/pipe3-phy.c
new file mode 100644
index 0000000000..b71d769410
--- /dev/null
+++ b/arch/arm/cpu/armv7/omap-common/pipe3-phy.c
@@ -0,0 +1,231 @@
+/*
+ * TI PIPE3 PHY
+ *
+ * (C) Copyright 2013
+ * Texas Instruments, <www.ti.com>
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#include <common.h>
+#include <sata.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/io.h>
+#include <asm/errno.h>
+#include "pipe3-phy.h"
+
+/* PLLCTRL Registers */
+#define PLL_STATUS              0x00000004
+#define PLL_GO                  0x00000008
+#define PLL_CONFIGURATION1      0x0000000C
+#define PLL_CONFIGURATION2      0x00000010
+#define PLL_CONFIGURATION3      0x00000014
+#define PLL_CONFIGURATION4      0x00000020
+
+#define PLL_REGM_MASK           0x001FFE00
+#define PLL_REGM_SHIFT          9
+#define PLL_REGM_F_MASK         0x0003FFFF
+#define PLL_REGM_F_SHIFT        0
+#define PLL_REGN_MASK           0x000001FE
+#define PLL_REGN_SHIFT          1
+#define PLL_SELFREQDCO_MASK     0x0000000E
+#define PLL_SELFREQDCO_SHIFT    1
+#define PLL_SD_MASK             0x0003FC00
+#define PLL_SD_SHIFT            10
+#define SET_PLL_GO              0x1
+#define PLL_TICOPWDN            BIT(16)
+#define PLL_LDOPWDN             BIT(15)
+#define PLL_LOCK                0x2
+#define PLL_IDLE                0x1
+
+/* PHY POWER CONTROL Register */
+#define OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_CMD_MASK         0x003FC000
+#define OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_CMD_SHIFT        0xE
+
+#define OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_FREQ_MASK        0xFFC00000
+#define OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_FREQ_SHIFT       0x16
+
+#define OMAP_CTRL_PIPE3_PHY_TX_RX_POWERON       0x3
+#define OMAP_CTRL_PIPE3_PHY_TX_RX_POWEROFF      0x0
+
+
+#define PLL_IDLE_TIME   100     /* in milliseconds */
+#define PLL_LOCK_TIME   100     /* in milliseconds */
+
+static inline u32 omap_pipe3_readl(void __iomem *addr, unsigned offset)
+{
+	return __raw_readl(addr + offset);
+}
+
+static inline void omap_pipe3_writel(void __iomem *addr, unsigned offset,
+		u32 data)
+{
+	__raw_writel(data, addr + offset);
+}
+
+static struct pipe3_dpll_params *omap_pipe3_get_dpll_params(struct omap_pipe3
+									*pipe3)
+{
+	u32 rate;
+	struct pipe3_dpll_map *dpll_map = pipe3->dpll_map;
+
+	rate = get_sys_clk_freq();
+
+	for (; dpll_map->rate; dpll_map++) {
+		if (rate == dpll_map->rate)
+			return &dpll_map->params;
+	}
+
+	printf("%s: No DPLL configuration for %u Hz SYS CLK\n",
+	       __func__, rate);
+	return NULL;
+}
+
+
+static int omap_pipe3_wait_lock(struct omap_pipe3 *phy)
+{
+	u32 val;
+	int timeout = PLL_LOCK_TIME;
+
+	do {
+		mdelay(1);
+		val = omap_pipe3_readl(phy->pll_ctrl_base, PLL_STATUS);
+		if (val & PLL_LOCK)
+			break;
+	} while (--timeout);
+
+	if (!(val & PLL_LOCK)) {
+		printf("%s: DPLL failed to lock\n", __func__);
+		return -EBUSY;
+	}
+
+	return 0;
+}
+
+static int omap_pipe3_dpll_program(struct omap_pipe3 *phy)
+{
+	u32                     val;
+	struct pipe3_dpll_params *dpll_params;
+
+	dpll_params = omap_pipe3_get_dpll_params(phy);
+	if (!dpll_params) {
+		printf("%s: Invalid DPLL parameters\n", __func__);
+		return -EINVAL;
+	}
+
+	val = omap_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION1);
+	val &= ~PLL_REGN_MASK;
+	val |= dpll_params->n << PLL_REGN_SHIFT;
+	omap_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION1, val);
+
+	val = omap_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION2);
+	val &= ~PLL_SELFREQDCO_MASK;
+	val |= dpll_params->freq << PLL_SELFREQDCO_SHIFT;
+	omap_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION2, val);
+
+	val = omap_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION1);
+	val &= ~PLL_REGM_MASK;
+	val |= dpll_params->m << PLL_REGM_SHIFT;
+	omap_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION1, val);
+
+	val = omap_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION4);
+	val &= ~PLL_REGM_F_MASK;
+	val |= dpll_params->mf << PLL_REGM_F_SHIFT;
+	omap_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION4, val);
+
+	val = omap_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION3);
+	val &= ~PLL_SD_MASK;
+	val |= dpll_params->sd << PLL_SD_SHIFT;
+	omap_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION3, val);
+
+	omap_pipe3_writel(phy->pll_ctrl_base, PLL_GO, SET_PLL_GO);
+
+	return omap_pipe3_wait_lock(phy);
+}
+
+static void omap_control_phy_power(struct omap_pipe3 *phy, int on)
+{
+	u32 val, rate;
+
+	val = readl(phy->power_reg);
+
+	rate = get_sys_clk_freq();
+	rate = rate/1000000;
+
+	if (on) {
+		val &= ~(OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_CMD_MASK |
+				OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_FREQ_MASK);
+		val |= OMAP_CTRL_PIPE3_PHY_TX_RX_POWERON <<
+			OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_CMD_SHIFT;
+		val |= rate <<
+			OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_FREQ_SHIFT;
+	} else {
+		val &= ~OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_CMD_MASK;
+		val |= OMAP_CTRL_PIPE3_PHY_TX_RX_POWEROFF <<
+			OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_CMD_SHIFT;
+	}
+
+	writel(val, phy->power_reg);
+}
+
+int phy_pipe3_power_on(struct omap_pipe3 *phy)
+{
+	int ret;
+	u32 val;
+
+	/* Program the DPLL only if not locked */
+	val = omap_pipe3_readl(phy->pll_ctrl_base, PLL_STATUS);
+	if (!(val & PLL_LOCK)) {
+		ret = omap_pipe3_dpll_program(phy);
+		if (ret)
+			return ret;
+	} else {
+		/* else just bring it out of IDLE mode */
+		val = omap_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION2);
+		if (val & PLL_IDLE) {
+			val &= ~PLL_IDLE;
+			omap_pipe3_writel(phy->pll_ctrl_base,
+					  PLL_CONFIGURATION2, val);
+			ret = omap_pipe3_wait_lock(phy);
+			if (ret)
+				return ret;
+		}
+	}
+
+	/* Power up the PHY */
+	omap_control_phy_power(phy, 1);
+
+	return 0;
+}
+
+int phy_pipe3_power_off(struct omap_pipe3 *phy)
+{
+	u32 val;
+	int timeout = PLL_IDLE_TIME;
+
+	/* Power down the PHY */
+	omap_control_phy_power(phy, 0);
+
+	/* Put DPLL in IDLE mode */
+	val = omap_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION2);
+	val |= PLL_IDLE;
+	omap_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION2, val);
+
+	/* wait for LDO and Oscillator to power down */
+	do {
+		mdelay(1);
+		val = omap_pipe3_readl(phy->pll_ctrl_base, PLL_STATUS);
+		if ((val & PLL_TICOPWDN) && (val & PLL_LDOPWDN))
+			break;
+	} while (--timeout);
+
+	if (!(val & PLL_TICOPWDN) || !(val & PLL_LDOPWDN)) {
+		printf("%s: Failed to power down DPLL: PLL_STATUS 0x%x\n",
+		       __func__, val);
+		return -EBUSY;
+	}
+
+	return 0;
+}
+
diff --git a/arch/arm/cpu/armv7/omap-common/pipe3-phy.h b/arch/arm/cpu/armv7/omap-common/pipe3-phy.h
new file mode 100644
index 0000000000..441f49a3f9
--- /dev/null
+++ b/arch/arm/cpu/armv7/omap-common/pipe3-phy.h
@@ -0,0 +1,36 @@
+/*
+ * TI PIPE3 PHY
+ *
+ * (C) Copyright 2013
+ * Texas Instruments, <www.ti.com>
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#ifndef __OMAP_PIPE3_PHY_H
+#define __OMAP_PIPE3_PHY_H
+
+struct pipe3_dpll_params {
+	u16     m;
+	u8      n;
+	u8      freq:3;
+	u8      sd;
+	u32     mf;
+};
+
+struct pipe3_dpll_map {
+	unsigned long rate;
+	struct pipe3_dpll_params params;
+};
+
+struct omap_pipe3 {
+	void __iomem            *pll_ctrl_base;
+	void __iomem		*power_reg;
+	struct pipe3_dpll_map   *dpll_map;
+};
+
+
+int phy_pipe3_power_on(struct omap_pipe3 *phy);
+int phy_pipe3_power_off(struct omap_pipe3 *pipe3);
+
+#endif /* __OMAP_PIPE3_PHY_H */
diff --git a/arch/arm/cpu/armv7/omap-common/sata.c b/arch/arm/cpu/armv7/omap-common/sata.c
new file mode 100644
index 0000000000..cad4feed00
--- /dev/null
+++ b/arch/arm/cpu/armv7/omap-common/sata.c
@@ -0,0 +1,76 @@
+/*
+ * TI SATA platform driver
+ *
+ * (C) Copyright 2013
+ * Texas Instruments, <www.ti.com>
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#include <common.h>
+#include <ahci.h>
+#include <scsi.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/sata.h>
+#include <sata.h>
+#include <asm/io.h>
+#include "pipe3-phy.h"
+
+static struct pipe3_dpll_map dpll_map_sata[] = {
+	{12000000, {1000, 7, 4, 6, 0} },        /* 12 MHz */
+	{16800000, {714, 7, 4, 6, 0} },         /* 16.8 MHz */
+	{19200000, {625, 7, 4, 6, 0} },         /* 19.2 MHz */
+	{20000000, {600, 7, 4, 6, 0} },         /* 20 MHz */
+	{26000000, {461, 7, 4, 6, 0} },         /* 26 MHz */
+	{38400000, {312, 7, 4, 6, 0} },         /* 38.4 MHz */
+	{ },                                    /* Terminator */
+};
+
+struct omap_pipe3 sata_phy = {
+	.pll_ctrl_base = (void __iomem *)TI_SATA_PLLCTRL_BASE,
+	/* .power_reg is updated at runtime */
+	.dpll_map = dpll_map_sata,
+};
+
+int init_sata(int dev)
+{
+	int ret;
+	u32 val;
+
+	u32 const clk_domains_sata[] = {
+		0
+	};
+
+	u32 const clk_modules_hw_auto_sata[] = {
+		(*prcm)->cm_l3init_ocp2scp3_clkctrl,
+		0
+	};
+
+	u32 const clk_modules_explicit_en_sata[] = {
+		(*prcm)->cm_l3init_sata_clkctrl,
+		0
+	};
+
+	do_enable_clocks(clk_domains_sata,
+			 clk_modules_hw_auto_sata,
+			 clk_modules_explicit_en_sata,
+			 0);
+
+	/* Enable optional functional clock for SATA */
+	setbits_le32((*prcm)->cm_l3init_sata_clkctrl,
+		     SATA_CLKCTRL_OPTFCLKEN_MASK);
+
+	sata_phy.power_reg = (void __iomem *)(*ctrl)->control_phy_power_sata;
+
+	/* Power up the PHY */
+	phy_pipe3_power_on(&sata_phy);
+
+	/* Enable SATA module, No Idle, No Standby */
+	val = TI_SATA_IDLE_NO | TI_SATA_STANDBY_NO;
+	writel(val, TI_SATA_WRAPPER_BASE + TI_SATA_SYSCONFIG);
+
+	ret = ahci_init(DWC_AHSATA_BASE);
+	scsi_scan(1);
+
+	return ret;
+}
diff --git a/arch/arm/cpu/armv7/omap-common/u-boot-spl.lds b/arch/arm/cpu/armv7/omap-common/u-boot-spl.lds
index 5e93b343e6..745603d0fe 100644
--- a/arch/arm/cpu/armv7/omap-common/u-boot-spl.lds
+++ b/arch/arm/cpu/armv7/omap-common/u-boot-spl.lds
@@ -33,8 +33,17 @@ SECTIONS
 	.data : { *(SORT_BY_ALIGNMENT(.data*)) } >.sram
 
 	. = ALIGN(4);
+	.u_boot_list : {
+		KEEP(*(SORT(.u_boot_list*_i2c_*)));
+	} >.sram
+
+	. = ALIGN(4);
 	__image_copy_end = .;
-	_end = .;
+
+	.end :
+	{
+		*(.__end)
+	}
 
 	.bss :
 	{
diff --git a/arch/arm/cpu/armv7/omap3/Makefile b/arch/arm/cpu/armv7/omap3/Makefile
index f070c18196..39ff2575bc 100644
--- a/arch/arm/cpu/armv7/omap3/Makefile
+++ b/arch/arm/cpu/armv7/omap3/Makefile
@@ -5,38 +5,17 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
+obj-y	:= lowlevel_init.o
 
-LIB	=  $(obj)lib$(SOC).o
-
-SOBJS	:= lowlevel_init.o
-
-COBJS	+= board.o
-COBJS	+= clock.o
-COBJS	+= mem.o
-COBJS	+= sys_info.o
+obj-y	+= board.o
+obj-y	+= clock.o
+obj-y	+= mem.o
+obj-y	+= sys_info.o
 ifdef CONFIG_SPL_BUILD
-COBJS-$(CONFIG_SPL_OMAP3_ID_NAND)	+= spl_id_nand.o
+obj-$(CONFIG_SPL_OMAP3_ID_NAND)	+= spl_id_nand.o
 endif
 
-COBJS-$(CONFIG_DRIVER_TI_EMAC)	+= emac.o
-COBJS-$(CONFIG_EMIF4)	+= emif4.o
-COBJS-$(CONFIG_SDRC)	+= sdrc.o
-COBJS-$(CONFIG_USB_MUSB_AM35X)	+= am35x_musb.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS) $(COBJS-y) $(SOBJS))
-
-all:	 $(obj).depend $(LIB)
-
-$(LIB):	$(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-$(CONFIG_DRIVER_TI_EMAC)	+= emac.o
+obj-$(CONFIG_EMIF4)	+= emif4.o
+obj-$(CONFIG_SDRC)	+= sdrc.o
+obj-$(CONFIG_USB_MUSB_AM35X)	+= am35x_musb.o
diff --git a/arch/arm/cpu/armv7/omap3/board.c b/arch/arm/cpu/armv7/omap3/board.c
index 7d1f8d9d2c..29228160c3 100644
--- a/arch/arm/cpu/armv7/omap3/board.c
+++ b/arch/arm/cpu/armv7/omap3/board.c
@@ -98,7 +98,7 @@ void spl_board_init(void)
 	gpmc_init();
 #endif
 #ifdef CONFIG_SPL_I2C_SUPPORT
-	i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
+	i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE);
 #endif
 }
 #endif /* CONFIG_SPL_BUILD */
diff --git a/arch/arm/cpu/armv7/omap3/clock.c b/arch/arm/cpu/armv7/omap3/clock.c
index 9f989ff860..1bc27bdc7f 100644
--- a/arch/arm/cpu/armv7/omap3/clock.c
+++ b/arch/arm/cpu/armv7/omap3/clock.c
@@ -708,7 +708,7 @@ void per_clocks_enable(void)
 	sr32(&prcm_base->iclken_per, 17, 1, 1);
 #endif
 
-#ifdef CONFIG_DRIVER_OMAP34XX_I2C
+#ifdef CONFIG_SYS_I2C_OMAP34XX
 	/* Turn on all 3 I2C clocks */
 	sr32(&prcm_base->fclken1_core, 15, 3, 0x7);
 	sr32(&prcm_base->iclken1_core, 15, 3, 0x7);	/* I2C1,2,3 = on */
@@ -730,8 +730,6 @@ void per_clocks_enable(void)
 		sr32(&prcm_base->fclken_cam, 0, 32, FCK_CAM_ON);
 		sr32(&prcm_base->iclken_cam, 0, 32, ICK_CAM_ON);
 	}
-	sr32(&prcm_base->fclken_per, 0, 32, FCK_PER_ON);
-	sr32(&prcm_base->iclken_per, 0, 32, ICK_PER_ON);
 
 	sdelay(1000);
 }
diff --git a/arch/arm/cpu/armv7/omap3/config.mk b/arch/arm/cpu/armv7/omap3/config.mk
index 1d6a57c66c..ad44d63840 100644
--- a/arch/arm/cpu/armv7/omap3/config.mk
+++ b/arch/arm/cpu/armv7/omap3/config.mk
@@ -9,7 +9,7 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 ifdef CONFIG_SPL_BUILD
-ALL-y	+= $(OBJTREE)/MLO
+ALL-y	+= MLO
 else
-ALL-y	+= $(obj)u-boot.img
+ALL-y	+= u-boot.img
 endif
diff --git a/arch/arm/cpu/armv7/omap3/lowlevel_init.S b/arch/arm/cpu/armv7/omap3/lowlevel_init.S
index 6f7261b7b8..78577b1d1c 100644
--- a/arch/arm/cpu/armv7/omap3/lowlevel_init.S
+++ b/arch/arm/cpu/armv7/omap3/lowlevel_init.S
@@ -17,9 +17,6 @@
 #include <asm/arch/clocks_omap3.h>
 #include <linux/linkage.h>
 
-_TEXT_BASE:
-	.word	CONFIG_SYS_TEXT_BASE	/* sdram load addr from config.mk */
-
 #ifdef CONFIG_SPL_BUILD
 ENTRY(save_boot_params)
 	ldr	r4, =omap3_boot_device
diff --git a/arch/arm/cpu/armv7/omap4/Makefile b/arch/arm/cpu/armv7/omap4/Makefile
index fc6e2ddd0a..76a032a2d9 100644
--- a/arch/arm/cpu/armv7/omap4/Makefile
+++ b/arch/arm/cpu/armv7/omap4/Makefile
@@ -5,29 +5,8 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	=  $(obj)lib$(SOC).o
-
-COBJS	+= sdram_elpida.o
-COBJS	+= hwinit.o
-COBJS	+= emif.o
-COBJS	+= prcm-regs.o
-COBJS	+= hw_data.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS) $(SOBJS))
-
-all:	 $(obj).depend $(LIB)
-
-$(LIB):	$(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	+= sdram_elpida.o
+obj-y	+= hwinit.o
+obj-y	+= emif.o
+obj-y	+= prcm-regs.o
+obj-y	+= hw_data.o
diff --git a/arch/arm/cpu/armv7/omap4/config.mk b/arch/arm/cpu/armv7/omap4/config.mk
index 1d6a57c66c..ad44d63840 100644
--- a/arch/arm/cpu/armv7/omap4/config.mk
+++ b/arch/arm/cpu/armv7/omap4/config.mk
@@ -9,7 +9,7 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 ifdef CONFIG_SPL_BUILD
-ALL-y	+= $(OBJTREE)/MLO
+ALL-y	+= MLO
 else
-ALL-y	+= $(obj)u-boot.img
+ALL-y	+= u-boot.img
 endif
diff --git a/arch/arm/cpu/armv7/omap4/hw_data.c b/arch/arm/cpu/armv7/omap4/hw_data.c
index 6a225c8cb2..029533c851 100644
--- a/arch/arm/cpu/armv7/omap4/hw_data.c
+++ b/arch/arm/cpu/armv7/omap4/hw_data.c
@@ -172,6 +172,20 @@ struct dplls omap4430_dplls_es1 = {
 	.ddr = NULL
 };
 
+struct dplls omap4430_dplls_es20 = {
+	.mpu = mpu_dpll_params_1200mhz,
+	.core = core_dpll_params_es2_1600mhz_ddr200mhz,
+	.per = per_dpll_params_1536mhz,
+	.iva = iva_dpll_params_1862mhz,
+#ifdef CONFIG_SYS_OMAP_ABE_SYSCK
+	.abe = abe_dpll_params_sysclk_196608khz,
+#else
+	.abe = &abe_dpll_params_32k_196608khz,
+#endif
+	.usb = usb_dpll_params_1920mhz,
+	.ddr = NULL
+};
+
 struct dplls omap4430_dplls = {
 	.mpu = mpu_dpll_params_1200mhz,
 	.core = core_dpll_params_1600mhz,
@@ -288,17 +302,21 @@ struct vcores_data omap4460_volts = {
 	.mm.pmic = &twl6030,
 };
 
+/*
+ * Take closest integer part of the mV value corresponding to a TWL6032 SMPS
+ * voltage selection code. Aligned with OMAP4470 ES1.0 OCA V.0.7.
+ */
 struct vcores_data omap4470_volts = {
-	.mpu.value = 1200,
+	.mpu.value = 1202,
 	.mpu.addr = SMPS_REG_ADDR_SMPS1,
 	.mpu.pmic = &twl6030,
 
 	.core.value = 1126,
-	.core.addr = SMPS_REG_ADDR_SMPS1,
+	.core.addr = SMPS_REG_ADDR_SMPS2,
 	.core.pmic = &twl6030,
 
-	.mm.value = 1137,
-	.mm.addr = SMPS_REG_ADDR_SMPS1,
+	.mm.value = 1139,
+	.mm.addr = SMPS_REG_ADDR_SMPS5,
 	.mm.pmic = &twl6030,
 };
 
@@ -395,91 +413,6 @@ void enable_basic_uboot_clocks(void)
 			 1);
 }
 
-/*
- * Enable non-essential clock domains, modules and
- * do some additional special settings needed
- */
-void enable_non_essential_clocks(void)
-{
-	u32 const clk_domains_non_essential[] = {
-		(*prcm)->cm_mpu_m3_clkstctrl,
-		(*prcm)->cm_ivahd_clkstctrl,
-		(*prcm)->cm_dsp_clkstctrl,
-		(*prcm)->cm_dss_clkstctrl,
-		(*prcm)->cm_sgx_clkstctrl,
-		(*prcm)->cm1_abe_clkstctrl,
-		(*prcm)->cm_c2c_clkstctrl,
-		(*prcm)->cm_cam_clkstctrl,
-		(*prcm)->cm_dss_clkstctrl,
-		(*prcm)->cm_sdma_clkstctrl,
-		0
-	};
-
-	u32 const clk_modules_hw_auto_non_essential[] = {
-		(*prcm)->cm_l3instr_l3_3_clkctrl,
-		(*prcm)->cm_l3instr_l3_instr_clkctrl,
-		(*prcm)->cm_l3instr_intrconn_wp1_clkctrl,
-		(*prcm)->cm_l3init_hsi_clkctrl,
-		0
-	};
-
-	u32 const clk_modules_explicit_en_non_essential[] = {
-		(*prcm)->cm1_abe_aess_clkctrl,
-		(*prcm)->cm1_abe_pdm_clkctrl,
-		(*prcm)->cm1_abe_dmic_clkctrl,
-		(*prcm)->cm1_abe_mcasp_clkctrl,
-		(*prcm)->cm1_abe_mcbsp1_clkctrl,
-		(*prcm)->cm1_abe_mcbsp2_clkctrl,
-		(*prcm)->cm1_abe_mcbsp3_clkctrl,
-		(*prcm)->cm1_abe_slimbus_clkctrl,
-		(*prcm)->cm1_abe_timer5_clkctrl,
-		(*prcm)->cm1_abe_timer6_clkctrl,
-		(*prcm)->cm1_abe_timer7_clkctrl,
-		(*prcm)->cm1_abe_timer8_clkctrl,
-		(*prcm)->cm1_abe_wdt3_clkctrl,
-		(*prcm)->cm_l4per_gptimer9_clkctrl,
-		(*prcm)->cm_l4per_gptimer10_clkctrl,
-		(*prcm)->cm_l4per_gptimer11_clkctrl,
-		(*prcm)->cm_l4per_gptimer3_clkctrl,
-		(*prcm)->cm_l4per_gptimer4_clkctrl,
-		(*prcm)->cm_l4per_hdq1w_clkctrl,
-		(*prcm)->cm_l4per_mcbsp4_clkctrl,
-		(*prcm)->cm_l4per_mcspi2_clkctrl,
-		(*prcm)->cm_l4per_mcspi3_clkctrl,
-		(*prcm)->cm_l4per_mcspi4_clkctrl,
-		(*prcm)->cm_l4per_mmcsd3_clkctrl,
-		(*prcm)->cm_l4per_mmcsd4_clkctrl,
-		(*prcm)->cm_l4per_mmcsd5_clkctrl,
-		(*prcm)->cm_l4per_uart1_clkctrl,
-		(*prcm)->cm_l4per_uart2_clkctrl,
-		(*prcm)->cm_l4per_uart4_clkctrl,
-		(*prcm)->cm_wkup_keyboard_clkctrl,
-		(*prcm)->cm_wkup_wdtimer2_clkctrl,
-		(*prcm)->cm_cam_iss_clkctrl,
-		(*prcm)->cm_cam_fdif_clkctrl,
-		(*prcm)->cm_dss_dss_clkctrl,
-		(*prcm)->cm_sgx_sgx_clkctrl,
-		0
-	};
-
-	/* Enable optional functional clock for ISS */
-	setbits_le32((*prcm)->cm_cam_iss_clkctrl, ISS_CLKCTRL_OPTFCLKEN_MASK);
-
-	/* Enable all optional functional clocks of DSS */
-	setbits_le32((*prcm)->cm_dss_dss_clkctrl, DSS_CLKCTRL_OPTFCLKEN_MASK);
-
-	do_enable_clocks(clk_domains_non_essential,
-			 clk_modules_hw_auto_non_essential,
-			 clk_modules_explicit_en_non_essential,
-			 0);
-
-	/* Put camera module in no sleep mode */
-	clrsetbits_le32((*prcm)->cm_cam_clkstctrl,
-			MODULE_CLKCTRL_MODULEMODE_MASK,
-			CD_CLKCTRL_CLKTRCTRL_NO_SLEEP <<
-			MODULE_CLKCTRL_MODULEMODE_SHIFT);
-}
-
 void hw_data_init(void)
 {
 	u32 omap_rev = omap_revision();
@@ -494,6 +427,10 @@ void hw_data_init(void)
 	break;
 
 	case OMAP4430_ES2_0:
+	*dplls_data = &omap4430_dplls_es20;
+	*omap_vcores = &omap4430_volts;
+	break;
+
 	case OMAP4430_ES2_1:
 	case OMAP4430_ES2_2:
 	case OMAP4430_ES2_3:
diff --git a/arch/arm/cpu/armv7/omap4/hwinit.c b/arch/arm/cpu/armv7/omap4/hwinit.c
index b0598a0774..db16548fac 100644
--- a/arch/arm/cpu/armv7/omap4/hwinit.c
+++ b/arch/arm/cpu/armv7/omap4/hwinit.c
@@ -15,7 +15,7 @@
 #include <asm/armv7.h>
 #include <asm/arch/cpu.h>
 #include <asm/arch/sys_proto.h>
-#include <asm/sizes.h>
+#include <linux/sizes.h>
 #include <asm/emif.h>
 #include <asm/arch/gpio.h>
 #include <asm/omap_common.h>
diff --git a/arch/arm/cpu/armv7/omap4/sdram_elpida.c b/arch/arm/cpu/armv7/omap4/sdram_elpida.c
index e4c8316370..6903696e1b 100644
--- a/arch/arm/cpu/armv7/omap4/sdram_elpida.c
+++ b/arch/arm/cpu/armv7/omap4/sdram_elpida.c
@@ -32,7 +32,7 @@
 
 #ifdef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
 
-static const struct emif_regs emif_regs_elpida_200_mhz_2cs = {
+const struct emif_regs emif_regs_elpida_200_mhz_2cs = {
 	.sdram_config_init		= 0x80000eb9,
 	.sdram_config			= 0x80001ab9,
 	.ref_ctrl			= 0x0000030c,
@@ -46,7 +46,7 @@ static const struct emif_regs emif_regs_elpida_200_mhz_2cs = {
 	.emif_ddr_phy_ctlr_1		= 0x049ff808
 };
 
-static const struct emif_regs emif_regs_elpida_380_mhz_1cs = {
+const struct emif_regs emif_regs_elpida_380_mhz_1cs = {
 	.sdram_config_init		= 0x80000eb1,
 	.sdram_config			= 0x80001ab1,
 	.ref_ctrl			= 0x000005cd,
@@ -321,3 +321,8 @@ void get_lpddr2_mr_regs(const struct lpddr2_mr_regs **regs)
 {
 	*regs = &mr_regs;
 }
+
+__weak const struct read_write_regs *get_bug_regs(u32 *iterations)
+{
+	return 0;
+}
diff --git a/arch/arm/cpu/armv7/omap5/Makefile b/arch/arm/cpu/armv7/omap5/Makefile
index 168302dd3b..64c68791f1 100644
--- a/arch/arm/cpu/armv7/omap5/Makefile
+++ b/arch/arm/cpu/armv7/omap5/Makefile
@@ -5,30 +5,9 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	=  $(obj)lib$(SOC).o
-
-COBJS	+= hwinit.o
-COBJS	+= emif.o
-COBJS	+= sdram.o
-COBJS	+= prcm-regs.o
-COBJS	+= hw_data.o
-COBJS	+= abb.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS) $(SOBJS))
-
-all:	 $(obj).depend $(LIB)
-
-$(LIB):	$(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	+= hwinit.o
+obj-y	+= emif.o
+obj-y	+= sdram.o
+obj-y	+= prcm-regs.o
+obj-y	+= hw_data.o
+obj-y	+= abb.o
diff --git a/arch/arm/cpu/armv7/omap5/abb.c b/arch/arm/cpu/armv7/omap5/abb.c
index 31b679516f..3bf88979e5 100644
--- a/arch/arm/cpu/armv7/omap5/abb.c
+++ b/arch/arm/cpu/armv7/omap5/abb.c
@@ -28,18 +28,25 @@
 s8 abb_setup_ldovbb(u32 fuse, u32 ldovbb)
 {
 	u32 vset;
+	u32 fuse_enable_mask = OMAP5_ABB_FUSE_ENABLE_MASK;
+	u32 fuse_vset_mask = OMAP5_ABB_FUSE_VSET_MASK;
 
+	if (!is_omap54xx()) {
+		/* DRA7 */
+		fuse_enable_mask = DRA7_ABB_FUSE_ENABLE_MASK;
+		fuse_vset_mask = DRA7_ABB_FUSE_VSET_MASK;
+	}
 	/*
 	 * ABB parameters must be properly fused
 	 * otherwise ABB should be disabled
 	 */
 	vset = readl(fuse);
-	if (!(vset & OMAP5_ABB_FUSE_ENABLE_MASK))
+	if (!(vset & fuse_enable_mask))
 		return -1;
 
 	/* prepare VSET value for LDOVBB mux register */
-	vset &= OMAP5_ABB_FUSE_VSET_MASK;
-	vset >>= ffs(OMAP5_ABB_FUSE_VSET_MASK) - 1;
+	vset &= fuse_vset_mask;
+	vset >>= ffs(fuse_vset_mask) - 1;
 	vset <<= ffs(OMAP5_ABB_LDOVBBMPU_VSET_OUT_MASK) - 1;
 	vset |= OMAP5_ABB_LDOVBBMPU_MUX_CTRL_MASK;
 
diff --git a/arch/arm/cpu/armv7/omap5/config.mk b/arch/arm/cpu/armv7/omap5/config.mk
index 2673af9668..ef2725affa 100644
--- a/arch/arm/cpu/armv7/omap5/config.mk
+++ b/arch/arm/cpu/armv7/omap5/config.mk
@@ -7,7 +7,7 @@
 #
 
 ifdef CONFIG_SPL_BUILD
-ALL-y	+= $(OBJTREE)/MLO
+ALL-y	+= MLO
 else
-ALL-y	+= $(obj)u-boot.img
+ALL-y	+= u-boot.img
 endif
diff --git a/arch/arm/cpu/armv7/omap5/hw_data.c b/arch/arm/cpu/armv7/omap5/hw_data.c
index a1b249e734..ad971327bf 100644
--- a/arch/arm/cpu/armv7/omap5/hw_data.c
+++ b/arch/arm/cpu/armv7/omap5/hw_data.c
@@ -39,17 +39,6 @@ static const struct dpll_params mpu_dpll_params_1_5ghz[NUM_SYS_CLKS] = {
 	{625, 15, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}	/* 38.4 MHz */
 };
 
-/* OPP NOM FREQUENCY for ES2.0, OPP HIGH for ES1.0 */
-static const struct dpll_params mpu_dpll_params_1100mhz[NUM_SYS_CLKS] = {
-	{275, 2, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 12 MHz   */
-	{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 13 MHz   */
-	{1375, 20, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 16.8 MHz */
-	{1375, 23, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 19.2 MHz */
-	{550, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 26 MHz   */
-	{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 27 MHz   */
-	{1375, 47, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}	/* 38.4 MHz */
-};
-
 /* OPP NOM FREQUENCY for ES1.0 */
 static const struct dpll_params mpu_dpll_params_800mhz[NUM_SYS_CLKS] = {
 	{200, 2, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 12 MHz   */
@@ -83,6 +72,7 @@ static const struct dpll_params mpu_dpll_params_499mhz[NUM_SYS_CLKS] = {
 	{493, 37, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}	/* 38.4 MHz */
 };
 
+/* OPP NOM FREQUENCY for OMAP5 ES2.0, and DRA7 ES1.0 */
 static const struct dpll_params mpu_dpll_params_1ghz[NUM_SYS_CLKS] = {
 	{250, 2, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1},		/* 12 MHz   */
 	{500, 9, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1},		/* 20 MHz   */
@@ -169,13 +159,13 @@ static const struct dpll_params per_dpll_params_768mhz_es2[NUM_SYS_CLKS] = {
 };
 
 static const struct dpll_params per_dpll_params_768mhz_dra7xx[NUM_SYS_CLKS] = {
-	{32, 0, 4, 1, 3, 4, 10, 2, -1, -1, -1, -1},		/* 12 MHz   */
+	{32, 0, 4, 1, 3, 4, 4, 2, -1, -1, -1, -1},		/* 12 MHz   */
 	{96, 4, 4, 1, 3, 4, 4, 2, -1, -1, -1, -1},		/* 20 MHz   */
-	{160, 6, 4, 1, 3, 4, 10, 2, -1, -1, -1, -1},		/* 16.8 MHz */
-	{20, 0, 4, 1, 3, 4, 10, 2, -1, -1, -1, -1},		/* 19.2 MHz */
-	{192, 12, 4, 1, 3, 4, 10, 2, -1, -1, -1, -1},		/* 26 MHz   */
+	{160, 6, 4, 1, 3, 4, 4, 2, -1, -1, -1, -1},		/* 16.8 MHz */
+	{20, 0, 4, 1, 3, 4, 4, 2, -1, -1, -1, -1},		/* 19.2 MHz */
+	{192, 12, 4, 1, 3, 4, 4, 2, -1, -1, -1, -1},		/* 26 MHz   */
 	{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 27 MHz   */
-	{10, 0, 4, 1, 3, 4, 10, 2, -1, -1, -1, -1},		/* 38.4 MHz */
+	{10, 0, 4, 1, 3, 4, 4, 2, -1, -1, -1, -1},		/* 38.4 MHz */
 };
 
 static const struct dpll_params iva_dpll_params_2330mhz[NUM_SYS_CLKS] = {
@@ -272,7 +262,7 @@ struct dplls omap5_dplls_es1 = {
 };
 
 struct dplls omap5_dplls_es2 = {
-	.mpu = mpu_dpll_params_1100mhz,
+	.mpu = mpu_dpll_params_1ghz,
 	.core = core_dpll_params_2128mhz_ddr532_es2,
 	.per = per_dpll_params_768mhz_es2,
 	.iva = iva_dpll_params_2330mhz,
@@ -496,94 +486,6 @@ void enable_basic_uboot_clocks(void)
 			 1);
 }
 
-/*
- * Enable non-essential clock domains, modules and
- * do some additional special settings needed
- */
-void enable_non_essential_clocks(void)
-{
-	u32 const clk_domains_non_essential[] = {
-		(*prcm)->cm_mpu_m3_clkstctrl,
-		(*prcm)->cm_ivahd_clkstctrl,
-		(*prcm)->cm_dsp_clkstctrl,
-		(*prcm)->cm_dss_clkstctrl,
-		(*prcm)->cm_sgx_clkstctrl,
-		(*prcm)->cm1_abe_clkstctrl,
-		(*prcm)->cm_c2c_clkstctrl,
-		(*prcm)->cm_cam_clkstctrl,
-		(*prcm)->cm_dss_clkstctrl,
-		(*prcm)->cm_sdma_clkstctrl,
-		0
-	};
-
-	u32 const clk_modules_hw_auto_non_essential[] = {
-		(*prcm)->cm_mpu_m3_mpu_m3_clkctrl,
-		(*prcm)->cm_ivahd_ivahd_clkctrl,
-		(*prcm)->cm_ivahd_sl2_clkctrl,
-		(*prcm)->cm_dsp_dsp_clkctrl,
-		(*prcm)->cm_l3instr_l3_3_clkctrl,
-		(*prcm)->cm_l3instr_l3_instr_clkctrl,
-		(*prcm)->cm_l3instr_intrconn_wp1_clkctrl,
-		(*prcm)->cm_l3init_hsi_clkctrl,
-		(*prcm)->cm_l4per_hdq1w_clkctrl,
-		0
-	};
-
-	u32 const clk_modules_explicit_en_non_essential[] = {
-		(*prcm)->cm1_abe_aess_clkctrl,
-		(*prcm)->cm1_abe_pdm_clkctrl,
-		(*prcm)->cm1_abe_dmic_clkctrl,
-		(*prcm)->cm1_abe_mcasp_clkctrl,
-		(*prcm)->cm1_abe_mcbsp1_clkctrl,
-		(*prcm)->cm1_abe_mcbsp2_clkctrl,
-		(*prcm)->cm1_abe_mcbsp3_clkctrl,
-		(*prcm)->cm1_abe_slimbus_clkctrl,
-		(*prcm)->cm1_abe_timer5_clkctrl,
-		(*prcm)->cm1_abe_timer6_clkctrl,
-		(*prcm)->cm1_abe_timer7_clkctrl,
-		(*prcm)->cm1_abe_timer8_clkctrl,
-		(*prcm)->cm1_abe_wdt3_clkctrl,
-		(*prcm)->cm_l4per_gptimer9_clkctrl,
-		(*prcm)->cm_l4per_gptimer10_clkctrl,
-		(*prcm)->cm_l4per_gptimer11_clkctrl,
-		(*prcm)->cm_l4per_gptimer3_clkctrl,
-		(*prcm)->cm_l4per_gptimer4_clkctrl,
-		(*prcm)->cm_l4per_mcspi2_clkctrl,
-		(*prcm)->cm_l4per_mcspi3_clkctrl,
-		(*prcm)->cm_l4per_mcspi4_clkctrl,
-		(*prcm)->cm_l4per_mmcsd3_clkctrl,
-		(*prcm)->cm_l4per_mmcsd4_clkctrl,
-		(*prcm)->cm_l4per_mmcsd5_clkctrl,
-		(*prcm)->cm_l4per_uart1_clkctrl,
-		(*prcm)->cm_l4per_uart2_clkctrl,
-		(*prcm)->cm_l4per_uart4_clkctrl,
-		(*prcm)->cm_wkup_keyboard_clkctrl,
-		(*prcm)->cm_wkup_wdtimer2_clkctrl,
-		(*prcm)->cm_cam_iss_clkctrl,
-		(*prcm)->cm_cam_fdif_clkctrl,
-		(*prcm)->cm_dss_dss_clkctrl,
-		(*prcm)->cm_sgx_sgx_clkctrl,
-		0
-	};
-
-	/* Enable optional functional clock for ISS */
-	setbits_le32((*prcm)->cm_cam_iss_clkctrl, ISS_CLKCTRL_OPTFCLKEN_MASK);
-
-	/* Enable all optional functional clocks of DSS */
-	setbits_le32((*prcm)->cm_dss_dss_clkctrl, DSS_CLKCTRL_OPTFCLKEN_MASK);
-
-	do_enable_clocks(clk_domains_non_essential,
-			 clk_modules_hw_auto_non_essential,
-			 clk_modules_explicit_en_non_essential,
-			 0);
-
-	/* Put camera module in no sleep mode */
-	clrsetbits_le32((*prcm)->cm_cam_clkstctrl,
-			MODULE_CLKCTRL_MODULEMODE_MASK,
-			CD_CLKCTRL_CLKTRCTRL_NO_SLEEP <<
-			MODULE_CLKCTRL_MODULEMODE_SHIFT);
-}
-
 const struct ctrl_ioregs ioregs_omap5430 = {
 	.ctrl_ddrch = DDR_IO_I_34OHM_SR_FASTEST_WD_DQ_NO_PULL_DQS_PULL_DOWN,
 	.ctrl_lpddr2ch = DDR_IO_I_34OHM_SR_FASTEST_WD_CK_CKE_NCS_CA_PULL_DOWN,
@@ -600,6 +502,7 @@ const struct ctrl_ioregs ioregs_omap5432_es1 = {
 	.ctrl_ddrio_1 = DDR_IO_1_VREF_CELLS_DDR3_VALUE,
 	.ctrl_ddrio_2 = DDR_IO_2_VREF_CELLS_DDR3_VALUE,
 	.ctrl_emif_sdram_config_ext = SDRAM_CONFIG_EXT_RD_LVL_11_SAMPLES,
+	.ctrl_emif_sdram_config_ext_final = SDRAM_CONFIG_EXT_RD_LVL_4_SAMPLES,
 };
 
 const struct ctrl_ioregs ioregs_omap5432_es2 = {
@@ -610,16 +513,18 @@ const struct ctrl_ioregs ioregs_omap5432_es2 = {
 	.ctrl_ddrio_1 = DDR_IO_1_VREF_CELLS_DDR3_VALUE_ES2,
 	.ctrl_ddrio_2 = DDR_IO_2_VREF_CELLS_DDR3_VALUE_ES2,
 	.ctrl_emif_sdram_config_ext = SDRAM_CONFIG_EXT_RD_LVL_11_SAMPLES,
+	.ctrl_emif_sdram_config_ext_final = SDRAM_CONFIG_EXT_RD_LVL_4_SAMPLES,
 };
 
 const struct ctrl_ioregs ioregs_dra7xx_es1 = {
 	.ctrl_ddrch = 0x40404040,
 	.ctrl_lpddr2ch = 0x40404040,
 	.ctrl_ddr3ch = 0x80808080,
-	.ctrl_ddrio_0 = 0xbae8c631,
-	.ctrl_ddrio_1 = 0xb46318d8,
+	.ctrl_ddrio_0 = 0xA2084210,
+	.ctrl_ddrio_1 = 0x84210840,
 	.ctrl_ddrio_2 = 0x84210000,
-	.ctrl_emif_sdram_config_ext = 0xb2c00000,
+	.ctrl_emif_sdram_config_ext = 0x0001C1A7,
+	.ctrl_emif_sdram_config_ext_final = 0x000101A7,
 	.ctrl_ddr_ctrl_ext_0 = 0xA2000000,
 };
 
@@ -646,6 +551,7 @@ void hw_data_init(void)
 	break;
 
 	case DRA752_ES1_0:
+	case DRA752_ES1_1:
 	*prcm = &dra7xx_prcm;
 	*dplls_data = &dra7xx_dplls;
 	*omap_vcores = &dra752_volts;
@@ -673,6 +579,7 @@ void get_ioregs(const struct ctrl_ioregs **regs)
 		*regs = &ioregs_omap5432_es2;
 		break;
 	case DRA752_ES1_0:
+	case DRA752_ES1_1:
 		*regs = &ioregs_dra7xx_es1;
 		break;
 
diff --git a/arch/arm/cpu/armv7/omap5/hwinit.c b/arch/arm/cpu/armv7/omap5/hwinit.c
index 1065891ae1..93feb1623c 100644
--- a/arch/arm/cpu/armv7/omap5/hwinit.c
+++ b/arch/arm/cpu/armv7/omap5/hwinit.c
@@ -17,7 +17,7 @@
 #include <asm/arch/cpu.h>
 #include <asm/arch/sys_proto.h>
 #include <asm/arch/clock.h>
-#include <asm/sizes.h>
+#include <linux/sizes.h>
 #include <asm/utils.h>
 #include <asm/arch/gpio.h>
 #include <asm/emif.h>
@@ -168,12 +168,6 @@ void do_io_settings(void)
 		io_settings_lpddr2();
 	else
 		io_settings_ddr3();
-
-	/* Efuse settings */
-	writel(EFUSE_1, (*ctrl)->control_efuse_1);
-	writel(EFUSE_2, (*ctrl)->control_efuse_2);
-	writel(EFUSE_3, (*ctrl)->control_efuse_3);
-	writel(EFUSE_4, (*ctrl)->control_efuse_4);
 }
 
 static const struct srcomp_params srcomp_parameters[NUM_SYS_CLKS] = {
@@ -297,13 +291,17 @@ void srcomp_enable(void)
 
 void config_data_eye_leveling_samples(u32 emif_base)
 {
+	const struct ctrl_ioregs *ioregs;
+
+	get_ioregs(&ioregs);
+
 	/*EMIF_SDRAM_CONFIG_EXT-Read data eye leveling no of samples =4*/
 	if (emif_base == EMIF1_BASE)
-		writel(SDRAM_CONFIG_EXT_RD_LVL_4_SAMPLES,
-			(*ctrl)->control_emif1_sdram_config_ext);
+		writel(ioregs->ctrl_emif_sdram_config_ext_final,
+		       (*ctrl)->control_emif1_sdram_config_ext);
 	else if (emif_base == EMIF2_BASE)
-		writel(SDRAM_CONFIG_EXT_RD_LVL_4_SAMPLES,
-			(*ctrl)->control_emif2_sdram_config_ext);
+		writel(ioregs->ctrl_emif_sdram_config_ext_final,
+		       (*ctrl)->control_emif2_sdram_config_ext);
 }
 
 void init_omap_revision(void)
@@ -335,6 +333,9 @@ void init_omap_revision(void)
 	case DRA752_CONTROL_ID_CODE_ES1_0:
 		*omap_si_rev = DRA752_ES1_0;
 		break;
+	case DRA752_CONTROL_ID_CODE_ES1_1:
+		*omap_si_rev = DRA752_ES1_1;
+		break;
 	default:
 		*omap_si_rev = OMAP5430_SILICON_ID_INVALID;
 	}
diff --git a/arch/arm/cpu/armv7/omap5/prcm-regs.c b/arch/arm/cpu/armv7/omap5/prcm-regs.c
index 764620d62a..7292161f3c 100644
--- a/arch/arm/cpu/armv7/omap5/prcm-regs.c
+++ b/arch/arm/cpu/armv7/omap5/prcm-regs.c
@@ -203,8 +203,10 @@ struct prcm_regs const omap5_es1_prcm = {
 	.cm_l3init_hsusbotg_clkctrl = 0x4a009360,
 	.cm_l3init_hsusbtll_clkctrl = 0x4a009368,
 	.cm_l3init_p1500_clkctrl = 0x4a009378,
+	.cm_l3init_sata_clkctrl = 0x4a009388,
 	.cm_l3init_fsusb_clkctrl = 0x4a0093d0,
 	.cm_l3init_ocp2scp1_clkctrl = 0x4a0093e0,
+	.cm_l3init_ocp2scp3_clkctrl = 0x4a0093e8,
 
 	/* cm2.l4per */
 	.cm_l4per_clkstctrl = 0x4a009400,
@@ -295,6 +297,8 @@ struct prcm_regs const omap5_es1_prcm = {
 struct omap_sys_ctrl_regs const omap5_ctrl = {
 	.control_status				= 0x4A002134,
 	.control_std_fuse_opp_vdd_mpu_2		= 0x4A0021B4,
+	.control_phy_power_usb 			= 0x4A002370,
+	.control_phy_power_sata			= 0x4A002374,
 	.control_padconf_core_base		= 0x4A002800,
 	.control_paconf_global			= 0x4A002DA0,
 	.control_paconf_mode			= 0x4A002DA4,
@@ -372,6 +376,7 @@ struct omap_sys_ctrl_regs const omap5_ctrl = {
 
 struct omap_sys_ctrl_regs const dra7xx_ctrl = {
 	.control_status				= 0x4A002134,
+	.control_phy_power_sata			= 0x4A002374,
 	.control_core_mac_id_0_lo		= 0x4A002514,
 	.control_core_mac_id_0_hi		= 0x4A002518,
 	.control_core_mac_id_1_lo		= 0x4A00251C,
@@ -427,11 +432,13 @@ struct omap_sys_ctrl_regs const dra7xx_ctrl = {
 	.control_srcomp_code_latch		= 0x4A002E84,
 	.control_ddr_control_ext_0		= 0x4A002E88,
 	.control_padconf_core_base		= 0x4A003400,
+	.control_std_fuse_opp_vdd_mpu_2		= 0x4A003B20,
 	.control_port_emif1_sdram_config	= 0x4AE0C110,
 	.control_port_emif1_lpddr2_nvm_config	= 0x4AE0C114,
 	.control_port_emif2_sdram_config	= 0x4AE0C118,
 	.control_emif1_sdram_config_ext		= 0x4AE0C144,
 	.control_emif2_sdram_config_ext		= 0x4AE0C148,
+	.control_wkup_ldovbb_mpu_voltage_ctrl	= 0x4AE0C158,
 	.control_padconf_mode			= 0x4AE0C5A0,
 	.control_xtal_oscillator		= 0x4AE0C5A4,
 	.control_i2c_2				= 0x4AE0C5A8,
@@ -567,6 +574,7 @@ struct prcm_regs const omap5_es2_prcm = {
 	.cm_div_m2_dpll_unipro = 0x4a0081d0,
 	.cm_ssc_deltamstep_dpll_unipro = 0x4a0081e8,
 	.cm_ssc_modfreqdiv_dpll_unipro = 0x4a0081ec,
+	.cm_coreaon_usb_phy_core_clkctrl = 0x4A008640,
 	.cm_coreaon_bandgap_clkctrl = 0x4a008648,
 	.cm_coreaon_io_srcomp_clkctrl = 0x4a008650,
 
@@ -696,8 +704,11 @@ struct prcm_regs const omap5_es2_prcm = {
 	.cm_l3init_hsusbotg_clkctrl = 0x4a009660,
 	.cm_l3init_hsusbtll_clkctrl = 0x4a009668,
 	.cm_l3init_p1500_clkctrl = 0x4a009678,
+	.cm_l3init_sata_clkctrl = 0x4a009688,
 	.cm_l3init_fsusb_clkctrl = 0x4a0096d0,
 	.cm_l3init_ocp2scp1_clkctrl = 0x4a0096e0,
+	.cm_l3init_ocp2scp3_clkctrl = 0x4a0096e8,
+	.cm_l3init_usb_otg_ss_clkctrl = 0x4a0096f0,
 
 	/* prm irqstatus regs */
 	.prm_irqstatus_mpu_2 = 0x4ae06014,
@@ -789,6 +800,7 @@ struct prcm_regs const dra7xx_prcm = {
 	.cm_clkmode_dpll_dsp			= 0x4a005234,
 	.cm_shadow_freq_config1			= 0x4a005260,
 	.cm_clkmode_dpll_gmac			= 0x4a0052a8,
+	.cm_coreaon_usb_phy2_core_clkctrl = 0x4a008688,
 
 	/* cm1.mpu */
 	.cm_mpu_mpu_clkctrl			= 0x4a005320,
@@ -797,6 +809,9 @@ struct prcm_regs const dra7xx_prcm = {
 	.cm_dsp_clkstctrl			= 0x4a005400,
 	.cm_dsp_dsp_clkctrl			= 0x4a005420,
 
+	/* prm irqstatus regs */
+	.prm_irqstatus_mpu_2			= 0x4ae06014,
+
 	/* cm2.ckgen */
 	.cm_clksel_usb_60mhz			= 0x4a008104,
 	.cm_clkmode_dpll_per			= 0x4a008140,
@@ -886,9 +901,11 @@ struct prcm_regs const dra7xx_prcm = {
 	.cm_l3init_hsusbhost_clkctrl		= 0x4a009340,
 	.cm_l3init_hsusbotg_clkctrl		= 0x4a009348,
 	.cm_l3init_hsusbtll_clkctrl		= 0x4a009350,
+	.cm_l3init_sata_clkctrl			= 0x4a009388,
 	.cm_gmac_clkstctrl			= 0x4a0093c0,
 	.cm_gmac_gmac_clkctrl			= 0x4a0093d0,
 	.cm_l3init_ocp2scp1_clkctrl		= 0x4a0093e0,
+	.cm_l3init_ocp2scp3_clkctrl		= 0x4a0093e8,
 
 	/* cm2.l4per */
 	.cm_l4per_clkstctrl			= 0x4a009700,
@@ -955,4 +972,7 @@ struct prcm_regs const dra7xx_prcm = {
 	.prm_vc_val_bypass			= 0x4ae07da0,
 	.prm_vc_cfg_i2c_mode			= 0x4ae07db4,
 	.prm_vc_cfg_i2c_clk			= 0x4ae07db8,
+
+	.prm_abbldo_mpu_setup			= 0x4AE07DDC,
+	.prm_abbldo_mpu_ctrl			= 0x4AE07DE0,
 };
diff --git a/arch/arm/cpu/armv7/omap5/sdram.c b/arch/arm/cpu/armv7/omap5/sdram.c
index e65c1160e2..16a91f911a 100644
--- a/arch/arm/cpu/armv7/omap5/sdram.c
+++ b/arch/arm/cpu/armv7/omap5/sdram.c
@@ -148,13 +148,13 @@ const struct emif_regs emif_1_regs_ddr3_532_mhz_1cs_dra_es1 = {
 	.read_idle_ctrl                 = 0x00050000,
 	.zq_config                      = 0x0007190B,
 	.temp_alert_config              = 0x00000000,
-	.emif_ddr_phy_ctlr_1_init       = 0x0E20400A,
-	.emif_ddr_phy_ctlr_1            = 0x0E24400A,
-	.emif_ddr_ext_phy_ctrl_1        = 0x04040100,
-	.emif_ddr_ext_phy_ctrl_2        = 0x009E009E,
-	.emif_ddr_ext_phy_ctrl_3        = 0x009E009E,
-	.emif_ddr_ext_phy_ctrl_4        = 0x009E009E,
-	.emif_ddr_ext_phy_ctrl_5        = 0x009E009E,
+	.emif_ddr_phy_ctlr_1_init       = 0x0024400A,
+	.emif_ddr_phy_ctlr_1            = 0x0024400A,
+	.emif_ddr_ext_phy_ctrl_1        = 0x10040100,
+	.emif_ddr_ext_phy_ctrl_2        = 0x00B000B0,
+	.emif_ddr_ext_phy_ctrl_3        = 0x00B000B0,
+	.emif_ddr_ext_phy_ctrl_4        = 0x00B000B0,
+	.emif_ddr_ext_phy_ctrl_5        = 0x00B000B0,
 	.emif_rd_wr_lvl_rmp_win         = 0x00000000,
 	.emif_rd_wr_lvl_rmp_ctl         = 0x80000000,
 	.emif_rd_wr_lvl_ctl             = 0x00000000,
@@ -172,13 +172,13 @@ const struct emif_regs emif_2_regs_ddr3_532_mhz_1cs_dra_es1 = {
 	.read_idle_ctrl                 = 0x00050000,
 	.zq_config                      = 0x0007190B,
 	.temp_alert_config              = 0x00000000,
-	.emif_ddr_phy_ctlr_1_init       = 0x0020400A,
-	.emif_ddr_phy_ctlr_1            = 0x0E24400A,
-	.emif_ddr_ext_phy_ctrl_1        = 0x04040100,
-	.emif_ddr_ext_phy_ctrl_2        = 0x009D009D,
-	.emif_ddr_ext_phy_ctrl_3        = 0x009D009D,
-	.emif_ddr_ext_phy_ctrl_4        = 0x009D009D,
-	.emif_ddr_ext_phy_ctrl_5        = 0x009D009D,
+	.emif_ddr_phy_ctlr_1_init       = 0x0024400A,
+	.emif_ddr_phy_ctlr_1            = 0x0024400A,
+	.emif_ddr_ext_phy_ctrl_1        = 0x10040100,
+	.emif_ddr_ext_phy_ctrl_2        = 0x00B000B0,
+	.emif_ddr_ext_phy_ctrl_3        = 0x00B000B0,
+	.emif_ddr_ext_phy_ctrl_4        = 0x00B000B0,
+	.emif_ddr_ext_phy_ctrl_5        = 0x00B000B0,
 	.emif_rd_wr_lvl_rmp_win         = 0x00000000,
 	.emif_rd_wr_lvl_rmp_ctl         = 0x80000000,
 	.emif_rd_wr_lvl_ctl             = 0x00000000,
@@ -245,6 +245,7 @@ static void emif_get_reg_dump_sdp(u32 emif_nr, const struct emif_regs **regs)
 		*regs = &emif_regs_ddr3_532_mhz_1cs_es2;
 		break;
 	case DRA752_ES1_0:
+	case DRA752_ES1_1:
 		switch (emif_nr) {
 		case 1:
 			*regs = &emif_1_regs_ddr3_532_mhz_1cs_dra_es1;
@@ -273,6 +274,7 @@ static void emif_get_dmm_regs_sdp(const struct dmm_lisa_map_regs
 		*dmm_lisa_regs = &lisa_map_4G_x_2_x_2;
 		break;
 	case DRA752_ES1_0:
+	case DRA752_ES1_1:
 	default:
 		*dmm_lisa_regs = &lisa_map_2G_x_2_x_2_2G_x_1_x_2;
 	}
@@ -306,7 +308,7 @@ void emif_get_device_details(u32 emif_nr,
 
 #endif /* CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS */
 
-const u32 ext_phy_ctrl_const_base[EMIF_EXT_PHY_CTRL_CONST_REG] = {
+const u32 ext_phy_ctrl_const_base[] = {
 	0x01004010,
 	0x00001004,
 	0x04010040,
@@ -329,7 +331,7 @@ const u32 ext_phy_ctrl_const_base[EMIF_EXT_PHY_CTRL_CONST_REG] = {
 	0x0
 };
 
-const u32 ddr3_ext_phy_ctrl_const_base_es1[EMIF_EXT_PHY_CTRL_CONST_REG] = {
+const u32 ddr3_ext_phy_ctrl_const_base_es1[] = {
 	0x01004010,
 	0x00001004,
 	0x04010040,
@@ -352,7 +354,7 @@ const u32 ddr3_ext_phy_ctrl_const_base_es1[EMIF_EXT_PHY_CTRL_CONST_REG] = {
 	0x0
 };
 
-const u32 ddr3_ext_phy_ctrl_const_base_es2[EMIF_EXT_PHY_CTRL_CONST_REG] = {
+const u32 ddr3_ext_phy_ctrl_const_base_es2[] = {
 	0x50D4350D,
 	0x00000D43,
 	0x04010040,
@@ -376,51 +378,61 @@ const u32 ddr3_ext_phy_ctrl_const_base_es2[EMIF_EXT_PHY_CTRL_CONST_REG] = {
 };
 
 const u32
-dra_ddr3_ext_phy_ctrl_const_base_es1_emif1[EMIF_EXT_PHY_CTRL_CONST_REG] = {
-	0x009E009E,
-	0x002E002E,
-	0x002E002E,
-	0x002E002E,
-	0x002E002E,
-	0x002E002E,
-	0x004D004D,
-	0x004D004D,
-	0x004D004D,
-	0x004D004D,
-	0x004D004D,
-	0x004D004D,
-	0x004D004D,
-	0x004D004D,
-	0x004D004D,
-	0x004D004D,
-	0x0,
-	0x600020,
+dra_ddr3_ext_phy_ctrl_const_base_es1_emif1[] = {
+	0x00B000B0,
+	0x00400040,
+	0x00400040,
+	0x00400040,
+	0x00400040,
+	0x00400040,
+	0x00800080,
+	0x00800080,
+	0x00800080,
+	0x00800080,
+	0x00800080,
+	0x00600060,
+	0x00600060,
+	0x00600060,
+	0x00600060,
+	0x00600060,
+	0x00800080,
+	0x00800080,
 	0x40010080,
-	0x8102040
+	0x08102040,
+	0x0,
+	0x0,
+	0x0,
+	0x0,
+	0x0
 };
 
 const u32
-dra_ddr3_ext_phy_ctrl_const_base_es1_emif2[EMIF_EXT_PHY_CTRL_CONST_REG] = {
-	0x009D009D,
-	0x002D002D,
-	0x002D002D,
-	0x002D002D,
-	0x002D002D,
-	0x002D002D,
-	0x00570057,
-	0x00570057,
-	0x00570057,
-	0x00570057,
-	0x00570057,
-	0x00570057,
-	0x00570057,
-	0x00570057,
-	0x00570057,
-	0x00570057,
+dra_ddr3_ext_phy_ctrl_const_base_es1_emif2[] = {
+	0x00BB00BB,
+	0x00440044,
+	0x00440044,
+	0x00440044,
+	0x00440044,
+	0x00440044,
+	0x007F007F,
+	0x007F007F,
+	0x007F007F,
+	0x007F007F,
+	0x007F007F,
+	0x00600060,
+	0x00600060,
+	0x00600060,
+	0x00600060,
+	0x00600060,
 	0x0,
-	0x600020,
+	0x00600020,
 	0x40010080,
-	0x8102040
+	0x08102040,
+	0x0,
+	0x0,
+	0x0,
+	0x0,
+	0x0
 };
 
 const struct lpddr2_mr_regs mr_regs = {
@@ -431,27 +443,39 @@ const struct lpddr2_mr_regs mr_regs = {
 	.mr16	= MR16_REF_FULL_ARRAY
 };
 
-static void emif_get_ext_phy_ctrl_const_regs(u32 emif_nr, const u32 **regs)
+static void emif_get_ext_phy_ctrl_const_regs(u32 emif_nr,
+					     const u32 **regs,
+					     u32 *size)
 {
 	switch (omap_revision()) {
 	case OMAP5430_ES1_0:
 	case OMAP5430_ES2_0:
 		*regs = ext_phy_ctrl_const_base;
+		*size = ARRAY_SIZE(ext_phy_ctrl_const_base);
 		break;
 	case OMAP5432_ES1_0:
 		*regs = ddr3_ext_phy_ctrl_const_base_es1;
+		*size = ARRAY_SIZE(ddr3_ext_phy_ctrl_const_base_es1);
 		break;
 	case OMAP5432_ES2_0:
 		*regs = ddr3_ext_phy_ctrl_const_base_es2;
+		*size = ARRAY_SIZE(ddr3_ext_phy_ctrl_const_base_es2);
 		break;
 	case DRA752_ES1_0:
-		if (emif_nr == 1)
+	case DRA752_ES1_1:
+		if (emif_nr == 1) {
 			*regs = dra_ddr3_ext_phy_ctrl_const_base_es1_emif1;
-		else
+			*size =
+			ARRAY_SIZE(dra_ddr3_ext_phy_ctrl_const_base_es1_emif1);
+		} else {
 			*regs = dra_ddr3_ext_phy_ctrl_const_base_es1_emif2;
+			*size =
+			ARRAY_SIZE(dra_ddr3_ext_phy_ctrl_const_base_es1_emif2);
+		}
 		break;
 	default:
 		*regs = ddr3_ext_phy_ctrl_const_base_es2;
+		*size = ARRAY_SIZE(ddr3_ext_phy_ctrl_const_base_es2);
 
 	}
 }
@@ -468,6 +492,7 @@ void do_ext_phy_settings(u32 base, const struct emif_regs *regs)
 	u32 emif_nr;
 	const u32 *ext_phy_ctrl_const_regs;
 	u32 i = 0;
+	u32 size;
 
 	emif_nr = (base == EMIF1_BASE) ? 1 : 2;
 
@@ -487,8 +512,10 @@ void do_ext_phy_settings(u32 base, const struct emif_regs *regs)
 	 * external phy 6-24 registers do not change with
 	 * ddr frequency
 	 */
-	emif_get_ext_phy_ctrl_const_regs(emif_nr, &ext_phy_ctrl_const_regs);
-	for (i = 0; i < EMIF_EXT_PHY_CTRL_CONST_REG; i++) {
+	emif_get_ext_phy_ctrl_const_regs(emif_nr,
+					 &ext_phy_ctrl_const_regs, &size);
+
+	for (i = 0; i < size; i++) {
 		writel(ext_phy_ctrl_const_regs[i],
 		       emif_ext_phy_ctrl_base++);
 		/* Update shadow registers */
@@ -545,6 +572,75 @@ static const struct lpddr2_device_timings dev_4G_S4_timings = {
 	.min_tck	= &min_tck,
 };
 
+/*
+ * List of status registers to be controlled back to control registers
+ * after initial leveling
+ * readreg, writereg
+ */
+const struct read_write_regs omap5_bug_00339_regs[] = {
+	{ 8,  5 },
+	{ 9,  6 },
+	{ 10, 7 },
+	{ 14, 8 },
+	{ 15, 9 },
+	{ 16, 10 },
+	{ 11, 2 },
+	{ 12, 3 },
+	{ 13, 4 },
+	{ 17, 11 },
+	{ 18, 12 },
+	{ 19, 13 },
+};
+
+const struct read_write_regs dra_bug_00339_regs[] = {
+	{ 7,  7 },
+	{ 8,  8 },
+	{ 9,  9 },
+	{ 10, 10 },
+	{ 11, 11 },
+	{ 12, 2 },
+	{ 13, 3 },
+	{ 14, 4 },
+	{ 15, 5 },
+	{ 16, 6 },
+	{ 17, 12 },
+	{ 18, 13 },
+	{ 19, 14 },
+	{ 20, 15 },
+	{ 21, 16 },
+	{ 22, 17 },
+	{ 23, 18 },
+	{ 24, 19 },
+	{ 25, 20 },
+	{ 26, 21}
+};
+
+const struct read_write_regs *get_bug_regs(u32 *iterations)
+{
+	const struct read_write_regs *bug_00339_regs_ptr = NULL;
+
+	switch (omap_revision()) {
+	case OMAP5430_ES1_0:
+	case OMAP5430_ES2_0:
+	case OMAP5432_ES1_0:
+	case OMAP5432_ES2_0:
+		bug_00339_regs_ptr = omap5_bug_00339_regs;
+		*iterations = sizeof(omap5_bug_00339_regs)/
+			     sizeof(omap5_bug_00339_regs[0]);
+		break;
+	case DRA752_ES1_0:
+	case DRA752_ES1_1:
+		bug_00339_regs_ptr = dra_bug_00339_regs;
+		*iterations = sizeof(dra_bug_00339_regs)/
+			     sizeof(dra_bug_00339_regs[0]);
+		break;
+	default:
+		printf("\n Error: UnKnown SOC");
+	}
+
+	return bug_00339_regs_ptr;
+}
+
 void emif_get_device_timings_sdp(u32 emif_nr,
 		const struct lpddr2_device_timings **cs0_device_timings,
 		const struct lpddr2_device_timings **cs1_device_timings)
diff --git a/arch/arm/cpu/armv7/rmobile/Makefile b/arch/arm/cpu/armv7/rmobile/Makefile
index 41bceb1cf5..22219990dd 100644
--- a/arch/arm/cpu/armv7/rmobile/Makefile
+++ b/arch/arm/cpu/armv7/rmobile/Makefile
@@ -5,44 +5,13 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(SOC).o
-
-SOBJS = lowlevel_init.o
-COBJS-y += cpu_info.o
-COBJS-y += emac.o
-
-COBJS-$(CONFIG_DISPLAY_BOARDINFO) += board.o
-COBJS-$(CONFIG_GLOBAL_TIMER) += timer.o
-COBJS-$(CONFIG_R8A7740) += cpu_info-r8a7740.o
-COBJS-$(CONFIG_R8A7740) += pfc-r8a7740.o
-COBJS-$(CONFIG_SH73A0) += cpu_info-sh73a0.o
-COBJS-$(CONFIG_SH73A0) += pfc-sh73a0.o
-COBJS_LN-$(CONFIG_TMU_TIMER) += sh_timer.o
-
-COBJS	:= $(COBJS-y)
-SRCS    := $(SOBJS:.o=.S) $(COBJS:.o=.c)
-SRCS    := $(SOBJS:.o=.S) $(COBJS:.o=.c) $(addprefix $(obj),$(COBJS_LN-y:.o=.c))
-OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS) $(COBJS_LN-y))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-START	:= $(addprefix $(obj),$(START))
-
-all:	$(obj).depend $(LIB)
-
-$(LIB):	$(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-# from arch/sh/lib/ directory
-$(obj)sh_timer.c:
-	@rm -f $(obj)sh_timer.c
-	ln -s $(SRCTREE)/arch/sh/lib/time.c $(obj)sh_timer.c
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y = cpu_info.o
+obj-y += emac.o
+
+obj-$(CONFIG_DISPLAY_BOARDINFO) += board.o
+obj-$(CONFIG_GLOBAL_TIMER) += timer.o
+obj-$(CONFIG_R8A7740) += lowlevel_init.o cpu_info-r8a7740.o pfc-r8a7740.o
+obj-$(CONFIG_R8A7790) += lowlevel_init_ca15.o cpu_info-r8a7790.o pfc-r8a7790.o
+obj-$(CONFIG_R8A7791) += lowlevel_init_ca15.o cpu_info-r8a7791.o pfc-r8a7791.o
+obj-$(CONFIG_SH73A0) += lowlevel_init.o cpu_info-sh73a0.o pfc-sh73a0.o
+obj-$(CONFIG_TMU_TIMER) += ../../../../sh/lib/time.o
diff --git a/arch/arm/cpu/armv7/rmobile/config.mk b/arch/arm/cpu/armv7/rmobile/config.mk
deleted file mode 100644
index 3a36ab65e1..0000000000
--- a/arch/arm/cpu/armv7/rmobile/config.mk
+++ /dev/null
@@ -1,9 +0,0 @@
-#
-# (C) Copyright 2002
-# Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-# Make ARMv5 to allow more compilers to work, even though its v7a.
-PLATFORM_CPPFLAGS += -march=armv5
diff --git a/arch/arm/cpu/armv7/rmobile/cpu_info-r8a7790.c b/arch/arm/cpu/armv7/rmobile/cpu_info-r8a7790.c
new file mode 100644
index 0000000000..7232e23774
--- /dev/null
+++ b/arch/arm/cpu/armv7/rmobile/cpu_info-r8a7790.c
@@ -0,0 +1,22 @@
+/*
+ * arch/arm/cpu/armv7/rmobile/cpu_info-r8a7790.c
+ *     This file is r8a7790 processor support.
+ *
+ * Copyright (C) 2013 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+#include <common.h>
+#include <asm/io.h>
+
+#define PRR 0xFF000044
+
+u32 rmobile_get_cpu_type(void)
+{
+	return (readl(PRR) & 0x00007F00) >> 8;
+}
+
+u32 rmobile_get_cpu_rev_integer(void)
+{
+	return (readl(PRR) & 0x000000F0) >> 4;
+}
diff --git a/arch/arm/cpu/armv7/rmobile/cpu_info-r8a7791.c b/arch/arm/cpu/armv7/rmobile/cpu_info-r8a7791.c
new file mode 100644
index 0000000000..2de58ed273
--- /dev/null
+++ b/arch/arm/cpu/armv7/rmobile/cpu_info-r8a7791.c
@@ -0,0 +1,29 @@
+/*
+ * arch/arm/cpu/armv7/rmobile/cpu_info-r8a7791.c
+ *
+ * Copyright (C) 2013 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+#include <common.h>
+#include <asm/io.h>
+
+#define PRR 0xFF000044
+
+u32 rmobile_get_cpu_type(void)
+{
+	u32 product;
+
+	product = readl(PRR);
+
+	return (u32)((product & 0x00007F00) >> 8);
+}
+
+u32 rmobile_get_cpu_rev_integer(void)
+{
+	u32 product;
+
+	product = readl(PRR);
+
+	return (u32)((product & 0x000000F0) >> 4);
+}
diff --git a/arch/arm/cpu/armv7/rmobile/cpu_info.c b/arch/arm/cpu/armv7/rmobile/cpu_info.c
index 07a33fb2ae..83d5282e3e 100644
--- a/arch/arm/cpu/armv7/rmobile/cpu_info.c
+++ b/arch/arm/cpu/armv7/rmobile/cpu_info.c
@@ -58,6 +58,16 @@ int print_cpuinfo(void)
 		       rmobile_get_cpu_rev_fraction());
 		break;
 
+	case 0x45:
+		printf("CPU: Renesas Electronics R8A7790 rev %d\n",
+		       rmobile_get_cpu_rev_integer());
+		break;
+
+	case 0x47:
+		printf("CPU: Renesas Electronics R8A7791 rev %d\n",
+			rmobile_get_cpu_rev_integer());
+		break;
+
 	default:
 		printf("CPU: Renesas Electronics CPU rev %d.%d\n",
 		       rmobile_get_cpu_rev_integer(),
diff --git a/arch/arm/cpu/armv7/rmobile/lowlevel_init_ca15.S b/arch/arm/cpu/armv7/rmobile/lowlevel_init_ca15.S
new file mode 100644
index 0000000000..e07cc8093a
--- /dev/null
+++ b/arch/arm/cpu/armv7/rmobile/lowlevel_init_ca15.S
@@ -0,0 +1,60 @@
+/*
+ * arch/arm/cpu/armv7/rmobile/lowlevel_init_ca15.S
+ *     This file is lager low level initialize.
+ *
+ * Copyright (C) 2013 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <config.h>
+#include <linux/linkage.h>
+
+ENTRY(lowlevel_init)
+	mrc	p15, 0, r4, c0, c0, 5 /* mpidr */
+	orr	r4, r4, r4, lsr #6
+	and	r4, r4, #7 /* id 0-3 = ca15.0,1,2,3 */
+
+	b do_lowlevel_init
+
+	.pool
+
+/*
+ * CPU ID #1-#3 come here
+ */
+	.align  4
+do_cpu_waiting:
+	ldr	r1, =0xe6180000 /* sysc */
+1:	ldr	r0, [r1, #0x20] /* sbar */
+	tst	r0, r0
+	beq	1b
+	bx	r0
+
+/*
+ * Only CPU ID #0 comes here
+ */
+	.align  4
+do_lowlevel_init:
+	/* surpress wfe if ca15 */
+	tst	r4, #4
+	mrceq p15, 0, r0, c1, c0, 1	/* actlr */
+	orreq r0, r0, #(1<<7)
+	mcreq p15, 0, r0, c1, c0, 1
+	/* and set l2 latency */
+	mrceq p15, 1, r0, c9, c0, 2	/* l2ctlr */
+	orreq r0, r0, #0x00000800
+	orreq r0, r0, #0x00000003
+	mcreq p15, 1, r0, c9, c0, 2
+
+	ldr	r3, =(CONFIG_SYS_INIT_SP_ADDR)
+	sub	sp, r3, #4
+	str	lr, [sp]
+
+	/* initialize system */
+	bl s_init
+
+	ldr	lr, [sp]
+	mov	pc, lr
+	nop
+ENDPROC(lowlevel_init)
+	.ltorg
diff --git a/arch/arm/cpu/armv7/rmobile/pfc-r8a7790.c b/arch/arm/cpu/armv7/rmobile/pfc-r8a7790.c
new file mode 100644
index 0000000000..1259062a64
--- /dev/null
+++ b/arch/arm/cpu/armv7/rmobile/pfc-r8a7790.c
@@ -0,0 +1,829 @@
+/*
+ * arch/arm/cpu/armv7/rmobile/pfc-r8a7790.c
+ *     This file is r8a7790 processor support - PFC hardware block.
+ *
+ * Copy from linux-kernel:drivers/pinctrl/sh-pfc/pfc-r8a7790.c
+ *
+ * Copyright (C) 2013 Renesas Electronics Corporation
+ * Copyright (C) 2013 Magnus Damm
+ * Copyright (C) 2012 Renesas Solutions Corp.
+ * Copyright (C) 2012 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <common.h>
+#include <sh_pfc.h>
+#include <asm/gpio.h>
+#include "pfc-r8a7790.h"
+
+enum {
+	PINMUX_RESERVED = 0,
+
+	PINMUX_DATA_BEGIN,
+	GP_ALL(DATA),
+	PINMUX_DATA_END,
+
+	PINMUX_INPUT_BEGIN,
+	GP_ALL(IN),
+	PINMUX_INPUT_END,
+
+	PINMUX_OUTPUT_BEGIN,
+	GP_ALL(OUT),
+	PINMUX_OUTPUT_END,
+
+	PINMUX_FUNCTION_BEGIN,
+	GP_ALL(FN),
+
+	/* GPSR0 */
+	FN_IP0_2_0, FN_IP0_5_3, FN_IP0_8_6, FN_IP0_11_9, FN_IP0_15_12,
+	FN_IP0_19_16, FN_IP0_22_20, FN_IP0_26_23, FN_IP0_30_27,
+	FN_IP1_3_0, FN_IP1_7_4, FN_IP1_11_8, FN_IP1_14_12,
+	FN_IP1_17_15, FN_IP1_21_18, FN_IP1_25_22, FN_IP1_27_26,
+	FN_IP1_29_28, FN_IP2_2_0, FN_IP2_5_3, FN_IP2_8_6, FN_IP2_11_9,
+	FN_IP2_14_12, FN_IP2_17_15, FN_IP2_21_18, FN_IP2_25_22,
+	FN_IP2_28_26, FN_IP3_3_0, FN_IP3_7_4, FN_IP3_11_8,
+	FN_IP3_14_12, FN_IP3_17_15,
+
+	/* GPSR1 */
+	FN_IP3_19_18, FN_IP3_22_20, FN_IP3_25_23, FN_IP3_28_26,
+	FN_IP3_31_29, FN_IP4_2_0, FN_IP4_5_3, FN_IP4_8_6, FN_IP4_11_9,
+	FN_IP4_14_12, FN_IP4_17_15, FN_IP4_20_18, FN_IP4_23_21,
+	FN_IP4_26_24, FN_IP4_29_27, FN_IP5_2_0, FN_IP5_5_3, FN_IP5_9_6,
+	FN_IP5_12_10, FN_IP5_14_13, FN_IP5_17_15, FN_IP5_20_18,
+	FN_IP5_23_21, FN_IP5_26_24, FN_IP5_29_27, FN_IP6_2_0,
+	FN_IP6_5_3, FN_IP6_8_6, FN_IP6_10_9, FN_IP6_13_11,
+
+	/* GPSR2 */
+	FN_IP7_28_27, FN_IP7_30_29, FN_IP8_1_0, FN_IP8_3_2, FN_IP8_5_4,
+	FN_IP8_7_6, FN_IP8_9_8, FN_IP8_11_10, FN_IP8_13_12, FN_IP8_15_14,
+	FN_IP8_17_16, FN_IP8_19_18, FN_IP8_21_20, FN_IP8_23_22,
+	FN_IP8_25_24, FN_IP8_26, FN_IP8_27, FN_VI1_DATA7_VI1_B7,
+	FN_IP6_16_14, FN_IP6_19_17, FN_IP6_22_20, FN_IP6_25_23,
+	FN_IP6_28_26, FN_IP6_31_29, FN_IP7_2_0, FN_IP7_5_3, FN_IP7_7_6,
+	FN_IP7_9_8, FN_IP7_12_10, FN_IP7_15_13,
+
+	/* GPSR3 */
+	FN_IP8_28, FN_IP8_30_29, FN_IP9_1_0, FN_IP9_3_2, FN_IP9_5_4,
+	FN_IP9_7_6, FN_IP9_11_8, FN_IP9_15_12, FN_IP9_17_16, FN_IP9_19_18,
+	FN_IP9_21_20, FN_IP9_23_22, FN_IP9_25_24, FN_IP9_27_26,
+	FN_IP9_31_28, FN_IP10_3_0, FN_IP10_6_4, FN_IP10_10_7, FN_IP10_14_11,
+	FN_IP10_18_15, FN_IP10_22_19, FN_IP10_25_23, FN_IP10_29_26,
+	FN_IP11_3_0, FN_IP11_4, FN_IP11_6_5, FN_IP11_8_7, FN_IP11_10_9,
+	FN_IP11_12_11, FN_IP11_14_13, FN_IP11_17_15, FN_IP11_21_18,
+
+	/* GPSR4 */
+	FN_IP11_23_22, FN_IP11_26_24, FN_IP11_29_27, FN_IP11_31_30,
+	FN_IP12_1_0, FN_IP12_3_2, FN_IP12_5_4, FN_IP12_7_6, FN_IP12_10_8,
+	FN_IP12_13_11, FN_IP12_16_14, FN_IP12_19_17, FN_IP12_22_20,
+	FN_IP12_24_23, FN_IP12_27_25, FN_IP12_30_28, FN_IP13_2_0,
+	FN_IP13_6_3, FN_IP13_9_7, FN_IP13_12_10, FN_IP13_15_13,
+	FN_IP13_18_16, FN_IP13_22_19, FN_IP13_25_23, FN_IP13_28_26,
+	FN_IP13_30_29, FN_IP14_2_0, FN_IP14_5_3, FN_IP14_8_6, FN_IP14_11_9,
+	FN_IP14_15_12, FN_IP14_18_16,
+
+	/* GPSR5 */
+	FN_IP14_21_19, FN_IP14_24_22, FN_IP14_27_25, FN_IP14_30_28,
+	FN_IP15_2_0, FN_IP15_5_3, FN_IP15_8_6, FN_IP15_11_9, FN_IP15_13_12,
+	FN_IP15_15_14, FN_IP15_17_16, FN_IP15_19_18, FN_IP15_22_20,
+	FN_IP15_25_23, FN_IP15_27_26, FN_IP15_29_28, FN_IP16_2_0,
+	FN_IP16_5_3, FN_USB0_PWEN, FN_USB0_OVC_VBUS, FN_IP16_6, FN_IP16_7,
+	FN_USB2_PWEN, FN_USB2_OVC, FN_AVS1, FN_AVS2, FN_DU_DOTCLKIN0,
+	FN_IP7_26_25, FN_DU_DOTCLKIN2, FN_IP7_18_16, FN_IP7_21_19, FN_IP7_24_22,
+
+	/* IPSR0 - IPSR5 */
+	/* IPSR6 */
+	FN_DACK0, FN_IRQ0, FN_INTC_IRQ0_N, FN_SSI_SCK6_B,
+	FN_VI1_VSYNC_N, FN_VI1_VSYNC_N_B, FN_SSI_WS78_C,
+	FN_DREQ1_N, FN_VI1_CLKENB, FN_VI1_CLKENB_B,
+	FN_SSI_SDATA7_C, FN_SSI_SCK78_B, FN_DACK1, FN_IRQ1,
+	FN_INTC_IRQ1_N, FN_SSI_WS6_B, FN_SSI_SDATA8_C,
+	FN_DREQ2_N, FN_HSCK1_B, FN_HCTS0_N_B,
+	FN_MSIOF0_TXD_B, FN_DACK2, FN_IRQ2, FN_INTC_IRQ2_N,
+	FN_SSI_SDATA6_B, FN_HRTS0_N_B, FN_MSIOF0_RXD_B,
+	FN_ETH_CRS_DV, FN_RMII_CRS_DV, FN_STP_ISCLK_0_B,
+	FN_TS_SDEN0_D, FN_GLO_Q0_C, FN_SCL2_E,
+	FN_SCL2_CIS_E, FN_ETH_RX_ER, FN_RMII_RX_ER,
+	FN_STP_ISD_0_B, FN_TS_SPSYNC0_D, FN_GLO_Q1_C,
+	FN_SDA2_E, FN_SDA2_CIS_E, FN_ETH_RXD0, FN_RMII_RXD0,
+	FN_STP_ISEN_0_B, FN_TS_SDAT0_D, FN_GLO_I0_C,
+	FN_SCIFB1_SCK_G, FN_SCK1_E, FN_ETH_RXD1,
+	FN_RMII_RXD1, FN_HRX0_E, FN_STP_ISSYNC_0_B,
+	FN_TS_SCK0_D, FN_GLO_I1_C, FN_SCIFB1_RXD_G,
+	FN_RX1_E, FN_ETH_LINK, FN_RMII_LINK, FN_HTX0_E,
+	FN_STP_IVCXO27_0_B, FN_SCIFB1_TXD_G, FN_TX1_E,
+	FN_ETH_REF_CLK, FN_RMII_REF_CLK, FN_HCTS0_N_E,
+	FN_STP_IVCXO27_1_B, FN_HRX0_F,
+
+	/* IPSR7 */
+	FN_ETH_MDIO, FN_RMII_MDIO, FN_HRTS0_N_E,
+	FN_SIM0_D_C, FN_HCTS0_N_F, FN_ETH_TXD1,
+	FN_RMII_TXD1, FN_HTX0_F, FN_BPFCLK_G, FN_RDS_CLK_F,
+	FN_ETH_TX_EN, FN_RMII_TX_EN, FN_SIM0_CLK_C,
+	FN_HRTS0_N_F, FN_ETH_MAGIC, FN_RMII_MAGIC,
+	FN_SIM0_RST_C, FN_ETH_TXD0, FN_RMII_TXD0,
+	FN_STP_ISCLK_1_B, FN_TS_SDEN1_C, FN_GLO_SCLK_C,
+	FN_ETH_MDC, FN_RMII_MDC, FN_STP_ISD_1_B,
+	FN_TS_SPSYNC1_C, FN_GLO_SDATA_C, FN_PWM0,
+	FN_SCIFA2_SCK_C, FN_STP_ISEN_1_B, FN_TS_SDAT1_C,
+	FN_GLO_SS_C, FN_PWM1, FN_SCIFA2_TXD_C,
+	FN_STP_ISSYNC_1_B, FN_TS_SCK1_C, FN_GLO_RFON_C,
+	FN_PCMOE_N, FN_PWM2, FN_PWMFSW0, FN_SCIFA2_RXD_C,
+	FN_PCMWE_N, FN_IECLK_C, FN_DU1_DOTCLKIN,
+	FN_AUDIO_CLKC, FN_AUDIO_CLKOUT_C, FN_VI0_CLK,
+	FN_ATACS00_N, FN_AVB_RXD1, FN_MII_RXD1,
+	FN_VI0_DATA0_VI0_B0, FN_ATACS10_N, FN_AVB_RXD2,
+	FN_MII_RXD2,
+
+	/* IPSR8 - IPSR16 */
+
+	FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2, FN_SEL_SCIF1_3,
+	FN_SEL_SCIF1_4,
+	FN_SEL_SCIFB_0, FN_SEL_SCIFB_1, FN_SEL_SCIFB_2,
+	FN_SEL_SCIFB2_0, FN_SEL_SCIFB2_1, FN_SEL_SCIFB2_2,
+	FN_SEL_SCIFB1_0, FN_SEL_SCIFB1_1, FN_SEL_SCIFB1_2, FN_SEL_SCIFB1_3,
+	FN_SEL_SCIFB1_4,
+	FN_SEL_SCIFB1_5, FN_SEL_SCIFB1_6,
+	FN_SEL_SCIFA1_0, FN_SEL_SCIFA1_1, FN_SEL_SCIFA1_2, FN_SEL_SCIFA1_3,
+	FN_SEL_SCIF0_0, FN_SEL_SCIF0_1,
+	FN_SEL_SCFA_0, FN_SEL_SCFA_1,
+	FN_SEL_SOF1_0, FN_SEL_SOF1_1,
+	FN_SEL_SSI7_0, FN_SEL_SSI7_1, FN_SEL_SSI7_2,
+	FN_SEL_SSI6_0, FN_SEL_SSI6_1,
+	FN_SEL_SSI5_0, FN_SEL_SSI5_1, FN_SEL_SSI5_2,
+	FN_SEL_VI3_0, FN_SEL_VI3_1,
+	FN_SEL_VI2_0, FN_SEL_VI2_1,
+	FN_SEL_VI1_0, FN_SEL_VI1_1,
+	FN_SEL_VI0_0, FN_SEL_VI0_1,
+	FN_SEL_TSIF1_0, FN_SEL_TSIF1_1, FN_SEL_TSIF1_2,
+	FN_SEL_LBS_0, FN_SEL_LBS_1,
+	FN_SEL_TSIF0_0, FN_SEL_TSIF0_1, FN_SEL_TSIF0_2, FN_SEL_TSIF0_3,
+	FN_SEL_SOF3_0, FN_SEL_SOF3_1,
+	FN_SEL_SOF0_0, FN_SEL_SOF0_1,
+
+	FN_SEL_TMU1_0, FN_SEL_TMU1_1,
+	FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1,
+	FN_SEL_SCIFCLK_0, FN_SEL_SCIFCLK_1,
+	FN_SEL_CAN0_0, FN_SEL_CAN0_1, FN_SEL_CAN0_2, FN_SEL_CAN0_3,
+	FN_SEL_CANCLK_0, FN_SEL_CANCLK_1,
+	FN_SEL_SCIFA2_0, FN_SEL_SCIFA2_1, FN_SEL_SCIFA2_2,
+	FN_SEL_CAN1_0, FN_SEL_CAN1_1,
+	FN_SEL_ADI_0, FN_SEL_ADI_1,
+	FN_SEL_SSP_0, FN_SEL_SSP_1,
+	FN_SEL_FM_0, FN_SEL_FM_1, FN_SEL_FM_2, FN_SEL_FM_3,
+	FN_SEL_FM_4, FN_SEL_FM_5, FN_SEL_FM_6,
+	FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1, FN_SEL_HSCIF0_2, FN_SEL_HSCIF0_3,
+	FN_SEL_HSCIF0_4, FN_SEL_HSCIF0_5,
+	FN_SEL_GPS_0, FN_SEL_GPS_1, FN_SEL_GPS_2,
+	FN_SEL_RDS_0, FN_SEL_RDS_1, FN_SEL_RDS_2,
+	FN_SEL_RDS_3, FN_SEL_RDS_4, FN_SEL_RDS_5,
+	FN_SEL_SIM_0, FN_SEL_SIM_1, FN_SEL_SIM_2,
+	FN_SEL_SSI8_0, FN_SEL_SSI8_1, FN_SEL_SSI8_2,
+
+	FN_SEL_IICDVFS_0, FN_SEL_IICDVFS_1,
+	FN_SEL_IIC0_0, FN_SEL_IIC0_1,
+	FN_SEL_IEB_0, FN_SEL_IEB_1, FN_SEL_IEB_2,
+	FN_SEL_IIC2_0, FN_SEL_IIC2_1, FN_SEL_IIC2_2, FN_SEL_IIC2_3,
+	FN_SEL_IIC2_4,
+	FN_SEL_IIC1_0, FN_SEL_IIC1_1, FN_SEL_IIC1_2,
+	FN_SEL_I2C2_0, FN_SEL_I2C2_1, FN_SEL_I2C2_2, FN_SEL_I2C2_3,
+	FN_SEL_I2C2_4,
+	FN_SEL_I2C1_0, FN_SEL_I2C1_1, FN_SEL_I2C1_2,
+
+	PINMUX_FUNCTION_END,
+
+	PINMUX_MARK_BEGIN,
+
+	DACK0_MARK, IRQ0_MARK, INTC_IRQ0_N_MARK, SSI_SCK6_B_MARK,
+	VI1_VSYNC_N_MARK, VI1_VSYNC_N_B_MARK, SSI_WS78_C_MARK,
+	DREQ1_N_MARK, VI1_CLKENB_MARK, VI1_CLKENB_B_MARK,
+	SSI_SDATA7_C_MARK, SSI_SCK78_B_MARK, DACK1_MARK, IRQ1_MARK,
+	INTC_IRQ1_N_MARK, SSI_WS6_B_MARK, SSI_SDATA8_C_MARK,
+	DREQ2_N_MARK, HSCK1_B_MARK, HCTS0_N_B_MARK,
+	MSIOF0_TXD_B_MARK, DACK2_MARK, IRQ2_MARK, INTC_IRQ2_N_MARK,
+	SSI_SDATA6_B_MARK, HRTS0_N_B_MARK, MSIOF0_RXD_B_MARK,
+	ETH_CRS_DV_MARK, RMII_CRS_DV_MARK, STP_ISCLK_0_B_MARK,
+	TS_SDEN0_D_MARK, GLO_Q0_C_MARK, SCL2_E_MARK,
+	SCL2_CIS_E_MARK, ETH_RX_ER_MARK, RMII_RX_ER_MARK,
+	STP_ISD_0_B_MARK, TS_SPSYNC0_D_MARK, GLO_Q1_C_MARK,
+	SDA2_E_MARK, SDA2_CIS_E_MARK, ETH_RXD0_MARK, RMII_RXD0_MARK,
+	STP_ISEN_0_B_MARK, TS_SDAT0_D_MARK, GLO_I0_C_MARK,
+	SCIFB1_SCK_G_MARK, SCK1_E_MARK, ETH_RXD1_MARK,
+	RMII_RXD1_MARK, HRX0_E_MARK, STP_ISSYNC_0_B_MARK,
+	TS_SCK0_D_MARK, GLO_I1_C_MARK, SCIFB1_RXD_G_MARK,
+	RX1_E_MARK, ETH_LINK_MARK, RMII_LINK_MARK, HTX0_E_MARK,
+	STP_IVCXO27_0_B_MARK, SCIFB1_TXD_G_MARK, TX1_E_MARK,
+	ETH_REF_CLK_MARK, RMII_REF_CLK_MARK, HCTS0_N_E_MARK,
+	STP_IVCXO27_1_B_MARK, HRX0_F_MARK,
+
+	ETH_MDIO_MARK, RMII_MDIO_MARK, HRTS0_N_E_MARK,
+	SIM0_D_C_MARK, HCTS0_N_F_MARK, ETH_TXD1_MARK,
+	RMII_TXD1_MARK, HTX0_F_MARK, BPFCLK_G_MARK, RDS_CLK_F_MARK,
+	ETH_TX_EN_MARK, RMII_TX_EN_MARK, SIM0_CLK_C_MARK,
+	HRTS0_N_F_MARK, ETH_MAGIC_MARK, RMII_MAGIC_MARK,
+	SIM0_RST_C_MARK, ETH_TXD0_MARK, RMII_TXD0_MARK,
+	STP_ISCLK_1_B_MARK, TS_SDEN1_C_MARK, GLO_SCLK_C_MARK,
+	ETH_MDC_MARK, RMII_MDC_MARK, STP_ISD_1_B_MARK,
+	TS_SPSYNC1_C_MARK, GLO_SDATA_C_MARK, PWM0_MARK,
+	SCIFA2_SCK_C_MARK, STP_ISEN_1_B_MARK, TS_SDAT1_C_MARK,
+	GLO_SS_C_MARK, PWM1_MARK, SCIFA2_TXD_C_MARK,
+	STP_ISSYNC_1_B_MARK, TS_SCK1_C_MARK, GLO_RFON_C_MARK,
+	PCMOE_N_MARK, PWM2_MARK, PWMFSW0_MARK, SCIFA2_RXD_C_MARK,
+	PCMWE_N_MARK, IECLK_C_MARK, DU1_DOTCLKIN_MARK,
+	AUDIO_CLKC_MARK, AUDIO_CLKOUT_C_MARK, VI0_CLK_MARK,
+	ATACS00_N_MARK, AVB_RXD1_MARK, MII_RXD1_MARK,
+	VI0_DATA0_VI0_B0_MARK, ATACS10_N_MARK, AVB_RXD2_MARK,
+	MII_RXD2_MARK,
+
+	PINMUX_MARK_END,
+};
+
+static pinmux_enum_t pinmux_data[] = {
+	PINMUX_DATA_GP_ALL(), /* PINMUX_DATA(GP_M_N_DATA, GP_M_N_FN...), */
+
+	PINMUX_IPSR_DATA(IP6_2_0, DACK0),
+	PINMUX_IPSR_DATA(IP6_2_0, IRQ0),
+	PINMUX_IPSR_DATA(IP6_2_0, INTC_IRQ0_N),
+	PINMUX_IPSR_MODSEL_DATA(IP6_2_0, SSI_SCK6_B, SEL_SSI6_1),
+	PINMUX_IPSR_MODSEL_DATA(IP6_2_0, VI1_VSYNC_N, SEL_VI1_0),
+	PINMUX_IPSR_MODSEL_DATA(IP6_2_0, VI1_VSYNC_N_B, SEL_VI1_1),
+	PINMUX_IPSR_MODSEL_DATA(IP6_2_0, SSI_WS78_C, SEL_SSI7_2),
+	PINMUX_IPSR_DATA(IP6_5_3, DREQ1_N),
+	PINMUX_IPSR_MODSEL_DATA(IP6_5_3, VI1_CLKENB, SEL_VI1_0),
+	PINMUX_IPSR_MODSEL_DATA(IP6_5_3, VI1_CLKENB_B, SEL_VI1_1),
+	PINMUX_IPSR_MODSEL_DATA(IP6_5_3, SSI_SDATA7_C, SEL_SSI7_2),
+	PINMUX_IPSR_MODSEL_DATA(IP6_5_3, SSI_SCK78_B, SEL_SSI7_1),
+	PINMUX_IPSR_DATA(IP6_8_6, DACK1),
+	PINMUX_IPSR_DATA(IP6_8_6, IRQ1),
+	PINMUX_IPSR_DATA(IP6_8_6, INTC_IRQ1_N),
+	PINMUX_IPSR_MODSEL_DATA(IP6_8_6, SSI_WS6_B, SEL_SSI6_1),
+	PINMUX_IPSR_MODSEL_DATA(IP6_8_6, SSI_SDATA8_C, SEL_SSI8_2),
+	PINMUX_IPSR_DATA(IP6_10_9, DREQ2_N),
+	PINMUX_IPSR_MODSEL_DATA(IP6_10_9, HSCK1_B, SEL_HSCIF1_1),
+	PINMUX_IPSR_MODSEL_DATA(IP6_10_9, HCTS0_N_B, SEL_HSCIF0_1),
+	PINMUX_IPSR_MODSEL_DATA(IP6_10_9, MSIOF0_TXD_B, SEL_SOF0_1),
+	PINMUX_IPSR_DATA(IP6_13_11, DACK2),
+	PINMUX_IPSR_DATA(IP6_13_11, IRQ2),
+	PINMUX_IPSR_DATA(IP6_13_11, INTC_IRQ2_N),
+	PINMUX_IPSR_MODSEL_DATA(IP6_13_11, SSI_SDATA6_B, SEL_SSI6_1),
+	PINMUX_IPSR_MODSEL_DATA(IP6_13_11, HRTS0_N_B, SEL_HSCIF0_1),
+	PINMUX_IPSR_MODSEL_DATA(IP6_13_11, MSIOF0_RXD_B, SEL_SOF0_1),
+	PINMUX_IPSR_DATA(IP6_16_14, ETH_CRS_DV),
+	PINMUX_IPSR_DATA(IP6_16_14, RMII_CRS_DV),
+	PINMUX_IPSR_MODSEL_DATA(IP6_16_14, STP_ISCLK_0_B, SEL_SSP_1),
+	PINMUX_IPSR_MODSEL_DATA(IP6_16_14, TS_SDEN0_D, SEL_TSIF0_3),
+	PINMUX_IPSR_MODSEL_DATA(IP6_16_14, GLO_Q0_C, SEL_GPS_2),
+	PINMUX_IPSR_MODSEL_DATA(IP6_16_14, SCL2_E, SEL_IIC2_4),
+	PINMUX_IPSR_MODSEL_DATA(IP6_16_14, SCL2_CIS_E, SEL_I2C2_4),
+	PINMUX_IPSR_DATA(IP6_19_17, ETH_RX_ER),
+	PINMUX_IPSR_DATA(IP6_19_17, RMII_RX_ER),
+	PINMUX_IPSR_MODSEL_DATA(IP6_19_17, STP_ISD_0_B, SEL_SSP_1),
+	PINMUX_IPSR_MODSEL_DATA(IP6_19_17, TS_SPSYNC0_D, SEL_TSIF0_3),
+	PINMUX_IPSR_MODSEL_DATA(IP6_19_17, GLO_Q1_C, SEL_GPS_2),
+	PINMUX_IPSR_MODSEL_DATA(IP6_19_17, SDA2_E, SEL_IIC2_4),
+	PINMUX_IPSR_MODSEL_DATA(IP6_19_17, SDA2_CIS_E, SEL_I2C2_4),
+	PINMUX_IPSR_DATA(IP6_22_20, ETH_RXD0),
+	PINMUX_IPSR_DATA(IP6_22_20, RMII_RXD0),
+	PINMUX_IPSR_MODSEL_DATA(IP6_22_20, STP_ISEN_0_B, SEL_SSP_1),
+	PINMUX_IPSR_MODSEL_DATA(IP6_22_20, TS_SDAT0_D, SEL_TSIF0_3),
+	PINMUX_IPSR_MODSEL_DATA(IP6_22_20, GLO_I0_C, SEL_GPS_2),
+	PINMUX_IPSR_MODSEL_DATA(IP6_22_20, SCIFB1_SCK_G, SEL_SCIFB1_6),
+	PINMUX_IPSR_MODSEL_DATA(IP6_22_20, SCK1_E, SEL_SCIF1_4),
+	PINMUX_IPSR_DATA(IP6_25_23, ETH_RXD1),
+	PINMUX_IPSR_DATA(IP6_25_23, RMII_RXD1),
+	PINMUX_IPSR_MODSEL_DATA(IP6_25_23, HRX0_E, SEL_HSCIF0_4),
+	PINMUX_IPSR_MODSEL_DATA(IP6_25_23, STP_ISSYNC_0_B, SEL_SSP_1),
+	PINMUX_IPSR_MODSEL_DATA(IP6_25_23, TS_SCK0_D, SEL_TSIF0_3),
+	PINMUX_IPSR_MODSEL_DATA(IP6_25_23, GLO_I1_C, SEL_GPS_2),
+	PINMUX_IPSR_MODSEL_DATA(IP6_25_23, SCIFB1_RXD_G, SEL_SCIFB1_6),
+	PINMUX_IPSR_MODSEL_DATA(IP6_25_23, RX1_E, SEL_SCIF1_4),
+	PINMUX_IPSR_DATA(IP6_28_26, ETH_LINK),
+	PINMUX_IPSR_DATA(IP6_28_26, RMII_LINK),
+	PINMUX_IPSR_MODSEL_DATA(IP6_28_26, HTX0_E, SEL_HSCIF0_4),
+	PINMUX_IPSR_MODSEL_DATA(IP6_28_26, STP_IVCXO27_0_B, SEL_SSP_1),
+	PINMUX_IPSR_MODSEL_DATA(IP6_28_26, SCIFB1_TXD_G, SEL_SCIFB1_6),
+	PINMUX_IPSR_MODSEL_DATA(IP6_28_26, TX1_E, SEL_SCIF1_4),
+	PINMUX_IPSR_DATA(IP6_31_29, ETH_REF_CLK),
+	PINMUX_IPSR_DATA(IP6_31_29, RMII_REF_CLK),
+	PINMUX_IPSR_MODSEL_DATA(IP6_31_29, HCTS0_N_E, SEL_HSCIF0_4),
+	PINMUX_IPSR_MODSEL_DATA(IP6_31_29, STP_IVCXO27_1_B, SEL_SSP_1),
+	PINMUX_IPSR_MODSEL_DATA(IP6_31_29, HRX0_F, SEL_HSCIF0_5),
+
+	PINMUX_IPSR_DATA(IP7_2_0, ETH_MDIO),
+	PINMUX_IPSR_DATA(IP7_2_0, RMII_MDIO),
+	PINMUX_IPSR_MODSEL_DATA(IP7_2_0, HRTS0_N_E, SEL_HSCIF0_4),
+	PINMUX_IPSR_MODSEL_DATA(IP7_2_0, SIM0_D_C, SEL_SIM_2),
+	PINMUX_IPSR_MODSEL_DATA(IP7_2_0, HCTS0_N_F, SEL_HSCIF0_5),
+	PINMUX_IPSR_DATA(IP7_5_3, ETH_TXD1),
+	PINMUX_IPSR_DATA(IP7_5_3, RMII_TXD1),
+	PINMUX_IPSR_MODSEL_DATA(IP7_5_3, HTX0_F, SEL_HSCIF0_4),
+	PINMUX_IPSR_MODSEL_DATA(IP7_5_3, BPFCLK_G, SEL_SIM_2),
+	PINMUX_IPSR_MODSEL_DATA(IP7_5_3, RDS_CLK_F, SEL_HSCIF0_5),
+	PINMUX_IPSR_DATA(IP7_7_6, ETH_TX_EN),
+	PINMUX_IPSR_DATA(IP7_7_6, RMII_TX_EN),
+	PINMUX_IPSR_MODSEL_DATA(IP7_7_6, SIM0_CLK_C, SEL_SIM_2),
+	PINMUX_IPSR_MODSEL_DATA(IP7_7_6, HRTS0_N_F, SEL_HSCIF0_5),
+	PINMUX_IPSR_DATA(IP7_9_8, ETH_MAGIC),
+	PINMUX_IPSR_DATA(IP7_9_8, RMII_MAGIC),
+	PINMUX_IPSR_MODSEL_DATA(IP7_9_8, SIM0_RST_C, SEL_SIM_2),
+	PINMUX_IPSR_DATA(IP7_12_10, ETH_TXD0),
+	PINMUX_IPSR_DATA(IP7_12_10, RMII_TXD0),
+	PINMUX_IPSR_MODSEL_DATA(IP7_12_10, STP_ISCLK_1_B, SEL_SSP_1),
+	PINMUX_IPSR_MODSEL_DATA(IP7_12_10, TS_SDEN1_C, SEL_TSIF1_2),
+	PINMUX_IPSR_MODSEL_DATA(IP7_12_10, GLO_SCLK_C, SEL_GPS_2),
+	PINMUX_IPSR_DATA(IP7_15_13, ETH_MDC),
+	PINMUX_IPSR_DATA(IP7_15_13, RMII_MDC),
+	PINMUX_IPSR_MODSEL_DATA(IP7_15_13, STP_ISD_1_B, SEL_SSP_1),
+	PINMUX_IPSR_MODSEL_DATA(IP7_15_13, TS_SPSYNC1_C, SEL_TSIF1_2),
+	PINMUX_IPSR_MODSEL_DATA(IP7_15_13, GLO_SDATA_C, SEL_GPS_2),
+	PINMUX_IPSR_DATA(IP7_18_16, PWM0),
+	PINMUX_IPSR_MODSEL_DATA(IP7_18_16, SCIFA2_SCK_C, SEL_SCIFA2_2),
+	PINMUX_IPSR_MODSEL_DATA(IP7_18_16, STP_ISEN_1_B, SEL_SSP_1),
+	PINMUX_IPSR_MODSEL_DATA(IP7_18_16, TS_SDAT1_C, SEL_TSIF1_2),
+	PINMUX_IPSR_MODSEL_DATA(IP7_18_16, GLO_SS_C, SEL_GPS_2),
+	PINMUX_IPSR_DATA(IP7_21_19, PWM1),
+	PINMUX_IPSR_MODSEL_DATA(IP7_21_19, SCIFA2_TXD_C, SEL_SCIFA2_2),
+	PINMUX_IPSR_MODSEL_DATA(IP7_21_19, STP_ISSYNC_1_B, SEL_SSP_1),
+	PINMUX_IPSR_MODSEL_DATA(IP7_21_19, TS_SCK1_C, SEL_TSIF1_2),
+	PINMUX_IPSR_MODSEL_DATA(IP7_21_19, GLO_RFON_C, SEL_GPS_2),
+	PINMUX_IPSR_DATA(IP7_21_19, PCMOE_N),
+	PINMUX_IPSR_DATA(IP7_24_22, PWM2),
+	PINMUX_IPSR_DATA(IP7_24_22, PWMFSW0),
+	PINMUX_IPSR_MODSEL_DATA(IP7_24_22, SCIFA2_RXD_C, SEL_SCIFA2_2),
+	PINMUX_IPSR_DATA(IP7_24_22, PCMWE_N),
+	PINMUX_IPSR_MODSEL_DATA(IP7_24_22, IECLK_C, SEL_IEB_2),
+	PINMUX_IPSR_DATA(IP7_26_25, DU1_DOTCLKIN),
+	PINMUX_IPSR_DATA(IP7_26_25, AUDIO_CLKC),
+	PINMUX_IPSR_DATA(IP7_26_25, AUDIO_CLKOUT_C),
+	PINMUX_IPSR_MODSEL_DATA(IP7_28_27, VI0_CLK, SEL_VI0_0),
+	PINMUX_IPSR_DATA(IP7_28_27, ATACS00_N),
+	PINMUX_IPSR_DATA(IP7_28_27, AVB_RXD1),
+	PINMUX_IPSR_DATA(IP7_28_27, MII_RXD1),
+	PINMUX_IPSR_MODSEL_DATA(IP7_30_29, VI0_DATA0_VI0_B0, SEL_VI0_0),
+	PINMUX_IPSR_DATA(IP7_30_29, ATACS10_N),
+	PINMUX_IPSR_DATA(IP7_30_29, AVB_RXD2),
+	PINMUX_IPSR_DATA(IP7_30_29, MII_RXD2),
+
+};
+
+static struct pinmux_gpio pinmux_gpios[] = {
+	PINMUX_GPIO_GP_ALL(),
+
+	/*IPSR0 - IPSR5*/
+	/*IPSR6*/
+	GPIO_FN(DACK0), GPIO_FN(IRQ0), GPIO_FN(INTC_IRQ0_N),
+	GPIO_FN(SSI_SCK6_B), GPIO_FN(VI1_VSYNC_N), GPIO_FN(VI1_VSYNC_N_B),
+	GPIO_FN(SSI_WS78_C), GPIO_FN(DREQ1_N), GPIO_FN(VI1_CLKENB),
+	GPIO_FN(VI1_CLKENB_B), GPIO_FN(SSI_SDATA7_C), GPIO_FN(SSI_SCK78_B),
+	GPIO_FN(DACK1), GPIO_FN(IRQ1), GPIO_FN(INTC_IRQ1_N), GPIO_FN(SSI_WS6_B),
+	GPIO_FN(SSI_SDATA8_C), GPIO_FN(DREQ2_N), GPIO_FN(HSCK1_B),
+	GPIO_FN(HCTS0_N_B), GPIO_FN(MSIOF0_TXD_B), GPIO_FN(DACK2),
+	GPIO_FN(IRQ2), GPIO_FN(INTC_IRQ2_N), GPIO_FN(SSI_SDATA6_B),
+	GPIO_FN(HRTS0_N_B), GPIO_FN(MSIOF0_RXD_B), GPIO_FN(ETH_CRS_DV),
+	GPIO_FN(RMII_CRS_DV), GPIO_FN(STP_ISCLK_0_B), GPIO_FN(TS_SDEN0_D),
+	GPIO_FN(GLO_Q0_C), GPIO_FN(SCL2_E), GPIO_FN(SCL2_CIS_E),
+	GPIO_FN(ETH_RX_ER), GPIO_FN(RMII_RX_ER), GPIO_FN(STP_ISD_0_B),
+	GPIO_FN(TS_SPSYNC0_D), GPIO_FN(GLO_Q1_C), GPIO_FN(SDA2_E),
+	GPIO_FN(SDA2_CIS_E), GPIO_FN(ETH_RXD0), GPIO_FN(RMII_RXD0),
+	GPIO_FN(STP_ISEN_0_B), GPIO_FN(TS_SDAT0_D), GPIO_FN(GLO_I0_C),
+	GPIO_FN(SCIFB1_SCK_G), GPIO_FN(SCK1_E), GPIO_FN(ETH_RXD1),
+	GPIO_FN(RMII_RXD1), GPIO_FN(HRX0_E), GPIO_FN(STP_ISSYNC_0_B),
+	GPIO_FN(TS_SCK0_D), GPIO_FN(GLO_I1_C), GPIO_FN(SCIFB1_RXD_G),
+	GPIO_FN(RX1_E), GPIO_FN(ETH_LINK), GPIO_FN(RMII_LINK), GPIO_FN(HTX0_E),
+	GPIO_FN(STP_IVCXO27_0_B), GPIO_FN(SCIFB1_TXD_G), GPIO_FN(TX1_E),
+	GPIO_FN(ETH_REF_CLK), GPIO_FN(RMII_REF_CLK), GPIO_FN(HCTS0_N_E),
+	GPIO_FN(STP_IVCXO27_1_B), GPIO_FN(HRX0_F),
+
+	/*IPSR7*/
+	GPIO_FN(ETH_MDIO), GPIO_FN(RMII_MDIO), GPIO_FN(HRTS0_N_E),
+	GPIO_FN(SIM0_D_C), GPIO_FN(HCTS0_N_F), GPIO_FN(ETH_TXD1),
+	GPIO_FN(RMII_TXD1), GPIO_FN(HTX0_F), GPIO_FN(BPFCLK_G),
+	GPIO_FN(RDS_CLK_F), GPIO_FN(ETH_TX_EN), GPIO_FN(RMII_TX_EN),
+	GPIO_FN(SIM0_CLK_C), GPIO_FN(HRTS0_N_F), GPIO_FN(ETH_MAGIC),
+	GPIO_FN(RMII_MAGIC), GPIO_FN(SIM0_RST_C), GPIO_FN(ETH_TXD0),
+	GPIO_FN(RMII_TXD0), GPIO_FN(STP_ISCLK_1_B), GPIO_FN(TS_SDEN1_C),
+	GPIO_FN(GLO_SCLK_C), GPIO_FN(ETH_MDC), GPIO_FN(RMII_MDC),
+	GPIO_FN(STP_ISD_1_B), GPIO_FN(TS_SPSYNC1_C), GPIO_FN(GLO_SDATA_C),
+	GPIO_FN(PWM0), GPIO_FN(SCIFA2_SCK_C), GPIO_FN(STP_ISEN_1_B),
+	GPIO_FN(TS_SDAT1_C), GPIO_FN(GLO_SS_C), GPIO_FN(PWM1),
+	GPIO_FN(SCIFA2_TXD_C), GPIO_FN(STP_ISSYNC_1_B), GPIO_FN(TS_SCK1_C),
+	GPIO_FN(GLO_RFON_C), GPIO_FN(PCMOE_N), GPIO_FN(PWM2), GPIO_FN(PWMFSW0),
+	GPIO_FN(SCIFA2_RXD_C), GPIO_FN(PCMWE_N), GPIO_FN(IECLK_C),
+	GPIO_FN(DU1_DOTCLKIN), GPIO_FN(AUDIO_CLKC), GPIO_FN(AUDIO_CLKOUT_C),
+	GPIO_FN(VI0_CLK), GPIO_FN(ATACS00_N), GPIO_FN(AVB_RXD1),
+	GPIO_FN(MII_RXD1), GPIO_FN(VI0_DATA0_VI0_B0), GPIO_FN(ATACS10_N),
+	GPIO_FN(AVB_RXD2), GPIO_FN(MII_RXD2),
+	/*IPSR8 - IPSR16*/
+};
+
+static struct pinmux_cfg_reg pinmux_config_regs[] = {
+	{ PINMUX_CFG_REG("GPSR0", 0xE6060004, 32, 1) {
+		GP_0_31_FN, FN_IP3_17_15,
+		GP_0_30_FN, FN_IP3_14_12,
+		GP_0_29_FN, FN_IP3_11_8,
+		GP_0_28_FN, FN_IP3_7_4,
+		GP_0_27_FN, FN_IP3_3_0,
+		GP_0_26_FN, FN_IP2_28_26,
+		GP_0_25_FN, FN_IP2_25_22,
+		GP_0_24_FN, FN_IP2_21_18,
+		GP_0_23_FN, FN_IP2_17_15,
+		GP_0_22_FN, FN_IP2_14_12,
+		GP_0_21_FN, FN_IP2_11_9,
+		GP_0_20_FN, FN_IP2_8_6,
+		GP_0_19_FN, FN_IP2_5_3,
+		GP_0_18_FN, FN_IP2_2_0,
+		GP_0_17_FN, FN_IP1_29_28,
+		GP_0_16_FN, FN_IP1_27_26,
+		GP_0_15_FN, FN_IP1_25_22,
+		GP_0_14_FN, FN_IP1_21_18,
+		GP_0_13_FN, FN_IP1_17_15,
+		GP_0_12_FN, FN_IP1_14_12,
+		GP_0_11_FN, FN_IP1_11_8,
+		GP_0_10_FN, FN_IP1_7_4,
+		GP_0_9_FN, FN_IP1_3_0,
+		GP_0_8_FN, FN_IP0_30_27,
+		GP_0_7_FN, FN_IP0_26_23,
+		GP_0_6_FN, FN_IP0_22_20,
+		GP_0_5_FN, FN_IP0_19_16,
+		GP_0_4_FN, FN_IP0_15_12,
+		GP_0_3_FN, FN_IP0_11_9,
+		GP_0_2_FN, FN_IP0_8_6,
+		GP_0_1_FN, FN_IP0_5_3,
+		GP_0_0_FN, FN_IP0_2_0 }
+	},
+	{ PINMUX_CFG_REG("GPSR1", 0xE6060008, 32, 1) {
+		0, 0,
+		0, 0,
+		GP_1_29_FN, FN_IP6_13_11,
+		GP_1_28_FN, FN_IP6_10_9,
+		GP_1_27_FN, FN_IP6_8_6,
+		GP_1_26_FN, FN_IP6_5_3,
+		GP_1_25_FN, FN_IP6_2_0,
+		GP_1_24_FN, FN_IP5_29_27,
+		GP_1_23_FN, FN_IP5_26_24,
+		GP_1_22_FN, FN_IP5_23_21,
+		GP_1_21_FN, FN_IP5_20_18,
+		GP_1_20_FN, FN_IP5_17_15,
+		GP_1_19_FN, FN_IP5_14_13,
+		GP_1_18_FN, FN_IP5_12_10,
+		GP_1_17_FN, FN_IP5_9_6,
+		GP_1_16_FN, FN_IP5_5_3,
+		GP_1_15_FN, FN_IP5_2_0,
+		GP_1_14_FN, FN_IP4_29_27,
+		GP_1_13_FN, FN_IP4_26_24,
+		GP_1_12_FN, FN_IP4_23_21,
+		GP_1_11_FN, FN_IP4_20_18,
+		GP_1_10_FN, FN_IP4_17_15,
+		GP_1_9_FN, FN_IP4_14_12,
+		GP_1_8_FN, FN_IP4_11_9,
+		GP_1_7_FN, FN_IP4_8_6,
+		GP_1_6_FN, FN_IP4_5_3,
+		GP_1_5_FN, FN_IP4_2_0,
+		GP_1_4_FN, FN_IP3_31_29,
+		GP_1_3_FN, FN_IP3_28_26,
+		GP_1_2_FN, FN_IP3_25_23,
+		GP_1_1_FN, FN_IP3_22_20,
+		GP_1_0_FN, FN_IP3_19_18, }
+	},
+	{ PINMUX_CFG_REG("GPSR2", 0xE606000C, 32, 1) {
+		0, 0,
+		0, 0,
+		GP_2_29_FN, FN_IP7_15_13,
+		GP_2_28_FN, FN_IP7_12_10,
+		GP_2_27_FN, FN_IP7_9_8,
+		GP_2_26_FN, FN_IP7_7_6,
+		GP_2_25_FN, FN_IP7_5_3,
+		GP_2_24_FN, FN_IP7_2_0,
+		GP_2_23_FN, FN_IP6_31_29,
+		GP_2_22_FN, FN_IP6_28_26,
+		GP_2_21_FN, FN_IP6_25_23,
+		GP_2_20_FN, FN_IP6_22_20,
+		GP_2_19_FN, FN_IP6_19_17,
+		GP_2_18_FN, FN_IP6_16_14,
+		GP_2_17_FN, FN_VI1_DATA7_VI1_B7,
+		GP_2_16_FN, FN_IP8_27,
+		GP_2_15_FN, FN_IP8_26,
+		GP_2_14_FN, FN_IP8_25_24,
+		GP_2_13_FN, FN_IP8_23_22,
+		GP_2_12_FN, FN_IP8_21_20,
+		GP_2_11_FN, FN_IP8_19_18,
+		GP_2_10_FN, FN_IP8_17_16,
+		GP_2_9_FN, FN_IP8_15_14,
+		GP_2_8_FN, FN_IP8_13_12,
+		GP_2_7_FN, FN_IP8_11_10,
+		GP_2_6_FN, FN_IP8_9_8,
+		GP_2_5_FN, FN_IP8_7_6,
+		GP_2_4_FN, FN_IP8_5_4,
+		GP_2_3_FN, FN_IP8_3_2,
+		GP_2_2_FN, FN_IP8_1_0,
+		GP_2_1_FN, FN_IP7_30_29,
+		GP_2_0_FN, FN_IP7_28_27 }
+	},
+	{ PINMUX_CFG_REG("GPSR3", 0xE6060010, 32, 1) {
+		GP_3_31_FN, FN_IP11_21_18,
+		GP_3_30_FN, FN_IP11_17_15,
+		GP_3_29_FN, FN_IP11_14_13,
+		GP_3_28_FN, FN_IP11_12_11,
+		GP_3_27_FN, FN_IP11_10_9,
+		GP_3_26_FN, FN_IP11_8_7,
+		GP_3_25_FN, FN_IP11_6_5,
+		GP_3_24_FN, FN_IP11_4,
+		GP_3_23_FN, FN_IP11_3_0,
+		GP_3_22_FN, FN_IP10_29_26,
+		GP_3_21_FN, FN_IP10_25_23,
+		GP_3_20_FN, FN_IP10_22_19,
+		GP_3_19_FN, FN_IP10_18_15,
+		GP_3_18_FN, FN_IP10_14_11,
+		GP_3_17_FN, FN_IP10_10_7,
+		GP_3_16_FN, FN_IP10_6_4,
+		GP_3_15_FN, FN_IP10_3_0,
+		GP_3_14_FN, FN_IP9_31_28,
+		GP_3_13_FN, FN_IP9_27_26,
+		GP_3_12_FN, FN_IP9_25_24,
+		GP_3_11_FN, FN_IP9_23_22,
+		GP_3_10_FN, FN_IP9_21_20,
+		GP_3_9_FN, FN_IP9_19_18,
+		GP_3_8_FN, FN_IP9_17_16,
+		GP_3_7_FN, FN_IP9_15_12,
+		GP_3_6_FN, FN_IP9_11_8,
+		GP_3_5_FN, FN_IP9_7_6,
+		GP_3_4_FN, FN_IP9_5_4,
+		GP_3_3_FN, FN_IP9_3_2,
+		GP_3_2_FN, FN_IP9_1_0,
+		GP_3_1_FN, FN_IP8_30_29,
+		GP_3_0_FN, FN_IP8_28 }
+	},
+	{ PINMUX_CFG_REG("GPSR4", 0xE6060014, 32, 1) {
+		GP_4_31_FN, FN_IP14_18_16,
+		GP_4_30_FN, FN_IP14_15_12,
+		GP_4_29_FN, FN_IP14_11_9,
+		GP_4_28_FN, FN_IP14_8_6,
+		GP_4_27_FN, FN_IP14_5_3,
+		GP_4_26_FN, FN_IP14_2_0,
+		GP_4_25_FN, FN_IP13_30_29,
+		GP_4_24_FN, FN_IP13_28_26,
+		GP_4_23_FN, FN_IP13_25_23,
+		GP_4_22_FN, FN_IP13_22_19,
+		GP_4_21_FN, FN_IP13_18_16,
+		GP_4_20_FN, FN_IP13_15_13,
+		GP_4_19_FN, FN_IP13_12_10,
+		GP_4_18_FN, FN_IP13_9_7,
+		GP_4_17_FN, FN_IP13_6_3,
+		GP_4_16_FN, FN_IP13_2_0,
+		GP_4_15_FN, FN_IP12_30_28,
+		GP_4_14_FN, FN_IP12_27_25,
+		GP_4_13_FN, FN_IP12_24_23,
+		GP_4_12_FN, FN_IP12_22_20,
+		GP_4_11_FN, FN_IP12_19_17,
+		GP_4_10_FN, FN_IP12_16_14,
+		GP_4_9_FN, FN_IP12_13_11,
+		GP_4_8_FN, FN_IP12_10_8,
+		GP_4_7_FN, FN_IP12_7_6,
+		GP_4_6_FN, FN_IP12_5_4,
+		GP_4_5_FN, FN_IP12_3_2,
+		GP_4_4_FN, FN_IP12_1_0,
+		GP_4_3_FN, FN_IP11_31_30,
+		GP_4_2_FN, FN_IP11_29_27,
+		GP_4_1_FN, FN_IP11_26_24,
+		GP_4_0_FN, FN_IP11_23_22 }
+	},
+	{ PINMUX_CFG_REG("GPSR5", 0xE6060018, 32, 1) {
+		GP_5_31_FN, FN_IP7_24_22,
+		GP_5_30_FN, FN_IP7_21_19,
+		GP_5_29_FN, FN_IP7_18_16,
+		GP_5_28_FN, FN_DU_DOTCLKIN2,
+		GP_5_27_FN, FN_IP7_26_25,
+		GP_5_26_FN, FN_DU_DOTCLKIN0,
+		GP_5_25_FN, FN_AVS2,
+		GP_5_24_FN, FN_AVS1,
+		GP_5_23_FN, FN_USB2_OVC,
+		GP_5_22_FN, FN_USB2_PWEN,
+		GP_5_21_FN, FN_IP16_7,
+		GP_5_20_FN, FN_IP16_6,
+		GP_5_19_FN, FN_USB0_OVC_VBUS,
+		GP_5_18_FN, FN_USB0_PWEN,
+		GP_5_17_FN, FN_IP16_5_3,
+		GP_5_16_FN, FN_IP16_2_0,
+		GP_5_15_FN, FN_IP15_29_28,
+		GP_5_14_FN, FN_IP15_27_26,
+		GP_5_13_FN, FN_IP15_25_23,
+		GP_5_12_FN, FN_IP15_22_20,
+		GP_5_11_FN, FN_IP15_19_18,
+		GP_5_10_FN, FN_IP15_17_16,
+		GP_5_9_FN, FN_IP15_15_14,
+		GP_5_8_FN, FN_IP15_13_12,
+		GP_5_7_FN, FN_IP15_11_9,
+		GP_5_6_FN, FN_IP15_8_6,
+		GP_5_5_FN, FN_IP15_5_3,
+		GP_5_4_FN, FN_IP15_2_0,
+		GP_5_3_FN, FN_IP14_30_28,
+		GP_5_2_FN, FN_IP14_27_25,
+		GP_5_1_FN, FN_IP14_24_22,
+		GP_5_0_FN, FN_IP14_21_19 }
+	},
+
+	/*IPSR0 - IPSR5*/
+	{ PINMUX_CFG_REG_VAR("IPSR6", 0xE6060038, 32,
+			     3, 3, 3, 3, 3, 3, 3, 2, 3, 3, 3) {
+		/* IP6_31_29 [3] */
+		FN_ETH_REF_CLK, FN_RMII_REF_CLK, FN_HCTS0_N_E,
+		FN_STP_IVCXO27_1_B, FN_HRX0_F, 0, 0, 0,
+		/* IP6_28_26 [3] */
+		FN_ETH_LINK, FN_RMII_LINK, FN_HTX0_E,
+		FN_STP_IVCXO27_0_B, FN_SCIFB1_TXD_G, FN_TX1_E, 0, 0,
+		/* IP6_25_23 [3] */
+		FN_ETH_RXD1, FN_RMII_RXD1, FN_HRX0_E, FN_STP_ISSYNC_0_B,
+		FN_TS_SCK0_D, FN_GLO_I1_C, FN_SCIFB1_RXD_G, FN_RX1_E,
+		/* IP6_22_20 [3] */
+		FN_ETH_RXD0, FN_RMII_RXD0, FN_STP_ISEN_0_B, FN_TS_SDAT0_D,
+		FN_GLO_I0_C, FN_SCIFB1_SCK_G, FN_SCK1_E, 0,
+		/* IP6_19_17 [3] */
+		FN_ETH_RX_ER, FN_RMII_RX_ER, FN_STP_ISD_0_B,
+		FN_TS_SPSYNC0_D, FN_GLO_Q1_C, FN_SDA2_E, FN_SDA2_CIS_E, 0,
+		/* IP6_16_14 [3] */
+		FN_ETH_CRS_DV, FN_RMII_CRS_DV, FN_STP_ISCLK_0_B,
+		FN_TS_SDEN0_D, FN_GLO_Q0_C, FN_SCL2_E,
+		FN_SCL2_CIS_E, 0,
+		/* IP6_13_11 [3] */
+		FN_DACK2, FN_IRQ2, FN_INTC_IRQ2_N,
+		FN_SSI_SDATA6_B, FN_HRTS0_N_B, FN_MSIOF0_RXD_B, 0, 0,
+		/* IP6_10_9 [2] */
+		FN_DREQ2_N, FN_HSCK1_B, FN_HCTS0_N_B, FN_MSIOF0_TXD_B,
+		/* IP6_8_6 [3] */
+		FN_DACK1, FN_IRQ1, FN_INTC_IRQ1_N, FN_SSI_WS6_B,
+		FN_SSI_SDATA8_C, 0, 0, 0,
+		/* IP6_5_3 [3] */
+		FN_DREQ1_N, FN_VI1_CLKENB, FN_VI1_CLKENB_B,
+		FN_SSI_SDATA7_C, FN_SSI_SCK78_B, 0, 0, 0,
+		/* IP6_2_0 [3] */
+		FN_DACK0, FN_IRQ0, FN_INTC_IRQ0_N, FN_SSI_SCK6_B,
+		FN_VI1_VSYNC_N, FN_VI1_VSYNC_N_B, FN_SSI_WS78_C, 0, }
+	},
+	{ PINMUX_CFG_REG_VAR("IPSR7", 0xE606003C, 32,
+			     1, 2, 2, 2, 3, 3, 3, 3, 3, 2, 2, 3, 3) {
+		/* IP7_31 [1] */
+		0, 0,
+		/* IP7_30_29 [2] */
+		FN_VI0_DATA0_VI0_B0, FN_ATACS10_N, FN_AVB_RXD2,
+		FN_MII_RXD2,
+		/* IP7_28_27 [2] */
+		FN_VI0_CLK, FN_ATACS00_N, FN_AVB_RXD1, FN_MII_RXD1,
+		/* IP7_26_25 [2] */
+		FN_DU1_DOTCLKIN, FN_AUDIO_CLKC, FN_AUDIO_CLKOUT_C, 0,
+		/* IP7_24_22 [3] */
+		FN_PWM2, FN_PWMFSW0, FN_SCIFA2_RXD_C, FN_PCMWE_N, FN_IECLK_C,
+		0, 0, 0,
+		/* IP7_21_19 [3] */
+		FN_PWM1, FN_SCIFA2_TXD_C, FN_STP_ISSYNC_1_B, FN_TS_SCK1_C,
+		FN_GLO_RFON_C, FN_PCMOE_N, 0, 0,
+		/* IP7_18_16 [3] */
+		FN_PWM0, FN_SCIFA2_SCK_C, FN_STP_ISEN_1_B, FN_TS_SDAT1_C,
+		FN_GLO_SS_C, 0, 0, 0,
+		/* IP7_15_13 [3] */
+		FN_ETH_MDC, FN_RMII_MDC, FN_STP_ISD_1_B,
+		FN_TS_SPSYNC1_C, FN_GLO_SDATA_C, 0, 0, 0,
+		/* IP7_12_10 [3] */
+		FN_ETH_TXD0, FN_RMII_TXD0, FN_STP_ISCLK_1_B, FN_TS_SDEN1_C,
+		FN_GLO_SCLK_C, 0, 0, 0,
+		/* IP7_9_8 [2] */
+		FN_ETH_MAGIC, FN_RMII_MAGIC, FN_SIM0_RST_C, 0,
+		/* IP7_7_6 [2] */
+		FN_ETH_TX_EN, FN_RMII_TX_EN, FN_SIM0_CLK_C, FN_HRTS0_N_F,
+		/* IP7_5_3 [3] */
+		FN_ETH_TXD1, FN_RMII_TXD1, FN_HTX0_F, FN_BPFCLK_G, FN_RDS_CLK_F,
+		0, 0, 0,
+		/* IP7_2_0 [3] */
+		FN_ETH_MDIO, FN_RMII_MDIO, FN_HRTS0_N_E,
+		FN_SIM0_D_C, FN_HCTS0_N_F, 0, 0, 0, }
+	},
+	/*IPSR8 - IPSR16*/
+	{ PINMUX_CFG_REG("INOUTSEL0", 0xE6050004, 32, 1) { GP_INOUTSEL(0) } },
+	{ PINMUX_CFG_REG("INOUTSEL1", 0xE6051004, 32, 1) {
+		0, 0,
+		0, 0,
+		GP_1_29_IN, GP_1_29_OUT,
+		GP_1_28_IN, GP_1_28_OUT,
+		GP_1_27_IN, GP_1_27_OUT,
+		GP_1_26_IN, GP_1_26_OUT,
+		GP_1_25_IN, GP_1_25_OUT,
+		GP_1_24_IN, GP_1_24_OUT,
+		GP_1_23_IN, GP_1_23_OUT,
+		GP_1_22_IN, GP_1_22_OUT,
+		GP_1_21_IN, GP_1_21_OUT,
+		GP_1_20_IN, GP_1_20_OUT,
+		GP_1_19_IN, GP_1_19_OUT,
+		GP_1_18_IN, GP_1_18_OUT,
+		GP_1_17_IN, GP_1_17_OUT,
+		GP_1_16_IN, GP_1_16_OUT,
+		GP_1_15_IN, GP_1_15_OUT,
+		GP_1_14_IN, GP_1_14_OUT,
+		GP_1_13_IN, GP_1_13_OUT,
+		GP_1_12_IN, GP_1_12_OUT,
+		GP_1_11_IN, GP_1_11_OUT,
+		GP_1_10_IN, GP_1_10_OUT,
+		GP_1_9_IN, GP_1_9_OUT,
+		GP_1_8_IN, GP_1_8_OUT,
+		GP_1_7_IN, GP_1_7_OUT,
+		GP_1_6_IN, GP_1_6_OUT,
+		GP_1_5_IN, GP_1_5_OUT,
+		GP_1_4_IN, GP_1_4_OUT,
+		GP_1_3_IN, GP_1_3_OUT,
+		GP_1_2_IN, GP_1_2_OUT,
+		GP_1_1_IN, GP_1_1_OUT,
+		GP_1_0_IN, GP_1_0_OUT, }
+	},
+	{ PINMUX_CFG_REG("INOUTSEL2", 0xE6052004, 32, 1) {
+		0, 0,
+		0, 0,
+		GP_2_29_IN, GP_2_29_OUT,
+		GP_2_28_IN, GP_2_28_OUT,
+		GP_2_27_IN, GP_2_27_OUT,
+		GP_2_26_IN, GP_2_26_OUT,
+		GP_2_25_IN, GP_2_25_OUT,
+		GP_2_24_IN, GP_2_24_OUT,
+		GP_2_23_IN, GP_2_23_OUT,
+		GP_2_22_IN, GP_2_22_OUT,
+		GP_2_21_IN, GP_2_21_OUT,
+		GP_2_20_IN, GP_2_20_OUT,
+		GP_2_19_IN, GP_2_19_OUT,
+		GP_2_18_IN, GP_2_18_OUT,
+		GP_2_17_IN, GP_2_17_OUT,
+		GP_2_16_IN, GP_2_16_OUT,
+		GP_2_15_IN, GP_2_15_OUT,
+		GP_2_14_IN, GP_2_14_OUT,
+		GP_2_13_IN, GP_2_13_OUT,
+		GP_2_12_IN, GP_2_12_OUT,
+		GP_2_11_IN, GP_2_11_OUT,
+		GP_2_10_IN, GP_2_10_OUT,
+		GP_2_9_IN, GP_2_9_OUT,
+		GP_2_8_IN, GP_2_8_OUT,
+		GP_2_7_IN, GP_2_7_OUT,
+		GP_2_6_IN, GP_2_6_OUT,
+		GP_2_5_IN, GP_2_5_OUT,
+		GP_2_4_IN, GP_2_4_OUT,
+		GP_2_3_IN, GP_2_3_OUT,
+		GP_2_2_IN, GP_2_2_OUT,
+		GP_2_1_IN, GP_2_1_OUT,
+		GP_2_0_IN, GP_2_0_OUT, }
+	},
+	{ PINMUX_CFG_REG("INOUTSEL3", 0xE6053004, 32, 1) { GP_INOUTSEL(3) } },
+	{ PINMUX_CFG_REG("INOUTSEL4", 0xE6054004, 32, 1) { GP_INOUTSEL(4) } },
+	{ PINMUX_CFG_REG("INOUTSEL5", 0xE6055004, 32, 1) { GP_INOUTSEL(5) } },
+	{ },
+};
+
+static struct pinmux_data_reg pinmux_data_regs[] = {
+	{ PINMUX_DATA_REG("INDT0", 0xE6050008, 32) { GP_INDT(0) } },
+	{ PINMUX_DATA_REG("INDT1", 0xE6051008, 32) {
+		0, 0, GP_1_29_DATA, GP_1_28_DATA,
+		GP_1_27_DATA, GP_1_26_DATA, GP_1_25_DATA, GP_1_24_DATA,
+		GP_1_23_DATA, GP_1_22_DATA, GP_1_21_DATA, GP_1_20_DATA,
+		GP_1_19_DATA, GP_1_18_DATA, GP_1_17_DATA, GP_1_16_DATA,
+		GP_1_15_DATA, GP_1_14_DATA, GP_1_13_DATA, GP_1_12_DATA,
+		GP_1_11_DATA, GP_1_10_DATA, GP_1_9_DATA, GP_1_8_DATA,
+		GP_1_7_DATA, GP_1_6_DATA, GP_1_5_DATA, GP_1_4_DATA,
+		GP_1_3_DATA, GP_1_2_DATA, GP_1_1_DATA, GP_1_0_DATA }
+	},
+	{ PINMUX_DATA_REG("INDT2", 0xE6052008, 32) {
+		0, 0, GP_2_29_DATA, GP_2_28_DATA,
+		GP_2_27_DATA, GP_2_26_DATA, GP_2_25_DATA, GP_2_24_DATA,
+		GP_2_23_DATA, GP_2_22_DATA, GP_2_21_DATA, GP_2_20_DATA,
+		GP_2_19_DATA, GP_2_18_DATA, GP_2_17_DATA, GP_2_16_DATA,
+		GP_2_15_DATA, GP_2_14_DATA, GP_2_13_DATA, GP_2_12_DATA,
+		GP_2_11_DATA, GP_2_10_DATA, GP_2_9_DATA, GP_2_8_DATA,
+		GP_2_7_DATA, GP_2_6_DATA, GP_2_5_DATA, GP_2_4_DATA,
+		GP_2_3_DATA, GP_2_2_DATA, GP_2_1_DATA, GP_2_0_DATA }
+	},
+	{ PINMUX_DATA_REG("INDT3", 0xE6053008, 32) { GP_INDT(3) } },
+	{ PINMUX_DATA_REG("INDT4", 0xE6054008, 32) { GP_INDT(4) } },
+	{ PINMUX_DATA_REG("INDT5", 0xE6055008, 32) { GP_INDT(5) } },
+	{ },
+};
+
+static struct pinmux_info r8a7790_pinmux_info = {
+	.name = "r8a7790_pfc",
+
+	.unlock_reg = 0xe6060000, /* PMMR */
+
+	.reserved_id = PINMUX_RESERVED,
+	.data = { PINMUX_DATA_BEGIN, PINMUX_DATA_END },
+	.input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END },
+	.output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END },
+	.mark = { PINMUX_MARK_BEGIN, PINMUX_MARK_END },
+	.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
+
+	.first_gpio = GPIO_GP_0_0,
+	.last_gpio = GPIO_FN_MII_RXD2 /* GPIO_FN_TCLK1_B */,
+
+	.gpios = pinmux_gpios,
+	.cfg_regs = pinmux_config_regs,
+	.data_regs = pinmux_data_regs,
+
+	.gpio_data = pinmux_data,
+	.gpio_data_size = ARRAY_SIZE(pinmux_data),
+};
+
+void r8a7790_pinmux_init(void)
+{
+	register_pinmux(&r8a7790_pinmux_info);
+}
diff --git a/arch/arm/cpu/armv7/rmobile/pfc-r8a7790.h b/arch/arm/cpu/armv7/rmobile/pfc-r8a7790.h
new file mode 100644
index 0000000000..a13317be0b
--- /dev/null
+++ b/arch/arm/cpu/armv7/rmobile/pfc-r8a7790.h
@@ -0,0 +1,92 @@
+/*
+ * arch/arm/cpu/armv7/rmobile/pfc-r8a7790.h
+ *
+ * Copyright (C) 2013 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#ifndef __PFC_R8A7790_H__
+#define __PFC_R8A7790_H__
+
+#include <sh_pfc.h>
+#include <asm/gpio.h>
+
+#define CPU_32_PORT(fn, pfx, sfx)				\
+	PORT_10(fn, pfx, sfx), PORT_10(fn, pfx##1, sfx),	\
+	PORT_10(fn, pfx##2, sfx), PORT_1(fn, pfx##30, sfx),	\
+	PORT_1(fn, pfx##31, sfx)
+
+#define CPU_32_PORT2(fn, pfx, sfx)				\
+	PORT_10(fn, pfx, sfx), PORT_10(fn, pfx##1, sfx),	\
+	PORT_10(fn, pfx##2, sfx)
+
+#if defined(CONFIG_R8A7790)
+#define CPU_32_PORT1(fn, pfx, sfx)				\
+	PORT_10(fn, pfx, sfx), PORT_10(fn, pfx##1, sfx),	\
+	PORT_10(fn, pfx##2, sfx)				\
+/* GP_0_0_DATA -> GP_5_31_DATA (except for GP1[30],GP1[31],GP2[30],GP2[31]) */
+#define CPU_ALL_PORT(fn, pfx, sfx)				\
+	CPU_32_PORT(fn, pfx##_0_, sfx),				\
+	CPU_32_PORT1(fn, pfx##_1_, sfx),			\
+	CPU_32_PORT2(fn, pfx##_2_, sfx),			\
+	CPU_32_PORT(fn, pfx##_3_, sfx),				\
+	CPU_32_PORT(fn, pfx##_4_, sfx),				\
+	CPU_32_PORT(fn, pfx##_5_, sfx)
+
+#elif defined(CONFIG_R8A7791)
+#define CPU_32_PORT1(fn, pfx, sfx)				\
+	PORT_10(fn, pfx, sfx), PORT_10(fn, pfx##1, sfx),	\
+	PORT_1(fn, pfx##20, sfx), PORT_1(fn, pfx##21, sfx),	\
+	PORT_1(fn, pfx##22, sfx), PORT_1(fn, pfx##23, sfx),	\
+	PORT_1(fn, pfx##24, sfx), PORT_1(fn, pfx##25, sfx)
+
+/*
+ * GP_0_0_DATA -> GP_7_25_DATA
+ * (except for GP1[26],GP1[27],GP1[28],GP1[29]),GP1[30]),GP1[31]
+ *  GP7[26],GP7[27],GP7[28],GP7[29]),GP7[30]),GP7[31])
+ */
+#define CPU_ALL_PORT(fn, pfx, sfx)				\
+	CPU_32_PORT(fn, pfx##_0_, sfx),				\
+	CPU_32_PORT1(fn, pfx##_1_, sfx),			\
+	CPU_32_PORT(fn, pfx##_2_, sfx),				\
+	CPU_32_PORT(fn, pfx##_3_, sfx),				\
+	CPU_32_PORT(fn, pfx##_4_, sfx),				\
+	CPU_32_PORT(fn, pfx##_5_, sfx),				\
+	CPU_32_PORT(fn, pfx##_6_, sfx),				\
+	CPU_32_PORT1(fn, pfx##_7_, sfx)
+#else
+#error "NO support"
+#endif
+
+#define _GP_GPIO(pfx, sfx) PINMUX_GPIO(GPIO_GP##pfx, GP##pfx##_DATA)
+#define _GP_DATA(pfx, sfx) PINMUX_DATA(GP##pfx##_DATA, GP##pfx##_FN,	\
+				       GP##pfx##_IN, GP##pfx##_OUT)
+
+#define _GP_INOUTSEL(pfx, sfx) GP##pfx##_IN, GP##pfx##_OUT
+#define _GP_INDT(pfx, sfx) GP##pfx##_DATA
+
+#define GP_ALL(str)	CPU_ALL_PORT(_PORT_ALL, GP, str)
+#define PINMUX_GPIO_GP_ALL()	CPU_ALL_PORT(_GP_GPIO, , unused)
+#define PINMUX_DATA_GP_ALL()	CPU_ALL_PORT(_GP_DATA, , unused)
+
+#define PORT_10_REV(fn, pfx, sfx)				\
+	PORT_1(fn, pfx##9, sfx), PORT_1(fn, pfx##8, sfx),	\
+	PORT_1(fn, pfx##7, sfx), PORT_1(fn, pfx##6, sfx),	\
+	PORT_1(fn, pfx##5, sfx), PORT_1(fn, pfx##4, sfx),	\
+	PORT_1(fn, pfx##3, sfx), PORT_1(fn, pfx##2, sfx),	\
+	PORT_1(fn, pfx##1, sfx), PORT_1(fn, pfx##0, sfx)
+
+#define CPU_32_PORT_REV(fn, pfx, sfx)					\
+	PORT_1(fn, pfx##31, sfx), PORT_1(fn, pfx##30, sfx),		\
+	PORT_10_REV(fn, pfx##2, sfx), PORT_10_REV(fn, pfx##1, sfx),	\
+	PORT_10_REV(fn, pfx, sfx)
+
+#define GP_INOUTSEL(bank) CPU_32_PORT_REV(_GP_INOUTSEL, _##bank##_, unused)
+#define GP_INDT(bank) CPU_32_PORT_REV(_GP_INDT, _##bank##_, unused)
+
+#define PINMUX_IPSR_DATA(ipsr, fn) PINMUX_DATA(fn##_MARK, FN_##ipsr, FN_##fn)
+#define PINMUX_IPSR_MODSEL_DATA(ipsr, fn, ms) PINMUX_DATA(fn##_MARK, FN_##ms, \
+							  FN_##ipsr, FN_##fn)
+
+#endif /* __PFC_R8A7790_H__ */
diff --git a/arch/arm/cpu/armv7/rmobile/pfc-r8a7791.c b/arch/arm/cpu/armv7/rmobile/pfc-r8a7791.c
new file mode 100644
index 0000000000..f49f990a02
--- /dev/null
+++ b/arch/arm/cpu/armv7/rmobile/pfc-r8a7791.c
@@ -0,0 +1,1117 @@
+/*
+ * arch/arm/cpu/armv7/rmobile/pfc-r8a7791.c
+ *
+ * Copyright (C) 2013 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <common.h>
+#include <sh_pfc.h>
+#include <asm/gpio.h>
+#include "pfc-r8a7790.h"
+
+enum {
+	PINMUX_RESERVED = 0,
+
+	PINMUX_DATA_BEGIN,
+	GP_ALL(DATA),
+	PINMUX_DATA_END,
+
+	PINMUX_INPUT_BEGIN,
+	GP_ALL(IN),
+	PINMUX_INPUT_END,
+
+	PINMUX_OUTPUT_BEGIN,
+	GP_ALL(OUT),
+	PINMUX_OUTPUT_END,
+
+	PINMUX_FUNCTION_BEGIN,
+	GP_ALL(FN),
+
+	/* GPSR0 */
+	FN_IP0_0, FN_IP0_1, FN_IP0_2, FN_IP0_3, FN_IP0_4, FN_IP0_5,
+	FN_IP0_6, FN_IP0_7, FN_IP0_8, FN_IP0_9, FN_IP0_10, FN_IP0_11,
+	FN_IP0_12, FN_IP0_13, FN_IP0_14, FN_IP0_15, FN_IP0_18_16, FN_IP0_20_19,
+	FN_IP0_22_21, FN_IP0_24_23, FN_IP0_26_25, FN_IP0_28_27, FN_IP0_30_29,
+	FN_IP1_1_0, FN_IP1_3_2, FN_IP1_5_4, FN_IP1_7_6, FN_IP1_10_8,
+	FN_IP1_13_11, FN_IP1_16_14, FN_IP1_19_17, FN_IP1_22_20,
+
+	/* GPSR1 */
+	FN_IP1_25_23, FN_IP1_28_26, FN_IP1_31_29, FN_IP2_2_0, FN_IP2_4_3,
+	FN_IP2_6_5, FN_IP2_9_7, FN_IP2_12_10, FN_IP2_15_13, FN_IP2_18_16,
+	FN_IP2_20_19, FN_IP2_22_21, FN_EX_CS0_N, FN_IP2_24_23, FN_IP2_26_25,
+	FN_IP2_29_27, FN_IP3_2_0, FN_IP3_5_3, FN_IP3_8_6, FN_RD_N,
+	FN_IP3_11_9, FN_IP3_13_12, FN_IP3_15_14 , FN_IP3_17_16 , FN_IP3_19_18,
+	FN_IP3_21_20,
+
+	/* GPSR2 */
+	FN_IP3_27_25, FN_IP3_30_28, FN_IP4_1_0, FN_IP4_4_2, FN_IP4_7_5,
+	FN_IP4_9_8, FN_IP4_12_10, FN_IP4_15_13, FN_IP4_18_16, FN_IP4_19,
+	FN_IP4_20, FN_IP4_21, FN_IP4_23_22, FN_IP4_25_24, FN_IP4_27_26,
+	FN_IP4_30_28, FN_IP5_2_0, FN_IP5_5_3, FN_IP5_8_6, FN_IP5_11_9,
+	FN_IP5_14_12, FN_IP5_16_15, FN_IP5_19_17, FN_IP5_21_20, FN_IP5_23_22,
+	FN_IP5_25_24, FN_IP5_28_26, FN_IP5_31_29, FN_AUDIO_CLKA, FN_IP6_2_0,
+	FN_IP6_5_3, FN_IP6_7_6,
+
+	/* GPSR3 */
+	FN_IP7_5_3, FN_IP7_8_6, FN_IP7_10_9, FN_IP7_12_11, FN_IP7_14_13,
+	FN_IP7_16_15, FN_IP7_18_17, FN_IP7_20_19, FN_IP7_23_21, FN_IP7_26_24,
+	FN_IP7_29_27, FN_IP8_2_0, FN_IP8_5_3, FN_IP8_8_6, FN_IP8_11_9,
+	FN_IP8_14_12, FN_IP8_17_15, FN_IP8_20_18, FN_IP8_23_21, FN_IP8_25_24,
+	FN_IP8_27_26, FN_IP8_30_28, FN_IP9_2_0, FN_IP9_5_3, FN_IP9_6, FN_IP9_7,
+	FN_IP9_10_8, FN_IP9_11, FN_IP9_12, FN_IP9_15_13, FN_IP9_16,
+	FN_IP9_18_17,
+
+	/* GPSR4 */
+	FN_VI0_CLK, FN_IP9_20_19, FN_IP9_22_21, FN_IP9_24_23, FN_IP9_26_25,
+	FN_VI0_DATA0_VI0_B0, FN_VI0_DATA0_VI0_B1, FN_VI0_DATA0_VI0_B2,
+	FN_IP9_28_27, FN_VI0_DATA0_VI0_B4, FN_VI0_DATA0_VI0_B5,
+	FN_VI0_DATA0_VI0_B6, FN_VI0_DATA0_VI0_B7, FN_IP9_31_29, FN_IP10_2_0,
+	FN_IP10_5_3, FN_IP10_8_6, FN_IP10_11_9, FN_IP10_14_12, FN_IP10_16_15,
+	FN_IP10_18_17, FN_IP10_21_19, FN_IP10_24_22, FN_IP10_26_25,
+	FN_IP10_28_27, FN_IP10_31_29, FN_IP11_2_0, FN_IP11_5_3, FN_IP11_8_6,
+	FN_IP15_1_0, FN_IP15_3_2, FN_IP15_5_4,
+
+	/* GPSR5 */
+	FN_IP11_11_9, FN_IP11_14_12, FN_IP11_16_15, FN_IP11_18_17, FN_IP11_19,
+	FN_IP11_20, FN_IP11_21, FN_IP11_22, FN_IP11_23, FN_IP11_24,
+	FN_IP11_25, FN_IP11_26, FN_IP11_27, FN_IP11_29_28, FN_IP11_31_30,
+	FN_IP12_1_0, FN_IP12_3_2, FN_IP12_6_4, FN_IP12_9_7, FN_IP12_12_10,
+	FN_IP12_15_13, FN_IP12_17_16, FN_IP12_19_18, FN_IP12_21_20,
+	FN_IP12_23_22, FN_IP12_26_24, FN_IP12_29_27, FN_IP13_2_0, FN_IP13_4_3,
+	FN_IP13_6_5, FN_IP13_9_7, FN_IP3_24_22,
+
+	/* GPSR6 */
+	FN_IP13_10, FN_IP13_11, FN_IP13_12, FN_IP13_13, FN_IP13_14,
+	FN_IP13_15, FN_IP13_18_16, FN_IP13_21_19, FN_IP13_22, FN_IP13_24_23,
+	FN_IP13_25, FN_IP13_26, FN_IP13_27, FN_IP13_30_28, FN_IP14_1_0,
+	FN_IP14_2, FN_IP14_3, FN_IP14_4, FN_IP14_5, FN_IP14_6, FN_IP14_7,
+	FN_IP14_10_8, FN_IP14_13_11, FN_IP14_16_14, FN_IP14_19_17,
+	FN_IP14_22_20, FN_IP14_25_23, FN_IP14_28_26, FN_IP14_31_29,
+
+	/* GPSR7 */
+	FN_IP15_17_15, FN_IP15_20_18, FN_IP15_23_21, FN_IP15_26_24,
+	FN_IP15_29_27, FN_IP16_2_0, FN_IP16_5_3, FN_IP16_7_6, FN_IP16_9_8,
+	FN_IP16_11_10, FN_IP6_9_8, FN_IP6_11_10, FN_IP6_13_12, FN_IP6_15_14,
+	FN_IP6_18_16, FN_IP6_20_19, FN_IP6_23_21, FN_IP6_26_24, FN_IP6_29_27,
+	FN_IP7_2_0, FN_IP15_8_6, FN_IP15_11_9, FN_IP15_14_12,
+	FN_USB0_PWEN, FN_USB0_OVC, FN_USB1_PWEN,
+
+	/* IPSR0 -  IPSR10 */
+
+	/* IPSR11 */
+	FN_VI0_R5, FN_VI2_DATA6, FN_GLO_SDATA_B, FN_RX0_C, FN_SDA1_D,
+	FN_VI0_R6, FN_VI2_DATA7, FN_GLO_SS_B, FN_TX1_C, FN_SCL4_B,
+	FN_VI0_R7, FN_GLO_RFON_B, FN_RX1_C, FN_CAN0_RX_E,
+	FN_SDA4_B, FN_HRX1_D, FN_SCIFB0_RXD_D,
+	FN_VI1_HSYNC_N, FN_AVB_RXD0, FN_TS_SDATA0_B, FN_TX4_B, FN_SCIFA4_TXD_B,
+	FN_VI1_VSYNC_N, FN_AVB_RXD1, FN_TS_SCK0_B, FN_RX4_B, FN_SCIFA4_RXD_B,
+	FN_VI1_CLKENB, FN_AVB_RXD2, FN_TS_SDEN0_B,
+	FN_VI1_FIELD, FN_AVB_RXD3, FN_TS_SPSYNC0_B,
+	FN_VI1_CLK, FN_AVB_RXD4, FN_VI1_DATA0, FN_AVB_RXD5,
+	FN_VI1_DATA1, FN_AVB_RXD6, FN_VI1_DATA2, FN_AVB_RXD7,
+	FN_VI1_DATA3, FN_AVB_RX_ER, FN_VI1_DATA4, FN_AVB_MDIO,
+	FN_VI1_DATA5, FN_AVB_RX_DV, FN_VI1_DATA6, FN_AVB_MAGIC,
+	FN_VI1_DATA7, FN_AVB_MDC,
+	FN_ETH_MDIO, FN_AVB_RX_CLK, FN_SCL2_C,
+	FN_ETH_CRS_DV, FN_AVB_LINK, FN_SDA2_C,
+
+	/* IPSR12 */
+	FN_ETH_RX_ER, FN_AVB_CRS, FN_SCL3, FN_SCL7,
+	FN_ETH_RXD0, FN_AVB_PHY_INT, FN_SDA3, FN_SDA7,
+	FN_ETH_RXD1, FN_AVB_GTXREFCLK, FN_CAN0_TX_C,
+	FN_SCL2_D, FN_MSIOF1_RXD_E,
+	FN_ETH_LINK, FN_AVB_TXD0, FN_CAN0_RX_C, FN_SDA2_D, FN_MSIOF1_SCK_E,
+	FN_ETH_REFCLK, FN_AVB_TXD1, FN_SCIFA3_RXD_B,
+	FN_CAN1_RX_C, FN_MSIOF1_SYNC_E,
+	FN_ETH_TXD1, FN_AVB_TXD2, FN_SCIFA3_TXD_B,
+	FN_CAN1_TX_C, FN_MSIOF1_TXD_E,
+	FN_ETH_TX_EN, FN_AVB_TXD3, FN_TCLK1_B, FN_CAN_CLK_B,
+	FN_ETH_MAGIC, FN_AVB_TXD4, FN_IETX_C,
+	FN_ETH_TXD0, FN_AVB_TXD5, FN_IECLK_C,
+	FN_ETH_MDC, FN_AVB_TXD6, FN_IERX_C,
+	FN_STP_IVCXO27_0, FN_AVB_TXD7, FN_SCIFB2_TXD_D,
+	FN_ADIDATA_B, FN_MSIOF0_SYNC_C,
+	FN_STP_ISCLK_0, FN_AVB_TX_EN, FN_SCIFB2_RXD_D,
+	FN_ADICS_SAMP_B, FN_MSIOF0_SCK_C,
+
+	/* IPSR13 */
+	/* MOD_SEL */
+	FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2, FN_SEL_SCIF1_3,
+	FN_SEL_SCIFB_0, FN_SEL_SCIFB_1, FN_SEL_SCIFB_2, FN_SEL_SCIFB_3,
+	FN_SEL_SCIFB2_0, FN_SEL_SCIFB2_1, FN_SEL_SCIFB2_2, FN_SEL_SCIFB2_3,
+	FN_SEL_SCIFB1_0, FN_SEL_SCIFB1_1, FN_SEL_SCIFB1_2, FN_SEL_SCIFB1_3,
+	FN_SEL_SCIFA1_0, FN_SEL_SCIFA1_1, FN_SEL_SCIFA1_2,
+	FN_SEL_SSI9_0, FN_SEL_SSI9_1,
+	FN_SEL_SCFA_0, FN_SEL_SCFA_1,
+	FN_SEL_QSP_0, FN_SEL_QSP_1,
+	FN_SEL_SSI7_0, FN_SEL_SSI7_1,
+	FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1, FN_SEL_HSCIF1_2, FN_SEL_HSCIF1_3,
+	FN_SEL_HSCIF1_4,
+	FN_SEL_VI1_0, FN_SEL_VI1_1, FN_SEL_VI1_2,
+	FN_SEL_TMU1_0, FN_SEL_TMU1_1,
+	FN_SEL_LBS_0, FN_SEL_LBS_1, FN_SEL_LBS_2, FN_SEL_LBS_3,
+	FN_SEL_TSIF0_0, FN_SEL_TSIF0_1, FN_SEL_TSIF0_2, FN_SEL_TSIF0_3,
+	FN_SEL_SOF0_0, FN_SEL_SOF0_1, FN_SEL_SOF0_2,
+
+	/* MOD_SEL2 */
+	FN_SEL_SCIF0_0, FN_SEL_SCIF0_1, FN_SEL_SCIF0_2, FN_SEL_SCIF0_3,
+	FN_SEL_SCIF0_4,
+	FN_SEL_SCIF_0, FN_SEL_SCIF_1,
+	FN_SEL_CAN0_0, FN_SEL_CAN0_1, FN_SEL_CAN0_2, FN_SEL_CAN0_3,
+	FN_SEL_CAN0_4, FN_SEL_CAN0_5,
+	FN_SEL_CAN1_0, FN_SEL_CAN1_1, FN_SEL_CAN1_2, FN_SEL_CAN1_3,
+	FN_SEL_SCIFA2_0, FN_SEL_SCIFA2_1,
+	FN_SEL_SCIF4_0, FN_SEL_SCIF4_1, FN_SEL_SCIF4_2,
+	FN_SEL_ADG_0, FN_SEL_ADG_1,
+	FN_SEL_FM_0, FN_SEL_FM_1, FN_SEL_FM_2, FN_SEL_FM_3, FN_SEL_FM_4,
+	FN_SEL_SCIFA5_0, FN_SEL_SCIFA5_1, FN_SEL_SCIFA5_2,
+	FN_SEL_GPS_0, FN_SEL_GPS_1, FN_SEL_GPS_2, FN_SEL_GPS_3,
+	FN_SEL_SCIFA4_0, FN_SEL_SCIFA4_1, FN_SEL_SCIFA4_2,
+	FN_SEL_SCIFA3_0, FN_SEL_SCIFA3_1, FN_SEL_SCIFA3_2,
+	FN_SEL_SIM_0, FN_SEL_SIM_1,
+	FN_SEL_SSI8_0, FN_SEL_SSI8_1,
+
+	/* MOD_SEL3 */
+	FN_SEL_HSCIF2_0, FN_SEL_HSCIF2_1, FN_SEL_HSCIF2_2, FN_SEL_HSCIF2_3,
+	FN_SEL_CANCLK_0, FN_SEL_CANCLK_1, FN_SEL_CANCLK_2, FN_SEL_CANCLK_3,
+	FN_SEL_IIC8_0, FN_SEL_IIC8_1, FN_SEL_IIC8_2,
+	FN_SEL_IIC7_0, FN_SEL_IIC7_1, FN_SEL_IIC7_2,
+	FN_SEL_IIC4_0, FN_SEL_IIC4_1, FN_SEL_IIC4_2,
+	FN_SEL_IIC3_0, FN_SEL_IIC3_1, FN_SEL_IIC3_2, FN_SEL_IIC3_3,
+	FN_SEL_SCIF3_0, FN_SEL_SCIF3_1, FN_SEL_SCIF3_2, FN_SEL_SCIF3_3,
+	FN_SEL_IEB_0, FN_SEL_IEB_1, FN_SEL_IEB_2,
+	FN_SEL_MMC_0, FN_SEL_MMC_1,
+	FN_SEL_SCIF5_0, FN_SEL_SCIF5_1,
+	FN_SEL_IIC2_0, FN_SEL_IIC2_1, FN_SEL_IIC2_2, FN_SEL_IIC2_3,
+	FN_SEL_IIC1_0, FN_SEL_IIC1_1, FN_SEL_IIC1_2, FN_SEL_IIC1_3,
+	FN_SEL_IIC1_4,
+	FN_SEL_IIC0_0, FN_SEL_IIC0_1, FN_SEL_IIC0_2,
+
+	/* MOD_SEL4 */
+	FN_SEL_SOF1_0, FN_SEL_SOF1_1, FN_SEL_SOF1_2, FN_SEL_SOF1_3,
+	FN_SEL_SOF1_4,
+	FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1, FN_SEL_HSCIF0_2,
+	FN_SEL_DIS_0, FN_SEL_DIS_1, FN_SEL_DIS_2,
+	FN_SEL_RAD_0, FN_SEL_RAD_1,
+	FN_SEL_RCN_0, FN_SEL_RCN_1,
+	FN_SEL_RSP_0, FN_SEL_RSP_1,
+	FN_SEL_SCIF2_0, FN_SEL_SCIF2_1, FN_SEL_SCIF2_2, FN_SEL_SCIF2_3,
+	FN_SEL_SCIF2_4,
+	FN_SEL_SOF2_0, FN_SEL_SOF2_1, FN_SEL_SOF2_2, FN_SEL_SOF2_3,
+	FN_SEL_SOF2_4,
+	FN_SEL_SSI1_0, FN_SEL_SSI1_1,
+	FN_SEL_SSI0_0, FN_SEL_SSI0_1,
+	FN_SEL_SSP_0, FN_SEL_SSP_1, FN_SEL_SSP_2,
+	PINMUX_FUNCTION_END,
+
+	PINMUX_MARK_BEGIN,
+
+	EX_CS0_N_MARK, RD_N_MARK,
+
+	AUDIO_CLKA_MARK,
+
+	VI0_CLK_MARK, VI0_DATA0_VI0_B0_MARK, VI0_DATA0_VI0_B1_MARK,
+	VI0_DATA0_VI0_B2_MARK, VI0_DATA0_VI0_B4_MARK, VI0_DATA0_VI0_B5_MARK,
+	VI0_DATA0_VI0_B6_MARK, VI0_DATA0_VI0_B7_MARK,
+
+	USB0_PWEN_MARK, USB0_OVC_MARK, USB1_PWEN_MARK,
+
+	/* IPSR0  IPSR10 */
+	/* IPSR11 */
+	VI0_R5_MARK, VI2_DATA6_MARK, GLO_SDATA_B_MARK, RX0_C_MARK, SDA1_D_MARK,
+	VI0_R6_MARK, VI2_DATA7_MARK, GLO_SS_B_MARK, TX1_C_MARK, SCL4_B_MARK,
+	VI0_R7_MARK, GLO_RFON_B_MARK, RX1_C_MARK, CAN0_RX_E_MARK,
+	SDA4_B_MARK, _MARK, HRX1_D_MARK, SCIFB0_RXD_D_MARK,
+	VI1_HSYNC_N_MARK, AVB_RXD0_MARK, TS_SDATA0_B_MARK,
+	TX4_B_MARK, SCIFA4_TXD_B_MARK,
+	VI1_VSYNC_N_MARK, AVB_RXD1_MARK, TS_SCK0_B_MARK,
+	RX4_B_MARK, SCIFA4_RXD_B_MARK,
+	VI1_CLKENB_MARK, AVB_RXD2_MARK, TS_SDEN0_B_MARK,
+	VI1_FIELD_MARK, AVB_RXD3_MARK, TS_SPSYNC0_B_MARK,
+	VI1_CLK_MARK, AVB_RXD4_MARK, VI1_DATA0_MARK, AVB_RXD5_MARK,
+	VI1_DATA1_MARK, AVB_RXD6_MARK, VI1_DATA2_MARK, AVB_RXD7_MARK,
+	VI1_DATA3_MARK, AVB_RX_ER_MARK, VI1_DATA4_MARK, AVB_MDIO_MARK,
+	VI1_DATA5_MARK, AVB_RX_DV_MARK, VI1_DATA6_MARK, AVB_MAGIC_MARK,
+	VI1_DATA7_MARK, AVB_MDC_MARK,
+	ETH_MDIO_MARK, AVB_RX_CLK_MARK, SCL2_C_MARK,
+	ETH_CRS_DV_MARK, AVB_LINK_MARK, SDA2_C_MARK,
+
+	/* IPSR12 */
+	ETH_RX_ER_MARK, AVB_CRS_MARK, SCL3_MARK, SCL7_MARK,
+	ETH_RXD0_MARK, AVB_PHY_INT_MARK, SDA3_MARK, SDA7_MARK,
+	ETH_RXD1_MARK, AVB_GTXREFCLK_MARK, CAN0_TX_C_MARK,
+	SCL2_D_MARK, MSIOF1_RXD_E_MARK,
+	ETH_LINK_MARK, AVB_TXD0_MARK, CAN0_RX_C_MARK,
+	SDA2_D_MARK, MSIOF1_SCK_E_MARK,
+	ETH_REFCLK_MARK, AVB_TXD1_MARK, SCIFA3_RXD_B_MARK,
+	CAN1_RX_C_MARK, MSIOF1_SYNC_E_MARK,
+	ETH_TXD1_MARK, AVB_TXD2_MARK, SCIFA3_TXD_B_MARK,
+	CAN1_TX_C_MARK, MSIOF1_TXD_E_MARK,
+	ETH_TX_EN_MARK, AVB_TXD3_MARK, TCLK1_B_MARK, CAN_CLK_B_MARK,
+	ETH_MAGIC_MARK, AVB_TXD4_MARK, IETX_C_MARK,
+	ETH_TXD0_MARK, AVB_TXD5_MARK, IECLK_C_MARK,
+	ETH_MDC_MARK, AVB_TXD6_MARK, IERX_C_MARK,
+	STP_IVCXO27_0_MARK, AVB_TXD7_MARK, SCIFB2_TXD_D_MARK,
+	ADIDATA_B_MARK, MSIOF0_SYNC_C_MARK,
+	STP_ISCLK_0_MARK, AVB_TX_EN_MARK, SCIFB2_RXD_D_MARK,
+	ADICS_SAMP_B_MARK, MSIOF0_SCK_C_MARK,
+
+	/* IPSR13 */
+	PINMUX_MARK_END,
+};
+
+static pinmux_enum_t pinmux_data[] = {
+	PINMUX_DATA_GP_ALL(), /* PINMUX_DATA(GP_M_N_DATA, GP_M_N_FN...), */
+
+	/* OTHER IPSR0  - IPSR10 */
+	/* IPSR11 */
+	PINMUX_IPSR_DATA(IP11_2_0, VI0_R5),
+	PINMUX_IPSR_DATA(IP11_2_0, VI2_DATA6),
+	PINMUX_IPSR_MODSEL_DATA(IP11_2_0, GLO_SDATA_B, SEL_GPS_1),
+	PINMUX_IPSR_MODSEL_DATA(IP11_2_0, RX0_C, SEL_SCIF0_2),
+	PINMUX_IPSR_MODSEL_DATA(IP11_2_0, SDA1_D, SEL_IIC1_3),
+	PINMUX_IPSR_DATA(IP11_5_3, VI0_R6),
+	PINMUX_IPSR_DATA(IP11_5_3, VI2_DATA7),
+	PINMUX_IPSR_MODSEL_DATA(IP11_5_3, GLO_SS_B, SEL_GPS_1),
+	PINMUX_IPSR_MODSEL_DATA(IP11_5_3, TX1_C, SEL_SCIF1_2),
+	PINMUX_IPSR_MODSEL_DATA(IP11_5_3, SCL4_B, SEL_IIC4_1),
+	PINMUX_IPSR_DATA(IP11_8_6, VI0_R7),
+	PINMUX_IPSR_MODSEL_DATA(IP11_8_6, GLO_RFON_B, SEL_GPS_1),
+	PINMUX_IPSR_MODSEL_DATA(IP11_8_6, RX1_C, SEL_SCIF1_2),
+	PINMUX_IPSR_MODSEL_DATA(IP11_8_6, CAN0_RX_E, SEL_CAN0_4),
+	PINMUX_IPSR_MODSEL_DATA(IP11_8_6, SDA4_B, SEL_IIC4_1),
+	PINMUX_IPSR_MODSEL_DATA(IP11_8_6, HRX1_D, SEL_HSCIF1_3),
+	PINMUX_IPSR_MODSEL_DATA(IP11_8_6, SCIFB0_RXD_D, SEL_SCIFB_3),
+	PINMUX_IPSR_MODSEL_DATA(IP11_11_9, VI1_HSYNC_N, SEL_VI1_0),
+	PINMUX_IPSR_DATA(IP11_11_9, AVB_RXD0),
+	PINMUX_IPSR_MODSEL_DATA(IP11_11_9, TS_SDATA0_B, SEL_TSIF0_1),
+	PINMUX_IPSR_MODSEL_DATA(IP11_11_9, TX4_B, SEL_SCIF4_1),
+	PINMUX_IPSR_MODSEL_DATA(IP11_11_9, SCIFA4_TXD_B, SEL_SCIFA4_1),
+	PINMUX_IPSR_MODSEL_DATA(IP11_14_12, VI1_VSYNC_N, SEL_VI1_0),
+	PINMUX_IPSR_DATA(IP11_14_12, AVB_RXD1),
+	PINMUX_IPSR_MODSEL_DATA(IP11_14_12, TS_SCK0_B, SEL_TSIF0_1),
+	PINMUX_IPSR_MODSEL_DATA(IP11_14_12, RX4_B, SEL_SCIF4_1),
+	PINMUX_IPSR_MODSEL_DATA(IP11_14_12, SCIFA4_RXD_B, SEL_SCIFA4_1),
+	PINMUX_IPSR_MODSEL_DATA(IP11_16_15, VI1_CLKENB, SEL_VI1_0),
+	PINMUX_IPSR_DATA(IP11_16_15, AVB_RXD2),
+	PINMUX_IPSR_MODSEL_DATA(IP11_16_15, TS_SDEN0_B, SEL_TSIF0_1),
+	PINMUX_IPSR_MODSEL_DATA(IP11_18_17, VI1_FIELD, SEL_VI1_0),
+	PINMUX_IPSR_DATA(IP11_18_17, AVB_RXD3),
+	PINMUX_IPSR_MODSEL_DATA(IP11_18_17, TS_SPSYNC0_B, SEL_TSIF0_1),
+	PINMUX_IPSR_MODSEL_DATA(IP11_19, VI1_CLK, SEL_VI1_0),
+	PINMUX_IPSR_DATA(IP11_19, AVB_RXD4),
+	PINMUX_IPSR_MODSEL_DATA(IP11_20, VI1_DATA0, SEL_VI1_0),
+	PINMUX_IPSR_DATA(IP11_20, AVB_RXD5),
+	PINMUX_IPSR_MODSEL_DATA(IP11_21, VI1_DATA1, SEL_VI1_0),
+	PINMUX_IPSR_DATA(IP11_21, AVB_RXD6),
+	PINMUX_IPSR_MODSEL_DATA(IP11_22, VI1_DATA2, SEL_VI1_0),
+	PINMUX_IPSR_DATA(IP11_22, AVB_RXD7),
+	PINMUX_IPSR_MODSEL_DATA(IP11_23, VI1_DATA3, SEL_VI1_0),
+	PINMUX_IPSR_DATA(IP11_23, AVB_RX_ER),
+	PINMUX_IPSR_MODSEL_DATA(IP11_24, VI1_DATA4, SEL_VI1_0),
+	PINMUX_IPSR_DATA(IP11_24, AVB_MDIO),
+	PINMUX_IPSR_MODSEL_DATA(IP11_25, VI1_DATA5, SEL_VI1_0),
+	PINMUX_IPSR_DATA(IP11_25, AVB_RX_DV),
+	PINMUX_IPSR_MODSEL_DATA(IP11_26, VI1_DATA6, SEL_VI1_0),
+	PINMUX_IPSR_DATA(IP11_26, AVB_MAGIC),
+	PINMUX_IPSR_MODSEL_DATA(IP11_27, VI1_DATA7, SEL_VI1_0),
+	PINMUX_IPSR_DATA(IP11_27, AVB_MDC),
+	PINMUX_IPSR_DATA(IP11_29_28, ETH_MDIO),
+	PINMUX_IPSR_DATA(IP11_29_28, AVB_RX_CLK),
+	PINMUX_IPSR_MODSEL_DATA(IP11_29_28, SCL2_C, SEL_IIC2_2),
+	PINMUX_IPSR_DATA(IP11_31_30, ETH_CRS_DV),
+	PINMUX_IPSR_DATA(IP11_31_30, AVB_LINK),
+	PINMUX_IPSR_MODSEL_DATA(IP11_31_30, SDA2_C, SEL_IIC2_2),
+
+	/* IPSR12 */
+	PINMUX_IPSR_DATA(IP12_1_0, ETH_RX_ER),
+	PINMUX_IPSR_DATA(IP12_1_0, AVB_CRS),
+	PINMUX_IPSR_MODSEL_DATA(IP12_1_0, SCL3, SEL_IIC3_0),
+	PINMUX_IPSR_MODSEL_DATA(IP12_1_0, SCL7, SEL_IIC7_0),
+	PINMUX_IPSR_DATA(IP12_3_2, ETH_RXD0),
+	PINMUX_IPSR_DATA(IP12_3_2, AVB_PHY_INT),
+	PINMUX_IPSR_MODSEL_DATA(IP12_3_2, SDA3, SEL_IIC3_0),
+	PINMUX_IPSR_MODSEL_DATA(IP12_3_2, SDA7, SEL_IIC7_0),
+	PINMUX_IPSR_DATA(IP12_6_4, ETH_RXD1),
+	PINMUX_IPSR_DATA(IP12_6_4, AVB_GTXREFCLK),
+	PINMUX_IPSR_MODSEL_DATA(IP12_6_4, CAN0_TX_C, SEL_CAN0_2),
+	PINMUX_IPSR_MODSEL_DATA(IP12_6_4, SCL2_D, SEL_IIC2_3),
+	PINMUX_IPSR_MODSEL_DATA(IP12_6_4, MSIOF1_RXD_E, SEL_SOF1_4),
+	PINMUX_IPSR_DATA(IP12_9_7, ETH_LINK),
+	PINMUX_IPSR_DATA(IP12_9_7, AVB_TXD0),
+	PINMUX_IPSR_MODSEL_DATA(IP12_9_7, CAN0_RX_C, SEL_CAN0_2),
+	PINMUX_IPSR_MODSEL_DATA(IP12_9_7, SDA2_D, SEL_IIC2_3),
+	PINMUX_IPSR_MODSEL_DATA(IP12_9_7, MSIOF1_SCK_E, SEL_SOF1_4),
+	PINMUX_IPSR_DATA(IP12_12_10, ETH_REFCLK),
+	PINMUX_IPSR_DATA(IP12_12_10, AVB_TXD1),
+	PINMUX_IPSR_MODSEL_DATA(IP12_12_10, SCIFA3_RXD_B, SEL_SCIFA3_1),
+	PINMUX_IPSR_MODSEL_DATA(IP12_12_10, CAN1_RX_C, SEL_CAN1_2),
+	PINMUX_IPSR_MODSEL_DATA(IP12_12_10, MSIOF1_SYNC_E, SEL_SOF1_4),
+	PINMUX_IPSR_DATA(IP12_15_13, ETH_TXD1),
+	PINMUX_IPSR_DATA(IP12_15_13, AVB_TXD2),
+	PINMUX_IPSR_MODSEL_DATA(IP12_15_13, SCIFA3_TXD_B, SEL_SCIFA3_1),
+	PINMUX_IPSR_MODSEL_DATA(IP12_15_13, CAN1_TX_C, SEL_CAN1_2),
+	PINMUX_IPSR_MODSEL_DATA(IP12_15_13, MSIOF1_TXD_E, SEL_SOF1_4),
+	PINMUX_IPSR_DATA(IP12_17_16, ETH_TX_EN),
+	PINMUX_IPSR_DATA(IP12_17_16, AVB_TXD3),
+	PINMUX_IPSR_MODSEL_DATA(IP12_17_16, TCLK1_B, SEL_TMU1_0),
+	PINMUX_IPSR_MODSEL_DATA(IP12_17_16, CAN_CLK_B, SEL_CANCLK_1),
+	PINMUX_IPSR_DATA(IP12_19_18, ETH_MAGIC),
+	PINMUX_IPSR_DATA(IP12_19_18, AVB_TXD4),
+	PINMUX_IPSR_MODSEL_DATA(IP12_19_18, IETX_C, SEL_IEB_2),
+	PINMUX_IPSR_DATA(IP12_21_20, ETH_TXD0),
+	PINMUX_IPSR_DATA(IP12_21_20, AVB_TXD5),
+	PINMUX_IPSR_MODSEL_DATA(IP12_21_20, IECLK_C, SEL_IEB_2),
+	PINMUX_IPSR_DATA(IP12_23_22, ETH_MDC),
+	PINMUX_IPSR_DATA(IP12_23_22, AVB_TXD6),
+	PINMUX_IPSR_MODSEL_DATA(IP12_23_22, IERX_C, SEL_IEB_2),
+	PINMUX_IPSR_MODSEL_DATA(IP12_26_24, STP_IVCXO27_0, SEL_SSP_0),
+	PINMUX_IPSR_DATA(IP12_26_24, AVB_TXD7),
+	PINMUX_IPSR_MODSEL_DATA(IP12_26_24, SCIFB2_TXD_D, SEL_SCIFB2_3),
+	PINMUX_IPSR_MODSEL_DATA(IP12_26_24, ADIDATA_B, SEL_RAD_1),
+	PINMUX_IPSR_MODSEL_DATA(IP12_26_24, MSIOF0_SYNC_C, SEL_SOF0_2),
+	PINMUX_IPSR_MODSEL_DATA(IP12_29_27, STP_ISCLK_0, SEL_SSP_0),
+	PINMUX_IPSR_DATA(IP12_29_27, AVB_TX_EN),
+	PINMUX_IPSR_MODSEL_DATA(IP12_29_27, SCIFB2_RXD_D, SEL_SCIFB2_3),
+	PINMUX_IPSR_MODSEL_DATA(IP12_29_27, ADICS_SAMP_B, SEL_RAD_1),
+	PINMUX_IPSR_MODSEL_DATA(IP12_29_27, MSIOF0_SCK_C, SEL_SOF0_2),
+
+	/* IPSR13 - IPSR16 */
+};
+
+static struct pinmux_gpio pinmux_gpios[] = {
+	PINMUX_GPIO_GP_ALL(),
+
+	/* OTHER, IPSR0 - IPSR10 */
+	/* IPSR11 */
+	GPIO_FN(VI0_R5), GPIO_FN(VI2_DATA6), GPIO_FN(GLO_SDATA_B),
+	GPIO_FN(RX0_C), GPIO_FN(SDA1_D),
+	GPIO_FN(VI0_R6), GPIO_FN(VI2_DATA7),
+	GPIO_FN(GLO_SS_B), GPIO_FN(TX1_C), GPIO_FN(SCL4_B),
+	GPIO_FN(VI0_R7), GPIO_FN(GLO_RFON_B),
+	GPIO_FN(RX1_C), GPIO_FN(CAN0_RX_E),
+	GPIO_FN(SDA4_B), GPIO_FN(HRX1_D), GPIO_FN(SCIFB0_RXD_D),
+	GPIO_FN(VI1_HSYNC_N), GPIO_FN(AVB_RXD0), GPIO_FN(TS_SDATA0_B),
+	GPIO_FN(TX4_B), GPIO_FN(SCIFA4_TXD_B),
+	GPIO_FN(VI1_VSYNC_N), GPIO_FN(AVB_RXD1), GPIO_FN(TS_SCK0_B),
+	GPIO_FN(RX4_B), GPIO_FN(SCIFA4_RXD_B),
+	GPIO_FN(VI1_CLKENB), GPIO_FN(AVB_RXD2), GPIO_FN(TS_SDEN0_B),
+	GPIO_FN(VI1_FIELD), GPIO_FN(AVB_RXD3), GPIO_FN(TS_SPSYNC0_B),
+	GPIO_FN(VI1_CLK), GPIO_FN(AVB_RXD4),
+	GPIO_FN(VI1_DATA0), GPIO_FN(AVB_RXD5),
+	GPIO_FN(VI1_DATA1), GPIO_FN(AVB_RXD6),
+	GPIO_FN(VI1_DATA2), GPIO_FN(AVB_RXD7),
+	GPIO_FN(VI1_DATA3), GPIO_FN(AVB_RX_ER),
+	GPIO_FN(VI1_DATA4), GPIO_FN(AVB_MDIO),
+	GPIO_FN(VI1_DATA5), GPIO_FN(AVB_RX_DV),
+	GPIO_FN(VI1_DATA6), GPIO_FN(AVB_MAGIC),
+	GPIO_FN(VI1_DATA7), GPIO_FN(AVB_MDC),
+	GPIO_FN(ETH_MDIO), GPIO_FN(AVB_RX_CLK), GPIO_FN(SCL2_C),
+	GPIO_FN(ETH_CRS_DV), GPIO_FN(AVB_LINK), GPIO_FN(SDA2_C),
+
+	/* IPSR12 */
+	GPIO_FN(ETH_RX_ER), GPIO_FN(AVB_CRS), GPIO_FN(SCL3), GPIO_FN(SCL7),
+	GPIO_FN(ETH_RXD0), GPIO_FN(AVB_PHY_INT), GPIO_FN(SDA3), GPIO_FN(SDA7),
+	GPIO_FN(ETH_RXD1), GPIO_FN(AVB_GTXREFCLK), GPIO_FN(CAN0_TX_C),
+	GPIO_FN(SCL2_D), GPIO_FN(MSIOF1_RXD_E),
+	GPIO_FN(ETH_LINK), GPIO_FN(AVB_TXD0), GPIO_FN(CAN0_RX_C),
+	GPIO_FN(SDA2_D), GPIO_FN(MSIOF1_SCK_E),
+	GPIO_FN(ETH_REFCLK), GPIO_FN(AVB_TXD1), GPIO_FN(SCIFA3_RXD_B),
+	GPIO_FN(CAN1_RX_C), GPIO_FN(MSIOF1_SYNC_E),
+	GPIO_FN(ETH_TXD1), GPIO_FN(AVB_TXD2), GPIO_FN(SCIFA3_TXD_B),
+	GPIO_FN(CAN1_TX_C), GPIO_FN(MSIOF1_TXD_E),
+	GPIO_FN(ETH_TX_EN), GPIO_FN(AVB_TXD3),
+	GPIO_FN(TCLK1_B), GPIO_FN(CAN_CLK_B),
+	GPIO_FN(ETH_MAGIC), GPIO_FN(AVB_TXD4), GPIO_FN(IETX_C),
+	GPIO_FN(ETH_TXD0), GPIO_FN(AVB_TXD5), GPIO_FN(IECLK_C),
+	GPIO_FN(ETH_MDC), GPIO_FN(AVB_TXD6), GPIO_FN(IERX_C),
+	GPIO_FN(STP_IVCXO27_0), GPIO_FN(AVB_TXD7), GPIO_FN(SCIFB2_TXD_D),
+	GPIO_FN(ADIDATA_B), GPIO_FN(MSIOF0_SYNC_C),
+	GPIO_FN(STP_ISCLK_0), GPIO_FN(AVB_TX_EN), GPIO_FN(SCIFB2_RXD_D),
+	GPIO_FN(ADICS_SAMP_B), GPIO_FN(MSIOF0_SCK_C),
+
+	/* IPSR13 - IPSR16 */
+};
+
+static struct pinmux_cfg_reg pinmux_config_regs[] = {
+	{ PINMUX_CFG_REG("GPSR0", 0xE6060004, 32, 1) {
+		GP_0_31_FN, FN_IP1_22_20,
+		GP_0_30_FN, FN_IP1_19_17,
+		GP_0_29_FN, FN_IP1_16_14,
+		GP_0_28_FN, FN_IP1_13_11,
+		GP_0_27_FN, FN_IP1_10_8,
+		GP_0_26_FN, FN_IP1_7_6,
+		GP_0_25_FN, FN_IP1_5_4,
+		GP_0_24_FN, FN_IP1_3_2,
+		GP_0_23_FN, FN_IP1_1_0,
+		GP_0_22_FN, FN_IP0_30_29,
+		GP_0_21_FN, FN_IP0_28_27,
+		GP_0_20_FN, FN_IP0_26_25,
+		GP_0_19_FN, FN_IP0_24_23,
+		GP_0_18_FN, FN_IP0_22_21,
+		GP_0_17_FN, FN_IP0_20_19,
+		GP_0_16_FN, FN_IP0_18_16,
+		GP_0_15_FN, FN_IP0_15,
+		GP_0_14_FN, FN_IP0_14,
+		GP_0_13_FN, FN_IP0_13,
+		GP_0_12_FN, FN_IP0_12,
+		GP_0_11_FN, FN_IP0_11,
+		GP_0_10_FN, FN_IP0_10,
+		GP_0_9_FN, FN_IP0_9,
+		GP_0_8_FN, FN_IP0_8,
+		GP_0_7_FN, FN_IP0_7,
+		GP_0_6_FN, FN_IP0_6,
+		GP_0_5_FN, FN_IP0_5,
+		GP_0_4_FN, FN_IP0_4,
+		GP_0_3_FN, FN_IP0_3,
+		GP_0_2_FN, FN_IP0_2,
+		GP_0_1_FN, FN_IP0_1,
+		GP_0_0_FN, FN_IP0_0, }
+	},
+	{ PINMUX_CFG_REG("GPSR1", 0xE6060008, 32, 1) {
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		GP_1_25_FN, FN_IP3_21_20,
+		GP_1_24_FN, FN_IP3_19_18,
+		GP_1_23_FN, FN_IP3_17_16,
+		GP_1_22_FN, FN_IP3_15_14,
+		GP_1_21_FN, FN_IP3_13_12,
+		GP_1_20_FN, FN_IP3_11_9,
+		GP_1_19_FN, FN_RD_N,
+		GP_1_18_FN, FN_IP3_8_6,
+		GP_1_17_FN, FN_IP3_5_3,
+		GP_1_16_FN, FN_IP3_2_0,
+		GP_1_15_FN, FN_IP2_29_27,
+		GP_1_14_FN, FN_IP2_26_25,
+		GP_1_13_FN, FN_IP2_24_23,
+		GP_1_12_FN, FN_EX_CS0_N,
+		GP_1_11_FN, FN_IP2_22_21,
+		GP_1_10_FN, FN_IP2_20_19,
+		GP_1_9_FN, FN_IP2_18_16,
+		GP_1_8_FN, FN_IP2_15_13,
+		GP_1_7_FN, FN_IP2_12_10,
+		GP_1_6_FN, FN_IP2_9_7,
+		GP_1_5_FN, FN_IP2_6_5,
+		GP_1_4_FN, FN_IP2_4_3,
+		GP_1_3_FN, FN_IP2_2_0,
+		GP_1_2_FN, FN_IP1_31_29,
+		GP_1_1_FN, FN_IP1_28_26,
+		GP_1_0_FN, FN_IP1_25_23, }
+	},
+	{ PINMUX_CFG_REG("GPSR2", 0xE606000C, 32, 1) {
+		GP_2_31_FN, FN_IP6_7_6,
+		GP_2_30_FN, FN_IP6_5_3,
+		GP_2_29_FN, FN_IP6_2_0,
+		GP_2_28_FN, FN_AUDIO_CLKA,
+		GP_2_27_FN, FN_IP5_31_29,
+		GP_2_26_FN, FN_IP5_28_26,
+		GP_2_25_FN, FN_IP5_25_24,
+		GP_2_24_FN, FN_IP5_23_22,
+		GP_2_23_FN, FN_IP5_21_20,
+		GP_2_22_FN, FN_IP5_19_17,
+		GP_2_21_FN, FN_IP5_16_15,
+		GP_2_20_FN, FN_IP5_14_12,
+		GP_2_19_FN, FN_IP5_11_9,
+		GP_2_18_FN, FN_IP5_8_6,
+		GP_2_17_FN, FN_IP5_5_3,
+		GP_2_16_FN, FN_IP5_2_0,
+		GP_2_15_FN, FN_IP4_30_28,
+		GP_2_14_FN, FN_IP4_27_26,
+		GP_2_13_FN, FN_IP4_25_24,
+		GP_2_12_FN, FN_IP4_23_22,
+		GP_2_11_FN, FN_IP4_21,
+		GP_2_10_FN, FN_IP4_20,
+		GP_2_9_FN, FN_IP4_19,
+		GP_2_8_FN, FN_IP4_18_16,
+		GP_2_7_FN, FN_IP4_15_13,
+		GP_2_6_FN, FN_IP4_12_10,
+		GP_2_5_FN, FN_IP4_9_8,
+		GP_2_4_FN, FN_IP4_7_5,
+		GP_2_3_FN, FN_IP4_4_2,
+		GP_2_2_FN, FN_IP4_1_0,
+		GP_2_1_FN, FN_IP3_30_28,
+		GP_2_0_FN, FN_IP3_27_25 }
+	},
+	{ PINMUX_CFG_REG("GPSR3", 0xE6060010, 32, 1) {
+		GP_3_31_FN, FN_IP9_18_17,
+		GP_3_30_FN, FN_IP9_16,
+		GP_3_29_FN, FN_IP9_15_13,
+		GP_3_28_FN, FN_IP9_12,
+		GP_3_27_FN, FN_IP9_11,
+		GP_3_26_FN, FN_IP9_10_8,
+		GP_3_25_FN, FN_IP9_7,
+		GP_3_24_FN, FN_IP9_6,
+		GP_3_23_FN, FN_IP9_5_3,
+		GP_3_22_FN, FN_IP9_2_0,
+		GP_3_21_FN, FN_IP8_30_28,
+		GP_3_20_FN, FN_IP8_27_26,
+		GP_3_19_FN, FN_IP8_25_24,
+		GP_3_18_FN, FN_IP8_23_21,
+		GP_3_17_FN, FN_IP8_20_18,
+		GP_3_16_FN, FN_IP8_17_15,
+		GP_3_15_FN, FN_IP8_14_12,
+		GP_3_14_FN, FN_IP8_11_9,
+		GP_3_13_FN, FN_IP8_8_6,
+		GP_3_12_FN, FN_IP8_5_3,
+		GP_3_11_FN, FN_IP8_2_0,
+		GP_3_10_FN, FN_IP7_29_27,
+		GP_3_9_FN, FN_IP7_26_24,
+		GP_3_8_FN, FN_IP7_23_21,
+		GP_3_7_FN, FN_IP7_20_19,
+		GP_3_6_FN, FN_IP7_18_17,
+		GP_3_5_FN, FN_IP7_16_15,
+		GP_3_4_FN, FN_IP7_14_13,
+		GP_3_3_FN, FN_IP7_12_11,
+		GP_3_2_FN, FN_IP7_10_9,
+		GP_3_1_FN, FN_IP7_8_6,
+		GP_3_0_FN, FN_IP7_5_3 }
+	},
+	{ PINMUX_CFG_REG("GPSR4", 0xE6060014, 32, 1) {
+		GP_4_31_FN, FN_IP15_5_4,
+		GP_4_30_FN, FN_IP15_3_2,
+		GP_4_29_FN, FN_IP15_1_0,
+		GP_4_28_FN, FN_IP11_8_6,
+		GP_4_27_FN, FN_IP11_5_3,
+		GP_4_26_FN, FN_IP11_2_0,
+		GP_4_25_FN, FN_IP10_31_29,
+		GP_4_24_FN, FN_IP10_28_27,
+		GP_4_23_FN, FN_IP10_26_25,
+		GP_4_22_FN, FN_IP10_24_22,
+		GP_4_21_FN, FN_IP10_21_19,
+		GP_4_20_FN, FN_IP10_18_17,
+		GP_4_19_FN, FN_IP10_16_15,
+		GP_4_18_FN, FN_IP10_14_12,
+		GP_4_17_FN, FN_IP10_11_9,
+		GP_4_16_FN, FN_IP10_8_6,
+		GP_4_15_FN, FN_IP10_5_3,
+		GP_4_14_FN, FN_IP10_2_0,
+		GP_4_13_FN, FN_IP9_31_29,
+		GP_4_12_FN, FN_VI0_DATA0_VI0_B7,
+		GP_4_11_FN, FN_VI0_DATA0_VI0_B6,
+		GP_4_10_FN, FN_VI0_DATA0_VI0_B5,
+		GP_4_9_FN, FN_VI0_DATA0_VI0_B4,
+		GP_4_8_FN, FN_IP9_28_27,
+		GP_4_7_FN, FN_VI0_DATA0_VI0_B2,
+		GP_4_6_FN, FN_VI0_DATA0_VI0_B1,
+		GP_4_5_FN, FN_VI0_DATA0_VI0_B0,
+		GP_4_4_FN, FN_IP9_26_25,
+		GP_4_3_FN, FN_IP9_24_23,
+		GP_4_2_FN, FN_IP9_22_21,
+		GP_4_1_FN, FN_IP9_20_19,
+		GP_4_0_FN, FN_VI0_CLK }
+	},
+	{ PINMUX_CFG_REG("GPSR5", 0xE6060018, 32, 1) {
+		GP_5_31_FN, FN_IP3_24_22,
+		GP_5_30_FN, FN_IP13_9_7,
+		GP_5_29_FN, FN_IP13_6_5,
+		GP_5_28_FN, FN_IP13_4_3,
+		GP_5_27_FN, FN_IP13_2_0,
+		GP_5_26_FN, FN_IP12_29_27,
+		GP_5_25_FN, FN_IP12_26_24,
+		GP_5_24_FN, FN_IP12_23_22,
+		GP_5_23_FN, FN_IP12_21_20,
+		GP_5_22_FN, FN_IP12_19_18,
+		GP_5_21_FN, FN_IP12_17_16,
+		GP_5_20_FN, FN_IP12_15_13,
+		GP_5_19_FN, FN_IP12_12_10,
+		GP_5_18_FN, FN_IP12_9_7,
+		GP_5_17_FN, FN_IP12_6_4,
+		GP_5_16_FN, FN_IP12_3_2,
+		GP_5_15_FN, FN_IP12_1_0,
+		GP_5_14_FN, FN_IP11_31_30,
+		GP_5_13_FN, FN_IP11_29_28,
+		GP_5_12_FN, FN_IP11_27,
+		GP_5_11_FN, FN_IP11_26,
+		GP_5_10_FN, FN_IP11_25,
+		GP_5_9_FN, FN_IP11_24,
+		GP_5_8_FN, FN_IP11_23,
+		GP_5_7_FN, FN_IP11_22,
+		GP_5_6_FN, FN_IP11_21,
+		GP_5_5_FN, FN_IP11_20,
+		GP_5_4_FN, FN_IP11_19,
+		GP_5_3_FN, FN_IP11_18_17,
+		GP_5_2_FN, FN_IP11_16_15,
+		GP_5_1_FN, FN_IP11_14_12,
+		GP_5_0_FN, FN_IP11_11_9 }
+	},
+	{ PINMUX_CFG_REG("GPSR6", 0xE606001C, 32, 1) {
+		0, 0,
+		0, 0,
+		GP_6_29_FN, FN_IP14_31_29,
+		GP_6_28_FN, FN_IP14_28_26,
+		GP_6_27_FN, FN_IP14_25_23,
+		GP_6_26_FN, FN_IP14_22_20,
+		GP_6_25_FN, FN_IP14_19_17,
+		GP_6_24_FN, FN_IP14_16_14,
+		GP_6_23_FN, FN_IP14_13_11,
+		GP_6_22_FN, FN_IP14_10_8,
+		GP_6_21_FN, FN_IP14_7,
+		GP_6_20_FN, FN_IP14_6,
+		GP_6_19_FN, FN_IP14_5,
+		GP_6_18_FN, FN_IP14_4,
+		GP_6_17_FN, FN_IP14_3,
+		GP_6_16_FN, FN_IP14_2,
+		GP_6_15_FN, FN_IP14_1_0,
+		GP_6_14_FN, FN_IP13_30_28,
+		GP_6_13_FN, FN_IP13_27,
+		GP_6_12_FN, FN_IP13_26,
+		GP_6_11_FN, FN_IP13_25,
+		GP_6_10_FN, FN_IP13_24_23,
+		GP_6_9_FN, FN_IP13_22,
+		0, 0,
+		GP_6_7_FN, FN_IP13_21_19,
+		GP_6_6_FN, FN_IP13_18_16,
+		GP_6_5_FN, FN_IP13_15,
+		GP_6_4_FN, FN_IP13_14,
+		GP_6_3_FN, FN_IP13_13,
+		GP_6_2_FN, FN_IP13_12,
+		GP_6_1_FN, FN_IP13_11,
+		GP_6_0_FN, FN_IP13_10 }
+	},
+	{ PINMUX_CFG_REG("GPSR7", 0xE6060074, 32, 1) {
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		GP_7_25_FN, FN_USB1_PWEN,
+		GP_7_24_FN, FN_USB0_OVC,
+		GP_7_23_FN, FN_USB0_PWEN,
+		GP_7_22_FN, FN_IP15_14_12,
+		GP_7_21_FN, FN_IP15_11_9,
+		GP_7_20_FN, FN_IP15_8_6,
+		GP_7_19_FN, FN_IP7_2_0,
+		GP_7_18_FN, FN_IP6_29_27,
+		GP_7_17_FN, FN_IP6_26_24,
+		GP_7_16_FN, FN_IP6_23_21,
+		GP_7_15_FN, FN_IP6_20_19,
+		GP_7_14_FN, FN_IP6_18_16,
+		GP_7_13_FN, FN_IP6_15_14,
+		GP_7_12_FN, FN_IP6_13_12,
+		GP_7_11_FN, FN_IP6_11_10,
+		GP_7_10_FN, FN_IP6_9_8,
+		GP_7_9_FN, FN_IP16_11_10,
+		GP_7_8_FN, FN_IP16_9_8,
+		GP_7_7_FN, FN_IP16_7_6,
+		GP_7_6_FN, FN_IP16_5_3,
+		GP_7_5_FN, FN_IP16_2_0,
+		GP_7_4_FN, FN_IP15_29_27,
+		GP_7_3_FN, FN_IP15_26_24,
+		GP_7_2_FN, FN_IP15_23_21,
+		GP_7_1_FN, FN_IP15_20_18,
+		GP_7_0_FN, FN_IP15_17_15 }
+	},
+	/* IPSR0 - IPSR10 */
+	{ PINMUX_CFG_REG_VAR("IPSR11", 0xE606004C, 32,
+			     2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 2, 2,
+			     3, 3, 3, 3, 3) {
+		/* IP11_31_30 [2] */
+		FN_ETH_CRS_DV, FN_AVB_LINK, FN_SDA2_C, 0,
+		/* IP11_29_28 [2] */
+		FN_ETH_MDIO, FN_AVB_RX_CLK, FN_SCL2_C, 0,
+		/* IP11_27 [1] */
+		FN_VI1_DATA7, FN_AVB_MDC,
+		/* IP11_26 [1] */
+		FN_VI1_DATA6, FN_AVB_MAGIC,
+		/* IP11_25 [1] */
+		FN_VI1_DATA5, FN_AVB_RX_DV,
+		/* IP11_24 [1] */
+		FN_VI1_DATA4, FN_AVB_MDIO,
+		/* IP11_23 [1] */
+		FN_VI1_DATA3, FN_AVB_RX_ER,
+		/* IP11_22 [1] */
+		FN_VI1_DATA2, FN_AVB_RXD7,
+		/* IP11_21 [1] */
+		FN_VI1_DATA1, FN_AVB_RXD6,
+		/* IP11_20 [1] */
+		FN_VI1_DATA0, FN_AVB_RXD5,
+		/* IP11_19 [1] */
+		FN_VI1_CLK, FN_AVB_RXD4,
+		/* IP11_18_17 [2] */
+		FN_VI1_FIELD, FN_AVB_RXD3, FN_TS_SPSYNC0_B, 0,
+		/* IP11_16_15 [2] */
+		FN_VI1_CLKENB, FN_AVB_RXD2, FN_TS_SDEN0_B, 0,
+		/* IP11_14_12 [3] */
+		FN_VI1_VSYNC_N, FN_AVB_RXD1, FN_TS_SCK0_B,
+		FN_RX4_B, FN_SCIFA4_RXD_B,
+		0, 0, 0,
+		/* IP11_11_9 [3] */
+		FN_VI1_HSYNC_N, FN_AVB_RXD0, FN_TS_SDATA0_B,
+		FN_TX4_B, FN_SCIFA4_TXD_B,
+		0, 0, 0,
+		/* IP11_8_6 [3] */
+		FN_VI0_R7, FN_GLO_RFON_B, FN_RX1_C, FN_CAN0_RX_E,
+		FN_SDA4_B, FN_HRX1_D, FN_SCIFB0_RXD_D, 0,
+		/* IP11_5_3 [3] */
+		FN_VI0_R6, FN_VI2_DATA7, FN_GLO_SS_B, FN_TX1_C, FN_SCL4_B,
+		0, 0, 0,
+		/* IP11_2_0 [3] */
+		FN_VI0_R5, FN_VI2_DATA6, FN_GLO_SDATA_B, FN_RX0_C, FN_SDA1_D,
+		0, 0, 0, }
+	},
+	{ PINMUX_CFG_REG_VAR("IPSR12", 0xE6060050, 32,
+			     2, 3, 3, 2, 2, 2, 2, 3, 3, 3, 3, 2, 2) {
+		/* IP12_31_30 [2] */
+		0, 0, 0, 0,
+		/* IP12_29_27 [3] */
+		FN_STP_ISCLK_0, FN_AVB_TX_EN, FN_SCIFB2_RXD_D,
+		FN_ADICS_SAMP_B, FN_MSIOF0_SCK_C,
+		0, 0, 0,
+		/* IP12_26_24 [3] */
+		FN_STP_IVCXO27_0, FN_AVB_TXD7, FN_SCIFB2_TXD_D,
+		FN_ADIDATA_B, FN_MSIOF0_SYNC_C,
+		0, 0, 0,
+		/* IP12_23_22 [2] */
+		FN_ETH_MDC, FN_AVB_TXD6, FN_IERX_C, 0,
+		/* IP12_21_20 [2] */
+		FN_ETH_TXD0, FN_AVB_TXD5, FN_IECLK_C, 0,
+		/* IP12_19_18 [2] */
+		FN_ETH_MAGIC, FN_AVB_TXD4, FN_IETX_C, 0,
+		/* IP12_17_16 [2] */
+		FN_ETH_TX_EN, FN_AVB_TXD3, FN_TCLK1_B, FN_CAN_CLK_B,
+		/* IP12_15_13 [3] */
+		FN_ETH_TXD1, FN_AVB_TXD2, FN_SCIFA3_TXD_B,
+		FN_CAN1_TX_C, FN_MSIOF1_TXD_E,
+		0, 0, 0,
+		/* IP12_12_10 [3] */
+		FN_ETH_REFCLK, FN_AVB_TXD1, FN_SCIFA3_RXD_B,
+		FN_CAN1_RX_C, FN_MSIOF1_SYNC_E,
+		0, 0, 0,
+		/* IP12_9_7 [3] */
+		FN_ETH_LINK, FN_AVB_TXD0, FN_CAN0_RX_C,
+		FN_SDA2_D, FN_MSIOF1_SCK_E,
+		0, 0, 0,
+		/* IP12_6_4 [3] */
+		FN_ETH_RXD1, FN_AVB_GTXREFCLK, FN_CAN0_TX_C,
+		FN_SCL2_D, FN_MSIOF1_RXD_E,
+		0, 0, 0,
+		/* IP12_3_2 [2] */
+		FN_ETH_RXD0, FN_AVB_PHY_INT, FN_SDA3, FN_SDA7,
+		/* IP12_1_0 [2] */
+		FN_ETH_RX_ER, FN_AVB_CRS, FN_SCL3, FN_SCL7, }
+	},
+
+	/* IPSR13 - IPSR16 */
+
+	{ PINMUX_CFG_REG_VAR("MOD_SEL", 0xE6060090, 32,
+			     1, 2, 2, 2, 3, 2, 1, 1, 1, 1,
+			     3, 2, 2, 2, 1, 2, 2, 2) {
+		/* RESEVED [1] */
+		0, 0,
+		/* SEL_SCIF1 [2] */
+		FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2, FN_SEL_SCIF1_3,
+		/* SEL_SCIFB [2] */
+		FN_SEL_SCIFB_0, FN_SEL_SCIFB_1, FN_SEL_SCIFB_2, FN_SEL_SCIFB_3,
+		/* SEL_SCIFB2 [2] */
+		FN_SEL_SCIFB2_0, FN_SEL_SCIFB2_1,
+		FN_SEL_SCIFB2_2, FN_SEL_SCIFB2_3,
+		/* SEL_SCIFB1 [3] */
+		FN_SEL_SCIFB1_0, FN_SEL_SCIFB1_1,
+		FN_SEL_SCIFB1_2, FN_SEL_SCIFB1_3,
+		0, 0, 0, 0,
+		/* SEL_SCIFA1 [2] */
+		FN_SEL_SCIFA1_0, FN_SEL_SCIFA1_1, FN_SEL_SCIFA1_2, 0,
+		/* SEL_SSI9 [1] */
+		FN_SEL_SSI9_0, FN_SEL_SSI9_1,
+		/* SEL_SCFA [1] */
+		FN_SEL_SCFA_0, FN_SEL_SCFA_1,
+		/* SEL_QSP [1] */
+		FN_SEL_QSP_0, FN_SEL_QSP_1,
+		/* SEL_SSI7 [1] */
+		FN_SEL_SSI7_0, FN_SEL_SSI7_1,
+		/* SEL_HSCIF1 [3] */
+		FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1, FN_SEL_HSCIF1_2,
+		FN_SEL_HSCIF1_3, FN_SEL_HSCIF1_4,
+		0, 0, 0,
+		/* RESEVED [2] */
+		0, 0, 0, 0,
+		/* SEL_VI1 [2] */
+		FN_SEL_VI1_0, FN_SEL_VI1_1, FN_SEL_VI1_2, 0,
+		/* RESEVED [2] */
+		0, 0, 0, 0,
+		/* SEL_TMU [1] */
+		FN_SEL_TMU1_0, FN_SEL_TMU1_1,
+		/* SEL_LBS [2] */
+		FN_SEL_LBS_0, FN_SEL_LBS_1, FN_SEL_LBS_2, FN_SEL_LBS_3,
+		/* SEL_TSIF0 [2] */
+		FN_SEL_TSIF0_0, FN_SEL_TSIF0_1, FN_SEL_TSIF0_2, FN_SEL_TSIF0_3,
+		/* SEL_SOF0 [2] */
+		FN_SEL_SOF0_0, FN_SEL_SOF0_1, FN_SEL_SOF0_2, 0, }
+	},
+	{ PINMUX_CFG_REG_VAR("MOD_SEL2", 0xE6060094, 32,
+			     3, 1, 1, 3, 2, 1, 1, 2, 2,
+			     1, 3, 2, 1, 2, 2, 2, 1, 1, 1) {
+		/* SEL_SCIF0 [3] */
+		FN_SEL_SCIF0_0, FN_SEL_SCIF0_1, FN_SEL_SCIF0_2,
+		FN_SEL_SCIF0_3, FN_SEL_SCIF0_4,
+		0, 0, 0,
+		/* RESEVED [1] */
+		0, 0,
+		/* SEL_SCIF [1] */
+		FN_SEL_SCIF_0, FN_SEL_SCIF_1,
+		/* SEL_CAN0 [3] */
+		FN_SEL_CAN0_0, FN_SEL_CAN0_1, FN_SEL_CAN0_2, FN_SEL_CAN0_3,
+		FN_SEL_CAN0_4, FN_SEL_CAN0_5,
+		0, 0,
+		/* SEL_CAN1 [2] */
+		FN_SEL_CAN1_0, FN_SEL_CAN1_1, FN_SEL_CAN1_2, FN_SEL_CAN1_3,
+		/* RESEVED [1] */
+		0, 0,
+		/* SEL_SCIFA2 [1] */
+		FN_SEL_SCIFA2_0, FN_SEL_SCIFA2_1,
+		/* SEL_SCIF4 [2] */
+		FN_SEL_SCIF4_0, FN_SEL_SCIF4_1, FN_SEL_SCIF4_2, 0,
+		/* RESEVED [2] */
+		0, 0, 0, 0,
+		/* SEL_ADG [1] */
+		FN_SEL_ADG_0, FN_SEL_ADG_1,
+		/* SEL_FM [3] */
+		FN_SEL_FM_0, FN_SEL_FM_1, FN_SEL_FM_2,
+		FN_SEL_FM_3, FN_SEL_FM_4,
+		0, 0, 0,
+		/* SEL_SCIFA5 [2] */
+		FN_SEL_SCIFA5_0, FN_SEL_SCIFA5_1, FN_SEL_SCIFA5_2, 0,
+		/* RESEVED [1] */
+		0, 0,
+		/* SEL_GPS [2] */
+		FN_SEL_GPS_0, FN_SEL_GPS_1, FN_SEL_GPS_2, FN_SEL_GPS_3,
+		/* SEL_SCIFA4 [2] */
+		FN_SEL_SCIFA4_0, FN_SEL_SCIFA4_1, FN_SEL_SCIFA4_2, 0,
+		/* SEL_SCIFA3 [2] */
+		FN_SEL_SCIFA3_0, FN_SEL_SCIFA3_1, FN_SEL_SCIFA3_2, 0,
+		/* SEL_SIM [1] */
+		FN_SEL_SIM_0, FN_SEL_SIM_1,
+		/* RESEVED [1] */
+		0, 0,
+		/* SEL_SSI8 [1] */
+		FN_SEL_SSI8_0, FN_SEL_SSI8_1, }
+	},
+	{ PINMUX_CFG_REG_VAR("MOD_SEL3", 0xE6060098, 32,
+			     2, 2, 2, 2, 2, 2, 2, 2,
+			     1, 1, 2, 2, 3, 2, 2, 2, 1) {
+		/* SEL_HSCIF2 [2] */
+		FN_SEL_HSCIF2_0, FN_SEL_HSCIF2_1,
+		FN_SEL_HSCIF2_2, FN_SEL_HSCIF2_3,
+		/* SEL_CANCLK [2] */
+		FN_SEL_CANCLK_0, FN_SEL_CANCLK_1,
+		FN_SEL_CANCLK_2, FN_SEL_CANCLK_3,
+		/* SEL_IIC8 [2] */
+		FN_SEL_IIC8_0, FN_SEL_IIC8_1, FN_SEL_IIC8_2, 0,
+		/* SEL_IIC7 [2] */
+		FN_SEL_IIC7_0, FN_SEL_IIC7_1, FN_SEL_IIC7_2, 0,
+		/* SEL_IIC4 [2] */
+		FN_SEL_IIC4_0, FN_SEL_IIC4_1, FN_SEL_IIC4_2, 0,
+		/* SEL_IIC3 [2] */
+		FN_SEL_IIC3_0, FN_SEL_IIC3_1, FN_SEL_IIC3_2, FN_SEL_IIC3_3,
+		/* SEL_SCIF3 [2] */
+		FN_SEL_SCIF3_0, FN_SEL_SCIF3_1, FN_SEL_SCIF3_2, FN_SEL_SCIF3_3,
+		/* SEL_IEB [2] */
+		FN_SEL_IEB_0, FN_SEL_IEB_1, FN_SEL_IEB_2,
+		/* SEL_MMC [1] */
+		FN_SEL_MMC_0, FN_SEL_MMC_1,
+		/* SEL_SCIF5 [1] */
+		FN_SEL_SCIF5_0, FN_SEL_SCIF5_1,
+		/* RESEVED [2] */
+		0, 0, 0, 0,
+		/* SEL_IIC2 [2] */
+		FN_SEL_IIC2_0, FN_SEL_IIC2_1, FN_SEL_IIC2_2, FN_SEL_IIC2_3,
+		/* SEL_IIC1 [3] */
+		FN_SEL_IIC1_0, FN_SEL_IIC1_1, FN_SEL_IIC1_2, FN_SEL_IIC1_3,
+		FN_SEL_IIC1_4,
+		0, 0, 0,
+		/* SEL_IIC0 [2] */
+		FN_SEL_IIC0_0, FN_SEL_IIC0_1, FN_SEL_IIC0_2, 0,
+		/* RESEVED [2] */
+		0, 0, 0, 0,
+		/* RESEVED [2] */
+		0, 0, 0, 0,
+		/* RESEVED [1] */
+		0, 0, }
+	},
+	{ PINMUX_CFG_REG_VAR("MOD_SEL4", 0xE606009C, 32,
+			     3, 2, 2, 1, 1, 1, 1, 3, 2,
+			     2, 3, 1, 1, 1, 2, 2, 2, 2) {
+		/* SEL_SOF1 [3] */
+		FN_SEL_SOF1_0, FN_SEL_SOF1_1, FN_SEL_SOF1_2, FN_SEL_SOF1_3,
+		FN_SEL_SOF1_4,
+		0, 0, 0,
+		/* SEL_HSCIF0 [2] */
+		FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1, FN_SEL_HSCIF0_2, 0,
+		/* SEL_DIS [2] */
+		FN_SEL_DIS_0, FN_SEL_DIS_1, FN_SEL_DIS_2, 0,
+		/* RESEVED [1] */
+		0, 0,
+		/* SEL_RAD [1] */
+		FN_SEL_RAD_0, FN_SEL_RAD_1,
+		/* SEL_RCN [1] */
+		FN_SEL_RCN_0, FN_SEL_RCN_1,
+		/* SEL_RSP [1] */
+		FN_SEL_RSP_0, FN_SEL_RSP_1,
+		/* SEL_SCIF2 [3] */
+		FN_SEL_SCIF2_0, FN_SEL_SCIF2_1, FN_SEL_SCIF2_2,
+		FN_SEL_SCIF2_3, FN_SEL_SCIF2_4,
+		0, 0, 0,
+		/* RESEVED [2] */
+		0, 0, 0, 0,
+		/* RESEVED [2] */
+		0, 0, 0, 0,
+		/* SEL_SOF2 [3] */
+		FN_SEL_SOF2_0, FN_SEL_SOF2_1, FN_SEL_SOF2_2,
+		FN_SEL_SOF2_3, FN_SEL_SOF2_4,
+		0, 0, 0,
+		/* RESEVED [1] */
+		0, 0,
+		/* SEL_SSI1 [1] */
+		FN_SEL_SSI1_0, FN_SEL_SSI1_1,
+		/* SEL_SSI0 [1] */
+		FN_SEL_SSI0_0, FN_SEL_SSI0_1,
+		/* SEL_SSP [2] */
+		FN_SEL_SSP_0, FN_SEL_SSP_1, FN_SEL_SSP_2, 0,
+		/* RESEVED [2] */
+		0, 0, 0, 0,
+		/* RESEVED [2] */
+		0, 0, 0, 0,
+		/* RESEVED [2] */
+		0, 0, 0, 0, }
+	},
+	{ PINMUX_CFG_REG("INOUTSEL0", 0xE6050004, 32, 1) { GP_INOUTSEL(0) } },
+	{ PINMUX_CFG_REG("INOUTSEL1", 0xE6051004, 32, 1) {
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		GP_1_25_IN, GP_1_25_OUT,
+		GP_1_24_IN, GP_1_24_OUT,
+		GP_1_23_IN, GP_1_23_OUT,
+		GP_1_22_IN, GP_1_22_OUT,
+		GP_1_21_IN, GP_1_21_OUT,
+		GP_1_20_IN, GP_1_20_OUT,
+		GP_1_19_IN, GP_1_19_OUT,
+		GP_1_18_IN, GP_1_18_OUT,
+		GP_1_17_IN, GP_1_17_OUT,
+		GP_1_16_IN, GP_1_16_OUT,
+		GP_1_15_IN, GP_1_15_OUT,
+		GP_1_14_IN, GP_1_14_OUT,
+		GP_1_13_IN, GP_1_13_OUT,
+		GP_1_12_IN, GP_1_12_OUT,
+		GP_1_11_IN, GP_1_11_OUT,
+		GP_1_10_IN, GP_1_10_OUT,
+		GP_1_9_IN, GP_1_9_OUT,
+		GP_1_8_IN, GP_1_8_OUT,
+		GP_1_7_IN, GP_1_7_OUT,
+		GP_1_6_IN, GP_1_6_OUT,
+		GP_1_5_IN, GP_1_5_OUT,
+		GP_1_4_IN, GP_1_4_OUT,
+		GP_1_3_IN, GP_1_3_OUT,
+		GP_1_2_IN, GP_1_2_OUT,
+		GP_1_1_IN, GP_1_1_OUT,
+		GP_1_0_IN, GP_1_0_OUT, }
+	},
+	{ PINMUX_CFG_REG("INOUTSEL2", 0xE6052004, 32, 1) { GP_INOUTSEL(2) } },
+	{ PINMUX_CFG_REG("INOUTSEL3", 0xE6053004, 32, 1) { GP_INOUTSEL(3) } },
+	{ PINMUX_CFG_REG("INOUTSEL4", 0xE6054004, 32, 1) { GP_INOUTSEL(4) } },
+	{ PINMUX_CFG_REG("INOUTSEL5", 0xE6055004, 32, 1) { GP_INOUTSEL(5) } },
+	{ PINMUX_CFG_REG("INOUTSEL6", 0xE6055404, 32, 1) { GP_INOUTSEL(6) } },
+	{ PINMUX_CFG_REG("INOUTSEL7", 0xE6055804, 32, 1) {
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		GP_7_25_IN, GP_7_25_OUT,
+		GP_7_24_IN, GP_7_24_OUT,
+		GP_7_23_IN, GP_7_23_OUT,
+		GP_7_22_IN, GP_7_22_OUT,
+		GP_7_21_IN, GP_7_21_OUT,
+		GP_7_20_IN, GP_7_20_OUT,
+		GP_7_19_IN, GP_7_19_OUT,
+		GP_7_18_IN, GP_7_18_OUT,
+		GP_7_17_IN, GP_7_17_OUT,
+		GP_7_16_IN, GP_7_16_OUT,
+		GP_7_15_IN, GP_7_15_OUT,
+		GP_7_14_IN, GP_7_14_OUT,
+		GP_7_13_IN, GP_7_13_OUT,
+		GP_7_12_IN, GP_7_12_OUT,
+		GP_7_11_IN, GP_7_11_OUT,
+		GP_7_10_IN, GP_7_10_OUT,
+		GP_7_9_IN, GP_7_9_OUT,
+		GP_7_8_IN, GP_7_8_OUT,
+		GP_7_7_IN, GP_7_7_OUT,
+		GP_7_6_IN, GP_7_6_OUT,
+		GP_7_5_IN, GP_7_5_OUT,
+		GP_7_4_IN, GP_7_4_OUT,
+		GP_7_3_IN, GP_7_3_OUT,
+		GP_7_2_IN, GP_7_2_OUT,
+		GP_7_1_IN, GP_7_1_OUT,
+		GP_7_0_IN, GP_7_0_OUT, }
+	},
+	{ },
+};
+
+static struct pinmux_data_reg pinmux_data_regs[] = {
+	{ PINMUX_DATA_REG("INDT0", 0xE6050008, 32) { GP_INDT(0) } },
+	{ PINMUX_DATA_REG("INDT1", 0xE6051008, 32) {
+		0, 0, 0, 0,
+		0, 0, GP_1_25_DATA, GP_1_24_DATA,
+		GP_1_23_DATA, GP_1_22_DATA, GP_1_21_DATA, GP_1_20_DATA,
+		GP_1_19_DATA, GP_1_18_DATA, GP_1_17_DATA, GP_1_16_DATA,
+		GP_1_15_DATA, GP_1_14_DATA, GP_1_13_DATA, GP_1_12_DATA,
+		GP_1_11_DATA, GP_1_10_DATA, GP_1_9_DATA, GP_1_8_DATA,
+		GP_1_7_DATA, GP_1_6_DATA, GP_1_5_DATA, GP_1_4_DATA,
+		GP_1_3_DATA, GP_1_2_DATA, GP_1_1_DATA, GP_1_0_DATA }
+	},
+	{ PINMUX_DATA_REG("INDT2", 0xE6052008, 32) { GP_INDT(2) } },
+	{ PINMUX_DATA_REG("INDT3", 0xE6053008, 32) { GP_INDT(3) } },
+	{ PINMUX_DATA_REG("INDT4", 0xE6054008, 32) { GP_INDT(4) } },
+	{ PINMUX_DATA_REG("INDT5", 0xE6055008, 32) { GP_INDT(5) } },
+	{ PINMUX_DATA_REG("INDT6", 0xE6055408, 32) { GP_INDT(6) } },
+	{ PINMUX_DATA_REG("INDT7", 0xE6055808, 32) {
+		0, 0, 0, 0,
+		0, 0, GP_7_25_DATA, GP_7_24_DATA,
+		GP_7_23_DATA, GP_7_22_DATA, GP_7_21_DATA, GP_7_20_DATA,
+		GP_7_19_DATA, GP_7_18_DATA, GP_7_17_DATA, GP_7_16_DATA,
+		GP_7_15_DATA, GP_7_14_DATA, GP_7_13_DATA, GP_7_12_DATA,
+		GP_7_11_DATA, GP_7_10_DATA, GP_7_9_DATA, GP_7_8_DATA,
+		GP_7_7_DATA, GP_7_6_DATA, GP_7_5_DATA, GP_7_4_DATA,
+		GP_7_3_DATA, GP_7_2_DATA, GP_7_1_DATA, GP_7_0_DATA }
+	},
+	{ },
+};
+
+static struct pinmux_info r8a7791_pinmux_info = {
+	.name = "r8a7791_pfc",
+
+	.unlock_reg = 0xe6060000, /* PMMR */
+
+	.reserved_id = PINMUX_RESERVED,
+	.data = { PINMUX_DATA_BEGIN, PINMUX_DATA_END },
+	.input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END },
+	.output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END },
+	.mark = { PINMUX_MARK_BEGIN, PINMUX_MARK_END },
+	.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
+
+	.first_gpio = GPIO_GP_0_0,
+	.last_gpio = GPIO_FN_MSIOF0_SCK_C /* GPIO_FN_CAN1_RX_B */,
+
+	.gpios = pinmux_gpios,
+	.cfg_regs = pinmux_config_regs,
+	.data_regs = pinmux_data_regs,
+
+	.gpio_data = pinmux_data,
+	.gpio_data_size = ARRAY_SIZE(pinmux_data),
+};
+
+void r8a7791_pinmux_init(void)
+{
+	register_pinmux(&r8a7791_pinmux_info);
+}
diff --git a/arch/arm/cpu/armv7/rmobile/timer.c b/arch/arm/cpu/armv7/rmobile/timer.c
index 72e0c12545..04700e7d34 100644
--- a/arch/arm/cpu/armv7/rmobile/timer.c
+++ b/arch/arm/cpu/armv7/rmobile/timer.c
@@ -6,6 +6,7 @@
  */
 
 #include <common.h>
+#include <div64.h>
 #include <asm/io.h>
 #include <asm/arch-armv7/globaltimer.h>
 #include <asm/arch/rmobile.h>
@@ -38,13 +39,16 @@ static u64 get_time_us(void)
 	u64 timer = get_cpu_global_timer();
 
 	timer = ((timer << 2) + (CLK2MHZ(CONFIG_SYS_CPU_CLK) >> 1));
-	timer /= (u64)CLK2MHZ(CONFIG_SYS_CPU_CLK);
+	do_div(timer, CLK2MHZ(CONFIG_SYS_CPU_CLK));
 	return timer;
 }
 
 static ulong get_time_ms(void)
 {
-	return (ulong)(get_time_us() / 1000);
+	u64 us = get_time_us();
+
+	do_div(us, 1000);
+	return us;
 }
 
 int timer_init(void)
diff --git a/arch/arm/cpu/armv7/s5p-common/Makefile b/arch/arm/cpu/armv7/s5p-common/Makefile
index fd7290caa3..f571d8a0e0 100644
--- a/arch/arm/cpu/armv7/s5p-common/Makefile
+++ b/arch/arm/cpu/armv7/s5p-common/Makefile
@@ -5,30 +5,9 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)libs5p-common.o
-
-COBJS-y		+= cpu_info.o
+obj-y		+= cpu_info.o
 ifndef CONFIG_SPL_BUILD
-COBJS-y		+= timer.o
-COBJS-y		+= sromc.o
-COBJS-$(CONFIG_PWM)	+= pwm.o
+obj-y		+= timer.o
+obj-y		+= sromc.o
+obj-$(CONFIG_PWM)	+= pwm.o
 endif
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS-y) $(SOBJS))
-
-all:	 $(obj).depend $(LIB)
-
-$(LIB):	$(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
diff --git a/arch/arm/cpu/armv7/s5pc1xx/Makefile b/arch/arm/cpu/armv7/s5pc1xx/Makefile
index 09fed66bfd..9f43ded1d9 100644
--- a/arch/arm/cpu/armv7/s5pc1xx/Makefile
+++ b/arch/arm/cpu/armv7/s5pc1xx/Makefile
@@ -8,28 +8,7 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
+obj-y	= cache.o
+obj-y	+= reset.o
 
-LIB	= $(obj)lib$(SOC).o
-
-SOBJS	= cache.o
-SOBJS	+= reset.o
-
-COBJS	+= clock.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS) $(SOBJS))
-
-all:	 $(obj).depend $(LIB)
-
-$(LIB):	$(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	+= clock.o
diff --git a/arch/arm/cpu/armv7/socfpga/Makefile b/arch/arm/cpu/armv7/socfpga/Makefile
index 0859e443d8..cbe1d406df 100644
--- a/arch/arm/cpu/armv7/socfpga/Makefile
+++ b/arch/arm/cpu/armv7/socfpga/Makefile
@@ -7,29 +7,6 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-
-include $(TOPDIR)/config.mk
-
-LIB	=  $(obj)lib$(SOC).o
-
-SOBJS	:= lowlevel_init.o
-COBJS-y	:= misc.o timer.o reset_manager.o system_manager.o
-COBJS-$(CONFIG_SPL_BUILD) += spl.o
-
-COBJS	:= $(COBJS-y)
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS) $(SOBJS))
-
-all:	 $(obj).depend $(LIB)
-
-$(LIB):	$(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	:= lowlevel_init.o
+obj-y	+= misc.o timer.o reset_manager.o system_manager.o clock_manager.o
+obj-$(CONFIG_SPL_BUILD) += spl.o freeze_controller.o
diff --git a/arch/arm/cpu/armv7/socfpga/clock_manager.c b/arch/arm/cpu/armv7/socfpga/clock_manager.c
new file mode 100644
index 0000000000..23d697dee2
--- /dev/null
+++ b/arch/arm/cpu/armv7/socfpga/clock_manager.c
@@ -0,0 +1,361 @@
+/*
+ *  Copyright (C) 2013 Altera Corporation <www.altera.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/clock_manager.h>
+
+static const struct socfpga_clock_manager *clock_manager_base =
+		(void *)SOCFPGA_CLKMGR_ADDRESS;
+
+#define CLKMGR_BYPASS_ENABLE	1
+#define CLKMGR_BYPASS_DISABLE	0
+#define CLKMGR_STAT_IDLE	0
+#define CLKMGR_STAT_BUSY	1
+#define CLKMGR_BYPASS_PERPLLSRC_SELECT_EOSC1		0
+#define CLKMGR_BYPASS_PERPLLSRC_SELECT_INPUT_MUX	1
+#define CLKMGR_BYPASS_SDRPLLSRC_SELECT_EOSC1		0
+#define CLKMGR_BYPASS_SDRPLLSRC_SELECT_INPUT_MUX	1
+
+#define CLEAR_BGP_EN_PWRDN \
+	(CLKMGR_MAINPLLGRP_VCO_PWRDN_SET(0)| \
+	CLKMGR_MAINPLLGRP_VCO_EN_SET(0)| \
+	CLKMGR_MAINPLLGRP_VCO_BGPWRDN_SET(0))
+
+#define VCO_EN_BASE \
+	(CLKMGR_MAINPLLGRP_VCO_PWRDN_SET(0)| \
+	CLKMGR_MAINPLLGRP_VCO_EN_SET(1)| \
+	CLKMGR_MAINPLLGRP_VCO_BGPWRDN_SET(0))
+
+static inline void cm_wait_for_lock(uint32_t mask)
+{
+	register uint32_t inter_val;
+	do {
+		inter_val = readl(&clock_manager_base->inter) & mask;
+	} while (inter_val != mask);
+}
+
+/* function to poll in the fsm busy bit */
+static inline void cm_wait_for_fsm(void)
+{
+	while (readl(&clock_manager_base->stat) & CLKMGR_STAT_BUSY)
+		;
+}
+
+/*
+ * function to write the bypass register which requires a poll of the
+ * busy bit
+ */
+static inline void cm_write_bypass(uint32_t val)
+{
+	writel(val, &clock_manager_base->bypass);
+	cm_wait_for_fsm();
+}
+
+/* function to write the ctrl register which requires a poll of the busy bit */
+static inline void cm_write_ctrl(uint32_t val)
+{
+	writel(val, &clock_manager_base->ctrl);
+	cm_wait_for_fsm();
+}
+
+/* function to write a clock register that has phase information */
+static inline void cm_write_with_phase(uint32_t value,
+	uint32_t reg_address, uint32_t mask)
+{
+	/* poll until phase is zero */
+	while (readl(reg_address) & mask)
+		;
+
+	writel(value, reg_address);
+
+	while (readl(reg_address) & mask)
+		;
+}
+
+/*
+ * Setup clocks while making no assumptions about previous state of the clocks.
+ *
+ * Start by being paranoid and gate all sw managed clocks
+ * Put all plls in bypass
+ * Put all plls VCO registers back to reset value (bandgap power down).
+ * Put peripheral and main pll src to reset value to avoid glitch.
+ * Delay 5 us.
+ * Deassert bandgap power down and set numerator and denominator
+ * Start 7 us timer.
+ * set internal dividers
+ * Wait for 7 us timer.
+ * Enable plls
+ * Set external dividers while plls are locking
+ * Wait for pll lock
+ * Assert/deassert outreset all.
+ * Take all pll's out of bypass
+ * Clear safe mode
+ * set source main and peripheral clocks
+ * Ungate clocks
+ */
+
+void cm_basic_init(const cm_config_t *cfg)
+{
+	uint32_t start, timeout;
+
+	/* Start by being paranoid and gate all sw managed clocks */
+
+	/*
+	 * We need to disable nandclk
+	 * and then do another apb access before disabling
+	 * gatting off the rest of the periperal clocks.
+	 */
+	writel(~CLKMGR_PERPLLGRP_EN_NANDCLK_MASK &
+		readl(&clock_manager_base->per_pll_en),
+		&clock_manager_base->per_pll_en);
+
+	/* DO NOT GATE OFF DEBUG CLOCKS & BRIDGE CLOCKS */
+	writel(CLKMGR_MAINPLLGRP_EN_DBGTIMERCLK_MASK |
+		CLKMGR_MAINPLLGRP_EN_DBGTRACECLK_MASK |
+		CLKMGR_MAINPLLGRP_EN_DBGCLK_MASK |
+		CLKMGR_MAINPLLGRP_EN_DBGATCLK_MASK |
+		CLKMGR_MAINPLLGRP_EN_S2FUSER0CLK_MASK |
+		CLKMGR_MAINPLLGRP_EN_L4MPCLK_MASK,
+		&clock_manager_base->main_pll_en);
+
+	writel(0, &clock_manager_base->sdr_pll_en);
+
+	/* now we can gate off the rest of the peripheral clocks */
+	writel(0, &clock_manager_base->per_pll_en);
+
+	/* Put all plls in bypass */
+	cm_write_bypass(
+		CLKMGR_BYPASS_PERPLLSRC_SET(
+		CLKMGR_BYPASS_PERPLLSRC_SELECT_EOSC1) |
+		CLKMGR_BYPASS_SDRPLLSRC_SET(
+		CLKMGR_BYPASS_SDRPLLSRC_SELECT_EOSC1) |
+		CLKMGR_BYPASS_PERPLL_SET(CLKMGR_BYPASS_ENABLE) |
+		CLKMGR_BYPASS_SDRPLL_SET(CLKMGR_BYPASS_ENABLE) |
+		CLKMGR_BYPASS_MAINPLL_SET(CLKMGR_BYPASS_ENABLE));
+
+	/*
+	 * Put all plls VCO registers back to reset value.
+	 * Some code might have messed with them.
+	 */
+	writel(CLKMGR_MAINPLLGRP_VCO_RESET_VALUE,
+	       &clock_manager_base->main_pll_vco);
+	writel(CLKMGR_PERPLLGRP_VCO_RESET_VALUE,
+	       &clock_manager_base->per_pll_vco);
+	writel(CLKMGR_SDRPLLGRP_VCO_RESET_VALUE,
+	       &clock_manager_base->sdr_pll_vco);
+
+	/*
+	 * The clocks to the flash devices and the L4_MAIN clocks can
+	 * glitch when coming out of safe mode if their source values
+	 * are different from their reset value.  So the trick it to
+	 * put them back to their reset state, and change input
+	 * after exiting safe mode but before ungating the clocks.
+	 */
+	writel(CLKMGR_PERPLLGRP_SRC_RESET_VALUE,
+	       &clock_manager_base->per_pll_src);
+	writel(CLKMGR_MAINPLLGRP_L4SRC_RESET_VALUE,
+	       &clock_manager_base->main_pll_l4src);
+
+	/* read back for the required 5 us delay. */
+	readl(&clock_manager_base->main_pll_vco);
+	readl(&clock_manager_base->per_pll_vco);
+	readl(&clock_manager_base->sdr_pll_vco);
+
+
+	/*
+	 * We made sure bgpwr down was assert for 5 us. Now deassert BG PWR DN
+	 * with numerator and denominator.
+	 */
+	writel(cfg->main_vco_base | CLEAR_BGP_EN_PWRDN |
+		CLKMGR_MAINPLLGRP_VCO_REGEXTSEL_MASK,
+		&clock_manager_base->main_pll_vco);
+
+	writel(cfg->peri_vco_base | CLEAR_BGP_EN_PWRDN |
+		CLKMGR_PERPLLGRP_VCO_REGEXTSEL_MASK,
+		&clock_manager_base->per_pll_vco);
+
+	writel(CLKMGR_SDRPLLGRP_VCO_OUTRESET_SET(0) |
+		CLKMGR_SDRPLLGRP_VCO_OUTRESETALL_SET(0) |
+		cfg->sdram_vco_base | CLEAR_BGP_EN_PWRDN |
+		CLKMGR_SDRPLLGRP_VCO_REGEXTSEL_MASK,
+		&clock_manager_base->sdr_pll_vco);
+
+	/*
+	 * Time starts here
+	 * must wait 7 us from BGPWRDN_SET(0) to VCO_ENABLE_SET(1)
+	 */
+	reset_timer();
+	start = get_timer(0);
+	/* timeout in unit of us as CONFIG_SYS_HZ = 1000*1000 */
+	timeout = 7;
+
+	/* main mpu */
+	writel(cfg->mpuclk, &clock_manager_base->main_pll_mpuclk);
+
+	/* main main clock */
+	writel(cfg->mainclk, &clock_manager_base->main_pll_mainclk);
+
+	/* main for dbg */
+	writel(cfg->dbgatclk, &clock_manager_base->main_pll_dbgatclk);
+
+	/* main for cfgs2fuser0clk */
+	writel(cfg->cfg2fuser0clk,
+	       &clock_manager_base->main_pll_cfgs2fuser0clk);
+
+	/* Peri emac0 50 MHz default to RMII */
+	writel(cfg->emac0clk, &clock_manager_base->per_pll_emac0clk);
+
+	/* Peri emac1 50 MHz default to RMII */
+	writel(cfg->emac1clk, &clock_manager_base->per_pll_emac1clk);
+
+	/* Peri QSPI */
+	writel(cfg->mainqspiclk, &clock_manager_base->main_pll_mainqspiclk);
+
+	writel(cfg->perqspiclk, &clock_manager_base->per_pll_perqspiclk);
+
+	/* Peri pernandsdmmcclk */
+	writel(cfg->pernandsdmmcclk,
+	       &clock_manager_base->per_pll_pernandsdmmcclk);
+
+	/* Peri perbaseclk */
+	writel(cfg->perbaseclk, &clock_manager_base->per_pll_perbaseclk);
+
+	/* Peri s2fuser1clk */
+	writel(cfg->s2fuser1clk, &clock_manager_base->per_pll_s2fuser1clk);
+
+	/* 7 us must have elapsed before we can enable the VCO */
+	while (get_timer(start) < timeout)
+		;
+
+	/* Enable vco */
+	/* main pll vco */
+	writel(cfg->main_vco_base | VCO_EN_BASE,
+	       &clock_manager_base->main_pll_vco);
+
+	/* periferal pll */
+	writel(cfg->peri_vco_base | VCO_EN_BASE,
+	       &clock_manager_base->per_pll_vco);
+
+	/* sdram pll vco */
+	writel(CLKMGR_SDRPLLGRP_VCO_OUTRESET_SET(0) |
+		CLKMGR_SDRPLLGRP_VCO_OUTRESETALL_SET(0) |
+		cfg->sdram_vco_base | VCO_EN_BASE,
+		&clock_manager_base->sdr_pll_vco);
+
+	/* L3 MP and L3 SP */
+	writel(cfg->maindiv, &clock_manager_base->main_pll_maindiv);
+
+	writel(cfg->dbgdiv, &clock_manager_base->main_pll_dbgdiv);
+
+	writel(cfg->tracediv, &clock_manager_base->main_pll_tracediv);
+
+	/* L4 MP, L4 SP, can0, and can1 */
+	writel(cfg->perdiv, &clock_manager_base->per_pll_div);
+
+	writel(cfg->gpiodiv, &clock_manager_base->per_pll_gpiodiv);
+
+#define LOCKED_MASK \
+	(CLKMGR_INTER_SDRPLLLOCKED_MASK  | \
+	CLKMGR_INTER_PERPLLLOCKED_MASK  | \
+	CLKMGR_INTER_MAINPLLLOCKED_MASK)
+
+	cm_wait_for_lock(LOCKED_MASK);
+
+	/* write the sdram clock counters before toggling outreset all */
+	writel(cfg->ddrdqsclk & CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_MASK,
+	       &clock_manager_base->sdr_pll_ddrdqsclk);
+
+	writel(cfg->ddr2xdqsclk & CLKMGR_SDRPLLGRP_DDR2XDQSCLK_CNT_MASK,
+	       &clock_manager_base->sdr_pll_ddr2xdqsclk);
+
+	writel(cfg->ddrdqclk & CLKMGR_SDRPLLGRP_DDRDQCLK_CNT_MASK,
+	       &clock_manager_base->sdr_pll_ddrdqclk);
+
+	writel(cfg->s2fuser2clk & CLKMGR_SDRPLLGRP_S2FUSER2CLK_CNT_MASK,
+	       &clock_manager_base->sdr_pll_s2fuser2clk);
+
+	/*
+	 * after locking, but before taking out of bypass
+	 * assert/deassert outresetall
+	 */
+	uint32_t mainvco = readl(&clock_manager_base->main_pll_vco);
+
+	/* assert main outresetall */
+	writel(mainvco | CLKMGR_MAINPLLGRP_VCO_OUTRESETALL_MASK,
+	       &clock_manager_base->main_pll_vco);
+
+	uint32_t periphvco = readl(&clock_manager_base->per_pll_vco);
+
+	/* assert pheriph outresetall */
+	writel(periphvco | CLKMGR_PERPLLGRP_VCO_OUTRESETALL_MASK,
+	       &clock_manager_base->per_pll_vco);
+
+	/* assert sdram outresetall */
+	writel(cfg->sdram_vco_base | VCO_EN_BASE|
+		CLKMGR_SDRPLLGRP_VCO_OUTRESETALL_SET(1),
+		&clock_manager_base->sdr_pll_vco);
+
+	/* deassert main outresetall */
+	writel(mainvco & ~CLKMGR_MAINPLLGRP_VCO_OUTRESETALL_MASK,
+	       &clock_manager_base->main_pll_vco);
+
+	/* deassert pheriph outresetall */
+	writel(periphvco & ~CLKMGR_PERPLLGRP_VCO_OUTRESETALL_MASK,
+	       &clock_manager_base->per_pll_vco);
+
+	/* deassert sdram outresetall */
+	writel(CLKMGR_SDRPLLGRP_VCO_OUTRESETALL_SET(0) |
+		cfg->sdram_vco_base | VCO_EN_BASE,
+		&clock_manager_base->sdr_pll_vco);
+
+	/*
+	 * now that we've toggled outreset all, all the clocks
+	 * are aligned nicely; so we can change any phase.
+	 */
+	cm_write_with_phase(cfg->ddrdqsclk,
+			    (uint32_t)&clock_manager_base->sdr_pll_ddrdqsclk,
+			    CLKMGR_SDRPLLGRP_DDRDQSCLK_PHASE_MASK);
+
+	/* SDRAM DDR2XDQSCLK */
+	cm_write_with_phase(cfg->ddr2xdqsclk,
+			    (uint32_t)&clock_manager_base->sdr_pll_ddr2xdqsclk,
+			    CLKMGR_SDRPLLGRP_DDR2XDQSCLK_PHASE_MASK);
+
+	cm_write_with_phase(cfg->ddrdqclk,
+			    (uint32_t)&clock_manager_base->sdr_pll_ddrdqclk,
+			    CLKMGR_SDRPLLGRP_DDRDQCLK_PHASE_MASK);
+
+	cm_write_with_phase(cfg->s2fuser2clk,
+			    (uint32_t)&clock_manager_base->sdr_pll_s2fuser2clk,
+			    CLKMGR_SDRPLLGRP_S2FUSER2CLK_PHASE_MASK);
+
+	/* Take all three PLLs out of bypass when safe mode is cleared. */
+	cm_write_bypass(
+		CLKMGR_BYPASS_PERPLLSRC_SET(
+			CLKMGR_BYPASS_PERPLLSRC_SELECT_EOSC1) |
+		CLKMGR_BYPASS_SDRPLLSRC_SET(
+			CLKMGR_BYPASS_SDRPLLSRC_SELECT_EOSC1) |
+		CLKMGR_BYPASS_PERPLL_SET(CLKMGR_BYPASS_DISABLE) |
+		CLKMGR_BYPASS_SDRPLL_SET(CLKMGR_BYPASS_DISABLE) |
+		CLKMGR_BYPASS_MAINPLL_SET(CLKMGR_BYPASS_DISABLE));
+
+	/* clear safe mode */
+	cm_write_ctrl(readl(&clock_manager_base->ctrl) |
+			CLKMGR_CTRL_SAFEMODE_SET(CLKMGR_CTRL_SAFEMODE_MASK));
+
+	/*
+	 * now that safe mode is clear with clocks gated
+	 * it safe to change the source mux for the flashes the the L4_MAIN
+	 */
+	writel(cfg->persrc, &clock_manager_base->per_pll_src);
+	writel(cfg->l4src, &clock_manager_base->main_pll_l4src);
+
+	/* Now ungate non-hw-managed clocks */
+	writel(~0, &clock_manager_base->main_pll_en);
+	writel(~0, &clock_manager_base->per_pll_en);
+	writel(~0, &clock_manager_base->sdr_pll_en);
+}
diff --git a/arch/arm/cpu/armv7/socfpga/config.mk b/arch/arm/cpu/armv7/socfpga/config.mk
index d33ab7d62f..3d18491577 100644
--- a/arch/arm/cpu/armv7/socfpga/config.mk
+++ b/arch/arm/cpu/armv7/socfpga/config.mk
@@ -4,5 +4,5 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 ifndef CONFIG_SPL_BUILD
-ALL-y	+= $(obj)u-boot.img
+ALL-y	+= u-boot.img
 endif
diff --git a/arch/arm/cpu/armv7/socfpga/freeze_controller.c b/arch/arm/cpu/armv7/socfpga/freeze_controller.c
new file mode 100644
index 0000000000..b8c9bce1e0
--- /dev/null
+++ b/arch/arm/cpu/armv7/socfpga/freeze_controller.c
@@ -0,0 +1,215 @@
+/*
+ *  Copyright (C) 2013 Altera Corporation <www.altera.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/freeze_controller.h>
+#include <asm/arch/timer.h>
+#include <asm/errno.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static const struct socfpga_freeze_controller *freeze_controller_base =
+		(void *)(SOCFPGA_SYSMGR_ADDRESS + SYSMGR_FRZCTRL_ADDRESS);
+
+/*
+ * Default state from cold reset is FREEZE_ALL; the global
+ * flag is set to TRUE to indicate the IO banks are frozen
+ */
+static uint32_t frzctrl_channel_freeze[FREEZE_CHANNEL_NUM]
+	= { FREEZE_CTRL_FROZEN, FREEZE_CTRL_FROZEN,
+	FREEZE_CTRL_FROZEN, FREEZE_CTRL_FROZEN};
+
+/* Freeze HPS IOs */
+void sys_mgr_frzctrl_freeze_req(void)
+{
+	u32 ioctrl_reg_offset;
+	u32 reg_value;
+	u32 reg_cfg_mask;
+	u32 channel_id;
+
+	/* select software FSM */
+	writel(SYSMGR_FRZCTRL_SRC_VIO1_ENUM_SW,	&freeze_controller_base->src);
+
+	/* Freeze channel 0 to 2 */
+	for (channel_id = 0; channel_id <= 2; channel_id++) {
+		ioctrl_reg_offset = (u32)(
+			&freeze_controller_base->vioctrl +
+			(channel_id << SYSMGR_FRZCTRL_VIOCTRL_SHIFT));
+
+		/*
+		 * Assert active low enrnsl, plniotri
+		 * and niotri signals
+		 */
+		reg_cfg_mask =
+			SYSMGR_FRZCTRL_VIOCTRL_SLEW_MASK
+			| SYSMGR_FRZCTRL_VIOCTRL_WKPULLUP_MASK
+			| SYSMGR_FRZCTRL_VIOCTRL_TRISTATE_MASK;
+		clrbits_le32(ioctrl_reg_offset,	reg_cfg_mask);
+
+		/*
+		 * Note: Delay for 20ns at min
+		 * Assert active low bhniotri signal and de-assert
+		 * active high csrdone
+		 */
+		reg_cfg_mask
+			= SYSMGR_FRZCTRL_VIOCTRL_BUSHOLD_MASK
+			| SYSMGR_FRZCTRL_VIOCTRL_CFG_MASK;
+		clrbits_le32(ioctrl_reg_offset,	reg_cfg_mask);
+
+		/* Set global flag to indicate channel is frozen */
+		frzctrl_channel_freeze[channel_id] = FREEZE_CTRL_FROZEN;
+	}
+
+	/* Freeze channel 3 */
+	/*
+	 * Assert active low enrnsl, plniotri and
+	 * niotri signals
+	 */
+	reg_cfg_mask
+		= SYSMGR_FRZCTRL_HIOCTRL_SLEW_MASK
+		| SYSMGR_FRZCTRL_HIOCTRL_WKPULLUP_MASK
+		| SYSMGR_FRZCTRL_HIOCTRL_TRISTATE_MASK;
+	clrbits_le32(&freeze_controller_base->hioctrl, reg_cfg_mask);
+
+	/*
+	 * assert active low bhniotri & nfrzdrv signals,
+	 * de-assert active high csrdone and assert
+	 * active high frzreg and nfrzdrv signals
+	 */
+	reg_value = readl(&freeze_controller_base->hioctrl);
+	reg_cfg_mask
+		= SYSMGR_FRZCTRL_HIOCTRL_BUSHOLD_MASK
+		| SYSMGR_FRZCTRL_HIOCTRL_CFG_MASK;
+	reg_value
+		= (reg_value & ~reg_cfg_mask)
+		| SYSMGR_FRZCTRL_HIOCTRL_REGRST_MASK
+		| SYSMGR_FRZCTRL_HIOCTRL_OCTRST_MASK;
+	writel(reg_value, &freeze_controller_base->hioctrl);
+
+	/*
+	 * assert active high reinit signal and de-assert
+	 * active high pllbiasen signals
+	 */
+	reg_value = readl(&freeze_controller_base->hioctrl);
+	reg_value
+		= (reg_value &
+		~SYSMGR_FRZCTRL_HIOCTRL_OCT_CFGEN_CALSTART_MASK)
+		| SYSMGR_FRZCTRL_HIOCTRL_DLLRST_MASK;
+	writel(reg_value, &freeze_controller_base->hioctrl);
+
+	/* Set global flag to indicate channel is frozen */
+	frzctrl_channel_freeze[channel_id] = FREEZE_CTRL_FROZEN;
+}
+
+/* Unfreeze/Thaw HPS IOs */
+void sys_mgr_frzctrl_thaw_req(void)
+{
+	u32 ioctrl_reg_offset;
+	u32 reg_cfg_mask;
+	u32 reg_value;
+	u32 channel_id;
+
+	/* select software FSM */
+	writel(SYSMGR_FRZCTRL_SRC_VIO1_ENUM_SW,	&freeze_controller_base->src);
+
+	/* Thaw channel 0 to 2 */
+	for (channel_id = 0; channel_id <= 2; channel_id++) {
+		ioctrl_reg_offset
+			= (u32)(&freeze_controller_base->vioctrl
+				+ (channel_id << SYSMGR_FRZCTRL_VIOCTRL_SHIFT));
+
+		/*
+		 * Assert active low bhniotri signal and
+		 * de-assert active high csrdone
+		 */
+		reg_cfg_mask
+			= SYSMGR_FRZCTRL_VIOCTRL_BUSHOLD_MASK
+			| SYSMGR_FRZCTRL_VIOCTRL_CFG_MASK;
+		setbits_le32(ioctrl_reg_offset,	reg_cfg_mask);
+
+		/*
+		 * Note: Delay for 20ns at min
+		 * de-assert active low plniotri and niotri signals
+		 */
+		reg_cfg_mask
+			= SYSMGR_FRZCTRL_VIOCTRL_WKPULLUP_MASK
+			| SYSMGR_FRZCTRL_VIOCTRL_TRISTATE_MASK;
+		setbits_le32(ioctrl_reg_offset,	reg_cfg_mask);
+
+		/*
+		 * Note: Delay for 20ns at min
+		 * de-assert active low enrnsl signal
+		 */
+		setbits_le32(ioctrl_reg_offset,
+			SYSMGR_FRZCTRL_VIOCTRL_SLEW_MASK);
+
+		/* Set global flag to indicate channel is thawed */
+		frzctrl_channel_freeze[channel_id] = FREEZE_CTRL_THAWED;
+	}
+
+	/* Thaw channel 3 */
+	/* de-assert active high reinit signal */
+	clrbits_le32(&freeze_controller_base->hioctrl,
+		SYSMGR_FRZCTRL_HIOCTRL_DLLRST_MASK);
+
+	/*
+	 * Note: Delay for 40ns at min
+	 * assert active high pllbiasen signals
+	 */
+	setbits_le32(&freeze_controller_base->hioctrl,
+		SYSMGR_FRZCTRL_HIOCTRL_OCT_CFGEN_CALSTART_MASK);
+
+	/*
+	 * Delay 1000 intosc. intosc is based on eosc1
+	 * Use worst case which is fatest eosc1=50MHz, delay required
+	 * is 1/50MHz * 1000 = 20us
+	 */
+	udelay(20);
+
+	/*
+	 * de-assert active low bhniotri signals,
+	 * assert active high csrdone and nfrzdrv signal
+	 */
+	reg_value = readl(&freeze_controller_base->hioctrl);
+	reg_value = (reg_value
+		| SYSMGR_FRZCTRL_HIOCTRL_BUSHOLD_MASK
+		| SYSMGR_FRZCTRL_HIOCTRL_CFG_MASK)
+		& ~SYSMGR_FRZCTRL_HIOCTRL_OCTRST_MASK;
+	writel(reg_value, &freeze_controller_base->hioctrl);
+
+	/*
+	 * Delay 33 intosc
+	 * Use worst case which is fatest eosc1=50MHz, delay required
+	 * is 1/50MHz * 33 = 660ns ~= 1us
+	 */
+	udelay(1);
+
+	/* de-assert active low plniotri and niotri signals */
+	reg_cfg_mask
+		= SYSMGR_FRZCTRL_HIOCTRL_WKPULLUP_MASK
+		| SYSMGR_FRZCTRL_HIOCTRL_TRISTATE_MASK;
+
+	setbits_le32(&freeze_controller_base->hioctrl, reg_cfg_mask);
+
+	/*
+	 * Note: Delay for 40ns at min
+	 * de-assert active high frzreg signal
+	 */
+	clrbits_le32(&freeze_controller_base->hioctrl,
+		SYSMGR_FRZCTRL_HIOCTRL_REGRST_MASK);
+
+	/*
+	 * Note: Delay for 40ns at min
+	 * de-assert active low enrnsl signal
+	 */
+	setbits_le32(&freeze_controller_base->hioctrl,
+		SYSMGR_FRZCTRL_HIOCTRL_SLEW_MASK);
+
+	/* Set global flag to indicate channel is thawed */
+	frzctrl_channel_freeze[channel_id] = FREEZE_CTRL_THAWED;
+}
diff --git a/arch/arm/cpu/armv7/socfpga/spl.c b/arch/arm/cpu/armv7/socfpga/spl.c
index 74bceab183..2ae88bbd04 100644
--- a/arch/arm/cpu/armv7/socfpga/spl.c
+++ b/arch/arm/cpu/armv7/socfpga/spl.c
@@ -13,6 +13,7 @@
 #include <asm/arch/reset_manager.h>
 #include <spl.h>
 #include <asm/arch/system_manager.h>
+#include <asm/arch/freeze_controller.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -27,6 +28,99 @@ u32 spl_boot_device(void)
 void spl_board_init(void)
 {
 #ifndef CONFIG_SOCFPGA_VIRTUAL_TARGET
+	cm_config_t cm_default_cfg = {
+		/* main group */
+		MAIN_VCO_BASE,
+		CLKMGR_MAINPLLGRP_MPUCLK_CNT_SET(
+			CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT),
+		CLKMGR_MAINPLLGRP_MAINCLK_CNT_SET(
+			CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT),
+		CLKMGR_MAINPLLGRP_DBGATCLK_CNT_SET(
+			CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT),
+		CLKMGR_MAINPLLGRP_MAINQSPICLK_CNT_SET(
+			CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT),
+		CLKMGR_PERPLLGRP_PERNANDSDMMCCLK_CNT_SET(
+			CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT),
+		CLKMGR_MAINPLLGRP_CFGS2FUSER0CLK_CNT_SET(
+			CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT),
+		CLKMGR_MAINPLLGRP_MAINDIV_L3MPCLK_SET(
+			CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK) |
+		CLKMGR_MAINPLLGRP_MAINDIV_L3SPCLK_SET(
+			CONFIG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK) |
+		CLKMGR_MAINPLLGRP_MAINDIV_L4MPCLK_SET(
+			CONFIG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK) |
+		CLKMGR_MAINPLLGRP_MAINDIV_L4SPCLK_SET(
+			CONFIG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK),
+		CLKMGR_MAINPLLGRP_DBGDIV_DBGATCLK_SET(
+			CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK) |
+		CLKMGR_MAINPLLGRP_DBGDIV_DBGCLK_SET(
+			CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGCLK),
+		CLKMGR_MAINPLLGRP_TRACEDIV_TRACECLK_SET(
+			CONFIG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK),
+		CLKMGR_MAINPLLGRP_L4SRC_L4MP_SET(
+			CONFIG_HPS_MAINPLLGRP_L4SRC_L4MP) |
+		CLKMGR_MAINPLLGRP_L4SRC_L4SP_SET(
+			CONFIG_HPS_MAINPLLGRP_L4SRC_L4SP),
+
+		/* peripheral group */
+		PERI_VCO_BASE,
+		CLKMGR_PERPLLGRP_EMAC0CLK_CNT_SET(
+			CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT),
+		CLKMGR_PERPLLGRP_EMAC1CLK_CNT_SET(
+			CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT),
+		CLKMGR_PERPLLGRP_PERQSPICLK_CNT_SET(
+			CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT),
+		CLKMGR_PERPLLGRP_PERNANDSDMMCCLK_CNT_SET(
+			CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT),
+		CLKMGR_PERPLLGRP_PERBASECLK_CNT_SET(
+			CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT),
+		CLKMGR_PERPLLGRP_S2FUSER1CLK_CNT_SET(
+			CONFIG_HPS_PERPLLGRP_S2FUSER1CLK_CNT),
+		CLKMGR_PERPLLGRP_DIV_USBCLK_SET(
+			CONFIG_HPS_PERPLLGRP_DIV_USBCLK) |
+		CLKMGR_PERPLLGRP_DIV_SPIMCLK_SET(
+			CONFIG_HPS_PERPLLGRP_DIV_SPIMCLK) |
+		CLKMGR_PERPLLGRP_DIV_CAN0CLK_SET(
+			CONFIG_HPS_PERPLLGRP_DIV_CAN0CLK) |
+		CLKMGR_PERPLLGRP_DIV_CAN1CLK_SET(
+			CONFIG_HPS_PERPLLGRP_DIV_CAN1CLK),
+		CLKMGR_PERPLLGRP_GPIODIV_GPIODBCLK_SET(
+			CONFIG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK),
+		CLKMGR_PERPLLGRP_SRC_QSPI_SET(
+			CONFIG_HPS_PERPLLGRP_SRC_QSPI) |
+		CLKMGR_PERPLLGRP_SRC_NAND_SET(
+			CONFIG_HPS_PERPLLGRP_SRC_NAND) |
+		CLKMGR_PERPLLGRP_SRC_SDMMC_SET(
+			CONFIG_HPS_PERPLLGRP_SRC_SDMMC),
+
+		/* sdram pll group */
+		SDR_VCO_BASE,
+		CLKMGR_SDRPLLGRP_DDRDQSCLK_PHASE_SET(
+			CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE) |
+		CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_SET(
+			CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_CNT),
+		CLKMGR_SDRPLLGRP_DDR2XDQSCLK_PHASE_SET(
+			CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE) |
+		CLKMGR_SDRPLLGRP_DDR2XDQSCLK_CNT_SET(
+			CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT),
+		CLKMGR_SDRPLLGRP_DDRDQCLK_PHASE_SET(
+			CONFIG_HPS_SDRPLLGRP_DDRDQCLK_PHASE) |
+		CLKMGR_SDRPLLGRP_DDRDQCLK_CNT_SET(
+			CONFIG_HPS_SDRPLLGRP_DDRDQCLK_CNT),
+		CLKMGR_SDRPLLGRP_S2FUSER2CLK_PHASE_SET(
+			CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE) |
+		CLKMGR_SDRPLLGRP_S2FUSER2CLK_CNT_SET(
+			CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT),
+	};
+
+	debug("Freezing all I/O banks\n");
+	/* freeze all IO banks */
+	sys_mgr_frzctrl_freeze_req();
+
+	debug("Reconfigure Clock Manager\n");
+	/* reconfigure the PLLs */
+	cm_basic_init(&cm_default_cfg);
+
 	/* configure the pin muxing through system manager */
 	sysmgr_pinmux_init();
 #endif /* CONFIG_SOCFPGA_VIRTUAL_TARGET */
@@ -34,6 +128,10 @@ void spl_board_init(void)
 	/* de-assert reset for peripherals and bridges based on handoff */
 	reset_deassert_peripherals_handoff();
 
+	debug("Unfreezing/Thaw all I/O banks\n");
+	/* unfreeze / thaw all IO banks */
+	sys_mgr_frzctrl_thaw_req();
+
 	/* enable console uart printing */
 	preloader_console_init();
 }
diff --git a/arch/arm/cpu/armv7/socfpga/timer.c b/arch/arm/cpu/armv7/socfpga/timer.c
index 09f6f14200..58fc789e64 100644
--- a/arch/arm/cpu/armv7/socfpga/timer.c
+++ b/arch/arm/cpu/armv7/socfpga/timer.c
@@ -8,8 +8,6 @@
 #include <asm/io.h>
 #include <asm/arch/timer.h>
 
-DECLARE_GLOBAL_DATA_PTR;
-
 static const struct socfpga_timer *timer_base = (void *)CONFIG_SYS_TIMERBASE;
 
 /*
@@ -22,73 +20,3 @@ int timer_init(void)
 	writel(readl(&timer_base->ctrl) | 0x3, &timer_base->ctrl);
 	return 0;
 }
-
-static u32 read_timer(void)
-{
-	return readl(&timer_base->curr_val);
-}
-
-/*
- * Delay x useconds
- */
-void __udelay(unsigned long usec)
-{
-	unsigned long now, last;
-	/*
-	 * get the tmo value based on timer clock speed
-	 * tmo = delay required / period of timer clock
-	 */
-	long tmo = usec * CONFIG_TIMER_CLOCK_KHZ / 1000;
-
-	last = read_timer();
-	while (tmo > 0) {
-		now = read_timer();
-		if (last >= now)
-			/* normal mode (non roll) */
-			tmo -= last - now;
-		else
-			/* we have overflow of the count down timer */
-			tmo -= TIMER_LOAD_VAL - last + now;
-		last = now;
-	}
-}
-
-/*
- * Get the timer value
- */
-ulong get_timer(ulong base)
-{
-	return get_timer_masked() - base;
-}
-
-/*
- * Timer : get the time difference
- * Unit of tick is based on the CONFIG_SYS_HZ
- */
-ulong get_timer_masked(void)
-{
-	/* current tick value */
-	ulong now = read_timer() / (CONFIG_TIMER_CLOCK_KHZ/CONFIG_SYS_HZ);
-	if (gd->arch.lastinc >= now) {
-		/* normal mode (non roll) */
-		/* move stamp forward with absolute diff ticks */
-		gd->arch.tbl += gd->arch.lastinc - now;
-	} else {
-		/* we have overflow of the count down timer */
-		gd->arch.tbl += TIMER_LOAD_VAL - gd->arch.lastinc + now;
-	}
-	gd->arch.lastinc = now;
-	return gd->arch.tbl;
-}
-
-/*
- * Reset the timer
- */
-void reset_timer(void)
-{
-	/* capture current decrementer value time */
-	gd->arch.lastinc = read_timer() /
-				(CONFIG_TIMER_CLOCK_KHZ / CONFIG_SYS_HZ);
-	/* start "advancing" time stamp from 0 */
-	gd->arch.tbl = 0;
-}
diff --git a/arch/arm/cpu/armv7/socfpga/u-boot-spl.lds b/arch/arm/cpu/armv7/socfpga/u-boot-spl.lds
index a7c9c9d281..4282beb395 100644
--- a/arch/arm/cpu/armv7/socfpga/u-boot-spl.lds
+++ b/arch/arm/cpu/armv7/socfpga/u-boot-spl.lds
@@ -28,7 +28,11 @@ SECTIONS
 
 	. = ALIGN(4);
 	__image_copy_end = .;
-	_end = .;
+
+	.end :
+	{
+		*(.__end)
+	}
 
 	.bss : {
 		. = ALIGN(4);
diff --git a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S
index 6c9b11a452..27be451a89 100644
--- a/arch/arm/cpu/armv7/start.S
+++ b/arch/arm/cpu/armv7/start.S
@@ -38,12 +38,19 @@ _irq:			.word _irq
 _fiq:			.word _fiq
 _pad:			.word 0x12345678 /* now 16*4=64 */
 #else
+.globl _undefined_instruction
 _undefined_instruction: .word undefined_instruction
+.globl _software_interrupt
 _software_interrupt:	.word software_interrupt
+.globl _prefetch_abort
 _prefetch_abort:	.word prefetch_abort
+.globl _data_abort
 _data_abort:		.word data_abort
+.globl _not_used
 _not_used:		.word not_used
+.globl _irq
 _irq:			.word irq
+.globl _fiq
 _fiq:			.word fiq
 _pad:			.word 0x12345678 /* now 16*4=64 */
 #endif	/* CONFIG_SPL_BUILD */
@@ -63,29 +70,6 @@ _end_vect:
  *
  *************************************************************************/
 
-.globl _TEXT_BASE
-_TEXT_BASE:
-#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_TEXT_BASE)
-	.word	CONFIG_SPL_TEXT_BASE
-#else
-	.word	CONFIG_SYS_TEXT_BASE
-#endif
-
-/*
- * These are defined in the board-specific linker script.
- */
-.globl _bss_start_ofs
-_bss_start_ofs:
-	.word __bss_start - _start
-
-.globl _bss_end_ofs
-_bss_end_ofs:
-	.word __bss_end - _start
-
-.globl _end_ofs
-_end_ofs:
-	.word _end - _start
-
 #ifdef CONFIG_USE_IRQ
 /* IRQ stack memory (calculated at run-time) */
 .globl IRQ_STACK_START
@@ -221,7 +205,7 @@ ENTRY(cpu_init_cp15)
 	mcr	p15, 0, r0, c1, c0, 0	@ write system control register
 #endif
 
-#ifdef CONFIG_ARM_ERRATA_742230
+#if (defined(CONFIG_ARM_ERRATA_742230) || defined(CONFIG_ARM_ERRATA_794072))
 	mrc	p15, 0, r0, c15, c0, 1	@ read diagnostic register
 	orr	r0, r0, #1 << 4		@ set bit #4
 	mcr	p15, 0, r0, c15, c0, 1	@ write diagnostic register
@@ -238,6 +222,11 @@ ENTRY(cpu_init_cp15)
 	orr	r0, r0, #1 << 11	@ set bit #11
 	mcr	p15, 0, r0, c15, c0, 1	@ write diagnostic register
 #endif
+#ifdef CONFIG_ARM_ERRATA_761320
+	mrc	p15, 0, r0, c15, c0, 1	@ read diagnostic register
+	orr	r0, r0, #1 << 21	@ set bit #21
+	mcr	p15, 0, r0, c15, c0, 1	@ write diagnostic register
+#endif
 
 	mov	pc, lr			@ back to my caller
 ENDPROC(cpu_init_cp15)
diff --git a/arch/arm/cpu/armv7/tegra-common/Makefile b/arch/arm/cpu/armv7/tegra-common/Makefile
index d97542d89d..463c260f18 100644
--- a/arch/arm/cpu/armv7/tegra-common/Makefile
+++ b/arch/arm/cpu/armv7/tegra-common/Makefile
@@ -7,26 +7,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	=  $(obj)libtegra-common.o
-
-COBJS-$(CONFIG_CMD_ENTERRCM) += cmd_enterrcm.o
-
-COBJS	:= $(COBJS-y)
-SRCS	:= $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-
-all:	 $(obj).depend $(LIB)
-
-$(LIB):	$(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-$(CONFIG_CMD_ENTERRCM) += cmd_enterrcm.o
diff --git a/arch/arm/cpu/armv7/tegra114/Makefile b/arch/arm/cpu/armv7/tegra114/Makefile
index eb98c8ea17..77e231959b 100644
--- a/arch/arm/cpu/armv7/tegra114/Makefile
+++ b/arch/arm/cpu/armv7/tegra114/Makefile
@@ -17,24 +17,5 @@
 # along with this program.  If not, see <http://www.gnu.org/licenses/>.
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(SOC).o
-
-COBJS	:= $(COBJS-y)
-SRCS	:= $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-
-all:	$(obj).depend $(LIB)
-
-$(LIB):	$(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+# necessary to create built-in.o
+obj- := __dummy__.o
diff --git a/arch/arm/cpu/armv7/tegra124/Makefile b/arch/arm/cpu/armv7/tegra124/Makefile
new file mode 100644
index 0000000000..9478d447db
--- /dev/null
+++ b/arch/arm/cpu/armv7/tegra124/Makefile
@@ -0,0 +1,9 @@
+#
+# (C) Copyright 2013-2014
+# NVIDIA Corporation <www.nvidia.com>
+#
+# SPDX-License-Identifier:     GPL-2.0+
+#
+
+# necessary to create built-in.o
+obj- := __dummy__.o
diff --git a/arch/arm/cpu/armv7/tegra20/Makefile b/arch/arm/cpu/armv7/tegra20/Makefile
index 4ee8e5baf3..9b4295c72d 100644
--- a/arch/arm/cpu/armv7/tegra20/Makefile
+++ b/arch/arm/cpu/armv7/tegra20/Makefile
@@ -7,27 +7,5 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	=  $(obj)lib$(SOC).o
-
-COBJS-$(CONFIG_PWM_TEGRA) += pwm.o
-COBJS-$(CONFIG_VIDEO_TEGRA) += display.o
-
-COBJS	:= $(COBJS-y)
-SRCS	:= $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-
-all:	 $(obj).depend $(LIB)
-
-$(LIB):	$(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-$(CONFIG_PWM_TEGRA) += pwm.o
+obj-$(CONFIG_VIDEO_TEGRA) += display.o
diff --git a/arch/arm/cpu/armv7/tegra30/Makefile b/arch/arm/cpu/armv7/tegra30/Makefile
index 04adb52994..413eba102a 100644
--- a/arch/arm/cpu/armv7/tegra30/Makefile
+++ b/arch/arm/cpu/armv7/tegra30/Makefile
@@ -17,24 +17,5 @@
 # along with this program.  If not, see <http://www.gnu.org/licenses/>.
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(SOC).o
-
-COBJS	:= $(COBJS-y)
-SRCS	:= $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-
-all:	$(obj).depend $(LIB)
-
-$(LIB):	$(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+# necessary to create built-in.o
+obj- := __dummy__.o
diff --git a/arch/arm/cpu/armv7/u8500/Makefile b/arch/arm/cpu/armv7/u8500/Makefile
index 3d7a592008..fad9d4ae3a 100644
--- a/arch/arm/cpu/armv7/u8500/Makefile
+++ b/arch/arm/cpu/armv7/u8500/Makefile
@@ -5,26 +5,5 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(SOC).o
-
-COBJS	= timer.o clock.o prcmu.o cpu.o
-SOBJS	= lowlevel.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS) $(SOBJS))
-
-all:	$(obj).depend $(LIB)
-
-$(LIB):	$(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	:= timer.o clock.o prcmu.o cpu.o
+obj-y	+= lowlevel.o
diff --git a/arch/arm/cpu/armv7/vf610/Makefile b/arch/arm/cpu/armv7/vf610/Makefile
index 7d3c454d59..68cb756d67 100644
--- a/arch/arm/cpu/armv7/vf610/Makefile
+++ b/arch/arm/cpu/armv7/vf610/Makefile
@@ -4,26 +4,5 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(SOC).o
-
-COBJS	+= generic.o
-COBJS	+= timer.o
-
-SRCS	:= $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-
-all:	$(obj).depend $(LIB)
-
-$(LIB):	$(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	+= generic.o
+obj-y	+= timer.o
diff --git a/arch/arm/cpu/armv7/zynq/Makefile b/arch/arm/cpu/armv7/zynq/Makefile
index de6b08157e..3363a3c71b 100644
--- a/arch/arm/cpu/armv7/zynq/Makefile
+++ b/arch/arm/cpu/armv7/zynq/Makefile
@@ -8,30 +8,9 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(SOC).o
-
-COBJS-y	:= timer.o
-COBJS-y	+= cpu.o
-COBJS-y	+= ddrc.o
-COBJS-y	+= slcr.o
-
-COBJS	:= $(COBJS-y)
-
-SRCS	:= $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-
-all:	$(obj).depend $(LIB)
-
-$(LIB): $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	:= timer.o
+obj-y	+= cpu.o
+obj-y	+= ddrc.o
+obj-y	+= slcr.o
+obj-y	+= clk.o
+obj-$(CONFIG_SPL_BUILD)	+= spl.o
diff --git a/arch/arm/cpu/armv7/zynq/clk.c b/arch/arm/cpu/armv7/zynq/clk.c
new file mode 100644
index 0000000000..d2885dc2b9
--- /dev/null
+++ b/arch/arm/cpu/armv7/zynq/clk.c
@@ -0,0 +1,664 @@
+/*
+ * Copyright (C) 2013 Soren Brinkmann <soren.brinkmann@xilinx.com>
+ * Copyright (C) 2013 Xilinx, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+#include <common.h>
+#include <errno.h>
+#include <clk.h>
+#include <asm/io.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/clk.h>
+
+/* Board oscillator frequency */
+#ifndef CONFIG_ZYNQ_PS_CLK_FREQ
+# define CONFIG_ZYNQ_PS_CLK_FREQ	33333333UL
+#endif
+
+/* Register bitfield defines */
+#define PLLCTRL_FBDIV_MASK	0x7f000
+#define PLLCTRL_FBDIV_SHIFT	12
+#define PLLCTRL_BPFORCE_MASK	(1 << 4)
+#define PLLCTRL_PWRDWN_MASK	2
+#define PLLCTRL_PWRDWN_SHIFT	1
+#define PLLCTRL_RESET_MASK	1
+#define PLLCTRL_RESET_SHIFT	0
+
+#define ZYNQ_CLK_MAXDIV		0x3f
+#define CLK_CTRL_DIV1_SHIFT	20
+#define CLK_CTRL_DIV1_MASK	(ZYNQ_CLK_MAXDIV << CLK_CTRL_DIV1_SHIFT)
+#define CLK_CTRL_DIV0_SHIFT	8
+#define CLK_CTRL_DIV0_MASK	(ZYNQ_CLK_MAXDIV << CLK_CTRL_DIV0_SHIFT)
+#define CLK_CTRL_SRCSEL_SHIFT	4
+#define CLK_CTRL_SRCSEL_MASK	(0x3 << CLK_CTRL_SRCSEL_SHIFT)
+
+#define CLK_CTRL_DIV2X_SHIFT	26
+#define CLK_CTRL_DIV2X_MASK	(ZYNQ_CLK_MAXDIV << CLK_CTRL_DIV2X_SHIFT)
+#define CLK_CTRL_DIV3X_SHIFT	20
+#define CLK_CTRL_DIV3X_MASK	(ZYNQ_CLK_MAXDIV << CLK_CTRL_DIV3X_SHIFT)
+
+#define ZYNQ_CLKMUX_SEL_0	0
+#define ZYNQ_CLKMUX_SEL_1	1
+#define ZYNQ_CLKMUX_SEL_2	2
+#define ZYNQ_CLKMUX_SEL_3	3
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct clk;
+
+/**
+ * struct clk_ops:
+ * @set_rate:	Function pointer to set_rate() implementation
+ * @get_rate:	Function pointer to get_rate() implementation
+ */
+struct clk_ops {
+	int (*set_rate)(struct clk *clk, unsigned long rate);
+	unsigned long (*get_rate)(struct clk *clk);
+};
+
+/**
+ * struct clk:
+ * @name:	Clock name
+ * @frequency:	Currenct frequency
+ * @parent:	Parent clock
+ * @flags:	Clock flags
+ * @reg:	Clock control register
+ * @ops:	Clock operations
+ */
+struct clk {
+	char		*name;
+	unsigned long	frequency;
+	enum zynq_clk	parent;
+	unsigned int	flags;
+	u32		*reg;
+	struct clk_ops	ops;
+};
+#define ZYNQ_CLK_FLAGS_HAS_2_DIVS	1
+
+static struct clk clks[clk_max];
+
+/**
+ * __zynq_clk_cpu_get_parent() - Decode clock multiplexer
+ * @srcsel:	Mux select value
+ * Returns the clock identifier associated with the selected mux input.
+ */
+static int __zynq_clk_cpu_get_parent(unsigned int srcsel)
+{
+	unsigned int ret;
+
+	switch (srcsel) {
+	case ZYNQ_CLKMUX_SEL_0:
+	case ZYNQ_CLKMUX_SEL_1:
+		ret = armpll_clk;
+		break;
+	case ZYNQ_CLKMUX_SEL_2:
+		ret = ddrpll_clk;
+		break;
+	case ZYNQ_CLKMUX_SEL_3:
+		ret = iopll_clk;
+		break;
+	default:
+		ret = armpll_clk;
+		break;
+	}
+
+	return ret;
+}
+
+/**
+ * ddr2x_get_rate() - Get clock rate of DDR2x clock
+ * @clk:	Clock handle
+ * Returns the current clock rate of @clk.
+ */
+static unsigned long ddr2x_get_rate(struct clk *clk)
+{
+	u32 clk_ctrl = readl(clk->reg);
+	u32 div = (clk_ctrl & CLK_CTRL_DIV2X_MASK) >> CLK_CTRL_DIV2X_SHIFT;
+
+	return DIV_ROUND_CLOSEST(zynq_clk_get_rate(clk->parent), div);
+}
+
+/**
+ * ddr3x_get_rate() - Get clock rate of DDR3x clock
+ * @clk:	Clock handle
+ * Returns the current clock rate of @clk.
+ */
+static unsigned long ddr3x_get_rate(struct clk *clk)
+{
+	u32 clk_ctrl = readl(clk->reg);
+	u32 div = (clk_ctrl & CLK_CTRL_DIV3X_MASK) >> CLK_CTRL_DIV3X_SHIFT;
+
+	return DIV_ROUND_CLOSEST(zynq_clk_get_rate(clk->parent), div);
+}
+
+static void init_ddr_clocks(void)
+{
+	u32 div0, div1;
+	unsigned long prate = zynq_clk_get_rate(ddrpll_clk);
+	u32 clk_ctrl = readl(&slcr_base->ddr_clk_ctrl);
+
+	/* DDR2x */
+	clks[ddr2x_clk].reg = &slcr_base->ddr_clk_ctrl;
+	clks[ddr2x_clk].parent = ddrpll_clk;
+	clks[ddr2x_clk].name = "ddr_2x";
+	clks[ddr2x_clk].frequency = ddr2x_get_rate(&clks[ddr2x_clk]);
+	clks[ddr2x_clk].ops.get_rate = ddr2x_get_rate;
+
+	/* DDR3x */
+	clks[ddr3x_clk].reg = &slcr_base->ddr_clk_ctrl;
+	clks[ddr3x_clk].parent = ddrpll_clk;
+	clks[ddr3x_clk].name = "ddr_3x";
+	clks[ddr3x_clk].frequency = ddr3x_get_rate(&clks[ddr3x_clk]);
+	clks[ddr3x_clk].ops.get_rate = ddr3x_get_rate;
+
+	/* DCI */
+	clk_ctrl = readl(&slcr_base->dci_clk_ctrl);
+	div0 = (clk_ctrl & CLK_CTRL_DIV0_MASK) >> CLK_CTRL_DIV0_SHIFT;
+	div1 = (clk_ctrl & CLK_CTRL_DIV1_MASK) >> CLK_CTRL_DIV1_SHIFT;
+	clks[dci_clk].reg = &slcr_base->dci_clk_ctrl;
+	clks[dci_clk].parent = ddrpll_clk;
+	clks[dci_clk].frequency = DIV_ROUND_CLOSEST(
+			DIV_ROUND_CLOSEST(prate, div0), div1);
+	clks[dci_clk].name = "dci";
+
+	gd->bd->bi_ddr_freq = clks[ddr3x_clk].frequency / 1000000;
+}
+
+static void init_cpu_clocks(void)
+{
+	int clk_621;
+	u32 reg, div, srcsel;
+	enum zynq_clk parent;
+
+	reg = readl(&slcr_base->arm_clk_ctrl);
+	clk_621 = readl(&slcr_base->clk_621_true) & 1;
+	div = (reg & CLK_CTRL_DIV0_MASK) >> CLK_CTRL_DIV0_SHIFT;
+	srcsel = (reg & CLK_CTRL_SRCSEL_MASK) >> CLK_CTRL_SRCSEL_SHIFT;
+	parent = __zynq_clk_cpu_get_parent(srcsel);
+
+	/* cpu clocks */
+	clks[cpu_6or4x_clk].reg = &slcr_base->arm_clk_ctrl;
+	clks[cpu_6or4x_clk].parent = parent;
+	clks[cpu_6or4x_clk].frequency = DIV_ROUND_CLOSEST(
+			zynq_clk_get_rate(parent), div);
+	clks[cpu_6or4x_clk].name = "cpu_6or4x";
+
+	clks[cpu_3or2x_clk].reg = &slcr_base->arm_clk_ctrl;
+	clks[cpu_3or2x_clk].parent = cpu_6or4x_clk;
+	clks[cpu_3or2x_clk].frequency = zynq_clk_get_rate(cpu_6or4x_clk) / 2;
+	clks[cpu_3or2x_clk].name = "cpu_3or2x";
+
+	clks[cpu_2x_clk].reg = &slcr_base->arm_clk_ctrl;
+	clks[cpu_2x_clk].parent = cpu_6or4x_clk;
+	clks[cpu_2x_clk].frequency = zynq_clk_get_rate(cpu_6or4x_clk) /
+			(2 + clk_621);
+	clks[cpu_2x_clk].name = "cpu_2x";
+
+	clks[cpu_1x_clk].reg = &slcr_base->arm_clk_ctrl;
+	clks[cpu_1x_clk].parent = cpu_6or4x_clk;
+	clks[cpu_1x_clk].frequency = zynq_clk_get_rate(cpu_6or4x_clk) /
+			(4 + 2 * clk_621);
+	clks[cpu_1x_clk].name = "cpu_1x";
+}
+
+/**
+ * periph_calc_two_divs() - Calculate clock dividers
+ * @cur_rate:	Current clock rate
+ * @tgt_rate:	Target clock rate
+ * @prate:	Parent clock rate
+ * @div0:	First divider (output)
+ * @div1:	Second divider (output)
+ * Returns the actual clock rate possible.
+ *
+ * Calculates clock dividers for clocks with two 6-bit dividers.
+ */
+static unsigned long periph_calc_two_divs(unsigned long cur_rate,
+		unsigned long tgt_rate, unsigned long prate, u32 *div0,
+		u32 *div1)
+{
+	long err, best_err = (long)(~0UL >> 1);
+	unsigned long rate, best_rate = 0;
+	u32 d0, d1;
+
+	for (d0 = 1; d0 <= ZYNQ_CLK_MAXDIV; d0++) {
+		for (d1 = 1; d1 <= ZYNQ_CLK_MAXDIV >> 1; d1++) {
+			rate = DIV_ROUND_CLOSEST(DIV_ROUND_CLOSEST(prate, d0),
+					d1);
+			err = abs(rate - tgt_rate);
+
+			if (err < best_err) {
+				*div0 = d0;
+				*div1 = d1;
+				best_err = err;
+				best_rate = rate;
+			}
+		}
+	}
+
+	return best_rate;
+}
+
+/**
+ * zynq_clk_periph_set_rate() - Set clock rate
+ * @clk:	Handle of the peripheral clock
+ * @rate:	New clock rate
+ * Sets the clock frequency of @clk to @rate. Returns zero on success.
+ */
+static int zynq_clk_periph_set_rate(struct clk *clk,
+		unsigned long rate)
+{
+	u32 ctrl, div0 = 0, div1 = 0;
+	unsigned long prate, new_rate, cur_rate = clk->frequency;
+
+	ctrl = readl(clk->reg);
+	prate = zynq_clk_get_rate(clk->parent);
+	ctrl &= ~CLK_CTRL_DIV0_MASK;
+
+	if (clk->flags & ZYNQ_CLK_FLAGS_HAS_2_DIVS) {
+		ctrl &= ~CLK_CTRL_DIV1_MASK;
+		new_rate = periph_calc_two_divs(cur_rate, rate, prate, &div0,
+				&div1);
+		ctrl |= div1 << CLK_CTRL_DIV1_SHIFT;
+	} else {
+		div0 = DIV_ROUND_CLOSEST(prate, rate);
+		div0 &= ZYNQ_CLK_MAXDIV;
+		new_rate = DIV_ROUND_CLOSEST(rate, div0);
+	}
+
+	/* write new divs to hardware */
+	ctrl |= div0 << CLK_CTRL_DIV0_SHIFT;
+	writel(ctrl, clk->reg);
+
+	/* update frequency in clk framework */
+	clk->frequency = new_rate;
+
+	return 0;
+}
+
+/**
+ * zynq_clk_periph_get_rate() - Get clock rate
+ * @clk:	Handle of the peripheral clock
+ * Returns the current clock rate of @clk.
+ */
+static unsigned long zynq_clk_periph_get_rate(struct clk *clk)
+{
+	u32 clk_ctrl = readl(clk->reg);
+	u32 div0 = (clk_ctrl & CLK_CTRL_DIV0_MASK) >> CLK_CTRL_DIV0_SHIFT;
+	u32 div1 = 1;
+
+	if (clk->flags & ZYNQ_CLK_FLAGS_HAS_2_DIVS)
+		div1 = (clk_ctrl & CLK_CTRL_DIV1_MASK) >> CLK_CTRL_DIV1_SHIFT;
+
+	/* a register value of zero == division by 1 */
+	if (!div0)
+		div0 = 1;
+	if (!div1)
+		div1 = 1;
+
+	return
+		DIV_ROUND_CLOSEST(
+			DIV_ROUND_CLOSEST(zynq_clk_get_rate(clk->parent), div0),
+			div1);
+}
+
+/**
+ * __zynq_clk_periph_get_parent() - Decode clock multiplexer
+ * @srcsel:	Mux select value
+ * Returns the clock identifier associated with the selected mux input.
+ */
+static enum zynq_clk __zynq_clk_periph_get_parent(u32 srcsel)
+{
+	switch (srcsel) {
+	case ZYNQ_CLKMUX_SEL_0:
+	case ZYNQ_CLKMUX_SEL_1:
+		return iopll_clk;
+	case ZYNQ_CLKMUX_SEL_2:
+		return armpll_clk;
+	case ZYNQ_CLKMUX_SEL_3:
+		return ddrpll_clk;
+	default:
+		return 0;
+	}
+}
+
+/**
+ * zynq_clk_periph_get_parent() - Decode clock multiplexer
+ * @clk:	Clock handle
+ * Returns the clock identifier associated with the selected mux input.
+ */
+static enum zynq_clk zynq_clk_periph_get_parent(struct clk *clk)
+{
+	u32 clk_ctrl = readl(clk->reg);
+	u32 srcsel = (clk_ctrl & CLK_CTRL_SRCSEL_MASK) >> CLK_CTRL_SRCSEL_SHIFT;
+
+	return __zynq_clk_periph_get_parent(srcsel);
+}
+
+/**
+ * zynq_clk_register_periph_clk() - Set up a peripheral clock with the framework
+ * @clk:	Pointer to struct clk for the clock
+ * @ctrl:	Clock control register
+ * @name:	PLL name
+ * @two_divs:	Indicates whether the clock features one or two dividers
+ */
+static int zynq_clk_register_periph_clk(struct clk *clk, u32 *ctrl, char *name,
+		bool two_divs)
+{
+	clk->name = name;
+	clk->reg = ctrl;
+	if (two_divs)
+		clk->flags = ZYNQ_CLK_FLAGS_HAS_2_DIVS;
+	clk->parent = zynq_clk_periph_get_parent(clk);
+	clk->frequency = zynq_clk_periph_get_rate(clk);
+	clk->ops.get_rate = zynq_clk_periph_get_rate;
+	clk->ops.set_rate = zynq_clk_periph_set_rate;
+
+	return 0;
+}
+
+static void init_periph_clocks(void)
+{
+	zynq_clk_register_periph_clk(&clks[gem0_clk], &slcr_base->gem0_clk_ctrl,
+				     "gem0", 1);
+	zynq_clk_register_periph_clk(&clks[gem1_clk], &slcr_base->gem1_clk_ctrl,
+				     "gem1", 1);
+
+	zynq_clk_register_periph_clk(&clks[smc_clk], &slcr_base->smc_clk_ctrl,
+				     "smc", 0);
+
+	zynq_clk_register_periph_clk(&clks[lqspi_clk],
+				     &slcr_base->lqspi_clk_ctrl, "lqspi", 0);
+
+	zynq_clk_register_periph_clk(&clks[sdio0_clk],
+				     &slcr_base->sdio_clk_ctrl, "sdio0", 0);
+	zynq_clk_register_periph_clk(&clks[sdio1_clk],
+				     &slcr_base->sdio_clk_ctrl, "sdio1", 0);
+
+	zynq_clk_register_periph_clk(&clks[spi0_clk], &slcr_base->spi_clk_ctrl,
+				     "spi0", 0);
+	zynq_clk_register_periph_clk(&clks[spi1_clk], &slcr_base->spi_clk_ctrl,
+				     "spi1", 0);
+
+	zynq_clk_register_periph_clk(&clks[uart0_clk],
+				     &slcr_base->uart_clk_ctrl, "uart0", 0);
+	zynq_clk_register_periph_clk(&clks[uart1_clk],
+				     &slcr_base->uart_clk_ctrl, "uart1", 0);
+
+	zynq_clk_register_periph_clk(&clks[dbg_trc_clk],
+				     &slcr_base->dbg_clk_ctrl, "dbg_trc", 0);
+	zynq_clk_register_periph_clk(&clks[dbg_apb_clk],
+				     &slcr_base->dbg_clk_ctrl, "dbg_apb", 0);
+
+	zynq_clk_register_periph_clk(&clks[pcap_clk],
+				     &slcr_base->pcap_clk_ctrl, "pcap", 0);
+
+	zynq_clk_register_periph_clk(&clks[fclk0_clk],
+				     &slcr_base->fpga0_clk_ctrl, "fclk0", 1);
+	zynq_clk_register_periph_clk(&clks[fclk1_clk],
+				     &slcr_base->fpga1_clk_ctrl, "fclk1", 1);
+	zynq_clk_register_periph_clk(&clks[fclk2_clk],
+				     &slcr_base->fpga2_clk_ctrl, "fclk2", 1);
+	zynq_clk_register_periph_clk(&clks[fclk3_clk],
+				     &slcr_base->fpga3_clk_ctrl, "fclk3", 1);
+}
+
+/**
+ * zynq_clk_register_aper_clk() - Set up a APER clock with the framework
+ * @clk:	Pointer to struct clk for the clock
+ * @ctrl:	Clock control register
+ * @name:	PLL name
+ */
+static void zynq_clk_register_aper_clk(struct clk *clk, u32 *ctrl, char *name)
+{
+	clk->name = name;
+	clk->reg = ctrl;
+	clk->parent = cpu_1x_clk;
+	clk->frequency = zynq_clk_get_rate(clk->parent);
+}
+
+static void init_aper_clocks(void)
+{
+	zynq_clk_register_aper_clk(&clks[usb0_aper_clk],
+				   &slcr_base->aper_clk_ctrl, "usb0_aper");
+	zynq_clk_register_aper_clk(&clks[usb1_aper_clk],
+				   &slcr_base->aper_clk_ctrl, "usb1_aper");
+
+	zynq_clk_register_aper_clk(&clks[gem0_aper_clk],
+				   &slcr_base->aper_clk_ctrl, "gem0_aper");
+	zynq_clk_register_aper_clk(&clks[gem1_aper_clk],
+				   &slcr_base->aper_clk_ctrl, "gem1_aper");
+
+	zynq_clk_register_aper_clk(&clks[sdio0_aper_clk],
+				   &slcr_base->aper_clk_ctrl, "sdio0_aper");
+	zynq_clk_register_aper_clk(&clks[sdio1_aper_clk],
+				   &slcr_base->aper_clk_ctrl, "sdio1_aper");
+
+	zynq_clk_register_aper_clk(&clks[spi0_aper_clk],
+				   &slcr_base->aper_clk_ctrl, "spi0_aper");
+	zynq_clk_register_aper_clk(&clks[spi1_aper_clk],
+				   &slcr_base->aper_clk_ctrl, "spi1_aper");
+
+	zynq_clk_register_aper_clk(&clks[can0_aper_clk],
+				   &slcr_base->aper_clk_ctrl, "can0_aper");
+	zynq_clk_register_aper_clk(&clks[can1_aper_clk],
+				   &slcr_base->aper_clk_ctrl, "can1_aper");
+
+	zynq_clk_register_aper_clk(&clks[i2c0_aper_clk],
+				   &slcr_base->aper_clk_ctrl, "i2c0_aper");
+	zynq_clk_register_aper_clk(&clks[i2c1_aper_clk],
+				   &slcr_base->aper_clk_ctrl, "i2c1_aper");
+
+	zynq_clk_register_aper_clk(&clks[uart0_aper_clk],
+				   &slcr_base->aper_clk_ctrl, "uart0_aper");
+	zynq_clk_register_aper_clk(&clks[uart1_aper_clk],
+				   &slcr_base->aper_clk_ctrl, "uart1_aper");
+
+	zynq_clk_register_aper_clk(&clks[gpio_aper_clk],
+				   &slcr_base->aper_clk_ctrl, "gpio_aper");
+
+	zynq_clk_register_aper_clk(&clks[lqspi_aper_clk],
+				   &slcr_base->aper_clk_ctrl, "lqspi_aper");
+
+	zynq_clk_register_aper_clk(&clks[smc_aper_clk],
+				   &slcr_base->aper_clk_ctrl, "smc_aper");
+}
+
+/**
+ * __zynq_clk_pll_get_rate() - Get PLL rate
+ * @addr:	Address of the PLL's control register
+ * Returns the current PLL output rate.
+ */
+static unsigned long __zynq_clk_pll_get_rate(u32 *addr)
+{
+	u32 reg, mul, bypass;
+
+	reg = readl(addr);
+	bypass = reg & PLLCTRL_BPFORCE_MASK;
+	if (bypass)
+		mul = 1;
+	else
+		mul = (reg & PLLCTRL_FBDIV_MASK) >> PLLCTRL_FBDIV_SHIFT;
+
+	return CONFIG_ZYNQ_PS_CLK_FREQ * mul;
+}
+
+/**
+ * zynq_clk_pll_get_rate() - Get PLL rate
+ * @pll:	Handle of the PLL
+ * Returns the current clock rate of @pll.
+ */
+static unsigned long zynq_clk_pll_get_rate(struct clk *pll)
+{
+	return __zynq_clk_pll_get_rate(pll->reg);
+}
+
+/**
+ * zynq_clk_register_pll() - Set up a PLL with the framework
+ * @clk:	Pointer to struct clk for the PLL
+ * @ctrl:	PLL control register
+ * @name:	PLL name
+ * @prate:	PLL input clock rate
+ */
+static void zynq_clk_register_pll(struct clk *clk, u32 *ctrl, char *name,
+		unsigned long prate)
+{
+	clk->name = name;
+	clk->reg = ctrl;
+	clk->frequency = zynq_clk_pll_get_rate(clk);
+	clk->ops.get_rate = zynq_clk_pll_get_rate;
+}
+
+/**
+ * clkid_2_register() - Get clock control register
+ * @id:	Clock identifier of one of the PLLs
+ * Returns the address of the requested PLL's control register.
+ */
+static u32 *clkid_2_register(enum zynq_clk id)
+{
+	switch (id) {
+	case armpll_clk:
+		return &slcr_base->arm_pll_ctrl;
+	case ddrpll_clk:
+		return &slcr_base->ddr_pll_ctrl;
+	case iopll_clk:
+		return &slcr_base->io_pll_ctrl;
+	default:
+		return &slcr_base->io_pll_ctrl;
+	}
+}
+
+/* API */
+/**
+ * zynq_clk_early_init() - Early init for the clock framework
+ *
+ * This function is called from before relocation and sets up the CPU clock
+ * frequency in the global data struct.
+ */
+void zynq_clk_early_init(void)
+{
+	u32 reg = readl(&slcr_base->arm_clk_ctrl);
+	u32 div = (reg & CLK_CTRL_DIV0_MASK) >> CLK_CTRL_DIV0_SHIFT;
+	u32 srcsel = (reg & CLK_CTRL_SRCSEL_MASK) >> CLK_CTRL_SRCSEL_SHIFT;
+	enum zynq_clk parent = __zynq_clk_cpu_get_parent(srcsel);
+	u32 *pllreg = clkid_2_register(parent);
+	unsigned long prate = __zynq_clk_pll_get_rate(pllreg);
+
+	if (!div)
+		div = 1;
+
+	gd->cpu_clk = DIV_ROUND_CLOSEST(prate, div);
+}
+
+/**
+ * get_uart_clk() - Get UART input frequency
+ * @dev_index:	UART ID
+ * Returns UART input clock frequency in Hz.
+ *
+ * Compared to zynq_clk_get_rate() this function is designed to work before
+ * relocation and can be called when the serial UART is set up.
+ */
+unsigned long get_uart_clk(int dev_index)
+{
+	u32 reg = readl(&slcr_base->uart_clk_ctrl);
+	u32 div = (reg & CLK_CTRL_DIV0_MASK) >> CLK_CTRL_DIV0_SHIFT;
+	u32 srcsel = (reg & CLK_CTRL_SRCSEL_MASK) >> CLK_CTRL_SRCSEL_SHIFT;
+	enum zynq_clk parent = __zynq_clk_periph_get_parent(srcsel);
+	u32 *pllreg = clkid_2_register(parent);
+	unsigned long prate = __zynq_clk_pll_get_rate(pllreg);
+
+	if (!div)
+		div = 1;
+
+	return DIV_ROUND_CLOSEST(prate, div);
+}
+
+/**
+ * set_cpu_clk_info() - Initialize clock framework
+ * Always returns zero.
+ *
+ * This function is called from common code after relocation and sets up the
+ * clock framework. The framework must not be used before this function had been
+ * called.
+ */
+int set_cpu_clk_info(void)
+{
+	zynq_clk_register_pll(&clks[armpll_clk], &slcr_base->arm_pll_ctrl,
+			      "armpll", CONFIG_ZYNQ_PS_CLK_FREQ);
+	zynq_clk_register_pll(&clks[ddrpll_clk], &slcr_base->ddr_pll_ctrl,
+			      "ddrpll", CONFIG_ZYNQ_PS_CLK_FREQ);
+	zynq_clk_register_pll(&clks[iopll_clk], &slcr_base->io_pll_ctrl,
+			      "iopll", CONFIG_ZYNQ_PS_CLK_FREQ);
+
+	init_ddr_clocks();
+	init_cpu_clocks();
+	init_periph_clocks();
+	init_aper_clocks();
+
+	gd->bd->bi_arm_freq = gd->cpu_clk / 1000000;
+	gd->bd->bi_dsp_freq = 0;
+
+	return 0;
+}
+
+/**
+ * zynq_clk_get_rate() - Get clock rate
+ * @clk:	Clock identifier
+ * Returns the current clock rate of @clk on success or zero for an invalid
+ * clock id.
+ */
+unsigned long zynq_clk_get_rate(enum zynq_clk clk)
+{
+	if (clk < 0 || clk >= clk_max)
+		return 0;
+
+	return clks[clk].frequency;
+}
+
+/**
+ * zynq_clk_set_rate() - Set clock rate
+ * @clk:	Clock identifier
+ * @rate:	Requested clock rate
+ * Passes on the return value from the clock's set_rate() function or negative
+ * errno.
+ */
+int zynq_clk_set_rate(enum zynq_clk clk, unsigned long rate)
+{
+	if (clk < 0 || clk >= clk_max)
+		return -ENODEV;
+
+	if (clks[clk].ops.set_rate)
+		return clks[clk].ops.set_rate(&clks[clk], rate);
+
+	return -ENXIO;
+}
+
+/**
+ * zynq_clk_get_name() - Get clock name
+ * @clk:	Clock identifier
+ * Returns the name of @clk.
+ */
+const char *zynq_clk_get_name(enum zynq_clk clk)
+{
+	return clks[clk].name;
+}
+
+/**
+ * soc_clk_dump() - Print clock frequencies
+ * Returns zero on success
+ *
+ * Implementation for the clk dump command.
+ */
+int soc_clk_dump(void)
+{
+	int i;
+
+	printf("clk\t\tfrequency\n");
+	for (i = 0; i < clk_max; i++) {
+		const char *name = zynq_clk_get_name(i);
+		if (name)
+			printf("%10s%20lu\n", name, zynq_clk_get_rate(i));
+	}
+
+	return 0;
+}
diff --git a/arch/arm/cpu/armv7/zynq/cpu.c b/arch/arm/cpu/armv7/zynq/cpu.c
index 49149861f8..7626b5c1a3 100644
--- a/arch/arm/cpu/armv7/zynq/cpu.c
+++ b/arch/arm/cpu/armv7/zynq/cpu.c
@@ -6,31 +6,40 @@
  */
 #include <common.h>
 #include <asm/io.h>
+#include <asm/arch/clk.h>
 #include <asm/arch/sys_proto.h>
 #include <asm/arch/hardware.h>
 
 void lowlevel_init(void)
 {
-	zynq_slcr_unlock();
-	/* remap DDR to zero, FILTERSTART */
-	writel(0, &scu_base->filter_start);
+}
 
+int arch_cpu_init(void)
+{
+	zynq_slcr_unlock();
+#ifndef CONFIG_SPL_BUILD
 	/* Device config APB, unlock the PCAP */
 	writel(0x757BDF0D, &devcfg_base->unlock);
 	writel(0xFFFFFFFF, &devcfg_base->rom_shadow);
 
+#if (CONFIG_SYS_SDRAM_BASE == 0)
+	/* remap DDR to zero, FILTERSTART */
+	writel(0, &scu_base->filter_start);
+
 	/* OCM_CFG, Mask out the ROM, map ram into upper addresses */
 	writel(0x1F, &slcr_base->ocm_cfg);
 	/* FPGA_RST_CTRL, clear resets on AXI fabric ports */
 	writel(0x0, &slcr_base->fpga_rst_ctrl);
-	/* TZ_DDR_RAM, Set DDR trust zone non-secure */
-	writel(0xFFFFFFFF, &slcr_base->trust_zone);
 	/* Set urgent bits with register */
 	writel(0x0, &slcr_base->ddr_urgent_sel);
 	/* Urgent write, ports S2/S3 */
 	writel(0xC, &slcr_base->ddr_urgent);
-
+#endif
+#endif
+	zynq_clk_early_init();
 	zynq_slcr_lock();
+
+	return 0;
 }
 
 void reset_cpu(ulong addr)
@@ -39,3 +48,11 @@ void reset_cpu(ulong addr)
 	while (1)
 		;
 }
+
+#ifndef CONFIG_SYS_DCACHE_OFF
+void enable_caches(void)
+{
+	/* Enable D-cache. I-cache is already enabled in start.S */
+	dcache_enable();
+}
+#endif
diff --git a/arch/arm/cpu/armv7/zynq/slcr.c b/arch/arm/cpu/armv7/zynq/slcr.c
index 717ec65aee..d7c1882332 100644
--- a/arch/arm/cpu/armv7/zynq/slcr.c
+++ b/arch/arm/cpu/armv7/zynq/slcr.c
@@ -8,6 +8,7 @@
 #include <asm/io.h>
 #include <malloc.h>
 #include <asm/arch/hardware.h>
+#include <asm/arch/clk.h>
 
 #define SLCR_LOCK_MAGIC		0x767B
 #define SLCR_UNLOCK_MAGIC	0xDF0D
@@ -50,8 +51,10 @@ void zynq_slcr_cpu_reset(void)
 }
 
 /* Setup clk for network */
-void zynq_slcr_gem_clk_setup(u32 gem_id, u32 rclk, u32 clk)
+void zynq_slcr_gem_clk_setup(u32 gem_id, unsigned long clk_rate)
 {
+	int ret;
+
 	zynq_slcr_unlock();
 
 	if (gem_id > 1) {
@@ -59,16 +62,16 @@ void zynq_slcr_gem_clk_setup(u32 gem_id, u32 rclk, u32 clk)
 		goto out;
 	}
 
+	ret = zynq_clk_set_rate(gem0_clk + gem_id, clk_rate);
+	if (ret)
+		goto out;
+
 	if (gem_id) {
-		/* Set divisors for appropriate frequency in GEM_CLK_CTRL */
-		writel(clk, &slcr_base->gem1_clk_ctrl);
 		/* Configure GEM_RCLK_CTRL */
-		writel(rclk, &slcr_base->gem1_rclk_ctrl);
+		writel(1, &slcr_base->gem1_rclk_ctrl);
 	} else {
-		/* Set divisors for appropriate frequency in GEM_CLK_CTRL */
-		writel(clk, &slcr_base->gem0_clk_ctrl);
 		/* Configure GEM_RCLK_CTRL */
-		writel(rclk, &slcr_base->gem0_rclk_ctrl);
+		writel(1, &slcr_base->gem0_rclk_ctrl);
 	}
 	udelay(100000);
 out:
@@ -101,6 +104,12 @@ void zynq_slcr_devcfg_enable(void)
 	zynq_slcr_lock();
 }
 
+u32 zynq_slcr_get_boot_mode(void)
+{
+	/* Get the bootmode register value */
+	return readl(&slcr_base->boot_mode);
+}
+
 u32 zynq_slcr_get_idcode(void)
 {
 	return (readl(&slcr_base->pss_idcode) & SLCR_IDCODE_MASK) >>
diff --git a/arch/arm/cpu/armv7/zynq/spl.c b/arch/arm/cpu/armv7/zynq/spl.c
new file mode 100644
index 0000000000..fcad762c03
--- /dev/null
+++ b/arch/arm/cpu/armv7/zynq/spl.c
@@ -0,0 +1,69 @@
+/*
+ * (C) Copyright 2014 Xilinx, Inc. Michal Simek
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+#include <common.h>
+#include <spl.h>
+
+#include <asm/io.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/spl.h>
+#include <asm/arch/sys_proto.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void board_init_f(ulong dummy)
+{
+	ps7_init();
+
+	/* Clear the BSS. */
+	memset(__bss_start, 0, __bss_end - __bss_start);
+
+	/* Set global data pointer. */
+	gd = &gdata;
+
+	preloader_console_init();
+	arch_cpu_init();
+	board_init_r(NULL, 0);
+}
+
+u32 spl_boot_device(void)
+{
+	u32 mode;
+
+	switch ((zynq_slcr_get_boot_mode()) & ZYNQ_BM_MASK) {
+#ifdef CONFIG_SPL_SPI_SUPPORT
+	case ZYNQ_BM_QSPI:
+		puts("qspi boot\n");
+		mode = BOOT_DEVICE_SPI;
+		break;
+#endif
+#ifdef CONFIG_SPL_MMC_SUPPORT
+	case ZYNQ_BM_SD:
+		puts("mmc boot\n");
+		mode = BOOT_DEVICE_MMC1;
+		break;
+#endif
+	default:
+		puts("Unsupported boot mode selected\n");
+		hang();
+	}
+
+	return mode;
+}
+
+#ifdef CONFIG_SPL_MMC_SUPPORT
+u32 spl_boot_mode(void)
+{
+	return MMCSD_MODE_FAT;
+}
+#endif
+
+#ifdef CONFIG_SPL_OS_BOOT
+int spl_start_uboot(void)
+{
+	/* boot linux */
+	return 0;
+}
+#endif
diff --git a/arch/arm/cpu/armv7/zynq/timer.c b/arch/arm/cpu/armv7/zynq/timer.c
index 636322a8e5..303dbcfcea 100644
--- a/arch/arm/cpu/armv7/zynq/timer.c
+++ b/arch/arm/cpu/armv7/zynq/timer.c
@@ -29,6 +29,7 @@
 #include <div64.h>
 #include <asm/io.h>
 #include <asm/arch/hardware.h>
+#include <asm/arch/clk.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -48,7 +49,6 @@ static struct scu_timer *timer_base =
 
 #define TIMER_LOAD_VAL 0xFFFFFFFF
 #define TIMER_PRESCALE 255
-#define TIMER_TICK_HZ  (CONFIG_CPU_FREQ_HZ / 2 / TIMER_PRESCALE)
 
 int timer_init(void)
 {
@@ -56,6 +56,8 @@ int timer_init(void)
 			(TIMER_PRESCALE << SCUTIMER_CONTROL_PRESCALER_SHIFT) |
 			SCUTIMER_CONTROL_ENABLE_MASK;
 
+	gd->arch.timer_rate_hz = (gd->cpu_clk / 2) / (TIMER_PRESCALE + 1);
+
 	/* Load the timer counter register */
 	writel(0xFFFFFFFF, &timer_base->load);
 
@@ -69,7 +71,7 @@ int timer_init(void)
 
 	/* Reset time */
 	gd->arch.lastinc = readl(&timer_base->counter) /
-					(TIMER_TICK_HZ / CONFIG_SYS_HZ);
+				(gd->arch.timer_rate_hz / CONFIG_SYS_HZ);
 	gd->arch.tbl = 0;
 
 	return 0;
@@ -83,14 +85,15 @@ ulong get_timer_masked(void)
 {
 	ulong now;
 
-	now = readl(&timer_base->counter) / (TIMER_TICK_HZ / CONFIG_SYS_HZ);
+	now = readl(&timer_base->counter) /
+			(gd->arch.timer_rate_hz / CONFIG_SYS_HZ);
 
 	if (gd->arch.lastinc >= now) {
 		/* Normal mode */
 		gd->arch.tbl += gd->arch.lastinc - now;
 	} else {
 		/* We have an overflow ... */
-		gd->arch.tbl += gd->arch.lastinc + TIMER_LOAD_VAL - now;
+		gd->arch.tbl += gd->arch.lastinc + TIMER_LOAD_VAL - now + 1;
 	}
 	gd->arch.lastinc = now;
 
@@ -107,8 +110,8 @@ void __udelay(unsigned long usec)
 	if (usec == 0)
 		return;
 
-	countticks = (u32) (((unsigned long long) TIMER_TICK_HZ * usec) /
-								1000000);
+	countticks = lldiv(((unsigned long long)gd->arch.timer_rate_hz * usec),
+			   1000000);
 
 	/* decrementing timer */
 	timeend = readl(&timer_base->counter) - countticks;
diff --git a/arch/arm/cpu/armv7/zynq/u-boot-spl.lds b/arch/arm/cpu/armv7/zynq/u-boot-spl.lds
new file mode 100644
index 0000000000..0c4501e5c7
--- /dev/null
+++ b/arch/arm/cpu/armv7/zynq/u-boot-spl.lds
@@ -0,0 +1,61 @@
+/*
+ * Copyright (c) 2014 Xilinx, Inc. Michal Simek
+ * Copyright (c) 2004-2008 Texas Instruments
+ *
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+MEMORY { .sram : ORIGIN = CONFIG_SPL_TEXT_BASE,\
+		LENGTH = CONFIG_SPL_MAX_SIZE }
+MEMORY { .sdram : ORIGIN = CONFIG_SPL_BSS_START_ADDR, \
+		LENGTH = CONFIG_SPL_BSS_MAX_SIZE }
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+	. = ALIGN(4);
+	.text :
+	{
+		__image_copy_start = .;
+		CPUDIR/start.o (.text*)
+		*(.text*)
+	} > .sram
+
+	. = ALIGN(4);
+	.rodata : {
+		*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
+	} > .sram
+
+	. = ALIGN(4);
+	.data : {
+		*(.data*)
+	} > .sram
+
+	. = ALIGN(4);
+
+	. = .;
+
+	__image_copy_end = .;
+
+	_end = .;
+
+	/* Move BSS section to RAM because of FAT */
+	.bss (NOLOAD) : {
+		__bss_start = .;
+		*(.bss*)
+		 . = ALIGN(4);
+		__bss_end = .;
+	} > .sdram
+
+	/DISCARD/ : { *(.dynsym) }
+	/DISCARD/ : { *(.dynstr*) }
+	/DISCARD/ : { *(.dynamic*) }
+	/DISCARD/ : { *(.plt*) }
+	/DISCARD/ : { *(.interp*) }
+	/DISCARD/ : { *(.gnu*) }
+}
diff --git a/arch/arm/cpu/armv7/zynq/u-boot.lds b/arch/arm/cpu/armv7/zynq/u-boot.lds
new file mode 100644
index 0000000000..f2a5965988
--- /dev/null
+++ b/arch/arm/cpu/armv7/zynq/u-boot.lds
@@ -0,0 +1,104 @@
+/*
+ * Copyright (c) 2004-2008 Texas Instruments
+ *
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+	. = 0x00000000;
+
+	. = ALIGN(4);
+	.text :
+	{
+		*(.__image_copy_start)
+		CPUDIR/start.o (.text*)
+		*(.text*)
+	}
+
+	. = ALIGN(4);
+	.rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
+
+	. = ALIGN(4);
+	.data : {
+		*(.data*)
+	}
+
+	. = ALIGN(4);
+
+	. = .;
+
+	. = ALIGN(4);
+	.u_boot_list : {
+		KEEP(*(SORT(.u_boot_list*)));
+	}
+
+	. = ALIGN(4);
+
+	.image_copy_end :
+	{
+		*(.__image_copy_end)
+	}
+
+	.rel_dyn_start :
+	{
+		*(.__rel_dyn_start)
+	}
+
+	.rel.dyn : {
+		*(.rel*)
+	}
+
+	.rel_dyn_end :
+	{
+		*(.__rel_dyn_end)
+	}
+
+	.end :
+	{
+		*(.__end)
+	}
+
+	_image_binary_end = .;
+
+/*
+ * Compiler-generated __bss_start and __bss_end, see arch/arm/lib/bss.c
+ * __bss_base and __bss_limit are for linker only (overlay ordering)
+ */
+
+	.bss_start __rel_dyn_start (OVERLAY) : {
+		KEEP(*(.__bss_start));
+		__bss_base = .;
+	}
+
+	.bss __bss_base (OVERLAY) : {
+		*(.bss*)
+		 . = ALIGN(4);
+		 __bss_limit = .;
+	}
+
+	.bss_end __bss_limit (OVERLAY) : {
+		KEEP(*(.__bss_end));
+	}
+
+	/*
+	 * Zynq needs to discard more sections because the user
+	 * is expected to pass this image on to tools for boot.bin
+	 * generation that require them to be dropped.
+	 */
+	/DISCARD/ : { *(.dynsym) }
+	/DISCARD/ : { *(.dynbss*) }
+	/DISCARD/ : { *(.dynstr*) }
+	/DISCARD/ : { *(.dynamic*) }
+	/DISCARD/ : { *(.plt*) }
+	/DISCARD/ : { *(.interp*) }
+	/DISCARD/ : { *(.gnu*) }
+	/DISCARD/ : { *(.ARM.exidx*) }
+	/DISCARD/ : { *(.gnu.linkonce.armexidx.*) }
+}
diff --git a/arch/arm/cpu/armv8/Makefile b/arch/arm/cpu/armv8/Makefile
new file mode 100644
index 0000000000..7d93f59428
--- /dev/null
+++ b/arch/arm/cpu/armv8/Makefile
@@ -0,0 +1,16 @@
+#
+# (C) Copyright 2000-2003
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+extra-y	:= start.o
+
+obj-y	+= cpu.o
+obj-y	+= generic_timer.o
+obj-y	+= cache_v8.o
+obj-y	+= exceptions.o
+obj-y	+= cache.o
+obj-y	+= tlb.o
+obj-y	+= transition.o
diff --git a/arch/arm/cpu/armv8/cache.S b/arch/arm/cpu/armv8/cache.S
new file mode 100644
index 0000000000..4b3ee6ed6f
--- /dev/null
+++ b/arch/arm/cpu/armv8/cache.S
@@ -0,0 +1,157 @@
+/*
+ * (C) Copyright 2013
+ * David Feng <fenghua@phytium.com.cn>
+ *
+ * This file is based on sample code from ARMv8 ARM.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <asm-offsets.h>
+#include <config.h>
+#include <version.h>
+#include <asm/macro.h>
+#include <linux/linkage.h>
+
+/*
+ * void __asm_flush_dcache_level(level)
+ *
+ * clean and invalidate one level cache.
+ *
+ * x0: cache level
+ * x1: 0 flush & invalidate, 1 invalidate only
+ * x2~x9: clobbered
+ */
+ENTRY(__asm_flush_dcache_level)
+	lsl	x12, x0, #1
+	msr	csselr_el1, x12		/* select cache level */
+	isb				/* sync change of cssidr_el1 */
+	mrs	x6, ccsidr_el1		/* read the new cssidr_el1 */
+	and	x2, x6, #7		/* x2 <- log2(cache line size)-4 */
+	add	x2, x2, #4		/* x2 <- log2(cache line size) */
+	mov	x3, #0x3ff
+	and	x3, x3, x6, lsr #3	/* x3 <- max number of #ways */
+	clz	w5, w3			/* bit position of #ways */
+	mov	x4, #0x7fff
+	and	x4, x4, x6, lsr #13	/* x4 <- max number of #sets */
+	/* x12 <- cache level << 1 */
+	/* x2 <- line length offset */
+	/* x3 <- number of cache ways - 1 */
+	/* x4 <- number of cache sets - 1 */
+	/* x5 <- bit position of #ways */
+
+loop_set:
+	mov	x6, x3			/* x6 <- working copy of #ways */
+loop_way:
+	lsl	x7, x6, x5
+	orr	x9, x12, x7		/* map way and level to cisw value */
+	lsl	x7, x4, x2
+	orr	x9, x9, x7		/* map set number to cisw value */
+	tbz	w1, #0, 1f
+	dc	isw, x9
+	b	2f
+1:	dc	cisw, x9		/* clean & invalidate by set/way */
+2:	subs	x6, x6, #1		/* decrement the way */
+	b.ge	loop_way
+	subs	x4, x4, #1		/* decrement the set */
+	b.ge	loop_set
+
+	ret
+ENDPROC(__asm_flush_dcache_level)
+
+/*
+ * void __asm_flush_dcache_all(int invalidate_only)
+ *
+ * x0: 0 flush & invalidate, 1 invalidate only
+ *
+ * clean and invalidate all data cache by SET/WAY.
+ */
+ENTRY(__asm_dcache_all)
+	mov	x1, x0
+	dsb	sy
+	mrs	x10, clidr_el1		/* read clidr_el1 */
+	lsr	x11, x10, #24
+	and	x11, x11, #0x7		/* x11 <- loc */
+	cbz	x11, finished		/* if loc is 0, exit */
+	mov	x15, lr
+	mov	x0, #0			/* start flush at cache level 0 */
+	/* x0  <- cache level */
+	/* x10 <- clidr_el1 */
+	/* x11 <- loc */
+	/* x15 <- return address */
+
+loop_level:
+	lsl	x12, x0, #1
+	add	x12, x12, x0		/* x0 <- tripled cache level */
+	lsr	x12, x10, x12
+	and	x12, x12, #7		/* x12 <- cache type */
+	cmp	x12, #2
+	b.lt	skip			/* skip if no cache or icache */
+	bl	__asm_flush_dcache_level	/* x1 = 0 flush, 1 invalidate */
+skip:
+	add	x0, x0, #1		/* increment cache level */
+	cmp	x11, x0
+	b.gt	loop_level
+
+	mov	x0, #0
+	msr	csselr_el1, x0		/* resotre csselr_el1 */
+	dsb	sy
+	isb
+	mov	lr, x15
+
+finished:
+	ret
+ENDPROC(__asm_dcache_all)
+
+ENTRY(__asm_flush_dcache_all)
+	mov	x16, lr
+	mov	x0, #0
+	bl	__asm_dcache_all
+	mov	lr, x16
+	ret
+ENDPROC(__asm_flush_dcache_all)
+
+ENTRY(__asm_invalidate_dcache_all)
+	mov	x16, lr
+	mov	x0, #0xffff
+	bl	__asm_dcache_all
+	mov	lr, x16
+	ret
+ENDPROC(__asm_invalidate_dcache_all)
+
+/*
+ * void __asm_flush_dcache_range(start, end)
+ *
+ * clean & invalidate data cache in the range
+ *
+ * x0: start address
+ * x1: end address
+ */
+ENTRY(__asm_flush_dcache_range)
+	mrs	x3, ctr_el0
+	lsr	x3, x3, #16
+	and	x3, x3, #0xf
+	mov	x2, #4
+	lsl	x2, x2, x3		/* cache line size */
+
+	/* x2 <- minimal cache line size in cache system */
+	sub	x3, x2, #1
+	bic	x0, x0, x3
+1:	dc	civac, x0	/* clean & invalidate data or unified cache */
+	add	x0, x0, x2
+	cmp	x0, x1
+	b.lo	1b
+	dsb	sy
+	ret
+ENDPROC(__asm_flush_dcache_range)
+
+/*
+ * void __asm_invalidate_icache_all(void)
+ *
+ * invalidate all tlb entries.
+ */
+ENTRY(__asm_invalidate_icache_all)
+	ic	ialluis
+	isb	sy
+	ret
+ENDPROC(__asm_invalidate_icache_all)
diff --git a/arch/arm/cpu/armv8/cache_v8.c b/arch/arm/cpu/armv8/cache_v8.c
new file mode 100644
index 0000000000..a96ecda7e3
--- /dev/null
+++ b/arch/arm/cpu/armv8/cache_v8.c
@@ -0,0 +1,236 @@
+/*
+ * (C) Copyright 2013
+ * David Feng <fenghua@phytium.com.cn>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/system.h>
+#include <asm/armv8/mmu.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#ifndef CONFIG_SYS_DCACHE_OFF
+
+static void set_pgtable_section(u64 section, u64 memory_type)
+{
+	u64 *page_table = (u64 *)gd->arch.tlb_addr;
+	u64 value;
+
+	value = (section << SECTION_SHIFT) | PMD_TYPE_SECT | PMD_SECT_AF;
+	value |= PMD_ATTRINDX(memory_type);
+	page_table[section] = value;
+}
+
+/* to activate the MMU we need to set up virtual memory */
+static void mmu_setup(void)
+{
+	int i, j, el;
+	bd_t *bd = gd->bd;
+
+	/* Setup an identity-mapping for all spaces */
+	for (i = 0; i < (PGTABLE_SIZE >> 3); i++)
+		set_pgtable_section(i, MT_DEVICE_NGNRNE);
+
+	/* Setup an identity-mapping for all RAM space */
+	for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
+		ulong start = bd->bi_dram[i].start;
+		ulong end = bd->bi_dram[i].start + bd->bi_dram[i].size;
+		for (j = start >> SECTION_SHIFT;
+		     j < end >> SECTION_SHIFT; j++) {
+			set_pgtable_section(j, MT_NORMAL);
+		}
+	}
+
+	/* load TTBR0 */
+	el = current_el();
+	if (el == 1) {
+		asm volatile("msr ttbr0_el1, %0"
+			     : : "r" (gd->arch.tlb_addr) : "memory");
+		asm volatile("msr tcr_el1, %0"
+			     : : "r" (TCR_FLAGS | TCR_EL1_IPS_BITS)
+			     : "memory");
+		asm volatile("msr mair_el1, %0"
+			     : : "r" (MEMORY_ATTRIBUTES) : "memory");
+	} else if (el == 2) {
+		asm volatile("msr ttbr0_el2, %0"
+			     : : "r" (gd->arch.tlb_addr) : "memory");
+		asm volatile("msr tcr_el2, %0"
+			     : : "r" (TCR_FLAGS | TCR_EL2_IPS_BITS)
+			     : "memory");
+		asm volatile("msr mair_el2, %0"
+			     : : "r" (MEMORY_ATTRIBUTES) : "memory");
+	} else {
+		asm volatile("msr ttbr0_el3, %0"
+			     : : "r" (gd->arch.tlb_addr) : "memory");
+		asm volatile("msr tcr_el3, %0"
+			     : : "r" (TCR_FLAGS | TCR_EL2_IPS_BITS)
+			     : "memory");
+		asm volatile("msr mair_el3, %0"
+			     : : "r" (MEMORY_ATTRIBUTES) : "memory");
+	}
+
+	/* enable the mmu */
+	set_sctlr(get_sctlr() | CR_M);
+}
+
+/*
+ * Performs a invalidation of the entire data cache at all levels
+ */
+void invalidate_dcache_all(void)
+{
+	__asm_invalidate_dcache_all();
+}
+
+/*
+ * Performs a clean & invalidation of the entire data cache at all levels
+ */
+void flush_dcache_all(void)
+{
+	__asm_flush_dcache_all();
+}
+
+/*
+ * Invalidates range in all levels of D-cache/unified cache
+ */
+void invalidate_dcache_range(unsigned long start, unsigned long stop)
+{
+	__asm_flush_dcache_range(start, stop);
+}
+
+/*
+ * Flush range(clean & invalidate) from all levels of D-cache/unified cache
+ */
+void flush_dcache_range(unsigned long start, unsigned long stop)
+{
+	__asm_flush_dcache_range(start, stop);
+}
+
+void dcache_enable(void)
+{
+	/* The data cache is not active unless the mmu is enabled */
+	if (!(get_sctlr() & CR_M)) {
+		invalidate_dcache_all();
+		__asm_invalidate_tlb_all();
+		mmu_setup();
+	}
+
+	set_sctlr(get_sctlr() | CR_C);
+}
+
+void dcache_disable(void)
+{
+	uint32_t sctlr;
+
+	sctlr = get_sctlr();
+
+	/* if cache isn't enabled no need to disable */
+	if (!(sctlr & CR_C))
+		return;
+
+	set_sctlr(sctlr & ~(CR_C|CR_M));
+
+	flush_dcache_all();
+	__asm_invalidate_tlb_all();
+}
+
+int dcache_status(void)
+{
+	return (get_sctlr() & CR_C) != 0;
+}
+
+#else	/* CONFIG_SYS_DCACHE_OFF */
+
+void invalidate_dcache_all(void)
+{
+}
+
+void flush_dcache_all(void)
+{
+}
+
+void invalidate_dcache_range(unsigned long start, unsigned long stop)
+{
+}
+
+void flush_dcache_range(unsigned long start, unsigned long stop)
+{
+}
+
+void dcache_enable(void)
+{
+}
+
+void dcache_disable(void)
+{
+}
+
+int dcache_status(void)
+{
+	return 0;
+}
+
+#endif	/* CONFIG_SYS_DCACHE_OFF */
+
+#ifndef CONFIG_SYS_ICACHE_OFF
+
+void icache_enable(void)
+{
+	__asm_invalidate_icache_all();
+	set_sctlr(get_sctlr() | CR_I);
+}
+
+void icache_disable(void)
+{
+	set_sctlr(get_sctlr() & ~CR_I);
+}
+
+int icache_status(void)
+{
+	return (get_sctlr() & CR_I) != 0;
+}
+
+void invalidate_icache_all(void)
+{
+	__asm_invalidate_icache_all();
+}
+
+#else	/* CONFIG_SYS_ICACHE_OFF */
+
+void icache_enable(void)
+{
+}
+
+void icache_disable(void)
+{
+}
+
+int icache_status(void)
+{
+	return 0;
+}
+
+void invalidate_icache_all(void)
+{
+}
+
+#endif	/* CONFIG_SYS_ICACHE_OFF */
+
+/*
+ * Enable dCache & iCache, whether cache is actually enabled
+ * depend on CONFIG_SYS_DCACHE_OFF and CONFIG_SYS_ICACHE_OFF
+ */
+void enable_caches(void)
+{
+	icache_enable();
+	dcache_enable();
+}
+
+/*
+ * Flush range from all levels of d-cache/unified-cache
+ */
+void flush_cache(unsigned long start, unsigned long size)
+{
+	flush_dcache_range(start, start + size);
+}
diff --git a/arch/arm/cpu/armv8/config.mk b/arch/arm/cpu/armv8/config.mk
new file mode 100644
index 0000000000..f5b95591af
--- /dev/null
+++ b/arch/arm/cpu/armv8/config.mk
@@ -0,0 +1,12 @@
+#
+# (C) Copyright 2002
+# Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+PLATFORM_RELFLAGS += -fno-common -ffixed-x18
+
+PF_CPPFLAGS_ARMV8 := $(call cc-option, -march=armv8-a)
+PF_NO_UNALIGNED := $(call cc-option, -mstrict-align)
+PLATFORM_CPPFLAGS += $(PF_CPPFLAGS_ARMV8)
+PLATFORM_CPPFLAGS += $(PF_NO_UNALIGNED)
diff --git a/arch/arm/cpu/armv8/cpu.c b/arch/arm/cpu/armv8/cpu.c
new file mode 100644
index 0000000000..e06c3cc04d
--- /dev/null
+++ b/arch/arm/cpu/armv8/cpu.c
@@ -0,0 +1,43 @@
+/*
+ * (C) Copyright 2008 Texas Insturments
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <command.h>
+#include <asm/system.h>
+#include <linux/compiler.h>
+
+int cleanup_before_linux(void)
+{
+	/*
+	 * this function is called just before we call linux
+	 * it prepares the processor for linux
+	 *
+	 * disable interrupt and turn off caches etc ...
+	 */
+	disable_interrupts();
+
+	/*
+	 * Turn off I-cache and invalidate it
+	 */
+	icache_disable();
+	invalidate_icache_all();
+
+	/*
+	 * turn off D-cache
+	 * dcache_disable() in turn flushes the d-cache and disables MMU
+	 */
+	dcache_disable();
+	invalidate_dcache_all();
+
+	return 0;
+}
diff --git a/arch/arm/cpu/armv8/exceptions.S b/arch/arm/cpu/armv8/exceptions.S
new file mode 100644
index 0000000000..b91a1b662f
--- /dev/null
+++ b/arch/arm/cpu/armv8/exceptions.S
@@ -0,0 +1,113 @@
+/*
+ * (C) Copyright 2013
+ * David Feng <fenghua@phytium.com.cn>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <asm-offsets.h>
+#include <config.h>
+#include <version.h>
+#include <asm/ptrace.h>
+#include <asm/macro.h>
+#include <linux/linkage.h>
+
+/*
+ * Enter Exception.
+ * This will save the processor state that is ELR/X0~X30
+ * to the stack frame.
+ */
+.macro	exception_entry
+	stp	x29, x30, [sp, #-16]!
+	stp	x27, x28, [sp, #-16]!
+	stp	x25, x26, [sp, #-16]!
+	stp	x23, x24, [sp, #-16]!
+	stp	x21, x22, [sp, #-16]!
+	stp	x19, x20, [sp, #-16]!
+	stp	x17, x18, [sp, #-16]!
+	stp	x15, x16, [sp, #-16]!
+	stp	x13, x14, [sp, #-16]!
+	stp	x11, x12, [sp, #-16]!
+	stp	x9, x10, [sp, #-16]!
+	stp	x7, x8, [sp, #-16]!
+	stp	x5, x6, [sp, #-16]!
+	stp	x3, x4, [sp, #-16]!
+	stp	x1, x2, [sp, #-16]!
+
+	/* Could be running at EL3/EL2/EL1 */
+	switch_el x11, 3f, 2f, 1f
+3:	mrs	x1, esr_el3
+	mrs	x2, elr_el3
+	b	0f
+2:	mrs	x1, esr_el2
+	mrs	x2, elr_el2
+	b	0f
+1:	mrs	x1, esr_el1
+	mrs	x2, elr_el1
+0:
+	stp	x2, x0, [sp, #-16]!
+	mov	x0, sp
+.endm
+
+/*
+ * Exception vectors.
+ */
+	.align	11
+	.globl	vectors
+vectors:
+	.align	7
+	b	_do_bad_sync	/* Current EL Synchronous Thread */
+
+	.align	7
+	b	_do_bad_irq	/* Current EL IRQ Thread */
+
+	.align	7
+	b	_do_bad_fiq	/* Current EL FIQ Thread */
+
+	.align	7
+	b	_do_bad_error	/* Current EL Error Thread */
+
+	.align	7
+	b	_do_sync	/* Current EL Synchronous Handler */
+
+	.align	7
+	b	_do_irq		/* Current EL IRQ Handler */
+
+	.align	7
+	b	_do_fiq		/* Current EL FIQ Handler */
+
+	.align	7
+	b	_do_error	/* Current EL Error Handler */
+
+
+_do_bad_sync:
+	exception_entry
+	bl	do_bad_sync
+
+_do_bad_irq:
+	exception_entry
+	bl	do_bad_irq
+
+_do_bad_fiq:
+	exception_entry
+	bl	do_bad_fiq
+
+_do_bad_error:
+	exception_entry
+	bl	do_bad_error
+
+_do_sync:
+	exception_entry
+	bl	do_sync
+
+_do_irq:
+	exception_entry
+	bl	do_irq
+
+_do_fiq:
+	exception_entry
+	bl	do_fiq
+
+_do_error:
+	exception_entry
+	bl	do_error
diff --git a/arch/arm/cpu/armv8/generic_timer.c b/arch/arm/cpu/armv8/generic_timer.c
new file mode 100644
index 0000000000..223b95e210
--- /dev/null
+++ b/arch/arm/cpu/armv8/generic_timer.c
@@ -0,0 +1,31 @@
+/*
+ * (C) Copyright 2013
+ * David Feng <fenghua@phytium.com.cn>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <command.h>
+#include <asm/system.h>
+
+/*
+ * Generic timer implementation of get_tbclk()
+ */
+unsigned long get_tbclk(void)
+{
+	unsigned long cntfrq;
+	asm volatile("mrs %0, cntfrq_el0" : "=r" (cntfrq));
+	return cntfrq;
+}
+
+/*
+ * Generic timer implementation of timer_read_counter()
+ */
+unsigned long timer_read_counter(void)
+{
+	unsigned long cntpct;
+	isb();
+	asm volatile("mrs %0, cntpct_el0" : "=r" (cntpct));
+	return cntpct;
+}
diff --git a/arch/arm/cpu/armv8/start.S b/arch/arm/cpu/armv8/start.S
new file mode 100644
index 0000000000..33d3f3688a
--- /dev/null
+++ b/arch/arm/cpu/armv8/start.S
@@ -0,0 +1,170 @@
+/*
+ * (C) Copyright 2013
+ * David Feng <fenghua@phytium.com.cn>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <asm-offsets.h>
+#include <config.h>
+#include <version.h>
+#include <linux/linkage.h>
+#include <asm/macro.h>
+#include <asm/armv8/mmu.h>
+
+/*************************************************************************
+ *
+ * Startup Code (reset vector)
+ *
+ *************************************************************************/
+
+.globl	_start
+_start:
+	b	reset
+
+	.align 3
+
+.globl	_TEXT_BASE
+_TEXT_BASE:
+	.quad	CONFIG_SYS_TEXT_BASE
+
+/*
+ * These are defined in the linker script.
+ */
+.globl	_end_ofs
+_end_ofs:
+	.quad	_end - _start
+
+.globl	_bss_start_ofs
+_bss_start_ofs:
+	.quad	__bss_start - _start
+
+.globl	_bss_end_ofs
+_bss_end_ofs:
+	.quad	__bss_end - _start
+
+reset:
+	/*
+	 * Could be EL3/EL2/EL1, Initial State:
+	 * Little Endian, MMU Disabled, i/dCache Disabled
+	 */
+	adr	x0, vectors
+	switch_el x1, 3f, 2f, 1f
+3:	mrs	x0, scr_el3
+	orr	x0, x0, #0xf			/* SCR_EL3.NS|IRQ|FIQ|EA */
+	msr	scr_el3, x0
+	msr	vbar_el3, x0
+	msr	cptr_el3, xzr			/* Enable FP/SIMD */
+	ldr	x0, =COUNTER_FREQUENCY
+	msr	cntfrq_el0, x0			/* Initialize CNTFRQ */
+	b	0f
+2:	msr	vbar_el2, x0
+	mov	x0, #0x33ff
+	msr	cptr_el2, x0			/* Enable FP/SIMD */
+	b	0f
+1:	msr	vbar_el1, x0
+	mov	x0, #3 << 20
+	msr	cpacr_el1, x0			/* Enable FP/SIMD */
+0:
+
+	/*
+	 * Cache/BPB/TLB Invalidate
+	 * i-cache is invalidated before enabled in icache_enable()
+	 * tlb is invalidated before mmu is enabled in dcache_enable()
+	 * d-cache is invalidated before enabled in dcache_enable()
+	 */
+
+	/* Processor specific initialization */
+	bl	lowlevel_init
+
+	branch_if_master x0, x1, master_cpu
+
+	/*
+	 * Slave CPUs
+	 */
+slave_cpu:
+	wfe
+	ldr	x1, =CPU_RELEASE_ADDR
+	ldr	x0, [x1]
+	cbz	x0, slave_cpu
+	br	x0			/* branch to the given address */
+
+	/*
+	 * Master CPU
+	 */
+master_cpu:
+	bl	_main
+
+/*-----------------------------------------------------------------------*/
+
+WEAK(lowlevel_init)
+	mov	x29, lr			/* Save LR */
+
+#if defined(CONFIG_GICV2) || defined(CONFIG_GICV3)
+	branch_if_slave x0, 1f
+	ldr	x0, =GICD_BASE
+	bl	gic_init_secure
+1:
+#if defined(CONFIG_GICV3)
+	ldr	x0, =GICR_BASE
+	bl	gic_init_secure_percpu
+#elif defined(CONFIG_GICV2)
+	ldr	x0, =GICD_BASE
+	ldr	x1, =GICC_BASE
+	bl	gic_init_secure_percpu
+#endif
+#endif
+
+	branch_if_master x0, x1, 2f
+
+	/*
+	 * Slave should wait for master clearing spin table.
+	 * This sync prevent salves observing incorrect
+	 * value of spin table and jumping to wrong place.
+	 */
+#if defined(CONFIG_GICV2) || defined(CONFIG_GICV3)
+#ifdef CONFIG_GICV2
+	ldr	x0, =GICC_BASE
+#endif
+	bl	gic_wait_for_interrupt
+#endif
+
+	/*
+	 * All slaves will enter EL2 and optionally EL1.
+	 */
+	bl	armv8_switch_to_el2
+#ifdef CONFIG_ARMV8_SWITCH_TO_EL1
+	bl	armv8_switch_to_el1
+#endif
+
+2:
+	mov	lr, x29			/* Restore LR */
+	ret
+ENDPROC(lowlevel_init)
+
+WEAK(smp_kick_all_cpus)
+	/* Kick secondary cpus up by SGI 0 interrupt */
+	mov	x29, lr			/* Save LR */
+#if defined(CONFIG_GICV2) || defined(CONFIG_GICV3)
+	ldr	x0, =GICD_BASE
+	bl	gic_kick_secondary_cpus
+#endif
+	mov	lr, x29			/* Restore LR */
+	ret
+ENDPROC(smp_kick_all_cpus)
+
+/*-----------------------------------------------------------------------*/
+
+ENTRY(c_runtime_cpu_setup)
+	/* Relocate vBAR */
+	adr	x0, vectors
+	switch_el x1, 3f, 2f, 1f
+3:	msr	vbar_el3, x0
+	b	0f
+2:	msr	vbar_el2, x0
+	b	0f
+1:	msr	vbar_el1, x0
+0:
+
+	ret
+ENDPROC(c_runtime_cpu_setup)
diff --git a/arch/arm/cpu/armv8/tlb.S b/arch/arm/cpu/armv8/tlb.S
new file mode 100644
index 0000000000..f840b04df5
--- /dev/null
+++ b/arch/arm/cpu/armv8/tlb.S
@@ -0,0 +1,34 @@
+/*
+ * (C) Copyright 2013
+ * David Feng <fenghua@phytium.com.cn>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <asm-offsets.h>
+#include <config.h>
+#include <version.h>
+#include <linux/linkage.h>
+#include <asm/macro.h>
+
+/*
+ * void __asm_invalidate_tlb_all(void)
+ *
+ * invalidate all tlb entries.
+ */
+ENTRY(__asm_invalidate_tlb_all)
+	switch_el x9, 3f, 2f, 1f
+3:	tlbi	alle3
+	dsb	sy
+	isb
+	b	0f
+2:	tlbi	alle2
+	dsb	sy
+	isb
+	b	0f
+1:	tlbi	vmalle1
+	dsb	sy
+	isb
+0:
+	ret
+ENDPROC(__asm_invalidate_tlb_all)
diff --git a/arch/arm/cpu/armv8/transition.S b/arch/arm/cpu/armv8/transition.S
new file mode 100644
index 0000000000..e0a5946009
--- /dev/null
+++ b/arch/arm/cpu/armv8/transition.S
@@ -0,0 +1,83 @@
+/*
+ * (C) Copyright 2013
+ * David Feng <fenghua@phytium.com.cn>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <asm-offsets.h>
+#include <config.h>
+#include <version.h>
+#include <linux/linkage.h>
+#include <asm/macro.h>
+
+ENTRY(armv8_switch_to_el2)
+	switch_el x0, 1f, 0f, 0f
+0:	ret
+1:
+	mov	x0, #0x5b1	/* Non-secure EL0/EL1 | HVC | 64bit EL2 */
+	msr	scr_el3, x0
+	msr	cptr_el3, xzr	/* Disable coprocessor traps to EL3 */
+	mov	x0, #0x33ff
+	msr	cptr_el2, x0	/* Disable coprocessor traps to EL2 */
+
+	/* Initialize SCTLR_EL2 */
+	msr	sctlr_el2, xzr
+
+	/* Return to the EL2_SP2 mode from EL3 */
+	mov	x0, sp
+	msr	sp_el2, x0	/* Migrate SP */
+	mrs	x0, vbar_el3
+	msr	vbar_el2, x0	/* Migrate VBAR */
+	mov	x0, #0x3c9
+	msr	spsr_el3, x0	/* EL2_SP2 | D | A | I | F */
+	msr	elr_el3, lr
+	eret
+ENDPROC(armv8_switch_to_el2)
+
+ENTRY(armv8_switch_to_el1)
+	switch_el x0, 0f, 1f, 0f
+0:	ret
+1:
+	/* Initialize Generic Timers */
+	mrs	x0, cnthctl_el2
+	orr	x0, x0, #0x3		/* Enable EL1 access to timers */
+	msr	cnthctl_el2, x0
+	msr	cntvoff_el2, x0
+	mrs	x0, cntkctl_el1
+	orr	x0, x0, #0x3		/* Enable EL0 access to timers */
+	msr	cntkctl_el1, x0
+
+	/* Initilize MPID/MPIDR registers */
+	mrs	x0, midr_el1
+	mrs	x1, mpidr_el1
+	msr	vpidr_el2, x0
+	msr	vmpidr_el2, x1
+
+	/* Disable coprocessor traps */
+	mov	x0, #0x33ff
+	msr	cptr_el2, x0		/* Disable coprocessor traps to EL2 */
+	msr	hstr_el2, xzr		/* Disable coprocessor traps to EL2 */
+	mov	x0, #3 << 20
+	msr	cpacr_el1, x0		/* Enable FP/SIMD at EL1 */
+
+	/* Initialize HCR_EL2 */
+	mov	x0, #(1 << 31)		/* 64bit EL1 */
+	orr	x0, x0, #(1 << 29)	/* Disable HVC */
+	msr	hcr_el2, x0
+
+	/* SCTLR_EL1 initialization */
+	mov	x0, #0x0800
+	movk	x0, #0x30d0, lsl #16
+	msr	sctlr_el1, x0
+
+	/* Return to the EL1_SP1 mode from EL2 */
+	mov	x0, sp
+	msr	sp_el1, x0		/* Migrate SP */
+	mrs	x0, vbar_el2
+	msr	vbar_el1, x0		/* Migrate VBAR */
+	mov	x0, #0x3c5
+	msr	spsr_el2, x0		/* EL1_SP1 | D | A | I | F */
+	msr	elr_el2, lr
+	eret
+ENDPROC(armv8_switch_to_el1)
diff --git a/arch/arm/cpu/armv8/u-boot.lds b/arch/arm/cpu/armv8/u-boot.lds
new file mode 100644
index 0000000000..4c12222370
--- /dev/null
+++ b/arch/arm/cpu/armv8/u-boot.lds
@@ -0,0 +1,89 @@
+/*
+ * (C) Copyright 2013
+ * David Feng <fenghua@phytium.com.cn>
+ *
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+OUTPUT_FORMAT("elf64-littleaarch64", "elf64-littleaarch64", "elf64-littleaarch64")
+OUTPUT_ARCH(aarch64)
+ENTRY(_start)
+SECTIONS
+{
+	. = 0x00000000;
+
+	. = ALIGN(8);
+	.text :
+	{
+		*(.__image_copy_start)
+		CPUDIR/start.o (.text*)
+		*(.text*)
+	}
+
+	. = ALIGN(8);
+	.rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
+
+	. = ALIGN(8);
+	.data : {
+		*(.data*)
+	}
+
+	. = ALIGN(8);
+
+	. = .;
+
+	. = ALIGN(8);
+	.u_boot_list : {
+		KEEP(*(SORT(.u_boot_list*)));
+	}
+
+	. = ALIGN(8);
+
+	.image_copy_end :
+	{
+		*(.__image_copy_end)
+	}
+
+	. = ALIGN(8);
+
+	.rel_dyn_start :
+	{
+		*(.__rel_dyn_start)
+	}
+
+	.rela.dyn : {
+		*(.rela*)
+	}
+
+	.rel_dyn_end :
+	{
+		*(.__rel_dyn_end)
+	}
+
+	_end = .;
+
+	. = ALIGN(8);
+
+	.bss_start : {
+		KEEP(*(.__bss_start));
+	}
+
+	.bss : {
+		*(.bss*)
+		 . = ALIGN(8);
+	}
+
+	.bss_end : {
+		KEEP(*(.__bss_end));
+	}
+
+	/DISCARD/ : { *(.dynsym) }
+	/DISCARD/ : { *(.dynstr*) }
+	/DISCARD/ : { *(.dynamic*) }
+	/DISCARD/ : { *(.plt*) }
+	/DISCARD/ : { *(.interp*) }
+	/DISCARD/ : { *(.gnu*) }
+}
diff --git a/arch/arm/cpu/at91-common/Makefile b/arch/arm/cpu/at91-common/Makefile
new file mode 100644
index 0000000000..5b978384eb
--- /dev/null
+++ b/arch/arm/cpu/at91-common/Makefile
@@ -0,0 +1,12 @@
+#
+# (C) Copyright 2000-2008
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# (C) Copyright 2013 Atmel Corporation
+#		     Bo Shen <voice.shen@atmel.com>
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-$(CONFIG_AT91_WANTS_COMMON_PHY) += phy.o
+obj-$(CONFIG_SPL_BUILD) += mpddrc.o spl.o
diff --git a/arch/arm/cpu/at91-common/mpddrc.c b/arch/arm/cpu/at91-common/mpddrc.c
new file mode 100644
index 0000000000..8136396403
--- /dev/null
+++ b/arch/arm/cpu/at91-common/mpddrc.c
@@ -0,0 +1,124 @@
+/*
+ * Copyright (C) 2013 Atmel Corporation
+ *		      Bo Shen <voice.shen@atmel.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/atmel_mpddrc.h>
+
+static inline void atmel_mpddr_op(int mode, u32 ram_address)
+{
+	struct atmel_mpddr *mpddr = (struct atmel_mpddr *)ATMEL_BASE_MPDDRC;
+
+	writel(mode, &mpddr->mr);
+	writel(0, ram_address);
+}
+
+int ddr2_init(const unsigned int ram_address,
+	      const struct atmel_mpddr *mpddr_value)
+{
+	struct atmel_mpddr *mpddr = (struct atmel_mpddr *)ATMEL_BASE_MPDDRC;
+	u32 ba_off, cr;
+
+	/* Compute bank offset according to NC in configuration register */
+	ba_off = (mpddr_value->cr & ATMEL_MPDDRC_CR_NC_MASK) + 9;
+	if (!(mpddr_value->cr & ATMEL_MPDDRC_CR_DECOD_INTERLEAVED))
+		ba_off += ((mpddr->cr & ATMEL_MPDDRC_CR_NR_MASK) >> 2) + 11;
+
+	ba_off += (mpddr_value->md & ATMEL_MPDDRC_MD_DBW_MASK) ? 1 : 2;
+
+	/* Program the memory device type into the memory device register */
+	writel(mpddr_value->md, &mpddr->md);
+
+	/* Program the configuration register */
+	writel(mpddr_value->cr, &mpddr->cr);
+
+	/* Program the timing register */
+	writel(mpddr_value->tpr0, &mpddr->tpr0);
+	writel(mpddr_value->tpr1, &mpddr->tpr1);
+	writel(mpddr_value->tpr2, &mpddr->tpr2);
+
+	/* Issue a NOP command */
+	atmel_mpddr_op(ATMEL_MPDDRC_MR_MODE_NOP_CMD, ram_address);
+
+	/* A 200 us is provided to precede any signal toggle */
+	udelay(200);
+
+	/* Issue a NOP command */
+	atmel_mpddr_op(ATMEL_MPDDRC_MR_MODE_NOP_CMD, ram_address);
+
+	/* Issue an all banks precharge command */
+	atmel_mpddr_op(ATMEL_MPDDRC_MR_MODE_PRCGALL_CMD, ram_address);
+
+	/* Issue an extended mode register set(EMRS2) to choose operation */
+	atmel_mpddr_op(ATMEL_MPDDRC_MR_MODE_EXT_LMR_CMD,
+		       ram_address + (0x2 << ba_off));
+
+	/* Issue an extended mode register set(EMRS3) to set EMSR to 0 */
+	atmel_mpddr_op(ATMEL_MPDDRC_MR_MODE_EXT_LMR_CMD,
+		       ram_address + (0x3 << ba_off));
+
+	/*
+	 * Issue an extended mode register set(EMRS1) to enable DLL and
+	 * program D.I.C (output driver impedance control)
+	 */
+	atmel_mpddr_op(ATMEL_MPDDRC_MR_MODE_EXT_LMR_CMD,
+		       ram_address + (0x1 << ba_off));
+
+	/* Enable DLL reset */
+	cr = readl(&mpddr->cr);
+	writel(cr | ATMEL_MPDDRC_CR_DLL_RESET_ENABLED, &mpddr->cr);
+
+	/* A mode register set(MRS) cycle is issued to reset DLL */
+	atmel_mpddr_op(ATMEL_MPDDRC_MR_MODE_LMR_CMD, ram_address);
+
+	/* Issue an all banks precharge command */
+	atmel_mpddr_op(ATMEL_MPDDRC_MR_MODE_PRCGALL_CMD, ram_address);
+
+	/* Two auto-refresh (CBR) cycles are provided */
+	atmel_mpddr_op(ATMEL_MPDDRC_MR_MODE_RFSH_CMD, ram_address);
+	atmel_mpddr_op(ATMEL_MPDDRC_MR_MODE_RFSH_CMD, ram_address);
+
+	/* Disable DLL reset */
+	cr = readl(&mpddr->cr);
+	writel(cr & (~ATMEL_MPDDRC_CR_DLL_RESET_ENABLED), &mpddr->cr);
+
+	/* A mode register set (MRS) cycle is issued to disable DLL reset */
+	atmel_mpddr_op(ATMEL_MPDDRC_MR_MODE_LMR_CMD, ram_address);
+
+	/* Set OCD calibration in default state */
+	cr = readl(&mpddr->cr);
+	writel(cr | ATMEL_MPDDRC_CR_OCD_DEFAULT, &mpddr->cr);
+
+	/*
+	 * An extended mode register set (EMRS1) cycle is issued
+	 * to OCD default value
+	 */
+	atmel_mpddr_op(ATMEL_MPDDRC_MR_MODE_EXT_LMR_CMD,
+		       ram_address + (0x1 << ba_off));
+
+	 /* OCD calibration mode exit */
+	cr = readl(&mpddr->cr);
+	writel(cr & (~ATMEL_MPDDRC_CR_OCD_DEFAULT), &mpddr->cr);
+
+	/*
+	 * An extended mode register set (EMRS1) cycle is issued
+	 * to enable OCD exit
+	 */
+	atmel_mpddr_op(ATMEL_MPDDRC_MR_MODE_EXT_LMR_CMD,
+		       ram_address + (0x1 << ba_off));
+
+	/* A nornal mode command is provided */
+	atmel_mpddr_op(ATMEL_MPDDRC_MR_MODE_NORMAL_CMD, ram_address);
+
+	/* Perform a write access to any DDR2-SDRAM address */
+	writel(0, ram_address);
+
+	/* Write the refresh rate */
+	writel(mpddr_value->rtr, &mpddr->rtr);
+
+	return 0;
+}
diff --git a/arch/arm/cpu/at91-common/phy.c b/arch/arm/cpu/at91-common/phy.c
new file mode 100644
index 0000000000..2cba7169e4
--- /dev/null
+++ b/arch/arm/cpu/at91-common/phy.c
@@ -0,0 +1,57 @@
+/*
+ * (C) Copyright 2007-2008
+ * Stelian Pop <stelian@popies.net>
+ * Lead Tech Design <www.leadtechdesign.com>
+ *
+ * (C) Copyright 2012
+ * Markus Hubig <mhubig@imko.de>
+ * IMKO GmbH <www.imko.de>
+ *
+ * Copyright (C) 2013 DENX Software Engineering, hs@denx.de
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <linux/sizes.h>
+#include <asm/arch/at91_pmc.h>
+#include <asm/arch/at91_rstc.h>
+#include <watchdog.h>
+
+void at91_phy_reset(void)
+{
+	unsigned long erstl;
+	unsigned long start = get_timer(0);
+	unsigned long const timeout = 1000; /* 1000ms */
+	at91_rstc_t *rstc = (at91_rstc_t *)ATMEL_BASE_RSTC;
+
+	erstl = readl(&rstc->mr) & AT91_RSTC_MR_ERSTL_MASK;
+
+	/*
+	 * Need to reset PHY -> 500ms reset
+	 * Reset PHY by pulling the NRST line for 500ms to low. To do so
+	 * disable user reset for low level on NRST pin and poll the NRST
+	 * level in reset status register.
+	 */
+	writel(AT91_RSTC_KEY | AT91_RSTC_MR_ERSTL(0x0D) |
+		AT91_RSTC_MR_URSTEN, &rstc->mr);
+
+	writel(AT91_RSTC_KEY | AT91_RSTC_CR_EXTRST, &rstc->cr);
+
+	/* Wait for end of hardware reset */
+	while (!(readl(&rstc->sr) & AT91_RSTC_SR_NRSTL)) {
+		/* avoid shutdown by watchdog */
+		WATCHDOG_RESET();
+		mdelay(10);
+
+		/* timeout for not getting stuck in an endless loop */
+		if (get_timer(start) >= timeout) {
+			puts("*** ERROR: Timeout waiting for PHY reset!\n");
+			break;
+		}
+	};
+
+	/* Restore NRST value */
+	writel(AT91_RSTC_KEY | erstl | AT91_RSTC_MR_URSTEN, &rstc->mr);
+}
diff --git a/arch/arm/cpu/at91-common/spl.c b/arch/arm/cpu/at91-common/spl.c
new file mode 100644
index 0000000000..7f4debb912
--- /dev/null
+++ b/arch/arm/cpu/at91-common/spl.c
@@ -0,0 +1,94 @@
+/*
+ * Copyright (C) 2013 Atmel Corporation
+ *		      Bo Shen <voice.shen@atmel.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/at91_common.h>
+#include <asm/arch/at91_pmc.h>
+#include <asm/arch/at91_wdt.h>
+#include <asm/arch/clk.h>
+#include <spl.h>
+
+static void at91_disable_wdt(void)
+{
+	struct at91_wdt *wdt = (struct at91_wdt *)ATMEL_BASE_WDT;
+
+	writel(AT91_WDT_MR_WDDIS, &wdt->mr);
+}
+
+void at91_plla_init(u32 pllar)
+{
+	struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
+
+	writel(pllar, &pmc->pllar);
+	while (!(readl(&pmc->sr) & (AT91_PMC_LOCKA | AT91_PMC_MCKRDY)))
+		;
+}
+
+void at91_mck_init(u32 mckr)
+{
+	struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
+	u32 tmp;
+
+	tmp = readl(&pmc->mckr);
+	tmp &= ~(AT91_PMC_MCKR_PRES_MASK |
+		 AT91_PMC_MCKR_MDIV_MASK |
+		 AT91_PMC_MCKR_PLLADIV_2);
+	tmp |= mckr & (AT91_PMC_MCKR_PRES_MASK |
+		       AT91_PMC_MCKR_MDIV_MASK |
+		       AT91_PMC_MCKR_PLLADIV_2);
+	writel(tmp, &pmc->mckr);
+
+	while (!(readl(&pmc->sr) & AT91_PMC_MCKRDY))
+		;
+}
+
+
+u32 spl_boot_device(void)
+{
+#ifdef CONFIG_SYS_USE_MMC
+	return BOOT_DEVICE_MMC1;
+#elif CONFIG_SYS_USE_NANDFLASH
+	return BOOT_DEVICE_NAND;
+#elif CONFIG_SYS_USE_SERIALFLASH
+	return BOOT_DEVICE_SPI;
+#endif
+	return BOOT_DEVICE_NONE;
+}
+
+u32 spl_boot_mode(void)
+{
+	switch (spl_boot_device()) {
+#ifdef CONFIG_SYS_USE_MMC
+	case BOOT_DEVICE_MMC1:
+		return MMCSD_MODE_FAT;
+		break;
+#endif
+	case BOOT_DEVICE_NONE:
+	default:
+		hang();
+	}
+}
+
+void s_init(void)
+{
+	/* disable watchdog */
+	at91_disable_wdt();
+
+	/* PMC configuration */
+	at91_pmc_init();
+
+	at91_clock_init(CONFIG_SYS_AT91_MAIN_CLOCK);
+
+	timer_init();
+
+	board_early_init_f();
+
+	preloader_console_init();
+
+	mem_init();
+}
diff --git a/arch/arm/cpu/at91-common/u-boot-spl.lds b/arch/arm/cpu/at91-common/u-boot-spl.lds
new file mode 100644
index 0000000000..57ac1eb242
--- /dev/null
+++ b/arch/arm/cpu/at91-common/u-boot-spl.lds
@@ -0,0 +1,54 @@
+/*
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
+ *
+ * (C) Copyright 2010
+ * Texas Instruments, <www.ti.com>
+ *	Aneesh V <aneesh@ti.com>
+ *
+ * (C) 2013 Atmel Corporation
+ *	    Bo Shen <voice.shen@atmel.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+MEMORY { .sram : ORIGIN = CONFIG_SPL_TEXT_BASE, \
+		LENGTH = CONFIG_SPL_MAX_SIZE }
+MEMORY { .sdram : ORIGIN = CONFIG_SPL_BSS_START_ADDR, \
+		LENGTH = CONFIG_SPL_BSS_MAX_SIZE }
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+	.text      :
+	{
+		__start = .;
+		arch/arm/cpu/armv7/start.o	(.text*)
+		*(.text*)
+	} >.sram
+
+	. = ALIGN(4);
+	.rodata : { *(SORT_BY_ALIGNMENT(.rodata*)) } >.sram
+
+	. = ALIGN(4);
+	.data : { *(SORT_BY_ALIGNMENT(.data*)) } >.sram
+
+	. = ALIGN(4);
+	__image_copy_end = .;
+
+	.end :
+	{
+		*(.__end)
+	} >.sram
+
+	.bss :
+	{
+		. = ALIGN(4);
+		__bss_start = .;
+		*(.bss*)
+		. = ALIGN(4);
+		__bss_end = .;
+	} >.sdram
+}
diff --git a/arch/arm/cpu/ixp/Makefile b/arch/arm/cpu/ixp/Makefile
deleted file mode 100644
index 788598ec78..0000000000
--- a/arch/arm/cpu/ixp/Makefile
+++ /dev/null
@@ -1,34 +0,0 @@
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(CPU).o
-
-START	= start.o
-
-COBJS-y	+= cpu.o
-COBJS-$(CONFIG_USE_IRQ)	+= interrupts.o
-COBJS-y	+= timer.o
-
-SRCS	:= $(START:.o=.S) $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
-OBJS	:= $(addprefix $(obj),$(SOBJS-y) $(COBJS-y))
-START	:= $(addprefix $(obj),$(START))
-
-all:	$(obj).depend $(START) $(LIB)
-
-$(LIB):	$(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
diff --git a/arch/arm/cpu/ixp/config.mk b/arch/arm/cpu/ixp/config.mk
deleted file mode 100644
index fd47c60939..0000000000
--- a/arch/arm/cpu/ixp/config.mk
+++ /dev/null
@@ -1,24 +0,0 @@
-#
-# (C) Copyright 2002
-# Sysgo Real-Time Solutions, GmbH <www.elinos.com>
-# Marius Groeger <mgroeger@sysgo.de>
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-BIG_ENDIAN = y
-
-PLATFORM_RELFLAGS += -mbig-endian
-
-PLATFORM_CPPFLAGS += -mbig-endian -march=armv5te -mtune=strongarm1100
-
-PLATFORM_LDFLAGS += -EB
-USE_PRIVATE_LIBGCC = yes
-
-# =========================================================================
-#
-# Supply options according to compiler version
-#
-# =========================================================================
-PF_RELFLAGS_SLB_AT := $(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,))
-PLATFORM_RELFLAGS += $(PF_RELFLAGS_SLB_AT)
diff --git a/arch/arm/cpu/ixp/cpu.c b/arch/arm/cpu/ixp/cpu.c
deleted file mode 100644
index 4387c18d3d..0000000000
--- a/arch/arm/cpu/ixp/cpu.c
+++ /dev/null
@@ -1,100 +0,0 @@
-/*
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Alex Zuepke <azu@sysgo.de>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-/*
- * CPU specific code
- */
-
-#include <common.h>
-#include <command.h>
-#include <netdev.h>
-#include <asm/arch/ixp425.h>
-#include <asm/system.h>
-
-static void cache_flush(void);
-
-#if defined(CONFIG_DISPLAY_CPUINFO)
-int print_cpuinfo (void)
-{
-	unsigned long id;
-	int speed = 0;
-
-	asm ("mrc p15, 0, %0, c0, c0, 0":"=r" (id));
-
-	puts("CPU:   Intel IXP425 at ");
-	switch ((id & 0x000003f0) >> 4) {
-	case 0x1c:
-		speed = 533;
-		break;
-
-	case 0x1d:
-		speed = 400;
-		break;
-
-	case 0x1f:
-		speed = 266;
-		break;
-	}
-
-	if (speed)
-		printf("%d MHz\n", speed);
-	else
-		puts("unknown revision\n");
-
-	return 0;
-}
-#endif /* CONFIG_DISPLAY_CPUINFO */
-
-int cleanup_before_linux (void)
-{
-	/*
-	 * this function is called just before we call linux
-	 * it prepares the processor for linux
-	 *
-	 * just disable everything that can disturb booting linux
-	 */
-
-	disable_interrupts ();
-
-	/* turn off I-cache */
-	icache_disable();
-	dcache_disable();
-
-	/* flush I-cache */
-	cache_flush();
-
-	return 0;
-}
-
-/* flush I/D-cache */
-static void cache_flush (void)
-{
-	unsigned long i = 0;
-
-	asm ("mcr p15, 0, %0, c7, c5, 0": :"r" (i));
-}
-
-/* FIXME */
-/*
-void pci_init(void)
-{
-	return;
-}
-*/
-
-int cpu_eth_init(bd_t *bis)
-{
-#ifdef CONFIG_IXP4XX_NPE
-	npe_initialize(bis);
-#endif
-	return 0;
-}
diff --git a/arch/arm/cpu/ixp/interrupts.c b/arch/arm/cpu/ixp/interrupts.c
deleted file mode 100644
index 7694c6a6cc..0000000000
--- a/arch/arm/cpu/ixp/interrupts.c
+++ /dev/null
@@ -1,66 +0,0 @@
-/*
- * (C) Copyright 2006
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Alex Zuepke <azu@sysgo.de>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/arch/ixp425.h>
-#include <asm/proc-armv/ptrace.h>
-
-struct _irq_handler {
-	void                *m_data;
-	void (*m_func)( void *data);
-};
-
-static struct _irq_handler IRQ_HANDLER[N_IRQS];
-
-static void default_isr(void *data)
-{
-	printf("default_isr():  called for IRQ %d, Interrupt Status=%x PR=%x\n",
-	       (int)data, *IXP425_ICIP, *IXP425_ICIH);
-}
-
-static int next_irq(void)
-{
-	return (((*IXP425_ICIH & 0x000000fc) >> 2) - 1);
-}
-
-void do_irq (struct pt_regs *pt_regs)
-{
-	int irq = next_irq();
-
-	IRQ_HANDLER[irq].m_func(IRQ_HANDLER[irq].m_data);
-}
-
-void irq_install_handler (int irq, interrupt_handler_t handle_irq, void *data)
-{
-	if (irq >= N_IRQS || !handle_irq)
-		return;
-
-	IRQ_HANDLER[irq].m_data = data;
-	IRQ_HANDLER[irq].m_func = handle_irq;
-}
-
-int arch_interrupt_init (void)
-{
-	int i;
-
-	/* install default interrupt handlers */
-	for (i = 0; i < N_IRQS; i++)
-		irq_install_handler(i, default_isr, (void *)i);
-
-	/* configure interrupts for IRQ mode */
-	*IXP425_ICLR = 0x00000000;
-
-	return (0);
-}
diff --git a/arch/arm/cpu/ixp/start.S b/arch/arm/cpu/ixp/start.S
deleted file mode 100644
index 82c868a174..0000000000
--- a/arch/arm/cpu/ixp/start.S
+++ /dev/null
@@ -1,430 +0,0 @@
-/* vi: set ts=8 sw=8 noet: */
-/*
- *  u-boot - Startup Code for XScale IXP
- *
- * Copyright (C) 2003	Kyle Harris <kharris@nexus-tech.net>
- *
- * Based on startup code example contained in the
- * Intel IXP4xx Programmer's Guide and past u-boot Start.S
- * samples.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <asm-offsets.h>
-#include <config.h>
-#include <version.h>
-#include <asm/arch/ixp425.h>
-
-#define MMU_Control_M  0x001    /* Enable MMU */
-#define MMU_Control_A  0x002    /* Enable address alignment faults */
-#define MMU_Control_C  0x004    /* Enable cache */
-#define MMU_Control_W  0x008    /* Enable write-buffer */
-#define MMU_Control_P  0x010    /* Compatability: 32 bit code */
-#define MMU_Control_D  0x020    /* Compatability: 32 bit data */
-#define MMU_Control_L  0x040    /* Compatability: */
-#define MMU_Control_B  0x080    /* Enable Big-Endian */
-#define MMU_Control_S  0x100    /* Enable system protection */
-#define MMU_Control_R  0x200    /* Enable ROM protection */
-#define MMU_Control_I  0x1000   /* Enable Instruction cache */
-#define MMU_Control_X  0x2000   /* Set interrupt vectors at 0xFFFF0000 */
-#define MMU_Control_Init (MMU_Control_P|MMU_Control_D|MMU_Control_L)
-
-
-/*
- * Macro definitions
- */
-	/* Delay a bit */
-	.macro DELAY_FOR cycles, reg0
-	ldr     \reg0, =\cycles
-	subs    \reg0, \reg0, #1
-	subne   pc,  pc, #0xc
-	.endm
-
-	/* wait for coprocessor write complete */
-	.macro CPWAIT reg
-	mrc  p15,0,\reg,c2,c0,0
-	mov  \reg,\reg
-	sub  pc,pc,#4
-	.endm
-
-.globl _start
-_start:
-	ldr	pc, _reset
-	ldr	pc, _undefined_instruction
-	ldr	pc, _software_interrupt
-	ldr	pc, _prefetch_abort
-	ldr	pc, _data_abort
-	ldr	pc, _not_used
-	ldr	pc, _irq
-	ldr	pc, _fiq
-
-_reset:                 .word reset
-_undefined_instruction: .word undefined_instruction
-_software_interrupt:	.word software_interrupt
-_prefetch_abort:	.word prefetch_abort
-_data_abort:		.word data_abort
-_not_used:		.word not_used
-_irq:			.word irq
-_fiq:			.word fiq
-
-	.balignl 16,0xdeadbeef
-
-
-/*
- * Startup Code (reset vector)
- *
- * do important init only if we don't start from memory!
- * - relocate armboot to ram
- * - setup stack
- * - jump to second stage
- */
-
-.globl _TEXT_BASE
-_TEXT_BASE:
-#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_TEXT_BASE)
-	.word	CONFIG_SPL_TEXT_BASE
-#else
-	.word	CONFIG_SYS_TEXT_BASE
-#endif
-
-/*
- * These are defined in the board-specific linker script.
- * Subtracting _start from them lets the linker put their
- * relative position in the executable instead of leaving
- * them null.
- */
-.globl _bss_start_ofs
-_bss_start_ofs:
-	.word __bss_start - _start
-
-.globl _bss_end_ofs
-_bss_end_ofs:
-	.word __bss_end - _start
-
-.globl _end_ofs
-_end_ofs:
-	.word _end - _start
-
-#ifdef CONFIG_USE_IRQ
-/* IRQ stack memory (calculated at run-time) */
-.globl IRQ_STACK_START
-IRQ_STACK_START:
-	.word	0x0badc0de
-
-/* IRQ stack memory (calculated at run-time) */
-.globl FIQ_STACK_START
-FIQ_STACK_START:
-	.word 0x0badc0de
-#endif
-
-/* IRQ stack memory (calculated at run-time) + 8 bytes */
-.globl IRQ_STACK_START_IN
-IRQ_STACK_START_IN:
-	.word	0x0badc0de
-
-/*
- * the actual reset code
- */
-
-reset:
-	/* disable mmu, set big-endian */
-	mov	r0, #0xf8
-	mcr	p15, 0, r0, c1, c0, 0
-	CPWAIT  r0
-
-	/* invalidate I & D caches & BTB */
-	mcr	p15, 0, r0, c7, c7, 0
-	CPWAIT	r0
-
-	/* invalidate I & Data TLB */
-	mcr	p15, 0, r0, c8, c7, 0
-	CPWAIT r0
-
-	/* drain write and fill buffers */
-	mcr	p15, 0, r0, c7, c10, 4
-	CPWAIT	r0
-
-	/* disable write buffer coalescing */
-	mrc	p15, 0, r0, c1, c0, 1
-	orr	r0, r0, #1
-	mcr	p15, 0, r0, c1, c0, 1
-	CPWAIT	r0
-
-	/* set EXP CS0 to the optimum timing */
-	ldr	r1, =CONFIG_SYS_EXP_CS0
-	ldr     r2, =IXP425_EXP_CS0
-	str     r1, [r2]
-
-	/* make sure flash is visible at 0 */
-	mov	r1, #CONFIG_SYS_SDR_CONFIG
-	ldr     r2, =IXP425_SDR_CONFIG
-	str     r1, [r2]
-
-	/* disable refresh cycles */
-	mov	r1, #0
-	ldr     r3, =IXP425_SDR_REFRESH
-	str	r1, [r3]
-
-	/* send nop command */
-	mov	r1, #3
-	ldr	r4, =IXP425_SDR_IR
-	str	r1, [r4]
-	DELAY_FOR 0x4000, r0
-
-	/* set SDRAM internal refresh val */
-	ldr	r1, =CONFIG_SYS_SDRAM_REFRESH_CNT
-	str     r1, [r3]
-	DELAY_FOR 0x4000, r0
-
-	/* send precharge-all command to close all open banks */
-	mov     r1, #2
-	str     r1, [r4]
-	DELAY_FOR 0x4000, r0
-
-	/* provide 8 auto-refresh cycles */
-	mov     r1, #4
-	mov     r5, #8
-111:    str	r1, [r4]
-	DELAY_FOR 0x100, r0
-	subs	r5, r5, #1
-	bne	111b
-
-	/* set mode register in sdram */
-	mov	r1, #CONFIG_SYS_SDR_MODE_CONFIG
-	str	r1, [r4]
-	DELAY_FOR 0x4000, r0
-
-	/* send normal operation command */
-	mov	r1, #6
-	str	r1, [r4]
-	DELAY_FOR 0x4000, r0
-
-	/* invalidate I & D caches & BTB */
-	mcr	p15, 0, r0, c7, c7, 0
-	CPWAIT	r0
-
-	/* invalidate I & Data TLB */
-	mcr	p15, 0, r0, c8, c7, 0
-	CPWAIT r0
-
-	/* drain write and fill buffers */
-	mcr	p15, 0, r0, c7, c10, 4
-	CPWAIT	r0
-
-	/* remove flash mirror at 0x00000000 */
-	ldr	r2, =IXP425_EXP_CFG0
-	ldr     r1, [r2]
-	bic     r1, r1, #0x80000000
-	str     r1, [r2]
-
-	/* invalidate I & Data TLB */
-	mcr	p15, 0, r0, c8, c7, 0
-	CPWAIT r0
-
-	/* enable I cache */
-	mrc     p15, 0, r0, c1, c0, 0
-	orr     r0, r0, #MMU_Control_I
-	mcr     p15, 0, r0, c1, c0, 0
-	CPWAIT  r0
-
-	mrs	r0,cpsr			/* set the cpu to SVC32 mode	    */
-	bic	r0,r0,#0x1f		/* (superviser mode, M=10011)	    */
-	orr	r0,r0,#0x13
-	msr	cpsr,r0
-
-	bl	_main
-
-/*------------------------------------------------------------------------------*/
-
-	.globl	c_runtime_cpu_setup
-c_runtime_cpu_setup:
-
-	bx	lr
-
-/****************************************************************************/
-/*									    */
-/* Interrupt handling							    */
-/*									    */
-/****************************************************************************/
-
-/* IRQ stack frame							    */
-
-#define S_FRAME_SIZE	72
-
-#define S_OLD_R0	68
-#define S_PSR		64
-#define S_PC		60
-#define S_LR		56
-#define S_SP		52
-
-#define S_IP		48
-#define S_FP		44
-#define S_R10		40
-#define S_R9		36
-#define S_R8		32
-#define S_R7		28
-#define S_R6		24
-#define S_R5		20
-#define S_R4		16
-#define S_R3		12
-#define S_R2		8
-#define S_R1		4
-#define S_R0		0
-
-#define MODE_SVC 0x13
-
-	/* use bad_save_user_regs for abort/prefetch/undef/swi ...	    */
-
-	.macro	bad_save_user_regs
-	sub	sp, sp, #S_FRAME_SIZE
-	stmia	sp, {r0 - r12}			/* Calling r0-r12	    */
-	add	r8, sp, #S_PC
-
-	ldr	r2, IRQ_STACK_START_IN
-	ldmia	r2, {r2 - r4}			/* get pc, cpsr, old_r0	    */
-	add	r0, sp, #S_FRAME_SIZE		/* restore sp_SVC	    */
-
-	add	r5, sp, #S_SP
-	mov	r1, lr
-	stmia	r5, {r0 - r4}			/* save sp_SVC, lr_SVC, pc, cpsr, old_r */
-	mov	r0, sp
-	.endm
-
-
-	/* use irq_save_user_regs / irq_restore_user_regs for		     */
-	/* IRQ/FIQ handling						     */
-
-	.macro	irq_save_user_regs
-	sub	sp, sp, #S_FRAME_SIZE
-	stmia	sp, {r0 - r12}			/* Calling r0-r12	     */
-	add	r8, sp, #S_PC
-	stmdb	r8, {sp, lr}^			/* Calling SP, LR	     */
-	str	lr, [r8, #0]			/* Save calling PC	     */
-	mrs	r6, spsr
-	str	r6, [r8, #4]			/* Save CPSR		     */
-	str	r0, [r8, #8]			/* Save OLD_R0		     */
-	mov	r0, sp
-	.endm
-
-	.macro	irq_restore_user_regs
-	ldmia	sp, {r0 - lr}^			@ Calling r0 - lr
-	mov	r0, r0
-	ldr	lr, [sp, #S_PC]			@ Get PC
-	add	sp, sp, #S_FRAME_SIZE
-	subs	pc, lr, #4			@ return & move spsr_svc into cpsr
-	.endm
-
-	.macro get_bad_stack
-	ldr	r13, IRQ_STACK_START_IN		@ setup our mode stack
-
-	str	lr, [r13]			@ save caller lr / spsr
-	mrs	lr, spsr
-	str	lr, [r13, #4]
-
-	mov	r13, #MODE_SVC			@ prepare SVC-Mode
-	msr	spsr_c, r13
-	mov	lr, pc
-	movs	pc, lr
-	.endm
-
-	.macro get_irq_stack			@ setup IRQ stack
-	ldr	sp, IRQ_STACK_START
-	.endm
-
-	.macro get_fiq_stack			@ setup FIQ stack
-	ldr	sp, FIQ_STACK_START
-	.endm
-
-
-/****************************************************************************/
-/*									    */
-/* exception handlers							    */
-/*									    */
-/****************************************************************************/
-
-	.align	5
-undefined_instruction:
-	get_bad_stack
-	bad_save_user_regs
-	bl	do_undefined_instruction
-
-	.align	5
-software_interrupt:
-	get_bad_stack
-	bad_save_user_regs
-	bl	do_software_interrupt
-
-	.align	5
-prefetch_abort:
-	get_bad_stack
-	bad_save_user_regs
-	bl	do_prefetch_abort
-
-	.align	5
-data_abort:
-	get_bad_stack
-	bad_save_user_regs
-	bl	do_data_abort
-
-	.align	5
-not_used:
-	get_bad_stack
-	bad_save_user_regs
-	bl	do_not_used
-
-#ifdef CONFIG_USE_IRQ
-
-	.align	5
-irq:
-	get_irq_stack
-	irq_save_user_regs
-	bl	do_irq
-	irq_restore_user_regs
-
-	.align	5
-fiq:
-	get_fiq_stack
-	irq_save_user_regs		/* someone ought to write a more    */
-	bl	do_fiq			/* effiction fiq_save_user_regs	    */
-	irq_restore_user_regs
-
-#else
-
-	.align	5
-irq:
-	get_bad_stack
-	bad_save_user_regs
-	bl	do_irq
-
-	.align	5
-fiq:
-	get_bad_stack
-	bad_save_user_regs
-	bl	do_fiq
-
-#endif
-
-/****************************************************************************/
-/*                                                                          */
-/* Reset function: Use Watchdog to reset                                    */
-/*                                                                          */
-/****************************************************************************/
-
-	.align	5
-.globl reset_cpu
-
-reset_cpu:
-	ldr	r1, =0x482e
-	ldr     r2, =IXP425_OSWK
-	str     r1, [r2]
-	ldr	r1, =0x0fff
-	ldr     r2, =IXP425_OSWT
-	str     r1, [r2]
-	ldr	r1, =0x5
-	ldr     r2, =IXP425_OSWE
-	str     r1, [r2]
-	b	reset_endless
-
-reset_endless:
-	b	reset_endless
diff --git a/arch/arm/cpu/ixp/timer.c b/arch/arm/cpu/ixp/timer.c
deleted file mode 100644
index 38e2e2879c..0000000000
--- a/arch/arm/cpu/ixp/timer.c
+++ /dev/null
@@ -1,101 +0,0 @@
-/*
- * (C) Copyright 2010
- * Michael Schwingen, michael@schwingen.org
- *
- * (C) Copyright 2006
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Alex Zuepke <azu@sysgo.de>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/arch/ixp425.h>
-#include <asm/io.h>
-#include <div64.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-/*
- * The IXP42x time-stamp timer runs at 2*OSC_IN (66.666MHz when using a
- * 33.333MHz crystal).
- */
-static inline unsigned long long tick_to_time(unsigned long long tick)
-{
-	tick *= CONFIG_SYS_HZ;
-	do_div(tick, CONFIG_IXP425_TIMER_CLK);
-	return tick;
-}
-
-static inline unsigned long long time_to_tick(unsigned long long time)
-{
-	time *= CONFIG_IXP425_TIMER_CLK;
-	do_div(time, CONFIG_SYS_HZ);
-	return time;
-}
-
-static inline unsigned long long us_to_tick(unsigned long long us)
-{
-	us = us * CONFIG_IXP425_TIMER_CLK + 999999;
-	do_div(us, 1000000);
-	return us;
-}
-
-unsigned long long get_ticks(void)
-{
-	ulong now = readl(IXP425_OSTS_B);
-
-	if (readl(IXP425_OSST) & IXP425_OSST_TIMER_TS_PEND) {
-		/* rollover of timestamp timer register */
-		gd->arch.timestamp += (0xFFFFFFFF - gd->arch.lastinc) + now + 1;
-		writel(IXP425_OSST_TIMER_TS_PEND, IXP425_OSST);
-	} else {
-		/* move stamp forward with absolut diff ticks */
-		gd->arch.timestamp += (now - gd->arch.lastinc);
-	}
-	gd->arch.lastinc = now;
-	return gd->arch.timestamp;
-}
-
-
-void reset_timer_masked(void)
-{
-	/* capture current timestamp counter */
-	gd->arch.lastinc = readl(IXP425_OSTS_B);
-	/* start "advancing" time stamp from 0 */
-	gd->arch.timestamp = 0;
-}
-
-ulong get_timer_masked(void)
-{
-	return tick_to_time(get_ticks());
-}
-
-ulong get_timer(ulong base)
-{
-	return get_timer_masked() - base;
-}
-
-/* delay x useconds AND preserve advance timestamp value */
-void __udelay(unsigned long usec)
-{
-	unsigned long long tmp;
-
-	tmp = get_ticks() + us_to_tick(usec);
-
-	while (get_ticks() < tmp)
-		;
-}
-
-int timer_init(void)
-{
-	writel(IXP425_OSST_TIMER_TS_PEND, IXP425_OSST);
-	return 0;
-}
diff --git a/arch/arm/cpu/ixp/u-boot.lds b/arch/arm/cpu/ixp/u-boot.lds
deleted file mode 100644
index c8d2e126ae..0000000000
--- a/arch/arm/cpu/ixp/u-boot.lds
+++ /dev/null
@@ -1,88 +0,0 @@
-/*
- * (C) Copyright 2000-2006
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-OUTPUT_FORMAT("elf32-bigarm", "elf32-bigarm", "elf32-bigarm")
-OUTPUT_ARCH(arm)
-ENTRY(_start)
-SECTIONS
-{
-	. = 0x00000000;
-
-	. = ALIGN(4);
-	.text :
-	{
-		*(.__image_copy_start)
-		arch/arm/cpu/ixp/start.o(.text*)
-		*(.text*)
-	}
-
-	. = ALIGN(4);
-	.rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
-
-	. = ALIGN(4);
-	.data : {
-		*(.data*)
-	}
-
-	. = ALIGN(4);
-
-	. = .;
-
-	. = ALIGN(4);
-	.u_boot_list : {
-		KEEP(*(SORT(.u_boot_list*)));
-	}
-
-	. = ALIGN(4);
-
-	.image_copy_end :
-	{
-		*(.__image_copy_end)
-	}
-
-	.rel_dyn_start :
-	{
-		*(.__rel_dyn_start)
-	}
-
-	.rel.dyn : {
-		*(.rel*)
-	}
-
-	.rel_dyn_end :
-	{
-		*(.__rel_dyn_end)
-	}
-
-	_end = .;
-
-/*
- * Compiler-generated __bss_start and __bss_end, see arch/arm/lib/bss.c
- * __bss_base and __bss_limit are for linker only (overlay ordering)
- */
-
-	.bss_start __rel_dyn_start (OVERLAY) : {
-		KEEP(*(.__bss_start));
-		__bss_base = .;
-	}
-
-	.bss __bss_base (OVERLAY) : {
-		*(.bss*)
-		 . = ALIGN(4);
-		 __bss_limit = .;
-	}
-	.bss_end __bss_limit (OVERLAY) : {
-		KEEP(*(.__bss_end));
-	}
-
-	/DISCARD/ : { *(.dynsym) }
-	/DISCARD/ : { *(.dynstr*) }
-	/DISCARD/ : { *(.dynamic*) }
-	/DISCARD/ : { *(.plt*) }
-	/DISCARD/ : { *(.interp*) }
-	/DISCARD/ : { *(.gnu*) }
-}
diff --git a/arch/arm/cpu/pxa/Makefile b/arch/arm/cpu/pxa/Makefile
index c84186a67c..8cd475e3a4 100644
--- a/arch/arm/cpu/pxa/Makefile
+++ b/arch/arm/cpu/pxa/Makefile
@@ -5,35 +5,11 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
+extra-y	= start.o
 
-LIB	= $(obj)lib$(CPU).o
+obj-$(CONFIG_CPU_PXA25X)	+= pxa2xx.o
+obj-$(CONFIG_CPU_PXA27X)	+= pxa2xx.o
 
-START	= start.o
-
-COBJS-$(CONFIG_CPU_PXA25X)	= pxa2xx.o
-COBJS-$(CONFIG_CPU_PXA27X)	= pxa2xx.o
-
-COBJS-y	+= cpuinfo.o
-
-COBJS	= $(COBJS-y)
-COBJS	+= timer.o
-COBJS	+= usb.o
-
-SRCS	:= $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS))
-START	:= $(addprefix $(obj),$(START))
-
-all:	$(obj).depend $(START) $(LIB)
-
-$(LIB):	$(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	+= cpuinfo.o
+obj-y	+= timer.o
+obj-y	+= usb.o
diff --git a/arch/arm/cpu/pxa/config.mk b/arch/arm/cpu/pxa/config.mk
index d8d263d404..525f5d33b7 100644
--- a/arch/arm/cpu/pxa/config.mk
+++ b/arch/arm/cpu/pxa/config.mk
@@ -7,10 +7,16 @@
 #
 
 PLATFORM_CPPFLAGS += -mcpu=xscale
-# =========================================================================
+
 #
-# Supply options according to compiler version
+# !WARNING!
+# The PXA's OneNAND SPL uses .text.0 and .text.1 segments to allow booting from
+# really small OneNAND memories where the mmap'd window is only 1KiB big. The
+# .text.0 contains only the bare minimum needed to load the real SPL into SRAM.
+# Add .text.0 and .text.1 into OBJFLAGS, so when the SPL is being objcopy'd,
+# they are not discarded.
 #
-# ========================================================================
-PF_RELFLAGS_SLB_AT := $(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,))
-PLATFORM_RELFLAGS += $(PF_RELFLAGS_SLB_AT)
+
+#ifdef CONFIG_SPL_BUILD
+OBJCOPYFLAGS += -j .text.0 -j .text.1
+#endif
diff --git a/arch/arm/cpu/pxa/pxa2xx.c b/arch/arm/cpu/pxa/pxa2xx.c
index c9a7d45392..7e861e26db 100644
--- a/arch/arm/cpu/pxa/pxa2xx.c
+++ b/arch/arm/cpu/pxa/pxa2xx.c
@@ -279,6 +279,7 @@ void reset_cpu(ulong ignored)
 	tmp = readl(OSCR);
 	tmp += 0x1000;
 	writel(tmp, OSMR3);
+	writel(MDREFR_SLFRSH, MDREFR);
 
 	for (;;)
 		;
diff --git a/arch/arm/cpu/pxa/start.S b/arch/arm/cpu/pxa/start.S
index d8fb812dbf..ae0d13ce8f 100644
--- a/arch/arm/cpu/pxa/start.S
+++ b/arch/arm/cpu/pxa/start.S
@@ -84,32 +84,6 @@ _end_vect:
  *************************************************************************
  */
 
-.globl _TEXT_BASE
-_TEXT_BASE:
-#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_TEXT_BASE)
-	.word	CONFIG_SPL_TEXT_BASE
-#else
-	.word	CONFIG_SYS_TEXT_BASE
-#endif
-
-/*
- * These are defined in the board-specific linker script.
- * Subtracting _start from them lets the linker put their
- * relative position in the executable instead of leaving
- * them null.
- */
-.globl _bss_start_ofs
-_bss_start_ofs:
-	.word __bss_start - _start
-
-.globl _bss_end_ofs
-_bss_end_ofs:
-	.word __bss_end - _start
-
-.globl _end_ofs
-_end_ofs:
-	.word _end - _start
-
 #ifdef CONFIG_USE_IRQ
 /* IRQ stack memory (calculated at run-time) */
 .globl IRQ_STACK_START
@@ -316,7 +290,6 @@ cpu_init_crit:
 #ifdef CONFIG_SPL_BUILD
 	.align	5
 do_hang:
-	ldr	sp, _TEXT_BASE			/* use 32 words about stack */
 	bl	hang				/* hang and never return */
 #else	/* !CONFIG_SPL_BUILD */
 	.align	5
diff --git a/arch/arm/cpu/pxa/timer.c b/arch/arm/cpu/pxa/timer.c
index 78d9f32745..c4717de6a9 100644
--- a/arch/arm/cpu/pxa/timer.c
+++ b/arch/arm/cpu/pxa/timer.c
@@ -28,12 +28,12 @@ DECLARE_GLOBAL_DATA_PTR;
 
 static unsigned long long tick_to_time(unsigned long long tick)
 {
-	return tick * CONFIG_SYS_HZ / TIMER_FREQ_HZ;
+	return lldiv(tick * CONFIG_SYS_HZ, TIMER_FREQ_HZ);
 }
 
 static unsigned long long us_to_tick(unsigned long long us)
 {
-	return (us * TIMER_FREQ_HZ) / 1000000;
+	return lldiv(us * TIMER_FREQ_HZ, 1000000);
 }
 
 int timer_init(void)
diff --git a/arch/arm/cpu/sa1100/Makefile b/arch/arm/cpu/sa1100/Makefile
index c84b7b975e..85a0d28f4b 100644
--- a/arch/arm/cpu/sa1100/Makefile
+++ b/arch/arm/cpu/sa1100/Makefile
@@ -5,29 +5,7 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
+extra-y	= start.o
 
-LIB	= $(obj)lib$(CPU).o
-
-START	= start.o
-
-COBJS	+= cpu.o
-COBJS	+= timer.o
-
-SRCS	:= $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS))
-START	:= $(addprefix $(obj),$(START))
-
-all:	$(obj).depend $(START) $(LIB)
-
-$(LIB):	$(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	+= cpu.o
+obj-y	+= timer.o
diff --git a/arch/arm/cpu/sa1100/config.mk b/arch/arm/cpu/sa1100/config.mk
index b3026cc50d..3afa685b3f 100644
--- a/arch/arm/cpu/sa1100/config.mk
+++ b/arch/arm/cpu/sa1100/config.mk
@@ -7,10 +7,3 @@
 #
 
 PLATFORM_CPPFLAGS += -march=armv4 -mtune=strongarm1100
-# =========================================================================
-#
-# Supply options according to compiler version
-#
-# ========================================================================
-PF_RELFLAGS_SLB_AT := $(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,))
-PLATFORM_RELFLAGS += $(PF_RELFLAGS_SLB_AT)
diff --git a/arch/arm/cpu/sa1100/start.S b/arch/arm/cpu/sa1100/start.S
index 27bcda598c..bf80937a7c 100644
--- a/arch/arm/cpu/sa1100/start.S
+++ b/arch/arm/cpu/sa1100/start.S
@@ -56,32 +56,6 @@ _fiq:			.word fiq
  *************************************************************************
  */
 
-.globl _TEXT_BASE
-_TEXT_BASE:
-#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_TEXT_BASE)
-	.word	CONFIG_SPL_TEXT_BASE
-#else
-	.word	CONFIG_SYS_TEXT_BASE
-#endif
-
-/*
- * These are defined in the board-specific linker script.
- * Subtracting _start from them lets the linker put their
- * relative position in the executable instead of leaving
- * them null.
- */
-.globl _bss_start_ofs
-_bss_start_ofs:
-	.word __bss_start - _start
-
-.globl _bss_end_ofs
-_bss_end_ofs:
-	.word __bss_end - _start
-
-.globl _end_ofs
-_end_ofs:
-	.word _end - _start
-
 #ifdef CONFIG_USE_IRQ
 /* IRQ stack memory (calculated at run-time) */
 .globl IRQ_STACK_START
diff --git a/arch/arm/cpu/sa1100/timer.c b/arch/arm/cpu/sa1100/timer.c
index 4b981e46e7..0a0006b426 100644
--- a/arch/arm/cpu/sa1100/timer.c
+++ b/arch/arm/cpu/sa1100/timer.c
@@ -13,11 +13,6 @@
 #include <common.h>
 #include <SA-1100.h>
 
-int timer_init (void)
-{
-	return 0;
-}
-
 ulong get_timer (ulong base)
 {
 	return get_timer_masked ();
diff --git a/arch/arm/cpu/tegra-common/Makefile b/arch/arm/cpu/tegra-common/Makefile
index 1b6cdf71a5..34d57349af 100644
--- a/arch/arm/cpu/tegra-common/Makefile
+++ b/arch/arm/cpu/tegra-common/Makefile
@@ -7,26 +7,6 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)libcputegra-common.o
-
-SOBJS += lowlevel_init.o
-COBJS-y	+= ap.o board.o sys_info.o timer.o clock.o cache.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
-OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS-y))
-
-all:	$(obj).depend $(LIB)
-
-$(LIB):	$(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y += lowlevel_init.o
+obj-y	+= ap.o board.o clock.o cache.o
+obj-$(CONFIG_DISPLAY_CPUINFO) += sys_info.o
diff --git a/arch/arm/cpu/tegra-common/ap.c b/arch/arm/cpu/tegra-common/ap.c
index 6fb11cb5c4..91d70da656 100644
--- a/arch/arm/cpu/tegra-common/ap.c
+++ b/arch/arm/cpu/tegra-common/ap.c
@@ -1,5 +1,5 @@
 /*
-* (C) Copyright 2010-2011
+* (C) Copyright 2010-2014
 * NVIDIA Corporation <www.nvidia.com>
 *
  * SPDX-License-Identifier:	GPL-2.0+
@@ -27,7 +27,7 @@ int tegra_get_chip(void)
 	/*
 	 * This is undocumented, Chip ID is bits 15:8 of the register
 	 * APB_MISC + 0x804, and has value 0x20 for Tegra20, 0x30 for
-	 * Tegra30, and 0x35 for T114.
+	 * Tegra30, 0x35 for T114, and 0x40 for Tegra124.
 	 */
 	rev = (readl(&gp->hidrev) & HIDREV_CHIPID_MASK) >> HIDREV_CHIPID_SHIFT;
 	debug("%s: CHIPID is 0x%02X\n", __func__, rev);
@@ -71,6 +71,8 @@ int tegra_get_chip_sku(void)
 		switch (sku_id) {
 		case SKU_ID_T33:
 		case SKU_ID_T30:
+		case SKU_ID_TM30MQS_P_A3:
+		default:
 			return TEGRA_SOC_T30;
 		}
 		break;
@@ -78,10 +80,19 @@ int tegra_get_chip_sku(void)
 		switch (sku_id) {
 		case SKU_ID_T114_ENG:
 		case SKU_ID_T114_1:
+		default:
 			return TEGRA_SOC_T114;
 		}
 		break;
+	case CHIPID_TEGRA124:
+		switch (sku_id) {
+		case SKU_ID_T124_ENG:
+		default:
+			return TEGRA_SOC_T124;
+		}
+		break;
 	}
+
 	/* unknown chip/sku id */
 	printf("%s: ERROR: UNKNOWN CHIP/SKU ID COMBO (0x%02X/0x%02X)\n",
 		__func__, chip_id, sku_id);
@@ -116,8 +127,8 @@ static u32 get_odmdata(void)
 	 * ODMDATA is stored in the BCT in IRAM by the BootROM.
 	 * The BCT start and size are stored in the BIT in IRAM.
 	 * Read the data @ bct_start + (bct_size - 12). This works
-	 * on T20 and T30 BCTs, which are locked down. If this changes
-	 * in new chips (T114, etc.), we can revisit this algorithm.
+	 * on BCTs for currently supported SoCs, which are locked down.
+	 * If this changes in new chips, we can revisit this algorithm.
 	 */
 
 	u32 bct_start, odmdata;
diff --git a/arch/arm/cpu/tegra-common/board.c b/arch/arm/cpu/tegra-common/board.c
index d9cbda8a74..6a6faf4b27 100644
--- a/arch/arm/cpu/tegra-common/board.c
+++ b/arch/arm/cpu/tegra-common/board.c
@@ -1,5 +1,5 @@
 /*
- *  (C) Copyright 2010,2011
+ *  (C) Copyright 2010-2014
  *  NVIDIA Corporation <www.nvidia.com>
  *
  * SPDX-License-Identifier:	GPL-2.0+
@@ -109,12 +109,18 @@ static int uart_configs[] = {
 	-1,
 	-1,
 	-1,
-#else	/* Tegra114 */
+#elif defined(CONFIG_TEGRA114)
 	-1,
 	-1,
 	-1,
 	FUNCMUX_UART4_GMI,	/* UARTD */
 	-1,
+#else	/* Tegra124 */
+	FUNCMUX_UART1_KBC,	/* UARTA */
+	-1,
+	-1,
+	FUNCMUX_UART4_GPIO,	/* UARTD */
+	-1,
 #endif
 };
 
diff --git a/arch/arm/cpu/tegra-common/cache.c b/arch/arm/cpu/tegra-common/cache.c
index 48e9319c75..94f5bce90e 100644
--- a/arch/arm/cpu/tegra-common/cache.c
+++ b/arch/arm/cpu/tegra-common/cache.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2013, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2013-2014, NVIDIA CORPORATION.  All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms and conditions of the GNU General Public License,
@@ -23,8 +23,6 @@
 
 void config_cache(void)
 {
-	struct apb_misc_gp_ctlr *gp =
-		(struct apb_misc_gp_ctlr *)NV_PA_APB_MISC_GP_BASE;
 	u32 reg = 0;
 
 	/* enable SMP mode and FW for CPU0, by writing to Auxiliary Ctl reg */
@@ -33,10 +31,10 @@ void config_cache(void)
 		"orr r0, r0, #0x41\n"
 		"mcr p15, 0, r0, c1, c0, 1\n");
 
-	/* Currently, only T114 needs this L2 cache change to boot Linux */
-	reg = (readl(&gp->hidrev) & HIDREV_CHIPID_MASK);
-	if (reg != (CHIPID_TEGRA114 << HIDREV_CHIPID_SHIFT))
+	/* Currently, only Tegra114+ needs this L2 cache change to boot Linux */
+	if (tegra_get_chip() < CHIPID_TEGRA114)
 		return;
+
 	/*
 	 * Systems with an architectural L2 cache must not use the PL310.
 	 * Config L2CTLR here for a data RAM latency of 3 cycles.
diff --git a/arch/arm/cpu/tegra-common/clock.c b/arch/arm/cpu/tegra-common/clock.c
index 268fb912b5..11c7435505 100644
--- a/arch/arm/cpu/tegra-common/clock.c
+++ b/arch/arm/cpu/tegra-common/clock.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2010-2013, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2010-2014, NVIDIA CORPORATION.  All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms and conditions of the GNU General Public License,
@@ -142,8 +142,8 @@ void clock_ll_set_source_divisor(enum periph_id periph_id, unsigned source,
 
 	value = readl(reg);
 
-	value &= ~OUT_CLK_SOURCE_MASK;
-	value |= source << OUT_CLK_SOURCE_SHIFT;
+	value &= ~OUT_CLK_SOURCE_31_30_MASK;
+	value |= source << OUT_CLK_SOURCE_31_30_SHIFT;
 
 	value &= ~OUT_CLK_DIVISOR_MASK;
 	value |= divisor << OUT_CLK_DIVISOR_SHIFT;
@@ -155,8 +155,8 @@ void clock_ll_set_source(enum periph_id periph_id, unsigned source)
 {
 	u32 *reg = get_periph_source_reg(periph_id);
 
-	clrsetbits_le32(reg, OUT_CLK_SOURCE_MASK,
-			source << OUT_CLK_SOURCE_SHIFT);
+	clrsetbits_le32(reg, OUT_CLK_SOURCE_31_30_MASK,
+			source << OUT_CLK_SOURCE_31_30_SHIFT);
 }
 
 /**
@@ -304,13 +304,27 @@ static int adjust_periph_pll(enum periph_id periph_id, int source,
 	/* work out the source clock and set it */
 	if (source < 0)
 		return -1;
-	if (mux_bits == 4) {
-		clrsetbits_le32(reg, OUT_CLK_SOURCE4_MASK,
-			source << OUT_CLK_SOURCE4_SHIFT);
-	} else {
-		clrsetbits_le32(reg, OUT_CLK_SOURCE_MASK,
-			source << OUT_CLK_SOURCE_SHIFT);
+
+	switch (mux_bits) {
+	case MASK_BITS_31_30:
+		clrsetbits_le32(reg, OUT_CLK_SOURCE_31_30_MASK,
+				source << OUT_CLK_SOURCE_31_30_SHIFT);
+		break;
+
+	case MASK_BITS_31_29:
+		clrsetbits_le32(reg, OUT_CLK_SOURCE_31_29_MASK,
+				source << OUT_CLK_SOURCE_31_29_SHIFT);
+		break;
+
+	case MASK_BITS_31_28:
+		clrsetbits_le32(reg, OUT_CLK_SOURCE_31_28_MASK,
+				source << OUT_CLK_SOURCE_31_28_SHIFT);
+		break;
+
+	default:
+		return -1;
 	}
+
 	udelay(2);
 	return 0;
 }
@@ -561,3 +575,95 @@ void clock_init(void)
 	/* Do any special system timer/TSC setup */
 	arch_timer_init();
 }
+
+static void set_avp_clock_source(u32 src)
+{
+	struct clk_rst_ctlr *clkrst =
+			(struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
+	u32 val;
+
+	val = (src << SCLK_SWAKEUP_FIQ_SOURCE_SHIFT) |
+		(src << SCLK_SWAKEUP_IRQ_SOURCE_SHIFT) |
+		(src << SCLK_SWAKEUP_RUN_SOURCE_SHIFT) |
+		(src << SCLK_SWAKEUP_IDLE_SOURCE_SHIFT) |
+		(SCLK_SYS_STATE_RUN << SCLK_SYS_STATE_SHIFT);
+	writel(val, &clkrst->crc_sclk_brst_pol);
+	udelay(3);
+}
+
+/*
+ * This function is useful on Tegra30, and any later SoCs that have compatible
+ * PLLP configuration registers.
+ */
+void tegra30_set_up_pllp(void)
+{
+	struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
+	u32 reg;
+
+	/*
+	 * Based on the Tegra TRM, the system clock (which is the AVP clock) can
+	 * run up to 275MHz. On power on, the default sytem clock source is set
+	 * to PLLP_OUT0. This function sets PLLP's (hence PLLP_OUT0's) rate to
+	 * 408MHz which is beyond system clock's upper limit.
+	 *
+	 * The fix is to set the system clock to CLK_M before initializing PLLP,
+	 * and then switch back to PLLP_OUT4, which has an appropriate divider
+	 * configured, after PLLP has been configured
+	 */
+	set_avp_clock_source(SCLK_SOURCE_CLKM);
+
+	/*
+	 * PLLP output frequency set to 408Mhz
+	 * PLLC output frequency set to 228Mhz
+	 */
+	switch (clock_get_osc_freq()) {
+	case CLOCK_OSC_FREQ_12_0: /* OSC is 12Mhz */
+		clock_set_rate(CLOCK_ID_PERIPH, 408, 12, 0, 8);
+		clock_set_rate(CLOCK_ID_CGENERAL, 456, 12, 1, 8);
+		break;
+
+	case CLOCK_OSC_FREQ_26_0: /* OSC is 26Mhz */
+		clock_set_rate(CLOCK_ID_PERIPH, 408, 26, 0, 8);
+		clock_set_rate(CLOCK_ID_CGENERAL, 600, 26, 0, 8);
+		break;
+
+	case CLOCK_OSC_FREQ_13_0: /* OSC is 13Mhz */
+		clock_set_rate(CLOCK_ID_PERIPH, 408, 13, 0, 8);
+		clock_set_rate(CLOCK_ID_CGENERAL, 600, 13, 0, 8);
+		break;
+	case CLOCK_OSC_FREQ_19_2:
+	default:
+		/*
+		 * These are not supported. It is too early to print a
+		 * message and the UART likely won't work anyway due to the
+		 * oscillator being wrong.
+		 */
+		break;
+	}
+
+	/* Set PLLP_OUT1, 2, 3 & 4 freqs to 9.6, 48, 102 & 204MHz */
+
+	/* OUT1, 2 */
+	/* Assert RSTN before enable */
+	reg = PLLP_OUT2_RSTN_EN | PLLP_OUT1_RSTN_EN;
+	writel(reg, &clkrst->crc_pll[CLOCK_ID_PERIPH].pll_out[0]);
+	/* Set divisor and reenable */
+	reg = (IN_408_OUT_48_DIVISOR << PLLP_OUT2_RATIO)
+		| PLLP_OUT2_OVR | PLLP_OUT2_CLKEN | PLLP_OUT2_RSTN_DIS
+		| (IN_408_OUT_9_6_DIVISOR << PLLP_OUT1_RATIO)
+		| PLLP_OUT1_OVR | PLLP_OUT1_CLKEN | PLLP_OUT1_RSTN_DIS;
+	writel(reg, &clkrst->crc_pll[CLOCK_ID_PERIPH].pll_out[0]);
+
+	/* OUT3, 4 */
+	/* Assert RSTN before enable */
+	reg = PLLP_OUT4_RSTN_EN | PLLP_OUT3_RSTN_EN;
+	writel(reg, &clkrst->crc_pll[CLOCK_ID_PERIPH].pll_out[1]);
+	/* Set divisor and reenable */
+	reg = (IN_408_OUT_204_DIVISOR << PLLP_OUT4_RATIO)
+		| PLLP_OUT4_OVR | PLLP_OUT4_CLKEN | PLLP_OUT4_RSTN_DIS
+		| (IN_408_OUT_102_DIVISOR << PLLP_OUT3_RATIO)
+		| PLLP_OUT3_OVR | PLLP_OUT3_CLKEN | PLLP_OUT3_RSTN_DIS;
+	writel(reg, &clkrst->crc_pll[CLOCK_ID_PERIPH].pll_out[1]);
+
+	set_avp_clock_source(SCLK_SOURCE_PLLP_OUT4);
+}
diff --git a/arch/arm/cpu/tegra-common/sys_info.c b/arch/arm/cpu/tegra-common/sys_info.c
index dc8a2e4d31..de20325ecf 100644
--- a/arch/arm/cpu/tegra-common/sys_info.c
+++ b/arch/arm/cpu/tegra-common/sys_info.c
@@ -8,7 +8,6 @@
 #include <common.h>
 #include <linux/ctype.h>
 
-#ifdef CONFIG_DISPLAY_CPUINFO
 void upstring(char *s)
 {
 	while (*s) {
@@ -30,4 +29,3 @@ int print_cpuinfo(void)
 	/* TBD: Add printf of major/minor rev info, stepping, etc. */
 	return 0;
 }
-#endif	/* CONFIG_DISPLAY_CPUINFO */
diff --git a/arch/arm/cpu/tegra-common/timer.c b/arch/arm/cpu/tegra-common/timer.c
deleted file mode 100644
index d0f783e660..0000000000
--- a/arch/arm/cpu/tegra-common/timer.c
+++ /dev/null
@@ -1,95 +0,0 @@
-/*
- * (C) Copyright 2010,2011
- * NVIDIA Corporation <www.nvidia.com>
- *
- * (C) Copyright 2008
- * Texas Instruments
- *
- * Richard Woodruff <r-woodruff2@ti.com>
- * Syed Moahmmed Khasim <khasim@ti.com>
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- * Alex Zuepke <azu@sysgo.de>
- *
- * (C) Copyright 2002
- * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/tegra.h>
-#include <asm/arch-tegra/timer.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-/* counter runs at 1MHz */
-#define TIMER_CLK	1000000
-#define TIMER_LOAD_VAL	0xffffffff
-
-/* timer without interrupts */
-ulong get_timer(ulong base)
-{
-	return get_timer_masked() - base;
-}
-
-/* delay x useconds */
-void __udelay(unsigned long usec)
-{
-	long tmo = usec * (TIMER_CLK / 1000) / 1000;
-	unsigned long now, last = timer_get_us();
-
-	while (tmo > 0) {
-		now = timer_get_us();
-		if (last > now) /* count up timer overflow */
-			tmo -= TIMER_LOAD_VAL - last + now;
-		else
-			tmo -= now - last;
-		last = now;
-	}
-}
-
-ulong get_timer_masked(void)
-{
-	ulong now;
-
-	/* current tick value */
-	now = timer_get_us() / (TIMER_CLK / CONFIG_SYS_HZ);
-
-	if (now >= gd->arch.lastinc)	/* normal mode (non roll) */
-		/* move stamp forward with absolute diff ticks */
-		gd->arch.tbl += (now - gd->arch.lastinc);
-	else	/* we have rollover of incrementer */
-		gd->arch.tbl += ((TIMER_LOAD_VAL / (TIMER_CLK / CONFIG_SYS_HZ))
-				- gd->arch.lastinc) + now;
-	gd->arch.lastinc = now;
-	return gd->arch.tbl;
-}
-
-/*
- * This function is derived from PowerPC code (read timebase as long long).
- * On ARM it just returns the timer value.
- */
-unsigned long long get_ticks(void)
-{
-	return get_timer(0);
-}
-
-/*
- * This function is derived from PowerPC code (timebase clock frequency).
- * On ARM it returns the number of timer ticks per second.
- */
-ulong get_tbclk(void)
-{
-	return CONFIG_SYS_HZ;
-}
-
-unsigned long timer_get_us(void)
-{
-	struct timerus *timer_base = (struct timerus *)NV_PA_TMRUS_BASE;
-
-	return readl(&timer_base->cntr_1us);
-}
diff --git a/arch/arm/cpu/tegra114-common/Makefile b/arch/arm/cpu/tegra114-common/Makefile
index 5b53a71ba3..d959b575ce 100644
--- a/arch/arm/cpu/tegra114-common/Makefile
+++ b/arch/arm/cpu/tegra114-common/Makefile
@@ -17,25 +17,4 @@
 # along with this program.  If not, see <http://www.gnu.org/licenses/>.
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(SOC)-common.o
-
-COBJS-y	+= clock.o funcmux.o pinmux.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
-OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS-y))
-
-all:	$(obj).depend $(LIB)
-
-$(LIB):	$(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	+= clock.o funcmux.o pinmux.o
diff --git a/arch/arm/cpu/tegra114-common/clock.c b/arch/arm/cpu/tegra114-common/clock.c
index 5c4305a418..d5194e11b5 100644
--- a/arch/arm/cpu/tegra114-common/clock.c
+++ b/arch/arm/cpu/tegra114-common/clock.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2010-2013, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2010-2014, NVIDIA CORPORATION.  All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms and conditions of the GNU General Public License,
@@ -61,12 +61,6 @@ enum {
 	CLOCK_MAX_MUX   = 8     /* number of source options for each clock */
 };
 
-enum {
-	MASK_BITS_31_30	= 2,	/* num of bits used to specify clock source */
-	MASK_BITS_31_29,
-	MASK_BITS_29_28,
-};
-
 /*
  * Clock source mux for each clock type. This just converts our enum into
  * a list of mux sources for use by the code.
@@ -109,7 +103,7 @@ static enum clock_id clock_source[CLOCK_TYPE_COUNT][CLOCK_MAX_MUX+1] = {
 		MASK_BITS_31_29},
 	{ CLK(PERIPH),	CLK(CGENERAL),	CLK(SFROM32KHZ),	CLK(OSC),
 		CLK(NONE),	CLK(NONE),	CLK(NONE),	CLK(NONE),
-		MASK_BITS_29_28}
+		MASK_BITS_31_28}
 };
 
 /*
@@ -610,26 +604,24 @@ void clock_early_init(void)
 	struct clk_rst_ctlr *clkrst =
 		(struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
 
+	tegra30_set_up_pllp();
+
 	/*
-	 * PLLP output frequency set to 408Mhz
 	 * PLLC output frequency set to 600Mhz
 	 * PLLD output frequency set to 925Mhz
 	 */
 	switch (clock_get_osc_freq()) {
 	case CLOCK_OSC_FREQ_12_0: /* OSC is 12Mhz */
-		clock_set_rate(CLOCK_ID_PERIPH, 408, 12, 0, 8);
 		clock_set_rate(CLOCK_ID_CGENERAL, 600, 12, 0, 8);
 		clock_set_rate(CLOCK_ID_DISPLAY, 925, 12, 0, 12);
 		break;
 
 	case CLOCK_OSC_FREQ_26_0: /* OSC is 26Mhz */
-		clock_set_rate(CLOCK_ID_PERIPH, 408, 26, 0, 8);
 		clock_set_rate(CLOCK_ID_CGENERAL, 600, 26, 0, 8);
 		clock_set_rate(CLOCK_ID_DISPLAY, 925, 26, 0, 12);
 		break;
 
 	case CLOCK_OSC_FREQ_13_0: /* OSC is 13Mhz */
-		clock_set_rate(CLOCK_ID_PERIPH, 408, 13, 0, 8);
 		clock_set_rate(CLOCK_ID_CGENERAL, 600, 13, 0, 8);
 		clock_set_rate(CLOCK_ID_DISPLAY, 925, 13, 0, 12);
 		break;
diff --git a/arch/arm/cpu/tegra124-common/Makefile b/arch/arm/cpu/tegra124-common/Makefile
new file mode 100644
index 0000000000..ff77992b33
--- /dev/null
+++ b/arch/arm/cpu/tegra124-common/Makefile
@@ -0,0 +1,10 @@
+#
+# (C) Copyright 2013-2014
+# NVIDIA Corporation <www.nvidia.com>
+#
+# SPDX-License-Identifier:     GPL-2.0+
+#
+
+obj-y	+= clock.o
+obj-y	+= funcmux.o
+obj-y	+= pinmux.o
diff --git a/arch/arm/cpu/tegra124-common/clock.c b/arch/arm/cpu/tegra124-common/clock.c
new file mode 100644
index 0000000000..739436326e
--- /dev/null
+++ b/arch/arm/cpu/tegra124-common/clock.c
@@ -0,0 +1,826 @@
+/*
+ * (C) Copyright 2013
+ * NVIDIA Corporation <www.nvidia.com>
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+/* Tegra124 Clock control functions */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/sysctr.h>
+#include <asm/arch/tegra.h>
+#include <asm/arch-tegra/clk_rst.h>
+#include <asm/arch-tegra/timer.h>
+#include <div64.h>
+#include <fdtdec.h>
+
+/*
+ * Clock types that we can use as a source. The Tegra124 has muxes for the
+ * peripheral clocks, and in most cases there are four options for the clock
+ * source. This gives us a clock 'type' and exploits what commonality exists
+ * in the device.
+ *
+ * Letters are obvious, except for T which means CLK_M, and S which means the
+ * clock derived from 32KHz. Beware that CLK_M (also called OSC in the
+ * datasheet) and PLL_M are different things. The former is the basic
+ * clock supplied to the SOC from an external oscillator. The latter is the
+ * memory clock PLL.
+ *
+ * See definitions in clock_id in the header file.
+ */
+enum clock_type_id {
+	CLOCK_TYPE_AXPT,	/* PLL_A, PLL_X, PLL_P, CLK_M */
+	CLOCK_TYPE_MCPA,	/* and so on */
+	CLOCK_TYPE_MCPT,
+	CLOCK_TYPE_PCM,
+	CLOCK_TYPE_PCMT,
+	CLOCK_TYPE_PDCT,
+	CLOCK_TYPE_ACPT,
+	CLOCK_TYPE_ASPTE,
+	CLOCK_TYPE_PMDACD2T,
+	CLOCK_TYPE_PCST,
+
+	CLOCK_TYPE_PC2CC3M,
+	CLOCK_TYPE_PC2CC3S_T,
+	CLOCK_TYPE_PC2CC3M_T,
+	CLOCK_TYPE_PC2CC3M_T16,	/* PC2CC3M_T, but w/16-bit divisor (I2C) */
+	CLOCK_TYPE_MC2CC3P_A,
+	CLOCK_TYPE_M,
+	CLOCK_TYPE_MCPTM2C2C3,
+	CLOCK_TYPE_PC2CC3T_S,
+	CLOCK_TYPE_AC2CC3P_TS2,
+
+	CLOCK_TYPE_COUNT,
+	CLOCK_TYPE_NONE = -1,   /* invalid clock type */
+};
+
+enum {
+	CLOCK_MAX_MUX   = 8     /* number of source options for each clock */
+};
+
+/*
+ * Clock source mux for each clock type. This just converts our enum into
+ * a list of mux sources for use by the code.
+ *
+ * Note:
+ *  The extra column in each clock source array is used to store the mask
+ *  bits in its register for the source.
+ */
+#define CLK(x) CLOCK_ID_ ## x
+static enum clock_id clock_source[CLOCK_TYPE_COUNT][CLOCK_MAX_MUX+1] = {
+	{ CLK(AUDIO),	CLK(XCPU),	CLK(PERIPH),	CLK(OSC),
+		CLK(NONE),	CLK(NONE),	CLK(NONE),	CLK(NONE),
+		MASK_BITS_31_30},
+	{ CLK(MEMORY),	CLK(CGENERAL),	CLK(PERIPH),	CLK(AUDIO),
+		CLK(NONE),	CLK(NONE),	CLK(NONE),	CLK(NONE),
+		MASK_BITS_31_30},
+	{ CLK(MEMORY),	CLK(CGENERAL),	CLK(PERIPH),	CLK(OSC),
+		CLK(NONE),	CLK(NONE),	CLK(NONE),	CLK(NONE),
+		MASK_BITS_31_30},
+	{ CLK(PERIPH),	CLK(CGENERAL),	CLK(MEMORY),	CLK(NONE),
+		CLK(NONE),	CLK(NONE),	CLK(NONE),	CLK(NONE),
+		MASK_BITS_31_30},
+	{ CLK(PERIPH),	CLK(CGENERAL),	CLK(MEMORY),	CLK(OSC),
+		CLK(NONE),	CLK(NONE),	CLK(NONE),	CLK(NONE),
+		MASK_BITS_31_30},
+	{ CLK(PERIPH),	CLK(DISPLAY),	CLK(CGENERAL),	CLK(OSC),
+		CLK(NONE),	CLK(NONE),	CLK(NONE),	CLK(NONE),
+		MASK_BITS_31_30},
+	{ CLK(AUDIO),	CLK(CGENERAL),	CLK(PERIPH),	CLK(OSC),
+		CLK(NONE),	CLK(NONE),	CLK(NONE),	CLK(NONE),
+		MASK_BITS_31_30},
+	{ CLK(AUDIO),	CLK(SFROM32KHZ),	CLK(PERIPH),	CLK(OSC),
+		CLK(EPCI),	CLK(NONE),	CLK(NONE),	CLK(NONE),
+		MASK_BITS_31_29},
+	{ CLK(PERIPH),	CLK(MEMORY),	CLK(DISPLAY),	CLK(AUDIO),
+		CLK(CGENERAL),	CLK(DISPLAY2),	CLK(OSC),	CLK(NONE),
+		MASK_BITS_31_29},
+	{ CLK(PERIPH),	CLK(CGENERAL),	CLK(SFROM32KHZ),	CLK(OSC),
+		CLK(NONE),	CLK(NONE),	CLK(NONE),	CLK(NONE),
+		MASK_BITS_31_28},
+
+	/* Additional clock types on Tegra114+ */
+	/* CLOCK_TYPE_PC2CC3M */
+	{ CLK(PERIPH),	CLK(CGENERAL2),	CLK(CGENERAL),	CLK(CGENERAL3),
+		CLK(MEMORY),	CLK(NONE),	CLK(NONE),	CLK(NONE),
+		MASK_BITS_31_29},
+	/* CLOCK_TYPE_PC2CC3S_T */
+	{ CLK(PERIPH),	CLK(CGENERAL2),	CLK(CGENERAL),	CLK(CGENERAL3),
+		CLK(SFROM32KHZ), CLK(NONE),	CLK(OSC),	CLK(NONE),
+		MASK_BITS_31_29},
+	/* CLOCK_TYPE_PC2CC3M_T */
+	{ CLK(PERIPH),	CLK(CGENERAL2),	CLK(CGENERAL),	CLK(CGENERAL3),
+		CLK(MEMORY),	CLK(NONE),	CLK(OSC),	CLK(NONE),
+		MASK_BITS_31_29},
+	/* CLOCK_TYPE_PC2CC3M_T, w/16-bit divisor (I2C) */
+	{ CLK(PERIPH),	CLK(CGENERAL2),	CLK(CGENERAL),	CLK(CGENERAL3),
+		CLK(MEMORY),	CLK(NONE),	CLK(OSC),	CLK(NONE),
+		MASK_BITS_31_29},
+	/* CLOCK_TYPE_MC2CC3P_A */
+	{ CLK(MEMORY),	CLK(CGENERAL2),	CLK(CGENERAL),	CLK(CGENERAL3),
+		CLK(PERIPH),	CLK(NONE),	CLK(AUDIO),	CLK(NONE),
+		MASK_BITS_31_29},
+	/* CLOCK_TYPE_M */
+	{ CLK(MEMORY),		CLK(NONE),	CLK(NONE),	CLK(NONE),
+		CLK(NONE),	CLK(NONE),	CLK(NONE),	CLK(NONE),
+		MASK_BITS_31_30},
+	/* CLOCK_TYPE_MCPTM2C2C3 */
+	{ CLK(MEMORY),	CLK(CGENERAL),	CLK(PERIPH),	CLK(OSC),
+		CLK(MEMORY2),	CLK(CGENERAL2),	CLK(CGENERAL3),	CLK(NONE),
+		MASK_BITS_31_29},
+	/* CLOCK_TYPE_PC2CC3T_S */
+	{ CLK(PERIPH),	CLK(CGENERAL2),	CLK(CGENERAL),	CLK(CGENERAL3),
+		CLK(OSC),	CLK(NONE),	CLK(SFROM32KHZ), CLK(NONE),
+		MASK_BITS_31_29},
+	/* CLOCK_TYPE_AC2CC3P_TS2 */
+	{ CLK(AUDIO),	CLK(CGENERAL2),	CLK(CGENERAL),	CLK(CGENERAL3),
+		CLK(PERIPH),	CLK(NONE),	CLK(OSC),	CLK(SRC2),
+		MASK_BITS_31_29},
+};
+
+/*
+ * Clock type for each peripheral clock source. We put the name in each
+ * record just so it is easy to match things up
+ */
+#define TYPE(name, type) type
+static enum clock_type_id clock_periph_type[PERIPHC_COUNT] = {
+	/* 0x00 */
+	TYPE(PERIPHC_I2S1,	CLOCK_TYPE_AXPT),
+	TYPE(PERIPHC_I2S2,	CLOCK_TYPE_AXPT),
+	TYPE(PERIPHC_SPDIF_OUT,	CLOCK_TYPE_AXPT),
+	TYPE(PERIPHC_SPDIF_IN,	CLOCK_TYPE_PC2CC3M),
+	TYPE(PERIPHC_PWM,	CLOCK_TYPE_PC2CC3S_T),
+	TYPE(PERIPHC_05h,	CLOCK_TYPE_NONE),
+	TYPE(PERIPHC_SBC2,	CLOCK_TYPE_PC2CC3M_T),
+	TYPE(PERIPHC_SBC3,	CLOCK_TYPE_PC2CC3M_T),
+
+	/* 0x08 */
+	TYPE(PERIPHC_08h,	CLOCK_TYPE_NONE),
+	TYPE(PERIPHC_I2C1,	CLOCK_TYPE_PC2CC3M_T16),
+	TYPE(PERIPHC_I2C5,	CLOCK_TYPE_PC2CC3M_T16),
+	TYPE(PERIPHC_0bh,	CLOCK_TYPE_NONE),
+	TYPE(PERIPHC_0ch,	CLOCK_TYPE_NONE),
+	TYPE(PERIPHC_SBC1,	CLOCK_TYPE_PC2CC3M_T),
+	TYPE(PERIPHC_DISP1,	CLOCK_TYPE_PMDACD2T),
+	TYPE(PERIPHC_DISP2,	CLOCK_TYPE_PMDACD2T),
+
+	/* 0x10 */
+	TYPE(PERIPHC_10h,	CLOCK_TYPE_NONE),
+	TYPE(PERIPHC_11h,	CLOCK_TYPE_NONE),
+	TYPE(PERIPHC_VI,	CLOCK_TYPE_MC2CC3P_A),
+	TYPE(PERIPHC_13h,	CLOCK_TYPE_NONE),
+	TYPE(PERIPHC_SDMMC1,	CLOCK_TYPE_PC2CC3M_T),
+	TYPE(PERIPHC_SDMMC2,	CLOCK_TYPE_PC2CC3M_T),
+	TYPE(PERIPHC_16h,	CLOCK_TYPE_NONE),
+	TYPE(PERIPHC_17h,	CLOCK_TYPE_NONE),
+
+	/* 0x18 */
+	TYPE(PERIPHC_18h,	CLOCK_TYPE_NONE),
+	TYPE(PERIPHC_SDMMC4,	CLOCK_TYPE_PC2CC3M_T),
+	TYPE(PERIPHC_VFIR,	CLOCK_TYPE_PC2CC3M_T),
+	TYPE(PERIPHC_1Bh,	CLOCK_TYPE_NONE),
+	TYPE(PERIPHC_1Ch,	CLOCK_TYPE_NONE),
+	TYPE(PERIPHC_HSI,	CLOCK_TYPE_PC2CC3M_T),
+	TYPE(PERIPHC_UART1,	CLOCK_TYPE_PC2CC3M_T),
+	TYPE(PERIPHC_UART2,	CLOCK_TYPE_PC2CC3M_T),
+
+	/* 0x20 */
+	TYPE(PERIPHC_HOST1X,	CLOCK_TYPE_MC2CC3P_A),
+	TYPE(PERIPHC_21h,	CLOCK_TYPE_NONE),
+	TYPE(PERIPHC_22h,	CLOCK_TYPE_NONE),
+	TYPE(PERIPHC_HDMI,	CLOCK_TYPE_PMDACD2T),
+	TYPE(PERIPHC_24h,	CLOCK_TYPE_NONE),
+	TYPE(PERIPHC_25h,	CLOCK_TYPE_NONE),
+	TYPE(PERIPHC_I2C2,	CLOCK_TYPE_PC2CC3M_T16),
+	TYPE(PERIPHC_EMC,	CLOCK_TYPE_MCPTM2C2C3),
+
+	/* 0x28 */
+	TYPE(PERIPHC_UART3,	CLOCK_TYPE_PC2CC3M_T),
+	TYPE(PERIPHC_29h,	CLOCK_TYPE_NONE),
+	TYPE(PERIPHC_VI_SENSOR,	CLOCK_TYPE_MC2CC3P_A),
+	TYPE(PERIPHC_2bh,	CLOCK_TYPE_NONE),
+	TYPE(PERIPHC_2ch,	CLOCK_TYPE_NONE),
+	TYPE(PERIPHC_SBC4,	CLOCK_TYPE_PC2CC3M_T),
+	TYPE(PERIPHC_I2C3,	CLOCK_TYPE_PC2CC3M_T16),
+	TYPE(PERIPHC_SDMMC3,	CLOCK_TYPE_PC2CC3M_T),
+
+	/* 0x30 */
+	TYPE(PERIPHC_UART4,	CLOCK_TYPE_PC2CC3M_T),
+	TYPE(PERIPHC_UART5,	CLOCK_TYPE_PC2CC3M_T),
+	TYPE(PERIPHC_VDE,	CLOCK_TYPE_PC2CC3M_T),
+	TYPE(PERIPHC_OWR,	CLOCK_TYPE_PC2CC3M_T),
+	TYPE(PERIPHC_NOR,	CLOCK_TYPE_PC2CC3M_T),
+	TYPE(PERIPHC_CSITE,	CLOCK_TYPE_PC2CC3M_T),
+	TYPE(PERIPHC_I2S0,	CLOCK_TYPE_AXPT),
+	TYPE(PERIPHC_DTV,	CLOCK_TYPE_NONE),
+
+	/* 0x38 */
+	TYPE(PERIPHC_38h,	CLOCK_TYPE_NONE),
+	TYPE(PERIPHC_39h,	CLOCK_TYPE_NONE),
+	TYPE(PERIPHC_3ah,	CLOCK_TYPE_NONE),
+	TYPE(PERIPHC_3bh,	CLOCK_TYPE_NONE),
+	TYPE(PERIPHC_MSENC,	CLOCK_TYPE_MC2CC3P_A),
+	TYPE(PERIPHC_TSEC,	CLOCK_TYPE_PC2CC3M_T),
+	TYPE(PERIPHC_3eh,	CLOCK_TYPE_NONE),
+	TYPE(PERIPHC_OSC,	CLOCK_TYPE_NONE),
+
+	/* 0x40 */
+	TYPE(PERIPHC_40h,	CLOCK_TYPE_NONE),	/* start with 0x3b0 */
+	TYPE(PERIPHC_MSELECT,	CLOCK_TYPE_PC2CC3M_T),
+	TYPE(PERIPHC_TSENSOR,	CLOCK_TYPE_PC2CC3T_S),
+	TYPE(PERIPHC_I2S3,	CLOCK_TYPE_AXPT),
+	TYPE(PERIPHC_I2S4,	CLOCK_TYPE_AXPT),
+	TYPE(PERIPHC_I2C4,	CLOCK_TYPE_PC2CC3M_T16),
+	TYPE(PERIPHC_SBC5,	CLOCK_TYPE_PC2CC3M_T),
+	TYPE(PERIPHC_SBC6,	CLOCK_TYPE_PC2CC3M_T),
+
+	/* 0x48 */
+	TYPE(PERIPHC_AUDIO,	CLOCK_TYPE_AC2CC3P_TS2),
+	TYPE(PERIPHC_49h,	CLOCK_TYPE_NONE),
+	TYPE(PERIPHC_DAM0,	CLOCK_TYPE_AC2CC3P_TS2),
+	TYPE(PERIPHC_DAM1,	CLOCK_TYPE_AC2CC3P_TS2),
+	TYPE(PERIPHC_DAM2,	CLOCK_TYPE_AC2CC3P_TS2),
+	TYPE(PERIPHC_HDA2CODEC2X, CLOCK_TYPE_PC2CC3M_T),
+	TYPE(PERIPHC_ACTMON,	CLOCK_TYPE_PC2CC3S_T),
+	TYPE(PERIPHC_EXTPERIPH1, CLOCK_TYPE_ASPTE),
+
+	/* 0x50 */
+	TYPE(PERIPHC_EXTPERIPH2, CLOCK_TYPE_ASPTE),
+	TYPE(PERIPHC_EXTPERIPH3, CLOCK_TYPE_ASPTE),
+	TYPE(PERIPHC_52h,	CLOCK_TYPE_NONE),
+	TYPE(PERIPHC_I2CSLOW,	CLOCK_TYPE_PC2CC3S_T),
+	TYPE(PERIPHC_SYS,	CLOCK_TYPE_NONE),
+	TYPE(PERIPHC_55h,	CLOCK_TYPE_NONE),
+	TYPE(PERIPHC_56h,	CLOCK_TYPE_NONE),
+	TYPE(PERIPHC_57h,	CLOCK_TYPE_NONE),
+
+	/* 0x58 */
+	TYPE(PERIPHC_58h,	CLOCK_TYPE_NONE),
+	TYPE(PERIPHC_59h,	CLOCK_TYPE_NONE),
+	TYPE(PERIPHC_5ah,	CLOCK_TYPE_NONE),
+	TYPE(PERIPHC_5bh,	CLOCK_TYPE_NONE),
+	TYPE(PERIPHC_SATAOOB,	CLOCK_TYPE_PCMT),
+	TYPE(PERIPHC_SATA,	CLOCK_TYPE_PCMT),
+	TYPE(PERIPHC_HDA,	CLOCK_TYPE_PC2CC3M_T),
+	TYPE(PERIPHC_5fh,	CLOCK_TYPE_NONE),
+
+	/* 0x60 */
+	TYPE(PERIPHC_XUSB_CORE_HOST, CLOCK_TYPE_NONE),
+	TYPE(PERIPHC_XUSB_FALCON, CLOCK_TYPE_NONE),
+	TYPE(PERIPHC_XUSB_FS,	CLOCK_TYPE_NONE),
+	TYPE(PERIPHC_XUSB_CORE_DEV, CLOCK_TYPE_NONE),
+	TYPE(PERIPHC_XUSB_SS,	CLOCK_TYPE_NONE),
+	TYPE(PERIPHC_CILAB,	CLOCK_TYPE_NONE),
+	TYPE(PERIPHC_CILCD,	CLOCK_TYPE_NONE),
+	TYPE(PERIPHC_CILE,	CLOCK_TYPE_NONE),
+
+	/* 0x68 */
+	TYPE(PERIPHC_DSIA_LP,	CLOCK_TYPE_NONE),
+	TYPE(PERIPHC_DSIB_LP,	CLOCK_TYPE_NONE),
+	TYPE(PERIPHC_ENTROPY,	CLOCK_TYPE_NONE),
+	TYPE(PERIPHC_DVFS_REF,	CLOCK_TYPE_NONE),
+	TYPE(PERIPHC_DVFS_SOC,	CLOCK_TYPE_NONE),
+	TYPE(PERIPHC_TRACECLKIN, CLOCK_TYPE_NONE),
+	TYPE(PERIPHC_ADX0,	CLOCK_TYPE_NONE),
+	TYPE(PERIPHC_AMX0,	CLOCK_TYPE_NONE),
+
+	/* 0x70 */
+	TYPE(PERIPHC_EMC_LATENCY, CLOCK_TYPE_NONE),
+	TYPE(PERIPHC_SOC_THERM,	CLOCK_TYPE_NONE),
+	TYPE(PERIPHC_72h,	CLOCK_TYPE_NONE),
+	TYPE(PERIPHC_73h,	CLOCK_TYPE_NONE),
+	TYPE(PERIPHC_74h,	CLOCK_TYPE_NONE),
+	TYPE(PERIPHC_75h,	CLOCK_TYPE_NONE),
+	TYPE(PERIPHC_VI_SENSOR2, CLOCK_TYPE_NONE),
+	TYPE(PERIPHC_I2C6,	CLOCK_TYPE_PC2CC3M_T16),
+
+	/* 0x78 */
+	TYPE(PERIPHC_78h,	CLOCK_TYPE_NONE),
+	TYPE(PERIPHC_EMC_DLL,	CLOCK_TYPE_MCPTM2C2C3),
+	TYPE(PERIPHC_HDMI_AUDIO, CLOCK_TYPE_NONE),
+	TYPE(PERIPHC_CLK72MHZ,	CLOCK_TYPE_NONE),
+	TYPE(PERIPHC_ADX1,	CLOCK_TYPE_AC2CC3P_TS2),
+	TYPE(PERIPHC_AMX1,	CLOCK_TYPE_AC2CC3P_TS2),
+	TYPE(PERIPHC_VIC,	CLOCK_TYPE_NONE),
+	TYPE(PERIPHC_7Fh,	CLOCK_TYPE_NONE),
+};
+
+/*
+ * This array translates a periph_id to a periphc_internal_id
+ *
+ * Not present/matched up:
+ *	uint vi_sensor;	 _VI_SENSOR_0,		0x1A8
+ *	SPDIF - which is both 0x08 and 0x0c
+ *
+ */
+#define NONE(name) (-1)
+#define OFFSET(name, value) PERIPHC_ ## name
+static s8 periph_id_to_internal_id[PERIPH_ID_COUNT] = {
+	/* Low word: 31:0 */
+	NONE(CPU),
+	NONE(COP),
+	NONE(TRIGSYS),
+	NONE(ISPB),
+	NONE(RESERVED4),
+	NONE(TMR),
+	PERIPHC_UART1,
+	PERIPHC_UART2,	/* and vfir 0x68 */
+
+	/* 8 */
+	NONE(GPIO),
+	PERIPHC_SDMMC2,
+	PERIPHC_SPDIF_IN,
+	PERIPHC_I2S1,
+	PERIPHC_I2C1,
+	NONE(RESERVED13),
+	PERIPHC_SDMMC1,
+	PERIPHC_SDMMC4,
+
+	/* 16 */
+	NONE(TCW),
+	PERIPHC_PWM,
+	PERIPHC_I2S2,
+	NONE(RESERVED19),
+	PERIPHC_VI,
+	NONE(RESERVED21),
+	NONE(USBD),
+	NONE(ISP),
+
+	/* 24 */
+	NONE(RESERVED24),
+	NONE(RESERVED25),
+	PERIPHC_DISP2,
+	PERIPHC_DISP1,
+	PERIPHC_HOST1X,
+	NONE(VCP),
+	PERIPHC_I2S0,
+	NONE(CACHE2),
+
+	/* Middle word: 63:32 */
+	NONE(MEM),
+	NONE(AHBDMA),
+	NONE(APBDMA),
+	NONE(RESERVED35),
+	NONE(RESERVED36),
+	NONE(STAT_MON),
+	NONE(RESERVED38),
+	NONE(FUSE),
+
+	/* 40 */
+	NONE(KFUSE),
+	PERIPHC_SBC1,		/* SBCx = SPIx */
+	PERIPHC_NOR,
+	NONE(RESERVED43),
+	PERIPHC_SBC2,
+	NONE(XIO),
+	PERIPHC_SBC3,
+	PERIPHC_I2C5,
+
+	/* 48 */
+	NONE(DSI),
+	NONE(RESERVED49),
+	PERIPHC_HSI,
+	PERIPHC_HDMI,
+	NONE(CSI),
+	NONE(RESERVED53),
+	PERIPHC_I2C2,
+	PERIPHC_UART3,
+
+	/* 56 */
+	NONE(MIPI_CAL),
+	PERIPHC_EMC,
+	NONE(USB2),
+	NONE(USB3),
+	NONE(RESERVED60),
+	PERIPHC_VDE,
+	NONE(BSEA),
+	NONE(BSEV),
+
+	/* Upper word 95:64 */
+	NONE(RESERVED64),
+	PERIPHC_UART4,
+	PERIPHC_UART5,
+	PERIPHC_I2C3,
+	PERIPHC_SBC4,
+	PERIPHC_SDMMC3,
+	NONE(PCIE),
+	PERIPHC_OWR,
+
+	/* 72 */
+	NONE(AFI),
+	PERIPHC_CSITE,
+	NONE(PCIEXCLK),
+	NONE(AVPUCQ),
+	NONE(LA),
+	NONE(TRACECLKIN),
+	NONE(SOC_THERM),
+	NONE(DTV),
+
+	/* 80 */
+	NONE(RESERVED80),
+	PERIPHC_I2CSLOW,
+	NONE(DSIB),
+	PERIPHC_TSEC,
+	NONE(RESERVED84),
+	NONE(RESERVED85),
+	NONE(RESERVED86),
+	NONE(EMUCIF),
+
+	/* 88 */
+	NONE(RESERVED88),
+	NONE(XUSB_HOST),
+	NONE(RESERVED90),
+	PERIPHC_MSENC,
+	NONE(RESERVED92),
+	NONE(RESERVED93),
+	NONE(RESERVED94),
+	NONE(XUSB_DEV),
+
+	/* V word: 31:0 */
+	NONE(CPUG),
+	NONE(CPULP),
+	NONE(V_RESERVED2),
+	PERIPHC_MSELECT,
+	NONE(V_RESERVED4),
+	PERIPHC_I2S3,
+	PERIPHC_I2S4,
+	PERIPHC_I2C4,
+
+	/* 104 */
+	PERIPHC_SBC5,
+	PERIPHC_SBC6,
+	PERIPHC_AUDIO,
+	NONE(APBIF),
+	PERIPHC_DAM0,
+	PERIPHC_DAM1,
+	PERIPHC_DAM2,
+	PERIPHC_HDA2CODEC2X,
+
+	/* 112 */
+	NONE(ATOMICS),
+	NONE(V_RESERVED17),
+	NONE(V_RESERVED18),
+	NONE(V_RESERVED19),
+	NONE(V_RESERVED20),
+	NONE(V_RESERVED21),
+	NONE(V_RESERVED22),
+	PERIPHC_ACTMON,
+
+	/* 120 */
+	NONE(EXTPERIPH1),
+	NONE(EXTPERIPH2),
+	NONE(EXTPERIPH3),
+	NONE(OOB),
+	PERIPHC_SATA,
+	PERIPHC_HDA,
+	NONE(TZRAM),
+	NONE(SE),
+
+	/* W word: 31:0 */
+	NONE(HDA2HDMICODEC),
+	NONE(SATACOLD),
+	NONE(W_RESERVED2),
+	NONE(W_RESERVED3),
+	NONE(W_RESERVED4),
+	NONE(W_RESERVED5),
+	NONE(W_RESERVED6),
+	NONE(W_RESERVED7),
+
+	/* 136 */
+	NONE(CEC),
+	NONE(W_RESERVED9),
+	NONE(W_RESERVED10),
+	NONE(W_RESERVED11),
+	NONE(W_RESERVED12),
+	NONE(W_RESERVED13),
+	NONE(XUSB_PADCTL),
+	NONE(W_RESERVED15),
+
+	/* 144 */
+	NONE(W_RESERVED16),
+	NONE(W_RESERVED17),
+	NONE(W_RESERVED18),
+	NONE(W_RESERVED19),
+	NONE(W_RESERVED20),
+	NONE(ENTROPY),
+	NONE(DDS),
+	NONE(W_RESERVED23),
+
+	/* 152 */
+	NONE(DP2),
+	NONE(AMX0),
+	NONE(ADX0),
+	NONE(DVFS),
+	NONE(XUSB_SS),
+	NONE(W_RESERVED29),
+	NONE(W_RESERVED30),
+	NONE(W_RESERVED31),
+
+	/* X word: 31:0 */
+	NONE(SPARE),
+	NONE(X_RESERVED1),
+	NONE(X_RESERVED2),
+	NONE(X_RESERVED3),
+	NONE(CAM_MCLK),
+	NONE(CAM_MCLK2),
+	PERIPHC_I2C6,
+	NONE(X_RESERVED7),
+
+	/* 168 */
+	NONE(X_RESERVED8),
+	NONE(X_RESERVED9),
+	NONE(X_RESERVED10),
+	NONE(VIM2_CLK),
+	NONE(X_RESERVED12),
+	NONE(X_RESERVED13),
+	NONE(EMC_DLL),
+	NONE(X_RESERVED15),
+
+	/* 176 */
+	NONE(HDMI_AUDIO),
+	NONE(CLK72MHZ),
+	NONE(VIC),
+	NONE(X_RESERVED19),
+	NONE(ADX1),
+	NONE(DPAUX),
+	NONE(SOR0),
+	NONE(X_RESERVED23),
+
+	/* 184 */
+	NONE(GPU),
+	NONE(AMX1),
+	NONE(X_RESERVED26),
+	NONE(X_RESERVED27),
+	NONE(X_RESERVED28),
+	NONE(X_RESERVED29),
+	NONE(X_RESERVED30),
+	NONE(X_RESERVED31),
+};
+
+/*
+ * Get the oscillator frequency, from the corresponding hardware configuration
+ * field. Note that Tegra30+ support 3 new higher freqs, but we map back
+ * to the old T20 freqs. Support for the higher oscillators is TBD.
+ */
+enum clock_osc_freq clock_get_osc_freq(void)
+{
+	struct clk_rst_ctlr *clkrst =
+			(struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
+	u32 reg;
+
+	reg = readl(&clkrst->crc_osc_ctrl);
+	reg = (reg & OSC_FREQ_MASK) >> OSC_FREQ_SHIFT;
+
+	if (reg & 1)				/* one of the newer freqs */
+		printf("Warning: OSC_FREQ is unsupported! (%d)\n", reg);
+
+	return reg >> 2;	/* Map to most common (T20) freqs */
+}
+
+/* Returns a pointer to the clock source register for a peripheral */
+u32 *get_periph_source_reg(enum periph_id periph_id)
+{
+	struct clk_rst_ctlr *clkrst =
+		(struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
+	enum periphc_internal_id internal_id;
+
+	/* Coresight is a special case */
+	if (periph_id == PERIPH_ID_CSI)
+		return &clkrst->crc_clk_src[PERIPH_ID_CSI+1];
+
+	assert(periph_id >= PERIPH_ID_FIRST && periph_id < PERIPH_ID_COUNT);
+	internal_id = periph_id_to_internal_id[periph_id];
+	assert(internal_id != -1);
+	if (internal_id >= PERIPHC_VW_FIRST) {
+		internal_id -= PERIPHC_VW_FIRST;
+		return &clkrst->crc_clk_src_vw[internal_id];
+	} else {
+		return &clkrst->crc_clk_src[internal_id];
+	}
+}
+
+/**
+ * Given a peripheral ID and the required source clock, this returns which
+ * value should be programmed into the source mux for that peripheral.
+ *
+ * There is special code here to handle the one source type with 5 sources.
+ *
+ * @param periph_id	peripheral to start
+ * @param source	PLL id of required parent clock
+ * @param mux_bits	Set to number of bits in mux register: 2 or 4
+ * @param divider_bits Set to number of divider bits (8 or 16)
+ * @return mux value (0-4, or -1 if not found)
+ */
+int get_periph_clock_source(enum periph_id periph_id,
+	enum clock_id parent, int *mux_bits, int *divider_bits)
+{
+	enum clock_type_id type;
+	enum periphc_internal_id internal_id;
+	int mux;
+
+	assert(clock_periph_id_isvalid(periph_id));
+
+	internal_id = periph_id_to_internal_id[periph_id];
+	assert(periphc_internal_id_isvalid(internal_id));
+
+	type = clock_periph_type[internal_id];
+	assert(clock_type_id_isvalid(type));
+
+	*mux_bits = clock_source[type][CLOCK_MAX_MUX];
+
+	if (type == CLOCK_TYPE_PC2CC3M_T16)
+		*divider_bits = 16;
+	else
+		*divider_bits = 8;
+
+	for (mux = 0; mux < CLOCK_MAX_MUX; mux++)
+		if (clock_source[type][mux] == parent)
+			return mux;
+
+	/* if we get here, either us or the caller has made a mistake */
+	printf("Caller requested bad clock: periph=%d, parent=%d\n", periph_id,
+	       parent);
+	return -1;
+}
+
+void clock_set_enable(enum periph_id periph_id, int enable)
+{
+	struct clk_rst_ctlr *clkrst =
+		(struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
+	u32 *clk;
+	u32 reg;
+
+	/* Enable/disable the clock to this peripheral */
+	assert(clock_periph_id_isvalid(periph_id));
+	if ((int)periph_id < (int)PERIPH_ID_VW_FIRST)
+		clk = &clkrst->crc_clk_out_enb[PERIPH_REG(periph_id)];
+	else
+		clk = &clkrst->crc_clk_out_enb_vw[PERIPH_REG(periph_id)];
+	reg = readl(clk);
+	if (enable)
+		reg |= PERIPH_MASK(periph_id);
+	else
+		reg &= ~PERIPH_MASK(periph_id);
+	writel(reg, clk);
+}
+
+void reset_set_enable(enum periph_id periph_id, int enable)
+{
+	struct clk_rst_ctlr *clkrst =
+		(struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
+	u32 *reset;
+	u32 reg;
+
+	/* Enable/disable reset to the peripheral */
+	assert(clock_periph_id_isvalid(periph_id));
+	if (periph_id < PERIPH_ID_VW_FIRST)
+		reset = &clkrst->crc_rst_dev[PERIPH_REG(periph_id)];
+	else
+		reset = &clkrst->crc_rst_dev_vw[PERIPH_REG(periph_id)];
+	reg = readl(reset);
+	if (enable)
+		reg |= PERIPH_MASK(periph_id);
+	else
+		reg &= ~PERIPH_MASK(periph_id);
+	writel(reg, reset);
+}
+
+#ifdef CONFIG_OF_CONTROL
+/*
+ * Convert a device tree clock ID to our peripheral ID. They are mostly
+ * the same but we are very cautious so we check that a valid clock ID is
+ * provided.
+ *
+ * @param clk_id    Clock ID according to tegra124 device tree binding
+ * @return peripheral ID, or PERIPH_ID_NONE if the clock ID is invalid
+ */
+enum periph_id clk_id_to_periph_id(int clk_id)
+{
+	if (clk_id > PERIPH_ID_COUNT)
+		return PERIPH_ID_NONE;
+
+	switch (clk_id) {
+	case PERIPH_ID_RESERVED4:
+	case PERIPH_ID_RESERVED25:
+	case PERIPH_ID_RESERVED35:
+	case PERIPH_ID_RESERVED36:
+	case PERIPH_ID_RESERVED38:
+	case PERIPH_ID_RESERVED43:
+	case PERIPH_ID_RESERVED49:
+	case PERIPH_ID_RESERVED53:
+	case PERIPH_ID_RESERVED64:
+	case PERIPH_ID_RESERVED84:
+	case PERIPH_ID_RESERVED85:
+	case PERIPH_ID_RESERVED86:
+	case PERIPH_ID_RESERVED88:
+	case PERIPH_ID_RESERVED90:
+	case PERIPH_ID_RESERVED92:
+	case PERIPH_ID_RESERVED93:
+	case PERIPH_ID_RESERVED94:
+	case PERIPH_ID_V_RESERVED2:
+	case PERIPH_ID_V_RESERVED4:
+	case PERIPH_ID_V_RESERVED17:
+	case PERIPH_ID_V_RESERVED18:
+	case PERIPH_ID_V_RESERVED19:
+	case PERIPH_ID_V_RESERVED20:
+	case PERIPH_ID_V_RESERVED21:
+	case PERIPH_ID_V_RESERVED22:
+	case PERIPH_ID_W_RESERVED2:
+	case PERIPH_ID_W_RESERVED3:
+	case PERIPH_ID_W_RESERVED4:
+	case PERIPH_ID_W_RESERVED5:
+	case PERIPH_ID_W_RESERVED6:
+	case PERIPH_ID_W_RESERVED7:
+	case PERIPH_ID_W_RESERVED9:
+	case PERIPH_ID_W_RESERVED10:
+	case PERIPH_ID_W_RESERVED11:
+	case PERIPH_ID_W_RESERVED12:
+	case PERIPH_ID_W_RESERVED13:
+	case PERIPH_ID_W_RESERVED15:
+	case PERIPH_ID_W_RESERVED16:
+	case PERIPH_ID_W_RESERVED17:
+	case PERIPH_ID_W_RESERVED18:
+	case PERIPH_ID_W_RESERVED19:
+	case PERIPH_ID_W_RESERVED20:
+	case PERIPH_ID_W_RESERVED23:
+	case PERIPH_ID_W_RESERVED29:
+	case PERIPH_ID_W_RESERVED30:
+	case PERIPH_ID_W_RESERVED31:
+		return PERIPH_ID_NONE;
+	default:
+		return clk_id;
+	}
+}
+#endif /* CONFIG_OF_CONTROL */
+
+void clock_early_init(void)
+{
+	struct clk_rst_ctlr *clkrst =
+		(struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
+
+	tegra30_set_up_pllp();
+
+	/*
+	 * PLLC output frequency set to 600Mhz
+	 * PLLD output frequency set to 925Mhz
+	 */
+	switch (clock_get_osc_freq()) {
+	case CLOCK_OSC_FREQ_12_0: /* OSC is 12Mhz */
+		clock_set_rate(CLOCK_ID_CGENERAL, 600, 12, 0, 8);
+		clock_set_rate(CLOCK_ID_DISPLAY, 925, 12, 0, 12);
+		break;
+
+	case CLOCK_OSC_FREQ_26_0: /* OSC is 26Mhz */
+		clock_set_rate(CLOCK_ID_CGENERAL, 600, 26, 0, 8);
+		clock_set_rate(CLOCK_ID_DISPLAY, 925, 26, 0, 12);
+		break;
+
+	case CLOCK_OSC_FREQ_13_0: /* OSC is 13Mhz */
+		clock_set_rate(CLOCK_ID_CGENERAL, 600, 13, 0, 8);
+		clock_set_rate(CLOCK_ID_DISPLAY, 925, 13, 0, 12);
+		break;
+	case CLOCK_OSC_FREQ_19_2:
+	default:
+		/*
+		 * These are not supported. It is too early to print a
+		 * message and the UART likely won't work anyway due to the
+		 * oscillator being wrong.
+		 */
+		break;
+	}
+
+	/* PLLC_MISC2: Set dynramp_stepA/B. MISC2 maps to pll_out[1] */
+	writel(0x00561600, &clkrst->crc_pll[CLOCK_ID_CGENERAL].pll_out[1]);
+
+	/* PLLC_MISC: Set LOCK_ENABLE */
+	writel(0x01000000, &clkrst->crc_pll[CLOCK_ID_CGENERAL].pll_misc);
+	udelay(2);
+
+	/* PLLD_MISC: Set CLKENABLE, CPCON 12, LFCON 1 */
+	writel(0x40000C10, &clkrst->crc_pll[CLOCK_ID_DISPLAY].pll_misc);
+	udelay(2);
+}
+
+void arch_timer_init(void)
+{
+	struct sysctr_ctlr *sysctr = (struct sysctr_ctlr *)NV_PA_TSC_BASE;
+	u32 freq, val;
+
+	freq = clock_get_rate(CLOCK_ID_OSC);
+	debug("%s: osc freq is %dHz [0x%08X]\n", __func__, freq, freq);
+
+	/* ARM CNTFRQ */
+	asm("mcr p15, 0, %0, c14, c0, 0\n" : : "r" (freq));
+
+	/* Only Tegra114+ has the System Counter regs */
+	debug("%s: setting CNTFID0 to 0x%08X\n", __func__, freq);
+	writel(freq, &sysctr->cntfid0);
+
+	val = readl(&sysctr->cntcr);
+	val |= TSC_CNTCR_ENABLE | TSC_CNTCR_HDBG;
+	writel(val, &sysctr->cntcr);
+	debug("%s: TSC CNTCR = 0x%08X\n", __func__, val);
+}
diff --git a/arch/arm/cpu/tegra124-common/funcmux.c b/arch/arm/cpu/tegra124-common/funcmux.c
new file mode 100644
index 0000000000..d19fda06c5
--- /dev/null
+++ b/arch/arm/cpu/tegra124-common/funcmux.c
@@ -0,0 +1,69 @@
+/*
+ * (C) Copyright 2013
+ * NVIDIA Corporation <www.nvidia.com>
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+/* Tegra124 high-level function multiplexing */
+
+#include <common.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/funcmux.h>
+#include <asm/arch/pinmux.h>
+
+int funcmux_select(enum periph_id id, int config)
+{
+	int bad_config = config != FUNCMUX_DEFAULT;
+
+	switch (id) {
+	case PERIPH_ID_UART4:
+		switch (config) {
+		case FUNCMUX_UART4_GPIO: /* TXD,RXD,CTS,RTS */
+			pinmux_set_func(PINGRP_GPIO_PJ7, PMUX_FUNC_UARTD);
+			pinmux_set_func(PINGRP_GPIO_PB0, PMUX_FUNC_UARTD);
+			pinmux_set_func(PINGRP_GPIO_PB1, PMUX_FUNC_UARTD);
+			pinmux_set_func(PINGRP_GPIO_PK7, PMUX_FUNC_UARTD);
+
+			pinmux_set_io(PINGRP_GPIO_PJ7, PMUX_PIN_OUTPUT);
+			pinmux_set_io(PINGRP_GPIO_PB0, PMUX_PIN_INPUT);
+			pinmux_set_io(PINGRP_GPIO_PB1, PMUX_PIN_INPUT);
+			pinmux_set_io(PINGRP_GPIO_PK7, PMUX_PIN_OUTPUT);
+
+			pinmux_tristate_disable(PINGRP_GPIO_PJ7);
+			pinmux_tristate_disable(PINGRP_GPIO_PB0);
+			pinmux_tristate_disable(PINGRP_GPIO_PB1);
+			pinmux_tristate_disable(PINGRP_GPIO_PK7);
+			break;
+		}
+		break;
+
+	case PERIPH_ID_UART1:
+		switch (config) {
+		case FUNCMUX_UART1_KBC:
+			pinmux_set_func(PINGRP_KB_ROW9, PMUX_FUNC_UARTA);
+			pinmux_set_func(PINGRP_KB_ROW10, PMUX_FUNC_UARTA);
+
+			pinmux_set_io(PINGRP_KB_ROW9, PMUX_PIN_OUTPUT);
+			pinmux_set_io(PINGRP_KB_ROW10, PMUX_PIN_INPUT);
+
+			pinmux_tristate_disable(PINGRP_KB_ROW9);
+			pinmux_tristate_disable(PINGRP_KB_ROW10);
+			break;
+		}
+		break;
+
+	/* Add other periph IDs here as needed */
+
+	default:
+		debug("%s: invalid periph_id %d", __func__, id);
+		return -1;
+	}
+
+	if (bad_config) {
+		debug("%s: invalid config %d for periph_id %d", __func__,
+		      config, id);
+		return -1;
+	}
+	return 0;
+}
diff --git a/arch/arm/cpu/tegra124-common/pinmux.c b/arch/arm/cpu/tegra124-common/pinmux.c
new file mode 100644
index 0000000000..a4ab4eae40
--- /dev/null
+++ b/arch/arm/cpu/tegra124-common/pinmux.c
@@ -0,0 +1,730 @@
+/*
+ * (C) Copyright 2013
+ * NVIDIA Corporation <www.nvidia.com>
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+/* Tegra124 pin multiplexing functions */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/tegra.h>
+#include <asm/arch/pinmux.h>
+
+struct tegra_pingroup_desc {
+	const char *name;
+	enum pmux_func funcs[4];
+	enum pmux_func func_safe;
+	enum pmux_vddio vddio;
+	enum pmux_pin_io io;
+};
+
+#define PMUX_MUXCTL_SHIFT	0
+#define PMUX_PULL_SHIFT		2
+#define PMUX_TRISTATE_SHIFT	4
+#define PMUX_TRISTATE_MASK	(1 << PMUX_TRISTATE_SHIFT)
+#define PMUX_IO_SHIFT		5
+#define PMUX_OD_SHIFT		6
+#define PMUX_LOCK_SHIFT		7
+#define PMUX_IO_RESET_SHIFT	8
+#define PMUX_RCV_SEL_SHIFT	9
+
+#define PGRP_HSM_SHIFT		2
+#define PGRP_SCHMT_SHIFT	3
+#define PGRP_LPMD_SHIFT		4
+#define PGRP_LPMD_MASK		(3 << PGRP_LPMD_SHIFT)
+#define PGRP_DRVDN_SHIFT	12
+#define PGRP_DRVDN_MASK		(0x7F << PGRP_DRVDN_SHIFT)
+#define PGRP_DRVUP_SHIFT	20
+#define PGRP_DRVUP_MASK		(0x7F << PGRP_DRVUP_SHIFT)
+#define PGRP_SLWR_SHIFT		28
+#define PGRP_SLWR_MASK		(3 << PGRP_SLWR_SHIFT)
+#define PGRP_SLWF_SHIFT		30
+#define PGRP_SLWF_MASK		(3 << PGRP_SLWF_SHIFT)
+
+/* Convenient macro for defining pin group properties */
+#define PIN(pg_name, vdd, f0, f1, f2, f3, iod)	\
+	{						\
+		.vddio = PMUX_VDDIO_ ## vdd,		\
+		.funcs = {				\
+			PMUX_FUNC_ ## f0,		\
+			PMUX_FUNC_ ## f1,		\
+			PMUX_FUNC_ ## f2,		\
+			PMUX_FUNC_ ## f3,		\
+		},					\
+		.func_safe = PMUX_FUNC_RSVD1,		\
+		.io = PMUX_PIN_ ## iod,			\
+	}
+
+/* Input and output pins */
+#define PINI(pg_name, vdd, f0, f1, f2, f3) \
+	PIN(pg_name, vdd, f0, f1, f2, f3, INPUT)
+#define PINO(pg_name, vdd, f0, f1, f2, f3) \
+	PIN(pg_name, vdd, f0, f1, f2, f3, OUTPUT)
+
+/* A pin group number which is not used */
+#define PIN_RESERVED \
+	PIN(NONE, NONE, INVALID, INVALID, INVALID, INVALID, NONE)
+
+const struct tegra_pingroup_desc tegra_soc_pingroups[PINGRP_COUNT] = {
+	/*	NAME	  VDD	   f0		f1	   f2	    f3  */
+	PINI(ULPI_DATA0,  BB,	   SPI3,       HSI,	   UARTA,   ULPI),
+	PINI(ULPI_DATA1,  BB,	   SPI3,       HSI,	   UARTA,   ULPI),
+	PINI(ULPI_DATA2,  BB,	   SPI3,       HSI,	   UARTA,   ULPI),
+	PINI(ULPI_DATA3,  BB,	   SPI3,	HSI,	   UARTA,   ULPI),
+	PINI(ULPI_DATA4,  BB,	   SPI2,	HSI,	   UARTA,   ULPI),
+	PINI(ULPI_DATA5,  BB,      SPI2,        HSI,       UARTA,   ULPI),
+	PINI(ULPI_DATA6,  BB,      SPI2,        HSI,       UARTA,   ULPI),
+	PINI(ULPI_DATA7,  BB,      SPI2,        HSI,       UARTA,   ULPI),
+	PINI(ULPI_CLK,    BB,      SPI1,       SPI5,       UARTD,   ULPI),
+	PINI(ULPI_DIR,    BB,      SPI1,       SPI5,       UARTD,   ULPI),
+	PINI(ULPI_NXT,    BB,      SPI1,       SPI5,       UARTD,   ULPI),
+	PINI(ULPI_STP,    BB,      SPI1,       SPI5,       UARTD,   ULPI),
+	PINI(DAP3_FS,     BB,      I2S2,       SPI5,       DISPA,   DISPB),
+	PINI(DAP3_DIN,    BB,      I2S2,       SPI5,       DISPA,   DISPB),
+	PINI(DAP3_DOUT,   BB,      I2S2,       SPI5,       DISPA,   DISPB),
+	PINI(DAP3_SCLK,   BB,      I2S2,       SPI5,       DISPA,   DISPB),
+	PINI(GPIO_PV0,    BB,      USB,        RSVD2,      RSVD3,   RSVD4),
+	PINI(GPIO_PV1,    BB,      RSVD1,      RSVD2,      RSVD3,   RSVD4),
+	PINI(SDMMC1_CLK,  SDMMC1,  SDMMC1,     CLK12,      RSVD3,   RSVD4),
+	PINI(SDMMC1_CMD,  SDMMC1,  SDMMC1,     SPDIF,      SPI4,    UARTA),
+	PINI(SDMMC1_DAT3, SDMMC1,  SDMMC1,     SPDIF,      SPI4,    UARTA),
+	PINI(SDMMC1_DAT2, SDMMC1,  SDMMC1,     PWM0,       SPI4,    UARTA),
+	PINI(SDMMC1_DAT1, SDMMC1,  SDMMC1,     PWM1,       SPI4,    UARTA),
+	PINI(SDMMC1_DAT0, SDMMC1,  SDMMC1,     RSVD2,      SPI4,    UARTA),
+	PIN_RESERVED,	/* Reserved: 0x3060 - 0x3064 */
+	PIN_RESERVED,
+	PINI(CLK2_OUT,    SDMMC1,  EXTPERIPH2, RSVD2,      RSVD3,   RSVD4),
+	PINI(CLK2_REQ,    SDMMC1,  DAP,        RSVD2,      RSVD3,   RSVD4),
+	PIN_RESERVED,	/* Reserved: 0x3070 - 0x310c */
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PINI(HDMI_INT,    LCD,     RSVD1,      RSVD2,      RSVD3,   RSVD4),
+	PINI(DDC_SCL,     LCD,     I2C4,       RSVD2,      RSVD3,   RSVD4),
+	PINI(DDC_SDA,     LCD,     I2C4,       RSVD2,      RSVD3,   RSVD4),
+	PIN_RESERVED,	/* Reserved: 0x311c - 0x3160 */
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PINI(UART2_RXD,   UART,    UARTB,      SPDIF,      UARTA,   SPI4),
+	PINI(UART2_TXD,   UART,    UARTB,      SPDIF,      UARTA,   SPI4),
+	PINI(UART2_RTS_N, UART,    UARTA,      UARTB,      RSVD3,   SPI4),
+	PINI(UART2_CTS_N, UART,    UARTA,      UARTB,      RSVD3,   SPI4),
+	PINI(UART3_TXD,   UART,    UARTC,      RSVD2,      RSVD3,   SPI4),
+	PINI(UART3_RXD,   UART,    UARTC,      RSVD2,      RSVD3,   SPI4),
+	PINI(UART3_CTS_N, UART,    UARTC,      SDMMC1,     DTV,     SPI4),
+	PINI(UART3_RTS_N, UART,    UARTC,      PWM0,       DTV,     DISPA),
+	PINI(GPIO_PU0,    UART,    OWR,        UARTA,      RSVD3,   RSVD4),
+	PINI(GPIO_PU1,    UART,    RSVD1,      UARTA,      RSVD3,   RSVD4),
+	PINI(GPIO_PU2,    UART,    RSVD1,      UARTA,      RSVD3,   RSVD4),
+	PINI(GPIO_PU3,    UART,    PWM0,       UARTA,      DISPA,   DISPB),
+	PINI(GPIO_PU4,    UART,    PWM1,       UARTA,      DISPA,   DISPB),
+	PINI(GPIO_PU5,    UART,    PWM2,       UARTA,      DISPA,   DISPB),
+	PINI(GPIO_PU6,    UART,    PWM3,       UARTA,      USB,     DISPB),
+	PINI(GEN1_I2C_SDA, UART,   I2C1,       RSVD2,      RSVD3,   RSVD4),
+	PINI(GEN1_I2C_SCL, UART,   I2C1,       RSVD2,      RSVD3,   RSVD4),
+	PINI(DAP4_FS,     UART,    I2S3,       RSVD2,      DTV,     RSVD4),
+	PINI(DAP4_DIN,    UART,    I2S3,       RSVD2,      RSVD3,   RSVD4),
+	PINI(DAP4_DOUT,   UART,    I2S3,       RSVD2,      DTV,     RSVD4),
+	PINI(DAP4_SCLK,   UART,    I2S3,       RSVD2,      RSVD3,   RSVD4),
+	PINI(CLK3_OUT,    UART,    EXTPERIPH3, RSVD2,      RSVD3,   RSVD4),
+	PINI(CLK3_REQ,    UART,    DEV3,       RSVD2,      RSVD3,   RSVD4),
+	PINI(GMI_WP_N,    GMI,     RSVD1,      NAND,       GMI,     GMI_ALT),
+	PINI(GMI_IORDY,   GMI,     SDMMC2,     RSVD2,      GMI,     TRACE),
+	PINI(GMI_WAIT,    GMI,     SPI4,       NAND,       GMI,     DTV),
+	PINI(GMI_ADV_N,   GMI,     RSVD1,      NAND,       GMI,     TRACE),
+	PINI(GMI_CLK,     GMI,     SDMMC2,     NAND,       GMI,     TRACE),
+	PINI(GMI_CS0_N,   GMI,     RSVD1,      NAND,       GMI,     USB),
+	PINI(GMI_CS1_N,   GMI,     RSVD1,      NAND,       GMI,     SOC),
+	PINI(GMI_CS2_N,   GMI,     SDMMC2,     NAND,       GMI,     TRACE),
+	PINI(GMI_CS3_N,   GMI,     SDMMC2,     NAND,       GMI,     GMI_ALT),
+	PINI(GMI_CS4_N,   GMI,     USB,        NAND,       GMI,     TRACE),
+	PINI(GMI_CS6_N,   GMI,     NAND,       NAND_ALT,   GMI,     SPI4),
+	PINI(GMI_CS7_N,   GMI,     NAND,       NAND_ALT,   GMI,     SDMMC2),
+	PINI(GMI_AD0,     GMI,     RSVD1,      NAND,       GMI,     RSVD4),
+	PINI(GMI_AD1,     GMI,     RSVD1,      NAND,       GMI,     RSVD4),
+	PINI(GMI_AD2,     GMI,     RSVD1,      NAND,       GMI,     RSVD4),
+	PINI(GMI_AD3,     GMI,     RSVD1,      NAND,       GMI,     RSVD4),
+	PINI(GMI_AD4,     GMI,     RSVD1,      NAND,       GMI,     RSVD4),
+	PINI(GMI_AD5,     GMI,     RSVD1,      NAND,       GMI,     SPI4),
+	PINI(GMI_AD6,     GMI,     RSVD1,      NAND,       GMI,     SPI4),
+	PINI(GMI_AD7,     GMI,     RSVD1,      NAND,       GMI,     SPI4),
+	PINI(GMI_AD8,     GMI,     PWM0,       NAND,       GMI,     DTV),
+	PINI(GMI_AD9,     GMI,     PWM1,       NAND,       GMI,     CLDVFS),
+	PINI(GMI_AD10,    GMI,     PWM2,       NAND,       GMI,     CLDVFS),
+	PINI(GMI_AD11,    GMI,     PWM3,       NAND,       GMI,     USB),
+	PINI(GMI_AD12,    GMI,     SDMMC2,     NAND,       GMI,     RSVD4),
+	PINI(GMI_AD13,    GMI,     SDMMC2,     NAND,       GMI,     RSVD4),
+	PINI(GMI_AD14,    GMI,     SDMMC2,     NAND,       GMI,     DTV),
+	PINI(GMI_AD15,    GMI,     SDMMC2,     NAND,       GMI,     DTV),
+	PINI(GMI_A16,     GMI,     UARTD,      TRACE,      GMI,     GMI_ALT),
+	PINI(GMI_A17,     GMI,     UARTD,      RSVD2,      GMI,     TRACE),
+	PINI(GMI_A18,     GMI,     UARTD,      RSVD2,      GMI,     TRACE),
+	PINI(GMI_A19,     GMI,     UARTD,      SPI4,       GMI,     TRACE),
+	PINI(GMI_WR_N,    GMI,     RSVD1,      NAND,       GMI,     SPI4),
+	PINI(GMI_OE_N,    GMI,     RSVD1,      NAND,       GMI,     SOC),
+	PINI(GMI_DQS,     GMI,     SDMMC2,     NAND,       GMI,     TRACE),
+	PINI(GMI_RST_N,   GMI,     NAND,       NAND_ALT,   GMI,     RSVD4),
+	PINI(GEN2_I2C_SCL, GMI,    I2C2,       RSVD2,      GMI,     RSVD4),
+	PINI(GEN2_I2C_SDA, GMI,    I2C2,       RSVD2,      GMI,     RSVD4),
+	PINI(SDMMC4_CLK,  SDMMC4,  SDMMC4,     RSVD2,      GMI,     RSVD4),
+	PINI(SDMMC4_CMD,  SDMMC4,  SDMMC4,     RSVD2,      GMI,     RSVD4),
+	PINI(SDMMC4_DAT0, SDMMC4,  SDMMC4,     SPI3,       GMI,     RSVD4),
+	PINI(SDMMC4_DAT1, SDMMC4,  SDMMC4,     SPI3,       GMI,     RSVD4),
+	PINI(SDMMC4_DAT2, SDMMC4,  SDMMC4,     SPI3,       GMI,     RSVD4),
+	PINI(SDMMC4_DAT3, SDMMC4,  SDMMC4,     SPI3,       GMI,     RSVD4),
+	PINI(SDMMC4_DAT4, SDMMC4,  SDMMC4,     SPI3,       GMI,     RSVD4),
+	PINI(SDMMC4_DAT5, SDMMC4,  SDMMC4,     SPI3,       GMI,     RSVD4),
+	PINI(SDMMC4_DAT6, SDMMC4,  SDMMC4,     SPI3,       GMI,     RSVD4),
+	PINI(SDMMC4_DAT7, SDMMC4,  SDMMC4,     RSVD2,      GMI,     RSVD4),
+	PIN_RESERVED,	/* Reserved: 0x3280 */
+	PINI(CAM_MCLK,    CAM,     VI,         VI_ALT1,    VI_ALT3, RSVD4),
+	PINI(GPIO_PCC1,   CAM,     I2S4,       RSVD2,      RSVD3,   RSVD4),
+	PINI(GPIO_PBB0,   CAM,     I2S4,       VI,         VI_ALT1, VI_ALT3),
+	PINI(CAM_I2C_SCL, CAM,     VGP1,       I2C3,       RSVD3,   RSVD4),
+	PINI(CAM_I2C_SDA, CAM,     VGP2,       I2C3,       RSVD3,   RSVD4),
+	PINI(GPIO_PBB3,   CAM,     VGP3,       DISPA,      DISPB,   RSVD4),
+	PINI(GPIO_PBB4,   CAM,     VGP4,       DISPA,      DISPB,   RSVD4),
+	PINI(GPIO_PBB5,   CAM,     VGP5,       DISPA,      DISPB,   RSVD4),
+	PINI(GPIO_PBB6,   CAM,     VGP6,       DISPA,      DISPB,   RSVD4),
+	PINI(GPIO_PBB7,   CAM,     I2S4,       RSVD2,      RSVD3,   RSVD4),
+	PINI(GPIO_PCC2,   CAM,     I2S4,       RSVD2,      RSVD3,   RSVD4),
+	PINI(JTAG_RTCK,   SYS,     RTCK,       RSVD2,      RSVD3,   RSVD4),
+	PINI(PWR_I2C_SCL, SYS,     I2CPWR,     RSVD2,      RSVD3,   RSVD4),
+	PINI(PWR_I2C_SDA, SYS,     I2CPWR,     RSVD2,      RSVD3,   RSVD4),
+	PINI(KB_ROW0,     SYS,     KBC,        RSVD2,      DTV,     RSVD4),
+	PINI(KB_ROW1,     SYS,     KBC,        RSVD2,      DTV,     RSVD4),
+	PINI(KB_ROW2,     SYS,     KBC,        RSVD2,      DTV,     SOC),
+	PINI(KB_ROW3,     SYS,     KBC,        DISPA,      RSVD3,   DISPB),
+	PINI(KB_ROW4,     SYS,     KBC,        DISPA,      SPI2,    DISPB),
+	PINI(KB_ROW5,     SYS,     KBC,        DISPA,      SPI2,    DISPB),
+	PINI(KB_ROW6,     SYS,     KBC,        DISPA,      RSVD3,   DISPB),
+	PINI(KB_ROW7,     SYS,     KBC,        RSVD2,      CLDVFS,  UARTA),
+	PINI(KB_ROW8,     SYS,     KBC,        RSVD2,      RSVD3,   UARTA),
+	PINI(KB_ROW9,     SYS,     KBC,        RSVD2,      RSVD3,   UARTA),
+	PINI(KB_ROW10,    SYS,     KBC,        RSVD2,      RSVD3,   UARTA),
+	PIN_RESERVED,	/* Reserved: 0x32e8 - 0x32f8 */
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PINI(KB_COL0,     SYS,     KBC,        USB,        SPI2,    EMC_DLL),
+	PINI(KB_COL1,     SYS,     KBC,        RSVD2,      SPI2,    EMC_DLL),
+	PINI(KB_COL2,     SYS,     KBC,        RSVD2,      SPI2,    RSVD4),
+	PINI(KB_COL3,     SYS,     KBC,        DISPA,      PWM2,    UARTA),
+	PINI(KB_COL4,     SYS,     KBC,        OWR,        SDMMC3,  UARTA),
+	PINI(KB_COL5,     SYS,     KBC,        RSVD2,      SDMMC1,  RSVD4),
+	PINI(KB_COL6,     SYS,     KBC,        RSVD2,      SPI2,    RSVD4),
+	PINI(KB_COL7,     SYS,     KBC,        RSVD2,      SPI2,    RSVD4),
+	PINI(CLK_32K_OUT, SYS,     BLINK,      SOC,        RSVD3,   RSVD4),
+	PINI(SYS_CLK_REQ, SYS,     SYSCLK,     RSVD2,      RSVD3,   RSVD4),
+	PINI(CORE_PWR_REQ, SYS,    PWRON,      RSVD2,      RSVD3,   RSVD4),
+	PINI(CPU_PWR_REQ, SYS,     CPU,        RSVD2,      RSVD3,   RSVD4),
+	PINI(PWR_INT_N,   SYS,     PMI,        RSVD2,      RSVD3,   RSVD4),
+	PINI(CLK_32K_IN,  SYS,     CLK,        RSVD2,      RSVD3,   RSVD4),
+	PINI(OWR,         SYS,     OWR,        RSVD2,      RSVD3,   RSVD4),
+	PINI(DAP1_FS,     AUDIO,   I2S0,       HDA,        GMI,     RSVD4),
+	PINI(DAP1_DIN,    AUDIO,   I2S0,       HDA,        GMI,     RSVD4),
+	PINI(DAP1_DOUT,   AUDIO,   I2S0,       HDA,        GMI,     RSVD4),
+	PINI(DAP1_SCLK,   AUDIO,   I2S0,       HDA,        GMI,     RSVD4),
+	PINI(CLK1_REQ,    AUDIO,   DAP,        DAP1,       RSVD3,   RSVD4),
+	PINI(CLK1_OUT,    AUDIO,   EXTPERIPH1, DAP2,       RSVD3,   RSVD4),
+	PINI(SPDIF_IN,    AUDIO,   SPDIF,      USB,        RSVD3,   RSVD4),
+	PINI(SPDIF_OUT,   AUDIO,   SPDIF,      RSVD2,      RSVD3,   RSVD4),
+	PINI(DAP2_FS,     AUDIO,   I2S1,       HDA,        RSVD3,   RSVD4),
+	PINI(DAP2_DIN,    AUDIO,   I2S1,       HDA,        RSVD3,   RSVD4),
+	PINI(DAP2_DOUT,   AUDIO,   I2S1,       HDA,        RSVD3,   RSVD4),
+	PINI(DAP2_SCLK,   AUDIO,   I2S1,       HDA,        RSVD3,   RSVD4),
+	PINI(DVFS_PWM,    AUDIO,   SPI6,       CLDVFS,     RSVD3,   RSVD4),
+	PINI(GPIO_X1_AUD, AUDIO,   SPI6,       RSVD2,      RSVD3,   RSVD4),
+	PINI(GPIO_X3_AUD, AUDIO,   SPI6,       SPI1,       RSVD3,   RSVD4),
+	PINI(DVFS_CLK,    AUDIO,   SPI6,       CLDVFS,     RSVD3,   RSVD4),
+	PINI(GPIO_X4_AUD, AUDIO,   RSVD1,      SPI1,       SPI2,    DAP2),
+	PINI(GPIO_X5_AUD, AUDIO,   RSVD1,      SPI1,       SPI2,    RSVD4),
+	PINI(GPIO_X6_AUD, AUDIO,   SPI6,       SPI1,       SPI2,    RSVD4),
+	PINI(GPIO_X7_AUD, AUDIO,   RSVD1,      SPI1,       SPI2,    RSVD4),
+	PIN_RESERVED,   /* Reserved: 0x3388 - 0x338c */
+	PIN_RESERVED,
+	PINI(SDMMC3_CLK,  SDMMC3,  SDMMC3,     RSVD2,      RSVD3,   SPI3),
+	PINI(SDMMC3_CMD,  SDMMC3,  SDMMC3,     PWM3,       UARTA,   SPI3),
+	PINI(SDMMC3_DAT0, SDMMC3,  SDMMC3,     RSVD2,      RSVD3,   SPI3),
+	PINI(SDMMC3_DAT1, SDMMC3,  SDMMC3,     PWM2,       UARTA,   SPI3),
+	PINI(SDMMC3_DAT2, SDMMC3,  SDMMC3,     PWM1,       DISPA,   SPI3),
+	PINI(SDMMC3_DAT3, SDMMC3,  SDMMC3,     PWM0,       DISPB,   SPI3),
+	PIN_RESERVED,   /* Reserved: 0x33a8 - 0x33dc */
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PINI(HDMI_CEC,    SYS,     CEC,        SDMMC3,     RSVD3,   SOC),
+	PINI(SDMMC1_WP_N, SDMMC1,  SDMMC1,     CLK12,      SPI4,    UARTA),
+	PINI(SDMMC3_CD_N, SYS,  SDMMC3,     OWR,        RSVD3,   RSVD4),
+	PINI(GPIO_W2_AUD, AUDIO,   SPI6,       RSVD2,      SPI2,    I2C1),
+	PINI(GPIO_W3_AUD, AUDIO,   SPI6,       SPI1,       SPI2,    I2C1),
+	PINI(USB_VBUS_EN0, LCD,    USB,        RSVD2,      RSVD3,   RSVD4),
+	PINI(USB_VBUS_EN1, LCD,    USB,        RSVD2,      RSVD3,   RSVD4),
+	PINI(SDMMC3_CLK_LB_IN,  SDMMC3, SDMMC3, RSVD2,     RSVD3,   RSVD4),
+	PINI(SDMMC3_CLK_LB_OUT, SDMMC3, SDMMC3, RSVD2,     RSVD3,   RSVD4),
+	PIN_RESERVED,	/* Reserved: 0x3404 */
+	PINO(RESET_OUT_N, SYS,     RSVD1,      RSVD2,      RSVD3, RESET_OUT_N),
+};
+
+void pinmux_set_tristate(enum pmux_pingrp pin, int enable)
+{
+	struct pmux_tri_ctlr *pmt =
+			(struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
+	u32 *tri = &pmt->pmt_ctl[pin];
+	u32 reg;
+
+	/* Error check on pin */
+	assert(pmux_pingrp_isvalid(pin));
+
+	reg = readl(tri);
+	if (enable)
+		reg |= PMUX_TRISTATE_MASK;
+	else
+		reg &= ~PMUX_TRISTATE_MASK;
+	writel(reg, tri);
+}
+
+void pinmux_tristate_enable(enum pmux_pingrp pin)
+{
+	pinmux_set_tristate(pin, 1);
+}
+
+void pinmux_tristate_disable(enum pmux_pingrp pin)
+{
+	pinmux_set_tristate(pin, 0);
+}
+
+void pinmux_set_pullupdown(enum pmux_pingrp pin, enum pmux_pull pupd)
+{
+	struct pmux_tri_ctlr *pmt =
+			(struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
+	u32 *pull = &pmt->pmt_ctl[pin];
+	u32 reg;
+
+	/* Error check on pin and pupd */
+	assert(pmux_pingrp_isvalid(pin));
+	assert(pmux_pin_pupd_isvalid(pupd));
+
+	reg = readl(pull);
+	reg &= ~(0x3 << PMUX_PULL_SHIFT);
+	reg |= (pupd << PMUX_PULL_SHIFT);
+	writel(reg, pull);
+}
+
+void pinmux_set_func(enum pmux_pingrp pin, enum pmux_func func)
+{
+	struct pmux_tri_ctlr *pmt =
+			(struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
+	u32 *muxctl = &pmt->pmt_ctl[pin];
+	int i, mux = -1;
+	u32 reg;
+
+	/* Error check on pin and func */
+	assert(pmux_pingrp_isvalid(pin));
+	assert(pmux_func_isvalid(func));
+
+	/* Handle special values */
+	if (func == PMUX_FUNC_SAFE)
+		func = tegra_soc_pingroups[pin].func_safe;
+
+	if (func & PMUX_FUNC_RSVD1) {
+		mux = func & 0x3;
+	} else {
+		/* Search for the appropriate function */
+		for (i = 0; i < 4; i++) {
+			if (tegra_soc_pingroups[pin].funcs[i] == func) {
+				mux = i;
+				break;
+			}
+		}
+	}
+	assert(mux != -1);
+
+	reg = readl(muxctl);
+	reg &= ~(0x3 << PMUX_MUXCTL_SHIFT);
+	reg |= (mux << PMUX_MUXCTL_SHIFT);
+	writel(reg, muxctl);
+}
+
+void pinmux_set_io(enum pmux_pingrp pin, enum pmux_pin_io io)
+{
+	struct pmux_tri_ctlr *pmt =
+			(struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
+	u32 *pin_io = &pmt->pmt_ctl[pin];
+	u32 reg;
+
+	/* Error check on pin and io */
+	assert(pmux_pingrp_isvalid(pin));
+	assert(pmux_pin_io_isvalid(io));
+
+	reg = readl(pin_io);
+	reg &= ~(0x1 << PMUX_IO_SHIFT);
+	reg |= (io & 0x1) << PMUX_IO_SHIFT;
+	writel(reg, pin_io);
+}
+
+static int pinmux_set_lock(enum pmux_pingrp pin, enum pmux_pin_lock lock)
+{
+	struct pmux_tri_ctlr *pmt =
+			(struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
+	u32 *pin_lock = &pmt->pmt_ctl[pin];
+	u32 reg;
+
+	/* Error check on pin and lock */
+	assert(pmux_pingrp_isvalid(pin));
+	assert(pmux_pin_lock_isvalid(lock));
+
+	if (lock == PMUX_PIN_LOCK_DEFAULT)
+		return 0;
+
+	reg = readl(pin_lock);
+	reg &= ~(0x1 << PMUX_LOCK_SHIFT);
+	if (lock == PMUX_PIN_LOCK_ENABLE) {
+		reg |= (0x1 << PMUX_LOCK_SHIFT);
+	} else {
+		/* lock == DISABLE, which isn't possible */
+		printf("%s: Warning: lock == %d, DISABLE is not allowed!\n",
+		       __func__, lock);
+	}
+	writel(reg, pin_lock);
+
+	return 0;
+}
+
+static int pinmux_set_od(enum pmux_pingrp pin, enum pmux_pin_od od)
+{
+	struct pmux_tri_ctlr *pmt =
+			(struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
+	u32 *pin_od = &pmt->pmt_ctl[pin];
+	u32 reg;
+
+	/* Error check on pin and od */
+	assert(pmux_pingrp_isvalid(pin));
+	assert(pmux_pin_od_isvalid(od));
+
+	if (od == PMUX_PIN_OD_DEFAULT)
+		return 0;
+
+	reg = readl(pin_od);
+	reg &= ~(0x1 << PMUX_OD_SHIFT);
+	if (od == PMUX_PIN_OD_ENABLE)
+		reg |= (0x1 << PMUX_OD_SHIFT);
+	writel(reg, pin_od);
+
+	return 0;
+}
+
+static int pinmux_set_ioreset(enum pmux_pingrp pin,
+				enum pmux_pin_ioreset ioreset)
+{
+	struct pmux_tri_ctlr *pmt =
+			(struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
+	u32 *pin_ioreset = &pmt->pmt_ctl[pin];
+	u32 reg;
+
+	/* Error check on pin and ioreset */
+	assert(pmux_pingrp_isvalid(pin));
+	assert(pmux_pin_ioreset_isvalid(ioreset));
+
+	if (ioreset == PMUX_PIN_IO_RESET_DEFAULT)
+		return 0;
+
+	reg = readl(pin_ioreset);
+	reg &= ~(0x1 << PMUX_IO_RESET_SHIFT);
+	if (ioreset == PMUX_PIN_IO_RESET_ENABLE)
+		reg |= (0x1 << PMUX_IO_RESET_SHIFT);
+	writel(reg, pin_ioreset);
+
+	return 0;
+}
+
+static int pinmux_set_rcv_sel(enum pmux_pingrp pin,
+				enum pmux_pin_rcv_sel rcv_sel)
+{
+	struct pmux_tri_ctlr *pmt =
+			(struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
+	u32 *pin_rcv_sel = &pmt->pmt_ctl[pin];
+	u32 reg;
+
+	/* Error check on pin and rcv_sel */
+	assert(pmux_pingrp_isvalid(pin));
+	assert(pmux_pin_rcv_sel_isvalid(rcv_sel));
+
+	if (rcv_sel == PMUX_PIN_RCV_SEL_DEFAULT)
+		return 0;
+
+	reg = readl(pin_rcv_sel);
+	reg &= ~(0x1 << PMUX_RCV_SEL_SHIFT);
+	if (rcv_sel == PMUX_PIN_RCV_SEL_HIGH)
+		reg |= (0x1 << PMUX_RCV_SEL_SHIFT);
+	writel(reg, pin_rcv_sel);
+
+	return 0;
+}
+
+void pinmux_config_pingroup(struct pingroup_config *config)
+{
+	enum pmux_pingrp pin = config->pingroup;
+
+	pinmux_set_func(pin, config->func);
+	pinmux_set_pullupdown(pin, config->pull);
+	pinmux_set_tristate(pin, config->tristate);
+	pinmux_set_io(pin, config->io);
+	pinmux_set_lock(pin, config->lock);
+	pinmux_set_od(pin, config->od);
+	pinmux_set_ioreset(pin, config->ioreset);
+	pinmux_set_rcv_sel(pin, config->rcv_sel);
+}
+
+void pinmux_config_table(struct pingroup_config *config, int len)
+{
+	int i;
+
+	for (i = 0; i < len; i++)
+		pinmux_config_pingroup(&config[i]);
+}
+
+static int padgrp_set_drvup_slwf(enum pdrive_pingrp pad, int slwf)
+{
+	struct pmux_tri_ctlr *pmt =
+			(struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
+	u32 *pad_slwf = &pmt->pmt_drive[pad];
+	u32 reg;
+
+	/* Error check on pad and slwf */
+	assert(pmux_padgrp_isvalid(pad));
+	assert(pmux_pad_slw_isvalid(slwf));
+
+	/* NONE means unspecified/do not change/use POR value */
+	if (slwf == PGRP_SLWF_NONE)
+		return 0;
+
+	reg = readl(pad_slwf);
+	reg &= ~PGRP_SLWF_MASK;
+	reg |= (slwf << PGRP_SLWF_SHIFT);
+	writel(reg, pad_slwf);
+
+	return 0;
+}
+
+static int padgrp_set_drvdn_slwr(enum pdrive_pingrp pad, int slwr)
+{
+	struct pmux_tri_ctlr *pmt =
+			(struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
+	u32 *pad_slwr = &pmt->pmt_drive[pad];
+	u32 reg;
+
+	/* Error check on pad and slwr */
+	assert(pmux_padgrp_isvalid(pad));
+	assert(pmux_pad_slw_isvalid(slwr));
+
+	/* NONE means unspecified/do not change/use POR value */
+	if (slwr == PGRP_SLWR_NONE)
+		return 0;
+
+	reg = readl(pad_slwr);
+	reg &= ~PGRP_SLWR_MASK;
+	reg |= (slwr << PGRP_SLWR_SHIFT);
+	writel(reg, pad_slwr);
+
+	return 0;
+}
+
+static int padgrp_set_drvup(enum pdrive_pingrp pad, int drvup)
+{
+	struct pmux_tri_ctlr *pmt =
+			(struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
+	u32 *pad_drvup = &pmt->pmt_drive[pad];
+	u32 reg;
+
+	/* Error check on pad and drvup */
+	assert(pmux_padgrp_isvalid(pad));
+	assert(pmux_pad_drv_isvalid(drvup));
+
+	/* NONE means unspecified/do not change/use POR value */
+	if (drvup == PGRP_DRVUP_NONE)
+		return 0;
+
+	reg = readl(pad_drvup);
+	reg &= ~PGRP_DRVUP_MASK;
+	reg |= (drvup << PGRP_DRVUP_SHIFT);
+	writel(reg, pad_drvup);
+
+	return 0;
+}
+
+static int padgrp_set_drvdn(enum pdrive_pingrp pad, int drvdn)
+{
+	struct pmux_tri_ctlr *pmt =
+			(struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
+	u32 *pad_drvdn = &pmt->pmt_drive[pad];
+	u32 reg;
+
+	/* Error check on pad and drvdn */
+	assert(pmux_padgrp_isvalid(pad));
+	assert(pmux_pad_drv_isvalid(drvdn));
+
+	/* NONE means unspecified/do not change/use POR value */
+	if (drvdn == PGRP_DRVDN_NONE)
+		return 0;
+
+	reg = readl(pad_drvdn);
+	reg &= ~PGRP_DRVDN_MASK;
+	reg |= (drvdn << PGRP_DRVDN_SHIFT);
+	writel(reg, pad_drvdn);
+
+	return 0;
+}
+
+static int padgrp_set_lpmd(enum pdrive_pingrp pad, enum pgrp_lpmd lpmd)
+{
+	struct pmux_tri_ctlr *pmt =
+			(struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
+	u32 *pad_lpmd = &pmt->pmt_drive[pad];
+	u32 reg;
+
+	/* Error check pad and lpmd value */
+	assert(pmux_padgrp_isvalid(pad));
+	assert(pmux_pad_lpmd_isvalid(lpmd));
+
+	/* NONE means unspecified/do not change/use POR value */
+	if (lpmd == PGRP_LPMD_NONE)
+		return 0;
+
+	reg = readl(pad_lpmd);
+	reg &= ~PGRP_LPMD_MASK;
+	reg |= (lpmd << PGRP_LPMD_SHIFT);
+	writel(reg, pad_lpmd);
+
+	return 0;
+}
+
+static int padgrp_set_schmt(enum pdrive_pingrp pad, enum pgrp_schmt schmt)
+{
+	struct pmux_tri_ctlr *pmt =
+			(struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
+	u32 *pad_schmt = &pmt->pmt_drive[pad];
+	u32 reg;
+
+	/* Error check pad */
+	assert(pmux_padgrp_isvalid(pad));
+
+	/* NONE means unspecified/do not change/use POR value */
+	if (schmt == PGRP_SCHMT_NONE)
+		return 0;
+
+	reg = readl(pad_schmt);
+	reg &= ~(1 << PGRP_SCHMT_SHIFT);
+	if (schmt == PGRP_SCHMT_ENABLE)
+		reg |= (0x1 << PGRP_SCHMT_SHIFT);
+	writel(reg, pad_schmt);
+
+	return 0;
+}
+static int padgrp_set_hsm(enum pdrive_pingrp pad, enum pgrp_hsm hsm)
+{
+	struct pmux_tri_ctlr *pmt =
+			(struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
+	u32 *pad_hsm = &pmt->pmt_drive[pad];
+	u32 reg;
+
+	/* Error check pad */
+	assert(pmux_padgrp_isvalid(pad));
+
+	/* NONE means unspecified/do not change/use POR value */
+	if (hsm == PGRP_HSM_NONE)
+		return 0;
+
+	reg = readl(pad_hsm);
+	reg &= ~(1 << PGRP_HSM_SHIFT);
+	if (hsm == PGRP_HSM_ENABLE)
+		reg |= (0x1 << PGRP_HSM_SHIFT);
+	writel(reg, pad_hsm);
+
+	return 0;
+}
+
+void padctrl_config_pingroup(struct padctrl_config *config)
+{
+	enum pdrive_pingrp pad = config->padgrp;
+
+	padgrp_set_drvup_slwf(pad, config->slwf);
+	padgrp_set_drvdn_slwr(pad, config->slwr);
+	padgrp_set_drvup(pad, config->drvup);
+	padgrp_set_drvdn(pad, config->drvdn);
+	padgrp_set_lpmd(pad, config->lpmd);
+	padgrp_set_schmt(pad, config->schmt);
+	padgrp_set_hsm(pad, config->hsm);
+}
+
+void padgrp_config_table(struct padctrl_config *config, int len)
+{
+	int i;
+
+	for (i = 0; i < len; i++)
+		padctrl_config_pingroup(&config[i]);
+}
diff --git a/arch/arm/cpu/tegra20-common/Makefile b/arch/arm/cpu/tegra20-common/Makefile
index 175387fd65..0e4b3fc1dd 100644
--- a/arch/arm/cpu/tegra20-common/Makefile
+++ b/arch/arm/cpu/tegra20-common/Makefile
@@ -7,32 +7,11 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
 # The AVP is ARMv4T architecture so we must use special compiler
 # flags for any startup files it might use.
-CFLAGS_arch/arm/cpu/tegra20-common/warmboot_avp.o += -march=armv4t
-
-LIB	= $(obj)lib$(SOC)-common.o
-
-COBJS-y	+= clock.o funcmux.o pinmux.o
-COBJS-$(CONFIG_TEGRA_LP0) += warmboot.o crypto.o warmboot_avp.o
-COBJS-$(CONFIG_TEGRA_CLOCK_SCALING) += emc.o
-COBJS-$(CONFIG_TEGRA_PMU) += pmu.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
-OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS-y))
-
-all:	$(obj).depend $(LIB)
-
-$(LIB):	$(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
+CFLAGS_warmboot_avp.o += -march=armv4t
 
-#########################################################################
+obj-y	+= clock.o funcmux.o pinmux.o
+obj-$(CONFIG_TEGRA_LP0) += warmboot.o crypto.o warmboot_avp.o
+obj-$(CONFIG_TEGRA_CLOCK_SCALING) += emc.o
+obj-$(CONFIG_TEGRA_PMU) += pmu.o
diff --git a/arch/arm/cpu/tegra20-common/clock.c b/arch/arm/cpu/tegra20-common/clock.c
index 34124f9bba..0c4f5fb288 100644
--- a/arch/arm/cpu/tegra20-common/clock.c
+++ b/arch/arm/cpu/tegra20-common/clock.c
@@ -412,9 +412,9 @@ int get_periph_clock_source(enum periph_id periph_id,
 	 * with its 16-bit divisor
 	 */
 	if (type == CLOCK_TYPE_PCXTS)
-		*mux_bits = 4;
+		*mux_bits = MASK_BITS_31_28;
 	else
-		*mux_bits = 2;
+		*mux_bits = MASK_BITS_31_30;
 	if (type == CLOCK_TYPE_PCMT16)
 		*divider_bits = 16;
 	else
diff --git a/arch/arm/cpu/tegra30-common/Makefile b/arch/arm/cpu/tegra30-common/Makefile
index 75fef32b0d..d2d616e8a4 100644
--- a/arch/arm/cpu/tegra30-common/Makefile
+++ b/arch/arm/cpu/tegra30-common/Makefile
@@ -17,28 +17,4 @@
 # along with this program.  If not, see <http://www.gnu.org/licenses/>.
 #
 
-include $(TOPDIR)/config.mk
-
-# The AVP is ARMv4T architecture so we must use special compiler
-# flags for any startup files it might use.
-
-LIB	= $(obj)lib$(SOC)-common.o
-
-COBJS-y	+= clock.o funcmux.o pinmux.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
-OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS-y))
-
-all:	$(obj).depend $(LIB)
-
-$(LIB):	$(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	+= clock.o funcmux.o pinmux.o
diff --git a/arch/arm/cpu/tegra30-common/clock.c b/arch/arm/cpu/tegra30-common/clock.c
index 74bd22be1a..80ba2d8c1c 100644
--- a/arch/arm/cpu/tegra30-common/clock.c
+++ b/arch/arm/cpu/tegra30-common/clock.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2010-2013, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2010-2014, NVIDIA CORPORATION.  All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms and conditions of the GNU General Public License,
@@ -60,12 +60,6 @@ enum {
 	CLOCK_MAX_MUX   = 8     /* number of source options for each clock */
 };
 
-enum {
-	MASK_BITS_31_30 = 2,    /* num of bits used to specify clock source */
-	MASK_BITS_31_29,
-	MASK_BITS_29_28,
-};
-
 /*
  * Clock source mux for each clock type. This just converts our enum into
  * a list of mux sources for use by the code.
@@ -108,7 +102,7 @@ static enum clock_id clock_source[CLOCK_TYPE_COUNT][CLOCK_MAX_MUX+1] = {
 		MASK_BITS_31_29},
 	{ CLK(PERIPH),  CLK(CGENERAL),  CLK(SFROM32KHZ), CLK(OSC),
 		CLK(NONE),      CLK(NONE),      CLK(NONE),      CLK(NONE),
-		MASK_BITS_29_28}
+		MASK_BITS_31_28}
 };
 
 /*
@@ -587,34 +581,7 @@ enum periph_id clk_id_to_periph_id(int clk_id)
 
 void clock_early_init(void)
 {
-	/*
-	 * PLLP output frequency set to 408Mhz
-	 * PLLC output frequency set to 228Mhz
-	 */
-	switch (clock_get_osc_freq()) {
-	case CLOCK_OSC_FREQ_12_0: /* OSC is 12Mhz */
-		clock_set_rate(CLOCK_ID_PERIPH, 408, 12, 0, 8);
-		clock_set_rate(CLOCK_ID_CGENERAL, 456, 12, 1, 8);
-		break;
-
-	case CLOCK_OSC_FREQ_26_0: /* OSC is 26Mhz */
-		clock_set_rate(CLOCK_ID_PERIPH, 408, 26, 0, 8);
-		clock_set_rate(CLOCK_ID_CGENERAL, 600, 26, 0, 8);
-		break;
-
-	case CLOCK_OSC_FREQ_13_0: /* OSC is 13Mhz */
-		clock_set_rate(CLOCK_ID_PERIPH, 408, 13, 0, 8);
-		clock_set_rate(CLOCK_ID_CGENERAL, 600, 13, 0, 8);
-		break;
-	case CLOCK_OSC_FREQ_19_2:
-	default:
-		/*
-		 * These are not supported. It is too early to print a
-		 * message and the UART likely won't work anyway due to the
-		 * oscillator being wrong.
-		 */
-		break;
-	}
+	tegra30_set_up_pllp();
 }
 
 void arch_timer_init(void)
diff --git a/arch/arm/cpu/u-boot-spl.lds b/arch/arm/cpu/u-boot-spl.lds
index 36cc54a292..3e886680e8 100644
--- a/arch/arm/cpu/u-boot-spl.lds
+++ b/arch/arm/cpu/u-boot-spl.lds
@@ -42,7 +42,12 @@ SECTIONS
 		__rel_dyn_end = .;
 	}
 
-	_end = .;
+	.end :
+	{
+		*(.__end)
+	}
+
+	_image_binary_end = .;
 
 	.bss __rel_dyn_start (OVERLAY) : {
 		__bss_start = .;
@@ -51,12 +56,15 @@ SECTIONS
 		__bss_end = .;
 	}
 
-	/DISCARD/ : { *(.dynsym) }
-	/DISCARD/ : { *(.dynstr*) }
-	/DISCARD/ : { *(.dynamic*) }
-	/DISCARD/ : { *(.plt*) }
-	/DISCARD/ : { *(.interp*) }
-	/DISCARD/ : { *(.gnu*) }
+	.dynsym _image_binary_end : { *(.dynsym) }
+	.dynbss : { *(.dynbss) }
+	.dynstr : { *(.dynstr*) }
+	.dynamic : { *(.dynamic*) }
+	.hash : { *(.hash*) }
+	.plt : { *(.plt*) }
+	.interp : { *(.interp*) }
+	.gnu : { *(.gnu*) }
+	.ARM.exidx : { *(.ARM.exidx*) }
 }
 
 #if defined(CONFIG_SPL_MAX_SIZE)
diff --git a/arch/arm/cpu/u-boot.lds b/arch/arm/cpu/u-boot.lds
index 23bf030655..33c1f99fc0 100644
--- a/arch/arm/cpu/u-boot.lds
+++ b/arch/arm/cpu/u-boot.lds
@@ -60,7 +60,12 @@ SECTIONS
 		*(.__rel_dyn_end)
 	}
 
-	_end = .;
+	.end :
+	{
+		*(.__end)
+	}
+
+	_image_binary_end = .;
 
 	/*
 	 * Deprecated: this MMU section is used by pxa at present but
@@ -91,12 +96,14 @@ SECTIONS
 		KEEP(*(.__bss_end));
 	}
 
-	/DISCARD/ : { *(.dynsym) }
-	/DISCARD/ : { *(.dynstr*) }
-	/DISCARD/ : { *(.dynamic*) }
-	/DISCARD/ : { *(.plt*) }
-	/DISCARD/ : { *(.interp*) }
-	/DISCARD/ : { *(.gnu*) }
-	/DISCARD/ : { *(.ARM.exidx*) }
-	/DISCARD/ : { *(.gnu.linkonce.armexidx.*) }
+	.dynsym _image_binary_end : { *(.dynsym) }
+	.dynbss : { *(.dynbss) }
+	.dynstr : { *(.dynstr*) }
+	.dynamic : { *(.dynamic*) }
+	.plt : { *(.plt*) }
+	.interp : { *(.interp*) }
+	.gnu.hash : { *(.gnu.hash) }
+	.gnu : { *(.gnu*) }
+	.ARM.exidx : { *(.ARM.exidx*) }
+	.gnu.linkonce.armexidx : { *(.gnu.linkonce.armexidx.*) }
 }
diff --git a/arch/arm/dts/.gitignore b/arch/arm/dts/.gitignore
new file mode 100644
index 0000000000..b60ed208c7
--- /dev/null
+++ b/arch/arm/dts/.gitignore
@@ -0,0 +1 @@
+*.dtb
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
new file mode 100644
index 0000000000..2c3c773306
--- /dev/null
+++ b/arch/arm/dts/Makefile
@@ -0,0 +1,42 @@
+dtb-$(CONFIG_EXYNOS4) += exynos4210-origen.dtb \
+	exynos4210-universal_c210.dtb \
+	exynos4210-trats.dtb \
+	exynos4412-trats2.dtb
+
+dtb-$(CONFIG_EXYNOS5) += exynos5250-arndale.dtb \
+	exynos5250-snow.dtb \
+	exynos5250-smdk5250.dtb \
+	exynos5420-smdk5420.dtb
+dtb-$(CONFIG_MX6) += imx6q-sabreauto.dtb
+dtb-$(CONFIG_TEGRA) += tegra20-harmony.dtb \
+	tegra20-medcom-wide.dtb \
+	tegra20-paz00.dtb \
+	tegra20-plutux.dtb \
+	tegra20-seaboard.dtb \
+	tegra20-tec.dtb \
+	tegra20-trimslice.dtb \
+	tegra20-ventana.dtb \
+	tegra20-whistler.dtb \
+	tegra20-colibri_t20_iris.dtb \
+	tegra30-beaver.dtb \
+	tegra30-cardhu.dtb \
+	tegra30-tec-ng.dtb \
+	tegra114-dalmore.dtb \
+	tegra124-venice2.dtb
+dtb-$(CONFIG_ZYNQ) += zynq-zc702.dtb \
+	zynq-zc706.dtb \
+	zynq-zed.dtb \
+	zynq-microzed.dtb \
+	zynq-zc770-xm010.dtb \
+	zynq-zc770-xm012.dtb \
+	zynq-zc770-xm013.dtb
+
+targets += $(dtb-y)
+
+DTC_FLAGS += -R 4 -p 0x1000
+
+PHONY += dtbs
+dtbs: $(addprefix $(obj)/, $(dtb-y))
+	@:
+
+clean-files := *.dtb
diff --git a/arch/arm/dts/exynos4.dtsi b/arch/arm/dts/exynos4.dtsi
new file mode 100644
index 0000000000..71dc7ebf4a
--- /dev/null
+++ b/arch/arm/dts/exynos4.dtsi
@@ -0,0 +1,138 @@
+/*
+ * Samsung's Exynos4 SoC common device tree source
+ *
+ * Copyright (c) 2014 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/include/ "skeleton.dtsi"
+
+/ {
+	serial@13800000 {
+		compatible = "samsung,exynos4210-uart";
+		reg = <0x13800000 0x3c>;
+		id = <0>;
+	};
+
+	serial@13810000 {
+		compatible = "samsung,exynos4210-uart";
+		reg = <0x13810000 0x3c>;
+		id = <1>;
+	};
+
+	serial@13820000 {
+		compatible = "samsung,exynos4210-uart";
+		reg = <0x13820000 0x3c>;
+		id = <2>;
+	};
+
+	serial@13830000 {
+		compatible = "samsung,exynos4210-uart";
+		reg = <0x13830000 0x3c>;
+		id = <3>;
+	};
+
+	serial@13840000 {
+		compatible = "samsung,exynos4210-uart";
+		reg = <0x13840000 0x3c>;
+		id = <4>;
+	};
+
+	i2c@13860000 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "samsung,s3c2440-i2c";
+		interrupts = <0 0 0>;
+	};
+
+	i2c@13870000 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "samsung,s3c2440-i2c";
+		interrupts = <1 1 0>;
+	};
+
+	i2c@13880000 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "samsung,s3c2440-i2c";
+		interrupts = <2 2 0>;
+	};
+
+	i2c@13890000 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "samsung,s3c2440-i2c";
+		interrupts = <3 3 0>;
+	};
+
+	i2c@138a0000 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "samsung,s3c2440-i2c";
+		interrupts = <4 4 0>;
+	};
+
+	i2c@138b0000 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "samsung,s3c2440-i2c";
+		interrupts = <5 5 0>;
+	};
+
+	i2c@138c0000 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "samsung,s3c2440-i2c";
+		interrupts = <6 6 0>;
+	};
+
+	i2c@138d0000 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "samsung,s3c2440-i2c";
+		interrupts = <7 7 0>;
+	};
+
+	sdhci@12510000 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "samsung,exynos-mmc";
+		reg = <0x12510000 0x1000>;
+		interrupts = <0 75 0>;
+	};
+
+	sdhci@12520000 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "samsung,exynos-mmc";
+		reg = <0x12520000 0x1000>;
+		interrupts = <0 76 0>;
+	};
+
+	sdhci@12530000 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "samsung,exynos-mmc";
+		reg = <0x12530000 0x1000>;
+		interrupts = <0 77 0>;
+	};
+
+	sdhci@12540000 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "samsung,exynos-mmc";
+		reg = <0x12540000 0x1000>;
+		interrupts = <0 78 0>;
+	};
+
+	gpio: gpio {
+		gpio-controller;
+		#gpio-cells = <2>;
+
+		interrupt-controller;
+		#interrupt-cells = <2>;
+	};
+};
diff --git a/arch/arm/dts/exynos4210-origen.dts b/arch/arm/dts/exynos4210-origen.dts
new file mode 100644
index 0000000000..5c9d2aed68
--- /dev/null
+++ b/arch/arm/dts/exynos4210-origen.dts
@@ -0,0 +1,45 @@
+/*
+ * Samsung's Exynos4210 based Origen board device tree source
+ *
+ * Copyright (c) 2014 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/dts-v1/;
+/include/ "skeleton.dtsi"
+/include/ "exynos4.dtsi"
+
+/ {
+	model = "Insignal Origen evaluation board based on Exynos4210";
+	compatible = "insignal,origen", "samsung,exynos4210";
+
+	chosen {
+		bootargs ="";
+	};
+
+	aliases {
+		serial0 = "/serial@13800000";
+		console = "/serial@13820000";
+		mmc2 = "sdhci@12530000";
+	};
+
+	sdhci@12510000 {
+		status = "disabled";
+	};
+
+	sdhci@12520000 {
+		status = "disabled";
+	};
+
+	sdhci@12530000 {
+		samsung,bus-width = <4>;
+		samsung,timing = <1 2 3>;
+		cd-gpios = <&gpio 0x2008002 0>;
+	};
+
+	sdhci@12540000 {
+		status = "disabled";
+	};
+};
\ No newline at end of file
diff --git a/arch/arm/dts/exynos4210-trats.dts b/arch/arm/dts/exynos4210-trats.dts
new file mode 100644
index 0000000000..992e0234c9
--- /dev/null
+++ b/arch/arm/dts/exynos4210-trats.dts
@@ -0,0 +1,120 @@
+/*
+ * Samsung's Exynos4210 based Trats board device tree source
+ *
+ * Copyright (c) 2014 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/dts-v1/;
+/include/ "exynos4.dtsi"
+
+/ {
+	model = "Samsung Trats based on Exynos4210";
+	compatible = "samsung,trats", "samsung,exynos4210";
+
+	config {
+		samsung,dsim-device-name = "s6e8ax0";
+	};
+
+	aliases {
+		i2c0 = "/i2c@13860000";
+		i2c1 = "/i2c@13870000";
+		i2c2 = "/i2c@13880000";
+		i2c3 = "/i2c@13890000";
+		i2c4 = "/i2c@138a0000";
+		i2c5 = "/i2c@138b0000";
+		i2c6 = "/i2c@138c0000";
+		i2c7 = "/i2c@138d0000";
+		serial0 = "/serial@13800000";
+		console = "/serial@13820000";
+		mmc0 = "sdhci@12510000";
+		mmc2 = "sdhci@12530000";
+	};
+
+	fimd@11c00000 {
+		compatible = "samsung,exynos-fimd";
+		reg = <0x11c00000 0xa4>;
+
+		samsung,vl-freq = <60>;
+		samsung,vl-col = <720>;
+		samsung,vl-row = <1280>;
+		samsung,vl-width = <720>;
+		samsung,vl-height = <1280>;
+
+		samsung,vl-clkp = <0>;
+		samsung,vl-oep = <0>;
+		samsung,vl-hsp = <1>;
+		samsung,vl-vsp = <1>;
+		samsung,vl-dp = <1>;
+		samsung,vl-bpix = <4>;
+
+		samsung,vl-hspw = <5>;
+		samsung,vl-hbpd = <10>;
+		samsung,vl-hfpd = <10>;
+		samsung,vl-vspw = <2>;
+		samsung,vl-vbpd = <1>;
+		samsung,vl-vfpd = <13>;
+		samsung,vl-cmd-allow-len = <0xf>;
+
+		samsung,winid = <3>;
+		samsung,power-on-delay = <30>;
+		samsung,interface-mode = <1>;
+		samsung,mipi-enabled = <1>;
+		samsung,dp-enabled;
+		samsung,dual-lcd-enabled;
+
+		samsung,logo-on = <1>;
+		samsung,resolution = <0>;
+		samsung,rgb-mode = <0>;
+	};
+
+	mipidsi@11c80000 {
+		compatible = "samsung,exynos-mipi-dsi";
+		reg = <0x11c80000 0x5c>;
+
+		samsung,dsim-config-e-interface = <1>;
+		samsung,dsim-config-e-virtual-ch = <0>;
+		samsung,dsim-config-e-pixel-format = <7>;
+		samsung,dsim-config-e-burst-mode = <1>;
+		samsung,dsim-config-e-no-data-lane = <3>;
+		samsung,dsim-config-e-byte-clk = <0>;
+		samsung,dsim-config-hfp = <1>;
+
+		samsung,dsim-config-p = <3>;
+		samsung,dsim-config-m = <120>;
+		samsung,dsim-config-s = <1>;
+
+		samsung,dsim-config-pll-stable-time = <500>;
+		samsung,dsim-config-esc-clk = <20000000>;
+		samsung,dsim-config-stop-holding-cnt = <0x7ff>;
+		samsung,dsim-config-bta-timeout = <0xff>;
+		samsung,dsim-config-rx-timeout = <0xffff>;
+
+		samsung,dsim-device-id = <0xffffffff>;
+		samsung,dsim-device-bus-id = <0>;
+
+		samsung,dsim-device-reverse-panel = <1>;
+	};
+
+	sdhci@12510000 {
+		samsung,bus-width = <8>;
+		samsung,timing = <1 3 3>;
+		pwr-gpios = <&gpio 0x2008002 0>;
+	};
+
+	sdhci@12520000 {
+		status = "disabled";
+	};
+
+	sdhci@12530000 {
+		samsung,bus-width = <4>;
+		samsung,timing = <1 2 3>;
+		cd-gpios = <&gpio 0x20c6004 0>;
+	};
+
+	sdhci@12540000 {
+		status = "disabled";
+	};
+};
\ No newline at end of file
diff --git a/arch/arm/dts/exynos4210-universal_c210.dts b/arch/arm/dts/exynos4210-universal_c210.dts
new file mode 100644
index 0000000000..1cdd981d6d
--- /dev/null
+++ b/arch/arm/dts/exynos4210-universal_c210.dts
@@ -0,0 +1,83 @@
+/*
+ * Samsung's Exynos4210 based Universal C210 board device tree source
+ *
+ * Copyright (c) 2014 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/dts-v1/;
+/include/ "exynos4.dtsi"
+
+/ {
+	model = "Samsung Universal C210 based on Exynos4210 rev0";
+	compatible = "samsung,universal_c210", "samsung,exynos4210";
+
+	aliases {
+		serial0 = "/serial@13800000";
+		console = "/serial@13820000";
+		mmc0 = "sdhci@12510000";
+		mmc2 = "sdhci@12530000";
+	};
+
+	sdhci@12510000 {
+		samsung,bus-width = <8>;
+		samsung,timing = <1 3 3>;
+		pwr-gpios = <&gpio 0x2008002 0>;
+	};
+
+	sdhci@12520000 {
+		status = "disabled";
+	};
+
+	sdhci@12530000 {
+		samsung,bus-width = <4>;
+		samsung,timing = <1 2 3>;
+		cd-gpios = <&gpio 0x20c6004 0>;
+	};
+
+	sdhci@12540000 {
+		status = "disabled";
+	};
+
+	fimd@11c00000 {
+		compatible = "samsung,exynos-fimd";
+		reg = <0x11c00000 0xa4>;
+
+		samsung,vl-freq = <60>;
+		samsung,vl-col = <480>;
+		samsung,vl-row = <800>;
+		samsung,vl-width = <480>;
+		samsung,vl-height = <800>;
+
+		samsung,vl-clkp = <0>;
+		samsung,vl-oep = <0>;
+		samsung,vl-hsp = <1>;
+		samsung,vl-vsp = <1>;
+		samsung,vl-dp = <1>;
+		samsung,vl-bpix = <4>;
+
+		samsung,vl-hspw = <2>;
+		samsung,vl-hbpd = <16>;
+		samsung,vl-hfpd = <16>;
+		samsung,vl-vspw = <2>;
+		samsung,vl-vbpd = <8>;
+		samsung,vl-vfpd = <8>;
+		samsung,vl-cmd-allow-len = <0xf>;
+
+		samsung,pclk_name = <1>;
+		samsung,sclk_div = <1>;
+
+		samsung,winid = <0>;
+		samsung,power-on-delay = <10000>;
+		samsung,interface-mode = <1>;
+		samsung,mipi-enabled = <0>;
+		samsung,dp-enabled;
+		samsung,dual-lcd-enabled;
+
+		samsung,logo-on = <1>;
+		samsung,resolution = <0>;
+		samsung,rgb-mode = <0>;
+	};
+};
diff --git a/arch/arm/dts/exynos4412-trats2.dts b/arch/arm/dts/exynos4412-trats2.dts
new file mode 100644
index 0000000000..7d32067fdd
--- /dev/null
+++ b/arch/arm/dts/exynos4412-trats2.dts
@@ -0,0 +1,434 @@
+/*
+ * Samsung's Exynos4412 based Trats2 board device tree source
+ *
+ * Copyright (c) 2014 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/dts-v1/;
+/include/ "exynos4.dtsi"
+
+/ {
+	model = "Samsung Trats2 based on Exynos4412";
+	compatible = "samsung,trats2", "samsung,exynos4412";
+
+	config {
+		samsung,dsim-device-name = "s6e8ax0";
+	};
+
+	aliases {
+		i2c0 = "/i2c@13860000";
+		i2c1 = "/i2c@13870000";
+		i2c2 = "/i2c@13880000";
+		i2c3 = "/i2c@13890000";
+		i2c4 = "/i2c@138a0000";
+		i2c5 = "/i2c@138b0000";
+		i2c6 = "/i2c@138c0000";
+		i2c7 = "/i2c@138d0000";
+		serial0 = "/serial@13800000";
+		console = "/serial@13820000";
+		mmc0 = "sdhci@12510000";
+		mmc2 = "sdhci@12530000";
+	};
+
+	i2c@138d0000 {
+		samsung,i2c-sda-delay = <100>;
+		samsung,i2c-slave-addr = <0x10>;
+		samsung,i2c-max-bus-freq = <100000>;
+		status = "okay";
+
+		max77686_pmic@09 {
+			compatible = "maxim,max77686_pmic";
+			interrupts = <7 0>;
+			reg = <0x09 0 0>;
+			#clock-cells = <1>;
+
+			voltage-regulators {
+				ldo1_reg: ldo1 {
+					regulator-compatible = "LDO1";
+					regulator-name = "VALIVE_1.0V_AP";
+					regulator-min-microvolt = <1000000>;
+					regulator-max-microvolt = <1000000>;
+					regulator-always-on;
+					regulator-mem-on;
+				};
+
+				ldo2_reg: ldo2 {
+					regulator-compatible = "LDO2";
+					regulator-name = "VM1M2_1.2V_AP";
+					regulator-min-microvolt = <1200000>;
+					regulator-max-microvolt = <1200000>;
+					regulator-always-on;
+					regulator-mem-on;
+				};
+
+				ldo3_reg: ldo3 {
+					regulator-compatible = "LDO3";
+					regulator-name = "VCC_1.8V_AP";
+					regulator-min-microvolt = <1800000>;
+					regulator-max-microvolt = <1800000>;
+					regulator-always-on;
+					regulator-mem-on;
+				};
+
+				ldo4_reg: ldo4 {
+					regulator-compatible = "LDO4";
+					regulator-name = "VCC_2.8V_AP";
+					regulator-min-microvolt = <2800000>;
+					regulator-max-microvolt = <2800000>;
+					regulator-always-on;
+					regulator-mem-on;
+				};
+
+				ldo5_reg: ldo5 {
+					regulator-compatible = "LDO5";
+					regulator-name = "VCC_1.8V_IO";
+					regulator-min-microvolt = <1800000>;
+					regulator-max-microvolt = <1800000>;
+					regulator-always-on;
+					regulator-mem-on;
+				};
+
+				ldo6_reg: ldo6 {
+					regulator-compatible = "LDO6";
+					regulator-name = "VMPLL_1.0V_AP";
+					regulator-min-microvolt = <1000000>;
+					regulator-max-microvolt = <1000000>;
+					regulator-always-on;
+					regulator-mem-on;
+				};
+
+				ldo7_reg: ldo7 {
+					regulator-compatible = "LDO7";
+					regulator-name = "VPLL_1.0V_AP";
+					regulator-min-microvolt = <1000000>;
+					regulator-max-microvolt = <1000000>;
+					regulator-always-on;
+					regulator-mem-on;
+				};
+
+				ldo8_reg: ldo8 {
+					regulator-compatible = "LDO8";
+					regulator-name = "VMIPI_1.0V";
+					regulator-min-microvolt = <1000000>;
+					regulator-max-microvolt = <1000000>;
+					regulator-mem-off;
+				};
+
+				ldo9_reg: ldo9 {
+					regulator-compatible = "LDO9";
+					regulator-name = "CAM_ISP_MIPI_1.2V";
+					regulator-min-microvolt = <1200000>;
+					regulator-max-microvolt = <1200000>;
+					regulator-mem-idle;
+				};
+
+				ldo10_reg: ldo10 {
+					regulator-compatible = "LDO10";
+					regulator-name = "VMIPI_1.8V";
+					regulator-min-microvolt = <1800000>;
+					regulator-max-microvolt = <1800000>;
+					regulator-mem-off;
+				};
+
+				ldo11_reg: ldo11 {
+					regulator-compatible = "LDO11";
+					regulator-name = "VABB1_1.95V";
+					regulator-min-microvolt = <1950000>;
+					regulator-max-microvolt = <1950000>;
+					regulator-always-on;
+					regulator-mem-off;
+				};
+
+				ldo12_reg: ldo12 {
+					regulator-compatible = "LDO12";
+					regulator-name = "VUOTG_3.0V";
+					regulator-min-microvolt = <3000000>;
+					regulator-max-microvolt = <3000000>;
+					regulator-mem-off;
+				};
+
+				ldo13_reg: ldo13 {
+					regulator-compatible = "LDO13";
+					regulator-name = "NFC_AVDD_1.8V";
+					regulator-min-microvolt = <1800000>;
+					regulator-max-microvolt = <1800000>;
+					regulator-mem-idle;
+				};
+
+				ldo14_reg: ldo14 {
+					regulator-compatible = "LDO14";
+					regulator-name = "VABB2_1.95V";
+					regulator-min-microvolt = <1950000>;
+					regulator-max-microvolt = <1950000>;
+					regulator-always-on;
+					regulator-mem-off;
+				};
+
+				ldo15_reg: ldo15 {
+					regulator-compatible = "LDO15";
+					regulator-name = "VHSIC_1.0V";
+					regulator-min-microvolt = <1000000>;
+					regulator-max-microvolt = <1000000>;
+					regulator-mem-off;
+				};
+
+				ldo16_reg: ldo16 {
+					regulator-compatible = "LDO16";
+					regulator-name = "VHSIC_1.8V";
+					regulator-min-microvolt = <1800000>;
+					regulator-max-microvolt = <1800000>;
+					regulator-mem-off;
+				};
+
+				ldo17_reg: ldo17 {
+					regulator-compatible = "LDO17";
+					regulator-name = "CAM_SENSOR_CORE_1.2V";
+					regulator-min-microvolt = <1200000>;
+					regulator-max-microvolt = <1200000>;
+					regulator-mem-idle;
+				};
+
+				ldo18_reg: ldo18 {
+					regulator-compatible = "LDO18";
+					regulator-name = "CAM_ISP_SEN_IO_1.8V";
+					regulator-min-microvolt = <1800000>;
+					regulator-max-microvolt = <1800000>;
+					regulator-mem-idle;
+				};
+
+				ldo19_reg: ldo19 {
+					regulator-compatible = "LDO19";
+					regulator-name = "VT_CAM_1.8V";
+					regulator-min-microvolt = <1800000>;
+					regulator-max-microvolt = <1800000>;
+					regulator-mem-idle;
+				};
+
+				ldo20_reg: ldo20 {
+					regulator-compatible = "LDO20";
+					regulator-name = "VDDQ_PRE_1.8V";
+					regulator-min-microvolt = <1800000>;
+					regulator-max-microvolt = <1800000>;
+					regulator-mem-idle;
+				};
+
+				ldo21_reg: ldo21 {
+					regulator-compatible = "LDO21";
+					regulator-name = "VTF_2.8V";
+					regulator-min-microvolt = <2800000>;
+					regulator-max-microvolt = <2800000>;
+					regulator-mem-idle;
+				};
+
+				ldo22_reg: ldo22 {
+					regulator-compatible = "LDO22";
+					regulator-name = "VMEM_VDD_2.8V";
+					regulator-min-microvolt = <2800000>;
+					regulator-max-microvolt = <2800000>;
+					regulator-always-on;
+					regulator-mem-off;
+				};
+
+				ldo23_reg: ldo23 {
+					regulator-compatible = "LDO23";
+					regulator-name = "TSP_AVDD_3.3V";
+					regulator-min-microvolt = <3300000>;
+					regulator-max-microvolt = <3300000>;
+					regulator-mem-idle;
+				};
+
+				ldo24_reg: ldo24 {
+					regulator-compatible = "LDO24";
+					regulator-name = "TSP_VDD_1.8V";
+					regulator-min-microvolt = <1800000>;
+					regulator-max-microvolt = <1800000>;
+					regulator-mem-idle;
+				};
+
+				ldo25_reg: ldo25 {
+					regulator-compatible = "LDO25";
+					regulator-name = "LCD_VCC_3.3V";
+					regulator-min-microvolt = <2800000>;
+					regulator-max-microvolt = <2800000>;
+					regulator-mem-idle;
+				};
+
+				ldo26_reg: ldo26 {
+					regulator-compatible = "LDO26";
+					regulator-name = "MOTOR_VCC_3.0V";
+					regulator-min-microvolt = <3000000>;
+					regulator-max-microvolt = <3000000>;
+					regulator-mem-idle;
+				};
+
+				buck1_reg: buck1 {
+					regulator-compatible = "BUCK1";
+					regulator-name = "vdd_mif";
+					regulator-min-microvolt = <850000>;
+					regulator-max-microvolt = <1100000>;
+					regulator-always-on;
+					regulator-boot-on;
+					regulator-mem-off;
+				};
+
+				buck2_reg: buck2 {
+					regulator-compatible = "BUCK2";
+					regulator-name = "vdd_arm";
+					regulator-min-microvolt = <850000>;
+					regulator-max-microvolt = <1500000>;
+					regulator-always-on;
+					regulator-boot-on;
+					regulator-mem-off;
+				};
+
+				buck3_reg: buck3 {
+					regulator-compatible = "BUCK3";
+					regulator-name = "vdd_int";
+					regulator-min-microvolt = <850000>;
+					regulator-max-microvolt = <1150000>;
+					regulator-always-on;
+					regulator-boot-on;
+					regulator-mem-off;
+				};
+
+				buck4_reg: buck4 {
+					regulator-compatible = "BUCK4";
+					regulator-name = "vdd_g3d";
+					regulator-min-microvolt = <850000>;
+					regulator-max-microvolt = <1150000>;
+					regulator-boot-on;
+					regulator-mem-off;
+				};
+
+				buck5_reg: buck5 {
+					regulator-compatible = "BUCK5";
+					regulator-name = "VMEM_1.2V_AP";
+					regulator-min-microvolt = <1200000>;
+					regulator-max-microvolt = <1200000>;
+					regulator-always-on;
+				};
+
+				buck6_reg: buck6 {
+					regulator-compatible = "BUCK6";
+					regulator-name = "VCC_SUB_1.35V";
+					regulator-min-microvolt = <1350000>;
+					regulator-max-microvolt = <1350000>;
+					regulator-always-on;
+				};
+
+				buck7_reg: buck7 {
+					regulator-compatible = "BUCK7";
+					regulator-name = "VCC_SUB_2.0V";
+					regulator-min-microvolt = <2000000>;
+					regulator-max-microvolt = <2000000>;
+					regulator-always-on;
+				};
+
+				buck8_reg: buck8 {
+					regulator-compatible = "BUCK8";
+					regulator-name = "VMEM_VDDF_3.0V";
+					regulator-min-microvolt = <2850000>;
+					regulator-max-microvolt = <2850000>;
+					regulator-always-on;
+					regulator-mem-off;
+				};
+
+				buck9_reg: buck9 {
+					regulator-compatible = "BUCK9";
+					regulator-name = "CAM_ISP_CORE_1.2V";
+					regulator-min-microvolt = <1000000>;
+					regulator-max-microvolt = <1200000>;
+					regulator-mem-off;
+				};
+			};
+		};
+	};
+
+	fimd@11c00000 {
+		compatible = "samsung,exynos-fimd";
+		reg = <0x11c00000 0xa4>;
+
+		samsung,vl-freq = <60>;
+		samsung,vl-col = <720>;
+		samsung,vl-row = <1280>;
+		samsung,vl-width = <720>;
+		samsung,vl-height = <1280>;
+
+		samsung,vl-clkp = <0>;
+		samsung,vl-oep = <0>;
+		samsung,vl-hsp = <1>;
+		samsung,vl-vsp = <1>;
+		samsung,vl-dp = <1>;
+		samsung,vl-bpix = <4>;
+
+		samsung,vl-hspw = <5>;
+		samsung,vl-hbpd = <10>;
+		samsung,vl-hfpd = <10>;
+		samsung,vl-vspw = <2>;
+		samsung,vl-vbpd = <1>;
+		samsung,vl-vfpd = <13>;
+		samsung,vl-cmd-allow-len = <0xf>;
+
+		samsung,winid = <0>;
+		samsung,power-on-delay = <30>;
+		samsung,interface-mode = <1>;
+		samsung,mipi-enabled = <1>;
+		samsung,dp-enabled;
+		samsung,dual-lcd-enabled;
+
+		samsung,logo-on = <1>;
+		samsung,resolution = <0>;
+		samsung,rgb-mode = <0>;
+	};
+
+	mipidsi@11c80000 {
+		compatible = "samsung,exynos-mipi-dsi";
+		reg = <0x11c80000 0x5c>;
+
+		samsung,dsim-config-e-interface = <1>;
+		samsung,dsim-config-e-virtual-ch = <0>;
+		samsung,dsim-config-e-pixel-format = <7>;
+		samsung,dsim-config-e-burst-mode = <1>;
+		samsung,dsim-config-e-no-data-lane = <3>;
+		samsung,dsim-config-e-byte-clk = <0>;
+		samsung,dsim-config-hfp = <1>;
+
+		samsung,dsim-config-p = <3>;
+		samsung,dsim-config-m = <120>;
+		samsung,dsim-config-s = <1>;
+
+		samsung,dsim-config-pll-stable-time = <500>;
+		samsung,dsim-config-esc-clk = <20000000>;
+		samsung,dsim-config-stop-holding-cnt = <0x7ff>;
+		samsung,dsim-config-bta-timeout = <0xff>;
+		samsung,dsim-config-rx-timeout = <0xffff>;
+
+		samsung,dsim-device-id = <0xffffffff>;
+		samsung,dsim-device-bus-id = <0>;
+
+		samsung,dsim-device-reverse-panel = <1>;
+	};
+
+	sdhci@12510000 {
+		samsung,bus-width = <8>;
+		samsung,timing = <1 3 3>;
+		pwr-gpios = <&gpio 0x2004002 0>;
+	};
+
+	sdhci@12520000 {
+		status = "disabled";
+	};
+
+	sdhci@12530000 {
+		samsung,bus-width = <4>;
+		samsung,timing = <1 2 3>;
+		cd-gpios = <&gpio 0x20C6004 0>;
+	};
+
+	sdhci@12540000 {
+		status = "disabled";
+	};
+};
diff --git a/arch/arm/dts/exynos5.dtsi b/arch/arm/dts/exynos5.dtsi
new file mode 100644
index 0000000000..f8c87411b6
--- /dev/null
+++ b/arch/arm/dts/exynos5.dtsi
@@ -0,0 +1,198 @@
+/*
+ * Copyright (c) 2013 The Chromium OS Authors
+ * SAMSUNG EXYNOS5 SoC device tree source
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/include/ "skeleton.dtsi"
+
+/ {
+	compatible = "samsung,exynos5";
+
+	sromc@12250000 {
+		compatible = "samsung,exynos-sromc";
+		reg = <0x12250000 0x20>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+	};
+
+	i2c@12c60000 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "samsung,s3c2440-i2c";
+		reg = <0x12C60000 0x100>;
+		interrupts = <0 56 0>;
+	};
+
+	i2c@12c70000 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "samsung,s3c2440-i2c";
+		reg = <0x12C70000 0x100>;
+		interrupts = <0 57 0>;
+	};
+
+	i2c@12c80000 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "samsung,s3c2440-i2c";
+		reg = <0x12C80000 0x100>;
+		interrupts = <0 58 0>;
+	};
+
+	i2c@12c90000 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "samsung,s3c2440-i2c";
+		reg = <0x12C90000 0x100>;
+		interrupts = <0 59 0>;
+	};
+
+	spi@12d20000 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "samsung,exynos-spi";
+		reg = <0x12d20000 0x30>;
+		interrupts = <0 68 0>;
+	};
+
+	spi@12d30000 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "samsung,exynos-spi";
+		reg = <0x12d30000 0x30>;
+		interrupts = <0 69 0>;
+	};
+
+	spi@12d40000 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "samsung,exynos-spi";
+		reg = <0x12d40000 0x30>;
+		clock-frequency = <50000000>;
+		interrupts = <0 70 0>;
+        };
+
+	spi@131a0000 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "samsung,exynos-spi";
+		reg = <0x131a0000 0x30>;
+		interrupts = <0 129 0>;
+	};
+
+	spi@131b0000 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "samsung,exynos-spi";
+		reg = <0x131b0000 0x30>;
+		interrupts = <0 130 0>;
+	};
+
+	ehci@12110000 {
+		compatible = "samsung,exynos-ehci";
+		reg = <0x12110000 0x100>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		phy {
+			compatible = "samsung,exynos-usb-phy";
+			reg = <0x12130000 0x100>;
+		};
+	};
+
+	tmu@10060000 {
+		compatible = "samsung,exynos-tmu";
+		reg = <0x10060000 0x10000>;
+	};
+
+	fimd@14400000 {
+		compatible = "samsung,exynos-fimd";
+		reg = <0x14400000 0x10000>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+	};
+
+	dp@145b0000 {
+		compatible = "samsung,exynos5-dp";
+		reg = <0x145b0000 0x1000>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+	};
+
+	xhci0: xhci@12000000 {
+		compatible = "samsung,exynos5250-xhci";
+		reg = <0x12000000 0x10000>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		phy {
+			compatible = "samsung,exynos5250-usb3-phy";
+			reg = <0x12100000 0x100>;
+		};
+	};
+
+	mmc@12200000 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "samsung,exynos5250-dwmmc";
+		reg = <0x12200000 0x1000>;
+		interrupts = <0 75 0>;
+	};
+
+	mmc@12210000 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "samsung,exynos5250-dwmmc";
+		reg = <0x12210000 0x1000>;
+		interrupts = <0 76 0>;
+	};
+
+	mmc@12220000 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "samsung,exynos5250-dwmmc";
+		reg = <0x12220000 0x1000>;
+		interrupts = <0 77 0>;
+	};
+
+	mmc@12230000 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "samsung,exynos5250-dwmmc";
+		reg = <0x12230000 0x1000>;
+		interrupts = <0 78 0>;
+	};
+
+	serial@12C00000 {
+		compatible = "samsung,exynos4210-uart";
+		reg = <0x12C00000 0x100>;
+		interrupts = <0 51 0>;
+		id = <0>;
+	};
+
+	serial@12C10000 {
+		compatible = "samsung,exynos4210-uart";
+		reg = <0x12C10000 0x100>;
+		interrupts = <0 52 0>;
+		id = <1>;
+	};
+
+	serial@12C20000 {
+		compatible = "samsung,exynos4210-uart";
+		reg = <0x12C20000 0x100>;
+		interrupts = <0 53 0>;
+		id = <2>;
+	};
+
+	serial@12C30000 {
+		compatible = "samsung,exynos4210-uart";
+		reg = <0x12C30000 0x100>;
+		interrupts = <0 54 0>;
+		id = <3>;
+	};
+
+	gpio: gpio {
+	};
+};
diff --git a/board/samsung/dts/exynos5250-arndale.dts b/arch/arm/dts/exynos5250-arndale.dts
index 202f2ea6ed..202f2ea6ed 100644
--- a/board/samsung/dts/exynos5250-arndale.dts
+++ b/arch/arm/dts/exynos5250-arndale.dts
diff --git a/arch/arm/dts/exynos5250-smdk5250.dts b/arch/arm/dts/exynos5250-smdk5250.dts
new file mode 100644
index 0000000000..9020382d97
--- /dev/null
+++ b/arch/arm/dts/exynos5250-smdk5250.dts
@@ -0,0 +1,151 @@
+/*
+ * SAMSUNG SMDK5250 board device tree source
+ *
+ * Copyright (c) 2012 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+/dts-v1/;
+/include/ "exynos5250.dtsi"
+
+/ {
+	model = "SAMSUNG SMDK5250 board based on EXYNOS5250";
+	compatible = "samsung,smdk5250", "samsung,exynos5250";
+
+	aliases {
+		i2c0 = "/i2c@12c60000";
+		i2c1 = "/i2c@12c70000";
+		i2c2 = "/i2c@12c80000";
+		i2c3 = "/i2c@12c90000";
+		i2c4 = "/i2c@12ca0000";
+		i2c5 = "/i2c@12cb0000";
+		i2c6 = "/i2c@12cc0000";
+		i2c7 = "/i2c@12cd0000";
+		spi0 = "/spi@12d20000";
+		spi1 = "/spi@12d30000";
+		spi2 = "/spi@12d40000";
+		spi3 = "/spi@131a0000";
+		spi4 = "/spi@131b0000";
+		mmc0 = "/mmc@12200000";
+		mmc1 = "/mmc@12210000";
+		mmc2 = "/mmc@12220000";
+		mmc3 = "/mmc@12230000";
+		serial0 = "/serial@12C30000";
+		console = "/serial@12C30000";
+		i2s = "/sound@3830000";
+	};
+
+	sromc@12250000 {
+		bank = <1>;
+		srom-timing = <1 9 12 1 6 1 1>;
+		width = <2>;
+		lan@5000000 {
+			compatible = "smsc,lan9215", "smsc,lan";
+			reg = <0x5000000 0x100>;
+			phy-mode = "mii";
+		};
+	};
+
+	sound@3830000 {
+		samsung,codec-type = "wm8994";
+	};
+
+	sound@12d60000 {
+		status = "disabled";
+	};
+
+	i2c@12c70000 {
+		soundcodec@1a {
+			reg = <0x1a>;
+			compatible = "wolfson,wm8994-codec";
+		};
+	};
+
+	i2c@12c60000 {
+		pmic@9 {
+			reg = <0x9>;
+			compatible = "maxim,max77686_pmic";
+		};
+	};
+
+	tmu@10060000 {
+		samsung,min-temp	= <25>;
+		samsung,max-temp	= <125>;
+		samsung,start-warning	= <95>;
+		samsung,start-tripping	= <105>;
+		samsung,hw-tripping	= <110>;
+		samsung,efuse-min-value	= <40>;
+		samsung,efuse-value	= <55>;
+		samsung,efuse-max-value	= <100>;
+		samsung,slope		= <274761730>;
+		samsung,dc-value	= <25>;
+	};
+
+	fimd@14400000 {
+		samsung,vl-freq = <60>;
+		samsung,vl-col = <2560>;
+		samsung,vl-row = <1600>;
+		samsung,vl-width = <2560>;
+		samsung,vl-height = <1600>;
+
+		samsung,vl-clkp;
+		samsung,vl-dp;
+		samsung,vl-bpix = <4>;
+
+		samsung,vl-hspw = <32>;
+		samsung,vl-hbpd = <80>;
+		samsung,vl-hfpd = <48>;
+		samsung,vl-vspw = <6>;
+		samsung,vl-vbpd = <37>;
+		samsung,vl-vfpd = <3>;
+		samsung,vl-cmd-allow-len = <0xf>;
+
+		samsung,winid = <3>;
+		samsung,interface-mode = <1>;
+		samsung,dp-enabled = <1>;
+		samsung,dual-lcd-enabled = <0>;
+	};
+
+	dp@145b0000 {
+		samsung,lt-status = <0>;
+
+		samsung,master-mode = <0>;
+		samsung,bist-mode = <0>;
+		samsung,bist-pattern = <0>;
+		samsung,h-sync-polarity = <0>;
+		samsung,v-sync-polarity = <0>;
+		samsung,interlaced = <0>;
+		samsung,color-space = <0>;
+		samsung,dynamic-range = <0>;
+		samsung,ycbcr-coeff = <0>;
+		samsung,color-depth = <1>;
+	};
+
+	mmc@12200000 {
+		samsung,bus-width = <8>;
+		samsung,timing = <1 3 3>;
+		samsung,removable = <0>;
+	};
+
+	mmc@12210000 {
+		status = "disabled";
+	};
+
+	mmc@12220000 {
+		samsung,bus-width = <4>;
+		samsung,timing = <1 2 3>;
+		samsung,removable = <1>;
+	};
+
+	mmc@12230000 {
+		status = "disabled";
+	};
+
+	ehci@12110000 {
+		samsung,vbus-gpio = <&gpio 0x316 0>; /* X26 */
+	};
+};
diff --git a/arch/arm/dts/exynos5250-snow.dts b/arch/arm/dts/exynos5250-snow.dts
new file mode 100644
index 0000000000..9b48a0ccd8
--- /dev/null
+++ b/arch/arm/dts/exynos5250-snow.dts
@@ -0,0 +1,187 @@
+/*
+ * SAMSUNG Snow board device tree source
+ *
+ * Copyright (c) 2012 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+/dts-v1/;
+/include/ "exynos5250.dtsi"
+
+/ {
+	model = "Google Snow";
+	compatible = "google,snow", "samsung,exynos5250";
+
+	aliases {
+		i2c0 = "/i2c@12c60000";
+		i2c1 = "/i2c@12c70000";
+		i2c2 = "/i2c@12c80000";
+		i2c3 = "/i2c@12c90000";
+		i2c4 = "/i2c@12ca0000";
+		i2c5 = "/i2c@12cb0000";
+		i2c6 = "/i2c@12cc0000";
+		i2c7 = "/i2c@12cd0000";
+		spi0 = "/spi@12d20000";
+		spi1 = "/spi@12d30000";
+		spi2 = "/spi@12d40000";
+		spi3 = "/spi@131a0000";
+		spi4 = "/spi@131b0000";
+		mmc0 = "/mmc@12200000";
+		mmc1 = "/mmc@12210000";
+		mmc2 = "/mmc@12220000";
+		mmc3 = "/mmc@12230000";
+		serial0 = "/serial@12C30000";
+		console = "/serial@12C30000";
+		i2s = "/sound@3830000";
+	};
+
+	i2c4: i2c@12ca0000 {
+		cros-ec@1e {
+			reg = <0x1e>;
+			compatible = "google,cros-ec";
+			i2c-max-frequency = <100000>;
+			ec-interrupt = <&gpio 782 1>;
+		};
+
+		power-regulator@48 {
+			compatible = "ti,tps65090";
+			reg = <0x48>;
+		};
+	};
+
+	spi@131b0000 {
+		spi-max-frequency = <1000000>;
+		spi-deactivate-delay = <100>;
+		cros-ec@0 {
+			reg = <0>;
+			compatible = "google,cros-ec";
+			spi-max-frequency = <5000000>;
+			ec-interrupt = <&gpio 782 1>;
+			optimise-flash-write;
+			status = "disabled";
+		};
+	};
+
+	sound@3830000 {
+		samsung,codec-type = "max98095";
+		codec-enable-gpio = <&gpio 0xb7 0>;
+	};
+
+	sound@12d60000 {
+		status = "disabled";
+	};
+
+	i2c@12cd0000 {
+		soundcodec@22 {
+			reg = <0x22>;
+			compatible = "maxim,max98095-codec";
+		};
+	};
+
+	i2c@12c60000 {
+		pmic@9 {
+			reg = <0x9>;
+			compatible = "maxim,max77686_pmic";
+		};
+	};
+
+	mmc@12200000 {
+		samsung,bus-width = <8>;
+		samsung,timing = <1 3 3>;
+		samsung,removable = <0>;
+	};
+
+	mmc@12210000 {
+		status = "disabled";
+	};
+
+	mmc@12220000 {
+		samsung,bus-width = <4>;
+		samsung,timing = <1 2 3>;
+		samsung,removable = <1>;
+	};
+
+	mmc@12230000 {
+		status = "disabled";
+	};
+
+	ehci@12110000 {
+		samsung,vbus-gpio = <&gpio 0x309 0>; /* X11 */
+	};
+
+	xhci@12000000 {
+		samsung,vbus-gpio = <&gpio 0x317 0>; /* X27 */
+	};
+
+	tmu@10060000 {
+		samsung,min-temp	= <25>;
+		samsung,max-temp	= <125>;
+		samsung,start-warning	= <95>;
+		samsung,start-tripping	= <105>;
+		samsung,hw-tripping	= <110>;
+		samsung,efuse-min-value	= <40>;
+		samsung,efuse-value	= <55>;
+		samsung,efuse-max-value	= <100>;
+		samsung,slope		= <274761730>;
+		samsung,dc-value	= <25>;
+	};
+
+	cros-ec-keyb {
+		compatible = "google,cros-ec-keyb";
+		google,key-rows = <8>;
+		google,key-columns = <13>;
+		google,repeat-delay-ms = <240>;
+		google,repeat-rate-ms = <30>;
+		google,ghost-filter;
+		/*
+		 * Keymap entries take the form of 0xRRCCKKKK where
+		 * RR=Row CC=Column KKKK=Key Code
+		 * The values below are for a US keyboard layout and
+		 * are taken from the Linux driver. Note that the
+		 * 102ND key is not used for US keyboards.
+		 */
+		linux,keymap = <
+			/* CAPSLCK F1         B          F10     */
+			0x0001003a 0x0002003b 0x00030030 0x00040044
+			/* N       =          R_ALT      ESC     */
+			0x00060031 0x0008000d 0x000a0064 0x01010001
+			/* F4      G          F7         H       */
+			0x0102003e 0x01030022 0x01040041 0x01060023
+			/* '       F9         BKSPACE    L_CTRL  */
+			0x01080028 0x01090043 0x010b000e 0x0200001d
+			/* TAB     F3         T          F6      */
+			0x0201000f 0x0202003d 0x02030014 0x02040040
+			/* ]       Y          102ND      [       */
+			0x0205001b 0x02060015 0x02070056 0x0208001a
+			/* F8      GRAVE      F2         5       */
+			0x02090042 0x03010029 0x0302003c 0x03030006
+			/* F5      6          -          \       */
+			0x0304003f 0x03060007 0x0308000c 0x030b002b
+			/* R_CTRL  A          D          F       */
+			0x04000061 0x0401001e 0x04020020 0x04030021
+			/* S       K          J          ;       */
+			0x0404001f 0x04050025 0x04060024 0x04080027
+			/* L       ENTER      Z          C       */
+			0x04090026 0x040b001c 0x0501002c 0x0502002e
+			/* V       X          ,          M       */
+			0x0503002f 0x0504002d 0x05050033 0x05060032
+			/* L_SHIFT /          .          SPACE   */
+			0x0507002a 0x05080035 0x05090034 0x050B0039
+			/* 1       3          4          2       */
+			0x06010002 0x06020004 0x06030005 0x06040003
+			/* 8       7          0          9       */
+			0x06050009 0x06060008 0x0608000b 0x0609000a
+			/* L_ALT   DOWN       RIGHT      Q       */
+			0x060a0038 0x060b006c 0x060c006a 0x07010010
+			/* E       R          W          I       */
+			0x07020012 0x07030013 0x07040011 0x07050017
+			/* U       R_SHIFT    P          O       */
+			0x07060016 0x07070036 0x07080019 0x07090018
+			/* UP      LEFT    */
+			0x070b0067 0x070c0069>;
+	};
+};
diff --git a/arch/arm/dts/exynos5250.dtsi b/arch/arm/dts/exynos5250.dtsi
index 44cbb5a2e5..0c644e7cac 100644
--- a/arch/arm/dts/exynos5250.dtsi
+++ b/arch/arm/dts/exynos5250.dtsi
@@ -1,66 +1,13 @@
 /*
+ * (C) Copyright 2012 SAMSUNG Electronics
  * SAMSUNG EXYNOS5250 SoC device tree source
  *
- * Copyright (c) 2012 Samsung Electronics Co., Ltd.
- *		http://www.samsung.com
- *
- * SAMSUNG EXYNOS5250 SoC device nodes are listed in this file.
- * EXYNOS5250 based board files can include this file and provide
- * values for board specfic bindings.
- *
- * Note: This file does not include device nodes for all the controllers in
- * EXYNOS5250 SoC. As device tree coverage for EXYNOS5250 increases,
- * additional nodes can be added to this file.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
 
-/include/ "skeleton.dtsi"
+/include/ "exynos5.dtsi"
 
 / {
-	compatible = "samsung,exynos5250";
-
-	sromc@12250000 {
-		compatible = "samsung,exynos-sromc";
-		reg = <0x12250000 0x20>;
-		#address-cells = <1>;
-		#size-cells = <0>;
-	};
-
-	i2c@12c60000 {
-		#address-cells = <1>;
-		#size-cells = <0>;
-		compatible = "samsung,s3c2440-i2c";
-		reg = <0x12C60000 0x100>;
-		interrupts = <0 56 0>;
-	};
-
-	i2c@12c70000 {
-		#address-cells = <1>;
-		#size-cells = <0>;
-		compatible = "samsung,s3c2440-i2c";
-		reg = <0x12C70000 0x100>;
-		interrupts = <0 57 0>;
-	};
-
-	i2c@12c80000 {
-		#address-cells = <1>;
-		#size-cells = <0>;
-		compatible = "samsung,s3c2440-i2c";
-		reg = <0x12C80000 0x100>;
-		interrupts = <0 58 0>;
-	};
-
-	i2c@12c90000 {
-		#address-cells = <1>;
-		#size-cells = <0>;
-		compatible = "samsung,s3c2440-i2c";
-		reg = <0x12C90000 0x100>;
-		interrupts = <0 59 0>;
-	};
-
 	i2c@12ca0000 {
 		#address-cells = <1>;
 		#size-cells = <0>;
@@ -117,138 +64,17 @@
 		samsung,i2s-id = <1>;
 	};
 
-	spi@12d20000 {
-		#address-cells = <1>;
-		#size-cells = <0>;
-		compatible = "samsung,exynos-spi";
-		reg = <0x12d20000 0x30>;
-		interrupts = <0 68 0>;
-	};
-
-	spi@12d30000 {
-		#address-cells = <1>;
-		#size-cells = <0>;
-		compatible = "samsung,exynos-spi";
-		reg = <0x12d30000 0x30>;
-		interrupts = <0 69 0>;
-	};
-
-	spi@12d40000 {
-		#address-cells = <1>;
-		#size-cells = <0>;
-		compatible = "samsung,exynos-spi";
-		reg = <0x12d40000 0x30>;
-		clock-frequency = <50000000>;
-		interrupts = <0 70 0>;
-	};
-
-	spi@131a0000 {
-		#address-cells = <1>;
-		#size-cells = <0>;
-		compatible = "samsung,exynos-spi";
-		reg = <0x131a0000 0x30>;
-		interrupts = <0 129 0>;
-	};
-
-	spi@131b0000 {
-		#address-cells = <1>;
-		#size-cells = <0>;
-		compatible = "samsung,exynos-spi";
-		reg = <0x131b0000 0x30>;
-		interrupts = <0 130 0>;
-	};
 
-	ehci@12110000 {
-		compatible = "samsung,exynos-ehci";
-		reg = <0x12110000 0x100>;
+	xhci@12000000 {
+		compatible = "samsung,exynos5250-xhci";
+		reg = <0x12000000 0x10000>;
 		#address-cells = <1>;
 		#size-cells = <1>;
 
 		phy {
-			compatible = "samsung,exynos-usb-phy";
-			reg = <0x12130000 0x100>;
+			compatible = "samsung,exynos5250-usb3-phy";
+			reg = <0x12100000 0x100>;
 		};
 	};
 
-	tmu@10060000 {
-		compatible = "samsung,exynos-tmu";
-		reg = <0x10060000 0x10000>;
-	};
-
-	fimd@14400000 {
-		compatible = "samsung,exynos-fimd";
-		reg = <0x14400000 0x10000>;
-		#address-cells = <1>;
-		#size-cells = <1>;
-	};
-
-	dp@145b0000 {
-		compatible = "samsung,exynos5-dp";
-		reg = <0x145b0000 0x1000>;
-		#address-cells = <1>;
-		#size-cells = <1>;
-	};
-
-	mmc@12200000 {
-		#address-cells = <1>;
-		#size-cells = <0>;
-		compatible = "samsung,exynos5250-dwmmc";
-		reg = <0x12200000 0x1000>;
-		interrupts = <0 75 0>;
-	};
-
-	mmc@12210000 {
-		#address-cells = <1>;
-		#size-cells = <0>;
-		compatible = "samsung,exynos5250-dwmmc";
-		reg = <0x12210000 0x1000>;
-		interrupts = <0 76 0>;
-	};
-
-	mmc@12220000 {
-		#address-cells = <1>;
-		#size-cells = <0>;
-		compatible = "samsung,exynos5250-dwmmc";
-		reg = <0x12220000 0x1000>;
-		interrupts = <0 77 0>;
-	};
-
-	mmc@12230000 {
-		#address-cells = <1>;
-		#size-cells = <0>;
-		compatible = "samsung,exynos5250-dwmmc";
-		reg = <0x12230000 0x1000>;
-		interrupts = <0 78 0>;
-	};
-
-	serial@12C00000 {
-		compatible = "samsung,exynos4210-uart";
-		reg = <0x12C00000 0x100>;
-		interrupts = <0 51 0>;
-		id = <0>;
-	};
-
-	serial@12C10000 {
-		compatible = "samsung,exynos4210-uart";
-		reg = <0x12C10000 0x100>;
-		interrupts = <0 52 0>;
-		id = <1>;
-	};
-
-	serial@12C20000 {
-		compatible = "samsung,exynos4210-uart";
-		reg = <0x12C20000 0x100>;
-		interrupts = <0 53 0>;
-		id = <2>;
-	};
-
-	serial@12C30000 {
-		compatible = "samsung,exynos4210-uart";
-		reg = <0x12C30000 0x100>;
-		interrupts = <0 54 0>;
-		id = <3>;
-	};
-
-	gpio: gpio {
-	};
 };
diff --git a/arch/arm/dts/exynos5420-smdk5420.dts b/arch/arm/dts/exynos5420-smdk5420.dts
new file mode 100644
index 0000000000..d73976356d
--- /dev/null
+++ b/arch/arm/dts/exynos5420-smdk5420.dts
@@ -0,0 +1,169 @@
+/*
+ * SAMSUNG SMDK5420 board device tree source
+ *
+ * Copyright (c) 2013 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/dts-v1/;
+/include/ "exynos5420.dtsi"
+
+/ {
+	model = "SAMSUNG SMDK5420 board based on EXYNOS5420";
+	compatible = "samsung,smdk5420", "samsung,exynos5";
+
+	config {
+		hwid = "smdk5420 TEST A-A 9382";
+	};
+
+	aliases {
+		i2c0 = "/i2c@12c60000";
+		i2c1 = "/i2c@12c70000";
+		i2c2 = "/i2c@12c80000";
+		i2c3 = "/i2c@12c90000";
+		i2c4 = "/i2c@12ca0000";
+		i2c5 = "/i2c@12cb0000";
+		i2c6 = "/i2c@12cc0000";
+		i2c7 = "/i2c@12cd0000";
+		i2c8 = "/i2c@12e00000";
+		i2c9 = "/i2c@12e10000";
+		i2c10 = "/i2c@12e20000";
+		spi0 = "/spi@12d20000";
+		spi1 = "/spi@12d30000";
+		spi2 = "/spi@12d40000";
+		spi3 = "/spi@131a0000";
+		spi4 = "/spi@131b0000";
+		mmc0 = "/mmc@12200000";
+		mmc1 = "/mmc@12210000";
+		mmc2 = "/mmc@12220000";
+		xhci0 = "/xhci@12000000";
+		xhci1 = "/xhci@12400000";
+		serial0 = "/serial@12C30000";
+		console = "/serial@12C30000";
+	};
+
+	tmu@10060000 {
+		samsung,min-temp	= <25>;
+		samsung,max-temp	= <125>;
+		samsung,start-warning	= <95>;
+		samsung,start-tripping	= <105>;
+		samsung,hw-tripping	= <110>;
+		samsung,efuse-min-value	= <40>;
+		samsung,efuse-value	= <55>;
+		samsung,efuse-max-value	= <100>;
+		samsung,slope		= <274761730>;
+		samsung,dc-value	= <25>;
+	};
+
+	/* s2mps11 is on i2c bus 4 */
+	i2c@12ca0000 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		pmic@66 {
+			reg = <0x66>;
+			compatible = "samsung,s2mps11-pmic";
+		};
+	};
+
+	spi@12d20000 { /* spi0 */
+		spi-max-frequency = <50000000>;
+		firmware_storage_spi: flash@0 {
+			reg = <0>;
+		};
+	};
+
+	fimd@14400000 {
+		samsung,vl-freq = <60>;
+		samsung,vl-col = <2560>;
+		samsung,vl-row = <1600>;
+		samsung,vl-width = <2560>;
+		samsung,vl-height = <1600>;
+
+		samsung,vl-clkp;
+		samsung,vl-dp;
+		samsung,vl-bpix = <4>;
+
+		samsung,vl-hspw = <32>;
+		samsung,vl-hbpd = <80>;
+		samsung,vl-hfpd = <48>;
+		samsung,vl-vspw = <6>;
+		samsung,vl-vbpd = <37>;
+		samsung,vl-vfpd = <3>;
+		samsung,vl-cmd-allow-len = <0xf>;
+
+		samsung,winid = <3>;
+		samsung,interface-mode = <1>;
+		samsung,dp-enabled = <1>;
+		samsung,dual-lcd-enabled = <0>;
+	};
+
+	sound@3830000 {
+		samsung,codec-type = "wm8994";
+	};
+
+	i2c@12c70000 {
+		soundcodec@1a {
+			reg = <0x1a>;
+			compatible = "wolfson,wm8994-codec";
+		};
+	};
+
+	mmc@12200000 {
+		samsung,bus-width = <8>;
+		samsung,timing = <1 3 3>;
+		samsung,removable = <0>;
+		samsung,pre-init;
+	};
+
+	mmc@12210000 {
+		status = "disabled";
+	};
+
+	mmc@12220000 {
+		samsung,bus-width = <4>;
+		samsung,timing = <1 2 3>;
+		samsung,removable = <1>;
+	};
+
+	mmc@12230000 {
+		status = "disabled";
+	};
+
+	fimd@14400000 {
+		/* sysmmu is not used in U-Boot */
+		samsung,disable-sysmmu;
+	};
+
+	dp@145b0000 {
+		samsung,lt-status = <0>;
+
+		samsung,master-mode = <0>;
+		samsung,bist-mode = <0>;
+		samsung,bist-pattern = <0>;
+		samsung,h-sync-polarity = <0>;
+		samsung,v-sync-polarity = <0>;
+		samsung,interlaced = <0>;
+		samsung,color-space = <0>;
+		samsung,dynamic-range = <0>;
+		samsung,ycbcr-coeff = <0>;
+		samsung,color-depth = <1>;
+	};
+
+	dmc {
+		mem-type = "ddr3";
+	};
+
+	xhci1: xhci@12400000 {
+		compatible = "samsung,exynos5250-xhci";
+		reg = <0x12400000 0x10000>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		phy {
+			compatible = "samsung,exynos5250-usb3-phy";
+			reg = <0x12500000 0x100>;
+		};
+	};
+};
diff --git a/arch/arm/dts/exynos5420.dtsi b/arch/arm/dts/exynos5420.dtsi
new file mode 100644
index 0000000000..02ead61a49
--- /dev/null
+++ b/arch/arm/dts/exynos5420.dtsi
@@ -0,0 +1,70 @@
+/*
+ * (C) Copyright 2013 SAMSUNG Electronics
+ * SAMSUNG EXYNOS5420 SoC device tree source
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/include/ "exynos5.dtsi"
+
+/ {
+	config {
+		machine-arch-id = <4151>;
+	};
+
+	i2c@12ca0000 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "samsung,exynos5-hsi2c";
+		reg = <0x12CA0000 0x100>;
+		interrupts = <0 60 0>;
+	};
+
+	i2c@12cb0000 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "samsung,exynos5-hsi2c";
+		reg = <0x12CB0000 0x100>;
+		interrupts = <0 61 0>;
+	};
+
+	i2c@12cc0000 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "samsung,exynos5-hsi2c";
+		reg = <0x12CC0000 0x100>;
+		interrupts = <0 62 0>;
+	};
+
+	i2c@12cd0000 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "samsung,exynos5-hsi2c";
+		reg = <0x12CD0000 0x100>;
+		interrupts = <0 63 0>;
+	};
+
+	i2c@12e00000 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "samsung,exynos5-hsi2c";
+		reg = <0x12E00000 0x100>;
+		interrupts = <0 87 0>;
+	};
+
+	i2c@12e10000 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "samsung,exynos5-hsi2c";
+		reg = <0x12E10000 0x100>;
+		interrupts = <0 88 0>;
+	};
+
+	i2c@12e20000 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "samsung,exynos5-hsi2c";
+		reg = <0x12E20000 0x100>;
+		interrupts = <0 203 0>;
+	};
+};
diff --git a/arch/arm/dts/imx6q-sabreauto.dts b/arch/arm/dts/imx6q-sabreauto.dts
new file mode 100644
index 0000000000..a3c9c91f32
--- /dev/null
+++ b/arch/arm/dts/imx6q-sabreauto.dts
@@ -0,0 +1,13 @@
+/*
+    + * Copyright 2012 Freescale Semiconductor, Inc.
+    + * Copyright 2011 Linaro Ltd.
+    + *
+    + * SPDX-License-Identifier:     GPL-2.0+
+    + */
+
+/dts-v1/;
+
+/ {
+	model = "Freescale i.MX6 Quad SABRE Automotive Board";
+	compatible = "fsl,imx6q-sabreauto", "fsl,imx6q";
+};
diff --git a/board/nvidia/dts/tegra114-dalmore.dts b/arch/arm/dts/tegra114-dalmore.dts
index 435c01e9f6..435c01e9f6 100644
--- a/board/nvidia/dts/tegra114-dalmore.dts
+++ b/arch/arm/dts/tegra114-dalmore.dts
diff --git a/arch/arm/dts/tegra114.dtsi b/arch/arm/dts/tegra114.dtsi
index 626cc3c982..f52fcf14dd 100644
--- a/arch/arm/dts/tegra114.dtsi
+++ b/arch/arm/dts/tegra114.dtsi
@@ -139,7 +139,7 @@
 
 	spi@7000d800 {
 		compatible = "nvidia,tegra114-spi";
-		reg = <0x7000d480 0x200>;
+		reg = <0x7000d800 0x200>;
 		interrupts = <0 83 0x04>;
 		nvidia,dma-request-selector = <&apbdma 17>;
 		#address-cells = <1>;
diff --git a/arch/arm/dts/tegra124-venice2.dts b/arch/arm/dts/tegra124-venice2.dts
new file mode 100644
index 0000000000..2f8d1dcc37
--- /dev/null
+++ b/arch/arm/dts/tegra124-venice2.dts
@@ -0,0 +1,84 @@
+/dts-v1/;
+
+#include "tegra124.dtsi"
+
+/ {
+	model = "NVIDIA Venice2";
+	compatible = "nvidia,venice2", "nvidia,tegra124";
+
+	aliases {
+		i2c0 = "/i2c@7000d000";
+		i2c1 = "/i2c@7000c000";
+		i2c2 = "/i2c@7000c400";
+		i2c3 = "/i2c@7000c500";
+		i2c4 = "/i2c@7000c700";
+		i2c5 = "/i2c@7000d100";
+		sdhci0 = "/sdhci@700b0600";
+		sdhci1 = "/sdhci@700b0400";
+		spi0 = "/spi@7000d400";
+		spi1 = "/spi@7000da00";
+		usb0 = "/usb@7d008000";
+	};
+
+	memory {
+		device_type = "memory";
+		reg = <0x80000000 0x80000000>;
+	};
+
+	i2c@7000c000 {
+		status = "okay";
+		clock-frequency = <100000>;
+	};
+
+	i2c@7000c400 {
+		status = "okay";
+		clock-frequency = <100000>;
+	};
+
+	i2c@7000c500 {
+		status = "okay";
+		clock-frequency = <100000>;
+	};
+
+	i2c@7000c700 {
+		status = "okay";
+		clock-frequency = <100000>;
+	};
+
+	i2c@7000d000 {
+		status = "okay";
+		clock-frequency = <400000>;
+	};
+
+	i2c@7000d100 {
+		status = "okay";
+		clock-frequency = <400000>;
+	};
+
+	spi@7000d400 {
+		status = "okay";
+		spi-max-frequency = <25000000>;
+	};
+
+	spi@7000da00 {
+		status = "okay";
+		spi-max-frequency = <25000000>;
+	};
+
+	sdhci@700b0400 {
+		status = "okay";
+		cd-gpios = <&gpio 170 0>; /* gpio PV2 */
+		power-gpios = <&gpio 136 0>; /* gpio PR0 */
+		bus-width = <4>;
+	};
+
+	sdhci@700b0600 {
+		status = "okay";
+		bus-width = <8>;
+	};
+
+	usb@7d008000 {
+		status = "okay";
+		nvidia,vbus-gpio = <&gpio 109 0>; /* gpio PN5, USB_VBUS_EN1 */
+	};
+};
diff --git a/arch/arm/dts/tegra124.dtsi b/arch/arm/dts/tegra124.dtsi
new file mode 100644
index 0000000000..18a8b24b71
--- /dev/null
+++ b/arch/arm/dts/tegra124.dtsi
@@ -0,0 +1,250 @@
+#include "skeleton.dtsi"
+
+/ {
+	compatible = "nvidia,tegra124";
+
+	tegra_car: clock@60006000 {
+		compatible = "nvidia,tegra124-car";
+		reg = <0x60006000 0x1000>;
+		#clock-cells = <1>;
+	};
+
+	apbdma: dma@60020000 {
+		compatible = "nvidia,tegra124-apbdma", "nvidia,tegra148-apbdma";
+		reg = <0x60020000 0x1400>;
+		interrupts = <0 104 0x04
+			      0 105 0x04
+			      0 106 0x04
+			      0 107 0x04
+			      0 108 0x04
+			      0 109 0x04
+			      0 110 0x04
+			      0 111 0x04
+			      0 112 0x04
+			      0 113 0x04
+			      0 114 0x04
+			      0 115 0x04
+			      0 116 0x04
+			      0 117 0x04
+			      0 118 0x04
+			      0 119 0x04
+			      0 128 0x04
+			      0 129 0x04
+			      0 130 0x04
+			      0 131 0x04
+			      0 132 0x04
+			      0 133 0x04
+			      0 134 0x04
+			      0 135 0x04
+			      0 136 0x04
+			      0 137 0x04
+			      0 138 0x04
+			      0 139 0x04
+			      0 140 0x04
+			      0 141 0x04
+			      0 142 0x04
+			      0 143 0x04>;
+	};
+
+	gpio: gpio@6000d000 {
+		compatible = "nvidia,tegra124-gpio", "nvidia,tegra30-gpio";
+		reg = <0x6000d000 0x1000>;
+		interrupts = <0 32 0x04
+			      0 33 0x04
+			      0 34 0x04
+			      0 35 0x04
+			      0 55 0x04
+			      0 87 0x04
+			      0 89 0x04
+			      0 125 0x04>;
+		#gpio-cells = <2>;
+		gpio-controller;
+		#interrupt-cells = <2>;
+		interrupt-controller;
+	};
+
+	i2c@7000c000 {
+		compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
+		reg = <0x7000c000 0x100>;
+		interrupts = <0 38 0x04>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		clocks = <&tegra_car 12>;
+		status = "disabled";
+	};
+
+	i2c@7000c400 {
+		compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
+		reg = <0x7000c400 0x100>;
+		interrupts = <0 84 0x04>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		clocks = <&tegra_car 54>;
+		status = "disabled";
+	};
+
+	i2c@7000c500 {
+		compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
+		reg = <0x7000c500 0x100>;
+		interrupts = <0 92 0x04>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		clocks = <&tegra_car 67>;
+		status = "disabled";
+	};
+
+	i2c@7000c700 {
+		compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
+		reg = <0x7000c700 0x100>;
+		interrupts = <0 120 0x04>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		clocks = <&tegra_car 103>;
+		status = "disabled";
+	};
+
+	i2c@7000d000 {
+		compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
+		reg = <0x7000d000 0x100>;
+		interrupts = <0 53 0x04>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		clocks = <&tegra_car 47>;
+		status = "disabled";
+	};
+
+	i2c@7000d100 {
+		compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
+		reg = <0x7000d100 0x100>;
+		interrupts = <0 53 0x04>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		clocks = <&tegra_car 47>;
+		status = "disabled";
+	};
+
+	spi@7000d400 {
+		compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
+		reg = <0x7000d400 0x200>;
+		interrupts = <0 59 0x04>;
+		nvidia,dma-request-selector = <&apbdma 15>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		status = "disabled";
+		clocks = <&tegra_car 41>;
+	};
+
+	spi@7000d600 {
+		compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
+		reg = <0x7000d600 0x200>;
+		interrupts = <0 82 0x04>;
+		nvidia,dma-request-selector = <&apbdma 16>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		status = "disabled";
+		clocks = <&tegra_car 44>;
+	};
+
+	spi@7000d800 {
+		compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
+		reg = <0x7000d800 0x200>;
+		interrupts = <0 83 0x04>;
+		nvidia,dma-request-selector = <&apbdma 17>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		status = "disabled";
+		clocks = <&tegra_car 46>;
+	};
+
+	spi@7000da00 {
+		compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
+		reg = <0x7000da00 0x200>;
+		interrupts = <0 93 0x04>;
+		nvidia,dma-request-selector = <&apbdma 18>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		status = "disabled";
+		clocks = <&tegra_car 68>;
+	};
+
+	spi@7000dc00 {
+		compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
+		reg = <0x7000dc00 0x200>;
+		interrupts = <0 94 0x04>;
+		nvidia,dma-request-selector = <&apbdma 27>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		status = "disabled";
+		clocks = <&tegra_car 104>;
+	};
+
+	spi@7000de00 {
+		compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
+		reg = <0x7000de00 0x200>;
+		interrupts = <0 79 0x04>;
+		nvidia,dma-request-selector = <&apbdma 28>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		status = "disabled";
+		clocks = <&tegra_car 105>;
+	};
+
+	sdhci@700b0000 {
+		compatible = "nvidia,tegra124-sdhci";
+		reg = <0x700b0000 0x200>;
+		interrupts = <0 14 0x04>;
+		clocks = <&tegra_car 14>;
+		status = "disabled";
+	};
+
+	sdhci@700b0200 {
+		compatible = "nvidia,tegra124-sdhci";
+		reg = <0x700b0200 0x200>;
+		interrupts = <0 15 0x04>;
+		clocks = <&tegra_car 9>;
+		status = "disabled";
+	};
+
+	sdhci@700b0400 {
+		compatible = "nvidia,tegra124-sdhci";
+		reg = <0x700b0400 0x200>;
+		interrupts = <0 19 0x04>;
+		clocks = <&tegra_car 69>;
+		status = "disabled";
+	};
+
+	sdhci@700b0600 {
+		compatible = "nvidia,tegra124-sdhci";
+		reg = <0x700b0600 0x200>;
+		interrupts = <0 31 0x04>;
+		clocks = <&tegra_car 15>;
+		status = "disabled";
+	};
+
+	usb@7d000000 {
+		compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci";
+		reg = <0x7d000000 0x4000>;
+		interrupts = < 52 >;
+		phy_type = "utmi";
+		clocks = <&tegra_car 22>;	/* PERIPH_ID_USBD */
+		status = "disabled";
+	};
+
+	usb@7d004000 {
+		compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci";
+		reg = <0x7d004000 0x4000>;
+		interrupts = < 53 >;
+		phy_type = "hsic";
+		clocks = <&tegra_car 58>;	/* PERIPH_ID_USB2 */
+		status = "disabled";
+	};
+
+	usb@7d008000 {
+		compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci";
+		reg = <0x7d008000 0x4000>;
+		interrupts = < 129 >;
+		phy_type = "utmi";
+		clocks = <&tegra_car 59>;	/* PERIPH_ID_USB3 */
+		status = "disabled";
+	};
+};
diff --git a/board/toradex/dts/tegra20-colibri_t20_iris.dts b/arch/arm/dts/tegra20-colibri_t20_iris.dts
index c0e54af886..c0e54af886 100644
--- a/board/toradex/dts/tegra20-colibri_t20_iris.dts
+++ b/arch/arm/dts/tegra20-colibri_t20_iris.dts
diff --git a/board/nvidia/dts/tegra20-harmony.dts b/arch/arm/dts/tegra20-harmony.dts
index b115f87821..b115f87821 100644
--- a/board/nvidia/dts/tegra20-harmony.dts
+++ b/arch/arm/dts/tegra20-harmony.dts
diff --git a/board/avionic-design/dts/tegra20-medcom-wide.dts b/arch/arm/dts/tegra20-medcom-wide.dts
index a9a07f9bcd..a9a07f9bcd 100644
--- a/board/avionic-design/dts/tegra20-medcom-wide.dts
+++ b/arch/arm/dts/tegra20-medcom-wide.dts
diff --git a/board/compal/dts/tegra20-paz00.dts b/arch/arm/dts/tegra20-paz00.dts
index 780203cfb3..780203cfb3 100644
--- a/board/compal/dts/tegra20-paz00.dts
+++ b/arch/arm/dts/tegra20-paz00.dts
diff --git a/board/avionic-design/dts/tegra20-plutux.dts b/arch/arm/dts/tegra20-plutux.dts
index 20016f29bb..20016f29bb 100644
--- a/board/avionic-design/dts/tegra20-plutux.dts
+++ b/arch/arm/dts/tegra20-plutux.dts
diff --git a/board/nvidia/dts/tegra20-seaboard.dts b/arch/arm/dts/tegra20-seaboard.dts
index c0e2e1e5fd..c0e2e1e5fd 100644
--- a/board/nvidia/dts/tegra20-seaboard.dts
+++ b/arch/arm/dts/tegra20-seaboard.dts
diff --git a/board/avionic-design/dts/tegra20-tamonten.dtsi b/arch/arm/dts/tegra20-tamonten.dtsi
index f379622c94..f379622c94 100644
--- a/board/avionic-design/dts/tegra20-tamonten.dtsi
+++ b/arch/arm/dts/tegra20-tamonten.dtsi
diff --git a/board/avionic-design/dts/tegra20-tec.dts b/arch/arm/dts/tegra20-tec.dts
index 4c1b08d768..4c1b08d768 100644
--- a/board/avionic-design/dts/tegra20-tec.dts
+++ b/arch/arm/dts/tegra20-tec.dts
diff --git a/board/compulab/dts/tegra20-trimslice.dts b/arch/arm/dts/tegra20-trimslice.dts
index ee31476c1e..ee31476c1e 100644
--- a/board/compulab/dts/tegra20-trimslice.dts
+++ b/arch/arm/dts/tegra20-trimslice.dts
diff --git a/board/nvidia/dts/tegra20-ventana.dts b/arch/arm/dts/tegra20-ventana.dts
index 1a526bab64..1a526bab64 100644
--- a/board/nvidia/dts/tegra20-ventana.dts
+++ b/arch/arm/dts/tegra20-ventana.dts
diff --git a/board/nvidia/dts/tegra20-whistler.dts b/arch/arm/dts/tegra20-whistler.dts
index eb92264f9d..eb92264f9d 100644
--- a/board/nvidia/dts/tegra20-whistler.dts
+++ b/arch/arm/dts/tegra20-whistler.dts
diff --git a/board/nvidia/dts/tegra30-beaver.dts b/arch/arm/dts/tegra30-beaver.dts
index a7cc93e93f..a7cc93e93f 100644
--- a/board/nvidia/dts/tegra30-beaver.dts
+++ b/arch/arm/dts/tegra30-beaver.dts
diff --git a/board/nvidia/dts/tegra30-cardhu.dts b/arch/arm/dts/tegra30-cardhu.dts
index ea2cf76ff3..ea2cf76ff3 100644
--- a/board/nvidia/dts/tegra30-cardhu.dts
+++ b/arch/arm/dts/tegra30-cardhu.dts
diff --git a/arch/arm/dts/tegra30-tamonten.dtsi b/arch/arm/dts/tegra30-tamonten.dtsi
new file mode 100644
index 0000000000..50d5762311
--- /dev/null
+++ b/arch/arm/dts/tegra30-tamonten.dtsi
@@ -0,0 +1,69 @@
+#include "tegra30.dtsi"
+
+/ {
+	model = "Avionic Design Tamonten NG";
+	compatible = "ad,tamonten-ng", "nvidia,tegra30";
+
+	memory {
+		reg = <0x80000000 0x40000000>;
+	};
+
+	aliases {
+		i2c0 = "/i2c@7000c000";
+		i2c1 = "/i2c@7000c700";
+		i2c2 = "/i2c@7000c400";
+		i2c3 = "/i2c@7000c500";
+		i2c4 = "/i2c@7000d000";
+		sdhci0 = "/sdhci@78000600";
+		sdhci1 = "/sdhci@78000400";
+		sdhci2 = "/sdhci@78000000";
+		usb0 = "/usb@7d008000";
+	};
+
+	/* GEN1 */
+	i2c@7000c000 {
+		status = "okay";
+		clock-frequency = <100000>;
+	};
+
+	/* GEN2 */
+	i2c@7000c400 {
+		clock-frequency = <100000>;
+	};
+
+	/* CAM */
+	i2c@7000c500 {
+		status = "okay";
+		clock-frequency = <100000>;
+	};
+
+	/* DDC */
+	i2c@7000c700 {
+		status = "okay";
+		clock-frequency = <100000>;
+	};
+
+	/* PWR */
+	i2c@7000d000 {
+		status = "okay";
+		clock-frequency = <100000>;
+	};
+
+	/* SD slot on the base board */
+	sdhci@78000400 {
+		cd-gpios = <&gpio 69 1>; /* gpio PI5 */
+		wp-gpios = <&gpio 67 0>; /* gpio PI3 */
+		bus-width = <4>;
+	};
+
+	/* EMMC on the COM module */
+	sdhci@78000600 {
+		status = "okay";
+		bus-width = <8>;
+	};
+
+	usb@7d008000 {
+		status = "okay";
+	};
+
+};
diff --git a/arch/arm/dts/tegra30-tec-ng.dts b/arch/arm/dts/tegra30-tec-ng.dts
new file mode 100644
index 0000000000..8a69e818ca
--- /dev/null
+++ b/arch/arm/dts/tegra30-tec-ng.dts
@@ -0,0 +1,18 @@
+/dts-v1/;
+
+#include "tegra30-tamonten.dtsi"
+
+/ {
+	model = "Avionic Design Tamonten™ NG Evaluation Carrier";
+	compatible = "ad,tec-ng", "nvidia,tegra30";
+
+	/* GEN2 */
+	i2c@7000c400 {
+		status = "okay";
+	};
+
+	/* SD card slot */
+	sdhci@78000400 {
+		status = "okay";
+	};
+};
diff --git a/arch/arm/dts/zynq-7000.dtsi b/arch/arm/dts/zynq-7000.dtsi
new file mode 100644
index 0000000000..f20b8bd604
--- /dev/null
+++ b/arch/arm/dts/zynq-7000.dtsi
@@ -0,0 +1,13 @@
+/*
+ * Xilinx Zynq 7000 DTSI
+ * Describes the hardware common to all Zynq 7000-based boards.
+ *
+ * Copyright (C) 2013 Xilinx, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+/include/ "skeleton.dtsi"
+
+/ {
+	compatible = "xlnx,zynq-7000";
+};
diff --git a/arch/arm/dts/zynq-microzed.dts b/arch/arm/dts/zynq-microzed.dts
new file mode 100644
index 0000000000..6da71c116d
--- /dev/null
+++ b/arch/arm/dts/zynq-microzed.dts
@@ -0,0 +1,14 @@
+/*
+ * Xilinx MicroZED board DTS
+ *
+ * Copyright (C) 2013 Xilinx, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+/dts-v1/;
+#include "zynq-7000.dtsi"
+
+/ {
+	model = "Zynq MicroZED Board";
+	compatible = "xlnx,zynq-microzed", "xlnx,zynq-7000";
+};
diff --git a/arch/arm/dts/zynq-zc702.dts b/arch/arm/dts/zynq-zc702.dts
new file mode 100644
index 0000000000..667dc28256
--- /dev/null
+++ b/arch/arm/dts/zynq-zc702.dts
@@ -0,0 +1,14 @@
+/*
+ * Xilinx ZC702 board DTS
+ *
+ * Copyright (C) 2013 Xilinx, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+/dts-v1/;
+#include "zynq-7000.dtsi"
+
+/ {
+	model = "Zynq ZC702 Board";
+	compatible = "xlnx,zynq-zc702", "xlnx,zynq-7000";
+};
diff --git a/arch/arm/dts/zynq-zc706.dts b/arch/arm/dts/zynq-zc706.dts
new file mode 100644
index 0000000000..526fc8888b
--- /dev/null
+++ b/arch/arm/dts/zynq-zc706.dts
@@ -0,0 +1,14 @@
+/*
+ * Xilinx ZC706 board DTS
+ *
+ * Copyright (C) 2013 Xilinx, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+/dts-v1/;
+#include "zynq-7000.dtsi"
+
+/ {
+	model = "Zynq ZC706 Board";
+	compatible = "xlnx,zynq-zc706", "xlnx,zynq-7000";
+};
diff --git a/arch/arm/dts/zynq-zc770-xm010.dts b/arch/arm/dts/zynq-zc770-xm010.dts
new file mode 100644
index 0000000000..8b542a109b
--- /dev/null
+++ b/arch/arm/dts/zynq-zc770-xm010.dts
@@ -0,0 +1,14 @@
+/*
+ * Xilinx ZC770 XM010 board DTS
+ *
+ * Copyright (C) 2013 Xilinx, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+/dts-v1/;
+#include "zynq-7000.dtsi"
+
+/ {
+	model = "Zynq ZC770 XM010 Board";
+	compatible = "xlnx,zynq-zc770-xm010", "xlnx,zynq-7000";
+};
diff --git a/arch/arm/dts/zynq-zc770-xm012.dts b/arch/arm/dts/zynq-zc770-xm012.dts
new file mode 100644
index 0000000000..0379a07068
--- /dev/null
+++ b/arch/arm/dts/zynq-zc770-xm012.dts
@@ -0,0 +1,14 @@
+/*
+ * Xilinx ZC770 XM012 board DTS
+ *
+ * Copyright (C) 2013 Xilinx, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+/dts-v1/;
+#include "zynq-7000.dtsi"
+
+/ {
+	model = "Zynq ZC770 XM012 Board";
+	compatible = "xlnx,zynq-zc770-xm012", "xlnx,zynq-7000";
+};
diff --git a/arch/arm/dts/zynq-zc770-xm013.dts b/arch/arm/dts/zynq-zc770-xm013.dts
new file mode 100644
index 0000000000..a4f9e05fc0
--- /dev/null
+++ b/arch/arm/dts/zynq-zc770-xm013.dts
@@ -0,0 +1,14 @@
+/*
+ * Xilinx ZC770 XM013 board DTS
+ *
+ * Copyright (C) 2013 Xilinx, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+/dts-v1/;
+#include "zynq-7000.dtsi"
+
+/ {
+	model = "Zynq ZC770 XM013 Board";
+	compatible = "xlnx,zynq-zc770-xm013", "xlnx,zynq-7000";
+};
diff --git a/arch/arm/dts/zynq-zed.dts b/arch/arm/dts/zynq-zed.dts
new file mode 100644
index 0000000000..91a5deba4a
--- /dev/null
+++ b/arch/arm/dts/zynq-zed.dts
@@ -0,0 +1,14 @@
+/*
+ * Xilinx ZED board DTS
+ *
+ * Copyright (C) 2013 Xilinx, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+/dts-v1/;
+#include "zynq-7000.dtsi"
+
+/ {
+	model = "Zynq ZED Board";
+	compatible = "xlnx,zynq-zed", "xlnx,zynq-7000";
+};
diff --git a/arch/arm/imx-common/Makefile b/arch/arm/imx-common/Makefile
index 727a052806..d6fdd383ca 100644
--- a/arch/arm/imx-common/Makefile
+++ b/arch/arm/imx-common/Makefile
@@ -7,73 +7,88 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB     = $(obj)libimx-common.o
-
 ifeq ($(SOC),$(filter $(SOC),mx25 mx35 mx5 mx6 vf610))
-COBJS-y	= iomux-v3.o
+obj-y	= iomux-v3.o
 endif
 ifeq ($(SOC),$(filter $(SOC),mx5 mx6))
-COBJS-y	+= timer.o cpu.o speed.o
-COBJS-$(CONFIG_I2C_MXC) += i2c-mxv7.o
+obj-y	+= timer.o cpu.o speed.o
+obj-$(CONFIG_SYS_I2C_MXC) += i2c-mxv7.o
 endif
 ifeq ($(SOC),$(filter $(SOC),mx6 mxs))
-COBJS-y	+= misc.o
+obj-y	+= misc.o
+endif
+ifeq ($(SOC),$(filter $(SOC),mx6))
+obj-$(CONFIG_CMD_SATA) += sata.o
+endif
+obj-$(CONFIG_CMD_BMODE) += cmd_bmode.o
+obj-$(CONFIG_CMD_HDMIDETECT) += cmd_hdmidet.o
+obj-$(CONFIG_CMD_WRITEBCB) += cmd_writebcb.o
+
+quiet_cmd_cpp_cfg = CFGS    $@
+      cmd_cpp_cfg = $(CPP) $(cpp_flags) -x c -o $@ $<
+
+IMX_CONFIG = $(CONFIG_IMX_CONFIG:"%"=%).cfgtmp
+
+$(IMX_CONFIG): %.cfgtmp: % FORCE
+	$(Q)mkdir -p $(dir $@)
+	$(call if_changed_dep,cpp_cfg)
+
+quiet_cmd_mkimage = MKIMAGE $@
+cmd_mkimage = $(objtree)/tools/mkimage $(MKIMAGEFLAGS_$(@F)) -d $< $@ \
+	$(if $(KBUILD_VERBOSE:1=), >/dev/null)
+
+MKIMAGEFLAGS_u-boot.imx = -n $(filter-out $< $(PHONY),$^) -T imximage \
+	-e $(CONFIG_SYS_TEXT_BASE)
+
+u-boot.imx: u-boot.bin $(IMX_CONFIG) FORCE
+	$(call if_changed,mkimage)
+
+ifeq ($(CONFIG_IMX_NAND),y)
+quiet_cmd_u-boot-nand_imx = GEN     $@
+cmd_u-boot-nand_imx = (dd bs=1024 count=1 if=/dev/zero 2>/dev/null) | \
+       cat - $< > $@
+
+u-boot-nand.imx: u-boot.imx $(IMX_CONFIG) FORCE
+	$(call if_changed,u-boot-nand_imx)
+endif
+
+ifeq ($(CONFIG_OF_SEPARATE),y)
+MKIMAGEFLAGS_u-boot-dtb.imx = -n $(filter-out $< $(PHONY),$^) -T imximage \
+	-e $(CONFIG_SYS_TEXT_BASE)
+
+u-boot-dtb.imx: u-boot-dtb.bin $(IMX_CONFIG) FORCE
+	$(call if_changed,mkimage)
 endif
-COBJS-$(CONFIG_CMD_BMODE) += cmd_bmode.o
-COBJS-$(CONFIG_CMD_HDMIDETECT) += cmd_hdmidet.o
-COBJS	:= $(sort $(COBJS-y))
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS))
-
-all:	$(obj).depend $(LIB)
-
-$(LIB):	$(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-$(OBJTREE)/$(patsubst "%",%,$(CONFIG_IMX_CONFIG)).cfgtmp: $(OBJTREE)/%.cfgtmp : $(SRCTREE)/%
-	mkdir -p $(dir $@)
-	$(CC) -E -x c $< $(CPPFLAGS) -o $@
-
-$(OBJTREE)/u-boot.imx: $(OBJTREE)/u-boot.bin $(OBJTREE)/$(patsubst "%",%,$(CONFIG_IMX_CONFIG)).cfgtmp
-	$(OBJTREE)/tools/mkimage -n $(filter-out %.bin,$^) -T imximage \
-	-e $(CONFIG_SYS_TEXT_BASE) -d $< $@
-
-$(OBJTREE)/SPL: $(OBJTREE)/spl/u-boot-spl.bin $(OBJTREE)/$(patsubst "%",%,$(CONFIG_IMX_CONFIG)).cfgtmp
-	$(OBJTREE)/tools/mkimage -n $(filter-out %.bin,$^) -T imximage \
-	-e $(CONFIG_SPL_TEXT_BASE) -d $< $@
-
-$(OBJTREE)/u-boot-with-spl.imx: $(OBJTREE)/SPL $(OBJTREE)/u-boot.bin
-	$(OBJCOPY) ${OBJCFLAGS} --pad-to=$(CONFIG_SPL_PAD_TO) \
-		-I binary -O binary $< $(OBJTREE)/spl/u-boot-spl-pad.imx
-	$(OBJTREE)/tools/mkimage -A arm -O U-Boot -a $(CONFIG_SYS_TEXT_BASE) \
-		-e $(CONFIG_SYS_TEXT_BASE) -C none -d $(OBJTREE)/u-boot.bin \
-		$(OBJTREE)/u-boot.uim
-	cat $(OBJTREE)/spl/u-boot-spl-pad.imx $(OBJTREE)/u-boot.uim > $@
-	rm $(OBJTREE)/spl/u-boot-spl-pad.imx $(OBJTREE)/u-boot.uim
-
-$(OBJTREE)/u-boot-with-nand-spl.imx: $(OBJTREE)/SPL $(OBJTREE)/u-boot.bin
-	(echo -ne '\x00\x00\x00\x00\x46\x43\x42\x20\x01' && \
-			dd bs=1015 count=1 if=/dev/zero 2>/dev/null) | \
-		cat - $< > $(OBJTREE)/spl/u-boot-nand-spl.imx
-	$(OBJCOPY) ${OBJCFLAGS} --pad-to=$(CONFIG_SPL_PAD_TO) \
-		-I binary -O binary $(OBJTREE)/spl/u-boot-nand-spl.imx \
-		$(OBJTREE)/spl/u-boot-nand-spl-pad.imx
-	rm $(OBJTREE)/spl/u-boot-nand-spl.imx
-	$(OBJTREE)/tools/mkimage -A arm -O U-Boot -a $(CONFIG_SYS_TEXT_BASE) \
-		-e $(CONFIG_SYS_TEXT_BASE) -C none -d $(OBJTREE)/u-boot.bin \
-		$(OBJTREE)/u-boot.uim
-	cat $(OBJTREE)/spl/u-boot-nand-spl-pad.imx $(OBJTREE)/u-boot.uim > $@
-	rm $(OBJTREE)/spl/u-boot-nand-spl-pad.imx $(OBJTREE)/u-boot.uim
-
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+
+MKIMAGEFLAGS_SPL = -n $(filter-out $< $(PHONY),$^) -T imximage \
+	-e $(CONFIG_SPL_TEXT_BASE)
+
+SPL: spl/u-boot-spl.bin $(IMX_CONFIG) FORCE
+	$(call if_changed,mkimage)
+
+MKIMAGEFLAGS_u-boot.uim = -A arm -O U-Boot -a $(CONFIG_SYS_TEXT_BASE) \
+		-e $(CONFIG_SYS_TEXT_BASE) -C none
+
+u-boot.uim: u-boot.bin FORCE
+	$(call if_changed,mkimage)
+
+OBJCOPYFLAGS += -I binary -O binary --pad-to=$(CONFIG_SPL_PAD_TO)
+append = cat $(filter-out $< $(PHONY), $^) >> $@
+
+quiet_cmd_pad_cat = CAT     $@
+cmd_pad_cat = $(cmd_objcopy) && $(append) || rm -f $@
+
+u-boot-with-spl.imx: SPL u-boot.uim FORCE
+	$(call if_changed,pad_cat)
+
+u-boot-with-nand-spl.imx: spl/u-boot-nand-spl.imx u-boot.uim FORCE
+	$(call if_changed,pad_cat)
+
+quiet_cmd_u-boot-nand-spl_imx = GEN     $@
+cmd_u-boot-nand-spl_imx = (echo -ne '\x00\x00\x00\x00\x46\x43\x42\x20\x01' && \
+	dd bs=1015 count=1 if=/dev/zero 2>/dev/null) | cat - $< > $@
+
+spl/u-boot-nand-spl.imx: SPL FORCE
+	$(call if_changed,u-boot-nand-spl_imx)
+
+targets += $(addprefix ../../../,$(IMX_CONFIG) SPL u-boot.uim spl/u-boot-nand-spl.imx)
diff --git a/arch/arm/imx-common/cmd_writebcb.c b/arch/arm/imx-common/cmd_writebcb.c
new file mode 100644
index 0000000000..9a7757d11a
--- /dev/null
+++ b/arch/arm/imx-common/cmd_writebcb.c
@@ -0,0 +1,181 @@
+/*
+ * Copyright (c) 2013, Toradex AG.  All rights reserved.
+ *
+ * Derived from downstream U-Boot (drivers/mtd/nand/fsl_nfc.c)
+ * and mxsboot
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <nand.h>
+#include <malloc.h>
+
+struct mxs_nand_fcb {
+	uint32_t		checksum;
+	uint32_t		fingerprint;
+	uint32_t		version;
+	struct {
+		uint8_t			data_setup;
+		uint8_t			data_hold;
+		uint8_t			address_setup;
+		uint8_t			dsample_time;
+		uint8_t			nand_timing_state;
+		uint8_t			rea;
+		uint8_t			rloh;
+		uint8_t			rhoh;
+	}			timing;
+	uint32_t		page_data_size;
+	uint32_t		total_page_size;
+	uint32_t		sectors_per_block;
+	uint32_t		number_of_nands;		/* Ignored */
+	uint32_t		total_internal_die;		/* Ignored */
+	uint32_t		cell_type;			/* Ignored */
+	uint32_t		ecc_block_n_ecc_type;
+	uint32_t		ecc_block_0_size;
+	uint32_t		ecc_block_n_size;
+	uint32_t		ecc_block_0_ecc_type;
+	uint32_t		metadata_bytes;
+	uint32_t		num_ecc_blocks_per_page;
+	uint32_t		ecc_block_n_ecc_level_sdk;	/* Ignored */
+	uint32_t		ecc_block_0_size_sdk;		/* Ignored */
+	uint32_t		ecc_block_n_size_sdk;		/* Ignored */
+	uint32_t		ecc_block_0_ecc_level_sdk;	/* Ignored */
+	uint32_t		num_ecc_blocks_per_page_sdk;	/* Ignored */
+	uint32_t		metadata_bytes_sdk;		/* Ignored */
+	uint32_t		erase_threshold;
+	uint32_t		boot_patch;
+	uint32_t		patch_sectors;
+	uint32_t		firmware1_starting_sector;
+	uint32_t		firmware2_starting_sector;
+	uint32_t		sectors_in_firmware1;
+	uint32_t		sectors_in_firmware2;
+	uint32_t		dbbt_search_area_start_address;
+	uint32_t		badblock_marker_byte;
+	uint32_t		badblock_marker_start_bit;
+	uint32_t		bb_marker_physical_offset;
+	uint32_t		reserved1[9];
+	uint32_t		disbbm;
+	uint32_t		reserved2[10];
+	uint32_t		disbbm_search;
+	uint32_t		disbbm_search_limit;
+};
+
+struct mxs_nand_dbbt {
+	uint32_t		checksum;
+	uint32_t		fingerprint;
+	uint32_t		version;
+	uint32_t		number_bb;
+	uint32_t		number_2k_pages_bb;
+};
+
+struct mxs_nand_bbt {
+	uint32_t		nand;
+	uint32_t		number_bb;
+	uint32_t		badblock[510];
+};
+
+static inline uint8_t parity_13_8(const uint8_t b)
+{
+	uint32_t parity = 0, tmp;
+
+	tmp = ((b >> 6) ^ (b >> 5) ^ (b >> 3) ^ (b >> 2)) & 1;
+	parity |= tmp << 0;
+
+	tmp = ((b >> 7) ^ (b >> 5) ^ (b >> 4) ^ (b >> 2) ^ (b >> 1)) & 1;
+	parity |= tmp << 1;
+
+	tmp = ((b >> 7) ^ (b >> 6) ^ (b >> 5) ^ (b >> 1) ^ (b >> 0)) & 1;
+	parity |= tmp << 2;
+
+	tmp = ((b >> 7) ^ (b >> 4) ^ (b >> 3) ^ (b >> 0)) & 1;
+	parity |= tmp << 3;
+
+	tmp = ((b >> 6) ^ (b >> 4) ^ (b >> 3) ^
+		(b >> 2) ^ (b >> 1) ^ (b >> 0)) & 1;
+	parity |= tmp << 4;
+
+	return parity;
+}
+
+static void create_fcb(nand_info_t *nand, uint8_t *buf, int fw1_start_address,
+		int fw2_start_address)
+{
+	int i;
+	uint8_t *ecc;
+	struct mxs_nand_fcb *fcb = (struct mxs_nand_fcb *)buf;
+
+	fcb->fingerprint =		0x46434220;
+	fcb->version =			0x00000001;
+
+	fcb->page_data_size =		nand->writesize;
+	fcb->total_page_size =		nand->writesize + nand->oobsize;
+	fcb->sectors_per_block =	nand->erasesize / nand->writesize;
+
+	/* ECC 45, default used by Linux/U-Boot */
+	fcb->ecc_block_0_ecc_type = 6;
+	
+	fcb->firmware1_starting_sector = fw1_start_address / nand->writesize;
+	fcb->firmware2_starting_sector = fw2_start_address / nand->writesize;
+
+	fcb->dbbt_search_area_start_address =	0;
+
+	/* This is typically the first byte of the pages OOB area */
+	fcb->bb_marker_physical_offset = nand->writesize;
+
+	/* Disable swapping of bad block marker byte */
+	fcb->disbbm = 1;
+
+	fcb->disbbm_search = 0;
+	fcb->disbbm_search_limit = 8;
+
+	ecc = buf + 512;
+
+	for (i = 0; i < sizeof(struct mxs_nand_fcb); i++)
+		ecc[i] = parity_13_8(buf[i]);
+}
+
+static int do_write_bcb(cmd_tbl_t *cmdtp, int flag, int argc,
+		       char * const argv[])
+{
+	int ret;
+	nand_info_t *nand;
+	int dev = nand_curr_device;
+	ulong off = 0;
+	uint8_t *buf;
+	size_t rwsize, maxsize;
+	ulong fw1_off, fw2_off = 0;
+
+	if (argc < 2)
+		return -1;
+	
+	fw1_off = simple_strtoul(argv[1], NULL, 16);
+	if (argc > 2)
+		fw2_off = simple_strtoul(argv[2], NULL, 16);
+
+	nand = &nand_info[dev];
+
+	/* Allocate one page, should be enought */
+	rwsize = nand->writesize;
+	buf = malloc(nand->writesize);
+
+	/* Set only the first page empty... */
+	memset(buf, 0, nand->writesize);
+
+	create_fcb(nand, buf, fw1_off, fw2_off);
+
+	puts("Write FCB...\n");
+	rwsize = maxsize = nand->writesize;
+	ret = nand_write_skip_bad(nand, off, &rwsize, NULL, maxsize,
+					  (u_char *)buf, 0);
+
+	printf("FCB %d bytes written to 0x0: %s\n", rwsize, 
+			ret ? "ERROR" : "OK");
+	return 0;
+}
+
+U_BOOT_CMD(
+	writebcb, 3, 0, do_write_bcb,
+	"Write Boot Control Block (FCB and DBBT)",
+	"fw1-off [fw2-off]"
+);
diff --git a/arch/arm/imx-common/cpu.c b/arch/arm/imx-common/cpu.c
index 0cd2538b21..a77c4decc9 100644
--- a/arch/arm/imx-common/cpu.c
+++ b/arch/arm/imx-common/cpu.c
@@ -51,9 +51,9 @@ char *get_reset_cause(void)
 
 #if defined(CONFIG_MX53) || defined(CONFIG_MX6)
 #if defined(CONFIG_MX53)
-#define MEMCTL_BASE	ESDCTL_BASE_ADDR;
+#define MEMCTL_BASE	ESDCTL_BASE_ADDR
 #else
-#define MEMCTL_BASE	MMDC_P0_BASE_ADDR;
+#define MEMCTL_BASE	MMDC_P0_BASE_ADDR
 #endif
 static const unsigned char col_lookup[] = {9, 10, 11, 8, 12, 9, 9, 9};
 static const unsigned char bank_lookup[] = {3, 2};
@@ -106,6 +106,8 @@ const char *get_imx_type(u32 imxtype)
 	switch (imxtype) {
 	case MXC_CPU_MX6Q:
 		return "6Q";	/* Quad-core version of the mx6 */
+	case MXC_CPU_MX6D:
+		return "6D";	/* Dual-core version of the mx6 */
 	case MXC_CPU_MX6DL:
 		return "6DL";	/* Dual Lite version of the mx6 */
 	case MXC_CPU_MX6SOLO:
diff --git a/arch/arm/imx-common/sata.c b/arch/arm/imx-common/sata.c
new file mode 100644
index 0000000000..2e694866e0
--- /dev/null
+++ b/arch/arm/imx-common/sata.c
@@ -0,0 +1,34 @@
+/*
+ * Copyright 2011 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <asm/imx-common/iomux-v3.h>
+#include <asm/arch/iomux.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+
+int setup_sata(void)
+{
+	struct iomuxc_base_regs *const iomuxc_regs
+		= (struct iomuxc_base_regs *)IOMUXC_BASE_ADDR;
+
+	int ret = enable_sata_clock();
+	if (ret)
+		return ret;
+
+	clrsetbits_le32(&iomuxc_regs->gpr[13],
+			IOMUXC_GPR13_SATA_MASK,
+			IOMUXC_GPR13_SATA_PHY_8_RXEQ_3P0DB
+			|IOMUXC_GPR13_SATA_PHY_7_SATA2M
+			|IOMUXC_GPR13_SATA_SPEED_3G
+			|(3<<IOMUXC_GPR13_SATA_PHY_6_SHIFT)
+			|IOMUXC_GPR13_SATA_SATA_PHY_5_SS_DISABLED
+			|IOMUXC_GPR13_SATA_SATA_PHY_4_ATTEN_9_16
+			|IOMUXC_GPR13_SATA_PHY_3_TXBOOST_0P00_DB
+			|IOMUXC_GPR13_SATA_PHY_2_TX_1P104V
+			|IOMUXC_GPR13_SATA_PHY_1_SLOW);
+
+	return 0;
+}
diff --git a/arch/arm/include/asm/arch-am33xx/clock.h b/arch/arm/include/asm/arch-am33xx/clock.h
index 519249e4af..7637457549 100644
--- a/arch/arm/include/asm/arch-am33xx/clock.h
+++ b/arch/arm/include/asm/arch-am33xx/clock.h
@@ -98,13 +98,12 @@ extern const struct dpll_regs dpll_mpu_regs;
 extern const struct dpll_regs dpll_core_regs;
 extern const struct dpll_regs dpll_per_regs;
 extern const struct dpll_regs dpll_ddr_regs;
-extern const struct dpll_params dpll_mpu;
-extern const struct dpll_params dpll_core;
-extern const struct dpll_params dpll_per;
-extern const struct dpll_params dpll_ddr;
 
 extern struct cm_wkuppll *const cmwkup;
 
+const struct dpll_params *get_dpll_mpu_params(void);
+const struct dpll_params *get_dpll_core_params(void);
+const struct dpll_params *get_dpll_per_params(void);
 const struct dpll_params *get_dpll_ddr_params(void);
 void do_setup_dpll(const struct dpll_regs *, const struct dpll_params *);
 void prcm_init(void);
diff --git a/arch/arm/include/asm/arch-am33xx/clocks_am33xx.h b/arch/arm/include/asm/arch-am33xx/clocks_am33xx.h
index 02ed5957e9..4c9352a2ed 100644
--- a/arch/arm/include/asm/arch-am33xx/clocks_am33xx.h
+++ b/arch/arm/include/asm/arch-am33xx/clocks_am33xx.h
@@ -28,6 +28,9 @@
 #define UART_CLK_RUNNING_MASK	0x1
 #define UART_SMART_IDLE_EN	(0x1 << 0x3)
 
+#define CM_DLL_CTRL_NO_OVERRIDE	0x0
+#define CM_DLL_READYST		0x4
+
 extern void enable_dmm_clocks(void);
 extern const struct dpll_params dpll_core_opp100;
 extern struct dpll_params dpll_mpu_opp100;
diff --git a/arch/arm/include/asm/arch-am33xx/cpu.h b/arch/arm/include/asm/arch-am33xx/cpu.h
index 52fa128af9..d9f0306b0a 100644
--- a/arch/arm/include/asm/arch-am33xx/cpu.h
+++ b/arch/arm/include/asm/arch-am33xx/cpu.h
@@ -78,58 +78,7 @@
 
 #ifndef __KERNEL_STRICT_NAMES
 #ifndef __ASSEMBLY__
-struct gpmc_cs {
-	u32 config1;		/* 0x00 */
-	u32 config2;		/* 0x04 */
-	u32 config3;		/* 0x08 */
-	u32 config4;		/* 0x0C */
-	u32 config5;		/* 0x10 */
-	u32 config6;		/* 0x14 */
-	u32 config7;		/* 0x18 */
-	u32 nand_cmd;		/* 0x1C */
-	u32 nand_adr;		/* 0x20 */
-	u32 nand_dat;		/* 0x24 */
-	u8 res[8];		/* blow up to 0x30 byte */
-};
-
-struct bch_res_0_3 {
-	u32 bch_result_x[4];
-};
 
-struct gpmc {
-	u8 res1[0x10];
-	u32 sysconfig;		/* 0x10 */
-	u8 res2[0x4];
-	u32 irqstatus;		/* 0x18 */
-	u32 irqenable;		/* 0x1C */
-	u8 res3[0x20];
-	u32 timeout_control;	/* 0x40 */
-	u8 res4[0xC];
-	u32 config;		/* 0x50 */
-	u32 status;		/* 0x54 */
-	u8 res5[0x8];		/* 0x58 */
-	struct gpmc_cs cs[8];	/* 0x60, 0x90, .. */
-	u8 res6[0x14];		/* 0x1E0 */
-	u32 ecc_config;		/* 0x1F4 */
-	u32 ecc_control;	/* 0x1F8 */
-	u32 ecc_size_config;	/* 0x1FC */
-	u32 ecc1_result;	/* 0x200 */
-	u32 ecc2_result;	/* 0x204 */
-	u32 ecc3_result;	/* 0x208 */
-	u32 ecc4_result;	/* 0x20C */
-	u32 ecc5_result;	/* 0x210 */
-	u32 ecc6_result;	/* 0x214 */
-	u32 ecc7_result;	/* 0x218 */
-	u32 ecc8_result;	/* 0x21C */
-	u32 ecc9_result;	/* 0x220 */
-	u8 res7[12];		/* 0x224 */
-	u32 testmomde_ctrl;	/* 0x230 */
-	u8 res8[12];		/* 0x234 */
-	struct bch_res_0_3 bch_result_0_3[2];	/* 0x240 */
-};
-
-/* Used for board specific gpmc initialization */
-extern struct gpmc *gpmc_cfg;
 
 #ifndef CONFIG_AM43XX
 /* Encapsulating core pll registers */
@@ -171,7 +120,8 @@ struct cm_wkuppll {
 	unsigned int resv11[1];
 	unsigned int wkup_uart0ctrl;	/* offset 0xB4 */
 	unsigned int wkup_i2c0ctrl;	/* offset 0xB8 */
-	unsigned int resv12[7];
+	unsigned int wkup_adctscctrl;	/* offset 0xBC */
+	unsigned int resv12[6];
 	unsigned int divm6dpllcore;	/* offset 0xD8 */
 };
 
@@ -221,7 +171,8 @@ struct cm_perpll {
 	unsigned int tpccclkctrl;	/* offset 0xBC */
 	unsigned int dcan0clkctrl;	/* offset 0xC0 */
 	unsigned int dcan1clkctrl;	/* offset 0xC4 */
-	unsigned int resv6[2];
+	unsigned int resv6;
+	unsigned int epwmss1clkctrl;	/* offset 0xCC */
 	unsigned int emiffwclkctrl;	/* offset 0xD0 */
 	unsigned int epwmss0clkctrl;	/* offset 0xD4 */
 	unsigned int epwmss2clkctrl;	/* offset 0xD8 */
@@ -237,6 +188,14 @@ struct cm_perpll {
 	unsigned int cpswclkstctrl;	/* offset 0x144 */
 	unsigned int lcdcclkstctrl;	/* offset 0x148 */
 };
+
+/* Encapsulating Display pll registers */
+struct cm_dpll {
+	unsigned int resv1[2];
+	unsigned int clktimer2clk;	/* offset 0x08 */
+	unsigned int resv2[10];
+	unsigned int clklcdcpixelclk;	/* offset 0x34 */
+};
 #else
 /* Encapsulating core pll registers */
 struct cm_wkuppll {
@@ -324,7 +283,9 @@ struct cm_perpll {
 	unsigned int mcasp1clkctrl;	/* offset 0x240 */
 	unsigned int resv11;
 	unsigned int mmc2clkctrl;	/* offset 0x248 */
-	unsigned int resv12[5];
+	unsigned int resv12[3];
+	unsigned int qspiclkctrl;       /* offset 0x258 */
+	unsigned int resv121;
 	unsigned int usb0clkctrl;	/* offset 0x260 */
 	unsigned int resv13[103];
 	unsigned int l4lsclkstctrl;	/* offset 0x400 */
@@ -343,7 +304,11 @@ struct cm_perpll {
 	unsigned int gpio2clkctrl;	/* offset 0x480 */
 	unsigned int resv20;
 	unsigned int gpio3clkctrl;	/* offset 0x488 */
-	unsigned int resv21[7];
+	unsigned int resv41;
+	unsigned int gpio4clkctrl;	/* offset 0x490 */
+	unsigned int resv42;
+	unsigned int gpio5clkctrl;	/* offset 0x498 */
+	unsigned int resv21[3];
 
 	unsigned int i2c1clkctrl;	/* offset 0x4A8 */
 	unsigned int resv22;
@@ -392,15 +357,17 @@ struct cm_perpll {
 	unsigned int resv40[7];
 	unsigned int cpgmac0clkctrl;	/* offset 0xB20 */
 };
-#endif /* CONFIG_AM43XX */
 
-/* Encapsulating Display pll registers */
+struct cm_device_inst {
+	unsigned int cm_clkout1_ctrl;
+	unsigned int cm_dll_ctrl;
+};
+
 struct cm_dpll {
-	unsigned int resv1[2];
-	unsigned int clktimer2clk;	/* offset 0x08 */
-	unsigned int resv2[10];
-	unsigned int clklcdcpixelclk;	/* offset 0x34 */
+	unsigned int resv1;
+	unsigned int clktimer2clk;	/* offset 0x04 */
 };
+#endif /* CONFIG_AM43XX */
 
 /* Control Module RTC registers */
 struct cm_rtc {
@@ -457,15 +424,6 @@ struct gptimer {
 	unsigned int tcar2;		/* offset 0x58 */
 };
 
-/* RTC Registers */
-struct rtc_regs {
-	unsigned int res[21];
-	unsigned int osc;		/* offset 0x54 */
-	unsigned int res2[5];
-	unsigned int kick0r;		/* offset 0x6c */
-	unsigned int kick1r;		/* offset 0x70 */
-};
-
 /* UART Registers */
 struct uart_sys {
 	unsigned int resv1[21];
@@ -484,6 +442,8 @@ struct ctrl_stat {
 	unsigned int statusreg;		/* ofset 0x40 */
 	unsigned int resv2[51];
 	unsigned int secure_emif_sdram_config;	/* offset 0x0110 */
+	unsigned int resv3[319];
+	unsigned int dev_attr;
 };
 
 /* AM33XX GPIO registers */
diff --git a/arch/arm/include/asm/arch-am33xx/ddr_defs.h b/arch/arm/include/asm/arch-am33xx/ddr_defs.h
index fe48b5fedc..4d899528f5 100644
--- a/arch/arm/include/asm/arch-am33xx/ddr_defs.h
+++ b/arch/arm/include/asm/arch-am33xx/ddr_defs.h
@@ -18,8 +18,11 @@
 #define VTP_CTRL_READY		(0x1 << 5)
 #define VTP_CTRL_ENABLE		(0x1 << 6)
 #define VTP_CTRL_START_EN	(0x1)
-#define PHY_DLL_LOCK_DIFF	0x0
+#ifdef CONFIG_AM43XX
+#define DDR_CKE_CTRL_NORMAL	0x3
+#else
 #define DDR_CKE_CTRL_NORMAL	0x1
+#endif
 #define PHY_EN_DYN_PWRDN	(0x1 << 20)
 
 /* Micron MT47H128M16RT-25E */
@@ -29,7 +32,6 @@
 #define MT47H128M16RT25E_EMIF_TIM3		0x0000033F
 #define MT47H128M16RT25E_EMIF_SDCFG		0x41805332
 #define MT47H128M16RT25E_EMIF_SDREF		0x0000081a
-#define MT47H128M16RT25E_DLL_LOCK_DIFF		0x0
 #define MT47H128M16RT25E_RATIO			0x80
 #define MT47H128M16RT25E_INVERT_CLKOUT		0x00
 #define MT47H128M16RT25E_RD_DQS			0x12
@@ -38,18 +40,16 @@
 #define MT47H128M16RT25E_PHY_GATELVL		0x00
 #define MT47H128M16RT25E_PHY_WR_DATA		0x40
 #define MT47H128M16RT25E_PHY_FIFO_WE		0x80
-#define MT47H128M16RT25E_PHY_RANK0_DELAY		0x1
 #define MT47H128M16RT25E_IOCTRL_VALUE		0x18B
 
 /* Micron MT41J128M16JT-125 */
-#define MT41J128MJT125_EMIF_READ_LATENCY	0x06
+#define MT41J128MJT125_EMIF_READ_LATENCY	0x100006
 #define MT41J128MJT125_EMIF_TIM1		0x0888A39B
 #define MT41J128MJT125_EMIF_TIM2		0x26337FDA
 #define MT41J128MJT125_EMIF_TIM3		0x501F830F
 #define MT41J128MJT125_EMIF_SDCFG		0x61C04AB2
 #define MT41J128MJT125_EMIF_SDREF		0x0000093B
 #define MT41J128MJT125_ZQ_CFG			0x50074BE4
-#define MT41J128MJT125_DLL_LOCK_DIFF		0x1
 #define MT41J128MJT125_RATIO			0x40
 #define MT41J128MJT125_INVERT_CLKOUT		0x1
 #define MT41J128MJT125_RD_DQS			0x3B
@@ -58,15 +58,36 @@
 #define MT41J128MJT125_PHY_FIFO_WE		0x100
 #define MT41J128MJT125_IOCTRL_VALUE		0x18B
 
+/* Micron MT41K128M16JT-187E */
+#define MT41K128MJT187E_EMIF_READ_LATENCY	0x06
+#define MT41K128MJT187E_EMIF_TIM1		0x0888B3DB
+#define MT41K128MJT187E_EMIF_TIM2		0x36337FDA
+#define MT41K128MJT187E_EMIF_TIM3		0x501F830F
+#define MT41K128MJT187E_EMIF_SDCFG		0x61C04AB2
+#define MT41K128MJT187E_EMIF_SDREF		0x0000093B
+#define MT41K128MJT187E_ZQ_CFG			0x50074BE4
+#define MT41K128MJT187E_RATIO			0x40
+#define MT41K128MJT187E_INVERT_CLKOUT		0x1
+#define MT41K128MJT187E_RD_DQS			0x3B
+#define MT41K128MJT187E_WR_DQS			0x85
+#define MT41K128MJT187E_PHY_WR_DATA		0xC1
+#define MT41K128MJT187E_PHY_FIFO_WE		0x100
+#define MT41K128MJT187E_IOCTRL_VALUE		0x18B
+
+/* Micron MT41J64M16JT-125 */
+#define MT41J64MJT125_EMIF_SDCFG		0x61C04A32
+
+/* Micron MT41J256M16JT-125 */
+#define MT41J256MJT125_EMIF_SDCFG		0x61C04B32
+
 /* Micron MT41J256M8HX-15E */
-#define MT41J256M8HX15E_EMIF_READ_LATENCY	0x06
+#define MT41J256M8HX15E_EMIF_READ_LATENCY	0x100006
 #define MT41J256M8HX15E_EMIF_TIM1		0x0888A39B
 #define MT41J256M8HX15E_EMIF_TIM2		0x26337FDA
 #define MT41J256M8HX15E_EMIF_TIM3		0x501F830F
 #define MT41J256M8HX15E_EMIF_SDCFG		0x61C04B32
 #define MT41J256M8HX15E_EMIF_SDREF		0x0000093B
 #define MT41J256M8HX15E_ZQ_CFG			0x50074BE4
-#define MT41J256M8HX15E_DLL_LOCK_DIFF		0x1
 #define MT41J256M8HX15E_RATIO			0x40
 #define MT41J256M8HX15E_INVERT_CLKOUT		0x1
 #define MT41J256M8HX15E_RD_DQS			0x3B
@@ -83,7 +104,6 @@
 #define MT41K256M16HA125E_EMIF_SDCFG		0x61C05332
 #define MT41K256M16HA125E_EMIF_SDREF		0xC30
 #define MT41K256M16HA125E_ZQ_CFG		0x50074BE4
-#define MT41K256M16HA125E_DLL_LOCK_DIFF		0x1
 #define MT41K256M16HA125E_RATIO			0x80
 #define MT41K256M16HA125E_INVERT_CLKOUT		0x0
 #define MT41K256M16HA125E_RD_DQS		0x38
@@ -93,14 +113,13 @@
 #define MT41K256M16HA125E_IOCTRL_VALUE		0x18B
 
 /* Micron MT41J512M8RH-125 on EVM v1.5 */
-#define MT41J512M8RH125_EMIF_READ_LATENCY	0x06
+#define MT41J512M8RH125_EMIF_READ_LATENCY	0x100006
 #define MT41J512M8RH125_EMIF_TIM1		0x0888A39B
 #define MT41J512M8RH125_EMIF_TIM2		0x26517FDA
 #define MT41J512M8RH125_EMIF_TIM3		0x501F84EF
 #define MT41J512M8RH125_EMIF_SDCFG		0x61C04BB2
 #define MT41J512M8RH125_EMIF_SDREF		0x0000093B
 #define MT41J512M8RH125_ZQ_CFG			0x50074BE4
-#define MT41J512M8RH125_DLL_LOCK_DIFF		0x1
 #define MT41J512M8RH125_RATIO			0x80
 #define MT41J512M8RH125_INVERT_CLKOUT		0x0
 #define MT41J512M8RH125_RD_DQS			0x3B
@@ -110,14 +129,13 @@
 #define MT41J512M8RH125_IOCTRL_VALUE		0x18B
 
 /* Samsung K4B2G1646E-BIH9 */
-#define K4B2G1646EBIH9_EMIF_READ_LATENCY	0x07
+#define K4B2G1646EBIH9_EMIF_READ_LATENCY	0x100007
 #define K4B2G1646EBIH9_EMIF_TIM1		0x0AAAE51B
 #define K4B2G1646EBIH9_EMIF_TIM2		0x2A1D7FDA
 #define K4B2G1646EBIH9_EMIF_TIM3		0x501F83FF
 #define K4B2G1646EBIH9_EMIF_SDCFG		0x61C052B2
 #define K4B2G1646EBIH9_EMIF_SDREF		0x00000C30
 #define K4B2G1646EBIH9_ZQ_CFG			0x50074BE4
-#define K4B2G1646EBIH9_DLL_LOCK_DIFF		0x1
 #define K4B2G1646EBIH9_RATIO			0x80
 #define K4B2G1646EBIH9_INVERT_CLKOUT		0x0
 #define K4B2G1646EBIH9_RD_DQS			0x35
@@ -126,6 +144,22 @@
 #define K4B2G1646EBIH9_PHY_WR_DATA		0x76
 #define K4B2G1646EBIH9_IOCTRL_VALUE		0x18B
 
+#define  LPDDR2_ADDRCTRL_IOCTRL_VALUE   0x294
+#define  LPDDR2_ADDRCTRL_WD0_IOCTRL_VALUE 0x00000000
+#define  LPDDR2_ADDRCTRL_WD1_IOCTRL_VALUE 0x00000000
+#define  LPDDR2_DATA0_IOCTRL_VALUE   0x20000294
+#define  LPDDR2_DATA1_IOCTRL_VALUE   0x20000294
+#define  LPDDR2_DATA2_IOCTRL_VALUE   0x20000294
+#define  LPDDR2_DATA3_IOCTRL_VALUE   0x20000294
+
+#define  DDR3_ADDRCTRL_WD0_IOCTRL_VALUE 0x00000000
+#define  DDR3_ADDRCTRL_WD1_IOCTRL_VALUE 0x00000000
+#define  DDR3_ADDRCTRL_IOCTRL_VALUE   0x84
+#define  DDR3_DATA0_IOCTRL_VALUE   0x84
+#define  DDR3_DATA1_IOCTRL_VALUE   0x84
+#define  DDR3_DATA2_IOCTRL_VALUE   0x84
+#define  DDR3_DATA3_IOCTRL_VALUE   0x84
+
 /**
  * Configure DMM
  */
@@ -135,6 +169,7 @@ void config_dmm(const struct dmm_lisa_map_regs *regs);
  * Configure SDRAM
  */
 void config_sdram(const struct emif_regs *regs, int nr);
+void config_sdram_emif4d5(const struct emif_regs *regs, int nr);
 
 /**
  * Set SDRAM timings
@@ -149,18 +184,15 @@ void config_ddr_phy(const struct emif_regs *regs, int nr);
 struct ddr_cmd_regs {
 	unsigned int resv0[7];
 	unsigned int cm0csratio;	/* offset 0x01C */
-	unsigned int resv1[2];
-	unsigned int cm0dldiff;		/* offset 0x028 */
+	unsigned int resv1[3];
 	unsigned int cm0iclkout;	/* offset 0x02C */
 	unsigned int resv2[8];
 	unsigned int cm1csratio;	/* offset 0x050 */
-	unsigned int resv3[2];
-	unsigned int cm1dldiff;		/* offset 0x05C */
+	unsigned int resv3[3];
 	unsigned int cm1iclkout;	/* offset 0x060 */
 	unsigned int resv4[8];
 	unsigned int cm2csratio;	/* offset 0x084 */
-	unsigned int resv5[2];
-	unsigned int cm2dldiff;		/* offset 0x090 */
+	unsigned int resv5[3];
 	unsigned int cm2iclkout;	/* offset 0x094 */
 	unsigned int resv6[3];
 };
@@ -197,24 +229,21 @@ struct ddr_regs {
 	unsigned int cm0configclk;	/* offset 0x010 */
 	unsigned int resv1[2];
 	unsigned int cm0csratio;	/* offset 0x01C */
-	unsigned int resv2[2];
-	unsigned int cm0dldiff;		/* offset 0x028 */
+	unsigned int resv2[3];
 	unsigned int cm0iclkout;	/* offset 0x02C */
 	unsigned int resv3[4];
 	unsigned int cm1config;		/* offset 0x040 */
 	unsigned int cm1configclk;	/* offset 0x044 */
 	unsigned int resv4[2];
 	unsigned int cm1csratio;	/* offset 0x050 */
-	unsigned int resv5[2];
-	unsigned int cm1dldiff;		/* offset 0x05C */
+	unsigned int resv5[3];
 	unsigned int cm1iclkout;	/* offset 0x060 */
 	unsigned int resv6[4];
 	unsigned int cm2config;		/* offset 0x074 */
 	unsigned int cm2configclk;	/* offset 0x078 */
 	unsigned int resv7[2];
 	unsigned int cm2csratio;	/* offset 0x084 */
-	unsigned int resv8[2];
-	unsigned int cm2dldiff;		/* offset 0x090 */
+	unsigned int resv8[3];
 	unsigned int cm2iclkout;	/* offset 0x094 */
 	unsigned int resv9[12];
 	unsigned int dt0rdsratio0;	/* offset 0x0C8 */
@@ -243,17 +272,14 @@ struct cmd_control {
 	unsigned long cmd0csratio;
 	unsigned long cmd0csforce;
 	unsigned long cmd0csdelay;
-	unsigned long cmd0dldiff;
 	unsigned long cmd0iclkout;
 	unsigned long cmd1csratio;
 	unsigned long cmd1csforce;
 	unsigned long cmd1csdelay;
-	unsigned long cmd1dldiff;
 	unsigned long cmd1iclkout;
 	unsigned long cmd2csratio;
 	unsigned long cmd2csforce;
 	unsigned long cmd2csdelay;
-	unsigned long cmd2dldiff;
 	unsigned long cmd2iclkout;
 };
 
@@ -267,8 +293,6 @@ struct ddr_data {
 	unsigned long datagiratio0;
 	unsigned long datafwsratio0;
 	unsigned long datawrsratio0;
-	unsigned long datauserank0delay;
-	unsigned long datadldiff0;
 };
 
 /**
@@ -291,12 +315,27 @@ struct ddr_cmdtctrl {
 	unsigned int resv2[12];
 	unsigned int dt0ioctl;
 	unsigned int dt1ioctl;
+	unsigned int dt2ioctrl;
+	unsigned int dt3ioctrl;
+	unsigned int resv3[4];
+	unsigned int emif_sdram_config_ext;
+};
+
+struct ctrl_ioregs {
+	unsigned int cm0ioctl;
+	unsigned int cm1ioctl;
+	unsigned int cm2ioctl;
+	unsigned int dt0ioctl;
+	unsigned int dt1ioctl;
+	unsigned int dt2ioctrl;
+	unsigned int dt3ioctrl;
+	unsigned int emif_sdram_config_ext;
 };
 
 /**
  * Configure DDR io control registers
  */
-void config_io_ctrl(unsigned long val);
+void config_io_ctrl(const struct ctrl_ioregs *ioregs);
 
 struct ddr_ctrl {
 	unsigned int ddrioctrl;
@@ -304,8 +343,9 @@ struct ddr_ctrl {
 	unsigned int ddrckectrl;
 };
 
-void config_ddr(unsigned int pll, unsigned int ioctrl,
+void config_ddr(unsigned int pll, const struct ctrl_ioregs *ioregs,
 		const struct ddr_data *data, const struct cmd_control *ctrl,
 		const struct emif_regs *regs, int nr);
+void emif_get_ext_phy_ctrl_const_regs(const u32 **regs, u32 *size);
 
 #endif  /* _DDR_DEFS_H */
diff --git a/arch/arm/include/asm/arch-am33xx/gpio.h b/arch/arm/include/asm/arch-am33xx/gpio.h
index 13a047fd72..220603db5a 100644
--- a/arch/arm/include/asm/arch-am33xx/gpio.h
+++ b/arch/arm/include/asm/arch-am33xx/gpio.h
@@ -12,5 +12,17 @@
 #define AM33XX_GPIO1_BASE       0x4804C000
 #define AM33XX_GPIO2_BASE       0x481AC000
 #define AM33XX_GPIO3_BASE       0x481AE000
+#define AM33XX_GPIO4_BASE	0x48320000
+#define AM33XX_GPIO5_BASE	0x48322000
 
+/* GPIO CTRL register */
+#define GPIO_CTRL_DISABLEMODULE_SHIFT	0
+#define GPIO_CTRL_DISABLEMODULE_MASK	(1 << 0)
+#define GPIO_CTRL_ENABLEMODULE		GPIO_CTRL_DISABLEMODULE_MASK
+
+/* GPIO OUTPUT ENABLE register */
+#define GPIO_OE_ENABLE(x)		(1 << x)
+
+/* GPIO SETDATAOUT register */
+#define GPIO_SETDATAOUT(x)		(1 << x)
 #endif /* _GPIO_AM33xx_H */
diff --git a/arch/arm/include/asm/arch-am33xx/hardware.h b/arch/arm/include/asm/arch-am33xx/hardware.h
index ee5fce0da1..dd950e5ac4 100644
--- a/arch/arm/include/asm/arch-am33xx/hardware.h
+++ b/arch/arm/include/asm/arch-am33xx/hardware.h
@@ -48,13 +48,6 @@
 #define EMIF4_0_CFG_BASE		0x4C000000
 #define EMIF4_1_CFG_BASE		0x4D000000
 
-/* PLL related registers */
-#define CM_DPLL				0x44E00500
-#define CM_DEVICE			0x44E00700
-#define CM_RTC				0x44E00800
-#define CM_CEFUSE			0x44E00A00
-#define PRM_DEVICE			0x44E00F00
-
 /* DDR Base address */
 #define DDR_CTRL_ADDR			0x44E10E04
 #define DDR_CONTROL_BASE_ADDR		0x44E11404
diff --git a/arch/arm/include/asm/arch-am33xx/hardware_am33xx.h b/arch/arm/include/asm/arch-am33xx/hardware_am33xx.h
index e4231c81ad..c67a0801a9 100644
--- a/arch/arm/include/asm/arch-am33xx/hardware_am33xx.h
+++ b/arch/arm/include/asm/arch-am33xx/hardware_am33xx.h
@@ -30,6 +30,8 @@
 #define PRCM_BASE			0x44E00000
 #define CM_PER				0x44E00000
 #define CM_WKUP				0x44E00400
+#define CM_DPLL				0x44E00500
+#define CM_RTC				0x44E00800
 
 #define PRM_RSTCTRL			(PRCM_BASE + 0x0F00)
 #define PRM_RSTST			(PRM_RSTCTRL + 8)
diff --git a/arch/arm/include/asm/arch-am33xx/hardware_am43xx.h b/arch/arm/include/asm/arch-am33xx/hardware_am43xx.h
index 303c594d22..15399dcc74 100644
--- a/arch/arm/include/asm/arch-am33xx/hardware_am43xx.h
+++ b/arch/arm/include/asm/arch-am33xx/hardware_am43xx.h
@@ -30,6 +30,8 @@
 #define PRCM_BASE			0x44DF0000
 #define	CM_WKUP				0x44DF2800
 #define	CM_PER				0x44DF8800
+#define CM_DPLL				0x44DF4200
+#define CM_RTC				0x44DF8500
 
 #define PRM_RSTCTRL			(PRCM_BASE + 0x4000)
 #define PRM_RSTST			(PRM_RSTCTRL + 4)
@@ -51,4 +53,28 @@
 /* RTC base address */
 #define RTC_BASE			0x44E3E000
 
+/* USB Clock Control */
+#define PRM_PER_USB_OTG_SS0_CLKCTRL (CM_PER + 0x260)
+#define PRM_PER_USB_OTG_SS1_CLKCTRL (CM_PER + 0x268)
+#define USBOTGSSX_CLKCTRL_MODULE_EN	(1 << 1)
+#define USBOTGSSX_CLKCTRL_OPTFCLKEN_REFCLK960 (1 << 8)
+
+#define PRM_PER_USBPHYOCP2SCP0_CLKCTRL (CM_PER + 0x5b8)
+#define PRM_PER_USBPHYOCP2SCP1_CLKCTRL (CM_PER + 0x5c0)
+#define USBPHYOCPSCP_MODULE_EN	(1 << 1)
+#define CM_DEVICE_INST			0x44df4100
+
+/* Control status register */
+#define CTRL_CRYSTAL_FREQ_SRC_MASK		(1 << 31)
+#define CTRL_CRYSTAL_FREQ_SRC_SHIFT		31
+#define CTRL_CRYSTAL_FREQ_SELECTION_MASK	(0x3 << 29)
+#define CTRL_CRYSTAL_FREQ_SELECTION_SHIFT	29
+#define CTRL_SYSBOOT_15_14_MASK			(0x3 << 22)
+#define CTRL_SYSBOOT_15_14_SHIFT		22
+
+#define CTRL_CRYSTAL_FREQ_SRC_SYSBOOT		0x0
+#define CTRL_CRYSTAL_FREQ_SRC_EFUSE		0x1
+
+#define NUM_CRYSTAL_FREQ			0x4
+
 #endif /* __AM43XX_HARDWARE_AM43XX_H */
diff --git a/arch/arm/include/asm/arch-am33xx/i2c.h b/arch/arm/include/asm/arch-am33xx/i2c.h
index 8bfa53f41b..8642c8f872 100644
--- a/arch/arm/include/asm/arch-am33xx/i2c.h
+++ b/arch/arm/include/asm/arch-am33xx/i2c.h
@@ -4,8 +4,8 @@
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */
-#ifndef _I2C_H_
-#define _I2C_H_
+#ifndef _I2C_AM33XX_H_
+#define _I2C_AM33XX_H_
 
 #define  I2C_BASE1		0x44E0B000
 #define  I2C_BASE2		0x4802A000
@@ -62,4 +62,4 @@ struct i2c {
 #define I2C_IP_CLK			48000000
 #define I2C_INTERNAL_SAMPLING_CLK	12000000
 
-#endif /* _I2C_H_ */
+#endif /* _I2C_AM33XX_H_ */
diff --git a/arch/arm/include/asm/arch-am33xx/mem.h b/arch/arm/include/asm/arch-am33xx/mem.h
index 983ea28dc0..e7e8c58b00 100644
--- a/arch/arm/include/asm/arch-am33xx/mem.h
+++ b/arch/arm/include/asm/arch-am33xx/mem.h
@@ -68,9 +68,4 @@
 #define PISMO2_NAND_CS0		7
 #define PISMO2_NAND_CS1		8
 
-/* make it readable for the gpmc_init */
-#define PISMO1_NOR_BASE	FLASH_BASE
-#define PISMO1_NAND_BASE	CONFIG_SYS_NAND_BASE
-#define PISMO1_NAND_SIZE	GPMC_SIZE_256M
-
 #endif /* endif _MEM_H_ */
diff --git a/arch/arm/include/asm/arch-am33xx/mux_am43xx.h b/arch/arm/include/asm/arch-am33xx/mux_am43xx.h
index 0206912d54..98fc2b50da 100644
--- a/arch/arm/include/asm/arch-am33xx/mux_am43xx.h
+++ b/arch/arm/include/asm/arch-am33xx/mux_am43xx.h
@@ -137,6 +137,51 @@ struct pad_signals {
 	int mcasp0_fsr;
 	int mcasp0_axr1;
 	int mcasp0_ahclkx;
+	int xdma_event_intr0;
+	int xdma_event_intr1;
+	int nresetin_out;
+	int porz;
+	int nnmi;
+	int osc0_in;
+	int osc0_out;
+	int rsvd1;
+	int tms;
+	int tdi;
+	int tdo;
+	int tck;
+	int ntrst;
+	int emu0;
+	int emu1;
+	int osc1_in;
+	int osc1_out;
+	int pmic_power_en;
+	int rtc_porz;
+	int rsvd2;
+	int ext_wakeup;
+	int enz_kaldo_1p8v;
+	int usb0_dm;
+	int usb0_dp;
+	int usb0_ce;
+	int usb0_id;
+	int usb0_vbus;
+	int usb0_drvvbus;
+	int usb1_dm;
+	int usb1_dp;
+	int usb1_ce;
+	int usb1_id;
+	int usb1_vbus;
+	int usb1_drvvbus;
+	int ddr_resetn;
+	int ddr_csn0;
+	int ddr_cke;
+	int ddr_ck;
+	int ddr_nck;
+	int ddr_casn;
+	int ddr_rasn;
+	int ddr_wen;
+	int ddr_ba0;
+	int ddr_ba1;
+	int ddr_ba2;
 };
 
 #endif /* _MUX_AM43XX_H_ */
diff --git a/arch/arm/include/asm/arch-am33xx/omap.h b/arch/arm/include/asm/arch-am33xx/omap.h
index 225072186d..0855d16ce5 100644
--- a/arch/arm/include/asm/arch-am33xx/omap.h
+++ b/arch/arm/include/asm/arch-am33xx/omap.h
@@ -26,6 +26,9 @@
 #elif defined(CONFIG_AM43XX)
 #define NON_SECURE_SRAM_START	0x402F0400
 #define NON_SECURE_SRAM_END	0x40340000
-#define SRAM_SCRATCH_SPACE_ADDR	0x4033C000
+#define SRAM_SCRATCH_SPACE_ADDR	0x40337C00
+#define AM4372_BOARD_NAME_START	SRAM_SCRATCH_SPACE_ADDR
+#define AM4372_BOARD_NAME_END	SRAM_SCRATCH_SPACE_ADDR + 0xC
+#define QSPI_BASE              0x47900000
 #endif
 #endif
diff --git a/arch/arm/include/asm/arch-am33xx/omap_gpmc.h b/arch/arm/include/asm/arch-am33xx/omap_gpmc.h
deleted file mode 100644
index 00ad1d0672..0000000000
--- a/arch/arm/include/asm/arch-am33xx/omap_gpmc.h
+++ /dev/null
@@ -1,48 +0,0 @@
-/*
- * (C) Copyright 2004-2008 Texas Instruments, <www.ti.com>
- * Rohit Choraria <rohitkc@ti.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-#ifndef __ASM_ARCH_OMAP_GPMC_H
-#define __ASM_ARCH_OMAP_GPMC_H
-
-/* These GPMC_NAND_HW_BCHx_ECC_LAYOUT defines are based on AM33xx ELM */
-#define GPMC_NAND_HW_BCH4_ECC_LAYOUT {\
-	.eccbytes = 32,\
-	.eccpos = {2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,\
-				16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27,\
-				28, 29, 30, 31, 32, 33},\
-	.oobfree = {\
-		{.offset = 34,\
-		 .length = 30 } } \
-}
-
-#define GPMC_NAND_HW_BCH8_ECC_LAYOUT {\
-	.eccbytes = 56,\
-	.eccpos = {2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,\
-				16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27,\
-				28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39,\
-				40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51,\
-				52, 53, 54, 55, 56, 57},\
-	.oobfree = {\
-		{.offset = 58,\
-		 .length = 6 } } \
-}
-
-#define GPMC_NAND_HW_BCH16_ECC_LAYOUT {\
-	.eccbytes = 104,\
-	.eccpos = {2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,\
-				16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27,\
-				28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39,\
-				40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51,\
-				52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63,\
-				64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75,\
-				76, 77, 78, 79, 80, 81, 82, 83, 84, 85, 86, 87,\
-				88, 89, 90, 91, 92, 93, 94, 95, 96, 97, 98, 99,\
-				100, 101, 102, 103, 104, 105},\
-	.oobfree = {\
-		{.offset = 106,\
-		 .length = 8 } } \
-}
-#endif /* __ASM_ARCH_OMAP_GPMC_H */
diff --git a/arch/arm/include/asm/arch-am33xx/spl.h b/arch/arm/include/asm/arch-am33xx/spl.h
index 95de9aa235..8543f4399c 100644
--- a/arch/arm/include/asm/arch-am33xx/spl.h
+++ b/arch/arm/include/asm/arch-am33xx/spl.h
@@ -5,7 +5,7 @@
  * SPDX-License-Identifier:	GPL-2.0+
  */
 #ifndef	_ASM_ARCH_SPL_H_
-#define	_ASM_SPL_H_
+#define	_ASM_ARCH_SPL_H_
 
 #if defined(CONFIG_TI816X)
 #define BOOT_DEVICE_XIP		2
@@ -13,11 +13,19 @@
 #define BOOT_DEVICE_MMC1	6
 #define BOOT_DEVICE_MMC2	5
 #define BOOT_DEVICE_UART	0x43
-#define BOOT_DEVICE_MMC2_2	0xFF
+#elif defined(CONFIG_AM43XX)
+#define BOOT_DEVICE_NOR		1
+#define BOOT_DEVICE_NAND	5
+#define BOOT_DEVICE_MMC1	7
+#define BOOT_DEVICE_MMC2	8
+#define BOOT_DEVICE_SPI		10
+#define BOOT_DEVICE_USB     13
+#define BOOT_DEVICE_UART	65
+#define BOOT_DEVICE_CPGMAC	71
 #else
 #define BOOT_DEVICE_XIP       	2
 #define BOOT_DEVICE_NAND	5
-#if defined(CONFIG_AM33XX) || defined(CONFIG_AM43XX)
+#if defined(CONFIG_AM33XX)
 #define BOOT_DEVICE_MMC1	8
 #define BOOT_DEVICE_MMC2	9	/* eMMC or daughter card */
 #elif defined(CONFIG_TI814X)
@@ -28,12 +36,19 @@
 #define BOOT_DEVICE_UART	65
 #define BOOT_DEVICE_USBETH	68
 #define BOOT_DEVICE_CPGMAC	70
-#define BOOT_DEVICE_MMC2_2      0xFF
 #endif
+#define BOOT_DEVICE_MMC2_2      0xFF
 
-#if defined(CONFIG_AM33XX) || defined(CONFIG_AM43XX)
-#define MMC_BOOT_DEVICES_START	BOOT_DEVICE_MMC1
-#define MMC_BOOT_DEVICES_END	BOOT_DEVICE_MMC2
+#if defined(CONFIG_AM33XX)
+#define MMC_BOOT_DEVICES_START BOOT_DEVICE_MMC1
+#define MMC_BOOT_DEVICES_END   BOOT_DEVICE_MMC2
+#elif defined(CONFIG_AM43XX)
+#define MMC_BOOT_DEVICES_START BOOT_DEVICE_MMC1
+#ifdef CONFIG_SPL_USB_SUPPORT
+#define MMC_BOOT_DEVICES_END   BOOT_DEVICE_USB
+#else
+#define MMC_BOOT_DEVICES_END   BOOT_DEVICE_MMC2
+#endif
 #elif defined(CONFIG_TI81XX)
 #define MMC_BOOT_DEVICES_START	BOOT_DEVICE_MMC2
 #define MMC_BOOT_DEVICES_END	BOOT_DEVICE_MMC1
diff --git a/arch/arm/include/asm/arch-am33xx/sys_proto.h b/arch/arm/include/asm/arch-am33xx/sys_proto.h
index 87b7d367b9..91ff2ad0e4 100644
--- a/arch/arm/include/asm/arch-am33xx/sys_proto.h
+++ b/arch/arm/include/asm/arch-am33xx/sys_proto.h
@@ -10,6 +10,7 @@
 
 #ifndef _SYS_PROTO_H_
 #define _SYS_PROTO_H_
+#include <linux/mtd/omap_gpmc.h>
 #include <asm/arch/cpu.h>
 
 #define BOARD_REV_ID	0x0
@@ -17,10 +18,6 @@
 u32 get_cpu_rev(void);
 u32 get_sysboot_value(void);
 
-#ifdef CONFIG_DISPLAY_CPUINFO
-int print_cpuinfo(void);
-#endif
-
 extern struct ctrl_stat *cstat;
 u32 get_device_type(void);
 void save_omap_boot_params(void);
diff --git a/arch/arm/include/asm/arch-at91/at91_common.h b/arch/arm/include/asm/arch-at91/at91_common.h
index abcb97d107..59e2f4391c 100644
--- a/arch/arm/include/asm/arch-at91/at91_common.h
+++ b/arch/arm/include/asm/arch-at91/at91_common.h
@@ -22,5 +22,10 @@ void at91_spi1_hw_init(unsigned long cs_mask);
 void at91_udp_hw_init(void);
 void at91_uhp_hw_init(void);
 void at91_lcd_hw_init(void);
+void at91_plla_init(u32 pllar);
+void at91_mck_init(u32 mckr);
+void at91_pmc_init(void);
+void mem_init(void);
+void at91_phy_reset(void);
 
 #endif /* AT91_COMMON_H */
diff --git a/arch/arm/include/asm/arch-at91/at91_pio.h b/arch/arm/include/asm/arch-at91/at91_pio.h
index 676f024e47..50464ffe8e 100644
--- a/arch/arm/include/asm/arch-at91/at91_pio.h
+++ b/arch/arm/include/asm/arch-at91/at91_pio.h
@@ -151,37 +151,4 @@ int at91_get_pio_value(unsigned port, unsigned pin);
 #define	AT91_PIO_PORTD		0x3
 #define	AT91_PIO_PORTE		0x4
 
-#ifdef CONFIG_AT91_LEGACY
-
-#define PIO_PER		0x00	/* Enable Register */
-#define PIO_PDR		0x04	/* Disable Register */
-#define PIO_PSR		0x08	/* Status Register */
-#define PIO_OER		0x10	/* Output Enable Register */
-#define PIO_ODR		0x14	/* Output Disable Register */
-#define PIO_OSR		0x18	/* Output Status Register */
-#define PIO_IFER	0x20	/* Glitch Input Filter Enable */
-#define PIO_IFDR	0x24	/* Glitch Input Filter Disable */
-#define PIO_IFSR	0x28	/* Glitch Input Filter Status */
-#define PIO_SODR	0x30	/* Set Output Data Register */
-#define PIO_CODR	0x34	/* Clear Output Data Register */
-#define PIO_ODSR	0x38	/* Output Data Status Register */
-#define PIO_PDSR	0x3c	/* Pin Data Status Register */
-#define PIO_IER		0x40	/* Interrupt Enable Register */
-#define PIO_IDR		0x44	/* Interrupt Disable Register */
-#define PIO_IMR		0x48	/* Interrupt Mask Register */
-#define PIO_ISR		0x4c	/* Interrupt Status Register */
-#define PIO_MDER	0x50	/* Multi-driver Enable Register */
-#define PIO_MDDR	0x54	/* Multi-driver Disable Register */
-#define PIO_MDSR	0x58	/* Multi-driver Status Register */
-#define PIO_PUDR	0x60	/* Pull-up Disable Register */
-#define PIO_PUER	0x64	/* Pull-up Enable Register */
-#define PIO_PUSR	0x68	/* Pull-up Status Register */
-#define PIO_ASR		0x70	/* Peripheral A Select Register */
-#define PIO_BSR		0x74	/* Peripheral B Select Register */
-#define PIO_ABSR	0x78	/* AB Status Register */
-#define PIO_OWER	0xa0	/* Output Write Enable Register */
-#define PIO_OWDR	0xa4	/* Output Write Disable Register */
-#define PIO_OWSR	0xa8	/* Output Write Status Register */
-#endif
-
 #endif
diff --git a/arch/arm/include/asm/arch-at91/at91_pit.h b/arch/arm/include/asm/arch-at91/at91_pit.h
index d314b062bf..56724f15e7 100644
--- a/arch/arm/include/asm/arch-at91/at91_pit.h
+++ b/arch/arm/include/asm/arch-at91/at91_pit.h
@@ -25,20 +25,4 @@ typedef struct at91_pit {
 #define		AT91_PIT_MR_PIV_MASK(x)	(x & 0x000fffff)
 #define		AT91_PIT_MR_PIV(x)	(x & AT91_PIT_MR_PIV_MASK)
 
-#ifdef CONFIG_AT91_LEGACY
-
-#define AT91_PIT_MR		(AT91_PIT + 0x00)	/* Mode Register */
-#define		AT91_PIT_PITIEN		(1 << 25)		/* Timer Interrupt Enable */
-#define		AT91_PIT_PITEN		(1 << 24)		/* Timer Enabled */
-#define		AT91_PIT_PIV		(0xfffff)		/* Periodic Interval Value */
-
-#define AT91_PIT_SR		(AT91_PIT + 0x04)	/* Status Register */
-#define		AT91_PIT_PITS		(1 << 0)		/* Timer Status */
-
-#define AT91_PIT_PIVR		(AT91_PIT + 0x08)	/* Periodic Interval Value Register */
-#define AT91_PIT_PIIR		(AT91_PIT + 0x0c)	/* Periodic Interval Image Register */
-#define		AT91_PIT_PICNT		(0xfff << 20)		/* Interval Counter */
-#define		AT91_PIT_CPIV		(0xfffff)		/* Inverval Value */
-
-#endif /* CONFIG_AT91_LEGACY */
 #endif
diff --git a/arch/arm/include/asm/arch-at91/at91_pmc.h b/arch/arm/include/asm/arch-at91/at91_pmc.h
index 003920cd84..4535608434 100644
--- a/arch/arm/include/asm/arch-at91/at91_pmc.h
+++ b/arch/arm/include/asm/arch-at91/at91_pmc.h
@@ -14,13 +14,15 @@
 #ifndef AT91_PMC_H
 #define AT91_PMC_H
 
+#ifdef __ASSEMBLY__
+
 #define	AT91_ASM_PMC_MOR	(ATMEL_BASE_PMC + 0x20)
 #define	AT91_ASM_PMC_PLLAR	(ATMEL_BASE_PMC + 0x28)
 #define	AT91_ASM_PMC_PLLBR	(ATMEL_BASE_PMC + 0x2c)
 #define AT91_ASM_PMC_MCKR	(ATMEL_BASE_PMC + 0x30)
 #define AT91_ASM_PMC_SR		(ATMEL_BASE_PMC + 0x68)
 
-#ifndef __ASSEMBLY__
+#else
 
 #include <asm/types.h>
 
@@ -73,7 +75,11 @@ typedef struct at91_pmc {
 #define AT91_PMC_PLLXR_DIV(x)		(x & 0xFF)
 #define AT91_PMC_PLLXR_PLLCOUNT(x)	((x & 0x3F) << 8)
 #define AT91_PMC_PLLXR_OUT(x)		((x & 0x03) << 14)
+#ifdef CONFIG_SAMA5D3
+#define AT91_PMC_PLLXR_MUL(x)		((x & 0x7F) << 18)
+#else
 #define AT91_PMC_PLLXR_MUL(x)		((x & 0x7FF) << 16)
+#endif
 #define AT91_PMC_PLLAR_29		0x20000000
 #define AT91_PMC_PLLBR_USBDIV_1		0x00000000
 #define AT91_PMC_PLLBR_USBDIV_2		0x10000000
@@ -124,8 +130,8 @@ typedef struct at91_pmc {
 #define AT91_PMC_MCKR_MDIV_MASK		0x00000300
 #endif
 
-#define AT91_PMC_MCKR_PLLADIV_1		0x00001000
-#define AT91_PMC_MCKR_PLLADIV_2		0x00002000
+#define AT91_PMC_MCKR_PLLADIV_1		0x00000000
+#define AT91_PMC_MCKR_PLLADIV_2		0x00001000
 
 #define AT91_PMC_IXR_MOSCS		0x00000001
 #define AT91_PMC_IXR_LOCKA		0x00000002
@@ -137,13 +143,6 @@ typedef struct at91_pmc {
 #define AT91_PMC_IXR_PCKRDY2		0x00000400
 #define AT91_PMC_IXR_PCKRDY3		0x00000800
 
-#ifdef CONFIG_AT91_LEGACY
-#define	AT91_PMC_SCER		(AT91_PMC + 0x00)	/* System Clock Enable Register */
-#define	AT91_PMC_SCDR		(AT91_PMC + 0x04)	/* System Clock Disable Register */
-
-#define	AT91_PMC_SCSR		(AT91_PMC + 0x08)	/* System Clock Status Register */
-#endif
-
 #define		AT91_PMC_PCK		(1 <<  0)		/* Processor Clock */
 #define		AT91RM9200_PMC_UDP	(1 <<  1)		/* USB Devcice Port Clock [AT91RM9200 only] */
 #define		AT91RM9200_PMC_MCKUDP	(1 <<  2)		/* USB Device Port Master Clock Automatic Disable on Suspend [AT91RM9200 only] */
@@ -159,34 +158,18 @@ typedef struct at91_pmc {
 #define		AT91_PMC_HCK0		(1 << 16)		/* AHB Clock (USB host) [AT91SAM9261 only] */
 #define		AT91_PMC_HCK1		(1 << 17)		/* AHB Clock (LCD) [AT91SAM9261 only] */
 
-#ifdef CONFIG_AT91_LEGACY
-#define	AT91_PMC_PCER		(AT91_PMC + 0x10)	/* Peripheral Clock Enable Register */
-#define	AT91_PMC_PCDR		(AT91_PMC + 0x14)	/* Peripheral Clock Disable Register */
-#define	AT91_PMC_PCSR		(AT91_PMC + 0x18)	/* Peripheral Clock Status Register */
-
-#define	AT91_CKGR_UCKR		(AT91_PMC + 0x1C)	/* UTMI Clock Register [SAM9RL, CAP9] */
-#endif
-
 #define		AT91_PMC_UPLLEN		(1   << 16)		/* UTMI PLL Enable */
 #define		AT91_PMC_UPLLCOUNT	(0xf << 20)		/* UTMI PLL Start-up Time */
 #define		AT91_PMC_BIASEN		(1   << 24)		/* UTMI BIAS Enable */
 #define		AT91_PMC_BIASCOUNT	(0xf << 28)		/* UTMI PLL Start-up Time */
 
-#ifdef CONFIG_AT91_LEGACY
-#define	AT91_CKGR_MOR		(AT91_PMC + 0x20)	/* Main Oscillator Register [not on SAM9RL] */
-#endif
 #define		AT91_PMC_MOSCEN		(1    << 0)		/* Main Oscillator Enable */
 #define		AT91_PMC_OSCBYPASS	(1    << 1)		/* Oscillator Bypass [SAM9x, CAP9] */
 #define		AT91_PMC_OSCOUNT	(0xff << 8)		/* Main Oscillator Start-up Time */
-#ifdef CONFIG_AT91_LEGACY
-#define	AT91_CKGR_MCFR		(AT91_PMC + 0x24)	/* Main Clock Frequency Register */
-#endif
+
 #define		AT91_PMC_MAINF		(0xffff <<  0)		/* Main Clock Frequency */
 #define		AT91_PMC_MAINRDY	(1	<< 16)		/* Main Clock Ready */
-#ifdef CONFIG_AT91_LEGACY
-#define	AT91_CKGR_PLLAR		(AT91_PMC + 0x28)	/* PLL A Register */
-#define	AT91_CKGR_PLLBR		(AT91_PMC + 0x2c)	/* PLL B Register */
-#endif
+
 #define		AT91_PMC_DIV		(0xff  <<  0)		/* Divider */
 #define		AT91_PMC_PLLCOUNT	(0x3f  <<  8)		/* PLL Counter */
 #define		AT91_PMC_OUT		(3     << 14)		/* PLL Clock Frequency Range */
@@ -198,9 +181,6 @@ typedef struct at91_pmc {
 #define		AT91_PMC_USB96M		(1     << 28)		/* Divider by 2 Enable (PLLB only) */
 #define		AT91_PMC_PLLA_WR_ERRATA	(1     << 29)		/* Bit 29 must always be set to 1 when programming the CKGR_PLLAR register */
 
-#ifdef CONFIG_AT91_LEGACY
-#define	AT91_PMC_MCKR		(AT91_PMC + 0x30)	/* Master Clock Register */
-#endif
 #define		AT91_PMC_CSS		(3 <<  0)		/* Master Clock Selection */
 #define			AT91_PMC_CSS_SLOW		(0 << 0)
 #define			AT91_PMC_CSS_MAIN		(1 << 0)
@@ -228,21 +208,13 @@ typedef struct at91_pmc {
 #define			AT91_PMC_PDIV_1			(0 << 12)
 #define			AT91_PMC_PDIV_2			(1 << 12)
 
-#ifdef CONFIG_AT91_LEGACY
-#define		AT91_PMC_USB			(AT91_PMC + 0x38)	/* USB Clock Register */
-#endif
 #define		AT91_PMC_USBS_USB_PLLA		(0x0)		/* USB Clock Input is PLLA */
 #define		AT91_PMC_USBS_USB_UPLL		(0x1)		/* USB Clock Input is UPLL */
+#define		AT91_PMC_USBS_USB_PLLB		(0x1)		/* USB Clock Input is PLLB, AT91SAM9N12 only */
+#define		AT91_PMC_USB_DIV_2		(0x1 <<  8)	/* USB Clock divided by 2 */
 #define		AT91_PMC_USBDIV_8		(0x7 <<  8)	/* USB Clock divided by 8 */
 #define		AT91_PMC_USBDIV_10		(0x9 <<  8)	/* USB Clock divided by 10 */
 
-#ifdef CONFIG_AT91_LEGACY
-#define	AT91_PMC_PCKR(n)	(AT91_PMC + 0x40 + ((n) * 4))	/* Programmable Clock 0-3 Registers */
-
-#define	AT91_PMC_IER		(AT91_PMC + 0x60)	/* Interrupt Enable Register */
-#define	AT91_PMC_IDR		(AT91_PMC + 0x64)	/* Interrupt Disable Register */
-#define	AT91_PMC_SR		(AT91_PMC + 0x68)	/* Status Register */
-#endif
 #define		AT91_PMC_MOSCS		(1 <<  0)		/* MOSCS Flag */
 #define		AT91_PMC_LOCKA		(1 <<  1)		/* PLLA Lock */
 #define		AT91_PMC_LOCKB		(1 <<  2)		/* PLLB Lock */
@@ -253,13 +225,6 @@ typedef struct at91_pmc {
 #define		AT91_PMC_PCK1RDY	(1 <<  9)		/* Programmable Clock 1 */
 #define		AT91_PMC_PCK2RDY	(1 << 10)		/* Programmable Clock 2 */
 #define		AT91_PMC_PCK3RDY	(1 << 11)		/* Programmable Clock 3 */
-#ifdef CONFIG_AT91_LEGACY
-#define	AT91_PMC_IMR		(AT91_PMC + 0x6c)	/* Interrupt Mask Register */
 
-#define AT91_PMC_PROT		(AT91_PMC + 0xe4)	/* Protect Register [AT91CAP9 revC only] */
-#endif
 #define		AT91_PMC_PROTKEY	0x504d4301	/* Activation Code */
-#ifdef CONFIG_AT91_LEGACY
-#define AT91_PMC_VER		(AT91_PMC + 0xfc)	/* PMC Module Version [AT91CAP9 only] */
-#endif /* CONFIG_AT91_LEGACY */
 #endif
diff --git a/arch/arm/include/asm/arch-at91/at91_rstc.h b/arch/arm/include/asm/arch-at91/at91_rstc.h
index 423cf515d9..a9423428e7 100644
--- a/arch/arm/include/asm/arch-at91/at91_rstc.h
+++ b/arch/arm/include/asm/arch-at91/at91_rstc.h
@@ -38,4 +38,11 @@ typedef struct at91_rstc {
 
 #define AT91_RSTC_SR_NRSTL	0x00010000
 
+#define AT91_RSTC_RSTTYP		(7 << 8)	/* Reset Type */
+#define AT91_RSTC_RSTTYP_GENERAL	(0 << 8)
+#define AT91_RSTC_RSTTYP_WAKEUP	(1 << 8)
+#define AT91_RSTC_RSTTYP_WATCHDOG	(2 << 8)
+#define AT91_RSTC_RSTTYP_SOFTWARE	(3 << 8)
+#define AT91_RSTC_RSTTYP_USER		(4 << 8)
+
 #endif
diff --git a/arch/arm/include/asm/arch-at91/at91_spi.h b/arch/arm/include/asm/arch-at91/at91_spi.h
index f44cf67849..b18665b62c 100644
--- a/arch/arm/include/asm/arch-at91/at91_spi.h
+++ b/arch/arm/include/asm/arch-at91/at91_spi.h
@@ -118,6 +118,6 @@ typedef struct at91_spi {
 
 #define AT91_SPI_PTSR		0x0124			/* PDC Transfer Status Register */
 
-#endif /* CONFIG_AT91_LEGACY */
+#endif /* CONFIG_ATMEL_LEGACY */
 
 #endif
diff --git a/arch/arm/include/asm/arch-at91/at91_wdt.h b/arch/arm/include/asm/arch-at91/at91_wdt.h
index f0f4ed154a..0644bbf3c6 100644
--- a/arch/arm/include/asm/arch-at91/at91_wdt.h
+++ b/arch/arm/include/asm/arch-at91/at91_wdt.h
@@ -40,25 +40,4 @@ typedef struct at91_wdt {
 #define AT91_WDT_MR_WDDBGHLT		0x10000000
 #define AT91_WDT_MR_WDIDLEHLT		0x20000000
 
-#ifdef CONFIG_AT91_LEGACY
-
-#define AT91_WDT_CR		(AT91_WDT + 0x00)	/* Watchdog Control Register */
-#define		AT91_WDT_WDRSTT		(1    << 0)		/* Restart */
-#define		AT91_WDT_KEY		(0xa5 << 24)		/* KEY Password */
-
-#define AT91_WDT_MR		(AT91_WDT + 0x04)	/* Watchdog Mode Register */
-#define		AT91_WDT_WDV		(0xfff << 0)		/* Counter Value */
-#define		AT91_WDT_WDFIEN		(1     << 12)		/* Fault Interrupt Enable */
-#define		AT91_WDT_WDRSTEN	(1     << 13)		/* Reset Processor */
-#define		AT91_WDT_WDRPROC	(1     << 14)		/* Timer Restart */
-#define		AT91_WDT_WDDIS		(1     << 15)		/* Watchdog Disable */
-#define		AT91_WDT_WDD		(0xfff << 16)		/* Delta Value */
-#define		AT91_WDT_WDDBGHLT	(1     << 28)		/* Debug Halt */
-#define		AT91_WDT_WDIDLEHLT	(1     << 29)		/* Idle Halt */
-
-#define AT91_WDT_SR		(AT91_WDT + 0x08)	/* Watchdog Status Register */
-#define		AT91_WDT_WDUNF		(1 << 0)		/* Watchdog Underflow */
-#define		AT91_WDT_WDERR		(1 << 1)		/* Watchdog Error */
-
-#endif /* CONFIG_AT91_LEGACY */
 #endif
diff --git a/arch/arm/include/asm/arch-at91/at91cap9.h b/arch/arm/include/asm/arch-at91/at91cap9.h
index 7ac5bc1e7a..63870bc65d 100644
--- a/arch/arm/include/asm/arch-at91/at91cap9.h
+++ b/arch/arm/include/asm/arch-at91/at91cap9.h
@@ -55,75 +55,6 @@
 #define AT91_RSTC_BASE	0xfffffd00
 #define AT91_PIT_BASE	0xfffffd30
 
-#ifdef CONFIG_AT91_LEGACY
-
-/*
- * User Peripheral physical base addresses.
- */
-#define AT91CAP9_BASE_UDPHS		0xfff78000
-#define AT91CAP9_BASE_TCB0		0xfff7c000
-#define AT91CAP9_BASE_TC0		0xfff7c000
-#define AT91CAP9_BASE_TC1		0xfff7c040
-#define AT91CAP9_BASE_TC2		0xfff7c080
-#define AT91CAP9_BASE_MCI0		0xfff80000
-#define AT91CAP9_BASE_MCI1		0xfff84000
-#define AT91CAP9_BASE_TWI		0xfff88000
-#define AT91CAP9_BASE_US0		0xfff8c000
-#define AT91CAP9_BASE_US1		0xfff90000
-#define AT91CAP9_BASE_US2		0xfff94000
-#define AT91CAP9_BASE_SSC0		0xfff98000
-#define AT91CAP9_BASE_SSC1		0xfff9c000
-#define AT91CAP9_BASE_AC97C		0xfffa0000
-#define AT91CAP9_BASE_SPI0		0xfffa4000
-#define AT91CAP9_BASE_SPI1		0xfffa8000
-#define AT91CAP9_BASE_CAN		0xfffac000
-#define AT91CAP9_BASE_PWMC		0xfffb8000
-#define AT91CAP9_BASE_EMAC		0xfffbc000
-#define AT91CAP9_BASE_ADC		0xfffc0000
-#define AT91CAP9_BASE_ISI		0xfffc4000
-#define AT91_BASE_SYS			0xffffe200
-
-/*
- * System Peripherals (offset from AT91_BASE_SYS)
- */
-#define AT91_ECC	(0xffffe200 - AT91_BASE_SYS)
-#define AT91_BCRAMC	(0xffffe400 - AT91_BASE_SYS)
-#define AT91_DDRSDRC	(0xffffe600 - AT91_BASE_SYS)
-#define AT91_SMC	(0xffffe800 - AT91_BASE_SYS)
-#define AT91_MATRIX	(0xffffea00 - AT91_BASE_SYS)
-#define AT91_CCFG	(0xffffeb10 - AT91_BASE_SYS)
-#define AT91_DMA	(0xffffec00 - AT91_BASE_SYS)
-#define AT91_DBGU	(0xffffee00 - AT91_BASE_SYS)
-#define AT91_AIC	(0xfffff000 - AT91_BASE_SYS)
-#define AT91_PIOA	(0xfffff200 - AT91_BASE_SYS)
-#define AT91_PIOB	(0xfffff400 - AT91_BASE_SYS)
-#define AT91_PIOC	(0xfffff600 - AT91_BASE_SYS)
-#define AT91_PIOD	(0xfffff800 - AT91_BASE_SYS)
-#define AT91_PMC	(0xfffffc00 - AT91_BASE_SYS)
-#define AT91_RSTC	(0xfffffd00 - AT91_BASE_SYS)
-#define AT91_SHDWC	(0xfffffd10 - AT91_BASE_SYS)
-#define AT91_RTT	(0xfffffd20 - AT91_BASE_SYS)
-#define AT91_PIT	(0xfffffd30 - AT91_BASE_SYS)
-#define AT91_WDT	(0xfffffd40 - AT91_BASE_SYS)
-#define AT91_SCKCR	(0xfffffd50 - AT91_BASE_SYS)
-#define AT91_GPBR_REVB	(0xfffffd50 - AT91_BASE_SYS)
-#define AT91_GPBR_REVC	(0xfffffd60 - AT91_BASE_SYS)
-
-#define AT91_USART0	AT91CAP9_BASE_US0
-#define AT91_USART1	AT91CAP9_BASE_US1
-#define AT91_USART2	AT91CAP9_BASE_US2
-
-/*
- * SCKCR flags
- */
-#define AT91CAP9_SCKCR_RCEN	(1 << 0)	/* RC Oscillator Enable */
-#define AT91CAP9_SCKCR_OSC32EN	(1 << 1)	/* 32kHz Oscillator Enable */
-#define AT91CAP9_SCKCR_OSC32BYP	(1 << 2)	/* 32kHz Oscillator Bypass */
-#define AT91CAP9_SCKCR_OSCSEL	(1 << 3)	/* Slow Clock Selector */
-#define		AT91CAP9_SCKCR_OSCSEL_RC	(0 << 3)
-#define		AT91CAP9_SCKCR_OSCSEL_32	(1 << 3)
-
-#endif /* CONFIG_AT91_LEGACY */
 /*
  * Internal Memory.
  */
diff --git a/arch/arm/include/asm/arch-at91/at91sam9_smc.h b/arch/arm/include/asm/arch-at91/at91sam9_smc.h
index ec5d79735e..d29e98e711 100644
--- a/arch/arm/include/asm/arch-at91/at91sam9_smc.h
+++ b/arch/arm/include/asm/arch-at91/at91sam9_smc.h
@@ -73,64 +73,4 @@ typedef struct	at91_smc {
 #define AT91_SMC_MODE_PS_16		0x20000000
 #define AT91_SMC_MODE_PS_32		0x30000000
 
-#ifdef CONFIG_AT91_LEGACY
-
-#define AT91_SMC_SETUP(n)	(AT91_SMC + 0x00 + ((n)*0x10))	/* Setup Register for CS n */
-#define		AT91_SMC_NWESETUP	(0x3f << 0)			/* NWE Setup Length */
-#define			AT91_SMC_NWESETUP_(x)	((x) << 0)
-#define		AT91_SMC_NCS_WRSETUP	(0x3f << 8)			/* NCS Setup Length in Write Access */
-#define			AT91_SMC_NCS_WRSETUP_(x)	((x) << 8)
-#define		AT91_SMC_NRDSETUP	(0x3f << 16)			/* NRD Setup Length */
-#define			AT91_SMC_NRDSETUP_(x)	((x) << 16)
-#define		AT91_SMC_NCS_RDSETUP	(0x3f << 24)			/* NCS Setup Length in Read Access */
-#define			AT91_SMC_NCS_RDSETUP_(x)	((x) << 24)
-
-#define AT91_SMC_PULSE(n)	(AT91_SMC + 0x04 + ((n)*0x10))	/* Pulse Register for CS n */
-#define		AT91_SMC_NWEPULSE	(0x7f <<  0)			/* NWE Pulse Length */
-#define			AT91_SMC_NWEPULSE_(x)	((x) << 0)
-#define		AT91_SMC_NCS_WRPULSE	(0x7f <<  8)			/* NCS Pulse Length in Write Access */
-#define			AT91_SMC_NCS_WRPULSE_(x)((x) << 8)
-#define		AT91_SMC_NRDPULSE	(0x7f << 16)			/* NRD Pulse Length */
-#define			AT91_SMC_NRDPULSE_(x)	((x) << 16)
-#define		AT91_SMC_NCS_RDPULSE	(0x7f << 24)			/* NCS Pulse Length in Read Access */
-#define			AT91_SMC_NCS_RDPULSE_(x)((x) << 24)
-
-#define AT91_SMC_CYCLE(n)	(AT91_SMC + 0x08 + ((n)*0x10))	/* Cycle Register for CS n */
-#define		AT91_SMC_NWECYCLE	(0x1ff << 0 )			/* Total Write Cycle Length */
-#define			AT91_SMC_NWECYCLE_(x)	((x) << 0)
-#define		AT91_SMC_NRDCYCLE	(0x1ff << 16)			/* Total Read Cycle Length */
-#define			AT91_SMC_NRDCYCLE_(x)	((x) << 16)
-
-#define AT91_SMC_MODE(n)	(AT91_SMC + 0x0c + ((n)*0x10))	/* Mode Register for CS n */
-#define		AT91_SMC_READMODE	(1 <<  0)			/* Read Mode */
-#define		AT91_SMC_WRITEMODE	(1 <<  1)			/* Write Mode */
-#define		AT91_SMC_EXNWMODE	(3 <<  4)			/* NWAIT Mode */
-#define			AT91_SMC_EXNWMODE_DISABLE	(0 << 4)
-#define			AT91_SMC_EXNWMODE_FROZEN	(2 << 4)
-#define			AT91_SMC_EXNWMODE_READY		(3 << 4)
-#define		AT91_SMC_BAT		(1 <<  8)			/* Byte Access Type */
-#define			AT91_SMC_BAT_SELECT		(0 << 8)
-#define			AT91_SMC_BAT_WRITE		(1 << 8)
-#define		AT91_SMC_DBW		(3 << 12)			/* Data Bus Width */
-#define			AT91_SMC_DBW_8			(0 << 12)
-#define			AT91_SMC_DBW_16			(1 << 12)
-#define			AT91_SMC_DBW_32			(2 << 12)
-#define		AT91_SMC_TDF		(0xf << 16)			/* Data Float Time. */
-#define			AT91_SMC_TDF_(x)		((x) << 16)
-#define		AT91_SMC_TDFMODE	(1 << 20)			/* TDF Optimization - Enabled */
-#define		AT91_SMC_PMEN		(1 << 24)			/* Page Mode Enabled */
-#define		AT91_SMC_PS		(3 << 28)			/* Page Size */
-#define			AT91_SMC_PS_4			(0 << 28)
-#define			AT91_SMC_PS_8			(1 << 28)
-#define			AT91_SMC_PS_16			(2 << 28)
-#define			AT91_SMC_PS_32			(3 << 28)
-
-#if defined(AT91_SMC1)		/* The AT91SAM9263 has 2 Static Memory contollers */
-#define AT91_SMC1_SETUP(n)	(AT91_SMC1 + 0x00 + ((n)*0x10))	/* Setup Register for CS n */
-#define AT91_SMC1_PULSE(n)	(AT91_SMC1 + 0x04 + ((n)*0x10))	/* Pulse Register for CS n */
-#define AT91_SMC1_CYCLE(n)	(AT91_SMC1 + 0x08 + ((n)*0x10))	/* Cycle Register for CS n */
-#define AT91_SMC1_MODE(n)	(AT91_SMC1 + 0x0c + ((n)*0x10))	/* Mode Register for CS n */
-#endif
-
-#endif
 #endif
diff --git a/arch/arm/include/asm/arch-at91/atmel_mpddrc.h b/arch/arm/include/asm/arch-at91/atmel_mpddrc.h
new file mode 100644
index 0000000000..5741f6e94a
--- /dev/null
+++ b/arch/arm/include/asm/arch-at91/atmel_mpddrc.h
@@ -0,0 +1,115 @@
+/*
+ * Copyright (C) 2013 Atmel Corporation
+ *		      Bo Shen <voice.shen@atmel.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __ATMEL_MPDDRC_H__
+#define __ATMEL_MPDDRC_H__
+
+/*
+ * Only define the needed register in mpddr
+ * If other register needed, will add them later
+ */
+struct atmel_mpddr {
+	u32 mr;
+	u32 rtr;
+	u32 cr;
+	u32 tpr0;
+	u32 tpr1;
+	u32 tpr2;
+	u32 reserved[2];
+	u32 md;
+};
+
+int ddr2_init(const unsigned int ram_address,
+	       const struct atmel_mpddr *mpddr);
+
+/* Bit field in mode register */
+#define ATMEL_MPDDRC_MR_MODE_NORMAL_CMD		0x0
+#define ATMEL_MPDDRC_MR_MODE_NOP_CMD		0x1
+#define ATMEL_MPDDRC_MR_MODE_PRCGALL_CMD	0x2
+#define ATMEL_MPDDRC_MR_MODE_LMR_CMD		0x3
+#define ATMEL_MPDDRC_MR_MODE_RFSH_CMD		0x4
+#define ATMEL_MPDDRC_MR_MODE_EXT_LMR_CMD	0x5
+#define ATMEL_MPDDRC_MR_MODE_DEEP_CMD		0x6
+#define ATMEL_MPDDRC_MR_MODE_LPDDR2_CMD		0x7
+
+/* Bit field in configuration register */
+#define ATMEL_MPDDRC_CR_NC_MASK			0x3
+#define ATMEL_MPDDRC_CR_NC_COL_9		0x0
+#define ATMEL_MPDDRC_CR_NC_COL_10		0x1
+#define ATMEL_MPDDRC_CR_NC_COL_11		0x2
+#define ATMEL_MPDDRC_CR_NC_COL_12		0x3
+#define ATMEL_MPDDRC_CR_NR_MASK			(0x3 << 2)
+#define ATMEL_MPDDRC_CR_NR_ROW_11		(0x0 << 2)
+#define ATMEL_MPDDRC_CR_NR_ROW_12		(0x1 << 2)
+#define ATMEL_MPDDRC_CR_NR_ROW_13		(0x2 << 2)
+#define ATMEL_MPDDRC_CR_NR_ROW_14		(0x3 << 2)
+#define ATMEL_MPDDRC_CR_CAS_MASK		(0x7 << 4)
+#define ATMEL_MPDDRC_CR_CAS_DDR_CAS2		(0x2 << 4)
+#define ATMEL_MPDDRC_CR_CAS_DDR_CAS3		(0x3 << 4)
+#define ATMEL_MPDDRC_CR_CAS_DDR_CAS4		(0x4 << 4)
+#define ATMEL_MPDDRC_CR_CAS_DDR_CAS5		(0x5 << 4)
+#define ATMEL_MPDDRC_CR_CAS_DDR_CAS6		(0x6 << 4)
+#define ATMEL_MPDDRC_CR_DLL_RESET_ENABLED	(0x1 << 7)
+#define ATMEL_MPDDRC_CR_DIC_DS			(0x1 << 8)
+#define ATMEL_MPDDRC_CR_DIS_DLL			(0x1 << 9)
+#define ATMEL_MPDDRC_CR_OCD_DEFAULT		(0x7 << 12)
+#define ATMEL_MPDDRC_CR_ENRDM_ON		(0x1 << 17)
+#define ATMEL_MPDDRC_CR_NB_8BANKS		(0x1 << 20)
+#define ATMEL_MPDDRC_CR_NDQS_DISABLED		(0x1 << 21)
+#define ATMEL_MPDDRC_CR_DECOD_INTERLEAVED	(0x1 << 22)
+#define ATMEL_MPDDRC_CR_UNAL_SUPPORTED		(0x1 << 23)
+
+/* Bit field in timing parameter 0 register */
+#define ATMEL_MPDDRC_TPR0_TRAS_OFFSET		0
+#define ATMEL_MPDDRC_TPR0_TRAS_MASK		0xf
+#define ATMEL_MPDDRC_TPR0_TRCD_OFFSET		4
+#define ATMEL_MPDDRC_TPR0_TRCD_MASK		0xf
+#define ATMEL_MPDDRC_TPR0_TWR_OFFSET		8
+#define ATMEL_MPDDRC_TPR0_TWR_MASK		0xf
+#define ATMEL_MPDDRC_TPR0_TRC_OFFSET		12
+#define ATMEL_MPDDRC_TPR0_TRC_MASK		0xf
+#define ATMEL_MPDDRC_TPR0_TRP_OFFSET		16
+#define ATMEL_MPDDRC_TPR0_TRP_MASK		0xf
+#define ATMEL_MPDDRC_TPR0_TRRD_OFFSET		20
+#define ATMEL_MPDDRC_TPR0_TRRD_MASK		0xf
+#define ATMEL_MPDDRC_TPR0_TWTR_OFFSET		24
+#define ATMEL_MPDDRC_TPR0_TWTR_MASK		0x7
+#define ATMEL_MPDDRC_TPR0_RDC_WRRD_OFFSET	27
+#define ATMEL_MPDDRC_TPR0_RDC_WRRD_MASK		0x1
+#define ATMEL_MPDDRC_TPR0_TMRD_OFFSET		28
+#define ATMEL_MPDDRC_TPR0_TMRD_MASK		0xf
+
+/* Bit field in timing parameter 1 register */
+#define ATMEL_MPDDRC_TPR1_TRFC_OFFSET		0
+#define ATMEL_MPDDRC_TPR1_TRFC_MASK		0x7f
+#define ATMEL_MPDDRC_TPR1_TXSNR_OFFSET		8
+#define ATMEL_MPDDRC_TPR1_TXSNR_MASK		0xff
+#define ATMEL_MPDDRC_TPR1_TXSRD_OFFSET		16
+#define ATMEL_MPDDRC_TPR1_TXSRD_MASK		0xff
+#define ATMEL_MPDDRC_TPR1_TXP_OFFSET		24
+#define ATMEL_MPDDRC_TPR1_TXP_MASK		0xf
+
+/* Bit field in timing parameter 2 register */
+#define ATMEL_MPDDRC_TPR2_TXARD_OFFSET		0
+#define ATMEL_MPDDRC_TPR2_TXARD_MASK		0xf
+#define ATMEL_MPDDRC_TPR2_TXARDS_OFFSET		4
+#define ATMEL_MPDDRC_TPR2_TXARDS_MASK		0xf
+#define ATMEL_MPDDRC_TPR2_TRPA_OFFSET		8
+#define ATMEL_MPDDRC_TPR2_TRPA_MASK		0xf
+#define ATMEL_MPDDRC_TPR2_TRTP_OFFSET		12
+#define ATMEL_MPDDRC_TPR2_TRTP_MASK		0x7
+#define ATMEL_MPDDRC_TPR2_TFAW_OFFSET		16
+#define ATMEL_MPDDRC_TPR2_TFAW_MASK		0xf
+
+/* Bit field in Memory Device Register */
+#define ATMEL_MPDDRC_MD_LPDDR_SDRAM	0x3
+#define ATMEL_MPDDRC_MD_DDR2_SDRAM	0x6
+#define ATMEL_MPDDRC_MD_DBW_MASK	(0x1 << 4)
+#define ATMEL_MPDDRC_MD_DBW_32_BITS	(0x0 << 4)
+#define ATMEL_MPDDRC_MD_DBW_16_BITS	(0x1 << 4)
+
+#endif
diff --git a/arch/arm/include/asm/arch-at91/gpio.h b/arch/arm/include/asm/arch-at91/gpio.h
index 0700427fa4..71213883d7 100644
--- a/arch/arm/include/asm/arch-at91/gpio.h
+++ b/arch/arm/include/asm/arch-at91/gpio.h
@@ -16,7 +16,7 @@
 
 #ifdef CONFIG_ATMEL_LEGACY
 
-#define PIN_BASE		32
+#define PIN_BASE		0
 
 #define MAX_GPIO_BANKS		5
 
@@ -214,7 +214,7 @@ static inline unsigned pin_to_mask(unsigned pin)
 
 /* The following macros are need for backward compatibility */
 #define at91_set_GPIO_periph(x, y) \
-	at91_set_gpio_periph((x - PIN_BASE) / 32,(x % 32), y)
+	at91_set_pio_periph((x - PIN_BASE) / 32,(x % 32), y)
 #define at91_set_A_periph(x, y) \
 	at91_set_a_periph((x - PIN_BASE) / 32,(x % 32), y)
 #define at91_set_B_periph(x, y) \
@@ -231,4 +231,26 @@ static inline unsigned pin_to_mask(unsigned pin)
 #define at91_set_gpio_value(x, y)	at91_set_pio_value(x, y)
 #define at91_get_gpio_value(x)		at91_get_pio_value(x)
 #endif
-#endif
+
+#define GPIO_PIOA_BASE  (0)
+#define GPIO_PIOB_BASE  (GPIO_PIOA_BASE + 32)
+#define GPIO_PIOC_BASE  (GPIO_PIOB_BASE + 32)
+#define GPIO_PIOD_BASE  (GPIO_PIOC_BASE + 32)
+#define GPIO_PIOE_BASE  (GPIO_PIOD_BASE + 32)
+#define GPIO_PIN_PA(x)  (GPIO_PIOA_BASE + (x))
+#define GPIO_PIN_PB(x)  (GPIO_PIOB_BASE + (x))
+#define GPIO_PIN_PC(x)  (GPIO_PIOC_BASE + (x))
+#define GPIO_PIN_PD(x)  (GPIO_PIOD_BASE + (x))
+#define GPIO_PIN_PE(x)  (GPIO_PIOE_BASE + (x))
+
+static inline unsigned at91_gpio_to_port(unsigned gpio)
+{
+	return gpio / 32;
+}
+
+static inline unsigned at91_gpio_to_pin(unsigned gpio)
+{
+	return gpio % 32;
+}
+
+#endif /* __ASM_ARCH_AT91_GPIO_H */
diff --git a/arch/arm/include/asm/arch-at91/sama5d3.h b/arch/arm/include/asm/arch-at91/sama5d3.h
index 123a627cca..6d936f47fa 100644
--- a/arch/arm/include/asm/arch-at91/sama5d3.h
+++ b/arch/arm/include/asm/arch-at91/sama5d3.h
@@ -79,6 +79,7 @@
 #define ARCH_EXID_SAMA5D33	0x00414300
 #define ARCH_EXID_SAMA5D34	0x00414301
 #define ARCH_EXID_SAMA5D35	0x00584300
+#define ARCH_EXID_SAMA5D36	0x00004301
 
 #define cpu_is_sama5d3()	(get_chip_id() == ARCH_ID_SAMA5D3)
 #define cpu_is_sama5d31()	(cpu_is_sama5d3() && \
@@ -89,6 +90,8 @@
 		(get_extension_chip_id() == ARCH_EXID_SAMA5D34))
 #define cpu_is_sama5d35()	(cpu_is_sama5d3() && \
 		(get_extension_chip_id() == ARCH_EXID_SAMA5D35))
+#define cpu_is_sama5d36()	(cpu_is_sama5d3() && \
+		(get_extension_chip_id() == ARCH_EXID_SAMA5D36))
 
 /*
  * User Peripherals physical base addresses.
diff --git a/arch/arm/include/asm/arch-at91/spl.h b/arch/arm/include/asm/arch-at91/spl.h
new file mode 100644
index 0000000000..d8a87daa4a
--- /dev/null
+++ b/arch/arm/include/asm/arch-at91/spl.h
@@ -0,0 +1,24 @@
+/*
+ * Copyright (C) 2013 Atmel Corporation
+ *		      Bo Shen <voice.shen@atmel.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef	_ASM_ARCH_SPL_H_
+#define	_ASM_ARCH_SPL_H_
+
+enum {
+	BOOT_DEVICE_NONE,
+#ifdef CONFIG_SYS_USE_MMC
+	BOOT_DEVICE_MMC1,
+	BOOT_DEVICE_MMC2,
+	BOOT_DEVICE_MMC2_2,
+#elif CONFIG_SYS_USE_NANDFLASH
+	BOOT_DEVICE_NAND,
+#elif CONFIG_SYS_USE_SERIALFLASH
+	BOOT_DEVICE_SPI,
+#endif
+};
+
+#endif
diff --git a/arch/arm/include/asm/arch-bcm281xx/gpio.h b/arch/arm/include/asm/arch-bcm281xx/gpio.h
new file mode 100644
index 0000000000..1b40a96ad4
--- /dev/null
+++ b/arch/arm/include/asm/arch-bcm281xx/gpio.h
@@ -0,0 +1,15 @@
+/*
+ * Copyright 2013 Broadcom Corporation.
+ *
+ * SPDX-License-Identifier:      GPL-2.0+
+ */
+
+#ifndef __ARCH_BCM281XX_GPIO_H
+#define __ARCH_BCM281XX_GPIO_H
+
+/*
+ * Empty file - cmd_gpio.c requires this. The implementation
+ * is in drivers/gpio/kona_gpio.c instead of inlined here.
+ */
+
+#endif
diff --git a/arch/arm/include/asm/arch-bcm281xx/sysmap.h b/arch/arm/include/asm/arch-bcm281xx/sysmap.h
new file mode 100644
index 0000000000..880b4e0907
--- /dev/null
+++ b/arch/arm/include/asm/arch-bcm281xx/sysmap.h
@@ -0,0 +1,25 @@
+/*
+ * Copyright 2013 Broadcom Corporation.
+ *
+ * SPDX-License-Identifier:      GPL-2.0+
+ */
+
+#ifndef __ARCH_BCM281XX_SYSMAP_H
+
+#define BSC1_BASE_ADDR		0x3e016000
+#define BSC2_BASE_ADDR		0x3e017000
+#define BSC3_BASE_ADDR		0x3e018000
+#define GPIO2_BASE_ADDR		0x35003000
+#define KONA_MST_CLK_BASE_ADDR	0x3f001000
+#define KONA_SLV_CLK_BASE_ADDR	0x3e011000
+#define PMU_BSC_BASE_ADDR	0x3500d000
+#define PWRMGR_BASE_ADDR	0x35010000
+#define SDIO1_BASE_ADDR		0x3f180000
+#define SDIO2_BASE_ADDR		0x3f190000
+#define SDIO3_BASE_ADDR		0x3f1a0000
+#define SDIO4_BASE_ADDR		0x3f1b0000
+#define SECWD_BASE_ADDR		0x3500c000
+#define SECWD2_BASE_ADDR	0x35002f40
+#define TIMER_BASE_ADDR		0x3e00d000
+
+#endif
diff --git a/arch/arm/include/asm/arch-bcm2835/mbox.h b/arch/arm/include/asm/arch-bcm2835/mbox.h
index 24abe57959..dded857c3a 100644
--- a/arch/arm/include/asm/arch-bcm2835/mbox.h
+++ b/arch/arm/include/asm/arch-bcm2835/mbox.h
@@ -133,6 +133,54 @@ struct bcm2835_mbox_tag_get_arm_mem {
 	} body;
 };
 
+#define BCM2835_MBOX_POWER_DEVID_SDHCI		0
+#define BCM2835_MBOX_POWER_DEVID_UART0		1
+#define BCM2835_MBOX_POWER_DEVID_UART1		2
+#define BCM2835_MBOX_POWER_DEVID_USB_HCD	3
+#define BCM2835_MBOX_POWER_DEVID_I2C0		4
+#define BCM2835_MBOX_POWER_DEVID_I2C1		5
+#define BCM2835_MBOX_POWER_DEVID_I2C2		6
+#define BCM2835_MBOX_POWER_DEVID_SPI		7
+#define BCM2835_MBOX_POWER_DEVID_CCP2TX		8
+
+#define BCM2835_MBOX_POWER_STATE_RESP_ON	(1 << 0)
+/* Device doesn't exist */
+#define BCM2835_MBOX_POWER_STATE_RESP_NODEV	(1 << 1)
+
+#define BCM2835_MBOX_TAG_GET_POWER_STATE	0x00020001
+
+struct bcm2835_mbox_tag_get_power_state {
+	struct bcm2835_mbox_tag_hdr tag_hdr;
+	union {
+		struct {
+			u32 device_id;
+		} req;
+		struct {
+			u32 device_id;
+			u32 state;
+		} resp;
+	} body;
+};
+
+#define BCM2835_MBOX_TAG_SET_POWER_STATE	0x00028001
+
+#define BCM2835_MBOX_SET_POWER_STATE_REQ_ON	(1 << 0)
+#define BCM2835_MBOX_SET_POWER_STATE_REQ_WAIT	(1 << 1)
+
+struct bcm2835_mbox_tag_set_power_state {
+	struct bcm2835_mbox_tag_hdr tag_hdr;
+	union {
+		struct {
+			u32 device_id;
+			u32 state;
+		} req;
+		struct {
+			u32 device_id;
+			u32 state;
+		} resp;
+	} body;
+};
+
 #define BCM2835_MBOX_TAG_GET_CLOCK_RATE	0x00030002
 
 #define BCM2835_MBOX_CLOCK_ID_EMMC	1
@@ -350,6 +398,7 @@ struct bcm2835_mbox_tag_overscan {
 			u32 top;
 			u32 bottom;
 			u32 left;
+			u32 right;
 		} resp;
 	} body;
 };
diff --git a/arch/arm/include/asm/arch-davinci/hardware.h b/arch/arm/include/asm/arch-davinci/hardware.h
index 05ecc78768..98fe56e686 100644
--- a/arch/arm/include/asm/arch-davinci/hardware.h
+++ b/arch/arm/include/asm/arch-davinci/hardware.h
@@ -15,7 +15,7 @@
 #define __ASM_ARCH_HARDWARE_H
 
 #include <config.h>
-#include <asm/sizes.h>
+#include <linux/sizes.h>
 
 #define	REG(addr)	(*(volatile unsigned int *)(addr))
 #define REG_P(addr)	((volatile unsigned int *)(addr))
@@ -478,8 +478,9 @@ struct davinci_syscfg_regs {
 	dv_reg	rsvd[13];
 	dv_reg	kick0;
 	dv_reg	kick1;
-	dv_reg	rsvd1[53];
+	dv_reg	rsvd1[52];
 	dv_reg	mstpri[3];
+	dv_reg  rsvd2;
 	dv_reg	pinmux[20];
 	dv_reg	suspsrc;
 	dv_reg	chipsig;
@@ -613,42 +614,4 @@ static inline enum davinci_clk_ids get_async3_src(void)
 
 #endif
 
-struct davinci_rtc {
-	dv_reg	second;
-	dv_reg	minutes;
-	dv_reg	hours;
-	dv_reg	day;
-	dv_reg	month; /* 0x10 */
-	dv_reg	year;
-	dv_reg	dotw;
-	dv_reg	resv1;
-	dv_reg	alarmsecond; /* 0x20 */
-	dv_reg	alarmminute;
-	dv_reg	alarmhour;
-	dv_reg	alarmday;
-	dv_reg	alarmmonth; /* 0x30 */
-	dv_reg	alarmyear;
-	dv_reg	resv2[2];
-	dv_reg	ctrl; /* 0x40 */
-	dv_reg	status;
-	dv_reg	irq;
-	dv_reg	complsb;
-	dv_reg	compmsb; /* 0x50 */
-	dv_reg	osc;
-	dv_reg	resv3[2];
-	dv_reg	scratch0; /* 0x60 */
-	dv_reg	scratch1;
-	dv_reg	scratch2;
-	dv_reg	kick0r;
-	dv_reg	kick1r; /* 0x70 */
-};
-
-#define RTC_STATE_BUSY	0x01
-#define RTC_STATE_RUN	0x02
-
-#define RTC_KICK0R_WE	0x83e70b13
-#define RTC_KICK1R_WE	0x95a4f1e0
-
-#define davinci_rtc_base ((struct davinci_rtc *)DAVINCI_RTC_BASE)
-
 #endif /* __ASM_ARCH_HARDWARE_H */
diff --git a/arch/arm/include/asm/arch-davinci/sdmmc_defs.h b/arch/arm/include/asm/arch-davinci/sdmmc_defs.h
index 3e9e6065c7..9aa3f4ab27 100644
--- a/arch/arm/include/asm/arch-davinci/sdmmc_defs.h
+++ b/arch/arm/include/asm/arch-davinci/sdmmc_defs.h
@@ -151,6 +151,7 @@ struct davinci_mmc {
 	uint host_caps;		/* Host capabilities */
 	uint voltages;		/* Host supported voltages */
 	uint version;		/* MMC Controller version */
+	struct mmc_config cfg;
 };
 
 enum {
diff --git a/arch/arm/include/asm/arch-davinci/spl.h b/arch/arm/include/asm/arch-davinci/spl.h
index 5aa5d2d019..5afe0d4ba5 100644
--- a/arch/arm/include/asm/arch-davinci/spl.h
+++ b/arch/arm/include/asm/arch-davinci/spl.h
@@ -5,7 +5,7 @@
  * SPDX-License-Identifier:	GPL-2.0+
  */
 #ifndef	_ASM_ARCH_SPL_H_
-#define	_ASM_SPL_H_
+#define	_ASM_ARCH_SPL_H_
 
 #define BOOT_DEVICE_NAND	1
 #define BOOT_DEVICE_SPI		2
diff --git a/arch/arm/include/asm/arch-exynos/board.h b/arch/arm/include/asm/arch-exynos/board.h
new file mode 100644
index 0000000000..1b1cd0dd9e
--- /dev/null
+++ b/arch/arm/include/asm/arch-exynos/board.h
@@ -0,0 +1,29 @@
+/*
+ * (C) Copyright 2013 Samsung Electronics
+ * Rajeshwari Shinde <rajeshwari.s@samsung.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _EXYNOS_BOARD_H
+#define _EXYNOS_BOARD_H
+
+/*
+ * Exynos baord specific changes for
+ * board_init
+ */
+int exynos_init(void);
+
+/*
+ * Exynos board specific changes for
+ * board_early_init_f
+ */
+int exynos_early_init_f(void);
+
+/*
+ * Exynos board specific changes for
+ * board_power_init
+ */
+int exynos_power_init(void);
+
+#endif	/* EXYNOS_BOARD_H */
diff --git a/arch/arm/include/asm/arch-exynos/clk.h b/arch/arm/include/asm/arch-exynos/clk.h
index 1d6fa9370f..cdeef324cc 100644
--- a/arch/arm/include/asm/arch-exynos/clk.h
+++ b/arch/arm/include/asm/arch-exynos/clk.h
@@ -14,6 +14,7 @@
 #define HPLL	3
 #define VPLL	4
 #define BPLL	5
+#define RPLL	6
 
 enum pll_src_bit {
 	EXYNOS_SRC_MPLL = 6,
diff --git a/arch/arm/include/asm/arch-exynos/clock.h b/arch/arm/include/asm/arch-exynos/clock.h
index cf26eeffcf..8259b92b8e 100644
--- a/arch/arm/include/asm/arch-exynos/clock.h
+++ b/arch/arm/include/asm/arch-exynos/clock.h
@@ -858,6 +858,500 @@ struct exynos5_clock {
 	unsigned char	res123[0xf5d8];
 };
 
+struct exynos5420_clock {
+	unsigned int	apll_lock;			/* 0x10010000 */
+	unsigned char	res1[0xfc];
+	unsigned int	apll_con0;
+	unsigned int	apll_con1;
+	unsigned char	res2[0xf8];
+	unsigned int	src_cpu;
+	unsigned char	res3[0x1fc];
+	unsigned int	mux_stat_cpu;
+	unsigned char	res4[0xfc];
+	unsigned int	div_cpu0;		/* 0x10010500 */
+	unsigned int	div_cpu1;
+	unsigned char	res5[0xf8];
+	unsigned int	div_stat_cpu0;
+	unsigned int	div_stat_cpu1;
+	unsigned char	res6[0xf8];
+	unsigned int	gate_bus_cpu;
+	unsigned char	res7[0xfc];
+	unsigned int	gate_sclk_cpu;
+	unsigned char	res8[0x1fc];
+	unsigned int	clkout_cmu_cpu;		/* 0x10010a00 */
+	unsigned int	clkout_cmu_cpu_div_stat;
+	unsigned char	res9[0x5f8];
+	unsigned int	armclk_stopctrl;
+	unsigned char	res10[0x4];
+	unsigned int	arm_ema_ctrl;
+	unsigned int	arm_ema_status;
+	unsigned char	res11[0x10];
+	unsigned int	pwr_ctrl;
+	unsigned int	pwr_ctrl2;
+	unsigned char	res12[0xd8];
+	unsigned int	apll_con0_l8;		/* 0x1001100 */
+	unsigned int	apll_con0_l7;
+	unsigned int	apll_con0_l6;
+	unsigned int	apll_con0_l5;
+	unsigned int	apll_con0_l4;
+	unsigned int	apll_con0_l3;
+	unsigned int	apll_con0_l2;
+	unsigned int	apll_con0_l1;
+	unsigned int	iem_control;
+	unsigned char	res13[0xdc];
+	unsigned int	apll_con1_l8;		/* 0x10011200 */
+	unsigned int	apll_con1_l7;
+	unsigned int	apll_con1_l6;
+	unsigned int	apll_con1_l5;
+	unsigned int	apll_con1_l4;
+	unsigned int	apll_con1_l3;
+	unsigned int	apll_con1_l2;
+	unsigned int	apll_con1_l1;
+	unsigned char	res14[0xe0];
+	unsigned int	clkdiv_iem_l8;
+	unsigned int	clkdiv_iem_l7;		/* 0x10011304 */
+	unsigned int	clkdiv_iem_l6;
+	unsigned int	clkdiv_iem_l5;
+	unsigned int	clkdiv_iem_l4;
+	unsigned int	clkdiv_iem_l3;
+	unsigned int	clkdiv_iem_l2;
+	unsigned int	clkdiv_iem_l1;
+	unsigned char	res15[0xe0];
+	unsigned int	l2_status;
+	unsigned char	res16[0x0c];
+	unsigned int	cpu_status;		/* 0x10011410 */
+	unsigned char	res17[0x0c];
+	unsigned int	ptm_status;
+	unsigned char	res18[0xbdc];
+	unsigned int	cmu_cpu_spare0;
+	unsigned int	cmu_cpu_spare1;
+	unsigned int	cmu_cpu_spare2;
+	unsigned int	cmu_cpu_spare3;
+	unsigned int	cmu_cpu_spare4;
+	unsigned char	res19[0x1fdc];
+	unsigned int	cmu_cpu_version;
+	unsigned char	res20[0x20c];
+	unsigned int	src_cperi0;		/* 0x10014200 */
+	unsigned int	src_cperi1;
+	unsigned char	res21[0xf8];
+	unsigned int	src_mask_cperi;
+	unsigned char	res22[0x100];
+	unsigned int	mux_stat_cperi1;
+	unsigned char	res23[0xfc];
+	unsigned int	div_cperi1;
+	unsigned char	res24[0xfc];
+	unsigned int	div_stat_cperi1;
+	unsigned char	res25[0xf8];
+	unsigned int	gate_bus_cperi0;	/* 0x10014700 */
+	unsigned int	gate_bus_cperi1;
+	unsigned char	res26[0xf8];
+	unsigned int	gate_sclk_cperi;
+	unsigned char	res27[0xfc];
+	unsigned int	gate_ip_cperi;
+	unsigned char	res28[0xfc];
+	unsigned int	clkout_cmu_cperi;
+	unsigned int	clkout_cmu_cperi_div_stat;
+	unsigned char	res29[0x5f8];
+	unsigned int	dcgidx_map0;		/* 0x10015000 */
+	unsigned int	dcgidx_map1;
+	unsigned int	dcgidx_map2;
+	unsigned char	res30[0x14];
+	unsigned int	dcgperf_map0;
+	unsigned int	dcgperf_map1;
+	unsigned char	res31[0x18];
+	unsigned int	dvcidx_map;
+	unsigned char	res32[0x1c];
+	unsigned int	freq_cpu;
+	unsigned int	freq_dpm;
+	unsigned char	res33[0x18];
+	unsigned int	dvsemclk_en;		/* 0x10015080 */
+	unsigned int	maxperf;
+	unsigned char	res34[0x2e78];
+	unsigned int	cmu_cperi_spare0;
+	unsigned int	cmu_cperi_spare1;
+	unsigned int	cmu_cperi_spare2;
+	unsigned int	cmu_cperi_spare3;
+	unsigned int	cmu_cperi_spare4;
+	unsigned int	cmu_cperi_spare5;
+	unsigned int	cmu_cperi_spare6;
+	unsigned int	cmu_cperi_spare7;
+	unsigned int	cmu_cperi_spare8;
+	unsigned char	res35[0xcc];
+	unsigned int	cmu_cperi_version;		/* 0x10017ff0 */
+	unsigned char	res36[0x50c];
+	unsigned int	div_g2d;
+	unsigned char	res37[0xfc];
+	unsigned int	div_stat_g2d;
+	unsigned char	res38[0xfc];
+	unsigned int	gate_bus_g2d;
+	unsigned char	res39[0xfc];
+	unsigned int	gate_ip_g2d;
+	unsigned char	res40[0x1fc];
+	unsigned int	clkout_cmu_g2d;
+	unsigned int	clkout_cmu_g2d_div_stat;	/* 0x10018a04 */
+	unsigned char	res41[0xf8];
+	unsigned int	cmu_g2d_spare0;
+	unsigned int	cmu_g2d_spare1;
+	unsigned int	cmu_g2d_spare2;
+	unsigned int	cmu_g2d_spare3;
+	unsigned int	cmu_g2d_spare4;
+	unsigned char	res42[0x34dc];
+	unsigned int	cmu_g2d_version;
+	unsigned char	res43[0x30c];
+	unsigned int	div_cmu_isp0;
+	unsigned int	div_cmu_isp1;
+	unsigned int	div_isp2;		/* 0x1001c308 */
+	unsigned char	res44[0xf4];
+	unsigned int	div_stat_cmu_isp0;
+	unsigned int	div_stat_cmu_isp1;
+	unsigned int	div_stat_isp2;
+	unsigned char	res45[0x2f4];
+	unsigned int	gate_bus_isp0;
+	unsigned int	gate_bus_isp1;
+	unsigned int	gate_bus_isp2;
+	unsigned int	gate_bus_isp3;
+	unsigned char	res46[0xf0];
+	unsigned int	gate_ip_isp0;
+	unsigned int	gate_ip_isp1;
+	unsigned char	res47[0xf8];
+	unsigned int	gate_sclk_isp;
+	unsigned char	res48[0x0c];
+	unsigned int	mcuisp_pwr_ctrl;		/* 0x1001c910 */
+	unsigned char	res49[0x0ec];
+	unsigned int	clkout_cmu_isp;
+	unsigned int	clkout_cmu_isp_div_stat;
+	unsigned char	res50[0xf8];
+	unsigned int	cmu_isp_spare0;
+	unsigned int	cmu_isp_spare1;
+	unsigned int	cmu_isp_spare2;
+	unsigned int	cmu_isp_spare3;
+	unsigned char	res51[0x34e0];
+	unsigned int	cmu_isp_version;
+	unsigned char	res52[0x2c];
+	unsigned int	cpll_lock;			/* 10020020 */
+	unsigned char	res53[0xc];
+	unsigned int	dpll_lock;
+	unsigned char	res54[0xc];
+	unsigned int	epll_lock;
+	unsigned char	res55[0xc];
+	unsigned int	rpll_lock;
+	unsigned char	res56[0xc];
+	unsigned int	ipll_lock;
+	unsigned char	res57[0xc];
+	unsigned int	spll_lock;
+	unsigned char	res58[0xc];
+	unsigned int	vpll_lock;
+	unsigned char	res59[0xc];
+	unsigned int	mpll_lock;
+	unsigned char	res60[0x8c];
+	unsigned int	cpll_con0;			/* 10020120 */
+	unsigned int	cpll_con1;
+	unsigned int	dpll_con0;
+	unsigned int	dpll_con1;
+	unsigned int	epll_con0;
+	unsigned int	epll_con1;
+	unsigned int	epll_con2;
+	unsigned char	res601[0x4];
+	unsigned int	rpll_con0;
+	unsigned int	rpll_con1;
+	unsigned int	rpll_con2;
+	unsigned char	res602[0x4];
+	unsigned int	ipll_con0;
+	unsigned int	ipll_con1;
+	unsigned char	res61[0x8];
+	unsigned int	spll_con0;
+	unsigned int	spll_con1;
+	unsigned char	res62[0x8];
+	unsigned int	vpll_con0;
+	unsigned int	vpll_con1;
+	unsigned char	res63[0x8];
+	unsigned int	mpll_con0;
+	unsigned int	mpll_con1;
+	unsigned char	res64[0x78];
+	unsigned int	src_top0;		/* 0x10020200 */
+	unsigned int	src_top1;
+	unsigned int	src_top2;
+	unsigned int	src_top3;
+	unsigned int	src_top4;
+	unsigned int	src_top5;
+	unsigned int	src_top6;
+	unsigned int	src_top7;
+	unsigned char	res65[0xc];
+	unsigned int	src_disp10;		/* 0x1002022c */
+	unsigned char	res66[0x10];
+	unsigned int	src_mau;
+	unsigned int	src_fsys;
+	unsigned char	res67[0x8];
+	unsigned int	src_peric0;
+	unsigned int	src_peric1;
+	unsigned char	res68[0x18];
+	unsigned int	src_isp;
+	unsigned char	res69[0x0c];
+	unsigned int	src_top10;
+	unsigned int	src_top11;
+	unsigned int	src_top12;
+	unsigned char	res70[0x74];
+	unsigned int	src_mask_top0;
+	unsigned int	src_mask_top1;
+	unsigned int	src_mask_top2;
+	unsigned char	res71[0x10];
+	unsigned int	src_mask_top7;
+	unsigned char	res72[0xc];
+	unsigned int	src_mask_disp10;	/* 0x1002032c */
+	unsigned char	res73[0x4];
+	unsigned int	src_mask_mau;
+	unsigned char	res74[0x8];
+	unsigned int	src_mask_fsys;
+	unsigned char	res75[0xc];
+	unsigned int	src_mask_peric0;
+	unsigned int	src_mask_peric1;
+	unsigned char	res76[0x18];
+	unsigned int	src_mask_isp;
+	unsigned char	res77[0x8c];
+	unsigned int	mux_stat_top0;		/* 0x10020400 */
+	unsigned int	mux_stat_top1;
+	unsigned int	mux_stat_top2;
+	unsigned int	mux_stat_top3;
+	unsigned int	mux_stat_top4;
+	unsigned int	mux_stat_top5;
+	unsigned int	mux_stat_top6;
+	unsigned int	mux_stat_top7;
+	unsigned char	res78[0x60];
+	unsigned int	mux_stat_top10;
+	unsigned int	mux_stat_top11;
+	unsigned int	mux_stat_top12;
+	unsigned char	res79[0x74];
+	unsigned int	div_top0;		/* 0x10020500 */
+	unsigned int	div_top1;
+	unsigned int	div_top2;
+	unsigned char	res80[0x20];
+	unsigned int	div_disp10;
+	unsigned char	res81[0x14];
+	unsigned int	div_mau;
+	unsigned int	div_fsys0;
+	unsigned int	div_fsys1;
+	unsigned int	div_fsys2;
+	unsigned char	res82[0x4];
+	unsigned int	div_peric0;
+	unsigned int	div_peric1;
+	unsigned int	div_peric2;
+	unsigned int	div_peric3;
+	unsigned int	div_peric4;		/* 0x10020568 */
+	unsigned char	res83[0x14];
+	unsigned int	div_isp0;
+	unsigned int	div_isp1;
+	unsigned char	res84[0x8];
+	unsigned int	clkdiv2_ratio;
+	unsigned char	res850[0xc];
+	unsigned int	clkdiv4_ratio;
+	unsigned char	res85[0x5c];
+	unsigned int	div_stat_top0;
+	unsigned int	div_stat_top1;
+	unsigned int	div_stat_top2;
+	unsigned char	res86[0x20];
+	unsigned int	div_stat_disp10;
+	unsigned char	res87[0x14];
+	unsigned int	div_stat_mau;		/* 0x10020644 */
+	unsigned int	div_stat_fsys0;
+	unsigned int	div_stat_fsys1;
+	unsigned int	div_stat_fsys2;
+	unsigned char	res88[0x4];
+	unsigned int	div_stat_peric0;
+	unsigned int	div_stat_peric1;
+	unsigned int	div_stat_peric2;
+	unsigned int	div_stat_peric3;
+	unsigned int	div_stat_peric4;
+	unsigned char	res89[0x14];
+	unsigned int	div_stat_isp0;
+	unsigned int	div_stat_isp1;
+	unsigned char	res90[0x8];
+	unsigned int	clkdiv2_stat0;
+	unsigned char	res91[0xc];
+	unsigned int	clkdiv4_stat;
+	unsigned char	res92[0x5c];
+	unsigned int	gate_bus_top;		/* 0x10020700 */
+	unsigned char	res93[0xc];
+	unsigned int	gate_bus_gscl0;
+	unsigned char	res94[0xc];
+	unsigned int	gate_bus_gscl1;
+	unsigned char	res95[0x4];
+	unsigned int	gate_bus_disp1;
+	unsigned char	res96[0x4];
+	unsigned int	gate_bus_wcore;
+	unsigned int	gate_bus_mfc;
+	unsigned int	gate_bus_g3d;
+	unsigned int	gate_bus_gen;
+	unsigned int	gate_bus_fsys0;
+	unsigned int	gate_bus_fsys1;
+	unsigned int	gate_bus_fsys2;
+	unsigned int	gate_bus_mscl;
+	unsigned int	gate_bus_peric;
+	unsigned int	gate_bus_peric1;
+	unsigned char	res97[0x8];
+	unsigned int	gate_bus_peris0;
+	unsigned int	gate_bus_peris1;	/* 0x10020764 */
+	unsigned char	res98[0x8];
+	unsigned int	gate_bus_noc;
+	unsigned char	res99[0xac];
+	unsigned int	gate_top_sclk_gscl;
+	unsigned char	res1000[0x4];
+	unsigned int	gate_top_sclk_disp1;
+	unsigned char	res100[0x10];
+	unsigned int	gate_top_sclk_mau;
+	unsigned int	gate_top_sclk_fsys;
+	unsigned char	res101[0xc];
+	unsigned int	gate_top_sclk_peric;
+	unsigned char	res102[0xc];
+	unsigned int	gate_top_sclk_cperi;
+	unsigned char	res103[0xc];
+	unsigned int	gate_top_sclk_isp;
+	unsigned char	res104[0x9c];
+	unsigned int	gate_ip_gscl0;
+	unsigned char	res105[0xc];
+	unsigned int	gate_ip_gscl1;
+	unsigned char	res106[0x4];
+	unsigned int	gate_ip_disp1;
+	unsigned int	gate_ip_mfc;
+	unsigned int	gate_ip_g3d;
+	unsigned int	gate_ip_gen;		/* 0x10020934 */
+	unsigned char	res107[0xc];
+	unsigned int	gate_ip_fsys;
+	unsigned char	res108[0x8];
+	unsigned int	gate_ip_peric;
+	unsigned char	res109[0xc];
+	unsigned int	gate_ip_peris;
+	unsigned char	res110[0xc];
+	unsigned int	gate_ip_mscl;
+	unsigned char	res111[0xc];
+	unsigned int	gate_ip_block;
+	unsigned char	res112[0xc];
+	unsigned int	bypass;
+	unsigned char	res113[0x6c];
+	unsigned int	clkout_cmu_top;
+	unsigned int	clkout_cmu_top_div_stat;
+	unsigned char	res114[0xf8];
+	unsigned int	clkout_top_spare0;
+	unsigned int	clkout_top_spare1;
+	unsigned int	clkout_top_spare2;
+	unsigned int	clkout_top_spare3;
+	unsigned char	res115[0x34e0];
+	unsigned int	clkout_top_version;
+	unsigned char	res116[0xc01c];
+	unsigned int	bpll_lock;			/* 0x10030010 */
+	unsigned char	res117[0xfc];
+	unsigned int	bpll_con0;
+	unsigned int	bpll_con1;
+	unsigned char	res118[0xe8];
+	unsigned int	src_cdrex;
+	unsigned char	res119[0x1fc];
+	unsigned int	mux_stat_cdrex;
+	unsigned char	res120[0xfc];
+	unsigned int	div_cdrex0;
+	unsigned int	div_cdrex1;
+	unsigned char	res121[0xf8];
+	unsigned int	div_stat_cdrex;
+	unsigned char	res1211[0xfc];
+	unsigned int	gate_bus_cdrex;
+	unsigned int	gate_bus_cdrex1;
+	unsigned char	res122[0x1f8];
+	unsigned int	gate_ip_cdrex;
+	unsigned char	res123[0x10];
+	unsigned int	dmc_freq_ctrl;		/* 0x10030914 */
+	unsigned char	res124[0x4];
+	unsigned int	pause;
+	unsigned int	ddrphy_lock_ctrl;
+	unsigned char	res125[0xdc];
+	unsigned int	clkout_cmu_cdrex;
+	unsigned int	clkout_cmu_cdrex_div_stat;
+	unsigned char	res126[0x8];
+	unsigned int	lpddr3phy_ctrl;
+	unsigned int	lpddr3phy_con0;
+	unsigned int	lpddr3phy_con1;
+	unsigned int	lpddr3phy_con2;
+	unsigned int	lpddr3phy_con3;
+	unsigned int	lpddr3phy_con4;
+	unsigned int	lpddr3phy_con5;		/* 0x10030a28 */
+	unsigned int	pll_div2_sel;
+	unsigned char	res127[0xd0];
+	unsigned int	cmu_cdrex_spare0;
+	unsigned int	cmu_cdrex_spare1;
+	unsigned int	cmu_cdrex_spare2;
+	unsigned int	cmu_cdrex_spare3;
+	unsigned int	cmu_cdrex_spare4;
+	unsigned char	res128[0x34dc];
+	unsigned int	cmu_cdrex_version;		/* 0x10033ff0 */
+	unsigned char	res129[0x400c];
+	unsigned int	kpll_lock;
+	unsigned char	res130[0xfc];
+	unsigned int	kpll_con0;
+	unsigned int	kpll_con1;
+	unsigned char	res131[0xf8];
+	unsigned int	src_kfc;
+	unsigned char	res132[0x1fc];
+	unsigned int	mux_stat_kfc;		/* 0x10038400 */
+	unsigned char	res133[0xfc];
+	unsigned int	div_kfc0;
+	unsigned char	res134[0xfc];
+	unsigned int	div_stat_kfc0;
+	unsigned char	res135[0xfc];
+	unsigned int	gate_bus_cpu_kfc;
+	unsigned char	res136[0xfc];
+	unsigned int	gate_sclk_cpu_kfc;
+	unsigned char	res137[0x1fc];
+	unsigned int	clkout_cmu_kfc;
+	unsigned int	clkout_cmu_kfc_div_stat;	/* 0x10038a04 */
+	unsigned char	res138[0x5f8];
+	unsigned int	armclk_stopctrl_kfc;
+	unsigned char	res139[0x4];
+	unsigned int	armclk_ema_ctrl_kfc;
+	unsigned int	armclk_ema_status_kfc;
+	unsigned char	res140[0x10];
+	unsigned int	pwr_ctrl_kfc;
+	unsigned int	pwr_ctrl2_kfc;
+	unsigned char	res141[0xd8];
+	unsigned int	kpll_con0_l8;
+	unsigned int	kpll_con0_l7;
+	unsigned int	kpll_con0_l6;
+	unsigned int	kpll_con0_l5;
+	unsigned int	kpll_con0_l4;
+	unsigned int	kpll_con0_l3;
+	unsigned int	kpll_con0_l2;
+	unsigned int	kpll_con0_l1;
+	unsigned int	iem_control_kfc;		/* 0x10039120 */
+	unsigned char	res142[0xdc];
+	unsigned int	kpll_con1_l8;
+	unsigned int	kpll_con1_l7;
+	unsigned int	kpll_con1_l6;
+	unsigned int	kpll_con1_l5;
+	unsigned int	kpll_con1_l4;
+	unsigned int	kpll_con1_l3;
+	unsigned int	kpll_con1_l2;
+	unsigned int	kpll_con1_l1;
+	unsigned char	res143[0xe0];
+	unsigned int	clkdiv_iem_l8_kfc;		/* 0x10039300 */
+	unsigned int	clkdiv_iem_l7_kfc;
+	unsigned int	clkdiv_iem_l6_kfc;
+	unsigned int	clkdiv_iem_l5_kfc;
+	unsigned int	clkdiv_iem_l4_kfc;
+	unsigned int	clkdiv_iem_l3_kfc;
+	unsigned int	clkdiv_iem_l2_kfc;
+	unsigned int	clkdiv_iem_l1_kfc;
+	unsigned char	res144[0xe0];
+	unsigned int	l2_status_kfc;
+	unsigned char	res145[0xc];
+	unsigned int	cpu_status_kfc;		/* 0x10039410 */
+	unsigned char	res146[0xc];
+	unsigned int	ptm_status_kfc;
+	unsigned char	res147[0xbdc];
+	unsigned int	cmu_kfc_spare0;
+	unsigned int	cmu_kfc_spare1;
+	unsigned int	cmu_kfc_spare2;
+	unsigned int	cmu_kfc_spare3;
+	unsigned int	cmu_kfc_spare4;
+	unsigned char	res148[0x1fdc];
+	unsigned int	cmu_kfc_version;		/* 0x1003bff0 */
+};
+
 /* structure for epll configuration used in audio clock configuration */
 struct set_epll_con_val {
 	unsigned int freq_out;		/* frequency out */
diff --git a/arch/arm/include/asm/arch-exynos/cpu.h b/arch/arm/include/asm/arch-exynos/cpu.h
index 4b67191c07..fdf73b507a 100644
--- a/arch/arm/include/asm/arch-exynos/cpu.h
+++ b/arch/arm/include/asm/arch-exynos/cpu.h
@@ -25,8 +25,9 @@
 #define EXYNOS4_SYSTIMER_BASE		0x10050000
 #define EXYNOS4_WATCHDOG_BASE		0x10060000
 #define EXYNOS4_TZPC_BASE		0x10110000
-#define EXYNOS4_MIU_BASE		0x10600000
 #define EXYNOS4_DMC_CTRL_BASE		0x10400000
+#define EXYNOS4_MIU_BASE		0x10600000
+#define EXYNOS4_ACE_SFR_BASE		0x10830000
 #define EXYNOS4_GPIO_PART2_BASE		0x11000000
 #define EXYNOS4_GPIO_PART1_BASE		0x11400000
 #define EXYNOS4_FIMD_BASE		0x11C00000
@@ -48,9 +49,11 @@
 #define EXYNOS4_GPIO_PART4_BASE		DEVICE_NOT_AVAILABLE
 #define EXYNOS4_DP_BASE			DEVICE_NOT_AVAILABLE
 #define EXYNOS4_SPI_ISP_BASE		DEVICE_NOT_AVAILABLE
-#define EXYNOS4_ACE_SFR_BASE		DEVICE_NOT_AVAILABLE
 #define EXYNOS4_DMC_PHY_BASE		DEVICE_NOT_AVAILABLE
 #define EXYNOS4_AUDIOSS_BASE		DEVICE_NOT_AVAILABLE
+#define EXYNOS4_USB_HOST_XHCI_BASE	DEVICE_NOT_AVAILABLE
+#define EXYNOS4_USB3PHY_BASE		DEVICE_NOT_AVAILABLE
+#define EXYNOS4_DMC_TZASC_BASE		DEVICE_NOT_AVAILABLE
 
 /* EXYNOS4X12 */
 #define EXYNOS4X12_GPIO_PART3_BASE	0x03860000
@@ -65,6 +68,7 @@
 #define EXYNOS4X12_TZPC_BASE		0x10110000
 #define EXYNOS4X12_DMC_CTRL_BASE	0x10600000
 #define EXYNOS4X12_GPIO_PART4_BASE	0x106E0000
+#define EXYNOS4X12_ACE_SFR_BASE		0x10830000
 #define EXYNOS4X12_GPIO_PART2_BASE	0x11000000
 #define EXYNOS4X12_GPIO_PART1_BASE	0x11400000
 #define EXYNOS4X12_FIMD_BASE		0x11C00000
@@ -84,11 +88,13 @@
 #define EXYNOS4X12_I2S_BASE		DEVICE_NOT_AVAILABLE
 #define EXYNOS4X12_SPI_BASE		DEVICE_NOT_AVAILABLE
 #define EXYNOS4X12_SPI_ISP_BASE		DEVICE_NOT_AVAILABLE
-#define EXYNOS4X12_ACE_SFR_BASE		DEVICE_NOT_AVAILABLE
 #define EXYNOS4X12_DMC_PHY_BASE		DEVICE_NOT_AVAILABLE
 #define EXYNOS4X12_AUDIOSS_BASE		DEVICE_NOT_AVAILABLE
+#define EXYNOS4X12_USB_HOST_XHCI_BASE	DEVICE_NOT_AVAILABLE
+#define EXYNOS4X12_USB3PHY_BASE		DEVICE_NOT_AVAILABLE
+#define EXYNOS4X12_DMC_TZASC_BASE	DEVICE_NOT_AVAILABLE
 
-/* EXYNOS5 Common*/
+/* EXYNOS5 */
 #define EXYNOS5_I2C_SPACING		0x10000
 
 #define EXYNOS5_AUDIOSS_BASE		0x03810000
@@ -100,12 +106,14 @@
 #define EXYNOS5_SYSREG_BASE		0x10050000
 #define EXYNOS5_TZPC_BASE		0x10100000
 #define EXYNOS5_WATCHDOG_BASE		0x101D0000
-#define EXYNOS5_ACE_SFR_BASE            0x10830000
+#define EXYNOS5_ACE_SFR_BASE		0x10830000
 #define EXYNOS5_DMC_PHY_BASE		0x10C00000
 #define EXYNOS5_GPIO_PART3_BASE		0x10D10000
 #define EXYNOS5_DMC_CTRL_BASE		0x10DD0000
 #define EXYNOS5_GPIO_PART1_BASE		0x11400000
 #define EXYNOS5_MIPI_DSIM_BASE		0x11D00000
+#define EXYNOS5_USB_HOST_XHCI_BASE	0x12000000
+#define EXYNOS5_USB3PHY_BASE		0x12100000
 #define EXYNOS5_USB_HOST_EHCI_BASE	0x12110000
 #define EXYNOS5_USBPHY_BASE		0x12130000
 #define EXYNOS5_USBOTG_BASE		0x12140000
@@ -123,6 +131,46 @@
 
 #define EXYNOS5_ADC_BASE		DEVICE_NOT_AVAILABLE
 #define EXYNOS5_MODEM_BASE		DEVICE_NOT_AVAILABLE
+#define EXYNOS5_DMC_TZASC_BASE		DEVICE_NOT_AVAILABLE
+
+/* EXYNOS5420 */
+#define EXYNOS5420_AUDIOSS_BASE		0x03810000
+#define EXYNOS5420_GPIO_PART5_BASE	0x03860000
+#define EXYNOS5420_PRO_ID		0x10000000
+#define EXYNOS5420_CLOCK_BASE		0x10010000
+#define EXYNOS5420_POWER_BASE		0x10040000
+#define EXYNOS5420_SWRESET		0x10040400
+#define EXYNOS5420_SYSREG_BASE		0x10050000
+#define EXYNOS5420_TZPC_BASE		0x100E0000
+#define EXYNOS5420_WATCHDOG_BASE	0x101D0000
+#define EXYNOS5420_ACE_SFR_BASE		0x10830000
+#define EXYNOS5420_DMC_PHY_BASE		0x10C00000
+#define EXYNOS5420_DMC_CTRL_BASE	0x10C20000
+#define EXYNOS5420_DMC_TZASC_BASE	0x10D40000
+#define EXYNOS5420_USB_HOST_EHCI_BASE	0x12110000
+#define EXYNOS5420_MMC_BASE		0x12200000
+#define EXYNOS5420_SROMC_BASE		0x12250000
+#define EXYNOS5420_UART_BASE		0x12C00000
+#define EXYNOS5420_I2C_BASE		0x12C60000
+#define EXYNOS5420_I2C_8910_BASE	0x12E00000
+#define EXYNOS5420_SPI_BASE		0x12D20000
+#define EXYNOS5420_I2S_BASE		0x12D60000
+#define EXYNOS5420_PWMTIMER_BASE	0x12DD0000
+#define EXYNOS5420_SPI_ISP_BASE		0x131A0000
+#define EXYNOS5420_GPIO_PART2_BASE	0x13400000
+#define EXYNOS5420_GPIO_PART3_BASE	0x13410000
+#define EXYNOS5420_GPIO_PART4_BASE	0x14000000
+#define EXYNOS5420_GPIO_PART1_BASE	0x14010000
+#define EXYNOS5420_MIPI_DSIM_BASE	0x14500000
+#define EXYNOS5420_DP_BASE		0x145B0000
+
+#define EXYNOS5420_USBPHY_BASE		DEVICE_NOT_AVAILABLE
+#define EXYNOS5420_USBOTG_BASE		DEVICE_NOT_AVAILABLE
+#define EXYNOS5420_FIMD_BASE		DEVICE_NOT_AVAILABLE
+#define EXYNOS5420_ADC_BASE		DEVICE_NOT_AVAILABLE
+#define EXYNOS5420_MODEM_BASE		DEVICE_NOT_AVAILABLE
+#define EXYNOS5420_USB3PHY_BASE		DEVICE_NOT_AVAILABLE
+#define EXYNOS5420_USB_HOST_XHCI_BASE	DEVICE_NOT_AVAILABLE
 
 #ifndef __ASSEMBLY__
 #include <asm/io.h>
@@ -137,9 +185,11 @@ static inline int s5p_get_cpu_rev(void)
 
 static inline void s5p_set_cpu_id(void)
 {
-	unsigned int pro_id = (readl(EXYNOS4_PRO_ID) & 0x00FFF000) >> 12;
+	unsigned int pro_id = readl(EXYNOS4_PRO_ID);
+	unsigned int cpu_id = (pro_id & 0x00FFF000) >> 12;
+	unsigned int cpu_rev = pro_id & 0x000000FF;
 
-	switch (pro_id) {
+	switch (cpu_id) {
 	case 0x200:
 		/* Exynos4210 EVT0 */
 		s5p_cpu_id = 0x4210;
@@ -148,15 +198,21 @@ static inline void s5p_set_cpu_id(void)
 	case 0x210:
 		/* Exynos4210 EVT1 */
 		s5p_cpu_id = 0x4210;
+		s5p_cpu_rev = cpu_rev;
 		break;
 	case 0x412:
 		/* Exynos4412 */
 		s5p_cpu_id = 0x4412;
+		s5p_cpu_rev = cpu_rev;
 		break;
 	case 0x520:
 		/* Exynos5250 */
 		s5p_cpu_id = 0x5250;
 		break;
+	case 0x420:
+		/* Exynos5420 */
+		s5p_cpu_id = 0x5420;
+		break;
 	}
 }
 
@@ -184,6 +240,7 @@ static inline int __attribute__((no_instrument_function)) \
 IS_EXYNOS_TYPE(exynos4210, 0x4210)
 IS_EXYNOS_TYPE(exynos4412, 0x4412)
 IS_EXYNOS_TYPE(exynos5250, 0x5250)
+IS_EXYNOS_TYPE(exynos5420, 0x5420)
 
 #define SAMSUNG_BASE(device, base)				\
 static inline unsigned int __attribute__((no_instrument_function)) \
@@ -194,6 +251,8 @@ static inline unsigned int __attribute__((no_instrument_function)) \
 			return EXYNOS4X12_##base;		\
 		return EXYNOS4_##base;				\
 	} else if (cpu_is_exynos5()) {				\
+		if (proid_is_exynos5420())			\
+			return EXYNOS5420_##base;		\
 		return EXYNOS5_##base;				\
 	}							\
 	return 0;						\
@@ -220,7 +279,9 @@ SAMSUNG_BASE(swreset, SWRESET)
 SAMSUNG_BASE(timer, PWMTIMER_BASE)
 SAMSUNG_BASE(uart, UART_BASE)
 SAMSUNG_BASE(usb_phy, USBPHY_BASE)
+SAMSUNG_BASE(usb3_phy, USB3PHY_BASE)
 SAMSUNG_BASE(usb_ehci, USB_HOST_EHCI_BASE)
+SAMSUNG_BASE(usb_xhci, USB_HOST_XHCI_BASE)
 SAMSUNG_BASE(usb_otg, USBOTG_BASE)
 SAMSUNG_BASE(watchdog, WATCHDOG_BASE)
 SAMSUNG_BASE(power, POWER_BASE)
@@ -229,6 +290,7 @@ SAMSUNG_BASE(spi_isp, SPI_ISP_BASE)
 SAMSUNG_BASE(tzpc, TZPC_BASE)
 SAMSUNG_BASE(dmc_ctrl, DMC_CTRL_BASE)
 SAMSUNG_BASE(dmc_phy, DMC_PHY_BASE)
+SAMSUNG_BASE(dmc_tzasc, DMC_TZASC_BASE)
 SAMSUNG_BASE(audio_ass, AUDIOSS_BASE)
 #endif
 
diff --git a/arch/arm/include/asm/arch-exynos/dmc.h b/arch/arm/include/asm/arch-exynos/dmc.h
index f65c676cc5..d78536d2df 100644
--- a/arch/arm/include/asm/arch-exynos/dmc.h
+++ b/arch/arm/include/asm/arch-exynos/dmc.h
@@ -205,6 +205,127 @@ struct exynos5_dmc {
 	unsigned int pmcnt3_ppc_a;
 };
 
+struct exynos5420_dmc {
+	unsigned int concontrol;
+	unsigned int memcontrol;
+	unsigned int cgcontrol;
+	unsigned char res500[0x4];
+	unsigned int directcmd;
+	unsigned int prechconfig0;
+	unsigned int phycontrol0;
+	unsigned int prechconfig1;
+	unsigned char res1[0x8];
+	unsigned int pwrdnconfig;
+	unsigned int timingpzq;
+	unsigned int timingref;
+	unsigned int timingrow0;
+	unsigned int timingdata0;
+	unsigned int timingpower0;
+	unsigned int phystatus;
+	unsigned int etctiming;
+	unsigned int chipstatus;
+	unsigned char res3[0x8];
+	unsigned int mrstatus;
+	unsigned char res4[0x8];
+	unsigned int qoscontrol0;
+	unsigned char resr5[0x4];
+	unsigned int qoscontrol1;
+	unsigned char res6[0x4];
+	unsigned int qoscontrol2;
+	unsigned char res7[0x4];
+	unsigned int qoscontrol3;
+	unsigned char res8[0x4];
+	unsigned int qoscontrol4;
+	unsigned char res9[0x4];
+	unsigned int qoscontrol5;
+	unsigned char res10[0x4];
+	unsigned int qoscontrol6;
+	unsigned char res11[0x4];
+	unsigned int qoscontrol7;
+	unsigned char res12[0x4];
+	unsigned int qoscontrol8;
+	unsigned char res13[0x4];
+	unsigned int qoscontrol9;
+	unsigned char res14[0x4];
+	unsigned int qoscontrol10;
+	unsigned char res15[0x4];
+	unsigned int qoscontrol11;
+	unsigned char res16[0x4];
+	unsigned int qoscontrol12;
+	unsigned char res17[0x4];
+	unsigned int qoscontrol13;
+	unsigned char res18[0x4];
+	unsigned int qoscontrol14;
+	unsigned char res19[0x4];
+	unsigned int qoscontrol15;
+	unsigned char res20[0x4];
+	unsigned int timing_set_sw;
+	unsigned int timingrow1;
+	unsigned int timingdata1;
+	unsigned int timingpower1;
+	unsigned char res300[0x4];
+	unsigned int wrtra_config;
+	unsigned int rdlvl_config;
+	unsigned char res21[0x4];
+	unsigned int brbrsvcontrol;
+	unsigned int brbrsvconfig;
+	unsigned int brbqosconfig;
+	unsigned char res301[0x14];
+	unsigned int wrlvl_config0;
+	unsigned int wrlvl_config1;
+	unsigned int wrlvl_status;
+	unsigned char res23[0x4];
+	unsigned int ppcclockon;
+	unsigned int perevconfig0;
+	unsigned int perevconfig1;
+	unsigned int perevconfig2;
+	unsigned int perevconfig3;
+	unsigned char res24[0xc];
+	unsigned int control_io_rdata;
+	unsigned char res240[0xc];
+	unsigned int cacal_config0;
+	unsigned int cacal_config1;
+	unsigned int cacal_status;
+	unsigned char res302[0xa4];
+	unsigned int bp_control0;
+	unsigned int bp_config0_r;
+	unsigned int bp_config0_w;
+	unsigned char res303[0x4];
+	unsigned int bp_control1;
+	unsigned int bp_config1_r;
+	unsigned int bp_config1_w;
+	unsigned char res304[0x4];
+	unsigned int bp_control2;
+	unsigned int bp_config2_r;
+	unsigned int bp_config2_w;
+	unsigned char res305[0x4];
+	unsigned int bp_control3;
+	unsigned int bp_config3_r;
+	unsigned int bp_config3_w;
+	unsigned char res306[0xddb4];
+	unsigned int pmnc_ppc;
+	unsigned char res25[0xc];
+	unsigned int cntens_ppc;
+	unsigned char res26[0xc];
+	unsigned int cntenc_ppc;
+	unsigned char res27[0xc];
+	unsigned int intens_ppc;
+	unsigned char res28[0xc];
+	unsigned int intenc_ppc;
+	unsigned char res29[0xc];
+	unsigned int flag_ppc;
+	unsigned char res30[0xac];
+	unsigned int ccnt_ppc;
+	unsigned char res31[0xc];
+	unsigned int pmcnt0_ppc;
+	unsigned char res32[0xc];
+	unsigned int pmcnt1_ppc;
+	unsigned char res33[0xc];
+	unsigned int pmcnt2_ppc;
+	unsigned char res34[0xc];
+	unsigned int pmcnt3_ppc;
+};
+
 struct exynos5_phy_control {
 	unsigned int phy_con0;
 	unsigned int phy_con1;
@@ -252,6 +373,61 @@ struct exynos5_phy_control {
 	unsigned int phy_con42;
 };
 
+struct exynos5420_phy_control {
+	unsigned int phy_con0;
+	unsigned int phy_con1;
+	unsigned int phy_con2;
+	unsigned int phy_con3;
+	unsigned int phy_con4;
+	unsigned int phy_con5;
+	unsigned int phy_con6;
+	unsigned char res2[0x4];
+	unsigned int phy_con8;
+	unsigned char res5[0x4];
+	unsigned int phy_con10;
+	unsigned int phy_con11;
+	unsigned int phy_con12;
+	unsigned int phy_con13;
+	unsigned int phy_con14;
+	unsigned int phy_con15;
+	unsigned int phy_con16;
+	unsigned char res4[0x4];
+	unsigned int phy_con17;
+	unsigned int phy_con18;
+	unsigned int phy_con19;
+	unsigned int phy_con20;
+	unsigned int phy_con21;
+	unsigned int phy_con22;
+	unsigned int phy_con23;
+	unsigned int phy_con24;
+	unsigned int phy_con25;
+	unsigned int phy_con26;
+	unsigned int phy_con27;
+	unsigned int phy_con28;
+	unsigned int phy_con29;
+	unsigned int phy_con30;
+	unsigned int phy_con31;
+	unsigned int phy_con32;
+	unsigned int phy_con33;
+	unsigned int phy_con34;
+	unsigned char res6[0x8];
+	unsigned int phy_con37;
+	unsigned char res7[0x4];
+	unsigned int phy_con39;
+	unsigned int phy_con40;
+	unsigned int phy_con41;
+	unsigned int phy_con42;
+};
+
+struct exynos5420_tzasc {
+	unsigned char res1[0xf00];
+	unsigned int membaseconfig0;
+	unsigned int membaseconfig1;
+	unsigned char res2[0x8];
+	unsigned int memconfig0;
+	unsigned int memconfig1;
+};
+
 enum ddr_mode {
 	DDR_MODE_DDR2,
 	DDR_MODE_DDR3,
@@ -286,6 +462,7 @@ enum mem_manuf {
 #define PHY_CON0_T_WRRDCMD_SHIFT	17
 #define PHY_CON0_T_WRRDCMD_MASK		(0x7 << PHY_CON0_T_WRRDCMD_SHIFT)
 #define PHY_CON0_CTRL_DDR_MODE_SHIFT	11
+#define PHY_CON0_CTRL_DDR_MODE_MASK	0x3
 
 /* PHY_CON1 register fields */
 #define PHY_CON1_RDLVL_RDDATA_ADJ_SHIFT	0
diff --git a/arch/arm/include/asm/arch-exynos/dwmmc.h b/arch/arm/include/asm/arch-exynos/dwmmc.h
index b9eca765cd..a7ca12c477 100644
--- a/arch/arm/include/asm/arch-exynos/dwmmc.h
+++ b/arch/arm/include/asm/arch-exynos/dwmmc.h
@@ -6,14 +6,27 @@
  */
 
 #define DWMCI_CLKSEL		0x09C
-#define DWMCI_SHIFT_0		0x0
-#define DWMCI_SHIFT_1		0x1
-#define DWMCI_SHIFT_2		0x2
-#define DWMCI_SHIFT_3		0x3
 #define DWMCI_SET_SAMPLE_CLK(x)	(x)
 #define DWMCI_SET_DRV_CLK(x)	((x) << 16)
 #define DWMCI_SET_DIV_RATIO(x)	((x) << 24)
 
+#define EMMCP_MPSBEGIN0		0x1200
+#define EMMCP_SEND0		0x1204
+#define EMMCP_CTRL0		0x120C
+
+#define MPSCTRL_SECURE_READ_BIT		(0x1<<7)
+#define MPSCTRL_SECURE_WRITE_BIT	(0x1<<6)
+#define MPSCTRL_NON_SECURE_READ_BIT	(0x1<<5)
+#define MPSCTRL_NON_SECURE_WRITE_BIT	(0x1<<4)
+#define MPSCTRL_USE_FUSE_KEY		(0x1<<3)
+#define MPSCTRL_ECB_MODE		(0x1<<2)
+#define MPSCTRL_ENCRYPTION		(0x1<<1)
+#define MPSCTRL_VALID			(0x1<<0)
+
+/* CLKSEL Register */
+#define DWMCI_DIVRATIO_BIT		24
+#define DWMCI_DIVRATIO_MASK		0x7
+
 #ifdef CONFIG_OF_CONTROL
 int exynos_dwmmc_init(const void *blob);
 #endif
diff --git a/arch/arm/include/asm/arch-exynos/ehci.h b/arch/arm/include/asm/arch-exynos/ehci.h
index d79f25c0c3..d2d70bd82b 100644
--- a/arch/arm/include/asm/arch-exynos/ehci.h
+++ b/arch/arm/include/asm/arch-exynos/ehci.h
@@ -29,6 +29,20 @@
 #define EHCICTRL_ENAINCR8			(1 << 27)
 #define EHCICTRL_ENAINCR16			(1 << 26)
 
+#define HSIC_CTRL_REFCLKSEL                     (0x2)
+#define HSIC_CTRL_REFCLKSEL_MASK                (0x3)
+#define HSIC_CTRL_REFCLKSEL_SHIFT               (23)
+
+#define HSIC_CTRL_REFCLKDIV_12                  (0x24)
+#define HSIC_CTRL_REFCLKDIV_MASK                (0x7f)
+#define HSIC_CTRL_REFCLKDIV_SHIFT               (16)
+
+#define HSIC_CTRL_SIDDQ                         (0x1 << 6)
+#define HSIC_CTRL_FORCESLEEP                    (0x1 << 5)
+#define HSIC_CTRL_FORCESUSPEND                  (0x1 << 4)
+#define HSIC_CTRL_UTMISWRST                     (0x1 << 2)
+#define HSIC_CTRL_PHYSWRST                      (0x1 << 0)
+
 /* Register map for PHY control */
 struct exynos_usb_phy {
 	unsigned int usbphyctrl0;
diff --git a/arch/arm/include/asm/arch-exynos/gpio.h b/arch/arm/include/asm/arch-exynos/gpio.h
index a1a74393d0..d6868fa25d 100644
--- a/arch/arm/include/asm/arch-exynos/gpio.h
+++ b/arch/arm/include/asm/arch-exynos/gpio.h
@@ -127,6 +127,58 @@ struct exynos4x12_gpio_part4 {
 	struct s5p_gpio_bank v4;
 };
 
+struct exynos5420_gpio_part1 {
+	struct s5p_gpio_bank a0;
+	struct s5p_gpio_bank a1;
+	struct s5p_gpio_bank a2;
+	struct s5p_gpio_bank b0;
+	struct s5p_gpio_bank b1;
+	struct s5p_gpio_bank b2;
+	struct s5p_gpio_bank b3;
+	struct s5p_gpio_bank b4;
+	struct s5p_gpio_bank h0;
+};
+
+struct exynos5420_gpio_part2 {
+	struct s5p_gpio_bank y7; /* 0x1340_0000 */
+	struct s5p_gpio_bank res[0x5f]; /*  */
+	struct s5p_gpio_bank x0; /* 0x1340_0C00 */
+	struct s5p_gpio_bank x1; /* 0x1340_0C20 */
+	struct s5p_gpio_bank x2; /* 0x1340_0C40 */
+	struct s5p_gpio_bank x3; /* 0x1340_0C60 */
+};
+
+struct exynos5420_gpio_part3 {
+	struct s5p_gpio_bank c0;
+	struct s5p_gpio_bank c1;
+	struct s5p_gpio_bank c2;
+	struct s5p_gpio_bank c3;
+	struct s5p_gpio_bank c4;
+	struct s5p_gpio_bank d1;
+	struct s5p_gpio_bank y0;
+	struct s5p_gpio_bank y1;
+	struct s5p_gpio_bank y2;
+	struct s5p_gpio_bank y3;
+	struct s5p_gpio_bank y4;
+	struct s5p_gpio_bank y5;
+	struct s5p_gpio_bank y6;
+};
+
+struct exynos5420_gpio_part4 {
+	struct s5p_gpio_bank e0; /* 0x1400_0000 */
+	struct s5p_gpio_bank e1; /* 0x1400_0020 */
+	struct s5p_gpio_bank f0; /* 0x1400_0040 */
+	struct s5p_gpio_bank f1; /* 0x1400_0060 */
+	struct s5p_gpio_bank g0; /* 0x1400_0080 */
+	struct s5p_gpio_bank g1; /* 0x1400_00A0 */
+	struct s5p_gpio_bank g2; /* 0x1400_00C0 */
+	struct s5p_gpio_bank j4; /* 0x1400_00E0 */
+};
+
+struct exynos5420_gpio_part5 {
+	struct s5p_gpio_bank z0; /* 0x0386_0000 */
+};
+
 struct exynos5_gpio_part1 {
 	struct s5p_gpio_bank a0;
 	struct s5p_gpio_bank a1;
@@ -195,117 +247,81 @@ void s5p_gpio_set_rate(struct s5p_gpio_bank *bank, int gpio, int mode);
 
 /* GPIO pins per bank  */
 #define GPIO_PER_BANK 8
-
-#define exynos4_gpio_part1_get_nr(bank, pin) \
-	((((((unsigned int) &(((struct exynos4_gpio_part1 *) \
-			       EXYNOS4_GPIO_PART1_BASE)->bank)) \
-	    - EXYNOS4_GPIO_PART1_BASE) / sizeof(struct s5p_gpio_bank)) \
-	  * GPIO_PER_BANK) + pin)
-
-#define EXYNOS4_GPIO_PART1_MAX ((sizeof(struct exynos4_gpio_part1) \
-			    / sizeof(struct s5p_gpio_bank)) * GPIO_PER_BANK)
-
-#define exynos4_gpio_part2_get_nr(bank, pin) \
-	(((((((unsigned int) &(((struct exynos4_gpio_part2 *) \
-				EXYNOS4_GPIO_PART2_BASE)->bank)) \
-	    - EXYNOS4_GPIO_PART2_BASE) / sizeof(struct s5p_gpio_bank)) \
-	  * GPIO_PER_BANK) + pin) + EXYNOS4_GPIO_PART1_MAX)
-
-#define exynos4x12_gpio_part1_get_nr(bank, pin) \
-	((((((unsigned int) &(((struct exynos4x12_gpio_part1 *) \
-			       EXYNOS4X12_GPIO_PART1_BASE)->bank)) \
-	    - EXYNOS4X12_GPIO_PART1_BASE) / sizeof(struct s5p_gpio_bank)) \
-	  * GPIO_PER_BANK) + pin)
-
-#define EXYNOS4X12_GPIO_PART1_MAX ((sizeof(struct exynos4x12_gpio_part1) \
-			    / sizeof(struct s5p_gpio_bank)) * GPIO_PER_BANK)
-
-#define exynos4x12_gpio_part2_get_nr(bank, pin) \
-	(((((((unsigned int) &(((struct exynos4x12_gpio_part2 *) \
-				EXYNOS4X12_GPIO_PART2_BASE)->bank)) \
-	    - EXYNOS4X12_GPIO_PART2_BASE) / sizeof(struct s5p_gpio_bank)) \
-	  * GPIO_PER_BANK) + pin) + EXYNOS4X12_GPIO_PART1_MAX)
-
-#define EXYNOS4X12_GPIO_PART2_MAX ((sizeof(struct exynos4x12_gpio_part2) \
-			    / sizeof(struct s5p_gpio_bank)) * GPIO_PER_BANK)
-
-#define exynos4x12_gpio_part3_get_nr(bank, pin) \
-	(((((((unsigned int) &(((struct exynos4x12_gpio_part3 *) \
-				EXYNOS4X12_GPIO_PART3_BASE)->bank)) \
-	    - EXYNOS4X12_GPIO_PART3_BASE) / sizeof(struct s5p_gpio_bank)) \
-	  * GPIO_PER_BANK) + pin) + EXYNOS4X12_GPIO_PART2_MAX)
-
-#define exynos5_gpio_part1_get_nr(bank, pin) \
-	((((((unsigned int) &(((struct exynos5_gpio_part1 *) \
-			       EXYNOS5_GPIO_PART1_BASE)->bank)) \
-	    - EXYNOS5_GPIO_PART1_BASE) / sizeof(struct s5p_gpio_bank)) \
-	  * GPIO_PER_BANK) + pin)
-
-#define EXYNOS5_GPIO_PART1_MAX ((sizeof(struct exynos5_gpio_part1) \
-			    / sizeof(struct s5p_gpio_bank)) * GPIO_PER_BANK)
-
-#define exynos5_gpio_part2_get_nr(bank, pin) \
-	(((((((unsigned int) &(((struct exynos5_gpio_part2 *) \
-				EXYNOS5_GPIO_PART2_BASE)->bank)) \
-	    - EXYNOS5_GPIO_PART2_BASE) / sizeof(struct s5p_gpio_bank)) \
-	  * GPIO_PER_BANK) + pin) + EXYNOS5_GPIO_PART1_MAX)
-
-#define EXYNOS5_GPIO_PART2_MAX ((sizeof(struct exynos5_gpio_part2) \
-			    / sizeof(struct s5p_gpio_bank)) * GPIO_PER_BANK)
-
-#define exynos5_gpio_part3_get_nr(bank, pin) \
-	(((((((unsigned int) &(((struct exynos5_gpio_part3 *) \
-				EXYNOS5_GPIO_PART3_BASE)->bank)) \
-	    - EXYNOS5_GPIO_PART3_BASE) / sizeof(struct s5p_gpio_bank)) \
-	  * GPIO_PER_BANK) + pin) + EXYNOS5_GPIO_PART2_MAX)
-
-static inline unsigned int s5p_gpio_base(int nr)
+#define S5P_GPIO_PART_SHIFT	(24)
+#define S5P_GPIO_PART_MASK	(0xff)
+#define S5P_GPIO_BANK_SHIFT	(8)
+#define S5P_GPIO_BANK_MASK	(0xffff)
+#define S5P_GPIO_PIN_MASK	(0xff)
+
+#define S5P_GPIO_SET_PART(x) \
+			(((x) & S5P_GPIO_PART_MASK) << S5P_GPIO_PART_SHIFT)
+
+#define S5P_GPIO_GET_PART(x) \
+			(((x) >> S5P_GPIO_PART_SHIFT) & S5P_GPIO_PART_MASK)
+
+#define S5P_GPIO_SET_PIN(x) \
+			((x) & S5P_GPIO_PIN_MASK)
+
+#define EXYNOS4_GPIO_SET_BANK(part, bank) \
+			((((unsigned)&(((struct exynos4_gpio_part##part *) \
+			EXYNOS4_GPIO_PART##part##_BASE)->bank) \
+			- EXYNOS4_GPIO_PART##part##_BASE) \
+			& S5P_GPIO_BANK_MASK) << S5P_GPIO_BANK_SHIFT)
+
+#define EXYNOS4X12_GPIO_SET_BANK(part, bank) \
+			((((unsigned)&(((struct exynos4x12_gpio_part##part *) \
+			EXYNOS4X12_GPIO_PART##part##_BASE)->bank) \
+			- EXYNOS4X12_GPIO_PART##part##_BASE) \
+			& S5P_GPIO_BANK_MASK) << S5P_GPIO_BANK_SHIFT)
+
+#define EXYNOS5_GPIO_SET_BANK(part, bank) \
+			((((unsigned)&(((struct exynos5420_gpio_part##part *) \
+			EXYNOS5420_GPIO_PART##part##_BASE)->bank) \
+			- EXYNOS5_GPIO_PART##part##_BASE) \
+			& S5P_GPIO_BANK_MASK) << S5P_GPIO_BANK_SHIFT)
+
+#define EXYNOS5420_GPIO_SET_BANK(part, bank) \
+			((((unsigned)&(((struct exynos5420_gpio_part##part *) \
+			EXYNOS5420_GPIO_PART##part##_BASE)->bank) \
+			- EXYNOS5420_GPIO_PART##part##_BASE) \
+			& S5P_GPIO_BANK_MASK) << S5P_GPIO_BANK_SHIFT)
+
+#define exynos4_gpio_get(part, bank, pin) \
+			(S5P_GPIO_SET_PART(part) | \
+			EXYNOS4_GPIO_SET_BANK(part, bank) | \
+			S5P_GPIO_SET_PIN(pin))
+
+#define exynos4x12_gpio_get(part, bank, pin) \
+			(S5P_GPIO_SET_PART(part) | \
+			EXYNOS4X12_GPIO_SET_BANK(part, bank) | \
+			S5P_GPIO_SET_PIN(pin))
+
+#define exynos5420_gpio_get(part, bank, pin) \
+			(S5P_GPIO_SET_PART(part) | \
+			EXYNOS5420_GPIO_SET_BANK(part, bank) | \
+			S5P_GPIO_SET_PIN(pin))
+
+#define exynos5_gpio_get(part, bank, pin) \
+			(S5P_GPIO_SET_PART(part) | \
+			EXYNOS5_GPIO_SET_BANK(part, bank) | \
+			S5P_GPIO_SET_PIN(pin))
+
+static inline unsigned int s5p_gpio_base(int gpio)
 {
-	if (cpu_is_exynos5()) {
-		if (nr < EXYNOS5_GPIO_PART1_MAX)
-			return EXYNOS5_GPIO_PART1_BASE;
-		else if (nr < EXYNOS5_GPIO_PART2_MAX)
-			return EXYNOS5_GPIO_PART2_BASE;
-		else
-			return EXYNOS5_GPIO_PART3_BASE;
-
-	} else if (cpu_is_exynos4()) {
-		if (nr < EXYNOS4_GPIO_PART1_MAX)
-			return EXYNOS4_GPIO_PART1_BASE;
-		else
-			return EXYNOS4_GPIO_PART2_BASE;
+	unsigned gpio_part = S5P_GPIO_GET_PART(gpio);
+
+	switch (gpio_part) {
+	case 1:
+		return samsung_get_base_gpio_part1();
+	case 2:
+		return samsung_get_base_gpio_part2();
+	case 3:
+		return samsung_get_base_gpio_part3();
+	case 4:
+		return samsung_get_base_gpio_part4();
+	default:
+		return 0;
 	}
-
-	return 0;
-}
-
-static inline unsigned int s5p_gpio_part_max(int nr)
-{
-	if (cpu_is_exynos5()) {
-		if (nr < EXYNOS5_GPIO_PART1_MAX)
-			return 0;
-		else if (nr < EXYNOS5_GPIO_PART2_MAX)
-			return EXYNOS5_GPIO_PART1_MAX;
-		else
-			return EXYNOS5_GPIO_PART2_MAX;
-
-	} else if (cpu_is_exynos4()) {
-		if (proid_is_exynos4412()) {
-			if (nr < EXYNOS4X12_GPIO_PART1_MAX)
-				return 0;
-			else if (nr < EXYNOS4X12_GPIO_PART2_MAX)
-				return EXYNOS4X12_GPIO_PART1_MAX;
-			else
-				return EXYNOS4X12_GPIO_PART2_MAX;
-		} else {
-			if (nr < EXYNOS4_GPIO_PART1_MAX)
-				return 0;
-			else
-				return EXYNOS4_GPIO_PART1_MAX;
-		}
-	}
-
-	return 0;
 }
 #endif
 
diff --git a/arch/arm/include/asm/arch-exynos/mipi_dsim.h b/arch/arm/include/asm/arch-exynos/mipi_dsim.h
index 40aca71678..50e5c258a9 100644
--- a/arch/arm/include/asm/arch-exynos/mipi_dsim.h
+++ b/arch/arm/include/asm/arch-exynos/mipi_dsim.h
@@ -12,6 +12,7 @@
 
 #include <linux/list.h>
 #include <linux/fb.h>
+#include <lcd.h>
 
 #define PANEL_NAME_SIZE		(32)
 
@@ -368,8 +369,12 @@ int exynos_mipi_dsi_register_lcd_device(struct mipi_dsim_lcd_device
 						*lcd_dev);
 
 void exynos_set_dsim_platform_data(struct exynos_platform_mipi_dsim *pd);
+void exynos_init_dsim_platform_data(vidinfo_t *vid);
 
 /* panel driver init based on mipi dsi interface */
 void s6e8ax0_init(void);
 
+#ifdef CONFIG_OF_CONTROL
+extern int mipi_power(void);
+#endif
 #endif /* _DSIM_H */
diff --git a/arch/arm/include/asm/arch-exynos/mmc.h b/arch/arm/include/asm/arch-exynos/mmc.h
index 98312d1c3c..0fb6461c08 100644
--- a/arch/arm/include/asm/arch-exynos/mmc.h
+++ b/arch/arm/include/asm/arch-exynos/mmc.h
@@ -53,13 +53,20 @@
 #define SDHCI_CTRL4_DRIVE_MASK(_x)	((_x) << 16)
 #define SDHCI_CTRL4_DRIVE_SHIFT		(16)
 
+#define SDHCI_MAX_HOSTS 4
+
 int s5p_sdhci_init(u32 regbase, int index, int bus_width);
 
-static inline unsigned int s5p_mmc_init(int index, int bus_width)
+static inline int s5p_mmc_init(int index, int bus_width)
 {
 	unsigned int base = samsung_get_base_mmc() +
 				(S5P_MMC_DEV_OFFSET * index);
 
 	return s5p_sdhci_init(base, index, bus_width);
 }
+
+#ifdef CONFIG_OF_CONTROL
+int exynos_mmc_init(const void *blob);
+#endif
+
 #endif
diff --git a/arch/arm/include/asm/arch-exynos/periph.h b/arch/arm/include/asm/arch-exynos/periph.h
index 64bd8b7c91..5c1c3d4a93 100644
--- a/arch/arm/include/asm/arch-exynos/periph.h
+++ b/arch/arm/include/asm/arch-exynos/periph.h
@@ -34,6 +34,8 @@ enum periph_id {
 	PERIPH_ID_SDMMC1,
 	PERIPH_ID_SDMMC2,
 	PERIPH_ID_SDMMC3,
+	PERIPH_ID_I2C8 = 87,
+	PERIPH_ID_I2C9,
 	PERIPH_ID_I2S0 = 98,
 	PERIPH_ID_I2S1 = 99,
 
@@ -51,8 +53,8 @@ enum periph_id {
 	PERIPH_ID_PWM2,
 	PERIPH_ID_PWM3,
 	PERIPH_ID_PWM4,
+	PERIPH_ID_I2C10 = 203,
 
-	PERIPH_ID_COUNT,
 	PERIPH_ID_NONE = -1,
 };
 
diff --git a/arch/arm/include/asm/arch-exynos/power.h b/arch/arm/include/asm/arch-exynos/power.h
index 3241327016..c9609a23f5 100644
--- a/arch/arm/include/asm/arch-exynos/power.h
+++ b/arch/arm/include/asm/arch-exynos/power.h
@@ -16,7 +16,7 @@ struct exynos4_power {
 	unsigned int	gnss_rtc_out_ctrl;
 	unsigned char	res2[0x1ec];
 	unsigned int	system_power_down_ctrl;
-	unsigned char	res3[0x1];
+	unsigned int	res3;
 	unsigned int	system_power_down_option;
 	unsigned char	res4[0x1f4];
 	unsigned int	swreset;
@@ -831,6 +831,843 @@ struct exynos5_power {
 	unsigned int	cmu_reset_mau_option;
 	unsigned char	res163[0x24];
 };
+
+struct exynos5420_power {
+	unsigned int	om_stat;
+	unsigned int	lpi_mask0;
+	unsigned int	lpi_mask1;
+	unsigned char	res1[0x10];
+	unsigned int	rtc_clko_sel;
+	unsigned char	res2[0x1e0];
+	unsigned int	central_seq_configuration;
+	unsigned int	central_seq_status;
+	unsigned int	central_seq_option;
+	unsigned char	res3[0x14];
+	unsigned int	seq_transition0;
+	unsigned int	seq_transition1;
+	unsigned int	seq_transition2;
+	unsigned int	seq_transition3;
+	unsigned int	seq_transition4;
+	unsigned int	seq_transition5;
+	unsigned int	seq_transition6;
+	unsigned int	seq_transition7;
+	unsigned int	central_seq_coreblk_configuration;
+	unsigned int	central_seq_coreblk_status;
+	unsigned int	central_seq_coreblk_option;
+	unsigned char	res4[0x14];
+	unsigned int	seq_coreblk_transition0;
+	unsigned int	seq_coreblk_transition1;
+	unsigned int	seq_coreblk_transition2;
+	unsigned int	seq_coreblk_transition3;
+	unsigned int	seq_coreblk_transition4;
+	unsigned int	seq_coreblk_transition5;
+	unsigned int	seq_coreblk_transition6;
+	unsigned int	seq_coreblk_transition7;
+	unsigned char	res5[0x180];
+	unsigned int	swreset;
+	unsigned int	rst_stat;
+	unsigned int	automatic_wdt_reset_disable;
+	unsigned int	mask_wdt_reset_request;
+	unsigned int	mask_wreset_request;
+	unsigned char	res6[0xec];
+	unsigned int	reset_sequencer_configuration;
+	unsigned int	reset_sequencer_status;
+	unsigned int	reset_sequencer_option;
+	unsigned char	res7[0xf4];
+	unsigned int	wakeup_stat;
+	unsigned int	eint_wakeup_mask;
+	unsigned int	wakeup_mask;
+	unsigned int	wakeup_interrupt;
+	unsigned char	res8[0x10];
+	unsigned int	wakeup_stat_coreblk;
+	unsigned int	eint_wakeup_mask_coreblk;
+	unsigned int	wakeup_mask_coreblk;
+	unsigned int	wakeup_interrupt_coreblk;
+	unsigned char	res9[0xd0];
+	unsigned int	hdmi_phy_control;
+	unsigned int	usbdev_phy_control;
+	unsigned int	usbdev1_phy_control;
+	unsigned int	usbhost_phy_control;
+	unsigned char	res104[0x4];
+	unsigned int	mipi_phy0_control;
+	unsigned int	mipi_phy1_control;
+	unsigned int	mipi_phy2_control;
+	unsigned int	adc_phy_control;
+	unsigned int	mtcadc_phy_control;
+	unsigned int	dptx_phy_control;
+	unsigned char	res10[0xd4];
+	unsigned int	inform0;
+	unsigned int	inform1;
+	unsigned int	inform2;
+	unsigned int	inform3;
+	unsigned int	sysip_dat0;
+	unsigned int	sysip_dat1;
+	unsigned int	sysip_dat2;
+	unsigned int	sysip_dat3;
+	unsigned char	res11[0xe0];
+	unsigned int	pmu_spare0;
+	unsigned int	pmu_spare1;
+	unsigned int	pmu_spare2;
+	unsigned int	pmu_spare3;
+	unsigned char	res12[0x4];
+	unsigned int	cg_status0;
+	unsigned int	cg_status1;
+	unsigned int	cg_status2;
+	unsigned int	cg_status3;
+	unsigned int	cg_status4;
+	unsigned char	res200[0x58];
+	unsigned int	irom_data_reg0;
+	unsigned int	irom_data_reg1;
+	unsigned int	irom_data_reg2;
+	unsigned int	irom_data_reg3;
+	unsigned char	res13[0x70];
+	unsigned int	pmu_debug;
+	unsigned char	res14[0x5fc];
+	unsigned int	arm_core0_sys_pwr_reg;
+	unsigned char	res500[0xc];
+	unsigned int	arm_core1_sys_pwr_reg;
+	unsigned char	res501[0xc];
+	unsigned int	arm_core2_sys_pwr_reg;
+	unsigned char	res502[0xc];
+	unsigned int	arm_core3_sys_pwr_reg;
+	unsigned char	res503[0xc];
+	unsigned int	kfc_core0_sys_pwr_reg;
+	unsigned char	res504[0xc];
+	unsigned int	kfc_core1_sys_pwr_reg;
+	unsigned char	res505[0xc];
+	unsigned int	kfc_core2_sys_pwr_reg;
+	unsigned char	res506[0xc];
+	unsigned int	kfc_core3_sys_pwr_reg;
+	unsigned char	res507[0x1c];
+	unsigned int	isp_arm_sys_pwr_reg;
+	unsigned char	res18[0xc];
+	unsigned int	arm_common_sys_pwr_reg;
+	unsigned char	res508[0xc];
+	unsigned int	kfc_common_sys_pwr_reg;
+	unsigned char	res19[0xc];
+	unsigned int	arm_l2_sys_pwr_reg;
+	unsigned char	res509[0xc];
+	unsigned int	kfc_l2_sys_pwr_reg;
+	unsigned char	res20[0xc];
+	unsigned int	cmu_cpu_aclkstop_sys_pwr_reg;
+	unsigned int	cmu_cpu_sclkstop_sys_pwr_reg;
+	unsigned char	res510[0x8];
+	unsigned int	cmu_kfc_aclkstop_sys_pwr_reg;
+	unsigned char	res511[0xc];
+	unsigned int	cmu_aclkstop_sys_pwr_reg;
+	unsigned int	cmu_sclkstop_sys_pwr_reg;
+	unsigned char	res21[0x4];
+	unsigned int	cmu_reset_sys_pwr_reg;
+	unsigned char	res22[0x10];
+	unsigned int	cmu_aclkstop_coreblk_sys_pwr_reg;
+	unsigned int	cmu_sclkstop_coreblk_sys_pwr_reg;
+	unsigned char	res23[0x4];
+	unsigned int	cmu_reset_coreblk_sys_pwr_reg;
+	unsigned int	dram_freq_down_sys_pwr_reg;
+	unsigned int	ddrphy_dlloff_sys_pwr_reg;
+	unsigned int	ddrphy_dlllock_sys_pwr_reg;
+	unsigned char	res25[0x4];
+	unsigned int	apll_sysclk_sys_pwr_reg;
+	unsigned int	mpll_sysclk_sys_pwr_reg;
+	unsigned int	vpll_sysclk_sys_pwr_reg;
+	unsigned int	epll_sysclk_sys_pwr_reg;
+	unsigned int	bpll_sysclk_sys_pwr_reg;
+	unsigned int	cpll_sysclk_sys_pwr_reg;
+	unsigned int	dpll_sysclk_sys_pwr_reg;
+	unsigned int	ipll_sysclk_sys_pwr_reg;
+	unsigned int	kpll_sysclk_sys_pwr_reg;
+	unsigned int	mplluser_sysclk_sys_pwr_reg;
+	unsigned char	res512[0x8];
+	unsigned int	bplluser_sysclk_sys_pwr_reg;
+	unsigned int	rpll_sysclk_sys_pwr_reg;
+	unsigned int	spll_sysclk_sys_pwr_reg;
+	unsigned char	res26[0x4];
+	unsigned int	top_bus_sys_pwr_reg;
+	unsigned int	top_retention_sys_pwr_reg;
+	unsigned int	top_pwr_sys_pwr_reg;
+	unsigned char	res29[0x4];
+	unsigned int	top_bus_coreblk_sys_pwr_reg;
+	unsigned int	top_retention_coreblk_sys_pwr_reg;
+	unsigned int	top_pwr_coreblk_sys_pwr_reg;
+	unsigned char	res30[0x4];
+	unsigned int	logic_reset_sys_pwr_reg;
+	unsigned int	oscclk_gate_sys_pwr_reg;
+	unsigned char	res31[0x8];
+	unsigned int	logic_reset_coreblk_sys_pwr_reg;
+	unsigned int	oscclk_gate_coreblk_sys_pwr_reg;
+	unsigned int	intram_mem_sys_pwr_reg;
+	unsigned int	introm_mem_sys_pwr_reg;
+	unsigned char	res32[0x44];
+	unsigned int	pad_retention_mau_sys_pwr_reg;
+	unsigned int	pad_retention_jtag_sys_pwr_reg;
+	unsigned char	res36[0x4];
+	unsigned int	pad_retention_dram_sys_pwr_reg;
+	unsigned int	pad_retention_uart_sys_pwr_reg;
+	unsigned int	pad_retention_mmca_sys_pwr_reg;
+	unsigned int	pad_retention_mmcb_sys_pwr_reg;
+	unsigned int	pad_retention_mmcc_sys_pwr_reg;
+	unsigned int	pad_retention_hsi_sys_pwr_reg;
+	unsigned int	pad_retention_ebia_sys_pwr_reg;
+	unsigned int	pad_retention_ebib_sys_pwr_reg;
+	unsigned int	pad_retention_spi_sys_pwr_reg;
+	unsigned int	pad_retention_dram_coreblk_sys_pwr_reg;
+	unsigned char	res28[0x8];
+	unsigned int	pad_isolation_sys_pwr_reg;
+	unsigned char	res37[0xc];
+	unsigned int	pad_isolation_coreblk_sys_pwr_reg;
+	unsigned char	res38[0xc];
+	unsigned int	pad_alv_sel_sys_pwr_reg;
+	unsigned char	res39[0x1c];
+	unsigned int	xusbxti_sys_pwr_reg;
+	unsigned int	xxti_sys_pwr_reg;
+	unsigned char	res40[0x38];
+	unsigned int	ext_regulator_sys_pwr_reg;
+	unsigned char	res41[0x3c];
+	unsigned int	gpio_mode_sys_pwr_reg;
+	unsigned char	res42[0x1c];
+	unsigned int	gpio_mode_coreblk_sys_pwr_reg;
+	unsigned char	res43[0x1c];
+	unsigned int	gpio_mode_mau_sys_pwr_reg;
+	unsigned int	top_asb_reset_sys_pwr_reg;
+	unsigned int	top_asb_isolation_sys_pwr_reg;
+	unsigned char	res44[0xb4];
+	unsigned int	gscl_sys_pwr_reg;
+	unsigned int	isp_sys_pwr_reg;
+	unsigned int	mfc_sys_pwr_reg;
+	unsigned int	g3d_sys_pwr_reg;
+	unsigned int	disp1_sys_pwr_reg;
+	unsigned int	mau_sys_pwr_reg;
+	unsigned int	g2d_sys_pwr_reg;
+	unsigned int	msc_sys_pwr_reg;
+	unsigned int	fsys_sys_pwr_reg;
+	unsigned int	fsys2_sys_pwr_reg;
+	unsigned int	psgen_sys_pwr_reg;
+	unsigned int	peric_sys_pwr_reg;
+	unsigned int	wcore_sys_pwr_reg;
+	unsigned char	res46[0x4c];
+	unsigned int	cmu_clkstop_gscl_sys_pwr_reg;
+	unsigned int	cmu_clkstop_isp_sys_pwr_reg;
+	unsigned int	cmu_clkstop_mfc_sys_pwr_reg;
+	unsigned int	cmu_clkstop_g3d_sys_pwr_reg;
+	unsigned int	cmu_clkstop_disp1_sys_pwr_reg;
+	unsigned int	cmu_clkstop_mau_sys_pwr_reg;
+	unsigned int	cmu_clkstop_g2d_sys_pwr_reg;
+	unsigned int	cmu_clkstop_msc_sys_pwr_reg;
+	unsigned int	cmu_clkstop_fsys_sys_pwr_reg;
+	unsigned int	cmu_clkstop_fsys2_sys_pwr_reg;
+	unsigned int	cmu_clkstop_psgen_sys_pwr_reg;
+	unsigned int	cmu_clkstop_peric_sys_pwr_reg;
+	unsigned int	cmu_clkstop_wcore_sys_pwr_reg;
+	unsigned char	res48[0x8];
+	unsigned int	cmu_sysclk_toppwr_sys_pwr_reg;
+	unsigned int	cmu_sysclk_gscl_sys_pwr_reg;
+	unsigned int	cmu_sysclk_isp_sys_pwr_reg;
+	unsigned int	cmu_sysclk_mfc_sys_pwr_reg;
+	unsigned int	cmu_sysclk_g3d_sys_pwr_reg;
+	unsigned int	cmu_sysclk_disp1_sys_pwr_reg;
+	unsigned int	cmu_sysclk_mau_sys_pwr_reg;
+	unsigned int	cmu_sysclk_g2d_sys_pwr_reg;
+	unsigned int	cmu_sysclk_msc_sys_pwr_reg;
+	unsigned int	cmu_sysclk_fsys_sys_pwr_reg;
+	unsigned int	cmu_sysclk_fsys2_sys_pwr_reg;
+	unsigned int	cmu_sysclk_psgen_sys_pwr_reg;
+	unsigned int	cmu_sysclk_peric_sys_pwr_reg;
+	unsigned int	cmu_sysclk_wcore_sys_pwr_reg;
+	unsigned int	cmu_sysclk_coreblk_toppwr_sys_pwr_reg;
+	unsigned char	res50[0x78];
+	unsigned int	cmu_reset_fsys2_sys_pwr_reg;
+	unsigned int	cmu_reset_psgen_sys_pwr_reg;
+	unsigned int	cmu_reset_peric_sys_pwr_reg;
+	unsigned int	cmu_reset_wcore_sys_pwr_reg;
+	unsigned int	cmu_reset_gscl_sys_pwr_reg;
+	unsigned int	cmu_reset_isp_sys_pwr_reg;
+	unsigned int	cmu_reset_mfc_sys_pwr_reg;
+	unsigned int	cmu_reset_g3d_sys_pwr_reg;
+	unsigned int	cmu_reset_disp1_sys_pwr_reg;
+	unsigned int	cmu_reset_mau_sys_pwr_reg;
+	unsigned int	cmu_reset_g2d_sys_pwr_reg;
+	unsigned int	cmu_reset_msc_sys_pwr_reg;
+	unsigned int	cmu_reset_fsys_sys_pwr_reg;
+	unsigned char	res52[0xa5c];
+	unsigned int	arm_core0_configuration;
+	unsigned int	arm_core0_status;
+	unsigned int	arm_core0_option;
+	unsigned char	res53[0x14];
+	unsigned int	dis_irq_arm_core0_local_configuration;
+	unsigned int	dis_irq_arm_core0_local_status;
+	unsigned int	dis_irq_arm_core0_local_option;
+	unsigned char	res54[0x14];
+	unsigned int	dis_irq_arm_core0_central_configuration;
+	unsigned int	dis_irq_arm_core0_central_status;
+	unsigned int	dis_irq_arm_core0_central_option;
+	unsigned char	res55[0x34];
+	unsigned int	arm_core1_configuration;
+	unsigned int	arm_core1_status;
+	unsigned int	arm_core1_option;
+	unsigned char	res56[0x14];
+	unsigned int	dis_irq_arm_core1_local_configuration;
+	unsigned int	dis_irq_arm_core1_local_status;
+	unsigned int	dis_irq_arm_core1_local_option;
+	unsigned char	res57[0x14];
+	unsigned int	dis_irq_arm_core1_central_configuration;
+	unsigned int	dis_irq_arm_core1_central_status;
+	unsigned int	dis_irq_arm_core1_central_option;
+	unsigned char	res600[0x34];
+	unsigned int	arm_core2_configuration;
+	unsigned int	arm_core2_status;
+	unsigned int	arm_core2_option;
+	unsigned char	res601[0x14];
+	unsigned int	dis_irq_arm_core2_local_configuration;
+	unsigned int	dis_irq_arm_core2_local_status;
+	unsigned int	dis_irq_arm_core2_local_option;
+	unsigned char	res602[0x14];
+	unsigned int	dis_irq_arm_core2_central_configuration;
+	unsigned int	dis_irq_arm_core2_central_status;
+	unsigned int	dis_irq_arm_core2_central_option;
+	unsigned char	res603[0x34];
+	unsigned int	arm_core3_configuration;
+	unsigned int	arm_core3_status;
+	unsigned int	arm_core3_option;
+	unsigned char	res900[0x14];
+	unsigned int	dis_irq_arm_core3_local_configuration;
+	unsigned int	dis_irq_arm_core3_local_status;
+	unsigned int	dis_irq_arm_core3_local_option;
+	unsigned char	res901[0x14];
+	unsigned int	dis_irq_arm_core3_central_configuration;
+	unsigned int	dis_irq_arm_core3_central_status;
+	unsigned int	dis_irq_arm_core3_central_option;
+	unsigned char	res604[0x34];
+	unsigned int	kfc_core0_configuration;
+	unsigned int	kfc_core0_status;
+	unsigned int	kfc_core0_option;
+	unsigned char	res605[0x14];
+	unsigned int	dis_irq_kfc_core0_local_configuration;
+	unsigned int	dis_irq_kfc_core0_local_status;
+	unsigned int	dis_irq_kfc_core0_local_option;
+	unsigned char	res606[0x14];
+	unsigned int	dis_irq_kfc_core0_central_configuration;
+	unsigned int	dis_irq_kfc_core0_central_status;
+	unsigned int	dis_irq_kfc_core0_central_option;
+	unsigned char	res607[0x34];
+	unsigned int	kfc_core1_configuration;
+	unsigned int	kfc_core1_status;
+	unsigned int	kfc_core1_option;
+	unsigned char	res608[0x14];
+	unsigned int	dis_irq_kfc_core1_local_configuration;
+	unsigned int	dis_irq_kfc_core1_local_status;
+	unsigned int	dis_irq_kfc_core1_local_option;
+	unsigned char	res609[0x14];
+	unsigned int	dis_irq_kfc_core1_central_configuration;
+	unsigned int	dis_irq_kfc_core1_central_status;
+	unsigned int	dis_irq_kfc_core1_central_option;
+	unsigned char	res610[0x34];
+	unsigned int	kfc_core2_configuration;
+	unsigned int	kfc_core2_status;
+	unsigned int	kfc_core2_option;
+	unsigned char	res611[0x14];
+	unsigned int	dis_irq_kfc_core2_local_configuration;
+	unsigned int	dis_irq_kfc_core2_local_status;
+	unsigned int	dis_irq_kfc_core2_local_option;
+	unsigned char	res612[0x14];
+	unsigned int	dis_irq_kfc_core2_central_configuration;
+	unsigned int	dis_irq_kfc_core2_central_status;
+	unsigned int	dis_irq_kfc_core2_central_option;
+	unsigned char	res613[0x34];
+	unsigned int	kfc_core3_configuration;
+	unsigned int	kfc_core3_status;
+	unsigned int	kfc_core3_option;
+	unsigned char	res614[0x14];
+	unsigned int	dis_irq_kfc_core3_local_configuration;
+	unsigned int	dis_irq_kfc_core3_local_status;
+	unsigned int	dis_irq_kfc_core3_local_option;
+	unsigned char	res615[0x14];
+	unsigned int	dis_irq_kfc_core3_central_configuration;
+	unsigned int	dis_irq_kfc_core3_central_status;
+	unsigned int	dis_irq_kfc_core3_central_option;
+	unsigned char	res61[0xb4];
+	unsigned int	isp_arm_configuration;
+	unsigned int	isp_arm_status;
+	unsigned int	isp_arm_option;
+	unsigned char	res62[0x14];
+	unsigned int	dis_irq_isp_arm_local_configuration;
+	unsigned int	dis_irq_isp_arm_local_status;
+	unsigned int	dis_irq_isp_arm_local_option;
+	unsigned char	res63[0x14];
+	unsigned int	dis_irq_isp_arm_central_configuration;
+	unsigned int	dis_irq_isp_arm_central_status;
+	unsigned int	dis_irq_isp_arm_central_option;
+	unsigned char	res64[0x34];
+	unsigned int	arm_common_configuration;
+	unsigned int	arm_common_status;
+	unsigned int	arm_common_option;
+	unsigned char	res616[0x74];
+	unsigned int	kfc_common_configuration;
+	unsigned int	kfc_common_status;
+	unsigned int	kfc_common_option;
+	unsigned char	res65[0x74];
+	unsigned int	arm_l2_configuration;
+	unsigned int	arm_l2_status;
+	unsigned int	arm_l2_option;
+	unsigned char	res617[0x74];
+	unsigned int	kfc_l2_configuration;
+	unsigned int	kfc_l2_status;
+	unsigned int	kfc_l2_option;
+	unsigned char	res66[0x74];
+	unsigned int	cmu_cpu_aclkstop_configuration;
+	unsigned int	cmu_cpu_aclkstop_status;
+	unsigned int	cmu_cpu_aclkstop_option;
+	unsigned char	res67[0x14];
+	unsigned int	cmu_cpu_sclkstop_configuration;
+	unsigned int	cmu_cpu_sclkstop_status;
+	unsigned int	cmu_cpu_sclkstop_option;
+	unsigned char	res618[0x4];
+	unsigned int	cmu_kfc_aclkstop_configuration;
+	unsigned int	cmu_kfc_aclkstop_status;
+	unsigned int	cmu_kfc_aclkstop_option;
+	unsigned char	res619[0xc4];
+	unsigned int	cmu_aclkstop_configuration;
+	unsigned int	cmu_aclkstop_status;
+	unsigned int	cmu_aclkstop_option;
+	unsigned char	res620[0x14];
+	unsigned int	cmu_sclkstop_configuration;
+	unsigned int	cmu_sclkstop_status;
+	unsigned int	cmu_sclkstop_option;
+	unsigned char	res68[0x34];
+	unsigned int	cmu_reset_configuration;
+	unsigned int	cmu_reset_status;
+	unsigned int	cmu_reset_option;
+	unsigned char	res69[0x94];
+	unsigned int	cmu_aclkstop_coreblk_configuration;
+	unsigned int	cmu_aclkstop_coreblk_status;
+	unsigned int	cmu_aclkstop_coreblk_option;
+	unsigned char	res70[0x14];
+	unsigned int	cmu_sclkstop_coreblk_configuration;
+	unsigned int	cmu_sclkstop_coreblk_status;
+	unsigned int	cmu_sclkstop_coreblk_option;
+	unsigned char	res71[0x34];
+	unsigned int	cmu_reset_coreblk_configuration;
+	unsigned int	cmu_reset_coreblk_status;
+	unsigned int	cmu_reset_coreblk_option;
+	unsigned char	res621[0x14];
+	unsigned int	dram_freq_down_configuration;
+	unsigned int	dram_freq_down_status;
+	unsigned int	dram_freq_down_option;
+	unsigned char	res622[0x14];
+	unsigned int	ddrphy_dlloff_configuration;
+	unsigned int	ddrphy_dlloff_status;
+	unsigned int	ddrphy_dlloff_option;
+	unsigned char	res72[0x14];
+	unsigned int	ddrphy_dlllock_configuration;
+	unsigned int	ddrphy_dlllock_status;
+	unsigned int	ddrphy_dlllock_option;
+	unsigned char	res73[0x34];
+	unsigned int	apll_sysclk_configuration;
+	unsigned int	apll_sysclk_status;
+	unsigned int	apll_sysclk_option;
+	unsigned char	res74[0x18];
+	unsigned int	mpll_sysclk_status;
+	unsigned int	mpll_sysclk_option;
+	unsigned char	res75[0x14];
+	unsigned int	vpll_sysclk_configuration;
+	unsigned int	vpll_sysclk_status;
+	unsigned int	vpll_sysclk_option;
+	unsigned char	res76[0x14];
+	unsigned int	epll_sysclk_configuration;
+	unsigned int	epll_sysclk_status;
+	unsigned int	epll_sysclk_option;
+	unsigned char	res77[0x14];
+	unsigned int	bpll_sysclk_configuration;
+	unsigned int	bpll_sysclk_status;
+	unsigned int	bpll_sysclk_option;
+	unsigned char	res78[0x14];
+	unsigned int	cpll_sysclk_configuration;
+	unsigned int	cpll_sysclk_status;
+	unsigned int	cpll_sysclk_option;
+	unsigned char	res79[0x14];
+	unsigned int	dpll_sysclk_configuration;
+	unsigned int	dpll_sysclk_status;
+	unsigned int	dpll_sysclk_option;
+	unsigned char	res700[0x14];
+	unsigned int	ipll_sysclk_configuration;
+	unsigned int	ipll_sysclk_status;
+	unsigned int	ipll_sysclk_option;
+	unsigned char	res903[0x14];
+	unsigned int	kpll_sysclk_configuration;
+	unsigned int	kpll_sysclk_status;
+	unsigned int	kpll_sysclk_option;
+	unsigned char	res80[0x14];
+	unsigned int	mplluser_sysclk_configuration;
+	unsigned int	mplluser_sysclk_status;
+	unsigned int	mplluser_sysclk_option;
+	unsigned char	res81[0x54];
+	unsigned int	bplluser_sysclk_configuration;
+	unsigned int	bplluser_sysclk_status;
+	unsigned int	bplluser_sysclk_option;
+	unsigned char	res701[0x14];
+	unsigned int	rplluser_sysclk_configuration;
+	unsigned int	rplluser_sysclk_status;
+	unsigned int	rplluser_sysclk_option;
+	unsigned char	res702[0x14];
+	unsigned int	splluser_sysclk_configuration;
+	unsigned int	splluser_sysclk_status;
+	unsigned int	splluser_sysclk_option;
+	unsigned char	res82[0x34];
+	unsigned int	top_bus_configuration;
+	unsigned int	top_bus_status;
+	unsigned int	top_bus_option;
+	unsigned char	res83[0x14];
+	unsigned int	top_retention_configuration;
+	unsigned int	top_retention_status;
+	unsigned int	top_retention_option;
+	unsigned char	res84[0x14];
+	unsigned int	top_pwr_configuration;
+	unsigned int	top_pwr_status;
+	unsigned int	top_pwr_option;
+	unsigned char	res85[0x34];
+	unsigned int	top_bus_coreblk_configuration;
+	unsigned int	top_bus_coreblk_status;
+	unsigned int	top_bus_coreblk_option;
+	unsigned char	res86[0x14];
+	unsigned int	top_retention_coreblk_configuration;
+	unsigned int	top_retention_coreblk_status;
+	unsigned int	top_retention_coreblk_option;
+	unsigned char	res87[0x14];
+	unsigned int	top_pwr_coreblk_configuration;
+	unsigned int	top_pwr_coreblk_status;
+	unsigned int	top_pwr_coreblk_option;
+	unsigned char	res88[0x34];
+	unsigned int	logic_reset_configuration;
+	unsigned int	logic_reset_status;
+	unsigned int	logic_reset_option;
+	unsigned char	res89[0x14];
+	unsigned int	oscclk_gate_configuration;
+	unsigned int	oscclk_gate_status;
+	unsigned int	oscclk_gate_option;
+	unsigned char	res90[0x54];
+	unsigned int	logic_reset_coreblk_configuration;
+	unsigned int	logic_reset_coreblk_status;
+	unsigned int	logic_reset_coreblk_option;
+	unsigned char	res91[0x14];
+	unsigned int	oscclk_gate_coreblk_configuration;
+	unsigned int	oscclk_gate_coreblk_status;
+	unsigned int	oscclk_gate_coreblk_option;
+	unsigned char	res99[0x174];
+	unsigned int	intram_mem_configuration;
+	unsigned int	intram_mem_status;
+	unsigned int	intram_mem_option;
+	unsigned char	res100[0x14];
+	unsigned int	introm_mem_configuration;
+	unsigned int	introm_mem_status;
+	unsigned int	introm_mem_option;
+	unsigned char	res101[0xb4];
+	unsigned int	pad_retention_dram_configuration;
+	unsigned int	pad_retention_dram_status;
+	unsigned int	pad_retention_dram_option;
+	unsigned char	res106[0x14];
+	unsigned int	pad_retention_mau_configuration;
+	unsigned int	pad_retention_mau_status;
+	unsigned int	pad_retention_mau_option;
+	unsigned char	res107[0x14];
+	unsigned int	pad_retention_jtag_configuration;
+	unsigned int	pad_retention_jtag_status;
+	unsigned int	pad_retention_jtag_option;
+	unsigned char	res92[0x74];
+	unsigned int	pad_retention_dram_configuration_2;
+	unsigned int	pad_retention_dram_status_2;
+	unsigned int	pad_retention_dram_option_2;
+	unsigned char	res111[0x14];
+	unsigned int	pad_retention_uart_configuration;
+	unsigned int	pad_retention_uart_status;
+	unsigned int	pad_retention_uart_option;
+	unsigned char	res112[0x14];
+	unsigned int	pad_retention_mmca_configuration;
+	unsigned int	pad_retention_mmca_status;
+	unsigned int	pad_retention_mmca_option;
+	unsigned char	res113[0x14];
+	unsigned int	pad_retention_mmcb_configuration;
+	unsigned int	pad_retention_mmcb_status;
+	unsigned int	pad_retention_mmcb_option;
+	unsigned char	res93[0x14];
+	unsigned int	pad_retention_mmcc_configuration;
+	unsigned int	pad_retention_mmcc_status;
+	unsigned int	pad_retention_mmcc_option;
+	unsigned char	res94[0x14];
+	unsigned int	pad_retention_hsi_configuration;
+	unsigned int	pad_retention_hsi_status;
+	unsigned int	pad_retention_hsi_option;
+	unsigned char	res114[0x14];
+	unsigned int	pad_retention_ebia_configuration;
+	unsigned int	pad_retention_ebia_status;
+	unsigned int	pad_retention_ebia_option;
+	unsigned char	res115[0x14];
+	unsigned int	pad_retention_ebib_configuration;
+	unsigned int	pad_retention_ebib_status;
+	unsigned int	pad_retention_ebib_option;
+	unsigned char	res116[0x14];
+	unsigned int	pad_retention_spi_configuration;
+	unsigned int	pad_retention_spi_status;
+	unsigned int	pad_retention_spi_option;
+	unsigned char	res117[0x14];
+	unsigned int	pad_retention_dram_coreblk_configuration;
+	unsigned int	pad_retention_dram_coreblk_status;
+	unsigned int	pad_retention_dram_coreblk_option;
+	unsigned char	res118[0x14];
+	unsigned int	pad_isolation_configuration;
+	unsigned int	pad_isolation_status;
+	unsigned int	pad_isolation_option;
+	unsigned char	res119[0x74];
+	unsigned int	pad_isolation_coreblk_configuration;
+	unsigned int	pad_isolation_coreblk_status;
+	unsigned int	pad_isolation_coreblk_option;
+	unsigned char	res120[0x74];
+	unsigned int	pad_alv_sel_configuration;
+	unsigned int	pad_alv_sel_status;
+	unsigned int	pad_alv_sel_option0;
+	unsigned int	ps_hold_control;
+	unsigned char	res130[0xf0];
+	unsigned int	xusbxti_configuration;
+	unsigned int	xusbxti_status;
+	unsigned int	xusbxti_option;
+	unsigned char	res910[0x10];
+	unsigned int	xusbxti_duration3;
+	unsigned int	xxti_configuration;
+	unsigned int	xxti_status;
+	unsigned int	xxti_option;
+	unsigned char	res131[0x10];
+	unsigned int	xxti_duration3;
+	unsigned char	res132[0x1c0];
+	unsigned int	ext_regulator_configuration;
+	unsigned int	ext_regulator_status;
+	unsigned int	ext_regulator_option;
+	unsigned char	res133[0x10];
+	unsigned int	ext_regulator_duration3;
+	unsigned char	res134[0x1e0];
+	unsigned int	gpio_mode_configuration;
+	unsigned int	gpio_mode_status;
+	unsigned int	gpio_mode_option;
+	unsigned char	res135[0xf4];
+	unsigned int	gpio_mode_coreblk_configuration;
+	unsigned int	gpio_mode_coreblk_status;
+	unsigned int	gpio_mode_coreblk_option;
+	unsigned char	res136[0xd4];
+	unsigned int	gpio_mode_mau_configuration;
+	unsigned int	gpio_mode_mau_status;
+	unsigned int	gpio_mode_mau_option;
+	unsigned char	res137[0x14];
+	unsigned int	top_asb_reset_configuration;
+	unsigned int	top_asb_reset_status;
+	unsigned int	top_asb_reset_option;
+	unsigned char	res138[0x14];
+	unsigned int	top_asb_isolation_configuration;
+	unsigned int	top_asb_isolation_status;
+	unsigned int	top_asb_isolation_option;
+	unsigned char	res139[0x5d4];
+	unsigned int	gscl_configuration;
+	unsigned int	gscl_status;
+	unsigned int	gscl_option;
+	unsigned char	res140[0x14];
+	unsigned int	isp_configuration;
+	unsigned int	isp_status;
+	unsigned int	isp_option;
+	unsigned char	res141[0x34];
+	unsigned int	mfc_configuration;
+	unsigned int	mfc_status;
+	unsigned int	mfc_option;
+	unsigned char	res142[0x14];
+	unsigned int	g3d_configuration;
+	unsigned int	g3d_status;
+	unsigned int	g3d_option;
+	unsigned char	res143[0x34];
+	unsigned int	disp1_configuration;
+	unsigned int	disp1_status;
+	unsigned int	disp1_option;
+	unsigned char	res144[0x14];
+	unsigned int	mau_configuration;
+	unsigned int	mau_status;
+	unsigned int	mau_option;
+	unsigned char	res800[0x14];
+	unsigned int	g2d_configuration;
+	unsigned int	g2d_status;
+	unsigned int	g2d_option;
+	unsigned char	res801[0x14];
+	unsigned int	msc_configuration;
+	unsigned int	msc_status;
+	unsigned int	msc_option;
+	unsigned char	res802[0x14];
+	unsigned int	fsys_configuration;
+	unsigned int	fsys_status;
+	unsigned int	fsys_option;
+	unsigned char	res803[0x14];
+	unsigned int	fsys2_configuration;
+	unsigned int	fsys2_status;
+	unsigned int	fsys2_option;
+	unsigned char	res804[0x14];
+	unsigned int	psgen_configuration;
+	unsigned int	psgen_status;
+	unsigned int	psgen_option;
+	unsigned char	res805[0x14];
+	unsigned int	peric_configuration;
+	unsigned int	peric_status;
+	unsigned int	peric_option;
+	unsigned char	res806[0x14];
+	unsigned int	wcore_configuration;
+	unsigned int	wcore_status;
+	unsigned int	wcore_option;
+	unsigned char	res145[0x234];
+	unsigned int	cmu_clkstop_gscl_configuration;
+	unsigned int	cmu_clkstop_gscl_status;
+	unsigned int	cmu_clkstop_gscl_option;
+	unsigned char	res146[0x14];
+	unsigned int	cmu_clkstop_isp_configuration;
+	unsigned int	cmu_clkstop_isp_status;
+	unsigned int	cmu_clkstop_isp_option;
+	unsigned char	res147[0x34];
+	unsigned int	cmu_clkstop_mfc_configuration;
+	unsigned int	cmu_clkstop_mfc_status;
+	unsigned int	cmu_clkstop_mfc_option;
+	unsigned char	res148[0x14];
+	unsigned int	cmu_clkstop_g3d_configuration;
+	unsigned int	cmu_clkstop_g3d_status;
+	unsigned int	cmu_clkstop_g3d_option;
+	unsigned char	res149[0x34];
+	unsigned int	cmu_clkstop_disp1_configuration;
+	unsigned int	cmu_clkstop_disp1_status;
+	unsigned int	cmu_clkstop_disp1_option;
+	unsigned char	res150[0x14];
+	unsigned int	cmu_clkstop_mau_configuration;
+	unsigned int	cmu_clkstop_mau_status;
+	unsigned int	cmu_clkstop_mau_option;
+	unsigned char	res807[0x14];
+	unsigned int	cmu_clkstop_g2d_configuration;
+	unsigned int	cmu_clkstop_g2d_status;
+	unsigned int	cmu_clkstop_g2d_option;
+	unsigned char	res808[0x14];
+	unsigned int	cmu_clkstop_msc_configuration;
+	unsigned int	cmu_clkstop_msc_status;
+	unsigned int	cmu_clkstop_msc_option;
+	unsigned char	res809[0x14];
+	unsigned int	cmu_clkstop_fsys_configuration;
+	unsigned int	cmu_clkstop_fsys_status;
+	unsigned int	cmu_clkstop_fsys_option;
+	unsigned char	res810[0x14];
+	unsigned int	cmu_clkstop_fsys2_configuration;
+	unsigned int	cmu_clkstop_fsys2_status;
+	unsigned int	cmu_clkstop_fsys2_option;
+	unsigned char	res811[0x14];
+	unsigned int	cmu_clkstop_psgen_configuration;
+	unsigned int	cmu_clkstop_psgen_status;
+	unsigned int	cmu_clkstop_psgen_option;
+	unsigned char	res812[0x14];
+	unsigned int	cmu_clkstop_peric_configuration;
+	unsigned int	cmu_clkstop_peric_status;
+	unsigned int	cmu_clkstop_peric_option;
+	unsigned char	res813[0x14];
+	unsigned int	cmu_clkstop_wcore_configuration;
+	unsigned int	cmu_clkstop_wcore_status;
+	unsigned int	cmu_clkstop_wcore_option;
+	unsigned char	res151[0x14];
+	unsigned int	cmu_sysclk_toppwr_configuration;
+	unsigned int	cmu_sysclk_toppwr_status;
+	unsigned int	cmu_sysclk_toppwr_option;
+	unsigned char	res920[0x18];
+	unsigned int	cmu_sysclk_gscl_status;
+	unsigned int	cmu_sysclk_gscl_option;
+	unsigned char	res152[0x18];
+	unsigned int	cmu_sysclk_isp_status;
+	unsigned int	cmu_sysclk_isp_option;
+	unsigned char	res153[0x38];
+	unsigned int	cmu_sysclk_mfc_status;
+	unsigned int	cmu_sysclk_mfc_option;
+	unsigned char	res154[0x18];
+	unsigned int	cmu_sysclk_g3d_status;
+	unsigned int	cmu_sysclk_g3d_option;
+	unsigned char	res155[0x38];
+	unsigned int	cmu_sysclk_disp1_status;
+	unsigned int	cmu_sysclk_disp1_option;
+	unsigned char	res156[0x18];
+	unsigned int	cmu_sysclk_mau_status;
+	unsigned int	cmu_sysclk_mau_option;
+	unsigned char	res814[0x18];
+	unsigned int	cmu_sysclk_g2d_status;
+	unsigned int	cmu_sysclk_g2d_option;
+	unsigned char	res815[0x18];
+	unsigned int	cmu_sysclk_msc_status;
+	unsigned int	cmu_sysclk_msc_option;
+	unsigned char	res922[0x18];
+	unsigned int	cmu_sysclk_fsys_status;
+	unsigned int	cmu_sysclk_fsys_option;
+	unsigned char	res816[0x18];
+	unsigned int	cmu_sysclk_fsys2_status;
+	unsigned int	cmu_sysclk_fsys2_option;
+	unsigned char	res817[0x18];
+	unsigned int	cmu_sysclk_psgen_status;
+	unsigned int	cmu_sysclk_psgen_option;
+	unsigned char	res950[0x18];
+	unsigned int	cmu_sysclk_peric_status;
+	unsigned int	cmu_sysclk_peric_option;
+	unsigned char	res818[0x18];
+	unsigned int	cmu_sysclk_wcore_status;
+	unsigned int	cmu_sysclk_wcore_option;
+	unsigned char	res819[0x18];
+	unsigned int	cmu_sysclk_coreblk_toppwr_status;
+	unsigned int	cmu_sysclk_coreblk_toppwr_option;
+	unsigned char	res157[0x414];
+	unsigned int	cmu_reset_gscl_configuration;
+	unsigned int	cmu_reset_gscl_status;
+	unsigned int	cmu_reset_gscl_option;
+	unsigned char	res158[0x14];
+	unsigned int	cmu_reset_isp_configuration;
+	unsigned int	cmu_reset_isp_status;
+	unsigned int	cmu_reset_isp_option;
+	unsigned char	res159[0x34];
+	unsigned int	cmu_reset_mfc_configuration;
+	unsigned int	cmu_reset_mfc_status;
+	unsigned int	cmu_reset_mfc_option;
+	unsigned char	res160[0x14];
+	unsigned int	cmu_reset_g3d_configuration;
+	unsigned int	cmu_reset_g3d_status;
+	unsigned int	cmu_reset_g3d_option;
+	unsigned char	res161[0x34];
+	unsigned int	cmu_reset_disp1_configuration;
+	unsigned int	cmu_reset_disp1_status;
+	unsigned int	cmu_reset_disp1_option;
+	unsigned char	res162[0x14];
+	unsigned int	cmu_reset_mau_configuration;
+	unsigned int	cmu_reset_mau_status;
+	unsigned int	cmu_reset_mau_option;
+	unsigned char	res163[0x14];
+	unsigned int	version_info;
+	unsigned int	i2s_bypass;
+	unsigned int	kfc_swreset_mask_from_eagle;
+	unsigned char	res164[0xf4];
+	unsigned int	cmu_reset_g2d_configuration;
+	unsigned int	cmu_reset_g2d_status;
+	unsigned int	cmu_reset_g2d_option;
+	unsigned char	res165[0x14];
+	unsigned int	cmu_reset_msc_configuration;
+	unsigned int	cmu_reset_msc_status;
+	unsigned int	cmu_reset_msc_option;
+	unsigned char	res166[0x14];
+	unsigned int	cmu_reset_fsys_configuration;
+	unsigned int	cmu_reset_fsys_status;
+	unsigned int	cmu_reset_fsys_option;
+	unsigned char	res167[0x14];
+	unsigned int	cmu_reset_fsys2_configuration;
+	unsigned int	cmu_reset_fsys2_status;
+	unsigned int	cmu_reset_fsys2_option;
+	unsigned char	res168[0x14];
+	unsigned int	cmu_reset_psgen_configuration;
+	unsigned int	cmu_reset_psgen_status;
+	unsigned int	cmu_reset_psgen_option;
+	unsigned char	res169[0x14];
+	unsigned int	cmu_reset_peric_configuration;
+	unsigned int	cmu_reset_peric_status;
+	unsigned int	cmu_reset_peric_option;
+	unsigned char	res170[0x14];
+	unsigned int	cmu_reset_wcore_configuration;
+	unsigned int	cmu_reset_wcore_status;
+	unsigned int	cmu_reset_wcore_option;
+};
 #endif	/* __ASSEMBLY__ */
 
 void set_mipi_phy_ctrl(unsigned int dev_index, unsigned int enable);
@@ -847,6 +1684,11 @@ void set_hw_thermal_trip(void);
 #define POWER_USB_HOST_PHY_CTRL_EN		(1 << 0)
 #define POWER_USB_HOST_PHY_CTRL_DISABLE		(0 << 0)
 
+void set_usbdrd_phy_ctrl(unsigned int enable);
+
+#define POWER_USB_DRD_PHY_CTRL_EN		(1 << 0)
+#define POWER_USB_DRD_PHY_CTRL_DISABLE		(0 << 0)
+
 void set_dp_phy_ctrl(unsigned int enable);
 
 #define EXYNOS_DP_PHY_ENABLE		(1 << 0)
diff --git a/arch/arm/include/asm/arch-exynos/spi.h b/arch/arm/include/asm/arch-exynos/spi.h
index 147c1a7304..0ba931b7e3 100644
--- a/arch/arm/include/asm/arch-exynos/spi.h
+++ b/arch/arm/include/asm/arch-exynos/spi.h
@@ -30,6 +30,7 @@ struct exynos_spi {
 #define EXYNOS_SPI_MAX_FREQ	50000000
 
 #define SPI_TIMEOUT_MS		10
+#define SF_READ_DATA_CMD	0x3
 
 /* SPI_CHCFG */
 #define SPI_CH_HS_EN		(1 << 6)
diff --git a/arch/arm/include/asm/arch-exynos/xhci-exynos.h b/arch/arm/include/asm/arch-exynos/xhci-exynos.h
new file mode 100644
index 0000000000..92b90a462c
--- /dev/null
+++ b/arch/arm/include/asm/arch-exynos/xhci-exynos.h
@@ -0,0 +1,88 @@
+/* Copyright (c) 2012 Samsung Electronics Co. Ltd
+ *
+ * Exynos Phy register definitions
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _ASM_ARCH_XHCI_EXYNOS_H_
+#define _ASM_ARCH_XHCI_EXYNOS_H_
+
+/* Phy register MACRO definitions */
+
+#define LINKSYSTEM_FLADJ_MASK			(0x3f << 1)
+#define LINKSYSTEM_FLADJ(_x)			((_x) << 1)
+#define LINKSYSTEM_XHCI_VERSION_CONTROL		(0x1 << 27)
+
+#define PHYUTMI_OTGDISABLE			(1 << 6)
+#define PHYUTMI_FORCESUSPEND			(1 << 1)
+#define PHYUTMI_FORCESLEEP			(1 << 0)
+
+#define PHYCLKRST_SSC_REFCLKSEL_MASK		(0xff << 23)
+#define PHYCLKRST_SSC_REFCLKSEL(_x)		((_x) << 23)
+
+#define PHYCLKRST_SSC_RANGE_MASK		(0x03 << 21)
+#define PHYCLKRST_SSC_RANGE(_x)			((_x) << 21)
+
+#define PHYCLKRST_SSC_EN			(0x1 << 20)
+#define PHYCLKRST_REF_SSP_EN			(0x1 << 19)
+#define PHYCLKRST_REF_CLKDIV2			(0x1 << 18)
+
+#define PHYCLKRST_MPLL_MULTIPLIER_MASK		(0x7f << 11)
+#define PHYCLKRST_MPLL_MULTIPLIER_100MHZ_REF	(0x19 << 11)
+#define PHYCLKRST_MPLL_MULTIPLIER_50M_REF	(0x02 << 11)
+#define PHYCLKRST_MPLL_MULTIPLIER_24MHZ_REF	(0x68 << 11)
+#define PHYCLKRST_MPLL_MULTIPLIER_20MHZ_REF	(0x7d << 11)
+#define PHYCLKRST_MPLL_MULTIPLIER_19200KHZ_REF	(0x02 << 11)
+
+#define PHYCLKRST_FSEL_MASK			(0x3f << 5)
+#define PHYCLKRST_FSEL(_x)			((_x) << 5)
+#define PHYCLKRST_FSEL_PAD_100MHZ		(0x27 << 5)
+#define PHYCLKRST_FSEL_PAD_24MHZ		(0x2a << 5)
+#define PHYCLKRST_FSEL_PAD_20MHZ		(0x31 << 5)
+#define PHYCLKRST_FSEL_PAD_19_2MHZ		(0x38 << 5)
+
+#define PHYCLKRST_RETENABLEN			(0x1 << 4)
+
+#define PHYCLKRST_REFCLKSEL_MASK		(0x03 << 2)
+#define PHYCLKRST_REFCLKSEL_PAD_REFCLK		(0x2 << 2)
+#define PHYCLKRST_REFCLKSEL_EXT_REFCLK		(0x3 << 2)
+
+#define PHYCLKRST_PORTRESET			(0x1 << 1)
+#define PHYCLKRST_COMMONONN			(0x1 << 0)
+
+#define PHYPARAM0_REF_USE_PAD			(0x1 << 31)
+#define PHYPARAM0_REF_LOSLEVEL_MASK		(0x1f << 26)
+#define PHYPARAM0_REF_LOSLEVEL			(0x9 << 26)
+
+#define PHYPARAM1_PCS_TXDEEMPH_MASK		(0x1f << 0)
+#define PHYPARAM1_PCS_TXDEEMPH			(0x1c)
+
+#define PHYTEST_POWERDOWN_SSP			(0x1 << 3)
+#define PHYTEST_POWERDOWN_HSP			(0x1 << 2)
+
+#define PHYBATCHG_UTMI_CLKSEL			(0x1 << 2)
+
+#define FSEL_CLKSEL_24M				(0x5)
+
+/* XHCI PHY register structure */
+struct exynos_usb3_phy {
+	unsigned int reserve1;
+	unsigned int link_system;
+	unsigned int phy_utmi;
+	unsigned int phy_pipe;
+	unsigned int phy_clk_rst;
+	unsigned int phy_reg0;
+	unsigned int phy_reg1;
+	unsigned int phy_param0;
+	unsigned int phy_param1;
+	unsigned int phy_term;
+	unsigned int phy_test;
+	unsigned int phy_adp;
+	unsigned int phy_batchg;
+	unsigned int phy_resume;
+	unsigned int reserve2[3];
+	unsigned int link_port;
+};
+
+#endif /* _ASM_ARCH_XHCI_EXYNOS_H_ */
diff --git a/arch/arm/include/asm/arch-imx/cpu.h b/arch/arm/include/asm/arch-imx/cpu.h
new file mode 100644
index 0000000000..a35940e64f
--- /dev/null
+++ b/arch/arm/include/asm/arch-imx/cpu.h
@@ -0,0 +1,13 @@
+/*
+ * (C) Copyright 2014 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#define MXC_CPU_MX51		0x51
+#define MXC_CPU_MX53		0x53
+#define MXC_CPU_MX6SL		0x60
+#define MXC_CPU_MX6DL		0x61
+#define MXC_CPU_MX6SOLO		0x62
+#define MXC_CPU_MX6Q		0x63
+#define MXC_CPU_MX6D		0x64
diff --git a/arch/arm/include/asm/arch-ixp/ixp425.h b/arch/arm/include/asm/arch-ixp/ixp425.h
deleted file mode 100644
index c2e9c82049..0000000000
--- a/arch/arm/include/asm/arch-ixp/ixp425.h
+++ /dev/null
@@ -1,548 +0,0 @@
-/*
- * include/asm-arm/arch-ixp425/ixp425.h
- *
- * Register definitions for IXP425
- *
- * Copyright (C) 2002 Intel Corporation.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- */
-
-#ifndef _ASM_ARM_IXP425_H_
-#define _ASM_ARM_IXP425_H_
-
-#define BIT(x)	(1<<(x))
-
-/* FIXME: Only this does work for u-boot... find out why... [RS] */
-#define UBOOT_REG_FIX 1
-#ifdef UBOOT_REG_FIX
-# undef	io_p2v
-# undef __REG
-# ifndef __ASSEMBLY__
-#  define io_p2v(PhAdd)    (PhAdd)
-#  define __REG(x)	(*((volatile u32 *)io_p2v(x)))
-#  define __REG2(x,y)	(*(volatile u32 *)((u32)&__REG(x) + (y)))
-# else
-#  define __REG(x) (x)
-# endif
-#endif /* UBOOT_REG_FIX */
-
-/*
- *
- * IXP425 Memory map:
- *
- * Phy		Phy Size	Map Size	Virt		Description
- * =========================================================================
- *
- * 0x00000000	0x10000000					SDRAM 1
- *
- * 0x10000000	0x10000000					SDRAM 2
- *
- * 0x20000000	0x10000000					SDRAM 3
- *
- * 0x30000000	0x10000000					SDRAM 4
- *
- * The above four are aliases to the same memory location  (0x00000000)
- *
- * 0x48000000	 0x4000000					PCI Memory
- *
- * 0x50000000	0x10000000			Not Mapped	EXP BUS
- *
- * 0x6000000	0x00004000	    0x4000	0xFFFEB000	QMgr
- *
- * 0xC0000000	     0x100	    0x1000	0xFFFDD000	PCI CFG
- *
- * 0xC4000000	     0x100          0x1000	0xFFFDE000	EXP CFG
- *
- * 0xC8000000	    0xC000          0xC000	0xFFFDF000	PERIPHERAL
- *
- * 0xCC000000	     0x100	    0x1000	Not Mapped	SDRAM CFG
- */
-
-/*
- * SDRAM
- */
-#define IXP425_SDRAM_BASE		(0x00000000)
-#define IXP425_SDRAM_BASE_ALT		(0x10000000)
-
-
-/*
- * PCI Configuration space
- */
-#define IXP425_PCI_CFG_BASE_PHYS	(0xC0000000)
-#define IXP425_PCI_CFG_REGION_SIZE	(0x00001000)
-
-/*
- * Expansion BUS Configuration registers
- */
-#define IXP425_EXP_CFG_BASE_PHYS	(0xC4000000)
-#define IXP425_EXP_CFG_REGION_SIZE	(0x00001000)
-
-/*
- * Peripheral space
- */
-#define IXP425_PERIPHERAL_BASE_PHYS	(0xC8000000)
-#define IXP425_PERIPHERAL_REGION_SIZE	(0x0000C000)
-
-/*
- * SDRAM configuration registers
- */
-#define IXP425_SDRAM_CFG_BASE_PHYS	(0xCC000000)
-
-/*
- * Q Manager space .. not static mapped
- */
-#define IXP425_QMGR_BASE_PHYS		(0x60000000)
-#define IXP425_QMGR_REGION_SIZE		(0x00004000)
-
-/*
- * Expansion BUS
- *
- * Expansion Bus 'lives' at either base1 or base 2 depending on the value of
- * Exp Bus config registers:
- *
- * Setting bit 31 of IXP425_EXP_CFG0 puts SDRAM at zero,
- * and The expansion bus to IXP425_EXP_BUS_BASE2
- */
-#define IXP425_EXP_BUS_BASE1_PHYS	(0x00000000)
-#define IXP425_EXP_BUS_BASE2_PHYS	(0x50000000)
-
-#define IXP425_EXP_BUS_BASE_PHYS	IXP425_EXP_BUS_BASE2_PHYS
-
-#define IXP425_EXP_BUS_REGION_SIZE	(0x08000000)
-#define IXP425_EXP_BUS_CSX_REGION_SIZE	(0x01000000)
-
-#define IXP425_EXP_BUS_CS0_BASE_PHYS	(IXP425_EXP_BUS_BASE2_PHYS + 0x00000000)
-#define IXP425_EXP_BUS_CS1_BASE_PHYS	(IXP425_EXP_BUS_BASE2_PHYS + 0x01000000)
-#define IXP425_EXP_BUS_CS2_BASE_PHYS	(IXP425_EXP_BUS_BASE2_PHYS + 0x02000000)
-#define IXP425_EXP_BUS_CS3_BASE_PHYS	(IXP425_EXP_BUS_BASE2_PHYS + 0x03000000)
-#define IXP425_EXP_BUS_CS4_BASE_PHYS	(IXP425_EXP_BUS_BASE2_PHYS + 0x04000000)
-#define IXP425_EXP_BUS_CS5_BASE_PHYS	(IXP425_EXP_BUS_BASE2_PHYS + 0x05000000)
-#define IXP425_EXP_BUS_CS6_BASE_PHYS	(IXP425_EXP_BUS_BASE2_PHYS + 0x06000000)
-#define IXP425_EXP_BUS_CS7_BASE_PHYS	(IXP425_EXP_BUS_BASE2_PHYS + 0x07000000)
-
-#define IXP425_FLASH_WRITABLE	(0x2)
-#define IXP425_FLASH_DEFAULT	(0xbcd23c40)
-#define IXP425_FLASH_WRITE	(0xbcd23c42)
-
-#define IXP425_EXP_CS0_OFFSET	0x00
-#define IXP425_EXP_CS1_OFFSET   0x04
-#define IXP425_EXP_CS2_OFFSET   0x08
-#define IXP425_EXP_CS3_OFFSET   0x0C
-#define IXP425_EXP_CS4_OFFSET   0x10
-#define IXP425_EXP_CS5_OFFSET   0x14
-#define IXP425_EXP_CS6_OFFSET   0x18
-#define IXP425_EXP_CS7_OFFSET   0x1C
-#define IXP425_EXP_CFG0_OFFSET	0x20
-#define IXP425_EXP_CFG1_OFFSET	0x24
-#define IXP425_EXP_CFG2_OFFSET	0x28
-#define IXP425_EXP_CFG3_OFFSET	0x2C
-
-/*
- * Expansion Bus Controller registers.
- */
-#ifndef __ASSEMBLY__
-#define IXP425_EXP_REG(x) ((volatile u32 *)(IXP425_EXP_CFG_BASE_PHYS+(x)))
-#else
-#define IXP425_EXP_REG(x) (IXP425_EXP_CFG_BASE_PHYS+(x))
-#endif
-
-#define IXP425_EXP_CS0      IXP425_EXP_REG(IXP425_EXP_CS0_OFFSET)
-#define IXP425_EXP_CS1      IXP425_EXP_REG(IXP425_EXP_CS1_OFFSET)
-#define IXP425_EXP_CS2      IXP425_EXP_REG(IXP425_EXP_CS2_OFFSET)
-#define IXP425_EXP_CS3      IXP425_EXP_REG(IXP425_EXP_CS3_OFFSET)
-#define IXP425_EXP_CS4      IXP425_EXP_REG(IXP425_EXP_CS4_OFFSET)
-#define IXP425_EXP_CS5      IXP425_EXP_REG(IXP425_EXP_CS5_OFFSET)
-#define IXP425_EXP_CS6      IXP425_EXP_REG(IXP425_EXP_CS6_OFFSET)
-#define IXP425_EXP_CS7      IXP425_EXP_REG(IXP425_EXP_CS7_OFFSET)
-
-#define IXP425_EXP_CFG0     IXP425_EXP_REG(IXP425_EXP_CFG0_OFFSET)
-#define IXP425_EXP_CFG1     IXP425_EXP_REG(IXP425_EXP_CFG1_OFFSET)
-#define IXP425_EXP_CFG2     IXP425_EXP_REG(IXP425_EXP_CFG2_OFFSET)
-#define IXP425_EXP_CFG3     IXP425_EXP_REG(IXP425_EXP_CFG3_OFFSET)
-
-/*
- * SDRAM Controller registers.
- */
-#define IXP425_SDR_CONFIG_OFFSET	0x00
-#define IXP425_SDR_REFRESH_OFFSET	0x04
-#define IXP425_SDR_IR_OFFSET		0x08
-
-#define IXP425_SDRAM_REG(x)	(IXP425_SDRAM_CFG_BASE_PHYS+(x))
-
-#define IXP425_SDR_CONFIG	IXP425_SDRAM_REG(IXP425_SDR_CONFIG_OFFSET)
-#define IXP425_SDR_REFRESH	IXP425_SDRAM_REG(IXP425_SDR_REFRESH_OFFSET)
-#define IXP425_SDR_IR		IXP425_SDRAM_REG(IXP425_SDR_IR_OFFSET)
-
-/*
- * UART registers
- */
-#define IXP425_UART1		0
-#define IXP425_UART2		0x1000
-
-#define IXP425_UART_RBR_OFFSET	0x00
-#define IXP425_UART_THR_OFFSET	0x00
-#define IXP425_UART_DLL_OFFSET	0x00
-#define IXP425_UART_IER_OFFSET	0x04
-#define IXP425_UART_DLH_OFFSET	0x04
-#define IXP425_UART_IIR_OFFSET	0x08
-#define IXP425_UART_FCR_OFFSET	0x00
-#define IXP425_UART_LCR_OFFSET	0x0c
-#define IXP425_UART_MCR_OFFSET	0x10
-#define IXP425_UART_LSR_OFFSET	0x14
-#define IXP425_UART_MSR_OFFSET	0x18
-#define IXP425_UART_SPR_OFFSET	0x1c
-#define IXP425_UART_ISR_OFFSET	0x20
-
-#define IXP425_UART_CFG_BASE_PHYS	(0xc8000000)
-
-#define RBR(x)		__REG(IXP425_UART_CFG_BASE_PHYS+(x)+IXP425_UART_RBR_OFFSET)
-#define THR(x)		__REG(IXP425_UART_CFG_BASE_PHYS+(x)+IXP425_UART_THR_OFFSET)
-#define DLL(x)		__REG(IXP425_UART_CFG_BASE_PHYS+(x)+IXP425_UART_DLL_OFFSET)
-#define IER(x)		__REG(IXP425_UART_CFG_BASE_PHYS+(x)+IXP425_UART_IER_OFFSET)
-#define DLH(x)		__REG(IXP425_UART_CFG_BASE_PHYS+(x)+IXP425_UART_DLH_OFFSET)
-#define IIR(x)		__REG(IXP425_UART_CFG_BASE_PHYS+(x)+IXP425_UART_IIR_OFFSET)
-#define FCR(x)		__REG(IXP425_UART_CFG_BASE_PHYS+(x)+IXP425_UART_FCR_OFFSET)
-#define LCR(x)		__REG(IXP425_UART_CFG_BASE_PHYS+(x)+IXP425_UART_LCR_OFFSET)
-#define MCR(x)		__REG(IXP425_UART_CFG_BASE_PHYS+(x)+IXP425_UART_MCR_OFFSET)
-#define LSR(x)		__REG(IXP425_UART_CFG_BASE_PHYS+(x)+IXP425_UART_LSR_OFFSET)
-#define MSR(x)		__REG(IXP425_UART_CFG_BASE_PHYS+(x)+IXP425_UART_MSR_OFFSET)
-#define SPR(x)		__REG(IXP425_UART_CFG_BASE_PHYS+(x)+IXP425_UART_SPR_OFFSET)
-#define ISR(x)		__REG(IXP425_UART_CFG_BASE_PHYS+(x)+IXP425_UART_ISR_OFFSET)
-
-#define IER_DMAE	(1 << 7)	/* DMA Requests Enable */
-#define IER_UUE		(1 << 6)	/* UART Unit Enable */
-#define IER_NRZE	(1 << 5)	/* NRZ coding Enable */
-#define IER_RTIOE	(1 << 4)	/* Receiver Time Out Interrupt Enable */
-#define IER_MIE		(1 << 3)	/* Modem Interrupt Enable */
-#define IER_RLSE	(1 << 2)	/* Receiver Line Status Interrupt Enable */
-#define IER_TIE		(1 << 1)	/* Transmit Data request Interrupt Enable */
-#define IER_RAVIE	(1 << 0)	/* Receiver Data Available Interrupt Enable */
-
-#define IIR_FIFOES1	(1 << 7)	/* FIFO Mode Enable Status */
-#define IIR_FIFOES0	(1 << 6)	/* FIFO Mode Enable Status */
-#define IIR_TOD		(1 << 3)	/* Time Out Detected */
-#define IIR_IID2	(1 << 2)	/* Interrupt Source Encoded */
-#define IIR_IID1	(1 << 1)	/* Interrupt Source Encoded */
-#define IIR_IP		(1 << 0)	/* Interrupt Pending (active low) */
-
-#define FCR_ITL2	(1 << 7)	/* Interrupt Trigger Level */
-#define FCR_ITL1	(1 << 6)	/* Interrupt Trigger Level */
-#define FCR_RESETTF	(1 << 2)	/* Reset Transmitter FIFO */
-#define FCR_RESETRF	(1 << 1)	/* Reset Receiver FIFO */
-#define FCR_TRFIFOE	(1 << 0)	/* Transmit and Receive FIFO Enable */
-#define FCR_ITL_1	(0)
-#define FCR_ITL_8	(FCR_ITL1)
-#define FCR_ITL_16	(FCR_ITL2)
-#define FCR_ITL_32	(FCR_ITL2|FCR_ITL1)
-
-#define LCR_DLAB	(1 << 7)	/* Divisor Latch Access Bit */
-#define LCR_SB		(1 << 6)	/* Set Break */
-#define LCR_STKYP	(1 << 5)	/* Sticky Parity */
-#define LCR_EPS		(1 << 4)	/* Even Parity Select */
-#define LCR_PEN		(1 << 3)	/* Parity Enable */
-#define LCR_STB		(1 << 2)	/* Stop Bit */
-#define LCR_WLS1	(1 << 1)	/* Word Length Select */
-#define LCR_WLS0	(1 << 0)	/* Word Length Select */
-
-#define LSR_FIFOE	(1 << 7)	/* FIFO Error Status */
-#define LSR_TEMT	(1 << 6)	/* Transmitter Empty */
-#define LSR_TDRQ	(1 << 5)	/* Transmit Data Request */
-#define LSR_BI		(1 << 4)	/* Break Interrupt */
-#define LSR_FE		(1 << 3)	/* Framing Error */
-#define LSR_PE		(1 << 2)	/* Parity Error */
-#define LSR_OE		(1 << 1)	/* Overrun Error */
-#define LSR_DR		(1 << 0)	/* Data Ready */
-
-#define MCR_LOOP	(1 << 4)	*/
-#define MCR_OUT2	(1 << 3)	/* force MSR_DCD in loopback mode */
-#define MCR_OUT1	(1 << 2)	/* force MSR_RI in loopback mode */
-#define MCR_RTS		(1 << 1)	/* Request to Send */
-#define MCR_DTR		(1 << 0)	/* Data Terminal Ready */
-
-#define MSR_DCD		(1 << 7)	/* Data Carrier Detect */
-#define MSR_RI		(1 << 6)	/* Ring Indicator */
-#define MSR_DSR		(1 << 5)	/* Data Set Ready */
-#define MSR_CTS		(1 << 4)	/* Clear To Send */
-#define MSR_DDCD	(1 << 3)	/* Delta Data Carrier Detect */
-#define MSR_TERI	(1 << 2)	/* Trailing Edge Ring Indicator */
-#define MSR_DDSR	(1 << 1)	/* Delta Data Set Ready */
-#define MSR_DCTS	(1 << 0)	/* Delta Clear To Send */
-
-#define IXP425_CONSOLE_UART_BASE_PHYS IXP425_UART1_BASE_PHYS
-/*
- * Peripheral Space Registers
- */
-#define IXP425_UART1_BASE_PHYS	(IXP425_PERIPHERAL_BASE_PHYS + 0x0000)
-#define IXP425_UART2_BASE_PHYS	(IXP425_PERIPHERAL_BASE_PHYS + 0x1000)
-#define IXP425_PMU_BASE_PHYS	(IXP425_PERIPHERAL_BASE_PHYS + 0x2000)
-#define IXP425_INTC_BASE_PHYS	(IXP425_PERIPHERAL_BASE_PHYS + 0x3000)
-#define IXP425_GPIO_BASE_PHYS	(IXP425_PERIPHERAL_BASE_PHYS + 0x4000)
-#define IXP425_TIMER_BASE_PHYS	(IXP425_PERIPHERAL_BASE_PHYS + 0x5000)
-#define IXP425_NPEA_BASE_PHYS	(IXP425_PERIPHERAL_BASE_PHYS + 0x6000)
-#define IXP425_NPEB_BASE_PHYS	(IXP425_PERIPHERAL_BASE_PHYS + 0x7000)
-#define IXP425_NPEC_BASE_PHYS	(IXP425_PERIPHERAL_BASE_PHYS + 0x8000)
-#define IXP425_EthA_BASE_PHYS	(IXP425_PERIPHERAL_BASE_PHYS + 0x9000)
-#define IXP425_EthB_BASE_PHYS	(IXP425_PERIPHERAL_BASE_PHYS + 0xA000)
-#define IXP425_USB_BASE_PHYS	(IXP425_PERIPHERAL_BASE_PHYS + 0xB000)
-
-/*
- * UART Register Definitions , Offsets only as there are 2 UARTS.
- *   IXP425_UART1_BASE , IXP425_UART2_BASE.
- */
-
-#undef  UART_NO_RX_INTERRUPT
-
-#define IXP425_UART_XTAL        14745600
-
-/*
- * Constants to make it easy to access  Interrupt Controller registers
- */
-#define IXP425_ICPR_OFFSET	0x00 /* Interrupt Status */
-#define IXP425_ICMR_OFFSET	0x04 /* Interrupt Enable */
-#define IXP425_ICLR_OFFSET	0x08 /* Interrupt IRQ/FIQ Select */
-#define IXP425_ICIP_OFFSET      0x0C /* IRQ Status */
-#define IXP425_ICFP_OFFSET	0x10 /* FIQ Status */
-#define IXP425_ICHR_OFFSET	0x14 /* Interrupt Priority */
-#define IXP425_ICIH_OFFSET	0x18 /* IRQ Highest Pri Int */
-#define IXP425_ICFH_OFFSET	0x1C /* FIQ Highest Pri Int */
-
-#define N_IRQS			32
-#define IXP425_TIMER_2_IRQ	11
-
-/*
- * Interrupt Controller Register Definitions.
- */
-#ifndef __ASSEMBLY__
-#define IXP425_INTC_REG(x) ((volatile u32 *)(IXP425_INTC_BASE_PHYS+(x)))
-#else
-#define IXP425_INTC_REG(x) (IXP425_INTC_BASE_PHYS+(x))
-#endif
-
-#define IXP425_ICPR     IXP425_INTC_REG(IXP425_ICPR_OFFSET)
-#define IXP425_ICMR     IXP425_INTC_REG(IXP425_ICMR_OFFSET)
-#define IXP425_ICLR     IXP425_INTC_REG(IXP425_ICLR_OFFSET)
-#define IXP425_ICIP     IXP425_INTC_REG(IXP425_ICIP_OFFSET)
-#define IXP425_ICFP     IXP425_INTC_REG(IXP425_ICFP_OFFSET)
-#define IXP425_ICHR     IXP425_INTC_REG(IXP425_ICHR_OFFSET)
-#define IXP425_ICIH     IXP425_INTC_REG(IXP425_ICIH_OFFSET)
-#define IXP425_ICFH     IXP425_INTC_REG(IXP425_ICFH_OFFSET)
-
-/*
- * Constants to make it easy to access GPIO registers
- */
-#define IXP425_GPIO_GPOUTR_OFFSET       0x00
-#define IXP425_GPIO_GPOER_OFFSET        0x04
-#define IXP425_GPIO_GPINR_OFFSET        0x08
-#define IXP425_GPIO_GPISR_OFFSET        0x0C
-#define IXP425_GPIO_GPIT1R_OFFSET	0x10
-#define IXP425_GPIO_GPIT2R_OFFSET	0x14
-#define IXP425_GPIO_GPCLKR_OFFSET	0x18
-#define IXP425_GPIO_GPDBSELR_OFFSET	0x1C
-
-/*
- * GPIO Register Definitions.
- * [Only perform 32bit reads/writes]
- */
-#define IXP425_GPIO_REG(x) ((volatile u32 *)(IXP425_GPIO_BASE_PHYS+(x)))
-
-#define IXP425_GPIO_GPOUTR	IXP425_GPIO_REG(IXP425_GPIO_GPOUTR_OFFSET)
-#define IXP425_GPIO_GPOER       IXP425_GPIO_REG(IXP425_GPIO_GPOER_OFFSET)
-#define IXP425_GPIO_GPINR       IXP425_GPIO_REG(IXP425_GPIO_GPINR_OFFSET)
-#define IXP425_GPIO_GPISR       IXP425_GPIO_REG(IXP425_GPIO_GPISR_OFFSET)
-#define IXP425_GPIO_GPIT1R      IXP425_GPIO_REG(IXP425_GPIO_GPIT1R_OFFSET)
-#define IXP425_GPIO_GPIT2R      IXP425_GPIO_REG(IXP425_GPIO_GPIT2R_OFFSET)
-#define IXP425_GPIO_GPCLKR      IXP425_GPIO_REG(IXP425_GPIO_GPCLKR_OFFSET)
-#define IXP425_GPIO_GPDBSELR    IXP425_GPIO_REG(IXP425_GPIO_GPDBSELR_OFFSET)
-
-#define IXP425_GPIO_GPITR(line)	(((line) >= 8) ? \
-				IXP425_GPIO_GPIT2R : IXP425_GPIO_GPIT1R)
-
-/*
- * Macros to make it easy to access the GPIO registers
- */
-#define GPIO_OUTPUT_ENABLE(line)	*IXP425_GPIO_GPOER &= ~(1 << (line))
-#define GPIO_OUTPUT_DISABLE(line)	*IXP425_GPIO_GPOER |= (1 << (line))
-#define GPIO_OUTPUT_SET(line)		*IXP425_GPIO_GPOUTR |= (1 << (line))
-#define GPIO_OUTPUT_CLEAR(line)		*IXP425_GPIO_GPOUTR &= ~(1 << (line))
-#define GPIO_INT_ACT_LOW_SET(line)				\
-	*IXP425_GPIO_GPITR(line) =				\
-			(*IXP425_GPIO_GPITR(line) &		\
-			~(0x7 << (((line) & 0x7) * 3))) |	\
-			(0x1 << (((line) & 0x7) * 3))		\
-
-/*
- * Constants to make it easy to access Timer Control/Status registers
- */
-#define IXP425_OSTS_OFFSET	0x00  /* Continious TimeStamp */
-#define IXP425_OST1_OFFSET	0x04  /* Timer 1 Timestamp */
-#define IXP425_OSRT1_OFFSET	0x08  /* Timer 1 Reload */
-#define IXP425_OST2_OFFSET	0x0C  /* Timer 2 Timestamp */
-#define IXP425_OSRT2_OFFSET	0x10  /* Timer 2 Reload */
-#define IXP425_OSWT_OFFSET	0x14  /* Watchdog Timer */
-#define IXP425_OSWE_OFFSET	0x18  /* Watchdog Enable */
-#define IXP425_OSWK_OFFSET	0x1C  /* Watchdog Key */
-#define IXP425_OSST_OFFSET	0x20  /* Timer Status */
-
-/*
- * Operating System Timer Register Definitions.
- */
-
-#ifndef __ASSEMBLY__
-#define IXP425_TIMER_REG(x) ((volatile u32 *)(IXP425_TIMER_BASE_PHYS+(x)))
-#else
-#define IXP425_TIMER_REG(x) (IXP425_TIMER_BASE_PHYS+(x))
-#endif
-
-/* _B to avoid collision: also defined in npe/include/... */
-#define IXP425_OSTS_B	IXP425_TIMER_REG(IXP425_OSTS_OFFSET)
-#define IXP425_OST1	IXP425_TIMER_REG(IXP425_OST1_OFFSET)
-#define IXP425_OSRT1	IXP425_TIMER_REG(IXP425_OSRT1_OFFSET)
-#define IXP425_OST2	IXP425_TIMER_REG(IXP425_OST2_OFFSET)
-#define IXP425_OSRT2	IXP425_TIMER_REG(IXP425_OSRT2_OFFSET)
-#define IXP425_OSWT	IXP425_TIMER_REG(IXP425_OSWT_OFFSET)
-#define IXP425_OSWE	IXP425_TIMER_REG(IXP425_OSWE_OFFSET)
-#define IXP425_OSWK	IXP425_TIMER_REG(IXP425_OSWK_OFFSET)
-#define IXP425_OSST	IXP425_TIMER_REG(IXP425_OSST_OFFSET)
-
-/*
- * Timer register values and bit definitions
- */
-#define IXP425_OST_ENABLE              BIT(0)
-#define IXP425_OST_ONE_SHOT            BIT(1)
-/* Low order bits of reload value ignored */
-#define IXP425_OST_RELOAD_MASK         (0x3)
-#define IXP425_OST_DISABLED            (0x0)
-#define IXP425_OSST_TIMER_1_PEND       BIT(0)
-#define IXP425_OSST_TIMER_2_PEND       BIT(1)
-#define IXP425_OSST_TIMER_TS_PEND      BIT(2)
-#define IXP425_OSST_TIMER_WDOG_PEND    BIT(3)
-#define IXP425_OSST_TIMER_WARM_RESET   BIT(4)
-
-/*
- * Constants to make it easy to access PCI Control/Status registers
- */
-#define PCI_NP_AD_OFFSET            0x00
-#define PCI_NP_CBE_OFFSET           0x04
-#define PCI_NP_WDATA_OFFSET         0x08
-#define PCI_NP_RDATA_OFFSET         0x0c
-#define PCI_CRP_AD_CBE_OFFSET       0x10
-#define PCI_CRP_WDATA_OFFSET        0x14
-#define PCI_CRP_RDATA_OFFSET        0x18
-#define PCI_CSR_OFFSET              0x1c
-#define PCI_ISR_OFFSET              0x20
-#define PCI_INTEN_OFFSET            0x24
-#define PCI_DMACTRL_OFFSET          0x28
-#define PCI_AHBMEMBASE_OFFSET       0x2c
-#define PCI_AHBIOBASE_OFFSET        0x30
-#define PCI_PCIMEMBASE_OFFSET       0x34
-#define PCI_AHBDOORBELL_OFFSET      0x38
-#define PCI_PCIDOORBELL_OFFSET      0x3C
-#define PCI_ATPDMA0_AHBADDR_OFFSET  0x40
-#define PCI_ATPDMA0_PCIADDR_OFFSET  0x44
-#define PCI_ATPDMA0_LENADDR_OFFSET  0x48
-#define PCI_ATPDMA1_AHBADDR_OFFSET  0x4C
-#define PCI_ATPDMA1_PCIADDR_OFFSET  0x50
-#define PCI_ATPDMA1_LENADDR_OFFSET  0x54
-
-/*
- * PCI Control/Status Registers
- */
-#define IXP425_PCI_CSR(x) ((volatile u32 *)(IXP425_PCI_CFG_BASE_PHYS+(x)))
-
-#define PCI_NP_AD               IXP425_PCI_CSR(PCI_NP_AD_OFFSET)
-#define PCI_NP_CBE              IXP425_PCI_CSR(PCI_NP_CBE_OFFSET)
-#define PCI_NP_WDATA            IXP425_PCI_CSR(PCI_NP_WDATA_OFFSET)
-#define PCI_NP_RDATA            IXP425_PCI_CSR(PCI_NP_RDATA_OFFSET)
-#define PCI_CRP_AD_CBE          IXP425_PCI_CSR(PCI_CRP_AD_CBE_OFFSET)
-#define PCI_CRP_WDATA           IXP425_PCI_CSR(PCI_CRP_WDATA_OFFSET)
-#define PCI_CRP_RDATA           IXP425_PCI_CSR(PCI_CRP_RDATA_OFFSET)
-#define PCI_CSR                 IXP425_PCI_CSR(PCI_CSR_OFFSET)
-#define PCI_ISR                 IXP425_PCI_CSR(PCI_ISR_OFFSET)
-#define PCI_INTEN               IXP425_PCI_CSR(PCI_INTEN_OFFSET)
-#define PCI_DMACTRL             IXP425_PCI_CSR(PCI_DMACTRL_OFFSET)
-#define PCI_AHBMEMBASE          IXP425_PCI_CSR(PCI_AHBMEMBASE_OFFSET)
-#define PCI_AHBIOBASE           IXP425_PCI_CSR(PCI_AHBIOBASE_OFFSET)
-#define PCI_PCIMEMBASE          IXP425_PCI_CSR(PCI_PCIMEMBASE_OFFSET)
-#define PCI_AHBDOORBELL         IXP425_PCI_CSR(PCI_AHBDOORBELL_OFFSET)
-#define PCI_PCIDOORBELL         IXP425_PCI_CSR(PCI_PCIDOORBELL_OFFSET)
-#define PCI_ATPDMA0_AHBADDR     IXP425_PCI_CSR(PCI_ATPDMA0_AHBADDR_OFFSET)
-#define PCI_ATPDMA0_PCIADDR     IXP425_PCI_CSR(PCI_ATPDMA0_PCIADDR_OFFSET)
-#define PCI_ATPDMA0_LENADDR     IXP425_PCI_CSR(PCI_ATPDMA0_LENADDR_OFFSET)
-#define PCI_ATPDMA1_AHBADDR     IXP425_PCI_CSR(PCI_ATPDMA1_AHBADDR_OFFSET)
-#define PCI_ATPDMA1_PCIADDR     IXP425_PCI_CSR(PCI_ATPDMA1_PCIADDR_OFFSET)
-#define PCI_ATPDMA1_LENADDR     IXP425_PCI_CSR(PCI_ATPDMA1_LENADDR_OFFSET)
-
-/*
- * PCI register values and bit definitions
- */
-
-/* CSR bit definitions */
-#define PCI_CSR_HOST		BIT(0)
-#define PCI_CSR_ARBEN		BIT(1)
-#define PCI_CSR_ADS		BIT(2)
-#define PCI_CSR_PDS		BIT(3)
-#define PCI_CSR_ABE		BIT(4)
-#define PCI_CSR_DBT		BIT(5)
-#define PCI_CSR_ASE		BIT(8)
-#define PCI_CSR_IC		BIT(15)
-
-/* ISR (Interrupt status) Register bit definitions */
-#define PCI_ISR_PSE		BIT(0)
-#define PCI_ISR_PFE		BIT(1)
-#define PCI_ISR_PPE		BIT(2)
-#define PCI_ISR_AHBE		BIT(3)
-#define PCI_ISR_APDC		BIT(4)
-#define PCI_ISR_PADC		BIT(5)
-#define PCI_ISR_ADB		BIT(6)
-#define PCI_ISR_PDB		BIT(7)
-
-/* INTEN (Interrupt Enable) Register bit definitions */
-#define PCI_INTEN_PSE		BIT(0)
-#define PCI_INTEN_PFE		BIT(1)
-#define PCI_INTEN_PPE		BIT(2)
-#define PCI_INTEN_AHBE		BIT(3)
-#define PCI_INTEN_APDC		BIT(4)
-#define PCI_INTEN_PADC		BIT(5)
-#define PCI_INTEN_ADB		BIT(6)
-#define PCI_INTEN_PDB		BIT(7)
-
-/*
- * Shift value for byte enable on NP cmd/byte enable register
- */
-#define IXP425_PCI_NP_CBE_BESL	4
-
-/*
- * PCI commands supported by NP access unit
- */
-#define NP_CMD_IOREAD		0x2
-#define NP_CMD_IOWRITE		0x3
-#define NP_CMD_CONFIGREAD	0xa
-#define NP_CMD_CONFIGWRITE	0xb
-#define NP_CMD_MEMREAD		0x6
-#define	NP_CMD_MEMWRITE		0x7
-
-#if 0
-#ifndef __ASSEMBLY__
-extern int ixp425_pci_read(u32 addr, u32 cmd, u32* data);
-extern int ixp425_pci_write(u32 addr, u32 cmd, u32 data);
-extern void ixp425_pci_init(void *);
-#endif
-#endif
-
-/*
- * Constants for CRP access into local config space
- */
-#define CRP_AD_CBE_BESL         20
-#define CRP_AD_CBE_WRITE        BIT(16)
-
-/*
- * Clock Speed Definitions.
- */
-#define IXP425_PERIPHERAL_BUS_CLOCK (66) /* 66Mhzi APB BUS   */
-
-
-#endif
diff --git a/arch/arm/include/asm/arch-ixp/ixp425pci.h b/arch/arm/include/asm/arch-ixp/ixp425pci.h
deleted file mode 100644
index f499883936..0000000000
--- a/arch/arm/include/asm/arch-ixp/ixp425pci.h
+++ /dev/null
@@ -1,174 +0,0 @@
-/*
- * IXP PCI Init
- * (C) Copyright 2004 eslab.whut.edu.cn
- * Yue Hu(huyue_whut@yahoo.com.cn), Ligong Xue(lgxue@hotmail.com)
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef _IXP425PCI_H
-#define _IXP425PCI_H
-
-#define OK	0
-#define ERROR	-1
-
-struct pci_controller;
-extern void pci_ixp_init(struct pci_controller *hose);
-
-/* Mask definitions*/
-#define IXP425_PCI_BOTTOM_NIBBLE_OF_LONG_MASK	0x0000000f
-
-#define PCI_NP_CBE_BESL	 (4)
-#define PCI_NP_AD_FUNCSL (8)
-
-/*Register addressing definitions for PCI controller configuration
-  and status registers*/
-
-#define PCI_CSR_BASE (0xC0000000)
-/*
-#define PCI_NP_AD_OFFSET       (0x00)
-#define PCI_NP_CBE_OFFSET      (0x04)
-#define PCI_NP_WDATA_OFFSET    (0x08)
-#define PCI_NP_RDATA_OFFSET    (0x0C)
-#define PCI_CRP_OFFSET	       (0x10)
-#define PCI_CRP_WDATA_OFFSET   (0x14)
-#define PCI_CRP_RDATA_OFFSET   (0x18)
-#define PCI_CSR_OFFSET	       (0x1C)
-#define PCI_ISR_OFFSET	       (0x20)
-#define PCI_INTEN_OFFSET       (0x24)
-#define PCI_DMACTRL_OFFSET     (0x28)
-#define PCI_AHBMEMBASE_OFFSET  (0x2C)
-#define PCI_AHBIOBASE_OFFSET   (0x30)
-#define PCI_PCIMEMBASE_OFFSET  (0x34)
-#define PCI_AHBDOORBELL_OFFSET (0x38)
-#define PCI_PCIDOORBELL_OFFSET (0x3C)
-#define PCI_ATPDMA0_AHBADDR    (0x40)
-#define PCI_ATPDMA0_PCIADDR    (0x44)
-#define PCI_ATPDMA0_LENADDR    (0x48)
-#define PCI_ATPDMA1_AHBADDR    (0x4C)
-#define PCI_ATPDMA1_PCIADDR    (0x50)
-#define PCI_ATPDMA1_LENADDR    (0x54)
-#define PCI_PTADMA0_AHBADDR    (0x58)
-#define PCI_PTADMA0_PCIADDR    (0x5C)
-#define PCI_PTADMA0_LENADDR    (0x60)
-#define PCI_PTADMA1_AHBADDR    (0x64)
-#define PCI_PTADMA1_PCIADDR    (0x68)
-#define PCI_PTADMA1_LENADDR    (0x6C)
-*/
-/*Non prefetch registers bit definitions*/
-/*
-#define NP_CMD_INTACK	   (0x0)
-#define NP_CMD_SPECIAL	   (0x1)
-#define NP_CMD_IOREAD	   (0x2)
-#define NP_CMD_IOWRITE	   (0x3)
-#define NP_CMD_MEMREAD	   (0x6)
-#define NP_CMD_MEMWRITE	   (0x7)
-#define NP_CMD_CONFIGREAD  (0xa)
-#define NP_CMD_CONFIGWRITE (0xb)
-*/
-
-/*Configuration Port register bit definitions*/
-#define PCI_CRP_WRITE BIT(16)
-
-/*ISR (Interrupt status) Register bit definitions*/
-#define PCI_ISR_PSE   BIT(0)
-#define PCI_ISR_PFE   BIT(1)
-#define PCI_ISR_PPE   BIT(2)
-#define PCI_ISR_AHBE  BIT(3)
-#define PCI_ISR_APDC  BIT(4)
-#define PCI_ISR_PADC  BIT(5)
-#define PCI_ISR_ADB   BIT(6)
-#define PCI_ISR_PDB   BIT(7)
-
-/*INTEN (Interrupt Enable) Register bit definitions*/
-#define PCI_INTEN_PSE	BIT(0)
-#define PCI_INTEN_PFE	BIT(1)
-#define PCI_INTEN_PPE	BIT(2)
-#define PCI_INTEN_AHBE	BIT(3)
-#define PCI_INTEN_APDC	BIT(4)
-#define PCI_INTEN_PADC	BIT(5)
-#define PCI_INTEN_ADB	BIT(6)
-#define PCI_INTEN_PDB	BIT(7)
-
-/*PCI configuration regs.*/
-
-#define PCI_CFG_VENDOR_ID	0x00
-#define PCI_CFG_DEVICE_ID	0x02
-#define PCI_CFG_COMMAND		0x04
-#define PCI_CFG_STATUS		0x06
-#define PCI_CFG_REVISION	0x08
-#define PCI_CFG_PROGRAMMING_IF	0x09
-#define PCI_CFG_SUBCLASS	0x0a
-#define PCI_CFG_CLASS		0x0b
-#define PCI_CFG_CACHE_LINE_SIZE 0x0c
-#define PCI_CFG_LATENCY_TIMER	0x0d
-#define PCI_CFG_HEADER_TYPE	0x0e
-#define PCI_CFG_BIST		0x0f
-#define PCI_CFG_BASE_ADDRESS_0	0x10
-#define PCI_CFG_BASE_ADDRESS_1	0x14
-#define PCI_CFG_BASE_ADDRESS_2	0x18
-#define PCI_CFG_BASE_ADDRESS_3	0x1c
-#define PCI_CFG_BASE_ADDRESS_4	0x20
-#define PCI_CFG_BASE_ADDRESS_5	0x24
-#define PCI_CFG_CIS		0x28
-#define PCI_CFG_SUB_VENDOR_ID	0x2c
-#define PCI_CFG_SUB_SYSTEM_ID	0x2e
-#define PCI_CFG_EXPANSION_ROM	0x30
-#define PCI_CFG_RESERVED_0	0x34
-#define PCI_CFG_RESERVED_1	0x38
-#define PCI_CFG_DEV_INT_LINE	0x3c
-#define PCI_CFG_DEV_INT_PIN	0x3d
-#define PCI_CFG_MIN_GRANT	0x3e
-#define PCI_CFG_MAX_LATENCY	0x3f
-#define PCI_CFG_SPECIAL_USE	0x41
-#define PCI_CFG_MODE		0x43
-
-#define PCI_CMD_IO_ENABLE	0x0001	/* IO access enable */
-#define PCI_CMD_MEM_ENABLE	0x0002	/* memory access enable */
-#define PCI_CMD_MASTER_ENABLE	0x0004	/* bus master enable */
-#define PCI_CMD_MON_ENABLE	0x0008	/* monitor special cycles enable */
-#define PCI_CMD_WI_ENABLE	0x0010	/* write and invalidate enable */
-#define PCI_CMD_SNOOP_ENABLE	0x0020	/* palette snoop enable */
-#define PCI_CMD_PERR_ENABLE	0x0040	/* parity error enable */
-#define PCI_CMD_WC_ENABLE	0x0080	/* wait cycle enable */
-#define PCI_CMD_SERR_ENABLE	0x0100	/* system error enable */
-#define PCI_CMD_FBTB_ENABLE	0x0200	/* fast back to back enable */
-
-
-/*CSR Register bit definitions*/
-#define PCI_CSR_HOST  BIT(0)
-#define PCI_CSR_ARBEN BIT(1)
-#define PCI_CSR_ADS   BIT(2)
-#define PCI_CSR_PDS   BIT(3)
-#define PCI_CSR_ABE   BIT(4)
-#define PCI_CSR_DBT   BIT(5)
-#define PCI_CSR_ASE   BIT(8)
-#define PCI_CSR_IC    BIT(15)
-
-/*Configuration command bit definitions*/
-#define PCI_CFG_CMD_IOAE BIT(0)
-#define PCI_CFG_CMD_MAE	 BIT(1)
-#define PCI_CFG_CMD_BME	 BIT(2)
-#define PCI_CFG_CMD_MWIE BIT(4)
-#define PCI_CFG_CMD_SER	 BIT(8)
-#define PCI_CFG_CMD_FBBE BIT(9)
-#define PCI_CFG_CMD_MDPE BIT(24)
-#define PCI_CFG_CMD_STA	 BIT(27)
-#define PCI_CFG_CMD_RTA	 BIT(28)
-#define PCI_CFG_CMD_RMA	 BIT(29)
-#define PCI_CFG_CMD_SSE	 BIT(30)
-#define PCI_CFG_CMD_DPE	 BIT(31)
-
-/*DMACTRL DMA Control and status Register*/
-#define PCI_DMACTRL_APDCEN  BIT(0)
-#define PCI_DMACTRL_APDC0   BIT(4)
-#define PCI_DMACTRL_APDE0   BIT(5)
-#define PCI_DMACTRL_APDC1   BIT(6)
-#define PCI_DMACTRL_APDE1   BIT(7)
-#define PCI_DMACTRL_PADCEN  BIT(8)
-#define PCI_DMACTRL_PADC0   BIT(12)
-#define PCI_DMACTRL_PADE0   BIT(13)
-#define PCI_DMACTRL_PADC1   BIT(14)
-#define PCI_DMACTRL_PADE1   BIT(15)
-
-#endif
diff --git a/arch/arm/include/asm/arch-kirkwood/config.h b/arch/arm/include/asm/arch-kirkwood/config.h
index 197703b838..7a688e46b0 100644
--- a/arch/arm/include/asm/arch-kirkwood/config.h
+++ b/arch/arm/include/asm/arch-kirkwood/config.h
@@ -38,7 +38,7 @@
  * CONFIG_SYS_KWD_CONFIG should be defined in board specific header file
  */
 #ifndef CONFIG_SYS_KWD_CONFIG
-#define	CONFIG_SYS_KWD_CONFIG	$(SRCTREE)/$(CONFIG_BOARDDIR)/kwbimage.cfg
+#define	CONFIG_SYS_KWD_CONFIG	$(CONFIG_BOARDDIR)/kwbimage.cfg
 #endif /* CONFIG_SYS_KWD_CONFIG */
 
 /* Kirkwood has 2k of Security SRAM, use it for SP */
diff --git a/arch/arm/include/asm/arch-lpc32xx/config.h b/arch/arm/include/asm/arch-lpc32xx/config.h
index a46baf249c..c985401d3c 100644
--- a/arch/arm/include/asm/arch-lpc32xx/config.h
+++ b/arch/arm/include/asm/arch-lpc32xx/config.h
@@ -15,9 +15,6 @@
 
 #define CONFIG_NR_DRAM_BANKS_MAX	2
 
-/* 1KHz clock tick */
-#define CONFIG_SYS_HZ			1000
-
 /* UART configuration */
 #if (CONFIG_SYS_LPC32XX_UART >= 3) && (CONFIG_SYS_LPC32XX_UART <= 6)
 #define CONFIG_SYS_NS16550_SERIAL
diff --git a/arch/arm/include/asm/arch-mb86r0x/hardware.h b/arch/arm/include/asm/arch-mb86r0x/hardware.h
index c0e3f206cd..42a52bc36c 100644
--- a/arch/arm/include/asm/arch-mb86r0x/hardware.h
+++ b/arch/arm/include/asm/arch-mb86r0x/hardware.h
@@ -9,7 +9,7 @@
 #ifndef __ASM_ARCH_HARDWARE_H
 #define __ASM_ARCH_HARDWARE_H
 
-#include <asm/sizes.h>
+#include <linux/sizes.h>
 #include <asm/arch/mb86r0x.h>
 
 #endif
diff --git a/arch/arm/include/asm/arch-mx35/spl.h b/arch/arm/include/asm/arch-mx35/spl.h
index f87c137c98..d0efec21ab 100644
--- a/arch/arm/include/asm/arch-mx35/spl.h
+++ b/arch/arm/include/asm/arch-mx35/spl.h
@@ -5,7 +5,7 @@
  * SPDX-License-Identifier:	GPL-2.0+
  */
 #ifndef	_ASM_ARCH_SPL_H_
-#define	_ASM_SPL_H_
+#define	_ASM_ARCH_SPL_H_
 
 #define BOOT_DEVICE_NONE	0
 #define BOOT_DEVICE_XIP		1
diff --git a/arch/arm/include/asm/arch-mx5/clock.h b/arch/arm/include/asm/arch-mx5/clock.h
index 9ee79aede3..3db4112d1f 100644
--- a/arch/arm/include/asm/arch-mx5/clock.h
+++ b/arch/arm/include/asm/arch-mx5/clock.h
@@ -53,5 +53,6 @@ void enable_usboh3_clk(bool enable);
 void mxc_set_sata_internal_clock(void);
 int enable_i2c_clk(unsigned char enable, unsigned i2c_num);
 void enable_nfc_clk(unsigned char enable);
+void enable_efuse_prog_supply(bool enable);
 
 #endif /* __ASM_ARCH_CLOCK_H */
diff --git a/arch/arm/include/asm/arch-mx5/crm_regs.h b/arch/arm/include/asm/arch-mx5/crm_regs.h
index 392881c0e7..efe57e07ea 100644
--- a/arch/arm/include/asm/arch-mx5/crm_regs.h
+++ b/arch/arm/include/asm/arch-mx5/crm_regs.h
@@ -305,6 +305,9 @@ struct mxc_ccm_reg {
 /* Define the bits in register CCDR */
 #define MXC_CCM_CCDR_IPU_HS_MASK			(0x1 << 17)
 
+/* Define the bits in register CGPR */
+#define MXC_CCM_CGPR_EFUSE_PROG_SUPPLY_GATE		(1 << 4)
+
 /* Define the bits in register CCGRx */
 #define MXC_CCM_CCGR_CG_MASK				0x3
 #define MXC_CCM_CCGR_CG_OFF				0x0
diff --git a/arch/arm/include/asm/arch-mx5/imx-regs.h b/arch/arm/include/asm/arch-mx5/imx-regs.h
index 4955ccff87..054c680a5a 100644
--- a/arch/arm/include/asm/arch-mx5/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx5/imx-regs.h
@@ -230,9 +230,10 @@
 #define MXC_CSPICTRL_CHAN	18
 
 /* Bit position inside CON register to be associated with SS */
-#define MXC_CSPICON_POL		4
-#define MXC_CSPICON_PHA		0
-#define MXC_CSPICON_SSPOL	12
+#define MXC_CSPICON_PHA		0  /* SCLK phase control */
+#define MXC_CSPICON_POL		4  /* SCLK polarity */
+#define MXC_CSPICON_SSPOL	12 /* SS polarity */
+#define MXC_CSPICON_CTL		20 /* inactive state of SCLK */
 #define MXC_SPI_BASE_ADDRESSES \
 	CSPI1_BASE_ADDR, \
 	CSPI2_BASE_ADDR, \
diff --git a/arch/arm/include/asm/arch-mx5/sys_proto.h b/arch/arm/include/asm/arch-mx5/sys_proto.h
index 9949ad1312..ac7705b3b0 100644
--- a/arch/arm/include/asm/arch-mx5/sys_proto.h
+++ b/arch/arm/include/asm/arch-mx5/sys_proto.h
@@ -8,12 +8,7 @@
 #ifndef _SYS_PROTO_H_
 #define _SYS_PROTO_H_
 
-#define MXC_CPU_MX51		0x51
-#define MXC_CPU_MX53		0x53
-#define MXC_CPU_MX6SL		0x60
-#define MXC_CPU_MX6DL		0x61
-#define MXC_CPU_MX6SOLO		0x62
-#define MXC_CPU_MX6Q		0x63
+#include "../arch-imx/cpu.h"
 
 #define is_soc_rev(rev)	((get_cpu_rev() & 0xFF) - rev)
 u32 get_cpu_rev(void);
diff --git a/arch/arm/include/asm/arch-mx6/clock.h b/arch/arm/include/asm/arch-mx6/clock.h
index 93f29a780f..1b4ded7feb 100644
--- a/arch/arm/include/asm/arch-mx6/clock.h
+++ b/arch/arm/include/asm/arch-mx6/clock.h
@@ -42,13 +42,21 @@ enum mxc_clock {
 	MXC_I2C_CLK,
 };
 
+enum enet_freq {
+	ENET_25MHz,
+	ENET_50MHz,
+	ENET_100MHz,
+	ENET_125MHz,
+};
+
 u32 imx_get_uartclk(void);
 u32 imx_get_fecclk(void);
 unsigned int mxc_get_clock(enum mxc_clock clk);
 void enable_ocotp_clk(unsigned char enable);
 void enable_usboh3_clk(unsigned char enable);
 int enable_sata_clock(void);
+int enable_pcie_clock(void);
 int enable_i2c_clk(unsigned char enable, unsigned i2c_num);
 void enable_ipu_clock(void);
-int enable_fec_anatop_clock(void);
+int enable_fec_anatop_clock(enum enet_freq freq);
 #endif /* __ASM_ARCH_CLOCK_H */
diff --git a/arch/arm/include/asm/arch-mx6/crm_regs.h b/arch/arm/include/asm/arch-mx6/crm_regs.h
index 2813593e25..720207303b 100644
--- a/arch/arm/include/asm/arch-mx6/crm_regs.h
+++ b/arch/arm/include/asm/arch-mx6/crm_regs.h
@@ -890,15 +890,4 @@ struct mxc_ccm_reg {
 #define BF_ANADIG_PFD_528_PFD0_FRAC(v)  \
 	(((v) << 0) & BM_ANADIG_PFD_528_PFD0_FRAC)
 
-#define PLL2_PFD0_FREQ		352000000
-#define PLL2_PFD1_FREQ		594000000
-#define PLL2_PFD2_FREQ		396000000
-#define PLL2_PFD2_DIV_FREQ	200000000
-#define PLL3_PFD0_FREQ		720000000
-#define PLL3_PFD1_FREQ		540000000
-#define PLL3_PFD2_FREQ		508200000
-#define PLL3_PFD3_FREQ		454700000
-#define PLL3_80M		80000000
-#define PLL3_60M		60000000
-
 #endif /*__ARCH_ARM_MACH_MX6_CCM_REGS_H__ */
diff --git a/arch/arm/include/asm/arch-mx6/imx-regs.h b/arch/arm/include/asm/arch-mx6/imx-regs.h
index 7ef7152678..1f19727b58 100644
--- a/arch/arm/include/asm/arch-mx6/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx6/imx-regs.h
@@ -53,6 +53,7 @@
 #define GLOBAL_TIMER_BASE_ADDR          0x00A00200
 #define PRIVATE_TIMERS_WD_BASE_ADDR     0x00A00600
 #define IC_DISTRIBUTOR_BASE_ADDR        0x00A01000
+#define L2_PL310_BASE			0x00A02000
 #define GPV0_BASE_ADDR                  0x00B00000
 #define GPV1_BASE_ADDR                  0x00C00000
 #define PCIE_ARB_BASE_ADDR              0x01000000
@@ -245,6 +246,10 @@ struct src {
 	u32     gpr10;
 };
 
+/* GPR1 bitfields */
+#define IOMUXC_GPR1_ENET_CLK_SEL_OFFSET		21
+#define IOMUXC_GPR1_ENET_CLK_SEL_MASK		(1 << IOMUXC_GPR1_ENET_CLK_SEL_OFFSET)
+
 /* GPR3 bitfields */
 #define IOMUXC_GPR3_GPU_DBG_OFFSET		29
 #define IOMUXC_GPR3_GPU_DBG_MASK		(3<<IOMUXC_GPR3_GPU_DBG_OFFSET)
@@ -401,10 +406,11 @@ struct cspi_regs {
 #define MXC_CSPICTRL_CHAN	18
 
 /* Bit position inside CON register to be associated with SS */
-#define MXC_CSPICON_POL		4
-#define MXC_CSPICON_PHA		0
-#define MXC_CSPICON_SSPOL	12
-#ifdef CONFIG_MX6SL
+#define MXC_CSPICON_PHA		0  /* SCLK phase control */
+#define MXC_CSPICON_POL		4  /* SCLK polarity */
+#define MXC_CSPICON_SSPOL	12 /* SS polarity */
+#define MXC_CSPICON_CTL		20 /* inactive state of SCLK */
+#if defined(CONFIG_MX6SL) || defined(CONFIG_MX6DL)
 #define MXC_SPI_BASE_ADDRESSES \
 	ECSPI1_BASE_ADDR, \
 	ECSPI2_BASE_ADDR, \
diff --git a/arch/arm/include/asm/arch-mx6/iomux.h b/arch/arm/include/asm/arch-mx6/iomux.h
index ff13a1ea9f..f9ee0d9839 100644
--- a/arch/arm/include/asm/arch-mx6/iomux.h
+++ b/arch/arm/include/asm/arch-mx6/iomux.h
@@ -10,6 +10,39 @@
 #define MX6_IOMUXC_GPR7		0x020e001c
 
 /*
+ * IOMUXC_GPR1 bit fields
+ */
+#define IOMUXC_GPR1_OTG_ID_ENET_RX_ERR	(0<<13)
+#define IOMUXC_GPR1_OTG_ID_GPIO1	(1<<13)
+#define IOMUXC_GPR1_OTG_ID_MASK		(1<<13)
+#define IOMUXC_GPR1_REF_SSP_EN			(1 << 16)
+#define IOMUXC_GPR1_TEST_POWERDOWN		(1 << 18)
+
+/*
+ * IOMUXC_GPR8 bit fields
+ */
+#define IOMUXC_GPR8_PCS_TX_DEEMPH_GEN1_MASK		(0x3f << 0)
+#define IOMUXC_GPR8_PCS_TX_DEEMPH_GEN1_OFFSET		0
+#define IOMUXC_GPR8_PCS_TX_DEEMPH_GEN2_3P5DB_MASK	(0x3f << 6)
+#define IOMUXC_GPR8_PCS_TX_DEEMPH_GEN2_3P5DB_OFFSET	6
+#define IOMUXC_GPR8_PCS_TX_DEEMPH_GEN2_6DB_MASK		(0x3f << 12)
+#define IOMUXC_GPR8_PCS_TX_DEEMPH_GEN2_6DB_OFFSET	12
+#define IOMUXC_GPR8_PCS_TX_SWING_FULL_MASK		(0x7f << 18)
+#define IOMUXC_GPR8_PCS_TX_SWING_FULL_OFFSET		18
+#define IOMUXC_GPR8_PCS_TX_SWING_LOW_MASK		(0x7f << 25)
+#define IOMUXC_GPR8_PCS_TX_SWING_LOW_OFFSET		25
+
+/*
+ * IOMUXC_GPR12 bit fields
+ */
+#define IOMUXC_GPR12_LOS_LEVEL_9		(0x9 << 4)
+#define IOMUXC_GPR12_LOS_LEVEL_MASK		(0x1f << 4)
+#define IOMUXC_GPR12_APPS_LTSSM_ENABLE		(1 << 10)
+#define IOMUXC_GPR12_DEVICE_TYPE_EP		(0x0 << 12)
+#define IOMUXC_GPR12_DEVICE_TYPE_RC		(0x2 << 12)
+#define IOMUXC_GPR12_DEVICE_TYPE_MASK		(0xf << 12)
+
+/*
  * IOMUXC_GPR13 bit fields
  */
 #define IOMUXC_GPR13_SDMA_STOP_REQ	(1<<30)
diff --git a/arch/arm/include/asm/arch-mx6/mx6-pins.h b/arch/arm/include/asm/arch-mx6/mx6-pins.h
index 1c9e3fe204..dcd7f8f327 100644
--- a/arch/arm/include/asm/arch-mx6/mx6-pins.h
+++ b/arch/arm/include/asm/arch-mx6/mx6-pins.h
@@ -6,18 +6,37 @@
 #ifndef __ASM_ARCH_MX6_PINS_H__
 #define __ASM_ARCH_MX6_PINS_H__
 
-#ifdef CONFIG_MX6Q
+#include <asm/imx-common/iomux-v3.h>
+
+#define MX6_PAD_DECLARE(prefix, name, pco, mc, mm, sio, si, pc) \
+	prefix##name = IOMUX_PAD(pco, mc, mm, sio, si, pc)
+
+#ifdef CONFIG_MX6QDL
+enum {
+#define MX6_PAD_DECL(name, pco, mc, mm, sio, si, pc) \
+	MX6_PAD_DECLARE(MX6Q_PAD_,name, pco, mc, mm, sio, si, pc),
 #include "mx6q_pins.h"
-#else
-#if defined(CONFIG_MX6DL) || defined(CONFIG_MX6S)
+#undef MX6_PAD_DECL
+#define MX6_PAD_DECL(name, pco, mc, mm, sio, si, pc) \
+	MX6_PAD_DECLARE(MX6DL_PAD_,name, pco, mc, mm, sio, si, pc),
 #include "mx6dl_pins.h"
-#else
-#if defined(CONFIG_MX6SL)
+};
+#elif defined(CONFIG_MX6Q)
+enum {
+#define MX6_PAD_DECL(name, pco, mc, mm, sio, si, pc) \
+	MX6_PAD_DECLARE(MX6_PAD_,name, pco, mc, mm, sio, si, pc),
+#include "mx6q_pins.h"
+};
+#elif defined(CONFIG_MX6DL) || defined(CONFIG_MX6S)
+enum {
+#define MX6_PAD_DECL(name, pco, mc, mm, sio, si, pc) \
+	MX6_PAD_DECLARE(MX6_PAD_,name, pco, mc, mm, sio, si, pc),
+#include "mx6dl_pins.h"
+};
+#elif defined(CONFIG_MX6SL)
 #include "mx6sl_pins.h"
 #else
 #error "Please select cpu"
-#endif	/* CONFIG_MX6SL */
-#endif	/* CONFIG_MX6DL or CONFIG_MX6S */
 #endif	/* CONFIG_MX6Q */
 
 #endif	/*__ASM_ARCH_MX6_PINS_H__ */
diff --git a/arch/arm/include/asm/arch-mx6/mx6dl_pins.h b/arch/arm/include/asm/arch-mx6/mx6dl_pins.h
index b5df68afc6..2e414adf3d 100644
--- a/arch/arm/include/asm/arch-mx6/mx6dl_pins.h
+++ b/arch/arm/include/asm/arch-mx6/mx6dl_pins.h
@@ -7,1664 +7,1074 @@
 #ifndef __ASM_ARCH_MX6_MX6DL_PINS_H__
 #define __ASM_ARCH_MX6_MX6DL_PINS_H__
 
-#include <asm/imx-common/iomux-v3.h>
+MX6_PAD_DECL(CSI0_DAT10__IPU1_CSI0_DATA10,	0x0360, 0x004C, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT10__AUD3_RXC,	0x0360, 0x004C, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT10__ECSPI2_MISO,	0x0360, 0x004C, 2, 0x07F8, 0, 0)
+MX6_PAD_DECL(CSI0_DAT10__UART1_TX_DATA,	0x0360, 0x004C, 3, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT10__UART1_RX_DATA,	0x0360, 0x004C, 3, 0x08FC, 0, 0)
+MX6_PAD_DECL(CSI0_DAT10__GPIO5_IO28,	0x0360, 0x004C, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT10__ARM_TRACE07,	0x0360, 0x004C, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT11__IPU1_CSI0_DATA11,	0x0364, 0x0050, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT11__AUD3_RXFS,	0x0364, 0x0050, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT11__ECSPI2_SS0,	0x0364, 0x0050, 2, 0x0800, 0, 0)
+MX6_PAD_DECL(CSI0_DAT11__UART1_TX_DATA,	0x0364, 0x0050, 3, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT11__UART1_RX_DATA,	0x0364, 0x0050, 3, 0x08FC, 1, 0)
+MX6_PAD_DECL(CSI0_DAT11__GPIO5_IO29,	0x0364, 0x0050, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT11__ARM_TRACE08,	0x0364, 0x0050, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT12__IPU1_CSI0_DATA12,	0x0368, 0x0054, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT12__EIM_DATA08,	0x0368, 0x0054, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT12__UART4_TX_DATA,	0x0368, 0x0054, 3, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT12__UART4_RX_DATA,	0x0368, 0x0054, 3, 0x0914, 0, 0)
+MX6_PAD_DECL(CSI0_DAT12__GPIO5_IO30,	0x0368, 0x0054, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT12__ARM_TRACE09,	0x0368, 0x0054, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT13__IPU1_CSI0_DATA13,	0x036C, 0x0058, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT13__EIM_DATA09,	0x036C, 0x0058, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT13__UART4_TX_DATA,	0x036C, 0x0058, 3, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT13__UART4_RX_DATA,	0x036C, 0x0058, 3, 0x0914, 1, 0)
+MX6_PAD_DECL(CSI0_DAT13__GPIO5_IO31,	0x036C, 0x0058, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT13__ARM_TRACE10,	0x036C, 0x0058, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT14__IPU1_CSI0_DATA14,	0x0370, 0x005C, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT14__EIM_DATA10,	0x0370, 0x005C, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT14__UART5_TX_DATA,	0x0370, 0x005C, 3, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT14__UART5_RX_DATA,	0x0370, 0x005C, 3, 0x091C, 0, 0)
+MX6_PAD_DECL(CSI0_DAT14__GPIO6_IO00,	0x0370, 0x005C, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT14__ARM_TRACE11,	0x0370, 0x005C, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT15__IPU1_CSI0_DATA15,	0x0374, 0x0060, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT15__EIM_DATA11,	0x0374, 0x0060, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT15__UART5_TX_DATA,	0x0374, 0x0060, 3, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT15__UART5_RX_DATA,	0x0374, 0x0060, 3, 0x091C, 1, 0)
+MX6_PAD_DECL(CSI0_DAT15__GPIO6_IO01,	0x0374, 0x0060, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT15__ARM_TRACE12,	0x0374, 0x0060, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT16__IPU1_CSI0_DATA16,	0x0378, 0x0064, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT16__EIM_DATA12,	0x0378, 0x0064, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT16__UART4_CTS_B,	0x0378, 0x0064, 3, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT16__UART4_RTS_B,	0x0378, 0x0064, 3, 0x0910, 0, 0)
+MX6_PAD_DECL(CSI0_DAT16__GPIO6_IO02,	0x0378, 0x0064, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT16__ARM_TRACE13,	0x0378, 0x0064, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT17__IPU1_CSI0_DATA17,	0x037C, 0x0068, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT17__EIM_DATA13,	0x037C, 0x0068, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT17__UART4_CTS_B,	0x037C, 0x0068, 3, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT17__UART4_RTS_B,	0x037C, 0x0068, 3, 0x0910, 1, 0)
+MX6_PAD_DECL(CSI0_DAT17__GPIO6_IO03,	0x037C, 0x0068, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT17__ARM_TRACE14,	0x037C, 0x0068, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT18__IPU1_CSI0_DATA18,	0x0380, 0x006C, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT18__EIM_DATA14,	0x0380, 0x006C, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT18__UART5_CTS_B,	0x0380, 0x006C, 3, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT18__UART5_RTS_B,	0x0380, 0x006C, 3, 0x0918, 0, 0)
+MX6_PAD_DECL(CSI0_DAT18__GPIO6_IO04,	0x0380, 0x006C, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT18__ARM_TRACE15,	0x0380, 0x006C, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT19__IPU1_CSI0_DATA19,	0x0384, 0x0070, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT19__EIM_DATA15,	0x0384, 0x0070, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT19__UART5_CTS_B,	0x0384, 0x0070, 3, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT19__UART5_RTS_B,	0x0384, 0x0070, 3, 0x0918, 1, 0)
+MX6_PAD_DECL(CSI0_DAT19__GPIO6_IO05,	0x0384, 0x0070, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT4__IPU1_CSI0_DATA04,	0x0388, 0x0074, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT4__EIM_DATA02,	0x0388, 0x0074, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT4__ECSPI1_SCLK,	0x0388, 0x0074, 2, 0x07D8, 0, 0)
+MX6_PAD_DECL(CSI0_DAT4__KEY_COL5,	0x0388, 0x0074, 3, 0x08C0, 0, 0)
+MX6_PAD_DECL(CSI0_DAT4__AUD3_TXC,	0x0388, 0x0074, 4, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT4__GPIO5_IO22,	0x0388, 0x0074, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT4__ARM_TRACE01,	0x0388, 0x0074, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT5__IPU1_CSI0_DATA05,	0x038C, 0x0078, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT5__EIM_DATA03,	0x038C, 0x0078, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT5__ECSPI1_MOSI,	0x038C, 0x0078, 2, 0x07E0, 0, 0)
+MX6_PAD_DECL(CSI0_DAT5__KEY_ROW5,	0x038C, 0x0078, 3, 0x08CC, 0, 0)
+MX6_PAD_DECL(CSI0_DAT5__AUD3_TXD,	0x038C, 0x0078, 4, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT5__GPIO5_IO23,	0x038C, 0x0078, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT5__ARM_TRACE02,	0x038C, 0x0078, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT6__IPU1_CSI0_DATA06,	0x0390, 0x007C, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT6__EIM_DATA04,	0x0390, 0x007C, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT6__ECSPI1_MISO,	0x0390, 0x007C, 2, 0x07DC, 0, 0)
+MX6_PAD_DECL(CSI0_DAT6__KEY_COL6,	0x0390, 0x007C, 3, 0x08C4, 0, 0)
+MX6_PAD_DECL(CSI0_DAT6__AUD3_TXFS,	0x0390, 0x007C, 4, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT6__GPIO5_IO24,	0x0390, 0x007C, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT6__ARM_TRACE03,	0x0390, 0x007C, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT7__IPU1_CSI0_DATA07,	0x0394, 0x0080, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT7__EIM_DATA05,	0x0394, 0x0080, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT7__ECSPI1_SS0,	0x0394, 0x0080, 2, 0x07E4, 0, 0)
+MX6_PAD_DECL(CSI0_DAT7__KEY_ROW6,	0x0394, 0x0080, 3, 0x08D0, 0, 0)
+MX6_PAD_DECL(CSI0_DAT7__AUD3_RXD,	0x0394, 0x0080, 4, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT7__GPIO5_IO25,	0x0394, 0x0080, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT7__ARM_TRACE04,	0x0394, 0x0080, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT8__IPU1_CSI0_DATA08,	0x0398, 0x0084, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT8__EIM_DATA06,	0x0398, 0x0084, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT8__ECSPI2_SCLK,	0x0398, 0x0084, 2, 0x07F4, 0, 0)
+MX6_PAD_DECL(CSI0_DAT8__KEY_COL7,	0x0398, 0x0084, 3, 0x08C8, 0, 0)
+MX6_PAD_DECL(CSI0_DAT8__I2C1_SDA,	0x0398, 0x0084, 4 | IOMUX_CONFIG_SION, 0x086C, 0, 0)
+MX6_PAD_DECL(CSI0_DAT8__GPIO5_IO26,	0x0398, 0x0084, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT8__ARM_TRACE05,	0x0398, 0x0084, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT9__IPU1_CSI0_DATA09,	0x039C, 0x0088, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT9__EIM_DATA07,	0x039C, 0x0088, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT9__ECSPI2_MOSI,	0x039C, 0x0088, 2, 0x07FC, 0, 0)
+MX6_PAD_DECL(CSI0_DAT9__KEY_ROW7,	0x039C, 0x0088, 3, 0x08D4, 0, 0)
+MX6_PAD_DECL(CSI0_DAT9__I2C1_SCL,	0x039C, 0x0088, 4 | IOMUX_CONFIG_SION, 0x0868, 0, 0)
+MX6_PAD_DECL(CSI0_DAT9__GPIO5_IO27,	0x039C, 0x0088, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT9__ARM_TRACE06,	0x039C, 0x0088, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DATA_EN__IPU1_CSI0_DATA_EN,	0x03A0, 0x008C, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DATA_EN__EIM_DATA00,	0x03A0, 0x008C, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DATA_EN__GPIO5_IO20,	0x03A0, 0x008C, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DATA_EN__ARM_TRACE_CLK,	0x03A0, 0x008C, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_MCLK__IPU1_CSI0_HSYNC,	0x03A4, 0x0090, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_MCLK__CCM_CLKO1,	0x03A4, 0x0090, 3, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_MCLK__GPIO5_IO19,	0x03A4, 0x0090, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_MCLK__ARM_TRACE_CTL,	0x03A4, 0x0090, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_PIXCLK__IPU1_CSI0_PIXCLK,	0x03A8, 0x0094, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_PIXCLK__GPIO5_IO18,	0x03A8, 0x0094, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_PIXCLK__ARM_EVENTO,	0x03A8, 0x0094, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_VSYNC__IPU1_CSI0_VSYNC,	0x03AC, 0x0098, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_VSYNC__EIM_DATA01,	0x03AC, 0x0098, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_VSYNC__GPIO5_IO21,	0x03AC, 0x0098, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_VSYNC__ARM_TRACE00,	0x03AC, 0x0098, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(DI0_DISP_CLK__IPU1_DI0_DISP_CLK,	0x03B0, 0x009C, 0, 0x0000, 0, PAD_CTL_DSE_120ohm)
+MX6_PAD_DECL(DI0_DISP_CLK__LCD_CLK,	0x03B0, 0x009C, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(DI0_DISP_CLK__GPIO4_IO16,	0x03B0, 0x009C, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(DI0_DISP_CLK__LCD_WR_RWN,	0x03B0, 0x009C, 8, 0x0000, 0, 0)
+MX6_PAD_DECL(DI0_PIN15__IPU1_DI0_PIN15,	0x03B4, 0x00A0, 0, 0x0000, 0, PAD_CTL_DSE_120ohm)
+MX6_PAD_DECL(DI0_PIN15__LCD_ENABLE,	0x03B4, 0x00A0, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(DI0_PIN15__AUD6_TXC,	0x03B4, 0x00A0, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(DI0_PIN15__GPIO4_IO17,	0x03B4, 0x00A0, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(DI0_PIN15__LCD_RD_E,	0x03B4, 0x00A0, 8, 0x0000, 0, 0)
+MX6_PAD_DECL(DI0_PIN2__IPU1_DI0_PIN02,	0x03B8, 0x00A4, 0, 0x0000, 0, PAD_CTL_DSE_120ohm)
+MX6_PAD_DECL(DI0_PIN2__LCD_HSYNC,	0x03B8, 0x00A4, 1, 0x08D8, 0, 0)
+MX6_PAD_DECL(DI0_PIN2__AUD6_TXD,	0x03B8, 0x00A4, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(DI0_PIN2__GPIO4_IO18,	0x03B8, 0x00A4, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(DI0_PIN2__LCD_RS,	0x03B8, 0x00A4, 8, 0x0000, 0, 0)
+MX6_PAD_DECL(DI0_PIN3__IPU1_DI0_PIN03,	0x03BC, 0x00A8, 0, 0x0000, 0, PAD_CTL_DSE_120ohm)
+MX6_PAD_DECL(DI0_PIN3__LCD_VSYNC,	0x03BC, 0x00A8, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(DI0_PIN3__AUD6_TXFS,	0x03BC, 0x00A8, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(DI0_PIN3__GPIO4_IO19,	0x03BC, 0x00A8, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(DI0_PIN3__LCD_CS,	0x03BC, 0x00A8, 8, 0x0000, 0, 0)
+MX6_PAD_DECL(DI0_PIN4__IPU1_DI0_PIN04,	0x03C0, 0x00AC, 0, 0x0000, 0, PAD_CTL_DSE_120ohm)
+MX6_PAD_DECL(DI0_PIN4__LCD_BUSY,	0x03C0, 0x00AC, 1, 0x08D8, 1, 0)
+MX6_PAD_DECL(DI0_PIN4__AUD6_RXD,	0x03C0, 0x00AC, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(DI0_PIN4__SD1_WP,	0x03C0, 0x00AC, 3, 0x092C, 0, 0)
+MX6_PAD_DECL(DI0_PIN4__GPIO4_IO20,	0x03C0, 0x00AC, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(DI0_PIN4__LCD_RESET,	0x03C0, 0x00AC, 8, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT0__IPU1_DISP0_DATA00,	0x03C4, 0x00B0, 0, 0x0000, 0, PAD_CTL_DSE_120ohm)
+MX6_PAD_DECL(DISP0_DAT0__LCD_DATA00,	0x03C4, 0x00B0, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT0__ECSPI3_SCLK,	0x03C4, 0x00B0, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT0__GPIO4_IO21,	0x03C4, 0x00B0, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT1__IPU1_DISP0_DATA01,	0x03C8, 0x00B4, 0, 0x0000, 0, PAD_CTL_DSE_120ohm)
+MX6_PAD_DECL(DISP0_DAT1__LCD_DATA01,	0x03C8, 0x00B4, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT1__ECSPI3_MOSI,	0x03C8, 0x00B4, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT1__GPIO4_IO22,	0x03C8, 0x00B4, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT10__IPU1_DISP0_DATA10,	0x03CC, 0x00B8, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT10__LCD_DATA10,	0x03CC, 0x00B8, 1, 0x0000, 0, PAD_CTL_DSE_120ohm)
+MX6_PAD_DECL(DISP0_DAT10__GPIO4_IO31,	0x03CC, 0x00B8, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT11__IPU1_DISP0_DATA11,	0x03D0, 0x00BC, 0, 0x0000, 0, PAD_CTL_DSE_120ohm)
+MX6_PAD_DECL(DISP0_DAT11__LCD_DATA11,	0x03D0, 0x00BC, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT11__GPIO5_IO05,	0x03D0, 0x00BC, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT12__IPU1_DISP0_DATA12,	0x03D4, 0x00C0, 0, 0x0000, 0, PAD_CTL_DSE_120ohm)
+MX6_PAD_DECL(DISP0_DAT12__LCD_DATA12,	0x03D4, 0x00C0, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT12__GPIO5_IO06,	0x03D4, 0x00C0, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT13__IPU1_DISP0_DATA13,	0x03D8, 0x00C4, 0, 0x0000, 0, PAD_CTL_DSE_120ohm)
+MX6_PAD_DECL(DISP0_DAT13__LCD_DATA13,	0x03D8, 0x00C4, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT13__AUD5_RXFS,	0x03D8, 0x00C4, 3, 0x07BC, 0, 0)
+MX6_PAD_DECL(DISP0_DAT13__GPIO5_IO07,	0x03D8, 0x00C4, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT14__IPU1_DISP0_DATA14,	0x03DC, 0x00C8, 0, 0x0000, 0, PAD_CTL_DSE_120ohm)
+MX6_PAD_DECL(DISP0_DAT14__LCD_DATA14,	0x03DC, 0x00C8, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT14__AUD5_RXC,	0x03DC, 0x00C8, 3, 0x07B8, 0, 0)
+MX6_PAD_DECL(DISP0_DAT14__GPIO5_IO08,	0x03DC, 0x00C8, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT15__IPU1_DISP0_DATA15,	0x03E0, 0x00CC, 0, 0x0000, 0, PAD_CTL_DSE_120ohm)
+MX6_PAD_DECL(DISP0_DAT15__LCD_DATA15,	0x03E0, 0x00CC, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT15__ECSPI1_SS1,	0x03E0, 0x00CC, 2, 0x07E8, 0, 0)
+MX6_PAD_DECL(DISP0_DAT15__ECSPI2_SS1,	0x03E0, 0x00CC, 3, 0x0804, 0, 0)
+MX6_PAD_DECL(DISP0_DAT15__GPIO5_IO09,	0x03E0, 0x00CC, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT16__IPU1_DISP0_DATA16,	0x03E4, 0x00D0, 0, 0x0000, 0, PAD_CTL_DSE_120ohm)
+MX6_PAD_DECL(DISP0_DAT16__LCD_DATA16,	0x03E4, 0x00D0, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT16__ECSPI2_MOSI,	0x03E4, 0x00D0, 2, 0x07FC, 1, 0)
+MX6_PAD_DECL(DISP0_DAT16__AUD5_TXC,	0x03E4, 0x00D0, 3, 0x07C0, 0, 0)
+MX6_PAD_DECL(DISP0_DAT16__SDMA_EXT_EVENT0,	0x03E4, 0x00D0, 4, 0x08E8, 0, 0)
+MX6_PAD_DECL(DISP0_DAT16__GPIO5_IO10,	0x03E4, 0x00D0, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT17__IPU1_DISP0_DATA17,	0x03E8, 0x00D4, 0, 0x0000, 0, PAD_CTL_DSE_120ohm)
+MX6_PAD_DECL(DISP0_DAT17__LCD_DATA17,	0x03E8, 0x00D4, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT17__ECSPI2_MISO,	0x03E8, 0x00D4, 2, 0x07F8, 1, 0)
+MX6_PAD_DECL(DISP0_DAT17__AUD5_TXD,	0x03E8, 0x00D4, 3, 0x07B4, 0, 0)
+MX6_PAD_DECL(DISP0_DAT17__SDMA_EXT_EVENT1,	0x03E8, 0x00D4, 4, 0x08EC, 0, 0)
+MX6_PAD_DECL(DISP0_DAT17__GPIO5_IO11,	0x03E8, 0x00D4, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT18__IPU1_DISP0_DATA18,	0x03EC, 0x00D8, 0, 0x0000, 0, PAD_CTL_DSE_120ohm)
+MX6_PAD_DECL(DISP0_DAT18__LCD_DATA18,	0x03EC, 0x00D8, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT18__ECSPI2_SS0,	0x03EC, 0x00D8, 2, 0x0800, 1, 0)
+MX6_PAD_DECL(DISP0_DAT18__AUD5_TXFS,	0x03EC, 0x00D8, 3, 0x07C4, 0, 0)
+MX6_PAD_DECL(DISP0_DAT18__AUD4_RXFS,	0x03EC, 0x00D8, 4, 0x07A4, 0, 0)
+MX6_PAD_DECL(DISP0_DAT18__GPIO5_IO12,	0x03EC, 0x00D8, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT18__EIM_CS2_B,	0x03EC, 0x00D8, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT19__IPU1_DISP0_DATA19,	0x03F0, 0x00DC, 0, 0x0000, 0, PAD_CTL_DSE_120ohm)
+MX6_PAD_DECL(DISP0_DAT19__LCD_DATA19,	0x03F0, 0x00DC, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT19__ECSPI2_SCLK,	0x03F0, 0x00DC, 2, 0x07F4, 1, 0)
+MX6_PAD_DECL(DISP0_DAT19__AUD5_RXD,	0x03F0, 0x00DC, 3, 0x07B0, 0, 0)
+MX6_PAD_DECL(DISP0_DAT19__AUD4_RXC,	0x03F0, 0x00DC, 4, 0x07A0, 0, 0)
+MX6_PAD_DECL(DISP0_DAT19__GPIO5_IO13,	0x03F0, 0x00DC, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT19__EIM_CS3_B,	0x03F0, 0x00DC, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT2__IPU1_DISP0_DATA02,	0x03F4, 0x00E0, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT2__LCD_DATA02,	0x03F4, 0x00E0, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT2__ECSPI3_MISO,	0x03F4, 0x00E0, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT2__GPIO4_IO23,	0x03F4, 0x00E0, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT20__IPU1_DISP0_DATA20,	0x03F8, 0x00E4, 0, 0x0000, 0, PAD_CTL_DSE_120ohm)
+MX6_PAD_DECL(DISP0_DAT20__LCD_DATA20,	0x03F8, 0x00E4, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT20__ECSPI1_SCLK,	0x03F8, 0x00E4, 2, 0x07D8, 1, 0)
+MX6_PAD_DECL(DISP0_DAT20__AUD4_TXC,	0x03F8, 0x00E4, 3, 0x07A8, 0, 0)
+MX6_PAD_DECL(DISP0_DAT20__GPIO5_IO14,	0x03F8, 0x00E4, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT21__IPU1_DISP0_DATA21,	0x03FC, 0x00E8, 0, 0x0000, 0, PAD_CTL_DSE_120ohm)
+MX6_PAD_DECL(DISP0_DAT21__LCD_DATA21,	0x03FC, 0x00E8, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT21__ECSPI1_MOSI,	0x03FC, 0x00E8, 2, 0x07E0, 1, 0)
+MX6_PAD_DECL(DISP0_DAT21__AUD4_TXD,	0x03FC, 0x00E8, 3, 0x079C, 0, 0)
+MX6_PAD_DECL(DISP0_DAT21__GPIO5_IO15,	0x03FC, 0x00E8, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT22__IPU1_DISP0_DATA22,	0x0400, 0x00EC, 0, 0x0000, 0, PAD_CTL_DSE_120ohm)
+MX6_PAD_DECL(DISP0_DAT22__LCD_DATA22,	0x0400, 0x00EC, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT22__ECSPI1_MISO,	0x0400, 0x00EC, 2, 0x07DC, 1, 0)
+MX6_PAD_DECL(DISP0_DAT22__AUD4_TXFS,	0x0400, 0x00EC, 3, 0x07AC, 0, 0)
+MX6_PAD_DECL(DISP0_DAT22__GPIO5_IO16,	0x0400, 0x00EC, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT23__IPU1_DISP0_DATA23,	0x0404, 0x00F0, 0, 0x0000, 0, PAD_CTL_DSE_120ohm)
+MX6_PAD_DECL(DISP0_DAT23__LCD_DATA23,	0x0404, 0x00F0, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT23__ECSPI1_SS0,	0x0404, 0x00F0, 2, 0x07E4, 1, 0)
+MX6_PAD_DECL(DISP0_DAT23__AUD4_RXD,	0x0404, 0x00F0, 3, 0x0798, 0, 0)
+MX6_PAD_DECL(DISP0_DAT23__GPIO5_IO17,	0x0404, 0x00F0, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT3__IPU1_DISP0_DATA03,	0x0408, 0x00F4, 0, 0x0000, 0, PAD_CTL_DSE_120ohm)
+MX6_PAD_DECL(DISP0_DAT3__LCD_DATA03,	0x0408, 0x00F4, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT3__ECSPI3_SS0,	0x0408, 0x00F4, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT3__GPIO4_IO24,	0x0408, 0x00F4, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT4__IPU1_DISP0_DATA04,	0x040C, 0x00F8, 0, 0x0000, 0, PAD_CTL_DSE_120ohm)
+MX6_PAD_DECL(DISP0_DAT4__LCD_DATA04,	0x040C, 0x00F8, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT4__ECSPI3_SS1,	0x040C, 0x00F8, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT4__GPIO4_IO25,	0x040C, 0x00F8, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT5__IPU1_DISP0_DATA05,	0x0410, 0x00FC, 0, 0x0000, 0, PAD_CTL_DSE_120ohm)
+MX6_PAD_DECL(DISP0_DAT5__LCD_DATA05,	0x0410, 0x00FC, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT5__ECSPI3_SS2,	0x0410, 0x00FC, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT5__AUD6_RXFS,	0x0410, 0x00FC, 3, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT5__GPIO4_IO26,	0x0410, 0x00FC, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT6__IPU1_DISP0_DATA06,	0x0414, 0x0100, 0, 0x0000, 0, PAD_CTL_DSE_120ohm)
+MX6_PAD_DECL(DISP0_DAT6__LCD_DATA06,	0x0414, 0x0100, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT6__ECSPI3_SS3,	0x0414, 0x0100, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT6__AUD6_RXC,	0x0414, 0x0100, 3, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT6__GPIO4_IO27,	0x0414, 0x0100, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT7__IPU1_DISP0_DATA07,	0x0418, 0x0104, 0, 0x0000, 0, PAD_CTL_DSE_120ohm)
+MX6_PAD_DECL(DISP0_DAT7__LCD_DATA07,	0x0418, 0x0104, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT7__ECSPI3_RDY,	0x0418, 0x0104, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT7__GPIO4_IO28,	0x0418, 0x0104, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT8__IPU1_DISP0_DATA08,	0x041C, 0x0108, 0, 0x0000, 0, PAD_CTL_DSE_120ohm)
+MX6_PAD_DECL(DISP0_DAT8__LCD_DATA08,	0x041C, 0x0108, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT8__PWM1_OUT,	0x041C, 0x0108, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT8__WDOG1_B,	0x041C, 0x0108, 3, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT8__GPIO4_IO29,	0x041C, 0x0108, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT9__IPU1_DISP0_DATA09,	0x0420, 0x010C, 0, 0x0000, 0, PAD_CTL_DSE_120ohm)
+MX6_PAD_DECL(DISP0_DAT9__LCD_DATA09,	0x0420, 0x010C, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT9__PWM2_OUT,	0x0420, 0x010C, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT9__WDOG2_B,	0x0420, 0x010C, 3, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT9__GPIO4_IO30,	0x0420, 0x010C, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_A16__EIM_ADDR16,	0x04E0, 0x0110, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_A16__IPU1_DI1_DISP_CLK,	0x04E0, 0x0110, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_A16__IPU1_CSI1_PIXCLK,	0x04E0, 0x0110, 2, 0x08B8, 0, 0)
+MX6_PAD_DECL(EIM_A16__GPIO2_IO22,	0x04E0, 0x0110, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_A16__SRC_BOOT_CFG16,	0x04E0, 0x0110, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_A16__EPDC_DATA00,	0x04E0, 0x0110, 8, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_A17__EIM_ADDR17,	0x04E4, 0x0114, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_A17__IPU1_DISP1_DATA12,	0x04E4, 0x0114, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_A17__IPU1_CSI1_DATA12,	0x04E4, 0x0114, 2, 0x0890, 0, 0)
+MX6_PAD_DECL(EIM_A17__GPIO2_IO21,	0x04E4, 0x0114, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_A17__SRC_BOOT_CFG17,	0x04E4, 0x0114, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_A17__EPDC_PWR_STAT,	0x04E4, 0x0114, 8, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_A18__EIM_ADDR18,	0x04E8, 0x0118, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_A18__IPU1_DISP1_DATA13,	0x04E8, 0x0118, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_A18__IPU1_CSI1_DATA13,	0x04E8, 0x0118, 2, 0x0894, 0, 0)
+MX6_PAD_DECL(EIM_A18__GPIO2_IO20,	0x04E8, 0x0118, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_A18__SRC_BOOT_CFG18,	0x04E8, 0x0118, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_A18__EPDC_PWR_CTRL0,	0x04E8, 0x0118, 8, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_A19__EIM_ADDR19,	0x04EC, 0x011C, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_A19__IPU1_DISP1_DATA14,	0x04EC, 0x011C, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_A19__IPU1_CSI1_DATA14,	0x04EC, 0x011C, 2, 0x0898, 0, 0)
+MX6_PAD_DECL(EIM_A19__GPIO2_IO19,	0x04EC, 0x011C, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_A19__SRC_BOOT_CFG19,	0x04EC, 0x011C, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_A19__EPDC_PWR_CTRL1,	0x04EC, 0x011C, 8, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_A20__EIM_ADDR20,	0x04F0, 0x0120, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_A20__IPU1_DISP1_DATA15,	0x04F0, 0x0120, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_A20__IPU1_CSI1_DATA15,	0x04F0, 0x0120, 2, 0x089C, 0, 0)
+MX6_PAD_DECL(EIM_A20__GPIO2_IO18,	0x04F0, 0x0120, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_A20__SRC_BOOT_CFG20,	0x04F0, 0x0120, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_A20__EPDC_PWR_CTRL2,	0x04F0, 0x0120, 8, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_A21__EIM_ADDR21,	0x04F4, 0x0124, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_A21__IPU1_DISP1_DATA16,	0x04F4, 0x0124, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_A21__IPU1_CSI1_DATA16,	0x04F4, 0x0124, 2, 0x08A0, 0, 0)
+MX6_PAD_DECL(EIM_A21__GPIO2_IO17,	0x04F4, 0x0124, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_A21__SRC_BOOT_CFG21,	0x04F4, 0x0124, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_A21__EPDC_GDCLK,	0x04F4, 0x0124, 8, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_A22__EIM_ADDR22,	0x04F8, 0x0128, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_A22__IPU1_DISP1_DATA17,	0x04F8, 0x0128, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_A22__IPU1_CSI1_DATA17,	0x04F8, 0x0128, 2, 0x08A4, 0, 0)
+MX6_PAD_DECL(EIM_A22__GPIO2_IO16,	0x04F8, 0x0128, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_A22__SRC_BOOT_CFG22,	0x04F8, 0x0128, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_A22__EPDC_GDSP,	0x04F8, 0x0128, 8, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_A23__EIM_ADDR23,	0x04FC, 0x012C, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_A23__IPU1_DISP1_DATA18,	0x04FC, 0x012C, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_A23__IPU1_CSI1_DATA18,	0x04FC, 0x012C, 2, 0x08A8, 0, 0)
+MX6_PAD_DECL(EIM_A23__IPU1_SISG3,	0x04FC, 0x012C, 4, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_A23__GPIO6_IO06,	0x04FC, 0x012C, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_A23__SRC_BOOT_CFG23,	0x04FC, 0x012C, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_A23__EPDC_GDOE,	0x04FC, 0x012C, 8, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_A24__EIM_ADDR24,	0x0500, 0x0130, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_A24__IPU1_DISP1_DATA19,	0x0500, 0x0130, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_A24__IPU1_CSI1_DATA19,	0x0500, 0x0130, 2, 0x08AC, 0, 0)
+MX6_PAD_DECL(EIM_A24__IPU1_SISG2,	0x0500, 0x0130, 4, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_A24__GPIO5_IO04,	0x0500, 0x0130, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_A24__SRC_BOOT_CFG24,	0x0500, 0x0130, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_A24__EPDC_GDRL,	0x0500, 0x0130, 8, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_A25__EIM_ADDR25,	0x0504, 0x0134, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_A25__ECSPI4_SS1,	0x0504, 0x0134, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_A25__ECSPI2_RDY,	0x0504, 0x0134, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_A25__IPU1_DI1_PIN12,	0x0504, 0x0134, 3, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_A25__IPU1_DI0_D1_CS,	0x0504, 0x0134, 4, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_A25__GPIO5_IO02,	0x0504, 0x0134, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_A25__HDMI_TX_CEC_LINE,	0x0504, 0x0134, 6, 0x085C, 0, 0)
+MX6_PAD_DECL(EIM_A25__EPDC_DATA15,	0x0504, 0x0134, 8, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_A25__EIM_ACLK_FREERUN,	0x0504, 0x0134, 9, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_BCLK__EIM_BCLK,	0x0508, 0x0138, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_BCLK__IPU1_DI1_PIN16,	0x0508, 0x0138, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_BCLK__GPIO6_IO31,	0x0508, 0x0138, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_BCLK__EPDC_SDCE9,	0x0508, 0x0138, 8, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_CS0__EIM_CS0_B,	0x050C, 0x013C, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_CS0__IPU1_DI1_PIN05,	0x050C, 0x013C, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_CS0__ECSPI2_SCLK,	0x050C, 0x013C, 2, 0x07F4, 2, 0)
+MX6_PAD_DECL(EIM_CS0__GPIO2_IO23,	0x050C, 0x013C, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_CS0__EPDC_DATA06,	0x050C, 0x013C, 8, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_CS1__EIM_CS1_B,	0x0510, 0x0140, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_CS1__IPU1_DI1_PIN06,	0x0510, 0x0140, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_CS1__ECSPI2_MOSI,	0x0510, 0x0140, 2, 0x07FC, 2, 0)
+MX6_PAD_DECL(EIM_CS1__GPIO2_IO24,	0x0510, 0x0140, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_CS1__EPDC_DATA08,	0x0510, 0x0140, 8, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D16__EIM_DATA16,	0x0514, 0x0144, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D16__ECSPI1_SCLK,	0x0514, 0x0144, 1, 0x07D8, 2, 0)
+MX6_PAD_DECL(EIM_D16__IPU1_DI0_PIN05,	0x0514, 0x0144, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D16__IPU1_CSI1_DATA18,	0x0514, 0x0144, 3, 0x08A8, 1, 0)
+MX6_PAD_DECL(EIM_D16__HDMI_TX_DDC_SDA,	0x0514, 0x0144, 4, 0x0864, 0, 0)
+MX6_PAD_DECL(EIM_D16__GPIO3_IO16,	0x0514, 0x0144, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D16__I2C2_SDA,	0x0514, 0x0144, 6 | IOMUX_CONFIG_SION, 0x0874, 0, 0)
+MX6_PAD_DECL(EIM_D16__EPDC_DATA10,	0x0514, 0x0144, 8, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D17__EIM_DATA17,	0x0518, 0x0148, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D17__ECSPI1_MISO,	0x0518, 0x0148, 1, 0x07DC, 2, 0)
+MX6_PAD_DECL(EIM_D17__IPU1_DI0_PIN06,	0x0518, 0x0148, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D17__IPU1_CSI1_PIXCLK,	0x0518, 0x0148, 3, 0x08B8, 1, 0)
+MX6_PAD_DECL(EIM_D17__DCIC1_OUT,	0x0518, 0x0148, 4, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D17__GPIO3_IO17,	0x0518, 0x0148, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D17__I2C3_SCL,	0x0518, 0x0148, 6 | IOMUX_CONFIG_SION, 0x0878, 0, 0)
+MX6_PAD_DECL(EIM_D17__EPDC_VCOM0,	0x0518, 0x0148, 8, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D18__EIM_DATA18,	0x051C, 0x014C, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D18__ECSPI1_MOSI,	0x051C, 0x014C, 1, 0x07E0, 2, 0)
+MX6_PAD_DECL(EIM_D18__IPU1_DI0_PIN07,	0x051C, 0x014C, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D18__IPU1_CSI1_DATA17,	0x051C, 0x014C, 3, 0x08A4, 1, 0)
+MX6_PAD_DECL(EIM_D18__IPU1_DI1_D0_CS,	0x051C, 0x014C, 4, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D18__GPIO3_IO18,	0x051C, 0x014C, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D18__I2C3_SDA,	0x051C, 0x014C, 6 | IOMUX_CONFIG_SION, 0x087C, 0, 0)
+MX6_PAD_DECL(EIM_D18__EPDC_VCOM1,	0x051C, 0x014C, 8, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D19__EIM_DATA19,	0x0520, 0x0150, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D19__ECSPI1_SS1,	0x0520, 0x0150, 1, 0x07E8, 1, 0)
+MX6_PAD_DECL(EIM_D19__IPU1_DI0_PIN08,	0x0520, 0x0150, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D19__IPU1_CSI1_DATA16,	0x0520, 0x0150, 3, 0x08A0, 1, 0)
+MX6_PAD_DECL(EIM_D19__UART1_CTS_B,	0x0520, 0x0150, 4, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D19__UART1_RTS_B,	0x0520, 0x0150, 4, 0x08F8, 0, 0)
+MX6_PAD_DECL(EIM_D19__GPIO3_IO19,	0x0520, 0x0150, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D19__EPIT1_OUT,	0x0520, 0x0150, 6, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D19__EPDC_DATA12,	0x0520, 0x0150, 8, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D20__EIM_DATA20,	0x0524, 0x0154, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D20__ECSPI4_SS0,	0x0524, 0x0154, 1, 0x0808, 0, 0)
+MX6_PAD_DECL(EIM_D20__IPU1_DI0_PIN16,	0x0524, 0x0154, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D20__IPU1_CSI1_DATA15,	0x0524, 0x0154, 3, 0x089C, 1, 0)
+MX6_PAD_DECL(EIM_D20__UART1_CTS_B,	0x0524, 0x0154, 4, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D20__UART1_RTS_B,	0x0524, 0x0154, 4, 0x08F8, 1, 0)
+MX6_PAD_DECL(EIM_D20__GPIO3_IO20,	0x0524, 0x0154, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D20__EPIT2_OUT,	0x0524, 0x0154, 6, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D21__EIM_DATA21,	0x0528, 0x0158, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D21__ECSPI4_SCLK,	0x0528, 0x0158, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D21__IPU1_DI0_PIN17,	0x0528, 0x0158, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D21__IPU1_CSI1_DATA11,	0x0528, 0x0158, 3, 0x088C, 0, 0)
+MX6_PAD_DECL(EIM_D21__USB_OTG_OC,	0x0528, 0x0158, 4, 0x0920, 0, 0)
+MX6_PAD_DECL(EIM_D21__GPIO3_IO21,	0x0528, 0x0158, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D21__I2C1_SCL,	0x0528, 0x0158, 6 | IOMUX_CONFIG_SION, 0x0868, 1, 0)
+MX6_PAD_DECL(EIM_D21__SPDIF_IN,	0x0528, 0x0158, 7, 0x08F0, 0, 0)
+MX6_PAD_DECL(EIM_D22__EIM_DATA22,	0x052C, 0x015C, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D22__ECSPI4_MISO,	0x052C, 0x015C, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D22__IPU1_DI0_PIN01,	0x052C, 0x015C, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D22__IPU1_CSI1_DATA10,	0x052C, 0x015C, 3, 0x0888, 0, 0)
+MX6_PAD_DECL(EIM_D22__USB_OTG_PWR,	0x052C, 0x015C, 4, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D22__GPIO3_IO22,	0x052C, 0x015C, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D22__SPDIF_OUT,	0x052C, 0x015C, 6, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D22__EPDC_SDCE6,	0x052C, 0x015C, 8, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D23__EIM_DATA23,	0x0530, 0x0160, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D23__IPU1_DI0_D0_CS,	0x0530, 0x0160, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D23__UART3_CTS_B,	0x0530, 0x0160, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D23__UART3_RTS_B,	0x0530, 0x0160, 2, 0x0908, 0, 0)
+MX6_PAD_DECL(EIM_D23__UART1_DCD_B,	0x0530, 0x0160, 3, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D23__IPU1_CSI1_DATA_EN,	0x0530, 0x0160, 4, 0x08B0, 0, 0)
+MX6_PAD_DECL(EIM_D23__GPIO3_IO23,	0x0530, 0x0160, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D23__IPU1_DI1_PIN02,	0x0530, 0x0160, 6, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D23__IPU1_DI1_PIN14,	0x0530, 0x0160, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D23__EPDC_DATA11,	0x0530, 0x0160, 8, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D24__EIM_DATA24,	0x0534, 0x0164, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D24__ECSPI4_SS2,	0x0534, 0x0164, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D24__UART3_TX_DATA,	0x0534, 0x0164, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D24__UART3_RX_DATA,	0x0534, 0x0164, 2, 0x090C, 0, 0)
+MX6_PAD_DECL(EIM_D24__ECSPI1_SS2,	0x0534, 0x0164, 3, 0x07EC, 0, 0)
+MX6_PAD_DECL(EIM_D24__ECSPI2_SS2,	0x0534, 0x0164, 4, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D24__GPIO3_IO24,	0x0534, 0x0164, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D24__AUD5_RXFS,	0x0534, 0x0164, 6, 0x07BC, 1, 0)
+MX6_PAD_DECL(EIM_D24__UART1_DTR_B,	0x0534, 0x0164, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D24__EPDC_SDCE7,	0x0534, 0x0164, 8, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D25__EIM_DATA25,	0x0538, 0x0168, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D25__ECSPI4_SS3,	0x0538, 0x0168, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D25__UART3_TX_DATA,	0x0538, 0x0168, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D25__UART3_RX_DATA,	0x0538, 0x0168, 2, 0x090C, 1, 0)
+MX6_PAD_DECL(EIM_D25__ECSPI1_SS3,	0x0538, 0x0168, 3, 0x07F0, 0, 0)
+MX6_PAD_DECL(EIM_D25__ECSPI2_SS3,	0x0538, 0x0168, 4, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D25__GPIO3_IO25,	0x0538, 0x0168, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D25__AUD5_RXC,	0x0538, 0x0168, 6, 0x07B8, 1, 0)
+MX6_PAD_DECL(EIM_D25__UART1_DSR_B,	0x0538, 0x0168, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D25__EPDC_SDCE8,	0x0538, 0x0168, 8, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D26__EIM_DATA26,	0x053C, 0x016C, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D26__IPU1_DI1_PIN11,	0x053C, 0x016C, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D26__IPU1_CSI0_DATA01,	0x053C, 0x016C, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D26__IPU1_CSI1_DATA14,	0x053C, 0x016C, 3, 0x0898, 1, 0)
+MX6_PAD_DECL(EIM_D26__UART2_TX_DATA,	0x053C, 0x016C, 4, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D26__UART2_RX_DATA,	0x053C, 0x016C, 4, 0x0904, 0, 0)
+MX6_PAD_DECL(EIM_D26__GPIO3_IO26,	0x053C, 0x016C, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D26__IPU1_SISG2,	0x053C, 0x016C, 6, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D26__IPU1_DISP1_DATA22,	0x053C, 0x016C, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D26__EPDC_SDOED,	0x053C, 0x016C, 8, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D27__EIM_DATA27,	0x0540, 0x0170, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D27__IPU1_DI1_PIN13,	0x0540, 0x0170, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D27__IPU1_CSI0_DATA00,	0x0540, 0x0170, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D27__IPU1_CSI1_DATA13,	0x0540, 0x0170, 3, 0x0894, 1, 0)
+MX6_PAD_DECL(EIM_D27__UART2_TX_DATA,	0x0540, 0x0170, 4, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D27__UART2_RX_DATA,	0x0540, 0x0170, 4, 0x0904, 1, 0)
+MX6_PAD_DECL(EIM_D27__GPIO3_IO27,	0x0540, 0x0170, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D27__IPU1_SISG3,	0x0540, 0x0170, 6, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D27__IPU1_DISP1_DATA23,	0x0540, 0x0170, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D27__EPDC_SDOE,	0x0540, 0x0170, 8, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D28__EIM_DATA28,	0x0544, 0x0174, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D28__I2C1_SDA,	0x0544, 0x0174, 1 | IOMUX_CONFIG_SION, 0x086C, 1, 0)
+MX6_PAD_DECL(EIM_D28__ECSPI4_MOSI,	0x0544, 0x0174, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D28__IPU1_CSI1_DATA12,	0x0544, 0x0174, 3, 0x0890, 1, 0)
+MX6_PAD_DECL(EIM_D28__UART2_DTE_RTS_B,	0x0544, 0x0174, 4, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D28__UART2_DTE_CTS_B,	0x0544, 0x0174, 4, 0x0900, 0, 0)
+MX6_PAD_DECL(EIM_D28__GPIO3_IO28,	0x0544, 0x0174, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D28__IPU1_EXT_TRIG,	0x0544, 0x0174, 6, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D28__IPU1_DI0_PIN13,	0x0544, 0x0174, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D28__EPDC_PWR_CTRL3,	0x0544, 0x0174, 8, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D29__EIM_DATA29,	0x0548, 0x0178, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D29__IPU1_DI1_PIN15,	0x0548, 0x0178, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D29__ECSPI4_SS0,	0x0548, 0x0178, 2, 0x0808, 1, 0)
+MX6_PAD_DECL(EIM_D29__UART2_CTS_B,	0x0548, 0x0178, 4, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D29__UART2_RTS_B,	0x0548, 0x0178, 4, 0x0900, 1, 0)
+MX6_PAD_DECL(EIM_D29__GPIO3_IO29,	0x0548, 0x0178, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D29__IPU1_CSI1_VSYNC,	0x0548, 0x0178, 6, 0x08BC, 0, 0)
+MX6_PAD_DECL(EIM_D29__IPU1_DI0_PIN14,	0x0548, 0x0178, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D29__EPDC_PWR_WAKE,	0x0548, 0x0178, 8, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D30__EIM_DATA30,	0x054C, 0x017C, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D30__IPU1_DISP1_DATA21,	0x054C, 0x017C, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D30__IPU1_DI0_PIN11,	0x054C, 0x017C, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D30__IPU1_CSI0_DATA03,	0x054C, 0x017C, 3, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D30__UART3_CTS_B,	0x054C, 0x017C, 4, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D30__UART3_RTS_B,	0x054C, 0x017C, 4, 0x0908, 1, 0)
+MX6_PAD_DECL(EIM_D30__GPIO3_IO30,	0x054C, 0x017C, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D30__USB_H1_OC,	0x054C, 0x017C, 6, 0x0924, 0, 0)
+MX6_PAD_DECL(EIM_D30__EPDC_SDOEZ,	0x054C, 0x017C, 8, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D31__EIM_DATA31,	0x0550, 0x0180, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D31__IPU1_DISP1_DATA20,	0x0550, 0x0180, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D31__IPU1_DI0_PIN12,	0x0550, 0x0180, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D31__IPU1_CSI0_DATA02,	0x0550, 0x0180, 3, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D31__UART3_CTS_B,	0x0550, 0x0180, 4, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D31__UART3_RTS_B,	0x0550, 0x0180, 4, 0x0908, 2, 0)
+MX6_PAD_DECL(EIM_D31__GPIO3_IO31,	0x0550, 0x0180, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D31__USB_H1_PWR,	0x0550, 0x0180, 6, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D31__EPDC_SDCLK_P,	0x0550, 0x0180, 8, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D31__EIM_ACLK_FREERUN,	0x0550, 0x0180, 9, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA0__EIM_AD00,	0x0554, 0x0184, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA0__IPU1_DISP1_DATA09,	0x0554, 0x0184, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA0__IPU1_CSI1_DATA09,	0x0554, 0x0184, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA0__GPIO3_IO00,	0x0554, 0x0184, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA0__SRC_BOOT_CFG00,	0x0554, 0x0184, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA0__EPDC_SDCLK_N,	0x0554, 0x0184, 8, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA1__EIM_AD01,	0x0558, 0x0188, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA1__IPU1_DISP1_DATA08,	0x0558, 0x0188, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA1__IPU1_CSI1_DATA08,	0x0558, 0x0188, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA1__GPIO3_IO01,	0x0558, 0x0188, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA1__SRC_BOOT_CFG01,	0x0558, 0x0188, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA1__EPDC_SDLE,	0x0558, 0x0188, 8, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA10__EIM_AD10,	0x055C, 0x018C, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA10__IPU1_DI1_PIN15,	0x055C, 0x018C, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA10__IPU1_CSI1_DATA_EN,	0x055C, 0x018C, 2, 0x08B0, 1, 0)
+MX6_PAD_DECL(EIM_DA10__GPIO3_IO10,	0x055C, 0x018C, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA10__SRC_BOOT_CFG10,	0x055C, 0x018C, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA10__EPDC_DATA01,	0x055C, 0x018C, 8, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA11__EIM_AD11,	0x0560, 0x0190, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA11__IPU1_DI1_PIN02,	0x0560, 0x0190, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA11__IPU1_CSI1_HSYNC,	0x0560, 0x0190, 2, 0x08B4, 0, 0)
+MX6_PAD_DECL(EIM_DA11__GPIO3_IO11,	0x0560, 0x0190, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA11__SRC_BOOT_CFG11,	0x0560, 0x0190, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA11__EPDC_DATA03,	0x0560, 0x0190, 8, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA12__EIM_AD12,	0x0564, 0x0194, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA12__IPU1_DI1_PIN03,	0x0564, 0x0194, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA12__IPU1_CSI1_VSYNC,	0x0564, 0x0194, 2, 0x08BC, 1, 0)
+MX6_PAD_DECL(EIM_DA12__GPIO3_IO12,	0x0564, 0x0194, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA12__SRC_BOOT_CFG12,	0x0564, 0x0194, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA12__EPDC_DATA02,	0x0564, 0x0194, 8, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA13__EIM_AD13,	0x0568, 0x0198, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA13__IPU1_DI1_D0_CS,	0x0568, 0x0198, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA13__GPIO3_IO13,	0x0568, 0x0198, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA13__SRC_BOOT_CFG13,	0x0568, 0x0198, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA13__EPDC_DATA13,	0x0568, 0x0198, 8, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA14__EIM_AD14,	0x056C, 0x019C, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA14__IPU1_DI1_D1_CS,	0x056C, 0x019C, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA14__GPIO3_IO14,	0x056C, 0x019C, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA14__SRC_BOOT_CFG14,	0x056C, 0x019C, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA14__EPDC_DATA14,	0x056C, 0x019C, 8, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA15__EIM_AD15,	0x0570, 0x01A0, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA15__IPU1_DI1_PIN01,	0x0570, 0x01A0, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA15__IPU1_DI1_PIN04,	0x0570, 0x01A0, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA15__GPIO3_IO15,	0x0570, 0x01A0, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA15__SRC_BOOT_CFG15,	0x0570, 0x01A0, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA15__EPDC_DATA09,	0x0570, 0x01A0, 8, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA2__EIM_AD02,	0x0574, 0x01A4, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA2__IPU1_DISP1_DATA07,	0x0574, 0x01A4, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA2__IPU1_CSI1_DATA07,	0x0574, 0x01A4, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA2__GPIO3_IO02,	0x0574, 0x01A4, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA2__SRC_BOOT_CFG02,	0x0574, 0x01A4, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA2__EPDC_BDR0,	0x0574, 0x01A4, 8, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA3__EIM_AD03,	0x0578, 0x01A8, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA3__IPU1_DISP1_DATA06,	0x0578, 0x01A8, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA3__IPU1_CSI1_DATA06,	0x0578, 0x01A8, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA3__GPIO3_IO03,	0x0578, 0x01A8, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA3__SRC_BOOT_CFG03,	0x0578, 0x01A8, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA3__EPDC_BDR1,	0x0578, 0x01A8, 8, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA4__EIM_AD04,	0x057C, 0x01AC, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA4__IPU1_DISP1_DATA05,	0x057C, 0x01AC, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA4__IPU1_CSI1_DATA05,	0x057C, 0x01AC, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA4__GPIO3_IO04,	0x057C, 0x01AC, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA4__SRC_BOOT_CFG04,	0x057C, 0x01AC, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA4__EPDC_SDCE0,	0x057C, 0x01AC, 8, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA5__EIM_AD05,	0x0580, 0x01B0, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA5__IPU1_DISP1_DATA04,	0x0580, 0x01B0, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA5__IPU1_CSI1_DATA04,	0x0580, 0x01B0, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA5__GPIO3_IO05,	0x0580, 0x01B0, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA5__SRC_BOOT_CFG05,	0x0580, 0x01B0, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA5__EPDC_SDCE1,	0x0580, 0x01B0, 8, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA6__EIM_AD06,	0x0584, 0x01B4, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA6__IPU1_DISP1_DATA03,	0x0584, 0x01B4, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA6__IPU1_CSI1_DATA03,	0x0584, 0x01B4, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA6__GPIO3_IO06,	0x0584, 0x01B4, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA6__SRC_BOOT_CFG06,	0x0584, 0x01B4, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA6__EPDC_SDCE2,	0x0584, 0x01B4, 8, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA7__EIM_AD07,	0x0588, 0x01B8, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA7__IPU1_DISP1_DATA02,	0x0588, 0x01B8, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA7__IPU1_CSI1_DATA02,	0x0588, 0x01B8, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA7__GPIO3_IO07,	0x0588, 0x01B8, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA7__SRC_BOOT_CFG07,	0x0588, 0x01B8, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA7__EPDC_SDCE3,	0x0588, 0x01B8, 8, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA8__EIM_AD08,	0x058C, 0x01BC, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA8__IPU1_DISP1_DATA01,	0x058C, 0x01BC, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA8__IPU1_CSI1_DATA01,	0x058C, 0x01BC, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA8__GPIO3_IO08,	0x058C, 0x01BC, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA8__SRC_BOOT_CFG08,	0x058C, 0x01BC, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA8__EPDC_SDCE4,	0x058C, 0x01BC, 8, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA9__EIM_AD09,	0x0590, 0x01C0, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA9__IPU1_DISP1_DATA00,	0x0590, 0x01C0, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA9__IPU1_CSI1_DATA00,	0x0590, 0x01C0, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA9__GPIO3_IO09,	0x0590, 0x01C0, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA9__SRC_BOOT_CFG09,	0x0590, 0x01C0, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA9__EPDC_SDCE5,	0x0590, 0x01C0, 8, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_EB0__EIM_EB0_B,	0x0594, 0x01C4, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_EB0__IPU1_DISP1_DATA11,	0x0594, 0x01C4, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_EB0__IPU1_CSI1_DATA11,	0x0594, 0x01C4, 2, 0x088C, 1, 0)
+MX6_PAD_DECL(EIM_EB0__CCM_PMIC_READY,	0x0594, 0x01C4, 4, 0x07D4, 0, 0)
+MX6_PAD_DECL(EIM_EB0__GPIO2_IO28,	0x0594, 0x01C4, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_EB0__SRC_BOOT_CFG27,	0x0594, 0x01C4, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_EB0__EPDC_PWR_COM,	0x0594, 0x01C4, 8, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_EB1__EIM_EB1_B,	0x0598, 0x01C8, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_EB1__IPU1_DISP1_DATA10,	0x0598, 0x01C8, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_EB1__IPU1_CSI1_DATA10,	0x0598, 0x01C8, 2, 0x0888, 1, 0)
+MX6_PAD_DECL(EIM_EB1__GPIO2_IO29,	0x0598, 0x01C8, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_EB1__SRC_BOOT_CFG28,	0x0598, 0x01C8, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_EB1__EPDC_SDSHR,	0x0598, 0x01C8, 8, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_EB2__EIM_EB2_B,	0x059C, 0x01CC, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_EB2__ECSPI1_SS0,	0x059C, 0x01CC, 1, 0x07E4, 2, 0)
+MX6_PAD_DECL(EIM_EB2__IPU1_CSI1_DATA19,	0x059C, 0x01CC, 3, 0x08AC, 1, 0)
+MX6_PAD_DECL(EIM_EB2__HDMI_TX_DDC_SCL,	0x059C, 0x01CC, 4, 0x0860, 0, 0)
+MX6_PAD_DECL(EIM_EB2__GPIO2_IO30,	0x059C, 0x01CC, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_EB2__I2C2_SCL,	0x059C, 0x01CC, 6 | IOMUX_CONFIG_SION, 0x0870, 0, 0)
+MX6_PAD_DECL(EIM_EB2__SRC_BOOT_CFG30,	0x059C, 0x01CC, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_EB2__EPDC_DATA05,	0x059C, 0x01CC, 8, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_EB3__EIM_EB3_B,	0x05A0, 0x01D0, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_EB3__ECSPI4_RDY,	0x05A0, 0x01D0, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_EB3__UART3_CTS_B,	0x05A0, 0x01D0, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_EB3__UART3_RTS_B,	0x05A0, 0x01D0, 2, 0x0908, 3, 0)
+MX6_PAD_DECL(EIM_EB3__UART1_RI_B,	0x05A0, 0x01D0, 3, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_EB3__IPU1_CSI1_HSYNC,	0x05A0, 0x01D0, 4, 0x08B4, 1, 0)
+MX6_PAD_DECL(EIM_EB3__GPIO2_IO31,	0x05A0, 0x01D0, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_EB3__IPU1_DI1_PIN03,	0x05A0, 0x01D0, 6, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_EB3__SRC_BOOT_CFG31,	0x05A0, 0x01D0, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_EB3__EPDC_SDCE0,	0x05A0, 0x01D0, 8, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_EB3__EIM_ACLK_FREERUN,	0x05A0, 0x01D0, 9, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_LBA__EIM_LBA_B,	0x05A4, 0x01D4, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_LBA__IPU1_DI1_PIN17,	0x05A4, 0x01D4, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_LBA__ECSPI2_SS1,	0x05A4, 0x01D4, 2, 0x0804, 1, 0)
+MX6_PAD_DECL(EIM_LBA__GPIO2_IO27,	0x05A4, 0x01D4, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_LBA__SRC_BOOT_CFG26,	0x05A4, 0x01D4, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_LBA__EPDC_DATA04,	0x05A4, 0x01D4, 8, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_OE__EIM_OE_B,	0x05A8, 0x01D8, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_OE__IPU1_DI1_PIN07,	0x05A8, 0x01D8, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_OE__ECSPI2_MISO,	0x05A8, 0x01D8, 2, 0x07F8, 2, 0)
+MX6_PAD_DECL(EIM_OE__GPIO2_IO25,	0x05A8, 0x01D8, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_OE__EPDC_PWR_IRQ,	0x05A8, 0x01D8, 8, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_RW__EIM_RW,	0x05AC, 0x01DC, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_RW__IPU1_DI1_PIN08,	0x05AC, 0x01DC, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_RW__ECSPI2_SS0,	0x05AC, 0x01DC, 2, 0x0800, 2, 0)
+MX6_PAD_DECL(EIM_RW__GPIO2_IO26,	0x05AC, 0x01DC, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_RW__SRC_BOOT_CFG29,	0x05AC, 0x01DC, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_RW__EPDC_DATA07,	0x05AC, 0x01DC, 8, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_WAIT__EIM_WAIT_B,	0x05B0, 0x01E0, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_WAIT__EIM_DTACK_B,	0x05B0, 0x01E0, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_WAIT__GPIO5_IO00,	0x05B0, 0x01E0, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_WAIT__SRC_BOOT_CFG25,	0x05B0, 0x01E0, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(ENET_CRS_DV__ENET_RX_EN,	0x05B4, 0x01E4, 1, 0x0828, 0, 0)
+MX6_PAD_DECL(ENET_CRS_DV__ESAI_TX_CLK,	0x05B4, 0x01E4, 2, 0x0840, 0, 0)
+MX6_PAD_DECL(ENET_CRS_DV__SPDIF_EXT_CLK,	0x05B4, 0x01E4, 3, 0x08F4, 0, 0)
+MX6_PAD_DECL(ENET_CRS_DV__GPIO1_IO25,	0x05B4, 0x01E4, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(ENET_MDC__MLB_DATA,	0x05B8, 0x01E8, 0, 0x08E0, 0, 0)
+MX6_PAD_DECL(ENET_MDC__ENET_MDC,	0x05B8, 0x01E8, 1, 0x0000, 0,  0)
+MX6_PAD_DECL(ENET_MDC__ESAI_TX5_RX0,	0x05B8, 0x01E8, 2, 0x0858, 0, 0)
+MX6_PAD_DECL(ENET_MDC__ENET_1588_EVENT1_IN,	0x05B8, 0x01E8, 4, 0x0000, 0, 0)
+MX6_PAD_DECL(ENET_MDC__GPIO1_IO31,	0x05B8, 0x01E8, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(ENET_MDIO__ENET_MDIO,	0x05BC, 0x01EC, 1, 0x0810, 0, 0)
+MX6_PAD_DECL(ENET_MDIO__ESAI_RX_CLK,	0x05BC, 0x01EC, 2, 0x083C, 0, 0)
+MX6_PAD_DECL(ENET_MDIO__ENET_1588_EVENT1_OUT,	0x05BC, 0x01EC, 4, 0x0000, 0, 0)
+MX6_PAD_DECL(ENET_MDIO__GPIO1_IO22,	0x05BC, 0x01EC, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(ENET_MDIO__SPDIF_LOCK,	0x05BC, 0x01EC, 6, 0x0000, 0, 0)
+MX6_PAD_DECL(ENET_REF_CLK__ENET_TX_CLK,	0x05C0, 0x01F0, 1 | IOMUX_CONFIG_SION, 0x0000, 0, 0)
+MX6_PAD_DECL(ENET_REF_CLK__ESAI_RX_FS,	0x05C0, 0x01F0, 2, 0x082C, 0, 0)
+MX6_PAD_DECL(ENET_REF_CLK__GPIO1_IO23,	0x05C0, 0x01F0, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(ENET_REF_CLK__SPDIF_SR_CLK,	0x05C0, 0x01F0, 6, 0x0000, 0, 0)
+MX6_PAD_DECL(ENET_RX_ER__USB_OTG_ID,	0x05C4, 0x01F4, 0, 0x0790, 0, 0)
+MX6_PAD_DECL(ENET_RX_ER__ENET_RX_ER,	0x05C4, 0x01F4, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(ENET_RX_ER__ESAI_RX_HF_CLK,	0x05C4, 0x01F4, 2, 0x0834, 0, 0)
+MX6_PAD_DECL(ENET_RX_ER__SPDIF_IN,	0x05C4, 0x01F4, 3, 0x08F0, 1, 0)
+MX6_PAD_DECL(ENET_RX_ER__ENET_1588_EVENT2_OUT,	0x05C4, 0x01F4, 4, 0x0000, 0, 0)
+MX6_PAD_DECL(ENET_RX_ER__GPIO1_IO24,	0x05C4, 0x01F4, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(ENET_RXD0__ENET_RX_DATA0,	0x05C8, 0x01F8, 1, 0x0818, 0, 0)
+MX6_PAD_DECL(ENET_RXD0__ESAI_TX_HF_CLK,	0x05C8, 0x01F8, 2, 0x0838, 0, 0)
+MX6_PAD_DECL(ENET_RXD0__SPDIF_OUT,	0x05C8, 0x01F8, 3, 0x0000, 0, 0)
+MX6_PAD_DECL(ENET_RXD0__GPIO1_IO27,	0x05C8, 0x01F8, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(ENET_RXD1__MLB_SIG,	0x05CC, 0x01FC, 0, 0x08E4, 0, 0)
+MX6_PAD_DECL(ENET_RXD1__ENET_RX_DATA1,	0x05CC, 0x01FC, 1, 0x081C, 0, 0)
+MX6_PAD_DECL(ENET_RXD1__ESAI_TX_FS,	0x05CC, 0x01FC, 2, 0x0830, 0, 0)
+MX6_PAD_DECL(ENET_RXD1__ENET_1588_EVENT3_OUT,	0x05CC, 0x01FC, 4, 0x0000, 0, 0)
+MX6_PAD_DECL(ENET_RXD1__GPIO1_IO26,	0x05CC, 0x01FC, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(ENET_TX_EN__ENET_TX_EN,	0x05D0, 0x0200, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(ENET_TX_EN__ESAI_TX3_RX2,	0x05D0, 0x0200, 2, 0x0850, 0, 0)
+MX6_PAD_DECL(ENET_TX_EN__GPIO1_IO28,	0x05D0, 0x0200, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(ENET_TX_EN__I2C4_SCL,	0x05D0, 0x0200, 9 | IOMUX_CONFIG_SION, 0x0880, 0, 0)
+MX6_PAD_DECL(ENET_TXD0__ENET_TX_DATA0,	0x05D4, 0x0204, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(ENET_TXD0__ESAI_TX4_RX1,	0x05D4, 0x0204, 2, 0x0854, 0, 0)
+MX6_PAD_DECL(ENET_TXD0__GPIO1_IO30,	0x05D4, 0x0204, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(ENET_TXD1__MLB_CLK,	0x05D8, 0x0208, 0, 0x08DC, 0, 0)
+MX6_PAD_DECL(ENET_TXD1__ENET_TX_DATA1,	0x05D8, 0x0208, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(ENET_TXD1__ESAI_TX2_RX3,	0x05D8, 0x0208, 2, 0x084C, 0, 0)
+MX6_PAD_DECL(ENET_TXD1__ENET_1588_EVENT0_IN,	0x05D8, 0x0208, 4, 0x0000, 0, 0)
+MX6_PAD_DECL(ENET_TXD1__GPIO1_IO29,	0x05D8, 0x0208, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(ENET_TXD1__I2C4_SDA,	0x05D8, 0x0208, 9 | IOMUX_CONFIG_SION, 0x0884, 0, 0)
+MX6_PAD_DECL(GPIO_0__CCM_CLKO1,	0x05DC, 0x020C, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(GPIO_0__KEY_COL5,	0x05DC, 0x020C, 2, 0x08C0, 1, 0)
+MX6_PAD_DECL(GPIO_0__ASRC_EXT_CLK,	0x05DC, 0x020C, 3, 0x0794, 0, 0)
+MX6_PAD_DECL(GPIO_0__EPIT1_OUT,	0x05DC, 0x020C, 4, 0x0000, 0, 0)
+MX6_PAD_DECL(GPIO_0__GPIO1_IO00,	0x05DC, 0x020C, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(GPIO_0__USB_H1_PWR,	0x05DC, 0x020C, 6, 0x0000, 0, 0)
+MX6_PAD_DECL(GPIO_0__SNVS_VIO_5,	0x05DC, 0x020C, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(GPIO_1__ESAI_RX_CLK,	0x05E0, 0x0210, 0, 0x083C, 1, 0)
+MX6_PAD_DECL(GPIO_1__WDOG2_B,	0x05E0, 0x0210, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(GPIO_1__KEY_ROW5,	0x05E0, 0x0210, 2, 0x08CC, 1, 0)
+MX6_PAD_DECL(GPIO_1__USB_OTG_ID,	0x05E0, 0x0210, 3, 0x0790, 1, 0)
+MX6_PAD_DECL(GPIO_1__PWM2_OUT,	0x05E0, 0x0210, 4, 0x0000, 0, 0)
+MX6_PAD_DECL(GPIO_1__GPIO1_IO01,	0x05E0, 0x0210, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(GPIO_1__SD1_CD_B,	0x05E0, 0x0210, 6, 0x0000, 0, 0)
+MX6_PAD_DECL(GPIO_16__ESAI_TX3_RX2,	0x05E4, 0x0214, 0, 0x0850, 1, 0)
+MX6_PAD_DECL(GPIO_16__ENET_1588_EVENT2_IN,	0x05E4, 0x0214, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(GPIO_16__ENET_REF_CLK,	0x05E4, 0x0214, 2 | IOMUX_CONFIG_SION, 0x080C, 0, 0)
+MX6_PAD_DECL(GPIO_16__SD1_LCTL,	0x05E4, 0x0214, 3, 0x0000, 0, 0)
+MX6_PAD_DECL(GPIO_16__SPDIF_IN,	0x05E4, 0x0214, 4, 0x08F0, 2, 0)
+MX6_PAD_DECL(GPIO_16__GPIO7_IO11,	0x05E4, 0x0214, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(GPIO_16__I2C3_SDA,	0x05E4, 0x0214, 6 | IOMUX_CONFIG_SION, 0x087C, 1, 0)
+MX6_PAD_DECL(GPIO_16__JTAG_DE_B,	0x05E4, 0x0214, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(GPIO_17__ESAI_TX0,	0x05E8, 0x0218, 0, 0x0844, 0, 0)
+MX6_PAD_DECL(GPIO_17__ENET_1588_EVENT3_IN,	0x05E8, 0x0218, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(GPIO_17__CCM_PMIC_READY,	0x05E8, 0x0218, 2, 0x07D4, 1, 0)
+MX6_PAD_DECL(GPIO_17__SDMA_EXT_EVENT0,	0x05E8, 0x0218, 3, 0x08E8, 1, 0)
+MX6_PAD_DECL(GPIO_17__SPDIF_OUT,	0x05E8, 0x0218, 4, 0x0000, 0, 0)
+MX6_PAD_DECL(GPIO_17__GPIO7_IO12,	0x05E8, 0x0218, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(GPIO_18__ESAI_TX1,	0x05EC, 0x021C, 0, 0x0848, 0, 0)
+MX6_PAD_DECL(GPIO_18__ENET_RX_CLK,	0x05EC, 0x021C, 1, 0x0814, 0, 0)
+MX6_PAD_DECL(GPIO_18__SD3_VSELECT,	0x05EC, 0x021C, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(GPIO_18__SDMA_EXT_EVENT1,	0x05EC, 0x021C, 3, 0x08EC, 1, 0)
+MX6_PAD_DECL(GPIO_18__ASRC_EXT_CLK,	0x05EC, 0x021C, 4, 0x0794, 1, 0)
+MX6_PAD_DECL(GPIO_18__GPIO7_IO13,	0x05EC, 0x021C, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(GPIO_18__SNVS_VIO_5_CTL,	0x05EC, 0x021C, 6, 0x0000, 0, 0)
+MX6_PAD_DECL(GPIO_19__KEY_COL5,	0x05F0, 0x0220, 0, 0x08C0, 2, 0)
+MX6_PAD_DECL(GPIO_19__ENET_1588_EVENT0_OUT,	0x05F0, 0x0220, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(GPIO_19__SPDIF_OUT,	0x05F0, 0x0220, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(GPIO_19__CCM_CLKO1,	0x05F0, 0x0220, 3, 0x0000, 0, 0)
+MX6_PAD_DECL(GPIO_19__ECSPI1_RDY,	0x05F0, 0x0220, 4, 0x0000, 0, 0)
+MX6_PAD_DECL(GPIO_19__GPIO4_IO05,	0x05F0, 0x0220, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(GPIO_19__ENET_TX_ER,	0x05F0, 0x0220, 6, 0x0000, 0, 0)
+MX6_PAD_DECL(GPIO_2__ESAI_TX_FS,	0x05F4, 0x0224, 0, 0x0830, 1, 0)
+MX6_PAD_DECL(GPIO_2__KEY_ROW6,	0x05F4, 0x0224, 2, 0x08D0, 1, 0)
+MX6_PAD_DECL(GPIO_2__GPIO1_IO02,	0x05F4, 0x0224, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(GPIO_2__SD2_WP,	0x05F4, 0x0224, 6, 0x0000, 0, 0)
+MX6_PAD_DECL(GPIO_2__MLB_DATA,	0x05F4, 0x0224, 7, 0x08E0, 1, 0)
+MX6_PAD_DECL(GPIO_3__ESAI_RX_HF_CLK,	0x05F8, 0x0228, 0, 0x0834, 1, 0)
+MX6_PAD_DECL(GPIO_3__I2C3_SCL,	0x05F8, 0x0228, 2 | IOMUX_CONFIG_SION, 0x0878, 1, 0)
+MX6_PAD_DECL(GPIO_3__XTALOSC_REF_CLK_24M,	0x05F8, 0x0228, 3, 0x0000, 0, 0)
+MX6_PAD_DECL(GPIO_3__CCM_CLKO2,	0x05F8, 0x0228, 4, 0x0000, 0, 0)
+MX6_PAD_DECL(GPIO_3__GPIO1_IO03,	0x05F8, 0x0228, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(GPIO_3__USB_H1_OC,	0x05F8, 0x0228, 6, 0x0924, 1, 0)
+MX6_PAD_DECL(GPIO_3__MLB_CLK,	0x05F8, 0x0228, 7, 0x08DC, 1, 0)
+MX6_PAD_DECL(GPIO_4__ESAI_TX_HF_CLK,	0x05FC, 0x022C, 0, 0x0838, 1, 0)
+MX6_PAD_DECL(GPIO_4__KEY_COL7,	0x05FC, 0x022C, 2, 0x08C8, 1, 0)
+MX6_PAD_DECL(GPIO_4__GPIO1_IO04,	0x05FC, 0x022C, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(GPIO_4__SD2_CD_B,	0x05FC, 0x022C, 6, 0x0000, 0, 0)
+MX6_PAD_DECL(GPIO_5__ESAI_TX2_RX3,	0x0600, 0x0230, 0, 0x084C, 1, 0)
+MX6_PAD_DECL(GPIO_5__KEY_ROW7,	0x0600, 0x0230, 2, 0x08D4, 1, 0)
+MX6_PAD_DECL(GPIO_5__CCM_CLKO1,	0x0600, 0x0230, 3, 0x0000, 0, 0)
+MX6_PAD_DECL(GPIO_5__GPIO1_IO05,	0x0600, 0x0230, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(GPIO_5__I2C3_SCL,	0x0600, 0x0230, 6 | IOMUX_CONFIG_SION, 0x0878, 2, 0)
+MX6_PAD_DECL(GPIO_5__ARM_EVENTI,	0x0600, 0x0230, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(GPIO_6__ESAI_TX_CLK,	0x0604, 0x0234, 0, 0x0840, 1, 0)
+MX6_PAD_DECL(GPIO_6__I2C3_SDA,	0x0604, 0x0234, 2 | IOMUX_CONFIG_SION, 0x087C, 2, 0)
+MX6_PAD_DECL(GPIO_6__GPIO1_IO06,	0x0604, 0x0234, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(GPIO_6__SD2_LCTL,	0x0604, 0x0234, 6, 0x0000, 0, 0)
+MX6_PAD_DECL(GPIO_6__MLB_SIG,	0x0604, 0x0234, 7, 0x08E4, 1, 0)
+MX6_PAD_DECL(GPIO_7__ESAI_TX4_RX1,	0x0608, 0x0238, 0, 0x0854, 1, 0)
+MX6_PAD_DECL(GPIO_7__EPIT1_OUT,	0x0608, 0x0238, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(GPIO_7__FLEXCAN1_TX,	0x0608, 0x0238, 3, 0x0000, 0, 0)
+MX6_PAD_DECL(GPIO_7__UART2_TX_DATA,	0x0608, 0x0238, 4, 0x0000, 0, 0)
+MX6_PAD_DECL(GPIO_7__UART2_RX_DATA,	0x0608, 0x0238, 4, 0x0904, 2, 0)
+MX6_PAD_DECL(GPIO_7__GPIO1_IO07,	0x0608, 0x0238, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(GPIO_7__SPDIF_LOCK,	0x0608, 0x0238, 6, 0x0000, 0, 0)
+MX6_PAD_DECL(GPIO_7__USB_OTG_HOST_MODE,	0x0608, 0x0238, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(GPIO_7__I2C4_SCL,	0x0608, 0x0238, 8 | IOMUX_CONFIG_SION, 0x0880, 1, 0)
+MX6_PAD_DECL(GPIO_8__ESAI_TX5_RX0,	0x060C, 0x023C, 0, 0x0858, 1, 0)
+MX6_PAD_DECL(GPIO_8__XTALOSC_REF_CLK_32K,	0x060C, 0x023C, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(GPIO_8__EPIT2_OUT,	0x060C, 0x023C, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(GPIO_8__FLEXCAN1_RX,	0x060C, 0x023C, 3, 0x07C8, 0, 0)
+MX6_PAD_DECL(GPIO_8__UART2_TX_DATA,	0x060C, 0x023C, 4, 0x0000, 0, 0)
+MX6_PAD_DECL(GPIO_8__UART2_RX_DATA,	0x060C, 0x023C, 4, 0x0904, 3, 0)
+MX6_PAD_DECL(GPIO_8__GPIO1_IO08,	0x060C, 0x023C, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(GPIO_8__SPDIF_SR_CLK,	0x060C, 0x023C, 6, 0x0000, 0, 0)
+MX6_PAD_DECL(GPIO_8__USB_OTG_PWR_CTL_WAKE,	0x060C, 0x023C, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(GPIO_8__I2C4_SDA,	0x060C, 0x023C, 8 | IOMUX_CONFIG_SION, 0x0884, 1, 0)
+MX6_PAD_DECL(GPIO_9__ESAI_RX_FS,	0x0610, 0x0240, 0, 0x082C, 1, 0)
+MX6_PAD_DECL(GPIO_9__WDOG1_B,	0x0610, 0x0240, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(GPIO_9__KEY_COL6,	0x0610, 0x0240, 2, 0x08C4, 1, 0)
+MX6_PAD_DECL(GPIO_9__CCM_REF_EN_B,	0x0610, 0x0240, 3, 0x0000, 0, 0)
+MX6_PAD_DECL(GPIO_9__PWM1_OUT,	0x0610, 0x0240, 4, 0x0000, 0, 0)
+MX6_PAD_DECL(GPIO_9__GPIO1_IO09,	0x0610, 0x0240, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(GPIO_9__SD1_WP,	0x0610, 0x0240, 6, 0x092C, 1, 0)
+MX6_PAD_DECL(KEY_COL0__ECSPI1_SCLK,	0x062C, 0x0244, 0, 0x07D8, 3, 0)
+MX6_PAD_DECL(KEY_COL0__ENET_RX_DATA3,	0x062C, 0x0244, 1, 0x0824, 0, 0)
+MX6_PAD_DECL(KEY_COL0__AUD5_TXC,	0x062C, 0x0244, 2, 0x07C0, 1, 0)
+MX6_PAD_DECL(KEY_COL0__KEY_COL0,	0x062C, 0x0244, 3, 0x0000, 0, 0)
+MX6_PAD_DECL(KEY_COL0__UART4_TX_DATA,	0x062C, 0x0244, 4, 0x0000, 0, 0)
+MX6_PAD_DECL(KEY_COL0__UART4_RX_DATA,	0x062C, 0x0244, 4, 0x0914, 2, 0)
+MX6_PAD_DECL(KEY_COL0__GPIO4_IO06,	0x062C, 0x0244, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(KEY_COL0__DCIC1_OUT,	0x062C, 0x0244, 6, 0x0000, 0, 0)
+MX6_PAD_DECL(KEY_COL1__ECSPI1_MISO,	0x0630, 0x0248, 0, 0x07DC, 3, 0)
+MX6_PAD_DECL(KEY_COL1__ENET_MDIO,	0x0630, 0x0248, 1, 0x0810, 1, 0)
+MX6_PAD_DECL(KEY_COL1__AUD5_TXFS,	0x0630, 0x0248, 2, 0x07C4, 1, 0)
+MX6_PAD_DECL(KEY_COL1__KEY_COL1,	0x0630, 0x0248, 3, 0x0000, 0, 0)
+MX6_PAD_DECL(KEY_COL1__UART5_TX_DATA,	0x0630, 0x0248, 4, 0x0000, 0, 0)
+MX6_PAD_DECL(KEY_COL1__UART5_RX_DATA,	0x0630, 0x0248, 4, 0x091C, 2, 0)
+MX6_PAD_DECL(KEY_COL1__GPIO4_IO08,	0x0630, 0x0248, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(KEY_COL1__SD1_VSELECT,	0x0630, 0x0248, 6, 0x0000, 0, 0)
+MX6_PAD_DECL(KEY_COL2__ECSPI1_SS1,	0x0634, 0x024C, 0, 0x07E8, 2, 0)
+MX6_PAD_DECL(KEY_COL2__ENET_RX_DATA2,	0x0634, 0x024C, 1, 0x0820, 0, 0)
+MX6_PAD_DECL(KEY_COL2__FLEXCAN1_TX,	0x0634, 0x024C, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(KEY_COL2__KEY_COL2,	0x0634, 0x024C, 3, 0x0000, 0, 0)
+MX6_PAD_DECL(KEY_COL2__ENET_MDC,	0x0634, 0x024C, 4, 0x0000, 0, 0)
+MX6_PAD_DECL(KEY_COL2__GPIO4_IO10,	0x0634, 0x024C, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(KEY_COL2__USB_H1_PWR_CTL_WAKE,	0x0634, 0x024C, 6, 0x0000, 0, 0)
+MX6_PAD_DECL(KEY_COL3__ECSPI1_SS3,	0x0638, 0x0250, 0, 0x07F0, 1, 0)
+MX6_PAD_DECL(KEY_COL3__ENET_CRS,	0x0638, 0x0250, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(KEY_COL3__HDMI_TX_DDC_SCL,	0x0638, 0x0250, 2, 0x0860, 1, 0)
+MX6_PAD_DECL(KEY_COL3__KEY_COL3,	0x0638, 0x0250, 3, 0x0000, 0, 0)
+MX6_PAD_DECL(KEY_COL3__I2C2_SCL,	0x0638, 0x0250, 4 | IOMUX_CONFIG_SION, 0x0870, 1, 0)
+MX6_PAD_DECL(KEY_COL3__GPIO4_IO12,	0x0638, 0x0250, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(KEY_COL3__SPDIF_IN,	0x0638, 0x0250, 6, 0x08F0, 3, 0)
+MX6_PAD_DECL(KEY_COL4__FLEXCAN2_TX,	0x063C, 0x0254, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(KEY_COL4__IPU1_SISG4,	0x063C, 0x0254, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(KEY_COL4__USB_OTG_OC,	0x063C, 0x0254, 2, 0x0920, 1, 0)
+MX6_PAD_DECL(KEY_COL4__KEY_COL4,	0x063C, 0x0254, 3, 0x0000, 0, 0)
+MX6_PAD_DECL(KEY_COL4__UART5_CTS_B,	0x063C, 0x0254, 4, 0x0000, 0, 0)
+MX6_PAD_DECL(KEY_COL4__UART5_RTS_B,	0x063C, 0x0254, 4, 0x0918, 2, 0)
+MX6_PAD_DECL(KEY_COL4__GPIO4_IO14,	0x063C, 0x0254, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(KEY_ROW0__ECSPI1_MOSI,	0x0640, 0x0258, 0, 0x07E0, 3, 0)
+MX6_PAD_DECL(KEY_ROW0__ENET_TX_DATA3,	0x0640, 0x0258, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(KEY_ROW0__AUD5_TXD,	0x0640, 0x0258, 2, 0x07B4, 1, 0)
+MX6_PAD_DECL(KEY_ROW0__KEY_ROW0,	0x0640, 0x0258, 3, 0x0000, 0, 0)
+MX6_PAD_DECL(KEY_ROW0__UART4_TX_DATA,	0x0640, 0x0258, 4, 0x0000, 0, 0)
+MX6_PAD_DECL(KEY_ROW0__UART4_RX_DATA,	0x0640, 0x0258, 4, 0x0914, 3, 0)
+MX6_PAD_DECL(KEY_ROW0__GPIO4_IO07,	0x0640, 0x0258, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(KEY_ROW0__DCIC2_OUT,	0x0640, 0x0258, 6, 0x0000, 0, 0)
+MX6_PAD_DECL(KEY_ROW1__ECSPI1_SS0,	0x0644, 0x025C, 0, 0x07E4, 3, 0)
+MX6_PAD_DECL(KEY_ROW1__ENET_COL,	0x0644, 0x025C, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(KEY_ROW1__AUD5_RXD,	0x0644, 0x025C, 2, 0x07B0, 1, 0)
+MX6_PAD_DECL(KEY_ROW1__KEY_ROW1,	0x0644, 0x025C, 3, 0x0000, 0, 0)
+MX6_PAD_DECL(KEY_ROW1__UART5_TX_DATA,	0x0644, 0x025C, 4, 0x0000, 0, 0)
+MX6_PAD_DECL(KEY_ROW1__UART5_RX_DATA,	0x0644, 0x025C, 4, 0x091C, 3, 0)
+MX6_PAD_DECL(KEY_ROW1__GPIO4_IO09,	0x0644, 0x025C, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(KEY_ROW1__SD2_VSELECT,	0x0644, 0x025C, 6, 0x0000, 0, 0)
+MX6_PAD_DECL(KEY_ROW2__ECSPI1_SS2,	0x0648, 0x0260, 0, 0x07EC, 1, 0)
+MX6_PAD_DECL(KEY_ROW2__ENET_TX_DATA2,	0x0648, 0x0260, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(KEY_ROW2__FLEXCAN1_RX,	0x0648, 0x0260, 2, 0x07C8, 1, 0)
+MX6_PAD_DECL(KEY_ROW2__KEY_ROW2,	0x0648, 0x0260, 3, 0x0000, 0, 0)
+MX6_PAD_DECL(KEY_ROW2__SD2_VSELECT,	0x0648, 0x0260, 4, 0x0000, 0, 0)
+MX6_PAD_DECL(KEY_ROW2__GPIO4_IO11,	0x0648, 0x0260, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(KEY_ROW2__HDMI_TX_CEC_LINE,	0x0648, 0x0260, 6, 0x085C, 1, 0)
+MX6_PAD_DECL(KEY_ROW3__ASRC_EXT_CLK,	0x064C, 0x0264, 1, 0x0794, 2, 0)
+MX6_PAD_DECL(KEY_ROW3__HDMI_TX_DDC_SDA,	0x064C, 0x0264, 2, 0x0864, 1, 0)
+MX6_PAD_DECL(KEY_ROW3__KEY_ROW3,	0x064C, 0x0264, 3, 0x0000, 0, 0)
+MX6_PAD_DECL(KEY_ROW3__I2C2_SDA,	0x064C, 0x0264, 4 | IOMUX_CONFIG_SION, 0x0874, 1, 0)
+MX6_PAD_DECL(KEY_ROW3__GPIO4_IO13,	0x064C, 0x0264, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(KEY_ROW3__SD1_VSELECT,	0x064C, 0x0264, 6, 0x0000, 0, 0)
+MX6_PAD_DECL(KEY_ROW4__FLEXCAN2_RX,	0x0650, 0x0268, 0, 0x07CC, 0, 0)
+MX6_PAD_DECL(KEY_ROW4__IPU1_SISG5,	0x0650, 0x0268, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(KEY_ROW4__USB_OTG_PWR,	0x0650, 0x0268, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(KEY_ROW4__KEY_ROW4,	0x0650, 0x0268, 3, 0x0000, 0, 0)
+MX6_PAD_DECL(KEY_ROW4__UART5_CTS_B,	0x0650, 0x0268, 4, 0x0000, 0, 0)
+MX6_PAD_DECL(KEY_ROW4__UART5_RTS_B,	0x0650, 0x0268, 4, 0x0918, 3, 0)
+MX6_PAD_DECL(KEY_ROW4__GPIO4_IO15,	0x0650, 0x0268, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(NANDF_ALE__NAND_ALE,	0x0654, 0x026C, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(NANDF_ALE__SD4_RESET,	0x0654, 0x026C, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(NANDF_ALE__GPIO6_IO08,	0x0654, 0x026C, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(NANDF_CLE__NAND_CLE,	0x0658, 0x0270, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(NANDF_CLE__GPIO6_IO07,	0x0658, 0x0270, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(NANDF_CS0__NAND_CE0_B,	0x065C, 0x0274, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(NANDF_CS0__GPIO6_IO11,	0x065C, 0x0274, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(NANDF_CS1__NAND_CE1_B,	0x0660, 0x0278, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(NANDF_CS1__SD4_VSELECT,	0x0660, 0x0278, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(NANDF_CS1__SD3_VSELECT,	0x0660, 0x0278, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(NANDF_CS1__GPIO6_IO14,	0x0660, 0x0278, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(NANDF_CS2__NAND_CE2_B,	0x0664, 0x027C, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(NANDF_CS2__IPU1_SISG0,	0x0664, 0x027C, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(NANDF_CS2__ESAI_TX0,	0x0664, 0x027C, 2, 0x0844, 1, 0)
+MX6_PAD_DECL(NANDF_CS2__EIM_CRE,	0x0664, 0x027C, 3, 0x0000, 0, 0)
+MX6_PAD_DECL(NANDF_CS2__CCM_CLKO2,	0x0664, 0x027C, 4, 0x0000, 0, 0)
+MX6_PAD_DECL(NANDF_CS2__GPIO6_IO15,	0x0664, 0x027C, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(NANDF_CS3__NAND_CE3_B,	0x0668, 0x0280, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(NANDF_CS3__IPU1_SISG1,	0x0668, 0x0280, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(NANDF_CS3__ESAI_TX1,	0x0668, 0x0280, 2, 0x0848, 1, 0)
+MX6_PAD_DECL(NANDF_CS3__EIM_ADDR26,	0x0668, 0x0280, 3, 0x0000, 0, 0)
+MX6_PAD_DECL(NANDF_CS3__GPIO6_IO16,	0x0668, 0x0280, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(NANDF_CS3__I2C4_SDA,	0x0668, 0x0280, 9 | IOMUX_CONFIG_SION, 0x0884, 2, 0)
+MX6_PAD_DECL(NANDF_D0__NAND_DATA00,	0x066C, 0x0284, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(NANDF_D0__SD1_DATA4,	0x066C, 0x0284, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(NANDF_D0__GPIO2_IO00,	0x066C, 0x0284, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(NANDF_D1__NAND_DATA01,	0x0670, 0x0288, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(NANDF_D1__SD1_DATA5,	0x0670, 0x0288, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(NANDF_D1__GPIO2_IO01,	0x0670, 0x0288, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(NANDF_D2__NAND_DATA02,	0x0674, 0x028C, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(NANDF_D2__SD1_DATA6,	0x0674, 0x028C, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(NANDF_D2__GPIO2_IO02,	0x0674, 0x028C, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(NANDF_D3__NAND_DATA03,	0x0678, 0x0290, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(NANDF_D3__SD1_DATA7,	0x0678, 0x0290, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(NANDF_D3__GPIO2_IO03,	0x0678, 0x0290, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(NANDF_D4__NAND_DATA04,	0x067C, 0x0294, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(NANDF_D4__SD2_DATA4,	0x067C, 0x0294, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(NANDF_D4__GPIO2_IO04,	0x067C, 0x0294, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(NANDF_D5__NAND_DATA05,	0x0680, 0x0298, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(NANDF_D5__SD2_DATA5,	0x0680, 0x0298, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(NANDF_D5__GPIO2_IO05,	0x0680, 0x0298, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(NANDF_D6__NAND_DATA06,	0x0684, 0x029C, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(NANDF_D6__SD2_DATA6,	0x0684, 0x029C, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(NANDF_D6__GPIO2_IO06,	0x0684, 0x029C, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(NANDF_D7__NAND_DATA07,	0x0688, 0x02A0, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(NANDF_D7__SD2_DATA7,	0x0688, 0x02A0, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(NANDF_D7__GPIO2_IO07,	0x0688, 0x02A0, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(NANDF_RB0__NAND_READY_B,	0x068C, 0x02A4, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(NANDF_RB0__GPIO6_IO10,	0x068C, 0x02A4, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(NANDF_WP_B__NAND_WP_B,	0x0690, 0x02A8, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(NANDF_WP_B__GPIO6_IO09,	0x0690, 0x02A8, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(NANDF_WP_B__I2C4_SCL,	0x0690, 0x02A8, 9 | IOMUX_CONFIG_SION, 0x0880, 2, 0)
+MX6_PAD_DECL(RGMII_RD0__HSI_RX_READY,	0x0694, 0x02AC, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(RGMII_RD0__RGMII_RD0,	0x0694, 0x02AC, 1, 0x0818, 1, 0)
+MX6_PAD_DECL(RGMII_RD0__GPIO6_IO25,	0x0694, 0x02AC, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(RGMII_RD1__HSI_TX_FLAG,	0x0698, 0x02B0, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(RGMII_RD1__RGMII_RD1,	0x0698, 0x02B0, 1, 0x081C, 1, 0)
+MX6_PAD_DECL(RGMII_RD1__GPIO6_IO27,	0x0698, 0x02B0, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(RGMII_RD2__HSI_TX_DATA,	0x069C, 0x02B4, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(RGMII_RD2__RGMII_RD2,	0x069C, 0x02B4, 1, 0x0820, 1, 0)
+MX6_PAD_DECL(RGMII_RD2__GPIO6_IO28,	0x069C, 0x02B4, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(RGMII_RD3__HSI_TX_WAKE,	0x06A0, 0x02B8, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(RGMII_RD3__RGMII_RD3,	0x06A0, 0x02B8, 1, 0x0824, 1, 0)
+MX6_PAD_DECL(RGMII_RD3__GPIO6_IO29,	0x06A0, 0x02B8, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(RGMII_RX_CTL__USB_H3_DATA,	0x06A4, 0x02BC, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0)
+MX6_PAD_DECL(RGMII_RX_CTL__RGMII_RX_CTL,	0x06A4, 0x02BC, 1, 0x0828, 1, 0)
+MX6_PAD_DECL(RGMII_RX_CTL__GPIO6_IO24,	0x06A4, 0x02BC, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(RGMII_RXC__USBOH3_H3_STROBE,	0x06A8, 0x02C0, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0)
+MX6_PAD_DECL(RGMII_RXC__USB_H3_STROBE,	0x06A8, 0x02C0, 0 | IOMUX_CONFIG_SION, 0x0000, 0, PAD_CTL_PUS_47K_UP)
+MX6_PAD_DECL(RGMII_RXC__RGMII_RXC,	0x06A8, 0x02C0, 1, 0x0814, 1, 0)
+MX6_PAD_DECL(RGMII_RXC__GPIO6_IO30,	0x06A8, 0x02C0, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(RGMII_TD0__HSI_TX_READY,	0x06AC, 0x02C4, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(RGMII_TD0__RGMII_TD0,	0x06AC, 0x02C4, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(RGMII_TD0__GPIO6_IO20,	0x06AC, 0x02C4, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(RGMII_TD1__HSI_RX_FLAG,	0x06B0, 0x02C8, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(RGMII_TD1__RGMII_TD1,	0x06B0, 0x02C8, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(RGMII_TD1__GPIO6_IO21,	0x06B0, 0x02C8, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(RGMII_TD2__HSI_RX_DATA,	0x06B4, 0x02CC, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(RGMII_TD2__RGMII_TD2,	0x06B4, 0x02CC, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(RGMII_TD2__GPIO6_IO22,	0x06B4, 0x02CC, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(RGMII_TD3__HSI_RX_WAKE,	0x06B8, 0x02D0, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(RGMII_TD3__RGMII_TD3,	0x06B8, 0x02D0, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(RGMII_TD3__GPIO6_IO23,	0x06B8, 0x02D0, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(RGMII_TX_CTL__USBOH3_H2_STROBE,	0x06BC, 0x02D4, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0)
+MX6_PAD_DECL(RGMII_TX_CTL__USB_H2_STROBE,	0x06BC, 0x02D4, 0 | IOMUX_CONFIG_SION, 0x0000, 0, PAD_CTL_PUS_47K_UP)
+MX6_PAD_DECL(RGMII_TX_CTL__RGMII_TX_CTL,	0x06BC, 0x02D4, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(RGMII_TX_CTL__GPIO6_IO26,	0x06BC, 0x02D4, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(RGMII_TX_CTL__ENET_REF_CLK,	0x06BC, 0x02D4, 7 | IOMUX_CONFIG_SION, 0x080C, 1, 0)
+MX6_PAD_DECL(RGMII_TXC__USB_H2_DATA,	0x06C0, 0x02D8, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0)
+MX6_PAD_DECL(RGMII_TXC__RGMII_TXC,	0x06C0, 0x02D8, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(RGMII_TXC__SPDIF_EXT_CLK,	0x06C0, 0x02D8, 2, 0x08F4, 1, 0)
+MX6_PAD_DECL(RGMII_TXC__GPIO6_IO19,	0x06C0, 0x02D8, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(RGMII_TXC__XTALOSC_REF_CLK_24M,	0x06C0, 0x02D8, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(SD1_CLK__SD1_CLK,	0x06C4, 0x02DC, 0, 0x0928, 1, 0)
+MX6_PAD_DECL(SD1_CLK__GPT_CLKIN,	0x06C4, 0x02DC, 3, 0x0000, 0, 0)
+MX6_PAD_DECL(SD1_CLK__GPIO1_IO20,	0x06C4, 0x02DC, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(SD1_CMD__SD1_CMD,	0x06C8, 0x02E0, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0)
+MX6_PAD_DECL(SD1_CMD__PWM4_OUT,	0x06C8, 0x02E0, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(SD1_CMD__GPT_COMPARE1,	0x06C8, 0x02E0, 3, 0x0000, 0, 0)
+MX6_PAD_DECL(SD1_CMD__GPIO1_IO18,	0x06C8, 0x02E0, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(SD1_DAT0__SD1_DATA0,	0x06CC, 0x02E4, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(SD1_DAT0__GPT_CAPTURE1,	0x06CC, 0x02E4, 3, 0x0000, 0, 0)
+MX6_PAD_DECL(SD1_DAT0__GPIO1_IO16,	0x06CC, 0x02E4, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(SD1_DAT1__SD1_DATA1,	0x06D0, 0x02E8, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(SD1_DAT1__PWM3_OUT,	0x06D0, 0x02E8, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(SD1_DAT1__GPT_CAPTURE2,	0x06D0, 0x02E8, 3, 0x0000, 0, 0)
+MX6_PAD_DECL(SD1_DAT1__GPIO1_IO17,	0x06D0, 0x02E8, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(SD1_DAT2__SD1_DATA2,	0x06D4, 0x02EC, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(SD1_DAT2__GPT_COMPARE2,	0x06D4, 0x02EC, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(SD1_DAT2__PWM2_OUT,	0x06D4, 0x02EC, 3, 0x0000, 0, 0)
+MX6_PAD_DECL(SD1_DAT2__WDOG1_B,	0x06D4, 0x02EC, 4, 0x0000, 0, 0)
+MX6_PAD_DECL(SD1_DAT2__GPIO1_IO19,	0x06D4, 0x02EC, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(SD1_DAT2__WDOG1_RESET_B_DEB,	0x06D4, 0x02EC, 6, 0x0000, 0, 0)
+MX6_PAD_DECL(SD1_DAT3__SD1_DATA3,	0x06D8, 0x02F0, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(SD1_DAT3__GPT_COMPARE3,	0x06D8, 0x02F0, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(SD1_DAT3__PWM1_OUT,	0x06D8, 0x02F0, 3, 0x0000, 0, 0)
+MX6_PAD_DECL(SD1_DAT3__WDOG2_B,	0x06D8, 0x02F0, 4, 0x0000, 0, 0)
+MX6_PAD_DECL(SD1_DAT3__GPIO1_IO21,	0x06D8, 0x02F0, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(SD1_DAT3__WDOG2_RESET_B_DEB,	0x06D8, 0x02F0, 6, 0x0000, 0, 0)
+MX6_PAD_DECL(SD2_CLK__SD2_CLK,	0x06DC, 0x02F4, 0, 0x0930, 1, 0)
+MX6_PAD_DECL(SD2_CLK__KEY_COL5,	0x06DC, 0x02F4, 2, 0x08C0, 3, 0)
+MX6_PAD_DECL(SD2_CLK__AUD4_RXFS,	0x06DC, 0x02F4, 3, 0x07A4, 1, 0)
+MX6_PAD_DECL(SD2_CLK__GPIO1_IO10,	0x06DC, 0x02F4, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(SD2_CMD__SD2_CMD,	0x06E0, 0x02F8, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0)
+MX6_PAD_DECL(SD2_CMD__KEY_ROW5,	0x06E0, 0x02F8, 2, 0x08CC, 2, 0)
+MX6_PAD_DECL(SD2_CMD__AUD4_RXC,	0x06E0, 0x02F8, 3, 0x07A0, 1, 0)
+MX6_PAD_DECL(SD2_CMD__GPIO1_IO11,	0x06E0, 0x02F8, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(SD2_DAT0__SD2_DATA0,	0x06E4, 0x02FC, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(SD2_DAT0__AUD4_RXD,	0x06E4, 0x02FC, 3, 0x0798, 1, 0)
+MX6_PAD_DECL(SD2_DAT0__KEY_ROW7,	0x06E4, 0x02FC, 4, 0x08D4, 2, 0)
+MX6_PAD_DECL(SD2_DAT0__GPIO1_IO15,	0x06E4, 0x02FC, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(SD2_DAT0__DCIC2_OUT,	0x06E4, 0x02FC, 6, 0x0000, 0, 0)
+MX6_PAD_DECL(SD2_DAT1__SD2_DATA1,	0x06E8, 0x0300, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(SD2_DAT1__EIM_CS2_B,	0x06E8, 0x0300, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(SD2_DAT1__AUD4_TXFS,	0x06E8, 0x0300, 3, 0x07AC, 1, 0)
+MX6_PAD_DECL(SD2_DAT1__KEY_COL7,	0x06E8, 0x0300, 4, 0x08C8, 2, 0)
+MX6_PAD_DECL(SD2_DAT1__GPIO1_IO14,	0x06E8, 0x0300, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(SD2_DAT2__SD2_DATA2,	0x06EC, 0x0304, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(SD2_DAT2__EIM_CS3_B,	0x06EC, 0x0304, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(SD2_DAT2__AUD4_TXD,	0x06EC, 0x0304, 3, 0x079C, 1, 0)
+MX6_PAD_DECL(SD2_DAT2__KEY_ROW6,	0x06EC, 0x0304, 4, 0x08D0, 2, 0)
+MX6_PAD_DECL(SD2_DAT2__GPIO1_IO13,	0x06EC, 0x0304, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(SD2_DAT3__SD2_DATA3,	0x06F0, 0x0308, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(SD2_DAT3__KEY_COL6,	0x06F0, 0x0308, 2, 0x08C4, 2, 0)
+MX6_PAD_DECL(SD2_DAT3__AUD4_TXC,	0x06F0, 0x0308, 3, 0x07A8, 1, 0)
+MX6_PAD_DECL(SD2_DAT3__GPIO1_IO12,	0x06F0, 0x0308, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(SD3_CLK__SD3_CLK,	0x06F4, 0x030C, 0, 0x0934, 1, 0)
+MX6_PAD_DECL(SD3_CLK__UART2_CTS_B,	0x06F4, 0x030C, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(SD3_CLK__UART2_RTS_B,	0x06F4, 0x030C, 1, 0x0900, 2, 0)
+MX6_PAD_DECL(SD3_CLK__FLEXCAN1_RX,	0x06F4, 0x030C, 2, 0x07C8, 2, 0)
+MX6_PAD_DECL(SD3_CLK__GPIO7_IO03,	0x06F4, 0x030C, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(SD3_CMD__SD3_CMD,	0x06F8, 0x0310, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0)
+MX6_PAD_DECL(SD3_CMD__UART2_CTS_B,	0x06F8, 0x0310, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(SD3_CMD__UART2_RTS_B,	0x06F8, 0x0310, 1, 0x0900, 3, 0)
+MX6_PAD_DECL(SD3_CMD__FLEXCAN1_TX,	0x06F8, 0x0310, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(SD3_CMD__GPIO7_IO02,	0x06F8, 0x0310, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(SD3_DAT0__SD3_DATA0,	0x06FC, 0x0314, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(SD3_DAT0__UART1_CTS_B,	0x06FC, 0x0314, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(SD3_DAT0__UART1_RTS_B,	0x06FC, 0x0314, 1, 0x08F8, 2, 0)
+MX6_PAD_DECL(SD3_DAT0__FLEXCAN2_TX,	0x06FC, 0x0314, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(SD3_DAT0__GPIO7_IO04,	0x06FC, 0x0314, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(SD3_DAT1__SD3_DATA1,	0x0700, 0x0318, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(SD3_DAT1__UART1_CTS_B,	0x0700, 0x0318, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(SD3_DAT1__UART1_RTS_B,	0x0700, 0x0318, 1, 0x08F8, 3, 0)
+MX6_PAD_DECL(SD3_DAT1__FLEXCAN2_RX,	0x0700, 0x0318, 2, 0x07CC, 1, 0)
+MX6_PAD_DECL(SD3_DAT1__GPIO7_IO05,	0x0700, 0x0318, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(SD3_DAT2__SD3_DATA2,	0x0704, 0x031C, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(SD3_DAT2__GPIO7_IO06,	0x0704, 0x031C, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(SD3_DAT3__SD3_DATA3,	0x0708, 0x0320, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(SD3_DAT3__UART3_CTS_B,	0x0708, 0x0320, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(SD3_DAT3__UART3_RTS_B,	0x0708, 0x0320, 1, 0x0908, 4, 0)
+MX6_PAD_DECL(SD3_DAT3__GPIO7_IO07,	0x0708, 0x0320, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(SD3_DAT4__SD3_DATA4,	0x070C, 0x0324, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(SD3_DAT4__UART2_TX_DATA,	0x070C, 0x0324, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(SD3_DAT4__UART2_RX_DATA,	0x070C, 0x0324, 1, 0x0904, 4, 0)
+MX6_PAD_DECL(SD3_DAT4__GPIO7_IO01,	0x070C, 0x0324, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(SD3_DAT5__SD3_DATA5,	0x0710, 0x0328, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(SD3_DAT5__UART2_TX_DATA,	0x0710, 0x0328, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(SD3_DAT5__UART2_RX_DATA,	0x0710, 0x0328, 1, 0x0904, 5, 0)
+MX6_PAD_DECL(SD3_DAT5__GPIO7_IO00,	0x0710, 0x0328, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(SD3_DAT6__SD3_DATA6,	0x0714, 0x032C, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(SD3_DAT6__UART1_TX_DATA,	0x0714, 0x032C, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(SD3_DAT6__UART1_RX_DATA,	0x0714, 0x032C, 1, 0x08FC, 2, 0)
+MX6_PAD_DECL(SD3_DAT6__GPIO6_IO18,	0x0714, 0x032C, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(SD3_DAT7__SD3_DATA7,	0x0718, 0x0330, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(SD3_DAT7__UART1_TX_DATA,	0x0718, 0x0330, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(SD3_DAT7__UART1_RX_DATA,	0x0718, 0x0330, 1, 0x08FC, 3, 0)
+MX6_PAD_DECL(SD3_DAT7__GPIO6_IO17,	0x0718, 0x0330, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(SD3_RST__SD3_RESET,	0x071C, 0x0334, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(SD3_RST__UART3_CTS_B,	0x071C, 0x0334, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(SD3_RST__UART3_RTS_B,	0x071C, 0x0334, 1, 0x0908, 5, 0)
+MX6_PAD_DECL(SD3_RST__GPIO7_IO08,	0x071C, 0x0334, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(SD4_CLK__SD4_CLK,	0x0720, 0x0338, 0, 0x0938, 1, 0)
+MX6_PAD_DECL(SD4_CLK__NAND_WE_B,	0x0720, 0x0338, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(SD4_CLK__UART3_TX_DATA,	0x0720, 0x0338, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(SD4_CLK__UART3_RX_DATA,	0x0720, 0x0338, 2, 0x090C, 2, 0)
+MX6_PAD_DECL(SD4_CLK__GPIO7_IO10,	0x0720, 0x0338, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(SD4_CMD__SD4_CMD,	0x0724, 0x033C, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0)
+MX6_PAD_DECL(SD4_CMD__NAND_RE_B,	0x0724, 0x033C, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(SD4_CMD__UART3_TX_DATA,	0x0724, 0x033C, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(SD4_CMD__UART3_RX_DATA,	0x0724, 0x033C, 2, 0x090C, 3, 0)
+MX6_PAD_DECL(SD4_CMD__GPIO7_IO09,	0x0724, 0x033C, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(SD4_DAT0__SD4_DATA0,	0x0728, 0x0340, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(SD4_DAT0__NAND_DQS,	0x0728, 0x0340, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(SD4_DAT0__GPIO2_IO08,	0x0728, 0x0340, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(SD4_DAT1__SD4_DATA1,	0x072C, 0x0344, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(SD4_DAT1__PWM3_OUT,	0x072C, 0x0344, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(SD4_DAT1__GPIO2_IO09,	0x072C, 0x0344, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(SD4_DAT2__SD4_DATA2,	0x0730, 0x0348, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(SD4_DAT2__PWM4_OUT,	0x0730, 0x0348, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(SD4_DAT2__GPIO2_IO10,	0x0730, 0x0348, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(SD4_DAT3__SD4_DATA3,	0x0734, 0x034C, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(SD4_DAT3__GPIO2_IO11,	0x0734, 0x034C, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(SD4_DAT4__SD4_DATA4,	0x0738, 0x0350, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(SD4_DAT4__UART2_TX_DATA,	0x0738, 0x0350, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(SD4_DAT4__UART2_RX_DATA,	0x0738, 0x0350, 2, 0x0904, 6, 0)
+MX6_PAD_DECL(SD4_DAT4__GPIO2_IO12,	0x0738, 0x0350, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(SD4_DAT5__SD4_DATA5,	0x073C, 0x0354, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(SD4_DAT5__UART2_CTS_B,	0x073C, 0x0354, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(SD4_DAT5__UART2_RTS_B,	0x073C, 0x0354, 2, 0x0900, 4, 0)
+MX6_PAD_DECL(SD4_DAT5__GPIO2_IO13,	0x073C, 0x0354, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(SD4_DAT6__SD4_DATA6,	0x0740, 0x0358, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(SD4_DAT6__UART2_CTS_B,	0x0740, 0x0358, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(SD4_DAT6__UART2_RTS_B,	0x0740, 0x0358, 2, 0x0900, 5, 0)
+MX6_PAD_DECL(SD4_DAT6__GPIO2_IO14,	0x0740, 0x0358, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(SD4_DAT7__SD4_DATA7,	0x0744, 0x035C, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(SD4_DAT7__UART2_TX_DATA,	0x0744, 0x035C, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(SD4_DAT7__UART2_RX_DATA,	0x0744, 0x035C, 2, 0x0904, 7, 0)
+MX6_PAD_DECL(SD4_DAT7__GPIO2_IO15,	0x0744, 0x035C, 5, 0x0000, 0, 0)
 
-enum {
-	MX6_PAD_CSI0_DAT10__IPU1_CSI0_D_10	= IOMUX_PAD(0x0360, 0x004C, 0, 0x0000, 0, 0),
-	MX6_PAD_CSI0_DAT10__AUDMUX_AUD3_RXC	= IOMUX_PAD(0x0360, 0x004C, 1, 0x0000, 0, 0),
-	MX6_PAD_CSI0_DAT10__ECSPI2_MISO		= IOMUX_PAD(0x0360, 0x004C, 2, 0x07F8, 0, 0),
-	MX6_PAD_CSI0_DAT10__UART1_TXD		= IOMUX_PAD(0x0360, 0x004C, 3, 0x0000, 0, 0),
-	MX6_PAD_CSI0_DAT10__UART1_RXD		= IOMUX_PAD(0x0360, 0x004C, 3, 0x08FC, 0, 0),
-	MX6_PAD_CSI0_DAT10__SDMA_DEBUG_PC_4	= IOMUX_PAD(0x0360, 0x004C, 4, 0x0000, 0, 0),
-	MX6_PAD_CSI0_DAT10__GPIO_5_28		= IOMUX_PAD(0x0360, 0x004C, 5, 0x0000, 0, 0),
-	MX6_PAD_CSI0_DAT10__MMDC_MMDC_DEBUG_33	= IOMUX_PAD(0x0360, 0x004C, 6, 0x0000, 0, 0),
-	MX6_PAD_CSI0_DAT10__SIMBA_TRACE_7	= IOMUX_PAD(0x0360, 0x004C, 7, 0x0000, 0, 0),
-	MX6_PAD_CSI0_DAT11__IPU1_CSI0_D_11	= IOMUX_PAD(0x0364, 0x0050, 0, 0x0000, 0, 0),
-	MX6_PAD_CSI0_DAT11__AUDMUX_AUD3_RXFS	= IOMUX_PAD(0x0364, 0x0050, 1, 0x0000, 0, 0),
-	MX6_PAD_CSI0_DAT11__ECSPI2_SS0		= IOMUX_PAD(0x0364, 0x0050, 2, 0x0800, 0, 0),
-	MX6_PAD_CSI0_DAT11__UART1_TXD		= IOMUX_PAD(0x0364, 0x0050, 3, 0x0000, 0, 0),
-	MX6_PAD_CSI0_DAT11__UART1_RXD		= IOMUX_PAD(0x0364, 0x0050, 3, 0x08FC, 1, 0),
-	MX6_PAD_CSI0_DAT11__SDMA_DEBUG_PC_5	= IOMUX_PAD(0x0364, 0x0050, 4, 0x0000, 0, 0),
-	MX6_PAD_CSI0_DAT11__GPIO_5_29		= IOMUX_PAD(0x0364, 0x0050, 5, 0x0000, 0, 0),
-	MX6_PAD_CSI0_DAT11__MMDC_MMDC_DEBUG_34	= IOMUX_PAD(0x0364, 0x0050, 6, 0x0000, 0, 0),
-	MX6_PAD_CSI0_DAT11__SIMBA_TRACE_8	= IOMUX_PAD(0x0364, 0x0050, 7, 0x0000, 0, 0),
-	MX6_PAD_CSI0_DAT12__IPU1_CSI0_D_12	= IOMUX_PAD(0x0368, 0x0054, 0, 0x0000, 0, 0),
-	MX6_PAD_CSI0_DAT12__WEIM_WEIM_D_8	= IOMUX_PAD(0x0368, 0x0054, 1, 0x0000, 0, 0),
-	MX6_PAD_CSI0_DAT12__PCIE_CTRL_DIAG_STATUS_BUS_MUX_16	= IOMUX_PAD(0x0368, 0x0054, 2, 0x0000, 0, 0),
-	MX6_PAD_CSI0_DAT12__UART4_TXD		= IOMUX_PAD(0x0368, 0x0054, 3, 0x0000, 0, 0),
-	MX6_PAD_CSI0_DAT12__UART4_RXD		= IOMUX_PAD(0x0368, 0x0054, 3, 0x0914, 0, 0),
-	MX6_PAD_CSI0_DAT12__SDMA_DEBUG_PC_6	= IOMUX_PAD(0x0368, 0x0054, 4, 0x0000, 0, 0),
-	MX6_PAD_CSI0_DAT12__GPIO_5_30		= IOMUX_PAD(0x0368, 0x0054, 5, 0x0000, 0, 0),
-	MX6_PAD_CSI0_DAT12__MMDC_MMDC_DEBUG_35	= IOMUX_PAD(0x0368, 0x0054, 6, 0x0000, 0, 0),
-	MX6_PAD_CSI0_DAT12__SIMBA_TRACE_9	= IOMUX_PAD(0x0368, 0x0054, 7, 0x0000, 0, 0),
-	MX6_PAD_CSI0_DAT13__IPU1_CSI0_D_13	= IOMUX_PAD(0x036C, 0x0058, 0, 0x0000, 0, 0),
-	MX6_PAD_CSI0_DAT13__WEIM_WEIM_D_9	= IOMUX_PAD(0x036C, 0x0058, 1, 0x0000, 0, 0),
-	MX6_PAD_CSI0_DAT13__PCIE_CTRL_DIAG_STATUS_BUS_MUX_17	= IOMUX_PAD(0x036C, 0x0058, 2, 0x0000, 0, 0),
-	MX6_PAD_CSI0_DAT13__UART4_TXD		= IOMUX_PAD(0x036C, 0x0058, 3, 0x0000, 0, 0),
-	MX6_PAD_CSI0_DAT13__UART4_RXD		= IOMUX_PAD(0x036C, 0x0058, 3, 0x0914, 1, 0),
-	MX6_PAD_CSI0_DAT13__SDMA_DEBUG_PC_7	= IOMUX_PAD(0x036C, 0x0058, 4, 0x0000, 0, 0),
-	MX6_PAD_CSI0_DAT13__GPIO_5_31		= IOMUX_PAD(0x036C, 0x0058, 5, 0x0000, 0, 0),
-	MX6_PAD_CSI0_DAT13__MMDC_MMDC_DEBUG_36	= IOMUX_PAD(0x036C, 0x0058, 6, 0x0000, 0, 0),
-	MX6_PAD_CSI0_DAT13__SIMBA_TRACE_10	= IOMUX_PAD(0x036C, 0x0058, 7, 0x0000, 0, 0),
-	MX6_PAD_CSI0_DAT14__IPU1_CSI0_D_14	= IOMUX_PAD(0x0370, 0x005C, 0, 0x0000, 0, 0),
-	MX6_PAD_CSI0_DAT14__WEIM_WEIM_D_10	= IOMUX_PAD(0x0370, 0x005C, 1, 0x0000, 0, 0),
-	MX6_PAD_CSI0_DAT14__PCIE_CTRL_DIAG_STATUS_BUS_MUX_18	= IOMUX_PAD(0x0370, 0x005C, 2, 0x0000, 0, 0),
-	MX6_PAD_CSI0_DAT14__UART5_TXD		= IOMUX_PAD(0x0370, 0x005C, 3, 0x0000, 0, 0),
-	MX6_PAD_CSI0_DAT14__UART5_RXD		= IOMUX_PAD(0x0370, 0x005C, 3, 0x091C, 0, 0),
-	MX6_PAD_CSI0_DAT14__SDMA_DEBUG_PC_8	= IOMUX_PAD(0x0370, 0x005C, 4, 0x0000, 0, 0),
-	MX6_PAD_CSI0_DAT14__GPIO_6_0		= IOMUX_PAD(0x0370, 0x005C, 5, 0x0000, 0, 0),
-	MX6_PAD_CSI0_DAT14__MMDC_MMDC_DEBUG_37	= IOMUX_PAD(0x0370, 0x005C, 6, 0x0000, 0, 0),
-	MX6_PAD_CSI0_DAT14__SIMBA_TRACE_11	= IOMUX_PAD(0x0370, 0x005C, 7, 0x0000, 0, 0),
-	MX6_PAD_CSI0_DAT15__IPU1_CSI0_D_15	= IOMUX_PAD(0x0374, 0x0060, 0, 0x0000, 0, 0),
-	MX6_PAD_CSI0_DAT15__WEIM_WEIM_D_11	= IOMUX_PAD(0x0374, 0x0060, 1, 0x0000, 0, 0),
-	MX6_PAD_CSI0_DAT15__PCIE_CTRL_DIAG_STATUS_BUS_MUX_19	= IOMUX_PAD(0x0374, 0x0060, 2, 0x0000, 0, 0),
-	MX6_PAD_CSI0_DAT15__UART5_TXD		= IOMUX_PAD(0x0374, 0x0060, 3, 0x0000, 0, 0),
-	MX6_PAD_CSI0_DAT15__UART5_RXD		= IOMUX_PAD(0x0374, 0x0060, 3, 0x091C, 1, 0),
-	MX6_PAD_CSI0_DAT15__SDMA_DEBUG_PC_9	= IOMUX_PAD(0x0374, 0x0060, 4, 0x0000, 0, 0),
-	MX6_PAD_CSI0_DAT15__GPIO_6_1		= IOMUX_PAD(0x0374, 0x0060, 5, 0x0000, 0, 0),
-	MX6_PAD_CSI0_DAT15__MMDC_MMDC_DEBUG_38	= IOMUX_PAD(0x0374, 0x0060, 6, 0x0000, 0, 0),
-	MX6_PAD_CSI0_DAT15__SIMBA_TRACE_12	= IOMUX_PAD(0x0374, 0x0060, 7, 0x0000, 0, 0),
-	MX6_PAD_CSI0_DAT16__IPU1_CSI0_D_16	= IOMUX_PAD(0x0378, 0x0064, 0, 0x0000, 0, 0),
-	MX6_PAD_CSI0_DAT16__WEIM_WEIM_D_12	= IOMUX_PAD(0x0378, 0x0064, 1, 0x0000, 0, 0),
-	MX6_PAD_CSI0_DAT16__PCIE_CTRL_DIAG_STATUS_BUS_MUX_20	= IOMUX_PAD(0x0378, 0x0064, 2, 0x0000, 0, 0),
-	MX6_PAD_CSI0_DAT16__UART4_CTS		= IOMUX_PAD(0x0378, 0x0064, 3, 0x0000, 0, 0),
-	MX6_PAD_CSI0_DAT16__UART4_RTS		= IOMUX_PAD(0x0378, 0x0064, 3, 0x0910, 0, 0),
-	MX6_PAD_CSI0_DAT16__SDMA_DEBUG_PC_10	= IOMUX_PAD(0x0378, 0x0064, 4, 0x0000, 0, 0),
-	MX6_PAD_CSI0_DAT16__GPIO_6_2		= IOMUX_PAD(0x0378, 0x0064, 5, 0x0000, 0, 0),
-	MX6_PAD_CSI0_DAT16__MMDC_MMDC_DEBUG_39	= IOMUX_PAD(0x0378, 0x0064, 6, 0x0000, 0, 0),
-	MX6_PAD_CSI0_DAT16__SIMBA_TRACE_13	= IOMUX_PAD(0x0378, 0x0064, 7, 0x0000, 0, 0),
-	MX6_PAD_CSI0_DAT17__IPU1_CSI0_D_17	= IOMUX_PAD(0x037C, 0x0068, 0, 0x0000, 0, 0),
-	MX6_PAD_CSI0_DAT17__WEIM_WEIM_D_13	= IOMUX_PAD(0x037C, 0x0068, 1, 0x0000, 0, 0),
-	MX6_PAD_CSI0_DAT17__PCIE_CTRL_DIAG_STATUS_BUS_MUX_21	= IOMUX_PAD(0x037C, 0x0068, 2, 0x0000, 0, 0),
-	MX6_PAD_CSI0_DAT17__UART4_CTS		= IOMUX_PAD(0x037C, 0x0068, 3, 0x0000, 0, 0),
-	MX6_PAD_CSI0_DAT17__UART4_RTS		= IOMUX_PAD(0x037C, 0x0068, 3, 0x0910, 1, 0),
-	MX6_PAD_CSI0_DAT17__SDMA_DEBUG_PC_11	= IOMUX_PAD(0x037C, 0x0068, 4, 0x0000, 0, 0),
-	MX6_PAD_CSI0_DAT17__GPIO_6_3		= IOMUX_PAD(0x037C, 0x0068, 5, 0x0000, 0, 0),
-	MX6_PAD_CSI0_DAT17__MMDC_MMDC_DEBUG_40	= IOMUX_PAD(0x037C, 0x0068, 6, 0x0000, 0, 0),
-	MX6_PAD_CSI0_DAT17__SIMBA_TRACE_14	= IOMUX_PAD(0x037C, 0x0068, 7, 0x0000, 0, 0),
-	MX6_PAD_CSI0_DAT18__IPU1_CSI0_D_18	= IOMUX_PAD(0x0380, 0x006C, 0, 0x0000, 0, 0),
-	MX6_PAD_CSI0_DAT18__WEIM_WEIM_D_14	= IOMUX_PAD(0x0380, 0x006C, 1, 0x0000, 0, 0),
-	MX6_PAD_CSI0_DAT18__PCIE_CTRL_DIAG_STATUS_BUS_MUX_22	= IOMUX_PAD(0x0380, 0x006C, 2, 0x0000, 0, 0),
-	MX6_PAD_CSI0_DAT18__UART5_CTS		= IOMUX_PAD(0x0380, 0x006C, 3, 0x0000, 0, 0),
-	MX6_PAD_CSI0_DAT18__UART5_RTS		= IOMUX_PAD(0x0380, 0x006C, 3, 0x0918, 0, 0),
-	MX6_PAD_CSI0_DAT18__SDMA_DEBUG_PC_12	= IOMUX_PAD(0x0380, 0x006C, 4, 0x0000, 0, 0),
-	MX6_PAD_CSI0_DAT18__GPIO_6_4		= IOMUX_PAD(0x0380, 0x006C, 5, 0x0000, 0, 0),
-	MX6_PAD_CSI0_DAT18__MMDC_MMDC_DEBUG_41	= IOMUX_PAD(0x0380, 0x006C, 6, 0x0000, 0, 0),
-	MX6_PAD_CSI0_DAT18__SIMBA_TRACE_15	= IOMUX_PAD(0x0380, 0x006C, 7, 0x0000, 0, 0),
-	MX6_PAD_CSI0_DAT19__IPU1_CSI0_D_19	= IOMUX_PAD(0x0384, 0x0070, 0, 0x0000, 0, 0),
-	MX6_PAD_CSI0_DAT19__WEIM_WEIM_D_15	= IOMUX_PAD(0x0384, 0x0070, 1, 0x0000, 0, 0),
-	MX6_PAD_CSI0_DAT19__PCIE_CTRL_DIAG_STATUS_BUS_MUX_23	= IOMUX_PAD(0x0384, 0x0070, 2, 0x0000, 0, 0),
-	MX6_PAD_CSI0_DAT19__UART5_CTS		= IOMUX_PAD(0x0384, 0x0070, 3, 0x0000, 0, 0),
-	MX6_PAD_CSI0_DAT19__UART5_RTS		= IOMUX_PAD(0x0384, 0x0070, 3, 0x0918, 1, 0),
-	MX6_PAD_CSI0_DAT19__SDMA_DEBUG_PC_13	= IOMUX_PAD(0x0384, 0x0070, 4, 0x0000, 0, 0),
-	MX6_PAD_CSI0_DAT19__GPIO_6_5		= IOMUX_PAD(0x0384, 0x0070, 5, 0x0000, 0, 0),
-	MX6_PAD_CSI0_DAT19__MMDC_MMDC_DEBUG_42	= IOMUX_PAD(0x0384, 0x0070, 6, 0x0000, 0, 0),
-	MX6_PAD_CSI0_DAT19__ANATOP_ANATOP_TESTO_9	= IOMUX_PAD(0x0384, 0x0070, 7, 0x0000, 0, 0),
-	MX6_PAD_CSI0_DAT4__IPU1_CSI0_D_4	= IOMUX_PAD(0x0388, 0x0074, 0, 0x0000, 0, 0),
-	MX6_PAD_CSI0_DAT4__WEIM_WEIM_D_2	= IOMUX_PAD(0x0388, 0x0074, 1, 0x0000, 0, 0),
-	MX6_PAD_CSI0_DAT4__ECSPI1_SCLK		= IOMUX_PAD(0x0388, 0x0074, 2, 0x07D8, 0, 0),
-	MX6_PAD_CSI0_DAT4__KPP_COL_5		= IOMUX_PAD(0x0388, 0x0074, 3, 0x08C0, 0, 0),
-	MX6_PAD_CSI0_DAT4__AUDMUX_AUD3_TXC	= IOMUX_PAD(0x0388, 0x0074, 4, 0x0000, 0, 0),
-	MX6_PAD_CSI0_DAT4__GPIO_5_22		= IOMUX_PAD(0x0388, 0x0074, 5, 0x0000, 0, 0),
-	MX6_PAD_CSI0_DAT4__MMDC_MMDC_DEBUG_43	= IOMUX_PAD(0x0388, 0x0074, 6, 0x0000, 0, 0),
-	MX6_PAD_CSI0_DAT4__SIMBA_TRACE_1	= IOMUX_PAD(0x0388, 0x0074, 7, 0x0000, 0, 0),
-	MX6_PAD_CSI0_DAT5__IPU1_CSI0_D_5	= IOMUX_PAD(0x038C, 0x0078, 0, 0x0000, 0, 0),
-	MX6_PAD_CSI0_DAT5__WEIM_WEIM_D_3	= IOMUX_PAD(0x038C, 0x0078, 1, 0x0000, 0, 0),
-	MX6_PAD_CSI0_DAT5__ECSPI1_MOSI		= IOMUX_PAD(0x038C, 0x0078, 2, 0x07E0, 0, 0),
-	MX6_PAD_CSI0_DAT5__KPP_ROW_5		= IOMUX_PAD(0x038C, 0x0078, 3, 0x08CC, 0, 0),
-	MX6_PAD_CSI0_DAT5__AUDMUX_AUD3_TXD	= IOMUX_PAD(0x038C, 0x0078, 4, 0x0000, 0, 0),
-	MX6_PAD_CSI0_DAT5__GPIO_5_23		= IOMUX_PAD(0x038C, 0x0078, 5, 0x0000, 0, 0),
-	MX6_PAD_CSI0_DAT5__MMDC_MMDC_DEBUG_44	= IOMUX_PAD(0x038C, 0x0078, 6, 0x0000, 0, 0),
-	MX6_PAD_CSI0_DAT5__SIMBA_TRACE_2	= IOMUX_PAD(0x038C, 0x0078, 7, 0x0000, 0, 0),
-	MX6_PAD_CSI0_DAT6__IPU1_CSI0_D_6	= IOMUX_PAD(0x0390, 0x007C, 0, 0x0000, 0, 0),
-	MX6_PAD_CSI0_DAT6__WEIM_WEIM_D_4	= IOMUX_PAD(0x0390, 0x007C, 1, 0x0000, 0, 0),
-	MX6_PAD_CSI0_DAT6__ECSPI1_MISO		= IOMUX_PAD(0x0390, 0x007C, 2, 0x07DC, 0, 0),
-	MX6_PAD_CSI0_DAT6__KPP_COL_6		= IOMUX_PAD(0x0390, 0x007C, 3, 0x08C4, 0, 0),
-	MX6_PAD_CSI0_DAT6__AUDMUX_AUD3_TXFS	= IOMUX_PAD(0x0390, 0x007C, 4, 0x0000, 0, 0),
-	MX6_PAD_CSI0_DAT6__GPIO_5_24		= IOMUX_PAD(0x0390, 0x007C, 5, 0x0000, 0, 0),
-	MX6_PAD_CSI0_DAT6__MMDC_MMDC_DEBUG_45	= IOMUX_PAD(0x0390, 0x007C, 6, 0x0000, 0, 0),
-	MX6_PAD_CSI0_DAT6__SIMBA_TRACE_3	= IOMUX_PAD(0x0390, 0x007C, 7, 0x0000, 0, 0),
-	MX6_PAD_CSI0_DAT7__IPU1_CSI0_D_7	= IOMUX_PAD(0x0394, 0x0080, 0, 0x0000, 0, 0),
-	MX6_PAD_CSI0_DAT7__WEIM_WEIM_D_5	= IOMUX_PAD(0x0394, 0x0080, 1, 0x0000, 0, 0),
-	MX6_PAD_CSI0_DAT7__ECSPI1_SS0		= IOMUX_PAD(0x0394, 0x0080, 2, 0x07E4, 0, 0),
-	MX6_PAD_CSI0_DAT7__KPP_ROW_6		= IOMUX_PAD(0x0394, 0x0080, 3, 0x08D0, 0, 0),
-	MX6_PAD_CSI0_DAT7__AUDMUX_AUD3_RXD	= IOMUX_PAD(0x0394, 0x0080, 4, 0x0000, 0, 0),
-	MX6_PAD_CSI0_DAT7__GPIO_5_25		= IOMUX_PAD(0x0394, 0x0080, 5, 0x0000, 0, 0),
-	MX6_PAD_CSI0_DAT7__MMDC_MMDC_DEBUG_46	= IOMUX_PAD(0x0394, 0x0080, 6, 0x0000, 0, 0),
-	MX6_PAD_CSI0_DAT7__SIMBA_TRACE_4	= IOMUX_PAD(0x0394, 0x0080, 7, 0x0000, 0, 0),
-	MX6_PAD_CSI0_DAT8__IPU1_CSI0_D_8	= IOMUX_PAD(0x0398, 0x0084, 0, 0x0000, 0, 0),
-	MX6_PAD_CSI0_DAT8__WEIM_WEIM_D_6	= IOMUX_PAD(0x0398, 0x0084, 1, 0x0000, 0, 0),
-	MX6_PAD_CSI0_DAT8__ECSPI2_SCLK		= IOMUX_PAD(0x0398, 0x0084, 2, 0x07F4, 0, 0),
-	MX6_PAD_CSI0_DAT8__KPP_COL_7		= IOMUX_PAD(0x0398, 0x0084, 3, 0x08C8, 0, 0),
-	MX6_PAD_CSI0_DAT8__I2C1_SDA		= IOMUX_PAD(0x0398, 0x0084, 4 | IOMUX_CONFIG_SION, 0x086C, 0, 0),
-	MX6_PAD_CSI0_DAT8__GPIO_5_26		= IOMUX_PAD(0x0398, 0x0084, 5, 0x0000, 0, 0),
-	MX6_PAD_CSI0_DAT8__MMDC_MMDC_DEBUG_47	= IOMUX_PAD(0x0398, 0x0084, 6, 0x0000, 0, 0),
-	MX6_PAD_CSI0_DAT8__SIMBA_TRACE_5	= IOMUX_PAD(0x0398, 0x0084, 7, 0x0000, 0, 0),
-	MX6_PAD_CSI0_DAT9__IPU1_CSI0_D_9	= IOMUX_PAD(0x039C, 0x0088, 0, 0x0000, 0, 0),
-	MX6_PAD_CSI0_DAT9__WEIM_WEIM_D_7	= IOMUX_PAD(0x039C, 0x0088, 1, 0x0000, 0, 0),
-	MX6_PAD_CSI0_DAT9__ECSPI2_MOSI		= IOMUX_PAD(0x039C, 0x0088, 2, 0x07FC, 0, 0),
-	MX6_PAD_CSI0_DAT9__KPP_ROW_7		= IOMUX_PAD(0x039C, 0x0088, 3, 0x08D4, 0, 0),
-	MX6_PAD_CSI0_DAT9__I2C1_SCL		= IOMUX_PAD(0x039C, 0x0088, 4 | IOMUX_CONFIG_SION, 0x0868, 0, 0),
-	MX6_PAD_CSI0_DAT9__GPIO_5_27		= IOMUX_PAD(0x039C, 0x0088, 5, 0x0000, 0, 0),
-	MX6_PAD_CSI0_DAT9__MMDC_MMDC_DEBUG_48	= IOMUX_PAD(0x039C, 0x0088, 6, 0x0000, 0, 0),
-	MX6_PAD_CSI0_DAT9__SIMBA_TRACE_6	= IOMUX_PAD(0x039C, 0x0088, 7, 0x0000, 0, 0),
-	MX6_PAD_CSI0_DATA_EN__IPU1_CSI0_DATA_EN	= IOMUX_PAD(0x03A0, 0x008C, 0, 0x0000, 0, 0),
-	MX6_PAD_CSI0_DATA_EN__WEIM_WEIM_D_0	= IOMUX_PAD(0x03A0, 0x008C, 1, 0x0000, 0, 0),
-	MX6_PAD_CSI0_DATA_EN__PCIE_CTRL_DIAG_STATUS_BUS_MUX_14	= IOMUX_PAD(0x03A0, 0x008C, 2, 0x0000, 0, 0),
-	MX6_PAD_CSI0_DATA_EN__SDMA_DEBUG_PC_2	= IOMUX_PAD(0x03A0, 0x008C, 4, 0x0000, 0, 0),
-	MX6_PAD_CSI0_DATA_EN__GPIO_5_20		= IOMUX_PAD(0x03A0, 0x008C, 5, 0x0000, 0, 0),
-	MX6_PAD_CSI0_DATA_EN__MMDC_MMDC_DEBUG_31	= IOMUX_PAD(0x03A0, 0x008C, 6, 0x0000, 0, 0),
-	MX6_PAD_CSI0_DATA_EN__SIMBA_TRCLK	= IOMUX_PAD(0x03A0, 0x008C, 7, 0x0000, 0, 0),
-	MX6_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC	= IOMUX_PAD(0x03A4, 0x0090, 0, 0x0000, 0, 0),
-	MX6_PAD_CSI0_MCLK__PCIE_CTRL_DIAG_STATUS_BUS_MUX_13	= IOMUX_PAD(0x03A4, 0x0090, 2, 0x0000, 0, 0),
-	MX6_PAD_CSI0_MCLK__CCM_CLKO		= IOMUX_PAD(0x03A4, 0x0090, 3, 0x0000, 0, 0),
-	MX6_PAD_CSI0_MCLK__SDMA_DEBUG_PC_1	= IOMUX_PAD(0x03A4, 0x0090, 4, 0x0000, 0, 0),
-	MX6_PAD_CSI0_MCLK__GPIO_5_19		= IOMUX_PAD(0x03A4, 0x0090, 5, 0x0000, 0, 0),
-	MX6_PAD_CSI0_MCLK__MMDC_MMDC_DEBUG_30	= IOMUX_PAD(0x03A4, 0x0090, 6, 0x0000, 0, 0),
-	MX6_PAD_CSI0_MCLK__SIMBA_TRCTL		= IOMUX_PAD(0x03A4, 0x0090, 7, 0x0000, 0, 0),
-	MX6_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK	= IOMUX_PAD(0x03A8, 0x0094, 0, 0x0000, 0, 0),
-	MX6_PAD_CSI0_PIXCLK__PCIE_CTRL_DIAG_STATUS_BUS_MUX_12	= IOMUX_PAD(0x03A8, 0x0094, 2, 0x0000, 0, 0),
-	MX6_PAD_CSI0_PIXCLK__SDMA_DEBUG_PC_0	= IOMUX_PAD(0x03A8, 0x0094, 4, 0x0000, 0, 0),
-	MX6_PAD_CSI0_PIXCLK__GPIO_5_18		= IOMUX_PAD(0x03A8, 0x0094, 5, 0x0000, 0, 0),
-	MX6_PAD_CSI0_PIXCLK__MMDC_MMDC_DEBUG_29	= IOMUX_PAD(0x03A8, 0x0094, 6, 0x0000, 0, 0),
-	MX6_PAD_CSI0_PIXCLK__SIMBA_EVENTO	= IOMUX_PAD(0x03A8, 0x0094, 7, 0x0000, 0, 0),
-	MX6_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC	= IOMUX_PAD(0x03AC, 0x0098, 0, 0x0000, 0, 0),
-	MX6_PAD_CSI0_VSYNC__WEIM_WEIM_D_1	= IOMUX_PAD(0x03AC, 0x0098, 1, 0x0000, 0, 0),
-	MX6_PAD_CSI0_VSYNC__PCIE_CTRL_DIAG_STATUS_BUS_MUX_15	= IOMUX_PAD(0x03AC, 0x0098, 2, 0x0000, 0, 0),
-	MX6_PAD_CSI0_VSYNC__SDMA_DEBUG_PC_3	= IOMUX_PAD(0x03AC, 0x0098, 4, 0x0000, 0, 0),
-	MX6_PAD_CSI0_VSYNC__GPIO_5_21		= IOMUX_PAD(0x03AC, 0x0098, 5, 0x0000, 0, 0),
-	MX6_PAD_CSI0_VSYNC__MMDC_MMDC_DEBUG_32	= IOMUX_PAD(0x03AC, 0x0098, 6, 0x0000, 0, 0),
-	MX6_PAD_CSI0_VSYNC__SIMBA_TRACE_0	= IOMUX_PAD(0x03AC, 0x0098, 7, 0x0000, 0, 0),
-	MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK	= IOMUX_PAD(0x03B0, 0x009C, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
-	MX6_PAD_DI0_DISP_CLK__LCDIF_CLK		= IOMUX_PAD(0x03B0, 0x009C, 1, 0x0000, 0, 0),
-	MX6_PAD_DI0_DISP_CLK__MIPI_CORE_DPHY_TEST_OUT_28	= IOMUX_PAD(0x03B0, 0x009C, 3, 0x0000, 0, 0),
-	MX6_PAD_DI0_DISP_CLK__SDMA_DEBUG_CORE_STATE_0	= IOMUX_PAD(0x03B0, 0x009C, 4, 0x0000, 0, 0),
-	MX6_PAD_DI0_DISP_CLK__GPIO_4_16		= IOMUX_PAD(0x03B0, 0x009C, 5, 0x0000, 0, 0),
-	MX6_PAD_DI0_DISP_CLK__MMDC_MMDC_DEBUG_0	= IOMUX_PAD(0x03B0, 0x009C, 6, 0x0000, 0, 0),
-	MX6_PAD_DI0_DISP_CLK__TPSMP_HDATA_DIR	= IOMUX_PAD(0x03B0, 0x009C, 7, 0x0000, 0, 0),
-	MX6_PAD_DI0_DISP_CLK__LCDIF_WR_RWN	= IOMUX_PAD(0x03B0, 0x009C, 8, 0x0000, 0, 0),
-	MX6_PAD_DI0_PIN15__IPU1_DI0_PIN15	= IOMUX_PAD(0x03B4, 0x00A0, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
-	MX6_PAD_DI0_PIN15__LCDIF_ENABLE		= IOMUX_PAD(0x03B4, 0x00A0, 1, 0x0000, 0, 0),
-	MX6_PAD_DI0_PIN15__AUDMUX_AUD6_TXC	= IOMUX_PAD(0x03B4, 0x00A0, 2, 0x0000, 0, 0),
-	MX6_PAD_DI0_PIN15__MIPI_CORE_DPHY_TEST_OUT_29	= IOMUX_PAD(0x03B4, 0x00A0, 3, 0x0000, 0, 0),
-	MX6_PAD_DI0_PIN15__SDMA_DEBUG_CORE_STATE_1	= IOMUX_PAD(0x03B4, 0x00A0, 4, 0x0000, 0, 0),
-	MX6_PAD_DI0_PIN15__GPIO_4_17		= IOMUX_PAD(0x03B4, 0x00A0, 5, 0x0000, 0, 0),
-	MX6_PAD_DI0_PIN15__MMDC_MMDC_DEBUG_1	= IOMUX_PAD(0x03B4, 0x00A0, 6, 0x0000, 0, 0),
-	MX6_PAD_DI0_PIN15__PL301_SIM_MX6DL_PER1_HSIZE_0	= IOMUX_PAD(0x03B4, 0x00A0, 7, 0x0000, 0, 0),
-	MX6_PAD_DI0_PIN15__LCDIF_RD_E		= IOMUX_PAD(0x03B4, 0x00A0, 8, 0x0000, 0, 0),
-	MX6_PAD_DI0_PIN2__IPU1_DI0_PIN2		= IOMUX_PAD(0x03B8, 0x00A4, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
-	MX6_PAD_DI0_PIN2__LCDIF_HSYNC		= IOMUX_PAD(0x03B8, 0x00A4, 1, 0x08D8, 0, 0),
-	MX6_PAD_DI0_PIN2__AUDMUX_AUD6_TXD	= IOMUX_PAD(0x03B8, 0x00A4, 2, 0x0000, 0, 0),
-	MX6_PAD_DI0_PIN2__MIPI_CORE_DPHY_TEST_OUT_30	= IOMUX_PAD(0x03B8, 0x00A4, 3, 0x0000, 0, 0),
-	MX6_PAD_DI0_PIN2__SDMA_DEBUG_CORE_STATE_2	= IOMUX_PAD(0x03B8, 0x00A4, 4, 0x0000, 0, 0),
-	MX6_PAD_DI0_PIN2__GPIO_4_18		= IOMUX_PAD(0x03B8, 0x00A4, 5, 0x0000, 0, 0),
-	MX6_PAD_DI0_PIN2__MMDC_MMDC_DEBUG_2	= IOMUX_PAD(0x03B8, 0x00A4, 6, 0x0000, 0, 0),
-	MX6_PAD_DI0_PIN2__PL301_SIM_MX6DL_PER1_HADDR_9	= IOMUX_PAD(0x03B8, 0x00A4, 7, 0x0000, 0, 0),
-	MX6_PAD_DI0_PIN2__LCDIF_RS		= IOMUX_PAD(0x03B8, 0x00A4, 8, 0x0000, 0, 0),
-	MX6_PAD_DI0_PIN3__IPU1_DI0_PIN3		= IOMUX_PAD(0x03BC, 0x00A8, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
-	MX6_PAD_DI0_PIN3__LCDIF_VSYNC		= IOMUX_PAD(0x03BC, 0x00A8, 1, 0x0000, 0, 0),
-	MX6_PAD_DI0_PIN3__AUDMUX_AUD6_TXFS	= IOMUX_PAD(0x03BC, 0x00A8, 2, 0x0000, 0, 0),
-	MX6_PAD_DI0_PIN3__MIPI_CORE_DPHY_TEST_OUT_31	= IOMUX_PAD(0x03BC, 0x00A8, 3, 0x0000, 0, 0),
-	MX6_PAD_DI0_PIN3__SDMA_DEBUG_CORE_STATE_3	= IOMUX_PAD(0x03BC, 0x00A8, 4, 0x0000, 0, 0),
-	MX6_PAD_DI0_PIN3__GPIO_4_19		= IOMUX_PAD(0x03BC, 0x00A8, 5, 0x0000, 0, 0),
-	MX6_PAD_DI0_PIN3__MMDC_MMDC_DEBUG_3	= IOMUX_PAD(0x03BC, 0x00A8, 6, 0x0000, 0, 0),
-	MX6_PAD_DI0_PIN3__PL301_SIM_MX6DL_PER1_HADDR_10	= IOMUX_PAD(0x03BC, 0x00A8, 7, 0x0000, 0, 0),
-	MX6_PAD_DI0_PIN3__LCDIF_CS		= IOMUX_PAD(0x03BC, 0x00A8, 8, 0x0000, 0, 0),
-	MX6_PAD_DI0_PIN4__IPU1_DI0_PIN4		= IOMUX_PAD(0x03C0, 0x00AC, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
-	MX6_PAD_DI0_PIN4__LCDIF_BUSY		= IOMUX_PAD(0x03C0, 0x00AC, 1, 0x08D8, 1, 0),
-	MX6_PAD_DI0_PIN4__AUDMUX_AUD6_RXD	= IOMUX_PAD(0x03C0, 0x00AC, 2, 0x0000, 0, 0),
-	MX6_PAD_DI0_PIN4__USDHC1_WP		= IOMUX_PAD(0x03C0, 0x00AC, 3, 0x092C, 0, 0),
-	MX6_PAD_DI0_PIN4__SDMA_DEBUG_YIELD	= IOMUX_PAD(0x03C0, 0x00AC, 4, 0x0000, 0, 0),
-	MX6_PAD_DI0_PIN4__GPIO_4_20		= IOMUX_PAD(0x03C0, 0x00AC, 5, 0x0000, 0, 0),
-	MX6_PAD_DI0_PIN4__MMDC_MMDC_DEBUG_4	= IOMUX_PAD(0x03C0, 0x00AC, 6, 0x0000, 0, 0),
-	MX6_PAD_DI0_PIN4__PL301_SIM_MX6DL_PER1_HADDR_11	= IOMUX_PAD(0x03C0, 0x00AC, 7, 0x0000, 0, 0),
-	MX6_PAD_DI0_PIN4__LCDIF_RESET		= IOMUX_PAD(0x03C0, 0x00AC, 8, 0x0000, 0, 0),
-	MX6_PAD_DISP0_DAT0__IPU1_DISP0_DAT_0	= IOMUX_PAD(0x03C4, 0x00B0, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
-	MX6_PAD_DISP0_DAT0__LCDIF_DAT_0		= IOMUX_PAD(0x03C4, 0x00B0, 1, 0x0000, 0, 0),
-	MX6_PAD_DISP0_DAT0__ECSPI3_SCLK		= IOMUX_PAD(0x03C4, 0x00B0, 2, 0x0000, 0, 0),
-	MX6_PAD_DISP0_DAT0__USDHC1_USDHC_DEBUG_0	= IOMUX_PAD(0x03C4, 0x00B0, 3, 0x0000, 0, 0),
-	MX6_PAD_DISP0_DAT0__SDMA_DEBUG_CORE_RUN	= IOMUX_PAD(0x03C4, 0x00B0, 4, 0x0000, 0, 0),
-	MX6_PAD_DISP0_DAT0__GPIO_4_21		= IOMUX_PAD(0x03C4, 0x00B0, 5, 0x0000, 0, 0),
-	MX6_PAD_DISP0_DAT0__MMDC_MMDC_DEBUG_5	= IOMUX_PAD(0x03C4, 0x00B0, 6, 0x0000, 0, 0),
-	MX6_PAD_DISP0_DAT0__PL301_SIM_MX6DL_PER1_HSIZE_1	= IOMUX_PAD(0x03C4, 0x00B0, 7, 0x0000, 0, 0),
-	MX6_PAD_DISP0_DAT1__IPU1_DISP0_DAT_1	= IOMUX_PAD(0x03C8, 0x00B4, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
-	MX6_PAD_DISP0_DAT1__LCDIF_DAT_1		= IOMUX_PAD(0x03C8, 0x00B4, 1, 0x0000, 0, 0),
-	MX6_PAD_DISP0_DAT1__ECSPI3_MOSI		= IOMUX_PAD(0x03C8, 0x00B4, 2, 0x0000, 0, 0),
-	MX6_PAD_DISP0_DAT1__USDHC1_USDHC_DEBUG_1	= IOMUX_PAD(0x03C8, 0x00B4, 3, 0x0000, 0, 0),
-	MX6_PAD_DISP0_DAT1__SDMA_DEBUG_EVENT_CHANNEL_SEL	= IOMUX_PAD(0x03C8, 0x00B4, 4, 0x0000, 0, 0),
-	MX6_PAD_DISP0_DAT1__GPIO_4_22		= IOMUX_PAD(0x03C8, 0x00B4, 5, 0x0000, 0, 0),
-	MX6_PAD_DISP0_DAT1__MMDC_MMDC_DEBUG_6	= IOMUX_PAD(0x03C8, 0x00B4, 6, 0x0000, 0, 0),
-	MX6_PAD_DISP0_DAT1__PL301_SIM_MX6DL_PER1_HADDR_12	= IOMUX_PAD(0x03C8, 0x00B4, 7, 0x0000, 0, 0),
-	MX6_PAD_DISP0_DAT10__IPU1_DISP0_DAT_10	= IOMUX_PAD(0x03CC, 0x00B8, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
-	MX6_PAD_DISP0_DAT10__LCDIF_DAT_10	= IOMUX_PAD(0x03CC, 0x00B8, 1, 0x0000, 0, PAD_CTL_DSE_120ohm),
-	MX6_PAD_DISP0_DAT10__USDHC1_USDHC_DEBUG_6	= IOMUX_PAD(0x03CC, 0x00B8, 3, 0x0000, 0, 0),
-	MX6_PAD_DISP0_DAT10__SDMA_DEBUG_EVENT_CHANNEL_3	= IOMUX_PAD(0x03CC, 0x00B8, 4, 0x0000, 0, 0),
-	MX6_PAD_DISP0_DAT10__GPIO_4_31		= IOMUX_PAD(0x03CC, 0x00B8, 5, 0x0000, 0, 0),
-	MX6_PAD_DISP0_DAT10__MMDC_MMDC_DEBUG_15	= IOMUX_PAD(0x03CC, 0x00B8, 6, 0x0000, 0, 0),
-	MX6_PAD_DISP0_DAT10__PL301_SIM_MX6DL_PER1_HADDR_21	= IOMUX_PAD(0x03CC, 0x00B8, 7, 0x0000, 0, 0),
-	MX6_PAD_DISP0_DAT11__IPU1_DISP0_DAT_11	= IOMUX_PAD(0x03D0, 0x00BC, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
-	MX6_PAD_DISP0_DAT11__LCDIF_DAT_11	= IOMUX_PAD(0x03D0, 0x00BC, 1, 0x0000, 0, 0),
-	MX6_PAD_DISP0_DAT11__USDHC1_USDHC_DEBUG_7	= IOMUX_PAD(0x03D0, 0x00BC, 3, 0x0000, 0, 0),
-	MX6_PAD_DISP0_DAT11__SDMA_DEBUG_EVENT_CHANNEL_4	= IOMUX_PAD(0x03D0, 0x00BC, 4, 0x0000, 0, 0),
-	MX6_PAD_DISP0_DAT11__GPIO_5_5		= IOMUX_PAD(0x03D0, 0x00BC, 5, 0x0000, 0, 0),
-	MX6_PAD_DISP0_DAT11__MMDC_MMDC_DEBUG_16	= IOMUX_PAD(0x03D0, 0x00BC, 6, 0x0000, 0, 0),
-	MX6_PAD_DISP0_DAT11__PL301_SIM_MX6DL_PER1_HADDR_22	= IOMUX_PAD(0x03D0, 0x00BC, 7, 0x0000, 0, 0),
-	MX6_PAD_DISP0_DAT12__IPU1_DISP0_DAT_12	= IOMUX_PAD(0x03D4, 0x00C0, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
-	MX6_PAD_DISP0_DAT12__LCDIF_DAT_12	= IOMUX_PAD(0x03D4, 0x00C0, 1, 0x0000, 0, 0),
-	MX6_PAD_DISP0_DAT12__SDMA_DEBUG_EVENT_CHANNEL_5	= IOMUX_PAD(0x03D4, 0x00C0, 4, 0x0000, 0, 0),
-	MX6_PAD_DISP0_DAT12__GPIO_5_6		= IOMUX_PAD(0x03D4, 0x00C0, 5, 0x0000, 0, 0),
-	MX6_PAD_DISP0_DAT12__MMDC_MMDC_DEBUG_17	= IOMUX_PAD(0x03D4, 0x00C0, 6, 0x0000, 0, 0),
-	MX6_PAD_DISP0_DAT12__PL301_SIM_MX6DL_PER1_HADDR_23	= IOMUX_PAD(0x03D4, 0x00C0, 7, 0x0000, 0, 0),
-	MX6_PAD_DISP0_DAT13__IPU1_DISP0_DAT_13	= IOMUX_PAD(0x03D8, 0x00C4, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
-	MX6_PAD_DISP0_DAT13__LCDIF_DAT_13	= IOMUX_PAD(0x03D8, 0x00C4, 1, 0x0000, 0, 0),
-	MX6_PAD_DISP0_DAT13__AUDMUX_AUD5_RXFS	= IOMUX_PAD(0x03D8, 0x00C4, 3, 0x07BC, 0, 0),
-	MX6_PAD_DISP0_DAT13__SDMA_DEBUG_EVT_CHN_LINES_0	= IOMUX_PAD(0x03D8, 0x00C4, 4, 0x0000, 0, 0),
-	MX6_PAD_DISP0_DAT13__GPIO_5_7		= IOMUX_PAD(0x03D8, 0x00C4, 5, 0x0000, 0, 0),
-	MX6_PAD_DISP0_DAT13__MMDC_MMDC_DEBUG_18	= IOMUX_PAD(0x03D8, 0x00C4, 6, 0x0000, 0, 0),
-	MX6_PAD_DISP0_DAT13__PL301_SIM_MX6DL_PER1_HADDR_24	= IOMUX_PAD(0x03D8, 0x00C4, 7, 0x0000, 0, 0),
-	MX6_PAD_DISP0_DAT14__IPU1_DISP0_DAT_14	= IOMUX_PAD(0x03DC, 0x00C8, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
-	MX6_PAD_DISP0_DAT14__LCDIF_DAT_14	= IOMUX_PAD(0x03DC, 0x00C8, 1, 0x0000, 0, 0),
-	MX6_PAD_DISP0_DAT14__AUDMUX_AUD5_RXC	= IOMUX_PAD(0x03DC, 0x00C8, 3, 0x07B8, 0, 0),
-	MX6_PAD_DISP0_DAT14__SDMA_DEBUG_EVT_CHN_LINES_1	= IOMUX_PAD(0x03DC, 0x00C8, 4, 0x0000, 0, 0),
-	MX6_PAD_DISP0_DAT14__GPIO_5_8		= IOMUX_PAD(0x03DC, 0x00C8, 5, 0x0000, 0, 0),
-	MX6_PAD_DISP0_DAT14__MMDC_MMDC_DEBUG_19	= IOMUX_PAD(0x03DC, 0x00C8, 6, 0x0000, 0, 0),
-	MX6_PAD_DISP0_DAT14__PL301_SIM_MX6DL_PER1_HSIZE_2	= IOMUX_PAD(0x03DC, 0x00C8, 7, 0x0000, 0, 0),
-	MX6_PAD_DISP0_DAT15__IPU1_DISP0_DAT_15	= IOMUX_PAD(0x03E0, 0x00CC, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
-	MX6_PAD_DISP0_DAT15__LCDIF_DAT_15	= IOMUX_PAD(0x03E0, 0x00CC, 1, 0x0000, 0, 0),
-	MX6_PAD_DISP0_DAT15__ECSPI1_SS1		= IOMUX_PAD(0x03E0, 0x00CC, 2, 0x07E8, 0, 0),
-	MX6_PAD_DISP0_DAT15__ECSPI2_SS1		= IOMUX_PAD(0x03E0, 0x00CC, 3, 0x0804, 0, 0),
-	MX6_PAD_DISP0_DAT15__SDMA_DEBUG_EVT_CHN_LINES_2	= IOMUX_PAD(0x03E0, 0x00CC, 4, 0x0000, 0, 0),
-	MX6_PAD_DISP0_DAT15__GPIO_5_9		= IOMUX_PAD(0x03E0, 0x00CC, 5, 0x0000, 0, 0),
-	MX6_PAD_DISP0_DAT15__MMDC_MMDC_DEBUG_20	= IOMUX_PAD(0x03E0, 0x00CC, 6, 0x0000, 0, 0),
-	MX6_PAD_DISP0_DAT15__PL301_SIM_MX6DL_PER1_HADDR_25	= IOMUX_PAD(0x03E0, 0x00CC, 7, 0x0000, 0, 0),
-	MX6_PAD_DISP0_DAT16__IPU1_DISP0_DAT_16	= IOMUX_PAD(0x03E4, 0x00D0, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
-	MX6_PAD_DISP0_DAT16__LCDIF_DAT_16	= IOMUX_PAD(0x03E4, 0x00D0, 1, 0x0000, 0, 0),
-	MX6_PAD_DISP0_DAT16__ECSPI2_MOSI	= IOMUX_PAD(0x03E4, 0x00D0, 2, 0x07FC, 1, 0),
-	MX6_PAD_DISP0_DAT16__AUDMUX_AUD5_TXC	= IOMUX_PAD(0x03E4, 0x00D0, 3, 0x07C0, 0, 0),
-	MX6_PAD_DISP0_DAT16__SDMA_SDMA_EXT_EVENT_0	= IOMUX_PAD(0x03E4, 0x00D0, 4, 0x08E8, 0, 0),
-	MX6_PAD_DISP0_DAT16__GPIO_5_10		= IOMUX_PAD(0x03E4, 0x00D0, 5, 0x0000, 0, 0),
-	MX6_PAD_DISP0_DAT16__MMDC_MMDC_DEBUG_21	= IOMUX_PAD(0x03E4, 0x00D0, 6, 0x0000, 0, 0),
-	MX6_PAD_DISP0_DAT16__PL301_SIM_MX6DL_PER1_HADDR_26	= IOMUX_PAD(0x03E4, 0x00D0, 7, 0x0000, 0, 0),
-	MX6_PAD_DISP0_DAT17__IPU1_DISP0_DAT_17	= IOMUX_PAD(0x03E8, 0x00D4, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
-	MX6_PAD_DISP0_DAT17__LCDIF_DAT_17	= IOMUX_PAD(0x03E8, 0x00D4, 1, 0x0000, 0, 0),
-	MX6_PAD_DISP0_DAT17__ECSPI2_MISO	= IOMUX_PAD(0x03E8, 0x00D4, 2, 0x07F8, 1, 0),
-	MX6_PAD_DISP0_DAT17__AUDMUX_AUD5_TXD	= IOMUX_PAD(0x03E8, 0x00D4, 3, 0x07B4, 0, 0),
-	MX6_PAD_DISP0_DAT17__SDMA_SDMA_EXT_EVENT_1	= IOMUX_PAD(0x03E8, 0x00D4, 4, 0x08EC, 0, 0),
-	MX6_PAD_DISP0_DAT17__GPIO_5_11		= IOMUX_PAD(0x03E8, 0x00D4, 5, 0x0000, 0, 0),
-	MX6_PAD_DISP0_DAT17__MMDC_MMDC_DEBUG_22	= IOMUX_PAD(0x03E8, 0x00D4, 6, 0x0000, 0, 0),
-	MX6_PAD_DISP0_DAT17__PL301_SIM_MX6DL_PER1_HADDR_27	= IOMUX_PAD(0x03E8, 0x00D4, 7, 0x0000, 0, 0),
-	MX6_PAD_DISP0_DAT18__IPU1_DISP0_DAT_18	= IOMUX_PAD(0x03EC, 0x00D8, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
-	MX6_PAD_DISP0_DAT18__LCDIF_DAT_18	= IOMUX_PAD(0x03EC, 0x00D8, 1, 0x0000, 0, 0),
-	MX6_PAD_DISP0_DAT18__ECSPI2_SS0		= IOMUX_PAD(0x03EC, 0x00D8, 2, 0x0800, 1, 0),
-	MX6_PAD_DISP0_DAT18__AUDMUX_AUD5_TXFS	= IOMUX_PAD(0x03EC, 0x00D8, 3, 0x07C4, 0, 0),
-	MX6_PAD_DISP0_DAT18__AUDMUX_AUD4_RXFS	= IOMUX_PAD(0x03EC, 0x00D8, 4, 0x07A4, 0, 0),
-	MX6_PAD_DISP0_DAT18__GPIO_5_12		= IOMUX_PAD(0x03EC, 0x00D8, 5, 0x0000, 0, 0),
-	MX6_PAD_DISP0_DAT18__MMDC_MMDC_DEBUG_23	= IOMUX_PAD(0x03EC, 0x00D8, 6, 0x0000, 0, 0),
-	MX6_PAD_DISP0_DAT18__WEIM_WEIM_CS_2	= IOMUX_PAD(0x03EC, 0x00D8, 7, 0x0000, 0, 0),
-	MX6_PAD_DISP0_DAT19__IPU1_DISP0_DAT_19	= IOMUX_PAD(0x03F0, 0x00DC, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
-	MX6_PAD_DISP0_DAT19__LCDIF_DAT_19	= IOMUX_PAD(0x03F0, 0x00DC, 1, 0x0000, 0, 0),
-	MX6_PAD_DISP0_DAT19__ECSPI2_SCLK	= IOMUX_PAD(0x03F0, 0x00DC, 2, 0x07F4, 1, 0),
-	MX6_PAD_DISP0_DAT19__AUDMUX_AUD5_RXD	= IOMUX_PAD(0x03F0, 0x00DC, 3, 0x07B0, 0, 0),
-	MX6_PAD_DISP0_DAT19__AUDMUX_AUD4_RXC	= IOMUX_PAD(0x03F0, 0x00DC, 4, 0x07A0, 0, 0),
-	MX6_PAD_DISP0_DAT19__GPIO_5_13		= IOMUX_PAD(0x03F0, 0x00DC, 5, 0x0000, 0, 0),
-	MX6_PAD_DISP0_DAT19__MMDC_MMDC_DEBUG_24	= IOMUX_PAD(0x03F0, 0x00DC, 6, 0x0000, 0, 0),
-	MX6_PAD_DISP0_DAT19__WEIM_WEIM_CS_3	= IOMUX_PAD(0x03F0, 0x00DC, 7, 0x0000, 0, 0),
-	MX6_PAD_DISP0_DAT2__IPU1_DISP0_DAT_2	= IOMUX_PAD(0x03F4, 0x00E0, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
-	MX6_PAD_DISP0_DAT2__LCDIF_DAT_2		= IOMUX_PAD(0x03F4, 0x00E0, 1, 0x0000, 0, 0),
-	MX6_PAD_DISP0_DAT2__ECSPI3_MISO		= IOMUX_PAD(0x03F4, 0x00E0, 2, 0x0000, 0, 0),
-	MX6_PAD_DISP0_DAT2__USDHC1_USDHC_DEBUG_2	= IOMUX_PAD(0x03F4, 0x00E0, 3, 0x0000, 0, 0),
-	MX6_PAD_DISP0_DAT2__SDMA_DEBUG_MODE	= IOMUX_PAD(0x03F4, 0x00E0, 4, 0x0000, 0, 0),
-	MX6_PAD_DISP0_DAT2__GPIO_4_23		= IOMUX_PAD(0x03F4, 0x00E0, 5, 0x0000, 0, 0),
-	MX6_PAD_DISP0_DAT2__MMDC_MMDC_DEBUG_7	= IOMUX_PAD(0x03F4, 0x00E0, 6, 0x0000, 0, 0),
-	MX6_PAD_DISP0_DAT2__PL301_SIM_MX6DL_PER1_HADDR_13	= IOMUX_PAD(0x03F4, 0x00E0, 7, 0x0000, 0, 0),
-	MX6_PAD_DISP0_DAT20__IPU1_DISP0_DAT_20	= IOMUX_PAD(0x03F8, 0x00E4, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
-	MX6_PAD_DISP0_DAT20__LCDIF_DAT_20	= IOMUX_PAD(0x03F8, 0x00E4, 1, 0x0000, 0, 0),
-	MX6_PAD_DISP0_DAT20__ECSPI1_SCLK	= IOMUX_PAD(0x03F8, 0x00E4, 2, 0x07D8, 1, 0),
-	MX6_PAD_DISP0_DAT20__AUDMUX_AUD4_TXC	= IOMUX_PAD(0x03F8, 0x00E4, 3, 0x07A8, 0, 0),
-	MX6_PAD_DISP0_DAT20__SDMA_DEBUG_EVT_CHN_LINES_7	= IOMUX_PAD(0x03F8, 0x00E4, 4, 0x0000, 0, 0),
-	MX6_PAD_DISP0_DAT20__GPIO_5_14		= IOMUX_PAD(0x03F8, 0x00E4, 5, 0x0000, 0, 0),
-	MX6_PAD_DISP0_DAT20__MMDC_MMDC_DEBUG_25	= IOMUX_PAD(0x03F8, 0x00E4, 6, 0x0000, 0, 0),
-	MX6_PAD_DISP0_DAT20__PL301_SIM_MX6DL_PER1_HADDR_28	= IOMUX_PAD(0x03F8, 0x00E4, 7, 0x0000, 0, 0),
-	MX6_PAD_DISP0_DAT21__IPU1_DISP0_DAT_21	= IOMUX_PAD(0x03FC, 0x00E8, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
-	MX6_PAD_DISP0_DAT21__LCDIF_DAT_21	= IOMUX_PAD(0x03FC, 0x00E8, 1, 0x0000, 0, 0),
-	MX6_PAD_DISP0_DAT21__ECSPI1_MOSI	= IOMUX_PAD(0x03FC, 0x00E8, 2, 0x07E0, 1, 0),
-	MX6_PAD_DISP0_DAT21__AUDMUX_AUD4_TXD	= IOMUX_PAD(0x03FC, 0x00E8, 3, 0x079C, 0, 0),
-	MX6_PAD_DISP0_DAT21__SDMA_DEBUG_BUS_DEVICE_0	= IOMUX_PAD(0x03FC, 0x00E8, 4, 0x0000, 0, 0),
-	MX6_PAD_DISP0_DAT21__GPIO_5_15		= IOMUX_PAD(0x03FC, 0x00E8, 5, 0x0000, 0, 0),
-	MX6_PAD_DISP0_DAT21__MMDC_MMDC_DEBUG_26	= IOMUX_PAD(0x03FC, 0x00E8, 6, 0x0000, 0, 0),
-	MX6_PAD_DISP0_DAT21__PL301_SIM_MX6DL_PER1_HADDR_29	= IOMUX_PAD(0x03FC, 0x00E8, 7, 0x0000, 0, 0),
-	MX6_PAD_DISP0_DAT22__IPU1_DISP0_DAT_22	= IOMUX_PAD(0x0400, 0x00EC, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
-	MX6_PAD_DISP0_DAT22__LCDIF_DAT_22	= IOMUX_PAD(0x0400, 0x00EC, 1, 0x0000, 0, 0),
-	MX6_PAD_DISP0_DAT22__ECSPI1_MISO	= IOMUX_PAD(0x0400, 0x00EC, 2, 0x07DC, 1, 0),
-	MX6_PAD_DISP0_DAT22__AUDMUX_AUD4_TXFS	= IOMUX_PAD(0x0400, 0x00EC, 3, 0x07AC, 0, 0),
-	MX6_PAD_DISP0_DAT22__SDMA_DEBUG_BUS_DEVICE_1	= IOMUX_PAD(0x0400, 0x00EC, 4, 0x0000, 0, 0),
-	MX6_PAD_DISP0_DAT22__GPIO_5_16		= IOMUX_PAD(0x0400, 0x00EC, 5, 0x0000, 0, 0),
-	MX6_PAD_DISP0_DAT22__MMDC_MMDC_DEBUG_27	= IOMUX_PAD(0x0400, 0x00EC, 6, 0x0000, 0, 0),
-	MX6_PAD_DISP0_DAT22__PL301_SIM_MX6DL_PER1_HADDR_30	= IOMUX_PAD(0x0400, 0x00EC, 7, 0x0000, 0, 0),
-	MX6_PAD_DISP0_DAT23__IPU1_DISP0_DAT_23	= IOMUX_PAD(0x0404, 0x00F0, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
-	MX6_PAD_DISP0_DAT23__LCDIF_DAT_23	= IOMUX_PAD(0x0404, 0x00F0, 1, 0x0000, 0, 0),
-	MX6_PAD_DISP0_DAT23__ECSPI1_SS0		= IOMUX_PAD(0x0404, 0x00F0, 2, 0x07E4, 1, 0),
-	MX6_PAD_DISP0_DAT23__AUDMUX_AUD4_RXD	= IOMUX_PAD(0x0404, 0x00F0, 3, 0x0798, 0, 0),
-	MX6_PAD_DISP0_DAT23__SDMA_DEBUG_BUS_DEVICE_2	= IOMUX_PAD(0x0404, 0x00F0, 4, 0x0000, 0, 0),
-	MX6_PAD_DISP0_DAT23__GPIO_5_17		= IOMUX_PAD(0x0404, 0x00F0, 5, 0x0000, 0, 0),
-	MX6_PAD_DISP0_DAT23__MMDC_MMDC_DEBUG_28	= IOMUX_PAD(0x0404, 0x00F0, 6, 0x0000, 0, 0),
-	MX6_PAD_DISP0_DAT23__PL301_SIM_MX6DL_PER1_HADDR_31	= IOMUX_PAD(0x0404, 0x00F0, 7, 0x0000, 0, 0),
-	MX6_PAD_DISP0_DAT3__IPU1_DISP0_DAT_3	= IOMUX_PAD(0x0408, 0x00F4, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
-	MX6_PAD_DISP0_DAT3__LCDIF_DAT_3		= IOMUX_PAD(0x0408, 0x00F4, 1, 0x0000, 0, 0),
-	MX6_PAD_DISP0_DAT3__ECSPI3_SS0		= IOMUX_PAD(0x0408, 0x00F4, 2, 0x0000, 0, 0),
-	MX6_PAD_DISP0_DAT3__USDHC1_USDHC_DEBUG_3	= IOMUX_PAD(0x0408, 0x00F4, 3, 0x0000, 0, 0),
-	MX6_PAD_DISP0_DAT3__SDMA_DEBUG_BUS_ERROR	= IOMUX_PAD(0x0408, 0x00F4, 4, 0x0000, 0, 0),
-	MX6_PAD_DISP0_DAT3__GPIO_4_24		= IOMUX_PAD(0x0408, 0x00F4, 5, 0x0000, 0, 0),
-	MX6_PAD_DISP0_DAT3__MMDC_MMDC_DEBUG_8	= IOMUX_PAD(0x0408, 0x00F4, 6, 0x0000, 0, 0),
-	MX6_PAD_DISP0_DAT3__PL301_SIM_MX6DL_PER1_HADDR_14	= IOMUX_PAD(0x0408, 0x00F4, 7, 0x0000, 0, 0),
-	MX6_PAD_DISP0_DAT4__IPU1_DISP0_DAT_4	= IOMUX_PAD(0x040C, 0x00F8, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
-	MX6_PAD_DISP0_DAT4__LCDIF_DAT_4		= IOMUX_PAD(0x040C, 0x00F8, 1, 0x0000, 0, 0),
-	MX6_PAD_DISP0_DAT4__ECSPI3_SS1		= IOMUX_PAD(0x040C, 0x00F8, 2, 0x0000, 0, 0),
-	MX6_PAD_DISP0_DAT4__USDHC1_USDHC_DEBUG_4	= IOMUX_PAD(0x040C, 0x00F8, 3, 0x0000, 0, 0),
-	MX6_PAD_DISP0_DAT4__SDMA_DEBUG_BUS_RWB	= IOMUX_PAD(0x040C, 0x00F8, 4, 0x0000, 0, 0),
-	MX6_PAD_DISP0_DAT4__GPIO_4_25		= IOMUX_PAD(0x040C, 0x00F8, 5, 0x0000, 0, 0),
-	MX6_PAD_DISP0_DAT4__MMDC_MMDC_DEBUG_9	= IOMUX_PAD(0x040C, 0x00F8, 6, 0x0000, 0, 0),
-	MX6_PAD_DISP0_DAT4__PL301_SIM_MX6DL_PER1_HADDR_15	= IOMUX_PAD(0x040C, 0x00F8, 7, 0x0000, 0, 0),
-	MX6_PAD_DISP0_DAT5__IPU1_DISP0_DAT_5	= IOMUX_PAD(0x0410, 0x00FC, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
-	MX6_PAD_DISP0_DAT5__LCDIF_DAT_5		= IOMUX_PAD(0x0410, 0x00FC, 1, 0x0000, 0, 0),
-	MX6_PAD_DISP0_DAT5__ECSPI3_SS2		= IOMUX_PAD(0x0410, 0x00FC, 2, 0x0000, 0, 0),
-	MX6_PAD_DISP0_DAT5__AUDMUX_AUD6_RXFS	= IOMUX_PAD(0x0410, 0x00FC, 3, 0x0000, 0, 0),
-	MX6_PAD_DISP0_DAT5__SDMA_DEBUG_MATCHED_DMBUS	= IOMUX_PAD(0x0410, 0x00FC, 4, 0x0000, 0, 0),
-	MX6_PAD_DISP0_DAT5__GPIO_4_26		= IOMUX_PAD(0x0410, 0x00FC, 5, 0x0000, 0, 0),
-	MX6_PAD_DISP0_DAT5__MMDC_MMDC_DEBUG_10	= IOMUX_PAD(0x0410, 0x00FC, 6, 0x0000, 0, 0),
-	MX6_PAD_DISP0_DAT5__PL301_SIM_MX6DL_PER1_HADDR_16	= IOMUX_PAD(0x0410, 0x00FC, 7, 0x0000, 0, 0),
-	MX6_PAD_DISP0_DAT6__IPU1_DISP0_DAT_6	= IOMUX_PAD(0x0414, 0x0100, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
-	MX6_PAD_DISP0_DAT6__LCDIF_DAT_6		= IOMUX_PAD(0x0414, 0x0100, 1, 0x0000, 0, 0),
-	MX6_PAD_DISP0_DAT6__ECSPI3_SS3		= IOMUX_PAD(0x0414, 0x0100, 2, 0x0000, 0, 0),
-	MX6_PAD_DISP0_DAT6__AUDMUX_AUD6_RXC	= IOMUX_PAD(0x0414, 0x0100, 3, 0x0000, 0, 0),
-	MX6_PAD_DISP0_DAT6__SDMA_DEBUG_RTBUFFER_WRITE	= IOMUX_PAD(0x0414, 0x0100, 4, 0x0000, 0, 0),
-	MX6_PAD_DISP0_DAT6__GPIO_4_27		= IOMUX_PAD(0x0414, 0x0100, 5, 0x0000, 0, 0),
-	MX6_PAD_DISP0_DAT6__MMDC_MMDC_DEBUG_11	= IOMUX_PAD(0x0414, 0x0100, 6, 0x0000, 0, 0),
-	MX6_PAD_DISP0_DAT6__PL301_SIM_MX6DL_PER1_HADDR_17	= IOMUX_PAD(0x0414, 0x0100, 7, 0x0000, 0, 0),
-	MX6_PAD_DISP0_DAT7__IPU1_DISP0_DAT_7	= IOMUX_PAD(0x0418, 0x0104, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
-	MX6_PAD_DISP0_DAT7__LCDIF_DAT_7		= IOMUX_PAD(0x0418, 0x0104, 1, 0x0000, 0, 0),
-	MX6_PAD_DISP0_DAT7__ECSPI3_RDY		= IOMUX_PAD(0x0418, 0x0104, 2, 0x0000, 0, 0),
-	MX6_PAD_DISP0_DAT7__USDHC1_USDHC_DEBUG_5	= IOMUX_PAD(0x0418, 0x0104, 3, 0x0000, 0, 0),
-	MX6_PAD_DISP0_DAT7__SDMA_DEBUG_EVENT_CHANNEL_0	= IOMUX_PAD(0x0418, 0x0104, 4, 0x0000, 0, 0),
-	MX6_PAD_DISP0_DAT7__GPIO_4_28		= IOMUX_PAD(0x0418, 0x0104, 5, 0x0000, 0, 0),
-	MX6_PAD_DISP0_DAT7__MMDC_MMDC_DEBUG_12	= IOMUX_PAD(0x0418, 0x0104, 6, 0x0000, 0, 0),
-	MX6_PAD_DISP0_DAT7__PL301_SIM_MX6DL_PER1_HADDR_18	= IOMUX_PAD(0x0418, 0x0104, 7, 0x0000, 0, 0),
-	MX6_PAD_DISP0_DAT8__IPU1_DISP0_DAT_8	= IOMUX_PAD(0x041C, 0x0108, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
-	MX6_PAD_DISP0_DAT8__LCDIF_DAT_8		= IOMUX_PAD(0x041C, 0x0108, 1, 0x0000, 0, 0),
-	MX6_PAD_DISP0_DAT8__PWM1_PWMO		= IOMUX_PAD(0x041C, 0x0108, 2, 0x0000, 0, 0),
-	MX6_PAD_DISP0_DAT8__WDOG1_WDOG_B	= IOMUX_PAD(0x041C, 0x0108, 3, 0x0000, 0, 0),
-	MX6_PAD_DISP0_DAT8__SDMA_DEBUG_EVENT_CHANNEL_1	= IOMUX_PAD(0x041C, 0x0108, 4, 0x0000, 0, 0),
-	MX6_PAD_DISP0_DAT8__GPIO_4_29		= IOMUX_PAD(0x041C, 0x0108, 5, 0x0000, 0, 0),
-	MX6_PAD_DISP0_DAT8__MMDC_MMDC_DEBUG_13	= IOMUX_PAD(0x041C, 0x0108, 6, 0x0000, 0, 0),
-	MX6_PAD_DISP0_DAT8__PL301_SIM_MX6DL_PER1_HADDR_19	= IOMUX_PAD(0x041C, 0x0108, 7, 0x0000, 0, 0),
-	MX6_PAD_DISP0_DAT9__IPU1_DISP0_DAT_9	= IOMUX_PAD(0x0420, 0x010C, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
-	MX6_PAD_DISP0_DAT9__LCDIF_DAT_9		= IOMUX_PAD(0x0420, 0x010C, 1, 0x0000, 0, 0),
-	MX6_PAD_DISP0_DAT9__PWM2_PWMO		= IOMUX_PAD(0x0420, 0x010C, 2, 0x0000, 0, 0),
-	MX6_PAD_DISP0_DAT9__WDOG2_WDOG_B	= IOMUX_PAD(0x0420, 0x010C, 3, 0x0000, 0, 0),
-	MX6_PAD_DISP0_DAT9__SDMA_DEBUG_EVENT_CHANNEL_2	= IOMUX_PAD(0x0420, 0x010C, 4, 0x0000, 0, 0),
-	MX6_PAD_DISP0_DAT9__GPIO_4_30		= IOMUX_PAD(0x0420, 0x010C, 5, 0x0000, 0, 0),
-	MX6_PAD_DISP0_DAT9__MMDC_MMDC_DEBUG_14	= IOMUX_PAD(0x0420, 0x010C, 6, 0x0000, 0, 0),
-	MX6_PAD_DISP0_DAT9__PL301_SIM_MX6DL_PER1_HADDR_20	= IOMUX_PAD(0x0420, 0x010C, 7, 0x0000, 0, 0),
-	MX6_PAD_DRAM_A0__MMDC_DRAM_A_0		= IOMUX_PAD(0x0424, NO_MUX_I, 0, 0x0000, 0, 0),
-	MX6_PAD_DRAM_A1__MMDC_DRAM_A_1		= IOMUX_PAD(0x0428, NO_MUX_I, 0, 0x0000, 0, 0),
-	MX6_PAD_DRAM_A10__MMDC_DRAM_A_10	= IOMUX_PAD(0x042C, NO_MUX_I, 0, 0x0000, 0, 0),
-	MX6_PAD_DRAM_A11__MMDC_DRAM_A_11	= IOMUX_PAD(0x0430, NO_MUX_I, 0, 0x0000, 0, 0),
-	MX6_PAD_DRAM_A12__MMDC_DRAM_A_12	= IOMUX_PAD(0x0434, NO_MUX_I, 0, 0x0000, 0, 0),
-	MX6_PAD_DRAM_A13__MMDC_DRAM_A_13	= IOMUX_PAD(0x0438, NO_MUX_I, 0, 0x0000, 0, 0),
-	MX6_PAD_DRAM_A14__MMDC_DRAM_A_14	= IOMUX_PAD(0x043C, NO_MUX_I, 0, 0x0000, 0, 0),
-	MX6_PAD_DRAM_A15__MMDC_DRAM_A_15	= IOMUX_PAD(0x0440, NO_MUX_I, 0, 0x0000, 0, 0),
-	MX6_PAD_DRAM_A2__MMDC_DRAM_A_2		= IOMUX_PAD(0x0444, NO_MUX_I, 0, 0x0000, 0, 0),
-	MX6_PAD_DRAM_A3__MMDC_DRAM_A_3		= IOMUX_PAD(0x0448, NO_MUX_I, 0, 0x0000, 0, 0),
-	MX6_PAD_DRAM_A4__MMDC_DRAM_A_4		= IOMUX_PAD(0x044C, NO_MUX_I, 0, 0x0000, 0, 0),
-	MX6_PAD_DRAM_A5__MMDC_DRAM_A_5		= IOMUX_PAD(0x0450, NO_MUX_I, 0, 0x0000, 0, 0),
-	MX6_PAD_DRAM_A6__MMDC_DRAM_A_6		= IOMUX_PAD(0x0454, NO_MUX_I, 0, 0x0000, 0, 0),
-	MX6_PAD_DRAM_A7__MMDC_DRAM_A_7		= IOMUX_PAD(0x0458, NO_MUX_I, 0, 0x0000, 0, 0),
-	MX6_PAD_DRAM_A8__MMDC_DRAM_A_8		= IOMUX_PAD(0x045C, NO_MUX_I, 0, 0x0000, 0, 0),
-	MX6_PAD_DRAM_A9__MMDC_DRAM_A_9		= IOMUX_PAD(0x0460, NO_MUX_I, 0, 0x0000, 0, 0),
-	MX6_PAD_DRAM_CAS__MMDC_DRAM_CAS		= IOMUX_PAD(0x0464, NO_MUX_I, 0, 0x0000, 0, 0),
-	MX6_PAD_DRAM_CS0__MMDC_DRAM_CS_0	= IOMUX_PAD(0x0468, NO_MUX_I, 0, 0x0000, 0, 0),
-	MX6_PAD_DRAM_CS1__MMDC_DRAM_CS_1	= IOMUX_PAD(0x046C, NO_MUX_I, 0, 0x0000, 0, 0),
-	MX6_PAD_DRAM_D0__MMDC_DRAM_D_0		= IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
-	MX6_PAD_DRAM_D1__MMDC_DRAM_D_1		= IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
-	MX6_PAD_DRAM_D10__MMDC_DRAM_D_10	= IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
-	MX6_PAD_DRAM_D11__MMDC_DRAM_D_11	= IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
-	MX6_PAD_DRAM_D12__MMDC_DRAM_D_12	= IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
-	MX6_PAD_DRAM_D13__MMDC_DRAM_D_13	= IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
-	MX6_PAD_DRAM_D14__MMDC_DRAM_D_14	= IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
-	MX6_PAD_DRAM_D15__MMDC_DRAM_D_15	= IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
-	MX6_PAD_DRAM_D16__MMDC_DRAM_D_16	= IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
-	MX6_PAD_DRAM_D17__MMDC_DRAM_D_17	= IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
-	MX6_PAD_DRAM_D18__MMDC_DRAM_D_18	= IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
-	MX6_PAD_DRAM_D19__MMDC_DRAM_D_19	= IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
-	MX6_PAD_DRAM_D2__MMDC_DRAM_D_2		= IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
-	MX6_PAD_DRAM_D20__MMDC_DRAM_D_20	= IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
-	MX6_PAD_DRAM_D21__MMDC_DRAM_D_21	= IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
-	MX6_PAD_DRAM_D22__MMDC_DRAM_D_22	= IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
-	MX6_PAD_DRAM_D23__MMDC_DRAM_D_23	= IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
-	MX6_PAD_DRAM_D24__MMDC_DRAM_D_24	= IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
-	MX6_PAD_DRAM_D25__MMDC_DRAM_D_25	= IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
-	MX6_PAD_DRAM_D26__MMDC_DRAM_D_26	= IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
-	MX6_PAD_DRAM_D27__MMDC_DRAM_D_27	= IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
-	MX6_PAD_DRAM_D28__MMDC_DRAM_D_28	= IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
-	MX6_PAD_DRAM_D29__MMDC_DRAM_D_29	= IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
-	MX6_PAD_DRAM_D3__MMDC_DRAM_D_3		= IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
-	MX6_PAD_DRAM_D30__MMDC_DRAM_D_30	= IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
-	MX6_PAD_DRAM_D31__MMDC_DRAM_D_31	= IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
-	MX6_PAD_DRAM_D32__MMDC_DRAM_D_32	= IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
-	MX6_PAD_DRAM_D33__MMDC_DRAM_D_33	= IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
-	MX6_PAD_DRAM_D34__MMDC_DRAM_D_34	= IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
-	MX6_PAD_DRAM_D35__MMDC_DRAM_D_35	= IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
-	MX6_PAD_DRAM_D36__MMDC_DRAM_D_36	= IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
-	MX6_PAD_DRAM_D37__MMDC_DRAM_D_37	= IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
-	MX6_PAD_DRAM_D38__MMDC_DRAM_D_38	= IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
-	MX6_PAD_DRAM_D39__MMDC_DRAM_D_39	= IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
-	MX6_PAD_DRAM_D4__MMDC_DRAM_D_4		= IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
-	MX6_PAD_DRAM_D40__MMDC_DRAM_D_40	= IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
-	MX6_PAD_DRAM_D41__MMDC_DRAM_D_41	= IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
-	MX6_PAD_DRAM_D42__MMDC_DRAM_D_42	= IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
-	MX6_PAD_DRAM_D43__MMDC_DRAM_D_43	= IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
-	MX6_PAD_DRAM_D44__MMDC_DRAM_D_44	= IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
-	MX6_PAD_DRAM_D45__MMDC_DRAM_D_45	= IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
-	MX6_PAD_DRAM_D46__MMDC_DRAM_D_46	= IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
-	MX6_PAD_DRAM_D47__MMDC_DRAM_D_47	= IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
-	MX6_PAD_DRAM_D48__MMDC_DRAM_D_48	= IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
-	MX6_PAD_DRAM_D49__MMDC_DRAM_D_49	= IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
-	MX6_PAD_DRAM_D5__MMDC_DRAM_D_5		= IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
-	MX6_PAD_DRAM_D50__MMDC_DRAM_D_50	= IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
-	MX6_PAD_DRAM_D51__MMDC_DRAM_D_51	= IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
-	MX6_PAD_DRAM_D52__MMDC_DRAM_D_52	= IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
-	MX6_PAD_DRAM_D53__MMDC_DRAM_D_53	= IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
-	MX6_PAD_DRAM_D54__MMDC_DRAM_D_54	= IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
-	MX6_PAD_DRAM_D55__MMDC_DRAM_D_55	= IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
-	MX6_PAD_DRAM_D56__MMDC_DRAM_D_56	= IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
-	MX6_PAD_DRAM_D57__MMDC_DRAM_D_57	= IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
-	MX6_PAD_DRAM_D58__MMDC_DRAM_D_58	= IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
-	MX6_PAD_DRAM_D59__MMDC_DRAM_D_59	= IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
-	MX6_PAD_DRAM_D6__MMDC_DRAM_D_6		= IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
-	MX6_PAD_DRAM_D60__MMDC_DRAM_D_60	= IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
-	MX6_PAD_DRAM_D61__MMDC_DRAM_D_61	= IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
-	MX6_PAD_DRAM_D62__MMDC_DRAM_D_62	= IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
-	MX6_PAD_DRAM_D63__MMDC_DRAM_D_63	= IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
-	MX6_PAD_DRAM_D7__MMDC_DRAM_D_7		= IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
-	MX6_PAD_DRAM_D8__MMDC_DRAM_D_8		= IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
-	MX6_PAD_DRAM_D9__MMDC_DRAM_D_9		= IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
-	MX6_PAD_DRAM_DQM0__MMDC_DRAM_DQM_0	= IOMUX_PAD(0x0470, NO_MUX_I, 0, 0x0000, 0, 0),
-	MX6_PAD_DRAM_DQM1__MMDC_DRAM_DQM_1	= IOMUX_PAD(0x0474, NO_MUX_I, 0, 0x0000, 0, 0),
-	MX6_PAD_DRAM_DQM2__MMDC_DRAM_DQM_2	= IOMUX_PAD(0x0478, NO_MUX_I, 0, 0x0000, 0, 0),
-	MX6_PAD_DRAM_DQM3__MMDC_DRAM_DQM_3	= IOMUX_PAD(0x047C, NO_MUX_I, 0, 0x0000, 0, 0),
-	MX6_PAD_DRAM_DQM4__MMDC_DRAM_DQM_4	= IOMUX_PAD(0x0480, NO_MUX_I, 0, 0x0000, 0, 0),
-	MX6_PAD_DRAM_DQM5__MMDC_DRAM_DQM_5	= IOMUX_PAD(0x0484, NO_MUX_I, 0, 0x0000, 0, 0),
-	MX6_PAD_DRAM_DQM6__MMDC_DRAM_DQM_6	= IOMUX_PAD(0x0488, NO_MUX_I, 0, 0x0000, 0, 0),
-	MX6_PAD_DRAM_DQM7__MMDC_DRAM_DQM_7	= IOMUX_PAD(0x048C, NO_MUX_I, 0, 0x0000, 0, 0),
-	MX6_PAD_DRAM_RAS__MMDC_DRAM_RAS		= IOMUX_PAD(0x0490, NO_MUX_I, 0, 0x0000, 0, 0),
-	MX6_PAD_DRAM_RESET__MMDC_DRAM_RESET	= IOMUX_PAD(0x0494, NO_MUX_I, 0, 0x0000, 0, 0),
-	MX6_PAD_DRAM_SDBA0__MMDC_DRAM_SDBA_0	= IOMUX_PAD(0x0498, NO_MUX_I, 0, 0x0000, 0, 0),
-	MX6_PAD_DRAM_SDBA1__MMDC_DRAM_SDBA_1	= IOMUX_PAD(0x049C, NO_MUX_I, 0, 0x0000, 0, 0),
-	MX6_PAD_DRAM_SDBA2__MMDC_DRAM_SDBA_2	= IOMUX_PAD(0x04A0, NO_MUX_I, 0, 0x0000, 0, 0),
-	MX6_PAD_DRAM_SDCKE0__MMDC_DRAM_SDCKE_0	= IOMUX_PAD(0x04A4, NO_MUX_I, 0, 0x0000, 0, 0),
-	MX6_PAD_DRAM_SDCKE1__MMDC_DRAM_SDCKE_1	= IOMUX_PAD(0x04A8, NO_MUX_I, 0, 0x0000, 0, 0),
-	MX6_PAD_DRAM_SDCLK_0__MMDC_DRAM_SDCLK0	= IOMUX_PAD(0x04AC, NO_MUX_I, 0, 0x0000, 0, 0),
-	MX6_PAD_DRAM_SDCLK_1__MMDC_DRAM_SDCLK1	= IOMUX_PAD(0x04B0, NO_MUX_I, 0, 0x0000, 0, 0),
-	MX6_PAD_DRAM_SDODT0__MMDC_DRAM_ODT_0	= IOMUX_PAD(0x04B4, NO_MUX_I, 0, 0x0000, 0, 0),
-	MX6_PAD_DRAM_SDODT1__MMDC_DRAM_ODT_1	= IOMUX_PAD(0x04B8, NO_MUX_I, 0, 0x0000, 0, 0),
-	MX6_PAD_DRAM_SDQS0__MMDC_DRAM_SDQS_0	= IOMUX_PAD(0x04BC, NO_MUX_I, 0, 0x0000, 0, 0),
-	MX6_PAD_DRAM_SDQS1__MMDC_DRAM_SDQS_1	= IOMUX_PAD(0x04C0, NO_MUX_I, 0, 0x0000, 0, 0),
-	MX6_PAD_DRAM_SDQS2__MMDC_DRAM_SDQS_2	= IOMUX_PAD(0x04C4, NO_MUX_I, 0, 0x0000, 0, 0),
-	MX6_PAD_DRAM_SDQS3__MMDC_DRAM_SDQS_3	= IOMUX_PAD(0x04C8, NO_MUX_I, 0, 0x0000, 0, 0),
-	MX6_PAD_DRAM_SDQS4__MMDC_DRAM_SDQS_4	= IOMUX_PAD(0x04CC, NO_MUX_I, 0, 0x0000, 0, 0),
-	MX6_PAD_DRAM_SDQS5__MMDC_DRAM_SDQS_5	= IOMUX_PAD(0x04D0, NO_MUX_I, 0, 0x0000, 0, 0),
-	MX6_PAD_DRAM_SDQS6__MMDC_DRAM_SDQS_6	= IOMUX_PAD(0x04D4, NO_MUX_I, 0, 0x0000, 0, 0),
-	MX6_PAD_DRAM_SDQS7__MMDC_DRAM_SDQS_7	= IOMUX_PAD(0x04D8, NO_MUX_I, 0, 0x0000, 0, 0),
-	MX6_PAD_DRAM_SDWE__MMDC_DRAM_SDWE	= IOMUX_PAD(0x04DC, NO_MUX_I, 0, 0x0000, 0, 0),
-	MX6_PAD_EIM_A16__WEIM_WEIM_A_16		= IOMUX_PAD(0x04E0, 0x0110, 0, 0x0000, 0, 0),
-	MX6_PAD_EIM_A16__IPU1_DI1_DISP_CLK	= IOMUX_PAD(0x04E0, 0x0110, 1, 0x0000, 0, 0),
-	MX6_PAD_EIM_A16__IPU1_CSI1_PIXCLK	= IOMUX_PAD(0x04E0, 0x0110, 2, 0x08B8, 0, 0),
-	MX6_PAD_EIM_A16__MIPI_CORE_DPHY_TEST_OUT_23	= IOMUX_PAD(0x04E0, 0x0110, 4, 0x0000, 0, 0),
-	MX6_PAD_EIM_A16__GPIO_2_22		= IOMUX_PAD(0x04E0, 0x0110, 5, 0x0000, 0, 0),
-	MX6_PAD_EIM_A16__TPSMP_HDATA_6		= IOMUX_PAD(0x04E0, 0x0110, 6, 0x0000, 0, 0),
-	MX6_PAD_EIM_A16__SRC_BT_CFG_16		= IOMUX_PAD(0x04E0, 0x0110, 7, 0x0000, 0, 0),
-	MX6_PAD_EIM_A16__EPDC_SDDO_0		= IOMUX_PAD(0x04E0, 0x0110, 8, 0x0000, 0, 0),
-	MX6_PAD_EIM_A17__WEIM_WEIM_A_17		= IOMUX_PAD(0x04E4, 0x0114, 0, 0x0000, 0, 0),
-	MX6_PAD_EIM_A17__IPU1_DISP1_DAT_12	= IOMUX_PAD(0x04E4, 0x0114, 1, 0x0000, 0, 0),
-	MX6_PAD_EIM_A17__IPU1_CSI1_D_12		= IOMUX_PAD(0x04E4, 0x0114, 2, 0x0890, 0, 0),
-	MX6_PAD_EIM_A17__MIPI_CORE_DPHY_TEST_OUT_22	= IOMUX_PAD(0x04E4, 0x0114, 4, 0x0000, 0, 0),
-	MX6_PAD_EIM_A17__GPIO_2_21		= IOMUX_PAD(0x04E4, 0x0114, 5, 0x0000, 0, 0),
-	MX6_PAD_EIM_A17__TPSMP_HDATA_5		= IOMUX_PAD(0x04E4, 0x0114, 6, 0x0000, 0, 0),
-	MX6_PAD_EIM_A17__SRC_BT_CFG_17		= IOMUX_PAD(0x04E4, 0x0114, 7, 0x0000, 0, 0),
-	MX6_PAD_EIM_A17__EPDC_PWRSTAT		= IOMUX_PAD(0x04E4, 0x0114, 8, 0x0000, 0, 0),
-	MX6_PAD_EIM_A18__WEIM_WEIM_A_18		= IOMUX_PAD(0x04E8, 0x0118, 0, 0x0000, 0, 0),
-	MX6_PAD_EIM_A18__IPU1_DISP1_DAT_13	= IOMUX_PAD(0x04E8, 0x0118, 1, 0x0000, 0, 0),
-	MX6_PAD_EIM_A18__IPU1_CSI1_D_13		= IOMUX_PAD(0x04E8, 0x0118, 2, 0x0894, 0, 0),
-	MX6_PAD_EIM_A18__MIPI_CORE_DPHY_TEST_OUT_21	= IOMUX_PAD(0x04E8, 0x0118, 4, 0x0000, 0, 0),
-	MX6_PAD_EIM_A18__GPIO_2_20		= IOMUX_PAD(0x04E8, 0x0118, 5, 0x0000, 0, 0),
-	MX6_PAD_EIM_A18__TPSMP_HDATA_4		= IOMUX_PAD(0x04E8, 0x0118, 6, 0x0000, 0, 0),
-	MX6_PAD_EIM_A18__SRC_BT_CFG_18		= IOMUX_PAD(0x04E8, 0x0118, 7, 0x0000, 0, 0),
-	MX6_PAD_EIM_A18__EPDC_PWRCTRL_0		= IOMUX_PAD(0x04E8, 0x0118, 8, 0x0000, 0, 0),
-	MX6_PAD_EIM_A19__WEIM_WEIM_A_19		= IOMUX_PAD(0x04EC, 0x011C, 0, 0x0000, 0, 0),
-	MX6_PAD_EIM_A19__IPU1_DISP1_DAT_14	= IOMUX_PAD(0x04EC, 0x011C, 1, 0x0000, 0, 0),
-	MX6_PAD_EIM_A19__IPU1_CSI1_D_14		= IOMUX_PAD(0x04EC, 0x011C, 2, 0x0898, 0, 0),
-	MX6_PAD_EIM_A19__MIPI_CORE_DPHY_TEST_OUT_20	= IOMUX_PAD(0x04EC, 0x011C, 4, 0x0000, 0, 0),
-	MX6_PAD_EIM_A19__GPIO_2_19		= IOMUX_PAD(0x04EC, 0x011C, 5, 0x0000, 0, 0),
-	MX6_PAD_EIM_A19__TPSMP_HDATA_3		= IOMUX_PAD(0x04EC, 0x011C, 6, 0x0000, 0, 0),
-	MX6_PAD_EIM_A19__SRC_BT_CFG_19		= IOMUX_PAD(0x04EC, 0x011C, 7, 0x0000, 0, 0),
-	MX6_PAD_EIM_A19__EPDC_PWRCTRL_1		= IOMUX_PAD(0x04EC, 0x011C, 8, 0x0000, 0, 0),
-	MX6_PAD_EIM_A20__WEIM_WEIM_A_20		= IOMUX_PAD(0x04F0, 0x0120, 0, 0x0000, 0, 0),
-	MX6_PAD_EIM_A20__IPU1_DISP1_DAT_15	= IOMUX_PAD(0x04F0, 0x0120, 1, 0x0000, 0, 0),
-	MX6_PAD_EIM_A20__IPU1_CSI1_D_15		= IOMUX_PAD(0x04F0, 0x0120, 2, 0x089C, 0, 0),
-	MX6_PAD_EIM_A20__MIPI_CORE_DPHY_TEST_OUT_19	= IOMUX_PAD(0x04F0, 0x0120, 4, 0x0000, 0, 0),
-	MX6_PAD_EIM_A20__GPIO_2_18		= IOMUX_PAD(0x04F0, 0x0120, 5, 0x0000, 0, 0),
-	MX6_PAD_EIM_A20__TPSMP_HDATA_2		= IOMUX_PAD(0x04F0, 0x0120, 6, 0x0000, 0, 0),
-	MX6_PAD_EIM_A20__SRC_BT_CFG_20		= IOMUX_PAD(0x04F0, 0x0120, 7, 0x0000, 0, 0),
-	MX6_PAD_EIM_A20__EPDC_PWRCTRL_2		= IOMUX_PAD(0x04F0, 0x0120, 8, 0x0000, 0, 0),
-	MX6_PAD_EIM_A21__WEIM_WEIM_A_21		= IOMUX_PAD(0x04F4, 0x0124, 0, 0x0000, 0, 0),
-	MX6_PAD_EIM_A21__IPU1_DISP1_DAT_16	= IOMUX_PAD(0x04F4, 0x0124, 1, 0x0000, 0, 0),
-	MX6_PAD_EIM_A21__IPU1_CSI1_D_16		= IOMUX_PAD(0x04F4, 0x0124, 2, 0x08A0, 0, 0),
-	MX6_PAD_EIM_A21__MIPI_CORE_DPHY_TEST_OUT_18	= IOMUX_PAD(0x04F4, 0x0124, 4, 0x0000, 0, 0),
-	MX6_PAD_EIM_A21__GPIO_2_17		= IOMUX_PAD(0x04F4, 0x0124, 5, 0x0000, 0, 0),
-	MX6_PAD_EIM_A21__TPSMP_HDATA_1		= IOMUX_PAD(0x04F4, 0x0124, 6, 0x0000, 0, 0),
-	MX6_PAD_EIM_A21__SRC_BT_CFG_21		= IOMUX_PAD(0x04F4, 0x0124, 7, 0x0000, 0, 0),
-	MX6_PAD_EIM_A21__EPDC_GDCLK		= IOMUX_PAD(0x04F4, 0x0124, 8, 0x0000, 0, 0),
-	MX6_PAD_EIM_A22__WEIM_WEIM_A_22		= IOMUX_PAD(0x04F8, 0x0128, 0, 0x0000, 0, 0),
-	MX6_PAD_EIM_A22__IPU1_DISP1_DAT_17	= IOMUX_PAD(0x04F8, 0x0128, 1, 0x0000, 0, 0),
-	MX6_PAD_EIM_A22__IPU1_CSI1_D_17		= IOMUX_PAD(0x04F8, 0x0128, 2, 0x08A4, 0, 0),
-	MX6_PAD_EIM_A22__GPIO_2_16		= IOMUX_PAD(0x04F8, 0x0128, 5, 0x0000, 0, 0),
-	MX6_PAD_EIM_A22__TPSMP_HDATA_0		= IOMUX_PAD(0x04F8, 0x0128, 6, 0x0000, 0, 0),
-	MX6_PAD_EIM_A22__SRC_BT_CFG_22		= IOMUX_PAD(0x04F8, 0x0128, 7, 0x0000, 0, 0),
-	MX6_PAD_EIM_A22__EPDC_GDSP		= IOMUX_PAD(0x04F8, 0x0128, 8, 0x0000, 0, 0),
-	MX6_PAD_EIM_A23__WEIM_WEIM_A_23		= IOMUX_PAD(0x04FC, 0x012C, 0, 0x0000, 0, 0),
-	MX6_PAD_EIM_A23__IPU1_DISP1_DAT_18	= IOMUX_PAD(0x04FC, 0x012C, 1, 0x0000, 0, 0),
-	MX6_PAD_EIM_A23__IPU1_CSI1_D_18		= IOMUX_PAD(0x04FC, 0x012C, 2, 0x08A8, 0, 0),
-	MX6_PAD_EIM_A23__IPU1_SISG_3		= IOMUX_PAD(0x04FC, 0x012C, 4, 0x0000, 0, 0),
-	MX6_PAD_EIM_A23__GPIO_6_6		= IOMUX_PAD(0x04FC, 0x012C, 5, 0x0000, 0, 0),
-	MX6_PAD_EIM_A23__PL301_SIM_MX6DL_PER1_HPROT_3	= IOMUX_PAD(0x04FC, 0x012C, 6, 0x0000, 0, 0),
-	MX6_PAD_EIM_A23__SRC_BT_CFG_23		= IOMUX_PAD(0x04FC, 0x012C, 7, 0x0000, 0, 0),
-	MX6_PAD_EIM_A23__EPDC_GDOE		= IOMUX_PAD(0x04FC, 0x012C, 8, 0x0000, 0, 0),
-	MX6_PAD_EIM_A24__WEIM_WEIM_A_24		= IOMUX_PAD(0x0500, 0x0130, 0, 0x0000, 0, 0),
-	MX6_PAD_EIM_A24__IPU1_DISP1_DAT_19	= IOMUX_PAD(0x0500, 0x0130, 1, 0x0000, 0, 0),
-	MX6_PAD_EIM_A24__IPU1_CSI1_D_19		= IOMUX_PAD(0x0500, 0x0130, 2, 0x08AC, 0, 0),
-	MX6_PAD_EIM_A24__IPU1_SISG_2		= IOMUX_PAD(0x0500, 0x0130, 4, 0x0000, 0, 0),
-	MX6_PAD_EIM_A24__GPIO_5_4		= IOMUX_PAD(0x0500, 0x0130, 5, 0x0000, 0, 0),
-	MX6_PAD_EIM_A24__PL301_SIM_MX6DL_PER1_HPROT_2	= IOMUX_PAD(0x0500, 0x0130, 6, 0x0000, 0, 0),
-	MX6_PAD_EIM_A24__SRC_BT_CFG_24		= IOMUX_PAD(0x0500, 0x0130, 7, 0x0000, 0, 0),
-	MX6_PAD_EIM_A24__EPDC_GDRL		= IOMUX_PAD(0x0500, 0x0130, 8, 0x0000, 0, 0),
-	MX6_PAD_EIM_A25__WEIM_WEIM_A_25		= IOMUX_PAD(0x0504, 0x0134, 0, 0x0000, 0, 0),
-	MX6_PAD_EIM_A25__ECSPI4_SS1		= IOMUX_PAD(0x0504, 0x0134, 1, 0x0000, 0, 0),
-	MX6_PAD_EIM_A25__ECSPI2_RDY		= IOMUX_PAD(0x0504, 0x0134, 2, 0x0000, 0, 0),
-	MX6_PAD_EIM_A25__IPU1_DI1_PIN12		= IOMUX_PAD(0x0504, 0x0134, 3, 0x0000, 0, 0),
-	MX6_PAD_EIM_A25__IPU1_DI0_D1_CS		= IOMUX_PAD(0x0504, 0x0134, 4, 0x0000, 0, 0),
-	MX6_PAD_EIM_A25__GPIO_5_2		= IOMUX_PAD(0x0504, 0x0134, 5, 0x0000, 0, 0),
-	MX6_PAD_EIM_A25__HDMI_TX_CEC_LINE	= IOMUX_PAD(0x0504, 0x0134, 6, 0x085C, 0, 0),
-	MX6_PAD_EIM_A25__PL301_SIM_MX6DL_PER1_HBURST_0	= IOMUX_PAD(0x0504, 0x0134, 7, 0x0000, 0, 0),
-	MX6_PAD_EIM_A25__EPDC_SDDO_15		= IOMUX_PAD(0x0504, 0x0134, 8, 0x0000, 0, 0),
-	MX6_PAD_EIM_A25__WEIM_ACLK_FREERUN	= IOMUX_PAD(0x0504, 0x0134, 9, 0x0000, 0, 0),
-	MX6_PAD_EIM_BCLK__WEIM_WEIM_BCLK	= IOMUX_PAD(0x0508, 0x0138, 0, 0x0000, 0, 0),
-	MX6_PAD_EIM_BCLK__IPU1_DI1_PIN16	= IOMUX_PAD(0x0508, 0x0138, 1, 0x0000, 0, 0),
-	MX6_PAD_EIM_BCLK__GPIO_6_31		= IOMUX_PAD(0x0508, 0x0138, 5, 0x0000, 0, 0),
-	MX6_PAD_EIM_BCLK__TPSMP_HDATA_31	= IOMUX_PAD(0x0508, 0x0138, 6, 0x0000, 0, 0),
-	MX6_PAD_EIM_BCLK__EPDC_SDCE_9		= IOMUX_PAD(0x0508, 0x0138, 8, 0x0000, 0, 0),
-	MX6_PAD_EIM_CS0__WEIM_WEIM_CS_0		= IOMUX_PAD(0x050C, 0x013C, 0, 0x0000, 0, 0),
-	MX6_PAD_EIM_CS0__IPU1_DI1_PIN5		= IOMUX_PAD(0x050C, 0x013C, 1, 0x0000, 0, 0),
-	MX6_PAD_EIM_CS0__ECSPI2_SCLK		= IOMUX_PAD(0x050C, 0x013C, 2, 0x07F4, 2, 0),
-	MX6_PAD_EIM_CS0__MIPI_CORE_DPHY_TEST_OUT_24	= IOMUX_PAD(0x050C, 0x013C, 4, 0x0000, 0, 0),
-	MX6_PAD_EIM_CS0__GPIO_2_23		= IOMUX_PAD(0x050C, 0x013C, 5, 0x0000, 0, 0),
-	MX6_PAD_EIM_CS0__TPSMP_HDATA_7		= IOMUX_PAD(0x050C, 0x013C, 6, 0x0000, 0, 0),
-	MX6_PAD_EIM_CS0__EPDC_SDDO_6		= IOMUX_PAD(0x050C, 0x013C, 8, 0x0000, 0, 0),
-	MX6_PAD_EIM_CS1__WEIM_WEIM_CS_1		= IOMUX_PAD(0x0510, 0x0140, 0, 0x0000, 0, 0),
-	MX6_PAD_EIM_CS1__IPU1_DI1_PIN6		= IOMUX_PAD(0x0510, 0x0140, 1, 0x0000, 0, 0),
-	MX6_PAD_EIM_CS1__ECSPI2_MOSI		= IOMUX_PAD(0x0510, 0x0140, 2, 0x07FC, 2, 0),
-	MX6_PAD_EIM_CS1__MIPI_CORE_DPHY_TEST_OUT_25	= IOMUX_PAD(0x0510, 0x0140, 4, 0x0000, 0, 0),
-	MX6_PAD_EIM_CS1__GPIO_2_24		= IOMUX_PAD(0x0510, 0x0140, 5, 0x0000, 0, 0),
-	MX6_PAD_EIM_CS1__TPSMP_HDATA_8		= IOMUX_PAD(0x0510, 0x0140, 6, 0x0000, 0, 0),
-	MX6_PAD_EIM_CS1__EPDC_SDDO_8		= IOMUX_PAD(0x0510, 0x0140, 8, 0x0000, 0, 0),
-	MX6_PAD_EIM_D16__WEIM_WEIM_D_16		= IOMUX_PAD(0x0514, 0x0144, 0, 0x0000, 0, 0),
-	MX6_PAD_EIM_D16__ECSPI1_SCLK		= IOMUX_PAD(0x0514, 0x0144, 1, 0x07D8, 2, 0),
-	MX6_PAD_EIM_D16__IPU1_DI0_PIN5		= IOMUX_PAD(0x0514, 0x0144, 2, 0x0000, 0, 0),
-	MX6_PAD_EIM_D16__IPU1_CSI1_D_18		= IOMUX_PAD(0x0514, 0x0144, 3, 0x08A8, 1, 0),
-	MX6_PAD_EIM_D16__HDMI_TX_DDC_SDA	= IOMUX_PAD(0x0514, 0x0144, 4, 0x0864, 0, 0),
-	MX6_PAD_EIM_D16__GPIO_3_16		= IOMUX_PAD(0x0514, 0x0144, 5, 0x0000, 0, 0),
-	MX6_PAD_EIM_D16__I2C2_SDA		= IOMUX_PAD(0x0514, 0x0144, 6 | IOMUX_CONFIG_SION, 0x0874, 0, 0),
-	MX6_PAD_EIM_D16__TPSMP_HTRANS_0		= IOMUX_PAD(0x0514, 0x0144, 7, 0x0000, 0, 0),
-	MX6_PAD_EIM_D16__EPDC_SDDO_10		= IOMUX_PAD(0x0514, 0x0144, 8, 0x0000, 0, 0),
-	MX6_PAD_EIM_D17__WEIM_WEIM_D_17		= IOMUX_PAD(0x0518, 0x0148, 0, 0x0000, 0, 0),
-	MX6_PAD_EIM_D17__ECSPI1_MISO		= IOMUX_PAD(0x0518, 0x0148, 1, 0x07DC, 2, 0),
-	MX6_PAD_EIM_D17__IPU1_DI0_PIN6		= IOMUX_PAD(0x0518, 0x0148, 2, 0x0000, 0, 0),
-	MX6_PAD_EIM_D17__IPU1_CSI1_PIXCLK	= IOMUX_PAD(0x0518, 0x0148, 3, 0x08B8, 1, 0),
-	MX6_PAD_EIM_D17__DCIC1_DCIC_OUT		= IOMUX_PAD(0x0518, 0x0148, 4, 0x0000, 0, 0),
-	MX6_PAD_EIM_D17__GPIO_3_17		= IOMUX_PAD(0x0518, 0x0148, 5, 0x0000, 0, 0),
-	MX6_PAD_EIM_D17__I2C3_SCL		= IOMUX_PAD(0x0518, 0x0148, 6 | IOMUX_CONFIG_SION, 0x0878, 0, 0),
-	MX6_PAD_EIM_D17__PL301_SIM_MX6DL_PER1_HBURST_1	= IOMUX_PAD(0x0518, 0x0148, 7, 0x0000, 0, 0),
-	MX6_PAD_EIM_D17__EPDC_VCOM_0		= IOMUX_PAD(0x0518, 0x0148, 8, 0x0000, 0, 0),
-	MX6_PAD_EIM_D18__WEIM_WEIM_D_18		= IOMUX_PAD(0x051C, 0x014C, 0, 0x0000, 0, 0),
-	MX6_PAD_EIM_D18__ECSPI1_MOSI		= IOMUX_PAD(0x051C, 0x014C, 1, 0x07E0, 2, 0),
-	MX6_PAD_EIM_D18__IPU1_DI0_PIN7		= IOMUX_PAD(0x051C, 0x014C, 2, 0x0000, 0, 0),
-	MX6_PAD_EIM_D18__IPU1_CSI1_D_17		= IOMUX_PAD(0x051C, 0x014C, 3, 0x08A4, 1, 0),
-	MX6_PAD_EIM_D18__IPU1_DI1_D0_CS		= IOMUX_PAD(0x051C, 0x014C, 4, 0x0000, 0, 0),
-	MX6_PAD_EIM_D18__GPIO_3_18		= IOMUX_PAD(0x051C, 0x014C, 5, 0x0000, 0, 0),
-	MX6_PAD_EIM_D18__I2C3_SDA		= IOMUX_PAD(0x051C, 0x014C, 6 | IOMUX_CONFIG_SION, 0x087C, 0, 0),
-	MX6_PAD_EIM_D18__PL301_SIM_MX6DL_PER1_HBURST_2	= IOMUX_PAD(0x051C, 0x014C, 7, 0x0000, 0, 0),
-	MX6_PAD_EIM_D18__EPDC_VCOM_1		= IOMUX_PAD(0x051C, 0x014C, 8, 0x0000, 0, 0),
-	MX6_PAD_EIM_D19__WEIM_WEIM_D_19		= IOMUX_PAD(0x0520, 0x0150, 0, 0x0000, 0, 0),
-	MX6_PAD_EIM_D19__ECSPI1_SS1		= IOMUX_PAD(0x0520, 0x0150, 1, 0x07E8, 1, 0),
-	MX6_PAD_EIM_D19__IPU1_DI0_PIN8		= IOMUX_PAD(0x0520, 0x0150, 2, 0x0000, 0, 0),
-	MX6_PAD_EIM_D19__IPU1_CSI1_D_16		= IOMUX_PAD(0x0520, 0x0150, 3, 0x08A0, 1, 0),
-	MX6_PAD_EIM_D19__UART1_CTS		= IOMUX_PAD(0x0520, 0x0150, 4, 0x0000, 0, 0),
-	MX6_PAD_EIM_D19__UART1_RTS		= IOMUX_PAD(0x0520, 0x0150, 4, 0x08F8, 0, 0),
-	MX6_PAD_EIM_D19__GPIO_3_19		= IOMUX_PAD(0x0520, 0x0150, 5, 0x0000, 0, 0),
-	MX6_PAD_EIM_D19__EPIT1_EPITO		= IOMUX_PAD(0x0520, 0x0150, 6, 0x0000, 0, 0),
-	MX6_PAD_EIM_D19__PL301_SIM_MX6DL_PER1_HRESP	= IOMUX_PAD(0x0520, 0x0150, 7, 0x0000, 0, 0),
-	MX6_PAD_EIM_D19__EPDC_SDDO_12		= IOMUX_PAD(0x0520, 0x0150, 8, 0x0000, 0, 0),
-	MX6_PAD_EIM_D20__WEIM_WEIM_D_20		= IOMUX_PAD(0x0524, 0x0154, 0, 0x0000, 0, 0),
-	MX6_PAD_EIM_D20__ECSPI4_SS0		= IOMUX_PAD(0x0524, 0x0154, 1, 0x0808, 0, 0),
-	MX6_PAD_EIM_D20__IPU1_DI0_PIN16		= IOMUX_PAD(0x0524, 0x0154, 2, 0x0000, 0, 0),
-	MX6_PAD_EIM_D20__IPU1_CSI1_D_15		= IOMUX_PAD(0x0524, 0x0154, 3, 0x089C, 1, 0),
-	MX6_PAD_EIM_D20__UART1_CTS		= IOMUX_PAD(0x0524, 0x0154, 4, 0x0000, 0, 0),
-	MX6_PAD_EIM_D20__UART1_RTS		= IOMUX_PAD(0x0524, 0x0154, 4, 0x08F8, 1, 0),
-	MX6_PAD_EIM_D20__GPIO_3_20		= IOMUX_PAD(0x0524, 0x0154, 5, 0x0000, 0, 0),
-	MX6_PAD_EIM_D20__EPIT2_EPITO		= IOMUX_PAD(0x0524, 0x0154, 6, 0x0000, 0, 0),
-	MX6_PAD_EIM_D20__TPSMP_HTRANS_1		= IOMUX_PAD(0x0524, 0x0154, 7, 0x0000, 0, 0),
-	MX6_PAD_EIM_D21__WEIM_WEIM_D_21		= IOMUX_PAD(0x0528, 0x0158, 0, 0x0000, 0, 0),
-	MX6_PAD_EIM_D21__ECSPI4_SCLK		= IOMUX_PAD(0x0528, 0x0158, 1, 0x0000, 0, 0),
-	MX6_PAD_EIM_D21__IPU1_DI0_PIN17		= IOMUX_PAD(0x0528, 0x0158, 2, 0x0000, 0, 0),
-	MX6_PAD_EIM_D21__IPU1_CSI1_D_11		= IOMUX_PAD(0x0528, 0x0158, 3, 0x088C, 0, 0),
-	MX6_PAD_EIM_D21__USBOH3_USBOTG_OC	= IOMUX_PAD(0x0528, 0x0158, 4, 0x0920, 0, 0),
-	MX6_PAD_EIM_D21__GPIO_3_21		= IOMUX_PAD(0x0528, 0x0158, 5, 0x0000, 0, 0),
-	MX6_PAD_EIM_D21__I2C1_SCL		= IOMUX_PAD(0x0528, 0x0158, 6 | IOMUX_CONFIG_SION, 0x0868, 1, 0),
-	MX6_PAD_EIM_D21__SPDIF_IN1		= IOMUX_PAD(0x0528, 0x0158, 7, 0x08F0, 0, 0),
-	MX6_PAD_EIM_D22__WEIM_WEIM_D_22		= IOMUX_PAD(0x052C, 0x015C, 0, 0x0000, 0, 0),
-	MX6_PAD_EIM_D22__ECSPI4_MISO		= IOMUX_PAD(0x052C, 0x015C, 1, 0x0000, 0, 0),
-	MX6_PAD_EIM_D22__IPU1_DI0_PIN1		= IOMUX_PAD(0x052C, 0x015C, 2, 0x0000, 0, 0),
-	MX6_PAD_EIM_D22__IPU1_CSI1_D_10		= IOMUX_PAD(0x052C, 0x015C, 3, 0x0888, 0, 0),
-	MX6_PAD_EIM_D22__USBOH3_USBOTG_PWR	= IOMUX_PAD(0x052C, 0x015C, 4, 0x0000, 0, 0),
-	MX6_PAD_EIM_D22__GPIO_3_22		= IOMUX_PAD(0x052C, 0x015C, 5, 0x0000, 0, 0),
-	MX6_PAD_EIM_D22__SPDIF_OUT1		= IOMUX_PAD(0x052C, 0x015C, 6, 0x0000, 0, 0),
-	MX6_PAD_EIM_D22__PL301_SIM_MX6DL_PER1_HWRITE	= IOMUX_PAD(0x052C, 0x015C, 7, 0x0000, 0, 0),
-	MX6_PAD_EIM_D22__EPDC_SDCE_6		= IOMUX_PAD(0x052C, 0x015C, 8, 0x0000, 0, 0),
-	MX6_PAD_EIM_D23__WEIM_WEIM_D_23		= IOMUX_PAD(0x0530, 0x0160, 0, 0x0000, 0, 0),
-	MX6_PAD_EIM_D23__IPU1_DI0_D0_CS		= IOMUX_PAD(0x0530, 0x0160, 1, 0x0000, 0, 0),
-	MX6_PAD_EIM_D23__UART3_CTS		= IOMUX_PAD(0x0530, 0x0160, 2, 0x0000, 0, 0),
-	MX6_PAD_EIM_D23__UART3_RTS		= IOMUX_PAD(0x0530, 0x0160, 2, 0x0908, 0, 0),
-	MX6_PAD_EIM_D23__UART1_DCD		= IOMUX_PAD(0x0530, 0x0160, 3, 0x0000, 0, 0),
-	MX6_PAD_EIM_D23__IPU1_CSI1_DATA_EN	= IOMUX_PAD(0x0530, 0x0160, 4, 0x08B0, 0, 0),
-	MX6_PAD_EIM_D23__GPIO_3_23		= IOMUX_PAD(0x0530, 0x0160, 5, 0x0000, 0, 0),
-	MX6_PAD_EIM_D23__IPU1_DI1_PIN2		= IOMUX_PAD(0x0530, 0x0160, 6, 0x0000, 0, 0),
-	MX6_PAD_EIM_D23__IPU1_DI1_PIN14		= IOMUX_PAD(0x0530, 0x0160, 7, 0x0000, 0, 0),
-	MX6_PAD_EIM_D23__EPDC_SDDO_11		= IOMUX_PAD(0x0530, 0x0160, 8, 0x0000, 0, 0),
-	MX6_PAD_EIM_D24__WEIM_WEIM_D_24		= IOMUX_PAD(0x0534, 0x0164, 0, 0x0000, 0, 0),
-	MX6_PAD_EIM_D24__ECSPI4_SS2		= IOMUX_PAD(0x0534, 0x0164, 1, 0x0000, 0, 0),
-	MX6_PAD_EIM_D24__UART3_TXD		= IOMUX_PAD(0x0534, 0x0164, 2, 0x0000, 0, 0),
-	MX6_PAD_EIM_D24__UART3_RXD		= IOMUX_PAD(0x0534, 0x0164, 2, 0x090C, 0, 0),
-	MX6_PAD_EIM_D24__ECSPI1_SS2		= IOMUX_PAD(0x0534, 0x0164, 3, 0x07EC, 0, 0),
-	MX6_PAD_EIM_D24__ECSPI2_SS2		= IOMUX_PAD(0x0534, 0x0164, 4, 0x0000, 0, 0),
-	MX6_PAD_EIM_D24__GPIO_3_24		= IOMUX_PAD(0x0534, 0x0164, 5, 0x0000, 0, 0),
-	MX6_PAD_EIM_D24__AUDMUX_AUD5_RXFS	= IOMUX_PAD(0x0534, 0x0164, 6, 0x07BC, 1, 0),
-	MX6_PAD_EIM_D24__UART1_DTR		= IOMUX_PAD(0x0534, 0x0164, 7, 0x0000, 0, 0),
-	MX6_PAD_EIM_D24__EPDC_SDCE_7		= IOMUX_PAD(0x0534, 0x0164, 8, 0x0000, 0, 0),
-	MX6_PAD_EIM_D25__WEIM_WEIM_D_25		= IOMUX_PAD(0x0538, 0x0168, 0, 0x0000, 0, 0),
-	MX6_PAD_EIM_D25__ECSPI4_SS3		= IOMUX_PAD(0x0538, 0x0168, 1, 0x0000, 0, 0),
-	MX6_PAD_EIM_D25__UART3_TXD		= IOMUX_PAD(0x0538, 0x0168, 2, 0x0000, 0, 0),
-	MX6_PAD_EIM_D25__UART3_RXD		= IOMUX_PAD(0x0538, 0x0168, 2, 0x090C, 1, 0),
-	MX6_PAD_EIM_D25__ECSPI1_SS3		= IOMUX_PAD(0x0538, 0x0168, 3, 0x07F0, 0, 0),
-	MX6_PAD_EIM_D25__ECSPI2_SS3		= IOMUX_PAD(0x0538, 0x0168, 4, 0x0000, 0, 0),
-	MX6_PAD_EIM_D25__GPIO_3_25		= IOMUX_PAD(0x0538, 0x0168, 5, 0x0000, 0, 0),
-	MX6_PAD_EIM_D25__AUDMUX_AUD5_RXC	= IOMUX_PAD(0x0538, 0x0168, 6, 0x07B8, 1, 0),
-	MX6_PAD_EIM_D25__UART1_DSR		= IOMUX_PAD(0x0538, 0x0168, 7, 0x0000, 0, 0),
-	MX6_PAD_EIM_D25__EPDC_SDCE_8		= IOMUX_PAD(0x0538, 0x0168, 8, 0x0000, 0, 0),
-	MX6_PAD_EIM_D26__WEIM_WEIM_D_26		= IOMUX_PAD(0x053C, 0x016C, 0, 0x0000, 0, 0),
-	MX6_PAD_EIM_D26__IPU1_DI1_PIN11		= IOMUX_PAD(0x053C, 0x016C, 1, 0x0000, 0, 0),
-	MX6_PAD_EIM_D26__IPU1_CSI0_D_1		= IOMUX_PAD(0x053C, 0x016C, 2, 0x0000, 0, 0),
-	MX6_PAD_EIM_D26__IPU1_CSI1_D_14		= IOMUX_PAD(0x053C, 0x016C, 3, 0x0898, 1, 0),
-	MX6_PAD_EIM_D26__UART2_TXD		= IOMUX_PAD(0x053C, 0x016C, 4, 0x0000, 0, 0),
-	MX6_PAD_EIM_D26__UART2_RXD		= IOMUX_PAD(0x053C, 0x016C, 4, 0x0904, 0, 0),
-	MX6_PAD_EIM_D26__GPIO_3_26		= IOMUX_PAD(0x053C, 0x016C, 5, 0x0000, 0, 0),
-	MX6_PAD_EIM_D26__IPU1_SISG_2		= IOMUX_PAD(0x053C, 0x016C, 6, 0x0000, 0, 0),
-	MX6_PAD_EIM_D26__IPU1_DISP1_DAT_22	= IOMUX_PAD(0x053C, 0x016C, 7, 0x0000, 0, 0),
-	MX6_PAD_EIM_D26__EPDC_SDOED		= IOMUX_PAD(0x053C, 0x016C, 8, 0x0000, 0, 0),
-	MX6_PAD_EIM_D27__WEIM_WEIM_D_27		= IOMUX_PAD(0x0540, 0x0170, 0, 0x0000, 0, 0),
-	MX6_PAD_EIM_D27__IPU1_DI1_PIN13		= IOMUX_PAD(0x0540, 0x0170, 1, 0x0000, 0, 0),
-	MX6_PAD_EIM_D27__IPU1_CSI0_D_0		= IOMUX_PAD(0x0540, 0x0170, 2, 0x0000, 0, 0),
-	MX6_PAD_EIM_D27__IPU1_CSI1_D_13		= IOMUX_PAD(0x0540, 0x0170, 3, 0x0894, 1, 0),
-	MX6_PAD_EIM_D27__UART2_TXD		= IOMUX_PAD(0x0540, 0x0170, 4, 0x0000, 0, 0),
-	MX6_PAD_EIM_D27__UART2_RXD		= IOMUX_PAD(0x0540, 0x0170, 4, 0x0904, 1, 0),
-	MX6_PAD_EIM_D27__GPIO_3_27		= IOMUX_PAD(0x0540, 0x0170, 5, 0x0000, 0, 0),
-	MX6_PAD_EIM_D27__IPU1_SISG_3		= IOMUX_PAD(0x0540, 0x0170, 6, 0x0000, 0, 0),
-	MX6_PAD_EIM_D27__IPU1_DISP1_DAT_23	= IOMUX_PAD(0x0540, 0x0170, 7, 0x0000, 0, 0),
-	MX6_PAD_EIM_D27__EPDC_SDOE		= IOMUX_PAD(0x0540, 0x0170, 8, 0x0000, 0, 0),
-	MX6_PAD_EIM_D28__WEIM_WEIM_D_28		= IOMUX_PAD(0x0544, 0x0174, 0, 0x0000, 0, 0),
-	MX6_PAD_EIM_D28__I2C1_SDA		= IOMUX_PAD(0x0544, 0x0174, 1 | IOMUX_CONFIG_SION, 0x086C, 1, 0),
-	MX6_PAD_EIM_D28__ECSPI4_MOSI		= IOMUX_PAD(0x0544, 0x0174, 2, 0x0000, 0, 0),
-	MX6_PAD_EIM_D28__IPU1_CSI1_D_12		= IOMUX_PAD(0x0544, 0x0174, 3, 0x0890, 1, 0),
-	MX6_PAD_EIM_D28__UART2_CTS		= IOMUX_PAD(0x0544, 0x0174, 4, 0x0000, 0, 0),
-	MX6_PAD_EIM_D28__UART2_RTS		= IOMUX_PAD(0x0544, 0x0174, 4, 0x0900, 0, 0),
-	MX6_PAD_EIM_D28__GPIO_3_28		= IOMUX_PAD(0x0544, 0x0174, 5, 0x0000, 0, 0),
-	MX6_PAD_EIM_D28__IPU1_EXT_TRIG		= IOMUX_PAD(0x0544, 0x0174, 6, 0x0000, 0, 0),
-	MX6_PAD_EIM_D28__IPU1_DI0_PIN13		= IOMUX_PAD(0x0544, 0x0174, 7, 0x0000, 0, 0),
-	MX6_PAD_EIM_D28__EPDC_PWRCTRL_3		= IOMUX_PAD(0x0544, 0x0174, 8, 0x0000, 0, 0),
-	MX6_PAD_EIM_D29__WEIM_WEIM_D_29		= IOMUX_PAD(0x0548, 0x0178, 0, 0x0000, 0, 0),
-	MX6_PAD_EIM_D29__IPU1_DI1_PIN15		= IOMUX_PAD(0x0548, 0x0178, 1, 0x0000, 0, 0),
-	MX6_PAD_EIM_D29__ECSPI4_SS0		= IOMUX_PAD(0x0548, 0x0178, 2, 0x0808, 1, 0),
-	MX6_PAD_EIM_D29__UART2_CTS		= IOMUX_PAD(0x0548, 0x0178, 4, 0x0000, 0, 0),
-	MX6_PAD_EIM_D29__UART2_RTS		= IOMUX_PAD(0x0548, 0x0178, 4, 0x0900, 1, 0),
-	MX6_PAD_EIM_D29__GPIO_3_29		= IOMUX_PAD(0x0548, 0x0178, 5, 0x0000, 0, 0),
-	MX6_PAD_EIM_D29__IPU1_CSI1_VSYNC	= IOMUX_PAD(0x0548, 0x0178, 6, 0x08BC, 0, 0),
-	MX6_PAD_EIM_D29__IPU1_DI0_PIN14		= IOMUX_PAD(0x0548, 0x0178, 7, 0x0000, 0, 0),
-	MX6_PAD_EIM_D29__EPDC_PWRWAKE		= IOMUX_PAD(0x0548, 0x0178, 8, 0x0000, 0, 0),
-	MX6_PAD_EIM_D30__WEIM_WEIM_D_30		= IOMUX_PAD(0x054C, 0x017C, 0, 0x0000, 0, 0),
-	MX6_PAD_EIM_D30__IPU1_DISP1_DAT_21	= IOMUX_PAD(0x054C, 0x017C, 1, 0x0000, 0, 0),
-	MX6_PAD_EIM_D30__IPU1_DI0_PIN11		= IOMUX_PAD(0x054C, 0x017C, 2, 0x0000, 0, 0),
-	MX6_PAD_EIM_D30__IPU1_CSI0_D_3		= IOMUX_PAD(0x054C, 0x017C, 3, 0x0000, 0, 0),
-	MX6_PAD_EIM_D30__UART3_CTS		= IOMUX_PAD(0x054C, 0x017C, 4, 0x0000, 0, 0),
-	MX6_PAD_EIM_D30__UART3_RTS		= IOMUX_PAD(0x054C, 0x017C, 4, 0x0908, 1, 0),
-	MX6_PAD_EIM_D30__GPIO_3_30		= IOMUX_PAD(0x054C, 0x017C, 5, 0x0000, 0, 0),
-	MX6_PAD_EIM_D30__USBOH3_USBH1_OC	= IOMUX_PAD(0x054C, 0x017C, 6, 0x0924, 0, 0),
-	MX6_PAD_EIM_D30__PL301_SIM_MX6DL_PER1_HPROT_0	= IOMUX_PAD(0x054C, 0x017C, 7, 0x0000, 0, 0),
-	MX6_PAD_EIM_D30__EPDC_SDOEZ		= IOMUX_PAD(0x054C, 0x017C, 8, 0x0000, 0, 0),
-	MX6_PAD_EIM_D31__WEIM_WEIM_D_31		= IOMUX_PAD(0x0550, 0x0180, 0, 0x0000, 0, 0),
-	MX6_PAD_EIM_D31__IPU1_DISP1_DAT_20	= IOMUX_PAD(0x0550, 0x0180, 1, 0x0000, 0, 0),
-	MX6_PAD_EIM_D31__IPU1_DI0_PIN12		= IOMUX_PAD(0x0550, 0x0180, 2, 0x0000, 0, 0),
-	MX6_PAD_EIM_D31__IPU1_CSI0_D_2		= IOMUX_PAD(0x0550, 0x0180, 3, 0x0000, 0, 0),
-	MX6_PAD_EIM_D31__UART3_CTS		= IOMUX_PAD(0x0550, 0x0180, 4, 0x0000, 0, 0),
-	MX6_PAD_EIM_D31__UART3_RTS		= IOMUX_PAD(0x0550, 0x0180, 4, 0x0908, 2, 0),
-	MX6_PAD_EIM_D31__GPIO_3_31		= IOMUX_PAD(0x0550, 0x0180, 5, 0x0000, 0, 0),
-	MX6_PAD_EIM_D31__USBOH3_USBH1_PWR	= IOMUX_PAD(0x0550, 0x0180, 6, 0x0000, 0, 0),
-	MX6_PAD_EIM_D31__PL301_SIM_MX6DL_PER1_HPROT_1	= IOMUX_PAD(0x0550, 0x0180, 7, 0x0000, 0, 0),
-	MX6_PAD_EIM_D31__EPDC_SDCLK		= IOMUX_PAD(0x0550, 0x0180, 8, 0x0000, 0, 0),
-	MX6_PAD_EIM_D31__WEIM_ACLK_FREERUN	= IOMUX_PAD(0x0550, 0x0180, 9, 0x0000, 0, 0),
-	MX6_PAD_EIM_DA0__WEIM_WEIM_DA_A_0	= IOMUX_PAD(0x0554, 0x0184, 0, 0x0000, 0, 0),
-	MX6_PAD_EIM_DA0__IPU1_DISP1_DAT_9	= IOMUX_PAD(0x0554, 0x0184, 1, 0x0000, 0, 0),
-	MX6_PAD_EIM_DA0__IPU1_CSI1_D_9		= IOMUX_PAD(0x0554, 0x0184, 2, 0x0000, 0, 0),
-	MX6_PAD_EIM_DA0__MIPI_CORE_DPHY_TEST_OUT_2	= IOMUX_PAD(0x0554, 0x0184, 3, 0x0000, 0, 0),
-	MX6_PAD_EIM_DA0__GPIO_3_0		= IOMUX_PAD(0x0554, 0x0184, 5, 0x0000, 0, 0),
-	MX6_PAD_EIM_DA0__TPSMP_HDATA_14		= IOMUX_PAD(0x0554, 0x0184, 6, 0x0000, 0, 0),
-	MX6_PAD_EIM_DA0__SRC_BT_CFG_0		= IOMUX_PAD(0x0554, 0x0184, 7, 0x0000, 0, 0),
-	MX6_PAD_EIM_DA0__EPDC_SDCLKN		= IOMUX_PAD(0x0554, 0x0184, 8, 0x0000, 0, 0),
-	MX6_PAD_EIM_DA1__WEIM_WEIM_DA_A_1	= IOMUX_PAD(0x0558, 0x0188, 0, 0x0000, 0, 0),
-	MX6_PAD_EIM_DA1__IPU1_DISP1_DAT_8	= IOMUX_PAD(0x0558, 0x0188, 1, 0x0000, 0, 0),
-	MX6_PAD_EIM_DA1__IPU1_CSI1_D_8		= IOMUX_PAD(0x0558, 0x0188, 2, 0x0000, 0, 0),
-	MX6_PAD_EIM_DA1__MIPI_CORE_DPHY_TEST_OUT_3	= IOMUX_PAD(0x0558, 0x0188, 3, 0x0000, 0, 0),
-	MX6_PAD_EIM_DA1__ANATOP_USBPHY1_TSTI_TX_LS_MODE	= IOMUX_PAD(0x0558, 0x0188, 4, 0x0000, 0, 0),
-	MX6_PAD_EIM_DA1__GPIO_3_1		= IOMUX_PAD(0x0558, 0x0188, 5, 0x0000, 0, 0),
-	MX6_PAD_EIM_DA1__TPSMP_HDATA_15		= IOMUX_PAD(0x0558, 0x0188, 6, 0x0000, 0, 0),
-	MX6_PAD_EIM_DA1__SRC_BT_CFG_1		= IOMUX_PAD(0x0558, 0x0188, 7, 0x0000, 0, 0),
-	MX6_PAD_EIM_DA1__EPDC_SDLE		= IOMUX_PAD(0x0558, 0x0188, 8, 0x0000, 0, 0),
-	MX6_PAD_EIM_DA10__WEIM_WEIM_DA_A_10	= IOMUX_PAD(0x055C, 0x018C, 0, 0x0000, 0, 0),
-	MX6_PAD_EIM_DA10__IPU1_DI1_PIN15	= IOMUX_PAD(0x055C, 0x018C, 1, 0x0000, 0, 0),
-	MX6_PAD_EIM_DA10__IPU1_CSI1_DATA_EN	= IOMUX_PAD(0x055C, 0x018C, 2, 0x08B0, 1, 0),
-	MX6_PAD_EIM_DA10__MIPI_CORE_DPHY_TEST_OUT_12	= IOMUX_PAD(0x055C, 0x018C, 3, 0x0000, 0, 0),
-	MX6_PAD_EIM_DA10__GPIO_3_10		= IOMUX_PAD(0x055C, 0x018C, 5, 0x0000, 0, 0),
-	MX6_PAD_EIM_DA10__TPSMP_HDATA_24	= IOMUX_PAD(0x055C, 0x018C, 6, 0x0000, 0, 0),
-	MX6_PAD_EIM_DA10__SRC_BT_CFG_10		= IOMUX_PAD(0x055C, 0x018C, 7, 0x0000, 0, 0),
-	MX6_PAD_EIM_DA10__EPDC_SDDO_1		= IOMUX_PAD(0x055C, 0x018C, 8, 0x0000, 0, 0),
-	MX6_PAD_EIM_DA11__WEIM_WEIM_DA_A_11	= IOMUX_PAD(0x0560, 0x0190, 0, 0x0000, 0, 0),
-	MX6_PAD_EIM_DA11__IPU1_DI1_PIN2		= IOMUX_PAD(0x0560, 0x0190, 1, 0x0000, 0, 0),
-	MX6_PAD_EIM_DA11__IPU1_CSI1_HSYNC	= IOMUX_PAD(0x0560, 0x0190, 2, 0x08B4, 0, 0),
-	MX6_PAD_EIM_DA11__MIPI_CORE_DPHY_TEST_OUT_13	= IOMUX_PAD(0x0560, 0x0190, 3, 0x0000, 0, 0),
-	MX6_PAD_EIM_DA11__SDMA_DEBUG_EVT_CHN_LINES_6	= IOMUX_PAD(0x0560, 0x0190, 4, 0x0000, 0, 0),
-	MX6_PAD_EIM_DA11__GPIO_3_11		= IOMUX_PAD(0x0560, 0x0190, 5, 0x0000, 0, 0),
-	MX6_PAD_EIM_DA11__TPSMP_HDATA_25	= IOMUX_PAD(0x0560, 0x0190, 6, 0x0000, 0, 0),
-	MX6_PAD_EIM_DA11__SRC_BT_CFG_11		= IOMUX_PAD(0x0560, 0x0190, 7, 0x0000, 0, 0),
-	MX6_PAD_EIM_DA11__EPDC_SDDO_3		= IOMUX_PAD(0x0560, 0x0190, 8, 0x0000, 0, 0),
-	MX6_PAD_EIM_DA12__WEIM_WEIM_DA_A_12	= IOMUX_PAD(0x0564, 0x0194, 0, 0x0000, 0, 0),
-	MX6_PAD_EIM_DA12__IPU1_DI1_PIN3		= IOMUX_PAD(0x0564, 0x0194, 1, 0x0000, 0, 0),
-	MX6_PAD_EIM_DA12__IPU1_CSI1_VSYNC	= IOMUX_PAD(0x0564, 0x0194, 2, 0x08BC, 1, 0),
-	MX6_PAD_EIM_DA12__MIPI_CORE_DPHY_TEST_OUT_14	= IOMUX_PAD(0x0564, 0x0194, 3, 0x0000, 0, 0),
-	MX6_PAD_EIM_DA12__SDMA_DEBUG_EVT_CHN_LINES_3	= IOMUX_PAD(0x0564, 0x0194, 4, 0x0000, 0, 0),
-	MX6_PAD_EIM_DA12__GPIO_3_12		= IOMUX_PAD(0x0564, 0x0194, 5, 0x0000, 0, 0),
-	MX6_PAD_EIM_DA12__TPSMP_HDATA_26	= IOMUX_PAD(0x0564, 0x0194, 6, 0x0000, 0, 0),
-	MX6_PAD_EIM_DA12__SRC_BT_CFG_12		= IOMUX_PAD(0x0564, 0x0194, 7, 0x0000, 0, 0),
-	MX6_PAD_EIM_DA12__EPDC_SDDO_2		= IOMUX_PAD(0x0564, 0x0194, 8, 0x0000, 0, 0),
-	MX6_PAD_EIM_DA13__WEIM_WEIM_DA_A_13	= IOMUX_PAD(0x0568, 0x0198, 0, 0x0000, 0, 0),
-	MX6_PAD_EIM_DA13__IPU1_DI1_D0_CS	= IOMUX_PAD(0x0568, 0x0198, 1, 0x0000, 0, 0),
-	MX6_PAD_EIM_DA13__CCM_DI1_EXT_CLK	= IOMUX_PAD(0x0568, 0x0198, 2, 0x07D0, 0, 0),
-	MX6_PAD_EIM_DA13__MIPI_CORE_DPHY_TEST_OUT_15	= IOMUX_PAD(0x0568, 0x0198, 3, 0x0000, 0, 0),
-	MX6_PAD_EIM_DA13__SDMA_DEBUG_EVT_CHN_LINES_4	= IOMUX_PAD(0x0568, 0x0198, 4, 0x0000, 0, 0),
-	MX6_PAD_EIM_DA13__GPIO_3_13		= IOMUX_PAD(0x0568, 0x0198, 5, 0x0000, 0, 0),
-	MX6_PAD_EIM_DA13__TPSMP_HDATA_27	= IOMUX_PAD(0x0568, 0x0198, 6, 0x0000, 0, 0),
-	MX6_PAD_EIM_DA13__SRC_BT_CFG_13		= IOMUX_PAD(0x0568, 0x0198, 7, 0x0000, 0, 0),
-	MX6_PAD_EIM_DA13__EPDC_SDDO_13		= IOMUX_PAD(0x0568, 0x0198, 8, 0x0000, 0, 0),
-	MX6_PAD_EIM_DA14__WEIM_WEIM_DA_A_14	= IOMUX_PAD(0x056C, 0x019C, 0, 0x0000, 0, 0),
-	MX6_PAD_EIM_DA14__IPU1_DI1_D1_CS	= IOMUX_PAD(0x056C, 0x019C, 1, 0x0000, 0, 0),
-	MX6_PAD_EIM_DA14__CCM_DI0_EXT_CLK	= IOMUX_PAD(0x056C, 0x019C, 2, 0x0000, 0, 0),
-	MX6_PAD_EIM_DA14__MIPI_CORE_DPHY_TEST_OUT_16	= IOMUX_PAD(0x056C, 0x019C, 3, 0x0000, 0, 0),
-	MX6_PAD_EIM_DA14__SDMA_DEBUG_EVT_CHN_LINES_5	= IOMUX_PAD(0x056C, 0x019C, 4, 0x0000, 0, 0),
-	MX6_PAD_EIM_DA14__GPIO_3_14		= IOMUX_PAD(0x056C, 0x019C, 5, 0x0000, 0, 0),
-	MX6_PAD_EIM_DA14__TPSMP_HDATA_28	= IOMUX_PAD(0x056C, 0x019C, 6, 0x0000, 0, 0),
-	MX6_PAD_EIM_DA14__SRC_BT_CFG_14		= IOMUX_PAD(0x056C, 0x019C, 7, 0x0000, 0, 0),
-	MX6_PAD_EIM_DA14__EPDC_SDDO_14		= IOMUX_PAD(0x056C, 0x019C, 8, 0x0000, 0, 0),
-	MX6_PAD_EIM_DA15__WEIM_WEIM_DA_A_15	= IOMUX_PAD(0x0570, 0x01A0, 0, 0x0000, 0, 0),
-	MX6_PAD_EIM_DA15__IPU1_DI1_PIN1		= IOMUX_PAD(0x0570, 0x01A0, 1, 0x0000, 0, 0),
-	MX6_PAD_EIM_DA15__IPU1_DI1_PIN4		= IOMUX_PAD(0x0570, 0x01A0, 2, 0x0000, 0, 0),
-	MX6_PAD_EIM_DA15__MIPI_CORE_DPHY_TEST_OUT_17	= IOMUX_PAD(0x0570, 0x01A0, 3, 0x0000, 0, 0),
-	MX6_PAD_EIM_DA15__GPIO_3_15		= IOMUX_PAD(0x0570, 0x01A0, 5, 0x0000, 0, 0),
-	MX6_PAD_EIM_DA15__TPSMP_HDATA_29	= IOMUX_PAD(0x0570, 0x01A0, 6, 0x0000, 0, 0),
-	MX6_PAD_EIM_DA15__SRC_BT_CFG_15		= IOMUX_PAD(0x0570, 0x01A0, 7, 0x0000, 0, 0),
-	MX6_PAD_EIM_DA15__EPDC_SDDO_9		= IOMUX_PAD(0x0570, 0x01A0, 8, 0x0000, 0, 0),
-	MX6_PAD_EIM_DA2__WEIM_WEIM_DA_A_2	= IOMUX_PAD(0x0574, 0x01A4, 0, 0x0000, 0, 0),
-	MX6_PAD_EIM_DA2__IPU1_DISP1_DAT_7	= IOMUX_PAD(0x0574, 0x01A4, 1, 0x0000, 0, 0),
-	MX6_PAD_EIM_DA2__IPU1_CSI1_D_7		= IOMUX_PAD(0x0574, 0x01A4, 2, 0x0000, 0, 0),
-	MX6_PAD_EIM_DA2__MIPI_CORE_DPHY_TEST_OUT_4	= IOMUX_PAD(0x0574, 0x01A4, 3, 0x0000, 0, 0),
-	MX6_PAD_EIM_DA2__ANATOP_USBPHY1_TSTI_TX_HS_MODE	= IOMUX_PAD(0x0574, 0x01A4, 4, 0x0000, 0, 0),
-	MX6_PAD_EIM_DA2__GPIO_3_2		= IOMUX_PAD(0x0574, 0x01A4, 5, 0x0000, 0, 0),
-	MX6_PAD_EIM_DA2__TPSMP_HDATA_16		= IOMUX_PAD(0x0574, 0x01A4, 6, 0x0000, 0, 0),
-	MX6_PAD_EIM_DA2__SRC_BT_CFG_2		= IOMUX_PAD(0x0574, 0x01A4, 7, 0x0000, 0, 0),
-	MX6_PAD_EIM_DA2__EPDC_BDR_0		= IOMUX_PAD(0x0574, 0x01A4, 8, 0x0000, 0, 0),
-	MX6_PAD_EIM_DA3__WEIM_WEIM_DA_A_3	= IOMUX_PAD(0x0578, 0x01A8, 0, 0x0000, 0, 0),
-	MX6_PAD_EIM_DA3__IPU1_DISP1_DAT_6	= IOMUX_PAD(0x0578, 0x01A8, 1, 0x0000, 0, 0),
-	MX6_PAD_EIM_DA3__IPU1_CSI1_D_6		= IOMUX_PAD(0x0578, 0x01A8, 2, 0x0000, 0, 0),
-	MX6_PAD_EIM_DA3__MIPI_CORE_DPHY_TEST_OUT_5	= IOMUX_PAD(0x0578, 0x01A8, 3, 0x0000, 0, 0),
-	MX6_PAD_EIM_DA3__ANATOP_USBPHY1_TSTI_TX_HIZ	= IOMUX_PAD(0x0578, 0x01A8, 4, 0x0000, 0, 0),
-	MX6_PAD_EIM_DA3__GPIO_3_3		= IOMUX_PAD(0x0578, 0x01A8, 5, 0x0000, 0, 0),
-	MX6_PAD_EIM_DA3__TPSMP_HDATA_17		= IOMUX_PAD(0x0578, 0x01A8, 6, 0x0000, 0, 0),
-	MX6_PAD_EIM_DA3__SRC_BT_CFG_3		= IOMUX_PAD(0x0578, 0x01A8, 7, 0x0000, 0, 0),
-	MX6_PAD_EIM_DA3__EPDC_BDR_1		= IOMUX_PAD(0x0578, 0x01A8, 8, 0x0000, 0, 0),
-	MX6_PAD_EIM_DA4__WEIM_WEIM_DA_A_4	= IOMUX_PAD(0x057C, 0x01AC, 0, 0x0000, 0, 0),
-	MX6_PAD_EIM_DA4__IPU1_DISP1_DAT_5	= IOMUX_PAD(0x057C, 0x01AC, 1, 0x0000, 0, 0),
-	MX6_PAD_EIM_DA4__IPU1_CSI1_D_5		= IOMUX_PAD(0x057C, 0x01AC, 2, 0x0000, 0, 0),
-	MX6_PAD_EIM_DA4__MIPI_CORE_DPHY_TEST_OUT_6	= IOMUX_PAD(0x057C, 0x01AC, 3, 0x0000, 0, 0),
-	MX6_PAD_EIM_DA4__ANATOP_USBPHY1_TSTI_TX_EN	= IOMUX_PAD(0x057C, 0x01AC, 4, 0x0000, 0, 0),
-	MX6_PAD_EIM_DA4__GPIO_3_4		= IOMUX_PAD(0x057C, 0x01AC, 5, 0x0000, 0, 0),
-	MX6_PAD_EIM_DA4__TPSMP_HDATA_18		= IOMUX_PAD(0x057C, 0x01AC, 6, 0x0000, 0, 0),
-	MX6_PAD_EIM_DA4__SRC_BT_CFG_4		= IOMUX_PAD(0x057C, 0x01AC, 7, 0x0000, 0, 0),
-	MX6_PAD_EIM_DA4__EPDC_SDCE_0		= IOMUX_PAD(0x057C, 0x01AC, 8, 0x0000, 0, 0),
-	MX6_PAD_EIM_DA5__WEIM_WEIM_DA_A_5	= IOMUX_PAD(0x0580, 0x01B0, 0, 0x0000, 0, 0),
-	MX6_PAD_EIM_DA5__IPU1_DISP1_DAT_4	= IOMUX_PAD(0x0580, 0x01B0, 1, 0x0000, 0, 0),
-	MX6_PAD_EIM_DA5__IPU1_CSI1_D_4		= IOMUX_PAD(0x0580, 0x01B0, 2, 0x0000, 0, 0),
-	MX6_PAD_EIM_DA5__MIPI_CORE_DPHY_TEST_OUT_7	= IOMUX_PAD(0x0580, 0x01B0, 3, 0x0000, 0, 0),
-	MX6_PAD_EIM_DA5__ANATOP_USBPHY1_TSTI_TX_DP	= IOMUX_PAD(0x0580, 0x01B0, 4, 0x0000, 0, 0),
-	MX6_PAD_EIM_DA5__GPIO_3_5		= IOMUX_PAD(0x0580, 0x01B0, 5, 0x0000, 0, 0),
-	MX6_PAD_EIM_DA5__TPSMP_HDATA_19		= IOMUX_PAD(0x0580, 0x01B0, 6, 0x0000, 0, 0),
-	MX6_PAD_EIM_DA5__SRC_BT_CFG_5		= IOMUX_PAD(0x0580, 0x01B0, 7, 0x0000, 0, 0),
-	MX6_PAD_EIM_DA5__EPDC_SDCE_1		= IOMUX_PAD(0x0580, 0x01B0, 8, 0x0000, 0, 0),
-	MX6_PAD_EIM_DA6__WEIM_WEIM_DA_A_6	= IOMUX_PAD(0x0584, 0x01B4, 0, 0x0000, 0, 0),
-	MX6_PAD_EIM_DA6__IPU1_DISP1_DAT_3	= IOMUX_PAD(0x0584, 0x01B4, 1, 0x0000, 0, 0),
-	MX6_PAD_EIM_DA6__IPU1_CSI1_D_3		= IOMUX_PAD(0x0584, 0x01B4, 2, 0x0000, 0, 0),
-	MX6_PAD_EIM_DA6__MIPI_CORE_DPHY_TEST_OUT_8	= IOMUX_PAD(0x0584, 0x01B4, 3, 0x0000, 0, 0),
-	MX6_PAD_EIM_DA6__ANATOP_USBPHY1_TSTI_TX_DN	= IOMUX_PAD(0x0584, 0x01B4, 4, 0x0000, 0, 0),
-	MX6_PAD_EIM_DA6__GPIO_3_6		= IOMUX_PAD(0x0584, 0x01B4, 5, 0x0000, 0, 0),
-	MX6_PAD_EIM_DA6__TPSMP_HDATA_20		= IOMUX_PAD(0x0584, 0x01B4, 6, 0x0000, 0, 0),
-	MX6_PAD_EIM_DA6__SRC_BT_CFG_6		= IOMUX_PAD(0x0584, 0x01B4, 7, 0x0000, 0, 0),
-	MX6_PAD_EIM_DA6__EPDC_SDCE_2		= IOMUX_PAD(0x0584, 0x01B4, 8, 0x0000, 0, 0),
-	MX6_PAD_EIM_DA7__WEIM_WEIM_DA_A_7	= IOMUX_PAD(0x0588, 0x01B8, 0, 0x0000, 0, 0),
-	MX6_PAD_EIM_DA7__IPU1_DISP1_DAT_2	= IOMUX_PAD(0x0588, 0x01B8, 1, 0x0000, 0, 0),
-	MX6_PAD_EIM_DA7__IPU1_CSI1_D_2		= IOMUX_PAD(0x0588, 0x01B8, 2, 0x0000, 0, 0),
-	MX6_PAD_EIM_DA7__MIPI_CORE_DPHY_TEST_OUT_9	= IOMUX_PAD(0x0588, 0x01B8, 3, 0x0000, 0, 0),
-	MX6_PAD_EIM_DA7__GPIO_3_7		= IOMUX_PAD(0x0588, 0x01B8, 5, 0x0000, 0, 0),
-	MX6_PAD_EIM_DA7__TPSMP_HDATA_21		= IOMUX_PAD(0x0588, 0x01B8, 6, 0x0000, 0, 0),
-	MX6_PAD_EIM_DA7__SRC_BT_CFG_7		= IOMUX_PAD(0x0588, 0x01B8, 7, 0x0000, 0, 0),
-	MX6_PAD_EIM_DA7__EPDC_SDCE_3		= IOMUX_PAD(0x0588, 0x01B8, 8, 0x0000, 0, 0),
-	MX6_PAD_EIM_DA8__WEIM_WEIM_DA_A_8	= IOMUX_PAD(0x058C, 0x01BC, 0, 0x0000, 0, 0),
-	MX6_PAD_EIM_DA8__IPU1_DISP1_DAT_1	= IOMUX_PAD(0x058C, 0x01BC, 1, 0x0000, 0, 0),
-	MX6_PAD_EIM_DA8__IPU1_CSI1_D_1		= IOMUX_PAD(0x058C, 0x01BC, 2, 0x0000, 0, 0),
-	MX6_PAD_EIM_DA8__MIPI_CORE_DPHY_TEST_OUT_10	= IOMUX_PAD(0x058C, 0x01BC, 3, 0x0000, 0, 0),
-	MX6_PAD_EIM_DA8__GPIO_3_8		= IOMUX_PAD(0x058C, 0x01BC, 5, 0x0000, 0, 0),
-	MX6_PAD_EIM_DA8__TPSMP_HDATA_22		= IOMUX_PAD(0x058C, 0x01BC, 6, 0x0000, 0, 0),
-	MX6_PAD_EIM_DA8__SRC_BT_CFG_8		= IOMUX_PAD(0x058C, 0x01BC, 7, 0x0000, 0, 0),
-	MX6_PAD_EIM_DA8__EPDC_SDCE_4		= IOMUX_PAD(0x058C, 0x01BC, 8, 0x0000, 0, 0),
-	MX6_PAD_EIM_DA9__WEIM_WEIM_DA_A_9	= IOMUX_PAD(0x0590, 0x01C0, 0, 0x0000, 0, 0),
-	MX6_PAD_EIM_DA9__IPU1_DISP1_DAT_0	= IOMUX_PAD(0x0590, 0x01C0, 1, 0x0000, 0, 0),
-	MX6_PAD_EIM_DA9__IPU1_CSI1_D_0		= IOMUX_PAD(0x0590, 0x01C0, 2, 0x0000, 0, 0),
-	MX6_PAD_EIM_DA9__MIPI_CORE_DPHY_TEST_OUT_11	= IOMUX_PAD(0x0590, 0x01C0, 3, 0x0000, 0, 0),
-	MX6_PAD_EIM_DA9__GPIO_3_9		= IOMUX_PAD(0x0590, 0x01C0, 5, 0x0000, 0, 0),
-	MX6_PAD_EIM_DA9__TPSMP_HDATA_23		= IOMUX_PAD(0x0590, 0x01C0, 6, 0x0000, 0, 0),
-	MX6_PAD_EIM_DA9__SRC_BT_CFG_9		= IOMUX_PAD(0x0590, 0x01C0, 7, 0x0000, 0, 0),
-	MX6_PAD_EIM_DA9__EPDC_SDCE_5		= IOMUX_PAD(0x0590, 0x01C0, 8, 0x0000, 0, 0),
-	MX6_PAD_EIM_EB0__WEIM_WEIM_EB_0		= IOMUX_PAD(0x0594, 0x01C4, 0, 0x0000, 0, 0),
-	MX6_PAD_EIM_EB0__IPU1_DISP1_DAT_11	= IOMUX_PAD(0x0594, 0x01C4, 1, 0x0000, 0, 0),
-	MX6_PAD_EIM_EB0__IPU1_CSI1_D_11		= IOMUX_PAD(0x0594, 0x01C4, 2, 0x088C, 1, 0),
-	MX6_PAD_EIM_EB0__MIPI_CORE_DPHY_TEST_OUT_0	= IOMUX_PAD(0x0594, 0x01C4, 3, 0x0000, 0, 0),
-	MX6_PAD_EIM_EB0__CCM_PMIC_RDY		= IOMUX_PAD(0x0594, 0x01C4, 4, 0x07D4, 0, 0),
-	MX6_PAD_EIM_EB0__GPIO_2_28		= IOMUX_PAD(0x0594, 0x01C4, 5, 0x0000, 0, 0),
-	MX6_PAD_EIM_EB0__TPSMP_HDATA_12		= IOMUX_PAD(0x0594, 0x01C4, 6, 0x0000, 0, 0),
-	MX6_PAD_EIM_EB0__SRC_BT_CFG_27		= IOMUX_PAD(0x0594, 0x01C4, 7, 0x0000, 0, 0),
-	MX6_PAD_EIM_EB0__EPDC_PWRCOM		= IOMUX_PAD(0x0594, 0x01C4, 8, 0x0000, 0, 0),
-	MX6_PAD_EIM_EB1__WEIM_WEIM_EB_1		= IOMUX_PAD(0x0598, 0x01C8, 0, 0x0000, 0, 0),
-	MX6_PAD_EIM_EB1__IPU1_DISP1_DAT_10	= IOMUX_PAD(0x0598, 0x01C8, 1, 0x0000, 0, 0),
-	MX6_PAD_EIM_EB1__IPU1_CSI1_D_10		= IOMUX_PAD(0x0598, 0x01C8, 2, 0x0888, 1, 0),
-	MX6_PAD_EIM_EB1__MIPI_CORE_DPHY_TEST_OUT_1	= IOMUX_PAD(0x0598, 0x01C8, 3, 0x0000, 0, 0),
-	MX6_PAD_EIM_EB1__GPIO_2_29		= IOMUX_PAD(0x0598, 0x01C8, 5, 0x0000, 0, 0),
-	MX6_PAD_EIM_EB1__TPSMP_HDATA_13		= IOMUX_PAD(0x0598, 0x01C8, 6, 0x0000, 0, 0),
-	MX6_PAD_EIM_EB1__SRC_BT_CFG_28		= IOMUX_PAD(0x0598, 0x01C8, 7, 0x0000, 0, 0),
-	MX6_PAD_EIM_EB1__EPDC_SDSHR		= IOMUX_PAD(0x0598, 0x01C8, 8, 0x0000, 0, 0),
-	MX6_PAD_EIM_EB2__WEIM_WEIM_EB_2		= IOMUX_PAD(0x059C, 0x01CC, 0, 0x0000, 0, 0),
-	MX6_PAD_EIM_EB2__ECSPI1_SS0		= IOMUX_PAD(0x059C, 0x01CC, 1, 0x07E4, 2, 0),
-	MX6_PAD_EIM_EB2__CCM_DI1_EXT_CLK	= IOMUX_PAD(0x059C, 0x01CC, 2, 0x07D0, 1, 0),
-	MX6_PAD_EIM_EB2__IPU1_CSI1_D_19		= IOMUX_PAD(0x059C, 0x01CC, 3, 0x08AC, 1, 0),
-	MX6_PAD_EIM_EB2__HDMI_TX_DDC_SCL	= IOMUX_PAD(0x059C, 0x01CC, 4, 0x0860, 0, 0),
-	MX6_PAD_EIM_EB2__GPIO_2_30		= IOMUX_PAD(0x059C, 0x01CC, 5, 0x0000, 0, 0),
-	MX6_PAD_EIM_EB2__I2C2_SCL		= IOMUX_PAD(0x059C, 0x01CC, 6 | IOMUX_CONFIG_SION, 0x0870, 0, 0),
-	MX6_PAD_EIM_EB2__SRC_BT_CFG_30		= IOMUX_PAD(0x059C, 0x01CC, 7, 0x0000, 0, 0),
-	MX6_PAD_EIM_EB2__EPDC_SDDO_5		= IOMUX_PAD(0x059C, 0x01CC, 8, 0x0000, 0, 0),
-	MX6_PAD_EIM_EB3__WEIM_WEIM_EB_3		= IOMUX_PAD(0x05A0, 0x01D0, 0, 0x0000, 0, 0),
-	MX6_PAD_EIM_EB3__ECSPI4_RDY		= IOMUX_PAD(0x05A0, 0x01D0, 1, 0x0000, 0, 0),
-	MX6_PAD_EIM_EB3__UART3_CTS		= IOMUX_PAD(0x05A0, 0x01D0, 2, 0x0000, 0, 0),
-	MX6_PAD_EIM_EB3__UART3_RTS		= IOMUX_PAD(0x05A0, 0x01D0, 2, 0x0908, 3, 0),
-	MX6_PAD_EIM_EB3__UART1_RI		= IOMUX_PAD(0x05A0, 0x01D0, 3, 0x0000, 0, 0),
-	MX6_PAD_EIM_EB3__IPU1_CSI1_HSYNC	= IOMUX_PAD(0x05A0, 0x01D0, 4, 0x08B4, 1, 0),
-	MX6_PAD_EIM_EB3__GPIO_2_31		= IOMUX_PAD(0x05A0, 0x01D0, 5, 0x0000, 0, 0),
-	MX6_PAD_EIM_EB3__IPU1_DI1_PIN3		= IOMUX_PAD(0x05A0, 0x01D0, 6, 0x0000, 0, 0),
-	MX6_PAD_EIM_EB3__SRC_BT_CFG_31		= IOMUX_PAD(0x05A0, 0x01D0, 7, 0x0000, 0, 0),
-	MX6_PAD_EIM_EB3__EPDC_SDCE_0		= IOMUX_PAD(0x05A0, 0x01D0, 8, 0x0000, 0, 0),
-	MX6_PAD_EIM_EB3__WEIM_ACLK_FREERUN	= IOMUX_PAD(0x05A0, 0x01D0, 9, 0x0000, 0, 0),
-	MX6_PAD_EIM_LBA__WEIM_WEIM_LBA		= IOMUX_PAD(0x05A4, 0x01D4, 0, 0x0000, 0, 0),
-	MX6_PAD_EIM_LBA__IPU1_DI1_PIN17		= IOMUX_PAD(0x05A4, 0x01D4, 1, 0x0000, 0, 0),
-	MX6_PAD_EIM_LBA__ECSPI2_SS1		= IOMUX_PAD(0x05A4, 0x01D4, 2, 0x0804, 1, 0),
-	MX6_PAD_EIM_LBA__GPIO_2_27		= IOMUX_PAD(0x05A4, 0x01D4, 5, 0x0000, 0, 0),
-	MX6_PAD_EIM_LBA__TPSMP_HDATA_11		= IOMUX_PAD(0x05A4, 0x01D4, 6, 0x0000, 0, 0),
-	MX6_PAD_EIM_LBA__SRC_BT_CFG_26		= IOMUX_PAD(0x05A4, 0x01D4, 7, 0x0000, 0, 0),
-	MX6_PAD_EIM_LBA__EPDC_SDDO_4		= IOMUX_PAD(0x05A4, 0x01D4, 8, 0x0000, 0, 0),
-	MX6_PAD_EIM_OE__WEIM_WEIM_OE		= IOMUX_PAD(0x05A8, 0x01D8, 0, 0x0000, 0, 0),
-	MX6_PAD_EIM_OE__IPU1_DI1_PIN7		= IOMUX_PAD(0x05A8, 0x01D8, 1, 0x0000, 0, 0),
-	MX6_PAD_EIM_OE__ECSPI2_MISO		= IOMUX_PAD(0x05A8, 0x01D8, 2, 0x07F8, 2, 0),
-	MX6_PAD_EIM_OE__MIPI_CORE_DPHY_TEST_OUT_26	= IOMUX_PAD(0x05A8, 0x01D8, 4, 0x0000, 0, 0),
-	MX6_PAD_EIM_OE__GPIO_2_25		= IOMUX_PAD(0x05A8, 0x01D8, 5, 0x0000, 0, 0),
-	MX6_PAD_EIM_OE__TPSMP_HDATA_9		= IOMUX_PAD(0x05A8, 0x01D8, 6, 0x0000, 0, 0),
-	MX6_PAD_EIM_OE__EPDC_PWRIRQ		= IOMUX_PAD(0x05A8, 0x01D8, 8, 0x0000, 0, 0),
-	MX6_PAD_EIM_RW__WEIM_WEIM_RW		= IOMUX_PAD(0x05AC, 0x01DC, 0, 0x0000, 0, 0),
-	MX6_PAD_EIM_RW__IPU1_DI1_PIN8		= IOMUX_PAD(0x05AC, 0x01DC, 1, 0x0000, 0, 0),
-	MX6_PAD_EIM_RW__ECSPI2_SS0		= IOMUX_PAD(0x05AC, 0x01DC, 2, 0x0800, 2, 0),
-	MX6_PAD_EIM_RW__MIPI_CORE_DPHY_TEST_OUT_27	= IOMUX_PAD(0x05AC, 0x01DC, 4, 0x0000, 0, 0),
-	MX6_PAD_EIM_RW__GPIO_2_26		= IOMUX_PAD(0x05AC, 0x01DC, 5, 0x0000, 0, 0),
-	MX6_PAD_EIM_RW__TPSMP_HDATA_10		= IOMUX_PAD(0x05AC, 0x01DC, 6, 0x0000, 0, 0),
-	MX6_PAD_EIM_RW__SRC_BT_CFG_29		= IOMUX_PAD(0x05AC, 0x01DC, 7, 0x0000, 0, 0),
-	MX6_PAD_EIM_RW__EPDC_SDDO_7		= IOMUX_PAD(0x05AC, 0x01DC, 8, 0x0000, 0, 0),
-	MX6_PAD_EIM_WAIT__WEIM_WEIM_WAIT	= IOMUX_PAD(0x05B0, 0x01E0, 0, 0x0000, 0, 0),
-	MX6_PAD_EIM_WAIT__WEIM_WEIM_DTACK_B	= IOMUX_PAD(0x05B0, 0x01E0, 1, 0x0000, 0, 0),
-	MX6_PAD_EIM_WAIT__GPIO_5_0		= IOMUX_PAD(0x05B0, 0x01E0, 5, 0x0000, 0, 0),
-	MX6_PAD_EIM_WAIT__TPSMP_HDATA_30	= IOMUX_PAD(0x05B0, 0x01E0, 6, 0x0000, 0, 0),
-	MX6_PAD_EIM_WAIT__SRC_BT_CFG_25		= IOMUX_PAD(0x05B0, 0x01E0, 7, 0x0000, 0, 0),
-	MX6_PAD_ENET_CRS_DV__ENET_RX_EN		= IOMUX_PAD(0x05B4, 0x01E4, 1, 0x0828, 0, 0),
-	MX6_PAD_ENET_CRS_DV__ESAI1_SCKT		= IOMUX_PAD(0x05B4, 0x01E4, 2, 0x0840, 0, 0),
-	MX6_PAD_ENET_CRS_DV__SPDIF_SPDIF_EXTCLK	= IOMUX_PAD(0x05B4, 0x01E4, 3, 0x08F4, 0, 0),
-	MX6_PAD_ENET_CRS_DV__GPIO_1_25		= IOMUX_PAD(0x05B4, 0x01E4, 5, 0x0000, 0, 0),
-	MX6_PAD_ENET_CRS_DV__PHY_TDO		= IOMUX_PAD(0x05B4, 0x01E4, 6, 0x0000, 0, 0),
-	MX6_PAD_ENET_CRS_DV__ANATOP_USBPHY1_TSTO_RX_FS_RXD	= IOMUX_PAD(0x05B4, 0x01E4, 7, 0x0000, 0, 0),
-	MX6_PAD_ENET_MDC__MLB_MLBDAT		= IOMUX_PAD(0x05B8, 0x01E8, 0, 0x08E0, 0, 0),
-	MX6_PAD_ENET_MDC__ENET_MDC		= IOMUX_PAD(0x05B8, 0x01E8, 1, 0x0000, 0,  0),
-	MX6_PAD_ENET_MDC__ESAI1_TX5_RX0		= IOMUX_PAD(0x05B8, 0x01E8, 2, 0x0858, 0, 0),
-	MX6_PAD_ENET_MDC__ENET_1588_EVENT1_IN	= IOMUX_PAD(0x05B8, 0x01E8, 4, 0x0000, 0, 0),
-	MX6_PAD_ENET_MDC__GPIO_1_31		= IOMUX_PAD(0x05B8, 0x01E8, 5, 0x0000, 0, 0),
-	MX6_PAD_ENET_MDC__ANATOP_USBPHY2_TSTO_RX_DISCON_DET	= IOMUX_PAD(0x05B8, 0x01E8, 7, 0x0000, 0, 0),
-	MX6_PAD_ENET_MDIO__ENET_MDIO		= IOMUX_PAD(0x05BC, 0x01EC, 1, 0x0810, 0, 0),
-	MX6_PAD_ENET_MDIO__ESAI1_SCKR		= IOMUX_PAD(0x05BC, 0x01EC, 2, 0x083C, 0, 0),
-	MX6_PAD_ENET_MDIO__SDMA_DEBUG_BUS_DEVICE_3	= IOMUX_PAD(0x05BC, 0x01EC, 3, 0x0000, 0, 0),
-	MX6_PAD_ENET_MDIO__ENET_1588_EVENT1_OUT	= IOMUX_PAD(0x05BC, 0x01EC, 4, 0x0000, 0, 0),
-	MX6_PAD_ENET_MDIO__GPIO_1_22		= IOMUX_PAD(0x05BC, 0x01EC, 5, 0x0000, 0, 0),
-	MX6_PAD_ENET_MDIO__SPDIF_PLOCK		= IOMUX_PAD(0x05BC, 0x01EC, 6, 0x0000, 0, 0),
-	MX6_PAD_ENET_REF_CLK__ENET_TX_CLK	= IOMUX_PAD(0x05C0, 0x01F0, 1, 0x0000, 0, 0),
-	MX6_PAD_ENET_REF_CLK__ESAI1_FSR		= IOMUX_PAD(0x05C0, 0x01F0, 2, 0x082C, 0, 0),
-	MX6_PAD_ENET_REF_CLK__SDMA_DEBUG_BUS_DEVICE_4	= IOMUX_PAD(0x05C0, 0x01F0, 3, 0x0000, 0, 0),
-	MX6_PAD_ENET_REF_CLK__GPIO_1_23		= IOMUX_PAD(0x05C0, 0x01F0, 5, 0x0000, 0, 0),
-	MX6_PAD_ENET_REF_CLK__SPDIF_SRCLK	= IOMUX_PAD(0x05C0, 0x01F0, 6, 0x0000, 0, 0),
-	MX6_PAD_ENET_REF_CLK__ANATOP_USBPHY1_TSTO_RX_SQUELCH	= IOMUX_PAD(0x05C0, 0x01F0, 7, 0x0000, 0, 0),
-	MX6_PAD_ENET_RX_ER__ANATOP_USBOTG_ID	= IOMUX_PAD(0x05C4, 0x01F4, 0, 0x0790, 0, 0),
-	MX6_PAD_ENET_RX_ER__ENET_RX_ER		= IOMUX_PAD(0x05C4, 0x01F4, 1, 0x0000, 0, 0),
-	MX6_PAD_ENET_RX_ER__ESAI1_HCKR		= IOMUX_PAD(0x05C4, 0x01F4, 2, 0x0834, 0, 0),
-	MX6_PAD_ENET_RX_ER__SPDIF_IN1		= IOMUX_PAD(0x05C4, 0x01F4, 3, 0x08F0, 1, 0),
-	MX6_PAD_ENET_RX_ER__ENET_1588_EVENT2_OUT	= IOMUX_PAD(0x05C4, 0x01F4, 4, 0x0000, 0, 0),
-	MX6_PAD_ENET_RX_ER__GPIO_1_24		= IOMUX_PAD(0x05C4, 0x01F4, 5, 0x0000, 0, 0),
-	MX6_PAD_ENET_RX_ER__PHY_TDI		= IOMUX_PAD(0x05C4, 0x01F4, 6, 0x0000, 0, 0),
-	MX6_PAD_ENET_RX_ER__ANATOP_USBPHY1_TSTO_RX_HS_RXD	= IOMUX_PAD(0x05C4, 0x01F4, 7, 0x0000, 0, 0),
-	MX6_PAD_ENET_RXD0__OSC32K_32K_OUT	= IOMUX_PAD(0x05C8, 0x01F8, 0, 0x0000, 0, 0),
-	MX6_PAD_ENET_RXD0__ENET_RDATA_0		= IOMUX_PAD(0x05C8, 0x01F8, 1, 0x0818, 0, 0),
-	MX6_PAD_ENET_RXD0__ESAI1_HCKT		= IOMUX_PAD(0x05C8, 0x01F8, 2, 0x0838, 0, 0),
-	MX6_PAD_ENET_RXD0__SPDIF_OUT1		= IOMUX_PAD(0x05C8, 0x01F8, 3, 0x0000, 0, 0),
-	MX6_PAD_ENET_RXD0__GPIO_1_27		= IOMUX_PAD(0x05C8, 0x01F8, 5, 0x0000, 0, 0),
-	MX6_PAD_ENET_RXD0__PHY_TMS		= IOMUX_PAD(0x05C8, 0x01F8, 6, 0x0000, 0, 0),
-	MX6_PAD_ENET_RXD0__ANATOP_USBPHY1_TSTO_PLL_CLK20DIV	= IOMUX_PAD(0x05C8, 0x01F8, 7, 0x0000, 0, 0),
-	MX6_PAD_ENET_RXD1__MLB_MLBSIG		= IOMUX_PAD(0x05CC, 0x01FC, 0, 0x08E4, 0, 0),
-	MX6_PAD_ENET_RXD1__ENET_RDATA_1		= IOMUX_PAD(0x05CC, 0x01FC, 1, 0x081C, 0, 0),
-	MX6_PAD_ENET_RXD1__ESAI1_FST		= IOMUX_PAD(0x05CC, 0x01FC, 2, 0x0830, 0, 0),
-	MX6_PAD_ENET_RXD1__ENET_1588_EVENT3_OUT	= IOMUX_PAD(0x05CC, 0x01FC, 4, 0x0000, 0, 0),
-	MX6_PAD_ENET_RXD1__GPIO_1_26		= IOMUX_PAD(0x05CC, 0x01FC, 5, 0x0000, 0, 0),
-	MX6_PAD_ENET_RXD1__PHY_TCK		= IOMUX_PAD(0x05CC, 0x01FC, 6, 0x0000, 0, 0),
-	MX6_PAD_ENET_RXD1__ANATOP_USBPHY1_TSTO_RX_DISCON_DET	= IOMUX_PAD(0x05CC, 0x01FC, 7, 0x0000, 0, 0),
-	MX6_PAD_ENET_TX_EN__ENET_TX_EN		= IOMUX_PAD(0x05D0, 0x0200, 1, 0x0000, 0, 0),
-	MX6_PAD_ENET_TX_EN__ESAI1_TX3_RX2	= IOMUX_PAD(0x05D0, 0x0200, 2, 0x0850, 0, 0),
-	MX6_PAD_ENET_TX_EN__GPIO_1_28		= IOMUX_PAD(0x05D0, 0x0200, 5, 0x0000, 0, 0),
-	MX6_PAD_ENET_TX_EN__ANATOP_USBPHY2_TSTO_RX_SQUELCH	= IOMUX_PAD(0x05D0, 0x0200, 7, 0x0000, 0, 0),
-	MX6_PAD_ENET_TX_EN__I2C4_SCL		= IOMUX_PAD(0x05D0, 0x0200, 9 | IOMUX_CONFIG_SION, 0x0880, 0, 0),
-	MX6_PAD_ENET_TXD0__ENET_TDATA_0		= IOMUX_PAD(0x05D4, 0x0204, 1, 0x0000, 0, 0),
-	MX6_PAD_ENET_TXD0__ESAI1_TX4_RX1	= IOMUX_PAD(0x05D4, 0x0204, 2, 0x0854, 0, 0),
-	MX6_PAD_ENET_TXD0__GPIO_1_30		= IOMUX_PAD(0x05D4, 0x0204, 5, 0x0000, 0, 0),
-	MX6_PAD_ENET_TXD0__ANATOP_USBPHY2_TSTO_RX_FS_RXD	= IOMUX_PAD(0x05D4, 0x0204, 7, 0x0000, 0, 0),
-	MX6_PAD_ENET_TXD1__MLB_MLBCLK		= IOMUX_PAD(0x05D8, 0x0208, 0, 0x08DC, 0, 0),
-	MX6_PAD_ENET_TXD1__ENET_TDATA_1		= IOMUX_PAD(0x05D8, 0x0208, 1, 0x0000, 0, 0),
-	MX6_PAD_ENET_TXD1__ESAI1_TX2_RX3	= IOMUX_PAD(0x05D8, 0x0208, 2, 0x084C, 0, 0),
-	MX6_PAD_ENET_TXD1__ENET_1588_EVENT0_IN	= IOMUX_PAD(0x05D8, 0x0208, 4, 0x0000, 0, 0),
-	MX6_PAD_ENET_TXD1__GPIO_1_29		= IOMUX_PAD(0x05D8, 0x0208, 5, 0x0000, 0, 0),
-	MX6_PAD_ENET_TXD1__ANATOP_USBPHY2_TSTO_RX_HS_RXD	= IOMUX_PAD(0x05D8, 0x0208, 7, 0x0000, 0, 0),
-	MX6_PAD_ENET_TXD1__I2C4_SDA		= IOMUX_PAD(0x05D8, 0x0208, 9 | IOMUX_CONFIG_SION, 0x0884, 0, 0),
-	MX6_PAD_GPIO_0__CCM_CLKO		= IOMUX_PAD(0x05DC, 0x020C, 0, 0x0000, 0, 0),
-	MX6_PAD_GPIO_0__KPP_COL_5		= IOMUX_PAD(0x05DC, 0x020C, 2, 0x08C0, 1, 0),
-	MX6_PAD_GPIO_0__ASRC_ASRC_EXT_CLK	= IOMUX_PAD(0x05DC, 0x020C, 3, 0x0794, 0, 0),
-	MX6_PAD_GPIO_0__EPIT1_EPITO		= IOMUX_PAD(0x05DC, 0x020C, 4, 0x0000, 0, 0),
-	MX6_PAD_GPIO_0__GPIO_1_0		= IOMUX_PAD(0x05DC, 0x020C, 5, 0x0000, 0, 0),
-	MX6_PAD_GPIO_0__USBOH3_USBH1_PWR	= IOMUX_PAD(0x05DC, 0x020C, 6, 0x0000, 0, 0),
-	MX6_PAD_GPIO_0__SNVS_HP_WRAPPER_SNVS_VIO_5	= IOMUX_PAD(0x05DC, 0x020C, 7, 0x0000, 0, 0),
-	MX6_PAD_GPIO_1__ESAI1_SCKR		= IOMUX_PAD(0x05E0, 0x0210, 0, 0x083C, 1, 0),
-	MX6_PAD_GPIO_1__WDOG2_WDOG_B		= IOMUX_PAD(0x05E0, 0x0210, 1, 0x0000, 0, 0),
-	MX6_PAD_GPIO_1__KPP_ROW_5		= IOMUX_PAD(0x05E0, 0x0210, 2, 0x08CC, 1, 0),
-	MX6_PAD_GPIO_1__USB_OTG_ID		= IOMUX_PAD(0x05E0, 0x0210, 3, 0x0790, 1, 0),
-	MX6_PAD_GPIO_1__PWM2_PWMO		= IOMUX_PAD(0x05E0, 0x0210, 4, 0x0000, 0, 0),
-	MX6_PAD_GPIO_1__GPIO_1_1		= IOMUX_PAD(0x05E0, 0x0210, 5, 0x0000, 0, 0),
-	MX6_PAD_GPIO_1__USDHC1_CD		= IOMUX_PAD(0x05E0, 0x0210, 6, 0x0000, 0, 0),
-	MX6_PAD_GPIO_1__SRC_TESTER_ACK		= IOMUX_PAD(0x05E0, 0x0210, 7, 0x0000, 0, 0),
-	MX6_PAD_GPIO_16__ESAI1_TX3_RX2		= IOMUX_PAD(0x05E4, 0x0214, 0, 0x0850, 1, 0),
-	MX6_PAD_GPIO_16__ENET_1588_EVENT2_IN	= IOMUX_PAD(0x05E4, 0x0214, 1, 0x0000, 0, 0),
-	MX6_PAD_GPIO_16__ENET_ANATOP_ETHERNET_REF_OUT	= IOMUX_PAD(0x05E4, 0x0214, 2, 0x080C, 0, 0),
-	MX6_PAD_GPIO_16__USDHC1_LCTL		= IOMUX_PAD(0x05E4, 0x0214, 3, 0x0000, 0, 0),
-	MX6_PAD_GPIO_16__SPDIF_IN1		= IOMUX_PAD(0x05E4, 0x0214, 4, 0x08F0, 2, 0),
-	MX6_PAD_GPIO_16__GPIO_7_11		= IOMUX_PAD(0x05E4, 0x0214, 5, 0x0000, 0, 0),
-	MX6_PAD_GPIO_16__I2C3_SDA		= IOMUX_PAD(0x05E4, 0x0214, 6 | IOMUX_CONFIG_SION, 0x087C, 1, 0),
-	MX6_PAD_GPIO_16__SJC_DE_B		= IOMUX_PAD(0x05E4, 0x0214, 7, 0x0000, 0, 0),
-	MX6_PAD_GPIO_17__ESAI1_TX0		= IOMUX_PAD(0x05E8, 0x0218, 0, 0x0844, 0, 0),
-	MX6_PAD_GPIO_17__ENET_1588_EVENT3_IN	= IOMUX_PAD(0x05E8, 0x0218, 1, 0x0000, 0, 0),
-	MX6_PAD_GPIO_17__CCM_PMIC_RDY		= IOMUX_PAD(0x05E8, 0x0218, 2, 0x07D4, 1, 0),
-	MX6_PAD_GPIO_17__SDMA_SDMA_EXT_EVENT_0	= IOMUX_PAD(0x05E8, 0x0218, 3, 0x08E8, 1, 0),
-	MX6_PAD_GPIO_17__SPDIF_OUT1		= IOMUX_PAD(0x05E8, 0x0218, 4, 0x0000, 0, 0),
-	MX6_PAD_GPIO_17__GPIO_7_12		= IOMUX_PAD(0x05E8, 0x0218, 5, 0x0000, 0, 0),
-	MX6_PAD_GPIO_17__SJC_JTAG_ACT		= IOMUX_PAD(0x05E8, 0x0218, 7, 0x0000, 0, 0),
-	MX6_PAD_GPIO_18__ESAI1_TX1		= IOMUX_PAD(0x05EC, 0x021C, 0, 0x0848, 0, 0),
-	MX6_PAD_GPIO_18__ENET_RX_CLK		= IOMUX_PAD(0x05EC, 0x021C, 1, 0x0814, 0, 0),
-	MX6_PAD_GPIO_18__USDHC3_VSELECT		= IOMUX_PAD(0x05EC, 0x021C, 2, 0x0000, 0, 0),
-	MX6_PAD_GPIO_18__SDMA_SDMA_EXT_EVENT_1	= IOMUX_PAD(0x05EC, 0x021C, 3, 0x08EC, 1, 0),
-	MX6_PAD_GPIO_18__ASRC_ASRC_EXT_CLK	= IOMUX_PAD(0x05EC, 0x021C, 4, 0x0794, 1, 0),
-	MX6_PAD_GPIO_18__GPIO_7_13		= IOMUX_PAD(0x05EC, 0x021C, 5, 0x0000, 0, 0),
-	MX6_PAD_GPIO_18__SNVS_HP_WRAPPER_SNVS_VIO_5_CTL	= IOMUX_PAD(0x05EC, 0x021C, 6, 0x0000, 0, 0),
-	MX6_PAD_GPIO_18__SRC_SYSTEM_RST		= IOMUX_PAD(0x05EC, 0x021C, 7, 0x0000, 0, 0),
-	MX6_PAD_GPIO_19__KPP_COL_5		= IOMUX_PAD(0x05F0, 0x0220, 0, 0x08C0, 2, 0),
-	MX6_PAD_GPIO_19__ENET_1588_EVENT0_OUT	= IOMUX_PAD(0x05F0, 0x0220, 1, 0x0000, 0, 0),
-	MX6_PAD_GPIO_19__SPDIF_OUT1		= IOMUX_PAD(0x05F0, 0x0220, 2, 0x0000, 0, 0),
-	MX6_PAD_GPIO_19__CCM_CLKO		= IOMUX_PAD(0x05F0, 0x0220, 3, 0x0000, 0, 0),
-	MX6_PAD_GPIO_19__ECSPI1_RDY		= IOMUX_PAD(0x05F0, 0x0220, 4, 0x0000, 0, 0),
-	MX6_PAD_GPIO_19__GPIO_4_5		= IOMUX_PAD(0x05F0, 0x0220, 5, 0x0000, 0, 0),
-	MX6_PAD_GPIO_19__ENET_TX_ER		= IOMUX_PAD(0x05F0, 0x0220, 6, 0x0000, 0, 0),
-	MX6_PAD_GPIO_19__SRC_INT_BOOT		= IOMUX_PAD(0x05F0, 0x0220, 7, 0x0000, 0, 0),
-	MX6_PAD_GPIO_2__ESAI1_FST		= IOMUX_PAD(0x05F4, 0x0224, 0, 0x0830, 1, 0),
-	MX6_PAD_GPIO_2__OBSERVE_MUX_OBSRV_INT_OUT2	= IOMUX_PAD(0x05F4, 0x0224, 1, 0x0000, 0, 0),
-	MX6_PAD_GPIO_2__KPP_ROW_6		= IOMUX_PAD(0x05F4, 0x0224, 2, 0x08D0, 1, 0),
-	MX6_PAD_GPIO_2__CCM_CCM_OUT_1		= IOMUX_PAD(0x05F4, 0x0224, 3, 0x0000, 0, 0),
-	MX6_PAD_GPIO_2__CSU_CSU_ALARM_AUT_0	= IOMUX_PAD(0x05F4, 0x0224, 4, 0x0000, 0, 0),
-	MX6_PAD_GPIO_2__GPIO_1_2		= IOMUX_PAD(0x05F4, 0x0224, 5, 0x0000, 0, 0),
-	MX6_PAD_GPIO_2__USDHC2_WP		= IOMUX_PAD(0x05F4, 0x0224, 6, 0x0000, 0, 0),
-	MX6_PAD_GPIO_2__MLB_MLBDAT		= IOMUX_PAD(0x05F4, 0x0224, 7, 0x08E0, 1, 0),
-	MX6_PAD_GPIO_3__ESAI1_HCKR		= IOMUX_PAD(0x05F8, 0x0228, 0, 0x0834, 1, 0),
-	MX6_PAD_GPIO_3__OBSERVE_MUX_OBSRV_INT_OUT0	= IOMUX_PAD(0x05F8, 0x0228, 1, 0x0000, 0, 0),
-	MX6_PAD_GPIO_3__I2C3_SCL		= IOMUX_PAD(0x05F8, 0x0228, 2 | IOMUX_CONFIG_SION, 0x0878, 1, 0),
-	MX6_PAD_GPIO_3__ANATOP_ANATOP_24M_OUT	= IOMUX_PAD(0x05F8, 0x0228, 3, 0x0000, 0, 0),
-	MX6_PAD_GPIO_3__CCM_CLKO2		= IOMUX_PAD(0x05F8, 0x0228, 4, 0x0000, 0, 0),
-	MX6_PAD_GPIO_3__GPIO_1_3		= IOMUX_PAD(0x05F8, 0x0228, 5, 0x0000, 0, 0),
-	MX6_PAD_GPIO_3__USBOH3_USBH1_OC		= IOMUX_PAD(0x05F8, 0x0228, 6, 0x0924, 1, 0),
-	MX6_PAD_GPIO_3__MLB_MLBCLK		= IOMUX_PAD(0x05F8, 0x0228, 7, 0x08DC, 1, 0),
-	MX6_PAD_GPIO_4__ESAI1_HCKT		= IOMUX_PAD(0x05FC, 0x022C, 0, 0x0838, 1, 0),
-	MX6_PAD_GPIO_4__OBSERVE_MUX_OBSRV_INT_OUT3	= IOMUX_PAD(0x05FC, 0x022C, 1, 0x0000, 0, 0),
-	MX6_PAD_GPIO_4__KPP_COL_7		= IOMUX_PAD(0x05FC, 0x022C, 2, 0x08C8, 1, 0),
-	MX6_PAD_GPIO_4__CCM_CCM_OUT_2		= IOMUX_PAD(0x05FC, 0x022C, 3, 0x0000, 0, 0),
-	MX6_PAD_GPIO_4__CSU_CSU_ALARM_AUT_1	= IOMUX_PAD(0x05FC, 0x022C, 4, 0x0000, 0, 0),
-	MX6_PAD_GPIO_4__GPIO_1_4		= IOMUX_PAD(0x05FC, 0x022C, 5, 0x0000, 0, 0),
-	MX6_PAD_GPIO_4__USDHC2_CD		= IOMUX_PAD(0x05FC, 0x022C, 6, 0x0000, 0, 0),
-	MX6_PAD_GPIO_4__OCOTP_CTRL_WRAPPER_FUSE_LATCHED	= IOMUX_PAD(0x05FC, 0x022C, 7, 0x0000, 0, 0),
-	MX6_PAD_GPIO_5__ESAI1_TX2_RX3		= IOMUX_PAD(0x0600, 0x0230, 0, 0x084C, 1, 0),
-	MX6_PAD_GPIO_5__OBSERVE_MUX_OBSRV_INT_OUT4	= IOMUX_PAD(0x0600, 0x0230, 1, 0x0000, 0, 0),
-	MX6_PAD_GPIO_5__KPP_ROW_7		= IOMUX_PAD(0x0600, 0x0230, 2, 0x08D4, 1, 0),
-	MX6_PAD_GPIO_5__CCM_CLKO		= IOMUX_PAD(0x0600, 0x0230, 3, 0x0000, 0, 0),
-	MX6_PAD_GPIO_5__CSU_CSU_ALARM_AUT_2	= IOMUX_PAD(0x0600, 0x0230, 4, 0x0000, 0, 0),
-	MX6_PAD_GPIO_5__GPIO_1_5		= IOMUX_PAD(0x0600, 0x0230, 5, 0x0000, 0, 0),
-	MX6_PAD_GPIO_5__I2C3_SCL		= IOMUX_PAD(0x0600, 0x0230, 6 | IOMUX_CONFIG_SION, 0x0878, 2, 0),
-	MX6_PAD_GPIO_5__SIMBA_EVENTI		= IOMUX_PAD(0x0600, 0x0230, 7, 0x0000, 0, 0),
-	MX6_PAD_GPIO_6__ESAI1_SCKT		= IOMUX_PAD(0x0604, 0x0234, 0, 0x0840, 1, 0),
-	MX6_PAD_GPIO_6__OBSERVE_MUX_OBSRV_INT_OUT1	= IOMUX_PAD(0x0604, 0x0234, 1, 0x0000, 0, 0),
-	MX6_PAD_GPIO_6__I2C3_SDA		= IOMUX_PAD(0x0604, 0x0234, 2 | IOMUX_CONFIG_SION, 0x087C, 2, 0),
-	MX6_PAD_GPIO_6__CCM_CCM_OUT_0		= IOMUX_PAD(0x0604, 0x0234, 3, 0x0000, 0, 0),
-	MX6_PAD_GPIO_6__CSU_CSU_INT_DEB		= IOMUX_PAD(0x0604, 0x0234, 4, 0x0000, 0, 0),
-	MX6_PAD_GPIO_6__GPIO_1_6		= IOMUX_PAD(0x0604, 0x0234, 5, 0x0000, 0, 0),
-	MX6_PAD_GPIO_6__USDHC2_LCTL		= IOMUX_PAD(0x0604, 0x0234, 6, 0x0000, 0, 0),
-	MX6_PAD_GPIO_6__MLB_MLBSIG		= IOMUX_PAD(0x0604, 0x0234, 7, 0x08E4, 1, 0),
-	MX6_PAD_GPIO_7__ESAI1_TX4_RX1		= IOMUX_PAD(0x0608, 0x0238, 0, 0x0854, 1, 0),
-	MX6_PAD_GPIO_7__EPIT1_EPITO		= IOMUX_PAD(0x0608, 0x0238, 2, 0x0000, 0, 0),
-	MX6_PAD_GPIO_7__CAN1_TXCAN		= IOMUX_PAD(0x0608, 0x0238, 3, 0x0000, 0, 0),
-	MX6_PAD_GPIO_7__UART2_TXD		= IOMUX_PAD(0x0608, 0x0238, 4, 0x0000, 0, 0),
-	MX6_PAD_GPIO_7__UART2_RXD		= IOMUX_PAD(0x0608, 0x0238, 4, 0x0904, 2, 0),
-	MX6_PAD_GPIO_7__GPIO_1_7		= IOMUX_PAD(0x0608, 0x0238, 5, 0x0000, 0, 0),
-	MX6_PAD_GPIO_7__SPDIF_PLOCK		= IOMUX_PAD(0x0608, 0x0238, 6, 0x0000, 0, 0),
-	MX6_PAD_GPIO_7__USBOH3_OTGUSB_HOST_MODE	= IOMUX_PAD(0x0608, 0x0238, 7, 0x0000, 0, 0),
-	MX6_PAD_GPIO_7__I2C4_SCL		= IOMUX_PAD(0x0608, 0x0238, 8 | IOMUX_CONFIG_SION, 0x0880, 1, 0),
-	MX6_PAD_GPIO_8__ESAI1_TX5_RX0		= IOMUX_PAD(0x060C, 0x023C, 0, 0x0858, 1, 0),
-	MX6_PAD_GPIO_8__ANATOP_ANATOP_32K_OUT	= IOMUX_PAD(0x060C, 0x023C, 1, 0x0000, 0, 0),
-	MX6_PAD_GPIO_8__EPIT2_EPITO		= IOMUX_PAD(0x060C, 0x023C, 2, 0x0000, 0, 0),
-	MX6_PAD_GPIO_8__CAN1_RXCAN		= IOMUX_PAD(0x060C, 0x023C, 3, 0x07C8, 0, 0),
-	MX6_PAD_GPIO_8__UART2_TXD		= IOMUX_PAD(0x060C, 0x023C, 4, 0x0000, 0, 0),
-	MX6_PAD_GPIO_8__UART2_RXD		= IOMUX_PAD(0x060C, 0x023C, 4, 0x0904, 3, 0),
-	MX6_PAD_GPIO_8__GPIO_1_8		= IOMUX_PAD(0x060C, 0x023C, 5, 0x0000, 0, 0),
-	MX6_PAD_GPIO_8__SPDIF_SRCLK		= IOMUX_PAD(0x060C, 0x023C, 6, 0x0000, 0, 0),
-	MX6_PAD_GPIO_8__USBOH3_OTGUSB_PWRCTL_WAKEUP	= IOMUX_PAD(0x060C, 0x023C, 7, 0x0000, 0, 0),
-	MX6_PAD_GPIO_8__I2C4_SDA		= IOMUX_PAD(0x060C, 0x023C, 8 | IOMUX_CONFIG_SION, 0x0884, 1, 0),
-	MX6_PAD_GPIO_9__ESAI1_FSR		= IOMUX_PAD(0x0610, 0x0240, 0, 0x082C, 1, 0),
-	MX6_PAD_GPIO_9__WDOG1_WDOG_B		= IOMUX_PAD(0x0610, 0x0240, 1, 0x0000, 0, 0),
-	MX6_PAD_GPIO_9__KPP_COL_6		= IOMUX_PAD(0x0610, 0x0240, 2, 0x08C4, 1, 0),
-	MX6_PAD_GPIO_9__CCM_REF_EN_B		= IOMUX_PAD(0x0610, 0x0240, 3, 0x0000, 0, 0),
-	MX6_PAD_GPIO_9__PWM1_PWMO		= IOMUX_PAD(0x0610, 0x0240, 4, 0x0000, 0, 0),
-	MX6_PAD_GPIO_9__GPIO_1_9		= IOMUX_PAD(0x0610, 0x0240, 5, 0x0000, 0, 0),
-	MX6_PAD_GPIO_9__USDHC1_WP		= IOMUX_PAD(0x0610, 0x0240, 6, 0x092C, 1, 0),
-	MX6_PAD_GPIO_9__SRC_EARLY_RST		= IOMUX_PAD(0x0610, 0x0240, 7, 0x0000, 0, 0),
-	MX6_PAD_JTAG_MOD__SJC_MOD		= IOMUX_PAD(0x0614, NO_MUX_I, 0, 0x0000, 0, 0),
-	MX6_PAD_JTAG_TCK__SJC_TCK		= IOMUX_PAD(0x0618, NO_MUX_I, 0, 0x0000, 0, 0),
-	MX6_PAD_JTAG_TDI__SJC_TDI		= IOMUX_PAD(0x061C, NO_MUX_I, 0, 0x0000, 0, 0),
-	MX6_PAD_JTAG_TDO__SJC_TDO		= IOMUX_PAD(0x0620, NO_MUX_I, 0, 0x0000, 0, 0),
-	MX6_PAD_JTAG_TMS__SJC_TMS		= IOMUX_PAD(0x0624, NO_MUX_I, 0, 0x0000, 0, 0),
-	MX6_PAD_JTAG_TRSTB__SJC_TRSTB		= IOMUX_PAD(0x0628, NO_MUX_I, 0, 0x0000, 0, 0),
-	MX6_PAD_KEY_COL0__ECSPI1_SCLK		= IOMUX_PAD(0x062C, 0x0244, 0, 0x07D8, 3, 0),
-	MX6_PAD_KEY_COL0__ENET_RDATA_3		= IOMUX_PAD(0x062C, 0x0244, 1, 0x0824, 0, 0),
-	MX6_PAD_KEY_COL0__AUDMUX_AUD5_TXC	= IOMUX_PAD(0x062C, 0x0244, 2, 0x07C0, 1, 0),
-	MX6_PAD_KEY_COL0__KPP_COL_0		= IOMUX_PAD(0x062C, 0x0244, 3, 0x0000, 0, 0),
-	MX6_PAD_KEY_COL0__UART4_TXD		= IOMUX_PAD(0x062C, 0x0244, 4, 0x0000, 0, 0),
-	MX6_PAD_KEY_COL0__UART4_RXD		= IOMUX_PAD(0x062C, 0x0244, 4, 0x0914, 2, 0),
-	MX6_PAD_KEY_COL0__GPIO_4_6		= IOMUX_PAD(0x062C, 0x0244, 5, 0x0000, 0, 0),
-	MX6_PAD_KEY_COL0__DCIC1_DCIC_OUT	= IOMUX_PAD(0x062C, 0x0244, 6, 0x0000, 0, 0),
-	MX6_PAD_KEY_COL0__SRC_ANY_PU_RST	= IOMUX_PAD(0x062C, 0x0244, 7, 0x0000, 0, 0),
-	MX6_PAD_KEY_COL1__ECSPI1_MISO		= IOMUX_PAD(0x0630, 0x0248, 0, 0x07DC, 3, 0),
-	MX6_PAD_KEY_COL1__ENET_MDIO		= IOMUX_PAD(0x0630, 0x0248, 1, 0x0810, 1, 0),
-	MX6_PAD_KEY_COL1__AUDMUX_AUD5_TXFS	= IOMUX_PAD(0x0630, 0x0248, 2, 0x07C4, 1, 0),
-	MX6_PAD_KEY_COL1__KPP_COL_1		= IOMUX_PAD(0x0630, 0x0248, 3, 0x0000, 0, 0),
-	MX6_PAD_KEY_COL1__UART5_TXD		= IOMUX_PAD(0x0630, 0x0248, 4, 0x0000, 0, 0),
-	MX6_PAD_KEY_COL1__UART5_RXD		= IOMUX_PAD(0x0630, 0x0248, 4, 0x091C, 2, 0),
-	MX6_PAD_KEY_COL1__GPIO_4_8		= IOMUX_PAD(0x0630, 0x0248, 5, 0x0000, 0, 0),
-	MX6_PAD_KEY_COL1__USDHC1_VSELECT	= IOMUX_PAD(0x0630, 0x0248, 6, 0x0000, 0, 0),
-	MX6_PAD_KEY_COL1__PL301_SIM_MX6DL_PER1_HADDR_1	= IOMUX_PAD(0x0630, 0x0248, 7, 0x0000, 0, 0),
-	MX6_PAD_KEY_COL2__ECSPI1_SS1		= IOMUX_PAD(0x0634, 0x024C, 0, 0x07E8, 2, 0),
-	MX6_PAD_KEY_COL2__ENET_RDATA_2		= IOMUX_PAD(0x0634, 0x024C, 1, 0x0820, 0, 0),
-	MX6_PAD_KEY_COL2__CAN1_TXCAN		= IOMUX_PAD(0x0634, 0x024C, 2, 0x0000, 0, 0),
-	MX6_PAD_KEY_COL2__KPP_COL_2		= IOMUX_PAD(0x0634, 0x024C, 3, 0x0000, 0, 0),
-	MX6_PAD_KEY_COL2__ENET_MDC		= IOMUX_PAD(0x0634, 0x024C, 4, 0x0000, 0, 0),
-	MX6_PAD_KEY_COL2__GPIO_4_10		= IOMUX_PAD(0x0634, 0x024C, 5, 0x0000, 0, 0),
-	MX6_PAD_KEY_COL2__USBOH3_H1USB_PWRCTL_WAKEUP	= IOMUX_PAD(0x0634, 0x024C, 6, 0x0000, 0, 0),
-	MX6_PAD_KEY_COL2__PL301_SIM_MX6DL_PER1_HADDR_3	= IOMUX_PAD(0x0634, 0x024C, 7, 0x0000, 0, 0),
-	MX6_PAD_KEY_COL3__ECSPI1_SS3		= IOMUX_PAD(0x0638, 0x0250, 0, 0x07F0, 1, 0),
-	MX6_PAD_KEY_COL3__ENET_CRS		= IOMUX_PAD(0x0638, 0x0250, 1, 0x0000, 0, 0),
-	MX6_PAD_KEY_COL3__HDMI_TX_DDC_SCL	= IOMUX_PAD(0x0638, 0x0250, 2, 0x0860, 1, 0),
-	MX6_PAD_KEY_COL3__KPP_COL_3		= IOMUX_PAD(0x0638, 0x0250, 3, 0x0000, 0, 0),
-	MX6_PAD_KEY_COL3__I2C2_SCL		= IOMUX_PAD(0x0638, 0x0250, 4 | IOMUX_CONFIG_SION, 0x0870, 1, 0),
-	MX6_PAD_KEY_COL3__GPIO_4_12		= IOMUX_PAD(0x0638, 0x0250, 5, 0x0000, 0, 0),
-	MX6_PAD_KEY_COL3__SPDIF_IN1		= IOMUX_PAD(0x0638, 0x0250, 6, 0x08F0, 3, 0),
-	MX6_PAD_KEY_COL3__PL301_SIM_MX6DL_PER1_HADDR_5	= IOMUX_PAD(0x0638, 0x0250, 7, 0x0000, 0, 0),
-	MX6_PAD_KEY_COL4__CAN2_TXCAN		= IOMUX_PAD(0x063C, 0x0254, 0, 0x0000, 0, 0),
-	MX6_PAD_KEY_COL4__IPU1_SISG_4		= IOMUX_PAD(0x063C, 0x0254, 1, 0x0000, 0, 0),
-	MX6_PAD_KEY_COL4__USBOH3_USBOTG_OC	= IOMUX_PAD(0x063C, 0x0254, 2, 0x0920, 1, 0),
-	MX6_PAD_KEY_COL4__KPP_COL_4		= IOMUX_PAD(0x063C, 0x0254, 3, 0x0000, 0, 0),
-	MX6_PAD_KEY_COL4__UART5_CTS		= IOMUX_PAD(0x063C, 0x0254, 4, 0x0000, 0, 0),
-	MX6_PAD_KEY_COL4__UART5_RTS		= IOMUX_PAD(0x063C, 0x0254, 4, 0x0918, 2, 0),
-	MX6_PAD_KEY_COL4__GPIO_4_14		= IOMUX_PAD(0x063C, 0x0254, 5, 0x0000, 0, 0),
-	MX6_PAD_KEY_COL4__MMDC_MMDC_DEBUG_49	= IOMUX_PAD(0x063C, 0x0254, 6, 0x0000, 0, 0),
-	MX6_PAD_KEY_COL4__PL301_SIM_MX6DL_PER1_HADDR_7	= IOMUX_PAD(0x063C, 0x0254, 7, 0x0000, 0, 0),
-	MX6_PAD_KEY_ROW0__ECSPI1_MOSI		= IOMUX_PAD(0x0640, 0x0258, 0, 0x07E0, 3, 0),
-	MX6_PAD_KEY_ROW0__ENET_TDATA_3		= IOMUX_PAD(0x0640, 0x0258, 1, 0x0000, 0, 0),
-	MX6_PAD_KEY_ROW0__AUDMUX_AUD5_TXD	= IOMUX_PAD(0x0640, 0x0258, 2, 0x07B4, 1, 0),
-	MX6_PAD_KEY_ROW0__KPP_ROW_0		= IOMUX_PAD(0x0640, 0x0258, 3, 0x0000, 0, 0),
-	MX6_PAD_KEY_ROW0__UART4_TXD		= IOMUX_PAD(0x0640, 0x0258, 4, 0x0000, 0, 0),
-	MX6_PAD_KEY_ROW0__UART4_RXD		= IOMUX_PAD(0x0640, 0x0258, 4, 0x0914, 3, 0),
-	MX6_PAD_KEY_ROW0__GPIO_4_7		= IOMUX_PAD(0x0640, 0x0258, 5, 0x0000, 0, 0),
-	MX6_PAD_KEY_ROW0__DCIC2_DCIC_OUT	= IOMUX_PAD(0x0640, 0x0258, 6, 0x0000, 0, 0),
-	MX6_PAD_KEY_ROW0__PL301_SIM_MX6DL_PER1_HADDR_0	= IOMUX_PAD(0x0640, 0x0258, 7, 0x0000, 0, 0),
-	MX6_PAD_KEY_ROW1__ECSPI1_SS0		= IOMUX_PAD(0x0644, 0x025C, 0, 0x07E4, 3, 0),
-	MX6_PAD_KEY_ROW1__ENET_COL		= IOMUX_PAD(0x0644, 0x025C, 1, 0x0000, 0, 0),
-	MX6_PAD_KEY_ROW1__AUDMUX_AUD5_RXD	= IOMUX_PAD(0x0644, 0x025C, 2, 0x07B0, 1, 0),
-	MX6_PAD_KEY_ROW1__KPP_ROW_1		= IOMUX_PAD(0x0644, 0x025C, 3, 0x0000, 0, 0),
-	MX6_PAD_KEY_ROW1__UART5_TXD		= IOMUX_PAD(0x0644, 0x025C, 4, 0x0000, 0, 0),
-	MX6_PAD_KEY_ROW1__UART5_RXD		= IOMUX_PAD(0x0644, 0x025C, 4, 0x091C, 3, 0),
-	MX6_PAD_KEY_ROW1__GPIO_4_9		= IOMUX_PAD(0x0644, 0x025C, 5, 0x0000, 0, 0),
-	MX6_PAD_KEY_ROW1__USDHC2_VSELECT	= IOMUX_PAD(0x0644, 0x025C, 6, 0x0000, 0, 0),
-	MX6_PAD_KEY_ROW1__PL301_SIM_MX6DL_PER1_HADDR_2	= IOMUX_PAD(0x0644, 0x025C, 7, 0x0000, 0, 0),
-	MX6_PAD_KEY_ROW2__ECSPI1_SS2		= IOMUX_PAD(0x0648, 0x0260, 0, 0x07EC, 1, 0),
-	MX6_PAD_KEY_ROW2__ENET_TDATA_2		= IOMUX_PAD(0x0648, 0x0260, 1, 0x0000, 0, 0),
-	MX6_PAD_KEY_ROW2__CAN1_RXCAN		= IOMUX_PAD(0x0648, 0x0260, 2, 0x07C8, 1, 0),
-	MX6_PAD_KEY_ROW2__KPP_ROW_2		= IOMUX_PAD(0x0648, 0x0260, 3, 0x0000, 0, 0),
-	MX6_PAD_KEY_ROW2__USDHC2_VSELECT	= IOMUX_PAD(0x0648, 0x0260, 4, 0x0000, 0, 0),
-	MX6_PAD_KEY_ROW2__GPIO_4_11		= IOMUX_PAD(0x0648, 0x0260, 5, 0x0000, 0, 0),
-	MX6_PAD_KEY_ROW2__HDMI_TX_CEC_LINE	= IOMUX_PAD(0x0648, 0x0260, 6, 0x085C, 1, 0),
-	MX6_PAD_KEY_ROW2__PL301_SIM_MX6DL_PER1_HADDR_4	= IOMUX_PAD(0x0648, 0x0260, 7, 0x0000, 0, 0),
-	MX6_PAD_KEY_ROW3__OSC32K_32K_OUT	= IOMUX_PAD(0x064C, 0x0264, 0, 0x0000, 0, 0),
-	MX6_PAD_KEY_ROW3__ASRC_ASRC_EXT_CLK	= IOMUX_PAD(0x064C, 0x0264, 1, 0x0794, 2, 0),
-	MX6_PAD_KEY_ROW3__HDMI_TX_DDC_SDA	= IOMUX_PAD(0x064C, 0x0264, 2, 0x0864, 1, 0),
-	MX6_PAD_KEY_ROW3__KPP_ROW_3		= IOMUX_PAD(0x064C, 0x0264, 3, 0x0000, 0, 0),
-	MX6_PAD_KEY_ROW3__I2C2_SDA		= IOMUX_PAD(0x064C, 0x0264, 4 | IOMUX_CONFIG_SION, 0x0874, 1, 0),
-	MX6_PAD_KEY_ROW3__GPIO_4_13		= IOMUX_PAD(0x064C, 0x0264, 5, 0x0000, 0, 0),
-	MX6_PAD_KEY_ROW3__USDHC1_VSELECT	= IOMUX_PAD(0x064C, 0x0264, 6, 0x0000, 0, 0),
-	MX6_PAD_KEY_ROW3__PL301_SIM_MX6DL_PER1_HADDR_6	= IOMUX_PAD(0x064C, 0x0264, 7, 0x0000, 0, 0),
-	MX6_PAD_KEY_ROW4__CAN2_RXCAN		= IOMUX_PAD(0x0650, 0x0268, 0, 0x07CC, 0, 0),
-	MX6_PAD_KEY_ROW4__IPU1_SISG_5		= IOMUX_PAD(0x0650, 0x0268, 1, 0x0000, 0, 0),
-	MX6_PAD_KEY_ROW4__USBOH3_USBOTG_PWR	= IOMUX_PAD(0x0650, 0x0268, 2, 0x0000, 0, 0),
-	MX6_PAD_KEY_ROW4__KPP_ROW_4		= IOMUX_PAD(0x0650, 0x0268, 3, 0x0000, 0, 0),
-	MX6_PAD_KEY_ROW4__UART5_CTS		= IOMUX_PAD(0x0650, 0x0268, 4, 0x0000, 0, 0),
-	MX6_PAD_KEY_ROW4__UART5_RTS		= IOMUX_PAD(0x0650, 0x0268, 4, 0x0918, 3, 0),
-	MX6_PAD_KEY_ROW4__GPIO_4_15		= IOMUX_PAD(0x0650, 0x0268, 5, 0x0000, 0, 0),
-	MX6_PAD_KEY_ROW4__MMDC_MMDC_DEBUG_50	= IOMUX_PAD(0x0650, 0x0268, 6, 0x0000, 0, 0),
-	MX6_PAD_KEY_ROW4__PL301_SIM_MX6DL_PER1_HADDR_8	= IOMUX_PAD(0x0650, 0x0268, 7, 0x0000, 0, 0),
-	MX6_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK	= IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
-	MX6_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0	= IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
-	MX6_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1	= IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
-	MX6_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2	= IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
-	MX6_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3	= IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
-	MX6_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK	= IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
-	MX6_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0	= IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
-	MX6_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1	= IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
-	MX6_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2	= IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
-	MX6_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3	= IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
-	MX6_PAD_NANDF_ALE__RAWNAND_ALE		= IOMUX_PAD(0x0654, 0x026C, 0, 0x0000, 0, 0),
-	MX6_PAD_NANDF_ALE__USDHC4_RST		= IOMUX_PAD(0x0654, 0x026C, 1, 0x0000, 0, 0),
-	MX6_PAD_NANDF_ALE__PCIE_CTRL_DIAG_STATUS_BUS_MUX_0	= IOMUX_PAD(0x0654, 0x026C, 2, 0x0000, 0, 0),
-	MX6_PAD_NANDF_ALE__USBOH3_UH3_DFD_OUT_12	= IOMUX_PAD(0x0654, 0x026C, 3, 0x0000, 0, 0),
-	MX6_PAD_NANDF_ALE__USBOH3_UH2_DFD_OUT_12	= IOMUX_PAD(0x0654, 0x026C, 4, 0x0000, 0, 0),
-	MX6_PAD_NANDF_ALE__GPIO_6_8		= IOMUX_PAD(0x0654, 0x026C, 5, 0x0000, 0, 0),
-	MX6_PAD_NANDF_ALE__MIPI_CORE_DPHY_TEST_IN_24	= IOMUX_PAD(0x0654, 0x026C, 6, 0x0000, 0, 0),
-	MX6_PAD_NANDF_ALE__USDHC3_CLKI		= IOMUX_PAD(0x0654, 0x026C, 8, 0x0934, 0, 0),
-	MX6_PAD_NANDF_CLE__RAWNAND_CLE		= IOMUX_PAD(0x0658, 0x0270, 0, 0x0000, 0, 0),
-	MX6_PAD_NANDF_CLE__PCIE_CTRL_DIAG_STATUS_BUS_MUX_31	= IOMUX_PAD(0x0658, 0x0270, 2, 0x0000, 0, 0),
-	MX6_PAD_NANDF_CLE__USBOH3_UH3_DFD_OUT_11	= IOMUX_PAD(0x0658, 0x0270, 3, 0x0000, 0, 0),
-	MX6_PAD_NANDF_CLE__USBOH3_UH2_DFD_OUT_11	= IOMUX_PAD(0x0658, 0x0270, 4, 0x0000, 0, 0),
-	MX6_PAD_NANDF_CLE__GPIO_6_7		= IOMUX_PAD(0x0658, 0x0270, 5, 0x0000, 0, 0),
-	MX6_PAD_NANDF_CLE__MIPI_CORE_DPHY_TEST_IN_23	= IOMUX_PAD(0x0658, 0x0270, 6, 0x0000, 0, 0),
-	MX6_PAD_NANDF_CLE__USDHC3_CLKO		= IOMUX_PAD(0x0658, 0x0270, 8, 0x0000, 0, 0),
-	MX6_PAD_NANDF_CS0__RAWNAND_CE0N		= IOMUX_PAD(0x065C, 0x0274, 0, 0x0000, 0, 0),
-	MX6_PAD_NANDF_CS0__USBOH3_UH3_DFD_OUT_15	= IOMUX_PAD(0x065C, 0x0274, 3, 0x0000, 0, 0),
-	MX6_PAD_NANDF_CS0__USBOH3_UH2_DFD_OUT_15	= IOMUX_PAD(0x065C, 0x0274, 4, 0x0000, 0, 0),
-	MX6_PAD_NANDF_CS0__GPIO_6_11		= IOMUX_PAD(0x065C, 0x0274, 5, 0x0000, 0, 0),
-	MX6_PAD_NANDF_CS0__USDHC1_CLKO		= IOMUX_PAD(0x065C, 0x0274, 8, 0x0000, 0, 0),
-	MX6_PAD_NANDF_CS1__RAWNAND_CE1N		= IOMUX_PAD(0x0660, 0x0278, 0, 0x0000, 0, 0),
-	MX6_PAD_NANDF_CS1__USDHC4_VSELECT	= IOMUX_PAD(0x0660, 0x0278, 1, 0x0000, 0, 0),
-	MX6_PAD_NANDF_CS1__USDHC3_VSELECT	= IOMUX_PAD(0x0660, 0x0278, 2, 0x0000, 0, 0),
-	MX6_PAD_NANDF_CS1__PCIE_CTRL_DIAG_STATUS_BUS_MUX_3	= IOMUX_PAD(0x0660, 0x0278, 4, 0x0000, 0, 0),
-	MX6_PAD_NANDF_CS1__GPIO_6_14		= IOMUX_PAD(0x0660, 0x0278, 5, 0x0000, 0, 0),
-	MX6_PAD_NANDF_CS1__PL301_SIM_MX6DL_PER1_HREADYOUT	= IOMUX_PAD(0x0660, 0x0278, 7, 0x0000, 0, 0),
-	MX6_PAD_NANDF_CS1__USDHC1_CLKI		= IOMUX_PAD(0x0660, 0x0278, 8, 0x0928, 0, 0),
-	MX6_PAD_NANDF_CS2__RAWNAND_CE2N		= IOMUX_PAD(0x0664, 0x027C, 0, 0x0000, 0, 0),
-	MX6_PAD_NANDF_CS2__IPU1_SISG_0		= IOMUX_PAD(0x0664, 0x027C, 1, 0x0000, 0, 0),
-	MX6_PAD_NANDF_CS2__ESAI1_TX0		= IOMUX_PAD(0x0664, 0x027C, 2, 0x0844, 1, 0),
-	MX6_PAD_NANDF_CS2__WEIM_WEIM_CRE	= IOMUX_PAD(0x0664, 0x027C, 3, 0x0000, 0, 0),
-	MX6_PAD_NANDF_CS2__CCM_CLKO2		= IOMUX_PAD(0x0664, 0x027C, 4, 0x0000, 0, 0),
-	MX6_PAD_NANDF_CS2__GPIO_6_15		= IOMUX_PAD(0x0664, 0x027C, 5, 0x0000, 0, 0),
-	MX6_PAD_NANDF_CS2__USDHC2_CLKO		= IOMUX_PAD(0x0664, 0x027C, 8, 0x0000, 0, 0),
-	MX6_PAD_NANDF_CS3__RAWNAND_CE3N		= IOMUX_PAD(0x0668, 0x0280, 0, 0x0000, 0, 0),
-	MX6_PAD_NANDF_CS3__IPU1_SISG_1		= IOMUX_PAD(0x0668, 0x0280, 1, 0x0000, 0, 0),
-	MX6_PAD_NANDF_CS3__ESAI1_TX1		= IOMUX_PAD(0x0668, 0x0280, 2, 0x0848, 1, 0),
-	MX6_PAD_NANDF_CS3__WEIM_WEIM_A_26	= IOMUX_PAD(0x0668, 0x0280, 3, 0x0000, 0, 0),
-	MX6_PAD_NANDF_CS3__PCIE_CTRL_DIAG_STATUS_BUS_MUX_4	= IOMUX_PAD(0x0668, 0x0280, 4, 0x0000, 0, 0),
-	MX6_PAD_NANDF_CS3__GPIO_6_16		= IOMUX_PAD(0x0668, 0x0280, 5, 0x0000, 0, 0),
-	MX6_PAD_NANDF_CS3__TPSMP_CLK		= IOMUX_PAD(0x0668, 0x0280, 7, 0x0000, 0, 0),
-	MX6_PAD_NANDF_CS3__USDHC2_CLKI		= IOMUX_PAD(0x0668, 0x0280, 8, 0x0930, 0, 0),
-	MX6_PAD_NANDF_CS3__I2C4_SDA		= IOMUX_PAD(0x0668, 0x0280, 9 | IOMUX_CONFIG_SION, 0x0884, 2, 0),
-	MX6_PAD_NANDF_D0__RAWNAND_D0		= IOMUX_PAD(0x066C, 0x0284, 0, 0x0000, 0, 0),
-	MX6_PAD_NANDF_D0__USDHC1_DAT4		= IOMUX_PAD(0x066C, 0x0284, 1, 0x0000, 0, 0),
-	MX6_PAD_NANDF_D0__GPU3D_GPU_DEBUG_OUT_0	= IOMUX_PAD(0x066C, 0x0284, 2, 0x0000, 0, 0),
-	MX6_PAD_NANDF_D0__USBOH3_UH2_DFD_OUT_16	= IOMUX_PAD(0x066C, 0x0284, 3, 0x0000, 0, 0),
-	MX6_PAD_NANDF_D0__USBOH3_UH3_DFD_OUT_16	= IOMUX_PAD(0x066C, 0x0284, 4, 0x0000, 0, 0),
-	MX6_PAD_NANDF_D0__GPIO_2_0		= IOMUX_PAD(0x066C, 0x0284, 5, 0x0000, 0, 0),
-	MX6_PAD_NANDF_D0__IPU1_IPU_DIAG_BUS_0	= IOMUX_PAD(0x066C, 0x0284, 6, 0x0000, 0, 0),
-	MX6_PAD_NANDF_D1__RAWNAND_D1		= IOMUX_PAD(0x0670, 0x0288, 0, 0x0000, 0, 0),
-	MX6_PAD_NANDF_D1__USDHC1_DAT5		= IOMUX_PAD(0x0670, 0x0288, 1, 0x0000, 0, 0),
-	MX6_PAD_NANDF_D1__GPU3D_GPU_DEBUG_OUT_1	= IOMUX_PAD(0x0670, 0x0288, 2, 0x0000, 0, 0),
-	MX6_PAD_NANDF_D1__USBOH3_UH2_DFD_OUT_17	= IOMUX_PAD(0x0670, 0x0288, 3, 0x0000, 0, 0),
-	MX6_PAD_NANDF_D1__USBOH3_UH3_DFD_OUT_17	= IOMUX_PAD(0x0670, 0x0288, 4, 0x0000, 0, 0),
-	MX6_PAD_NANDF_D1__GPIO_2_1		= IOMUX_PAD(0x0670, 0x0288, 5, 0x0000, 0, 0),
-	MX6_PAD_NANDF_D1__IPU1_IPU_DIAG_BUS_1	= IOMUX_PAD(0x0670, 0x0288, 6, 0x0000, 0, 0),
-	MX6_PAD_NANDF_D2__RAWNAND_D2		= IOMUX_PAD(0x0674, 0x028C, 0, 0x0000, 0, 0),
-	MX6_PAD_NANDF_D2__USDHC1_DAT6		= IOMUX_PAD(0x0674, 0x028C, 1, 0x0000, 0, 0),
-	MX6_PAD_NANDF_D2__GPU3D_GPU_DEBUG_OUT_2	= IOMUX_PAD(0x0674, 0x028C, 2, 0x0000, 0, 0),
-	MX6_PAD_NANDF_D2__USBOH3_UH2_DFD_OUT_18	= IOMUX_PAD(0x0674, 0x028C, 3, 0x0000, 0, 0),
-	MX6_PAD_NANDF_D2__USBOH3_UH3_DFD_OUT_18	= IOMUX_PAD(0x0674, 0x028C, 4, 0x0000, 0, 0),
-	MX6_PAD_NANDF_D2__GPIO_2_2		= IOMUX_PAD(0x0674, 0x028C, 5, 0x0000, 0, 0),
-	MX6_PAD_NANDF_D2__IPU1_IPU_DIAG_BUS_2	= IOMUX_PAD(0x0674, 0x028C, 6, 0x0000, 0, 0),
-	MX6_PAD_NANDF_D3__RAWNAND_D3		= IOMUX_PAD(0x0678, 0x0290, 0, 0x0000, 0, 0),
-	MX6_PAD_NANDF_D3__USDHC1_DAT7		= IOMUX_PAD(0x0678, 0x0290, 1, 0x0000, 0, 0),
-	MX6_PAD_NANDF_D3__GPU3D_GPU_DEBUG_OUT_3	= IOMUX_PAD(0x0678, 0x0290, 2, 0x0000, 0, 0),
-	MX6_PAD_NANDF_D3__USBOH3_UH2_DFD_OUT_19	= IOMUX_PAD(0x0678, 0x0290, 3, 0x0000, 0, 0),
-	MX6_PAD_NANDF_D3__USBOH3_UH3_DFD_OUT_19	= IOMUX_PAD(0x0678, 0x0290, 4, 0x0000, 0, 0),
-	MX6_PAD_NANDF_D3__GPIO_2_3		= IOMUX_PAD(0x0678, 0x0290, 5, 0x0000, 0, 0),
-	MX6_PAD_NANDF_D3__IPU1_IPU_DIAG_BUS_3	= IOMUX_PAD(0x0678, 0x0290, 6, 0x0000, 0, 0),
-	MX6_PAD_NANDF_D4__RAWNAND_D4		= IOMUX_PAD(0x067C, 0x0294, 0, 0x0000, 0, 0),
-	MX6_PAD_NANDF_D4__USDHC2_DAT4		= IOMUX_PAD(0x067C, 0x0294, 1, 0x0000, 0, 0),
-	MX6_PAD_NANDF_D4__GPU3D_GPU_DEBUG_OUT_4	= IOMUX_PAD(0x067C, 0x0294, 2, 0x0000, 0, 0),
-	MX6_PAD_NANDF_D4__USBOH3_UH2_DFD_OUT_20	= IOMUX_PAD(0x067C, 0x0294, 3, 0x0000, 0, 0),
-	MX6_PAD_NANDF_D4__USBOH3_UH3_DFD_OUT_20	= IOMUX_PAD(0x067C, 0x0294, 4, 0x0000, 0, 0),
-	MX6_PAD_NANDF_D4__GPIO_2_4		= IOMUX_PAD(0x067C, 0x0294, 5, 0x0000, 0, 0),
-	MX6_PAD_NANDF_D4__IPU1_IPU_DIAG_BUS_4	= IOMUX_PAD(0x067C, 0x0294, 6, 0x0000, 0, 0),
-	MX6_PAD_NANDF_D5__RAWNAND_D5		= IOMUX_PAD(0x0680, 0x0298, 0, 0x0000, 0, 0),
-	MX6_PAD_NANDF_D5__USDHC2_DAT5		= IOMUX_PAD(0x0680, 0x0298, 1, 0x0000, 0, 0),
-	MX6_PAD_NANDF_D5__GPU3D_GPU_DEBUG_OUT_5	= IOMUX_PAD(0x0680, 0x0298, 2, 0x0000, 0, 0),
-	MX6_PAD_NANDF_D5__USBOH3_UH2_DFD_OUT_21	= IOMUX_PAD(0x0680, 0x0298, 3, 0x0000, 0, 0),
-	MX6_PAD_NANDF_D5__USBOH3_UH3_DFD_OUT_21	= IOMUX_PAD(0x0680, 0x0298, 4, 0x0000, 0, 0),
-	MX6_PAD_NANDF_D5__GPIO_2_5		= IOMUX_PAD(0x0680, 0x0298, 5, 0x0000, 0, 0),
-	MX6_PAD_NANDF_D5__IPU1_IPU_DIAG_BUS_5	= IOMUX_PAD(0x0680, 0x0298, 6, 0x0000, 0, 0),
-	MX6_PAD_NANDF_D6__RAWNAND_D6		= IOMUX_PAD(0x0684, 0x029C, 0, 0x0000, 0, 0),
-	MX6_PAD_NANDF_D6__USDHC2_DAT6		= IOMUX_PAD(0x0684, 0x029C, 1, 0x0000, 0, 0),
-	MX6_PAD_NANDF_D6__GPU3D_GPU_DEBUG_OUT_6	= IOMUX_PAD(0x0684, 0x029C, 2, 0x0000, 0, 0),
-	MX6_PAD_NANDF_D6__USBOH3_UH2_DFD_OUT_22	= IOMUX_PAD(0x0684, 0x029C, 3, 0x0000, 0, 0),
-	MX6_PAD_NANDF_D6__USBOH3_UH3_DFD_OUT_22	= IOMUX_PAD(0x0684, 0x029C, 4, 0x0000, 0, 0),
-	MX6_PAD_NANDF_D6__GPIO_2_6		= IOMUX_PAD(0x0684, 0x029C, 5, 0x0000, 0, 0),
-	MX6_PAD_NANDF_D6__IPU1_IPU_DIAG_BUS_6	= IOMUX_PAD(0x0684, 0x029C, 6, 0x0000, 0, 0),
-	MX6_PAD_NANDF_D7__RAWNAND_D7		= IOMUX_PAD(0x0688, 0x02A0, 0, 0x0000, 0, 0),
-	MX6_PAD_NANDF_D7__USDHC2_DAT7		= IOMUX_PAD(0x0688, 0x02A0, 1, 0x0000, 0, 0),
-	MX6_PAD_NANDF_D7__GPU3D_GPU_DEBUG_OUT_7	= IOMUX_PAD(0x0688, 0x02A0, 2, 0x0000, 0, 0),
-	MX6_PAD_NANDF_D7__USBOH3_UH2_DFD_OUT_23	= IOMUX_PAD(0x0688, 0x02A0, 3, 0x0000, 0, 0),
-	MX6_PAD_NANDF_D7__USBOH3_UH3_DFD_OUT_23	= IOMUX_PAD(0x0688, 0x02A0, 4, 0x0000, 0, 0),
-	MX6_PAD_NANDF_D7__GPIO_2_7		= IOMUX_PAD(0x0688, 0x02A0, 5, 0x0000, 0, 0),
-	MX6_PAD_NANDF_D7__IPU1_IPU_DIAG_BUS_7	= IOMUX_PAD(0x0688, 0x02A0, 6, 0x0000, 0, 0),
-	MX6_PAD_NANDF_RB0__RAWNAND_READY0	= IOMUX_PAD(0x068C, 0x02A4, 0, 0x0000, 0, 0),
-	MX6_PAD_NANDF_RB0__PCIE_CTRL_DIAG_STATUS_BUS_MUX_2	= IOMUX_PAD(0x068C, 0x02A4, 2, 0x0000, 0, 0),
-	MX6_PAD_NANDF_RB0__USBOH3_UH3_DFD_OUT_14	= IOMUX_PAD(0x068C, 0x02A4, 3, 0x0000, 0, 0),
-	MX6_PAD_NANDF_RB0__USBOH3_UH2_DFD_OUT_14	= IOMUX_PAD(0x068C, 0x02A4, 4, 0x0000, 0, 0),
-	MX6_PAD_NANDF_RB0__GPIO_6_10		= IOMUX_PAD(0x068C, 0x02A4, 5, 0x0000, 0, 0),
-	MX6_PAD_NANDF_RB0__MIPI_CORE_DPHY_TEST_OUT_33	= IOMUX_PAD(0x068C, 0x02A4, 6, 0x0000, 0, 0),
-	MX6_PAD_NANDF_RB0__USDHC4_CLKI		= IOMUX_PAD(0x068C, 0x02A4, 8, 0x0938, 0, 0),
-	MX6_PAD_NANDF_WP_B__RAWNAND_RESETN	= IOMUX_PAD(0x0690, 0x02A8, 0, 0x0000, 0, 0),
-	MX6_PAD_NANDF_WP_B__PCIE_CTRL_DIAG_STATUS_BUS_MUX_1	= IOMUX_PAD(0x0690, 0x02A8, 2, 0x0000, 0, 0),
-	MX6_PAD_NANDF_WP_B__USBOH3_UH3_DFD_OUT_13	= IOMUX_PAD(0x0690, 0x02A8, 3, 0x0000, 0, 0),
-	MX6_PAD_NANDF_WP_B__USBOH3_UH2_DFD_OUT_13	= IOMUX_PAD(0x0690, 0x02A8, 4, 0x0000, 0, 0),
-	MX6_PAD_NANDF_WP_B__GPIO_6_9		= IOMUX_PAD(0x0690, 0x02A8, 5, 0x0000, 0, 0),
-	MX6_PAD_NANDF_WP_B__MIPI_CORE_DPHY_TEST_OUT_32	= IOMUX_PAD(0x0690, 0x02A8, 6, 0x0000, 0, 0),
-	MX6_PAD_NANDF_WP_B__USDHC4_CLKO		= IOMUX_PAD(0x0690, 0x02A8, 8, 0x0000, 0, 0),
-	MX6_PAD_NANDF_WP_B__I2C4_SCL		= IOMUX_PAD(0x0690, 0x02A8, 9 | IOMUX_CONFIG_SION, 0x0880, 2, 0),
-	MX6_PAD_PMIC_ON_REQ__SNVS_LP_WRAPPER_SNVS_WAKEUP_ALARM	= IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
-	MX6_PAD_PMIC_STBY_REQ__CCM_PMIC_VSTBY_REQ	= IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
-	MX6_PAD_POR_B__SRC_POR_B		= IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
-	MX6_PAD_RESET_IN_B__SRC_RESET_B		= IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
-	MX6_PAD_RGMII_RD0__MIPI_HSI_CTRL_RX_READY	= IOMUX_PAD(0x0694, 0x02AC, 0, 0x0000, 0, 0),
-	MX6_PAD_RGMII_RD0__ENET_RGMII_RD0	= IOMUX_PAD(0x0694, 0x02AC, 1, 0x0818, 1, 0),
-	MX6_PAD_RGMII_RD0__GPIO_6_25		= IOMUX_PAD(0x0694, 0x02AC, 5, 0x0000, 0, 0),
-	MX6_PAD_RGMII_RD0__MIPI_CORE_DPHY_TEST_IN_6	= IOMUX_PAD(0x0694, 0x02AC, 6, 0x0000, 0, 0),
-	MX6_PAD_RGMII_RD1__MIPI_HSI_CTRL_TX_FLAG	= IOMUX_PAD(0x0698, 0x02B0, 0, 0x0000, 0, 0),
-	MX6_PAD_RGMII_RD1__ENET_RGMII_RD1	= IOMUX_PAD(0x0698, 0x02B0, 1, 0x081C, 1, 0),
-	MX6_PAD_RGMII_RD1__GPIO_6_27		= IOMUX_PAD(0x0698, 0x02B0, 5, 0x0000, 0, 0),
-	MX6_PAD_RGMII_RD1__MIPI_CORE_DPHY_TEST_IN_8	= IOMUX_PAD(0x0698, 0x02B0, 6, 0x0000, 0, 0),
-	MX6_PAD_RGMII_RD1__SJC_FAIL		= IOMUX_PAD(0x0698, 0x02B0, 7, 0x0000, 0, 0),
-	MX6_PAD_RGMII_RD2__MIPI_HSI_CTRL_TX_DATA	= IOMUX_PAD(0x069C, 0x02B4, 0, 0x0000, 0, 0),
-	MX6_PAD_RGMII_RD2__ENET_RGMII_RD2	= IOMUX_PAD(0x069C, 0x02B4, 1, 0x0820, 1, 0),
-	MX6_PAD_RGMII_RD2__GPIO_6_28		= IOMUX_PAD(0x069C, 0x02B4, 5, 0x0000, 0, 0),
-	MX6_PAD_RGMII_RD2__MIPI_CORE_DPHY_TEST_IN_9	= IOMUX_PAD(0x069C, 0x02B4, 6, 0x0000, 0, 0),
-	MX6_PAD_RGMII_RD3__MIPI_HSI_CTRL_TX_WAKE	= IOMUX_PAD(0x06A0, 0x02B8, 0, 0x0000, 0, 0),
-	MX6_PAD_RGMII_RD3__ENET_RGMII_RD3	= IOMUX_PAD(0x06A0, 0x02B8, 1, 0x0824, 1, 0),
-	MX6_PAD_RGMII_RD3__GPIO_6_29		= IOMUX_PAD(0x06A0, 0x02B8, 5, 0x0000, 0, 0),
-	MX6_PAD_RGMII_RD3__MIPI_CORE_DPHY_TEST_IN_10	= IOMUX_PAD(0x06A0, 0x02B8, 6, 0x0000, 0, 0),
-	MX6_PAD_RGMII_RX_CTL__USBOH3_H3_DATA	= IOMUX_PAD(0x06A4, 0x02BC, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0),
-	MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL	= IOMUX_PAD(0x06A4, 0x02BC, 1, 0x0828, 1, 0),
-	MX6_PAD_RGMII_RX_CTL__GPIO_6_24		= IOMUX_PAD(0x06A4, 0x02BC, 5, 0x0000, 0, 0),
-	MX6_PAD_RGMII_RX_CTL__MIPI_CORE_DPHY_TEST_IN_5	= IOMUX_PAD(0x06A4, 0x02BC, 6, 0x0000, 0, 0),
-	MX6_PAD_RGMII_RXC__USBOH3_H3_STROBE	= IOMUX_PAD(0x06A8, 0x02C0, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0),
-	MX6_PAD_RGMII_RXC__USBOH3_H3_STROBE_START	= IOMUX_PAD(0x06A8, 0x02C0, 0 | IOMUX_CONFIG_SION, 0x0000, 0, PAD_CTL_PUS_47K_UP),
-	MX6_PAD_RGMII_RXC__ENET_RGMII_RXC	= IOMUX_PAD(0x06A8, 0x02C0, 1, 0x0814, 1, 0),
-	MX6_PAD_RGMII_RXC__GPIO_6_30		= IOMUX_PAD(0x06A8, 0x02C0, 5, 0x0000, 0, 0),
-	MX6_PAD_RGMII_RXC__MIPI_CORE_DPHY_TEST_IN_11	= IOMUX_PAD(0x06A8, 0x02C0, 6, 0x0000, 0, 0),
-	MX6_PAD_RGMII_TD0__MIPI_HSI_CTRL_TX_READY	= IOMUX_PAD(0x06AC, 0x02C4, 0, 0x0000, 0, 0),
-	MX6_PAD_RGMII_TD0__ENET_RGMII_TD0	= IOMUX_PAD(0x06AC, 0x02C4, 1, 0x0000, 0, 0),
-	MX6_PAD_RGMII_TD0__GPIO_6_20		= IOMUX_PAD(0x06AC, 0x02C4, 5, 0x0000, 0, 0),
-	MX6_PAD_RGMII_TD0__MIPI_CORE_DPHY_TEST_IN_1	= IOMUX_PAD(0x06AC, 0x02C4, 6, 0x0000, 0, 0),
-	MX6_PAD_RGMII_TD1__MIPI_HSI_CTRL_RX_FLAG	= IOMUX_PAD(0x06B0, 0x02C8, 0, 0x0000, 0, 0),
-	MX6_PAD_RGMII_TD1__ENET_RGMII_TD1	= IOMUX_PAD(0x06B0, 0x02C8, 1, 0x0000, 0, 0),
-	MX6_PAD_RGMII_TD1__GPIO_6_21		= IOMUX_PAD(0x06B0, 0x02C8, 5, 0x0000, 0, 0),
-	MX6_PAD_RGMII_TD1__MIPI_CORE_DPHY_TEST_IN_2	= IOMUX_PAD(0x06B0, 0x02C8, 6, 0x0000, 0, 0),
-	MX6_PAD_RGMII_TD1__CCM_PLL3_BYP		= IOMUX_PAD(0x06B0, 0x02C8, 7, 0x0000, 0, 0),
-	MX6_PAD_RGMII_TD2__MIPI_HSI_CTRL_RX_DATA	= IOMUX_PAD(0x06B4, 0x02CC, 0, 0x0000, 0, 0),
-	MX6_PAD_RGMII_TD2__ENET_RGMII_TD2	= IOMUX_PAD(0x06B4, 0x02CC, 1, 0x0000, 0, 0),
-	MX6_PAD_RGMII_TD2__GPIO_6_22		= IOMUX_PAD(0x06B4, 0x02CC, 5, 0x0000, 0, 0),
-	MX6_PAD_RGMII_TD2__MIPI_CORE_DPHY_TEST_IN_3	= IOMUX_PAD(0x06B4, 0x02CC, 6, 0x0000, 0, 0),
-	MX6_PAD_RGMII_TD2__CCM_PLL2_BYP		= IOMUX_PAD(0x06B4, 0x02CC, 7, 0x0000, 0, 0),
-	MX6_PAD_RGMII_TD3__MIPI_HSI_CTRL_RX_WAKE	= IOMUX_PAD(0x06B8, 0x02D0, 0, 0x0000, 0, 0),
-	MX6_PAD_RGMII_TD3__ENET_RGMII_TD3	= IOMUX_PAD(0x06B8, 0x02D0, 1, 0x0000, 0, 0),
-	MX6_PAD_RGMII_TD3__GPIO_6_23		= IOMUX_PAD(0x06B8, 0x02D0, 5, 0x0000, 0, 0),
-	MX6_PAD_RGMII_TD3__MIPI_CORE_DPHY_TEST_IN_4	= IOMUX_PAD(0x06B8, 0x02D0, 6, 0x0000, 0, 0),
-	MX6_PAD_RGMII_TX_CTL__USBOH3_H2_STROBE	= IOMUX_PAD(0x06BC, 0x02D4, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0),
-	MX6_PAD_RGMII_TX_CTL__USBOH3_H2_STROBE_START	= IOMUX_PAD(0x06BC, 0x02D4, 0 | IOMUX_CONFIG_SION, 0x0000, 0, PAD_CTL_PUS_47K_UP),
-	MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL	= IOMUX_PAD(0x06BC, 0x02D4, 1, 0x0000, 0, 0),
-	MX6_PAD_RGMII_TX_CTL__GPIO_6_26		= IOMUX_PAD(0x06BC, 0x02D4, 5, 0x0000, 0, 0),
-	MX6_PAD_RGMII_TX_CTL__MIPI_CORE_DPHY_TEST_IN_7	= IOMUX_PAD(0x06BC, 0x02D4, 6, 0x0000, 0, 0),
-	MX6_PAD_RGMII_TX_CTL__ENET_ANATOP_ETHERNET_REF_OUT	= IOMUX_PAD(0x06BC, 0x02D4, 7, 0x080C, 1, 0),
-	MX6_PAD_RGMII_TXC__USBOH3_H2_DATA	= IOMUX_PAD(0x06C0, 0x02D8, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0),
-	MX6_PAD_RGMII_TXC__ENET_RGMII_TXC	= IOMUX_PAD(0x06C0, 0x02D8, 1, 0x0000, 0, 0),
-	MX6_PAD_RGMII_TXC__SPDIF_SPDIF_EXTCLK	= IOMUX_PAD(0x06C0, 0x02D8, 2, 0x08F4, 1, 0),
-	MX6_PAD_RGMII_TXC__GPIO_6_19		= IOMUX_PAD(0x06C0, 0x02D8, 5, 0x0000, 0, 0),
-	MX6_PAD_RGMII_TXC__MIPI_CORE_DPHY_TEST_IN_0	= IOMUX_PAD(0x06C0, 0x02D8, 6, 0x0000, 0, 0),
-	MX6_PAD_RGMII_TXC__ANATOP_ANATOP_24M_OUT	= IOMUX_PAD(0x06C0, 0x02D8, 7, 0x0000, 0, 0),
-	MX6_PAD_SD1_CLK__USDHC1_CLK		= IOMUX_PAD(0x06C4, 0x02DC, 0, 0x0928, 1, 0),
-	MX6_PAD_SD1_CLK__OSC32K_32K_OUT		= IOMUX_PAD(0x06C4, 0x02DC, 2, 0x0000, 0, 0),
-	MX6_PAD_SD1_CLK__GPT_CLKIN		= IOMUX_PAD(0x06C4, 0x02DC, 3, 0x0000, 0, 0),
-	MX6_PAD_SD1_CLK__GPIO_1_20		= IOMUX_PAD(0x06C4, 0x02DC, 5, 0x0000, 0, 0),
-	MX6_PAD_SD1_CLK__PHY_DTB_0		= IOMUX_PAD(0x06C4, 0x02DC, 6, 0x0000, 0, 0),
-	MX6_PAD_SD1_CMD__USDHC1_CMD		= IOMUX_PAD(0x06C8, 0x02E0, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0),
-	MX6_PAD_SD1_CMD__PWM4_PWMO		= IOMUX_PAD(0x06C8, 0x02E0, 2, 0x0000, 0, 0),
-	MX6_PAD_SD1_CMD__GPT_CMPOUT1		= IOMUX_PAD(0x06C8, 0x02E0, 3, 0x0000, 0, 0),
-	MX6_PAD_SD1_CMD__GPIO_1_18		= IOMUX_PAD(0x06C8, 0x02E0, 5, 0x0000, 0, 0),
-	MX6_PAD_SD1_CMD__ANATOP_ANATOP_TESTO_5	= IOMUX_PAD(0x06C8, 0x02E0, 7, 0x0000, 0, 0),
-	MX6_PAD_SD1_DAT0__USDHC1_DAT0		= IOMUX_PAD(0x06CC, 0x02E4, 0, 0x0000, 0, 0),
-	MX6_PAD_SD1_DAT0__CAAM_WRAPPER_RNG_OSC_OBS	= IOMUX_PAD(0x06CC, 0x02E4, 2, 0x0000, 0, 0),
-	MX6_PAD_SD1_DAT0__GPT_CAPIN1		= IOMUX_PAD(0x06CC, 0x02E4, 3, 0x0000, 0, 0),
-	MX6_PAD_SD1_DAT0__PCIE_CTRL_DIAG_STATUS_BUS_MUX_8	= IOMUX_PAD(0x06CC, 0x02E4, 4, 0x0000, 0, 0),
-	MX6_PAD_SD1_DAT0__GPIO_1_16		= IOMUX_PAD(0x06CC, 0x02E4, 5, 0x0000, 0, 0),
-	MX6_PAD_SD1_DAT0__HDMI_TX_OPHYDTB_1	= IOMUX_PAD(0x06CC, 0x02E4, 6, 0x0000, 0, 0),
-	MX6_PAD_SD1_DAT0__ANATOP_ANATOP_TESTO_7	= IOMUX_PAD(0x06CC, 0x02E4, 7, 0x0000, 0, 0),
-	MX6_PAD_SD1_DAT1__USDHC1_DAT1		= IOMUX_PAD(0x06D0, 0x02E8, 0, 0x0000, 0, 0),
-	MX6_PAD_SD1_DAT1__PWM3_PWMO		= IOMUX_PAD(0x06D0, 0x02E8, 2, 0x0000, 0, 0),
-	MX6_PAD_SD1_DAT1__GPT_CAPIN2		= IOMUX_PAD(0x06D0, 0x02E8, 3, 0x0000, 0, 0),
-	MX6_PAD_SD1_DAT1__PCIE_CTRL_DIAG_STATUS_BUS_MUX_7	= IOMUX_PAD(0x06D0, 0x02E8, 4, 0x0000, 0, 0),
-	MX6_PAD_SD1_DAT1__GPIO_1_17		= IOMUX_PAD(0x06D0, 0x02E8, 5, 0x0000, 0, 0),
-	MX6_PAD_SD1_DAT1__HDMI_TX_OPHYDTB_0	= IOMUX_PAD(0x06D0, 0x02E8, 6, 0x0000, 0, 0),
-	MX6_PAD_SD1_DAT1__ANATOP_ANATOP_TESTO_8	= IOMUX_PAD(0x06D0, 0x02E8, 7, 0x0000, 0, 0),
-	MX6_PAD_SD1_DAT2__USDHC1_DAT2		= IOMUX_PAD(0x06D4, 0x02EC, 0, 0x0000, 0, 0),
-	MX6_PAD_SD1_DAT2__GPT_CMPOUT2		= IOMUX_PAD(0x06D4, 0x02EC, 2, 0x0000, 0, 0),
-	MX6_PAD_SD1_DAT2__PWM2_PWMO		= IOMUX_PAD(0x06D4, 0x02EC, 3, 0x0000, 0, 0),
-	MX6_PAD_SD1_DAT2__WDOG1_WDOG_B		= IOMUX_PAD(0x06D4, 0x02EC, 4, 0x0000, 0, 0),
-	MX6_PAD_SD1_DAT2__GPIO_1_19		= IOMUX_PAD(0x06D4, 0x02EC, 5, 0x0000, 0, 0),
-	MX6_PAD_SD1_DAT2__WDOG1_WDOG_RST_B_DEB	= IOMUX_PAD(0x06D4, 0x02EC, 6, 0x0000, 0, 0),
-	MX6_PAD_SD1_DAT2__ANATOP_ANATOP_TESTO_4	= IOMUX_PAD(0x06D4, 0x02EC, 7, 0x0000, 0, 0),
-	MX6_PAD_SD1_DAT3__USDHC1_DAT3		= IOMUX_PAD(0x06D8, 0x02F0, 0, 0x0000, 0, 0),
-	MX6_PAD_SD1_DAT3__GPT_CMPOUT3		= IOMUX_PAD(0x06D8, 0x02F0, 2, 0x0000, 0, 0),
-	MX6_PAD_SD1_DAT3__PWM1_PWMO		= IOMUX_PAD(0x06D8, 0x02F0, 3, 0x0000, 0, 0),
-	MX6_PAD_SD1_DAT3__WDOG2_WDOG_B		= IOMUX_PAD(0x06D8, 0x02F0, 4, 0x0000, 0, 0),
-	MX6_PAD_SD1_DAT3__GPIO_1_21		= IOMUX_PAD(0x06D8, 0x02F0, 5, 0x0000, 0, 0),
-	MX6_PAD_SD1_DAT3__WDOG2_WDOG_RST_B_DEB	= IOMUX_PAD(0x06D8, 0x02F0, 6, 0x0000, 0, 0),
-	MX6_PAD_SD1_DAT3__ANATOP_ANATOP_TESTO_6	= IOMUX_PAD(0x06D8, 0x02F0, 7, 0x0000, 0, 0),
-	MX6_PAD_SD2_CLK__USDHC2_CLK		= IOMUX_PAD(0x06DC, 0x02F4, 0, 0x0930, 1, 0),
-	MX6_PAD_SD2_CLK__KPP_COL_5		= IOMUX_PAD(0x06DC, 0x02F4, 2, 0x08C0, 3, 0),
-	MX6_PAD_SD2_CLK__AUDMUX_AUD4_RXFS	= IOMUX_PAD(0x06DC, 0x02F4, 3, 0x07A4, 1, 0),
-	MX6_PAD_SD2_CLK__PCIE_CTRL_DIAG_STATUS_BUS_MUX_9	= IOMUX_PAD(0x06DC, 0x02F4, 4, 0x0000, 0, 0),
-	MX6_PAD_SD2_CLK__GPIO_1_10		= IOMUX_PAD(0x06DC, 0x02F4, 5, 0x0000, 0, 0),
-	MX6_PAD_SD2_CLK__PHY_DTB_1		= IOMUX_PAD(0x06DC, 0x02F4, 6, 0x0000, 0, 0),
-	MX6_PAD_SD2_CMD__USDHC2_CMD		= IOMUX_PAD(0x06E0, 0x02F8, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0),
-	MX6_PAD_SD2_CMD__KPP_ROW_5		= IOMUX_PAD(0x06E0, 0x02F8, 2, 0x08CC, 2, 0),
-	MX6_PAD_SD2_CMD__AUDMUX_AUD4_RXC	= IOMUX_PAD(0x06E0, 0x02F8, 3, 0x07A0, 1, 0),
-	MX6_PAD_SD2_CMD__PCIE_CTRL_DIAG_STATUS_BUS_MUX_10	= IOMUX_PAD(0x06E0, 0x02F8, 4, 0x0000, 0, 0),
-	MX6_PAD_SD2_CMD__GPIO_1_11		= IOMUX_PAD(0x06E0, 0x02F8, 5, 0x0000, 0, 0),
-	MX6_PAD_SD2_DAT0__USDHC2_DAT0		= IOMUX_PAD(0x06E4, 0x02FC, 0, 0x0000, 0, 0),
-	MX6_PAD_SD2_DAT0__AUDMUX_AUD4_RXD	= IOMUX_PAD(0x06E4, 0x02FC, 3, 0x0798, 1, 0),
-	MX6_PAD_SD2_DAT0__KPP_ROW_7		= IOMUX_PAD(0x06E4, 0x02FC, 4, 0x08D4, 2, 0),
-	MX6_PAD_SD2_DAT0__GPIO_1_15		= IOMUX_PAD(0x06E4, 0x02FC, 5, 0x0000, 0, 0),
-	MX6_PAD_SD2_DAT0__DCIC2_DCIC_OUT	= IOMUX_PAD(0x06E4, 0x02FC, 6, 0x0000, 0, 0),
-	MX6_PAD_SD2_DAT0__ANATOP_ANATOP_TESTO_2	= IOMUX_PAD(0x06E4, 0x02FC, 7, 0x0000, 0, 0),
-	MX6_PAD_SD2_DAT1__USDHC2_DAT1		= IOMUX_PAD(0x06E8, 0x0300, 0, 0x0000, 0, 0),
-	MX6_PAD_SD2_DAT1__WEIM_WEIM_CS_2	= IOMUX_PAD(0x06E8, 0x0300, 2, 0x0000, 0, 0),
-	MX6_PAD_SD2_DAT1__AUDMUX_AUD4_TXFS	= IOMUX_PAD(0x06E8, 0x0300, 3, 0x07AC, 1, 0),
-	MX6_PAD_SD2_DAT1__KPP_COL_7		= IOMUX_PAD(0x06E8, 0x0300, 4, 0x08C8, 2, 0),
-	MX6_PAD_SD2_DAT1__GPIO_1_14		= IOMUX_PAD(0x06E8, 0x0300, 5, 0x0000, 0, 0),
-	MX6_PAD_SD2_DAT1__CCM_WAIT		= IOMUX_PAD(0x06E8, 0x0300, 6, 0x0000, 0, 0),
-	MX6_PAD_SD2_DAT1__ANATOP_ANATOP_TESTO_0	= IOMUX_PAD(0x06E8, 0x0300, 7, 0x0000, 0, 0),
-	MX6_PAD_SD2_DAT2__USDHC2_DAT2		= IOMUX_PAD(0x06EC, 0x0304, 0, 0x0000, 0, 0),
-	MX6_PAD_SD2_DAT2__WEIM_WEIM_CS_3	= IOMUX_PAD(0x06EC, 0x0304, 2, 0x0000, 0, 0),
-	MX6_PAD_SD2_DAT2__AUDMUX_AUD4_TXD	= IOMUX_PAD(0x06EC, 0x0304, 3, 0x079C, 1, 0),
-	MX6_PAD_SD2_DAT2__KPP_ROW_6		= IOMUX_PAD(0x06EC, 0x0304, 4, 0x08D0, 2, 0),
-	MX6_PAD_SD2_DAT2__GPIO_1_13		= IOMUX_PAD(0x06EC, 0x0304, 5, 0x0000, 0, 0),
-	MX6_PAD_SD2_DAT2__CCM_STOP		= IOMUX_PAD(0x06EC, 0x0304, 6, 0x0000, 0, 0),
-	MX6_PAD_SD2_DAT2__ANATOP_ANATOP_TESTO_1	= IOMUX_PAD(0x06EC, 0x0304, 7, 0x0000, 0, 0),
-	MX6_PAD_SD2_DAT3__USDHC2_DAT3		= IOMUX_PAD(0x06F0, 0x0308, 0, 0x0000, 0, 0),
-	MX6_PAD_SD2_DAT3__KPP_COL_6		= IOMUX_PAD(0x06F0, 0x0308, 2, 0x08C4, 2, 0),
-	MX6_PAD_SD2_DAT3__AUDMUX_AUD4_TXC	= IOMUX_PAD(0x06F0, 0x0308, 3, 0x07A8, 1, 0),
-	MX6_PAD_SD2_DAT3__PCIE_CTRL_DIAG_STATUS_BUS_MUX_11	= IOMUX_PAD(0x06F0, 0x0308, 4, 0x0000, 0, 0),
-	MX6_PAD_SD2_DAT3__GPIO_1_12		= IOMUX_PAD(0x06F0, 0x0308, 5, 0x0000, 0, 0),
-	MX6_PAD_SD2_DAT3__SJC_DONE		= IOMUX_PAD(0x06F0, 0x0308, 6, 0x0000, 0, 0),
-	MX6_PAD_SD2_DAT3__ANATOP_ANATOP_TESTO_3	= IOMUX_PAD(0x06F0, 0x0308, 7, 0x0000, 0, 0),
-	MX6_PAD_SD3_CLK__USDHC3_CLK		= IOMUX_PAD(0x06F4, 0x030C, 0, 0x0934, 1, 0),
-	MX6_PAD_SD3_CLK__UART2_CTS		= IOMUX_PAD(0x06F4, 0x030C, 1, 0x0000, 0, 0),
-	MX6_PAD_SD3_CLK__UART2_RTS		= IOMUX_PAD(0x06F4, 0x030C, 1, 0x0900, 2, 0),
-	MX6_PAD_SD3_CLK__CAN1_RXCAN		= IOMUX_PAD(0x06F4, 0x030C, 2, 0x07C8, 2, 0),
-	MX6_PAD_SD3_CLK__USBOH3_UH3_DFD_OUT_5	= IOMUX_PAD(0x06F4, 0x030C, 3, 0x0000, 0, 0),
-	MX6_PAD_SD3_CLK__USBOH3_UH2_DFD_OUT_5	= IOMUX_PAD(0x06F4, 0x030C, 4, 0x0000, 0, 0),
-	MX6_PAD_SD3_CLK__GPIO_7_3		= IOMUX_PAD(0x06F4, 0x030C, 5, 0x0000, 0, 0),
-	MX6_PAD_SD3_CLK__MIPI_CORE_DPHY_TEST_IN_17	= IOMUX_PAD(0x06F4, 0x030C, 6, 0x0000, 0, 0),
-	MX6_PAD_SD3_CLK__ANATOP_ANATOP_TESTO_14	= IOMUX_PAD(0x06F4, 0x030C, 7, 0x0000, 0, 0),
-	MX6_PAD_SD3_CMD__USDHC3_CMD		= IOMUX_PAD(0x06F8, 0x0310, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0),
-	MX6_PAD_SD3_CMD__UART2_CTS		= IOMUX_PAD(0x06F8, 0x0310, 1, 0x0000, 0, 0),
-	MX6_PAD_SD3_CMD__UART2_RTS		= IOMUX_PAD(0x06F8, 0x0310, 1, 0x0900, 3, 0),
-	MX6_PAD_SD3_CMD__CAN1_TXCAN		= IOMUX_PAD(0x06F8, 0x0310, 2, 0x0000, 0, 0),
-	MX6_PAD_SD3_CMD__USBOH3_UH3_DFD_OUT_4	= IOMUX_PAD(0x06F8, 0x0310, 3, 0x0000, 0, 0),
-	MX6_PAD_SD3_CMD__USBOH3_UH2_DFD_OUT_4	= IOMUX_PAD(0x06F8, 0x0310, 4, 0x0000, 0, 0),
-	MX6_PAD_SD3_CMD__GPIO_7_2		= IOMUX_PAD(0x06F8, 0x0310, 5, 0x0000, 0, 0),
-	MX6_PAD_SD3_CMD__MIPI_CORE_DPHY_TEST_IN_16	= IOMUX_PAD(0x06F8, 0x0310, 6, 0x0000, 0, 0),
-	MX6_PAD_SD3_CMD__ANATOP_ANATOP_TESTO_13	= IOMUX_PAD(0x06F8, 0x0310, 7, 0x0000, 0, 0),
-	MX6_PAD_SD3_DAT0__USDHC3_DAT0		= IOMUX_PAD(0x06FC, 0x0314, 0, 0x0000, 0, 0),
-	MX6_PAD_SD3_DAT0__UART1_CTS		= IOMUX_PAD(0x06FC, 0x0314, 1, 0x0000, 0, 0),
-	MX6_PAD_SD3_DAT0__UART1_RTS		= IOMUX_PAD(0x06FC, 0x0314, 1, 0x08F8, 2, 0),
-	MX6_PAD_SD3_DAT0__CAN2_TXCAN		= IOMUX_PAD(0x06FC, 0x0314, 2, 0x0000, 0, 0),
-	MX6_PAD_SD3_DAT0__USBOH3_UH3_DFD_OUT_6	= IOMUX_PAD(0x06FC, 0x0314, 3, 0x0000, 0, 0),
-	MX6_PAD_SD3_DAT0__USBOH3_UH2_DFD_OUT_6	= IOMUX_PAD(0x06FC, 0x0314, 4, 0x0000, 0, 0),
-	MX6_PAD_SD3_DAT0__GPIO_7_4		= IOMUX_PAD(0x06FC, 0x0314, 5, 0x0000, 0, 0),
-	MX6_PAD_SD3_DAT0__MIPI_CORE_DPHY_TEST_IN_18	= IOMUX_PAD(0x06FC, 0x0314, 6, 0x0000, 0, 0),
-	MX6_PAD_SD3_DAT0__ANATOP_ANATOP_TESTO_15	= IOMUX_PAD(0x06FC, 0x0314, 7, 0x0000, 0, 0),
-	MX6_PAD_SD3_DAT1__USDHC3_DAT1		= IOMUX_PAD(0x0700, 0x0318, 0, 0x0000, 0, 0),
-	MX6_PAD_SD3_DAT1__UART1_CTS		= IOMUX_PAD(0x0700, 0x0318, 1, 0x0000, 0, 0),
-	MX6_PAD_SD3_DAT1__UART1_RTS		= IOMUX_PAD(0x0700, 0x0318, 1, 0x08F8, 3, 0),
-	MX6_PAD_SD3_DAT1__CAN2_RXCAN		= IOMUX_PAD(0x0700, 0x0318, 2, 0x07CC, 1, 0),
-	MX6_PAD_SD3_DAT1__USBOH3_UH3_DFD_OUT_7	= IOMUX_PAD(0x0700, 0x0318, 3, 0x0000, 0, 0),
-	MX6_PAD_SD3_DAT1__USBOH3_UH2_DFD_OUT_7	= IOMUX_PAD(0x0700, 0x0318, 4, 0x0000, 0, 0),
-	MX6_PAD_SD3_DAT1__GPIO_7_5		= IOMUX_PAD(0x0700, 0x0318, 5, 0x0000, 0, 0),
-	MX6_PAD_SD3_DAT1__MIPI_CORE_DPHY_TEST_IN_19	= IOMUX_PAD(0x0700, 0x0318, 6, 0x0000, 0, 0),
-	MX6_PAD_SD3_DAT1__ANATOP_ANATOP_TESTI_0	= IOMUX_PAD(0x0700, 0x0318, 7, 0x0000, 0, 0),
-	MX6_PAD_SD3_DAT2__USDHC3_DAT2		= IOMUX_PAD(0x0704, 0x031C, 0, 0x0000, 0, 0),
-	MX6_PAD_SD3_DAT2__PCIE_CTRL_DIAG_STATUS_BUS_MUX_28	= IOMUX_PAD(0x0704, 0x031C, 2, 0x0000, 0, 0),
-	MX6_PAD_SD3_DAT2__USBOH3_UH3_DFD_OUT_8	= IOMUX_PAD(0x0704, 0x031C, 3, 0x0000, 0, 0),
-	MX6_PAD_SD3_DAT2__USBOH3_UH2_DFD_OUT_8	= IOMUX_PAD(0x0704, 0x031C, 4, 0x0000, 0, 0),
-	MX6_PAD_SD3_DAT2__GPIO_7_6		= IOMUX_PAD(0x0704, 0x031C, 5, 0x0000, 0, 0),
-	MX6_PAD_SD3_DAT2__MIPI_CORE_DPHY_TEST_IN_20	= IOMUX_PAD(0x0704, 0x031C, 6, 0x0000, 0, 0),
-	MX6_PAD_SD3_DAT2__ANATOP_ANATOP_TESTI_1	= IOMUX_PAD(0x0704, 0x031C, 7, 0x0000, 0, 0),
-	MX6_PAD_SD3_DAT3__USDHC3_DAT3		= IOMUX_PAD(0x0708, 0x0320, 0, 0x0000, 0, 0),
-	MX6_PAD_SD3_DAT3__UART3_CTS		= IOMUX_PAD(0x0708, 0x0320, 1, 0x0000, 0, 0),
-	MX6_PAD_SD3_DAT3__UART3_RTS		= IOMUX_PAD(0x0708, 0x0320, 1, 0x0908, 4, 0),
-	MX6_PAD_SD3_DAT3__PCIE_CTRL_DIAG_STATUS_BUS_MUX_29	= IOMUX_PAD(0x0708, 0x0320, 2, 0x0000, 0, 0),
-	MX6_PAD_SD3_DAT3__USBOH3_UH3_DFD_OUT_9	= IOMUX_PAD(0x0708, 0x0320, 3, 0x0000, 0, 0),
-	MX6_PAD_SD3_DAT3__USBOH3_UH2_DFD_OUT_9	= IOMUX_PAD(0x0708, 0x0320, 4, 0x0000, 0, 0),
-	MX6_PAD_SD3_DAT3__GPIO_7_7		= IOMUX_PAD(0x0708, 0x0320, 5, 0x0000, 0, 0),
-	MX6_PAD_SD3_DAT3__MIPI_CORE_DPHY_TEST_IN_21	= IOMUX_PAD(0x0708, 0x0320, 6, 0x0000, 0, 0),
-	MX6_PAD_SD3_DAT3__ANATOP_ANATOP_TESTI_2	= IOMUX_PAD(0x0708, 0x0320, 7, 0x0000, 0, 0),
-	MX6_PAD_SD3_DAT4__USDHC3_DAT4		= IOMUX_PAD(0x070C, 0x0324, 0, 0x0000, 0, 0),
-	MX6_PAD_SD3_DAT4__UART2_TXD		= IOMUX_PAD(0x070C, 0x0324, 1, 0x0000, 0, 0),
-	MX6_PAD_SD3_DAT4__UART2_RXD		= IOMUX_PAD(0x070C, 0x0324, 1, 0x0904, 4, 0),
-	MX6_PAD_SD3_DAT4__PCIE_CTRL_DIAG_STATUS_BUS_MUX_27	= IOMUX_PAD(0x070C, 0x0324, 2, 0x0000, 0, 0),
-	MX6_PAD_SD3_DAT4__USBOH3_UH3_DFD_OUT_3	= IOMUX_PAD(0x070C, 0x0324, 3, 0x0000, 0, 0),
-	MX6_PAD_SD3_DAT4__USBOH3_UH2_DFD_OUT_3	= IOMUX_PAD(0x070C, 0x0324, 4, 0x0000, 0, 0),
-	MX6_PAD_SD3_DAT4__GPIO_7_1		= IOMUX_PAD(0x070C, 0x0324, 5, 0x0000, 0, 0),
-	MX6_PAD_SD3_DAT4__MIPI_CORE_DPHY_TEST_IN_15	= IOMUX_PAD(0x070C, 0x0324, 6, 0x0000, 0, 0),
-	MX6_PAD_SD3_DAT4__ANATOP_ANATOP_TESTO_12	= IOMUX_PAD(0x070C, 0x0324, 7, 0x0000, 0, 0),
-	MX6_PAD_SD3_DAT5__USDHC3_DAT5		= IOMUX_PAD(0x0710, 0x0328, 0, 0x0000, 0, 0),
-	MX6_PAD_SD3_DAT5__UART2_TXD		= IOMUX_PAD(0x0710, 0x0328, 1, 0x0000, 0, 0),
-	MX6_PAD_SD3_DAT5__UART2_RXD		= IOMUX_PAD(0x0710, 0x0328, 1, 0x0904, 5, 0),
-	MX6_PAD_SD3_DAT5__PCIE_CTRL_DIAG_STATUS_BUS_MUX_26	= IOMUX_PAD(0x0710, 0x0328, 2, 0x0000, 0, 0),
-	MX6_PAD_SD3_DAT5__USBOH3_UH3_DFD_OUT_2	= IOMUX_PAD(0x0710, 0x0328, 3, 0x0000, 0, 0),
-	MX6_PAD_SD3_DAT5__USBOH3_UH2_DFD_OUT_2	= IOMUX_PAD(0x0710, 0x0328, 4, 0x0000, 0, 0),
-	MX6_PAD_SD3_DAT5__GPIO_7_0		= IOMUX_PAD(0x0710, 0x0328, 5, 0x0000, 0, 0),
-	MX6_PAD_SD3_DAT5__MIPI_CORE_DPHY_TEST_IN_14	= IOMUX_PAD(0x0710, 0x0328, 6, 0x0000, 0, 0),
-	MX6_PAD_SD3_DAT5__ANATOP_ANATOP_TESTO_11	= IOMUX_PAD(0x0710, 0x0328, 7, 0x0000, 0, 0),
-	MX6_PAD_SD3_DAT6__USDHC3_DAT6		= IOMUX_PAD(0x0714, 0x032C, 0, 0x0000, 0, 0),
-	MX6_PAD_SD3_DAT6__UART1_TXD		= IOMUX_PAD(0x0714, 0x032C, 1, 0x0000, 0, 0),
-	MX6_PAD_SD3_DAT6__UART1_RXD		= IOMUX_PAD(0x0714, 0x032C, 1, 0x08FC, 2, 0),
-	MX6_PAD_SD3_DAT6__PCIE_CTRL_DIAG_STATUS_BUS_MUX_25	= IOMUX_PAD(0x0714, 0x032C, 2, 0x0000, 0, 0),
-	MX6_PAD_SD3_DAT6__USBOH3_UH3_DFD_OUT_1	= IOMUX_PAD(0x0714, 0x032C, 3, 0x0000, 0, 0),
-	MX6_PAD_SD3_DAT6__USBOH3_UH2_DFD_OUT_1	= IOMUX_PAD(0x0714, 0x032C, 4, 0x0000, 0, 0),
-	MX6_PAD_SD3_DAT6__GPIO_6_18		= IOMUX_PAD(0x0714, 0x032C, 5, 0x0000, 0, 0),
-	MX6_PAD_SD3_DAT6__MIPI_CORE_DPHY_TEST_IN_13	= IOMUX_PAD(0x0714, 0x032C, 6, 0x0000, 0, 0),
-	MX6_PAD_SD3_DAT6__ANATOP_ANATOP_TESTO_10	= IOMUX_PAD(0x0714, 0x032C, 7, 0x0000, 0, 0),
-	MX6_PAD_SD3_DAT7__USDHC3_DAT7		= IOMUX_PAD(0x0718, 0x0330, 0, 0x0000, 0, 0),
-	MX6_PAD_SD3_DAT7__UART1_TXD		= IOMUX_PAD(0x0718, 0x0330, 1, 0x0000, 0, 0),
-	MX6_PAD_SD3_DAT7__UART1_RXD		= IOMUX_PAD(0x0718, 0x0330, 1, 0x08FC, 3, 0),
-	MX6_PAD_SD3_DAT7__PCIE_CTRL_DIAG_STATUS_BUS_MUX_24	= IOMUX_PAD(0x0718, 0x0330, 2, 0x0000, 0, 0),
-	MX6_PAD_SD3_DAT7__USBOH3_UH3_DFD_OUT_0	= IOMUX_PAD(0x0718, 0x0330, 3, 0x0000, 0, 0),
-	MX6_PAD_SD3_DAT7__USBOH3_UH2_DFD_OUT_0	= IOMUX_PAD(0x0718, 0x0330, 4, 0x0000, 0, 0),
-	MX6_PAD_SD3_DAT7__GPIO_6_17		= IOMUX_PAD(0x0718, 0x0330, 5, 0x0000, 0, 0),
-	MX6_PAD_SD3_DAT7__MIPI_CORE_DPHY_TEST_IN_12	= IOMUX_PAD(0x0718, 0x0330, 6, 0x0000, 0, 0),
-	MX6_PAD_SD3_DAT7__ANATOP_USBPHY2_TSTO_PLL_CLK20DIV	= IOMUX_PAD(0x0718, 0x0330, 7, 0x0000, 0, 0),
-	MX6_PAD_SD3_RST__USDHC3_RST		= IOMUX_PAD(0x071C, 0x0334, 0, 0x0000, 0, 0),
-	MX6_PAD_SD3_RST__UART3_CTS		= IOMUX_PAD(0x071C, 0x0334, 1, 0x0000, 0, 0),
-	MX6_PAD_SD3_RST__UART3_RTS		= IOMUX_PAD(0x071C, 0x0334, 1, 0x0908, 5, 0),
-	MX6_PAD_SD3_RST__PCIE_CTRL_DIAG_STATUS_BUS_MUX_30	= IOMUX_PAD(0x071C, 0x0334, 2, 0x0000, 0, 0),
-	MX6_PAD_SD3_RST__USBOH3_UH3_DFD_OUT_10	= IOMUX_PAD(0x071C, 0x0334, 3, 0x0000, 0, 0),
-	MX6_PAD_SD3_RST__USBOH3_UH2_DFD_OUT_10	= IOMUX_PAD(0x071C, 0x0334, 4, 0x0000, 0, 0),
-	MX6_PAD_SD3_RST__GPIO_7_8		= IOMUX_PAD(0x071C, 0x0334, 5, 0x0000, 0, 0),
-	MX6_PAD_SD3_RST__MIPI_CORE_DPHY_TEST_IN_22	= IOMUX_PAD(0x071C, 0x0334, 6, 0x0000, 0, 0),
-	MX6_PAD_SD3_RST__ANATOP_ANATOP_TESTI_3	= IOMUX_PAD(0x071C, 0x0334, 7, 0x0000, 0, 0),
-	MX6_PAD_SD4_CLK__USDHC4_CLK		= IOMUX_PAD(0x0720, 0x0338, 0, 0x0938, 1, 0),
-	MX6_PAD_SD4_CLK__RAWNAND_WRN		= IOMUX_PAD(0x0720, 0x0338, 1, 0x0000, 0, 0),
-	MX6_PAD_SD4_CLK__UART3_TXD		= IOMUX_PAD(0x0720, 0x0338, 2, 0x0000, 0, 0),
-	MX6_PAD_SD4_CLK__UART3_RXD		= IOMUX_PAD(0x0720, 0x0338, 2, 0x090C, 2, 0),
-	MX6_PAD_SD4_CLK__PCIE_CTRL_DIAG_STATUS_BUS_MUX_6	= IOMUX_PAD(0x0720, 0x0338, 4, 0x0000, 0, 0),
-	MX6_PAD_SD4_CLK__GPIO_7_10		= IOMUX_PAD(0x0720, 0x0338, 5, 0x0000, 0, 0),
-	MX6_PAD_SD4_CMD__USDHC4_CMD		= IOMUX_PAD(0x0724, 0x033C, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0),
-	MX6_PAD_SD4_CMD__RAWNAND_RDN		= IOMUX_PAD(0x0724, 0x033C, 1, 0x0000, 0, 0),
-	MX6_PAD_SD4_CMD__UART3_TXD		= IOMUX_PAD(0x0724, 0x033C, 2, 0x0000, 0, 0),
-	MX6_PAD_SD4_CMD__UART3_RXD		= IOMUX_PAD(0x0724, 0x033C, 2, 0x090C, 3, 0),
-	MX6_PAD_SD4_CMD__PCIE_CTRL_DIAG_STATUS_BUS_MUX_5	= IOMUX_PAD(0x0724, 0x033C, 4, 0x0000, 0, 0),
-	MX6_PAD_SD4_CMD__GPIO_7_9		= IOMUX_PAD(0x0724, 0x033C, 5, 0x0000, 0, 0),
-	MX6_PAD_SD4_DAT0__RAWNAND_D8		= IOMUX_PAD(0x0728, 0x0340, 0, 0x0000, 0, 0),
-	MX6_PAD_SD4_DAT0__USDHC4_DAT0		= IOMUX_PAD(0x0728, 0x0340, 1, 0x0000, 0, 0),
-	MX6_PAD_SD4_DAT0__RAWNAND_DQS		= IOMUX_PAD(0x0728, 0x0340, 2, 0x0000, 0, 0),
-	MX6_PAD_SD4_DAT0__USBOH3_UH2_DFD_OUT_24	= IOMUX_PAD(0x0728, 0x0340, 3, 0x0000, 0, 0),
-	MX6_PAD_SD4_DAT0__USBOH3_UH3_DFD_OUT_24	= IOMUX_PAD(0x0728, 0x0340, 4, 0x0000, 0, 0),
-	MX6_PAD_SD4_DAT0__GPIO_2_8		= IOMUX_PAD(0x0728, 0x0340, 5, 0x0000, 0, 0),
-	MX6_PAD_SD4_DAT0__IPU1_IPU_DIAG_BUS_8	= IOMUX_PAD(0x0728, 0x0340, 6, 0x0000, 0, 0),
-	MX6_PAD_SD4_DAT1__RAWNAND_D9		= IOMUX_PAD(0x072C, 0x0344, 0, 0x0000, 0, 0),
-	MX6_PAD_SD4_DAT1__USDHC4_DAT1		= IOMUX_PAD(0x072C, 0x0344, 1, 0x0000, 0, 0),
-	MX6_PAD_SD4_DAT1__PWM3_PWMO		= IOMUX_PAD(0x072C, 0x0344, 2, 0x0000, 0, 0),
-	MX6_PAD_SD4_DAT1__USBOH3_UH2_DFD_OUT_25	= IOMUX_PAD(0x072C, 0x0344, 3, 0x0000, 0, 0),
-	MX6_PAD_SD4_DAT1__USBOH3_UH3_DFD_OUT_25	= IOMUX_PAD(0x072C, 0x0344, 4, 0x0000, 0, 0),
-	MX6_PAD_SD4_DAT1__GPIO_2_9		= IOMUX_PAD(0x072C, 0x0344, 5, 0x0000, 0, 0),
-	MX6_PAD_SD4_DAT1__IPU1_IPU_DIAG_BUS_9	= IOMUX_PAD(0x072C, 0x0344, 6, 0x0000, 0, 0),
-	MX6_PAD_SD4_DAT2__RAWNAND_D10		= IOMUX_PAD(0x0730, 0x0348, 0, 0x0000, 0, 0),
-	MX6_PAD_SD4_DAT2__USDHC4_DAT2		= IOMUX_PAD(0x0730, 0x0348, 1, 0x0000, 0, 0),
-	MX6_PAD_SD4_DAT2__PWM4_PWMO		= IOMUX_PAD(0x0730, 0x0348, 2, 0x0000, 0, 0),
-	MX6_PAD_SD4_DAT2__USBOH3_UH2_DFD_OUT_26	= IOMUX_PAD(0x0730, 0x0348, 3, 0x0000, 0, 0),
-	MX6_PAD_SD4_DAT2__USBOH3_UH3_DFD_OUT_26	= IOMUX_PAD(0x0730, 0x0348, 4, 0x0000, 0, 0),
-	MX6_PAD_SD4_DAT2__GPIO_2_10		= IOMUX_PAD(0x0730, 0x0348, 5, 0x0000, 0, 0),
-	MX6_PAD_SD4_DAT2__IPU1_IPU_DIAG_BUS_10	= IOMUX_PAD(0x0730, 0x0348, 6, 0x0000, 0, 0),
-	MX6_PAD_SD4_DAT3__RAWNAND_D11		= IOMUX_PAD(0x0734, 0x034C, 0, 0x0000, 0, 0),
-	MX6_PAD_SD4_DAT3__USDHC4_DAT3		= IOMUX_PAD(0x0734, 0x034C, 1, 0x0000, 0, 0),
-	MX6_PAD_SD4_DAT3__USBOH3_UH2_DFD_OUT_27	= IOMUX_PAD(0x0734, 0x034C, 3, 0x0000, 0, 0),
-	MX6_PAD_SD4_DAT3__USBOH3_UH3_DFD_OUT_27	= IOMUX_PAD(0x0734, 0x034C, 4, 0x0000, 0, 0),
-	MX6_PAD_SD4_DAT3__GPIO_2_11		= IOMUX_PAD(0x0734, 0x034C, 5, 0x0000, 0, 0),
-	MX6_PAD_SD4_DAT3__IPU1_IPU_DIAG_BUS_11	= IOMUX_PAD(0x0734, 0x034C, 6, 0x0000, 0, 0),
-	MX6_PAD_SD4_DAT4__RAWNAND_D12		= IOMUX_PAD(0x0738, 0x0350, 0, 0x0000, 0, 0),
-	MX6_PAD_SD4_DAT4__USDHC4_DAT4		= IOMUX_PAD(0x0738, 0x0350, 1, 0x0000, 0, 0),
-	MX6_PAD_SD4_DAT4__UART2_TXD		= IOMUX_PAD(0x0738, 0x0350, 2, 0x0000, 0, 0),
-	MX6_PAD_SD4_DAT4__UART2_RXD		= IOMUX_PAD(0x0738, 0x0350, 2, 0x0904, 6, 0),
-	MX6_PAD_SD4_DAT4__USBOH3_UH2_DFD_OUT_28	= IOMUX_PAD(0x0738, 0x0350, 3, 0x0000, 0, 0),
-	MX6_PAD_SD4_DAT4__USBOH3_UH3_DFD_OUT_28	= IOMUX_PAD(0x0738, 0x0350, 4, 0x0000, 0, 0),
-	MX6_PAD_SD4_DAT4__GPIO_2_12		= IOMUX_PAD(0x0738, 0x0350, 5, 0x0000, 0, 0),
-	MX6_PAD_SD4_DAT4__IPU1_IPU_DIAG_BUS_12	= IOMUX_PAD(0x0738, 0x0350, 6, 0x0000, 0, 0),
-	MX6_PAD_SD4_DAT5__RAWNAND_D13		= IOMUX_PAD(0x073C, 0x0354, 0, 0x0000, 0, 0),
-	MX6_PAD_SD4_DAT5__USDHC4_DAT5		= IOMUX_PAD(0x073C, 0x0354, 1, 0x0000, 0, 0),
-	MX6_PAD_SD4_DAT5__UART2_CTS		= IOMUX_PAD(0x073C, 0x0354, 2, 0x0000, 0, 0),
-	MX6_PAD_SD4_DAT5__UART2_RTS		= IOMUX_PAD(0x073C, 0x0354, 2, 0x0900, 4, 0),
-	MX6_PAD_SD4_DAT5__USBOH3_UH2_DFD_OUT_29	= IOMUX_PAD(0x073C, 0x0354, 3, 0x0000, 0, 0),
-	MX6_PAD_SD4_DAT5__USBOH3_UH3_DFD_OUT_29	= IOMUX_PAD(0x073C, 0x0354, 4, 0x0000, 0, 0),
-	MX6_PAD_SD4_DAT5__GPIO_2_13		= IOMUX_PAD(0x073C, 0x0354, 5, 0x0000, 0, 0),
-	MX6_PAD_SD4_DAT5__IPU1_IPU_DIAG_BUS_13	= IOMUX_PAD(0x073C, 0x0354, 6, 0x0000, 0, 0),
-	MX6_PAD_SD4_DAT6__RAWNAND_D14		= IOMUX_PAD(0x0740, 0x0358, 0, 0x0000, 0, 0),
-	MX6_PAD_SD4_DAT6__USDHC4_DAT6		= IOMUX_PAD(0x0740, 0x0358, 1, 0x0000, 0, 0),
-	MX6_PAD_SD4_DAT6__UART2_CTS		= IOMUX_PAD(0x0740, 0x0358, 2, 0x0000, 0, 0),
-	MX6_PAD_SD4_DAT6__UART2_RTS		= IOMUX_PAD(0x0740, 0x0358, 2, 0x0900, 5, 0),
-	MX6_PAD_SD4_DAT6__USBOH3_UH2_DFD_OUT_30	= IOMUX_PAD(0x0740, 0x0358, 3, 0x0000, 0, 0),
-	MX6_PAD_SD4_DAT6__USBOH3_UH3_DFD_OUT_30	= IOMUX_PAD(0x0740, 0x0358, 4, 0x0000, 0, 0),
-	MX6_PAD_SD4_DAT6__GPIO_2_14		= IOMUX_PAD(0x0740, 0x0358, 5, 0x0000, 0, 0),
-	MX6_PAD_SD4_DAT6__IPU1_IPU_DIAG_BUS_14	= IOMUX_PAD(0x0740, 0x0358, 6, 0x0000, 0, 0),
-	MX6_PAD_SD4_DAT7__RAWNAND_D15		= IOMUX_PAD(0x0744, 0x035C, 0, 0x0000, 0, 0),
-	MX6_PAD_SD4_DAT7__USDHC4_DAT7		= IOMUX_PAD(0x0744, 0x035C, 1, 0x0000, 0, 0),
-	MX6_PAD_SD4_DAT7__UART2_TXD		= IOMUX_PAD(0x0744, 0x035C, 2, 0x0000, 0, 0),
-	MX6_PAD_SD4_DAT7__UART2_RXD		= IOMUX_PAD(0x0744, 0x035C, 2, 0x0904, 7, 0),
-	MX6_PAD_SD4_DAT7__USBOH3_UH2_DFD_OUT_31	= IOMUX_PAD(0x0744, 0x035C, 3, 0x0000, 0, 0),
-	MX6_PAD_SD4_DAT7__USBOH3_UH3_DFD_OUT_31	= IOMUX_PAD(0x0744, 0x035C, 4, 0x0000, 0, 0),
-	MX6_PAD_SD4_DAT7__GPIO_2_15		= IOMUX_PAD(0x0744, 0x035C, 5, 0x0000, 0, 0),
-	MX6_PAD_SD4_DAT7__IPU1_IPU_DIAG_BUS_15	= IOMUX_PAD(0x0744, 0x035C, 6, 0x0000, 0, 0),
-};
 #endif	/* __ASM_ARCH_MX6_MX6DL_PINS_H__ */
diff --git a/arch/arm/include/asm/arch-mx6/mx6q_pins.h b/arch/arm/include/asm/arch-mx6/mx6q_pins.h
index fe9a8c343d..a8456a284a 100644
--- a/arch/arm/include/asm/arch-mx6/mx6q_pins.h
+++ b/arch/arm/include/asm/arch-mx6/mx6q_pins.h
@@ -9,1624 +9,1028 @@
 #ifndef __ASM_ARCH_MX6_MX6Q_PINS_H__
 #define __ASM_ARCH_MX6_MX6Q_PINS_H__
 
-#include <asm/imx-common/iomux-v3.h>
-
-enum {
-	MX6_PAD_SD2_DAT1__USDHC2_DAT1		= IOMUX_PAD(0x0360, 0x004C, 0, 0x0000, 0, 0),
-	MX6_PAD_SD2_DAT1__ECSPI5_SS0		= IOMUX_PAD(0x0360, 0x004C, 1, 0x0834, 0, 0),
-	MX6_PAD_SD2_DAT1__WEIM_WEIM_CS_2	= IOMUX_PAD(0x0360, 0x004C, 2, 0x0000, 0, 0),
-	MX6_PAD_SD2_DAT1__AUDMUX_AUD4_TXFS	= IOMUX_PAD(0x0360, 0x004C, 3, 0x07C8, 0, 0),
-	MX6_PAD_SD2_DAT1__KPP_COL_7		= IOMUX_PAD(0x0360, 0x004C, 4, 0x08F0, 0, 0),
-	MX6_PAD_SD2_DAT1__GPIO_1_14		= IOMUX_PAD(0x0360, 0x004C, 5, 0x0000, 0, 0),
-	MX6_PAD_SD2_DAT1__CCM_WAIT		= IOMUX_PAD(0x0360, 0x004C, 6, 0x0000, 0, 0),
-	MX6_PAD_SD2_DAT1__ANATOP_TESTO_0	= IOMUX_PAD(0x0360, 0x004C, 7, 0x0000, 0, 0),
-	MX6_PAD_SD2_DAT2__USDHC2_DAT2		= IOMUX_PAD(0x0364, 0x0050, 0, 0x0000, 0, 0),
-	MX6_PAD_SD2_DAT2__ECSPI5_SS1		= IOMUX_PAD(0x0364, 0x0050, 1, 0x0838, 0, 0),
-	MX6_PAD_SD2_DAT2__WEIM_WEIM_CS_3	= IOMUX_PAD(0x0364, 0x0050, 2, 0x0000, 0, 0),
-	MX6_PAD_SD2_DAT2__AUDMUX_AUD4_TXD	= IOMUX_PAD(0x0364, 0x0050, 3, 0x07B8, 0, 0),
-	MX6_PAD_SD2_DAT2__KPP_ROW_6		= IOMUX_PAD(0x0364, 0x0050, 4, 0x08F8, 0, 0),
-	MX6_PAD_SD2_DAT2__GPIO_1_13		= IOMUX_PAD(0x0364, 0x0050, 5, 0x0000, 0, 0),
-	MX6_PAD_SD2_DAT2__CCM_STOP		= IOMUX_PAD(0x0364, 0x0050, 6, 0x0000, 0, 0),
-	MX6_PAD_SD2_DAT2__ANATOP_TESTO_1	= IOMUX_PAD(0x0364, 0x0050, 7, 0x0000, 0, 0),
-	MX6_PAD_SD2_DAT0__USDHC2_DAT0		= IOMUX_PAD(0x0368, 0x0054, 0, 0x0000, 0, 0),
-	MX6_PAD_SD2_DAT0__ECSPI5_MISO		= IOMUX_PAD(0x0368, 0x0054, 1, 0x082C, 0, 0),
-	MX6_PAD_SD2_DAT0__AUDMUX_AUD4_RXD	= IOMUX_PAD(0x0368, 0x0054, 3, 0x07B4, 0, 0),
-	MX6_PAD_SD2_DAT0__KPP_ROW_7		= IOMUX_PAD(0x0368, 0x0054, 4, 0x08FC, 0, 0),
-	MX6_PAD_SD2_DAT0__GPIO_1_15		= IOMUX_PAD(0x0368, 0x0054, 5, 0x0000, 0, 0),
-	MX6_PAD_SD2_DAT0__DCIC2_DCIC_OUT	= IOMUX_PAD(0x0368, 0x0054, 6, 0x0000, 0, 0),
-	MX6_PAD_SD2_DAT0__TESTO_2		= IOMUX_PAD(0x0368, 0x0054, 7, 0x0000, 0, 0),
-	MX6_PAD_RGMII_TXC__USBOH3_H2_DATA	= IOMUX_PAD(0x036C, 0x0058, 0, 0x0000, 0, 0),
-	MX6_PAD_RGMII_TXC__ENET_RGMII_TXC	= IOMUX_PAD(0x036C, 0x0058, 1, 0x0000, 0, 0),
-	MX6_PAD_RGMII_TXC__SPDIF_SPDIF_EXTCLK	= IOMUX_PAD(0x036C, 0x0058, 2, 0x0918, 0, 0),
-	MX6_PAD_RGMII_TXC__GPIO_6_19		= IOMUX_PAD(0x036C, 0x0058, 5, 0x0000, 0, 0),
-	MX6_PAD_RGMII_TXC__MIPI_CORE_DPHY_IN_0 = IOMUX_PAD(0x036C, 0x0058, 6, 0x0000, 0, 0),
-	MX6_PAD_RGMII_TXC__ANATOP_24M_OUT	= IOMUX_PAD(0x036C, 0x0058, 7, 0x0000, 0, 0),
-	MX6_PAD_RGMII_TD0__MIPI_HSI_CRL_TX_RDY = IOMUX_PAD(0x0370, 0x005C, 0, 0x0000, 0, 0),
-	MX6_PAD_RGMII_TD0__ENET_RGMII_TD0	= IOMUX_PAD(0x0370, 0x005C, 1, 0x0000, 0, 0),
-	MX6_PAD_RGMII_TD0__GPIO_6_20		= IOMUX_PAD(0x0370, 0x005C, 5, 0x0000, 0, 0),
-	MX6_PAD_RGMII_TD0__MIPI_CORE_DPHY_IN_1 = IOMUX_PAD(0x0370, 0x005C, 6, 0x0000, 0, 0),
-	MX6_PAD_RGMII_TD1__MIPI_HSI_CRL_RX_FLG = IOMUX_PAD(0x0374, 0x0060, 0, 0x0000, 0, 0),
-	MX6_PAD_RGMII_TD1__ENET_RGMII_TD1	= IOMUX_PAD(0x0374, 0x0060, 1, 0x0000, 0, 0),
-	MX6_PAD_RGMII_TD1__GPIO_6_21		= IOMUX_PAD(0x0374, 0x0060, 5, 0x0000, 0, 0),
-	MX6_PAD_RGMII_TD1__MIPI_CORE_DPHY_IN_2 = IOMUX_PAD(0x0374, 0x0060, 6, 0x0000, 0, 0),
-	MX6_PAD_RGMII_TD1__CCM_PLL3_BYP	= IOMUX_PAD(0x0374, 0x0060, 7, 0x0000, 0, 0),
-	MX6_PAD_RGMII_TD2__MIPI_HSI_CRL_RX_DTA = IOMUX_PAD(0x0378, 0x0064, 0, 0x0000, 0, 0),
-	MX6_PAD_RGMII_TD2__ENET_RGMII_TD2	= IOMUX_PAD(0x0378, 0x0064, 1, 0x0000, 0, 0),
-	MX6_PAD_RGMII_TD2__GPIO_6_22		= IOMUX_PAD(0x0378, 0x0064, 5, 0x0000, 0, 0),
-	MX6_PAD_RGMII_TD2__MIPI_CORE_DPHY_IN_3 = IOMUX_PAD(0x0378, 0x0064, 6, 0x0000, 0, 0),
-	MX6_PAD_RGMII_TD2__CCM_PLL2_BYP	= IOMUX_PAD(0x0378, 0x0064, 7, 0x0000, 0, 0),
-	MX6_PAD_RGMII_TD3__MIPI_HSI_CRL_RX_WAK = IOMUX_PAD(0x037C, 0x0068, 0, 0x0000, 0, 0),
-	MX6_PAD_RGMII_TD3__ENET_RGMII_TD3	= IOMUX_PAD(0x037C, 0x0068, 1, 0x0000, 0, 0),
-	MX6_PAD_RGMII_TD3__GPIO_6_23		= IOMUX_PAD(0x037C, 0x0068, 5, 0x0000, 0, 0),
-	MX6_PAD_RGMII_TD3__MIPI_CORE_DPHY_IN_4 = IOMUX_PAD(0x037C, 0x0068, 6, 0x0000, 0, 0),
-	MX6_PAD_RGMII_RX_CTL__USBOH3_H3_DATA   = IOMUX_PAD(0x0380, 0x006C, 0, 0x0000, 0, 0),
-	MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL	= IOMUX_PAD(0x0380, 0x006C, 1, 0x0858, 0, 0),
-	MX6_PAD_RGMII_RX_CTL__GPIO_6_24	= IOMUX_PAD(0x0380, 0x006C, 5, 0x0000, 0, 0),
-	MX6_PAD_RGMII_RX_CTL__MIPI_DPHY_IN_5	= IOMUX_PAD(0x0380, 0x006C, 6, 0x0000, 0, 0),
-	MX6_PAD_RGMII_RD0__MIPI_HSI_CRL_RX_RDY = IOMUX_PAD(0x0384, 0x0070, 0, 0x0000, 0, 0),
-	MX6_PAD_RGMII_RD0__ENET_RGMII_RD0      = IOMUX_PAD(0x0384, 0x0070, 1, 0x0848, 0, 0),
-	MX6_PAD_RGMII_RD0__GPIO_6_25		= IOMUX_PAD(0x0384, 0x0070, 5, 0x0000, 0, 0),
-	MX6_PAD_RGMII_RD0__MIPI_CORE_DPHY_IN_6 = IOMUX_PAD(0x0384, 0x0070, 6, 0x0000, 0, 0),
-	MX6_PAD_RGMII_TX_CTL__USBOH3_H2_STROBE = IOMUX_PAD(0x0388, 0x0074, 0, 0x0000, 0, 0),
-	MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL	= IOMUX_PAD(0x0388, 0x0074, 1, 0x0000, 0, 0),
-	MX6_PAD_RGMII_TX_CTL__GPIO_6_26	= IOMUX_PAD(0x0388, 0x0074, 5, 0x0000, 0, 0),
-	MX6_PAD_RGMII_TX_CTL__CORE_DPHY_IN_7	= IOMUX_PAD(0x0388, 0x0074, 6, 0x0000, 0, 0),
-	MX6_PAD_RGMII_TX_CTL__ANATOP_REF_OUT	= IOMUX_PAD(0x0388, 0x0074, 7, 0x083C, 0, 0),
-	MX6_PAD_RGMII_RD1__MIPI_HSI_CTRL_TX_FL = IOMUX_PAD(0x038C, 0x0078, 0, 0x0000, 0, 0),
-	MX6_PAD_RGMII_RD1__ENET_RGMII_RD1	= IOMUX_PAD(0x038C, 0x0078, 1, 0x084C, 0, 0),
-	MX6_PAD_RGMII_RD1__GPIO_6_27		= IOMUX_PAD(0x038C, 0x0078, 5, 0x0000, 0, 0),
-	MX6_PAD_RGMII_RD1__CORE_DPHY_TEST_IN_8 = IOMUX_PAD(0x038C, 0x0078, 6, 0x0000, 0, 0),
-	MX6_PAD_RGMII_RD1__SJC_FAIL		= IOMUX_PAD(0x038C, 0x0078, 7, 0x0000, 0, 0),
-	MX6_PAD_RGMII_RD2__MIPI_HSI_CRL_TX_DTA = IOMUX_PAD(0x0390, 0x007C, 0, 0x0000, 0, 0),
-	MX6_PAD_RGMII_RD2__ENET_RGMII_RD2	= IOMUX_PAD(0x0390, 0x007C, 1, 0x0850, 0, 0),
-	MX6_PAD_RGMII_RD2__GPIO_6_28		= IOMUX_PAD(0x0390, 0x007C, 5, 0x0000, 0, 0),
-	MX6_PAD_RGMII_RD2__MIPI_CORE_DPHY_IN_9 = IOMUX_PAD(0x0390, 0x007C, 6, 0x0000, 0, 0),
-	MX6_PAD_RGMII_RD3__MIPI_HSI_CRL_TX_WAK = IOMUX_PAD(0x0394, 0x0080, 0, 0x0000, 0, 0),
-	MX6_PAD_RGMII_RD3__ENET_RGMII_RD3	= IOMUX_PAD(0x0394, 0x0080, 1, 0x0854, 0, 0),
-	MX6_PAD_RGMII_RD3__GPIO_6_29		= IOMUX_PAD(0x0394, 0x0080, 5, 0x0000, 0, 0),
-	MX6_PAD_RGMII_RD3__MIPI_CORE_DPHY_IN10 = IOMUX_PAD(0x0394, 0x0080, 6, 0x0000, 0, 0),
-	MX6_PAD_RGMII_RXC__USBOH3_H3_STROBE    = IOMUX_PAD(0x0398, 0x0084, 0, 0x0000, 0, 0),
-	MX6_PAD_RGMII_RXC__ENET_RGMII_RXC	= IOMUX_PAD(0x0398, 0x0084, 1, 0x0844, 0, 0),
-	MX6_PAD_RGMII_RXC__GPIO_6_30		= IOMUX_PAD(0x0398, 0x0084, 5, 0x0000, 0, 0),
-	MX6_PAD_RGMII_RXC__MIPI_CORE_DPHY_IN11 = IOMUX_PAD(0x0398, 0x0084, 6, 0x0000, 0, 0),
-	MX6_PAD_EIM_A25__WEIM_WEIM_A_25	= IOMUX_PAD(0x039C, 0x0088, 0, 0x0000, 0, 0),
-	MX6_PAD_EIM_A25__ECSPI4_SS1		= IOMUX_PAD(0x039C, 0x0088, 1, 0x0000, 0, 0),
-	MX6_PAD_EIM_A25__ECSPI2_RDY		= IOMUX_PAD(0x039C, 0x0088, 2, 0x0000, 0, 0),
-	MX6_PAD_EIM_A25__IPU1_DI1_PIN12	= IOMUX_PAD(0x039C, 0x0088, 3, 0x0000, 0, 0),
-	MX6_PAD_EIM_A25__IPU1_DI0_D1_CS	= IOMUX_PAD(0x039C, 0x0088, 4, 0x0000, 0, 0),
-	MX6_PAD_EIM_A25__GPIO_5_2		= IOMUX_PAD(0x039C, 0x0088, 5, 0x0000, 0, 0),
-	MX6_PAD_EIM_A25__HDMI_TX_CEC_LINE	= IOMUX_PAD(0x039C, 0x0088, 6, 0x088C, 0, 0),
-	MX6_PAD_EIM_A25__PL301_PER1_HBURST_0	= IOMUX_PAD(0x039C, 0x0088, 7, 0x0000, 0, 0),
-	MX6_PAD_EIM_EB2__WEIM_WEIM_EB_2	= IOMUX_PAD(0x03A0, 0x008C, 0, 0x0000, 0, 0),
-	MX6_PAD_EIM_EB2__ECSPI1_SS0		= IOMUX_PAD(0x03A0, 0x008C, 1, 0x0800, 0, 0),
-	MX6_PAD_EIM_EB2__CCM_DI1_EXT_CLK	= IOMUX_PAD(0x03A0, 0x008C, 2, 0x07EC, 0, 0),
-	MX6_PAD_EIM_EB2__IPU2_CSI1_D_19	= IOMUX_PAD(0x03A0, 0x008C, 3, 0x08D4, 0, 0),
-	MX6_PAD_EIM_EB2__HDMI_TX_DDC_SCL	= IOMUX_PAD(0x03A0, 0x008C, 4, 0x0890, 0, 0),
-	MX6_PAD_EIM_EB2__GPIO_2_30		= IOMUX_PAD(0x03A0, 0x008C, 5, 0x0000, 0, 0),
-	MX6_PAD_EIM_EB2__I2C2_SCL		= IOMUX_PAD(0x03A0, 0x008C, 22, 0x08A0, 0, 0),
-	MX6_PAD_EIM_EB2__SRC_BT_CFG_30		= IOMUX_PAD(0x03A0, 0x008C, 7, 0x0000, 0, 0),
-	MX6_PAD_EIM_D16__WEIM_WEIM_D_16	= IOMUX_PAD(0x03A4, 0x0090, 0, 0x0000, 0, 0),
-	MX6_PAD_EIM_D16__ECSPI1_SCLK		= IOMUX_PAD(0x03A4, 0x0090, 1, 0x07F4, 0, 0),
-	MX6_PAD_EIM_D16__IPU1_DI0_PIN5		= IOMUX_PAD(0x03A4, 0x0090, 2, 0x0000, 0, 0),
-	MX6_PAD_EIM_D16__IPU2_CSI1_D_18	= IOMUX_PAD(0x03A4, 0x0090, 3, 0x08D0, 0, 0),
-	MX6_PAD_EIM_D16__HDMI_TX_DDC_SDA	= IOMUX_PAD(0x03A4, 0x0090, 4, 0x0894, 0, 0),
-	MX6_PAD_EIM_D16__GPIO_3_16		= IOMUX_PAD(0x03A4, 0x0090, 5, 0x0000, 0, 0),
-	MX6_PAD_EIM_D16__I2C2_SDA		= IOMUX_PAD(0x03A4, 0x0090, 22, 0x08A4, 0, 0),
-	MX6_PAD_EIM_D17__WEIM_WEIM_D_17	= IOMUX_PAD(0x03A8, 0x0094, 0, 0x0000, 0, 0),
-	MX6_PAD_EIM_D17__ECSPI1_MISO		= IOMUX_PAD(0x03A8, 0x0094, 1, 0x07F8, 0, 0),
-	MX6_PAD_EIM_D17__IPU1_DI0_PIN6		= IOMUX_PAD(0x03A8, 0x0094, 2, 0x0000, 0, 0),
-	MX6_PAD_EIM_D17__IPU2_CSI1_PIXCLK	= IOMUX_PAD(0x03A8, 0x0094, 3, 0x08E0, 0, 0),
-	MX6_PAD_EIM_D17__DCIC1_DCIC_OUT	= IOMUX_PAD(0x03A8, 0x0094, 4, 0x0000, 0, 0),
-	MX6_PAD_EIM_D17__GPIO_3_17		= IOMUX_PAD(0x03A8, 0x0094, 5, 0x0000, 0, 0),
-	MX6_PAD_EIM_D17__I2C3_SCL		= IOMUX_PAD(0x03A8, 0x0094, 22, 0x08A8, 0, 0),
-	MX6_PAD_EIM_D17__PL301_PER1_HBURST_1	= IOMUX_PAD(0x03A8, 0x0094, 7, 0x0000, 0, 0),
-	MX6_PAD_EIM_D18__WEIM_WEIM_D_18	= IOMUX_PAD(0x03AC, 0x0098, 0, 0x0000, 0, 0),
-	MX6_PAD_EIM_D18__ECSPI1_MOSI		= IOMUX_PAD(0x03AC, 0x0098, 1, 0x07FC, 0, 0),
-	MX6_PAD_EIM_D18__IPU1_DI0_PIN7		= IOMUX_PAD(0x03AC, 0x0098, 2, 0x0000, 0, 0),
-	MX6_PAD_EIM_D18__IPU2_CSI1_D_17	= IOMUX_PAD(0x03AC, 0x0098, 3, 0x08CC, 0, 0),
-	MX6_PAD_EIM_D18__IPU1_DI1_D0_CS	= IOMUX_PAD(0x03AC, 0x0098, 4, 0x0000, 0, 0),
-	MX6_PAD_EIM_D18__GPIO_3_18		= IOMUX_PAD(0x03AC, 0x0098, 5, 0x0000, 0, 0),
-	MX6_PAD_EIM_D18__I2C3_SDA		= IOMUX_PAD(0x03AC, 0x0098, 22, 0x08AC, 0, 0),
-	MX6_PAD_EIM_D18__PL301_PER1_HBURST_2	= IOMUX_PAD(0x03AC, 0x0098, 7, 0x0000, 0, 0),
-	MX6_PAD_EIM_D19__WEIM_WEIM_D_19	= IOMUX_PAD(0x03B0, 0x009C, 0, 0x0000, 0, 0),
-	MX6_PAD_EIM_D19__ECSPI1_SS1		= IOMUX_PAD(0x03B0, 0x009C, 1, 0x0804, 0, 0),
-	MX6_PAD_EIM_D19__IPU1_DI0_PIN8		= IOMUX_PAD(0x03B0, 0x009C, 2, 0x0000, 0, 0),
-	MX6_PAD_EIM_D19__IPU2_CSI1_D_16	= IOMUX_PAD(0x03B0, 0x009C, 3, 0x08C8, 0, 0),
-	MX6_PAD_EIM_D19__UART1_CTS		= IOMUX_PAD(0x03B0, 0x009C, 4, 0x091C, 0, 0),
-	MX6_PAD_EIM_D19__GPIO_3_19		= IOMUX_PAD(0x03B0, 0x009C, 5, 0x0000, 0, 0),
-	MX6_PAD_EIM_D19__EPIT1_EPITO		= IOMUX_PAD(0x03B0, 0x009C, 6, 0x0000, 0, 0),
-	MX6_PAD_EIM_D19__PL301MX6QPER1_HRESP   = IOMUX_PAD(0x03B0, 0x009C, 7, 0x0000, 0, 0),
-	MX6_PAD_EIM_D20__WEIM_WEIM_D_20	= IOMUX_PAD(0x03B4, 0x00A0, 0, 0x0000, 0, 0),
-	MX6_PAD_EIM_D20__ECSPI4_SS0		= IOMUX_PAD(0x03B4, 0x00A0, 1, 0x0824, 0, 0),
-	MX6_PAD_EIM_D20__IPU1_DI0_PIN16	= IOMUX_PAD(0x03B4, 0x00A0, 2, 0x0000, 0, 0),
-	MX6_PAD_EIM_D20__IPU2_CSI1_D_15	= IOMUX_PAD(0x03B4, 0x00A0, 3, 0x08C4, 0, 0),
-	MX6_PAD_EIM_D20__UART1_CTS		= IOMUX_PAD(0x03B4, 0x00A0, 4, 0x0000, 0, 0),
-	MX6_PAD_EIM_D20__UART1_RTS		= IOMUX_PAD(0x03B4, 0x00A0, 4, 0x091C, 1, 0),
-	MX6_PAD_EIM_D20__GPIO_3_20		= IOMUX_PAD(0x03B4, 0x00A0, 5, 0x0000, 0, 0),
-	MX6_PAD_EIM_D20__EPIT2_EPITO		= IOMUX_PAD(0x03B4, 0x00A0, 6, 0x0000, 0, 0),
-	MX6_PAD_EIM_D21__WEIM_WEIM_D_21	= IOMUX_PAD(0x03B8, 0x00A4, 0, 0x0000, 0, 0),
-	MX6_PAD_EIM_D21__ECSPI4_SCLK		= IOMUX_PAD(0x03B8, 0x00A4, 1, 0x0000, 0, 0),
-	MX6_PAD_EIM_D21__IPU1_DI0_PIN17	= IOMUX_PAD(0x03B8, 0x00A4, 2, 0x0000, 0, 0),
-	MX6_PAD_EIM_D21__IPU2_CSI1_D_11	= IOMUX_PAD(0x03B8, 0x00A4, 3, 0x08B4, 0, 0),
-	MX6_PAD_EIM_D21__USBOH3_USBOTG_OC	= IOMUX_PAD(0x03B8, 0x00A4, 4, 0x0944, 0, 0),
-	MX6_PAD_EIM_D21__GPIO_3_21		= IOMUX_PAD(0x03B8, 0x00A4, 5, 0x0000, 0, 0),
-	MX6_PAD_EIM_D21__I2C1_SCL		= IOMUX_PAD(0x03B8, 0x00A4, 22, 0x0898, 0, 0),
-	MX6_PAD_EIM_D21__SPDIF_IN1		= IOMUX_PAD(0x03B8, 0x00A4, 7, 0x0914, 0, 0),
-	MX6_PAD_EIM_D22__WEIM_WEIM_D_22	= IOMUX_PAD(0x03BC, 0x00A8, 0, 0x0000, 0, 0),
-	MX6_PAD_EIM_D22__ECSPI4_MISO		= IOMUX_PAD(0x03BC, 0x00A8, 1, 0x0000, 0, 0),
-	MX6_PAD_EIM_D22__IPU1_DI0_PIN1		= IOMUX_PAD(0x03BC, 0x00A8, 2, 0x0000, 0, 0),
-	MX6_PAD_EIM_D22__IPU2_CSI1_D_10	= IOMUX_PAD(0x03BC, 0x00A8, 3, 0x08B0, 0, 0),
-	MX6_PAD_EIM_D22__USBOH3_USBOTG_PWR	= IOMUX_PAD(0x03BC, 0x00A8, 4, 0x0000, 0, 0),
-	MX6_PAD_EIM_D22__GPIO_3_22		= IOMUX_PAD(0x03BC, 0x00A8, 5, 0x0000, 0, 0),
-	MX6_PAD_EIM_D22__SPDIF_OUT1		= IOMUX_PAD(0x03BC, 0x00A8, 6, 0x0000, 0, 0),
-	MX6_PAD_EIM_D22__PL301MX6QPER1_HWRITE	= IOMUX_PAD(0x03BC, 0x00A8, 7, 0x0000, 0, 0),
-	MX6_PAD_EIM_D23__WEIM_WEIM_D_23	= IOMUX_PAD(0x03C0, 0x00AC, 0, 0x0000, 0, 0),
-	MX6_PAD_EIM_D23__IPU1_DI0_D0_CS	= IOMUX_PAD(0x03C0, 0x00AC, 1, 0x0000, 0, 0),
-	MX6_PAD_EIM_D23__UART3_CTS		= IOMUX_PAD(0x03C0, 0x00AC, 2, 0x092C, 0, 0),
-	MX6_PAD_EIM_D23__UART1_DCD		= IOMUX_PAD(0x03C0, 0x00AC, 3, 0x0000, 0, 0),
-	MX6_PAD_EIM_D23__IPU2_CSI1_DATA_EN	= IOMUX_PAD(0x03C0, 0x00AC, 4, 0x08D8, 0, 0),
-	MX6_PAD_EIM_D23__GPIO_3_23		= IOMUX_PAD(0x03C0, 0x00AC, 5, 0x0000, 0, 0),
-	MX6_PAD_EIM_D23__IPU1_DI1_PIN2		= IOMUX_PAD(0x03C0, 0x00AC, 6, 0x0000, 0, 0),
-	MX6_PAD_EIM_D23__IPU1_DI1_PIN14	= IOMUX_PAD(0x03C0, 0x00AC, 7, 0x0000, 0, 0),
-	MX6_PAD_EIM_EB3__WEIM_WEIM_EB_3	= IOMUX_PAD(0x03C4, 0x00B0, 0, 0x0000, 0, 0),
-	MX6_PAD_EIM_EB3__ECSPI4_RDY		= IOMUX_PAD(0x03C4, 0x00B0, 1, 0x0000, 0, 0),
-	MX6_PAD_EIM_EB3__UART3_CTS		= IOMUX_PAD(0x03C4, 0x00B0, 2, 0x0000, 0, 0),
-	MX6_PAD_EIM_EB3__UART3_RTS		= IOMUX_PAD(0x03C4, 0x00B0, 2, 0x092C, 1, 0),
-	MX6_PAD_EIM_EB3__UART1_RI		= IOMUX_PAD(0x03C4, 0x00B0, 3, 0x0000, 0, 0),
-	MX6_PAD_EIM_EB3__IPU2_CSI1_HSYNC	= IOMUX_PAD(0x03C4, 0x00B0, 4, 0x08DC, 0, 0),
-	MX6_PAD_EIM_EB3__GPIO_2_31		= IOMUX_PAD(0x03C4, 0x00B0, 5, 0x0000, 0, 0),
-	MX6_PAD_EIM_EB3__IPU1_DI1_PIN3		= IOMUX_PAD(0x03C4, 0x00B0, 6, 0x0000, 0, 0),
-	MX6_PAD_EIM_EB3__SRC_BT_CFG_31		= IOMUX_PAD(0x03C4, 0x00B0, 7, 0x0000, 0, 0),
-	MX6_PAD_EIM_D24__WEIM_WEIM_D_24	= IOMUX_PAD(0x03C8, 0x00B4, 0, 0x0000, 0, 0),
-	MX6_PAD_EIM_D24__ECSPI4_SS2		= IOMUX_PAD(0x03C8, 0x00B4, 1, 0x0000, 0, 0),
-	MX6_PAD_EIM_D24__UART3_TXD		= IOMUX_PAD(0x03C8, 0x00B4, 2, 0x0000, 0, 0),
-	MX6_PAD_EIM_D24__UART3_TXD_RXD		= IOMUX_PAD(0x03C8, 0x00B4, 2, 0x0930, 0, 0),
-	MX6_PAD_EIM_D24__ECSPI1_SS2		= IOMUX_PAD(0x03C8, 0x00B4, 3, 0x0808, 0, 0),
-	MX6_PAD_EIM_D24__ECSPI2_SS2		= IOMUX_PAD(0x03C8, 0x00B4, 4, 0x0000, 0, 0),
-	MX6_PAD_EIM_D24__GPIO_3_24		= IOMUX_PAD(0x03C8, 0x00B4, 5, 0x0000, 0, 0),
-	MX6_PAD_EIM_D24__AUDMUX_AUD5_RXFS	= IOMUX_PAD(0x03C8, 0x00B4, 6, 0x07D8, 0, 0),
-	MX6_PAD_EIM_D24__UART1_DTR		= IOMUX_PAD(0x03C8, 0x00B4, 7, 0x0000, 0, 0),
-	MX6_PAD_EIM_D25__WEIM_WEIM_D_25	= IOMUX_PAD(0x03CC, 0x00B8, 0, 0x0000, 0, 0),
-	MX6_PAD_EIM_D25__ECSPI4_SS3		= IOMUX_PAD(0x03CC, 0x00B8, 1, 0x0000, 0, 0),
-	MX6_PAD_EIM_D25__UART3_RXD		= IOMUX_PAD(0x03CC, 0x00B8, 2, 0x0930, 1, 0),
-	MX6_PAD_EIM_D25__ECSPI1_SS3		= IOMUX_PAD(0x03CC, 0x00B8, 3, 0x080C, 0, 0),
-	MX6_PAD_EIM_D25__ECSPI2_SS3		= IOMUX_PAD(0x03CC, 0x00B8, 4, 0x0000, 0, 0),
-	MX6_PAD_EIM_D25__GPIO_3_25		= IOMUX_PAD(0x03CC, 0x00B8, 5, 0x0000, 0, 0),
-	MX6_PAD_EIM_D25__AUDMUX_AUD5_RXC	= IOMUX_PAD(0x03CC, 0x00B8, 6, 0x07D4, 0, 0),
-	MX6_PAD_EIM_D25__UART1_DSR		= IOMUX_PAD(0x03CC, 0x00B8, 7, 0x0000, 0, 0),
-	MX6_PAD_EIM_D26__WEIM_WEIM_D_26	= IOMUX_PAD(0x03D0, 0x00BC, 0, 0x0000, 0, 0),
-	MX6_PAD_EIM_D26__IPU1_DI1_PIN11	= IOMUX_PAD(0x03D0, 0x00BC, 1, 0x0000, 0, 0),
-	MX6_PAD_EIM_D26__IPU1_CSI0_D_1		= IOMUX_PAD(0x03D0, 0x00BC, 2, 0x0000, 0, 0),
-	MX6_PAD_EIM_D26__IPU2_CSI1_D_14	= IOMUX_PAD(0x03D0, 0x00BC, 3, 0x08C0, 0, 0),
-	MX6_PAD_EIM_D26__UART2_TXD		= IOMUX_PAD(0x03D0, 0x00BC, 4, 0x0000, 0, 0),
-	MX6_PAD_EIM_D26__UART2_TXD_RXD		= IOMUX_PAD(0x03D0, 0x00BC, 4, 0x0928, 0, 0),
-	MX6_PAD_EIM_D26__GPIO_3_26		= IOMUX_PAD(0x03D0, 0x00BC, 5, 0x0000, 0, 0),
-	MX6_PAD_EIM_D26__IPU1_SISG_2		= IOMUX_PAD(0x03D0, 0x00BC, 6, 0x0000, 0, 0),
-	MX6_PAD_EIM_D26__IPU1_DISP1_DAT_22	= IOMUX_PAD(0x03D0, 0x00BC, 7, 0x0000, 0, 0),
-	MX6_PAD_EIM_D27__WEIM_WEIM_D_27	= IOMUX_PAD(0x03D4, 0x00C0, 0, 0x0000, 0, 0),
-	MX6_PAD_EIM_D27__IPU1_DI1_PIN13	= IOMUX_PAD(0x03D4, 0x00C0, 1, 0x0000, 0, 0),
-	MX6_PAD_EIM_D27__IPU1_CSI0_D_0		= IOMUX_PAD(0x03D4, 0x00C0, 2, 0x0000, 0, 0),
-	MX6_PAD_EIM_D27__IPU2_CSI1_D_13	= IOMUX_PAD(0x03D4, 0x00C0, 3, 0x08BC, 0, 0),
-	MX6_PAD_EIM_D27__UART2_RXD		= IOMUX_PAD(0x03D4, 0x00C0, 4, 0x0928, 1, 0),
-	MX6_PAD_EIM_D27__GPIO_3_27		= IOMUX_PAD(0x03D4, 0x00C0, 5, 0x0000, 0, 0),
-	MX6_PAD_EIM_D27__IPU1_SISG_3		= IOMUX_PAD(0x03D4, 0x00C0, 6, 0x0000, 0, 0),
-	MX6_PAD_EIM_D27__IPU1_DISP1_DAT_23	= IOMUX_PAD(0x03D4, 0x00C0, 7, 0x0000, 0, 0),
-	MX6_PAD_EIM_D28__WEIM_WEIM_D_28	= IOMUX_PAD(0x03D8, 0x00C4, 0, 0x0000, 0, 0),
-	MX6_PAD_EIM_D28__I2C1_SDA		= IOMUX_PAD(0x03D8, 0x00C4, 17, 0x089C, 0, 0),
-	MX6_PAD_EIM_D28__ECSPI4_MOSI		= IOMUX_PAD(0x03D8, 0x00C4, 2, 0x0000, 0, 0),
-	MX6_PAD_EIM_D28__IPU2_CSI1_D_12	= IOMUX_PAD(0x03D8, 0x00C4, 3, 0x08B8, 0, 0),
-	MX6_PAD_EIM_D28__UART2_CTS		= IOMUX_PAD(0x03D8, 0x00C4, 4, 0x0924, 0, 0),
-	MX6_PAD_EIM_D28__GPIO_3_28		= IOMUX_PAD(0x03D8, 0x00C4, 5, 0x0000, 0, 0),
-	MX6_PAD_EIM_D28__IPU1_EXT_TRIG		= IOMUX_PAD(0x03D8, 0x00C4, 6, 0x0000, 0, 0),
-	MX6_PAD_EIM_D28__IPU1_DI0_PIN13	= IOMUX_PAD(0x03D8, 0x00C4, 7, 0x0000, 0, 0),
-	MX6_PAD_EIM_D29__WEIM_WEIM_D_29	= IOMUX_PAD(0x03DC, 0x00C8, 0, 0x0000, 0, 0),
-	MX6_PAD_EIM_D29__IPU1_DI1_PIN15	= IOMUX_PAD(0x03DC, 0x00C8, 1, 0x0000, 0, 0),
-	MX6_PAD_EIM_D29__ECSPI4_SS0		= IOMUX_PAD(0x03DC, 0x00C8, 2, 0x0824, 1, 0),
-	MX6_PAD_EIM_D29__UART2_CTS		= IOMUX_PAD(0x03DC, 0x00C8, 4, 0x0000, 0, 0),
-	MX6_PAD_EIM_D29__UART2_RTS		= IOMUX_PAD(0x03DC, 0x00C8, 4, 0x0924, 1, 0),
-	MX6_PAD_EIM_D29__GPIO_3_29		= IOMUX_PAD(0x03DC, 0x00C8, 5, 0x0000, 0, 0),
-	MX6_PAD_EIM_D29__IPU2_CSI1_VSYNC	= IOMUX_PAD(0x03DC, 0x00C8, 6, 0x08E4, 0, 0),
-	MX6_PAD_EIM_D29__IPU1_DI0_PIN14	= IOMUX_PAD(0x03DC, 0x00C8, 7, 0x0000, 0, 0),
-	MX6_PAD_EIM_D30__WEIM_WEIM_D_30	= IOMUX_PAD(0x03E0, 0x00CC, 0, 0x0000, 0, 0),
-	MX6_PAD_EIM_D30__IPU1_DISP1_DAT_21	= IOMUX_PAD(0x03E0, 0x00CC, 1, 0x0000, 0, 0),
-	MX6_PAD_EIM_D30__IPU1_DI0_PIN11	= IOMUX_PAD(0x03E0, 0x00CC, 2, 0x0000, 0, 0),
-	MX6_PAD_EIM_D30__IPU1_CSI0_D_3		= IOMUX_PAD(0x03E0, 0x00CC, 3, 0x0000, 0, 0),
-	MX6_PAD_EIM_D30__UART3_CTS		= IOMUX_PAD(0x03E0, 0x00CC, 4, 0x092C, 2, 0),
-	MX6_PAD_EIM_D30__GPIO_3_30		= IOMUX_PAD(0x03E0, 0x00CC, 5, 0x0000, 0, 0),
-	MX6_PAD_EIM_D30__USBOH3_USBH1_OC	= IOMUX_PAD(0x03E0, 0x00CC, 6, 0x0948, 0, 0),
-	MX6_PAD_EIM_D30__PL301MX6QPER1_HPROT_0 = IOMUX_PAD(0x03E0, 0x00CC, 7, 0x0000, 0, 0),
-	MX6_PAD_EIM_D31__WEIM_WEIM_D_31	= IOMUX_PAD(0x03E4, 0x00D0, 0, 0x0000, 0, 0),
-	MX6_PAD_EIM_D31__IPU1_DISP1_DAT_20	= IOMUX_PAD(0x03E4, 0x00D0, 1, 0x0000, 0, 0),
-	MX6_PAD_EIM_D31__IPU1_DI0_PIN12	= IOMUX_PAD(0x03E4, 0x00D0, 2, 0x0000, 0, 0),
-	MX6_PAD_EIM_D31__IPU1_CSI0_D_2		= IOMUX_PAD(0x03E4, 0x00D0, 3, 0x0000, 0, 0),
-	MX6_PAD_EIM_D31__UART3_CTS		= IOMUX_PAD(0x03E4, 0x00D0, 4, 0x0000, 0, 0),
-	MX6_PAD_EIM_D31__UART3_RTS		= IOMUX_PAD(0x03E4, 0x00D0, 4, 0x092C, 3, 0),
-	MX6_PAD_EIM_D31__GPIO_3_31		= IOMUX_PAD(0x03E4, 0x00D0, 5, 0x0000, 0, 0),
-	MX6_PAD_EIM_D31__USBOH3_USBH1_PWR	= IOMUX_PAD(0x03E4, 0x00D0, 6, 0x0000, 0, 0),
-	MX6_PAD_EIM_D31__PL301MX6QPER1_HPROT_1 = IOMUX_PAD(0x03E4, 0x00D0, 7, 0x0000, 0, 0),
-	MX6_PAD_EIM_A24__WEIM_WEIM_A_24	= IOMUX_PAD(0x03E8, 0x00D4, 0, 0x0000, 0, 0),
-	MX6_PAD_EIM_A24__IPU1_DISP1_DAT_19	= IOMUX_PAD(0x03E8, 0x00D4, 1, 0x0000, 0, 0),
-	MX6_PAD_EIM_A24__IPU2_CSI1_D_19	= IOMUX_PAD(0x03E8, 0x00D4, 2, 0x08D4, 1, 0),
-	MX6_PAD_EIM_A24__IPU2_SISG_2		= IOMUX_PAD(0x03E8, 0x00D4, 3, 0x0000, 0, 0),
-	MX6_PAD_EIM_A24__IPU1_SISG_2		= IOMUX_PAD(0x03E8, 0x00D4, 4, 0x0000, 0, 0),
-	MX6_PAD_EIM_A24__GPIO_5_4		= IOMUX_PAD(0x03E8, 0x00D4, 5, 0x0000, 0, 0),
-	MX6_PAD_EIM_A24__PL301MX6QPER1_HPROT_2 = IOMUX_PAD(0x03E8, 0x00D4, 6, 0x0000, 0, 0),
-	MX6_PAD_EIM_A24__SRC_BT_CFG_24		= IOMUX_PAD(0x03E8, 0x00D4, 7, 0x0000, 0, 0),
-	MX6_PAD_EIM_A23__WEIM_WEIM_A_23	= IOMUX_PAD(0x03EC, 0x00D8, 0, 0x0000, 0, 0),
-	MX6_PAD_EIM_A23__IPU1_DISP1_DAT_18	= IOMUX_PAD(0x03EC, 0x00D8, 1, 0x0000, 0, 0),
-	MX6_PAD_EIM_A23__IPU2_CSI1_D_18	= IOMUX_PAD(0x03EC, 0x00D8, 2, 0x08D0, 1, 0),
-	MX6_PAD_EIM_A23__IPU2_SISG_3		= IOMUX_PAD(0x03EC, 0x00D8, 3, 0x0000, 0, 0),
-	MX6_PAD_EIM_A23__IPU1_SISG_3		= IOMUX_PAD(0x03EC, 0x00D8, 4, 0x0000, 0, 0),
-	MX6_PAD_EIM_A23__GPIO_6_6		= IOMUX_PAD(0x03EC, 0x00D8, 5, 0x0000, 0, 0),
-	MX6_PAD_EIM_A23__PL301MX6QPER1_HPROT_3	= IOMUX_PAD(0x03EC, 0x00D8, 6, 0x0000, 0, 0),
-	MX6_PAD_EIM_A23__SRC_BT_CFG_23		= IOMUX_PAD(0x03EC, 0x00D8, 7, 0x0000, 0, 0),
-	MX6_PAD_EIM_A22__WEIM_WEIM_A_22	= IOMUX_PAD(0x03F0, 0x00DC, 0, 0x0000, 0, 0),
-	MX6_PAD_EIM_A22__IPU1_DISP1_DAT_17	= IOMUX_PAD(0x03F0, 0x00DC, 1, 0x0000, 0, 0),
-	MX6_PAD_EIM_A22__IPU2_CSI1_D_17	= IOMUX_PAD(0x03F0, 0x00DC, 2, 0x08CC, 1, 0),
-	MX6_PAD_EIM_A22__GPIO_2_16		= IOMUX_PAD(0x03F0, 0x00DC, 5, 0x0000, 0, 0),
-	MX6_PAD_EIM_A22__TPSMP_HDATA_0		= IOMUX_PAD(0x03F0, 0x00DC, 6, 0x0000, 0, 0),
-	MX6_PAD_EIM_A22__SRC_BT_CFG_22		= IOMUX_PAD(0x03F0, 0x00DC, 7, 0x0000, 0, 0),
-	MX6_PAD_EIM_A21__WEIM_WEIM_A_21	= IOMUX_PAD(0x03F4, 0x00E0, 0, 0x0000, 0, 0),
-	MX6_PAD_EIM_A21__IPU1_DISP1_DAT_16	= IOMUX_PAD(0x03F4, 0x00E0, 1, 0x0000, 0, 0),
-	MX6_PAD_EIM_A21__IPU2_CSI1_D_16	= IOMUX_PAD(0x03F4, 0x00E0, 2, 0x08C8, 1, 0),
-	MX6_PAD_EIM_A21__RESERVED_RESERVED	= IOMUX_PAD(0x03F4, 0x00E0, 3, 0x0000, 0, 0),
-	MX6_PAD_EIM_A21__MIPI_CORE_DPHY_OUT_18 = IOMUX_PAD(0x03F4, 0x00E0, 4, 0x0000, 0, 0),
-	MX6_PAD_EIM_A21__GPIO_2_17		= IOMUX_PAD(0x03F4, 0x00E0, 5, 0x0000, 0, 0),
-	MX6_PAD_EIM_A21__TPSMP_HDATA_1		= IOMUX_PAD(0x03F4, 0x00E0, 6, 0x0000, 0, 0),
-	MX6_PAD_EIM_A21__SRC_BT_CFG_21		= IOMUX_PAD(0x03F4, 0x00E0, 7, 0x0000, 0, 0),
-	MX6_PAD_EIM_A20__WEIM_WEIM_A_20	= IOMUX_PAD(0x03F8, 0x00E4, 0, 0x0000, 0, 0),
-	MX6_PAD_EIM_A20__IPU1_DISP1_DAT_15	= IOMUX_PAD(0x03F8, 0x00E4, 1, 0x0000, 0, 0),
-	MX6_PAD_EIM_A20__IPU2_CSI1_D_15	= IOMUX_PAD(0x03F8, 0x00E4, 2, 0x08C4, 1, 0),
-	MX6_PAD_EIM_A20__RESERVED_RESERVED	= IOMUX_PAD(0x03F8, 0x00E4, 3, 0x0000, 0, 0),
-	MX6_PAD_EIM_A20__MIPI_CORE_DPHY_OUT_19 = IOMUX_PAD(0x03F8, 0x00E4, 4, 0x0000, 0, 0),
-	MX6_PAD_EIM_A20__GPIO_2_18		= IOMUX_PAD(0x03F8, 0x00E4, 5, 0x0000, 0, 0),
-	MX6_PAD_EIM_A20__TPSMP_HDATA_2		= IOMUX_PAD(0x03F8, 0x00E4, 6, 0x0000, 0, 0),
-	MX6_PAD_EIM_A20__SRC_BT_CFG_20		= IOMUX_PAD(0x03F8, 0x00E4, 7, 0x0000, 0, 0),
-	MX6_PAD_EIM_A19__WEIM_WEIM_A_19	= IOMUX_PAD(0x03FC, 0x00E8, 0, 0x0000, 0, 0),
-	MX6_PAD_EIM_A19__IPU1_DISP1_DAT_14	= IOMUX_PAD(0x03FC, 0x00E8, 1, 0x0000, 0, 0),
-	MX6_PAD_EIM_A19__IPU2_CSI1_D_14	= IOMUX_PAD(0x03FC, 0x00E8, 2, 0x08C0, 1, 0),
-	MX6_PAD_EIM_A19__RESERVED_RESERVED	= IOMUX_PAD(0x03FC, 0x00E8, 3, 0x0000, 0, 0),
-	MX6_PAD_EIM_A19__MIPI_CORE_DPHY_OUT_20 = IOMUX_PAD(0x03FC, 0x00E8, 4, 0x0000, 0, 0),
-	MX6_PAD_EIM_A19__GPIO_2_19		= IOMUX_PAD(0x03FC, 0x00E8, 5, 0x0000, 0, 0),
-	MX6_PAD_EIM_A19__TPSMP_HDATA_3		= IOMUX_PAD(0x03FC, 0x00E8, 6, 0x0000, 0, 0),
-	MX6_PAD_EIM_A19__SRC_BT_CFG_19		= IOMUX_PAD(0x03FC, 0x00E8, 7, 0x0000, 0, 0),
-	MX6_PAD_EIM_A18__WEIM_WEIM_A_18	= IOMUX_PAD(0x0400, 0x00EC, 0, 0x0000, 0, 0),
-	MX6_PAD_EIM_A18__IPU1_DISP1_DAT_13	= IOMUX_PAD(0x0400, 0x00EC, 1, 0x0000, 0, 0),
-	MX6_PAD_EIM_A18__IPU2_CSI1_D_13	= IOMUX_PAD(0x0400, 0x00EC, 2, 0x08BC, 1, 0),
-	MX6_PAD_EIM_A18__RESERVED_RESERVED	= IOMUX_PAD(0x0400, 0x00EC, 3, 0x0000, 0, 0),
-	MX6_PAD_EIM_A18__MIPI_CORE_DPHY_OUT_21 = IOMUX_PAD(0x0400, 0x00EC, 4, 0x0000, 0, 0),
-	MX6_PAD_EIM_A18__GPIO_2_20		= IOMUX_PAD(0x0400, 0x00EC, 5, 0x0000, 0, 0),
-	MX6_PAD_EIM_A18__TPSMP_HDATA_4		= IOMUX_PAD(0x0400, 0x00EC, 6, 0x0000, 0, 0),
-	MX6_PAD_EIM_A18__SRC_BT_CFG_18		= IOMUX_PAD(0x0400, 0x00EC, 7, 0x0000, 0, 0),
-	MX6_PAD_EIM_A17__WEIM_WEIM_A_17	= IOMUX_PAD(0x0404, 0x00F0, 0, 0x0000, 0, 0),
-	MX6_PAD_EIM_A17__IPU1_DISP1_DAT_12	= IOMUX_PAD(0x0404, 0x00F0, 1, 0x0000, 0, 0),
-	MX6_PAD_EIM_A17__IPU2_CSI1_D_12	= IOMUX_PAD(0x0404, 0x00F0, 2, 0x08B8, 1, 0),
-	MX6_PAD_EIM_A17__RESERVED_RESERVED	= IOMUX_PAD(0x0404, 0x00F0, 3, 0x0000, 0, 0),
-	MX6_PAD_EIM_A17__MIPI_CORE_DPHY_OUT_22 = IOMUX_PAD(0x0404, 0x00F0, 4, 0x0000, 0, 0),
-	MX6_PAD_EIM_A17__GPIO_2_21		= IOMUX_PAD(0x0404, 0x00F0, 5, 0x0000, 0, 0),
-	MX6_PAD_EIM_A17__TPSMP_HDATA_5		= IOMUX_PAD(0x0404, 0x00F0, 6, 0x0000, 0, 0),
-	MX6_PAD_EIM_A17__SRC_BT_CFG_17		= IOMUX_PAD(0x0404, 0x00F0, 7, 0x0000, 0, 0),
-	MX6_PAD_EIM_A16__WEIM_WEIM_A_16	= IOMUX_PAD(0x0408, 0x00F4, 0, 0x0000, 0, 0),
-	MX6_PAD_EIM_A16__IPU1_DI1_DISP_CLK	= IOMUX_PAD(0x0408, 0x00F4, 1, 0x0000, 0, 0),
-	MX6_PAD_EIM_A16__IPU2_CSI1_PIXCLK	= IOMUX_PAD(0x0408, 0x00F4, 2, 0x08E0, 1, 0),
-	MX6_PAD_EIM_A16__MIPI_CORE_DPHY_OUT_23 = IOMUX_PAD(0x0408, 0x00F4, 4, 0x0000, 0, 0),
-	MX6_PAD_EIM_A16__GPIO_2_22		= IOMUX_PAD(0x0408, 0x00F4, 5, 0x0000, 0, 0),
-	MX6_PAD_EIM_A16__TPSMP_HDATA_6		= IOMUX_PAD(0x0408, 0x00F4, 6, 0x0000, 0, 0),
-	MX6_PAD_EIM_A16__SRC_BT_CFG_16		= IOMUX_PAD(0x0408, 0x00F4, 7, 0x0000, 0, 0),
-	MX6_PAD_EIM_CS0__WEIM_WEIM_CS_0	= IOMUX_PAD(0x040C, 0x00F8, 0, 0x0000, 0, 0),
-	MX6_PAD_EIM_CS0__IPU1_DI1_PIN5		= IOMUX_PAD(0x040C, 0x00F8, 1, 0x0000, 0, 0),
-	MX6_PAD_EIM_CS0__ECSPI2_SCLK		= IOMUX_PAD(0x040C, 0x00F8, 2, 0x0810, 0, 0),
-	MX6_PAD_EIM_CS0__MIPI_CORE_DPHY_OUT_24 = IOMUX_PAD(0x040C, 0x00F8, 4, 0x0000, 0, 0),
-	MX6_PAD_EIM_CS0__GPIO_2_23		= IOMUX_PAD(0x040C, 0x00F8, 5, 0x0000, 0, 0),
-	MX6_PAD_EIM_CS0__TPSMP_HDATA_7		= IOMUX_PAD(0x040C, 0x00F8, 6, 0x0000, 0, 0),
-	MX6_PAD_EIM_CS1__WEIM_WEIM_CS_1	= IOMUX_PAD(0x0410, 0x00FC, 0, 0x0000, 0, 0),
-	MX6_PAD_EIM_CS1__IPU1_DI1_PIN6		= IOMUX_PAD(0x0410, 0x00FC, 1, 0x0000, 0, 0),
-	MX6_PAD_EIM_CS1__ECSPI2_MOSI		= IOMUX_PAD(0x0410, 0x00FC, 2, 0x0818, 0, 0),
-	MX6_PAD_EIM_CS1__MIPI_CORE_DPHY_OUT_25 = IOMUX_PAD(0x0410, 0x00FC, 4, 0x0000, 0, 0),
-	MX6_PAD_EIM_CS1__GPIO_2_24		= IOMUX_PAD(0x0410, 0x00FC, 5, 0x0000, 0, 0),
-	MX6_PAD_EIM_CS1__TPSMP_HDATA_8		= IOMUX_PAD(0x0410, 0x00FC, 6, 0x0000, 0, 0),
-	MX6_PAD_EIM_OE__WEIM_WEIM_OE		= IOMUX_PAD(0x0414, 0x0100, 0, 0x0000, 0, 0),
-	MX6_PAD_EIM_OE__IPU1_DI1_PIN7		= IOMUX_PAD(0x0414, 0x0100, 1, 0x0000, 0, 0),
-	MX6_PAD_EIM_OE__ECSPI2_MISO		= IOMUX_PAD(0x0414, 0x0100, 2, 0x0814, 0, 0),
-	MX6_PAD_EIM_OE__MIPI_CORE_DPHY_OUT_26  = IOMUX_PAD(0x0414, 0x0100, 4, 0x0000, 0, 0),
-	MX6_PAD_EIM_OE__GPIO_2_25		= IOMUX_PAD(0x0414, 0x0100, 5, 0x0000, 0, 0),
-	MX6_PAD_EIM_OE__TPSMP_HDATA_9		= IOMUX_PAD(0x0414, 0x0100, 6, 0x0000, 0, 0),
-	MX6_PAD_EIM_RW__WEIM_WEIM_RW		= IOMUX_PAD(0x0418, 0x0104, 0, 0x0000, 0, 0),
-	MX6_PAD_EIM_RW__IPU1_DI1_PIN8		= IOMUX_PAD(0x0418, 0x0104, 1, 0x0000, 0, 0),
-	MX6_PAD_EIM_RW__ECSPI2_SS0		= IOMUX_PAD(0x0418, 0x0104, 2, 0x081C, 0, 0),
-	MX6_PAD_EIM_RW__MIPI_CORE_DPHY_OUT_27  = IOMUX_PAD(0x0418, 0x0104, 4, 0x0000, 0, 0),
-	MX6_PAD_EIM_RW__GPIO_2_26		= IOMUX_PAD(0x0418, 0x0104, 5, 0x0000, 0, 0),
-	MX6_PAD_EIM_RW__TPSMP_HDATA_10		= IOMUX_PAD(0x0418, 0x0104, 6, 0x0000, 0, 0),
-	MX6_PAD_EIM_RW__SRC_BT_CFG_29		= IOMUX_PAD(0x0418, 0x0104, 7, 0x0000, 0, 0),
-	MX6_PAD_EIM_LBA__WEIM_WEIM_LBA		= IOMUX_PAD(0x041C, 0x0108, 0, 0x0000, 0, 0),
-	MX6_PAD_EIM_LBA__IPU1_DI1_PIN17	= IOMUX_PAD(0x041C, 0x0108, 1, 0x0000, 0, 0),
-	MX6_PAD_EIM_LBA__ECSPI2_SS1		= IOMUX_PAD(0x041C, 0x0108, 2, 0x0820, 0, 0),
-	MX6_PAD_EIM_LBA__GPIO_2_27		= IOMUX_PAD(0x041C, 0x0108, 5, 0x0000, 0, 0),
-	MX6_PAD_EIM_LBA__TPSMP_HDATA_11	= IOMUX_PAD(0x041C, 0x0108, 6, 0x0000, 0, 0),
-	MX6_PAD_EIM_LBA__SRC_BT_CFG_26		= IOMUX_PAD(0x041C, 0x0108, 7, 0x0000, 0, 0),
-	MX6_PAD_EIM_EB0__WEIM_WEIM_EB_0	= IOMUX_PAD(0x0420, 0x010C, 0, 0x0000, 0, 0),
-	MX6_PAD_EIM_EB0__IPU1_DISP1_DAT_11	= IOMUX_PAD(0x0420, 0x010C, 1, 0x0000, 0, 0),
-	MX6_PAD_EIM_EB0__IPU2_CSI1_D_11	= IOMUX_PAD(0x0420, 0x010C, 2, 0x08B4, 1, 0),
-	MX6_PAD_EIM_EB0__MIPI_CORE_DPHY_OUT_0  = IOMUX_PAD(0x0420, 0x010C, 3, 0x0000, 0, 0),
-	MX6_PAD_EIM_EB0__CCM_PMIC_RDY		= IOMUX_PAD(0x0420, 0x010C, 4, 0x07F0, 0, 0),
-	MX6_PAD_EIM_EB0__GPIO_2_28		= IOMUX_PAD(0x0420, 0x010C, 5, 0x0000, 0, 0),
-	MX6_PAD_EIM_EB0__TPSMP_HDATA_12	= IOMUX_PAD(0x0420, 0x010C, 6, 0x0000, 0, 0),
-	MX6_PAD_EIM_EB0__SRC_BT_CFG_27		= IOMUX_PAD(0x0420, 0x010C, 7, 0x0000, 0, 0),
-	MX6_PAD_EIM_EB1__WEIM_WEIM_EB_1	= IOMUX_PAD(0x0424, 0x0110, 0, 0x0000, 0, 0),
-	MX6_PAD_EIM_EB1__IPU1_DISP1_DAT_10	= IOMUX_PAD(0x0424, 0x0110, 1, 0x0000, 0, 0),
-	MX6_PAD_EIM_EB1__IPU2_CSI1_D_10	= IOMUX_PAD(0x0424, 0x0110, 2, 0x08B0, 1, 0),
-	MX6_PAD_EIM_EB1__MIPI_CORE_DPHY__OUT_1 = IOMUX_PAD(0x0424, 0x0110, 3, 0x0000, 0, 0),
-	MX6_PAD_EIM_EB1__GPIO_2_29		= IOMUX_PAD(0x0424, 0x0110, 5, 0x0000, 0, 0),
-	MX6_PAD_EIM_EB1__TPSMP_HDATA_13	= IOMUX_PAD(0x0424, 0x0110, 6, 0x0000, 0, 0),
-	MX6_PAD_EIM_EB1__SRC_BT_CFG_28		= IOMUX_PAD(0x0424, 0x0110, 7, 0x0000, 0, 0),
-	MX6_PAD_EIM_DA0__WEIM_WEIM_DA_A_0	= IOMUX_PAD(0x0428, 0x0114, 0, 0x0000, 0, 0),
-	MX6_PAD_EIM_DA0__IPU1_DISP1_DAT_9	= IOMUX_PAD(0x0428, 0x0114, 1, 0x0000, 0, 0),
-	MX6_PAD_EIM_DA0__IPU2_CSI1_D_9		= IOMUX_PAD(0x0428, 0x0114, 2, 0x0000, 0, 0),
-	MX6_PAD_EIM_DA0__MIPI_CORE_DPHY__OUT_2	= IOMUX_PAD(0x0428, 0x0114, 3, 0x0000, 0, 0),
-	MX6_PAD_EIM_DA0__GPIO_3_0		= IOMUX_PAD(0x0428, 0x0114, 5, 0x0000, 0, 0),
-	MX6_PAD_EIM_DA0__TPSMP_HDATA_14	= IOMUX_PAD(0x0428, 0x0114, 6, 0x0000, 0, 0),
-	MX6_PAD_EIM_DA0__SRC_BT_CFG_0		= IOMUX_PAD(0x0428, 0x0114, 7, 0x0000, 0, 0),
-	MX6_PAD_EIM_DA1__WEIM_WEIM_DA_A_1	= IOMUX_PAD(0x042C, 0x0118, 0, 0x0000, 0, 0),
-	MX6_PAD_EIM_DA1__IPU1_DISP1_DAT_8	= IOMUX_PAD(0x042C, 0x0118, 1, 0x0000, 0, 0),
-	MX6_PAD_EIM_DA1__IPU2_CSI1_D_8		= IOMUX_PAD(0x042C, 0x0118, 2, 0x0000, 0, 0),
-	MX6_PAD_EIM_DA1__MIPI_CORE_DPHY_OUT_3	= IOMUX_PAD(0x042C, 0x0118, 3, 0x0000, 0, 0),
-	MX6_PAD_EIM_DA1__USBPHY1_TX_LS_MODE	= IOMUX_PAD(0x042C, 0x0118, 4, 0x0000, 0, 0),
-	MX6_PAD_EIM_DA1__GPIO_3_1		= IOMUX_PAD(0x042C, 0x0118, 5, 0x0000, 0, 0),
-	MX6_PAD_EIM_DA1__TPSMP_HDATA_15	= IOMUX_PAD(0x042C, 0x0118, 6, 0x0000, 0, 0),
-	MX6_PAD_EIM_DA1__SRC_BT_CFG_1		= IOMUX_PAD(0x042C, 0x0118, 7, 0x0000, 0, 0),
-	MX6_PAD_EIM_DA2__WEIM_WEIM_DA_A_2	= IOMUX_PAD(0x0430, 0x011C, 0, 0x0000, 0, 0),
-	MX6_PAD_EIM_DA2__IPU1_DISP1_DAT_7	= IOMUX_PAD(0x0430, 0x011C, 1, 0x0000, 0, 0),
-	MX6_PAD_EIM_DA2__IPU2_CSI1_D_7		= IOMUX_PAD(0x0430, 0x011C, 2, 0x0000, 0, 0),
-	MX6_PAD_EIM_DA2__MIPI_CORE_DPHY_OUT_4  = IOMUX_PAD(0x0430, 0x011C, 3, 0x0000, 0, 0),
-	MX6_PAD_EIM_DA2__USBPHY1_TX_HS_MODE	= IOMUX_PAD(0x0430, 0x011C, 4, 0x0000, 0, 0),
-	MX6_PAD_EIM_DA2__GPIO_3_2		= IOMUX_PAD(0x0430, 0x011C, 5, 0x0000, 0, 0),
-	MX6_PAD_EIM_DA2__TPSMP_HDATA_16	= IOMUX_PAD(0x0430, 0x011C, 6, 0x0000, 0, 0),
-	MX6_PAD_EIM_DA2__SRC_BT_CFG_2		= IOMUX_PAD(0x0430, 0x011C, 7, 0x0000, 0, 0),
-	MX6_PAD_EIM_DA3__WEIM_WEIM_DA_A_3	= IOMUX_PAD(0x0434, 0x0120, 0, 0x0000, 0, 0),
-	MX6_PAD_EIM_DA3__IPU1_DISP1_DAT_6	= IOMUX_PAD(0x0434, 0x0120, 1, 0x0000, 0, 0),
-	MX6_PAD_EIM_DA3__IPU2_CSI1_D_6		= IOMUX_PAD(0x0434, 0x0120, 2, 0x0000, 0, 0),
-	MX6_PAD_EIM_DA3__MIPI_CORE_DPHY_OUT_5  = IOMUX_PAD(0x0434, 0x0120, 3, 0x0000, 0, 0),
-	MX6_PAD_EIM_DA3__USBPHY1_TX_HIZ        = IOMUX_PAD(0x0434, 0x0120, 4, 0x0000, 0, 0),
-	MX6_PAD_EIM_DA3__GPIO_3_3		= IOMUX_PAD(0x0434, 0x0120, 5, 0x0000, 0, 0),
-	MX6_PAD_EIM_DA3__TPSMP_HDATA_17	= IOMUX_PAD(0x0434, 0x0120, 6, 0x0000, 0, 0),
-	MX6_PAD_EIM_DA3__SRC_BT_CFG_3		= IOMUX_PAD(0x0434, 0x0120, 7, 0x0000, 0, 0),
-	MX6_PAD_EIM_DA4__WEIM_WEIM_DA_A_4	= IOMUX_PAD(0x0438, 0x0124, 0, 0x0000, 0, 0),
-	MX6_PAD_EIM_DA4__IPU1_DISP1_DAT_5	= IOMUX_PAD(0x0438, 0x0124, 1, 0x0000, 0, 0),
-	MX6_PAD_EIM_DA4__IPU2_CSI1_D_5		= IOMUX_PAD(0x0438, 0x0124, 2, 0x0000, 0, 0),
-	MX6_PAD_EIM_DA4__MIPI_CORE_DPHY_OUT_6  = IOMUX_PAD(0x0438, 0x0124, 3, 0x0000, 0, 0),
-	MX6_PAD_EIM_DA4__ANATOP_USBPHY1_TX_EN  = IOMUX_PAD(0x0438, 0x0124, 4, 0x0000, 0, 0),
-	MX6_PAD_EIM_DA4__GPIO_3_4		= IOMUX_PAD(0x0438, 0x0124, 5, 0x0000, 0, 0),
-	MX6_PAD_EIM_DA4__TPSMP_HDATA_18	= IOMUX_PAD(0x0438, 0x0124, 6, 0x0000, 0, 0),
-	MX6_PAD_EIM_DA4__SRC_BT_CFG_4		= IOMUX_PAD(0x0438, 0x0124, 7, 0x0000, 0, 0),
-	MX6_PAD_EIM_DA5__WEIM_WEIM_DA_A_5	= IOMUX_PAD(0x043C, 0x0128, 0, 0x0000, 0, 0),
-	MX6_PAD_EIM_DA5__IPU1_DISP1_DAT_4	= IOMUX_PAD(0x043C, 0x0128, 1, 0x0000, 0, 0),
-	MX6_PAD_EIM_DA5__IPU2_CSI1_D_4		= IOMUX_PAD(0x043C, 0x0128, 2, 0x0000, 0, 0),
-	MX6_PAD_EIM_DA5__MIPI_CORE_DPHY_OUT_7  = IOMUX_PAD(0x043C, 0x0128, 3, 0x0000, 0, 0),
-	MX6_PAD_EIM_DA5__ANATOP_USBPHY1_TX_DP  = IOMUX_PAD(0x043C, 0x0128, 4, 0x0000, 0, 0),
-	MX6_PAD_EIM_DA5__GPIO_3_5		= IOMUX_PAD(0x043C, 0x0128, 5, 0x0000, 0, 0),
-	MX6_PAD_EIM_DA5__TPSMP_HDATA_19	= IOMUX_PAD(0x043C, 0x0128, 6, 0x0000, 0, 0),
-	MX6_PAD_EIM_DA5__SRC_BT_CFG_5		= IOMUX_PAD(0x043C, 0x0128, 7, 0x0000, 0, 0),
-	MX6_PAD_EIM_DA6__WEIM_WEIM_DA_A_6	= IOMUX_PAD(0x0440, 0x012C, 0, 0x0000, 0, 0),
-	MX6_PAD_EIM_DA6__IPU1_DISP1_DAT_3	= IOMUX_PAD(0x0440, 0x012C, 1, 0x0000, 0, 0),
-	MX6_PAD_EIM_DA6__IPU2_CSI1_D_3		= IOMUX_PAD(0x0440, 0x012C, 2, 0x0000, 0, 0),
-	MX6_PAD_EIM_DA6__MIPI_CORE_DPHY_OUT_8  = IOMUX_PAD(0x0440, 0x012C, 3, 0x0000, 0, 0),
-	MX6_PAD_EIM_DA6__ANATOP_USBPHY1_TX_DN  = IOMUX_PAD(0x0440, 0x012C, 4, 0x0000, 0, 0),
-	MX6_PAD_EIM_DA6__GPIO_3_6		= IOMUX_PAD(0x0440, 0x012C, 5, 0x0000, 0, 0),
-	MX6_PAD_EIM_DA6__TPSMP_HDATA_20	= IOMUX_PAD(0x0440, 0x012C, 6, 0x0000, 0, 0),
-	MX6_PAD_EIM_DA6__SRC_BT_CFG_6		= IOMUX_PAD(0x0440, 0x012C, 7, 0x0000, 0, 0),
-	MX6_PAD_EIM_DA7__WEIM_WEIM_DA_A_7	= IOMUX_PAD(0x0444, 0x0130, 0, 0x0000, 0, 0),
-	MX6_PAD_EIM_DA7__IPU1_DISP1_DAT_2	= IOMUX_PAD(0x0444, 0x0130, 1, 0x0000, 0, 0),
-	MX6_PAD_EIM_DA7__IPU2_CSI1_D_2		= IOMUX_PAD(0x0444, 0x0130, 2, 0x0000, 0, 0),
-	MX6_PAD_EIM_DA7__MIPI_CORE_DPHY_OUT_9	= IOMUX_PAD(0x0444, 0x0130, 3, 0x0000, 0, 0),
-	MX6_PAD_EIM_DA7__GPIO_3_7		= IOMUX_PAD(0x0444, 0x0130, 5, 0x0000, 0, 0),
-	MX6_PAD_EIM_DA7__TPSMP_HDATA_21	= IOMUX_PAD(0x0444, 0x0130, 6, 0x0000, 0, 0),
-	MX6_PAD_EIM_DA7__SRC_BT_CFG_7		= IOMUX_PAD(0x0444, 0x0130, 7, 0x0000, 0, 0),
-	MX6_PAD_EIM_DA8__WEIM_WEIM_DA_A_8	= IOMUX_PAD(0x0448, 0x0134, 0, 0x0000, 0, 0),
-	MX6_PAD_EIM_DA8__IPU1_DISP1_DAT_1	= IOMUX_PAD(0x0448, 0x0134, 1, 0x0000, 0, 0),
-	MX6_PAD_EIM_DA8__IPU2_CSI1_D_1		= IOMUX_PAD(0x0448, 0x0134, 2, 0x0000, 0, 0),
-	MX6_PAD_EIM_DA8__MIPI_CORE_DPHY_OUT_10 = IOMUX_PAD(0x0448, 0x0134, 3, 0x0000, 0, 0),
-	MX6_PAD_EIM_DA8__GPIO_3_8		= IOMUX_PAD(0x0448, 0x0134, 5, 0x0000, 0, 0),
-	MX6_PAD_EIM_DA8__TPSMP_HDATA_22	= IOMUX_PAD(0x0448, 0x0134, 6, 0x0000, 0, 0),
-	MX6_PAD_EIM_DA8__SRC_BT_CFG_8		= IOMUX_PAD(0x0448, 0x0134, 7, 0x0000, 0, 0),
-	MX6_PAD_EIM_DA9__WEIM_WEIM_DA_A_9	= IOMUX_PAD(0x044C, 0x0138, 0, 0x0000, 0, 0),
-	MX6_PAD_EIM_DA9__IPU1_DISP1_DAT_0	= IOMUX_PAD(0x044C, 0x0138, 1, 0x0000, 0, 0),
-	MX6_PAD_EIM_DA9__IPU2_CSI1_D_0		= IOMUX_PAD(0x044C, 0x0138, 2, 0x0000, 0, 0),
-	MX6_PAD_EIM_DA9__MIPI_CORE_DPHY_OUT_11 = IOMUX_PAD(0x044C, 0x0138, 3, 0x0000, 0, 0),
-	MX6_PAD_EIM_DA9__GPIO_3_9		= IOMUX_PAD(0x044C, 0x0138, 5, 0x0000, 0, 0),
-	MX6_PAD_EIM_DA9__TPSMP_HDATA_23	= IOMUX_PAD(0x044C, 0x0138, 6, 0x0000, 0, 0),
-	MX6_PAD_EIM_DA9__SRC_BT_CFG_9		= IOMUX_PAD(0x044C, 0x0138, 7, 0x0000, 0, 0),
-	MX6_PAD_EIM_DA10__WEIM_WEIM_DA_A_10	= IOMUX_PAD(0x0450, 0x013C, 0, 0x0000, 0, 0),
-	MX6_PAD_EIM_DA10__IPU1_DI1_PIN15	= IOMUX_PAD(0x0450, 0x013C, 1, 0x0000, 0, 0),
-	MX6_PAD_EIM_DA10__IPU2_CSI1_DATA_EN    = IOMUX_PAD(0x0450, 0x013C, 2, 0x08D8, 1, 0),
-	MX6_PAD_EIM_DA10__MIPI_CORE_DPHY_OUT12	= IOMUX_PAD(0x0450, 0x013C, 3, 0x0000, 0, 0),
-	MX6_PAD_EIM_DA10__GPIO_3_10		= IOMUX_PAD(0x0450, 0x013C, 5, 0x0000, 0, 0),
-	MX6_PAD_EIM_DA10__TPSMP_HDATA_24	= IOMUX_PAD(0x0450, 0x013C, 6, 0x0000, 0, 0),
-	MX6_PAD_EIM_DA10__SRC_BT_CFG_10	= IOMUX_PAD(0x0450, 0x013C, 7, 0x0000, 0, 0),
-	MX6_PAD_EIM_DA11__WEIM_WEIM_DA_A_11	= IOMUX_PAD(0x0454, 0x0140, 0, 0x0000, 0, 0),
-	MX6_PAD_EIM_DA11__IPU1_DI1_PIN2	= IOMUX_PAD(0x0454, 0x0140, 1, 0x0000, 0, 0),
-	MX6_PAD_EIM_DA11__IPU2_CSI1_HSYNC	= IOMUX_PAD(0x0454, 0x0140, 2, 0x08DC, 1, 0),
-	MX6_PAD_EIM_DA11__MIPI_CORE_DPHY_OUT13	= IOMUX_PAD(0x0454, 0x0140, 3, 0x0000, 0, 0),
-	MX6_PAD_EIM_DA11__SDMA_DBG_EVT_CHN_6	= IOMUX_PAD(0x0454, 0x0140, 4, 0x0000, 0, 0),
-	MX6_PAD_EIM_DA11__GPIO_3_11		= IOMUX_PAD(0x0454, 0x0140, 5, 0x0000, 0, 0),
-	MX6_PAD_EIM_DA11__TPSMP_HDATA_25	= IOMUX_PAD(0x0454, 0x0140, 6, 0x0000, 0, 0),
-	MX6_PAD_EIM_DA11__SRC_BT_CFG_11	= IOMUX_PAD(0x0454, 0x0140, 7, 0x0000, 0, 0),
-	MX6_PAD_EIM_DA12__WEIM_WEIM_DA_A_12	= IOMUX_PAD(0x0458, 0x0144, 0, 0x0000, 0, 0),
-	MX6_PAD_EIM_DA12__IPU1_DI1_PIN3	= IOMUX_PAD(0x0458, 0x0144, 1, 0x0000, 0, 0),
-	MX6_PAD_EIM_DA12__IPU2_CSI1_VSYNC	= IOMUX_PAD(0x0458, 0x0144, 2, 0x08E4, 1, 0),
-	MX6_PAD_EIM_DA12__MIPI_CORE_DPHY_OUT14	= IOMUX_PAD(0x0458, 0x0144, 3, 0x0000, 0, 0),
-	MX6_PAD_EIM_DA12__SDMA_DEBUG_EVT_CHN_3 = IOMUX_PAD(0x0458, 0x0144, 4, 0x0000, 0, 0),
-	MX6_PAD_EIM_DA12__GPIO_3_12		= IOMUX_PAD(0x0458, 0x0144, 5, 0x0000, 0, 0),
-	MX6_PAD_EIM_DA12__TPSMP_HDATA_26	= IOMUX_PAD(0x0458, 0x0144, 6, 0x0000, 0, 0),
-	MX6_PAD_EIM_DA12__SRC_BT_CFG_12	= IOMUX_PAD(0x0458, 0x0144, 7, 0x0000, 0, 0),
-	MX6_PAD_EIM_DA13__WEIM_WEIM_DA_A_13	= IOMUX_PAD(0x045C, 0x0148, 0, 0x0000, 0, 0),
-	MX6_PAD_EIM_DA13__IPU1_DI1_D0_CS	= IOMUX_PAD(0x045C, 0x0148, 1, 0x0000, 0, 0),
-	MX6_PAD_EIM_DA13__CCM_DI1_EXT_CLK	= IOMUX_PAD(0x045C, 0x0148, 2, 0x07EC, 1, 0),
-	MX6_PAD_EIM_DA13__MIPI_CORE_DPHY_OUT15	= IOMUX_PAD(0x045C, 0x0148, 3, 0x0000, 0, 0),
-	MX6_PAD_EIM_DA13__SDMA_DEBUG_EVT_CHN_4 = IOMUX_PAD(0x045C, 0x0148, 4, 0x0000, 0, 0),
-	MX6_PAD_EIM_DA13__GPIO_3_13		= IOMUX_PAD(0x045C, 0x0148, 5, 0x0000, 0, 0),
-	MX6_PAD_EIM_DA13__TPSMP_HDATA_27	= IOMUX_PAD(0x045C, 0x0148, 6, 0x0000, 0, 0),
-	MX6_PAD_EIM_DA13__SRC_BT_CFG_13	= IOMUX_PAD(0x045C, 0x0148, 7, 0x0000, 0, 0),
-	MX6_PAD_EIM_DA14__WEIM_WEIM_DA_A_14	= IOMUX_PAD(0x0460, 0x014C, 0, 0x0000, 0, 0),
-	MX6_PAD_EIM_DA14__IPU1_DI1_D1_CS	= IOMUX_PAD(0x0460, 0x014C, 1, 0x0000, 0, 0),
-	MX6_PAD_EIM_DA14__CCM_DI0_EXT_CLK	= IOMUX_PAD(0x0460, 0x014C, 2, 0x0000, 0, 0),
-	MX6_PAD_EIM_DA14__MIPI_CORE_DPHY_OUT16	= IOMUX_PAD(0x0460, 0x014C, 3, 0x0000, 0, 0),
-	MX6_PAD_EIM_DA14__SDMA_DEBUG_EVT_CHN_5 = IOMUX_PAD(0x0460, 0x014C, 4, 0x0000, 0, 0),
-	MX6_PAD_EIM_DA14__GPIO_3_14		= IOMUX_PAD(0x0460, 0x014C, 5, 0x0000, 0, 0),
-	MX6_PAD_EIM_DA14__TPSMP_HDATA_28	= IOMUX_PAD(0x0460, 0x014C, 6, 0x0000, 0, 0),
-	MX6_PAD_EIM_DA14__SRC_BT_CFG_14	= IOMUX_PAD(0x0460, 0x014C, 7, 0x0000, 0, 0),
-	MX6_PAD_EIM_DA15__WEIM_WEIM_DA_A_15	= IOMUX_PAD(0x0464, 0x0150, 0, 0x0000, 0, 0),
-	MX6_PAD_EIM_DA15__IPU1_DI1_PIN1	= IOMUX_PAD(0x0464, 0x0150, 1, 0x0000, 0, 0),
-	MX6_PAD_EIM_DA15__IPU1_DI1_PIN4	= IOMUX_PAD(0x0464, 0x0150, 2, 0x0000, 0, 0),
-	MX6_PAD_EIM_DA15__MIPI_CORE_DPHY_OUT17	= IOMUX_PAD(0x0464, 0x0150, 3, 0x0000, 0, 0),
-	MX6_PAD_EIM_DA15__GPIO_3_15		= IOMUX_PAD(0x0464, 0x0150, 5, 0x0000, 0, 0),
-	MX6_PAD_EIM_DA15__TPSMP_HDATA_29	= IOMUX_PAD(0x0464, 0x0150, 6, 0x0000, 0, 0),
-	MX6_PAD_EIM_DA15__SRC_BT_CFG_15	= IOMUX_PAD(0x0464, 0x0150, 7, 0x0000, 0, 0),
-	MX6_PAD_EIM_WAIT__WEIM_WEIM_WAIT	= IOMUX_PAD(0x0468, 0x0154, 0, 0x0000, 0, 0),
-	MX6_PAD_EIM_WAIT__WEIM_WEIM_DTACK_B	= IOMUX_PAD(0x0468, 0x0154, 1, 0x0000, 0, 0),
-	MX6_PAD_EIM_WAIT__GPIO_5_0		= IOMUX_PAD(0x0468, 0x0154, 5, 0x0000, 0, 0),
-	MX6_PAD_EIM_WAIT__TPSMP_HDATA_30	= IOMUX_PAD(0x0468, 0x0154, 6, 0x0000, 0, 0),
-	MX6_PAD_EIM_WAIT__SRC_BT_CFG_25	= IOMUX_PAD(0x0468, 0x0154, 7, 0x0000, 0, 0),
-	MX6_PAD_EIM_BCLK__WEIM_WEIM_BCLK	= IOMUX_PAD(0x046C, 0x0158, 0, 0x0000, 0, 0),
-	MX6_PAD_EIM_BCLK__IPU1_DI1_PIN16	= IOMUX_PAD(0x046C, 0x0158, 1, 0x0000, 0, 0),
-	MX6_PAD_EIM_BCLK__GPIO_6_31		= IOMUX_PAD(0x046C, 0x0158, 5, 0x0000, 0, 0),
-	MX6_PAD_EIM_BCLK__TPSMP_HDATA_31	= IOMUX_PAD(0x046C, 0x0158, 6, 0x0000, 0, 0),
-	MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK = IOMUX_PAD(0x0470, 0x015C, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
-	MX6_PAD_DI0_DISP_CLK__IPU2_DI0_DISP_CLK = IOMUX_PAD(0x0470, 0x015C, 1, 0x0000, 0, 0),
-	MX6_PAD_DI0_DISP_CLK__MIPI_CR_DPY_OT28 = IOMUX_PAD(0x0470, 0x015C, 3, 0x0000, 0, 0),
-	MX6_PAD_DI0_DISP_CLK__SDMA_DBG_CR_STA0 = IOMUX_PAD(0x0470, 0x015C, 4, 0x0000, 0, 0),
-	MX6_PAD_DI0_DISP_CLK__GPIO_4_16	= IOMUX_PAD(0x0470, 0x015C, 5, 0x0000, 0, 0),
-	MX6_PAD_DI0_DISP_CLK__MMDC_DEBUG_0	= IOMUX_PAD(0x0470, 0x015C, 6, 0x0000, 0, 0),
-	MX6_PAD_DI0_PIN15__IPU1_DI0_PIN15	= IOMUX_PAD(0x0474, 0x0160, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
-	MX6_PAD_DI0_PIN15__IPU2_DI0_PIN15	= IOMUX_PAD(0x0474, 0x0160, 1, 0x0000, 0, 0),
-	MX6_PAD_DI0_PIN15__AUDMUX_AUD6_TXC	= IOMUX_PAD(0x0474, 0x0160, 2, 0x0000, 0, 0),
-	MX6_PAD_DI0_PIN15__MIPI_CR_DPHY_OUT_29 = IOMUX_PAD(0x0474, 0x0160, 3, 0x0000, 0, 0),
-	MX6_PAD_DI0_PIN15__SDMA_DBG_CORE_STA_1 = IOMUX_PAD(0x0474, 0x0160, 4, 0x0000, 0, 0),
-	MX6_PAD_DI0_PIN15__GPIO_4_17		= IOMUX_PAD(0x0474, 0x0160, 5, 0x0000, 0, 0),
-	MX6_PAD_DI0_PIN15__MMDC_MMDC_DEBUG_1	= IOMUX_PAD(0x0474, 0x0160, 6, 0x0000, 0, 0),
-	MX6_PAD_DI0_PIN2__IPU1_DI0_PIN2	= IOMUX_PAD(0x0478, 0x0164, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
-	MX6_PAD_DI0_PIN2__IPU2_DI0_PIN2	= IOMUX_PAD(0x0478, 0x0164, 1, 0x0000, 0, 0),
-	MX6_PAD_DI0_PIN2__AUDMUX_AUD6_TXD	= IOMUX_PAD(0x0478, 0x0164, 2, 0x0000, 0, 0),
-	MX6_PAD_DI0_PIN2__MIPI_CR_DPHY_OUT_30	= IOMUX_PAD(0x0478, 0x0164, 3, 0x0000, 0, 0),
-	MX6_PAD_DI0_PIN2__SDMA_DBG_CORE_STA_2	= IOMUX_PAD(0x0478, 0x0164, 4, 0x0000, 0, 0),
-	MX6_PAD_DI0_PIN2__GPIO_4_18		= IOMUX_PAD(0x0478, 0x0164, 5, 0x0000, 0, 0),
-	MX6_PAD_DI0_PIN2__MMDC_DEBUG_2		= IOMUX_PAD(0x0478, 0x0164, 6, 0x0000, 0, 0),
-	MX6_PAD_DI0_PIN2__PL301_PER1_HADDR_9	= IOMUX_PAD(0x0478, 0x0164, 7, 0x0000, 0, 0),
-	MX6_PAD_DI0_PIN3__IPU1_DI0_PIN3	= IOMUX_PAD(0x047C, 0x0168, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
-	MX6_PAD_DI0_PIN3__IPU2_DI0_PIN3	= IOMUX_PAD(0x047C, 0x0168, 1, 0x0000, 0, 0),
-	MX6_PAD_DI0_PIN3__AUDMUX_AUD6_TXFS	= IOMUX_PAD(0x047C, 0x0168, 2, 0x0000, 0, 0),
-	MX6_PAD_DI0_PIN3__MIPI_CORE_DPHY_OUT31 = IOMUX_PAD(0x047C, 0x0168, 3, 0x0000, 0, 0),
-	MX6_PAD_DI0_PIN3__SDMA_DBG_CORE_STA_3	= IOMUX_PAD(0x047C, 0x0168, 4, 0x0000, 0, 0),
-	MX6_PAD_DI0_PIN3__GPIO_4_19		= IOMUX_PAD(0x047C, 0x0168, 5, 0x0000, 0, 0),
-	MX6_PAD_DI0_PIN3__MMDC_MMDC_DEBUG_3	= IOMUX_PAD(0x047C, 0x0168, 6, 0x0000, 0, 0),
-	MX6_PAD_DI0_PIN3__PL301_PER1_HADDR_10	= IOMUX_PAD(0x047C, 0x0168, 7, 0x0000, 0, 0),
-	MX6_PAD_DI0_PIN4__IPU1_DI0_PIN4	= IOMUX_PAD(0x0480, 0x016C, 0, 0x0000, 0, 0),
-	MX6_PAD_DI0_PIN4__IPU2_DI0_PIN4	= IOMUX_PAD(0x0480, 0x016C, 1, 0x0000, 0, 0),
-	MX6_PAD_DI0_PIN4__AUDMUX_AUD6_RXD	= IOMUX_PAD(0x0480, 0x016C, 2, 0x0000, 0, 0),
-	MX6_PAD_DI0_PIN4__USDHC1_WP		= IOMUX_PAD(0x0480, 0x016C, 3, 0x094C, 0, 0),
-	MX6_PAD_DI0_PIN4__SDMA_DEBUG_YIELD	= IOMUX_PAD(0x0480, 0x016C, 4, 0x0000, 0, 0),
-	MX6_PAD_DI0_PIN4__GPIO_4_20		= IOMUX_PAD(0x0480, 0x016C, 5, 0x0000, 0, PAD_CTL_DSE_120ohm),
-	MX6_PAD_DI0_PIN4__MMDC_MMDC_DEBUG_4	= IOMUX_PAD(0x0480, 0x016C, 6, 0x0000, 0, 0),
-	MX6_PAD_DI0_PIN4__PL301_PER1_HADDR_11  = IOMUX_PAD(0x0480, 0x016C, 7, 0x0000, 0, 0),
-	MX6_PAD_DISP0_DAT0__IPU1_DISP0_DAT_0	= IOMUX_PAD(0x0484, 0x0170, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
-	MX6_PAD_DISP0_DAT0__IPU2_DISP0_DAT_0	= IOMUX_PAD(0x0484, 0x0170, 1, 0x0000, 0, 0),
-	MX6_PAD_DISP0_DAT0__ECSPI3_SCLK	= IOMUX_PAD(0x0484, 0x0170, 2, 0x0000, 0, 0),
-	MX6_PAD_DISP0_DAT0__USDHC1_USDHC_DBG_0 = IOMUX_PAD(0x0484, 0x0170, 3, 0x0000, 0, 0),
-	MX6_PAD_DISP0_DAT0__SDMA_DBG_CORE_RUN	= IOMUX_PAD(0x0484, 0x0170, 4, 0x0000, 0, 0),
-	MX6_PAD_DISP0_DAT0__GPIO_4_21		= IOMUX_PAD(0x0484, 0x0170, 5, 0x0000, 0, 0),
-	MX6_PAD_DISP0_DAT0__MMDC_MMDC_DEBUG_5	= IOMUX_PAD(0x0484, 0x0170, 6, 0x0000, 0, 0),
-	MX6_PAD_DISP0_DAT1__IPU1_DISP0_DAT_1	= IOMUX_PAD(0x0488, 0x0174, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
-	MX6_PAD_DISP0_DAT1__IPU2_DISP0_DAT_1	= IOMUX_PAD(0x0488, 0x0174, 1, 0x0000, 0, 0),
-	MX6_PAD_DISP0_DAT1__ECSPI3_MOSI	= IOMUX_PAD(0x0488, 0x0174, 2, 0x0000, 0, 0),
-	MX6_PAD_DISP0_DAT1__USDHC1_USDHC_DBG_1 = IOMUX_PAD(0x0488, 0x0174, 3, 0x0000, 0, 0),
-	MX6_PAD_DISP0_DAT1__SDMA_DBG_EVT_CHNSL = IOMUX_PAD(0x0488, 0x0174, 4, 0x0000, 0, 0),
-	MX6_PAD_DISP0_DAT1__GPIO_4_22		= IOMUX_PAD(0x0488, 0x0174, 5, 0x0000, 0, 0),
-	MX6_PAD_DISP0_DAT1__MMDC_DEBUG_6	= IOMUX_PAD(0x0488, 0x0174, 6, 0x0000, 0, 0),
-	MX6_PAD_DISP0_DAT1__PL301_PER1_HADR_12 = IOMUX_PAD(0x0488, 0x0174, 7, 0x0000, 0, 0),
-	MX6_PAD_DISP0_DAT2__IPU1_DISP0_DAT_2	= IOMUX_PAD(0x048C, 0x0178, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
-	MX6_PAD_DISP0_DAT2__IPU2_DISP0_DAT_2	= IOMUX_PAD(0x048C, 0x0178, 1, 0x0000, 0, 0),
-	MX6_PAD_DISP0_DAT2__ECSPI3_MISO	= IOMUX_PAD(0x048C, 0x0178, 2, 0x0000, 0, 0),
-	MX6_PAD_DISP0_DAT2__USDHC1_USDHC_DBG_2 = IOMUX_PAD(0x048C, 0x0178, 3, 0x0000, 0, 0),
-	MX6_PAD_DISP0_DAT2__SDMA_DEBUG_MODE	= IOMUX_PAD(0x048C, 0x0178, 4, 0x0000, 0, 0),
-	MX6_PAD_DISP0_DAT2__GPIO_4_23		= IOMUX_PAD(0x048C, 0x0178, 5, 0x0000, 0, 0),
-	MX6_PAD_DISP0_DAT2__MMDC_DEBUG_7	= IOMUX_PAD(0x048C, 0x0178, 6, 0x0000, 0, 0),
-	MX6_PAD_DISP0_DAT2__PL301_PER1_HADR_13 = IOMUX_PAD(0x048C, 0x0178, 7, 0x0000, 0, 0),
-	MX6_PAD_DISP0_DAT3__IPU1_DISP0_DAT_3	= IOMUX_PAD(0x0490, 0x017C, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
-	MX6_PAD_DISP0_DAT3__IPU2_DISP0_DAT_3	= IOMUX_PAD(0x0490, 0x017C, 1, 0x0000, 0, 0),
-	MX6_PAD_DISP0_DAT3__ECSPI3_SS0		= IOMUX_PAD(0x0490, 0x017C, 2, 0x0000, 0, 0),
-	MX6_PAD_DISP0_DAT3__USDHC1_USDHC_DBG_3 = IOMUX_PAD(0x0490, 0x017C, 3, 0x0000, 0, 0),
-	MX6_PAD_DISP0_DAT3__SDMA_DBG_BUS_ERROR = IOMUX_PAD(0x0490, 0x017C, 4, 0x0000, 0, 0),
-	MX6_PAD_DISP0_DAT3__GPIO_4_24		= IOMUX_PAD(0x0490, 0x017C, 5, 0x0000, 0, 0),
-	MX6_PAD_DISP0_DAT3__MMDC_MMDC_DBG_8	= IOMUX_PAD(0x0490, 0x017C, 6, 0x0000, 0, 0),
-	MX6_PAD_DISP0_DAT3__PL301_PER1_HADR_14 = IOMUX_PAD(0x0490, 0x017C, 7, 0x0000, 0, 0),
-	MX6_PAD_DISP0_DAT4__IPU1_DISP0_DAT_4	= IOMUX_PAD(0x0494, 0x0180, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
-	MX6_PAD_DISP0_DAT4__IPU2_DISP0_DAT_4	= IOMUX_PAD(0x0494, 0x0180, 1, 0x0000, 0, 0),
-	MX6_PAD_DISP0_DAT4__ECSPI3_SS1		= IOMUX_PAD(0x0494, 0x0180, 2, 0x0000, 0, 0),
-	MX6_PAD_DISP0_DAT4__USDHC1_USDHC_DBG_4	= IOMUX_PAD(0x0494, 0x0180, 3, 0x0000, 0, 0),
-	MX6_PAD_DISP0_DAT4__SDMA_DEBUG_BUS_RWB = IOMUX_PAD(0x0494, 0x0180, 4, 0x0000, 0, 0),
-	MX6_PAD_DISP0_DAT4__GPIO_4_25		= IOMUX_PAD(0x0494, 0x0180, 5, 0x0000, 0, 0),
-	MX6_PAD_DISP0_DAT4__MMDC_MMDC_DEBUG_9	= IOMUX_PAD(0x0494, 0x0180, 6, 0x0000, 0, 0),
-	MX6_PAD_DISP0_DAT4__PL301_PER1_HADR_15	= IOMUX_PAD(0x0494, 0x0180, 7, 0x0000, 0, 0),
-	MX6_PAD_DISP0_DAT5__IPU1_DISP0_DAT_5	= IOMUX_PAD(0x0498, 0x0184, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
-	MX6_PAD_DISP0_DAT5__IPU2_DISP0_DAT_5	= IOMUX_PAD(0x0498, 0x0184, 1, 0x0000, 0, 0),
-	MX6_PAD_DISP0_DAT5__ECSPI3_SS2		= IOMUX_PAD(0x0498, 0x0184, 2, 0x0000, 0, 0),
-	MX6_PAD_DISP0_DAT5__AUDMUX_AUD6_RXFS	= IOMUX_PAD(0x0498, 0x0184, 3, 0x0000, 0, 0),
-	MX6_PAD_DISP0_DAT5__SDMA_DBG_MCH_DMBUS = IOMUX_PAD(0x0498, 0x0184, 4, 0x0000, 0, 0),
-	MX6_PAD_DISP0_DAT5__GPIO_4_26		= IOMUX_PAD(0x0498, 0x0184, 5, 0x0000, 0, 0),
-	MX6_PAD_DISP0_DAT5__MMDC_DEBUG_10	= IOMUX_PAD(0x0498, 0x0184, 6, 0x0000, 0, 0),
-	MX6_PAD_DISP0_DAT5__PL301_PER1_HADR_16 = IOMUX_PAD(0x0498, 0x0184, 7, 0x0000, 0, 0),
-	MX6_PAD_DISP0_DAT6__IPU1_DISP0_DAT_6	= IOMUX_PAD(0x049C, 0x0188, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
-	MX6_PAD_DISP0_DAT6__IPU2_DISP0_DAT_6	= IOMUX_PAD(0x049C, 0x0188, 1, 0x0000, 0, 0),
-	MX6_PAD_DISP0_DAT6__ECSPI3_SS3		= IOMUX_PAD(0x049C, 0x0188, 2, 0x0000, 0, 0),
-	MX6_PAD_DISP0_DAT6__AUDMUX_AUD6_RXC	= IOMUX_PAD(0x049C, 0x0188, 3, 0x0000, 0, 0),
-	MX6_PAD_DISP0_DAT6__SDMA_DBG_RTBUF_WRT = IOMUX_PAD(0x049C, 0x0188, 4, 0x0000, 0, 0),
-	MX6_PAD_DISP0_DAT6__GPIO_4_27		= IOMUX_PAD(0x049C, 0x0188, 5, 0x0000, 0, 0),
-	MX6_PAD_DISP0_DAT6__MMDC_DEBUG_11	= IOMUX_PAD(0x049C, 0x0188, 6, 0x0000, 0, 0),
-	MX6_PAD_DISP0_DAT6__PL301_PER1_HADR_17 = IOMUX_PAD(0x049C, 0x0188, 7, 0x0000, 0, 0),
-	MX6_PAD_DISP0_DAT7__IPU1_DISP0_DAT_7	= IOMUX_PAD(0x04A0, 0x018C, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
-	MX6_PAD_DISP0_DAT7__IPU2_DISP0_DAT_7	= IOMUX_PAD(0x04A0, 0x018C, 1, 0x0000, 0, 0),
-	MX6_PAD_DISP0_DAT7__ECSPI3_RDY		= IOMUX_PAD(0x04A0, 0x018C, 2, 0x0000, 0, 0),
-	MX6_PAD_DISP0_DAT7__USDHC1_USDHC_DBG_5 = IOMUX_PAD(0x04A0, 0x018C, 3, 0x0000, 0, 0),
-	MX6_PAD_DISP0_DAT7__SDMA_DBG_EVT_CHN_0 = IOMUX_PAD(0x04A0, 0x018C, 4, 0x0000, 0, 0),
-	MX6_PAD_DISP0_DAT7__GPIO_4_28		= IOMUX_PAD(0x04A0, 0x018C, 5, 0x0000, 0, 0),
-	MX6_PAD_DISP0_DAT7__MMDC_DEBUG_12	= IOMUX_PAD(0x04A0, 0x018C, 6, 0x0000, 0, 0),
-	MX6_PAD_DISP0_DAT7__PL301_PER1_HADR_18 = IOMUX_PAD(0x04A0, 0x018C, 7, 0x0000, 0, 0),
-	MX6_PAD_DISP0_DAT8__IPU1_DISP0_DAT_8	= IOMUX_PAD(0x04A4, 0x0190, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
-	MX6_PAD_DISP0_DAT8__IPU2_DISP0_DAT_8	= IOMUX_PAD(0x04A4, 0x0190, 1, 0x0000, 0, 0),
-	MX6_PAD_DISP0_DAT8__PWM1_PWMO		= IOMUX_PAD(0x04A4, 0x0190, 2, 0x0000, 0, 0),
-	MX6_PAD_DISP0_DAT8__WDOG1_WDOG_B	= IOMUX_PAD(0x04A4, 0x0190, 3, 0x0000, 0, 0),
-	MX6_PAD_DISP0_DAT8__SDMA_DBG_EVT_CHN_1	= IOMUX_PAD(0x04A4, 0x0190, 4, 0x0000, 0, 0),
-	MX6_PAD_DISP0_DAT8__GPIO_4_29		= IOMUX_PAD(0x04A4, 0x0190, 5, 0x0000, 0, 0),
-	MX6_PAD_DISP0_DAT8__MMDC_DEBUG_13	= IOMUX_PAD(0x04A4, 0x0190, 6, 0x0000, 0, 0),
-	MX6_PAD_DISP0_DAT8__PL301_PER1_HADR_19 = IOMUX_PAD(0x04A4, 0x0190, 7, 0x0000, 0, 0),
-	MX6_PAD_DISP0_DAT9__IPU1_DISP0_DAT_9	= IOMUX_PAD(0x04A8, 0x0194, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
-	MX6_PAD_DISP0_DAT9__IPU2_DISP0_DAT_9	= IOMUX_PAD(0x04A8, 0x0194, 1, 0x0000, 0, 0),
-	MX6_PAD_DISP0_DAT9__PWM2_PWMO		= IOMUX_PAD(0x04A8, 0x0194, 2, 0x0000, 0, 0),
-	MX6_PAD_DISP0_DAT9__WDOG2_WDOG_B	= IOMUX_PAD(0x04A8, 0x0194, 3, 0x0000, 0, 0),
-	MX6_PAD_DISP0_DAT9__SDMA_DBG_EVT_CHN_2 = IOMUX_PAD(0x04A8, 0x0194, 4, 0x0000, 0, 0),
-	MX6_PAD_DISP0_DAT9__GPIO_4_30		= IOMUX_PAD(0x04A8, 0x0194, 5, 0x0000, 0, 0),
-	MX6_PAD_DISP0_DAT9__MMDC_DEBUG_14	= IOMUX_PAD(0x04A8, 0x0194, 6, 0x0000, 0, 0),
-	MX6_PAD_DISP0_DAT9__PL301_PER1_HADR_20 = IOMUX_PAD(0x04A8, 0x0194, 7, 0x0000, 0, 0),
-	MX6_PAD_DISP0_DAT10__IPU1_DISP0_DAT_10	= IOMUX_PAD(0x04AC, 0x0198, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
-	MX6_PAD_DISP0_DAT10__IPU2_DISP0_DAT_10	= IOMUX_PAD(0x04AC, 0x0198, 1, 0x0000, 0, 0),
-	MX6_PAD_DISP0_DAT10__USDHC1_DBG_6	= IOMUX_PAD(0x04AC, 0x0198, 3, 0x0000, 0, 0),
-	MX6_PAD_DISP0_DAT10__SDMA_DBG_EVT_CHN3 = IOMUX_PAD(0x04AC, 0x0198, 4, 0x0000, 0, 0),
-	MX6_PAD_DISP0_DAT10__GPIO_4_31		= IOMUX_PAD(0x04AC, 0x0198, 5, 0x0000, 0, 0),
-	MX6_PAD_DISP0_DAT10__MMDC_DEBUG_15	= IOMUX_PAD(0x04AC, 0x0198, 6, 0x0000, 0, 0),
-	MX6_PAD_DISP0_DAT10__PL301_PER1_HADR21 = IOMUX_PAD(0x04AC, 0x0198, 7, 0x0000, 0, 0),
-	MX6_PAD_DISP0_DAT11__IPU1_DISP0_DAT_11	= IOMUX_PAD(0x04B0, 0x019C, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
-	MX6_PAD_DISP0_DAT11__IPU2_DISP0_DAT_11	= IOMUX_PAD(0x04B0, 0x019C, 1, 0x0000, 0, 0),
-	MX6_PAD_DISP0_DAT11__USDHC1_USDHC_DBG7 = IOMUX_PAD(0x04B0, 0x019C, 3, 0x0000, 0, 0),
-	MX6_PAD_DISP0_DAT11__SDMA_DBG_EVT_CHN4 = IOMUX_PAD(0x04B0, 0x019C, 4, 0x0000, 0, 0),
-	MX6_PAD_DISP0_DAT11__GPIO_5_5		= IOMUX_PAD(0x04B0, 0x019C, 5, 0x0000, 0, 0),
-	MX6_PAD_DISP0_DAT11__MMDC_DEBUG_16	= IOMUX_PAD(0x04B0, 0x019C, 6, 0x0000, 0, 0),
-	MX6_PAD_DISP0_DAT11__PL301_PER1_HADR22 = IOMUX_PAD(0x04B0, 0x019C, 7, 0x0000, 0, 0),
-	MX6_PAD_DISP0_DAT12__IPU1_DISP0_DAT_12	= IOMUX_PAD(0x04B4, 0x01A0, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
-	MX6_PAD_DISP0_DAT12__IPU2_DISP0_DAT_12	= IOMUX_PAD(0x04B4, 0x01A0, 1, 0x0000, 0, 0),
-	MX6_PAD_DISP0_DAT12__RESERVED_RESERVED	= IOMUX_PAD(0x04B4, 0x01A0, 3, 0x0000, 0, 0),
-	MX6_PAD_DISP0_DAT12__SDMA_DBG_EVT_CHN5 = IOMUX_PAD(0x04B4, 0x01A0, 4, 0x0000, 0, 0),
-	MX6_PAD_DISP0_DAT12__GPIO_5_6		= IOMUX_PAD(0x04B4, 0x01A0, 5, 0x0000, 0, 0),
-	MX6_PAD_DISP0_DAT12__MMDC_DEBUG_17	= IOMUX_PAD(0x04B4, 0x01A0, 6, 0x0000, 0, 0),
-	MX6_PAD_DISP0_DAT12__PL301_PER1_HADR23 = IOMUX_PAD(0x04B4, 0x01A0, 7, 0x0000, 0, 0),
-	MX6_PAD_DISP0_DAT13__IPU1_DISP0_DAT_13	= IOMUX_PAD(0x04B8, 0x01A4, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
-	MX6_PAD_DISP0_DAT13__IPU2_DISP0_DAT_13	= IOMUX_PAD(0x04B8, 0x01A4, 1, 0x0000, 0, 0),
-	MX6_PAD_DISP0_DAT13__AUDMUX_AUD5_RXFS	= IOMUX_PAD(0x04B8, 0x01A4, 3, 0x07D8, 1, 0),
-	MX6_PAD_DISP0_DAT13__SDMA_DBG_EVT_CHN0 = IOMUX_PAD(0x04B8, 0x01A4, 4, 0x0000, 0, 0),
-	MX6_PAD_DISP0_DAT13__GPIO_5_7		= IOMUX_PAD(0x04B8, 0x01A4, 5, 0x0000, 0, 0),
-	MX6_PAD_DISP0_DAT13__MMDC_DEBUG_18	= IOMUX_PAD(0x04B8, 0x01A4, 6, 0x0000, 0, 0),
-	MX6_PAD_DISP0_DAT13__PL301_PER1_HADR24 = IOMUX_PAD(0x04B8, 0x01A4, 7, 0x0000, 0, 0),
-	MX6_PAD_DISP0_DAT14__IPU1_DISP0_DAT_14	= IOMUX_PAD(0x04BC, 0x01A8, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
-	MX6_PAD_DISP0_DAT14__IPU2_DISP0_DAT_14	= IOMUX_PAD(0x04BC, 0x01A8, 1, 0x0000, 0, 0),
-	MX6_PAD_DISP0_DAT14__AUDMUX_AUD5_RXC	= IOMUX_PAD(0x04BC, 0x01A8, 3, 0x07D4, 1, 0),
-	MX6_PAD_DISP0_DAT14__SDMA_DBG_EVT_CHN1 = IOMUX_PAD(0x04BC, 0x01A8, 4, 0x0000, 0, 0),
-	MX6_PAD_DISP0_DAT14__GPIO_5_8		= IOMUX_PAD(0x04BC, 0x01A8, 5, 0x0000, 0, 0),
-	MX6_PAD_DISP0_DAT14__MMDC_DEBUG_19	= IOMUX_PAD(0x04BC, 0x01A8, 6, 0x0000, 0, 0),
-	MX6_PAD_DISP0_DAT15__IPU1_DISP0_DAT_15	= IOMUX_PAD(0x04C0, 0x01AC, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
-	MX6_PAD_DISP0_DAT15__IPU2_DISP0_DAT_15	= IOMUX_PAD(0x04C0, 0x01AC, 1, 0x0000, 0, 0),
-	MX6_PAD_DISP0_DAT15__ECSPI1_SS1	= IOMUX_PAD(0x04C0, 0x01AC, 2, 0x0804, 1, 0),
-	MX6_PAD_DISP0_DAT15__ECSPI2_SS1	= IOMUX_PAD(0x04C0, 0x01AC, 3, 0x0820, 1, 0),
-	MX6_PAD_DISP0_DAT15__SDMA_DBG_EVT_CHN2 = IOMUX_PAD(0x04C0, 0x01AC, 4, 0x0000, 0, 0),
-	MX6_PAD_DISP0_DAT15__GPIO_5_9		= IOMUX_PAD(0x04C0, 0x01AC, 5, 0x0000, 0, 0),
-	MX6_PAD_DISP0_DAT15__MMDC_DEBUG_20	= IOMUX_PAD(0x04C0, 0x01AC, 6, 0x0000, 0, 0),
-	MX6_PAD_DISP0_DAT15__PL301_PER1_HADR25 = IOMUX_PAD(0x04C0, 0x01AC, 7, 0x0000, 0, 0),
-	MX6_PAD_DISP0_DAT16__IPU1_DISP0_DAT_16	= IOMUX_PAD(0x04C4, 0x01B0, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
-	MX6_PAD_DISP0_DAT16__IPU2_DISP0_DAT_16	= IOMUX_PAD(0x04C4, 0x01B0, 1, 0x0000, 0, 0),
-	MX6_PAD_DISP0_DAT16__ECSPI2_MOSI	= IOMUX_PAD(0x04C4, 0x01B0, 2, 0x0818, 1, 0),
-	MX6_PAD_DISP0_DAT16__AUDMUX_AUD5_TXC	= IOMUX_PAD(0x04C4, 0x01B0, 3, 0x07DC, 0, 0),
-	MX6_PAD_DISP0_DAT16__SDMA_EXT_EVENT_0	= IOMUX_PAD(0x04C4, 0x01B0, 4, 0x090C, 0, 0),
-	MX6_PAD_DISP0_DAT16__GPIO_5_10		= IOMUX_PAD(0x04C4, 0x01B0, 5, 0x0000, 0, 0),
-	MX6_PAD_DISP0_DAT16__MMDC_DEBUG_21	= IOMUX_PAD(0x04C4, 0x01B0, 6, 0x0000, 0, 0),
-	MX6_PAD_DISP0_DAT16__PL301_PER1_HADR26 = IOMUX_PAD(0x04C4, 0x01B0, 7, 0x0000, 0, 0),
-	MX6_PAD_DISP0_DAT17__IPU1_DISP0_DAT_17	= IOMUX_PAD(0x04C8, 0x01B4, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
-	MX6_PAD_DISP0_DAT17__IPU2_DISP0_DAT_17	= IOMUX_PAD(0x04C8, 0x01B4, 1, 0x0000, 0, 0),
-	MX6_PAD_DISP0_DAT17__ECSPI2_MISO	= IOMUX_PAD(0x04C8, 0x01B4, 2, 0x0814, 1, 0),
-	MX6_PAD_DISP0_DAT17__AUDMUX_AUD5_TXD	= IOMUX_PAD(0x04C8, 0x01B4, 3, 0x07D0, 0, 0),
-	MX6_PAD_DISP0_DAT17__SDMA_EXT_EVENT_1	= IOMUX_PAD(0x04C8, 0x01B4, 4, 0x0910, 0, 0),
-	MX6_PAD_DISP0_DAT17__GPIO_5_11		= IOMUX_PAD(0x04C8, 0x01B4, 5, 0x0000, 0, 0),
-	MX6_PAD_DISP0_DAT17__MMDC_DEBUG_22	= IOMUX_PAD(0x04C8, 0x01B4, 6, 0x0000, 0, 0),
-	MX6_PAD_DISP0_DAT17__PL301_PER1_HADR27	= IOMUX_PAD(0x04C8, 0x01B4, 7, 0x0000, 0, 0),
-	MX6_PAD_DISP0_DAT18__IPU1_DISP0_DAT_18	= IOMUX_PAD(0x04CC, 0x01B8, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
-	MX6_PAD_DISP0_DAT18__IPU2_DISP0_DAT_18	= IOMUX_PAD(0x04CC, 0x01B8, 1, 0x0000, 0, 0),
-	MX6_PAD_DISP0_DAT18__ECSPI2_SS0	= IOMUX_PAD(0x04CC, 0x01B8, 2, 0x081C, 1, 0),
-	MX6_PAD_DISP0_DAT18__AUDMUX_AUD5_TXFS	= IOMUX_PAD(0x04CC, 0x01B8, 3, 0x07E0, 0, 0),
-	MX6_PAD_DISP0_DAT18__AUDMUX_AUD4_RXFS	= IOMUX_PAD(0x04CC, 0x01B8, 4, 0x07C0, 0, 0),
-	MX6_PAD_DISP0_DAT18__GPIO_5_12		= IOMUX_PAD(0x04CC, 0x01B8, 5, 0x0000, 0, 0),
-	MX6_PAD_DISP0_DAT18__MMDC_DEBUG_23	= IOMUX_PAD(0x04CC, 0x01B8, 6, 0x0000, 0, 0),
-	MX6_PAD_DISP0_DAT18__WEIM_WEIM_CS_2	= IOMUX_PAD(0x04CC, 0x01B8, 7, 0x0000, 0, 0),
-	MX6_PAD_DISP0_DAT19__IPU1_DISP0_DAT_19	= IOMUX_PAD(0x04D0, 0x01BC, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
-	MX6_PAD_DISP0_DAT19__IPU2_DISP0_DAT_19	= IOMUX_PAD(0x04D0, 0x01BC, 1, 0x0000, 0, 0),
-	MX6_PAD_DISP0_DAT19__ECSPI2_SCLK	= IOMUX_PAD(0x04D0, 0x01BC, 2, 0x0810, 1, 0),
-	MX6_PAD_DISP0_DAT19__AUDMUX_AUD5_RXD	= IOMUX_PAD(0x04D0, 0x01BC, 3, 0x07CC, 0, 0),
-	MX6_PAD_DISP0_DAT19__AUDMUX_AUD4_RXC	= IOMUX_PAD(0x04D0, 0x01BC, 4, 0x07BC, 0, 0),
-	MX6_PAD_DISP0_DAT19__GPIO_5_13		= IOMUX_PAD(0x04D0, 0x01BC, 5, 0x0000, 0, 0),
-	MX6_PAD_DISP0_DAT19__MMDC_DEBUG_24	= IOMUX_PAD(0x04D0, 0x01BC, 6, 0x0000, 0, 0),
-	MX6_PAD_DISP0_DAT19__WEIM_WEIM_CS_3	= IOMUX_PAD(0x04D0, 0x01BC, 7, 0x0000, 0, 0),
-	MX6_PAD_DISP0_DAT20__IPU1_DISP0_DAT_20	= IOMUX_PAD(0x04D4, 0x01C0, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
-	MX6_PAD_DISP0_DAT20__IPU2_DISP0_DAT_20	= IOMUX_PAD(0x04D4, 0x01C0, 1, 0x0000, 0, 0),
-	MX6_PAD_DISP0_DAT20__ECSPI1_SCLK	= IOMUX_PAD(0x04D4, 0x01C0, 2, 0x07F4, 1, 0),
-	MX6_PAD_DISP0_DAT20__AUDMUX_AUD4_TXC	= IOMUX_PAD(0x04D4, 0x01C0, 3, 0x07C4, 0, 0),
-	MX6_PAD_DISP0_DAT20__SDMA_DBG_EVT_CHN7	= IOMUX_PAD(0x04D4, 0x01C0, 4, 0x0000, 0, 0),
-	MX6_PAD_DISP0_DAT20__GPIO_5_14		= IOMUX_PAD(0x04D4, 0x01C0, 5, 0x0000, 0, 0),
-	MX6_PAD_DISP0_DAT20__MMDC_DEBUG_25	= IOMUX_PAD(0x04D4, 0x01C0, 6, 0x0000, 0, 0),
-	MX6_PAD_DISP0_DAT20__PL301_PER1_HADR28 = IOMUX_PAD(0x04D4, 0x01C0, 7, 0x0000, 0, 0),
-	MX6_PAD_DISP0_DAT21__IPU1_DISP0_DAT_21	= IOMUX_PAD(0x04D8, 0x01C4, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
-	MX6_PAD_DISP0_DAT21__IPU2_DISP0_DAT_21	= IOMUX_PAD(0x04D8, 0x01C4, 1, 0x0000, 0, 0),
-	MX6_PAD_DISP0_DAT21__ECSPI1_MOSI	= IOMUX_PAD(0x04D8, 0x01C4, 2, 0x07FC, 1, 0),
-	MX6_PAD_DISP0_DAT21__AUDMUX_AUD4_TXD	= IOMUX_PAD(0x04D8, 0x01C4, 3, 0x07B8, 1, 0),
-	MX6_PAD_DISP0_DAT21__SDMA_DBG_BUS_DEV0 = IOMUX_PAD(0x04D8, 0x01C4, 4, 0x0000, 0, 0),
-	MX6_PAD_DISP0_DAT21__GPIO_5_15		= IOMUX_PAD(0x04D8, 0x01C4, 5, 0x0000, 0, 0),
-	MX6_PAD_DISP0_DAT21__MMDC_DEBUG_26	= IOMUX_PAD(0x04D8, 0x01C4, 6, 0x0000, 0, 0),
-	MX6_PAD_DISP0_DAT21__PL301_PER1_HADR29 = IOMUX_PAD(0x04D8, 0x01C4, 7, 0x0000, 0, 0),
-	MX6_PAD_DISP0_DAT22__IPU1_DISP0_DAT_22	= IOMUX_PAD(0x04DC, 0x01C8, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
-	MX6_PAD_DISP0_DAT22__IPU2_DISP0_DAT_22	= IOMUX_PAD(0x04DC, 0x01C8, 1, 0x0000, 0, 0),
-	MX6_PAD_DISP0_DAT22__ECSPI1_MISO	= IOMUX_PAD(0x04DC, 0x01C8, 2, 0x07F8, 1, 0),
-	MX6_PAD_DISP0_DAT22__AUDMUX_AUD4_TXFS	= IOMUX_PAD(0x04DC, 0x01C8, 3, 0x07C8, 1, 0),
-	MX6_PAD_DISP0_DAT22__SDMA_DBG_BUS_DEV1 = IOMUX_PAD(0x04DC, 0x01C8, 4, 0x0000, 0, 0),
-	MX6_PAD_DISP0_DAT22__GPIO_5_16		= IOMUX_PAD(0x04DC, 0x01C8, 5, 0x0000, 0, 0),
-	MX6_PAD_DISP0_DAT22__MMDC_DEBUG_27	= IOMUX_PAD(0x04DC, 0x01C8, 6, 0x0000, 0, 0),
-	MX6_PAD_DISP0_DAT22__PL301_PER1_HADR30 = IOMUX_PAD(0x04DC, 0x01C8, 7, 0x0000, 0, 0),
-	MX6_PAD_DISP0_DAT23__IPU1_DISP0_DAT_23	= IOMUX_PAD(0x04E0, 0x01CC, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
-	MX6_PAD_DISP0_DAT23__IPU2_DISP0_DAT_23	= IOMUX_PAD(0x04E0, 0x01CC, 1, 0x0000, 0, 0),
-	MX6_PAD_DISP0_DAT23__ECSPI1_SS0	= IOMUX_PAD(0x04E0, 0x01CC, 2, 0x0800, 1, 0),
-	MX6_PAD_DISP0_DAT23__AUDMUX_AUD4_RXD	= IOMUX_PAD(0x04E0, 0x01CC, 3, 0x07B4, 1, 0),
-	MX6_PAD_DISP0_DAT23__SDMA_DBG_BUS_DEV2 = IOMUX_PAD(0x04E0, 0x01CC, 4, 0x0000, 0, 0),
-	MX6_PAD_DISP0_DAT23__GPIO_5_17		= IOMUX_PAD(0x04E0, 0x01CC, 5, 0x0000, 0, 0),
-	MX6_PAD_DISP0_DAT23__MMDC_DEBUG_28	= IOMUX_PAD(0x04E0, 0x01CC, 6, 0x0000, 0, 0),
-	MX6_PAD_DISP0_DAT23__PL301_PER1_HADR31	= IOMUX_PAD(0x04E0, 0x01CC, 7, 0x0000, 0, 0),
-	MX6_PAD_ENET_MDIO__RESERVED_RESERVED	= IOMUX_PAD(0x04E4, 0x01D0, 0, 0x0000, 0, 0),
-	MX6_PAD_ENET_MDIO__ENET_MDIO		= IOMUX_PAD(0x04E4, 0x01D0, 1, 0x0840, 0, 0),
-	MX6_PAD_ENET_MDIO__ESAI1_SCKR		= IOMUX_PAD(0x04E4, 0x01D0, 2, 0x086C, 0, 0),
-	MX6_PAD_ENET_MDIO__SDMA_DEBUG_BUS_DEV3 = IOMUX_PAD(0x04E4, 0x01D0, 3, 0x0000, 0, 0),
-	MX6_PAD_ENET_MDIO__ENET_1588_EVT1_OUT	= IOMUX_PAD(0x04E4, 0x01D0, 4, 0x0000, 0, 0),
-	MX6_PAD_ENET_MDIO__GPIO_1_22		= IOMUX_PAD(0x04E4, 0x01D0, 5, 0x0000, 0, 0),
-	MX6_PAD_ENET_MDIO__SPDIF_PLOCK		= IOMUX_PAD(0x04E4, 0x01D0, 6, 0x0000, 0, 0),
-	MX6_PAD_ENET_REF_CLK__RESERVED_RSRVED	= IOMUX_PAD(0x04E8, 0x01D4, 0, 0x0000, 0, 0),
-	MX6_PAD_ENET_REF_CLK__ENET_TX_CLK	= IOMUX_PAD(0x04E8, 0x01D4, 1, 0x0000, 0, 0),
-	MX6_PAD_ENET_REF_CLK__ESAI1_FSR	= IOMUX_PAD(0x04E8, 0x01D4, 2, 0x085C, 0, 0),
-	MX6_PAD_ENET_REF_CLK__SDMA_DBGBUS_DEV4 = IOMUX_PAD(0x04E8, 0x01D4, 3, 0x0000, 0, 0),
-	MX6_PAD_ENET_REF_CLK__GPIO_1_23	= IOMUX_PAD(0x04E8, 0x01D4, 5, 0x0000, 0, 0),
-	MX6_PAD_ENET_REF_CLK__SPDIF_SRCLK	= IOMUX_PAD(0x04E8, 0x01D4, 6, 0x0000, 0, 0),
-	MX6_PAD_ENET_REF_CLK__USBPHY1_RX_SQH	= IOMUX_PAD(0x04E8, 0x01D4, 7, 0x0000, 0, 0),
-	MX6_PAD_ENET_RX_ER__ENET_RX_ER		= IOMUX_PAD(0x04EC, 0x01D8, 1, 0x0000, 0, 0),
-	MX6_PAD_ENET_RX_ER__ESAI1_HCKR		= IOMUX_PAD(0x04EC, 0x01D8, 2, 0x0864, 0, 0),
-	MX6_PAD_ENET_RX_ER__SPDIF_IN1		= IOMUX_PAD(0x04EC, 0x01D8, 3, 0x0914, 1, 0),
-	MX6_PAD_ENET_RX_ER__ENET_1588_EVT2_OUT = IOMUX_PAD(0x04EC, 0x01D8, 4, 0x0000, 0, 0),
-	MX6_PAD_ENET_RX_ER__GPIO_1_24		= IOMUX_PAD(0x04EC, 0x01D8, 5, 0x0000, 0, 0),
-	MX6_PAD_ENET_RX_ER__PHY_TDI		= IOMUX_PAD(0x04EC, 0x01D8, 6, 0x0000, 0, 0),
-	MX6_PAD_ENET_RX_ER__USBPHY1_RX_HS_RXD	= IOMUX_PAD(0x04EC, 0x01D8, 7, 0x0000, 0, 0),
-	MX6_PAD_ENET_CRS_DV__RESERVED_RSRVED	= IOMUX_PAD(0x04F0, 0x01DC, 0, 0x0000, 0, 0),
-	MX6_PAD_ENET_CRS_DV__ENET_RX_EN	= IOMUX_PAD(0x04F0, 0x01DC, 1, 0x0858, 1, 0),
-	MX6_PAD_ENET_CRS_DV__ESAI1_SCKT	= IOMUX_PAD(0x04F0, 0x01DC, 2, 0x0870, 0, 0),
-	MX6_PAD_ENET_CRS_DV__SPDIF_EXTCLK	= IOMUX_PAD(0x04F0, 0x01DC, 3, 0x0918, 1, 0),
-	MX6_PAD_ENET_CRS_DV__GPIO_1_25		= IOMUX_PAD(0x04F0, 0x01DC, 5, 0x0000, 0, 0),
-	MX6_PAD_ENET_CRS_DV__PHY_TDO		= IOMUX_PAD(0x04F0, 0x01DC, 6, 0x0000, 0, 0),
-	MX6_PAD_ENET_CRS_DV__USBPHY1_RX_FS_RXD	= IOMUX_PAD(0x04F0, 0x01DC, 7, 0x0000, 0, 0),
-	MX6_PAD_ENET_RXD1__MLB_MLBSIG		= IOMUX_PAD(0x04F4, 0x01E0, 0, 0x0908, 0, 0),
-	MX6_PAD_ENET_RXD1__ENET_RDATA_1	= IOMUX_PAD(0x04F4, 0x01E0, 1, 0x084C, 1, 0),
-	MX6_PAD_ENET_RXD1__ESAI1_FST		= IOMUX_PAD(0x04F4, 0x01E0, 2, 0x0860, 0, 0),
-	MX6_PAD_ENET_RXD1__ENET_1588_EVT3_OUT	= IOMUX_PAD(0x04F4, 0x01E0, 4, 0x0000, 0, 0),
-	MX6_PAD_ENET_RXD1__GPIO_1_26		= IOMUX_PAD(0x04F4, 0x01E0, 5, 0x0000, 0, 0),
-	MX6_PAD_ENET_RXD1__PHY_TCK		= IOMUX_PAD(0x04F4, 0x01E0, 6, 0x0000, 0, 0),
-	MX6_PAD_ENET_RXD1__USBPHY1_RX_DISCON	= IOMUX_PAD(0x04F4, 0x01E0, 7, 0x0000, 0, 0),
-	MX6_PAD_ENET_RXD0__OSC32K_32K_OUT	= IOMUX_PAD(0x04F8, 0x01E4, 0, 0x0000, 0, 0),
-	MX6_PAD_ENET_RXD0__ENET_RDATA_0	= IOMUX_PAD(0x04F8, 0x01E4, 1, 0x0848, 1, 0),
-	MX6_PAD_ENET_RXD0__ESAI1_HCKT		= IOMUX_PAD(0x04F8, 0x01E4, 2, 0x0868, 0, 0),
-	MX6_PAD_ENET_RXD0__SPDIF_OUT1		= IOMUX_PAD(0x04F8, 0x01E4, 3, 0x0000, 0, 0),
-	MX6_PAD_ENET_RXD0__GPIO_1_27		= IOMUX_PAD(0x04F8, 0x01E4, 5, 0x0000, 0, 0),
-	MX6_PAD_ENET_RXD0__PHY_TMS		= IOMUX_PAD(0x04F8, 0x01E4, 6, 0x0000, 0, 0),
-	MX6_PAD_ENET_RXD0__USBPHY1_PLL_CK20DIV	= IOMUX_PAD(0x04F8, 0x01E4, 7, 0x0000, 0, 0),
-	MX6_PAD_ENET_TX_EN__RESERVED_RSRVED	= IOMUX_PAD(0x04FC, 0x01E8, 0, 0x0000, 0, 0),
-	MX6_PAD_ENET_TX_EN__ENET_TX_EN		= IOMUX_PAD(0x04FC, 0x01E8, 1, 0x0000, 0, 0),
-	MX6_PAD_ENET_TX_EN__ESAI1_TX3_RX2	= IOMUX_PAD(0x04FC, 0x01E8, 2, 0x0880, 0, 0),
-	MX6_PAD_ENET_TX_EN__GPIO_1_28		= IOMUX_PAD(0x04FC, 0x01E8, 5, 0x0000, 0, 0),
-	MX6_PAD_ENET_TX_EN__SATA_PHY_TDI	= IOMUX_PAD(0x04FC, 0x01E8, 6, 0x0000, 0, 0),
-	MX6_PAD_ENET_TX_EN__USBPHY2_RX_SQH	= IOMUX_PAD(0x04FC, 0x01E8, 7, 0x0000, 0, 0),
-	MX6_PAD_ENET_TXD1__MLB_MLBCLK		= IOMUX_PAD(0x0500, 0x01EC, 0, 0x0900, 0, 0),
-	MX6_PAD_ENET_TXD1__ENET_TDATA_1	= IOMUX_PAD(0x0500, 0x01EC, 1, 0x0000, 0, 0),
-	MX6_PAD_ENET_TXD1__ESAI1_TX2_RX3	= IOMUX_PAD(0x0500, 0x01EC, 2, 0x087C, 0, 0),
-	MX6_PAD_ENET_TXD1__ENET_1588_EVENT0_IN	= IOMUX_PAD(0x0500, 0x01EC, 4, 0x0000, 0, 0),
-	MX6_PAD_ENET_TXD1__GPIO_1_29		= IOMUX_PAD(0x0500, 0x01EC, 5, 0x0000, 0, 0),
-	MX6_PAD_ENET_TXD1__SATA_PHY_TDO	= IOMUX_PAD(0x0500, 0x01EC, 6, 0x0000, 0, 0),
-	MX6_PAD_ENET_TXD1__USBPHY2_RX_HS_RXD	= IOMUX_PAD(0x0500, 0x01EC, 7, 0x0000, 0, 0),
-	MX6_PAD_ENET_TXD0__RESERVED_RSRVED	= IOMUX_PAD(0x0504, 0x01F0, 0, 0x0000, 0, 0),
-	MX6_PAD_ENET_TXD0__ENET_TDATA_0	= IOMUX_PAD(0x0504, 0x01F0, 1, 0x0000, 0, 0),
-	MX6_PAD_ENET_TXD0__ESAI1_TX4_RX1	= IOMUX_PAD(0x0504, 0x01F0, 2, 0x0884, 0, 0),
-	MX6_PAD_ENET_TXD0__GPIO_1_30		= IOMUX_PAD(0x0504, 0x01F0, 5, 0x0000, 0, 0),
-	MX6_PAD_ENET_TXD0__SATA_PHY_TCK	= IOMUX_PAD(0x0504, 0x01F0, 6, 0x0000, 0, 0),
-	MX6_PAD_ENET_TXD0__USBPHY2_RX_FS_RXD   = IOMUX_PAD(0x0504, 0x01F0, 7, 0x0000, 0, 0),
-	MX6_PAD_ENET_MDC__MLB_MLBDAT		= IOMUX_PAD(0x0508, 0x01F4, 0, 0x0904, 0, 0),
-	MX6_PAD_ENET_MDC__ENET_MDC		= IOMUX_PAD(0x0508, 0x01F4, 1, 0x0000, 0, 0),
-	MX6_PAD_ENET_MDC__ESAI1_TX5_RX0	= IOMUX_PAD(0x0508, 0x01F4, 2, 0x0888, 0, 0),
-	MX6_PAD_ENET_MDC__ENET_1588_EVENT1_IN	= IOMUX_PAD(0x0508, 0x01F4, 4, 0x0000, 0, 0),
-	MX6_PAD_ENET_MDC__GPIO_1_31		= IOMUX_PAD(0x0508, 0x01F4, 5, 0x0000, 0, 0),
-	MX6_PAD_ENET_MDC__SATA_PHY_TMS		= IOMUX_PAD(0x0508, 0x01F4, 6, 0x0000, 0, 0),
-	MX6_PAD_ENET_MDC__USBPHY2_RX_DISCON	= IOMUX_PAD(0x0508, 0x01F4, 7, 0x0000, 0, 0),
-	MX6_PAD_DRAM_D40__MMDC_DRAM_D_40	= IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
-	MX6_PAD_DRAM_D41__MMDC_DRAM_D_41	= IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
-	MX6_PAD_DRAM_D42__MMDC_DRAM_D_42	= IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
-	MX6_PAD_DRAM_D43__MMDC_DRAM_D_43	= IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
-	MX6_PAD_DRAM_D44__MMDC_DRAM_D_44	= IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
-	MX6_PAD_DRAM_D45__MMDC_DRAM_D_45	= IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
-	MX6_PAD_DRAM_D46__MMDC_DRAM_D_46	= IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
-	MX6_PAD_DRAM_D47__MMDC_DRAM_D_47	= IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
-	MX6_PAD_DRAM_SDQS5__MMDC_DRAM_SDQS_5	= IOMUX_PAD(0x050C, NO_MUX_I, 0, 0x0000, 0, 0),
-	MX6_PAD_DRAM_DQM5__MMDC_DRAM_DQM_5	= IOMUX_PAD(0x0510, NO_MUX_I, 0, 0x0000, 0, 0),
-	MX6_PAD_DRAM_D32__MMDC_DRAM_D_32	= IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
-	MX6_PAD_DRAM_D33__MMDC_DRAM_D_33	= IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
-	MX6_PAD_DRAM_D34__MMDC_DRAM_D_34	= IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
-	MX6_PAD_DRAM_D35__MMDC_DRAM_D_35	= IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
-	MX6_PAD_DRAM_D36__MMDC_DRAM_D_36	= IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
-	MX6_PAD_DRAM_D37__MMDC_DRAM_D_37	= IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
-	MX6_PAD_DRAM_D38__MMDC_DRAM_D_38	= IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
-	MX6_PAD_DRAM_D39__MMDC_DRAM_D_39	= IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
-	MX6_PAD_DRAM_DQM4__MMDC_DRAM_DQM_4	= IOMUX_PAD(0x0514, NO_MUX_I, 0, 0x0000, 0, 0),
-	MX6_PAD_DRAM_SDQS4__MMDC_DRAM_SDQS_4	= IOMUX_PAD(0x0518, NO_MUX_I, 0, 0x0000, 0, 0),
-	MX6_PAD_DRAM_D24__MMDC_DRAM_D_24	= IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
-	MX6_PAD_DRAM_D25__MMDC_DRAM_D_25	= IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
-	MX6_PAD_DRAM_D26__MMDC_DRAM_D_26	= IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
-	MX6_PAD_DRAM_D27__MMDC_DRAM_D_27	= IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
-	MX6_PAD_DRAM_D28__MMDC_DRAM_D_28	= IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
-	MX6_PAD_DRAM_D29__MMDC_DRAM_D_29	= IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
-	MX6_PAD_DRAM_SDQS3__MMDC_DRAM_SDQS_3	= IOMUX_PAD(0x051C, NO_MUX_I, 0, 0x0000, 0, 0),
-	MX6_PAD_DRAM_D30__MMDC_DRAM_D_30	= IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
-	MX6_PAD_DRAM_D31__MMDC_DRAM_D_31	= IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
-	MX6_PAD_DRAM_DQM3__MMDC_DRAM_DQM_3	= IOMUX_PAD(0x0520, NO_MUX_I, 0, 0x0000, 0, 0),
-	MX6_PAD_DRAM_D16__MMDC_DRAM_D_16	= IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
-	MX6_PAD_DRAM_D17__MMDC_DRAM_D_17	= IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
-	MX6_PAD_DRAM_D18__MMDC_DRAM_D_18	= IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
-	MX6_PAD_DRAM_D19__MMDC_DRAM_D_19	= IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
-	MX6_PAD_DRAM_D20__MMDC_DRAM_D_20	= IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
-	MX6_PAD_DRAM_D21__MMDC_DRAM_D_21	= IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
-	MX6_PAD_DRAM_D22__MMDC_DRAM_D_22	= IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
-	MX6_PAD_DRAM_SDQS2__MMDC_DRAM_SDQS_2	= IOMUX_PAD(0x0524, NO_MUX_I, 0, 0x0000, 0, 0),
-	MX6_PAD_DRAM_D23__MMDC_DRAM_D_23	= IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
-	MX6_PAD_DRAM_DQM2__MMDC_DRAM_DQM_2	= IOMUX_PAD(0x0528, NO_MUX_I, 0, 0x0000, 0, 0),
-	MX6_PAD_DRAM_A0__MMDC_DRAM_A_0		= IOMUX_PAD(0x052C, NO_MUX_I, 0, 0x0000, 0, 0),
-	MX6_PAD_DRAM_A1__MMDC_DRAM_A_1		= IOMUX_PAD(0x0530, NO_MUX_I, 0, 0x0000, 0, 0),
-	MX6_PAD_DRAM_A2__MMDC_DRAM_A_2		= IOMUX_PAD(0x0534, NO_MUX_I, 0, 0x0000, 0, 0),
-	MX6_PAD_DRAM_A3__MMDC_DRAM_A_3		= IOMUX_PAD(0x0538, NO_MUX_I, 0, 0x0000, 0, 0),
-	MX6_PAD_DRAM_A4__MMDC_DRAM_A_4		= IOMUX_PAD(0x053C, NO_MUX_I, 0, 0x0000, 0, 0),
-	MX6_PAD_DRAM_A5__MMDC_DRAM_A_5		= IOMUX_PAD(0x0540, NO_MUX_I, 0, 0x0000, 0, 0),
-	MX6_PAD_DRAM_A6__MMDC_DRAM_A_6		= IOMUX_PAD(0x0544, NO_MUX_I, 0, 0x0000, 0, 0),
-	MX6_PAD_DRAM_A7__MMDC_DRAM_A_7		= IOMUX_PAD(0x0548, NO_MUX_I, 0, 0x0000, 0, 0),
-	MX6_PAD_DRAM_A8__MMDC_DRAM_A_8		= IOMUX_PAD(0x054C, NO_MUX_I, 0, 0x0000, 0, 0),
-	MX6_PAD_DRAM_A9__MMDC_DRAM_A_9		= IOMUX_PAD(0x0550, NO_MUX_I, 0, 0x0000, 0, 0),
-	MX6_PAD_DRAM_A10__MMDC_DRAM_A_10	= IOMUX_PAD(0x0554, NO_MUX_I, 0, 0x0000, 0, 0),
-	MX6_PAD_DRAM_A11__MMDC_DRAM_A_11	= IOMUX_PAD(0x0558, NO_MUX_I, 0, 0x0000, 0, 0),
-	MX6_PAD_DRAM_A12__MMDC_DRAM_A_12	= IOMUX_PAD(0x055C, NO_MUX_I, 0, 0x0000, 0, 0),
-	MX6_PAD_DRAM_A13__MMDC_DRAM_A_13	= IOMUX_PAD(0x0560, NO_MUX_I, 0, 0x0000, 0, 0),
-	MX6_PAD_DRAM_A14__MMDC_DRAM_A_14	= IOMUX_PAD(0x0564, NO_MUX_I, 0, 0x0000, 0, 0),
-	MX6_PAD_DRAM_A15__MMDC_DRAM_A_15	= IOMUX_PAD(0x0568, NO_MUX_I, 0, 0x0000, 0, 0),
-	MX6_PAD_DRAM_CAS__MMDC_DRAM_CAS	= IOMUX_PAD(0x056C, NO_MUX_I, 0, 0x0000, 0, 0),
-	MX6_PAD_DRAM_CS0__MMDC_DRAM_CS_0	= IOMUX_PAD(0x0570, NO_MUX_I, 0, 0x0000, 0, 0),
-	MX6_PAD_DRAM_CS1__MMDC_DRAM_CS_1	= IOMUX_PAD(0x0574, NO_MUX_I, 0, 0x0000, 0, 0),
-	MX6_PAD_DRAM_RAS__MMDC_DRAM_RAS	= IOMUX_PAD(0x0578, NO_MUX_I, 0, 0x0000, 0, 0),
-	MX6_PAD_DRAM_RESET__MMDC_DRAM_RESET	= IOMUX_PAD(0x057C, NO_MUX_I, 0, 0x0000, 0, 0),
-	MX6_PAD_DRAM_SDBA0__MMDC_DRAM_SDBA_0	= IOMUX_PAD(0x0580, NO_MUX_I, 0, 0x0000, 0, 0),
-	MX6_PAD_DRAM_SDBA1__MMDC_DRAM_SDBA_1	= IOMUX_PAD(0x0584, NO_MUX_I, 0, 0x0000, 0, 0),
-	MX6_PAD_DRAM_SDCLK_0__MMDC_DRAM_SDCLK0	= IOMUX_PAD(0x0588, NO_MUX_I, 0, 0x0000, 0, 0),
-	MX6_PAD_DRAM_SDBA2__MMDC_DRAM_SDBA_2	= IOMUX_PAD(0x058C, NO_MUX_I, 0, 0x0000, 0, 0),
-	MX6_PAD_DRAM_SDCKE0__MMDC_DRAM_SDCKE_0	= IOMUX_PAD(0x0590, NO_MUX_I, 0, 0x0000, 0, 0),
-	MX6_PAD_DRAM_SDCLK_1__MMDC_DRAM_SDCLK1	= IOMUX_PAD(0x0594, NO_MUX_I, 0, 0x0000, 0, 0),
-	MX6_PAD_DRAM_SDCKE1__MMDC_DRAM_SDCKE_1	= IOMUX_PAD(0x0598, NO_MUX_I, 0, 0x0000, 0, 0),
-	MX6_PAD_DRAM_SDODT0__MMDC_DRAM_ODT_0	= IOMUX_PAD(0x059C, NO_MUX_I, 0, 0x0000, 0, 0),
-	MX6_PAD_DRAM_SDODT1__MMDC_DRAM_ODT_1	= IOMUX_PAD(0x05A0, NO_MUX_I, 0, 0x0000, 0, 0),
-	MX6_PAD_DRAM_SDWE__MMDC_DRAM_SDWE	= IOMUX_PAD(0x05A4, NO_MUX_I, 0, 0x0000, 0, 0),
-	MX6_PAD_DRAM_D0__MMDC_DRAM_D_0		= IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
-	MX6_PAD_DRAM_D1__MMDC_DRAM_D_1		= IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
-	MX6_PAD_DRAM_D2__MMDC_DRAM_D_2		= IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
-	MX6_PAD_DRAM_D3__MMDC_DRAM_D_3		= IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
-	MX6_PAD_DRAM_D4__MMDC_DRAM_D_4		= IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
-	MX6_PAD_DRAM_D5__MMDC_DRAM_D_5		= IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
-	MX6_PAD_DRAM_SDQS0__MMDC_DRAM_SDQS_0	= IOMUX_PAD(0x05A8, NO_MUX_I, 0, 0x0000, 0, 0),
-	MX6_PAD_DRAM_D6__MMDC_DRAM_D_6		= IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
-	MX6_PAD_DRAM_D7__MMDC_DRAM_D_7		= IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
-	MX6_PAD_DRAM_DQM0__MMDC_DRAM_DQM_0	= IOMUX_PAD(0x05AC, NO_MUX_I, 0, 0x0000, 0, 0),
-	MX6_PAD_DRAM_D8__MMDC_DRAM_D_8		= IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
-	MX6_PAD_DRAM_D9__MMDC_DRAM_D_9		= IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
-	MX6_PAD_DRAM_D10__MMDC_DRAM_D_10	= IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
-	MX6_PAD_DRAM_D11__MMDC_DRAM_D_11	= IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
-	MX6_PAD_DRAM_D12__MMDC_DRAM_D_12	= IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
-	MX6_PAD_DRAM_D13__MMDC_DRAM_D_13	= IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
-	MX6_PAD_DRAM_D14__MMDC_DRAM_D_14	= IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
-	MX6_PAD_DRAM_SDQS1__MMDC_DRAM_SDQS_1	= IOMUX_PAD(0x05B0, NO_MUX_I, 0, 0x0000, 0, 0),
-	MX6_PAD_DRAM_D15__MMDC_DRAM_D_15	= IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
-	MX6_PAD_DRAM_DQM1__MMDC_DRAM_DQM_1	= IOMUX_PAD(0x05B4, NO_MUX_I, 0, 0x0000, 0, 0),
-	MX6_PAD_DRAM_D48__MMDC_DRAM_D_48	= IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
-	MX6_PAD_DRAM_D49__MMDC_DRAM_D_49	= IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
-	MX6_PAD_DRAM_D50__MMDC_DRAM_D_50	= IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
-	MX6_PAD_DRAM_D51__MMDC_DRAM_D_51	= IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
-	MX6_PAD_DRAM_D52__MMDC_DRAM_D_52	= IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
-	MX6_PAD_DRAM_D53__MMDC_DRAM_D_53	= IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
-	MX6_PAD_DRAM_D54__MMDC_DRAM_D_54	= IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
-	MX6_PAD_DRAM_D55__MMDC_DRAM_D_55	= IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
-	MX6_PAD_DRAM_SDQS6__MMDC_DRAM_SDQS_6	= IOMUX_PAD(0x05B8, NO_MUX_I, 0, 0x0000, 0, 0),
-	MX6_PAD_DRAM_DQM6__MMDC_DRAM_DQM_6	= IOMUX_PAD(0x05BC, NO_MUX_I, 0, 0x0000, 0, 0),
-	MX6_PAD_DRAM_D56__MMDC_DRAM_D_56	= IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
-	MX6_PAD_DRAM_SDQS7__MMDC_DRAM_SDQS_7	= IOMUX_PAD(0x05C0, NO_MUX_I, 0, 0x0000, 0, 0),
-	MX6_PAD_DRAM_D57__MMDC_DRAM_D_57	= IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
-	MX6_PAD_DRAM_D58__MMDC_DRAM_D_58	= IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
-	MX6_PAD_DRAM_D59__MMDC_DRAM_D_59	= IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
-	MX6_PAD_DRAM_D60__MMDC_DRAM_D_60	= IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
-	MX6_PAD_DRAM_DQM7__MMDC_DRAM_DQM_7	= IOMUX_PAD(0x05C4, NO_MUX_I, 0, 0x0000, 0, 0),
-	MX6_PAD_DRAM_D61__MMDC_DRAM_D_61	= IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
-	MX6_PAD_DRAM_D62__MMDC_DRAM_D_62	= IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
-	MX6_PAD_DRAM_D63__MMDC_DRAM_D_63	= IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
-	MX6_PAD_KEY_COL0__ECSPI1_SCLK		= IOMUX_PAD(0x05C8, 0x01F8, 0, 0x07F4, 2, 0),
-	MX6_PAD_KEY_COL0__ENET_RDATA_3		= IOMUX_PAD(0x05C8, 0x01F8, 1, 0x0854, 1, 0),
-	MX6_PAD_KEY_COL0__AUDMUX_AUD5_TXC	= IOMUX_PAD(0x05C8, 0x01F8, 2, 0x07DC, 1, 0),
-	MX6_PAD_KEY_COL0__KPP_COL_0		= IOMUX_PAD(0x05C8, 0x01F8, 3, 0x0000, 0, 0),
-	MX6_PAD_KEY_COL0__UART4_TXD		= IOMUX_PAD(0x05C8, 0x01F8, 4, 0x0000, 0, 0),
-	MX6_PAD_KEY_COL0__UART4_TXD_RXD	= IOMUX_PAD(0x05C8, 0x01F8, 4, 0x0938, 0, 0),
-	MX6_PAD_KEY_COL0__GPIO_4_6		= IOMUX_PAD(0x05C8, 0x01F8, 5, 0x0000, 0, 0),
-	MX6_PAD_KEY_COL0__DCIC1_DCIC_OUT	= IOMUX_PAD(0x05C8, 0x01F8, 6, 0x0000, 0, 0),
-	MX6_PAD_KEY_COL0__SRC_ANY_PU_RST	= IOMUX_PAD(0x05C8, 0x01F8, 7, 0x0000, 0, 0),
-	MX6_PAD_KEY_ROW0__ECSPI1_MOSI		= IOMUX_PAD(0x05CC, 0x01FC, 0, 0x07FC, 2, 0),
-	MX6_PAD_KEY_ROW0__ENET_TDATA_3		= IOMUX_PAD(0x05CC, 0x01FC, 1, 0x0000, 0, 0),
-	MX6_PAD_KEY_ROW0__AUDMUX_AUD5_TXD	= IOMUX_PAD(0x05CC, 0x01FC, 2, 0x07D0, 1, 0),
-	MX6_PAD_KEY_ROW0__KPP_ROW_0		= IOMUX_PAD(0x05CC, 0x01FC, 3, 0x0000, 0, 0),
-	MX6_PAD_KEY_ROW0__UART4_RXD		= IOMUX_PAD(0x05CC, 0x01FC, 4, 0x0938, 1, 0),
-	MX6_PAD_KEY_ROW0__GPIO_4_7		= IOMUX_PAD(0x05CC, 0x01FC, 5, 0x0000, 0, 0),
-	MX6_PAD_KEY_ROW0__DCIC2_DCIC_OUT	= IOMUX_PAD(0x05CC, 0x01FC, 6, 0x0000, 0, 0),
-	MX6_PAD_KEY_ROW0__PL301_PER1_HADR_0	= IOMUX_PAD(0x05CC, 0x01FC, 7, 0x0000, 0, 0),
-	MX6_PAD_KEY_COL1__ECSPI1_MISO		= IOMUX_PAD(0x05D0, 0x0200, 0, 0x07F8, 2, 0),
-	MX6_PAD_KEY_COL1__ENET_MDIO		= IOMUX_PAD(0x05D0, 0x0200, 1, 0x0840, 1, 0),
-	MX6_PAD_KEY_COL1__AUDMUX_AUD5_TXFS	= IOMUX_PAD(0x05D0, 0x0200, 2, 0x07E0, 1, 0),
-	MX6_PAD_KEY_COL1__KPP_COL_1		= IOMUX_PAD(0x05D0, 0x0200, 3, 0x0000, 0, 0),
-	MX6_PAD_KEY_COL1__UART5_TXD		= IOMUX_PAD(0x05D0, 0x0200, 4, 0x0000, 0, 0),
-	MX6_PAD_KEY_COL1__UART5_TXD_RXD	= IOMUX_PAD(0x05D0, 0x0200, 4, 0x0940, 0, 0),
-	MX6_PAD_KEY_COL1__GPIO_4_8		= IOMUX_PAD(0x05D0, 0x0200, 5, 0x0000, 0, 0),
-	MX6_PAD_KEY_COL1__USDHC1_VSELECT	= IOMUX_PAD(0x05D0, 0x0200, 6, 0x0000, 0, 0),
-	MX6_PAD_KEY_COL1__PL301MX_PER1_HADR_1	= IOMUX_PAD(0x05D0, 0x0200, 7, 0x0000, 0, 0),
-	MX6_PAD_KEY_ROW1__ECSPI1_SS0		= IOMUX_PAD(0x05D4, 0x0204, 0, 0x0800, 2, 0),
-	MX6_PAD_KEY_ROW1__ENET_COL		= IOMUX_PAD(0x05D4, 0x0204, 1, 0x0000, 0, 0),
-	MX6_PAD_KEY_ROW1__AUDMUX_AUD5_RXD	= IOMUX_PAD(0x05D4, 0x0204, 2, 0x07CC, 1, 0),
-	MX6_PAD_KEY_ROW1__KPP_ROW_1		= IOMUX_PAD(0x05D4, 0x0204, 3, 0x0000, 0, 0),
-	MX6_PAD_KEY_ROW1__UART5_RXD		= IOMUX_PAD(0x05D4, 0x0204, 4, 0x0940, 1, 0),
-	MX6_PAD_KEY_ROW1__GPIO_4_9		= IOMUX_PAD(0x05D4, 0x0204, 5, 0x0000, 0, 0),
-	MX6_PAD_KEY_ROW1__USDHC2_VSELECT	= IOMUX_PAD(0x05D4, 0x0204, 6, 0x0000, 0, 0),
-	MX6_PAD_KEY_ROW1__PL301_PER1_HADDR_2	= IOMUX_PAD(0x05D4, 0x0204, 7, 0x0000, 0, 0),
-	MX6_PAD_KEY_COL2__ECSPI1_SS1		= IOMUX_PAD(0x05D8, 0x0208, 0, 0x0804, 2, 0),
-	MX6_PAD_KEY_COL2__ENET_RDATA_2		= IOMUX_PAD(0x05D8, 0x0208, 1, 0x0850, 1, 0),
-	MX6_PAD_KEY_COL2__CAN1_TXCAN		= IOMUX_PAD(0x05D8, 0x0208, 2, 0x0000, 0, 0),
-	MX6_PAD_KEY_COL2__KPP_COL_2		= IOMUX_PAD(0x05D8, 0x0208, 3, 0x0000, 0, 0),
-	MX6_PAD_KEY_COL2__ENET_MDC		= IOMUX_PAD(0x05D8, 0x0208, 4, 0x0000, 0, 0),
-	MX6_PAD_KEY_COL2__GPIO_4_10		= IOMUX_PAD(0x05D8, 0x0208, 5, 0x0000, 0, 0),
-	MX6_PAD_KEY_COL2__USBOH3_H1_PWRCTL_WKP = IOMUX_PAD(0x05D8, 0x0208, 6, 0x0000, 0, 0),
-	MX6_PAD_KEY_COL2__PL301_PER1_HADDR_3   = IOMUX_PAD(0x05D8, 0x0208, 7, 0x0000, 0, 0),
-	MX6_PAD_KEY_ROW2__ECSPI1_SS2		= IOMUX_PAD(0x05DC, 0x020C, 0, 0x0808, 1, 0),
-	MX6_PAD_KEY_ROW2__ENET_TDATA_2		= IOMUX_PAD(0x05DC, 0x020C, 1, 0x0000, 0, 0),
-	MX6_PAD_KEY_ROW2__CAN1_RXCAN		= IOMUX_PAD(0x05DC, 0x020C, 2, 0x07E4, 0, 0),
-	MX6_PAD_KEY_ROW2__KPP_ROW_2		= IOMUX_PAD(0x05DC, 0x020C, 3, 0x0000, 0, 0),
-	MX6_PAD_KEY_ROW2__USDHC2_VSELECT	= IOMUX_PAD(0x05DC, 0x020C, 4, 0x0000, 0, 0),
-	MX6_PAD_KEY_ROW2__GPIO_4_11		= IOMUX_PAD(0x05DC, 0x020C, 5, 0x0000, 0, 0),
-	MX6_PAD_KEY_ROW2__HDMI_TX_CEC_LINE	= IOMUX_PAD(0x05DC, 0x020C, 6, 0x088C, 1, 0),
-	MX6_PAD_KEY_ROW2__PL301_PER1_HADR_4    = IOMUX_PAD(0x05DC, 0x020C, 7, 0x0000, 0, 0),
-	MX6_PAD_KEY_COL3__ECSPI1_SS3		= IOMUX_PAD(0x05E0, 0x0210, 0, 0x080C, 1, 0),
-	MX6_PAD_KEY_COL3__ENET_CRS		= IOMUX_PAD(0x05E0, 0x0210, 1, 0x0000, 0, 0),
-	MX6_PAD_KEY_COL3__HDMI_TX_DDC_SCL	= IOMUX_PAD(0x05E0, 0x0210, 2, 0x0890, 1, 0),
-	MX6_PAD_KEY_COL3__KPP_COL_3		= IOMUX_PAD(0x05E0, 0x0210, 3, 0x0000, 0, 0),
-	MX6_PAD_KEY_COL3__I2C2_SCL		= IOMUX_PAD(0x05E0, 0x0210, 20, 0x08A0, 1, 0),
-	MX6_PAD_KEY_COL3__GPIO_4_12		= IOMUX_PAD(0x05E0, 0x0210, 5, 0x0000, 0, 0),
-	MX6_PAD_KEY_COL3__SPDIF_IN1		= IOMUX_PAD(0x05E0, 0x0210, 6, 0x0914, 2, 0),
-	MX6_PAD_KEY_COL3__PL301_PER1_HADR_5	= IOMUX_PAD(0x05E0, 0x0210, 7, 0x0000, 0, 0),
-	MX6_PAD_KEY_ROW3__OSC32K_32K_OUT	= IOMUX_PAD(0x05E4, 0x0214, 0, 0x0000, 0, 0),
-	MX6_PAD_KEY_ROW3__ASRC_ASRC_EXT_CLK	= IOMUX_PAD(0x05E4, 0x0214, 1, 0x07B0, 0, 0),
-	MX6_PAD_KEY_ROW3__HDMI_TX_DDC_SDA	= IOMUX_PAD(0x05E4, 0x0214, 2, 0x0894, 1, 0),
-	MX6_PAD_KEY_ROW3__KPP_ROW_3		= IOMUX_PAD(0x05E4, 0x0214, 3, 0x0000, 0, 0),
-	MX6_PAD_KEY_ROW3__I2C2_SDA		= IOMUX_PAD(0x05E4, 0x0214, 20, 0x08A4, 1, 0),
-	MX6_PAD_KEY_ROW3__GPIO_4_13		= IOMUX_PAD(0x05E4, 0x0214, 5, 0x0000, 0, 0),
-	MX6_PAD_KEY_ROW3__USDHC1_VSELECT	= IOMUX_PAD(0x05E4, 0x0214, 6, 0x0000, 0, 0),
-	MX6_PAD_KEY_ROW3__PL301_PER1_HADR_6	= IOMUX_PAD(0x05E4, 0x0214, 7, 0x0000, 0, 0),
-	MX6_PAD_KEY_COL4__CAN2_TXCAN		= IOMUX_PAD(0x05E8, 0x0218, 0, 0x0000, 0, 0),
-	MX6_PAD_KEY_COL4__IPU1_SISG_4		= IOMUX_PAD(0x05E8, 0x0218, 1, 0x0000, 0, 0),
-	MX6_PAD_KEY_COL4__USBOH3_USBOTG_OC	= IOMUX_PAD(0x05E8, 0x0218, 2, 0x0944, 1, 0),
-	MX6_PAD_KEY_COL4__KPP_COL_4		= IOMUX_PAD(0x05E8, 0x0218, 3, 0x0000, 0, 0),
-	MX6_PAD_KEY_COL4__UART5_CTS		= IOMUX_PAD(0x05E8, 0x0218, 4, 0x0000, 0, 0),
-	MX6_PAD_KEY_COL4__UART5_RTS		= IOMUX_PAD(0x05E8, 0x0218, 4, 0x093C, 0, 0),
-	MX6_PAD_KEY_COL4__GPIO_4_14		= IOMUX_PAD(0x05E8, 0x0218, 5, 0x0000, 0, 0),
-	MX6_PAD_KEY_COL4__MMDC_DEBUG_49	= IOMUX_PAD(0x05E8, 0x0218, 6, 0x0000, 0, 0),
-	MX6_PAD_KEY_COL4__PL301_PER1_HADDR_7	= IOMUX_PAD(0x05E8, 0x0218, 7, 0x0000, 0, 0),
-	MX6_PAD_KEY_ROW4__CAN2_RXCAN		= IOMUX_PAD(0x05EC, 0x021C, 0, 0x07E8, 0, 0),
-	MX6_PAD_KEY_ROW4__IPU1_SISG_5		= IOMUX_PAD(0x05EC, 0x021C, 1, 0x0000, 0, 0),
-	MX6_PAD_KEY_ROW4__USBOH3_USBOTG_PWR	= IOMUX_PAD(0x05EC, 0x021C, 2, 0x0000, 0, 0),
-	MX6_PAD_KEY_ROW4__KPP_ROW_4		= IOMUX_PAD(0x05EC, 0x021C, 3, 0x0000, 0, 0),
-	MX6_PAD_KEY_ROW4__UART5_CTS		= IOMUX_PAD(0x05EC, 0x021C, 4, 0x093C, 1, 0),
-	MX6_PAD_KEY_ROW4__GPIO_4_15		= IOMUX_PAD(0x05EC, 0x021C, 5, 0x0000, 0, 0),
-	MX6_PAD_KEY_ROW4__MMDC_DEBUG_50	= IOMUX_PAD(0x05EC, 0x021C, 6, 0x0000, 0, 0),
-	MX6_PAD_KEY_ROW4__PL301_PER1_HADR_8    = IOMUX_PAD(0x05EC, 0x021C, 7, 0x0000, 0, 0),
-	MX6_PAD_GPIO_0__CCM_CLKO		= IOMUX_PAD(0x05F0, 0x0220, 0, 0x0000, 0, 0),
-	MX6_PAD_GPIO_0__KPP_COL_5		= IOMUX_PAD(0x05F0, 0x0220, 2, 0x08E8, 0, 0),
-	MX6_PAD_GPIO_0__ASRC_ASRC_EXT_CLK	= IOMUX_PAD(0x05F0, 0x0220, 3, 0x07B0, 1, 0),
-	MX6_PAD_GPIO_0__EPIT1_EPITO		= IOMUX_PAD(0x05F0, 0x0220, 4, 0x0000, 0, 0),
-	MX6_PAD_GPIO_0__GPIO_1_0		= IOMUX_PAD(0x05F0, 0x0220, 5, 0x0000, 0, 0),
-	MX6_PAD_GPIO_0__USBOH3_USBH1_PWR	= IOMUX_PAD(0x05F0, 0x0220, 6, 0x0000, 0, 0),
-	MX6_PAD_GPIO_0__SNVS_HP_WRAP_SNVS_VIO5 = IOMUX_PAD(0x05F0, 0x0220, 7, 0x0000, 0, 0),
-	MX6_PAD_GPIO_1__ESAI1_SCKR		= IOMUX_PAD(0x05F4, 0x0224, 0, 0x086C, 1, 0),
-	MX6_PAD_GPIO_1__WDOG2_WDOG_B		= IOMUX_PAD(0x05F4, 0x0224, 1, 0x0000, 0, 0),
-	MX6_PAD_GPIO_1__KPP_ROW_5		= IOMUX_PAD(0x05F4, 0x0224, 2, 0x08F4, 0, 0),
-	MX6_PAD_GPIO_1__USB_OTG_ID		= IOMUX_PAD(0x05F4, 0x0224, 3, 0x0000, 0, 0),
-	MX6_PAD_GPIO_1__PWM2_PWMO		= IOMUX_PAD(0x05F4, 0x0224, 4, 0x0000, 0, 0),
-	MX6_PAD_GPIO_1__GPIO_1_1		= IOMUX_PAD(0x05F4, 0x0224, 5, 0x0000, 0, 0),
-	MX6_PAD_GPIO_1__USDHC1_CD		= IOMUX_PAD(0x05F4, 0x0224, 6, 0x0000, 0, 0),
-	MX6_PAD_GPIO_1__SRC_TESTER_ACK		= IOMUX_PAD(0x05F4, 0x0224, 7, 0x0000, 0, 0),
-	MX6_PAD_GPIO_9__ESAI1_FSR		= IOMUX_PAD(0x05F8, 0x0228, 0, 0x085C, 1, 0),
-	MX6_PAD_GPIO_9__WDOG1_WDOG_B		= IOMUX_PAD(0x05F8, 0x0228, 1, 0x0000, 0, 0),
-	MX6_PAD_GPIO_9__KPP_COL_6		= IOMUX_PAD(0x05F8, 0x0228, 2, 0x08EC, 0, 0),
-	MX6_PAD_GPIO_9__CCM_REF_EN_B		= IOMUX_PAD(0x05F8, 0x0228, 3, 0x0000, 0, 0),
-	MX6_PAD_GPIO_9__PWM1_PWMO		= IOMUX_PAD(0x05F8, 0x0228, 4, 0x0000, 0, 0),
-	MX6_PAD_GPIO_9__GPIO_1_9		= IOMUX_PAD(0x05F8, 0x0228, 5, 0x0000, 0, 0),
-	MX6_PAD_GPIO_9__USDHC1_WP		= IOMUX_PAD(0x05F8, 0x0228, 6, 0x094C, 1, 0),
-	MX6_PAD_GPIO_9__SRC_EARLY_RST		= IOMUX_PAD(0x05F8, 0x0228, 7, 0x0000, 0, 0),
-	MX6_PAD_GPIO_3__ESAI1_HCKR		= IOMUX_PAD(0x05FC, 0x022C, 0, 0x0864, 1, 0),
-	MX6_PAD_GPIO_3__OBSERVE_MUX_INT_OUT0	= IOMUX_PAD(0x05FC, 0x022C, 1, 0x0000, 0, 0),
-	MX6_PAD_GPIO_3__I2C3_SCL		= IOMUX_PAD(0x05FC, 0x022C, 18, 0x08A8, 1, 0),
-	MX6_PAD_GPIO_3__ANATOP_24M_OUT		= IOMUX_PAD(0x05FC, 0x022C, 3, 0x0000, 0, 0),
-	MX6_PAD_GPIO_3__CCM_CLKO2		= IOMUX_PAD(0x05FC, 0x022C, 4, 0x0000, 0, 0),
-	MX6_PAD_GPIO_3__GPIO_1_3		= IOMUX_PAD(0x05FC, 0x022C, 5, 0x0000, 0, 0),
-	MX6_PAD_GPIO_3__USBOH3_USBH1_OC	= IOMUX_PAD(0x05FC, 0x022C, 6, 0x0948, 1, 0),
-	MX6_PAD_GPIO_3__MLB_MLBCLK		= IOMUX_PAD(0x05FC, 0x022C, 7, 0x0900, 1, 0),
-	MX6_PAD_GPIO_6__ESAI1_SCKT		= IOMUX_PAD(0x0600, 0x0230, 0, 0x0870, 1, 0),
-	MX6_PAD_GPIO_6__OBSERVE_MUX_INT_OUT1	= IOMUX_PAD(0x0600, 0x0230, 1, 0x0000, 0, 0),
-	MX6_PAD_GPIO_6__I2C3_SDA		= IOMUX_PAD(0x0600, 0x0230, 18, 0x08AC, 1, 0),
-	MX6_PAD_GPIO_6__CCM_CCM_OUT_0		= IOMUX_PAD(0x0600, 0x0230, 3, 0x0000, 0, 0),
-	MX6_PAD_GPIO_6__CSU_CSU_INT_DEB	= IOMUX_PAD(0x0600, 0x0230, 4, 0x0000, 0, 0),
-	MX6_PAD_GPIO_6__GPIO_1_6		= IOMUX_PAD(0x0600, 0x0230, 5, 0x0000, 0, 0),
-	MX6_PAD_GPIO_6__USDHC2_LCTL		= IOMUX_PAD(0x0600, 0x0230, 6, 0x0000, 0, 0),
-	MX6_PAD_GPIO_6__MLB_MLBSIG		= IOMUX_PAD(0x0600, 0x0230, 7, 0x0908, 1, 0),
-	MX6_PAD_GPIO_2__ESAI1_FST		= IOMUX_PAD(0x0604, 0x0234, 0, 0x0860, 1, 0),
-	MX6_PAD_GPIO_2__OBSERVE_MUX_INT_OUT2	= IOMUX_PAD(0x0604, 0x0234, 1, 0x0000, 0, 0),
-	MX6_PAD_GPIO_2__KPP_ROW_6		= IOMUX_PAD(0x0604, 0x0234, 2, 0x08F8, 1, 0),
-	MX6_PAD_GPIO_2__CCM_CCM_OUT_1		= IOMUX_PAD(0x0604, 0x0234, 3, 0x0000, 0, 0),
-	MX6_PAD_GPIO_2__CSU_CSU_ALARM_AUT_0	= IOMUX_PAD(0x0604, 0x0234, 4, 0x0000, 0, 0),
-	MX6_PAD_GPIO_2__GPIO_1_2		= IOMUX_PAD(0x0604, 0x0234, 5, 0x0000, 0, 0),
-	MX6_PAD_GPIO_2__USDHC2_WP		= IOMUX_PAD(0x0604, 0x0234, 6, 0x0000, 0, 0),
-	MX6_PAD_GPIO_2__MLB_MLBDAT		= IOMUX_PAD(0x0604, 0x0234, 7, 0x0904, 1, 0),
-	MX6_PAD_GPIO_4__ESAI1_HCKT		= IOMUX_PAD(0x0608, 0x0238, 0, 0x0868, 1, 0),
-	MX6_PAD_GPIO_4__OBSERVE_MUX_INT_OUT3	= IOMUX_PAD(0x0608, 0x0238, 1, 0x0000, 0, 0),
-	MX6_PAD_GPIO_4__KPP_COL_7		= IOMUX_PAD(0x0608, 0x0238, 2, 0x08F0, 1, 0),
-	MX6_PAD_GPIO_4__CCM_CCM_OUT_2		= IOMUX_PAD(0x0608, 0x0238, 3, 0x0000, 0, 0),
-	MX6_PAD_GPIO_4__CSU_CSU_ALARM_AUT_1	= IOMUX_PAD(0x0608, 0x0238, 4, 0x0000, 0, 0),
-	MX6_PAD_GPIO_4__GPIO_1_4		= IOMUX_PAD(0x0608, 0x0238, 5, 0x0000, 0, 0),
-	MX6_PAD_GPIO_4__USDHC2_CD		= IOMUX_PAD(0x0608, 0x0238, 6, 0x0000, 0, 0),
-	MX6_PAD_GPIO_4__OCOTP_CRL_WRAR_FUSE_LA = IOMUX_PAD(0x0608, 0x0238, 7, 0x0000, 0, 0),
-	MX6_PAD_GPIO_5__ESAI1_TX2_RX3		= IOMUX_PAD(0x060C, 0x023C, 0, 0x087C, 1, 0),
-	MX6_PAD_GPIO_5__OBSERVE_MUX_INT_OUT4	= IOMUX_PAD(0x060C, 0x023C, 1, 0x0000, 0, 0),
-	MX6_PAD_GPIO_5__KPP_ROW_7		= IOMUX_PAD(0x060C, 0x023C, 2, 0x08FC, 1, 0),
-	MX6_PAD_GPIO_5__CCM_CLKO		= IOMUX_PAD(0x060C, 0x023C, 3, 0x0000, 0, 0),
-	MX6_PAD_GPIO_5__CSU_CSU_ALARM_AUT_2	= IOMUX_PAD(0x060C, 0x023C, 4, 0x0000, 0, 0),
-	MX6_PAD_GPIO_5__GPIO_1_5		= IOMUX_PAD(0x060C, 0x023C, 5, 0x0000, 0, 0),
-	MX6_PAD_GPIO_5__I2C3_SCL		= IOMUX_PAD(0x060C, 0x023C, 22, 0x08A8, 2, 0),
-	MX6_PAD_GPIO_5__CHEETAH_EVENTI		= IOMUX_PAD(0x060C, 0x023C, 7, 0x0000, 0, 0),
-	MX6_PAD_GPIO_7__ESAI1_TX4_RX1		= IOMUX_PAD(0x0610, 0x0240, 0, 0x0884, 1, 0),
-	MX6_PAD_GPIO_7__ECSPI5_RDY		= IOMUX_PAD(0x0610, 0x0240, 1, 0x0000, 0, 0),
-	MX6_PAD_GPIO_7__EPIT1_EPITO		= IOMUX_PAD(0x0610, 0x0240, 2, 0x0000, 0, 0),
-	MX6_PAD_GPIO_7__CAN1_TXCAN		= IOMUX_PAD(0x0610, 0x0240, 3, 0x0000, 0, 0),
-	MX6_PAD_GPIO_7__UART2_TXD		= IOMUX_PAD(0x0610, 0x0240, 4, 0x0000, 0, 0),
-	MX6_PAD_GPIO_7__UART2_TXD_RXD		= IOMUX_PAD(0x0610, 0x0240, 4, 0x0928, 2, 0),
-	MX6_PAD_GPIO_7__GPIO_1_7		= IOMUX_PAD(0x0610, 0x0240, 5, 0x0000, 0, 0),
-	MX6_PAD_GPIO_7__SPDIF_PLOCK		= IOMUX_PAD(0x0610, 0x0240, 6, 0x0000, 0, 0),
-	MX6_PAD_GPIO_7__USBOH3_OTGUSB_HST_MODE	= IOMUX_PAD(0x0610, 0x0240, 7, 0x0000, 0, 0),
-	MX6_PAD_GPIO_8__ESAI1_TX5_RX0		= IOMUX_PAD(0x0614, 0x0244, 0, 0x0888, 1, 0),
-	MX6_PAD_GPIO_8__ANATOP_ANATOP_32K_OUT	= IOMUX_PAD(0x0614, 0x0244, 1, 0x0000, 0, 0),
-	MX6_PAD_GPIO_8__EPIT2_EPITO		= IOMUX_PAD(0x0614, 0x0244, 2, 0x0000, 0, 0),
-	MX6_PAD_GPIO_8__CAN1_RXCAN		= IOMUX_PAD(0x0614, 0x0244, 3, 0x07E4, 1, 0),
-	MX6_PAD_GPIO_8__UART2_RXD		= IOMUX_PAD(0x0614, 0x0244, 4, 0x0928, 3, 0),
-	MX6_PAD_GPIO_8__GPIO_1_8		= IOMUX_PAD(0x0614, 0x0244, 5, 0x0000, 0, 0),
-	MX6_PAD_GPIO_8__SPDIF_SRCLK		= IOMUX_PAD(0x0614, 0x0244, 6, 0x0000, 0, 0),
-	MX6_PAD_GPIO_8__USBOH3_OTG_PWRCTL_WAK	= IOMUX_PAD(0x0614, 0x0244, 7, 0x0000, 0, 0),
-	MX6_PAD_GPIO_16__ESAI1_TX3_RX2		= IOMUX_PAD(0x0618, 0x0248, 0, 0x0880, 1, 0),
-	MX6_PAD_GPIO_16__ENET_1588_EVENT2_IN	= IOMUX_PAD(0x0618, 0x0248, 1, 0x0000, 0, 0),
-	MX6_PAD_GPIO_16__ENET_ETHERNET_REF_OUT = IOMUX_PAD(0x0618, 0x0248, 2, 0x083C, 1, 0),
-	MX6_PAD_GPIO_16__USDHC1_LCTL		= IOMUX_PAD(0x0618, 0x0248, 3, 0x0000, 0, 0),
-	MX6_PAD_GPIO_16__SPDIF_IN1		= IOMUX_PAD(0x0618, 0x0248, 4, 0x0914, 3, 0),
-	MX6_PAD_GPIO_16__GPIO_7_11		= IOMUX_PAD(0x0618, 0x0248, 5, 0x0000, 0, 0),
-	MX6_PAD_GPIO_16__I2C3_SDA		= IOMUX_PAD(0x0618, 0x0248, 22, 0x08AC, 2, 0),
-	MX6_PAD_GPIO_16__SJC_DE_B		= IOMUX_PAD(0x0618, 0x0248, 7, 0x0000, 0, 0),
-	MX6_PAD_GPIO_17__ESAI1_TX0		= IOMUX_PAD(0x061C, 0x024C, 0, 0x0874, 0, 0),
-	MX6_PAD_GPIO_17__ENET_1588_EVENT3_IN	= IOMUX_PAD(0x061C, 0x024C, 1, 0x0000, 0, 0),
-	MX6_PAD_GPIO_17__CCM_PMIC_RDY		= IOMUX_PAD(0x061C, 0x024C, 2, 0x07F0, 1, 0),
-	MX6_PAD_GPIO_17__SDMA_SDMA_EXT_EVENT_0	= IOMUX_PAD(0x061C, 0x024C, 3, 0x090C, 1, 0),
-	MX6_PAD_GPIO_17__SPDIF_OUT1		= IOMUX_PAD(0x061C, 0x024C, 4, 0x0000, 0, 0),
-	MX6_PAD_GPIO_17__GPIO_7_12		= IOMUX_PAD(0x061C, 0x024C, 5, 0x0000, 0, 0),
-	MX6_PAD_GPIO_17__SJC_JTAG_ACT		= IOMUX_PAD(0x061C, 0x024C, 7, 0x0000, 0, 0),
-	MX6_PAD_GPIO_18__ESAI1_TX1		= IOMUX_PAD(0x0620, 0x0250, 0, 0x0878, 0, 0),
-	MX6_PAD_GPIO_18__ENET_RX_CLK		= IOMUX_PAD(0x0620, 0x0250, 1, 0x0844, 1, 0),
-	MX6_PAD_GPIO_18__USDHC3_VSELECT	= IOMUX_PAD(0x0620, 0x0250, 2, 0x0000, 0, 0),
-	MX6_PAD_GPIO_18__SDMA_SDMA_EXT_EVENT_1 = IOMUX_PAD(0x0620, 0x0250, 3, 0x0910, 1, 0),
-	MX6_PAD_GPIO_18__ASRC_ASRC_EXT_CLK	= IOMUX_PAD(0x0620, 0x0250, 4, 0x07B0, 2, 0),
-	MX6_PAD_GPIO_18__GPIO_7_13		= IOMUX_PAD(0x0620, 0x0250, 5, 0x0000, 0, 0),
-	MX6_PAD_GPIO_18__SNVS_HP_WRA_SNVS_VIO5 = IOMUX_PAD(0x0620, 0x0250, 6, 0x0000, 0, 0),
-	MX6_PAD_GPIO_18__SRC_SYSTEM_RST	= IOMUX_PAD(0x0620, 0x0250, 7, 0x0000, 0, 0),
-	MX6_PAD_GPIO_19__KPP_COL_5		= IOMUX_PAD(0x0624, 0x0254, 0, 0x08E8, 1, 0),
-	MX6_PAD_GPIO_19__ENET_1588_EVENT0_OUT	= IOMUX_PAD(0x0624, 0x0254, 1, 0x0000, 0, 0),
-	MX6_PAD_GPIO_19__SPDIF_OUT1		= IOMUX_PAD(0x0624, 0x0254, 2, 0x0000, 0, 0),
-	MX6_PAD_GPIO_19__CCM_CLKO		= IOMUX_PAD(0x0624, 0x0254, 3, 0x0000, 0, 0),
-	MX6_PAD_GPIO_19__ECSPI1_RDY		= IOMUX_PAD(0x0624, 0x0254, 4, 0x0000, 0, 0),
-	MX6_PAD_GPIO_19__GPIO_4_5		= IOMUX_PAD(0x0624, 0x0254, 5, 0x0000, 0, 0),
-	MX6_PAD_GPIO_19__ENET_TX_ER		= IOMUX_PAD(0x0624, 0x0254, 6, 0x0000, 0, 0),
-	MX6_PAD_GPIO_19__SRC_INT_BOOT		= IOMUX_PAD(0x0624, 0x0254, 7, 0x0000, 0, 0),
-	MX6_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK	= IOMUX_PAD(0x0628, 0x0258, 0, 0x0000, 0, 0),
-	MX6_PAD_CSI0_PIXCLK__PCIE_CTRL_MUX_12	= IOMUX_PAD(0x0628, 0x0258, 2, 0x0000, 0, 0),
-	MX6_PAD_CSI0_PIXCLK__SDMA_DEBUG_PC_0	= IOMUX_PAD(0x0628, 0x0258, 4, 0x0000, 0, 0),
-	MX6_PAD_CSI0_PIXCLK__GPIO_5_18		= IOMUX_PAD(0x0628, 0x0258, 5, 0x0000, 0, 0),
-	MX6_PAD_CSI0_PIXCLK___MMDC_DEBUG_29	= IOMUX_PAD(0x0628, 0x0258, 6, 0x0000, 0, 0),
-	MX6_PAD_CSI0_PIXCLK__CHEETAH_EVENTO	= IOMUX_PAD(0x0628, 0x0258, 7, 0x0000, 0, 0),
-	MX6_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC	= IOMUX_PAD(0x062C, 0x025C, 0, 0x0000, 0, 0),
-	MX6_PAD_CSI0_MCLK__PCIE_CTRL_MUX_13	= IOMUX_PAD(0x062C, 0x025C, 2, 0x0000, 0, 0),
-	MX6_PAD_CSI0_MCLK__CCM_CLKO		= IOMUX_PAD(0x062C, 0x025C, 3, 0x0000, 0, 0),
-	MX6_PAD_CSI0_MCLK__SDMA_DEBUG_PC_1	= IOMUX_PAD(0x062C, 0x025C, 4, 0x0000, 0, 0),
-	MX6_PAD_CSI0_MCLK__GPIO_5_19		= IOMUX_PAD(0x062C, 0x025C, 5, 0x0000, 0, 0),
-	MX6_PAD_CSI0_MCLK__MMDC_MMDC_DEBUG_30	= IOMUX_PAD(0x062C, 0x025C, 6, 0x0000, 0, 0),
-	MX6_PAD_CSI0_MCLK__CHEETAH_TRCTL	= IOMUX_PAD(0x062C, 0x025C, 7, 0x0000, 0, 0),
-	MX6_PAD_CSI0_DATA_EN__IPU1_CSI0_DA_EN	= IOMUX_PAD(0x0630, 0x0260, 0, 0x0000, 0, 0),
-	MX6_PAD_CSI0_DATA_EN__WEIM_WEIM_D_0	= IOMUX_PAD(0x0630, 0x0260, 1, 0x0000, 0, 0),
-	MX6_PAD_CSI0_DATA_EN__PCIE_CTRL_MUX_14	= IOMUX_PAD(0x0630, 0x0260, 2, 0x0000, 0, 0),
-	MX6_PAD_CSI0_DATA_EN__SDMA_DEBUG_PC_2	= IOMUX_PAD(0x0630, 0x0260, 4, 0x0000, 0, 0),
-	MX6_PAD_CSI0_DATA_EN__GPIO_5_20	= IOMUX_PAD(0x0630, 0x0260, 5, 0x0000, 0, 0),
-	MX6_PAD_CSI0_DATA_EN__MMDC_DEBUG_31	= IOMUX_PAD(0x0630, 0x0260, 6, 0x0000, 0, 0),
-	MX6_PAD_CSI0_DATA_EN__CHEETAH_TRCLK	= IOMUX_PAD(0x0630, 0x0260, 7, 0x0000, 0, 0),
-	MX6_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC	= IOMUX_PAD(0x0634, 0x0264, 0, 0x0000, 0, 0),
-	MX6_PAD_CSI0_VSYNC__WEIM_WEIM_D_1	= IOMUX_PAD(0x0634, 0x0264, 1, 0x0000, 0, 0),
-	MX6_PAD_CSI0_VSYNC__PCIE_CTRL_MUX_15	= IOMUX_PAD(0x0634, 0x0264, 2, 0x0000, 0, 0),
-	MX6_PAD_CSI0_VSYNC__SDMA_DEBUG_PC_3	= IOMUX_PAD(0x0634, 0x0264, 4, 0x0000, 0, 0),
-	MX6_PAD_CSI0_VSYNC__GPIO_5_21		= IOMUX_PAD(0x0634, 0x0264, 5, 0x0000, 0, 0),
-	MX6_PAD_CSI0_VSYNC__MMDC_DEBUG_32	= IOMUX_PAD(0x0634, 0x0264, 6, 0x0000, 0, 0),
-	MX6_PAD_CSI0_VSYNC__CHEETAH_TRACE_0	= IOMUX_PAD(0x0634, 0x0264, 7, 0x0000, 0, 0),
-	MX6_PAD_CSI0_DAT4__IPU1_CSI0_D_4	= IOMUX_PAD(0x0638, 0x0268, 0, 0x0000, 0, 0),
-	MX6_PAD_CSI0_DAT4__WEIM_WEIM_D_2	= IOMUX_PAD(0x0638, 0x0268, 1, 0x0000, 0, 0),
-	MX6_PAD_CSI0_DAT4__ECSPI1_SCLK		= IOMUX_PAD(0x0638, 0x0268, 2, 0x07F4, 3, 0),
-	MX6_PAD_CSI0_DAT4__KPP_COL_5		= IOMUX_PAD(0x0638, 0x0268, 3, 0x08E8, 2, 0),
-	MX6_PAD_CSI0_DAT4__AUDMUX_AUD3_TXC	= IOMUX_PAD(0x0638, 0x0268, 4, 0x0000, 0, 0),
-	MX6_PAD_CSI0_DAT4__GPIO_5_22		= IOMUX_PAD(0x0638, 0x0268, 5, 0x0000, 0, 0),
-	MX6_PAD_CSI0_DAT4__MMDC_DEBUG_43	= IOMUX_PAD(0x0638, 0x0268, 6, 0x0000, 0, 0),
-	MX6_PAD_CSI0_DAT4__CHEETAH_TRACE_1	= IOMUX_PAD(0x0638, 0x0268, 7, 0x0000, 0, 0),
-	MX6_PAD_CSI0_DAT5__IPU1_CSI0_D_5	= IOMUX_PAD(0x063C, 0x026C, 0, 0x0000, 0, 0),
-	MX6_PAD_CSI0_DAT5__WEIM_WEIM_D_3	= IOMUX_PAD(0x063C, 0x026C, 1, 0x0000, 0, 0),
-	MX6_PAD_CSI0_DAT5__ECSPI1_MOSI		= IOMUX_PAD(0x063C, 0x026C, 2, 0x07FC, 3, 0),
-	MX6_PAD_CSI0_DAT5__KPP_ROW_5		= IOMUX_PAD(0x063C, 0x026C, 3, 0x08F4, 1, 0),
-	MX6_PAD_CSI0_DAT5__AUDMUX_AUD3_TXD	= IOMUX_PAD(0x063C, 0x026C, 4, 0x0000, 0, 0),
-	MX6_PAD_CSI0_DAT5__GPIO_5_23		= IOMUX_PAD(0x063C, 0x026C, 5, 0x0000, 0, 0),
-	MX6_PAD_CSI0_DAT5__MMDC_MMDC_DEBUG_44	= IOMUX_PAD(0x063C, 0x026C, 6, 0x0000, 0, 0),
-	MX6_PAD_CSI0_DAT5__CHEETAH_TRACE_2	= IOMUX_PAD(0x063C, 0x026C, 7, 0x0000, 0, 0),
-	MX6_PAD_CSI0_DAT6__IPU1_CSI0_D_6	= IOMUX_PAD(0x0640, 0x0270, 0, 0x0000, 0, 0),
-	MX6_PAD_CSI0_DAT6__WEIM_WEIM_D_4	= IOMUX_PAD(0x0640, 0x0270, 1, 0x0000, 0, 0),
-	MX6_PAD_CSI0_DAT6__ECSPI1_MISO		= IOMUX_PAD(0x0640, 0x0270, 2, 0x07F8, 3, 0),
-	MX6_PAD_CSI0_DAT6__KPP_COL_6		= IOMUX_PAD(0x0640, 0x0270, 3, 0x08EC, 1, 0),
-	MX6_PAD_CSI0_DAT6__AUDMUX_AUD3_TXFS	= IOMUX_PAD(0x0640, 0x0270, 4, 0x0000, 0, 0),
-	MX6_PAD_CSI0_DAT6__GPIO_5_24		= IOMUX_PAD(0x0640, 0x0270, 5, 0x0000, 0, 0),
-	MX6_PAD_CSI0_DAT6__MMDC_MMDC_DEBUG_45	= IOMUX_PAD(0x0640, 0x0270, 6, 0x0000, 0, 0),
-	MX6_PAD_CSI0_DAT6__CHEETAH_TRACE_3	= IOMUX_PAD(0x0640, 0x0270, 7, 0x0000, 0, 0),
-	MX6_PAD_CSI0_DAT7__IPU1_CSI0_D_7	= IOMUX_PAD(0x0644, 0x0274, 0, 0x0000, 0, 0),
-	MX6_PAD_CSI0_DAT7__WEIM_WEIM_D_5	= IOMUX_PAD(0x0644, 0x0274, 1, 0x0000, 0, 0),
-	MX6_PAD_CSI0_DAT7__ECSPI1_SS0		= IOMUX_PAD(0x0644, 0x0274, 2, 0x0800, 3, 0),
-	MX6_PAD_CSI0_DAT7__KPP_ROW_6		= IOMUX_PAD(0x0644, 0x0274, 3, 0x08F8, 2, 0),
-	MX6_PAD_CSI0_DAT7__AUDMUX_AUD3_RXD	= IOMUX_PAD(0x0644, 0x0274, 4, 0x0000, 0, 0),
-	MX6_PAD_CSI0_DAT7__GPIO_5_25		= IOMUX_PAD(0x0644, 0x0274, 5, 0x0000, 0, 0),
-	MX6_PAD_CSI0_DAT7__MMDC_MMDC_DEBUG_46	= IOMUX_PAD(0x0644, 0x0274, 6, 0x0000, 0, 0),
-	MX6_PAD_CSI0_DAT7__CHEETAH_TRACE_4	= IOMUX_PAD(0x0644, 0x0274, 7, 0x0000, 0, 0),
-	MX6_PAD_CSI0_DAT8__IPU1_CSI0_D_8	= IOMUX_PAD(0x0648, 0x0278, 0, 0x0000, 0, 0),
-	MX6_PAD_CSI0_DAT8__WEIM_WEIM_D_6	= IOMUX_PAD(0x0648, 0x0278, 1, 0x0000, 0, 0),
-	MX6_PAD_CSI0_DAT8__ECSPI2_SCLK		= IOMUX_PAD(0x0648, 0x0278, 2, 0x0810, 2, 0),
-	MX6_PAD_CSI0_DAT8__KPP_COL_7		= IOMUX_PAD(0x0648, 0x0278, 3, 0x08F0, 2, 0),
-	MX6_PAD_CSI0_DAT8__I2C1_SDA		= IOMUX_PAD(0x0648, 0x0278, 20, 0x089C, 1, 0),
-	MX6_PAD_CSI0_DAT8__GPIO_5_26		= IOMUX_PAD(0x0648, 0x0278, 5, 0x0000, 0, 0),
-	MX6_PAD_CSI0_DAT8__MMDC_MMDC_DEBUG_47	= IOMUX_PAD(0x0648, 0x0278, 6, 0x0000, 0, 0),
-	MX6_PAD_CSI0_DAT8__CHEETAH_TRACE_5	= IOMUX_PAD(0x0648, 0x0278, 7, 0x0000, 0, 0),
-	MX6_PAD_CSI0_DAT9__IPU1_CSI0_D_9	= IOMUX_PAD(0x064C, 0x027C, 0, 0x0000, 0, 0),
-	MX6_PAD_CSI0_DAT9__WEIM_WEIM_D_7	= IOMUX_PAD(0x064C, 0x027C, 1, 0x0000, 0, 0),
-	MX6_PAD_CSI0_DAT9__ECSPI2_MOSI		= IOMUX_PAD(0x064C, 0x027C, 2, 0x0818, 2, 0),
-	MX6_PAD_CSI0_DAT9__KPP_ROW_7		= IOMUX_PAD(0x064C, 0x027C, 3, 0x08FC, 2, 0),
-	MX6_PAD_CSI0_DAT9__I2C1_SCL		= IOMUX_PAD(0x064C, 0x027C, 20, 0x0898, 1, 0),
-	MX6_PAD_CSI0_DAT9__GPIO_5_27		= IOMUX_PAD(0x064C, 0x027C, 5, 0x0000, 0, 0),
-	MX6_PAD_CSI0_DAT9__MMDC_MMDC_DEBUG_48	= IOMUX_PAD(0x064C, 0x027C, 6, 0x0000, 0, 0),
-	MX6_PAD_CSI0_DAT9__CHEETAH_TRACE_6	= IOMUX_PAD(0x064C, 0x027C, 7, 0x0000, 0, 0),
-	MX6_PAD_CSI0_DAT10__IPU1_CSI0_D_10	= IOMUX_PAD(0x0650, 0x0280, 0, 0x0000, 0, 0),
-	MX6_PAD_CSI0_DAT10__AUDMUX_AUD3_RXC	= IOMUX_PAD(0x0650, 0x0280, 1, 0x0000, 0, 0),
-	MX6_PAD_CSI0_DAT10__ECSPI2_MISO	= IOMUX_PAD(0x0650, 0x0280, 2, 0x0814, 2, 0),
-	MX6_PAD_CSI0_DAT10__UART1_TXD		= IOMUX_PAD(0x0650, 0x0280, 3, 0x0000, 0, 0),
-	MX6_PAD_CSI0_DAT10__UART1_TXD_RXD	= IOMUX_PAD(0x0650, 0x0280, 3, 0x0920, 0, 0),
-	MX6_PAD_CSI0_DAT10__SDMA_DEBUG_PC_4	= IOMUX_PAD(0x0650, 0x0280, 4, 0x0000, 0, 0),
-	MX6_PAD_CSI0_DAT10__GPIO_5_28		= IOMUX_PAD(0x0650, 0x0280, 5, 0x0000, 0, 0),
-	MX6_PAD_CSI0_DAT10__MMDC_MMDC_DEBUG_33	= IOMUX_PAD(0x0650, 0x0280, 6, 0x0000, 0, 0),
-	MX6_PAD_CSI0_DAT10__CHEETAH_TRACE_7	= IOMUX_PAD(0x0650, 0x0280, 7, 0x0000, 0, 0),
-	MX6_PAD_CSI0_DAT11__IPU1_CSI0_D_11	= IOMUX_PAD(0x0654, 0x0284, 0, 0x0000, 0, 0),
-	MX6_PAD_CSI0_DAT11__AUDMUX_AUD3_RXFS	= IOMUX_PAD(0x0654, 0x0284, 1, 0x0000, 0, 0),
-	MX6_PAD_CSI0_DAT11__ECSPI2_SS0		= IOMUX_PAD(0x0654, 0x0284, 2, 0x081C, 2, 0),
-	MX6_PAD_CSI0_DAT11__UART1_RXD		= IOMUX_PAD(0x0654, 0x0284, 3, 0x0920, 1, 0),
-	MX6_PAD_CSI0_DAT11__SDMA_DEBUG_PC_5	= IOMUX_PAD(0x0654, 0x0284, 4, 0x0000, 0, 0),
-	MX6_PAD_CSI0_DAT11__GPIO_5_29		= IOMUX_PAD(0x0654, 0x0284, 5, 0x0000, 0, 0),
-	MX6_PAD_CSI0_DAT11__MMDC_MMDC_DEBUG_34	= IOMUX_PAD(0x0654, 0x0284, 6, 0x0000, 0, 0),
-	MX6_PAD_CSI0_DAT11__CHEETAH_TRACE_8	= IOMUX_PAD(0x0654, 0x0284, 7, 0x0000, 0, 0),
-	MX6_PAD_CSI0_DAT12__IPU1_CSI0_D_12	= IOMUX_PAD(0x0658, 0x0288, 0, 0x0000, 0, 0),
-	MX6_PAD_CSI0_DAT12__WEIM_WEIM_D_8	= IOMUX_PAD(0x0658, 0x0288, 1, 0x0000, 0, 0),
-	MX6_PAD_CSI0_DAT12__PCIE_CTRL_MUX_16	= IOMUX_PAD(0x0658, 0x0288, 2, 0x0000, 0, 0),
-	MX6_PAD_CSI0_DAT12__UART4_TXD		= IOMUX_PAD(0x0658, 0x0288, 3, 0x0000, 0, 0),
-	MX6_PAD_CSI0_DAT12__UART4_TXD_RXD	= IOMUX_PAD(0x0658, 0x0288, 3, 0x0938, 2, 0),
-	MX6_PAD_CSI0_DAT12__SDMA_DEBUG_PC_6	= IOMUX_PAD(0x0658, 0x0288, 4, 0x0000, 0, 0),
-	MX6_PAD_CSI0_DAT12__GPIO_5_30		= IOMUX_PAD(0x0658, 0x0288, 5, 0x0000, 0, 0),
-	MX6_PAD_CSI0_DAT12__MMDC_MMDC_DEBUG_35	= IOMUX_PAD(0x0658, 0x0288, 6, 0x0000, 0, 0),
-	MX6_PAD_CSI0_DAT12__CHEETAH_TRACE_9	= IOMUX_PAD(0x0658, 0x0288, 7, 0x0000, 0, 0),
-	MX6_PAD_CSI0_DAT13__IPU1_CSI0_D_13	= IOMUX_PAD(0x065C, 0x028C, 0, 0x0000, 0, 0),
-	MX6_PAD_CSI0_DAT13__WEIM_WEIM_D_9	= IOMUX_PAD(0x065C, 0x028C, 1, 0x0000, 0, 0),
-	MX6_PAD_CSI0_DAT13__PCIE_CTRL_MUX_17	= IOMUX_PAD(0x065C, 0x028C, 2, 0x0000, 0, 0),
-	MX6_PAD_CSI0_DAT13__UART4_RXD		= IOMUX_PAD(0x065C, 0x028C, 3, 0x0938, 3, 0),
-	MX6_PAD_CSI0_DAT13__SDMA_DEBUG_PC_7	= IOMUX_PAD(0x065C, 0x028C, 4, 0x0000, 0, 0),
-	MX6_PAD_CSI0_DAT13__GPIO_5_31		= IOMUX_PAD(0x065C, 0x028C, 5, 0x0000, 0, 0),
-	MX6_PAD_CSI0_DAT13__MMDC_MMDC_DEBUG_36	= IOMUX_PAD(0x065C, 0x028C, 6, 0x0000, 0, 0),
-	MX6_PAD_CSI0_DAT13__CHEETAH_TRACE_10	= IOMUX_PAD(0x065C, 0x028C, 7, 0x0000, 0, 0),
-	MX6_PAD_CSI0_DAT14__IPU1_CSI0_D_14	= IOMUX_PAD(0x0660, 0x0290, 0, 0x0000, 0, 0),
-	MX6_PAD_CSI0_DAT14__WEIM_WEIM_D_10	= IOMUX_PAD(0x0660, 0x0290, 1, 0x0000, 0, 0),
-	MX6_PAD_CSI0_DAT14__PCIE_CTRL_MUX_18	= IOMUX_PAD(0x0660, 0x0290, 2, 0x0000, 0, 0),
-	MX6_PAD_CSI0_DAT14__UART5_TXD		= IOMUX_PAD(0x0660, 0x0290, 3, 0x0000, 0, 0),
-	MX6_PAD_CSI0_DAT14__UART5_TXD_RXD	= IOMUX_PAD(0x0660, 0x0290, 3, 0x0940, 2, 0),
-	MX6_PAD_CSI0_DAT14__SDMA_DEBUG_PC_8	= IOMUX_PAD(0x0660, 0x0290, 4, 0x0000, 0, 0),
-	MX6_PAD_CSI0_DAT14__GPIO_6_0		= IOMUX_PAD(0x0660, 0x0290, 5, 0x0000, 0, 0),
-	MX6_PAD_CSI0_DAT14__MMDC_MMDC_DEBUG_37	= IOMUX_PAD(0x0660, 0x0290, 6, 0x0000, 0, 0),
-	MX6_PAD_CSI0_DAT14__CHEETAH_TRACE_11	= IOMUX_PAD(0x0660, 0x0290, 7, 0x0000, 0, 0),
-	MX6_PAD_CSI0_DAT15__IPU1_CSI0_D_15	= IOMUX_PAD(0x0664, 0x0294, 0, 0x0000, 0, 0),
-	MX6_PAD_CSI0_DAT15__WEIM_WEIM_D_11	= IOMUX_PAD(0x0664, 0x0294, 1, 0x0000, 0, 0),
-	MX6_PAD_CSI0_DAT15__PCIE_CTRL_MUX_19	= IOMUX_PAD(0x0664, 0x0294, 2, 0x0000, 0, 0),
-	MX6_PAD_CSI0_DAT15__UART5_RXD		= IOMUX_PAD(0x0664, 0x0294, 3, 0x0940, 3, 0),
-	MX6_PAD_CSI0_DAT15__SDMA_DEBUG_PC_9	= IOMUX_PAD(0x0664, 0x0294, 4, 0x0000, 0, 0),
-	MX6_PAD_CSI0_DAT15__GPIO_6_1		= IOMUX_PAD(0x0664, 0x0294, 5, 0x0000, 0, 0),
-	MX6_PAD_CSI0_DAT15__MMDC_MMDC_DEBUG_38	= IOMUX_PAD(0x0664, 0x0294, 6, 0x0000, 0, 0),
-	MX6_PAD_CSI0_DAT15__CHEETAH_TRACE_12	= IOMUX_PAD(0x0664, 0x0294, 7, 0x0000, 0, 0),
-	MX6_PAD_CSI0_DAT16__IPU1_CSI0_D_16	= IOMUX_PAD(0x0668, 0x0298, 0, 0x0000, 0, 0),
-	MX6_PAD_CSI0_DAT16__WEIM_WEIM_D_12	= IOMUX_PAD(0x0668, 0x0298, 1, 0x0000, 0, 0),
-	MX6_PAD_CSI0_DAT16__PCIE_CTRL_MUX_20	= IOMUX_PAD(0x0668, 0x0298, 2, 0x0000, 0, 0),
-	MX6_PAD_CSI0_DAT16__UART4_CTS		= IOMUX_PAD(0x0668, 0x0298, 3, 0x0000, 0, 0),
-	MX6_PAD_CSI0_DAT16__UART4_RTS		= IOMUX_PAD(0x0668, 0x0298, 3, 0x0934, 0, 0),
-	MX6_PAD_CSI0_DAT16__SDMA_DEBUG_PC_10	= IOMUX_PAD(0x0668, 0x0298, 4, 0x0000, 0, 0),
-	MX6_PAD_CSI0_DAT16__GPIO_6_2		= IOMUX_PAD(0x0668, 0x0298, 5, 0x0000, 0, 0),
-	MX6_PAD_CSI0_DAT16__MMDC_MMDC_DEBUG_39	= IOMUX_PAD(0x0668, 0x0298, 6, 0x0000, 0, 0),
-	MX6_PAD_CSI0_DAT16__CHEETAH_TRACE_13	= IOMUX_PAD(0x0668, 0x0298, 7, 0x0000, 0, 0),
-	MX6_PAD_CSI0_DAT17__IPU1_CSI0_D_17	= IOMUX_PAD(0x066C, 0x029C, 0, 0x0000, 0, 0),
-	MX6_PAD_CSI0_DAT17__WEIM_WEIM_D_13	= IOMUX_PAD(0x066C, 0x029C, 1, 0x0000, 0, 0),
-	MX6_PAD_CSI0_DAT17__PCIE_CTRL_MUX_21	= IOMUX_PAD(0x066C, 0x029C, 2, 0x0000, 0, 0),
-	MX6_PAD_CSI0_DAT17__UART4_CTS		= IOMUX_PAD(0x066C, 0x029C, 3, 0x0934, 1, 0),
-	MX6_PAD_CSI0_DAT17__SDMA_DEBUG_PC_11	= IOMUX_PAD(0x066C, 0x029C, 4, 0x0000, 0, 0),
-	MX6_PAD_CSI0_DAT17__GPIO_6_3		= IOMUX_PAD(0x066C, 0x029C, 5, 0x0000, 0, 0),
-	MX6_PAD_CSI0_DAT17__MMDC_MMDC_DEBUG_40	= IOMUX_PAD(0x066C, 0x029C, 6, 0x0000, 0, 0),
-	MX6_PAD_CSI0_DAT17__CHEETAH_TRACE_14	= IOMUX_PAD(0x066C, 0x029C, 7, 0x0000, 0, 0),
-	MX6_PAD_CSI0_DAT18__IPU1_CSI0_D_18	= IOMUX_PAD(0x0670, 0x02A0, 0, 0x0000, 0, 0),
-	MX6_PAD_CSI0_DAT18__WEIM_WEIM_D_14	= IOMUX_PAD(0x0670, 0x02A0, 1, 0x0000, 0, 0),
-	MX6_PAD_CSI0_DAT18__PCIE_CTRL_MUX_22	= IOMUX_PAD(0x0670, 0x02A0, 2, 0x0000, 0, 0),
-	MX6_PAD_CSI0_DAT18__UART5_CTS		= IOMUX_PAD(0x0670, 0x02A0, 3, 0x0000, 0, 0),
-	MX6_PAD_CSI0_DAT18__UART5_RTS		= IOMUX_PAD(0x0670, 0x02A0, 3, 0x093C, 2, 0),
-	MX6_PAD_CSI0_DAT18__SDMA_DEBUG_PC_12	= IOMUX_PAD(0x0670, 0x02A0, 4, 0x0000, 0, 0),
-	MX6_PAD_CSI0_DAT18__GPIO_6_4		= IOMUX_PAD(0x0670, 0x02A0, 5, 0x0000, 0, 0),
-	MX6_PAD_CSI0_DAT18__MMDC_MMDC_DEBUG_41	= IOMUX_PAD(0x0670, 0x02A0, 6, 0x0000, 0, 0),
-	MX6_PAD_CSI0_DAT18__CHEETAH_TRACE_15	= IOMUX_PAD(0x0670, 0x02A0, 7, 0x0000, 0, 0),
-	MX6_PAD_CSI0_DAT19__IPU1_CSI0_D_19	= IOMUX_PAD(0x0674, 0x02A4, 0, 0x0000, 0, 0),
-	MX6_PAD_CSI0_DAT19__WEIM_WEIM_D_15	= IOMUX_PAD(0x0674, 0x02A4, 1, 0x0000, 0, 0),
-	MX6_PAD_CSI0_DAT19__PCIE_CTRL_MUX_23	= IOMUX_PAD(0x0674, 0x02A4, 2, 0x0000, 0, 0),
-	MX6_PAD_CSI0_DAT19__UART5_CTS		= IOMUX_PAD(0x0674, 0x02A4, 3, 0x093C, 3, 0),
-	MX6_PAD_CSI0_DAT19__SDMA_DEBUG_PC_13	= IOMUX_PAD(0x0674, 0x02A4, 4, 0x0000, 0, 0),
-	MX6_PAD_CSI0_DAT19__GPIO_6_5		= IOMUX_PAD(0x0674, 0x02A4, 5, 0x0000, 0, 0),
-	MX6_PAD_CSI0_DAT19__MMDC_MMDC_DEBUG_42	= IOMUX_PAD(0x0674, 0x02A4, 6, 0x0000, 0, 0),
-	MX6_PAD_CSI0_DAT19__ANATOP_TESTO_9	= IOMUX_PAD(0x0674, 0x02A4, 7, 0x0000, 0, 0),
-	MX6_PAD_JTAG_TMS__SJC_TMS		= IOMUX_PAD(0x0678, NO_MUX_I, 0, 0x0000, 0, 0),
-	MX6_PAD_JTAG_MOD__SJC_MOD		= IOMUX_PAD(0x067C, NO_MUX_I, 0, 0x0000, 0, 0),
-	MX6_PAD_JTAG_TRSTB__SJC_TRSTB		= IOMUX_PAD(0x0680, NO_MUX_I, 0, 0x0000, 0, 0),
-	MX6_PAD_JTAG_TDI__SJC_TDI		= IOMUX_PAD(0x0684, NO_MUX_I, 0, 0x0000, 0, 0),
-	MX6_PAD_JTAG_TCK__SJC_TCK		= IOMUX_PAD(0x0688, NO_MUX_I, 0, 0x0000, 0, 0),
-	MX6_PAD_JTAG_TDO__SJC_TDO		= IOMUX_PAD(0x068C, NO_MUX_I, 0, 0x0000, 0, 0),
-	MX6_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3	= IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
-	MX6_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2	= IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
-	MX6_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK	= IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
-	MX6_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1	= IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
-	MX6_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0	= IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
-	MX6_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3	= IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
-	MX6_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK	= IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
-	MX6_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2	= IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
-	MX6_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1	= IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
-	MX6_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0	= IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
-	MX6_PAD_TAMPER__SNVS_LP_WRAP_SNVS_TD1	= IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
-	MX6_PAD_PMIC_ON_REQ__SNVS_LPWRAP_WKALM = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
-	MX6_PAD_PMIC_STBY_REQ__CCM_PMIC_STBYRQ = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
-	MX6_PAD_POR_B__SRC_POR_B		= IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
-	MX6_PAD_BOOT_MODE1__SRC_BOOT_MODE_1	= IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
-	MX6_PAD_RESET_IN_B__SRC_RESET_B	= IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
-	MX6_PAD_BOOT_MODE0__SRC_BOOT_MODE_0	= IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
-	MX6_PAD_TEST_MODE__TCU_TEST_MODE	= IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
-	MX6_PAD_SD3_DAT7__USDHC3_DAT7		= IOMUX_PAD(0x0690, 0x02A8, 0, 0x0000, 0, 0),
-	MX6_PAD_SD3_DAT7__UART1_TXD		= IOMUX_PAD(0x0690, 0x02A8, 1, 0x0000, 0, 0),
-	MX6_PAD_SD3_DAT7__UART1_TXD_RXD	= IOMUX_PAD(0x0690, 0x02A8, 1, 0x0920, 2, 0),
-	MX6_PAD_SD3_DAT7__PCIE_CTRL_MUX_24	= IOMUX_PAD(0x0690, 0x02A8, 2, 0x0000, 0, 0),
-	MX6_PAD_SD3_DAT7__USBOH3_UH3_DFD_OUT_0	= IOMUX_PAD(0x0690, 0x02A8, 3, 0x0000, 0, 0),
-	MX6_PAD_SD3_DAT7__USBOH3_UH2_DFD_OUT_0	= IOMUX_PAD(0x0690, 0x02A8, 4, 0x0000, 0, 0),
-	MX6_PAD_SD3_DAT7__GPIO_6_17		= IOMUX_PAD(0x0690, 0x02A8, 5, 0x0000, 0, 0),
-	MX6_PAD_SD3_DAT7__MIPI_CORE_DPHY_IN_12	= IOMUX_PAD(0x0690, 0x02A8, 6, 0x0000, 0, 0),
-	MX6_PAD_SD3_DAT7__USBPHY2_CLK20DIV	= IOMUX_PAD(0x0690, 0x02A8, 7, 0x0000, 0, 0),
-	MX6_PAD_SD3_DAT6__USDHC3_DAT6		= IOMUX_PAD(0x0694, 0x02AC, 0, 0x0000, 0, 0),
-	MX6_PAD_SD3_DAT6__UART1_RXD		= IOMUX_PAD(0x0694, 0x02AC, 1, 0x0920, 3, 0),
-	MX6_PAD_SD3_DAT6__PCIE_CTRL_MUX_25	= IOMUX_PAD(0x0694, 0x02AC, 2, 0x0000, 0, 0),
-	MX6_PAD_SD3_DAT6__USBOH3_UH3_DFD_OUT_1 = IOMUX_PAD(0x0694, 0x02AC, 3, 0x0000, 0, 0),
-	MX6_PAD_SD3_DAT6__USBOH3_UH2_DFD_OUT_1 = IOMUX_PAD(0x0694, 0x02AC, 4, 0x0000, 0, 0),
-	MX6_PAD_SD3_DAT6__GPIO_6_18		= IOMUX_PAD(0x0694, 0x02AC, 5, 0x0000, 0, 0),
-	MX6_PAD_SD3_DAT6__MIPI_CORE_DPHY_IN_13	= IOMUX_PAD(0x0694, 0x02AC, 6, 0x0000, 0, 0),
-	MX6_PAD_SD3_DAT6__ANATOP_TESTO_10	= IOMUX_PAD(0x0694, 0x02AC, 7, 0x0000, 0, 0),
-	MX6_PAD_SD3_DAT5__USDHC3_DAT5		= IOMUX_PAD(0x0698, 0x02B0, 0, 0x0000, 0, 0),
-	MX6_PAD_SD3_DAT5__UART2_TXD		= IOMUX_PAD(0x0698, 0x02B0, 1, 0x0000, 0, 0),
-	MX6_PAD_SD3_DAT5__UART2_TXD_RXD	= IOMUX_PAD(0x0698, 0x02B0, 1, 0x0928, 4, 0),
-	MX6_PAD_SD3_DAT5__PCIE_CTRL_MUX_26	= IOMUX_PAD(0x0698, 0x02B0, 2, 0x0000, 0, 0),
-	MX6_PAD_SD3_DAT5__USBOH3_UH3_DFD_OUT_2	= IOMUX_PAD(0x0698, 0x02B0, 3, 0x0000, 0, 0),
-	MX6_PAD_SD3_DAT5__USBOH3_UH2_DFD_OUT_2	= IOMUX_PAD(0x0698, 0x02B0, 4, 0x0000, 0, 0),
-	MX6_PAD_SD3_DAT5__GPIO_7_0		= IOMUX_PAD(0x0698, 0x02B0, 5, 0x0000, 0, 0),
-	MX6_PAD_SD3_DAT5__MIPI_CORE_DPHY_IN_14	= IOMUX_PAD(0x0698, 0x02B0, 6, 0x0000, 0, 0),
-	MX6_PAD_SD3_DAT5__ANATOP_TESTO_11	= IOMUX_PAD(0x0698, 0x02B0, 7, 0x0000, 0, 0),
-	MX6_PAD_SD3_DAT4__USDHC3_DAT4		= IOMUX_PAD(0x069C, 0x02B4, 0, 0x0000, 0, 0),
-	MX6_PAD_SD3_DAT4__UART2_RXD		= IOMUX_PAD(0x069C, 0x02B4, 1, 0x0928, 5, 0),
-	MX6_PAD_SD3_DAT4__PCIE_CTRL_MUX_27	= IOMUX_PAD(0x069C, 0x02B4, 2, 0x0000, 0, 0),
-	MX6_PAD_SD3_DAT4__USBOH3_UH3_DFD_OUT_3	= IOMUX_PAD(0x069C, 0x02B4, 3, 0x0000, 0, 0),
-	MX6_PAD_SD3_DAT4__USBOH3_UH2_DFD_OUT_3	= IOMUX_PAD(0x069C, 0x02B4, 4, 0x0000, 0, 0),
-	MX6_PAD_SD3_DAT4__GPIO_7_1		= IOMUX_PAD(0x069C, 0x02B4, 5, 0x0000, 0, 0),
-	MX6_PAD_SD3_DAT4__MIPI_CORE_DPHY_IN_15	= IOMUX_PAD(0x069C, 0x02B4, 6, 0x0000, 0, 0),
-	MX6_PAD_SD3_DAT4__ANATOP_TESTO_12	= IOMUX_PAD(0x069C, 0x02B4, 7, 0x0000, 0, 0),
-	MX6_PAD_SD3_CMD__USDHC3_CMD		= IOMUX_PAD(0x06A0, 0x02B8, 16, 0x0000, 0, 0),
-	MX6_PAD_SD3_CMD__UART2_CTS		= IOMUX_PAD(0x06A0, 0x02B8, 1, 0x0924, 2, 0),
-	MX6_PAD_SD3_CMD__CAN1_TXCAN		= IOMUX_PAD(0x06A0, 0x02B8, 2, 0x0000, 0, 0),
-	MX6_PAD_SD3_CMD__USBOH3_UH3_DFD_OUT_4	= IOMUX_PAD(0x06A0, 0x02B8, 3, 0x0000, 0, 0),
-	MX6_PAD_SD3_CMD__USBOH3_UH2_DFD_OUT_4	= IOMUX_PAD(0x06A0, 0x02B8, 4, 0x0000, 0, 0),
-	MX6_PAD_SD3_CMD__GPIO_7_2		= IOMUX_PAD(0x06A0, 0x02B8, 5, 0x0000, 0, 0),
-	MX6_PAD_SD3_CMD__MIPI_CORE_DPHY_IN_16	= IOMUX_PAD(0x06A0, 0x02B8, 6, 0x0000, 0, 0),
-	MX6_PAD_SD3_CMD__ANATOP_TESTO_13	= IOMUX_PAD(0x06A0, 0x02B8, 7, 0x0000, 0, 0),
-	MX6_PAD_SD3_CLK__USDHC3_CLK		= IOMUX_PAD(0x06A4, 0x02BC, 0, 0x0000, 0, 0),
-	MX6_PAD_SD3_CLK__UART2_CTS		= IOMUX_PAD(0x06A4, 0x02BC, 1, 0x0000, 0, 0),
-	MX6_PAD_SD3_CLK__UART2_RTS		= IOMUX_PAD(0x06A4, 0x02BC, 1, 0x0924, 3, 0),
-	MX6_PAD_SD3_CLK__CAN1_RXCAN		= IOMUX_PAD(0x06A4, 0x02BC, 2, 0x07E4, 2, 0),
-	MX6_PAD_SD3_CLK__USBOH3_UH3_DFD_OUT_5	= IOMUX_PAD(0x06A4, 0x02BC, 3, 0x0000, 0, 0),
-	MX6_PAD_SD3_CLK__USBOH3_UH2_DFD_OUT_5	= IOMUX_PAD(0x06A4, 0x02BC, 4, 0x0000, 0, 0),
-	MX6_PAD_SD3_CLK__GPIO_7_3		= IOMUX_PAD(0x06A4, 0x02BC, 5, 0x0000, 0, 0),
-	MX6_PAD_SD3_CLK__MIPI_CORE_DPHY_IN_17	= IOMUX_PAD(0x06A4, 0x02BC, 6, 0x0000, 0, 0),
-	MX6_PAD_SD3_CLK__ANATOP_TESTO_14	= IOMUX_PAD(0x06A4, 0x02BC, 7, 0x0000, 0, 0),
-	MX6_PAD_SD3_DAT0__USDHC3_DAT0		= IOMUX_PAD(0x06A8, 0x02C0, 0, 0x0000, 0, 0),
-	MX6_PAD_SD3_DAT0__UART1_CTS		= IOMUX_PAD(0x06A8, 0x02C0, 1, 0x091C, 2, 0),
-	MX6_PAD_SD3_DAT0__CAN2_TXCAN		= IOMUX_PAD(0x06A8, 0x02C0, 2, 0x0000, 0, 0),
-	MX6_PAD_SD3_DAT0__USBOH3_UH3_DFD_OUT_6	= IOMUX_PAD(0x06A8, 0x02C0, 3, 0x0000, 0, 0),
-	MX6_PAD_SD3_DAT0__USBOH3_UH2_DFD_OUT_6	= IOMUX_PAD(0x06A8, 0x02C0, 4, 0x0000, 0, 0),
-	MX6_PAD_SD3_DAT0__GPIO_7_4		= IOMUX_PAD(0x06A8, 0x02C0, 5, 0x0000, 0, 0),
-	MX6_PAD_SD3_DAT0__MIPI_CORE_DPHY_IN_18	= IOMUX_PAD(0x06A8, 0x02C0, 6, 0x0000, 0, 0),
-	MX6_PAD_SD3_DAT0__ANATOP_TESTO_15	= IOMUX_PAD(0x06A8, 0x02C0, 7, 0x0000, 0, 0),
-	MX6_PAD_SD3_DAT1__USDHC3_DAT1		= IOMUX_PAD(0x06AC, 0x02C4, 0, 0x0000, 0, 0),
-	MX6_PAD_SD3_DAT1__UART1_CTS		= IOMUX_PAD(0x06AC, 0x02C4, 1, 0x0000, 0, 0),
-	MX6_PAD_SD3_DAT1__UART1_RTS		= IOMUX_PAD(0x06AC, 0x02C4, 1, 0x091C, 3, 0),
-	MX6_PAD_SD3_DAT1__CAN2_RXCAN		= IOMUX_PAD(0x06AC, 0x02C4, 2, 0x07E8, 1, 0),
-	MX6_PAD_SD3_DAT1__USBOH3_UH3_DFD_OUT_7	= IOMUX_PAD(0x06AC, 0x02C4, 3, 0x0000, 0, 0),
-	MX6_PAD_SD3_DAT1__USBOH3_UH2_DFD_OUT_7	= IOMUX_PAD(0x06AC, 0x02C4, 4, 0x0000, 0, 0),
-	MX6_PAD_SD3_DAT1__GPIO_7_5		= IOMUX_PAD(0x06AC, 0x02C4, 5, 0x0000, 0, 0),
-	MX6_PAD_SD3_DAT1__MIPI_CORE_DPHY_IN_19 = IOMUX_PAD(0x06AC, 0x02C4, 6, 0x0000, 0, 0),
-	MX6_PAD_SD3_DAT1__ANATOP_TESTI_0	= IOMUX_PAD(0x06AC, 0x02C4, 7, 0x0000, 0, 0),
-	MX6_PAD_SD3_DAT2__USDHC3_DAT2		= IOMUX_PAD(0x06B0, 0x02C8, 0, 0x0000, 0, 0),
-	MX6_PAD_SD3_DAT2__PCIE_CTRL_MUX_28	= IOMUX_PAD(0x06B0, 0x02C8, 2, 0x0000, 0, 0),
-	MX6_PAD_SD3_DAT2__USBOH3_UH3_DFD_OUT_8	= IOMUX_PAD(0x06B0, 0x02C8, 3, 0x0000, 0, 0),
-	MX6_PAD_SD3_DAT2__USBOH3_UH2_DFD_OUT_8	= IOMUX_PAD(0x06B0, 0x02C8, 4, 0x0000, 0, 0),
-	MX6_PAD_SD3_DAT2__GPIO_7_6		= IOMUX_PAD(0x06B0, 0x02C8, 5, 0x0000, 0, 0),
-	MX6_PAD_SD3_DAT2__MIPI_CORE_DPHY_IN_20	= IOMUX_PAD(0x06B0, 0x02C8, 6, 0x0000, 0, 0),
-	MX6_PAD_SD3_DAT2__ANATOP_TESTI_1	= IOMUX_PAD(0x06B0, 0x02C8, 7, 0x0000, 0, 0),
-	MX6_PAD_SD3_DAT3__USDHC3_DAT3		= IOMUX_PAD(0x06B4, 0x02CC, 0, 0x0000, 0, 0),
-	MX6_PAD_SD3_DAT3__UART3_CTS		= IOMUX_PAD(0x06B4, 0x02CC, 1, 0x092C, 4, 0),
-	MX6_PAD_SD3_DAT3__PCIE_CTRL_MUX_29	= IOMUX_PAD(0x06B4, 0x02CC, 2, 0x0000, 0, 0),
-	MX6_PAD_SD3_DAT3__USBOH3_UH3_DFD_OUT_9	= IOMUX_PAD(0x06B4, 0x02CC, 3, 0x0000, 0, 0),
-	MX6_PAD_SD3_DAT3__USBOH3_UH2_DFD_OUT_9	= IOMUX_PAD(0x06B4, 0x02CC, 4, 0x0000, 0, 0),
-	MX6_PAD_SD3_DAT3__GPIO_7_7		= IOMUX_PAD(0x06B4, 0x02CC, 5, 0x0000, 0, 0),
-	MX6_PAD_SD3_DAT3__MIPI_CORE_DPHY_IN_21	= IOMUX_PAD(0x06B4, 0x02CC, 6, 0x0000, 0, 0),
-	MX6_PAD_SD3_DAT3__ANATOP_TESTI_2	= IOMUX_PAD(0x06B4, 0x02CC, 7, 0x0000, 0, 0),
-	MX6_PAD_SD3_RST__USDHC3_RST		= IOMUX_PAD(0x06B8, 0x02D0, 0, 0x0000, 0, 0),
-	MX6_PAD_SD3_RST__UART3_CTS		= IOMUX_PAD(0x06B8, 0x02D0, 1, 0x0000, 0, 0),
-	MX6_PAD_SD3_RST__UART3_RTS		= IOMUX_PAD(0x06B8, 0x02D0, 1, 0x092C, 5, 0),
-	MX6_PAD_SD3_RST__PCIE_CTRL_MUX_30	= IOMUX_PAD(0x06B8, 0x02D0, 2, 0x0000, 0, 0),
-	MX6_PAD_SD3_RST__USBOH3_UH3_DFD_OUT_10	= IOMUX_PAD(0x06B8, 0x02D0, 3, 0x0000, 0, 0),
-	MX6_PAD_SD3_RST__USBOH3_UH2_DFD_OUT_10	= IOMUX_PAD(0x06B8, 0x02D0, 4, 0x0000, 0, 0),
-	MX6_PAD_SD3_RST__GPIO_7_8		= IOMUX_PAD(0x06B8, 0x02D0, 5, 0x0000, 0, 0),
-	MX6_PAD_SD3_RST__MIPI_CORE_DPHY_IN_22	= IOMUX_PAD(0x06B8, 0x02D0, 6, 0x0000, 0, 0),
-	MX6_PAD_SD3_RST__ANATOP_ANATOP_TESTI_3	= IOMUX_PAD(0x06B8, 0x02D0, 7, 0x0000, 0, 0),
-	MX6_PAD_NANDF_CLE__RAWNAND_CLE		= IOMUX_PAD(0x06BC, 0x02D4, 0, 0x0000, 0, 0),
-	MX6_PAD_NANDF_CLE__IPU2_SISG_4		= IOMUX_PAD(0x06BC, 0x02D4, 1, 0x0000, 0, 0),
-	MX6_PAD_NANDF_CLE__PCIE_CTRL_MUX_31	= IOMUX_PAD(0x06BC, 0x02D4, 2, 0x0000, 0, 0),
-	MX6_PAD_NANDF_CLE__USBOH3_UH3_DFD_OT11 = IOMUX_PAD(0x06BC, 0x02D4, 3, 0x0000, 0, 0),
-	MX6_PAD_NANDF_CLE__USBOH3_UH2_DFD_OT11	= IOMUX_PAD(0x06BC, 0x02D4, 4, 0x0000, 0, 0),
-	MX6_PAD_NANDF_CLE__GPIO_6_7		= IOMUX_PAD(0x06BC, 0x02D4, 5, 0x0000, 0, 0),
-	MX6_PAD_NANDF_CLE__MIPI_CORE_DPHY_IN23 = IOMUX_PAD(0x06BC, 0x02D4, 6, 0x0000, 0, 0),
-	MX6_PAD_NANDF_CLE__TPSMP_HTRANS_0	= IOMUX_PAD(0x06BC, 0x02D4, 7, 0x0000, 0, 0),
-	MX6_PAD_NANDF_ALE__RAWNAND_ALE		= IOMUX_PAD(0x06C0, 0x02D8, 0, 0x0000, 0, 0),
-	MX6_PAD_NANDF_ALE__USDHC4_RST		= IOMUX_PAD(0x06C0, 0x02D8, 1, 0x0000, 0, 0),
-	MX6_PAD_NANDF_ALE__PCIE_CTRL_MUX_0	= IOMUX_PAD(0x06C0, 0x02D8, 2, 0x0000, 0, 0),
-	MX6_PAD_NANDF_ALE__USBOH3_UH3_DFD_OT12	= IOMUX_PAD(0x06C0, 0x02D8, 3, 0x0000, 0, 0),
-	MX6_PAD_NANDF_ALE__USBOH3_UH2_DFD_OT12	= IOMUX_PAD(0x06C0, 0x02D8, 4, 0x0000, 0, 0),
-	MX6_PAD_NANDF_ALE__GPIO_6_8		= IOMUX_PAD(0x06C0, 0x02D8, 5, 0x0000, 0, 0),
-	MX6_PAD_NANDF_ALE__MIPI_CR_DPHY_IN_24	= IOMUX_PAD(0x06C0, 0x02D8, 6, 0x0000, 0, 0),
-	MX6_PAD_NANDF_ALE__TPSMP_HTRANS_1	= IOMUX_PAD(0x06C0, 0x02D8, 7, 0x0000, 0, 0),
-	MX6_PAD_NANDF_WP_B__RAWNAND_RESETN	= IOMUX_PAD(0x06C4, 0x02DC, 0, 0x0000, 0, 0),
-	MX6_PAD_NANDF_WP_B__IPU2_SISG_5	= IOMUX_PAD(0x06C4, 0x02DC, 1, 0x0000, 0, 0),
-	MX6_PAD_NANDF_WP_B__PCIE_CTRL__MUX_1	= IOMUX_PAD(0x06C4, 0x02DC, 2, 0x0000, 0, 0),
-	MX6_PAD_NANDF_WP_B__USBOH3_UH3_DFDOT13 = IOMUX_PAD(0x06C4, 0x02DC, 3, 0x0000, 0, 0),
-	MX6_PAD_NANDF_WP_B__USBOH3_UH2_DFDOT13 = IOMUX_PAD(0x06C4, 0x02DC, 4, 0x0000, 0, 0),
-	MX6_PAD_NANDF_WP_B__GPIO_6_9		= IOMUX_PAD(0x06C4, 0x02DC, 5, 0x0000, 0, 0),
-	MX6_PAD_NANDF_WP_B__MIPI_CR_DPHY_OUT32	= IOMUX_PAD(0x06C4, 0x02DC, 6, 0x0000, 0, 0),
-	MX6_PAD_NANDF_WP_B__PL301_PER1_HSIZE_0 = IOMUX_PAD(0x06C4, 0x02DC, 7, 0x0000, 0, 0),
-	MX6_PAD_NANDF_RB0__RAWNAND_READY0	= IOMUX_PAD(0x06C8, 0x02E0, 0, 0x0000, 0, 0),
-	MX6_PAD_NANDF_RB0__IPU2_DI0_PIN1	= IOMUX_PAD(0x06C8, 0x02E0, 1, 0x0000, 0, 0),
-	MX6_PAD_NANDF_RB0__PCIE_CTRL_MUX_2	= IOMUX_PAD(0x06C8, 0x02E0, 2, 0x0000, 0, 0),
-	MX6_PAD_NANDF_RB0__USBOH3_UH3_DFD_OT14 = IOMUX_PAD(0x06C8, 0x02E0, 3, 0x0000, 0, 0),
-	MX6_PAD_NANDF_RB0__USBOH3_UH2_DFD_OT14 = IOMUX_PAD(0x06C8, 0x02E0, 4, 0x0000, 0, 0),
-	MX6_PAD_NANDF_RB0__GPIO_6_10		= IOMUX_PAD(0x06C8, 0x02E0, 5, 0x0000, 0, 0),
-	MX6_PAD_NANDF_RB0__MIPI_CR_DPHY_OUT_33	= IOMUX_PAD(0x06C8, 0x02E0, 6, 0x0000, 0, 0),
-	MX6_PAD_NANDF_RB0__PL301_PER1_HSIZE_1	= IOMUX_PAD(0x06C8, 0x02E0, 7, 0x0000, 0, 0),
-	MX6_PAD_NANDF_CS0__RAWNAND_CE0N	= IOMUX_PAD(0x06CC, 0x02E4, 0, 0x0000, 0, 0),
-	MX6_PAD_NANDF_CS0__USBOH3_UH3_DFD_OT15 = IOMUX_PAD(0x06CC, 0x02E4, 3, 0x0000, 0, 0),
-	MX6_PAD_NANDF_CS0__USBOH3_UH2_DFD_OT15 = IOMUX_PAD(0x06CC, 0x02E4, 4, 0x0000, 0, 0),
-	MX6_PAD_NANDF_CS0__GPIO_6_11		= IOMUX_PAD(0x06CC, 0x02E4, 5, 0x0000, 0, 0),
-	MX6_PAD_NANDF_CS0__PL301_PER1_HSIZE_2	= IOMUX_PAD(0x06CC, 0x02E4, 7, 0x0000, 0, 0),
-	MX6_PAD_NANDF_CS1__RAWNAND_CE1N	= IOMUX_PAD(0x06D0, 0x02E8, 0, 0x0000, 0, 0),
-	MX6_PAD_NANDF_CS1__USDHC4_VSELECT	= IOMUX_PAD(0x06D0, 0x02E8, 1, 0x0000, 0, 0),
-	MX6_PAD_NANDF_CS1__USDHC3_VSELECT	= IOMUX_PAD(0x06D0, 0x02E8, 2, 0x0000, 0, 0),
-	MX6_PAD_NANDF_CS1__PCIE_CTRL_MUX_3	= IOMUX_PAD(0x06D0, 0x02E8, 4, 0x0000, 0, 0),
-	MX6_PAD_NANDF_CS1__GPIO_6_14		= IOMUX_PAD(0x06D0, 0x02E8, 5, 0x0000, 0, 0),
-	MX6_PAD_NANDF_CS1__PL301_PER1_HRDYOUT	= IOMUX_PAD(0x06D0, 0x02E8, 7, 0x0000, 0, 0),
-	MX6_PAD_NANDF_CS2__RAWNAND_CE2N	= IOMUX_PAD(0x06D4, 0x02EC, 0, 0x0000, 0, 0),
-	MX6_PAD_NANDF_CS2__IPU1_SISG_0		= IOMUX_PAD(0x06D4, 0x02EC, 1, 0x0000, 0, 0),
-	MX6_PAD_NANDF_CS2__ESAI1_TX0		= IOMUX_PAD(0x06D4, 0x02EC, 2, 0x0874, 1, 0),
-	MX6_PAD_NANDF_CS2__WEIM_WEIM_CRE	= IOMUX_PAD(0x06D4, 0x02EC, 3, 0x0000, 0, 0),
-	MX6_PAD_NANDF_CS2__CCM_CLKO2		= IOMUX_PAD(0x06D4, 0x02EC, 4, 0x0000, 0, 0),
-	MX6_PAD_NANDF_CS2__GPIO_6_15		= IOMUX_PAD(0x06D4, 0x02EC, 5, 0x0000, 0, 0),
-	MX6_PAD_NANDF_CS2__IPU2_SISG_0		= IOMUX_PAD(0x06D4, 0x02EC, 6, 0x0000, 0, 0),
-	MX6_PAD_NANDF_CS3__RAWNAND_CE3N	= IOMUX_PAD(0x06D8, 0x02F0, 0, 0x0000, 0, 0),
-	MX6_PAD_NANDF_CS3__IPU1_SISG_1		= IOMUX_PAD(0x06D8, 0x02F0, 1, 0x0000, 0, 0),
-	MX6_PAD_NANDF_CS3__ESAI1_TX1		= IOMUX_PAD(0x06D8, 0x02F0, 2, 0x0878, 1, 0),
-	MX6_PAD_NANDF_CS3__WEIM_WEIM_A_26	= IOMUX_PAD(0x06D8, 0x02F0, 3, 0x0000, 0, 0),
-	MX6_PAD_NANDF_CS3__PCIE_CTRL_MUX_4	= IOMUX_PAD(0x06D8, 0x02F0, 4, 0x0000, 0, 0),
-	MX6_PAD_NANDF_CS3__GPIO_6_16		= IOMUX_PAD(0x06D8, 0x02F0, 5, 0x0000, 0, 0),
-	MX6_PAD_NANDF_CS3__IPU2_SISG_1		= IOMUX_PAD(0x06D8, 0x02F0, 6, 0x0000, 0, 0),
-	MX6_PAD_NANDF_CS3__TPSMP_CLK		= IOMUX_PAD(0x06D8, 0x02F0, 7, 0x0000, 0, 0),
-	MX6_PAD_SD4_CMD__USDHC4_CMD		= IOMUX_PAD(0x06DC, 0x02F4, 16, 0x0000, 0, 0),
-	MX6_PAD_SD4_CMD__RAWNAND_RDN		= IOMUX_PAD(0x06DC, 0x02F4, 1, 0x0000, 0, 0),
-	MX6_PAD_SD4_CMD__UART3_TXD		= IOMUX_PAD(0x06DC, 0x02F4, 2, 0x0000, 0, 0),
-	MX6_PAD_SD4_CMD__UART3_TXD_RXD		= IOMUX_PAD(0x06DC, 0x02F4, 2, 0x0930, 2, 0),
-	MX6_PAD_SD4_CMD__PCIE_CTRL_MUX_5	= IOMUX_PAD(0x06DC, 0x02F4, 4, 0x0000, 0, 0),
-	MX6_PAD_SD4_CMD__GPIO_7_9		= IOMUX_PAD(0x06DC, 0x02F4, 5, 0x0000, 0, 0),
-	MX6_PAD_SD4_CMD__TPSMP_HDATA_DIR	= IOMUX_PAD(0x06DC, 0x02F4, 7, 0x0000, 0, 0),
-	MX6_PAD_SD4_CLK__USDHC4_CLK		= IOMUX_PAD(0x06E0, 0x02F8, 0, 0x0000, 0, 0),
-	MX6_PAD_SD4_CLK__RAWNAND_WRN		= IOMUX_PAD(0x06E0, 0x02F8, 1, 0x0000, 0, 0),
-	MX6_PAD_SD4_CLK__UART3_RXD		= IOMUX_PAD(0x06E0, 0x02F8, 2, 0x0930, 3, 0),
-	MX6_PAD_SD4_CLK__PCIE_CTRL_MUX_6	= IOMUX_PAD(0x06E0, 0x02F8, 4, 0x0000, 0, 0),
-	MX6_PAD_SD4_CLK__GPIO_7_10		= IOMUX_PAD(0x06E0, 0x02F8, 5, 0x0000, 0, 0),
-	MX6_PAD_NANDF_D0__RAWNAND_D0		= IOMUX_PAD(0x06E4, 0x02FC, 0, 0x0000, 0, 0),
-	MX6_PAD_NANDF_D0__USDHC1_DAT4		= IOMUX_PAD(0x06E4, 0x02FC, 1, 0x0000, 0, 0),
-	MX6_PAD_NANDF_D0__GPU3D_GPU_DBG_OUT_0	= IOMUX_PAD(0x06E4, 0x02FC, 2, 0x0000, 0, 0),
-	MX6_PAD_NANDF_D0__USBOH3_UH2_DFD_OUT16	= IOMUX_PAD(0x06E4, 0x02FC, 3, 0x0000, 0, 0),
-	MX6_PAD_NANDF_D0__USBOH3_UH3_DFD_OUT16	= IOMUX_PAD(0x06E4, 0x02FC, 4, 0x0000, 0, 0),
-	MX6_PAD_NANDF_D0__GPIO_2_0		= IOMUX_PAD(0x06E4, 0x02FC, 5, 0x0000, 0, 0),
-	MX6_PAD_NANDF_D0__IPU1_IPU_DIAG_BUS_0	= IOMUX_PAD(0x06E4, 0x02FC, 6, 0x0000, 0, 0),
-	MX6_PAD_NANDF_D0__IPU2_IPU_DIAG_BUS_0	= IOMUX_PAD(0x06E4, 0x02FC, 7, 0x0000, 0, 0),
-	MX6_PAD_NANDF_D1__RAWNAND_D1		= IOMUX_PAD(0x06E8, 0x0300, 0, 0x0000, 0, 0),
-	MX6_PAD_NANDF_D1__USDHC1_DAT5		= IOMUX_PAD(0x06E8, 0x0300, 1, 0x0000, 0, 0),
-	MX6_PAD_NANDF_D1__GPU3D_GPU_DEBUG_OUT1	= IOMUX_PAD(0x06E8, 0x0300, 2, 0x0000, 0, 0),
-	MX6_PAD_NANDF_D1__USBOH3_UH2_DFD_OUT17	= IOMUX_PAD(0x06E8, 0x0300, 3, 0x0000, 0, 0),
-	MX6_PAD_NANDF_D1__USBOH3_UH3_DFD_OUT17	= IOMUX_PAD(0x06E8, 0x0300, 4, 0x0000, 0, 0),
-	MX6_PAD_NANDF_D1__GPIO_2_1		= IOMUX_PAD(0x06E8, 0x0300, 5, 0x0000, 0, 0),
-	MX6_PAD_NANDF_D1__IPU1_IPU_DIAG_BUS_1	= IOMUX_PAD(0x06E8, 0x0300, 6, 0x0000, 0, 0),
-	MX6_PAD_NANDF_D1__IPU2_IPU_DIAG_BUS_1	= IOMUX_PAD(0x06E8, 0x0300, 7, 0x0000, 0, 0),
-	MX6_PAD_NANDF_D2__RAWNAND_D2		= IOMUX_PAD(0x06EC, 0x0304, 0, 0x0000, 0, 0),
-	MX6_PAD_NANDF_D2__USDHC1_DAT6		= IOMUX_PAD(0x06EC, 0x0304, 1, 0x0000, 0, 0),
-	MX6_PAD_NANDF_D2__GPU3D_GPU_DBG_OUT_2	= IOMUX_PAD(0x06EC, 0x0304, 2, 0x0000, 0, 0),
-	MX6_PAD_NANDF_D2__USBOH3_UH2_DFD_OUT18	= IOMUX_PAD(0x06EC, 0x0304, 3, 0x0000, 0, 0),
-	MX6_PAD_NANDF_D2__USBOH3_UH3_DFD_OUT18	= IOMUX_PAD(0x06EC, 0x0304, 4, 0x0000, 0, 0),
-	MX6_PAD_NANDF_D2__GPIO_2_2		= IOMUX_PAD(0x06EC, 0x0304, 5, 0x0000, 0, 0),
-	MX6_PAD_NANDF_D2__IPU1_IPU_DIAG_BUS_2	= IOMUX_PAD(0x06EC, 0x0304, 6, 0x0000, 0, 0),
-	MX6_PAD_NANDF_D2__IPU2_IPU_DIAG_BUS_2	= IOMUX_PAD(0x06EC, 0x0304, 7, 0x0000, 0, 0),
-	MX6_PAD_NANDF_D3__RAWNAND_D3		= IOMUX_PAD(0x06F0, 0x0308, 0, 0x0000, 0, 0),
-	MX6_PAD_NANDF_D3__USDHC1_DAT7		= IOMUX_PAD(0x06F0, 0x0308, 1, 0x0000, 0, 0),
-	MX6_PAD_NANDF_D3__GPU3D_GPU_DBG_OUT_3	= IOMUX_PAD(0x06F0, 0x0308, 2, 0x0000, 0, 0),
-	MX6_PAD_NANDF_D3__USBOH3_UH2_DFD_OUT19	= IOMUX_PAD(0x06F0, 0x0308, 3, 0x0000, 0, 0),
-	MX6_PAD_NANDF_D3__USBOH3_UH3_DFD_OUT19	= IOMUX_PAD(0x06F0, 0x0308, 4, 0x0000, 0, 0),
-	MX6_PAD_NANDF_D3__GPIO_2_3		= IOMUX_PAD(0x06F0, 0x0308, 5, 0x0000, 0, 0),
-	MX6_PAD_NANDF_D3__IPU1_IPU_DIAG_BUS_3	= IOMUX_PAD(0x06F0, 0x0308, 6, 0x0000, 0, 0),
-	MX6_PAD_NANDF_D3__IPU2_IPU_DIAG_BUS_3	= IOMUX_PAD(0x06F0, 0x0308, 7, 0x0000, 0, 0),
-	MX6_PAD_NANDF_D4__RAWNAND_D4		= IOMUX_PAD(0x06F4, 0x030C, 0, 0x0000, 0, 0),
-	MX6_PAD_NANDF_D4__USDHC2_DAT4		= IOMUX_PAD(0x06F4, 0x030C, 1, 0x0000, 0, 0),
-	MX6_PAD_NANDF_D4__GPU3D_GPU_DBG_OUT_4	= IOMUX_PAD(0x06F4, 0x030C, 2, 0x0000, 0, 0),
-	MX6_PAD_NANDF_D4__USBOH3_UH2_DFD_OUT20	= IOMUX_PAD(0x06F4, 0x030C, 3, 0x0000, 0, 0),
-	MX6_PAD_NANDF_D4__USBOH3_UH3_DFD_OUT20	= IOMUX_PAD(0x06F4, 0x030C, 4, 0x0000, 0, 0),
-	MX6_PAD_NANDF_D4__GPIO_2_4		= IOMUX_PAD(0x06F4, 0x030C, 5, 0x0000, 0, 0),
-	MX6_PAD_NANDF_D4__IPU1_IPU_DIAG_BUS_4	= IOMUX_PAD(0x06F4, 0x030C, 6, 0x0000, 0, 0),
-	MX6_PAD_NANDF_D4__IPU2_IPU_DIAG_BUS_4	= IOMUX_PAD(0x06F4, 0x030C, 7, 0x0000, 0, 0),
-	MX6_PAD_NANDF_D5__RAWNAND_D5		= IOMUX_PAD(0x06F8, 0x0310, 0, 0x0000, 0, 0),
-	MX6_PAD_NANDF_D5__USDHC2_DAT5		= IOMUX_PAD(0x06F8, 0x0310, 1, 0x0000, 0, 0),
-	MX6_PAD_NANDF_D5__GPU3D_GPU_DBG_OUT_5	= IOMUX_PAD(0x06F8, 0x0310, 2, 0x0000, 0, 0),
-	MX6_PAD_NANDF_D5__USBOH3_UH2_DFD_OUT21	= IOMUX_PAD(0x06F8, 0x0310, 3, 0x0000, 0, 0),
-	MX6_PAD_NANDF_D5__USBOH3_UH3_DFD_OUT21	= IOMUX_PAD(0x06F8, 0x0310, 4, 0x0000, 0, 0),
-	MX6_PAD_NANDF_D5__GPIO_2_5		= IOMUX_PAD(0x06F8, 0x0310, 5, 0x0000, 0, 0),
-	MX6_PAD_NANDF_D5__IPU1_IPU_DIAG_BUS_5	= IOMUX_PAD(0x06F8, 0x0310, 6, 0x0000, 0, 0),
-	MX6_PAD_NANDF_D5__IPU2_IPU_DIAG_BUS_5	= IOMUX_PAD(0x06F8, 0x0310, 7, 0x0000, 0, 0),
-	MX6_PAD_NANDF_D6__RAWNAND_D6		= IOMUX_PAD(0x06FC, 0x0314, 0, 0x0000, 0, 0),
-	MX6_PAD_NANDF_D6__USDHC2_DAT6		= IOMUX_PAD(0x06FC, 0x0314, 1, 0x0000, 0, 0),
-	MX6_PAD_NANDF_D6__GPU3D_GPU_DBG_OUT_6	= IOMUX_PAD(0x06FC, 0x0314, 2, 0x0000, 0, 0),
-	MX6_PAD_NANDF_D6__USBOH3_UH2_DFD_OUT22	= IOMUX_PAD(0x06FC, 0x0314, 3, 0x0000, 0, 0),
-	MX6_PAD_NANDF_D6__USBOH3_UH3_DFD_OUT22	= IOMUX_PAD(0x06FC, 0x0314, 4, 0x0000, 0, 0),
-	MX6_PAD_NANDF_D6__GPIO_2_6		= IOMUX_PAD(0x06FC, 0x0314, 5, 0x0000, 0, 0),
-	MX6_PAD_NANDF_D6__IPU1_IPU_DIAG_BUS_6	= IOMUX_PAD(0x06FC, 0x0314, 6, 0x0000, 0, 0),
-	MX6_PAD_NANDF_D6__IPU2_IPU_DIAG_BUS_6	= IOMUX_PAD(0x06FC, 0x0314, 7, 0x0000, 0, 0),
-	MX6_PAD_NANDF_D7__RAWNAND_D7		= IOMUX_PAD(0x0700, 0x0318, 0, 0x0000, 0, 0),
-	MX6_PAD_NANDF_D7__USDHC2_DAT7		= IOMUX_PAD(0x0700, 0x0318, 1, 0x0000, 0, 0),
-	MX6_PAD_NANDF_D7__GPU3D_GPU_DBG_OUT_7	= IOMUX_PAD(0x0700, 0x0318, 2, 0x0000, 0, 0),
-	MX6_PAD_NANDF_D7__USBOH3_UH2_DFD_OUT23	= IOMUX_PAD(0x0700, 0x0318, 3, 0x0000, 0, 0),
-	MX6_PAD_NANDF_D7__USBOH3_UH3_DFD_OUT23	= IOMUX_PAD(0x0700, 0x0318, 4, 0x0000, 0, 0),
-	MX6_PAD_NANDF_D7__GPIO_2_7		= IOMUX_PAD(0x0700, 0x0318, 5, 0x0000, 0, 0),
-	MX6_PAD_NANDF_D7__IPU1_IPU_DIAG_BUS_7	= IOMUX_PAD(0x0700, 0x0318, 6, 0x0000, 0, 0),
-	MX6_PAD_NANDF_D7__IPU2_IPU_DIAG_BUS_7	= IOMUX_PAD(0x0700, 0x0318, 7, 0x0000, 0, 0),
-	MX6_PAD_SD4_DAT0__RAWNAND_D8		= IOMUX_PAD(0x0704, 0x031C, 0, 0x0000, 0, 0),
-	MX6_PAD_SD4_DAT0__USDHC4_DAT0		= IOMUX_PAD(0x0704, 0x031C, 1, 0x0000, 0, 0),
-	MX6_PAD_SD4_DAT0__RAWNAND_DQS		= IOMUX_PAD(0x0704, 0x031C, 2, 0x0000, 0, 0),
-	MX6_PAD_SD4_DAT0__USBOH3_UH2_DFD_OUT24	= IOMUX_PAD(0x0704, 0x031C, 3, 0x0000, 0, 0),
-	MX6_PAD_SD4_DAT0__USBOH3_UH3_DFD_OUT24	= IOMUX_PAD(0x0704, 0x031C, 4, 0x0000, 0, 0),
-	MX6_PAD_SD4_DAT0__GPIO_2_8		= IOMUX_PAD(0x0704, 0x031C, 5, 0x0000, 0, 0),
-	MX6_PAD_SD4_DAT0__IPU1_IPU_DIAG_BUS_8	= IOMUX_PAD(0x0704, 0x031C, 6, 0x0000, 0, 0),
-	MX6_PAD_SD4_DAT0__IPU2_IPU_DIAG_BUS_8	= IOMUX_PAD(0x0704, 0x031C, 7, 0x0000, 0, 0),
-	MX6_PAD_SD4_DAT1__RAWNAND_D9		= IOMUX_PAD(0x0708, 0x0320, 0, 0x0000, 0, 0),
-	MX6_PAD_SD4_DAT1__USDHC4_DAT1		= IOMUX_PAD(0x0708, 0x0320, 1, 0x0000, 0, 0),
-	MX6_PAD_SD4_DAT1__PWM3_PWMO		= IOMUX_PAD(0x0708, 0x0320, 2, 0x0000, 0, 0),
-	MX6_PAD_SD4_DAT1__USBOH3_UH2_DFD_OUT25	= IOMUX_PAD(0x0708, 0x0320, 3, 0x0000, 0, 0),
-	MX6_PAD_SD4_DAT1__USBOH3_UH3_DFD_OUT25	= IOMUX_PAD(0x0708, 0x0320, 4, 0x0000, 0, 0),
-	MX6_PAD_SD4_DAT1__GPIO_2_9		= IOMUX_PAD(0x0708, 0x0320, 5, 0x0000, 0, 0),
-	MX6_PAD_SD4_DAT1__IPU1_IPU_DIAG_BUS_9	= IOMUX_PAD(0x0708, 0x0320, 6, 0x0000, 0, 0),
-	MX6_PAD_SD4_DAT1__IPU2_IPU_DIAG_BUS_9	= IOMUX_PAD(0x0708, 0x0320, 7, 0x0000, 0, 0),
-	MX6_PAD_SD4_DAT2__RAWNAND_D10		= IOMUX_PAD(0x070C, 0x0324, 0, 0x0000, 0, 0),
-	MX6_PAD_SD4_DAT2__USDHC4_DAT2		= IOMUX_PAD(0x070C, 0x0324, 1, 0x0000, 0, 0),
-	MX6_PAD_SD4_DAT2__PWM4_PWMO		= IOMUX_PAD(0x070C, 0x0324, 2, 0x0000, 0, 0),
-	MX6_PAD_SD4_DAT2__USBOH3_UH2_DFD_OUT26	= IOMUX_PAD(0x070C, 0x0324, 3, 0x0000, 0, 0),
-	MX6_PAD_SD4_DAT2__USBOH3_UH3_DFD_OUT26	= IOMUX_PAD(0x070C, 0x0324, 4, 0x0000, 0, 0),
-	MX6_PAD_SD4_DAT2__GPIO_2_10		= IOMUX_PAD(0x070C, 0x0324, 5, 0x0000, 0, 0),
-	MX6_PAD_SD4_DAT2__IPU1_IPU_DIAG_BUS_10	= IOMUX_PAD(0x070C, 0x0324, 6, 0x0000, 0, 0),
-	MX6_PAD_SD4_DAT2__IPU2_IPU_DIAG_BUS_10	= IOMUX_PAD(0x070C, 0x0324, 7, 0x0000, 0, 0),
-	MX6_PAD_SD4_DAT3__RAWNAND_D11		= IOMUX_PAD(0x0710, 0x0328, 0, 0x0000, 0, 0),
-	MX6_PAD_SD4_DAT3__USDHC4_DAT3		= IOMUX_PAD(0x0710, 0x0328, 1, 0x0000, 0, 0),
-	MX6_PAD_SD4_DAT3__USBOH3_UH2_DFD_OUT27	= IOMUX_PAD(0x0710, 0x0328, 3, 0x0000, 0, 0),
-	MX6_PAD_SD4_DAT3__USBOH3_UH3_DFD_OUT27	= IOMUX_PAD(0x0710, 0x0328, 4, 0x0000, 0, 0),
-	MX6_PAD_SD4_DAT3__GPIO_2_11		= IOMUX_PAD(0x0710, 0x0328, 5, 0x0000, 0, 0),
-	MX6_PAD_SD4_DAT3__IPU1_IPU_DIAG_BUS_11	= IOMUX_PAD(0x0710, 0x0328, 6, 0x0000, 0, 0),
-	MX6_PAD_SD4_DAT3__IPU2_IPU_DIAG_BUS_11	= IOMUX_PAD(0x0710, 0x0328, 7, 0x0000, 0, 0),
-	MX6_PAD_SD4_DAT4__RAWNAND_D12		= IOMUX_PAD(0x0714, 0x032C, 0, 0x0000, 0, 0),
-	MX6_PAD_SD4_DAT4__USDHC4_DAT4		= IOMUX_PAD(0x0714, 0x032C, 1, 0x0000, 0, 0),
-	MX6_PAD_SD4_DAT4__UART2_RXD		= IOMUX_PAD(0x0714, 0x032C, 2, 0x0928, 6, 0),
-	MX6_PAD_SD4_DAT4__USBOH3_UH2_DFD_OUT28	= IOMUX_PAD(0x0714, 0x032C, 3, 0x0000, 0, 0),
-	MX6_PAD_SD4_DAT4__USBOH3_UH3_DFD_OUT28	= IOMUX_PAD(0x0714, 0x032C, 4, 0x0000, 0, 0),
-	MX6_PAD_SD4_DAT4__GPIO_2_12		= IOMUX_PAD(0x0714, 0x032C, 5, 0x0000, 0, 0),
-	MX6_PAD_SD4_DAT4__IPU1_IPU_DIAG_BUS_12	= IOMUX_PAD(0x0714, 0x032C, 6, 0x0000, 0, 0),
-	MX6_PAD_SD4_DAT4__IPU2_IPU_DIAG_BUS_12	= IOMUX_PAD(0x0714, 0x032C, 7, 0x0000, 0, 0),
-	MX6_PAD_SD4_DAT5__RAWNAND_D13		= IOMUX_PAD(0x0718, 0x0330, 0, 0x0000, 0, 0),
-	MX6_PAD_SD4_DAT5__USDHC4_DAT5		= IOMUX_PAD(0x0718, 0x0330, 1, 0x0000, 0, 0),
-	MX6_PAD_SD4_DAT5__UART2_CTS		= IOMUX_PAD(0x0718, 0x0330, 2, 0x0000, 0, 0),
-	MX6_PAD_SD4_DAT5__UART2_RTS		= IOMUX_PAD(0x0718, 0x0330, 2, 0x0924, 4, 0),
-	MX6_PAD_SD4_DAT5__USBOH3_UH2_DFD_OUT29	= IOMUX_PAD(0x0718, 0x0330, 3, 0x0000, 0, 0),
-	MX6_PAD_SD4_DAT5__USBOH3_UH3_DFD_OUT29	= IOMUX_PAD(0x0718, 0x0330, 4, 0x0000, 0, 0),
-	MX6_PAD_SD4_DAT5__GPIO_2_13		= IOMUX_PAD(0x0718, 0x0330, 5, 0x0000, 0, 0),
-	MX6_PAD_SD4_DAT5__IPU1_IPU_DIAG_BUS_13	= IOMUX_PAD(0x0718, 0x0330, 6, 0x0000, 0, 0),
-	MX6_PAD_SD4_DAT5__IPU2_IPU_DIAG_BUS_13	= IOMUX_PAD(0x0718, 0x0330, 7, 0x0000, 0, 0),
-	MX6_PAD_SD4_DAT6__RAWNAND_D14		= IOMUX_PAD(0x071C, 0x0334, 0, 0x0000, 0, 0),
-	MX6_PAD_SD4_DAT6__USDHC4_DAT6		= IOMUX_PAD(0x071C, 0x0334, 1, 0x0000, 0, 0),
-	MX6_PAD_SD4_DAT6__UART2_CTS		= IOMUX_PAD(0x071C, 0x0334, 2, 0x0924, 5, 0),
-	MX6_PAD_SD4_DAT6__USBOH3_UH2_DFD_OUT30	= IOMUX_PAD(0x071C, 0x0334, 3, 0x0000, 0, 0),
-	MX6_PAD_SD4_DAT6__USBOH3_UH3_DFD_OUT30	= IOMUX_PAD(0x071C, 0x0334, 4, 0x0000, 0, 0),
-	MX6_PAD_SD4_DAT6__GPIO_2_14		= IOMUX_PAD(0x071C, 0x0334, 5, 0x0000, 0, 0),
-	MX6_PAD_SD4_DAT6__IPU1_IPU_DIAG_BUS_14	= IOMUX_PAD(0x071C, 0x0334, 6, 0x0000, 0, 0),
-	MX6_PAD_SD4_DAT6__IPU2_IPU_DIAG_BUS_14	= IOMUX_PAD(0x071C, 0x0334, 7, 0x0000, 0, 0),
-	MX6_PAD_SD4_DAT7__RAWNAND_D15		= IOMUX_PAD(0x0720, 0x0338, 0, 0x0000, 0, 0),
-	MX6_PAD_SD4_DAT7__USDHC4_DAT7		= IOMUX_PAD(0x0720, 0x0338, 1, 0x0000, 0, 0),
-	MX6_PAD_SD4_DAT7__UART2_TXD		= IOMUX_PAD(0x0720, 0x0338, 2, 0x0000, 0, 0),
-	MX6_PAD_SD4_DAT7__UART2_TXD_RXD	= IOMUX_PAD(0x0720, 0x0338, 2, 0x0928, 7, 0),
-	MX6_PAD_SD4_DAT7__USBOH3_UH2_DFD_OUT31 = IOMUX_PAD(0x0720, 0x0338, 3, 0x0000, 0, 0),
-	MX6_PAD_SD4_DAT7__USBOH3_UH3_DFD_OUT31 = IOMUX_PAD(0x0720, 0x0338, 4, 0x0000, 0, 0),
-	MX6_PAD_SD4_DAT7__GPIO_2_15		= IOMUX_PAD(0x0720, 0x0338, 5, 0x0000, 0, 0),
-	MX6_PAD_SD4_DAT7__IPU1_IPU_DIAG_BUS_15	= IOMUX_PAD(0x0720, 0x0338, 6, 0x0000, 0, 0),
-	MX6_PAD_SD4_DAT7__IPU2_IPU_DIAG_BUS_15	= IOMUX_PAD(0x0720, 0x0338, 7, 0x0000, 0, 0),
-	MX6_PAD_SD1_DAT1__USDHC1_DAT1		= IOMUX_PAD(0x0724, 0x033C, 0, 0x0000, 0, 0),
-	MX6_PAD_SD1_DAT1__ECSPI5_SS0		= IOMUX_PAD(0x0724, 0x033C, 1, 0x0834, 1, 0),
-	MX6_PAD_SD1_DAT1__PWM3_PWMO		= IOMUX_PAD(0x0724, 0x033C, 2, 0x0000, 0, 0),
-	MX6_PAD_SD1_DAT1__GPT_CAPIN2		= IOMUX_PAD(0x0724, 0x033C, 3, 0x0000, 0, 0),
-	MX6_PAD_SD1_DAT1__PCIE_CTRL_MUX_7	= IOMUX_PAD(0x0724, 0x033C, 4, 0x0000, 0, 0),
-	MX6_PAD_SD1_DAT1__GPIO_1_17		= IOMUX_PAD(0x0724, 0x033C, 5, 0x0000, 0, 0),
-	MX6_PAD_SD1_DAT1__HDMI_TX_OPHYDTB_0	= IOMUX_PAD(0x0724, 0x033C, 6, 0x0000, 0, 0),
-	MX6_PAD_SD1_DAT1__ANATOP_TESTO_8	= IOMUX_PAD(0x0724, 0x033C, 7, 0x0000, 0, 0),
-	MX6_PAD_SD1_DAT0__USDHC1_DAT0		= IOMUX_PAD(0x0728, 0x0340, 0, 0x0000, 0, 0),
-	MX6_PAD_SD1_DAT0__ECSPI5_MISO		= IOMUX_PAD(0x0728, 0x0340, 1, 0x082C, 1, 0),
-	MX6_PAD_SD1_DAT0__CAAM_WRAP_RNG_OSCOBS	= IOMUX_PAD(0x0728, 0x0340, 2, 0x0000, 0, 0),
-	MX6_PAD_SD1_DAT0__GPT_CAPIN1		= IOMUX_PAD(0x0728, 0x0340, 3, 0x0000, 0, 0),
-	MX6_PAD_SD1_DAT0__PCIE_CTRL_MUX_8	= IOMUX_PAD(0x0728, 0x0340, 4, 0x0000, 0, 0),
-	MX6_PAD_SD1_DAT0__GPIO_1_16		= IOMUX_PAD(0x0728, 0x0340, 5, 0x0000, 0, 0),
-	MX6_PAD_SD1_DAT0__HDMI_TX_OPHYDTB_1	= IOMUX_PAD(0x0728, 0x0340, 6, 0x0000, 0, 0),
-	MX6_PAD_SD1_DAT0__ANATOP_TESTO_7	= IOMUX_PAD(0x0728, 0x0340, 7, 0x0000, 0, 0),
-	MX6_PAD_SD1_DAT3__USDHC1_DAT3		= IOMUX_PAD(0x072C, 0x0344, 0, 0x0000, 0, 0),
-	MX6_PAD_SD1_DAT3__ECSPI5_SS2		= IOMUX_PAD(0x072C, 0x0344, 1, 0x0000, 0, 0),
-	MX6_PAD_SD1_DAT3__GPT_CMPOUT3		= IOMUX_PAD(0x072C, 0x0344, 2, 0x0000, 0, 0),
-	MX6_PAD_SD1_DAT3__PWM1_PWMO		= IOMUX_PAD(0x072C, 0x0344, 3, 0x0000, 0, 0),
-	MX6_PAD_SD1_DAT3__WDOG2_WDOG_B		= IOMUX_PAD(0x072C, 0x0344, 4, 0x0000, 0, 0),
-	MX6_PAD_SD1_DAT3__GPIO_1_21		= IOMUX_PAD(0x072C, 0x0344, 5, 0x0000, 0, 0),
-	MX6_PAD_SD1_DAT3__WDOG2_WDOG_RST_B_DEB	= IOMUX_PAD(0x072C, 0x0344, 6, 0x0000, 0, 0),
-	MX6_PAD_SD1_DAT3__ANATOP_TESTO_6	= IOMUX_PAD(0x072C, 0x0344, 7, 0x0000, 0, 0),
-	MX6_PAD_SD1_CMD__USDHC1_CMD		= IOMUX_PAD(0x0730, 0x0348, 16, 0x0000, 0, 0),
-	MX6_PAD_SD1_CMD__ECSPI5_MOSI		= IOMUX_PAD(0x0730, 0x0348, 1, 0x0830, 0, 0),
-	MX6_PAD_SD1_CMD__PWM4_PWMO		= IOMUX_PAD(0x0730, 0x0348, 2, 0x0000, 0, 0),
-	MX6_PAD_SD1_CMD__GPT_CMPOUT1		= IOMUX_PAD(0x0730, 0x0348, 3, 0x0000, 0, 0),
-	MX6_PAD_SD1_CMD__GPIO_1_18		= IOMUX_PAD(0x0730, 0x0348, 5, 0x0000, 0, 0),
-	MX6_PAD_SD1_CMD__ANATOP_TESTO_5	= IOMUX_PAD(0x0730, 0x0348, 7, 0x0000, 0, 0),
-	MX6_PAD_SD1_DAT2__USDHC1_DAT2		= IOMUX_PAD(0x0734, 0x034C, 0, 0x0000, 0, 0),
-	MX6_PAD_SD1_DAT2__ECSPI5_SS1		= IOMUX_PAD(0x0734, 0x034C, 1, 0x0838, 1, 0),
-	MX6_PAD_SD1_DAT2__GPT_CMPOUT2		= IOMUX_PAD(0x0734, 0x034C, 2, 0x0000, 0, 0),
-	MX6_PAD_SD1_DAT2__PWM2_PWMO		= IOMUX_PAD(0x0734, 0x034C, 3, 0x0000, 0, 0),
-	MX6_PAD_SD1_DAT2__WDOG1_WDOG_B		= IOMUX_PAD(0x0734, 0x034C, 4, 0x0000, 0, 0),
-	MX6_PAD_SD1_DAT2__GPIO_1_19		= IOMUX_PAD(0x0734, 0x034C, 5, 0x0000, 0, 0),
-	MX6_PAD_SD1_DAT2__WDOG1_WDOG_RST_B_DEB	= IOMUX_PAD(0x0734, 0x034C, 6, 0x0000, 0, 0),
-	MX6_PAD_SD1_DAT2__ANATOP_TESTO_4	= IOMUX_PAD(0x0734, 0x034C, 7, 0x0000, 0, 0),
-	MX6_PAD_SD1_CLK__USDHC1_CLK		= IOMUX_PAD(0x0738, 0x0350, 0, 0x0000, 0, 0),
-	MX6_PAD_SD1_CLK__ECSPI5_SCLK		= IOMUX_PAD(0x0738, 0x0350, 1, 0x0828, 0, 0),
-	MX6_PAD_SD1_CLK__OSC32K_32K_OUT	= IOMUX_PAD(0x0738, 0x0350, 2, 0x0000, 0, 0),
-	MX6_PAD_SD1_CLK__GPT_CLKIN		= IOMUX_PAD(0x0738, 0x0350, 3, 0x0000, 0, 0),
-	MX6_PAD_SD1_CLK__GPIO_1_20		= IOMUX_PAD(0x0738, 0x0350, 5, 0x0000, 0, 0),
-	MX6_PAD_SD1_CLK__PHY_DTB_0		= IOMUX_PAD(0x0738, 0x0350, 6, 0x0000, 0, 0),
-	MX6_PAD_SD1_CLK__SATA_PHY_DTB_0	= IOMUX_PAD(0x0738, 0x0350, 7, 0x0000, 0, 0),
-	MX6_PAD_SD2_CLK__USDHC2_CLK		= IOMUX_PAD(0x073C, 0x0354, 0, 0x0000, 0, 0),
-	MX6_PAD_SD2_CLK__ECSPI5_SCLK		= IOMUX_PAD(0x073C, 0x0354, 1, 0x0828, 1, 0),
-	MX6_PAD_SD2_CLK__KPP_COL_5		= IOMUX_PAD(0x073C, 0x0354, 2, 0x08E8, 3, 0),
-	MX6_PAD_SD2_CLK__AUDMUX_AUD4_RXFS	= IOMUX_PAD(0x073C, 0x0354, 3, 0x07C0, 1, 0),
-	MX6_PAD_SD2_CLK__PCIE_CTRL_MUX_9	= IOMUX_PAD(0x073C, 0x0354, 4, 0x0000, 0, 0),
-	MX6_PAD_SD2_CLK__GPIO_1_10		= IOMUX_PAD(0x073C, 0x0354, 5, 0x0000, 0, 0),
-	MX6_PAD_SD2_CLK__PHY_DTB_1		= IOMUX_PAD(0x073C, 0x0354, 6, 0x0000, 0, 0),
-	MX6_PAD_SD2_CLK__SATA_PHY_DTB_1	= IOMUX_PAD(0x073C, 0x0354, 7, 0x0000, 0, 0),
-	MX6_PAD_SD2_CMD__USDHC2_CMD		= IOMUX_PAD(0x0740, 0x0358, 16, 0x0000, 0, 0),
-	MX6_PAD_SD2_CMD__ECSPI5_MOSI		= IOMUX_PAD(0x0740, 0x0358, 1, 0x0830, 1, 0),
-	MX6_PAD_SD2_CMD__KPP_ROW_5		= IOMUX_PAD(0x0740, 0x0358, 2, 0x08F4, 2, 0),
-	MX6_PAD_SD2_CMD__AUDMUX_AUD4_RXC	= IOMUX_PAD(0x0740, 0x0358, 3, 0x07BC, 1, 0),
-	MX6_PAD_SD2_CMD__PCIE_CTRL_MUX_10	= IOMUX_PAD(0x0740, 0x0358, 4, 0x0000, 0, 0),
-	MX6_PAD_SD2_CMD__GPIO_1_11		= IOMUX_PAD(0x0740, 0x0358, 5, 0x0000, 0, 0),
-	MX6_PAD_SD2_DAT3__USDHC2_DAT3		= IOMUX_PAD(0x0744, 0x035C, 0, 0x0000, 0, 0),
-	MX6_PAD_SD2_DAT3__ECSPI5_SS3		= IOMUX_PAD(0x0744, 0x035C, 1, 0x0000, 0, 0),
-	MX6_PAD_SD2_DAT3__KPP_COL_6		= IOMUX_PAD(0x0744, 0x035C, 2, 0x08EC, 2, 0),
-	MX6_PAD_SD2_DAT3__AUDMUX_AUD4_TXC	= IOMUX_PAD(0x0744, 0x035C, 3, 0x07C4, 1, 0),
-	MX6_PAD_SD2_DAT3__PCIE_CTRL_MUX_11	= IOMUX_PAD(0x0744, 0x035C, 4, 0x0000, 0, 0),
-	MX6_PAD_SD2_DAT3__GPIO_1_12		= IOMUX_PAD(0x0744, 0x035C, 5, 0x0000, 0, 0),
-	MX6_PAD_SD2_DAT3__SJC_DONE		= IOMUX_PAD(0x0744, 0x035C, 6, 0x0000, 0, 0),
-	MX6_PAD_SD2_DAT3__ANATOP_TESTO_3	= IOMUX_PAD(0x0744, 0x035C, 7, 0x0000, 0, 0),
-};
+MX6_PAD_DECL(SD2_DAT1__SD2_DATA1,	0x0360, 0x004C, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(SD2_DAT1__ECSPI5_SS0,	0x0360, 0x004C, 1, 0x0834, 0, 0)
+MX6_PAD_DECL(SD2_DAT1__EIM_CS2_B,	0x0360, 0x004C, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(SD2_DAT1__AUD4_TXFS,	0x0360, 0x004C, 3, 0x07C8, 0, 0)
+MX6_PAD_DECL(SD2_DAT1__KEY_COL7,	0x0360, 0x004C, 4, 0x08F0, 0, 0)
+MX6_PAD_DECL(SD2_DAT1__GPIO1_IO14,	0x0360, 0x004C, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(SD2_DAT2__SD2_DATA2,	0x0364, 0x0050, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(SD2_DAT2__ECSPI5_SS1,	0x0364, 0x0050, 1, 0x0838, 0, 0)
+MX6_PAD_DECL(SD2_DAT2__EIM_CS3_B,	0x0364, 0x0050, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(SD2_DAT2__AUD4_TXD,	0x0364, 0x0050, 3, 0x07B8, 0, 0)
+MX6_PAD_DECL(SD2_DAT2__KEY_ROW6,	0x0364, 0x0050, 4, 0x08F8, 0, 0)
+MX6_PAD_DECL(SD2_DAT2__GPIO1_IO13,	0x0364, 0x0050, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(SD2_DAT0__SD2_DATA0,	0x0368, 0x0054, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(SD2_DAT0__ECSPI5_MISO,	0x0368, 0x0054, 1, 0x082C, 0, 0)
+MX6_PAD_DECL(SD2_DAT0__AUD4_RXD,	0x0368, 0x0054, 3, 0x07B4, 0, 0)
+MX6_PAD_DECL(SD2_DAT0__KEY_ROW7,	0x0368, 0x0054, 4, 0x08FC, 0, 0)
+MX6_PAD_DECL(SD2_DAT0__GPIO1_IO15,	0x0368, 0x0054, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(SD2_DAT0__DCIC2_OUT,	0x0368, 0x0054, 6, 0x0000, 0, 0)
+MX6_PAD_DECL(RGMII_TXC__USB_H2_DATA,	0x036C, 0x0058, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(RGMII_TXC__RGMII_TXC,	0x036C, 0x0058, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(RGMII_TXC__SPDIF_EXT_CLK,	0x036C, 0x0058, 2, 0x0918, 0, 0)
+MX6_PAD_DECL(RGMII_TXC__GPIO6_IO19,	0x036C, 0x0058, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(RGMII_TXC__XTALOSC_REF_CLK_24M,	0x036C, 0x0058, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(RGMII_TD0__HSI_TX_READY,	0x0370, 0x005C, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(RGMII_TD0__RGMII_TD0,	0x0370, 0x005C, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(RGMII_TD0__GPIO6_IO20,	0x0370, 0x005C, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(RGMII_TD1__HSI_RX_FLAG,	0x0374, 0x0060, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(RGMII_TD1__RGMII_TD1,	0x0374, 0x0060, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(RGMII_TD1__GPIO6_IO21,	0x0374, 0x0060, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(RGMII_TD2__HSI_RX_DATA,	0x0378, 0x0064, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(RGMII_TD2__RGMII_TD2,	0x0378, 0x0064, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(RGMII_TD2__GPIO6_IO22,	0x0378, 0x0064, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(RGMII_TD3__HSI_RX_WAKE,	0x037C, 0x0068, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(RGMII_TD3__RGMII_TD3,	0x037C, 0x0068, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(RGMII_TD3__GPIO6_IO23,	0x037C, 0x0068, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(RGMII_RX_CTL__USB_H3_DATA,	0x0380, 0x006C, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(RGMII_RX_CTL__RGMII_RX_CTL,	0x0380, 0x006C, 1, 0x0858, 0, 0)
+MX6_PAD_DECL(RGMII_RX_CTL__GPIO6_IO24,	0x0380, 0x006C, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(RGMII_RD0__HSI_RX_READY,	0x0384, 0x0070, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(RGMII_RD0__RGMII_RD0,	0x0384, 0x0070, 1, 0x0848, 0, 0)
+MX6_PAD_DECL(RGMII_RD0__GPIO6_IO25,	0x0384, 0x0070, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(RGMII_TX_CTL__USB_H2_STROBE,	0x0388, 0x0074, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(RGMII_TX_CTL__RGMII_TX_CTL,	0x0388, 0x0074, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(RGMII_TX_CTL__GPIO6_IO26,	0x0388, 0x0074, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(RGMII_TX_CTL__ENET_REF_CLK,	0x0388, 0x0074, 7 | IOMUX_CONFIG_SION, 0x083C, 0, 0)
+MX6_PAD_DECL(RGMII_RD1__HSI_TX_FLAG,	0x038C, 0x0078, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(RGMII_RD1__RGMII_RD1,	0x038C, 0x0078, 1, 0x084C, 0, 0)
+MX6_PAD_DECL(RGMII_RD1__GPIO6_IO27,	0x038C, 0x0078, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(RGMII_RD2__HSI_TX_DATA,	0x0390, 0x007C, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(RGMII_RD2__RGMII_RD2,	0x0390, 0x007C, 1, 0x0850, 0, 0)
+MX6_PAD_DECL(RGMII_RD2__GPIO6_IO28,	0x0390, 0x007C, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(RGMII_RD3__HSI_TX_WAKE,	0x0394, 0x0080, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(RGMII_RD3__RGMII_RD3,	0x0394, 0x0080, 1, 0x0854, 0, 0)
+MX6_PAD_DECL(RGMII_RD3__GPIO6_IO29,	0x0394, 0x0080, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(RGMII_RXC__USB_H3_STROBE,	0x0398, 0x0084, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(RGMII_RXC__RGMII_RXC,	0x0398, 0x0084, 1, 0x0844, 0, 0)
+MX6_PAD_DECL(RGMII_RXC__GPIO6_IO30,	0x0398, 0x0084, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_A25__EIM_ADDR25,	0x039C, 0x0088, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_A25__ECSPI4_SS1,	0x039C, 0x0088, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_A25__ECSPI2_RDY,	0x039C, 0x0088, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_A25__IPU1_DI1_PIN12,	0x039C, 0x0088, 3, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_A25__IPU1_DI0_D1_CS,	0x039C, 0x0088, 4, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_A25__GPIO5_IO02,	0x039C, 0x0088, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_A25__HDMI_TX_CEC_LINE,	0x039C, 0x0088, 6, 0x088C, 0, 0)
+MX6_PAD_DECL(EIM_EB2__EIM_EB2_B,	0x03A0, 0x008C, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_EB2__ECSPI1_SS0,	0x03A0, 0x008C, 1, 0x0800, 0, 0)
+MX6_PAD_DECL(EIM_EB2__IPU2_CSI1_DATA19,	0x03A0, 0x008C, 3, 0x08D4, 0, 0)
+MX6_PAD_DECL(EIM_EB2__HDMI_TX_DDC_SCL,	0x03A0, 0x008C, 4, 0x0890, 0, 0)
+MX6_PAD_DECL(EIM_EB2__GPIO2_IO30,	0x03A0, 0x008C, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_EB2__I2C2_SCL,	0x03A0, 0x008C, 22, 0x08A0, 0, 0)
+MX6_PAD_DECL(EIM_EB2__SRC_BOOT_CFG30,	0x03A0, 0x008C, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D16__EIM_DATA16,	0x03A4, 0x0090, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D16__ECSPI1_SCLK,	0x03A4, 0x0090, 1, 0x07F4, 0, 0)
+MX6_PAD_DECL(EIM_D16__IPU1_DI0_PIN05,	0x03A4, 0x0090, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D16__IPU2_CSI1_DATA18,	0x03A4, 0x0090, 3, 0x08D0, 0, 0)
+MX6_PAD_DECL(EIM_D16__HDMI_TX_DDC_SDA,	0x03A4, 0x0090, 4, 0x0894, 0, 0)
+MX6_PAD_DECL(EIM_D16__GPIO3_IO16,	0x03A4, 0x0090, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D16__I2C2_SDA,	0x03A4, 0x0090, 22, 0x08A4, 0, 0)
+MX6_PAD_DECL(EIM_D17__EIM_DATA17,	0x03A8, 0x0094, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D17__ECSPI1_MISO,	0x03A8, 0x0094, 1, 0x07F8, 0, 0)
+MX6_PAD_DECL(EIM_D17__IPU1_DI0_PIN06,	0x03A8, 0x0094, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D17__IPU2_CSI1_PIXCLK,	0x03A8, 0x0094, 3, 0x08E0, 0, 0)
+MX6_PAD_DECL(EIM_D17__DCIC1_OUT,	0x03A8, 0x0094, 4, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D17__GPIO3_IO17,	0x03A8, 0x0094, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D17__I2C3_SCL,	0x03A8, 0x0094, 22, 0x08A8, 0, 0)
+MX6_PAD_DECL(EIM_D18__EIM_DATA18,	0x03AC, 0x0098, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D18__ECSPI1_MOSI,	0x03AC, 0x0098, 1, 0x07FC, 0, 0)
+MX6_PAD_DECL(EIM_D18__IPU1_DI0_PIN07,	0x03AC, 0x0098, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D18__IPU2_CSI1_DATA17,	0x03AC, 0x0098, 3, 0x08CC, 0, 0)
+MX6_PAD_DECL(EIM_D18__IPU1_DI1_D0_CS,	0x03AC, 0x0098, 4, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D18__GPIO3_IO18,	0x03AC, 0x0098, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D18__I2C3_SDA,	0x03AC, 0x0098, 22, 0x08AC, 0, 0)
+MX6_PAD_DECL(EIM_D19__EIM_DATA19,	0x03B0, 0x009C, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D19__ECSPI1_SS1,	0x03B0, 0x009C, 1, 0x0804, 0, 0)
+MX6_PAD_DECL(EIM_D19__IPU1_DI0_PIN08,	0x03B0, 0x009C, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D19__IPU2_CSI1_DATA16,	0x03B0, 0x009C, 3, 0x08C8, 0, 0)
+MX6_PAD_DECL(EIM_D19__UART1_CTS_B,	0x03B0, 0x009C, 4, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D19__UART1_RTS_B,	0x03B0, 0x009C, 4, 0x091C, 0, 0)
+MX6_PAD_DECL(EIM_D19__GPIO3_IO19,	0x03B0, 0x009C, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D19__EPIT1_OUT,	0x03B0, 0x009C, 6, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D20__EIM_DATA20,	0x03B4, 0x00A0, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D20__ECSPI4_SS0,	0x03B4, 0x00A0, 1, 0x0824, 0, 0)
+MX6_PAD_DECL(EIM_D20__IPU1_DI0_PIN16,	0x03B4, 0x00A0, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D20__IPU2_CSI1_DATA15,	0x03B4, 0x00A0, 3, 0x08C4, 0, 0)
+MX6_PAD_DECL(EIM_D20__UART1_CTS_B,	0x03B4, 0x00A0, 4, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D20__UART1_RTS_B,	0x03B4, 0x00A0, 4, 0x091C, 1, 0)
+MX6_PAD_DECL(EIM_D20__GPIO3_IO20,	0x03B4, 0x00A0, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D20__EPIT2_OUT,	0x03B4, 0x00A0, 6, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D21__EIM_DATA21,	0x03B8, 0x00A4, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D21__ECSPI4_SCLK,	0x03B8, 0x00A4, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D21__IPU1_DI0_PIN17,	0x03B8, 0x00A4, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D21__IPU2_CSI1_DATA11,	0x03B8, 0x00A4, 3, 0x08B4, 0, 0)
+MX6_PAD_DECL(EIM_D21__USB_OTG_OC,	0x03B8, 0x00A4, 4, 0x0944, 0, 0)
+MX6_PAD_DECL(EIM_D21__GPIO3_IO21,	0x03B8, 0x00A4, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D21__I2C1_SCL,	0x03B8, 0x00A4, 22, 0x0898, 0, 0)
+MX6_PAD_DECL(EIM_D21__SPDIF_IN,	0x03B8, 0x00A4, 7, 0x0914, 0, 0)
+MX6_PAD_DECL(EIM_D22__EIM_DATA22,	0x03BC, 0x00A8, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D22__ECSPI4_MISO,	0x03BC, 0x00A8, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D22__IPU1_DI0_PIN01,	0x03BC, 0x00A8, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D22__IPU2_CSI1_DATA10,	0x03BC, 0x00A8, 3, 0x08B0, 0, 0)
+MX6_PAD_DECL(EIM_D22__USB_OTG_PWR,	0x03BC, 0x00A8, 4, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D22__GPIO3_IO22,	0x03BC, 0x00A8, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D22__SPDIF_OUT,	0x03BC, 0x00A8, 6, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D23__EIM_DATA23,	0x03C0, 0x00AC, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D23__IPU1_DI0_D0_CS,	0x03C0, 0x00AC, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D23__UART3_CTS_B,	0x03C0, 0x00AC, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D23__UART3_RTS_B,	0x03C0, 0x00AC, 2, 0x092C, 0, 0)
+MX6_PAD_DECL(EIM_D23__UART1_DCD_B,	0x03C0, 0x00AC, 3, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D23__IPU2_CSI1_DATA_EN,	0x03C0, 0x00AC, 4, 0x08D8, 0, 0)
+MX6_PAD_DECL(EIM_D23__GPIO3_IO23,	0x03C0, 0x00AC, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D23__IPU1_DI1_PIN02,	0x03C0, 0x00AC, 6, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D23__IPU1_DI1_PIN14,	0x03C0, 0x00AC, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_EB3__EIM_EB3_B,	0x03C4, 0x00B0, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_EB3__ECSPI4_RDY,	0x03C4, 0x00B0, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_EB3__UART3_CTS_B,	0x03C4, 0x00B0, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_EB3__UART3_RTS_B,	0x03C4, 0x00B0, 2, 0x092C, 1, 0)
+MX6_PAD_DECL(EIM_EB3__UART1_RI_B,	0x03C4, 0x00B0, 3, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_EB3__IPU2_CSI1_HSYNC,	0x03C4, 0x00B0, 4, 0x08DC, 0, 0)
+MX6_PAD_DECL(EIM_EB3__GPIO2_IO31,	0x03C4, 0x00B0, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_EB3__IPU1_DI1_PIN03,	0x03C4, 0x00B0, 6, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_EB3__SRC_BOOT_CFG31,	0x03C4, 0x00B0, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D24__EIM_DATA24,	0x03C8, 0x00B4, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D24__ECSPI4_SS2,	0x03C8, 0x00B4, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D24__UART3_TX_DATA,	0x03C8, 0x00B4, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D24__UART3_RX_DATA,	0x03C8, 0x00B4, 2, 0x0930, 0, 0)
+MX6_PAD_DECL(EIM_D24__ECSPI1_SS2,	0x03C8, 0x00B4, 3, 0x0808, 0, 0)
+MX6_PAD_DECL(EIM_D24__ECSPI2_SS2,	0x03C8, 0x00B4, 4, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D24__GPIO3_IO24,	0x03C8, 0x00B4, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D24__AUD5_RXFS,	0x03C8, 0x00B4, 6, 0x07D8, 0, 0)
+MX6_PAD_DECL(EIM_D24__UART1_DTR_B,	0x03C8, 0x00B4, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D25__EIM_DATA25,	0x03CC, 0x00B8, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D25__ECSPI4_SS3,	0x03CC, 0x00B8, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D25__UART3_TX_DATA,	0x03CC, 0x00B8, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D25__UART3_RX_DATA,	0x03CC, 0x00B8, 2, 0x0930, 1, 0)
+MX6_PAD_DECL(EIM_D25__ECSPI1_SS3,	0x03CC, 0x00B8, 3, 0x080C, 0, 0)
+MX6_PAD_DECL(EIM_D25__ECSPI2_SS3,	0x03CC, 0x00B8, 4, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D25__GPIO3_IO25,	0x03CC, 0x00B8, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D25__AUD5_RXC,	0x03CC, 0x00B8, 6, 0x07D4, 0, 0)
+MX6_PAD_DECL(EIM_D25__UART1_DSR_B,	0x03CC, 0x00B8, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D26__EIM_DATA26,	0x03D0, 0x00BC, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D26__IPU1_DI1_PIN11,	0x03D0, 0x00BC, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D26__IPU1_CSI0_DATA01,	0x03D0, 0x00BC, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D26__IPU2_CSI1_DATA14,	0x03D0, 0x00BC, 3, 0x08C0, 0, 0)
+MX6_PAD_DECL(EIM_D26__UART2_TX_DATA,	0x03D0, 0x00BC, 4, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D26__UART2_RX_DATA,	0x03D0, 0x00BC, 4, 0x0928, 0, 0)
+MX6_PAD_DECL(EIM_D26__GPIO3_IO26,	0x03D0, 0x00BC, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D26__IPU1_SISG2,	0x03D0, 0x00BC, 6, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D26__IPU1_DISP1_DATA22,	0x03D0, 0x00BC, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D27__EIM_DATA27,	0x03D4, 0x00C0, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D27__IPU1_DI1_PIN13,	0x03D4, 0x00C0, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D27__IPU1_CSI0_DATA00,	0x03D4, 0x00C0, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D27__IPU2_CSI1_DATA13,	0x03D4, 0x00C0, 3, 0x08BC, 0, 0)
+MX6_PAD_DECL(EIM_D27__UART2_TX_DATA,	0x03D4, 0x00C0, 4, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D27__UART2_RX_DATA,	0x03D4, 0x00C0, 4, 0x0928, 1, 0)
+MX6_PAD_DECL(EIM_D27__GPIO3_IO27,	0x03D4, 0x00C0, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D27__IPU1_SISG3,	0x03D4, 0x00C0, 6, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D27__IPU1_DISP1_DATA23,	0x03D4, 0x00C0, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D28__EIM_DATA28,	0x03D8, 0x00C4, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D28__I2C1_SDA,	0x03D8, 0x00C4, 17, 0x089C, 0, 0)
+MX6_PAD_DECL(EIM_D28__ECSPI4_MOSI,	0x03D8, 0x00C4, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D28__IPU2_CSI1_DATA12,	0x03D8, 0x00C4, 3, 0x08B8, 0, 0)
+MX6_PAD_DECL(EIM_D28__UART2_DTE_CTS_B,	0x03D8, 0x00C4, 4, 0x0924, 0, 0)
+MX6_PAD_DECL(EIM_D28__UART2_DTE_RTS_B,	0x03D8, 0x00C4, 4, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D28__GPIO3_IO28,	0x03D8, 0x00C4, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D28__IPU1_EXT_TRIG,	0x03D8, 0x00C4, 6, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D28__IPU1_DI0_PIN13,	0x03D8, 0x00C4, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D29__EIM_DATA29,	0x03DC, 0x00C8, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D29__IPU1_DI1_PIN15,	0x03DC, 0x00C8, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D29__ECSPI4_SS0,	0x03DC, 0x00C8, 2, 0x0824, 1, 0)
+MX6_PAD_DECL(EIM_D29__UART2_CTS_B,	0x03DC, 0x00C8, 4, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D29__UART2_RTS_B,	0x03DC, 0x00C8, 4, 0x0924, 1, 0)
+MX6_PAD_DECL(EIM_D29__GPIO3_IO29,	0x03DC, 0x00C8, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D29__IPU2_CSI1_VSYNC,	0x03DC, 0x00C8, 6, 0x08E4, 0, 0)
+MX6_PAD_DECL(EIM_D29__IPU1_DI0_PIN14,	0x03DC, 0x00C8, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D30__EIM_DATA30,	0x03E0, 0x00CC, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D30__IPU1_DISP1_DATA21,	0x03E0, 0x00CC, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D30__IPU1_DI0_PIN11,	0x03E0, 0x00CC, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D30__IPU1_CSI0_DATA03,	0x03E0, 0x00CC, 3, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D30__UART3_CTS_B,	0x03E0, 0x00CC, 4, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D30__UART3_RTS_B,	0x03E0, 0x00CC, 4, 0x092C, 2, 0)
+MX6_PAD_DECL(EIM_D30__GPIO3_IO30,	0x03E0, 0x00CC, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D30__USB_H1_OC,	0x03E0, 0x00CC, 6, 0x0948, 0, 0)
+MX6_PAD_DECL(EIM_D31__EIM_DATA31,	0x03E4, 0x00D0, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D31__IPU1_DISP1_DATA20,	0x03E4, 0x00D0, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D31__IPU1_DI0_PIN12,	0x03E4, 0x00D0, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D31__IPU1_CSI0_DATA02,	0x03E4, 0x00D0, 3, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D31__UART3_CTS_B,	0x03E4, 0x00D0, 4, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D31__UART3_RTS_B,	0x03E4, 0x00D0, 4, 0x092C, 3, 0)
+MX6_PAD_DECL(EIM_D31__GPIO3_IO31,	0x03E4, 0x00D0, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D31__USB_H1_PWR,	0x03E4, 0x00D0, 6, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_A24__EIM_ADDR24,	0x03E8, 0x00D4, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_A24__IPU1_DISP1_DATA19,	0x03E8, 0x00D4, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_A24__IPU2_CSI1_DATA19,	0x03E8, 0x00D4, 2, 0x08D4, 1, 0)
+MX6_PAD_DECL(EIM_A24__IPU2_SISG2,	0x03E8, 0x00D4, 3, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_A24__IPU1_SISG2,	0x03E8, 0x00D4, 4, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_A24__GPIO5_IO04,	0x03E8, 0x00D4, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_A24__SRC_BOOT_CFG24,	0x03E8, 0x00D4, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_A23__EIM_ADDR23,	0x03EC, 0x00D8, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_A23__IPU1_DISP1_DATA18,	0x03EC, 0x00D8, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_A23__IPU2_CSI1_DATA18,	0x03EC, 0x00D8, 2, 0x08D0, 1, 0)
+MX6_PAD_DECL(EIM_A23__IPU2_SISG3,	0x03EC, 0x00D8, 3, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_A23__IPU1_SISG3,	0x03EC, 0x00D8, 4, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_A23__GPIO6_IO06,	0x03EC, 0x00D8, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_A23__SRC_BOOT_CFG23,	0x03EC, 0x00D8, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_A22__EIM_ADDR22,	0x03F0, 0x00DC, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_A22__IPU1_DISP1_DATA17,	0x03F0, 0x00DC, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_A22__IPU2_CSI1_DATA17,	0x03F0, 0x00DC, 2, 0x08CC, 1, 0)
+MX6_PAD_DECL(EIM_A22__GPIO2_IO16,	0x03F0, 0x00DC, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_A22__SRC_BOOT_CFG22,	0x03F0, 0x00DC, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_A21__EIM_ADDR21,	0x03F4, 0x00E0, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_A21__IPU1_DISP1_DATA16,	0x03F4, 0x00E0, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_A21__IPU2_CSI1_DATA16,	0x03F4, 0x00E0, 2, 0x08C8, 1, 0)
+MX6_PAD_DECL(EIM_A21__GPIO2_IO17,	0x03F4, 0x00E0, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_A21__SRC_BOOT_CFG21,	0x03F4, 0x00E0, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_A20__EIM_ADDR20,	0x03F8, 0x00E4, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_A20__IPU1_DISP1_DATA15,	0x03F8, 0x00E4, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_A20__IPU2_CSI1_DATA15,	0x03F8, 0x00E4, 2, 0x08C4, 1, 0)
+MX6_PAD_DECL(EIM_A20__GPIO2_IO18,	0x03F8, 0x00E4, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_A20__SRC_BOOT_CFG20,	0x03F8, 0x00E4, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_A19__EIM_ADDR19,	0x03FC, 0x00E8, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_A19__IPU1_DISP1_DATA14,	0x03FC, 0x00E8, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_A19__IPU2_CSI1_DATA14,	0x03FC, 0x00E8, 2, 0x08C0, 1, 0)
+MX6_PAD_DECL(EIM_A19__GPIO2_IO19,	0x03FC, 0x00E8, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_A19__SRC_BOOT_CFG19,	0x03FC, 0x00E8, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_A18__EIM_ADDR18,	0x0400, 0x00EC, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_A18__IPU1_DISP1_DATA13,	0x0400, 0x00EC, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_A18__IPU2_CSI1_DATA13,	0x0400, 0x00EC, 2, 0x08BC, 1, 0)
+MX6_PAD_DECL(EIM_A18__GPIO2_IO20,	0x0400, 0x00EC, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_A18__SRC_BOOT_CFG18,	0x0400, 0x00EC, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_A17__EIM_ADDR17,	0x0404, 0x00F0, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_A17__IPU1_DISP1_DATA12,	0x0404, 0x00F0, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_A17__IPU2_CSI1_DATA12,	0x0404, 0x00F0, 2, 0x08B8, 1, 0)
+MX6_PAD_DECL(EIM_A17__GPIO2_IO21,	0x0404, 0x00F0, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_A17__SRC_BOOT_CFG17,	0x0404, 0x00F0, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_A16__EIM_ADDR16,	0x0408, 0x00F4, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_A16__IPU1_DI1_DISP_CLK,	0x0408, 0x00F4, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_A16__IPU2_CSI1_PIXCLK,	0x0408, 0x00F4, 2, 0x08E0, 1, 0)
+MX6_PAD_DECL(EIM_A16__GPIO2_IO22,	0x0408, 0x00F4, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_A16__SRC_BOOT_CFG16,	0x0408, 0x00F4, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_CS0__EIM_CS0_B,	0x040C, 0x00F8, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_CS0__IPU1_DI1_PIN05,	0x040C, 0x00F8, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_CS0__ECSPI2_SCLK,	0x040C, 0x00F8, 2, 0x0810, 0, 0)
+MX6_PAD_DECL(EIM_CS0__GPIO2_IO23,	0x040C, 0x00F8, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_CS1__EIM_CS1_B,	0x0410, 0x00FC, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_CS1__IPU1_DI1_PIN06,	0x0410, 0x00FC, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_CS1__ECSPI2_MOSI,	0x0410, 0x00FC, 2, 0x0818, 0, 0)
+MX6_PAD_DECL(EIM_CS1__GPIO2_IO24,	0x0410, 0x00FC, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_OE__EIM_OE_B,	0x0414, 0x0100, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_OE__IPU1_DI1_PIN07,	0x0414, 0x0100, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_OE__ECSPI2_MISO,	0x0414, 0x0100, 2, 0x0814, 0, 0)
+MX6_PAD_DECL(EIM_OE__GPIO2_IO25,	0x0414, 0x0100, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_RW__EIM_RW,	0x0418, 0x0104, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_RW__IPU1_DI1_PIN08,	0x0418, 0x0104, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_RW__ECSPI2_SS0,	0x0418, 0x0104, 2, 0x081C, 0, 0)
+MX6_PAD_DECL(EIM_RW__GPIO2_IO26,	0x0418, 0x0104, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_RW__SRC_BOOT_CFG29,	0x0418, 0x0104, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_LBA__EIM_LBA_B,	0x041C, 0x0108, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_LBA__IPU1_DI1_PIN17,	0x041C, 0x0108, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_LBA__ECSPI2_SS1,	0x041C, 0x0108, 2, 0x0820, 0, 0)
+MX6_PAD_DECL(EIM_LBA__GPIO2_IO27,	0x041C, 0x0108, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_LBA__SRC_BOOT_CFG26,	0x041C, 0x0108, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_EB0__EIM_EB0_B,	0x0420, 0x010C, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_EB0__IPU1_DISP1_DATA11,	0x0420, 0x010C, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_EB0__IPU2_CSI1_DATA11,	0x0420, 0x010C, 2, 0x08B4, 1, 0)
+MX6_PAD_DECL(EIM_EB0__CCM_PMIC_READY,	0x0420, 0x010C, 4, 0x07F0, 0, 0)
+MX6_PAD_DECL(EIM_EB0__GPIO2_IO28,	0x0420, 0x010C, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_EB0__SRC_BOOT_CFG27,	0x0420, 0x010C, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_EB1__EIM_EB1_B,	0x0424, 0x0110, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_EB1__IPU1_DISP1_DATA10,	0x0424, 0x0110, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_EB1__IPU2_CSI1_DATA10,	0x0424, 0x0110, 2, 0x08B0, 1, 0)
+MX6_PAD_DECL(EIM_EB1__GPIO2_IO29,	0x0424, 0x0110, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_EB1__SRC_BOOT_CFG28,	0x0424, 0x0110, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA0__EIM_AD00,	0x0428, 0x0114, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA0__IPU1_DISP1_DATA09,	0x0428, 0x0114, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA0__IPU2_CSI1_DATA09,	0x0428, 0x0114, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA0__GPIO3_IO00,	0x0428, 0x0114, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA0__SRC_BOOT_CFG00,	0x0428, 0x0114, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA1__EIM_AD01,	0x042C, 0x0118, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA1__IPU1_DISP1_DATA08,	0x042C, 0x0118, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA1__IPU2_CSI1_DATA08,	0x042C, 0x0118, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA1__GPIO3_IO01,	0x042C, 0x0118, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA1__SRC_BOOT_CFG01,	0x042C, 0x0118, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA2__EIM_AD02,	0x0430, 0x011C, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA2__IPU1_DISP1_DATA07,	0x0430, 0x011C, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA2__IPU2_CSI1_DATA07,	0x0430, 0x011C, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA2__GPIO3_IO02,	0x0430, 0x011C, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA2__SRC_BOOT_CFG02,	0x0430, 0x011C, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA3__EIM_AD03,	0x0434, 0x0120, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA3__IPU1_DISP1_DATA06,	0x0434, 0x0120, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA3__IPU2_CSI1_DATA06,	0x0434, 0x0120, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA3__GPIO3_IO03,	0x0434, 0x0120, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA3__SRC_BOOT_CFG03,	0x0434, 0x0120, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA4__EIM_AD04,	0x0438, 0x0124, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA4__IPU1_DISP1_DATA05,	0x0438, 0x0124, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA4__IPU2_CSI1_DATA05,	0x0438, 0x0124, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA4__GPIO3_IO04,	0x0438, 0x0124, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA4__SRC_BOOT_CFG04,	0x0438, 0x0124, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA5__EIM_AD05,	0x043C, 0x0128, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA5__IPU1_DISP1_DATA04,	0x043C, 0x0128, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA5__IPU2_CSI1_DATA04,	0x043C, 0x0128, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA5__GPIO3_IO05,	0x043C, 0x0128, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA5__SRC_BOOT_CFG05,	0x043C, 0x0128, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA6__EIM_AD06,	0x0440, 0x012C, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA6__IPU1_DISP1_DATA03,	0x0440, 0x012C, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA6__IPU2_CSI1_DATA03,	0x0440, 0x012C, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA6__GPIO3_IO06,	0x0440, 0x012C, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA6__SRC_BOOT_CFG06,	0x0440, 0x012C, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA7__EIM_AD07,	0x0444, 0x0130, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA7__IPU1_DISP1_DATA02,	0x0444, 0x0130, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA7__IPU2_CSI1_DATA02,	0x0444, 0x0130, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA7__GPIO3_IO07,	0x0444, 0x0130, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA7__SRC_BOOT_CFG07,	0x0444, 0x0130, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA8__EIM_AD08,	0x0448, 0x0134, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA8__IPU1_DISP1_DATA01,	0x0448, 0x0134, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA8__IPU2_CSI1_DATA01,	0x0448, 0x0134, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA8__GPIO3_IO08,	0x0448, 0x0134, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA8__SRC_BOOT_CFG08,	0x0448, 0x0134, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA9__EIM_AD09,	0x044C, 0x0138, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA9__IPU1_DISP1_DATA00,	0x044C, 0x0138, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA9__IPU2_CSI1_DATA00,	0x044C, 0x0138, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA9__GPIO3_IO09,	0x044C, 0x0138, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA9__SRC_BOOT_CFG09,	0x044C, 0x0138, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA10__EIM_AD10,	0x0450, 0x013C, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA10__IPU1_DI1_PIN15,	0x0450, 0x013C, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA10__IPU2_CSI1_DATA_EN,	0x0450, 0x013C, 2, 0x08D8, 1, 0)
+MX6_PAD_DECL(EIM_DA10__GPIO3_IO10,	0x0450, 0x013C, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA10__SRC_BOOT_CFG10,	0x0450, 0x013C, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA11__EIM_AD11,	0x0454, 0x0140, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA11__IPU1_DI1_PIN02,	0x0454, 0x0140, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA11__IPU2_CSI1_HSYNC,	0x0454, 0x0140, 2, 0x08DC, 1, 0)
+MX6_PAD_DECL(EIM_DA11__GPIO3_IO11,	0x0454, 0x0140, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA11__SRC_BOOT_CFG11,	0x0454, 0x0140, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA12__EIM_AD12,	0x0458, 0x0144, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA12__IPU1_DI1_PIN03,	0x0458, 0x0144, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA12__IPU2_CSI1_VSYNC,	0x0458, 0x0144, 2, 0x08E4, 1, 0)
+MX6_PAD_DECL(EIM_DA12__GPIO3_IO12,	0x0458, 0x0144, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA12__SRC_BOOT_CFG12,	0x0458, 0x0144, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA13__EIM_AD13,	0x045C, 0x0148, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA13__IPU1_DI1_D0_CS,	0x045C, 0x0148, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA13__GPIO3_IO13,	0x045C, 0x0148, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA13__SRC_BOOT_CFG13,	0x045C, 0x0148, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA14__EIM_AD14,	0x0460, 0x014C, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA14__IPU1_DI1_D1_CS,	0x0460, 0x014C, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA14__GPIO3_IO14,	0x0460, 0x014C, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA14__SRC_BOOT_CFG14,	0x0460, 0x014C, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA15__EIM_AD15,	0x0464, 0x0150, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA15__IPU1_DI1_PIN01,	0x0464, 0x0150, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA15__IPU1_DI1_PIN04,	0x0464, 0x0150, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA15__GPIO3_IO15,	0x0464, 0x0150, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA15__SRC_BOOT_CFG15,	0x0464, 0x0150, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_WAIT__EIM_WAIT_B,	0x0468, 0x0154, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_WAIT__EIM_DTACK_B,	0x0468, 0x0154, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_WAIT__GPIO5_IO00,	0x0468, 0x0154, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_WAIT__SRC_BOOT_CFG25,	0x0468, 0x0154, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_BCLK__EIM_BCLK,	0x046C, 0x0158, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_BCLK__IPU1_DI1_PIN16,	0x046C, 0x0158, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_BCLK__GPIO6_IO31,	0x046C, 0x0158, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(DI0_DISP_CLK__IPU1_DI0_DISP_CLK,	0x0470, 0x015C, 0, 0x0000, 0, PAD_CTL_DSE_120ohm)
+MX6_PAD_DECL(DI0_DISP_CLK__IPU2_DI0_DISP_CLK,	0x0470, 0x015C, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(DI0_DISP_CLK__GPIO4_IO16,	0x0470, 0x015C, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(DI0_PIN15__IPU1_DI0_PIN15,	0x0474, 0x0160, 0, 0x0000, 0, PAD_CTL_DSE_120ohm)
+MX6_PAD_DECL(DI0_PIN15__IPU2_DI0_PIN15,	0x0474, 0x0160, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(DI0_PIN15__AUD6_TXC,	0x0474, 0x0160, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(DI0_PIN15__GPIO4_IO17,	0x0474, 0x0160, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(DI0_PIN2__IPU1_DI0_PIN02,	0x0478, 0x0164, 0, 0x0000, 0, PAD_CTL_DSE_120ohm)
+MX6_PAD_DECL(DI0_PIN2__IPU2_DI0_PIN02,	0x0478, 0x0164, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(DI0_PIN2__AUD6_TXD,	0x0478, 0x0164, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(DI0_PIN2__GPIO4_IO18,	0x0478, 0x0164, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(DI0_PIN3__IPU1_DI0_PIN03,	0x047C, 0x0168, 0, 0x0000, 0, PAD_CTL_DSE_120ohm)
+MX6_PAD_DECL(DI0_PIN3__IPU2_DI0_PIN03,	0x047C, 0x0168, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(DI0_PIN3__AUD6_TXFS,	0x047C, 0x0168, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(DI0_PIN3__GPIO4_IO19,	0x047C, 0x0168, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(DI0_PIN4__IPU1_DI0_PIN04,	0x0480, 0x016C, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(DI0_PIN4__IPU2_DI0_PIN04,	0x0480, 0x016C, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(DI0_PIN4__AUD6_RXD,	0x0480, 0x016C, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(DI0_PIN4__SD1_WP,	0x0480, 0x016C, 3, 0x094C, 0, 0)
+MX6_PAD_DECL(DI0_PIN4__GPIO4_IO20,	0x0480, 0x016C, 5, 0x0000, 0, PAD_CTL_DSE_120ohm)
+MX6_PAD_DECL(DISP0_DAT0__IPU1_DISP0_DATA00,	0x0484, 0x0170, 0, 0x0000, 0, PAD_CTL_DSE_120ohm)
+MX6_PAD_DECL(DISP0_DAT0__IPU2_DISP0_DATA00,	0x0484, 0x0170, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT0__ECSPI3_SCLK,	0x0484, 0x0170, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT0__GPIO4_IO21,	0x0484, 0x0170, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT1__IPU1_DISP0_DATA01,	0x0488, 0x0174, 0, 0x0000, 0, PAD_CTL_DSE_120ohm)
+MX6_PAD_DECL(DISP0_DAT1__IPU2_DISP0_DATA01,	0x0488, 0x0174, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT1__ECSPI3_MOSI,	0x0488, 0x0174, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT1__GPIO4_IO22,	0x0488, 0x0174, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT2__IPU1_DISP0_DATA02,	0x048C, 0x0178, 0, 0x0000, 0, PAD_CTL_DSE_120ohm)
+MX6_PAD_DECL(DISP0_DAT2__IPU2_DISP0_DATA02,	0x048C, 0x0178, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT2__ECSPI3_MISO,	0x048C, 0x0178, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT2__GPIO4_IO23,	0x048C, 0x0178, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT3__IPU1_DISP0_DATA03,	0x0490, 0x017C, 0, 0x0000, 0, PAD_CTL_DSE_120ohm)
+MX6_PAD_DECL(DISP0_DAT3__IPU2_DISP0_DATA03,	0x0490, 0x017C, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT3__ECSPI3_SS0,	0x0490, 0x017C, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT3__GPIO4_IO24,	0x0490, 0x017C, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT4__IPU1_DISP0_DATA04,	0x0494, 0x0180, 0, 0x0000, 0, PAD_CTL_DSE_120ohm)
+MX6_PAD_DECL(DISP0_DAT4__IPU2_DISP0_DATA04,	0x0494, 0x0180, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT4__ECSPI3_SS1,	0x0494, 0x0180, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT4__GPIO4_IO25,	0x0494, 0x0180, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT5__IPU1_DISP0_DATA05,	0x0498, 0x0184, 0, 0x0000, 0, PAD_CTL_DSE_120ohm)
+MX6_PAD_DECL(DISP0_DAT5__IPU2_DISP0_DATA05,	0x0498, 0x0184, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT5__ECSPI3_SS2,	0x0498, 0x0184, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT5__AUD6_RXFS,	0x0498, 0x0184, 3, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT5__GPIO4_IO26,	0x0498, 0x0184, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT6__IPU1_DISP0_DATA06,	0x049C, 0x0188, 0, 0x0000, 0, PAD_CTL_DSE_120ohm)
+MX6_PAD_DECL(DISP0_DAT6__IPU2_DISP0_DATA06,	0x049C, 0x0188, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT6__ECSPI3_SS3,	0x049C, 0x0188, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT6__AUD6_RXC,	0x049C, 0x0188, 3, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT6__GPIO4_IO27,	0x049C, 0x0188, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT7__IPU1_DISP0_DATA07,	0x04A0, 0x018C, 0, 0x0000, 0, PAD_CTL_DSE_120ohm)
+MX6_PAD_DECL(DISP0_DAT7__IPU2_DISP0_DATA07,	0x04A0, 0x018C, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT7__ECSPI3_RDY,	0x04A0, 0x018C, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT7__GPIO4_IO28,	0x04A0, 0x018C, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT8__IPU1_DISP0_DATA08,	0x04A4, 0x0190, 0, 0x0000, 0, PAD_CTL_DSE_120ohm)
+MX6_PAD_DECL(DISP0_DAT8__IPU2_DISP0_DATA08,	0x04A4, 0x0190, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT8__PWM1_OUT,	0x04A4, 0x0190, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT8__WDOG1_B,	0x04A4, 0x0190, 3, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT8__GPIO4_IO29,	0x04A4, 0x0190, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT9__IPU1_DISP0_DATA09,	0x04A8, 0x0194, 0, 0x0000, 0, PAD_CTL_DSE_120ohm)
+MX6_PAD_DECL(DISP0_DAT9__IPU2_DISP0_DATA09,	0x04A8, 0x0194, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT9__PWM2_OUT,	0x04A8, 0x0194, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT9__WDOG2_B,	0x04A8, 0x0194, 3, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT9__GPIO4_IO30,	0x04A8, 0x0194, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT10__IPU1_DISP0_DATA10,	0x04AC, 0x0198, 0, 0x0000, 0, PAD_CTL_DSE_120ohm)
+MX6_PAD_DECL(DISP0_DAT10__IPU2_DISP0_DATA10,	0x04AC, 0x0198, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT10__GPIO4_IO31,	0x04AC, 0x0198, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT11__IPU1_DISP0_DATA11,	0x04B0, 0x019C, 0, 0x0000, 0, PAD_CTL_DSE_120ohm)
+MX6_PAD_DECL(DISP0_DAT11__IPU2_DISP0_DATA11,	0x04B0, 0x019C, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT11__GPIO5_IO05,	0x04B0, 0x019C, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT12__IPU1_DISP0_DATA12,	0x04B4, 0x01A0, 0, 0x0000, 0, PAD_CTL_DSE_120ohm)
+MX6_PAD_DECL(DISP0_DAT12__IPU2_DISP0_DATA12,	0x04B4, 0x01A0, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT12__GPIO5_IO06,	0x04B4, 0x01A0, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT13__IPU1_DISP0_DATA13,	0x04B8, 0x01A4, 0, 0x0000, 0, PAD_CTL_DSE_120ohm)
+MX6_PAD_DECL(DISP0_DAT13__IPU2_DISP0_DATA13,	0x04B8, 0x01A4, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT13__AUD5_RXFS,	0x04B8, 0x01A4, 3, 0x07D8, 1, 0)
+MX6_PAD_DECL(DISP0_DAT13__GPIO5_IO07,	0x04B8, 0x01A4, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT14__IPU1_DISP0_DATA14,	0x04BC, 0x01A8, 0, 0x0000, 0, PAD_CTL_DSE_120ohm)
+MX6_PAD_DECL(DISP0_DAT14__IPU2_DISP0_DATA14,	0x04BC, 0x01A8, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT14__AUD5_RXC,	0x04BC, 0x01A8, 3, 0x07D4, 1, 0)
+MX6_PAD_DECL(DISP0_DAT14__GPIO5_IO08,	0x04BC, 0x01A8, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT15__IPU1_DISP0_DATA15,	0x04C0, 0x01AC, 0, 0x0000, 0, PAD_CTL_DSE_120ohm)
+MX6_PAD_DECL(DISP0_DAT15__IPU2_DISP0_DATA15,	0x04C0, 0x01AC, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT15__ECSPI1_SS1,	0x04C0, 0x01AC, 2, 0x0804, 1, 0)
+MX6_PAD_DECL(DISP0_DAT15__ECSPI2_SS1,	0x04C0, 0x01AC, 3, 0x0820, 1, 0)
+MX6_PAD_DECL(DISP0_DAT15__GPIO5_IO09,	0x04C0, 0x01AC, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT16__IPU1_DISP0_DATA16,	0x04C4, 0x01B0, 0, 0x0000, 0, PAD_CTL_DSE_120ohm)
+MX6_PAD_DECL(DISP0_DAT16__IPU2_DISP0_DATA16,	0x04C4, 0x01B0, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT16__ECSPI2_MOSI,	0x04C4, 0x01B0, 2, 0x0818, 1, 0)
+MX6_PAD_DECL(DISP0_DAT16__AUD5_TXC,	0x04C4, 0x01B0, 3, 0x07DC, 0, 0)
+MX6_PAD_DECL(DISP0_DAT16__SDMA_EXT_EVENT0,	0x04C4, 0x01B0, 4, 0x090C, 0, 0)
+MX6_PAD_DECL(DISP0_DAT16__GPIO5_IO10,	0x04C4, 0x01B0, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT17__IPU1_DISP0_DATA17,	0x04C8, 0x01B4, 0, 0x0000, 0, PAD_CTL_DSE_120ohm)
+MX6_PAD_DECL(DISP0_DAT17__IPU2_DISP0_DATA17,	0x04C8, 0x01B4, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT17__ECSPI2_MISO,	0x04C8, 0x01B4, 2, 0x0814, 1, 0)
+MX6_PAD_DECL(DISP0_DAT17__AUD5_TXD,	0x04C8, 0x01B4, 3, 0x07D0, 0, 0)
+MX6_PAD_DECL(DISP0_DAT17__SDMA_EXT_EVENT1,	0x04C8, 0x01B4, 4, 0x0910, 0, 0)
+MX6_PAD_DECL(DISP0_DAT17__GPIO5_IO11,	0x04C8, 0x01B4, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT18__IPU1_DISP0_DATA18,	0x04CC, 0x01B8, 0, 0x0000, 0, PAD_CTL_DSE_120ohm)
+MX6_PAD_DECL(DISP0_DAT18__IPU2_DISP0_DATA18,	0x04CC, 0x01B8, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT18__ECSPI2_SS0,	0x04CC, 0x01B8, 2, 0x081C, 1, 0)
+MX6_PAD_DECL(DISP0_DAT18__AUD5_TXFS,	0x04CC, 0x01B8, 3, 0x07E0, 0, 0)
+MX6_PAD_DECL(DISP0_DAT18__AUD4_RXFS,	0x04CC, 0x01B8, 4, 0x07C0, 0, 0)
+MX6_PAD_DECL(DISP0_DAT18__GPIO5_IO12,	0x04CC, 0x01B8, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT18__EIM_CS2_B,	0x04CC, 0x01B8, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT19__IPU1_DISP0_DATA19,	0x04D0, 0x01BC, 0, 0x0000, 0, PAD_CTL_DSE_120ohm)
+MX6_PAD_DECL(DISP0_DAT19__IPU2_DISP0_DATA19,	0x04D0, 0x01BC, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT19__ECSPI2_SCLK,	0x04D0, 0x01BC, 2, 0x0810, 1, 0)
+MX6_PAD_DECL(DISP0_DAT19__AUD5_RXD,	0x04D0, 0x01BC, 3, 0x07CC, 0, 0)
+MX6_PAD_DECL(DISP0_DAT19__AUD4_RXC,	0x04D0, 0x01BC, 4, 0x07BC, 0, 0)
+MX6_PAD_DECL(DISP0_DAT19__GPIO5_IO13,	0x04D0, 0x01BC, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT19__EIM_CS3_B,	0x04D0, 0x01BC, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT20__IPU1_DISP0_DATA20,	0x04D4, 0x01C0, 0, 0x0000, 0, PAD_CTL_DSE_120ohm)
+MX6_PAD_DECL(DISP0_DAT20__IPU2_DISP0_DATA20,	0x04D4, 0x01C0, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT20__ECSPI1_SCLK,	0x04D4, 0x01C0, 2, 0x07F4, 1, 0)
+MX6_PAD_DECL(DISP0_DAT20__AUD4_TXC,	0x04D4, 0x01C0, 3, 0x07C4, 0, 0)
+MX6_PAD_DECL(DISP0_DAT20__GPIO5_IO14,	0x04D4, 0x01C0, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT21__IPU1_DISP0_DATA21,	0x04D8, 0x01C4, 0, 0x0000, 0, PAD_CTL_DSE_120ohm)
+MX6_PAD_DECL(DISP0_DAT21__IPU2_DISP0_DATA21,	0x04D8, 0x01C4, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT21__ECSPI1_MOSI,	0x04D8, 0x01C4, 2, 0x07FC, 1, 0)
+MX6_PAD_DECL(DISP0_DAT21__AUD4_TXD,	0x04D8, 0x01C4, 3, 0x07B8, 1, 0)
+MX6_PAD_DECL(DISP0_DAT21__GPIO5_IO15,	0x04D8, 0x01C4, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT22__IPU1_DISP0_DATA22,	0x04DC, 0x01C8, 0, 0x0000, 0, PAD_CTL_DSE_120ohm)
+MX6_PAD_DECL(DISP0_DAT22__IPU2_DISP0_DATA22,	0x04DC, 0x01C8, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT22__ECSPI1_MISO,	0x04DC, 0x01C8, 2, 0x07F8, 1, 0)
+MX6_PAD_DECL(DISP0_DAT22__AUD4_TXFS,	0x04DC, 0x01C8, 3, 0x07C8, 1, 0)
+MX6_PAD_DECL(DISP0_DAT22__GPIO5_IO16,	0x04DC, 0x01C8, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT23__IPU1_DISP0_DATA23,	0x04E0, 0x01CC, 0, 0x0000, 0, PAD_CTL_DSE_120ohm)
+MX6_PAD_DECL(DISP0_DAT23__IPU2_DISP0_DATA23,	0x04E0, 0x01CC, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT23__ECSPI1_SS0,	0x04E0, 0x01CC, 2, 0x0800, 1, 0)
+MX6_PAD_DECL(DISP0_DAT23__AUD4_RXD,	0x04E0, 0x01CC, 3, 0x07B4, 1, 0)
+MX6_PAD_DECL(DISP0_DAT23__GPIO5_IO17,	0x04E0, 0x01CC, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(ENET_MDIO__ENET_MDIO,	0x04E4, 0x01D0, 1, 0x0840, 0, 0)
+MX6_PAD_DECL(ENET_MDIO__ESAI_RX_CLK,	0x04E4, 0x01D0, 2, 0x086C, 0, 0)
+MX6_PAD_DECL(ENET_MDIO__ENET_1588_EVENT1_OUT,	0x04E4, 0x01D0, 4, 0x0000, 0, 0)
+MX6_PAD_DECL(ENET_MDIO__GPIO1_IO22,	0x04E4, 0x01D0, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(ENET_MDIO__SPDIF_LOCK,	0x04E4, 0x01D0, 6, 0x0000, 0, 0)
+MX6_PAD_DECL(ENET_REF_CLK__ENET_TX_CLK,	0x04E8, 0x01D4, 1 | IOMUX_CONFIG_SION, 0x0000, 0, 0)
+MX6_PAD_DECL(ENET_REF_CLK__ESAI_RX_FS,	0x04E8, 0x01D4, 2, 0x085C, 0, 0)
+MX6_PAD_DECL(ENET_REF_CLK__GPIO1_IO23,	0x04E8, 0x01D4, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(ENET_REF_CLK__SPDIF_SR_CLK,	0x04E8, 0x01D4, 6, 0x0000, 0, 0)
+MX6_PAD_DECL(ENET_RX_ER__USB_OTG_ID,	0x04EC, 0x01D8, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(ENET_RX_ER__ENET_RX_ER,	0x04EC, 0x01D8, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(ENET_RX_ER__ESAI_RX_HF_CLK,	0x04EC, 0x01D8, 2, 0x0864, 0, 0)
+MX6_PAD_DECL(ENET_RX_ER__SPDIF_IN,	0x04EC, 0x01D8, 3, 0x0914, 1, 0)
+MX6_PAD_DECL(ENET_RX_ER__ENET_1588_EVENT2_OUT,	0x04EC, 0x01D8, 4, 0x0000, 0, 0)
+MX6_PAD_DECL(ENET_RX_ER__GPIO1_IO24,	0x04EC, 0x01D8, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(ENET_CRS_DV__ENET_RX_EN,	0x04F0, 0x01DC, 1, 0x0858, 1, 0)
+MX6_PAD_DECL(ENET_CRS_DV__ESAI_TX_CLK,	0x04F0, 0x01DC, 2, 0x0870, 0, 0)
+MX6_PAD_DECL(ENET_CRS_DV__SPDIF_EXT_CLK,	0x04F0, 0x01DC, 3, 0x0918, 1, 0)
+MX6_PAD_DECL(ENET_CRS_DV__GPIO1_IO25,	0x04F0, 0x01DC, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(ENET_RXD1__MLB_SIG,	0x04F4, 0x01E0, 0, 0x0908, 0, 0)
+MX6_PAD_DECL(ENET_RXD1__ENET_RX_DATA1,	0x04F4, 0x01E0, 1, 0x084C, 1, 0)
+MX6_PAD_DECL(ENET_RXD1__ESAI_TX_FS,	0x04F4, 0x01E0, 2, 0x0860, 0, 0)
+MX6_PAD_DECL(ENET_RXD1__ENET_1588_EVENT3_OUT,	0x04F4, 0x01E0, 4, 0x0000, 0, 0)
+MX6_PAD_DECL(ENET_RXD1__GPIO1_IO26,	0x04F4, 0x01E0, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(ENET_RXD0__ENET_RX_DATA0,	0x04F8, 0x01E4, 1, 0x0848, 1, 0)
+MX6_PAD_DECL(ENET_RXD0__ESAI_TX_HF_CLK,	0x04F8, 0x01E4, 2, 0x0868, 0, 0)
+MX6_PAD_DECL(ENET_RXD0__SPDIF_OUT,	0x04F8, 0x01E4, 3, 0x0000, 0, 0)
+MX6_PAD_DECL(ENET_RXD0__GPIO1_IO27,	0x04F8, 0x01E4, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(ENET_TX_EN__ENET_TX_EN,	0x04FC, 0x01E8, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(ENET_TX_EN__ESAI_TX3_RX2,	0x04FC, 0x01E8, 2, 0x0880, 0, 0)
+MX6_PAD_DECL(ENET_TX_EN__GPIO1_IO28,	0x04FC, 0x01E8, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(ENET_TXD1__MLB_CLK,	0x0500, 0x01EC, 0, 0x0900, 0, 0)
+MX6_PAD_DECL(ENET_TXD1__ENET_TX_DATA1,	0x0500, 0x01EC, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(ENET_TXD1__ESAI_TX2_RX3,	0x0500, 0x01EC, 2, 0x087C, 0, 0)
+MX6_PAD_DECL(ENET_TXD1__ENET_1588_EVENT0_IN,	0x0500, 0x01EC, 4, 0x0000, 0, 0)
+MX6_PAD_DECL(ENET_TXD1__GPIO1_IO29,	0x0500, 0x01EC, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(ENET_TXD0__ENET_TX_DATA0,	0x0504, 0x01F0, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(ENET_TXD0__ESAI_TX4_RX1,	0x0504, 0x01F0, 2, 0x0884, 0, 0)
+MX6_PAD_DECL(ENET_TXD0__GPIO1_IO30,	0x0504, 0x01F0, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(ENET_MDC__MLB_DATA,	0x0508, 0x01F4, 0, 0x0904, 0, 0)
+MX6_PAD_DECL(ENET_MDC__ENET_MDC,	0x0508, 0x01F4, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(ENET_MDC__ESAI_TX5_RX0,	0x0508, 0x01F4, 2, 0x0888, 0, 0)
+MX6_PAD_DECL(ENET_MDC__ENET_1588_EVENT1_IN,	0x0508, 0x01F4, 4, 0x0000, 0, 0)
+MX6_PAD_DECL(ENET_MDC__GPIO1_IO31,	0x0508, 0x01F4, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(KEY_COL0__ECSPI1_SCLK,	0x05C8, 0x01F8, 0, 0x07F4, 2, 0)
+MX6_PAD_DECL(KEY_COL0__ENET_RX_DATA3,	0x05C8, 0x01F8, 1, 0x0854, 1, 0)
+MX6_PAD_DECL(KEY_COL0__AUD5_TXC,	0x05C8, 0x01F8, 2, 0x07DC, 1, 0)
+MX6_PAD_DECL(KEY_COL0__KEY_COL0,	0x05C8, 0x01F8, 3, 0x0000, 0, 0)
+MX6_PAD_DECL(KEY_COL0__UART4_TX_DATA,	0x05C8, 0x01F8, 4, 0x0000, 0, 0)
+MX6_PAD_DECL(KEY_COL0__UART4_RX_DATA,	0x05C8, 0x01F8, 4, 0x0938, 0, 0)
+MX6_PAD_DECL(KEY_COL0__GPIO4_IO06,	0x05C8, 0x01F8, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(KEY_COL0__DCIC1_OUT,	0x05C8, 0x01F8, 6, 0x0000, 0, 0)
+MX6_PAD_DECL(KEY_ROW0__ECSPI1_MOSI,	0x05CC, 0x01FC, 0, 0x07FC, 2, 0)
+MX6_PAD_DECL(KEY_ROW0__ENET_TX_DATA3,	0x05CC, 0x01FC, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(KEY_ROW0__AUD5_TXD,	0x05CC, 0x01FC, 2, 0x07D0, 1, 0)
+MX6_PAD_DECL(KEY_ROW0__KEY_ROW0,	0x05CC, 0x01FC, 3, 0x0000, 0, 0)
+MX6_PAD_DECL(KEY_ROW0__UART4_TX_DATA,	0x05CC, 0x01FC, 4, 0x0000, 0, 0)
+MX6_PAD_DECL(KEY_ROW0__UART4_RX_DATA,	0x05CC, 0x01FC, 4, 0x0938, 1, 0)
+MX6_PAD_DECL(KEY_ROW0__GPIO4_IO07,	0x05CC, 0x01FC, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(KEY_ROW0__DCIC2_OUT,	0x05CC, 0x01FC, 6, 0x0000, 0, 0)
+MX6_PAD_DECL(KEY_COL1__ECSPI1_MISO,	0x05D0, 0x0200, 0, 0x07F8, 2, 0)
+MX6_PAD_DECL(KEY_COL1__ENET_MDIO,	0x05D0, 0x0200, 1, 0x0840, 1, 0)
+MX6_PAD_DECL(KEY_COL1__AUD5_TXFS,	0x05D0, 0x0200, 2, 0x07E0, 1, 0)
+MX6_PAD_DECL(KEY_COL1__KEY_COL1,	0x05D0, 0x0200, 3, 0x0000, 0, 0)
+MX6_PAD_DECL(KEY_COL1__UART5_TX_DATA,	0x05D0, 0x0200, 4, 0x0000, 0, 0)
+MX6_PAD_DECL(KEY_COL1__UART5_RX_DATA,	0x05D0, 0x0200, 4, 0x0940, 0, 0)
+MX6_PAD_DECL(KEY_COL1__GPIO4_IO08,	0x05D0, 0x0200, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(KEY_COL1__SD1_VSELECT,	0x05D0, 0x0200, 6, 0x0000, 0, 0)
+MX6_PAD_DECL(KEY_ROW1__ECSPI1_SS0,	0x05D4, 0x0204, 0, 0x0800, 2, 0)
+MX6_PAD_DECL(KEY_ROW1__ENET_COL,	0x05D4, 0x0204, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(KEY_ROW1__AUD5_RXD,	0x05D4, 0x0204, 2, 0x07CC, 1, 0)
+MX6_PAD_DECL(KEY_ROW1__KEY_ROW1,	0x05D4, 0x0204, 3, 0x0000, 0, 0)
+MX6_PAD_DECL(KEY_ROW1__UART5_TX_DATA,	0x05D4, 0x0204, 4, 0x0000, 0, 0)
+MX6_PAD_DECL(KEY_ROW1__UART5_RX_DATA,	0x05D4, 0x0204, 4, 0x0940, 1, 0)
+MX6_PAD_DECL(KEY_ROW1__GPIO4_IO09,	0x05D4, 0x0204, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(KEY_ROW1__SD2_VSELECT,	0x05D4, 0x0204, 6, 0x0000, 0, 0)
+MX6_PAD_DECL(KEY_COL2__ECSPI1_SS1,	0x05D8, 0x0208, 0, 0x0804, 2, 0)
+MX6_PAD_DECL(KEY_COL2__ENET_RX_DATA2,	0x05D8, 0x0208, 1, 0x0850, 1, 0)
+MX6_PAD_DECL(KEY_COL2__FLEXCAN1_TX,	0x05D8, 0x0208, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(KEY_COL2__KEY_COL2,	0x05D8, 0x0208, 3, 0x0000, 0, 0)
+MX6_PAD_DECL(KEY_COL2__ENET_MDC,	0x05D8, 0x0208, 4, 0x0000, 0, 0)
+MX6_PAD_DECL(KEY_COL2__GPIO4_IO10,	0x05D8, 0x0208, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(KEY_COL2__USB_H1_PWR_CTL_WAKE,	0x05D8, 0x0208, 6, 0x0000, 0, 0)
+MX6_PAD_DECL(KEY_ROW2__ECSPI1_SS2,	0x05DC, 0x020C, 0, 0x0808, 1, 0)
+MX6_PAD_DECL(KEY_ROW2__ENET_TX_DATA2,	0x05DC, 0x020C, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(KEY_ROW2__FLEXCAN1_RX,	0x05DC, 0x020C, 2, 0x07E4, 0, 0)
+MX6_PAD_DECL(KEY_ROW2__KEY_ROW2,	0x05DC, 0x020C, 3, 0x0000, 0, 0)
+MX6_PAD_DECL(KEY_ROW2__SD2_VSELECT,	0x05DC, 0x020C, 4, 0x0000, 0, 0)
+MX6_PAD_DECL(KEY_ROW2__GPIO4_IO11,	0x05DC, 0x020C, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(KEY_ROW2__HDMI_TX_CEC_LINE,	0x05DC, 0x020C, 6, 0x088C, 1, 0)
+MX6_PAD_DECL(KEY_COL3__ECSPI1_SS3,	0x05E0, 0x0210, 0, 0x080C, 1, 0)
+MX6_PAD_DECL(KEY_COL3__ENET_CRS,	0x05E0, 0x0210, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(KEY_COL3__HDMI_TX_DDC_SCL,	0x05E0, 0x0210, 2, 0x0890, 1, 0)
+MX6_PAD_DECL(KEY_COL3__KEY_COL3,	0x05E0, 0x0210, 3, 0x0000, 0, 0)
+MX6_PAD_DECL(KEY_COL3__I2C2_SCL,	0x05E0, 0x0210, 20, 0x08A0, 1, 0)
+MX6_PAD_DECL(KEY_COL3__GPIO4_IO12,	0x05E0, 0x0210, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(KEY_COL3__SPDIF_IN,	0x05E0, 0x0210, 6, 0x0914, 2, 0)
+MX6_PAD_DECL(KEY_ROW3__ASRC_EXT_CLK,	0x05E4, 0x0214, 1, 0x07B0, 0, 0)
+MX6_PAD_DECL(KEY_ROW3__HDMI_TX_DDC_SDA,	0x05E4, 0x0214, 2, 0x0894, 1, 0)
+MX6_PAD_DECL(KEY_ROW3__KEY_ROW3,	0x05E4, 0x0214, 3, 0x0000, 0, 0)
+MX6_PAD_DECL(KEY_ROW3__I2C2_SDA,	0x05E4, 0x0214, 20, 0x08A4, 1, 0)
+MX6_PAD_DECL(KEY_ROW3__GPIO4_IO13,	0x05E4, 0x0214, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(KEY_ROW3__SD1_VSELECT,	0x05E4, 0x0214, 6, 0x0000, 0, 0)
+MX6_PAD_DECL(KEY_COL4__FLEXCAN2_TX,	0x05E8, 0x0218, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(KEY_COL4__IPU1_SISG4,	0x05E8, 0x0218, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(KEY_COL4__USB_OTG_OC,	0x05E8, 0x0218, 2, 0x0944, 1, 0)
+MX6_PAD_DECL(KEY_COL4__KEY_COL4,	0x05E8, 0x0218, 3, 0x0000, 0, 0)
+MX6_PAD_DECL(KEY_COL4__UART5_CTS_B,	0x05E8, 0x0218, 4, 0x0000, 0, 0)
+MX6_PAD_DECL(KEY_COL4__UART5_RTS_B,	0x05E8, 0x0218, 4, 0x093C, 0, 0)
+MX6_PAD_DECL(KEY_COL4__GPIO4_IO14,	0x05E8, 0x0218, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(KEY_ROW4__FLEXCAN2_RX,	0x05EC, 0x021C, 0, 0x07E8, 0, 0)
+MX6_PAD_DECL(KEY_ROW4__IPU1_SISG5,	0x05EC, 0x021C, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(KEY_ROW4__USB_OTG_PWR,	0x05EC, 0x021C, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(KEY_ROW4__KEY_ROW4,	0x05EC, 0x021C, 3, 0x0000, 0, 0)
+MX6_PAD_DECL(KEY_ROW4__UART5_CTS_B,	0x05EC, 0x021C, 4, 0x0000, 0, 0)
+MX6_PAD_DECL(KEY_ROW4__UART5_RTS_B,	0x05EC, 0x021C, 4, 0x093C, 1, 0)
+MX6_PAD_DECL(KEY_ROW4__GPIO4_IO15,	0x05EC, 0x021C, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(GPIO_0__CCM_CLKO1,	0x05F0, 0x0220, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(GPIO_0__KEY_COL5,	0x05F0, 0x0220, 2, 0x08E8, 0, 0)
+MX6_PAD_DECL(GPIO_0__ASRC_EXT_CLK,	0x05F0, 0x0220, 3, 0x07B0, 1, 0)
+MX6_PAD_DECL(GPIO_0__EPIT1_OUT,	0x05F0, 0x0220, 4, 0x0000, 0, 0)
+MX6_PAD_DECL(GPIO_0__GPIO1_IO00,	0x05F0, 0x0220, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(GPIO_0__USB_H1_PWR,	0x05F0, 0x0220, 6, 0x0000, 0, 0)
+MX6_PAD_DECL(GPIO_0__SNVS_VIO_5,	0x05F0, 0x0220, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(GPIO_1__ESAI_RX_CLK,	0x05F4, 0x0224, 0, 0x086C, 1, 0)
+MX6_PAD_DECL(GPIO_1__WDOG2_B,	0x05F4, 0x0224, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(GPIO_1__KEY_ROW5,	0x05F4, 0x0224, 2, 0x08F4, 0, 0)
+MX6_PAD_DECL(GPIO_1__USB_OTG_ID,	0x05F4, 0x0224, 3, 0x0000, 0, 0)
+MX6_PAD_DECL(GPIO_1__PWM2_OUT,	0x05F4, 0x0224, 4, 0x0000, 0, 0)
+MX6_PAD_DECL(GPIO_1__GPIO1_IO01,	0x05F4, 0x0224, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(GPIO_1__SD1_CD_B,	0x05F4, 0x0224, 6, 0x0000, 0, 0)
+MX6_PAD_DECL(GPIO_9__ESAI_RX_FS,	0x05F8, 0x0228, 0, 0x085C, 1, 0)
+MX6_PAD_DECL(GPIO_9__WDOG1_B,	0x05F8, 0x0228, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(GPIO_9__KEY_COL6,	0x05F8, 0x0228, 2, 0x08EC, 0, 0)
+MX6_PAD_DECL(GPIO_9__CCM_REF_EN_B,	0x05F8, 0x0228, 3, 0x0000, 0, 0)
+MX6_PAD_DECL(GPIO_9__PWM1_OUT,	0x05F8, 0x0228, 4, 0x0000, 0, 0)
+MX6_PAD_DECL(GPIO_9__GPIO1_IO09,	0x05F8, 0x0228, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(GPIO_9__SD1_WP,	0x05F8, 0x0228, 6, 0x094C, 1, 0)
+MX6_PAD_DECL(GPIO_3__ESAI_RX_HF_CLK,	0x05FC, 0x022C, 0, 0x0864, 1, 0)
+MX6_PAD_DECL(GPIO_3__I2C3_SCL,	0x05FC, 0x022C, 18, 0x08A8, 1, 0)
+MX6_PAD_DECL(GPIO_3__XTALOSC_REF_CLK_24M,	0x05FC, 0x022C, 3, 0x0000, 0, 0)
+MX6_PAD_DECL(GPIO_3__CCM_CLKO2,	0x05FC, 0x022C, 4, 0x0000, 0, 0)
+MX6_PAD_DECL(GPIO_3__GPIO1_IO03,	0x05FC, 0x022C, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(GPIO_3__USB_H1_OC,	0x05FC, 0x022C, 6, 0x0948, 1, 0)
+MX6_PAD_DECL(GPIO_3__MLB_CLK,	0x05FC, 0x022C, 7, 0x0900, 1, 0)
+MX6_PAD_DECL(GPIO_6__ESAI_TX_CLK,	0x0600, 0x0230, 0, 0x0870, 1, 0)
+MX6_PAD_DECL(GPIO_6__I2C3_SDA,	0x0600, 0x0230, 18, 0x08AC, 1, 0)
+MX6_PAD_DECL(GPIO_6__GPIO1_IO06,	0x0600, 0x0230, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(GPIO_6__SD2_LCTL,	0x0600, 0x0230, 6, 0x0000, 0, 0)
+MX6_PAD_DECL(GPIO_6__MLB_SIG,	0x0600, 0x0230, 7, 0x0908, 1, 0)
+MX6_PAD_DECL(GPIO_2__ESAI_TX_FS,	0x0604, 0x0234, 0, 0x0860, 1, 0)
+MX6_PAD_DECL(GPIO_2__KEY_ROW6,	0x0604, 0x0234, 2, 0x08F8, 1, 0)
+MX6_PAD_DECL(GPIO_2__GPIO1_IO02,	0x0604, 0x0234, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(GPIO_2__SD2_WP,	0x0604, 0x0234, 6, 0x0000, 0, 0)
+MX6_PAD_DECL(GPIO_2__MLB_DATA,	0x0604, 0x0234, 7, 0x0904, 1, 0)
+MX6_PAD_DECL(GPIO_4__ESAI_TX_HF_CLK,	0x0608, 0x0238, 0, 0x0868, 1, 0)
+MX6_PAD_DECL(GPIO_4__KEY_COL7,	0x0608, 0x0238, 2, 0x08F0, 1, 0)
+MX6_PAD_DECL(GPIO_4__GPIO1_IO04,	0x0608, 0x0238, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(GPIO_4__SD2_CD_B,	0x0608, 0x0238, 6, 0x0000, 0, 0)
+MX6_PAD_DECL(GPIO_5__ESAI_TX2_RX3,	0x060C, 0x023C, 0, 0x087C, 1, 0)
+MX6_PAD_DECL(GPIO_5__KEY_ROW7,	0x060C, 0x023C, 2, 0x08FC, 1, 0)
+MX6_PAD_DECL(GPIO_5__CCM_CLKO1,	0x060C, 0x023C, 3, 0x0000, 0, 0)
+MX6_PAD_DECL(GPIO_5__GPIO1_IO05,	0x060C, 0x023C, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(GPIO_5__I2C3_SCL,	0x060C, 0x023C, 22, 0x08A8, 2, 0)
+MX6_PAD_DECL(GPIO_5__ARM_EVENTI,	0x060C, 0x023C, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(GPIO_7__ESAI_TX4_RX1,	0x0610, 0x0240, 0, 0x0884, 1, 0)
+MX6_PAD_DECL(GPIO_7__ECSPI5_RDY,	0x0610, 0x0240, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(GPIO_7__EPIT1_OUT,	0x0610, 0x0240, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(GPIO_7__FLEXCAN1_TX,	0x0610, 0x0240, 3, 0x0000, 0, 0)
+MX6_PAD_DECL(GPIO_7__UART2_TX_DATA,	0x0610, 0x0240, 4, 0x0000, 0, 0)
+MX6_PAD_DECL(GPIO_7__UART2_RX_DATA,	0x0610, 0x0240, 4, 0x0928, 2, 0)
+MX6_PAD_DECL(GPIO_7__GPIO1_IO07,	0x0610, 0x0240, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(GPIO_7__SPDIF_LOCK,	0x0610, 0x0240, 6, 0x0000, 0, 0)
+MX6_PAD_DECL(GPIO_7__USB_OTG_HOST_MODE,	0x0610, 0x0240, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(GPIO_8__ESAI_TX5_RX0,	0x0614, 0x0244, 0, 0x0888, 1, 0)
+MX6_PAD_DECL(GPIO_8__XTALOSC_REF_CLK_32K,	0x0614, 0x0244, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(GPIO_8__EPIT2_OUT,	0x0614, 0x0244, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(GPIO_8__FLEXCAN1_RX,	0x0614, 0x0244, 3, 0x07E4, 1, 0)
+MX6_PAD_DECL(GPIO_8__UART2_TX_DATA,	0x0614, 0x0244, 4, 0x0000, 0, 0)
+MX6_PAD_DECL(GPIO_8__UART2_RX_DATA,	0x0614, 0x0244, 4, 0x0928, 3, 0)
+MX6_PAD_DECL(GPIO_8__GPIO1_IO08,	0x0614, 0x0244, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(GPIO_8__SPDIF_SR_CLK,	0x0614, 0x0244, 6, 0x0000, 0, 0)
+MX6_PAD_DECL(GPIO_8__USB_OTG_PWR_CTL_WAKE,	0x0614, 0x0244, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(GPIO_16__ESAI_TX3_RX2,	0x0618, 0x0248, 0, 0x0880, 1, 0)
+MX6_PAD_DECL(GPIO_16__ENET_1588_EVENT2_IN,	0x0618, 0x0248, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(GPIO_16__ENET_REF_CLK,	0x0618, 0x0248, 2 | IOMUX_CONFIG_SION, 0x083C, 1, 0)
+MX6_PAD_DECL(GPIO_16__SD1_LCTL,	0x0618, 0x0248, 3, 0x0000, 0, 0)
+MX6_PAD_DECL(GPIO_16__SPDIF_IN,	0x0618, 0x0248, 4, 0x0914, 3, 0)
+MX6_PAD_DECL(GPIO_16__GPIO7_IO11,	0x0618, 0x0248, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(GPIO_16__I2C3_SDA,	0x0618, 0x0248, 22, 0x08AC, 2, 0)
+MX6_PAD_DECL(GPIO_16__JTAG_DE_B,	0x0618, 0x0248, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(GPIO_17__ESAI_TX0,	0x061C, 0x024C, 0, 0x0874, 0, 0)
+MX6_PAD_DECL(GPIO_17__ENET_1588_EVENT3_IN,	0x061C, 0x024C, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(GPIO_17__CCM_PMIC_READY,	0x061C, 0x024C, 2, 0x07F0, 1, 0)
+MX6_PAD_DECL(GPIO_17__SDMA_EXT_EVENT0,	0x061C, 0x024C, 3, 0x090C, 1, 0)
+MX6_PAD_DECL(GPIO_17__SPDIF_OUT,	0x061C, 0x024C, 4, 0x0000, 0, 0)
+MX6_PAD_DECL(GPIO_17__GPIO7_IO12,	0x061C, 0x024C, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(GPIO_18__ESAI_TX1,	0x0620, 0x0250, 0, 0x0878, 0, 0)
+MX6_PAD_DECL(GPIO_18__ENET_RX_CLK,	0x0620, 0x0250, 1, 0x0844, 1, 0)
+MX6_PAD_DECL(GPIO_18__SD3_VSELECT,	0x0620, 0x0250, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(GPIO_18__SDMA_EXT_EVENT1,	0x0620, 0x0250, 3, 0x0910, 1, 0)
+MX6_PAD_DECL(GPIO_18__ASRC_EXT_CLK,	0x0620, 0x0250, 4, 0x07B0, 2, 0)
+MX6_PAD_DECL(GPIO_18__GPIO7_IO13,	0x0620, 0x0250, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(GPIO_18__SNVS_VIO_5_CTL,	0x0620, 0x0250, 6, 0x0000, 0, 0)
+MX6_PAD_DECL(GPIO_19__KEY_COL5,	0x0624, 0x0254, 0, 0x08E8, 1, 0)
+MX6_PAD_DECL(GPIO_19__ENET_1588_EVENT0_OUT,	0x0624, 0x0254, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(GPIO_19__SPDIF_OUT,	0x0624, 0x0254, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(GPIO_19__CCM_CLKO1,	0x0624, 0x0254, 3, 0x0000, 0, 0)
+MX6_PAD_DECL(GPIO_19__ECSPI1_RDY,	0x0624, 0x0254, 4, 0x0000, 0, 0)
+MX6_PAD_DECL(GPIO_19__GPIO4_IO05,	0x0624, 0x0254, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(GPIO_19__ENET_TX_ER,	0x0624, 0x0254, 6, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_PIXCLK__IPU1_CSI0_PIXCLK,	0x0628, 0x0258, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_PIXCLK__GPIO5_IO18,	0x0628, 0x0258, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_PIXCLK__ARM_EVENTO,	0x0628, 0x0258, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_MCLK__IPU1_CSI0_HSYNC,	0x062C, 0x025C, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_MCLK__CCM_CLKO1,	0x062C, 0x025C, 3, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_MCLK__GPIO5_IO19,	0x062C, 0x025C, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_MCLK__ARM_TRACE_CTL,	0x062C, 0x025C, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DATA_EN__IPU1_CSI0_DATA_EN,	0x0630, 0x0260, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DATA_EN__EIM_DATA00,	0x0630, 0x0260, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DATA_EN__GPIO5_IO20,	0x0630, 0x0260, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DATA_EN__ARM_TRACE_CLK,	0x0630, 0x0260, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_VSYNC__IPU1_CSI0_VSYNC,	0x0634, 0x0264, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_VSYNC__EIM_DATA01,	0x0634, 0x0264, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_VSYNC__GPIO5_IO21,	0x0634, 0x0264, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_VSYNC__ARM_TRACE00,	0x0634, 0x0264, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT4__IPU1_CSI0_DATA04,	0x0638, 0x0268, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT4__EIM_DATA02,	0x0638, 0x0268, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT4__ECSPI1_SCLK,	0x0638, 0x0268, 2, 0x07F4, 3, 0)
+MX6_PAD_DECL(CSI0_DAT4__KEY_COL5,	0x0638, 0x0268, 3, 0x08E8, 2, 0)
+MX6_PAD_DECL(CSI0_DAT4__AUD3_TXC,	0x0638, 0x0268, 4, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT4__GPIO5_IO22,	0x0638, 0x0268, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT4__ARM_TRACE01,	0x0638, 0x0268, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT5__IPU1_CSI0_DATA05,	0x063C, 0x026C, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT5__EIM_DATA03,	0x063C, 0x026C, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT5__ECSPI1_MOSI,	0x063C, 0x026C, 2, 0x07FC, 3, 0)
+MX6_PAD_DECL(CSI0_DAT5__KEY_ROW5,	0x063C, 0x026C, 3, 0x08F4, 1, 0)
+MX6_PAD_DECL(CSI0_DAT5__AUD3_TXD,	0x063C, 0x026C, 4, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT5__GPIO5_IO23,	0x063C, 0x026C, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT5__ARM_TRACE02,	0x063C, 0x026C, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT6__IPU1_CSI0_DATA06,	0x0640, 0x0270, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT6__EIM_DATA04,	0x0640, 0x0270, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT6__ECSPI1_MISO,	0x0640, 0x0270, 2, 0x07F8, 3, 0)
+MX6_PAD_DECL(CSI0_DAT6__KEY_COL6,	0x0640, 0x0270, 3, 0x08EC, 1, 0)
+MX6_PAD_DECL(CSI0_DAT6__AUD3_TXFS,	0x0640, 0x0270, 4, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT6__GPIO5_IO24,	0x0640, 0x0270, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT6__ARM_TRACE03,	0x0640, 0x0270, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT7__IPU1_CSI0_DATA07,	0x0644, 0x0274, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT7__EIM_DATA05,	0x0644, 0x0274, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT7__ECSPI1_SS0,	0x0644, 0x0274, 2, 0x0800, 3, 0)
+MX6_PAD_DECL(CSI0_DAT7__KEY_ROW6,	0x0644, 0x0274, 3, 0x08F8, 2, 0)
+MX6_PAD_DECL(CSI0_DAT7__AUD3_RXD,	0x0644, 0x0274, 4, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT7__GPIO5_IO25,	0x0644, 0x0274, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT7__ARM_TRACE04,	0x0644, 0x0274, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT8__IPU1_CSI0_DATA08,	0x0648, 0x0278, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT8__EIM_DATA06,	0x0648, 0x0278, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT8__ECSPI2_SCLK,	0x0648, 0x0278, 2, 0x0810, 2, 0)
+MX6_PAD_DECL(CSI0_DAT8__KEY_COL7,	0x0648, 0x0278, 3, 0x08F0, 2, 0)
+MX6_PAD_DECL(CSI0_DAT8__I2C1_SDA,	0x0648, 0x0278, 20, 0x089C, 1, 0)
+MX6_PAD_DECL(CSI0_DAT8__GPIO5_IO26,	0x0648, 0x0278, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT8__ARM_TRACE05,	0x0648, 0x0278, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT9__IPU1_CSI0_DATA09,	0x064C, 0x027C, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT9__EIM_DATA07,	0x064C, 0x027C, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT9__ECSPI2_MOSI,	0x064C, 0x027C, 2, 0x0818, 2, 0)
+MX6_PAD_DECL(CSI0_DAT9__KEY_ROW7,	0x064C, 0x027C, 3, 0x08FC, 2, 0)
+MX6_PAD_DECL(CSI0_DAT9__I2C1_SCL,	0x064C, 0x027C, 20, 0x0898, 1, 0)
+MX6_PAD_DECL(CSI0_DAT9__GPIO5_IO27,	0x064C, 0x027C, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT9__ARM_TRACE06,	0x064C, 0x027C, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT10__IPU1_CSI0_DATA10,	0x0650, 0x0280, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT10__AUD3_RXC,	0x0650, 0x0280, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT10__ECSPI2_MISO,	0x0650, 0x0280, 2, 0x0814, 2, 0)
+MX6_PAD_DECL(CSI0_DAT10__UART1_TX_DATA,	0x0650, 0x0280, 3, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT10__UART1_RX_DATA,	0x0650, 0x0280, 3, 0x0920, 0, 0)
+MX6_PAD_DECL(CSI0_DAT10__GPIO5_IO28,	0x0650, 0x0280, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT10__ARM_TRACE07,	0x0650, 0x0280, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT11__IPU1_CSI0_DATA11,	0x0654, 0x0284, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT11__AUD3_RXFS,	0x0654, 0x0284, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT11__ECSPI2_SS0,	0x0654, 0x0284, 2, 0x081C, 2, 0)
+MX6_PAD_DECL(CSI0_DAT11__UART1_TX_DATA,	0x0654, 0x0284, 3, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT11__UART1_RX_DATA,	0x0654, 0x0284, 3, 0x0920, 1, 0)
+MX6_PAD_DECL(CSI0_DAT11__GPIO5_IO29,	0x0654, 0x0284, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT11__ARM_TRACE08,	0x0654, 0x0284, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT12__IPU1_CSI0_DATA12,	0x0658, 0x0288, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT12__EIM_DATA08,	0x0658, 0x0288, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT12__UART4_TX_DATA,	0x0658, 0x0288, 3, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT12__UART4_RX_DATA,	0x0658, 0x0288, 3, 0x0938, 2, 0)
+MX6_PAD_DECL(CSI0_DAT12__GPIO5_IO30,	0x0658, 0x0288, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT12__ARM_TRACE09,	0x0658, 0x0288, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT13__IPU1_CSI0_DATA13,	0x065C, 0x028C, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT13__EIM_DATA09,	0x065C, 0x028C, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT13__UART4_TX_DATA,	0x065C, 0x028C, 3, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT13__UART4_RX_DATA,	0x065C, 0x028C, 3, 0x0938, 3, 0)
+MX6_PAD_DECL(CSI0_DAT13__GPIO5_IO31,	0x065C, 0x028C, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT13__ARM_TRACE10,	0x065C, 0x028C, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT14__IPU1_CSI0_DATA14,	0x0660, 0x0290, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT14__EIM_DATA10,	0x0660, 0x0290, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT14__UART5_TX_DATA,	0x0660, 0x0290, 3, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT14__UART5_RX_DATA,	0x0660, 0x0290, 3, 0x0940, 2, 0)
+MX6_PAD_DECL(CSI0_DAT14__GPIO6_IO00,	0x0660, 0x0290, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT14__ARM_TRACE11,	0x0660, 0x0290, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT15__IPU1_CSI0_DATA15,	0x0664, 0x0294, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT15__EIM_DATA11,	0x0664, 0x0294, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT15__UART5_TX_DATA,	0x0664, 0x0294, 3, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT15__UART5_RX_DATA,	0x0664, 0x0294, 3, 0x0940, 3, 0)
+MX6_PAD_DECL(CSI0_DAT15__GPIO6_IO01,	0x0664, 0x0294, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT15__ARM_TRACE12,	0x0664, 0x0294, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT16__IPU1_CSI0_DATA16,	0x0668, 0x0298, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT16__EIM_DATA12,	0x0668, 0x0298, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT16__UART4_CTS_B,	0x0668, 0x0298, 3, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT16__UART4_RTS_B,	0x0668, 0x0298, 3, 0x0934, 0, 0)
+MX6_PAD_DECL(CSI0_DAT16__GPIO6_IO02,	0x0668, 0x0298, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT16__ARM_TRACE13,	0x0668, 0x0298, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT17__IPU1_CSI0_DATA17,	0x066C, 0x029C, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT17__EIM_DATA13,	0x066C, 0x029C, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT17__UART4_CTS_B,	0x066C, 0x029C, 3, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT17__UART4_RTS_B,	0x066C, 0x029C, 3, 0x0934, 1, 0)
+MX6_PAD_DECL(CSI0_DAT17__GPIO6_IO03,	0x066C, 0x029C, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT17__ARM_TRACE14,	0x066C, 0x029C, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT18__IPU1_CSI0_DATA18,	0x0670, 0x02A0, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT18__EIM_DATA14,	0x0670, 0x02A0, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT18__UART5_CTS_B,	0x0670, 0x02A0, 3, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT18__UART5_RTS_B,	0x0670, 0x02A0, 3, 0x093C, 2, 0)
+MX6_PAD_DECL(CSI0_DAT18__GPIO6_IO04,	0x0670, 0x02A0, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT18__ARM_TRACE15,	0x0670, 0x02A0, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT19__IPU1_CSI0_DATA19,	0x0674, 0x02A4, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT19__EIM_DATA15,	0x0674, 0x02A4, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT19__UART5_CTS_B,	0x0674, 0x02A4, 3, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT19__UART5_RTS_B,	0x0674, 0x02A4, 3, 0x093C, 3, 0)
+MX6_PAD_DECL(CSI0_DAT19__GPIO6_IO05,	0x0674, 0x02A4, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(SD3_DAT7__SD3_DATA7,	0x0690, 0x02A8, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(SD3_DAT7__UART1_TX_DATA,	0x0690, 0x02A8, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(SD3_DAT7__UART1_RX_DATA,	0x0690, 0x02A8, 1, 0x0920, 2, 0)
+MX6_PAD_DECL(SD3_DAT7__GPIO6_IO17,	0x0690, 0x02A8, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(SD3_DAT6__SD3_DATA6,	0x0694, 0x02AC, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(SD3_DAT6__UART1_TX_DATA,	0x0694, 0x02AC, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(SD3_DAT6__UART1_RX_DATA,	0x0694, 0x02AC, 1, 0x0920, 3, 0)
+MX6_PAD_DECL(SD3_DAT6__GPIO6_IO18,	0x0694, 0x02AC, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(SD3_DAT5__SD3_DATA5,	0x0698, 0x02B0, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(SD3_DAT5__UART2_TX_DATA,	0x0698, 0x02B0, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(SD3_DAT5__UART2_RX_DATA,	0x0698, 0x02B0, 1, 0x0928, 4, 0)
+MX6_PAD_DECL(SD3_DAT5__GPIO7_IO00,	0x0698, 0x02B0, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(SD3_DAT4__SD3_DATA4,	0x069C, 0x02B4, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(SD3_DAT4__UART2_TX_DATA,	0x069C, 0x02B4, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(SD3_DAT4__UART2_RX_DATA,	0x069C, 0x02B4, 1, 0x0928, 5, 0)
+MX6_PAD_DECL(SD3_DAT4__GPIO7_IO01,	0x069C, 0x02B4, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(SD3_CMD__SD3_CMD,	0x06A0, 0x02B8, 16, 0x0000, 0, 0)
+MX6_PAD_DECL(SD3_CMD__UART2_CTS_B,	0x06A0, 0x02B8, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(SD3_CMD__UART2_RTS_B,	0x06A0, 0x02B8, 1, 0x0924, 2, 0)
+MX6_PAD_DECL(SD3_CMD__FLEXCAN1_TX,	0x06A0, 0x02B8, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(SD3_CMD__GPIO7_IO02,	0x06A0, 0x02B8, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(SD3_CLK__SD3_CLK,	0x06A4, 0x02BC, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(SD3_CLK__UART2_CTS_B,	0x06A4, 0x02BC, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(SD3_CLK__UART2_RTS_B,	0x06A4, 0x02BC, 1, 0x0924, 3, 0)
+MX6_PAD_DECL(SD3_CLK__FLEXCAN1_RX,	0x06A4, 0x02BC, 2, 0x07E4, 2, 0)
+MX6_PAD_DECL(SD3_CLK__GPIO7_IO03,	0x06A4, 0x02BC, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(SD3_DAT0__SD3_DATA0,	0x06A8, 0x02C0, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(SD3_DAT0__UART1_CTS_B,	0x06A8, 0x02C0, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(SD3_DAT0__UART1_RTS_B,	0x06A8, 0x02C0, 1, 0x091C, 2, 0)
+MX6_PAD_DECL(SD3_DAT0__FLEXCAN2_TX,	0x06A8, 0x02C0, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(SD3_DAT0__GPIO7_IO04,	0x06A8, 0x02C0, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(SD3_DAT1__SD3_DATA1,	0x06AC, 0x02C4, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(SD3_DAT1__UART1_CTS_B,	0x06AC, 0x02C4, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(SD3_DAT1__UART1_RTS_B,	0x06AC, 0x02C4, 1, 0x091C, 3, 0)
+MX6_PAD_DECL(SD3_DAT1__FLEXCAN2_RX,	0x06AC, 0x02C4, 2, 0x07E8, 1, 0)
+MX6_PAD_DECL(SD3_DAT1__GPIO7_IO05,	0x06AC, 0x02C4, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(SD3_DAT2__SD3_DATA2,	0x06B0, 0x02C8, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(SD3_DAT2__GPIO7_IO06,	0x06B0, 0x02C8, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(SD3_DAT3__SD3_DATA3,	0x06B4, 0x02CC, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(SD3_DAT3__UART3_CTS_B,	0x06B4, 0x02CC, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(SD3_DAT3__UART3_RTS_B,	0x06B4, 0x02CC, 1, 0x092C, 4, 0)
+MX6_PAD_DECL(SD3_DAT3__GPIO7_IO07,	0x06B4, 0x02CC, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(SD3_RST__SD3_RESET,	0x06B8, 0x02D0, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(SD3_RST__UART3_CTS_B,	0x06B8, 0x02D0, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(SD3_RST__UART3_RTS_B,	0x06B8, 0x02D0, 1, 0x092C, 5, 0)
+MX6_PAD_DECL(SD3_RST__GPIO7_IO08,	0x06B8, 0x02D0, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(NANDF_CLE__NAND_CLE,	0x06BC, 0x02D4, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(NANDF_CLE__IPU2_SISG4,	0x06BC, 0x02D4, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(NANDF_CLE__GPIO6_IO07,	0x06BC, 0x02D4, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(NANDF_ALE__NAND_ALE,	0x06C0, 0x02D8, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(NANDF_ALE__SD4_RESET,	0x06C0, 0x02D8, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(NANDF_ALE__GPIO6_IO08,	0x06C0, 0x02D8, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(NANDF_WP_B__NAND_WP_B,	0x06C4, 0x02DC, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(NANDF_WP_B__IPU2_SISG5,	0x06C4, 0x02DC, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(NANDF_WP_B__GPIO6_IO09,	0x06C4, 0x02DC, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(NANDF_RB0__NAND_READY_B,	0x06C8, 0x02E0, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(NANDF_RB0__IPU2_DI0_PIN01,	0x06C8, 0x02E0, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(NANDF_RB0__GPIO6_IO10,	0x06C8, 0x02E0, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(NANDF_CS0__NAND_CE0_B,	0x06CC, 0x02E4, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(NANDF_CS0__GPIO6_IO11,	0x06CC, 0x02E4, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(NANDF_CS1__NAND_CE1_B,	0x06D0, 0x02E8, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(NANDF_CS1__SD4_VSELECT,	0x06D0, 0x02E8, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(NANDF_CS1__SD3_VSELECT,	0x06D0, 0x02E8, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(NANDF_CS1__GPIO6_IO14,	0x06D0, 0x02E8, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(NANDF_CS2__NAND_CE2_B,	0x06D4, 0x02EC, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(NANDF_CS2__IPU1_SISG0,	0x06D4, 0x02EC, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(NANDF_CS2__ESAI_TX0,	0x06D4, 0x02EC, 2, 0x0874, 1, 0)
+MX6_PAD_DECL(NANDF_CS2__EIM_CRE,	0x06D4, 0x02EC, 3, 0x0000, 0, 0)
+MX6_PAD_DECL(NANDF_CS2__CCM_CLKO2,	0x06D4, 0x02EC, 4, 0x0000, 0, 0)
+MX6_PAD_DECL(NANDF_CS2__GPIO6_IO15,	0x06D4, 0x02EC, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(NANDF_CS2__IPU2_SISG0,	0x06D4, 0x02EC, 6, 0x0000, 0, 0)
+MX6_PAD_DECL(NANDF_CS3__NAND_CE3_B,	0x06D8, 0x02F0, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(NANDF_CS3__IPU1_SISG1,	0x06D8, 0x02F0, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(NANDF_CS3__ESAI_TX1,	0x06D8, 0x02F0, 2, 0x0878, 1, 0)
+MX6_PAD_DECL(NANDF_CS3__EIM_ADDR26,	0x06D8, 0x02F0, 3, 0x0000, 0, 0)
+MX6_PAD_DECL(NANDF_CS3__GPIO6_IO16,	0x06D8, 0x02F0, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(NANDF_CS3__IPU2_SISG1,	0x06D8, 0x02F0, 6, 0x0000, 0, 0)
+MX6_PAD_DECL(SD4_CMD__SD4_CMD,	0x06DC, 0x02F4, 16, 0x0000, 0, 0)
+MX6_PAD_DECL(SD4_CMD__NAND_RE_B,	0x06DC, 0x02F4, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(SD4_CMD__UART3_TX_DATA,	0x06DC, 0x02F4, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(SD4_CMD__UART3_RX_DATA,	0x06DC, 0x02F4, 2, 0x0930, 2, 0)
+MX6_PAD_DECL(SD4_CMD__GPIO7_IO09,	0x06DC, 0x02F4, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(SD4_CLK__SD4_CLK,	0x06E0, 0x02F8, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(SD4_CLK__NAND_WE_B,	0x06E0, 0x02F8, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(SD4_CLK__UART3_TX_DATA,	0x06E0, 0x02F8, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(SD4_CLK__UART3_RX_DATA,	0x06E0, 0x02F8, 2, 0x0930, 3, 0)
+MX6_PAD_DECL(SD4_CLK__GPIO7_IO10,	0x06E0, 0x02F8, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(NANDF_D0__NAND_DATA00,	0x06E4, 0x02FC, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(NANDF_D0__SD1_DATA4,	0x06E4, 0x02FC, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(NANDF_D0__GPIO2_IO00,	0x06E4, 0x02FC, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(NANDF_D1__NAND_DATA01,	0x06E8, 0x0300, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(NANDF_D1__SD1_DATA5,	0x06E8, 0x0300, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(NANDF_D1__GPIO2_IO01,	0x06E8, 0x0300, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(NANDF_D2__NAND_DATA02,	0x06EC, 0x0304, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(NANDF_D2__SD1_DATA6,	0x06EC, 0x0304, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(NANDF_D2__GPIO2_IO02,	0x06EC, 0x0304, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(NANDF_D3__NAND_DATA03,	0x06F0, 0x0308, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(NANDF_D3__SD1_DATA7,	0x06F0, 0x0308, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(NANDF_D3__GPIO2_IO03,	0x06F0, 0x0308, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(NANDF_D4__NAND_DATA04,	0x06F4, 0x030C, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(NANDF_D4__SD2_DATA4,	0x06F4, 0x030C, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(NANDF_D4__GPIO2_IO04,	0x06F4, 0x030C, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(NANDF_D5__NAND_DATA05,	0x06F8, 0x0310, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(NANDF_D5__SD2_DATA5,	0x06F8, 0x0310, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(NANDF_D5__GPIO2_IO05,	0x06F8, 0x0310, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(NANDF_D6__NAND_DATA06,	0x06FC, 0x0314, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(NANDF_D6__SD2_DATA6,	0x06FC, 0x0314, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(NANDF_D6__GPIO2_IO06,	0x06FC, 0x0314, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(NANDF_D7__NAND_DATA07,	0x0700, 0x0318, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(NANDF_D7__SD2_DATA7,	0x0700, 0x0318, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(NANDF_D7__GPIO2_IO07,	0x0700, 0x0318, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(SD4_DAT0__SD4_DATA0,	0x0704, 0x031C, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(SD4_DAT0__NAND_DQS,	0x0704, 0x031C, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(SD4_DAT0__GPIO2_IO08,	0x0704, 0x031C, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(SD4_DAT1__SD4_DATA1,	0x0708, 0x0320, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(SD4_DAT1__PWM3_OUT,	0x0708, 0x0320, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(SD4_DAT1__GPIO2_IO09,	0x0708, 0x0320, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(SD4_DAT2__SD4_DATA2,	0x070C, 0x0324, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(SD4_DAT2__PWM4_OUT,	0x070C, 0x0324, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(SD4_DAT2__GPIO2_IO10,	0x070C, 0x0324, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(SD4_DAT3__SD4_DATA3,	0x0710, 0x0328, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(SD4_DAT3__GPIO2_IO11,	0x0710, 0x0328, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(SD4_DAT4__SD4_DATA4,	0x0714, 0x032C, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(SD4_DAT4__UART2_TX_DATA,	0x0714, 0x032C, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(SD4_DAT4__UART2_RX_DATA,	0x0714, 0x032C, 2, 0x0928, 6, 0)
+MX6_PAD_DECL(SD4_DAT4__GPIO2_IO12,	0x0714, 0x032C, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(SD4_DAT5__SD4_DATA5,	0x0718, 0x0330, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(SD4_DAT5__UART2_CTS_B,	0x0718, 0x0330, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(SD4_DAT5__UART2_RTS_B,	0x0718, 0x0330, 2, 0x0924, 4, 0)
+MX6_PAD_DECL(SD4_DAT5__GPIO2_IO13,	0x0718, 0x0330, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(SD4_DAT6__SD4_DATA6,	0x071C, 0x0334, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(SD4_DAT6__UART2_CTS_B,	0x071C, 0x0334, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(SD4_DAT6__UART2_RTS_B,	0x071C, 0x0334, 2, 0x0924, 5, 0)
+MX6_PAD_DECL(SD4_DAT6__GPIO2_IO14,	0x071C, 0x0334, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(SD4_DAT7__SD4_DATA7,	0x0720, 0x0338, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(SD4_DAT7__UART2_TX_DATA,	0x0720, 0x0338, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(SD4_DAT7__UART2_RX_DATA,	0x0720, 0x0338, 2, 0x0928, 7, 0)
+MX6_PAD_DECL(SD4_DAT7__GPIO2_IO15,	0x0720, 0x0338, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(SD1_DAT1__SD1_DATA1,	0x0724, 0x033C, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(SD1_DAT1__ECSPI5_SS0,	0x0724, 0x033C, 1, 0x0834, 1, 0)
+MX6_PAD_DECL(SD1_DAT1__PWM3_OUT,	0x0724, 0x033C, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(SD1_DAT1__GPT_CAPTURE2,	0x0724, 0x033C, 3, 0x0000, 0, 0)
+MX6_PAD_DECL(SD1_DAT1__GPIO1_IO17,	0x0724, 0x033C, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(SD1_DAT0__SD1_DATA0,	0x0728, 0x0340, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(SD1_DAT0__ECSPI5_MISO,	0x0728, 0x0340, 1, 0x082C, 1, 0)
+MX6_PAD_DECL(SD1_DAT0__GPT_CAPTURE1,	0x0728, 0x0340, 3, 0x0000, 0, 0)
+MX6_PAD_DECL(SD1_DAT0__GPIO1_IO16,	0x0728, 0x0340, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(SD1_DAT3__SD1_DATA3,	0x072C, 0x0344, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(SD1_DAT3__ECSPI5_SS2,	0x072C, 0x0344, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(SD1_DAT3__GPT_COMPARE3,	0x072C, 0x0344, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(SD1_DAT3__PWM1_OUT,	0x072C, 0x0344, 3, 0x0000, 0, 0)
+MX6_PAD_DECL(SD1_DAT3__WDOG2_B,	0x072C, 0x0344, 4, 0x0000, 0, 0)
+MX6_PAD_DECL(SD1_DAT3__GPIO1_IO21,	0x072C, 0x0344, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(SD1_DAT3__WDOG2_RESET_B_DEB,	0x072C, 0x0344, 6, 0x0000, 0, 0)
+MX6_PAD_DECL(SD1_CMD__SD1_CMD,	0x0730, 0x0348, 16, 0x0000, 0, 0)
+MX6_PAD_DECL(SD1_CMD__ECSPI5_MOSI,	0x0730, 0x0348, 1, 0x0830, 0, 0)
+MX6_PAD_DECL(SD1_CMD__PWM4_OUT,	0x0730, 0x0348, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(SD1_CMD__GPT_COMPARE1,	0x0730, 0x0348, 3, 0x0000, 0, 0)
+MX6_PAD_DECL(SD1_CMD__GPIO1_IO18,	0x0730, 0x0348, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(SD1_DAT2__SD1_DATA2,	0x0734, 0x034C, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(SD1_DAT2__ECSPI5_SS1,	0x0734, 0x034C, 1, 0x0838, 1, 0)
+MX6_PAD_DECL(SD1_DAT2__GPT_COMPARE2,	0x0734, 0x034C, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(SD1_DAT2__PWM2_OUT,	0x0734, 0x034C, 3, 0x0000, 0, 0)
+MX6_PAD_DECL(SD1_DAT2__WDOG1_B,	0x0734, 0x034C, 4, 0x0000, 0, 0)
+MX6_PAD_DECL(SD1_DAT2__GPIO1_IO19,	0x0734, 0x034C, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(SD1_DAT2__WDOG1_RESET_B_DEB,	0x0734, 0x034C, 6, 0x0000, 0, 0)
+MX6_PAD_DECL(SD1_CLK__SD1_CLK,	0x0738, 0x0350, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(SD1_CLK__ECSPI5_SCLK,	0x0738, 0x0350, 1, 0x0828, 0, 0)
+MX6_PAD_DECL(SD1_CLK__GPT_CLKIN,	0x0738, 0x0350, 3, 0x0000, 0, 0)
+MX6_PAD_DECL(SD1_CLK__GPIO1_IO20,	0x0738, 0x0350, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(SD2_CLK__SD2_CLK,	0x073C, 0x0354, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(SD2_CLK__ECSPI5_SCLK,	0x073C, 0x0354, 1, 0x0828, 1, 0)
+MX6_PAD_DECL(SD2_CLK__KEY_COL5,	0x073C, 0x0354, 2, 0x08E8, 3, 0)
+MX6_PAD_DECL(SD2_CLK__AUD4_RXFS,	0x073C, 0x0354, 3, 0x07C0, 1, 0)
+MX6_PAD_DECL(SD2_CLK__GPIO1_IO10,	0x073C, 0x0354, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(SD2_CMD__SD2_CMD,	0x0740, 0x0358, 16, 0x0000, 0, 0)
+MX6_PAD_DECL(SD2_CMD__ECSPI5_MOSI,	0x0740, 0x0358, 1, 0x0830, 1, 0)
+MX6_PAD_DECL(SD2_CMD__KEY_ROW5,	0x0740, 0x0358, 2, 0x08F4, 2, 0)
+MX6_PAD_DECL(SD2_CMD__AUD4_RXC,	0x0740, 0x0358, 3, 0x07BC, 1, 0)
+MX6_PAD_DECL(SD2_CMD__GPIO1_IO11,	0x0740, 0x0358, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(SD2_DAT3__SD2_DATA3,	0x0744, 0x035C, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(SD2_DAT3__ECSPI5_SS3,	0x0744, 0x035C, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(SD2_DAT3__KEY_COL6,	0x0744, 0x035C, 2, 0x08EC, 2, 0)
+MX6_PAD_DECL(SD2_DAT3__AUD4_TXC,	0x0744, 0x035C, 3, 0x07C4, 1, 0)
+MX6_PAD_DECL(SD2_DAT3__GPIO1_IO12,	0x0744, 0x035C, 5, 0x0000, 0, 0)
 
 #endif	/* __ASM_ARCH_MX6_MX6Q_PINS_H__ */
diff --git a/arch/arm/include/asm/arch-mx6/sys_proto.h b/arch/arm/include/asm/arch-mx6/sys_proto.h
index 8c21364e71..38851a135c 100644
--- a/arch/arm/include/asm/arch-mx6/sys_proto.h
+++ b/arch/arm/include/asm/arch-mx6/sys_proto.h
@@ -9,13 +9,7 @@
 #define _SYS_PROTO_H_
 
 #include <asm/imx-common/regs-common.h>
-
-#define MXC_CPU_MX51		0x51
-#define MXC_CPU_MX53		0x53
-#define MXC_CPU_MX6SL		0x60
-#define MXC_CPU_MX6DL		0x61
-#define MXC_CPU_MX6SOLO		0x62
-#define MXC_CPU_MX6Q		0x63
+#include "../arch-imx/cpu.h"
 
 #define is_soc_rev(rev)	((get_cpu_rev() & 0xFF) - rev)
 u32 get_cpu_rev(void);
@@ -29,8 +23,6 @@ u32 get_cpu_rev(void);
 const char *get_imx_type(u32 imxtype);
 unsigned imx_ddr_size(void);
 
-void set_vddsoc(u32 mv);
-
 /*
  * Initializes on-chip ethernet controllers.
  * to override, implement board_eth_init()
diff --git a/arch/arm/include/asm/arch-mxs/sys_proto.h b/arch/arm/include/asm/arch-mxs/sys_proto.h
index 43c7dd6bf1..09dfc90a9b 100644
--- a/arch/arm/include/asm/arch-mxs/sys_proto.h
+++ b/arch/arm/include/asm/arch-mxs/sys_proto.h
@@ -46,6 +46,7 @@ static const struct mxs_pair mxs_boot_modes[] = {
 	{ 0x02, 0x1f, "SSP SPI #1, master, NOR" },
 	{ 0x03, 0x1f, "SSP SPI #2, master, NOR" },
 	{ 0x04, 0x1f, "NAND" },
+	{ 0x06, 0x1f, "JTAG" },
 	{ 0x08, 0x1f, "SSP SPI #3, master, EEPROM" },
 	{ 0x09, 0x1f, "SSP SD/MMC #0" },
 	{ 0x0a, 0x1f, "SSP SD/MMC #1" },
@@ -60,6 +61,7 @@ static const struct mxs_pair mxs_boot_modes[] = {
 	{ 0x13, 0x1f, "SSP SPI #3, master, 1V8 NOR" },
 	{ 0x04, 0x1f, "NAND, 3V3" },
 	{ 0x14, 0x1f, "NAND, 1V8" },
+	{ 0x06, 0x1f, "JTAG" },
 	{ 0x08, 0x1f, "SSP SPI #3, master, 3V3 EEPROM" },
 	{ 0x18, 0x1f, "SSP SPI #3, master, 1V8 EEPROM" },
 	{ 0x09, 0x1f, "SSP SD/MMC #0, 3V3" },
diff --git a/arch/arm/include/asm/arch-omap3/clock.h b/arch/arm/include/asm/arch-omap3/clock.h
index be669c156f..1912cc9a67 100644
--- a/arch/arm/include/asm/arch-omap3/clock.h
+++ b/arch/arm/include/asm/arch-omap3/clock.h
@@ -27,8 +27,6 @@
 #define ICK_DSS_ON	0x00000001
 #define FCK_CAM_ON	0x00000001
 #define ICK_CAM_ON	0x00000001
-#define FCK_PER_ON	0x0003ffff
-#define ICK_PER_ON	0x0003ffff
 
 /* Used to index into DPLL parameter tables */
 typedef struct {
diff --git a/arch/arm/include/asm/arch-omap3/cpu.h b/arch/arm/include/asm/arch-omap3/cpu.h
index 61ec8f24e0..4d06ef83fe 100644
--- a/arch/arm/include/asm/arch-omap3/cpu.h
+++ b/arch/arm/include/asm/arch-omap3/cpu.h
@@ -77,59 +77,7 @@ struct ctrl_id {
 #define GPMC_CONFIG_CS0_BASE	(GPMC_BASE + GPMC_CONFIG_CS0)
 
 #ifndef __KERNEL_STRICT_NAMES
-#ifndef __ASSEMBLY__
-struct gpmc_cs {
-	u32 config1;		/* 0x00 */
-	u32 config2;		/* 0x04 */
-	u32 config3;		/* 0x08 */
-	u32 config4;		/* 0x0C */
-	u32 config5;		/* 0x10 */
-	u32 config6;		/* 0x14 */
-	u32 config7;		/* 0x18 */
-	u32 nand_cmd;		/* 0x1C */
-	u32 nand_adr;		/* 0x20 */
-	u32 nand_dat;		/* 0x24 */
-	u8 res[8];		/* blow up to 0x30 byte */
-};
-
-struct bch_res_0_3 {
-	u32 bch_result_x[4];
-};
-
-struct gpmc {
-	u8 res1[0x10];
-	u32 sysconfig;		/* 0x10 */
-	u8 res2[0x4];
-	u32 irqstatus;		/* 0x18 */
-	u32 irqenable;		/* 0x1C */
-	u8 res3[0x20];
-	u32 timeout_control; 	/* 0x40 */
-	u8 res4[0xC];
-	u32 config;		/* 0x50 */
-	u32 status;		/* 0x54 */
-	u8 res5[0x8];	/* 0x58 */
-	struct gpmc_cs cs[8];	/* 0x60, 0x90, .. */
-	u8 res6[0x14];		/* 0x1E0 */
-	u32 ecc_config;		/* 0x1F4 */
-	u32 ecc_control;	/* 0x1F8 */
-	u32 ecc_size_config;	/* 0x1FC */
-	u32 ecc1_result;	/* 0x200 */
-	u32 ecc2_result;	/* 0x204 */
-	u32 ecc3_result;	/* 0x208 */
-	u32 ecc4_result;	/* 0x20C */
-	u32 ecc5_result;	/* 0x210 */
-	u32 ecc6_result;	/* 0x214 */
-	u32 ecc7_result;	/* 0x218 */
-	u32 ecc8_result;	/* 0x21C */
-	u32 ecc9_result;	/* 0x220 */
-	u8 res7[0x1C];		/* fill up to 0x240 */
-	struct bch_res_0_3 bch_result_0_3[7];	/* 0x240 */
-};
-
-/* Used for board specific gpmc initialization */
-extern struct gpmc *gpmc_cfg;
-
-#else /* __ASSEMBLY__ */
+#ifdef __ASSEMBLY__
 #define GPMC_CONFIG1		0x00
 #define GPMC_CONFIG2		0x04
 #define GPMC_CONFIG3		0x08
diff --git a/arch/arm/include/asm/arch-omap3/dss.h b/arch/arm/include/asm/arch-omap3/dss.h
index ae0babf17c..8bf6b4895f 100644
--- a/arch/arm/include/asm/arch-omap3/dss.h
+++ b/arch/arm/include/asm/arch-omap3/dss.h
@@ -178,10 +178,11 @@ struct venc_regs {
 #define LCD_INTERFACE_24_BIT	3
 
 /* Polarity */
-#define DSS_IVS	(1 << 12)
-#define DSS_IHS	(1 << 13)
-#define DSS_IPC	(1 << 14)
-#define DSS_IEO	(1 << 15)
+#define DSS_IVS		(1 << 12)
+#define DSS_IHS		(1 << 13)
+#define DSS_IPC		(1 << 14)
+#define DSS_IEO		(1 << 15)
+#define DSS_ONOFF	(1 << 17)
 
 /* GFX format */
 #define GFXFORMAT_BITMAP1		(0x0 << 1)
diff --git a/arch/arm/include/asm/arch-omap3/mem.h b/arch/arm/include/asm/arch-omap3/mem.h
index bcc22c43e1..18041913c4 100644
--- a/arch/arm/include/asm/arch-omap3/mem.h
+++ b/arch/arm/include/asm/arch-omap3/mem.h
@@ -419,6 +419,16 @@ enum {
 #define NET_GPMC_CONFIG6	0x00000FCF
 #define NET_GPMC_CONFIG7	0x00000f6c
 
+/* GPMC CS configuration for an SMSC LAN9221 ethernet controller */
+#define NET_LAN9221_GPMC_CONFIG1    0x00001000
+#define NET_LAN9221_GPMC_CONFIG2    0x00060700
+#define NET_LAN9221_GPMC_CONFIG3    0x00020201
+#define NET_LAN9221_GPMC_CONFIG4    0x06000700
+#define NET_LAN9221_GPMC_CONFIG5    0x0006090A
+#define NET_LAN9221_GPMC_CONFIG6    0x87030000
+#define NET_LAN9221_GPMC_CONFIG7    0x00000f6c
+
+
 /* max number of GPMC Chip Selects */
 #define GPMC_MAX_CS	8
 /* max number of GPMC regs */
diff --git a/arch/arm/include/asm/arch-omap3/omap3.h b/arch/arm/include/asm/arch-omap3/omap3.h
index 7fb549af54..194b93bf56 100644
--- a/arch/arm/include/asm/arch-omap3/omap3.h
+++ b/arch/arm/include/asm/arch-omap3/omap3.h
@@ -55,6 +55,7 @@ struct control_prog_io {
 #define OMAP34XX_UART1			(OMAP34XX_L4_IO_BASE + 0x6a000)
 #define OMAP34XX_UART2			(OMAP34XX_L4_IO_BASE + 0x6c000)
 #define OMAP34XX_UART3			(OMAP34XX_L4_PER + 0x20000)
+#define OMAP34XX_UART4			(OMAP34XX_L4_PER + 0x42000)
 
 /* General Purpose Timers */
 #define OMAP34XX_GPT1			0x48318000
@@ -139,13 +140,13 @@ struct gpio {
 					 SRAM_OFFSET2)
 #define SRAM_CLK_CODE			(SRAM_VECT_CODE + 64)
 
-#define OMAP3_PUBLIC_SRAM_BASE		0x40208000 /* Works for GP & EMU */
-#define OMAP3_PUBLIC_SRAM_END		0x40210000
+#define NON_SECURE_SRAM_START		0x40208000 /* Works for GP & EMU */
+#define NON_SECURE_SRAM_END		0x40210000
 
 #define LOW_LEVEL_SRAM_STACK		0x4020FFFC
 
 /* scratch area - accessible on both EMU and GP */
-#define OMAP3_PUBLIC_SRAM_SCRATCH_AREA	OMAP3_PUBLIC_SRAM_BASE
+#define OMAP3_PUBLIC_SRAM_SCRATCH_AREA	NON_SECURE_SRAM_START
 
 #define DEBUG_LED1			149	/* gpio */
 #define DEBUG_LED2			150	/* gpio */
diff --git a/arch/arm/include/asm/arch-omap3/omap_gpmc.h b/arch/arm/include/asm/arch-omap3/omap_gpmc.h
deleted file mode 100644
index bf2321932a..0000000000
--- a/arch/arm/include/asm/arch-omap3/omap_gpmc.h
+++ /dev/null
@@ -1,36 +0,0 @@
-/*
- * (C) Copyright 2004-2008 Texas Instruments, <www.ti.com>
- * Rohit Choraria <rohitkc@ti.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-#ifndef __ASM_ARCH_OMAP_GPMC_H
-#define __ASM_ARCH_OMAP_GPMC_H
-
-/*
- * These GPMC_NAND_HW_BCHx_ECC_LAYOUT defines using the BCH library.
- * The OOB layout was first defined by linx kernel in commit
- * 0e618ef0a6a33cf7ef96c2c824402088dd8ef48c, we have to reuse it here cause
- * we want to be compatible.
- */
-#define GPMC_NAND_HW_BCH8_ECC_LAYOUT {\
-	.eccbytes = 56,\
-	.eccpos = {12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22,\
-			23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36,\
-			37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50,\
-			51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63},\
-	.oobfree = {\
-		{.offset = 2,\
-		 .length = 10 } } \
-}
-
-/* GPMC CS configuration for an SMSC LAN9221 ethernet controller */
-#define NET_LAN9221_GPMC_CONFIG1    0x00001000
-#define NET_LAN9221_GPMC_CONFIG2    0x00060700
-#define NET_LAN9221_GPMC_CONFIG3    0x00020201
-#define NET_LAN9221_GPMC_CONFIG4    0x06000700
-#define NET_LAN9221_GPMC_CONFIG5    0x0006090A
-#define NET_LAN9221_GPMC_CONFIG6    0x87030000
-#define NET_LAN9221_GPMC_CONFIG7    0x00000f6c
-
-#endif /* __ASM_ARCH_OMAP_GPMC_H */
diff --git a/arch/arm/include/asm/arch-omap3/spl.h b/arch/arm/include/asm/arch-omap3/spl.h
index 2ec319c08a..8350532786 100644
--- a/arch/arm/include/asm/arch-omap3/spl.h
+++ b/arch/arm/include/asm/arch-omap3/spl.h
@@ -5,7 +5,7 @@
  * SPDX-License-Identifier:	GPL-2.0+
  */
 #ifndef	_ASM_ARCH_SPL_H_
-#define	_ASM_SPL_H_
+#define	_ASM_ARCH_SPL_H_
 
 #define BOOT_DEVICE_NONE	0
 #define BOOT_DEVICE_XIP		1
diff --git a/arch/arm/include/asm/arch-omap3/sys_proto.h b/arch/arm/include/asm/arch-omap3/sys_proto.h
index 43b54f7cae..44fa66f8a3 100644
--- a/arch/arm/include/asm/arch-omap3/sys_proto.h
+++ b/arch/arm/include/asm/arch-omap3/sys_proto.h
@@ -7,6 +7,7 @@
  */
 #ifndef _SYS_PROTO_H_
 #define _SYS_PROTO_H_
+#include <linux/mtd/omap_gpmc.h>
 
 typedef struct {
 	u32 mtype;
diff --git a/arch/arm/include/asm/arch-omap4/cpu.h b/arch/arm/include/asm/arch-omap4/cpu.h
index 545d9d96ad..c21fb54714 100644
--- a/arch/arm/include/asm/arch-omap4/cpu.h
+++ b/arch/arm/include/asm/arch-omap4/cpu.h
@@ -14,51 +14,6 @@
 
 #ifndef __KERNEL_STRICT_NAMES
 #ifndef __ASSEMBLY__
-struct gpmc_cs {
-	u32 config1;		/* 0x00 */
-	u32 config2;		/* 0x04 */
-	u32 config3;		/* 0x08 */
-	u32 config4;		/* 0x0C */
-	u32 config5;		/* 0x10 */
-	u32 config6;		/* 0x14 */
-	u32 config7;		/* 0x18 */
-	u32 nand_cmd;		/* 0x1C */
-	u32 nand_adr;		/* 0x20 */
-	u32 nand_dat;		/* 0x24 */
-	u8 res[8];		/* blow up to 0x30 byte */
-};
-
-struct gpmc {
-	u8 res1[0x10];
-	u32 sysconfig;		/* 0x10 */
-	u8 res2[0x4];
-	u32 irqstatus;		/* 0x18 */
-	u32 irqenable;		/* 0x1C */
-	u8 res3[0x20];
-	u32 timeout_control;	/* 0x40 */
-	u8 res4[0xC];
-	u32 config;		/* 0x50 */
-	u32 status;		/* 0x54 */
-	u8 res5[0x8];	/* 0x58 */
-	struct gpmc_cs cs[8];	/* 0x60, 0x90, .. */
-	u8 res6[0x14];		/* 0x1E0 */
-	u32 ecc_config;		/* 0x1F4 */
-	u32 ecc_control;	/* 0x1F8 */
-	u32 ecc_size_config;	/* 0x1FC */
-	u32 ecc1_result;	/* 0x200 */
-	u32 ecc2_result;	/* 0x204 */
-	u32 ecc3_result;	/* 0x208 */
-	u32 ecc4_result;	/* 0x20C */
-	u32 ecc5_result;	/* 0x210 */
-	u32 ecc6_result;	/* 0x214 */
-	u32 ecc7_result;	/* 0x218 */
-	u32 ecc8_result;	/* 0x21C */
-	u32 ecc9_result;	/* 0x220 */
-};
-
-/* Used for board specific gpmc initialization */
-extern struct gpmc *gpmc_cfg;
-
 struct gptimer {
 	u32 tidr;		/* 0x00 r */
 	u8 res[0xc];
diff --git a/arch/arm/include/asm/arch-omap4/omap.h b/arch/arm/include/asm/arch-omap4/omap.h
index e35f51c7bf..f66da0d603 100644
--- a/arch/arm/include/asm/arch-omap4/omap.h
+++ b/arch/arm/include/asm/arch-omap4/omap.h
@@ -116,7 +116,7 @@ struct s32ktimer {
  */
 #define NON_SECURE_SRAM_START	0x40304000
 #define NON_SECURE_SRAM_END	0x4030E000	/* Not inclusive */
-#define SRAM_SCRATCH_SPACE_ADDR	NON_SECURE_SRAM_START
+#define SRAM_SCRATCH_SPACE_ADDR	0x4030C000
 /* base address for indirect vectors (internal boot mode) */
 #define SRAM_ROM_VECT_BASE	0x4030D000
 
diff --git a/arch/arm/include/asm/arch-omap4/spl.h b/arch/arm/include/asm/arch-omap4/spl.h
index 551b27df14..fb842a2264 100644
--- a/arch/arm/include/asm/arch-omap4/spl.h
+++ b/arch/arm/include/asm/arch-omap4/spl.h
@@ -5,7 +5,7 @@
  * SPDX-License-Identifier:	GPL-2.0+
  */
 #ifndef	_ASM_ARCH_SPL_H_
-#define	_ASM_SPL_H_
+#define	_ASM_ARCH_SPL_H_
 
 #define BOOT_DEVICE_NONE	0
 #define BOOT_DEVICE_XIP		1
diff --git a/arch/arm/include/asm/arch-omap4/sys_proto.h b/arch/arm/include/asm/arch-omap4/sys_proto.h
index 39c531632e..b338a1566c 100644
--- a/arch/arm/include/asm/arch-omap4/sys_proto.h
+++ b/arch/arm/include/asm/arch-omap4/sys_proto.h
@@ -12,10 +12,15 @@
 #include <asm/arch/clock.h>
 #include <asm/io.h>
 #include <asm/omap_common.h>
+#include <linux/mtd/omap_gpmc.h>
 #include <asm/arch/mux_omap4.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
+extern const struct emif_regs emif_regs_elpida_200_mhz_2cs;
+extern const struct emif_regs emif_regs_elpida_380_mhz_1cs;
+extern const struct emif_regs emif_regs_elpida_400_mhz_1cs;
+extern const struct emif_regs emif_regs_elpida_400_mhz_2cs;
 struct omap_sysinfo {
 	char *board_string;
 };
@@ -26,7 +31,6 @@ void watchdog_init(void);
 u32 get_device_type(void);
 void do_set_mux(u32 base, struct pad_conf_entry const *array, int size);
 void set_muxconf_regs_essential(void);
-void set_muxconf_regs_non_essential(void);
 void sr32(void *, u32, u32, u32);
 u32 wait_on_value(u32, u32, void *, u32);
 void sdelay(unsigned long);
diff --git a/arch/arm/include/asm/arch-omap5/clock.h b/arch/arm/include/asm/arch-omap5/clock.h
index 9a2166ce4a..2dfe4efb4b 100644
--- a/arch/arm/include/asm/arch-omap5/clock.h
+++ b/arch/arm/include/asm/arch-omap5/clock.h
@@ -137,6 +137,9 @@
 #define HSMMC_CLKCTRL_CLKSEL_MASK		(1 << 24)
 #define HSMMC_CLKCTRL_CLKSEL_DIV_MASK		(1 << 25)
 
+/* CM_L3INIT_SATA_CLKCTRL */
+#define SATA_CLKCTRL_OPTFCLKEN_MASK		(1 << 8)
+
 /* CM_WKUP_GPTIMER1_CLKCTRL */
 #define GPTIMER1_CLKCTRL_CLKSEL_MASK		(1 << 24)
 
@@ -166,6 +169,16 @@
 #define OPTFCLKEN_USB_CH1_CLK_ENABLE	(1 << 9)
 #define OPTFCLKEN_USB_CH2_CLK_ENABLE	(1 << 10)
 
+/* CM_COREAON_USB_PHY_CORE_CLKCTRL */
+#define USBPHY_CORE_CLKCTRL_OPTFCLKEN_CLK32K	(1 << 8)
+
+/* CM_L3INIT_USB_OTG_SS_CLKCTRL */
+#define OTG_SS_CLKCTRL_MODULEMODE_HW	(1 << 0)
+#define OPTFCLKEN_REFCLK960M			(1 << 8)
+
+/* CM_L3INIT_OCP2SCP1_CLKCTRL */
+#define OCP2SCP1_CLKCTRL_MODULEMODE_HW	(1 << 0)
+
 /* CM_MPU_MPU_CLKCTRL */
 #define MPU_CLKCTRL_CLKSEL_EMIF_DIV_MODE_SHIFT	24
 #define MPU_CLKCTRL_CLKSEL_EMIF_DIV_MODE_MASK	(3 << 24)
@@ -192,6 +205,10 @@
 /* PRM_VC_VAL_BYPASS */
 #define PRM_VC_I2C_CHANNEL_FREQ_KHZ	400
 
+/* CTRL_CORE_SRCOMP_NORTH_SIDE */
+#define USB2PHY_DISCHGDET	(1 << 29)
+#define USB2PHY_AUTORESUME_EN (1 << 30)
+
 /* SMPS */
 #define SMPS_I2C_SLAVE_ADDR	0x12
 #define SMPS_REG_ADDR_12_MPU	0x23
diff --git a/arch/arm/include/asm/arch-omap5/cpu.h b/arch/arm/include/asm/arch-omap5/cpu.h
index fb5a568b69..5f1d7454d0 100644
--- a/arch/arm/include/asm/arch-omap5/cpu.h
+++ b/arch/arm/include/asm/arch-omap5/cpu.h
@@ -16,51 +16,6 @@
 
 #ifndef __KERNEL_STRICT_NAMES
 #ifndef __ASSEMBLY__
-struct gpmc_cs {
-	u32 config1;		/* 0x00 */
-	u32 config2;		/* 0x04 */
-	u32 config3;		/* 0x08 */
-	u32 config4;		/* 0x0C */
-	u32 config5;		/* 0x10 */
-	u32 config6;		/* 0x14 */
-	u32 config7;		/* 0x18 */
-	u32 nand_cmd;		/* 0x1C */
-	u32 nand_adr;		/* 0x20 */
-	u32 nand_dat;		/* 0x24 */
-	u8 res[8];		/* blow up to 0x30 byte */
-};
-
-struct gpmc {
-	u8 res1[0x10];
-	u32 sysconfig;		/* 0x10 */
-	u8 res2[0x4];
-	u32 irqstatus;		/* 0x18 */
-	u32 irqenable;		/* 0x1C */
-	u8 res3[0x20];
-	u32 timeout_control;	/* 0x40 */
-	u8 res4[0xC];
-	u32 config;		/* 0x50 */
-	u32 status;		/* 0x54 */
-	u8 res5[0x8];	/* 0x58 */
-	struct gpmc_cs cs[8];	/* 0x60, 0x90, .. */
-	u8 res6[0x14];		/* 0x1E0 */
-	u32 ecc_config;		/* 0x1F4 */
-	u32 ecc_control;	/* 0x1F8 */
-	u32 ecc_size_config;	/* 0x1FC */
-	u32 ecc1_result;	/* 0x200 */
-	u32 ecc2_result;	/* 0x204 */
-	u32 ecc3_result;	/* 0x208 */
-	u32 ecc4_result;	/* 0x20C */
-	u32 ecc5_result;	/* 0x210 */
-	u32 ecc6_result;	/* 0x214 */
-	u32 ecc7_result;	/* 0x218 */
-	u32 ecc8_result;	/* 0x21C */
-	u32 ecc9_result;	/* 0x220 */
-};
-
-/* Used for board specific gpmc initialization */
-extern struct gpmc *gpmc_cfg;
-
 struct gptimer {
 	u32 tidr;		/* 0x00 r */
 	u8 res1[0xc];
diff --git a/arch/arm/include/asm/arch-omap5/omap.h b/arch/arm/include/asm/arch-omap5/omap.h
index 414d37a5a7..19fdecec01 100644
--- a/arch/arm/include/asm/arch-omap5/omap.h
+++ b/arch/arm/include/asm/arch-omap5/omap.h
@@ -44,6 +44,7 @@
 #define OMAP5432_CONTROL_ID_CODE_ES1_0		0x0B99802F
 #define OMAP5432_CONTROL_ID_CODE_ES2_0          0x1B99802F
 #define DRA752_CONTROL_ID_CODE_ES1_0		0x0B99002F
+#define DRA752_CONTROL_ID_CODE_ES1_1		0x1B99002F
 
 /* UART */
 #define UART1_BASE		(OMAP54XX_L4_PER_BASE + 0x6a000)
@@ -64,6 +65,9 @@
 /* QSPI */
 #define QSPI_BASE		0x4B300000
 
+/* SATA */
+#define DWC_AHSATA_BASE		0x4A140000
+
 /*
  * Hardware Register Details
  */
@@ -145,9 +149,9 @@ struct s32ktimer {
 #define DDR_IO_2_VREF_CELLS_DDR3_VALUE				0x0
 
 #define DDR_IO_I_40OHM_SR_SLOWEST_WD_DQ_NO_PULL_DQS_NO_PULL_ES2 0x7C7C7C7C
-#define DDR_IO_I_40OHM_SR_FAST_WD_DQ_NO_PULL_DQS_NO_PULL_ES2 0x64656465
+#define DDR_IO_I_40OHM_SR_FAST_WD_DQ_NO_PULL_DQS_NO_PULL_ES2 0x64646464
 #define DDR_IO_0_VREF_CELLS_DDR3_VALUE_ES2 0xBAE8C631
-#define DDR_IO_1_VREF_CELLS_DDR3_VALUE_ES2 0xB46318D8
+#define DDR_IO_1_VREF_CELLS_DDR3_VALUE_ES2 0xBC6318DC
 #define DDR_IO_2_VREF_CELLS_DDR3_VALUE_ES2 0x84210000
 
 #define EFUSE_1 0x45145100
@@ -201,6 +205,8 @@ struct s32ktimer {
 /* ABB efuse masks */
 #define OMAP5_ABB_FUSE_VSET_MASK		(0x1F << 24)
 #define OMAP5_ABB_FUSE_ENABLE_MASK		(0x1 << 29)
+#define DRA7_ABB_FUSE_VSET_MASK			(0x1F << 20)
+#define DRA7_ABB_FUSE_ENABLE_MASK		(0x1 << 25)
 #define OMAP5_ABB_LDOVBBMPU_MUX_CTRL_MASK	(0x1 << 10)
 #define OMAP5_ABB_LDOVBBMPU_VSET_OUT_MASK	(0x1f << 0)
 
@@ -239,6 +245,7 @@ struct ctrl_ioregs {
 	u32 ctrl_ddrio_1;
 	u32 ctrl_ddrio_2;
 	u32 ctrl_emif_sdram_config_ext;
+	u32 ctrl_emif_sdram_config_ext_final;
 	u32 ctrl_ddr_ctrl_ext_0;
 };
 
diff --git a/arch/arm/include/asm/arch-omap5/sata.h b/arch/arm/include/asm/arch-omap5/sata.h
new file mode 100644
index 0000000000..b69165b5ee
--- /dev/null
+++ b/arch/arm/include/asm/arch-omap5/sata.h
@@ -0,0 +1,39 @@
+/*
+ * SATA Wrapper Register map
+ *
+ * (C) Copyright 2013
+ * Texas Instruments, <www.ti.com>
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#ifndef _TI_SATA_H
+#define _TI_SATA_H
+
+/* SATA Wrapper module */
+#define TI_SATA_WRAPPER_BASE		(OMAP54XX_L4_CORE_BASE + 0x141100)
+/* SATA PHY Module */
+#define TI_SATA_PLLCTRL_BASE		(OMAP54XX_L4_CORE_BASE + 0x96800)
+
+/* SATA Wrapper register offsets */
+#define TI_SATA_SYSCONFIG			0x00
+#define TI_SATA_CDRLOCK				0x04
+
+/* Register Set */
+#define TI_SATA_SYSCONFIG_OVERRIDE0		(1 << 16)
+#define TI_SATA_SYSCONFIG_STANDBY_MASK		(0x3 << 4)
+#define TI_SATA_SYSCONFIG_IDLE_MASK		(0x3 << 2)
+
+/* Standby modes */
+#define TI_SATA_STANDBY_FORCE			0x0
+#define TI_SATA_STANDBY_NO			(0x1 << 4)
+#define TI_SATA_STANDBY_SMART_WAKE		(0x3 << 4)
+#define TI_SATA_STANDBY_SMART			(0x2 << 4)
+
+/* Idle modes */
+#define TI_SATA_IDLE_FORCE			0x0
+#define TI_SATA_IDLE_NO				(0x1 << 2)
+#define TI_SATA_IDLE_SMART_WAKE			(0x3 << 2)
+#define TI_SATA_IDLE_SMART			(0x2 << 2)
+
+#endif /* _TI_SATA_H */
diff --git a/arch/arm/include/asm/arch-omap5/spl.h b/arch/arm/include/asm/arch-omap5/spl.h
index 57f0de5ffe..f70799860f 100644
--- a/arch/arm/include/asm/arch-omap5/spl.h
+++ b/arch/arm/include/asm/arch-omap5/spl.h
@@ -5,7 +5,7 @@
  * SPDX-License-Identifier:	GPL-2.0+
  */
 #ifndef	_ASM_ARCH_SPL_H_
-#define	_ASM_SPL_H_
+#define	_ASM_ARCH_SPL_H_
 
 #define BOOT_DEVICE_NONE        0
 #define BOOT_DEVICE_XIP         1
@@ -15,7 +15,9 @@
 #define BOOT_DEVICE_MMC1        5
 #define BOOT_DEVICE_MMC2        6
 #define BOOT_DEVICE_MMC2_2	7
+#define BOOT_DEVICE_SATA	9
 #define BOOT_DEVICE_SPI		10
+#define BOOT_DEVICE_UART	0x43
 
 #define MMC_BOOT_DEVICES_START	BOOT_DEVICE_MMC1
 #define MMC_BOOT_DEVICES_END	BOOT_DEVICE_MMC2_2
diff --git a/arch/arm/include/asm/arch-omap5/sys_proto.h b/arch/arm/include/asm/arch-omap5/sys_proto.h
index 9e70d48f43..9e007c87ae 100644
--- a/arch/arm/include/asm/arch-omap5/sys_proto.h
+++ b/arch/arm/include/asm/arch-omap5/sys_proto.h
@@ -12,6 +12,7 @@
 #include <asm/io.h>
 #include <asm/arch/clock.h>
 #include <asm/omap_common.h>
+#include <linux/mtd/omap_gpmc.h>
 #include <asm/arch/clock.h>
 
 DECLARE_GLOBAL_DATA_PTR;
@@ -31,7 +32,6 @@ void watchdog_init(void);
 u32 get_device_type(void);
 void do_set_mux(u32 base, struct pad_conf_entry const *array, int size);
 void set_muxconf_regs_essential(void);
-void set_muxconf_regs_non_essential(void);
 void sr32(void *, u32, u32, u32);
 u32 wait_on_value(u32, u32, void *, u32);
 void sdelay(unsigned long);
diff --git a/arch/arm/include/asm/arch-pxa/hardware.h b/arch/arm/include/asm/arch-pxa/hardware.h
index 2397bcef0d..e671c143ac 100644
--- a/arch/arm/include/asm/arch-pxa/hardware.h
+++ b/arch/arm/include/asm/arch-pxa/hardware.h
@@ -18,7 +18,6 @@
 #ifndef __ASM_ARCH_HARDWARE_H
 #define __ASM_ARCH_HARDWARE_H
 
-#include <linux/config.h>
 #include <asm/mach-types.h>
 
 /*
diff --git a/arch/arm/include/asm/arch-rmobile/gpio.h b/arch/arm/include/asm/arch-rmobile/gpio.h
index 6b5e4ed4eb..560e9f42d9 100644
--- a/arch/arm/include/asm/arch-rmobile/gpio.h
+++ b/arch/arm/include/asm/arch-rmobile/gpio.h
@@ -7,6 +7,12 @@ void sh73a0_pinmux_init(void);
 #elif defined(CONFIG_R8A7740)
 #include "r8a7740-gpio.h"
 void r8a7740_pinmux_init(void);
+#elif defined(CONFIG_R8A7790)
+#include "r8a7790-gpio.h"
+void r8a7790_pinmux_init(void);
+#elif defined(CONFIG_R8A7791)
+#include "r8a7791-gpio.h"
+void r8a7791_pinmux_init(void);
 #endif
 
 #endif /* __ASM_ARCH_GPIO_H */
diff --git a/arch/arm/include/asm/arch-rmobile/r8a7790-gpio.h b/arch/arm/include/asm/arch-rmobile/r8a7790-gpio.h
new file mode 100644
index 0000000000..444e361c06
--- /dev/null
+++ b/arch/arm/include/asm/arch-rmobile/r8a7790-gpio.h
@@ -0,0 +1,387 @@
+#ifndef __ASM_R8A7790_H__
+#define __ASM_R8A7790_H__
+
+/* Pin Function Controller:
+ * GPIO_FN_xx - GPIO used to select pin function
+ * GPIO_GP_x_x - GPIO mapped to real I/O pin on CPU
+ */
+enum {
+	GPIO_GP_0_0, GPIO_GP_0_1, GPIO_GP_0_2, GPIO_GP_0_3,
+	GPIO_GP_0_4, GPIO_GP_0_5, GPIO_GP_0_6, GPIO_GP_0_7,
+	GPIO_GP_0_8, GPIO_GP_0_9, GPIO_GP_0_10, GPIO_GP_0_11,
+	GPIO_GP_0_12, GPIO_GP_0_13, GPIO_GP_0_14, GPIO_GP_0_15,
+	GPIO_GP_0_16, GPIO_GP_0_17, GPIO_GP_0_18, GPIO_GP_0_19,
+	GPIO_GP_0_20, GPIO_GP_0_21, GPIO_GP_0_22, GPIO_GP_0_23,
+	GPIO_GP_0_24, GPIO_GP_0_25, GPIO_GP_0_26, GPIO_GP_0_27,
+	GPIO_GP_0_28, GPIO_GP_0_29, GPIO_GP_0_30, GPIO_GP_0_31,
+
+	GPIO_GP_1_0, GPIO_GP_1_1, GPIO_GP_1_2, GPIO_GP_1_3,
+	GPIO_GP_1_4, GPIO_GP_1_5, GPIO_GP_1_6, GPIO_GP_1_7,
+	GPIO_GP_1_8, GPIO_GP_1_9, GPIO_GP_1_10, GPIO_GP_1_11,
+	GPIO_GP_1_12, GPIO_GP_1_13, GPIO_GP_1_14, GPIO_GP_1_15,
+	GPIO_GP_1_16, GPIO_GP_1_17, GPIO_GP_1_18, GPIO_GP_1_19,
+	GPIO_GP_1_20, GPIO_GP_1_21, GPIO_GP_1_22, GPIO_GP_1_23,
+	GPIO_GP_1_24, GPIO_GP_1_25, GPIO_GP_1_26, GPIO_GP_1_27,
+	GPIO_GP_1_28, GPIO_GP_1_29,
+
+	GPIO_GP_2_0, GPIO_GP_2_1, GPIO_GP_2_2, GPIO_GP_2_3,
+	GPIO_GP_2_4, GPIO_GP_2_5, GPIO_GP_2_6, GPIO_GP_2_7,
+	GPIO_GP_2_8, GPIO_GP_2_9, GPIO_GP_2_10, GPIO_GP_2_11,
+	GPIO_GP_2_12, GPIO_GP_2_13, GPIO_GP_2_14, GPIO_GP_2_15,
+	GPIO_GP_2_16, GPIO_GP_2_17, GPIO_GP_2_18, GPIO_GP_2_19,
+	GPIO_GP_2_20, GPIO_GP_2_21, GPIO_GP_2_22, GPIO_GP_2_23,
+	GPIO_GP_2_24, GPIO_GP_2_25, GPIO_GP_2_26, GPIO_GP_2_27,
+	GPIO_GP_2_28, GPIO_GP_2_29,
+
+	GPIO_GP_3_0, GPIO_GP_3_1, GPIO_GP_3_2, GPIO_GP_3_3,
+	GPIO_GP_3_4, GPIO_GP_3_5, GPIO_GP_3_6, GPIO_GP_3_7,
+	GPIO_GP_3_8, GPIO_GP_3_9, GPIO_GP_3_10, GPIO_GP_3_11,
+	GPIO_GP_3_12, GPIO_GP_3_13, GPIO_GP_3_14, GPIO_GP_3_15,
+	GPIO_GP_3_16, GPIO_GP_3_17, GPIO_GP_3_18, GPIO_GP_3_19,
+	GPIO_GP_3_20, GPIO_GP_3_21, GPIO_GP_3_22, GPIO_GP_3_23,
+	GPIO_GP_3_24, GPIO_GP_3_25, GPIO_GP_3_26, GPIO_GP_3_27,
+	GPIO_GP_3_28, GPIO_GP_3_29, GPIO_GP_3_30, GPIO_GP_3_31,
+
+	GPIO_GP_4_0, GPIO_GP_4_1, GPIO_GP_4_2, GPIO_GP_4_3,
+	GPIO_GP_4_4, GPIO_GP_4_5, GPIO_GP_4_6, GPIO_GP_4_7,
+	GPIO_GP_4_8, GPIO_GP_4_9, GPIO_GP_4_10, GPIO_GP_4_11,
+	GPIO_GP_4_12, GPIO_GP_4_13, GPIO_GP_4_14, GPIO_GP_4_15,
+	GPIO_GP_4_16, GPIO_GP_4_17, GPIO_GP_4_18, GPIO_GP_4_19,
+	GPIO_GP_4_20, GPIO_GP_4_21, GPIO_GP_4_22, GPIO_GP_4_23,
+	GPIO_GP_4_24, GPIO_GP_4_25, GPIO_GP_4_26, GPIO_GP_4_27,
+	GPIO_GP_4_28, GPIO_GP_4_29, GPIO_GP_4_30, GPIO_GP_4_31,
+
+	GPIO_GP_5_0, GPIO_GP_5_1, GPIO_GP_5_2, GPIO_GP_5_3,
+	GPIO_GP_5_4, GPIO_GP_5_5, GPIO_GP_5_6, GPIO_GP_5_7,
+	GPIO_GP_5_8, GPIO_GP_5_9, GPIO_GP_5_10, GPIO_GP_5_11,
+	GPIO_GP_5_12, GPIO_GP_5_13, GPIO_GP_5_14, GPIO_GP_5_15,
+	GPIO_GP_5_16, GPIO_GP_5_17, GPIO_GP_5_18, GPIO_GP_5_19,
+	GPIO_GP_5_20, GPIO_GP_5_21, GPIO_GP_5_22, GPIO_GP_5_23,
+	GPIO_GP_5_24, GPIO_GP_5_25, GPIO_GP_5_26, GPIO_GP_5_27,
+	GPIO_GP_5_28, GPIO_GP_5_29, GPIO_GP_5_30, GPIO_GP_5_31,
+
+	GPIO_FN_VI1_DATA7_VI1_B7, GPIO_FN_USB0_PWEN, GPIO_FN_USB0_OVC_VBUS,
+	GPIO_FN_USB2_PWEN, GPIO_FN_USB2_OVC, GPIO_FN_AVS1, GPIO_FN_AVS2,
+	GPIO_FN_DU_DOTCLKIN0, GPIO_FN_DU_DOTCLKIN2,
+
+	/* IPSR0 */
+	GPIO_FN_D1, GPIO_FN_MSIOF3_SYNC_B, GPIO_FN_VI3_DATA1, GPIO_FN_VI0_G5,
+	GPIO_FN_VI0_G5_B, GPIO_FN_D2, GPIO_FN_MSIOF3_RXD_B, GPIO_FN_VI3_DATA2,
+	GPIO_FN_VI0_G6, GPIO_FN_VI0_G6_B, GPIO_FN_D3, GPIO_FN_MSIOF3_TXD_B,
+	GPIO_FN_VI3_DATA3, GPIO_FN_VI0_G7, GPIO_FN_VI0_G7_B, GPIO_FN_D4,
+	GPIO_FN_SCIFB1_RXD_F, GPIO_FN_SCIFB0_RXD_C, GPIO_FN_VI3_DATA4,
+	GPIO_FN_VI0_R0, GPIO_FN_VI0_R0_B, GPIO_FN_RX0_B, GPIO_FN_D5,
+	GPIO_FN_SCIFB1_TXD_F, GPIO_FN_SCIFB0_TXD_C, GPIO_FN_VI3_DATA5,
+	GPIO_FN_VI0_R1, GPIO_FN_VI0_R1_B, GPIO_FN_TX0_B, GPIO_FN_D6,
+	GPIO_FN_SCL2_C, GPIO_FN_VI3_DATA6, GPIO_FN_VI0_R2, GPIO_FN_VI0_R2_B,
+	GPIO_FN_SCL2_CIS_C, GPIO_FN_D7, GPIO_FN_AD_DI_B, GPIO_FN_SDA2_C,
+	GPIO_FN_VI3_DATA7, GPIO_FN_VI0_R3, GPIO_FN_VI0_R3_B, GPIO_FN_SDA2_CIS_C,
+	GPIO_FN_D8, GPIO_FN_SCIFA1_SCK_C, GPIO_FN_AVB_TXD0, GPIO_FN_MII_TXD0,
+	GPIO_FN_VI0_G0, GPIO_FN_VI0_G0_B, GPIO_FN_VI2_DATA0_VI2_B0,
+
+	/* IPSR1 */
+	GPIO_FN_D9, GPIO_FN_SCIFA1_RXD_C, GPIO_FN_AVB_TXD1, GPIO_FN_MII_TXD1,
+	GPIO_FN_VI0_G1, GPIO_FN_VI0_G1_B, GPIO_FN_VI2_DATA1_VI2_B1, GPIO_FN_D10,
+	GPIO_FN_SCIFA1_TXD_C, GPIO_FN_AVB_TXD2, GPIO_FN_MII_TXD2,
+	GPIO_FN_VI0_G2, GPIO_FN_VI0_G2_B, GPIO_FN_VI2_DATA2_VI2_B2, GPIO_FN_D11,
+	GPIO_FN_SCIFA1_CTS_N_C, GPIO_FN_AVB_TXD3, GPIO_FN_MII_TXD3,
+	GPIO_FN_VI0_G3, GPIO_FN_VI0_G3_B, GPIO_FN_VI2_DATA3_VI2_B3,
+	GPIO_FN_D12, GPIO_FN_SCIFA1_RTS_N_C, GPIO_FN_AVB_TXD4,
+	GPIO_FN_VI0_HSYNC_N, GPIO_FN_VI0_HSYNC_N_B, GPIO_FN_VI2_DATA4_VI2_B4,
+	GPIO_FN_D13, GPIO_FN_AVB_TXD5, GPIO_FN_VI0_VSYNC_N,
+	GPIO_FN_VI0_VSYNC_N_B, GPIO_FN_VI2_DATA5_VI2_B5, GPIO_FN_D14,
+	GPIO_FN_SCIFB1_RXD_C, GPIO_FN_AVB_TXD6, GPIO_FN_RX1_B,
+	GPIO_FN_VI0_CLKENB, GPIO_FN_VI0_CLKENB_B, GPIO_FN_VI2_DATA6_VI2_B6,
+	GPIO_FN_D15, GPIO_FN_SCIFB1_TXD_C, GPIO_FN_AVB_TXD7, GPIO_FN_TX1_B,
+	GPIO_FN_VI0_FIELD, GPIO_FN_VI0_FIELD_B, GPIO_FN_VI2_DATA7_VI2_B7,
+	GPIO_FN_A0, GPIO_FN_PWM3, GPIO_FN_A1, GPIO_FN_PWM4,
+
+	/* IPSR2 */
+	GPIO_FN_A2, GPIO_FN_PWM5, GPIO_FN_MSIOF1_SS1_B, GPIO_FN_A3,
+	GPIO_FN_PWM6, GPIO_FN_MSIOF1_SS2_B, GPIO_FN_A4, GPIO_FN_MSIOF1_TXD_B,
+	GPIO_FN_TPU0TO0, GPIO_FN_A5, GPIO_FN_SCIFA1_TXD_B, GPIO_FN_TPU0TO1,
+	GPIO_FN_A6, GPIO_FN_SCIFA1_RTS_N_B, GPIO_FN_TPU0TO2, GPIO_FN_A7,
+	GPIO_FN_SCIFA1_SCK_B, GPIO_FN_AUDIO_CLKOUT_B, GPIO_FN_TPU0TO3,
+	GPIO_FN_A8, GPIO_FN_SCIFA1_RXD_B, GPIO_FN_SSI_SCK5_B, GPIO_FN_VI0_R4,
+	GPIO_FN_VI0_R4_B, GPIO_FN_SCIFB2_RXD_C, GPIO_FN_VI2_DATA0_VI2_B0_B,
+	GPIO_FN_A9, GPIO_FN_SCIFA1_CTS_N_B, GPIO_FN_SSI_WS5_B, GPIO_FN_VI0_R5,
+	GPIO_FN_VI0_R5_B, GPIO_FN_SCIFB2_TXD_C, GPIO_FN_VI2_DATA1_VI2_B1_B,
+	GPIO_FN_A10, GPIO_FN_SSI_SDATA5_B, GPIO_FN_MSIOF2_SYNC, GPIO_FN_VI0_R6,
+	GPIO_FN_VI0_R6_B, GPIO_FN_VI2_DATA2_VI2_B2_B,
+
+	/* IPSR3 */
+	GPIO_FN_A11, GPIO_FN_SCIFB2_CTS_N_B, GPIO_FN_MSIOF2_SCK, GPIO_FN_VI1_R0,
+	GPIO_FN_VI1_R0_B, GPIO_FN_VI2_G0, GPIO_FN_VI2_DATA3_VI2_B3_B,
+	GPIO_FN_A12, GPIO_FN_SCIFB2_RXD_B, GPIO_FN_MSIOF2_TXD, GPIO_FN_VI1_R1,
+	GPIO_FN_VI1_R1_B, GPIO_FN_VI2_G1, GPIO_FN_VI2_DATA4_VI2_B4_B,
+	GPIO_FN_A13, GPIO_FN_SCIFB2_RTS_N_B, GPIO_FN_EX_WAIT2,
+	GPIO_FN_MSIOF2_RXD, GPIO_FN_VI1_R2, GPIO_FN_VI1_R2_B, GPIO_FN_VI2_G2,
+	GPIO_FN_VI2_DATA5_VI2_B5_B, GPIO_FN_A14, GPIO_FN_SCIFB2_TXD_B,
+	GPIO_FN_ATACS11_N, GPIO_FN_MSIOF2_SS1, GPIO_FN_A15,
+	GPIO_FN_SCIFB2_SCK_B, GPIO_FN_ATARD1_N, GPIO_FN_MSIOF2_SS2, GPIO_FN_A16,
+	GPIO_FN_ATAWR1_N, GPIO_FN_A17, GPIO_FN_AD_DO_B, GPIO_FN_ATADIR1_N,
+	GPIO_FN_A18, GPIO_FN_AD_CLK_B, GPIO_FN_ATAG1_N, GPIO_FN_A19,
+	GPIO_FN_AD_NCS_N_B, GPIO_FN_ATACS01_N, GPIO_FN_EX_WAIT0_B, GPIO_FN_A20,
+	GPIO_FN_SPCLK, GPIO_FN_VI1_R3, GPIO_FN_VI1_R3_B, GPIO_FN_VI2_G4,
+
+	/* IPSR4 */
+	GPIO_FN_A21, GPIO_FN_MOSI_IO0, GPIO_FN_VI1_R4, GPIO_FN_VI1_R4_B,
+	GPIO_FN_VI2_G5, GPIO_FN_A22, GPIO_FN_MISO_IO1, GPIO_FN_VI1_R5,
+	GPIO_FN_VI1_R5_B, GPIO_FN_VI2_G6, GPIO_FN_A23, GPIO_FN_IO2,
+	GPIO_FN_VI1_G7, GPIO_FN_VI1_G7_B, GPIO_FN_VI2_G7, GPIO_FN_A24,
+	GPIO_FN_IO3, GPIO_FN_VI1_R7, GPIO_FN_VI1_R7_B, GPIO_FN_VI2_CLKENB,
+	GPIO_FN_VI2_CLKENB_B, GPIO_FN_A25, GPIO_FN_SSL, GPIO_FN_VI1_G6,
+	GPIO_FN_VI1_G6_B, GPIO_FN_VI2_FIELD, GPIO_FN_VI2_FIELD_B, GPIO_FN_CS0_N,
+	GPIO_FN_VI1_R6, GPIO_FN_VI1_R6_B, GPIO_FN_VI2_G3, GPIO_FN_MSIOF0_SS2_B,
+	GPIO_FN_CS1_N_A26, GPIO_FN_SPEEDIN, GPIO_FN_VI0_R7, GPIO_FN_VI0_R7_B,
+	GPIO_FN_VI2_CLK, GPIO_FN_VI2_CLK_B, GPIO_FN_EX_CS0_N, GPIO_FN_HRX1_B,
+	GPIO_FN_VI1_G5, GPIO_FN_VI1_G5_B, GPIO_FN_VI2_R0, GPIO_FN_HTX0_B,
+	GPIO_FN_MSIOF0_SS1_B, GPIO_FN_EX_CS1_N, GPIO_FN_GPS_CLK,
+	GPIO_FN_HCTS1_N_B, GPIO_FN_VI1_FIELD, GPIO_FN_VI1_FIELD_B,
+	GPIO_FN_VI2_R1, GPIO_FN_EX_CS2_N, GPIO_FN_GPS_SIGN, GPIO_FN_HRTS1_N_B,
+	GPIO_FN_VI3_CLKENB, GPIO_FN_VI1_G0, GPIO_FN_VI1_G0_B, GPIO_FN_VI2_R2,
+
+	/* IPSR5 */
+	GPIO_FN_EX_CS3_N, GPIO_FN_GPS_MAG, GPIO_FN_VI3_FIELD, GPIO_FN_VI1_G1,
+	GPIO_FN_VI1_G1_B, GPIO_FN_VI2_R3, GPIO_FN_EX_CS4_N,
+	GPIO_FN_MSIOF1_SCK_B, GPIO_FN_VI3_HSYNC_N,
+	GPIO_FN_VI2_HSYNC_N, GPIO_FN_SCL1, GPIO_FN_VI2_HSYNC_N_B,
+	GPIO_FN_INTC_EN0_N, GPIO_FN_SCL1_CIS, GPIO_FN_EX_CS5_N, GPIO_FN_CAN0_RX,
+	GPIO_FN_MSIOF1_RXD_B, GPIO_FN_VI3_VSYNC_N, GPIO_FN_VI1_G2,
+	GPIO_FN_VI1_G2_B, GPIO_FN_VI2_R4, GPIO_FN_SDA1, GPIO_FN_INTC_EN1_N,
+	GPIO_FN_SDA1_CIS, GPIO_FN_BS_N, GPIO_FN_IETX, GPIO_FN_HTX1_B,
+	GPIO_FN_CAN1_TX, GPIO_FN_DRACK0, GPIO_FN_IETX_C, GPIO_FN_RD_N,
+	GPIO_FN_CAN0_TX, GPIO_FN_SCIFA0_SCK_B, GPIO_FN_RD_WR_N, GPIO_FN_VI1_G3,
+	GPIO_FN_VI1_G3_B, GPIO_FN_VI2_R5, GPIO_FN_SCIFA0_RXD_B,
+	GPIO_FN_INTC_IRQ4_N, GPIO_FN_WE0_N, GPIO_FN_IECLK, GPIO_FN_CAN_CLK,
+	GPIO_FN_VI2_VSYNC_N, GPIO_FN_SCIFA0_TXD_B, GPIO_FN_VI2_VSYNC_N_B,
+	GPIO_FN_WE1_N, GPIO_FN_IERX, GPIO_FN_CAN1_RX, GPIO_FN_VI1_G4,
+	GPIO_FN_VI1_G4_B, GPIO_FN_VI2_R6, GPIO_FN_SCIFA0_CTS_N_B,
+	GPIO_FN_IERX_C, GPIO_FN_EX_WAIT0, GPIO_FN_IRQ3, GPIO_FN_INTC_IRQ3_N,
+	GPIO_FN_VI3_CLK, GPIO_FN_SCIFA0_RTS_N_B, GPIO_FN_HRX0_B,
+	GPIO_FN_MSIOF0_SCK_B, GPIO_FN_DREQ0_N, GPIO_FN_VI1_HSYNC_N,
+	GPIO_FN_VI1_HSYNC_N_B, GPIO_FN_VI2_R7, GPIO_FN_SSI_SCK78_C,
+	GPIO_FN_SSI_WS78_B,
+
+	/* IPSR6 */
+	GPIO_FN_DACK0, GPIO_FN_IRQ0, GPIO_FN_INTC_IRQ0_N, GPIO_FN_SSI_SCK6_B,
+	GPIO_FN_VI1_VSYNC_N, GPIO_FN_VI1_VSYNC_N_B, GPIO_FN_SSI_WS78_C,
+	GPIO_FN_DREQ1_N, GPIO_FN_VI1_CLKENB, GPIO_FN_VI1_CLKENB_B,
+	GPIO_FN_SSI_SDATA7_C, GPIO_FN_SSI_SCK78_B, GPIO_FN_DACK1, GPIO_FN_IRQ1,
+	GPIO_FN_INTC_IRQ1_N, GPIO_FN_SSI_WS6_B, GPIO_FN_SSI_SDATA8_C,
+	GPIO_FN_DREQ2_N, GPIO_FN_HSCK1_B, GPIO_FN_HCTS0_N_B,
+	GPIO_FN_MSIOF0_TXD_B, GPIO_FN_DACK2, GPIO_FN_IRQ2, GPIO_FN_INTC_IRQ2_N,
+	GPIO_FN_SSI_SDATA6_B, GPIO_FN_HRTS0_N_B, GPIO_FN_MSIOF0_RXD_B,
+	GPIO_FN_ETH_CRS_DV, GPIO_FN_RMII_CRS_DV, GPIO_FN_STP_ISCLK_0_B,
+	GPIO_FN_TS_SDEN0_D, GPIO_FN_GLO_Q0_C, GPIO_FN_SCL2_E,
+	GPIO_FN_SCL2_CIS_E, GPIO_FN_ETH_RX_ER, GPIO_FN_RMII_RX_ER,
+	GPIO_FN_STP_ISD_0_B, GPIO_FN_TS_SPSYNC0_D, GPIO_FN_GLO_Q1_C,
+	GPIO_FN_SDA2_E, GPIO_FN_SDA2_CIS_E, GPIO_FN_ETH_RXD0, GPIO_FN_RMII_RXD0,
+	GPIO_FN_STP_ISEN_0_B, GPIO_FN_TS_SDAT0_D, GPIO_FN_GLO_I0_C,
+	GPIO_FN_SCIFB1_SCK_G, GPIO_FN_SCK1_E, GPIO_FN_ETH_RXD1,
+	GPIO_FN_RMII_RXD1, GPIO_FN_HRX0_E, GPIO_FN_STP_ISSYNC_0_B,
+	GPIO_FN_TS_SCK0_D, GPIO_FN_GLO_I1_C, GPIO_FN_SCIFB1_RXD_G,
+	GPIO_FN_RX1_E, GPIO_FN_ETH_LINK, GPIO_FN_RMII_LINK, GPIO_FN_HTX0_E,
+	GPIO_FN_STP_IVCXO27_0_B, GPIO_FN_SCIFB1_TXD_G, GPIO_FN_TX1_E,
+	GPIO_FN_ETH_REF_CLK, GPIO_FN_RMII_REF_CLK, GPIO_FN_HCTS0_N_E,
+	GPIO_FN_STP_IVCXO27_1_B, GPIO_FN_HRX0_F,
+
+	/* IPSR7 */
+	GPIO_FN_ETH_MDIO, GPIO_FN_RMII_MDIO, GPIO_FN_HRTS0_N_E,
+	GPIO_FN_SIM0_D_C, GPIO_FN_HCTS0_N_F, GPIO_FN_ETH_TXD1,
+	GPIO_FN_RMII_TXD1, GPIO_FN_HTX0_F, GPIO_FN_BPFCLK_G, GPIO_FN_RDS_CLK_F,
+	GPIO_FN_ETH_TX_EN, GPIO_FN_RMII_TX_EN, GPIO_FN_SIM0_CLK_C,
+	GPIO_FN_HRTS0_N_F, GPIO_FN_ETH_MAGIC, GPIO_FN_RMII_MAGIC,
+	GPIO_FN_SIM0_RST_C, GPIO_FN_ETH_TXD0, GPIO_FN_RMII_TXD0,
+	GPIO_FN_STP_ISCLK_1_B, GPIO_FN_TS_SDEN1_C, GPIO_FN_GLO_SCLK_C,
+	GPIO_FN_ETH_MDC, GPIO_FN_RMII_MDC, GPIO_FN_STP_ISD_1_B,
+	GPIO_FN_TS_SPSYNC1_C, GPIO_FN_GLO_SDATA_C, GPIO_FN_PWM0,
+	GPIO_FN_SCIFA2_SCK_C, GPIO_FN_STP_ISEN_1_B, GPIO_FN_TS_SDAT1_C,
+	GPIO_FN_GLO_SS_C, GPIO_FN_PWM1, GPIO_FN_SCIFA2_TXD_C,
+	GPIO_FN_STP_ISSYNC_1_B, GPIO_FN_TS_SCK1_C, GPIO_FN_GLO_RFON_C,
+	GPIO_FN_PCMOE_N, GPIO_FN_PWM2, GPIO_FN_PWMFSW0, GPIO_FN_SCIFA2_RXD_C,
+	GPIO_FN_PCMWE_N, GPIO_FN_IECLK_C, GPIO_FN_DU1_DOTCLKIN,
+	GPIO_FN_AUDIO_CLKC, GPIO_FN_AUDIO_CLKOUT_C, GPIO_FN_VI0_CLK,
+	GPIO_FN_ATACS00_N, GPIO_FN_AVB_RXD1, GPIO_FN_MII_RXD1,
+	GPIO_FN_VI0_DATA0_VI0_B0, GPIO_FN_ATACS10_N, GPIO_FN_AVB_RXD2,
+	GPIO_FN_MII_RXD2,
+
+	/* IPSR8 */
+	GPIO_FN_VI0_DATA1_VI0_B1, GPIO_FN_ATARD0_N, GPIO_FN_AVB_RXD3,
+	GPIO_FN_MII_RXD3, GPIO_FN_VI0_DATA2_VI0_B2, GPIO_FN_ATAWR0_N,
+	GPIO_FN_AVB_RXD4, GPIO_FN_VI0_DATA3_VI0_B3, GPIO_FN_ATADIR0_N,
+	GPIO_FN_AVB_RXD5, GPIO_FN_VI0_DATA4_VI0_B4, GPIO_FN_ATAG0_N,
+	GPIO_FN_AVB_RXD6, GPIO_FN_VI0_DATA5_VI0_B5, GPIO_FN_EX_WAIT1,
+	GPIO_FN_AVB_RXD7, GPIO_FN_VI0_DATA6_VI0_B6, GPIO_FN_AVB_RX_ER,
+	GPIO_FN_MII_RX_ER, GPIO_FN_VI0_DATA7_VI0_B7, GPIO_FN_AVB_RX_CLK,
+	GPIO_FN_MII_RX_CLK, GPIO_FN_VI1_CLK, GPIO_FN_AVB_RX_DV,
+	GPIO_FN_MII_RX_DV, GPIO_FN_VI1_DATA0_VI1_B0, GPIO_FN_SCIFA1_SCK_D,
+	GPIO_FN_AVB_CRS, GPIO_FN_MII_CRS, GPIO_FN_VI1_DATA1_VI1_B1,
+	GPIO_FN_SCIFA1_RXD_D, GPIO_FN_AVB_MDC, GPIO_FN_MII_MDC,
+	GPIO_FN_VI1_DATA2_VI1_B2, GPIO_FN_SCIFA1_TXD_D, GPIO_FN_AVB_MDIO,
+	GPIO_FN_MII_MDIO, GPIO_FN_VI1_DATA3_VI1_B3, GPIO_FN_SCIFA1_CTS_N_D,
+	GPIO_FN_AVB_GTX_CLK, GPIO_FN_VI1_DATA4_VI1_B4, GPIO_FN_SCIFA1_RTS_N_D,
+	GPIO_FN_AVB_MAGIC, GPIO_FN_MII_MAGIC, GPIO_FN_VI1_DATA5_VI1_B5,
+	GPIO_FN_AVB_PHY_INT, GPIO_FN_VI1_DATA6_VI1_B6, GPIO_FN_AVB_GTXREFCLK,
+	GPIO_FN_SD0_CLK, GPIO_FN_VI1_DATA0_VI1_B0_B, GPIO_FN_SD0_CMD,
+	GPIO_FN_SCIFB1_SCK_B, GPIO_FN_VI1_DATA1_VI1_B1_B,
+
+	/* IPSR9 */
+	GPIO_FN_SD0_DAT0, GPIO_FN_SCIFB1_RXD_B, GPIO_FN_VI1_DATA2_VI1_B2_B,
+	GPIO_FN_SD0_DAT1, GPIO_FN_SCIFB1_TXD_B, GPIO_FN_VI1_DATA3_VI1_B3_B,
+	GPIO_FN_SD0_DAT2, GPIO_FN_SCIFB1_CTS_N_B, GPIO_FN_VI1_DATA4_VI1_B4_B,
+	GPIO_FN_SD0_DAT3, GPIO_FN_SCIFB1_RTS_N_B, GPIO_FN_VI1_DATA5_VI1_B5_B,
+	GPIO_FN_SD0_CD, GPIO_FN_MMC0_D6, GPIO_FN_TS_SDEN0_B, GPIO_FN_USB0_EXTP,
+	GPIO_FN_GLO_SCLK, GPIO_FN_VI1_DATA6_VI1_B6_B, GPIO_FN_SCL1_B,
+	GPIO_FN_SCL1_CIS_B, GPIO_FN_VI2_DATA6_VI2_B6_B, GPIO_FN_SD0_WP,
+	GPIO_FN_MMC0_D7, GPIO_FN_TS_SPSYNC0_B, GPIO_FN_USB0_IDIN,
+	GPIO_FN_GLO_SDATA, GPIO_FN_VI1_DATA7_VI1_B7_B, GPIO_FN_SDA1_B,
+	GPIO_FN_SDA1_CIS_B, GPIO_FN_VI2_DATA7_VI2_B7_B, GPIO_FN_SD1_CLK,
+	GPIO_FN_AVB_TX_EN, GPIO_FN_MII_TX_EN, GPIO_FN_SD1_CMD,
+	GPIO_FN_AVB_TX_ER, GPIO_FN_MII_TX_ER, GPIO_FN_SCIFB0_SCK_B,
+	GPIO_FN_SD1_DAT0, GPIO_FN_AVB_TX_CLK, GPIO_FN_MII_TX_CLK,
+	GPIO_FN_SCIFB0_RXD_B, GPIO_FN_SD1_DAT1, GPIO_FN_AVB_LINK,
+	GPIO_FN_MII_LINK, GPIO_FN_SCIFB0_TXD_B, GPIO_FN_SD1_DAT2,
+	GPIO_FN_AVB_COL, GPIO_FN_MII_COL, GPIO_FN_SCIFB0_CTS_N_B,
+	GPIO_FN_SD1_DAT3, GPIO_FN_AVB_RXD0, GPIO_FN_MII_RXD0,
+	GPIO_FN_SCIFB0_RTS_N_B, GPIO_FN_SD1_CD, GPIO_FN_MMC1_D6,
+	GPIO_FN_TS_SDEN1, GPIO_FN_USB1_EXTP, GPIO_FN_GLO_SS, GPIO_FN_VI0_CLK_B,
+	GPIO_FN_SCL2_D, GPIO_FN_SCL2_CIS_D, GPIO_FN_SIM0_CLK_B,
+	GPIO_FN_VI3_CLK_B,
+
+	/* IPSR10 */
+	GPIO_FN_SD1_WP, GPIO_FN_MMC1_D7, GPIO_FN_TS_SPSYNC1, GPIO_FN_USB1_IDIN,
+	GPIO_FN_GLO_RFON, GPIO_FN_VI1_CLK_B, GPIO_FN_SDA2_D, GPIO_FN_SDA2_CIS_D,
+	GPIO_FN_SIM0_D_B, GPIO_FN_SD2_CLK, GPIO_FN_MMC0_CLK, GPIO_FN_SIM0_CLK,
+	GPIO_FN_VI0_DATA0_VI0_B0_B, GPIO_FN_TS_SDEN0_C, GPIO_FN_GLO_SCLK_B,
+	GPIO_FN_VI3_DATA0_B, GPIO_FN_SD2_CMD, GPIO_FN_MMC0_CMD, GPIO_FN_SIM0_D,
+	GPIO_FN_VI0_DATA1_VI0_B1_B, GPIO_FN_SCIFB1_SCK_E, GPIO_FN_SCK1_D,
+	GPIO_FN_TS_SPSYNC0_C, GPIO_FN_GLO_SDATA_B, GPIO_FN_VI3_DATA1_B,
+	GPIO_FN_SD2_DAT0, GPIO_FN_MMC0_D0, GPIO_FN_FMCLK_B,
+	GPIO_FN_VI0_DATA2_VI0_B2_B, GPIO_FN_SCIFB1_RXD_E, GPIO_FN_RX1_D,
+	GPIO_FN_TS_SDAT0_C, GPIO_FN_GLO_SS_B, GPIO_FN_VI3_DATA2_B,
+	GPIO_FN_SD2_DAT1, GPIO_FN_MMC0_D1, GPIO_FN_FMIN_B, GPIO_FN_RDS_DATA,
+	GPIO_FN_VI0_DATA3_VI0_B3_B, GPIO_FN_SCIFB1_TXD_E, GPIO_FN_TX1_D,
+	GPIO_FN_TS_SCK0_C, GPIO_FN_GLO_RFON_B, GPIO_FN_VI3_DATA3_B,
+	GPIO_FN_SD2_DAT2, GPIO_FN_MMC0_D2, GPIO_FN_BPFCLK_B, GPIO_FN_RDS_CLK,
+	GPIO_FN_VI0_DATA4_VI0_B4_B, GPIO_FN_HRX0_D, GPIO_FN_TS_SDEN1_B,
+	GPIO_FN_GLO_Q0_B, GPIO_FN_VI3_DATA4_B, GPIO_FN_SD2_DAT3,
+	GPIO_FN_MMC0_D3, GPIO_FN_SIM0_RST, GPIO_FN_VI0_DATA5_VI0_B5_B,
+	GPIO_FN_HTX0_D, GPIO_FN_TS_SPSYNC1_B, GPIO_FN_GLO_Q1_B,
+	GPIO_FN_VI3_DATA5_B, GPIO_FN_SD2_CD, GPIO_FN_MMC0_D4,
+	GPIO_FN_TS_SDAT0_B, GPIO_FN_USB2_EXTP, GPIO_FN_GLO_I0,
+	GPIO_FN_VI0_DATA6_VI0_B6_B, GPIO_FN_HCTS0_N_D, GPIO_FN_TS_SDAT1_B,
+	GPIO_FN_GLO_I0_B, GPIO_FN_VI3_DATA6_B,
+
+	/* IPSR11 */
+	GPIO_FN_SD2_WP, GPIO_FN_MMC0_D5, GPIO_FN_TS_SCK0_B, GPIO_FN_USB2_IDIN,
+	GPIO_FN_GLO_I1, GPIO_FN_VI0_DATA7_VI0_B7_B, GPIO_FN_HRTS0_N_D,
+	GPIO_FN_TS_SCK1_B, GPIO_FN_GLO_I1_B, GPIO_FN_VI3_DATA7_B,
+	GPIO_FN_SD3_CLK, GPIO_FN_MMC1_CLK, GPIO_FN_SD3_CMD, GPIO_FN_MMC1_CMD,
+	GPIO_FN_MTS_N, GPIO_FN_SD3_DAT0, GPIO_FN_MMC1_D0, GPIO_FN_STM_N,
+	GPIO_FN_SD3_DAT1, GPIO_FN_MMC1_D1, GPIO_FN_MDATA, GPIO_FN_SD3_DAT2,
+	GPIO_FN_MMC1_D2, GPIO_FN_SDATA, GPIO_FN_SD3_DAT3, GPIO_FN_MMC1_D3,
+	GPIO_FN_SCKZ, GPIO_FN_SD3_CD, GPIO_FN_MMC1_D4, GPIO_FN_TS_SDAT1,
+	GPIO_FN_VSP, GPIO_FN_GLO_Q0, GPIO_FN_SIM0_RST_B, GPIO_FN_SD3_WP,
+	GPIO_FN_MMC1_D5, GPIO_FN_TS_SCK1, GPIO_FN_GLO_Q1, GPIO_FN_FMIN_C,
+	GPIO_FN_RDS_DATA_B, GPIO_FN_FMIN_E, GPIO_FN_RDS_DATA_D, GPIO_FN_FMIN_F,
+	GPIO_FN_RDS_DATA_E, GPIO_FN_MLB_CLK, GPIO_FN_SCL2_B, GPIO_FN_SCL2_CIS_B,
+	GPIO_FN_MLB_SIG, GPIO_FN_SCIFB1_RXD_D, GPIO_FN_RX1_C, GPIO_FN_SDA2_B,
+	GPIO_FN_SDA2_CIS_B, GPIO_FN_MLB_DAT, GPIO_FN_SPV_EVEN,
+	GPIO_FN_SCIFB1_TXD_D, GPIO_FN_TX1_C, GPIO_FN_BPFCLK_C,
+	GPIO_FN_RDS_CLK_B, GPIO_FN_SSI_SCK0129, GPIO_FN_CAN_CLK_B,
+	GPIO_FN_MOUT0,
+
+	/* IPSR12 */
+	GPIO_FN_SSI_WS0129, GPIO_FN_CAN0_TX_B, GPIO_FN_MOUT1,
+	GPIO_FN_SSI_SDATA0, GPIO_FN_CAN0_RX_B, GPIO_FN_MOUT2,
+	GPIO_FN_SSI_SDATA1, GPIO_FN_CAN1_TX_B, GPIO_FN_MOUT5,
+	GPIO_FN_SSI_SDATA2, GPIO_FN_CAN1_RX_B, GPIO_FN_SSI_SCK1, GPIO_FN_MOUT6,
+	GPIO_FN_SSI_SCK34, GPIO_FN_STP_OPWM_0, GPIO_FN_SCIFB0_SCK,
+	GPIO_FN_MSIOF1_SCK, GPIO_FN_CAN_DEBUG_HW_TRIGGER, GPIO_FN_SSI_WS34,
+	GPIO_FN_STP_IVCXO27_0, GPIO_FN_SCIFB0_RXD, GPIO_FN_MSIOF1_SYNC,
+	GPIO_FN_CAN_STEP0, GPIO_FN_SSI_SDATA3, GPIO_FN_STP_ISCLK_0,
+	GPIO_FN_SCIFB0_TXD, GPIO_FN_MSIOF1_SS1, GPIO_FN_CAN_TXCLK,
+	GPIO_FN_SSI_SCK4, GPIO_FN_STP_ISD_0, GPIO_FN_SCIFB0_CTS_N,
+	GPIO_FN_MSIOF1_SS2, GPIO_FN_SSI_SCK5_C, GPIO_FN_CAN_DEBUGOUT0,
+	GPIO_FN_SSI_WS4, GPIO_FN_STP_ISEN_0, GPIO_FN_SCIFB0_RTS_N,
+	GPIO_FN_MSIOF1_TXD, GPIO_FN_SSI_WS5_C, GPIO_FN_CAN_DEBUGOUT1,
+	GPIO_FN_SSI_SDATA4, GPIO_FN_STP_ISSYNC_0, GPIO_FN_MSIOF1_RXD,
+	GPIO_FN_CAN_DEBUGOUT2, GPIO_FN_SSI_SCK5, GPIO_FN_SCIFB1_SCK,
+	GPIO_FN_IERX_B, GPIO_FN_DU2_EXHSYNC_DU2_HSYNC, GPIO_FN_QSTH_QHS,
+	GPIO_FN_CAN_DEBUGOUT3, GPIO_FN_SSI_WS5, GPIO_FN_SCIFB1_RXD,
+	GPIO_FN_IECLK_B, GPIO_FN_DU2_EXVSYNC_DU2_VSYNC, GPIO_FN_QSTB_QHE,
+	GPIO_FN_CAN_DEBUGOUT4,
+
+	/* IPSR13 */
+	GPIO_FN_SSI_SDATA5, GPIO_FN_SCIFB1_TXD, GPIO_FN_IETX_B, GPIO_FN_DU2_DR2,
+	GPIO_FN_LCDOUT2, GPIO_FN_CAN_DEBUGOUT5, GPIO_FN_SSI_SCK6,
+	GPIO_FN_SCIFB1_CTS_N, GPIO_FN_BPFCLK_D, GPIO_FN_RDS_CLK_C,
+	GPIO_FN_DU2_DR3, GPIO_FN_LCDOUT3, GPIO_FN_CAN_DEBUGOUT6,
+	GPIO_FN_BPFCLK_F, GPIO_FN_RDS_CLK_E, GPIO_FN_SSI_WS6,
+	GPIO_FN_SCIFB1_RTS_N, GPIO_FN_CAN0_TX_D, GPIO_FN_DU2_DR4,
+	GPIO_FN_LCDOUT4, GPIO_FN_CAN_DEBUGOUT7, GPIO_FN_SSI_SDATA6,
+	GPIO_FN_FMIN_D, GPIO_FN_RDS_DATA_C, GPIO_FN_DU2_DR5, GPIO_FN_LCDOUT5,
+	GPIO_FN_CAN_DEBUGOUT8, GPIO_FN_SSI_SCK78, GPIO_FN_STP_IVCXO27_1,
+	GPIO_FN_SCK1, GPIO_FN_SCIFA1_SCK, GPIO_FN_DU2_DR6, GPIO_FN_LCDOUT6,
+	GPIO_FN_CAN_DEBUGOUT9, GPIO_FN_SSI_WS78, GPIO_FN_STP_ISCLK_1,
+	GPIO_FN_SCIFB2_SCK, GPIO_FN_SCIFA2_CTS_N, GPIO_FN_DU2_DR7,
+	GPIO_FN_LCDOUT7, GPIO_FN_CAN_DEBUGOUT10, GPIO_FN_SSI_SDATA7,
+	GPIO_FN_STP_ISD_1, GPIO_FN_SCIFB2_RXD, GPIO_FN_SCIFA2_RTS_N,
+	GPIO_FN_TCLK2, GPIO_FN_QSTVA_QVS, GPIO_FN_CAN_DEBUGOUT11,
+	GPIO_FN_BPFCLK_E, GPIO_FN_RDS_CLK_D, GPIO_FN_SSI_SDATA7_B,
+	GPIO_FN_FMIN_G, GPIO_FN_RDS_DATA_F, GPIO_FN_SSI_SDATA8,
+	GPIO_FN_STP_ISEN_1, GPIO_FN_SCIFB2_TXD, GPIO_FN_CAN0_TX_C,
+	GPIO_FN_CAN_DEBUGOUT12, GPIO_FN_SSI_SDATA8_B, GPIO_FN_SSI_SDATA9,
+	GPIO_FN_STP_ISSYNC_1, GPIO_FN_SCIFB2_CTS_N, GPIO_FN_SSI_WS1,
+	GPIO_FN_SSI_SDATA5_C, GPIO_FN_CAN_DEBUGOUT13, GPIO_FN_AUDIO_CLKA,
+	GPIO_FN_SCIFB2_RTS_N, GPIO_FN_CAN_DEBUGOUT14,
+
+	/* IPSR14 */
+	GPIO_FN_AUDIO_CLKB, GPIO_FN_SCIF_CLK, GPIO_FN_CAN0_RX_D,
+	GPIO_FN_DVC_MUTE, GPIO_FN_CAN0_RX_C, GPIO_FN_CAN_DEBUGOUT15,
+	GPIO_FN_REMOCON, GPIO_FN_SCIFA0_SCK, GPIO_FN_HSCK1, GPIO_FN_SCK0,
+	GPIO_FN_MSIOF3_SS2, GPIO_FN_DU2_DG2, GPIO_FN_LCDOUT10, GPIO_FN_SDA1_C,
+	GPIO_FN_SDA1_CIS_C, GPIO_FN_SCIFA0_RXD, GPIO_FN_HRX1, GPIO_FN_RX0,
+	GPIO_FN_DU2_DR0, GPIO_FN_LCDOUT0, GPIO_FN_SCIFA0_TXD, GPIO_FN_HTX1,
+	GPIO_FN_TX0, GPIO_FN_DU2_DR1, GPIO_FN_LCDOUT1, GPIO_FN_SCIFA0_CTS_N,
+	GPIO_FN_HCTS1_N, GPIO_FN_CTS0_N, GPIO_FN_MSIOF3_SYNC, GPIO_FN_DU2_DG3,
+	GPIO_FN_LCDOUT11, GPIO_FN_PWM0_B, GPIO_FN_SCL1_C, GPIO_FN_SCL1_CIS_C,
+	GPIO_FN_SCIFA0_RTS_N, GPIO_FN_HRTS1_N, GPIO_FN_RTS0_N_TANS,
+	GPIO_FN_MSIOF3_SS1, GPIO_FN_DU2_DG0, GPIO_FN_LCDOUT8, GPIO_FN_PWM1_B,
+	GPIO_FN_SCIFA1_RXD, GPIO_FN_AD_DI, GPIO_FN_RX1,
+	GPIO_FN_DU2_EXODDF_DU2_ODDF_DISP_CDE, GPIO_FN_QCPV_QDE,
+	GPIO_FN_SCIFA1_TXD, GPIO_FN_AD_DO, GPIO_FN_TX1, GPIO_FN_DU2_DG1,
+	GPIO_FN_LCDOUT9, GPIO_FN_SCIFA1_CTS_N, GPIO_FN_AD_CLK,
+	GPIO_FN_CTS1_N, GPIO_FN_MSIOF3_RXD, GPIO_FN_DU0_DOTCLKOUT, GPIO_FN_QCLK,
+	GPIO_FN_SCIFA1_RTS_N, GPIO_FN_AD_NCS_N, GPIO_FN_RTS1_N_TANS,
+	GPIO_FN_MSIOF3_TXD, GPIO_FN_DU1_DOTCLKOUT, GPIO_FN_QSTVB_QVE,
+	GPIO_FN_HRTS0_N_C,
+
+	/* IPSR15 */
+	GPIO_FN_SCIFA2_SCK, GPIO_FN_FMCLK, GPIO_FN_MSIOF3_SCK, GPIO_FN_DU2_DG7,
+	GPIO_FN_LCDOUT15, GPIO_FN_SCIF_CLK_B, GPIO_FN_SCIFA2_RXD, GPIO_FN_FMIN,
+	GPIO_FN_DU2_DB0, GPIO_FN_LCDOUT16, GPIO_FN_SCL2, GPIO_FN_SCL2_CIS,
+	GPIO_FN_SCIFA2_TXD, GPIO_FN_BPFCLK, GPIO_FN_DU2_DB1, GPIO_FN_LCDOUT17,
+	GPIO_FN_SDA2, GPIO_FN_SDA2_CIS, GPIO_FN_HSCK0, GPIO_FN_TS_SDEN0,
+	GPIO_FN_DU2_DG4, GPIO_FN_LCDOUT12, GPIO_FN_HCTS0_N_C, GPIO_FN_HRX0,
+	GPIO_FN_DU2_DB2, GPIO_FN_LCDOUT18, GPIO_FN_HTX0, GPIO_FN_DU2_DB3,
+	GPIO_FN_LCDOUT19, GPIO_FN_HCTS0_N, GPIO_FN_SSI_SCK9, GPIO_FN_DU2_DB4,
+	GPIO_FN_LCDOUT20, GPIO_FN_HRTS0_N, GPIO_FN_SSI_WS9, GPIO_FN_DU2_DB5,
+	GPIO_FN_LCDOUT21, GPIO_FN_MSIOF0_SCK, GPIO_FN_TS_SDAT0, GPIO_FN_ADICLK,
+	GPIO_FN_DU2_DB6, GPIO_FN_LCDOUT22, GPIO_FN_MSIOF0_SYNC, GPIO_FN_TS_SCK0,
+	GPIO_FN_SSI_SCK2, GPIO_FN_ADIDATA, GPIO_FN_DU2_DB7, GPIO_FN_LCDOUT23,
+	GPIO_FN_SCIFA2_RXD_B, GPIO_FN_MSIOF0_SS1, GPIO_FN_ADICHS0,
+	GPIO_FN_DU2_DG5, GPIO_FN_LCDOUT13, GPIO_FN_MSIOF0_TXD, GPIO_FN_ADICHS1,
+	GPIO_FN_DU2_DG6, GPIO_FN_LCDOUT14,
+
+	/* IPSR16 */
+	GPIO_FN_MSIOF0_SS2, GPIO_FN_AUDIO_CLKOUT, GPIO_FN_ADICHS2,
+	GPIO_FN_DU2_DISP, GPIO_FN_QPOLA, GPIO_FN_HTX0_C, GPIO_FN_SCIFA2_TXD_B,
+	GPIO_FN_MSIOF0_RXD, GPIO_FN_TS_SPSYNC0, GPIO_FN_SSI_WS2,
+	GPIO_FN_ADICS_SAMP, GPIO_FN_DU2_CDE, GPIO_FN_QPOLB, GPIO_FN_HRX0_C,
+	GPIO_FN_USB1_PWEN, GPIO_FN_AUDIO_CLKOUT_D, GPIO_FN_USB1_OVC,
+	GPIO_FN_TCLK1_B,
+};
+
+#endif /* __ASM_R8A7790_H__ */
diff --git a/arch/arm/include/asm/arch-rmobile/r8a7790.h b/arch/arm/include/asm/arch-rmobile/r8a7790.h
new file mode 100644
index 0000000000..d9ea71fa14
--- /dev/null
+++ b/arch/arm/include/asm/arch-rmobile/r8a7790.h
@@ -0,0 +1,615 @@
+/*
+ * arch/arm/include/asm/arch-rmobile/r8a7790.h
+ *
+ * Copyright (C) 2013 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#ifndef __ASM_ARCH_R8A7790_H
+#define __ASM_ARCH_R8A7790_H
+
+/*
+ * R8A7790 I/O Addresses
+ */
+#define	RWDT_BASE		0xE6020000
+#define	SWDT_BASE		0xE6030000
+#define	LBSC_BASE		0xFEC00200
+#define DBSC3_0_BASE		0xE6790000
+#define DBSC3_1_BASE		0xE67A0000
+#define TMU_BASE		0xE61E0000
+#define	GPIO5_BASE		0xE6055000
+#define SH_QSPI_BASE	0xE6B10000
+
+#define S3C_BASE		0xE6784000
+#define S3C_INT_BASE		0xE6784A00
+#define S3C_MEDIA_BASE		0xE6784B00
+
+#define S3C_QOS_DCACHE_BASE	0xE6784BDC
+#define S3C_QOS_CCI0_BASE	0xE6784C00
+#define S3C_QOS_CCI1_BASE	0xE6784C24
+#define S3C_QOS_MXI_BASE	0xE6784C48
+#define S3C_QOS_AXI_BASE	0xE6784C6C
+
+#define DBSC3_0_QOS_R0_BASE	0xE6791000
+#define DBSC3_0_QOS_R1_BASE	0xE6791100
+#define DBSC3_0_QOS_R2_BASE	0xE6791200
+#define DBSC3_0_QOS_R3_BASE	0xE6791300
+#define DBSC3_0_QOS_R4_BASE	0xE6791400
+#define DBSC3_0_QOS_R5_BASE	0xE6791500
+#define DBSC3_0_QOS_R6_BASE	0xE6791600
+#define DBSC3_0_QOS_R7_BASE	0xE6791700
+#define DBSC3_0_QOS_R8_BASE	0xE6791800
+#define DBSC3_0_QOS_R9_BASE	0xE6791900
+#define DBSC3_0_QOS_R10_BASE	0xE6791A00
+#define DBSC3_0_QOS_R11_BASE	0xE6791B00
+#define DBSC3_0_QOS_R12_BASE	0xE6791C00
+#define DBSC3_0_QOS_R13_BASE	0xE6791D00
+#define DBSC3_0_QOS_R14_BASE	0xE6791E00
+#define DBSC3_0_QOS_R15_BASE	0xE6791F00
+#define DBSC3_0_QOS_W0_BASE	0xE6792000
+#define DBSC3_0_QOS_W1_BASE	0xE6792100
+#define DBSC3_0_QOS_W2_BASE	0xE6792200
+#define DBSC3_0_QOS_W3_BASE	0xE6792300
+#define DBSC3_0_QOS_W4_BASE	0xE6792400
+#define DBSC3_0_QOS_W5_BASE	0xE6792500
+#define DBSC3_0_QOS_W6_BASE	0xE6792600
+#define DBSC3_0_QOS_W7_BASE	0xE6792700
+#define DBSC3_0_QOS_W8_BASE	0xE6792800
+#define DBSC3_0_QOS_W9_BASE	0xE6792900
+#define DBSC3_0_QOS_W10_BASE	0xE6792A00
+#define DBSC3_0_QOS_W11_BASE	0xE6792B00
+#define DBSC3_0_QOS_W12_BASE	0xE6792C00
+#define DBSC3_0_QOS_W13_BASE	0xE6792D00
+#define DBSC3_0_QOS_W14_BASE	0xE6792E00
+#define DBSC3_0_QOS_W15_BASE	0xE6792F00
+
+#define DBSC3_0_DBADJ2		0xE67900C8
+
+#define CCI_400_MAXOT_1		0xF0091110
+#define CCI_400_MAXOT_2		0xF0092110
+#define CCI_400_QOSCNTL_1	0xF009110C
+#define CCI_400_QOSCNTL_2	0xF009210C
+
+#define	MXI_BASE		0xFE960000
+#define	MXI_QOS_BASE		0xFE960300
+
+#define SYS_AXI_SYX64TO128_BASE	0xFF800300
+#define SYS_AXI_AVB_BASE	0xFF800340
+#define SYS_AXI_G2D_BASE	0xFF800540
+#define SYS_AXI_IMP0_BASE	0xFF800580
+#define SYS_AXI_IMP1_BASE	0xFF8005C0
+#define SYS_AXI_IMUX0_BASE	0xFF800600
+#define SYS_AXI_IMUX1_BASE	0xFF800640
+#define SYS_AXI_IMUX2_BASE	0xFF800680
+#define SYS_AXI_LBS_BASE	0xFF8006C0
+#define SYS_AXI_MMUDS_BASE	0xFF800700
+#define SYS_AXI_MMUM_BASE	0xFF800740
+#define SYS_AXI_MMUR_BASE	0xFF800780
+#define SYS_AXI_MMUS0_BASE	0xFF8007C0
+#define SYS_AXI_MMUS1_BASE	0xFF800800
+#define SYS_AXI_MTSB0_BASE	0xFF800880
+#define SYS_AXI_MTSB1_BASE	0xFF8008C0
+#define SYS_AXI_PCI_BASE	0xFF800900
+#define SYS_AXI_RTX_BASE	0xFF800940
+#define SYS_AXI_SDS0_BASE	0xFF800A80
+#define SYS_AXI_SDS1_BASE	0xFF800AC0
+#define SYS_AXI_USB20_BASE	0xFF800C00
+#define SYS_AXI_USB21_BASE	0xFF800C40
+#define SYS_AXI_USB22_BASE	0xFF800C80
+#define SYS_AXI_USB30_BASE	0xFF800CC0
+
+#define RT_AXI_SHX_BASE		0xFF810100
+#define RT_AXI_RDS_BASE		0xFF8101C0
+#define RT_AXI_RTX64TO128_BASE	0xFF810200
+#define RT_AXI_STPRO_BASE	0xFF810240
+
+#define MP_AXI_ADSP_BASE	0xFF820100
+#define MP_AXI_ASDS0_BASE	0xFF8201C0
+#define MP_AXI_ASDS1_BASE	0xFF820200
+#define MP_AXI_MLP_BASE		0xFF820240
+#define MP_AXI_MMUMP_BASE	0xFF820280
+#define MP_AXI_SPU_BASE		0xFF8202C0
+#define MP_AXI_SPUC_BASE	0xFF820300
+
+#define SYS_AXI256_AXI128TO256_BASE	0xFF860100
+#define SYS_AXI256_SYX_BASE	0xFF860140
+#define SYS_AXI256_MPX_BASE	0xFF860180
+#define SYS_AXI256_MXI_BASE	0xFF8601C0
+
+#define CCI_AXI_MMUS0_BASE	0xFF880100
+#define CCI_AXI_SYX2_BASE	0xFF880140
+#define CCI_AXI_MMUR_BASE	0xFF880180
+#define CCI_AXI_MMUDS_BASE	0xFF8801C0
+#define CCI_AXI_MMUM_BASE	0xFF880200
+#define CCI_AXI_MXI_BASE	0xFF880240
+#define CCI_AXI_MMUS1_BASE	0xFF880280
+#define CCI_AXI_MMUMP_BASE	0xFF8802C0
+
+#define MEDIA_AXI_JPR_BASE	0xFE964100
+#define MEDIA_AXI_JPW_BASE	0xFE966100
+#define MEDIA_AXI_GCU0R_BASE	0xFE964140
+#define MEDIA_AXI_GCU0W_BASE	0xFE966140
+#define MEDIA_AXI_GCU1R_BASE	0xFE964180
+#define MEDIA_AXI_GCU1W_BASE	0xFE966180
+#define MEDIA_AXI_TDMR_BASE	0xFE964500
+#define MEDIA_AXI_TDMW_BASE	0xFE966500
+#define MEDIA_AXI_VSP0CR_BASE	0xFE964540
+#define MEDIA_AXI_VSP0CW_BASE	0xFE966540
+#define MEDIA_AXI_VSP1CR_BASE	0xFE964580
+#define MEDIA_AXI_VSP1CW_BASE	0xFE966580
+#define MEDIA_AXI_VSPDU0CR_BASE	0xFE9645C0
+#define MEDIA_AXI_VSPDU0CW_BASE	0xFE9665C0
+#define MEDIA_AXI_VSPDU1CR_BASE	0xFE964600
+#define MEDIA_AXI_VSPDU1CW_BASE	0xFE966600
+#define MEDIA_AXI_VIN0W_BASE	0xFE966900
+#define MEDIA_AXI_VSP0R_BASE	0xFE964D00
+#define MEDIA_AXI_VSP0W_BASE	0xFE966D00
+#define MEDIA_AXI_FDP0R_BASE	0xFE964D40
+#define MEDIA_AXI_FDP0W_BASE	0xFE966D40
+#define MEDIA_AXI_IMSR_BASE	0xFE964D80
+#define MEDIA_AXI_IMSW_BASE	0xFE966D80
+#define MEDIA_AXI_VSP1R_BASE	0xFE965100
+#define MEDIA_AXI_VSP1W_BASE	0xFE967100
+#define MEDIA_AXI_FDP1R_BASE	0xFE965140
+#define MEDIA_AXI_FDP1W_BASE	0xFE967140
+#define MEDIA_AXI_IMRR_BASE	0xFE965180
+#define MEDIA_AXI_IMRW_BASE	0xFE967180
+#define MEDIA_AXI_FDP2R_BASE	0xFE9651C0
+#define MEDIA_AXI_FDP2W_BASE	0xFE966DC0
+#define MEDIA_AXI_VSPD0R_BASE	0xFE965500
+#define MEDIA_AXI_VSPD0W_BASE	0xFE967500
+#define MEDIA_AXI_VSPD1R_BASE	0xFE965540
+#define MEDIA_AXI_VSPD1W_BASE	0xFE967540
+#define MEDIA_AXI_DU0R_BASE	0xFE965580
+#define MEDIA_AXI_DU0W_BASE	0xFE967580
+#define MEDIA_AXI_DU1R_BASE	0xFE9655C0
+#define MEDIA_AXI_DU1W_BASE	0xFE9675C0
+#define MEDIA_AXI_VCP0CR_BASE	0xFE965900
+#define MEDIA_AXI_VCP0CW_BASE	0xFE967900
+#define MEDIA_AXI_VCP0VR_BASE	0xFE965940
+#define MEDIA_AXI_VCP0VW_BASE	0xFE967940
+#define MEDIA_AXI_VPC0R_BASE	0xFE965980
+#define MEDIA_AXI_VCP1CR_BASE	0xFE965D00
+#define MEDIA_AXI_VCP1CW_BASE	0xFE967D00
+#define MEDIA_AXI_VCP1VR_BASE	0xFE965D40
+#define MEDIA_AXI_VCP1VW_BASE	0xFE967D40
+#define MEDIA_AXI_VPC1R_BASE	0xFE965D80
+
+#define SYS_AXI_AVBDMSCR	0xFF802000
+#define SYS_AXI_SYX2DMSCR	0xFF802004
+#define SYS_AXI_CC50DMSCR	0xFF802008
+#define SYS_AXI_CC51DMSCR	0xFF80200C
+#define SYS_AXI_CCIDMSCR	0xFF802010
+#define SYS_AXI_CSDMSCR		0xFF802014
+#define SYS_AXI_DDMDMSCR	0xFF802018
+#define SYS_AXI_ETHDMSCR	0xFF80201C
+#define SYS_AXI_G2DDMSCR	0xFF802020
+#define SYS_AXI_IMP0DMSCR	0xFF802024
+#define SYS_AXI_IMP1DMSCR	0xFF802028
+#define SYS_AXI_LBSDMSCR	0xFF80202C
+#define SYS_AXI_MMUDSDMSCR	0xFF802030
+#define SYS_AXI_MMUMXDMSCR	0xFF802034
+#define SYS_AXI_MMURDDMSCR	0xFF802038
+#define SYS_AXI_MMUS0DMSCR	0xFF80203C
+#define SYS_AXI_MMUS1DMSCR	0xFF802040
+#define SYS_AXI_MPXDMSCR	0xFF802044
+#define SYS_AXI_MTSB0DMSCR	0xFF802048
+#define SYS_AXI_MTSB1DMSCR	0xFF80204C
+#define SYS_AXI_PCIDMSCR	0xFF802050
+#define SYS_AXI_RTXDMSCR	0xFF802054
+#define SYS_AXI_SAT0DMSCR	0xFF802058
+#define SYS_AXI_SAT1DMSCR	0xFF80205C
+#define SYS_AXI_SDM0DMSCR	0xFF802060
+#define SYS_AXI_SDM1DMSCR	0xFF802064
+#define SYS_AXI_SDS0DMSCR	0xFF802068
+#define SYS_AXI_SDS1DMSCR	0xFF80206C
+#define SYS_AXI_ETRABDMSCR	0xFF802070
+#define SYS_AXI_ETRKFDMSCR	0xFF802074
+#define SYS_AXI_UDM0DMSCR	0xFF802078
+#define SYS_AXI_UDM1DMSCR	0xFF80207C
+#define SYS_AXI_USB20DMSCR	0xFF802080
+#define SYS_AXI_USB21DMSCR	0xFF802084
+#define SYS_AXI_USB22DMSCR	0xFF802088
+#define SYS_AXI_USB30DMSCR	0xFF80208C
+#define SYS_AXI_X128TO64SLVDMSCR	0xFF802100
+#define SYS_AXI_X64TO128SLVDMSCR	0xFF802104
+#define SYS_AXI_AVBSLVDMSCR	0xFF802108
+#define SYS_AXI_SYX2SLVDMSCR	0xFF80210C
+#define SYS_AXI_ETHSLVDMSCR	0xFF802110
+#define SYS_AXI_GICSLVDMSCR	0xFF802114
+#define SYS_AXI_IMPSLVDMSCR	0xFF802118
+#define SYS_AXI_IMX0SLVDMSCR	0xFF80211C
+#define SYS_AXI_IMX1SLVDMSCR	0xFF802120
+#define SYS_AXI_IMX2SLVDMSCR	0xFF802124
+#define SYS_AXI_LBSSLVDMSCR	0xFF802128
+#define SYS_AXI_MMC0SLVDMSCR	0xFF80212C
+#define SYS_AXI_MMC1SLVDMSCR	0xFF802130
+#define SYS_AXI_MPXSLVDMSCR	0xFF802134
+#define SYS_AXI_MTSB0SLVDMSCR	0xFF802138
+#define SYS_AXI_MTSB1SLVDMSCR	0xFF80213C
+#define SYS_AXI_MXTSLVDMSCR	0xFF802140
+#define SYS_AXI_PCISLVDMSCR	0xFF802144
+#define SYS_AXI_SYAPBSLVDMSCR	0xFF802148
+#define SYS_AXI_QSAPBSLVDMSCR	0xFF80214C
+#define SYS_AXI_RTXSLVDMSCR	0xFF802150
+#define SYS_AXI_SAT0SLVDMSCR	0xFF802168
+#define SYS_AXI_SAT1SLVDMSCR	0xFF80216C
+#define SYS_AXI_SDAP0SLVDMSCR	0xFF802170
+#define SYS_AXI_SDAP1SLVDMSCR	0xFF802174
+#define SYS_AXI_SDAP2SLVDMSCR	0xFF802178
+#define SYS_AXI_SDAP3SLVDMSCR	0xFF80217C
+#define SYS_AXI_SGXSLVDMSCR	0xFF802180
+#define SYS_AXI_STBSLVDMSCR	0xFF802188
+#define SYS_AXI_STMSLVDMSCR	0xFF80218C
+#define SYS_AXI_TSPL0SLVDMSCR	0xFF802194
+#define SYS_AXI_TSPL1SLVDMSCR	0xFF802198
+#define SYS_AXI_TSPL2SLVDMSCR	0xFF80219C
+#define SYS_AXI_USB20SLVDMSCR	0xFF8021A0
+#define SYS_AXI_USB21SLVDMSCR	0xFF8021A4
+#define SYS_AXI_USB22SLVDMSCR	0xFF8021A8
+#define SYS_AXI_USB30SLVDMSCR	0xFF8021AC
+
+#define RT_AXI_CBMDMSCR		0xFF812000
+#define RT_AXI_DBDMSCR		0xFF812004
+#define RT_AXI_RDMDMSCR		0xFF812008
+#define RT_AXI_RDSDMSCR		0xFF81200C
+#define RT_AXI_STRDMSCR		0xFF812010
+#define RT_AXI_SY2RTDMSCR	0xFF812014
+#define RT_AXI_CBSSLVDMSCR	0xFF812100
+#define RT_AXI_DBSSLVDMSCR	0xFF812104
+#define RT_AXI_RTAP1SLVDMSCR	0xFF812108
+#define RT_AXI_RTAP2SLVDMSCR	0xFF81210C
+#define RT_AXI_RTAP3SLVDMSCR	0xFF812110
+#define RT_AXI_RT2SYSLVDMSCR	0xFF812114
+#define RT_AXI_A128TO64SLVDMSCR	0xFF812118
+#define RT_AXI_A64TO128SLVDMSCR	0xFF81211C
+#define RT_AXI_A64TO128CSLVDMSCR	0xFF812120
+#define RT_AXI_UTLBRSLVDMSCR	0xFF812128
+
+#define MP_AXI_ADSPDMSCR	0xFF822000
+#define MP_AXI_ASDM0DMSCR	0xFF822004
+#define MP_AXI_ASDM1DMSCR	0xFF822008
+#define MP_AXI_ASDS0DMSCR	0xFF82200C
+#define MP_AXI_ASDS1DMSCR	0xFF822010
+#define MP_AXI_MLPDMSCR		0xFF822014
+#define MP_AXI_MMUMPDMSCR	0xFF822018
+#define MP_AXI_SPUDMSCR		0xFF82201C
+#define MP_AXI_SPUCDMSCR	0xFF822020
+#define MP_AXI_SY2MPDMSCR	0xFF822024
+#define MP_AXI_ADSPSLVDMSCR	0xFF822100
+#define MP_AXI_MLMSLVDMSCR	0xFF822104
+#define MP_AXI_MPAP4SLVDMSCR	0xFF822108
+#define MP_AXI_MPAP5SLVDMSCR	0xFF82210C
+#define MP_AXI_MPAP6SLVDMSCR	0xFF822110
+#define MP_AXI_MPAP7SLVDMSCR	0xFF822114
+#define MP_AXI_MP2SYSLVDMSCR	0xFF822118
+#define MP_AXI_MP2SY2SLVDMSCR	0xFF82211C
+#define MP_AXI_MPXAPSLVDMSCR	0xFF822124
+#define MP_AXI_SPUSLVDMSCR	0xFF822128
+#define MP_AXI_UTLBMPSLVDMSCR	0xFF82212C
+
+#define ADM_AXI_ASDM0DMSCR	0xFF842000
+#define ADM_AXI_ASDM1DMSCR	0xFF842004
+#define ADM_AXI_MPAP1SLVDMSCR	0xFF842104
+#define ADM_AXI_MPAP2SLVDMSCR	0xFF842108
+#define ADM_AXI_MPAP3SLVDMSCR	0xFF84210C
+
+#define DM_AXI_RDMDMSCR		0xFF852000
+#define DM_AXI_SDM0DMSCR	0xFF852004
+#define DM_AXI_SDM1DMSCR	0xFF852008
+#define DM_AXI_MMAP0SLVDMSCR	0xFF852100
+#define DM_AXI_MMAP1SLVDMSCR	0xFF852104
+#define DM_AXI_QSPAPSLVDMSCR	0xFF852108
+#define DM_AXI_RAP4SLVDMSCR	0xFF85210C
+#define DM_AXI_RAP5SLVDMSCR	0xFF852110
+#define DM_AXI_SAP4SLVDMSCR	0xFF852114
+#define DM_AXI_SAP5SLVDMSCR	0xFF852118
+#define DM_AXI_SAP6SLVDMSCR	0xFF85211C
+#define DM_AXI_SAP65SLVDMSCR	0xFF852120
+#define DM_AXI_SDAP0SLVDMSCR	0xFF852124
+#define DM_AXI_SDAP1SLVDMSCR	0xFF852128
+#define DM_AXI_SDAP2SLVDMSCR	0xFF85212C
+#define DM_AXI_SDAP3SLVDMSCR	0xFF852130
+
+#define SYS_AXI256_SYXDMSCR	0xFF862000
+#define SYS_AXI256_MPXDMSCR	0xFF862004
+#define SYS_AXI256_MXIDMSCR	0xFF862008
+#define SYS_AXI256_X128TO256SLVDMSCR	0xFF862100
+#define SYS_AXI256_X256TO128SLVDMSCR	0xFF862104
+#define SYS_AXI256_SYXSLVDMSCR	0xFF862108
+#define SYS_AXI256_CCXSLVDMSCR	0xFF86210C
+#define SYS_AXI256_S3CSLVDMSCR	0xFF862110
+
+#define MXT_SYXDMSCR		0xFF872000
+#define MXT_CMM0SLVDMSCR	0xFF872100
+#define MXT_CMM1SLVDMSCR	0xFF872104
+#define MXT_CMM2SLVDMSCR	0xFF872108
+#define MXT_FDPSLVDMSCR		0xFF87210C
+#define MXT_IMRSLVDMSCR		0xFF872110
+#define MXT_VINSLVDMSCR		0xFF872114
+#define MXT_VPC0SLVDMSCR	0xFF872118
+#define MXT_VPC1SLVDMSCR	0xFF87211C
+#define MXT_VSP0SLVDMSCR	0xFF872120
+#define MXT_VSP1SLVDMSCR	0xFF872124
+#define MXT_VSPD0SLVDMSCR	0xFF872128
+#define MXT_VSPD1SLVDMSCR	0xFF87212C
+#define MXT_MAP1SLVDMSCR	0xFF872130
+#define MXT_MAP2SLVDMSCR	0xFF872134
+
+#define CCI_AXI_MMUS0DMSCR	0xFF882000
+#define CCI_AXI_SYX2DMSCR	0xFF882004
+#define CCI_AXI_MMURDMSCR	0xFF882008
+#define CCI_AXI_MMUDSDMSCR	0xFF88200C
+#define CCI_AXI_MMUMDMSCR	0xFF882010
+#define CCI_AXI_MXIDMSCR	0xFF882014
+#define CCI_AXI_MMUS1DMSCR	0xFF882018
+#define CCI_AXI_MMUMPDMSCR	0xFF88201C
+#define CCI_AXI_DVMDMSCR	0xFF882020
+#define CCI_AXI_CCISLVDMSCR	0xFF882100
+
+#define CCI_AXI_IPMMUIDVMCR	0xFF880400
+#define CCI_AXI_IPMMURDVMCR	0xFF880404
+#define CCI_AXI_IPMMUS0DVMCR	0xFF880408
+#define CCI_AXI_IPMMUS1DVMCR	0xFF88040C
+#define CCI_AXI_IPMMUMPDVMCR	0xFF880410
+#define CCI_AXI_IPMMUDSDVMCR	0xFF880414
+#define CCI_AXI_AX2ADDRMASK	0xFF88041C
+
+#ifndef __ASSEMBLY__
+#include <asm/types.h>
+
+/* RWDT */
+struct r8a7790_rwdt {
+	u32 rwtcnt;	/* 0x00 */
+	u32 rwtcsra;	/* 0x04 */
+	u16 rwtcsrb;	/* 0x08 */
+};
+
+/* SWDT */
+struct r8a7790_swdt {
+	u32 swtcnt;	/* 0x00 */
+	u32 swtcsra;	/* 0x04 */
+	u16 swtcsrb;	/* 0x08 */
+};
+
+/* LBSC */
+struct r8a7790_lbsc {
+	u32 cs0ctrl;
+	u32 cs1ctrl;
+	u32 ecs0ctrl;
+	u32 ecs1ctrl;
+	u32 ecs2ctrl;
+	u32 ecs3ctrl;
+	u32 ecs4ctrl;
+	u32 ecs5ctrl;
+	u32 dummy0[4];	/* 0x20 .. 0x2C */
+	u32 cswcr0;
+	u32 cswcr1;
+	u32 ecswcr0;
+	u32 ecswcr1;
+	u32 ecswcr2;
+	u32 ecswcr3;
+	u32 ecswcr4;
+	u32 ecswcr5;
+	u32 exdmawcr0;
+	u32 exdmawcr1;
+	u32 exdmawcr2;
+	u32 dummy1[9];	/* 0x5C .. 0x7C */
+	u32 cspwcr0;
+	u32 cspwcr1;
+	u32 ecspwcr0;
+	u32 ecspwcr1;
+	u32 ecspwcr2;
+	u32 ecspwcr3;
+	u32 ecspwcr4;
+	u32 ecspwcr5;
+	u32 exwtsync;
+	u32 dummy2[3];	/* 0xA4 .. 0xAC */
+	u32 cs0bstctl;
+	u32 cs0btph;
+	u32 dummy3[2];	/* 0xB8 .. 0xBC */
+	u32 cs1gdst;
+	u32 ecs0gdst;
+	u32 ecs1gdst;
+	u32 ecs2gdst;
+	u32 ecs3gdst;
+	u32 ecs4gdst;
+	u32 ecs5gdst;
+	u32 dummy4[5];	/* 0xDC .. 0xEC */
+	u32 exdmaset0;
+	u32 exdmaset1;
+	u32 exdmaset2;
+	u32 dummy5[5];	/* 0xFC .. 0x10C */
+	u32 exdmcr0;
+	u32 exdmcr1;
+	u32 exdmcr2;
+	u32 dummy6[5];	/* 0x11C .. 0x12C */
+	u32 bcintsr;
+	u32 bcintcr;
+	u32 bcintmr;
+	u32 dummy7;	/* 0x13C */
+	u32 exbatlv;
+	u32 exwtsts;
+	u32 dummy8[14];	/* 0x148 .. 0x17C */
+	u32 atacsctrl;
+	u32 dummy9[15]; /* 0x184 .. 0x1BC */
+	u32 exbct;
+	u32 extct;
+};
+
+/* DBSC3 */
+struct r8a7790_dbsc3 {
+	u32 dummy0[3];	/* 0x00 .. 0x08 */
+	u32 dbstate1;
+	u32 dbacen;
+	u32 dbrfen;
+	u32 dbcmd;
+	u32 dbwait;
+	u32 dbkind;
+	u32 dbconf0;
+	u32 dummy1[2];	/* 0x28 .. 0x2C */
+	u32 dbphytype;
+	u32 dummy2[3];	/* 0x34 .. 0x3C */
+	u32 dbtr0;
+	u32 dbtr1;
+	u32 dbtr2;
+	u32 dummy3;	/* 0x4C */
+	u32 dbtr3;
+	u32 dbtr4;
+	u32 dbtr5;
+	u32 dbtr6;
+	u32 dbtr7;
+	u32 dbtr8;
+	u32 dbtr9;
+	u32 dbtr10;
+	u32 dbtr11;
+	u32 dbtr12;
+	u32 dbtr13;
+	u32 dbtr14;
+	u32 dbtr15;
+	u32 dbtr16;
+	u32 dbtr17;
+	u32 dbtr18;
+	u32 dbtr19;
+	u32 dummy4[7];	/* 0x94 .. 0xAC */
+	u32 dbbl;
+	u32 dummy5[3];	/* 0xB4 .. 0xBC */
+	u32 dbadj0;
+	u32 dummy6;	/* 0xC4 */
+	u32 dbadj2;
+	u32 dummy7[5];	/* 0xCC .. 0xDC */
+	u32 dbrfcnf0;
+	u32 dbrfcnf1;
+	u32 dbrfcnf2;
+	u32 dummy8[2];	/* 0xEC .. 0xF0 */
+	u32 dbcalcnf;
+	u32 dbcaltr;
+	u32 dummy9;	/* 0xFC */
+	u32 dbrnk0;
+	u32 dummy10[31];	/* 0x104 .. 0x17C */
+	u32 dbpdncnf;
+	u32 dummy11[47];	/* 0x184 ..0x23C */
+	u32 dbdfistat;
+	u32 dbdficnt;
+	u32 dummy12[14];	/* 0x248 .. 0x27C */
+	u32 dbpdlck;
+	u32 dummy13[3];	/* 0x284 .. 0x28C */
+	u32 dbpdrga;
+	u32 dummy14[3];	/* 0x294 .. 0x29C */
+	u32 dbpdrgd;
+	u32 dummy15[24];	/* 0x2A4 .. 0x300 */
+	u32 dbbs0cnt1;
+	u32 dummy16[30];	/* 0x308 .. 0x37C */
+	u32 dbwt0cnf0;
+	u32 dbwt0cnf1;
+	u32 dbwt0cnf2;
+	u32 dbwt0cnf3;
+	u32 dbwt0cnf4;
+};
+
+/* GPIO */
+struct r8a7790_gpio {
+	u32 iointsel;
+	u32 inoutsel;
+	u32 outdt;
+	u32 indt;
+	u32 intdt;
+	u32 intclr;
+	u32 intmsk;
+	u32 posneg;
+	u32 edglevel;
+	u32 filonoff;
+	u32 intmsks;
+	u32 mskclrs;
+	u32 outdtsel;
+	u32 outdth;
+	u32 outdtl;
+	u32 bothedge;
+};
+
+/* S3C(QoS) */
+struct r8a7790_s3c {
+	u32 s3cexcladdmsk;
+	u32 s3cexclidmsk;
+	u32 s3cadsplcr;
+	u32 s3cmaar;
+	u32 s3carcr11;
+	u32 s3crorr;
+	u32 s3cworr;
+	u32 s3carcr22;
+	u32 dummy1[2];	/* 0x20 .. 0x24 */
+	u32 s3cmctr;
+	u32 dummy2;	/* 0x2C */
+	u32 cconf0;
+	u32 cconf1;
+	u32 cconf2;
+	u32 cconf3;
+};
+
+struct r8a7790_s3c_qos {
+	u32 s3cqos0;
+	u32 s3cqos1;
+	u32 s3cqos2;
+	u32 s3cqos3;
+	u32 s3cqos4;
+	u32 s3cqos5;
+	u32 s3cqos6;
+	u32 s3cqos7;
+	u32 s3cqos8;
+};
+
+/* DBSC(QoS) */
+struct r8a7790_dbsc3_qos {
+	u32 dblgcnt;
+	u32 dbtmval0;
+	u32 dbtmval1;
+	u32 dbtmval2;
+	u32 dbtmval3;
+	u32 dbrqctr;
+	u32 dbthres0;
+	u32 dbthres1;
+	u32 dbthres2;
+	u32 dummy0;	/* 0x24 */
+	u32 dblgqon;
+};
+
+/* MXI(QoS) */
+struct r8a7790_mxi {
+	u32 mxsaar0;
+	u32 mxsaar1;
+	u32 dummy0[7];	/* 0x08 .. 0x20 */
+	u32 mxaxiracr;
+	u32 mxs3cracr;
+	u32 dummy1[2];	/* 0x2C .. 0x30 */
+	u32 mxaxiwacr;
+	u32 mxs3cwacr;
+	u32 dummy2;	/* 0x3C */
+	u32 mxrtcr;
+	u32 mxwtcr;
+};
+
+struct r8a7790_mxi_qos {
+	u32 vspdu0;
+	u32 vspdu1;
+	u32 du0;
+	u32 du1;
+};
+
+/* AXI(QoS) */
+struct r8a7790_axi_qos {
+	u32 qosconf;
+	u32 qosctset0;
+	u32 qosctset1;
+	u32 qosctset2;
+	u32 qosctset3;
+	u32 qosreqctr;
+	u32 qosthres0;
+	u32 qosthres1;
+	u32 qosthres2;
+	u32 qosqon;
+};
+
+#endif
+
+#endif /* __ASM_ARCH_R8A7790_H */
diff --git a/arch/arm/include/asm/arch-rmobile/r8a7791-gpio.h b/arch/arm/include/asm/arch-rmobile/r8a7791-gpio.h
new file mode 100644
index 0000000000..d3cf0c10ac
--- /dev/null
+++ b/arch/arm/include/asm/arch-rmobile/r8a7791-gpio.h
@@ -0,0 +1,438 @@
+#ifndef __ASM_R8A7791_H__
+#define __ASM_R8A7791_H__
+
+/* Pin Function Controller:
+ * GPIO_FN_xx - GPIO used to select pin function
+ * GPIO_GP_x_x - GPIO mapped to real I/O pin on CPU
+ */
+enum {
+	GPIO_GP_0_0, GPIO_GP_0_1, GPIO_GP_0_2, GPIO_GP_0_3,
+	GPIO_GP_0_4, GPIO_GP_0_5, GPIO_GP_0_6, GPIO_GP_0_7,
+	GPIO_GP_0_8, GPIO_GP_0_9, GPIO_GP_0_10, GPIO_GP_0_11,
+	GPIO_GP_0_12, GPIO_GP_0_13, GPIO_GP_0_14, GPIO_GP_0_15,
+	GPIO_GP_0_16, GPIO_GP_0_17, GPIO_GP_0_18, GPIO_GP_0_19,
+	GPIO_GP_0_20, GPIO_GP_0_21, GPIO_GP_0_22, GPIO_GP_0_23,
+	GPIO_GP_0_24, GPIO_GP_0_25, GPIO_GP_0_26, GPIO_GP_0_27,
+	GPIO_GP_0_28, GPIO_GP_0_29, GPIO_GP_0_30, GPIO_GP_0_31,
+
+	GPIO_GP_1_0, GPIO_GP_1_1, GPIO_GP_1_2, GPIO_GP_1_3,
+	GPIO_GP_1_4, GPIO_GP_1_5, GPIO_GP_1_6, GPIO_GP_1_7,
+	GPIO_GP_1_8, GPIO_GP_1_9, GPIO_GP_1_10, GPIO_GP_1_11,
+	GPIO_GP_1_12, GPIO_GP_1_13, GPIO_GP_1_14, GPIO_GP_1_15,
+	GPIO_GP_1_16, GPIO_GP_1_17, GPIO_GP_1_18, GPIO_GP_1_19,
+	GPIO_GP_1_20, GPIO_GP_1_21, GPIO_GP_1_22, GPIO_GP_1_23,
+	GPIO_GP_1_24, GPIO_GP_1_25,
+
+	GPIO_GP_2_0, GPIO_GP_2_1, GPIO_GP_2_2, GPIO_GP_2_3,
+	GPIO_GP_2_4, GPIO_GP_2_5, GPIO_GP_2_6, GPIO_GP_2_7,
+	GPIO_GP_2_8, GPIO_GP_2_9, GPIO_GP_2_10, GPIO_GP_2_11,
+	GPIO_GP_2_12, GPIO_GP_2_13, GPIO_GP_2_14, GPIO_GP_2_15,
+	GPIO_GP_2_16, GPIO_GP_2_17, GPIO_GP_2_18, GPIO_GP_2_19,
+	GPIO_GP_2_20, GPIO_GP_2_21, GPIO_GP_2_22, GPIO_GP_2_23,
+	GPIO_GP_2_24, GPIO_GP_2_25, GPIO_GP_2_26, GPIO_GP_2_27,
+	GPIO_GP_2_28, GPIO_GP_2_29, GPIO_GP_2_30, GPIO_GP_2_31,
+
+	GPIO_GP_3_0, GPIO_GP_3_1, GPIO_GP_3_2, GPIO_GP_3_3,
+	GPIO_GP_3_4, GPIO_GP_3_5, GPIO_GP_3_6, GPIO_GP_3_7,
+	GPIO_GP_3_8, GPIO_GP_3_9, GPIO_GP_3_10, GPIO_GP_3_11,
+	GPIO_GP_3_12, GPIO_GP_3_13, GPIO_GP_3_14, GPIO_GP_3_15,
+	GPIO_GP_3_16, GPIO_GP_3_17, GPIO_GP_3_18, GPIO_GP_3_19,
+	GPIO_GP_3_20, GPIO_GP_3_21, GPIO_GP_3_22, GPIO_GP_3_23,
+	GPIO_GP_3_24, GPIO_GP_3_25, GPIO_GP_3_26, GPIO_GP_3_27,
+	GPIO_GP_3_28, GPIO_GP_3_29, GPIO_GP_3_30, GPIO_GP_3_31,
+
+	GPIO_GP_4_0, GPIO_GP_4_1, GPIO_GP_4_2, GPIO_GP_4_3,
+	GPIO_GP_4_4, GPIO_GP_4_5, GPIO_GP_4_6, GPIO_GP_4_7,
+	GPIO_GP_4_8, GPIO_GP_4_9, GPIO_GP_4_10, GPIO_GP_4_11,
+	GPIO_GP_4_12, GPIO_GP_4_13, GPIO_GP_4_14, GPIO_GP_4_15,
+	GPIO_GP_4_16, GPIO_GP_4_17, GPIO_GP_4_18, GPIO_GP_4_19,
+	GPIO_GP_4_20, GPIO_GP_4_21, GPIO_GP_4_22, GPIO_GP_4_23,
+	GPIO_GP_4_24, GPIO_GP_4_25, GPIO_GP_4_26, GPIO_GP_4_27,
+	GPIO_GP_4_28, GPIO_GP_4_29, GPIO_GP_4_30, GPIO_GP_4_31,
+
+	GPIO_GP_5_0, GPIO_GP_5_1, GPIO_GP_5_2, GPIO_GP_5_3,
+	GPIO_GP_5_4, GPIO_GP_5_5, GPIO_GP_5_6, GPIO_GP_5_7,
+	GPIO_GP_5_8, GPIO_GP_5_9, GPIO_GP_5_10, GPIO_GP_5_11,
+	GPIO_GP_5_12, GPIO_GP_5_13, GPIO_GP_5_14, GPIO_GP_5_15,
+	GPIO_GP_5_16, GPIO_GP_5_17, GPIO_GP_5_18, GPIO_GP_5_19,
+	GPIO_GP_5_20, GPIO_GP_5_21, GPIO_GP_5_22, GPIO_GP_5_23,
+	GPIO_GP_5_24, GPIO_GP_5_25, GPIO_GP_5_26, GPIO_GP_5_27,
+	GPIO_GP_5_28, GPIO_GP_5_29, GPIO_GP_5_30, GPIO_GP_5_31,
+
+	GPIO_GP_6_0, GPIO_GP_6_1, GPIO_GP_6_2, GPIO_GP_6_3,
+	GPIO_GP_6_4, GPIO_GP_6_5, GPIO_GP_6_6, GPIO_GP_6_7,
+	GPIO_GP_6_8, GPIO_GP_6_9, GPIO_GP_6_10, GPIO_GP_6_11,
+	GPIO_GP_6_12, GPIO_GP_6_13, GPIO_GP_6_14, GPIO_GP_6_15,
+	GPIO_GP_6_16, GPIO_GP_6_17, GPIO_GP_6_18, GPIO_GP_6_19,
+	GPIO_GP_6_20, GPIO_GP_6_21, GPIO_GP_6_22, GPIO_GP_6_23,
+	GPIO_GP_6_24, GPIO_GP_6_25, GPIO_GP_6_26, GPIO_GP_6_27,
+	GPIO_GP_6_28, GPIO_GP_6_29, GPIO_GP_6_30, GPIO_GP_6_31,
+
+	GPIO_GP_7_0, GPIO_GP_7_1, GPIO_GP_7_2, GPIO_GP_7_3,
+	GPIO_GP_7_4, GPIO_GP_7_5, GPIO_GP_7_6, GPIO_GP_7_7,
+	GPIO_GP_7_8, GPIO_GP_7_9, GPIO_GP_7_10, GPIO_GP_7_11,
+	GPIO_GP_7_12, GPIO_GP_7_13, GPIO_GP_7_14, GPIO_GP_7_15,
+	GPIO_GP_7_16, GPIO_GP_7_17, GPIO_GP_7_18, GPIO_GP_7_19,
+	GPIO_GP_7_20, GPIO_GP_7_21, GPIO_GP_7_22, GPIO_GP_7_23,
+	GPIO_GP_7_24, GPIO_GP_7_25,
+
+	GPIO_FN_EX_CS0_N, GPIO_FN_RD_N, GPIO_FN_AUDIO_CLKA,
+	GPIO_FN_VI0_CLK, GPIO_FN_VI0_DATA0_VI0_B0,
+	GPIO_FN_VI0_DATA0_VI0_B1, GPIO_FN_VI0_DATA0_VI0_B2,
+	GPIO_FN_VI0_DATA0_VI0_B4, GPIO_FN_VI0_DATA0_VI0_B5,
+	GPIO_FN_VI0_DATA0_VI0_B6, GPIO_FN_VI0_DATA0_VI0_B7,
+	GPIO_FN_USB0_PWEN, GPIO_FN_USB0_OVC, GPIO_FN_USB1_PWEN,
+
+	/* IPSR0 */
+	GPIO_FN_D0, GPIO_FN_D1, GPIO_FN_D2, GPIO_FN_D3, GPIO_FN_D4, GPIO_FN_D5,
+	GPIO_FN_D6, GPIO_FN_D7, GPIO_FN_D8, GPIO_FN_D9, GPIO_FN_D10,
+	GPIO_FN_D11, GPIO_FN_D12, GPIO_FN_D13, GPIO_FN_D14, GPIO_FN_D15,
+	GPIO_FN_A0, GPIO_FN_ATAWR0_N_C, GPIO_FN_MSIOF0_SCK_B,
+	GPIO_FN_SCL0_C, GPIO_FN_PWM2_B,
+	GPIO_FN_A1, GPIO_FN_MSIOF0_SYNC_B, GPIO_FN_A2, GPIO_FN_MSIOF0_SS1_B,
+	GPIO_FN_A3, GPIO_FN_MSIOF0_SS2_B, GPIO_FN_A4, GPIO_FN_MSIOF0_TXD_B,
+	GPIO_FN_A5, GPIO_FN_MSIOF0_RXD_B, GPIO_FN_A6, GPIO_FN_MSIOF1_SCK,
+
+	/* IPSR1 */
+	GPIO_FN_A7, GPIO_FN_MSIOF1_SYNC, GPIO_FN_A8,
+	GPIO_FN_MSIOF1_SS1, GPIO_FN_SCL0,
+	GPIO_FN_A9, GPIO_FN_MSIOF1_SS2, GPIO_FN_SDA0,
+	GPIO_FN_A10, GPIO_FN_MSIOF1_TXD, GPIO_FN_MSIOF1_TXD_D,
+	GPIO_FN_A11, GPIO_FN_MSIOF1_RXD, GPIO_FN_SCL3_D, GPIO_FN_MSIOF1_RXD_D,
+	GPIO_FN_A12, GPIO_FN_FMCLK, GPIO_FN_SDA3_D, GPIO_FN_MSIOF1_SCK_D,
+	GPIO_FN_A13, GPIO_FN_ATAG0_N_C, GPIO_FN_BPFCLK, GPIO_FN_MSIOF1_SS1_D,
+	GPIO_FN_A14, GPIO_FN_ATADIR0_N_C, GPIO_FN_FMIN,
+	GPIO_FN_FMIN_C, GPIO_FN_MSIOF1_SYNC_D,
+	GPIO_FN_A15, GPIO_FN_BPFCLK_C,
+	GPIO_FN_A16, GPIO_FN_DREQ2_B, GPIO_FN_FMCLK_C, GPIO_FN_SCIFA1_SCK_B,
+	GPIO_FN_A17, GPIO_FN_DACK2_B, GPIO_FN_SDA0_C,
+	GPIO_FN_A18, GPIO_FN_DREQ1, GPIO_FN_SCIFA1_RXD_C, GPIO_FN_SCIFB1_RXD_C,
+
+	/* IPSR2 */
+	GPIO_FN_A19, GPIO_FN_DACK1, GPIO_FN_SCIFA1_TXD_C,
+	GPIO_FN_SCIFB1_TXD_C, GPIO_FN_SCIFB1_SCK_B,
+	GPIO_FN_A20, GPIO_FN_SPCLK,
+	GPIO_FN_A21, GPIO_FN_ATAWR0_N_B, GPIO_FN_MOSI_IO0,
+	GPIO_FN_A22, GPIO_FN_MISO_IO1, GPIO_FN_FMCLK_B,
+	GPIO_FN_TX0, GPIO_FN_SCIFA0_TXD,
+	GPIO_FN_A23, GPIO_FN_IO2, GPIO_FN_BPFCLK_B,
+	GPIO_FN_RX0, GPIO_FN_SCIFA0_RXD,
+	GPIO_FN_A24, GPIO_FN_DREQ2, GPIO_FN_IO3,
+	GPIO_FN_TX1, GPIO_FN_SCIFA1_TXD,
+	GPIO_FN_A25, GPIO_FN_DACK2, GPIO_FN_SSL, GPIO_FN_DREQ1_C,
+	GPIO_FN_RX1, GPIO_FN_SCIFA1_RXD,
+	GPIO_FN_CS0_N, GPIO_FN_ATAG0_N_B, GPIO_FN_SCL1,
+	GPIO_FN_CS1_N_A26, GPIO_FN_ATADIR0_N_B, GPIO_FN_SDA1,
+	GPIO_FN_EX_CS1_N, GPIO_FN_MSIOF2_SCK,
+	GPIO_FN_EX_CS2_N, GPIO_FN_ATAWR0_N, GPIO_FN_MSIOF2_SYNC,
+	GPIO_FN_EX_CS3_N, GPIO_FN_ATADIR0_N, GPIO_FN_MSIOF2_TXD,
+	GPIO_FN_ATAG0_N, GPIO_FN_EX_WAIT1,
+
+	/* IPSR3 */
+	GPIO_FN_EX_CS4_N, GPIO_FN_ATARD0_N,
+	GPIO_FN_MSIOF2_RXD, GPIO_FN_EX_WAIT2,
+	GPIO_FN_EX_CS5_N, GPIO_FN_ATACS00_N, GPIO_FN_MSIOF2_SS1,
+	GPIO_FN_HRX1_B, GPIO_FN_SCIFB1_RXD_B,
+	GPIO_FN_PWM1, GPIO_FN_TPU_TO1,
+	GPIO_FN_BS_N, GPIO_FN_ATACS10_N, GPIO_FN_MSIOF2_SS2,
+	GPIO_FN_HTX1_B, GPIO_FN_SCIFB1_TXD_B,
+	GPIO_FN_PWM2, GPIO_FN_TPU_TO2,
+	GPIO_FN_RD_WR_N, GPIO_FN_HRX2_B, GPIO_FN_FMIN_B,
+	GPIO_FN_SCIFB0_RXD_B, GPIO_FN_DREQ1_D,
+	GPIO_FN_WE0_N, GPIO_FN_HCTS2_N_B, GPIO_FN_SCIFB0_TXD_B,
+	GPIO_FN_WE1_N, GPIO_FN_ATARD0_N_B,
+	GPIO_FN_HTX2_B, GPIO_FN_SCIFB0_RTS_N_B,
+	GPIO_FN_EX_WAIT0, GPIO_FN_HRTS2_N_B, GPIO_FN_SCIFB0_CTS_N_B,
+	GPIO_FN_DREQ0, GPIO_FN_PWM3, GPIO_FN_TPU_TO3,
+	GPIO_FN_DACK0, GPIO_FN_DRACK0, GPIO_FN_REMOCON,
+	GPIO_FN_SPEEDIN, GPIO_FN_HSCK0_C, GPIO_FN_HSCK2_C,
+	GPIO_FN_SCIFB0_SCK_B, GPIO_FN_SCIFB2_SCK_B,
+	GPIO_FN_DREQ2_C, GPIO_FN_HTX2_D,
+	GPIO_FN_SSI_SCK0129, GPIO_FN_HRX0_C, GPIO_FN_HRX2_C,
+	GPIO_FN_SCIFB0_RXD_C, GPIO_FN_SCIFB2_RXD_C,
+	GPIO_FN_SSI_WS0129, GPIO_FN_HTX0_C, GPIO_FN_HTX2_C,
+	GPIO_FN_SCIFB0_TXD_C, GPIO_FN_SCIFB2_TXD_C,
+
+	/* IPSR4 */
+	GPIO_FN_SSI_SDATA0, GPIO_FN_SCL0_B,
+	GPIO_FN_SCL7_B, GPIO_FN_MSIOF2_SCK_C,
+	GPIO_FN_SSI_SCK1, GPIO_FN_SDA0_B, GPIO_FN_SDA7_B,
+	GPIO_FN_MSIOF2_SYNC_C, GPIO_FN_GLO_I0_D,
+	GPIO_FN_SSI_WS1, GPIO_FN_SCL1_B, GPIO_FN_SCL8_B,
+	GPIO_FN_MSIOF2_TXD_C, GPIO_FN_GLO_I1_D,
+	GPIO_FN_SSI_SDATA1, GPIO_FN_SDA1_B,
+	GPIO_FN_SDA8_B, GPIO_FN_MSIOF2_RXD_C,
+	GPIO_FN_SSI_SCK2, GPIO_FN_SCL2, GPIO_FN_GPS_CLK_B,
+	GPIO_FN_GLO_Q0_D, GPIO_FN_HSCK1_E,
+	GPIO_FN_SSI_WS2, GPIO_FN_SDA2, GPIO_FN_GPS_SIGN_B,
+	GPIO_FN_RX2_E, GPIO_FN_GLO_Q1_D, GPIO_FN_HCTS1_N_E,
+	GPIO_FN_SSI_SDATA2, GPIO_FN_GPS_MAG_B,
+	GPIO_FN_TX2_E, GPIO_FN_HRTS1_N_E,
+	GPIO_FN_SSI_SCK34, GPIO_FN_SSI_WS34, GPIO_FN_SSI_SDATA3,
+	GPIO_FN_SSI_SCK4, GPIO_FN_GLO_SS_D,
+	GPIO_FN_SSI_WS4, GPIO_FN_GLO_RFON_D,
+	GPIO_FN_SSI_SDATA4, GPIO_FN_MSIOF2_SCK_D,
+	GPIO_FN_SSI_SCK5, GPIO_FN_MSIOF1_SCK_C,
+	GPIO_FN_TS_SDATA0, GPIO_FN_GLO_I0,
+	GPIO_FN_MSIOF2_SYNC_D, GPIO_FN_VI1_R2_B,
+
+	/* IPSR5 */
+	GPIO_FN_SSI_WS5, GPIO_FN_MSIOF1_SYNC_C, GPIO_FN_TS_SCK0,
+	GPIO_FN_GLO_I1, GPIO_FN_MSIOF2_TXD_D, GPIO_FN_VI1_R3_B,
+	GPIO_FN_SSI_SDATA5, GPIO_FN_MSIOF1_TXD_C, GPIO_FN_TS_SDEN0,
+	GPIO_FN_GLO_Q0, GPIO_FN_MSIOF2_SS1_D, GPIO_FN_VI1_R4_B,
+	GPIO_FN_SSI_SCK6, GPIO_FN_MSIOF1_RXD_C, GPIO_FN_TS_SPSYNC0,
+	GPIO_FN_GLO_Q1, GPIO_FN_MSIOF2_RXD_D, GPIO_FN_VI1_R5_B,
+	GPIO_FN_SSI_WS6, GPIO_FN_GLO_SCLK,
+	GPIO_FN_MSIOF2_SS2_D, GPIO_FN_VI1_R6_B,
+	GPIO_FN_SSI_SDATA6, GPIO_FN_STP_IVCXO27_0_B,
+	GPIO_FN_GLO_SDATA, GPIO_FN_VI1_R7_B,
+	GPIO_FN_SSI_SCK78, GPIO_FN_STP_ISCLK_0_B, GPIO_FN_GLO_SS,
+	GPIO_FN_SSI_WS78, GPIO_FN_TX0_D, GPIO_FN_STP_ISD_0_B, GPIO_FN_GLO_RFON,
+	GPIO_FN_SSI_SDATA7, GPIO_FN_RX0_D, GPIO_FN_STP_ISEN_0_B,
+	GPIO_FN_SSI_SDATA8, GPIO_FN_TX1_D, GPIO_FN_STP_ISSYNC_0_B,
+	GPIO_FN_SSI_SCK9, GPIO_FN_RX1_D, GPIO_FN_GLO_SCLK_D,
+	GPIO_FN_SSI_WS9, GPIO_FN_TX3_D, GPIO_FN_CAN0_TX_D, GPIO_FN_GLO_SDATA_D,
+	GPIO_FN_SSI_SDATA9, GPIO_FN_RX3_D, GPIO_FN_CAN0_RX_D,
+
+	/* IPSR6 */
+	GPIO_FN_AUDIO_CLKB, GPIO_FN_STP_OPWM_0_B, GPIO_FN_MSIOF1_SCK_B,
+	GPIO_FN_SCIF_CLK, GPIO_FN_BPFCLK_E,
+	GPIO_FN_AUDIO_CLKC, GPIO_FN_SCIFB0_SCK_C, GPIO_FN_MSIOF1_SYNC_B,
+	GPIO_FN_RX2, GPIO_FN_SCIFA2_RXD, GPIO_FN_FMIN_E,
+	GPIO_FN_AUDIO_CLKOUT, GPIO_FN_MSIOF1_SS1_B,
+	GPIO_FN_TX2, GPIO_FN_SCIFA2_TXD,
+	GPIO_FN_IRQ0, GPIO_FN_SCIFB1_RXD_D, GPIO_FN_INTC_IRQ0_N,
+	GPIO_FN_IRQ1, GPIO_FN_SCIFB1_SCK_C, GPIO_FN_INTC_IRQ1_N,
+	GPIO_FN_IRQ2, GPIO_FN_SCIFB1_TXD_D, GPIO_FN_INTC_IRQ2_N,
+	GPIO_FN_IRQ3, GPIO_FN_SCL4_C,
+	GPIO_FN_MSIOF2_TXD_E, GPIO_FN_INTC_IRQ3_N,
+	GPIO_FN_IRQ4, GPIO_FN_HRX1_C, GPIO_FN_SDA4_C,
+	GPIO_FN_MSIOF2_RXD_E, GPIO_FN_INTC_IRQ4_N,
+	GPIO_FN_IRQ5, GPIO_FN_HTX1_C, GPIO_FN_SCL1_E, GPIO_FN_MSIOF2_SCK_E,
+	GPIO_FN_IRQ6, GPIO_FN_HSCK1_C, GPIO_FN_MSIOF1_SS2_B,
+	GPIO_FN_SDA1_E, GPIO_FN_MSIOF2_SYNC_E,
+	GPIO_FN_IRQ7, GPIO_FN_HCTS1_N_C, GPIO_FN_MSIOF1_TXD_B,
+	GPIO_FN_GPS_CLK_C, GPIO_FN_GPS_CLK_D,
+	GPIO_FN_IRQ8, GPIO_FN_HRTS1_N_C, GPIO_FN_MSIOF1_RXD_B,
+	GPIO_FN_GPS_SIGN_C, GPIO_FN_GPS_SIGN_D,
+
+	/* IPSR7 */
+	GPIO_FN_IRQ9, GPIO_FN_DU1_DOTCLKIN_B, GPIO_FN_CAN_CLK_D,
+	GPIO_FN_GPS_MAG_C, GPIO_FN_SCIF_CLK_B, GPIO_FN_GPS_MAG_D,
+	GPIO_FN_DU1_DR0, GPIO_FN_LCDOUT0, GPIO_FN_VI1_DATA0_B, GPIO_FN_TX0_B,
+	GPIO_FN_SCIFA0_TXD_B, GPIO_FN_MSIOF2_SCK_B,
+	GPIO_FN_DU1_DR1, GPIO_FN_LCDOUT1, GPIO_FN_VI1_DATA1_B, GPIO_FN_RX0_B,
+	GPIO_FN_SCIFA0_RXD_B, GPIO_FN_MSIOF2_SYNC_B,
+	GPIO_FN_DU1_DR2, GPIO_FN_LCDOUT2, GPIO_FN_SSI_SCK0129_B,
+	GPIO_FN_DU1_DR3, GPIO_FN_LCDOUT3, GPIO_FN_SSI_WS0129_B,
+	GPIO_FN_DU1_DR4, GPIO_FN_LCDOUT4, GPIO_FN_SSI_SDATA0_B,
+	GPIO_FN_DU1_DR5, GPIO_FN_LCDOUT5, GPIO_FN_SSI_SCK1_B,
+	GPIO_FN_DU1_DR6, GPIO_FN_LCDOUT6, GPIO_FN_SSI_WS1_B,
+	GPIO_FN_DU1_DR7, GPIO_FN_LCDOUT7, GPIO_FN_SSI_SDATA1_B,
+	GPIO_FN_DU1_DG0, GPIO_FN_LCDOUT8, GPIO_FN_VI1_DATA2_B, GPIO_FN_TX1_B,
+	GPIO_FN_SCIFA1_TXD_B, GPIO_FN_MSIOF2_SS1_B,
+	GPIO_FN_DU1_DG1, GPIO_FN_LCDOUT9, GPIO_FN_VI1_DATA3_B, GPIO_FN_RX1_B,
+	GPIO_FN_SCIFA1_RXD_B, GPIO_FN_MSIOF2_SS2_B,
+	GPIO_FN_DU1_DG2, GPIO_FN_LCDOUT10, GPIO_FN_VI1_DATA4_B,
+	GPIO_FN_SCIF1_SCK_B, GPIO_FN_SCIFA1_SCK, GPIO_FN_SSI_SCK78_B,
+
+	/* IPSR8 */
+	GPIO_FN_DU1_DG3, GPIO_FN_LCDOUT11,
+	GPIO_FN_VI1_DATA5_B, GPIO_FN_SSI_WS78_B,
+	GPIO_FN_DU1_DG4, GPIO_FN_LCDOUT12, GPIO_FN_VI1_DATA6_B,
+	GPIO_FN_HRX0_B, GPIO_FN_SCIFB2_RXD_B, GPIO_FN_SSI_SDATA7_B,
+	GPIO_FN_DU1_DG5, GPIO_FN_LCDOUT13, GPIO_FN_VI1_DATA7_B,
+	GPIO_FN_HCTS0_N_B, GPIO_FN_SCIFB2_TXD_B, GPIO_FN_SSI_SDATA8_B,
+	GPIO_FN_DU1_DG6, GPIO_FN_LCDOUT14, GPIO_FN_HRTS0_N_B,
+	GPIO_FN_SCIFB2_CTS_N_B, GPIO_FN_SSI_SCK9_B,
+	GPIO_FN_DU1_DG7, GPIO_FN_LCDOUT15, GPIO_FN_HTX0_B,
+	GPIO_FN_SCIFB2_RTS_N_B, GPIO_FN_SSI_WS9_B,
+	GPIO_FN_DU1_DB0, GPIO_FN_LCDOUT16, GPIO_FN_VI1_CLK_B, GPIO_FN_TX2_B,
+	GPIO_FN_SCIFA2_TXD_B, GPIO_FN_MSIOF2_TXD_B,
+	GPIO_FN_DU1_DB1, GPIO_FN_LCDOUT17, GPIO_FN_VI1_HSYNC_N_B,
+	GPIO_FN_RX2_B, GPIO_FN_SCIFA2_RXD_B, GPIO_FN_MSIOF2_RXD_B,
+	GPIO_FN_DU1_DB2, GPIO_FN_LCDOUT18, GPIO_FN_VI1_VSYNC_N_B,
+	GPIO_FN_SCIF2_SCK_B, GPIO_FN_SCIFA2_SCK, GPIO_FN_SSI_SDATA9_B,
+	GPIO_FN_DU1_DB3, GPIO_FN_LCDOUT19, GPIO_FN_VI1_CLKENB_B,
+	GPIO_FN_DU1_DB4, GPIO_FN_LCDOUT20,
+	GPIO_FN_VI1_FIELD_B, GPIO_FN_CAN1_RX,
+	GPIO_FN_DU1_DB5, GPIO_FN_LCDOUT21, GPIO_FN_TX3,
+	GPIO_FN_SCIFA3_TXD, GPIO_FN_CAN1_TX,
+
+	/* IPSR9 */
+	GPIO_FN_DU1_DB6, GPIO_FN_LCDOUT22, GPIO_FN_SCL3_C,
+	GPIO_FN_RX3, GPIO_FN_SCIFA3_RXD,
+	GPIO_FN_DU1_DB7, GPIO_FN_LCDOUT23, GPIO_FN_SDA3_C,
+	GPIO_FN_SCIF3_SCK, GPIO_FN_SCIFA3_SCK,
+	GPIO_FN_DU1_DOTCLKIN, GPIO_FN_QSTVA_QVS,
+	GPIO_FN_DU1_DOTCLKOUT0, GPIO_FN_QCLK,
+	GPIO_FN_DU1_DOTCLKOUT1, GPIO_FN_QSTVB_QVE, GPIO_FN_CAN0_TX,
+	GPIO_FN_TX3_B, GPIO_FN_SCL2_B, GPIO_FN_PWM4,
+	GPIO_FN_DU1_EXHSYNC_DU1_HSYNC, GPIO_FN_QSTH_QHS,
+	GPIO_FN_DU1_EXVSYNC_DU1_VSYNC, GPIO_FN_QSTB_QHE,
+	GPIO_FN_DU1_EXODDF_DU1_ODDF_DISP_CDE, GPIO_FN_QCPV_QDE,
+	GPIO_FN_CAN0_RX, GPIO_FN_RX3_B, GPIO_FN_SDA2_B,
+	GPIO_FN_DU1_DISP, GPIO_FN_QPOLA,
+	GPIO_FN_DU1_CDE, GPIO_FN_QPOLB, GPIO_FN_PWM4_B,
+	GPIO_FN_VI0_CLKENB, GPIO_FN_TX4,
+	GPIO_FN_SCIFA4_TXD, GPIO_FN_TS_SDATA0_D,
+	GPIO_FN_VI0_FIELD, GPIO_FN_RX4, GPIO_FN_SCIFA4_RXD, GPIO_FN_TS_SCK0_D,
+	GPIO_FN_VI0_HSYNC_N, GPIO_FN_TX5,
+	GPIO_FN_SCIFA5_TXD, GPIO_FN_TS_SDEN0_D,
+	GPIO_FN_VI0_VSYNC_N, GPIO_FN_RX5,
+	GPIO_FN_SCIFA5_RXD, GPIO_FN_TS_SPSYNC0_D,
+	GPIO_FN_VI0_DATA3_VI0_B3, GPIO_FN_SCIF3_SCK_B, GPIO_FN_SCIFA3_SCK_B,
+	GPIO_FN_VI0_G0, GPIO_FN_SCL8, GPIO_FN_STP_IVCXO27_0_C, GPIO_FN_SCL4,
+	GPIO_FN_HCTS2_N, GPIO_FN_SCIFB2_CTS_N, GPIO_FN_ATAWR1_N,
+
+	/* IPSR10 */
+	GPIO_FN_VI0_G1, GPIO_FN_SDA8, GPIO_FN_STP_ISCLK_0_C, GPIO_FN_SDA4,
+	GPIO_FN_HRTS2_N, GPIO_FN_SCIFB2_RTS_N, GPIO_FN_ATADIR1_N,
+	GPIO_FN_VI0_G2, GPIO_FN_VI2_HSYNC_N, GPIO_FN_STP_ISD_0_C,
+	GPIO_FN_SCL3_B, GPIO_FN_HSCK2, GPIO_FN_SCIFB2_SCK, GPIO_FN_ATARD1_N,
+	GPIO_FN_VI0_G3, GPIO_FN_VI2_VSYNC_N, GPIO_FN_STP_ISEN_0_C,
+	GPIO_FN_SDA3_B, GPIO_FN_HRX2, GPIO_FN_SCIFB2_RXD, GPIO_FN_ATACS01_N,
+	GPIO_FN_VI0_G4, GPIO_FN_VI2_CLKENB, GPIO_FN_STP_ISSYNC_0_C,
+	GPIO_FN_HTX2, GPIO_FN_SCIFB2_TXD, GPIO_FN_SCIFB0_SCK_D,
+	GPIO_FN_VI0_G5, GPIO_FN_VI2_FIELD, GPIO_FN_STP_OPWM_0_C,
+	GPIO_FN_FMCLK_D, GPIO_FN_CAN0_TX_E,
+	GPIO_FN_HTX1_D, GPIO_FN_SCIFB0_TXD_D,
+	GPIO_FN_VI0_G6, GPIO_FN_VI2_CLK, GPIO_FN_BPFCLK_D,
+	GPIO_FN_VI0_G7, GPIO_FN_VI2_DATA0, GPIO_FN_FMIN_D,
+	GPIO_FN_VI0_R0, GPIO_FN_VI2_DATA1, GPIO_FN_GLO_I0_B,
+	GPIO_FN_TS_SDATA0_C, GPIO_FN_ATACS11_N,
+	GPIO_FN_VI0_R1, GPIO_FN_VI2_DATA2, GPIO_FN_GLO_I1_B,
+	GPIO_FN_TS_SCK0_C, GPIO_FN_ATAG1_N,
+	GPIO_FN_VI0_R2, GPIO_FN_VI2_DATA3,
+	GPIO_FN_GLO_Q0_B, GPIO_FN_TS_SDEN0_C,
+	GPIO_FN_VI0_R3, GPIO_FN_VI2_DATA4,
+	GPIO_FN_GLO_Q1_B, GPIO_FN_TS_SPSYNC0_C,
+	GPIO_FN_VI0_R4, GPIO_FN_VI2_DATA5, GPIO_FN_GLO_SCLK_B,
+	GPIO_FN_TX0_C, GPIO_FN_SCL1_D,
+
+	/* IPSR11 */
+	GPIO_FN_VI0_R5, GPIO_FN_VI2_DATA6, GPIO_FN_GLO_SDATA_B,
+	GPIO_FN_RX0_C, GPIO_FN_SDA1_D,
+	GPIO_FN_VI0_R6, GPIO_FN_VI2_DATA7, GPIO_FN_GLO_SS_B,
+	GPIO_FN_TX1_C, GPIO_FN_SCL4_B,
+	GPIO_FN_VI0_R7, GPIO_FN_GLO_RFON_B, GPIO_FN_RX1_C, GPIO_FN_CAN0_RX_E,
+	GPIO_FN_SDA4_B, GPIO_FN_HRX1_D, GPIO_FN_SCIFB0_RXD_D,
+	GPIO_FN_VI1_HSYNC_N, GPIO_FN_AVB_RXD0, GPIO_FN_TS_SDATA0_B,
+	GPIO_FN_TX4_B, GPIO_FN_SCIFA4_TXD_B,
+	GPIO_FN_VI1_VSYNC_N, GPIO_FN_AVB_RXD1, GPIO_FN_TS_SCK0_B,
+	GPIO_FN_RX4_B, GPIO_FN_SCIFA4_RXD_B,
+	GPIO_FN_VI1_CLKENB, GPIO_FN_AVB_RXD2, GPIO_FN_TS_SDEN0_B,
+	GPIO_FN_VI1_FIELD, GPIO_FN_AVB_RXD3, GPIO_FN_TS_SPSYNC0_B,
+	GPIO_FN_VI1_CLK, GPIO_FN_AVB_RXD4, GPIO_FN_VI1_DATA0, GPIO_FN_AVB_RXD5,
+	GPIO_FN_VI1_DATA1, GPIO_FN_AVB_RXD6,
+	GPIO_FN_VI1_DATA2, GPIO_FN_AVB_RXD7,
+	GPIO_FN_VI1_DATA3, GPIO_FN_AVB_RX_ER,
+	GPIO_FN_VI1_DATA4, GPIO_FN_AVB_MDIO,
+	GPIO_FN_VI1_DATA5, GPIO_FN_AVB_RX_DV,
+	GPIO_FN_VI1_DATA6, GPIO_FN_AVB_MAGIC,
+	GPIO_FN_VI1_DATA7, GPIO_FN_AVB_MDC,
+	GPIO_FN_ETH_MDIO, GPIO_FN_AVB_RX_CLK, GPIO_FN_SCL2_C,
+	GPIO_FN_ETH_CRS_DV, GPIO_FN_AVB_LINK, GPIO_FN_SDA2_C,
+
+	/* IPSR12 */
+	GPIO_FN_ETH_RX_ER, GPIO_FN_AVB_CRS, GPIO_FN_SCL3, GPIO_FN_SCL7,
+	GPIO_FN_ETH_RXD0, GPIO_FN_AVB_PHY_INT, GPIO_FN_SDA3, GPIO_FN_SDA7,
+	GPIO_FN_ETH_RXD1, GPIO_FN_AVB_GTXREFCLK, GPIO_FN_CAN0_TX_C,
+	GPIO_FN_SCL2_D, GPIO_FN_MSIOF1_RXD_E,
+	GPIO_FN_ETH_LINK, GPIO_FN_AVB_TXD0, GPIO_FN_CAN0_RX_C,
+	GPIO_FN_SDA2_D, GPIO_FN_MSIOF1_SCK_E,
+	GPIO_FN_ETH_REFCLK, GPIO_FN_AVB_TXD1, GPIO_FN_SCIFA3_RXD_B,
+	GPIO_FN_CAN1_RX_C, GPIO_FN_MSIOF1_SYNC_E,
+	GPIO_FN_ETH_TXD1, GPIO_FN_AVB_TXD2, GPIO_FN_SCIFA3_TXD_B,
+	GPIO_FN_CAN1_TX_C, GPIO_FN_MSIOF1_TXD_E,
+	GPIO_FN_ETH_TX_EN, GPIO_FN_AVB_TXD3,
+	GPIO_FN_TCLK1_B, GPIO_FN_CAN_CLK_B,
+	GPIO_FN_ETH_MAGIC, GPIO_FN_AVB_TXD4, GPIO_FN_IETX_C,
+	GPIO_FN_ETH_TXD0, GPIO_FN_AVB_TXD5, GPIO_FN_IECLK_C,
+	GPIO_FN_ETH_MDC, GPIO_FN_AVB_TXD6, GPIO_FN_IERX_C,
+	GPIO_FN_STP_IVCXO27_0, GPIO_FN_AVB_TXD7, GPIO_FN_SCIFB2_TXD_D,
+	GPIO_FN_ADIDATA_B, GPIO_FN_MSIOF0_SYNC_C,
+	GPIO_FN_STP_ISCLK_0, GPIO_FN_AVB_TX_EN, GPIO_FN_SCIFB2_RXD_D,
+	GPIO_FN_ADICS_SAMP_B, GPIO_FN_MSIOF0_SCK_C,
+
+	/* IPSR13 */
+	GPIO_FN_STP_ISD_0, GPIO_FN_AVB_TX_ER, GPIO_FN_SCIFB2_SCK_C,
+	GPIO_FN_ADICLK_B, GPIO_FN_MSIOF0_SS1_C,
+	GPIO_FN_STP_ISEN_0, GPIO_FN_AVB_TX_CLK,
+	GPIO_FN_ADICHS0_B, GPIO_FN_MSIOF0_SS2_C,
+	GPIO_FN_STP_ISSYNC_0, GPIO_FN_AVB_COL,
+	GPIO_FN_ADICHS1_B, GPIO_FN_MSIOF0_RXD_C,
+	GPIO_FN_STP_OPWM_0, GPIO_FN_AVB_GTX_CLK, GPIO_FN_PWM0_B,
+	GPIO_FN_ADICHS2_B, GPIO_FN_MSIOF0_TXD_C,
+	GPIO_FN_SD0_CLK, GPIO_FN_SPCLK_B, GPIO_FN_SD0_CMD, GPIO_FN_MOSI_IO0_B,
+	GPIO_FN_SD0_DATA0, GPIO_FN_MISO_IO1_B,
+	GPIO_FN_SD0_DATA1, GPIO_FN_IO2_B,
+	GPIO_FN_SD0_DATA2, GPIO_FN_IO3_B, GPIO_FN_SD0_DATA3, GPIO_FN_SSL_B,
+	GPIO_FN_SD0_CD, GPIO_FN_MMC_D6_B,
+	GPIO_FN_SIM0_RST_B, GPIO_FN_CAN0_RX_F,
+	GPIO_FN_SCIFA5_TXD_B, GPIO_FN_TX3_C,
+	GPIO_FN_SD0_WP, GPIO_FN_MMC_D7_B, GPIO_FN_SIM0_D_B, GPIO_FN_CAN0_TX_F,
+	GPIO_FN_SCIFA5_RXD_B, GPIO_FN_RX3_C,
+	GPIO_FN_SD1_CMD, GPIO_FN_REMOCON_B,
+	GPIO_FN_SD1_DATA0, GPIO_FN_SPEEDIN_B,
+	GPIO_FN_SD1_DATA1, GPIO_FN_IETX_B, GPIO_FN_SD1_DATA2, GPIO_FN_IECLK_B,
+	GPIO_FN_SD1_DATA3, GPIO_FN_IERX_B,
+	GPIO_FN_SD1_CD, GPIO_FN_PWM0, GPIO_FN_TPU_TO0, GPIO_FN_SCL1_C,
+
+	/* IPSR14 */
+	GPIO_FN_SD1_WP, GPIO_FN_PWM1_B, GPIO_FN_SDA1_C,
+	GPIO_FN_SD2_CLK, GPIO_FN_MMC_CLK, GPIO_FN_SD2_CMD, GPIO_FN_MMC_CMD,
+	GPIO_FN_SD2_DATA0, GPIO_FN_MMC_D0, GPIO_FN_SD2_DATA1, GPIO_FN_MMC_D1,
+	GPIO_FN_SD2_DATA2, GPIO_FN_MMC_D2, GPIO_FN_SD2_DATA3, GPIO_FN_MMC_D3,
+	GPIO_FN_SD2_CD, GPIO_FN_MMC_D4, GPIO_FN_SCL8_C,
+	GPIO_FN_TX5_B, GPIO_FN_SCIFA5_TXD_C,
+	GPIO_FN_SD2_WP, GPIO_FN_MMC_D5, GPIO_FN_SDA8_C,
+	GPIO_FN_RX5_B, GPIO_FN_SCIFA5_RXD_C,
+	GPIO_FN_MSIOF0_SCK, GPIO_FN_RX2_C, GPIO_FN_ADIDATA,
+	GPIO_FN_VI1_CLK_C, GPIO_FN_VI1_G0_B,
+	GPIO_FN_MSIOF0_SYNC, GPIO_FN_TX2_C, GPIO_FN_ADICS_SAMP,
+	GPIO_FN_VI1_CLKENB_C, GPIO_FN_VI1_G1_B,
+	GPIO_FN_MSIOF0_TXD, GPIO_FN_ADICLK,
+	GPIO_FN_VI1_FIELD_C, GPIO_FN_VI1_G2_B,
+	GPIO_FN_MSIOF0_RXD, GPIO_FN_ADICHS0,
+	GPIO_FN_VI1_DATA0_C, GPIO_FN_VI1_G3_B,
+	GPIO_FN_MSIOF0_SS1, GPIO_FN_MMC_D6, GPIO_FN_ADICHS1, GPIO_FN_TX0_E,
+	GPIO_FN_VI1_HSYNC_N_C, GPIO_FN_SCL7_C, GPIO_FN_VI1_G4_B,
+	GPIO_FN_MSIOF0_SS2, GPIO_FN_MMC_D7, GPIO_FN_ADICHS2, GPIO_FN_RX0_E,
+	GPIO_FN_VI1_VSYNC_N_C, GPIO_FN_SDA7_C, GPIO_FN_VI1_G5_B,
+
+	/* IPSR15 */
+	GPIO_FN_SIM0_RST, GPIO_FN_IETX, GPIO_FN_CAN1_TX_D,
+	GPIO_FN_SIM0_CLK, GPIO_FN_IECLK, GPIO_FN_CAN_CLK_C,
+	GPIO_FN_SIM0_D, GPIO_FN_IERX, GPIO_FN_CAN1_RX_D,
+	GPIO_FN_GPS_CLK, GPIO_FN_DU1_DOTCLKIN_C, GPIO_FN_AUDIO_CLKB_B,
+	GPIO_FN_PWM5_B, GPIO_FN_SCIFA3_TXD_C,
+	GPIO_FN_GPS_SIGN, GPIO_FN_TX4_C, GPIO_FN_SCIFA4_TXD_C, GPIO_FN_PWM5,
+	GPIO_FN_VI1_G6_B, GPIO_FN_SCIFA3_RXD_C,
+	GPIO_FN_GPS_MAG, GPIO_FN_RX4_C, GPIO_FN_SCIFA4_RXD_C, GPIO_FN_PWM6,
+	GPIO_FN_VI1_G7_B, GPIO_FN_SCIFA3_SCK_C,
+	GPIO_FN_HCTS0_N, GPIO_FN_SCIFB0_CTS_N, GPIO_FN_GLO_I0_C,
+	GPIO_FN_TCLK1, GPIO_FN_VI1_DATA1_C,
+	GPIO_FN_HRTS0_N, GPIO_FN_SCIFB0_RTS_N,
+	GPIO_FN_GLO_I1_C, GPIO_FN_VI1_DATA2_C,
+	GPIO_FN_HSCK0, GPIO_FN_SCIFB0_SCK, GPIO_FN_GLO_Q0_C, GPIO_FN_CAN_CLK,
+	GPIO_FN_TCLK2, GPIO_FN_VI1_DATA3_C,
+	GPIO_FN_HRX0, GPIO_FN_SCIFB0_RXD, GPIO_FN_GLO_Q1_C,
+	GPIO_FN_CAN0_RX_B, GPIO_FN_VI1_DATA4_C,
+	GPIO_FN_HTX0, GPIO_FN_SCIFB0_TXD, GPIO_FN_GLO_SCLK_C,
+	GPIO_FN_CAN0_TX_B, GPIO_FN_VI1_DATA5_C,
+
+	/* IPSR16 */
+	GPIO_FN_HRX1, GPIO_FN_SCIFB1_RXD, GPIO_FN_VI1_R0_B,
+	GPIO_FN_GLO_SDATA_C, GPIO_FN_VI1_DATA6_C,
+	GPIO_FN_HTX1, GPIO_FN_SCIFB1_TXD, GPIO_FN_VI1_R1_B,
+	GPIO_FN_GLO_SS_C, GPIO_FN_VI1_DATA7_C,
+	GPIO_FN_HSCK1, GPIO_FN_SCIFB1_SCK, GPIO_FN_MLB_CK, GPIO_FN_GLO_RFON_C,
+	GPIO_FN_HCTS1_N, GPIO_FN_SCIFB1_CTS_N,
+	GPIO_FN_MLB_SIG, GPIO_FN_CAN1_TX_B,
+	GPIO_FN_HRTS1_N, GPIO_FN_SCIFB1_RTS_N,
+	GPIO_FN_MLB_DAT, GPIO_FN_CAN1_RX_B,
+};
+
+#endif /* __ASM_R8A7791_H__ */
diff --git a/arch/arm/include/asm/arch-rmobile/r8a7791.h b/arch/arm/include/asm/arch-rmobile/r8a7791.h
new file mode 100644
index 0000000000..ff30180591
--- /dev/null
+++ b/arch/arm/include/asm/arch-rmobile/r8a7791.h
@@ -0,0 +1,665 @@
+/*
+ * arch/arm/include/asm/arch-rmobile/r8a7791.h
+ *
+ * Copyright (C) 2013 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#ifndef __ASM_ARCH_R8A7791_H
+#define __ASM_ARCH_R8A7791_H
+
+/*
+ * R8A7791 I/O Addresses
+ */
+#define	RWDT_BASE	0xE6020000
+#define	SWDT_BASE	0xE6030000
+#define	LBSC_BASE	0xFEC00200
+#define DBSC3_0_BASE	0xE6790000
+#define DBSC3_1_BASE	0xE67A0000
+#define TMU_BASE	0xE61E0000
+#define	GPIO5_BASE	0xE6055000
+#define SH_QSPI_BASE	0xE6B10000
+
+#define S3C_BASE	0xE6784000
+#define S3C_INT_BASE	0xE6784A00
+#define S3C_MEDIA_BASE	0xE6784B00
+
+#define S3C_QOS_DCACHE_BASE	0xE6784BDC
+#define S3C_QOS_CCI0_BASE	0xE6784C00
+#define S3C_QOS_CCI1_BASE	0xE6784C24
+#define S3C_QOS_MXI_BASE	0xE6784C48
+#define S3C_QOS_AXI_BASE	0xE6784C6C
+
+#define DBSC3_0_QOS_R0_BASE	0xE6791000
+#define DBSC3_0_QOS_R1_BASE	0xE6791100
+#define DBSC3_0_QOS_R2_BASE	0xE6791200
+#define DBSC3_0_QOS_R3_BASE	0xE6791300
+#define DBSC3_0_QOS_R4_BASE	0xE6791400
+#define DBSC3_0_QOS_R5_BASE	0xE6791500
+#define DBSC3_0_QOS_R6_BASE	0xE6791600
+#define DBSC3_0_QOS_R7_BASE	0xE6791700
+#define DBSC3_0_QOS_R8_BASE	0xE6791800
+#define DBSC3_0_QOS_R9_BASE	0xE6791900
+#define DBSC3_0_QOS_R10_BASE	0xE6791A00
+#define DBSC3_0_QOS_R11_BASE	0xE6791B00
+#define DBSC3_0_QOS_R12_BASE	0xE6791C00
+#define DBSC3_0_QOS_R13_BASE	0xE6791D00
+#define DBSC3_0_QOS_R14_BASE	0xE6791E00
+#define DBSC3_0_QOS_R15_BASE	0xE6791F00
+#define DBSC3_0_QOS_W0_BASE	0xE6792000
+#define DBSC3_0_QOS_W1_BASE	0xE6792100
+#define DBSC3_0_QOS_W2_BASE	0xE6792200
+#define DBSC3_0_QOS_W3_BASE	0xE6792300
+#define DBSC3_0_QOS_W4_BASE	0xE6792400
+#define DBSC3_0_QOS_W5_BASE	0xE6792500
+#define DBSC3_0_QOS_W6_BASE	0xE6792600
+#define DBSC3_0_QOS_W7_BASE	0xE6792700
+#define DBSC3_0_QOS_W8_BASE	0xE6792800
+#define DBSC3_0_QOS_W9_BASE	0xE6792900
+#define DBSC3_0_QOS_W10_BASE	0xE6792A00
+#define DBSC3_0_QOS_W11_BASE	0xE6792B00
+#define DBSC3_0_QOS_W12_BASE	0xE6792C00
+#define DBSC3_0_QOS_W13_BASE	0xE6792D00
+#define DBSC3_0_QOS_W14_BASE	0xE6792E00
+#define DBSC3_0_QOS_W15_BASE	0xE6792F00
+
+#define DBSC3_1_QOS_R0_BASE	0xE67A1000
+#define DBSC3_1_QOS_R1_BASE	0xE67A1100
+#define DBSC3_1_QOS_R2_BASE	0xE67A1200
+#define DBSC3_1_QOS_R3_BASE	0xE67A1300
+#define DBSC3_1_QOS_R4_BASE	0xE67A1400
+#define DBSC3_1_QOS_R5_BASE	0xE67A1500
+#define DBSC3_1_QOS_R6_BASE	0xE67A1600
+#define DBSC3_1_QOS_R7_BASE	0xE67A1700
+#define DBSC3_1_QOS_R8_BASE	0xE67A1800
+#define DBSC3_1_QOS_R9_BASE	0xE67A1900
+#define DBSC3_1_QOS_R10_BASE	0xE67A1A00
+#define DBSC3_1_QOS_R11_BASE	0xE67A1B00
+#define DBSC3_1_QOS_R12_BASE	0xE67A1C00
+#define DBSC3_1_QOS_R13_BASE	0xE67A1D00
+#define DBSC3_1_QOS_R14_BASE	0xE67A1E00
+#define DBSC3_1_QOS_R15_BASE	0xE67A1F00
+#define DBSC3_1_QOS_W0_BASE	0xE67A2000
+#define DBSC3_1_QOS_W1_BASE	0xE67A2100
+#define DBSC3_1_QOS_W2_BASE	0xE67A2200
+#define DBSC3_1_QOS_W3_BASE	0xE67A2300
+#define DBSC3_1_QOS_W4_BASE	0xE67A2400
+#define DBSC3_1_QOS_W5_BASE	0xE67A2500
+#define DBSC3_1_QOS_W6_BASE	0xE67A2600
+#define DBSC3_1_QOS_W7_BASE	0xE67A2700
+#define DBSC3_1_QOS_W8_BASE	0xE67A2800
+#define DBSC3_1_QOS_W9_BASE	0xE67A2900
+#define DBSC3_1_QOS_W10_BASE	0xE67A2A00
+#define DBSC3_1_QOS_W11_BASE	0xE67A2B00
+#define DBSC3_1_QOS_W12_BASE	0xE67A2C00
+#define DBSC3_1_QOS_W13_BASE	0xE67A2D00
+#define DBSC3_1_QOS_W14_BASE	0xE67A2E00
+#define DBSC3_1_QOS_W15_BASE	0xE67A2F00
+
+#define DBSC3_0_DBADJ2		0xE67900C8
+
+#define CCI_400_MAXOT_1		0xF0091110
+#define CCI_400_MAXOT_2		0xF0092110
+#define CCI_400_QOSCNTL_1	0xF009110C
+#define CCI_400_QOSCNTL_2	0xF009210C
+
+#define	MXI_BASE		0xFE960000
+#define	MXI_QOS_BASE		0xFE960300
+
+#define SYS_AXI_SYX64TO128_BASE	0xFF800300
+#define SYS_AXI_AVB_BASE	0xFF800340
+#define SYS_AXI_G2D_BASE	0xFF800540
+#define SYS_AXI_IMP0_BASE	0xFF800580
+#define SYS_AXI_IMP1_BASE	0xFF8005C0
+#define SYS_AXI_IMUX0_BASE	0xFF800600
+#define SYS_AXI_IMUX1_BASE	0xFF800640
+#define SYS_AXI_IMUX2_BASE	0xFF800680
+#define SYS_AXI_LBS_BASE	0xFF8006C0
+#define SYS_AXI_MMUDS_BASE	0xFF800700
+#define SYS_AXI_MMUM_BASE	0xFF800740
+#define SYS_AXI_MMUR_BASE	0xFF800780
+#define SYS_AXI_MMUS0_BASE	0xFF8007C0
+#define SYS_AXI_MMUS1_BASE	0xFF800800
+#define SYS_AXI_MTSB0_BASE	0xFF800880
+#define SYS_AXI_MTSB1_BASE	0xFF8008C0
+#define SYS_AXI_PCI_BASE	0xFF800900
+#define SYS_AXI_RTX_BASE	0xFF800940
+#define SYS_AXI_SDS0_BASE	0xFF800A80
+#define SYS_AXI_SDS1_BASE	0xFF800AC0
+#define SYS_AXI_USB20_BASE	0xFF800C00
+#define SYS_AXI_USB21_BASE	0xFF800C40
+#define SYS_AXI_USB22_BASE	0xFF800C80
+#define SYS_AXI_USB30_BASE	0xFF800CC0
+#define SYS_AXI_AX2M_BASE	0xFF800380
+#define SYS_AXI_CC50_BASE	0xFF8003C0
+#define SYS_AXI_CCI_BASE	0xFF800440
+#define SYS_AXI_CS_BASE		0xFF800480
+#define SYS_AXI_DDM_BASE	0xFF8004C0
+#define SYS_AXI_ETH_BASE	0xFF800500
+#define SYS_AXI_MPXM_BASE	0xFF800840
+#define SYS_AXI_SAT0_BASE	0xFF800980
+#define SYS_AXI_SAT1_BASE	0xFF8009C0
+#define SYS_AXI_SDM0_BASE	0xFF800A00
+#define SYS_AXI_SDM1_BASE	0xFF800A40
+#define SYS_AXI_TRAB_BASE	0xFF800B00
+#define SYS_AXI_UDM0_BASE	0xFF800B80
+#define SYS_AXI_UDM1_BASE	0xFF800BC0
+
+#define RT_AXI_SHX_BASE		0xFF810100
+#define RT_AXI_DBG_BASE		0xFF810140
+#define RT_AXI_RDM_BASE		0xFF810180
+#define RT_AXI_RDS_BASE		0xFF8101C0
+#define RT_AXI_RTX64TO128_BASE	0xFF810200
+#define RT_AXI_STPRO_BASE	0xFF810240
+#define RT_AXI_SY2RT_BASE	0xFF810280
+
+#define MP_AXI_ADSP_BASE	0xFF820100
+#define MP_AXI_ASDS0_BASE	0xFF8201C0
+#define MP_AXI_ASDS1_BASE	0xFF820200
+#define MP_AXI_MLP_BASE		0xFF820240
+#define MP_AXI_MMUMP_BASE	0xFF820280
+#define MP_AXI_SPU_BASE		0xFF8202C0
+#define MP_AXI_SPUC_BASE	0xFF820300
+
+#define SYS_AXI256_AXI128TO256_BASE	0xFF860100
+#define SYS_AXI256_SYX_BASE	0xFF860140
+#define SYS_AXI256_MPX_BASE	0xFF860180
+#define SYS_AXI256_MXI_BASE	0xFF8601C0
+
+#define CCI_AXI_MMUS0_BASE	0xFF880100
+#define CCI_AXI_SYX2_BASE	0xFF880140
+#define CCI_AXI_MMUR_BASE	0xFF880180
+#define CCI_AXI_MMUDS_BASE	0xFF8801C0
+#define CCI_AXI_MMUM_BASE	0xFF880200
+#define CCI_AXI_MXI_BASE	0xFF880240
+#define CCI_AXI_MMUS1_BASE	0xFF880280
+#define CCI_AXI_MMUMP_BASE	0xFF8802C0
+
+#define MEDIA_AXI_MXR_BASE	0xFE960080
+#define MEDIA_AXI_MXW_BASE	0xFE9600C0
+#define MEDIA_AXI_JPR_BASE	0xFE964100
+#define MEDIA_AXI_JPW_BASE	0xFE966100
+#define MEDIA_AXI_GCU0R_BASE	0xFE964140
+#define MEDIA_AXI_GCU0W_BASE	0xFE966140
+#define MEDIA_AXI_GCU1R_BASE	0xFE964180
+#define MEDIA_AXI_GCU1W_BASE	0xFE966180
+#define MEDIA_AXI_TDMR_BASE	0xFE964500
+#define MEDIA_AXI_TDMW_BASE	0xFE966500
+#define MEDIA_AXI_VSP0CR_BASE	0xFE964540
+#define MEDIA_AXI_VSP0CW_BASE	0xFE966540
+#define MEDIA_AXI_VSP1CR_BASE	0xFE964580
+#define MEDIA_AXI_VSP1CW_BASE	0xFE966580
+#define MEDIA_AXI_VSPDU0CR_BASE	0xFE9645C0
+#define MEDIA_AXI_VSPDU0CW_BASE	0xFE9665C0
+#define MEDIA_AXI_VSPDU1CR_BASE	0xFE964600
+#define MEDIA_AXI_VSPDU1CW_BASE	0xFE966600
+#define MEDIA_AXI_VIN0W_BASE	0xFE966900
+#define MEDIA_AXI_VSP0R_BASE	0xFE964D00
+#define MEDIA_AXI_VSP0W_BASE	0xFE966D00
+#define MEDIA_AXI_FDP0R_BASE	0xFE964D40
+#define MEDIA_AXI_FDP0W_BASE	0xFE966D40
+#define MEDIA_AXI_IMSR_BASE	0xFE964D80
+#define MEDIA_AXI_IMSW_BASE	0xFE966D80
+#define MEDIA_AXI_VSP1R_BASE	0xFE965100
+#define MEDIA_AXI_VSP1W_BASE	0xFE967100
+#define MEDIA_AXI_FDP1R_BASE	0xFE965140
+#define MEDIA_AXI_FDP1W_BASE	0xFE967140
+#define MEDIA_AXI_IMRR_BASE	0xFE965180
+#define MEDIA_AXI_IMRW_BASE	0xFE967180
+#define MEDIA_AXI_FDP2R_BASE	0xFE9651C0
+#define MEDIA_AXI_FDP2W_BASE	0xFE966DC0
+#define MEDIA_AXI_VSPD0R_BASE	0xFE965500
+#define MEDIA_AXI_VSPD0W_BASE	0xFE967500
+#define MEDIA_AXI_VSPD1R_BASE	0xFE965540
+#define MEDIA_AXI_VSPD1W_BASE	0xFE967540
+#define MEDIA_AXI_DU0R_BASE	0xFE965580
+#define MEDIA_AXI_DU0W_BASE	0xFE967580
+#define MEDIA_AXI_DU1R_BASE	0xFE9655C0
+#define MEDIA_AXI_DU1W_BASE	0xFE9675C0
+#define MEDIA_AXI_VCP0CR_BASE	0xFE965900
+#define MEDIA_AXI_VCP0CW_BASE	0xFE967900
+#define MEDIA_AXI_VCP0VR_BASE	0xFE965940
+#define MEDIA_AXI_VCP0VW_BASE	0xFE967940
+#define MEDIA_AXI_VPC0R_BASE	0xFE965980
+#define MEDIA_AXI_VCP1CR_BASE	0xFE965D00
+#define MEDIA_AXI_VCP1CW_BASE	0xFE967D00
+#define MEDIA_AXI_VCP1VR_BASE	0xFE965D40
+#define MEDIA_AXI_VCP1VW_BASE	0xFE967D40
+#define MEDIA_AXI_VPC1R_BASE	0xFE965D80
+
+#define SYS_AXI_AVBDMSCR	0xFF802000
+#define SYS_AXI_SYX2DMSCR	0xFF802004
+#define SYS_AXI_CC50DMSCR	0xFF802008
+#define SYS_AXI_CC51DMSCR	0xFF80200C
+#define SYS_AXI_CCIDMSCR	0xFF802010
+#define SYS_AXI_CSDMSCR		0xFF802014
+#define SYS_AXI_DDMDMSCR	0xFF802018
+#define SYS_AXI_ETHDMSCR	0xFF80201C
+#define SYS_AXI_G2DDMSCR	0xFF802020
+#define SYS_AXI_IMP0DMSCR	0xFF802024
+#define SYS_AXI_IMP1DMSCR	0xFF802028
+#define SYS_AXI_LBSDMSCR	0xFF80202C
+#define SYS_AXI_MMUDSDMSCR	0xFF802030
+#define SYS_AXI_MMUMXDMSCR	0xFF802034
+#define SYS_AXI_MMURDDMSCR	0xFF802038
+#define SYS_AXI_MMUS0DMSCR	0xFF80203C
+#define SYS_AXI_MMUS1DMSCR	0xFF802040
+#define SYS_AXI_MPXDMSCR	0xFF802044
+#define SYS_AXI_MTSB0DMSCR	0xFF802048
+#define SYS_AXI_MTSB1DMSCR	0xFF80204C
+#define SYS_AXI_PCIDMSCR	0xFF802050
+#define SYS_AXI_RTXDMSCR	0xFF802054
+#define SYS_AXI_SAT0DMSCR	0xFF802058
+#define SYS_AXI_SAT1DMSCR	0xFF80205C
+#define SYS_AXI_SDM0DMSCR	0xFF802060
+#define SYS_AXI_SDM1DMSCR	0xFF802064
+#define SYS_AXI_SDS0DMSCR	0xFF802068
+#define SYS_AXI_SDS1DMSCR	0xFF80206C
+#define SYS_AXI_ETRABDMSCR	0xFF802070
+#define SYS_AXI_ETRKFDMSCR	0xFF802074
+#define SYS_AXI_UDM0DMSCR	0xFF802078
+#define SYS_AXI_UDM1DMSCR	0xFF80207C
+#define SYS_AXI_USB20DMSCR	0xFF802080
+#define SYS_AXI_USB21DMSCR	0xFF802084
+#define SYS_AXI_USB22DMSCR	0xFF802088
+#define SYS_AXI_USB30DMSCR	0xFF80208C
+#define SYS_AXI_X128TO64SLVDMSCR	0xFF802100
+#define SYS_AXI_X64TO128SLVDMSCR	0xFF802104
+#define SYS_AXI_AVBSLVDMSCR	0xFF802108
+#define SYS_AXI_SYX2SLVDMSCR	0xFF80210C
+#define SYS_AXI_ETHSLVDMSCR	0xFF802110
+#define SYS_AXI_GICSLVDMSCR	0xFF802114
+#define SYS_AXI_IMPSLVDMSCR	0xFF802118
+#define SYS_AXI_IMX0SLVDMSCR	0xFF80211C
+#define SYS_AXI_IMX1SLVDMSCR	0xFF802120
+#define SYS_AXI_IMX2SLVDMSCR	0xFF802124
+#define SYS_AXI_LBSSLVDMSCR	0xFF802128
+#define SYS_AXI_MMC0SLVDMSCR	0xFF80212C
+#define SYS_AXI_MMC1SLVDMSCR	0xFF802130
+#define SYS_AXI_MPXSLVDMSCR	0xFF802134
+#define SYS_AXI_MTSB0SLVDMSCR	0xFF802138
+#define SYS_AXI_MTSB1SLVDMSCR	0xFF80213C
+#define SYS_AXI_MXTSLVDMSCR	0xFF802140
+#define SYS_AXI_PCISLVDMSCR	0xFF802144
+#define SYS_AXI_SYAPBSLVDMSCR	0xFF802148
+#define SYS_AXI_QSAPBSLVDMSCR	0xFF80214C
+#define SYS_AXI_RTXSLVDMSCR	0xFF802150
+#define SYS_AXI_SAT0SLVDMSCR	0xFF802168
+#define SYS_AXI_SAT1SLVDMSCR	0xFF80216C
+#define SYS_AXI_SDAP0SLVDMSCR	0xFF802170
+#define SYS_AXI_SDAP1SLVDMSCR	0xFF802174
+#define SYS_AXI_SDAP2SLVDMSCR	0xFF802178
+#define SYS_AXI_SDAP3SLVDMSCR	0xFF80217C
+#define SYS_AXI_SGXSLVDMSCR	0xFF802180
+#define SYS_AXI_STBSLVDMSCR	0xFF802188
+#define SYS_AXI_STMSLVDMSCR	0xFF80218C
+#define SYS_AXI_TSPL0SLVDMSCR	0xFF802194
+#define SYS_AXI_TSPL1SLVDMSCR	0xFF802198
+#define SYS_AXI_TSPL2SLVDMSCR	0xFF80219C
+#define SYS_AXI_USB20SLVDMSCR	0xFF8021A0
+#define SYS_AXI_USB21SLVDMSCR	0xFF8021A4
+#define SYS_AXI_USB22SLVDMSCR	0xFF8021A8
+#define SYS_AXI_USB30SLVDMSCR	0xFF8021AC
+
+#define RT_AXI_CBMDMSCR		0xFF812000
+#define RT_AXI_DBDMSCR		0xFF812004
+#define RT_AXI_RDMDMSCR		0xFF812008
+#define RT_AXI_RDSDMSCR		0xFF81200C
+#define RT_AXI_STRDMSCR		0xFF812010
+#define RT_AXI_SY2RTDMSCR	0xFF812014
+#define RT_AXI_CBSSLVDMSCR	0xFF812100
+#define RT_AXI_DBSSLVDMSCR	0xFF812104
+#define RT_AXI_RTAP1SLVDMSCR	0xFF812108
+#define RT_AXI_RTAP2SLVDMSCR	0xFF81210C
+#define RT_AXI_RTAP3SLVDMSCR	0xFF812110
+#define RT_AXI_RT2SYSLVDMSCR	0xFF812114
+#define RT_AXI_A128TO64SLVDMSCR	0xFF812118
+#define RT_AXI_A64TO128SLVDMSCR	0xFF81211C
+#define RT_AXI_A64TO128CSLVDMSCR	0xFF812120
+#define RT_AXI_UTLBRSLVDMSCR	0xFF812128
+
+#define MP_AXI_ADSPDMSCR	0xFF822000
+#define MP_AXI_ASDM0DMSCR	0xFF822004
+#define MP_AXI_ASDM1DMSCR	0xFF822008
+#define MP_AXI_ASDS0DMSCR	0xFF82200C
+#define MP_AXI_ASDS1DMSCR	0xFF822010
+#define MP_AXI_MLPDMSCR		0xFF822014
+#define MP_AXI_MMUMPDMSCR	0xFF822018
+#define MP_AXI_SPUDMSCR		0xFF82201C
+#define MP_AXI_SPUCDMSCR	0xFF822020
+#define MP_AXI_SY2MPDMSCR	0xFF822024
+#define MP_AXI_ADSPSLVDMSCR	0xFF822100
+#define MP_AXI_MLMSLVDMSCR	0xFF822104
+#define MP_AXI_MPAP4SLVDMSCR	0xFF822108
+#define MP_AXI_MPAP5SLVDMSCR	0xFF82210C
+#define MP_AXI_MPAP6SLVDMSCR	0xFF822110
+#define MP_AXI_MPAP7SLVDMSCR	0xFF822114
+#define MP_AXI_MP2SYSLVDMSCR	0xFF822118
+#define MP_AXI_MP2SY2SLVDMSCR	0xFF82211C
+#define MP_AXI_MPXAPSLVDMSCR	0xFF822124
+#define MP_AXI_SPUSLVDMSCR	0xFF822128
+#define MP_AXI_UTLBMPSLVDMSCR	0xFF82212C
+
+#define ADM_AXI_ASDM0DMSCR	0xFF842000
+#define ADM_AXI_ASDM1DMSCR	0xFF842004
+#define ADM_AXI_MPAP1SLVDMSCR	0xFF842104
+#define ADM_AXI_MPAP2SLVDMSCR	0xFF842108
+#define ADM_AXI_MPAP3SLVDMSCR	0xFF84210C
+
+#define DM_AXI_RDMDMSCR		0xFF852000
+#define DM_AXI_SDM0DMSCR	0xFF852004
+#define DM_AXI_SDM1DMSCR	0xFF852008
+#define DM_AXI_MMAP0SLVDMSCR	0xFF852100
+#define DM_AXI_MMAP1SLVDMSCR	0xFF852104
+#define DM_AXI_QSPAPSLVDMSCR	0xFF852108
+#define DM_AXI_RAP4SLVDMSCR	0xFF85210C
+#define DM_AXI_RAP5SLVDMSCR	0xFF852110
+#define DM_AXI_SAP4SLVDMSCR	0xFF852114
+#define DM_AXI_SAP5SLVDMSCR	0xFF852118
+#define DM_AXI_SAP6SLVDMSCR	0xFF85211C
+#define DM_AXI_SAP65SLVDMSCR	0xFF852120
+#define DM_AXI_SDAP0SLVDMSCR	0xFF852124
+#define DM_AXI_SDAP1SLVDMSCR	0xFF852128
+#define DM_AXI_SDAP2SLVDMSCR	0xFF85212C
+#define DM_AXI_SDAP3SLVDMSCR	0xFF852130
+
+#define SYS_AXI256_SYXDMSCR	0xFF862000
+#define SYS_AXI256_MPXDMSCR	0xFF862004
+#define SYS_AXI256_MXIDMSCR	0xFF862008
+#define SYS_AXI256_X128TO256SLVDMSCR	0xFF862100
+#define SYS_AXI256_X256TO128SLVDMSCR	0xFF862104
+#define SYS_AXI256_SYXSLVDMSCR	0xFF862108
+#define SYS_AXI256_CCXSLVDMSCR	0xFF86210C
+#define SYS_AXI256_S3CSLVDMSCR	0xFF862110
+
+#define MXT_SYXDMSCR		0xFF872000
+#define MXT_CMM0SLVDMSCR	0xFF872100
+#define MXT_CMM1SLVDMSCR	0xFF872104
+#define MXT_CMM2SLVDMSCR	0xFF872108
+#define MXT_FDPSLVDMSCR		0xFF87210C
+#define MXT_IMRSLVDMSCR		0xFF872110
+#define MXT_VINSLVDMSCR		0xFF872114
+#define MXT_VPC0SLVDMSCR	0xFF872118
+#define MXT_VPC1SLVDMSCR	0xFF87211C
+#define MXT_VSP0SLVDMSCR	0xFF872120
+#define MXT_VSP1SLVDMSCR	0xFF872124
+#define MXT_VSPD0SLVDMSCR	0xFF872128
+#define MXT_VSPD1SLVDMSCR	0xFF87212C
+#define MXT_MAP1SLVDMSCR	0xFF872130
+#define MXT_MAP2SLVDMSCR	0xFF872134
+
+#define CCI_AXI_MMUS0DMSCR	0xFF882000
+#define CCI_AXI_SYX2DMSCR	0xFF882004
+#define CCI_AXI_MMURDMSCR	0xFF882008
+#define CCI_AXI_MMUDSDMSCR	0xFF88200C
+#define CCI_AXI_MMUMDMSCR	0xFF882010
+#define CCI_AXI_MXIDMSCR	0xFF882014
+#define CCI_AXI_MMUS1DMSCR	0xFF882018
+#define CCI_AXI_MMUMPDMSCR	0xFF88201C
+#define CCI_AXI_DVMDMSCR	0xFF882020
+#define CCI_AXI_CCISLVDMSCR	0xFF882100
+
+#define CCI_AXI_IPMMUIDVMCR	0xFF880400
+#define CCI_AXI_IPMMURDVMCR	0xFF880404
+#define CCI_AXI_IPMMUS0DVMCR	0xFF880408
+#define CCI_AXI_IPMMUS1DVMCR	0xFF88040C
+#define CCI_AXI_IPMMUMPDVMCR	0xFF880410
+#define CCI_AXI_IPMMUDSDVMCR	0xFF880414
+#define CCI_AXI_AX2ADDRMASK	0xFF88041C
+
+#ifndef __ASSEMBLY__
+#include <asm/types.h>
+
+/* RWDT */
+struct r8a7791_rwdt {
+	u32 rwtcnt;	/* 0x00 */
+	u32 rwtcsra;	/* 0x04 */
+	u16 rwtcsrb;	/* 0x08 */
+};
+
+/* SWDT */
+struct r8a7791_swdt {
+	u32 swtcnt;	/* 0x00 */
+	u32 swtcsra;	/* 0x04 */
+	u16 swtcsrb;	/* 0x08 */
+};
+
+/* LBSC */
+struct r8a7791_lbsc {
+	u32 cs0ctrl;
+	u32 cs1ctrl;
+	u32 ecs0ctrl;
+	u32 ecs1ctrl;
+	u32 ecs2ctrl;
+	u32 ecs3ctrl;
+	u32 ecs4ctrl;
+	u32 ecs5ctrl;
+	u32 dummy0[4];	/* 0x20 .. 0x2C */
+	u32 cswcr0;
+	u32 cswcr1;
+	u32 ecswcr0;
+	u32 ecswcr1;
+	u32 ecswcr2;
+	u32 ecswcr3;
+	u32 ecswcr4;
+	u32 ecswcr5;
+	u32 exdmawcr0;
+	u32 exdmawcr1;
+	u32 exdmawcr2;
+	u32 dummy1[9];	/* 0x5C .. 0x7C */
+	u32 cspwcr0;
+	u32 cspwcr1;
+	u32 ecspwcr0;
+	u32 ecspwcr1;
+	u32 ecspwcr2;
+	u32 ecspwcr3;
+	u32 ecspwcr4;
+	u32 ecspwcr5;
+	u32 exwtsync;
+	u32 dummy2[3];	/* 0xA4 .. 0xAC */
+	u32 cs0bstctl;
+	u32 cs0btph;
+	u32 dummy3[2];	/* 0xB8 .. 0xBC */
+	u32 cs1gdst;
+	u32 ecs0gdst;
+	u32 ecs1gdst;
+	u32 ecs2gdst;
+	u32 ecs3gdst;
+	u32 ecs4gdst;
+	u32 ecs5gdst;
+	u32 dummy4[5];	/* 0xDC .. 0xEC */
+	u32 exdmaset0;
+	u32 exdmaset1;
+	u32 exdmaset2;
+	u32 dummy5[5];	/* 0xFC .. 0x10C */
+	u32 exdmcr0;
+	u32 exdmcr1;
+	u32 exdmcr2;
+	u32 dummy6[5];	/* 0x11C .. 0x12C */
+	u32 bcintsr;
+	u32 bcintcr;
+	u32 bcintmr;
+	u32 dummy7;	/* 0x13C */
+	u32 exbatlv;
+	u32 exwtsts;
+	u32 dummy8[14];	/* 0x148 .. 0x17C */
+	u32 atacsctrl;
+	u32 dummy9[15]; /* 0x184 .. 0x1BC */
+	u32 exbct;
+	u32 extct;
+};
+
+/* DBSC3 */
+struct r8a7791_dbsc3 {
+	u32 dummy0[3];	/* 0x00 .. 0x08 */
+	u32 dbstate1;
+	u32 dbacen;
+	u32 dbrfen;
+	u32 dbcmd;
+	u32 dbwait;
+	u32 dbkind;
+	u32 dbconf0;
+	u32 dummy1[2];	/* 0x28 .. 0x2C */
+	u32 dbphytype;
+	u32 dummy2[3];	/* 0x34 .. 0x3C */
+	u32 dbtr0;
+	u32 dbtr1;
+	u32 dbtr2;
+	u32 dummy3;	/* 0x4C */
+	u32 dbtr3;
+	u32 dbtr4;
+	u32 dbtr5;
+	u32 dbtr6;
+	u32 dbtr7;
+	u32 dbtr8;
+	u32 dbtr9;
+	u32 dbtr10;
+	u32 dbtr11;
+	u32 dbtr12;
+	u32 dbtr13;
+	u32 dbtr14;
+	u32 dbtr15;
+	u32 dbtr16;
+	u32 dbtr17;
+	u32 dbtr18;
+	u32 dbtr19;
+	u32 dummy4[7];	/* 0x94 .. 0xAC */
+	u32 dbbl;
+	u32 dummy5[3];	/* 0xB4 .. 0xBC */
+	u32 dbadj0;
+	u32 dummy6;	/* 0xC4 */
+	u32 dbadj2;
+	u32 dummy7[5];	/* 0xCC .. 0xDC */
+	u32 dbrfcnf0;
+	u32 dbrfcnf1;
+	u32 dbrfcnf2;
+	u32 dummy8[2];	/* 0xEC .. 0xF0 */
+	u32 dbcalcnf;
+	u32 dbcaltr;
+	u32 dummy9;	/* 0xFC */
+	u32 dbrnk0;
+	u32 dummy10[31];	/* 0x104 .. 0x17C */
+	u32 dbpdncnf;
+	u32 dummy11[47];	/* 0x184 ..0x23C */
+	u32 dbdfistat;
+	u32 dbdficnt;
+	u32 dummy12[14];	/* 0x248 .. 0x27C */
+	u32 dbpdlck;
+	u32 dummy13[3];	/* 0x284 .. 0x28C */
+	u32 dbpdrga;
+	u32 dummy14[3];	/* 0x294 .. 0x29C */
+	u32 dbpdrgd;
+	u32 dummy15[24];	/* 0x2A4 .. 0x300 */
+	u32 dbbs0cnt1;
+	u32 dummy16[30];	/* 0x308 .. 0x37C */
+	u32 dbwt0cnf0;
+	u32 dbwt0cnf1;
+	u32 dbwt0cnf2;
+	u32 dbwt0cnf3;
+	u32 dbwt0cnf4;
+};
+
+/* GPIO */
+struct r8a7791_gpio {
+	u32 iointsel;
+	u32 inoutsel;
+	u32 outdt;
+	u32 indt;
+	u32 intdt;
+	u32 intclr;
+	u32 intmsk;
+	u32 posneg;
+	u32 edglevel;
+	u32 filonoff;
+	u32 intmsks;
+	u32 mskclrs;
+	u32 outdtsel;
+	u32 outdth;
+	u32 outdtl;
+	u32 bothedge;
+};
+
+/* S3C(QoS) */
+struct r8a7791_s3c {
+	u32 s3cexcladdmsk;
+	u32 s3cexclidmsk;
+	u32 s3cadsplcr;
+	u32 s3cmaar;
+	u32 dummy0;	/* 0x10 */
+	u32 s3crorr;
+	u32 s3cworr;
+	u32 s3carcr22;
+	u32 dummy1[2];	/* 0x20 .. 0x24 */
+	u32 s3cmctr;
+	u32 dummy2;	/* 0x2C */
+	u32 cconf0;
+	u32 cconf1;
+	u32 cconf2;
+	u32 cconf3;
+};
+
+struct r8a7791_s3c_qos {
+	u32 s3cqos0;
+	u32 s3cqos1;
+	u32 s3cqos2;
+	u32 s3cqos3;
+	u32 s3cqos4;
+	u32 s3cqos5;
+	u32 s3cqos6;
+	u32 s3cqos7;
+	u32 s3cqos8;
+};
+
+/* DBSC(QoS) */
+struct r8a7791_dbsc3_qos {
+	u32 dblgcnt;
+	u32 dbtmval0;
+	u32 dbtmval1;
+	u32 dbtmval2;
+	u32 dbtmval3;
+	u32 dbrqctr;
+	u32 dbthres0;
+	u32 dbthres1;
+	u32 dbthres2;
+	u32 dummy0;	/* 0x24 */
+	u32 dblgqon;
+};
+
+/* MXI(QoS) */
+struct r8a7791_mxi {
+	u32 mxsaar0;
+	u32 mxsaar1;
+	u32 dummy0[8];	/* 0x08 .. 0x24 */
+	u32 mxs3cracr;
+	u32 dummy1[3];	/* 0x2C .. 0x34 */
+	u32 mxs3cwacr;
+	u32 dummy2;	/* 0x3C */
+	u32 mxrtcr;
+	u32 mxwtcr;
+};
+
+struct r8a7791_mxi_qos {
+	u32 vspdu0;
+	u32 vspdu1;
+	u32 du0;
+	u32 du1;
+};
+
+/* AXI(QoS) */
+struct r8a7791_axi_qos {
+	u32 qosconf;
+	u32 qosctset0;
+	u32 qosctset1;
+	u32 qosctset2;
+	u32 qosctset3;
+	u32 qosreqctr;
+	u32 qosthres0;
+	u32 qosthres1;
+	u32 qosthres2;
+	u32 qosqon;
+};
+
+#endif
+
+#endif /* __ASM_ARCH_R8A7791_H */
diff --git a/arch/arm/include/asm/arch-rmobile/rmobile.h b/arch/arm/include/asm/arch-rmobile/rmobile.h
index ac175617cd..2382565023 100644
--- a/arch/arm/include/asm/arch-rmobile/rmobile.h
+++ b/arch/arm/include/asm/arch-rmobile/rmobile.h
@@ -6,6 +6,10 @@
 #include <asm/arch/sh73a0.h>
 #elif defined(CONFIG_R8A7740)
 #include <asm/arch/r8a7740.h>
+#elif defined(CONFIG_R8A7790)
+#include <asm/arch/r8a7790.h>
+#elif defined(CONFIG_R8A7791)
+#include <asm/arch/r8a7791.h>
 #else
 #error "SOC Name not defined"
 #endif
diff --git a/arch/arm/include/asm/arch-s3c24x0/memory.h b/arch/arm/include/asm/arch-s3c24x0/memory.h
index 61d62707c7..d6a787b663 100644
--- a/arch/arm/include/asm/arch-s3c24x0/memory.h
+++ b/arch/arm/include/asm/arch-s3c24x0/memory.h
@@ -32,9 +32,6 @@
  */
 #define PHYS_OFFSET	(0x0c000000UL)
 
-#include <linux/config.h>
-
-
 /* Modified for S3C2400, by chc, 20010509 */
 #define RAM_IN_BANK_0  32*1024*1024
 #define RAM_IN_BANK_1  0
diff --git a/arch/arm/include/asm/arch-s5pc1xx/cpu.h b/arch/arm/include/asm/arch-s5pc1xx/cpu.h
index 4fc5a0c3c9..5ae5c87169 100644
--- a/arch/arm/include/asm/arch-s5pc1xx/cpu.h
+++ b/arch/arm/include/asm/arch-s5pc1xx/cpu.h
@@ -51,10 +51,17 @@
 #include <asm/io.h>
 /* CPU detection macros */
 extern unsigned int s5p_cpu_id;
+extern unsigned int s5p_cpu_rev;
+
+static inline int s5p_get_cpu_rev(void)
+{
+	return s5p_cpu_rev;
+}
 
 static inline void s5p_set_cpu_id(void)
 {
 	s5p_cpu_id = readl(S5PC100_PRO_ID);
+	s5p_cpu_rev = s5p_cpu_id & 0x000000FF;
 	s5p_cpu_id = 0xC000 | ((s5p_cpu_id & 0x00FFF000) >> 12);
 }
 
diff --git a/arch/arm/include/asm/arch-s5pc1xx/gpio.h b/arch/arm/include/asm/arch-s5pc1xx/gpio.h
index ac60fe6386..da8df74a10 100644
--- a/arch/arm/include/asm/arch-s5pc1xx/gpio.h
+++ b/arch/arm/include/asm/arch-s5pc1xx/gpio.h
@@ -125,20 +125,45 @@ void s5p_gpio_set_rate(struct s5p_gpio_bank *bank, int gpio, int mode);
 /* GPIO pins per bank  */
 #define GPIO_PER_BANK 8
 
-static inline unsigned int s5p_gpio_base(int nr)
-{
-	return S5PC110_GPIO_BASE;
-}
+#define S5P_GPIO_PART_SHIFT	(24)
+#define S5P_GPIO_PART_MASK	(0xff)
+#define S5P_GPIO_BANK_SHIFT	(8)
+#define S5P_GPIO_BANK_MASK	(0xffff)
+#define S5P_GPIO_PIN_MASK	(0xff)
+
+#define S5P_GPIO_SET_PART(x) \
+			(((x) & S5P_GPIO_PART_MASK) << S5P_GPIO_PART_SHIFT)
+
+#define S5P_GPIO_GET_PART(x) \
+			(((x) >> S5P_GPIO_PART_SHIFT) & S5P_GPIO_PART_MASK)
+
+#define S5P_GPIO_SET_PIN(x) \
+			((x) & S5P_GPIO_PIN_MASK)
 
-static inline unsigned int s5p_gpio_part_max(int nr)
+#define S5PC100_SET_BANK(bank) \
+			(((unsigned)&(((struct s5pc100_gpio *) \
+			S5PC100_GPIO_BASE)->bank) - S5PC100_GPIO_BASE) \
+			& S5P_GPIO_BANK_MASK) << S5P_GPIO_BANK_SHIFT)
+
+#define S5PC110_SET_BANK(bank) \
+			((((unsigned)&(((struct s5pc110_gpio *) \
+			S5PC110_GPIO_BASE)->bank) - S5PC110_GPIO_BASE) \
+			& S5P_GPIO_BANK_MASK) << S5P_GPIO_BANK_SHIFT)
+
+#define s5pc100_gpio_get(bank, pin) \
+			(S5P_GPIO_SET_PART(0) | \
+			S5PC100_SET_BANK(bank) | \
+			S5P_GPIO_SET_PIN(pin))
+
+#define s5pc110_gpio_get(bank, pin) \
+			(S5P_GPIO_SET_PART(0) | \
+			S5PC110_SET_BANK(bank) | \
+			S5P_GPIO_SET_PIN(pin))
+
+static inline unsigned int s5p_gpio_base(int nr)
 {
-	return 0;
+	return samsung_get_base_gpio();
 }
-
-#define s5pc110_gpio_get_nr(bank, pin)	  \
-	((((((unsigned int)&(((struct s5pc110_gpio *)S5PC110_GPIO_BASE)->bank))\
-	    - S5PC110_GPIO_BASE) / sizeof(struct s5p_gpio_bank)) \
-	  * GPIO_PER_BANK) + pin)
 #endif
 
 /* Pin configurations */
diff --git a/arch/arm/include/asm/arch-s5pc1xx/mmc.h b/arch/arm/include/asm/arch-s5pc1xx/mmc.h
index 55ff10b23c..dd473c8ecd 100644
--- a/arch/arm/include/asm/arch-s5pc1xx/mmc.h
+++ b/arch/arm/include/asm/arch-s5pc1xx/mmc.h
@@ -55,7 +55,7 @@
 
 int s5p_sdhci_init(u32 regbase, int index, int bus_width);
 
-static inline unsigned int s5p_mmc_init(int index, int bus_width)
+static inline int s5p_mmc_init(int index, int bus_width)
 {
 	unsigned int base = samsung_get_base_mmc() +
 				 (S5P_MMC_DEV_OFFSET * index);
diff --git a/arch/arm/include/asm/arch-socfpga/clock_manager.h b/arch/arm/include/asm/arch-socfpga/clock_manager.h
new file mode 100644
index 0000000000..966add3e91
--- /dev/null
+++ b/arch/arm/include/asm/arch-socfpga/clock_manager.h
@@ -0,0 +1,205 @@
+/*
+ *  Copyright (C) 2013 Altera Corporation <www.altera.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef	_CLOCK_MANAGER_H_
+#define	_CLOCK_MANAGER_H_
+
+typedef struct {
+	/* main group */
+	uint32_t main_vco_base;
+	uint32_t mpuclk;
+	uint32_t mainclk;
+	uint32_t dbgatclk;
+	uint32_t mainqspiclk;
+	uint32_t mainnandsdmmcclk;
+	uint32_t cfg2fuser0clk;
+	uint32_t maindiv;
+	uint32_t dbgdiv;
+	uint32_t tracediv;
+	uint32_t l4src;
+
+	/* peripheral group */
+	uint32_t peri_vco_base;
+	uint32_t emac0clk;
+	uint32_t emac1clk;
+	uint32_t perqspiclk;
+	uint32_t pernandsdmmcclk;
+	uint32_t perbaseclk;
+	uint32_t s2fuser1clk;
+	uint32_t perdiv;
+	uint32_t gpiodiv;
+	uint32_t persrc;
+
+	/* sdram pll group */
+	uint32_t sdram_vco_base;
+	uint32_t ddrdqsclk;
+	uint32_t ddr2xdqsclk;
+	uint32_t ddrdqclk;
+	uint32_t s2fuser2clk;
+} cm_config_t;
+
+extern void cm_basic_init(const cm_config_t *cfg);
+
+struct socfpga_clock_manager {
+	u32	ctrl;
+	u32	bypass;
+	u32	inter;
+	u32	intren;
+	u32	dbctrl;
+	u32	stat;
+	u32	_pad_0x18_0x3f[10];
+	u32	mainpllgrp;
+	u32	perpllgrp;
+	u32	sdrpllgrp;
+	u32	_pad_0xe0_0x200[72];
+
+	u32	main_pll_vco;
+	u32	main_pll_misc;
+	u32	main_pll_mpuclk;
+	u32	main_pll_mainclk;
+	u32	main_pll_dbgatclk;
+	u32	main_pll_mainqspiclk;
+	u32	main_pll_mainnandsdmmcclk;
+	u32	main_pll_cfgs2fuser0clk;
+	u32	main_pll_en;
+	u32	main_pll_maindiv;
+	u32	main_pll_dbgdiv;
+	u32	main_pll_tracediv;
+	u32	main_pll_l4src;
+	u32	main_pll_stat;
+	u32	main_pll__pad_0x38_0x40[2];
+
+	u32	per_pll_vco;
+	u32	per_pll_misc;
+	u32	per_pll_emac0clk;
+	u32	per_pll_emac1clk;
+	u32	per_pll_perqspiclk;
+	u32	per_pll_pernandsdmmcclk;
+	u32	per_pll_perbaseclk;
+	u32	per_pll_s2fuser1clk;
+	u32	per_pll_en;
+	u32	per_pll_div;
+	u32	per_pll_gpiodiv;
+	u32	per_pll_src;
+	u32	per_pll_stat;
+	u32	per_pll__pad_0x34_0x40[3];
+
+	u32	sdr_pll_vco;
+	u32	sdr_pll_ctrl;
+	u32	sdr_pll_ddrdqsclk;
+	u32	sdr_pll_ddr2xdqsclk;
+	u32	sdr_pll_ddrdqclk;
+	u32	sdr_pll_s2fuser2clk;
+	u32	sdr_pll_en;
+	u32	sdr_pll_stat;
+};
+
+#define CLKMGR_MAINPLLGRP_EN_S2FUSER0CLK_MASK 0x00000200
+#define CLKMGR_MAINPLLGRP_EN_DBGTIMERCLK_MASK 0x00000080
+#define CLKMGR_MAINPLLGRP_EN_DBGTRACECLK_MASK 0x00000040
+#define CLKMGR_MAINPLLGRP_EN_DBGCLK_MASK 0x00000020
+#define CLKMGR_MAINPLLGRP_EN_DBGATCLK_MASK 0x00000010
+#define CLKMGR_MAINPLLGRP_EN_L4MPCLK_MASK 0x00000004
+#define CLKMGR_MAINPLLGRP_VCO_RESET_VALUE 0x8001000d
+#define CLKMGR_PERPLLGRP_VCO_RESET_VALUE 0x8001000d
+#define CLKMGR_SDRPLLGRP_VCO_RESET_VALUE 0x8001000d
+#define CLKMGR_MAINPLLGRP_MAINDIV_L4MPCLK_SET(x) (((x) << 4) & 0x00000070)
+#define CLKMGR_MAINPLLGRP_MAINDIV_L4SPCLK_SET(x)  (((x) << 7) & 0x00000380)
+#define CLKMGR_MAINPLLGRP_L4SRC_L4MP_SET(x) (((x) << 0) & 0x00000001)
+#define CLKMGR_MAINPLLGRP_L4SRC_L4SP_SET(x) (((x) << 1) & 0x00000002)
+#define CLKMGR_PERPLLGRP_SRC_QSPI_SET(x) (((x) << 4) & 0x00000030)
+#define CLKMGR_PERPLLGRP_SRC_NAND_SET(x) (((x) << 2) & 0x0000000c)
+#define CLKMGR_PERPLLGRP_SRC_SDMMC_SET(x) (((x) << 0) & 0x00000003)
+#define CLKMGR_MAINPLLGRP_VCO_DENOM_SET(x) (((x) << 16) & 0x003f0000)
+#define CLKMGR_MAINPLLGRP_VCO_NUMER_SET(x) (((x) << 3) & 0x0000fff8)
+#define CLKMGR_MAINPLLGRP_VCO_PWRDN_SET(x) (((x) << 2) & 0x00000004)
+#define CLKMGR_MAINPLLGRP_VCO_EN_SET(x) (((x) << 1) & 0x00000002)
+#define CLKMGR_MAINPLLGRP_VCO_BGPWRDN_SET(x) (((x) << 0) & 0x00000001)
+#define CLKMGR_PERPLLGRP_VCO_PSRC_SET(x) (((x) << 22) & 0x00c00000)
+#define CLKMGR_PERPLLGRP_VCO_DENOM_SET(x) (((x) << 16) & 0x003f0000)
+#define CLKMGR_PERPLLGRP_VCO_NUMER_SET(x) (((x) << 3) & 0x0000fff8)
+#define CLKMGR_SDRPLLGRP_VCO_OUTRESET_SET(x) (((x) << 25) & 0x7e000000)
+#define CLKMGR_SDRPLLGRP_VCO_OUTRESETALL_SET(x) (((x) << 24) & 0x01000000)
+#define CLKMGR_SDRPLLGRP_VCO_SSRC_SET(x) (((x) << 22) & 0x00c00000)
+#define CLKMGR_SDRPLLGRP_VCO_DENOM_SET(x) (((x) << 16) & 0x003f0000)
+#define CLKMGR_SDRPLLGRP_VCO_NUMER_SET(x) (((x) << 3) & 0x0000fff8)
+#define CLKMGR_MAINPLLGRP_MPUCLK_CNT_SET(x) (((x) << 0) & 0x000001ff)
+#define CLKMGR_MAINPLLGRP_MAINCLK_CNT_SET(x) (((x) << 0) & 0x000001ff)
+#define CLKMGR_MAINPLLGRP_DBGATCLK_CNT_SET(x) (((x) << 0) & 0x000001ff)
+#define CLKMGR_MAINPLLGRP_CFGS2FUSER0CLK_CNT_SET(x) \
+	(((x) << 0) & 0x000001ff)
+#define CLKMGR_PERPLLGRP_EMAC0CLK_CNT_SET(x) (((x) << 0) & 0x000001ff)
+#define CLKMGR_PERPLLGRP_EMAC1CLK_CNT_SET(x) (((x) << 0) & 0x000001ff)
+#define CLKMGR_MAINPLLGRP_MAINQSPICLK_CNT_SET(x) (((x) << 0) & 0x000001ff)
+#define CLKMGR_MAINPLLGRP_MAINNANDSDMMCCLK_CNT_SET(x) \
+	(((x) << 0) & 0x000001ff)
+#define CLKMGR_PERPLLGRP_PERBASECLK_CNT_SET(x) (((x) << 0) & 0x000001ff)
+#define CLKMGR_PERPLLGRP_S2FUSER1CLK_CNT_SET(x) (((x) << 0) & 0x000001ff)
+#define CLKMGR_PERPLLGRP_PERNANDSDMMCCLK_CNT_SET(x) (((x) << 0) & 0x000001ff)
+#define CLKMGR_SDRPLLGRP_DDRDQSCLK_PHASE_SET(x) (((x) << 9) & 0x00000e00)
+#define CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_SET(x) (((x) << 0) & 0x000001ff)
+#define CLKMGR_SDRPLLGRP_DDR2XDQSCLK_PHASE_SET(x) (((x) << 9) & 0x00000e00)
+#define CLKMGR_SDRPLLGRP_DDR2XDQSCLK_CNT_SET(x) (((x) << 0) & 0x000001ff)
+#define CLKMGR_SDRPLLGRP_DDRDQCLK_PHASE_SET(x) (((x) << 9) & 0x00000e00)
+#define CLKMGR_SDRPLLGRP_DDRDQCLK_CNT_SET(x) (((x) << 0) & 0x000001ff)
+#define CLKMGR_SDRPLLGRP_S2FUSER2CLK_PHASE_SET(x) (((x) << 9) & 0x00000e00)
+#define CLKMGR_SDRPLLGRP_S2FUSER2CLK_CNT_SET(x) (((x) << 0) & 0x000001ff)
+#define CLKMGR_MAINPLLGRP_DBGDIV_DBGCLK_SET(x) (((x) << 2) & 0x0000000c)
+#define CLKMGR_MAINPLLGRP_DBGDIV_DBGATCLK_SET(x) (((x) << 0) & 0x00000003)
+#define CLKMGR_MAINPLLGRP_TRACEDIV_TRACECLK_SET(x) (((x) << 0) & 0x00000007)
+#define CLKMGR_MAINPLLGRP_MAINDIV_L3MPCLK_SET(x) (((x) << 0) & 0x00000003)
+#define CLKMGR_MAINPLLGRP_MAINDIV_L3SPCLK_SET(x) (((x) << 2) & 0x0000000c)
+#define CLKMGR_BYPASS_PERPLL_SET(x) (((x) << 3) & 0x00000008)
+#define CLKMGR_BYPASS_SDRPLL_SET(x) (((x) << 1) & 0x00000002)
+#define CLKMGR_BYPASS_MAINPLL_SET(x) (((x) << 0) & 0x00000001)
+#define CLKMGR_PERPLLGRP_DIV_USBCLK_SET(x) (((x) << 0) & 0x00000007)
+#define CLKMGR_PERPLLGRP_DIV_SPIMCLK_SET(x) (((x) << 3) & 0x00000038)
+#define CLKMGR_PERPLLGRP_DIV_CAN0CLK_SET(x) (((x) << 6) & 0x000001c0)
+#define CLKMGR_PERPLLGRP_DIV_CAN1CLK_SET(x) (((x) << 9) & 0x00000e00)
+#define CLKMGR_INTER_SDRPLLLOCKED_MASK 0x00000100
+#define CLKMGR_INTER_PERPLLLOCKED_MASK 0x00000080
+#define CLKMGR_INTER_MAINPLLLOCKED_MASK 0x00000040
+#define CLKMGR_CTRL_SAFEMODE_MASK 0x00000001
+#define CLKMGR_CTRL_SAFEMODE_SET(x) (((x) << 0) & 0x00000001)
+#define CLKMGR_SDRPLLGRP_VCO_OUTRESET_MASK 0x7e000000
+#define CLKMGR_SDRPLLGRP_VCO_OUTRESETALL_SET(x) (((x) << 24) & 0x01000000)
+#define CLKMGR_PERPLLGRP_PERQSPICLK_CNT_SET(x) (((x) << 0) & 0x000001ff)
+#define CLKMGR_PERPLLGRP_DIV_SPIMCLK_SET(x) (((x) << 3) & 0x00000038)
+#define CLKMGR_PERPLLGRP_GPIODIV_GPIODBCLK_SET(x) (((x) << 0) & 0x00ffffff)
+#define CLKMGR_BYPASS_PERPLLSRC_SET(x) (((x) << 4) & 0x00000010)
+#define CLKMGR_BYPASS_SDRPLLSRC_SET(x) (((x) << 2) & 0x00000004)
+#define CLKMGR_PERPLLGRP_SRC_RESET_VALUE 0x00000015
+#define CLKMGR_MAINPLLGRP_L4SRC_RESET_VALUE 0x00000000
+#define CLKMGR_MAINPLLGRP_VCO_REGEXTSEL_MASK 0x80000000
+#define CLKMGR_PERPLLGRP_VCO_REGEXTSEL_MASK 0x80000000
+#define CLKMGR_SDRPLLGRP_VCO_REGEXTSEL_MASK 0x80000000
+#define CLKMGR_SDRPLLGRP_DDRDQSCLK_PHASE_MASK 0x001ffe00
+#define CLKMGR_SDRPLLGRP_DDR2XDQSCLK_PHASE_MASK 0x001ffe00
+#define CLKMGR_SDRPLLGRP_DDRDQCLK_PHASE_MASK 0x001ffe00
+#define CLKMGR_SDRPLLGRP_S2FUSER2CLK_PHASE_MASK 0x001ffe00
+#define CLKMGR_MAINPLLGRP_VCO_OUTRESETALL_MASK 0x01000000
+#define CLKMGR_PERPLLGRP_VCO_OUTRESETALL_MASK 0x01000000
+#define CLKMGR_PERPLLGRP_EN_NANDCLK_MASK 0x00000400
+#define CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_MASK 0x000001ff
+#define CLKMGR_SDRPLLGRP_DDR2XDQSCLK_CNT_MASK 0x000001ff
+#define CLKMGR_SDRPLLGRP_DDRDQCLK_CNT_MASK 0x000001ff
+#define CLKMGR_SDRPLLGRP_S2FUSER2CLK_CNT_MASK 0x000001ff
+
+#define MAIN_VCO_BASE \
+	(CLKMGR_MAINPLLGRP_VCO_DENOM_SET(CONFIG_HPS_MAINPLLGRP_VCO_DENOM) | \
+	CLKMGR_MAINPLLGRP_VCO_NUMER_SET(CONFIG_HPS_MAINPLLGRP_VCO_NUMER))
+
+#define PERI_VCO_BASE \
+	(CLKMGR_PERPLLGRP_VCO_PSRC_SET(CONFIG_HPS_PERPLLGRP_VCO_PSRC) | \
+	CLKMGR_PERPLLGRP_VCO_DENOM_SET(CONFIG_HPS_PERPLLGRP_VCO_DENOM) | \
+	CLKMGR_PERPLLGRP_VCO_NUMER_SET(CONFIG_HPS_PERPLLGRP_VCO_NUMER))
+
+#define SDR_VCO_BASE \
+	(CLKMGR_SDRPLLGRP_VCO_SSRC_SET(CONFIG_HPS_SDRPLLGRP_VCO_SSRC) | \
+	CLKMGR_SDRPLLGRP_VCO_DENOM_SET(CONFIG_HPS_SDRPLLGRP_VCO_DENOM) | \
+	CLKMGR_SDRPLLGRP_VCO_NUMER_SET(CONFIG_HPS_SDRPLLGRP_VCO_NUMER))
+
+#endif /* _CLOCK_MANAGER_H_ */
diff --git a/arch/arm/include/asm/arch-socfpga/dwmmc.h b/arch/arm/include/asm/arch-socfpga/dwmmc.h
new file mode 100644
index 0000000000..945eb646ce
--- /dev/null
+++ b/arch/arm/include/asm/arch-socfpga/dwmmc.h
@@ -0,0 +1,12 @@
+/*
+ * (C) Copyright 2013 Altera Corporation <www.altera.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef	_SOCFPGA_DWMMC_H_
+#define	_SOCFPGA_DWMMC_H_
+
+extern int socfpga_dwmmc_init(u32 regbase, int bus_width, int index);
+
+#endif /* _SOCFPGA_SDMMC_H_ */
diff --git a/arch/arm/include/asm/arch-socfpga/freeze_controller.h b/arch/arm/include/asm/arch-socfpga/freeze_controller.h
new file mode 100644
index 0000000000..120f20e038
--- /dev/null
+++ b/arch/arm/include/asm/arch-socfpga/freeze_controller.h
@@ -0,0 +1,50 @@
+/*
+ *  Copyright (C) 2013 Altera Corporation <www.altera.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef	_FREEZE_CONTROLLER_H_
+#define	_FREEZE_CONTROLLER_H_
+
+struct socfpga_freeze_controller {
+	u32	vioctrl;
+	u32	padding[3];
+	u32	hioctrl;
+	u32	src;
+	u32	hwctrl;
+};
+
+#define FREEZE_CHANNEL_NUM		(4)
+
+typedef enum {
+	FREEZE_CTRL_FROZEN = 0,
+	FREEZE_CTRL_THAWED = 1
+} FREEZE_CTRL_CHAN_STATE;
+
+#define SYSMGR_FRZCTRL_ADDRESS 0x40
+#define SYSMGR_FRZCTRL_SRC_VIO1_ENUM_SW 0x0
+#define SYSMGR_FRZCTRL_SRC_VIO1_ENUM_HW 0x1
+#define SYSMGR_FRZCTRL_VIOCTRL_SLEW_MASK 0x00000010
+#define SYSMGR_FRZCTRL_VIOCTRL_WKPULLUP_MASK 0x00000008
+#define SYSMGR_FRZCTRL_VIOCTRL_TRISTATE_MASK 0x00000004
+#define SYSMGR_FRZCTRL_VIOCTRL_BUSHOLD_MASK 0x00000002
+#define SYSMGR_FRZCTRL_VIOCTRL_CFG_MASK 0x00000001
+#define SYSMGR_FRZCTRL_HIOCTRL_SLEW_MASK 0x00000010
+#define SYSMGR_FRZCTRL_HIOCTRL_WKPULLUP_MASK 0x00000008
+#define SYSMGR_FRZCTRL_HIOCTRL_TRISTATE_MASK 0x00000004
+#define SYSMGR_FRZCTRL_HIOCTRL_BUSHOLD_MASK 0x00000002
+#define SYSMGR_FRZCTRL_HIOCTRL_CFG_MASK 0x00000001
+#define SYSMGR_FRZCTRL_HIOCTRL_REGRST_MASK 0x00000080
+#define SYSMGR_FRZCTRL_HIOCTRL_OCTRST_MASK 0x00000040
+#define SYSMGR_FRZCTRL_HIOCTRL_OCT_CFGEN_CALSTART_MASK 0x00000100
+#define SYSMGR_FRZCTRL_HIOCTRL_DLLRST_MASK 0x00000020
+#define SYSMGR_FRZCTRL_HWCTRL_VIO1REQ_MASK 0x00000001
+#define SYSMGR_FRZCTRL_HWCTRL_VIO1STATE_ENUM_FROZEN 0x2
+#define SYSMGR_FRZCTRL_HWCTRL_VIO1STATE_ENUM_THAWED 0x1
+#define SYSMGR_FRZCTRL_VIOCTRL_SHIFT 0x2
+
+void sys_mgr_frzctrl_freeze_req(void);
+void sys_mgr_frzctrl_thaw_req(void);
+
+#endif /* _FREEZE_CONTROLLER_H_ */
diff --git a/arch/arm/include/asm/arch-socfpga/socfpga_base_addrs.h b/arch/arm/include/asm/arch-socfpga/socfpga_base_addrs.h
index 50c4ebd849..f564046bc0 100644
--- a/arch/arm/include/asm/arch-socfpga/socfpga_base_addrs.h
+++ b/arch/arm/include/asm/arch-socfpga/socfpga_base_addrs.h
@@ -11,6 +11,7 @@
 #define SOCFPGA_UART0_ADDRESS 0xffc02000
 #define SOCFPGA_UART1_ADDRESS 0xffc03000
 #define SOCFPGA_OSC1TIMER0_ADDRESS 0xffd00000
+#define SOCFPGA_CLKMGR_ADDRESS 0xffd04000
 #define SOCFPGA_RSTMGR_ADDRESS 0xffd05000
 #define SOCFPGA_SYSMGR_ADDRESS 0xffd08000
 
diff --git a/arch/arm/include/asm/arch-socfpga/system_manager.h b/arch/arm/include/asm/arch-socfpga/system_manager.h
index d965d25eff..838d21053e 100644
--- a/arch/arm/include/asm/arch-socfpga/system_manager.h
+++ b/arch/arm/include/asm/arch-socfpga/system_manager.h
@@ -19,4 +19,69 @@ extern unsigned long sys_mgr_init_table[CONFIG_HPS_PINMUX_NUM];
 
 #define CONFIG_SYSMGR_PINMUXGRP_OFFSET	(0x400)
 
+#define SYSMGR_SDMMC_CTRL_SET(smplsel, drvsel)	\
+	((((drvsel) << 0) & 0x7) | (((smplsel) << 3) & 0x38))
+
+struct socfpga_system_manager {
+	u32	siliconid1;
+	u32	siliconid2;
+	u32	_pad_0x8_0xf[2];
+	u32	wddbg;
+	u32	bootinfo;
+	u32	hpsinfo;
+	u32	parityinj;
+	u32	fpgaintfgrp_gbl;
+	u32	fpgaintfgrp_indiv;
+	u32	fpgaintfgrp_module;
+	u32	_pad_0x2c_0x2f;
+	u32	scanmgrgrp_ctrl;
+	u32	_pad_0x34_0x3f[3];
+	u32	frzctrl_vioctrl;
+	u32	_pad_0x44_0x4f[3];
+	u32	frzctrl_hioctrl;
+	u32	frzctrl_src;
+	u32	frzctrl_hwctrl;
+	u32	_pad_0x5c_0x5f;
+	u32	emacgrp_ctrl;
+	u32	emacgrp_l3master;
+	u32	_pad_0x68_0x6f[2];
+	u32	dmagrp_ctrl;
+	u32	dmagrp_persecurity;
+	u32	_pad_0x78_0x7f[2];
+	u32	iswgrp_handoff[8];
+	u32	_pad_0xa0_0xbf[8];
+	u32	romcodegrp_ctrl;
+	u32	romcodegrp_cpu1startaddr;
+	u32	romcodegrp_initswstate;
+	u32	romcodegrp_initswlastld;
+	u32	romcodegrp_bootromswstate;
+	u32	__pad_0xd4_0xdf[3];
+	u32	romcodegrp_warmramgrp_enable;
+	u32	romcodegrp_warmramgrp_datastart;
+	u32	romcodegrp_warmramgrp_length;
+	u32	romcodegrp_warmramgrp_execution;
+	u32	romcodegrp_warmramgrp_crc;
+	u32	__pad_0xf4_0xff[3];
+	u32	romhwgrp_ctrl;
+	u32	_pad_0x104_0x107;
+	u32	sdmmcgrp_ctrl;
+	u32	sdmmcgrp_l3master;
+	u32	nandgrp_bootstrap;
+	u32	nandgrp_l3master;
+	u32	usbgrp_l3master;
+	u32	_pad_0x11c_0x13f[9];
+	u32	eccgrp_l2;
+	u32	eccgrp_ocram;
+	u32	eccgrp_usb0;
+	u32	eccgrp_usb1;
+	u32	eccgrp_emac0;
+	u32	eccgrp_emac1;
+	u32	eccgrp_dma;
+	u32	eccgrp_can0;
+	u32	eccgrp_can1;
+	u32	eccgrp_nand;
+	u32	eccgrp_qspi;
+	u32	eccgrp_sdmmc;
+};
+
 #endif /* _SYSTEM_MANAGER_H_ */
diff --git a/arch/arm/include/asm/arch-spear/hardware.h b/arch/arm/include/asm/arch-spear/hardware.h
index f3afd4d065..c6da405cc0 100644
--- a/arch/arm/include/asm/arch-spear/hardware.h
+++ b/arch/arm/include/asm/arch-spear/hardware.h
@@ -26,7 +26,6 @@
 #define CONFIG_SYS_NAND_ALE			(1 << 17)
 
 #if defined(CONFIG_SPEAR600)
-#define CONFIG_SYS_I2C_BASE			0xD0200000
 #define CONFIG_SYS_FSMC_BASE			0xD1800000
 #define CONFIG_FSMC_NAND_BASE			0xD2000000
 
@@ -42,11 +41,9 @@
 #define CONFIG_SPEAR_MPMCREGS			100
 
 #elif defined(CONFIG_SPEAR300)
-#define CONFIG_SYS_I2C_BASE			0xD0180000
 #define CONFIG_SYS_FSMC_BASE			0x94000000
 
 #elif defined(CONFIG_SPEAR310)
-#define CONFIG_SYS_I2C_BASE			0xD0180000
 #define CONFIG_SYS_FSMC_BASE			0x44000000
 
 #undef CONFIG_SYS_NAND_CLE
@@ -63,7 +60,6 @@
 #define CONFIG_SYS_MACB3_BASE			0xB1800000
 
 #elif defined(CONFIG_SPEAR320)
-#define CONFIG_SYS_I2C_BASE			0xD0180000
 #define CONFIG_SYS_FSMC_BASE			0x4C000000
 
 #define CONFIG_SPEAR_EMIBASE			0x40000000
diff --git a/arch/arm/include/asm/arch-tegra/clk_rst.h b/arch/arm/include/asm/arch-tegra/clk_rst.h
index 074b3bca0b..7d28e16f1c 100644
--- a/arch/arm/include/asm/arch-tegra/clk_rst.h
+++ b/arch/arm/include/asm/arch-tegra/clk_rst.h
@@ -1,5 +1,5 @@
 /*
- *  (C) Copyright 2010,2011
+ *  (C) Copyright 2010-2014
  *  NVIDIA Corporation <www.nvidia.com>
  *
  * SPDX-License-Identifier:	GPL-2.0+
@@ -11,7 +11,8 @@
 /* PLL registers - there are several PLLs in the clock controller */
 struct clk_pll {
 	uint pll_base;		/* the control register */
-	uint pll_out[2];	/* output control */
+	/* pll_out[0] is output A control, pll_out[1] is output B control */
+	uint pll_out[2];
 	uint pll_misc;		/* other misc things */
 };
 
@@ -21,6 +22,13 @@ struct clk_pll_simple {
 	uint pll_misc;		/* other misc things */
 };
 
+struct clk_pllm {
+	uint pllm_base;		/* the control register */
+	uint pllm_out;		/* output control */
+	uint pllm_misc1;	/* misc1 */
+	uint pllm_misc2;	/* misc2 */
+};
+
 /* RST_DEV_(L,H,U,V,W)_(SET,CLR) and CLK_ENB_(L,H,U,V,W)_(SET,CLR) */
 struct clk_set_clr {
 	uint set;
@@ -38,7 +46,8 @@ enum {
 	TEGRA_CLK_REGS		= 3,	/* Number of clock enable regs L/H/U */
 	TEGRA_CLK_SOURCES	= 64,	/* Number of ppl clock sources L/H/U */
 	TEGRA_CLK_REGS_VW	= 2,	/* Number of clock enable regs V/W */
-	TEGRA_CLK_SOURCES_VW	= 32,	/* Number of ppl clock sources V/W*/
+	TEGRA_CLK_SOURCES_VW	= 32,	/* Number of ppl clock sources V/W */
+	TEGRA_CLK_SOURCES_X	= 32,	/* Number of ppl clock sources X */
 };
 
 /* Clock/Reset Controller (CLK_RST_CONTROLLER_) regs */
@@ -47,7 +56,7 @@ struct clk_rst_ctlr {
 	uint crc_rst_dev[TEGRA_CLK_REGS];	/* _RST_DEVICES_L/H/U_0 */
 	uint crc_clk_out_enb[TEGRA_CLK_REGS];	/* _CLK_OUT_ENB_L/H/U_0 */
 	uint crc_reserved0;		/* reserved_0,		0x1C */
-	uint crc_cclk_brst_pol;		/* _CCLK_BURST_POLICY_0,0x20 */
+	uint crc_cclk_brst_pol;		/* _CCLK_BURST_POLICY_0, 0x20 */
 	uint crc_super_cclk_div;	/* _SUPER_CCLK_DIVIDER_0,0x24 */
 	uint crc_sclk_brst_pol;		/* _SCLK_BURST_POLICY_0, 0x28 */
 	uint crc_super_sclk_div;	/* _SUPER_SCLK_DIVIDER_0,0x2C */
@@ -75,7 +84,21 @@ struct clk_rst_ctlr {
 
 	uint crc_clk_src[TEGRA_CLK_SOURCES]; /*_I2S1_0...	0x100-1fc */
 
-	uint crc_reserved20[64];	/* _reserved_20,	0x200-2fc */
+	uint crc_reserved20[32];	/* _reserved_20,	0x200-27c */
+
+	uint crc_clk_out_enb_x;		/* _CLK_OUT_ENB_X_0,	0x280 */
+	uint crc_clk_enb_x_set;		/* _CLK_ENB_X_SET_0,	0x284 */
+	uint crc_clk_enb_x_clr;		/* _CLK_ENB_X_CLR_0,	0x288 */
+
+	uint crc_rst_devices_x;		/* _RST_DEVICES_X_0,	0x28c */
+	uint crc_rst_dev_x_set;		/* _RST_DEV_X_SET_0,	0x290 */
+	uint crc_rst_dev_x_clr;		/* _RST_DEV_X_CLR_0,	0x294 */
+
+	uint crc_reserved21[23];	/* _reserved_21,	0x298-2f0 */
+
+	uint crc_dfll_base;		/* _DFLL_BASE_0,	0x2f4 */
+
+	uint crc_reserved22[2];		/* _reserved_22,	0x2f8-2fc */
 
 	/* _RST_DEV_L/H/U_SET_0 0x300 ~ 0x314 */
 	struct clk_set_clr crc_rst_dev_ex[TEGRA_CLK_REGS];
@@ -105,10 +128,10 @@ struct clk_rst_ctlr {
 	uint crc_clk_cpug_cmplx;	/* _CLK_CPUG_CMPLX_0,       0x378 */
 	uint crc_clk_cpulp_cmplx;	/* _CLK_CPULP_CMPLX_0,      0x37C */
 	uint crc_cpu_softrst_ctrl;	/* _CPU_SOFTRST_CTRL_0,     0x380 */
-	uint crc_cpu_softrst_ctrl1;	/* _CPU_SOFTRST_CTR1L_0,    0x384 */
+	uint crc_cpu_softrst_ctrl1;	/* _CPU_SOFTRST_CTRL1_0,    0x384 */
 	uint crc_cpu_softrst_ctrl2;	/* _CPU_SOFTRST_CTRL2_0,    0x388 */
 	uint crc_reserved33[9];		/* _reserved_33,        0x38c-3ac */
-	uint crc_clk_src_vw[TEGRA_CLK_SOURCES_VW]; /* _G3D2_0..., 0x3b0-0x42c */
+	uint crc_clk_src_vw[TEGRA_CLK_SOURCES_VW];	/* 0x3B0-0x42C */
 	/* _RST_DEV_V/W_SET_0 0x430 ~ 0x43c */
 	struct clk_set_clr crc_rst_dev_ex_vw[TEGRA_CLK_REGS_VW];
 	/* _CLK_ENB_V/W_CLR_0 0x440 ~ 0x44c */
@@ -142,6 +165,47 @@ struct clk_rst_ctlr {
 	uint crc_audio_sync_clk_i2s3;	/* _AUDIO_SYNC_CLK_I2S3_0, 0x4AC */
 	uint crc_audio_sync_clk_i2s4;	/* _AUDIO_SYNC_CLK_I2S4_0, 0x4B0 */
 	uint crc_audio_sync_clk_spdif;	/* _AUDIO_SYNC_CLK_SPDIF_0, 0x4B4 */
+
+	uint crc_plld2_base;		/* _PLLD2_BASE_0, 0x4B8 */
+	uint crc_plld2_misc;		/* _PLLD2_MISC_0, 0x4BC */
+	uint crc_utmip_pll_cfg3;	/* _UTMIP_PLL_CFG3_0, 0x4C0 */
+	uint crc_pllrefe_base;		/* _PLLREFE_BASE_0, 0x4C4 */
+	uint crc_pllrefe_misc;		/* _PLLREFE_MISC_0, 0x4C8 */
+	uint crs_reserved_50[7];	/* _reserved_50, 0x4CC-0x4E4 */
+	uint crc_pllc2_base;		/* _PLLC2_BASE_0, 0x4E8 */
+	uint crc_pllc2_misc0;		/* _PLLC2_MISC_0_0, 0x4EC */
+	uint crc_pllc2_misc1;		/* _PLLC2_MISC_1_0, 0x4F0 */
+	uint crc_pllc2_misc2;		/* _PLLC2_MISC_2_0, 0x4F4 */
+	uint crc_pllc2_misc3;		/* _PLLC2_MISC_3_0, 0x4F8 */
+	uint crc_pllc3_base;		/* _PLLC3_BASE_0, 0x4FC */
+	uint crc_pllc3_misc0;		/* _PLLC3_MISC_0_0, 0x500 */
+	uint crc_pllc3_misc1;		/* _PLLC3_MISC_1_0, 0x504 */
+	uint crc_pllc3_misc2;		/* _PLLC3_MISC_2_0, 0x508 */
+	uint crc_pllc3_misc3;		/* _PLLC3_MISC_3_0, 0x50C */
+	uint crc_pllx_misc1;		/* _PLLX_MISC_1_0, 0x510 */
+	uint crc_pllx_misc2;		/* _PLLX_MISC_2_0, 0x514 */
+	uint crc_pllx_misc3;		/* _PLLX_MISC_3_0, 0x518 */
+	uint crc_xusbio_pll_cfg0;	/* _XUSBIO_PLL_CFG0_0, 0x51C */
+	uint crc_xusbio_pll_cfg1;	/* _XUSBIO_PLL_CFG0_1, 0x520 */
+	uint crc_plle_aux1;		/* _PLLE_AUX1_0, 0x524 */
+	uint crc_pllp_reshift;		/* _PLLP_RESHIFT_0, 0x528 */
+	uint crc_utmipll_hw_pwrdn_cfg0;	/* _UTMIPLL_HW_PWRDN_CFG0_0, 0x52C */
+	uint crc_pllu_hw_pwrdn_cfg0;	/* _PLLU_HW_PWRDN_CFG0_0, 0x530 */
+	uint crc_xusb_pll_cfg0;		/* _XUSB_PLL_CFG0_0, 0x534 */
+	uint crc_reserved51[1];		/* _reserved_51, 0x538 */
+	uint crc_clk_cpu_misc;		/* _CLK_CPU_MISC_0, 0x53C */
+	uint crc_clk_cpug_misc;		/* _CLK_CPUG_MISC_0, 0x540 */
+	uint crc_clk_cpulp_misc;	/* _CLK_CPULP_MISC_0, 0x544 */
+	uint crc_pllx_hw_ctrl_cfg;	/* _PLLX_HW_CTRL_CFG_0, 0x548 */
+	uint crc_pllx_sw_ramp_cfg;	/* _PLLX_SW_RAMP_CFG_0, 0x54C */
+	uint crc_pllx_hw_ctrl_status;	/* _PLLX_HW_CTRL_STATUS_0, 0x550 */
+	uint crc_reserved52[1];		/* _reserved_52, 0x554 */
+	uint crc_super_gr3d_clk_div;	/* _SUPER_GR3D_CLK_DIVIDER_0, 0x558 */
+	uint crc_spare_reg0;		/* _SPARE_REG0_0, 0x55C */
+
+	/* Tegra124 - skip to 0x600 here for new CLK_SOURCE_ regs */
+	uint crc_reserved60[40];	/* _reserved_60, 0x560 - 0x5FC */
+	uint crc_clk_src_x[TEGRA_CLK_SOURCES_X]; /* XUSB, etc, 0x600-0x678 */
 };
 
 /* CLK_RST_CONTROLLER_CLK_CPU_CMPLX_0 */
@@ -160,6 +224,9 @@ struct clk_rst_ctlr {
 
 #define PLL_BASE_OVRRIDE_MASK	(1U << 28)
 
+#define PLL_LOCK_SHIFT		27
+#define PLL_LOCK_MASK		(1U << PLL_LOCK_SHIFT)
+
 #define PLL_DIVP_SHIFT		20
 #define PLL_DIVP_MASK		(7U << PLL_DIVP_SHIFT)
 
@@ -209,6 +276,20 @@ enum {
 	IN_408_OUT_9_6_DIVISOR = 83,
 };
 
+#define PLLP_OUT1_RSTN_DIS	(1 << 0)
+#define PLLP_OUT1_RSTN_EN	(0 << 0)
+#define PLLP_OUT1_CLKEN		(1 << 1)
+#define PLLP_OUT2_RSTN_DIS	(1 << 16)
+#define PLLP_OUT2_RSTN_EN	(0 << 16)
+#define PLLP_OUT2_CLKEN		(1 << 17)
+
+#define PLLP_OUT3_RSTN_DIS	(1 << 0)
+#define PLLP_OUT3_RSTN_EN	(0 << 0)
+#define PLLP_OUT3_CLKEN		(1 << 1)
+#define PLLP_OUT4_RSTN_DIS	(1 << 16)
+#define PLLP_OUT4_RSTN_EN	(0 << 16)
+#define PLLP_OUT4_CLKEN		(1 << 17)
+
 /* CLK_RST_CONTROLLER_UTMIP_PLL_CFG1_0 */
 #define PLLU_POWERDOWN		(1 << 16)
 #define PLL_ENABLE_POWERDOWN	(1 << 14)
@@ -219,9 +300,15 @@ enum {
 #define UTMIP_FORCE_PD_SAMP_B_POWERDOWN		(1 << 2)
 #define UTMIP_FORCE_PD_SAMP_A_POWERDOWN		(1 << 0)
 
-/* CLK_RST_CONTROLLER_OSC_CTRL_0 */
-#define OSC_XOBP_SHIFT		1
-#define OSC_XOBP_MASK		(1U << OSC_XOBP_SHIFT)
+/* CLK_RST_CONTROLLER_OSC_CTRL_0 0x50 */
+#define OSC_XOE_SHIFT			0
+#define OSC_XOE_MASK			(1 << OSC_XOE_SHIFT)
+#define OSC_XOE_ENABLE			(1 << OSC_XOE_SHIFT)
+#define OSC_XOBP_SHIFT			1
+#define OSC_XOBP_MASK			(1U << OSC_XOBP_SHIFT)
+#define OSC_XOFS_SHIFT			4
+#define OSC_XOFS_MASK			(0x3F << OSC_XOFS_SHIFT)
+#define OSC_DRIVE_STRENGTH		7
 
 /*
  * CLK_RST_CONTROLLER_CLK_SOURCE_x_OUT_0 - the mask here is normally 8 bits
@@ -233,11 +320,15 @@ enum {
 #define OUT_CLK_DIVISOR_SHIFT	0
 #define OUT_CLK_DIVISOR_MASK	(0xffff << OUT_CLK_DIVISOR_SHIFT)
 
-#define OUT_CLK_SOURCE_SHIFT	30
-#define OUT_CLK_SOURCE_MASK	(3U << OUT_CLK_SOURCE_SHIFT)
+#define OUT_CLK_SOURCE_31_30_SHIFT	30
+#define OUT_CLK_SOURCE_31_30_MASK	(3U << OUT_CLK_SOURCE_31_30_SHIFT)
+
+#define OUT_CLK_SOURCE_31_29_SHIFT	29
+#define OUT_CLK_SOURCE_31_29_MASK	(7U << OUT_CLK_SOURCE_31_29_SHIFT)
 
-#define OUT_CLK_SOURCE4_SHIFT	28
-#define OUT_CLK_SOURCE4_MASK	(15U << OUT_CLK_SOURCE4_SHIFT)
+/* Note: See comment for MASK_BITS_31_28 in arch-tegra/clock.h */
+#define OUT_CLK_SOURCE_31_28_SHIFT	28
+#define OUT_CLK_SOURCE_31_28_MASK	(15U << OUT_CLK_SOURCE_31_28_SHIFT)
 
 /* CLK_RST_CONTROLLER_SCLK_BURST_POLICY */
 #define SCLK_SYS_STATE_SHIFT    28U
@@ -290,7 +381,7 @@ enum {
 #define SUPER_SCLK_DIVISOR_SHIFT	0
 #define SUPER_SCLK_DIVISOR_MASK		(0xff << SUPER_SCLK_DIVISOR_SHIFT)
 
-/* CLK_RST_CONTROLLER_CLK_SYSTEM_RATE */
+/* CLK_RST_CONTROLLER_CLK_SYSTEM_RATE 0x30 */
 #define CLK_SYS_RATE_HCLK_DISABLE_SHIFT 7
 #define CLK_SYS_RATE_HCLK_DISABLE_MASK  (1 << CLK_SYS_RATE_HCLK_DISABLE_SHIFT)
 #define CLK_SYS_RATE_AHB_RATE_SHIFT     4
@@ -300,23 +391,53 @@ enum {
 #define CLK_SYS_RATE_APB_RATE_SHIFT     0
 #define CLK_SYS_RATE_APB_RATE_MASK      (3 << CLK_SYS_RATE_AHB_RATE_SHIFT)
 
-/* CLK_RST_CONTROLLER_RST_CPUxx_CMPLX_CLR */
-#define CLR_CPURESET0   (1 << 0)
-#define CLR_CPURESET1   (1 << 1)
-#define CLR_CPURESET2   (1 << 2)
-#define CLR_CPURESET3   (1 << 3)
-#define CLR_DBGRESET0   (1 << 12)
-#define CLR_DBGRESET1   (1 << 13)
-#define CLR_DBGRESET2   (1 << 14)
-#define CLR_DBGRESET3   (1 << 15)
-#define CLR_CORERESET0  (1 << 16)
-#define CLR_CORERESET1  (1 << 17)
-#define CLR_CORERESET2  (1 << 18)
-#define CLR_CORERESET3  (1 << 19)
-#define CLR_CXRESET0    (1 << 20)
-#define CLR_CXRESET1    (1 << 21)
-#define CLR_CXRESET2    (1 << 22)
-#define CLR_CXRESET3    (1 << 23)
-#define CLR_NONCPURESET (1 << 29)
+/* CLK_RST_CONTROLLER_RST_CPUxx_CMPLX_CLR 0x344 */
+#define CLR_CPURESET0			(1 << 0)
+#define CLR_CPURESET1			(1 << 1)
+#define CLR_CPURESET2			(1 << 2)
+#define CLR_CPURESET3			(1 << 3)
+#define CLR_DBGRESET0			(1 << 12)
+#define CLR_DBGRESET1			(1 << 13)
+#define CLR_DBGRESET2			(1 << 14)
+#define CLR_DBGRESET3			(1 << 15)
+#define CLR_CORERESET0			(1 << 16)
+#define CLR_CORERESET1			(1 << 17)
+#define CLR_CORERESET2			(1 << 18)
+#define CLR_CORERESET3			(1 << 19)
+#define CLR_CXRESET0			(1 << 20)
+#define CLR_CXRESET1			(1 << 21)
+#define CLR_CXRESET2			(1 << 22)
+#define CLR_CXRESET3			(1 << 23)
+#define CLR_L2RESET			(1 << 24)
+#define CLR_NONCPURESET			(1 << 29)
+#define CLR_PRESETDBG			(1 << 30)
+
+/* CLK_RST_CONTROLLER_CLK_CPU_CMPLX_CLR 0x34c */
+#define CLR_CPU0_CLK_STP		(1 << 8)
+#define CLR_CPU1_CLK_STP		(1 << 9)
+#define CLR_CPU2_CLK_STP		(1 << 10)
+#define CLR_CPU3_CLK_STP		(1 << 11)
+
+/* CRC_CLK_SOURCE_MSELECT_0 0x3b4 */
+#define MSELECT_CLK_SRC_PLLP_OUT0	(0 << 29)
+
+/* CRC_CLK_ENB_V_SET_0 0x440 */
+#define SET_CLK_ENB_CPUG_ENABLE		(1 << 0)
+#define SET_CLK_ENB_CPULP_ENABLE	(1 << 1)
+#define SET_CLK_ENB_MSELECT_ENABLE	(1 << 3)
+
+/* CLK_RST_CONTROLLER_UTMIP_PLL_CFG1_0 0x484 */
+#define PLL_ACTIVE_POWERDOWN		(1 << 12)
+#define PLL_ENABLE_POWERDOWN		(1 << 14)
+#define PLLU_POWERDOWN			(1 << 16)
+
+/* CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0 0x488 */
+#define UTMIP_FORCE_PD_SAMP_A_POWERDOWN	(1 << 0)
+#define UTMIP_FORCE_PD_SAMP_B_POWERDOWN	(1 << 2)
+#define UTMIP_FORCE_PD_SAMP_C_POWERDOWN	(1 << 4)
+
+/* CLK_RST_CONTROLLER_PLLX_MISC_3 */
+#define PLLX_IDDQ_SHIFT			3
+#define PLLX_IDDQ_MASK			(1U << PLLX_IDDQ_SHIFT)
 
 #endif	/* _TEGRA_CLK_RST_H_ */
diff --git a/arch/arm/include/asm/arch-tegra/clock.h b/arch/arm/include/asm/arch-tegra/clock.h
index c3174bd7fc..9d8114c4ec 100644
--- a/arch/arm/include/asm/arch-tegra/clock.h
+++ b/arch/arm/include/asm/arch-tegra/clock.h
@@ -20,6 +20,21 @@ enum clock_osc_freq {
 	CLOCK_OSC_FREQ_COUNT,
 };
 
+/*
+ * Note that no Tegra clock register actually uses all of bits 31:28 as
+ * the mux field. Rather, bits 30:28, 29:28, or 28 are used. However, in
+ * those cases, nothing is stored in the bits about the mux field, so it's
+ * safe to pretend that the mux field extends all the way to the end of the
+ * register. As such, the U-Boot clock driver is currently a bit lazy, and
+ * doesn't distinguish between 31:28, 30:28, 29:28 and 28; it just lumps
+ * them all together and pretends they're all 31:28.
+ */
+enum {
+	MASK_BITS_31_30,
+	MASK_BITS_31_29,
+	MASK_BITS_31_28,
+};
+
 #include <asm/arch/clock-tables.h>
 /* PLL stabilization delay in usec */
 #define CLOCK_PLL_STABLE_DELAY_US 300
@@ -113,9 +128,9 @@ void reset_set_enable(enum periph_id periph_id, int enable);
 enum crc_reset_id {
 	/* Things we can hold in reset for each CPU */
 	crc_rst_cpu = 1,
-	crc_rst_de = 1 << 2,	/* What is de? */
-	crc_rst_watchdog = 1 << 3,
-	crc_rst_debug = 1 << 4,
+	crc_rst_de = 1 << 4,	/* What is de? */
+	crc_rst_watchdog = 1 << 8,
+	crc_rst_debug = 1 << 12,
 };
 
 /**
@@ -305,4 +320,6 @@ int clock_set_rate(enum clock_id clkid, u32 n, u32 m, u32 p, u32 cpcon);
 /* SoC-specific TSC init */
 void arch_timer_init(void);
 
+void tegra30_set_up_pllp(void);
+
 #endif  /* _TEGRA_CLOCK_H_ */
diff --git a/arch/arm/include/asm/arch-tegra/gp_padctrl.h b/arch/arm/include/asm/arch-tegra/gp_padctrl.h
index c840c08a89..7a86acb1b2 100644
--- a/arch/arm/include/asm/arch-tegra/gp_padctrl.h
+++ b/arch/arm/include/asm/arch-tegra/gp_padctrl.h
@@ -20,5 +20,6 @@
 #define CHIPID_TEGRA20			0x20
 #define CHIPID_TEGRA30			0x30
 #define CHIPID_TEGRA114			0x35
+#define CHIPID_TEGRA124			0x40
 
 #endif	/* _TEGRA_GP_PADCTRL_H_ */
diff --git a/arch/arm/include/asm/arch-tegra/pmc.h b/arch/arm/include/asm/arch-tegra/pmc.h
index ba22236ee3..1dd3154fbc 100644
--- a/arch/arm/include/asm/arch-tegra/pmc.h
+++ b/arch/arm/include/asm/arch-tegra/pmc.h
@@ -1,5 +1,5 @@
 /*
- *  (C) Copyright 2010,2011
+ *  (C) Copyright 2010,2011,2014
  *  NVIDIA Corporation <www.nvidia.com>
  *
  * SPDX-License-Identifier:	GPL-2.0+
@@ -21,7 +21,11 @@ struct pmc_ctlr {
 	uint pmc_dpd_sample;		/* _DPD_PADS_SAMPLE_0, offset 20 */
 	uint pmc_dpd_enable;		/* _DPD_PADS_ENABLE_0, offset 24 */
 	uint pmc_pwrgate_timer_off;	/* _PWRGATE_TIMER_OFF_0, offset 28 */
+#if defined(CONFIG_TEGRA20) || defined(CONFIG_TEGRA30)
 	uint pmc_pwrgate_timer_on;	/* _PWRGATE_TIMER_ON_0, offset 2C */
+#else
+	uint pmc_clamp_status;		/* _CLAMP_STATUS_0, offset 2C */
+#endif
 	uint pmc_pwrgate_toggle;	/* _PWRGATE_TOGGLE_0, offset 30 */
 	uint pmc_remove_clamping;	/* _REMOVE_CLAMPING_CMD_0, offset 34 */
 	uint pmc_pwrgate_status;	/* _PWRGATE_STATUS_0, offset 38 */
@@ -103,6 +107,179 @@ struct pmc_ctlr {
 	uint pmc_sys_33v_en;		/* _SYS_33V_EN_0, offset 154 */
 	uint pmc_bo_mirror_access;	/* _BOUNDOUT_MIRROR_ACCESS_0, off158 */
 	uint pmc_gate;			/* _GATE_0, offset 15C */
+	/* The following fields are in Tegra124 and later only */
+	uint pmc_wake2_mask;		/* _WAKE2_MASK_0, offset 160 */
+	uint pmc_wake2_lvl;		/* _WAKE2_LVL_0,  offset 164 */
+	uint pmc_wake2_stat;		/* _WAKE2_STATUS_0, offset 168 */
+	uint pmc_sw_wake2_stat;		/* _SW_WAKE2_STATUS_0, offset 16C */
+	uint pmc_auto_wake2_lvl_mask;	/* _AUTO_WAKE2_LVL_MASK_0, offset 170 */
+	uint pmc_pg_mask2;		/* _PG_MASK_2_0, offset 174 */
+	uint pmc_pg_mask_ce1;		/* _PG_MASK_CE1_0, offset 178 */
+	uint pmc_pg_mask_ce2;		/* _PG_MASK_CE2_0, offset 17C */
+	uint pmc_pg_mask_ce3;		/* _PG_MASK_CE3_0, offset 180 */
+	uint pmc_pwrgate_timer_ce0;	/* _PWRGATE_TIMER_CE_0_0, offset 184 */
+	uint pmc_pwrgate_timer_ce1;	/* _PWRGATE_TIMER_CE_1_0, offset 188 */
+	uint pmc_pwrgate_timer_ce2;	/* _PWRGATE_TIMER_CE_2_0, offset 18C */
+	uint pmc_pwrgate_timer_ce3;	/* _PWRGATE_TIMER_CE_3_0, offset 190 */
+	uint pmc_pwrgate_timer_ce4;	/* _PWRGATE_TIMER_CE_4_0, offset 194 */
+	uint pmc_pwrgate_timer_ce5;	/* _PWRGATE_TIMER_CE_5_0, offset 198 */
+	uint pmc_pwrgate_timer_ce6;	/* _PWRGATE_TIMER_CE_6_0, offset 19C */
+	uint pmc_pcx_edpd_cntrl;	/* _PCX_EDPD_CNTRL_0, offset 1A0 */
+	uint pmc_osc_edpd_over;		/* _OSC_EDPD_OVER_0, offset 1A4 */
+	uint pmc_clk_out_cntrl;		/* _CLK_OUT_CNTRL_0, offset 1A8 */
+	uint pmc_sata_pwrgate;		/* _SATA_PWRGT_0, offset 1AC */
+	uint pmc_sensor_ctrl;		/* _SENSOR_CTRL_0, offset 1B0 */
+	uint pmc_reset_status;		/* _RTS_STATUS_0, offset 1B4 */
+	uint pmc_io_dpd_req;		/* _IO_DPD_REQ_0, offset 1B8 */
+	uint pmc_io_dpd_stat;		/* _IO_DPD_STATUS_0, offset 1BC */
+	uint pmc_io_dpd2_req;		/* _IO_DPD2_REQ_0, offset 1C0 */
+	uint pmc_io_dpd2_stat;		/* _IO_DPD2_STATUS_0, offset 1C4 */
+	uint pmc_sel_dpd_tim;		/* _SEL_DPD_TIM_0, offset 1C8 */
+	uint pmc_vddp_sel;		/* _VDDP_SEL_0, offset 1CC */
+
+	uint pmc_ddr_cfg;		/* _DDR_CFG_0, offset 1D0 */
+	uint pmc_e_no_vttgen;		/* _E_NO_VTTGEN_0, offset 1D4 */
+	uint pmc_reserved0;		/* _RESERVED, offset 1D8 */
+	uint pmc_pllm_wb0_ovrride_frq;	/* _PLLM_WB0_OVERRIDE_FREQ_0, off 1DC */
+	uint pmc_test_pwrgate;		/* _TEST_PWRGATE_0, offset 1E0 */
+	uint pmc_pwrgate_timer_mult;	/* _PWRGATE_TIMER_MULT_0, offset 1E4 */
+	uint pmc_dsi_sel_dpd;		/* _DSI_SEL_DPD_0, offset 1E8 */
+	uint pmc_utmip_uhsic_triggers;	/* _UTMIP_UHSIC_TRIGGERS_0, off 1EC */
+	uint pmc_utmip_uhsic_saved_st;  /* _UTMIP_UHSIC_SAVED_STATE_0, off1F0 */
+	uint pmc_utmip_pad_cfg;		/* _UTMIP_PAD_CFG_0, offset 1F4 */
+	uint pmc_utmip_term_pad_cfg;	/* _UTMIP_TERM_PAD_CFG_0, offset 1F8 */
+	uint pmc_utmip_uhsic_sleep_cfg;	/* _UTMIP_UHSIC_SLEEP_CFG_0, off 1FC */
+
+	uint pmc_todo_0[9];		/* offset 200-220 */
+	uint pmc_secure_scratch6;	/* _SECURE_SCRATCH6_0, offset 224 */
+	uint pmc_secure_scratch7;	/* _SECURE_SCRATCH7_0, offset 228 */
+	uint pmc_scratch43;		/* _SCRATCH43_0, offset 22C */
+	uint pmc_scratch44;		/* _SCRATCH44_0, offset 230 */
+	uint pmc_scratch45;
+	uint pmc_scratch46;
+	uint pmc_scratch47;
+	uint pmc_scratch48;
+	uint pmc_scratch49;
+	uint pmc_scratch50;
+	uint pmc_scratch51;
+	uint pmc_scratch52;
+	uint pmc_scratch53;
+	uint pmc_scratch54;
+	uint pmc_scratch55;		/* _SCRATCH55_0, offset 25C */
+	uint pmc_scratch0_eco;		/* _SCRATCH0_ECO_0, offset 260 */
+	uint pmc_por_dpd_ctrl;		/* _POR_DPD_CTRL_0, offset 264 */
+	uint pmc_scratch2_eco;		/* _SCRATCH2_ECO_0, offset 268 */
+	uint pmc_todo_1[17];		/* TODO: 26C ~ 2AC */
+	uint pmc_pllm_wb0_override2;	/* _PLLM_WB0_OVERRIDE2, offset 2B0 */
+	uint pmc_tsc_mult;		/* _TSC_MULT_0, offset 2B4 */
+	uint pmc_cpu_vsense_override;	/* _CPU_VSENSE_OVERRIDE_0, offset 2B8 */
+	uint pmc_glb_amap_cfg;		/* _GLB_AMAP_CFG_0, offset 2BC */
+	uint pmc_sticky_bits;		/* _STICKY_BITS_0, offset 2C0 */
+	uint pmc_sec_disable2;		/* _SEC_DISALBE2, offset 2C4 */
+	uint pmc_weak_bias;		/* _WEAK_BIAS_0, offset 2C8 */
+	uint pmc_todo_3[13];		/* TODO: 2CC ~ 2FC */
+	uint pmc_secure_scratch8;	/* _SECURE_SCRATCH8_0, offset 300 */
+	uint pmc_secure_scratch9;
+	uint pmc_secure_scratch10;
+	uint pmc_secure_scratch11;
+	uint pmc_secure_scratch12;
+	uint pmc_secure_scratch13;
+	uint pmc_secure_scratch14;
+	uint pmc_secure_scratch15;
+	uint pmc_secure_scratch16;
+	uint pmc_secure_scratch17;
+	uint pmc_secure_scratch18;
+	uint pmc_secure_scratch19;
+	uint pmc_secure_scratch20;
+	uint pmc_secure_scratch21;
+	uint pmc_secure_scratch22;
+	uint pmc_secure_scratch23;
+	uint pmc_secure_scratch24;	/* _SECURE_SCRATCH24_0, offset 340 */
+	uint pmc_secure_scratch25;
+	uint pmc_secure_scratch26;
+	uint pmc_secure_scratch27;
+	uint pmc_secure_scratch28;
+	uint pmc_secure_scratch29;
+	uint pmc_secure_scratch30;
+	uint pmc_secure_scratch31;
+	uint pmc_secure_scratch32;
+	uint pmc_secure_scratch33;
+	uint pmc_secure_scratch34;
+	uint pmc_secure_scratch35;	/* _SECURE_SCRATCH35_0, offset 36C */
+
+	uint pmc_reserved1[52];		/* RESERVED: 370 ~ 43C */
+	uint pmc_cntrl2;		/* _CNTRL2_0, offset 440 */
+	uint pmc_reserved2[6];		/* RESERVED: 444 ~ 458 */
+	uint pmc_io_dpd3_req;		/* _IO_DPD3_REQ_0, offset 45c */
+	uint pmc_io_dpd3_stat;		/* _IO_DPD3_STATUS_0, offset 460 */
+	uint pmc_strap_opt_a;		/* _STRAPPING_OPT_A_0, offset 464 */
+	uint pmc_reserved3[102];	/* RESERVED: 468 ~ 5FC */
+
+	uint pmc_scratch56;		/* _SCRATCH56_0, offset 600 */
+	uint pmc_scratch57;
+	uint pmc_scratch58;
+	uint pmc_scratch59;
+	uint pmc_scratch60;
+	uint pmc_scratch61;
+	uint pmc_scratch62;
+	uint pmc_scratch63;
+	uint pmc_scratch64;
+	uint pmc_scratch65;
+	uint pmc_scratch66;
+	uint pmc_scratch67;
+	uint pmc_scratch68;
+	uint pmc_scratch69;
+	uint pmc_scratch70;
+	uint pmc_scratch71;
+	uint pmc_scratch72;
+	uint pmc_scratch73;
+	uint pmc_scratch74;
+	uint pmc_scratch75;
+	uint pmc_scratch76;
+	uint pmc_scratch77;
+	uint pmc_scratch78;
+	uint pmc_scratch79;
+	uint pmc_scratch80;
+	uint pmc_scratch81;
+	uint pmc_scratch82;
+	uint pmc_scratch83;
+	uint pmc_scratch84;
+	uint pmc_scratch85;
+	uint pmc_scratch86;
+	uint pmc_scratch87;
+	uint pmc_scratch88;
+	uint pmc_scratch89;
+	uint pmc_scratch90;
+	uint pmc_scratch91;
+	uint pmc_scratch92;
+	uint pmc_scratch93;
+	uint pmc_scratch94;
+	uint pmc_scratch95;
+	uint pmc_scratch96;
+	uint pmc_scratch97;
+	uint pmc_scratch98;
+	uint pmc_scratch99;
+	uint pmc_scratch100;
+	uint pmc_scratch101;
+	uint pmc_scratch102;
+	uint pmc_scratch103;
+	uint pmc_scratch104;
+	uint pmc_scratch105;
+	uint pmc_scratch106;
+	uint pmc_scratch107;
+	uint pmc_scratch108;
+	uint pmc_scratch109;
+	uint pmc_scratch110;
+	uint pmc_scratch111;
+	uint pmc_scratch112;
+	uint pmc_scratch113;
+	uint pmc_scratch114;
+	uint pmc_scratch115;
+	uint pmc_scratch116;
+	uint pmc_scratch117;
+	uint pmc_scratch118;
+	uint pmc_scratch119;
+	uint pmc_scratch1_eco;	/* offset 700 */
 };
 
 #define CPU_PWRED	1
@@ -114,11 +291,101 @@ struct pmc_ctlr {
 #define CPUPWRREQ_OE	(1 << 16)
 #define CPUPWRREQ_POL	(1 << 15)
 
-#define CRAILID		(0)
-#define CE0ID		(14)
-#define C0NCID		(15)
-#define CRAIL		(1 << CRAILID)
-#define CE0		(1 << CE0ID)
-#define C0NC		(1 << C0NCID)
+#define CRAIL		0
+#define CE0		14
+#define C0NC		15
+
+#define PMC_XOFS_SHIFT	1
+#define PMC_XOFS_MASK	(0x3F << PMC_XOFS_SHIFT)
+
+#if defined(CONFIG_TEGRA114)
+#define TIMER_MULT_SHIFT	0
+#define TIMER_MULT_MASK		(3 << TIMER_MULT_SHIFT)
+#define TIMER_MULT_CPU_SHIFT	2
+#define TIMER_MULT_CPU_MASK	(3 << TIMER_MULT_CPU_SHIFT)
+#elif defined(CONFIG_TEGRA124)
+#define TIMER_MULT_SHIFT	0
+#define TIMER_MULT_MASK		(7 << TIMER_MULT_SHIFT)
+#define TIMER_MULT_CPU_SHIFT	3
+#define TIMER_MULT_CPU_MASK	(7 << TIMER_MULT_CPU_SHIFT)
+#endif
+
+#define MULT_1			0
+#define MULT_2			1
+#define MULT_4			2
+#define MULT_8			3
+#if defined(CONFIG_TEGRA124)
+#define MULT_16			4
+#endif
+
+#define AMAP_WRITE_SHIFT	20
+#define AMAP_WRITE_ON		(1 << AMAP_WRITE_SHIFT)
+
+/* SEC_DISABLE_0, 0x04 */
+#define SEC_DISABLE_WRITE0_ON			(1 << 4)
+#define SEC_DISABLE_READ0_ON			(1 << 5)
+#define SEC_DISABLE_WRITE1_ON			(1 << 6)
+#define SEC_DISABLE_READ1_ON			(1 << 7)
+#define SEC_DISABLE_WRITE2_ON			(1 << 8)
+#define SEC_DISABLE_READ2_ON			(1 << 9)
+#define SEC_DISABLE_WRITE3_ON			(1 << 10)
+#define SEC_DISABLE_READ3_ON			(1 << 11)
+#define SEC_DISABLE_AMAP_WRITE_ON		(1 << 20)
+
+/* APBDEV_PMC_PWRGATE_TOGGLE_0 0x30 */
+#define PWRGATE_TOGGLE_PARTID_CRAIL		0
+#define PWRGATE_TOGGLE_PARTID_TD		1
+#define PWRGATE_TOGGLE_PARTID_VE		2
+#define PWRGATE_TOGGLE_PARTID_PCX		3
+#define PWRGATE_TOGGLE_PARTID_VDE		4
+#define PWRGATE_TOGGLE_PARTID_L2C		5
+#define PWRGATE_TOGGLE_PARTID_MPE		6
+#define PWRGATE_TOGGLE_PARTID_HEG		7
+#define PWRGATE_TOGGLE_PARTID_SAX		8
+#define PWRGATE_TOGGLE_PARTID_CE1		9
+#define PWRGATE_TOGGLE_PARTID_CE2		10
+#define PWRGATE_TOGGLE_PARTID_CE3		11
+#define PWRGATE_TOGGLE_PARTID_CELP		12
+#define PWRGATE_TOGGLE_PARTID_CE0		14
+#define PWRGATE_TOGGLE_PARTID_C0NC		15
+#define PWRGATE_TOGGLE_PARTID_C1NC		16
+#define PWRGATE_TOGGLE_PARTID_SOR		17
+#define PWRGATE_TOGGLE_PARTID_DIS		18
+#define PWRGATE_TOGGLE_PARTID_DISB		19
+#define PWRGATE_TOGGLE_PARTID_XUSBA		20
+#define PWRGATE_TOGGLE_PARTID_XUSBB		21
+#define PWRGATE_TOGGLE_PARTID_XUSBC		22
+#define PWRGATE_TOGGLE_PARTID_VIC		23
+#define PWRGATE_TOGGLE_PARTID_IRAM		24
+#define PWRGATE_TOGGLE_START			(1 << 8)
+
+/* APBDEV_PMC_PWRGATE_STATUS_0 0x38 */
+#define PWRGATE_STATUS_CRAIL_ENABLE		(1 << 0)
+#define PWRGATE_STATUS_TD_ENABLE		(1 << 1)
+#define PWRGATE_STATUS_VE_ENABLE		(1 << 2)
+#define PWRGATE_STATUS_PCX_ENABLE		(1 << 3)
+#define PWRGATE_STATUS_VDE_ENABLE		(1 << 4)
+#define PWRGATE_STATUS_L2C_ENABLE		(1 << 5)
+#define PWRGATE_STATUS_MPE_ENABLE		(1 << 6)
+#define PWRGATE_STATUS_HEG_ENABLE		(1 << 7)
+#define PWRGATE_STATUS_SAX_ENABLE		(1 << 8)
+#define PWRGATE_STATUS_CE1_ENABLE		(1 << 9)
+#define PWRGATE_STATUS_CE2_ENABLE		(1 << 10)
+#define PWRGATE_STATUS_CE3_ENABLE		(1 << 11)
+#define PWRGATE_STATUS_CELP_ENABLE		(1 << 12)
+#define PWRGATE_STATUS_CE0_ENABLE		(1 << 14)
+#define PWRGATE_STATUS_C0NC_ENABLE		(1 << 15)
+#define PWRGATE_STATUS_C1NC_ENABLE		(1 << 16)
+#define PWRGATE_STATUS_SOR_ENABLE		(1 << 17)
+#define PWRGATE_STATUS_DIS_ENABLE		(1 << 18)
+#define PWRGATE_STATUS_DISB_ENABLE		(1 << 19)
+#define PWRGATE_STATUS_XUSBA_ENABLE		(1 << 20)
+#define PWRGATE_STATUS_XUSBB_ENABLE		(1 << 21)
+#define PWRGATE_STATUS_XUSBC_ENABLE		(1 << 22)
+#define PWRGATE_STATUS_VIC_ENABLE		(1 << 23)
+#define PWRGATE_STATUS_IRAM_ENABLE		(1 << 24)
+
+/* APBDEV_PMC_CNTRL2_0 0x440 */
+#define HOLD_CKE_LOW_EN				(1 << 12)
 
 #endif	/* PMC_H */
diff --git a/arch/arm/include/asm/arch-tegra/tegra.h b/arch/arm/include/asm/arch-tegra/tegra.h
index 25d1fc4db1..d63af0e5fd 100644
--- a/arch/arm/include/asm/arch-tegra/tegra.h
+++ b/arch/arm/include/asm/arch-tegra/tegra.h
@@ -34,7 +34,12 @@
 #define NV_PA_PMC_BASE		(NV_PA_APB_MISC_BASE + 0xE400)
 #define NV_PA_EMC_BASE		(NV_PA_APB_MISC_BASE + 0xF400)
 #define NV_PA_FUSE_BASE		(NV_PA_APB_MISC_BASE + 0xF800)
+#if defined(CONFIG_TEGRA20) || defined(CONFIG_TEGRA30) || \
+	defined(CONFIG_TEGRA114)
 #define NV_PA_CSITE_BASE	0x70040000
+#else
+#define NV_PA_CSITE_BASE	0x70800000
+#endif
 #define TEGRA_USB_ADDR_MASK	0xFFFFC000
 
 #define NV_PA_SDRC_CS0		NV_PA_SDRAM_BASE
@@ -65,8 +70,10 @@ enum {
 	SKU_ID_T25E		= 0x1c,
 	SKU_ID_T33		= 0x80,
 	SKU_ID_T30		= 0x81, /* Cardhu value */
+	SKU_ID_TM30MQS_P_A3	= 0xb1,
 	SKU_ID_T114_ENG		= 0x00, /* Dalmore value, unfused */
 	SKU_ID_T114_1		= 0x01,
+	SKU_ID_T124_ENG		= 0x00, /* Venice2 value, unfused */
 };
 
 /*
@@ -80,6 +87,7 @@ enum {
 	TEGRA_SOC_T25,
 	TEGRA_SOC_T30,
 	TEGRA_SOC_T114,
+	TEGRA_SOC_T124,
 
 	TEGRA_SOC_CNT,
 	TEGRA_SOC_UNKNOWN	= -1,
diff --git a/arch/arm/include/asm/arch-tegra/tegra_mmc.h b/arch/arm/include/asm/arch-tegra/tegra_mmc.h
index b6896afd96..310bbd7df9 100644
--- a/arch/arm/include/asm/arch-tegra/tegra_mmc.h
+++ b/arch/arm/include/asm/arch-tegra/tegra_mmc.h
@@ -11,6 +11,9 @@
 
 #include <fdtdec.h>
 
+/* for mmc_config definition */
+#include <mmc.h>
+
 #define MAX_HOSTS		4	/* Max number of 'hosts'/controllers */
 
 #ifndef __ASSEMBLY__
@@ -138,6 +141,7 @@ struct mmc_host {
 	struct fdt_gpio_state wp_gpio;		/* Write Protect GPIO */
 	unsigned int version;	/* SDHCI spec. version */
 	unsigned int clock;	/* Current clock (MHz) */
+	struct mmc_config cfg;	/* mmc configuration */
 };
 
 void pad_init_mmc(struct mmc_host *host);
diff --git a/arch/arm/include/asm/arch-tegra/usb.h b/arch/arm/include/asm/arch-tegra/usb.h
index f66257c9f7..a1efd07c7d 100644
--- a/arch/arm/include/asm/arch-tegra/usb.h
+++ b/arch/arm/include/asm/arch-tegra/usb.h
@@ -131,8 +131,7 @@
 /* USB3_IF_USB_PHY_VBUS_SENSORS_0 */
 #define VBUS_VLD_STS			(1 << 26)
 
-
 /* Setup USB on the board */
-int board_usb_init(const void *blob);
+int usb_process_devicetree(const void *blob);
 
 #endif	/* _TEGRA_USB_H_ */
diff --git a/arch/arm/include/asm/arch-tegra114/tegra.h b/arch/arm/include/asm/arch-tegra114/tegra.h
index 5d426b524a..705ca5758e 100644
--- a/arch/arm/include/asm/arch-tegra114/tegra.h
+++ b/arch/arm/include/asm/arch-tegra114/tegra.h
@@ -17,6 +17,8 @@
 #ifndef _TEGRA114_H_
 #define _TEGRA114_H_
 
+#define CONFIG_TEGRA114
+
 #define NV_PA_SDRAM_BASE	0x80000000	/* 0x80000000 for real T114 */
 #define NV_PA_TSC_BASE		0x700F0000	/* System Counter TSC regs */
 
diff --git a/arch/arm/include/asm/arch-tegra124/ahb.h b/arch/arm/include/asm/arch-tegra124/ahb.h
new file mode 100644
index 0000000000..4e48c43bbf
--- /dev/null
+++ b/arch/arm/include/asm/arch-tegra124/ahb.h
@@ -0,0 +1,91 @@
+/*
+ * (C) Copyright 2013
+ * NVIDIA Corporation <www.nvidia.com>
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#ifndef _TEGRA124_AHB_H_
+#define _TEGRA124_AHB_H_
+
+struct ahb_ctlr {
+	u32 reserved0;			/* 00h */
+	u32 arbitration_disable;	/* _ARBITRATION_DISABLE_0,	04h */
+	u32 arbitration_priority_ctrl;	/* _ARBITRATION_PRIORITY_CTRL_0,08h */
+	u32 arbitration_usr_protect;	/* _ARBITRATION_USR_PROTECT_0,	0ch */
+	u32 gizmo_ahb_mem;		/* _GIZMO_AHB_MEM_0,		10h */
+	u32 gizmo_apb_dma;		/* _GIZMO_APB_DMA_0,		14h */
+	u32 reserved6[2];		/* 18h, 1ch */
+	u32 gizmo_usb;			/* _GIZMO_USB_0,		20h */
+	u32 gizmo_ahb_xbar_bridge;	/* _GIZMO_AHB_XBAR_BRIDGE_0,	24h */
+	u32 gizmo_cpu_ahb_bridge;	/* _GIZMO_CPU_AHB_BRIDGE_0,	28h */
+	u32 gizmo_cop_ahb_bridge;	/* _GIZMO_COP_AHB_BRIDGE_0,	2ch */
+	u32 gizmo_xbar_apb_ctlr;	/* _GIZMO_XBAR_APB_CTLR_0,	30h */
+	u32 gizmo_vcp_ahb_bridge;	/* _GIZMO_VCP_AHB_BRIDGE_0,	34h */
+	u32 reserved13[2];		/* 38h, 3ch */
+	u32 gizmo_nand;			/* _GIZMO_NAND_0,		40h */
+	u32 reserved15;			/* 44h */
+	u32 gizmo_sdmmc4;		/* _GIZMO_SDMMC4_0,		48h */
+	u32 reserved17;			/* 4ch */
+	u32 gizmo_se;			/* _GIZMO_SE_0,			50h */
+	u32 gizmo_tzram;		/* _GIZMO_TZRAM_0,		54h */
+	u32 reserved20[3];		/* 58h, 5ch, 60h */
+	u32 gizmo_bsev;			/* _GIZMO_BSEV_0,		64h */
+	u32 reserved22[3];		/* 68h, 6ch, 70h */
+	u32 gizmo_bsea;			/* _GIZMO_BSEA_0,		74h */
+	u32 gizmo_nor;			/* _GIZMO_NOR_0,		78h */
+	u32 gizmo_usb2;			/* _GIZMO_USB2_0,		7ch */
+	u32 gizmo_usb3;			/* _GIZMO_USB3_0,		80h */
+	u32 gizmo_sdmmc1;		/* _GIZMO_SDMMC1_0,		84h */
+	u32 gizmo_sdmmc2;		/* _GIZMO_SDMMC2_0,		88h */
+	u32 gizmo_sdmmc3;		/* _GIZMO_SDMMC3_0,		8ch */
+	u32 reserved30[13];		/* 90h ~ c0h */
+	u32 ahb_wrq_empty;		/* _AHB_WRQ_EMPTY_0,		c4h */
+	u32 reserved32[5];		/* c8h ~ d8h */
+	u32 ahb_mem_prefetch_cfg_x;	/* _AHB_MEM_PREFETCH_CFG_X_0,	dch */
+	u32 arbitration_xbar_ctrl;	/* _ARBITRATION_XBAR_CTRL_0,	e0h */
+	u32 ahb_mem_prefetch_cfg3;	/* _AHB_MEM_PREFETCH_CFG3_0,	e4h */
+	u32 ahb_mem_prefetch_cfg4;	/* _AHB_MEM_PREFETCH_CFG3_0,	e8h */
+	u32 avp_ppcs_rd_coh_status;	/* _AVP_PPCS_RD_COH_STATUS_0,	ech */
+	u32 ahb_mem_prefetch_cfg1;	/* _AHB_MEM_PREFETCH_CFG1_0,	f0h */
+	u32 ahb_mem_prefetch_cfg2;	/* _AHB_MEM_PREFETCH_CFG2_0,	f4h */
+	u32 ahbslvmem_status;		/* _AHBSLVMEM_STATUS_0, f8h */
+	/* _ARBITRATION_AHB_MEM_WRQUE_MST_ID_0, fch */
+	u32 arbitration_ahb_mem_wrque_mst_id;
+	u32 arbitration_cpu_abort_addr;	/* _ARBITRATION_CPU_ABORT_ADDR_0,100h */
+	u32 arbitration_cpu_abort_info;	/* _ARBITRATION_CPU_ABORT_INFO_0,104h */
+	u32 arbitration_cop_abort_addr;	/* _ARBITRATION_COP_ABORT_ADDR_0,108h */
+	u32 arbitration_cop_abort_info;	/* _ARBITRATION_COP_ABORT_INFO_0,10ch */
+	u32 reserved46[4];		/* 110h ~ 11ch */
+	u32 avpc_mccif_fifoctrl;	/* _AVPC_MCCIF_FIFOCTRL_0,	120h */
+	u32 timeout_wcoal_avpc;		/* _TIMEOUT_WCOAL_AVPC_0,	124h */
+	u32 mpcorelp_mccif_fifoctrl;	/* _MPCORELP_MCCIF_FIFOCTRL_0,	128h */
+	u32 mpcore_mccif_fifoctrl;	/* _MPCORE_MCCIF_FIFOCTRL_0,	12ch */
+	u32 axicif_fastsync_ctrl;	/* AXICIF_FASTSYNC_CTRL_0,	130h */
+	u32 axicif_fastsync_statistics;	/* _AXICIF_FASTSYNC_STATISTICS_0,134h */
+	/* _AXICIF_FASTSYNC0_CPUCLK_TO_MCCLK_0,	138h */
+	u32 axicif_fastsync0_cpuclk_to_mcclk;
+	/* _AXICIF_FASTSYNC1_CPUCLK_TO_MCCLK_0, 13ch */
+	u32 axicif_fastsync1_cpuclk_to_mcclk;
+	/* _AXICIF_FASTSYNC2_CPUCLK_TO_MCCLK_0, 140h */
+	u32 axicif_fastsync2_cpuclk_to_mcclk;
+	/* _AXICIF_FASTSYNC0_MCCLK_TO_CPUCLK_0, 144h */
+	u32 axicif_fastsync0_mcclk_to_cpuclk;
+	/* _AXICIF_FASTSYNC1_MCCLK_TO_CPUCLK_0, 148h */
+	u32 axicif_fastsync1_mcclk_to_cpuclk;
+	/* _AXICIF_FASTSYNC2_MCCLK_TO_CPUCLK_0, 14ch */
+	u32 axicif_fastsync2_mcclk_to_cpuclk;
+};
+
+#define PPSB_STOPCLK_ENABLE	(1 << 2)
+
+#define GIZ_ENABLE_SPLIT	(1 << 0)
+#define GIZ_ENB_FAST_REARB	(1 << 2)
+#define GIZ_DONT_SPLIT_AHB_WR	(1 << 7)
+
+#define GIZ_USB_IMMEDIATE	(1 << 18)
+
+/* AHB_ARBITRATION_XBAR_CTRL_0 0xe0 */
+#define ARBITRATION_XBAR_CTRL_PPSB_ENABLE	(1 << 2)
+
+#endif	/* _TEGRA124_AHB_H_ */
diff --git a/arch/arm/include/asm/arch-tegra124/clock-tables.h b/arch/arm/include/asm/arch-tegra124/clock-tables.h
new file mode 100644
index 0000000000..daf9a2b351
--- /dev/null
+++ b/arch/arm/include/asm/arch-tegra124/clock-tables.h
@@ -0,0 +1,496 @@
+/*
+ * (C) Copyright 2013
+ * NVIDIA Corporation <www.nvidia.com>
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+/* Tegra124 clock PLL tables */
+
+#ifndef _TEGRA124_CLOCK_TABLES_H_
+#define _TEGRA124_CLOCK_TABLES_H_
+
+/* The PLLs supported by the hardware */
+enum clock_id {
+	CLOCK_ID_FIRST,
+	CLOCK_ID_CGENERAL = CLOCK_ID_FIRST,
+	CLOCK_ID_MEMORY,
+	CLOCK_ID_PERIPH,
+	CLOCK_ID_AUDIO,
+	CLOCK_ID_USB,
+	CLOCK_ID_DISPLAY,
+
+	/* now the simple ones */
+	CLOCK_ID_FIRST_SIMPLE,
+	CLOCK_ID_XCPU = CLOCK_ID_FIRST_SIMPLE,
+	CLOCK_ID_EPCI,
+	CLOCK_ID_SFROM32KHZ,
+
+	/* These are the base clocks (inputs to the Tegra SoC) */
+	CLOCK_ID_32KHZ,
+	CLOCK_ID_OSC,
+
+	CLOCK_ID_COUNT,	/* number of PLLs */
+
+	/*
+	 * These are clock IDs that are used in table clock_source[][]
+	 * but will not be assigned as a clock source for any peripheral.
+	 */
+	CLOCK_ID_DISPLAY2,
+	CLOCK_ID_CGENERAL2,
+	CLOCK_ID_CGENERAL3,
+	CLOCK_ID_MEMORY2,
+	CLOCK_ID_SRC2,
+
+	CLOCK_ID_NONE = -1,
+};
+
+/* The clocks supported by the hardware */
+enum periph_id {
+	PERIPH_ID_FIRST,
+
+	/* Low word: 31:0 (DEVICES_L) */
+	PERIPH_ID_CPU = PERIPH_ID_FIRST,
+	PERIPH_ID_COP,
+	PERIPH_ID_TRIGSYS,
+	PERIPH_ID_ISPB,
+	PERIPH_ID_RESERVED4,
+	PERIPH_ID_TMR,
+	PERIPH_ID_UART1,
+	PERIPH_ID_UART2,
+
+	/* 8 */
+	PERIPH_ID_GPIO,
+	PERIPH_ID_SDMMC2,
+	PERIPH_ID_SPDIF,
+	PERIPH_ID_I2S1,
+	PERIPH_ID_I2C1,
+	PERIPH_ID_RESERVED13,
+	PERIPH_ID_SDMMC1,
+	PERIPH_ID_SDMMC4,
+
+	/* 16 */
+	PERIPH_ID_TCW,
+	PERIPH_ID_PWM,
+	PERIPH_ID_I2S2,
+	PERIPH_ID_RESERVED19,
+	PERIPH_ID_VI,
+	PERIPH_ID_RESERVED21,
+	PERIPH_ID_USBD,
+	PERIPH_ID_ISP,
+
+	/* 24 */
+	PERIPH_ID_RESERVED24,
+	PERIPH_ID_RESERVED25,
+	PERIPH_ID_DISP2,
+	PERIPH_ID_DISP1,
+	PERIPH_ID_HOST1X,
+	PERIPH_ID_VCP,
+	PERIPH_ID_I2S0,
+	PERIPH_ID_CACHE2,
+
+	/* Middle word: 63:32 (DEVICES_H) */
+	PERIPH_ID_MEM,
+	PERIPH_ID_AHBDMA,
+	PERIPH_ID_APBDMA,
+	PERIPH_ID_RESERVED35,
+	PERIPH_ID_RESERVED36,
+	PERIPH_ID_STAT_MON,
+	PERIPH_ID_RESERVED38,
+	PERIPH_ID_FUSE,
+
+	/* 40 */
+	PERIPH_ID_KFUSE,
+	PERIPH_ID_SBC1,
+	PERIPH_ID_SNOR,
+	PERIPH_ID_RESERVED43,
+	PERIPH_ID_SBC2,
+	PERIPH_ID_XIO,
+	PERIPH_ID_SBC3,
+	PERIPH_ID_I2C5,
+
+	/* 48 */
+	PERIPH_ID_DSI,
+	PERIPH_ID_RESERVED49,
+	PERIPH_ID_HSI,
+	PERIPH_ID_HDMI,
+	PERIPH_ID_CSI,
+	PERIPH_ID_RESERVED53,
+	PERIPH_ID_I2C2,
+	PERIPH_ID_UART3,
+
+	/* 56 */
+	PERIPH_ID_MIPI_CAL,
+	PERIPH_ID_EMC,
+	PERIPH_ID_USB2,
+	PERIPH_ID_USB3,
+	PERIPH_ID_RESERVED60,
+	PERIPH_ID_VDE,
+	PERIPH_ID_BSEA,
+	PERIPH_ID_BSEV,
+
+	/* Upper word 95:64 (DEVICES_U) */
+	PERIPH_ID_RESERVED64,
+	PERIPH_ID_UART4,
+	PERIPH_ID_UART5,
+	PERIPH_ID_I2C3,
+	PERIPH_ID_SBC4,
+	PERIPH_ID_SDMMC3,
+	PERIPH_ID_PCIE,
+	PERIPH_ID_OWR,
+
+	/* 72 */
+	PERIPH_ID_AFI,
+	PERIPH_ID_CORESIGHT,
+	PERIPH_ID_PCIEXCLK,
+	PERIPH_ID_AVPUCQ,
+	PERIPH_ID_LA,
+	PERIPH_ID_TRACECLKIN,
+	PERIPH_ID_SOC_THERM,
+	PERIPH_ID_DTV,
+
+	/* 80 */
+	PERIPH_ID_RESERVED80,
+	PERIPH_ID_I2CSLOW,
+	PERIPH_ID_DSIB,
+	PERIPH_ID_TSEC,
+	PERIPH_ID_RESERVED84,
+	PERIPH_ID_RESERVED85,
+	PERIPH_ID_RESERVED86,
+	PERIPH_ID_EMUCIF,
+
+	/* 88 */
+	PERIPH_ID_RESERVED88,
+	PERIPH_ID_XUSB_HOST,
+	PERIPH_ID_RESERVED90,
+	PERIPH_ID_MSENC,
+	PERIPH_ID_RESERVED92,
+	PERIPH_ID_RESERVED93,
+	PERIPH_ID_RESERVED94,
+	PERIPH_ID_XUSB_DEV,
+
+	PERIPH_ID_VW_FIRST,
+	/* V word: 31:0 */
+	PERIPH_ID_CPUG = PERIPH_ID_VW_FIRST,
+	PERIPH_ID_CPULP,
+	PERIPH_ID_V_RESERVED2,
+	PERIPH_ID_MSELECT,
+	PERIPH_ID_V_RESERVED4,
+	PERIPH_ID_I2S3,
+	PERIPH_ID_I2S4,
+	PERIPH_ID_I2C4,
+
+	/* 104 */
+	PERIPH_ID_SBC5,
+	PERIPH_ID_SBC6,
+	PERIPH_ID_AUDIO,
+	PERIPH_ID_APBIF,
+	PERIPH_ID_DAM0,
+	PERIPH_ID_DAM1,
+	PERIPH_ID_DAM2,
+	PERIPH_ID_HDA2CODEC2X,
+
+	/* 112 */
+	PERIPH_ID_ATOMICS,
+	PERIPH_ID_V_RESERVED17,
+	PERIPH_ID_V_RESERVED18,
+	PERIPH_ID_V_RESERVED19,
+	PERIPH_ID_V_RESERVED20,
+	PERIPH_ID_V_RESERVED21,
+	PERIPH_ID_V_RESERVED22,
+	PERIPH_ID_ACTMON,
+
+	/* 120 */
+	PERIPH_ID_EXTPERIPH1,
+	PERIPH_ID_EXTPERIPH2,
+	PERIPH_ID_EXTPERIPH3,
+	PERIPH_ID_OOB,
+	PERIPH_ID_SATA,
+	PERIPH_ID_HDA,
+	PERIPH_ID_V_RESERVED30,
+	PERIPH_ID_V_RESERVED31,
+
+	/* W word: 31:0 */
+	PERIPH_ID_HDA2HDMICODEC,
+	PERIPH_ID_SATACOLD,
+	PERIPH_ID_W_RESERVED2,
+	PERIPH_ID_W_RESERVED3,
+	PERIPH_ID_W_RESERVED4,
+	PERIPH_ID_W_RESERVED5,
+	PERIPH_ID_W_RESERVED6,
+	PERIPH_ID_W_RESERVED7,
+
+	/* 136 */
+	PERIPH_ID_CEC,
+	PERIPH_ID_W_RESERVED9,
+	PERIPH_ID_W_RESERVED10,
+	PERIPH_ID_W_RESERVED11,
+	PERIPH_ID_W_RESERVED12,
+	PERIPH_ID_W_RESERVED13,
+	PERIPH_ID_XUSB_PADCTL,
+	PERIPH_ID_W_RESERVED15,
+
+	/* 144 */
+	PERIPH_ID_W_RESERVED16,
+	PERIPH_ID_W_RESERVED17,
+	PERIPH_ID_W_RESERVED18,
+	PERIPH_ID_W_RESERVED19,
+	PERIPH_ID_W_RESERVED20,
+	PERIPH_ID_ENTROPY,
+	PERIPH_ID_DDS,
+	PERIPH_ID_W_RESERVED23,
+
+	/* 152 */
+	PERIPH_ID_DP2,
+	PERIPH_ID_AMX0,
+	PERIPH_ID_ADX0,
+	PERIPH_ID_DVFS,
+	PERIPH_ID_XUSB_SS,
+	PERIPH_ID_W_RESERVED29,
+	PERIPH_ID_W_RESERVED30,
+	PERIPH_ID_W_RESERVED31,
+
+	PERIPH_ID_X_FIRST,
+	/* X word: 31:0 */
+	PERIPH_ID_SPARE = PERIPH_ID_X_FIRST,
+	PERIPH_ID_X_RESERVED1,
+	PERIPH_ID_X_RESERVED2,
+	PERIPH_ID_X_RESERVED3,
+	PERIPH_ID_CAM_MCLK,
+	PERIPH_ID_CAM_MCLK2,
+	PERIPH_ID_I2C6,
+	PERIPH_ID_X_RESERVED7,
+
+	/* 168 */
+	PERIPH_ID_X_RESERVED8,
+	PERIPH_ID_X_RESERVED9,
+	PERIPH_ID_X_RESERVED10,
+	PERIPH_ID_VIM2_CLK,
+	PERIPH_ID_X_RESERVED12,
+	PERIPH_ID_X_RESERVED13,
+	PERIPH_ID_EMC_DLL,
+	PERIPH_ID_X_RESERVED15,
+
+	/* 176 */
+	PERIPH_ID_HDMI_AUDIO,
+	PERIPH_ID_CLK72MHZ,
+	PERIPH_ID_VIC,
+	PERIPH_ID_X_RESERVED19,
+	PERIPH_ID_ADX1,
+	PERIPH_ID_DPAUX,
+	PERIPH_ID_SOR0,
+	PERIPH_ID_X_RESERVED23,
+
+	/* 184 */
+	PERIPH_ID_GPU,
+	PERIPH_ID_AMX1,
+	PERIPH_ID_X_RESERVED26,
+	PERIPH_ID_X_RESERVED27,
+	PERIPH_ID_X_RESERVED28,
+	PERIPH_ID_X_RESERVED29,
+	PERIPH_ID_X_RESERVED30,
+	PERIPH_ID_X_RESERVED31,
+
+	PERIPH_ID_COUNT,
+	PERIPH_ID_NONE = -1,
+};
+
+enum pll_out_id {
+	PLL_OUT1,
+	PLL_OUT2,
+	PLL_OUT3,
+	PLL_OUT4
+};
+
+/*
+ * Clock peripheral IDs which sadly don't match up with PERIPH_ID. we want
+ * callers to use the PERIPH_ID for all access to peripheral clocks to avoid
+ * confusion bewteen PERIPH_ID_... and PERIPHC_...
+ *
+ * We don't call this CLOCK_PERIPH_ID or PERIPH_CLOCK_ID as it would just be
+ * confusing.
+ */
+enum periphc_internal_id {
+	/* 0x00 */
+	PERIPHC_I2S1,
+	PERIPHC_I2S2,
+	PERIPHC_SPDIF_OUT,
+	PERIPHC_SPDIF_IN,
+	PERIPHC_PWM,
+	PERIPHC_05h,
+	PERIPHC_SBC2,
+	PERIPHC_SBC3,
+
+	/* 0x08 */
+	PERIPHC_08h,
+	PERIPHC_I2C1,
+	PERIPHC_I2C5,
+	PERIPHC_0bh,
+	PERIPHC_0ch,
+	PERIPHC_SBC1,
+	PERIPHC_DISP1,
+	PERIPHC_DISP2,
+
+	/* 0x10 */
+	PERIPHC_10h,
+	PERIPHC_11h,
+	PERIPHC_VI,
+	PERIPHC_13h,
+	PERIPHC_SDMMC1,
+	PERIPHC_SDMMC2,
+	PERIPHC_G3D,
+	PERIPHC_G2D,
+
+	/* 0x18 */
+	PERIPHC_18h,
+	PERIPHC_SDMMC4,
+	PERIPHC_VFIR,
+	PERIPHC_1Bh,
+	PERIPHC_1Ch,
+	PERIPHC_HSI,
+	PERIPHC_UART1,
+	PERIPHC_UART2,
+
+	/* 0x20 */
+	PERIPHC_HOST1X,
+	PERIPHC_21h,
+	PERIPHC_22h,
+	PERIPHC_HDMI,
+	PERIPHC_24h,
+	PERIPHC_25h,
+	PERIPHC_I2C2,
+	PERIPHC_EMC,
+
+	/* 0x28 */
+	PERIPHC_UART3,
+	PERIPHC_29h,
+	PERIPHC_VI_SENSOR,
+	PERIPHC_2bh,
+	PERIPHC_2ch,
+	PERIPHC_SBC4,
+	PERIPHC_I2C3,
+	PERIPHC_SDMMC3,
+
+	/* 0x30 */
+	PERIPHC_UART4,
+	PERIPHC_UART5,
+	PERIPHC_VDE,
+	PERIPHC_OWR,
+	PERIPHC_NOR,
+	PERIPHC_CSITE,
+	PERIPHC_I2S0,
+	PERIPHC_DTV,
+
+	/* 0x38 */
+	PERIPHC_38h,
+	PERIPHC_39h,
+	PERIPHC_3ah,
+	PERIPHC_3bh,
+	PERIPHC_MSENC,
+	PERIPHC_TSEC,
+	PERIPHC_3eh,
+	PERIPHC_OSC,
+
+	PERIPHC_VW_FIRST,
+	/* 0x40 */
+	PERIPHC_40h = PERIPHC_VW_FIRST,
+	PERIPHC_MSELECT,
+	PERIPHC_TSENSOR,
+	PERIPHC_I2S3,
+	PERIPHC_I2S4,
+	PERIPHC_I2C4,
+	PERIPHC_SBC5,
+	PERIPHC_SBC6,
+
+	/* 0x48 */
+	PERIPHC_AUDIO,
+	PERIPHC_49h,
+	PERIPHC_DAM0,
+	PERIPHC_DAM1,
+	PERIPHC_DAM2,
+	PERIPHC_HDA2CODEC2X,
+	PERIPHC_ACTMON,
+	PERIPHC_EXTPERIPH1,
+
+	/* 0x50 */
+	PERIPHC_EXTPERIPH2,
+	PERIPHC_EXTPERIPH3,
+	PERIPHC_52h,
+	PERIPHC_I2CSLOW,
+	PERIPHC_SYS,
+	PERIPHC_55h,
+	PERIPHC_56h,
+	PERIPHC_57h,
+
+	/* 0x58 */
+	PERIPHC_58h,
+	PERIPHC_59h,
+	PERIPHC_5ah,
+	PERIPHC_5bh,
+	PERIPHC_SATAOOB,
+	PERIPHC_SATA,
+	PERIPHC_HDA,		/* 0x428 */
+	PERIPHC_5fh,
+
+	PERIPHC_X_FIRST,
+	/* 0x60 */
+	PERIPHC_XUSB_CORE_HOST = PERIPHC_X_FIRST,	/* 0x600 */
+	PERIPHC_XUSB_FALCON,
+	PERIPHC_XUSB_FS,
+	PERIPHC_XUSB_CORE_DEV,
+	PERIPHC_XUSB_SS,
+	PERIPHC_CILAB,
+	PERIPHC_CILCD,
+	PERIPHC_CILE,
+
+	/* 0x68 */
+	PERIPHC_DSIA_LP,
+	PERIPHC_DSIB_LP,
+	PERIPHC_ENTROPY,
+	PERIPHC_DVFS_REF,
+	PERIPHC_DVFS_SOC,
+	PERIPHC_TRACECLKIN,
+	PERIPHC_ADX0,
+	PERIPHC_AMX0,
+
+	/* 0x70 */
+	PERIPHC_EMC_LATENCY,
+	PERIPHC_SOC_THERM,
+	PERIPHC_72h,
+	PERIPHC_73h,
+	PERIPHC_74h,
+	PERIPHC_75h,
+	PERIPHC_VI_SENSOR2,
+	PERIPHC_I2C6,
+
+	/* 0x78 */
+	PERIPHC_78h,
+	PERIPHC_EMC_DLL,
+	PERIPHC_HDMI_AUDIO,
+	PERIPHC_CLK72MHZ,
+	PERIPHC_ADX1,
+	PERIPHC_AMX1,
+	PERIPHC_VIC,
+	PERIPHC_7fh,
+
+	PERIPHC_COUNT,
+
+	PERIPHC_NONE = -1,
+};
+
+/* Converts a clock number to a clock register: 0=L, 1=H, 2=U, 0=V, 1=W */
+#define PERIPH_REG(id) \
+	(id < PERIPH_ID_VW_FIRST) ? \
+		((id) >> 5) : ((id - PERIPH_ID_VW_FIRST) >> 5)
+
+/* Mask value for a clock (within PERIPH_REG(id)) */
+#define PERIPH_MASK(id) (1 << ((id) & 0x1f))
+
+/* return 1 if a PLL ID is in range */
+#define clock_id_is_pll(id) ((id) >= CLOCK_ID_FIRST && (id) < CLOCK_ID_COUNT)
+
+/* return 1 if a peripheral ID is in range */
+#define clock_periph_id_isvalid(id) ((id) >= PERIPH_ID_FIRST && \
+		(id) < PERIPH_ID_COUNT)
+
+#endif	/* _TEGRA124_CLOCK_TABLES_H_ */
diff --git a/arch/arm/include/asm/arch-tegra124/clock.h b/arch/arm/include/asm/arch-tegra124/clock.h
new file mode 100644
index 0000000000..8e39d21a7b
--- /dev/null
+++ b/arch/arm/include/asm/arch-tegra124/clock.h
@@ -0,0 +1,19 @@
+/*
+ * (C) Copyright 2010-2013
+ * NVIDIA Corporation <www.nvidia.com>
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+/* Tegra124 clock control definitions */
+
+#ifndef _TEGRA124_CLOCK_H_
+#define _TEGRA124_CLOCK_H_
+
+#include <asm/arch-tegra/clock.h>
+
+/* CLK_RST_CONTROLLER_OSC_CTRL_0 */
+#define OSC_FREQ_SHIFT          28
+#define OSC_FREQ_MASK           (0xF << OSC_FREQ_SHIFT)
+
+#endif	/* _TEGRA124_CLOCK_H_ */
diff --git a/arch/arm/include/asm/arch-tegra124/flow.h b/arch/arm/include/asm/arch-tegra124/flow.h
new file mode 100644
index 0000000000..0db1881bc6
--- /dev/null
+++ b/arch/arm/include/asm/arch-tegra124/flow.h
@@ -0,0 +1,40 @@
+/*
+ * (C) Copyright 2010-2013
+ * NVIDIA Corporation <www.nvidia.com>
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#ifndef _TEGRA124_FLOW_H_
+#define _TEGRA124_FLOW_H_
+
+struct flow_ctlr {
+	u32 halt_cpu_events;	/* offset 0x00 */
+	u32 halt_cop_events;	/* offset 0x04 */
+	u32 cpu_csr;		/* offset 0x08 */
+	u32 cop_csr;		/* offset 0x0c */
+	u32 xrq_events;		/* offset 0x10 */
+	u32 halt_cpu1_events;	/* offset 0x14 */
+	u32 cpu1_csr;		/* offset 0x18 */
+	u32 halt_cpu2_events;	/* offset 0x1c */
+	u32 cpu2_csr;		/* offset 0x20 */
+	u32 halt_cpu3_events;	/* offset 0x24 */
+	u32 cpu3_csr;		/* offset 0x28 */
+	u32 cluster_control;	/* offset 0x2c */
+	u32 halt_cop1_events;	/* offset 0x30 */
+	u32 halt_cop1_csr;	/* offset 0x34 */
+	u32 cpu_pwr_csr;	/* offset 0x38 */
+	u32 mpid;		/* offset 0x3c */
+	u32 ram_repair;		/* offset 0x40 */
+};
+
+/* HALT_COP_EVENTS_0, 0x04 */
+#define EVENT_MSEC		(1 << 24)
+#define EVENT_USEC		(1 << 25)
+#define EVENT_JTAG		(1 << 28)
+#define EVENT_MODE_STOP		(2 << 29)
+
+/* FLOW_CTLR_CLUSTER_CONTROL_0 0x2c */
+#define ACTIVE_LP		(1 << 0)
+
+#endif	/*  _TEGRA124_FLOW_H_ */
diff --git a/arch/arm/include/asm/arch-tegra124/funcmux.h b/arch/arm/include/asm/arch-tegra124/funcmux.h
new file mode 100644
index 0000000000..df94d135f8
--- /dev/null
+++ b/arch/arm/include/asm/arch-tegra124/funcmux.h
@@ -0,0 +1,23 @@
+/*
+ * (C) Copyright 2013
+ * NVIDIA Corporation <www.nvidia.com>
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+/* Tegra124 high-level function multiplexing */
+
+#ifndef _TEGRA124_FUNCMUX_H_
+#define _TEGRA124_FUNCMUX_H_
+
+#include <asm/arch-tegra/funcmux.h>
+
+/* Configs supported by the func mux */
+enum {
+	FUNCMUX_DEFAULT = 0,	/* default config */
+
+	/* UART configs */
+	FUNCMUX_UART1_KBC = 0,
+	FUNCMUX_UART4_GPIO = 0,
+};
+#endif	/* _TEGRA124_FUNCMUX_H_ */
diff --git a/arch/arm/include/asm/arch-tegra124/gp_padctrl.h b/arch/arm/include/asm/arch-tegra124/gp_padctrl.h
new file mode 100644
index 0000000000..440cbbfa3e
--- /dev/null
+++ b/arch/arm/include/asm/arch-tegra124/gp_padctrl.h
@@ -0,0 +1,74 @@
+/*
+ * (C) Copyright 2010-2013
+ * NVIDIA Corporation <www.nvidia.com>
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#ifndef _TEGRA124_GP_PADCTRL_H_
+#define _TEGRA124_GP_PADCTRL_H_
+
+#include <asm/arch-tegra/gp_padctrl.h>
+
+/* APB_MISC_GP and padctrl registers */
+struct apb_misc_gp_ctlr {
+	u32	modereg;	/* 0x00: APB_MISC_GP_MODEREG */
+	u32	hidrev;		/* 0x04: APB_MISC_GP_HIDREV */
+	u32	reserved0[22];	/* 0x08 - 0x5C: */
+	u32	emu_revid;	/* 0x60: APB_MISC_GP_EMU_REVID */
+	u32	xactor_scratch;	/* 0x64: APB_MISC_GP_XACTOR_SCRATCH */
+	u32	aocfg1;		/* 0x68: APB_MISC_GP_AOCFG1PADCTRL */
+	u32	aocfg2;		/* 0x6C: APB_MISC_GP_AOCFG2PADCTRL */
+	u32	atcfg1;		/* 0x70: APB_MISC_GP_ATCFG1PADCTRL */
+	u32	atcfg2;		/* 0x74: APB_MISC_GP_ATCFG2PADCTRL */
+	u32	atcfg3;		/* 0x78: APB_MISC_GP_ATCFG3PADCTRL */
+	u32	atcfg4;		/* 0x7C: APB_MISC_GP_ATCFG4PADCTRL */
+	u32	atcfg5;		/* 0x80: APB_MISC_GP_ATCFG5PADCTRL */
+	u32	cdev1cfg;	/* 0x84: APB_MISC_GP_CDEV1CFGPADCTRL */
+	u32	cdev2cfg;	/* 0x88: APB_MISC_GP_CDEV2CFGPADCTRL */
+	u32	reserved1;	/* 0x8C: */
+	u32	dap1cfg;	/* 0x90: APB_MISC_GP_DAP1CFGPADCTRL */
+	u32	dap2cfg;	/* 0x94: APB_MISC_GP_DAP2CFGPADCTRL */
+	u32	dap3cfg;	/* 0x98: APB_MISC_GP_DAP3CFGPADCTRL */
+	u32	dap4cfg;	/* 0x9C: APB_MISC_GP_DAP4CFGPADCTRL */
+	u32	dbgcfg;		/* 0xA0: APB_MISC_GP_DBGCFGPADCTRL */
+	u32	reserved2[3];	/* 0xA4 - 0xAC: */
+	u32	sdio3cfg;	/* 0xB0: APB_MISC_GP_SDIO3CFGPADCTRL */
+	u32	spicfg;		/* 0xB4: APB_MISC_GP_SPICFGPADCTRL */
+	u32	uaacfg;		/* 0xB8: APB_MISC_GP_UAACFGPADCTRL */
+	u32	uabcfg;		/* 0xBC: APB_MISC_GP_UABCFGPADCTRL */
+	u32	uart2cfg;	/* 0xC0: APB_MISC_GP_UART2CFGPADCTRL */
+	u32	uart3cfg;	/* 0xC4: APB_MISC_GP_UART3CFGPADCTRL */
+	u32	reserved3[9];	/* 0xC8-0xE8: */
+	u32	sdio1cfg;	/* 0xEC: APB_MISC_GP_SDIO1CFGPADCTRL */
+	u32	reserved4[3];	/* 0xF0-0xF8: */
+	u32	ddccfg;		/* 0xFC: APB_MISC_GP_DDCCFGPADCTRL */
+	u32	gmacfg;		/* 0x100: APB_MISC_GP_GMACFGPADCTRL */
+	u32	reserved5[3];	/* 0x104-0x10C: */
+	u32	gmecfg;		/* 0x110: APB_MISC_GP_GMECFGPADCTRL */
+	u32	gmfcfg;		/* 0x114: APB_MISC_GP_GMFCFGPADCTRL */
+	u32	gmgcfg;		/* 0x118: APB_MISC_GP_GMGCFGPADCTRL */
+	u32	gmhcfg;		/* 0x11C: APB_MISC_GP_GMHCFGPADCTRL */
+	u32	owrcfg;		/* 0x120: APB_MISC_GP_OWRCFGPADCTRL */
+	u32	uadcfg;		/* 0x124: APB_MISC_GP_UADCFGPADCTRL */
+	u32	reserved6;	/* 0x128: */
+	u32	dev3cfg;	/* 0x12C: APB_MISC_GP_DEV3CFGPADCTRL */
+	u32	reserved7[2];	/* 0x130 - 0x134: */
+	u32	ceccfg;		/* 0x138: APB_MISC_GP_CECCFGPADCTRL */
+	u32	reserved8[22];	/* 0x13C - 0x190: */
+	u32	atcfg6;		/* 0x194: APB_MISC_GP_ATCFG6PADCTRL */
+	u32	dap5cfg;	/* 0x198: APB_MISC_GP_DAP5CFGPADCTRL */
+	u32	vbuscfg;	/* 0x19C: APB_MISC_GP_USBVBUSENCFGPADCTRL */
+	u32	aocfg3;		/* 0x1A0: APB_MISC_GP_AOCFG3PADCTRL */
+	u32	hvccfg0;	/* 0x1A4: APB_MISC_GP_HVCCFG0PADCTRL */
+	u32	sdio4cfg;	/* 0x1A8: APB_MISC_GP_SDIO4CFGPADCTRL */
+	u32	aocfg0;		/* 0x1AC: APB_MISC_GP_AOCFG0PADCTRL */
+};
+
+/* SDMMC1/3 settings from section 27.5 of T114 TRM */
+#define SDIOCFG_DRVUP_SLWF	0
+#define SDIOCFG_DRVDN_SLWR	0
+#define SDIOCFG_DRVUP		0x24
+#define SDIOCFG_DRVDN		0x14
+
+#endif	/* _TEGRA124_GP_PADCTRL_H_ */
diff --git a/arch/arm/include/asm/arch-tegra124/gpio.h b/arch/arm/include/asm/arch-tegra124/gpio.h
new file mode 100644
index 0000000000..1a6dcb8715
--- /dev/null
+++ b/arch/arm/include/asm/arch-tegra124/gpio.h
@@ -0,0 +1,303 @@
+/*
+ * (C) Copyright 2013
+ * NVIDIA Corporation <www.nvidia.com>
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#ifndef _TEGRA124_GPIO_H_
+#define _TEGRA124_GPIO_H_
+
+/*
+ * The Tegra124 GPIO controller has 256 GPIOS in 8 banks of 4 ports,
+ * each with 8 GPIOs.
+ */
+#define TEGRA_GPIO_PORTS	4	/* number of ports per bank */
+#define TEGRA_GPIO_BANKS	8	/* number of banks */
+
+#include <asm/arch-tegra/gpio.h>
+
+/* GPIO Controller registers for a single bank */
+struct gpio_ctlr_bank {
+	uint gpio_config[TEGRA_GPIO_PORTS];
+	uint gpio_dir_out[TEGRA_GPIO_PORTS];
+	uint gpio_out[TEGRA_GPIO_PORTS];
+	uint gpio_in[TEGRA_GPIO_PORTS];
+	uint gpio_int_status[TEGRA_GPIO_PORTS];
+	uint gpio_int_enable[TEGRA_GPIO_PORTS];
+	uint gpio_int_level[TEGRA_GPIO_PORTS];
+	uint gpio_int_clear[TEGRA_GPIO_PORTS];
+	uint gpio_masked_config[TEGRA_GPIO_PORTS];
+	uint gpio_masked_dir_out[TEGRA_GPIO_PORTS];
+	uint gpio_masked_out[TEGRA_GPIO_PORTS];
+	uint gpio_masked_in[TEGRA_GPIO_PORTS];
+	uint gpio_masked_int_status[TEGRA_GPIO_PORTS];
+	uint gpio_masked_int_enable[TEGRA_GPIO_PORTS];
+	uint gpio_masked_int_level[TEGRA_GPIO_PORTS];
+	uint gpio_masked_int_clear[TEGRA_GPIO_PORTS];
+};
+
+struct gpio_ctlr {
+	struct gpio_ctlr_bank gpio_bank[TEGRA_GPIO_BANKS];
+};
+
+enum gpio_pin {
+	GPIO_PA0 = 0,	/* pin 0 */
+	GPIO_PA1,
+	GPIO_PA2,
+	GPIO_PA3,
+	GPIO_PA4,
+	GPIO_PA5,
+	GPIO_PA6,
+	GPIO_PA7,
+	GPIO_PB0,	/* pin 8 */
+	GPIO_PB1,
+	GPIO_PB2,
+	GPIO_PB3,
+	GPIO_PB4,
+	GPIO_PB5,
+	GPIO_PB6,
+	GPIO_PB7,
+	GPIO_PC0,	/* pin 16 */
+	GPIO_PC1,
+	GPIO_PC2,
+	GPIO_PC3,
+	GPIO_PC4,
+	GPIO_PC5,
+	GPIO_PC6,
+	GPIO_PC7,
+	GPIO_PD0,	/* pin 24 */
+	GPIO_PD1,
+	GPIO_PD2,
+	GPIO_PD3,
+	GPIO_PD4,
+	GPIO_PD5,
+	GPIO_PD6,
+	GPIO_PD7,
+	GPIO_PE0,	/* pin 32 */
+	GPIO_PE1,
+	GPIO_PE2,
+	GPIO_PE3,
+	GPIO_PE4,
+	GPIO_PE5,
+	GPIO_PE6,
+	GPIO_PE7,
+	GPIO_PF0,	/* pin 40 */
+	GPIO_PF1,
+	GPIO_PF2,
+	GPIO_PF3,
+	GPIO_PF4,
+	GPIO_PF5,
+	GPIO_PF6,
+	GPIO_PF7,
+	GPIO_PG0,	/* pin 48 */
+	GPIO_PG1,
+	GPIO_PG2,
+	GPIO_PG3,
+	GPIO_PG4,
+	GPIO_PG5,
+	GPIO_PG6,
+	GPIO_PG7,
+	GPIO_PH0,	/* pin 56 */
+	GPIO_PH1,
+	GPIO_PH2,
+	GPIO_PH3,
+	GPIO_PH4,
+	GPIO_PH5,
+	GPIO_PH6,
+	GPIO_PH7,
+	GPIO_PI0,	/* pin 64 */
+	GPIO_PI1,
+	GPIO_PI2,
+	GPIO_PI3,
+	GPIO_PI4,
+	GPIO_PI5,
+	GPIO_PI6,
+	GPIO_PI7,
+	GPIO_PJ0,	/* pin 72 */
+	GPIO_PJ1,
+	GPIO_PJ2,
+	GPIO_PJ3,
+	GPIO_PJ4,
+	GPIO_PJ5,
+	GPIO_PJ6,
+	GPIO_PJ7,
+	GPIO_PK0,	/* pin 80 */
+	GPIO_PK1,
+	GPIO_PK2,
+	GPIO_PK3,
+	GPIO_PK4,
+	GPIO_PK5,
+	GPIO_PK6,
+	GPIO_PK7,
+	GPIO_PL0,	/* pin 88 */
+	GPIO_PL1,
+	GPIO_PL2,
+	GPIO_PL3,
+	GPIO_PL4,
+	GPIO_PL5,
+	GPIO_PL6,
+	GPIO_PL7,
+	GPIO_PM0,	/* pin 96 */
+	GPIO_PM1,
+	GPIO_PM2,
+	GPIO_PM3,
+	GPIO_PM4,
+	GPIO_PM5,
+	GPIO_PM6,
+	GPIO_PM7,
+	GPIO_PN0,	/* pin 104 */
+	GPIO_PN1,
+	GPIO_PN2,
+	GPIO_PN3,
+	GPIO_PN4,
+	GPIO_PN5,
+	GPIO_PN6,
+	GPIO_PN7,
+	GPIO_PO0,	/* pin 112 */
+	GPIO_PO1,
+	GPIO_PO2,
+	GPIO_PO3,
+	GPIO_PO4,
+	GPIO_PO5,
+	GPIO_PO6,
+	GPIO_PO7,
+	GPIO_PP0,	/* pin 120 */
+	GPIO_PP1,
+	GPIO_PP2,
+	GPIO_PP3,
+	GPIO_PP4,
+	GPIO_PP5,
+	GPIO_PP6,
+	GPIO_PP7,
+	GPIO_PQ0,	/* pin 128 */
+	GPIO_PQ1,
+	GPIO_PQ2,
+	GPIO_PQ3,
+	GPIO_PQ4,
+	GPIO_PQ5,
+	GPIO_PQ6,
+	GPIO_PQ7,
+	GPIO_PR0,	/* pin 136 */
+	GPIO_PR1,
+	GPIO_PR2,
+	GPIO_PR3,
+	GPIO_PR4,
+	GPIO_PR5,
+	GPIO_PR6,
+	GPIO_PR7,
+	GPIO_PS0,	/* pin 144 */
+	GPIO_PS1,
+	GPIO_PS2,
+	GPIO_PS3,
+	GPIO_PS4,
+	GPIO_PS5,
+	GPIO_PS6,
+	GPIO_PS7,
+	GPIO_PT0,	/* pin 152 */
+	GPIO_PT1,
+	GPIO_PT2,
+	GPIO_PT3,
+	GPIO_PT4,
+	GPIO_PT5,
+	GPIO_PT6,
+	GPIO_PT7,
+	GPIO_PU0,	/* pin 160 */
+	GPIO_PU1,
+	GPIO_PU2,
+	GPIO_PU3,
+	GPIO_PU4,
+	GPIO_PU5,
+	GPIO_PU6,
+	GPIO_PU7,
+	GPIO_PV0,	/* pin 168 */
+	GPIO_PV1,
+	GPIO_PV2,
+	GPIO_PV3,
+	GPIO_PV4,
+	GPIO_PV5,
+	GPIO_PV6,
+	GPIO_PV7,
+	GPIO_PW0,	/* pin 176 */
+	GPIO_PW1,
+	GPIO_PW2,
+	GPIO_PW3,
+	GPIO_PW4,
+	GPIO_PW5,
+	GPIO_PW6,
+	GPIO_PW7,
+	GPIO_PX0,	/* pin 184 */
+	GPIO_PX1,
+	GPIO_PX2,
+	GPIO_PX3,
+	GPIO_PX4,
+	GPIO_PX5,
+	GPIO_PX6,
+	GPIO_PX7,
+	GPIO_PY0,	/* pin 192 */
+	GPIO_PY1,
+	GPIO_PY2,
+	GPIO_PY3,
+	GPIO_PY4,
+	GPIO_PY5,
+	GPIO_PY6,
+	GPIO_PY7,
+	GPIO_PZ0,	/* pin 200 */
+	GPIO_PZ1,
+	GPIO_PZ2,
+	GPIO_PZ3,
+	GPIO_PZ4,
+	GPIO_PZ5,
+	GPIO_PZ6,
+	GPIO_PZ7,
+	GPIO_PAA0,	/* pin 208 */
+	GPIO_PAA1,
+	GPIO_PAA2,
+	GPIO_PAA3,
+	GPIO_PAA4,
+	GPIO_PAA5,
+	GPIO_PAA6,
+	GPIO_PAA7,
+	GPIO_PBB0,	/* pin 216 */
+	GPIO_PBB1,
+	GPIO_PBB2,
+	GPIO_PBB3,
+	GPIO_PBB4,
+	GPIO_PBB5,
+	GPIO_PBB6,
+	GPIO_PBB7,
+	GPIO_PCC0,	/* pin 224 */
+	GPIO_PCC1,
+	GPIO_PCC2,
+	GPIO_PCC3,
+	GPIO_PCC4,
+	GPIO_PCC5,
+	GPIO_PCC6,
+	GPIO_PCC7,
+	GPIO_PDD0,	/* pin 232 */
+	GPIO_PDD1,
+	GPIO_PDD2,
+	GPIO_PDD3,
+	GPIO_PDD4,
+	GPIO_PDD5,
+	GPIO_PDD6,
+	GPIO_PDD7,
+	GPIO_PEE0,	/* pin 240 */
+	GPIO_PEE1,
+	GPIO_PEE2,
+	GPIO_PEE3,
+	GPIO_PEE4,
+	GPIO_PEE5,
+	GPIO_PEE6,
+	GPIO_PEE7,
+	GPIO_PFF0,	/* pin 248 */
+	GPIO_PFF1,
+	GPIO_PFF2,
+	GPIO_PFF3,
+	GPIO_PFF4,
+	GPIO_PFF5,
+	GPIO_PFF6,
+	GPIO_PFF7,	/* pin 255 */
+};
+
+#endif	/* _TEGRA124_GPIO_H_ */
diff --git a/arch/arm/include/asm/arch-tegra124/hardware.h b/arch/arm/include/asm/arch-tegra124/hardware.h
new file mode 100644
index 0000000000..114fce8ada
--- /dev/null
+++ b/arch/arm/include/asm/arch-tegra124/hardware.h
@@ -0,0 +1,16 @@
+/*
+ * (C) Copyright 2013
+ * NVIDIA Corporation <www.nvidia.com>
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#ifndef _TEGRA124_HARDWARE_H_
+#define _TEGRA124_HARDWARE_H_
+
+/*
+ * Include Tegra-specific hardware definitions
+ * Nothing needed currently for Tegra124
+ */
+
+#endif /* _TEGRA124_HARDWARE_H_ */
diff --git a/arch/arm/include/asm/arch-tegra124/pinmux.h b/arch/arm/include/asm/arch-tegra124/pinmux.h
new file mode 100644
index 0000000000..9662e2b8aa
--- /dev/null
+++ b/arch/arm/include/asm/arch-tegra124/pinmux.h
@@ -0,0 +1,620 @@
+/*
+ * (C) Copyright 2013
+ * NVIDIA Corporation <www.nvidia.com>
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#ifndef _TEGRA124_PINMUX_H_
+#define _TEGRA124_PINMUX_H_
+
+/*
+ * Pin groups which we adjust. There are three basic attributes of each pin
+ * group which use this enum:
+ *
+ *	- function
+ *	- pullup / pulldown
+ *	- tristate or normal
+ */
+enum pmux_pingrp {
+	PINGRP_ULPI_DATA0 = 0,  /* offset 0x3000 */
+	PINGRP_ULPI_DATA1,
+	PINGRP_ULPI_DATA2,
+	PINGRP_ULPI_DATA3,
+	PINGRP_ULPI_DATA4,
+	PINGRP_ULPI_DATA5,
+	PINGRP_ULPI_DATA6,
+	PINGRP_ULPI_DATA7,
+	PINGRP_ULPI_CLK,
+	PINGRP_ULPI_DIR,
+	PINGRP_ULPI_NXT,
+	PINGRP_ULPI_STP,
+	PINGRP_DAP3_FS,
+	PINGRP_DAP3_DIN,
+	PINGRP_DAP3_DOUT,
+	PINGRP_DAP3_SCLK,
+	PINGRP_GPIO_PV0,
+	PINGRP_GPIO_PV1,
+	PINGRP_SDMMC1_CLK,
+	PINGRP_SDMMC1_CMD,
+	PINGRP_SDMMC1_DAT3,
+	PINGRP_SDMMC1_DAT2,
+	PINGRP_SDMMC1_DAT1,
+	PINGRP_SDMMC1_DAT0,
+	PINGRP_CLK2_OUT = PINGRP_SDMMC1_DAT0 + 3,
+	PINGRP_CLK2_REQ,
+	PINGRP_HDMI_INT = PINGRP_CLK2_REQ + 41,
+	PINGRP_DDC_SCL,
+	PINGRP_DDC_SDA,
+	PINGRP_UART2_RXD = PINGRP_DDC_SDA + 19,
+	PINGRP_UART2_TXD,
+	PINGRP_UART2_RTS_N,
+	PINGRP_UART2_CTS_N,
+	PINGRP_UART3_TXD,
+	PINGRP_UART3_RXD,
+	PINGRP_UART3_CTS_N,
+	PINGRP_UART3_RTS_N,
+	PINGRP_GPIO_PU0,
+	PINGRP_GPIO_PU1,
+	PINGRP_GPIO_PU2,
+	PINGRP_GPIO_PU3,
+	PINGRP_GPIO_PU4,
+	PINGRP_GPIO_PU5,
+	PINGRP_GPIO_PU6,
+	PINGRP_GEN1_I2C_SDA,
+	PINGRP_GEN1_I2C_SCL,
+	PINGRP_DAP4_FS,
+	PINGRP_DAP4_DIN,
+	PINGRP_DAP4_DOUT,
+	PINGRP_DAP4_SCLK,
+	PINGRP_CLK3_OUT,
+	PINGRP_CLK3_REQ,
+	/* Renamed on Tegra124, from GMI_xx to GPIO_Pxx */
+	PINGRP_GPIO_PC7,			/* offset 0x31c0 */
+	PINGRP_GPIO_PI5,
+	PINGRP_GPIO_PI7,
+	PINGRP_GPIO_PK0,
+	PINGRP_GPIO_PK1,
+	PINGRP_GPIO_PJ0,
+	PINGRP_GPIO_PJ2,
+	PINGRP_GPIO_PK3,
+	PINGRP_GPIO_PK4,
+	PINGRP_GPIO_PK2,
+	PINGRP_GPIO_PI3,
+	PINGRP_GPIO_PI6,
+	PINGRP_GPIO_PG0,
+	PINGRP_GPIO_PG1,
+	PINGRP_GPIO_PG2,
+	PINGRP_GPIO_PG3,
+	PINGRP_GPIO_PG4,
+	PINGRP_GPIO_PG5,
+	PINGRP_GPIO_PG6,
+	PINGRP_GPIO_PG7,
+	PINGRP_GPIO_PH0,
+	PINGRP_GPIO_PH1,
+	PINGRP_GPIO_PH2,
+	PINGRP_GPIO_PH3,
+	PINGRP_GPIO_PH4,
+	PINGRP_GPIO_PH5,
+	PINGRP_GPIO_PH6,
+	PINGRP_GPIO_PH7,
+	PINGRP_GPIO_PJ7,
+	PINGRP_GPIO_PB0,
+	PINGRP_GPIO_PB1,
+	PINGRP_GPIO_PK7,
+	PINGRP_GPIO_PI0,
+	PINGRP_GPIO_PI1,
+	PINGRP_GPIO_PI2,
+	PINGRP_GPIO_PI4,			/* offset 0x324c */
+	PINGRP_GEN2_I2C_SCL,
+	PINGRP_GEN2_I2C_SDA,
+	PINGRP_SDMMC4_CLK,
+	PINGRP_SDMMC4_CMD,
+	PINGRP_SDMMC4_DAT0,
+	PINGRP_SDMMC4_DAT1,
+	PINGRP_SDMMC4_DAT2,
+	PINGRP_SDMMC4_DAT3,
+	PINGRP_SDMMC4_DAT4,
+	PINGRP_SDMMC4_DAT5,
+	PINGRP_SDMMC4_DAT6,
+	PINGRP_SDMMC4_DAT7,
+	PINGRP_CAM_MCLK = PINGRP_SDMMC4_DAT7 + 2,
+	PINGRP_GPIO_PCC1,
+	PINGRP_GPIO_PBB0,
+	PINGRP_CAM_I2C_SCL,
+	PINGRP_CAM_I2C_SDA,
+	PINGRP_GPIO_PBB3,
+	PINGRP_GPIO_PBB4,
+	PINGRP_GPIO_PBB5,
+	PINGRP_GPIO_PBB6,
+	PINGRP_GPIO_PBB7,
+	PINGRP_GPIO_PCC2,
+	PINGRP_JTAG_RTCK,
+	PINGRP_PWR_I2C_SCL,
+	PINGRP_PWR_I2C_SDA,
+	PINGRP_KB_ROW0,
+	PINGRP_KB_ROW1,
+	PINGRP_KB_ROW2,
+	PINGRP_KB_ROW3,
+	PINGRP_KB_ROW4,
+	PINGRP_KB_ROW5,
+	PINGRP_KB_ROW6,
+	PINGRP_KB_ROW7,
+	PINGRP_KB_ROW8,
+	PINGRP_KB_ROW9,
+	PINGRP_KB_ROW10,
+	PINGRP_KB_ROW11,
+	PINGRP_KB_ROW12,
+	PINGRP_KB_ROW13,
+	PINGRP_KB_ROW14,
+	PINGRP_KB_ROW15,
+	PINGRP_KB_COL0,				/* offset 0x32fc */
+	PINGRP_KB_COL1,
+	PINGRP_KB_COL2,
+	PINGRP_KB_COL3,
+	PINGRP_KB_COL4,
+	PINGRP_KB_COL5,
+	PINGRP_KB_COL6,
+	PINGRP_KB_COL7,
+	PINGRP_CLK_32K_OUT,
+	PINGRP_CORE_PWR_REQ = PINGRP_CLK_32K_OUT + 2,	/* offset 0x3324 */
+	PINGRP_CPU_PWR_REQ,
+	PINGRP_PWR_INT_N,
+	PINGRP_CLK_32K_IN,
+	PINGRP_OWR,
+	PINGRP_DAP1_FS,
+	PINGRP_DAP1_DIN,
+	PINGRP_DAP1_DOUT,
+	PINGRP_DAP1_SCLK,
+	PINGRP_CLK1_REQ,
+	PINGRP_CLK1_OUT,
+	PINGRP_SPDIF_IN,
+	PINGRP_SPDIF_OUT,
+	PINGRP_DAP2_FS,
+	PINGRP_DAP2_DIN,
+	PINGRP_DAP2_DOUT,
+	PINGRP_DAP2_SCLK,
+	PINGRP_DVFS_PWM,
+	PINGRP_GPIO_X1_AUD,
+	PINGRP_GPIO_X3_AUD,
+	PINGRP_DVFS_CLK,
+	PINGRP_GPIO_X4_AUD,
+	PINGRP_GPIO_X5_AUD,
+	PINGRP_GPIO_X6_AUD,
+	PINGRP_GPIO_X7_AUD,
+	PINGRP_SDMMC3_CLK = PINGRP_GPIO_X7_AUD + 3,
+	PINGRP_SDMMC3_CMD,
+	PINGRP_SDMMC3_DAT0,
+	PINGRP_SDMMC3_DAT1,
+	PINGRP_SDMMC3_DAT2,
+	PINGRP_SDMMC3_DAT3,
+	PINGRP_PEX_L0_RST = PINGRP_SDMMC3_DAT3 + 6, /* offset 0x33bc */
+	PINGRP_PEX_L0_CLKREQ,
+	PINGRP_PEX_WAKE,
+	PINGRP_PEX_L1_RST = PINGRP_PEX_WAKE + 2,
+	PINGRP_PEX_L1_CLKREQ,
+	PINGRP_HDMI_CEC = PINGRP_PEX_L1_CLKREQ + 4, /* offset 0x33e0 */
+	PINGRP_SDMMC1_WP_N,
+	PINGRP_SDMMC3_CD_N,
+	PINGRP_GPIO_W2_AUD,
+	PINGRP_GPIO_W3_AUD,
+	PINGRP_USB_VBUS_EN0,
+	PINGRP_USB_VBUS_EN1,
+	PINGRP_SDMMC3_CLK_LB_IN,
+	PINGRP_SDMMC3_CLK_LB_OUT,
+	PINGRP_GMI_CLK_LB,
+	PINGRP_RESET_OUT_N,
+	PINGRP_KB_ROW16,			/* offset 0x340c */
+	PINGRP_KB_ROW17,
+	PINGRP_USB_VBUS_EN2,
+	PINGRP_GPIO_PFF2,
+	PINGRP_DP_HPD,				/* last reg offset = 0x3430 */
+	PINGRP_COUNT,
+};
+
+enum pdrive_pingrp {
+	PDRIVE_PINGROUP_AO1 = 0, /* offset 0x868 */
+	PDRIVE_PINGROUP_AO2,
+	PDRIVE_PINGROUP_AT1,
+	PDRIVE_PINGROUP_AT2,
+	PDRIVE_PINGROUP_AT3,
+	PDRIVE_PINGROUP_AT4,
+	PDRIVE_PINGROUP_AT5,
+	PDRIVE_PINGROUP_CDEV1,
+	PDRIVE_PINGROUP_CDEV2,
+	PDRIVE_PINGROUP_DAP1 = 10,	/* offset 0x890 */
+	PDRIVE_PINGROUP_DAP2,
+	PDRIVE_PINGROUP_DAP3,
+	PDRIVE_PINGROUP_DAP4,
+	PDRIVE_PINGROUP_DBG,
+	PDRIVE_PINGROUP_SDIO3 = 18,	/* offset 0x8B0 */
+	PDRIVE_PINGROUP_SPI,
+	PDRIVE_PINGROUP_UAA,
+	PDRIVE_PINGROUP_UAB,
+	PDRIVE_PINGROUP_UART2,
+	PDRIVE_PINGROUP_UART3,
+	PDRIVE_PINGROUP_SDIO1 = 33,     /* offset 0x8EC */
+	PDRIVE_PINGROUP_DDC = 37,       /* offset 0x8FC */
+	PDRIVE_PINGROUP_GMA,
+	PDRIVE_PINGROUP_GME = 42,	/* offset 0x910 */
+	PDRIVE_PINGROUP_GMF,
+	PDRIVE_PINGROUP_GMG,
+	PDRIVE_PINGROUP_GMH,
+	PDRIVE_PINGROUP_OWR,
+	PDRIVE_PINGROUP_UAD,
+	PDRIVE_PINGROUP_DEV3 = 49,      /* offset 0x92c */
+	PDRIVE_PINGROUP_CEC = 52,       /* offset 0x938 */
+	PDRIVE_PINGROUP_AT6 = 75,	/* offset 0x994 */
+	PDRIVE_PINGROUP_DAP5,
+	PDRIVE_PINGROUP_VBUS,
+	PDRIVE_PINGROUP_AO3,
+	PDRIVE_PINGROUP_HVC,
+	PDRIVE_PINGROUP_SDIO4,
+	PDRIVE_PINGROUP_AO0,
+	PDRIVE_PINGROUP_COUNT,
+};
+
+/*
+ * Functions which can be assigned to each of the pin groups. The values here
+ * bear no relation to the values programmed into pinmux registers and are
+ * purely a convenience. The translation is done through a table search.
+ */
+enum pmux_func {
+	PMUX_FUNC_AHB_CLK,
+	PMUX_FUNC_APB_CLK,
+	PMUX_FUNC_AUDIO_SYNC,
+	PMUX_FUNC_CRT,
+	PMUX_FUNC_DAP1,
+	PMUX_FUNC_DAP2,
+	PMUX_FUNC_DAP3,
+	PMUX_FUNC_DAP4,
+	PMUX_FUNC_DAP5,
+	PMUX_FUNC_DISPA,
+	PMUX_FUNC_DISPB,
+	PMUX_FUNC_EMC_TEST0_DLL,
+	PMUX_FUNC_EMC_TEST1_DLL,
+	PMUX_FUNC_GMI,
+	PMUX_FUNC_GMI_INT,
+	PMUX_FUNC_HDMI,
+	PMUX_FUNC_I2C1,
+	PMUX_FUNC_I2C2,
+	PMUX_FUNC_I2C3,
+	PMUX_FUNC_IDE,
+	PMUX_FUNC_KBC,
+	PMUX_FUNC_MIO,
+	PMUX_FUNC_MIPI_HS,
+	PMUX_FUNC_NAND,
+	PMUX_FUNC_OSC,
+	PMUX_FUNC_OWR,
+	PMUX_FUNC_PCIE,
+	PMUX_FUNC_PLLA_OUT,
+	PMUX_FUNC_PLLC_OUT1,
+	PMUX_FUNC_PLLM_OUT1,
+	PMUX_FUNC_PLLP_OUT2,
+	PMUX_FUNC_PLLP_OUT3,
+	PMUX_FUNC_PLLP_OUT4,
+	PMUX_FUNC_PWM,
+	PMUX_FUNC_PWR_INTR,
+	PMUX_FUNC_PWR_ON,
+	PMUX_FUNC_RTCK,
+	PMUX_FUNC_SDMMC1,
+	PMUX_FUNC_SDMMC2,
+	PMUX_FUNC_SDMMC3,
+	PMUX_FUNC_SDMMC4,
+	PMUX_FUNC_SFLASH,
+	PMUX_FUNC_SPDIF,
+	PMUX_FUNC_SPI1,
+	PMUX_FUNC_SPI2,
+	PMUX_FUNC_SPI2_ALT,
+	PMUX_FUNC_SPI3,
+	PMUX_FUNC_SPI4,
+	PMUX_FUNC_TRACE,
+	PMUX_FUNC_TWC,
+	PMUX_FUNC_UARTA,
+	PMUX_FUNC_UARTB,
+	PMUX_FUNC_UARTC,
+	PMUX_FUNC_UARTD,
+	PMUX_FUNC_UARTE,
+	PMUX_FUNC_ULPI,
+	PMUX_FUNC_VI,
+	PMUX_FUNC_VI_SENSOR_CLK,
+	PMUX_FUNC_XIO,
+	/* End of Tegra2 MUX selectors */
+	PMUX_FUNC_BLINK,
+	PMUX_FUNC_CEC,
+	PMUX_FUNC_CLK12,
+	PMUX_FUNC_DAP,
+	PMUX_FUNC_DAPSDMMC2,
+	PMUX_FUNC_DDR,
+	PMUX_FUNC_DEV3,
+	PMUX_FUNC_DTV,
+	PMUX_FUNC_VI_ALT1,
+	PMUX_FUNC_VI_ALT2,
+	PMUX_FUNC_VI_ALT3,
+	PMUX_FUNC_EMC_DLL,
+	PMUX_FUNC_EXTPERIPH1,
+	PMUX_FUNC_EXTPERIPH2,
+	PMUX_FUNC_EXTPERIPH3,
+	PMUX_FUNC_GMI_ALT,
+	PMUX_FUNC_HDA,
+	PMUX_FUNC_HSI,
+	PMUX_FUNC_I2C4,
+	PMUX_FUNC_I2C5,
+	PMUX_FUNC_I2CPWR,
+	PMUX_FUNC_I2S0,
+	PMUX_FUNC_I2S1,
+	PMUX_FUNC_I2S2,
+	PMUX_FUNC_I2S3,
+	PMUX_FUNC_I2S4,
+	PMUX_FUNC_NAND_ALT,
+	PMUX_FUNC_POPSDIO4,
+	PMUX_FUNC_POPSDMMC4,
+	PMUX_FUNC_PWM0,
+	PMUX_FUNC_PWM1,
+	PMUX_FUNC_PWM2,
+	PMUX_FUNC_PWM3,
+	PMUX_FUNC_SATA,
+	PMUX_FUNC_SPI5,
+	PMUX_FUNC_SPI6,
+	PMUX_FUNC_SYSCLK,
+	PMUX_FUNC_VGP1,
+	PMUX_FUNC_VGP2,
+	PMUX_FUNC_VGP3,
+	PMUX_FUNC_VGP4,
+	PMUX_FUNC_VGP5,
+	PMUX_FUNC_VGP6,
+	/* End of Tegra3 MUX selectors */
+	PMUX_FUNC_USB,
+	PMUX_FUNC_SOC,
+	PMUX_FUNC_CPU,
+	PMUX_FUNC_CLK,
+	PMUX_FUNC_PWRON,
+	PMUX_FUNC_PMI,
+	PMUX_FUNC_CLDVFS,
+	PMUX_FUNC_RESET_OUT_N,
+	/* End of Tegra114 MUX selectors */
+
+	PMUX_FUNC_SAFE,
+	PMUX_FUNC_MAX,
+
+	PMUX_FUNC_INVALID = 0x4000,
+	PMUX_FUNC_RSVD1 = 0x8000,
+	PMUX_FUNC_RSVD2 = 0x8001,
+	PMUX_FUNC_RSVD3 = 0x8002,
+	PMUX_FUNC_RSVD4 = 0x8003,
+};
+
+/* return 1 if a pmux_func is in range */
+#define pmux_func_isvalid(func) \
+	((((func) >= 0) && ((func) < PMUX_FUNC_MAX)) || \
+	(((func) >= PMUX_FUNC_RSVD1) && ((func) <= PMUX_FUNC_RSVD4)))
+
+/* return 1 if a pingrp is in range */
+#define pmux_pingrp_isvalid(pin) (((pin) >= 0) && ((pin) < PINGRP_COUNT))
+
+/* The pullup/pulldown state of a pin group */
+enum pmux_pull {
+	PMUX_PULL_NORMAL = 0,
+	PMUX_PULL_DOWN,
+	PMUX_PULL_UP,
+};
+/* return 1 if a pin_pupd_is in range */
+#define pmux_pin_pupd_isvalid(pupd) (((pupd) >= PMUX_PULL_NORMAL) && \
+				((pupd) <= PMUX_PULL_UP))
+
+/* Defines whether a pin group is tristated or in normal operation */
+enum pmux_tristate {
+	PMUX_TRI_NORMAL = 0,
+	PMUX_TRI_TRISTATE = 1,
+};
+/* return 1 if a pin_tristate_is in range */
+#define pmux_pin_tristate_isvalid(tristate) \
+	(((tristate) >= PMUX_TRI_NORMAL) && \
+	((tristate) <= PMUX_TRI_TRISTATE))
+
+enum pmux_pin_io {
+	PMUX_PIN_OUTPUT = 0,
+	PMUX_PIN_INPUT = 1,
+	PMUX_PIN_NONE,
+};
+/* return 1 if a pin_io_is in range */
+#define pmux_pin_io_isvalid(io) (((io) >= PMUX_PIN_OUTPUT) && \
+				((io) <= PMUX_PIN_INPUT))
+
+enum pmux_pin_lock {
+	PMUX_PIN_LOCK_DEFAULT = 0,
+	PMUX_PIN_LOCK_DISABLE,
+	PMUX_PIN_LOCK_ENABLE,
+};
+/* return 1 if a pin_lock is in range */
+#define pmux_pin_lock_isvalid(lock) (((lock) >= PMUX_PIN_LOCK_DEFAULT) && \
+				((lock) <= PMUX_PIN_LOCK_ENABLE))
+
+enum pmux_pin_od {
+	PMUX_PIN_OD_DEFAULT = 0,
+	PMUX_PIN_OD_DISABLE,
+	PMUX_PIN_OD_ENABLE,
+};
+/* return 1 if a pin_od is in range */
+#define pmux_pin_od_isvalid(od) (((od) >= PMUX_PIN_OD_DEFAULT) && \
+				((od) <= PMUX_PIN_OD_ENABLE))
+
+enum pmux_pin_ioreset {
+	PMUX_PIN_IO_RESET_DEFAULT = 0,
+	PMUX_PIN_IO_RESET_DISABLE,
+	PMUX_PIN_IO_RESET_ENABLE,
+};
+/* return 1 if a pin_ioreset_is in range */
+#define pmux_pin_ioreset_isvalid(ioreset) \
+				(((ioreset) >= PMUX_PIN_IO_RESET_DEFAULT) && \
+				((ioreset) <= PMUX_PIN_IO_RESET_ENABLE))
+
+enum pmux_pin_rcv_sel {
+	PMUX_PIN_RCV_SEL_DEFAULT = 0,
+	PMUX_PIN_RCV_SEL_NORMAL,
+	PMUX_PIN_RCV_SEL_HIGH,
+};
+/* return 1 if a pin_rcv_sel_is in range */
+#define pmux_pin_rcv_sel_isvalid(rcv_sel) \
+				(((rcv_sel) >= PMUX_PIN_RCV_SEL_DEFAULT) && \
+				((rcv_sel) <= PMUX_PIN_RCV_SEL_HIGH))
+
+/* Available power domains used by pin groups */
+enum pmux_vddio {
+	PMUX_VDDIO_BB = 0,
+	PMUX_VDDIO_LCD,
+	PMUX_VDDIO_VI,
+	PMUX_VDDIO_UART,
+	PMUX_VDDIO_DDR,
+	PMUX_VDDIO_NAND,
+	PMUX_VDDIO_SYS,
+	PMUX_VDDIO_AUDIO,
+	PMUX_VDDIO_SD,
+	PMUX_VDDIO_CAM,
+	PMUX_VDDIO_GMI,
+	PMUX_VDDIO_PEXCTL,
+	PMUX_VDDIO_SDMMC1,
+	PMUX_VDDIO_SDMMC3,
+	PMUX_VDDIO_SDMMC4,
+
+	PMUX_VDDIO_NONE
+};
+
+#define PGRP_SLWF_NONE	-1
+#define PGRP_SLWF_MAX	3
+#define PGRP_SLWR_NONE	PGRP_SLWF_NONE
+#define PGRP_SLWR_MAX	PGRP_SLWF_MAX
+
+#define PGRP_DRVUP_NONE	-1
+#define PGRP_DRVUP_MAX	127
+#define PGRP_DRVDN_NONE	PGRP_DRVUP_NONE
+#define PGRP_DRVDN_MAX	PGRP_DRVUP_MAX
+
+#define PGRP_SCHMT_NONE	-1
+#define PGRP_HSM_NONE	PGRP_SCHMT_NONE
+
+/* return 1 if a padgrp is in range */
+#define pmux_padgrp_isvalid(pd) (((pd) >= 0) && ((pd) < PDRIVE_PINGROUP_COUNT))
+
+/* return 1 if a slew-rate rising/falling edge value is in range */
+#define pmux_pad_slw_isvalid(slw) (((slw) == PGRP_SLWF_NONE) || \
+				(((slw) >= 0) && ((slw) <= PGRP_SLWF_MAX)))
+
+/* return 1 if a driver output pull-up/down strength code value is in range */
+#define pmux_pad_drv_isvalid(drv) (((drv) == PGRP_DRVUP_NONE) || \
+				(((drv) >= 0) && ((drv) <= PGRP_DRVUP_MAX)))
+
+/* return 1 if a low-power mode value is in range */
+#define pmux_pad_lpmd_isvalid(lpm) (((lpm) == PGRP_LPMD_NONE) || \
+				(((lpm) >= 0) && ((lpm) <= PGRP_LPMD_X)))
+
+/* Defines a pin group cfg's low-power mode select */
+enum pgrp_lpmd {
+	PGRP_LPMD_X8 = 0,
+	PGRP_LPMD_X4,
+	PGRP_LPMD_X2,
+	PGRP_LPMD_X,
+	PGRP_LPMD_NONE = -1,
+};
+
+/* Defines whether a pin group cfg's schmidt is enabled or not */
+enum pgrp_schmt {
+	PGRP_SCHMT_DISABLE = 0,
+	PGRP_SCHMT_ENABLE = 1,
+};
+
+/* Defines whether a pin group cfg's high-speed mode is enabled or not */
+enum pgrp_hsm {
+	PGRP_HSM_DISABLE = 0,
+	PGRP_HSM_ENABLE = 1,
+};
+
+/*
+ * This defines the configuration for a pin group's pad control config
+ */
+struct padctrl_config {
+	enum pdrive_pingrp padgrp;	/* pin group PDRIVE_PINGRP_x */
+	int slwf;			/* falling edge slew         */
+	int slwr;			/* rising edge slew          */
+	int drvup;			/* pull-up drive strength    */
+	int drvdn;			/* pull-down drive strength  */
+	enum pgrp_lpmd lpmd;		/* low-power mode selection  */
+	enum pgrp_schmt schmt;		/* schmidt enable            */
+	enum pgrp_hsm hsm;		/* high-speed mode enable    */
+};
+
+/* Tegra124 pin drive group and pin mux registers */
+#define PDRIVE_PINGROUP_OFFSET	(0x868 >> 2)
+#define PMUX_OFFSET	((0x3000 >> 2) - PDRIVE_PINGROUP_OFFSET - \
+				PDRIVE_PINGROUP_COUNT)
+struct pmux_tri_ctlr {
+	uint pmt_reserved0[9];		/* ABP_MISC_PP_ offsets 00-20 */
+	uint pmt_cfg_ctl;		/* _CONFIG_CTL_0, offset 24        */
+
+	uint pmt_reserved[528];		/* ABP_MISC_PP_ reserved offs 28-864 */
+
+	uint pmt_drive[PDRIVE_PINGROUP_COUNT];	/* pin drive grps offs 868 */
+	uint pmt_reserved5[PMUX_OFFSET];
+	uint pmt_ctl[PINGRP_COUNT];	/* mux/pupd/tri regs, offset 0x3000 */
+};
+
+/*
+ * This defines the configuration for a pin, including the function assigned,
+ * pull up/down settings and tristate settings. Having set up one of these
+ * you can call pinmux_config_pingroup() to configure a pin in one step. Also
+ * available is pinmux_config_table() to configure a list of pins.
+ */
+struct pingroup_config {
+	enum pmux_pingrp pingroup;	/* pin group PINGRP_...             */
+	enum pmux_func func;		/* function to assign FUNC_...      */
+	enum pmux_pull pull;		/* pull up/down/normal PMUX_PULL_...*/
+	enum pmux_tristate tristate;	/* tristate or normal PMUX_TRI_...  */
+	enum pmux_pin_io io;		/* input or output PMUX_PIN_...  */
+	enum pmux_pin_lock lock;	/* lock enable/disable PMUX_PIN...  */
+	enum pmux_pin_od od;		/* open-drain or push-pull driver  */
+	enum pmux_pin_ioreset ioreset;	/* input/output reset PMUX_PIN...  */
+	enum pmux_pin_rcv_sel rcv_sel;	/* select between High and Normal  */
+					/* VIL/VIH receivers */
+};
+
+/* Set a pin group to tristate */
+void pinmux_tristate_enable(enum pmux_pingrp pin);
+
+/* Set a pin group to normal (non tristate) */
+void pinmux_tristate_disable(enum pmux_pingrp pin);
+
+/* Set the pull up/down feature for a pin group */
+void pinmux_set_pullupdown(enum pmux_pingrp pin, enum pmux_pull pupd);
+
+/* Set the mux function for a pin group */
+void pinmux_set_func(enum pmux_pingrp pin, enum pmux_func func);
+
+/* Set the complete configuration for a pin group */
+void pinmux_config_pingroup(struct pingroup_config *config);
+
+/* Set a pin group to tristate or normal */
+void pinmux_set_tristate(enum pmux_pingrp pin, int enable);
+
+/* Set a pin group as input or output */
+void pinmux_set_io(enum pmux_pingrp pin, enum pmux_pin_io io);
+
+/**
+ * Configure a list of pin groups
+ *
+ * @param config	List of config items
+ * @param len		Number of config items in list
+ */
+void pinmux_config_table(struct pingroup_config *config, int len);
+
+/* Set a group of pins from a table */
+void pinmux_init(void);
+
+/**
+ * Set the GP pad configs
+ *
+ * @param config	List of config items
+ * @param len		Number of config items in list
+ */
+void padgrp_config_table(struct padctrl_config *config, int len);
+
+#endif	/* _TEGRA124_PINMUX_H_ */
diff --git a/arch/arm/include/asm/arch-tegra124/pmu.h b/arch/arm/include/asm/arch-tegra124/pmu.h
new file mode 100644
index 0000000000..b10100a636
--- /dev/null
+++ b/arch/arm/include/asm/arch-tegra124/pmu.h
@@ -0,0 +1,14 @@
+/*
+ * (C) Copyright 2010-2013
+ * NVIDIA Corporation <www.nvidia.com>
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#ifndef _TEGRA124_PMU_H_
+#define _TEGRA124_PMU_H_
+
+/* Set core and CPU voltages to nominal levels */
+int pmu_set_nominal(void);
+
+#endif	/* _TEGRA124_PMU_H_ */
diff --git a/arch/arm/include/asm/arch-tegra124/spl.h b/arch/arm/include/asm/arch-tegra124/spl.h
new file mode 100644
index 0000000000..e2663954bf
--- /dev/null
+++ b/arch/arm/include/asm/arch-tegra124/spl.h
@@ -0,0 +1,13 @@
+/*
+ * (C) Copyright 2010-2013
+ * NVIDIA Corporation <www.nvidia.com>
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#ifndef _ASM_ARCH_SPL_H_
+#define _ASM_ARCH_SPL_H_
+
+#define BOOT_DEVICE_RAM 1
+
+#endif /* _ASM_ARCH_SPL_H_ */
diff --git a/arch/arm/include/asm/arch-tegra124/sysctr.h b/arch/arm/include/asm/arch-tegra124/sysctr.h
new file mode 100644
index 0000000000..3f0309b78f
--- /dev/null
+++ b/arch/arm/include/asm/arch-tegra124/sysctr.h
@@ -0,0 +1,26 @@
+/*
+ * (C) Copyright 2013
+ * NVIDIA Corporation <www.nvidia.com>
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#ifndef _TEGRA124_SYSCTR_H_
+#define _TEGRA124_SYSCTR_H_
+
+struct sysctr_ctlr {
+	u32 cntcr;		/* 0x00: SYSCTR0_CNTCR Counter Control */
+	u32 cntsr;		/* 0x04: SYSCTR0_CNTSR Counter Status */
+	u32 cntcv0;		/* 0x08: SYSCTR0_CNTCV0 Counter Count 31:00 */
+	u32 cntcv1;		/* 0x0C: SYSCTR0_CNTCV1 Counter Count 63:32 */
+	u32 reserved1[4];	/* 0x10 - 0x1C */
+	u32 cntfid0;		/* 0x20: SYSCTR0_CNTFID0 Freq Table Entry */
+	u32 cntfid1;		/* 0x24: SYSCTR0_CNTFID1 Freq Table End */
+	u32 reserved2[1002];	/* 0x28 - 0xFCC */
+	u32 counterid[12];	/* 0xFD0 - 0xFxx CounterID regs, RO */
+};
+
+#define TSC_CNTCR_ENABLE	(1 << 0)	/* Enable */
+#define TSC_CNTCR_HDBG		(1 << 1)	/* Halt on debug */
+
+#endif	/* _TEGRA124_SYSCTR_H_ */
diff --git a/arch/arm/include/asm/arch-tegra124/tegra.h b/arch/arm/include/asm/arch-tegra124/tegra.h
new file mode 100644
index 0000000000..86ebd19453
--- /dev/null
+++ b/arch/arm/include/asm/arch-tegra124/tegra.h
@@ -0,0 +1,32 @@
+/*
+ * (C) Copyright 2013
+ * NVIDIA Corporation <www.nvidia.com>
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#ifndef _TEGRA124_H_
+#define _TEGRA124_H_
+
+#define CONFIG_TEGRA124
+
+#define NV_PA_SDRAM_BASE	0x80000000
+#define NV_PA_TSC_BASE		0x700F0000	/* System Counter TSC regs */
+#define NV_PA_MC_BASE		0x70019000	/* Mem Ctlr regs (MCB, etc.) */
+#define NV_PA_AHB_BASE		0x6000C000	/* System regs (AHB, etc.) */
+
+#include <asm/arch-tegra/tegra.h>
+
+#define BCT_ODMDATA_OFFSET	1704	/* offset to ODMDATA word */
+
+#undef NVBOOTINFOTABLE_BCTSIZE
+#undef NVBOOTINFOTABLE_BCTPTR
+#define NVBOOTINFOTABLE_BCTSIZE	0x48	/* BCT size in BIT in IRAM */
+#define NVBOOTINFOTABLE_BCTPTR	0x4C	/* BCT pointer in BIT in IRAM */
+
+#define MAX_NUM_CPU		4
+#define MCB_EMEM_ARB_OVERRIDE	(NV_PA_MC_BASE + 0xE8)
+
+#define TEGRA_USB1_BASE		0x7D000000
+
+#endif /* _TEGRA124_H_ */
diff --git a/arch/arm/include/asm/arch-tegra124/usb.h b/arch/arm/include/asm/arch-tegra124/usb.h
new file mode 100644
index 0000000000..7a2d7859d9
--- /dev/null
+++ b/arch/arm/include/asm/arch-tegra124/usb.h
@@ -0,0 +1,268 @@
+/*
+ * (C) Copyright 2013
+ * NVIDIA Corporation <www.nvidia.com>
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#ifndef _TEGRA124_USB_H_
+#define _TEGRA124_USB_H_
+
+
+/* USB Controller (USBx_CONTROLLER_) regs */
+struct usb_ctlr {
+	/* 0x000 */
+	uint id;
+	uint reserved0;
+	uint host;
+	uint device;
+
+	/* 0x010 */
+	uint txbuf;
+	uint rxbuf;
+	uint reserved1[2];
+
+	/* 0x020 */
+	uint reserved2[56];
+
+	/* 0x100 */
+	u16 cap_length;
+	u16 hci_version;
+	uint hcs_params;
+	uint hcc_params;
+	uint reserved3[5];
+
+	/* 0x120 */
+	uint dci_version;
+	uint dcc_params;
+	uint reserved4[2];
+
+	/* 0x130 */
+	uint usb_cmd;
+	uint usb_sts;
+	uint usb_intr;
+	uint frindex;
+
+	/* 0x140 */
+	uint reserved5;
+	uint periodic_list_base;
+	uint async_list_addr;
+	uint reserved5_1;
+
+	/* 0x150 */
+	uint burst_size;
+	uint tx_fill_tuning;
+	uint reserved6;
+	uint icusb_ctrl;
+
+	/* 0x160 */
+	uint ulpi_viewport;
+	uint reserved7;
+	uint reserved7_0;
+	uint reserved7_1;
+
+	/* 0x170 */
+	uint reserved;
+	uint port_sc1;
+	uint reserved8[6];
+
+	/* 0x190 */
+	uint reserved9[8];
+
+	/* 0x1b0 */
+	uint reserved10;
+	uint hostpc1_devlc;
+	uint reserved10_1[2];
+
+	/* 0x1c0 */
+	uint reserved10_2[4];
+
+	/* 0x1d0 */
+	uint reserved10_3[4];
+
+	/* 0x1e0 */
+	uint reserved10_4[4];
+
+	/* 0x1f0 */
+	uint reserved10_5;
+	uint otgsc;
+	uint usb_mode;
+	uint reserved10_6;
+
+	/* 0x200 */
+	uint endpt_nak;
+	uint endpt_nak_enable;
+	uint endpt_setup_stat;
+	uint reserved11_1[0x7D];
+
+	/* 0x400 */
+	uint susp_ctrl;
+	uint phy_vbus_sensors;
+	uint phy_vbus_wakeup_id;
+	uint phy_alt_vbus_sys;
+
+	/* 0x410 */
+	uint usb1_legacy_ctrl;
+	uint reserved12[3];
+
+	/* 0x420 */
+	uint reserved13[56];
+
+	/* 0x500 */
+	uint reserved14[64 * 3];
+
+	/* 0x800 */
+	uint utmip_pll_cfg0;
+	uint utmip_pll_cfg1;
+	uint utmip_xcvr_cfg0;
+	uint utmip_bias_cfg0;
+
+	/* 0x810 */
+	uint utmip_hsrx_cfg0;
+	uint utmip_hsrx_cfg1;
+	uint utmip_fslsrx_cfg0;
+	uint utmip_fslsrx_cfg1;
+
+	/* 0x820 */
+	uint utmip_tx_cfg0;
+	uint utmip_misc_cfg0;
+	uint utmip_misc_cfg1;
+	uint utmip_debounce_cfg0;
+
+	/* 0x830 */
+	uint utmip_bat_chrg_cfg0;
+	uint utmip_spare_cfg0;
+	uint utmip_xcvr_cfg1;
+	uint utmip_bias_cfg1;
+};
+
+/* USB1_LEGACY_CTRL */
+#define USB1_NO_LEGACY_MODE		1
+
+#define VBUS_SENSE_CTL_SHIFT			1
+#define VBUS_SENSE_CTL_MASK			(3 << VBUS_SENSE_CTL_SHIFT)
+#define VBUS_SENSE_CTL_VBUS_WAKEUP		0
+#define VBUS_SENSE_CTL_AB_SESS_VLD_OR_VBUS_WAKEUP	1
+#define VBUS_SENSE_CTL_AB_SESS_VLD		2
+#define VBUS_SENSE_CTL_A_SESS_VLD		3
+
+/* USBx_IF_USB_SUSP_CTRL_0 */
+#define UTMIP_PHY_ENB			        (1 << 12)
+#define UTMIP_RESET			        (1 << 11)
+#define USB_PHY_CLK_VALID			(1 << 7)
+#define USB_SUSP_CLR				(1 << 5)
+
+/* USBx_UTMIP_MISC_CFG0 */
+#define UTMIP_SUSPEND_EXIT_ON_EDGE		(1 << 22)
+
+/* USBx_UTMIP_MISC_CFG1 */
+#define UTMIP_PHY_XTAL_CLOCKEN			(1 << 30)
+
+/* Moved to Clock and Reset register space */
+#define UTMIP_PLLU_STABLE_COUNT_SHIFT		6
+#define UTMIP_PLLU_STABLE_COUNT_MASK		\
+				(0xfff << UTMIP_PLLU_STABLE_COUNT_SHIFT)
+/* Moved to Clock and Reset register space */
+#define UTMIP_PLL_ACTIVE_DLY_COUNT_SHIFT	18
+#define UTMIP_PLL_ACTIVE_DLY_COUNT_MASK		\
+				(0x1f << UTMIP_PLL_ACTIVE_DLY_COUNT_SHIFT)
+
+/* USBx_UTMIP_PLL_CFG1_0 */
+/* Moved to Clock and Reset register space */
+#define UTMIP_PLLU_ENABLE_DLY_COUNT_SHIFT	27
+#define UTMIP_PLLU_ENABLE_DLY_COUNT_MASK	\
+				(0x1f << UTMIP_PLLU_ENABLE_DLY_COUNT_SHIFT)
+#define UTMIP_XTAL_FREQ_COUNT_SHIFT		0
+#define UTMIP_XTAL_FREQ_COUNT_MASK		0xfff
+
+/* USBx_UTMIP_BIAS_CFG0_0 */
+#define UTMIP_HSDISCON_LEVEL_MSB		(1 << 24)
+#define UTMIP_OTGPD				(1 << 11)
+#define UTMIP_BIASPD				(1 << 10)
+#define UTMIP_HSDISCON_LEVEL_SHIFT		2
+#define UTMIP_HSDISCON_LEVEL_MASK		\
+				(0x3 << UTMIP_HSDISCON_LEVEL_SHIFT)
+#define UTMIP_HSSQUELCH_LEVEL_SHIFT		0
+#define UTMIP_HSSQUELCH_LEVEL_MASK		\
+				(0x3 << UTMIP_HSSQUELCH_LEVEL_SHIFT)
+
+/* USBx_UTMIP_BIAS_CFG1_0 */
+#define UTMIP_FORCE_PDTRK_POWERDOWN		1
+#define UTMIP_BIAS_PDTRK_COUNT_SHIFT		3
+#define UTMIP_BIAS_PDTRK_COUNT_MASK		\
+				(0x1f << UTMIP_BIAS_PDTRK_COUNT_SHIFT)
+
+/* USBx_UTMIP_DEBOUNCE_CFG0_0 */
+#define UTMIP_DEBOUNCE_CFG0_SHIFT		0
+#define UTMIP_DEBOUNCE_CFG0_MASK		0xffff
+
+/* USBx_UTMIP_TX_CFG0_0 */
+#define UTMIP_FS_PREAMBLE_J			(1 << 19)
+
+/* USBx_UTMIP_BAT_CHRG_CFG0_0 */
+#define UTMIP_PD_CHRG				1
+
+/* USBx_UTMIP_SPARE_CFG0_0 */
+#define FUSE_SETUP_SEL				(1 << 3)
+
+/* USBx_UTMIP_HSRX_CFG0_0 */
+#define UTMIP_IDLE_WAIT_SHIFT			15
+#define UTMIP_IDLE_WAIT_MASK			(0x1f << UTMIP_IDLE_WAIT_SHIFT)
+#define UTMIP_ELASTIC_LIMIT_SHIFT		10
+#define UTMIP_ELASTIC_LIMIT_MASK		\
+				(0x1f << UTMIP_ELASTIC_LIMIT_SHIFT)
+
+/* USBx_UTMIP_HSRX_CFG0_1 */
+#define UTMIP_HS_SYNC_START_DLY_SHIFT		1
+#define UTMIP_HS_SYNC_START_DLY_MASK		\
+				(0x1f << UTMIP_HS_SYNC_START_DLY_SHIFT)
+
+/* USBx_CONTROLLER_2_USB2D_ICUSB_CTRL_0 */
+#define IC_ENB1					(1 << 3)
+
+/* PORTSC1, USB1, defined for Tegra20 to avoid compiling error */
+#define PTS1_SHIFT				31
+#define PTS1_MASK				(1 << PTS1_SHIFT)
+#define STS1					(1 << 30)
+
+/* USB2D_HOSTPC1_DEVLC_0 */
+#define PTS_SHIFT				29
+#define PTS_MASK				(0x7U << PTS_SHIFT)
+#define PTS_UTMI	0
+#define PTS_RESERVED	1
+#define PTS_ULPI	2
+#define PTS_ICUSB_SER	3
+#define PTS_HSIC	4
+
+#define STS					(1 << 28)
+
+/* SB2_CONTROLLER_2_USB2D_PORTSC1_0 */
+#define WKOC				(1 << 22)
+#define WKDS				(1 << 21)
+#define WKCN				(1 << 20)
+
+/* USBx_UTMIP_XCVR_CFG0_0 */
+#define UTMIP_FORCE_PD_POWERDOWN		(1 << 14)
+#define UTMIP_FORCE_PD2_POWERDOWN		(1 << 16)
+#define UTMIP_FORCE_PDZI_POWERDOWN		(1 << 18)
+#define UTMIP_XCVR_LSBIAS_SE			(1 << 21)
+#define UTMIP_XCVR_HSSLEW_MSB_SHIFT		25
+#define UTMIP_XCVR_HSSLEW_MSB_MASK		\
+			(0x7f << UTMIP_XCVR_HSSLEW_MSB_SHIFT)
+#define UTMIP_XCVR_SETUP_MSB_SHIFT	22
+#define UTMIP_XCVR_SETUP_MSB_MASK	(0x7 << UTMIP_XCVR_SETUP_MSB_SHIFT)
+#define UTMIP_XCVR_SETUP_SHIFT		0
+#define UTMIP_XCVR_SETUP_MASK		(0xf << UTMIP_XCVR_SETUP_SHIFT)
+
+/* USBx_UTMIP_XCVR_CFG1_0 */
+#define UTMIP_XCVR_TERM_RANGE_ADJ_SHIFT		18
+#define UTMIP_XCVR_TERM_RANGE_ADJ_MASK		\
+			(0xf << UTMIP_XCVR_TERM_RANGE_ADJ_SHIFT)
+#define UTMIP_FORCE_PDDISC_POWERDOWN		(1 << 0)
+#define UTMIP_FORCE_PDCHRP_POWERDOWN		(1 << 2)
+#define UTMIP_FORCE_PDDR_POWERDOWN		(1 << 4)
+
+/* USB3_IF_USB_PHY_VBUS_SENSORS_0 */
+#define VBUS_VLD_STS			(1 << 26)
+
+#endif	/* _TEGRA124_USB_H_ */
diff --git a/arch/arm/include/asm/arch-tegra20/tegra.h b/arch/arm/include/asm/arch-tegra20/tegra.h
index 18856ac372..6a4b40ec76 100644
--- a/arch/arm/include/asm/arch-tegra20/tegra.h
+++ b/arch/arm/include/asm/arch-tegra20/tegra.h
@@ -8,6 +8,8 @@
 #ifndef _TEGRA20_H_
 #define _TEGRA20_H_
 
+#define CONFIG_TEGRA20
+
 #define NV_PA_SDRAM_BASE	0x00000000
 
 #include <asm/arch-tegra/tegra.h>
diff --git a/arch/arm/include/asm/arch-tegra30/tegra.h b/arch/arm/include/asm/arch-tegra30/tegra.h
index c02c5d8500..4ad8b1c053 100644
--- a/arch/arm/include/asm/arch-tegra30/tegra.h
+++ b/arch/arm/include/asm/arch-tegra30/tegra.h
@@ -17,6 +17,8 @@
 #ifndef _TEGRA30_H_
 #define _TEGRA30_H_
 
+#define CONFIG_TEGRA30
+
 #define NV_PA_SDRAM_BASE	0x80000000	/* 0x80000000 for real T30 */
 
 #include <asm/arch-tegra/tegra.h>
diff --git a/arch/arm/include/asm/arch-tnetv107x/hardware.h b/arch/arm/include/asm/arch-tnetv107x/hardware.h
index aed6c46f64..2a7ca4e00c 100644
--- a/arch/arm/include/asm/arch-tnetv107x/hardware.h
+++ b/arch/arm/include/asm/arch-tnetv107x/hardware.h
@@ -9,7 +9,7 @@
 
 #ifndef __ASSEMBLY__
 
-#include <asm/sizes.h>
+#include <linux/sizes.h>
 
 #define ASYNC_EMIF_NUM_CS		4
 #define ASYNC_EMIF_MODE_NOR		0
diff --git a/arch/arm/include/asm/arch-vf610/crm_regs.h b/arch/arm/include/asm/arch-vf610/crm_regs.h
index 85f1fda9f5..509559c1cd 100644
--- a/arch/arm/include/asm/arch-vf610/crm_regs.h
+++ b/arch/arm/include/asm/arch-vf610/crm_regs.h
@@ -55,57 +55,59 @@ struct ccm_reg {
 
 /* Analog components control digital interface (ANADIG) */
 struct anadig_reg {
+	u32 reserved_0x000[4];
 	u32 pll3_ctrl;
-	u32 resv0[3];
+	u32 reserved_0x014[3];
 	u32 pll7_ctrl;
-	u32 resv1[3];
+	u32 reserved_0x024[3];
 	u32 pll2_ctrl;
-	u32 resv2[3];
+	u32 reserved_0x034[3];
 	u32 pll2_ss;
-	u32 resv3[3];
+	u32 reserved_0x044[3];
 	u32 pll2_num;
-	u32 resv4[3];
+	u32 reserved_0x054[3];
 	u32 pll2_denom;
-	u32 resv5[3];
+	u32 reserved_0x064[3];
 	u32 pll4_ctrl;
-	u32 resv6[3];
+	u32 reserved_0x074[3];
 	u32 pll4_num;
-	u32 resv7[3];
+	u32 reserved_0x084[3];
 	u32 pll4_denom;
+	u32 reserved_0x094[3];
 	u32 pll6_ctrl;
-	u32 resv8[3];
+	u32 reserved_0x0A4[3];
 	u32 pll6_num;
-	u32 resv9[3];
+	u32 reserved_0x0B4[3];
 	u32 pll6_denom;
-	u32 resv10[3];
+	u32 reserved_0x0C4[7];
 	u32 pll5_ctrl;
-	u32 resv11[3];
+	u32 reserved_0x0E4[3];
 	u32 pll3_pfd;
-	u32 resv12[3];
+	u32 reserved_0x0F4[3];
 	u32 pll2_pfd;
-	u32 resv13[3];
+	u32 reserved_0x104[3];
 	u32 reg_1p1;
-	u32 resv14[3];
+	u32 reserved_0x114[3];
 	u32 reg_3p0;
-	u32 resv15[3];
+	u32 reserved_0x124[3];
 	u32 reg_2p5;
-	u32 resv16[7];
+	u32 reserved_0x134[7];
 	u32 ana_misc0;
-	u32 resv17[3];
+	u32 reserved_0x154[3];
 	u32 ana_misc1;
-	u32 resv18[63];
+	u32 reserved_0x164[63];
 	u32 anadig_digprog;
-	u32 resv19[3];
+	u32 reserved_0x264[3];
 	u32 pll1_ctrl;
-	u32 resv20[3];
+	u32 reserved_0x274[3];
 	u32 pll1_ss;
-	u32 resv21[3];
+	u32 reserved_0x284[3];
 	u32 pll1_num;
-	u32 resv22[3];
+	u32 reserved_0x294[3];
 	u32 pll1_denom;
-	u32 resv23[3];
+	u32 reserved_0x2A4[3];
 	u32 pll1_pdf;
-	u32 resv24[3];
+	u32 reserved_0x2B4[3];
 	u32 pll_lock;
 };
 #endif
@@ -148,22 +150,38 @@ struct anadig_reg {
 #define CCM_CACRR_ARM_CLK_DIV_MASK		0x7
 #define CCM_CACRR_ARM_CLK_DIV(v)		((v) & 0x7)
 
+#define CCM_CSCMR1_NFC_CLK_SEL_OFFSET		12
+#define CCM_CSCMR1_NFC_CLK_SEL_MASK		(0x3 << 12)
+#define CCM_CSCMR1_NFC_CLK_SEL(v)		(((v) & 0x3) << 12)
+
 #define CCM_CSCMR1_ESDHC1_CLK_SEL_OFFSET	18
 #define CCM_CSCMR1_ESDHC1_CLK_SEL_MASK		(0x3 << 18)
 #define CCM_CSCMR1_ESDHC1_CLK_SEL(v)		(((v) & 0x3) << 18)
 
 #define CCM_CSCDR1_RMII_CLK_EN			(1 << 24)
 
+#define CCM_CSCDR2_NFC_EN			(1 << 9)
+#define CCM_CSCDR2_NFC_FRAC_DIV_EN		(1 << 13)
+#define CCM_CSCDR2_NFC_CLK_INV			(1 << 14)
+#define CCM_CSCDR2_NFC_FRAC_DIV_OFFSET		4
+#define CCM_CSCDR2_NFC_FRAC_DIV_MASK		(0xf << 4)
+#define CCM_CSCDR2_NFC_FRAC_DIV(v)		(((v) & 0xf) << 4)
+
 #define CCM_CSCDR2_ESDHC1_EN			(1 << 29)
 #define CCM_CSCDR2_ESDHC1_CLK_DIV_OFFSET	20
 #define CCM_CSCDR2_ESDHC1_CLK_DIV_MASK		(0xf << 20)
 #define CCM_CSCDR2_ESDHC1_CLK_DIV(v)		(((v) & 0xf) << 20)
 
+#define CCM_CSCDR3_NFC_PRE_DIV_OFFSET		13
+#define CCM_CSCDR3_NFC_PRE_DIV_MASK		(0x7 << 13)
+#define CCM_CSCDR3_NFC_PRE_DIV(v)		(((v) & 0x7) << 13)
+
 #define CCM_CSCMR2_RMII_CLK_SEL_OFFSET		4
 #define CCM_CSCMR2_RMII_CLK_SEL_MASK		(0x3 << 4)
 #define CCM_CSCMR2_RMII_CLK_SEL(v)		(((v) & 0x3) << 4)
 
 #define CCM_REG_CTRL_MASK			0xffffffff
+#define CCM_CCGR0_UART0_CTRL_MASK               (0x3 << 14)
 #define CCM_CCGR0_UART1_CTRL_MASK		(0x3 << 16)
 #define CCM_CCGR1_PIT_CTRL_MASK			(0x3 << 14)
 #define CCM_CCGR1_WDOGA5_CTRL_MASK		(0x3 << 28)
@@ -183,7 +201,12 @@ struct anadig_reg {
 #define CCM_CCGR7_SDHC1_CTRL_MASK		(0x3 << 4)
 #define CCM_CCGR9_FEC0_CTRL_MASK		0x3
 #define CCM_CCGR9_FEC1_CTRL_MASK		(0x3 << 2)
+#define CCM_CCGR10_NFC_CTRL_MASK		0x3
 
+#define ANADIG_PLL5_CTRL_BYPASS                 (1 << 16)
+#define ANADIG_PLL5_CTRL_ENABLE                 (1 << 13)
+#define ANADIG_PLL5_CTRL_POWERDOWN              (1 << 12)
+#define ANADIG_PLL5_CTRL_DIV_SELECT		1
 #define ANADIG_PLL2_CTRL_ENABLE			(1 << 13)
 #define ANADIG_PLL2_CTRL_POWERDOWN		(1 << 12)
 #define ANADIG_PLL2_CTRL_DIV_SELECT		1
diff --git a/arch/arm/include/asm/arch-vf610/imx-regs.h b/arch/arm/include/asm/arch-vf610/imx-regs.h
index b8c877f939..42943f3732 100644
--- a/arch/arm/include/asm/arch-vf610/imx-regs.h
+++ b/arch/arm/include/asm/arch-vf610/imx-regs.h
@@ -85,6 +85,8 @@
 #define ESDHC0_BASE_ADDR	(AIPS1_BASE_ADDR + 0x00031000)
 #define ESDHC1_BASE_ADDR	(AIPS1_BASE_ADDR + 0x00032000)
 #define ENET_BASE_ADDR		(AIPS1_BASE_ADDR + 0x00050000)
+#define ENET1_BASE_ADDR		(AIPS1_BASE_ADDR + 0x00051000)
+#define NFC_BASE_ADDR		(AIPS1_BASE_ADDR + 0x00060000)
 
 /* MUX mode and PAD ctrl are in one register */
 #define CONFIG_IOMUX_SHARE_CONF_REG
@@ -96,6 +98,8 @@
 #define MSCM_IRSPRC_CP0_EN				1
 #define MSCM_IRSPRC_NUM					112
 
+#define MSCM_CP0CFG1		(MSCM_BASE_ADDR + 0x000000014)
+
 /* DDRMC */
 #define DDRMC_PHY_DQ_TIMING				0x00002613
 #define DDRMC_PHY_DQS_TIMING				0x00002615
@@ -214,7 +218,9 @@
 #define DDRMC_CR139_PHY_WRLV_EN(v)			((v) & 0xff)
 #define DDRMC_CR154_PAD_ZQ_EARLY_CMP_EN_TIMER(v)	(((v) & 0x1f) << 27)
 #define DDRMC_CR154_PAD_ZQ_MODE(v)			(((v) & 0x3) << 21)
+#define DDRMC_CR154_DDR_SEL_PAD_CONTR(v)		(((v) & 0x3) << 18)
 #define DDRMC_CR155_AXI0_AWCACHE			(1 << 10)
+#define DDRMC_CR155_AXI0_COBUF				(1 << 8)
 #define DDRMC_CR155_PAD_ODT_BYTE1(v)			((v) & 0x7)
 #define DDRMC_CR158_TWR(v)				((v) & 0x3f)
 
@@ -402,6 +408,18 @@ struct mscm_ir {
 	u16 rsvd3[848];
 };
 
+/* MSCM */
+struct mscm {
+	u32 cpxtype;
+	u32 cpxnum;
+	u32 cpxmaster;
+	u32 cpxcount;
+	u32 cpxcfg0;
+	u32 cpxcfg1;
+	u32 cpxcfg2;
+	u32 cpxcfg3;
+};
+
 #endif	/* __ASSEMBLER__*/
 
 #endif	/* __ASM_ARCH_IMX_REGS_H__ */
diff --git a/arch/arm/include/asm/arch-vf610/iomux-vf610.h b/arch/arm/include/asm/arch-vf610/iomux-vf610.h
index 4a39eb0d60..86ac69bc52 100644
--- a/arch/arm/include/asm/arch-vf610/iomux-vf610.h
+++ b/arch/arm/include/asm/arch-vf610/iomux-vf610.h
@@ -19,11 +19,21 @@
 #define VF610_DDR_PAD_CTRL	PAD_CTL_DSE_25ohm
 #define VF610_I2C_PAD_CTRL	(PAD_CTL_PUS_47K_UP | PAD_CTL_DSE_50ohm | \
 				PAD_CTL_SPEED_HIGH | PAD_CTL_OBE_IBE_ENABLE)
+#define VF610_NFC_IO_PAD_CTRL	(PAD_CTL_SPEED_MED | PAD_CTL_SRE | \
+				PAD_CTL_DSE_50ohm | PAD_CTL_PUS_47K_UP | \
+				PAD_CTL_OBE_IBE_ENABLE)
+#define VF610_NFC_CN_PAD_CTRL	(PAD_CTL_SPEED_MED | PAD_CTL_SRE | \
+				PAD_CTL_DSE_25ohm | PAD_CTL_OBE_ENABLE)
+#define VF610_NFC_RB_PAD_CTRL	(PAD_CTL_SPEED_MED | PAD_CTL_SRE | \
+				PAD_CTL_PUS_22K_UP | PAD_CTL_IBE_ENABLE)
 
 enum {
 	VF610_PAD_PTA6__RMII0_CLKIN		= IOMUX_PAD(0x0000, 0x0000, 2, __NA_, 0, VF610_ENET_PAD_CTRL),
+	VF610_PAD_PTA6__RMII0_CLKOUT		= IOMUX_PAD(0x0000, 0x0000, 1, __NA_, 0, VF610_ENET_PAD_CTRL),
 	VF610_PAD_PTB4__UART1_TX		= IOMUX_PAD(0x0068, 0x0068, 2, 0x0380, 0, VF610_UART_PAD_CTRL),
 	VF610_PAD_PTB5__UART1_RX		= IOMUX_PAD(0x006c, 0x006c, 2, 0x037c, 0, VF610_UART_PAD_CTRL),
+	VF610_PAD_PTB10__UART0_TX		= IOMUX_PAD(0x0080, 0x0080, 1, __NA_, 0, VF610_UART_PAD_CTRL),
+	VF610_PAD_PTB11__UART0_RX		= IOMUX_PAD(0x0084, 0x0084, 1, __NA_, 0, VF610_UART_PAD_CTRL),
 	VF610_PAD_PTC1__RMII0_MDIO		= IOMUX_PAD(0x00b8, 0x00b8, 1, __NA_, 0, VF610_ENET_PAD_CTRL),
 	VF610_PAD_PTC0__RMII0_MDC		= IOMUX_PAD(0x00b4, 0x00b4, 1, __NA_, 0, VF610_ENET_PAD_CTRL),
 	VF610_PAD_PTC2__RMII0_CRS_DV		= IOMUX_PAD(0x00bc, 0x00bc, 1, __NA_, 0, VF610_ENET_PAD_CTRL),
@@ -33,6 +43,15 @@ enum {
 	VF610_PAD_PTC6__RMII0_TD1		= IOMUX_PAD(0x00cc, 0x00cc, 1, __NA_, 0, VF610_ENET_PAD_CTRL),
 	VF610_PAD_PTC7__RMII0_TD0		= IOMUX_PAD(0x00D0, 0x00D0, 1, __NA_, 0, VF610_ENET_PAD_CTRL),
 	VF610_PAD_PTC8__RMII0_TXEN		= IOMUX_PAD(0x00D4, 0x00D4, 1, __NA_, 0, VF610_ENET_PAD_CTRL),
+	VF610_PAD_PTC10__RMII1_MDIO		= IOMUX_PAD(0x00dc, 0x00dc, 1, __NA_, 0, VF610_ENET_PAD_CTRL),
+	VF610_PAD_PTC9__RMII1_MDC		= IOMUX_PAD(0x00d8, 0x00d8, 1, __NA_, 0, VF610_ENET_PAD_CTRL),
+	VF610_PAD_PTC11__RMII1_CRS_DV		= IOMUX_PAD(0x00e0, 0x00e0, 1, __NA_, 0, VF610_ENET_PAD_CTRL),
+	VF610_PAD_PTC12__RMII1_RD1		= IOMUX_PAD(0x00e4, 0x00e4, 1, __NA_, 0, VF610_ENET_PAD_CTRL),
+	VF610_PAD_PTC13__RMII1_RD0		= IOMUX_PAD(0x00e8, 0x00e8, 1, __NA_, 0, VF610_ENET_PAD_CTRL),
+	VF610_PAD_PTC14__RMII1_RXER		= IOMUX_PAD(0x00ec, 0x00ec, 1, __NA_, 0, VF610_ENET_PAD_CTRL),
+	VF610_PAD_PTC15__RMII1_TD1		= IOMUX_PAD(0x00f0, 0x00f0, 1, __NA_, 0, VF610_ENET_PAD_CTRL),
+	VF610_PAD_PTC16__RMII1_TD0		= IOMUX_PAD(0x00f4, 0x00f4, 1, __NA_, 0, VF610_ENET_PAD_CTRL),
+	VF610_PAD_PTC17__RMII1_TXEN		= IOMUX_PAD(0x00f8, 0x00f8, 1, __NA_, 0, VF610_ENET_PAD_CTRL),
 	VF610_PAD_PTA24__ESDHC1_CLK		= IOMUX_PAD(0x0038, 0x0038, 5, __NA_, 0, VF610_SDHC_PAD_CTRL),
 	VF610_PAD_PTA25__ESDHC1_CMD		= IOMUX_PAD(0x003c, 0x003c, 5, __NA_, 0, VF610_SDHC_PAD_CTRL),
 	VF610_PAD_PTA26__ESDHC1_DAT0		= IOMUX_PAD(0x0040, 0x0040, 5, __NA_, 0, VF610_SDHC_PAD_CTRL),
@@ -41,6 +60,25 @@ enum {
 	VF610_PAD_PTA29__ESDHC1_DAT3		= IOMUX_PAD(0x004c, 0x004c, 5, __NA_, 0, VF610_SDHC_PAD_CTRL),
 	VF610_PAD_PTB14__I2C0_SCL		= IOMUX_PAD(0x0090, 0x0090, 2, 0x033c, 1, VF610_I2C_PAD_CTRL),
 	VF610_PAD_PTB15__I2C0_SDA		= IOMUX_PAD(0x0094, 0x0094, 2, 0x0340, 1, VF610_I2C_PAD_CTRL),
+	VF610_PAD_PTD23__NF_IO7			= IOMUX_PAD(0x011C, 0x011C, 2, __NA_, 0, VF610_NFC_IO_PAD_CTRL),
+	VF610_PAD_PTD22__NF_IO6			= IOMUX_PAD(0x0120, 0x0120, 2, __NA_, 0, VF610_NFC_IO_PAD_CTRL),
+	VF610_PAD_PTD21__NF_IO5			= IOMUX_PAD(0x0124, 0x0124, 2, __NA_, 0, VF610_NFC_IO_PAD_CTRL), 
+	VF610_PAD_PTD20__NF_IO4			= IOMUX_PAD(0x0128, 0x0128, 2, __NA_, 0, VF610_NFC_IO_PAD_CTRL), 
+	VF610_PAD_PTD19__NF_IO3			= IOMUX_PAD(0x012C, 0x012C, 2, __NA_, 0, VF610_NFC_IO_PAD_CTRL),
+	VF610_PAD_PTD18__NF_IO2			= IOMUX_PAD(0x0130, 0x0130, 2, __NA_, 0, VF610_NFC_IO_PAD_CTRL), 
+	VF610_PAD_PTD17__NF_IO1			= IOMUX_PAD(0x0134, 0x0134, 2, __NA_, 0, VF610_NFC_IO_PAD_CTRL),
+	VF610_PAD_PTD16__NF_IO0			= IOMUX_PAD(0x0138, 0x0138, 2, __NA_, 0, VF610_NFC_IO_PAD_CTRL),
+	VF610_PAD_PTB24__NF_WE_B		= IOMUX_PAD(0x0178, 0x0178, 5, __NA_, 0, VF610_NFC_CN_PAD_CTRL),
+	VF610_PAD_PTB25__NF_CE0_B		= IOMUX_PAD(0x017C, 0x017C, 5, __NA_, 0, VF610_NFC_CN_PAD_CTRL),
+
+	VF610_PAD_PTB27__NF_RE_B 		= IOMUX_PAD(0x0184, 0x0184, 6, __NA_, 0, VF610_NFC_CN_PAD_CTRL),
+
+	VF610_PAD_PTC26__NF_RB_B 		= IOMUX_PAD(0x018C, 0x018C, 5, __NA_, 0, VF610_NFC_RB_PAD_CTRL),
+
+	VF610_PAD_PTC27__NF_ALE  		= IOMUX_PAD(0x0190, 0x0190, 6, __NA_, 0, VF610_NFC_CN_PAD_CTRL),
+
+	VF610_PAD_PTC28__NF_CLE  		= IOMUX_PAD(0x0194, 0x0194, 6, __NA_, 0, VF610_NFC_CN_PAD_CTRL),
+
 	VF610_PAD_DDR_A15__DDR_A_15		= IOMUX_PAD(0x0220, 0x0220, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
 	VF610_PAD_DDR_A14__DDR_A_14		= IOMUX_PAD(0x0224, 0x0224, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
 	VF610_PAD_DDR_A13__DDR_A_13		= IOMUX_PAD(0x0228, 0x0228, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
diff --git a/arch/arm/include/asm/arch-zynq/clk.h b/arch/arm/include/asm/arch-zynq/clk.h
new file mode 100644
index 0000000000..250c5bc07b
--- /dev/null
+++ b/arch/arm/include/asm/arch-zynq/clk.h
@@ -0,0 +1,29 @@
+/*
+ * Copyright (c) 2013 Xilinx Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _ZYNQ_CLK_H_
+#define _ZYNQ_CLK_H_
+
+enum zynq_clk {
+	armpll_clk, ddrpll_clk, iopll_clk,
+	cpu_6or4x_clk, cpu_3or2x_clk, cpu_2x_clk, cpu_1x_clk,
+	ddr2x_clk, ddr3x_clk, dci_clk,
+	lqspi_clk, smc_clk, pcap_clk, gem0_clk, gem1_clk,
+	fclk0_clk, fclk1_clk, fclk2_clk, fclk3_clk, can0_clk, can1_clk,
+	sdio0_clk, sdio1_clk, uart0_clk, uart1_clk, spi0_clk, spi1_clk, dma_clk,
+	usb0_aper_clk, usb1_aper_clk, gem0_aper_clk, gem1_aper_clk,
+	sdio0_aper_clk, sdio1_aper_clk, spi0_aper_clk, spi1_aper_clk,
+	can0_aper_clk, can1_aper_clk, i2c0_aper_clk, i2c1_aper_clk,
+	uart0_aper_clk, uart1_aper_clk, gpio_aper_clk, lqspi_aper_clk,
+	smc_aper_clk, swdt_clk, dbg_trc_clk, dbg_apb_clk, clk_max};
+
+void zynq_clk_early_init(void);
+int zynq_clk_set_rate(enum zynq_clk clk, unsigned long rate);
+unsigned long zynq_clk_get_rate(enum zynq_clk clk);
+const char *zynq_clk_get_name(enum zynq_clk clk);
+unsigned long get_uart_clk(int dev_id);
+
+#endif
diff --git a/arch/arm/include/asm/arch-zynq/gpio.h b/arch/arm/include/asm/arch-zynq/gpio.h
new file mode 100644
index 0000000000..2dbba756d7
--- /dev/null
+++ b/arch/arm/include/asm/arch-zynq/gpio.h
@@ -0,0 +1,25 @@
+/*
+ * Copyright (c) 2013 Xilinx, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _ZYNQ_GPIO_H
+#define _ZYNQ_GPIO_H
+
+inline int gpio_get_value(unsigned gpio)
+{
+	return 0;
+}
+
+inline int gpio_set_value(unsigned gpio, int val)
+{
+	return 0;
+}
+
+inline int gpio_request(unsigned gpio, const char *label)
+{
+	return 0;
+}
+
+#endif /* _ZYNQ_GPIO_H */
diff --git a/arch/arm/include/asm/arch-zynq/hardware.h b/arch/arm/include/asm/arch-zynq/hardware.h
index cd69677729..39184da40e 100644
--- a/arch/arm/include/asm/arch-zynq/hardware.h
+++ b/arch/arm/include/asm/arch-zynq/hardware.h
@@ -7,6 +7,8 @@
 #ifndef _ASM_ARCH_HARDWARE_H
 #define _ASM_ARCH_HARDWARE_H
 
+#define ZYNQ_SERIAL_BASEADDR0		0xE0000000
+#define ZYNQ_SERIAL_BASEADDR1		0xE0001000
 #define ZYNQ_SYS_CTRL_BASEADDR		0xF8000000
 #define ZYNQ_DEV_CFG_APB_BASEADDR	0xF8007000
 #define ZYNQ_SCU_BASEADDR		0xF8F00000
@@ -21,17 +23,51 @@
 #define ZYNQ_SPI_BASEADDR1		0xE0007000
 #define ZYNQ_DDRC_BASEADDR		0xF8006000
 
+/* Bootmode setting values */
+#define ZYNQ_BM_MASK		0xF
+#define ZYNQ_BM_NOR		0x2
+#define ZYNQ_BM_SD		0x5
+#define ZYNQ_BM_JTAG		0x0
+
 /* Reflect slcr offsets */
 struct slcr_regs {
 	u32 scl; /* 0x0 */
 	u32 slcr_lock; /* 0x4 */
 	u32 slcr_unlock; /* 0x8 */
-	u32 reserved0[75];
+	u32 reserved0_1[61];
+	u32 arm_pll_ctrl; /* 0x100 */
+	u32 ddr_pll_ctrl; /* 0x104 */
+	u32 io_pll_ctrl; /* 0x108 */
+	u32 reserved0_2[5];
+	u32 arm_clk_ctrl; /* 0x120 */
+	u32 ddr_clk_ctrl; /* 0x124 */
+	u32 dci_clk_ctrl; /* 0x128 */
+	u32 aper_clk_ctrl; /* 0x12c */
+	u32 reserved0_3[2];
 	u32 gem0_rclk_ctrl; /* 0x138 */
 	u32 gem1_rclk_ctrl; /* 0x13c */
 	u32 gem0_clk_ctrl; /* 0x140 */
 	u32 gem1_clk_ctrl; /* 0x144 */
-	u32 reserved1[46];
+	u32 smc_clk_ctrl; /* 0x148 */
+	u32 lqspi_clk_ctrl; /* 0x14c */
+	u32 sdio_clk_ctrl; /* 0x150 */
+	u32 uart_clk_ctrl; /* 0x154 */
+	u32 spi_clk_ctrl; /* 0x158 */
+	u32 can_clk_ctrl; /* 0x15c */
+	u32 can_mioclk_ctrl; /* 0x160 */
+	u32 dbg_clk_ctrl; /* 0x164 */
+	u32 pcap_clk_ctrl; /* 0x168 */
+	u32 reserved0_4[1];
+	u32 fpga0_clk_ctrl; /* 0x170 */
+	u32 reserved0_5[3];
+	u32 fpga1_clk_ctrl; /* 0x180 */
+	u32 reserved0_6[3];
+	u32 fpga2_clk_ctrl; /* 0x190 */
+	u32 reserved0_7[3];
+	u32 fpga3_clk_ctrl; /* 0x1a0 */
+	u32 reserved0_8[8];
+	u32 clk_621_true; /* 0x1c4 */
+	u32 reserved1[14];
 	u32 pss_rst_ctrl; /* 0x200 */
 	u32 reserved2[15];
 	u32 fpga_rst_ctrl; /* 0x240 */
diff --git a/arch/arm/include/asm/arch-zynq/spl.h b/arch/arm/include/asm/arch-zynq/spl.h
new file mode 100644
index 0000000000..5789d28bb3
--- /dev/null
+++ b/arch/arm/include/asm/arch-zynq/spl.h
@@ -0,0 +1,18 @@
+/*
+ * (C) Copyright 2014 Xilinx, Inc. Michal Simek
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+#ifndef	_ASM_ARCH_SPL_H_
+#define	_ASM_ARCH_SPL_H_
+
+extern void ps7_init(void);
+
+#define BOOT_DEVICE_NONE	0
+#define BOOT_DEVICE_RAM		1
+#define BOOT_DEVICE_SPI		2
+#define BOOT_DEVICE_MMC1	3
+#define BOOT_DEVICE_MMC2	4
+#define BOOT_DEVICE_MMC2_2	5
+
+#endif
diff --git a/arch/arm/include/asm/arch-zynq/sys_proto.h b/arch/arm/include/asm/arch-zynq/sys_proto.h
index 110de90922..a68e1b3d23 100644
--- a/arch/arm/include/asm/arch-zynq/sys_proto.h
+++ b/arch/arm/include/asm/arch-zynq/sys_proto.h
@@ -10,13 +10,15 @@
 extern void zynq_slcr_lock(void);
 extern void zynq_slcr_unlock(void);
 extern void zynq_slcr_cpu_reset(void);
-extern void zynq_slcr_gem_clk_setup(u32 gem_id, u32 rclk, u32 clk);
+extern void zynq_slcr_gem_clk_setup(u32 gem_id, unsigned long clk_rate);
 extern void zynq_slcr_devcfg_disable(void);
 extern void zynq_slcr_devcfg_enable(void);
+extern u32 zynq_slcr_get_boot_mode(void);
 extern u32 zynq_slcr_get_idcode(void);
 extern void zynq_ddrc_init(void);
 
 /* Driver extern functions */
 extern int zynq_sdhci_init(u32 regbase);
+extern int zynq_sdhci_of_init(const void *blob);
 
 #endif /* _SYS_PROTO_H_ */
diff --git a/arch/arm/include/asm/armv8/mmu.h b/arch/arm/include/asm/armv8/mmu.h
new file mode 100644
index 0000000000..1193e76a82
--- /dev/null
+++ b/arch/arm/include/asm/armv8/mmu.h
@@ -0,0 +1,111 @@
+/*
+ * (C) Copyright 2013
+ * David Feng <fenghua@phytium.com.cn>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _ASM_ARMV8_MMU_H_
+#define _ASM_ARMV8_MMU_H_
+
+#ifdef __ASSEMBLY__
+#define _AC(X, Y)	X
+#else
+#define _AC(X, Y)	(X##Y)
+#endif
+
+#define UL(x)		_AC(x, UL)
+
+/***************************************************************/
+/*
+ * The following definitions are related each other, shoud be
+ * calculated specifically.
+ */
+#define VA_BITS			(42)	/* 42 bits virtual address */
+
+/* PAGE_SHIFT determines the page size */
+#undef  PAGE_SIZE
+#define PAGE_SHIFT		16
+#define PAGE_SIZE		(1 << PAGE_SHIFT)
+#define PAGE_MASK		(~(PAGE_SIZE-1))
+
+/*
+ * section address mask and size definitions.
+ */
+#define SECTION_SHIFT		29
+#define SECTION_SIZE		(UL(1) << SECTION_SHIFT)
+#define SECTION_MASK		(~(SECTION_SIZE-1))
+/***************************************************************/
+
+/*
+ * Memory types
+ */
+#define MT_DEVICE_NGNRNE	0
+#define MT_DEVICE_NGNRE		1
+#define MT_DEVICE_GRE		2
+#define MT_NORMAL_NC		3
+#define MT_NORMAL		4
+
+#define MEMORY_ATTRIBUTES	((0x00 << (MT_DEVICE_NGNRNE*8)) |	\
+				(0x04 << (MT_DEVICE_NGNRE*8)) |		\
+				(0x0c << (MT_DEVICE_GRE*8)) |		\
+				(0x44 << (MT_NORMAL_NC*8)) |		\
+				(UL(0xff) << (MT_NORMAL*8)))
+
+/*
+ * Hardware page table definitions.
+ *
+ * Level 2 descriptor (PMD).
+ */
+#define PMD_TYPE_MASK		(3 << 0)
+#define PMD_TYPE_FAULT		(0 << 0)
+#define PMD_TYPE_TABLE		(3 << 0)
+#define PMD_TYPE_SECT		(1 << 0)
+
+/*
+ * Section
+ */
+#define PMD_SECT_S		(3 << 8)
+#define PMD_SECT_AF		(1 << 10)
+#define PMD_SECT_NG		(1 << 11)
+#define PMD_SECT_PXN		(UL(1) << 53)
+#define PMD_SECT_UXN		(UL(1) << 54)
+
+/*
+ * AttrIndx[2:0]
+ */
+#define PMD_ATTRINDX(t)		((t) << 2)
+#define PMD_ATTRINDX_MASK	(7 << 2)
+
+/*
+ * TCR flags.
+ */
+#define TCR_T0SZ(x)		((64 - (x)) << 0)
+#define TCR_IRGN_NC		(0 << 8)
+#define TCR_IRGN_WBWA		(1 << 8)
+#define TCR_IRGN_WT		(2 << 8)
+#define TCR_IRGN_WBNWA		(3 << 8)
+#define TCR_IRGN_MASK		(3 << 8)
+#define TCR_ORGN_NC		(0 << 10)
+#define TCR_ORGN_WBWA		(1 << 10)
+#define TCR_ORGN_WT		(2 << 10)
+#define TCR_ORGN_WBNWA		(3 << 10)
+#define TCR_ORGN_MASK		(3 << 10)
+#define TCR_SHARED_NON		(0 << 12)
+#define TCR_SHARED_OUTER	(1 << 12)
+#define TCR_SHARED_INNER	(2 << 12)
+#define TCR_TG0_4K		(0 << 14)
+#define TCR_TG0_64K		(1 << 14)
+#define TCR_TG0_16K		(2 << 14)
+#define TCR_EL1_IPS_BITS	(UL(3) << 32)	/* 42 bits physical address */
+#define TCR_EL2_IPS_BITS	(3 << 16)	/* 42 bits physical address */
+#define TCR_EL3_IPS_BITS	(3 << 16)	/* 42 bits physical address */
+
+/* PTWs cacheable, inner/outer WBWA and non-shareable */
+#define TCR_FLAGS		(TCR_TG0_64K |		\
+				TCR_SHARED_NON |	\
+				TCR_ORGN_WBWA |		\
+				TCR_IRGN_WBWA |		\
+				TCR_T0SZ(VA_BITS))
+
+#endif /* _ASM_ARMV8_MMU_H_ */
diff --git a/arch/arm/include/asm/atomic.h b/arch/arm/include/asm/atomic.h
index ba9e4b72d8..1b22eeb5fc 100644
--- a/arch/arm/include/asm/atomic.h
+++ b/arch/arm/include/asm/atomic.h
@@ -16,8 +16,6 @@
 #ifndef __ASM_ARM_ATOMIC_H
 #define __ASM_ARM_ATOMIC_H
 
-#include <linux/config.h>
-
 #ifdef CONFIG_SMP
 #error SMP not supported
 #endif
diff --git a/arch/arm/include/asm/byteorder.h b/arch/arm/include/asm/byteorder.h
index c3489f1e1f..20cce7657e 100644
--- a/arch/arm/include/asm/byteorder.h
+++ b/arch/arm/include/asm/byteorder.h
@@ -23,7 +23,7 @@
 #  define __SWAB_64_THRU_32__
 #endif
 
-#ifdef __ARMEB__
+#if defined(__ARMEB__) || defined(__AARCH64EB__)
 #include <linux/byteorder/big_endian.h>
 #else
 #include <linux/byteorder/little_endian.h>
diff --git a/arch/arm/include/asm/cache.h b/arch/arm/include/asm/cache.h
index 6d60a4a6d9..ddebbc8fcd 100644
--- a/arch/arm/include/asm/cache.h
+++ b/arch/arm/include/asm/cache.h
@@ -11,6 +11,8 @@
 
 #include <asm/system.h>
 
+#ifndef CONFIG_ARM64
+
 /*
  * Invalidate L2 Cache using co-proc instruction
  */
@@ -28,6 +30,9 @@ void l2_cache_disable(void);
 void set_section_dcache(int section, enum dcache_option option);
 
 void dram_bank_mmu_setup(int bank);
+
+#endif
+
 /*
  * The current upper bound for ARM L1 data cache line sizes is 64 bytes.  We
  * use that value for aligning DMA buffers unless the board config has specified
diff --git a/arch/arm/include/asm/config.h b/arch/arm/include/asm/config.h
index 99b703e1e4..abf79e5c9e 100644
--- a/arch/arm/include/asm/config.h
+++ b/arch/arm/include/asm/config.h
@@ -9,4 +9,10 @@
 
 #define CONFIG_LMB
 #define CONFIG_SYS_BOOT_RAMDISK_HIGH
+
+#ifdef CONFIG_ARM64
+#define CONFIG_PHYS_64BIT
+#define CONFIG_STATIC_RELA
+#endif
+
 #endif
diff --git a/arch/arm/include/asm/davinci_rtc.h b/arch/arm/include/asm/davinci_rtc.h
new file mode 100644
index 0000000000..575b590888
--- /dev/null
+++ b/arch/arm/include/asm/davinci_rtc.h
@@ -0,0 +1,52 @@
+/*
+ * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
+ *
+ * Based on:
+ *
+ * -------------------------------------------------------------------------
+ *
+ *  linux/include/asm-arm/arch-davinci/hardware.h
+ *
+ *  Copyright (C) 2006 Texas Instruments.
+ *
+ * SPDX-License-Identifier:	GPL-2.0
+ */
+#ifndef __ASM_DAVINCI_RTC_H
+#define __ASM_DAVINCI_RTC_H
+
+struct davinci_rtc {
+	unsigned int	second;
+	unsigned int	minutes;
+	unsigned int	hours;
+	unsigned int	day;
+	unsigned int	month; /* 0x10 */
+	unsigned int	year;
+	unsigned int	dotw;
+	unsigned int	resv1;
+	unsigned int	alarmsecond; /* 0x20 */
+	unsigned int	alarmminute;
+	unsigned int	alarmhour;
+	unsigned int	alarmday;
+	unsigned int	alarmmonth; /* 0x30 */
+	unsigned int	alarmyear;
+	unsigned int	resv2[2];
+	unsigned int	ctrl; /* 0x40 */
+	unsigned int	status;
+	unsigned int	irq;
+	unsigned int	complsb;
+	unsigned int	compmsb; /* 0x50 */
+	unsigned int	osc;
+	unsigned int	resv3[2];
+	unsigned int	scratch0; /* 0x60 */
+	unsigned int	scratch1;
+	unsigned int	scratch2;
+	unsigned int	kick0r;
+	unsigned int	kick1r; /* 0x70 */
+};
+
+#define RTC_STATE_BUSY	0x01
+#define RTC_STATE_RUN	0x02
+
+#define RTC_KICK0R_WE	0x83e70b13
+#define RTC_KICK1R_WE	0x95a4f1e0
+#endif
diff --git a/arch/arm/include/asm/ehci-omap.h b/arch/arm/include/asm/ehci-omap.h
index ac83a539a8..c7bca05682 100644
--- a/arch/arm/include/asm/ehci-omap.h
+++ b/arch/arm/include/asm/ehci-omap.h
@@ -145,8 +145,8 @@ struct omap_ehci {
 struct ehci_hccr;
 struct ehci_hcor;
 
-int omap_ehci_hcd_init(struct omap_usbhs_board_data *usbhs_pdata,
-		struct ehci_hccr **hccr, struct ehci_hcor **hcor);
+int omap_ehci_hcd_init(int index, struct omap_usbhs_board_data *usbhs_pdata,
+		       struct ehci_hccr **hccr, struct ehci_hcor **hcor);
 int omap_ehci_hcd_stop(void);
 
 #endif /* _OMAP_COMMON_EHCI_H_ */
diff --git a/arch/arm/include/asm/emif.h b/arch/arm/include/asm/emif.h
index 1b94a99c54..45668ca4dd 100644
--- a/arch/arm/include/asm/emif.h
+++ b/arch/arm/include/asm/emif.h
@@ -14,11 +14,15 @@
 #define _EMIF_H_
 #include <asm/types.h>
 #include <common.h>
+#include <asm/io.h>
 
 /* Base address */
 #define EMIF1_BASE				0x4c000000
 #define EMIF2_BASE				0x4d000000
 
+#define EMIF_4D					0x4
+#define EMIF_4D5				0x5
+
 /* Registers shifts, masks and values */
 
 /* EMIF_MOD_ID_REV */
@@ -581,7 +585,6 @@
 	(0xFF << EMIF_SYS_ADDR_SHIFT))
 
 #define EMIF_EXT_PHY_CTRL_TIMING_REG	0x5
-#define EMIF_EXT_PHY_CTRL_CONST_REG	0x14
 
 /* Reg mapping structure */
 struct emif_reg_struct {
@@ -641,7 +644,9 @@ struct emif_reg_struct {
 	u32 emif_ddr_phy_ctrl_2;
 	u32 padding7[12];
 	u32 emif_rd_wr_exec_thresh;
-	u32 padding8[55];
+	u32 padding8[7];
+	u32 emif_ddr_phy_status[21];
+	u32 padding9[27];
 	u32 emif_ddr_ext_phy_ctrl_1;
 	u32 emif_ddr_ext_phy_ctrl_1_shdw;
 	u32 emif_ddr_ext_phy_ctrl_2;
@@ -690,6 +695,9 @@ struct emif_reg_struct {
 	u32 emif_ddr_ext_phy_ctrl_23_shdw;
 	u32 emif_ddr_ext_phy_ctrl_24;
 	u32 emif_ddr_ext_phy_ctrl_24_shdw;
+	u32 padding[22];
+	u32 emif_ddr_fifo_misaligned_clear_1;
+	u32 emif_ddr_fifo_misaligned_clear_2;
 };
 
 struct dmm_lisa_map_regs {
@@ -1139,6 +1147,33 @@ struct lpddr2_mr_regs {
 	s8 mr16;
 };
 
+struct read_write_regs {
+	u32 read_reg;
+	u32 write_reg;
+};
+
+static inline u32 get_emif_rev(u32 base)
+{
+	struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
+
+	return (readl(&emif->emif_mod_id_rev) & EMIF_REG_MAJOR_REVISION_MASK)
+		>> EMIF_REG_MAJOR_REVISION_SHIFT;
+}
+
+/*
+ * Get SDRAM type connected to EMIF.
+ * Assuming similar SDRAM parts are connected to both EMIF's
+ * which is typically the case. So it is sufficient to get
+ * SDRAM type from EMIF1.
+ */
+static inline u32 emif_sdram_type(void)
+{
+	struct emif_reg_struct *emif = (struct emif_reg_struct *)EMIF1_BASE;
+
+	return (readl(&emif->emif_sdram_config) &
+		EMIF_REG_SDRAM_TYPE_MASK) >> EMIF_REG_SDRAM_TYPE_SHIFT;
+}
+
 /* assert macros */
 #if defined(DEBUG)
 #define emif_assert(c)	({ if (!(c)) for (;;); })
@@ -1167,4 +1202,5 @@ extern u32 *const T_den;
 
 void config_data_eye_leveling_samples(u32 emif_base);
 u32 emif_sdram_type(void);
+const struct read_write_regs *get_bug_regs(u32 *iterations);
 #endif
diff --git a/arch/arm/include/asm/gic.h b/arch/arm/include/asm/gic.h
index a0891cc09c..bd3a80cdf7 100644
--- a/arch/arm/include/asm/gic.h
+++ b/arch/arm/include/asm/gic.h
@@ -1,19 +1,110 @@
-#ifndef __GIC_V2_H__
-#define __GIC_V2_H__
+#ifndef __GIC_H__
+#define __GIC_H__
 
-/* register offsets for the ARM generic interrupt controller (GIC) */
+/* Register offsets for the ARM generic interrupt controller (GIC) */
 
 #define GIC_DIST_OFFSET		0x1000
+#define GIC_CPU_OFFSET_A9	0x0100
+#define GIC_CPU_OFFSET_A15	0x2000
+
+/* Distributor Registers */
 #define GICD_CTLR		0x0000
 #define GICD_TYPER		0x0004
+#define GICD_IIDR		0x0008
+#define GICD_STATUSR		0x0010
+#define GICD_SETSPI_NSR		0x0040
+#define GICD_CLRSPI_NSR		0x0048
+#define GICD_SETSPI_SR		0x0050
+#define GICD_CLRSPI_SR		0x0058
+#define GICD_SEIR		0x0068
 #define GICD_IGROUPRn		0x0080
-#define GICD_SGIR		0x0F00
+#define GICD_ISENABLERn		0x0100
+#define GICD_ICENABLERn		0x0180
+#define GICD_ISPENDRn		0x0200
+#define GICD_ICPENDRn		0x0280
+#define GICD_ISACTIVERn		0x0300
+#define GICD_ICACTIVERn		0x0380
+#define GICD_IPRIORITYRn	0x0400
+#define GICD_ITARGETSRn		0x0800
+#define GICD_ICFGR		0x0c00
+#define GICD_IGROUPMODRn	0x0d00
+#define GICD_NSACRn		0x0e00
+#define GICD_SGIR		0x0f00
+#define GICD_CPENDSGIRn		0x0f10
+#define GICD_SPENDSGIRn		0x0f20
+#define GICD_IROUTERn		0x6000
 
-#define GIC_CPU_OFFSET_A9	0x0100
-#define GIC_CPU_OFFSET_A15	0x2000
+/* Cpu Interface Memory Mapped Registers */
 #define GICC_CTLR		0x0000
 #define GICC_PMR		0x0004
+#define GICC_BPR		0x0008
 #define GICC_IAR		0x000C
 #define GICC_EOIR		0x0010
+#define GICC_RPR		0x0014
+#define GICC_HPPIR		0x0018
+#define GICC_ABPR		0x001c
+#define GICC_AIAR		0x0020
+#define GICC_AEOIR		0x0024
+#define GICC_AHPPIR		0x0028
+#define GICC_APRn		0x00d0
+#define GICC_NSAPRn		0x00e0
+#define GICC_IIDR		0x00fc
+#define GICC_DIR		0x1000
+
+/* ReDistributor Registers for Control and Physical LPIs */
+#define GICR_CTLR		0x0000
+#define GICR_IIDR		0x0004
+#define GICR_TYPER		0x0008
+#define GICR_STATUSR		0x0010
+#define GICR_WAKER		0x0014
+#define GICR_SETLPIR		0x0040
+#define GICR_CLRLPIR		0x0048
+#define GICR_SEIR		0x0068
+#define GICR_PROPBASER		0x0070
+#define GICR_PENDBASER		0x0078
+#define GICR_INVLPIR		0x00a0
+#define GICR_INVALLR		0x00b0
+#define GICR_SYNCR		0x00c0
+#define GICR_MOVLPIR		0x0100
+#define GICR_MOVALLR		0x0110
+
+/* ReDistributor Registers for SGIs and PPIs */
+#define GICR_IGROUPRn		0x0080
+#define GICR_ISENABLERn		0x0100
+#define GICR_ICENABLERn		0x0180
+#define GICR_ISPENDRn		0x0200
+#define GICR_ICPENDRn		0x0280
+#define GICR_ISACTIVERn		0x0300
+#define GICR_ICACTIVERn		0x0380
+#define GICR_IPRIORITYRn	0x0400
+#define GICR_ICFGR0		0x0c00
+#define GICR_ICFGR1		0x0c04
+#define GICR_IGROUPMODRn	0x0d00
+#define GICR_NSACRn		0x0e00
+
+/* Cpu Interface System Registers */
+#define ICC_IAR0_EL1		S3_0_C12_C8_0
+#define ICC_IAR1_EL1		S3_0_C12_C12_0
+#define ICC_EOIR0_EL1		S3_0_C12_C8_1
+#define ICC_EOIR1_EL1		S3_0_C12_C12_1
+#define ICC_HPPIR0_EL1		S3_0_C12_C8_2
+#define ICC_HPPIR1_EL1		S3_0_C12_C12_2
+#define ICC_BPR0_EL1		S3_0_C12_C8_3
+#define ICC_BPR1_EL1		S3_0_C12_C12_3
+#define ICC_DIR_EL1		S3_0_C12_C11_1
+#define ICC_PMR_EL1		S3_0_C4_C6_0
+#define ICC_RPR_EL1		S3_0_C12_C11_3
+#define ICC_CTLR_EL1		S3_0_C12_C12_4
+#define ICC_CTLR_EL3		S3_6_C12_C12_4
+#define ICC_SRE_EL1		S3_0_C12_C12_5
+#define ICC_SRE_EL2		S3_4_C12_C9_5
+#define ICC_SRE_EL3		S3_6_C12_C12_5
+#define ICC_IGRPEN0_EL1		S3_0_C12_C12_6
+#define ICC_IGRPEN1_EL1		S3_0_C12_C12_7
+#define ICC_IGRPEN1_EL3		S3_6_C12_C12_7
+#define ICC_SEIEN_EL1		S3_0_C12_C13_0
+#define ICC_SGI0R_EL1		S3_0_C12_C11_7
+#define ICC_SGI1R_EL1		S3_0_C12_C11_5
+#define ICC_ASGI1R_EL1		S3_0_C12_C11_6
 
-#endif
+#endif /* __GIC_H__ */
diff --git a/arch/arm/include/asm/global_data.h b/arch/arm/include/asm/global_data.h
index e126436093..63e4ad5a67 100644
--- a/arch/arm/include/asm/global_data.h
+++ b/arch/arm/include/asm/global_data.h
@@ -32,9 +32,6 @@ struct arch_global_data {
 	unsigned long tbl;
 	unsigned long lastinc;
 	unsigned long long timer_reset_value;
-#ifdef CONFIG_IXP425
-	unsigned long timestamp;
-#endif
 #if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF))
 	unsigned long tlb_addr;
 	unsigned long tlb_size;
@@ -47,6 +44,10 @@ struct arch_global_data {
 
 #include <asm-generic/global_data.h>
 
-#define DECLARE_GLOBAL_DATA_PTR     register volatile gd_t *gd asm ("r9")
+#ifdef CONFIG_ARM64
+#define DECLARE_GLOBAL_DATA_PTR		register volatile gd_t *gd asm ("x18")
+#else
+#define DECLARE_GLOBAL_DATA_PTR		register volatile gd_t *gd asm ("r9")
+#endif
 
 #endif /* __ASM_GBL_DATA_H */
diff --git a/arch/arm/include/asm/imx-common/iomux-v3.h b/arch/arm/include/asm/imx-common/iomux-v3.h
index dc2b3ef47a..64226493f1 100644
--- a/arch/arm/include/asm/imx-common/iomux-v3.h
+++ b/arch/arm/include/asm/imx-common/iomux-v3.h
@@ -63,6 +63,8 @@ typedef u64 iomux_v3_cfg_t;
 #define MUX_SEL_INPUT_SHIFT	59
 #define MUX_SEL_INPUT_MASK	((iomux_v3_cfg_t)0xf << MUX_SEL_INPUT_SHIFT)
 
+#define MUX_MODE_SION		((iomux_v3_cfg_t)IOMUX_CONFIG_SION << \
+	MUX_MODE_SHIFT)
 #define MUX_PAD_CTRL(x)		((iomux_v3_cfg_t)(x) << MUX_PAD_CTRL_SHIFT)
 
 #define IOMUX_PAD(pad_ctrl_ofs, mux_ctrl_ofs, mux_mode, sel_input_ofs,	\
@@ -116,16 +118,21 @@ typedef u64 iomux_v3_cfg_t;
 #define PAD_CTL_SPEED_MED	(1 << 12)
 #define PAD_CTL_SPEED_HIGH	(3 << 12)
 
+#define PAD_CTL_SRE		(1 << 11)
+
 #define PAD_CTL_DSE_50ohm	(3 << 6)
 #define PAD_CTL_DSE_25ohm	(6 << 6)
 #define PAD_CTL_DSE_20ohm	(7 << 6)
 
 #define PAD_CTL_PUS_47K_UP	(1 << 4 | PAD_CTL_PUE)
 #define PAD_CTL_PUS_100K_UP	(2 << 4 | PAD_CTL_PUE)
+#define PAD_CTL_PUS_22K_UP	(3 << 4 | PAD_CTL_PUE)
 #define PAD_CTL_PKE		(1 << 3)
 #define PAD_CTL_PUE		(1 << 2 | PAD_CTL_PKE)
 
 #define PAD_CTL_OBE_IBE_ENABLE	(3 << 0)
+#define PAD_CTL_OBE_ENABLE	(1 << 1)
+#define PAD_CTL_IBE_ENABLE	(1 << 0)
 
 #else
 
diff --git a/arch/arm/include/asm/imx-common/sata.h b/arch/arm/include/asm/imx-common/sata.h
new file mode 100644
index 0000000000..6b864cbd11
--- /dev/null
+++ b/arch/arm/include/asm/imx-common/sata.h
@@ -0,0 +1,16 @@
+/*
+ * Copyright 2011 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __IMX_SATA_H_
+#define __IMX_SATA_H_
+
+/*
+ * SATA setup for i.mx6 quad based platform
+ */
+
+int setup_sata(void);
+
+#endif
diff --git a/arch/arm/include/asm/io.h b/arch/arm/include/asm/io.h
index 1fbc531a08..6a1f05ac3e 100644
--- a/arch/arm/include/asm/io.h
+++ b/arch/arm/include/asm/io.h
@@ -75,42 +75,45 @@ static inline phys_addr_t virt_to_phys(void * vaddr)
 #define __arch_putw(v,a)		(*(volatile unsigned short *)(a) = (v))
 #define __arch_putl(v,a)		(*(volatile unsigned int *)(a) = (v))
 
-extern inline void __raw_writesb(unsigned int addr, const void *data, int bytelen)
+extern inline void __raw_writesb(unsigned long addr, const void *data,
+				 int bytelen)
 {
 	uint8_t *buf = (uint8_t *)data;
 	while(bytelen--)
 		__arch_putb(*buf++, addr);
 }
 
-extern inline void __raw_writesw(unsigned int addr, const void *data, int wordlen)
+extern inline void __raw_writesw(unsigned long addr, const void *data,
+				 int wordlen)
 {
 	uint16_t *buf = (uint16_t *)data;
 	while(wordlen--)
 		__arch_putw(*buf++, addr);
 }
 
-extern inline void __raw_writesl(unsigned int addr, const void *data, int longlen)
+extern inline void __raw_writesl(unsigned long addr, const void *data,
+				 int longlen)
 {
 	uint32_t *buf = (uint32_t *)data;
 	while(longlen--)
 		__arch_putl(*buf++, addr);
 }
 
-extern inline void __raw_readsb(unsigned int addr, void *data, int bytelen)
+extern inline void __raw_readsb(unsigned long addr, void *data, int bytelen)
 {
 	uint8_t *buf = (uint8_t *)data;
 	while(bytelen--)
 		*buf++ = __arch_getb(addr);
 }
 
-extern inline void __raw_readsw(unsigned int addr, void *data, int wordlen)
+extern inline void __raw_readsw(unsigned long addr, void *data, int wordlen)
 {
 	uint16_t *buf = (uint16_t *)data;
 	while(wordlen--)
 		*buf++ = __arch_getw(addr);
 }
 
-extern inline void __raw_readsl(unsigned int addr, void *data, int longlen)
+extern inline void __raw_readsl(unsigned long addr, void *data, int longlen)
 {
 	uint32_t *buf = (uint32_t *)data;
 	while(longlen--)
diff --git a/arch/arm/include/asm/kona-common/clk.h b/arch/arm/include/asm/kona-common/clk.h
new file mode 100644
index 0000000000..2c7e829994
--- /dev/null
+++ b/arch/arm/include/asm/kona-common/clk.h
@@ -0,0 +1,29 @@
+/*
+ * Copyright 2013 Broadcom Corporation.
+ *
+ * SPDX-License-Identifier:      GPL-2.0+
+ */
+
+/* This API file is loosely based on u-boot/drivers/video/ipu.h and linux */
+
+#ifndef __KONA_COMMON_CLK_H
+#define __KONA_COMMON_CLK_H
+
+#include <linux/types.h>
+
+struct clk;
+
+/* Only implement required functions for your specific architecture */
+int clk_init(void);
+struct clk *clk_get(const char *id);
+int clk_enable(struct clk *clk);
+void clk_disable(struct clk *clk);
+unsigned long clk_get_rate(struct clk *clk);
+long clk_round_rate(struct clk *clk, unsigned long rate);
+int clk_set_rate(struct clk *clk, unsigned long rate);
+int clk_set_parent(struct clk *clk, struct clk *parent);
+struct clk *clk_get_parent(struct clk *clk);
+int clk_sdio_enable(void *base, u32 rate, u32 *actual_ratep);
+int clk_bsc_enable(void *base);
+
+#endif
diff --git a/arch/arm/include/asm/kona-common/kona_sdhci.h b/arch/arm/include/asm/kona-common/kona_sdhci.h
new file mode 100644
index 0000000000..1ff0e55d13
--- /dev/null
+++ b/arch/arm/include/asm/kona-common/kona_sdhci.h
@@ -0,0 +1,12 @@
+/*
+ * Copyright 2013 Broadcom Corporation.
+ *
+ * SPDX-License-Identifier:      GPL-2.0+
+ */
+
+#ifndef __KONA_SDHCI_H
+#define __KONA_SDHCI_H
+
+int kona_sdhci_init(int dev_index, u32 min_clk, u32 quirks);
+
+#endif
diff --git a/arch/arm/include/asm/mach-types.h b/arch/arm/include/asm/mach-types.h
index 440b041a16..266b37cea2 100644
--- a/arch/arm/include/asm/mach-types.h
+++ b/arch/arm/include/asm/mach-types.h
@@ -1106,6 +1106,8 @@ extern unsigned int __machine_arch_type;
 #define MACH_TYPE_OMAP5_SEVM           3777
 #define MACH_TYPE_ARMADILLO_800EVA     3863
 #define MACH_TYPE_KZM9G                4140
+#define MACH_TYPE_COLIBRI_VF50         4749
+#define MACH_TYPE_COLIBRI_VF61         4750
 
 #ifdef CONFIG_ARCH_EBSA110
 # ifdef machine_arch_type
@@ -14235,6 +14237,30 @@ extern unsigned int __machine_arch_type;
 # define machine_is_kzm9g()	(0)
 #endif
 
+#ifdef CONFIG_MACH_COLIBRI_VF50
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type __machine_arch_type
+# else
+#  define machine_arch_type MACH_TYPE_COLIBRI_VF50
+# endif
+# define machine_is_colibri_vf50()	(machine_arch_type == MACH_TYPE_COLIBRI_VF50)
+#else
+# define machine_is_colibri_vf50()	(0)
+#endif
+
+#ifdef CONFIG_MACH_COLIBRI_VF61
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type __machine_arch_type
+# else
+#  define machine_arch_type MACH_TYPE_COLIBRI_VF61
+# endif
+# define machine_is_colibri_vf61()	(machine_arch_type == MACH_TYPE_COLIBRI_VF61)
+#else
+# define machine_is_colibri_vf61()	(0)
+#endif
+
 /*
  * These have not yet been registered
  */
diff --git a/arch/arm/include/asm/macro.h b/arch/arm/include/asm/macro.h
index ff13f36ba0..f77e4b880e 100644
--- a/arch/arm/include/asm/macro.h
+++ b/arch/arm/include/asm/macro.h
@@ -54,5 +54,58 @@
 	bcs	1b
 .endm
 
+#ifdef CONFIG_ARM64
+/*
+ * Register aliases.
+ */
+lr	.req	x30
+
+/*
+ * Branch according to exception level
+ */
+.macro	switch_el, xreg, el3_label, el2_label, el1_label
+	mrs	\xreg, CurrentEL
+	cmp	\xreg, 0xc
+	b.eq	\el3_label
+	cmp	\xreg, 0x8
+	b.eq	\el2_label
+	cmp	\xreg, 0x4
+	b.eq	\el1_label
+.endm
+
+/*
+ * Branch if current processor is a slave,
+ * choose processor with all zero affinity value as the master.
+ */
+.macro	branch_if_slave, xreg, slave_label
+	mrs	\xreg, mpidr_el1
+	tst	\xreg, #0xff		/* Test Affinity 0 */
+	b.ne	\slave_label
+	lsr	\xreg, \xreg, #8
+	tst	\xreg, #0xff		/* Test Affinity 1 */
+	b.ne	\slave_label
+	lsr	\xreg, \xreg, #8
+	tst	\xreg, #0xff		/* Test Affinity 2 */
+	b.ne	\slave_label
+	lsr	\xreg, \xreg, #16
+	tst	\xreg, #0xff		/* Test Affinity 3 */
+	b.ne	\slave_label
+.endm
+
+/*
+ * Branch if current processor is a master,
+ * choose processor with all zero affinity value as the master.
+ */
+.macro	branch_if_master, xreg1, xreg2, master_label
+	mrs	\xreg1, mpidr_el1
+	lsr	\xreg2, \xreg1, #32
+	lsl	\xreg1, \xreg1, #40
+	lsr	\xreg1, \xreg1, #40
+	orr	\xreg1, \xreg1, \xreg2
+	cbz	\xreg1, \master_label
+.endm
+
+#endif /* CONFIG_ARM64 */
+
 #endif /* __ASSEMBLY__ */
 #endif /* __ASM_ARM_MACRO_H__ */
diff --git a/arch/arm/include/asm/memory.h b/arch/arm/include/asm/memory.h
index c3b2afd907..1864ab9fb5 100644
--- a/arch/arm/include/asm/memory.h
+++ b/arch/arm/include/asm/memory.h
@@ -14,7 +14,6 @@
 
 #if 0	/* XXX###XXX */
 
-#include <linux/config.h>
 #include <asm/arch/memory.h>
 
 /*
diff --git a/arch/arm/include/asm/omap_common.h b/arch/arm/include/asm/omap_common.h
index 3a998cc10c..04925bca1c 100644
--- a/arch/arm/include/asm/omap_common.h
+++ b/arch/arm/include/asm/omap_common.h
@@ -143,6 +143,8 @@ struct prcm_regs {
 	u32 cm_div_m2_dpll_unipro;
 	u32 cm_ssc_deltamstep_dpll_unipro;
 	u32 cm_ssc_modfreqdiv_dpll_unipro;
+	u32 cm_coreaon_usb_phy_core_clkctrl;
+	u32 cm_coreaon_usb_phy2_core_clkctrl;
 
 	/* cm2.core */
 	u32 cm_coreaon_bandgap_clkctrl;
@@ -224,8 +226,11 @@ struct prcm_regs {
 	u32 cm_l3init_hsusbotg_clkctrl;
 	u32 cm_l3init_hsusbtll_clkctrl;
 	u32 cm_l3init_p1500_clkctrl;
+	u32 cm_l3init_sata_clkctrl;
 	u32 cm_l3init_fsusb_clkctrl;
 	u32 cm_l3init_ocp2scp1_clkctrl;
+	u32 cm_l3init_ocp2scp3_clkctrl;
+	u32 cm_l3init_usb_otg_ss_clkctrl;
 
 	u32 prm_irqstatus_mpu_2;
 
@@ -348,6 +353,7 @@ struct omap_sys_ctrl_regs {
 	u32 control_core_mac_id_1_lo;
 	u32 control_core_mac_id_1_hi;
 	u32 control_std_fuse_opp_vdd_mpu_2;
+	u32 control_phy_power_usb;
 	u32 control_core_mmr_lock1;
 	u32 control_core_mmr_lock2;
 	u32 control_core_mmr_lock3;
@@ -361,6 +367,7 @@ struct omap_sys_ctrl_regs {
 	u32 control_ldosram_mpu_voltage_ctrl;
 	u32 control_ldosram_core_voltage_ctrl;
 	u32 control_usbotghs_ctrl;
+	u32 control_phy_power_sata;
 	u32 control_padconf_core_base;
 	u32 control_paconf_global;
 	u32 control_paconf_mode;
@@ -560,7 +567,6 @@ u32 omap_ddr_clk(void);
 u32 get_sys_clk_index(void);
 void enable_basic_clocks(void);
 void enable_basic_uboot_clocks(void);
-void enable_non_essential_clocks(void);
 void scale_vcores(struct vcores_data const *);
 u32 get_offset_code(u32 volt_offset, struct pmic_data *pmic);
 void do_scale_vcore(u32 vcore_reg, u32 volt_mv, struct pmic_data *pmic);
@@ -600,6 +606,14 @@ static inline u8 is_omap54xx(void)
 	extern u32 *const omap_si_rev;
 	return ((*omap_si_rev & 0xFF000000) == OMAP54xx);
 }
+
+#define DRA7XX		0x07000000
+
+static inline u8 is_dra7xx(void)
+{
+	extern u32 *const omap_si_rev;
+	return ((*omap_si_rev & 0xFF000000) == DRA7XX);
+}
 #endif
 
 /*
@@ -628,6 +642,7 @@ static inline u8 is_omap54xx(void)
 
 /* DRA7XX */
 #define DRA752_ES1_0	0x07520100
+#define DRA752_ES1_1	0x07520110
 
 /*
  * SRAM scratch space entries
diff --git a/arch/arm/include/asm/omap_gpmc.h b/arch/arm/include/asm/omap_gpmc.h
deleted file mode 100644
index dd40cb6c16..0000000000
--- a/arch/arm/include/asm/omap_gpmc.h
+++ /dev/null
@@ -1,71 +0,0 @@
-/*
- * (C) Copyright 2004-2008 Texas Instruments, <www.ti.com>
- * Rohit Choraria <rohitkc@ti.com>
- *
- * (C) Copyright 2013 Andreas Bießmann <andreas.devel@googlemail.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-#ifndef __ASM_OMAP_GPMC_H
-#define __ASM_OMAP_GPMC_H
-
-#include <asm/arch/omap_gpmc.h>
-
-#define GPMC_BUF_EMPTY	0
-#define GPMC_BUF_FULL	1
-
-#define ECCCLEAR	(0x1 << 8)
-#define ECCRESULTREG1	(0x1 << 0)
-#define ECCSIZE512BYTE	0xFF
-#define ECCSIZE1	(ECCSIZE512BYTE << 22)
-#define ECCSIZE0	(ECCSIZE512BYTE << 12)
-#define ECCSIZE0SEL	(0x000 << 0)
-
-/* Generic ECC Layouts */
-/* Large Page x8 NAND device Layout */
-#ifdef GPMC_NAND_ECC_LP_x8_LAYOUT
-#define GPMC_NAND_HW_ECC_LAYOUT {\
-	.eccbytes = 12,\
-	.eccpos = {1, 2, 3, 4, 5, 6, 7, 8,\
-		9, 10, 11, 12},\
-	.oobfree = {\
-		{.offset = 13,\
-		 .length = 51 } } \
-}
-#endif
-
-/* Large Page x16 NAND device Layout */
-#ifdef GPMC_NAND_ECC_LP_x16_LAYOUT
-#define GPMC_NAND_HW_ECC_LAYOUT {\
-	.eccbytes = 12,\
-	.eccpos = {2, 3, 4, 5, 6, 7, 8, 9,\
-		10, 11, 12, 13},\
-	.oobfree = {\
-		{.offset = 14,\
-		 .length = 50 } } \
-}
-#endif
-
-/* Small Page x8 NAND device Layout */
-#ifdef GPMC_NAND_ECC_SP_x8_LAYOUT
-#define GPMC_NAND_HW_ECC_LAYOUT {\
-	.eccbytes = 3,\
-	.eccpos = {1, 2, 3},\
-	.oobfree = {\
-		{.offset = 4,\
-		 .length = 12 } } \
-}
-#endif
-
-/* Small Page x16 NAND device Layout */
-#ifdef GPMC_NAND_ECC_SP_x16_LAYOUT
-#define GPMC_NAND_HW_ECC_LAYOUT {\
-	.eccbytes = 3,\
-	.eccpos = {2, 3, 4},\
-	.oobfree = {\
-		{.offset = 5,\
-		 .length = 11 } } \
-}
-#endif
-
-#endif /* __ASM_OMAP_GPMC_H */
diff --git a/arch/arm/include/asm/pl310.h b/arch/arm/include/asm/pl310.h
index f41ad8c559..ddc245bfd5 100644
--- a/arch/arm/include/asm/pl310.h
+++ b/arch/arm/include/asm/pl310.h
@@ -12,6 +12,9 @@
 
 /* Register bit fields */
 #define PL310_AUX_CTRL_ASSOCIATIVITY_MASK	(1 << 16)
+#define L2X0_DYNAMIC_CLK_GATING_EN		(1 << 1)
+#define L2X0_STNDBY_MODE_EN			(1 << 0)
+#define L2X0_CTRL_EN				1
 
 struct pl310_regs {
 	u32 pl310_cache_id;
@@ -47,6 +50,24 @@ struct pl310_regs {
 	u32 pad9[1];
 	u32 pl310_clean_inv_line_idx;
 	u32 pl310_clean_inv_way;
+	u32 pad10[64];
+	u32 pl310_lockdown_dbase;
+	u32 pl310_lockdown_ibase;
+	u32 pad11[190];
+	u32 pl310_addr_filter_start;
+	u32 pl310_addr_filter_end;
+	u32 pad12[190];
+	u32 pl310_test_operation;
+	u32 pad13[3];
+	u32 pl310_line_data;
+	u32 pad14[7];
+	u32 pl310_line_tag;
+	u32 pad15[3];
+	u32 pl310_debug_ctrl;
+	u32 pad16[7];
+	u32 pl310_prefetch_ctrl;
+	u32 pad17[7];
+	u32 pl310_power_ctrl;
 };
 
 void pl310_inval_all(void);
diff --git a/arch/arm/include/asm/posix_types.h b/arch/arm/include/asm/posix_types.h
index c412486db5..d254b95b2a 100644
--- a/arch/arm/include/asm/posix_types.h
+++ b/arch/arm/include/asm/posix_types.h
@@ -28,9 +28,17 @@ typedef int			__kernel_pid_t;
 typedef unsigned short		__kernel_ipc_pid_t;
 typedef unsigned short		__kernel_uid_t;
 typedef unsigned short		__kernel_gid_t;
+
+#ifdef	__aarch64__
+typedef unsigned long		__kernel_size_t;
+typedef long			__kernel_ssize_t;
+typedef long			__kernel_ptrdiff_t;
+#else
 typedef unsigned int		__kernel_size_t;
 typedef int			__kernel_ssize_t;
 typedef int			__kernel_ptrdiff_t;
+#endif
+
 typedef long			__kernel_time_t;
 typedef long			__kernel_suseconds_t;
 typedef long			__kernel_clock_t;
diff --git a/arch/arm/include/asm/proc-armv/ptrace.h b/arch/arm/include/asm/proc-armv/ptrace.h
index 79cc6443f4..21aef58b7b 100644
--- a/arch/arm/include/asm/proc-armv/ptrace.h
+++ b/arch/arm/include/asm/proc-armv/ptrace.h
@@ -10,7 +10,24 @@
 #ifndef __ASM_PROC_PTRACE_H
 #define __ASM_PROC_PTRACE_H
 
-#include <linux/config.h>
+#ifdef CONFIG_ARM64
+
+#define PCMASK		0
+
+#ifndef __ASSEMBLY__
+
+/*
+ * This struct defines the way the registers are stored
+ * on the stack during an exception.
+ */
+struct pt_regs {
+	unsigned long elr;
+	unsigned long regs[31];
+};
+
+#endif	/* __ASSEMBLY__ */
+
+#else	/* CONFIG_ARM64 */
 
 #define USR26_MODE	0x00
 #define FIQ26_MODE	0x01
@@ -106,4 +123,6 @@ static inline int valid_user_regs(struct pt_regs *regs)
 
 #endif	/* __ASSEMBLY__ */
 
+#endif	/* CONFIG_ARM64 */
+
 #endif
diff --git a/arch/arm/include/asm/proc-armv/system.h b/arch/arm/include/asm/proc-armv/system.h
index b4cfa68ca3..693d1f4921 100644
--- a/arch/arm/include/asm/proc-armv/system.h
+++ b/arch/arm/include/asm/proc-armv/system.h
@@ -10,11 +10,63 @@
 #ifndef __ASM_PROC_SYSTEM_H
 #define __ASM_PROC_SYSTEM_H
 
-#include <linux/config.h>
-
 /*
  * Save the current interrupt enable state & disable IRQs
  */
+#ifdef CONFIG_ARM64
+
+/*
+ * Save the current interrupt enable state
+ * and disable IRQs/FIQs
+ */
+#define local_irq_save(flags)					\
+	({							\
+	asm volatile(						\
+	"mrs	%0, daif"					\
+	"msr	daifset, #3"					\
+	: "=r" (flags)						\
+	:							\
+	: "memory");						\
+	})
+
+/*
+ * restore saved IRQ & FIQ state
+ */
+#define local_irq_restore(flags)				\
+	({							\
+	asm volatile(						\
+	"msr	daif, %0"					\
+	:							\
+	: "r" (flags)						\
+	: "memory");						\
+	})
+
+/*
+ * Enable IRQs/FIQs
+ */
+#define local_irq_enable()					\
+	({							\
+	asm volatile(						\
+	"msr	daifclr, #3"					\
+	:							\
+	:							\
+	: "memory");						\
+	})
+
+/*
+ * Disable IRQs/FIQs
+ */
+#define local_irq_disable()					\
+	({							\
+	asm volatile(						\
+	"msr	daifset, #3"					\
+	:							\
+	:							\
+	: "memory");						\
+	})
+
+#else	/* CONFIG_ARM64 */
+
 #define local_irq_save(x)					\
 	({							\
 		unsigned long temp;				\
@@ -109,7 +161,10 @@
 	: "r" (x)						\
 	: "memory")
 
-#if defined(CONFIG_CPU_SA1100) || defined(CONFIG_CPU_SA110)
+#endif	/* CONFIG_ARM64 */
+
+#if defined(CONFIG_CPU_SA1100) || defined(CONFIG_CPU_SA110) || \
+	defined(CONFIG_ARM64)
 /*
  * On the StrongARM, "swp" is terminally broken since it bypasses the
  * cache totally.  This means that the cache becomes inconsistent, and,
diff --git a/arch/arm/include/asm/sizes.h b/arch/arm/include/asm/sizes.h
deleted file mode 100644
index 28cf5eaeba..0000000000
--- a/arch/arm/include/asm/sizes.h
+++ /dev/null
@@ -1,39 +0,0 @@
-/*
- * SPDX-License-Identifier:	GPL-2.0+
- */
-/*  Size defintions
- *  Copyright (C) ARM Limited 1998. All rights reserved.
- */
-
-#ifndef __sizes_h
-#define __sizes_h                       1
-
-/* handy sizes */
-#define SZ_1K                           0x00000400
-#define SZ_4K                           0x00001000
-#define SZ_8K                           0x00002000
-#define SZ_16K                          0x00004000
-#define SZ_32K                          0x00008000
-#define SZ_64K                          0x00010000
-#define SZ_128K                         0x00020000
-#define SZ_256K                         0x00040000
-#define SZ_512K                         0x00080000
-
-#define SZ_1M                           0x00100000
-#define SZ_2M                           0x00200000
-#define SZ_4M                           0x00400000
-#define SZ_8M                           0x00800000
-#define SZ_16M                          0x01000000
-#define SZ_31M                          0x01F00000
-#define SZ_32M                          0x02000000
-#define SZ_64M                          0x04000000
-#define SZ_128M                         0x08000000
-#define SZ_256M                         0x10000000
-#define SZ_512M                         0x20000000
-
-#define SZ_1G                           0x40000000
-#define SZ_2G                           0x80000000
-
-#endif
-
-/*         END */
diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h
index 760345f847..74ee9a4df9 100644
--- a/arch/arm/include/asm/system.h
+++ b/arch/arm/include/asm/system.h
@@ -1,6 +1,87 @@
 #ifndef __ASM_ARM_SYSTEM_H
 #define __ASM_ARM_SYSTEM_H
 
+#ifdef CONFIG_ARM64
+
+/*
+ * SCTLR_EL1/SCTLR_EL2/SCTLR_EL3 bits definitions
+ */
+#define CR_M		(1 << 0)	/* MMU enable			*/
+#define CR_A		(1 << 1)	/* Alignment abort enable	*/
+#define CR_C		(1 << 2)	/* Dcache enable		*/
+#define CR_SA		(1 << 3)	/* Stack Alignment Check Enable	*/
+#define CR_I		(1 << 12)	/* Icache enable		*/
+#define CR_WXN		(1 << 19)	/* Write Permision Imply XN	*/
+#define CR_EE		(1 << 25)	/* Exception (Big) Endian	*/
+
+#define PGTABLE_SIZE	(0x10000)
+
+#ifndef __ASSEMBLY__
+
+#define isb()				\
+	({asm volatile(			\
+	"isb" : : : "memory");		\
+	})
+
+#define wfi()				\
+	({asm volatile(			\
+	"wfi" : : : "memory");		\
+	})
+
+static inline unsigned int current_el(void)
+{
+	unsigned int el;
+	asm volatile("mrs %0, CurrentEL" : "=r" (el) : : "cc");
+	return el >> 2;
+}
+
+static inline unsigned int get_sctlr(void)
+{
+	unsigned int el, val;
+
+	el = current_el();
+	if (el == 1)
+		asm volatile("mrs %0, sctlr_el1" : "=r" (val) : : "cc");
+	else if (el == 2)
+		asm volatile("mrs %0, sctlr_el2" : "=r" (val) : : "cc");
+	else
+		asm volatile("mrs %0, sctlr_el3" : "=r" (val) : : "cc");
+
+	return val;
+}
+
+static inline void set_sctlr(unsigned int val)
+{
+	unsigned int el;
+
+	el = current_el();
+	if (el == 1)
+		asm volatile("msr sctlr_el1, %0" : : "r" (val) : "cc");
+	else if (el == 2)
+		asm volatile("msr sctlr_el2, %0" : : "r" (val) : "cc");
+	else
+		asm volatile("msr sctlr_el3, %0" : : "r" (val) : "cc");
+
+	asm volatile("isb");
+}
+
+void __asm_flush_dcache_all(void);
+void __asm_invalidate_dcache_all(void);
+void __asm_flush_dcache_range(u64 start, u64 end);
+void __asm_invalidate_tlb_all(void);
+void __asm_invalidate_icache_all(void);
+
+void armv8_switch_to_el2(void);
+void armv8_switch_to_el1(void);
+void gic_init(void);
+void gic_send_sgi(unsigned long sgino);
+void wait_for_wakeup(void);
+void smp_kick_all_cpus(void);
+
+#endif	/* __ASSEMBLY__ */
+
+#else /* CONFIG_ARM64 */
+
 #ifdef __KERNEL__
 
 #define CPU_ARCH_UNKNOWN	0
@@ -45,6 +126,8 @@
 #define CR_AFE	(1 << 29)	/* Access flag enable			*/
 #define CR_TE	(1 << 30)	/* Thumb exception enable		*/
 
+#define PGTABLE_SIZE		(4096 * 4)
+
 /*
  * This is used to ensure the compiler did actually allocate the register we
  * asked it for some inline assembly sequences.  Apparently we can't trust
@@ -132,4 +215,6 @@ void mmu_page_table_flush(unsigned long start, unsigned long stop);
 
 #endif /* __KERNEL__ */
 
+#endif /* CONFIG_ARM64 */
+
 #endif
diff --git a/arch/arm/include/asm/types.h b/arch/arm/include/asm/types.h
index 71dc049da6..2326420a7f 100644
--- a/arch/arm/include/asm/types.h
+++ b/arch/arm/include/asm/types.h
@@ -39,7 +39,11 @@ typedef unsigned int u32;
 typedef signed long long s64;
 typedef unsigned long long u64;
 
+#ifdef	CONFIG_ARM64
+#define BITS_PER_LONG 64
+#else	/* CONFIG_ARM64 */
 #define BITS_PER_LONG 32
+#endif	/* CONFIG_ARM64 */
 
 /* Dma addresses are 32-bits wide.  */
 
diff --git a/arch/arm/include/asm/u-boot.h b/arch/arm/include/asm/u-boot.h
index 2b5fce86ab..cb81232b83 100644
--- a/arch/arm/include/asm/u-boot.h
+++ b/arch/arm/include/asm/u-boot.h
@@ -44,6 +44,10 @@ typedef struct bd_info {
 #endif /* !CONFIG_SYS_GENERIC_BOARD */
 
 /* For image.h:image_check_target_arch() */
+#ifndef CONFIG_ARM64
 #define IH_ARCH_DEFAULT IH_ARCH_ARM
+#else
+#define IH_ARCH_DEFAULT IH_ARCH_ARM64
+#endif
 
 #endif	/* _U_BOOT_H_ */
diff --git a/arch/arm/include/asm/unaligned.h b/arch/arm/include/asm/unaligned.h
index 44593a8949..0a228fb8ee 100644
--- a/arch/arm/include/asm/unaligned.h
+++ b/arch/arm/include/asm/unaligned.h
@@ -8,7 +8,7 @@
 /*
  * Select endianness
  */
-#ifndef __ARMEB__
+#if __BYTE_ORDER == __LITTLE_ENDIAN
 #define get_unaligned	__get_unaligned_le
 #define put_unaligned	__put_unaligned_le
 #else
diff --git a/arch/arm/lib/Makefile b/arch/arm/lib/Makefile
index 4e78723ea9..e035d6acc0 100644
--- a/arch/arm/lib/Makefile
+++ b/arch/arm/lib/Makefile
@@ -5,77 +5,49 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
+lib-$(CONFIG_USE_PRIVATE_LIBGCC) += _ashldi3.o _ashrdi3.o _divsi3.o \
+			_lshrdi3.o _modsi3.o _udivsi3.o _umodsi3.o div0.o
 
-LIB	= $(obj)lib$(ARCH).o
-LIBGCC	= $(obj)libgcc.o
-
-GLSOBJS	+= _ashldi3.o
-GLSOBJS	+= _ashrdi3.o
-GLSOBJS	+= _divsi3.o
-GLSOBJS	+= _lshrdi3.o
-GLSOBJS	+= _modsi3.o
-GLSOBJS	+= _udivsi3.o
-GLSOBJS	+= _umodsi3.o
-
-GLCOBJS	+= div0.o
-
-SOBJS-y += crt0.o
+ifdef CONFIG_ARM64
+obj-y	+= crt0_64.o
+else
+obj-y	+= crt0.o
+endif
 
 ifndef CONFIG_SPL_BUILD
-SOBJS-y += relocate.o
+ifdef CONFIG_ARM64
+obj-y	+= relocate_64.o
+else
+obj-y	+= relocate.o
+endif
 ifndef CONFIG_SYS_GENERIC_BOARD
-COBJS-y	+= board.o
+obj-y	+= board.o
 endif
-COBJS-y += sections.o
 
-COBJS-$(CONFIG_OF_LIBFDT) += bootm-fdt.o
-COBJS-$(CONFIG_CMD_BOOTM) += bootm.o
-COBJS-$(CONFIG_SYS_L2_PL310) += cache-pl310.o
-SOBJS-$(CONFIG_USE_ARCH_MEMSET) += memset.o
-SOBJS-$(CONFIG_USE_ARCH_MEMCPY) += memcpy.o
+obj-$(CONFIG_OF_LIBFDT) += bootm-fdt.o
+obj-$(CONFIG_CMD_BOOTM) += bootm.o
+obj-$(CONFIG_SYS_L2_PL310) += cache-pl310.o
+obj-$(CONFIG_USE_ARCH_MEMSET) += memset.o
+obj-$(CONFIG_USE_ARCH_MEMCPY) += memcpy.o
 else
-COBJS-$(CONFIG_SPL_FRAMEWORK) += spl.o
+obj-$(CONFIG_SPL_FRAMEWORK) += spl.o
 endif
 
-COBJS-y	+= interrupts.o
-COBJS-y	+= reset.o
-
-COBJS-y	+= cache.o
-COBJS-y	+= cache-cp15.o
-
-SRCS	:= $(GLSOBJS:.o=.S) $(GLCOBJS:.o=.c) \
-	   $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
-OBJS	:= $(addprefix $(obj),$(SOBJS-y) $(COBJS-y))
-LGOBJS	:= $(addprefix $(obj),$(GLSOBJS)) \
-	   $(addprefix $(obj),$(GLCOBJS))
-
-# Always build libarm.o
-TARGETS	:= $(LIB)
+obj-y	+= sections.o
+ifdef CONFIG_ARM64
+obj-y	+= gic_64.o
+obj-y	+= interrupts_64.o
+else
+obj-y	+= interrupts.o
+endif
+obj-y	+= reset.o
 
-# Build private libgcc only when asked for
-ifdef USE_PRIVATE_LIBGCC
-TARGETS	+= $(LIBGCC)
+obj-y	+= cache.o
+ifndef CONFIG_ARM64
+obj-y	+= cache-cp15.o
 endif
 
 # For EABI conformant tool chains, provide eabi_compat()
 ifneq (,$(findstring -mabi=aapcs-linux,$(PLATFORM_CPPFLAGS)))
-TARGETS	+= $(obj)eabi_compat.o
+extra-y	+= eabi_compat.o
 endif
-
-all:	$(TARGETS)
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-$(LIBGCC): $(obj).depend $(LGOBJS)
-	$(call cmd_link_o_target, $(LGOBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
diff --git a/arch/arm/lib/_divsi3.S b/arch/arm/lib/_divsi3.S
index cfbadb2ab9..601549304e 100644
--- a/arch/arm/lib/_divsi3.S
+++ b/arch/arm/lib/_divsi3.S
@@ -1,4 +1,3 @@
-
 .macro ARM_DIV_BODY dividend, divisor, result, curbit
 
 #if __LINUX_ARM_ARCH__ >= 5
diff --git a/arch/arm/lib/_modsi3.S b/arch/arm/lib/_modsi3.S
index 539c584997..3d31a559f8 100644
--- a/arch/arm/lib/_modsi3.S
+++ b/arch/arm/lib/_modsi3.S
@@ -1,4 +1,3 @@
-
 .macro ARM_MOD_BODY dividend, divisor, order, spare
 
 #if __LINUX_ARM_ARCH__ >= 5
diff --git a/arch/arm/lib/asm-offsets.c b/arch/arm/lib/asm-offsets.c
new file mode 100644
index 0000000000..b0c26e5d68
--- /dev/null
+++ b/arch/arm/lib/asm-offsets.c
@@ -0,0 +1,248 @@
+/*
+ * Adapted from Linux v2.6.36 kernel: arch/powerpc/kernel/asm-offsets.c
+ *
+ * This program is used to generate definitions needed by
+ * assembly language modules.
+ *
+ * We use the technique used in the OSF Mach kernel code:
+ * generate asm statements containing #defines,
+ * compile this file to assembler, and then extract the
+ * #defines from the assembly-language output.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <linux/kbuild.h>
+
+#if defined(CONFIG_MB86R0x)
+#include <asm/arch/mb86r0x.h>
+#endif
+#if defined(CONFIG_MX25) || defined(CONFIG_MX27) || defined(CONFIG_MX35) \
+	|| defined(CONFIG_MX51) || defined(CONFIG_MX53)
+#include <asm/arch/imx-regs.h>
+#endif
+
+int main(void)
+{
+	/*
+	 * TODO : Check if each entry in this file is really necessary.
+	 *   - struct mb86r0x_ddr2
+	 *   - struct mb86r0x_memc
+	 *   - struct esdramc_regs
+	 *   - struct max_regs
+	 *   - struct aips_regs
+	 *   - struct aipi_regs
+	 *   - struct clkctl
+	 *   - struct dpll
+	 * are used only for generating asm-offsets.h.
+	 * It means their offset addresses are referenced only from assembly
+	 * code. Is it better to define the macros directly in headers?
+	 */
+
+#if defined(CONFIG_MB86R0x)
+	/* ddr2 controller */
+	DEFINE(DDR2_DRIC, offsetof(struct mb86r0x_ddr2c, dric));
+	DEFINE(DDR2_DRIC1, offsetof(struct mb86r0x_ddr2c, dric1));
+	DEFINE(DDR2_DRIC2, offsetof(struct mb86r0x_ddr2c, dric2));
+	DEFINE(DDR2_DRCA, offsetof(struct mb86r0x_ddr2c, drca));
+	DEFINE(DDR2_DRCM, offsetof(struct mb86r0x_ddr2c, drcm));
+	DEFINE(DDR2_DRCST1, offsetof(struct mb86r0x_ddr2c, drcst1));
+	DEFINE(DDR2_DRCST2, offsetof(struct mb86r0x_ddr2c, drcst2));
+	DEFINE(DDR2_DRCR, offsetof(struct mb86r0x_ddr2c, drcr));
+	DEFINE(DDR2_DRCF, offsetof(struct mb86r0x_ddr2c, drcf));
+	DEFINE(DDR2_DRASR, offsetof(struct mb86r0x_ddr2c, drasr));
+	DEFINE(DDR2_DRIMS, offsetof(struct mb86r0x_ddr2c, drims));
+	DEFINE(DDR2_DROS, offsetof(struct mb86r0x_ddr2c, dros));
+	DEFINE(DDR2_DRIBSODT1, offsetof(struct mb86r0x_ddr2c, dribsodt1));
+	DEFINE(DDR2_DROABA, offsetof(struct mb86r0x_ddr2c, droaba));
+	DEFINE(DDR2_DROBS, offsetof(struct mb86r0x_ddr2c, drobs));
+
+	/* clock reset generator */
+	DEFINE(CRG_CRPR, offsetof(struct mb86r0x_crg, crpr));
+	DEFINE(CRG_CRHA, offsetof(struct mb86r0x_crg, crha));
+	DEFINE(CRG_CRPA, offsetof(struct mb86r0x_crg, crpa));
+	DEFINE(CRG_CRPB, offsetof(struct mb86r0x_crg, crpb));
+	DEFINE(CRG_CRHB, offsetof(struct mb86r0x_crg, crhb));
+	DEFINE(CRG_CRAM, offsetof(struct mb86r0x_crg, cram));
+
+	/* chip control module */
+	DEFINE(CCNT_CDCRC, offsetof(struct mb86r0x_ccnt, cdcrc));
+
+	/* external bus interface */
+	DEFINE(MEMC_MCFMODE0, offsetof(struct mb86r0x_memc, mcfmode[0]));
+	DEFINE(MEMC_MCFMODE2, offsetof(struct mb86r0x_memc, mcfmode[2]));
+	DEFINE(MEMC_MCFMODE4, offsetof(struct mb86r0x_memc, mcfmode[4]));
+	DEFINE(MEMC_MCFTIM0, offsetof(struct mb86r0x_memc, mcftim[0]));
+	DEFINE(MEMC_MCFTIM2, offsetof(struct mb86r0x_memc, mcftim[2]));
+	DEFINE(MEMC_MCFTIM4, offsetof(struct mb86r0x_memc, mcftim[4]));
+	DEFINE(MEMC_MCFAREA0, offsetof(struct mb86r0x_memc, mcfarea[0]));
+	DEFINE(MEMC_MCFAREA2, offsetof(struct mb86r0x_memc, mcfarea[2]));
+	DEFINE(MEMC_MCFAREA4, offsetof(struct mb86r0x_memc, mcfarea[4]));
+#endif
+
+#if defined(CONFIG_MX25)
+	/* Clock Control Module */
+	DEFINE(CCM_CCTL, offsetof(struct ccm_regs, cctl));
+	DEFINE(CCM_CGCR0, offsetof(struct ccm_regs, cgr0));
+	DEFINE(CCM_CGCR1, offsetof(struct ccm_regs, cgr1));
+	DEFINE(CCM_CGCR2, offsetof(struct ccm_regs, cgr2));
+	DEFINE(CCM_PCDR2, offsetof(struct ccm_regs, pcdr[2]));
+	DEFINE(CCM_MCR, offsetof(struct ccm_regs, mcr));
+
+	/* Enhanced SDRAM Controller */
+	DEFINE(ESDRAMC_ESDCTL0, offsetof(struct esdramc_regs, ctl0));
+	DEFINE(ESDRAMC_ESDCFG0, offsetof(struct esdramc_regs, cfg0));
+	DEFINE(ESDRAMC_ESDMISC, offsetof(struct esdramc_regs, misc));
+
+	/* Multi-Layer AHB Crossbar Switch */
+	DEFINE(MAX_MPR0, offsetof(struct max_regs, mpr0));
+	DEFINE(MAX_SGPCR0, offsetof(struct max_regs, sgpcr0));
+	DEFINE(MAX_MPR1, offsetof(struct max_regs, mpr1));
+	DEFINE(MAX_SGPCR1, offsetof(struct max_regs, sgpcr1));
+	DEFINE(MAX_MPR2, offsetof(struct max_regs, mpr2));
+	DEFINE(MAX_SGPCR2, offsetof(struct max_regs, sgpcr2));
+	DEFINE(MAX_MPR3, offsetof(struct max_regs, mpr3));
+	DEFINE(MAX_SGPCR3, offsetof(struct max_regs, sgpcr3));
+	DEFINE(MAX_MPR4, offsetof(struct max_regs, mpr4));
+	DEFINE(MAX_SGPCR4, offsetof(struct max_regs, sgpcr4));
+	DEFINE(MAX_MGPCR0, offsetof(struct max_regs, mgpcr0));
+	DEFINE(MAX_MGPCR1, offsetof(struct max_regs, mgpcr1));
+	DEFINE(MAX_MGPCR2, offsetof(struct max_regs, mgpcr2));
+	DEFINE(MAX_MGPCR3, offsetof(struct max_regs, mgpcr3));
+	DEFINE(MAX_MGPCR4, offsetof(struct max_regs, mgpcr4));
+
+	/* AHB <-> IP-Bus Interface */
+	DEFINE(AIPS_MPR_0_7, offsetof(struct aips_regs, mpr_0_7));
+	DEFINE(AIPS_MPR_8_15, offsetof(struct aips_regs, mpr_8_15));
+#endif
+
+#if defined(CONFIG_MX27)
+	DEFINE(AIPI1_PSR0, IMX_AIPI1_BASE + offsetof(struct aipi_regs, psr0));
+	DEFINE(AIPI1_PSR1, IMX_AIPI1_BASE + offsetof(struct aipi_regs, psr1));
+	DEFINE(AIPI2_PSR0, IMX_AIPI2_BASE + offsetof(struct aipi_regs, psr0));
+	DEFINE(AIPI2_PSR1, IMX_AIPI2_BASE + offsetof(struct aipi_regs, psr1));
+
+	DEFINE(CSCR, IMX_PLL_BASE + offsetof(struct pll_regs, cscr));
+	DEFINE(MPCTL0, IMX_PLL_BASE + offsetof(struct pll_regs, mpctl0));
+	DEFINE(SPCTL0, IMX_PLL_BASE + offsetof(struct pll_regs, spctl0));
+	DEFINE(PCDR0, IMX_PLL_BASE + offsetof(struct pll_regs, pcdr0));
+	DEFINE(PCDR1, IMX_PLL_BASE + offsetof(struct pll_regs, pcdr1));
+	DEFINE(PCCR0, IMX_PLL_BASE + offsetof(struct pll_regs, pccr0));
+	DEFINE(PCCR1, IMX_PLL_BASE + offsetof(struct pll_regs, pccr1));
+
+	DEFINE(ESDCTL0_ROF, offsetof(struct esdramc_regs, esdctl0));
+	DEFINE(ESDCFG0_ROF, offsetof(struct esdramc_regs, esdcfg0));
+	DEFINE(ESDCTL1_ROF, offsetof(struct esdramc_regs, esdctl1));
+	DEFINE(ESDCFG1_ROF, offsetof(struct esdramc_regs, esdcfg1));
+	DEFINE(ESDMISC_ROF, offsetof(struct esdramc_regs, esdmisc));
+
+	DEFINE(GPCR, IMX_SYSTEM_CTL_BASE +
+		offsetof(struct system_control_regs, gpcr));
+	DEFINE(FMCR, IMX_SYSTEM_CTL_BASE +
+		offsetof(struct system_control_regs, fmcr));
+#endif
+
+#if defined(CONFIG_MX35)
+	/* Round up to make sure size gives nice stack alignment */
+	DEFINE(CLKCTL_CCMR, offsetof(struct ccm_regs, ccmr));
+	DEFINE(CLKCTL_PDR0, offsetof(struct ccm_regs, pdr0));
+	DEFINE(CLKCTL_PDR1, offsetof(struct ccm_regs, pdr1));
+	DEFINE(CLKCTL_PDR2, offsetof(struct ccm_regs, pdr2));
+	DEFINE(CLKCTL_PDR3, offsetof(struct ccm_regs, pdr3));
+	DEFINE(CLKCTL_PDR4, offsetof(struct ccm_regs, pdr4));
+	DEFINE(CLKCTL_RCSR, offsetof(struct ccm_regs, rcsr));
+	DEFINE(CLKCTL_MPCTL, offsetof(struct ccm_regs, mpctl));
+	DEFINE(CLKCTL_PPCTL, offsetof(struct ccm_regs, ppctl));
+	DEFINE(CLKCTL_ACMR, offsetof(struct ccm_regs, acmr));
+	DEFINE(CLKCTL_COSR, offsetof(struct ccm_regs, cosr));
+	DEFINE(CLKCTL_CGR0, offsetof(struct ccm_regs, cgr0));
+	DEFINE(CLKCTL_CGR1, offsetof(struct ccm_regs, cgr1));
+	DEFINE(CLKCTL_CGR2, offsetof(struct ccm_regs, cgr2));
+	DEFINE(CLKCTL_CGR3, offsetof(struct ccm_regs, cgr3));
+
+	/* Multi-Layer AHB Crossbar Switch */
+	DEFINE(MAX_MPR0, offsetof(struct max_regs, mpr0));
+	DEFINE(MAX_SGPCR0, offsetof(struct max_regs, sgpcr0));
+	DEFINE(MAX_MPR1, offsetof(struct max_regs, mpr1));
+	DEFINE(MAX_SGPCR1, offsetof(struct max_regs, sgpcr1));
+	DEFINE(MAX_MPR2, offsetof(struct max_regs, mpr2));
+	DEFINE(MAX_SGPCR2, offsetof(struct max_regs, sgpcr2));
+	DEFINE(MAX_MPR3, offsetof(struct max_regs, mpr3));
+	DEFINE(MAX_SGPCR3, offsetof(struct max_regs, sgpcr3));
+	DEFINE(MAX_MPR4, offsetof(struct max_regs, mpr4));
+	DEFINE(MAX_SGPCR4, offsetof(struct max_regs, sgpcr4));
+	DEFINE(MAX_MGPCR0, offsetof(struct max_regs, mgpcr0));
+	DEFINE(MAX_MGPCR1, offsetof(struct max_regs, mgpcr1));
+	DEFINE(MAX_MGPCR2, offsetof(struct max_regs, mgpcr2));
+	DEFINE(MAX_MGPCR3, offsetof(struct max_regs, mgpcr3));
+	DEFINE(MAX_MGPCR4, offsetof(struct max_regs, mgpcr4));
+	DEFINE(MAX_MGPCR5, offsetof(struct max_regs, mgpcr5));
+
+	/* AHB <-> IP-Bus Interface */
+	DEFINE(AIPS_MPR_0_7, offsetof(struct aips_regs, mpr_0_7));
+	DEFINE(AIPS_MPR_8_15, offsetof(struct aips_regs, mpr_8_15));
+	DEFINE(AIPS_PACR_0_7, offsetof(struct aips_regs, pacr_0_7));
+	DEFINE(AIPS_PACR_8_15, offsetof(struct aips_regs, pacr_8_15));
+	DEFINE(AIPS_PACR_16_23, offsetof(struct aips_regs, pacr_16_23));
+	DEFINE(AIPS_PACR_24_31, offsetof(struct aips_regs, pacr_24_31));
+	DEFINE(AIPS_OPACR_0_7, offsetof(struct aips_regs, opacr_0_7));
+	DEFINE(AIPS_OPACR_8_15, offsetof(struct aips_regs, opacr_8_15));
+	DEFINE(AIPS_OPACR_16_23, offsetof(struct aips_regs, opacr_16_23));
+	DEFINE(AIPS_OPACR_24_31, offsetof(struct aips_regs, opacr_24_31));
+	DEFINE(AIPS_OPACR_32_39, offsetof(struct aips_regs, opacr_32_39));
+#endif
+
+#if defined(CONFIG_MX51) || defined(CONFIG_MX53)
+	/* Round up to make sure size gives nice stack alignment */
+	DEFINE(CLKCTL_CCMR, offsetof(struct clkctl, ccr));
+	DEFINE(CLKCTL_CCDR, offsetof(struct clkctl, ccdr));
+	DEFINE(CLKCTL_CSR, offsetof(struct clkctl, csr));
+	DEFINE(CLKCTL_CCSR, offsetof(struct clkctl, ccsr));
+	DEFINE(CLKCTL_CACRR, offsetof(struct clkctl, cacrr));
+	DEFINE(CLKCTL_CBCDR, offsetof(struct clkctl, cbcdr));
+	DEFINE(CLKCTL_CBCMR, offsetof(struct clkctl, cbcmr));
+	DEFINE(CLKCTL_CSCMR1, offsetof(struct clkctl, cscmr1));
+	DEFINE(CLKCTL_CSCMR2, offsetof(struct clkctl, cscmr2));
+	DEFINE(CLKCTL_CSCDR1, offsetof(struct clkctl, cscdr1));
+	DEFINE(CLKCTL_CS1CDR, offsetof(struct clkctl, cs1cdr));
+	DEFINE(CLKCTL_CS2CDR, offsetof(struct clkctl, cs2cdr));
+	DEFINE(CLKCTL_CDCDR, offsetof(struct clkctl, cdcdr));
+	DEFINE(CLKCTL_CHSCCDR, offsetof(struct clkctl, chsccdr));
+	DEFINE(CLKCTL_CSCDR2, offsetof(struct clkctl, cscdr2));
+	DEFINE(CLKCTL_CSCDR3, offsetof(struct clkctl, cscdr3));
+	DEFINE(CLKCTL_CSCDR4, offsetof(struct clkctl, cscdr4));
+	DEFINE(CLKCTL_CWDR, offsetof(struct clkctl, cwdr));
+	DEFINE(CLKCTL_CDHIPR, offsetof(struct clkctl, cdhipr));
+	DEFINE(CLKCTL_CDCR, offsetof(struct clkctl, cdcr));
+	DEFINE(CLKCTL_CTOR, offsetof(struct clkctl, ctor));
+	DEFINE(CLKCTL_CLPCR, offsetof(struct clkctl, clpcr));
+	DEFINE(CLKCTL_CISR, offsetof(struct clkctl, cisr));
+	DEFINE(CLKCTL_CIMR, offsetof(struct clkctl, cimr));
+	DEFINE(CLKCTL_CCOSR, offsetof(struct clkctl, ccosr));
+	DEFINE(CLKCTL_CGPR, offsetof(struct clkctl, cgpr));
+	DEFINE(CLKCTL_CCGR0, offsetof(struct clkctl, ccgr0));
+	DEFINE(CLKCTL_CCGR1, offsetof(struct clkctl, ccgr1));
+	DEFINE(CLKCTL_CCGR2, offsetof(struct clkctl, ccgr2));
+	DEFINE(CLKCTL_CCGR3, offsetof(struct clkctl, ccgr3));
+	DEFINE(CLKCTL_CCGR4, offsetof(struct clkctl, ccgr4));
+	DEFINE(CLKCTL_CCGR5, offsetof(struct clkctl, ccgr5));
+	DEFINE(CLKCTL_CCGR6, offsetof(struct clkctl, ccgr6));
+	DEFINE(CLKCTL_CMEOR, offsetof(struct clkctl, cmeor));
+#if defined(CONFIG_MX53)
+	DEFINE(CLKCTL_CCGR7, offsetof(struct clkctl, ccgr7));
+#endif
+
+	/* DPLL */
+	DEFINE(PLL_DP_CTL, offsetof(struct dpll, dp_ctl));
+	DEFINE(PLL_DP_CONFIG, offsetof(struct dpll, dp_config));
+	DEFINE(PLL_DP_OP, offsetof(struct dpll, dp_op));
+	DEFINE(PLL_DP_MFD, offsetof(struct dpll, dp_mfd));
+	DEFINE(PLL_DP_MFN, offsetof(struct dpll, dp_mfn));
+	DEFINE(PLL_DP_HFS_OP, offsetof(struct dpll, dp_hfs_op));
+	DEFINE(PLL_DP_HFS_MFD, offsetof(struct dpll, dp_hfs_mfd));
+	DEFINE(PLL_DP_HFS_MFN, offsetof(struct dpll, dp_hfs_mfn));
+#endif
+
+	return 0;
+}
diff --git a/arch/arm/lib/board.c b/arch/arm/lib/board.c
index 34f50b08a5..92e85c4db5 100644
--- a/arch/arm/lib/board.c
+++ b/arch/arm/lib/board.c
@@ -33,6 +33,7 @@
 #include <nand.h>
 #include <onenand_uboot.h>
 #include <mmc.h>
+#include <scsi.h>
 #include <libfdt.h>
 #include <fdtdec.h>
 #include <post.h>
@@ -105,8 +106,8 @@ static int display_banner(void)
 {
 	printf("\n\n%s\n\n", version_string);
 	debug("U-Boot code: %08lX -> %08lX  BSS: -> %08lX\n",
-	       _TEXT_BASE,
-	       _bss_start_ofs + _TEXT_BASE, _bss_end_ofs + _TEXT_BASE);
+	       (ulong)&_start,
+	       (ulong)&__bss_start, (ulong)&__bss_end);
 #ifdef CONFIG_MODEM_SUPPORT
 	debug("Modem Support enabled\n");
 #endif
@@ -197,8 +198,6 @@ static int arm_pci_init(void)
  */
 typedef int (init_fnc_t) (void);
 
-int print_cpuinfo(void);
-
 void __dram_init_banksize(void)
 {
 	gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
@@ -250,9 +249,7 @@ init_fnc_t *init_sequence[] = {
 	serial_init,		/* serial communications setup */
 	console_init_f,		/* stage 1 init of console */
 	display_banner,		/* say that we are here */
-#if defined(CONFIG_DISPLAY_CPUINFO)
 	print_cpuinfo,		/* display cpu info (and speed) */
-#endif
 #if defined(CONFIG_DISPLAY_BOARDINFO)
 	checkboard,		/* display board info */
 #endif
@@ -277,13 +274,13 @@ void board_init_f(ulong bootflag)
 
 	memset((void *)gd, 0, sizeof(gd_t));
 
-	gd->mon_len = _bss_end_ofs;
+	gd->mon_len = (ulong)&__bss_end - (ulong)_start;
 #ifdef CONFIG_OF_EMBED
 	/* Get a pointer to the FDT */
-	gd->fdt_blob = _binary_dt_dtb_start;
+	gd->fdt_blob = __dtb_db_begin;
 #elif defined CONFIG_OF_SEPARATE
 	/* FDT is at end of image */
-	gd->fdt_blob = (void *)(_end_ofs + _TEXT_BASE);
+	gd->fdt_blob = &_end;
 #endif
 	/* Allow the early environment to override the fdt address */
 	gd->fdt_blob = (void *)getenv_ulong("fdtcontroladdr", 16,
@@ -322,7 +319,7 @@ void board_init_f(ulong bootflag)
 	gd->ram_size -= CONFIG_SYS_MEM_TOP_HIDE;
 #endif
 
-	addr = CONFIG_SYS_SDRAM_BASE + gd->ram_size;
+	addr = CONFIG_SYS_SDRAM_BASE + get_effective_memsize();
 
 #ifdef CONFIG_LOGBUFFER
 #ifndef CONFIG_ALT_LB_ADDR
@@ -344,7 +341,7 @@ void board_init_f(ulong bootflag)
 
 #if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF))
 	/* reserve TLB table */
-	gd->arch.tlb_size = 4096 * 4;
+	gd->arch.tlb_size = PGTABLE_SIZE;
 	addr -= gd->arch.tlb_size;
 
 	/* round down to next 64 kB limit */
@@ -419,6 +416,7 @@ void board_init_f(ulong bootflag)
 	}
 #endif
 
+#ifndef CONFIG_ARM64
 	/* setup stackpointer for exeptions */
 	gd->irq_sp = addr_sp;
 #ifdef CONFIG_USE_IRQ
@@ -431,11 +429,14 @@ void board_init_f(ulong bootflag)
 
 	/* 8-byte alignment for ABI compliance */
 	addr_sp &= ~0x07;
+#else	/* CONFIG_ARM64 */
+	/* 16-byte alignment for ABI compliance */
+	addr_sp &= ~0x0f;
+#endif	/* CONFIG_ARM64 */
 #else
 	addr_sp += 128;	/* leave 32 words for abort-stack   */
 	gd->irq_sp = addr_sp;
 #endif
-	interrupt_init();
 
 	debug("New Stack Pointer is: %08lx\n", addr_sp);
 
@@ -451,7 +452,7 @@ void board_init_f(ulong bootflag)
 
 	gd->relocaddr = addr;
 	gd->start_addr_sp = addr_sp;
-	gd->reloc_off = addr - _TEXT_BASE;
+	gd->reloc_off = addr - (ulong)&_start;
 	debug("relocation Offset is: %08lx\n", gd->reloc_off);
 	if (new_fdt) {
 		memcpy(new_fdt, gd->fdt_blob, fdt_size);
@@ -516,7 +517,7 @@ void board_init_r(gd_t *id, ulong dest_addr)
 	gd->flags |= GD_FLG_RELOC;	/* tell others: relocation done */
 	bootstage_mark_name(BOOTSTAGE_ID_START_UBOOT_R, "board_init_r");
 
-	monitor_flash_len = _end_ofs;
+	monitor_flash_len = (ulong)&__rel_dyn_end - (ulong)_start;
 
 	/* Enable caches */
 	enable_caches();
@@ -593,6 +594,11 @@ void board_init_r(gd_t *id, ulong dest_addr)
 	mmc_initialize(gd->bd);
 #endif
 
+#ifdef CONFIG_CMD_SCSI
+	puts("SCSI:  ");
+	scsi_init();
+#endif
+
 #ifdef CONFIG_HAS_DATAFLASH
 	AT91F_DataflashInit();
 	dataflash_print_info();
@@ -637,6 +643,8 @@ void board_init_r(gd_t *id, ulong dest_addr)
 	misc_init_r();
 #endif
 
+	 /* set up exceptions */
+	interrupt_init();
 	/* enable exceptions */
 	enable_interrupts();
 
diff --git a/arch/arm/lib/bootm.c b/arch/arm/lib/bootm.c
index f476a89702..47ee070593 100644
--- a/arch/arm/lib/bootm.c
+++ b/arch/arm/lib/bootm.c
@@ -71,8 +71,7 @@ static void announce_and_cleanup(int fake)
 		"(fake run for tracing)" : "");
 	bootstage_mark_name(BOOTSTAGE_ID_BOOTM_HANDOFF, "start_kernel");
 #ifdef CONFIG_BOOTSTAGE_FDT
-	if (flag == BOOTM_STATE_OS_FAKE_GO)
-		bootstage_fdt_add_report();
+	bootstage_fdt_add_report();
 #endif
 #ifdef CONFIG_BOOTSTAGE_REPORT
 	bootstage_report();
@@ -196,6 +195,15 @@ static void do_nonsec_virt_switch(void)
 		debug("entered non-secure state\n");
 #endif
 #endif
+
+#ifdef CONFIG_ARM64
+	smp_kick_all_cpus();
+	flush_dcache_all();	/* flush cache before swtiching to EL2 */
+	armv8_switch_to_el2();
+#ifdef CONFIG_ARMV8_SWITCH_TO_EL1
+	armv8_switch_to_el1();
+#endif
+#endif
 }
 
 /* Subcommand: PREP */
@@ -240,6 +248,21 @@ static void boot_prep_linux(bootm_headers_t *images)
 /* Subcommand: GO */
 static void boot_jump_linux(bootm_headers_t *images, int flag)
 {
+#ifdef CONFIG_ARM64
+	void (*kernel_entry)(void *fdt_addr);
+	int fake = (flag & BOOTM_STATE_OS_FAKE_GO);
+
+	kernel_entry = (void (*)(void *fdt_addr))images->ep;
+
+	debug("## Transferring control to Linux (at address %lx)...\n",
+		(ulong) kernel_entry);
+	bootstage_mark(BOOTSTAGE_ID_RUN_OS);
+
+	announce_and_cleanup(fake);
+
+	if (!fake)
+		kernel_entry(images->ft_addr);
+#else
 	unsigned long machid = gd->bd->bi_arch_number;
 	char *s;
 	void (*kernel_entry)(int zero, int arch, uint params);
@@ -266,6 +289,7 @@ static void boot_jump_linux(bootm_headers_t *images, int flag)
 
 	if (!fake)
 		kernel_entry(0, machid, r2);
+#endif
 }
 
 /* Main Entry point for arm bootm implementation
@@ -326,3 +350,26 @@ int bootz_setup(ulong image, ulong *start, ulong *end)
 }
 
 #endif	/* CONFIG_CMD_BOOTZ */
+
+#if defined(CONFIG_BOOTM_VXWORKS)
+void boot_prep_vxworks(bootm_headers_t *images)
+{
+#if defined(CONFIG_OF_LIBFDT)
+	int off;
+
+	if (images->ft_addr) {
+		off = fdt_path_offset(images->ft_addr, "/memory");
+		if (off < 0) {
+			if (arch_fixup_memory_node(images->ft_addr))
+				puts("## WARNING: fixup memory failed!\n");
+		}
+	}
+#endif
+	cleanup_before_linux();
+}
+void boot_jump_vxworks(bootm_headers_t *images)
+{
+	/* ARM VxWorks requires device tree physical address to be passed */
+	((void (*)(void *))images->ep)(images->ft_addr);
+}
+#endif
diff --git a/arch/arm/lib/crt0.S b/arch/arm/lib/crt0.S
index ac54b9359a..dfc2de9a61 100644
--- a/arch/arm/lib/crt0.S
+++ b/arch/arm/lib/crt0.S
@@ -67,7 +67,7 @@ ENTRY(_main)
 	ldr	sp, =(CONFIG_SYS_INIT_SP_ADDR)
 #endif
 	bic	sp, sp, #7	/* 8-byte alignment for ABI compliance */
-	sub	sp, #GD_SIZE	/* allocate one GD above SP */
+	sub	sp, sp, #GD_SIZE	/* allocate one GD above SP */
 	bic	sp, sp, #7	/* 8-byte alignment for ABI compliance */
 	mov	r9, sp		/* GD is above SP */
 	mov	r0, #0
diff --git a/arch/arm/lib/crt0_64.S b/arch/arm/lib/crt0_64.S
new file mode 100644
index 0000000000..77563967e5
--- /dev/null
+++ b/arch/arm/lib/crt0_64.S
@@ -0,0 +1,113 @@
+/*
+ * crt0 - C-runtime startup Code for AArch64 U-Boot
+ *
+ * (C) Copyright 2013
+ * David Feng <fenghua@phytium.com.cn>
+ *
+ * (C) Copyright 2012
+ * Albert ARIBAUD <albert.u.boot@aribaud.net>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <config.h>
+#include <asm-offsets.h>
+#include <asm/macro.h>
+#include <linux/linkage.h>
+
+/*
+ * This file handles the target-independent stages of the U-Boot
+ * start-up where a C runtime environment is needed. Its entry point
+ * is _main and is branched into from the target's start.S file.
+ *
+ * _main execution sequence is:
+ *
+ * 1. Set up initial environment for calling board_init_f().
+ *    This environment only provides a stack and a place to store
+ *    the GD ('global data') structure, both located in some readily
+ *    available RAM (SRAM, locked cache...). In this context, VARIABLE
+ *    global data, initialized or not (BSS), are UNAVAILABLE; only
+ *    CONSTANT initialized data are available.
+ *
+ * 2. Call board_init_f(). This function prepares the hardware for
+ *    execution from system RAM (DRAM, DDR...) As system RAM may not
+ *    be available yet, , board_init_f() must use the current GD to
+ *    store any data which must be passed on to later stages. These
+ *    data include the relocation destination, the future stack, and
+ *    the future GD location.
+ *
+ * (the following applies only to non-SPL builds)
+ *
+ * 3. Set up intermediate environment where the stack and GD are the
+ *    ones allocated by board_init_f() in system RAM, but BSS and
+ *    initialized non-const data are still not available.
+ *
+ * 4. Call relocate_code(). This function relocates U-Boot from its
+ *    current location into the relocation destination computed by
+ *    board_init_f().
+ *
+ * 5. Set up final environment for calling board_init_r(). This
+ *    environment has BSS (initialized to 0), initialized non-const
+ *    data (initialized to their intended value), and stack in system
+ *    RAM. GD has retained values set by board_init_f(). Some CPUs
+ *    have some work left to do at this point regarding memory, so
+ *    call c_runtime_cpu_setup.
+ *
+ * 6. Branch to board_init_r().
+ */
+
+ENTRY(_main)
+
+/*
+ * Set up initial C runtime environment and call board_init_f(0).
+ */
+	ldr	x0, =(CONFIG_SYS_INIT_SP_ADDR)
+	sub	x0, x0, #GD_SIZE	/* allocate one GD above SP */
+	bic	sp, x0, #0xf	/* 16-byte alignment for ABI compliance */
+	mov	x18, sp			/* GD is above SP */
+	mov	x0, #0
+	bl	board_init_f
+
+/*
+ * Set up intermediate environment (new sp and gd) and call
+ * relocate_code(addr_moni). Trick here is that we'll return
+ * 'here' but relocated.
+ */
+	ldr	x0, [x18, #GD_START_ADDR_SP]	/* x0 <- gd->start_addr_sp */
+	bic	sp, x0, #0xf	/* 16-byte alignment for ABI compliance */
+	ldr	x18, [x18, #GD_BD]		/* x18 <- gd->bd */
+	sub	x18, x18, #GD_SIZE		/* new GD is below bd */
+
+	adr	lr, relocation_return
+	ldr	x9, [x18, #GD_RELOC_OFF]	/* x9 <- gd->reloc_off */
+	add	lr, lr, x9	/* new return address after relocation */
+	ldr	x0, [x18, #GD_RELOCADDR]	/* x0 <- gd->relocaddr */
+	b	relocate_code
+
+relocation_return:
+
+/*
+ * Set up final (full) environment
+ */
+	bl	c_runtime_cpu_setup		/* still call old routine */
+
+/*
+ * Clear BSS section
+ */
+	ldr	x0, =__bss_start		/* this is auto-relocated! */
+	ldr	x1, =__bss_end			/* this is auto-relocated! */
+	mov	x2, #0
+clear_loop:
+	str	x2, [x0]
+	add	x0, x0, #8
+	cmp	x0, x1
+	b.lo	clear_loop
+
+	/* call board_init_r(gd_t *id, ulong dest_addr) */
+	mov	x0, x18				/* gd_t */
+	ldr	x1, [x18, #GD_RELOCADDR]	/* dest_addr */
+	b	board_init_r			/* PC relative jump */
+
+	/* NOTREACHED - board_init_r() does not return */
+
+ENDPROC(_main)
diff --git a/arch/arm/lib/gic_64.S b/arch/arm/lib/gic_64.S
new file mode 100644
index 0000000000..d56396ea22
--- /dev/null
+++ b/arch/arm/lib/gic_64.S
@@ -0,0 +1,194 @@
+/*
+ * GIC Initialization Routines.
+ *
+ * (C) Copyright 2013
+ * David Feng <fenghua@phytium.com.cn>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <asm-offsets.h>
+#include <config.h>
+#include <linux/linkage.h>
+#include <asm/macro.h>
+#include <asm/gic.h>
+
+
+/*************************************************************************
+ *
+ * void gic_init_secure(DistributorBase);
+ *
+ * Initialize secure copy of GIC at EL3.
+ *
+ *************************************************************************/
+ENTRY(gic_init_secure)
+	/*
+	 * Initialize Distributor
+	 * x0: Distributor Base
+	 */
+#if defined(CONFIG_GICV3)
+	mov	w9, #0x37		/* EnableGrp0 | EnableGrp1NS */
+					/* EnableGrp1S | ARE_S | ARE_NS */
+	str	w9, [x0, GICD_CTLR]	/* Secure GICD_CTLR */
+	ldr	w9, [x0, GICD_TYPER]
+	and	w10, w9, #0x1f		/* ITLinesNumber */
+	cbz	w10, 1f			/* No SPIs */
+	add	x11, x0, (GICD_IGROUPRn + 4)
+	add	x12, x0, (GICD_IGROUPMODRn + 4)
+	mov	w9, #~0
+0:	str	w9, [x11], #0x4
+	str	wzr, [x12], #0x4	/* Config SPIs as Group1NS */
+	sub	w10, w10, #0x1
+	cbnz	w10, 0b
+#elif defined(CONFIG_GICV2)
+	mov	w9, #0x3		/* EnableGrp0 | EnableGrp1 */
+	str	w9, [x0, GICD_CTLR]	/* Secure GICD_CTLR */
+	ldr	w9, [x0, GICD_TYPER]
+	and	w10, w9, #0x1f		/* ITLinesNumber */
+	cbz	w10, 1f			/* No SPIs */
+	add	x11, x0, (GICD_IGROUPRn + 4)
+	mov	w9, #~0			/* Config SPIs as Grp1 */
+0:	str	w9, [x11], #0x4
+	sub	w10, w10, #0x1
+	cbnz	w10, 0b
+#endif
+1:
+	ret
+ENDPROC(gic_init_secure)
+
+
+/*************************************************************************
+ * For Gicv2:
+ * void gic_init_secure_percpu(DistributorBase, CpuInterfaceBase);
+ * For Gicv3:
+ * void gic_init_secure_percpu(ReDistributorBase);
+ *
+ * Initialize secure copy of GIC at EL3.
+ *
+ *************************************************************************/
+ENTRY(gic_init_secure_percpu)
+#if defined(CONFIG_GICV3)
+	/*
+	 * Initialize ReDistributor
+	 * x0: ReDistributor Base
+	 */
+	mrs	x10, mpidr_el1
+	lsr	x9, x10, #32
+	bfi	x10, x9, #24, #8	/* w10 is aff3:aff2:aff1:aff0 */
+	mov	x9, x0
+1:	ldr	x11, [x9, GICR_TYPER]
+	lsr	x11, x11, #32		/* w11 is aff3:aff2:aff1:aff0 */
+	cmp	w10, w11
+	b.eq	2f
+	add	x9, x9, #(2 << 16)
+	b	1b
+
+	/* x9: ReDistributor Base Address of Current CPU */
+2:	mov	w10, #~0x2
+	ldr	w11, [x9, GICR_WAKER]
+	and	w11, w11, w10		/* Clear ProcessorSleep */
+	str	w11, [x9, GICR_WAKER]
+	dsb	st
+	isb
+3:	ldr	w10, [x9, GICR_WAKER]
+	tbnz	w10, #2, 3b		/* Wait Children be Alive */
+
+	add	x10, x9, #(1 << 16)	/* SGI_Base */
+	mov	w11, #~0
+	str	w11, [x10, GICR_IGROUPRn]
+	str	wzr, [x10, GICR_IGROUPMODRn]	/* SGIs|PPIs Group1NS */
+	mov	w11, #0x1		/* Enable SGI 0 */
+	str	w11, [x10, GICR_ISENABLERn]
+
+	/* Initialize Cpu Interface */
+	mrs	x10, ICC_SRE_EL3
+	orr	x10, x10, #0xf		/* SRE & Disable IRQ/FIQ Bypass & */
+					/* Allow EL2 access to ICC_SRE_EL2 */
+	msr	ICC_SRE_EL3, x10
+	isb
+
+	mrs	x10, ICC_SRE_EL2
+	orr	x10, x10, #0xf		/* SRE & Disable IRQ/FIQ Bypass & */
+					/* Allow EL1 access to ICC_SRE_EL1 */
+	msr	ICC_SRE_EL2, x10
+	isb
+
+	mov	x10, #0x3		/* EnableGrp1NS | EnableGrp1S */
+	msr	ICC_IGRPEN1_EL3, x10
+	isb
+
+	msr	ICC_CTLR_EL3, xzr
+	isb
+
+	msr	ICC_CTLR_EL1, xzr	/* NonSecure ICC_CTLR_EL1 */
+	isb
+
+	mov	x10, #0x1 << 7		/* Non-Secure access to ICC_PMR_EL1 */
+	msr	ICC_PMR_EL1, x10
+	isb
+#elif defined(CONFIG_GICV2)
+	/*
+	 * Initialize SGIs and PPIs
+	 * x0: Distributor Base
+	 * x1: Cpu Interface Base
+	 */
+	mov	w9, #~0			/* Config SGIs and PPIs as Grp1 */
+	str	w9, [x0, GICD_IGROUPRn]	/* GICD_IGROUPR0 */
+	mov	w9, #0x1		/* Enable SGI 0 */
+	str	w9, [x0, GICD_ISENABLERn]
+
+	/* Initialize Cpu Interface */
+	mov	w9, #0x1e7		/* Disable IRQ/FIQ Bypass & */
+					/* Enable Ack Group1 Interrupt & */
+					/* EnableGrp0 & EnableGrp1 */
+	str	w9, [x1, GICC_CTLR]	/* Secure GICC_CTLR */
+
+	mov	w9, #0x1 << 7		/* Non-Secure access to GICC_PMR */
+	str	w9, [x1, GICC_PMR]
+#endif
+	ret
+ENDPROC(gic_init_secure_percpu)
+
+
+/*************************************************************************
+ * For Gicv2:
+ * void gic_kick_secondary_cpus(DistributorBase);
+ * For Gicv3:
+ * void gic_kick_secondary_cpus(void);
+ *
+ *************************************************************************/
+ENTRY(gic_kick_secondary_cpus)
+#if defined(CONFIG_GICV3)
+	mov	x9, #(1 << 40)
+	msr	ICC_ASGI1R_EL1, x9
+	isb
+#elif defined(CONFIG_GICV2)
+	mov	w9, #0x8000
+	movk	w9, #0x100, lsl #16
+	str	w9, [x0, GICD_SGIR]
+#endif
+	ret
+ENDPROC(gic_kick_secondary_cpus)
+
+
+/*************************************************************************
+ * For Gicv2:
+ * void gic_wait_for_interrupt(CpuInterfaceBase);
+ * For Gicv3:
+ * void gic_wait_for_interrupt(void);
+ *
+ * Wait for SGI 0 from master.
+ *
+ *************************************************************************/
+ENTRY(gic_wait_for_interrupt)
+0:	wfi
+#if defined(CONFIG_GICV3)
+	mrs	x9, ICC_IAR1_EL1
+	msr	ICC_EOIR1_EL1, x9
+#elif defined(CONFIG_GICV2)
+	ldr	w9, [x0, GICC_AIAR]
+	str	w9, [x0, GICC_AEOIR]
+#endif
+	cbnz	w9, 0b
+	ret
+ENDPROC(gic_wait_for_interrupt)
diff --git a/arch/arm/lib/interrupts.c b/arch/arm/lib/interrupts.c
index 603bf14627..758b01371e 100644
--- a/arch/arm/lib/interrupts.c
+++ b/arch/arm/lib/interrupts.c
@@ -153,7 +153,7 @@ void do_prefetch_abort (struct pt_regs *pt_regs)
 
 void do_data_abort (struct pt_regs *pt_regs)
 {
-	printf ("data abort\n\n    MAYBE you should read doc/README.arm-unaligned-accesses\n\n");
+	printf ("data abort\n");
 	show_regs (pt_regs);
 	bad_mode ();
 }
diff --git a/arch/arm/lib/interrupts_64.c b/arch/arm/lib/interrupts_64.c
new file mode 100644
index 0000000000..b476722556
--- /dev/null
+++ b/arch/arm/lib/interrupts_64.c
@@ -0,0 +1,120 @@
+/*
+ * (C) Copyright 2013
+ * David Feng <fenghua@phytium.com.cn>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <linux/compiler.h>
+
+
+int interrupt_init(void)
+{
+	return 0;
+}
+
+void enable_interrupts(void)
+{
+	return;
+}
+
+int disable_interrupts(void)
+{
+	return 0;
+}
+
+void show_regs(struct pt_regs *regs)
+{
+	int i;
+
+	printf("ELR:     %lx\n", regs->elr);
+	printf("LR:      %lx\n", regs->regs[30]);
+	for (i = 0; i < 29; i += 2)
+		printf("x%-2d: %016lx x%-2d: %016lx\n",
+		       i, regs->regs[i], i+1, regs->regs[i+1]);
+	printf("\n");
+}
+
+/*
+ * do_bad_sync handles the impossible case in the Synchronous Abort vector.
+ */
+void do_bad_sync(struct pt_regs *pt_regs, unsigned int esr)
+{
+	printf("Bad mode in \"Synchronous Abort\" handler, esr 0x%08x\n", esr);
+	show_regs(pt_regs);
+	panic("Resetting CPU ...\n");
+}
+
+/*
+ * do_bad_irq handles the impossible case in the Irq vector.
+ */
+void do_bad_irq(struct pt_regs *pt_regs, unsigned int esr)
+{
+	printf("Bad mode in \"Irq\" handler, esr 0x%08x\n", esr);
+	show_regs(pt_regs);
+	panic("Resetting CPU ...\n");
+}
+
+/*
+ * do_bad_fiq handles the impossible case in the Fiq vector.
+ */
+void do_bad_fiq(struct pt_regs *pt_regs, unsigned int esr)
+{
+	printf("Bad mode in \"Fiq\" handler, esr 0x%08x\n", esr);
+	show_regs(pt_regs);
+	panic("Resetting CPU ...\n");
+}
+
+/*
+ * do_bad_error handles the impossible case in the Error vector.
+ */
+void do_bad_error(struct pt_regs *pt_regs, unsigned int esr)
+{
+	printf("Bad mode in \"Error\" handler, esr 0x%08x\n", esr);
+	show_regs(pt_regs);
+	panic("Resetting CPU ...\n");
+}
+
+/*
+ * do_sync handles the Synchronous Abort exception.
+ */
+void do_sync(struct pt_regs *pt_regs, unsigned int esr)
+{
+	printf("\"Synchronous Abort\" handler, esr 0x%08x\n", esr);
+	show_regs(pt_regs);
+	panic("Resetting CPU ...\n");
+}
+
+/*
+ * do_irq handles the Irq exception.
+ */
+void do_irq(struct pt_regs *pt_regs, unsigned int esr)
+{
+	printf("\"Irq\" handler, esr 0x%08x\n", esr);
+	show_regs(pt_regs);
+	panic("Resetting CPU ...\n");
+}
+
+/*
+ * do_fiq handles the Fiq exception.
+ */
+void do_fiq(struct pt_regs *pt_regs, unsigned int esr)
+{
+	printf("\"Fiq\" handler, esr 0x%08x\n", esr);
+	show_regs(pt_regs);
+	panic("Resetting CPU ...\n");
+}
+
+/*
+ * do_error handles the Error exception.
+ * Errors are more likely to be processor specific,
+ * it is defined with weak attribute and can be redefined
+ * in processor specific code.
+ */
+void __weak do_error(struct pt_regs *pt_regs, unsigned int esr)
+{
+	printf("\"Error\" handler, esr 0x%08x\n", esr);
+	show_regs(pt_regs);
+	panic("Resetting CPU ...\n");
+}
diff --git a/arch/arm/lib/relocate_64.S b/arch/arm/lib/relocate_64.S
new file mode 100644
index 0000000000..5c51cae8ab
--- /dev/null
+++ b/arch/arm/lib/relocate_64.S
@@ -0,0 +1,77 @@
+/*
+ * relocate - common relocation function for AArch64 U-Boot
+ *
+ * (C) Copyright 2013
+ * Albert ARIBAUD <albert.u.boot@aribaud.net>
+ * David Feng <fenghua@phytium.com.cn>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <asm-offsets.h>
+#include <config.h>
+#include <linux/linkage.h>
+#include <asm/macro.h>
+
+/*
+ * void relocate_code (addr_moni)
+ *
+ * This function relocates the monitor code.
+ * x0 holds the destination address.
+ */
+ENTRY(relocate_code)
+	stp	x29, x30, [sp, #-32]!	/* create a stack frame */
+	mov	x29, sp
+	str	x0, [sp, #16]
+	/*
+	 * Copy u-boot from flash to RAM
+	 */
+	ldr	x1, =__image_copy_start	/* x1 <- SRC &__image_copy_start */
+	subs	x9, x0, x1		/* x9 <- relocation offset */
+	b.eq	relocate_done		/* skip relocation */
+	ldr	x2, =__image_copy_end	/* x2 <- SRC &__image_copy_end */
+
+copy_loop:
+	ldp	x10, x11, [x1], #16	/* copy from source address [x1] */
+	stp	x10, x11, [x0], #16	/* copy to   target address [x0] */
+	cmp	x1, x2			/* until source end address [x2] */
+	b.lo	copy_loop
+	str	x0, [sp, #24]
+
+	/*
+	 * Fix .rela.dyn relocations
+	 */
+	ldr	x2, =__rel_dyn_start	/* x2 <- SRC &__rel_dyn_start */
+	ldr	x3, =__rel_dyn_end	/* x3 <- SRC &__rel_dyn_end */
+fixloop:
+	ldp	x0, x1, [x2], #16	/* (x0,x1) <- (SRC location, fixup) */
+	ldr	x4, [x2], #8		/* x4 <- addend */
+	and	x1, x1, #0xffffffff
+	cmp	x1, #1027		/* relative fixup? */
+	bne	fixnext
+
+	/* relative fix: store addend plus offset at dest location */
+	add	x0, x0, x9
+	add	x4, x4, x9
+	str	x4, [x0]
+fixnext:
+	cmp	x2, x3
+	b.lo	fixloop
+
+relocate_done:
+	switch_el x1, 3f, 2f, 1f
+	bl	hang
+3:	mrs	x0, sctlr_el3
+	b	0f
+2:	mrs	x0, sctlr_el2
+	b	0f
+1:	mrs	x0, sctlr_el1
+0:	tbz	w0, #2, 5f	/* skip flushing cache if disabled */
+	tbz	w0, #12, 4f	/* invalide i-cache is enabled */
+	ic	iallu		/* i-cache invalidate all */
+	isb	sy
+4:	ldp	x0, x1, [sp, #16]
+	bl	__asm_flush_dcache_range
+5:	ldp	x29, x30, [sp],#16
+	ret
+ENDPROC(relocate_code)
diff --git a/arch/arm/lib/sections.c b/arch/arm/lib/sections.c
index e35687c09c..5b30bcb9a5 100644
--- a/arch/arm/lib/sections.c
+++ b/arch/arm/lib/sections.c
@@ -25,3 +25,4 @@ char __image_copy_start[0] __attribute__((section(".__image_copy_start")));
 char __image_copy_end[0] __attribute__((section(".__image_copy_end")));
 char __rel_dyn_start[0] __attribute__((section(".__rel_dyn_start")));
 char __rel_dyn_end[0] __attribute__((section(".__rel_dyn_end")));
+char _end[0] __attribute__((section(".__end")));
diff --git a/arch/avr32/config.mk b/arch/avr32/config.mk
index 4ab4745edf..28a371c806 100644
--- a/arch/avr32/config.mk
+++ b/arch/avr32/config.mk
@@ -5,8 +5,11 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-CROSS_COMPILE ?= avr32-linux-
+ifeq ($(CROSS_COMPILE),)
+CROSS_COMPILE := avr32-linux-
+endif
 
+PLATFORM_CPPFLAGS += -DCONFIG_AVR32
 CONFIG_STANDALONE_LOAD_ADDR ?= 0x00000000
 
 PLATFORM_RELFLAGS	+= -ffixed-r5 -fPIC -mno-init-got -mrelax
diff --git a/arch/avr32/cpu/Makefile b/arch/avr32/cpu/Makefile
index 7e648fd7f5..5e11721257 100644
--- a/arch/avr32/cpu/Makefile
+++ b/arch/avr32/cpu/Makefile
@@ -7,34 +7,12 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	:= $(obj)lib$(CPU).o
-
-START-y			+= start.o
-
-COBJS-y			+= cpu.o
-COBJS-$(CONFIG_SYS_HSDRAMC) += hsdramc.o
-COBJS-y			+= exception.o
-COBJS-y			+= cache.o
-COBJS-y			+= interrupts.o
-COBJS-$(CONFIG_PORTMUX_PIO) += portmux-pio.o
-COBJS-$(CONFIG_PORTMUX_GPIO) += portmux-gpio.o
-
-SRCS	:= $(START-y:.o=.S) $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
-OBJS	:= $(addprefix $(obj),$(SOBJS-y) $(COBJS-y))
-START	:= $(addprefix $(obj),$(START-y))
-
-all: $(obj).depend $(START) $(LIB)
-
-$(LIB): $(OBJS)
-	$(call cmd_link_o_target, $^)
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+extra-y			+= start.o
+
+obj-y			+= cpu.o
+obj-$(CONFIG_SYS_HSDRAMC) += hsdramc.o
+obj-y			+= exception.o
+obj-y			+= cache.o
+obj-y			+= interrupts.o
+obj-$(CONFIG_PORTMUX_PIO) += portmux-pio.o
+obj-$(CONFIG_PORTMUX_GPIO) += portmux-gpio.o
diff --git a/arch/avr32/cpu/at32ap700x/Makefile b/arch/avr32/cpu/at32ap700x/Makefile
index 8be8c1d05e..06f18963e2 100644
--- a/arch/avr32/cpu/at32ap700x/Makefile
+++ b/arch/avr32/cpu/at32ap700x/Makefile
@@ -4,24 +4,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	:= $(obj)lib$(SOC).o
-
-COBJS	:= portmux.o clk.o mmu.o
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS))
-
-all: $(obj).depend $(LIB)
-
-$(LIB): $(OBJS)
-	$(call cmd_link_o_target, $^)
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	:= portmux.o clk.o mmu.o
diff --git a/arch/avr32/cpu/pio2.h b/arch/avr32/cpu/pio2.h
deleted file mode 100644
index 9719ea8c43..0000000000
--- a/arch/avr32/cpu/pio2.h
+++ /dev/null
@@ -1,44 +0,0 @@
-/*
- * Register definitions for Parallel Input/Output Controller
- */
-#ifndef __CPU_AT32AP_PIO2_H__
-#define __CPU_AT32AP_PIO2_H__
-
-/* PIO2 register offsets */
-#define PIO2_PER				0x0000
-#define PIO2_PDR				0x0004
-#define PIO2_PSR				0x0008
-#define PIO2_OER				0x0010
-#define PIO2_ODR				0x0014
-#define PIO2_OSR				0x0018
-#define PIO2_IFER				0x0020
-#define PIO2_IFDR				0x0024
-#define PIO2_ISFR				0x0028
-#define PIO2_SODR				0x0030
-#define PIO2_CODR				0x0034
-#define PIO2_ODSR				0x0038
-#define PIO2_PDSR				0x003c
-#define PIO2_IER				0x0040
-#define PIO2_IDR				0x0044
-#define PIO2_IMR				0x0048
-#define PIO2_ISR				0x004c
-#define PIO2_MDER				0x0050
-#define PIO2_MDDR				0x0054
-#define PIO2_MDSR				0x0058
-#define PIO2_PUDR				0x0060
-#define PIO2_PUER				0x0064
-#define PIO2_PUSR				0x0068
-#define PIO2_ASR				0x0070
-#define PIO2_BSR				0x0074
-#define PIO2_ABSR				0x0078
-#define PIO2_OWER				0x00a0
-#define PIO2_OWDR				0x00a4
-#define PIO2_OWSR				0x00a8
-
-/* Register access macros */
-#define pio2_readl(base,reg)				\
-	readl((void *)base + PIO2_##reg)
-#define pio2_writel(base,reg,value)			\
-	writel((value), (void *)base + PIO2_##reg)
-
-#endif /* __CPU_AT32AP_PIO2_H__ */
diff --git a/arch/avr32/include/asm/arch-at32ap700x/gpio-impl.h b/arch/avr32/include/asm/arch-at32ap700x/gpio-impl.h
deleted file mode 100644
index 8801bd006c..0000000000
--- a/arch/avr32/include/asm/arch-at32ap700x/gpio-impl.h
+++ /dev/null
@@ -1,86 +0,0 @@
-#ifndef __ASM_AVR32_ARCH_GPIO_IMPL_H__
-#define __ASM_AVR32_ARCH_GPIO_IMPL_H__
-
-/* Register offsets */
-struct gpio_regs {
-	u32	GPER;
-	u32	GPERS;
-	u32	GPERC;
-	u32	GPERT;
-	u32	PMR0;
-	u32	PMR0S;
-	u32	PMR0C;
-	u32	PMR0T;
-	u32	PMR1;
-	u32	PMR1S;
-	u32	PMR1C;
-	u32	PMR1T;
-	u32	__reserved0[4];
-	u32	ODER;
-	u32	ODERS;
-	u32	ODERC;
-	u32	ODERT;
-	u32	OVR;
-	u32	OVRS;
-	u32	OVRC;
-	u32	OVRT;
-	u32	PVR;
-	u32	__reserved_PVRS;
-	u32	__reserved_PVRC;
-	u32	__reserved_PVRT;
-	u32	PUER;
-	u32	PUERS;
-	u32	PUERC;
-	u32	PUERT;
-	u32	PDER;
-	u32	PDERS;
-	u32	PDERC;
-	u32	PDERT;
-	u32	IER;
-	u32	IERS;
-	u32	IERC;
-	u32	IERT;
-	u32	IMR0;
-	u32	IMR0S;
-	u32	IMR0C;
-	u32	IMR0T;
-	u32	IMR1;
-	u32	IMR1S;
-	u32	IMR1C;
-	u32	IMR1T;
-	u32	GFER;
-	u32	GFERS;
-	u32	GFERC;
-	u32	GFERT;
-	u32	IFR;
-	u32	__reserved_IFRS;
-	u32	IFRC;
-	u32	__reserved_IFRT;
-	u32	ODMER;
-	u32	ODMERS;
-	u32	ODMERC;
-	u32	ODMERT;
-	u32	__reserved1[4];
-	u32	ODCR0;
-	u32	ODCR0S;
-	u32	ODCR0C;
-	u32	ODCR0T;
-	u32	ODCR1;
-	u32	ODCR1S;
-	u32	ODCR1C;
-	u32	ODCR1T;
-	u32	__reserved2[4];
-	u32	OSRR0;
-	u32	OSRR0S;
-	u32	OSRR0C;
-	u32	OSRR0T;
-	u32	__reserved3[8];
-	u32	STER;
-	u32	STERS;
-	u32	STERC;
-	u32	STERT;
-	u32	__reserved4[35];
-	u32	VERSION;
-};
-
-#endif /* __ASM_AVR32_ARCH_GPIO_IMPL_H__ */
diff --git a/arch/avr32/include/asm/arch-common/portmux-gpio.h b/arch/avr32/include/asm/arch-common/portmux-gpio.h
deleted file mode 100644
index fb01a17fc1..0000000000
--- a/arch/avr32/include/asm/arch-common/portmux-gpio.h
+++ /dev/null
@@ -1,98 +0,0 @@
-/*
- * Copyright (C) 2008 Atmel Corporation
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-#ifndef __AVR32_PORTMUX_GPIO_H__
-#define __AVR32_PORTMUX_GPIO_H__
-
-#include <asm/io.h>
-
-/* Register layout for this specific device */
-#include <asm/arch/gpio-impl.h>
-
-/* Register access macros */
-#define gpio_readl(port, reg)						\
-	__raw_readl(&((struct gpio_regs *)port)->reg)
-#define gpio_writel(gpio, reg, value)					\
-	__raw_writel(value, &((struct gpio_regs *)port)->reg)
-
-/* Portmux API starts here. See doc/README.AVR32-port-muxing */
-
-enum portmux_function {
-	PORTMUX_FUNC_A,
-	PORTMUX_FUNC_B,
-	PORTMUX_FUNC_C,
-	PORTMUX_FUNC_D,
-};
-
-#define PORTMUX_DIR_INPUT	(0 << 0)
-#define PORTMUX_DIR_OUTPUT	(1 << 0)
-#define PORTMUX_INIT_LOW	(0 << 1)
-#define PORTMUX_INIT_HIGH	(1 << 1)
-#define PORTMUX_PULL_UP		(1 << 2)
-#define PORTMUX_PULL_DOWN	(2 << 2)
-#define PORTMUX_BUSKEEPER	(3 << 2)
-#define PORTMUX_DRIVE_MIN	(0 << 4)
-#define PORTMUX_DRIVE_LOW	(1 << 4)
-#define PORTMUX_DRIVE_HIGH	(2 << 4)
-#define PORTMUX_DRIVE_MAX	(3 << 4)
-#define PORTMUX_OPEN_DRAIN	(1 << 6)
-
-void portmux_select_peripheral(void *port, unsigned long pin_mask,
-		enum portmux_function func, unsigned long flags);
-void portmux_select_gpio(void *port, unsigned long pin_mask,
-		unsigned long flags);
-
-/* Internal helper functions */
-
-static inline void *gpio_pin_to_port(unsigned int pin)
-{
-	return (void *)GPIO_BASE + (pin >> 5) * 0x200;
-}
-
-static inline void __gpio_set_output_value(void *port, unsigned int pin,
-		int value)
-{
-	if (value)
-		gpio_writel(port, OVRS, 1 << pin);
-	else
-		gpio_writel(port, OVRC, 1 << pin);
-}
-
-static inline int __gpio_get_input_value(void *port, unsigned int pin)
-{
-	return (gpio_readl(port, PVR) >> pin) & 1;
-}
-
-void gpio_set_output_value(unsigned int pin, int value);
-int gpio_get_input_value(unsigned int pin);
-
-/* GPIO API starts here */
-
-/*
- * GCC doesn't realize that the constant case is extremely trivial,
- * so we need to help it make the right decision by using
- * always_inline.
- */
-__attribute__((always_inline))
-static inline void gpio_set_value(unsigned int pin, int value)
-{
-	if (__builtin_constant_p(pin))
-		__gpio_set_output_value(gpio_pin_to_port(pin),
-				pin & 0x1f, value);
-	else
-		gpio_set_output_value(pin, value);
-}
-
-__attribute__((always_inline))
-static inline int gpio_get_value(unsigned int pin)
-{
-	if (__builtin_constant_p(pin))
-		return __gpio_get_input_value(gpio_pin_to_port(pin),
-				pin & 0x1f);
-	else
-		return gpio_get_input_value(pin);
-}
-
-#endif /* __AVR32_PORTMUX_GPIO_H__ */
diff --git a/arch/avr32/lib/Makefile b/arch/avr32/lib/Makefile
index d5245d32f6..bb45cbe153 100644
--- a/arch/avr32/lib/Makefile
+++ b/arch/avr32/lib/Makefile
@@ -7,27 +7,7 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(ARCH).o
-
-SOBJS-y	+= memset.o
-
-COBJS-y	+= board.o
-COBJS-$(CONFIG_CMD_BOOTM) += bootm.o
-COBJS-y	+= interrupts.o
-
-SRCS	:= $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
-OBJS	:= $(addprefix $(obj),$(SOBJS-y) $(COBJS-y))
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	+= memset.o
+obj-y	+= board.o
+obj-$(CONFIG_CMD_BOOTM) += bootm.o
+obj-y	+= interrupts.o
diff --git a/arch/blackfin/config.mk b/arch/blackfin/config.mk
index 35f871662d..fcaa44f1d6 100644
--- a/arch/blackfin/config.mk
+++ b/arch/blackfin/config.mk
@@ -5,18 +5,20 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-CROSS_COMPILE ?= bfin-uclinux-
+ifeq ($(CROSS_COMPILE),)
+CROSS_COMPILE := bfin-uclinux-
+endif
 
 CONFIG_STANDALONE_LOAD_ADDR ?= 0x1000 -m elf32bfin
 
 ifeq ($(CONFIG_BFIN_CPU),)
 CONFIG_BFIN_CPU := \
 	$(shell awk '$$2 == "CONFIG_BFIN_CPU" { print $$3 }' \
-		$(src)include/configs/$(BOARD).h)
+		$(srctree)/include/configs/$(BOARD).h)
 else
-CONFIG_BFIN_CPU := $(strip $(subst ",,$(CONFIG_BFIN_CPU)))
+CONFIG_BFIN_CPU := $(strip $(CONFIG_BFIN_CPU:"%"=%))
 endif
-CONFIG_BFIN_BOOT_MODE := $(strip $(subst ",,$(CONFIG_BFIN_BOOT_MODE)))
+CONFIG_BFIN_BOOT_MODE := $(strip $(CONFIG_BFIN_BOOT_MODE:"%"=%))
 
 PLATFORM_RELFLAGS += -ffixed-P3 -fomit-frame-pointer -mno-fdpic
 PLATFORM_CPPFLAGS += -DCONFIG_BLACKFIN
@@ -28,10 +30,10 @@ PLATFORM_RELFLAGS += -ffunction-sections -fdata-sections
 PLATFORM_RELFLAGS += -mcpu=$(CONFIG_BFIN_CPU)
 
 ifneq ($(CONFIG_BFIN_BOOT_MODE),BFIN_BOOT_BYPASS)
-ALL-y += $(obj)u-boot.ldr
+ALL-y += u-boot.ldr
 endif
 ifeq ($(CONFIG_ENV_IS_EMBEDDED_IN_LDR),y)
-CREATE_LDR_ENV = $(obj)tools/envcrc --binary > $(obj)env-ldr.o
+CREATE_LDR_ENV = tools/envcrc --binary > env-ldr.o
 HOSTCFLAGS_NOPED_ADSP := \
 	$(shell $(CPP) -dD - -mcpu=$(CONFIG_BFIN_CPU) </dev/null \
 		| awk '$$2 ~ /ADSP/ { print "-D" $$2 }')
@@ -41,16 +43,17 @@ CREATE_LDR_ENV =
 endif
 
 SYM_PREFIX = _
+export SYM_PREFIX
 
 LDR_FLAGS-y :=
 LDR_FLAGS-$(CONFIG_BFIN_BOOTROM_USES_EVT1) += -J
 
 LDR_FLAGS += --bmode $(subst BFIN_BOOT_,,$(CONFIG_BFIN_BOOT_MODE))
 LDR_FLAGS += --use-vmas
-LDR_FLAGS += --initcode $(obj)$(CPUDIR)/initcode.o
+LDR_FLAGS += --initcode $(CPUDIR)/initcode.o
 ifneq ($(CONFIG_BFIN_BOOT_MODE),BFIN_BOOT_UART)
 LDR_FLAGS-$(CONFIG_ENV_IS_EMBEDDED_IN_LDR) += \
-	--punchit $$(($(CONFIG_ENV_OFFSET))):$$(($(CONFIG_ENV_SIZE))):$(obj)env-ldr.o
+	--punchit $$(($(CONFIG_ENV_OFFSET))):$$(($(CONFIG_ENV_SIZE))):env-ldr.o
 endif
 ifneq (,$(findstring s,$(MAKEFLAGS)))
 LDR_FLAGS += --quiet
diff --git a/arch/blackfin/cpu/.gitignore b/arch/blackfin/cpu/.gitignore
index ba986d8ba8..3df1fa21c9 100644
--- a/arch/blackfin/cpu/.gitignore
+++ b/arch/blackfin/cpu/.gitignore
@@ -1,4 +1,2 @@
-bootrom-asm-offsets.[chs]
-
 init.lds
 init.elf
diff --git a/arch/blackfin/cpu/Makefile b/arch/blackfin/cpu/Makefile
index 1421cb2ca2..cfbcd3124f 100644
--- a/arch/blackfin/cpu/Makefile
+++ b/arch/blackfin/cpu/Makefile
@@ -9,48 +9,26 @@
 # Licensed under the GPL-2 or later.
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(CPU).o
-
-EXTRA    := init.elf
-CEXTRA   := initcode.o
-SEXTRA   := start.o
-SOBJS    := interrupt.o cache.o
-COBJS-y  += cpu.o
-COBJS-$(CONFIG_ADI_GPIO1) += gpio.o
-COBJS-y  += interrupts.o
-COBJS-$(CONFIG_JTAG_CONSOLE) += jtag-console.o
-COBJS-y  += os_log.o
-COBJS-y  += reset.o
-COBJS-y  += traps.o
-
-SRCS     := $(SEXTRA:.o=.S) $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
-OBJS     := $(addprefix $(obj),$(COBJS-y) $(SOBJS))
-EXTRA    := $(addprefix $(obj),$(EXTRA))
-CEXTRA   := $(addprefix $(obj),$(CEXTRA))
-SEXTRA   := $(addprefix $(obj),$(SEXTRA))
-
-all:	$(obj).depend $(LIB) $(obj).depend $(EXTRA) $(CEXTRA) $(SEXTRA) check_initcode
-
-$(LIB):	$(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-$(OBJS): $(obj)bootrom-asm-offsets.h
-$(obj)bootrom-asm-offsets.c: bootrom-asm-offsets.c.in bootrom-asm-offsets.awk
-	echo '#include <asm/mach-common/bits/bootrom.h>' | $(CPP) $(CPPFLAGS) - | gawk -f ./bootrom-asm-offsets.awk > $@.tmp
-	mv $@.tmp $@
-$(obj)bootrom-asm-offsets.s: $(obj)bootrom-asm-offsets.c
-	$(CC) $(CFLAGS) -S $^ -o $@.tmp
-	mv $@.tmp $@
-$(obj)bootrom-asm-offsets.h: $(obj)bootrom-asm-offsets.s
-	sed -ne "/^->/{s:^->\([^ ]*\) [\$$#]*\([^ ]*\) \(.*\):#define \1 \2 /* \3 */:; s:->::; p;}" $^ > $@
+extra-y := init.elf
+extra-y += initcode.o
+extra-y += start.o
+obj-y    := interrupt.o cache.o
+obj-y  += cpu.o
+obj-y += gpio.o
+obj-y  += interrupts.o
+obj-$(CONFIG_JTAG_CONSOLE) += jtag-console.o
+obj-y  += os_log.o
+obj-y  += reset.o
+obj-y  += traps.o
+
+extra-y += check_initcode
+clean-files := init.lds
 
 # make sure our initcode (which goes into LDR) does not
 # have relocs or external references
-$(obj)initcode.o: CFLAGS += -fno-function-sections -fno-data-sections
+CFLAGS_REMOVE_initcode.o := -ffunction-sections -fdata-sections
 READINIT = env LC_ALL=C $(CROSS_COMPILE)readelf -s $<
-check_initcode: $(obj)initcode.o
+$(obj)/check_initcode: $(obj)/initcode.o
 ifneq ($(CONFIG_BFIN_BOOT_MODE),BFIN_BOOT_BYPASS)
 	@if $(READINIT) | grep '\<GLOBAL\>.*\<UND\>' ; then \
 		echo "$< contains external references!" 1>&2 ; \
@@ -58,16 +36,10 @@ ifneq ($(CONFIG_BFIN_BOOT_MODE),BFIN_BOOT_BYPASS)
 	fi
 endif
 
-$(obj)init.lds: init.lds.S
-	$(CPP) $(CPPFLAGS) $(LDPPFLAGS) -ansi -D__ASSEMBLY__ -P $^ -o $@
-$(obj)init.elf: $(obj)init.lds $(obj)init.o $(obj)initcode.o
-	$(LD) $(LDFLAGS) -T $^ -o $@
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
+CPPFLAGS_init.lds := -ansi
 
-#########################################################################
+quiet_cmd_link_init = LD      $@
+      cmd_link_init = $(LD) $(LDFLAGS) -T $^ -o $@
+$(obj)/init.elf: $(obj)/init.lds $(obj)/init.o $(obj)/initcode.o
+	$(call if_changed,link_init)
+targets += init.lds init.o
diff --git a/arch/blackfin/cpu/bootrom-asm-offsets.awk b/arch/blackfin/cpu/bootrom-asm-offsets.awk
deleted file mode 100755
index 1d61824254..0000000000
--- a/arch/blackfin/cpu/bootrom-asm-offsets.awk
+++ /dev/null
@@ -1,41 +0,0 @@
-#!/usr/bin/gawk -f
-BEGIN {
-	print "/* DO NOT EDIT: AUTOMATICALLY GENERATED"
-	print " * Input files: bootrom-asm-offsets.awk bootrom-asm-offsets.c.in"
-	print " * DO NOT EDIT: AUTOMATICALLY GENERATED"
-	print " */"
-	print ""
-	system("cat bootrom-asm-offsets.c.in")
-	print "{"
-}
-
-{
-	/* find a structure definition */
-	if ($0 ~ /typedef struct .* {/) {
-		delete members;
-		i = 0;
-
-		/* extract each member of the structure */
-		while (1) {
-			getline
-			if ($1 == "}")
-				break;
-			gsub(/[*;]/, "");
-			members[i++] = $NF;
-		}
-
-		/* grab the structure's name */
-		struct = $NF;
-		sub(/;$/, "", struct);
-
-		/* output the DEFINE() macros */
-		while (i-- > 0)
-			print "\tDEFINE(" struct ", " members[i] ");"
-		print ""
-	}
-}
-
-END {
-	print "\treturn 0;"
-	print "}"
-}
diff --git a/arch/blackfin/cpu/bootrom-asm-offsets.c.in b/arch/blackfin/cpu/bootrom-asm-offsets.c.in
deleted file mode 100644
index 64c2f24120..0000000000
--- a/arch/blackfin/cpu/bootrom-asm-offsets.c.in
+++ /dev/null
@@ -1,12 +0,0 @@
-/* A little trick taken from the kernel asm-offsets.h where we convert
- * the C structures automatically into a bunch of defines for use in
- * the assembly files.
- */
-
-#include <linux/stddef.h>
-#include <asm/mach-common/bits/bootrom.h>
-
-#define _DEFINE(sym, val) asm volatile("\n->" #sym " %0 " #val : : "i" (val))
-#define DEFINE(s, m) _DEFINE(offset_##s##_##m, offsetof(s, m))
-
-int main(int argc, char * const argv[])
diff --git a/arch/blackfin/cpu/cpu.c b/arch/blackfin/cpu/cpu.c
index 218f57ed38..2409c300ed 100644
--- a/arch/blackfin/cpu/cpu.c
+++ b/arch/blackfin/cpu/cpu.c
@@ -104,6 +104,9 @@ void cpu_init_f(ulong bootflag, ulong loaded_from_ldr)
 
 	serial_early_puts("Board init flash\n");
 	board_init_f(bootflag);
+
+	/* should not be reached */
+	while (1);
 }
 
 int exception_init(void)
diff --git a/arch/blackfin/cpu/gpio.c b/arch/blackfin/cpu/gpio.c
index f9aff4d894..86da706f08 100644
--- a/arch/blackfin/cpu/gpio.c
+++ b/arch/blackfin/cpu/gpio.c
@@ -12,6 +12,7 @@
 #include <asm/gpio.h>
 #include <asm/portmux.h>
 
+#ifndef CONFIG_ADI_GPIO2
 #if ANOMALY_05000311 || ANOMALY_05000323
 enum {
 	AWA_data = SYSCR,
@@ -774,3 +775,19 @@ void gpio_labels(void)
 			continue;
 	}
 }
+#else
+struct gpio_port_t * const gpio_array[] = {
+	(struct gpio_port_t *)PORTA_FER,
+	(struct gpio_port_t *)PORTB_FER,
+	(struct gpio_port_t *)PORTC_FER,
+	(struct gpio_port_t *)PORTD_FER,
+	(struct gpio_port_t *)PORTE_FER,
+	(struct gpio_port_t *)PORTF_FER,
+	(struct gpio_port_t *)PORTG_FER,
+#if defined(CONFIG_BF54x)
+	(struct gpio_port_t *)PORTH_FER,
+	(struct gpio_port_t *)PORTI_FER,
+	(struct gpio_port_t *)PORTJ_FER,
+#endif
+};
+#endif
diff --git a/arch/blackfin/cpu/initcode.c b/arch/blackfin/cpu/initcode.c
index ffaf1017d7..2e640afc45 100644
--- a/arch/blackfin/cpu/initcode.c
+++ b/arch/blackfin/cpu/initcode.c
@@ -18,8 +18,6 @@
 #include <asm/mach-common/bits/core.h>
 #include <asm/serial.h>
 
-#define BUG() while (1) asm volatile("emuexcpt;");
-
 #ifndef __ADSPBF60x__
 #include <asm/mach-common/bits/ebiu.h>
 #include <asm/mach-common/bits/pll.h>
@@ -147,8 +145,6 @@ static struct ddr_config ddr_config_table[] = {
 __attribute__((always_inline))
 static inline void serial_init(void)
 {
-	uint32_t uart_base = UART_BASE;
-
 #if defined(__ADSPBF54x__) || defined(__ADSPBF60x__)
 # ifdef BFIN_BOOT_UART_USE_RTS
 #  define BFIN_UART_USE_RTS 1
@@ -156,6 +152,7 @@ static inline void serial_init(void)
 #  define BFIN_UART_USE_RTS 0
 # endif
 	if (BFIN_UART_USE_RTS && CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_UART) {
+		uint32_t uart_base = UART_BASE;
 		size_t i;
 
 		/* force RTS rather than relying on auto RTS */
@@ -195,8 +192,8 @@ static inline void serial_init(void)
 
 #if CONFIG_BFIN_BOOT_MODE != BFIN_BOOT_BYPASS
 	if (BFIN_DEBUG_EARLY_SERIAL) {
-		serial_early_init(uart_base);
-		serial_early_set_baud(uart_base, CONFIG_BAUDRATE);
+		serial_early_init(UART_BASE);
+		serial_early_set_baud(UART_BASE, CONFIG_BAUDRATE);
 	}
 #endif
 }
@@ -547,7 +544,7 @@ maybe_self_refresh(ADI_BOOT_DATA *bs)
 __attribute__((always_inline)) static inline u16
 program_clocks(ADI_BOOT_DATA *bs, bool put_into_srfs)
 {
-	u16 vr_ctl;
+	u16 vr_ctl = 0;
 
 	serial_putc('a');
 
@@ -731,6 +728,8 @@ update_serial_clocks(ADI_BOOT_DATA *bs, uint sdivB, uint divB, uint vcoB)
 
 	serial_putc('a');
 
+	if (BFIN_DEBUG_EARLY_SERIAL ||
+		CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_UART) {
 #ifdef __ADSPBF60x__
 	sdivR = bfin_read_CGU_DIV();
 	sdivR = ((sdivR >> 8) & 0x1f) * ((sdivR >> 5) & 0x7);
@@ -744,6 +743,8 @@ update_serial_clocks(ADI_BOOT_DATA *bs, uint sdivB, uint divB, uint vcoB)
 	divisor = vcoB * sdivR;
 	quotient = early_division(dividend, divisor);
 	serial_early_put_div(quotient - ANOMALY_05000230);
+	}
+
 	serial_putc('c');
 }
 
@@ -913,7 +914,8 @@ check_hibernation(ADI_BOOT_DATA *bs, u16 vr_ctl, bool put_into_srfs)
 			continue;
 
 		serial_putc('z');
-		uint32_t *hibernate_magic = bfin_read32(DPM0_RESTORE4);
+		uint32_t *hibernate_magic =
+			(uint32_t *)bfin_read32(DPM0_RESTORE4);
 		SSYNC(); /* make sure memory controller is done */
 		if (hibernate_magic[0] == 0xDEADBEEF) {
 			serial_putc('c');
diff --git a/arch/blackfin/cpu/initcode.h b/arch/blackfin/cpu/initcode.h
index 1fec7f3d85..ab7fa45075 100644
--- a/arch/blackfin/cpu/initcode.h
+++ b/arch/blackfin/cpu/initcode.h
@@ -49,7 +49,7 @@ program_async_controller(ADI_BOOT_DATA *bs)
 
 	serial_putc('a');
 
-#ifdef __ADSPBF60x__
+#ifndef __ADSPBF60x__
 	/* Program the async banks controller. */
 #ifdef EBIU_AMGCTL
 	bfin_write_EBIU_AMBCTL0(CONFIG_EBIU_AMBCTL0_VAL);
@@ -74,7 +74,7 @@ program_async_controller(ADI_BOOT_DATA *bs)
 
 	serial_putc('c');
 
-#else   /* __ADSPBF60x__ */
+#else 	/* __ADSPBF60x__ */
 	/* Program the static memory controller. */
 # ifdef CONFIG_SMC_GCTL_VAL
 	bfin_write_SMC_GCTL(CONFIG_SMC_GCTL_VAL);
@@ -116,7 +116,7 @@ program_async_controller(ADI_BOOT_DATA *bs)
 	bfin_write_SMC_B3ETIM(CONFIG_SMC_B3ETIM_VAL);
 # endif
 
-#endif
+#endif /* __ADSPBF60x__ */
 	serial_putc('d');
 }
 
diff --git a/arch/blackfin/cpu/os_log.c b/arch/blackfin/cpu/os_log.c
index e1c8e2948d..2092d9e3b6 100644
--- a/arch/blackfin/cpu/os_log.c
+++ b/arch/blackfin/cpu/os_log.c
@@ -12,12 +12,12 @@
 #define OS_LOG_MAGIC_ADDR  ((unsigned long *)0x4f0)
 #define OS_LOG_PTR_ADDR    ((char **)0x4f4)
 
-bool bfin_os_log_check(void)
+int bfin_os_log_check(void)
 {
 	if (*OS_LOG_MAGIC_ADDR != OS_LOG_MAGIC)
-		return false;
+		return 0;
 	*OS_LOG_MAGIC_ADDR = 0;
-	return true;
+	return 1;
 }
 
 void bfin_os_log_dump(void)
diff --git a/arch/blackfin/cpu/start.S b/arch/blackfin/cpu/start.S
index c99cf49833..29a7c232e2 100644
--- a/arch/blackfin/cpu/start.S
+++ b/arch/blackfin/cpu/start.S
@@ -190,6 +190,7 @@ ENTRY(_start)
 	call _memcpy_ASM;
 #endif
 
+.Lnorelocate:
 	/* Initialize BSS section ... we know that memset() does not
 	 * use the BSS, so it is safe to call here.  The bootrom LDR
 	 * takes care of clearing things for us.
@@ -202,7 +203,6 @@ ENTRY(_start)
 	r2.h = __bss_len;
 	call _memset;
 
-.Lnorelocate:
 
 	/* Setup the actual stack in external memory */
 	sp.h = HI(CONFIG_STACKBASE);
diff --git a/arch/blackfin/include/asm/bitops.h b/arch/blackfin/include/asm/bitops.h
index b58b0050ce..cd7e356459 100644
--- a/arch/blackfin/include/asm/bitops.h
+++ b/arch/blackfin/include/asm/bitops.h
@@ -13,7 +13,6 @@
  * Copyright 1992, Linus Torvalds.
  */
 
-#include <linux/config.h>
 #include <asm/byteorder.h>
 #include <asm/system.h>
 
diff --git a/arch/blackfin/include/asm/blackfin_local.h b/arch/blackfin/include/asm/blackfin_local.h
index ab31dcb815..868c82ea7d 100644
--- a/arch/blackfin/include/asm/blackfin_local.h
+++ b/arch/blackfin/include/asm/blackfin_local.h
@@ -42,16 +42,9 @@
 
 # include <linux/types.h>
 
-extern u_long get_vco(void);
-extern u_long get_cclk(void);
-extern u_long get_sclk(void);
-extern u_long get_sclk0(void);
-extern u_long get_sclk1(void);
-extern u_long get_dclk(void);
-
 # define bfin_revid() (bfin_read_CHIPID() >> 28)
 
-extern bool bfin_os_log_check(void);
+extern int bfin_os_log_check(void);
 extern void bfin_os_log_dump(void);
 
 extern void blackfin_icache_flush_range(const void *, const void *);
@@ -81,6 +74,8 @@ extern void blackfin_dcache_flush_invalidate_range(const void *, const void *);
 # define NOP_PAD_ANOMALY_05000198
 #endif
 
+#define BFIN_BUG() while (1) asm volatile("emuexcpt;");
+
 #define _bfin_readX(addr, size, asm_size, asm_ext) ({ \
 	u32 __v; \
 	__asm__ __volatile__( \
@@ -111,7 +106,7 @@ extern void blackfin_dcache_flush_invalidate_range(const void *, const void *);
 	sizeof(*(addr)) == 1 ? bfin_read8(addr)  : \
 	sizeof(*(addr)) == 2 ? bfin_read16(addr) : \
 	sizeof(*(addr)) == 4 ? bfin_read32(addr) : \
-	({ BUG(); 0; }); \
+	({ BFIN_BUG(); 0; }); \
 })
 #define bfin_write(addr, val) \
 do { \
@@ -119,7 +114,8 @@ do { \
 	case 1: bfin_write8(addr, val);  break; \
 	case 2: bfin_write16(addr, val); break; \
 	case 4: bfin_write32(addr, val); break; \
-	default: BUG(); \
+	default: \
+		BFIN_BUG(); \
 	} \
 } while (0)
 
diff --git a/arch/blackfin/include/asm/clock.h b/arch/blackfin/include/asm/clock.h
index f1fcd40499..59d3faa29d 100644
--- a/arch/blackfin/include/asm/clock.h
+++ b/arch/blackfin/include/asm/clock.h
@@ -1,4 +1,3 @@
-
 /*
  * Copyright (C) 2012 Analog Devices Inc.
  * Licensed under the GPL-2 or later.
@@ -69,10 +68,21 @@ static inline uint32_t early_get_uart_clk(void)
 	return uclk;
 }
 
+extern u_long get_vco(void);
+extern u_long get_cclk(void);
+extern u_long get_sclk(void);
+
 #ifdef CGU_DIV
+extern u_long get_sclk0(void);
+extern u_long get_sclk1(void);
+extern u_long get_dclk(void);
 # define get_uart_clk get_sclk0
+# define get_i2c_clk get_sclk0
+# define get_spi_clk get_sclk0
 #else
 # define get_uart_clk get_sclk
+# define get_i2c_clk get_sclk
+# define get_spi_clk get_sclk
 #endif
 
 #endif
diff --git a/arch/blackfin/include/asm/config.h b/arch/blackfin/include/asm/config.h
index d870d1224f..1da386ea49 100644
--- a/arch/blackfin/include/asm/config.h
+++ b/arch/blackfin/include/asm/config.h
@@ -155,13 +155,6 @@
 #ifndef CONFIG_SYS_MAXARGS
 # define CONFIG_SYS_MAXARGS 16
 #endif
-#if defined(CONFIG_SYS_HZ)
-# if (CONFIG_SYS_HZ != 1000)
-#  warning "CONFIG_SYS_HZ must always be 1000"
-# endif
-# undef CONFIG_SYS_HZ
-#endif
-#define CONFIG_SYS_HZ 1000
 
 /* Blackfin POST tests */
 #ifdef CONFIG_POST_BSPEC1_GPIO_LEDS
diff --git a/arch/blackfin/include/asm/gpio.h b/arch/blackfin/include/asm/gpio.h
index 58a6191107..6ebcf01aff 100644
--- a/arch/blackfin/include/asm/gpio.h
+++ b/arch/blackfin/include/asm/gpio.h
@@ -8,6 +8,7 @@
 #define __ARCH_BLACKFIN_GPIO_H__
 
 #include <asm-generic/gpio.h>
+#include <asm/portmux.h>
 
 #define gpio_bank(x)	((x) >> 4)
 #define gpio_bit(x)	(1<<((x) & 0xF))
@@ -71,7 +72,7 @@
 
 #ifndef __ASSEMBLY__
 
-#ifdef CONFIG_ADI_GPIO1
+#ifndef CONFIG_ADI_GPIO2
 void set_gpio_dir(unsigned, unsigned short);
 void set_gpio_inen(unsigned, unsigned short);
 void set_gpio_polar(unsigned, unsigned short);
@@ -141,6 +142,8 @@ struct gpio_port_t {
 	unsigned short dummy16;
 	unsigned short inen;
 };
+#else
+extern struct gpio_port_t * const gpio_array[];
 #endif
 
 #ifdef ADI_SPECIAL_GPIO_BANKS
diff --git a/arch/blackfin/include/asm/mach-common/bits/emac.h b/arch/blackfin/include/asm/mach-common/bits/emac.h
index 7a43bbb1a3..4c9bc9dc57 100644
--- a/arch/blackfin/include/asm/mach-common/bits/emac.h
+++ b/arch/blackfin/include/asm/mach-common/bits/emac.h
@@ -217,4 +217,7 @@
 #define	TX_GE1024_CNT	0x00200000	/* 1024-Max-Byte TX Frames Sent */
 #define	TX_ABORT_CNT	0x00400000	/* TX Frames Aborted */
 
+/*default value for EMAC_VLANx reg*/
+#define EMAC_VLANX_DEF_VAL 0xFFFF
+
 #endif
diff --git a/arch/blackfin/include/asm/mach-common/bits/lockbox.h b/arch/blackfin/include/asm/mach-common/bits/lockbox.h
deleted file mode 100644
index 17d22ab57f..0000000000
--- a/arch/blackfin/include/asm/mach-common/bits/lockbox.h
+++ /dev/null
@@ -1,62 +0,0 @@
-/*
- * Lockbox/Security Masks
- */
-
-#ifndef __BFIN_PERIPHERAL_LOCKBOX__
-#define __BFIN_PERIPHERAL_LOCKBOX__
-
-#ifndef __ASSEMBLY__
-
-#include "bootrom.h"
-
-/* SESR argument structure. Expected to reside at 0xFF900018. */
-typedef struct SESR_args {
-	unsigned short  usFlags;            /* security firmware flags            */
-	unsigned short  usIRQMask;          /* interrupt mask                     */
-	unsigned long   ulMessageSize;      /* message length in bytes            */
-	unsigned long   ulSFEntryPoint;     /* entry point of secure function     */
-	unsigned long   ulMessagePtr;       /* pointer to the buffer containing
-					       the digital signature and message  */
-	unsigned long   ulReserved1;        /* reserved                           */
-	unsigned long   ulReserved2;        /* reserved                           */
-} tSESR_args;
-
-/* Secure Entry Service Routine */
-static void (* const sesr)(void) = (void *)_BOOTROM_SESR;
-
-#endif
-
-/* SESR flags argument bitfields */
-#define SESR_FLAGS_STAY_AT_NMI              0x0000
-#define SESR_FLAGS_DROP_BELOW_NMI           0x0001
-#define SESR_FLAGS_NO_SF_DMA                0x0000
-#define SESR_FLAGS_DMA_SF_TO_RUN_DEST       0x0002
-#define SESR_FLAGS_USE_ADI_PUB_KEY          0x0000
-#define SESR_FLAGS_USE_CUST_PUB_KEY         0x0100
-
-/* Bit masks for SECURE_SYSSWT */
-#define EMUDABL                0x00000001    /* Emulation Disable */
-#define RSTDABL                0x00000002    /* Reset Disable */
-#define L1IDABL                0x0000001c    /* L1 Instruction Memory Disable */
-#define L1DADABL               0x000000e0    /* L1 Data Bank A Memory Disable */
-#define L1DBDABL               0x00000700    /* L1 Data Bank B Memory Disable */
-#define DMA0OVR                0x00000800    /* DMA0 Memory Access Override */
-#define DMA1OVR                0x00001000    /* DMA1 Memory Access Override */
-#define EMUOVR                 0x00004000    /* Emulation Override */
-#define OTPSEN                 0x00008000    /* OTP Secrets Enable */
-#define L2DABL                 0x00070000    /* L2 Memory Disable */
-
-/* Bit masks for SECURE_CONTROL */
-#define SECURE0                0x0001        /* SECURE 0 */
-#define SECURE1                0x0002        /* SECURE 1 */
-#define SECURE2                0x0004        /* SECURE 2 */
-#define SECURE3                0x0008        /* SECURE 3 */
-
-/* Bit masks for SECURE_STATUS */
-#define SECMODE                0x0003        /* Secured Mode Control State */
-#define NMI                    0x0004        /* Non Maskable Interrupt */
-#define AFVALID                0x0008        /* Authentication Firmware Valid */
-#define AFEXIT                 0x0010        /* Authentication Firmware Exit */
-#define SECSTAT                0x00e0        /* Secure Status */
-
-#endif
diff --git a/arch/blackfin/include/asm/mach-common/bits/sport.h b/arch/blackfin/include/asm/mach-common/bits/sport.h
deleted file mode 100644
index 88e7a5d324..0000000000
--- a/arch/blackfin/include/asm/mach-common/bits/sport.h
+++ /dev/null
@@ -1,89 +0,0 @@
-/*
- * SPORT Masks
- */
-
-#ifndef __BFIN_PERIPHERAL_SPORT__
-#define __BFIN_PERIPHERAL_SPORT__
-
-/* SPORTx_TCR1 Masks */
-#define TSPEN			0x0001	/* TX enable */
-#define ITCLK			0x0002	/* Internal TX Clock Select */
-#define TDTYPE			0x000C	/* TX Data Formatting Select */
-#define DTYPE_NORM		0x0004	/* Data Format Normal */
-#define DTYPE_ULAW		0x0008	/* Compand Using u-Law */
-#define DTYPE_ALAW		0x000C	/* Compand Using A-Law */
-#define TLSBIT			0x0010	/* TX Bit Order */
-#define ITFS			0x0200	/* Internal TX Frame Sync Select */
-#define TFSR			0x0400	/* TX Frame Sync Required Select */
-#define DITFS			0x0800	/* Data Independent TX Frame Sync Select */
-#define LTFS			0x1000	/* Low TX Frame Sync Select */
-#define LATFS			0x2000	/* Late TX Frame Sync Select */
-#define TCKFE			0x4000	/* TX Clock Falling Edge Select */
-
-/* SPORTx_TCR2 Masks */
-#define SLEN			0x001F	/* TX Word Length */
-#define TXSE			0x0100	/* TX Secondary Enable */
-#define TSFSE			0x0200	/* TX Stereo Frame Sync Enable */
-#define TRFST			0x0400	/* TX Right-First Data Order */
-
-/* SPORTx_RCR1 Masks */
-#define RSPEN			0x0001	/* RX enable */
-#define IRCLK			0x0002	/* Internal RX Clock Select */
-#define RDTYPE			0x000C	/* RX Data Formatting Select */
-#define DTYPE_NORM		0x0004	/* Data Format Normal */
-#define DTYPE_ULAW		0x0008	/* Compand Using u-Law */
-#define DTYPE_ALAW		0x000C	/* Compand Using A-Law */
-#define RLSBIT			0x0010	/* RX Bit Order */
-#define IRFS			0x0200	/* Internal RX Frame Sync Select */
-#define RFSR			0x0400	/* RX Frame Sync Required Select */
-#define LRFS			0x1000	/* Low RX Frame Sync Select */
-#define LARFS			0x2000	/* Late RX Frame Sync Select */
-#define RCKFE			0x4000	/* RX Clock Falling Edge Select */
-
-/* SPORTx_RCR2 Masks */
-#define SLEN			0x001F	/* RX Word Length */
-#define RXSE			0x0100	/* RX Secondary Enable */
-#define RSFSE			0x0200	/* RX Stereo Frame Sync Enable */
-#define RRFST			0x0400	/* Right-First Data Order */
-
-/* SPORTx_STAT Masks */
-#define RXNE			0x0001	/* RX FIFO Not Empty Status */
-#define RUVF			0x0002	/* RX Underflow Status */
-#define ROVF			0x0004	/* RX Overflow Status */
-#define TXF			0x0008	/* TX FIFO Full Status */
-#define TUVF			0x0010	/* TX Underflow Status */
-#define TOVF			0x0020	/* TX Overflow Status */
-#define TXHRE			0x0040	/* TX Hold Register Empty */
-
-/* SPORTx_MCMC1 Masks */
-#define WSIZE			0xF000	/* Multichannel Window Size Field */
-#define WOFF			0x03FF	/* Multichannel Window Offset Field */
-
-/* SPORTx_MCMC2 Masks */
-#define MCCRM			0x0003	/* Multichannel Clock Recovery Mode */
-#define REC_BYPASS		0x0000	/* Bypass Mode (No Clock Recovery) */
-#define REC_2FROM4		0x0002	/* Recover 2 MHz Clock from 4 MHz Clock */
-#define REC_8FROM16		0x0003	/* Recover 8 MHz Clock from 16 MHz Clock */
-#define MCDTXPE			0x0004	/* Multichannel DMA Transmit Packing */
-#define MCDRXPE			0x0008	/* Multichannel DMA Receive Packing */
-#define MCMEN			0x0010	/* Multichannel Frame Mode Enable */
-#define FSDR			0x0080	/* Multichannel Frame Sync to Data Relationship */
-#define MFD			0xF000	/* Multichannel Frame Delay */
-#define MFD_0			0x0000	/* Multichannel Frame Delay = 0 */
-#define MFD_1			0x1000	/* Multichannel Frame Delay = 1 */
-#define MFD_2			0x2000	/* Multichannel Frame Delay = 2 */
-#define MFD_3			0x3000	/* Multichannel Frame Delay = 3 */
-#define MFD_4			0x4000	/* Multichannel Frame Delay = 4 */
-#define MFD_5			0x5000	/* Multichannel Frame Delay = 5 */
-#define MFD_6			0x6000	/* Multichannel Frame Delay = 6 */
-#define MFD_7			0x7000	/* Multichannel Frame Delay = 7 */
-#define MFD_8			0x8000	/* Multichannel Frame Delay = 8 */
-#define MFD_9			0x9000	/* Multichannel Frame Delay = 9 */
-#define MFD_10			0xA000	/* Multichannel Frame Delay = 10 */
-#define MFD_11			0xB000	/* Multichannel Frame Delay = 11 */
-#define MFD_12			0xC000	/* Multichannel Frame Delay = 12 */
-#define MFD_13			0xD000	/* Multichannel Frame Delay = 13 */
-#define MFD_14			0xE000	/* Multichannel Frame Delay = 14 */
-#define MFD_15			0xF000	/* Multichannel Frame Delay = 15 */
-
-#endif
diff --git a/arch/blackfin/include/asm/twi.h b/arch/blackfin/include/asm/twi.h
new file mode 100644
index 0000000000..922cdbd892
--- /dev/null
+++ b/arch/blackfin/include/asm/twi.h
@@ -0,0 +1,15 @@
+/*
+ * i2c.c - driver for Blackfin on-chip TWI/I2C
+ *
+ * Copyright (c) 2006-2010 Analog Devices Inc.
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+#ifndef __ARCH_TWI_H
+#define __ARCH_TWI_H
+
+#include <asm/blackfin.h>
+#include <asm/mach-common/bits/twi.h>
+
+#endif
diff --git a/arch/blackfin/lib/Makefile b/arch/blackfin/lib/Makefile
index 5603eb93e5..4ba7bf6949 100644
--- a/arch/blackfin/lib/Makefile
+++ b/arch/blackfin/lib/Makefile
@@ -9,41 +9,24 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-CFLAGS += -DBFIN_BOARD_NAME='"$(BOARD)"'
-
-LIB	= $(obj)lib$(ARCH).o
-
-SOBJS-y	+= ins.o
-SOBJS-y	+= memcmp.o
-SOBJS-y	+= memcpy.o
-SOBJS-y	+= memmove.o
-SOBJS-y	+= memset.o
-SOBJS-y	+= outs.o
-SOBJS-$(CONFIG_CMD_KGDB) += __kgdb.o
-
-COBJS-y	+= board.o
-COBJS-y	+= boot.o
-COBJS-y	+= cache.o
-COBJS-y	+= clocks.o
-COBJS-$(CONFIG_CMD_CACHE_DUMP) += cmd_cache_dump.o
-COBJS-$(CONFIG_CMD_KGDB) += kgdb.o
-COBJS-y	+= muldi3.o
-COBJS-$(CONFIG_HAS_POST) += post.o
-COBJS-y	+= string.o
-
-SRCS	:= $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
-OBJS	:= $(addprefix $(obj),$(SOBJS-y) $(COBJS-y))
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+# Unnecessary.
+# Use CONFIG_SYS_BOARD instead of BFIN_BOARD_NAME
+# and delete this.
+ccflags-y += -DBFIN_BOARD_NAME='"$(BOARD)"'
+
+obj-y	+= ins.o
+obj-y	+= memcmp.o
+obj-y	+= memcpy.o
+obj-y	+= memmove.o
+obj-y	+= memset.o
+obj-y	+= outs.o
+obj-$(CONFIG_CMD_KGDB) += __kgdb.o
+obj-y	+= board.o
+obj-y	+= boot.o
+obj-y	+= cache.o
+obj-y	+= clocks.o
+obj-$(CONFIG_CMD_CACHE_DUMP) += cmd_cache_dump.o
+obj-$(CONFIG_CMD_KGDB) += kgdb.o
+obj-y	+= muldi3.o
+obj-$(CONFIG_HAS_POST) += post.o
+obj-y	+= string.o
diff --git a/arch/blackfin/lib/__kgdb.S b/arch/blackfin/lib/__kgdb.S
index 4ccde8f104..4e7b6a4eb5 100644
--- a/arch/blackfin/lib/__kgdb.S
+++ b/arch/blackfin/lib/__kgdb.S
@@ -1,4 +1,3 @@
-
 #include <linux/linkage.h>
 
 /* save stack context for non-local goto
diff --git a/arch/blackfin/lib/board.c b/arch/blackfin/lib/board.c
index 17d1f468dd..62342014a4 100644
--- a/arch/blackfin/lib/board.c
+++ b/arch/blackfin/lib/board.c
@@ -19,9 +19,11 @@
 #include <net.h>
 #include <status_led.h>
 #include <version.h>
+#include <watchdog.h>
 
 #include <asm/cplb.h>
 #include <asm/mach-common/bits/mpu.h>
+#include <asm/clock.h>
 #include <kgdb.h>
 
 #ifdef CONFIG_CMD_NAND
@@ -141,7 +143,8 @@ void init_cplbtables(void)
 	++i;
 #if defined(__ADSPBF60x__)
 	icplb_add(0x0, 0x0);
-	dcplb_add(CONFIG_SYS_FLASH_BASE, SDRAM_EBIU);
+	dcplb_add(CONFIG_SYS_FLASH_BASE, PAGE_SIZE_16MB | CPLB_DIRTY |
+		CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID);
 	++i;
 #endif
 
diff --git a/arch/blackfin/lib/clocks.c b/arch/blackfin/lib/clocks.c
index 97795e11ac..7ed56a7274 100644
--- a/arch/blackfin/lib/clocks.c
+++ b/arch/blackfin/lib/clocks.c
@@ -36,7 +36,10 @@ u_long get_vco(void)
 u_long get_cclk(void)
 {
 	static u_long cached_cclk_pll_div, cached_cclk;
-	u_long div, csel, ssel;
+	u_long div, csel;
+#ifndef CGU_DIV
+	u_long ssel;
+#endif
 
 	if (pll_is_bypassed())
 		return CONFIG_CLKIN_HZ;
diff --git a/arch/m68k/config.mk b/arch/m68k/config.mk
index 9c3e24f2fc..33b3d51af0 100644
--- a/arch/m68k/config.mk
+++ b/arch/m68k/config.mk
@@ -5,11 +5,14 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-CROSS_COMPILE ?= m68k-elf-
+ifeq ($(CROSS_COMPILE),)
+CROSS_COMPILE := m68k-elf-
+endif
 
 CONFIG_STANDALONE_LOAD_ADDR ?= 0x20000
 
 PLATFORM_CPPFLAGS += -DCONFIG_M68K -D__M68K__
 PLATFORM_LDFLAGS  += -n
-PLATFORM_RELFLAGS              += -ffunction-sections -fdata-sections
+PLATFORM_RELFLAGS += -ffunction-sections -fdata-sections
+PLATFORM_RELFLAGS += -ffixed-d7 -msep-data
 LDFLAGS_FINAL                  += --gc-sections
diff --git a/arch/m68k/cpu/mcf5227x/Makefile b/arch/m68k/cpu/mcf5227x/Makefile
index e5384cc10e..e0c5db60f4 100644
--- a/arch/m68k/cpu/mcf5227x/Makefile
+++ b/arch/m68k/cpu/mcf5227x/Makefile
@@ -5,28 +5,7 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
+# ccflags-y += -DET_DEBUG
 
-# CFLAGS += -DET_DEBUG
-
-LIB	= $(obj)lib$(CPU).o
-
-START	= start.o
-COBJS	= cpu.o speed.o cpu_init.o interrupts.o
-
-SRCS	:= $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS))
-START	:= $(addprefix $(obj),$(START))
-
-all:	$(obj).depend $(START) $(LIB)
-
-$(LIB):	$(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+extra-y	= start.o
+obj-y	= cpu.o speed.o cpu_init.o interrupts.o
diff --git a/arch/m68k/cpu/mcf5227x/config.mk b/arch/m68k/cpu/mcf5227x/config.mk
index 2681171458..b5c26e4e5b 100644
--- a/arch/m68k/cpu/mcf5227x/config.mk
+++ b/arch/m68k/cpu/mcf5227x/config.mk
@@ -7,5 +7,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-PLATFORM_RELFLAGS += -ffixed-d7 -msep-data
 PLATFORM_CPPFLAGS += -mcpu=52277 -fPIC
diff --git a/arch/m68k/cpu/mcf523x/Makefile b/arch/m68k/cpu/mcf523x/Makefile
index e5384cc10e..e0c5db60f4 100644
--- a/arch/m68k/cpu/mcf523x/Makefile
+++ b/arch/m68k/cpu/mcf523x/Makefile
@@ -5,28 +5,7 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
+# ccflags-y += -DET_DEBUG
 
-# CFLAGS += -DET_DEBUG
-
-LIB	= $(obj)lib$(CPU).o
-
-START	= start.o
-COBJS	= cpu.o speed.o cpu_init.o interrupts.o
-
-SRCS	:= $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS))
-START	:= $(addprefix $(obj),$(START))
-
-all:	$(obj).depend $(START) $(LIB)
-
-$(LIB):	$(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+extra-y	= start.o
+obj-y	= cpu.o speed.o cpu_init.o interrupts.o
diff --git a/arch/m68k/cpu/mcf523x/config.mk b/arch/m68k/cpu/mcf523x/config.mk
index 620769fb19..c9435ab99b 100644
--- a/arch/m68k/cpu/mcf523x/config.mk
+++ b/arch/m68k/cpu/mcf523x/config.mk
@@ -7,5 +7,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-PLATFORM_RELFLAGS += -ffixed-d7 -msep-data
 PLATFORM_CPPFLAGS += -mcpu=5235 -fPIC
diff --git a/arch/m68k/cpu/mcf52x2/Makefile b/arch/m68k/cpu/mcf52x2/Makefile
index 3a22aeebf1..b92fd864c4 100644
--- a/arch/m68k/cpu/mcf52x2/Makefile
+++ b/arch/m68k/cpu/mcf52x2/Makefile
@@ -5,29 +5,7 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
+# ccflags-y += -DET_DEBUG
 
-# CFLAGS += -DET_DEBUG
-
-LIB	= $(obj)lib$(CPU).o
-
-START	= start.o
-COBJS	= interrupts.o cpu.o speed.o cpu_init.o
-
-SRCS	:= $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS))
-START	:= $(addprefix $(obj),$(START))
-
-all:	$(obj).depend $(START) $(LIB)
-
-$(LIB):	$(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+extra-y	= start.o
+obj-y	= interrupts.o cpu.o speed.o cpu_init.o
diff --git a/arch/m68k/cpu/mcf52x2/config.mk b/arch/m68k/cpu/mcf52x2/config.mk
index d0be46fd9c..34ad99e92c 100644
--- a/arch/m68k/cpu/mcf52x2/config.mk
+++ b/arch/m68k/cpu/mcf52x2/config.mk
@@ -7,16 +7,14 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-PLATFORM_RELFLAGS += -ffixed-d7 -msep-data
-
-cfg=$(shell grep configs $(OBJTREE)/include/config.h | sed 's/.*<\(configs.*\)>/\1/')
-is5208:=$(shell grep CONFIG_M5208 $(TOPDIR)/include/$(cfg))
-is5249:=$(shell grep CONFIG_M5249 $(TOPDIR)/include/$(cfg))
-is5253:=$(shell grep CONFIG_M5253 $(TOPDIR)/include/$(cfg))
-is5271:=$(shell grep CONFIG_M5271 $(TOPDIR)/include/$(cfg))
-is5272:=$(shell grep CONFIG_M5272 $(TOPDIR)/include/$(cfg))
-is5275:=$(shell grep CONFIG_M5275 $(TOPDIR)/include/$(cfg))
-is5282:=$(shell grep CONFIG_M5282 $(TOPDIR)/include/$(cfg))
+cfg=$(shell grep configs $(objtree)/include/config.h | sed 's/.*<\(configs.*\)>/\1/')
+is5208:=$(shell grep CONFIG_M5208 $(srctree)/include/$(cfg))
+is5249:=$(shell grep CONFIG_M5249 $(srctree)/include/$(cfg))
+is5253:=$(shell grep CONFIG_M5253 $(srctree)/include/$(cfg))
+is5271:=$(shell grep CONFIG_M5271 $(srctree)/include/$(cfg))
+is5272:=$(shell grep CONFIG_M5272 $(srctree)/include/$(cfg))
+is5275:=$(shell grep CONFIG_M5275 $(srctree)/include/$(cfg))
+is5282:=$(shell grep CONFIG_M5282 $(srctree)/include/$(cfg))
 
 ifneq (,$(findstring CONFIG_M5208,$(is5208)))
 PLATFORM_CPPFLAGS += -mcpu=5208
diff --git a/arch/m68k/cpu/mcf532x/Makefile b/arch/m68k/cpu/mcf532x/Makefile
index 7d71dd9ca5..9c53c50c48 100644
--- a/arch/m68k/cpu/mcf532x/Makefile
+++ b/arch/m68k/cpu/mcf532x/Makefile
@@ -5,28 +5,7 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
+# ccflags-y += -DET_DEBUG
 
-# CFLAGS += -DET_DEBUG
-
-LIB	= $(obj)lib$(CPU).o
-
-START	=
-COBJS	= cpu.o speed.o cpu_init.o interrupts.o
-
-SRCS	:= $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS))
-START	:= $(addprefix $(obj),$(START))
-
-all:	$(obj).depend $(START) $(LIB)
-
-$(LIB):	$(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+extra-y := start.o
+obj-y	= cpu.o speed.o cpu_init.o interrupts.o
diff --git a/arch/m68k/cpu/mcf532x/config.mk b/arch/m68k/cpu/mcf532x/config.mk
index be1220365a..af943543a2 100644
--- a/arch/m68k/cpu/mcf532x/config.mk
+++ b/arch/m68k/cpu/mcf532x/config.mk
@@ -7,11 +7,9 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-PLATFORM_RELFLAGS += -ffixed-d7 -msep-data
-
-cfg=$(shell grep configs $(OBJTREE)/include/config.h | sed 's/.*<\(configs.*\)>/\1/')
-is5301x:=$(shell grep CONFIG_MCF5301x $(TOPDIR)/include/$(cfg))
-is532x:=$(shell grep CONFIG_MCF532x $(TOPDIR)/include/$(cfg))
+cfg=$(shell grep configs $(objtree)/include/config.h | sed 's/.*<\(configs.*\)>/\1/')
+is5301x:=$(shell grep CONFIG_MCF5301x $(srctree)/include/$(cfg))
+is532x:=$(shell grep CONFIG_MCF532x $(srctree)/include/$(cfg))
 
 ifneq (,$(findstring CONFIG_MCF5301x,$(is5301x)))
 PLATFORM_CPPFLAGS += -mcpu=53015 -fPIC
diff --git a/arch/m68k/cpu/mcf5445x/Makefile b/arch/m68k/cpu/mcf5445x/Makefile
index b76d0ed803..9be91ed157 100644
--- a/arch/m68k/cpu/mcf5445x/Makefile
+++ b/arch/m68k/cpu/mcf5445x/Makefile
@@ -5,28 +5,7 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
+# ccflags-y += -DET_DEBUG
 
-# CFLAGS += -DET_DEBUG
-
-LIB	= $(obj)lib$(CPU).o
-
-START	= start.o
-COBJS	= cpu.o speed.o cpu_init.o interrupts.o pci.o
-
-SRCS	:= $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS))
-START	:= $(addprefix $(obj),$(START))
-
-all:	$(obj).depend $(START) $(LIB)
-
-$(LIB):	$(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+extra-y	= start.o
+obj-y	= cpu.o speed.o cpu_init.o interrupts.o pci.o
diff --git a/arch/m68k/cpu/mcf5445x/config.mk b/arch/m68k/cpu/mcf5445x/config.mk
index d546b22058..5fd0d4d0e2 100644
--- a/arch/m68k/cpu/mcf5445x/config.mk
+++ b/arch/m68k/cpu/mcf5445x/config.mk
@@ -9,10 +9,8 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-PLATFORM_RELFLAGS += -ffixed-d7 -msep-data
-
-cfg=$(shell grep configs $(OBJTREE)/include/config.h | sed 's/.*<\(configs.*\)>/\1/')
-is5441x:=$(shell grep CONFIG_MCF5441x $(TOPDIR)/include/$(cfg))
+cfg=$(shell grep configs $(objtree)/include/config.h | sed 's/.*<\(configs.*\)>/\1/')
+is5441x:=$(shell grep CONFIG_MCF5441x $(srctree)/include/$(cfg))
 
 ifneq (,$(findstring CONFIG_MCF5441x,$(is5441x)))
 PLATFORM_CPPFLAGS += -mcpu=54418 -fPIC
diff --git a/arch/m68k/cpu/mcf547x_8x/Makefile b/arch/m68k/cpu/mcf547x_8x/Makefile
index 13d3c9bb3c..4f82099b6b 100644
--- a/arch/m68k/cpu/mcf547x_8x/Makefile
+++ b/arch/m68k/cpu/mcf547x_8x/Makefile
@@ -5,28 +5,7 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
+# ccflags-y += -DET_DEBUG
 
-# CFLAGS += -DET_DEBUG
-
-LIB	= $(obj)lib$(CPU).o
-
-START	=
-COBJS	= cpu.o speed.o cpu_init.o pci.o interrupts.o slicetimer.o
-
-SRCS	:= $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS))
-START	:= $(addprefix $(obj),$(START))
-
-all:	$(obj).depend $(START) $(LIB)
-
-$(LIB):	$(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+extra-y = start.o
+obj-y	= cpu.o speed.o cpu_init.o pci.o interrupts.o slicetimer.o
diff --git a/arch/m68k/cpu/mcf547x_8x/config.mk b/arch/m68k/cpu/mcf547x_8x/config.mk
index 345f5841ac..825f6ccebe 100644
--- a/arch/m68k/cpu/mcf547x_8x/config.mk
+++ b/arch/m68k/cpu/mcf547x_8x/config.mk
@@ -7,7 +7,6 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-PLATFORM_RELFLAGS += -ffixed-d7 -msep-data
 PLATFORM_CPPFLAGS += -mcpu=5485 -fPIC
 
 ifneq (,$(findstring -linux-,$(shell $(CC) --version)))
diff --git a/arch/m68k/include/asm/bitops.h b/arch/m68k/include/asm/bitops.h
index 525d90ccb0..f9c434b4a3 100644
--- a/arch/m68k/include/asm/bitops.h
+++ b/arch/m68k/include/asm/bitops.h
@@ -5,7 +5,6 @@
 #ifndef _M68K_BITOPS_H
 #define _M68K_BITOPS_H
 
-#include <linux/config.h>
 #include <asm/byteorder.h>
 
 extern void set_bit(int nr, volatile void *addr);
diff --git a/arch/m68k/lib/Makefile b/arch/m68k/lib/Makefile
index 48973fd87b..65867d6e47 100644
--- a/arch/m68k/lib/Makefile
+++ b/arch/m68k/lib/Makefile
@@ -5,30 +5,9 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(ARCH).o
-
-SOBJS-y	+=
-
-COBJS-y	+= board.o
-COBJS-$(CONFIG_CMD_BOOTM) += bootm.o
-COBJS-y	+= cache.o
-COBJS-y	+= interrupts.o
-COBJS-y	+= time.o
-COBJS-y	+= traps.o
-
-SRCS	:= $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
-OBJS	:= $(addprefix $(obj),$(SOBJS-y) $(COBJS-y))
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	+= board.o
+obj-$(CONFIG_CMD_BOOTM) += bootm.o
+obj-y	+= cache.o
+obj-y	+= interrupts.o
+obj-y	+= time.o
+obj-y	+= traps.o
diff --git a/arch/microblaze/config.mk b/arch/microblaze/config.mk
index fc545a9ee6..98bbf794fa 100644
--- a/arch/microblaze/config.mk
+++ b/arch/microblaze/config.mk
@@ -8,10 +8,10 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-CROSS_COMPILE ?= mb-
+ifeq ($(CROSS_COMPILE),)
+CROSS_COMPILE := mb-
+endif
 
 CONFIG_STANDALONE_LOAD_ADDR ?= 0x80F00000
 
 PLATFORM_CPPFLAGS += -ffixed-r31 -D__microblaze__
-
-LDSCRIPT ?= $(SRCTREE)/$(CPUDIR)/u-boot.lds
diff --git a/arch/microblaze/cpu/Makefile b/arch/microblaze/cpu/Makefile
index d0931f8495..4955e81236 100644
--- a/arch/microblaze/cpu/Makefile
+++ b/arch/microblaze/cpu/Makefile
@@ -5,28 +5,7 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(CPU).o
-
-START	= start.o
-SOBJS	= irq.o
-COBJS	= cpu.o interrupts.o cache.o exception.o timer.o
-
-SRCS	:= $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS))
-START	:= $(addprefix $(obj),$(START))
-
-all:	$(obj).depend $(START) $(LIB)
-
-$(LIB):	$(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+extra-y	= start.o
+obj-y	= irq.o
+obj-y	+= cpu.o interrupts.o cache.o exception.o timer.o
+obj-$(CONFIG_SPL_BUILD)	+= spl.o
diff --git a/arch/microblaze/cpu/exception.c b/arch/microblaze/cpu/exception.c
index 9218355ae1..227842f6a4 100644
--- a/arch/microblaze/cpu/exception.c
+++ b/arch/microblaze/cpu/exception.c
@@ -35,6 +35,9 @@ void _hw_exception_handler (void)
 		puts ("Divide by zero exception\n");
 		break;
 #ifdef MICROBLAZE_V5
+	case 0x7:
+		puts("Priviledged or stack protection violation exception\n");
+		break;
 	case 0x1000:
 		puts ("Exception in delay slot\n");
 		break;
diff --git a/arch/microblaze/cpu/spl.c b/arch/microblaze/cpu/spl.c
new file mode 100644
index 0000000000..091226133e
--- /dev/null
+++ b/arch/microblaze/cpu/spl.c
@@ -0,0 +1,55 @@
+/*
+ * (C) Copyright 2013 - 2014 Xilinx, Inc
+ *
+ * Michal Simek <michal.simek@xilinx.com>
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#include <common.h>
+#include <image.h>
+#include <spl.h>
+#include <version.h>
+#include <asm/io.h>
+#include <asm/u-boot.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+bool boot_linux;
+
+u32 spl_boot_device(void)
+{
+	return BOOT_DEVICE_NOR;
+}
+
+/* Board initialization after bss clearance */
+void spl_board_init(void)
+{
+	gd = (gd_t *)CONFIG_SPL_STACK_ADDR;
+
+	/* enable console uart printing */
+	preloader_console_init();
+}
+
+#ifdef CONFIG_SPL_OS_BOOT
+void __noreturn jump_to_image_linux(void *arg)
+{
+	debug("Entering kernel arg pointer: 0x%p\n", arg);
+	typedef void (*image_entry_arg_t)(char *, ulong, ulong)
+		__attribute__ ((noreturn));
+	image_entry_arg_t image_entry =
+		(image_entry_arg_t)spl_image.entry_point;
+
+	image_entry(NULL, 0, (ulong)arg);
+}
+#endif /* CONFIG_SPL_OS_BOOT */
+
+int spl_start_uboot(void)
+{
+#ifdef CONFIG_SPL_OS_BOOT
+	if (boot_linux)
+		return 0;
+#endif
+
+	return 1;
+}
diff --git a/arch/microblaze/cpu/start.S b/arch/microblaze/cpu/start.S
index 8928024838..1757bbfa94 100644
--- a/arch/microblaze/cpu/start.S
+++ b/arch/microblaze/cpu/start.S
@@ -22,6 +22,11 @@ _start:
 	 */
 
 	mts	rmsr, r0	/* disable cache */
+
+#if defined(CONFIG_SPL_BUILD)
+	addi	r1, r0, CONFIG_SPL_STACK_ADDR
+	addi	r1, r1, -4	/* Decrement SP to top of memory */
+#else
 	addi	r1, r0, CONFIG_SYS_INIT_SP_OFFSET
 	addi	r1, r1, -4	/* Decrement SP to top of memory */
 
@@ -115,6 +120,7 @@ _start:
 	sh	r7, r0, r8
 	rsubi	r8, r10, 0x26
 	sh	r6, r0, r8
+#endif /* BUILD_SPL */
 
 	/* Flush cache before enable cache */
 	addik	r5, r0, 0
@@ -139,9 +145,14 @@ clear_bss:
 	cmp     r6, r5, r4 /* check if we have reach the end */
 	bnei    r6, 2b
 3:	/* jumping to board_init */
+#ifndef CONFIG_SPL_BUILD
 	brai	board_init_f
+#else
+	brai	board_init_r
+#endif
 1:	bri	1b
 
+#ifndef CONFIG_SPL_BUILD
 /*
  * Read 16bit little endian
  */
@@ -174,3 +185,4 @@ out16:	bslli	r3, r6, 8
 	rtsd	r15, 8
 	or	r0, r0, r0
 	.end	out16
+#endif
diff --git a/arch/microblaze/cpu/timer.c b/arch/microblaze/cpu/timer.c
index 69ae6d4d87..3960bbb08a 100644
--- a/arch/microblaze/cpu/timer.c
+++ b/arch/microblaze/cpu/timer.c
@@ -34,6 +34,7 @@ void __udelay(unsigned long usec)
 	}
 }
 
+#ifndef CONFIG_SPL_BUILD
 static void timer_isr(void *arg)
 {
 	timestamp++;
@@ -62,10 +63,15 @@ int timer_init (void)
 		if (ret)
 			tmr = NULL;
 	}
-
 	/* No problem if timer is not found/initialized */
 	return 0;
 }
+#else
+int timer_init(void)
+{
+	return 0;
+}
+#endif
 
 /*
  * This function is derived from PowerPC code (read timebase as long long).
diff --git a/arch/microblaze/cpu/u-boot-spl.lds b/arch/microblaze/cpu/u-boot-spl.lds
new file mode 100644
index 0000000000..96353cd96c
--- /dev/null
+++ b/arch/microblaze/cpu/u-boot-spl.lds
@@ -0,0 +1,57 @@
+/*
+ * (C) Copyright 2013 - 2014 Xilinx, Inc
+ *
+ * Michal Simek <michal.simek@xilinx.com>
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#include <asm-offsets.h>
+
+OUTPUT_ARCH(microblaze)
+ENTRY(_start)
+
+SECTIONS
+{
+	.text ALIGN(0x4):
+	{
+		__text_start = .;
+		arch/microblaze/cpu/start.o (.text)
+		*(.text)
+		*(.text.*)
+		__text_end = .;
+	}
+
+	.rodata ALIGN(0x4):
+	{
+		__rodata_start = .;
+		*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
+		__rodata_end = .;
+	}
+
+	.data ALIGN(0x4):
+	{
+		__data_start = .;
+		*(.data)
+		*(.data.*)
+		__data_end = .;
+	}
+
+	.bss ALIGN(0x4):
+	{
+		__bss_start = .;
+		*(.sbss)
+		*(.scommon)
+		*(.bss)
+		*(.bss.*)
+		*(COMMON)
+		. = ALIGN(4);
+		__bss_end = .;
+	}
+	__end = . ;
+}
+
+#if defined(CONFIG_SPL_MAX_FOOTPRINT)
+ASSERT(__end - _start < (CONFIG_SPL_MAX_FOOTPRINT), \
+        "SPL image plus BSS too big");
+#endif
diff --git a/arch/microblaze/cpu/u-boot.lds b/arch/microblaze/cpu/u-boot.lds
index 3e6204de32..fdad20753d 100644
--- a/arch/microblaze/cpu/u-boot.lds
+++ b/arch/microblaze/cpu/u-boot.lds
@@ -30,7 +30,7 @@ SECTIONS
 	{
 		__data_start = .;
 #ifdef CONFIG_OF_EMBED
-		dts/libdts.o (.data)
+		dts/built-in.o (.data)
 #endif
 		*(.data)
 		__data_end = .;
diff --git a/arch/microblaze/dts/.gitignore b/arch/microblaze/dts/.gitignore
new file mode 100644
index 0000000000..b60ed208c7
--- /dev/null
+++ b/arch/microblaze/dts/.gitignore
@@ -0,0 +1 @@
+*.dtb
diff --git a/arch/microblaze/dts/Makefile b/arch/microblaze/dts/Makefile
new file mode 100644
index 0000000000..6d4a11f62f
--- /dev/null
+++ b/arch/microblaze/dts/Makefile
@@ -0,0 +1,11 @@
+dtb-y += microblaze-generic.dtb
+
+targets += $(dtb-y)
+
+DTC_FLAGS += -R 4 -p 0x1000
+
+PHONY += dtbs
+dtbs: $(addprefix $(obj)/, $(dtb-y))
+	@:
+
+clean-files := *.dtb
diff --git a/board/xilinx/dts/microblaze-generic.dts b/arch/microblaze/dts/microblaze-generic.dts
index 203330987b..203330987b 100644
--- a/board/xilinx/dts/microblaze-generic.dts
+++ b/arch/microblaze/dts/microblaze-generic.dts
diff --git a/arch/microblaze/include/asm/bitops.h b/arch/microblaze/include/asm/bitops.h
index eafa2b576b..0ac78d76f9 100644
--- a/arch/microblaze/include/asm/bitops.h
+++ b/arch/microblaze/include/asm/bitops.h
@@ -5,7 +5,6 @@
  * Copyright 1992, Linus Torvalds.
  */
 
-#include <linux/config.h>
 #include <asm/byteorder.h>	/* swab32 */
 #include <asm/system.h>		/* save_flags */
 
diff --git a/arch/microblaze/include/asm/spl.h b/arch/microblaze/include/asm/spl.h
new file mode 100644
index 0000000000..c1cae6cf0f
--- /dev/null
+++ b/arch/microblaze/include/asm/spl.h
@@ -0,0 +1,16 @@
+/*
+ * (C) Copyright 2013 - 2014 Xilinx, Inc
+ *
+ * Michal Simek <michal.simek@xilinx.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _ASM_MICROBLAZE_SPL_H_
+#define _ASM_MICROBLAZE_SPL_H_
+
+#define BOOT_DEVICE_RAM		1
+#define BOOT_DEVICE_NOR		2
+#define BOOT_DEVICE_SPI		3
+
+#endif
diff --git a/arch/microblaze/include/asm/u-boot.h b/arch/microblaze/include/asm/u-boot.h
index 31b014c77d..ab3f23202d 100644
--- a/arch/microblaze/include/asm/u-boot.h
+++ b/arch/microblaze/include/asm/u-boot.h
@@ -25,6 +25,7 @@ typedef struct bd_info {
 	unsigned long	bi_sramstart;	/* start of SRAM memory */
 	unsigned long	bi_sramsize;	/* size	 of SRAM memory */
 	unsigned int	bi_baudrate;	/* Console Baudrate */
+	ulong		bi_boot_params; /* where this board expects params */
 } bd_t;
 
 /* For image.h:image_check_target_arch() */
diff --git a/arch/microblaze/lib/Makefile b/arch/microblaze/lib/Makefile
index b86f980e16..339dd153a0 100644
--- a/arch/microblaze/lib/Makefile
+++ b/arch/microblaze/lib/Makefile
@@ -5,27 +5,6 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(ARCH).o
-
-SOBJS-y	+=
-
-COBJS-y	+= board.o
-COBJS-$(CONFIG_CMD_BOOTM) += bootm.o
-COBJS-y	+= muldi3.o
-
-SRCS	:= $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
-OBJS	:= $(addprefix $(obj),$(SOBJS-y) $(COBJS-y))
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	+= board.o
+obj-$(CONFIG_CMD_BOOTM) += bootm.o
+obj-y	+= muldi3.o
diff --git a/arch/microblaze/lib/board.c b/arch/microblaze/lib/board.c
index 896e73a762..fafeeaebd6 100644
--- a/arch/microblaze/lib/board.c
+++ b/arch/microblaze/lib/board.c
@@ -24,6 +24,12 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
+static int display_banner(void)
+{
+	printf("\n\n%s\n\n", version_string);
+	return 0;
+}
+
 /*
  * All attempts to come up with a "common" initialization sequence
  * that works for all boards and architectures failed: some of the
@@ -44,9 +50,14 @@ init_fnc_t *init_sequence[] = {
 	fdtdec_check_fdt,
 #endif
 	serial_init,
+#ifndef CONFIG_SPL_BUILD
 	console_init_f,
+#endif
+	display_banner,
+#ifndef CONFIG_SPL_BUILD
 	interrupts_init,
 	timer_init,
+#endif
 	NULL,
 };
 
@@ -59,7 +70,7 @@ void board_init_f(ulong not_used)
 	gd = (gd_t *)(CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_GBL_DATA_OFFSET);
 	bd = (bd_t *)(CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_GBL_DATA_OFFSET
 						- GENERATED_BD_INFO_SIZE);
-#if defined(CONFIG_CMD_FLASH)
+#if defined(CONFIG_CMD_FLASH) && !defined(CONFIG_SPL_BUILD)
 	ulong flash_size = 0;
 #endif
 	asm ("nop");	/* FIXME gd is not initialize - wait */
@@ -76,14 +87,17 @@ void board_init_f(ulong not_used)
 
 #ifdef CONFIG_OF_EMBED
 	/* Get a pointer to the FDT */
-	gd->fdt_blob = _binary_dt_dtb_start;
+	gd->fdt_blob = __dtb_dt_begin;
 #elif defined CONFIG_OF_SEPARATE
 	/* FDT is at end of image */
 	gd->fdt_blob = (void *)__end;
 #endif
+
+#ifndef CONFIG_SPL_BUILD
 	/* Allow the early environment to override the fdt address */
 	gd->fdt_blob = (void *)getenv_ulong("fdtcontroladdr", 16,
 						(uintptr_t)gd->fdt_blob);
+#endif
 
 	/*
 	 * The Malloc area is immediately below the monitor copy in DRAM
@@ -103,6 +117,7 @@ void board_init_f(ulong not_used)
 			hang();
 	}
 
+#ifndef CONFIG_SPL_BUILD
 #ifdef CONFIG_OF_CONTROL
 	/* For now, put this check after the console is ready */
 	if (fdtdec_prepare_fdt())
@@ -183,4 +198,5 @@ void board_init_f(ulong not_used)
 		WATCHDOG_RESET();
 		main_loop();
 	}
+#endif /* CONFIG_SPL_BUILD */
 }
diff --git a/arch/microblaze/lib/time.c b/arch/microblaze/lib/time.c
deleted file mode 100644
index e69de29bb2..0000000000
--- a/arch/microblaze/lib/time.c
+++ /dev/null
diff --git a/arch/mips/config.mk b/arch/mips/config.mk
index c3f81b5a18..1899f51872 100644
--- a/arch/mips/config.mk
+++ b/arch/mips/config.mk
@@ -5,7 +5,9 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-CROSS_COMPILE ?= mips_4KC-
+ifeq ($(CROSS_COMPILE),)
+CROSS_COMPILE := mips_4KC-
+endif
 
 # Handle special prefix in ELDK 4.0 toolchain
 ifneq (,$(findstring 4KCle,$(CROSS_COMPILE)))
@@ -50,4 +52,4 @@ PLATFORM_CPPFLAGS		+= -msoft-float
 PLATFORM_LDFLAGS		+= -G 0 -static -n -nostdlib $(ENDIANNESS)
 PLATFORM_RELFLAGS		+= -ffunction-sections -fdata-sections
 LDFLAGS_FINAL			+= --gc-sections -pie
-OBJCFLAGS			+= --remove-section=.dynsym
+OBJCOPYFLAGS			+= --remove-section=.dynsym
diff --git a/arch/mips/cpu/mips32/Makefile b/arch/mips/cpu/mips32/Makefile
index 1974034dfb..e0e6309c6f 100644
--- a/arch/mips/cpu/mips32/Makefile
+++ b/arch/mips/cpu/mips32/Makefile
@@ -5,28 +5,6 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(CPU).o
-
-START	= start.o
-SOBJS-y	= cache.o
-COBJS-y	= cpu.o interrupts.o time.o
-
-SRCS	:= $(START:.o=.S) $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
-OBJS	:= $(addprefix $(obj),$(SOBJS-y) $(COBJS-y))
-START	:= $(addprefix $(obj),$(START))
-
-all:	$(obj).depend $(START) $(LIB)
-
-$(LIB):	$(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+extra-y	= start.o
+obj-y	= cache.o
+obj-y	+= cpu.o interrupts.o time.o
diff --git a/arch/mips/cpu/mips32/au1x00/Makefile b/arch/mips/cpu/mips32/au1x00/Makefile
index 4a045e3a91..c5643e713b 100644
--- a/arch/mips/cpu/mips32/au1x00/Makefile
+++ b/arch/mips/cpu/mips32/au1x00/Makefile
@@ -5,25 +5,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(SOC).o
-
-COBJS	= au1x00_eth.o au1x00_serial.o au1x00_usb_ohci.o au1x00_ide.o
-
-SRCS	:= $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-
-all:	$(obj).depend $(LIB)
-
-$(LIB):	$(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	= au1x00_eth.o au1x00_serial.o au1x00_usb_ohci.o au1x00_ide.o
diff --git a/arch/mips/cpu/mips32/au1x00/au1x00_usb_ohci.c b/arch/mips/cpu/mips32/au1x00/au1x00_usb_ohci.c
index 931f95a0da..a3dac70798 100644
--- a/arch/mips/cpu/mips32/au1x00/au1x00_usb_ohci.c
+++ b/arch/mips/cpu/mips32/au1x00/au1x00_usb_ohci.c
@@ -839,104 +839,7 @@ static int dl_done_list (ohci_t *ohci, td_t *td_list)
  * Virtual Root Hub
  *-------------------------------------------------------------------------*/
 
-/* Device descriptor */
-static __u8 root_hub_dev_des[] =
-{
-	0x12,	    /*	__u8  bLength; */
-	0x01,	    /*	__u8  bDescriptorType; Device */
-	0x10,	    /*	__u16 bcdUSB; v1.1 */
-	0x01,
-	0x09,	    /*	__u8  bDeviceClass; HUB_CLASSCODE */
-	0x00,	    /*	__u8  bDeviceSubClass; */
-	0x00,	    /*	__u8  bDeviceProtocol; */
-	0x08,	    /*	__u8  bMaxPacketSize0; 8 Bytes */
-	0x00,	    /*	__u16 idVendor; */
-	0x00,
-	0x00,	    /*	__u16 idProduct; */
-	0x00,
-	0x00,	    /*	__u16 bcdDevice; */
-	0x00,
-	0x00,	    /*	__u8  iManufacturer; */
-	0x01,	    /*	__u8  iProduct; */
-	0x00,	    /*	__u8  iSerialNumber; */
-	0x01	    /*	__u8  bNumConfigurations; */
-};
-
-
-/* Configuration descriptor */
-static __u8 root_hub_config_des[] =
-{
-	0x09,	    /*	__u8  bLength; */
-	0x02,	    /*	__u8  bDescriptorType; Configuration */
-	0x19,	    /*	__u16 wTotalLength; */
-	0x00,
-	0x01,	    /*	__u8  bNumInterfaces; */
-	0x01,	    /*	__u8  bConfigurationValue; */
-	0x00,	    /*	__u8  iConfiguration; */
-	0x40,	    /*	__u8  bmAttributes;
-		 Bit 7: Bus-powered, 6: Self-powered, 5 Remote-wakwup, 4..0: resvd */
-	0x00,	    /*	__u8  MaxPower; */
-
-	/* interface */
-	0x09,	    /*	__u8  if_bLength; */
-	0x04,	    /*	__u8  if_bDescriptorType; Interface */
-	0x00,	    /*	__u8  if_bInterfaceNumber; */
-	0x00,	    /*	__u8  if_bAlternateSetting; */
-	0x01,	    /*	__u8  if_bNumEndpoints; */
-	0x09,	    /*	__u8  if_bInterfaceClass; HUB_CLASSCODE */
-	0x00,	    /*	__u8  if_bInterfaceSubClass; */
-	0x00,	    /*	__u8  if_bInterfaceProtocol; */
-	0x00,	    /*	__u8  if_iInterface; */
-
-	/* endpoint */
-	0x07,	    /*	__u8  ep_bLength; */
-	0x05,	    /*	__u8  ep_bDescriptorType; Endpoint */
-	0x81,	    /*	__u8  ep_bEndpointAddress; IN Endpoint 1 */
-	0x03,	    /*	__u8  ep_bmAttributes; Interrupt */
-	0x02,	    /*	__u16 ep_wMaxPacketSize; ((MAX_ROOT_PORTS + 1) / 8 */
-	0x00,
-	0xff	    /*	__u8  ep_bInterval; 255 ms */
-};
-
-static unsigned char root_hub_str_index0[] =
-{
-	0x04,			/*  __u8  bLength; */
-	0x03,			/*  __u8  bDescriptorType; String-descriptor */
-	0x09,			/*  __u8  lang ID */
-	0x04,			/*  __u8  lang ID */
-};
-
-static unsigned char root_hub_str_index1[] =
-{
-	28,			/*  __u8  bLength; */
-	0x03,			/*  __u8  bDescriptorType; String-descriptor */
-	'O',			/*  __u8  Unicode */
-	0,				/*  __u8  Unicode */
-	'H',			/*  __u8  Unicode */
-	0,				/*  __u8  Unicode */
-	'C',			/*  __u8  Unicode */
-	0,				/*  __u8  Unicode */
-	'I',			/*  __u8  Unicode */
-	0,				/*  __u8  Unicode */
-	' ',			/*  __u8  Unicode */
-	0,				/*  __u8  Unicode */
-	'R',			/*  __u8  Unicode */
-	0,				/*  __u8  Unicode */
-	'o',			/*  __u8  Unicode */
-	0,				/*  __u8  Unicode */
-	'o',			/*  __u8  Unicode */
-	0,				/*  __u8  Unicode */
-	't',			/*  __u8  Unicode */
-	0,				/*  __u8  Unicode */
-	' ',			/*  __u8  Unicode */
-	0,				/*  __u8  Unicode */
-	'H',			/*  __u8  Unicode */
-	0,				/*  __u8  Unicode */
-	'u',			/*  __u8  Unicode */
-	0,				/*  __u8  Unicode */
-	'b',			/*  __u8  Unicode */
-	0,				/*  __u8  Unicode */
-};
+#include <usbroothubdes.h>
 
 /* Hub class-specific descriptor is constructed dynamically */
 
@@ -1548,7 +1451,7 @@ static void hc_release_ohci (ohci_t *ohci)
  */
 static char ohci_inited = 0;
 
-int usb_lowlevel_init(int index, void **controller)
+int usb_lowlevel_init(int index, enum usb_init_type init, void **controller)
 {
 	u32 pin_func;
 	u32 sys_freqctrl, sys_clksrc;
diff --git a/arch/mips/cpu/mips32/cache.S b/arch/mips/cpu/mips32/cache.S
index 12f656cad0..22bd844eae 100644
--- a/arch/mips/cpu/mips32/cache.S
+++ b/arch/mips/cpu/mips32/cache.S
@@ -20,15 +20,6 @@
 
 #define RA		t9
 
-/*
- * 16kB is the maximum size of instruction and data caches on MIPS 4K,
- * 64kB is on 4KE, 24K, 5K, etc. Set bigger size for convenience.
- *
- * Note that the above size is the maximum size of primary cache. U-Boot
- * doesn't have L2 cache support for now.
- */
-#define MIPS_MAX_CACHE_SIZE	0x10000
-
 #define INDEX_BASE	CKSEG0
 
 	.macro	cache_op op addr
@@ -126,12 +117,85 @@ LEAF(mips_init_dcache)
  */
 NESTED(mips_cache_reset, 0, ra)
 	move	RA, ra
-	li	t2, CONFIG_SYS_ICACHE_SIZE
-	li	t3, CONFIG_SYS_DCACHE_SIZE
+
+#if !defined(CONFIG_SYS_ICACHE_SIZE) || !defined(CONFIG_SYS_DCACHE_SIZE) || \
+    !defined(CONFIG_SYS_CACHELINE_SIZE)
+	/* read Config1 for use below */
+	mfc0	t5, CP0_CONFIG, 1
+#endif
+
+#ifdef CONFIG_SYS_CACHELINE_SIZE
+	li	t7, CONFIG_SYS_CACHELINE_SIZE
 	li	t8, CONFIG_SYS_CACHELINE_SIZE
+#else
+	/* Detect I-cache line size. */
+	srl	t8, t5, MIPS_CONF1_IL_SHIFT
+	andi	t8, t8, (MIPS_CONF1_IL >> MIPS_CONF1_IL_SHIFT)
+	beqz	t8, 1f
+	li	t6, 2
+	sllv	t8, t6, t8
 
-	li	v0, MIPS_MAX_CACHE_SIZE
+1:	/* Detect D-cache line size. */
+	srl	t7, t5, MIPS_CONF1_DL_SHIFT
+	andi	t7, t7, (MIPS_CONF1_DL >> MIPS_CONF1_DL_SHIFT)
+	beqz	t7, 1f
+	li	t6, 2
+	sllv	t7, t6, t7
+1:
+#endif
 
+#ifdef CONFIG_SYS_ICACHE_SIZE
+	li	t2, CONFIG_SYS_ICACHE_SIZE
+#else
+	/* Detect I-cache size. */
+	srl	t6, t5, MIPS_CONF1_IS_SHIFT
+	andi	t6, t6, (MIPS_CONF1_IS >> MIPS_CONF1_IS_SHIFT)
+	li	t4, 32
+	xori	t2, t6, 0x7
+	beqz	t2, 1f
+	addi	t6, t6, 1
+	sllv	t4, t4, t6
+1:	/* At this point t4 == I-cache sets. */
+	mul	t2, t4, t8
+	srl	t6, t5, MIPS_CONF1_IA_SHIFT
+	andi	t6, t6, (MIPS_CONF1_IA >> MIPS_CONF1_IA_SHIFT)
+	addi	t6, t6, 1
+	/* At this point t6 == I-cache ways. */
+	mul	t2, t2, t6
+#endif
+
+#ifdef CONFIG_SYS_DCACHE_SIZE
+	li	t3, CONFIG_SYS_DCACHE_SIZE
+#else
+	/* Detect D-cache size. */
+	srl	t6, t5, MIPS_CONF1_DS_SHIFT
+	andi	t6, t6, (MIPS_CONF1_DS >> MIPS_CONF1_DS_SHIFT)
+	li	t4, 32
+	xori	t3, t6, 0x7
+	beqz	t3, 1f
+	addi	t6, t6, 1
+	sllv	t4, t4, t6
+1:	/* At this point t4 == I-cache sets. */
+	mul	t3, t4, t7
+	srl	t6, t5, MIPS_CONF1_DA_SHIFT
+	andi	t6, t6, (MIPS_CONF1_DA >> MIPS_CONF1_DA_SHIFT)
+	addi	t6, t6, 1
+	/* At this point t6 == I-cache ways. */
+	mul	t3, t3, t6
+#endif
+
+	/* Determine the largest L1 cache size */
+#if defined(CONFIG_SYS_ICACHE_SIZE) && defined(CONFIG_SYS_DCACHE_SIZE)
+#if CONFIG_SYS_ICACHE_SIZE > CONFIG_SYS_DCACHE_SIZE
+	li	v0, CONFIG_SYS_ICACHE_SIZE
+#else
+	li	v0, CONFIG_SYS_DCACHE_SIZE
+#endif
+#else
+	move	v0, t2
+	sltu	t1, t2, t3
+	movn	v0, t3, t1
+#endif
 	/*
 	 * Now clear that much memory starting from zero.
 	 */
@@ -163,7 +227,7 @@ NESTED(mips_cache_reset, 0, ra)
 	 * then initialize D-cache.
 	 */
 	move	a1, t3
-	move	a2, t8
+	move	a2, t7
 	PTR_LA	v1, mips_init_dcache
 	jalr	v1
 
diff --git a/arch/mips/cpu/mips32/config.mk b/arch/mips/cpu/mips32/config.mk
index 067f871525..332cd62c74 100644
--- a/arch/mips/cpu/mips32/config.mk
+++ b/arch/mips/cpu/mips32/config.mk
@@ -11,9 +11,7 @@
 # Note: Toolchains with binutils prior to v2.16
 # are no longer supported by U-Boot MIPS tree!
 #
-MIPSFLAGS := -march=mips32r2
-
-PLATFORM_CPPFLAGS += $(MIPSFLAGS)
+PLATFORM_CPPFLAGS += -DCONFIG_MIPS32 -march=mips32r2
 PLATFORM_CPPFLAGS += -mabi=32 -DCONFIG_32BIT
 ifdef CONFIG_SYS_BIG_ENDIAN
 PLATFORM_LDFLAGS  += -m elf32btsmip
@@ -21,4 +19,5 @@ else
 PLATFORM_LDFLAGS  += -m elf32ltsmip
 endif
 
-CONFIG_STANDALONE_LOAD_ADDR ?= 0x80200000 -T mips.lds
+CONFIG_STANDALONE_LOAD_ADDR ?= 0x80200000 \
+			       -T $(srctree)/examples/standalone/mips.lds
diff --git a/arch/mips/cpu/mips32/cpu.c b/arch/mips/cpu/mips32/cpu.c
index 28d5c45683..278865b6ff 100644
--- a/arch/mips/cpu/mips32/cpu.c
+++ b/arch/mips/cpu/mips32/cpu.c
@@ -34,28 +34,89 @@ int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 	return 0;
 }
 
+#ifdef CONFIG_SYS_CACHELINE_SIZE
+
+static inline unsigned long icache_line_size(void)
+{
+	return CONFIG_SYS_CACHELINE_SIZE;
+}
+
+static inline unsigned long dcache_line_size(void)
+{
+	return CONFIG_SYS_CACHELINE_SIZE;
+}
+
+#else /* !CONFIG_SYS_CACHELINE_SIZE */
+
+static inline unsigned long icache_line_size(void)
+{
+	unsigned long conf1, il;
+	conf1 = read_c0_config1();
+	il = (conf1 & MIPS_CONF1_IL) >> MIPS_CONF1_IL_SHIFT;
+	if (!il)
+		return 0;
+	return 2 << il;
+}
+
+static inline unsigned long dcache_line_size(void)
+{
+	unsigned long conf1, dl;
+	conf1 = read_c0_config1();
+	dl = (conf1 & MIPS_CONF1_DL) >> MIPS_CONF1_DL_SHIFT;
+	if (!dl)
+		return 0;
+	return 2 << dl;
+}
+
+#endif /* !CONFIG_SYS_CACHELINE_SIZE */
+
 void flush_cache(ulong start_addr, ulong size)
 {
-	unsigned long lsize = CONFIG_SYS_CACHELINE_SIZE;
-	unsigned long addr = start_addr & ~(lsize - 1);
-	unsigned long aend = (start_addr + size - 1) & ~(lsize - 1);
+	unsigned long ilsize = icache_line_size();
+	unsigned long dlsize = dcache_line_size();
+	unsigned long addr, aend;
 
 	/* aend will be miscalculated when size is zero, so we return here */
 	if (size == 0)
 		return;
 
+	addr = start_addr & ~(dlsize - 1);
+	aend = (start_addr + size - 1) & ~(dlsize - 1);
+
+	if (ilsize == dlsize) {
+		/* flush I-cache & D-cache simultaneously */
+		while (1) {
+			cache_op(HIT_WRITEBACK_INV_D, addr);
+			cache_op(HIT_INVALIDATE_I, addr);
+			if (addr == aend)
+				break;
+			addr += dlsize;
+		}
+		return;
+	}
+
+	/* flush D-cache */
 	while (1) {
 		cache_op(HIT_WRITEBACK_INV_D, addr);
+		if (addr == aend)
+			break;
+		addr += dlsize;
+	}
+
+	/* flush I-cache */
+	addr = start_addr & ~(ilsize - 1);
+	aend = (start_addr + size - 1) & ~(ilsize - 1);
+	while (1) {
 		cache_op(HIT_INVALIDATE_I, addr);
 		if (addr == aend)
 			break;
-		addr += lsize;
+		addr += ilsize;
 	}
 }
 
 void flush_dcache_range(ulong start_addr, ulong stop)
 {
-	unsigned long lsize = CONFIG_SYS_CACHELINE_SIZE;
+	unsigned long lsize = dcache_line_size();
 	unsigned long addr = start_addr & ~(lsize - 1);
 	unsigned long aend = (stop - 1) & ~(lsize - 1);
 
@@ -69,7 +130,7 @@ void flush_dcache_range(ulong start_addr, ulong stop)
 
 void invalidate_dcache_range(ulong start_addr, ulong stop)
 {
-	unsigned long lsize = CONFIG_SYS_CACHELINE_SIZE;
+	unsigned long lsize = dcache_line_size();
 	unsigned long addr = start_addr & ~(lsize - 1);
 	unsigned long aend = (stop - 1) & ~(lsize - 1);
 
diff --git a/arch/mips/cpu/mips32/incaip/Makefile b/arch/mips/cpu/mips32/incaip/Makefile
index 6368d57a88..7341a4a3e8 100644
--- a/arch/mips/cpu/mips32/incaip/Makefile
+++ b/arch/mips/cpu/mips32/incaip/Makefile
@@ -5,26 +5,5 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(SOC).o
-
-SOBJS	= incaip_wdt.o
-COBJS	= incaip_clock.o asc_serial.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS))
-
-all:	$(obj).depend $(LIB)
-
-$(LIB):	$(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	= incaip_wdt.o
+obj-y	+= incaip_clock.o asc_serial.o
diff --git a/arch/mips/cpu/mips32/start.S b/arch/mips/cpu/mips32/start.S
index 70ad198cc9..68e59b596f 100644
--- a/arch/mips/cpu/mips32/start.S
+++ b/arch/mips/cpu/mips32/start.S
@@ -51,7 +51,7 @@ _start:
 	 */
 	.word CONFIG_SYS_XWAY_EBU_BOOTCFG
 	.word 0x0
-#elif defined(CONFIG_QEMU_MALTA)
+#elif defined(CONFIG_MALTA)
 	/*
 	 * Linux expects the Board ID here.
 	 */
diff --git a/arch/mips/cpu/mips64/Makefile b/arch/mips/cpu/mips64/Makefile
index b4adb950a2..899c319c9a 100644
--- a/arch/mips/cpu/mips64/Makefile
+++ b/arch/mips/cpu/mips64/Makefile
@@ -5,25 +5,5 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(CPU).o
-
-START	= start.o
-COBJS-y	= cpu.o interrupts.o time.o cache.o
-
-SRCS	:= $(START:.o=.S) $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
-OBJS	:= $(addprefix $(obj),$(SOBJS-y) $(COBJS-y))
-START	:= $(addprefix $(obj),$(START))
-
-all:	$(obj).depend $(START) $(LIB)
-
-$(LIB):	$(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
+extra-y	= start.o
+obj-y	= cpu.o interrupts.o time.o cache.o
diff --git a/arch/mips/cpu/mips64/config.mk b/arch/mips/cpu/mips64/config.mk
index d1a8b2c7aa..c55eb7f2ee 100644
--- a/arch/mips/cpu/mips64/config.mk
+++ b/arch/mips/cpu/mips64/config.mk
@@ -11,9 +11,7 @@
 # Note: Toolchains with binutils prior to v2.16
 # are no longer supported by U-Boot MIPS tree!
 #
-MIPSFLAGS = -march=mips64
-
-PLATFORM_CPPFLAGS += $(MIPSFLAGS)
+PLATFORM_CPPFLAGS += -DCONFIG_MIPS64 -march=mips64
 PLATFORM_CPPFLAGS += -mabi=64 -DCONFIG_64BIT
 ifdef CONFIG_SYS_BIG_ENDIAN
 PLATFORM_LDFLAGS  += -m elf64btsmip
@@ -21,4 +19,5 @@ else
 PLATFORM_LDFLAGS  += -m elf64ltsmip
 endif
 
-CONFIG_STANDALONE_LOAD_ADDR ?= 0xffffffff80200000 -T mips64.lds
+CONFIG_STANDALONE_LOAD_ADDR ?= 0xffffffff80200000 \
+			       -T $(srctree)/examples/standalone/mips64.lds
diff --git a/arch/mips/cpu/xburst/Makefile b/arch/mips/cpu/xburst/Makefile
index bf58e046b1..57714d0c95 100644
--- a/arch/mips/cpu/xburst/Makefile
+++ b/arch/mips/cpu/xburst/Makefile
@@ -4,30 +4,6 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(CPU).o
-
-START	= start.o
-SOBJS-y	=
-COBJS-y	= cpu.o timer.o jz_serial.o
-
-COBJS-$(CONFIG_JZ4740) += jz4740.o
-
-SRCS	:= $(START:.o=.S) $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
-OBJS	:= $(addprefix $(obj),$(SOBJS-y) $(COBJS-y))
-START	:= $(addprefix $(obj),$(START))
-
-all:	$(obj).depend $(START) $(LIB)
-
-$(LIB):	$(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+extra-y	= start.o
+obj-y	= cpu.o timer.o jz_serial.o
+obj-$(CONFIG_JZ4740) += jz4740.o
diff --git a/arch/mips/cpu/xburst/config.mk b/arch/mips/cpu/xburst/config.mk
index d81da21017..b8e53e55c0 100644
--- a/arch/mips/cpu/xburst/config.mk
+++ b/arch/mips/cpu/xburst/config.mk
@@ -12,4 +12,5 @@ else
 PLATFORM_LDFLAGS  += -m elf32ltsmip
 endif
 
-CONFIG_STANDALONE_LOAD_ADDR ?= 0x80200000 -T mips.lds
+CONFIG_STANDALONE_LOAD_ADDR ?= 0x80200000 \
+			       -T $(srctree)/examples/standalone/mips.lds
diff --git a/arch/mips/include/asm/bitops.h b/arch/mips/include/asm/bitops.h
index f2dc533569..b5c2a6367d 100644
--- a/arch/mips/include/asm/bitops.h
+++ b/arch/mips/include/asm/bitops.h
@@ -16,7 +16,6 @@
 
 #include <asm/sgidefs.h>
 #include <asm/system.h>
-#include <linux/config.h>
 
 /*
  * clear_bit() doesn't provide any barrier for the compiler.
diff --git a/arch/mips/include/asm/inca-ip.h b/arch/mips/include/asm/inca-ip.h
index 26f100290c..5f03e2aa20 100644
--- a/arch/mips/include/asm/inca-ip.h
+++ b/arch/mips/include/asm/inca-ip.h
@@ -1,4 +1,3 @@
-
 /******************************************************************************
        Copyright (c) 2002, Infineon Technologies.  All rights reserved.
 
diff --git a/arch/mips/include/asm/io.h b/arch/mips/include/asm/io.h
index 50a882ca5a..3fa37f5dd2 100644
--- a/arch/mips/include/asm/io.h
+++ b/arch/mips/include/asm/io.h
@@ -11,7 +11,6 @@
 #ifndef _ASM_IO_H
 #define _ASM_IO_H
 
-#include <linux/config.h>
 #if 0
 #include <linux/pagemap.h>
 #endif
diff --git a/arch/mips/include/asm/malta.h b/arch/mips/include/asm/malta.h
index d4d44a299f..9e7c045aac 100644
--- a/arch/mips/include/asm/malta.h
+++ b/arch/mips/include/asm/malta.h
@@ -1,23 +1,67 @@
 /*
  * Copyright (C) 2013 Gabor Juhos <juhosg@openwrt.org>
+ * Copyright (C) 2013 Imagination Technologies
  *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
+ * SPDX-License-Identifier:	GPL-2.0
  */
 
 #ifndef _MIPS_ASM_MALTA_H
 #define _MIPS_ASM_MALTA_H
 
-#define MALTA_IO_PORT_BASE	0x18000000
+#define MALTA_GT_BASE			0x1be00000
+#define MALTA_GT_PCIIO_BASE		0x18000000
+#define MALTA_GT_UART0_BASE		(MALTA_GT_PCIIO_BASE + 0x3f8)
 
-#define MALTA_UART_BASE		(MALTA_IO_PORT_BASE + 0x3f8)
+#define MALTA_MSC01_BIU_BASE		0x1bc80000
+#define MALTA_MSC01_PCI_BASE		0x1bd00000
+#define MALTA_MSC01_PBC_BASE		0x1bd40000
+#define MALTA_MSC01_IP1_BASE		0x1bc00000
+#define MALTA_MSC01_IP1_SIZE		0x00400000
+#define MALTA_MSC01_IP2_BASE1		0x10000000
+#define MALTA_MSC01_IP2_SIZE1		0x08000000
+#define MALTA_MSC01_IP2_BASE2		0x18000000
+#define MALTA_MSC01_IP2_SIZE2		0x04000000
+#define MALTA_MSC01_IP3_BASE		0x1c000000
+#define MALTA_MSC01_IP3_SIZE		0x04000000
+#define MALTA_MSC01_PCIMEM_BASE		0x10000000
+#define MALTA_MSC01_PCIMEM_SIZE		0x10000000
+#define MALTA_MSC01_PCIMEM_MAP		0x10000000
+#define MALTA_MSC01_PCIIO_BASE		0x1b000000
+#define MALTA_MSC01_PCIIO_SIZE		0x00800000
+#define MALTA_MSC01_PCIIO_MAP		0x00000000
+#define MALTA_MSC01_UART0_BASE		(MALTA_MSC01_PCIIO_BASE + 0x3f8)
 
-#define MALTA_GT_BASE		0x1be00000
+#define MALTA_ASCIIWORD			0x1f000410
+#define MALTA_ASCIIPOS0			0x1f000418
+#define MALTA_ASCIIPOS1			0x1f000420
+#define MALTA_ASCIIPOS2			0x1f000428
+#define MALTA_ASCIIPOS3			0x1f000430
+#define MALTA_ASCIIPOS4			0x1f000438
+#define MALTA_ASCIIPOS5			0x1f000440
+#define MALTA_ASCIIPOS6			0x1f000448
+#define MALTA_ASCIIPOS7			0x1f000450
 
-#define MALTA_RESET_BASE	0x1f000500
-#define GORESET			0x42
+#define MALTA_RESET_BASE		0x1f000500
+#define GORESET				0x42
 
-#define MALTA_FLASH_BASE	0x1fc00000
+#define MALTA_FLASH_BASE		0x1e000000
+
+#define MALTA_REVISION			0x1fc00010
+#define MALTA_REVISION_CORID_SHF	10
+#define MALTA_REVISION_CORID_MSK	(0x3f << MALTA_REVISION_CORID_SHF)
+#define MALTA_REVISION_CORID_CORE_LV		1
+#define MALTA_REVISION_CORID_CORE_FPGA6		14
+
+#define PCI_CFG_PIIX4_PIRQRCA		0x60
+#define PCI_CFG_PIIX4_PIRQRCB		0x61
+#define PCI_CFG_PIIX4_PIRQRCC		0x62
+#define PCI_CFG_PIIX4_PIRQRCD		0x63
+#define PCI_CFG_PIIX4_SERIRQC		0x64
+#define PCI_CFG_PIIX4_GENCFG		0xb0
+
+#define PCI_CFG_PIIX4_SERIRQC_EN	(1 << 7)
+#define PCI_CFG_PIIX4_SERIRQC_CONT	(1 << 6)
+
+#define PCI_CFG_PIIX4_GENCFG_SERIRQ	(1 << 16)
 
 #endif /* _MIPS_ASM_MALTA_H */
diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h
index be7e5c65ec..3571e4fdf2 100644
--- a/arch/mips/include/asm/mipsregs.h
+++ b/arch/mips/include/asm/mipsregs.h
@@ -494,11 +494,17 @@
 #define MIPS_CONF1_PC		(_ULCAST_(1) <<  4)
 #define MIPS_CONF1_MD		(_ULCAST_(1) <<  5)
 #define MIPS_CONF1_C2		(_ULCAST_(1) <<  6)
+#define MIPS_CONF1_DA_SHIFT	7
 #define MIPS_CONF1_DA		(_ULCAST_(7) <<  7)
+#define MIPS_CONF1_DL_SHIFT	10
 #define MIPS_CONF1_DL		(_ULCAST_(7) << 10)
+#define MIPS_CONF1_DS_SHIFT	13
 #define MIPS_CONF1_DS		(_ULCAST_(7) << 13)
+#define MIPS_CONF1_IA_SHIFT	16
 #define MIPS_CONF1_IA		(_ULCAST_(7) << 16)
+#define MIPS_CONF1_IL_SHIFT	19
 #define MIPS_CONF1_IL		(_ULCAST_(7) << 19)
+#define MIPS_CONF1_IS_SHIFT	22
 #define MIPS_CONF1_IS		(_ULCAST_(7) << 22)
 #define MIPS_CONF1_TLBS		(_ULCAST_(63)<< 25)
 
diff --git a/arch/mips/include/asm/processor.h b/arch/mips/include/asm/processor.h
index 24858ddda5..ba7f5381a3 100644
--- a/arch/mips/include/asm/processor.h
+++ b/arch/mips/include/asm/processor.h
@@ -11,8 +11,6 @@
 #ifndef _ASM_PROCESSOR_H
 #define _ASM_PROCESSOR_H
 
-#include <linux/config.h>
-
 #include <asm/isadep.h>
 
 #include <asm/cachectl.h>
diff --git a/arch/mips/include/asm/system.h b/arch/mips/include/asm/system.h
index b6d50e2f04..7a2895284e 100644
--- a/arch/mips/include/asm/system.h
+++ b/arch/mips/include/asm/system.h
@@ -16,7 +16,6 @@
 #ifndef _ASM_SYSTEM_H
 #define _ASM_SYSTEM_H
 
-#include <linux/config.h>
 #include <asm/sgidefs.h>
 #include <asm/ptrace.h>
 #if 0
diff --git a/arch/mips/include/asm/types.h b/arch/mips/include/asm/types.h
index d4bb85999b..aebafdbba1 100644
--- a/arch/mips/include/asm/types.h
+++ b/arch/mips/include/asm/types.h
@@ -27,18 +27,12 @@ typedef unsigned short __u16;
 typedef __signed__ int __s32;
 typedef unsigned int __u32;
 
-#if (_MIPS_SZLONG == 64)
-
-typedef __signed__ long __s64;
-typedef unsigned long __u64;
-
-#else
-
 #if defined(__GNUC__)
 __extension__ typedef __signed__ long long __s64;
 __extension__ typedef unsigned long long __u64;
-#endif
-
+#else
+typedef __signed__ long long __s64;
+typedef unsigned long long __u64;
 #endif
 
 #endif /* __ASSEMBLY__ */
@@ -61,19 +55,8 @@ typedef unsigned short u16;
 typedef __signed int s32;
 typedef unsigned int u32;
 
-#if (_MIPS_SZLONG == 64)
-
-typedef __signed__ long s64;
-typedef unsigned long u64;
-
-#else
-
-#if defined(__GNUC__) && !defined(__STRICT_ANSI__)
 typedef __signed__ long long s64;
 typedef unsigned long long u64;
-#endif
-
-#endif
 
 #if (defined(CONFIG_HIGHMEM) && defined(CONFIG_64BIT_PHYS_ADDR)) \
     || defined(CONFIG_64BIT)
diff --git a/arch/mips/lib/Makefile b/arch/mips/lib/Makefile
index f91406c060..fabeb83f7e 100644
--- a/arch/mips/lib/Makefile
+++ b/arch/mips/lib/Makefile
@@ -5,46 +5,7 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
+obj-y	+= board.o
+obj-$(CONFIG_CMD_BOOTM) += bootm.o
 
-LIB	= $(obj)lib$(ARCH).o
-
-## Build a couple of necessary functions into a private libgcc
-LIBGCC	= $(obj)libgcc.o
-GLSOBJS	+= ashldi3.o
-GLSOBJS	+= ashrdi3.o
-GLSOBJS	+= lshrdi3.o
-LGOBJS	:= $(addprefix $(obj),$(GLSOBJS))
-
-SOBJS-y	+=
-
-COBJS-y	+= board.o
-COBJS-$(CONFIG_CMD_BOOTM) += bootm.o
-
-SRCS	:= $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
-OBJS	:= $(addprefix $(obj),$(SOBJS-y) $(COBJS-y))
-
-# Always build libmips.o
-TARGETS	:= $(LIB)
-
-# Build private libgcc only when asked for
-ifdef USE_PRIVATE_LIBGCC
-TARGETS	+= $(LIBGCC)
-endif
-
-all:	$(TARGETS)
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-$(LIBGCC): $(obj).depend $(LGOBJS)
-	$(call cmd_link_o_target, $(LGOBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+lib-$(CONFIG_USE_PRIVATE_LIBGCC) += ashldi3.o ashrdi3.o lshrdi3.o
diff --git a/arch/mips/lib/bootm.c b/arch/mips/lib/bootm.c
index 66340ea470..71bb0d2a19 100644
--- a/arch/mips/lib/bootm.c
+++ b/arch/mips/lib/bootm.c
@@ -17,10 +17,10 @@ DECLARE_GLOBAL_DATA_PTR;
 #define	LINUX_MAX_ENVS		256
 #define	LINUX_MAX_ARGS		256
 
-#if defined(CONFIG_QEMU_MALTA)
-#define mips_boot_qemu_malta	1
+#if defined(CONFIG_MALTA)
+#define mips_boot_malta		1
 #else
-#define mips_boot_qemu_malta	0
+#define mips_boot_malta		0
 #endif
 
 static int linux_argc;
@@ -139,7 +139,7 @@ static void linux_env_set(const char *env_name, const char *env_val)
 		strcpy(linux_env_p, env_name);
 		linux_env_p += strlen(env_name);
 
-		if (mips_boot_qemu_malta) {
+		if (mips_boot_malta) {
 			linux_env_p++;
 			linux_env[++linux_env_idx] = linux_env_p;
 		} else {
@@ -196,8 +196,10 @@ static void boot_prep_linux(bootm_headers_t *images)
 	if (cp)
 		linux_env_set("eth1addr", cp);
 
-	if (mips_boot_qemu_malta)
-		linux_env_set("modetty0", "38400n8r");
+	if (mips_boot_malta) {
+		sprintf(env_buf, "%un8r", gd->baudrate);
+		linux_env_set("modetty0", env_buf);
+	}
 }
 
 static void boot_jump_linux(bootm_headers_t *images)
@@ -210,7 +212,7 @@ static void boot_jump_linux(bootm_headers_t *images)
 
 	bootstage_mark(BOOTSTAGE_ID_RUN_OS);
 
-	if (mips_boot_qemu_malta)
+	if (mips_boot_malta)
 		linux_extra = gd->ram_size;
 
 	/* we assume that the kernel is in place */
diff --git a/arch/nds32/config.mk b/arch/nds32/config.mk
index e93e3a8c28..10248524d1 100644
--- a/arch/nds32/config.mk
+++ b/arch/nds32/config.mk
@@ -8,9 +8,12 @@
 #
 # SPDX-License-Identifier:	GPL-2.0+
 
-CROSS_COMPILE ?= nds32le-linux-
+ifeq ($(CROSS_COMPILE),)
+CROSS_COMPILE := nds32le-linux-
+endif
 
-CONFIG_STANDALONE_LOAD_ADDR = 0x300000 -T nds32.lds
+CONFIG_STANDALONE_LOAD_ADDR = 0x300000 \
+			      -T $(srctree)/examples/standalone/nds32.lds
 
 PLATFORM_RELFLAGS	+= -fno-strict-aliasing -fno-common -mrelax
 PLATFORM_RELFLAGS	+= -gdwarf-2
diff --git a/arch/nds32/cpu/n1213/Makefile b/arch/nds32/cpu/n1213/Makefile
index b8e0d72739..206d304d4c 100644
--- a/arch/nds32/cpu/n1213/Makefile
+++ b/arch/nds32/cpu/n1213/Makefile
@@ -9,26 +9,7 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
+# necessary to create built-in.o
+obj- := __dummy__.o
 
-LIB	= $(obj)lib$(CPU).o
-
-START	= start.o
-
-SRCS	:= $(START:.o=.S) $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS-y) $(SOBJS-y))
-START	:= $(addprefix $(obj),$(START))
-
-all:	$(obj).depend $(START) $(LIB)
-
-$(LIB):	$(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+extra-y	= start.o
diff --git a/arch/nds32/cpu/n1213/ag101/Makefile b/arch/nds32/cpu/n1213/ag101/Makefile
index b53a3eb5f4..c21ce02828 100644
--- a/arch/nds32/cpu/n1213/ag101/Makefile
+++ b/arch/nds32/cpu/n1213/ag101/Makefile
@@ -10,33 +10,12 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(SOC).o
-
-COBJS-y	:= cpu.o timer.o
+obj-y	:= cpu.o timer.o
 
 ifndef CONFIG_SKIP_LOWLEVEL_INIT
-SOBJS-y	:= lowlevel_init.o
+obj-y	+= lowlevel_init.o
 endif
 
 ifndef CONFIG_SKIP_TRUNOFF_WATCHDOG
-SOBJS-y	+= watchdog.o
+obj-y	+= watchdog.o
 endif
-
-SRCS	:= $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
-OBJS	:= $(addprefix $(obj),$(SOBJS-y) $(COBJS-y))
-
-all:	$(obj).depend $(LIB)
-
-$(LIB):	$(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
diff --git a/arch/nds32/cpu/n1213/ag101/asm-offsets.c b/arch/nds32/cpu/n1213/ag101/asm-offsets.c
deleted file mode 100644
index 92ada8ac28..0000000000
--- a/arch/nds32/cpu/n1213/ag101/asm-offsets.c
+++ /dev/null
@@ -1,43 +0,0 @@
-/*
- * Adapted from Linux v2.6.36 kernel: arch/powerpc/kernel/asm-offsets.c
- *
- * Generate definitions needed by assembly language modules.
- * This code generates raw asm output which is post-processed to extract
- * and format the required data.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-#include <common.h>
-
-#include <linux/kbuild.h>
-
-int main(void)
-{
-#ifdef CONFIG_FTSMC020
-	OFFSET(FTSMC020_BANK0_CR,	ftsmc020, bank[0].cr);
-	OFFSET(FTSMC020_BANK0_TPR,	ftsmc020, bank[0].tpr);
-#endif
-	BLANK();
-#ifdef CONFIG_FTAHBC020S
-	OFFSET(FTAHBC020S_SLAVE_BSR_6,	ftahbc02s, s_bsr[6]);
-	OFFSET(FTAHBC020S_CR,		ftahbc02s, cr);
-#endif
-	BLANK();
-#ifdef CONFIG_FTPMU010
-	OFFSET(FTPMU010_PDLLCR0,	ftpmu010, PDLLCR0);
-#endif
-	BLANK();
-#ifdef CONFIG_FTSDMC021
-	OFFSET(FTSDMC021_TP1,		ftsdmc021, tp1);
-	OFFSET(FTSDMC021_TP2,		ftsdmc021, tp2);
-	OFFSET(FTSDMC021_CR1,		ftsdmc021, cr1);
-	OFFSET(FTSDMC021_CR2,		ftsdmc021, cr2);
-	OFFSET(FTSDMC021_BANK0_BSR,	ftsdmc021, bank0_bsr);
-	OFFSET(FTSDMC021_BANK1_BSR,	ftsdmc021, bank1_bsr);
-	OFFSET(FTSDMC021_BANK2_BSR,	ftsdmc021, bank2_bsr);
-	OFFSET(FTSDMC021_BANK3_BSR,	ftsdmc021, bank3_bsr);
-#endif
-	return 0;
-}
diff --git a/arch/nds32/cpu/n1213/ag101/lowlevel_init.S b/arch/nds32/cpu/n1213/ag101/lowlevel_init.S
index 810326d200..d6484b9cc5 100644
--- a/arch/nds32/cpu/n1213/ag101/lowlevel_init.S
+++ b/arch/nds32/cpu/n1213/ag101/lowlevel_init.S
@@ -32,6 +32,15 @@
 #define SDMC_B0_BSR_D		CONFIG_SYS_FTSDMC021_BANK0_BSR
 #define SDMC_B1_BSR_D		CONFIG_SYS_FTSDMC021_BANK1_BSR
 
+
+/*
+ * for Orca and Emerald
+ */
+#define BOARD_ID_REG		0x104
+#define BOARD_ID_FAMILY_MASK 	0xfff000
+#define BOARD_ID_FAMILY_V5   	0x556000
+#define BOARD_ID_FAMILY_K7   	0x74b000
+
 /*
  * parameters for the static memory controller
  */
@@ -47,6 +56,10 @@
 #define AHBC_CR_A		(CONFIG_FTAHBC020S_BASE + FTAHBC020S_CR)
 #define AHBC_BSR6_A	(CONFIG_FTAHBC020S_BASE + FTAHBC020S_SLAVE_BSR_6)
 
+/*
+ * for Orca and Emerald
+ */
+#define AHBC_BSR4_A	(CONFIG_FTAHBC020S_BASE + FTAHBC020S_SLAVE_BSR_4)
 #define AHBC_BSR6_D		CONFIG_SYS_FTAHBC020S_SLAVE_BSR_6
 
 /*
@@ -100,14 +113,49 @@ mem_init:
 	 *	we need to set onboard SDRAM before remap and relocation.
 	 */
 	led	0x01
-	write32	SMC_BANK0_CR_A, SMC_BANK0_CR_D			! 0x10000052
-	write32	SMC_BANK0_TPR_A, SMC_BANK0_TPR_D		! 0x00151151
+
+  /*
+   * for Orca and Emerald
+   * disable write protection and reset bank size
+   */
+	li	$r0, SMC_BANK0_CR_A
+	lwi $r1, [$r0+#0x00]
+	ori $r1, $r1, 0x8f0
+	xori $r1, $r1, 0x8f0
+  /*
+   * check board
+   */
+	li      $r3, CONFIG_FTPMU010_BASE + BOARD_ID_REG
+  lwi     $r3, [$r3]
+  li      $r4, BOARD_ID_FAMILY_MASK
+  and     $r3, $r3, $r4
+  li      $r4, BOARD_ID_FAMILY_K7
+  xor     $r4, $r3, $r4
+  beqz    $r4, use_flash_16bit_boot
+  /*
+   * 32-bit mode
+   */
+use_flash_32bit_boot:
+	ori     $r1, $r1, 0x50
+  li      $r2, 0x00151151
+  j       sdram_b0_cr
+  /*
+   * 16-bit mode
+   */
+use_flash_16bit_boot:
+  ori     $r1, $r1, 0x60
+  li      $r2, 0x00153153
+  /*
+   * SRAM bank0 config
+   */
+sdram_b0_cr:
+  swi     $r1, [$r0+#0x00]
+  swi     $r2, [$r0+#0x04]
 
 	/*
 	 * config AHB Controller
 	 */
 	led	0x02
-	write32	AHBC_BSR6_A, AHBC_BSR6_D
 
 	/*
 	 * config PMU controller
@@ -194,7 +242,16 @@ relo_base:
 	 * a FLASH connected to bank0.
 	 */
 	led	0x11
-	li	$r4, PHYS_SDRAM_0_AT_INIT		/* 0x10000000 */
+   /*
+    * for Orca and Emerald
+    * read sdram base address automatically
+    */
+	li	$r5, AHBC_BSR6_A
+	lwi $r8, [$r5]
+	li	$r4, 0xfff00000
+	and $r4, $r4, $r8
+
+
 	li	$r5, 0x0
 	la	$r1, relo_base				/* get $pc or $lp */
 	sub	$r2, $r0, $r1
@@ -218,6 +275,29 @@ relo_base:
 	write32 SDMC_B1_BSR_A, 0x00001040
 	setbf15	AHBC_CR_A, FTAHBC020S_CR_REMAP		! 0x1
 
+  /*
+   * for Orca and Emerald
+   * extend sdram size from 256MB to 2GB
+   */
+	li	$r5, AHBC_BSR6_A
+	lwi $r6, [$r5]
+	li  $r4, 0xfff0ffff
+	and $r6 ,$r4 , $r6
+	li	$r4, 0x000b0000
+	or  $r6, $r4,	$r6
+	swi	$r6, [$r5]
+
+  /*
+   * for Orca and Emerald
+   * extend rom base from 256MB to 2GB
+   */
+	li	$r4, AHBC_BSR4_A
+	lwi $r5, [$r4]
+	li	$r6, 0xffffff
+	and $r5, $r5, $r6
+	li  $r6, 0x80000000
+	or  $r5, $r5, $r6
+	swi $r5,	[$r4]
 #endif /* #ifdef CONFIG_MEM_REMAP */
 	move	$lp, $r11
 2:
diff --git a/arch/nds32/cpu/n1213/ag102/Makefile b/arch/nds32/cpu/n1213/ag102/Makefile
index b53a3eb5f4..c21ce02828 100644
--- a/arch/nds32/cpu/n1213/ag102/Makefile
+++ b/arch/nds32/cpu/n1213/ag102/Makefile
@@ -10,33 +10,12 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(SOC).o
-
-COBJS-y	:= cpu.o timer.o
+obj-y	:= cpu.o timer.o
 
 ifndef CONFIG_SKIP_LOWLEVEL_INIT
-SOBJS-y	:= lowlevel_init.o
+obj-y	+= lowlevel_init.o
 endif
 
 ifndef CONFIG_SKIP_TRUNOFF_WATCHDOG
-SOBJS-y	+= watchdog.o
+obj-y	+= watchdog.o
 endif
-
-SRCS	:= $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
-OBJS	:= $(addprefix $(obj),$(SOBJS-y) $(COBJS-y))
-
-all:	$(obj).depend $(LIB)
-
-$(LIB):	$(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
diff --git a/arch/nds32/cpu/n1213/ag102/asm-offsets.c b/arch/nds32/cpu/n1213/ag102/asm-offsets.c
deleted file mode 100644
index 4769a9521d..0000000000
--- a/arch/nds32/cpu/n1213/ag102/asm-offsets.c
+++ /dev/null
@@ -1,54 +0,0 @@
-/*
- * Adapted from Linux v2.6.36 kernel: arch/powerpc/kernel/asm-offsets.c
- *
- * Generate definitions needed by assembly language modules.
- * This code generates raw asm output which is post-processed to extract
- * and format the required data.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-#include <common.h>
-
-#include <linux/kbuild.h>
-
-int main(void)
-{
-#ifdef CONFIG_FTSMC020
-	OFFSET(FTSMC020_BANK0_CR,	ftsmc020, bank[0].cr);
-	OFFSET(FTSMC020_BANK0_TPR,	ftsmc020, bank[0].tpr);
-#endif
-	BLANK();
-#ifdef CONFIG_FTAHBC020S
-	OFFSET(FTAHBC020S_SLAVE_BSR_6,	ftahbc02s, s_bsr[6]);
-	OFFSET(FTAHBC020S_CR,		ftahbc02s, cr);
-#endif
-	BLANK();
-#ifdef CONFIG_ANDES_PCU
-	OFFSET(ANDES_PCU_PCS4,		andes_pcu, pcs4.parm);	/* 0x104 */
-#endif
-	BLANK();
-#ifdef CONFIG_DWCDDR21MCTL
-	OFFSET(DWCDDR21MCTL_CCR,	dwcddr21mctl, ccr);	/* 0x04 */
-	OFFSET(DWCDDR21MCTL_DCR,	dwcddr21mctl, dcr);	/* 0x04 */
-	OFFSET(DWCDDR21MCTL_IOCR,	dwcddr21mctl, iocr);	/* 0x08 */
-	OFFSET(DWCDDR21MCTL_CSR,	dwcddr21mctl, csr);	/* 0x0c */
-	OFFSET(DWCDDR21MCTL_DRR,	dwcddr21mctl, drr);	/* 0x10 */
-	OFFSET(DWCDDR21MCTL_DLLCR0,	dwcddr21mctl, dllcr[0]); /* 0x24 */
-	OFFSET(DWCDDR21MCTL_DLLCR1,	dwcddr21mctl, dllcr[1]); /* 0x28 */
-	OFFSET(DWCDDR21MCTL_DLLCR2,	dwcddr21mctl, dllcr[2]); /* 0x2c */
-	OFFSET(DWCDDR21MCTL_DLLCR3,	dwcddr21mctl, dllcr[3]); /* 0x30 */
-	OFFSET(DWCDDR21MCTL_DLLCR4,	dwcddr21mctl, dllcr[4]); /* 0x34 */
-	OFFSET(DWCDDR21MCTL_DLLCR5,	dwcddr21mctl, dllcr[5]); /* 0x38 */
-	OFFSET(DWCDDR21MCTL_DLLCR6,	dwcddr21mctl, dllcr[6]); /* 0x3c */
-	OFFSET(DWCDDR21MCTL_DLLCR7,	dwcddr21mctl, dllcr[7]); /* 0x40 */
-	OFFSET(DWCDDR21MCTL_DLLCR8,	dwcddr21mctl, dllcr[8]); /* 0x44 */
-	OFFSET(DWCDDR21MCTL_DLLCR9,	dwcddr21mctl, dllcr[9]); /* 0x48 */
-	OFFSET(DWCDDR21MCTL_RSLR0,	dwcddr21mctl, rslr[0]);	/* 0x4c */
-	OFFSET(DWCDDR21MCTL_RDGR0,	dwcddr21mctl, rdgr[0]);	/* 0x5c */
-	OFFSET(DWCDDR21MCTL_DTAR,	dwcddr21mctl, dtar);	/* 0xa4 */
-	OFFSET(DWCDDR21MCTL_MR,		dwcddr21mctl, mr);	/* 0x1f0 */
-#endif
-	return 0;
-}
diff --git a/arch/nds32/lib/Makefile b/arch/nds32/lib/Makefile
index 2f7e155578..6ea96db958 100644
--- a/arch/nds32/lib/Makefile
+++ b/arch/nds32/lib/Makefile
@@ -9,26 +9,7 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(ARCH).o
-
-COBJS-y += board.o
-COBJS-y += cache.o
-COBJS-$(CONFIG_CMD_BOOTM) += bootm.o
-COBJS-y += interrupts.o
-
-SRCS  := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
-OBJS	:= $(addprefix $(obj),$(SOBJS-y) $(COBJS-y))
-
-$(LIB): $(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y += board.o
+obj-y += cache.o
+obj-$(CONFIG_CMD_BOOTM) += bootm.o
+obj-y += interrupts.o
diff --git a/arch/nds32/lib/asm-offsets.c b/arch/nds32/lib/asm-offsets.c
new file mode 100644
index 0000000000..39e3480bd5
--- /dev/null
+++ b/arch/nds32/lib/asm-offsets.c
@@ -0,0 +1,82 @@
+/*
+ * Adapted from Linux v2.6.36 kernel: arch/powerpc/kernel/asm-offsets.c
+ *
+ * Generate definitions needed by assembly language modules.
+ * This code generates raw asm output which is post-processed to extract
+ * and format the required data.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <common.h>
+
+#include <linux/kbuild.h>
+
+int main(void)
+{
+	/*
+	 * TODO : Check if each entry in this file is really necessary.
+	 *   - struct ftahbc02s
+	 *   - struct ftsdmc021
+	 *   - struct andes_pcu
+	 *   - struct dwcddr21mctl
+	 * are used only for generating asm-offsets.h.
+	 * It means their offset addresses are referenced only from assembly
+	 * code. Is it better to define the macros directly in headers?
+	 */
+
+#ifdef CONFIG_FTSMC020
+	OFFSET(FTSMC020_BANK0_CR,	ftsmc020, bank[0].cr);
+	OFFSET(FTSMC020_BANK0_TPR,	ftsmc020, bank[0].tpr);
+#endif
+	BLANK();
+#ifdef CONFIG_FTAHBC020S
+	OFFSET(FTAHBC020S_SLAVE_BSR_4,	ftahbc02s, s_bsr[4]);
+	OFFSET(FTAHBC020S_SLAVE_BSR_6,	ftahbc02s, s_bsr[6]);
+	OFFSET(FTAHBC020S_CR,		ftahbc02s, cr);
+#endif
+	BLANK();
+#ifdef CONFIG_FTPMU010
+	OFFSET(FTPMU010_PDLLCR0,	ftpmu010, PDLLCR0);
+#endif
+	BLANK();
+#ifdef CONFIG_FTSDMC021
+	OFFSET(FTSDMC021_TP1,		ftsdmc021, tp1);
+	OFFSET(FTSDMC021_TP2,		ftsdmc021, tp2);
+	OFFSET(FTSDMC021_CR1,		ftsdmc021, cr1);
+	OFFSET(FTSDMC021_CR2,		ftsdmc021, cr2);
+	OFFSET(FTSDMC021_BANK0_BSR,	ftsdmc021, bank0_bsr);
+	OFFSET(FTSDMC021_BANK1_BSR,	ftsdmc021, bank1_bsr);
+	OFFSET(FTSDMC021_BANK2_BSR,	ftsdmc021, bank2_bsr);
+	OFFSET(FTSDMC021_BANK3_BSR,	ftsdmc021, bank3_bsr);
+#endif
+	BLANK();
+#ifdef CONFIG_ANDES_PCU
+	OFFSET(ANDES_PCU_PCS4,		andes_pcu, pcs4.parm);	/* 0x104 */
+#endif
+	BLANK();
+#ifdef CONFIG_DWCDDR21MCTL
+	OFFSET(DWCDDR21MCTL_CCR,	dwcddr21mctl, ccr);	/* 0x04 */
+	OFFSET(DWCDDR21MCTL_DCR,	dwcddr21mctl, dcr);	/* 0x04 */
+	OFFSET(DWCDDR21MCTL_IOCR,	dwcddr21mctl, iocr);	/* 0x08 */
+	OFFSET(DWCDDR21MCTL_CSR,	dwcddr21mctl, csr);	/* 0x0c */
+	OFFSET(DWCDDR21MCTL_DRR,	dwcddr21mctl, drr);	/* 0x10 */
+	OFFSET(DWCDDR21MCTL_DLLCR0,	dwcddr21mctl, dllcr[0]); /* 0x24 */
+	OFFSET(DWCDDR21MCTL_DLLCR1,	dwcddr21mctl, dllcr[1]); /* 0x28 */
+	OFFSET(DWCDDR21MCTL_DLLCR2,	dwcddr21mctl, dllcr[2]); /* 0x2c */
+	OFFSET(DWCDDR21MCTL_DLLCR3,	dwcddr21mctl, dllcr[3]); /* 0x30 */
+	OFFSET(DWCDDR21MCTL_DLLCR4,	dwcddr21mctl, dllcr[4]); /* 0x34 */
+	OFFSET(DWCDDR21MCTL_DLLCR5,	dwcddr21mctl, dllcr[5]); /* 0x38 */
+	OFFSET(DWCDDR21MCTL_DLLCR6,	dwcddr21mctl, dllcr[6]); /* 0x3c */
+	OFFSET(DWCDDR21MCTL_DLLCR7,	dwcddr21mctl, dllcr[7]); /* 0x40 */
+	OFFSET(DWCDDR21MCTL_DLLCR8,	dwcddr21mctl, dllcr[8]); /* 0x44 */
+	OFFSET(DWCDDR21MCTL_DLLCR9,	dwcddr21mctl, dllcr[9]); /* 0x48 */
+	OFFSET(DWCDDR21MCTL_RSLR0,	dwcddr21mctl, rslr[0]);	/* 0x4c */
+	OFFSET(DWCDDR21MCTL_RDGR0,	dwcddr21mctl, rdgr[0]);	/* 0x5c */
+	OFFSET(DWCDDR21MCTL_DTAR,	dwcddr21mctl, dtar);	/* 0xa4 */
+	OFFSET(DWCDDR21MCTL_MR,		dwcddr21mctl, mr);	/* 0x1f0 */
+#endif
+
+	return 0;
+}
diff --git a/arch/nios2/config.mk b/arch/nios2/config.mk
index 7d546eff69..65a5a40b6d 100644
--- a/arch/nios2/config.mk
+++ b/arch/nios2/config.mk
@@ -6,7 +6,9 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-CROSS_COMPILE ?= nios2-elf-
+ifeq ($(CROSS_COMPILE),)
+CROSS_COMPILE := nios2-elf-
+endif
 
 CONFIG_STANDALONE_LOAD_ADDR ?= 0x02000000
 
diff --git a/arch/nios2/cpu/Makefile b/arch/nios2/cpu/Makefile
index 0834476731..bdd983d3f1 100644
--- a/arch/nios2/cpu/Makefile
+++ b/arch/nios2/cpu/Makefile
@@ -5,29 +5,7 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(CPU).o
-
-START	= start.o
-SOBJS	= exceptions.o
-COBJS	= cpu.o interrupts.o sysid.o traps.o epcs.o
-COBJS	+= fdt.o
-
-SRCS	:= $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS))
-START	:= $(addprefix $(obj),$(START))
-
-all:	$(obj).depend $(START) $(LIB)
-
-$(LIB):	$(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+extra-y	= start.o
+obj-y	= exceptions.o
+obj-y	+= cpu.o interrupts.o sysid.o traps.o epcs.o
+obj-y	+= fdt.o
diff --git a/arch/nios2/lib/Makefile b/arch/nios2/lib/Makefile
index d5dce67abe..7cb25c0ee1 100644
--- a/arch/nios2/lib/Makefile
+++ b/arch/nios2/lib/Makefile
@@ -5,28 +5,8 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(ARCH).o
-
-SOBJS-y	+= cache.o
-
-COBJS-y	+= board.o
-COBJS-$(CONFIG_CMD_BOOTM) += bootm.o
-COBJS-y	+= libgcc.o
-COBJS-y	+= time.o
-
-SRCS	:= $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
-OBJS	:= $(addprefix $(obj),$(SOBJS-y) $(COBJS-y))
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	+= cache.o
+obj-y	+= board.o
+obj-$(CONFIG_CMD_BOOTM) += bootm.o
+obj-y	+= libgcc.o
+obj-y	+= time.o
diff --git a/arch/openrisc/config.mk b/arch/openrisc/config.mk
index 13015ebc21..9902b9adba 100644
--- a/arch/openrisc/config.mk
+++ b/arch/openrisc/config.mk
@@ -5,12 +5,12 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-CROSS_COMPILE ?= or32-elf-
+ifeq ($(CROSS_COMPILE),)
+CROSS_COMPILE := or32-elf-
+endif
 
 # r10 used for global object pointer, already set in OR32 GCC but just to be
 # clear
 PLATFORM_CPPFLAGS += -DCONFIG_OPENRISC -D__OR1K__ -ffixed-r10
 
 CONFIG_STANDALONE_LOAD_ADDR ?= 0x40000
-
-LDSCRIPT ?= $(SRCTREE)/$(CPUDIR)/u-boot.lds
diff --git a/arch/openrisc/cpu/Makefile b/arch/openrisc/cpu/Makefile
index 863d9b3e86..fc47d666fe 100644
--- a/arch/openrisc/cpu/Makefile
+++ b/arch/openrisc/cpu/Makefile
@@ -5,27 +5,5 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(CPU).o
-
-START	= start.o
-COBJS-y	= cache.o cpu.o exceptions.o interrupts.o
-
-SRCS	:= $(START:.o=.S) $(COBJS-y:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS-y))
-START	:= $(addprefix $(obj),$(START))
-
-all:	$(obj).depend $(START) $(LIB)
-
-$(LIB):	$(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+extra-y	= start.o
+obj-y	= cache.o cpu.o exceptions.o interrupts.o
diff --git a/arch/openrisc/lib/Makefile b/arch/openrisc/lib/Makefile
index b2218c990f..dfa72d915f 100644
--- a/arch/openrisc/lib/Makefile
+++ b/arch/openrisc/lib/Makefile
@@ -5,27 +5,6 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(ARCH).o
-
-SOBJS-y	+=
-
-COBJS-y	+= board.o
-COBJS-$(CONFIG_CMD_BOOTM) += bootm.o
-COBJS-y	+= timer.o
-
-SRCS	:= $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
-OBJS	:= $(addprefix $(obj),$(SOBJS-y) $(COBJS-y))
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	+= board.o
+obj-$(CONFIG_CMD_BOOTM) += bootm.o
+obj-y	+= timer.o
diff --git a/arch/powerpc/config.mk b/arch/powerpc/config.mk
index e6bb935729..fb7096e7b5 100644
--- a/arch/powerpc/config.mk
+++ b/arch/powerpc/config.mk
@@ -5,12 +5,15 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-CROSS_COMPILE ?= ppc_8xx-
+ifeq ($(CROSS_COMPILE),)
+CROSS_COMPILE := ppc_8xx-
+endif
 
 CONFIG_STANDALONE_LOAD_ADDR ?= 0x40000
 LDFLAGS_FINAL += --gc-sections
-PLATFORM_RELFLAGS += -fpic -mrelocatable -ffunction-sections -fdata-sections
-PLATFORM_CPPFLAGS += -DCONFIG_PPC -D__powerpc__
+PLATFORM_RELFLAGS += -fpic -mrelocatable -ffunction-sections -fdata-sections \
+								-meabi
+PLATFORM_CPPFLAGS += -DCONFIG_PPC -D__powerpc__ -ffixed-r2
 PLATFORM_LDFLAGS  += -n
 
 # Support generic board on PPC
@@ -32,5 +35,14 @@ endif
 
 # Only test once
 ifneq ($(CONFIG_SPL_BUILD),y)
-ALL-y += checkgcc4
+archprepare: checkgcc4
+
+# GCC 3.x is reported to have problems generating the type of relocation
+# that U-Boot wants.
+# See http://lists.denx.de/pipermail/u-boot/2012-September/135156.html
+checkgcc4:
+	@if test $(call cc-version) -lt 0400; then \
+		echo -n '*** Your GCC is too old, please upgrade to GCC 4.x or newer'; \
+		false; \
+	fi
 endif
diff --git a/arch/powerpc/cpu/74xx_7xx/Makefile b/arch/powerpc/cpu/74xx_7xx/Makefile
index de9b4a72cd..f31fe756e3 100644
--- a/arch/powerpc/cpu/74xx_7xx/Makefile
+++ b/arch/powerpc/cpu/74xx_7xx/Makefile
@@ -8,28 +8,6 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(CPU).o
-
-START	= start.o
-SOBJS	= cache.o kgdb.o io.o
-COBJS	= traps.o cpu.o cpu_init.o speed.o interrupts.o
-
-SRCS	:= $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS))
-START	:= $(addprefix $(obj),$(START))
-
-all:	$(obj).depend $(START) $(LIB)
-
-$(LIB):	$(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+extra-y	= start.o
+obj-y	= cache.o kgdb.o io.o
+obj-y	+= traps.o cpu.o cpu_init.o speed.o interrupts.o
diff --git a/arch/powerpc/cpu/74xx_7xx/config.mk b/arch/powerpc/cpu/74xx_7xx/config.mk
index 9053191602..96812a02d8 100644
--- a/arch/powerpc/cpu/74xx_7xx/config.mk
+++ b/arch/powerpc/cpu/74xx_7xx/config.mk
@@ -5,6 +5,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-PLATFORM_RELFLAGS += -meabi
-
-PLATFORM_CPPFLAGS += -DCONFIG_74xx_7xx -ffixed-r2 -mstring
+PLATFORM_CPPFLAGS += -DCONFIG_74xx_7xx -mstring
diff --git a/arch/powerpc/cpu/Makefile b/arch/powerpc/cpu/Makefile
new file mode 100644
index 0000000000..88b5298be0
--- /dev/null
+++ b/arch/powerpc/cpu/Makefile
@@ -0,0 +1,3 @@
+obj-$(CONFIG_MPC83xx) += mpc8xxx/
+obj-$(CONFIG_MPC85xx) += mpc8xxx/
+obj-$(CONFIG_MPC86xx) += mpc8xxx/
diff --git a/arch/powerpc/cpu/mpc512x/Makefile b/arch/powerpc/cpu/mpc512x/Makefile
index 1af9ab1e96..a4934ef78a 100644
--- a/arch/powerpc/cpu/mpc512x/Makefile
+++ b/arch/powerpc/cpu/mpc512x/Makefile
@@ -4,44 +4,19 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-$(shell mkdir -p $(OBJTREE)/board/freescale/common)
-
-LIB	= $(obj)lib$(CPU).o
-
-START	= start.o
-COBJS-y	:= cpu.o
-COBJS-y	+= traps.o
-COBJS-y += cpu_init.o
-COBJS-y += fixed_sdram.o
-COBJS-y += i2c.o
-COBJS-y += interrupts.o
-COBJS-y += iopin.o
-COBJS-y += serial.o
-COBJS-y += speed.o
-COBJS-$(CONFIG_FSL_DIU_FB) += diu.o
-COBJS-$(CONFIG_CMD_IDE) += ide.o
-COBJS-$(CONFIG_PCI) += pci.o
+extra-y	= start.o
+obj-y	:= cpu.o
+obj-y	+= traps.o
+obj-y += cpu_init.o
+obj-y += fixed_sdram.o
+obj-y += i2c.o
+obj-y += interrupts.o
+obj-y += iopin.o
+obj-y += serial.o
+obj-y += speed.o
+obj-$(CONFIG_FSL_DIU_FB) += diu.o
+obj-$(CONFIG_CMD_IDE) += ide.o
+obj-$(CONFIG_PCI) += pci.o
 
 # Stub implementations of cache management functions for USB
-COBJS-$(CONFIG_USB_EHCI) += cache.o
-
-COBJS	:= $(COBJS-y)
-SRCS	:= $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS))
-START	:= $(addprefix $(obj),$(START))
-
-all:	$(obj).depend $(START) $(LIB)
-
-$(LIB):	$(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-$(CONFIG_USB_EHCI) += cache.o
diff --git a/arch/powerpc/cpu/mpc512x/config.mk b/arch/powerpc/cpu/mpc512x/config.mk
index 04717a485e..03759e6625 100644
--- a/arch/powerpc/cpu/mpc512x/config.mk
+++ b/arch/powerpc/cpu/mpc512x/config.mk
@@ -4,7 +4,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-PLATFORM_RELFLAGS += -meabi
-
-PLATFORM_CPPFLAGS += -DCONFIG_MPC512X -DCONFIG_E300 \
-			-ffixed-r2 -msoft-float -mcpu=603e
+PLATFORM_CPPFLAGS += -DCONFIG_MPC512X -DCONFIG_E300 -msoft-float -mcpu=603e
diff --git a/arch/powerpc/cpu/mpc512x/traps.c b/arch/powerpc/cpu/mpc512x/traps.c
index 10169912b7..9f5bcd7fc3 100644
--- a/arch/powerpc/cpu/mpc512x/traps.c
+++ b/arch/powerpc/cpu/mpc512x/traps.c
@@ -27,7 +27,6 @@ extern unsigned long search_exception_table(unsigned long);
  * amount of memory on the system if we're unable to keep all
  * the memory mapped in.
  */
-extern ulong get_effective_memsize(void);
 #define END_OF_MEM (gd->bd->bi_memstart + get_effective_memsize())
 
 /*
diff --git a/arch/powerpc/cpu/mpc5xx/Makefile b/arch/powerpc/cpu/mpc5xx/Makefile
index e3e50af2cd..7b8826a643 100644
--- a/arch/powerpc/cpu/mpc5xx/Makefile
+++ b/arch/powerpc/cpu/mpc5xx/Makefile
@@ -16,28 +16,5 @@
 #			uses the definitions made in arch/powerpc/cpu/mpc5xx/config.mk
 #
 
-
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(CPU).o
-
-START	= start.o
-COBJS	= serial.o cpu.o cpu_init.o interrupts.o traps.o speed.o spi.o
-
-SRCS	:= $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS))
-START	:= $(addprefix $(obj),$(START))
-
-all:	$(obj).depend $(START) $(LIB)
-
-$(LIB):	$(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+extra-y	= start.o
+obj-y	= serial.o cpu.o cpu_init.o interrupts.o traps.o speed.o spi.o
diff --git a/arch/powerpc/cpu/mpc5xx/config.mk b/arch/powerpc/cpu/mpc5xx/config.mk
index b33f17a1ba..31e2dc9873 100644
--- a/arch/powerpc/cpu/mpc5xx/config.mk
+++ b/arch/powerpc/cpu/mpc5xx/config.mk
@@ -5,6 +5,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-PLATFORM_RELFLAGS +=	-meabi
-
-PLATFORM_CPPFLAGS +=	-DCONFIG_5xx -ffixed-r2 -mpowerpc -msoft-float
+PLATFORM_CPPFLAGS += -DCONFIG_5xx -mpowerpc -msoft-float
diff --git a/arch/powerpc/cpu/mpc5xx/start.S b/arch/powerpc/cpu/mpc5xx/start.S
index bdd46d955d..6b196de355 100644
--- a/arch/powerpc/cpu/mpc5xx/start.S
+++ b/arch/powerpc/cpu/mpc5xx/start.S
@@ -19,13 +19,9 @@
 #include <mpc5xx.h>
 #include <version.h>
 
-#define CONFIG_5xx 1		/* needed for Linux kernel header files */
-#define _LINUX_CONFIG_H 1	/* avoid reading Linux autoconf.h file	*/
-
 #include <ppc_asm.tmpl>
 #include <ppc_defs.h>
 
-#include <linux/config.h>
 #include <asm/processor.h>
 #include <asm/u-boot.h>
 
diff --git a/arch/powerpc/cpu/mpc5xxx/Makefile b/arch/powerpc/cpu/mpc5xxx/Makefile
index fc0b7a192e..5c67e1d37d 100644
--- a/arch/powerpc/cpu/mpc5xxx/Makefile
+++ b/arch/powerpc/cpu/mpc5xxx/Makefile
@@ -5,44 +5,22 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(CPU).o
-
-SSTART	= start.o
-CSTART  = traps.o
-SOBJS  += io.o
-SOBJS  += firmware_sc_task_bestcomm.impl.o
-COBJS-y += i2c.o
-COBJS-y += cpu.o
-COBJS-y += cpu_init.o
-COBJS-y += ide.o
-COBJS-y += interrupts.o
-COBJS-y += loadtask.o
-COBJS-y += pci_mpc5200.o
-COBJS-y += serial.o
-COBJS-y += speed.o
-COBJS-$(CONFIG_CMD_USB) += usb_ohci.o
-COBJS-$(CONFIG_CMD_USB) += usb.o
+extra-y	= start.o
+extra-y += traps.o
+obj-y  += io.o
+obj-y  += firmware_sc_task_bestcomm.impl.o
+obj-y += i2c.o
+obj-y += cpu.o
+obj-y += cpu_init.o
+obj-y += ide.o
+obj-y += interrupts.o
+obj-y += loadtask.o
+obj-y += pci_mpc5200.o
+obj-y += serial.o
+obj-y += speed.o
+obj-$(CONFIG_CMD_USB) += usb_ohci.o
+obj-$(CONFIG_CMD_USB) += usb.o
 
 ifdef CONFIG_SPL_BUILD
-COBJS-y += spl_boot.o
+obj-y += spl_boot.o
 endif
-
-SRCS	:= $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
-OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS-y))
-START	:= $(addprefix $(obj),$(SSTART) $(CSTART))
-
-all:	$(obj).depend $(START) $(LIB)
-
-$(LIB):	$(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
diff --git a/arch/powerpc/cpu/mpc5xxx/config.mk b/arch/powerpc/cpu/mpc5xxx/config.mk
index 57bdd2d252..3384f6ffcc 100644
--- a/arch/powerpc/cpu/mpc5xxx/config.mk
+++ b/arch/powerpc/cpu/mpc5xxx/config.mk
@@ -5,7 +5,5 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-PLATFORM_RELFLAGS += -meabi
-
-PLATFORM_CPPFLAGS += -DCONFIG_MPC5xxx -ffixed-r2 \
+PLATFORM_CPPFLAGS += -DCONFIG_MPC5xxx \
 		     -mstring -mcpu=603e -mmultiple
diff --git a/arch/powerpc/cpu/mpc5xxx/start.S b/arch/powerpc/cpu/mpc5xxx/start.S
index 517b5808fe..02c706ec63 100644
--- a/arch/powerpc/cpu/mpc5xxx/start.S
+++ b/arch/powerpc/cpu/mpc5xxx/start.S
@@ -14,9 +14,6 @@
 #include <mpc5xxx.h>
 #include <version.h>
 
-#define CONFIG_MPC5xxx 1	/* needed for Linux kernel header files */
-#define _LINUX_CONFIG_H 1	/* avoid reading Linux autoconf.h file	*/
-
 #include <ppc_asm.tmpl>
 #include <ppc_defs.h>
 
diff --git a/arch/powerpc/cpu/mpc5xxx/usb_ohci.c b/arch/powerpc/cpu/mpc5xxx/usb_ohci.c
index 3d345ff53e..3c8b2d904f 100644
--- a/arch/powerpc/cpu/mpc5xxx/usb_ohci.c
+++ b/arch/powerpc/cpu/mpc5xxx/usb_ohci.c
@@ -842,104 +842,7 @@ static int dl_done_list (ohci_t *ohci, td_t *td_list)
  * Virtual Root Hub
  *-------------------------------------------------------------------------*/
 
-/* Device descriptor */
-static __u8 root_hub_dev_des[] =
-{
-	0x12,	    /*	__u8  bLength; */
-	0x01,	    /*	__u8  bDescriptorType; Device */
-	0x10,	    /*	__u16 bcdUSB; v1.1 */
-	0x01,
-	0x09,	    /*	__u8  bDeviceClass; HUB_CLASSCODE */
-	0x00,	    /*	__u8  bDeviceSubClass; */
-	0x00,	    /*	__u8  bDeviceProtocol; */
-	0x08,	    /*	__u8  bMaxPacketSize0; 8 Bytes */
-	0x00,	    /*	__u16 idVendor; */
-	0x00,
-	0x00,	    /*	__u16 idProduct; */
-	0x00,
-	0x00,	    /*	__u16 bcdDevice; */
-	0x00,
-	0x00,	    /*	__u8  iManufacturer; */
-	0x01,	    /*	__u8  iProduct; */
-	0x00,	    /*	__u8  iSerialNumber; */
-	0x01	    /*	__u8  bNumConfigurations; */
-};
-
-
-/* Configuration descriptor */
-static __u8 root_hub_config_des[] =
-{
-	0x09,	    /*	__u8  bLength; */
-	0x02,	    /*	__u8  bDescriptorType; Configuration */
-	0x19,	    /*	__u16 wTotalLength; */
-	0x00,
-	0x01,	    /*	__u8  bNumInterfaces; */
-	0x01,	    /*	__u8  bConfigurationValue; */
-	0x00,	    /*	__u8  iConfiguration; */
-	0x40,	    /*	__u8  bmAttributes;
-		 Bit 7: Bus-powered, 6: Self-powered, 5 Remote-wakwup, 4..0: resvd */
-	0x00,	    /*	__u8  MaxPower; */
-
-	/* interface */
-	0x09,	    /*	__u8  if_bLength; */
-	0x04,	    /*	__u8  if_bDescriptorType; Interface */
-	0x00,	    /*	__u8  if_bInterfaceNumber; */
-	0x00,	    /*	__u8  if_bAlternateSetting; */
-	0x01,	    /*	__u8  if_bNumEndpoints; */
-	0x09,	    /*	__u8  if_bInterfaceClass; HUB_CLASSCODE */
-	0x00,	    /*	__u8  if_bInterfaceSubClass; */
-	0x00,	    /*	__u8  if_bInterfaceProtocol; */
-	0x00,	    /*	__u8  if_iInterface; */
-
-	/* endpoint */
-	0x07,	    /*	__u8  ep_bLength; */
-	0x05,	    /*	__u8  ep_bDescriptorType; Endpoint */
-	0x81,	    /*	__u8  ep_bEndpointAddress; IN Endpoint 1 */
-	0x03,	    /*	__u8  ep_bmAttributes; Interrupt */
-	0x02,	    /*	__u16 ep_wMaxPacketSize; ((MAX_ROOT_PORTS + 1) / 8 */
-	0x00,
-	0xff	    /*	__u8  ep_bInterval; 255 ms */
-};
-
-static unsigned char root_hub_str_index0[] =
-{
-	0x04,			/*  __u8  bLength; */
-	0x03,			/*  __u8  bDescriptorType; String-descriptor */
-	0x09,			/*  __u8  lang ID */
-	0x04,			/*  __u8  lang ID */
-};
-
-static unsigned char root_hub_str_index1[] =
-{
-	28,			/*  __u8  bLength; */
-	0x03,			/*  __u8  bDescriptorType; String-descriptor */
-	'O',			/*  __u8  Unicode */
-	0,				/*  __u8  Unicode */
-	'H',			/*  __u8  Unicode */
-	0,				/*  __u8  Unicode */
-	'C',			/*  __u8  Unicode */
-	0,				/*  __u8  Unicode */
-	'I',			/*  __u8  Unicode */
-	0,				/*  __u8  Unicode */
-	' ',			/*  __u8  Unicode */
-	0,				/*  __u8  Unicode */
-	'R',			/*  __u8  Unicode */
-	0,				/*  __u8  Unicode */
-	'o',			/*  __u8  Unicode */
-	0,				/*  __u8  Unicode */
-	'o',			/*  __u8  Unicode */
-	0,				/*  __u8  Unicode */
-	't',			/*  __u8  Unicode */
-	0,				/*  __u8  Unicode */
-	' ',			/*  __u8  Unicode */
-	0,				/*  __u8  Unicode */
-	'H',			/*  __u8  Unicode */
-	0,				/*  __u8  Unicode */
-	'u',			/*  __u8  Unicode */
-	0,				/*  __u8  Unicode */
-	'b',			/*  __u8  Unicode */
-	0,				/*  __u8  Unicode */
-};
+#include <usbroothubdes.h>
 
 /* Hub class-specific descriptor is constructed dynamically */
 
@@ -1544,7 +1447,7 @@ static void hc_release_ohci (ohci_t *ohci)
  */
 static char ohci_inited = 0;
 
-int usb_lowlevel_init(int index, void **controller)
+int usb_lowlevel_init(int index, enum usb_init_type init, void **controller)
 {
 
 	/* Set the USB Clock						     */
diff --git a/arch/powerpc/cpu/mpc824x/.gitignore b/arch/powerpc/cpu/mpc824x/.gitignore
deleted file mode 100644
index 2d79931e96..0000000000
--- a/arch/powerpc/cpu/mpc824x/.gitignore
+++ /dev/null
@@ -1 +0,0 @@
-/bedbug_603e.c
diff --git a/arch/powerpc/cpu/mpc824x/Makefile b/arch/powerpc/cpu/mpc824x/Makefile
index 8f27aac25d..2c8be92571 100644
--- a/arch/powerpc/cpu/mpc824x/Makefile
+++ b/arch/powerpc/cpu/mpc824x/Makefile
@@ -5,35 +5,7 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-ifneq ($(OBJTREE),$(SRCTREE))
-$(shell mkdir -p $(obj)drivers/epic $(obj)drivers/i2c)
-endif
-
-LIB	= $(obj)lib$(CPU).o
-
-START	= start.o
-COBJS	= traps.o cpu.o cpu_init.o interrupts.o speed.o \
+extra-y	= start.o
+obj-y	= traps.o cpu.o cpu_init.o interrupts.o speed.o \
 	  drivers/epic/epic1.o drivers/i2c/i2c.o pci.o
-COBJS_LN = bedbug_603e.o
-
-SRCS	:= $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c) $(addprefix $(obj),$(COBJS_LN:.o=.c))
-OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS) $(COBJS_LN))
-START	:= $(addprefix $(obj),$(START))
-
-all:	$(obj).depend $(START) $(LIB)
-
-$(LIB):	$(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-$(obj)bedbug_603e.c:
-	ln -sf $(src)../mpc8260/bedbug_603e.c $(obj)bedbug_603e.c
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y += ../mpc8260/bedbug_603e.o
diff --git a/arch/powerpc/cpu/mpc824x/config.mk b/arch/powerpc/cpu/mpc824x/config.mk
index ef605f0797..a224bc8e73 100644
--- a/arch/powerpc/cpu/mpc824x/config.mk
+++ b/arch/powerpc/cpu/mpc824x/config.mk
@@ -5,6 +5,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-PLATFORM_RELFLAGS += -meabi
-
-PLATFORM_CPPFLAGS += -DCONFIG_MPC824X -ffixed-r2 -mstring -mcpu=603e -msoft-float
+PLATFORM_CPPFLAGS += -DCONFIG_MPC824X -mstring -mcpu=603e -msoft-float
diff --git a/arch/powerpc/cpu/mpc824x/cpu_init.c b/arch/powerpc/cpu/mpc824x/cpu_init.c
index 37d796e635..47ac18e757 100644
--- a/arch/powerpc/cpu/mpc824x/cpu_init.c
+++ b/arch/powerpc/cpu/mpc824x/cpu_init.c
@@ -52,7 +52,7 @@ cpu_init_f (void)
     CONFIG_WRITE_HALFWORD(PCICR, 0x06); /* Bus Master, respond to PCI memory space acesses*/
 /*    CONFIG_WRITE_HALFWORD(PCISR, 0xffff); */ /*reset PCISR*/
 
-#if defined(CONFIG_MUSENKI) || defined(CONFIG_PN62)
+#if defined(CONFIG_MUSENKI)
 /* Why is this here, you ask?  Try, just try setting 0x8000
  * in PCIACR with CONFIG_WRITE_HALFWORD()
  * this one was a stumper, and we are annoyed
@@ -142,9 +142,7 @@ cpu_init_f (void)
 
 	CONFIG_READ_WORD(PICR2, val);
 	val= val & ~ (PICR2_CF_SNOOP_WS_MASK | PICR2_CF_APHASE_WS_MASK); /*mask off waitstate bits*/
-#ifndef CONFIG_PN62
 	val |= PICR2_CF_SNOOP_WS_1WS | PICR2_CF_APHASE_WS_1WS; /*1 wait state*/
-#endif
 	CONFIG_WRITE_WORD(PICR2, val);
 
 	CONFIG_WRITE_WORD(EUMBBAR, CONFIG_SYS_EUMB_ADDR);
@@ -186,7 +184,7 @@ cpu_init_f (void)
  *  should define CONFIG_SYS_ACTORW to 0 if they don't want to set it, or even, if
  *  its not set, we define it to zero in this file
  */
-#if defined(CONFIG_CU824) || defined(CONFIG_PN62)
+#if defined(CONFIG_CU824)
 	CONFIG_WRITE_WORD(MCCR4,
 	(CONFIG_SYS_PRETOACT << MCCR4_PRETOACT_SHIFT) |
 	(CONFIG_SYS_ACTTOPRE << MCCR4_ACTTOPRE_SHIFT) |
diff --git a/arch/powerpc/cpu/mpc824x/drivers/i2c_export.h b/arch/powerpc/cpu/mpc824x/drivers/i2c_export.h
deleted file mode 100644
index 6264d189bb..0000000000
--- a/arch/powerpc/cpu/mpc824x/drivers/i2c_export.h
+++ /dev/null
@@ -1,103 +0,0 @@
-#ifndef I2C_EXPORT_H
-#define I2C_EXPORT_H
-
-/****************************************************
- *
- * Copyright Motrola 1999
- *
- ****************************************************/
-
-/* These are the defined return values for the I2C_do_transaction function.
- * Any non-zero value indicates failure.  Failure modes can be added for
- * more detailed error reporting.
- */
-typedef enum _i2c_status
-{
- I2C_SUCCESS     = 0,
- I2C_ERROR,
-} I2C_Status;
-
-/* These are the defined tasks for I2C_do_transaction.
- * Modes for SLAVE_RCV and SLAVE_XMIT will be added.
- */
-typedef enum _i2c_transaction_mode
-{
-	I2C_MASTER_RCV =  0,
-	I2C_MASTER_XMIT = 1,
-} I2C_TRANSACTION_MODE;
-
-typedef enum _i2c_interrupt_mode
-{
-	I2C_INT_DISABLE =  0,
-	I2C_INT_ENABLE = 1,
-} I2C_INTERRUPT_MODE;
-
-typedef enum _i2c_stop
-{
-	I2C_NO_STOP =  0,
-	I2C_STOP = 1,
-} I2C_STOP_MODE;
-
-typedef enum _i2c_restart
-{
-	I2C_NO_RESTART =  0,
-	I2C_RESTART = 1,
-} I2C_RESTART_MODE;
-
-/******************** App. API ********************
- * The application API is for user level application
- * to use the functionality provided by I2C driver.
- * This is a "generic" I2C interface, it should contain
- * nothing specific to the Kahlua implementation.
- * Only the generic functions are exported by the library.
- *
- * Note: Its App.s responsibility to swap the data
- *       byte. In our API, we just transfer whatever
- *       we are given
- **************************************************/
-
-
-/*  Initialize I2C unit with the following:
- *  driver's slave address
- *  interrupt enabled
- *  optional pointer to application layer print function
- *
- *  These parameters may be added:
- *  desired clock rate
- *  digital filter frequency sampling rate
- *
- *  This function must be called before I2C unit can be used.
- */
-extern I2C_Status I2C_Initialize(
-	unsigned char addr,            /* driver's I2C slave address */
-	I2C_INTERRUPT_MODE en_int,     /* 1 - enable I2C interrupt
-					* 0 - disable I2C interrupt
-					*/
-	int (*app_print_function)(char *,...)); /* pointer to optional "printf"
-						 * provided by application
-						 */
-
-/* Perform the given I2C transaction, only MASTER_XMIT and MASTER_RCV
- * are implemented.  Both are only in polling mode.
- *
- * en_int controls interrupt/polling mode
- * act is the type of transaction
- * addr is the I2C address of the slave device
- * len is the length of data to send or receive
- * buffer is the address of the data buffer
- * stop = I2C_NO_STOP, don't signal STOP at end of transaction
- *        I2C_STOP, signal STOP at end of transaction
- * retry is the timeout retry value, currently ignored
- * rsta = I2C_NO_RESTART, this is not continuation of existing transaction
- *        I2C_RESTART, this is a continuation of existing transaction
- */
-extern I2C_Status I2C_do_transaction( I2C_INTERRUPT_MODE en_int,
-				      I2C_TRANSACTION_MODE act,
-				      unsigned char i2c_addr,
-				      unsigned char data_addr,
-				      int len,
-				      char *buffer,
-				      I2C_STOP_MODE stop,
-				      int retry,
-				      I2C_RESTART_MODE rsta);
-#endif
diff --git a/arch/powerpc/cpu/mpc824x/start.S b/arch/powerpc/cpu/mpc824x/start.S
index 6f397a44c6..b1fb062a08 100644
--- a/arch/powerpc/cpu/mpc824x/start.S
+++ b/arch/powerpc/cpu/mpc824x/start.S
@@ -26,8 +26,6 @@
 #include <mpc824x.h>
 #include <version.h>
 
-#define _LINUX_CONFIG_H 1	/* avoid reading Linux autoconf.h file	*/
-
 #include <ppc_asm.tmpl>
 #include <ppc_defs.h>
 
diff --git a/arch/powerpc/cpu/mpc8260/Makefile b/arch/powerpc/cpu/mpc8260/Makefile
index d87eff6414..83adc4c436 100644
--- a/arch/powerpc/cpu/mpc8260/Makefile
+++ b/arch/powerpc/cpu/mpc8260/Makefile
@@ -5,33 +5,9 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(CPU).o
-
-START	= start.o kgdb.o
-COBJS	= traps.o serial_smc.o serial_scc.o cpu.o cpu_init.o speed.o \
+extra-y	= start.o
+obj-y	= traps.o serial_smc.o serial_scc.o cpu.o cpu_init.o speed.o \
 	  interrupts.o ether_fcc.o i2c.o commproc.o \
-	  bedbug_603e.o pci.o spi.o
-
-COBJS-$(CONFIG_ETHER_ON_SCC) = ether_scc.o
-
-COBJS	+= $(COBJS-y)
-
-SRCS	:= $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS))
-START	:= $(addprefix $(obj),$(START))
-
-all:	$(obj).depend $(START) $(LIB)
-
-$(LIB):	$(OBJS)
-	$(call cmd_link_o_target, $(OBJS) $(obj)kgdb.o)
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
+	  bedbug_603e.o pci.o spi.o kgdb.o
 
-#########################################################################
+obj-$(CONFIG_ETHER_ON_SCC) += ether_scc.o
diff --git a/arch/powerpc/cpu/mpc8260/config.mk b/arch/powerpc/cpu/mpc8260/config.mk
index 91b0497ccb..59f152df74 100644
--- a/arch/powerpc/cpu/mpc8260/config.mk
+++ b/arch/powerpc/cpu/mpc8260/config.mk
@@ -5,7 +5,5 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-PLATFORM_RELFLAGS += -meabi
-
-PLATFORM_CPPFLAGS += -DCONFIG_8260 -DCONFIG_CPM2 -ffixed-r2 \
+PLATFORM_CPPFLAGS += -DCONFIG_MPC8260 -DCONFIG_CPM2 \
 		     -mstring -mcpu=603e -mmultiple
diff --git a/arch/powerpc/cpu/mpc8260/kgdb.S b/arch/powerpc/cpu/mpc8260/kgdb.S
index 5a298f9d05..1432344bcc 100644
--- a/arch/powerpc/cpu/mpc8260/kgdb.S
+++ b/arch/powerpc/cpu/mpc8260/kgdb.S
@@ -9,9 +9,6 @@
 #include <mpc8260.h>
 #include <version.h>
 
-#define CONFIG_8260 1		/* needed for Linux kernel header files */
-#define _LINUX_CONFIG_H 1	/* avoid reading Linux autoconf.h file	*/
-
 #include <ppc_asm.tmpl>
 #include <ppc_defs.h>
 
diff --git a/arch/powerpc/cpu/mpc8260/speed.h b/arch/powerpc/cpu/mpc8260/speed.h
deleted file mode 100644
index f1b10bf25e..0000000000
--- a/arch/powerpc/cpu/mpc8260/speed.h
+++ /dev/null
@@ -1,38 +0,0 @@
-/*
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-/*-----------------------------------------------------------------------
- * Timer value for timer 2, ICLK = 10
- *
- * SPEED_FCOUNT2 =  GCLK / (16 * (TIMER_TMR_PS + 1))
- * SPEED_TMR3_PS = (GCLK / (16 * SPEED_FCOUNT3)) - 1
- *
- * SPEED_FCOUNT2	timer 2 counting frequency
- * GCLK			CPU clock
- * SPEED_TMR2_PS	prescaler
- */
-#define SPEED_TMR2_PS	(250 - 1)	/* divide by 250	*/
-
-/*-----------------------------------------------------------------------
- * Timer value for PIT
- *
- * PIT_TIME = SPEED_PITC / PITRTCLK
- * PITRTCLK = 8192
- */
-#define SPEED_PITC	(82 << 16)	/* start counting from 82	*/
-
-/*
- * The new value for PTA is calculated from
- *
- *	PTA = (gclk * Trefresh) / (2 ^ (2 * DFBRG) * PTP * NCS)
- *
- * gclk		CPU clock (not bus clock !)
- * Trefresh	Refresh cycle * 4 (four word bursts used)
- * DFBRG	For normal mode (no clock reduction) always 0
- * PTP		Prescaler (already adjusted for no. of banks and 4K / 8K refresh)
- * NCS		Number of SDRAM banks (chip selects) on this UPM.
- */
diff --git a/arch/powerpc/cpu/mpc8260/start.S b/arch/powerpc/cpu/mpc8260/start.S
index 1269291c45..324f132bad 100644
--- a/arch/powerpc/cpu/mpc8260/start.S
+++ b/arch/powerpc/cpu/mpc8260/start.S
@@ -14,9 +14,6 @@
 #include <mpc8260.h>
 #include <version.h>
 
-#define CONFIG_8260 1		/* needed for Linux kernel header files */
-#define _LINUX_CONFIG_H 1	/* avoid reading Linux autoconf.h file	*/
-
 #include <ppc_asm.tmpl>
 #include <ppc_defs.h>
 
diff --git a/arch/powerpc/cpu/mpc83xx/Makefile b/arch/powerpc/cpu/mpc83xx/Makefile
index 6341cd4fff..cf9116274d 100644
--- a/arch/powerpc/cpu/mpc83xx/Makefile
+++ b/arch/powerpc/cpu/mpc83xx/Makefile
@@ -7,10 +7,6 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(CPU).o
-
 MINIMAL=
 
 ifdef CONFIG_SPL_BUILD
@@ -19,62 +15,32 @@ MINIMAL=y
 endif
 endif
 
-START	= start.o
+extra-y	= start.o
 
 ifdef MINIMAL
 
-COBJS-y	+= spl_minimal.o
+obj-y	+= spl_minimal.o
 
 else
 
-COBJS-y += traps.o
-COBJS-y += cpu.o
-COBJS-y += cpu_init.o
-COBJS-y += speed.o
-COBJS-y += interrupts.o
-COBJS-y += ecc.o
-COBJS-$(CONFIG_QE) += qe_io.o
-COBJS-$(CONFIG_FSL_SERDES) += serdes.o
-COBJS-$(CONFIG_PCI) += pci.o
-COBJS-$(CONFIG_PCIE) += pcie.o
-COBJS-$(CONFIG_OF_LIBFDT) += fdt.o
+obj-y += traps.o
+obj-y += cpu.o
+obj-y += cpu_init.o
+obj-y += speed.o
+obj-y += interrupts.o
+obj-y += ecc.o
+obj-$(CONFIG_QE) += qe_io.o
+obj-$(CONFIG_FSL_SERDES) += serdes.o
+obj-$(CONFIG_PCI) += pci.o
+obj-$(CONFIG_PCIE) += pcie.o
+obj-$(CONFIG_OF_LIBFDT) += fdt.o
 
 # Stub implementations of cache management functions for USB
-COBJS-y += cache.o
+obj-y += cache.o
 
-ifdef CONFIG_FSL_DDR2
-COBJS_LN-$(CONFIG_MPC8349) += ddr-gen2.o
-else
-COBJS-y += spd_sdram.o
+ifndef CONFIG_SYS_FSL_DDRC_GEN2
+obj-y += spd_sdram.o
 endif
-COBJS-$(CONFIG_FSL_DDR2) += law.o
+obj-$(CONFIG_SYS_FSL_DDR2) += law.o
 
 endif # not minimal
-
-COBJS	:= $(COBJS-y)
-SRCS	:= $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c) $(addprefix $(obj),$(COBJS_LN-y:.o=.c))
-OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS) $(COBJS_LN-y))
-START	:= $(addprefix $(obj),$(START))
-
-all:	$(obj).depend $(START) $(LIB)
-
-$(LIB):	$(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-$(obj)ddr-gen1.c:
-	ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/ddr-gen1.c $(obj)ddr-gen1.c
-
-$(obj)ddr-gen2.c:
-	ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/ddr-gen2.c $(obj)ddr-gen2.c
-
-$(obj)ddr-gen3.c:
-	ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/ddr-gen3.c $(obj)ddr-gen3.c
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
diff --git a/arch/powerpc/cpu/mpc83xx/config.mk b/arch/powerpc/cpu/mpc83xx/config.mk
index c16a00376f..dfce4d53b4 100644
--- a/arch/powerpc/cpu/mpc83xx/config.mk
+++ b/arch/powerpc/cpu/mpc83xx/config.mk
@@ -4,7 +4,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-PLATFORM_RELFLAGS += -meabi
-
-PLATFORM_CPPFLAGS += -DCONFIG_MPC83xx -DCONFIG_E300 \
-			-ffixed-r2 -msoft-float
+PLATFORM_CPPFLAGS += -DCONFIG_MPC83xx -DCONFIG_E300 -msoft-float
diff --git a/arch/powerpc/cpu/mpc83xx/cpu_init.c b/arch/powerpc/cpu/mpc83xx/cpu_init.c
index 0e9ddb8e26..00572de121 100644
--- a/arch/powerpc/cpu/mpc83xx/cpu_init.c
+++ b/arch/powerpc/cpu/mpc83xx/cpu_init.c
@@ -315,7 +315,7 @@ void cpu_init_f (volatile immap_t * im)
 #endif
 #if defined(CONFIG_USB_EHCI_FSL) && defined(CONFIG_MPC831x)
 	uint32_t temp;
-	struct usb_ehci *ehci = (struct usb_ehci *)CONFIG_SYS_FSL_USB_ADDR;
+	struct usb_ehci *ehci = (struct usb_ehci *)CONFIG_SYS_FSL_USB1_ADDR;
 
 	/* Configure interface. */
 	setbits_be32(&ehci->control, REFSEL_16MHZ | UTMI_PHY_EN);
diff --git a/arch/powerpc/cpu/mpc83xx/ecc.c b/arch/powerpc/cpu/mpc83xx/ecc.c
index 120b37ba63..985a024425 100644
--- a/arch/powerpc/cpu/mpc83xx/ecc.c
+++ b/arch/powerpc/cpu/mpc83xx/ecc.c
@@ -15,8 +15,8 @@
 void ecc_print_status(void)
 {
 	immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
-#ifdef CONFIG_FSL_DDR2
-	ccsr_ddr_t *ddr = &immap->ddr;
+#ifdef CONFIG_SYS_FSL_DDR2
+	struct ccsr_ddr __iomem *ddr = &immap->ddr;
 #else
 	ddr83xx_t *ddr = &immap->ddr;
 #endif
@@ -99,8 +99,8 @@ void ecc_print_status(void)
 int do_ecc(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
 {
 	immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
-#ifdef CONFIG_FSL_DDR2
-	ccsr_ddr_t *ddr = &immap->ddr;
+#ifdef CONFIG_SYS_FSL_DDR2
+	struct ccsr_ddr __iomem *ddr = &immap->ddr;
 #else
 	ddr83xx_t *ddr = &immap->ddr;
 #endif
diff --git a/arch/powerpc/cpu/mpc83xx/start.S b/arch/powerpc/cpu/mpc83xx/start.S
index b4fafe65ef..36724e5aa5 100644
--- a/arch/powerpc/cpu/mpc83xx/start.S
+++ b/arch/powerpc/cpu/mpc83xx/start.S
@@ -20,7 +20,6 @@
 #include <version.h>
 
 #define CONFIG_83XX	1		/* needed for Linux kernel header files*/
-#define _LINUX_CONFIG_H 1	/* avoid reading Linux autoconf.h file */
 
 #include <ppc_asm.tmpl>
 #include <ppc_defs.h>
@@ -120,6 +119,11 @@ disable_addr_trans:
 	mtspr	SRR1, r3
 	rfi
 
+	.globl get_svr
+get_svr:
+	mfspr	r3, SVR
+	blr
+
 	.globl get_pvr
 get_pvr:
 	mfspr	r3, PVR
diff --git a/arch/powerpc/cpu/mpc85xx/Makefile b/arch/powerpc/cpu/mpc85xx/Makefile
index f70f0d747d..ef7637a49c 100644
--- a/arch/powerpc/cpu/mpc85xx/Makefile
+++ b/arch/powerpc/cpu/mpc85xx/Makefile
@@ -8,10 +8,6 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(CPU).o
-
 MINIMAL=
 
 ifdef CONFIG_SPL_BUILD
@@ -20,149 +16,97 @@ MINIMAL=y
 endif
 endif
 
-START = start.o resetvec.o
+extra-y = start.o resetvec.o
 
 ifdef MINIMAL
 
-COBJS-y	+= cpu_init_early.o tlb.o spl_minimal.o
+obj-y	+= cpu_init_early.o tlb.o spl_minimal.o
 
 else
 
-SOBJS-$(CONFIG_MP)	+= release.o
-SOBJS	= $(SOBJS-y)
-
-COBJS-$(CONFIG_CMD_ERRATA) += cmd_errata.o
-COBJS-$(CONFIG_CPM2)	+= commproc.o
-
-# supports ddr1
-COBJS-$(CONFIG_MPC8540) += ddr-gen1.o
-COBJS-$(CONFIG_MPC8560) += ddr-gen1.o
-COBJS-$(CONFIG_MPC8541) += ddr-gen1.o
-COBJS-$(CONFIG_MPC8555) += ddr-gen1.o
-
-# supports ddr1/2
-COBJS-$(CONFIG_MPC8548) += ddr-gen2.o
-COBJS-$(CONFIG_MPC8568) += ddr-gen2.o
-COBJS-$(CONFIG_MPC8544) += ddr-gen2.o
-
-# supports ddr1/2/3
-COBJS-$(CONFIG_PPC_C29X)	+= ddr-gen3.o
-COBJS-$(CONFIG_MPC8572) += ddr-gen3.o
-COBJS-$(CONFIG_MPC8536) += ddr-gen3.o
-COBJS-$(CONFIG_MPC8569)	+= ddr-gen3.o
-COBJS-$(CONFIG_P1010)	+= ddr-gen3.o
-COBJS-$(CONFIG_P1011)	+= ddr-gen3.o
-COBJS-$(CONFIG_P1012)	+= ddr-gen3.o
-COBJS-$(CONFIG_P1013)	+= ddr-gen3.o
-COBJS-$(CONFIG_P1014)	+= ddr-gen3.o
-COBJS-$(CONFIG_P1020)	+= ddr-gen3.o
-COBJS-$(CONFIG_P1021)	+= ddr-gen3.o
-COBJS-$(CONFIG_P1022)	+= ddr-gen3.o
-COBJS-$(CONFIG_P1023)	+= ddr-gen3.o
-COBJS-$(CONFIG_P1024)	+= ddr-gen3.o
-COBJS-$(CONFIG_P1025)	+= ddr-gen3.o
-COBJS-$(CONFIG_P2010)	+= ddr-gen3.o
-COBJS-$(CONFIG_P2020)	+= ddr-gen3.o
-COBJS-$(CONFIG_PPC_P2041)	+= ddr-gen3.o
-COBJS-$(CONFIG_PPC_P3041)	+= ddr-gen3.o
-COBJS-$(CONFIG_PPC_P4080)	+= ddr-gen3.o
-COBJS-$(CONFIG_PPC_P5020)	+= ddr-gen3.o
-COBJS-$(CONFIG_PPC_P5040)	+= ddr-gen3.o
-COBJS-$(CONFIG_PPC_T4240)	+= ddr-gen3.o
-COBJS-$(CONFIG_PPC_T4160)	+= ddr-gen3.o
-COBJS-$(CONFIG_PPC_B4420)	+= ddr-gen3.o
-COBJS-$(CONFIG_PPC_B4860)	+= ddr-gen3.o
-COBJS-$(CONFIG_BSC9131)		+= ddr-gen3.o
-COBJS-$(CONFIG_BSC9132)		+= ddr-gen3.o
-COBJS-$(CONFIG_PPC_T1040)	+= ddr-gen3.o
-
-COBJS-$(CONFIG_CPM2)	+= ether_fcc.o
-COBJS-$(CONFIG_OF_LIBFDT) += fdt.o
-COBJS-$(CONFIG_FSL_CORENET) += liodn.o
-COBJS-$(CONFIG_MP)	+= mp.o
-COBJS-$(CONFIG_PCI)	+= pci.o
-COBJS-$(CONFIG_SYS_DPAA_QBMAN) += portals.o
+obj-$(CONFIG_MP)	+= release.o
+
+obj-$(CONFIG_CMD_ERRATA) += cmd_errata.o
+obj-$(CONFIG_CPM2)	+= commproc.o
+
+obj-$(CONFIG_CPM2)	+= ether_fcc.o
+obj-$(CONFIG_OF_LIBFDT) += fdt.o
+obj-$(CONFIG_FSL_CORENET) += liodn.o
+obj-$(CONFIG_MP)	+= mp.o
+obj-$(CONFIG_PCI)	+= pci.o
+obj-$(CONFIG_SYS_DPAA_QBMAN) += portals.o
 
 # various SoC specific assignments
-COBJS-$(CONFIG_PPC_P2041) += p2041_ids.o
-COBJS-$(CONFIG_PPC_P3041) += p3041_ids.o
-COBJS-$(CONFIG_PPC_P4080) += p4080_ids.o
-COBJS-$(CONFIG_PPC_P5020) += p5020_ids.o
-COBJS-$(CONFIG_PPC_P5040) += p5040_ids.o
-COBJS-$(CONFIG_PPC_T4240) += t4240_ids.o
-COBJS-$(CONFIG_PPC_T4160) += t4240_ids.o
-COBJS-$(CONFIG_PPC_B4420) += b4860_ids.o
-COBJS-$(CONFIG_PPC_B4860) += b4860_ids.o
-COBJS-$(CONFIG_PPC_T1040) += t1040_ids.o
-
-COBJS-$(CONFIG_QE)	+= qe_io.o
-COBJS-$(CONFIG_CPM2)	+= serial_scc.o
-COBJS-$(CONFIG_SYS_FSL_QORIQ_CHASSIS1) += fsl_corenet_serdes.o
-COBJS-$(CONFIG_SYS_FSL_QORIQ_CHASSIS2) += fsl_corenet2_serdes.o
+obj-$(CONFIG_PPC_P2041) += p2041_ids.o
+obj-$(CONFIG_PPC_P3041) += p3041_ids.o
+obj-$(CONFIG_PPC_P4080) += p4080_ids.o
+obj-$(CONFIG_PPC_P5020) += p5020_ids.o
+obj-$(CONFIG_PPC_P5040) += p5040_ids.o
+obj-$(CONFIG_PPC_T4240) += t4240_ids.o
+obj-$(CONFIG_PPC_T4160) += t4240_ids.o
+obj-$(CONFIG_PPC_B4420) += b4860_ids.o
+obj-$(CONFIG_PPC_B4860) += b4860_ids.o
+obj-$(CONFIG_PPC_T1040) += t1040_ids.o
+obj-$(CONFIG_PPC_T1042)	+= t1040_ids.o
+obj-$(CONFIG_PPC_T1020)	+= t1040_ids.o
+obj-$(CONFIG_PPC_T1022)	+= t1040_ids.o
+obj-$(CONFIG_PPC_T2080) += t2080_ids.o
+obj-$(CONFIG_PPC_T2081) += t2080_ids.o
+
+
+obj-$(CONFIG_QE)	+= qe_io.o
+obj-$(CONFIG_CPM2)	+= serial_scc.o
+obj-$(CONFIG_SYS_FSL_QORIQ_CHASSIS1) += fsl_corenet_serdes.o
+obj-$(CONFIG_SYS_FSL_QORIQ_CHASSIS2) += fsl_corenet2_serdes.o
 
 # SoC specific SERDES support
-COBJS-$(CONFIG_PPC_C29X)	+= c29x_serdes.o
-COBJS-$(CONFIG_MPC8536) += mpc8536_serdes.o
-COBJS-$(CONFIG_MPC8544) += mpc8544_serdes.o
-COBJS-$(CONFIG_MPC8548) += mpc8548_serdes.o
-COBJS-$(CONFIG_MPC8568) += mpc8568_serdes.o
-COBJS-$(CONFIG_MPC8569) += mpc8569_serdes.o
-COBJS-$(CONFIG_MPC8572) += mpc8572_serdes.o
-COBJS-$(CONFIG_P1010)	+= p1010_serdes.o
-COBJS-$(CONFIG_P1011)	+= p1021_serdes.o
-COBJS-$(CONFIG_P1012)	+= p1021_serdes.o
-COBJS-$(CONFIG_P1013)	+= p1022_serdes.o
-COBJS-$(CONFIG_P1014)	+= p1010_serdes.o
-COBJS-$(CONFIG_P1017)	+= p1023_serdes.o
-COBJS-$(CONFIG_P1020)	+= p1021_serdes.o
-COBJS-$(CONFIG_P1021)	+= p1021_serdes.o
-COBJS-$(CONFIG_P1022)	+= p1022_serdes.o
-COBJS-$(CONFIG_P1023)	+= p1023_serdes.o
-COBJS-$(CONFIG_P1024)	+= p1021_serdes.o
-COBJS-$(CONFIG_P1025)	+= p1021_serdes.o
-COBJS-$(CONFIG_P2010)	+= p2020_serdes.o
-COBJS-$(CONFIG_P2020)	+= p2020_serdes.o
-COBJS-$(CONFIG_PPC_P2041) += p2041_serdes.o
-COBJS-$(CONFIG_PPC_P3041) += p3041_serdes.o
-COBJS-$(CONFIG_PPC_P4080) += p4080_serdes.o
-COBJS-$(CONFIG_PPC_P5020) += p5020_serdes.o
-COBJS-$(CONFIG_PPC_P5040) += p5040_serdes.o
-COBJS-$(CONFIG_PPC_T4240) += t4240_serdes.o
-COBJS-$(CONFIG_PPC_T4160) += t4240_serdes.o
-COBJS-$(CONFIG_PPC_B4420) += b4860_serdes.o
-COBJS-$(CONFIG_PPC_B4860) += b4860_serdes.o
-COBJS-$(CONFIG_BSC9132) += bsc9132_serdes.o
-COBJS-$(CONFIG_PPC_T1040) += t1040_serdes.o
-
-COBJS-y	+= cpu.o
-COBJS-y	+= cpu_init.o
-COBJS-y	+= cpu_init_early.o
-COBJS-y	+= interrupts.o
-COBJS-y	+= speed.o
-COBJS-y	+= tlb.o
-COBJS-y	+= traps.o
+obj-$(CONFIG_PPC_C29X)	+= c29x_serdes.o
+obj-$(CONFIG_MPC8536) += mpc8536_serdes.o
+obj-$(CONFIG_MPC8544) += mpc8544_serdes.o
+obj-$(CONFIG_MPC8548) += mpc8548_serdes.o
+obj-$(CONFIG_MPC8568) += mpc8568_serdes.o
+obj-$(CONFIG_MPC8569) += mpc8569_serdes.o
+obj-$(CONFIG_MPC8572) += mpc8572_serdes.o
+obj-$(CONFIG_P1010)	+= p1010_serdes.o
+obj-$(CONFIG_P1011)	+= p1021_serdes.o
+obj-$(CONFIG_P1012)	+= p1021_serdes.o
+obj-$(CONFIG_P1013)	+= p1022_serdes.o
+obj-$(CONFIG_P1014)	+= p1010_serdes.o
+obj-$(CONFIG_P1017)	+= p1023_serdes.o
+obj-$(CONFIG_P1020)	+= p1021_serdes.o
+obj-$(CONFIG_P1021)	+= p1021_serdes.o
+obj-$(CONFIG_P1022)	+= p1022_serdes.o
+obj-$(CONFIG_P1023)	+= p1023_serdes.o
+obj-$(CONFIG_P1024)	+= p1021_serdes.o
+obj-$(CONFIG_P1025)	+= p1021_serdes.o
+obj-$(CONFIG_P2010)	+= p2020_serdes.o
+obj-$(CONFIG_P2020)	+= p2020_serdes.o
+obj-$(CONFIG_PPC_P2041) += p2041_serdes.o
+obj-$(CONFIG_PPC_P3041) += p3041_serdes.o
+obj-$(CONFIG_PPC_P4080) += p4080_serdes.o
+obj-$(CONFIG_PPC_P5020) += p5020_serdes.o
+obj-$(CONFIG_PPC_P5040) += p5040_serdes.o
+obj-$(CONFIG_PPC_T4240) += t4240_serdes.o
+obj-$(CONFIG_PPC_T4160) += t4240_serdes.o
+obj-$(CONFIG_PPC_B4420) += b4860_serdes.o
+obj-$(CONFIG_PPC_B4860) += b4860_serdes.o
+obj-$(CONFIG_BSC9132) += bsc9132_serdes.o
+obj-$(CONFIG_PPC_T1040) += t1040_serdes.o
+obj-$(CONFIG_PPC_T1042)	+= t1040_serdes.o
+obj-$(CONFIG_PPC_T1020)	+= t1040_serdes.o
+obj-$(CONFIG_PPC_T1022)	+= t1040_serdes.o
+obj-$(CONFIG_PPC_T2080) += t2080_serdes.o
+obj-$(CONFIG_PPC_T2081) += t2080_serdes.o
+
+obj-y	+= cpu.o
+obj-y	+= cpu_init.o
+obj-y	+= cpu_init_early.o
+obj-y	+= interrupts.o
+obj-y	+= speed.o
+obj-y	+= tlb.o
+obj-y	+= traps.o
 
 # Stub implementations of cache management functions for USB
-COBJS-y += cache.o
+obj-y += cache.o
 
 endif # not minimal
-
-COBJS	= $(COBJS-y)
-
-SRCS	:= $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS))
-START	:= $(addprefix $(obj),$(START))
-
-all:	$(obj).depend $(START) $(LIB)
-
-$(LIB):	$(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
diff --git a/arch/powerpc/cpu/mpc85xx/b4860_serdes.c b/arch/powerpc/cpu/mpc85xx/b4860_serdes.c
index 6ff6a70294..cf18be5528 100644
--- a/arch/powerpc/cpu/mpc85xx/b4860_serdes.c
+++ b/arch/powerpc/cpu/mpc85xx/b4860_serdes.c
@@ -18,12 +18,32 @@ struct serdes_config {
 #ifdef CONFIG_PPC_B4860
 static struct serdes_config serdes1_cfg_tbl[] = {
 	/* SerDes 1 */
+	{0x02, {AURORA, AURORA, CPRI6, CPRI5,
+		CPRI4, CPRI3, CPRI2, CPRI1} },
+	{0x04, {AURORA, AURORA, CPRI6, CPRI5,
+		CPRI4, CPRI3, CPRI2, CPRI1} },
+	{0x05, {AURORA, AURORA, CPRI6, CPRI5,
+		CPRI4, CPRI3, CPRI2, CPRI1} },
+	{0x06, {AURORA, AURORA, CPRI6, CPRI5,
+		CPRI4, CPRI3, CPRI2, CPRI1} },
+	{0x08, {AURORA, AURORA, CPRI6, CPRI5,
+		CPRI4, CPRI3, CPRI2, CPRI1} },
+	{0x09, {AURORA, AURORA, CPRI6, CPRI5,
+		CPRI4, CPRI3, CPRI2, CPRI1} },
+	{0x0A, {AURORA, AURORA, CPRI6, CPRI5,
+		CPRI4, CPRI3, CPRI2, CPRI1} },
+	{0x0B, {AURORA, AURORA, CPRI6, CPRI5,
+		CPRI4, CPRI3, CPRI2, CPRI1} },
+	{0x0C, {AURORA, AURORA, CPRI6, CPRI5,
+		CPRI4, CPRI3, CPRI2, CPRI1} },
 	{0x0D, {CPRI8, CPRI7, CPRI6, CPRI5,
 		CPRI4, CPRI3, CPRI2, CPRI1}},
 	{0x0E, {CPRI8, CPRI7,	CPRI6, CPRI5,
 		CPRI4, CPRI3, CPRI2, CPRI1}},
 	{0x12, {CPRI8, CPRI7,	CPRI6, CPRI5,
 		CPRI4, CPRI3, CPRI2, CPRI1}},
+	{0x29, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
+		CPRI6, CPRI5, CPRI4, CPRI3, CPRI2, CPRI1} },
 	{0x2a, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
 		CPRI6, CPRI5, CPRI4, CPRI3, CPRI2, CPRI1}},
 	{0x2C, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
@@ -32,6 +52,9 @@ static struct serdes_config serdes1_cfg_tbl[] = {
 		CPRI6, CPRI5, CPRI4, CPRI3, CPRI2, CPRI1}},
 	{0x2E, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
 		CPRI6, CPRI5, CPRI4, CPRI3, CPRI2, CPRI1}},
+	{0x2F, {AURORA, AURORA,
+		SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
+		CPRI4, CPRI3, CPRI2, CPRI1} },
 	{0x30, {AURORA, AURORA,
 		SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
 		CPRI4, CPRI3, CPRI2, CPRI1}},
@@ -44,18 +67,38 @@ static struct serdes_config serdes1_cfg_tbl[] = {
 	{0x34, {AURORA, AURORA,
 		SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
 		CPRI4, CPRI3, CPRI2, CPRI1}},
+	{0x39, {AURORA, AURORA, CPRI6, CPRI5,
+		CPRI4, CPRI3, CPRI2, CPRI1} },
+	{0x3A, {AURORA, AURORA, CPRI6, CPRI5,
+		CPRI4, CPRI3, CPRI2, CPRI1} },
+	{0x3C, {AURORA, AURORA, CPRI6, CPRI5,
+		CPRI4, CPRI3, CPRI2, CPRI1} },
+	{0x3D, {AURORA, AURORA, CPRI6, CPRI5,
+		CPRI4, CPRI3, CPRI2, CPRI1} },
 	{0x3E, {CPRI8, CPRI7,	CPRI6, CPRI5,
 		CPRI4, CPRI3, CPRI2, CPRI1}},
+	{0x5C, {AURORA, AURORA,
+		SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
+		CPRI4, CPRI3, CPRI2, CPRI1} },
+	{0x5D, {AURORA, AURORA,
+		SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
+		CPRI4, CPRI3, CPRI2, CPRI1} },
 	{}
 };
 static struct serdes_config serdes2_cfg_tbl[] = {
 	/* SerDes 2 */
+	{0x17, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
+		SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
+		AURORA, AURORA,	SRIO1, SRIO1} },
 	{0x18, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
 		SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
 		AURORA, AURORA,	SRIO1, SRIO1}},
 	{0x1D, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
 		SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
 		AURORA, AURORA,	SRIO1, SRIO1}},
+	{0x2A, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
+		SRIO2, SRIO2,
+		AURORA, AURORA, SRIO1, SRIO1} },
 	{0x2B, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
 		SRIO2, SRIO2,
 		AURORA, AURORA, SRIO1, SRIO1}},
@@ -63,6 +106,9 @@ static struct serdes_config serdes2_cfg_tbl[] = {
 		SRIO2, SRIO2,
 		AURORA, AURORA,
 		SRIO1, SRIO1}},
+	{0x48, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
+		SGMII_FM1_DTSEC3, AURORA,
+		SRIO1, SRIO1, SRIO1, SRIO1} },
 	{0x49, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
 		SGMII_FM1_DTSEC3, AURORA,
 		SRIO1, SRIO1, SRIO1, SRIO1}},
@@ -75,18 +121,30 @@ static struct serdes_config serdes2_cfg_tbl[] = {
 	{0x4E, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
 		SGMII_FM1_DTSEC3, AURORA,
 		SRIO1, SRIO1, SRIO1, SRIO1}},
+	{0x79, {SRIO2, SRIO2, SRIO2, SRIO2,
+		SRIO1, SRIO1, SRIO1, SRIO1} },
 	{0x7A, {SRIO2, SRIO2, SRIO2, SRIO2,
 		SRIO1, SRIO1, SRIO1, SRIO1}},
+	{0x83, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
+		SRIO2, SRIO2, AURORA, AURORA,
+		XFI_FM1_MAC9, XFI_FM1_MAC10} },
 	{0x84, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
 		SRIO2, SRIO2, AURORA, AURORA,
 		XFI_FM1_MAC9, XFI_FM1_MAC10}},
 	{0x85, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
 		SRIO2, SRIO2, AURORA, AURORA,
 		XFI_FM1_MAC9, XFI_FM1_MAC10}},
+	{0x86, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
+		SRIO2, SRIO2,
+		SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
+		XFI_FM1_MAC9, XFI_FM1_MAC10} },
 	{0x87, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
 		SRIO2, SRIO2,
 		SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
 		XFI_FM1_MAC9, XFI_FM1_MAC10}},
+	{0x8C, {SRIO2, SRIO2, SRIO2, SRIO2,
+		SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
+		XFI_FM1_MAC9, XFI_FM1_MAC10} },
 	{0x8D, {SRIO2, SRIO2, SRIO2, SRIO2,
 		SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
 		XFI_FM1_MAC9, XFI_FM1_MAC10}},
@@ -101,6 +159,9 @@ static struct serdes_config serdes2_cfg_tbl[] = {
 		SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
 		XAUI_FM1_MAC10, XAUI_FM1_MAC10,
 		XAUI_FM1_MAC10, XAUI_FM1_MAC10}},
+	{0xB1, {PCIE1, PCIE1, PCIE1, PCIE1,
+		SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
+		XFI_FM1_MAC9, XFI_FM1_MAC10} },
 	{0xB2, {PCIE1, PCIE1, PCIE1, PCIE1,
 		SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
 		XFI_FM1_MAC9, XFI_FM1_MAC10}},
diff --git a/arch/powerpc/cpu/mpc85xx/cmd_errata.c b/arch/powerpc/cpu/mpc85xx/cmd_errata.c
index c441bd2f54..8b79c05b1f 100644
--- a/arch/powerpc/cpu/mpc85xx/cmd_errata.c
+++ b/arch/powerpc/cpu/mpc85xx/cmd_errata.c
@@ -7,6 +7,7 @@
 #include <common.h>
 #include <command.h>
 #include <linux/compiler.h>
+#include <asm/fsl_errata.h>
 #include <asm/processor.h>
 #include "fsl_corenet_serdes.h"
 
@@ -155,7 +156,7 @@ static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 	puts("Work-around for Erratum CPU-A003999 enabled\n");
 #endif
 #if defined(CONFIG_SYS_FSL_ERRATUM_DDR_A003474)
-	puts("Work-around for Erratum DDR-A003473 enabled\n");
+	puts("Work-around for Erratum DDR-A003474 enabled\n");
 #endif
 #if defined(CONFIG_SYS_FSL_ERRATUM_DDR_MSYNC_IN)
 	puts("Work-around for DDR MSYNC_IN Erratum enabled\n");
@@ -228,6 +229,14 @@ static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 	if (IS_SVR_REV(svr, 1, 0))
 		puts("Work-around for Erratum A005871 enabled\n");
 #endif
+#ifdef CONFIG_SYS_FSL_ERRATUM_A006475
+	if (SVR_MAJ(get_svr()) == 1)
+		puts("Work-around for Erratum A006475 enabled\n");
+#endif
+#ifdef CONFIG_SYS_FSL_ERRATUM_A006384
+	if (SVR_MAJ(get_svr()) == 1)
+		puts("Work-around for Erratum A006384 enabled\n");
+#endif
 #ifdef CONFIG_SYS_FSL_ERRATUM_A004849
 	/* This work-around is implemented in PBI, so just check for it */
 	check_erratum_a4849(svr);
@@ -245,6 +254,10 @@ static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 #ifdef CONFIG_SYS_FSL_ERRATUM_A006593
 	puts("Work-around for Erratum A006593 enabled\n");
 #endif
+#ifdef CONFIG_SYS_FSL_ERRATUM_A006379
+	if (has_erratum_a006379())
+		puts("Work-around for Erratum A006379 enabled\n");
+#endif
 #ifdef CONFIG_SYS_FSL_ERRATUM_SEC_A003571
 	if (IS_SVR_REV(svr, 1, 0))
 		puts("Work-around for Erratum A003571 enabled\n");
@@ -260,6 +273,10 @@ static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 	    (SVR_REV(svr) <= CONFIG_SYS_FSL_A004447_SVR_REV))
 		puts("Work-around for Erratum I2C-A004447 enabled\n");
 #endif
+#ifdef CONFIG_SYS_FSL_ERRATUM_A006261
+	if (has_erratum_a006261())
+		puts("Work-around for Erratum A006261 enabled\n");
+#endif
 	return 0;
 }
 
diff --git a/arch/powerpc/cpu/mpc85xx/config.mk b/arch/powerpc/cpu/mpc85xx/config.mk
index 9eef539e5e..1470f95ff1 100644
--- a/arch/powerpc/cpu/mpc85xx/config.mk
+++ b/arch/powerpc/cpu/mpc85xx/config.mk
@@ -5,13 +5,10 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-PLATFORM_RELFLAGS += -meabi
-
-PLATFORM_CPPFLAGS += -ffixed-r2 -Wa,-me500 -msoft-float -mno-string
+PLATFORM_CPPFLAGS += -DCONFIG_MPC85xx -Wa,-me500 -msoft-float -mno-string
 
 # -mspe=yes is needed to have -mno-spe accepted by a buggy GCC;
 # see "[PATCH,rs6000] make -mno-spe work as expected" on
 # http://gcc.gnu.org/ml/gcc-patches/2008-04/msg00311.html
-PF_CPPFLAGS_SPE := $(call cc-option,-mspe=yes) \
+PLATFORM_CPPFLAGS += $(call cc-option,-mspe=yes) \
 		   $(call cc-option,-mno-spe)
-PLATFORM_CPPFLAGS += $(PF_CPPFLAGS_SPE)
diff --git a/arch/powerpc/cpu/mpc85xx/cpu.c b/arch/powerpc/cpu/mpc85xx/cpu.c
index 1a0196c7c4..3e99b079c7 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu.c
@@ -17,12 +17,12 @@
 #include <asm/cache.h>
 #include <asm/io.h>
 #include <asm/mmu.h>
-#include <asm/fsl_ifc.h>
+#include <fsl_ifc.h>
 #include <asm/fsl_law.h>
 #include <asm/fsl_lbc.h>
 #include <post.h>
 #include <asm/processor.h>
-#include <asm/fsl_ddr_sdram.h>
+#include <fsl_ddr_sdram.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -416,7 +416,7 @@ static void dump_spd_ddr_reg(void)
 	int i, j, k, m;
 	u8 *p_8;
 	u32 *p_32;
-	ccsr_ddr_t *ddr[CONFIG_NUM_DDR_CONTROLLERS];
+	struct ccsr_ddr __iomem *ddr[CONFIG_NUM_DDR_CONTROLLERS];
 	generic_spd_eeprom_t
 		spd[CONFIG_NUM_DDR_CONTROLLERS][CONFIG_DIMM_SLOTS_PER_CTLR];
 
@@ -453,21 +453,21 @@ static void dump_spd_ddr_reg(void)
 	for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
 		switch (i) {
 		case 0:
-			ddr[i] = (void *)CONFIG_SYS_MPC8xxx_DDR_ADDR;
+			ddr[i] = (void *)CONFIG_SYS_FSL_DDR_ADDR;
 			break;
-#if defined(CONFIG_SYS_MPC8xxx_DDR2_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 1)
+#if defined(CONFIG_SYS_FSL_DDR2_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 1)
 		case 1:
-			ddr[i] = (void *)CONFIG_SYS_MPC8xxx_DDR2_ADDR;
+			ddr[i] = (void *)CONFIG_SYS_FSL_DDR2_ADDR;
 			break;
 #endif
-#if defined(CONFIG_SYS_MPC8xxx_DDR3_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 2)
+#if defined(CONFIG_SYS_FSL_DDR3_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 2)
 		case 2:
-			ddr[i] = (void *)CONFIG_SYS_MPC8xxx_DDR3_ADDR;
+			ddr[i] = (void *)CONFIG_SYS_FSL_DDR3_ADDR;
 			break;
 #endif
-#if defined(CONFIG_SYS_MPC8xxx_DDR4_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 3)
+#if defined(CONFIG_SYS_FSL_DDR4_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 3)
 		case 3:
-			ddr[i] = (void *)CONFIG_SYS_MPC8xxx_DDR4_ADDR;
+			ddr[i] = (void *)CONFIG_SYS_FSL_DDR4_ADDR;
 			break;
 #endif
 		default:
@@ -482,7 +482,7 @@ static void dump_spd_ddr_reg(void)
 	for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++)
 		printf("     Base + 0x%04x", (u32)ddr[i] & 0xFFFF);
 	puts("\n");
-	for (k = 0; k < sizeof(ccsr_ddr_t)/4; k++) {
+	for (k = 0; k < sizeof(struct ccsr_ddr)/4; k++) {
 		m = 0;
 		printf("%6d (0x%04x)", k * 4, k * 4);
 		for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c
index 6036333eaa..81aeadd363 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu_init.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c
@@ -19,6 +19,7 @@
 #include <asm/io.h>
 #include <asm/cache.h>
 #include <asm/mmu.h>
+#include <asm/fsl_errata.h>
 #include <asm/fsl_law.h>
 #include <asm/fsl_serdes.h>
 #include <asm/fsl_srio.h>
@@ -35,6 +36,54 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
+#ifdef CONFIG_SYS_FSL_ERRATUM_A006261
+void fsl_erratum_a006261_workaround(struct ccsr_usb_phy __iomem *usb_phy)
+{
+#ifdef CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE
+	u32 xcvrprg = in_be32(&usb_phy->port1.xcvrprg);
+
+	/* Increase Disconnect Threshold by 50mV */
+	xcvrprg &= ~CONFIG_SYS_FSL_USB_XCVRPRG_HS_DCNT_PROG_MASK |
+						INC_DCNT_THRESHOLD_50MV;
+	/* Enable programming of USB High speed Disconnect threshold */
+	xcvrprg |= CONFIG_SYS_FSL_USB_XCVRPRG_HS_DCNT_PROG_EN;
+	out_be32(&usb_phy->port1.xcvrprg, xcvrprg);
+
+	xcvrprg = in_be32(&usb_phy->port2.xcvrprg);
+	/* Increase Disconnect Threshold by 50mV */
+	xcvrprg &= ~CONFIG_SYS_FSL_USB_XCVRPRG_HS_DCNT_PROG_MASK |
+						INC_DCNT_THRESHOLD_50MV;
+	/* Enable programming of USB High speed Disconnect threshold */
+	xcvrprg |= CONFIG_SYS_FSL_USB_XCVRPRG_HS_DCNT_PROG_EN;
+	out_be32(&usb_phy->port2.xcvrprg, xcvrprg);
+#else
+
+	u32 temp = 0;
+	u32 status = in_be32(&usb_phy->status1);
+
+	u32 squelch_prog_rd_0_2 =
+		(status >> CONFIG_SYS_FSL_USB_SQUELCH_PROG_RD_0)
+			& CONFIG_SYS_FSL_USB_SQUELCH_PROG_MASK;
+
+	u32 squelch_prog_rd_3_5 =
+		(status >> CONFIG_SYS_FSL_USB_SQUELCH_PROG_RD_3)
+			& CONFIG_SYS_FSL_USB_SQUELCH_PROG_MASK;
+
+	setbits_be32(&usb_phy->config1,
+		     CONFIG_SYS_FSL_USB_HS_DISCNCT_INC);
+	setbits_be32(&usb_phy->config2,
+		     CONFIG_SYS_FSL_USB_RX_AUTO_CAL_RD_WR_SEL);
+
+	temp = squelch_prog_rd_0_2 << CONFIG_SYS_FSL_USB_SQUELCH_PROG_WR_0;
+	out_be32(&usb_phy->config2, in_be32(&usb_phy->config2) | temp);
+
+	temp = squelch_prog_rd_3_5 << CONFIG_SYS_FSL_USB_SQUELCH_PROG_WR_3;
+	out_be32(&usb_phy->config2, in_be32(&usb_phy->config2) | temp);
+#endif
+}
+#endif
+
+
 #ifdef CONFIG_QE
 extern qe_iop_conf_t qe_iop_conf_tab[];
 extern void qe_config_iopin(u8 port, u8 pin, int dir,
@@ -160,6 +209,12 @@ static void enable_cpc(void)
 #ifdef CONFIG_SYS_FSL_ERRATUM_A006593
 		setbits_be32(&cpc->cpchdbcr0, 1 << (31 - 21));
 #endif
+#ifdef CONFIG_SYS_FSL_ERRATUM_A006379
+		if (has_erratum_a006379()) {
+			setbits_be32(&cpc->cpchdbcr0,
+				     CPC_HDBCR0_SPLRU_LEVEL_EN);
+		}
+#endif
 
 		out_be32(&cpc->cpccsr0, CPC_CSR0_CE | CPC_CSR0_PE);
 		/* Read back to sync write */
@@ -284,7 +339,7 @@ static void __fsl_serdes__init(void)
 }
 __attribute__((weak, alias("__fsl_serdes__init"))) void fsl_serdes_init(void);
 
-#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
+#if defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && defined(CONFIG_E6500)
 int enable_cluster_l2(void)
 {
 	int i = 0;
@@ -350,7 +405,7 @@ int cpu_init_r(void)
 #endif
 #ifdef CONFIG_L2_CACHE
 	ccsr_l2cache_t *l2cache = (void __iomem *)CONFIG_SYS_MPC85xx_L2_ADDR;
-#elif defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2)
+#elif defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && defined(CONFIG_E6500)
 	struct ccsr_cluster_l2 * l2cache = (void __iomem *)CONFIG_SYS_FSL_CLUSTER_1_L2;
 #endif
 #if defined(CONFIG_PPC_SPINTABLE_COMPATIBLE) && defined(CONFIG_MP)
@@ -533,7 +588,7 @@ int cpu_init_r(void)
 	}
 
 skip_l2:
-#elif defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2)
+#elif defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && defined(CONFIG_E6500)
 	if (l2cache->l2csr0 & L2CSR0_L2E)
 		print_size((l2cache->l2cfg0 & 0x3fff) * 64 * 1024,
 			   " enabled\n");
@@ -618,6 +673,10 @@ skip_l2:
 	{
 		struct ccsr_usb_phy __iomem *usb_phy1 =
 			(void *)CONFIG_SYS_MPC85xx_USB1_PHY_ADDR;
+#ifdef CONFIG_SYS_FSL_ERRATUM_A006261
+		if (has_erratum_a006261())
+			fsl_erratum_a006261_workaround(usb_phy1);
+#endif
 		out_be32(&usb_phy1->usb_enable_override,
 				CONFIG_SYS_FSL_USB_ENABLE_OVERRIDE);
 	}
@@ -626,6 +685,10 @@ skip_l2:
 	{
 		struct ccsr_usb_phy __iomem *usb_phy2 =
 			(void *)CONFIG_SYS_MPC85xx_USB2_PHY_ADDR;
+#ifdef CONFIG_SYS_FSL_ERRATUM_A006261
+		if (has_erratum_a006261())
+			fsl_erratum_a006261_workaround(usb_phy2);
+#endif
 		out_be32(&usb_phy2->usb_enable_override,
 				CONFIG_SYS_FSL_USB_ENABLE_OVERRIDE);
 	}
@@ -665,8 +728,14 @@ skip_l2:
 			     CONFIG_SYS_FSL_USB_DRVVBUS_CR_EN);
 		setbits_be32(&usb_phy->port2.pwrfltcfg,
 			     CONFIG_SYS_FSL_USB_PWRFLT_CR_EN);
+
+#ifdef CONFIG_SYS_FSL_ERRATUM_A006261
+		if (has_erratum_a006261())
+			fsl_erratum_a006261_workaround(usb_phy);
 #endif
 
+#endif /* CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE */
+
 #ifdef CONFIG_FMAN_ENET
 	fman_enet_init();
 #endif
diff --git a/arch/powerpc/cpu/mpc85xx/ddr-gen1.c b/arch/powerpc/cpu/mpc85xx/ddr-gen1.c
deleted file mode 100644
index 4dd8c0b5bf..0000000000
--- a/arch/powerpc/cpu/mpc85xx/ddr-gen1.c
+++ /dev/null
@@ -1,89 +0,0 @@
-/*
- * Copyright 2008 Freescale Semiconductor, Inc.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * Version 2 as published by the Free Software Foundation.
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/fsl_ddr_sdram.h>
-
-#if (CONFIG_CHIP_SELECTS_PER_CTRL > 4)
-#error Invalid setting for CONFIG_CHIP_SELECTS_PER_CTRL
-#endif
-
-void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
-			     unsigned int ctrl_num, int step)
-{
-	unsigned int i;
-	volatile ccsr_ddr_t *ddr = (void *)CONFIG_SYS_MPC8xxx_DDR_ADDR;
-
-	if (ctrl_num != 0) {
-		printf("%s unexpected ctrl_num = %u\n", __FUNCTION__, ctrl_num);
-		return;
-	}
-
-	for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
-		if (i == 0) {
-			out_be32(&ddr->cs0_bnds, regs->cs[i].bnds);
-			out_be32(&ddr->cs0_config, regs->cs[i].config);
-
-		} else if (i == 1) {
-			out_be32(&ddr->cs1_bnds, regs->cs[i].bnds);
-			out_be32(&ddr->cs1_config, regs->cs[i].config);
-
-		} else if (i == 2) {
-			out_be32(&ddr->cs2_bnds, regs->cs[i].bnds);
-			out_be32(&ddr->cs2_config, regs->cs[i].config);
-
-		} else if (i == 3) {
-			out_be32(&ddr->cs3_bnds, regs->cs[i].bnds);
-			out_be32(&ddr->cs3_config, regs->cs[i].config);
-		}
-	}
-
-	out_be32(&ddr->timing_cfg_1, regs->timing_cfg_1);
-	out_be32(&ddr->timing_cfg_2, regs->timing_cfg_2);
-	out_be32(&ddr->sdram_mode, regs->ddr_sdram_mode);
-	out_be32(&ddr->sdram_interval, regs->ddr_sdram_interval);
-#if defined(CONFIG_MPC8555) || defined(CONFIG_MPC8541)
-	out_be32(&ddr->sdram_clk_cntl, regs->ddr_sdram_clk_cntl);
-#endif
-
-	/*
-	 * 200 painful micro-seconds must elapse between
-	 * the DDR clock setup and the DDR config enable.
-	 */
-	udelay(200);
-	asm volatile("sync;isync");
-
-	out_be32(&ddr->sdram_cfg, regs->ddr_sdram_cfg);
-
-	asm("sync;isync;msync");
-	udelay(500);
-}
-
-#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
-/*
- * Initialize all of memory for ECC, then enable errors.
- */
-
-void
-ddr_enable_ecc(unsigned int dram_size)
-{
-	volatile ccsr_ddr_t *ddr= (void *)(CONFIG_SYS_MPC8xxx_DDR_ADDR);
-
-	dma_meminit(CONFIG_MEM_INIT_VALUE, dram_size);
-
-	/*
-	 * Enable errors for ECC.
-	 */
-	debug("DMA DDR: err_disable = 0x%08x\n", ddr->err_disable);
-	ddr->err_disable = 0x00000000;
-	asm("sync;isync;msync");
-	debug("DMA DDR: err_disable = 0x%08x\n", ddr->err_disable);
-}
-
-#endif	/* CONFIG_DDR_ECC  && ! CONFIG_ECC_INIT_VIA_DDRCONTROLLER */
diff --git a/arch/powerpc/cpu/mpc85xx/ddr-gen2.c b/arch/powerpc/cpu/mpc85xx/ddr-gen2.c
deleted file mode 100644
index 542bc84acf..0000000000
--- a/arch/powerpc/cpu/mpc85xx/ddr-gen2.c
+++ /dev/null
@@ -1,95 +0,0 @@
-/*
- * Copyright 2008-2011 Freescale Semiconductor, Inc.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * Version 2 as published by the Free Software Foundation.
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/processor.h>
-#include <asm/fsl_ddr_sdram.h>
-
-#if (CONFIG_CHIP_SELECTS_PER_CTRL > 4)
-#error Invalid setting for CONFIG_CHIP_SELECTS_PER_CTRL
-#endif
-
-void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
-			     unsigned int ctrl_num, int step)
-{
-	unsigned int i;
-	ccsr_ddr_t *ddr = (void *)CONFIG_SYS_MPC8xxx_DDR_ADDR;
-
-#if defined(CONFIG_SYS_FSL_ERRATUM_NMG_DDR120) && defined(CONFIG_MPC85xx)
-	ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
-	uint svr;
-#endif
-
-	if (ctrl_num) {
-		printf("%s unexpected ctrl_num = %u\n", __FUNCTION__, ctrl_num);
-		return;
-	}
-
-#ifdef CONFIG_SYS_FSL_ERRATUM_NMG_DDR120
-	/*
-	 * Set the DDR IO receiver to an acceptable bias point.
-	 * Fixed in Rev 2.1.
-	 */
-	svr = get_svr();
-	if ((SVR_MAJ(svr) == 1) || IS_SVR_REV(svr, 2, 0)) {
-		if ((regs->ddr_sdram_cfg & SDRAM_CFG_SDRAM_TYPE_MASK) ==
-		   SDRAM_CFG_SDRAM_TYPE_DDR2)
-			out_be32(&gur->ddrioovcr, 0x90000000);
-		else
-			out_be32(&gur->ddrioovcr, 0xA8000000);
-	}
-#endif
-
-	for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
-		if (i == 0) {
-			out_be32(&ddr->cs0_bnds, regs->cs[i].bnds);
-			out_be32(&ddr->cs0_config, regs->cs[i].config);
-
-		} else if (i == 1) {
-			out_be32(&ddr->cs1_bnds, regs->cs[i].bnds);
-			out_be32(&ddr->cs1_config, regs->cs[i].config);
-
-		} else if (i == 2) {
-			out_be32(&ddr->cs2_bnds, regs->cs[i].bnds);
-			out_be32(&ddr->cs2_config, regs->cs[i].config);
-
-		} else if (i == 3) {
-			out_be32(&ddr->cs3_bnds, regs->cs[i].bnds);
-			out_be32(&ddr->cs3_config, regs->cs[i].config);
-		}
-	}
-
-	out_be32(&ddr->timing_cfg_3, regs->timing_cfg_3);
-	out_be32(&ddr->timing_cfg_0, regs->timing_cfg_0);
-	out_be32(&ddr->timing_cfg_1, regs->timing_cfg_1);
-	out_be32(&ddr->timing_cfg_2, regs->timing_cfg_2);
-	out_be32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2);
-	out_be32(&ddr->sdram_mode, regs->ddr_sdram_mode);
-	out_be32(&ddr->sdram_mode_2, regs->ddr_sdram_mode_2);
-	out_be32(&ddr->sdram_md_cntl, regs->ddr_sdram_md_cntl);
-	out_be32(&ddr->sdram_interval, regs->ddr_sdram_interval);
-	out_be32(&ddr->sdram_data_init, regs->ddr_data_init);
-	out_be32(&ddr->sdram_clk_cntl, regs->ddr_sdram_clk_cntl);
-	out_be32(&ddr->init_addr, regs->ddr_init_addr);
-	out_be32(&ddr->init_ext_addr, regs->ddr_init_ext_addr);
-
-	/*
-	 * 200 painful micro-seconds must elapse between
-	 * the DDR clock setup and the DDR config enable.
-	 */
-	udelay(200);
-	asm volatile("sync;isync");
-
-	out_be32(&ddr->sdram_cfg, regs->ddr_sdram_cfg);
-
-	/* Poll DDR_SDRAM_CFG_2[D_INIT] bit until auto-data init is done.  */
-	while (in_be32(&ddr->sdram_cfg_2) & 0x10) {
-		udelay(10000);		/* throttle polling rate */
-	}
-}
diff --git a/arch/powerpc/cpu/mpc85xx/ddr-gen3.c b/arch/powerpc/cpu/mpc85xx/ddr-gen3.c
deleted file mode 100644
index 1be51d3307..0000000000
--- a/arch/powerpc/cpu/mpc85xx/ddr-gen3.c
+++ /dev/null
@@ -1,464 +0,0 @@
-/*
- * Copyright 2008-2012 Freescale Semiconductor, Inc.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * Version 2 as published by the Free Software Foundation.
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/fsl_ddr_sdram.h>
-#include <asm/processor.h>
-
-#if (CONFIG_CHIP_SELECTS_PER_CTRL > 4)
-#error Invalid setting for CONFIG_CHIP_SELECTS_PER_CTRL
-#endif
-
-
-/*
- * regs has the to-be-set values for DDR controller registers
- * ctrl_num is the DDR controller number
- * step: 0 goes through the initialization in one pass
- *       1 sets registers and returns before enabling controller
- *       2 resumes from step 1 and continues to initialize
- * Dividing the initialization to two steps to deassert DDR reset signal
- * to comply with JEDEC specs for RDIMMs.
- */
-void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
-			     unsigned int ctrl_num, int step)
-{
-	unsigned int i, bus_width;
-	volatile ccsr_ddr_t *ddr;
-	u32 temp_sdram_cfg;
-	u32 total_gb_size_per_controller;
-	int timeout;
-#ifdef CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134
-	int timeout_save;
-	volatile ccsr_local_ecm_t *ecm = (void *)CONFIG_SYS_MPC85xx_ECM_ADDR;
-	unsigned int csn_bnds_backup = 0, cs_sa, cs_ea, *csn_bnds_t;
-	int csn = -1;
-#endif
-
-	switch (ctrl_num) {
-	case 0:
-		ddr = (void *)CONFIG_SYS_MPC8xxx_DDR_ADDR;
-		break;
-#if defined(CONFIG_SYS_MPC8xxx_DDR2_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 1)
-	case 1:
-		ddr = (void *)CONFIG_SYS_MPC8xxx_DDR2_ADDR;
-		break;
-#endif
-#if defined(CONFIG_SYS_MPC8xxx_DDR3_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 2)
-	case 2:
-		ddr = (void *)CONFIG_SYS_MPC8xxx_DDR3_ADDR;
-		break;
-#endif
-#if defined(CONFIG_SYS_MPC8xxx_DDR4_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 3)
-	case 3:
-		ddr = (void *)CONFIG_SYS_MPC8xxx_DDR4_ADDR;
-		break;
-#endif
-	default:
-		printf("%s unexpected ctrl_num = %u\n", __FUNCTION__, ctrl_num);
-		return;
-	}
-
-	if (step == 2)
-		goto step2;
-
-	if (regs->ddr_eor)
-		out_be32(&ddr->eor, regs->ddr_eor);
-#ifdef CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134
-	debug("Workaround for ERRATUM_DDR111_DDR134\n");
-	for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
-		cs_sa = (regs->cs[i].bnds >> 16) & 0xfff;
-		cs_ea = regs->cs[i].bnds & 0xfff;
-		if ((cs_sa <= 0xff) && (cs_ea >= 0xff)) {
-			csn = i;
-			csn_bnds_backup = regs->cs[i].bnds;
-			csn_bnds_t = (unsigned int *) &regs->cs[i].bnds;
-			if (cs_ea > 0xeff)
-				*csn_bnds_t = regs->cs[i].bnds + 0x01000000;
-			else
-				*csn_bnds_t = regs->cs[i].bnds + 0x01000100;
-			debug("Found cs%d_bns (0x%08x) covering 0xff000000, "
-				"change it to 0x%x\n",
-				csn, csn_bnds_backup, regs->cs[i].bnds);
-			break;
-		}
-	}
-#endif
-	for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
-		if (i == 0) {
-			out_be32(&ddr->cs0_bnds, regs->cs[i].bnds);
-			out_be32(&ddr->cs0_config, regs->cs[i].config);
-			out_be32(&ddr->cs0_config_2, regs->cs[i].config_2);
-
-		} else if (i == 1) {
-			out_be32(&ddr->cs1_bnds, regs->cs[i].bnds);
-			out_be32(&ddr->cs1_config, regs->cs[i].config);
-			out_be32(&ddr->cs1_config_2, regs->cs[i].config_2);
-
-		} else if (i == 2) {
-			out_be32(&ddr->cs2_bnds, regs->cs[i].bnds);
-			out_be32(&ddr->cs2_config, regs->cs[i].config);
-			out_be32(&ddr->cs2_config_2, regs->cs[i].config_2);
-
-		} else if (i == 3) {
-			out_be32(&ddr->cs3_bnds, regs->cs[i].bnds);
-			out_be32(&ddr->cs3_config, regs->cs[i].config);
-			out_be32(&ddr->cs3_config_2, regs->cs[i].config_2);
-		}
-	}
-
-	out_be32(&ddr->timing_cfg_3, regs->timing_cfg_3);
-	out_be32(&ddr->timing_cfg_0, regs->timing_cfg_0);
-	out_be32(&ddr->timing_cfg_1, regs->timing_cfg_1);
-	out_be32(&ddr->timing_cfg_2, regs->timing_cfg_2);
-	out_be32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2);
-	out_be32(&ddr->sdram_mode, regs->ddr_sdram_mode);
-	out_be32(&ddr->sdram_mode_2, regs->ddr_sdram_mode_2);
-	out_be32(&ddr->sdram_mode_3, regs->ddr_sdram_mode_3);
-	out_be32(&ddr->sdram_mode_4, regs->ddr_sdram_mode_4);
-	out_be32(&ddr->sdram_mode_5, regs->ddr_sdram_mode_5);
-	out_be32(&ddr->sdram_mode_6, regs->ddr_sdram_mode_6);
-	out_be32(&ddr->sdram_mode_7, regs->ddr_sdram_mode_7);
-	out_be32(&ddr->sdram_mode_8, regs->ddr_sdram_mode_8);
-	out_be32(&ddr->sdram_md_cntl, regs->ddr_sdram_md_cntl);
-	out_be32(&ddr->sdram_interval, regs->ddr_sdram_interval);
-	out_be32(&ddr->sdram_data_init, regs->ddr_data_init);
-	out_be32(&ddr->sdram_clk_cntl, regs->ddr_sdram_clk_cntl);
-	out_be32(&ddr->init_addr, regs->ddr_init_addr);
-	out_be32(&ddr->init_ext_addr, regs->ddr_init_ext_addr);
-
-	out_be32(&ddr->timing_cfg_4, regs->timing_cfg_4);
-	out_be32(&ddr->timing_cfg_5, regs->timing_cfg_5);
-	out_be32(&ddr->ddr_zq_cntl, regs->ddr_zq_cntl);
-	out_be32(&ddr->ddr_wrlvl_cntl, regs->ddr_wrlvl_cntl);
-#ifndef CONFIG_SYS_FSL_DDR_EMU
-	/*
-	 * Skip these two registers if running on emulator
-	 * because emulator doesn't have skew between bytes.
-	 */
-
-	if (regs->ddr_wrlvl_cntl_2)
-		out_be32(&ddr->ddr_wrlvl_cntl_2, regs->ddr_wrlvl_cntl_2);
-	if (regs->ddr_wrlvl_cntl_3)
-		out_be32(&ddr->ddr_wrlvl_cntl_3, regs->ddr_wrlvl_cntl_3);
-#endif
-
-	out_be32(&ddr->ddr_sr_cntr, regs->ddr_sr_cntr);
-	out_be32(&ddr->ddr_sdram_rcw_1, regs->ddr_sdram_rcw_1);
-	out_be32(&ddr->ddr_sdram_rcw_2, regs->ddr_sdram_rcw_2);
-	out_be32(&ddr->ddr_cdr1, regs->ddr_cdr1);
-	out_be32(&ddr->ddr_cdr2, regs->ddr_cdr2);
-	out_be32(&ddr->err_disable, regs->err_disable);
-	out_be32(&ddr->err_int_en, regs->err_int_en);
-	for (i = 0; i < 32; i++) {
-		if (regs->debug[i]) {
-			debug("Write to debug_%d as %08x\n", i+1, regs->debug[i]);
-			out_be32(&ddr->debug[i], regs->debug[i]);
-		}
-	}
-#ifdef CONFIG_SYS_FSL_ERRATUM_A_004934
-	out_be32(&ddr->debug[28], 0x30003000);
-#endif
-
-#ifdef CONFIG_SYS_FSL_ERRATUM_DDR_A003474
-	out_be32(&ddr->debug[12], 0x00000015);
-	out_be32(&ddr->debug[21], 0x24000000);
-#endif /* CONFIG_SYS_FSL_ERRATUM_DDR_A003474 */
-
-	/*
-	 * For RDIMMs, JEDEC spec requires clocks to be stable before reset is
-	 * deasserted. Clocks start when any chip select is enabled and clock
-	 * control register is set. Because all DDR components are connected to
-	 * one reset signal, this needs to be done in two steps. Step 1 is to
-	 * get the clocks started. Step 2 resumes after reset signal is
-	 * deasserted.
-	 */
-	if (step == 1) {
-		udelay(200);
-		return;
-	}
-
-step2:
-	/* Set, but do not enable the memory */
-	temp_sdram_cfg = regs->ddr_sdram_cfg;
-	temp_sdram_cfg &= ~(SDRAM_CFG_MEM_EN);
-	out_be32(&ddr->sdram_cfg, temp_sdram_cfg);
-#ifdef CONFIG_SYS_FSL_ERRATUM_DDR_A003
-	debug("Workaround for ERRATUM_DDR_A003\n");
-	if (regs->ddr_sdram_rcw_2 & 0x00f00000) {
-		out_be32(&ddr->timing_cfg_2, regs->timing_cfg_2 & 0xf07fffff);
-		out_be32(&ddr->debug[2], 0x00000400);
-		out_be32(&ddr->ddr_zq_cntl, regs->ddr_zq_cntl & 0x7fffffff);
-		out_be32(&ddr->ddr_wrlvl_cntl, regs->ddr_wrlvl_cntl & 0x7fffffff);
-		out_be32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2 & 0xffffffeb);
-		out_be32(&ddr->mtcr, 0);
-		out_be32(&ddr->debug[12], 0x00000015);
-		out_be32(&ddr->debug[21], 0x24000000);
-		out_be32(&ddr->sdram_interval, regs->ddr_sdram_interval & 0xffff);
-		out_be32(&ddr->sdram_cfg, temp_sdram_cfg | SDRAM_CFG_BI | SDRAM_CFG_MEM_EN);
-
-		asm volatile("sync;isync");
-		while (!(in_be32(&ddr->debug[1]) & 0x2))
-			;
-
-		switch (regs->ddr_sdram_rcw_2 & 0x00f00000) {
-		case 0x00000000:
-			out_be32(&ddr->sdram_md_cntl,
-				MD_CNTL_MD_EN		|
-				MD_CNTL_CS_SEL_CS0_CS1	|
-				0x04000000		|
-				MD_CNTL_WRCW		|
-				MD_CNTL_MD_VALUE(0x02));
-			break;
-		case 0x00100000:
-			out_be32(&ddr->sdram_md_cntl,
-				MD_CNTL_MD_EN		|
-				MD_CNTL_CS_SEL_CS0_CS1	|
-				0x04000000		|
-				MD_CNTL_WRCW		|
-				MD_CNTL_MD_VALUE(0x0a));
-			break;
-		case 0x00200000:
-			out_be32(&ddr->sdram_md_cntl,
-				MD_CNTL_MD_EN		|
-				MD_CNTL_CS_SEL_CS0_CS1	|
-				0x04000000		|
-				MD_CNTL_WRCW		|
-				MD_CNTL_MD_VALUE(0x12));
-			break;
-		case 0x00300000:
-			out_be32(&ddr->sdram_md_cntl,
-				MD_CNTL_MD_EN		|
-				MD_CNTL_CS_SEL_CS0_CS1	|
-				0x04000000		|
-				MD_CNTL_WRCW		|
-				MD_CNTL_MD_VALUE(0x1a));
-			break;
-		default:
-			out_be32(&ddr->sdram_md_cntl,
-				MD_CNTL_MD_EN		|
-				MD_CNTL_CS_SEL_CS0_CS1	|
-				0x04000000		|
-				MD_CNTL_WRCW		|
-				MD_CNTL_MD_VALUE(0x02));
-			printf("Unsupported RC10\n");
-			break;
-		}
-
-		while (in_be32(&ddr->sdram_md_cntl) & 0x80000000)
-			;
-		udelay(6);
-		out_be32(&ddr->sdram_cfg, temp_sdram_cfg);
-		out_be32(&ddr->timing_cfg_2, regs->timing_cfg_2);
-		out_be32(&ddr->debug[2], 0x0);
-		out_be32(&ddr->ddr_zq_cntl, regs->ddr_zq_cntl);
-		out_be32(&ddr->ddr_wrlvl_cntl, regs->ddr_wrlvl_cntl);
-		out_be32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2);
-		out_be32(&ddr->debug[12], 0x0);
-		out_be32(&ddr->debug[21], 0x0);
-		out_be32(&ddr->sdram_interval, regs->ddr_sdram_interval);
-
-	}
-#endif
-	/*
-	 * For 8572 DDR1 erratum - DDR controller may enter illegal state
-	 * when operatiing in 32-bit bus mode with 4-beat bursts,
-	 * This erratum does not affect DDR3 mode, only for DDR2 mode.
-	 */
-#ifdef CONFIG_SYS_FSL_ERRATUM_DDR_115
-	debug("Workaround for ERRATUM_DDR_115\n");
-	if ((((in_be32(&ddr->sdram_cfg) >> 24) & 0x7) == SDRAM_TYPE_DDR2)
-	    && in_be32(&ddr->sdram_cfg) & 0x80000) {
-		/* set DEBUG_1[31] */
-		setbits_be32(&ddr->debug[0], 1);
-	}
-#endif
-#ifdef CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134
-	debug("Workaround for ERRATUM_DDR111_DDR134\n");
-	/*
-	 * This is the combined workaround for DDR111 and DDR134
-	 * following the published errata for MPC8572
-	 */
-
-	/* 1. Set EEBACR[3] */
-	setbits_be32(&ecm->eebacr, 0x10000000);
-	debug("Setting EEBACR[3] to 0x%08x\n", in_be32(&ecm->eebacr));
-
-	/* 2. Set DINIT in SDRAM_CFG_2*/
-	setbits_be32(&ddr->sdram_cfg_2, SDRAM_CFG2_D_INIT);
-	debug("Setting sdram_cfg_2[D_INIT] to 0x%08x\n",
-		in_be32(&ddr->sdram_cfg_2));
-
-	/* 3. Set DEBUG_3[21] */
-	setbits_be32(&ddr->debug[2], 0x400);
-	debug("Setting DEBUG_3[21] to 0x%08x\n", in_be32(&ddr->debug[2]));
-
-#endif	/* part 1 of the workaound */
-
-	/*
-	 * 500 painful micro-seconds must elapse between
-	 * the DDR clock setup and the DDR config enable.
-	 * DDR2 need 200 us, and DDR3 need 500 us from spec,
-	 * we choose the max, that is 500 us for all of case.
-	 */
-	udelay(500);
-	asm volatile("sync;isync");
-
-	/* Let the controller go */
-	temp_sdram_cfg = in_be32(&ddr->sdram_cfg) & ~SDRAM_CFG_BI;
-	out_be32(&ddr->sdram_cfg, temp_sdram_cfg | SDRAM_CFG_MEM_EN);
-	asm volatile("sync;isync");
-
-	total_gb_size_per_controller = 0;
-	for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
-		if (!(regs->cs[i].config & 0x80000000))
-			continue;
-		total_gb_size_per_controller += 1 << (
-			((regs->cs[i].config >> 14) & 0x3) + 2 +
-			((regs->cs[i].config >> 8) & 0x7) + 12 +
-			((regs->cs[i].config >> 0) & 0x7) + 8 +
-			3 - ((regs->ddr_sdram_cfg >> 19) & 0x3) -
-			26);			/* minus 26 (count of 64M) */
-	}
-	if (fsl_ddr_get_intl3r() & 0x80000000)	/* 3-way interleaving */
-		total_gb_size_per_controller *= 3;
-	else if (regs->cs[0].config & 0x20000000) /* 2-way interleaving */
-		total_gb_size_per_controller <<= 1;
-	/*
-	 * total memory / bus width = transactions needed
-	 * transactions needed / data rate = seconds
-	 * to add plenty of buffer, double the time
-	 * For example, 2GB on 666MT/s 64-bit bus takes about 402ms
-	 * Let's wait for 800ms
-	 */
-	bus_width = 3 - ((ddr->sdram_cfg & SDRAM_CFG_DBW_MASK)
-			>> SDRAM_CFG_DBW_SHIFT);
-	timeout = ((total_gb_size_per_controller << (6 - bus_width)) * 100 /
-		(get_ddr_freq(0) >> 20)) << 1;
-#ifdef CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134
-	timeout_save = timeout;
-#endif
-	total_gb_size_per_controller >>= 4;	/* shift down to gb size */
-	debug("total %d GB\n", total_gb_size_per_controller);
-	debug("Need to wait up to %d * 10ms\n", timeout);
-
-	/* Poll DDR_SDRAM_CFG_2[D_INIT] bit until auto-data init is done.  */
-	while ((in_be32(&ddr->sdram_cfg_2) & SDRAM_CFG2_D_INIT) &&
-		(timeout >= 0)) {
-		udelay(10000);		/* throttle polling rate */
-		timeout--;
-	}
-
-	if (timeout <= 0)
-		printf("Waiting for D_INIT timeout. Memory may not work.\n");
-
-#ifdef CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134
-	/* continue this workaround */
-
-	/* 4. Clear DEBUG3[21] */
-	clrbits_be32(&ddr->debug[2], 0x400);
-	debug("Clearing D3[21] to 0x%08x\n", in_be32(&ddr->debug[2]));
-
-	/* DDR134 workaround starts */
-	/* A: Clear sdram_cfg_2[odt_cfg] */
-	clrbits_be32(&ddr->sdram_cfg_2, SDRAM_CFG2_ODT_CFG_MASK);
-	debug("Clearing SDRAM_CFG2[ODT_CFG] to 0x%08x\n",
-		in_be32(&ddr->sdram_cfg_2));
-
-	/* B: Set DEBUG1[15] */
-	setbits_be32(&ddr->debug[0], 0x10000);
-	debug("Setting D1[15] to 0x%08x\n", in_be32(&ddr->debug[0]));
-
-	/* C: Set timing_cfg_2[cpo] to 0b11111 */
-	setbits_be32(&ddr->timing_cfg_2, TIMING_CFG_2_CPO_MASK);
-	debug("Setting TMING_CFG_2[CPO] to 0x%08x\n",
-		in_be32(&ddr->timing_cfg_2));
-
-	/* D: Set D6 to 0x9f9f9f9f */
-	out_be32(&ddr->debug[5], 0x9f9f9f9f);
-	debug("Setting D6 to 0x%08x\n", in_be32(&ddr->debug[5]));
-
-	/* E: Set D7 to 0x9f9f9f9f */
-	out_be32(&ddr->debug[6], 0x9f9f9f9f);
-	debug("Setting D7 to 0x%08x\n", in_be32(&ddr->debug[6]));
-
-	/* F: Set D2[20] */
-	setbits_be32(&ddr->debug[1], 0x800);
-	debug("Setting D2[20] to 0x%08x\n", in_be32(&ddr->debug[1]));
-
-	/* G: Poll on D2[20] until cleared */
-	while (in_be32(&ddr->debug[1]) & 0x800)
-		udelay(10000);          /* throttle polling rate */
-
-	/* H: Clear D1[15] */
-	clrbits_be32(&ddr->debug[0], 0x10000);
-	debug("Setting D1[15] to 0x%08x\n", in_be32(&ddr->debug[0]));
-
-	/* I: Set sdram_cfg_2[odt_cfg] */
-	setbits_be32(&ddr->sdram_cfg_2,
-		regs->ddr_sdram_cfg_2 & SDRAM_CFG2_ODT_CFG_MASK);
-	debug("Setting sdram_cfg_2 to 0x%08x\n", in_be32(&ddr->sdram_cfg_2));
-
-	/* Continuing with the DDR111 workaround */
-	/* 5. Set D2[21] */
-	setbits_be32(&ddr->debug[1], 0x400);
-	debug("Setting D2[21] to 0x%08x\n", in_be32(&ddr->debug[1]));
-
-	/* 6. Poll D2[21] until its cleared */
-	while (in_be32(&ddr->debug[1]) & 0x400)
-		udelay(10000);          /* throttle polling rate */
-
-	/* 7. Wait for state machine 2nd run, roughly 400ms/GB */
-	debug("Wait for %d * 10ms\n", timeout_save);
-	udelay(timeout_save * 10000);
-
-	/* 8. Set sdram_cfg_2[dinit] if options requires */
-	setbits_be32(&ddr->sdram_cfg_2,
-		regs->ddr_sdram_cfg_2 & SDRAM_CFG2_D_INIT);
-	debug("Setting sdram_cfg_2 to 0x%08x\n", in_be32(&ddr->sdram_cfg_2));
-
-	/* 9. Poll until dinit is cleared */
-	timeout = timeout_save;
-	debug("Need to wait up to %d * 10ms\n", timeout);
-	while ((in_be32(&ddr->sdram_cfg_2) & SDRAM_CFG2_D_INIT) &&
-		(timeout >= 0)) {
-		udelay(10000);		/* throttle polling rate */
-		timeout--;
-	}
-
-	if (timeout <= 0)
-		printf("Waiting for D_INIT timeout. Memory may not work.\n");
-
-	/* 10. Clear EEBACR[3] */
-	clrbits_be32(&ecm->eebacr, 10000000);
-	debug("Clearing EEBACR[3] to 0x%08x\n", in_be32(&ecm->eebacr));
-
-	if (csn != -1) {
-		csn_bnds_t = (unsigned int *) &regs->cs[csn].bnds;
-		*csn_bnds_t = csn_bnds_backup;
-		debug("Change cs%d_bnds back to 0x%08x\n",
-			csn, regs->cs[csn].bnds);
-		setbits_be32(&ddr->sdram_cfg, 0x2);	/* MEM_HALT */
-		switch (csn) {
-		case 0:
-			out_be32(&ddr->cs0_bnds, regs->cs[csn].bnds);
-			break;
-		case 1:
-			out_be32(&ddr->cs1_bnds, regs->cs[csn].bnds);
-			break;
-		case 2:
-			out_be32(&ddr->cs2_bnds, regs->cs[csn].bnds);
-			break;
-		case 3:
-			out_be32(&ddr->cs3_bnds, regs->cs[csn].bnds);
-			break;
-		}
-		clrbits_be32(&ddr->sdram_cfg, 0x2);
-	}
-#endif /* CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134 */
-}
diff --git a/arch/powerpc/cpu/mpc85xx/fdt.c b/arch/powerpc/cpu/mpc85xx/fdt.c
index 533d47ab43..33bc900167 100644
--- a/arch/powerpc/cpu/mpc85xx/fdt.c
+++ b/arch/powerpc/cpu/mpc85xx/fdt.c
@@ -273,7 +273,7 @@ static inline void ft_fixup_l2cache(void *blob)
 		if (has_l2) {
 #ifdef CONFIG_SYS_CACHE_STASHING
 			u32 *reg = (u32 *)fdt_getprop(blob, off, "reg", 0);
-#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
+#if defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && defined(CONFIG_E6500)
 			/* Only initialize every eighth thread */
 			if (reg && !((*reg) % 8))
 #else
@@ -586,6 +586,7 @@ void ft_cpu_setup(void *blob, bd_t *bd)
 {
 	int off;
 	int val;
+	int len;
 	sys_info_t sysinfo;
 
 	/* delete crypto node if not on an E-processor */
@@ -615,8 +616,8 @@ void ft_cpu_setup(void *blob, bd_t *bd)
 	get_sys_info(&sysinfo);
 	off = fdt_node_offset_by_prop_value(blob, -1, "device_type", "cpu", 4);
 	while (off != -FDT_ERR_NOTFOUND) {
-		u32 *reg = (u32 *)fdt_getprop(blob, off, "reg", 0);
-		val = cpu_to_fdt32(sysinfo.freq_processor[*reg]);
+		u32 *reg = (u32 *)fdt_getprop(blob, off, "reg", &len);
+		val = cpu_to_fdt32(sysinfo.freq_processor[(*reg) / (len / 4)]);
 		fdt_setprop(blob, off, "clock-frequency", &val, 4);
 		off = fdt_node_offset_by_prop_value(blob, off, "device_type",
 							"cpu", 4);
diff --git a/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c b/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c
index 39d9409d64..70e09eaed5 100644
--- a/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c
+++ b/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c
@@ -75,6 +75,8 @@ static const char *serdes_prtcl_str[] = {
 	[XFI_FM2_MAC9] = "XFI_FM2_MAC9",
 	[XFI_FM2_MAC10] = "XFI_FM2_MAC10",
 	[INTERLAKEN] = "INTERLAKEN",
+	[QSGMII_SW1_A] = "QSGMII_SW1_A",
+	[QSGMII_SW1_B] = "QSGMII_SW1_B",
 };
 #endif
 
@@ -201,3 +203,24 @@ void fsl_serdes_init(void)
 #endif
 
 }
+
+const char *serdes_clock_to_string(u32 clock)
+{
+	switch (clock) {
+	case SRDS_PLLCR0_RFCK_SEL_100:
+		return "100";
+	case SRDS_PLLCR0_RFCK_SEL_125:
+		return "125";
+	case SRDS_PLLCR0_RFCK_SEL_156_25:
+		return "156.25";
+	case SRDS_PLLCR0_RFCK_SEL_161_13:
+		return "161.1328123";
+	default:
+#if defined(CONFIG_T4240QDS)
+		return "???";
+#else
+		return "122.88";
+#endif
+	}
+}
+
diff --git a/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c b/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c
index 680b5222bc..ba22f90a6f 100644
--- a/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c
+++ b/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c
@@ -858,3 +858,20 @@ void fsl_serdes_init(void)
 	}
 #endif
 }
+
+const char *serdes_clock_to_string(u32 clock)
+{
+	switch (clock) {
+	case SRDS_PLLCR0_RFCK_SEL_100:
+		return "100";
+	case SRDS_PLLCR0_RFCK_SEL_125:
+		return "125";
+	case SRDS_PLLCR0_RFCK_SEL_156_25:
+		return "156.25";
+	case SRDS_PLLCR0_RFCK_SEL_161_13:
+		return "161.1328123";
+	default:
+		return "150";
+	}
+}
+
diff --git a/arch/powerpc/cpu/mpc85xx/liodn.c b/arch/powerpc/cpu/mpc85xx/liodn.c
index 4b00da9f75..19e130e87f 100644
--- a/arch/powerpc/cpu/mpc85xx/liodn.c
+++ b/arch/powerpc/cpu/mpc85xx/liodn.c
@@ -239,9 +239,9 @@ static void fdt_fixup_srio_liodn(void *blob, struct srio_liodn_id_table *tbl)
 #endif
 
 #define CONFIG_SYS_MAX_PCI_EPS		8
-#define CONFIG_SYS_PCI_EP_LIODN_START	256
 
-static void fdt_fixup_pci_liodn_offsets(void *fdt, const char *compat)
+static void fdt_fixup_pci_liodn_offsets(void *fdt, const char *compat,
+					int ep_liodn_start)
 {
 	int off, pci_idx = 0, pci_cnt = 0, i, rc;
 	const uint32_t *base_liodn;
@@ -271,7 +271,7 @@ static void fdt_fixup_pci_liodn_offsets(void *fdt, const char *compat)
 			continue;
 		}
 		for (i = 0; i < CONFIG_SYS_MAX_PCI_EPS; i++)
-			liodn_offs[i + 1] = CONFIG_SYS_PCI_EP_LIODN_START +
+			liodn_offs[i + 1] = ep_liodn_start +
 					i * pci_cnt + pci_idx - *base_liodn;
 		rc = fdt_setprop(fdt, off, "fsl,liodn-offset-list",
 				 liodn_offs, sizeof(liodn_offs));
@@ -338,5 +338,22 @@ void fdt_fixup_liodn(void *blob)
 	fdt_fixup_liodn_tbl(blob, rman_liodn_tbl, rman_liodn_tbl_sz);
 #endif
 
-	fdt_fixup_pci_liodn_offsets(blob, "fsl,qoriq-pcie-v2.4");
+	ccsr_pcix_t *pcix = (ccsr_pcix_t *)CONFIG_SYS_PCIE1_ADDR;
+	int pci_ver = pcix->ipver1 & 0xffff, liodn_base = 0;
+
+	if (pci_ver >= 0x0204) {
+		if (pci_ver >= 0x0300)
+			liodn_base = 1024;
+		else
+			liodn_base = 256;
+	}
+
+	if (liodn_base) {
+		char compat[32];
+
+		sprintf(compat, "fsl,qoriq-pcie-v%d.%d",
+			(pci_ver & 0xff00) >> 8, pci_ver & 0xff);
+		fdt_fixup_pci_liodn_offsets(blob, compat, liodn_base);
+		fdt_fixup_pci_liodn_offsets(blob, "fsl,qoriq-pcie", liodn_base);
+	}
 }
diff --git a/arch/powerpc/cpu/mpc85xx/mp.c b/arch/powerpc/cpu/mpc85xx/mp.c
index 5f198eb305..88c8e65930 100644
--- a/arch/powerpc/cpu/mpc85xx/mp.c
+++ b/arch/powerpc/cpu/mpc85xx/mp.c
@@ -11,7 +11,7 @@
 #include <asm/io.h>
 #include <asm/mmu.h>
 #include <asm/fsl_law.h>
-#include <asm/fsl_ddr_sdram.h>
+#include <fsl_ddr_sdram.h>
 #include "mp.h"
 
 DECLARE_GLOBAL_DATA_PTR;
diff --git a/arch/powerpc/cpu/mpc85xx/release.S b/arch/powerpc/cpu/mpc85xx/release.S
index c15e83b521..fcfba7ec19 100644
--- a/arch/powerpc/cpu/mpc85xx/release.S
+++ b/arch/powerpc/cpu/mpc85xx/release.S
@@ -10,8 +10,6 @@
 #include <mpc85xx.h>
 #include <version.h>
 
-#define _LINUX_CONFIG_H 1	/* avoid reading Linux autoconf.h file	*/
-
 #include <ppc_asm.tmpl>
 #include <ppc_defs.h>
 
diff --git a/arch/powerpc/cpu/mpc85xx/speed.c b/arch/powerpc/cpu/mpc85xx/speed.c
index 4b8d928956..adf09efa27 100644
--- a/arch/powerpc/cpu/mpc85xx/speed.c
+++ b/arch/powerpc/cpu/mpc85xx/speed.c
@@ -18,6 +18,10 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
+
+#ifndef CONFIG_SYS_FSL_NUM_CC_PLLS
+#define CONFIG_SYS_FSL_NUM_CC_PLLS	6
+#endif
 /* --------------------------------------------------------------- */
 
 void get_sys_info(sys_info_t *sys_info)
@@ -30,6 +34,9 @@ void get_sys_info(sys_info_t *sys_info)
 #ifdef CONFIG_FSL_CORENET
 	volatile ccsr_clk_t *clk = (void *)(CONFIG_SYS_FSL_CORENET_CLK_ADDR);
 	unsigned int cpu;
+#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
+	int cc_group[12] = CONFIG_SYS_FSL_CLUSTER_CLOCKS;
+#endif
 
 	const u8 core_cplx_PLL[16] = {
 		[ 0] = 0,	/* CC1 PPL / 1 */
@@ -60,60 +67,92 @@ void get_sys_info(sys_info_t *sys_info)
 		[13] = 2,	/* CC4 PPL / 2 */
 		[14] = 4,	/* CC4 PPL / 4 */
 	};
-	uint i, freq_cc_pll[6], rcw_tmp;
-	uint ratio[6];
+	uint i, freq_c_pll[CONFIG_SYS_FSL_NUM_CC_PLLS];
+#if !defined(CONFIG_FM_PLAT_CLK_DIV) || !defined(CONFIG_PME_PLAT_CLK_DIV)
+	uint rcw_tmp;
+#endif
+	uint ratio[CONFIG_SYS_FSL_NUM_CC_PLLS];
 	unsigned long sysclk = CONFIG_SYS_CLK_FREQ;
 	uint mem_pll_rat;
+#ifdef CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
+	uint single_src;
+#endif
 
 	sys_info->freq_systembus = sysclk;
+#ifdef CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
+	/*
+	 * DDR_REFCLK_SEL rcw bit is used to determine if DDR PLLS
+	 * are driven by separate DDR Refclock or single source
+	 * differential clock.
+	 */
+	single_src = (in_be32(&gur->rcwsr[5]) >>
+		      FSL_CORENET2_RCWSR5_DDR_REFCLK_SEL_SHIFT) &
+		      FSL_CORENET2_RCWSR5_DDR_REFCLK_SEL_MASK;
+	/*
+	 * For single source clocking, both ddrclock and syclock
+	 * are driven by differential sysclock.
+	 */
+	if (single_src == FSL_CORENET2_RCWSR5_DDR_REFCLK_SINGLE_CLK) {
+		printf("Single Source Clock Configuration\n");
+		sys_info->freq_ddrbus = CONFIG_SYS_CLK_FREQ;
+	} else
+#endif
 #ifdef CONFIG_DDR_CLK_FREQ
-	sys_info->freq_ddrbus = CONFIG_DDR_CLK_FREQ;
+		sys_info->freq_ddrbus = CONFIG_DDR_CLK_FREQ;
 #else
-	sys_info->freq_ddrbus = sysclk;
+		sys_info->freq_ddrbus = sysclk;
 #endif
 
 	sys_info->freq_systembus *= (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f;
 	mem_pll_rat = (in_be32(&gur->rcwsr[0]) >>
 			FSL_CORENET_RCWSR0_MEM_PLL_RAT_SHIFT)
 			& FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK;
+	/* T4240/T4160 Rev2.0 MEM_PLL_RAT uses a value which is half of
+	 * T4240/T4160 Rev1.0. eg. It's 12 in Rev1.0, however, for Rev2.0
+	 * it uses 6.
+	 */
+#if defined(CONFIG_PPC_T4240) || defined(CONFIG_PPC_T4160)
+	if (SVR_MAJ(get_svr()) >= 2)
+		mem_pll_rat *= 2;
+#endif
 	if (mem_pll_rat > 2)
 		sys_info->freq_ddrbus *= mem_pll_rat;
 	else
 		sys_info->freq_ddrbus = sys_info->freq_systembus * mem_pll_rat;
 
-	ratio[0] = (in_be32(&clk->pllc1gsr) >> 1) & 0x3f;
-	ratio[1] = (in_be32(&clk->pllc2gsr) >> 1) & 0x3f;
-	ratio[2] = (in_be32(&clk->pllc3gsr) >> 1) & 0x3f;
-	ratio[3] = (in_be32(&clk->pllc4gsr) >> 1) & 0x3f;
-	ratio[4] = (in_be32(&clk->pllc5gsr) >> 1) & 0x3f;
-	ratio[5] = (in_be32(&clk->pllc6gsr) >> 1) & 0x3f;
-	for (i = 0; i < 6; i++) {
+	for (i = 0; i < CONFIG_SYS_FSL_NUM_CC_PLLS; i++) {
+		ratio[i] = (in_be32(&clk->pllcgsr[i].pllcngsr) >> 1) & 0x3f;
 		if (ratio[i] > 4)
-			freq_cc_pll[i] = sysclk * ratio[i];
+			freq_c_pll[i] = sysclk * ratio[i];
 		else
-			freq_cc_pll[i] = sys_info->freq_systembus * ratio[i];
+			freq_c_pll[i] = sys_info->freq_systembus * ratio[i];
 	}
 #ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
 	/*
+	 * As per CHASSIS2 architeture total 12 clusters are posible and
 	 * Each cluster has up to 4 cores, sharing the same PLL selection.
-	 * The cluster assignment is fixed per SoC. PLL1, PLL2, PLL3 are
-	 * cluster group A, feeding cores on cluster 1 and cluster 2.
-	 * PLL4, PLL5, PLL6 are cluster group B, feeding cores on cluster 3
-	 * and cluster 4 if existing.
+	 * The cluster clock assignment is SoC defined.
+	 *
+	 * Total 4 clock groups are possible with 3 PLLs each.
+	 * as per array indices, clock group A has 0, 1, 2 numbered PLLs &
+	 * clock group B has 3, 4, 6 and so on.
+	 *
+	 * Clock group A having PLL1, PLL2, PLL3, feeding cores of any cluster
+	 * depends upon the SoC architeture. Same applies to other
+	 * clock groups and clusters.
+	 *
 	 */
 	for_each_cpu(i, cpu, cpu_numcores(), cpu_mask()) {
 		int cluster = fsl_qoriq_core_to_cluster(cpu);
 		u32 c_pll_sel = (in_be32(&clk->clkcsr[cluster].clkcncsr) >> 27)
 				& 0xf;
 		u32 cplx_pll = core_cplx_PLL[c_pll_sel];
-		if (cplx_pll > 3)
-			printf("Unsupported architecture configuration"
-				" in function %s\n", __func__);
-		cplx_pll += (cluster / 2) * 3;
+		cplx_pll += cc_group[cluster] - 1;
 		sys_info->freq_processor[cpu] =
-			 freq_cc_pll[cplx_pll] / core_cplx_pll_div[c_pll_sel];
+			 freq_c_pll[cplx_pll] / core_cplx_pll_div[c_pll_sel];
 	}
-#ifdef CONFIG_PPC_B4860
+#if defined(CONFIG_PPC_B4860) || defined(CONFIG_PPC_T2080) || \
+	defined(CONFIG_PPC_T2081)
 #define FM1_CLK_SEL	0xe0000000
 #define FM1_CLK_SHIFT	29
 #else
@@ -122,27 +161,30 @@ void get_sys_info(sys_info_t *sys_info)
 #define FM1_CLK_SEL	0x1c000000
 #define FM1_CLK_SHIFT	26
 #endif
+#if !defined(CONFIG_FM_PLAT_CLK_DIV) || !defined(CONFIG_PME_PLAT_CLK_DIV)
 	rcw_tmp = in_be32(&gur->rcwsr[7]);
+#endif
 
 #ifdef CONFIG_SYS_DPAA_PME
+#ifndef CONFIG_PME_PLAT_CLK_DIV
 	switch ((rcw_tmp & PME_CLK_SEL) >> PME_CLK_SHIFT) {
 	case 1:
-		sys_info->freq_pme = freq_cc_pll[0];
+		sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK];
 		break;
 	case 2:
-		sys_info->freq_pme = freq_cc_pll[0] / 2;
+		sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK] / 2;
 		break;
 	case 3:
-		sys_info->freq_pme = freq_cc_pll[0] / 3;
+		sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK] / 3;
 		break;
 	case 4:
-		sys_info->freq_pme = freq_cc_pll[0] / 4;
+		sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK] / 4;
 		break;
 	case 6:
-		sys_info->freq_pme = freq_cc_pll[1] / 2;
+		sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK + 1] / 2;
 		break;
 	case 7:
-		sys_info->freq_pme = freq_cc_pll[1] / 3;
+		sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK + 1] / 3;
 		break;
 	default:
 		printf("Error: Unknown PME clock select!\n");
@@ -151,6 +193,10 @@ void get_sys_info(sys_info_t *sys_info)
 		break;
 
 	}
+#else
+	sys_info->freq_pme = sys_info->freq_systembus / CONFIG_SYS_PME_CLK;
+
+#endif
 #endif
 
 #ifdef CONFIG_SYS_DPAA_QBMAN
@@ -158,27 +204,28 @@ void get_sys_info(sys_info_t *sys_info)
 #endif
 
 #ifdef CONFIG_SYS_DPAA_FMAN
+#ifndef CONFIG_FM_PLAT_CLK_DIV
 	switch ((rcw_tmp & FM1_CLK_SEL) >> FM1_CLK_SHIFT) {
 	case 1:
-		sys_info->freq_fman[0] = freq_cc_pll[3];
+		sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK];
 		break;
 	case 2:
-		sys_info->freq_fman[0] = freq_cc_pll[3] / 2;
+		sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK] / 2;
 		break;
 	case 3:
-		sys_info->freq_fman[0] = freq_cc_pll[3] / 3;
+		sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK] / 3;
 		break;
 	case 4:
-		sys_info->freq_fman[0] = freq_cc_pll[3] / 4;
+		sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK] / 4;
 		break;
 	case 5:
 		sys_info->freq_fman[0] = sys_info->freq_systembus;
 		break;
 	case 6:
-		sys_info->freq_fman[0] = freq_cc_pll[4] / 2;
+		sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK + 1] / 2;
 		break;
 	case 7:
-		sys_info->freq_fman[0] = freq_cc_pll[4] / 3;
+		sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK + 1] / 3;
 		break;
 	default:
 		printf("Error: Unknown FMan1 clock select!\n");
@@ -187,27 +234,31 @@ void get_sys_info(sys_info_t *sys_info)
 		break;
 	}
 #if (CONFIG_SYS_NUM_FMAN) == 2
+#ifdef CONFIG_SYS_FM2_CLK
 #define FM2_CLK_SEL	0x00000038
 #define FM2_CLK_SHIFT	3
 	rcw_tmp = in_be32(&gur->rcwsr[15]);
 	switch ((rcw_tmp & FM2_CLK_SEL) >> FM2_CLK_SHIFT) {
 	case 1:
-		sys_info->freq_fman[1] = freq_cc_pll[4];
+		sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK + 1];
 		break;
 	case 2:
-		sys_info->freq_fman[1] = freq_cc_pll[4] / 2;
+		sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK + 1] / 2;
 		break;
 	case 3:
-		sys_info->freq_fman[1] = freq_cc_pll[4] / 3;
+		sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK + 1] / 3;
 		break;
 	case 4:
-		sys_info->freq_fman[1] = freq_cc_pll[4] / 4;
+		sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK + 1] / 4;
+		break;
+	case 5:
+		sys_info->freq_fman[1] = sys_info->freq_systembus;
 		break;
 	case 6:
-		sys_info->freq_fman[1] = freq_cc_pll[3] / 2;
+		sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK] / 2;
 		break;
 	case 7:
-		sys_info->freq_fman[1] = freq_cc_pll[3] / 3;
+		sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK] / 3;
 		break;
 	default:
 		printf("Error: Unknown FMan2 clock select!\n");
@@ -215,8 +266,12 @@ void get_sys_info(sys_info_t *sys_info)
 		sys_info->freq_fman[1] = sys_info->freq_systembus / 2;
 		break;
 	}
+#endif
 #endif	/* CONFIG_SYS_NUM_FMAN == 2 */
-#endif	/* CONFIG_SYS_DPAA_FMAN */
+#else
+	sys_info->freq_fman[0] = sys_info->freq_systembus / CONFIG_SYS_FM1_CLK;
+#endif
+#endif
 
 #else /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */
 
@@ -226,7 +281,7 @@ void get_sys_info(sys_info_t *sys_info)
 		u32 cplx_pll = core_cplx_PLL[c_pll_sel];
 
 		sys_info->freq_processor[cpu] =
-			 freq_cc_pll[cplx_pll] / core_cplx_pll_div[c_pll_sel];
+			 freq_c_pll[cplx_pll] / core_cplx_pll_div[c_pll_sel];
 	}
 #define PME_CLK_SEL	0x80000000
 #define FM1_CLK_SEL	0x40000000
@@ -246,9 +301,9 @@ void get_sys_info(sys_info_t *sys_info)
 #ifdef CONFIG_SYS_DPAA_PME
 	if (rcw_tmp & PME_CLK_SEL) {
 		if (rcw_tmp & HWA_ASYNC_DIV)
-			sys_info->freq_pme = freq_cc_pll[HWA_CC_PLL] / 4;
+			sys_info->freq_pme = freq_c_pll[HWA_CC_PLL] / 4;
 		else
-			sys_info->freq_pme = freq_cc_pll[HWA_CC_PLL] / 2;
+			sys_info->freq_pme = freq_c_pll[HWA_CC_PLL] / 2;
 	} else {
 		sys_info->freq_pme = sys_info->freq_systembus / 2;
 	}
@@ -257,18 +312,18 @@ void get_sys_info(sys_info_t *sys_info)
 #ifdef CONFIG_SYS_DPAA_FMAN
 	if (rcw_tmp & FM1_CLK_SEL) {
 		if (rcw_tmp & HWA_ASYNC_DIV)
-			sys_info->freq_fman[0] = freq_cc_pll[HWA_CC_PLL] / 4;
+			sys_info->freq_fman[0] = freq_c_pll[HWA_CC_PLL] / 4;
 		else
-			sys_info->freq_fman[0] = freq_cc_pll[HWA_CC_PLL] / 2;
+			sys_info->freq_fman[0] = freq_c_pll[HWA_CC_PLL] / 2;
 	} else {
 		sys_info->freq_fman[0] = sys_info->freq_systembus / 2;
 	}
 #if (CONFIG_SYS_NUM_FMAN) == 2
 	if (rcw_tmp & FM2_CLK_SEL) {
 		if (rcw_tmp & HWA_ASYNC_DIV)
-			sys_info->freq_fman[1] = freq_cc_pll[HWA_CC_PLL] / 4;
+			sys_info->freq_fman[1] = freq_c_pll[HWA_CC_PLL] / 4;
 		else
-			sys_info->freq_fman[1] = freq_cc_pll[HWA_CC_PLL] / 2;
+			sys_info->freq_fman[1] = freq_c_pll[HWA_CC_PLL] / 2;
 	} else {
 		sys_info->freq_fman[1] = sys_info->freq_systembus / 2;
 	}
diff --git a/arch/powerpc/cpu/mpc85xx/spl_minimal.c b/arch/powerpc/cpu/mpc85xx/spl_minimal.c
index 199b33e3bd..9e4c6c9078 100644
--- a/arch/powerpc/cpu/mpc85xx/spl_minimal.c
+++ b/arch/powerpc/cpu/mpc85xx/spl_minimal.c
@@ -7,7 +7,7 @@
 #include <common.h>
 #include <asm/processor.h>
 #include <asm/global_data.h>
-#include <asm/fsl_ifc.h>
+#include <fsl_ifc.h>
 #include <asm/io.h>
 
 DECLARE_GLOBAL_DATA_PTR;
diff --git a/arch/powerpc/cpu/mpc85xx/start.S b/arch/powerpc/cpu/mpc85xx/start.S
index d329aa84ab..dbbd8e588c 100644
--- a/arch/powerpc/cpu/mpc85xx/start.S
+++ b/arch/powerpc/cpu/mpc85xx/start.S
@@ -17,8 +17,6 @@
 #include <mpc85xx.h>
 #include <version.h>
 
-#define _LINUX_CONFIG_H 1	/* avoid reading Linux autoconf.h file	*/
-
 #include <ppc_asm.tmpl>
 #include <ppc_defs.h>
 
@@ -699,7 +697,7 @@ delete_temp_tlbs:
 
 #endif /* #if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR_PHYS) */
 
-#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
+#if defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && defined(CONFIG_E6500)
 create_ccsr_l2_tlb:
 	/*
 	 * Create a TLB for the MMR location of CCSR
@@ -886,7 +884,11 @@ delete_ccsr_l2_tlb:
 	erratum_set_dcsr 0xb0008 0x00900000
 	erratum_set_dcsr 0xb0e40 0xe00a0000
 	erratum_set_ccsr 0x18600 CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY
+#ifdef  CONFIG_RAMBOOT_PBL
+	erratum_set_ccsr 0x10f00 0x495e5000
+#else
 	erratum_set_ccsr 0x10f00 0x415e5000
+#endif
 	erratum_set_ccsr 0x11f00 0x415e5000
 
 	/* Make temp mapping uncacheable again, if it was initially */
diff --git a/arch/powerpc/cpu/mpc85xx/t1040_ids.c b/arch/powerpc/cpu/mpc85xx/t1040_ids.c
index 32075ce220..68160a9512 100644
--- a/arch/powerpc/cpu/mpc85xx/t1040_ids.c
+++ b/arch/powerpc/cpu/mpc85xx/t1040_ids.c
@@ -21,21 +21,6 @@ struct qportal_info qp_info[CONFIG_SYS_QMAN_NUM_PORTALS] = {
 	SET_QP_INFO(8, 34, 1, 3),
 	SET_QP_INFO(9, 35, 1, 0),
 	SET_QP_INFO(10, 36, 1, 0),
-	SET_QP_INFO(11, 37, 1, 1),
-	SET_QP_INFO(12, 38, 1, 1),
-	SET_QP_INFO(13, 39, 1, 2),
-	SET_QP_INFO(14, 40, 1, 2),
-	SET_QP_INFO(15, 41, 1, 3),
-	SET_QP_INFO(16, 42, 1, 3),
-	SET_QP_INFO(17, 43, 1, 0),
-	SET_QP_INFO(18, 44, 1, 0),
-	SET_QP_INFO(19, 45, 1, 1),
-	SET_QP_INFO(20, 46, 1, 1),
-	SET_QP_INFO(21, 47, 1, 2),
-	SET_QP_INFO(22, 48, 1, 2),
-	SET_QP_INFO(23, 49, 1, 3),
-	SET_QP_INFO(24, 50, 1, 3),
-	SET_QP_INFO(25, 51, 1, 0),
 };
 #endif
 
@@ -60,11 +45,6 @@ struct liodn_id_table liodn_tbl[] = {
 	SET_DMA_LIODN(1, 147),
 	SET_DMA_LIODN(2, 227),
 
-	SET_GUTS_LIODN("fsl,rapidio-delta", 199, rio1liodnr, 0),
-	SET_GUTS_LIODN(NULL, 200, rio2liodnr, 0),
-	SET_GUTS_LIODN(NULL, 201, rio1maintliodnr, 0),
-	SET_GUTS_LIODN(NULL, 202, rio2maintliodnr, 0),
-
 	/* SET_NEXUS_LIODN(557), -- not yet implemented */
 };
 int liodn_tbl_sz = ARRAY_SIZE(liodn_tbl);
@@ -77,8 +57,6 @@ struct liodn_id_table fman1_liodn_tbl[] = {
 	SET_FMAN_RX_1G_LIODN(1, 3, 91),
 	SET_FMAN_RX_1G_LIODN(1, 4, 92),
 	SET_FMAN_RX_1G_LIODN(1, 5, 93),
-	SET_FMAN_RX_10G_LIODN(1, 0, 94),
-	SET_FMAN_RX_10G_LIODN(1, 1, 95),
 };
 int fman1_liodn_tbl_sz = ARRAY_SIZE(fman1_liodn_tbl);
 #endif
@@ -97,23 +75,9 @@ struct liodn_id_table sec_liodn_tbl[] = {
 };
 int sec_liodn_tbl_sz = ARRAY_SIZE(sec_liodn_tbl);
 
-#ifdef CONFIG_SYS_DPAA_RMAN
-struct liodn_id_table rman_liodn_tbl[] = {
-	/* Set RMan block 0-3 liodn offset */
-	SET_RMAN_LIODN(0, 678),
-	SET_RMAN_LIODN(1, 679),
-	SET_RMAN_LIODN(2, 680),
-	SET_RMAN_LIODN(3, 681),
-};
-int rman_liodn_tbl_sz = ARRAY_SIZE(rman_liodn_tbl);
-#endif
-
 struct liodn_id_table liodn_bases[] = {
 	[FSL_HW_PORTAL_SEC]  = SET_LIODN_BASE_2(462, 558),
 #ifdef CONFIG_SYS_DPAA_FMAN
 	[FSL_HW_PORTAL_FMAN1] = SET_LIODN_BASE_1(973),
 #endif
-#ifdef CONFIG_SYS_DPAA_RMAN
-	[FSL_HW_PORTAL_RMAN] = SET_LIODN_BASE_1(922),
-#endif
 };
diff --git a/arch/powerpc/cpu/mpc85xx/t1040_serdes.c b/arch/powerpc/cpu/mpc85xx/t1040_serdes.c
index 94814ac13e..d86bb27372 100644
--- a/arch/powerpc/cpu/mpc85xx/t1040_serdes.c
+++ b/arch/powerpc/cpu/mpc85xx/t1040_serdes.c
@@ -8,68 +8,59 @@
 #include <asm/fsl_serdes.h>
 #include <asm/processor.h>
 #include <asm/io.h>
-#include "fsl_corenet2_serdes.h"
 
-static u8 serdes_cfg_tbl[MAX_SERDES][0xC4][SRDS_MAX_LANES] = {
-	{	/* SerDes 1 */
-	[0x69] = {PCIE1, SGMII_FM1_DTSEC3, QSGMII_SW1_A, QSGMII_SW1_B,
-		PCIE2, PCIE3, SGMII_FM1_DTSEC4, SATA1},
+
+static u8 serdes_cfg_tbl[][SRDS_MAX_LANES] = {
+	[0x00] = {PCIE1, PCIE1, PCIE1, PCIE1,
+		PCIE2, PCIE2, PCIE2, PCIE2},
+	[0x06] = {PCIE1, PCIE1, PCIE1, PCIE1,
+		PCIE2, PCIE3, PCIE4, SATA1},
+	[0x08] = {PCIE1, PCIE1, PCIE1, PCIE1,
+		PCIE2, PCIE3, SATA2, SATA1},
+	[0x40] = {PCIE1, PCIE1, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
+		PCIE2, PCIE2, PCIE2, PCIE2},
+	[0x60] = {PCIE1, SGMII_FM1_DTSEC3, QSGMII_SW1_A, QSGMII_SW1_B,
+		PCIE2, PCIE2, PCIE2, PCIE2},
 	[0x66] = {PCIE1, SGMII_FM1_DTSEC3, QSGMII_SW1_A, QSGMII_SW1_B,
 		PCIE2, PCIE3, PCIE4, SATA1},
 	[0x67] = {PCIE1, SGMII_FM1_DTSEC3, QSGMII_SW1_A, QSGMII_SW1_B,
 		PCIE2, PCIE3, PCIE4, SGMII_FM1_DTSEC5},
-	[0x60] = {PCIE1, SGMII_FM1_DTSEC3, QSGMII_SW1_A, QSGMII_SW1_B,
-		PCIE2, PCIE2, PCIE2, PCIE2},
-	[0x8D] = {PCIE1, SGMII_SW1_DTSEC3, SGMII_SW1_DTSEC1, SGMII_SW1_DTSEC2,
-		PCIE2, SGMII_SW1_DTSEC6, SGMII_SW1_DTSEC4, SGMII_SW1_DTSEC5},
-	[0x89] = {PCIE1, SGMII_SW1_DTSEC3, SGMII_SW1_DTSEC1, SGMII_SW1_DTSEC2,
-		PCIE2, PCIE3, SGMII_SW1_DTSEC4, SATA1},
+	[0x69] = {PCIE1, SGMII_FM1_DTSEC3, QSGMII_SW1_A, QSGMII_SW1_B,
+		PCIE2, PCIE3, SGMII_FM1_DTSEC4, SATA1},
 	[0x86] = {PCIE1, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
 		PCIE2, PCIE3, PCIE4, SATA1},
+	[0x85] = {PCIE1, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
+		PCIE2, PCIE2, SGMII_FM1_DTSEC4, SGMII_FM1_DTSEC5},
 	[0x87] = {PCIE1, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
 		PCIE2, PCIE3, PCIE4, SGMII_FM1_DTSEC5},
-	[0xA7] = {PCIE1, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
-		 PCIE2, PCIE3, PCIE4, SGMII_FM1_DTSEC5},
-	[0xAA] = {PCIE1, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
-		 PCIE2, PCIE3, SGMII_FM1_DTSEC4, SGMII_FM1_DTSEC5},
-	[0x40] = {PCIE1, PCIE1, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
-		PCIE2, PCIE2, PCIE2, PCIE2},
-	[0x06] = {PCIE1, PCIE1, PCIE1, PCIE1,
-		PCIE2, PCIE3, PCIE4, SATA1},
-	[0x08] = {PCIE1, PCIE1, PCIE1, PCIE1,
-		PCIE2, PCIE3, SATA2, SATA1},
+	[0x89] = {PCIE1, QSGMII_SW1_A, QSGMII_SW1_A, QSGMII_SW1_A,
+		PCIE2, PCIE3, QSGMII_SW1_B, SATA1},
+	[0x8D] = {PCIE1, QSGMII_SW1_A, QSGMII_SW1_A, QSGMII_SW1_A,
+		PCIE2, QSGMII_SW1_B, QSGMII_SW1_B, QSGMII_SW1_B},
 	[0x8F] = {PCIE1, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
 		AURORA, NONE, SGMII_FM1_DTSEC4, SGMII_FM1_DTSEC5},
-	[0x85] = {PCIE1, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
-		PCIE2, PCIE2, SGMII_FM1_DTSEC4, SGMII_FM1_DTSEC5},
 	[0xA5] = {PCIE1, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
 		PCIE2, PCIE2, SGMII_FM1_DTSEC4, SGMII_FM1_DTSEC5},
-	[0x00] = {PCIE1, PCIE1, PCIE1, PCIE1,
-		PCIE2, PCIE2, PCIE2, PCIE2},
-	},
-	{
-	},
-	{
-	},
-	{
-	},
+	[0xA7] = {PCIE1, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
+		 PCIE2, PCIE3, PCIE4, SGMII_FM1_DTSEC5},
+	[0xAA] = {PCIE1, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
+		 PCIE2, PCIE3, SGMII_FM1_DTSEC4, SGMII_FM1_DTSEC5},
 };
 
-
 enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane)
 {
-	return serdes_cfg_tbl[serdes][cfg][lane];
+	return serdes_cfg_tbl[cfg][lane];
 }
 
 int is_serdes_prtcl_valid(int serdes, u32 prtcl)
 {
 	int i;
 
-	if (prtcl >= ARRAY_SIZE(serdes_cfg_tbl[serdes]))
+	if (prtcl >= ARRAY_SIZE(serdes_cfg_tbl))
 		return 0;
 
 	for (i = 0; i < SRDS_MAX_LANES; i++) {
-		if (serdes_cfg_tbl[serdes][prtcl][i] != NONE)
+		if (serdes_cfg_tbl[prtcl][i] != NONE)
 			return 1;
 	}
 
diff --git a/arch/powerpc/cpu/mpc85xx/t2080_ids.c b/arch/powerpc/cpu/mpc85xx/t2080_ids.c
new file mode 100644
index 0000000000..0bfd447381
--- /dev/null
+++ b/arch/powerpc/cpu/mpc85xx/t2080_ids.c
@@ -0,0 +1,144 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/fsl_portals.h>
+#include <asm/fsl_liodn.h>
+
+#ifdef CONFIG_SYS_DPAA_QBMAN
+struct qportal_info qp_info[CONFIG_SYS_QMAN_NUM_PORTALS] = {
+	/* dqrr liodn, frame data liodn, liodn off, sdest */
+	SET_QP_INFO(1, 27, 1, 0),
+	SET_QP_INFO(2, 28, 1, 0),
+	SET_QP_INFO(3, 29, 1, 1),
+	SET_QP_INFO(4, 30, 1, 1),
+	SET_QP_INFO(5, 31, 1, 2),
+	SET_QP_INFO(6, 32, 1, 2),
+	SET_QP_INFO(7, 33, 1, 3),
+	SET_QP_INFO(8, 34, 1, 3),
+	SET_QP_INFO(9, 35, 1, 0),
+	SET_QP_INFO(10, 36, 1, 0),
+	SET_QP_INFO(11, 37, 1, 1),
+	SET_QP_INFO(12, 38, 1, 1),
+	SET_QP_INFO(13, 39, 1, 2),
+	SET_QP_INFO(14, 40, 1, 2),
+	SET_QP_INFO(15, 41, 1, 3),
+	SET_QP_INFO(16, 42, 1, 3),
+	SET_QP_INFO(17, 43, 1, 0),
+	SET_QP_INFO(18, 44, 1, 0),
+};
+#endif
+
+#ifdef CONFIG_SYS_SRIO
+struct srio_liodn_id_table srio_liodn_tbl[] = {
+	SET_SRIO_LIODN_BASE(1, 307),
+	SET_SRIO_LIODN_BASE(2, 387),
+};
+int srio_liodn_tbl_sz = ARRAY_SIZE(srio_liodn_tbl);
+#endif
+
+struct liodn_id_table liodn_tbl[] = {
+#ifdef CONFIG_SYS_DPAA_QBMAN
+	SET_QMAN_LIODN(62),
+	SET_BMAN_LIODN(63),
+#endif
+
+	SET_SDHC_LIODN(1, 552),
+
+	SET_PME_LIODN(117),
+
+	SET_USB_LIODN(1, "fsl-usb2-mph", 553),
+	SET_USB_LIODN(2, "fsl-usb2-dr", 554),
+
+#ifdef CONFIG_FSL_SATA_V2
+	SET_SATA_LIODN(1, 555),
+	SET_SATA_LIODN(2, 556),
+#endif
+
+	SET_PCI_LIODN_BASE(CONFIG_SYS_FSL_PCIE_COMPAT, 1, 148),
+	SET_PCI_LIODN_BASE(CONFIG_SYS_FSL_PCIE_COMPAT, 2, 228),
+	SET_PCI_LIODN_BASE(CONFIG_SYS_FSL_PCIE_COMPAT, 3, 308),
+	SET_PCI_LIODN_BASE(CONFIG_SYS_FSL_PCIE_COMPAT, 4, 388),
+
+	SET_DMA_LIODN(1, 147),
+	SET_DMA_LIODN(2, 227),
+	SET_DMA_LIODN(3, 226),
+
+	SET_GUTS_LIODN("fsl,rapidio-delta", 199, rio1liodnr, 0),
+	SET_GUTS_LIODN(NULL, 200, rio2liodnr, 0),
+	SET_GUTS_LIODN(NULL, 201, rio1maintliodnr, 0),
+	SET_GUTS_LIODN(NULL, 202, rio2maintliodnr, 0),
+
+#ifdef CONFIG_SYS_PMAN
+	SET_PMAN_LIODN(1, 513),
+	SET_PMAN_LIODN(2, 514),
+	SET_PMAN_LIODN(3, 515),
+#endif
+
+	/* SET_NEXUS_LIODN(557), -- not yet implemented */
+};
+int liodn_tbl_sz = ARRAY_SIZE(liodn_tbl);
+
+#ifdef CONFIG_SYS_DPAA_FMAN
+struct liodn_id_table fman1_liodn_tbl[] = {
+	SET_FMAN_RX_1G_LIODN(1, 0, 88),
+	SET_FMAN_RX_1G_LIODN(1, 1, 89),
+	SET_FMAN_RX_1G_LIODN(1, 2, 90),
+	SET_FMAN_RX_1G_LIODN(1, 3, 91),
+	SET_FMAN_RX_1G_LIODN(1, 4, 92),
+	SET_FMAN_RX_1G_LIODN(1, 5, 93),
+	SET_FMAN_RX_10G_LIODN(1, 0, 94),
+	SET_FMAN_RX_10G_LIODN(1, 1, 95),
+};
+int fman1_liodn_tbl_sz = ARRAY_SIZE(fman1_liodn_tbl);
+#endif
+
+struct liodn_id_table sec_liodn_tbl[] = {
+	SET_SEC_JR_LIODN_ENTRY(0, 454, 458),
+	SET_SEC_JR_LIODN_ENTRY(1, 455, 459),
+	SET_SEC_JR_LIODN_ENTRY(2, 456, 460),
+	SET_SEC_JR_LIODN_ENTRY(3, 457, 461),
+	SET_SEC_RTIC_LIODN_ENTRY(a, 453),
+	SET_SEC_RTIC_LIODN_ENTRY(b, 549),
+	SET_SEC_RTIC_LIODN_ENTRY(c, 550),
+	SET_SEC_RTIC_LIODN_ENTRY(d, 551),
+	SET_SEC_DECO_LIODN_ENTRY(0, 541, 610),
+	SET_SEC_DECO_LIODN_ENTRY(1, 542, 611),
+	SET_SEC_DECO_LIODN_ENTRY(2, 543, 612),
+	SET_SEC_DECO_LIODN_ENTRY(3, 544, 613),
+	SET_SEC_DECO_LIODN_ENTRY(4, 545, 614),
+	SET_SEC_DECO_LIODN_ENTRY(5, 546, 615),
+	SET_SEC_DECO_LIODN_ENTRY(6, 547, 616),
+	SET_SEC_DECO_LIODN_ENTRY(7, 548, 617),
+};
+int sec_liodn_tbl_sz = ARRAY_SIZE(sec_liodn_tbl);
+
+#ifdef CONFIG_SYS_DPAA_RMAN
+struct liodn_id_table rman_liodn_tbl[] = {
+	/* Set RMan block 0-3 liodn offset */
+	SET_RMAN_LIODN(0, 6),
+	SET_RMAN_LIODN(1, 7),
+	SET_RMAN_LIODN(2, 8),
+	SET_RMAN_LIODN(3, 9),
+};
+int rman_liodn_tbl_sz = ARRAY_SIZE(rman_liodn_tbl);
+#endif
+
+struct liodn_id_table liodn_bases[] = {
+#ifdef CONFIG_SYS_DPAA_DCE
+	[FSL_HW_PORTAL_DCE]  = SET_LIODN_BASE_2(618, 694),
+#endif
+	[FSL_HW_PORTAL_SEC]  = SET_LIODN_BASE_2(462, 558),
+#ifdef CONFIG_SYS_DPAA_FMAN
+	[FSL_HW_PORTAL_FMAN1] = SET_LIODN_BASE_1(973),
+#endif
+#ifdef CONFIG_SYS_DPAA_PME
+	[FSL_HW_PORTAL_PME]   = SET_LIODN_BASE_2(770, 846),
+#endif
+#ifdef CONFIG_SYS_DPAA_RMAN
+	[FSL_HW_PORTAL_RMAN] = SET_LIODN_BASE_1(922),
+#endif
+};
diff --git a/arch/powerpc/cpu/mpc85xx/t2080_serdes.c b/arch/powerpc/cpu/mpc85xx/t2080_serdes.c
new file mode 100644
index 0000000000..07e27deb1f
--- /dev/null
+++ b/arch/powerpc/cpu/mpc85xx/t2080_serdes.c
@@ -0,0 +1,207 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * Shengzhou Liu <Shengzhou.Liu@freescale.com>
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/fsl_serdes.h>
+#include <asm/processor.h>
+#include "fsl_corenet2_serdes.h"
+
+struct serdes_config {
+	u32 protocol;
+	u8 lanes[SRDS_MAX_LANES];
+};
+
+static const struct serdes_config serdes1_cfg_tbl[] = {
+	/* SerDes 1 */
+	{0x6E, {XFI_FM1_MAC9, XFI_FM1_MAC10,
+		SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
+		PCIE4, PCIE4, SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
+	{0xBC, {PCIE3, PCIE3, SGMII_FM1_DTSEC1,
+		SGMII_FM1_DTSEC2, PCIE4, PCIE4, PCIE4, PCIE4} },
+	{0xC8, {PCIE3, SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC1,
+		SGMII_FM1_DTSEC2, PCIE4, PCIE4,
+		SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
+	{0xD6, {PCIE3, SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC1,
+		SGMII_FM1_DTSEC2, PCIE4, PCIE4,
+		SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
+	{0xDE, {PCIE3, PCIE3, PCIE3, PCIE3,
+		PCIE4, PCIE1, PCIE2, SGMII_FM1_DTSEC6} },
+	{0xE0, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE4,
+		PCIE1, SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
+	{0xF2, {PCIE3, SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC1,
+		SGMII_FM1_DTSEC2, PCIE4, PCIE1, PCIE2, SGMII_FM1_DTSEC6} },
+	{0xF8, {PCIE3, SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC1,
+		SGMII_FM1_DTSEC2, PCIE4, PCIE1, PCIE2, SGMII_FM1_DTSEC6} },
+	{0xFA, {PCIE3, SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC1,
+		SGMII_FM1_DTSEC2, PCIE4, PCIE1,
+		SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
+	{0x6C, {XFI_FM1_MAC9, XFI_FM1_MAC10,
+		SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
+		PCIE4, PCIE4, PCIE4, PCIE4} },
+	{0x1C, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC10,
+		SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
+		SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
+		SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
+	{0x95, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC10,
+		SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
+		SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
+		SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
+	{0xA2, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC10,
+		SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
+		SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
+		SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
+	{0x94, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC10,
+		SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
+		SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
+		SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
+	{0x51, {XAUI_FM1_MAC9, XAUI_FM1_MAC9,
+		XAUI_FM1_MAC9, XAUI_FM1_MAC9,
+		PCIE4, SGMII_FM1_DTSEC4,
+		SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
+	{0x5F, {HIGIG_FM1_MAC9, HIGIG_FM1_MAC9,
+		HIGIG_FM1_MAC9, HIGIG_FM1_MAC9,
+		PCIE4, SGMII_FM1_DTSEC4,
+		SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
+	{0x65, {HIGIG_FM1_MAC9, HIGIG_FM1_MAC9,
+		HIGIG_FM1_MAC9, HIGIG_FM1_MAC9,
+		PCIE4, SGMII_FM1_DTSEC4,
+		SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
+	{0x6B, {XFI_FM1_MAC9, XFI_FM1_MAC10,
+		XFI_FM1_MAC1, XFI_FM1_MAC2,
+		PCIE4, SGMII_FM1_DTSEC4,
+		SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
+	{0x6D, {XFI_FM1_MAC9, XFI_FM1_MAC10,
+		SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
+		PCIE4, PCIE4, PCIE4, PCIE4} },
+	{0x71, {XFI_FM1_MAC9, XFI_FM1_MAC10,
+		SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, PCIE4,
+		SGMII_FM1_DTSEC4, SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
+	{0xA6, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC10,
+		SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, PCIE4,
+		PCIE4, SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
+	{0x8E, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC10,
+		SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, PCIE4,
+		PCIE4, SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
+	{0x8F, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC10,
+		SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, PCIE4,
+		PCIE4, SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
+	{0x82, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC10,
+		SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
+		PCIE4, PCIE4, SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
+	{0x83, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC10,
+		SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
+		PCIE4, PCIE4, SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
+	{0xA4, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC10,
+		SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
+		PCIE4, PCIE4, PCIE4, PCIE4} },
+	{0x96, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC10,
+		SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
+		PCIE4, PCIE4, PCIE4, PCIE4} },
+	{0x8A, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC10,
+		SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
+		PCIE4, PCIE4, PCIE4, PCIE4} },
+	{0x67, {XFI_FM1_MAC9, XFI_FM1_MAC10,
+		XFI_FM1_MAC1, XFI_FM1_MAC2,
+		PCIE4, PCIE4, PCIE4, PCIE4} },
+	{0xAB, {PCIE3, PCIE3, PCIE3, PCIE3,
+		PCIE4, PCIE4, PCIE4, PCIE4} },
+	{0xDA, {PCIE3, PCIE3, PCIE3, PCIE3,
+		PCIE3, PCIE3, PCIE3, PCIE3} },
+	{0xD9, {PCIE3, SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC1,
+		SGMII_FM1_DTSEC2, PCIE4, SGMII_FM1_DTSEC4,
+		SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
+	{0xD3, {PCIE3, SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC1,
+		SGMII_FM1_DTSEC2, PCIE4, SGMII_FM1_DTSEC4,
+		SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
+	{0xCB, {PCIE3, SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC1,
+		SGMII_FM1_DTSEC2, PCIE4, SGMII_FM1_DTSEC4,
+		SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
+	{0xD8, {PCIE3, SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC1,
+		SGMII_FM1_DTSEC2, PCIE4, SGMII_FM1_DTSEC4,
+		SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
+	{0x66, {XFI_FM1_MAC9, XFI_FM1_MAC10,
+		XFI_FM1_MAC1, XFI_FM1_MAC2,
+		PCIE4, PCIE4, PCIE4, PCIE4} },
+
+#if defined(CONFIG_PPC_T2081)
+	{0xAA, {PCIE3, PCIE3, PCIE3, PCIE3,
+		PCIE4, PCIE4, PCIE4, PCIE4} },
+	{0xCA, {PCIE3, SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC1,
+		SGMII_FM1_DTSEC2, PCIE4, SGMII_FM1_DTSEC4,
+		SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
+	{0x70, {XFI_FM1_MAC9, XFI_FM1_MAC10, SGMII_FM1_DTSEC1,
+		SGMII_FM1_DTSEC2, PCIE4, SGMII_FM1_DTSEC4,
+		SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
+#endif
+	{}
+};
+
+#ifndef CONFIG_PPC_T2081
+static const struct serdes_config serdes2_cfg_tbl[] = {
+	/* SerDes 2 */
+	{0x1F, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2} },
+	{0x16, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, SATA1, SATA2} },
+	{0x01, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1} },
+	{0x29, {SRIO2, SRIO2, SRIO2, SRIO2, SRIO1, SRIO1, SRIO1, SRIO1} },
+	{0x2D, {SRIO2, SRIO2, SRIO2, SRIO2, SRIO1, SRIO1, SRIO1, SRIO1} },
+	{0x15, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, SATA1, SATA2} },
+	{0x18, {PCIE1, PCIE1, PCIE1, PCIE1, AURORA, AURORA, SATA1, SATA2} },
+	{0x02, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1} },
+	{0x36, {SRIO2, SRIO2, SRIO2, SRIO2, AURORA, AURORA, SATA1, SATA2} },
+	{}
+};
+#endif
+
+static const struct serdes_config *serdes_cfg_tbl[] = {
+	serdes1_cfg_tbl,
+#ifndef CONFIG_PPC_T2081
+	serdes2_cfg_tbl,
+#endif
+};
+
+enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane)
+{
+	const struct serdes_config *ptr;
+
+	if (serdes >= ARRAY_SIZE(serdes_cfg_tbl))
+		return 0;
+
+	ptr = serdes_cfg_tbl[serdes];
+	while (ptr->protocol) {
+		if (ptr->protocol == cfg)
+			return ptr->lanes[lane];
+		ptr++;
+	}
+	return 0;
+}
+
+int is_serdes_prtcl_valid(int serdes, u32 prtcl)
+{
+	int i;
+	const struct serdes_config *ptr;
+
+	if (serdes >= ARRAY_SIZE(serdes_cfg_tbl))
+		return 0;
+
+	ptr = serdes_cfg_tbl[serdes];
+	while (ptr->protocol) {
+		if (ptr->protocol == prtcl)
+			break;
+		ptr++;
+	}
+
+	if (!ptr->protocol)
+		return 0;
+
+	for (i = 0; i < SRDS_MAX_LANES; i++) {
+		if (ptr->lanes[i] != NONE)
+			return 1;
+	}
+
+	return 0;
+}
diff --git a/arch/powerpc/cpu/mpc85xx/t4240_ids.c b/arch/powerpc/cpu/mpc85xx/t4240_ids.c
index 54c1cfd2c1..f181315134 100644
--- a/arch/powerpc/cpu/mpc85xx/t4240_ids.c
+++ b/arch/powerpc/cpu/mpc85xx/t4240_ids.c
@@ -86,10 +86,10 @@ struct liodn_id_table liodn_tbl[] = {
 	SET_SATA_LIODN(1, 555),
 	SET_SATA_LIODN(2, 556),
 
-	SET_PCI_LIODN(CONFIG_SYS_FSL_PCIE_COMPAT, 1, 148),
-	SET_PCI_LIODN(CONFIG_SYS_FSL_PCIE_COMPAT, 2, 228),
-	SET_PCI_LIODN(CONFIG_SYS_FSL_PCIE_COMPAT, 3, 308),
-	SET_PCI_LIODN(CONFIG_SYS_FSL_PCIE_COMPAT, 4, 388),
+	SET_PCI_LIODN_BASE(CONFIG_SYS_FSL_PCIE_COMPAT, 1, 148),
+	SET_PCI_LIODN_BASE(CONFIG_SYS_FSL_PCIE_COMPAT, 2, 228),
+	SET_PCI_LIODN_BASE(CONFIG_SYS_FSL_PCIE_COMPAT, 3, 308),
+	SET_PCI_LIODN_BASE(CONFIG_SYS_FSL_PCIE_COMPAT, 4, 388),
 
 	SET_DMA_LIODN(1, 147),
 	SET_DMA_LIODN(2, 227),
diff --git a/arch/powerpc/cpu/mpc85xx/traps.c b/arch/powerpc/cpu/mpc85xx/traps.c
index 3ef6e4ae16..24adbc3078 100644
--- a/arch/powerpc/cpu/mpc85xx/traps.c
+++ b/arch/powerpc/cpu/mpc85xx/traps.c
@@ -35,7 +35,6 @@ extern unsigned long search_exception_table(unsigned long);
  * amount of memory on the system if we're unable to keep all
  * the memory mapped in.
  */
-extern ulong get_effective_memsize(void);
 #define END_OF_MEM (gd->bd->bi_memstart + get_effective_memsize())
 
 static __inline__ void set_tsr(unsigned long val)
diff --git a/arch/powerpc/cpu/mpc85xx/u-boot-spl.lds b/arch/powerpc/cpu/mpc85xx/u-boot-spl.lds
index bc132673a5..acaa0939ab 100644
--- a/arch/powerpc/cpu/mpc85xx/u-boot-spl.lds
+++ b/arch/powerpc/cpu/mpc85xx/u-boot-spl.lds
@@ -57,7 +57,14 @@ SECTIONS
 	. = ALIGN(8);
 	__init_begin = .;
 	__init_end = .;
-/* FIXME for non-NAND SPL */
+
+/* For ifc, elbc, esdhc, espi, all need the SPL without section .resetvec */
+#ifdef CONFIG_SYS_MPC85XX_NO_RESETVEC
+	.bootpg ADDR(.text) - 0x1000 :
+	{
+		KEEP(*(.bootpg))
+	} :text = 0xffff
+#else
 #if defined(CONFIG_FSL_IFC) /* Restrict bootpg at 4K boundry for IFC */
 	.bootpg ADDR(.text) + 0x1000 :
 	{
@@ -69,12 +76,6 @@ SECTIONS
 #else
 #error unknown NAND controller
 #endif
-#ifdef CONFIG_SYS_MPC85XX_NO_RESETVEC
-	.bootpg ADDR(.text) - 0x1000 :
-	{
-		KEEP(*(.bootpg))
-	} :text = 0xffff
-#else
 	.resetvec ADDR(.text) + RESET_VECTOR_OFFSET : {
 		KEEP(*(.resetvec))
 	} = 0xffff
diff --git a/arch/powerpc/cpu/mpc86xx/Makefile b/arch/powerpc/cpu/mpc86xx/Makefile
index 04271b0f0c..0f790b0efc 100644
--- a/arch/powerpc/cpu/mpc86xx/Makefile
+++ b/arch/powerpc/cpu/mpc86xx/Makefile
@@ -8,42 +8,17 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(CPU).o
-
-SSTART	= start.o
-CSTART	= traps.o
-
-SOBJS-y += cache.o
-SOBJS-$(CONFIG_MP) += release.o
-
-COBJS-y	+= cpu.o
-COBJS-y	+= cpu_init.o
-# 8610 & 8641 are identical w/regards to DDR
-COBJS-$(CONFIG_MPC8610) += ddr-8641.o
-COBJS-$(CONFIG_MPC8641) += ddr-8641.o
-COBJS-$(CONFIG_OF_LIBFDT) += fdt.o
-COBJS-y	+= interrupts.o
-COBJS-$(CONFIG_MP) += mp.o
-COBJS-$(CONFIG_MPC8610) += mpc8610_serdes.o
-COBJS-$(CONFIG_MPC8641) += mpc8641_serdes.o
-COBJS-y	+= speed.o
-
-SRCS	:= $(START:.o=.S) $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
-OBJS	:= $(addprefix $(obj),$(SOBJS-y) $(COBJS-y))
-START	:= $(addprefix $(obj),$(SSTART) $(CSTART))
-
-all:	$(obj).depend $(START) $(LIB)
-
-$(LIB):	$(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+extra-y	= start.o
+extra-y	+= traps.o
+
+obj-y += cache.o
+obj-$(CONFIG_MP) += release.o
+
+obj-y	+= cpu.o
+obj-y	+= cpu_init.o
+obj-$(CONFIG_OF_LIBFDT) += fdt.o
+obj-y	+= interrupts.o
+obj-$(CONFIG_MP) += mp.o
+obj-$(CONFIG_MPC8610) += mpc8610_serdes.o
+obj-$(CONFIG_MPC8641) += mpc8641_serdes.o
+obj-y	+= speed.o
diff --git a/arch/powerpc/cpu/mpc86xx/config.mk b/arch/powerpc/cpu/mpc86xx/config.mk
index 5dbf6a8472..4c7235fcde 100644
--- a/arch/powerpc/cpu/mpc86xx/config.mk
+++ b/arch/powerpc/cpu/mpc86xx/config.mk
@@ -5,7 +5,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-PLATFORM_RELFLAGS += -meabi
-
-PLATFORM_CPPFLAGS += -ffixed-r2 -mstring
-PLATFORM_CPPFLAGS += -maltivec -mabi=altivec -msoft-float
+PLATFORM_CPPFLAGS += -DCONFIG_MPC86xx -mstring -maltivec -mabi=altivec -msoft-float
diff --git a/arch/powerpc/cpu/mpc86xx/ddr-8641.c b/arch/powerpc/cpu/mpc86xx/ddr-8641.c
deleted file mode 100644
index 33a91f9f78..0000000000
--- a/arch/powerpc/cpu/mpc86xx/ddr-8641.c
+++ /dev/null
@@ -1,85 +0,0 @@
-/*
- * Copyright 2008 Freescale Semiconductor, Inc.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * Version 2 as published by the Free Software Foundation.
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/fsl_ddr_sdram.h>
-
-#if (CONFIG_CHIP_SELECTS_PER_CTRL > 4)
-#error Invalid setting for CONFIG_CHIP_SELECTS_PER_CTRL
-#endif
-
-void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
-			     unsigned int ctrl_num, int step)
-{
-	unsigned int i;
-	volatile ccsr_ddr_t *ddr;
-
-	switch (ctrl_num) {
-	case 0:
-		ddr = (void *)CONFIG_SYS_MPC8xxx_DDR_ADDR;
-		break;
-	case 1:
-		ddr = (void *)CONFIG_SYS_MPC8xxx_DDR2_ADDR;
-		break;
-	default:
-		printf("%s unexpected ctrl_num = %u\n", __FUNCTION__, ctrl_num);
-		return;
-	}
-
-	for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
-		if (i == 0) {
-			out_be32(&ddr->cs0_bnds, regs->cs[i].bnds);
-			out_be32(&ddr->cs0_config, regs->cs[i].config);
-
-		} else if (i == 1) {
-			out_be32(&ddr->cs1_bnds, regs->cs[i].bnds);
-			out_be32(&ddr->cs1_config, regs->cs[i].config);
-
-		} else if (i == 2) {
-			out_be32(&ddr->cs2_bnds, regs->cs[i].bnds);
-			out_be32(&ddr->cs2_config, regs->cs[i].config);
-
-		} else if (i == 3) {
-			out_be32(&ddr->cs3_bnds, regs->cs[i].bnds);
-			out_be32(&ddr->cs3_config, regs->cs[i].config);
-		}
-	}
-
-	out_be32(&ddr->timing_cfg_3, regs->timing_cfg_3);
-	out_be32(&ddr->timing_cfg_0, regs->timing_cfg_0);
-	out_be32(&ddr->timing_cfg_1, regs->timing_cfg_1);
-	out_be32(&ddr->timing_cfg_2, regs->timing_cfg_2);
-	out_be32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2);
-	out_be32(&ddr->sdram_mode, regs->ddr_sdram_mode);
-	out_be32(&ddr->sdram_mode_2, regs->ddr_sdram_mode_2);
-	out_be32(&ddr->sdram_mode_cntl, regs->ddr_sdram_md_cntl);
-	out_be32(&ddr->sdram_interval, regs->ddr_sdram_interval);
-	out_be32(&ddr->sdram_data_init, regs->ddr_data_init);
-	out_be32(&ddr->sdram_clk_cntl, regs->ddr_sdram_clk_cntl);
-	out_be32(&ddr->init_addr, regs->ddr_init_addr);
-	out_be32(&ddr->init_ext_addr, regs->ddr_init_ext_addr);
-
-	debug("before go\n");
-
-	/*
-	 * 200 painful micro-seconds must elapse between
-	 * the DDR clock setup and the DDR config enable.
-	 */
-	udelay(200);
-	asm volatile("sync;isync");
-
-	out_be32(&ddr->sdram_cfg, regs->ddr_sdram_cfg);
-
-	/*
-	 * Poll DDR_SDRAM_CFG_2[D_INIT] bit until auto-data init is done
-	 */
-	while (in_be32(&ddr->sdram_cfg_2) & 0x10) {
-		udelay(10000);		/* throttle polling rate */
-	}
-}
diff --git a/arch/powerpc/cpu/mpc86xx/traps.c b/arch/powerpc/cpu/mpc86xx/traps.c
index 0b7ea3b184..92fb537453 100644
--- a/arch/powerpc/cpu/mpc86xx/traps.c
+++ b/arch/powerpc/cpu/mpc86xx/traps.c
@@ -29,7 +29,6 @@ extern unsigned long search_exception_table(unsigned long);
  * amount of memory on the system if we're unable to keep all
  * the memory mapped in.
  */
-extern ulong get_effective_memsize(void);
 #define END_OF_MEM (gd->bd->bi_memstart + get_effective_memsize())
 
 /*
diff --git a/arch/powerpc/cpu/mpc8xx/Makefile b/arch/powerpc/cpu/mpc8xx/Makefile
index 71d5e302ca..f83fd5ecf4 100644
--- a/arch/powerpc/cpu/mpc8xx/Makefile
+++ b/arch/powerpc/cpu/mpc8xx/Makefile
@@ -5,45 +5,23 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-# CFLAGS += -DET_DEBUG
-
-LIB	= $(obj)lib$(CPU).o
-
-SSTART-y += start.o
-CSTART-y += traps.o
-COBJS-y	+= bedbug_860.o
-COBJS-y	+= commproc.o
-COBJS-y	+= cpu.o
-COBJS-y	+= cpu_init.o
-COBJS-y	+= fec.o
-COBJS-$(CONFIG_OF_LIBFDT) += fdt.o
-COBJS-y	+= i2c.o
-COBJS-y	+= interrupts.o
-COBJS-y	+= scc.o
-COBJS-y	+= serial.o
-COBJS-y	+= speed.o
-COBJS-y	+= spi.o
-COBJS-y	+= upatch.o
-COBJS-y	+= video.o
-SOBJS-y	+= kgdb.o
-SOBJS-y	+= plprcr_write.o
-
-SRCS	:= $(SSTART-y:.o=.S) $(CSTART-y:.o=.c) $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
-OBJS	:= $(addprefix $(obj),$(SOBJS-y) $(COBJS-y))
-START	:= $(addprefix $(obj),$(SSTART-y) $(CSTART-y))
-
-all:	$(obj).depend $(START) $(LIB)
-
-$(LIB):	$(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+# ccflags-y += -DET_DEBUG
+
+extra-y += start.o
+extra-y += traps.o
+obj-y	+= bedbug_860.o
+obj-y	+= commproc.o
+obj-y	+= cpu.o
+obj-y	+= cpu_init.o
+obj-y	+= fec.o
+obj-$(CONFIG_OF_LIBFDT) += fdt.o
+obj-y	+= i2c.o
+obj-y	+= interrupts.o
+obj-y	+= scc.o
+obj-y	+= serial.o
+obj-y	+= speed.o
+obj-y	+= spi.o
+obj-y	+= upatch.o
+obj-y	+= video.o
+obj-y	+= kgdb.o
+obj-y	+= plprcr_write.o
diff --git a/arch/powerpc/cpu/mpc8xx/config.mk b/arch/powerpc/cpu/mpc8xx/config.mk
index c04e7338c8..ee2c883665 100644
--- a/arch/powerpc/cpu/mpc8xx/config.mk
+++ b/arch/powerpc/cpu/mpc8xx/config.mk
@@ -5,6 +5,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-PLATFORM_RELFLAGS += -meabi
-
-PLATFORM_CPPFLAGS += -DCONFIG_8xx -ffixed-r2 -mstring -mcpu=860 -msoft-float
+PLATFORM_CPPFLAGS += -DCONFIG_8xx -mstring -mcpu=860 -msoft-float
diff --git a/arch/powerpc/cpu/mpc8xx/kgdb.S b/arch/powerpc/cpu/mpc8xx/kgdb.S
index ea27d59a6c..e774d1e70a 100644
--- a/arch/powerpc/cpu/mpc8xx/kgdb.S
+++ b/arch/powerpc/cpu/mpc8xx/kgdb.S
@@ -9,9 +9,6 @@
 #include <mpc8xx.h>
 #include <version.h>
 
-#define CONFIG_8xx 1		/* needed for Linux kernel header files */
-#define _LINUX_CONFIG_H 1	/* avoid reading Linux autoconf.h file	*/
-
 #include <ppc_asm.tmpl>
 #include <ppc_defs.h>
 
diff --git a/arch/powerpc/cpu/mpc8xx/start.S b/arch/powerpc/cpu/mpc8xx/start.S
index 9869bbd183..f8aa93d611 100644
--- a/arch/powerpc/cpu/mpc8xx/start.S
+++ b/arch/powerpc/cpu/mpc8xx/start.S
@@ -26,9 +26,6 @@
 #include <mpc8xx.h>
 #include <version.h>
 
-#define CONFIG_8xx 1		/* needed for Linux kernel header files */
-#define _LINUX_CONFIG_H 1	/* avoid reading Linux autoconf.h file	*/
-
 #include <ppc_asm.tmpl>
 #include <ppc_defs.h>
 
diff --git a/arch/powerpc/cpu/mpc8xxx/Makefile b/arch/powerpc/cpu/mpc8xxx/Makefile
index 3dc8e055b6..e95539e0a3 100644
--- a/arch/powerpc/cpu/mpc8xxx/Makefile
+++ b/arch/powerpc/cpu/mpc8xxx/Makefile
@@ -6,10 +6,6 @@
 # Version 2 as published by the Free Software Foundation.
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib8xxx.o
-
 MINIMAL=
 
 ifdef CONFIG_SPL_BUILD
@@ -20,30 +16,15 @@ endif
 
 ifdef MINIMAL
 
-COBJS-$(CONFIG_FSL_LAW) += law.o
+obj-$(CONFIG_FSL_LAW) += law.o
 
 else
+obj-$(CONFIG_MPC85xx) += cpu.o
+obj-$(CONFIG_MPC86xx) += cpu.o
 
-ifneq ($(CPU),mpc83xx)
-COBJS-y	+= cpu.o
-endif
-
-COBJS-$(CONFIG_OF_LIBFDT) += fdt.o
-COBJS-$(CONFIG_FSL_IFC) += fsl_ifc.o
-COBJS-$(CONFIG_FSL_LBC) += fsl_lbc.o
-COBJS-$(CONFIG_SYS_SRIO) += srio.o
-COBJS-$(CONFIG_FSL_LAW) += law.o
+obj-$(CONFIG_OF_LIBFDT) += fdt.o
+obj-$(CONFIG_FSL_LBC) += fsl_lbc.o
+obj-$(CONFIG_SYS_SRIO) += srio.o
+obj-$(CONFIG_FSL_LAW) += law.o
 
 endif
-
-SRCS	:= $(START:.o=.S) $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
-OBJS	:= $(addprefix $(obj),$(SOBJS-y) $(COBJS-y))
-
-all:	$(obj).depend $(LIB)
-
-$(LIB):	$(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
diff --git a/arch/powerpc/cpu/mpc8xxx/cpu.c b/arch/powerpc/cpu/mpc8xxx/cpu.c
index c67be4ef29..35795c4fbe 100644
--- a/arch/powerpc/cpu/mpc8xxx/cpu.c
+++ b/arch/powerpc/cpu/mpc8xxx/cpu.c
@@ -75,6 +75,8 @@ static struct cpu_type cpu_type_list[] = {
 	CPU_TYPE_ENTRY(T1020, T1020, 0),
 	CPU_TYPE_ENTRY(T1021, T1021, 0),
 	CPU_TYPE_ENTRY(T1022, T1022, 0),
+	CPU_TYPE_ENTRY(T2080, T2080, 0),
+	CPU_TYPE_ENTRY(T2081, T2081, 0),
 	CPU_TYPE_ENTRY(BSC9130, 9130, 1),
 	CPU_TYPE_ENTRY(BSC9131, 9131, 1),
 	CPU_TYPE_ENTRY(BSC9132, 9132, 2),
diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/Makefile b/arch/powerpc/cpu/mpc8xxx/ddr/Makefile
deleted file mode 100644
index 29523aa913..0000000000
--- a/arch/powerpc/cpu/mpc8xxx/ddr/Makefile
+++ /dev/null
@@ -1,45 +0,0 @@
-#
-# Copyright 2008-2011 Freescale Semiconductor, Inc.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License
-# Version 2 as published by the Free Software Foundation.
-#
-
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)libddr.o
-
-COBJS-$(CONFIG_FSL_DDR1)	+= main.o util.o ctrl_regs.o options.o \
-				   lc_common_dimm_params.o
-
-COBJS-$(CONFIG_FSL_DDR2)	+= main.o util.o ctrl_regs.o options.o \
-				   lc_common_dimm_params.o
-
-COBJS-$(CONFIG_FSL_DDR3)	+= main.o util.o ctrl_regs.o options.o \
-				   lc_common_dimm_params.o
-ifdef CONFIG_DDR_SPD
-SPD := y
-endif
-ifdef CONFIG_SPD_EEPROM
-SPD := y
-endif
-ifdef SPD
-COBJS-$(CONFIG_FSL_DDR1)	+= ddr1_dimm_params.o
-COBJS-$(CONFIG_FSL_DDR2)	+= ddr2_dimm_params.o
-COBJS-$(CONFIG_FSL_DDR3)	+= ddr3_dimm_params.o
-endif
-
-COBJS-$(CONFIG_FSL_DDR_INTERACTIVE) += interactive.o
-
-SRCS	:= $(START:.o=.S) $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
-OBJS	:= $(addprefix $(obj),$(SOBJS-y) $(COBJS-y))
-
-all:	$(obj).depend $(LIB)
-
-$(LIB):	$(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/common_timing_params.h b/arch/powerpc/cpu/mpc8xxx/ddr/common_timing_params.h
deleted file mode 100644
index 06706ed78c..0000000000
--- a/arch/powerpc/cpu/mpc8xxx/ddr/common_timing_params.h
+++ /dev/null
@@ -1,56 +0,0 @@
-/*
- * Copyright 2008 Freescale Semiconductor, Inc.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * Version 2 as published by the Free Software Foundation.
- */
-
-#ifndef COMMON_TIMING_PARAMS_H
-#define COMMON_TIMING_PARAMS_H
-
-typedef struct {
-	/* parameters to constrict */
-
-	unsigned int tCKmin_X_ps;
-	unsigned int tCKmax_ps;
-	unsigned int tCKmax_max_ps;
-	unsigned int tRCD_ps;
-	unsigned int tRP_ps;
-	unsigned int tRAS_ps;
-
-	unsigned int tWR_ps;	/* maximum = 63750 ps */
-	unsigned int tWTR_ps;	/* maximum = 63750 ps */
-	unsigned int tRFC_ps;	/* maximum = 255 ns + 256 ns + .75 ns
-					   = 511750 ps */
-
-	unsigned int tRRD_ps;	/* maximum = 63750 ps */
-	unsigned int tRC_ps;	/* maximum = 254 ns + .75 ns = 254750 ps */
-
-	unsigned int refresh_rate_ps;
-
-	unsigned int tIS_ps;	/* byte 32, spd->ca_setup */
-	unsigned int tIH_ps;	/* byte 33, spd->ca_hold */
-	unsigned int tDS_ps;	/* byte 34, spd->data_setup */
-	unsigned int tDH_ps;	/* byte 35, spd->data_hold */
-	unsigned int tRTP_ps;	/* byte 38, spd->trtp */
-	unsigned int tDQSQ_max_ps;	/* byte 44, spd->tdqsq */
-	unsigned int tQHS_ps;	/* byte 45, spd->tqhs */
-
-	unsigned int ndimms_present;
-	unsigned int lowest_common_SPD_caslat;
-	unsigned int highest_common_derated_caslat;
-	unsigned int additive_latency;
-	unsigned int all_DIMMs_burst_lengths_bitmask;
-	unsigned int all_DIMMs_registered;
-	unsigned int all_DIMMs_unbuffered;
-	unsigned int all_DIMMs_ECC_capable;
-
-	unsigned long long total_mem;
-	unsigned long long base_address;
-
-	/* DDR3 RDIMM */
-	unsigned char rcw[16];	/* Register Control Word 0-15 */
-} common_timing_params_t;
-
-#endif
diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c b/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c
deleted file mode 100644
index 242eb47ac3..0000000000
--- a/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c
+++ /dev/null
@@ -1,1651 +0,0 @@
-/*
- * Copyright 2008-2012 Freescale Semiconductor, Inc.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-/*
- * Generic driver for Freescale DDR/DDR2/DDR3 memory controller.
- * Based on code from spd_sdram.c
- * Author: James Yang [at freescale.com]
- */
-
-#include <common.h>
-#include <asm/fsl_ddr_sdram.h>
-
-#include "ddr.h"
-
-#define _DDR_ADDR CONFIG_SYS_MPC8xxx_DDR_ADDR
-
-static u32 fsl_ddr_get_version(void)
-{
-	ccsr_ddr_t *ddr;
-	u32 ver_major_minor_errata;
-
-	ddr = (void *)_DDR_ADDR;
-	ver_major_minor_errata = (in_be32(&ddr->ip_rev1) & 0xFFFF) << 8;
-	ver_major_minor_errata |= (in_be32(&ddr->ip_rev2) & 0xFF00) >> 8;
-
-	return ver_major_minor_errata;
-}
-
-unsigned int picos_to_mclk(unsigned int picos);
-
-/*
- * Determine Rtt value.
- *
- * This should likely be either board or controller specific.
- *
- * Rtt(nominal) - DDR2:
- *	0 = Rtt disabled
- *	1 = 75 ohm
- *	2 = 150 ohm
- *	3 = 50 ohm
- * Rtt(nominal) - DDR3:
- *	0 = Rtt disabled
- *	1 = 60 ohm
- *	2 = 120 ohm
- *	3 = 40 ohm
- *	4 = 20 ohm
- *	5 = 30 ohm
- *
- * FIXME: Apparently 8641 needs a value of 2
- * FIXME: Old code seys if 667 MHz or higher, use 3 on 8572
- *
- * FIXME: There was some effort down this line earlier:
- *
- *	unsigned int i;
- *	for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL/2; i++) {
- *		if (popts->dimmslot[i].num_valid_cs
- *		    && (popts->cs_local_opts[2*i].odt_rd_cfg
- *			|| popts->cs_local_opts[2*i].odt_wr_cfg)) {
- *			rtt = 2;
- *			break;
- *		}
- *	}
- */
-static inline int fsl_ddr_get_rtt(void)
-{
-	int rtt;
-
-#if defined(CONFIG_FSL_DDR1)
-	rtt = 0;
-#elif defined(CONFIG_FSL_DDR2)
-	rtt = 3;
-#else
-	rtt = 0;
-#endif
-
-	return rtt;
-}
-
-/*
- * compute the CAS write latency according to DDR3 spec
- * CWL = 5 if tCK >= 2.5ns
- *       6 if 2.5ns > tCK >= 1.875ns
- *       7 if 1.875ns > tCK >= 1.5ns
- *       8 if 1.5ns > tCK >= 1.25ns
- *       9 if 1.25ns > tCK >= 1.07ns
- *       10 if 1.07ns > tCK >= 0.935ns
- *       11 if 0.935ns > tCK >= 0.833ns
- *       12 if 0.833ns > tCK >= 0.75ns
- */
-static inline unsigned int compute_cas_write_latency(void)
-{
-	unsigned int cwl;
-	const unsigned int mclk_ps = get_memory_clk_period_ps();
-
-	if (mclk_ps >= 2500)
-		cwl = 5;
-	else if (mclk_ps >= 1875)
-		cwl = 6;
-	else if (mclk_ps >= 1500)
-		cwl = 7;
-	else if (mclk_ps >= 1250)
-		cwl = 8;
-	else if (mclk_ps >= 1070)
-		cwl = 9;
-	else if (mclk_ps >= 935)
-		cwl = 10;
-	else if (mclk_ps >= 833)
-		cwl = 11;
-	else if (mclk_ps >= 750)
-		cwl = 12;
-	else {
-		cwl = 12;
-		printf("Warning: CWL is out of range\n");
-	}
-	return cwl;
-}
-
-/* Chip Select Configuration (CSn_CONFIG) */
-static void set_csn_config(int dimm_number, int i, fsl_ddr_cfg_regs_t *ddr,
-			       const memctl_options_t *popts,
-			       const dimm_params_t *dimm_params)
-{
-	unsigned int cs_n_en = 0; /* Chip Select enable */
-	unsigned int intlv_en = 0; /* Memory controller interleave enable */
-	unsigned int intlv_ctl = 0; /* Interleaving control */
-	unsigned int ap_n_en = 0; /* Chip select n auto-precharge enable */
-	unsigned int odt_rd_cfg = 0; /* ODT for reads configuration */
-	unsigned int odt_wr_cfg = 0; /* ODT for writes configuration */
-	unsigned int ba_bits_cs_n = 0; /* Num of bank bits for SDRAM on CSn */
-	unsigned int row_bits_cs_n = 0; /* Num of row bits for SDRAM on CSn */
-	unsigned int col_bits_cs_n = 0; /* Num of ocl bits for SDRAM on CSn */
-	int go_config = 0;
-
-	/* Compute CS_CONFIG only for existing ranks of each DIMM.  */
-	switch (i) {
-	case 0:
-		if (dimm_params[dimm_number].n_ranks > 0) {
-			go_config = 1;
-			/* These fields only available in CS0_CONFIG */
-			if (!popts->memctl_interleaving)
-				break;
-			switch (popts->memctl_interleaving_mode) {
-			case FSL_DDR_CACHE_LINE_INTERLEAVING:
-			case FSL_DDR_PAGE_INTERLEAVING:
-			case FSL_DDR_BANK_INTERLEAVING:
-			case FSL_DDR_SUPERBANK_INTERLEAVING:
-				intlv_en = popts->memctl_interleaving;
-				intlv_ctl = popts->memctl_interleaving_mode;
-				break;
-			default:
-				break;
-			}
-		}
-		break;
-	case 1:
-		if ((dimm_number == 0 && dimm_params[0].n_ranks > 1) || \
-		    (dimm_number == 1 && dimm_params[1].n_ranks > 0))
-			go_config = 1;
-		break;
-	case 2:
-		if ((dimm_number == 0 && dimm_params[0].n_ranks > 2) || \
-		   (dimm_number >= 1 && dimm_params[dimm_number].n_ranks > 0))
-			go_config = 1;
-		break;
-	case 3:
-		if ((dimm_number == 0 && dimm_params[0].n_ranks > 3) || \
-		    (dimm_number == 1 && dimm_params[1].n_ranks > 1) || \
-		    (dimm_number == 3 && dimm_params[3].n_ranks > 0))
-			go_config = 1;
-		break;
-	default:
-		break;
-	}
-	if (go_config) {
-		unsigned int n_banks_per_sdram_device;
-		cs_n_en = 1;
-		ap_n_en = popts->cs_local_opts[i].auto_precharge;
-		odt_rd_cfg = popts->cs_local_opts[i].odt_rd_cfg;
-		odt_wr_cfg = popts->cs_local_opts[i].odt_wr_cfg;
-		n_banks_per_sdram_device
-			= dimm_params[dimm_number].n_banks_per_sdram_device;
-		ba_bits_cs_n = __ilog2(n_banks_per_sdram_device) - 2;
-		row_bits_cs_n = dimm_params[dimm_number].n_row_addr - 12;
-		col_bits_cs_n = dimm_params[dimm_number].n_col_addr - 8;
-	}
-	ddr->cs[i].config = (0
-		| ((cs_n_en & 0x1) << 31)
-		| ((intlv_en & 0x3) << 29)
-		| ((intlv_ctl & 0xf) << 24)
-		| ((ap_n_en & 0x1) << 23)
-
-		/* XXX: some implementation only have 1 bit starting at left */
-		| ((odt_rd_cfg & 0x7) << 20)
-
-		/* XXX: Some implementation only have 1 bit starting at left */
-		| ((odt_wr_cfg & 0x7) << 16)
-
-		| ((ba_bits_cs_n & 0x3) << 14)
-		| ((row_bits_cs_n & 0x7) << 8)
-		| ((col_bits_cs_n & 0x7) << 0)
-		);
-	debug("FSLDDR: cs[%d]_config = 0x%08x\n", i,ddr->cs[i].config);
-}
-
-/* Chip Select Configuration 2 (CSn_CONFIG_2) */
-/* FIXME: 8572 */
-static void set_csn_config_2(int i, fsl_ddr_cfg_regs_t *ddr)
-{
-	unsigned int pasr_cfg = 0;	/* Partial array self refresh config */
-
-	ddr->cs[i].config_2 = ((pasr_cfg & 7) << 24);
-	debug("FSLDDR: cs[%d]_config_2 = 0x%08x\n", i, ddr->cs[i].config_2);
-}
-
-/* -3E = 667 CL5, -25 = CL6 800, -25E = CL5 800 */
-
-#if !defined(CONFIG_FSL_DDR1)
-static inline int avoid_odt_overlap(const dimm_params_t *dimm_params)
-{
-#if CONFIG_DIMM_SLOTS_PER_CTLR == 1
-	if (dimm_params[0].n_ranks == 4)
-		return 1;
-#endif
-
-#if CONFIG_DIMM_SLOTS_PER_CTLR == 2
-	if ((dimm_params[0].n_ranks == 2) &&
-		(dimm_params[1].n_ranks == 2))
-		return 1;
-
-#ifdef CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
-	if (dimm_params[0].n_ranks == 4)
-		return 1;
-#endif
-#endif
-	return 0;
-}
-
-/*
- * DDR SDRAM Timing Configuration 0 (TIMING_CFG_0)
- *
- * Avoid writing for DDR I.  The new PQ38 DDR controller
- * dreams up non-zero default values to be backwards compatible.
- */
-static void set_timing_cfg_0(fsl_ddr_cfg_regs_t *ddr,
-				const memctl_options_t *popts,
-				const dimm_params_t *dimm_params)
-{
-	unsigned char trwt_mclk = 0;   /* Read-to-write turnaround */
-	unsigned char twrt_mclk = 0;   /* Write-to-read turnaround */
-	/* 7.5 ns on -3E; 0 means WL - CL + BL/2 + 1 */
-	unsigned char trrt_mclk = 0;   /* Read-to-read turnaround */
-	unsigned char twwt_mclk = 0;   /* Write-to-write turnaround */
-
-	/* Active powerdown exit timing (tXARD and tXARDS). */
-	unsigned char act_pd_exit_mclk;
-	/* Precharge powerdown exit timing (tXP). */
-	unsigned char pre_pd_exit_mclk;
-	/* ODT powerdown exit timing (tAXPD). */
-	unsigned char taxpd_mclk;
-	/* Mode register set cycle time (tMRD). */
-	unsigned char tmrd_mclk;
-
-#ifdef CONFIG_FSL_DDR3
-	/*
-	 * (tXARD and tXARDS). Empirical?
-	 * The DDR3 spec has not tXARD,
-	 * we use the tXP instead of it.
-	 * tXP=max(3nCK, 7.5ns) for DDR3.
-	 * spec has not the tAXPD, we use
-	 * tAXPD=1, need design to confirm.
-	 */
-	int tXP = max((get_memory_clk_period_ps() * 3), 7500); /* unit=ps */
-	unsigned int data_rate = get_ddr_freq(0);
-	tmrd_mclk = 4;
-	/* set the turnaround time */
-
-	/*
-	 * for single quad-rank DIMM and two dual-rank DIMMs
-	 * to avoid ODT overlap
-	 */
-	if (avoid_odt_overlap(dimm_params)) {
-		twwt_mclk = 2;
-		trrt_mclk = 1;
-	}
-	/* for faster clock, need more time for data setup */
-	trwt_mclk = (data_rate/1000000 > 1800) ? 2 : 1;
-
-	if ((data_rate/1000000 > 1150) || (popts->memctl_interleaving))
-		twrt_mclk = 1;
-
-	if (popts->dynamic_power == 0) {	/* powerdown is not used */
-		act_pd_exit_mclk = 1;
-		pre_pd_exit_mclk = 1;
-		taxpd_mclk = 1;
-	} else {
-		/* act_pd_exit_mclk = tXARD, see above */
-		act_pd_exit_mclk = picos_to_mclk(tXP);
-		/* Mode register MR0[A12] is '1' - fast exit */
-		pre_pd_exit_mclk = act_pd_exit_mclk;
-		taxpd_mclk = 1;
-	}
-#else /* CONFIG_FSL_DDR2 */
-	/*
-	 * (tXARD and tXARDS). Empirical?
-	 * tXARD = 2 for DDR2
-	 * tXP=2
-	 * tAXPD=8
-	 */
-	act_pd_exit_mclk = 2;
-	pre_pd_exit_mclk = 2;
-	taxpd_mclk = 8;
-	tmrd_mclk = 2;
-#endif
-
-	if (popts->trwt_override)
-		trwt_mclk = popts->trwt;
-
-	ddr->timing_cfg_0 = (0
-		| ((trwt_mclk & 0x3) << 30)	/* RWT */
-		| ((twrt_mclk & 0x3) << 28)	/* WRT */
-		| ((trrt_mclk & 0x3) << 26)	/* RRT */
-		| ((twwt_mclk & 0x3) << 24)	/* WWT */
-		| ((act_pd_exit_mclk & 0x7) << 20)  /* ACT_PD_EXIT */
-		| ((pre_pd_exit_mclk & 0xF) << 16)  /* PRE_PD_EXIT */
-		| ((taxpd_mclk & 0xf) << 8)	/* ODT_PD_EXIT */
-		| ((tmrd_mclk & 0xf) << 0)	/* MRS_CYC */
-		);
-	debug("FSLDDR: timing_cfg_0 = 0x%08x\n", ddr->timing_cfg_0);
-}
-#endif	/* defined(CONFIG_FSL_DDR2) */
-
-/* DDR SDRAM Timing Configuration 3 (TIMING_CFG_3) */
-static void set_timing_cfg_3(fsl_ddr_cfg_regs_t *ddr,
-			       const memctl_options_t *popts,
-			       const common_timing_params_t *common_dimm,
-			       unsigned int cas_latency)
-{
-	/* Extended precharge to activate interval (tRP) */
-	unsigned int ext_pretoact = 0;
-	/* Extended Activate to precharge interval (tRAS) */
-	unsigned int ext_acttopre = 0;
-	/* Extended activate to read/write interval (tRCD) */
-	unsigned int ext_acttorw = 0;
-	/* Extended refresh recovery time (tRFC) */
-	unsigned int ext_refrec;
-	/* Extended MCAS latency from READ cmd */
-	unsigned int ext_caslat = 0;
-	/* Extended last data to precharge interval (tWR) */
-	unsigned int ext_wrrec = 0;
-	/* Control Adjust */
-	unsigned int cntl_adj = 0;
-
-	ext_pretoact = picos_to_mclk(common_dimm->tRP_ps) >> 4;
-	ext_acttopre = picos_to_mclk(common_dimm->tRAS_ps) >> 4;
-	ext_acttorw = picos_to_mclk(common_dimm->tRCD_ps) >> 4;
-	ext_caslat = (2 * cas_latency - 1) >> 4;
-	ext_refrec = (picos_to_mclk(common_dimm->tRFC_ps) - 8) >> 4;
-	/* ext_wrrec only deals with 16 clock and above, or 14 with OTF */
-	ext_wrrec = (picos_to_mclk(common_dimm->tWR_ps) +
-		(popts->OTF_burst_chop_en ? 2 : 0)) >> 4;
-
-	ddr->timing_cfg_3 = (0
-		| ((ext_pretoact & 0x1) << 28)
-		| ((ext_acttopre & 0x3) << 24)
-		| ((ext_acttorw & 0x1) << 22)
-		| ((ext_refrec & 0x1F) << 16)
-		| ((ext_caslat & 0x3) << 12)
-		| ((ext_wrrec & 0x1) << 8)
-		| ((cntl_adj & 0x7) << 0)
-		);
-	debug("FSLDDR: timing_cfg_3 = 0x%08x\n", ddr->timing_cfg_3);
-}
-
-/* DDR SDRAM Timing Configuration 1 (TIMING_CFG_1) */
-static void set_timing_cfg_1(fsl_ddr_cfg_regs_t *ddr,
-			       const memctl_options_t *popts,
-			       const common_timing_params_t *common_dimm,
-			       unsigned int cas_latency)
-{
-	/* Precharge-to-activate interval (tRP) */
-	unsigned char pretoact_mclk;
-	/* Activate to precharge interval (tRAS) */
-	unsigned char acttopre_mclk;
-	/*  Activate to read/write interval (tRCD) */
-	unsigned char acttorw_mclk;
-	/* CASLAT */
-	unsigned char caslat_ctrl;
-	/*  Refresh recovery time (tRFC) ; trfc_low */
-	unsigned char refrec_ctrl;
-	/* Last data to precharge minimum interval (tWR) */
-	unsigned char wrrec_mclk;
-	/* Activate-to-activate interval (tRRD) */
-	unsigned char acttoact_mclk;
-	/* Last write data pair to read command issue interval (tWTR) */
-	unsigned char wrtord_mclk;
-	/* DDR_SDRAM_MODE doesn't support 9,11,13,15 */
-	static const u8 wrrec_table[] = {
-		1, 2, 3, 4, 5, 6, 7, 8, 10, 10, 12, 12, 14, 14, 0, 0};
-
-	pretoact_mclk = picos_to_mclk(common_dimm->tRP_ps);
-	acttopre_mclk = picos_to_mclk(common_dimm->tRAS_ps);
-	acttorw_mclk = picos_to_mclk(common_dimm->tRCD_ps);
-
-	/*
-	 * Translate CAS Latency to a DDR controller field value:
-	 *
-	 *      CAS Lat DDR I   DDR II  Ctrl
-	 *      Clocks  SPD Bit SPD Bit Value
-	 *      ------- ------- ------- -----
-	 *      1.0     0               0001
-	 *      1.5     1               0010
-	 *      2.0     2       2       0011
-	 *      2.5     3               0100
-	 *      3.0     4       3       0101
-	 *      3.5     5               0110
-	 *      4.0             4       0111
-	 *      4.5                     1000
-	 *      5.0             5       1001
-	 */
-#if defined(CONFIG_FSL_DDR1)
-	caslat_ctrl = (cas_latency + 1) & 0x07;
-#elif defined(CONFIG_FSL_DDR2)
-	caslat_ctrl = 2 * cas_latency - 1;
-#else
-	/*
-	 * if the CAS latency more than 8 cycle,
-	 * we need set extend bit for it at
-	 * TIMING_CFG_3[EXT_CASLAT]
-	 */
-	caslat_ctrl = 2 * cas_latency - 1;
-#endif
-
-	refrec_ctrl = picos_to_mclk(common_dimm->tRFC_ps) - 8;
-	wrrec_mclk = picos_to_mclk(common_dimm->tWR_ps);
-
-	if (wrrec_mclk > 16)
-		printf("Error: WRREC doesn't support more than 16 clocks\n");
-	else
-		wrrec_mclk = wrrec_table[wrrec_mclk - 1];
-	if (popts->OTF_burst_chop_en)
-		wrrec_mclk += 2;
-
-	acttoact_mclk = picos_to_mclk(common_dimm->tRRD_ps);
-	/*
-	 * JEDEC has min requirement for tRRD
-	 */
-#if defined(CONFIG_FSL_DDR3)
-	if (acttoact_mclk < 4)
-		acttoact_mclk = 4;
-#endif
-	wrtord_mclk = picos_to_mclk(common_dimm->tWTR_ps);
-	/*
-	 * JEDEC has some min requirements for tWTR
-	 */
-#if defined(CONFIG_FSL_DDR2)
-	if (wrtord_mclk < 2)
-		wrtord_mclk = 2;
-#elif defined(CONFIG_FSL_DDR3)
-	if (wrtord_mclk < 4)
-		wrtord_mclk = 4;
-#endif
-	if (popts->OTF_burst_chop_en)
-		wrtord_mclk += 2;
-
-	ddr->timing_cfg_1 = (0
-		| ((pretoact_mclk & 0x0F) << 28)
-		| ((acttopre_mclk & 0x0F) << 24)
-		| ((acttorw_mclk & 0xF) << 20)
-		| ((caslat_ctrl & 0xF) << 16)
-		| ((refrec_ctrl & 0xF) << 12)
-		| ((wrrec_mclk & 0x0F) << 8)
-		| ((acttoact_mclk & 0x0F) << 4)
-		| ((wrtord_mclk & 0x0F) << 0)
-		);
-	debug("FSLDDR: timing_cfg_1 = 0x%08x\n", ddr->timing_cfg_1);
-}
-
-/* DDR SDRAM Timing Configuration 2 (TIMING_CFG_2) */
-static void set_timing_cfg_2(fsl_ddr_cfg_regs_t *ddr,
-			       const memctl_options_t *popts,
-			       const common_timing_params_t *common_dimm,
-			       unsigned int cas_latency,
-			       unsigned int additive_latency)
-{
-	/* Additive latency */
-	unsigned char add_lat_mclk;
-	/* CAS-to-preamble override */
-	unsigned short cpo;
-	/* Write latency */
-	unsigned char wr_lat;
-	/*  Read to precharge (tRTP) */
-	unsigned char rd_to_pre;
-	/* Write command to write data strobe timing adjustment */
-	unsigned char wr_data_delay;
-	/* Minimum CKE pulse width (tCKE) */
-	unsigned char cke_pls;
-	/* Window for four activates (tFAW) */
-	unsigned short four_act;
-
-	/* FIXME add check that this must be less than acttorw_mclk */
-	add_lat_mclk = additive_latency;
-	cpo = popts->cpo_override;
-
-#if defined(CONFIG_FSL_DDR1)
-	/*
-	 * This is a lie.  It should really be 1, but if it is
-	 * set to 1, bits overlap into the old controller's
-	 * otherwise unused ACSM field.  If we leave it 0, then
-	 * the HW will magically treat it as 1 for DDR 1.  Oh Yea.
-	 */
-	wr_lat = 0;
-#elif defined(CONFIG_FSL_DDR2)
-	wr_lat = cas_latency - 1;
-#else
-	wr_lat = compute_cas_write_latency();
-#endif
-
-	rd_to_pre = picos_to_mclk(common_dimm->tRTP_ps);
-	/*
-	 * JEDEC has some min requirements for tRTP
-	 */
-#if defined(CONFIG_FSL_DDR2)
-	if (rd_to_pre  < 2)
-		rd_to_pre  = 2;
-#elif defined(CONFIG_FSL_DDR3)
-	if (rd_to_pre < 4)
-		rd_to_pre = 4;
-#endif
-	if (additive_latency)
-		rd_to_pre += additive_latency;
-	if (popts->OTF_burst_chop_en)
-		rd_to_pre += 2; /* according to UM */
-
-	wr_data_delay = popts->write_data_delay;
-	cke_pls = picos_to_mclk(popts->tCKE_clock_pulse_width_ps);
-	four_act = picos_to_mclk(popts->tFAW_window_four_activates_ps);
-
-	ddr->timing_cfg_2 = (0
-		| ((add_lat_mclk & 0xf) << 28)
-		| ((cpo & 0x1f) << 23)
-		| ((wr_lat & 0xf) << 19)
-		| ((rd_to_pre & RD_TO_PRE_MASK) << RD_TO_PRE_SHIFT)
-		| ((wr_data_delay & WR_DATA_DELAY_MASK) << WR_DATA_DELAY_SHIFT)
-		| ((cke_pls & 0x7) << 6)
-		| ((four_act & 0x3f) << 0)
-		);
-	debug("FSLDDR: timing_cfg_2 = 0x%08x\n", ddr->timing_cfg_2);
-}
-
-/* DDR SDRAM Register Control Word */
-static void set_ddr_sdram_rcw(fsl_ddr_cfg_regs_t *ddr,
-			       const memctl_options_t *popts,
-			       const common_timing_params_t *common_dimm)
-{
-	if (common_dimm->all_DIMMs_registered
-		&& !common_dimm->all_DIMMs_unbuffered) {
-		if (popts->rcw_override) {
-			ddr->ddr_sdram_rcw_1 = popts->rcw_1;
-			ddr->ddr_sdram_rcw_2 = popts->rcw_2;
-		} else {
-			ddr->ddr_sdram_rcw_1 =
-				common_dimm->rcw[0] << 28 | \
-				common_dimm->rcw[1] << 24 | \
-				common_dimm->rcw[2] << 20 | \
-				common_dimm->rcw[3] << 16 | \
-				common_dimm->rcw[4] << 12 | \
-				common_dimm->rcw[5] << 8 | \
-				common_dimm->rcw[6] << 4 | \
-				common_dimm->rcw[7];
-			ddr->ddr_sdram_rcw_2 =
-				common_dimm->rcw[8] << 28 | \
-				common_dimm->rcw[9] << 24 | \
-				common_dimm->rcw[10] << 20 | \
-				common_dimm->rcw[11] << 16 | \
-				common_dimm->rcw[12] << 12 | \
-				common_dimm->rcw[13] << 8 | \
-				common_dimm->rcw[14] << 4 | \
-				common_dimm->rcw[15];
-		}
-		debug("FSLDDR: ddr_sdram_rcw_1 = 0x%08x\n", ddr->ddr_sdram_rcw_1);
-		debug("FSLDDR: ddr_sdram_rcw_2 = 0x%08x\n", ddr->ddr_sdram_rcw_2);
-	}
-}
-
-/* DDR SDRAM control configuration (DDR_SDRAM_CFG) */
-static void set_ddr_sdram_cfg(fsl_ddr_cfg_regs_t *ddr,
-			       const memctl_options_t *popts,
-			       const common_timing_params_t *common_dimm)
-{
-	unsigned int mem_en;		/* DDR SDRAM interface logic enable */
-	unsigned int sren;		/* Self refresh enable (during sleep) */
-	unsigned int ecc_en;		/* ECC enable. */
-	unsigned int rd_en;		/* Registered DIMM enable */
-	unsigned int sdram_type;	/* Type of SDRAM */
-	unsigned int dyn_pwr;		/* Dynamic power management mode */
-	unsigned int dbw;		/* DRAM dta bus width */
-	unsigned int eight_be = 0;	/* 8-beat burst enable, DDR2 is zero */
-	unsigned int ncap = 0;		/* Non-concurrent auto-precharge */
-	unsigned int threeT_en;		/* Enable 3T timing */
-	unsigned int twoT_en;		/* Enable 2T timing */
-	unsigned int ba_intlv_ctl;	/* Bank (CS) interleaving control */
-	unsigned int x32_en = 0;	/* x32 enable */
-	unsigned int pchb8 = 0;		/* precharge bit 8 enable */
-	unsigned int hse;		/* Global half strength override */
-	unsigned int mem_halt = 0;	/* memory controller halt */
-	unsigned int bi = 0;		/* Bypass initialization */
-
-	mem_en = 1;
-	sren = popts->self_refresh_in_sleep;
-	if (common_dimm->all_DIMMs_ECC_capable) {
-		/* Allow setting of ECC only if all DIMMs are ECC. */
-		ecc_en = popts->ECC_mode;
-	} else {
-		ecc_en = 0;
-	}
-
-	if (common_dimm->all_DIMMs_registered
-		&& !common_dimm->all_DIMMs_unbuffered) {
-		rd_en = 1;
-		twoT_en = 0;
-	} else {
-		rd_en = 0;
-		twoT_en = popts->twoT_en;
-	}
-
-	sdram_type = CONFIG_FSL_SDRAM_TYPE;
-
-	dyn_pwr = popts->dynamic_power;
-	dbw = popts->data_bus_width;
-	/* 8-beat burst enable DDR-III case
-	 * we must clear it when use the on-the-fly mode,
-	 * must set it when use the 32-bits bus mode.
-	 */
-	if (sdram_type == SDRAM_TYPE_DDR3) {
-		if (popts->burst_length == DDR_BL8)
-			eight_be = 1;
-		if (popts->burst_length == DDR_OTF)
-			eight_be = 0;
-		if (dbw == 0x1)
-			eight_be = 1;
-	}
-
-	threeT_en = popts->threeT_en;
-	ba_intlv_ctl = popts->ba_intlv_ctl;
-	hse = popts->half_strength_driver_enable;
-
-	ddr->ddr_sdram_cfg = (0
-			| ((mem_en & 0x1) << 31)
-			| ((sren & 0x1) << 30)
-			| ((ecc_en & 0x1) << 29)
-			| ((rd_en & 0x1) << 28)
-			| ((sdram_type & 0x7) << 24)
-			| ((dyn_pwr & 0x1) << 21)
-			| ((dbw & 0x3) << 19)
-			| ((eight_be & 0x1) << 18)
-			| ((ncap & 0x1) << 17)
-			| ((threeT_en & 0x1) << 16)
-			| ((twoT_en & 0x1) << 15)
-			| ((ba_intlv_ctl & 0x7F) << 8)
-			| ((x32_en & 0x1) << 5)
-			| ((pchb8 & 0x1) << 4)
-			| ((hse & 0x1) << 3)
-			| ((mem_halt & 0x1) << 1)
-			| ((bi & 0x1) << 0)
-			);
-	debug("FSLDDR: ddr_sdram_cfg = 0x%08x\n", ddr->ddr_sdram_cfg);
-}
-
-/* DDR SDRAM control configuration 2 (DDR_SDRAM_CFG_2) */
-static void set_ddr_sdram_cfg_2(fsl_ddr_cfg_regs_t *ddr,
-			       const memctl_options_t *popts,
-			       const unsigned int unq_mrs_en)
-{
-	unsigned int frc_sr = 0;	/* Force self refresh */
-	unsigned int sr_ie = 0;		/* Self-refresh interrupt enable */
-	unsigned int dll_rst_dis;	/* DLL reset disable */
-	unsigned int dqs_cfg;		/* DQS configuration */
-	unsigned int odt_cfg = 0;	/* ODT configuration */
-	unsigned int num_pr;		/* Number of posted refreshes */
-	unsigned int slow = 0;		/* DDR will be run less than 1250 */
-	unsigned int x4_en = 0;		/* x4 DRAM enable */
-	unsigned int obc_cfg;		/* On-The-Fly Burst Chop Cfg */
-	unsigned int ap_en;		/* Address Parity Enable */
-	unsigned int d_init;		/* DRAM data initialization */
-	unsigned int rcw_en = 0;	/* Register Control Word Enable */
-	unsigned int md_en = 0;		/* Mirrored DIMM Enable */
-	unsigned int qd_en = 0;		/* quad-rank DIMM Enable */
-	int i;
-
-	dll_rst_dis = 1;	/* Make this configurable */
-	dqs_cfg = popts->DQS_config;
-	for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
-		if (popts->cs_local_opts[i].odt_rd_cfg
-			|| popts->cs_local_opts[i].odt_wr_cfg) {
-			odt_cfg = SDRAM_CFG2_ODT_ONLY_READ;
-			break;
-		}
-	}
-
-	num_pr = 1;	/* Make this configurable */
-
-	/*
-	 * 8572 manual says
-	 *     {TIMING_CFG_1[PRETOACT]
-	 *      + [DDR_SDRAM_CFG_2[NUM_PR]
-	 *        * ({EXT_REFREC || REFREC} + 8 + 2)]}
-	 *      << DDR_SDRAM_INTERVAL[REFINT]
-	 */
-#if defined(CONFIG_FSL_DDR3)
-	obc_cfg = popts->OTF_burst_chop_en;
-#else
-	obc_cfg = 0;
-#endif
-
-#if (CONFIG_SYS_FSL_DDR_VER >= FSL_DDR_VER_4_7)
-	slow = get_ddr_freq(0) < 1249000000;
-#endif
-
-	if (popts->registered_dimm_en) {
-		rcw_en = 1;
-		ap_en = popts->ap_en;
-	} else {
-		ap_en = 0;
-	}
-
-	x4_en = popts->x4_en ? 1 : 0;
-
-#if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
-	/* Use the DDR controller to auto initialize memory. */
-	d_init = popts->ECC_init_using_memctl;
-	ddr->ddr_data_init = CONFIG_MEM_INIT_VALUE;
-	debug("DDR: ddr_data_init = 0x%08x\n", ddr->ddr_data_init);
-#else
-	/* Memory will be initialized via DMA, or not at all. */
-	d_init = 0;
-#endif
-
-#if defined(CONFIG_FSL_DDR3)
-	md_en = popts->mirrored_dimm;
-#endif
-	qd_en = popts->quad_rank_present ? 1 : 0;
-	ddr->ddr_sdram_cfg_2 = (0
-		| ((frc_sr & 0x1) << 31)
-		| ((sr_ie & 0x1) << 30)
-		| ((dll_rst_dis & 0x1) << 29)
-		| ((dqs_cfg & 0x3) << 26)
-		| ((odt_cfg & 0x3) << 21)
-		| ((num_pr & 0xf) << 12)
-		| ((slow & 1) << 11)
-		| (x4_en << 10)
-		| (qd_en << 9)
-		| (unq_mrs_en << 8)
-		| ((obc_cfg & 0x1) << 6)
-		| ((ap_en & 0x1) << 5)
-		| ((d_init & 0x1) << 4)
-		| ((rcw_en & 0x1) << 2)
-		| ((md_en & 0x1) << 0)
-		);
-	debug("FSLDDR: ddr_sdram_cfg_2 = 0x%08x\n", ddr->ddr_sdram_cfg_2);
-}
-
-/* DDR SDRAM Mode configuration 2 (DDR_SDRAM_MODE_2) */
-static void set_ddr_sdram_mode_2(fsl_ddr_cfg_regs_t *ddr,
-				const memctl_options_t *popts,
-				const unsigned int unq_mrs_en)
-{
-	unsigned short esdmode2 = 0;	/* Extended SDRAM mode 2 */
-	unsigned short esdmode3 = 0;	/* Extended SDRAM mode 3 */
-
-#if defined(CONFIG_FSL_DDR3)
-	int i;
-	unsigned int rtt_wr = 0;	/* Rtt_WR - dynamic ODT off */
-	unsigned int srt = 0;	/* self-refresh temerature, normal range */
-	unsigned int asr = 0;	/* auto self-refresh disable */
-	unsigned int cwl = compute_cas_write_latency() - 5;
-	unsigned int pasr = 0;	/* partial array self refresh disable */
-
-	if (popts->rtt_override)
-		rtt_wr = popts->rtt_wr_override_value;
-	else
-		rtt_wr = popts->cs_local_opts[0].odt_rtt_wr;
-	esdmode2 = (0
-		| ((rtt_wr & 0x3) << 9)
-		| ((srt & 0x1) << 7)
-		| ((asr & 0x1) << 6)
-		| ((cwl & 0x7) << 3)
-		| ((pasr & 0x7) << 0));
-#endif
-	ddr->ddr_sdram_mode_2 = (0
-				 | ((esdmode2 & 0xFFFF) << 16)
-				 | ((esdmode3 & 0xFFFF) << 0)
-				 );
-	debug("FSLDDR: ddr_sdram_mode_2 = 0x%08x\n", ddr->ddr_sdram_mode_2);
-
-#ifdef CONFIG_FSL_DDR3
-	if (unq_mrs_en) {	/* unique mode registers are supported */
-		for (i = 1; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
-			if (popts->rtt_override)
-				rtt_wr = popts->rtt_wr_override_value;
-			else
-				rtt_wr = popts->cs_local_opts[i].odt_rtt_wr;
-
-			esdmode2 &= 0xF9FF;	/* clear bit 10, 9 */
-			esdmode2 |= (rtt_wr & 0x3) << 9;
-			switch (i) {
-			case 1:
-				ddr->ddr_sdram_mode_4 = (0
-					| ((esdmode2 & 0xFFFF) << 16)
-					| ((esdmode3 & 0xFFFF) << 0)
-					);
-				break;
-			case 2:
-				ddr->ddr_sdram_mode_6 = (0
-					| ((esdmode2 & 0xFFFF) << 16)
-					| ((esdmode3 & 0xFFFF) << 0)
-					);
-				break;
-			case 3:
-				ddr->ddr_sdram_mode_8 = (0
-					| ((esdmode2 & 0xFFFF) << 16)
-					| ((esdmode3 & 0xFFFF) << 0)
-					);
-				break;
-			}
-		}
-		debug("FSLDDR: ddr_sdram_mode_4 = 0x%08x\n",
-			ddr->ddr_sdram_mode_4);
-		debug("FSLDDR: ddr_sdram_mode_6 = 0x%08x\n",
-			ddr->ddr_sdram_mode_6);
-		debug("FSLDDR: ddr_sdram_mode_8 = 0x%08x\n",
-			ddr->ddr_sdram_mode_8);
-	}
-#endif
-}
-
-/* DDR SDRAM Interval Configuration (DDR_SDRAM_INTERVAL) */
-static void set_ddr_sdram_interval(fsl_ddr_cfg_regs_t *ddr,
-			       const memctl_options_t *popts,
-			       const common_timing_params_t *common_dimm)
-{
-	unsigned int refint;	/* Refresh interval */
-	unsigned int bstopre;	/* Precharge interval */
-
-	refint = picos_to_mclk(common_dimm->refresh_rate_ps);
-
-	bstopre = popts->bstopre;
-
-	/* refint field used 0x3FFF in earlier controllers */
-	ddr->ddr_sdram_interval = (0
-				   | ((refint & 0xFFFF) << 16)
-				   | ((bstopre & 0x3FFF) << 0)
-				   );
-	debug("FSLDDR: ddr_sdram_interval = 0x%08x\n", ddr->ddr_sdram_interval);
-}
-
-#if defined(CONFIG_FSL_DDR3)
-/* DDR SDRAM Mode configuration set (DDR_SDRAM_MODE) */
-static void set_ddr_sdram_mode(fsl_ddr_cfg_regs_t *ddr,
-			       const memctl_options_t *popts,
-			       const common_timing_params_t *common_dimm,
-			       unsigned int cas_latency,
-			       unsigned int additive_latency,
-			       const unsigned int unq_mrs_en)
-{
-	unsigned short esdmode;		/* Extended SDRAM mode */
-	unsigned short sdmode;		/* SDRAM mode */
-
-	/* Mode Register - MR1 */
-	unsigned int qoff = 0;		/* Output buffer enable 0=yes, 1=no */
-	unsigned int tdqs_en = 0;	/* TDQS Enable: 0=no, 1=yes */
-	unsigned int rtt;
-	unsigned int wrlvl_en = 0;	/* Write level enable: 0=no, 1=yes */
-	unsigned int al = 0;		/* Posted CAS# additive latency (AL) */
-	unsigned int dic = 0;		/* Output driver impedance, 40ohm */
-	unsigned int dll_en = 0;	/* DLL Enable  0=Enable (Normal),
-						       1=Disable (Test/Debug) */
-
-	/* Mode Register - MR0 */
-	unsigned int dll_on;	/* DLL control for precharge PD, 0=off, 1=on */
-	unsigned int wr = 0;	/* Write Recovery */
-	unsigned int dll_rst;	/* DLL Reset */
-	unsigned int mode;	/* Normal=0 or Test=1 */
-	unsigned int caslat = 4;/* CAS# latency, default set as 6 cycles */
-	/* BT: Burst Type (0=Nibble Sequential, 1=Interleaved) */
-	unsigned int bt;
-	unsigned int bl;	/* BL: Burst Length */
-
-	unsigned int wr_mclk;
-	/*
-	 * DDR_SDRAM_MODE doesn't support 9,11,13,15
-	 * Please refer JEDEC Standard No. 79-3E for Mode Register MR0
-	 * for this table
-	 */
-	static const u8 wr_table[] = {1, 2, 3, 4, 5, 5, 6, 6, 7, 7, 0, 0};
-
-	const unsigned int mclk_ps = get_memory_clk_period_ps();
-	int i;
-
-	if (popts->rtt_override)
-		rtt = popts->rtt_override_value;
-	else
-		rtt = popts->cs_local_opts[0].odt_rtt_norm;
-
-	if (additive_latency == (cas_latency - 1))
-		al = 1;
-	if (additive_latency == (cas_latency - 2))
-		al = 2;
-
-	if (popts->quad_rank_present)
-		dic = 1;	/* output driver impedance 240/7 ohm */
-
-	/*
-	 * The esdmode value will also be used for writing
-	 * MR1 during write leveling for DDR3, although the
-	 * bits specifically related to the write leveling
-	 * scheme will be handled automatically by the DDR
-	 * controller. so we set the wrlvl_en = 0 here.
-	 */
-	esdmode = (0
-		| ((qoff & 0x1) << 12)
-		| ((tdqs_en & 0x1) << 11)
-		| ((rtt & 0x4) << 7)   /* rtt field is split */
-		| ((wrlvl_en & 0x1) << 7)
-		| ((rtt & 0x2) << 5)   /* rtt field is split */
-		| ((dic & 0x2) << 4)   /* DIC field is split */
-		| ((al & 0x3) << 3)
-		| ((rtt & 0x1) << 2)  /* rtt field is split */
-		| ((dic & 0x1) << 1)   /* DIC field is split */
-		| ((dll_en & 0x1) << 0)
-		);
-
-	/*
-	 * DLL control for precharge PD
-	 * 0=slow exit DLL off (tXPDLL)
-	 * 1=fast exit DLL on (tXP)
-	 */
-	dll_on = 1;
-
-	wr_mclk = (common_dimm->tWR_ps + mclk_ps - 1) / mclk_ps;
-	if (wr_mclk <= 16) {
-		wr = wr_table[wr_mclk - 5];
-	} else {
-		printf("Error: unsupported write recovery for mode register "
-		       "wr_mclk = %d\n", wr_mclk);
-	}
-
-	dll_rst = 0;	/* dll no reset */
-	mode = 0;	/* normal mode */
-
-	/* look up table to get the cas latency bits */
-	if (cas_latency >= 5 && cas_latency <= 16) {
-		unsigned char cas_latency_table[] = {
-			0x2,	/* 5 clocks */
-			0x4,	/* 6 clocks */
-			0x6,	/* 7 clocks */
-			0x8,	/* 8 clocks */
-			0xa,	/* 9 clocks */
-			0xc,	/* 10 clocks */
-			0xe,	/* 11 clocks */
-			0x1,	/* 12 clocks */
-			0x3,	/* 13 clocks */
-			0x5,	/* 14 clocks */
-			0x7,	/* 15 clocks */
-			0x9,	/* 16 clocks */
-		};
-		caslat = cas_latency_table[cas_latency - 5];
-	} else {
-		printf("Error: unsupported cas latency for mode register\n");
-	}
-
-	bt = 0;	/* Nibble sequential */
-
-	switch (popts->burst_length) {
-	case DDR_BL8:
-		bl = 0;
-		break;
-	case DDR_OTF:
-		bl = 1;
-		break;
-	case DDR_BC4:
-		bl = 2;
-		break;
-	default:
-		printf("Error: invalid burst length of %u specified. "
-			" Defaulting to on-the-fly BC4 or BL8 beats.\n",
-			popts->burst_length);
-		bl = 1;
-		break;
-	}
-
-	sdmode = (0
-		  | ((dll_on & 0x1) << 12)
-		  | ((wr & 0x7) << 9)
-		  | ((dll_rst & 0x1) << 8)
-		  | ((mode & 0x1) << 7)
-		  | (((caslat >> 1) & 0x7) << 4)
-		  | ((bt & 0x1) << 3)
-		  | ((caslat & 1) << 2)
-		  | ((bl & 0x3) << 0)
-		  );
-
-	ddr->ddr_sdram_mode = (0
-			       | ((esdmode & 0xFFFF) << 16)
-			       | ((sdmode & 0xFFFF) << 0)
-			       );
-
-	debug("FSLDDR: ddr_sdram_mode = 0x%08x\n", ddr->ddr_sdram_mode);
-
-	if (unq_mrs_en) {	/* unique mode registers are supported */
-		for (i = 1; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
-			if (popts->rtt_override)
-				rtt = popts->rtt_override_value;
-			else
-				rtt = popts->cs_local_opts[i].odt_rtt_norm;
-
-			esdmode &= 0xFDBB;	/* clear bit 9,6,2 */
-			esdmode |= (0
-				| ((rtt & 0x4) << 7)   /* rtt field is split */
-				| ((rtt & 0x2) << 5)   /* rtt field is split */
-				| ((rtt & 0x1) << 2)  /* rtt field is split */
-				);
-			switch (i) {
-			case 1:
-				ddr->ddr_sdram_mode_3 = (0
-				       | ((esdmode & 0xFFFF) << 16)
-				       | ((sdmode & 0xFFFF) << 0)
-				       );
-				break;
-			case 2:
-				ddr->ddr_sdram_mode_5 = (0
-				       | ((esdmode & 0xFFFF) << 16)
-				       | ((sdmode & 0xFFFF) << 0)
-				       );
-				break;
-			case 3:
-				ddr->ddr_sdram_mode_7 = (0
-				       | ((esdmode & 0xFFFF) << 16)
-				       | ((sdmode & 0xFFFF) << 0)
-				       );
-				break;
-			}
-		}
-		debug("FSLDDR: ddr_sdram_mode_3 = 0x%08x\n",
-			ddr->ddr_sdram_mode_3);
-		debug("FSLDDR: ddr_sdram_mode_5 = 0x%08x\n",
-			ddr->ddr_sdram_mode_5);
-		debug("FSLDDR: ddr_sdram_mode_5 = 0x%08x\n",
-			ddr->ddr_sdram_mode_5);
-	}
-}
-
-#else /* !CONFIG_FSL_DDR3 */
-
-/* DDR SDRAM Mode configuration set (DDR_SDRAM_MODE) */
-static void set_ddr_sdram_mode(fsl_ddr_cfg_regs_t *ddr,
-			       const memctl_options_t *popts,
-			       const common_timing_params_t *common_dimm,
-			       unsigned int cas_latency,
-			       unsigned int additive_latency,
-			       const unsigned int unq_mrs_en)
-{
-	unsigned short esdmode;		/* Extended SDRAM mode */
-	unsigned short sdmode;		/* SDRAM mode */
-
-	/*
-	 * FIXME: This ought to be pre-calculated in a
-	 * technology-specific routine,
-	 * e.g. compute_DDR2_mode_register(), and then the
-	 * sdmode and esdmode passed in as part of common_dimm.
-	 */
-
-	/* Extended Mode Register */
-	unsigned int mrs = 0;		/* Mode Register Set */
-	unsigned int outputs = 0;	/* 0=Enabled, 1=Disabled */
-	unsigned int rdqs_en = 0;	/* RDQS Enable: 0=no, 1=yes */
-	unsigned int dqs_en = 0;	/* DQS# Enable: 0=enable, 1=disable */
-	unsigned int ocd = 0;		/* 0x0=OCD not supported,
-					   0x7=OCD default state */
-	unsigned int rtt;
-	unsigned int al;		/* Posted CAS# additive latency (AL) */
-	unsigned int ods = 0;		/* Output Drive Strength:
-						0 = Full strength (18ohm)
-						1 = Reduced strength (4ohm) */
-	unsigned int dll_en = 0;	/* DLL Enable  0=Enable (Normal),
-						       1=Disable (Test/Debug) */
-
-	/* Mode Register (MR) */
-	unsigned int mr;	/* Mode Register Definition */
-	unsigned int pd;	/* Power-Down Mode */
-	unsigned int wr;	/* Write Recovery */
-	unsigned int dll_res;	/* DLL Reset */
-	unsigned int mode;	/* Normal=0 or Test=1 */
-	unsigned int caslat = 0;/* CAS# latency */
-	/* BT: Burst Type (0=Sequential, 1=Interleaved) */
-	unsigned int bt;
-	unsigned int bl;	/* BL: Burst Length */
-
-#if defined(CONFIG_FSL_DDR2)
-	const unsigned int mclk_ps = get_memory_clk_period_ps();
-#endif
-	dqs_en = !popts->DQS_config;
-	rtt = fsl_ddr_get_rtt();
-
-	al = additive_latency;
-
-	esdmode = (0
-		| ((mrs & 0x3) << 14)
-		| ((outputs & 0x1) << 12)
-		| ((rdqs_en & 0x1) << 11)
-		| ((dqs_en & 0x1) << 10)
-		| ((ocd & 0x7) << 7)
-		| ((rtt & 0x2) << 5)   /* rtt field is split */
-		| ((al & 0x7) << 3)
-		| ((rtt & 0x1) << 2)   /* rtt field is split */
-		| ((ods & 0x1) << 1)
-		| ((dll_en & 0x1) << 0)
-		);
-
-	mr = 0;		 /* FIXME: CHECKME */
-
-	/*
-	 * 0 = Fast Exit (Normal)
-	 * 1 = Slow Exit (Low Power)
-	 */
-	pd = 0;
-
-#if defined(CONFIG_FSL_DDR1)
-	wr = 0;       /* Historical */
-#elif defined(CONFIG_FSL_DDR2)
-	wr = (common_dimm->tWR_ps + mclk_ps - 1) / mclk_ps - 1;
-#endif
-	dll_res = 0;
-	mode = 0;
-
-#if defined(CONFIG_FSL_DDR1)
-	if (1 <= cas_latency && cas_latency <= 4) {
-		unsigned char mode_caslat_table[4] = {
-			0x5,	/* 1.5 clocks */
-			0x2,	/* 2.0 clocks */
-			0x6,	/* 2.5 clocks */
-			0x3	/* 3.0 clocks */
-		};
-		caslat = mode_caslat_table[cas_latency - 1];
-	} else {
-		printf("Warning: unknown cas_latency %d\n", cas_latency);
-	}
-#elif defined(CONFIG_FSL_DDR2)
-	caslat = cas_latency;
-#endif
-	bt = 0;
-
-	switch (popts->burst_length) {
-	case DDR_BL4:
-		bl = 2;
-		break;
-	case DDR_BL8:
-		bl = 3;
-		break;
-	default:
-		printf("Error: invalid burst length of %u specified. "
-			" Defaulting to 4 beats.\n",
-			popts->burst_length);
-		bl = 2;
-		break;
-	}
-
-	sdmode = (0
-		  | ((mr & 0x3) << 14)
-		  | ((pd & 0x1) << 12)
-		  | ((wr & 0x7) << 9)
-		  | ((dll_res & 0x1) << 8)
-		  | ((mode & 0x1) << 7)
-		  | ((caslat & 0x7) << 4)
-		  | ((bt & 0x1) << 3)
-		  | ((bl & 0x7) << 0)
-		  );
-
-	ddr->ddr_sdram_mode = (0
-			       | ((esdmode & 0xFFFF) << 16)
-			       | ((sdmode & 0xFFFF) << 0)
-			       );
-	debug("FSLDDR: ddr_sdram_mode = 0x%08x\n", ddr->ddr_sdram_mode);
-}
-#endif
-
-/* DDR SDRAM Data Initialization (DDR_DATA_INIT) */
-static void set_ddr_data_init(fsl_ddr_cfg_regs_t *ddr)
-{
-	unsigned int init_value;	/* Initialization value */
-
-#ifdef CONFIG_MEM_INIT_VALUE
-	init_value = CONFIG_MEM_INIT_VALUE;
-#else
-	init_value = 0xDEADBEEF;
-#endif
-	ddr->ddr_data_init = init_value;
-}
-
-/*
- * DDR SDRAM Clock Control (DDR_SDRAM_CLK_CNTL)
- * The old controller on the 8540/60 doesn't have this register.
- * Hope it's OK to set it (to 0) anyway.
- */
-static void set_ddr_sdram_clk_cntl(fsl_ddr_cfg_regs_t *ddr,
-					 const memctl_options_t *popts)
-{
-	unsigned int clk_adjust;	/* Clock adjust */
-
-	clk_adjust = popts->clk_adjust;
-	ddr->ddr_sdram_clk_cntl = (clk_adjust & 0xF) << 23;
-	debug("FSLDDR: clk_cntl = 0x%08x\n", ddr->ddr_sdram_clk_cntl);
-}
-
-/* DDR Initialization Address (DDR_INIT_ADDR) */
-static void set_ddr_init_addr(fsl_ddr_cfg_regs_t *ddr)
-{
-	unsigned int init_addr = 0;	/* Initialization address */
-
-	ddr->ddr_init_addr = init_addr;
-}
-
-/* DDR Initialization Address (DDR_INIT_EXT_ADDR) */
-static void set_ddr_init_ext_addr(fsl_ddr_cfg_regs_t *ddr)
-{
-	unsigned int uia = 0;	/* Use initialization address */
-	unsigned int init_ext_addr = 0;	/* Initialization address */
-
-	ddr->ddr_init_ext_addr = (0
-				  | ((uia & 0x1) << 31)
-				  | (init_ext_addr & 0xF)
-				  );
-}
-
-/* DDR SDRAM Timing Configuration 4 (TIMING_CFG_4) */
-static void set_timing_cfg_4(fsl_ddr_cfg_regs_t *ddr,
-				const memctl_options_t *popts)
-{
-	unsigned int rwt = 0; /* Read-to-write turnaround for same CS */
-	unsigned int wrt = 0; /* Write-to-read turnaround for same CS */
-	unsigned int rrt = 0; /* Read-to-read turnaround for same CS */
-	unsigned int wwt = 0; /* Write-to-write turnaround for same CS */
-	unsigned int dll_lock = 0; /* DDR SDRAM DLL Lock Time */
-
-#if defined(CONFIG_FSL_DDR3)
-	if (popts->burst_length == DDR_BL8) {
-		/* We set BL/2 for fixed BL8 */
-		rrt = 0;	/* BL/2 clocks */
-		wwt = 0;	/* BL/2 clocks */
-	} else {
-		/* We need to set BL/2 + 2 to BC4 and OTF */
-		rrt = 2;	/* BL/2 + 2 clocks */
-		wwt = 2;	/* BL/2 + 2 clocks */
-	}
-	dll_lock = 1;	/* tDLLK = 512 clocks from spec */
-#endif
-	ddr->timing_cfg_4 = (0
-			     | ((rwt & 0xf) << 28)
-			     | ((wrt & 0xf) << 24)
-			     | ((rrt & 0xf) << 20)
-			     | ((wwt & 0xf) << 16)
-			     | (dll_lock & 0x3)
-			     );
-	debug("FSLDDR: timing_cfg_4 = 0x%08x\n", ddr->timing_cfg_4);
-}
-
-/* DDR SDRAM Timing Configuration 5 (TIMING_CFG_5) */
-static void set_timing_cfg_5(fsl_ddr_cfg_regs_t *ddr, unsigned int cas_latency)
-{
-	unsigned int rodt_on = 0;	/* Read to ODT on */
-	unsigned int rodt_off = 0;	/* Read to ODT off */
-	unsigned int wodt_on = 0;	/* Write to ODT on */
-	unsigned int wodt_off = 0;	/* Write to ODT off */
-
-#if defined(CONFIG_FSL_DDR3)
-	/* rodt_on = timing_cfg_1[caslat] - timing_cfg_2[wrlat] + 1 */
-	rodt_on = cas_latency - ((ddr->timing_cfg_2 & 0x00780000) >> 19) + 1;
-	rodt_off = 4;	/*  4 clocks */
-	wodt_on = 1;	/*  1 clocks */
-	wodt_off = 4;	/*  4 clocks */
-#endif
-
-	ddr->timing_cfg_5 = (0
-			     | ((rodt_on & 0x1f) << 24)
-			     | ((rodt_off & 0x7) << 20)
-			     | ((wodt_on & 0x1f) << 12)
-			     | ((wodt_off & 0x7) << 8)
-			     );
-	debug("FSLDDR: timing_cfg_5 = 0x%08x\n", ddr->timing_cfg_5);
-}
-
-/* DDR ZQ Calibration Control (DDR_ZQ_CNTL) */
-static void set_ddr_zq_cntl(fsl_ddr_cfg_regs_t *ddr, unsigned int zq_en)
-{
-	unsigned int zqinit = 0;/* POR ZQ Calibration Time (tZQinit) */
-	/* Normal Operation Full Calibration Time (tZQoper) */
-	unsigned int zqoper = 0;
-	/* Normal Operation Short Calibration Time (tZQCS) */
-	unsigned int zqcs = 0;
-
-	if (zq_en) {
-		zqinit = 9;	/* 512 clocks */
-		zqoper = 8;	/* 256 clocks */
-		zqcs = 6;	/* 64 clocks */
-	}
-
-	ddr->ddr_zq_cntl = (0
-			    | ((zq_en & 0x1) << 31)
-			    | ((zqinit & 0xF) << 24)
-			    | ((zqoper & 0xF) << 16)
-			    | ((zqcs & 0xF) << 8)
-			    );
-	debug("FSLDDR: zq_cntl = 0x%08x\n", ddr->ddr_zq_cntl);
-}
-
-/* DDR Write Leveling Control (DDR_WRLVL_CNTL) */
-static void set_ddr_wrlvl_cntl(fsl_ddr_cfg_regs_t *ddr, unsigned int wrlvl_en,
-				const memctl_options_t *popts)
-{
-	/*
-	 * First DQS pulse rising edge after margining mode
-	 * is programmed (tWL_MRD)
-	 */
-	unsigned int wrlvl_mrd = 0;
-	/* ODT delay after margining mode is programmed (tWL_ODTEN) */
-	unsigned int wrlvl_odten = 0;
-	/* DQS/DQS_ delay after margining mode is programmed (tWL_DQSEN) */
-	unsigned int wrlvl_dqsen = 0;
-	/* WRLVL_SMPL: Write leveling sample time */
-	unsigned int wrlvl_smpl = 0;
-	/* WRLVL_WLR: Write leveling repeition time */
-	unsigned int wrlvl_wlr = 0;
-	/* WRLVL_START: Write leveling start time */
-	unsigned int wrlvl_start = 0;
-
-	/* suggest enable write leveling for DDR3 due to fly-by topology */
-	if (wrlvl_en) {
-		/* tWL_MRD min = 40 nCK, we set it 64 */
-		wrlvl_mrd = 0x6;
-		/* tWL_ODTEN 128 */
-		wrlvl_odten = 0x7;
-		/* tWL_DQSEN min = 25 nCK, we set it 32 */
-		wrlvl_dqsen = 0x5;
-		/*
-		 * Write leveling sample time at least need 6 clocks
-		 * higher than tWLO to allow enough time for progagation
-		 * delay and sampling the prime data bits.
-		 */
-		wrlvl_smpl = 0xf;
-		/*
-		 * Write leveling repetition time
-		 * at least tWLO + 6 clocks clocks
-		 * we set it 64
-		 */
-		wrlvl_wlr = 0x6;
-		/*
-		 * Write leveling start time
-		 * The value use for the DQS_ADJUST for the first sample
-		 * when write leveling is enabled. It probably needs to be
-		 * overriden per platform.
-		 */
-		wrlvl_start = 0x8;
-		/*
-		 * Override the write leveling sample and start time
-		 * according to specific board
-		 */
-		if (popts->wrlvl_override) {
-			wrlvl_smpl = popts->wrlvl_sample;
-			wrlvl_start = popts->wrlvl_start;
-		}
-	}
-
-	ddr->ddr_wrlvl_cntl = (0
-			       | ((wrlvl_en & 0x1) << 31)
-			       | ((wrlvl_mrd & 0x7) << 24)
-			       | ((wrlvl_odten & 0x7) << 20)
-			       | ((wrlvl_dqsen & 0x7) << 16)
-			       | ((wrlvl_smpl & 0xf) << 12)
-			       | ((wrlvl_wlr & 0x7) << 8)
-			       | ((wrlvl_start & 0x1F) << 0)
-			       );
-	debug("FSLDDR: wrlvl_cntl = 0x%08x\n", ddr->ddr_wrlvl_cntl);
-	ddr->ddr_wrlvl_cntl_2 = popts->wrlvl_ctl_2;
-	debug("FSLDDR: wrlvl_cntl_2 = 0x%08x\n", ddr->ddr_wrlvl_cntl_2);
-	ddr->ddr_wrlvl_cntl_3 = popts->wrlvl_ctl_3;
-	debug("FSLDDR: wrlvl_cntl_3 = 0x%08x\n", ddr->ddr_wrlvl_cntl_3);
-
-}
-
-/* DDR Self Refresh Counter (DDR_SR_CNTR) */
-static void set_ddr_sr_cntr(fsl_ddr_cfg_regs_t *ddr, unsigned int sr_it)
-{
-	/* Self Refresh Idle Threshold */
-	ddr->ddr_sr_cntr = (sr_it & 0xF) << 16;
-}
-
-static void set_ddr_eor(fsl_ddr_cfg_regs_t *ddr, const memctl_options_t *popts)
-{
-	if (popts->addr_hash) {
-		ddr->ddr_eor = 0x40000000;	/* address hash enable */
-		puts("Address hashing enabled.\n");
-	}
-}
-
-static void set_ddr_cdr1(fsl_ddr_cfg_regs_t *ddr, const memctl_options_t *popts)
-{
-	ddr->ddr_cdr1 = popts->ddr_cdr1;
-	debug("FSLDDR: ddr_cdr1 = 0x%08x\n", ddr->ddr_cdr1);
-}
-
-static void set_ddr_cdr2(fsl_ddr_cfg_regs_t *ddr, const memctl_options_t *popts)
-{
-	ddr->ddr_cdr2 = popts->ddr_cdr2;
-	debug("FSLDDR: ddr_cdr2 = 0x%08x\n", ddr->ddr_cdr2);
-}
-
-unsigned int
-check_fsl_memctl_config_regs(const fsl_ddr_cfg_regs_t *ddr)
-{
-	unsigned int res = 0;
-
-	/*
-	 * Check that DDR_SDRAM_CFG[RD_EN] and DDR_SDRAM_CFG[2T_EN] are
-	 * not set at the same time.
-	 */
-	if (ddr->ddr_sdram_cfg & 0x10000000
-	    && ddr->ddr_sdram_cfg & 0x00008000) {
-		printf("Error: DDR_SDRAM_CFG[RD_EN] and DDR_SDRAM_CFG[2T_EN] "
-				" should not be set at the same time.\n");
-		res++;
-	}
-
-	return res;
-}
-
-unsigned int
-compute_fsl_memctl_config_regs(const memctl_options_t *popts,
-			       fsl_ddr_cfg_regs_t *ddr,
-			       const common_timing_params_t *common_dimm,
-			       const dimm_params_t *dimm_params,
-			       unsigned int dbw_cap_adj,
-			       unsigned int size_only)
-{
-	unsigned int i;
-	unsigned int cas_latency;
-	unsigned int additive_latency;
-	unsigned int sr_it;
-	unsigned int zq_en;
-	unsigned int wrlvl_en;
-	unsigned int ip_rev = 0;
-	unsigned int unq_mrs_en = 0;
-	int cs_en = 1;
-
-	memset(ddr, 0, sizeof(fsl_ddr_cfg_regs_t));
-
-	if (common_dimm == NULL) {
-		printf("Error: subset DIMM params struct null pointer\n");
-		return 1;
-	}
-
-	/*
-	 * Process overrides first.
-	 *
-	 * FIXME: somehow add dereated caslat to this
-	 */
-	cas_latency = (popts->cas_latency_override)
-		? popts->cas_latency_override_value
-		: common_dimm->lowest_common_SPD_caslat;
-
-	additive_latency = (popts->additive_latency_override)
-		? popts->additive_latency_override_value
-		: common_dimm->additive_latency;
-
-	sr_it = (popts->auto_self_refresh_en)
-		? popts->sr_it
-		: 0;
-	/* ZQ calibration */
-	zq_en = (popts->zq_en) ? 1 : 0;
-	/* write leveling */
-	wrlvl_en = (popts->wrlvl_en) ? 1 : 0;
-
-	/* Chip Select Memory Bounds (CSn_BNDS) */
-	for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
-		unsigned long long ea, sa;
-		unsigned int cs_per_dimm
-			= CONFIG_CHIP_SELECTS_PER_CTRL / CONFIG_DIMM_SLOTS_PER_CTLR;
-		unsigned int dimm_number
-			= i / cs_per_dimm;
-		unsigned long long rank_density
-			= dimm_params[dimm_number].rank_density >> dbw_cap_adj;
-
-		if (dimm_params[dimm_number].n_ranks == 0) {
-			debug("Skipping setup of CS%u "
-				"because n_ranks on DIMM %u is 0\n", i, dimm_number);
-			continue;
-		}
-		if (popts->memctl_interleaving) {
-			switch (popts->ba_intlv_ctl & FSL_DDR_CS0_CS1_CS2_CS3) {
-			case FSL_DDR_CS0_CS1_CS2_CS3:
-				break;
-			case FSL_DDR_CS0_CS1:
-			case FSL_DDR_CS0_CS1_AND_CS2_CS3:
-				if (i > 1)
-					cs_en = 0;
-				break;
-			case FSL_DDR_CS2_CS3:
-			default:
-				if (i > 0)
-					cs_en = 0;
-				break;
-			}
-			sa = common_dimm->base_address;
-			ea = sa + common_dimm->total_mem - 1;
-		} else if (!popts->memctl_interleaving) {
-			/*
-			 * If memory interleaving between controllers is NOT
-			 * enabled, the starting address for each memory
-			 * controller is distinct.  However, because rank
-			 * interleaving is enabled, the starting and ending
-			 * addresses of the total memory on that memory
-			 * controller needs to be programmed into its
-			 * respective CS0_BNDS.
-			 */
-			switch (popts->ba_intlv_ctl & FSL_DDR_CS0_CS1_CS2_CS3) {
-			case FSL_DDR_CS0_CS1_CS2_CS3:
-				sa = common_dimm->base_address;
-				ea = sa + common_dimm->total_mem - 1;
-				break;
-			case FSL_DDR_CS0_CS1_AND_CS2_CS3:
-				if ((i >= 2) && (dimm_number == 0)) {
-					sa = dimm_params[dimm_number].base_address +
-					      2 * rank_density;
-					ea = sa + 2 * rank_density - 1;
-				} else {
-					sa = dimm_params[dimm_number].base_address;
-					ea = sa + 2 * rank_density - 1;
-				}
-				break;
-			case FSL_DDR_CS0_CS1:
-				if (dimm_params[dimm_number].n_ranks > (i % cs_per_dimm)) {
-					sa = dimm_params[dimm_number].base_address;
-					ea = sa + rank_density - 1;
-					if (i != 1)
-						sa += (i % cs_per_dimm) * rank_density;
-					ea += (i % cs_per_dimm) * rank_density;
-				} else {
-					sa = 0;
-					ea = 0;
-				}
-				if (i == 0)
-					ea += rank_density;
-				break;
-			case FSL_DDR_CS2_CS3:
-				if (dimm_params[dimm_number].n_ranks > (i % cs_per_dimm)) {
-					sa = dimm_params[dimm_number].base_address;
-					ea = sa + rank_density - 1;
-					if (i != 3)
-						sa += (i % cs_per_dimm) * rank_density;
-					ea += (i % cs_per_dimm) * rank_density;
-				} else {
-					sa = 0;
-					ea = 0;
-				}
-				if (i == 2)
-					ea += (rank_density >> dbw_cap_adj);
-				break;
-			default:  /* No bank(chip-select) interleaving */
-				sa = dimm_params[dimm_number].base_address;
-				ea = sa + rank_density - 1;
-				if (dimm_params[dimm_number].n_ranks > (i % cs_per_dimm)) {
-					sa += (i % cs_per_dimm) * rank_density;
-					ea += (i % cs_per_dimm) * rank_density;
-				} else {
-					sa = 0;
-					ea = 0;
-				}
-				break;
-			}
-		}
-
-		sa >>= 24;
-		ea >>= 24;
-
-		if (cs_en) {
-			ddr->cs[i].bnds = (0
-				| ((sa & 0xFFF) << 16)/* starting address MSB */
-				| ((ea & 0xFFF) << 0)	/* ending address MSB */
-				);
-		} else {
-			/* setting bnds to 0xffffffff for inactive CS */
-			ddr->cs[i].bnds = 0xffffffff;
-		}
-
-		debug("FSLDDR: cs[%d]_bnds = 0x%08x\n", i, ddr->cs[i].bnds);
-		set_csn_config(dimm_number, i, ddr, popts, dimm_params);
-		set_csn_config_2(i, ddr);
-	}
-
-	/*
-	 * In the case we only need to compute the ddr sdram size, we only need
-	 * to set csn registers, so return from here.
-	 */
-	if (size_only)
-		return 0;
-
-	set_ddr_eor(ddr, popts);
-
-#if !defined(CONFIG_FSL_DDR1)
-	set_timing_cfg_0(ddr, popts, dimm_params);
-#endif
-
-	set_timing_cfg_3(ddr, popts, common_dimm, cas_latency);
-	set_timing_cfg_1(ddr, popts, common_dimm, cas_latency);
-	set_timing_cfg_2(ddr, popts, common_dimm,
-				cas_latency, additive_latency);
-
-	set_ddr_cdr1(ddr, popts);
-	set_ddr_cdr2(ddr, popts);
-	set_ddr_sdram_cfg(ddr, popts, common_dimm);
-	ip_rev = fsl_ddr_get_version();
-	if (ip_rev > 0x40400)
-		unq_mrs_en = 1;
-
-	set_ddr_sdram_cfg_2(ddr, popts, unq_mrs_en);
-	set_ddr_sdram_mode(ddr, popts, common_dimm,
-				cas_latency, additive_latency, unq_mrs_en);
-	set_ddr_sdram_mode_2(ddr, popts, unq_mrs_en);
-	set_ddr_sdram_interval(ddr, popts, common_dimm);
-	set_ddr_data_init(ddr);
-	set_ddr_sdram_clk_cntl(ddr, popts);
-	set_ddr_init_addr(ddr);
-	set_ddr_init_ext_addr(ddr);
-	set_timing_cfg_4(ddr, popts);
-	set_timing_cfg_5(ddr, cas_latency);
-
-	set_ddr_zq_cntl(ddr, zq_en);
-	set_ddr_wrlvl_cntl(ddr, wrlvl_en, popts);
-
-	set_ddr_sr_cntr(ddr, sr_it);
-
-	set_ddr_sdram_rcw(ddr, popts, common_dimm);
-
-#ifdef CONFIG_SYS_FSL_DDR_EMU
-	/* disble DDR training for emulator */
-	ddr->debug[2] = 0x00000400;
-	ddr->debug[4] = 0xff800000;
-#endif
-	return check_fsl_memctl_config_regs(ddr);
-}
diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/ddr.h b/arch/powerpc/cpu/mpc8xxx/ddr/ddr.h
deleted file mode 100644
index c173a5a74b..0000000000
--- a/arch/powerpc/cpu/mpc8xxx/ddr/ddr.h
+++ /dev/null
@@ -1,105 +0,0 @@
-/*
- * Copyright 2008-2011 Freescale Semiconductor, Inc.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * Version 2 as published by the Free Software Foundation.
- */
-
-#ifndef FSL_DDR_MAIN_H
-#define FSL_DDR_MAIN_H
-
-#include <asm/fsl_ddr_sdram.h>
-#include <asm/fsl_ddr_dimm_params.h>
-
-#include "common_timing_params.h"
-
-#if defined(CONFIG_DDR_SPD) || defined(CONFIG_SPD_EEPROM)
-/*
- * Bind the main DDR setup driver's generic names
- * to this specific DDR technology.
- */
-static __inline__ int
-compute_dimm_parameters(const generic_spd_eeprom_t *spd,
-			dimm_params_t *pdimm,
-			unsigned int dimm_number)
-{
-	return ddr_compute_dimm_parameters(spd, pdimm, dimm_number);
-}
-#endif
-
-/*
- * Data Structures
- *
- * All data structures have to be on the stack
- */
-#define CONFIG_SYS_NUM_DDR_CTLRS CONFIG_NUM_DDR_CONTROLLERS
-#define CONFIG_SYS_DIMM_SLOTS_PER_CTLR CONFIG_DIMM_SLOTS_PER_CTLR
-
-typedef struct {
-	generic_spd_eeprom_t
-	   spd_installed_dimms[CONFIG_SYS_NUM_DDR_CTLRS][CONFIG_SYS_DIMM_SLOTS_PER_CTLR];
-	struct dimm_params_s
-	   dimm_params[CONFIG_SYS_NUM_DDR_CTLRS][CONFIG_SYS_DIMM_SLOTS_PER_CTLR];
-	memctl_options_t memctl_opts[CONFIG_SYS_NUM_DDR_CTLRS];
-	common_timing_params_t common_timing_params[CONFIG_SYS_NUM_DDR_CTLRS];
-	fsl_ddr_cfg_regs_t fsl_ddr_config_reg[CONFIG_SYS_NUM_DDR_CTLRS];
-} fsl_ddr_info_t;
-
-/* Compute steps */
-#define STEP_GET_SPD                 (1 << 0)
-#define STEP_COMPUTE_DIMM_PARMS      (1 << 1)
-#define STEP_COMPUTE_COMMON_PARMS    (1 << 2)
-#define STEP_GATHER_OPTS             (1 << 3)
-#define STEP_ASSIGN_ADDRESSES        (1 << 4)
-#define STEP_COMPUTE_REGS            (1 << 5)
-#define STEP_PROGRAM_REGS            (1 << 6)
-#define STEP_ALL                     0xFFF
-
-unsigned long long
-fsl_ddr_compute(fsl_ddr_info_t *pinfo, unsigned int start_step,
-				       unsigned int size_only);
-
-const char *step_to_string(unsigned int step);
-
-unsigned int compute_fsl_memctl_config_regs(const memctl_options_t *popts,
-			       fsl_ddr_cfg_regs_t *ddr,
-			       const common_timing_params_t *common_dimm,
-			       const dimm_params_t *dimm_parameters,
-			       unsigned int dbw_capacity_adjust,
-			       unsigned int size_only);
-unsigned int compute_lowest_common_dimm_parameters(
-				const dimm_params_t *dimm_params,
-				common_timing_params_t *outpdimm,
-				unsigned int number_of_dimms);
-unsigned int populate_memctl_options(int all_DIMMs_registered,
-				memctl_options_t *popts,
-				dimm_params_t *pdimm,
-				unsigned int ctrl_num);
-void check_interleaving_options(fsl_ddr_info_t *pinfo);
-
-unsigned int mclk_to_picos(unsigned int mclk);
-unsigned int get_memory_clk_period_ps(void);
-unsigned int picos_to_mclk(unsigned int picos);
-void fsl_ddr_set_lawbar(
-		const common_timing_params_t *memctl_common_params,
-		unsigned int memctl_interleaved,
-		unsigned int ctrl_num);
-
-int fsl_ddr_interactive_env_var_exists(void);
-unsigned long long fsl_ddr_interactive(fsl_ddr_info_t *pinfo, int var_is_set);
-void fsl_ddr_get_spd(generic_spd_eeprom_t *ctrl_dimms_spd,
-			   unsigned int ctrl_num);
-
-int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]);
-unsigned int check_fsl_memctl_config_regs(const fsl_ddr_cfg_regs_t *ddr);
-
-/* processor specific function */
-void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
-				   unsigned int ctrl_num, int step);
-
-/* board specific function */
-int fsl_ddr_get_dimm_params(dimm_params_t *pdimm,
-			unsigned int controller_number,
-			unsigned int dimm_number);
-#endif
diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/ddr1_dimm_params.c b/arch/powerpc/cpu/mpc8xxx/ddr/ddr1_dimm_params.c
deleted file mode 100644
index 376be2fb37..0000000000
--- a/arch/powerpc/cpu/mpc8xxx/ddr/ddr1_dimm_params.c
+++ /dev/null
@@ -1,343 +0,0 @@
-/*
- * Copyright 2008 Freescale Semiconductor, Inc.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * Version 2 as published by the Free Software Foundation.
- */
-
-#include <common.h>
-#include <asm/fsl_ddr_sdram.h>
-
-#include "ddr.h"
-
-/*
- * Calculate the Density of each Physical Rank.
- * Returned size is in bytes.
- *
- * Study these table from Byte 31 of JEDEC SPD Spec.
- *
- *		DDR I	DDR II
- *	Bit	Size	Size
- *	---	-----	------
- *	7 high	512MB	512MB
- *	6	256MB	256MB
- *	5	128MB	128MB
- *	4	 64MB	 16GB
- *	3	 32MB	  8GB
- *	2	 16MB	  4GB
- *	1	  2GB	  2GB
- *	0 low	  1GB	  1GB
- *
- * Reorder Table to be linear by stripping the bottom
- * 2 or 5 bits off and shifting them up to the top.
- */
-
-static unsigned long long
-compute_ranksize(unsigned int mem_type, unsigned char row_dens)
-{
-	unsigned long long bsize;
-
-	/* Bottom 2 bits up to the top. */
-	bsize = ((row_dens >> 2) | ((row_dens & 3) << 6));
-	bsize <<= 24ULL;
-	debug("DDR: DDR I rank density = 0x%16llx\n", bsize);
-
-	return bsize;
-}
-
-/*
- * Convert a two-nibble BCD value into a cycle time.
- * While the spec calls for nano-seconds, picos are returned.
- *
- * This implements the tables for bytes 9, 23 and 25 for both
- * DDR I and II.  No allowance for distinguishing the invalid
- * fields absent for DDR I yet present in DDR II is made.
- * (That is, cycle times of .25, .33, .66 and .75 ns are
- * allowed for both DDR II and I.)
- */
-static unsigned int
-convert_bcd_tenths_to_cycle_time_ps(unsigned int spd_val)
-{
-	/* Table look up the lower nibble, allow DDR I & II. */
-	unsigned int tenths_ps[16] = {
-		0,
-		100,
-		200,
-		300,
-		400,
-		500,
-		600,
-		700,
-		800,
-		900,
-		250,	/* This and the next 3 entries valid ... */
-		330,	/* ...  only for tCK calculations. */
-		660,
-		750,
-		0,	/* undefined */
-		0	/* undefined */
-	};
-
-	unsigned int whole_ns = (spd_val & 0xF0) >> 4;
-	unsigned int tenth_ns = spd_val & 0x0F;
-	unsigned int ps = whole_ns * 1000 + tenths_ps[tenth_ns];
-
-	return ps;
-}
-
-static unsigned int
-convert_bcd_hundredths_to_cycle_time_ps(unsigned int spd_val)
-{
-	unsigned int tenth_ns = (spd_val & 0xF0) >> 4;
-	unsigned int hundredth_ns = spd_val & 0x0F;
-	unsigned int ps = tenth_ns * 100 + hundredth_ns * 10;
-
-	return ps;
-}
-
-static unsigned int byte40_table_ps[8] = {
-	0,
-	250,
-	330,
-	500,
-	660,
-	750,
-	0,	/* supposed to be RFC, but not sure what that means */
-	0	/* Undefined */
-};
-
-static unsigned int
-compute_trfc_ps_from_spd(unsigned char trctrfc_ext, unsigned char trfc)
-{
-	unsigned int trfc_ps;
-
-	trfc_ps = (((trctrfc_ext & 0x1) * 256) + trfc) * 1000
-		+ byte40_table_ps[(trctrfc_ext >> 1) & 0x7];
-
-	return trfc_ps;
-}
-
-static unsigned int
-compute_trc_ps_from_spd(unsigned char trctrfc_ext, unsigned char trc)
-{
-	unsigned int trc_ps;
-
-	trc_ps = trc * 1000 + byte40_table_ps[(trctrfc_ext >> 4) & 0x7];
-
-	return trc_ps;
-}
-
-/*
- * tCKmax from DDR I SPD Byte 43
- *
- * Bits 7:2 == whole ns
- * Bits 1:0 == quarter ns
- *    00    == 0.00 ns
- *    01    == 0.25 ns
- *    10    == 0.50 ns
- *    11    == 0.75 ns
- *
- * Returns picoseconds.
- */
-static unsigned int
-compute_tckmax_from_spd_ps(unsigned int byte43)
-{
-	return (byte43 >> 2) * 1000 + (byte43 & 0x3) * 250;
-}
-
-/*
- * Determine Refresh Rate.  Ignore self refresh bit on DDR I.
- * Table from SPD Spec, Byte 12, converted to picoseconds and
- * filled in with "default" normal values.
- */
-static unsigned int
-determine_refresh_rate_ps(const unsigned int spd_refresh)
-{
-	unsigned int refresh_time_ps[8] = {
-		15625000,	/* 0 Normal    1.00x */
-		3900000,	/* 1 Reduced    .25x */
-		7800000,	/* 2 Extended   .50x */
-		31300000,	/* 3 Extended  2.00x */
-		62500000,	/* 4 Extended  4.00x */
-		125000000,	/* 5 Extended  8.00x */
-		15625000,	/* 6 Normal    1.00x  filler */
-		15625000,	/* 7 Normal    1.00x  filler */
-	};
-
-	return refresh_time_ps[spd_refresh & 0x7];
-}
-
-/*
- * The purpose of this function is to compute a suitable
- * CAS latency given the DRAM clock period.  The SPD only
- * defines at most 3 CAS latencies.  Typically the slower in
- * frequency the DIMM runs at, the shorter its CAS latency can be.
- * If the DIMM is operating at a sufficiently low frequency,
- * it may be able to run at a CAS latency shorter than the
- * shortest SPD-defined CAS latency.
- *
- * If a CAS latency is not found, 0 is returned.
- *
- * Do this by finding in the standard speed bin table the longest
- * tCKmin that doesn't exceed the value of mclk_ps (tCK).
- *
- * An assumption made is that the SDRAM device allows the
- * CL to be programmed for a value that is lower than those
- * advertised by the SPD.  This is not always the case,
- * as those modes not defined in the SPD are optional.
- *
- * CAS latency de-rating based upon values JEDEC Standard No. 79-E
- * Table 11.
- *
- * ordinal 2, ddr1_speed_bins[1] contains tCK for CL=2
- */
-				  /*   CL2.0 CL2.5 CL3.0  */
-unsigned short ddr1_speed_bins[] = {0, 7500, 6000, 5000 };
-
-unsigned int
-compute_derated_DDR1_CAS_latency(unsigned int mclk_ps)
-{
-	const unsigned int num_speed_bins = ARRAY_SIZE(ddr1_speed_bins);
-	unsigned int lowest_tCKmin_found = 0;
-	unsigned int lowest_tCKmin_CL = 0;
-	unsigned int i;
-
-	debug("mclk_ps = %u\n", mclk_ps);
-
-	for (i = 0; i < num_speed_bins; i++) {
-		unsigned int x = ddr1_speed_bins[i];
-		debug("i=%u, x = %u, lowest_tCKmin_found = %u\n",
-		      i, x, lowest_tCKmin_found);
-		if (x && lowest_tCKmin_found <= x && x <= mclk_ps) {
-			lowest_tCKmin_found = x;
-			lowest_tCKmin_CL = i + 1;
-		}
-	}
-
-	debug("lowest_tCKmin_CL = %u\n", lowest_tCKmin_CL);
-
-	return lowest_tCKmin_CL;
-}
-
-/*
- * ddr_compute_dimm_parameters for DDR1 SPD
- *
- * Compute DIMM parameters based upon the SPD information in spd.
- * Writes the results to the dimm_params_t structure pointed by pdimm.
- *
- * FIXME: use #define for the retvals
- */
-unsigned int
-ddr_compute_dimm_parameters(const ddr1_spd_eeprom_t *spd,
-			     dimm_params_t *pdimm,
-			     unsigned int dimm_number)
-{
-	unsigned int retval;
-
-	if (spd->mem_type) {
-		if (spd->mem_type != SPD_MEMTYPE_DDR) {
-			printf("DIMM %u: is not a DDR1 SPD.\n", dimm_number);
-			return 1;
-		}
-	} else {
-		memset(pdimm, 0, sizeof(dimm_params_t));
-		return 1;
-	}
-
-	retval = ddr1_spd_check(spd);
-	if (retval) {
-		printf("DIMM %u: failed checksum\n", dimm_number);
-		return 2;
-	}
-
-	/*
-	 * The part name in ASCII in the SPD EEPROM is not null terminated.
-	 * Guarantee null termination here by presetting all bytes to 0
-	 * and copying the part name in ASCII from the SPD onto it
-	 */
-	memset(pdimm->mpart, 0, sizeof(pdimm->mpart));
-	memcpy(pdimm->mpart, spd->mpart, sizeof(pdimm->mpart) - 1);
-
-	/* DIMM organization parameters */
-	pdimm->n_ranks = spd->nrows;
-	pdimm->rank_density = compute_ranksize(spd->mem_type, spd->bank_dens);
-	pdimm->capacity = pdimm->n_ranks * pdimm->rank_density;
-	pdimm->data_width = spd->dataw_lsb;
-	pdimm->primary_sdram_width = spd->primw;
-	pdimm->ec_sdram_width = spd->ecw;
-
-	/*
-	 * FIXME: Need to determine registered_dimm status.
-	 *     1 == register buffered
-	 *     0 == unbuffered
-	 */
-	pdimm->registered_dimm = 0;	/* unbuffered */
-
-	/* SDRAM device parameters */
-	pdimm->n_row_addr = spd->nrow_addr;
-	pdimm->n_col_addr = spd->ncol_addr;
-	pdimm->n_banks_per_sdram_device = spd->nbanks;
-	pdimm->edc_config = spd->config;
-	pdimm->burst_lengths_bitmask = spd->burstl;
-	pdimm->row_density = spd->bank_dens;
-
-	/*
-	 * Calculate the Maximum Data Rate based on the Minimum Cycle time.
-	 * The SPD clk_cycle field (tCKmin) is measured in tenths of
-	 * nanoseconds and represented as BCD.
-	 */
-	pdimm->tCKmin_X_ps
-		= convert_bcd_tenths_to_cycle_time_ps(spd->clk_cycle);
-	pdimm->tCKmin_X_minus_1_ps
-		= convert_bcd_tenths_to_cycle_time_ps(spd->clk_cycle2);
-	pdimm->tCKmin_X_minus_2_ps
-		= convert_bcd_tenths_to_cycle_time_ps(spd->clk_cycle3);
-
-	pdimm->tCKmax_ps = compute_tckmax_from_spd_ps(spd->tckmax);
-
-	/*
-	 * Compute CAS latencies defined by SPD
-	 * The SPD caslat_X should have at least 1 and at most 3 bits set.
-	 *
-	 * If cas_lat after masking is 0, the __ilog2 function returns
-	 * 255 into the variable.   This behavior is abused once.
-	 */
-	pdimm->caslat_X  = __ilog2(spd->cas_lat);
-	pdimm->caslat_X_minus_1 = __ilog2(spd->cas_lat
-					  & ~(1 << pdimm->caslat_X));
-	pdimm->caslat_X_minus_2 = __ilog2(spd->cas_lat
-					  & ~(1 << pdimm->caslat_X)
-					  & ~(1 << pdimm->caslat_X_minus_1));
-
-	/* Compute CAS latencies below that defined by SPD */
-	pdimm->caslat_lowest_derated
-		= compute_derated_DDR1_CAS_latency(get_memory_clk_period_ps());
-
-	/* Compute timing parameters */
-	pdimm->tRCD_ps = spd->trcd * 250;
-	pdimm->tRP_ps = spd->trp * 250;
-	pdimm->tRAS_ps = spd->tras * 1000;
-
-	pdimm->tWR_ps = mclk_to_picos(3);
-	pdimm->tWTR_ps = mclk_to_picos(1);
-	pdimm->tRFC_ps = compute_trfc_ps_from_spd(0, spd->trfc);
-
-	pdimm->tRRD_ps = spd->trrd * 250;
-	pdimm->tRC_ps = compute_trc_ps_from_spd(0, spd->trc);
-
-	pdimm->refresh_rate_ps = determine_refresh_rate_ps(spd->refresh);
-
-	pdimm->tIS_ps = convert_bcd_hundredths_to_cycle_time_ps(spd->ca_setup);
-	pdimm->tIH_ps = convert_bcd_hundredths_to_cycle_time_ps(spd->ca_hold);
-	pdimm->tDS_ps
-		= convert_bcd_hundredths_to_cycle_time_ps(spd->data_setup);
-	pdimm->tDH_ps
-		= convert_bcd_hundredths_to_cycle_time_ps(spd->data_hold);
-
-	pdimm->tRTP_ps = mclk_to_picos(2);	/* By the book. */
-	pdimm->tDQSQ_max_ps = spd->tdqsq * 10;
-	pdimm->tQHS_ps = spd->tqhs * 10;
-
-	return 0;
-}
diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/ddr2_dimm_params.c b/arch/powerpc/cpu/mpc8xxx/ddr/ddr2_dimm_params.c
deleted file mode 100644
index f637f3d045..0000000000
--- a/arch/powerpc/cpu/mpc8xxx/ddr/ddr2_dimm_params.c
+++ /dev/null
@@ -1,342 +0,0 @@
-/*
- * Copyright 2008 Freescale Semiconductor, Inc.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * Version 2 as published by the Free Software Foundation.
- */
-
-#include <common.h>
-#include <asm/fsl_ddr_sdram.h>
-
-#include "ddr.h"
-/*
- * Calculate the Density of each Physical Rank.
- * Returned size is in bytes.
- *
- * Study these table from Byte 31 of JEDEC SPD Spec.
- *
- *		DDR I	DDR II
- *	Bit	Size	Size
- *	---	-----	------
- *	7 high	512MB	512MB
- *	6	256MB	256MB
- *	5	128MB	128MB
- *	4	 64MB	 16GB
- *	3	 32MB	  8GB
- *	2	 16MB	  4GB
- *	1	  2GB	  2GB
- *	0 low	  1GB	  1GB
- *
- * Reorder Table to be linear by stripping the bottom
- * 2 or 5 bits off and shifting them up to the top.
- *
- */
-static unsigned long long
-compute_ranksize(unsigned int mem_type, unsigned char row_dens)
-{
-	unsigned long long bsize;
-
-	/* Bottom 5 bits up to the top. */
-	bsize = ((row_dens >> 5) | ((row_dens & 31) << 3));
-	bsize <<= 27ULL;
-	debug("DDR: DDR II rank density = 0x%16llx\n", bsize);
-
-	return bsize;
-}
-
-/*
- * Convert a two-nibble BCD value into a cycle time.
- * While the spec calls for nano-seconds, picos are returned.
- *
- * This implements the tables for bytes 9, 23 and 25 for both
- * DDR I and II.  No allowance for distinguishing the invalid
- * fields absent for DDR I yet present in DDR II is made.
- * (That is, cycle times of .25, .33, .66 and .75 ns are
- * allowed for both DDR II and I.)
- */
-static unsigned int
-convert_bcd_tenths_to_cycle_time_ps(unsigned int spd_val)
-{
-	/* Table look up the lower nibble, allow DDR I & II. */
-	unsigned int tenths_ps[16] = {
-		0,
-		100,
-		200,
-		300,
-		400,
-		500,
-		600,
-		700,
-		800,
-		900,
-		250,	/* This and the next 3 entries valid ... */
-		330,	/* ...  only for tCK calculations. */
-		660,
-		750,
-		0,	/* undefined */
-		0	/* undefined */
-	};
-
-	unsigned int whole_ns = (spd_val & 0xF0) >> 4;
-	unsigned int tenth_ns = spd_val & 0x0F;
-	unsigned int ps = whole_ns * 1000 + tenths_ps[tenth_ns];
-
-	return ps;
-}
-
-static unsigned int
-convert_bcd_hundredths_to_cycle_time_ps(unsigned int spd_val)
-{
-	unsigned int tenth_ns = (spd_val & 0xF0) >> 4;
-	unsigned int hundredth_ns = spd_val & 0x0F;
-	unsigned int ps = tenth_ns * 100 + hundredth_ns * 10;
-
-	return ps;
-}
-
-static unsigned int byte40_table_ps[8] = {
-	0,
-	250,
-	330,
-	500,
-	660,
-	750,
-	0,	/* supposed to be RFC, but not sure what that means */
-	0	/* Undefined */
-};
-
-static unsigned int
-compute_trfc_ps_from_spd(unsigned char trctrfc_ext, unsigned char trfc)
-{
-	unsigned int trfc_ps;
-
-	trfc_ps = (((trctrfc_ext & 0x1) * 256) + trfc) * 1000
-		+ byte40_table_ps[(trctrfc_ext >> 1) & 0x7];
-
-	return trfc_ps;
-}
-
-static unsigned int
-compute_trc_ps_from_spd(unsigned char trctrfc_ext, unsigned char trc)
-{
-	unsigned int trc_ps;
-
-	trc_ps = trc * 1000 + byte40_table_ps[(trctrfc_ext >> 4) & 0x7];
-
-	return trc_ps;
-}
-
-/*
- * Determine Refresh Rate.  Ignore self refresh bit on DDR I.
- * Table from SPD Spec, Byte 12, converted to picoseconds and
- * filled in with "default" normal values.
- */
-static unsigned int
-determine_refresh_rate_ps(const unsigned int spd_refresh)
-{
-	unsigned int refresh_time_ps[8] = {
-		15625000,	/* 0 Normal    1.00x */
-		3900000,	/* 1 Reduced    .25x */
-		7800000,	/* 2 Extended   .50x */
-		31300000,	/* 3 Extended  2.00x */
-		62500000,	/* 4 Extended  4.00x */
-		125000000,	/* 5 Extended  8.00x */
-		15625000,	/* 6 Normal    1.00x  filler */
-		15625000,	/* 7 Normal    1.00x  filler */
-	};
-
-	return refresh_time_ps[spd_refresh & 0x7];
-}
-
-/*
- * The purpose of this function is to compute a suitable
- * CAS latency given the DRAM clock period.  The SPD only
- * defines at most 3 CAS latencies.  Typically the slower in
- * frequency the DIMM runs at, the shorter its CAS latency can.
- * be.  If the DIMM is operating at a sufficiently low frequency,
- * it may be able to run at a CAS latency shorter than the
- * shortest SPD-defined CAS latency.
- *
- * If a CAS latency is not found, 0 is returned.
- *
- * Do this by finding in the standard speed bin table the longest
- * tCKmin that doesn't exceed the value of mclk_ps (tCK).
- *
- * An assumption made is that the SDRAM device allows the
- * CL to be programmed for a value that is lower than those
- * advertised by the SPD.  This is not always the case,
- * as those modes not defined in the SPD are optional.
- *
- * CAS latency de-rating based upon values JEDEC Standard No. 79-2C
- * Table 40, "DDR2 SDRAM stanadard speed bins and tCK, tRCD, tRP, tRAS,
- * and tRC for corresponding bin"
- *
- * ordinal 2, ddr2_speed_bins[1] contains tCK for CL=3
- * Not certain if any good value exists for CL=2
- */
-				 /* CL2   CL3   CL4   CL5   CL6  CL7*/
-unsigned short ddr2_speed_bins[] = {   0, 5000, 3750, 3000, 2500, 1875 };
-
-unsigned int
-compute_derated_DDR2_CAS_latency(unsigned int mclk_ps)
-{
-	const unsigned int num_speed_bins = ARRAY_SIZE(ddr2_speed_bins);
-	unsigned int lowest_tCKmin_found = 0;
-	unsigned int lowest_tCKmin_CL = 0;
-	unsigned int i;
-
-	debug("mclk_ps = %u\n", mclk_ps);
-
-	for (i = 0; i < num_speed_bins; i++) {
-		unsigned int x = ddr2_speed_bins[i];
-		debug("i=%u, x = %u, lowest_tCKmin_found = %u\n",
-		      i, x, lowest_tCKmin_found);
-		if (x && x <= mclk_ps && x >= lowest_tCKmin_found ) {
-			lowest_tCKmin_found = x;
-			lowest_tCKmin_CL = i + 2;
-		}
-	}
-
-	debug("lowest_tCKmin_CL = %u\n", lowest_tCKmin_CL);
-
-	return lowest_tCKmin_CL;
-}
-
-/*
- * ddr_compute_dimm_parameters for DDR2 SPD
- *
- * Compute DIMM parameters based upon the SPD information in spd.
- * Writes the results to the dimm_params_t structure pointed by pdimm.
- *
- * FIXME: use #define for the retvals
- */
-unsigned int
-ddr_compute_dimm_parameters(const ddr2_spd_eeprom_t *spd,
-			     dimm_params_t *pdimm,
-			     unsigned int dimm_number)
-{
-	unsigned int retval;
-
-	if (spd->mem_type) {
-		if (spd->mem_type != SPD_MEMTYPE_DDR2) {
-			printf("DIMM %u: is not a DDR2 SPD.\n", dimm_number);
-			return 1;
-		}
-	} else {
-		memset(pdimm, 0, sizeof(dimm_params_t));
-		return 1;
-	}
-
-	retval = ddr2_spd_check(spd);
-	if (retval) {
-		printf("DIMM %u: failed checksum\n", dimm_number);
-		return 2;
-	}
-
-	/*
-	 * The part name in ASCII in the SPD EEPROM is not null terminated.
-	 * Guarantee null termination here by presetting all bytes to 0
-	 * and copying the part name in ASCII from the SPD onto it
-	 */
-	memset(pdimm->mpart, 0, sizeof(pdimm->mpart));
-	memcpy(pdimm->mpart, spd->mpart, sizeof(pdimm->mpart) - 1);
-
-	/* DIMM organization parameters */
-	pdimm->n_ranks = (spd->mod_ranks & 0x7) + 1;
-	pdimm->rank_density = compute_ranksize(spd->mem_type, spd->rank_dens);
-	pdimm->capacity = pdimm->n_ranks * pdimm->rank_density;
-	pdimm->data_width = spd->dataw;
-	pdimm->primary_sdram_width = spd->primw;
-	pdimm->ec_sdram_width = spd->ecw;
-
-	/* These are all the types defined by the JEDEC DDR2 SPD 1.3 spec */
-	switch (spd->dimm_type) {
-	case DDR2_SPD_DIMMTYPE_RDIMM:
-	case DDR2_SPD_DIMMTYPE_72B_SO_RDIMM:
-	case DDR2_SPD_DIMMTYPE_MINI_RDIMM:
-		/* Registered/buffered DIMMs */
-		pdimm->registered_dimm = 1;
-		break;
-
-	case DDR2_SPD_DIMMTYPE_UDIMM:
-	case DDR2_SPD_DIMMTYPE_SO_DIMM:
-	case DDR2_SPD_DIMMTYPE_MICRO_DIMM:
-	case DDR2_SPD_DIMMTYPE_MINI_UDIMM:
-		/* Unbuffered DIMMs */
-		pdimm->registered_dimm = 0;
-		break;
-
-	case DDR2_SPD_DIMMTYPE_72B_SO_CDIMM:
-	default:
-		printf("unknown dimm_type 0x%02X\n", spd->dimm_type);
-		return 1;
-	}
-
-	/* SDRAM device parameters */
-	pdimm->n_row_addr = spd->nrow_addr;
-	pdimm->n_col_addr = spd->ncol_addr;
-	pdimm->n_banks_per_sdram_device = spd->nbanks;
-	pdimm->edc_config = spd->config;
-	pdimm->burst_lengths_bitmask = spd->burstl;
-	pdimm->row_density = spd->rank_dens;
-
-	/*
-	 * Calculate the Maximum Data Rate based on the Minimum Cycle time.
-	 * The SPD clk_cycle field (tCKmin) is measured in tenths of
-	 * nanoseconds and represented as BCD.
-	 */
-	pdimm->tCKmin_X_ps
-		= convert_bcd_tenths_to_cycle_time_ps(spd->clk_cycle);
-	pdimm->tCKmin_X_minus_1_ps
-		= convert_bcd_tenths_to_cycle_time_ps(spd->clk_cycle2);
-	pdimm->tCKmin_X_minus_2_ps
-		= convert_bcd_tenths_to_cycle_time_ps(spd->clk_cycle3);
-
-	pdimm->tCKmax_ps = convert_bcd_tenths_to_cycle_time_ps(spd->tckmax);
-
-	/*
-	 * Compute CAS latencies defined by SPD
-	 * The SPD caslat_X should have at least 1 and at most 3 bits set.
-	 *
-	 * If cas_lat after masking is 0, the __ilog2 function returns
-	 * 255 into the variable.   This behavior is abused once.
-	 */
-	pdimm->caslat_X  = __ilog2(spd->cas_lat);
-	pdimm->caslat_X_minus_1 = __ilog2(spd->cas_lat
-					  & ~(1 << pdimm->caslat_X));
-	pdimm->caslat_X_minus_2 = __ilog2(spd->cas_lat
-					  & ~(1 << pdimm->caslat_X)
-					  & ~(1 << pdimm->caslat_X_minus_1));
-
-	/* Compute CAS latencies below that defined by SPD */
-	pdimm->caslat_lowest_derated
-		= compute_derated_DDR2_CAS_latency(get_memory_clk_period_ps());
-
-	/* Compute timing parameters */
-	pdimm->tRCD_ps = spd->trcd * 250;
-	pdimm->tRP_ps = spd->trp * 250;
-	pdimm->tRAS_ps = spd->tras * 1000;
-
-	pdimm->tWR_ps = spd->twr * 250;
-	pdimm->tWTR_ps = spd->twtr * 250;
-	pdimm->tRFC_ps = compute_trfc_ps_from_spd(spd->trctrfc_ext, spd->trfc);
-
-	pdimm->tRRD_ps = spd->trrd * 250;
-	pdimm->tRC_ps = compute_trc_ps_from_spd(spd->trctrfc_ext, spd->trc);
-
-	pdimm->refresh_rate_ps = determine_refresh_rate_ps(spd->refresh);
-
-	pdimm->tIS_ps = convert_bcd_hundredths_to_cycle_time_ps(spd->ca_setup);
-	pdimm->tIH_ps = convert_bcd_hundredths_to_cycle_time_ps(spd->ca_hold);
-	pdimm->tDS_ps
-		= convert_bcd_hundredths_to_cycle_time_ps(spd->data_setup);
-	pdimm->tDH_ps
-		= convert_bcd_hundredths_to_cycle_time_ps(spd->data_hold);
-
-	pdimm->tRTP_ps = spd->trtp * 250;
-	pdimm->tDQSQ_max_ps = spd->tdqsq * 10;
-	pdimm->tQHS_ps = spd->tqhs * 10;
-
-	return 0;
-}
diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/ddr3_dimm_params.c b/arch/powerpc/cpu/mpc8xxx/ddr/ddr3_dimm_params.c
deleted file mode 100644
index b67158c0ff..0000000000
--- a/arch/powerpc/cpu/mpc8xxx/ddr/ddr3_dimm_params.c
+++ /dev/null
@@ -1,337 +0,0 @@
-/*
- * Copyright 2008-2012 Freescale Semiconductor, Inc.
- *	Dave Liu <daveliu@freescale.com>
- *
- * calculate the organization and timing parameter
- * from ddr3 spd, please refer to the spec
- * JEDEC standard No.21-C 4_01_02_11R18.pdf
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * Version 2 as published by the Free Software Foundation.
- */
-
-#include <common.h>
-#include <asm/fsl_ddr_sdram.h>
-
-#include "ddr.h"
-
-/*
- * Calculate the Density of each Physical Rank.
- * Returned size is in bytes.
- *
- * each rank size =
- * sdram capacity(bit) / 8 * primary bus width / sdram width
- *
- * where: sdram capacity  = spd byte4[3:0]
- *        primary bus width = spd byte8[2:0]
- *        sdram width = spd byte7[2:0]
- *
- * SPD byte4 - sdram density and banks
- *	bit[3:0]	size(bit)	size(byte)
- *	0000		256Mb		32MB
- *	0001		512Mb		64MB
- *	0010		1Gb		128MB
- *	0011		2Gb		256MB
- *	0100		4Gb		512MB
- *	0101		8Gb		1GB
- *	0110		16Gb		2GB
- *
- * SPD byte8 - module memory bus width
- * 	bit[2:0]	primary bus width
- *	000		8bits
- * 	001		16bits
- * 	010		32bits
- * 	011		64bits
- *
- * SPD byte7 - module organiztion
- * 	bit[2:0]	sdram device width
- * 	000		4bits
- * 	001		8bits
- * 	010		16bits
- * 	011		32bits
- *
- */
-static unsigned long long
-compute_ranksize(const ddr3_spd_eeprom_t *spd)
-{
-	unsigned long long bsize;
-
-	int nbit_sdram_cap_bsize = 0;
-	int nbit_primary_bus_width = 0;
-	int nbit_sdram_width = 0;
-
-	if ((spd->density_banks & 0xf) < 7)
-		nbit_sdram_cap_bsize = (spd->density_banks & 0xf) + 28;
-	if ((spd->bus_width & 0x7) < 4)
-		nbit_primary_bus_width = (spd->bus_width & 0x7) + 3;
-	if ((spd->organization & 0x7) < 4)
-		nbit_sdram_width = (spd->organization & 0x7) + 2;
-
-	bsize = 1ULL << (nbit_sdram_cap_bsize - 3
-		    + nbit_primary_bus_width - nbit_sdram_width);
-
-	debug("DDR: DDR III rank density = 0x%16llx\n", bsize);
-
-	return bsize;
-}
-
-/*
- * ddr_compute_dimm_parameters for DDR3 SPD
- *
- * Compute DIMM parameters based upon the SPD information in spd.
- * Writes the results to the dimm_params_t structure pointed by pdimm.
- *
- */
-unsigned int
-ddr_compute_dimm_parameters(const ddr3_spd_eeprom_t *spd,
-			     dimm_params_t *pdimm,
-			     unsigned int dimm_number)
-{
-	unsigned int retval;
-	unsigned int mtb_ps;
-	int ftb_10th_ps;
-	int i;
-
-	if (spd->mem_type) {
-		if (spd->mem_type != SPD_MEMTYPE_DDR3) {
-			printf("DIMM %u: is not a DDR3 SPD.\n", dimm_number);
-			return 1;
-		}
-	} else {
-		memset(pdimm, 0, sizeof(dimm_params_t));
-		return 1;
-	}
-
-	retval = ddr3_spd_check(spd);
-	if (retval) {
-		printf("DIMM %u: failed checksum\n", dimm_number);
-		return 2;
-	}
-
-	/*
-	 * The part name in ASCII in the SPD EEPROM is not null terminated.
-	 * Guarantee null termination here by presetting all bytes to 0
-	 * and copying the part name in ASCII from the SPD onto it
-	 */
-	memset(pdimm->mpart, 0, sizeof(pdimm->mpart));
-	if ((spd->info_size_crc & 0xF) > 1)
-		memcpy(pdimm->mpart, spd->mpart, sizeof(pdimm->mpart) - 1);
-
-	/* DIMM organization parameters */
-	pdimm->n_ranks = ((spd->organization >> 3) & 0x7) + 1;
-	pdimm->rank_density = compute_ranksize(spd);
-	pdimm->capacity = pdimm->n_ranks * pdimm->rank_density;
-	pdimm->primary_sdram_width = 1 << (3 + (spd->bus_width & 0x7));
-	if ((spd->bus_width >> 3) & 0x3)
-		pdimm->ec_sdram_width = 8;
-	else
-		pdimm->ec_sdram_width = 0;
-	pdimm->data_width = pdimm->primary_sdram_width
-			  + pdimm->ec_sdram_width;
-	pdimm->device_width = 1 << ((spd->organization & 0x7) + 2);
-
-	/* These are the types defined by the JEDEC DDR3 SPD spec */
-	pdimm->mirrored_dimm = 0;
-	pdimm->registered_dimm = 0;
-	switch (spd->module_type & DDR3_SPD_MODULETYPE_MASK) {
-	case DDR3_SPD_MODULETYPE_RDIMM:
-	case DDR3_SPD_MODULETYPE_MINI_RDIMM:
-	case DDR3_SPD_MODULETYPE_72B_SO_RDIMM:
-		/* Registered/buffered DIMMs */
-		pdimm->registered_dimm = 1;
-		for (i = 0; i < 16; i += 2) {
-			u8 rcw = spd->mod_section.registered.rcw[i/2];
-			pdimm->rcw[i]   = (rcw >> 0) & 0x0F;
-			pdimm->rcw[i+1] = (rcw >> 4) & 0x0F;
-		}
-		break;
-
-	case DDR3_SPD_MODULETYPE_UDIMM:
-	case DDR3_SPD_MODULETYPE_SO_DIMM:
-	case DDR3_SPD_MODULETYPE_MICRO_DIMM:
-	case DDR3_SPD_MODULETYPE_MINI_UDIMM:
-	case DDR3_SPD_MODULETYPE_MINI_CDIMM:
-	case DDR3_SPD_MODULETYPE_72B_SO_UDIMM:
-	case DDR3_SPD_MODULETYPE_72B_SO_CDIMM:
-	case DDR3_SPD_MODULETYPE_LRDIMM:
-	case DDR3_SPD_MODULETYPE_16B_SO_DIMM:
-	case DDR3_SPD_MODULETYPE_32B_SO_DIMM:
-		/* Unbuffered DIMMs */
-		if (spd->mod_section.unbuffered.addr_mapping & 0x1)
-			pdimm->mirrored_dimm = 1;
-		break;
-
-	default:
-		printf("unknown module_type 0x%02X\n", spd->module_type);
-		return 1;
-	}
-
-	/* SDRAM device parameters */
-	pdimm->n_row_addr = ((spd->addressing >> 3) & 0x7) + 12;
-	pdimm->n_col_addr = (spd->addressing & 0x7) + 9;
-	pdimm->n_banks_per_sdram_device = 8 << ((spd->density_banks >> 4) & 0x7);
-
-	/*
-	 * The SPD spec has not the ECC bit,
-	 * We consider the DIMM as ECC capability
-	 * when the extension bus exist
-	 */
-	if (pdimm->ec_sdram_width)
-		pdimm->edc_config = 0x02;
-	else
-		pdimm->edc_config = 0x00;
-
-	/*
-	 * The SPD spec has not the burst length byte
-	 * but DDR3 spec has nature BL8 and BC4,
-	 * BL8 -bit3, BC4 -bit2
-	 */
-	pdimm->burst_lengths_bitmask = 0x0c;
-	pdimm->row_density = __ilog2(pdimm->rank_density);
-
-	/* MTB - medium timebase
-	 * The unit in the SPD spec is ns,
-	 * We convert it to ps.
-	 * eg: MTB = 0.125ns (125ps)
-	 */
-	mtb_ps = (spd->mtb_dividend * 1000) /spd->mtb_divisor;
-	pdimm->mtb_ps = mtb_ps;
-
-	/*
-	 * FTB - fine timebase
-	 * use 1/10th of ps as our unit to avoid floating point
-	 * eg, 10 for 1ps, 25 for 2.5ps, 50 for 5ps
-	 */
-	ftb_10th_ps =
-		((spd->ftb_div & 0xf0) >> 4) * 10 / (spd->ftb_div & 0x0f);
-	pdimm->ftb_10th_ps = ftb_10th_ps;
-	/*
-	 * sdram minimum cycle time
-	 * we assume the MTB is 0.125ns
-	 * eg:
-	 * tCK_min=15 MTB (1.875ns) ->DDR3-1066
-	 *        =12 MTB (1.5ns) ->DDR3-1333
-	 *        =10 MTB (1.25ns) ->DDR3-1600
-	 */
-	pdimm->tCKmin_X_ps = spd->tCK_min * mtb_ps +
-		(spd->fine_tCK_min * ftb_10th_ps) / 10;
-
-	/*
-	 * CAS latency supported
-	 * bit4 - CL4
-	 * bit5 - CL5
-	 * bit18 - CL18
-	 */
-	pdimm->caslat_X  = ((spd->caslat_msb << 8) | spd->caslat_lsb) << 4;
-
-	/*
-	 * min CAS latency time
-	 * eg: tAA_min =
-	 * DDR3-800D	100 MTB (12.5ns)
-	 * DDR3-1066F	105 MTB (13.125ns)
-	 * DDR3-1333H	108 MTB (13.5ns)
-	 * DDR3-1600H	90 MTB (11.25ns)
-	 */
-	pdimm->tAA_ps = spd->tAA_min * mtb_ps +
-		(spd->fine_tAA_min * ftb_10th_ps) / 10;
-
-	/*
-	 * min write recovery time
-	 * eg:
-	 * tWR_min = 120 MTB (15ns) -> all speed grades.
-	 */
-	pdimm->tWR_ps = spd->tWR_min * mtb_ps;
-
-	/*
-	 * min RAS to CAS delay time
-	 * eg: tRCD_min =
-	 * DDR3-800	100 MTB (12.5ns)
-	 * DDR3-1066F	105 MTB (13.125ns)
-	 * DDR3-1333H	108 MTB (13.5ns)
-	 * DDR3-1600H	90 MTB (11.25)
-	 */
-	pdimm->tRCD_ps = spd->tRCD_min * mtb_ps +
-		(spd->fine_tRCD_min * ftb_10th_ps) / 10;
-
-	/*
-	 * min row active to row active delay time
-	 * eg: tRRD_min =
-	 * DDR3-800(1KB page)	80 MTB (10ns)
-	 * DDR3-1333(1KB page)	48 MTB (6ns)
-	 */
-	pdimm->tRRD_ps = spd->tRRD_min * mtb_ps;
-
-	/*
-	 * min row precharge delay time
-	 * eg: tRP_min =
-	 * DDR3-800D	100 MTB (12.5ns)
-	 * DDR3-1066F	105 MTB (13.125ns)
-	 * DDR3-1333H	108 MTB (13.5ns)
-	 * DDR3-1600H	90 MTB (11.25ns)
-	 */
-	pdimm->tRP_ps = spd->tRP_min * mtb_ps +
-		(spd->fine_tRP_min * ftb_10th_ps) / 10;
-
-	/* min active to precharge delay time
-	 * eg: tRAS_min =
-	 * DDR3-800D	300 MTB (37.5ns)
-	 * DDR3-1066F	300 MTB (37.5ns)
-	 * DDR3-1333H	288 MTB (36ns)
-	 * DDR3-1600H	280 MTB (35ns)
-	 */
-	pdimm->tRAS_ps = (((spd->tRAS_tRC_ext & 0xf) << 8) | spd->tRAS_min_lsb)
-			* mtb_ps;
-	/*
-	 * min active to actice/refresh delay time
-	 * eg: tRC_min =
-	 * DDR3-800D	400 MTB (50ns)
-	 * DDR3-1066F	405 MTB (50.625ns)
-	 * DDR3-1333H	396 MTB (49.5ns)
-	 * DDR3-1600H	370 MTB (46.25ns)
-	 */
-	pdimm->tRC_ps = (((spd->tRAS_tRC_ext & 0xf0) << 4) | spd->tRC_min_lsb)
-			* mtb_ps + (spd->fine_tRC_min * ftb_10th_ps) / 10;
-	/*
-	 * min refresh recovery delay time
-	 * eg: tRFC_min =
-	 * 512Mb	720 MTB (90ns)
-	 * 1Gb		880 MTB (110ns)
-	 * 2Gb		1280 MTB (160ns)
-	 */
-	pdimm->tRFC_ps = ((spd->tRFC_min_msb << 8) | spd->tRFC_min_lsb)
-			* mtb_ps;
-	/*
-	 * min internal write to read command delay time
-	 * eg: tWTR_min = 40 MTB (7.5ns) - all speed bins.
-	 * tWRT is at least 4 mclk independent of operating freq.
-	 */
-	pdimm->tWTR_ps = spd->tWTR_min * mtb_ps;
-
-	/*
-	 * min internal read to precharge command delay time
-	 * eg: tRTP_min = 40 MTB (7.5ns) - all speed bins.
-	 * tRTP is at least 4 mclk independent of operating freq.
-	 */
-	pdimm->tRTP_ps = spd->tRTP_min * mtb_ps;
-
-	/*
-	 * Average periodic refresh interval
-	 * tREFI = 7.8 us at normal temperature range
-	 *       = 3.9 us at ext temperature range
-	 */
-	pdimm->refresh_rate_ps = 7800000;
-
-	/*
-	 * min four active window delay time
-	 * eg: tFAW_min =
-	 * DDR3-800(1KB page)	320 MTB (40ns)
-	 * DDR3-1066(1KB page)	300 MTB (37.5ns)
-	 * DDR3-1333(1KB page)	240 MTB (30ns)
-	 * DDR3-1600(1KB page)	240 MTB (30ns)
-	 */
-	pdimm->tFAW_ps = (((spd->tFAW_msb & 0xf) << 8) | spd->tFAW_min)
-			* mtb_ps;
-
-	return 0;
-}
diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/interactive.c b/arch/powerpc/cpu/mpc8xxx/ddr/interactive.c
deleted file mode 100644
index 260fce577f..0000000000
--- a/arch/powerpc/cpu/mpc8xxx/ddr/interactive.c
+++ /dev/null
@@ -1,1870 +0,0 @@
-/*
- * Copyright 2010-2012 Freescale Semiconductor, Inc.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-/*
- * Generic driver for Freescale DDR/DDR2/DDR3 memory controller.
- * Based on code from spd_sdram.c
- * Author: James Yang [at freescale.com]
- *         York Sun [at freescale.com]
- */
-
-#include <common.h>
-#include <linux/ctype.h>
-#include <asm/types.h>
-
-#include <asm/fsl_ddr_sdram.h>
-#include "ddr.h"
-
-/* Option parameter Structures */
-struct options_string {
-	const char *option_name;
-	size_t offset;
-	unsigned int size;
-	const char printhex;
-};
-
-static unsigned int picos_to_mhz(unsigned int picos)
-{
-	return 1000000 / picos;
-}
-
-static void print_option_table(const struct options_string *table,
-			 int table_size,
-			 const void *base)
-{
-	unsigned int i;
-	unsigned int *ptr;
-	unsigned long long *ptr_l;
-
-	for (i = 0; i < table_size; i++) {
-		switch (table[i].size) {
-		case 4:
-			ptr = (unsigned int *) (base + table[i].offset);
-			if (table[i].printhex) {
-				printf("%s = 0x%08X\n",
-					table[i].option_name, *ptr);
-			} else {
-				printf("%s = %u\n",
-					table[i].option_name, *ptr);
-			}
-			break;
-		case 8:
-			ptr_l = (unsigned long long *) (base + table[i].offset);
-			printf("%s = %llu\n",
-				table[i].option_name, *ptr_l);
-			break;
-		default:
-			printf("Unrecognized size!\n");
-			break;
-		}
-	}
-}
-
-static int handle_option_table(const struct options_string *table,
-			 int table_size,
-			 void *base,
-			 const char *opt,
-			 const char *val)
-{
-	unsigned int i;
-	unsigned int value, *ptr;
-	unsigned long long value_l, *ptr_l;
-
-	for (i = 0; i < table_size; i++) {
-		if (strcmp(table[i].option_name, opt) != 0)
-			continue;
-		switch (table[i].size) {
-		case 4:
-			value = simple_strtoul(val, NULL, 0);
-			ptr = base + table[i].offset;
-			*ptr = value;
-			break;
-		case 8:
-			value_l = simple_strtoull(val, NULL, 0);
-			ptr_l = base + table[i].offset;
-			*ptr_l = value_l;
-			break;
-		default:
-			printf("Unrecognized size!\n");
-			break;
-		}
-		return 1;
-	}
-
-	return 0;
-}
-
-static void fsl_ddr_generic_edit(void *pdata,
-			   void *pend,
-			   unsigned int element_size,
-			   unsigned int element_num,
-			   unsigned int value)
-{
-	char *pcdata = (char *)pdata;		/* BIG ENDIAN ONLY */
-
-	pcdata += element_num * element_size;
-	if ((pcdata + element_size) > (char *) pend) {
-		printf("trying to write past end of data\n");
-		return;
-	}
-
-	switch (element_size) {
-	case 1:
-		__raw_writeb(value, pcdata);
-		break;
-	case 2:
-		__raw_writew(value, pcdata);
-		break;
-	case 4:
-		__raw_writel(value, pcdata);
-		break;
-	default:
-		printf("unexpected element size %u\n", element_size);
-		break;
-	}
-}
-
-static void fsl_ddr_spd_edit(fsl_ddr_info_t *pinfo,
-		       unsigned int ctrl_num,
-		       unsigned int dimm_num,
-		       unsigned int element_num,
-		       unsigned int value)
-{
-	generic_spd_eeprom_t *pspd;
-
-	pspd = &(pinfo->spd_installed_dimms[ctrl_num][dimm_num]);
-	fsl_ddr_generic_edit(pspd, pspd + 1, 1, element_num, value);
-}
-
-#define COMMON_TIMING(x) {#x, offsetof(common_timing_params_t, x), \
-	sizeof((common_timing_params_t *)0)->x, 0}
-
-static void lowest_common_dimm_parameters_edit(fsl_ddr_info_t *pinfo,
-					unsigned int ctrl_num,
-					const char *optname_str,
-					const char *value_str)
-{
-	common_timing_params_t *p = &pinfo->common_timing_params[ctrl_num];
-
-	static const struct options_string options[] = {
-		COMMON_TIMING(tCKmin_X_ps),
-		COMMON_TIMING(tCKmax_ps),
-		COMMON_TIMING(tCKmax_max_ps),
-		COMMON_TIMING(tRCD_ps),
-		COMMON_TIMING(tRP_ps),
-		COMMON_TIMING(tRAS_ps),
-		COMMON_TIMING(tWR_ps),
-		COMMON_TIMING(tWTR_ps),
-		COMMON_TIMING(tRFC_ps),
-		COMMON_TIMING(tRRD_ps),
-		COMMON_TIMING(tRC_ps),
-		COMMON_TIMING(refresh_rate_ps),
-		COMMON_TIMING(tIS_ps),
-		COMMON_TIMING(tIH_ps),
-		COMMON_TIMING(tDS_ps),
-		COMMON_TIMING(tDH_ps),
-		COMMON_TIMING(tRTP_ps),
-		COMMON_TIMING(tDQSQ_max_ps),
-		COMMON_TIMING(tQHS_ps),
-		COMMON_TIMING(ndimms_present),
-		COMMON_TIMING(lowest_common_SPD_caslat),
-		COMMON_TIMING(highest_common_derated_caslat),
-		COMMON_TIMING(additive_latency),
-		COMMON_TIMING(all_DIMMs_burst_lengths_bitmask),
-		COMMON_TIMING(all_DIMMs_registered),
-		COMMON_TIMING(all_DIMMs_unbuffered),
-		COMMON_TIMING(all_DIMMs_ECC_capable),
-		COMMON_TIMING(total_mem),
-		COMMON_TIMING(base_address),
-	};
-	static const unsigned int n_opts = ARRAY_SIZE(options);
-
-	if (handle_option_table(options, n_opts, p, optname_str, value_str))
-		return;
-
-	printf("Error: couldn't find option string %s\n", optname_str);
-}
-
-#define DIMM_PARM(x) {#x, offsetof(dimm_params_t, x), \
-	sizeof((dimm_params_t *)0)->x, 0}
-
-static void fsl_ddr_dimm_parameters_edit(fsl_ddr_info_t *pinfo,
-				   unsigned int ctrl_num,
-				   unsigned int dimm_num,
-				   const char *optname_str,
-				   const char *value_str)
-{
-	dimm_params_t *p = &(pinfo->dimm_params[ctrl_num][dimm_num]);
-
-	static const struct options_string options[] = {
-		DIMM_PARM(n_ranks),
-		DIMM_PARM(data_width),
-		DIMM_PARM(primary_sdram_width),
-		DIMM_PARM(ec_sdram_width),
-		DIMM_PARM(registered_dimm),
-		DIMM_PARM(device_width),
-
-		DIMM_PARM(n_row_addr),
-		DIMM_PARM(n_col_addr),
-		DIMM_PARM(edc_config),
-		DIMM_PARM(n_banks_per_sdram_device),
-		DIMM_PARM(burst_lengths_bitmask),
-		DIMM_PARM(row_density),
-
-		DIMM_PARM(tCKmin_X_ps),
-		DIMM_PARM(tCKmin_X_minus_1_ps),
-		DIMM_PARM(tCKmin_X_minus_2_ps),
-		DIMM_PARM(tCKmax_ps),
-
-		DIMM_PARM(caslat_X),
-		DIMM_PARM(caslat_X_minus_1),
-		DIMM_PARM(caslat_X_minus_2),
-
-		DIMM_PARM(caslat_lowest_derated),
-
-		DIMM_PARM(tRCD_ps),
-		DIMM_PARM(tRP_ps),
-		DIMM_PARM(tRAS_ps),
-		DIMM_PARM(tWR_ps),
-		DIMM_PARM(tWTR_ps),
-		DIMM_PARM(tRFC_ps),
-		DIMM_PARM(tRRD_ps),
-		DIMM_PARM(tRC_ps),
-		DIMM_PARM(refresh_rate_ps),
-
-		DIMM_PARM(tIS_ps),
-		DIMM_PARM(tIH_ps),
-		DIMM_PARM(tDS_ps),
-		DIMM_PARM(tDH_ps),
-		DIMM_PARM(tRTP_ps),
-		DIMM_PARM(tDQSQ_max_ps),
-		DIMM_PARM(tQHS_ps),
-
-		DIMM_PARM(rank_density),
-		DIMM_PARM(capacity),
-		DIMM_PARM(base_address),
-	};
-
-	static const unsigned int n_opts = ARRAY_SIZE(options);
-
-	if (handle_option_table(options, n_opts, p, optname_str, value_str))
-		return;
-
-	printf("couldn't find option string %s\n", optname_str);
-}
-
-static void print_dimm_parameters(const dimm_params_t *pdimm)
-{
-	static const struct options_string options[] = {
-		DIMM_PARM(n_ranks),
-		DIMM_PARM(data_width),
-		DIMM_PARM(primary_sdram_width),
-		DIMM_PARM(ec_sdram_width),
-		DIMM_PARM(registered_dimm),
-		DIMM_PARM(device_width),
-
-		DIMM_PARM(n_row_addr),
-		DIMM_PARM(n_col_addr),
-		DIMM_PARM(edc_config),
-		DIMM_PARM(n_banks_per_sdram_device),
-
-		DIMM_PARM(tCKmin_X_ps),
-		DIMM_PARM(tCKmin_X_minus_1_ps),
-		DIMM_PARM(tCKmin_X_minus_2_ps),
-		DIMM_PARM(tCKmax_ps),
-
-		DIMM_PARM(caslat_X),
-		DIMM_PARM(tAA_ps),
-		DIMM_PARM(caslat_X_minus_1),
-		DIMM_PARM(caslat_X_minus_2),
-		DIMM_PARM(caslat_lowest_derated),
-
-		DIMM_PARM(tRCD_ps),
-		DIMM_PARM(tRP_ps),
-		DIMM_PARM(tRAS_ps),
-		DIMM_PARM(tWR_ps),
-		DIMM_PARM(tWTR_ps),
-		DIMM_PARM(tRFC_ps),
-		DIMM_PARM(tRRD_ps),
-		DIMM_PARM(tRC_ps),
-		DIMM_PARM(refresh_rate_ps),
-
-		DIMM_PARM(tIS_ps),
-		DIMM_PARM(tIH_ps),
-		DIMM_PARM(tDS_ps),
-		DIMM_PARM(tDH_ps),
-		DIMM_PARM(tRTP_ps),
-		DIMM_PARM(tDQSQ_max_ps),
-		DIMM_PARM(tQHS_ps),
-	};
-	static const unsigned int n_opts = ARRAY_SIZE(options);
-
-	if (pdimm->n_ranks == 0) {
-		printf("DIMM not present\n");
-		return;
-	}
-	printf("DIMM organization parameters:\n");
-	printf("module part name = %s\n", pdimm->mpart);
-	printf("rank_density = %llu bytes (%llu megabytes)\n",
-	       pdimm->rank_density, pdimm->rank_density / 0x100000);
-	printf("capacity = %llu bytes (%llu megabytes)\n",
-	       pdimm->capacity, pdimm->capacity / 0x100000);
-	printf("burst_lengths_bitmask = %02X\n",
-	       pdimm->burst_lengths_bitmask);
-	printf("base_addresss = %llu (%08llX %08llX)\n",
-	       pdimm->base_address,
-	       (pdimm->base_address >> 32),
-	       pdimm->base_address & 0xFFFFFFFF);
-	print_option_table(options, n_opts, pdimm);
-}
-
-static void print_lowest_common_dimm_parameters(
-		const common_timing_params_t *plcd_dimm_params)
-{
-	static const struct options_string options[] = {
-		COMMON_TIMING(tCKmax_max_ps),
-		COMMON_TIMING(tRCD_ps),
-		COMMON_TIMING(tRP_ps),
-		COMMON_TIMING(tRAS_ps),
-		COMMON_TIMING(tWR_ps),
-		COMMON_TIMING(tWTR_ps),
-		COMMON_TIMING(tRFC_ps),
-		COMMON_TIMING(tRRD_ps),
-		COMMON_TIMING(tRC_ps),
-		COMMON_TIMING(refresh_rate_ps),
-		COMMON_TIMING(tIS_ps),
-		COMMON_TIMING(tDS_ps),
-		COMMON_TIMING(tDH_ps),
-		COMMON_TIMING(tRTP_ps),
-		COMMON_TIMING(tDQSQ_max_ps),
-		COMMON_TIMING(tQHS_ps),
-		COMMON_TIMING(lowest_common_SPD_caslat),
-		COMMON_TIMING(highest_common_derated_caslat),
-		COMMON_TIMING(additive_latency),
-		COMMON_TIMING(ndimms_present),
-		COMMON_TIMING(all_DIMMs_registered),
-		COMMON_TIMING(all_DIMMs_unbuffered),
-		COMMON_TIMING(all_DIMMs_ECC_capable),
-	};
-	static const unsigned int n_opts = ARRAY_SIZE(options);
-
-	/* Clock frequencies */
-	printf("tCKmin_X_ps = %u (%u MHz)\n",
-	       plcd_dimm_params->tCKmin_X_ps,
-	       picos_to_mhz(plcd_dimm_params->tCKmin_X_ps));
-	printf("tCKmax_ps = %u (%u MHz)\n",
-	       plcd_dimm_params->tCKmax_ps,
-	       picos_to_mhz(plcd_dimm_params->tCKmax_ps));
-	printf("all_DIMMs_burst_lengths_bitmask = %02X\n",
-	       plcd_dimm_params->all_DIMMs_burst_lengths_bitmask);
-
-	print_option_table(options, n_opts, plcd_dimm_params);
-
-	printf("total_mem = %llu (%llu megabytes)\n",
-	       plcd_dimm_params->total_mem,
-	       plcd_dimm_params->total_mem / 0x100000);
-	printf("base_address = %llu (%llu megabytes)\n",
-	       plcd_dimm_params->base_address,
-	       plcd_dimm_params->base_address / 0x100000);
-}
-
-#define CTRL_OPTIONS(x) {#x, offsetof(memctl_options_t, x), \
-	sizeof((memctl_options_t *)0)->x, 0}
-#define CTRL_OPTIONS_CS(x, y) {"cs" #x "_" #y, \
-	offsetof(memctl_options_t, cs_local_opts[x].y), \
-	sizeof((memctl_options_t *)0)->cs_local_opts[x].y, 0}
-
-static void fsl_ddr_options_edit(fsl_ddr_info_t *pinfo,
-			   unsigned int ctl_num,
-			   const char *optname_str,
-			   const char *value_str)
-{
-	memctl_options_t *p = &(pinfo->memctl_opts[ctl_num]);
-	/*
-	 * This array all on the stack and *computed* each time this
-	 * function is rung.
-	 */
-	static const struct options_string options[] = {
-		CTRL_OPTIONS_CS(0, odt_rd_cfg),
-		CTRL_OPTIONS_CS(0, odt_wr_cfg),
-#if (CONFIG_CHIP_SELECTS_PER_CTRL > 1)
-		CTRL_OPTIONS_CS(1, odt_rd_cfg),
-		CTRL_OPTIONS_CS(1, odt_wr_cfg),
-#endif
-#if (CONFIG_CHIP_SELECTS_PER_CTRL > 2)
-		CTRL_OPTIONS_CS(2, odt_rd_cfg),
-		CTRL_OPTIONS_CS(2, odt_wr_cfg),
-#endif
-#if (CONFIG_CHIP_SELECTS_PER_CTRL > 2)
-		CTRL_OPTIONS_CS(3, odt_rd_cfg),
-		CTRL_OPTIONS_CS(3, odt_wr_cfg),
-#endif
-#if defined(CONFIG_FSL_DDR3)
-		CTRL_OPTIONS_CS(0, odt_rtt_norm),
-		CTRL_OPTIONS_CS(0, odt_rtt_wr),
-#if (CONFIG_CHIP_SELECTS_PER_CTRL > 1)
-		CTRL_OPTIONS_CS(1, odt_rtt_norm),
-		CTRL_OPTIONS_CS(1, odt_rtt_wr),
-#endif
-#if (CONFIG_CHIP_SELECTS_PER_CTRL > 2)
-		CTRL_OPTIONS_CS(2, odt_rtt_norm),
-		CTRL_OPTIONS_CS(2, odt_rtt_wr),
-#endif
-#if (CONFIG_CHIP_SELECTS_PER_CTRL > 2)
-		CTRL_OPTIONS_CS(3, odt_rtt_norm),
-		CTRL_OPTIONS_CS(3, odt_rtt_wr),
-#endif
-#endif
-		CTRL_OPTIONS(memctl_interleaving),
-		CTRL_OPTIONS(memctl_interleaving_mode),
-		CTRL_OPTIONS(ba_intlv_ctl),
-		CTRL_OPTIONS(ECC_mode),
-		CTRL_OPTIONS(ECC_init_using_memctl),
-		CTRL_OPTIONS(DQS_config),
-		CTRL_OPTIONS(self_refresh_in_sleep),
-		CTRL_OPTIONS(dynamic_power),
-		CTRL_OPTIONS(data_bus_width),
-		CTRL_OPTIONS(burst_length),
-		CTRL_OPTIONS(cas_latency_override),
-		CTRL_OPTIONS(cas_latency_override_value),
-		CTRL_OPTIONS(use_derated_caslat),
-		CTRL_OPTIONS(additive_latency_override),
-		CTRL_OPTIONS(additive_latency_override_value),
-		CTRL_OPTIONS(clk_adjust),
-		CTRL_OPTIONS(cpo_override),
-		CTRL_OPTIONS(write_data_delay),
-		CTRL_OPTIONS(half_strength_driver_enable),
-
-		/*
-		 * These can probably be changed to 2T_EN and 3T_EN
-		 * (using a leading numerical character) without problem
-		 */
-		CTRL_OPTIONS(twoT_en),
-		CTRL_OPTIONS(threeT_en),
-		CTRL_OPTIONS(ap_en),
-		CTRL_OPTIONS(x4_en),
-		CTRL_OPTIONS(bstopre),
-		CTRL_OPTIONS(wrlvl_override),
-		CTRL_OPTIONS(wrlvl_sample),
-		CTRL_OPTIONS(wrlvl_start),
-		CTRL_OPTIONS(rcw_override),
-		CTRL_OPTIONS(rcw_1),
-		CTRL_OPTIONS(rcw_2),
-		CTRL_OPTIONS(ddr_cdr1),
-		CTRL_OPTIONS(ddr_cdr2),
-		CTRL_OPTIONS(tCKE_clock_pulse_width_ps),
-		CTRL_OPTIONS(tFAW_window_four_activates_ps),
-		CTRL_OPTIONS(trwt_override),
-		CTRL_OPTIONS(trwt),
-	};
-
-	static const unsigned int n_opts = ARRAY_SIZE(options);
-
-	if (handle_option_table(options, n_opts, p,
-					optname_str, value_str))
-		return;
-
-	printf("couldn't find option string %s\n", optname_str);
-}
-
-#define CFG_REGS(x) {#x, offsetof(fsl_ddr_cfg_regs_t, x), \
-	sizeof((fsl_ddr_cfg_regs_t *)0)->x, 1}
-#define CFG_REGS_CS(x, y) {"cs" #x "_" #y, \
-	offsetof(fsl_ddr_cfg_regs_t, cs[x].y), \
-	sizeof((fsl_ddr_cfg_regs_t *)0)->cs[x].y, 1}
-
-static void print_fsl_memctl_config_regs(const fsl_ddr_cfg_regs_t *ddr)
-{
-	unsigned int i;
-	static const struct options_string options[] = {
-		CFG_REGS_CS(0, bnds),
-		CFG_REGS_CS(0, config),
-		CFG_REGS_CS(0, config_2),
-#if (CONFIG_CHIP_SELECTS_PER_CTRL > 1)
-		CFG_REGS_CS(1, bnds),
-		CFG_REGS_CS(1, config),
-		CFG_REGS_CS(1, config_2),
-#endif
-#if (CONFIG_CHIP_SELECTS_PER_CTRL > 2)
-		CFG_REGS_CS(2, bnds),
-		CFG_REGS_CS(2, config),
-		CFG_REGS_CS(2, config_2),
-#endif
-#if (CONFIG_CHIP_SELECTS_PER_CTRL > 2)
-		CFG_REGS_CS(3, bnds),
-		CFG_REGS_CS(3, config),
-		CFG_REGS_CS(3, config_2),
-#endif
-		CFG_REGS(timing_cfg_3),
-		CFG_REGS(timing_cfg_0),
-		CFG_REGS(timing_cfg_1),
-		CFG_REGS(timing_cfg_2),
-		CFG_REGS(ddr_sdram_cfg),
-		CFG_REGS(ddr_sdram_cfg_2),
-		CFG_REGS(ddr_sdram_mode),
-		CFG_REGS(ddr_sdram_mode_2),
-		CFG_REGS(ddr_sdram_mode_3),
-		CFG_REGS(ddr_sdram_mode_4),
-		CFG_REGS(ddr_sdram_mode_5),
-		CFG_REGS(ddr_sdram_mode_6),
-		CFG_REGS(ddr_sdram_mode_7),
-		CFG_REGS(ddr_sdram_mode_8),
-		CFG_REGS(ddr_sdram_interval),
-		CFG_REGS(ddr_data_init),
-		CFG_REGS(ddr_sdram_clk_cntl),
-		CFG_REGS(ddr_init_addr),
-		CFG_REGS(ddr_init_ext_addr),
-		CFG_REGS(timing_cfg_4),
-		CFG_REGS(timing_cfg_5),
-		CFG_REGS(ddr_zq_cntl),
-		CFG_REGS(ddr_wrlvl_cntl),
-		CFG_REGS(ddr_wrlvl_cntl_2),
-		CFG_REGS(ddr_wrlvl_cntl_3),
-		CFG_REGS(ddr_sr_cntr),
-		CFG_REGS(ddr_sdram_rcw_1),
-		CFG_REGS(ddr_sdram_rcw_2),
-		CFG_REGS(ddr_cdr1),
-		CFG_REGS(ddr_cdr2),
-		CFG_REGS(err_disable),
-		CFG_REGS(err_int_en),
-		CFG_REGS(ddr_eor),
-	};
-	static const unsigned int n_opts = ARRAY_SIZE(options);
-
-	print_option_table(options, n_opts, ddr);
-
-	for (i = 0; i < 32; i++)
-		printf("debug_%02d = 0x%08X\n", i+1, ddr->debug[i]);
-}
-
-static void fsl_ddr_regs_edit(fsl_ddr_info_t *pinfo,
-			unsigned int ctrl_num,
-			const char *regname,
-			const char *value_str)
-{
-	unsigned int i;
-	fsl_ddr_cfg_regs_t *ddr;
-	char buf[20];
-	static const struct options_string options[] = {
-		CFG_REGS_CS(0, bnds),
-		CFG_REGS_CS(0, config),
-		CFG_REGS_CS(0, config_2),
-#if (CONFIG_CHIP_SELECTS_PER_CTRL > 1)
-		CFG_REGS_CS(1, bnds),
-		CFG_REGS_CS(1, config),
-		CFG_REGS_CS(1, config_2),
-#endif
-#if (CONFIG_CHIP_SELECTS_PER_CTRL > 2)
-		CFG_REGS_CS(2, bnds),
-		CFG_REGS_CS(2, config),
-		CFG_REGS_CS(2, config_2),
-#endif
-#if (CONFIG_CHIP_SELECTS_PER_CTRL > 3)
-		CFG_REGS_CS(3, bnds),
-		CFG_REGS_CS(3, config),
-		CFG_REGS_CS(3, config_2),
-#endif
-		CFG_REGS(timing_cfg_3),
-		CFG_REGS(timing_cfg_0),
-		CFG_REGS(timing_cfg_1),
-		CFG_REGS(timing_cfg_2),
-		CFG_REGS(ddr_sdram_cfg),
-		CFG_REGS(ddr_sdram_cfg_2),
-		CFG_REGS(ddr_sdram_mode),
-		CFG_REGS(ddr_sdram_mode_2),
-		CFG_REGS(ddr_sdram_mode_3),
-		CFG_REGS(ddr_sdram_mode_4),
-		CFG_REGS(ddr_sdram_mode_5),
-		CFG_REGS(ddr_sdram_mode_6),
-		CFG_REGS(ddr_sdram_mode_7),
-		CFG_REGS(ddr_sdram_mode_8),
-		CFG_REGS(ddr_sdram_interval),
-		CFG_REGS(ddr_data_init),
-		CFG_REGS(ddr_sdram_clk_cntl),
-		CFG_REGS(ddr_init_addr),
-		CFG_REGS(ddr_init_ext_addr),
-		CFG_REGS(timing_cfg_4),
-		CFG_REGS(timing_cfg_5),
-		CFG_REGS(ddr_zq_cntl),
-		CFG_REGS(ddr_wrlvl_cntl),
-		CFG_REGS(ddr_wrlvl_cntl_2),
-		CFG_REGS(ddr_wrlvl_cntl_3),
-		CFG_REGS(ddr_sr_cntr),
-		CFG_REGS(ddr_sdram_rcw_1),
-		CFG_REGS(ddr_sdram_rcw_2),
-		CFG_REGS(ddr_cdr1),
-		CFG_REGS(ddr_cdr2),
-		CFG_REGS(err_disable),
-		CFG_REGS(err_int_en),
-		CFG_REGS(ddr_sdram_rcw_2),
-		CFG_REGS(ddr_sdram_rcw_2),
-		CFG_REGS(ddr_eor),
-	};
-	static const unsigned int n_opts = ARRAY_SIZE(options);
-
-	debug("fsl_ddr_regs_edit: ctrl_num = %u, "
-		"regname = %s, value = %s\n",
-		ctrl_num, regname, value_str);
-	if (ctrl_num > CONFIG_NUM_DDR_CONTROLLERS)
-		return;
-
-	ddr = &(pinfo->fsl_ddr_config_reg[ctrl_num]);
-
-	if (handle_option_table(options, n_opts, ddr, regname, value_str))
-		return;
-
-	for (i = 0; i < 32; i++) {
-		unsigned int value = simple_strtoul(value_str, NULL, 0);
-		sprintf(buf, "debug_%u", i + 1);
-		if (strcmp(buf, regname) == 0) {
-			ddr->debug[i] = value;
-			return;
-		}
-	}
-	printf("Error: couldn't find register string %s\n", regname);
-}
-
-#define CTRL_OPTIONS_HEX(x) {#x, offsetof(memctl_options_t, x), \
-	sizeof((memctl_options_t *)0)->x, 1}
-
-static void print_memctl_options(const memctl_options_t *popts)
-{
-	static const struct options_string options[] = {
-		CTRL_OPTIONS_CS(0, odt_rd_cfg),
-		CTRL_OPTIONS_CS(0, odt_wr_cfg),
-#if (CONFIG_CHIP_SELECTS_PER_CTRL > 1)
-		CTRL_OPTIONS_CS(1, odt_rd_cfg),
-		CTRL_OPTIONS_CS(1, odt_wr_cfg),
-#endif
-#if (CONFIG_CHIP_SELECTS_PER_CTRL > 2)
-		CTRL_OPTIONS_CS(2, odt_rd_cfg),
-		CTRL_OPTIONS_CS(2, odt_wr_cfg),
-#endif
-#if (CONFIG_CHIP_SELECTS_PER_CTRL > 3)
-		CTRL_OPTIONS_CS(3, odt_rd_cfg),
-		CTRL_OPTIONS_CS(3, odt_wr_cfg),
-#endif
-#if defined(CONFIG_FSL_DDR3)
-		CTRL_OPTIONS_CS(0, odt_rtt_norm),
-		CTRL_OPTIONS_CS(0, odt_rtt_wr),
-#if (CONFIG_CHIP_SELECTS_PER_CTRL > 1)
-		CTRL_OPTIONS_CS(1, odt_rtt_norm),
-		CTRL_OPTIONS_CS(1, odt_rtt_wr),
-#endif
-#if (CONFIG_CHIP_SELECTS_PER_CTRL > 2)
-		CTRL_OPTIONS_CS(2, odt_rtt_norm),
-		CTRL_OPTIONS_CS(2, odt_rtt_wr),
-#endif
-#if (CONFIG_CHIP_SELECTS_PER_CTRL > 3)
-		CTRL_OPTIONS_CS(3, odt_rtt_norm),
-		CTRL_OPTIONS_CS(3, odt_rtt_wr),
-#endif
-#endif
-		CTRL_OPTIONS(memctl_interleaving),
-		CTRL_OPTIONS(memctl_interleaving_mode),
-		CTRL_OPTIONS_HEX(ba_intlv_ctl),
-		CTRL_OPTIONS(ECC_mode),
-		CTRL_OPTIONS(ECC_init_using_memctl),
-		CTRL_OPTIONS(DQS_config),
-		CTRL_OPTIONS(self_refresh_in_sleep),
-		CTRL_OPTIONS(dynamic_power),
-		CTRL_OPTIONS(data_bus_width),
-		CTRL_OPTIONS(burst_length),
-		CTRL_OPTIONS(cas_latency_override),
-		CTRL_OPTIONS(cas_latency_override_value),
-		CTRL_OPTIONS(use_derated_caslat),
-		CTRL_OPTIONS(additive_latency_override),
-		CTRL_OPTIONS(additive_latency_override_value),
-		CTRL_OPTIONS(clk_adjust),
-		CTRL_OPTIONS(cpo_override),
-		CTRL_OPTIONS(write_data_delay),
-		CTRL_OPTIONS(half_strength_driver_enable),
-		/*
-		 * These can probably be changed to 2T_EN and 3T_EN
-		 * (using a leading numerical character) without problem
-		 */
-		CTRL_OPTIONS(twoT_en),
-		CTRL_OPTIONS(threeT_en),
-		CTRL_OPTIONS(registered_dimm_en),
-		CTRL_OPTIONS(ap_en),
-		CTRL_OPTIONS(x4_en),
-		CTRL_OPTIONS(bstopre),
-		CTRL_OPTIONS(wrlvl_override),
-		CTRL_OPTIONS(wrlvl_sample),
-		CTRL_OPTIONS(wrlvl_start),
-		CTRL_OPTIONS(rcw_override),
-		CTRL_OPTIONS(rcw_1),
-		CTRL_OPTIONS(rcw_2),
-		CTRL_OPTIONS_HEX(ddr_cdr1),
-		CTRL_OPTIONS_HEX(ddr_cdr2),
-		CTRL_OPTIONS(tCKE_clock_pulse_width_ps),
-		CTRL_OPTIONS(tFAW_window_four_activates_ps),
-		CTRL_OPTIONS(trwt_override),
-		CTRL_OPTIONS(trwt),
-	};
-	static const unsigned int n_opts = ARRAY_SIZE(options);
-
-	print_option_table(options, n_opts, popts);
-}
-
-#ifdef CONFIG_FSL_DDR1
-void ddr1_spd_dump(const ddr1_spd_eeprom_t *spd)
-{
-	unsigned int i;
-
-	printf("%-3d    : %02x %s\n", 0, spd->info_size,
-	       " spd->info_size,   *  0 # bytes written into serial memory *");
-	printf("%-3d    : %02x %s\n", 1, spd->chip_size,
-	       " spd->chip_size,   *  1 Total # bytes of SPD memory device *");
-	printf("%-3d    : %02x %s\n", 2, spd->mem_type,
-	       " spd->mem_type,    *  2 Fundamental memory type *");
-	printf("%-3d    : %02x %s\n", 3, spd->nrow_addr,
-	       " spd->nrow_addr,   *  3 # of Row Addresses on this assembly *");
-	printf("%-3d    : %02x %s\n", 4, spd->ncol_addr,
-	       " spd->ncol_addr,   *  4 # of Column Addrs on this assembly *");
-	printf("%-3d    : %02x %s\n", 5, spd->nrows,
-	       " spd->nrows        *  5 # of DIMM Banks *");
-	printf("%-3d    : %02x %s\n", 6, spd->dataw_lsb,
-	       " spd->dataw_lsb,   *  6 Data Width lsb of this assembly *");
-	printf("%-3d    : %02x %s\n", 7, spd->dataw_msb,
-	       " spd->dataw_msb,   *  7 Data Width msb of this assembly *");
-	printf("%-3d    : %02x %s\n", 8, spd->voltage,
-	       " spd->voltage,     *  8 Voltage intf std of this assembly *");
-	printf("%-3d    : %02x %s\n", 9, spd->clk_cycle,
-	       " spd->clk_cycle,   *  9 SDRAM Cycle time at CL=X *");
-	printf("%-3d    : %02x %s\n", 10, spd->clk_access,
-	       " spd->clk_access,  * 10 SDRAM Access from Clock at CL=X *");
-	printf("%-3d    : %02x %s\n", 11, spd->config,
-	       " spd->config,      * 11 DIMM Configuration type *");
-	printf("%-3d    : %02x %s\n", 12, spd->refresh,
-	       " spd->refresh,     * 12 Refresh Rate/Type *");
-	printf("%-3d    : %02x %s\n", 13, spd->primw,
-	       " spd->primw,       * 13 Primary SDRAM Width *");
-	printf("%-3d    : %02x %s\n", 14, spd->ecw,
-	       " spd->ecw,         * 14 Error Checking SDRAM width *");
-	printf("%-3d    : %02x %s\n", 15, spd->min_delay,
-	       " spd->min_delay,   * 15 Back to Back Random Access *");
-	printf("%-3d    : %02x %s\n", 16, spd->burstl,
-	       " spd->burstl,      * 16 Burst Lengths Supported *");
-	printf("%-3d    : %02x %s\n", 17, spd->nbanks,
-	       " spd->nbanks,      * 17 # of Banks on Each SDRAM Device *");
-	printf("%-3d    : %02x %s\n", 18, spd->cas_lat,
-	       " spd->cas_lat,     * 18 CAS# Latencies Supported *");
-	printf("%-3d    : %02x %s\n", 19, spd->cs_lat,
-	       " spd->cs_lat,      * 19 Chip Select Latency *");
-	printf("%-3d    : %02x %s\n", 20, spd->write_lat,
-	       " spd->write_lat,   * 20 Write Latency/Recovery *");
-	printf("%-3d    : %02x %s\n", 21, spd->mod_attr,
-	       " spd->mod_attr,    * 21 SDRAM Module Attributes *");
-	printf("%-3d    : %02x %s\n", 22, spd->dev_attr,
-	       " spd->dev_attr,    * 22 SDRAM Device Attributes *");
-	printf("%-3d    : %02x %s\n", 23, spd->clk_cycle2,
-	       " spd->clk_cycle2,  * 23 Min SDRAM Cycle time at CL=X-1 *");
-	printf("%-3d    : %02x %s\n", 24, spd->clk_access2,
-	       " spd->clk_access2, * 24 SDRAM Access from Clock at CL=X-1 *");
-	printf("%-3d    : %02x %s\n", 25, spd->clk_cycle3,
-	       " spd->clk_cycle3,  * 25 Min SDRAM Cycle time at CL=X-2 *");
-	printf("%-3d    : %02x %s\n", 26, spd->clk_access3,
-	       " spd->clk_access3, * 26 Max Access from Clock at CL=X-2 *");
-	printf("%-3d    : %02x %s\n", 27, spd->trp,
-	       " spd->trp,         * 27 Min Row Precharge Time (tRP)*");
-	printf("%-3d    : %02x %s\n", 28, spd->trrd,
-	       " spd->trrd,        * 28 Min Row Active to Row Active (tRRD) *");
-	printf("%-3d    : %02x %s\n", 29, spd->trcd,
-	       " spd->trcd,        * 29 Min RAS to CAS Delay (tRCD) *");
-	printf("%-3d    : %02x %s\n", 30, spd->tras,
-	       " spd->tras,        * 30 Minimum RAS Pulse Width (tRAS) *");
-	printf("%-3d    : %02x %s\n", 31, spd->bank_dens,
-	       " spd->bank_dens,   * 31 Density of each bank on module *");
-	printf("%-3d    : %02x %s\n", 32, spd->ca_setup,
-	       " spd->ca_setup,    * 32 Cmd + Addr signal input setup time *");
-	printf("%-3d    : %02x %s\n", 33, spd->ca_hold,
-	       " spd->ca_hold,     * 33 Cmd and Addr signal input hold time *");
-	printf("%-3d    : %02x %s\n", 34, spd->data_setup,
-	       " spd->data_setup,  * 34 Data signal input setup time *");
-	printf("%-3d    : %02x %s\n", 35, spd->data_hold,
-	       " spd->data_hold,   * 35 Data signal input hold time *");
-	printf("%-3d    : %02x %s\n", 36, spd->res_36_40[0],
-	       " spd->res_36_40[0], * 36 Reserved / tWR *");
-	printf("%-3d    : %02x %s\n", 37, spd->res_36_40[1],
-	       " spd->res_36_40[1], * 37 Reserved / tWTR *");
-	printf("%-3d    : %02x %s\n", 38, spd->res_36_40[2],
-	       " spd->res_36_40[2], * 38 Reserved / tRTP *");
-	printf("%-3d    : %02x %s\n", 39, spd->res_36_40[3],
-	       " spd->res_36_40[3], * 39 Reserved / mem_probe *");
-	printf("%-3d    : %02x %s\n", 40, spd->res_36_40[4],
-	       " spd->res_36_40[4], * 40 Reserved / trc,trfc extensions *");
-	printf("%-3d    : %02x %s\n", 41, spd->trc,
-	       " spd->trc,         * 41 Min Active to Auto refresh time tRC *");
-	printf("%-3d    : %02x %s\n", 42, spd->trfc,
-	       " spd->trfc,        * 42 Min Auto to Active period tRFC *");
-	printf("%-3d    : %02x %s\n", 43, spd->tckmax,
-	       " spd->tckmax,      * 43 Max device cycle time tCKmax *");
-	printf("%-3d    : %02x %s\n", 44, spd->tdqsq,
-	       " spd->tdqsq,       * 44 Max DQS to DQ skew *");
-	printf("%-3d    : %02x %s\n", 45, spd->tqhs,
-	       " spd->tqhs,        * 45 Max Read DataHold skew tQHS *");
-	printf("%-3d    : %02x %s\n", 46, spd->res_46,
-	       " spd->res_46,  * 46 Reserved/ PLL Relock time *");
-	printf("%-3d    : %02x %s\n", 47, spd->dimm_height,
-	       " spd->dimm_height  * 47 SDRAM DIMM Height *");
-
-	printf("%-3d-%3d: ",  48, 61);
-
-	for (i = 0; i < 14; i++)
-		printf("%02x", spd->res_48_61[i]);
-
-	printf(" * 48-61 IDD in SPD and Reserved space *\n");
-
-	printf("%-3d    : %02x %s\n", 62, spd->spd_rev,
-	       " spd->spd_rev,     * 62 SPD Data Revision Code *");
-	printf("%-3d    : %02x %s\n", 63, spd->cksum,
-	       " spd->cksum,       * 63 Checksum for bytes 0-62 *");
-	printf("%-3d-%3d: ",  64, 71);
-
-	for (i = 0; i < 8; i++)
-		printf("%02x", spd->mid[i]);
-
-	printf("* 64 Mfr's JEDEC ID code per JEP-108E *\n");
-	printf("%-3d    : %02x %s\n", 72, spd->mloc,
-	       " spd->mloc,        * 72 Manufacturing Location *");
-
-	printf("%-3d-%3d: >>",  73, 90);
-
-	for (i = 0; i < 18; i++)
-		printf("%c", spd->mpart[i]);
-
-	printf("<<* 73 Manufacturer's Part Number *\n");
-
-	printf("%-3d-%3d: %02x %02x %s\n", 91, 92, spd->rev[0], spd->rev[1],
-	       "* 91 Revision Code *");
-	printf("%-3d-%3d: %02x %02x %s\n", 93, 94, spd->mdate[0], spd->mdate[1],
-	       "* 93 Manufacturing Date *");
-	printf("%-3d-%3d: ", 95, 98);
-
-	for (i = 0; i < 4; i++)
-		printf("%02x", spd->sernum[i]);
-
-	printf("* 95 Assembly Serial Number *\n");
-
-	printf("%-3d-%3d: ", 99, 127);
-
-	for (i = 0; i < 27; i++)
-		printf("%02x", spd->mspec[i]);
-
-	printf("* 99 Manufacturer Specific Data *\n");
-}
-#endif
-
-#ifdef CONFIG_FSL_DDR2
-void ddr2_spd_dump(const ddr2_spd_eeprom_t *spd)
-{
-	unsigned int i;
-
-	printf("%-3d    : %02x %s\n", 0, spd->info_size,
-	       " spd->info_size,   *  0 # bytes written into serial memory *");
-	printf("%-3d    : %02x %s\n", 1, spd->chip_size,
-	       " spd->chip_size,   *  1 Total # bytes of SPD memory device *");
-	printf("%-3d    : %02x %s\n", 2, spd->mem_type,
-	       " spd->mem_type,    *  2 Fundamental memory type *");
-	printf("%-3d    : %02x %s\n", 3, spd->nrow_addr,
-	       " spd->nrow_addr,   *  3 # of Row Addresses on this assembly *");
-	printf("%-3d    : %02x %s\n", 4, spd->ncol_addr,
-	       " spd->ncol_addr,   *  4 # of Column Addrs on this assembly *");
-	printf("%-3d    : %02x %s\n", 5, spd->mod_ranks,
-	       " spd->mod_ranks    *  5 # of Module Rows on this assembly *");
-	printf("%-3d    : %02x %s\n", 6, spd->dataw,
-	       " spd->dataw,       *  6 Data Width of this assembly *");
-	printf("%-3d    : %02x %s\n", 7, spd->res_7,
-	       " spd->res_7,       *  7 Reserved *");
-	printf("%-3d    : %02x %s\n", 8, spd->voltage,
-	       " spd->voltage,     *  8 Voltage intf std of this assembly *");
-	printf("%-3d    : %02x %s\n", 9, spd->clk_cycle,
-	       " spd->clk_cycle,   *  9 SDRAM Cycle time at CL=X *");
-	printf("%-3d    : %02x %s\n", 10, spd->clk_access,
-	       " spd->clk_access,  * 10 SDRAM Access from Clock at CL=X *");
-	printf("%-3d    : %02x %s\n", 11, spd->config,
-	       " spd->config,      * 11 DIMM Configuration type *");
-	printf("%-3d    : %02x %s\n", 12, spd->refresh,
-	       " spd->refresh,     * 12 Refresh Rate/Type *");
-	printf("%-3d    : %02x %s\n", 13, spd->primw,
-	       " spd->primw,       * 13 Primary SDRAM Width *");
-	printf("%-3d    : %02x %s\n", 14, spd->ecw,
-	       " spd->ecw,         * 14 Error Checking SDRAM width *");
-	printf("%-3d    : %02x %s\n", 15, spd->res_15,
-	       " spd->res_15,      * 15 Reserved *");
-	printf("%-3d    : %02x %s\n", 16, spd->burstl,
-	       " spd->burstl,      * 16 Burst Lengths Supported *");
-	printf("%-3d    : %02x %s\n", 17, spd->nbanks,
-	       " spd->nbanks,      * 17 # of Banks on Each SDRAM Device *");
-	printf("%-3d    : %02x %s\n", 18, spd->cas_lat,
-	       " spd->cas_lat,     * 18 CAS# Latencies Supported *");
-	printf("%-3d    : %02x %s\n", 19, spd->mech_char,
-	       " spd->mech_char,   * 19 Mechanical Characteristics *");
-	printf("%-3d    : %02x %s\n", 20, spd->dimm_type,
-	       " spd->dimm_type,   * 20 DIMM type *");
-	printf("%-3d    : %02x %s\n", 21, spd->mod_attr,
-	       " spd->mod_attr,    * 21 SDRAM Module Attributes *");
-	printf("%-3d    : %02x %s\n", 22, spd->dev_attr,
-	       " spd->dev_attr,    * 22 SDRAM Device Attributes *");
-	printf("%-3d    : %02x %s\n", 23, spd->clk_cycle2,
-	       " spd->clk_cycle2,  * 23 Min SDRAM Cycle time at CL=X-1 *");
-	printf("%-3d    : %02x %s\n", 24, spd->clk_access2,
-	       " spd->clk_access2, * 24 SDRAM Access from Clock at CL=X-1 *");
-	printf("%-3d    : %02x %s\n", 25, spd->clk_cycle3,
-	       " spd->clk_cycle3,  * 25 Min SDRAM Cycle time at CL=X-2 *");
-	printf("%-3d    : %02x %s\n", 26, spd->clk_access3,
-	       " spd->clk_access3, * 26 Max Access from Clock at CL=X-2 *");
-	printf("%-3d    : %02x %s\n", 27, spd->trp,
-	       " spd->trp,         * 27 Min Row Precharge Time (tRP)*");
-	printf("%-3d    : %02x %s\n", 28, spd->trrd,
-	       " spd->trrd,        * 28 Min Row Active to Row Active (tRRD) *");
-	printf("%-3d    : %02x %s\n", 29, spd->trcd,
-	       " spd->trcd,        * 29 Min RAS to CAS Delay (tRCD) *");
-	printf("%-3d    : %02x %s\n", 30, spd->tras,
-	       " spd->tras,        * 30 Minimum RAS Pulse Width (tRAS) *");
-	printf("%-3d    : %02x %s\n", 31, spd->rank_dens,
-	       " spd->rank_dens,   * 31 Density of each rank on module *");
-	printf("%-3d    : %02x %s\n", 32, spd->ca_setup,
-	       " spd->ca_setup,    * 32 Cmd + Addr signal input setup time *");
-	printf("%-3d    : %02x %s\n", 33, spd->ca_hold,
-	       " spd->ca_hold,     * 33 Cmd and Addr signal input hold time *");
-	printf("%-3d    : %02x %s\n", 34, spd->data_setup,
-	       " spd->data_setup,  * 34 Data signal input setup time *");
-	printf("%-3d    : %02x %s\n", 35, spd->data_hold,
-	       " spd->data_hold,   * 35 Data signal input hold time *");
-	printf("%-3d    : %02x %s\n", 36, spd->twr,
-	       " spd->twr,         * 36 Write Recovery time tWR *");
-	printf("%-3d    : %02x %s\n", 37, spd->twtr,
-	       " spd->twtr,        * 37 Int write to read delay tWTR *");
-	printf("%-3d    : %02x %s\n", 38, spd->trtp,
-	       " spd->trtp,        * 38 Int read to precharge delay tRTP *");
-	printf("%-3d    : %02x %s\n", 39, spd->mem_probe,
-	       " spd->mem_probe,   * 39 Mem analysis probe characteristics *");
-	printf("%-3d    : %02x %s\n", 40, spd->trctrfc_ext,
-	       " spd->trctrfc_ext, * 40 Extensions to trc and trfc *");
-	printf("%-3d    : %02x %s\n", 41, spd->trc,
-	       " spd->trc,         * 41 Min Active to Auto refresh time tRC *");
-	printf("%-3d    : %02x %s\n", 42, spd->trfc,
-	       " spd->trfc,        * 42 Min Auto to Active period tRFC *");
-	printf("%-3d    : %02x %s\n", 43, spd->tckmax,
-	       " spd->tckmax,      * 43 Max device cycle time tCKmax *");
-	printf("%-3d    : %02x %s\n", 44, spd->tdqsq,
-	       " spd->tdqsq,       * 44 Max DQS to DQ skew *");
-	printf("%-3d    : %02x %s\n", 45, spd->tqhs,
-	       " spd->tqhs,        * 45 Max Read DataHold skew tQHS *");
-	printf("%-3d    : %02x %s\n", 46, spd->pll_relock,
-	       " spd->pll_relock,  * 46 PLL Relock time *");
-	printf("%-3d    : %02x %s\n", 47, spd->Tcasemax,
-	       " spd->Tcasemax,    * 47 Tcasemax *");
-	printf("%-3d    : %02x %s\n", 48, spd->psiTAdram,
-	       " spd->psiTAdram,   * 48 Thermal Resistance of DRAM Package "
-	       "from Top (Case) to Ambient (Psi T-A DRAM) *");
-	printf("%-3d    : %02x %s\n", 49, spd->dt0_mode,
-	       " spd->dt0_mode,    * 49 DRAM Case Temperature Rise from "
-	       "Ambient due to Activate-Precharge/Mode Bits "
-	       "(DT0/Mode Bits) *)");
-	printf("%-3d    : %02x %s\n", 50, spd->dt2n_dt2q,
-	       " spd->dt2n_dt2q,   * 50 DRAM Case Temperature Rise from "
-	       "Ambient due to Precharge/Quiet Standby "
-	       "(DT2N/DT2Q) *");
-	printf("%-3d    : %02x %s\n", 51, spd->dt2p,
-	       " spd->dt2p,        * 51 DRAM Case Temperature Rise from "
-	       "Ambient due to Precharge Power-Down (DT2P) *");
-	printf("%-3d    : %02x %s\n", 52, spd->dt3n,
-	       " spd->dt3n,        * 52 DRAM Case Temperature Rise from "
-	       "Ambient due to Active Standby (DT3N) *");
-	printf("%-3d    : %02x %s\n", 53, spd->dt3pfast,
-	       " spd->dt3pfast,    * 53 DRAM Case Temperature Rise from "
-	       "Ambient due to Active Power-Down with Fast PDN Exit "
-	       "(DT3Pfast) *");
-	printf("%-3d    : %02x %s\n", 54, spd->dt3pslow,
-	       " spd->dt3pslow,    * 54 DRAM Case Temperature Rise from "
-	       "Ambient due to Active Power-Down with Slow PDN Exit "
-	       "(DT3Pslow) *");
-	printf("%-3d    : %02x %s\n", 55, spd->dt4r_dt4r4w,
-	       " spd->dt4r_dt4r4w, * 55 DRAM Case Temperature Rise from "
-	       "Ambient due to Page Open Burst Read/DT4R4W Mode Bit "
-	       "(DT4R/DT4R4W Mode Bit) *");
-	printf("%-3d    : %02x %s\n", 56, spd->dt5b,
-	       " spd->dt5b,        * 56 DRAM Case Temperature Rise from "
-	       "Ambient due to Burst Refresh (DT5B) *");
-	printf("%-3d    : %02x %s\n", 57, spd->dt7,
-	       " spd->dt7,         * 57 DRAM Case Temperature Rise from "
-	       "Ambient due to Bank Interleave Reads with "
-	       "Auto-Precharge (DT7) *");
-	printf("%-3d    : %02x %s\n", 58, spd->psiTApll,
-	       " spd->psiTApll,    * 58 Thermal Resistance of PLL Package form"
-	       " Top (Case) to Ambient (Psi T-A PLL) *");
-	printf("%-3d    : %02x %s\n", 59, spd->psiTAreg,
-	       " spd->psiTAreg,    * 59 Thermal Reisitance of Register Package"
-	       " from Top (Case) to Ambient (Psi T-A Register) *");
-	printf("%-3d    : %02x %s\n", 60, spd->dtpllactive,
-	       " spd->dtpllactive, * 60 PLL Case Temperature Rise from "
-	       "Ambient due to PLL Active (DT PLL Active) *");
-	printf("%-3d    : %02x %s\n", 61, spd->dtregact,
-	       " spd->dtregact,    "
-	       "* 61 Register Case Temperature Rise from Ambient due to "
-	       "Register Active/Mode Bit (DT Register Active/Mode Bit) *");
-	printf("%-3d    : %02x %s\n", 62, spd->spd_rev,
-	       " spd->spd_rev,     * 62 SPD Data Revision Code *");
-	printf("%-3d    : %02x %s\n", 63, spd->cksum,
-	       " spd->cksum,       * 63 Checksum for bytes 0-62 *");
-
-	printf("%-3d-%3d: ",  64, 71);
-
-	for (i = 0; i < 8; i++)
-		printf("%02x", spd->mid[i]);
-
-	printf("* 64 Mfr's JEDEC ID code per JEP-108E *\n");
-
-	printf("%-3d    : %02x %s\n", 72, spd->mloc,
-	       " spd->mloc,        * 72 Manufacturing Location *");
-
-	printf("%-3d-%3d: >>",  73, 90);
-	for (i = 0; i < 18; i++)
-		printf("%c", spd->mpart[i]);
-
-
-	printf("<<* 73 Manufacturer's Part Number *\n");
-
-	printf("%-3d-%3d: %02x %02x %s\n", 91, 92, spd->rev[0], spd->rev[1],
-	       "* 91 Revision Code *");
-	printf("%-3d-%3d: %02x %02x %s\n", 93, 94, spd->mdate[0], spd->mdate[1],
-	       "* 93 Manufacturing Date *");
-	printf("%-3d-%3d: ", 95, 98);
-
-	for (i = 0; i < 4; i++)
-		printf("%02x", spd->sernum[i]);
-
-	printf("* 95 Assembly Serial Number *\n");
-
-	printf("%-3d-%3d: ", 99, 127);
-	for (i = 0; i < 27; i++)
-		printf("%02x", spd->mspec[i]);
-
-
-	printf("* 99 Manufacturer Specific Data *\n");
-}
-#endif
-
-#ifdef CONFIG_FSL_DDR3
-void ddr3_spd_dump(const ddr3_spd_eeprom_t *spd)
-{
-	unsigned int i;
-
-	/* General Section: Bytes 0-59 */
-
-#define PRINT_NXS(x, y, z...) printf("%-3d    : %02x " z "\n", x, (u8)y);
-#define PRINT_NNXXS(n0, n1, x0, x1, s) \
-	printf("%-3d-%3d: %02x %02x " s "\n", n0, n1, x0, x1);
-
-	PRINT_NXS(0, spd->info_size_crc,
-		"info_size_crc  bytes written into serial memory, "
-		"CRC coverage");
-	PRINT_NXS(1, spd->spd_rev,
-		"spd_rev        SPD Revision");
-	PRINT_NXS(2, spd->mem_type,
-		"mem_type       Key Byte / DRAM Device Type");
-	PRINT_NXS(3, spd->module_type,
-		"module_type    Key Byte / Module Type");
-	PRINT_NXS(4, spd->density_banks,
-		"density_banks  SDRAM Density and Banks");
-	PRINT_NXS(5, spd->addressing,
-		"addressing     SDRAM Addressing");
-	PRINT_NXS(6, spd->module_vdd,
-		"module_vdd     Module Nominal Voltage, VDD");
-	PRINT_NXS(7, spd->organization,
-		"organization   Module Organization");
-	PRINT_NXS(8, spd->bus_width,
-		"bus_width      Module Memory Bus Width");
-	PRINT_NXS(9, spd->ftb_div,
-		"ftb_div        Fine Timebase (FTB) Dividend / Divisor");
-	PRINT_NXS(10, spd->mtb_dividend,
-		"mtb_dividend   Medium Timebase (MTB) Dividend");
-	PRINT_NXS(11, spd->mtb_divisor,
-		"mtb_divisor    Medium Timebase (MTB) Divisor");
-	PRINT_NXS(12, spd->tCK_min,
-		"tCK_min        SDRAM Minimum Cycle Time");
-	PRINT_NXS(13, spd->res_13,
-		"res_13         Reserved");
-	PRINT_NXS(14, spd->caslat_lsb,
-		"caslat_lsb     CAS Latencies Supported, LSB");
-	PRINT_NXS(15, spd->caslat_msb,
-		"caslat_msb     CAS Latencies Supported, MSB");
-	PRINT_NXS(16, spd->tAA_min,
-		"tAA_min        Min CAS Latency Time");
-	PRINT_NXS(17, spd->tWR_min,
-		"tWR_min        Min Write REcovery Time");
-	PRINT_NXS(18, spd->tRCD_min,
-		"tRCD_min       Min RAS# to CAS# Delay Time");
-	PRINT_NXS(19, spd->tRRD_min,
-		"tRRD_min       Min Row Active to Row Active Delay Time");
-	PRINT_NXS(20, spd->tRP_min,
-		"tRP_min        Min Row Precharge Delay Time");
-	PRINT_NXS(21, spd->tRAS_tRC_ext,
-		"tRAS_tRC_ext   Upper Nibbles for tRAS and tRC");
-	PRINT_NXS(22, spd->tRAS_min_lsb,
-		"tRAS_min_lsb   Min Active to Precharge Delay Time, LSB");
-	PRINT_NXS(23, spd->tRC_min_lsb,
-		"tRC_min_lsb    Min Active to Active/Refresh Delay Time, LSB");
-	PRINT_NXS(24, spd->tRFC_min_lsb,
-		"tRFC_min_lsb   Min Refresh Recovery Delay Time LSB");
-	PRINT_NXS(25, spd->tRFC_min_msb,
-		"tRFC_min_msb   Min Refresh Recovery Delay Time MSB");
-	PRINT_NXS(26, spd->tWTR_min,
-		"tWTR_min       Min Internal Write to Read Command Delay Time");
-	PRINT_NXS(27, spd->tRTP_min,
-		"tRTP_min "
-		"Min Internal Read to Precharge Command Delay Time");
-	PRINT_NXS(28, spd->tFAW_msb,
-		"tFAW_msb       Upper Nibble for tFAW");
-	PRINT_NXS(29, spd->tFAW_min,
-		"tFAW_min       Min Four Activate Window Delay Time");
-	PRINT_NXS(30, spd->opt_features,
-		"opt_features   SDRAM Optional Features");
-	PRINT_NXS(31, spd->therm_ref_opt,
-		"therm_ref_opt  SDRAM Thermal and Refresh Opts");
-	PRINT_NXS(32, spd->therm_sensor,
-		"therm_sensor  SDRAM Thermal Sensor");
-	PRINT_NXS(33, spd->device_type,
-		"device_type  SDRAM Device Type");
-	PRINT_NXS(34, spd->fine_tCK_min,
-		"fine_tCK_min  Fine offset for tCKmin");
-	PRINT_NXS(35, spd->fine_tAA_min,
-		"fine_tAA_min  Fine offset for tAAmin");
-	PRINT_NXS(36, spd->fine_tRCD_min,
-		"fine_tRCD_min Fine offset for tRCDmin");
-	PRINT_NXS(37, spd->fine_tRP_min,
-		"fine_tRP_min  Fine offset for tRPmin");
-	PRINT_NXS(38, spd->fine_tRC_min,
-		"fine_tRC_min  Fine offset for tRCmin");
-
-	printf("%-3d-%3d: ",  39, 59);  /* Reserved, General Section */
-
-	for (i = 39; i <= 59; i++)
-		printf("%02x ", spd->res_39_59[i - 39]);
-
-	puts("\n");
-
-	switch (spd->module_type) {
-	case 0x02:  /* UDIMM */
-	case 0x03:  /* SO-DIMM */
-	case 0x04:  /* Micro-DIMM */
-	case 0x06:  /* Mini-UDIMM */
-		PRINT_NXS(60, spd->mod_section.unbuffered.mod_height,
-			"mod_height    (Unbuffered) Module Nominal Height");
-		PRINT_NXS(61, spd->mod_section.unbuffered.mod_thickness,
-			"mod_thickness (Unbuffered) Module Maximum Thickness");
-		PRINT_NXS(62, spd->mod_section.unbuffered.ref_raw_card,
-			"ref_raw_card  (Unbuffered) Reference Raw Card Used");
-		PRINT_NXS(63, spd->mod_section.unbuffered.addr_mapping,
-			"addr_mapping  (Unbuffered) Address mapping from "
-			"Edge Connector to DRAM");
-		break;
-	case 0x01:  /* RDIMM */
-	case 0x05:  /* Mini-RDIMM */
-		PRINT_NXS(60, spd->mod_section.registered.mod_height,
-			"mod_height    (Registered) Module Nominal Height");
-		PRINT_NXS(61, spd->mod_section.registered.mod_thickness,
-			"mod_thickness (Registered) Module Maximum Thickness");
-		PRINT_NXS(62, spd->mod_section.registered.ref_raw_card,
-			"ref_raw_card  (Registered) Reference Raw Card Used");
-		PRINT_NXS(63, spd->mod_section.registered.modu_attr,
-			"modu_attr     (Registered) DIMM Module Attributes");
-		PRINT_NXS(64, spd->mod_section.registered.thermal,
-			"thermal       (Registered) Thermal Heat "
-			"Spreader Solution");
-		PRINT_NXS(65, spd->mod_section.registered.reg_id_lo,
-			"reg_id_lo     (Registered) Register Manufacturer ID "
-			"Code, LSB");
-		PRINT_NXS(66, spd->mod_section.registered.reg_id_hi,
-			"reg_id_hi     (Registered) Register Manufacturer ID "
-			"Code, MSB");
-		PRINT_NXS(67, spd->mod_section.registered.reg_rev,
-			"reg_rev       (Registered) Register "
-			"Revision Number");
-		PRINT_NXS(68, spd->mod_section.registered.reg_type,
-			"reg_type      (Registered) Register Type");
-		for (i = 69; i <= 76; i++) {
-			printf("%-3d    : %02x rcw[%d]\n", i,
-				spd->mod_section.registered.rcw[i-69], i-69);
-		}
-		break;
-	default:
-		/* Module-specific Section, Unsupported Module Type */
-		printf("%-3d-%3d: ", 60, 116);
-
-		for (i = 60; i <= 116; i++)
-			printf("%02x", spd->mod_section.uc[i - 60]);
-
-		break;
-	}
-
-	/* Unique Module ID: Bytes 117-125 */
-	PRINT_NXS(117, spd->mmid_lsb, "Module MfgID Code LSB - JEP-106");
-	PRINT_NXS(118, spd->mmid_msb, "Module MfgID Code MSB - JEP-106");
-	PRINT_NXS(119, spd->mloc,     "Mfg Location");
-	PRINT_NNXXS(120, 121, spd->mdate[0], spd->mdate[1], "Mfg Date");
-
-	printf("%-3d-%3d: ", 122, 125);
-
-	for (i = 122; i <= 125; i++)
-		printf("%02x ", spd->sernum[i - 122]);
-	printf("   Module Serial Number\n");
-
-	/* CRC: Bytes 126-127 */
-	PRINT_NNXXS(126, 127, spd->crc[0], spd->crc[1], "  SPD CRC");
-
-	/* Other Manufacturer Fields and User Space: Bytes 128-255 */
-	printf("%-3d-%3d: ", 128, 145);
-	for (i = 128; i <= 145; i++)
-		printf("%02x ", spd->mpart[i - 128]);
-	printf("   Mfg's Module Part Number\n");
-
-	PRINT_NNXXS(146, 147, spd->mrev[0], spd->mrev[1],
-		"Module Revision code");
-
-	PRINT_NXS(148, spd->dmid_lsb, "DRAM MfgID Code LSB - JEP-106");
-	PRINT_NXS(149, spd->dmid_msb, "DRAM MfgID Code MSB - JEP-106");
-
-	printf("%-3d-%3d: ", 150, 175);
-	for (i = 150; i <= 175; i++)
-		printf("%02x ", spd->msd[i - 150]);
-	printf("   Mfg's Specific Data\n");
-
-	printf("%-3d-%3d: ", 176, 255);
-	for (i = 176; i <= 255; i++)
-		printf("%02x", spd->cust[i - 176]);
-	printf("   Mfg's Specific Data\n");
-
-}
-#endif
-
-static inline void generic_spd_dump(const generic_spd_eeprom_t *spd)
-{
-#if defined(CONFIG_FSL_DDR1)
-	ddr1_spd_dump(spd);
-#elif defined(CONFIG_FSL_DDR2)
-	ddr2_spd_dump(spd);
-#elif defined(CONFIG_FSL_DDR3)
-	ddr3_spd_dump(spd);
-#endif
-}
-
-static void fsl_ddr_printinfo(const fsl_ddr_info_t *pinfo,
-			unsigned int ctrl_mask,
-			unsigned int dimm_mask,
-			unsigned int do_mask)
-{
-	unsigned int i, j, retval;
-
-	/* STEP 1:  DIMM SPD data */
-	if (do_mask & STEP_GET_SPD) {
-		for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
-			if (!(ctrl_mask & (1 << i)))
-				continue;
-
-			for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
-				if (!(dimm_mask & (1 << j)))
-					continue;
-
-				printf("SPD info:  Controller=%u "
-						"DIMM=%u\n", i, j);
-				generic_spd_dump(
-					&(pinfo->spd_installed_dimms[i][j]));
-				printf("\n");
-			}
-			printf("\n");
-		}
-		printf("\n");
-	}
-
-	/* STEP 2:  DIMM Parameters */
-	if (do_mask & STEP_COMPUTE_DIMM_PARMS) {
-		for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
-			if (!(ctrl_mask & (1 << i)))
-				continue;
-			for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
-				if (!(dimm_mask & (1 << j)))
-					continue;
-				printf("DIMM parameters:  Controller=%u "
-						"DIMM=%u\n", i, j);
-				print_dimm_parameters(
-					&(pinfo->dimm_params[i][j]));
-				printf("\n");
-			}
-			printf("\n");
-		}
-		printf("\n");
-	}
-
-	/* STEP 3:  Common Parameters */
-	if (do_mask & STEP_COMPUTE_COMMON_PARMS) {
-		for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
-			if (!(ctrl_mask & (1 << i)))
-				continue;
-			printf("\"lowest common\" DIMM parameters:  "
-					"Controller=%u\n", i);
-			print_lowest_common_dimm_parameters(
-				&pinfo->common_timing_params[i]);
-			printf("\n");
-		}
-		printf("\n");
-	}
-
-	/* STEP 4:  User Configuration Options */
-	if (do_mask & STEP_GATHER_OPTS) {
-		for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
-			if (!(ctrl_mask & (1 << i)))
-				continue;
-			printf("User Config Options: Controller=%u\n", i);
-			print_memctl_options(&pinfo->memctl_opts[i]);
-			printf("\n");
-		}
-		printf("\n");
-	}
-
-	/* STEP 5:  Address assignment */
-	if (do_mask & STEP_ASSIGN_ADDRESSES) {
-		for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
-			if (!(ctrl_mask & (1 << i)))
-				continue;
-			for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
-				printf("Address Assignment: Controller=%u "
-						"DIMM=%u\n", i, j);
-				printf("Don't have this functionality yet\n");
-			}
-			printf("\n");
-		}
-		printf("\n");
-	}
-
-	/* STEP 6:  computed controller register values */
-	if (do_mask & STEP_COMPUTE_REGS) {
-		for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
-			if (!(ctrl_mask & (1 << i)))
-				continue;
-			printf("Computed Register Values: Controller=%u\n", i);
-			print_fsl_memctl_config_regs(
-				&pinfo->fsl_ddr_config_reg[i]);
-			retval = check_fsl_memctl_config_regs(
-				&pinfo->fsl_ddr_config_reg[i]);
-			if (retval) {
-				printf("check_fsl_memctl_config_regs "
-					"result = %u\n", retval);
-			}
-			printf("\n");
-		}
-		printf("\n");
-	}
-}
-
-struct data_strings {
-	const char *data_name;
-	unsigned int step_mask;
-	unsigned int dimm_number_required;
-};
-
-#define DATA_OPTIONS(name, step, dimm) {#name, step, dimm}
-
-static unsigned int fsl_ddr_parse_interactive_cmd(
-	char **argv,
-	int argc,
-	unsigned int *pstep_mask,
-	unsigned int *pctlr_mask,
-	unsigned int *pdimm_mask,
-	unsigned int *pdimm_number_required
-	 ) {
-
-	static const struct data_strings options[] = {
-		DATA_OPTIONS(spd, STEP_GET_SPD, 1),
-		DATA_OPTIONS(dimmparms, STEP_COMPUTE_DIMM_PARMS, 1),
-		DATA_OPTIONS(commonparms, STEP_COMPUTE_COMMON_PARMS, 0),
-		DATA_OPTIONS(opts, STEP_GATHER_OPTS, 0),
-		DATA_OPTIONS(addresses, STEP_ASSIGN_ADDRESSES, 0),
-		DATA_OPTIONS(regs, STEP_COMPUTE_REGS, 0),
-	};
-	static const unsigned int n_opts = ARRAY_SIZE(options);
-
-	unsigned int i, j;
-	unsigned int error = 0;
-
-	for (i = 1; i < argc; i++) {
-		unsigned int matched = 0;
-
-		for (j = 0; j < n_opts; j++) {
-			if (strcmp(options[j].data_name, argv[i]) != 0)
-				continue;
-			*pstep_mask |= options[j].step_mask;
-			*pdimm_number_required =
-				options[j].dimm_number_required;
-			matched = 1;
-			break;
-		}
-
-		if (matched)
-			continue;
-
-		if (argv[i][0] == 'c') {
-			char c = argv[i][1];
-			if (isdigit(c))
-				*pctlr_mask |= 1 << (c - '0');
-			continue;
-		}
-
-		if (argv[i][0] == 'd') {
-			char c = argv[i][1];
-			if (isdigit(c))
-				*pdimm_mask |= 1 << (c - '0');
-			continue;
-		}
-
-		printf("unknown arg %s\n", argv[i]);
-		*pstep_mask = 0;
-		error = 1;
-		break;
-	}
-
-	return error;
-}
-
-int fsl_ddr_interactive_env_var_exists(void)
-{
-	char buffer[CONFIG_SYS_CBSIZE];
-
-	if (getenv_f("ddr_interactive", buffer, CONFIG_SYS_CBSIZE) >= 0)
-		return 1;
-
-	return 0;
-}
-
-unsigned long long fsl_ddr_interactive(fsl_ddr_info_t *pinfo, int var_is_set)
-{
-	unsigned long long ddrsize;
-	const char *prompt = "FSL DDR>";
-	char buffer[CONFIG_SYS_CBSIZE];
-	char buffer2[CONFIG_SYS_CBSIZE];
-	char *p = NULL;
-	char *argv[CONFIG_SYS_MAXARGS + 1];	/* NULL terminated */
-	int argc;
-	unsigned int next_step = STEP_GET_SPD;
-	const char *usage = {
-		"commands:\n"
-		"print      print SPD and intermediate computed data\n"
-		"reset      reboot machine\n"
-		"recompute  reload SPD and options to default and recompute regs\n"
-		"edit       modify spd, parameter, or option\n"
-		"compute    recompute registers from current next_step to end\n"
-		"copy       copy parameters\n"
-		"next_step  shows current next_step\n"
-		"help       this message\n"
-		"go         program the memory controller and continue with u-boot\n"
-	};
-
-	if (var_is_set) {
-		if (getenv_f("ddr_interactive", buffer2, CONFIG_SYS_CBSIZE) > 0) {
-			p = buffer2;
-		} else {
-			var_is_set = 0;
-		}
-	}
-
-	/*
-	 * The strategy for next_step is that it points to the next
-	 * step in the computation process that needs to be done.
-	 */
-	while (1) {
-		if (var_is_set) {
-			char *pend = strchr(p, ';');
-			if (pend) {
-				/* found command separator, copy sub-command */
-				*pend = '\0';
-				strcpy(buffer, p);
-				p = pend + 1;
-			} else {
-				/* separator not found, copy whole string */
-				strcpy(buffer, p);
-				p = NULL;
-				var_is_set = 0;
-			}
-		} else {
-			/*
-			 * No need to worry for buffer overflow here in
-			 * this function;  readline() maxes out at CFG_CBSIZE
-			 */
-			readline_into_buffer(prompt, buffer, 0);
-		}
-		argc = parse_line(buffer, argv);
-		if (argc == 0)
-			continue;
-
-
-		if (strcmp(argv[0], "help") == 0) {
-			puts(usage);
-			continue;
-		}
-
-		if (strcmp(argv[0], "next_step") == 0) {
-			printf("next_step = 0x%02X (%s)\n",
-			       next_step,
-			       step_to_string(next_step));
-			continue;
-		}
-
-		if (strcmp(argv[0], "copy") == 0) {
-			unsigned int error = 0;
-			unsigned int step_mask = 0;
-			unsigned int src_ctlr_mask = 0;
-			unsigned int src_dimm_mask = 0;
-			unsigned int dimm_number_required = 0;
-			unsigned int src_ctlr_num = 0;
-			unsigned int src_dimm_num = 0;
-			unsigned int dst_ctlr_num = -1;
-			unsigned int dst_dimm_num = -1;
-			unsigned int i, num_dest_parms;
-
-			if (argc == 1) {
-				printf("copy <src c#> <src d#> <spd|dimmparms|commonparms|opts|addresses|regs> <dst c#> <dst d#>\n");
-				continue;
-			}
-
-			error = fsl_ddr_parse_interactive_cmd(
-				argv, argc,
-				&step_mask,
-				&src_ctlr_mask,
-				&src_dimm_mask,
-				&dimm_number_required
-			);
-
-			/* XXX: only dimm_number_required and step_mask will
-			   be used by this function.  Parse the controller and
-			   DIMM number separately because it is easier.  */
-
-			if (error)
-				continue;
-
-			/* parse source destination controller / DIMM */
-
-			num_dest_parms = dimm_number_required ? 2 : 1;
-
-			for (i = 0; i < argc; i++) {
-				if (argv[i][0] == 'c') {
-					char c = argv[i][1];
-					if (isdigit(c)) {
-						src_ctlr_num = (c - '0');
-						break;
-					}
-				}
-			}
-
-			for (i = 0; i < argc; i++) {
-				if (argv[i][0] == 'd') {
-					char c = argv[i][1];
-					if (isdigit(c)) {
-						src_dimm_num = (c - '0');
-						break;
-					}
-				}
-			}
-
-			/* parse destination controller / DIMM */
-
-			for (i = argc - 1; i >= argc - num_dest_parms; i--) {
-				if (argv[i][0] == 'c') {
-					char c = argv[i][1];
-					if (isdigit(c)) {
-						dst_ctlr_num = (c - '0');
-						break;
-					}
-				}
-			}
-
-			for (i = argc - 1; i >= argc - num_dest_parms; i--) {
-				if (argv[i][0] == 'd') {
-					char c = argv[i][1];
-					if (isdigit(c)) {
-						dst_dimm_num = (c - '0');
-						break;
-					}
-				}
-			}
-
-			/* TODO: validate inputs */
-
-			debug("src_ctlr_num = %u, src_dimm_num = %u, dst_ctlr_num = %u, dst_dimm_num = %u, step_mask = %x\n",
-				src_ctlr_num, src_dimm_num, dst_ctlr_num, dst_dimm_num, step_mask);
-
-
-			switch (step_mask) {
-
-			case STEP_GET_SPD:
-				memcpy(&(pinfo->spd_installed_dimms[dst_ctlr_num][dst_dimm_num]),
-					&(pinfo->spd_installed_dimms[src_ctlr_num][src_dimm_num]),
-					sizeof(pinfo->spd_installed_dimms[0][0]));
-				break;
-
-			case STEP_COMPUTE_DIMM_PARMS:
-				memcpy(&(pinfo->dimm_params[dst_ctlr_num][dst_dimm_num]),
-					&(pinfo->dimm_params[src_ctlr_num][src_dimm_num]),
-					sizeof(pinfo->dimm_params[0][0]));
-				break;
-
-			case STEP_COMPUTE_COMMON_PARMS:
-				memcpy(&(pinfo->common_timing_params[dst_ctlr_num]),
-					&(pinfo->common_timing_params[src_ctlr_num]),
-					sizeof(pinfo->common_timing_params[0]));
-				break;
-
-			case STEP_GATHER_OPTS:
-				memcpy(&(pinfo->memctl_opts[dst_ctlr_num]),
-					&(pinfo->memctl_opts[src_ctlr_num]),
-					sizeof(pinfo->memctl_opts[0]));
-				break;
-
-			/* someday be able to have addresses to copy addresses... */
-
-			case STEP_COMPUTE_REGS:
-				memcpy(&(pinfo->fsl_ddr_config_reg[dst_ctlr_num]),
-					&(pinfo->fsl_ddr_config_reg[src_ctlr_num]),
-					sizeof(pinfo->memctl_opts[0]));
-				break;
-
-			default:
-				printf("unexpected step_mask value\n");
-			}
-
-			continue;
-
-		}
-
-		if (strcmp(argv[0], "edit") == 0) {
-			unsigned int error = 0;
-			unsigned int step_mask = 0;
-			unsigned int ctlr_mask = 0;
-			unsigned int dimm_mask = 0;
-			char *p_element = NULL;
-			char *p_value = NULL;
-			unsigned int dimm_number_required = 0;
-			unsigned int ctrl_num;
-			unsigned int dimm_num;
-
-			if (argc == 1) {
-				/* Only the element and value must be last */
-				printf("edit <c#> <d#> "
-					"<spd|dimmparms|commonparms|opts|"
-					"addresses|regs> <element> <value>\n");
-				printf("for spd, specify byte number for "
-					"element\n");
-				continue;
-			}
-
-			error = fsl_ddr_parse_interactive_cmd(
-				argv, argc - 2,
-				&step_mask,
-				&ctlr_mask,
-				&dimm_mask,
-				&dimm_number_required
-			);
-
-			if (error)
-				continue;
-
-
-			/* Check arguments */
-
-			/* ERROR: If no steps were found */
-			if (step_mask == 0) {
-				printf("Error: No valid steps were specified "
-						"in argument.\n");
-				continue;
-			}
-
-			/* ERROR: If multiple steps were found */
-			if (step_mask & (step_mask - 1)) {
-				printf("Error: Multiple steps specified in "
-						"argument.\n");
-				continue;
-			}
-
-			/* ERROR: Controller not specified */
-			if (ctlr_mask == 0) {
-				printf("Error: controller number not "
-					"specified or no element and "
-					"value specified\n");
-				continue;
-			}
-
-			if (ctlr_mask & (ctlr_mask - 1)) {
-				printf("Error: multiple controllers "
-						"specified, %X\n", ctlr_mask);
-				continue;
-			}
-
-			/* ERROR: DIMM number not specified */
-			if (dimm_number_required && dimm_mask == 0) {
-				printf("Error: DIMM number number not "
-					"specified or no element and "
-					"value specified\n");
-				continue;
-			}
-
-			if (dimm_mask & (dimm_mask - 1)) {
-				printf("Error: multipled DIMMs specified\n");
-				continue;
-			}
-
-			p_element = argv[argc - 2];
-			p_value = argv[argc - 1];
-
-			ctrl_num = __ilog2(ctlr_mask);
-			dimm_num = __ilog2(dimm_mask);
-
-			switch (step_mask) {
-			case STEP_GET_SPD:
-				{
-					unsigned int element_num;
-					unsigned int value;
-
-					element_num = simple_strtoul(p_element,
-								     NULL, 0);
-					value = simple_strtoul(p_value,
-							       NULL, 0);
-					fsl_ddr_spd_edit(pinfo,
-							       ctrl_num,
-							       dimm_num,
-							       element_num,
-							       value);
-					next_step = STEP_COMPUTE_DIMM_PARMS;
-				}
-				break;
-
-			case STEP_COMPUTE_DIMM_PARMS:
-				fsl_ddr_dimm_parameters_edit(
-						 pinfo, ctrl_num, dimm_num,
-						 p_element, p_value);
-				next_step = STEP_COMPUTE_COMMON_PARMS;
-				break;
-
-			case STEP_COMPUTE_COMMON_PARMS:
-				lowest_common_dimm_parameters_edit(pinfo,
-						ctrl_num, p_element, p_value);
-				next_step = STEP_GATHER_OPTS;
-				break;
-
-			case STEP_GATHER_OPTS:
-				fsl_ddr_options_edit(pinfo, ctrl_num,
-							   p_element, p_value);
-				next_step = STEP_ASSIGN_ADDRESSES;
-				break;
-
-			case STEP_ASSIGN_ADDRESSES:
-				printf("editing of address assignment "
-						"not yet implemented\n");
-				break;
-
-			case STEP_COMPUTE_REGS:
-				{
-					fsl_ddr_regs_edit(pinfo,
-								ctrl_num,
-								p_element,
-								p_value);
-					next_step = STEP_PROGRAM_REGS;
-				}
-				break;
-
-			default:
-				printf("programming error\n");
-				while (1)
-					;
-				break;
-			}
-			continue;
-		}
-
-		if (strcmp(argv[0], "reset") == 0) {
-			/*
-			 * Reboot machine.
-			 * Args don't seem to matter because this
-			 * doesn't return
-			 */
-			do_reset(NULL, 0, 0, NULL);
-			printf("Reset didn't work\n");
-		}
-
-		if (strcmp(argv[0], "recompute") == 0) {
-			/*
-			 * Recalculate everything, starting with
-			 * loading SPD EEPROM from DIMMs
-			 */
-			next_step = STEP_GET_SPD;
-			ddrsize = fsl_ddr_compute(pinfo, next_step, 0);
-			continue;
-		}
-
-		if (strcmp(argv[0], "compute") == 0) {
-			/*
-			 * Compute rest of steps starting at
-			 * the current next_step/
-			 */
-			ddrsize = fsl_ddr_compute(pinfo, next_step, 0);
-			continue;
-		}
-
-		if (strcmp(argv[0], "print") == 0) {
-			unsigned int error = 0;
-			unsigned int step_mask = 0;
-			unsigned int ctlr_mask = 0;
-			unsigned int dimm_mask = 0;
-			unsigned int dimm_number_required = 0;
-
-			if (argc == 1) {
-				printf("print [c<n>] [d<n>] [spd] [dimmparms] "
-				  "[commonparms] [opts] [addresses] [regs]\n");
-				continue;
-			}
-
-			error = fsl_ddr_parse_interactive_cmd(
-				argv, argc,
-				&step_mask,
-				&ctlr_mask,
-				&dimm_mask,
-				&dimm_number_required
-			);
-
-			if (error)
-				continue;
-
-			/* If no particular controller was found, print all */
-			if (ctlr_mask == 0)
-				ctlr_mask = 0xFF;
-
-			/* If no particular dimm was found, print all dimms. */
-			if (dimm_mask == 0)
-				dimm_mask = 0xFF;
-
-			/* If no steps were found, print all steps. */
-			if (step_mask == 0)
-				step_mask = STEP_ALL;
-
-			fsl_ddr_printinfo(pinfo, ctlr_mask,
-						dimm_mask, step_mask);
-			continue;
-		}
-
-		if (strcmp(argv[0], "go") == 0) {
-			if (next_step)
-				ddrsize = fsl_ddr_compute(pinfo, next_step, 0);
-			break;
-		}
-
-		printf("unknown command %s\n", argv[0]);
-	}
-
-	debug("end of memory = %llu\n", (u64)ddrsize);
-
-	return ddrsize;
-}
diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/lc_common_dimm_params.c b/arch/powerpc/cpu/mpc8xxx/ddr/lc_common_dimm_params.c
deleted file mode 100644
index 56128a7b96..0000000000
--- a/arch/powerpc/cpu/mpc8xxx/ddr/lc_common_dimm_params.c
+++ /dev/null
@@ -1,521 +0,0 @@
-/*
- * Copyright 2008-2012 Freescale Semiconductor, Inc.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * Version 2 as published by the Free Software Foundation.
- */
-
-#include <common.h>
-#include <asm/fsl_ddr_sdram.h>
-
-#include "ddr.h"
-
-#if defined(CONFIG_FSL_DDR3)
-static unsigned int
-compute_cas_latency_ddr3(const dimm_params_t *dimm_params,
-			 common_timing_params_t *outpdimm,
-			 unsigned int number_of_dimms)
-{
-	unsigned int i;
-	unsigned int tAAmin_ps = 0;
-	unsigned int tCKmin_X_ps = 0;
-	unsigned int common_caslat;
-	unsigned int caslat_actual;
-	unsigned int retry = 16;
-	unsigned int tmp;
-	const unsigned int mclk_ps = get_memory_clk_period_ps();
-
-	/* compute the common CAS latency supported between slots */
-	tmp = dimm_params[0].caslat_X;
-	for (i = 1; i < number_of_dimms; i++) {
-		if (dimm_params[i].n_ranks)
-			tmp &= dimm_params[i].caslat_X;
-	}
-	common_caslat = tmp;
-
-	/* compute the max tAAmin tCKmin between slots */
-	for (i = 0; i < number_of_dimms; i++) {
-		tAAmin_ps = max(tAAmin_ps, dimm_params[i].tAA_ps);
-		tCKmin_X_ps = max(tCKmin_X_ps, dimm_params[i].tCKmin_X_ps);
-	}
-	/* validate if the memory clk is in the range of dimms */
-	if (mclk_ps < tCKmin_X_ps) {
-		printf("DDR clock (MCLK cycle %u ps) is faster than "
-			"the slowest DIMM(s) (tCKmin %u ps) can support.\n",
-			mclk_ps, tCKmin_X_ps);
-	}
-	/* determine the acutal cas latency */
-	caslat_actual = (tAAmin_ps + mclk_ps - 1) / mclk_ps;
-	/* check if the dimms support the CAS latency */
-	while (!(common_caslat & (1 << caslat_actual)) && retry > 0) {
-		caslat_actual++;
-		retry--;
-	}
-	/* once the caculation of caslat_actual is completed
-	 * we must verify that this CAS latency value does not
-	 * exceed tAAmax, which is 20 ns for all DDR3 speed grades
-	 */
-	if (caslat_actual * mclk_ps > 20000) {
-		printf("The choosen cas latency %d is too large\n",
-			caslat_actual);
-	}
-	outpdimm->lowest_common_SPD_caslat = caslat_actual;
-
-	return 0;
-}
-#endif
-
-/*
- * compute_lowest_common_dimm_parameters()
- *
- * Determine the worst-case DIMM timing parameters from the set of DIMMs
- * whose parameters have been computed into the array pointed to
- * by dimm_params.
- */
-unsigned int
-compute_lowest_common_dimm_parameters(const dimm_params_t *dimm_params,
-				      common_timing_params_t *outpdimm,
-				      const unsigned int number_of_dimms)
-{
-	unsigned int i, j;
-
-	unsigned int tCKmin_X_ps = 0;
-	unsigned int tCKmax_ps = 0xFFFFFFFF;
-	unsigned int tCKmax_max_ps = 0;
-	unsigned int tRCD_ps = 0;
-	unsigned int tRP_ps = 0;
-	unsigned int tRAS_ps = 0;
-	unsigned int tWR_ps = 0;
-	unsigned int tWTR_ps = 0;
-	unsigned int tRFC_ps = 0;
-	unsigned int tRRD_ps = 0;
-	unsigned int tRC_ps = 0;
-	unsigned int refresh_rate_ps = 0;
-	unsigned int tIS_ps = 0;
-	unsigned int tIH_ps = 0;
-	unsigned int tDS_ps = 0;
-	unsigned int tDH_ps = 0;
-	unsigned int tRTP_ps = 0;
-	unsigned int tDQSQ_max_ps = 0;
-	unsigned int tQHS_ps = 0;
-
-	unsigned int temp1, temp2;
-	unsigned int additive_latency = 0;
-#if !defined(CONFIG_FSL_DDR3)
-	const unsigned int mclk_ps = get_memory_clk_period_ps();
-	unsigned int lowest_good_caslat;
-	unsigned int not_ok;
-
-	debug("using mclk_ps = %u\n", mclk_ps);
-#endif
-
-	temp1 = 0;
-	for (i = 0; i < number_of_dimms; i++) {
-		/*
-		 * If there are no ranks on this DIMM,
-		 * it probably doesn't exist, so skip it.
-		 */
-		if (dimm_params[i].n_ranks == 0) {
-			temp1++;
-			continue;
-		}
-		if (dimm_params[i].n_ranks == 4 && i != 0) {
-			printf("Found Quad-rank DIMM in wrong bank, ignored."
-				" Software may not run as expected.\n");
-			temp1++;
-			continue;
-		}
-
-		/*
-		 * check if quad-rank DIMM is plugged if
-		 * CONFIG_CHIP_SELECT_QUAD_CAPABLE is not defined
-		 * Only the board with proper design is capable
-		 */
-#ifndef CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
-		if (dimm_params[i].n_ranks == 4 && \
-		  CONFIG_CHIP_SELECTS_PER_CTRL/CONFIG_DIMM_SLOTS_PER_CTLR < 4) {
-			printf("Found Quad-rank DIMM, not able to support.");
-			temp1++;
-			continue;
-		}
-#endif
-		/*
-		 * Find minimum tCKmax_ps to find fastest slow speed,
-		 * i.e., this is the slowest the whole system can go.
-		 */
-		tCKmax_ps = min(tCKmax_ps, dimm_params[i].tCKmax_ps);
-
-		/* Either find maximum value to determine slowest
-		 * speed, delay, time, period, etc */
-		tCKmin_X_ps = max(tCKmin_X_ps, dimm_params[i].tCKmin_X_ps);
-		tCKmax_max_ps = max(tCKmax_max_ps, dimm_params[i].tCKmax_ps);
-		tRCD_ps = max(tRCD_ps, dimm_params[i].tRCD_ps);
-		tRP_ps = max(tRP_ps, dimm_params[i].tRP_ps);
-		tRAS_ps = max(tRAS_ps, dimm_params[i].tRAS_ps);
-		tWR_ps = max(tWR_ps, dimm_params[i].tWR_ps);
-		tWTR_ps = max(tWTR_ps, dimm_params[i].tWTR_ps);
-		tRFC_ps = max(tRFC_ps, dimm_params[i].tRFC_ps);
-		tRRD_ps = max(tRRD_ps, dimm_params[i].tRRD_ps);
-		tRC_ps = max(tRC_ps, dimm_params[i].tRC_ps);
-		tIS_ps = max(tIS_ps, dimm_params[i].tIS_ps);
-		tIH_ps = max(tIH_ps, dimm_params[i].tIH_ps);
-		tDS_ps = max(tDS_ps, dimm_params[i].tDS_ps);
-		tDH_ps = max(tDH_ps, dimm_params[i].tDH_ps);
-		tRTP_ps = max(tRTP_ps, dimm_params[i].tRTP_ps);
-		tQHS_ps = max(tQHS_ps, dimm_params[i].tQHS_ps);
-		refresh_rate_ps = max(refresh_rate_ps,
-				      dimm_params[i].refresh_rate_ps);
-
-		/*
-		 * Find maximum tDQSQ_max_ps to find slowest.
-		 *
-		 * FIXME: is finding the slowest value the correct
-		 * strategy for this parameter?
-		 */
-		tDQSQ_max_ps = max(tDQSQ_max_ps, dimm_params[i].tDQSQ_max_ps);
-	}
-
-	outpdimm->ndimms_present = number_of_dimms - temp1;
-
-	if (temp1 == number_of_dimms) {
-		debug("no dimms this memory controller\n");
-		return 0;
-	}
-
-	outpdimm->tCKmin_X_ps = tCKmin_X_ps;
-	outpdimm->tCKmax_ps = tCKmax_ps;
-	outpdimm->tCKmax_max_ps = tCKmax_max_ps;
-	outpdimm->tRCD_ps = tRCD_ps;
-	outpdimm->tRP_ps = tRP_ps;
-	outpdimm->tRAS_ps = tRAS_ps;
-	outpdimm->tWR_ps = tWR_ps;
-	outpdimm->tWTR_ps = tWTR_ps;
-	outpdimm->tRFC_ps = tRFC_ps;
-	outpdimm->tRRD_ps = tRRD_ps;
-	outpdimm->tRC_ps = tRC_ps;
-	outpdimm->refresh_rate_ps = refresh_rate_ps;
-	outpdimm->tIS_ps = tIS_ps;
-	outpdimm->tIH_ps = tIH_ps;
-	outpdimm->tDS_ps = tDS_ps;
-	outpdimm->tDH_ps = tDH_ps;
-	outpdimm->tRTP_ps = tRTP_ps;
-	outpdimm->tDQSQ_max_ps = tDQSQ_max_ps;
-	outpdimm->tQHS_ps = tQHS_ps;
-
-	/* Determine common burst length for all DIMMs. */
-	temp1 = 0xff;
-	for (i = 0; i < number_of_dimms; i++) {
-		if (dimm_params[i].n_ranks) {
-			temp1 &= dimm_params[i].burst_lengths_bitmask;
-		}
-	}
-	outpdimm->all_DIMMs_burst_lengths_bitmask = temp1;
-
-	/* Determine if all DIMMs registered buffered. */
-	temp1 = temp2 = 0;
-	for (i = 0; i < number_of_dimms; i++) {
-		if (dimm_params[i].n_ranks) {
-			if (dimm_params[i].registered_dimm) {
-				temp1 = 1;
-#ifndef CONFIG_SPL_BUILD
-				printf("Detected RDIMM %s\n",
-					dimm_params[i].mpart);
-#endif
-			} else {
-				temp2 = 1;
-#ifndef CONFIG_SPL_BUILD
-				printf("Detected UDIMM %s\n",
-					dimm_params[i].mpart);
-#endif
-			}
-		}
-	}
-
-	outpdimm->all_DIMMs_registered = 0;
-	outpdimm->all_DIMMs_unbuffered = 0;
-	if (temp1 && !temp2) {
-		outpdimm->all_DIMMs_registered = 1;
-	} else if (!temp1 && temp2) {
-		outpdimm->all_DIMMs_unbuffered = 1;
-	} else {
-		printf("ERROR:  Mix of registered buffered and unbuffered "
-				"DIMMs detected!\n");
-	}
-
-	temp1 = 0;
-	if (outpdimm->all_DIMMs_registered)
-		for (j = 0; j < 16; j++) {
-			outpdimm->rcw[j] = dimm_params[0].rcw[j];
-			for (i = 1; i < number_of_dimms; i++) {
-				if (!dimm_params[i].n_ranks)
-					continue;
-				if (dimm_params[i].rcw[j] != dimm_params[0].rcw[j]) {
-					temp1 = 1;
-					break;
-				}
-			}
-		}
-
-	if (temp1 != 0)
-		printf("ERROR: Mix different RDIMM detected!\n");
-
-#if defined(CONFIG_FSL_DDR3)
-	if (compute_cas_latency_ddr3(dimm_params, outpdimm, number_of_dimms))
-		return 1;
-#else
-	/*
-	 * Compute a CAS latency suitable for all DIMMs
-	 *
-	 * Strategy for SPD-defined latencies: compute only
-	 * CAS latency defined by all DIMMs.
-	 */
-
-	/*
-	 * Step 1: find CAS latency common to all DIMMs using bitwise
-	 * operation.
-	 */
-	temp1 = 0xFF;
-	for (i = 0; i < number_of_dimms; i++) {
-		if (dimm_params[i].n_ranks) {
-			temp2 = 0;
-			temp2 |= 1 << dimm_params[i].caslat_X;
-			temp2 |= 1 << dimm_params[i].caslat_X_minus_1;
-			temp2 |= 1 << dimm_params[i].caslat_X_minus_2;
-			/*
-			 * FIXME: If there was no entry for X-2 (X-1) in
-			 * the SPD, then caslat_X_minus_2
-			 * (caslat_X_minus_1) contains either 255 or
-			 * 0xFFFFFFFF because that's what the glorious
-			 * __ilog2 function returns for an input of 0.
-			 * On 32-bit PowerPC, left shift counts with bit
-			 * 26 set (that the value of 255 or 0xFFFFFFFF
-			 * will have), cause the destination register to
-			 * be 0.  That is why this works.
-			 */
-			temp1 &= temp2;
-		}
-	}
-
-	/*
-	 * Step 2: check each common CAS latency against tCK of each
-	 * DIMM's SPD.
-	 */
-	lowest_good_caslat = 0;
-	temp2 = 0;
-	while (temp1) {
-		not_ok = 0;
-		temp2 =  __ilog2(temp1);
-		debug("checking common caslat = %u\n", temp2);
-
-		/* Check if this CAS latency will work on all DIMMs at tCK. */
-		for (i = 0; i < number_of_dimms; i++) {
-			if (!dimm_params[i].n_ranks) {
-				continue;
-			}
-			if (dimm_params[i].caslat_X == temp2) {
-				if (mclk_ps >= dimm_params[i].tCKmin_X_ps) {
-					debug("CL = %u ok on DIMM %u at tCK=%u"
-					    " ps with its tCKmin_X_ps of %u\n",
-					       temp2, i, mclk_ps,
-					       dimm_params[i].tCKmin_X_ps);
-					continue;
-				} else {
-					not_ok++;
-				}
-			}
-
-			if (dimm_params[i].caslat_X_minus_1 == temp2) {
-				unsigned int tCKmin_X_minus_1_ps
-					= dimm_params[i].tCKmin_X_minus_1_ps;
-				if (mclk_ps >= tCKmin_X_minus_1_ps) {
-					debug("CL = %u ok on DIMM %u at "
-						"tCK=%u ps with its "
-						"tCKmin_X_minus_1_ps of %u\n",
-					       temp2, i, mclk_ps,
-					       tCKmin_X_minus_1_ps);
-					continue;
-				} else {
-					not_ok++;
-				}
-			}
-
-			if (dimm_params[i].caslat_X_minus_2 == temp2) {
-				unsigned int tCKmin_X_minus_2_ps
-					= dimm_params[i].tCKmin_X_minus_2_ps;
-				if (mclk_ps >= tCKmin_X_minus_2_ps) {
-					debug("CL = %u ok on DIMM %u at "
-						"tCK=%u ps with its "
-						"tCKmin_X_minus_2_ps of %u\n",
-					       temp2, i, mclk_ps,
-					       tCKmin_X_minus_2_ps);
-					continue;
-				} else {
-					not_ok++;
-				}
-			}
-		}
-
-		if (!not_ok) {
-			lowest_good_caslat = temp2;
-		}
-
-		temp1 &= ~(1 << temp2);
-	}
-
-	debug("lowest common SPD-defined CAS latency = %u\n",
-	       lowest_good_caslat);
-	outpdimm->lowest_common_SPD_caslat = lowest_good_caslat;
-
-
-	/*
-	 * Compute a common 'de-rated' CAS latency.
-	 *
-	 * The strategy here is to find the *highest* dereated cas latency
-	 * with the assumption that all of the DIMMs will support a dereated
-	 * CAS latency higher than or equal to their lowest dereated value.
-	 */
-	temp1 = 0;
-	for (i = 0; i < number_of_dimms; i++) {
-		temp1 = max(temp1, dimm_params[i].caslat_lowest_derated);
-	}
-	outpdimm->highest_common_derated_caslat = temp1;
-	debug("highest common dereated CAS latency = %u\n", temp1);
-#endif /* #if defined(CONFIG_FSL_DDR3) */
-
-	/* Determine if all DIMMs ECC capable. */
-	temp1 = 1;
-	for (i = 0; i < number_of_dimms; i++) {
-		if (dimm_params[i].n_ranks &&
-			!(dimm_params[i].edc_config & EDC_ECC)) {
-			temp1 = 0;
-			break;
-		}
-	}
-	if (temp1) {
-		debug("all DIMMs ECC capable\n");
-	} else {
-		debug("Warning: not all DIMMs ECC capable, cant enable ECC\n");
-	}
-	outpdimm->all_DIMMs_ECC_capable = temp1;
-
-#ifndef CONFIG_FSL_DDR3
-	/* FIXME: move to somewhere else to validate. */
-	if (mclk_ps > tCKmax_max_ps) {
-		printf("Warning: some of the installed DIMMs "
-				"can not operate this slowly.\n");
-		return 1;
-	}
-#endif
-	/*
-	 * Compute additive latency.
-	 *
-	 * For DDR1, additive latency should be 0.
-	 *
-	 * For DDR2, with ODT enabled, use "a value" less than ACTTORW,
-	 *	which comes from Trcd, and also note that:
-	 *	    add_lat + caslat must be >= 4
-	 *
-	 * For DDR3, we use the AL=0
-	 *
-	 * When to use additive latency for DDR2:
-	 *
-	 * I. Because you are using CL=3 and need to do ODT on writes and
-	 *    want functionality.
-	 *    1. Are you going to use ODT? (Does your board not have
-	 *      additional termination circuitry for DQ, DQS, DQS_,
-	 *      DM, RDQS, RDQS_ for x4/x8 configs?)
-	 *    2. If so, is your lowest supported CL going to be 3?
-	 *    3. If so, then you must set AL=1 because
-	 *
-	 *       WL >= 3 for ODT on writes
-	 *       RL = AL + CL
-	 *       WL = RL - 1
-	 *       ->
-	 *       WL = AL + CL - 1
-	 *       AL + CL - 1 >= 3
-	 *       AL + CL >= 4
-	 *  QED
-	 *
-	 *  RL >= 3 for ODT on reads
-	 *  RL = AL + CL
-	 *
-	 *  Since CL aren't usually less than 2, AL=0 is a minimum,
-	 *  so the WL-derived AL should be the  -- FIXME?
-	 *
-	 * II. Because you are using auto-precharge globally and want to
-	 *     use additive latency (posted CAS) to get more bandwidth.
-	 *     1. Are you going to use auto-precharge mode globally?
-	 *
-	 *        Use addtivie latency and compute AL to be 1 cycle less than
-	 *        tRCD, i.e. the READ or WRITE command is in the cycle
-	 *        immediately following the ACTIVATE command..
-	 *
-	 * III. Because you feel like it or want to do some sort of
-	 *      degraded-performance experiment.
-	 *     1.  Do you just want to use additive latency because you feel
-	 *         like it?
-	 *
-	 * Validation:  AL is less than tRCD, and within the other
-	 * read-to-precharge constraints.
-	 */
-
-	additive_latency = 0;
-
-#if defined(CONFIG_FSL_DDR2)
-	if (lowest_good_caslat < 4) {
-		additive_latency = (picos_to_mclk(tRCD_ps) > lowest_good_caslat)
-			? picos_to_mclk(tRCD_ps) - lowest_good_caslat : 0;
-		if (mclk_to_picos(additive_latency) > tRCD_ps) {
-			additive_latency = picos_to_mclk(tRCD_ps);
-			debug("setting additive_latency to %u because it was "
-				" greater than tRCD_ps\n", additive_latency);
-		}
-	}
-
-#elif defined(CONFIG_FSL_DDR3)
-	/*
-	 * The system will not use the global auto-precharge mode.
-	 * However, it uses the page mode, so we set AL=0
-	 */
-	additive_latency = 0;
-#endif
-
-	/*
-	 * Validate additive latency
-	 * FIXME: move to somewhere else to validate
-	 *
-	 * AL <= tRCD(min)
-	 */
-	if (mclk_to_picos(additive_latency) > tRCD_ps) {
-		printf("Error: invalid additive latency exceeds tRCD(min).\n");
-		return 1;
-	}
-
-	/*
-	 * RL = CL + AL;  RL >= 3 for ODT_RD_CFG to be enabled
-	 * WL = RL - 1;  WL >= 3 for ODT_WL_CFG to be enabled
-	 * ADD_LAT (the register) must be set to a value less
-	 * than ACTTORW if WL = 1, then AL must be set to 1
-	 * RD_TO_PRE (the register) must be set to a minimum
-	 * tRTP + AL if AL is nonzero
-	 */
-
-	/*
-	 * Additive latency will be applied only if the memctl option to
-	 * use it.
-	 */
-	outpdimm->additive_latency = additive_latency;
-
-	debug("tCKmin_ps = %u\n", outpdimm->tCKmin_X_ps);
-	debug("tRCD_ps   = %u\n", outpdimm->tRCD_ps);
-	debug("tRP_ps    = %u\n", outpdimm->tRP_ps);
-	debug("tRAS_ps   = %u\n", outpdimm->tRAS_ps);
-	debug("tWR_ps    = %u\n", outpdimm->tWR_ps);
-	debug("tWTR_ps   = %u\n", outpdimm->tWTR_ps);
-	debug("tRFC_ps   = %u\n", outpdimm->tRFC_ps);
-	debug("tRRD_ps   = %u\n", outpdimm->tRRD_ps);
-	debug("tRC_ps    = %u\n", outpdimm->tRC_ps);
-
-	return 0;
-}
diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/main.c b/arch/powerpc/cpu/mpc8xxx/ddr/main.c
deleted file mode 100644
index 842bf1989e..0000000000
--- a/arch/powerpc/cpu/mpc8xxx/ddr/main.c
+++ /dev/null
@@ -1,714 +0,0 @@
-/*
- * Copyright 2008-2012 Freescale Semiconductor, Inc.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * Version 2 as published by the Free Software Foundation.
- */
-
-/*
- * Generic driver for Freescale DDR/DDR2/DDR3 memory controller.
- * Based on code from spd_sdram.c
- * Author: James Yang [at freescale.com]
- */
-
-#include <common.h>
-#include <i2c.h>
-#include <asm/fsl_ddr_sdram.h>
-#include <asm/fsl_law.h>
-
-#include "ddr.h"
-
-void fsl_ddr_set_lawbar(
-		const common_timing_params_t *memctl_common_params,
-		unsigned int memctl_interleaved,
-		unsigned int ctrl_num);
-void fsl_ddr_set_intl3r(const unsigned int granule_size);
-
-#if defined(SPD_EEPROM_ADDRESS) || \
-    defined(SPD_EEPROM_ADDRESS1) || defined(SPD_EEPROM_ADDRESS2) || \
-    defined(SPD_EEPROM_ADDRESS3) || defined(SPD_EEPROM_ADDRESS4)
-#if (CONFIG_NUM_DDR_CONTROLLERS == 1) && (CONFIG_DIMM_SLOTS_PER_CTLR == 1)
-u8 spd_i2c_addr[CONFIG_NUM_DDR_CONTROLLERS][CONFIG_DIMM_SLOTS_PER_CTLR] = {
-	[0][0] = SPD_EEPROM_ADDRESS,
-};
-#elif (CONFIG_NUM_DDR_CONTROLLERS == 1) && (CONFIG_DIMM_SLOTS_PER_CTLR == 2)
-u8 spd_i2c_addr[CONFIG_NUM_DDR_CONTROLLERS][CONFIG_DIMM_SLOTS_PER_CTLR] = {
-	[0][0] = SPD_EEPROM_ADDRESS1,	/* controller 1 */
-	[0][1] = SPD_EEPROM_ADDRESS2,	/* controller 1 */
-};
-#elif (CONFIG_NUM_DDR_CONTROLLERS == 2) && (CONFIG_DIMM_SLOTS_PER_CTLR == 1)
-u8 spd_i2c_addr[CONFIG_NUM_DDR_CONTROLLERS][CONFIG_DIMM_SLOTS_PER_CTLR] = {
-	[0][0] = SPD_EEPROM_ADDRESS1,	/* controller 1 */
-	[1][0] = SPD_EEPROM_ADDRESS2,	/* controller 2 */
-};
-#elif (CONFIG_NUM_DDR_CONTROLLERS == 2) && (CONFIG_DIMM_SLOTS_PER_CTLR == 2)
-u8 spd_i2c_addr[CONFIG_NUM_DDR_CONTROLLERS][CONFIG_DIMM_SLOTS_PER_CTLR] = {
-	[0][0] = SPD_EEPROM_ADDRESS1,	/* controller 1 */
-	[0][1] = SPD_EEPROM_ADDRESS2,	/* controller 1 */
-	[1][0] = SPD_EEPROM_ADDRESS3,	/* controller 2 */
-	[1][1] = SPD_EEPROM_ADDRESS4,	/* controller 2 */
-};
-#elif (CONFIG_NUM_DDR_CONTROLLERS == 3) && (CONFIG_DIMM_SLOTS_PER_CTLR == 1)
-u8 spd_i2c_addr[CONFIG_NUM_DDR_CONTROLLERS][CONFIG_DIMM_SLOTS_PER_CTLR] = {
-	[0][0] = SPD_EEPROM_ADDRESS1,	/* controller 1 */
-	[1][0] = SPD_EEPROM_ADDRESS2,	/* controller 2 */
-	[2][0] = SPD_EEPROM_ADDRESS3,	/* controller 3 */
-};
-#elif (CONFIG_NUM_DDR_CONTROLLERS == 3) && (CONFIG_DIMM_SLOTS_PER_CTLR == 2)
-u8 spd_i2c_addr[CONFIG_NUM_DDR_CONTROLLERS][CONFIG_DIMM_SLOTS_PER_CTLR] = {
-	[0][0] = SPD_EEPROM_ADDRESS1,	/* controller 1 */
-	[0][1] = SPD_EEPROM_ADDRESS2,	/* controller 1 */
-	[1][0] = SPD_EEPROM_ADDRESS3,	/* controller 2 */
-	[1][1] = SPD_EEPROM_ADDRESS4,	/* controller 2 */
-	[2][0] = SPD_EEPROM_ADDRESS5,	/* controller 3 */
-	[2][1] = SPD_EEPROM_ADDRESS6,	/* controller 3 */
-};
-
-#endif
-
-static void __get_spd(generic_spd_eeprom_t *spd, u8 i2c_address)
-{
-	int ret = i2c_read(i2c_address, 0, 1, (uchar *)spd,
-				sizeof(generic_spd_eeprom_t));
-
-	if (ret) {
-		if (i2c_address ==
-#ifdef SPD_EEPROM_ADDRESS
-				SPD_EEPROM_ADDRESS
-#elif defined(SPD_EEPROM_ADDRESS1)
-				SPD_EEPROM_ADDRESS1
-#endif
-				) {
-			printf("DDR: failed to read SPD from address %u\n",
-				i2c_address);
-		} else {
-			debug("DDR: failed to read SPD from address %u\n",
-				i2c_address);
-		}
-		memset(spd, 0, sizeof(generic_spd_eeprom_t));
-	}
-}
-
-__attribute__((weak, alias("__get_spd")))
-void get_spd(generic_spd_eeprom_t *spd, u8 i2c_address);
-
-void fsl_ddr_get_spd(generic_spd_eeprom_t *ctrl_dimms_spd,
-		      unsigned int ctrl_num)
-{
-	unsigned int i;
-	unsigned int i2c_address = 0;
-
-	if (ctrl_num >= CONFIG_NUM_DDR_CONTROLLERS) {
-		printf("%s unexpected ctrl_num = %u\n", __FUNCTION__, ctrl_num);
-		return;
-	}
-
-	for (i = 0; i < CONFIG_DIMM_SLOTS_PER_CTLR; i++) {
-		i2c_address = spd_i2c_addr[ctrl_num][i];
-		get_spd(&(ctrl_dimms_spd[i]), i2c_address);
-	}
-}
-#else
-void fsl_ddr_get_spd(generic_spd_eeprom_t *ctrl_dimms_spd,
-		      unsigned int ctrl_num)
-{
-}
-#endif /* SPD_EEPROM_ADDRESSx */
-
-/*
- * ASSUMPTIONS:
- *    - Same number of CONFIG_DIMM_SLOTS_PER_CTLR on each controller
- *    - Same memory data bus width on all controllers
- *
- * NOTES:
- *
- * The memory controller and associated documentation use confusing
- * terminology when referring to the orgranization of DRAM.
- *
- * Here is a terminology translation table:
- *
- * memory controller/documention  |industry   |this code  |signals
- * -------------------------------|-----------|-----------|-----------------
- * physical bank/bank		  |rank       |rank	  |chip select (CS)
- * logical bank/sub-bank	  |bank       |bank	  |bank address (BA)
- * page/row			  |row	      |page	  |row address
- * ???				  |column     |column	  |column address
- *
- * The naming confusion is further exacerbated by the descriptions of the
- * memory controller interleaving feature, where accesses are interleaved
- * _BETWEEN_ two seperate memory controllers.  This is configured only in
- * CS0_CONFIG[INTLV_CTL] of each memory controller.
- *
- * memory controller documentation | number of chip selects
- *				   | per memory controller supported
- * --------------------------------|-----------------------------------------
- * cache line interleaving	   | 1 (CS0 only)
- * page interleaving		   | 1 (CS0 only)
- * bank interleaving		   | 1 (CS0 only)
- * superbank interleraving	   | depends on bank (chip select)
- *				   |   interleraving [rank interleaving]
- *				   |   mode used on every memory controller
- *
- * Even further confusing is the existence of the interleaving feature
- * _WITHIN_ each memory controller.  The feature is referred to in
- * documentation as chip select interleaving or bank interleaving,
- * although it is configured in the DDR_SDRAM_CFG field.
- *
- * Name of field		| documentation name	| this code
- * -----------------------------|-----------------------|------------------
- * DDR_SDRAM_CFG[BA_INTLV_CTL]	| Bank (chip select)	| rank interleaving
- *				|  interleaving
- */
-
-const char *step_string_tbl[] = {
-	"STEP_GET_SPD",
-	"STEP_COMPUTE_DIMM_PARMS",
-	"STEP_COMPUTE_COMMON_PARMS",
-	"STEP_GATHER_OPTS",
-	"STEP_ASSIGN_ADDRESSES",
-	"STEP_COMPUTE_REGS",
-	"STEP_PROGRAM_REGS",
-	"STEP_ALL"
-};
-
-const char * step_to_string(unsigned int step) {
-
-	unsigned int s = __ilog2(step);
-
-	if ((1 << s) != step)
-		return step_string_tbl[7];
-
-	return step_string_tbl[s];
-}
-
-static unsigned long long __step_assign_addresses(fsl_ddr_info_t *pinfo,
-			  unsigned int dbw_cap_adj[])
-{
-	int i, j;
-	unsigned long long total_mem, current_mem_base, total_ctlr_mem;
-	unsigned long long rank_density, ctlr_density = 0;
-
-	/*
-	 * If a reduced data width is requested, but the SPD
-	 * specifies a physically wider device, adjust the
-	 * computed dimm capacities accordingly before
-	 * assigning addresses.
-	 */
-	for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
-		unsigned int found = 0;
-
-		switch (pinfo->memctl_opts[i].data_bus_width) {
-		case 2:
-			/* 16-bit */
-			for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
-				unsigned int dw;
-				if (!pinfo->dimm_params[i][j].n_ranks)
-					continue;
-				dw = pinfo->dimm_params[i][j].primary_sdram_width;
-				if ((dw == 72 || dw == 64)) {
-					dbw_cap_adj[i] = 2;
-					break;
-				} else if ((dw == 40 || dw == 32)) {
-					dbw_cap_adj[i] = 1;
-					break;
-				}
-			}
-			break;
-
-		case 1:
-			/* 32-bit */
-			for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
-				unsigned int dw;
-				dw = pinfo->dimm_params[i][j].data_width;
-				if (pinfo->dimm_params[i][j].n_ranks
-				    && (dw == 72 || dw == 64)) {
-					/*
-					 * FIXME: can't really do it
-					 * like this because this just
-					 * further reduces the memory
-					 */
-					found = 1;
-					break;
-				}
-			}
-			if (found) {
-				dbw_cap_adj[i] = 1;
-			}
-			break;
-
-		case 0:
-			/* 64-bit */
-			break;
-
-		default:
-			printf("unexpected data bus width "
-				"specified controller %u\n", i);
-			return 1;
-		}
-		debug("dbw_cap_adj[%d]=%d\n", i, dbw_cap_adj[i]);
-	}
-
-	current_mem_base = 0ull;
-	total_mem = 0;
-	if (pinfo->memctl_opts[0].memctl_interleaving) {
-		rank_density = pinfo->dimm_params[0][0].rank_density >>
-					dbw_cap_adj[0];
-		switch (pinfo->memctl_opts[0].ba_intlv_ctl &
-					FSL_DDR_CS0_CS1_CS2_CS3) {
-		case FSL_DDR_CS0_CS1_CS2_CS3:
-			ctlr_density = 4 * rank_density;
-			break;
-		case FSL_DDR_CS0_CS1:
-		case FSL_DDR_CS0_CS1_AND_CS2_CS3:
-			ctlr_density = 2 * rank_density;
-			break;
-		case FSL_DDR_CS2_CS3:
-		default:
-			ctlr_density = rank_density;
-			break;
-		}
-		debug("rank density is 0x%llx, ctlr density is 0x%llx\n",
-			rank_density, ctlr_density);
-		for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
-			if (pinfo->memctl_opts[i].memctl_interleaving) {
-				switch (pinfo->memctl_opts[i].memctl_interleaving_mode) {
-				case FSL_DDR_CACHE_LINE_INTERLEAVING:
-				case FSL_DDR_PAGE_INTERLEAVING:
-				case FSL_DDR_BANK_INTERLEAVING:
-				case FSL_DDR_SUPERBANK_INTERLEAVING:
-					total_ctlr_mem = 2 * ctlr_density;
-					break;
-				case FSL_DDR_3WAY_1KB_INTERLEAVING:
-				case FSL_DDR_3WAY_4KB_INTERLEAVING:
-				case FSL_DDR_3WAY_8KB_INTERLEAVING:
-					total_ctlr_mem = 3 * ctlr_density;
-					break;
-				case FSL_DDR_4WAY_1KB_INTERLEAVING:
-				case FSL_DDR_4WAY_4KB_INTERLEAVING:
-				case FSL_DDR_4WAY_8KB_INTERLEAVING:
-					total_ctlr_mem = 4 * ctlr_density;
-					break;
-				default:
-					panic("Unknown interleaving mode");
-				}
-				pinfo->common_timing_params[i].base_address =
-							current_mem_base;
-				pinfo->common_timing_params[i].total_mem =
-							total_ctlr_mem;
-				total_mem = current_mem_base + total_ctlr_mem;
-				debug("ctrl %d base 0x%llx\n", i, current_mem_base);
-				debug("ctrl %d total 0x%llx\n", i, total_ctlr_mem);
-			} else {
-				/* when 3rd controller not interleaved */
-				current_mem_base = total_mem;
-				total_ctlr_mem = 0;
-				pinfo->common_timing_params[i].base_address =
-							current_mem_base;
-				for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
-					unsigned long long cap =
-						pinfo->dimm_params[i][j].capacity >> dbw_cap_adj[i];
-					pinfo->dimm_params[i][j].base_address =
-						current_mem_base;
-					debug("ctrl %d dimm %d base 0x%llx\n", i, j, current_mem_base);
-					current_mem_base += cap;
-					total_ctlr_mem += cap;
-				}
-				debug("ctrl %d total 0x%llx\n", i, total_ctlr_mem);
-				pinfo->common_timing_params[i].total_mem =
-							total_ctlr_mem;
-				total_mem += total_ctlr_mem;
-			}
-		}
-	} else {
-		/*
-		 * Simple linear assignment if memory
-		 * controllers are not interleaved.
-		 */
-		for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
-			total_ctlr_mem = 0;
-			pinfo->common_timing_params[i].base_address =
-						current_mem_base;
-			for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
-				/* Compute DIMM base addresses. */
-				unsigned long long cap =
-					pinfo->dimm_params[i][j].capacity >> dbw_cap_adj[i];
-				pinfo->dimm_params[i][j].base_address =
-					current_mem_base;
-				debug("ctrl %d dimm %d base 0x%llx\n", i, j, current_mem_base);
-				current_mem_base += cap;
-				total_ctlr_mem += cap;
-			}
-			debug("ctrl %d total 0x%llx\n", i, total_ctlr_mem);
-			pinfo->common_timing_params[i].total_mem =
-							total_ctlr_mem;
-			total_mem += total_ctlr_mem;
-		}
-	}
-	debug("Total mem by %s is 0x%llx\n", __func__, total_mem);
-
-	return total_mem;
-}
-
-/* Use weak function to allow board file to override the address assignment */
-__attribute__((weak, alias("__step_assign_addresses")))
-unsigned long long step_assign_addresses(fsl_ddr_info_t *pinfo,
-			  unsigned int dbw_cap_adj[]);
-
-unsigned long long
-fsl_ddr_compute(fsl_ddr_info_t *pinfo, unsigned int start_step,
-				       unsigned int size_only)
-{
-	unsigned int i, j;
-	unsigned long long total_mem = 0;
-	int assert_reset;
-
-	fsl_ddr_cfg_regs_t *ddr_reg = pinfo->fsl_ddr_config_reg;
-	common_timing_params_t *timing_params = pinfo->common_timing_params;
-	assert_reset = board_need_mem_reset();
-
-	/* data bus width capacity adjust shift amount */
-	unsigned int dbw_capacity_adjust[CONFIG_NUM_DDR_CONTROLLERS];
-
-	for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
-		dbw_capacity_adjust[i] = 0;
-	}
-
-	debug("starting at step %u (%s)\n",
-	      start_step, step_to_string(start_step));
-
-	switch (start_step) {
-	case STEP_GET_SPD:
-#if defined(CONFIG_DDR_SPD) || defined(CONFIG_SPD_EEPROM)
-		/* STEP 1:  Gather all DIMM SPD data */
-		for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
-			fsl_ddr_get_spd(pinfo->spd_installed_dimms[i], i);
-		}
-
-	case STEP_COMPUTE_DIMM_PARMS:
-		/* STEP 2:  Compute DIMM parameters from SPD data */
-
-		for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
-			for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
-				unsigned int retval;
-				generic_spd_eeprom_t *spd =
-					&(pinfo->spd_installed_dimms[i][j]);
-				dimm_params_t *pdimm =
-					&(pinfo->dimm_params[i][j]);
-
-				retval = compute_dimm_parameters(spd, pdimm, i);
-#ifdef CONFIG_SYS_DDR_RAW_TIMING
-				if (!i && !j && retval) {
-					printf("SPD error on controller %d! "
-					"Trying fallback to raw timing "
-					"calculation\n", i);
-					fsl_ddr_get_dimm_params(pdimm, i, j);
-				}
-#else
-				if (retval == 2) {
-					printf("Error: compute_dimm_parameters"
-					" non-zero returned FATAL value "
-					"for memctl=%u dimm=%u\n", i, j);
-					return 0;
-				}
-#endif
-				if (retval) {
-					debug("Warning: compute_dimm_parameters"
-					" non-zero return value for memctl=%u "
-					"dimm=%u\n", i, j);
-				}
-			}
-		}
-
-#elif defined(CONFIG_SYS_DDR_RAW_TIMING)
-	case STEP_COMPUTE_DIMM_PARMS:
-		for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
-			for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
-				dimm_params_t *pdimm =
-					&(pinfo->dimm_params[i][j]);
-				fsl_ddr_get_dimm_params(pdimm, i, j);
-			}
-		}
-		debug("Filling dimm parameters from board specific file\n");
-#endif
-	case STEP_COMPUTE_COMMON_PARMS:
-		/*
-		 * STEP 3: Compute a common set of timing parameters
-		 * suitable for all of the DIMMs on each memory controller
-		 */
-		for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
-			debug("Computing lowest common DIMM"
-				" parameters for memctl=%u\n", i);
-			compute_lowest_common_dimm_parameters(
-				pinfo->dimm_params[i],
-				&timing_params[i],
-				CONFIG_DIMM_SLOTS_PER_CTLR);
-		}
-
-	case STEP_GATHER_OPTS:
-		/* STEP 4:  Gather configuration requirements from user */
-		for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
-			debug("Reloading memory controller "
-				"configuration options for memctl=%u\n", i);
-			/*
-			 * This "reloads" the memory controller options
-			 * to defaults.  If the user "edits" an option,
-			 * next_step points to the step after this,
-			 * which is currently STEP_ASSIGN_ADDRESSES.
-			 */
-			populate_memctl_options(
-					timing_params[i].all_DIMMs_registered,
-					&pinfo->memctl_opts[i],
-					pinfo->dimm_params[i], i);
-			/*
-			 * For RDIMMs, JEDEC spec requires clocks to be stable
-			 * before reset signal is deasserted. For the boards
-			 * using fixed parameters, this function should be
-			 * be called from board init file.
-			 */
-			if (timing_params[i].all_DIMMs_registered)
-				assert_reset = 1;
-		}
-		if (assert_reset) {
-			debug("Asserting mem reset\n");
-			board_assert_mem_reset();
-		}
-
-	case STEP_ASSIGN_ADDRESSES:
-		/* STEP 5:  Assign addresses to chip selects */
-		check_interleaving_options(pinfo);
-		total_mem = step_assign_addresses(pinfo, dbw_capacity_adjust);
-
-	case STEP_COMPUTE_REGS:
-		/* STEP 6:  compute controller register values */
-		debug("FSL Memory ctrl register computation\n");
-		for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
-			if (timing_params[i].ndimms_present == 0) {
-				memset(&ddr_reg[i], 0,
-					sizeof(fsl_ddr_cfg_regs_t));
-				continue;
-			}
-
-			compute_fsl_memctl_config_regs(
-					&pinfo->memctl_opts[i],
-					&ddr_reg[i], &timing_params[i],
-					pinfo->dimm_params[i],
-					dbw_capacity_adjust[i],
-					size_only);
-		}
-
-	default:
-		break;
-	}
-
-	{
-		/*
-		 * Compute the amount of memory available just by
-		 * looking for the highest valid CSn_BNDS value.
-		 * This allows us to also experiment with using
-		 * only CS0 when using dual-rank DIMMs.
-		 */
-		unsigned int max_end = 0;
-
-		for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
-			for (j = 0; j < CONFIG_CHIP_SELECTS_PER_CTRL; j++) {
-				fsl_ddr_cfg_regs_t *reg = &ddr_reg[i];
-				if (reg->cs[j].config & 0x80000000) {
-					unsigned int end;
-					/*
-					 * 0xfffffff is a special value we put
-					 * for unused bnds
-					 */
-					if (reg->cs[j].bnds == 0xffffffff)
-						continue;
-					end = reg->cs[j].bnds & 0xffff;
-					if (end > max_end) {
-						max_end = end;
-					}
-				}
-			}
-		}
-
-		total_mem = 1 + (((unsigned long long)max_end << 24ULL)
-				    | 0xFFFFFFULL);
-	}
-
-	return total_mem;
-}
-
-/*
- * fsl_ddr_sdram() -- this is the main function to be called by
- *	initdram() in the board file.
- *
- * It returns amount of memory configured in bytes.
- */
-phys_size_t fsl_ddr_sdram(void)
-{
-	unsigned int i;
-	unsigned int law_memctl = LAW_TRGT_IF_DDR_1;
-	unsigned long long total_memory;
-	fsl_ddr_info_t info;
-	int deassert_reset;
-
-	/* Reset info structure. */
-	memset(&info, 0, sizeof(fsl_ddr_info_t));
-
-	/* Compute it once normally. */
-#ifdef CONFIG_FSL_DDR_INTERACTIVE
-	if (tstc() && (getc() == 'd')) {	/* we got a key press of 'd' */
-		total_memory = fsl_ddr_interactive(&info, 0);
-	} else if (fsl_ddr_interactive_env_var_exists()) {
-		total_memory = fsl_ddr_interactive(&info, 1);
-	} else
-#endif
-		total_memory = fsl_ddr_compute(&info, STEP_GET_SPD, 0);
-
-	/* setup 3-way interleaving before enabling DDRC */
-	if (info.memctl_opts[0].memctl_interleaving) {
-		switch (info.memctl_opts[0].memctl_interleaving_mode) {
-		case FSL_DDR_3WAY_1KB_INTERLEAVING:
-		case FSL_DDR_3WAY_4KB_INTERLEAVING:
-		case FSL_DDR_3WAY_8KB_INTERLEAVING:
-			fsl_ddr_set_intl3r(
-				info.memctl_opts[0].memctl_interleaving_mode);
-			break;
-		default:
-			break;
-		}
-	}
-
-	/*
-	 * Program configuration registers.
-	 * JEDEC specs requires clocks to be stable before deasserting reset
-	 * for RDIMMs. Clocks start after chip select is enabled and clock
-	 * control register is set. During step 1, all controllers have their
-	 * registers set but not enabled. Step 2 proceeds after deasserting
-	 * reset through board FPGA or GPIO.
-	 * For non-registered DIMMs, initialization can go through but it is
-	 * also OK to follow the same flow.
-	 */
-	deassert_reset = board_need_mem_reset();
-	for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
-		if (info.common_timing_params[i].all_DIMMs_registered)
-			deassert_reset = 1;
-	}
-	for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
-		debug("Programming controller %u\n", i);
-		if (info.common_timing_params[i].ndimms_present == 0) {
-			debug("No dimms present on controller %u; "
-					"skipping programming\n", i);
-			continue;
-		}
-		/*
-		 * The following call with step = 1 returns before enabling
-		 * the controller. It has to finish with step = 2 later.
-		 */
-		fsl_ddr_set_memctl_regs(&(info.fsl_ddr_config_reg[i]), i,
-					deassert_reset ? 1 : 0);
-	}
-	if (deassert_reset) {
-		/* Use board FPGA or GPIO to deassert reset signal */
-		debug("Deasserting mem reset\n");
-		board_deassert_mem_reset();
-		for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
-			/* Call with step = 2 to continue initialization */
-			fsl_ddr_set_memctl_regs(&(info.fsl_ddr_config_reg[i]),
-						i, 2);
-		}
-	}
-
-	/* program LAWs */
-	for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
-		if (info.memctl_opts[i].memctl_interleaving) {
-			switch (info.memctl_opts[i].memctl_interleaving_mode) {
-			case FSL_DDR_CACHE_LINE_INTERLEAVING:
-			case FSL_DDR_PAGE_INTERLEAVING:
-			case FSL_DDR_BANK_INTERLEAVING:
-			case FSL_DDR_SUPERBANK_INTERLEAVING:
-				if (i == 0) {
-					law_memctl = LAW_TRGT_IF_DDR_INTRLV;
-					fsl_ddr_set_lawbar(&info.common_timing_params[i],
-						law_memctl, i);
-				} else if (i == 2) {
-					law_memctl = LAW_TRGT_IF_DDR_INTLV_34;
-					fsl_ddr_set_lawbar(&info.common_timing_params[i],
-						law_memctl, i);
-				}
-				break;
-			case FSL_DDR_3WAY_1KB_INTERLEAVING:
-			case FSL_DDR_3WAY_4KB_INTERLEAVING:
-			case FSL_DDR_3WAY_8KB_INTERLEAVING:
-				law_memctl = LAW_TRGT_IF_DDR_INTLV_123;
-				if (i == 0) {
-					fsl_ddr_set_lawbar(&info.common_timing_params[i],
-						law_memctl, i);
-				}
-				break;
-			case FSL_DDR_4WAY_1KB_INTERLEAVING:
-			case FSL_DDR_4WAY_4KB_INTERLEAVING:
-			case FSL_DDR_4WAY_8KB_INTERLEAVING:
-				law_memctl = LAW_TRGT_IF_DDR_INTLV_1234;
-				if (i == 0)
-					fsl_ddr_set_lawbar(&info.common_timing_params[i],
-						law_memctl, i);
-				/* place holder for future 4-way interleaving */
-				break;
-			default:
-				break;
-			}
-		} else {
-			switch (i) {
-			case 0:
-				law_memctl = LAW_TRGT_IF_DDR_1;
-				break;
-			case 1:
-				law_memctl = LAW_TRGT_IF_DDR_2;
-				break;
-			case 2:
-				law_memctl = LAW_TRGT_IF_DDR_3;
-				break;
-			case 3:
-				law_memctl = LAW_TRGT_IF_DDR_4;
-				break;
-			default:
-				break;
-			}
-			fsl_ddr_set_lawbar(&info.common_timing_params[i],
-					law_memctl, i);
-		}
-	}
-
-	debug("total_memory by %s = %llu\n", __func__, total_memory);
-
-#if !defined(CONFIG_PHYS_64BIT)
-	/* Check for 4G or more.  Bad. */
-	if (total_memory >= (1ull << 32)) {
-		puts("Detected ");
-		print_size(total_memory, " of memory\n");
-		printf("       This U-Boot only supports < 4G of DDR\n");
-		printf("       You could rebuild it with CONFIG_PHYS_64BIT\n");
-		printf("       "); /* re-align to match init_func_ram print */
-		total_memory = CONFIG_MAX_MEM_MAPPED;
-	}
-#endif
-
-	return total_memory;
-}
-
-/*
- * fsl_ddr_sdram_size() - This function only returns the size of the total
- * memory without setting ddr control registers.
- */
-phys_size_t
-fsl_ddr_sdram_size(void)
-{
-	fsl_ddr_info_t  info;
-	unsigned long long total_memory = 0;
-
-	memset(&info, 0 , sizeof(fsl_ddr_info_t));
-
-	/* Compute it once normally. */
-	total_memory = fsl_ddr_compute(&info, STEP_GET_SPD, 1);
-
-	return total_memory;
-}
diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/options.c b/arch/powerpc/cpu/mpc8xxx/ddr/options.c
deleted file mode 100644
index 30cdca497e..0000000000
--- a/arch/powerpc/cpu/mpc8xxx/ddr/options.c
+++ /dev/null
@@ -1,1147 +0,0 @@
-/*
- * Copyright 2008, 2010-2012 Freescale Semiconductor, Inc.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <hwconfig.h>
-#include <asm/fsl_ddr_sdram.h>
-
-#include "ddr.h"
-
-/*
- * Use our own stack based buffer before relocation to allow accessing longer
- * hwconfig strings that might be in the environment before we've relocated.
- * This is pretty fragile on both the use of stack and if the buffer is big
- * enough. However we will get a warning from getenv_f for the later.
- */
-
-/* Board-specific functions defined in each board's ddr.c */
-extern void fsl_ddr_board_options(memctl_options_t *popts,
-		dimm_params_t *pdimm,
-		unsigned int ctrl_num);
-
-struct dynamic_odt {
-	unsigned int odt_rd_cfg;
-	unsigned int odt_wr_cfg;
-	unsigned int odt_rtt_norm;
-	unsigned int odt_rtt_wr;
-};
-
-#ifdef CONFIG_FSL_DDR3
-static const struct dynamic_odt single_Q[4] = {
-	{	/* cs0 */
-		FSL_DDR_ODT_NEVER,
-		FSL_DDR_ODT_CS_AND_OTHER_DIMM,
-		DDR3_RTT_20_OHM,
-		DDR3_RTT_120_OHM
-	},
-	{	/* cs1 */
-		FSL_DDR_ODT_NEVER,
-		FSL_DDR_ODT_NEVER,	/* tied high */
-		DDR3_RTT_OFF,
-		DDR3_RTT_120_OHM
-	},
-	{	/* cs2 */
-		FSL_DDR_ODT_NEVER,
-		FSL_DDR_ODT_CS_AND_OTHER_DIMM,
-		DDR3_RTT_20_OHM,
-		DDR3_RTT_120_OHM
-	},
-	{	/* cs3 */
-		FSL_DDR_ODT_NEVER,
-		FSL_DDR_ODT_NEVER,	/* tied high */
-		DDR3_RTT_OFF,
-		DDR3_RTT_120_OHM
-	}
-};
-
-static const struct dynamic_odt single_D[4] = {
-	{	/* cs0 */
-		FSL_DDR_ODT_NEVER,
-		FSL_DDR_ODT_ALL,
-		DDR3_RTT_40_OHM,
-		DDR3_RTT_OFF
-	},
-	{	/* cs1 */
-		FSL_DDR_ODT_NEVER,
-		FSL_DDR_ODT_NEVER,
-		DDR3_RTT_OFF,
-		DDR3_RTT_OFF
-	},
-	{0, 0, 0, 0},
-	{0, 0, 0, 0}
-};
-
-static const struct dynamic_odt single_S[4] = {
-	{	/* cs0 */
-		FSL_DDR_ODT_NEVER,
-		FSL_DDR_ODT_ALL,
-		DDR3_RTT_40_OHM,
-		DDR3_RTT_OFF
-	},
-	{0, 0, 0, 0},
-	{0, 0, 0, 0},
-	{0, 0, 0, 0},
-};
-
-static const struct dynamic_odt dual_DD[4] = {
-	{	/* cs0 */
-		FSL_DDR_ODT_NEVER,
-		FSL_DDR_ODT_SAME_DIMM,
-		DDR3_RTT_120_OHM,
-		DDR3_RTT_OFF
-	},
-	{	/* cs1 */
-		FSL_DDR_ODT_OTHER_DIMM,
-		FSL_DDR_ODT_OTHER_DIMM,
-		DDR3_RTT_30_OHM,
-		DDR3_RTT_OFF
-	},
-	{	/* cs2 */
-		FSL_DDR_ODT_NEVER,
-		FSL_DDR_ODT_SAME_DIMM,
-		DDR3_RTT_120_OHM,
-		DDR3_RTT_OFF
-	},
-	{	/* cs3 */
-		FSL_DDR_ODT_OTHER_DIMM,
-		FSL_DDR_ODT_OTHER_DIMM,
-		DDR3_RTT_30_OHM,
-		DDR3_RTT_OFF
-	}
-};
-
-static const struct dynamic_odt dual_DS[4] = {
-	{	/* cs0 */
-		FSL_DDR_ODT_NEVER,
-		FSL_DDR_ODT_SAME_DIMM,
-		DDR3_RTT_120_OHM,
-		DDR3_RTT_OFF
-	},
-	{	/* cs1 */
-		FSL_DDR_ODT_OTHER_DIMM,
-		FSL_DDR_ODT_OTHER_DIMM,
-		DDR3_RTT_30_OHM,
-		DDR3_RTT_OFF
-	},
-	{	/* cs2 */
-		FSL_DDR_ODT_OTHER_DIMM,
-		FSL_DDR_ODT_ALL,
-		DDR3_RTT_20_OHM,
-		DDR3_RTT_120_OHM
-	},
-	{0, 0, 0, 0}
-};
-static const struct dynamic_odt dual_SD[4] = {
-	{	/* cs0 */
-		FSL_DDR_ODT_OTHER_DIMM,
-		FSL_DDR_ODT_ALL,
-		DDR3_RTT_20_OHM,
-		DDR3_RTT_120_OHM
-	},
-	{0, 0, 0, 0},
-	{	/* cs2 */
-		FSL_DDR_ODT_NEVER,
-		FSL_DDR_ODT_SAME_DIMM,
-		DDR3_RTT_120_OHM,
-		DDR3_RTT_OFF
-	},
-	{	/* cs3 */
-		FSL_DDR_ODT_OTHER_DIMM,
-		FSL_DDR_ODT_OTHER_DIMM,
-		DDR3_RTT_20_OHM,
-		DDR3_RTT_OFF
-	}
-};
-
-static const struct dynamic_odt dual_SS[4] = {
-	{	/* cs0 */
-		FSL_DDR_ODT_OTHER_DIMM,
-		FSL_DDR_ODT_ALL,
-		DDR3_RTT_30_OHM,
-		DDR3_RTT_120_OHM
-	},
-	{0, 0, 0, 0},
-	{	/* cs2 */
-		FSL_DDR_ODT_OTHER_DIMM,
-		FSL_DDR_ODT_ALL,
-		DDR3_RTT_30_OHM,
-		DDR3_RTT_120_OHM
-	},
-	{0, 0, 0, 0}
-};
-
-static const struct dynamic_odt dual_D0[4] = {
-	{	/* cs0 */
-		FSL_DDR_ODT_NEVER,
-		FSL_DDR_ODT_SAME_DIMM,
-		DDR3_RTT_40_OHM,
-		DDR3_RTT_OFF
-	},
-	{	/* cs1 */
-		FSL_DDR_ODT_NEVER,
-		FSL_DDR_ODT_NEVER,
-		DDR3_RTT_OFF,
-		DDR3_RTT_OFF
-	},
-	{0, 0, 0, 0},
-	{0, 0, 0, 0}
-};
-
-static const struct dynamic_odt dual_0D[4] = {
-	{0, 0, 0, 0},
-	{0, 0, 0, 0},
-	{	/* cs2 */
-		FSL_DDR_ODT_NEVER,
-		FSL_DDR_ODT_SAME_DIMM,
-		DDR3_RTT_40_OHM,
-		DDR3_RTT_OFF
-	},
-	{	/* cs3 */
-		FSL_DDR_ODT_NEVER,
-		FSL_DDR_ODT_NEVER,
-		DDR3_RTT_OFF,
-		DDR3_RTT_OFF
-	}
-};
-
-static const struct dynamic_odt dual_S0[4] = {
-	{	/* cs0 */
-		FSL_DDR_ODT_NEVER,
-		FSL_DDR_ODT_CS,
-		DDR3_RTT_40_OHM,
-		DDR3_RTT_OFF
-	},
-	{0, 0, 0, 0},
-	{0, 0, 0, 0},
-	{0, 0, 0, 0}
-
-};
-
-static const struct dynamic_odt dual_0S[4] = {
-	{0, 0, 0, 0},
-	{0, 0, 0, 0},
-	{	/* cs2 */
-		FSL_DDR_ODT_NEVER,
-		FSL_DDR_ODT_CS,
-		DDR3_RTT_40_OHM,
-		DDR3_RTT_OFF
-	},
-	{0, 0, 0, 0}
-
-};
-
-static const struct dynamic_odt odt_unknown[4] = {
-	{	/* cs0 */
-		FSL_DDR_ODT_NEVER,
-		FSL_DDR_ODT_CS,
-		DDR3_RTT_120_OHM,
-		DDR3_RTT_OFF
-	},
-	{	/* cs1 */
-		FSL_DDR_ODT_NEVER,
-		FSL_DDR_ODT_CS,
-		DDR3_RTT_120_OHM,
-		DDR3_RTT_OFF
-	},
-	{	/* cs2 */
-		FSL_DDR_ODT_NEVER,
-		FSL_DDR_ODT_CS,
-		DDR3_RTT_120_OHM,
-		DDR3_RTT_OFF
-	},
-	{	/* cs3 */
-		FSL_DDR_ODT_NEVER,
-		FSL_DDR_ODT_CS,
-		DDR3_RTT_120_OHM,
-		DDR3_RTT_OFF
-	}
-};
-#else	/* CONFIG_FSL_DDR3 */
-static const struct dynamic_odt single_Q[4] = {
-	{0, 0, 0, 0},
-	{0, 0, 0, 0},
-	{0, 0, 0, 0},
-	{0, 0, 0, 0}
-};
-
-static const struct dynamic_odt single_D[4] = {
-	{	/* cs0 */
-		FSL_DDR_ODT_NEVER,
-		FSL_DDR_ODT_ALL,
-		DDR2_RTT_150_OHM,
-		DDR2_RTT_OFF
-	},
-	{	/* cs1 */
-		FSL_DDR_ODT_NEVER,
-		FSL_DDR_ODT_NEVER,
-		DDR2_RTT_OFF,
-		DDR2_RTT_OFF
-	},
-	{0, 0, 0, 0},
-	{0, 0, 0, 0}
-};
-
-static const struct dynamic_odt single_S[4] = {
-	{	/* cs0 */
-		FSL_DDR_ODT_NEVER,
-		FSL_DDR_ODT_ALL,
-		DDR2_RTT_150_OHM,
-		DDR2_RTT_OFF
-	},
-	{0, 0, 0, 0},
-	{0, 0, 0, 0},
-	{0, 0, 0, 0},
-};
-
-static const struct dynamic_odt dual_DD[4] = {
-	{	/* cs0 */
-		FSL_DDR_ODT_OTHER_DIMM,
-		FSL_DDR_ODT_OTHER_DIMM,
-		DDR2_RTT_75_OHM,
-		DDR2_RTT_OFF
-	},
-	{	/* cs1 */
-		FSL_DDR_ODT_NEVER,
-		FSL_DDR_ODT_NEVER,
-		DDR2_RTT_OFF,
-		DDR2_RTT_OFF
-	},
-	{	/* cs2 */
-		FSL_DDR_ODT_OTHER_DIMM,
-		FSL_DDR_ODT_OTHER_DIMM,
-		DDR2_RTT_75_OHM,
-		DDR2_RTT_OFF
-	},
-	{	/* cs3 */
-		FSL_DDR_ODT_NEVER,
-		FSL_DDR_ODT_NEVER,
-		DDR2_RTT_OFF,
-		DDR2_RTT_OFF
-	}
-};
-
-static const struct dynamic_odt dual_DS[4] = {
-	{	/* cs0 */
-		FSL_DDR_ODT_OTHER_DIMM,
-		FSL_DDR_ODT_OTHER_DIMM,
-		DDR2_RTT_75_OHM,
-		DDR2_RTT_OFF
-	},
-	{	/* cs1 */
-		FSL_DDR_ODT_NEVER,
-		FSL_DDR_ODT_NEVER,
-		DDR2_RTT_OFF,
-		DDR2_RTT_OFF
-	},
-	{	/* cs2 */
-		FSL_DDR_ODT_OTHER_DIMM,
-		FSL_DDR_ODT_OTHER_DIMM,
-		DDR2_RTT_75_OHM,
-		DDR2_RTT_OFF
-	},
-	{0, 0, 0, 0}
-};
-
-static const struct dynamic_odt dual_SD[4] = {
-	{	/* cs0 */
-		FSL_DDR_ODT_OTHER_DIMM,
-		FSL_DDR_ODT_OTHER_DIMM,
-		DDR2_RTT_75_OHM,
-		DDR2_RTT_OFF
-	},
-	{0, 0, 0, 0},
-	{	/* cs2 */
-		FSL_DDR_ODT_OTHER_DIMM,
-		FSL_DDR_ODT_OTHER_DIMM,
-		DDR2_RTT_75_OHM,
-		DDR2_RTT_OFF
-	},
-	{	/* cs3 */
-		FSL_DDR_ODT_NEVER,
-		FSL_DDR_ODT_NEVER,
-		DDR2_RTT_OFF,
-		DDR2_RTT_OFF
-	}
-};
-
-static const struct dynamic_odt dual_SS[4] = {
-	{	/* cs0 */
-		FSL_DDR_ODT_OTHER_DIMM,
-		FSL_DDR_ODT_OTHER_DIMM,
-		DDR2_RTT_75_OHM,
-		DDR2_RTT_OFF
-	},
-	{0, 0, 0, 0},
-	{	/* cs2 */
-		FSL_DDR_ODT_OTHER_DIMM,
-		FSL_DDR_ODT_OTHER_DIMM,
-		DDR2_RTT_75_OHM,
-		DDR2_RTT_OFF
-	},
-	{0, 0, 0, 0}
-};
-
-static const struct dynamic_odt dual_D0[4] = {
-	{	/* cs0 */
-		FSL_DDR_ODT_NEVER,
-		FSL_DDR_ODT_ALL,
-		DDR2_RTT_150_OHM,
-		DDR2_RTT_OFF
-	},
-	{	/* cs1 */
-		FSL_DDR_ODT_NEVER,
-		FSL_DDR_ODT_NEVER,
-		DDR2_RTT_OFF,
-		DDR2_RTT_OFF
-	},
-	{0, 0, 0, 0},
-	{0, 0, 0, 0}
-};
-
-static const struct dynamic_odt dual_0D[4] = {
-	{0, 0, 0, 0},
-	{0, 0, 0, 0},
-	{	/* cs2 */
-		FSL_DDR_ODT_NEVER,
-		FSL_DDR_ODT_ALL,
-		DDR2_RTT_150_OHM,
-		DDR2_RTT_OFF
-	},
-	{	/* cs3 */
-		FSL_DDR_ODT_NEVER,
-		FSL_DDR_ODT_NEVER,
-		DDR2_RTT_OFF,
-		DDR2_RTT_OFF
-	}
-};
-
-static const struct dynamic_odt dual_S0[4] = {
-	{	/* cs0 */
-		FSL_DDR_ODT_NEVER,
-		FSL_DDR_ODT_CS,
-		DDR2_RTT_150_OHM,
-		DDR2_RTT_OFF
-	},
-	{0, 0, 0, 0},
-	{0, 0, 0, 0},
-	{0, 0, 0, 0}
-
-};
-
-static const struct dynamic_odt dual_0S[4] = {
-	{0, 0, 0, 0},
-	{0, 0, 0, 0},
-	{	/* cs2 */
-		FSL_DDR_ODT_NEVER,
-		FSL_DDR_ODT_CS,
-		DDR2_RTT_150_OHM,
-		DDR2_RTT_OFF
-	},
-	{0, 0, 0, 0}
-
-};
-
-static const struct dynamic_odt odt_unknown[4] = {
-	{	/* cs0 */
-		FSL_DDR_ODT_NEVER,
-		FSL_DDR_ODT_CS,
-		DDR2_RTT_75_OHM,
-		DDR2_RTT_OFF
-	},
-	{	/* cs1 */
-		FSL_DDR_ODT_NEVER,
-		FSL_DDR_ODT_NEVER,
-		DDR2_RTT_OFF,
-		DDR2_RTT_OFF
-	},
-	{	/* cs2 */
-		FSL_DDR_ODT_NEVER,
-		FSL_DDR_ODT_CS,
-		DDR2_RTT_75_OHM,
-		DDR2_RTT_OFF
-	},
-	{	/* cs3 */
-		FSL_DDR_ODT_NEVER,
-		FSL_DDR_ODT_NEVER,
-		DDR2_RTT_OFF,
-		DDR2_RTT_OFF
-	}
-};
-#endif
-
-/*
- * Automatically seleect bank interleaving mode based on DIMMs
- * in this order: cs0_cs1_cs2_cs3, cs0_cs1, null.
- * This function only deal with one or two slots per controller.
- */
-static inline unsigned int auto_bank_intlv(dimm_params_t *pdimm)
-{
-#if (CONFIG_DIMM_SLOTS_PER_CTLR == 1)
-	if (pdimm[0].n_ranks == 4)
-		return FSL_DDR_CS0_CS1_CS2_CS3;
-	else if (pdimm[0].n_ranks == 2)
-		return FSL_DDR_CS0_CS1;
-#elif (CONFIG_DIMM_SLOTS_PER_CTLR == 2)
-#ifdef CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
-	if (pdimm[0].n_ranks == 4)
-		return FSL_DDR_CS0_CS1_CS2_CS3;
-#endif
-	if (pdimm[0].n_ranks == 2) {
-		if (pdimm[1].n_ranks == 2)
-			return FSL_DDR_CS0_CS1_CS2_CS3;
-		else
-			return FSL_DDR_CS0_CS1;
-	}
-#endif
-	return 0;
-}
-
-unsigned int populate_memctl_options(int all_DIMMs_registered,
-			memctl_options_t *popts,
-			dimm_params_t *pdimm,
-			unsigned int ctrl_num)
-{
-	unsigned int i;
-	char buffer[HWCONFIG_BUFFER_SIZE];
-	char *buf = NULL;
-#if defined(CONFIG_FSL_DDR3) || defined(CONFIG_FSL_DDR2)
-	const struct dynamic_odt *pdodt = odt_unknown;
-#endif
-	ulong ddr_freq;
-
-	/*
-	 * Extract hwconfig from environment since we have not properly setup
-	 * the environment but need it for ddr config params
-	 */
-	if (getenv_f("hwconfig", buffer, sizeof(buffer)) > 0)
-		buf = buffer;
-
-#if defined(CONFIG_FSL_DDR3) || defined(CONFIG_FSL_DDR2)
-	/* Chip select options. */
-	if (CONFIG_DIMM_SLOTS_PER_CTLR == 1) {
-		switch (pdimm[0].n_ranks) {
-		case 1:
-			pdodt = single_S;
-			break;
-		case 2:
-			pdodt = single_D;
-			break;
-		case 4:
-			pdodt = single_Q;
-			break;
-		}
-	} else if (CONFIG_DIMM_SLOTS_PER_CTLR == 2) {
-		switch (pdimm[0].n_ranks) {
-#ifdef CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
-		case 4:
-			pdodt = single_Q;
-			if (pdimm[1].n_ranks)
-				printf("Error: Quad- and Dual-rank DIMMs "
-					"cannot be used together\n");
-			break;
-#endif
-		case 2:
-			switch (pdimm[1].n_ranks) {
-			case 2:
-				pdodt = dual_DD;
-				break;
-			case 1:
-				pdodt = dual_DS;
-				break;
-			case 0:
-				pdodt = dual_D0;
-				break;
-			}
-			break;
-		case 1:
-			switch (pdimm[1].n_ranks) {
-			case 2:
-				pdodt = dual_SD;
-				break;
-			case 1:
-				pdodt = dual_SS;
-				break;
-			case 0:
-				pdodt = dual_S0;
-				break;
-			}
-			break;
-		case 0:
-			switch (pdimm[1].n_ranks) {
-			case 2:
-				pdodt = dual_0D;
-				break;
-			case 1:
-				pdodt = dual_0S;
-				break;
-			}
-			break;
-		}
-	}
-#endif
-
-	/* Pick chip-select local options. */
-	for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
-#if defined(CONFIG_FSL_DDR3) || defined(CONFIG_FSL_DDR2)
-		popts->cs_local_opts[i].odt_rd_cfg = pdodt[i].odt_rd_cfg;
-		popts->cs_local_opts[i].odt_wr_cfg = pdodt[i].odt_wr_cfg;
-		popts->cs_local_opts[i].odt_rtt_norm = pdodt[i].odt_rtt_norm;
-		popts->cs_local_opts[i].odt_rtt_wr = pdodt[i].odt_rtt_wr;
-#else
-		popts->cs_local_opts[i].odt_rd_cfg = FSL_DDR_ODT_NEVER;
-		popts->cs_local_opts[i].odt_wr_cfg = FSL_DDR_ODT_CS;
-#endif
-		popts->cs_local_opts[i].auto_precharge = 0;
-	}
-
-	/* Pick interleaving mode. */
-
-	/*
-	 * 0 = no interleaving
-	 * 1 = interleaving between 2 controllers
-	 */
-	popts->memctl_interleaving = 0;
-
-	/*
-	 * 0 = cacheline
-	 * 1 = page
-	 * 2 = (logical) bank
-	 * 3 = superbank (only if CS interleaving is enabled)
-	 */
-	popts->memctl_interleaving_mode = 0;
-
-	/*
-	 * 0: cacheline: bit 30 of the 36-bit physical addr selects the memctl
-	 * 1: page:      bit to the left of the column bits selects the memctl
-	 * 2: bank:      bit to the left of the bank bits selects the memctl
-	 * 3: superbank: bit to the left of the chip select selects the memctl
-	 *
-	 * NOTE: ba_intlv (rank interleaving) is independent of memory
-	 * controller interleaving; it is only within a memory controller.
-	 * Must use superbank interleaving if rank interleaving is used and
-	 * memory controller interleaving is enabled.
-	 */
-
-	/*
-	 * 0 = no
-	 * 0x40 = CS0,CS1
-	 * 0x20 = CS2,CS3
-	 * 0x60 = CS0,CS1 + CS2,CS3
-	 * 0x04 = CS0,CS1,CS2,CS3
-	 */
-	popts->ba_intlv_ctl = 0;
-
-	/* Memory Organization Parameters */
-	popts->registered_dimm_en = all_DIMMs_registered;
-
-	/* Operational Mode Paramters */
-
-	/* Pick ECC modes */
-	popts->ECC_mode = 0;		  /* 0 = disabled, 1 = enabled */
-#ifdef CONFIG_DDR_ECC
-	if (hwconfig_sub_f("fsl_ddr", "ecc", buf)) {
-		if (hwconfig_subarg_cmp_f("fsl_ddr", "ecc", "on", buf))
-			popts->ECC_mode = 1;
-	} else
-		popts->ECC_mode = 1;
-#endif
-	popts->ECC_init_using_memctl = 1; /* 0 = use DMA, 1 = use memctl */
-
-	/*
-	 * Choose DQS config
-	 * 0 for DDR1
-	 * 1 for DDR2
-	 */
-#if defined(CONFIG_FSL_DDR1)
-	popts->DQS_config = 0;
-#elif defined(CONFIG_FSL_DDR2) || defined(CONFIG_FSL_DDR3)
-	popts->DQS_config = 1;
-#endif
-
-	/* Choose self-refresh during sleep. */
-	popts->self_refresh_in_sleep = 1;
-
-	/* Choose dynamic power management mode. */
-	popts->dynamic_power = 0;
-
-	/*
-	 * check first dimm for primary sdram width
-	 * presuming all dimms are similar
-	 * 0 = 64-bit, 1 = 32-bit, 2 = 16-bit
-	 */
-#if defined(CONFIG_FSL_DDR1) || defined(CONFIG_FSL_DDR2)
-	if (pdimm[0].n_ranks != 0) {
-		if ((pdimm[0].data_width >= 64) && \
-			(pdimm[0].data_width <= 72))
-			popts->data_bus_width = 0;
-		else if ((pdimm[0].data_width >= 32) || \
-			(pdimm[0].data_width <= 40))
-			popts->data_bus_width = 1;
-		else {
-			panic("Error: data width %u is invalid!\n",
-				pdimm[0].data_width);
-		}
-	}
-#else
-	if (pdimm[0].n_ranks != 0) {
-		if (pdimm[0].primary_sdram_width == 64)
-			popts->data_bus_width = 0;
-		else if (pdimm[0].primary_sdram_width == 32)
-			popts->data_bus_width = 1;
-		else if (pdimm[0].primary_sdram_width == 16)
-			popts->data_bus_width = 2;
-		else {
-			panic("Error: primary sdram width %u is invalid!\n",
-				pdimm[0].primary_sdram_width);
-		}
-	}
-#endif
-
-	popts->x4_en = (pdimm[0].device_width == 4) ? 1 : 0;
-
-	/* Choose burst length. */
-#if defined(CONFIG_FSL_DDR3)
-#if defined(CONFIG_E500MC)
-	popts->OTF_burst_chop_en = 0;	/* on-the-fly burst chop disable */
-	popts->burst_length = DDR_BL8;	/* Fixed 8-beat burst len */
-#else
-	if ((popts->data_bus_width == 1) || (popts->data_bus_width == 2)) {
-		/* 32-bit or 16-bit bus */
-		popts->OTF_burst_chop_en = 0;
-		popts->burst_length = DDR_BL8;
-	} else {
-		popts->OTF_burst_chop_en = 1;	/* on-the-fly burst chop */
-		popts->burst_length = DDR_OTF;	/* on-the-fly BC4 and BL8 */
-	}
-#endif
-#else
-	popts->burst_length = DDR_BL4;	/* has to be 4 for DDR2 */
-#endif
-
-	/* Choose ddr controller address mirror mode */
-#if defined(CONFIG_FSL_DDR3)
-	popts->mirrored_dimm = pdimm[0].mirrored_dimm;
-#endif
-
-	/* Global Timing Parameters. */
-	debug("mclk_ps = %u ps\n", get_memory_clk_period_ps());
-
-	/* Pick a caslat override. */
-	popts->cas_latency_override = 0;
-	popts->cas_latency_override_value = 3;
-	if (popts->cas_latency_override) {
-		debug("using caslat override value = %u\n",
-		       popts->cas_latency_override_value);
-	}
-
-	/* Decide whether to use the computed derated latency */
-	popts->use_derated_caslat = 0;
-
-	/* Choose an additive latency. */
-	popts->additive_latency_override = 0;
-	popts->additive_latency_override_value = 3;
-	if (popts->additive_latency_override) {
-		debug("using additive latency override value = %u\n",
-		       popts->additive_latency_override_value);
-	}
-
-	/*
-	 * 2T_EN setting
-	 *
-	 * Factors to consider for 2T_EN:
-	 *	- number of DIMMs installed
-	 *	- number of components, number of active ranks
-	 *	- how much time you want to spend playing around
-	 */
-	popts->twoT_en = 0;
-	popts->threeT_en = 0;
-
-	/* for RDIMM, address parity enable */
-	popts->ap_en = 1;
-
-	/*
-	 * BSTTOPRE precharge interval
-	 *
-	 * Set this to 0 for global auto precharge
-	 *
-	 * FIXME: Should this be configured in picoseconds?
-	 * Why it should be in ps:  better understanding of this
-	 * relative to actual DRAM timing parameters such as tRAS.
-	 * e.g. tRAS(min) = 40 ns
-	 */
-	popts->bstopre = 0x100;
-
-	/* Minimum CKE pulse width -- tCKE(MIN) */
-	popts->tCKE_clock_pulse_width_ps
-		= mclk_to_picos(FSL_DDR_MIN_TCKE_PULSE_WIDTH_DDR);
-
-	/*
-	 * Window for four activates -- tFAW
-	 *
-	 * FIXME: UM: applies only to DDR2/DDR3 with eight logical banks only
-	 * FIXME: varies depending upon number of column addresses or data
-	 * FIXME: width, was considering looking at pdimm->primary_sdram_width
-	 */
-#if defined(CONFIG_FSL_DDR1)
-	popts->tFAW_window_four_activates_ps = mclk_to_picos(1);
-
-#elif defined(CONFIG_FSL_DDR2)
-	/*
-	 * x4/x8;  some datasheets have 35000
-	 * x16 wide columns only?  Use 50000?
-	 */
-	popts->tFAW_window_four_activates_ps = 37500;
-
-#elif defined(CONFIG_FSL_DDR3)
-	popts->tFAW_window_four_activates_ps = pdimm[0].tFAW_ps;
-#endif
-	popts->zq_en = 0;
-	popts->wrlvl_en = 0;
-#if defined(CONFIG_FSL_DDR3)
-	/*
-	 * due to ddr3 dimm is fly-by topology
-	 * we suggest to enable write leveling to
-	 * meet the tQDSS under different loading.
-	 */
-	popts->wrlvl_en = 1;
-	popts->zq_en = 1;
-	popts->wrlvl_override = 0;
-#endif
-
-	/*
-	 * Check interleaving configuration from environment.
-	 * Please refer to doc/README.fsl-ddr for the detail.
-	 *
-	 * If memory controller interleaving is enabled, then the data
-	 * bus widths must be programmed identically for all memory controllers.
-	 *
-	 * XXX: Attempt to set all controllers to the same chip select
-	 * interleaving mode. It will do a best effort to get the
-	 * requested ranks interleaved together such that the result
-	 * should be a subset of the requested configuration.
-	 */
-#if (CONFIG_NUM_DDR_CONTROLLERS > 1)
-	if (!hwconfig_sub_f("fsl_ddr", "ctlr_intlv", buf))
-		goto done;
-
-	if (pdimm[0].n_ranks == 0) {
-		printf("There is no rank on CS0 for controller %d.\n", ctrl_num);
-		popts->memctl_interleaving = 0;
-		goto done;
-	}
-	popts->memctl_interleaving = 1;
-	/*
-	 * test null first. if CONFIG_HWCONFIG is not defined
-	 * hwconfig_arg_cmp returns non-zero
-	 */
-	if (hwconfig_subarg_cmp_f("fsl_ddr", "ctlr_intlv",
-				    "null", buf)) {
-		popts->memctl_interleaving = 0;
-		debug("memory controller interleaving disabled.\n");
-	} else if (hwconfig_subarg_cmp_f("fsl_ddr",
-					"ctlr_intlv",
-					"cacheline", buf)) {
-		popts->memctl_interleaving_mode =
-			((CONFIG_NUM_DDR_CONTROLLERS == 3) && ctrl_num == 2) ?
-			0 : FSL_DDR_CACHE_LINE_INTERLEAVING;
-		popts->memctl_interleaving =
-			((CONFIG_NUM_DDR_CONTROLLERS == 3) && ctrl_num == 2) ?
-			0 : 1;
-	} else if (hwconfig_subarg_cmp_f("fsl_ddr",
-					"ctlr_intlv",
-					"page", buf)) {
-		popts->memctl_interleaving_mode =
-			((CONFIG_NUM_DDR_CONTROLLERS == 3) && ctrl_num == 2) ?
-			0 : FSL_DDR_PAGE_INTERLEAVING;
-		popts->memctl_interleaving =
-			((CONFIG_NUM_DDR_CONTROLLERS == 3) && ctrl_num == 2) ?
-			0 : 1;
-	} else if (hwconfig_subarg_cmp_f("fsl_ddr",
-					"ctlr_intlv",
-					"bank", buf)) {
-		popts->memctl_interleaving_mode =
-			((CONFIG_NUM_DDR_CONTROLLERS == 3) && ctrl_num == 2) ?
-			0 : FSL_DDR_BANK_INTERLEAVING;
-		popts->memctl_interleaving =
-			((CONFIG_NUM_DDR_CONTROLLERS == 3) && ctrl_num == 2) ?
-			0 : 1;
-	} else if (hwconfig_subarg_cmp_f("fsl_ddr",
-					"ctlr_intlv",
-					"superbank", buf)) {
-		popts->memctl_interleaving_mode =
-			((CONFIG_NUM_DDR_CONTROLLERS == 3) && ctrl_num == 2) ?
-			0 : FSL_DDR_SUPERBANK_INTERLEAVING;
-		popts->memctl_interleaving =
-			((CONFIG_NUM_DDR_CONTROLLERS == 3) && ctrl_num == 2) ?
-			0 : 1;
-#if (CONFIG_NUM_DDR_CONTROLLERS == 3)
-	} else if (hwconfig_subarg_cmp_f("fsl_ddr",
-					"ctlr_intlv",
-					"3way_1KB", buf)) {
-		popts->memctl_interleaving_mode =
-			FSL_DDR_3WAY_1KB_INTERLEAVING;
-	} else if (hwconfig_subarg_cmp_f("fsl_ddr",
-					"ctlr_intlv",
-					"3way_4KB", buf)) {
-		popts->memctl_interleaving_mode =
-			FSL_DDR_3WAY_4KB_INTERLEAVING;
-	} else if (hwconfig_subarg_cmp_f("fsl_ddr",
-					"ctlr_intlv",
-					"3way_8KB", buf)) {
-		popts->memctl_interleaving_mode =
-			FSL_DDR_3WAY_8KB_INTERLEAVING;
-#elif (CONFIG_NUM_DDR_CONTROLLERS == 4)
-	} else if (hwconfig_subarg_cmp_f("fsl_ddr",
-					"ctlr_intlv",
-					"4way_1KB", buf)) {
-		popts->memctl_interleaving_mode =
-			FSL_DDR_4WAY_1KB_INTERLEAVING;
-	} else if (hwconfig_subarg_cmp_f("fsl_ddr",
-					"ctlr_intlv",
-					"4way_4KB", buf)) {
-		popts->memctl_interleaving_mode =
-			FSL_DDR_4WAY_4KB_INTERLEAVING;
-	} else if (hwconfig_subarg_cmp_f("fsl_ddr",
-					"ctlr_intlv",
-					"4way_8KB", buf)) {
-		popts->memctl_interleaving_mode =
-			FSL_DDR_4WAY_8KB_INTERLEAVING;
-#endif
-	} else {
-		popts->memctl_interleaving = 0;
-		printf("hwconfig has unrecognized parameter for ctlr_intlv.\n");
-	}
-done:
-#endif
-	if ((hwconfig_sub_f("fsl_ddr", "bank_intlv", buf)) &&
-		(CONFIG_CHIP_SELECTS_PER_CTRL > 1)) {
-		/* test null first. if CONFIG_HWCONFIG is not defined,
-		 * hwconfig_subarg_cmp_f returns non-zero */
-		if (hwconfig_subarg_cmp_f("fsl_ddr", "bank_intlv",
-					    "null", buf))
-			debug("bank interleaving disabled.\n");
-		else if (hwconfig_subarg_cmp_f("fsl_ddr", "bank_intlv",
-						 "cs0_cs1", buf))
-			popts->ba_intlv_ctl = FSL_DDR_CS0_CS1;
-		else if (hwconfig_subarg_cmp_f("fsl_ddr", "bank_intlv",
-						 "cs2_cs3", buf))
-			popts->ba_intlv_ctl = FSL_DDR_CS2_CS3;
-		else if (hwconfig_subarg_cmp_f("fsl_ddr", "bank_intlv",
-						 "cs0_cs1_and_cs2_cs3", buf))
-			popts->ba_intlv_ctl = FSL_DDR_CS0_CS1_AND_CS2_CS3;
-		else if (hwconfig_subarg_cmp_f("fsl_ddr", "bank_intlv",
-						 "cs0_cs1_cs2_cs3", buf))
-			popts->ba_intlv_ctl = FSL_DDR_CS0_CS1_CS2_CS3;
-		else if (hwconfig_subarg_cmp_f("fsl_ddr", "bank_intlv",
-						"auto", buf))
-			popts->ba_intlv_ctl = auto_bank_intlv(pdimm);
-		else
-			printf("hwconfig has unrecognized parameter for bank_intlv.\n");
-		switch (popts->ba_intlv_ctl & FSL_DDR_CS0_CS1_CS2_CS3) {
-		case FSL_DDR_CS0_CS1_CS2_CS3:
-#if (CONFIG_DIMM_SLOTS_PER_CTLR == 1)
-			if (pdimm[0].n_ranks < 4) {
-				popts->ba_intlv_ctl = 0;
-				printf("Not enough bank(chip-select) for "
-					"CS0+CS1+CS2+CS3 on controller %d, "
-					"interleaving disabled!\n", ctrl_num);
-			}
-#elif (CONFIG_DIMM_SLOTS_PER_CTLR == 2)
-#ifdef CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
-			if (pdimm[0].n_ranks == 4)
-				break;
-#endif
-			if ((pdimm[0].n_ranks < 2) && (pdimm[1].n_ranks < 2)) {
-				popts->ba_intlv_ctl = 0;
-				printf("Not enough bank(chip-select) for "
-					"CS0+CS1+CS2+CS3 on controller %d, "
-					"interleaving disabled!\n", ctrl_num);
-			}
-			if (pdimm[0].capacity != pdimm[1].capacity) {
-				popts->ba_intlv_ctl = 0;
-				printf("Not identical DIMM size for "
-					"CS0+CS1+CS2+CS3 on controller %d, "
-					"interleaving disabled!\n", ctrl_num);
-			}
-#endif
-			break;
-		case FSL_DDR_CS0_CS1:
-			if (pdimm[0].n_ranks < 2) {
-				popts->ba_intlv_ctl = 0;
-				printf("Not enough bank(chip-select) for "
-					"CS0+CS1 on controller %d, "
-					"interleaving disabled!\n", ctrl_num);
-			}
-			break;
-		case FSL_DDR_CS2_CS3:
-#if (CONFIG_DIMM_SLOTS_PER_CTLR == 1)
-			if (pdimm[0].n_ranks < 4) {
-				popts->ba_intlv_ctl = 0;
-				printf("Not enough bank(chip-select) for CS2+CS3 "
-					"on controller %d, interleaving disabled!\n", ctrl_num);
-			}
-#elif (CONFIG_DIMM_SLOTS_PER_CTLR == 2)
-			if (pdimm[1].n_ranks < 2) {
-				popts->ba_intlv_ctl = 0;
-				printf("Not enough bank(chip-select) for CS2+CS3 "
-					"on controller %d, interleaving disabled!\n", ctrl_num);
-			}
-#endif
-			break;
-		case FSL_DDR_CS0_CS1_AND_CS2_CS3:
-#if (CONFIG_DIMM_SLOTS_PER_CTLR == 1)
-			if (pdimm[0].n_ranks < 4) {
-				popts->ba_intlv_ctl = 0;
-				printf("Not enough bank(CS) for CS0+CS1 and "
-					"CS2+CS3 on controller %d, "
-					"interleaving disabled!\n", ctrl_num);
-			}
-#elif (CONFIG_DIMM_SLOTS_PER_CTLR == 2)
-			if ((pdimm[0].n_ranks < 2) || (pdimm[1].n_ranks < 2)) {
-				popts->ba_intlv_ctl = 0;
-				printf("Not enough bank(CS) for CS0+CS1 and "
-					"CS2+CS3 on controller %d, "
-					"interleaving disabled!\n", ctrl_num);
-			}
-#endif
-			break;
-		default:
-			popts->ba_intlv_ctl = 0;
-			break;
-		}
-	}
-
-	if (hwconfig_sub_f("fsl_ddr", "addr_hash", buf)) {
-		if (hwconfig_subarg_cmp_f("fsl_ddr", "addr_hash", "null", buf))
-			popts->addr_hash = 0;
-		else if (hwconfig_subarg_cmp_f("fsl_ddr", "addr_hash",
-					       "true", buf))
-			popts->addr_hash = 1;
-	}
-
-	if (pdimm[0].n_ranks == 4)
-		popts->quad_rank_present = 1;
-
-	ddr_freq = get_ddr_freq(0) / 1000000;
-	if (popts->registered_dimm_en) {
-		popts->rcw_override = 1;
-		popts->rcw_1 = 0x000a5a00;
-		if (ddr_freq <= 800)
-			popts->rcw_2 = 0x00000000;
-		else if (ddr_freq <= 1066)
-			popts->rcw_2 = 0x00100000;
-		else if (ddr_freq <= 1333)
-			popts->rcw_2 = 0x00200000;
-		else
-			popts->rcw_2 = 0x00300000;
-	}
-
-	fsl_ddr_board_options(popts, pdimm, ctrl_num);
-
-	return 0;
-}
-
-void check_interleaving_options(fsl_ddr_info_t *pinfo)
-{
-	int i, j, k, check_n_ranks, intlv_invalid = 0;
-	unsigned int check_intlv, check_n_row_addr, check_n_col_addr;
-	unsigned long long check_rank_density;
-	struct dimm_params_s *dimm;
-	/*
-	 * Check if all controllers are configured for memory
-	 * controller interleaving. Identical dimms are recommended. At least
-	 * the size, row and col address should be checked.
-	 */
-	j = 0;
-	check_n_ranks = pinfo->dimm_params[0][0].n_ranks;
-	check_rank_density = pinfo->dimm_params[0][0].rank_density;
-	check_n_row_addr =  pinfo->dimm_params[0][0].n_row_addr;
-	check_n_col_addr = pinfo->dimm_params[0][0].n_col_addr;
-	check_intlv = pinfo->memctl_opts[0].memctl_interleaving_mode;
-	for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
-		dimm = &pinfo->dimm_params[i][0];
-		if (!pinfo->memctl_opts[i].memctl_interleaving) {
-			continue;
-		} else if (((check_rank_density != dimm->rank_density) ||
-		     (check_n_ranks != dimm->n_ranks) ||
-		     (check_n_row_addr != dimm->n_row_addr) ||
-		     (check_n_col_addr != dimm->n_col_addr) ||
-		     (check_intlv !=
-			pinfo->memctl_opts[i].memctl_interleaving_mode))){
-			intlv_invalid = 1;
-			break;
-		} else {
-			j++;
-		}
-
-	}
-	if (intlv_invalid) {
-		for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++)
-			pinfo->memctl_opts[i].memctl_interleaving = 0;
-		printf("Not all DIMMs are identical. "
-			"Memory controller interleaving disabled.\n");
-	} else {
-		switch (check_intlv) {
-		case FSL_DDR_CACHE_LINE_INTERLEAVING:
-		case FSL_DDR_PAGE_INTERLEAVING:
-		case FSL_DDR_BANK_INTERLEAVING:
-		case FSL_DDR_SUPERBANK_INTERLEAVING:
-			if (3 == CONFIG_NUM_DDR_CONTROLLERS)
-				k = 2;
-			else
-				k = CONFIG_NUM_DDR_CONTROLLERS;
-			break;
-		case FSL_DDR_3WAY_1KB_INTERLEAVING:
-		case FSL_DDR_3WAY_4KB_INTERLEAVING:
-		case FSL_DDR_3WAY_8KB_INTERLEAVING:
-		case FSL_DDR_4WAY_1KB_INTERLEAVING:
-		case FSL_DDR_4WAY_4KB_INTERLEAVING:
-		case FSL_DDR_4WAY_8KB_INTERLEAVING:
-		default:
-			k = CONFIG_NUM_DDR_CONTROLLERS;
-			break;
-		}
-		debug("%d of %d controllers are interleaving.\n", j, k);
-		if (j && (j != k)) {
-			for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++)
-				pinfo->memctl_opts[i].memctl_interleaving = 0;
-			printf("Not all controllers have compatible "
-				"interleaving mode. All disabled.\n");
-		}
-	}
-	debug("Checking interleaving options completed\n");
-}
-
-int fsl_use_spd(void)
-{
-	int use_spd = 0;
-
-#ifdef CONFIG_DDR_SPD
-	char buffer[HWCONFIG_BUFFER_SIZE];
-	char *buf = NULL;
-
-	/*
-	 * Extract hwconfig from environment since we have not properly setup
-	 * the environment but need it for ddr config params
-	 */
-	if (getenv_f("hwconfig", buffer, sizeof(buffer)) > 0)
-		buf = buffer;
-
-	/* if hwconfig is not enabled, or "sdram" is not defined, use spd */
-	if (hwconfig_sub_f("fsl_ddr", "sdram", buf)) {
-		if (hwconfig_subarg_cmp_f("fsl_ddr", "sdram", "spd", buf))
-			use_spd = 1;
-		else if (hwconfig_subarg_cmp_f("fsl_ddr", "sdram",
-					       "fixed", buf))
-			use_spd = 0;
-		else
-			use_spd = 1;
-	} else
-		use_spd = 1;
-#endif
-
-	return use_spd;
-}
diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/util.c b/arch/powerpc/cpu/mpc8xxx/ddr/util.c
deleted file mode 100644
index acfe1f095f..0000000000
--- a/arch/powerpc/cpu/mpc8xxx/ddr/util.c
+++ /dev/null
@@ -1,264 +0,0 @@
-/*
- * Copyright 2008-2012 Freescale Semiconductor, Inc.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * Version 2 as published by the Free Software Foundation.
- */
-
-#include <common.h>
-#include <asm/fsl_law.h>
-#include <div64.h>
-
-#include "ddr.h"
-
-/* To avoid 64-bit full-divides, we factor this here */
-#define ULL_2E12 2000000000000ULL
-#define UL_5POW12 244140625UL
-#define UL_2POW13 (1UL << 13)
-
-#define ULL_8FS 0xFFFFFFFFULL
-
-/*
- * Round up mclk_ps to nearest 1 ps in memory controller code
- * if the error is 0.5ps or more.
- *
- * If an imprecise data rate is too high due to rounding error
- * propagation, compute a suitably rounded mclk_ps to compute
- * a working memory controller configuration.
- */
-unsigned int get_memory_clk_period_ps(void)
-{
-	unsigned int data_rate = get_ddr_freq(0);
-	unsigned int result;
-
-	/* Round to nearest 10ps, being careful about 64-bit multiply/divide */
-	unsigned long long rem, mclk_ps = ULL_2E12;
-
-	/* Now perform the big divide, the result fits in 32-bits */
-	rem = do_div(mclk_ps, data_rate);
-	result = (rem >= (data_rate >> 1)) ? mclk_ps + 1 : mclk_ps;
-
-	return result;
-}
-
-/* Convert picoseconds into DRAM clock cycles (rounding up if needed). */
-unsigned int picos_to_mclk(unsigned int picos)
-{
-	unsigned long long clks, clks_rem;
-	unsigned long data_rate = get_ddr_freq(0);
-
-	/* Short circuit for zero picos */
-	if (!picos)
-		return 0;
-
-	/* First multiply the time by the data rate (32x32 => 64) */
-	clks = picos * (unsigned long long)data_rate;
-	/*
-	 * Now divide by 5^12 and track the 32-bit remainder, then divide
-	 * by 2*(2^12) using shifts (and updating the remainder).
-	 */
-	clks_rem = do_div(clks, UL_5POW12);
-	clks_rem += (clks & (UL_2POW13-1)) * UL_5POW12;
-	clks >>= 13;
-
-	/* If we had a remainder greater than the 1ps error, then round up */
-	if (clks_rem > data_rate)
-		clks++;
-
-	/* Clamp to the maximum representable value */
-	if (clks > ULL_8FS)
-		clks = ULL_8FS;
-	return (unsigned int) clks;
-}
-
-unsigned int mclk_to_picos(unsigned int mclk)
-{
-	return get_memory_clk_period_ps() * mclk;
-}
-
-void
-__fsl_ddr_set_lawbar(const common_timing_params_t *memctl_common_params,
-			   unsigned int law_memctl,
-			   unsigned int ctrl_num)
-{
-	unsigned long long base = memctl_common_params->base_address;
-	unsigned long long size = memctl_common_params->total_mem;
-
-	/*
-	 * If no DIMMs on this controller, do not proceed any further.
-	 */
-	if (!memctl_common_params->ndimms_present) {
-		return;
-	}
-
-#if !defined(CONFIG_PHYS_64BIT)
-	if (base >= CONFIG_MAX_MEM_MAPPED)
-		return;
-	if ((base + size) >= CONFIG_MAX_MEM_MAPPED)
-		size = CONFIG_MAX_MEM_MAPPED - base;
-#endif
-	if (set_ddr_laws(base, size, law_memctl) < 0) {
-		printf("%s: ERROR (ctrl #%d, TRGT ID=%x)\n", __func__, ctrl_num,
-			law_memctl);
-		return ;
-	}
-	debug("setup ddr law base = 0x%llx, size 0x%llx, TRGT_ID 0x%x\n",
-		base, size, law_memctl);
-}
-
-__attribute__((weak, alias("__fsl_ddr_set_lawbar"))) void
-fsl_ddr_set_lawbar(const common_timing_params_t *memctl_common_params,
-			 unsigned int memctl_interleaved,
-			 unsigned int ctrl_num);
-
-void fsl_ddr_set_intl3r(const unsigned int granule_size)
-{
-#ifdef CONFIG_E6500
-	u32 *mcintl3r = (void *) (CONFIG_SYS_IMMR + 0x18004);
-	*mcintl3r = 0x80000000 | (granule_size & 0x1f);
-	debug("Enable MCINTL3R with granule size 0x%x\n", granule_size);
-#endif
-}
-
-u32 fsl_ddr_get_intl3r(void)
-{
-	u32 val = 0;
-#ifdef CONFIG_E6500
-	u32 *mcintl3r = (void *) (CONFIG_SYS_IMMR + 0x18004);
-	val = *mcintl3r;
-#endif
-	return val;
-}
-
-void board_add_ram_info(int use_default)
-{
-	ccsr_ddr_t *ddr = (void *)(CONFIG_SYS_MPC8xxx_DDR_ADDR);
-
-#if	defined(CONFIG_E6500) && (CONFIG_NUM_DDR_CONTROLLERS == 3)
-	u32 *mcintl3r = (void *) (CONFIG_SYS_IMMR + 0x18004);
-#endif
-#if (CONFIG_NUM_DDR_CONTROLLERS > 1)
-	uint32_t cs0_config = in_be32(&ddr->cs0_config);
-#endif
-	uint32_t sdram_cfg = in_be32(&ddr->sdram_cfg);
-	int cas_lat;
-
-#if CONFIG_NUM_DDR_CONTROLLERS >= 2
-	if (!(sdram_cfg & SDRAM_CFG_MEM_EN)) {
-		ddr = (void __iomem *)CONFIG_SYS_MPC8xxx_DDR2_ADDR;
-		sdram_cfg = in_be32(&ddr->sdram_cfg);
-	}
-#endif
-#if CONFIG_NUM_DDR_CONTROLLERS >= 3
-	if (!(sdram_cfg & SDRAM_CFG_MEM_EN)) {
-		ddr = (void __iomem *)CONFIG_SYS_MPC8xxx_DDR3_ADDR;
-		sdram_cfg = in_be32(&ddr->sdram_cfg);
-	}
-#endif
-	puts(" (DDR");
-	switch ((sdram_cfg & SDRAM_CFG_SDRAM_TYPE_MASK) >>
-		SDRAM_CFG_SDRAM_TYPE_SHIFT) {
-	case SDRAM_TYPE_DDR1:
-		puts("1");
-		break;
-	case SDRAM_TYPE_DDR2:
-		puts("2");
-		break;
-	case SDRAM_TYPE_DDR3:
-		puts("3");
-		break;
-	default:
-		puts("?");
-		break;
-	}
-
-	if (sdram_cfg & SDRAM_CFG_32_BE)
-		puts(", 32-bit");
-	else if (sdram_cfg & SDRAM_CFG_16_BE)
-		puts(", 16-bit");
-	else
-		puts(", 64-bit");
-
-	/* Calculate CAS latency based on timing cfg values */
-	cas_lat = ((in_be32(&ddr->timing_cfg_1) >> 16) & 0xf) + 1;
-	if ((in_be32(&ddr->timing_cfg_3) >> 12) & 1)
-		cas_lat += (8 << 1);
-	printf(", CL=%d", cas_lat >> 1);
-	if (cas_lat & 0x1)
-		puts(".5");
-
-	if (sdram_cfg & SDRAM_CFG_ECC_EN)
-		puts(", ECC on)");
-	else
-		puts(", ECC off)");
-
-#if (CONFIG_NUM_DDR_CONTROLLERS == 3)
-#ifdef CONFIG_E6500
-	if (*mcintl3r & 0x80000000) {
-		puts("\n");
-		puts("       DDR Controller Interleaving Mode: ");
-		switch (*mcintl3r & 0x1f) {
-		case FSL_DDR_3WAY_1KB_INTERLEAVING:
-			puts("3-way 1KB");
-			break;
-		case FSL_DDR_3WAY_4KB_INTERLEAVING:
-			puts("3-way 4KB");
-			break;
-		case FSL_DDR_3WAY_8KB_INTERLEAVING:
-			puts("3-way 8KB");
-			break;
-		default:
-			puts("3-way UNKNOWN");
-			break;
-		}
-	}
-#endif
-#endif
-#if (CONFIG_NUM_DDR_CONTROLLERS >= 2)
-	if (cs0_config & 0x20000000) {
-		puts("\n");
-		puts("       DDR Controller Interleaving Mode: ");
-
-		switch ((cs0_config >> 24) & 0xf) {
-		case FSL_DDR_CACHE_LINE_INTERLEAVING:
-			puts("cache line");
-			break;
-		case FSL_DDR_PAGE_INTERLEAVING:
-			puts("page");
-			break;
-		case FSL_DDR_BANK_INTERLEAVING:
-			puts("bank");
-			break;
-		case FSL_DDR_SUPERBANK_INTERLEAVING:
-			puts("super-bank");
-			break;
-		default:
-			puts("invalid");
-			break;
-		}
-	}
-#endif
-
-	if ((sdram_cfg >> 8) & 0x7f) {
-		puts("\n");
-		puts("       DDR Chip-Select Interleaving Mode: ");
-		switch(sdram_cfg >> 8 & 0x7f) {
-		case FSL_DDR_CS0_CS1_CS2_CS3:
-			puts("CS0+CS1+CS2+CS3");
-			break;
-		case FSL_DDR_CS0_CS1:
-			puts("CS0+CS1");
-			break;
-		case FSL_DDR_CS2_CS3:
-			puts("CS2+CS3");
-			break;
-		case FSL_DDR_CS0_CS1_AND_CS2_CS3:
-			puts("CS0+CS1 and CS2+CS3");
-			break;
-		default:
-			puts("invalid");
-			break;
-		}
-	}
-}
diff --git a/arch/powerpc/cpu/mpc8xxx/fdt.c b/arch/powerpc/cpu/mpc8xxx/fdt.c
index eb7cbbce7e..9273745299 100644
--- a/arch/powerpc/cpu/mpc8xxx/fdt.c
+++ b/arch/powerpc/cpu/mpc8xxx/fdt.c
@@ -15,7 +15,9 @@
 #include <phy.h>
 #include <hwconfig.h>
 
-#define FSL_MAX_NUM_USB_CTRLS	2
+#ifndef CONFIG_USB_MAX_CONTROLLER_COUNT
+#define CONFIG_USB_MAX_CONTROLLER_COUNT	1
+#endif
 
 #if defined(CONFIG_MP) && (defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx))
 static int ft_del_cpuhandle(void *blob, int cpuhandle)
@@ -128,7 +130,7 @@ void fdt_fixup_dr_usb(void *blob, bd_t *bd)
 	char str[5];
 	int i, j;
 
-	for (i = 1; i <= FSL_MAX_NUM_USB_CTRLS; i++) {
+	for (i = 1; i <= CONFIG_USB_MAX_CONTROLLER_COUNT; i++) {
 		int mode_idx = -1, phy_idx = -1;
 		snprintf(str, 5, "%s%d", "usb", i);
 		if (hwconfig(str)) {
diff --git a/arch/powerpc/cpu/mpc8xxx/fsl_ifc.c b/arch/powerpc/cpu/mpc8xxx/fsl_ifc.c
deleted file mode 100644
index 2d0fb433bc..0000000000
--- a/arch/powerpc/cpu/mpc8xxx/fsl_ifc.c
+++ /dev/null
@@ -1,140 +0,0 @@
-/*
- * Copyright 2010-2011 Freescale Semiconductor, Inc.
- * Author: Dipen Dudhat <dipen.dudhat@freescale.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/fsl_ifc.h>
-
-void print_ifc_regs(void)
-{
-	int i, j;
-
-	printf("IFC Controller Registers\n");
-	for (i = 0; i < CONFIG_SYS_FSL_IFC_BANK_COUNT; i++) {
-		printf("CSPR%d:0x%08X\tAMASK%d:0x%08X\tCSOR%d:0x%08X\n",
-			i, get_ifc_cspr(i), i, get_ifc_amask(i),
-			i, get_ifc_csor(i));
-		for (j = 0; j < 4; j++)
-			printf("IFC_FTIM%d:0x%08X\n", j, get_ifc_ftim(i, j));
-	}
-}
-
-void init_early_memctl_regs(void)
-{
-#if defined(CONFIG_SYS_CSPR0) && defined(CONFIG_SYS_CSOR0)
-	set_ifc_ftim(IFC_CS0, IFC_FTIM0, CONFIG_SYS_CS0_FTIM0);
-	set_ifc_ftim(IFC_CS0, IFC_FTIM1, CONFIG_SYS_CS0_FTIM1);
-	set_ifc_ftim(IFC_CS0, IFC_FTIM2, CONFIG_SYS_CS0_FTIM2);
-	set_ifc_ftim(IFC_CS0, IFC_FTIM3, CONFIG_SYS_CS0_FTIM3);
-
-#ifndef CONFIG_A003399_NOR_WORKAROUND
-#ifdef CONFIG_SYS_CSPR0_EXT
-	set_ifc_cspr_ext(IFC_CS0, CONFIG_SYS_CSPR0_EXT);
-#endif
-	set_ifc_cspr(IFC_CS0, CONFIG_SYS_CSPR0);
-	set_ifc_amask(IFC_CS0, CONFIG_SYS_AMASK0);
-	set_ifc_csor(IFC_CS0, CONFIG_SYS_CSOR0);
-#endif
-#endif
-
-#ifdef CONFIG_SYS_CSPR1_EXT
-	set_ifc_cspr_ext(IFC_CS1, CONFIG_SYS_CSPR1_EXT);
-#endif
-#if defined(CONFIG_SYS_CSPR1) && defined(CONFIG_SYS_CSOR1)
-	set_ifc_ftim(IFC_CS1, IFC_FTIM0, CONFIG_SYS_CS1_FTIM0);
-	set_ifc_ftim(IFC_CS1, IFC_FTIM1, CONFIG_SYS_CS1_FTIM1);
-	set_ifc_ftim(IFC_CS1, IFC_FTIM2, CONFIG_SYS_CS1_FTIM2);
-	set_ifc_ftim(IFC_CS1, IFC_FTIM3, CONFIG_SYS_CS1_FTIM3);
-
-	set_ifc_csor(IFC_CS1, CONFIG_SYS_CSOR1);
-	set_ifc_amask(IFC_CS1, CONFIG_SYS_AMASK1);
-	set_ifc_cspr(IFC_CS1, CONFIG_SYS_CSPR1);
-#endif
-
-#ifdef CONFIG_SYS_CSPR2_EXT
-	set_ifc_cspr_ext(IFC_CS2, CONFIG_SYS_CSPR2_EXT);
-#endif
-#if defined(CONFIG_SYS_CSPR2) && defined(CONFIG_SYS_CSOR2)
-	set_ifc_ftim(IFC_CS2, IFC_FTIM0, CONFIG_SYS_CS2_FTIM0);
-	set_ifc_ftim(IFC_CS2, IFC_FTIM1, CONFIG_SYS_CS2_FTIM1);
-	set_ifc_ftim(IFC_CS2, IFC_FTIM2, CONFIG_SYS_CS2_FTIM2);
-	set_ifc_ftim(IFC_CS2, IFC_FTIM3, CONFIG_SYS_CS2_FTIM3);
-
-	set_ifc_csor(IFC_CS2, CONFIG_SYS_CSOR2);
-	set_ifc_amask(IFC_CS2, CONFIG_SYS_AMASK2);
-	set_ifc_cspr(IFC_CS2, CONFIG_SYS_CSPR2);
-#endif
-
-#ifdef CONFIG_SYS_CSPR3_EXT
-	set_ifc_cspr_ext(IFC_CS3, CONFIG_SYS_CSPR3_EXT);
-#endif
-#if defined(CONFIG_SYS_CSPR3) && defined(CONFIG_SYS_CSOR3)
-	set_ifc_ftim(IFC_CS3, IFC_FTIM0, CONFIG_SYS_CS3_FTIM0);
-	set_ifc_ftim(IFC_CS3, IFC_FTIM1, CONFIG_SYS_CS3_FTIM1);
-	set_ifc_ftim(IFC_CS3, IFC_FTIM2, CONFIG_SYS_CS3_FTIM2);
-	set_ifc_ftim(IFC_CS3, IFC_FTIM3, CONFIG_SYS_CS3_FTIM3);
-
-	set_ifc_cspr(IFC_CS3, CONFIG_SYS_CSPR3);
-	set_ifc_amask(IFC_CS3, CONFIG_SYS_AMASK3);
-	set_ifc_csor(IFC_CS3, CONFIG_SYS_CSOR3);
-#endif
-
-#ifdef CONFIG_SYS_CSPR4_EXT
-	set_ifc_cspr_ext(IFC_CS4, CONFIG_SYS_CSPR4_EXT);
-#endif
-#if defined(CONFIG_SYS_CSPR4) && defined(CONFIG_SYS_CSOR4)
-	set_ifc_ftim(IFC_CS4, IFC_FTIM0, CONFIG_SYS_CS4_FTIM0);
-	set_ifc_ftim(IFC_CS4, IFC_FTIM1, CONFIG_SYS_CS4_FTIM1);
-	set_ifc_ftim(IFC_CS4, IFC_FTIM2, CONFIG_SYS_CS4_FTIM2);
-	set_ifc_ftim(IFC_CS4, IFC_FTIM3, CONFIG_SYS_CS4_FTIM3);
-
-	set_ifc_cspr(IFC_CS4, CONFIG_SYS_CSPR4);
-	set_ifc_amask(IFC_CS4, CONFIG_SYS_AMASK4);
-	set_ifc_csor(IFC_CS4, CONFIG_SYS_CSOR4);
-#endif
-
-#ifdef CONFIG_SYS_CSPR5_EXT
-	set_ifc_cspr_ext(IFC_CS5, CONFIG_SYS_CSPR5_EXT);
-#endif
-#if defined(CONFIG_SYS_CSPR5) && defined(CONFIG_SYS_CSOR5)
-	set_ifc_ftim(IFC_CS5, IFC_FTIM0, CONFIG_SYS_CS5_FTIM0);
-	set_ifc_ftim(IFC_CS5, IFC_FTIM1, CONFIG_SYS_CS5_FTIM1);
-	set_ifc_ftim(IFC_CS5, IFC_FTIM2, CONFIG_SYS_CS5_FTIM2);
-	set_ifc_ftim(IFC_CS5, IFC_FTIM3, CONFIG_SYS_CS5_FTIM3);
-
-	set_ifc_cspr(IFC_CS5, CONFIG_SYS_CSPR5);
-	set_ifc_amask(IFC_CS5, CONFIG_SYS_AMASK5);
-	set_ifc_csor(IFC_CS5, CONFIG_SYS_CSOR5);
-#endif
-
-#ifdef CONFIG_SYS_CSPR6_EXT
-	set_ifc_cspr_ext(IFC_CS6, CONFIG_SYS_CSPR6_EXT);
-#endif
-#if defined(CONFIG_SYS_CSPR6) && defined(CONFIG_SYS_CSOR6)
-	set_ifc_ftim(IFC_CS6, IFC_FTIM0, CONFIG_SYS_CS6_FTIM0);
-	set_ifc_ftim(IFC_CS6, IFC_FTIM1, CONFIG_SYS_CS6_FTIM1);
-	set_ifc_ftim(IFC_CS6, IFC_FTIM2, CONFIG_SYS_CS6_FTIM2);
-	set_ifc_ftim(IFC_CS6, IFC_FTIM3, CONFIG_SYS_CS6_FTIM3);
-
-	set_ifc_cspr(IFC_CS6, CONFIG_SYS_CSPR6);
-	set_ifc_amask(IFC_CS6, CONFIG_SYS_AMASK6);
-	set_ifc_csor(IFC_CS6, CONFIG_SYS_CSOR6);
-#endif
-
-#ifdef CONFIG_SYS_CSPR7_EXT
-	set_ifc_cspr_ext(IFC_CS7, CONFIG_SYS_CSPR7_EXT);
-#endif
-#if defined(CONFIG_SYS_CSPR7) && defined(CONFIG_SYS_CSOR7)
-	set_ifc_ftim(IFC_CS7, IFC_FTIM0, CONFIG_SYS_CS7_FTIM0);
-	set_ifc_ftim(IFC_CS7, IFC_FTIM1, CONFIG_SYS_CS7_FTIM1);
-	set_ifc_ftim(IFC_CS7, IFC_FTIM2, CONFIG_SYS_CS7_FTIM2);
-	set_ifc_ftim(IFC_CS7, IFC_FTIM3, CONFIG_SYS_CS7_FTIM3);
-
-	set_ifc_cspr(IFC_CS7, CONFIG_SYS_CSPR7);
-	set_ifc_amask(IFC_CS7, CONFIG_SYS_AMASK7);
-	set_ifc_csor(IFC_CS7, CONFIG_SYS_CSOR7);
-#endif
-}
diff --git a/arch/powerpc/cpu/ppc4xx/44x_spd_ddr2.c b/arch/powerpc/cpu/ppc4xx/44x_spd_ddr2.c
index fe928db039..f8d03cba2d 100644
--- a/arch/powerpc/cpu/ppc4xx/44x_spd_ddr2.c
+++ b/arch/powerpc/cpu/ppc4xx/44x_spd_ddr2.c
@@ -49,7 +49,6 @@
 		       "SDRAM_" #mnemonic, SDRAM_##mnemonic, data);	\
 	} while (0)
 
-#if !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
 static void update_rdcc(void)
 {
 	u32 val;
@@ -72,7 +71,6 @@ static void update_rdcc(void)
 		}
 	}
 }
-#endif
 
 #if defined(CONFIG_440)
 /*
@@ -101,7 +99,6 @@ void dcbz_area(u32 start_address, u32 num_bytes);
 
 #define MULDIV64(m1, m2, d)	(u32)(((u64)(m1) * (u64)(m2)) / (u64)(d))
 
-#if !defined(CONFIG_NAND_SPL)
 /*-----------------------------------------------------------------------------+
  * sdram_memsize
  *-----------------------------------------------------------------------------*/
@@ -217,7 +214,6 @@ void board_add_ram_info(int use_default)
 	val = (val & SDRAM_MMODE_DCL_MASK) >> 4;
 	printf(", CL%d)", val);
 }
-#endif /* !CONFIG_NAND_SPL */
 
 #if defined(CONFIG_SPD_EEPROM)
 
@@ -2843,16 +2839,6 @@ static void test(void)
  *---------------------------------------------------------------------------*/
 phys_size_t initdram(int board_type)
 {
-	/*
-	 * Only run this SDRAM init code once. For NAND booting
-	 * targets like Kilauea, we call initdram() early from the
-	 * 4k NAND booting image (CONFIG_NAND_SPL) from nand_boot().
-	 * Later on the NAND U-Boot image runs (CONFIG_NAND_U_BOOT)
-	 * which calls initdram() again. This time the controller
-	 * mustn't be reconfigured again since we're already running
-	 * from SDRAM.
-	 */
-#if !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
 	unsigned long val;
 
 #if defined(CONFIG_440)
@@ -2969,12 +2955,10 @@ phys_size_t initdram(int board_type)
 #endif
 
 #if defined(CONFIG_PPC4xx_DDR_AUTOCALIBRATION)
-#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
 	/*------------------------------------------------------------------
 	 | DQS calibration.
 	 +-----------------------------------------------------------------*/
 	DQS_autocalibration();
-#endif /* !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) */
 #endif /* CONFIG_PPC4xx_DDR_AUTOCALIBRATION */
 
 	/*
@@ -3009,13 +2993,10 @@ phys_size_t initdram(int board_type)
 	set_mcsr(get_mcsr());
 #endif /* CONFIG_PPC4xx_DDR_AUTOCALIBRATION */
 
-#endif /* !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL) */
-
 	return (CONFIG_SYS_MBYTES_SDRAM << 20);
 }
 #endif /* CONFIG_SPD_EEPROM */
 
-#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
 #if defined(CONFIG_440)
 u32 mfdcr_any(u32 dcr)
 {
@@ -3062,7 +3043,6 @@ void mtdcr_any(u32 dcr, u32 val)
 	}
 }
 #endif /* defined(CONFIG_440) */
-#endif /* !defined(CONFIG_NAND_U_BOOT) &&  !defined(CONFIG_NAND_SPL) */
 
 inline void ppc4xx_ibm_ddr2_register_dump(void)
 {
diff --git a/arch/powerpc/cpu/ppc4xx/4xx_ibm_ddr2_autocalib.c b/arch/powerpc/cpu/ppc4xx/4xx_ibm_ddr2_autocalib.c
index 82823147fe..67f149deef 100644
--- a/arch/powerpc/cpu/ppc4xx/4xx_ibm_ddr2_autocalib.c
+++ b/arch/powerpc/cpu/ppc4xx/4xx_ibm_ddr2_autocalib.c
@@ -27,12 +27,6 @@
 
 #include "ecc.h"
 
-/*
- * Only compile the DDR auto-calibration code for NOR boot and
- * not for NAND boot (NAND SPL and NAND U-Boot - NUB)
- */
-#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
-
 #define MAXBXCF			4
 #define SDRAM_RXBAS_SHIFT_1M	20
 
@@ -1231,9 +1225,3 @@ u32 DQS_autocalibration(void)
 
 	return 0;
 }
-#else /* defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL) */
-u32 DQS_autocalibration(void)
-{
-	return 0;
-}
-#endif /* !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) */
diff --git a/arch/powerpc/cpu/ppc4xx/Makefile b/arch/powerpc/cpu/ppc4xx/Makefile
index d38b4aa701..4b792ae2d2 100644
--- a/arch/powerpc/cpu/ppc4xx/Makefile
+++ b/arch/powerpc/cpu/ppc4xx/Makefile
@@ -5,71 +5,45 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(CPU).o
-
-START	:= resetvec.o
-START	+= start.o
-
-SOBJS	:= cache.o
-SOBJS	+= dcr.o
-SOBJS	+= kgdb.o
-
-COBJS	:= 40x_spd_sdram.o
-
-ifndef CONFIG_NAND_SPL
-ifndef CONFIG_NAND_U_BOOT
-COBJS	+= 44x_spd_ddr.o
-endif
-endif
-COBJS-$(CONFIG_SDRAM_PPC4xx_IBM_DDR2) += 44x_spd_ddr2.o
-COBJS-$(CONFIG_PPC4xx_DDR_AUTOCALIBRATION) += 4xx_ibm_ddr2_autocalib.o
-COBJS	+= 4xx_pci.o
-COBJS	+= 4xx_pcie.o
-COBJS	+= bedbug_405.o
-COBJS-$(CONFIG_CMD_CHIP_CONFIG)	+= cmd_chip_config.o
-COBJS	+= cpu.o
-COBJS	+= cpu_init.o
-COBJS	+= denali_data_eye.o
-COBJS	+= denali_spd_ddr2.o
-COBJS	+= ecc.o
-COBJS-$(CONFIG_CMD_ECCTEST) += cmd_ecctest.o
-COBJS	+= fdt.o
-COBJS	+= interrupts.o
-COBJS-$(CONFIG_CMD_REGINFO) += reginfo.o
-COBJS	+= sdram.o
-COBJS	+= speed.o
-COBJS	+= tlb.o
-COBJS	+= traps.o
-COBJS	+= usb.o
-COBJS	+= usb_ohci.o
-COBJS-$(CONFIG_XILINX_440) += xilinx_irq.o
+extra-y	:= resetvec.o
+extra-y	+= start.o
+
+obj-y	:= cache.o
+obj-y	+= dcr.o
+obj-y	+= kgdb.o
+
+obj-y	+= 40x_spd_sdram.o
+
+obj-y	+= 44x_spd_ddr.o
+obj-$(CONFIG_SDRAM_PPC4xx_IBM_DDR2) += 44x_spd_ddr2.o
+obj-$(CONFIG_PPC4xx_DDR_AUTOCALIBRATION) += 4xx_ibm_ddr2_autocalib.o
+obj-y	+= 4xx_pci.o
+obj-y	+= 4xx_pcie.o
+obj-y	+= bedbug_405.o
+obj-$(CONFIG_CMD_CHIP_CONFIG)	+= cmd_chip_config.o
+obj-y	+= cpu.o
+obj-y	+= cpu_init.o
+obj-y	+= denali_data_eye.o
+obj-y	+= denali_spd_ddr2.o
+obj-y	+= ecc.o
+obj-$(CONFIG_CMD_ECCTEST) += cmd_ecctest.o
+obj-y	+= fdt.o
+obj-y	+= interrupts.o
+obj-$(CONFIG_CMD_REGINFO) += reginfo.o
+obj-y	+= sdram.o
+obj-y	+= speed.o
+obj-y	+= tlb.o
+obj-y	+= traps.o
+obj-y	+= usb.o
+obj-y	+= usb_ohci.o
+obj-$(CONFIG_XILINX_440) += xilinx_irq.o
 ifndef CONFIG_XILINX_440
-COBJS	+= 4xx_uart.o
-COBJS	+= gpio.o
-COBJS	+= miiphy.o
-COBJS	+= uic.o
+obj-y	+= 4xx_uart.o
+obj-y	+= gpio.o
+obj-y	+= miiphy.o
+obj-y	+= uic.o
 endif
 
 ifdef CONFIG_SPL_BUILD
-COBJS-y += spl_boot.o
+obj-y += spl_boot.o
 endif
-
-SRCS	:= $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS) $(COBJS-y))
-START	:= $(addprefix $(obj),$(START))
-
-all:	$(obj).depend $(START) $(LIB)
-
-$(LIB):	$(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
diff --git a/arch/powerpc/cpu/ppc4xx/config.mk b/arch/powerpc/cpu/ppc4xx/config.mk
index c2b0f9aab6..102f069f9e 100644
--- a/arch/powerpc/cpu/ppc4xx/config.mk
+++ b/arch/powerpc/cpu/ppc4xx/config.mk
@@ -5,11 +5,10 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-PLATFORM_RELFLAGS += -meabi
-PLATFORM_CPPFLAGS += -DCONFIG_4xx -ffixed-r2 -mstring -msoft-float
+PLATFORM_CPPFLAGS += -DCONFIG_4xx -mstring -msoft-float
 
-cfg=$(shell grep configs $(OBJTREE)/include/config.h | sed 's/.*<\(configs.*\)>/\1/')
-is440:=$(shell grep CONFIG_440 $(TOPDIR)/include/$(cfg))
+cfg=$(shell grep configs $(objtree)/include/config.h | sed 's/.*<\(configs.*\)>/\1/')
+is440:=$(shell grep CONFIG_440 $(srctree)/include/$(cfg))
 
 ifneq (,$(findstring CONFIG_440,$(is440)))
 PLATFORM_CPPFLAGS += -Wa,-m440 -mcpu=440
diff --git a/arch/powerpc/cpu/ppc4xx/dcr.S b/arch/powerpc/cpu/ppc4xx/dcr.S
index 0d99391dfb..6b13528c9a 100644
--- a/arch/powerpc/cpu/ppc4xx/dcr.S
+++ b/arch/powerpc/cpu/ppc4xx/dcr.S
@@ -10,8 +10,6 @@
 
 #include <asm/ppc4xx.h>
 
-#define _LINUX_CONFIG_H 1       /* avoid reading Linux autoconf.h file  */
-
 #include <ppc_asm.tmpl>
 #include <ppc_defs.h>
 
diff --git a/arch/powerpc/cpu/ppc4xx/kgdb.S b/arch/powerpc/cpu/ppc4xx/kgdb.S
index dbc4a6c881..f274c5d564 100644
--- a/arch/powerpc/cpu/ppc4xx/kgdb.S
+++ b/arch/powerpc/cpu/ppc4xx/kgdb.S
@@ -10,7 +10,6 @@
 #include <version.h>
 
 #define CONFIG_405GP 1		/* needed for Linux kernel header files */
-#define _LINUX_CONFIG_H 1	/* avoid reading Linux autoconf.h file	*/
 
 #include <ppc_asm.tmpl>
 #include <ppc_defs.h>
diff --git a/arch/powerpc/cpu/ppc4xx/start.S b/arch/powerpc/cpu/ppc4xx/start.S
index 38bbc5a9bc..11b55d5a56 100644
--- a/arch/powerpc/cpu/ppc4xx/start.S
+++ b/arch/powerpc/cpu/ppc4xx/start.S
@@ -31,8 +31,6 @@
 #include <asm/ppc4xx.h>
 #include <version.h>
 
-#define _LINUX_CONFIG_H 1	/* avoid reading Linux autoconf.h file	*/
-
 #include <ppc_asm.tmpl>
 #include <ppc_defs.h>
 
@@ -184,16 +182,13 @@
 
 
 	.extern ext_bus_cntlr_init
-#ifdef CONFIG_NAND_U_BOOT
-	.extern reconfig_tlb0
-#endif
 
 /*
  * Set up GOT: Global Offset Table
  *
  * Use r12 to access the GOT
  */
-#if !defined(CONFIG_NAND_SPL) && !defined(CONFIG_SPL_BUILD)
+#if !defined(CONFIG_SPL_BUILD)
 	START_GOT
 	GOT_ENTRY(_GOT2_TABLE_)
 	GOT_ENTRY(_FIXUP_TABLE_)
@@ -207,22 +202,7 @@
 	GOT_ENTRY(__bss_end)
 	GOT_ENTRY(__bss_start)
 	END_GOT
-#endif /* CONFIG_NAND_SPL */
-
-#if defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) && \
-	!defined(CONFIG_SPL_BUILD)
-	/*
-	 * NAND U-Boot image is started from offset 0
-	 */
-	.text
-#if defined(CONFIG_440)
-	bl	reconfig_tlb0
-#endif
-	GET_GOT
-	bl	cpu_init_f	/* run low-level CPU init code	   (from Flash) */
-	bl	board_init_f
-	/* NOTREACHED - board_init_f() does not return */
-#endif
+#endif /* CONFIG_SPL_BUILD */
 
 #if defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_BOOT_FROM_XMD)
 	/*
@@ -257,9 +237,7 @@
  */
 
 #if defined(CONFIG_440)
-#if !defined(CONFIG_NAND_SPL)
     .section .bootpg,"ax"
-#endif
     .globl _start_440
 
 /**************************************************************************/
@@ -513,7 +491,7 @@ tlbnx2:	addi	r4,r4,1		/* Next TLB */
  * r3 - 1st arg to board_init(): IMMP pointer
  * r4 - 2nd arg to board_init(): boot flag
  */
-#if !defined(CONFIG_NAND_SPL) && !defined(CONFIG_SPL_BUILD)
+#if !defined(CONFIG_SPL_BUILD)
 	.text
 	.long	0x27051956		/* U-Boot Magic Number			*/
 	.globl	version_string
@@ -779,9 +757,6 @@ _start:
 	stwu	r1,-8(r1)		/* Save back chain and move SP */
 	stw	r0,+12(r1)		/* Save return addr (underflow vect) */
 
-#ifdef CONFIG_NAND_SPL
-	bl	nand_boot_common	/* will not return */
-#else
 #ifndef CONFIG_SPL_BUILD
 	GET_GOT
 #endif
@@ -789,7 +764,6 @@ _start:
 	bl	cpu_init_f	/* run low-level CPU init code	   (from Flash) */
 	bl	board_init_f
 	/* NOTREACHED - board_init_f() does not return */
-#endif
 
 #endif /* CONFIG_440 */
 
@@ -1052,9 +1026,6 @@ _start:
 	stw	r0, +12(r1)		/* Save return addr (underflow vect) */
 #endif /* CONFIG_SYS_INIT_DCACHE_CS */
 
-#ifdef CONFIG_NAND_SPL
-	bl	nand_boot_common	/* will not return */
-#else
 	GET_GOT			/* initialize GOT access			*/
 
 	bl	cpu_init_f	/* run low-level CPU init code	   (from Flash) */
@@ -1062,13 +1033,11 @@ _start:
 	bl	board_init_f	/* run first part of init code (from Flash)	*/
 	/* NOTREACHED - board_init_f() does not return */
 
-#endif /* CONFIG_NAND_SPL */
-
 #endif	/* CONFIG_405GP || CONFIG_405 || CONFIG_405EP */
 	/*----------------------------------------------------------------------- */
 
 
-#if !defined(CONFIG_NAND_SPL) && !defined(CONFIG_SPL_BUILD)
+#if !defined(CONFIG_SPL_BUILD)
 /*
  * This code finishes saving the registers to the exception frame
  * and jumps to the appropriate handler for the exception.
@@ -1634,7 +1603,7 @@ __440_msr_continue:
 	blr
 	function_epilog(dcbz_area)
 #endif /* CONFIG_440 */
-#endif /* CONFIG_NAND_SPL */
+#endif /* CONFIG_SPL_BUILD */
 
 /*------------------------------------------------------------------------------- */
 /* Function:	 in8 */
@@ -1983,75 +1952,3 @@ pll_wait:
 	blr
 	function_epilog(mftlb1)
 #endif /* CONFIG_440 */
-
-#if defined(CONFIG_NAND_SPL)
-/*
- * void nand_boot_relocate(dst, src, bytes)
- *
- * r3 = Destination address to copy code to (in SDRAM)
- * r4 = Source address to copy code from
- * r5 = size to copy in bytes
- */
-nand_boot_relocate:
-	mr	r6,r3
-	mr	r7,r4
-	mflr	r8
-
-	/*
-	 * Copy SPL from icache into SDRAM
-	 */
-	subi	r3,r3,4
-	subi	r4,r4,4
-	srwi	r5,r5,2
-	mtctr	r5
-..spl_loop:
-	lwzu	r0,4(r4)
-	stwu	r0,4(r3)
-	bdnz	..spl_loop
-
-	/*
-	 * Calculate "corrected" link register, so that we "continue"
-	 * in execution in destination range
-	 */
-	sub	r3,r7,r6	/* r3 = src - dst */
-	sub	r8,r8,r3	/* r8 = link-reg - (src - dst) */
-	mtlr	r8
-	blr
-
-nand_boot_common:
-	/*
-	 * First initialize SDRAM. It has to be available *before* calling
-	 * nand_boot().
-	 */
-	lis	r3,CONFIG_SYS_SDRAM_BASE@h
-	ori	r3,r3,CONFIG_SYS_SDRAM_BASE@l
-	bl	initdram
-
-	/*
-	 * Now copy the 4k SPL code into SDRAM and continue execution
-	 * from there.
-	 */
-	lis	r3,CONFIG_SYS_NAND_BOOT_SPL_DST@h
-	ori	r3,r3,CONFIG_SYS_NAND_BOOT_SPL_DST@l
-	lis	r4,CONFIG_SYS_NAND_BOOT_SPL_SRC@h
-	ori	r4,r4,CONFIG_SYS_NAND_BOOT_SPL_SRC@l
-	lis	r5,CONFIG_SYS_NAND_BOOT_SPL_SIZE@h
-	ori	r5,r5,CONFIG_SYS_NAND_BOOT_SPL_SIZE@l
-	bl	nand_boot_relocate
-
-	/*
-	 * We're running from SDRAM now!!!
-	 *
-	 * It is necessary for 4xx systems to relocate from running at
-	 * the original location (0xfffffxxx) to somewhere else (SDRAM
-	 * preferably). This is because CS0 needs to be reconfigured for
-	 * NAND access. And we can't reconfigure this CS when currently
-	 * "running" from it.
-	 */
-
-	/*
-	 * Finally call nand_boot() to load main NAND U-Boot image from
-	 * NAND and jump to it.
-	 */
-	bl	nand_boot		/* will not return */
-#endif /* CONFIG_NAND_SPL */
diff --git a/arch/powerpc/cpu/ppc4xx/usb_ohci.c b/arch/powerpc/cpu/ppc4xx/usb_ohci.c
index b371a752f9..d1e78f6b0c 100644
--- a/arch/powerpc/cpu/ppc4xx/usb_ohci.c
+++ b/arch/powerpc/cpu/ppc4xx/usb_ohci.c
@@ -847,104 +847,7 @@ static int dl_done_list (ohci_t *ohci, td_t *td_list)
  * Virtual Root Hub
  *-------------------------------------------------------------------------*/
 
-/* Device descriptor */
-static __u8 root_hub_dev_des[] =
-{
-	0x12,	    /*	__u8  bLength; */
-	0x01,	    /*	__u8  bDescriptorType; Device */
-	0x10,	    /*	__u16 bcdUSB; v1.1 */
-	0x01,
-	0x09,	    /*	__u8  bDeviceClass; HUB_CLASSCODE */
-	0x00,	    /*	__u8  bDeviceSubClass; */
-	0x00,	    /*	__u8  bDeviceProtocol; */
-	0x08,	    /*	__u8  bMaxPacketSize0; 8 Bytes */
-	0x00,	    /*	__u16 idVendor; */
-	0x00,
-	0x00,	    /*	__u16 idProduct; */
-	0x00,
-	0x00,	    /*	__u16 bcdDevice; */
-	0x00,
-	0x00,	    /*	__u8  iManufacturer; */
-	0x01,	    /*	__u8  iProduct; */
-	0x00,	    /*	__u8  iSerialNumber; */
-	0x01	    /*	__u8  bNumConfigurations; */
-};
-
-
-/* Configuration descriptor */
-static __u8 root_hub_config_des[] =
-{
-	0x09,	    /*	__u8  bLength; */
-	0x02,	    /*	__u8  bDescriptorType; Configuration */
-	0x19,	    /*	__u16 wTotalLength; */
-	0x00,
-	0x01,	    /*	__u8  bNumInterfaces; */
-	0x01,	    /*	__u8  bConfigurationValue; */
-	0x00,	    /*	__u8  iConfiguration; */
-	0x40,	    /*	__u8  bmAttributes;
-		 Bit 7: Bus-powered, 6: Self-powered, 5 Remote-wakwup, 4..0: resvd */
-	0x00,	    /*	__u8  MaxPower; */
-
-	/* interface */
-	0x09,	    /*	__u8  if_bLength; */
-	0x04,	    /*	__u8  if_bDescriptorType; Interface */
-	0x00,	    /*	__u8  if_bInterfaceNumber; */
-	0x00,	    /*	__u8  if_bAlternateSetting; */
-	0x01,	    /*	__u8  if_bNumEndpoints; */
-	0x09,	    /*	__u8  if_bInterfaceClass; HUB_CLASSCODE */
-	0x00,	    /*	__u8  if_bInterfaceSubClass; */
-	0x00,	    /*	__u8  if_bInterfaceProtocol; */
-	0x00,	    /*	__u8  if_iInterface; */
-
-	/* endpoint */
-	0x07,	    /*	__u8  ep_bLength; */
-	0x05,	    /*	__u8  ep_bDescriptorType; Endpoint */
-	0x81,	    /*	__u8  ep_bEndpointAddress; IN Endpoint 1 */
-	0x03,	    /*	__u8  ep_bmAttributes; Interrupt */
-	0x02,	    /*	__u16 ep_wMaxPacketSize; ((MAX_ROOT_PORTS + 1) / 8 */
-	0x00,
-	0xff	    /*	__u8  ep_bInterval; 255 ms */
-};
-
-static unsigned char root_hub_str_index0[] =
-{
-	0x04,			/*  __u8  bLength; */
-	0x03,			/*  __u8  bDescriptorType; String-descriptor */
-	0x09,			/*  __u8  lang ID */
-	0x04,			/*  __u8  lang ID */
-};
-
-static unsigned char root_hub_str_index1[] =
-{
-	28,			/*  __u8  bLength; */
-	0x03,			/*  __u8  bDescriptorType; String-descriptor */
-	'O',			/*  __u8  Unicode */
-	0,				/*  __u8  Unicode */
-	'H',			/*  __u8  Unicode */
-	0,				/*  __u8  Unicode */
-	'C',			/*  __u8  Unicode */
-	0,				/*  __u8  Unicode */
-	'I',			/*  __u8  Unicode */
-	0,				/*  __u8  Unicode */
-	' ',			/*  __u8  Unicode */
-	0,				/*  __u8  Unicode */
-	'R',			/*  __u8  Unicode */
-	0,				/*  __u8  Unicode */
-	'o',			/*  __u8  Unicode */
-	0,				/*  __u8  Unicode */
-	'o',			/*  __u8  Unicode */
-	0,				/*  __u8  Unicode */
-	't',			/*  __u8  Unicode */
-	0,				/*  __u8  Unicode */
-	' ',			/*  __u8  Unicode */
-	0,				/*  __u8  Unicode */
-	'H',			/*  __u8  Unicode */
-	0,				/*  __u8  Unicode */
-	'u',			/*  __u8  Unicode */
-	0,				/*  __u8  Unicode */
-	'b',			/*  __u8  Unicode */
-	0,				/*  __u8  Unicode */
-};
+#include <usbroothubdes.h>
 
 /* Hub class-specific descriptor is constructed dynamically */
 
@@ -1549,7 +1452,7 @@ static void hc_release_ohci (ohci_t *ohci)
  */
 static char ohci_inited = 0;
 
-int usb_lowlevel_init(int index, void **controller)
+int usb_lowlevel_init(int index, enum usb_init_type init, void **controller)
 {
 	memset (&gohci, 0, sizeof (ohci_t));
 	memset (&urb_priv, 0, sizeof (urb_priv_t));
diff --git a/arch/powerpc/include/asm/8xx_immap.h b/arch/powerpc/include/asm/8xx_immap.h
index 01129ed4f0..dfaddb6f1d 100644
--- a/arch/powerpc/include/asm/8xx_immap.h
+++ b/arch/powerpc/include/asm/8xx_immap.h
@@ -1,4 +1,3 @@
-
 /*
  * MPC8xx Internal Memory Map
  * Copyright (c) 1997 Dan Malek (dmalek@jlc.net)
diff --git a/arch/powerpc/include/asm/atomic.h b/arch/powerpc/include/asm/atomic.h
index 23f22df1b7..43a2bb2b3e 100644
--- a/arch/powerpc/include/asm/atomic.h
+++ b/arch/powerpc/include/asm/atomic.h
@@ -5,8 +5,6 @@
 #ifndef _ASM_PPC_ATOMIC_H_
 #define _ASM_PPC_ATOMIC_H_
 
-#include <linux/config.h>
-
 #ifdef CONFIG_SMP
 typedef struct { volatile int counter; } atomic_t;
 #else
diff --git a/arch/powerpc/include/asm/bitops.h b/arch/powerpc/include/asm/bitops.h
index adaf091492..a6bcf3c3fe 100644
--- a/arch/powerpc/include/asm/bitops.h
+++ b/arch/powerpc/include/asm/bitops.h
@@ -5,7 +5,6 @@
 #ifndef _PPC_BITOPS_H
 #define _PPC_BITOPS_H
 
-#include <linux/config.h>
 #include <asm/byteorder.h>
 
 extern void set_bit(int nr, volatile void *addr);
diff --git a/arch/powerpc/include/asm/cache.h b/arch/powerpc/include/asm/cache.h
index 5f9c640aa2..cdc1f10872 100644
--- a/arch/powerpc/include/asm/cache.h
+++ b/arch/powerpc/include/asm/cache.h
@@ -4,7 +4,6 @@
 #ifndef __ARCH_PPC_CACHE_H
 #define __ARCH_PPC_CACHE_H
 
-#include <linux/config.h>
 #include <asm/processor.h>
 
 /* bytes per L1 cache line */
diff --git a/arch/powerpc/include/asm/config.h b/arch/powerpc/include/asm/config.h
index 3c17c99146..423a6fb8dc 100644
--- a/arch/powerpc/include/asm/config.h
+++ b/arch/powerpc/include/asm/config.h
@@ -9,10 +9,16 @@
 
 #ifdef CONFIG_MPC85xx
 #include <asm/config_mpc85xx.h>
+#define CONFIG_SYS_FSL_DDR
 #endif
 
 #ifdef CONFIG_MPC86xx
 #include <asm/config_mpc86xx.h>
+#define CONFIG_SYS_FSL_DDR
+#endif
+
+#ifdef CONFIG_MPC83xx
+#define CONFIG_SYS_FSL_DDR
 #endif
 
 #ifndef HWCONFIG_BUFFER_SIZE
diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h
index bec8966fde..df44451091 100644
--- a/arch/powerpc/include/asm/config_mpc85xx.h
+++ b/arch/powerpc/include/asm/config_mpc85xx.h
@@ -20,6 +20,10 @@
 #define CONFIG_PPC_SPINTABLE_COMPATIBLE
 
 #define FSL_DDR_VER_4_7	47
+#define FSL_DDR_VER_5_0	50
+
+/* IP endianness */
+#define CONFIG_SYS_FSL_IFC_BE
 
 /* Number of TLB CAM entries we have on FSL Book-E chips */
 #if defined(CONFIG_E500MC)
@@ -39,17 +43,20 @@
 #elif defined(CONFIG_MPC8540)
 #define CONFIG_MAX_CPUS			1
 #define CONFIG_SYS_FSL_NUM_LAWS		8
+#define CONFIG_SYS_FSL_DDRC_GEN1
 #define CONFIG_SYS_CCSRBAR_DEFAULT	0xff700000
 
 #elif defined(CONFIG_MPC8541)
 #define CONFIG_MAX_CPUS			1
 #define CONFIG_SYS_FSL_NUM_LAWS		8
+#define CONFIG_SYS_FSL_DDRC_GEN1
 #define CONFIG_SYS_FSL_SEC_COMPAT	2
 #define CONFIG_SYS_CCSRBAR_DEFAULT	0xff700000
 
 #elif defined(CONFIG_MPC8544)
 #define CONFIG_MAX_CPUS			1
 #define CONFIG_SYS_FSL_NUM_LAWS		10
+#define CONFIG_SYS_FSL_DDRC_GEN2
 #define CONFIG_SYS_PPC_E500_DEBUG_TLB	0
 #define CONFIG_SYS_FSL_SEC_COMPAT	2
 #define CONFIG_SYS_CCSRBAR_DEFAULT	0xff700000
@@ -58,6 +65,7 @@
 #elif defined(CONFIG_MPC8548)
 #define CONFIG_MAX_CPUS			1
 #define CONFIG_SYS_FSL_NUM_LAWS		10
+#define CONFIG_SYS_FSL_DDRC_GEN2
 #define CONFIG_SYS_PPC_E500_DEBUG_TLB	0
 #define CONFIG_SYS_FSL_SEC_COMPAT	2
 #define CONFIG_SYS_CCSRBAR_DEFAULT	0xff700000
@@ -76,17 +84,20 @@
 #elif defined(CONFIG_MPC8555)
 #define CONFIG_MAX_CPUS			1
 #define CONFIG_SYS_FSL_NUM_LAWS		8
+#define CONFIG_SYS_FSL_DDRC_GEN1
 #define CONFIG_SYS_FSL_SEC_COMPAT	2
 #define CONFIG_SYS_CCSRBAR_DEFAULT	0xff700000
 
 #elif defined(CONFIG_MPC8560)
 #define CONFIG_MAX_CPUS			1
 #define CONFIG_SYS_FSL_NUM_LAWS		8
+#define CONFIG_SYS_FSL_DDRC_GEN1
 #define CONFIG_SYS_CCSRBAR_DEFAULT	0xff700000
 
 #elif defined(CONFIG_MPC8568)
 #define CONFIG_MAX_CPUS			1
 #define CONFIG_SYS_FSL_NUM_LAWS		10
+#define CONFIG_SYS_FSL_DDRC_GEN2
 #define CONFIG_SYS_FSL_SEC_COMPAT	2
 #define QE_MURAM_SIZE			0x10000UL
 #define MAX_QE_RISC			2
@@ -132,6 +143,7 @@
 #define CONFIG_SYS_FSL_SEC_COMPAT	4
 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
 #define CONFIG_NUM_DDR_CONTROLLERS	1
+#define CONFIG_USB_MAX_CONTROLLER_COUNT	1
 #define CONFIG_SYS_FSL_IFC_BANK_COUNT	4
 #define CONFIG_SYS_CCSRBAR_DEFAULT	0xff700000
 #define CONFIG_SYS_FSL_PCIE_COMPAT	"fsl,qoriq-pcie-v2.2"
@@ -142,7 +154,9 @@
 #define CONFIG_SYS_FSL_ERRATUM_IFC_A003399
 #define CONFIG_SYS_FSL_ERRATUM_A005125
 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
+#define CONFIG_SYS_FSL_ERRATUM_A006261
 #define CONFIG_SYS_FSL_A004447_SVR_REV	0x10
+#define CONFIG_ESDHC_HC_BLK_ADDR
 
 /* P1011 is single core version of P1020 */
 #elif defined(CONFIG_P1011)
@@ -152,6 +166,7 @@
 #define CONFIG_TSECV2
 #define CONFIG_FSL_PCIE_DISABLE_ASPM
 #define CONFIG_SYS_FSL_SEC_COMPAT	2
+#define CONFIG_USB_MAX_CONTROLLER_COUNT	2
 #define CONFIG_SYS_CCSRBAR_DEFAULT	0xff700000
 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
@@ -161,6 +176,7 @@
 #elif defined(CONFIG_P1012)
 #define CONFIG_MAX_CPUS			1
 #define CONFIG_SYS_FSL_NUM_LAWS		12
+#define CONFIG_USB_MAX_CONTROLLER_COUNT	2
 #define CONFIG_SYS_PPC_E500_DEBUG_TLB	2
 #define CONFIG_TSECV2
 #define CONFIG_FSL_PCIE_DISABLE_ASPM
@@ -177,6 +193,7 @@
 #elif defined(CONFIG_P1013)
 #define CONFIG_MAX_CPUS			1
 #define CONFIG_SYS_FSL_NUM_LAWS		12
+#define CONFIG_USB_MAX_CONTROLLER_COUNT	2
 #define CONFIG_SYS_PPC_E500_DEBUG_TLB	2
 #define CONFIG_TSECV2
 #define CONFIG_SYS_FSL_SEC_COMPAT	2
@@ -195,6 +212,7 @@
 #define CONFIG_SYS_FSL_SEC_COMPAT	4
 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
 #define CONFIG_NUM_DDR_CONTROLLERS	1
+#define CONFIG_USB_MAX_CONTROLLER_COUNT	1
 #define CONFIG_SYS_CCSRBAR_DEFAULT	0xff700000
 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
 #define CONFIG_SYS_FSL_ERRATUM_IFC_A002769
@@ -209,6 +227,7 @@
 #define CONFIG_SYS_NUM_FMAN		1
 #define CONFIG_SYS_NUM_FM1_DTSEC	2
 #define CONFIG_NUM_DDR_CONTROLLERS	1
+#define CONFIG_USB_MAX_CONTROLLER_COUNT	1
 #define CONFIG_SYS_QMAN_NUM_PORTALS	3
 #define CONFIG_SYS_BMAN_NUM_PORTALS	3
 #define CONFIG_SYS_FM_MURAM_SIZE	0x10000
@@ -227,6 +246,7 @@
 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
 #define CONFIG_SYS_FSL_ERRATUM_A005125
+#define CONFIG_USB_MAX_CONTROLLER_COUNT	2
 
 #elif defined(CONFIG_P1021)
 #define CONFIG_MAX_CPUS			2
@@ -242,6 +262,7 @@
 #define MAX_QE_RISC			1
 #define QE_NUM_OF_SNUM			28
 #define CONFIG_SYS_FSL_ERRATUM_A005125
+#define CONFIG_USB_MAX_CONTROLLER_COUNT	1
 
 #elif defined(CONFIG_P1022)
 #define CONFIG_MAX_CPUS			2
@@ -249,6 +270,7 @@
 #define CONFIG_SYS_PPC_E500_DEBUG_TLB	2
 #define CONFIG_TSECV2
 #define CONFIG_SYS_FSL_SEC_COMPAT	2
+#define CONFIG_USB_MAX_CONTROLLER_COUNT	2
 #define CONFIG_SYS_CCSRBAR_DEFAULT	0xff700000
 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
@@ -262,6 +284,7 @@
 #define CONFIG_SYS_NUM_FMAN		1
 #define CONFIG_SYS_NUM_FM1_DTSEC	2
 #define CONFIG_NUM_DDR_CONTROLLERS	1
+#define CONFIG_USB_MAX_CONTROLLER_COUNT	1
 #define CONFIG_SYS_QMAN_NUM_PORTALS	3
 #define CONFIG_SYS_BMAN_NUM_PORTALS	3
 #define CONFIG_SYS_FM_MURAM_SIZE	0x10000
@@ -279,6 +302,7 @@
 #define CONFIG_TSECV2
 #define CONFIG_FSL_PCIE_DISABLE_ASPM
 #define CONFIG_SYS_FSL_SEC_COMPAT	2
+#define CONFIG_USB_MAX_CONTROLLER_COUNT	2
 #define CONFIG_SYS_CCSRBAR_DEFAULT	0xff700000
 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
@@ -288,6 +312,7 @@
 #elif defined(CONFIG_P1025)
 #define CONFIG_MAX_CPUS			2
 #define CONFIG_SYS_FSL_NUM_LAWS		12
+#define CONFIG_USB_MAX_CONTROLLER_COUNT	2
 #define CONFIG_SYS_PPC_E500_DEBUG_TLB	2
 #define CONFIG_TSECV2
 #define CONFIG_FSL_PCIE_DISABLE_ASPM
@@ -306,6 +331,7 @@
 #define CONFIG_SYS_FSL_NUM_LAWS		12
 #define CONFIG_SYS_PPC_E500_DEBUG_TLB	2
 #define CONFIG_SYS_FSL_SEC_COMPAT	2
+#define CONFIG_USB_MAX_CONTROLLER_COUNT	1
 #define CONFIG_SYS_CCSRBAR_DEFAULT	0xff700000
 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
 #define CONFIG_SYS_FSL_ERRATUM_ESDHC_A001
@@ -325,7 +351,7 @@
 #define CONFIG_SYS_FSL_RMU
 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM	2
 #define CONFIG_SYS_FSL_ERRATUM_A005125
-
+#define CONFIG_USB_MAX_CONTROLLER_COUNT	1
 #elif defined(CONFIG_PPC_P2041) /* also supports P2040 */
 #define CONFIG_SYS_FSL_QORIQ_CHASSIS1
 #define CONFIG_FSL_CORENET		/* Freescale CoreNet platform */
@@ -337,6 +363,7 @@
 #define CONFIG_SYS_NUM_FM1_DTSEC	5
 #define CONFIG_SYS_NUM_FM1_10GEC	1
 #define CONFIG_NUM_DDR_CONTROLLERS	1
+#define CONFIG_USB_MAX_CONTROLLER_COUNT	2
 #define CONFIG_SYS_FM_MURAM_SIZE	0x28000
 #define CONFIG_SYS_FSL_TBCLK_DIV	32
 #define CONFIG_SYS_FSL_PCIE_COMPAT	"fsl,qoriq-pcie-v2.2"
@@ -360,6 +387,7 @@
 #define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034
 #define CONFIG_SYS_FSL_ERRATUM_A004849
 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
+#define CONFIG_SYS_FSL_ERRATUM_A006261
 #define CONFIG_SYS_FSL_A004447_SVR_REV	0x11
 
 #elif defined(CONFIG_PPC_P3041)
@@ -380,6 +408,7 @@
 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE
 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE
 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
+#define CONFIG_USB_MAX_CONTROLLER_COUNT	2
 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
 #define CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011
 #define CONFIG_SYS_FSL_ERRATUM_USB14
@@ -397,6 +426,7 @@
 #define CONFIG_SYS_FSL_ERRATUM_A004849
 #define CONFIG_SYS_FSL_ERRATUM_A005812
 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
+#define CONFIG_SYS_FSL_ERRATUM_A006261
 #define CONFIG_SYS_FSL_A004447_SVR_REV	0x20
 
 #elif defined(CONFIG_PPC_P4080) /* also supports P4040 */
@@ -412,6 +442,7 @@
 #define CONFIG_SYS_NUM_FM1_10GEC	1
 #define CONFIG_SYS_NUM_FM2_10GEC	1
 #define CONFIG_NUM_DDR_CONTROLLERS	2
+#define CONFIG_USB_MAX_CONTROLLER_COUNT	2
 #define CONFIG_SYS_FM_MURAM_SIZE	0x28000
 #define CONFIG_SYS_FSL_TBCLK_DIV	16
 #define CONFIG_SYS_FSL_PCIE_COMPAT	"fsl,p4080-pcie"
@@ -459,6 +490,7 @@
 #define CONFIG_SYS_NUM_FM1_DTSEC	5
 #define CONFIG_SYS_NUM_FM1_10GEC	1
 #define CONFIG_NUM_DDR_CONTROLLERS	2
+#define CONFIG_USB_MAX_CONTROLLER_COUNT	2
 #define CONFIG_SYS_FM_MURAM_SIZE	0x28000
 #define CONFIG_SYS_FSL_TBCLK_DIV	32
 #define CONFIG_SYS_FSL_PCIE_COMPAT	"fsl,qoriq-pcie-v2.2"
@@ -478,6 +510,7 @@
 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xc0000000
 #define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034
 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
+#define CONFIG_SYS_FSL_ERRATUM_A006261
 #define CONFIG_SYS_FSL_A004447_SVR_REV	0x20
 
 #elif defined(CONFIG_PPC_P5040)
@@ -494,6 +527,7 @@
 #define CONFIG_SYS_NUM_FM2_DTSEC	5
 #define CONFIG_SYS_NUM_FM2_10GEC	1
 #define CONFIG_NUM_DDR_CONTROLLERS	2
+#define CONFIG_USB_MAX_CONTROLLER_COUNT	2
 #define CONFIG_SYS_FM_MURAM_SIZE	0x28000
 #define CONFIG_SYS_FSL_TBCLK_DIV	16
 #define CONFIG_SYS_FSL_PCIE_COMPAT	"fsl,qoriq-pcie-v2.4"
@@ -508,6 +542,7 @@
 #define CONFIG_SYS_FSL_ERRATUM_A004699
 #define CONFIG_SYS_FSL_ERRATUM_A004510
 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV	0x10
+#define CONFIG_SYS_FSL_ERRATUM_A006261
 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
 #define CONFIG_SYS_FSL_ERRATUM_A005812
 
@@ -518,6 +553,7 @@
 #define CONFIG_TSECV2
 #define CONFIG_SYS_FSL_SEC_COMPAT	4
 #define CONFIG_NUM_DDR_CONTROLLERS	1
+#define CONFIG_USB_MAX_CONTROLLER_COUNT	1
 #define CONFIG_SYS_FSL_DSP_M2_RAM_ADDR	0xb0000000
 #define CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT	0xff600000
 #define CONFIG_SYS_FSL_IFC_BANK_COUNT	3
@@ -525,6 +561,7 @@
 #define CONFIG_NAND_FSL_IFC
 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
 #define CONFIG_SYS_FSL_ERRATUM_A005125
+#define CONFIG_ESDHC_HC_BLK_ADDR
 
 #elif defined(CONFIG_BSC9132)
 #define CONFIG_MAX_CPUS			2
@@ -534,6 +571,7 @@
 #define CONFIG_TSECV2
 #define CONFIG_SYS_FSL_SEC_COMPAT	4
 #define CONFIG_NUM_DDR_CONTROLLERS	2
+#define CONFIG_USB_MAX_CONTROLLER_COUNT	1
 #define CONFIG_SYS_FSL_DSP_DDR_ADDR	0x40000000
 #define CONFIG_SYS_FSL_DSP_M2_RAM_ADDR	0xb0000000
 #define CONFIG_SYS_FSL_DSP_M3_RAM_ADDR	0xc0000000
@@ -547,6 +585,7 @@
 #define CONFIG_SYS_FSL_ERRATUM_A005125
 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
 #define CONFIG_SYS_FSL_A004447_SVR_REV	0x11
+#define CONFIG_ESDHC_HC_BLK_ADDR
 
 #elif defined(CONFIG_PPC_T4240) || defined(CONFIG_PPC_T4160)
 #define CONFIG_E6500
@@ -557,6 +596,7 @@
 #define CONFIG_SYS_FSL_QMAN_V3		/* QMAN version 3 */
 #ifdef CONFIG_PPC_T4240
 #define CONFIG_MAX_CPUS			12
+#define CONFIG_SYS_FSL_CLUSTER_CLOCKS   { 1, 1, 4 }
 #define CONFIG_SYS_NUM_FM1_DTSEC	8
 #define CONFIG_SYS_NUM_FM1_10GEC	2
 #define CONFIG_SYS_NUM_FM2_DTSEC	8
@@ -564,6 +604,7 @@
 #define CONFIG_NUM_DDR_CONTROLLERS	3
 #else
 #define CONFIG_MAX_CPUS			8
+#define CONFIG_SYS_FSL_CLUSTER_CLOCKS   { 1, 1 }
 #define CONFIG_SYS_NUM_FM1_DTSEC	7
 #define CONFIG_SYS_NUM_FM1_10GEC	1
 #define CONFIG_SYS_NUM_FM2_DTSEC	7
@@ -578,9 +619,13 @@
 #define CONFIG_SYS_FSL_SRDS_4
 #define CONFIG_SYS_FSL_SEC_COMPAT	4
 #define CONFIG_SYS_NUM_FMAN		2
+#define CONFIG_USB_MAX_CONTROLLER_COUNT	2
+#define CONFIG_SYS_PME_CLK		0
 #define CONFIG_SYS_FSL_DDR_VER		FSL_DDR_VER_4_7
 #define CONFIG_SYS_FSL_IFC_BANK_COUNT	8
 #define CONFIG_SYS_FMAN_V3
+#define CONFIG_SYS_FM1_CLK		3
+#define CONFIG_SYS_FM2_CLK		3
 #define CONFIG_SYS_FM_MURAM_SIZE	0x60000
 #define CONFIG_SYS_FSL_TBCLK_DIV	16
 #define CONFIG_SYS_FSL_PCIE_COMPAT	"fsl,qoriq-pcie-v3.0"
@@ -593,6 +638,8 @@
 #define CONFIG_SYS_FSL_ERRATUM_A004468
 #define CONFIG_SYS_FSL_ERRATUM_A_004934
 #define CONFIG_SYS_FSL_ERRATUM_A005871
+#define CONFIG_SYS_FSL_ERRATUM_A006261
+#define CONFIG_SYS_FSL_ERRATUM_A006379
 #define CONFIG_SYS_FSL_ERRATUM_A006593
 #define CONFIG_SYS_CCSRBAR_DEFAULT	0xfe000000
 #define CONFIG_SYS_FSL_PCI_VER_3_X
@@ -608,6 +655,8 @@
 #define CONFIG_SYS_FSL_SRDS_2
 #define CONFIG_SYS_FSL_SEC_COMPAT	4
 #define CONFIG_SYS_NUM_FMAN		1
+#define CONFIG_USB_MAX_CONTROLLER_COUNT	1
+#define CONFIG_SYS_FM1_CLK		0
 #define CONFIG_SYS_FSL_DDR_VER		FSL_DDR_VER_4_7
 #define CONFIG_SYS_FSL_IFC_BANK_COUNT	4
 #define CONFIG_SYS_FMAN_V3
@@ -617,55 +666,123 @@
 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE
 #define CONFIG_SYS_FSL_ERRATUM_A_004934
 #define CONFIG_SYS_FSL_ERRATUM_A005871
+#define CONFIG_SYS_FSL_ERRATUM_A006379
 #define CONFIG_SYS_FSL_ERRATUM_A006593
+#define CONFIG_SYS_FSL_ERRATUM_A006475
+#define CONFIG_SYS_FSL_ERRATUM_A006384
 #define CONFIG_SYS_CCSRBAR_DEFAULT	0xfe000000
 
 #ifdef CONFIG_PPC_B4860
 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4
 #define CONFIG_MAX_CPUS			4
+#define CONFIG_SYS_FSL_SRDS_NUM_PLLS	2
 #define CONFIG_SYS_FSL_NUM_CC_PLLS	4
+#define CONFIG_SYS_FSL_CLUSTER_CLOCKS	{ 1, 4, 4, 4 }
 #define CONFIG_SYS_NUM_FM1_DTSEC	6
 #define CONFIG_SYS_NUM_FM1_10GEC	2
 #define CONFIG_NUM_DDR_CONTROLLERS	2
+#define CONFIG_USB_MAX_CONTROLLER_COUNT	1
 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS	2
 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM	9
 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM	5
 #define CONFIG_SYS_FSL_SRIO_LIODN
 #else
 #define CONFIG_MAX_CPUS			2
+#define CONFIG_SYS_FSL_SRDS_NUM_PLLS	1
 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 2
 #define CONFIG_SYS_FSL_NUM_CC_PLLS	4
+#define CONFIG_SYS_FSL_CLUSTER_CLOCKS	{ 1, 4 }
 #define CONFIG_SYS_NUM_FM1_DTSEC	4
 #define CONFIG_SYS_NUM_FM1_10GEC	0
 #define CONFIG_NUM_DDR_CONTROLLERS	1
 #endif
 
-#elif defined(CONFIG_PPC_T1040)
+#elif defined(CONFIG_PPC_T1040) || defined(CONFIG_PPC_T1042) ||\
+defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022)
 #define CONFIG_E5500
 #define CONFIG_FSL_CORENET		/* Freescale CoreNet platform */
 #define CONFIG_SYS_FSL_QORIQ_CHASSIS2	/* Freescale Chassis generation 2 */
 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 1
 #define CONFIG_SYS_FSL_QMAN_V3		/* QMAN version 3 */
+#if defined(CONFIG_PPC_T1040) || defined(CONFIG_PPC_T1042)
 #define CONFIG_MAX_CPUS			4
-#define CONFIG_SYS_FSL_NUM_CC_PLLS	5
+#elif defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022)
+#define CONFIG_MAX_CPUS			2
+#endif
+#define CONFIG_SYS_FSL_NUM_CC_PLLS	2
+#define CONFIG_SYS_FSL_CLUSTER_CLOCKS   { 1, 1, 1, 1 }
+#define CONFIG_SYS_SDHC_CLOCK		0
 #define CONFIG_SYS_FSL_NUM_LAWS		16
-#define CONFIG_SYS_FSL_SEC_COMPAT	4
+#define CONFIG_SYS_FSL_SRDS_1
+#define CONFIG_SYS_FSL_SEC_COMPAT	5
 #define CONFIG_SYS_NUM_FMAN		1
 #define CONFIG_SYS_NUM_FM1_DTSEC	5
 #define CONFIG_NUM_DDR_CONTROLLERS	1
-#define CONFIG_SYS_FSL_DDR_VER		FSL_DDR_VER_4_7
-#define CONFIG_SYS_FSL_IFC_BANK_COUNT	4
+#define CONFIG_USB_MAX_CONTROLLER_COUNT	2
+#define CONFIG_PME_PLAT_CLK_DIV		2
+#define CONFIG_SYS_PME_CLK		CONFIG_PME_PLAT_CLK_DIV
+#define CONFIG_SYS_FSL_DDR_VER		FSL_DDR_VER_5_0
+#define CONFIG_SYS_FSL_IFC_BANK_COUNT	8
 #define CONFIG_SYS_FMAN_V3
-#define CONFIG_SYS_FM_MURAM_SIZE	0x28000
-#define CONFIG_SYS_FSL_TBCLK_DIV	32
+#define CONFIG_FM_PLAT_CLK_DIV	1
+#define CONFIG_SYS_FM1_CLK		CONFIG_FM_PLAT_CLK_DIV
+#define CONFIG_SYS_FM_MURAM_SIZE	0x30000
+#define CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
+#define CONFIG_SYS_FSL_TBCLK_DIV	16
 #define CONFIG_SYS_FSL_PCIE_COMPAT	"fsl,qoriq-pcie-v2.4"
+#define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE
+#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
+#define CONFIG_SYS_FSL_ERRATUM_A006261
+#define CONFIG_SYS_CCSRBAR_DEFAULT	0xfe000000
+#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
+#define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE
+
+#elif defined(CONFIG_PPC_T2080) || defined(CONFIG_PPC_T2081)
+#define CONFIG_E6500
+#define CONFIG_SYS_PPC64		/* 64-bit core */
+#define CONFIG_FSL_CORENET		/* Freescale CoreNet platform */
+#define CONFIG_SYS_FSL_QORIQ_CHASSIS2	/* Freescale Chassis generation 2 */
+#define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4
+#define CONFIG_SYS_FSL_NUM_CC_PLLS	2
+#define CONFIG_SYS_FSL_QMAN_V3
+#define CONFIG_MAX_CPUS			4
+#define CONFIG_SYS_FSL_NUM_LAWS		32
+#define CONFIG_SYS_FSL_SEC_COMPAT	4
+#define CONFIG_SYS_NUM_FMAN		1
+#define CONFIG_SYS_FSL_CLUSTER_CLOCKS	{ 1, 4, 4, 4 }
+#define CONFIG_SYS_FSL_SRDS_1
+#define CONFIG_SYS_FSL_PCI_VER_3_X
+#if defined(CONFIG_PPC_T2080)
+#define CONFIG_SYS_NUM_FM1_DTSEC	8
+#define CONFIG_SYS_NUM_FM1_10GEC	4
+#define CONFIG_SYS_FSL_SRDS_2
+#define CONFIG_SYS_FSL_SRIO_LIODN
 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS	2
 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM	9
 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM	5
-#define CONFIG_SYS_FSL_USB1_PHY_ENABLE
-#define CONFIG_SYS_FSL_USB2_PHY_ENABLE
+#elif defined(CONFIG_PPC_T2081)
+#define CONFIG_SYS_NUM_FM1_DTSEC	6
+#define CONFIG_SYS_NUM_FM1_10GEC	2
+#endif
+#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
+#define CONFIG_NUM_DDR_CONTROLLERS	1
+#define CONFIG_PME_PLAT_CLK_DIV		1
+#define CONFIG_SYS_PME_CLK		CONFIG_PME_PLAT_CLK_DIV
+#define CONFIG_SYS_FM1_CLK		0
+#define CONFIG_SYS_FSL_DDR_VER		FSL_DDR_VER_4_7
+#define CONFIG_SYS_FSL_IFC_BANK_COUNT	8
+#define CONFIG_SYS_FMAN_V3
+#define CONFIG_SYS_FM_MURAM_SIZE	0x28000
+#define CONFIG_SYS_FSL_TBCLK_DIV	16
+#define CONFIG_SYS_FSL_PCIE_COMPAT	"fsl,qoriq-pcie-v3.0"
+#define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE
 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
 #define CONFIG_SYS_CCSRBAR_DEFAULT	0xfe000000
+#define CONFIG_SYS_FSL_SFP_VER_3_0
+#define CONFIG_SYS_FSL_ISBC_VER		2
+#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
+#define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE
+
 
 #elif defined(CONFIG_PPC_C29X)
 #define CONFIG_MAX_CPUS			1
@@ -694,4 +811,10 @@
 #define CONFIG_SYS_FSL_THREADS_PER_CORE 1
 #endif
 
+#if !defined(CONFIG_SYS_FSL_DDRC_GEN1) && \
+	!defined(CONFIG_SYS_FSL_DDRC_GEN2) && \
+	!defined(CONFIG_SYS_FSL_DDRC_GEN3)
+#define CONFIG_SYS_FSL_DDRC_GEN3
+#endif
+
 #endif /* _ASM_MPC85xx_CONFIG_H_ */
diff --git a/arch/powerpc/include/asm/config_mpc86xx.h b/arch/powerpc/include/asm/config_mpc86xx.h
index 694b110302..4f9b2252be 100644
--- a/arch/powerpc/include/asm/config_mpc86xx.h
+++ b/arch/powerpc/include/asm/config_mpc86xx.h
@@ -7,6 +7,8 @@
 #ifndef _ASM_MPC86xx_CONFIG_H_
 #define _ASM_MPC86xx_CONFIG_H_
 
+#define CONFIG_SYS_FSL_DDR_86XX
+
 /* SoC specific defines for Freescale MPC86xx processors */
 
 #if defined(CONFIG_MPC8610)
diff --git a/arch/powerpc/include/asm/cpm_8260.h b/arch/powerpc/include/asm/cpm_8260.h
index 6a4a51a9aa..4f78186d9d 100644
--- a/arch/powerpc/include/asm/cpm_8260.h
+++ b/arch/powerpc/include/asm/cpm_8260.h
@@ -1,4 +1,3 @@
-
 /*
  * MPC8260 Communication Processor Module.
  * Copyright (c) 1999 Dan Malek (dmalek@jlc.net)
diff --git a/arch/powerpc/include/asm/cpm_85xx.h b/arch/powerpc/include/asm/cpm_85xx.h
index 1681ecd507..b137a71450 100644
--- a/arch/powerpc/include/asm/cpm_85xx.h
+++ b/arch/powerpc/include/asm/cpm_85xx.h
@@ -1,4 +1,3 @@
-
 /*
  * MPC85xx Communication Processor Module
  * Copyright (c) 2003,Motorola Inc.
diff --git a/arch/powerpc/include/asm/fsl_ddr_dimm_params.h b/arch/powerpc/include/asm/fsl_ddr_dimm_params.h
deleted file mode 100644
index bd312ad5c5..0000000000
--- a/arch/powerpc/include/asm/fsl_ddr_dimm_params.h
+++ /dev/null
@@ -1,100 +0,0 @@
-/*
- * Copyright 2008 Freescale Semiconductor, Inc.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * Version 2 as published by the Free Software Foundation.
- */
-
-#ifndef DDR2_DIMM_PARAMS_H
-#define DDR2_DIMM_PARAMS_H
-
-#define EDC_DATA_PARITY	1
-#define EDC_ECC		2
-#define EDC_AC_PARITY	4
-
-/* Parameters for a DDR2 dimm computed from the SPD */
-typedef struct dimm_params_s {
-
-	/* DIMM organization parameters */
-	char mpart[19];		/* guaranteed null terminated */
-
-	unsigned int n_ranks;
-	unsigned long long rank_density;
-	unsigned long long capacity;
-	unsigned int data_width;
-	unsigned int primary_sdram_width;
-	unsigned int ec_sdram_width;
-	unsigned int registered_dimm;
-	unsigned int device_width;	/* x4, x8, x16 components */
-
-	/* SDRAM device parameters */
-	unsigned int n_row_addr;
-	unsigned int n_col_addr;
-	unsigned int edc_config;	/* 0 = none, 1 = parity, 2 = ECC */
-	unsigned int n_banks_per_sdram_device;
-	unsigned int burst_lengths_bitmask;	/* BL=4 bit 2, BL=8 = bit 3 */
-	unsigned int row_density;
-
-	/* used in computing base address of DIMMs */
-	unsigned long long base_address;
-	/* mirrored DIMMs */
-	unsigned int mirrored_dimm;	/* only for ddr3 */
-
-	/* DIMM timing parameters */
-
-	unsigned int mtb_ps;	/* medium timebase ps, only for ddr3 */
-	unsigned int ftb_10th_ps; /* fine timebase, in 1/10 ps, only for ddr3 */
-	unsigned int tAA_ps;	/* minimum CAS latency time, only for ddr3 */
-	unsigned int tFAW_ps;	/* four active window delay, only for ddr3 */
-
-	/*
-	 * SDRAM clock periods
-	 * The range for these are 1000-10000 so a short should be sufficient
-	 */
-	unsigned int tCKmin_X_ps;
-	unsigned int tCKmin_X_minus_1_ps;
-	unsigned int tCKmin_X_minus_2_ps;
-	unsigned int tCKmax_ps;
-
-	/* SPD-defined CAS latencies */
-	unsigned int caslat_X;
-	unsigned int caslat_X_minus_1;
-	unsigned int caslat_X_minus_2;
-
-	unsigned int caslat_lowest_derated;	/* Derated CAS latency */
-
-	/* basic timing parameters */
-	unsigned int tRCD_ps;
-	unsigned int tRP_ps;
-	unsigned int tRAS_ps;
-
-	unsigned int tWR_ps;	/* maximum = 63750 ps */
-	unsigned int tWTR_ps;	/* maximum = 63750 ps */
-	unsigned int tRFC_ps;   /* max = 255 ns + 256 ns + .75 ns
-				       = 511750 ps */
-
-	unsigned int tRRD_ps;	/* maximum = 63750 ps */
-	unsigned int tRC_ps;	/* maximum = 254 ns + .75 ns = 254750 ps */
-
-	unsigned int refresh_rate_ps;
-
-	/* DDR3 doesn't need these as below */
-	unsigned int tIS_ps;	/* byte 32, spd->ca_setup */
-	unsigned int tIH_ps;	/* byte 33, spd->ca_hold */
-	unsigned int tDS_ps;	/* byte 34, spd->data_setup */
-	unsigned int tDH_ps;	/* byte 35, spd->data_hold */
-	unsigned int tRTP_ps;	/* byte 38, spd->trtp */
-	unsigned int tDQSQ_max_ps;	/* byte 44, spd->tdqsq */
-	unsigned int tQHS_ps;	/* byte 45, spd->tqhs */
-
-	/* DDR3 RDIMM */
-	unsigned char rcw[16];	/* Register Control Word 0-15 */
-} dimm_params_t;
-
-extern unsigned int ddr_compute_dimm_parameters(
-					 const generic_spd_eeprom_t *spd,
-					 dimm_params_t *pdimm,
-					 unsigned int dimm_number);
-
-#endif
diff --git a/arch/powerpc/include/asm/fsl_ddr_sdram.h b/arch/powerpc/include/asm/fsl_ddr_sdram.h
deleted file mode 100644
index f4eec82d5d..0000000000
--- a/arch/powerpc/include/asm/fsl_ddr_sdram.h
+++ /dev/null
@@ -1,377 +0,0 @@
-/*
- * Copyright 2008-2011 Freescale Semiconductor, Inc.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * Version 2 as published by the Free Software Foundation.
- */
-
-#ifndef FSL_DDR_MEMCTL_H
-#define FSL_DDR_MEMCTL_H
-
-/*
- * Pick a basic DDR Technology.
- */
-#include <ddr_spd.h>
-
-#define SDRAM_TYPE_DDR1    2
-#define SDRAM_TYPE_DDR2    3
-#define SDRAM_TYPE_LPDDR1  6
-#define SDRAM_TYPE_DDR3    7
-
-#define DDR_BL4		4	/* burst length 4 */
-#define DDR_BC4		DDR_BL4	/* burst chop for ddr3 */
-#define DDR_OTF		6	/* on-the-fly BC4 and BL8 */
-#define DDR_BL8		8	/* burst length 8 */
-
-#define DDR3_RTT_OFF		0
-#define DDR3_RTT_60_OHM		1 /* RTT_Nom = RZQ/4 */
-#define DDR3_RTT_120_OHM	2 /* RTT_Nom = RZQ/2 */
-#define DDR3_RTT_40_OHM		3 /* RTT_Nom = RZQ/6 */
-#define DDR3_RTT_20_OHM		4 /* RTT_Nom = RZQ/12 */
-#define DDR3_RTT_30_OHM		5 /* RTT_Nom = RZQ/8 */
-
-#define DDR2_RTT_OFF		0
-#define DDR2_RTT_75_OHM		1
-#define DDR2_RTT_150_OHM	2
-#define DDR2_RTT_50_OHM		3
-
-#if defined(CONFIG_FSL_DDR1)
-#define FSL_DDR_MIN_TCKE_PULSE_WIDTH_DDR	(1)
-typedef ddr1_spd_eeprom_t generic_spd_eeprom_t;
-#ifndef CONFIG_FSL_SDRAM_TYPE
-#define CONFIG_FSL_SDRAM_TYPE	SDRAM_TYPE_DDR1
-#endif
-#elif defined(CONFIG_FSL_DDR2)
-#define FSL_DDR_MIN_TCKE_PULSE_WIDTH_DDR	(3)
-typedef ddr2_spd_eeprom_t generic_spd_eeprom_t;
-#ifndef CONFIG_FSL_SDRAM_TYPE
-#define CONFIG_FSL_SDRAM_TYPE	SDRAM_TYPE_DDR2
-#endif
-#elif defined(CONFIG_FSL_DDR3)
-#define FSL_DDR_MIN_TCKE_PULSE_WIDTH_DDR	(3)	/* FIXME */
-typedef ddr3_spd_eeprom_t generic_spd_eeprom_t;
-#ifndef CONFIG_FSL_SDRAM_TYPE
-#define CONFIG_FSL_SDRAM_TYPE	SDRAM_TYPE_DDR3
-#endif
-#endif	/* #if defined(CONFIG_FSL_DDR1) */
-
-#define FSL_DDR_ODT_NEVER		0x0
-#define FSL_DDR_ODT_CS			0x1
-#define FSL_DDR_ODT_ALL_OTHER_CS	0x2
-#define FSL_DDR_ODT_OTHER_DIMM		0x3
-#define FSL_DDR_ODT_ALL			0x4
-#define FSL_DDR_ODT_SAME_DIMM		0x5
-#define FSL_DDR_ODT_CS_AND_OTHER_DIMM	0x6
-#define FSL_DDR_ODT_OTHER_CS_ONSAMEDIMM	0x7
-
-/* define bank(chip select) interleaving mode */
-#define FSL_DDR_CS0_CS1			0x40
-#define FSL_DDR_CS2_CS3			0x20
-#define FSL_DDR_CS0_CS1_AND_CS2_CS3	(FSL_DDR_CS0_CS1 | FSL_DDR_CS2_CS3)
-#define FSL_DDR_CS0_CS1_CS2_CS3		(FSL_DDR_CS0_CS1_AND_CS2_CS3 | 0x04)
-
-/* define memory controller interleaving mode */
-#define FSL_DDR_CACHE_LINE_INTERLEAVING	0x0
-#define FSL_DDR_PAGE_INTERLEAVING	0x1
-#define FSL_DDR_BANK_INTERLEAVING	0x2
-#define FSL_DDR_SUPERBANK_INTERLEAVING	0x3
-#define FSL_DDR_3WAY_1KB_INTERLEAVING	0xA
-#define FSL_DDR_3WAY_4KB_INTERLEAVING	0xC
-#define FSL_DDR_3WAY_8KB_INTERLEAVING	0xD
-/* placeholder for 4-way interleaving */
-#define FSL_DDR_4WAY_1KB_INTERLEAVING	0x1A
-#define FSL_DDR_4WAY_4KB_INTERLEAVING	0x1C
-#define FSL_DDR_4WAY_8KB_INTERLEAVING	0x1D
-
-#define SDRAM_CS_CONFIG_EN		0x80000000
-
-/* DDR_SDRAM_CFG - DDR SDRAM Control Configuration
- */
-#define SDRAM_CFG_MEM_EN		0x80000000
-#define SDRAM_CFG_SREN			0x40000000
-#define SDRAM_CFG_ECC_EN		0x20000000
-#define SDRAM_CFG_RD_EN			0x10000000
-#define SDRAM_CFG_SDRAM_TYPE_DDR1	0x02000000
-#define SDRAM_CFG_SDRAM_TYPE_DDR2	0x03000000
-#define SDRAM_CFG_SDRAM_TYPE_MASK	0x07000000
-#define SDRAM_CFG_SDRAM_TYPE_SHIFT	24
-#define SDRAM_CFG_DYN_PWR		0x00200000
-#define SDRAM_CFG_DBW_MASK		0x00180000
-#define SDRAM_CFG_DBW_SHIFT		19
-#define SDRAM_CFG_32_BE			0x00080000
-#define SDRAM_CFG_16_BE			0x00100000
-#define SDRAM_CFG_8_BE			0x00040000
-#define SDRAM_CFG_NCAP			0x00020000
-#define SDRAM_CFG_2T_EN			0x00008000
-#define SDRAM_CFG_BI			0x00000001
-
-#define SDRAM_CFG2_D_INIT		0x00000010
-#define SDRAM_CFG2_ODT_CFG_MASK		0x00600000
-#define SDRAM_CFG2_ODT_NEVER		0
-#define SDRAM_CFG2_ODT_ONLY_WRITE	1
-#define SDRAM_CFG2_ODT_ONLY_READ	2
-#define SDRAM_CFG2_ODT_ALWAYS		3
-
-#define TIMING_CFG_2_CPO_MASK	0x0F800000
-
-#if defined(CONFIG_P4080)
-#define RD_TO_PRE_MASK		0xf
-#define RD_TO_PRE_SHIFT		13
-#define WR_DATA_DELAY_MASK	0xf
-#define WR_DATA_DELAY_SHIFT	9
-#else
-#define RD_TO_PRE_MASK		0x7
-#define RD_TO_PRE_SHIFT		13
-#define WR_DATA_DELAY_MASK	0x7
-#define WR_DATA_DELAY_SHIFT	10
-#endif
-
-/* DDR_MD_CNTL */
-#define MD_CNTL_MD_EN		0x80000000
-#define MD_CNTL_CS_SEL_CS0	0x00000000
-#define MD_CNTL_CS_SEL_CS1	0x10000000
-#define MD_CNTL_CS_SEL_CS2	0x20000000
-#define MD_CNTL_CS_SEL_CS3	0x30000000
-#define MD_CNTL_CS_SEL_CS0_CS1	0x40000000
-#define MD_CNTL_CS_SEL_CS2_CS3	0x50000000
-#define MD_CNTL_MD_SEL_MR	0x00000000
-#define MD_CNTL_MD_SEL_EMR	0x01000000
-#define MD_CNTL_MD_SEL_EMR2	0x02000000
-#define MD_CNTL_MD_SEL_EMR3	0x03000000
-#define MD_CNTL_SET_REF		0x00800000
-#define MD_CNTL_SET_PRE		0x00400000
-#define MD_CNTL_CKE_CNTL_LOW	0x00100000
-#define MD_CNTL_CKE_CNTL_HIGH	0x00200000
-#define MD_CNTL_WRCW		0x00080000
-#define MD_CNTL_MD_VALUE(x)	(x & 0x0000FFFF)
-
-/* DDR_CDR1 */
-#define DDR_CDR1_DHC_EN	0x80000000
-#define DDR_CDR1_ODT_SHIFT	17
-#define DDR_CDR1_ODT_MASK	0x6
-#define DDR_CDR2_ODT_MASK	0x1
-#define DDR_CDR1_ODT(x) ((x & DDR_CDR1_ODT_MASK) << DDR_CDR1_ODT_SHIFT)
-#define DDR_CDR2_ODT(x) (x & DDR_CDR2_ODT_MASK)
-
-#if (defined(CONFIG_SYS_FSL_DDR_VER) && \
-	(CONFIG_SYS_FSL_DDR_VER >= FSL_DDR_VER_4_7))
-#define DDR_CDR_ODT_OFF		0x0
-#define DDR_CDR_ODT_120ohm	0x1
-#define DDR_CDR_ODT_180ohm	0x2
-#define DDR_CDR_ODT_75ohm	0x3
-#define DDR_CDR_ODT_110ohm	0x4
-#define DDR_CDR_ODT_60hm	0x5
-#define DDR_CDR_ODT_70ohm	0x6
-#define DDR_CDR_ODT_47ohm	0x7
-#else
-#define DDR_CDR_ODT_75ohm	0x0
-#define DDR_CDR_ODT_55ohm	0x1
-#define DDR_CDR_ODT_60ohm	0x2
-#define DDR_CDR_ODT_50ohm	0x3
-#define DDR_CDR_ODT_150ohm	0x4
-#define DDR_CDR_ODT_43ohm	0x5
-#define DDR_CDR_ODT_120ohm	0x6
-#endif
-
-/* Record of register values computed */
-typedef struct fsl_ddr_cfg_regs_s {
-	struct {
-		unsigned int bnds;
-		unsigned int config;
-		unsigned int config_2;
-	} cs[CONFIG_CHIP_SELECTS_PER_CTRL];
-	unsigned int timing_cfg_3;
-	unsigned int timing_cfg_0;
-	unsigned int timing_cfg_1;
-	unsigned int timing_cfg_2;
-	unsigned int ddr_sdram_cfg;
-	unsigned int ddr_sdram_cfg_2;
-	unsigned int ddr_sdram_mode;
-	unsigned int ddr_sdram_mode_2;
-	unsigned int ddr_sdram_mode_3;
-	unsigned int ddr_sdram_mode_4;
-	unsigned int ddr_sdram_mode_5;
-	unsigned int ddr_sdram_mode_6;
-	unsigned int ddr_sdram_mode_7;
-	unsigned int ddr_sdram_mode_8;
-	unsigned int ddr_sdram_md_cntl;
-	unsigned int ddr_sdram_interval;
-	unsigned int ddr_data_init;
-	unsigned int ddr_sdram_clk_cntl;
-	unsigned int ddr_init_addr;
-	unsigned int ddr_init_ext_addr;
-	unsigned int timing_cfg_4;
-	unsigned int timing_cfg_5;
-	unsigned int ddr_zq_cntl;
-	unsigned int ddr_wrlvl_cntl;
-	unsigned int ddr_wrlvl_cntl_2;
-	unsigned int ddr_wrlvl_cntl_3;
-	unsigned int ddr_sr_cntr;
-	unsigned int ddr_sdram_rcw_1;
-	unsigned int ddr_sdram_rcw_2;
-	unsigned int ddr_eor;
-	unsigned int ddr_cdr1;
-	unsigned int ddr_cdr2;
-	unsigned int err_disable;
-	unsigned int err_int_en;
-	unsigned int debug[32];
-} fsl_ddr_cfg_regs_t;
-
-typedef struct memctl_options_partial_s {
-	unsigned int all_DIMMs_ECC_capable;
-	unsigned int all_DIMMs_tCKmax_ps;
-	unsigned int all_DIMMs_burst_lengths_bitmask;
-	unsigned int all_DIMMs_registered;
-	unsigned int all_DIMMs_unbuffered;
-	/*	unsigned int lowest_common_SPD_caslat; */
-	unsigned int all_DIMMs_minimum_tRCD_ps;
-} memctl_options_partial_t;
-
-#define DDR_DATA_BUS_WIDTH_64 0
-#define DDR_DATA_BUS_WIDTH_32 1
-#define DDR_DATA_BUS_WIDTH_16 2
-/*
- * Generalized parameters for memory controller configuration,
- * might be a little specific to the FSL memory controller
- */
-typedef struct memctl_options_s {
-	/*
-	 * Memory organization parameters
-	 *
-	 * if DIMM is present in the system
-	 * where DIMMs are with respect to chip select
-	 * where chip selects are with respect to memory boundaries
-	 */
-	unsigned int registered_dimm_en;    /* use registered DIMM support */
-
-	/* Options local to a Chip Select */
-	struct cs_local_opts_s {
-		unsigned int auto_precharge;
-		unsigned int odt_rd_cfg;
-		unsigned int odt_wr_cfg;
-		unsigned int odt_rtt_norm;
-		unsigned int odt_rtt_wr;
-	} cs_local_opts[CONFIG_CHIP_SELECTS_PER_CTRL];
-
-	/* Special configurations for chip select */
-	unsigned int memctl_interleaving;
-	unsigned int memctl_interleaving_mode;
-	unsigned int ba_intlv_ctl;
-	unsigned int addr_hash;
-
-	/* Operational mode parameters */
-	unsigned int ECC_mode;	 /* Use ECC? */
-	/* Initialize ECC using memory controller? */
-	unsigned int ECC_init_using_memctl;
-	unsigned int DQS_config;	/* Use DQS? maybe only with DDR2? */
-	/* SREN - self-refresh during sleep */
-	unsigned int self_refresh_in_sleep;
-	unsigned int dynamic_power;	/* DYN_PWR */
-	/* memory data width to use (16-bit, 32-bit, 64-bit) */
-	unsigned int data_bus_width;
-	unsigned int burst_length;	/* BL4, OTF and BL8 */
-	/* On-The-Fly Burst Chop enable */
-	unsigned int OTF_burst_chop_en;
-	/* mirrior DIMMs for DDR3 */
-	unsigned int mirrored_dimm;
-	unsigned int quad_rank_present;
-	unsigned int ap_en;	/* address parity enable for RDIMM */
-	unsigned int x4_en;	/* enable x4 devices */
-
-	/* Global Timing Parameters */
-	unsigned int cas_latency_override;
-	unsigned int cas_latency_override_value;
-	unsigned int use_derated_caslat;
-	unsigned int additive_latency_override;
-	unsigned int additive_latency_override_value;
-
-	unsigned int clk_adjust;		/* */
-	unsigned int cpo_override;
-	unsigned int write_data_delay;		/* DQS adjust */
-
-	unsigned int wrlvl_override;
-	unsigned int wrlvl_sample;		/* Write leveling */
-	unsigned int wrlvl_start;
-	unsigned int wrlvl_ctl_2;
-	unsigned int wrlvl_ctl_3;
-
-	unsigned int half_strength_driver_enable;
-	unsigned int twoT_en;
-	unsigned int threeT_en;
-	unsigned int bstopre;
-	unsigned int tCKE_clock_pulse_width_ps;	/* tCKE */
-	unsigned int tFAW_window_four_activates_ps;	/* tFAW --  FOUR_ACT */
-
-	/* Rtt impedance */
-	unsigned int rtt_override;		/* rtt_override enable */
-	unsigned int rtt_override_value;	/* that is Rtt_Nom for DDR3 */
-	unsigned int rtt_wr_override_value;	/* this is Rtt_WR for DDR3 */
-
-	/* Automatic self refresh */
-	unsigned int auto_self_refresh_en;
-	unsigned int sr_it;
-	/* ZQ calibration */
-	unsigned int zq_en;
-	/* Write leveling */
-	unsigned int wrlvl_en;
-	/* RCW override for RDIMM */
-	unsigned int rcw_override;
-	unsigned int rcw_1;
-	unsigned int rcw_2;
-	/* control register 1 */
-	unsigned int ddr_cdr1;
-	unsigned int ddr_cdr2;
-
-	unsigned int trwt_override;
-	unsigned int trwt;			/* read-to-write turnaround */
-} memctl_options_t;
-
-extern phys_size_t fsl_ddr_sdram(void);
-extern phys_size_t fsl_ddr_sdram_size(void);
-extern int fsl_use_spd(void);
-extern void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
-					unsigned int ctrl_num, int step);
-u32 fsl_ddr_get_intl3r(void);
-
-static void __board_assert_mem_reset(void)
-{
-}
-
-static void __board_deassert_mem_reset(void)
-{
-}
-
-void board_assert_mem_reset(void)
-	__attribute__((weak, alias("__board_assert_mem_reset")));
-
-void board_deassert_mem_reset(void)
-	__attribute__((weak, alias("__board_deassert_mem_reset")));
-
-static int __board_need_mem_reset(void)
-{
-	return 0;
-}
-
-int board_need_mem_reset(void)
-	__attribute__((weak, alias("__board_need_mem_reset")));
-
-/*
- * The 85xx boards have a common prototype for fixed_sdram so put the
- * declaration here.
- */
-#ifdef CONFIG_MPC85xx
-extern phys_size_t fixed_sdram(void);
-#endif
-
-#if defined(CONFIG_DDR_ECC)
-extern void ddr_enable_ecc(unsigned int dram_size);
-#endif
-
-
-typedef struct fixed_ddr_parm{
-	int min_freq;
-	int max_freq;
-	fsl_ddr_cfg_regs_t *ddr_settings;
-} fixed_ddr_parm_t;
-#endif
diff --git a/arch/powerpc/include/asm/fsl_errata.h b/arch/powerpc/include/asm/fsl_errata.h
new file mode 100644
index 0000000000..c9982cc8ec
--- /dev/null
+++ b/arch/powerpc/include/asm/fsl_errata.h
@@ -0,0 +1,63 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#ifndef _ASM_FSL_ERRATA_H
+#define _ASM_FSL_ERRATA_H
+
+#include <common.h>
+#include <asm/processor.h>
+
+#ifdef CONFIG_SYS_FSL_ERRATUM_A006379
+static inline bool has_erratum_a006379(void)
+{
+	u32 svr = get_svr();
+	if (((SVR_SOC_VER(svr) == SVR_T4240) && SVR_MAJ(svr) <= 1) ||
+	    ((SVR_SOC_VER(svr) == SVR_T4160) && SVR_MAJ(svr) <= 1) ||
+	    ((SVR_SOC_VER(svr) == SVR_B4860) && SVR_MAJ(svr) <= 2) ||
+	    ((SVR_SOC_VER(svr) == SVR_B4420) && SVR_MAJ(svr) <= 2) ||
+	    ((SVR_SOC_VER(svr) == SVR_T2080) && SVR_MAJ(svr) <= 1) ||
+	    ((SVR_SOC_VER(svr) == SVR_T2081) && SVR_MAJ(svr) <= 1))
+		return true;
+
+	return false;
+}
+#endif
+
+#ifdef CONFIG_SYS_FSL_ERRATUM_A006261
+static inline bool has_erratum_a006261(void)
+{
+	u32 svr = get_svr();
+	u32 soc = SVR_SOC_VER(svr);
+
+	switch (soc) {
+	case SVR_P1010:
+		return IS_SVR_REV(svr, 1, 0) || IS_SVR_REV(svr, 2, 0);
+	case SVR_P2041:
+	case SVR_P2040:
+		return IS_SVR_REV(svr, 1, 0) ||
+			IS_SVR_REV(svr, 1, 1) || IS_SVR_REV(svr, 2, 1);
+	case SVR_P3041:
+		return IS_SVR_REV(svr, 1, 0) ||
+			IS_SVR_REV(svr, 1, 1) ||
+			IS_SVR_REV(svr, 2, 0) || IS_SVR_REV(svr, 2, 1);
+	case SVR_P5010:
+	case SVR_P5020:
+	case SVR_P5021:
+		return IS_SVR_REV(svr, 1, 0) || IS_SVR_REV(svr, 2, 0);
+	case SVR_T4240:
+	case SVR_T4160:
+		return IS_SVR_REV(svr, 1, 0) || IS_SVR_REV(svr, 2, 0);
+	case SVR_T1040:
+		return IS_SVR_REV(svr, 1, 0);
+	case SVR_P5040:
+		return IS_SVR_REV(svr, 1, 0);
+	}
+
+	return false;
+}
+#endif
+
+#endif
diff --git a/arch/powerpc/include/asm/fsl_ifc.h b/arch/powerpc/include/asm/fsl_ifc.h
deleted file mode 100644
index a945e4b2d4..0000000000
--- a/arch/powerpc/include/asm/fsl_ifc.h
+++ /dev/null
@@ -1,986 +0,0 @@
-/*
- * Copyright 2010-2011 Freescale Semiconductor, Inc.
- * Author: Dipen Dudhat <dipen.dudhat@freescale.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef __ASM_PPC_FSL_IFC_H
-#define __ASM_PPC_FSL_IFC_H
-
-#ifdef CONFIG_FSL_IFC
-#include <config.h>
-#include <common.h>
-
-/*
- * CSPR - Chip Select Property Register
- */
-#define CSPR_BA				0xFFFF0000
-#define CSPR_BA_SHIFT			16
-#define CSPR_PORT_SIZE			0x00000180
-#define CSPR_PORT_SIZE_SHIFT		7
-/* Port Size 8 bit */
-#define CSPR_PORT_SIZE_8		0x00000080
-/* Port Size 16 bit */
-#define CSPR_PORT_SIZE_16		0x00000100
-/* Port Size 32 bit */
-#define CSPR_PORT_SIZE_32		0x00000180
-/* Write Protect */
-#define CSPR_WP				0x00000040
-#define CSPR_WP_SHIFT			6
-/* Machine Select */
-#define CSPR_MSEL			0x00000006
-#define CSPR_MSEL_SHIFT			1
-/* NOR */
-#define CSPR_MSEL_NOR			0x00000000
-/* NAND */
-#define CSPR_MSEL_NAND			0x00000002
-/* GPCM */
-#define CSPR_MSEL_GPCM			0x00000004
-/* Bank Valid */
-#define CSPR_V				0x00000001
-#define CSPR_V_SHIFT			0
-
-/* Convert an address into the right format for the CSPR Registers */
-#define CSPR_PHYS_ADDR(x)		(((uint64_t)x) & 0xffff0000)
-
-/*
- * Address Mask Register
- */
-#define IFC_AMASK_MASK			0xFFFF0000
-#define IFC_AMASK_SHIFT			16
-#define IFC_AMASK(n)			(IFC_AMASK_MASK << \
-					(__ilog2(n) - IFC_AMASK_SHIFT))
-
-/*
- * Chip Select Option Register IFC_NAND Machine
- */
-/* Enable ECC Encoder */
-#define CSOR_NAND_ECC_ENC_EN		0x80000000
-#define CSOR_NAND_ECC_MODE_MASK		0x30000000
-/* 4 bit correction per 520 Byte sector */
-#define CSOR_NAND_ECC_MODE_4		0x00000000
-/* 8 bit correction per 528 Byte sector */
-#define CSOR_NAND_ECC_MODE_8		0x10000000
-/* Enable ECC Decoder */
-#define CSOR_NAND_ECC_DEC_EN		0x04000000
-/* Row Address Length */
-#define CSOR_NAND_RAL_MASK		0x01800000
-#define CSOR_NAND_RAL_SHIFT		20
-#define CSOR_NAND_RAL_1			0x00000000
-#define CSOR_NAND_RAL_2			0x00800000
-#define CSOR_NAND_RAL_3			0x01000000
-#define CSOR_NAND_RAL_4			0x01800000
-/* Page Size 512b, 2k, 4k */
-#define CSOR_NAND_PGS_MASK		0x00180000
-#define CSOR_NAND_PGS_SHIFT		16
-#define CSOR_NAND_PGS_512		0x00000000
-#define CSOR_NAND_PGS_2K		0x00080000
-#define CSOR_NAND_PGS_4K		0x00100000
-/* Spare region Size */
-#define CSOR_NAND_SPRZ_MASK		0x0000E000
-#define CSOR_NAND_SPRZ_SHIFT		13
-#define CSOR_NAND_SPRZ_16		0x00000000
-#define CSOR_NAND_SPRZ_64		0x00002000
-#define CSOR_NAND_SPRZ_128		0x00004000
-#define CSOR_NAND_SPRZ_210		0x00006000
-#define CSOR_NAND_SPRZ_218		0x00008000
-#define CSOR_NAND_SPRZ_224		0x0000A000
-/* Pages Per Block */
-#define CSOR_NAND_PB_MASK		0x00000700
-#define CSOR_NAND_PB_SHIFT		8
-#define CSOR_NAND_PB(n)		((__ilog2(n) - 5) << CSOR_NAND_PB_SHIFT)
-/* Time for Read Enable High to Output High Impedance */
-#define CSOR_NAND_TRHZ_MASK		0x0000001C
-#define CSOR_NAND_TRHZ_SHIFT		2
-#define CSOR_NAND_TRHZ_20		0x00000000
-#define CSOR_NAND_TRHZ_40		0x00000004
-#define CSOR_NAND_TRHZ_60		0x00000008
-#define CSOR_NAND_TRHZ_80		0x0000000C
-#define CSOR_NAND_TRHZ_100		0x00000010
-/* Buffer control disable */
-#define CSOR_NAND_BCTLD			0x00000001
-
-/*
- * Chip Select Option Register - NOR Flash Mode
- */
-/* Enable Address shift Mode */
-#define CSOR_NOR_ADM_SHFT_MODE_EN	0x80000000
-/* Page Read Enable from NOR device */
-#define CSOR_NOR_PGRD_EN		0x10000000
-/* AVD Toggle Enable during Burst Program */
-#define CSOR_NOR_AVD_TGL_PGM_EN		0x01000000
-/* Address Data Multiplexing Shift */
-#define CSOR_NOR_ADM_MASK		0x0003E000
-#define CSOR_NOR_ADM_SHIFT_SHIFT	13
-#define CSOR_NOR_ADM_SHIFT(n)	((n) << CSOR_NOR_ADM_SHIFT_SHIFT)
-/* Type of the NOR device hooked */
-#define CSOR_NOR_NOR_MODE_AYSNC_NOR	0x00000000
-#define CSOR_NOR_NOR_MODE_AVD_NOR	0x00000020
-/* Time for Read Enable High to Output High Impedance */
-#define CSOR_NOR_TRHZ_MASK		0x0000001C
-#define CSOR_NOR_TRHZ_SHIFT		2
-#define CSOR_NOR_TRHZ_20		0x00000000
-#define CSOR_NOR_TRHZ_40		0x00000004
-#define CSOR_NOR_TRHZ_60		0x00000008
-#define CSOR_NOR_TRHZ_80		0x0000000C
-#define CSOR_NOR_TRHZ_100		0x00000010
-/* Buffer control disable */
-#define CSOR_NOR_BCTLD			0x00000001
-
-/*
- * Chip Select Option Register - GPCM Mode
- */
-/* GPCM Mode - Normal */
-#define CSOR_GPCM_GPMODE_NORMAL		0x00000000
-/* GPCM Mode - GenericASIC */
-#define CSOR_GPCM_GPMODE_ASIC		0x80000000
-/* Parity Mode odd/even */
-#define CSOR_GPCM_PARITY_EVEN		0x40000000
-/* Parity Checking enable/disable */
-#define CSOR_GPCM_PAR_EN		0x20000000
-/* GPCM Timeout Count */
-#define CSOR_GPCM_GPTO_MASK		0x0F000000
-#define CSOR_GPCM_GPTO_SHIFT		24
-#define CSOR_GPCM_GPTO(n)	((__ilog2(n) - 8) << CSOR_GPCM_GPTO_SHIFT)
-/* GPCM External Access Termination mode for read access */
-#define CSOR_GPCM_RGETA_EXT		0x00080000
-/* GPCM External Access Termination mode for write access */
-#define CSOR_GPCM_WGETA_EXT		0x00040000
-/* Address Data Multiplexing Shift */
-#define CSOR_GPCM_ADM_MASK		0x0003E000
-#define CSOR_GPCM_ADM_SHIFT_SHIFT	13
-#define CSOR_GPCM_ADM_SHIFT(n)	((n) << CSOR_GPCM_ADM_SHIFT_SHIFT)
-/* Generic ASIC Parity error indication delay */
-#define CSOR_GPCM_GAPERRD_MASK		0x00000180
-#define CSOR_GPCM_GAPERRD_SHIFT		7
-#define CSOR_GPCM_GAPERRD(n)	(((n) - 1) << CSOR_GPCM_GAPERRD_SHIFT)
-/* Time for Read Enable High to Output High Impedance */
-#define CSOR_GPCM_TRHZ_MASK		0x0000001C
-#define CSOR_GPCM_TRHZ_20		0x00000000
-#define CSOR_GPCM_TRHZ_40		0x00000004
-#define CSOR_GPCM_TRHZ_60		0x00000008
-#define CSOR_GPCM_TRHZ_80		0x0000000C
-#define CSOR_GPCM_TRHZ_100		0x00000010
-/* Buffer control disable */
-#define CSOR_GPCM_BCTLD			0x00000001
-
-/*
- * Flash Timing Registers (FTIM0 - FTIM2_CSn)
- */
-/*
- * FTIM0 - NAND Flash Mode
- */
-#define FTIM0_NAND			0x7EFF3F3F
-#define FTIM0_NAND_TCCST_SHIFT	25
-#define FTIM0_NAND_TCCST(n)	((n) << FTIM0_NAND_TCCST_SHIFT)
-#define FTIM0_NAND_TWP_SHIFT	16
-#define FTIM0_NAND_TWP(n)	((n) << FTIM0_NAND_TWP_SHIFT)
-#define FTIM0_NAND_TWCHT_SHIFT	8
-#define FTIM0_NAND_TWCHT(n)	((n) << FTIM0_NAND_TWCHT_SHIFT)
-#define FTIM0_NAND_TWH_SHIFT	0
-#define FTIM0_NAND_TWH(n)	((n) << FTIM0_NAND_TWH_SHIFT)
-/*
- * FTIM1 - NAND Flash Mode
- */
-#define FTIM1_NAND			0xFFFF3FFF
-#define FTIM1_NAND_TADLE_SHIFT	24
-#define FTIM1_NAND_TADLE(n)	((n) << FTIM1_NAND_TADLE_SHIFT)
-#define FTIM1_NAND_TWBE_SHIFT	16
-#define FTIM1_NAND_TWBE(n)	((n) << FTIM1_NAND_TWBE_SHIFT)
-#define FTIM1_NAND_TRR_SHIFT	8
-#define FTIM1_NAND_TRR(n)	((n) << FTIM1_NAND_TRR_SHIFT)
-#define FTIM1_NAND_TRP_SHIFT	0
-#define FTIM1_NAND_TRP(n)	((n) << FTIM1_NAND_TRP_SHIFT)
-/*
- * FTIM2 - NAND Flash Mode
- */
-#define FTIM2_NAND			0x1FE1F8FF
-#define FTIM2_NAND_TRAD_SHIFT	21
-#define FTIM2_NAND_TRAD(n)	((n) << FTIM2_NAND_TRAD_SHIFT)
-#define FTIM2_NAND_TREH_SHIFT	11
-#define FTIM2_NAND_TREH(n)	((n) << FTIM2_NAND_TREH_SHIFT)
-#define FTIM2_NAND_TWHRE_SHIFT	0
-#define FTIM2_NAND_TWHRE(n)	((n) << FTIM2_NAND_TWHRE_SHIFT)
-/*
- * FTIM3 - NAND Flash Mode
- */
-#define FTIM3_NAND			0xFF000000
-#define FTIM3_NAND_TWW_SHIFT	24
-#define FTIM3_NAND_TWW(n)	((n) << FTIM3_NAND_TWW_SHIFT)
-
-/*
- * FTIM0 - NOR Flash Mode
- */
-#define FTIM0_NOR			0xF03F3F3F
-#define FTIM0_NOR_TACSE_SHIFT	28
-#define FTIM0_NOR_TACSE(n)	((n) << FTIM0_NOR_TACSE_SHIFT)
-#define FTIM0_NOR_TEADC_SHIFT	16
-#define FTIM0_NOR_TEADC(n)	((n) << FTIM0_NOR_TEADC_SHIFT)
-#define FTIM0_NOR_TAVDS_SHIFT	8
-#define FTIM0_NOR_TAVDS(n)	((n) << FTIM0_NOR_TAVDS_SHIFT)
-#define FTIM0_NOR_TEAHC_SHIFT	0
-#define FTIM0_NOR_TEAHC(n)	((n) << FTIM0_NOR_TEAHC_SHIFT)
-/*
- * FTIM1 - NOR Flash Mode
- */
-#define FTIM1_NOR			0xFF003F3F
-#define FTIM1_NOR_TACO_SHIFT	24
-#define FTIM1_NOR_TACO(n)	((n) << FTIM1_NOR_TACO_SHIFT)
-#define FTIM1_NOR_TRAD_NOR_SHIFT	8
-#define FTIM1_NOR_TRAD_NOR(n)	((n) << FTIM1_NOR_TRAD_NOR_SHIFT)
-#define FTIM1_NOR_TSEQRAD_NOR_SHIFT	0
-#define FTIM1_NOR_TSEQRAD_NOR(n)	((n) << FTIM1_NOR_TSEQRAD_NOR_SHIFT)
-/*
- * FTIM2 - NOR Flash Mode
- */
-#define FTIM2_NOR			0x0F3CFCFF
-#define FTIM2_NOR_TCS_SHIFT		24
-#define FTIM2_NOR_TCS(n)	((n) << FTIM2_NOR_TCS_SHIFT)
-#define FTIM2_NOR_TCH_SHIFT		18
-#define FTIM2_NOR_TCH(n)	((n) << FTIM2_NOR_TCH_SHIFT)
-#define FTIM2_NOR_TWPH_SHIFT	10
-#define FTIM2_NOR_TWPH(n)	((n) << FTIM2_NOR_TWPH_SHIFT)
-#define FTIM2_NOR_TWP_SHIFT		0
-#define FTIM2_NOR_TWP(n)	((n) << FTIM2_NOR_TWP_SHIFT)
-
-/*
- * FTIM0 - Normal GPCM Mode
- */
-#define FTIM0_GPCM			0xF03F3F3F
-#define FTIM0_GPCM_TACSE_SHIFT	28
-#define FTIM0_GPCM_TACSE(n)	((n) << FTIM0_GPCM_TACSE_SHIFT)
-#define FTIM0_GPCM_TEADC_SHIFT	16
-#define FTIM0_GPCM_TEADC(n)	((n) << FTIM0_GPCM_TEADC_SHIFT)
-#define FTIM0_GPCM_TAVDS_SHIFT	8
-#define FTIM0_GPCM_TAVDS(n)	((n) << FTIM0_GPCM_TAVDS_SHIFT)
-#define FTIM0_GPCM_TEAHC_SHIFT	0
-#define FTIM0_GPCM_TEAHC(n)	((n) << FTIM0_GPCM_TEAHC_SHIFT)
-/*
- * FTIM1 - Normal GPCM Mode
- */
-#define FTIM1_GPCM			0xFF003F00
-#define FTIM1_GPCM_TACO_SHIFT	24
-#define FTIM1_GPCM_TACO(n)	((n) << FTIM1_GPCM_TACO_SHIFT)
-#define FTIM1_GPCM_TRAD_SHIFT	8
-#define FTIM1_GPCM_TRAD(n)	((n) << FTIM1_GPCM_TRAD_SHIFT)
-/*
- * FTIM2 - Normal GPCM Mode
- */
-#define FTIM2_GPCM			0x0F3C00FF
-#define FTIM2_GPCM_TCS_SHIFT	24
-#define FTIM2_GPCM_TCS(n)	((n) << FTIM2_GPCM_TCS_SHIFT)
-#define FTIM2_GPCM_TCH_SHIFT	18
-#define FTIM2_GPCM_TCH(n)	((n) << FTIM2_GPCM_TCH_SHIFT)
-#define FTIM2_GPCM_TWP_SHIFT	0
-#define FTIM2_GPCM_TWP(n)	((n) << FTIM2_GPCM_TWP_SHIFT)
-
-/*
- * Ready Busy Status Register (RB_STAT)
- */
-/* CSn is READY */
-#define IFC_RB_STAT_READY_CS0		0x80000000
-#define IFC_RB_STAT_READY_CS1		0x40000000
-#define IFC_RB_STAT_READY_CS2		0x20000000
-#define IFC_RB_STAT_READY_CS3		0x10000000
-
-/*
- * General Control Register (GCR)
- */
-#define IFC_GCR_MASK			0x8000F800
-/* reset all IFC hardware */
-#define IFC_GCR_SOFT_RST_ALL		0x80000000
-/* Turnaroud Time of external buffer */
-#define IFC_GCR_TBCTL_TRN_TIME		0x0000F800
-#define IFC_GCR_TBCTL_TRN_TIME_SHIFT	11
-
-/*
- * Common Event and Error Status Register (CM_EVTER_STAT)
- */
-/* Chip select error */
-#define IFC_CM_EVTER_STAT_CSER		0x80000000
-
-/*
- * Common Event and Error Enable Register (CM_EVTER_EN)
- */
-/* Chip select error checking enable */
-#define IFC_CM_EVTER_EN_CSEREN		0x80000000
-
-/*
- * Common Event and Error Interrupt Enable Register (CM_EVTER_INTR_EN)
- */
-/* Chip select error interrupt enable */
-#define IFC_CM_EVTER_INTR_EN_CSERIREN	0x80000000
-
-/*
- * Common Transfer Error Attribute Register-0 (CM_ERATTR0)
- */
-/* transaction type of error Read/Write */
-#define IFC_CM_ERATTR0_ERTYP_READ	0x80000000
-#define IFC_CM_ERATTR0_ERAID		0x0FF00000
-#define IFC_CM_ERATTR0_ESRCID		0x0000FF00
-
-/*
- * Clock Control Register (CCR)
- */
-#define IFC_CCR_MASK			0x0F0F8800
-/* Clock division ratio */
-#define IFC_CCR_CLK_DIV_MASK		0x0F000000
-#define IFC_CCR_CLK_DIV_SHIFT		24
-#define IFC_CCR_CLK_DIV(n)		((n-1) << IFC_CCR_CLK_DIV_SHIFT)
-/* IFC Clock Delay */
-#define IFC_CCR_CLK_DLY_MASK		0x000F0000
-#define IFC_CCR_CLK_DLY_SHIFT		16
-#define IFC_CCR_CLK_DLY(n)		((n) << IFC_CCR_CLK_DLY_SHIFT)
-/* Invert IFC clock before sending out */
-#define IFC_CCR_INV_CLK_EN		0x00008000
-/* Fedback IFC Clock */
-#define IFC_CCR_FB_IFC_CLK_SEL		0x00000800
-
-/*
- * Clock Status Register (CSR)
- */
-/* Clk is stable */
-#define IFC_CSR_CLK_STAT_STABLE		0x80000000
-
-/*
- * IFC_NAND Machine Specific Registers
- */
-/*
- * NAND Configuration Register (NCFGR)
- */
-/* Auto Boot Mode */
-#define IFC_NAND_NCFGR_BOOT		0x80000000
-/* Addressing Mode-ROW0+n/COL0 */
-#define IFC_NAND_NCFGR_ADDR_MODE_RC0	0x00000000
-/* Addressing Mode-ROW0+n/COL0+n */
-#define IFC_NAND_NCFGR_ADDR_MODE_RC1	0x00400000
-/* Number of loop iterations of FIR sequences for multi page operations */
-#define IFC_NAND_NCFGR_NUM_LOOP_MASK	0x0000F000
-#define IFC_NAND_NCFGR_NUM_LOOP_SHIFT	12
-#define IFC_NAND_NCFGR_NUM_LOOP(n)	((n) << IFC_NAND_NCFGR_NUM_LOOP_SHIFT)
-/* Number of wait cycles */
-#define IFC_NAND_NCFGR_NUM_WAIT_MASK	0x000000FF
-#define IFC_NAND_NCFGR_NUM_WAIT_SHIFT	0
-
-/*
- * NAND Flash Command Registers (NAND_FCR0/NAND_FCR1)
- */
-/* General purpose FCM flash command bytes CMD0-CMD7 */
-#define IFC_NAND_FCR0_CMD0		0xFF000000
-#define IFC_NAND_FCR0_CMD0_SHIFT	24
-#define IFC_NAND_FCR0_CMD1		0x00FF0000
-#define IFC_NAND_FCR0_CMD1_SHIFT	16
-#define IFC_NAND_FCR0_CMD2		0x0000FF00
-#define IFC_NAND_FCR0_CMD2_SHIFT	8
-#define IFC_NAND_FCR0_CMD3		0x000000FF
-#define IFC_NAND_FCR0_CMD3_SHIFT	0
-#define IFC_NAND_FCR1_CMD4		0xFF000000
-#define IFC_NAND_FCR1_CMD4_SHIFT	24
-#define IFC_NAND_FCR1_CMD5		0x00FF0000
-#define IFC_NAND_FCR1_CMD5_SHIFT	16
-#define IFC_NAND_FCR1_CMD6		0x0000FF00
-#define IFC_NAND_FCR1_CMD6_SHIFT	8
-#define IFC_NAND_FCR1_CMD7		0x000000FF
-#define IFC_NAND_FCR1_CMD7_SHIFT	0
-
-/*
- * Flash ROW and COL Address Register (ROWn, COLn)
- */
-/* Main/spare region locator */
-#define IFC_NAND_COL_MS			0x80000000
-/* Column Address */
-#define IFC_NAND_COL_CA_MASK		0x00000FFF
-
-/*
- * NAND Flash Byte Count Register (NAND_BC)
- */
-/* Byte Count for read/Write */
-#define IFC_NAND_BC			0x000001FF
-
-/*
- * NAND Flash Instruction Registers (NAND_FIR0/NAND_FIR1/NAND_FIR2)
- */
-/* NAND Machine specific opcodes OP0-OP14*/
-#define IFC_NAND_FIR0_OP0		0xFC000000
-#define IFC_NAND_FIR0_OP0_SHIFT		26
-#define IFC_NAND_FIR0_OP1		0x03F00000
-#define IFC_NAND_FIR0_OP1_SHIFT		20
-#define IFC_NAND_FIR0_OP2		0x000FC000
-#define IFC_NAND_FIR0_OP2_SHIFT		14
-#define IFC_NAND_FIR0_OP3		0x00003F00
-#define IFC_NAND_FIR0_OP3_SHIFT		8
-#define IFC_NAND_FIR0_OP4		0x000000FC
-#define IFC_NAND_FIR0_OP4_SHIFT		2
-#define IFC_NAND_FIR1_OP5		0xFC000000
-#define IFC_NAND_FIR1_OP5_SHIFT		26
-#define IFC_NAND_FIR1_OP6		0x03F00000
-#define IFC_NAND_FIR1_OP6_SHIFT		20
-#define IFC_NAND_FIR1_OP7		0x000FC000
-#define IFC_NAND_FIR1_OP7_SHIFT		14
-#define IFC_NAND_FIR1_OP8		0x00003F00
-#define IFC_NAND_FIR1_OP8_SHIFT		8
-#define IFC_NAND_FIR1_OP9		0x000000FC
-#define IFC_NAND_FIR1_OP9_SHIFT		2
-#define IFC_NAND_FIR2_OP10		0xFC000000
-#define IFC_NAND_FIR2_OP10_SHIFT	26
-#define IFC_NAND_FIR2_OP11		0x03F00000
-#define IFC_NAND_FIR2_OP11_SHIFT	20
-#define IFC_NAND_FIR2_OP12		0x000FC000
-#define IFC_NAND_FIR2_OP12_SHIFT	14
-#define IFC_NAND_FIR2_OP13		0x00003F00
-#define IFC_NAND_FIR2_OP13_SHIFT	8
-#define IFC_NAND_FIR2_OP14		0x000000FC
-#define IFC_NAND_FIR2_OP14_SHIFT	2
-
-/*
- * Instruction opcodes to be programmed
- * in FIR registers- 6bits
- */
-enum ifc_nand_fir_opcodes {
-	IFC_FIR_OP_NOP,
-	IFC_FIR_OP_CA0,
-	IFC_FIR_OP_CA1,
-	IFC_FIR_OP_CA2,
-	IFC_FIR_OP_CA3,
-	IFC_FIR_OP_RA0,
-	IFC_FIR_OP_RA1,
-	IFC_FIR_OP_RA2,
-	IFC_FIR_OP_RA3,
-	IFC_FIR_OP_CMD0,
-	IFC_FIR_OP_CMD1,
-	IFC_FIR_OP_CMD2,
-	IFC_FIR_OP_CMD3,
-	IFC_FIR_OP_CMD4,
-	IFC_FIR_OP_CMD5,
-	IFC_FIR_OP_CMD6,
-	IFC_FIR_OP_CMD7,
-	IFC_FIR_OP_CW0,
-	IFC_FIR_OP_CW1,
-	IFC_FIR_OP_CW2,
-	IFC_FIR_OP_CW3,
-	IFC_FIR_OP_CW4,
-	IFC_FIR_OP_CW5,
-	IFC_FIR_OP_CW6,
-	IFC_FIR_OP_CW7,
-	IFC_FIR_OP_WBCD,
-	IFC_FIR_OP_RBCD,
-	IFC_FIR_OP_BTRD,
-	IFC_FIR_OP_RDSTAT,
-	IFC_FIR_OP_NWAIT,
-	IFC_FIR_OP_WFR,
-	IFC_FIR_OP_SBRD,
-	IFC_FIR_OP_UA,
-	IFC_FIR_OP_RB,
-};
-
-/*
- * NAND Chip Select Register (NAND_CSEL)
- */
-#define IFC_NAND_CSEL			0x0C000000
-#define IFC_NAND_CSEL_SHIFT		26
-#define IFC_NAND_CSEL_CS0		0x00000000
-#define IFC_NAND_CSEL_CS1		0x04000000
-#define IFC_NAND_CSEL_CS2		0x08000000
-#define IFC_NAND_CSEL_CS3		0x0C000000
-
-/*
- * NAND Operation Sequence Start (NANDSEQ_STRT)
- */
-/* NAND Flash Operation Start */
-#define IFC_NAND_SEQ_STRT_FIR_STRT	0x80000000
-/* Automatic Erase */
-#define IFC_NAND_SEQ_STRT_AUTO_ERS	0x00800000
-/* Automatic Program */
-#define IFC_NAND_SEQ_STRT_AUTO_PGM	0x00100000
-/* Automatic Copyback */
-#define IFC_NAND_SEQ_STRT_AUTO_CPB	0x00020000
-/* Automatic Read Operation */
-#define IFC_NAND_SEQ_STRT_AUTO_RD	0x00004000
-/* Automatic Status Read */
-#define IFC_NAND_SEQ_STRT_AUTO_STAT_RD	0x00000800
-
-/*
- * NAND Event and Error Status Register (NAND_EVTER_STAT)
- */
-/* Operation Complete */
-#define IFC_NAND_EVTER_STAT_OPC		0x80000000
-/* Flash Timeout Error */
-#define IFC_NAND_EVTER_STAT_FTOER	0x08000000
-/* Write Protect Error */
-#define IFC_NAND_EVTER_STAT_WPER	0x04000000
-/* ECC Error */
-#define IFC_NAND_EVTER_STAT_ECCER	0x02000000
-/* RCW Load Done */
-#define IFC_NAND_EVTER_STAT_RCW_DN	0x00008000
-/* Boot Loadr Done */
-#define IFC_NAND_EVTER_STAT_BOOT_DN	0x00004000
-/* Bad Block Indicator search select */
-#define IFC_NAND_EVTER_STAT_BBI_SRCH_SE	0x00000800
-
-/*
- * NAND Flash Page Read Completion Event Status Register
- * (PGRDCMPL_EVT_STAT)
- */
-#define PGRDCMPL_EVT_STAT_MASK		0xFFFF0000
-/* Small Page 0-15 Done */
-#define PGRDCMPL_EVT_STAT_SECTION_SP(n)	(1 << (31 - (n)))
-/* Large Page(2K) 0-3 Done */
-#define PGRDCMPL_EVT_STAT_LP_2K(n)	(0xF << (28 - (n)*4))
-/* Large Page(4K) 0-1 Done */
-#define PGRDCMPL_EVT_STAT_LP_4K(n)	(0xFF << (24 - (n)*8))
-
-/*
- * NAND Event and Error Enable Register (NAND_EVTER_EN)
- */
-/* Operation complete event enable */
-#define IFC_NAND_EVTER_EN_OPC_EN	0x80000000
-/* Page read complete event enable */
-#define IFC_NAND_EVTER_EN_PGRDCMPL_EN	0x20000000
-/* Flash Timeout error enable */
-#define IFC_NAND_EVTER_EN_FTOER_EN	0x08000000
-/* Write Protect error enable */
-#define IFC_NAND_EVTER_EN_WPER_EN	0x04000000
-/* ECC error logging enable */
-#define IFC_NAND_EVTER_EN_ECCER_EN	0x02000000
-
-/*
- * NAND Event and Error Interrupt Enable Register (NAND_EVTER_INTR_EN)
- */
-/* Enable interrupt for operation complete */
-#define IFC_NAND_EVTER_INTR_OPCIR_EN		0x80000000
-/* Enable interrupt for Page read complete */
-#define IFC_NAND_EVTER_INTR_PGRDCMPLIR_EN	0x20000000
-/* Enable interrupt for Flash timeout error */
-#define IFC_NAND_EVTER_INTR_FTOERIR_EN		0x08000000
-/* Enable interrupt for Write protect error */
-#define IFC_NAND_EVTER_INTR_WPERIR_EN		0x04000000
-/* Enable interrupt for ECC error*/
-#define IFC_NAND_EVTER_INTR_ECCERIR_EN		0x02000000
-
-/*
- * NAND Transfer Error Attribute Register-0 (NAND_ERATTR0)
- */
-#define IFC_NAND_ERATTR0_MASK		0x0C080000
-/* Error on CS0-3 for NAND */
-#define IFC_NAND_ERATTR0_ERCS_CS0	0x00000000
-#define IFC_NAND_ERATTR0_ERCS_CS1	0x04000000
-#define IFC_NAND_ERATTR0_ERCS_CS2	0x08000000
-#define IFC_NAND_ERATTR0_ERCS_CS3	0x0C000000
-/* Transaction type of error Read/Write */
-#define IFC_NAND_ERATTR0_ERTTYPE_READ	0x00080000
-
-/*
- * NAND Flash Status Register (NAND_FSR)
- */
-/* First byte of data read from read status op */
-#define IFC_NAND_NFSR_RS0		0xFF000000
-/* Second byte of data read from read status op */
-#define IFC_NAND_NFSR_RS1		0x00FF0000
-
-/*
- * ECC Error Status Registers (ECCSTAT0-ECCSTAT3)
- */
-/* Number of ECC errors on sector n (n = 0-15) */
-#define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR0_MASK	0x0F000000
-#define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR0_SHIFT	24
-#define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR1_MASK	0x000F0000
-#define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR1_SHIFT	16
-#define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR2_MASK	0x00000F00
-#define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR2_SHIFT	8
-#define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR3_MASK	0x0000000F
-#define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR3_SHIFT	0
-#define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR4_MASK	0x0F000000
-#define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR4_SHIFT	24
-#define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR5_MASK	0x000F0000
-#define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR5_SHIFT	16
-#define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR6_MASK	0x00000F00
-#define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR6_SHIFT	8
-#define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR7_MASK	0x0000000F
-#define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR7_SHIFT	0
-#define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR8_MASK	0x0F000000
-#define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR8_SHIFT	24
-#define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR9_MASK	0x000F0000
-#define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR9_SHIFT	16
-#define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR10_MASK	0x00000F00
-#define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR10_SHIFT	8
-#define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR11_MASK	0x0000000F
-#define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR11_SHIFT	0
-#define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR12_MASK	0x0F000000
-#define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR12_SHIFT	24
-#define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR13_MASK	0x000F0000
-#define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR13_SHIFT	16
-#define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR14_MASK	0x00000F00
-#define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR14_SHIFT	8
-#define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR15_MASK	0x0000000F
-#define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR15_SHIFT	0
-
-/*
- * NAND Control Register (NANDCR)
- */
-#define IFC_NAND_NCR_FTOCNT_MASK	0x1E000000
-#define IFC_NAND_NCR_FTOCNT_SHIFT	25
-#define IFC_NAND_NCR_FTOCNT(n)	((_ilog2(n) - 8)  << IFC_NAND_NCR_FTOCNT_SHIFT)
-
-/*
- * NAND_AUTOBOOT_TRGR
- */
-/* Trigger RCW load */
-#define IFC_NAND_AUTOBOOT_TRGR_RCW_LD	0x80000000
-/* Trigget Auto Boot */
-#define IFC_NAND_AUTOBOOT_TRGR_BOOT_LD	0x20000000
-
-/*
- * NAND_MDR
- */
-/* 1st read data byte when opcode SBRD */
-#define IFC_NAND_MDR_RDATA0		0xFF000000
-/* 2nd read data byte when opcode SBRD */
-#define IFC_NAND_MDR_RDATA1		0x00FF0000
-
-/*
- * NOR Machine Specific Registers
- */
-/*
- * NOR Event and Error Status Register (NOR_EVTER_STAT)
- */
-/* NOR Command Sequence Operation Complete */
-#define IFC_NOR_EVTER_STAT_OPC_NOR	0x80000000
-/* Write Protect Error */
-#define IFC_NOR_EVTER_STAT_WPER		0x04000000
-/* Command Sequence Timeout Error */
-#define IFC_NOR_EVTER_STAT_STOER	0x01000000
-
-/*
- * NOR Event and Error Enable Register (NOR_EVTER_EN)
- */
-/* NOR Command Seq complete event enable */
-#define IFC_NOR_EVTER_EN_OPCEN_NOR	0x80000000
-/* Write Protect Error Checking Enable */
-#define IFC_NOR_EVTER_EN_WPEREN		0x04000000
-/* Timeout Error Enable */
-#define IFC_NOR_EVTER_EN_STOEREN	0x01000000
-
-/*
- * NOR Event and Error Interrupt Enable Register (NOR_EVTER_INTR_EN)
- */
-/* Enable interrupt for OPC complete */
-#define IFC_NOR_EVTER_INTR_OPCEN_NOR	0x80000000
-/* Enable interrupt for write protect error */
-#define IFC_NOR_EVTER_INTR_WPEREN	0x04000000
-/* Enable interrupt for timeout error */
-#define IFC_NOR_EVTER_INTR_STOEREN	0x01000000
-
-/*
- * NOR Transfer Error Attribute Register-0 (NOR_ERATTR0)
- */
-/* Source ID for error transaction */
-#define IFC_NOR_ERATTR0_ERSRCID		0xFF000000
-/* AXI ID for error transation */
-#define IFC_NOR_ERATTR0_ERAID		0x000FF000
-/* Chip select corresponds to NOR error */
-#define IFC_NOR_ERATTR0_ERCS_CS0	0x00000000
-#define IFC_NOR_ERATTR0_ERCS_CS1	0x00000010
-#define IFC_NOR_ERATTR0_ERCS_CS2	0x00000020
-#define IFC_NOR_ERATTR0_ERCS_CS3	0x00000030
-/* Type of transaction read/write */
-#define IFC_NOR_ERATTR0_ERTYPE_READ	0x00000001
-
-/*
- * NOR Transfer Error Attribute Register-2 (NOR_ERATTR2)
- */
-#define IFC_NOR_ERATTR2_ER_NUM_PHASE_EXP	0x000F0000
-#define IFC_NOR_ERATTR2_ER_NUM_PHASE_PER	0x00000F00
-
-/*
- * NOR Control Register (NORCR)
- */
-#define IFC_NORCR_MASK			0x0F0F0000
-/* No. of Address/Data Phase */
-#define IFC_NORCR_NUM_PHASE_MASK	0x0F000000
-#define IFC_NORCR_NUM_PHASE_SHIFT	24
-#define IFC_NORCR_NUM_PHASE(n)	((n-1) << IFC_NORCR_NUM_PHASE_SHIFT)
-/* Sequence Timeout Count */
-#define IFC_NORCR_STOCNT_MASK		0x000F0000
-#define IFC_NORCR_STOCNT_SHIFT		16
-#define IFC_NORCR_STOCNT(n)	((__ilog2(n) - 8) << IFC_NORCR_STOCNT_SHIFT)
-
-/*
- * GPCM Machine specific registers
- */
-/*
- * GPCM Event and Error Status Register (GPCM_EVTER_STAT)
- */
-/* Timeout error */
-#define IFC_GPCM_EVTER_STAT_TOER	0x04000000
-/* Parity error */
-#define IFC_GPCM_EVTER_STAT_PER		0x01000000
-
-/*
- * GPCM Event and Error Enable Register (GPCM_EVTER_EN)
- */
-/* Timeout error enable */
-#define IFC_GPCM_EVTER_EN_TOER_EN	0x04000000
-/* Parity error enable */
-#define IFC_GPCM_EVTER_EN_PER_EN	0x01000000
-
-/*
- * GPCM Event and Error Interrupt Enable Register (GPCM_EVTER_INTR_EN)
- */
-/* Enable Interrupt for timeout error */
-#define IFC_GPCM_EEIER_TOERIR_EN	0x04000000
-/* Enable Interrupt for Parity error */
-#define IFC_GPCM_EEIER_PERIR_EN		0x01000000
-
-/*
- * GPCM Transfer Error Attribute Register-0 (GPCM_ERATTR0)
- */
-/* Source ID for error transaction */
-#define IFC_GPCM_ERATTR0_ERSRCID	0xFF000000
-/* AXI ID for error transaction */
-#define IFC_GPCM_ERATTR0_ERAID		0x000FF000
-/* Chip select corresponds to GPCM error */
-#define IFC_GPCM_ERATTR0_ERCS_CS0	0x00000000
-#define IFC_GPCM_ERATTR0_ERCS_CS1	0x00000040
-#define IFC_GPCM_ERATTR0_ERCS_CS2	0x00000080
-#define IFC_GPCM_ERATTR0_ERCS_CS3	0x000000C0
-/* Type of transaction read/Write */
-#define IFC_GPCM_ERATTR0_ERTYPE_READ	0x00000001
-
-/*
- * GPCM Transfer Error Attribute Register-2 (GPCM_ERATTR2)
- */
-/* On which beat of address/data parity error is observed */
-#define IFC_GPCM_ERATTR2_PERR_BEAT		0x00000C00
-/* Parity Error on byte */
-#define IFC_GPCM_ERATTR2_PERR_BYTE		0x000000F0
-/* Parity Error reported in addr or data phase */
-#define IFC_GPCM_ERATTR2_PERR_DATA_PHASE	0x00000001
-
-/*
- * GPCM Status Register (GPCM_STAT)
- */
-#define IFC_GPCM_STAT_BSY		0x80000000  /* GPCM is busy */
-
-
-#ifndef __ASSEMBLY__
-#include <asm/io.h>
-
-extern void print_ifc_regs(void);
-extern void init_early_memctl_regs(void);
-
-#define IFC_BASE_ADDR ((struct fsl_ifc *)CONFIG_SYS_IFC_ADDR)
-
-#define get_ifc_cspr_ext(i) (in_be32(&(IFC_BASE_ADDR)->cspr_cs[i].cspr_ext))
-#define get_ifc_cspr(i) (in_be32(&(IFC_BASE_ADDR)->cspr_cs[i].cspr))
-#define get_ifc_csor_ext(i) (in_be32(&(IFC_BASE_ADDR)->csor_cs[i].csor_ext))
-#define get_ifc_csor(i) (in_be32(&(IFC_BASE_ADDR)->csor_cs[i].csor))
-#define get_ifc_amask(i) (in_be32(&(IFC_BASE_ADDR)->amask_cs[i].amask))
-#define get_ifc_ftim(i, j) (in_be32(&(IFC_BASE_ADDR)->ftim_cs[i].ftim[j]))
-
-#define set_ifc_cspr_ext(i, v) (out_be32(&(IFC_BASE_ADDR)->cspr_cs[i].cspr_ext, v))
-#define set_ifc_cspr(i, v) (out_be32(&(IFC_BASE_ADDR)->cspr_cs[i].cspr, v))
-#define set_ifc_csor_ext(i, v) (out_be32(&(IFC_BASE_ADDR)->csor_cs[i].csor_ext, v))
-#define set_ifc_csor(i, v) (out_be32(&(IFC_BASE_ADDR)->csor_cs[i].csor, v))
-#define set_ifc_amask(i, v) (out_be32(&(IFC_BASE_ADDR)->amask_cs[i].amask, v))
-#define set_ifc_ftim(i, j, v) \
-			(out_be32(&(IFC_BASE_ADDR)->ftim_cs[i].ftim[j], v))
-
-enum ifc_chip_sel {
-	IFC_CS0,
-	IFC_CS1,
-	IFC_CS2,
-	IFC_CS3,
-	IFC_CS4,
-	IFC_CS5,
-	IFC_CS6,
-	IFC_CS7,
-};
-
-enum ifc_ftims {
-	IFC_FTIM0,
-	IFC_FTIM1,
-	IFC_FTIM2,
-	IFC_FTIM3,
-};
-
-/*
- * IFC Controller NAND Machine registers
- */
-struct fsl_ifc_nand {
-	u32 ncfgr;
-	u32 res1[0x4];
-	u32 nand_fcr0;
-	u32 nand_fcr1;
-	u32 res2[0x8];
-	u32 row0;
-	u32 res3;
-	u32 col0;
-	u32 res4;
-	u32 row1;
-	u32 res5;
-	u32 col1;
-	u32 res6;
-	u32 row2;
-	u32 res7;
-	u32 col2;
-	u32 res8;
-	u32 row3;
-	u32 res9;
-	u32 col3;
-	u32 res10[0x24];
-	u32 nand_fbcr;
-	u32 res11;
-	u32 nand_fir0;
-	u32 nand_fir1;
-	u32 nand_fir2;
-	u32 res12[0x10];
-	u32 nand_csel;
-	u32 res13;
-	u32 nandseq_strt;
-	u32 res14;
-	u32 nand_evter_stat;
-	u32 res15;
-	u32 pgrdcmpl_evt_stat;
-	u32 res16[0x2];
-	u32 nand_evter_en;
-	u32 res17[0x2];
-	u32 nand_evter_intr_en;
-	u32 res18[0x2];
-	u32 nand_erattr0;
-	u32 nand_erattr1;
-	u32 res19[0x10];
-	u32 nand_fsr;
-	u32 res20;
-	u32 nand_eccstat[4];
-	u32 res21[0x20];
-	u32 nanndcr;
-	u32 res22[0x2];
-	u32 nand_autoboot_trgr;
-	u32 res23;
-	u32 nand_mdr;
-	u32 res24[0x5C];
-};
-
-/*
- * IFC controller NOR Machine registers
- */
-struct fsl_ifc_nor {
-	u32 nor_evter_stat;
-	u32 res1[0x2];
-	u32 nor_evter_en;
-	u32 res2[0x2];
-	u32 nor_evter_intr_en;
-	u32 res3[0x2];
-	u32 nor_erattr0;
-	u32 nor_erattr1;
-	u32 nor_erattr2;
-	u32 res4[0x4];
-	u32 norcr;
-	u32 res5[0xEF];
-};
-
-/*
- * IFC controller GPCM Machine registers
- */
-struct fsl_ifc_gpcm {
-	u32 gpcm_evter_stat;
-	u32 res1[0x2];
-	u32 gpcm_evter_en;
-	u32 res2[0x2];
-	u32 gpcm_evter_intr_en;
-	u32 res3[0x2];
-	u32 gpcm_erattr0;
-	u32 gpcm_erattr1;
-	u32 gpcm_erattr2;
-	u32 gpcm_stat;
-	u32 res4[0x1F3];
-};
-
-#ifdef CONFIG_SYS_FSL_IFC_BANK_COUNT
-#if (CONFIG_SYS_FSL_IFC_BANK_COUNT <= 8)
-#define IFC_CSPR_REG_LEN	148
-#define IFC_AMASK_REG_LEN	144
-#define IFC_CSOR_REG_LEN	144
-#define IFC_FTIM_REG_LEN	576
-
-#define IFC_CSPR_USED_LEN	sizeof(struct fsl_ifc_cspr) * \
-					CONFIG_SYS_FSL_IFC_BANK_COUNT
-#define IFC_AMASK_USED_LEN	sizeof(struct fsl_ifc_amask) * \
-					CONFIG_SYS_FSL_IFC_BANK_COUNT
-#define IFC_CSOR_USED_LEN	sizeof(struct fsl_ifc_csor) * \
-					CONFIG_SYS_FSL_IFC_BANK_COUNT
-#define IFC_FTIM_USED_LEN	sizeof(struct fsl_ifc_ftim) * \
-					CONFIG_SYS_FSL_IFC_BANK_COUNT
-#else
-#error IFC BANK count not vaild
-#endif
-#else
-#error IFC BANK count not defined
-#endif
-
-struct fsl_ifc_cspr {
-	u32 cspr_ext;
-	u32 cspr;
-	u32 res;
-};
-
-struct fsl_ifc_amask {
-	u32 amask;
-	u32 res[0x2];
-};
-
-struct fsl_ifc_csor {
-	u32 csor;
-	u32 csor_ext;
-	u32 res;
-};
-
-struct fsl_ifc_ftim {
-	u32 ftim[4];
-	u32 res[0x8];
-};
-
-/*
- * IFC Controller Registers
- */
-struct fsl_ifc {
-	u32 ifc_rev;
-	u32 res1[0x2];
-	struct fsl_ifc_cspr cspr_cs[CONFIG_SYS_FSL_IFC_BANK_COUNT];
-	u8 res2[IFC_CSPR_REG_LEN - IFC_CSPR_USED_LEN];
-	struct fsl_ifc_amask amask_cs[CONFIG_SYS_FSL_IFC_BANK_COUNT];
-	u8 res3[IFC_AMASK_REG_LEN - IFC_AMASK_USED_LEN];
-	struct fsl_ifc_csor csor_cs[CONFIG_SYS_FSL_IFC_BANK_COUNT];
-	u8 res4[IFC_CSOR_REG_LEN - IFC_CSOR_USED_LEN];
-	struct fsl_ifc_ftim ftim_cs[CONFIG_SYS_FSL_IFC_BANK_COUNT];
-	u8 res5[IFC_FTIM_REG_LEN - IFC_FTIM_USED_LEN];
-	u32 rb_stat;
-	u32 res6[0x2];
-	u32 ifc_gcr;
-	u32 res7[0x2];
-	u32 cm_evter_stat;
-	u32 res8[0x2];
-	u32 cm_evter_en;
-	u32 res9[0x2];
-	u32 cm_evter_intr_en;
-	u32 res10[0x2];
-	u32 cm_erattr0;
-	u32 cm_erattr1;
-	u32 res11[0x2];
-	u32 ifc_ccr;
-	u32 ifc_csr;
-	u32 res12[0x2EB];
-	struct fsl_ifc_nand ifc_nand;
-	struct fsl_ifc_nor ifc_nor;
-	struct fsl_ifc_gpcm ifc_gpcm;
-};
-
-#ifdef CONFIG_SYS_FSL_ERRATUM_IFC_A002769
-#undef CSPR_MSEL_NOR
-#define CSPR_MSEL_NOR	CSPR_MSEL_GPCM
-#endif
-#endif /* CONFIG_FSL_IFC */
-
-#endif /* __ASSEMBLY__ */
-#endif /* __ASM_PPC_FSL_IFC_H */
diff --git a/arch/powerpc/include/asm/fsl_pci.h b/arch/powerpc/include/asm/fsl_pci.h
index 749411c101..5be718b162 100644
--- a/arch/powerpc/include/asm/fsl_pci.h
+++ b/arch/powerpc/include/asm/fsl_pci.h
@@ -18,24 +18,6 @@
 /* Freescale-specific PCI config registers */
 #define FSL_PCI_PBFR		0x44
 
-#ifdef CONFIG_SYS_FSL_PCI_VER_3_X
-/* Currently only the PCIe capability is used, so hardcode the offset.
- * if more capabilities need to be justified, the capability link method
- * should be applied here
- */
-#define FSL_PCIE_CAP_ID		0x70
-#define PCI_DCR		0x78    /* PCIe Device Control Register */
-#define PCI_DSR		0x7a    /* PCIe Device Status Register */
-#define PCI_LSR		0x82    /* PCIe Link Status Register */
-#define PCI_LCR		0x80    /* PCIe Link Control Register */
-#else
-#define FSL_PCIE_CAP_ID		0x4c
-#define PCI_DCR		0x54    /* PCIe Device Control Register */
-#define PCI_DSR		0x56    /* PCIe Device Status Register */
-#define PCI_LSR		0x5e    /* PCIe Link Status Register */
-#define PCI_LCR		0x5c    /* PCIe Link Control Register */
-#endif
-
 #define FSL_PCIE_CFG_RDY	0x4b0
 #define FSL_PROG_IF_AGENT	0x1
 
diff --git a/arch/powerpc/include/asm/fsl_secure_boot.h b/arch/powerpc/include/asm/fsl_secure_boot.h
index c36f3c388a..4c7f0b1cae 100644
--- a/arch/powerpc/include/asm/fsl_secure_boot.h
+++ b/arch/powerpc/include/asm/fsl_secure_boot.h
@@ -7,6 +7,7 @@
 #ifndef __FSL_SECURE_BOOT_H
 #define __FSL_SECURE_BOOT_H
 
+#ifdef CONFIG_SECURE_BOOT
 #if defined(CONFIG_FSL_CORENET)
 #define CONFIG_SYS_PBI_FLASH_BASE		0xc0000000
 #else
@@ -15,3 +16,4 @@
 #define CONFIG_SYS_PBI_FLASH_WINDOW		0xcff80000
 
 #endif
+#endif
diff --git a/arch/powerpc/include/asm/fsl_serdes.h b/arch/powerpc/include/asm/fsl_serdes.h
index 1106d28058..f60cb0a6de 100644
--- a/arch/powerpc/include/asm/fsl_serdes.h
+++ b/arch/powerpc/include/asm/fsl_serdes.h
@@ -62,18 +62,14 @@ enum srds_prtcl {
 	QSGMII_FM1_B,		/* B indicates MACs 5,6,9,10 */
 	QSGMII_FM2_A,
 	QSGMII_FM2_B,
+	XFI_FM1_MAC1,
+	XFI_FM1_MAC2,
 	XFI_FM1_MAC9,
 	XFI_FM1_MAC10,
 	XFI_FM2_MAC9,
 	XFI_FM2_MAC10,
 	INTERLAKEN,
-	SGMII_SW1_DTSEC1,	/* SW indicates on L2 switch */
-	SGMII_SW1_DTSEC2,
-	SGMII_SW1_DTSEC3,
-	SGMII_SW1_DTSEC4,
-	SGMII_SW1_DTSEC5,
-	SGMII_SW1_DTSEC6,
-	QSGMII_SW1_A,		/* SW indicates on L2 swtich */
+	QSGMII_SW1_A,		/* Indicates ports on L2 Switch */
 	QSGMII_SW1_B,
 };
 
@@ -86,6 +82,7 @@ enum srds {
 
 int is_serdes_configured(enum srds_prtcl device);
 void fsl_serdes_init(void);
+const char *serdes_clock_to_string(u32 clock);
 
 #ifdef CONFIG_FSL_CORENET
 #ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
diff --git a/arch/powerpc/include/asm/immap_512x.h b/arch/powerpc/include/asm/immap_512x.h
index 01c9efff97..bed80aa933 100644
--- a/arch/powerpc/include/asm/immap_512x.h
+++ b/arch/powerpc/include/asm/immap_512x.h
@@ -279,8 +279,8 @@ typedef struct ddr512x {
 	u32 self_refresh_cmd_5;	/* Enter/Exit Self Refresh Registers */
 	u32 self_refresh_cmd_6;	/* Enter/Exit Self Refresh Registers */
 	u32 self_refresh_cmd_7;	/* Enter/Exit Self Refresh Registers */
-	u32 DQS_config_offset_count;	/* DQS Config Offset Count */
-	u32 DQS_config_offset_time;	/* DQS Config Offset Time */
+	u32 dqs_config_offset_count;	/* DQS Config Offset Count */
+	u32 dqs_config_offset_time;	/* DQS Config Offset Time */
 	u32 DQS_delay_status;	/* DQS Delay Status */
 	u32 res0[0xF];
 	u32 prioman_config1;	/* Priority Manager Configuration */
@@ -1255,9 +1255,9 @@ static inline u32 get_pata_base (void)
 }
 #endif	/* __ASSEMBLY__ */
 
-#define CONFIG_SYS_MPC512x_USB_OFFSET   0x4000
-#define CONFIG_SYS_MPC512x_USB_ADDR \
-			(CONFIG_SYS_IMMR + CONFIG_SYS_MPC512x_USB_OFFSET)
+#define CONFIG_SYS_MPC512x_USB1_OFFSET   0x4000
+#define CONFIG_SYS_MPC512x_USB1_ADDR \
+			(CONFIG_SYS_IMMR + CONFIG_SYS_MPC512x_USB1_OFFSET)
 
 #define IIM_BASE_ADDR	(CONFIG_SYS_IMMR + offsetof(immap_t, iim))
 
diff --git a/arch/powerpc/include/asm/immap_83xx.h b/arch/powerpc/include/asm/immap_83xx.h
index 57189c9136..251840255b 100644
--- a/arch/powerpc/include/asm/immap_83xx.h
+++ b/arch/powerpc/include/asm/immap_83xx.h
@@ -14,6 +14,7 @@
 #ifndef __IMMAP_83xx__
 #define __IMMAP_83xx__
 
+#include <fsl_immap.h>
 #include <asm/types.h>
 #include <asm/fsl_i2c.h>
 #include <asm/mpc8xxx_spi.h>
@@ -277,107 +278,10 @@ typedef struct qesba83xx {
 } qesba83xx_t;
 
 /*
- * DDR Memory Controller Memory Map
+ * DDR Memory Controller Memory Map for DDR1
+ * The structure of DDR2, or DDR3 is defined in fsl_immap.h
  */
-#if defined(CONFIG_FSL_DDR2) || defined(CONFIG_FSL_DDR3)
-typedef struct ccsr_ddr {
-	u32	cs0_bnds;		/* Chip Select 0 Memory Bounds */
-	u8	res1[4];
-	u32	cs1_bnds;		/* Chip Select 1 Memory Bounds */
-	u8	res2[4];
-	u32	cs2_bnds;		/* Chip Select 2 Memory Bounds */
-	u8	res3[4];
-	u32	cs3_bnds;		/* Chip Select 3 Memory Bounds */
-	u8	res4[100];
-	u32	cs0_config;		/* Chip Select Configuration */
-	u32	cs1_config;		/* Chip Select Configuration */
-	u32	cs2_config;		/* Chip Select Configuration */
-	u32	cs3_config;		/* Chip Select Configuration */
-	u8	res4a[48];
-	u32	cs0_config_2;		/* Chip Select Configuration 2 */
-	u32	cs1_config_2;		/* Chip Select Configuration 2 */
-	u32	cs2_config_2;		/* Chip Select Configuration 2 */
-	u32	cs3_config_2;		/* Chip Select Configuration 2 */
-	u8	res5[48];
-	u32	timing_cfg_3;		/* SDRAM Timing Configuration 3 */
-	u32	timing_cfg_0;		/* SDRAM Timing Configuration 0 */
-	u32	timing_cfg_1;		/* SDRAM Timing Configuration 1 */
-	u32	timing_cfg_2;		/* SDRAM Timing Configuration 2 */
-	u32	sdram_cfg;		/* SDRAM Control Configuration */
-	u32	sdram_cfg_2;		/* SDRAM Control Configuration 2 */
-	u32	sdram_mode;		/* SDRAM Mode Configuration */
-	u32	sdram_mode_2;		/* SDRAM Mode Configuration 2 */
-	u32	sdram_md_cntl;		/* SDRAM Mode Control */
-	u32	sdram_interval;		/* SDRAM Interval Configuration */
-	u32	sdram_data_init;	/* SDRAM Data initialization */
-	u8	res6[4];
-	u32	sdram_clk_cntl;		/* SDRAM Clock Control */
-	u8	res7[20];
-	u32	init_addr;		/* training init addr */
-	u32	init_ext_addr;		/* training init extended addr */
-	u8	res8_1[16];
-	u32	timing_cfg_4;		/* SDRAM Timing Configuration 4 */
-	u32	timing_cfg_5;		/* SDRAM Timing Configuration 5 */
-	u8	reg8_1a[8];
-	u32	ddr_zq_cntl;		/* ZQ calibration control*/
-	u32	ddr_wrlvl_cntl;		/* write leveling control*/
-	u8	reg8_1aa[4];
-	u32	ddr_sr_cntr;		/* self refresh counter */
-	u32	ddr_sdram_rcw_1;	/* Control Words 1 */
-	u32	ddr_sdram_rcw_2;	/* Control Words 2 */
-	u8	reg_1ab[8];
-	u32	ddr_wrlvl_cntl_2;	/* write leveling control 2 */
-	u32	ddr_wrlvl_cntl_3;	/* write leveling control 3 */
-	u8	res8_1b[104];
-	u32	sdram_mode_3;		/* SDRAM Mode Configuration 3 */
-	u32	sdram_mode_4;		/* SDRAM Mode Configuration 4 */
-	u32	sdram_mode_5;		/* SDRAM Mode Configuration 5 */
-	u32	sdram_mode_6;		/* SDRAM Mode Configuration 6 */
-	u32	sdram_mode_7;		/* SDRAM Mode Configuration 7 */
-	u32	sdram_mode_8;		/* SDRAM Mode Configuration 8 */
-	u8	res8_1ba[0x908];
-	u32	ddr_dsr1;		/* Debug Status 1 */
-	u32	ddr_dsr2;		/* Debug Status 2 */
-	u32	ddr_cdr1;		/* Control Driver 1 */
-	u32	ddr_cdr2;		/* Control Driver 2 */
-	u8	res8_1c[200];
-	u32	ip_rev1;		/* IP Block Revision 1 */
-	u32	ip_rev2;		/* IP Block Revision 2 */
-	u32	eor;			/* Enhanced Optimization Register */
-	u8	res8_2[252];
-	u32	mtcr;			/* Memory Test Control Register */
-	u8	res8_3[28];
-	u32	mtp1;			/* Memory Test Pattern 1 */
-	u32	mtp2;			/* Memory Test Pattern 2 */
-	u32	mtp3;			/* Memory Test Pattern 3 */
-	u32	mtp4;			/* Memory Test Pattern 4 */
-	u32	mtp5;			/* Memory Test Pattern 5 */
-	u32	mtp6;			/* Memory Test Pattern 6 */
-	u32	mtp7;			/* Memory Test Pattern 7 */
-	u32	mtp8;			/* Memory Test Pattern 8 */
-	u32	mtp9;			/* Memory Test Pattern 9 */
-	u32	mtp10;			/* Memory Test Pattern 10 */
-	u8	res8_4[184];
-	u32	data_err_inject_hi;	/* Data Path Err Injection Mask High */
-	u32	data_err_inject_lo;	/* Data Path Err Injection Mask Low */
-	u32	ecc_err_inject;		/* Data Path Err Injection Mask ECC */
-	u8	res9[20];
-	u32	capture_data_hi;	/* Data Path Read Capture High */
-	u32	capture_data_lo;	/* Data Path Read Capture Low */
-	u32	capture_ecc;		/* Data Path Read Capture ECC */
-	u8	res10[20];
-	u32	err_detect;		/* Error Detect */
-	u32	err_disable;		/* Error Disable */
-	u32	err_int_en;
-	u32	capture_attributes;	/* Error Attrs Capture */
-	u32	capture_address;	/* Error Addr Capture */
-	u32	capture_ext_address;	/* Error Extended Addr Capture */
-	u32	err_sbe;		/* Single-Bit ECC Error Management */
-	u8	res11[164];
-	u32	debug[32];		/* debug_1 to debug_32 */
-	u8	res12[128];
-} ccsr_ddr_t;
-#else
+#if !defined(CONFIG_SYS_FSL_DDR2) && !defined(CONFIG_SYS_FSL_DDR3)
 typedef struct ddr_cs_bnds {
 	u32 csbnds;
 	u8 res0[4];
@@ -739,8 +643,8 @@ typedef struct immap {
 	u8			dll_ddr[0x100];
 	u8			dll_lbc[0x100];
 	u8			res1[0xE00];
-#if defined(CONFIG_FSL_DDR2) || defined(CONFIG_FSL_DDR3)
-	ccsr_ddr_t		ddr;	/* DDR Memory Controller Memory */
+#if defined(CONFIG_SYS_FSL_DDR2) || defined(CONFIG_SYS_FSL_DDR3)
+	struct ccsr_ddr		ddr;	/* DDR Memory Controller Memory */
 #else
 	ddr83xx_t		ddr;	/* DDR Memory Controller Memory */
 #endif
@@ -763,10 +667,17 @@ typedef struct immap {
 	u8			res7[0xC0000];
 } immap_t;
 
+#ifndef	CONFIG_MPC834x
 #ifdef CONFIG_HAS_FSL_MPH_USB
-#define CONFIG_SYS_MPC83xx_USB_OFFSET  0x22000	/* use the MPH controller */
+#define CONFIG_SYS_MPC83xx_USB1_OFFSET  0x22000	/* use the MPH controller */
+#define CONFIG_SYS_MPC83xx_USB2_OFFSET	0
+#else
+#define CONFIG_SYS_MPC83xx_USB1_OFFSET	0
+#define CONFIG_SYS_MPC83xx_USB2_OFFSET  0x23000	/* use the DR controller */
+#endif
 #else
-#define CONFIG_SYS_MPC83xx_USB_OFFSET  0x23000	/* use the DR controller */
+#define CONFIG_SYS_MPC83xx_USB1_OFFSET	0x22000
+#define CONFIG_SYS_MPC83xx_USB2_OFFSET  0x23000
 #endif
 
 #elif defined(CONFIG_MPC8313)
@@ -1022,7 +933,7 @@ typedef struct immap {
 #endif
 
 #define CONFIG_SYS_MPC8xxx_DDR_OFFSET	(0x2000)
-#define CONFIG_SYS_MPC8xxx_DDR_ADDR \
+#define CONFIG_SYS_FSL_DDR_ADDR \
 			(CONFIG_SYS_IMMR + CONFIG_SYS_MPC8xxx_DDR_OFFSET)
 #define CONFIG_SYS_MPC83xx_DMA_OFFSET	(0x8000)
 #define CONFIG_SYS_MPC83xx_DMA_ADDR \
@@ -1031,11 +942,15 @@ typedef struct immap {
 #define CONFIG_SYS_MPC83xx_ESDHC_ADDR \
 			(CONFIG_SYS_IMMR + CONFIG_SYS_MPC83xx_ESDHC_OFFSET)
 
-#ifndef CONFIG_SYS_MPC83xx_USB_OFFSET
-#define CONFIG_SYS_MPC83xx_USB_OFFSET  0x23000
+#ifndef CONFIG_SYS_MPC83xx_USB1_OFFSET
+#define CONFIG_SYS_MPC83xx_USB1_OFFSET  0x23000
+#endif
+#define CONFIG_SYS_MPC83xx_USB1_ADDR \
+			(CONFIG_SYS_IMMR + CONFIG_SYS_MPC83xx_USB1_OFFSET)
+#if defined(CONFIG_MPC834x)
+#define CONFIG_SYS_MPC83xx_USB2_ADDR \
+			(CONFIG_SYS_IMMR + CONFIG_SYS_MPC83xx_USB2_OFFSET)
 #endif
-#define CONFIG_SYS_MPC83xx_USB_ADDR \
-			(CONFIG_SYS_IMMR + CONFIG_SYS_MPC83xx_USB_OFFSET)
 #define CONFIG_SYS_LBC_ADDR (&((immap_t *)CONFIG_SYS_IMMR)->im_lbc)
 
 #define CONFIG_SYS_TSEC1_OFFSET		0x24000
diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h
index 3a10d778f1..4b6f9d018e 100644
--- a/arch/powerpc/include/asm/immap_85xx.h
+++ b/arch/powerpc/include/asm/immap_85xx.h
@@ -15,9 +15,10 @@
 #include <asm/types.h>
 #include <asm/fsl_dma.h>
 #include <asm/fsl_i2c.h>
-#include <asm/fsl_ifc.h>
+#include <fsl_ifc.h>
 #include <asm/fsl_lbc.h>
 #include <asm/fsl_fman.h>
+#include <fsl_immap.h>
 
 typedef struct ccsr_local {
 	u32	ccsrbarh;	/* CCSR Base Addr High */
@@ -112,105 +113,6 @@ typedef struct ccsr_local_ecm {
 	u8	res24[492];
 } ccsr_local_ecm_t;
 
-/* DDR memory controller registers */
-typedef struct ccsr_ddr {
-	u32	cs0_bnds;		/* Chip Select 0 Memory Bounds */
-	u8	res1[4];
-	u32	cs1_bnds;		/* Chip Select 1 Memory Bounds */
-	u8	res2[4];
-	u32	cs2_bnds;		/* Chip Select 2 Memory Bounds */
-	u8	res3[4];
-	u32	cs3_bnds;		/* Chip Select 3 Memory Bounds */
-	u8	res4[100];
-	u32	cs0_config;		/* Chip Select Configuration */
-	u32	cs1_config;		/* Chip Select Configuration */
-	u32	cs2_config;		/* Chip Select Configuration */
-	u32	cs3_config;		/* Chip Select Configuration */
-	u8	res4a[48];
-	u32	cs0_config_2;		/* Chip Select Configuration 2 */
-	u32	cs1_config_2;		/* Chip Select Configuration 2 */
-	u32	cs2_config_2;		/* Chip Select Configuration 2 */
-	u32	cs3_config_2;		/* Chip Select Configuration 2 */
-	u8	res5[48];
-	u32	timing_cfg_3;		/* SDRAM Timing Configuration 3 */
-	u32	timing_cfg_0;		/* SDRAM Timing Configuration 0 */
-	u32	timing_cfg_1;		/* SDRAM Timing Configuration 1 */
-	u32	timing_cfg_2;		/* SDRAM Timing Configuration 2 */
-	u32	sdram_cfg;		/* SDRAM Control Configuration */
-	u32	sdram_cfg_2;		/* SDRAM Control Configuration 2 */
-	u32	sdram_mode;		/* SDRAM Mode Configuration */
-	u32	sdram_mode_2;		/* SDRAM Mode Configuration 2 */
-	u32	sdram_md_cntl;		/* SDRAM Mode Control */
-	u32	sdram_interval;		/* SDRAM Interval Configuration */
-	u32	sdram_data_init;	/* SDRAM Data initialization */
-	u8	res6[4];
-	u32	sdram_clk_cntl;		/* SDRAM Clock Control */
-	u8	res7[20];
-	u32	init_addr;		/* training init addr */
-	u32	init_ext_addr;		/* training init extended addr */
-	u8	res8_1[16];
-	u32	timing_cfg_4;		/* SDRAM Timing Configuration 4 */
-	u32	timing_cfg_5;		/* SDRAM Timing Configuration 5 */
-	u8	reg8_1a[8];
-	u32	ddr_zq_cntl;		/* ZQ calibration control*/
-	u32	ddr_wrlvl_cntl;		/* write leveling control*/
-	u8	reg8_1aa[4];
-	u32	ddr_sr_cntr;		/* self refresh counter */
-	u32	ddr_sdram_rcw_1;	/* Control Words 1 */
-	u32	ddr_sdram_rcw_2;	/* Control Words 2 */
-	u8	reg_1ab[8];
-	u32	ddr_wrlvl_cntl_2;	/* write leveling control 2 */
-	u32	ddr_wrlvl_cntl_3;	/* write leveling control 3 */
-	u8	res8_1b[104];
-	u32	sdram_mode_3;		/* SDRAM Mode Configuration 3 */
-	u32	sdram_mode_4;		/* SDRAM Mode Configuration 4 */
-	u32	sdram_mode_5;		/* SDRAM Mode Configuration 5 */
-	u32	sdram_mode_6;		/* SDRAM Mode Configuration 6 */
-	u32	sdram_mode_7;		/* SDRAM Mode Configuration 7 */
-	u32	sdram_mode_8;		/* SDRAM Mode Configuration 8 */
-	u8	res8_1ba[0x908];
-	u32	ddr_dsr1;		/* Debug Status 1 */
-	u32	ddr_dsr2;		/* Debug Status 2 */
-	u32	ddr_cdr1;		/* Control Driver 1 */
-	u32	ddr_cdr2;		/* Control Driver 2 */
-	u8	res8_1c[200];
-	u32	ip_rev1;		/* IP Block Revision 1 */
-	u32	ip_rev2;		/* IP Block Revision 2 */
-	u32	eor;			/* Enhanced Optimization Register */
-	u8	res8_2[252];
-	u32	mtcr;			/* Memory Test Control Register */
-	u8	res8_3[28];
-	u32	mtp1;			/* Memory Test Pattern 1 */
-	u32	mtp2;			/* Memory Test Pattern 2 */
-	u32	mtp3;			/* Memory Test Pattern 3 */
-	u32	mtp4;			/* Memory Test Pattern 4 */
-	u32	mtp5;			/* Memory Test Pattern 5 */
-	u32	mtp6;			/* Memory Test Pattern 6 */
-	u32	mtp7;			/* Memory Test Pattern 7 */
-	u32	mtp8;			/* Memory Test Pattern 8 */
-	u32	mtp9;			/* Memory Test Pattern 9 */
-	u32	mtp10;			/* Memory Test Pattern 10 */
-	u8	res8_4[184];
-	u32	data_err_inject_hi;	/* Data Path Err Injection Mask High */
-	u32	data_err_inject_lo;	/* Data Path Err Injection Mask Low */
-	u32	ecc_err_inject;		/* Data Path Err Injection Mask ECC */
-	u8	res9[20];
-	u32	capture_data_hi;	/* Data Path Read Capture High */
-	u32	capture_data_lo;	/* Data Path Read Capture Low */
-	u32	capture_ecc;		/* Data Path Read Capture ECC */
-	u8	res10[20];
-	u32	err_detect;		/* Error Detect */
-	u32	err_disable;		/* Error Disable */
-	u32	err_int_en;
-	u32	capture_attributes;	/* Error Attrs Capture */
-	u32	capture_address;	/* Error Addr Capture */
-	u32	capture_ext_address;	/* Error Extended Addr Capture */
-	u32	err_sbe;		/* Single-Bit ECC Error Management */
-	u8	res11[164];
-	u32	debug[32];		/* debug_1 to debug_32 */
-	u8	res12[128];
-} ccsr_ddr_t;
-
 #define DDR_EOR_RD_BDW_OPT_DIS	0x80000000 /* Read BDW Opt. disable */
 #define DDR_EOR_ADDR_HASH_EN	0x40000000 /* Address hash enabled */
 
@@ -282,7 +184,9 @@ typedef struct ccsr_pcix {
 	u32	int_ack;	/* PCIX IRQ Acknowledge */
 	u8	res000c[52];
 	u32	liodn_base;	/* PCIX LIODN base register */
-	u8	res0044[3004];
+	u8	res0044[2996];
+	u32	ipver1;		/* PCIX IP block revision register 1 */
+	u32	ipver2;		/* PCIX IP block revision register 2 */
 	u32	potar0;		/* PCIX Outbound Transaction Addr 0 */
 	u32	potear0;	/* PCIX Outbound Translation Extended Addr 0 */
 	u32	powbar0;	/* PCIX Outbound Window Base Addr 0 */
@@ -1671,6 +1575,7 @@ typedef struct cpc_corenet {
 #define CPC_HDBCR0_CDQ_SPEC_DIS	0x08000000
 #define CPC_HDBCR0_TAG_ECC_SCRUB_DIS	0x01000000
 #define CPC_HDBCR0_DATA_ECC_SCRUB_DIS	0x00400000
+#define CPC_HDBCR0_SPLRU_LEVEL_EN	0x003c0000
 #endif /* CONFIG_SYS_FSL_CPC */
 
 /* Global Utilities Block */
@@ -1716,6 +1621,8 @@ typedef struct ccsr_gur {
 #define FSL_CORENET_DEVDISR2_DTSEC1_10	0x00400000
 #define FSL_CORENET_DEVDISR2_10GEC1_1	0x00800000
 #define FSL_CORENET_DEVDISR2_10GEC1_2	0x00400000
+#define FSL_CORENET_DEVDISR2_10GEC1_3	0x80000000
+#define FSL_CORENET_DEVDISR2_10GEC1_4	0x40000000
 #define FSL_CORENET_DEVDISR2_DTSEC2_1	0x00080000
 #define FSL_CORENET_DEVDISR2_DTSEC2_2	0x00040000
 #define FSL_CORENET_DEVDISR2_DTSEC2_3	0x00020000
@@ -1815,6 +1722,9 @@ typedef struct ccsr_gur {
 	u32	rstrqpblsr;	/* Reset request preboot loader status */
 	u8	res11[8];
 	u32	rstrqmr1;	/* Reset request mask */
+#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
+#define FSL_CORENET_RSTRQMR1_SRDS_RST_MSK      0x00000800
+#endif
 	u8	res12[4];
 	u32	rstrqsr1;	/* Reset request status */
 	u8	res13[4];
@@ -1846,11 +1756,33 @@ typedef struct ccsr_gur {
 #define FSL_CORENET2_RCWSR4_SRDS2_PRTCL	0x00ff0000
 #define FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT	16
 #define FSL_CORENET_RCWSR6_BOOT_LOC	0x0f800000
-#elif defined(CONFIG_PPC_T1040)
+#elif defined(CONFIG_PPC_T1040) || defined(CONFIG_PPC_T1042) ||\
+defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022)
 #define FSL_CORENET2_RCWSR4_SRDS1_PRTCL	0xff000000
 #define FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT	24
 #define FSL_CORENET2_RCWSR4_SRDS2_PRTCL	0x00fe0000
 #define FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT	17
+#define FSL_CORENET_RCWSR13_EC1	0x30000000 /* bits 418..419 */
+#define FSL_CORENET_RCWSR13_EC1_FM1_DTSEC4_RGMII	0x00000000
+#define FSL_CORENET_RCWSR13_EC1_FM1_GPIO	0x10000000
+#define FSL_CORENET_RCWSR13_EC1_FM1_DTSEC4_MII	0x20000000
+#define FSL_CORENET_RCWSR13_EC2	0x0c000000 /* bits 420..421 */
+#define FSL_CORENET_RCWSR13_EC2_FM1_DTSEC5_RGMII	0x00000000
+#define FSL_CORENET_RCWSR13_EC2_FM1_GPIO	0x10000000
+#define FSL_CORENET_RCWSR13_EC2_FM1_DTSEC5_MII	0x20000000
+#define FSL_CORENET_RCWSR13_MAC2_GMII_SEL	0x00000080
+#define FSL_CORENET_RCWSR13_MAC2_GMII_SEL_L2_SWITCH	0x00000000
+#define FSL_CORENET_RCWSR13_MAC2_GMII_SEL_ENET_PORT	0x80000000
+#define CONFIG_SYS_FSL_SCFG_PIXCLKCR_OFFSET	0x28
+#define PXCKEN_MASK	0x80000000
+#define PXCK_MASK	0x00FF0000
+#define PXCK_BITS_START	16
+#elif defined(CONFIG_PPC_T2080) || defined(CONFIG_PPC_T2081)
+#define FSL_CORENET2_RCWSR4_SRDS1_PRTCL		0xff000000
+#define FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT	24
+#define FSL_CORENET2_RCWSR4_SRDS2_PRTCL		0x00ff0000
+#define FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT	16
+#define FSL_CORENET_RCWSR6_BOOT_LOC		0x0f800000
 #endif
 #define FSL_CORENET2_RCWSR5_SRDS_PLL_PD_S1_PLL1	0x00800000
 #define FSL_CORENET2_RCWSR5_SRDS_PLL_PD_S1_PLL2	0x00400000
@@ -1860,6 +1792,9 @@ typedef struct ccsr_gur {
 #define FSL_CORENET2_RCWSR5_SRDS_PLL_PD_S3_PLL2	0x00040000
 #define FSL_CORENET2_RCWSR5_SRDS_PLL_PD_S4_PLL1	0x00020000
 #define FSL_CORENET2_RCWSR5_SRDS_PLL_PD_S4_PLL2	0x00010000
+#define FSL_CORENET2_RCWSR5_DDR_REFCLK_SEL_SHIFT 4
+#define FSL_CORENET2_RCWSR5_DDR_REFCLK_SEL_MASK	0x00000011
+#define FSL_CORENET2_RCWSR5_DDR_REFCLK_SINGLE_CLK	1
 
 #else /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */
 #define FSL_CORENET_RCWSR0_MEM_PLL_RAT_SHIFT	17
@@ -1914,6 +1849,15 @@ typedef struct ccsr_gur {
 #define FSL_CORENET_RCWSR13_EC2_FM1_DTSEC6_RGMII	0x08000000
 #define FSL_CORENET_RCWSR13_EC2_FM1_GPIO		0x10000000
 #endif
+#if defined(CONFIG_PPC_T2080) || defined(CONFIG_PPC_T2081)
+#define FSL_CORENET_RCWSR13_EC1			0x60000000 /* bits 417..418 */
+#define FSL_CORENET_RCWSR13_EC1_DTSEC3_RGMII	0x00000000
+#define FSL_CORENET_RCWSR13_EC1_GPIO		0x40000000
+#define FSL_CORENET_RCWSR13_EC2			0x18000000 /* bits 419..420 */
+#define FSL_CORENET_RCWSR13_EC2_DTSEC4_RGMII	0x00000000
+#define FSL_CORENET_RCWSR13_EC2_DTSEC10_RGMII	0x08000000
+#define FSL_CORENET_RCWSR13_EC2_GPIO		0x10000000
+#endif
 	u8	res18[192];
 	u32	scratchrw[4];	/* Scratch Read/Write */
 	u8	res19[240];
@@ -2016,20 +1960,13 @@ typedef struct ccsr_clk {
 		u8  res_004[0x0c];
 		u32 clkcgnhwacsr;/* clock generator n hardware accelerator */
 		u8  res_014[0x0c];
-	} clkcsr[8];
-	u8	res_100[0x700]; /* 0x100 */
-	u32	pllc1gsr;	/* 0x800 Cluster PLL 1 General Status */
-	u8	res10[0x1c];
-	u32	pllc2gsr;	/* 0x820 Cluster PLL 2 General Status */
-	u8	res11[0x1c];
-	u32	pllc3gsr;	/* 0x840 Cluster PLL 3 General Status */
-	u8	res12[0x1c];
-	u32	pllc4gsr;	/* 0x860 Cluster PLL 4 General Status */
-	u8	res13[0x1c];
-	u32	pllc5gsr;	/* 0x880 Cluster PLL 5 General Status */
-	u8	res14[0x1c];
-	u32	pllc6gsr;	/* 0x8a0 Cluster PLL 6 General Status */
-	u8	res15[0x35c];
+	} clkcsr[12];
+	u8	res_100[0x680]; /* 0x100 */
+	struct {
+		u32 pllcngsr;
+		u8 res10[0x1c];
+	} pllcgsr[12];
+	u8	res21[0x280];
 	u32	pllpgsr;	/* 0xc00 Platform PLL General Status */
 	u8	res16[0x1c];
 	u32	plldgsr;	/* 0xc20 DDR PLL General Status */
@@ -2562,6 +2499,7 @@ typedef struct serdes_corenet {
 #define SRDS_RSTCTL_SDEN	0x00000020
 #define SRDS_RSTCTL_SDRST_B	0x00000040
 #define SRDS_RSTCTL_PLLRST_B	0x00000080
+#define SRDS_RSTCTL_RSTERR_SHIFT  29
 		u32	pllcr0; /* PLL Control Register 0 */
 #define SRDS_PLLCR0_POFF		0x80000000
 #define SRDS_PLLCR0_RFCK_SEL_MASK	0x70000000
@@ -2571,6 +2509,7 @@ typedef struct serdes_corenet {
 #define SRDS_PLLCR0_RFCK_SEL_150	0x30000000
 #define SRDS_PLLCR0_RFCK_SEL_161_13	0x40000000
 #define SRDS_PLLCR0_RFCK_SEL_122_88	0x50000000
+#define SRDS_PLLCR0_DCBIAS_OUT_EN      0x02000000
 #define SRDS_PLLCR0_FRATE_SEL_MASK	0x000f0000
 #define SRDS_PLLCR0_FRATE_SEL_5		0x00000000
 #define SRDS_PLLCR0_FRATE_SEL_3_75	0x00050000
@@ -2578,9 +2517,22 @@ typedef struct serdes_corenet {
 #define SRDS_PLLCR0_FRATE_SEL_4		0x00070000
 #define SRDS_PLLCR0_FRATE_SEL_3_12	0x00090000
 #define SRDS_PLLCR0_FRATE_SEL_3		0x000a0000
+#define SRDS_PLLCR0_DCBIAS_OVRD		0x000000F0
+#define SRDS_PLLCR0_DCBIAS_OVRD_SHIFT	4
 		u32	pllcr1; /* PLL Control Register 1 */
-#define SRDS_PLLCR1_PLL_BWSEL	0x08000000
-		u32	res_0c;	/* 0x00c */
+#define SRDS_PLLCR1_BCAP_EN		0x20000000
+#define SRDS_PLLCR1_BCAP_OVD		0x10000000
+#define SRDS_PLLCR1_PLL_FCAP		0x001F8000
+#define SRDS_PLLCR1_PLL_FCAP_SHIFT	15
+#define SRDS_PLLCR1_PLL_BWSEL		0x08000000
+#define SRDS_PLLCR1_BYP_CAL		0x02000000
+		u32	pllsr2;	/* At 0x00c, PLL Status Register 2 */
+#define SRDS_PLLSR2_BCAP_EN		0x00800000
+#define SRDS_PLLSR2_BCAP_EN_SHIFT	23
+#define SRDS_PLLSR2_FCAP		0x003F0000
+#define SRDS_PLLSR2_FCAP_SHIFT		16
+#define SRDS_PLLSR2_DCBIAS		0x000F0000
+#define SRDS_PLLSR2_DCBIAS_SHIFT	16
 		u32	pllcr3;
 		u32	pllcr4;
 		u8	res_18[0x20-0x18];
@@ -2915,8 +2867,10 @@ struct ccsr_pman {
 #define CONFIG_SYS_FSL_CORENET_SERDES_OFFSET	0xEA000
 #define CONFIG_SYS_FSL_CORENET_SERDES2_OFFSET	0xEB000
 #define CONFIG_SYS_FSL_CPC_OFFSET		0x10000
+#define CONFIG_SYS_FSL_SCFG_OFFSET		0xFC000
 #define CONFIG_SYS_MPC85xx_DMA1_OFFSET		0x100000
 #define CONFIG_SYS_MPC85xx_DMA2_OFFSET		0x101000
+#define CONFIG_SYS_MPC85xx_DMA3_OFFSET		0x102000
 #define CONFIG_SYS_MPC85xx_DMA_OFFSET		CONFIG_SYS_MPC85xx_DMA1_OFFSET
 #define CONFIG_SYS_MPC85xx_ESPI_OFFSET		0x110000
 #define CONFIG_SYS_MPC85xx_ESDHC_OFFSET		0x114000
@@ -2938,7 +2892,6 @@ struct ccsr_pman {
 #endif
 #define CONFIG_SYS_MPC85xx_USB1_OFFSET		0x210000
 #define CONFIG_SYS_MPC85xx_USB2_OFFSET		0x211000
-#define CONFIG_SYS_MPC85xx_USB_OFFSET		CONFIG_SYS_MPC85xx_USB1_OFFSET
 #define CONFIG_SYS_MPC85xx_USB1_PHY_OFFSET 0x214000
 #define CONFIG_SYS_MPC85xx_USB2_PHY_OFFSET 0x214100
 #define CONFIG_SYS_MPC85xx_SATA1_OFFSET		0x220000
@@ -2991,7 +2944,7 @@ struct ccsr_pman {
 #define CONFIG_SYS_MPC85xx_IFC_OFFSET		0x1e000
 #define CONFIG_SYS_MPC85xx_L2_OFFSET		0x20000
 #define CONFIG_SYS_MPC85xx_DMA_OFFSET		0x21000
-#define CONFIG_SYS_MPC85xx_USB_OFFSET		0x22000
+#define CONFIG_SYS_MPC85xx_USB1_OFFSET		0x22000
 #define CONFIG_SYS_MPC85xx_USB2_OFFSET		0x23000
 #ifdef CONFIG_TSECV2
 #define CONFIG_SYS_TSEC1_OFFSET			0xB0000
@@ -3032,6 +2985,10 @@ struct ccsr_pman {
 
 #define CONFIG_SYS_FSL_CPC_ADDR	\
 	(CONFIG_SYS_CCSRBAR + CONFIG_SYS_FSL_CPC_OFFSET)
+#define CONFIG_SYS_FSL_SCFG_ADDR	\
+	(CONFIG_SYS_CCSRBAR + CONFIG_SYS_FSL_SCFG_OFFSET)
+#define CONFIG_SYS_FSL_SCFG_PIXCLK_ADDR	\
+	(CONFIG_SYS_FSL_SCFG_ADDR + CONFIG_SYS_FSL_SCFG_PIXCLKCR_OFFSET)
 #define CONFIG_SYS_FSL_QMAN_ADDR \
 	(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_QMAN_OFFSET)
 #define CONFIG_SYS_FSL_BMAN_ADDR \
@@ -3052,11 +3009,11 @@ struct ccsr_pman {
 	(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_RCPM_OFFSET)
 #define CONFIG_SYS_MPC85xx_ECM_ADDR \
 	(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_ECM_OFFSET)
-#define CONFIG_SYS_MPC8xxx_DDR_ADDR \
+#define CONFIG_SYS_FSL_DDR_ADDR \
 	(CONFIG_SYS_IMMR + CONFIG_SYS_MPC8xxx_DDR_OFFSET)
-#define CONFIG_SYS_MPC8xxx_DDR2_ADDR \
+#define CONFIG_SYS_FSL_DDR2_ADDR \
 	(CONFIG_SYS_IMMR + CONFIG_SYS_MPC8xxx_DDR2_OFFSET)
-#define CONFIG_SYS_MPC8xxx_DDR3_ADDR \
+#define CONFIG_SYS_FSL_DDR3_ADDR \
 	(CONFIG_SYS_IMMR + CONFIG_SYS_MPC8xxx_DDR3_OFFSET)
 #define CONFIG_SYS_LBC_ADDR \
 	(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_LBC_OFFSET)
@@ -3092,8 +3049,10 @@ struct ccsr_pman {
 	(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_SERDES_OFFSET)
 #define CONFIG_SYS_FSL_CORENET_SERDES2_ADDR \
 	(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_SERDES2_OFFSET)
-#define CONFIG_SYS_MPC85xx_USB_ADDR \
-	(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_USB_OFFSET)
+#define CONFIG_SYS_MPC85xx_USB1_ADDR \
+	(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_USB1_OFFSET)
+#define CONFIG_SYS_MPC85xx_USB2_ADDR \
+	(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_USB2_OFFSET)
 #define CONFIG_SYS_MPC85xx_USB1_PHY_ADDR \
 	(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_USB1_PHY_OFFSET)
 #define CONFIG_SYS_MPC85xx_USB2_PHY_ADDR \
diff --git a/arch/powerpc/include/asm/immap_86xx.h b/arch/powerpc/include/asm/immap_86xx.h
index 2a704fe6b7..177918b7f9 100644
--- a/arch/powerpc/include/asm/immap_86xx.h
+++ b/arch/powerpc/include/asm/immap_86xx.h
@@ -10,6 +10,7 @@
 #ifndef __IMMAP_86xx__
 #define __IMMAP_86xx__
 
+#include <fsl_immap.h>
 #include <asm/types.h>
 #include <asm/fsl_dma.h>
 #include <asm/fsl_lbc.h>
@@ -89,75 +90,6 @@ typedef struct ccsr_local_mcm {
 	char	res31[488];
 } ccsr_local_mcm_t;
 
-/* DDR memory controller registers(0x2000-0x3000) and (0x6000-0x7000) */
-
-typedef struct ccsr_ddr {
-	uint	cs0_bnds;		/* 0x2000 - DDR Chip Select 0 Memory Bounds */
-	char	res1[4];
-	uint	cs1_bnds;		/* 0x2008 - DDR Chip Select 1 Memory Bounds */
-	char	res2[4];
-	uint	cs2_bnds;		/* 0x2010 - DDR Chip Select 2 Memory Bounds */
-	char	res3[4];
-	uint	cs3_bnds;		/* 0x2018 - DDR Chip Select 3 Memory Bounds */
-	char	res4[4];
-	uint	cs4_bnds;		/* 0x2020 - DDR Chip Select 4 Memory Bounds */
-	char	res5[4];
-	uint	cs5_bnds;		/* 0x2028 - DDR Chip Select 5 Memory Bounds */
-	char	res6[84];
-	uint	cs0_config;		/* 0x2080 - DDR Chip Select Configuration */
-	uint	cs1_config;		/* 0x2084 - DDR Chip Select Configuration */
-	uint	cs2_config;		/* 0x2088 - DDR Chip Select Configuration */
-	uint	cs3_config;		/* 0x208c - DDR Chip Select Configuration */
-	uint	cs4_config;		/* 0x2090 - DDR Chip Select Configuration */
-	uint	cs5_config;		/* 0x2094 - DDR Chip Select Configuration */
-	char	res7[104];
-	uint	timing_cfg_3;		/* 0x2100 - DDR SDRAM Timing Configuration Register 3 */
-	uint	timing_cfg_0;		/* 0x2104 - DDR SDRAM Timing Configuration Register 0 */
-	uint	timing_cfg_1;		/* 0x2108 - DDR SDRAM Timing Configuration Register 1 */
-	uint	timing_cfg_2;		/* 0x210c - DDR SDRAM Timing Configuration Register 2 */
-	uint	sdram_cfg;		/* 0x2110 - DDR SDRAM Control Configuration 1 */
-	uint    sdram_cfg_2;            /* 0x2114 - DDR SDRAM Control Configuration 2 */
-	uint	sdram_mode;		/* 0x2118 - DDR SDRAM Mode Configuration 1 */
-	uint    sdram_mode_2;		/* 0x211c - DDR SDRAM Mode Configuration 2 */
-	uint    sdram_mode_cntl;        /* 0x2120 - DDR SDRAM Mode Control */
-	uint	sdram_interval;		/* 0x2124 - DDR SDRAM Interval Configuration */
-	uint    sdram_data_init;	/* 0x2128 - DDR SDRAM Data Initialization */
-	char	res8[4];
-	uint	sdram_clk_cntl;		/* 0x2130 - DDR SDRAM Clock Control */
-	char    res9[12];
-	uint    sdram_ocd_cntl;		/* 0x2140 - DDR SDRAM OCD Control */
-	uint    sdram_ocd_status;	/* 0x2144 - DDR SDRAM OCD Status */
-	uint    init_addr;		/* 0x2148 - DDR training initialzation address */
-	uint    init_ext_addr;		/* 0x214C - DDR training initialzation extended address */
-	char    res10[2728];
-	uint    ip_rev1;		/* 0x2BF8 - DDR IP Block Revision 1 */
-	uint    ip_rev2;		/* 0x2BFC - DDR IP Block Revision 2 */
-	char	res11[512];
-	uint	data_err_inject_hi;	/* 0x2e00 - DDR Memory Data Path Error Injection Mask High */
-	uint	data_err_inject_lo;	/* 0x2e04 - DDR Memory Data Path Error Injection Mask Low */
-	uint	ecc_err_inject;		/* 0x2e08 - DDR Memory Data Path Error Injection Mask ECC */
-	char	res12[20];
-	uint	capture_data_hi;	/* 0x2e20 - DDR Memory Data Path Read Capture High */
-	uint	capture_data_lo;	/* 0x2e24 - DDR Memory Data Path Read Capture Low */
-	uint	capture_ecc;		/* 0x2e28 - DDR Memory Data Path Read Capture ECC */
-	char	res13[20];
-	uint	err_detect;		/* 0x2e40 - DDR Memory Error Detect */
-	uint	err_disable;		/* 0x2e44 - DDR Memory Error Disable */
-	uint	err_int_en;		/* 0x2e48 - DDR Memory Error Interrupt Enable */
-	uint	capture_attributes;	/* 0x2e4c - DDR Memory Error Attributes Capture */
-	uint	capture_address;	/* 0x2e50 - DDR Memory Error Address Capture */
-	uint	capture_ext_address;	/* 0x2e54 - DDR Memory Error Extended Address Capture */
-	uint	err_sbe;		/* 0x2e58 - DDR Memory Single-Bit ECC Error Management */
-	char	res14[164];
-	uint	debug_1;		/* 0x2f00 */
-	uint	debug_2;
-	uint	debug_3;
-	uint	debug_4;
-	uint	debug_5;
-	char	res15[236];
-} ccsr_ddr_t;
-
-
 /* Daul I2C Registers(0x3000-0x4000) */
 typedef struct ccsr_i2c {
 	struct fsl_i2c	i2c[2];
@@ -1225,11 +1157,11 @@ typedef struct ccsr_wdt {
 
 typedef struct immap {
 	ccsr_local_mcm_t	im_local_mcm;
-	ccsr_ddr_t		im_ddr1;
+	struct ccsr_ddr		im_ddr1;
 	ccsr_i2c_t		im_i2c;
 	ccsr_duart_t		im_duart;
 	fsl_lbc_t		im_lbc;
-	ccsr_ddr_t		im_ddr2;
+	struct ccsr_ddr		im_ddr2;
 	char                    res1[4096];
 	ccsr_pex_t		im_pex1;
 	ccsr_pex_t		im_pex2;
@@ -1253,9 +1185,9 @@ typedef struct immap {
 extern immap_t  *immr;
 
 #define CONFIG_SYS_MPC8xxx_DDR_OFFSET	0x2000
-#define CONFIG_SYS_MPC8xxx_DDR_ADDR	(CONFIG_SYS_IMMR + CONFIG_SYS_MPC8xxx_DDR_OFFSET)
+#define CONFIG_SYS_FSL_DDR_ADDR	(CONFIG_SYS_IMMR + CONFIG_SYS_MPC8xxx_DDR_OFFSET)
 #define CONFIG_SYS_MPC8xxx_DDR2_OFFSET	0x6000
-#define CONFIG_SYS_MPC8xxx_DDR2_ADDR	(CONFIG_SYS_IMMR + CONFIG_SYS_MPC8xxx_DDR2_OFFSET)
+#define CONFIG_SYS_FSL_DDR2_ADDR	(CONFIG_SYS_IMMR + CONFIG_SYS_MPC8xxx_DDR2_OFFSET)
 #define CONFIG_SYS_MPC86xx_DMA_OFFSET	0x21000
 #define CONFIG_SYS_MPC86xx_DMA_ADDR	(CONFIG_SYS_IMMR + CONFIG_SYS_MPC86xx_DMA_OFFSET)
 #define CONFIG_SYS_MPC86xx_PIC_OFFSET	0x40000
diff --git a/arch/powerpc/include/asm/io.h b/arch/powerpc/include/asm/io.h
index 1f12c29ba8..d8b7b974d4 100644
--- a/arch/powerpc/include/asm/io.h
+++ b/arch/powerpc/include/asm/io.h
@@ -7,7 +7,6 @@
 #ifndef _PPC_IO_H
 #define _PPC_IO_H
 
-#include <linux/config.h>
 #include <asm/byteorder.h>
 
 #ifdef CONFIG_ADDR_MAP
diff --git a/arch/powerpc/include/asm/iopin_85xx.h b/arch/powerpc/include/asm/iopin_85xx.h
deleted file mode 100644
index 0f07ba355e..0000000000
--- a/arch/powerpc/include/asm/iopin_85xx.h
+++ /dev/null
@@ -1,146 +0,0 @@
-/*
- * MPC85xx I/O port pin manipulation functions
- */
-
-#ifndef _ASM_IOPIN_85xx_H_
-#define _ASM_IOPIN_85xx_H_
-
-#include <linux/types.h>
-#include <asm/immap_85xx.h>
-
-#ifdef __KERNEL__
-
-typedef struct {
-	u_char port:2;		/* port number (A=0, B=1, C=2, D=3) */
-	u_char pin:5;		/* port pin (0-31) */
-	u_char flag:1;		/* for whatever */
-} iopin_t;
-
-#define IOPIN_PORTA	0
-#define IOPIN_PORTB	1
-#define IOPIN_PORTC	2
-#define IOPIN_PORTD	3
-
-extern __inline__ void iopin_set_high (iopin_t * iopin)
-{
-	volatile uint *datp = &((ccsr_cpm_t *) CONFIG_SYS_MPC85xx_CPM_ADDR)->im_cpm_iop.pdata;
-	datp[iopin->port * 8] |= (1 << (31 - iopin->pin));
-}
-
-extern __inline__ void iopin_set_low (iopin_t * iopin)
-{
-	volatile uint *datp = &((ccsr_cpm_t *) CONFIG_SYS_MPC85xx_CPM_ADDR)->im_cpm_iop.pdata;
-	datp[iopin->port * 8] &= ~(1 << (31 - iopin->pin));
-}
-
-extern __inline__ uint iopin_is_high (iopin_t * iopin)
-{
-	volatile uint *datp = &((ccsr_cpm_t *) CONFIG_SYS_MPC85xx_CPM_ADDR)->im_cpm_iop.pdata;
-	return (datp[iopin->port * 8] >> (31 - iopin->pin)) & 1;
-}
-
-extern __inline__ uint iopin_is_low (iopin_t * iopin)
-{
-	volatile uint *datp = &((ccsr_cpm_t *) CONFIG_SYS_MPC85xx_CPM_ADDR)->im_cpm_iop.pdata;
-	return ((datp[iopin->port * 8] >> (31 - iopin->pin)) & 1) ^ 1;
-}
-
-extern __inline__ void iopin_set_out (iopin_t * iopin)
-{
-	volatile uint *dirp = &((ccsr_cpm_t *) CONFIG_SYS_MPC85xx_CPM_ADDR)->im_cpm_iop.pdira;
-	dirp[iopin->port * 8] |= (1 << (31 - iopin->pin));
-}
-
-extern __inline__ void iopin_set_in (iopin_t * iopin)
-{
-	volatile uint *dirp = &((ccsr_cpm_t *) CONFIG_SYS_MPC85xx_CPM_ADDR)->im_cpm_iop.pdira;
-	dirp[iopin->port * 8] &= ~(1 << (31 - iopin->pin));
-}
-
-extern __inline__ uint iopin_is_out (iopin_t * iopin)
-{
-	volatile uint *dirp = &((ccsr_cpm_t *) CONFIG_SYS_MPC85xx_CPM_ADDR)->im_cpm_iop.pdira;
-	return (dirp[iopin->port * 8] >> (31 - iopin->pin)) & 1;
-}
-
-extern __inline__ uint iopin_is_in (iopin_t * iopin)
-{
-	volatile uint *dirp = &((ccsr_cpm_t *) CONFIG_SYS_MPC85xx_CPM_ADDR)->im_cpm_iop.pdira;
-	return ((dirp[iopin->port * 8] >> (31 - iopin->pin)) & 1) ^ 1;
-}
-
-extern __inline__ void iopin_set_odr (iopin_t * iopin)
-{
-	volatile uint *odrp = &((ccsr_cpm_t *) CONFIG_SYS_MPC85xx_CPM_ADDR)->im_cpm_iop.podra;
-	odrp[iopin->port * 8] |= (1 << (31 - iopin->pin));
-}
-
-extern __inline__ void iopin_set_act (iopin_t * iopin)
-{
-	volatile uint *odrp = &((ccsr_cpm_t *) CONFIG_SYS_MPC85xx_CPM_ADDR)->im_cpm_iop.podra;
-	odrp[iopin->port * 8] &= ~(1 << (31 - iopin->pin));
-}
-
-extern __inline__ uint iopin_is_odr (iopin_t * iopin)
-{
-	volatile uint *odrp = &((ccsr_cpm_t *) CONFIG_SYS_MPC85xx_CPM_ADDR)->im_cpm_iop.podra;
-	return (odrp[iopin->port * 8] >> (31 - iopin->pin)) & 1;
-}
-
-extern __inline__ uint iopin_is_act (iopin_t * iopin)
-{
-	volatile uint *odrp = &((ccsr_cpm_t *) CONFIG_SYS_MPC85xx_CPM_ADDR)->im_cpm_iop.podra;
-	return ((odrp[iopin->port * 8] >> (31 - iopin->pin)) & 1) ^ 1;
-}
-
-extern __inline__ void iopin_set_ded (iopin_t * iopin)
-{
-	volatile uint *parp = &((ccsr_cpm_t *) CONFIG_SYS_MPC85xx_CPM_ADDR)->im_cpm_iop.ppara;
-	parp[iopin->port * 8] |= (1 << (31 - iopin->pin));
-}
-
-extern __inline__ void iopin_set_gen (iopin_t * iopin)
-{
-	volatile uint *parp = &((ccsr_cpm_t *) CONFIG_SYS_MPC85xx_CPM_ADDR)->im_cpm_iop.ppara;
-	parp[iopin->port * 8] &= ~(1 << (31 - iopin->pin));
-}
-
-extern __inline__ uint iopin_is_ded (iopin_t * iopin)
-{
-	volatile uint *parp = &((ccsr_cpm_t *) CONFIG_SYS_MPC85xx_CPM_ADDR)->im_cpm_iop.ppara;
-	return (parp[iopin->port * 8] >> (31 - iopin->pin)) & 1;
-}
-
-extern __inline__ uint iopin_is_gen (iopin_t * iopin)
-{
-	volatile uint *parp = &((ccsr_cpm_t *) CONFIG_SYS_MPC85xx_CPM_ADDR)->im_cpm_iop.ppara;
-	return ((parp[iopin->port * 8] >> (31 - iopin->pin)) & 1) ^ 1;
-}
-
-extern __inline__ void iopin_set_opt2 (iopin_t * iopin)
-{
-	volatile uint *sorp = &((ccsr_cpm_t *) CONFIG_SYS_MPC85xx_CPM_ADDR)->im_cpm_iop.psora;
-	sorp[iopin->port * 8] |= (1 << (31 - iopin->pin));
-}
-
-extern __inline__ void iopin_set_opt1 (iopin_t * iopin)
-{
-	volatile uint *sorp = &((ccsr_cpm_t *) CONFIG_SYS_MPC85xx_CPM_ADDR)->im_cpm_iop.psora;
-	sorp[iopin->port * 8] &= ~(1 << (31 - iopin->pin));
-}
-
-extern __inline__ uint iopin_is_opt2 (iopin_t * iopin)
-{
-	volatile uint *sorp = &((ccsr_cpm_t *) CONFIG_SYS_MPC85xx_CPM_ADDR)->im_cpm_iop.psora;
-	return (sorp[iopin->port * 8] >> (31 - iopin->pin)) & 1;
-}
-
-extern __inline__ uint iopin_is_opt1 (iopin_t * iopin)
-{
-	volatile uint *sorp = &((ccsr_cpm_t *) CONFIG_SYS_MPC85xx_CPM_ADDR)->im_cpm_iop.psora;
-	return ((sorp[iopin->port * 8] >> (31 - iopin->pin)) & 1) ^ 1;
-}
-
-#endif /* __KERNEL__ */
-
-#endif /* _ASM_IOPIN_85xx_H_ */
diff --git a/arch/powerpc/include/asm/m8260_pci.h b/arch/powerpc/include/asm/m8260_pci.h
index 45f01de820..6daca4f99b 100644
--- a/arch/powerpc/include/asm/m8260_pci.h
+++ b/arch/powerpc/include/asm/m8260_pci.h
@@ -1,4 +1,3 @@
-
 #ifndef _PPC_KERNEL_M8260_PCI_H
 #define _PPC_KERNEL_M8260_PCI_H
 
diff --git a/arch/powerpc/include/asm/mmu.h b/arch/powerpc/include/asm/mmu.h
index b700a3a0be..cadaeef85a 100644
--- a/arch/powerpc/include/asm/mmu.h
+++ b/arch/powerpc/include/asm/mmu.h
@@ -5,8 +5,6 @@
 #ifndef _PPC_MMU_H_
 #define _PPC_MMU_H_
 
-#include <linux/config.h>
-
 #ifndef __ASSEMBLY__
 /* Hardware Page Table Entry */
 typedef struct _PTE {
diff --git a/arch/powerpc/include/asm/mpc85xx_gpio.h b/arch/powerpc/include/asm/mpc85xx_gpio.h
index 3d1188467c..87bb4a092b 100644
--- a/arch/powerpc/include/asm/mpc85xx_gpio.h
+++ b/arch/powerpc/include/asm/mpc85xx_gpio.h
@@ -20,7 +20,7 @@
 static inline void mpc85xx_gpio_set(unsigned int mask,
 		unsigned int dir, unsigned int val)
 {
-	ccsr_gpio_t *gpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR + 0xc00);
+	ccsr_gpio_t *gpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR);
 
 	/* First mask off the unwanted parts of "dir" and "val" */
 	dir &= mask;
@@ -56,7 +56,7 @@ static inline void mpc85xx_gpio_set_high(unsigned int gpios)
 
 static inline unsigned int mpc85xx_gpio_get(unsigned int mask)
 {
-	ccsr_gpio_t *gpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR + 0xc00);
+	ccsr_gpio_t *gpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR);
 
 	/* Read the requested values */
 	return in_be32(&gpio->gpdat) & mask;
diff --git a/arch/powerpc/include/asm/pnp.h b/arch/powerpc/include/asm/pnp.h
deleted file mode 100644
index 22ceba2253..0000000000
--- a/arch/powerpc/include/asm/pnp.h
+++ /dev/null
@@ -1,643 +0,0 @@
-/* 11/02/95                                                                   */
-/*----------------------------------------------------------------------------*/
-/*      Plug and Play header definitions                                      */
-/*----------------------------------------------------------------------------*/
-
-/* Structure map for PnP on PowerPC Reference Platform                        */
-/* See Plug and Play ISA Specification, Version 1.0, May 28, 1993.  It        */
-/* (or later versions) is available on Compuserve in the PLUGPLAY area.       */
-/* This code has extensions to that specification, namely new short and       */
-/* long tag types for platform dependent information                          */
-
-/* Warning: LE notation used throughout this file                             */
-
-/* For enum's: if given in hex then they are bit significant, i.e.            */
-/* only one bit is on for each enum                                           */
-
-#ifndef _PNP_
-#define _PNP_
-
-#ifndef __ASSEMBLY__
-#define MAX_MEM_REGISTERS 9
-#define MAX_IO_PORTS 20
-#define MAX_IRQS 7
-/*#define MAX_DMA_CHANNELS 7*/
-
-/* Interrupt controllers */
-
-#define PNPinterrupt0 "PNP0000"      /* AT Interrupt Controller               */
-#define PNPinterrupt1 "PNP0001"      /* EISA Interrupt Controller             */
-#define PNPinterrupt2 "PNP0002"      /* MCA Interrupt Controller              */
-#define PNPinterrupt3 "PNP0003"      /* APIC                                  */
-#define PNPExtInt     "IBM000D"      /* PowerPC Extended Interrupt Controller */
-
-/* Timers */
-
-#define PNPtimer0     "PNP0100"      /* AT Timer                              */
-#define PNPtimer1     "PNP0101"      /* EISA Timer                            */
-#define PNPtimer2     "PNP0102"      /* MCA Timer                             */
-
-/* DMA controllers */
-
-#define PNPdma0       "PNP0200"      /* AT DMA Controller                     */
-#define PNPdma1       "PNP0201"      /* EISA DMA Controller                   */
-#define PNPdma2       "PNP0202"      /* MCA DMA Controller                    */
-
-/* start of August 15, 1994 additions */
-/* CMOS */
-#define PNPCMOS       "IBM0009"      /* CMOS                                  */
-
-/* L2 Cache */
-#define PNPL2         "IBM0007"      /* L2 Cache                              */
-
-/* NVRAM */
-#define PNPNVRAM      "IBM0008"      /* NVRAM                                 */
-
-/* Power Management */
-#define PNPPM         "IBM0005"      /* Power Management                      */
-/* end of August 15, 1994 additions */
-
-/* Keyboards */
-
-#define PNPkeyboard0  "PNP0300"      /* IBM PC/XT KB Cntlr (83 key, no mouse) */
-#define PNPkeyboard1  "PNP0301"      /* Olivetti ICO (102 key)                */
-#define PNPkeyboard2  "PNP0302"      /* IBM PC/AT KB Cntlr (84 key)           */
-#define PNPkeyboard3  "PNP0303"      /* IBM Enhanced (101/2 key, PS/2 mouse)  */
-#define PNPkeyboard4  "PNP0304"      /* Nokia 1050 KB Cntlr                   */
-#define PNPkeyboard5  "PNP0305"      /* Nokia 9140 KB Cntlr                   */
-#define PNPkeyboard6  "PNP0306"      /* Standard Japanese KB Cntlr            */
-#define PNPkeyboard7  "PNP0307"      /* Microsoft Windows (R) KB Cntlr        */
-
-/* Parallel port controllers */
-
-#define PNPparallel0 "PNP0400"       /* Standard LPT Parallel Port            */
-#define PNPparallel1 "PNP0401"       /* ECP Parallel Port                     */
-#define PNPepp       "IBM001C"       /* EPP Parallel Port                     */
-
-/* Serial port controllers */
-
-#define PNPserial0   "PNP0500"       /* Standard PC Serial port               */
-#define PNPSerial1   "PNP0501"       /* 16550A Compatible Serial port         */
-
-/* Disk controllers */
-
-#define PNPdisk0     "PNP0600"       /* Generic ESDI/IDE/ATA Compat HD Cntlr  */
-#define PNPdisk1     "PNP0601"       /* Plus Hardcard II                      */
-#define PNPdisk2     "PNP0602"       /* Plus Hardcard IIXL/EZ                 */
-
-/* Diskette controllers */
-
-#define PNPdiskette0 "PNP0700"       /* PC Standard Floppy Disk Controller    */
-
-/* Display controllers */
-
-#define PNPdisplay0  "PNP0900"       /* VGA Compatible                        */
-#define PNPdisplay1  "PNP0901"       /* Video Seven VGA                       */
-#define PNPdisplay2  "PNP0902"       /* 8514/A Compatible                     */
-#define PNPdisplay3  "PNP0903"       /* Trident VGA                           */
-#define PNPdisplay4  "PNP0904"       /* Cirrus Logic Laptop VGA               */
-#define PNPdisplay5  "PNP0905"       /* Cirrus Logic VGA                      */
-#define PNPdisplay6  "PNP0906"       /* Tseng ET4000 or ET4000/W32            */
-#define PNPdisplay7  "PNP0907"       /* Western Digital VGA                   */
-#define PNPdisplay8  "PNP0908"       /* Western Digital Laptop VGA            */
-#define PNPdisplay9  "PNP0909"       /* S3                                    */
-#define PNPdisplayA  "PNP090A"       /* ATI Ultra Pro/Plus (Mach 32)          */
-#define PNPdisplayB  "PNP090B"       /* ATI Ultra (Mach 8)                    */
-#define PNPdisplayC  "PNP090C"       /* XGA Compatible                        */
-#define PNPdisplayD  "PNP090D"       /* ATI VGA Wonder                        */
-#define PNPdisplayE  "PNP090E"       /* Weitek P9000 Graphics Adapter         */
-#define PNPdisplayF  "PNP090F"       /* Oak Technology VGA                    */
-
-/* Peripheral busses */
-
-#define PNPbuses0    "PNP0A00"       /* ISA Bus                               */
-#define PNPbuses1    "PNP0A01"       /* EISA Bus                              */
-#define PNPbuses2    "PNP0A02"       /* MCA Bus                               */
-#define PNPbuses3    "PNP0A03"       /* PCI Bus                               */
-#define PNPbuses4    "PNP0A04"       /* VESA/VL Bus                           */
-
-/* RTC, BIOS, planar devices */
-
-#define PNPspeaker0  "PNP0800"       /* AT Style Speaker Sound                */
-#define PNPrtc0      "PNP0B00"       /* AT RTC                                */
-#define PNPpnpbios0  "PNP0C00"       /* PNP BIOS (only created by root enum)  */
-#define PNPpnpbios1  "PNP0C01"       /* System Board Memory Device            */
-#define PNPpnpbios2  "PNP0C02"       /* Math Coprocessor                      */
-#define PNPpnpbios3  "PNP0C03"       /* PNP BIOS Event Notification Interrupt */
-
-/* PCMCIA controller */
-
-#define PNPpcmcia0   "PNP0E00"       /* Intel 82365 Compatible PCMCIA Cntlr   */
-
-/* Mice */
-
-#define PNPmouse0    "PNP0F00"       /* Microsoft Bus Mouse                   */
-#define PNPmouse1    "PNP0F01"       /* Microsoft Serial Mouse                */
-#define PNPmouse2    "PNP0F02"       /* Microsoft Inport Mouse                */
-#define PNPmouse3    "PNP0F03"       /* Microsoft PS/2 Mouse                  */
-#define PNPmouse4    "PNP0F04"       /* Mousesystems Mouse                    */
-#define PNPmouse5    "PNP0F05"       /* Mousesystems 3 Button Mouse - COM2    */
-#define PNPmouse6    "PNP0F06"       /* Genius Mouse - COM1                   */
-#define PNPmouse7    "PNP0F07"       /* Genius Mouse - COM2                   */
-#define PNPmouse8    "PNP0F08"       /* Logitech Serial Mouse                 */
-#define PNPmouse9    "PNP0F09"       /* Microsoft Ballpoint Serial Mouse      */
-#define PNPmouseA    "PNP0F0A"       /* Microsoft PNP Mouse                   */
-#define PNPmouseB    "PNP0F0B"       /* Microsoft PNP Ballpoint Mouse         */
-
-/* Modems */
-
-#define PNPmodem0    "PNP9000"       /* Specific IDs TBD                      */
-
-/* Network controllers */
-
-#define PNPnetworkC9 "PNP80C9"       /* IBM Token Ring                        */
-#define PNPnetworkCA "PNP80CA"       /* IBM Token Ring II                     */
-#define PNPnetworkCB "PNP80CB"       /* IBM Token Ring II/Short               */
-#define PNPnetworkCC "PNP80CC"       /* IBM Token Ring 4/16Mbs                */
-#define PNPnetwork27 "PNP8327"       /* IBM Token Ring (All types)            */
-#define PNPnetworket "IBM0010"       /* IBM Ethernet used by Power PC         */
-#define PNPneteisaet "IBM2001"       /* IBM Ethernet EISA adapter             */
-#define PNPAMD79C970 "IBM0016"       /* AMD 79C970 (PCI Ethernet)             */
-
-/* SCSI controllers */
-
-#define PNPscsi0     "PNPA000"       /* Adaptec 154x Compatible SCSI Cntlr    */
-#define PNPscsi1     "PNPA001"       /* Adaptec 174x Compatible SCSI Cntlr    */
-#define PNPscsi2     "PNPA002"       /* Future Domain 16-700 Compat SCSI Cntlr*/
-#define PNPscsi3     "PNPA003"       /* Panasonic CDROM Adapter (SBPro/SB16)  */
-#define PNPscsiF     "IBM000F"       /* NCR 810 SCSI Controller               */
-#define PNPscsi825   "IBM001B"       /* NCR 825 SCSI Controller               */
-#define PNPscsi875   "IBM0018"       /* NCR 875 SCSI Controller               */
-
-/* Sound/Video, Multimedia */
-
-#define PNPmm0       "PNPB000"       /* Sound Blaster Compatible Sound Device */
-#define PNPmm1       "PNPB001"       /* MS Windows Sound System Compat Device */
-#define PNPmmF       "IBM000E"       /* Crystal CS4231 Audio Device           */
-#define PNPv7310     "IBM0015"       /* ASCII V7310 Video Capture Device      */
-#define PNPmm4232    "IBM0017"       /* Crystal CS4232 Audio Device           */
-#define PNPpmsyn     "IBM001D"       /* YMF 289B chip (Yamaha)                */
-#define PNPgp4232    "IBM0012"       /* Crystal CS4232 Game Port              */
-#define PNPmidi4232  "IBM0013"       /* Crystal CS4232 MIDI                   */
-
-/* Operator Panel */
-#define PNPopctl     "IBM000B"       /* Operator's panel                      */
-
-/* Service Processor */
-#define PNPsp        "IBM0011"       /* IBM Service Processor                 */
-#define PNPLTsp      "IBM001E"       /* Lightning/Terlingua Support Processor */
-#define PNPLTmsp     "IBM001F"       /* Lightning/Terlingua Mini-SP           */
-
-/* Memory Controller */
-#define PNPmemctl    "IBM000A"       /* Memory controller                     */
-
-/* Graphics Assist */
-#define PNPg_assist  "IBM0014"       /* Graphics Assist                       */
-
-/* Miscellaneous Device Controllers */
-#define PNPtablet    "IBM0019"       /* IBM Tablet Controller                 */
-
-/* PNP Packet Handles */
-
-#define S1_Packet                0x0A   /* Version resource                   */
-#define S2_Packet                0x15   /* Logical DEVID (without flags)      */
-#define S2_Packet_flags          0x16   /* Logical DEVID (with flags)         */
-#define S3_Packet                0x1C   /* Compatible device ID               */
-#define S4_Packet                0x22   /* IRQ resource (without flags)       */
-#define S4_Packet_flags          0x23   /* IRQ resource (with flags)          */
-#define S5_Packet                0x2A   /* DMA resource                       */
-#define S6_Packet                0x30   /* Depend funct start (w/o priority)  */
-#define S6_Packet_priority       0x31   /* Depend funct start (w/ priority)   */
-#define S7_Packet                0x38   /* Depend funct end                   */
-#define S8_Packet                0x47   /* I/O port resource (w/o fixed loc)  */
-#define S9_Packet_fixed          0x4B   /* I/O port resource (w/ fixed loc)   */
-#define S14_Packet               0x71   /* Vendor defined                     */
-#define S15_Packet               0x78   /* End of resource (w/o checksum)     */
-#define S15_Packet_checksum      0x79   /* End of resource (w/ checksum)      */
-#define L1_Packet                0x81   /* Memory range                       */
-#define L1_Shadow                0x20   /* Memory is shadowable               */
-#define L1_32bit_mem             0x18   /* 32-bit memory only                 */
-#define L1_8_16bit_mem           0x10   /* 8- and 16-bit supported            */
-#define L1_Decode_Hi             0x04   /* decode supports high address       */
-#define L1_Cache                 0x02   /* read cacheable, write-through      */
-#define L1_Writeable             0x01   /* Memory is writeable                */
-#define L2_Packet                0x82   /* ANSI ID string                     */
-#define L3_Packet                0x83   /* Unicode ID string                  */
-#define L4_Packet                0x84   /* Vendor defined                     */
-#define L5_Packet                0x85   /* Large I/O                          */
-#define L6_Packet                0x86   /* 32-bit Fixed Loc Mem Range Desc    */
-#define END_TAG                  0x78   /* End of resource                    */
-#define DF_START_TAG             0x30   /* Dependent function start           */
-#define DF_START_TAG_priority    0x31   /* Dependent function start           */
-#define DF_END_TAG               0x38   /* Dependent function end             */
-#define SUBOPTIMAL_CONFIGURATION 0x2    /* Priority byte sub optimal config   */
-
-/* Device Base Type Codes */
-
-typedef enum _PnP_BASE_TYPE {
-  Reserved = 0,
-  MassStorageDevice = 1,
-  NetworkInterfaceController = 2,
-  DisplayController = 3,
-  MultimediaController = 4,
-  MemoryController = 5,
-  BridgeController = 6,
-  CommunicationsDevice = 7,
-  SystemPeripheral = 8,
-  InputDevice = 9,
-  ServiceProcessor = 0x0A,              /* 11/2/95                            */
-  } PnP_BASE_TYPE;
-
-/* Device Sub Type Codes */
-
-typedef enum _PnP_SUB_TYPE {
-  SCSIController = 0,
-  IDEController = 1,
-  FloppyController = 2,
-  IPIController = 3,
-  OtherMassStorageController = 0x80,
-
-  EthernetController = 0,
-  TokenRingController = 1,
-  FDDIController = 2,
-  OtherNetworkController = 0x80,
-
-  VGAController= 0,
-  SVGAController= 1,
-  XGAController= 2,
-  OtherDisplayController = 0x80,
-
-  VideoController = 0,
-  AudioController = 1,
-  OtherMultimediaController = 0x80,
-
-  RAM = 0,
-  FLASH = 1,
-  OtherMemoryDevice = 0x80,
-
-  HostProcessorBridge = 0,
-  ISABridge = 1,
-  EISABridge = 2,
-  MicroChannelBridge = 3,
-  PCIBridge = 4,
-  PCMCIABridge = 5,
-  VMEBridge = 6,
-  OtherBridgeDevice = 0x80,
-
-  RS232Device = 0,
-  ATCompatibleParallelPort = 1,
-  OtherCommunicationsDevice = 0x80,
-
-  ProgrammableInterruptController = 0,
-  DMAController = 1,
-  SystemTimer = 2,
-  RealTimeClock = 3,
-  L2Cache = 4,
-  NVRAM = 5,
-  PowerManagement = 6,
-  CMOS = 7,
-  OperatorPanel = 8,
-  ServiceProcessorClass1 = 9,
-  ServiceProcessorClass2 = 0xA,
-  ServiceProcessorClass3 = 0xB,
-  GraphicAssist = 0xC,
-  SystemPlanar = 0xF,                   /* 10/5/95                            */
-  OtherSystemPeripheral = 0x80,
-
-  KeyboardController = 0,
-  Digitizer = 1,
-  MouseController = 2,
-  TabletController = 3,                 /* 10/27/95                           */
-  OtherInputController = 0x80,
-
-  GeneralMemoryController = 0,
-  } PnP_SUB_TYPE;
-
-/* Device Interface Type Codes */
-
-typedef enum _PnP_INTERFACE {
-  General = 0,
-  GeneralSCSI = 0,
-  GeneralIDE = 0,
-  ATACompatible = 1,
-
-  GeneralFloppy = 0,
-  Compatible765 = 1,
-  NS398_Floppy = 2,                     /* NS Super I/O wired to use index
-					   register at port 398 and data
-					   register at port 399               */
-  NS26E_Floppy = 3,                     /* Ports 26E and 26F                  */
-  NS15C_Floppy = 4,                     /* Ports 15C and 15D                  */
-  NS2E_Floppy = 5,                      /* Ports 2E and 2F                    */
-  CHRP_Floppy = 6,                      /* CHRP Floppy in PR*P system         */
-
-  GeneralIPI = 0,
-
-  GeneralEther = 0,
-  GeneralToken = 0,
-  GeneralFDDI = 0,
-
-  GeneralVGA = 0,
-  GeneralSVGA = 0,
-  GeneralXGA = 0,
-
-  GeneralVideo = 0,
-  GeneralAudio = 0,
-  CS4232Audio = 1,                      /* CS 4232 Plug 'n Play Configured    */
-
-  GeneralRAM = 0,
-  GeneralFLASH = 0,
-  PCIMemoryController = 0,              /* PCI Config Method                  */
-  RS6KMemoryController = 1,             /* RS6K Config Method                 */
-
-  GeneralHostBridge = 0,
-  GeneralISABridge = 0,
-  GeneralEISABridge = 0,
-  GeneralMCABridge = 0,
-  GeneralPCIBridge = 0,
-  PCIBridgeDirect = 0,
-  PCIBridgeIndirect = 1,
-  PCIBridgeRS6K = 2,
-  GeneralPCMCIABridge = 0,
-  GeneralVMEBridge = 0,
-
-  GeneralRS232 = 0,
-  COMx = 1,
-  Compatible16450 = 2,
-  Compatible16550 = 3,
-  NS398SerPort = 4,                     /* NS Super I/O wired to use index
-					   register at port 398 and data
-					   register at port 399               */
-  NS26ESerPort = 5,                     /* Ports 26E and 26F                  */
-  NS15CSerPort = 6,                     /* Ports 15C and 15D                  */
-  NS2ESerPort = 7,                      /* Ports 2E and 2F                    */
-
-  GeneralParPort = 0,
-  LPTx = 1,
-  NS398ParPort = 2,                     /* NS Super I/O wired to use index
-					   register at port 398 and data
-					   register at port 399               */
-  NS26EParPort = 3,                     /* Ports 26E and 26F                  */
-  NS15CParPort = 4,                     /* Ports 15C and 15D                  */
-  NS2EParPort = 5,                      /* Ports 2E and 2F                    */
-
-  GeneralPIC = 0,
-  ISA_PIC = 1,
-  EISA_PIC = 2,
-  MPIC = 3,
-  RS6K_PIC = 4,
-
-  GeneralDMA = 0,
-  ISA_DMA = 1,
-  EISA_DMA = 2,
-
-  GeneralTimer = 0,
-  ISA_Timer = 1,
-  EISA_Timer = 2,
-  GeneralRTC = 0,
-  ISA_RTC = 1,
-
-  StoreThruOnly = 1,
-  StoreInEnabled = 2,
-  RS6KL2Cache = 3,
-
-  IndirectNVRAM = 0,                    /* Indirectly addressed               */
-  DirectNVRAM = 1,                      /* Memory Mapped                      */
-  IndirectNVRAM24 = 2,                  /* Indirectly addressed - 24 bit      */
-
-  GeneralPowerManagement = 0,
-  EPOWPowerManagement = 1,
-  PowerControl = 2,                    /* d1378 */
-
-  GeneralCMOS = 0,
-
-  GeneralOPPanel = 0,
-  HarddiskLight = 1,
-  CDROMLight = 2,
-  PowerLight = 3,
-  KeyLock = 4,
-  ANDisplay = 5,                        /* AlphaNumeric Display               */
-  SystemStatusLED = 6,                  /* 3 digit 7 segment LED              */
-  CHRP_SystemStatusLED = 7,             /* CHRP LEDs in PR*P system           */
-
-  GeneralServiceProcessor = 0,
-
-  TransferData = 1,
-  IGMC32 = 2,
-  IGMC64 = 3,
-
-  GeneralSystemPlanar = 0,              /* 10/5/95                            */
-
-  } PnP_INTERFACE;
-
-/* PnP resources */
-
-/* Compressed ASCII is 5 bits per char; 00001=A ... 11010=Z */
-
-typedef struct _SERIAL_ID {
-  unsigned char VendorID0;              /*    Bit(7)=0                        */
-					/*    Bits(6:2)=1st character in      */
-					/*       compressed ASCII             */
-					/*    Bits(1:0)=2nd character in      */
-					/*       compressed ASCII bits(4:3)   */
-  unsigned char VendorID1;              /*    Bits(7:5)=2nd character in      */
-					/*       compressed ASCII bits(2:0)   */
-					/*    Bits(4:0)=3rd character in      */
-					/*       compressed ASCII             */
-  unsigned char VendorID2;              /* Product number - vendor assigned   */
-  unsigned char VendorID3;              /* Product number - vendor assigned   */
-
-/* Serial number is to provide uniqueness if more than one board of same      */
-/* type is in system.  Must be "FFFFFFFF" if feature not supported.           */
-
-  unsigned char Serial0;                /* Unique serial number bits (7:0)    */
-  unsigned char Serial1;                /* Unique serial number bits (15:8)   */
-  unsigned char Serial2;                /* Unique serial number bits (23:16)  */
-  unsigned char Serial3;                /* Unique serial number bits (31:24)  */
-  unsigned char Checksum;
-  } SERIAL_ID;
-
-typedef enum _PnPItemName {
-  Unused = 0,
-  PnPVersion = 1,
-  LogicalDevice = 2,
-  CompatibleDevice = 3,
-  IRQFormat = 4,
-  DMAFormat = 5,
-  StartDepFunc = 6,
-  EndDepFunc = 7,
-  IOPort = 8,
-  FixedIOPort = 9,
-  Res1 = 10,
-  Res2 = 11,
-  Res3 = 12,
-  SmallVendorItem = 14,
-  EndTag = 15,
-  MemoryRange = 1,
-  ANSIIdentifier = 2,
-  UnicodeIdentifier = 3,
-  LargeVendorItem = 4,
-  MemoryRange32 = 5,
-  MemoryRangeFixed32 = 6,
-  } PnPItemName;
-
-/* Define a bunch of access functions for the bits in the tag field */
-
-/* Tag type - 0 = small; 1 = large */
-#define tag_type(t) (((t) & 0x80)>>7)
-#define set_tag_type(t,v) (t = (t & 0x7f) | ((v)<<7))
-
-/* Small item name is 4 bits - one of PnPItemName enum above */
-#define tag_small_item_name(t) (((t) & 0x78)>>3)
-#define set_tag_small_item_name(t,v) (t = (t & 0x07) | ((v)<<3))
-
-/* Small item count is 3 bits - count of further bytes in packet */
-#define tag_small_count(t) ((t) & 0x07)
-#define set_tag_count(t,v) (t = (t & 0x78) | (v))
-
-/* Large item name is 7 bits - one of PnPItemName enum above */
-#define tag_large_item_name(t) ((t) & 0x7f)
-#define set_tag_large_item_name(t,v) (t = (t | 0x80) | (v))
-
-/* a PnP resource is a bunch of contiguous TAG packets ending with an end tag */
-
-typedef union _PnP_TAG_PACKET {
-  struct _S1_Pack{                      /* VERSION PACKET                     */
-    unsigned char Tag;                  /* small tag = 0x0a                   */
-    unsigned char Version[2];           /* PnP version, Vendor version        */
-    } S1_Pack;
-
-  struct _S2_Pack{                      /* LOGICAL DEVICE ID PACKET           */
-    unsigned char Tag;                  /* small tag = 0x15 or 0x16           */
-    unsigned char DevId[4];             /* Logical device id                  */
-    unsigned char Flags[2];             /* bit(0) boot device;                */
-					/* bit(7:1) cmd in range x31-x37      */
-					/* bit(7:0) cmd in range x28-x3f (opt)*/
-    } S2_Pack;
-
-  struct _S3_Pack{                      /* COMPATIBLE DEVICE ID PACKET        */
-    unsigned char Tag;                  /* small tag = 0x1c                   */
-    unsigned char CompatId[4];          /* Compatible device id               */
-    } S3_Pack;
-
-  struct _S4_Pack{                      /* IRQ PACKET                         */
-    unsigned char Tag;                  /* small tag = 0x22 or 0x23           */
-    unsigned char IRQMask[2];           /* bit(0) is IRQ0, ...;               */
-					/* bit(0) is IRQ8 ...                 */
-    unsigned char IRQInfo;              /* optional; assume bit(0)=1; else    */
-					/*  bit(0) - high true edge sensitive */
-					/*  bit(1) - low true edge sensitive  */
-					/*  bit(2) - high true level sensitive*/
-					/*  bit(3) - low true level sensitive */
-					/*  bit(7:4) - must be 0              */
-    } S4_Pack;
-
-  struct _S5_Pack{                      /* DMA PACKET                         */
-    unsigned char Tag;                  /* small tag = 0x2a                   */
-    unsigned char DMAMask;              /* bit(0) is channel 0 ...            */
-    unsigned char DMAInfo;
-    } S5_Pack;
-
-  struct _S6_Pack{                      /* START DEPENDENT FUNCTION PACKET    */
-    unsigned char Tag;                  /* small tag = 0x30 or 0x31           */
-    unsigned char Priority;             /* Optional; if missing then x01; else*/
-					/*  x00 = best possible               */
-					/*  x01 = acceptible                  */
-					/*  x02 = sub-optimal but functional  */
-    } S6_Pack;
-
-  struct _S7_Pack{                      /* END DEPENDENT FUNCTION PACKET      */
-    unsigned char Tag;                  /* small tag = 0x38                   */
-    } S7_Pack;
-
-  struct _S8_Pack{                      /* VARIABLE I/O PORT PACKET           */
-    unsigned char Tag;                  /* small tag x47                      */
-    unsigned char IOInfo;               /* x0  = decode only bits(9:0);       */
-#define  ISAAddr16bit         0x01      /* x01 = decode bits(15:0)            */
-    unsigned char RangeMin[2];          /* Min base address                   */
-    unsigned char RangeMax[2];          /* Max base address                   */
-    unsigned char IOAlign;              /* base alignmt, incr in 1B blocks    */
-    unsigned char IONum;                /* number of contiguous I/O ports     */
-    } S8_Pack;
-
-  struct _S9_Pack{                      /* FIXED I/O PORT PACKET              */
-    unsigned char Tag;                  /* small tag = 0x4b                   */
-    unsigned char Range[2];             /* base address 10 bits               */
-    unsigned char IONum;                /* number of contiguous I/O ports     */
-    } S9_Pack;
-
-  struct _S14_Pack{                     /* VENDOR DEFINED PACKET              */
-    unsigned char Tag;                  /* small tag = 0x7m m = 1-7           */
-    union _S14_Data{
-      unsigned char Data[7];            /* Vendor defined                     */
-      struct _S14_PPCPack{              /* Pr*p s14 pack                      */
-	 unsigned char Type;            /* 00=non-IBM                         */
-	 unsigned char PPCData[6];      /* Vendor defined                     */
-	} S14_PPCPack;
-      } S14_Data;
-    } S14_Pack;
-
-  struct _S15_Pack{                     /* END PACKET                         */
-    unsigned char Tag;                  /* small tag = 0x78 or 0x79           */
-    unsigned char Check;                /* optional - checksum                */
-    } S15_Pack;
-
-  struct _L1_Pack{                      /* MEMORY RANGE PACKET                */
-    unsigned char Tag;                  /* large tag = 0x81                   */
-    unsigned char Count0;               /* x09                                */
-    unsigned char Count1;               /* x00                                */
-    unsigned char Data[9];              /* a variable array of bytes,         */
-					/* count in tag                       */
-    } L1_Pack;
-
-  struct _L2_Pack{                      /* ANSI ID STRING PACKET              */
-    unsigned char Tag;                  /* large tag = 0x82                   */
-    unsigned char Count0;               /* Length of string                   */
-    unsigned char Count1;
-    unsigned char Identifier[1];        /* a variable array of bytes,         */
-					/* count in tag                       */
-    } L2_Pack;
-
-  struct _L3_Pack{                      /* UNICODE ID STRING PACKET           */
-    unsigned char Tag;                  /* large tag = 0x83                   */
-    unsigned char Count0;               /* Length + 2 of string               */
-    unsigned char Count1;
-    unsigned char Country0;             /* TBD                                */
-    unsigned char Country1;             /* TBD                                */
-    unsigned char Identifier[1];        /* a variable array of bytes,         */
-					/* count in tag                       */
-    } L3_Pack;
-
-  struct _L4_Pack{                      /* VENDOR DEFINED PACKET              */
-    unsigned char Tag;                  /* large tag = 0x84                   */
-    unsigned char Count0;
-    unsigned char Count1;
-    union _L4_Data{
-      unsigned char Data[1];            /* a variable array of bytes,         */
-					/* count in tag                       */
-      struct _L4_PPCPack{               /* Pr*p L4 packet                     */
-	 unsigned char Type;            /* 00=non-IBM                         */
-	 unsigned char PPCData[1];      /* a variable array of bytes,         */
-					/* count in tag                       */
-	} L4_PPCPack;
-      } L4_Data;
-    } L4_Pack;
-
-  struct _L5_Pack{
-    unsigned char Tag;                  /* large tag = 0x85                   */
-    unsigned char Count0;               /* Count = 17                         */
-    unsigned char Count1;
-    unsigned char Data[17];
-    } L5_Pack;
-
-  struct _L6_Pack{
-    unsigned char Tag;                  /* large tag = 0x86                   */
-    unsigned char Count0;               /* Count = 9                          */
-    unsigned char Count1;
-    unsigned char Data[9];
-    } L6_Pack;
-
-  } PnP_TAG_PACKET;
-
-#endif /* __ASSEMBLY__ */
-#endif  /* ndef _PNP_ */
diff --git a/arch/powerpc/include/asm/ppc4xx-isram.h b/arch/powerpc/include/asm/ppc4xx-isram.h
index 04fc8916eb..4d1106b124 100644
--- a/arch/powerpc/include/asm/ppc4xx-isram.h
+++ b/arch/powerpc/include/asm/ppc4xx-isram.h
@@ -1,4 +1,3 @@
-
 /*
  * SPDX-License-Identifier:	GPL-2.0+
  */
diff --git a/arch/powerpc/include/asm/processor.h b/arch/powerpc/include/asm/processor.h
index c0fb51993e..72f30feee6 100644
--- a/arch/powerpc/include/asm/processor.h
+++ b/arch/powerpc/include/asm/processor.h
@@ -7,8 +7,6 @@
  */
 #define current_text_addr() ({ __label__ _l; _l: &&_l;})
 
-#include <linux/config.h>
-
 #include <asm/ptrace.h>
 #include <asm/types.h>
 
@@ -1129,6 +1127,8 @@
 #define SVR_T1020	0x852100
 #define SVR_T1021	0x852101
 #define SVR_T1022	0x852102
+#define SVR_T2080	0x853000
+#define SVR_T2081	0x853100
 
 #define SVR_8610	0x80A000
 #define SVR_8641	0x809000
@@ -1356,7 +1356,7 @@ void _nmask_and_or_msr(unsigned long nmask, unsigned long or_val);
 #elif defined(CONFIG_GEMINI)
 #define _machine _MACH_gemini
 #define have_of 0
-#elif defined(CONFIG_8260)
+#elif defined(CONFIG_MPC8260)
 #define _machine _MACH_8260
 #define have_of 0
 #elif defined(CONFIG_SANDPOINT)
diff --git a/arch/powerpc/include/asm/ptrace.h b/arch/powerpc/include/asm/ptrace.h
index cf09edf156..2d56de61d1 100644
--- a/arch/powerpc/include/asm/ptrace.h
+++ b/arch/powerpc/include/asm/ptrace.h
@@ -17,8 +17,6 @@
  * the PT_* values below.  This simplifies arch/powerpc/kernel/ptrace.c.
  */
 
-#include <linux/config.h>
-
 #ifndef __ASSEMBLY__
 #ifdef CONFIG_PPC64BRIDGE
 #define PPC_REG unsigned long /*long*/
diff --git a/arch/powerpc/include/asm/residual.h b/arch/powerpc/include/asm/residual.h
deleted file mode 100644
index dc85edbc3c..0000000000
--- a/arch/powerpc/include/asm/residual.h
+++ /dev/null
@@ -1,331 +0,0 @@
-/* 7/18/95                                                                    */
-/*----------------------------------------------------------------------------*/
-/*      Residual Data header definitions and prototypes                       */
-/*----------------------------------------------------------------------------*/
-
-/* Structure map for RESIDUAL on PowerPC Reference Platform                   */
-/* residual.h - Residual data structure passed in r3.                         */
-/*              Load point passed in r4 to boot image.                        */
-/* For enum's: if given in hex then they are bit significant,                 */
-/*             i.e. only one bit is on for each enum                          */
-/* Reserved fields must be filled with zeros.                                */
-
-#ifndef _RESIDUAL_
-#define _RESIDUAL_
-
-#ifndef __ASSEMBLY__
-
-#define MAX_CPUS 32                     /* These should be set to the maximum */
-#define MAX_MEMS 64                     /* number possible for this system.   */
-#define MAX_DEVICES 256                 /* Changing these will change the     */
-#define AVE_PNP_SIZE 32                 /* structure, hence the version of    */
-#define MAX_MEM_SEGS 64                 /* this header file.                  */
-
-/*----------------------------------------------------------------------------*/
-/*               Public structures...                                         */
-/*----------------------------------------------------------------------------*/
-
-#include "pnp.h"
-
-typedef enum _L1CACHE_TYPE {
-  NoneCAC = 0,
-  SplitCAC = 1,
-  CombinedCAC = 2
-  } L1CACHE_TYPE;
-
-typedef enum _TLB_TYPE {
-  NoneTLB = 0,
-  SplitTLB = 1,
-  CombinedTLB = 2
-  } TLB_TYPE;
-
-typedef enum _FIRMWARE_SUPPORT {
-  Conventional = 0x01,
-  OpenFirmware = 0x02,
-  Diagnostics = 0x04,
-  LowDebug = 0x08,
-  Multiboot = 0x10,
-  LowClient = 0x20,
-  Hex41 = 0x40,
-  FAT = 0x80,
-  ISO9660 = 0x0100,
-  SCSI_InitiatorID_Override = 0x0200,
-  Tape_Boot = 0x0400,
-  FW_Boot_Path = 0x0800
-  } FIRMWARE_SUPPORT;
-
-typedef enum _FIRMWARE_SUPPLIERS {
-  IBMFirmware = 0x00,
-  MotoFirmware = 0x01,                  /* 7/18/95                            */
-  FirmWorks = 0x02,                     /* 10/5/95                            */
-  Bull = 0x03,                          /* 04/03/96                           */
-  } FIRMWARE_SUPPLIERS;
-
-typedef enum _ENDIAN_SWITCH_METHODS {
-  UsePort92 = 0x01,
-  UsePCIConfigA8 = 0x02,
-  UseFF001030 = 0x03,
-  } ENDIAN_SWITCH_METHODS;
-
-typedef enum _SPREAD_IO_METHODS {
-  UsePort850 = 0x00,
-/*UsePCIConfigA8 = 0x02,*/
-  } SPREAD_IO_METHODS;
-
-typedef struct _VPD {
-
-  /* Box dependent stuff */
-  unsigned char PrintableModel[32];     /* Null terminated string.
-					   Must be of the form:
-					   vvv,<20h>,<model designation>,<0x0>
-					   where vvv is the vendor ID
-					   e.g. IBM PPS MODEL 6015<0x0>       */
-  unsigned char Serial[16];             /* 12/94:
-					   Serial Number; must be of the form:
-					   vvv<serial number> where vvv is the
-					   vendor ID.
-					   e.g. IBM60151234567<20h><20h>      */
-  unsigned char Reserved[48];
-  unsigned long FirmwareSupplier;       /* See FirmwareSuppliers enum         */
-  unsigned long FirmwareSupports;       /* See FirmwareSupport enum           */
-  unsigned long NvramSize;              /* Size of nvram in bytes             */
-  unsigned long NumSIMMSlots;
-  unsigned short EndianSwitchMethod;    /* See EndianSwitchMethods enum       */
-  unsigned short SpreadIOMethod;        /* See SpreadIOMethods enum           */
-  unsigned long SmpIar;
-  unsigned long RAMErrLogOffset;        /* Heap offset to error log           */
-  unsigned long Reserved5;
-  unsigned long Reserved6;
-  unsigned long ProcessorHz;            /* Processor clock frequency in Hertz */
-  unsigned long ProcessorBusHz;         /* Processor bus clock frequency      */
-  unsigned long Reserved7;
-  unsigned long TimeBaseDivisor;        /* (Bus clocks per timebase tic)*1000 */
-  unsigned long WordWidth;              /* Word width in bits                 */
-  unsigned long PageSize;               /* Page size in bytes                 */
-  unsigned long CoherenceBlockSize;     /* Unit of transfer in/out of cache
-					   for which coherency is maintained;
-					   normally <= CacheLineSize.         */
-  unsigned long GranuleSize;            /* Unit of lock allocation to avoid   */
-					/*   false sharing of locks.          */
-
-  /* L1 Cache variables */
-  unsigned long CacheSize;              /* L1 Cache size in KB. This is the   */
-					/*   total size of the L1, whether    */
-					/*   combined or split                */
-  unsigned long CacheAttrib;            /* L1CACHE_TYPE                       */
-  unsigned long CacheAssoc;             /* L1 Cache associativity. Use this
-					   for combined cache. If split, put
-					   zeros here.                        */
-  unsigned long CacheLineSize;          /* L1 Cache line size in bytes. Use
-					   for combined cache. If split, put
-					   zeros here.                        */
-  /* For split L1 Cache: (= combined if combined cache) */
-  unsigned long I_CacheSize;
-  unsigned long I_CacheAssoc;
-  unsigned long I_CacheLineSize;
-  unsigned long D_CacheSize;
-  unsigned long D_CacheAssoc;
-  unsigned long D_CacheLineSize;
-
-  /* Translation Lookaside Buffer variables */
-  unsigned long TLBSize;                /* Total number of TLBs on the system */
-  unsigned long TLBAttrib;              /* Combined I+D or split TLB          */
-  unsigned long TLBAssoc;               /* TLB Associativity. Use this for
-					   combined TLB. If split, put zeros
-					   here.                              */
-  /* For split TLB: (= combined if combined TLB) */
-  unsigned long I_TLBSize;
-  unsigned long I_TLBAssoc;
-  unsigned long D_TLBSize;
-  unsigned long D_TLBAssoc;
-
-  unsigned long ExtendedVPD;            /* Offset to extended VPD area;
-					   null if unused                     */
-  } VPD;
-
-typedef enum _DEVICE_FLAGS {
-  Enabled = 0x4000,                     /* 1 - PCI device is enabled          */
-  Integrated = 0x2000,
-  Failed = 0x1000,                      /* 1 - device failed POST code tests  */
-  Static = 0x0800,                      /* 0 - dynamically configurable
-					   1 - static                         */
-  Dock = 0x0400,                        /* 0 - not a docking station device
-					   1 - is a docking station device    */
-  Boot = 0x0200,                        /* 0 - device cannot be used for BOOT
-					   1 - can be a BOOT device           */
-  Configurable = 0x0100,                /* 1 - device is configurable         */
-  Disableable = 0x80,                   /* 1 - device can be disabled         */
-  PowerManaged = 0x40,                  /* 0 - not managed; 1 - managed       */
-  ReadOnly = 0x20,                      /* 1 - device is read only            */
-  Removable = 0x10,                     /* 1 - device is removable            */
-  ConsoleIn = 0x08,
-  ConsoleOut = 0x04,
-  Input = 0x02,
-  Output = 0x01
-  } DEVICE_FLAGS;
-
-typedef enum _BUS_ID {
-  ISADEVICE = 0x01,
-  EISADEVICE = 0x02,
-  PCIDEVICE = 0x04,
-  PCMCIADEVICE = 0x08,
-  PNPISADEVICE = 0x10,
-  MCADEVICE = 0x20,
-  MXDEVICE = 0x40,                      /* Devices on mezzanine bus           */
-  PROCESSORDEVICE = 0x80,               /* Devices on processor bus           */
-  VMEDEVICE = 0x100,
-  } BUS_ID;
-
-typedef struct _DEVICE_ID {
-  unsigned long BusId;                  /* See BUS_ID enum above              */
-  unsigned long DevId;                  /* Big Endian format                  */
-  unsigned long SerialNum;              /* For multiple usage of a single
-					   DevId                              */
-  unsigned long Flags;                  /* See DEVICE_FLAGS enum above        */
-  unsigned char BaseType;               /* See pnp.h for bit definitions      */
-  unsigned char SubType;                /* See pnp.h for bit definitions      */
-  unsigned char Interface;              /* See pnp.h for bit definitions      */
-  unsigned char Spare;
-  } DEVICE_ID;
-
-typedef union _BUS_ACCESS {
-  struct _PnPAccess{
-    unsigned char CSN;
-    unsigned char LogicalDevNumber;
-    unsigned short ReadDataPort;
-    } PnPAccess;
-  struct _ISAAccess{
-    unsigned char SlotNumber;           /* ISA Slot Number generally not
-					   available; 0 if unknown            */
-    unsigned char LogicalDevNumber;
-    unsigned short ISAReserved;
-    } ISAAccess;
-  struct _MCAAccess{
-    unsigned char SlotNumber;
-    unsigned char LogicalDevNumber;
-    unsigned short MCAReserved;
-    } MCAAccess;
-  struct _PCMCIAAccess{
-    unsigned char SlotNumber;
-    unsigned char LogicalDevNumber;
-    unsigned short PCMCIAReserved;
-    } PCMCIAAccess;
-  struct _EISAAccess{
-    unsigned char SlotNumber;
-    unsigned char FunctionNumber;
-    unsigned short EISAReserved;
-    } EISAAccess;
-  struct _PCIAccess{
-    unsigned char BusNumber;
-    unsigned char DevFuncNumber;
-    unsigned short PCIReserved;
-    } PCIAccess;
-  struct _ProcBusAccess{
-    unsigned char BusNumber;
-    unsigned char BUID;
-    unsigned short ProcBusReserved;
-    } ProcBusAccess;
-  } BUS_ACCESS;
-
-/* Per logical device information */
-typedef struct _PPC_DEVICE {
-  DEVICE_ID DeviceId;
-  BUS_ACCESS BusAccess;
-
-  /* The following three are offsets into the DevicePnPHeap */
-  /* All are in PnP compressed format                       */
-  unsigned long AllocatedOffset;        /* Allocated resource description     */
-  unsigned long PossibleOffset;         /* Possible resource description      */
-  unsigned long CompatibleOffset;       /* Compatible device identifiers      */
-  } PPC_DEVICE;
-
-typedef enum _CPU_STATE {
-  CPU_GOOD = 0,                         /* CPU is present, and active         */
-  CPU_GOOD_FW = 1,                      /* CPU is present, and in firmware    */
-  CPU_OFF = 2,                          /* CPU is present, but inactive       */
-  CPU_FAILED = 3,                       /* CPU is present, but failed POST    */
-  CPU_NOT_PRESENT = 255                 /* CPU not present                    */
-  } CPU_STATE;
-
-typedef struct _PPC_CPU {
-  unsigned long CpuType;                /* Result of mfspr from Processor
-					   Version Register (PVR).
-					   PVR(0-15) = Version (e.g. 601)
-					   PVR(16-31 = EC Level               */
-  unsigned char CpuNumber;              /* CPU Number for this processor      */
-  unsigned char CpuState;               /* CPU State, see CPU_STATE enum      */
-  unsigned short Reserved;
-  } PPC_CPU;
-
-typedef struct _PPC_MEM {
-  unsigned long SIMMSize;               /* 0 - absent or bad
-					   8M, 32M (in MB)                    */
-  } PPC_MEM;
-
-typedef enum _MEM_USAGE {
-  Other = 0x8000,
-  ResumeBlock = 0x4000,                 /* for use by power management        */
-  SystemROM = 0x2000,                   /* Flash memory (populated)           */
-  UnPopSystemROM = 0x1000,              /* Unpopulated part of SystemROM area */
-  IOMemory = 0x0800,
-  SystemIO = 0x0400,
-  SystemRegs = 0x0200,
-  PCIAddr = 0x0100,
-  PCIConfig = 0x80,
-  ISAAddr = 0x40,
-  Unpopulated = 0x20,                   /* Unpopulated part of System Memory  */
-  Free = 0x10,                          /* Free part of System Memory         */
-  BootImage = 0x08,                     /* BootImage part of System Memory    */
-  FirmwareCode = 0x04,                  /* FirmwareCode part of System Memory */
-  FirmwareHeap = 0x02,                  /* FirmwareHeap part of System Memory */
-  FirmwareStack = 0x01                  /* FirmwareStack part of System Memory*/
-  } MEM_USAGE;
-
-typedef struct _MEM_MAP {
-  unsigned long Usage;                  /* See MEM_USAGE above                */
-  unsigned long BasePage;               /* Page number measured in 4KB pages  */
-  unsigned long PageCount;              /* Page count measured in 4KB pages   */
-  } MEM_MAP;
-
-typedef struct _RESIDUAL {
-  unsigned long ResidualLength;         /* Length of Residual                 */
-  unsigned char Version;                /* of this data structure             */
-  unsigned char Revision;               /* of this data structure             */
-  unsigned short EC;                    /* of this data structure             */
-  /* VPD */
-  VPD VitalProductData;
-  /* CPU */
-  unsigned short MaxNumCpus;            /* Max CPUs in this system            */
-  unsigned short ActualNumCpus;         /* ActualNumCpus < MaxNumCpus means   */
-					/* that there are unpopulated or      */
-					/* otherwise unusable cpu locations   */
-  PPC_CPU Cpus[MAX_CPUS];
-  /* Memory */
-  unsigned long TotalMemory;            /* Total amount of memory installed   */
-  unsigned long GoodMemory;             /* Total amount of good memory        */
-  unsigned long ActualNumMemSegs;
-  MEM_MAP Segs[MAX_MEM_SEGS];
-  unsigned long ActualNumMemories;
-  PPC_MEM Memories[MAX_MEMS];
-  /* Devices */
-  unsigned long ActualNumDevices;
-  PPC_DEVICE Devices[MAX_DEVICES];
-  unsigned char DevicePnPHeap[2*MAX_DEVICES*AVE_PNP_SIZE];
-  } RESIDUAL;
-
-
-extern RESIDUAL *res;
-extern void print_residual_device_info(void);
-extern PPC_DEVICE *residual_find_device(unsigned long BusMask,
-					unsigned char * DevID, int BaseType,
-					int SubType, int Interface, int n);
-extern PnP_TAG_PACKET *PnP_find_packet(unsigned char *p, unsigned packet_tag,
-				       int n);
-extern PnP_TAG_PACKET *PnP_find_small_vendor_packet(unsigned char *p,
-						    unsigned packet_type,
-						    int n);
-extern PnP_TAG_PACKET *PnP_find_large_vendor_packet(unsigned char *p,
-						    unsigned packet_type,
-						    int n);
-#endif /* __ASSEMBLY__ */
-#endif  /* ndef _RESIDUAL_ */
diff --git a/arch/powerpc/include/asm/status_led.h b/arch/powerpc/include/asm/status_led.h
index 037570993a..441619042d 100644
--- a/arch/powerpc/include/asm/status_led.h
+++ b/arch/powerpc/include/asm/status_led.h
@@ -11,7 +11,7 @@
 #ifndef CONFIG_BOARD_SPECIFIC_LED
 # if defined(CONFIG_8xx)
 #  include <mpc8xx.h>
-# elif defined(CONFIG_8260)
+# elif defined(CONFIG_MPC8260)
 #  include <mpc8260.h>
 # elif defined(CONFIG_5xx)
 #  include <mpc5xx.h>
diff --git a/arch/powerpc/include/asm/u-boot.h b/arch/powerpc/include/asm/u-boot.h
index 5916f7ce99..3c28420574 100644
--- a/arch/powerpc/include/asm/u-boot.h
+++ b/arch/powerpc/include/asm/u-boot.h
@@ -35,7 +35,7 @@ typedef struct bd_info {
 	unsigned long	bi_flashoffset; /* reserved area for startup monitor */
 	unsigned long	bi_sramstart;	/* start of SRAM memory */
 	unsigned long	bi_sramsize;	/* size	 of SRAM memory */
-#if defined(CONFIG_5xx) || defined(CONFIG_8xx) || defined(CONFIG_8260) \
+#if defined(CONFIG_5xx) || defined(CONFIG_8xx) || defined(CONFIG_MPC8260) \
 	|| defined(CONFIG_E500) || defined(CONFIG_MPC86xx)
 	unsigned long	bi_immr_base;	/* base of IMMR register */
 #endif
diff --git a/arch/powerpc/lib/Makefile b/arch/powerpc/lib/Makefile
index 88152920b2..0f6298269a 100644
--- a/arch/powerpc/lib/Makefile
+++ b/arch/powerpc/lib/Makefile
@@ -5,22 +5,9 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
 ## Build a couple of necessary functions into a private libgcc
-LIBGCC	= $(obj)libgcc.o
-GLSOBJS	+= _ashldi3.o
-GLSOBJS	+= _ashrdi3.o
-GLSOBJS	+= _lshrdi3.o
-LGOBJS	:= $(addprefix $(obj),$(GLSOBJS)) \
-	   $(addprefix $(obj),$(GLCOBJS))
-
-## But only build it if the user asked for it
-ifdef USE_PRIVATE_LIBGCC
-TARGETS	+= $(LIBGCC)
-endif
-
-LIB	= $(obj)lib$(ARCH).o
+## if the user asked for it
+lib-$(CONFIG_USE_PRIVATE_LIBGCC) += _ashldi3.o _ashrdi3.o _lshrdi3.o
 
 MINIMAL=
 
@@ -31,29 +18,29 @@ endif
 endif
 
 ifdef MINIMAL
-COBJS-y += cache.o time.o
-SOBJS-y += ticks.o
+obj-y += cache.o time.o
+obj-y += ticks.o
 else
 
-SOBJS-y	+= ppcstring.o
+obj-y	+= ppcstring.o
 
-SOBJS-y	+= ppccache.o
-SOBJS-y	+= ticks.o
-SOBJS-y	+= reloc.o
+obj-y	+= ppccache.o
+obj-y	+= ticks.o
+obj-y	+= reloc.o
 
-COBJS-$(CONFIG_BAT_RW) += bat_rw.o
+obj-$(CONFIG_BAT_RW) += bat_rw.o
 ifndef CONFIG_SPL_BUILD
 ifndef CONFIG_SYS_GENERIC_BOARD
-COBJS-y	+= board.o
+obj-y	+= board.o
 endif
 endif
-COBJS-$(CONFIG_CMD_BOOTM) += bootm.o
-COBJS-y	+= cache.o
-COBJS-y	+= extable.o
-COBJS-y	+= interrupts.o
-COBJS-$(CONFIG_CMD_KGDB) += kgdb.o
-COBJS-${CONFIG_CMD_IDE} += ide.o
-COBJS-y	+= time.o
+obj-$(CONFIG_CMD_BOOTM) += bootm.o
+obj-y	+= cache.o
+obj-y	+= extable.o
+obj-y	+= interrupts.o
+obj-$(CONFIG_CMD_KGDB) += kgdb.o
+obj-$(CONFIG_CMD_IDE) += ide.o
+obj-y	+= time.o
 
 # Don't include the MPC5xxx special memcpy into the
 # SPL U-Boot image. memcpy is used in the SPL NOR
@@ -63,42 +50,17 @@ ifndef CONFIG_SPL_BUILD
 # Workaround for local bus unaligned access problems
 # on MPC512x and MPC5200
 ifdef CONFIG_MPC512X
-$(obj)ppcstring.o: AFLAGS += -Dmemcpy=__memcpy
-COBJS-y += memcpy_mpc5200.o
+AFLAGS_ppcstring.o += -Dmemcpy=__memcpy
+obj-y += memcpy_mpc5200.o
 endif
 ifdef CONFIG_MPC5200
-$(obj)ppcstring.o: AFLAGS += -Dmemcpy=__memcpy
-COBJS-y += memcpy_mpc5200.o
+AFLAGS_ppcstring.o += -Dmemcpy=__memcpy
+obj-y += memcpy_mpc5200.o
 endif
 endif
 
 endif # not minimal
 
 ifdef CONFIG_SPL_BUILD
-COBJS-$(CONFIG_SPL_FRAMEWORK) += spl.o
+obj-$(CONFIG_SPL_FRAMEWORK) += spl.o
 endif
-
-COBJS	+= $(sort $(COBJS-y))
-
-SRCS	:= $(GLSOBJS:.o=.S) $(GLCOBJS:.o=.c) \
-	   $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
-OBJS	:= $(addprefix $(obj),$(SOBJS-y) $(COBJS-y))
-
-TARGETS += $(LIB)
-
-all: $(TARGETS)
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-$(LIBGCC): $(obj).depend $(LGOBJS)
-	$(call cmd_link_o_target, $(LGOBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
diff --git a/arch/powerpc/lib/board.c b/arch/powerpc/lib/board.c
index a101e03601..f86c6f3e8f 100644
--- a/arch/powerpc/lib/board.c
+++ b/arch/powerpc/lib/board.c
@@ -277,10 +277,10 @@ static init_fnc_t *init_sequence[] = {
 	serial_init,
 	console_init_f,
 	display_options,
-#if defined(CONFIG_8260)
+#if defined(CONFIG_MPC8260)
 	prt_8260_rsr,
 	prt_8260_clks,
-#endif /* CONFIG_8260 */
+#endif /* CONFIG_MPC8260 */
 #if defined(CONFIG_MPC83xx)
 	prt_83xx_rsr,
 #endif
@@ -312,17 +312,6 @@ static init_fnc_t *init_sequence[] = {
 	NULL,	/* Terminate this list */
 };
 
-ulong get_effective_memsize(void)
-{
-#ifndef	CONFIG_VERY_BIG_RAM
-	return gd->ram_size;
-#else
-	/* limit stack to what we can reasonable map */
-	return ((gd->ram_size > CONFIG_MAX_MEM_MAPPED) ?
-		CONFIG_MAX_MEM_MAPPED : gd->ram_size);
-#endif
-}
-
 static int __fixup_cpu(void)
 {
 	return 0;
@@ -343,13 +332,6 @@ int fixup_cpu(void) __attribute__((weak, alias("__fixup_cpu")));
  * initialized, and stack space is limited to a few kB.
  */
 
-#ifdef CONFIG_LOGBUFFER
-unsigned long logbuffer_base(void)
-{
-	return CONFIG_SYS_SDRAM_BASE + get_effective_memsize() - LOGBUFF_LEN;
-}
-#endif
-
 void board_init_f(ulong bootflag)
 {
 	bd_t *bd;
@@ -522,7 +504,7 @@ void board_init_f(ulong bootflag)
 	bd->bi_sramsize = CONFIG_SYS_SRAM_SIZE;		/* size  of SRAM */
 #endif
 
-#if defined(CONFIG_8xx) || defined(CONFIG_8260) || defined(CONFIG_5xx) || \
+#if defined(CONFIG_8xx) || defined(CONFIG_MPC8260) || defined(CONFIG_5xx) || \
     defined(CONFIG_E500) || defined(CONFIG_MPC86xx)
 	bd->bi_immr_base = CONFIG_SYS_IMMR;	/* base  of IMMR register     */
 #endif
@@ -984,7 +966,7 @@ void board_init_r(gd_t *id, ulong dest_addr)
 		pram += (LOGBUFF_LEN + LOGBUFF_OVERHEAD) / 1024;
 #endif
 #endif
-		sprintf(memsz, "%ldk", (bd->bi_memsize / 1024) - pram);
+		sprintf(memsz, "%ldk", (ulong) (bd->bi_memsize / 1024) - pram);
 		setenv("mem", memsz);
 	}
 #endif
diff --git a/arch/powerpc/lib/bootm.c b/arch/powerpc/lib/bootm.c
index e7153b0480..33099a492d 100644
--- a/arch/powerpc/lib/bootm.c
+++ b/arch/powerpc/lib/bootm.c
@@ -30,8 +30,8 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-extern ulong get_effective_memsize(void);
 static ulong get_sp (void);
+extern void ft_fixup_num_cores(void *blob);
 static void set_clocks_in_mhz (bd_t *kbd);
 
 #ifndef CONFIG_SYS_LINUX_LOWMEM_MAX_SIZE
@@ -53,6 +53,13 @@ static void boot_jump_linux(bootm_headers_t *images)
 
 	bootstage_mark(BOOTSTAGE_ID_RUN_OS);
 
+#ifdef CONFIG_BOOTSTAGE_FDT
+	bootstage_fdt_add_report();
+#endif
+#ifdef CONFIG_BOOTSTAGE_REPORT
+	bootstage_report();
+#endif
+
 #if defined(CONFIG_SYS_INIT_RAM_LOCK) && !defined(CONFIG_E500)
 	unlock_ram_in_cache();
 #endif
@@ -277,3 +284,58 @@ static void set_clocks_in_mhz (bd_t *kbd)
 #endif /* CONFIG_MPC5xxx */
 	}
 }
+
+#if defined(CONFIG_BOOTM_VXWORKS)
+void boot_prep_vxworks(bootm_headers_t *images)
+{
+#if defined(CONFIG_OF_LIBFDT)
+	int off;
+	u64 base, size;
+
+	if (!images->ft_addr)
+		return;
+
+	base = (u64)gd->bd->bi_memstart;
+	size = (u64)gd->bd->bi_memsize;
+
+	off = fdt_path_offset(images->ft_addr, "/memory");
+	if (off < 0)
+		fdt_fixup_memory(images->ft_addr, base, size);
+
+#if defined(CONFIG_MP)
+#if defined(CONFIG_MPC85xx)
+	ft_fixup_cpu(images->ft_addr, base + size);
+	ft_fixup_num_cores(images->ft_addr);
+#elif defined(CONFIG_MPC86xx)
+	off = fdt_add_mem_rsv(images->ft_addr,
+			determine_mp_bootpg(NULL), (u64)4096);
+	if (off < 0)
+		printf("## WARNING %s: %s\n", __func__, fdt_strerror(off));
+	ft_fixup_num_cores(images->ft_addr);
+#endif
+	flush_cache((unsigned long)images->ft_addr, images->ft_len);
+#endif
+#endif
+}
+
+void boot_jump_vxworks(bootm_headers_t *images)
+{
+	/* PowerPC VxWorks boot interface conforms to the ePAPR standard
+	 * general purpuse registers:
+	 *
+	 *	r3: Effective address of the device tree image
+	 *	r4: 0
+	 *	r5: 0
+	 *	r6: ePAPR magic value
+	 *	r7: shall be the size of the boot IMA in bytes
+	 *	r8: 0
+	 *	r9: 0
+	 *	TCR: WRC = 0, no watchdog timer reset will occur
+	 */
+	WATCHDOG_RESET();
+
+	((void (*)(void *, ulong, ulong, ulong,
+		ulong, ulong, ulong))images->ep)(images->ft_addr,
+		0, 0, EPAPR_MAGIC, getenv_bootm_mapsize(), 0, 0);
+}
+#endif
diff --git a/arch/powerpc/lib/kgdb.c b/arch/powerpc/lib/kgdb.c
index 19a56dbe21..01a7708aef 100644
--- a/arch/powerpc/lib/kgdb.c
+++ b/arch/powerpc/lib/kgdb.c
@@ -159,7 +159,7 @@ kgdb_trap(struct pt_regs *regs)
 
 #define SPACE_REQUIRED	((32*4)+(32*8)+(6*4))
 
-#ifdef CONFIG_8260
+#ifdef CONFIG_MPC8260
 /* store floating double indexed */
 #define STFDI(n,p)	__asm__ __volatile__ ("stfd " #n ",%0" : "=o"(p[2*n]))
 /* store floating double multiple */
@@ -190,7 +190,7 @@ kgdb_getregs(struct pt_regs *regs, char *buf, int max)
 		*ptr++ = regs->gpr[i];
 
 	/* Floating Point Regs */
-#ifdef CONFIG_8260
+#ifdef CONFIG_MPC8260
 	STFDM(ptr);
 	ptr += 32*2;
 #else
@@ -213,7 +213,7 @@ kgdb_getregs(struct pt_regs *regs, char *buf, int max)
 
 /* set the value of the CPU registers */
 
-#ifdef CONFIG_8260
+#ifdef CONFIG_MPC8260
 /* load floating double */
 #define LFD(n,v)	__asm__ __volatile__ ("lfd " #n ",%0" :: "o"(v))
 /* load floating double indexed */
@@ -252,7 +252,7 @@ kgdb_putreg(struct pt_regs *regs, int regno, char *buf, int length)
 		regs->gpr[regno] = *ptr;
 	else switch (regno) {
 
-#ifdef CONFIG_8260
+#ifdef CONFIG_MPC8260
 #define caseF(n) \
 	case (n) + 32:	LFD(n, *ptr);		break;
 
@@ -298,7 +298,7 @@ kgdb_putregs(struct pt_regs *regs, char *buf, int length)
 		regs->gpr[i] = *ptr++;
 
 	/* Floating Point Regs */
-#ifdef CONFIG_8260
+#ifdef CONFIG_MPC8260
 	LFDM(ptr);
 #endif
 	ptr += 32*2;
diff --git a/arch/sandbox/config.mk b/arch/sandbox/config.mk
index 6142dd4c70..e094ae2d05 100644
--- a/arch/sandbox/config.mk
+++ b/arch/sandbox/config.mk
@@ -5,5 +5,16 @@ PLATFORM_CPPFLAGS += -DCONFIG_SANDBOX -D__SANDBOX__ -U_FORTIFY_SOURCE
 PLATFORM_CPPFLAGS += -DCONFIG_ARCH_MAP_SYSMEM -DCONFIG_SYS_GENERIC_BOARD
 PLATFORM_LIBS += -lrt
 
+ifdef CONFIG_SANDBOX_SDL
+PLATFORM_LIBS += $(shell sdl-config --libs)
+PLATFORM_CPPFLAGS += $(shell sdl-config --cflags)
+endif
+
 # Support generic board on sandbox
 __HAVE_ARCH_GENERIC_BOARD := y
+
+cmd_u-boot__ = $(CC) -o $@ -T u-boot.lds \
+	-Wl,--start-group $(u-boot-main) -Wl,--end-group \
+	$(PLATFORM_LIBS) -Wl,-Map -Wl,u-boot.map
+
+CONFIG_ARCH_DEVICE_TREE := sandbox
diff --git a/arch/sandbox/cpu/Makefile b/arch/sandbox/cpu/Makefile
index e386867fe6..7d4410c42a 100644
--- a/arch/sandbox/cpu/Makefile
+++ b/arch/sandbox/cpu/Makefile
@@ -7,29 +7,16 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(CPU).o
-
-COBJS	:= cpu.o os.o start.o state.o
-
-SRCS	:= $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-
-all:	$(obj).depend $(LIB)
-
-$(LIB):	$(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
+obj-y	:= cpu.o os.o start.o state.o
+obj-$(CONFIG_SANDBOX_SDL)	+= sdl.o
 
 # os.c is build in the system environment, so needs standard includes
-$(obj)os.o: ALL_CFLAGS := $(filter-out -nostdinc,$(ALL_CFLAGS))
-$(obj).depend.os: CPPFLAGS := $(filter-out -nostdinc,$(CPPFLAGS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+# CFLAGS_REMOVE_os.o cannot be used to drop header include path
+quiet_cmd_cc_os.o = CC $(quiet_modtag)  $@
+cmd_cc_os.o = $(CC) $(filter-out -nostdinc, \
+	$(patsubst -I%,-idirafter%,$(c_flags))) -c -o $@ $<
+
+$(obj)/os.o: $(src)/os.c FORCE
+	$(call if_changed_dep,cc_os.o)
+$(obj)/sdl.o: $(src)/sdl.c FORCE
+	$(call if_changed_dep,cc_os.o)
diff --git a/arch/sandbox/cpu/cpu.c b/arch/sandbox/cpu/cpu.c
index cfc1fda1e1..3f4005b5d7 100644
--- a/arch/sandbox/cpu/cpu.c
+++ b/arch/sandbox/cpu/cpu.c
@@ -5,13 +5,23 @@
 
 #include <common.h>
 #include <os.h>
+#include <asm/state.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
-int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+void reset_cpu(ulong ignored)
 {
+	if (state_uninit())
+		os_exit(2);
+
 	/* This is considered normal termination for now */
 	os_exit(0);
+}
+
+int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	reset_cpu(0);
+
 	return 0;
 }
 
@@ -28,7 +38,14 @@ unsigned long __attribute__((no_instrument_function)) timer_get_us(void)
 
 int do_bootm_linux(int flag, int argc, char *argv[], bootm_headers_t *images)
 {
-	return -1;
+	if (flag & (BOOTM_STATE_OS_GO | BOOTM_STATE_OS_FAKE_GO)) {
+		bootstage_mark(BOOTSTAGE_ID_RUN_OS);
+		printf("## Transferring control to Linux (at address %08lx)...\n",
+		       images->ep);
+		reset_cpu(0);
+	}
+
+	return 0;
 }
 
 int cleanup_before_linux(void)
@@ -41,7 +58,7 @@ void *map_physmem(phys_addr_t paddr, unsigned long len, unsigned long flags)
 	return (void *)(gd->arch.ram_buf + paddr);
 }
 
-phys_addr_t map_to_sysmem(void *ptr)
+phys_addr_t map_to_sysmem(const void *ptr)
 {
 	return (u8 *)ptr - gd->arch.ram_buf;
 }
diff --git a/arch/sandbox/cpu/os.c b/arch/sandbox/cpu/os.c
index c2e5f57193..57d04a45b2 100644
--- a/arch/sandbox/cpu/os.c
+++ b/arch/sandbox/cpu/os.c
@@ -8,6 +8,7 @@
 #include <fcntl.h>
 #include <getopt.h>
 #include <stdio.h>
+#include <stdint.h>
 #include <stdlib.h>
 #include <string.h>
 #include <termios.h>
@@ -26,6 +27,10 @@
 
 /* Operating System Interface */
 
+struct os_mem_hdr {
+	size_t length;		/* number of bytes in the block */
+};
+
 ssize_t os_read(int fd, void *buf, size_t count)
 {
 	return read(fd, buf, count);
@@ -87,6 +92,11 @@ int os_close(int fd)
 	return close(fd);
 }
 
+int os_unlink(const char *pathname)
+{
+	return unlink(pathname);
+}
+
 void os_exit(int exit_code)
 {
 	exit(exit_code);
@@ -94,21 +104,22 @@ void os_exit(int exit_code)
 
 /* Restore tty state when we exit */
 static struct termios orig_term;
+static bool term_setup;
 
 static void os_fd_restore(void)
 {
-	tcsetattr(0, TCSANOW, &orig_term);
+	if (term_setup)
+		tcsetattr(0, TCSANOW, &orig_term);
 }
 
 /* Put tty into raw mode so <tab> and <ctrl+c> work */
-void os_tty_raw(int fd)
+void os_tty_raw(int fd, bool allow_sigs)
 {
-	static int setup = 0;
 	struct termios term;
 
-	if (setup)
+	if (term_setup)
 		return;
-	setup = 1;
+	term_setup = true;
 
 	/* If not a tty, don't complain */
 	if (tcgetattr(fd, &orig_term))
@@ -118,7 +129,7 @@ void os_tty_raw(int fd)
 	term.c_iflag = IGNBRK | IGNPAR;
 	term.c_oflag = OPOST | ONLCR;
 	term.c_cflag = CS8 | CREAD | CLOCAL;
-	term.c_lflag = 0;
+	term.c_lflag = allow_sigs ? ISIG : 0;
 	if (tcsetattr(fd, TCSANOW, &term))
 		return;
 
@@ -127,8 +138,45 @@ void os_tty_raw(int fd)
 
 void *os_malloc(size_t length)
 {
-	return mmap(NULL, length, PROT_READ | PROT_WRITE,
-			MAP_PRIVATE | MAP_ANONYMOUS, -1, 0);
+	struct os_mem_hdr *hdr;
+
+	hdr = mmap(NULL, length + sizeof(*hdr), PROT_READ | PROT_WRITE,
+		   MAP_PRIVATE | MAP_ANONYMOUS, -1, 0);
+	if (hdr == MAP_FAILED)
+		return NULL;
+	hdr->length = length;
+
+	return hdr + 1;
+}
+
+void os_free(void *ptr)
+{
+	struct os_mem_hdr *hdr = ptr;
+
+	hdr--;
+	if (ptr)
+		munmap(hdr, hdr->length + sizeof(*hdr));
+}
+
+void *os_realloc(void *ptr, size_t length)
+{
+	struct os_mem_hdr *hdr = ptr;
+	void *buf = NULL;
+
+	hdr--;
+	if (length != 0) {
+		buf = os_malloc(length);
+		if (!buf)
+			return buf;
+		if (ptr) {
+			if (length > hdr->length)
+				length = hdr->length;
+			memcpy(buf, ptr, length);
+		}
+	}
+	os_free(ptr);
+
+	return buf;
 }
 
 void os_usleep(unsigned long usec)
@@ -136,7 +184,7 @@ void os_usleep(unsigned long usec)
 	usleep(usec);
 }
 
-u64 __attribute__((no_instrument_function)) os_get_nsec(void)
+uint64_t __attribute__((no_instrument_function)) os_get_nsec(void)
 {
 #if defined(CLOCK_MONOTONIC) && defined(_POSIX_MONOTONIC_CLOCK)
 	struct timespec tp;
@@ -160,7 +208,7 @@ static struct option *long_opts;
 
 int os_parse_args(struct sandbox_state *state, int argc, char *argv[])
 {
-	struct sb_cmdline_option **sb_opt = __u_boot_sandbox_option_start;
+	struct sandbox_cmdline_option **sb_opt = __u_boot_sandbox_option_start;
 	size_t num_options = __u_boot_sandbox_option_count();
 	size_t i;
 
@@ -346,3 +394,143 @@ ssize_t os_get_filesize(const char *fname)
 		return ret;
 	return buf.st_size;
 }
+
+void os_putc(int ch)
+{
+	putchar(ch);
+}
+
+void os_puts(const char *str)
+{
+	while (*str)
+		os_putc(*str++);
+}
+
+int os_write_ram_buf(const char *fname)
+{
+	struct sandbox_state *state = state_get_current();
+	int fd, ret;
+
+	fd = open(fname, O_CREAT | O_WRONLY, 0777);
+	if (fd < 0)
+		return -ENOENT;
+	ret = write(fd, state->ram_buf, state->ram_size);
+	close(fd);
+	if (ret != state->ram_size)
+		return -EIO;
+
+	return 0;
+}
+
+int os_read_ram_buf(const char *fname)
+{
+	struct sandbox_state *state = state_get_current();
+	int fd, ret;
+	int size;
+
+	size = os_get_filesize(fname);
+	if (size < 0)
+		return -ENOENT;
+	if (size != state->ram_size)
+		return -ENOSPC;
+	fd = open(fname, O_RDONLY);
+	if (fd < 0)
+		return -ENOENT;
+
+	ret = read(fd, state->ram_buf, state->ram_size);
+	close(fd);
+	if (ret != state->ram_size)
+		return -EIO;
+
+	return 0;
+}
+
+static int make_exec(char *fname, const void *data, int size)
+{
+	int fd;
+
+	strcpy(fname, "/tmp/u-boot.jump.XXXXXX");
+	fd = mkstemp(fname);
+	if (fd < 0)
+		return -ENOENT;
+	if (write(fd, data, size) < 0)
+		return -EIO;
+	close(fd);
+	if (chmod(fname, 0777))
+		return -ENOEXEC;
+
+	return 0;
+}
+
+static int add_args(char ***argvp, const char *add_args[], int count)
+{
+	char **argv;
+	int argc;
+
+	for (argv = *argvp, argc = 0; (*argvp)[argc]; argc++)
+		;
+
+	argv = malloc((argc + count + 1) * sizeof(char *));
+	if (!argv) {
+		printf("Out of memory for %d argv\n", count);
+		return -ENOMEM;
+	}
+	memcpy(argv, *argvp, argc * sizeof(char *));
+	memcpy(argv + argc, add_args, count * sizeof(char *));
+	argv[argc + count] = NULL;
+
+	*argvp = argv;
+	return 0;
+}
+
+int os_jump_to_image(const void *dest, int size)
+{
+	struct sandbox_state *state = state_get_current();
+	char fname[30], mem_fname[30];
+	int fd, err;
+	const char *extra_args[5];
+	char **argv = state->argv;
+#ifdef DEBUG
+	int argc, i;
+#endif
+
+	err = make_exec(fname, dest, size);
+	if (err)
+		return err;
+
+	strcpy(mem_fname, "/tmp/u-boot.mem.XXXXXX");
+	fd = mkstemp(mem_fname);
+	if (fd < 0)
+		return -ENOENT;
+	close(fd);
+	err = os_write_ram_buf(mem_fname);
+	if (err)
+		return err;
+
+	os_fd_restore();
+
+	extra_args[0] = "-j";
+	extra_args[1] = fname;
+	extra_args[2] = "-m";
+	extra_args[3] = mem_fname;
+	extra_args[4] = "--rm_memory";
+	err = add_args(&argv, extra_args,
+		       sizeof(extra_args) / sizeof(extra_args[0]));
+	if (err)
+		return err;
+
+#ifdef DEBUG
+	for (i = 0; argv[i]; i++)
+		printf("%d %s\n", i, argv[i]);
+#endif
+
+	if (state_uninit())
+		os_exit(2);
+
+	err = execv(fname, argv);
+	free(argv);
+	if (err)
+		return err;
+
+	return unlink(fname);
+}
diff --git a/arch/sandbox/cpu/sdl.c b/arch/sandbox/cpu/sdl.c
new file mode 100644
index 0000000000..18dc7edf19
--- /dev/null
+++ b/arch/sandbox/cpu/sdl.c
@@ -0,0 +1,341 @@
+/*
+ * Copyright (c) 2013 Google, Inc
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <errno.h>
+#include <linux/input.h>
+#include <SDL/SDL.h>
+#include <sound.h>
+#include <asm/state.h>
+
+static struct sdl_info {
+	SDL_Surface *screen;
+	int width;
+	int height;
+	int depth;
+	int pitch;
+	uint frequency;
+	uint audio_pos;
+	uint audio_size;
+	uint8_t *audio_data;
+	bool audio_active;
+	bool inited;
+} sdl;
+
+static void sandbox_sdl_poll_events(void)
+{
+	/*
+	 * We don't want to include common.h in this file since it uses
+	 * system headers. So add a declation here.
+	 */
+	extern void reset_cpu(unsigned long addr);
+	SDL_Event event;
+
+	while (SDL_PollEvent(&event)) {
+		switch (event.type) {
+		case SDL_QUIT:
+			puts("LCD window closed - quitting\n");
+			reset_cpu(1);
+			break;
+		}
+	}
+}
+
+static int sandbox_sdl_ensure_init(void)
+{
+	if (!sdl.inited) {
+		if (SDL_Init(0) < 0) {
+			printf("Unable to initialize SDL: %s\n",
+			       SDL_GetError());
+			return -EIO;
+		}
+
+		atexit(SDL_Quit);
+
+		sdl.inited = true;
+	}
+	return 0;
+}
+
+int sandbox_sdl_init_display(int width, int height, int log2_bpp)
+{
+	struct sandbox_state *state = state_get_current();
+	int err;
+
+	if (!width || !state->show_lcd)
+		return 0;
+	err = sandbox_sdl_ensure_init();
+	if (err)
+		return err;
+	if (SDL_InitSubSystem(SDL_INIT_VIDEO) < 0) {
+		printf("Unable to initialize SDL LCD: %s\n", SDL_GetError());
+		return -EPERM;
+	}
+	SDL_WM_SetCaption("U-Boot", "U-Boot");
+
+	sdl.width = width;
+	sdl.height = height;
+	sdl.depth = 1 << log2_bpp;
+	sdl.pitch = sdl.width * sdl.depth / 8;
+	sdl.screen = SDL_SetVideoMode(width, height, 0, 0);
+	sandbox_sdl_poll_events();
+
+	return 0;
+}
+
+int sandbox_sdl_sync(void *lcd_base)
+{
+	SDL_Surface *frame;
+
+	frame = SDL_CreateRGBSurfaceFrom(lcd_base, sdl.width, sdl.height,
+			sdl.depth, sdl.pitch,
+			0x1f << 11, 0x3f << 5, 0x1f << 0, 0);
+	SDL_BlitSurface(frame, NULL, sdl.screen, NULL);
+	SDL_FreeSurface(frame);
+	SDL_UpdateRect(sdl.screen, 0, 0, 0, 0);
+	sandbox_sdl_poll_events();
+
+	return 0;
+}
+
+#define NONE (-1)
+#define NUM_SDL_CODES	(SDLK_UNDO + 1)
+
+static int16_t sdl_to_keycode[NUM_SDL_CODES] = {
+	/* 0 */
+	NONE, NONE, NONE, NONE, NONE,
+	NONE, NONE, NONE, KEY_BACKSPACE, KEY_TAB,
+	NONE, NONE, NONE, KEY_ENTER, NONE,
+	NONE, NONE, NONE, NONE, KEY_POWER,	/* use PAUSE as POWER */
+
+	/* 20 */
+	NONE, NONE, NONE, NONE, NONE,
+	NONE, NONE, KEY_ESC, NONE, NONE,
+	NONE, NONE, KEY_SPACE, NONE, NONE,
+	NONE, NONE, NONE, NONE, NONE,
+
+	/* 40 */
+	NONE, NONE, NONE, NONE, KEY_COMMA,
+	KEY_MINUS, KEY_DOT, KEY_SLASH, KEY_0, KEY_1,
+	KEY_2, KEY_3, KEY_4, KEY_5, KEY_6,
+	KEY_7, KEY_8, KEY_9, NONE, KEY_SEMICOLON,
+
+	/* 60 */
+	NONE, KEY_EQUAL, NONE, NONE, NONE,
+	NONE, NONE, NONE, NONE, NONE,
+	NONE, NONE, NONE, NONE, NONE,
+	NONE, NONE, NONE, NONE, NONE,
+
+	/* 80 */
+	NONE, NONE, NONE, NONE, NONE,
+	NONE, NONE, NONE, NONE, NONE,
+	NONE, NONE, KEY_BACKSLASH, NONE, NONE,
+	NONE, KEY_GRAVE, KEY_A, KEY_B, KEY_C,
+
+	/* 100 */
+	KEY_D, KEY_E, KEY_F, KEY_G, KEY_H,
+	KEY_I, KEY_J, KEY_K, KEY_L, KEY_M,
+	KEY_N, KEY_O, KEY_P, KEY_Q, KEY_R,
+	KEY_S, KEY_T, KEY_U, KEY_V, KEY_W,
+
+	/* 120 */
+	KEY_X, KEY_Y, KEY_Z, NONE, NONE,
+	NONE, NONE, KEY_DELETE, NONE, NONE,
+	NONE, NONE, NONE, NONE, NONE,
+	NONE, NONE, NONE, NONE, NONE,
+
+	/* 140 */
+	NONE, NONE, NONE, NONE, NONE,
+	NONE, NONE, NONE, NONE, NONE,
+	NONE, NONE, NONE, NONE, NONE,
+	NONE, NONE, NONE, NONE, NONE,
+
+	/* 160 */
+	NONE, NONE, NONE, NONE, NONE,
+	NONE, NONE, NONE, NONE, NONE,
+	NONE, NONE, NONE, NONE, NONE,
+	NONE, NONE, NONE, NONE, NONE,
+
+	/* 180 */
+	NONE, NONE, NONE, NONE, NONE,
+	NONE, NONE, NONE, NONE, NONE,
+	NONE, NONE, NONE, NONE, NONE,
+	NONE, NONE, NONE, NONE, NONE,
+
+	/* 200 */
+	NONE, NONE, NONE, NONE, NONE,
+	NONE, NONE, NONE, NONE, NONE,
+	NONE, NONE, NONE, NONE, NONE,
+	NONE, NONE, NONE, NONE, NONE,
+
+	/* 220 */
+	NONE, NONE, NONE, NONE, NONE,
+	NONE, NONE, NONE, NONE, NONE,
+	NONE, NONE, NONE, NONE, NONE,
+	NONE, NONE, NONE, NONE, NONE,
+
+	/* 240 */
+	NONE, NONE, NONE, NONE, NONE,
+	NONE, NONE, NONE, NONE, NONE,
+	NONE, NONE, NONE, NONE, NONE,
+	NONE, KEY_KP0, KEY_KP1, KEY_KP2, KEY_KP3,
+
+	/* 260 */
+	KEY_KP4, KEY_KP5, KEY_KP6, KEY_KP7, KEY_KP8,
+	KEY_KP9, KEY_KPDOT, KEY_KPSLASH, KEY_KPASTERISK, KEY_KPMINUS,
+	KEY_KPPLUS, KEY_KPENTER, KEY_KPEQUAL, KEY_UP, KEY_DOWN,
+	KEY_RIGHT, KEY_LEFT, KEY_INSERT, KEY_HOME, KEY_END,
+
+	/* 280 */
+	KEY_PAGEUP, KEY_PAGEDOWN, KEY_F1, KEY_F2, KEY_F3,
+	KEY_F4, KEY_F5, KEY_F6, KEY_F7, KEY_F8,
+	KEY_F9, KEY_F10, KEY_F11, KEY_F12, NONE,
+	NONE, NONE, NONE, NONE, NONE,
+
+	/* 300 */
+	KEY_NUMLOCK, KEY_CAPSLOCK, KEY_SCROLLLOCK, KEY_RIGHTSHIFT,
+		KEY_LEFTSHIFT,
+	KEY_RIGHTCTRL, KEY_LEFTCTRL, KEY_RIGHTALT, KEY_LEFTALT, KEY_RIGHTMETA,
+	KEY_LEFTMETA, NONE, KEY_FN, NONE, KEY_COMPOSE,
+	NONE, KEY_PRINT, KEY_SYSRQ, KEY_PAUSE, NONE,
+
+	/* 320 */
+	NONE, NONE, NONE,
+};
+
+int sandbox_sdl_scan_keys(int key[], int max_keys)
+{
+	Uint8 *keystate;
+	int i, count;
+
+	sandbox_sdl_poll_events();
+	keystate = SDL_GetKeyState(NULL);
+	for (i = count = 0; i < NUM_SDL_CODES; i++) {
+		if (count >= max_keys)
+			break;
+		else if (keystate[i])
+			key[count++] = sdl_to_keycode[i];
+	}
+
+	return count;
+}
+
+int sandbox_sdl_key_pressed(int keycode)
+{
+	int key[8];	/* allow up to 8 keys to be pressed at once */
+	int count;
+	int i;
+
+	count = sandbox_sdl_scan_keys(key, sizeof(key) / sizeof(key[0]));
+	for (i = 0; i < count; i++) {
+		if (key[i] == keycode)
+			return 0;
+	}
+
+	return -ENOENT;
+}
+
+void sandbox_sdl_fill_audio(void *udata, Uint8 *stream, int len)
+{
+	int avail;
+
+	avail = sdl.audio_size - sdl.audio_pos;
+	if (avail < len)
+		len = avail;
+
+	SDL_MixAudio(stream, sdl.audio_data + sdl.audio_pos, len,
+		     SDL_MIX_MAXVOLUME);
+	sdl.audio_pos += len;
+
+	/* Loop if we are at the end */
+	if (sdl.audio_pos == sdl.audio_size)
+		sdl.audio_pos = 0;
+}
+
+int sandbox_sdl_sound_init(void)
+{
+	SDL_AudioSpec wanted;
+
+	if (sandbox_sdl_ensure_init())
+		return -1;
+
+	if (sdl.audio_active)
+		return 0;
+
+	/*
+	 * At present all sandbox sounds crash. This is probably due to
+	 * symbol name conflicts with U-Boot. We can remove the malloc()
+	 * probles with:
+	 *
+	 * #define USE_DL_PREFIX
+	 *
+	 * and get this:
+	 *
+	 * Assertion 'e->pollfd->fd == e->fd' failed at pulse/mainloop.c:676,
+	 *		function dispatch_pollfds(). Aborting.
+	 *
+	 * The right solution is probably to make U-Boot's names private or
+	 * link os.c and sdl.c against their libraries before liking with
+	 * U-Boot. TBD. For now sound is disabled.
+	 */
+	printf("(Warning: sandbox sound disabled)\n");
+	return 0;
+
+	/* Set the audio format */
+	wanted.freq = 22050;
+	wanted.format = AUDIO_S16;
+	wanted.channels = 1;    /* 1 = mono, 2 = stereo */
+	wanted.samples = 1024;  /* Good low-latency value for callback */
+	wanted.callback = sandbox_sdl_fill_audio;
+	wanted.userdata = NULL;
+
+	sdl.audio_size = sizeof(uint16_t) * wanted.freq;
+	sdl.audio_data = malloc(sdl.audio_size);
+	if (!sdl.audio_data) {
+		printf("%s: Out of memory\n", __func__);
+		return -1;
+	}
+	sdl.audio_pos = 0;
+
+	if (SDL_InitSubSystem(SDL_INIT_AUDIO) < 0) {
+		printf("Unable to initialize SDL audio: %s\n", SDL_GetError());
+		goto err;
+	}
+
+	/* Open the audio device, forcing the desired format */
+	if (SDL_OpenAudio(&wanted, NULL) < 0) {
+		printf("Couldn't open audio: %s\n", SDL_GetError());
+		goto err;
+	}
+	sdl.audio_active = true;
+
+	return 0;
+
+err:
+	free(sdl.audio_data);
+	return -1;
+}
+
+int sandbox_sdl_sound_start(uint frequency)
+{
+	if (!sdl.audio_active)
+		return -1;
+	sdl.frequency = frequency;
+	sound_create_square_wave((unsigned short *)sdl.audio_data,
+				 sdl.audio_size, frequency);
+	sdl.audio_pos = 0;
+	SDL_PauseAudio(0);
+
+	return 0;
+}
+
+int sandbox_sdl_sound_stop(void)
+{
+	if (!sdl.audio_active)
+		return -1;
+	SDL_PauseAudio(1);
+
+	return 0;
+}
diff --git a/arch/sandbox/cpu/start.c b/arch/sandbox/cpu/start.c
index f1cb7930b1..aad3b8b147 100644
--- a/arch/sandbox/cpu/start.c
+++ b/arch/sandbox/cpu/start.c
@@ -4,16 +4,17 @@
  */
 
 #include <common.h>
+#include <os.h>
 #include <asm/getopt.h>
 #include <asm/sections.h>
 #include <asm/state.h>
 
-#include <os.h>
+DECLARE_GLOBAL_DATA_PTR;
 
 int sandbox_early_getopt_check(void)
 {
 	struct sandbox_state *state = state_get_current();
-	struct sb_cmdline_option **sb_opt = __u_boot_sandbox_option_start;
+	struct sandbox_cmdline_option **sb_opt = __u_boot_sandbox_option_start;
 	size_t num_options = __u_boot_sandbox_option_count();
 	size_t i;
 	int max_arg_len, max_noarg_len;
@@ -40,7 +41,7 @@ int sandbox_early_getopt_check(void)
 	max_noarg_len = max_arg_len + 7;
 
 	for (i = 0; i < num_options; ++i) {
-		struct sb_cmdline_option *opt = sb_opt[i];
+		struct sandbox_cmdline_option *opt = sb_opt[i];
 
 		/* first output the short flag if it has one */
 		if (opt->flag_short >= 0x100)
@@ -50,9 +51,9 @@ int sandbox_early_getopt_check(void)
 
 		/* then the long flag */
 		if (opt->has_arg)
-			printf("--%-*s", max_noarg_len, opt->flag);
-		else
 			printf("--%-*s <arg> ", max_arg_len, opt->flag);
+		else
+			printf("--%-*s", max_noarg_len, opt->flag);
 
 		/* finally the help text */
 		printf("  %s\n", opt->help);
@@ -61,12 +62,12 @@ int sandbox_early_getopt_check(void)
 	os_exit(0);
 }
 
-static int sb_cmdline_cb_help(struct sandbox_state *state, const char *arg)
+static int sandbox_cmdline_cb_help(struct sandbox_state *state, const char *arg)
 {
 	/* just flag to sandbox_early_getopt_check to show usage */
 	return 1;
 }
-SB_CMDLINE_OPT_SHORT(help, 'h', 0, "Display help");
+SANDBOX_CMDLINE_OPT_SHORT(help, 'h', 0, "Display help");
 
 int sandbox_main_loop_init(void)
 {
@@ -75,45 +76,175 @@ int sandbox_main_loop_init(void)
 	/* Execute command if required */
 	if (state->cmd) {
 		run_command_list(state->cmd, -1, 0);
-		os_exit(state->exit_type);
+		if (!state->interactive)
+			os_exit(state->exit_type);
 	}
 
 	return 0;
 }
 
-static int sb_cmdline_cb_command(struct sandbox_state *state, const char *arg)
+static int sandbox_cmdline_cb_command(struct sandbox_state *state,
+				      const char *arg)
 {
 	state->cmd = arg;
 	return 0;
 }
-SB_CMDLINE_OPT_SHORT(command, 'c', 1, "Execute U-Boot command");
+SANDBOX_CMDLINE_OPT_SHORT(command, 'c', 1, "Execute U-Boot command");
 
-static int sb_cmdline_cb_fdt(struct sandbox_state *state, const char *arg)
+static int sandbox_cmdline_cb_fdt(struct sandbox_state *state, const char *arg)
 {
 	state->fdt_fname = arg;
 	return 0;
 }
-SB_CMDLINE_OPT_SHORT(fdt, 'd', 1, "Specify U-Boot's control FDT");
+SANDBOX_CMDLINE_OPT_SHORT(fdt, 'd', 1, "Specify U-Boot's control FDT");
 
-int main(int argc, char *argv[])
+static int sandbox_cmdline_cb_interactive(struct sandbox_state *state,
+					  const char *arg)
+{
+	state->interactive = true;
+	return 0;
+}
+
+SANDBOX_CMDLINE_OPT_SHORT(interactive, 'i', 0, "Enter interactive mode");
+
+static int sandbox_cmdline_cb_jump(struct sandbox_state *state,
+				   const char *arg)
+{
+	/* Remember to delete this U-Boot image later */
+	state->jumped_fname = arg;
+
+	return 0;
+}
+SANDBOX_CMDLINE_OPT_SHORT(jump, 'j', 1, "Jumped from previous U-Boot");
+
+static int sandbox_cmdline_cb_memory(struct sandbox_state *state,
+				     const char *arg)
 {
-	struct sandbox_state *state;
 	int err;
 
-	err = state_init();
-	if (err)
+	/* For now assume we always want to write it */
+	state->write_ram_buf = true;
+	state->ram_buf_fname = arg;
+
+	if (os_read_ram_buf(arg)) {
+		printf("Failed to read RAM buffer\n");
 		return err;
+	}
+
+	return 0;
+}
+SANDBOX_CMDLINE_OPT_SHORT(memory, 'm', 1,
+			  "Read/write ram_buf memory contents from file");
+
+static int sandbox_cmdline_cb_rm_memory(struct sandbox_state *state,
+					const char *arg)
+{
+	state->ram_buf_rm = true;
+
+	return 0;
+}
+SANDBOX_CMDLINE_OPT(rm_memory, 0, "Remove memory file after reading");
+
+static int sandbox_cmdline_cb_state(struct sandbox_state *state,
+				    const char *arg)
+{
+	state->state_fname = arg;
+	return 0;
+}
+SANDBOX_CMDLINE_OPT_SHORT(state, 's', 1, "Specify the sandbox state FDT");
+
+static int sandbox_cmdline_cb_read(struct sandbox_state *state,
+				   const char *arg)
+{
+	state->read_state = true;
+	return 0;
+}
+SANDBOX_CMDLINE_OPT_SHORT(read, 'r', 0, "Read the state FDT on startup");
+
+static int sandbox_cmdline_cb_write(struct sandbox_state *state,
+				    const char *arg)
+{
+	state->write_state = true;
+	return 0;
+}
+SANDBOX_CMDLINE_OPT_SHORT(write, 'w', 0, "Write state FDT on exit");
+
+static int sandbox_cmdline_cb_ignore_missing(struct sandbox_state *state,
+					     const char *arg)
+{
+	state->ignore_missing_state_on_read = true;
+	return 0;
+}
+SANDBOX_CMDLINE_OPT_SHORT(ignore_missing, 'n', 0,
+			  "Ignore missing state on read");
+
+static int sandbox_cmdline_cb_show_lcd(struct sandbox_state *state,
+				       const char *arg)
+{
+	state->show_lcd = true;
+	return 0;
+}
+SANDBOX_CMDLINE_OPT_SHORT(show_lcd, 'l', 0,
+			  "Show the sandbox LCD display");
+
+static const char *term_args[STATE_TERM_COUNT] = {
+	"raw-with-sigs",
+	"raw",
+	"cooked",
+};
+
+static int sandbox_cmdline_cb_terminal(struct sandbox_state *state,
+				       const char *arg)
+{
+	int i;
+
+	for (i = 0; i < STATE_TERM_COUNT; i++) {
+		if (!strcmp(arg, term_args[i])) {
+			state->term_raw = i;
+			return 0;
+		}
+	}
+
+	printf("Unknown terminal setting '%s' (", arg);
+	for (i = 0; i < STATE_TERM_COUNT; i++)
+		printf("%s%s", i ? ", " : "", term_args[i]);
+	puts(")\n");
+
+	return 1;
+}
+SANDBOX_CMDLINE_OPT_SHORT(terminal, 't', 1,
+			  "Set terminal to raw/cooked mode");
+
+int main(int argc, char *argv[])
+{
+	struct sandbox_state *state;
+	int ret;
+
+	ret = state_init();
+	if (ret)
+		goto err;
 
 	state = state_get_current();
 	if (os_parse_args(state, argc, argv))
 		return 1;
 
-	/*
-	 * Do pre- and post-relocation init, then start up U-Boot. This will
-	 * never return.
-	 */
+	ret = sandbox_read_state(state, state->state_fname);
+	if (ret)
+		goto err;
+
+	/* Remove old memory file if required */
+	if (state->ram_buf_rm && state->ram_buf_fname)
+		os_unlink(state->ram_buf_fname);
+
+	/* Do pre- and post-relocation init */
 	board_init_f(0);
 
-	/* NOTREACHED - board_init_f() does not return */
+	board_init_r(gd->new_gd, 0);
+
+	/* NOTREACHED - board_init_r() does not return */
 	return 0;
+
+err:
+	printf("Error %d\n", ret);
+	return 1;
 }
diff --git a/arch/sandbox/cpu/state.c b/arch/sandbox/cpu/state.c
index 56d5041411..59adad653c 100644
--- a/arch/sandbox/cpu/state.c
+++ b/arch/sandbox/cpu/state.c
@@ -4,6 +4,9 @@
  */
 
 #include <common.h>
+#include <errno.h>
+#include <fdtdec.h>
+#include <os.h>
 #include <asm/state.h>
 
 /* Main state record for the sandbox */
@@ -15,6 +18,324 @@ void state_record_exit(enum exit_type_id exit_type)
 	state->exit_type = exit_type;
 }
 
+static int state_ensure_space(int extra_size)
+{
+	void *blob = state->state_fdt;
+	int used, size, free;
+	void *buf;
+	int ret;
+
+	used = fdt_off_dt_strings(blob) + fdt_size_dt_strings(blob);
+	size = fdt_totalsize(blob);
+	free = size - used;
+	if (free > extra_size)
+		return 0;
+
+	size = used + extra_size;
+	buf = os_malloc(size);
+	if (!buf)
+		return -ENOMEM;
+
+	ret = fdt_open_into(blob, buf, size);
+	if (ret) {
+		os_free(buf);
+		return -EIO;
+	}
+
+	os_free(blob);
+	state->state_fdt = buf;
+	return 0;
+}
+
+static int state_read_file(struct sandbox_state *state, const char *fname)
+{
+	int size;
+	int ret;
+	int fd;
+
+	size = os_get_filesize(fname);
+	if (size < 0) {
+		printf("Cannot find sandbox state file '%s'\n", fname);
+		return -ENOENT;
+	}
+	state->state_fdt = os_malloc(size);
+	if (!state->state_fdt) {
+		puts("No memory to read sandbox state\n");
+		return -ENOMEM;
+	}
+	fd = os_open(fname, OS_O_RDONLY);
+	if (fd < 0) {
+		printf("Cannot open sandbox state file '%s'\n", fname);
+		ret = -EPERM;
+		goto err_open;
+	}
+	if (os_read(fd, state->state_fdt, size) != size) {
+		printf("Cannot read sandbox state file '%s'\n", fname);
+		ret = -EIO;
+		goto err_read;
+	}
+	os_close(fd);
+
+	return 0;
+err_read:
+	os_close(fd);
+err_open:
+	os_free(state->state_fdt);
+	state->state_fdt = NULL;
+
+	return ret;
+}
+
+/***
+ * sandbox_read_state_nodes() - Read state associated with a driver
+ *
+ * This looks through all compatible nodes and calls the read function on
+ * each one, to read in the state.
+ *
+ * If nothing is found, it still calls the read function once, to set up a
+ * single global state for that driver.
+ *
+ * @state: Sandbox state
+ * @io: Method to use for reading state
+ * @blob: FDT containing state
+ * @return 0 if OK, -EINVAL if the read function returned failure
+ */
+int sandbox_read_state_nodes(struct sandbox_state *state,
+			     struct sandbox_state_io *io, const void *blob)
+{
+	int count;
+	int node;
+	int ret;
+
+	debug("   - read %s\n", io->name);
+	if (!io->read)
+		return 0;
+
+	node = -1;
+	count = 0;
+	while (blob) {
+		node = fdt_node_offset_by_compatible(blob, node, io->compat);
+		if (node < 0)
+			return 0;	/* No more */
+		debug("   - read node '%s'\n", fdt_get_name(blob, node, NULL));
+		ret = io->read(blob, node);
+		if (ret) {
+			printf("Unable to read state for '%s'\n", io->compat);
+			return -EINVAL;
+		}
+		count++;
+	}
+
+	/*
+	 * If we got no saved state, call the read function once without a
+	 * node, to set up the global state.
+	 */
+	if (count == 0) {
+		debug("   - read global\n");
+		ret = io->read(NULL, -1);
+		if (ret) {
+			printf("Unable to read global state for '%s'\n",
+			       io->name);
+			return -EINVAL;
+		}
+	}
+
+	return 0;
+}
+
+int sandbox_read_state(struct sandbox_state *state, const char *fname)
+{
+	struct sandbox_state_io *io;
+	const void *blob;
+	bool got_err;
+	int ret;
+
+	if (state->read_state && fname) {
+		ret = state_read_file(state, fname);
+		if (ret == -ENOENT && state->ignore_missing_state_on_read)
+			ret = 0;
+		if (ret)
+			return ret;
+	}
+
+	/* Call all the state read funtcions */
+	got_err = false;
+	blob = state->state_fdt;
+	io = ll_entry_start(struct sandbox_state_io, state_io);
+	for (; io < ll_entry_end(struct sandbox_state_io, state_io); io++) {
+		ret = sandbox_read_state_nodes(state, io, blob);
+		if (ret < 0)
+			got_err = true;
+	}
+
+	if (state->read_state && fname) {
+		debug("Read sandbox state from '%s'%s\n", fname,
+		      got_err ? " (with errors)" : "");
+	}
+
+	return got_err ? -1 : 0;
+}
+
+/***
+ * sandbox_write_state_node() - Write state associated with a driver
+ *
+ * This calls the write function to write out global state for that driver.
+ *
+ * TODO(sjg@chromium.org): Support writing out state from multiple drivers
+ * of the same time. We don't need this yet,and it will be much easier to
+ * do when driver model is available.
+ *
+ * @state: Sandbox state
+ * @io: Method to use for writing state
+ * @return 0 if OK, -EIO if there is a fatal error (such as out of space
+ * for adding the data), -EINVAL if the write function failed.
+ */
+int sandbox_write_state_node(struct sandbox_state *state,
+			     struct sandbox_state_io *io)
+{
+	void *blob;
+	int node;
+	int ret;
+
+	if (!io->write)
+		return 0;
+
+	ret = state_ensure_space(SANDBOX_STATE_MIN_SPACE);
+	if (ret) {
+		printf("Failed to add more space for state\n");
+		return -EIO;
+	}
+
+	/* The blob location can change when the size increases */
+	blob = state->state_fdt;
+	node = fdt_node_offset_by_compatible(blob, -1, io->compat);
+	if (node == -FDT_ERR_NOTFOUND) {
+		node = fdt_add_subnode(blob, 0, io->name);
+		if (node < 0) {
+			printf("Cannot create node '%s': %s\n", io->name,
+			       fdt_strerror(node));
+			return -EIO;
+		}
+
+		if (fdt_setprop_string(blob, node, "compatible", io->compat)) {
+			puts("Cannot set compatible\n");
+			return -EIO;
+		}
+	} else if (node < 0) {
+		printf("Cannot access node '%s': %s\n", io->name,
+		       fdt_strerror(node));
+		return -EIO;
+	}
+	debug("Write state for '%s' to node %d\n", io->compat, node);
+	ret = io->write(blob, node);
+	if (ret) {
+		printf("Unable to write state for '%s'\n", io->compat);
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+int sandbox_write_state(struct sandbox_state *state, const char *fname)
+{
+	struct sandbox_state_io *io;
+	bool got_err;
+	int size;
+	int ret;
+	int fd;
+
+	/* Create a state FDT if we don't have one */
+	if (!state->state_fdt) {
+		size = 0x4000;
+		state->state_fdt = os_malloc(size);
+		if (!state->state_fdt) {
+			puts("No memory to create FDT\n");
+			return -ENOMEM;
+		}
+		ret = fdt_create_empty_tree(state->state_fdt, size);
+		if (ret < 0) {
+			printf("Cannot create empty state FDT: %s\n",
+			       fdt_strerror(ret));
+			ret = -EIO;
+			goto err_create;
+		}
+	}
+
+	/* Call all the state write funtcions */
+	got_err = false;
+	io = ll_entry_start(struct sandbox_state_io, state_io);
+	ret = 0;
+	for (; io < ll_entry_end(struct sandbox_state_io, state_io); io++) {
+		ret = sandbox_write_state_node(state, io);
+		if (ret == -EIO)
+			break;
+		else if (ret)
+			got_err = true;
+	}
+
+	if (ret == -EIO) {
+		printf("Could not write sandbox state\n");
+		goto err_create;
+	}
+
+	ret = fdt_pack(state->state_fdt);
+	if (ret < 0) {
+		printf("Cannot pack state FDT: %s\n", fdt_strerror(ret));
+		ret = -EINVAL;
+		goto err_create;
+	}
+	size = fdt_totalsize(state->state_fdt);
+	fd = os_open(fname, OS_O_WRONLY | OS_O_CREAT);
+	if (fd < 0) {
+		printf("Cannot open sandbox state file '%s'\n", fname);
+		ret = -EIO;
+		goto err_create;
+	}
+	if (os_write(fd, state->state_fdt, size) != size) {
+		printf("Cannot write sandbox state file '%s'\n", fname);
+		ret = -EIO;
+		goto err_write;
+	}
+	os_close(fd);
+
+	debug("Wrote sandbox state to '%s'%s\n", fname,
+	      got_err ? " (with errors)" : "");
+
+	return 0;
+err_write:
+	os_close(fd);
+err_create:
+	os_free(state->state_fdt);
+
+	return ret;
+}
+
+int state_setprop(int node, const char *prop_name, const void *data, int size)
+{
+	void *blob;
+	int len;
+	int ret;
+
+	fdt_getprop(state->state_fdt, node, prop_name, &len);
+
+	/* Add space for the new property, its name and some overhead */
+	ret = state_ensure_space(size - len + strlen(prop_name) + 32);
+	if (ret)
+		return ret;
+
+	/* This should succeed, barring a mutiny */
+	blob = state->state_fdt;
+	ret = fdt_setprop(blob, node, prop_name, data, size);
+	if (ret) {
+		printf("%s: Unable to set property '%s' in node '%s': %s\n",
+		       __func__, prop_name, fdt_get_name(blob, node, NULL),
+			fdt_strerror(ret));
+		return -ENOSPC;
+	}
+
+	return 0;
+}
+
 struct sandbox_state *state_get_current(void)
 {
 	assert(state);
@@ -25,6 +346,10 @@ int state_init(void)
 {
 	state = &main_state;
 
+	state->ram_size = CONFIG_SYS_SDRAM_SIZE;
+	state->ram_buf = os_malloc(state->ram_size);
+	assert(state->ram_buf);
+
 	/*
 	 * Example of how to use GPIOs:
 	 *
@@ -33,3 +358,35 @@ int state_init(void)
 	 */
 	return 0;
 }
+
+int state_uninit(void)
+{
+	int err;
+
+	state = &main_state;
+
+	if (state->write_ram_buf && !state->ram_buf_rm) {
+		err = os_write_ram_buf(state->ram_buf_fname);
+		if (err) {
+			printf("Failed to write RAM buffer\n");
+			return err;
+		}
+	}
+
+	if (state->write_state) {
+		if (sandbox_write_state(state, state->state_fname)) {
+			printf("Failed to write sandbox state\n");
+			return -1;
+		}
+	}
+
+	/* Delete this at the last moment so as not to upset gdb too much */
+	if (state->jumped_fname)
+		os_unlink(state->jumped_fname);
+
+	if (state->state_fdt)
+		os_free(state->state_fdt);
+	memset(state, '\0', sizeof(*state));
+
+	return 0;
+}
diff --git a/arch/sandbox/dts/Makefile b/arch/sandbox/dts/Makefile
new file mode 100644
index 0000000000..a4c980b235
--- /dev/null
+++ b/arch/sandbox/dts/Makefile
@@ -0,0 +1,11 @@
+dtb-$(CONFIG_SANDBOX) += sandbox.dtb
+
+targets += $(dtb-y)
+
+DTC_FLAGS += -R 4 -p 0x1000
+
+PHONY += dtbs
+dtbs: $(addprefix $(obj)/, $(dtb-y))
+	@:
+
+clean-files := *.dtb
diff --git a/arch/sandbox/dts/sandbox.dts b/arch/sandbox/dts/sandbox.dts
new file mode 100644
index 0000000000..62d803789c
--- /dev/null
+++ b/arch/sandbox/dts/sandbox.dts
@@ -0,0 +1,116 @@
+/dts-v1/;
+
+/ {
+	triangle {
+		compatible = "demo-shape";
+		colour = "cyan";
+		sides = <3>;
+		character = <83>;
+	};
+	square {
+		compatible = "demo-shape";
+		colour = "blue";
+		sides = <4>;
+	};
+	hexagon {
+		compatible = "demo-simple";
+		colour = "white";
+		sides = <6>;
+	};
+
+	host@0 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "sandbox,host-emulation";
+		cros-ec@0 {
+			reg = <0>;
+			compatible = "google,cros-ec";
+
+			/*
+			 * This describes the flash memory within the EC. Note
+			 * that the STM32L flash erases to 0, not 0xff.
+			 */
+			#address-cells = <1>;
+			#size-cells = <1>;
+			flash@8000000 {
+				reg = <0x08000000 0x20000>;
+				erase-value = <0>;
+				#address-cells = <1>;
+				#size-cells = <1>;
+
+				/* Information for sandbox */
+				ro {
+					reg = <0 0xf000>;
+				};
+				wp-ro {
+					reg = <0xf000 0x1000>;
+				};
+				rw {
+					reg = <0x10000 0x10000>;
+				};
+			};
+		};
+	};
+
+	lcd {
+		compatible = "sandbox,lcd-sdl";
+		xres = <800>;
+		yres = <600>;
+	};
+
+	cros-ec-keyb {
+		compatible = "google,cros-ec-keyb";
+		google,key-rows = <8>;
+		google,key-columns = <13>;
+		google,repeat-delay-ms = <240>;
+		google,repeat-rate-ms = <30>;
+		google,ghost-filter;
+		/*
+		 * Keymap entries take the form of 0xRRCCKKKK where
+		 * RR=Row CC=Column KKKK=Key Code
+		 * The values below are for a US keyboard layout and
+		 * are taken from the Linux driver. Note that the
+		 * 102ND key is not used for US keyboards.
+		 */
+		linux,keymap = <
+			/* CAPSLCK F1         B          F10     */
+			0x0001003a 0x0002003b 0x00030030 0x00040044
+			/* N       =          R_ALT      ESC     */
+			0x00060031 0x0008000d 0x000a0064 0x01010001
+			/* F4      G          F7         H       */
+			0x0102003e 0x01030022 0x01040041 0x01060023
+			/* '       F9         BKSPACE    L_CTRL  */
+			0x01080028 0x01090043 0x010b000e 0x0200001d
+			/* TAB     F3         T          F6      */
+			0x0201000f 0x0202003d 0x02030014 0x02040040
+			/* ]       Y          102ND      [       */
+			0x0205001b 0x02060015 0x02070056 0x0208001a
+			/* F8      GRAVE      F2         5       */
+			0x02090042 0x03010029 0x0302003c 0x03030006
+			/* F5      6          -          \       */
+			0x0304003f 0x03060007 0x0308000c 0x030b002b
+			/* R_CTRL  A          D          F       */
+			0x04000061 0x0401001e 0x04020020 0x04030021
+			/* S       K          J          ;       */
+			0x0404001f 0x04050025 0x04060024 0x04080027
+			/* L       ENTER      Z          C       */
+			0x04090026 0x040b001c 0x0501002c 0x0502002e
+			/* V       X          ,          M       */
+			0x0503002f 0x0504002d 0x05050033 0x05060032
+			/* L_SHIFT /          .          SPACE   */
+			0x0507002a 0x05080035 0x05090034 0x050B0039
+			/* 1       3          4          2       */
+			0x06010002 0x06020004 0x06030005 0x06040003
+			/* 8       7          0          9       */
+			0x06050009 0x06060008 0x0608000b 0x0609000a
+			/* L_ALT   DOWN       RIGHT      Q       */
+			0x060a0038 0x060b006c 0x060c006a 0x07010010
+			/* E       R          W          I       */
+			0x07020012 0x07030013 0x07040011 0x07050017
+			/* U       R_SHIFT    P          O       */
+			0x07060016 0x07070036 0x07080019 0x07090018
+			/* UP      LEFT    */
+			0x070b0067 0x070c0069>;
+	};
+
+};
diff --git a/arch/sandbox/include/asm/arch-sandbox/sound.h b/arch/sandbox/include/asm/arch-sandbox/sound.h
new file mode 100644
index 0000000000..a32e8c802d
--- /dev/null
+++ b/arch/sandbox/include/asm/arch-sandbox/sound.h
@@ -0,0 +1,14 @@
+/*
+ * Copyright (c) 2013 Google, Inc
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __SANDBOX_SOUND_H
+#define __SANDBOX_SOUND_H
+
+int sound_play(unsigned int msec, unsigned int frequency);
+
+int sound_init(const void *blob);
+
+#endif
diff --git a/arch/sandbox/include/asm/config.h b/arch/sandbox/include/asm/config.h
index 7755a4deff..ec7729eb4c 100644
--- a/arch/sandbox/include/asm/config.h
+++ b/arch/sandbox/include/asm/config.h
@@ -9,4 +9,12 @@
 
 #define CONFIG_SANDBOX_ARCH
 
+/* Used by drivers/spi/sandbox_spi.c and arch/sandbox/include/asm/state.h */
+#ifndef CONFIG_SANDBOX_SPI_MAX_BUS
+#define CONFIG_SANDBOX_SPI_MAX_BUS 1
+#endif
+#ifndef CONFIG_SANDBOX_SPI_MAX_CS
+#define CONFIG_SANDBOX_SPI_MAX_CS 10
+#endif
+
 #endif
diff --git a/arch/sandbox/include/asm/getopt.h b/arch/sandbox/include/asm/getopt.h
index 685883cd3f..3048c2cc30 100644
--- a/arch/sandbox/include/asm/getopt.h
+++ b/arch/sandbox/include/asm/getopt.h
@@ -18,7 +18,7 @@ struct sandbox_state;
  * consumer code should focus on the macros below and
  * the callback function.
  */
-struct sb_cmdline_option {
+struct sandbox_cmdline_option {
 	/* The long flag name: "help" for "--help" */
 	const char *flag;
 	/* The (optional) short flag name: "h" for "-h" */
@@ -35,18 +35,19 @@ struct sb_cmdline_option {
  * Internal macro to expand the lower macros into the necessary
  * magic junk that makes this all work.
  */
-#define _SB_CMDLINE_OPT(f, s, ha, h) \
-	static struct sb_cmdline_option sb_cmdline_option_##f = { \
+#define _SANDBOX_CMDLINE_OPT(f, s, ha, h) \
+	static struct sandbox_cmdline_option sandbox_cmdline_option_##f = { \
 		.flag = #f, \
 		.flag_short = s, \
 		.help = h, \
 		.has_arg = ha, \
-		.callback = sb_cmdline_cb_##f, \
+		.callback = sandbox_cmdline_cb_##f, \
 	}; \
 	/* Ppointer to the struct in a special section for the linker script */ \
 	static __attribute__((section(".u_boot_sandbox_getopt"), used)) \
-		struct sb_cmdline_option *sb_cmdline_option_##f##_ptr = \
-		&sb_cmdline_option_##f
+		struct sandbox_cmdline_option \
+			*sandbox_cmdline_option_##f##_ptr = \
+			&sandbox_cmdline_option_##f
 
 /**
  * Macros for end code to declare new command line flags.
@@ -56,16 +57,16 @@ struct sb_cmdline_option {
  * @param h   The help string displayed when showing --help
  *
  * This invocation:
- *   SB_CMDLINE_OPT(foo, 0, "The foo arg");
+ *   SANDBOX_CMDLINE_OPT(foo, 0, "The foo arg");
  * Will create a new flag named "--foo" (no short option) that takes
  * no argument.  If the user specifies "--foo", then the callback func
- * sb_cmdline_cb_foo() will automatically be called.
+ * sandbox_cmdline_cb_foo() will automatically be called.
  */
-#define SB_CMDLINE_OPT(f, ha, h) _SB_CMDLINE_OPT(f, 0, ha, h)
+#define SANDBOX_CMDLINE_OPT(f, ha, h) _SANDBOX_CMDLINE_OPT(f, 0, ha, h)
 /*
  * Same as above, but @s is used to specify a short flag e.g.
- *   SB_CMDLINE_OPT(foo, 'f', 0, "The foo arg");
+ *   SANDBOX_CMDLINE_OPT(foo, 'f', 0, "The foo arg");
  */
-#define SB_CMDLINE_OPT_SHORT(f, s, ha, h) _SB_CMDLINE_OPT(f, s, ha, h)
+#define SANDBOX_CMDLINE_OPT_SHORT(f, s, ha, h) _SANDBOX_CMDLINE_OPT(f, s, ha, h)
 
 #endif
diff --git a/arch/sandbox/include/asm/global_data.h b/arch/sandbox/include/asm/global_data.h
index d70532aa4d..b2e9b488f1 100644
--- a/arch/sandbox/include/asm/global_data.h
+++ b/arch/sandbox/include/asm/global_data.h
@@ -12,7 +12,7 @@
 
 /* Architecture-specific global data */
 struct arch_global_data {
-	u8		*ram_buf;	/* emulated RAM buffer */
+	uint8_t		*ram_buf;	/* emulated RAM buffer */
 };
 
 #include <asm-generic/global_data.h>
diff --git a/arch/sandbox/include/asm/gpio.h b/arch/sandbox/include/asm/gpio.h
index afb9c7842f..95b59da6b4 100644
--- a/arch/sandbox/include/asm/gpio.h
+++ b/arch/sandbox/include/asm/gpio.h
@@ -29,7 +29,7 @@
  * @param gp	GPIO number
  * @return -1 on error, 0 if GPIO is low, >0 if high
  */
-int sandbox_gpio_get_value(unsigned gp);
+int sandbox_gpio_get_value(struct device *dev, unsigned int offset);
 
 /**
  * Set the simulated value of a GPIO (used only in sandbox test code)
@@ -38,7 +38,7 @@ int sandbox_gpio_get_value(unsigned gp);
  * @param value	value to set (0 for low, non-zero for high)
  * @return -1 on error, 0 if ok
  */
-int sandbox_gpio_set_value(unsigned gp, int value);
+int sandbox_gpio_set_value(struct device *dev, unsigned int offset, int value);
 
 /**
  * Return the simulated direction of a GPIO (used only in sandbox test code)
@@ -46,7 +46,7 @@ int sandbox_gpio_set_value(unsigned gp, int value);
  * @param gp	GPIO number
  * @return -1 on error, 0 if GPIO is input, >0 if output
  */
-int sandbox_gpio_get_direction(unsigned gp);
+int sandbox_gpio_get_direction(struct device *dev, unsigned int offset);
 
 /**
  * Set the simulated direction of a GPIO (used only in sandbox test code)
@@ -55,11 +55,7 @@ int sandbox_gpio_get_direction(unsigned gp);
  * @param output 0 to set as input, 1 to set as output
  * @return -1 on error, 0 if ok
  */
-int sandbox_gpio_set_direction(unsigned gp, int output);
-
-/* Display information about each GPIO */
-void gpio_info(void);
-
-#define gpio_status()	gpio_info()
+int sandbox_gpio_set_direction(struct device *dev, unsigned int offset,
+			       int output);
 
 #endif
diff --git a/arch/sandbox/include/asm/io.h b/arch/sandbox/include/asm/io.h
index 9ac6a5f00d..7956041171 100644
--- a/arch/sandbox/include/asm/io.h
+++ b/arch/sandbox/include/asm/io.h
@@ -38,6 +38,6 @@ static inline void unmap_sysmem(const void *vaddr)
 }
 
 /* Map from a pointer to our RAM buffer */
-phys_addr_t map_to_sysmem(void *ptr);
+phys_addr_t map_to_sysmem(const void *ptr);
 
 #endif
diff --git a/arch/sandbox/include/asm/sdl.h b/arch/sandbox/include/asm/sdl.h
new file mode 100644
index 0000000000..6edec1acfa
--- /dev/null
+++ b/arch/sandbox/include/asm/sdl.h
@@ -0,0 +1,118 @@
+/*
+ * Copyright (c) 2013 Google, Inc
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __SANDBOX_SDL_H
+#define __SANDBOX_SDL_H
+
+#include <errno.h>
+
+#ifdef CONFIG_SANDBOX_SDL
+
+/**
+ * sandbox_sdl_init_display() - Set up SDL video ready for use
+ *
+ * @width:	Window width in pixels
+ * @height	Window height in pixels
+ * @log2_bpp:	Log to base 2 of the number of bits per pixel. So a 32bpp
+ *		display will pass 5, since 2*5 = 32
+ * @return 0 if OK, -ENODEV if no device, -EIO if SDL failed to initialize
+ *		and -EPERM if the video failed to come up.
+ */
+int sandbox_sdl_init_display(int width, int height, int log2_bpp);
+
+/**
+ * sandbox_sdl_sync() - Sync current U-Boot LCD frame buffer to SDL
+ *
+ * This must be called periodically to update the screen for SDL so that the
+ * user can see it.
+ *
+ * @lcd_base: Base of frame buffer
+ * @return 0 if screen was updated, -ENODEV is there is no screen.
+ */
+int sandbox_sdl_sync(void *lcd_base);
+
+/**
+ * sandbox_sdl_scan_keys() - scan for pressed keys
+ *
+ * Works out which keys are pressed and returns a list
+ *
+ * @key:	Array to receive keycodes
+ * @max_keys:	Size of array
+ * @return number of keycodes found, 0 if none, -ENODEV if no keyboard
+ */
+int sandbox_sdl_scan_keys(int key[], int max_keys);
+
+/**
+ * sandbox_sdl_key_pressed() - check if a particular key is pressed
+ *
+ * @keycode:	Keycode to check (KEY_... - see include/linux/input.h
+ * @return 0 if pressed, -ENOENT if not pressed. -ENODEV if keybord not
+ * available,
+ */
+int sandbox_sdl_key_pressed(int keycode);
+
+/**
+ * sandbox_sdl_sound_start() - start playing a sound
+ *
+ * @frequency:	Frequency of sounds in Hertz
+ * @return 0 if OK, -ENODEV if no sound is available
+ */
+int sandbox_sdl_sound_start(uint frequency);
+
+/**
+ * sandbox_sdl_sound_stop() - stop playing a sound
+ *
+ * @return 0 if OK, -ENODEV if no sound is available
+ */
+int sandbox_sdl_sound_stop(void);
+
+/**
+ * sandbox_sdl_sound_init() - set up the sound system
+ *
+ * @return 0 if OK, -ENODEV if no sound is available
+ */
+int sandbox_sdl_sound_init(void);
+
+#else
+static inline int sandbox_sdl_init_display(int width, int height,
+					    int log2_bpp)
+{
+	return -ENODEV;
+}
+
+static inline int sandbox_sdl_sync(void *lcd_base)
+{
+	return -ENODEV;
+}
+
+static inline int sandbox_sdl_scan_keys(int key[], int max_keys)
+{
+	return -ENODEV;
+}
+
+static inline int sandbox_sdl_key_pressed(int keycode)
+{
+	return -ENODEV;
+}
+
+static inline int sandbox_sdl_sound_start(uint frequency)
+{
+	return -ENODEV;
+}
+
+static inline int sandbox_sdl_sound_stop(void)
+{
+	return -ENODEV;
+}
+
+static inline int sandbox_sdl_sound_init(void)
+{
+	return -ENODEV;
+}
+
+#endif
+
+#endif
diff --git a/arch/sandbox/include/asm/sections.h b/arch/sandbox/include/asm/sections.h
index 4c378600b0..fbc1bd11a3 100644
--- a/arch/sandbox/include/asm/sections.h
+++ b/arch/sandbox/include/asm/sections.h
@@ -11,9 +11,9 @@
 
 #include <asm-generic/sections.h>
 
-struct sb_cmdline_option;
+struct sandbox_cmdline_option;
 
-extern struct sb_cmdline_option *__u_boot_sandbox_option_start[],
+extern struct sandbox_cmdline_option *__u_boot_sandbox_option_start[],
 	*__u_boot_sandbox_option_end[];
 
 static inline size_t __u_boot_sandbox_option_count(void)
diff --git a/arch/sandbox/include/asm/spi.h b/arch/sandbox/include/asm/spi.h
new file mode 100644
index 0000000000..49b4a0f103
--- /dev/null
+++ b/arch/sandbox/include/asm/spi.h
@@ -0,0 +1,58 @@
+/*
+ * Simulate a SPI port and clients (see README.sandbox for details)
+ *
+ * Copyright (c) 2011-2013 The Chromium OS Authors.
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+#ifndef __ASM_SPI_H__
+#define __ASM_SPI_H__
+
+#include <linux/types.h>
+
+/*
+ * The interface between the SPI bus and the SPI client.  The bus will
+ * instantiate a client, and that then call into it via these entry
+ * points.  These should be enough for the client to emulate the SPI
+ * device just like the real hardware.
+ */
+struct sandbox_spi_emu_ops {
+	/* The bus wants to instantiate a new client, so setup everything */
+	int (*setup)(void **priv, const char *spec);
+	/* The bus is done with us, so break things down */
+	void (*free)(void *priv);
+	/* The CS has been "activated" -- we won't worry about low/high */
+	void (*cs_activate)(void *priv);
+	/* The CS has been "deactivated" -- we won't worry about low/high */
+	void (*cs_deactivate)(void *priv);
+	/* The client is rx-ing bytes from the bus, so it should tx some */
+	int (*xfer)(void *priv, const u8 *rx, u8 *tx, uint bytes);
+};
+
+/*
+ * There are times when the data lines are allowed to tristate.  What
+ * is actually sensed on the line depends on the hardware.  It could
+ * always be 0xFF/0x00 (if there are pull ups/downs), or things could
+ * float and so we'd get garbage back.  This func encapsulates that
+ * scenario so we can worry about the details here.
+ */
+static inline void sandbox_spi_tristate(u8 *buf, uint len)
+{
+	/* XXX: make this into a user config option ? */
+	memset(buf, 0xff, len);
+}
+
+/*
+ * Extract the bus/cs from the spi spec and return the start of the spi
+ * client spec.  If the bus/cs are invalid for the current config, then
+ * it returns NULL.
+ *
+ * Example: arg="0:1:foo" will set bus to 0, cs to 1, and return "foo"
+ */
+const char *sandbox_spi_parse_spec(const char *arg, unsigned long *bus,
+				   unsigned long *cs);
+
+#endif
diff --git a/arch/sandbox/include/asm/state.h b/arch/sandbox/include/asm/state.h
index 093c81d918..d17a82e90f 100644
--- a/arch/sandbox/include/asm/state.h
+++ b/arch/sandbox/include/asm/state.h
@@ -7,6 +7,8 @@
 #define __SANDBOX_STATE_H
 
 #include <config.h>
+#include <stdbool.h>
+#include <linux/stringify.h>
 
 /* How we exited U-Boot */
 enum exit_type_id {
@@ -15,16 +17,127 @@ enum exit_type_id {
 	STATE_EXIT_POWER_OFF,
 };
 
+/**
+ * Selects the behavior of the serial terminal.
+ *
+ * If Ctrl-C is processed by U-Boot, then the only way to quit sandbox is with
+ * the 'reset' command, or equivalent.
+ *
+ * If the terminal is cooked, then Ctrl-C will terminate U-Boot, and the
+ * command line will not be quite such a faithful emulation.
+ *
+ * Options are:
+ *
+ *	raw-with-sigs		- Raw, but allow signals (Ctrl-C will quit)
+ *	raw			- Terminal is always raw
+ *	cooked			- Terminal is always cooked
+ */
+enum state_terminal_raw {
+	STATE_TERM_RAW_WITH_SIGS,	/* Default */
+	STATE_TERM_RAW,
+	STATE_TERM_COOKED,
+
+	STATE_TERM_COUNT,
+};
+
+struct sandbox_spi_info {
+	const char *spec;
+	const struct sandbox_spi_emu_ops *ops;
+};
+
 /* The complete state of the test system */
 struct sandbox_state {
 	const char *cmd;		/* Command to execute */
+	bool interactive;		/* Enable cmdline after execute */
 	const char *fdt_fname;		/* Filename of FDT binary */
 	enum exit_type_id exit_type;	/* How we exited U-Boot */
 	const char *parse_err;		/* Error to report from parsing */
 	int argc;			/* Program arguments */
-	char **argv;
+	char **argv;			/* Command line arguments */
+	const char *jumped_fname;	/* Jumped from previous U_Boot */
+	uint8_t *ram_buf;		/* Emulated RAM buffer */
+	unsigned int ram_size;		/* Size of RAM buffer */
+	const char *ram_buf_fname;	/* Filename to use for RAM buffer */
+	bool ram_buf_rm;		/* Remove RAM buffer file after read */
+	bool write_ram_buf;		/* Write RAM buffer on exit */
+	const char *state_fname;	/* File containing sandbox state */
+	void *state_fdt;		/* Holds saved state for sandbox */
+	bool read_state;		/* Read sandbox state on startup */
+	bool write_state;		/* Write sandbox state on exit */
+	bool ignore_missing_state_on_read;	/* No error if state missing */
+	bool show_lcd;			/* Show LCD on start-up */
+	enum state_terminal_raw term_raw;	/* Terminal raw/cooked */
+
+	/* Pointer to information for each SPI bus/cs */
+	struct sandbox_spi_info spi[CONFIG_SANDBOX_SPI_MAX_BUS]
+					[CONFIG_SANDBOX_SPI_MAX_CS];
 };
 
+/* Minimum space we guarantee in the state FDT when calling read/write*/
+#define SANDBOX_STATE_MIN_SPACE		0x1000
+
+/**
+ * struct sandbox_state_io - methods to saved/restore sandbox state
+ * @name: Name of of the device tree node, also the name of the variable
+ *	holding this data so it should be an identifier (use underscore
+ *	instead of minus)
+ * @compat: Compatible string for the node containing this state
+ *
+ * @read: Function to read state from FDT
+ *	If data is available, then blob and node will provide access to it. If
+ *	not (blob == NULL and node == -1) this function should set up an empty
+ *	data set for start-of-day.
+ *	@param blob: Pointer to device tree blob, or NULL if no data to read
+ *	@param node: Node offset to read from
+ *	@return 0 if OK, -ve on error
+ *
+ * @write: Function to write state to FDT
+ *	The caller will ensure that there is a node ready for the state. The
+ *	node may already contain the old state, in which case it should be
+ *	overridden. There is guaranteed to be SANDBOX_STATE_MIN_SPACE bytes
+ *	of free space, so error checking is not required for fdt_setprop...()
+ *	calls which add up to less than this much space.
+ *
+ *	For adding larger properties, use state_setprop().
+ *
+ * @param blob: Device tree blob holding state
+ * @param node: Node to write our state into
+ *
+ * Note that it is possible to save data as large blobs or as individual
+ * hierarchical properties. However, unless you intend to keep state files
+ * around for a long time and be able to run an old state file on a new
+ * sandbox, it might not be worth using individual properties for everything.
+ * This is certainly supported, it is just a matter of the effort you wish
+ * to put into the state read/write feature.
+ */
+struct sandbox_state_io {
+	const char *name;
+	const char *compat;
+	int (*write)(void *blob, int node);
+	int (*read)(const void *blob, int node);
+};
+
+/**
+ * SANDBOX_STATE_IO - Declare sandbox state to read/write
+ *
+ * Sandbox permits saving state from one run and restoring it in another. This
+ * allows the test system to retain state between runs and thus better
+ * emulate a real system. Examples of state that might be useful to save are
+ * the emulated GPIOs pin settings, flash memory contents and TPM private
+ * data. U-Boot memory contents is dealth with separately since it is large
+ * and it is not normally useful to save it (since a normal system does not
+ * preserve DRAM between runs). See the '-m' option for this.
+ *
+ * See struct sandbox_state_io above for member documentation.
+ */
+#define SANDBOX_STATE_IO(_name, _compat, _read, _write) \
+	ll_entry_declare(struct sandbox_state_io, _name, state_io) = { \
+		.name = __stringify(_name), \
+		.read = _read, \
+		.write = _write, \
+		.compat = _compat, \
+	}
+
 /**
  * Record the exit type to be reported by the test program.
  *
@@ -40,8 +153,59 @@ void state_record_exit(enum exit_type_id exit_type);
 struct sandbox_state *state_get_current(void);
 
 /**
+ * Read the sandbox state from the supplied device tree file
+ *
+ * This calls all registered state handlers to read in the sandbox state
+ * from a previous test run.
+ *
+ * @param state		Sandbox state to update
+ * @param fname		Filename of device tree file to read from
+ * @return 0 if OK, -ve on error
+ */
+int sandbox_read_state(struct sandbox_state *state, const char *fname);
+
+/**
+ * Write the sandbox state to the supplied device tree file
+ *
+ * This calls all registered state handlers to write out the sandbox state
+ * so that it can be preserved for a future test run.
+ *
+ * If the file exists it is overwritten.
+ *
+ * @param state		Sandbox state to update
+ * @param fname		Filename of device tree file to write to
+ * @return 0 if OK, -ve on error
+ */
+int sandbox_write_state(struct sandbox_state *state, const char *fname);
+
+/**
+ * Add a property to a sandbox state node
+ *
+ * This is equivalent to fdt_setprop except that it automatically enlarges
+ * the device tree if necessary. That means it is safe to write any amount
+ * of data here.
+ *
+ * This function can only be called from within struct sandbox_state_io's
+ * ->write method, i.e. within state I/O drivers.
+ *
+ * @param node		Device tree node to write to
+ * @param prop_name	Property to write
+ * @param data		Data to write into property
+ * @param size		Size of data to write into property
+ */
+int state_setprop(int node, const char *prop_name, const void *data, int size);
+
+/**
  * Initialize the test system state
  */
 int state_init(void);
 
+/**
+ * Uninitialize the test system state, writing out state if configured to
+ * do so.
+ *
+ * @return 0 if OK, -ve on error
+ */
+int state_uninit(void);
+
 #endif
diff --git a/arch/sandbox/include/asm/types.h b/arch/sandbox/include/asm/types.h
index 88c84bae7c..6d3eb1f3de 100644
--- a/arch/sandbox/include/asm/types.h
+++ b/arch/sandbox/include/asm/types.h
@@ -48,8 +48,8 @@ typedef unsigned long long u64;
 #define BITS_PER_LONG	CONFIG_SANDBOX_BITS_PER_LONG
 
 typedef unsigned long dma_addr_t;
-typedef unsigned long phys_addr_t;
-typedef unsigned long phys_size_t;
+typedef u32 phys_addr_t;
+typedef u32 phys_size_t;
 
 #endif /* __KERNEL__ */
 
diff --git a/arch/sandbox/include/asm/u-boot-sandbox.h b/arch/sandbox/include/asm/u-boot-sandbox.h
index bed720cf81..d2f1b6566d 100644
--- a/arch/sandbox/include/asm/u-boot-sandbox.h
+++ b/arch/sandbox/include/asm/u-boot-sandbox.h
@@ -23,4 +23,9 @@ int dram_init(void);
 int sandbox_early_getopt_check(void);
 int sandbox_main_loop_init(void);
 
+int cleanup_before_linux(void);
+
+/* drivers/video/sandbox_sdl.c */
+int sandbox_lcd_sdl_early_init(void);
+
 #endif	/* _U_BOOT_SANDBOX_H_ */
diff --git a/arch/sandbox/lib/Makefile b/arch/sandbox/lib/Makefile
index 993fb4e06b..4c1a38d6bc 100644
--- a/arch/sandbox/lib/Makefile
+++ b/arch/sandbox/lib/Makefile
@@ -7,28 +7,5 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
 
-LIB	= $(obj)lib$(ARCH).o
-
-COBJS-y	+= interrupts.o
-
-SRCS	:= $(COBJS-y:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS-y))
-
-# Always build libsandbox.o
-TARGETS	:= $(LIB)
-
-all:	$(TARGETS)
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	+= interrupts.o
diff --git a/arch/sh/config.mk b/arch/sh/config.mk
index 758c0701e5..0578fa3fd8 100644
--- a/arch/sh/config.mk
+++ b/arch/sh/config.mk
@@ -5,7 +5,9 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-CROSS_COMPILE ?= sh4-linux-
+ifeq ($(CROSS_COMPILE),)
+CROSS_COMPILE := sh4-linux-
+endif
 
 CONFIG_STANDALONE_LOAD_ADDR ?= 0x8C000000
 ifeq ($(CPU),sh2)
@@ -15,3 +17,4 @@ endif
 PLATFORM_CPPFLAGS += -DCONFIG_SH -D__SH__
 PLATFORM_LDFLAGS += -e $(CONFIG_SYS_TEXT_BASE) --defsym reloc_dst=$(CONFIG_SYS_TEXT_BASE)
 LDFLAGS_FINAL = --gc-sections
+PLATFORM_RELFLAGS += -ffixed-r13
diff --git a/arch/sh/cpu/sh2/Makefile b/arch/sh/cpu/sh2/Makefile
index 1cc00313e9..a19ed5ecf5 100644
--- a/arch/sh/cpu/sh2/Makefile
+++ b/arch/sh/cpu/sh2/Makefile
@@ -8,25 +8,5 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(CPU).o
-
-SOBJS	= start.o
-COBJS	= cpu.o interrupts.o watchdog.o
-
-SRCS    := $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS    := $(addprefix $(obj),$(COBJS))
-SOBJS   := $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(OBJS) $(SOBJS)
-	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+extra-y	= start.o
+obj-y	= cpu.o interrupts.o watchdog.o
diff --git a/arch/sh/cpu/sh2/config.mk b/arch/sh/cpu/sh2/config.mk
index 8a0de96714..4904d76d44 100644
--- a/arch/sh/cpu/sh2/config.mk
+++ b/arch/sh/cpu/sh2/config.mk
@@ -8,11 +8,10 @@
 ENDIANNESS += -EB
 
 ifdef CONFIG_SH2A
-PLATFORM_CPPFLAGS += -m2a -m2a-nofpu -mb -ffreestanding
+PLATFORM_CPPFLAGS += -m2a -m2a-nofpu -mb
 else # SH2
 PLATFORM_CPPFLAGS += -m3e -mb
 endif
-PLATFORM_CPPFLAGS += $(call cc-option,-mno-fdpic)
+PLATFORM_CPPFLAGS += -DCONFIG_SH2 $(call cc-option,-mno-fdpic)
 
-PLATFORM_RELFLAGS += -ffixed-r13
 PLATFORM_LDFLAGS += $(ENDIANNESS)
diff --git a/arch/sh/cpu/sh2/cpu.c b/arch/sh/cpu/sh2/cpu.c
index 18479a4c40..a2f856f459 100644
--- a/arch/sh/cpu/sh2/cpu.c
+++ b/arch/sh/cpu/sh2/cpu.c
@@ -23,11 +23,7 @@
 
 int checkcpu(void)
 {
-#if defined(CONFIG_SH2A)
-	puts("CPU: SH2A\n");
-#else
 	puts("CPU: SH2\n");
-#endif
 	return 0;
 }
 
diff --git a/arch/sh/cpu/sh3/Makefile b/arch/sh/cpu/sh3/Makefile
index e707de3f89..1dccaf9520 100644
--- a/arch/sh/cpu/sh3/Makefile
+++ b/arch/sh/cpu/sh3/Makefile
@@ -11,25 +11,5 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(CPU).o
-
-SOBJS	= start.o
-COBJS	= cpu.o interrupts.o watchdog.o cache.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(OBJS) $(SOBJS)
-	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+extra-y	= start.o
+obj-y	= cpu.o interrupts.o watchdog.o cache.o
diff --git a/arch/sh/cpu/sh3/config.mk b/arch/sh/cpu/sh3/config.mk
index 5c77e5c32d..24b5c47859 100644
--- a/arch/sh/cpu/sh3/config.mk
+++ b/arch/sh/cpu/sh3/config.mk
@@ -11,5 +11,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 #
-PLATFORM_CPPFLAGS += -m3
-PLATFORM_RELFLAGS += -ffixed-r13
+PLATFORM_CPPFLAGS += -DCONFIG_SH3 -m3
diff --git a/arch/sh/cpu/sh4/Makefile b/arch/sh/cpu/sh4/Makefile
index e7d8903814..38c6188c38 100644
--- a/arch/sh/cpu/sh4/Makefile
+++ b/arch/sh/cpu/sh4/Makefile
@@ -8,25 +8,5 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(CPU).o
-
-SOBJS	= start.o
-COBJS	= cpu.o interrupts.o watchdog.o cache.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(OBJS) $(SOBJS)
-	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+extra-y	= start.o
+obj-y	= cpu.o interrupts.o watchdog.o cache.o
diff --git a/arch/sh/cpu/sh4/cache.c b/arch/sh/cpu/sh4/cache.c
index 1947ec8e95..e1ee970a91 100644
--- a/arch/sh/cpu/sh4/cache.c
+++ b/arch/sh/cpu/sh4/cache.c
@@ -91,7 +91,7 @@ int cache_control(unsigned int cmd)
 	return 0;
 }
 
-void dcache_wback_range(u32 start, u32 end)
+void flush_dcache_range(unsigned long start, unsigned long end)
 {
 	u32 v;
 
@@ -102,7 +102,7 @@ void dcache_wback_range(u32 start, u32 end)
 	}
 }
 
-void dcache_invalid_range(u32 start, u32 end)
+void invalidate_dcache_range(unsigned long start, unsigned long end)
 {
 	u32 v;
 
diff --git a/arch/sh/cpu/sh4/config.mk b/arch/sh/cpu/sh4/config.mk
index c3575570e7..5773d4fec9 100644
--- a/arch/sh/cpu/sh4/config.mk
+++ b/arch/sh/cpu/sh4/config.mk
@@ -8,5 +8,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 #
-PLATFORM_CPPFLAGS += -m4-nofpu
-PLATFORM_RELFLAGS += -ffixed-r13
+PLATFORM_CPPFLAGS += -DCONFIG_SH4 -m4-nofpu
diff --git a/arch/sh/cpu/sh4/cpu.c b/arch/sh/cpu/sh4/cpu.c
index 9fae61473b..e8ee0a45ab 100644
--- a/arch/sh/cpu/sh4/cpu.c
+++ b/arch/sh/cpu/sh4/cpu.c
@@ -13,11 +13,7 @@
 
 int checkcpu(void)
 {
-#ifdef CONFIG_SH4A
-	puts("CPU: SH-4A\n");
-#else
 	puts("CPU: SH4\n");
-#endif
 	return 0;
 }
 
@@ -41,7 +37,7 @@ int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 
 void flush_cache (unsigned long addr, unsigned long size)
 {
-	dcache_invalid_range( addr , addr + size );
+	invalidate_dcache_range(addr , addr + size);
 }
 
 void icache_enable (void)
diff --git a/arch/sh/include/asm/cache.h b/arch/sh/include/asm/cache.h
index 24941b3019..0698a37759 100644
--- a/arch/sh/include/asm/cache.h
+++ b/arch/sh/include/asm/cache.h
@@ -1,7 +1,7 @@
 #ifndef __ASM_SH_CACHE_H
 #define __ASM_SH_CACHE_H
 
-#if defined(CONFIG_SH4) || defined(CONFIG_SH4A)
+#if defined(CONFIG_SH4)
 
 int cache_control(unsigned int cmd);
 
@@ -10,9 +10,6 @@ int cache_control(unsigned int cmd);
 struct __large_struct { unsigned long buf[100]; };
 #define __m(x) (*(struct __large_struct *)(x))
 
-void dcache_wback_range(u32 start, u32 end);
-void dcache_invalid_range(u32 start, u32 end);
-
 #else
 
 /*
@@ -21,7 +18,7 @@ void dcache_invalid_range(u32 start, u32 end);
  */
 #define ARCH_DMA_MINALIGN	32
 
-#endif /* CONFIG_SH4 || CONFIG_SH4A */
+#endif /* CONFIG_SH4 */
 
 /*
  * Use the L1 data cache line size value for the minimum DMA buffer alignment
diff --git a/arch/sh/include/asm/cpu_sh4.h b/arch/sh/include/asm/cpu_sh4.h
index 9181d59a94..9f48e4fe04 100644
--- a/arch/sh/include/asm/cpu_sh4.h
+++ b/arch/sh/include/asm/cpu_sh4.h
@@ -37,6 +37,8 @@
 # include <asm/cpu_sh7734.h>
 #elif defined (CONFIG_CPU_SH7752)
 # include <asm/cpu_sh7752.h>
+#elif defined (CONFIG_CPU_SH7753)
+# include <asm/cpu_sh7753.h>
 #elif defined (CONFIG_CPU_SH7757)
 # include <asm/cpu_sh7757.h>
 #elif defined (CONFIG_CPU_SH7763)
diff --git a/arch/sh/include/asm/cpu_sh7722.h b/arch/sh/include/asm/cpu_sh7722.h
index 7be37ae984..bf57e18a64 100644
--- a/arch/sh/include/asm/cpu_sh7722.h
+++ b/arch/sh/include/asm/cpu_sh7722.h
@@ -1250,8 +1250,9 @@
 #define PUDR        0xA4050162
 #define PVDR        0xA4050164
 #define PWDR        0xA4050166
-#define PYDR        0xA4050168
-#define PZDR        0xA405016A
+#define PXDR        0xA4050168
+#define PYDR        0xA405016A
+#define PZDR        0xA405016C
 
 /*	UBC	*/
 #define CBR0        0xFF200000
diff --git a/arch/sh/include/asm/cpu_sh7723.h b/arch/sh/include/asm/cpu_sh7723.h
index 3af0b0db2f..9d8cb8db44 100644
--- a/arch/sh/include/asm/cpu_sh7723.h
+++ b/arch/sh/include/asm/cpu_sh7723.h
@@ -178,8 +178,9 @@
 #define PUDR        0xA4050162
 #define PVDR        0xA4050164
 #define PWDR        0xA4050166
-#define PYDR        0xA4050168
-#define PZDR        0xA405016A
+#define PXDR        0xA4050168
+#define PYDR        0xA405016A
+#define PZDR        0xA405016C
 
 /* UBC */
 /* H-UDI */
diff --git a/arch/sh/include/asm/cpu_sh7724.h b/arch/sh/include/asm/cpu_sh7724.h
index 2c2a474d37..88c418a17f 100644
--- a/arch/sh/include/asm/cpu_sh7724.h
+++ b/arch/sh/include/asm/cpu_sh7724.h
@@ -200,8 +200,9 @@
 #define PUDR        0xA4050162
 #define PVDR        0xA4050164
 #define PWDR        0xA4050166
-#define PYDR        0xA4050168
-#define PZDR        0xA405016A
+#define PXDR        0xA4050168
+#define PYDR        0xA405016A
+#define PZDR        0xA405016C
 
 /* Ether */
 #define EDMR		0xA4600000
diff --git a/arch/sh/include/asm/cpu_sh7753.h b/arch/sh/include/asm/cpu_sh7753.h
new file mode 100644
index 0000000000..cd0e0bba6c
--- /dev/null
+++ b/arch/sh/include/asm/cpu_sh7753.h
@@ -0,0 +1,197 @@
+/*
+ * Copyright (C) 2012  Renesas Solutions Corp.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _ASM_CPU_SH7753_H_
+#define _ASM_CPU_SH7753_H_
+
+#define CCR		0xFF00001C
+#define WTCNT		0xFFCC0000
+#define CCR_CACHE_INIT	0x0000090b
+#define CACHE_OC_NUM_WAYS	1
+
+#ifndef __ASSEMBLY__		/* put C only stuff in this section */
+/* MMU */
+struct mmu_regs {
+	unsigned int	reserved[4];
+	unsigned int	mmucr;
+};
+#define MMU_BASE	((struct mmu_regs *)0xff000000)
+
+/* Watchdog */
+#define WTCSR0		0xffcc0002
+#define WRSTCSR_R	0xffcc0003
+#define WRSTCSR_W	0xffcc0002
+#define WTCSR_PREFIX		0xa500
+#define WRSTCSR_PREFIX		0x6900
+#define WRSTCSR_WOVF_PREFIX	0x9600
+
+/* SCIF */
+#define SCIF0_BASE	0xfe4b0000	/* The real name is SCIF2 */
+#define SCIF1_BASE	0xfe4c0000	/* The real name is SCIF3 */
+#define SCIF2_BASE	0xfe4d0000	/* The real name is SCIF4 */
+
+/* TMU0 */
+#define TMU_BASE	 0xFE430000
+
+/* ETHER, GETHER MAC address */
+struct ether_mac_regs {
+	unsigned int	reserved[114];
+	unsigned int	mahr;
+	unsigned int	reserved2;
+	unsigned int	malr;
+};
+#define GETHER0_MAC_BASE	((struct ether_mac_regs *)0xfee0400)
+#define GETHER1_MAC_BASE	((struct ether_mac_regs *)0xfee0c00)
+#define ETHER0_MAC_BASE		((struct ether_mac_regs *)0xfef0000)
+#define ETHER1_MAC_BASE		((struct ether_mac_regs *)0xfef0800)
+
+/* GETHER */
+struct gether_control_regs {
+	unsigned int	gbecont;
+};
+#define GETHER_CONTROL_BASE	((struct gether_control_regs *)0xffc10100)
+#define GBECONT_RMII1		0x00020000
+#define GBECONT_RMII0		0x00010000
+
+/* SerMux */
+struct sermux_regs {
+	unsigned char	smr0;
+	unsigned char	smr1;
+	unsigned char	smr2;
+	unsigned char	smr3;
+	unsigned char	smr4;
+	unsigned char	smr5;
+};
+#define SERMUX_BASE	((struct sermux_regs *)0xfe470000)
+
+
+/* USB0/1 */
+struct usb_common_regs {
+	unsigned short	reserved[129];
+	unsigned short	suspmode;
+};
+#define USB0_COMMON_BASE	((struct usb_common_regs *)0xfe450000)
+#define USB1_COMMON_BASE	((struct usb_common_regs *)0xfe4f0000)
+
+struct usb0_phy_regs {
+	unsigned short	reset;
+	unsigned short	reserved[4];
+	unsigned short	portsel;
+};
+#define USB0_PHY_BASE		((struct usb0_phy_regs *)0xfe5f0000)
+
+struct usb1_port_regs {
+	unsigned int	port1sel;
+	unsigned int	reserved;
+	unsigned int	usb1intsts;
+};
+#define USB1_PORT_BASE		((struct usb1_port_regs *)0xfe4f2000)
+
+struct usb1_alignment_regs {
+	unsigned int	ehcidatac;	/* 0xfe4fe018 */
+	unsigned int	reserved[63];
+	unsigned int	ohcidatac;
+};
+#define USB1_ALIGNMENT_BASE	((struct usb1_alignment_regs *)0xfe4fe018)
+
+/* GPIO */
+struct gpio_regs {
+	unsigned short	pacr;
+	unsigned short	pbcr;
+	unsigned short	pccr;
+	unsigned short	pdcr;
+	unsigned short	pecr;
+	unsigned short	pfcr;
+	unsigned short	pgcr;
+	unsigned short	phcr;
+	unsigned short	picr;
+	unsigned short	pjcr;
+	unsigned short	pkcr;
+	unsigned short	plcr;
+	unsigned short	pmcr;
+	unsigned short	pncr;
+	unsigned short	pocr;
+	unsigned short	reserved;
+	unsigned short	pqcr;
+	unsigned short	prcr;
+	unsigned short	pscr;
+	unsigned short	ptcr;
+	unsigned short	pucr;
+	unsigned short	pvcr;
+	unsigned short	pwcr;
+	unsigned short	pxcr;
+	unsigned short	pycr;
+	unsigned short	pzcr;
+	unsigned char	padr;
+	unsigned char	reserved_a;
+	unsigned char	pbdr;
+	unsigned char	reserved_b;
+	unsigned char	pcdr;
+	unsigned char	reserved_c;
+	unsigned char	pddr;
+	unsigned char	reserved_d;
+	unsigned char	pedr;
+	unsigned char	reserved_e;
+	unsigned char	pfdr;
+	unsigned char	reserved_f;
+	unsigned char	pgdr;
+	unsigned char	reserved_g;
+	unsigned char	phdr;
+	unsigned char	reserved_h;
+	unsigned char	pidr;
+	unsigned char	reserved_i;
+	unsigned char	pjdr;
+	unsigned char	reserved_j;
+	unsigned char	pkdr;
+	unsigned char	reserved_k;
+	unsigned char	pldr;
+	unsigned char	reserved_l;
+	unsigned char	pmdr;
+	unsigned char	reserved_m;
+	unsigned char	pndr;
+	unsigned char	reserved_n;
+	unsigned char	podr;
+	unsigned char	reserved_o;
+	unsigned char	ppdr;
+	unsigned char	reserved_p;
+	unsigned char	pqdr;
+	unsigned char	reserved_q;
+	unsigned char	prdr;
+	unsigned char	reserved_r;
+	unsigned char	psdr;
+	unsigned char	reserved_s;
+	unsigned char	ptdr;
+	unsigned char	reserved_t;
+	unsigned char	pudr;
+	unsigned char	reserved_u;
+	unsigned char	pvdr;
+	unsigned char	reserved_v;
+	unsigned char	pwdr;
+	unsigned char	reserved_w;
+	unsigned char	pxdr;
+	unsigned char	reserved_x;
+	unsigned char	pydr;
+	unsigned char	reserved_y;
+	unsigned char	pzdr;
+	unsigned char	reserved_z;
+	unsigned short	ncer;
+	unsigned short	ncmcr;
+	unsigned short	nccsr;
+	unsigned char	reserved2[2];
+	unsigned short	psel0;		/* +0x70 */
+	unsigned short	psel1;
+	unsigned short	psel2;
+	unsigned short	psel3;
+	unsigned short	psel4;
+	unsigned short	psel5;
+	unsigned short	psel6;
+	unsigned short	reserved3[2];
+	unsigned short	psel7;
+};
+#define GPIO_BASE	((struct gpio_regs *)0xffec0000)
+
+#endif	/* ifndef __ASSEMBLY__ */
+#endif	/* _ASM_CPU_SH7753_H_ */
diff --git a/arch/sh/include/asm/processor.h b/arch/sh/include/asm/processor.h
index 938a89cff5..b8677da959 100644
--- a/arch/sh/include/asm/processor.h
+++ b/arch/sh/include/asm/processor.h
@@ -1,12 +1,10 @@
 #ifndef _ASM_SH_PROCESSOR_H_
 #define _ASM_SH_PROCESSOR_H_
-#if defined(CONFIG_SH2) || \
-	defined (CONFIG_SH2A)
+#if defined(CONFIG_SH2)
 # include <asm/cpu_sh2.h>
-#elif defined (CONFIG_SH3)
+#elif defined(CONFIG_SH3)
 # include <asm/cpu_sh3.h>
-#elif defined (CONFIG_SH4) || \
-	defined (CONFIG_SH4A)
+#elif defined(CONFIG_SH4)
 # include <asm/cpu_sh4.h>
 #endif
 #endif
diff --git a/arch/sh/lib/Makefile b/arch/sh/lib/Makefile
index 8165963ee8..8a84b24af1 100644
--- a/arch/sh/lib/Makefile
+++ b/arch/sh/lib/Makefile
@@ -5,57 +5,15 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
 
-LIB	= $(obj)lib$(ARCH).o
-LIBGCC	= $(obj)libgcc.o
-
-SOBJS-y	+=
-GLSOBJS	+= ashiftrt.o
-GLSOBJS	+= ashiftlt.o
-GLSOBJS	+= lshiftrt.o
-GLSOBJS	+= ashldi3.o
-GLSOBJS	+= ashrsi3.o
-GLSOBJS	+= lshrdi3.o
-GLSOBJS	+= movmem.o
-
-COBJS-y	+= board.o
-COBJS-$(CONFIG_CMD_BOOTM) += bootm.o
+obj-y	+= board.o
+obj-$(CONFIG_CMD_BOOTM) += bootm.o
 ifeq ($(CONFIG_SH2),y)
-COBJS-y	+= time_sh2.o
+obj-y	+= time_sh2.o
 else
-COBJS-y	+= time.o
-endif
-ifeq ($(CONFIG_CMD_SH_ZIMAGEBOOT),y)
-COBJS-y += zimageboot.o
-endif
-
-SRCS	:= $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
-OBJS	:= $(addprefix $(obj),$(SOBJS-y) $(COBJS-y))
-LGOBJS	:= $(addprefix $(obj),$(GLSOBJS)) \
-	   $(addprefix $(obj),$(GLCOBJS))
-
-# Always build libsh.o
-TARGETS	:= $(LIB)
-
-# Build private libgcc only when asked for
-ifdef USE_PRIVATE_LIBGCC
-TARGETS	+= $(LIBGCC)
+obj-y	+= time.o
 endif
+obj-$(CONFIG_CMD_SH_ZIMAGEBOOT) += zimageboot.o
 
-all:	$(TARGETS)
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-$(LIBGCC): $(obj).depend $(LGOBJS)
-	$(call cmd_link_o_target, $(LGOBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+lib-$(CONFIG_USE_PRIVATE_LIBGCC) += ashiftrt.o ashiftlt.o lshiftrt.o \
+				    ashldi3.o ashrsi3.o lshrdi3.o movmem.o
diff --git a/arch/sh/lib/time.c b/arch/sh/lib/time.c
index 1fe537e83b..d970a1e4f0 100644
--- a/arch/sh/lib/time.c
+++ b/arch/sh/lib/time.c
@@ -12,36 +12,23 @@
  */
 
 #include <common.h>
-#include <div64.h>
 #include <asm/processor.h>
 #include <asm/io.h>
 #include <sh_tmu.h>
 
-static struct tmu_regs *tmu = (struct tmu_regs *)TMU_BASE;
+#define TCR_TPSC 0x07
 
-static u16 bit;
-static unsigned long last_tcnt;
-static unsigned long long overflow_ticks;
+static struct tmu_regs *tmu = (struct tmu_regs *)TMU_BASE;
 
 unsigned long get_tbclk(void)
 {
-	return get_tmu0_clk_rate() >> ((bit + 1) * 2);
+	u16 tmu_bit = (ffs(CONFIG_SYS_TMU_CLK_DIV) >> 1) - 1;
+	return get_tmu0_clk_rate() >> ((tmu_bit + 1) * 2);
 }
 
-static inline unsigned long long tick_to_time(unsigned long long tick)
+unsigned long timer_read_counter(void)
 {
-	tick *= CONFIG_SYS_HZ;
-	do_div(tick, get_tbclk());
-
-	return tick;
-}
-
-static inline unsigned long long usec_to_tick(unsigned long long usec)
-{
-	usec *= get_tbclk();
-	do_div(usec, 1000000);
-
-	return usec;
+	return ~readl(&tmu->tcnt0);
 }
 
 static void tmu_timer_start(unsigned int timer)
@@ -60,55 +47,12 @@ static void tmu_timer_stop(unsigned int timer)
 
 int timer_init(void)
 {
-	bit = (ffs(CONFIG_SYS_TMU_CLK_DIV) >> 1) - 1;
-	writew(readw(&tmu->tcr0) | bit, &tmu->tcr0);
+	u16 tmu_bit = (ffs(CONFIG_SYS_TMU_CLK_DIV) >> 1) - 1;
+	writew((readw(&tmu->tcr0) & ~TCR_TPSC) | tmu_bit, &tmu->tcr0);
 
 	tmu_timer_stop(0);
 	tmu_timer_start(0);
 
-	last_tcnt = 0;
-	overflow_ticks = 0;
-
 	return 0;
 }
 
-unsigned long long get_ticks(void)
-{
-	unsigned long tcnt = 0 - readl(&tmu->tcnt0);
-
-	if (last_tcnt > tcnt) /* overflow */
-		overflow_ticks++;
-	last_tcnt = tcnt;
-
-	return (overflow_ticks << 32) | tcnt;
-}
-
-void __udelay(unsigned long usec)
-{
-	unsigned long long tmp;
-	ulong tmo;
-
-	tmo = usec_to_tick(usec);
-	tmp = get_ticks() + tmo;	/* get current timestamp */
-
-	while (get_ticks() < tmp)	/* loop till event */
-		 /*NOP*/;
-}
-
-unsigned long get_timer(unsigned long base)
-{
-	/* return msec */
-	return tick_to_time(get_ticks()) - base;
-}
-
-void set_timer(unsigned long t)
-{
-	writel((0 - t), &tmu->tcnt0);
-}
-
-void reset_timer(void)
-{
-	tmu_timer_stop(0);
-	set_timer(0);
-	tmu_timer_start(0);
-}
diff --git a/arch/sh/lib/time_sh2.c b/arch/sh/lib/time_sh2.c
index be3896c3ed..4b1f47b6ad 100644
--- a/arch/sh/lib/time_sh2.c
+++ b/arch/sh/lib/time_sh2.c
@@ -84,5 +84,5 @@ void __udelay(unsigned long usec)
 
 unsigned long get_tbclk(void)
 {
-	return CONFIG_SYS_HZ;
+	return CONFIG_SH_CMT_CLK_FREQ;
 }
diff --git a/arch/sparc/config.mk b/arch/sparc/config.mk
index e94e7cbab5..be59f58190 100644
--- a/arch/sparc/config.mk
+++ b/arch/sparc/config.mk
@@ -5,8 +5,13 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-CROSS_COMPILE ?= sparc-elf-
+ifeq ($(CROSS_COMPILE),)
+CROSS_COMPILE := sparc-elf-
+endif
 
-CONFIG_STANDALONE_LOAD_ADDR ?= 0x00000000 -L $(gcclibdir) -T sparc.lds
+gcclibdir := $(shell dirname `$(CC) -print-libgcc-file-name`)
+
+CONFIG_STANDALONE_LOAD_ADDR ?= 0x00000000 -L $(gcclibdir) \
+			       -T $(srctree)/examples/standalone/sparc.lds
 
 PLATFORM_CPPFLAGS += -DCONFIG_SPARC -D__sparc__
diff --git a/arch/sparc/cpu/leon2/Makefile b/arch/sparc/cpu/leon2/Makefile
index f43d3d2cd3..8c95ca5670 100644
--- a/arch/sparc/cpu/leon2/Makefile
+++ b/arch/sparc/cpu/leon2/Makefile
@@ -5,28 +5,5 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(CPU).o
-
-START	= start.o
-SOBJS	=
-COBJS	= cpu_init.o serial.o cpu.o interrupts.o prom.o
-
-SRCS	:= $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS))
-START	:= $(addprefix $(obj),$(START))
-
-all:	$(obj).depend $(START) $(LIB)
-
-$(LIB):	$(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+extra-y	= start.o
+obj-y	= cpu_init.o serial.o cpu.o interrupts.o prom.o
diff --git a/arch/sparc/cpu/leon3/Makefile b/arch/sparc/cpu/leon3/Makefile
index 95bbfc9bac..4f13ec3071 100644
--- a/arch/sparc/cpu/leon3/Makefile
+++ b/arch/sparc/cpu/leon3/Makefile
@@ -5,28 +5,5 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(CPU).o
-
-START	= start.o
-SOBJS	=
-COBJS	= cpu_init.o serial.o cpu.o ambapp.o interrupts.o prom.o usb_uhci.o
-
-SRCS	:= $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS))
-START	:= $(addprefix $(obj),$(START))
-
-all:	$(obj).depend $(START) $(LIB)
-
-$(LIB):	$(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+extra-y	= start.o
+obj-y	= cpu_init.o serial.o cpu.o ambapp.o interrupts.o prom.o usb_uhci.o
diff --git a/arch/sparc/cpu/leon3/start.S b/arch/sparc/cpu/leon3/start.S
index 70aee78054..cf897f6877 100644
--- a/arch/sparc/cpu/leon3/start.S
+++ b/arch/sparc/cpu/leon3/start.S
@@ -1,31 +1,41 @@
-TRAP ta 0; nop; nop; nop;
-
-/* Software trap. Treat as BAD_TRAP for the time being... */
-#define SOFT_TRAP TRAP(_hwerr)
-
-#define PSR_INIT   0x1FC0	/* Disable traps, set s and ps */
-#define WIM_INIT   2
-
-/* All traps low-level code here must end with this macro. */
-#define RESTORE_ALL b ret_trap_entry; clr %l6;
-
-#define WRITE_PAUSE nop;nop;nop
-
-WINDOWSIZE = (16 * 4)
-ARGPUSHSIZE = (6 * 4)
-ARGPUSH = (WINDOWSIZE + 4)
-MINFRAME = (WINDOWSIZE + ARGPUSHSIZE + 4)
-
-/* Number of register windows */
-#ifndef CONFIG_SYS_SPARC_NWINDOWS
-#error Must define number of SPARC register windows, default is 8
-#endif
-
-#define STACK_ALIGN	8
-#define SA(X)	(((X)+(STACK_ALIGN-1)) & ~(STACK_ALIGN-1))
+/* This is where the SPARC/LEON3 starts
+ * Copyright (C) 2007,
+ * Daniel Hellstrom, daniel@gaisler.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
 
-	.section ".start", "ax"
-	.globl	_starttate */
+#include <asm-offsets.h>
+#include <config.h>
+#include <asm/asmmacro.h>
+#include <asm/winmacro.h>
+#include <asm/psr.h>
+#include <asm/stack.h>
+#include <asm/leon.h>
+#include <version.h>
+
+/* Entry for traps which jump to a programmer-specified trap handler.  */
+#define TRAPR(H)  \
+	wr	%g0, 0xfe0, %psr; \
+	mov	%g0, %tbr; \
+	ba	(H); \
+	mov	%g0, %wim;
+
+#define TRAP(H) \
+	mov	%psr, %l0; \
+	ba	(H); \
+	nop; nop;
+
+#define TRAPI(ilevel) \
+	mov	ilevel, %l7; \
+	mov	%psr, %l0; \
+	b	_irq_entry; \
+	mov	%wim, %l3
+
+/* Unexcpected trap will halt the processor by forcing it to error state */
 #undef BAD_TRAP
 #define BAD_TRAP ta 0; nop; nop; nop;
 
diff --git a/arch/sparc/cpu/leon3/usb_uhci.c b/arch/sparc/cpu/leon3/usb_uhci.c
index 5de48c11c2..ca7d6e86f0 100644
--- a/arch/sparc/cpu/leon3/usb_uhci.c
+++ b/arch/sparc/cpu/leon3/usb_uhci.c
@@ -688,7 +688,7 @@ void handle_usb_interrupt(void)
 
 /* init uhci
  */
-int usb_lowlevel_init(int index, void **controller)
+int usb_lowlevel_init(int index, enum usb_init_type init, void **controller)
 {
 	unsigned char temp;
 	ambapp_ahbdev ahbdev;
@@ -757,110 +757,9 @@ static void usb_display_Req(unsigned short req)
 }
 #endif
 
-static unsigned char root_hub_dev_des[] = {
-	0x12,			/*  __u8  bLength; */
-	0x01,			/*  __u8  bDescriptorType; Device */
-	0x00,			/*  __u16 bcdUSB; v1.0 */
-	0x01,
-	0x09,			/*  __u8  bDeviceClass; HUB_CLASSCODE */
-	0x00,			/*  __u8  bDeviceSubClass; */
-	0x00,			/*  __u8  bDeviceProtocol; */
-	0x08,			/*  __u8  bMaxPacketSize0; 8 Bytes */
-	0x00,			/*  __u16 idVendor; */
-	0x00,
-	0x00,			/*  __u16 idProduct; */
-	0x00,
-	0x00,			/*  __u16 bcdDevice; */
-	0x00,
-	0x01,			/*  __u8  iManufacturer; */
-	0x00,			/*  __u8  iProduct; */
-	0x00,			/*  __u8  iSerialNumber; */
-	0x01			/*  __u8  bNumConfigurations; */
-};
-
-/* Configuration descriptor */
-static unsigned char root_hub_config_des[] = {
-	0x09,			/*  __u8  bLength; */
-	0x02,			/*  __u8  bDescriptorType; Configuration */
-	0x19,			/*  __u16 wTotalLength; */
-	0x00,
-	0x01,			/*  __u8  bNumInterfaces; */
-	0x01,			/*  __u8  bConfigurationValue; */
-	0x00,			/*  __u8  iConfiguration; */
-	0x40,			/*  __u8  bmAttributes;
-				   Bit 7: Bus-powered, 6: Self-powered, 5 Remote-wakwup, 4..0: resvd */
-	0x00,			/*  __u8  MaxPower; */
-
-	/* interface */
-	0x09,			/*  __u8  if_bLength; */
-	0x04,			/*  __u8  if_bDescriptorType; Interface */
-	0x00,			/*  __u8  if_bInterfaceNumber; */
-	0x00,			/*  __u8  if_bAlternateSetting; */
-	0x01,			/*  __u8  if_bNumEndpoints; */
-	0x09,			/*  __u8  if_bInterfaceClass; HUB_CLASSCODE */
-	0x00,			/*  __u8  if_bInterfaceSubClass; */
-	0x00,			/*  __u8  if_bInterfaceProtocol; */
-	0x00,			/*  __u8  if_iInterface; */
-
-	/* endpoint */
-	0x07,			/*  __u8  ep_bLength; */
-	0x05,			/*  __u8  ep_bDescriptorType; Endpoint */
-	0x81,			/*  __u8  ep_bEndpointAddress; IN Endpoint 1 */
-	0x03,			/*  __u8  ep_bmAttributes; Interrupt */
-	0x08,			/*  __u16 ep_wMaxPacketSize; 8 Bytes */
-	0x00,
-	0xff			/*  __u8  ep_bInterval; 255 ms */
-};
-
-static unsigned char root_hub_hub_des[] = {
-	0x09,			/*  __u8  bLength; */
-	0x29,			/*  __u8  bDescriptorType; Hub-descriptor */
-	0x02,			/*  __u8  bNbrPorts; */
-	0x00,			/* __u16  wHubCharacteristics; */
-	0x00,
-	0x01,			/*  __u8  bPwrOn2pwrGood; 2ms */
-	0x00,			/*  __u8  bHubContrCurrent; 0 mA */
-	0x00,			/*  __u8  DeviceRemovable; *** 7 Ports max *** */
-	0xff			/*  __u8  PortPwrCtrlMask; *** 7 ports max *** */
-};
-
-static unsigned char root_hub_str_index0[] = {
-	0x04,			/*  __u8  bLength; */
-	0x03,			/*  __u8  bDescriptorType; String-descriptor */
-	0x09,			/*  __u8  lang ID */
-	0x04,			/*  __u8  lang ID */
-};
-
-static unsigned char root_hub_str_index1[] = {
-	28,			/*  __u8  bLength; */
-	0x03,			/*  __u8  bDescriptorType; String-descriptor */
-	'U',			/*  __u8  Unicode */
-	0,			/*  __u8  Unicode */
-	'H',			/*  __u8  Unicode */
-	0,			/*  __u8  Unicode */
-	'C',			/*  __u8  Unicode */
-	0,			/*  __u8  Unicode */
-	'I',			/*  __u8  Unicode */
-	0,			/*  __u8  Unicode */
-	' ',			/*  __u8  Unicode */
-	0,			/*  __u8  Unicode */
-	'R',			/*  __u8  Unicode */
-	0,			/*  __u8  Unicode */
-	'o',			/*  __u8  Unicode */
-	0,			/*  __u8  Unicode */
-	'o',			/*  __u8  Unicode */
-	0,			/*  __u8  Unicode */
-	't',			/*  __u8  Unicode */
-	0,			/*  __u8  Unicode */
-	' ',			/*  __u8  Unicode */
-	0,			/*  __u8  Unicode */
-	'H',			/*  __u8  Unicode */
-	0,			/*  __u8  Unicode */
-	'u',			/*  __u8  Unicode */
-	0,			/*  __u8  Unicode */
-	'b',			/*  __u8  Unicode */
-	0,			/*  __u8  Unicode */
-};
+#define WANT_USB_ROOT_HUB_HUB_DES
+#include <usbroothubdes.h>
+#undef WANT_USB_ROOT_HUB_HUB_DES
 
 /*
  * Root Hub Control Pipe (interrupt Pipes are not supported)
diff --git a/arch/sparc/include/asm/cache.h b/arch/sparc/include/asm/cache.h
index 8ee0976659..d9671d1c74 100644
--- a/arch/sparc/include/asm/cache.h
+++ b/arch/sparc/include/asm/cache.h
@@ -8,7 +8,6 @@
 #ifndef __SPARC_CACHE_H__
 #define __SPARC_CACHE_H__
 
-#include <linux/config.h>
 #include <asm/processor.h>
 
 /*
diff --git a/arch/sparc/include/asm/page.h b/arch/sparc/include/asm/page.h
index ecc0dc5657..181d1c1952 100644
--- a/arch/sparc/include/asm/page.h
+++ b/arch/sparc/include/asm/page.h
@@ -10,7 +10,6 @@
 #ifndef _SPARC_PAGE_H
 #define _SPARC_PAGE_H
 
-#include <linux/config.h>
 #ifdef CONFIG_SUN4
 #define PAGE_SHIFT   13
 #else
diff --git a/arch/sparc/lib/Makefile b/arch/sparc/lib/Makefile
index 7e78d44754..e69b9ba426 100644
--- a/arch/sparc/lib/Makefile
+++ b/arch/sparc/lib/Makefile
@@ -5,26 +5,5 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(ARCH).o
-
-SOBJS	=
-
-COBJS	= board.o cache.o interrupts.o time.o
-COBJS-$(CONFIG_CMD_BOOTM) += bootm.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS))
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	= board.o cache.o interrupts.o time.o
+obj-$(CONFIG_CMD_BOOTM) += bootm.o
diff --git a/arch/x86/config.mk b/arch/x86/config.mk
index b22959f54b..38cb7c93a5 100644
--- a/arch/x86/config.mk
+++ b/arch/x86/config.mk
@@ -8,13 +8,10 @@
 CONFIG_STANDALONE_LOAD_ADDR ?= 0x40000
 
 PLATFORM_CPPFLAGS += -fno-strict-aliasing
-PLATFORM_CPPFLAGS += -Wstrict-prototypes
 PLATFORM_CPPFLAGS += -mregparm=3
 PLATFORM_CPPFLAGS += -fomit-frame-pointer
-PF_CPPFLAGS_X86   := $(call cc-option, -ffreestanding) \
-		     $(call cc-option, -fno-toplevel-reorder, \
+PF_CPPFLAGS_X86   := $(call cc-option, -fno-toplevel-reorder, \
 		       $(call cc-option, -fno-unit-at-a-time)) \
-		     $(call cc-option, -fno-stack-protector) \
 		     $(call cc-option, -mpreferred-stack-boundary=2)
 PLATFORM_CPPFLAGS += $(PF_CPPFLAGS_X86)
 PLATFORM_CPPFLAGS += -fno-dwarf2-cfi-asm
@@ -31,7 +28,5 @@ LDFLAGS_FINAL += --gc-sections -pie
 LDFLAGS_FINAL += --wrap=__divdi3 --wrap=__udivdi3
 LDFLAGS_FINAL += --wrap=__moddi3 --wrap=__umoddi3
 
-NORMAL_LIBGCC = $(shell $(CC) $(CFLAGS) -print-libgcc-file-name)
-PREFIXED_LIBGCC = $(OBJTREE)/arch/$(ARCH)/lib/$(shell basename $(NORMAL_LIBGCC))
-
-export USE_PRIVATE_LIBGCC=$(shell dirname $(PREFIXED_LIBGCC))
+export NORMAL_LIBGCC = $(shell $(CC) $(CFLAGS) -print-libgcc-file-name)
+CONFIG_USE_PRIVATE_LIBGCC := arch/x86/lib
diff --git a/arch/x86/cpu/Makefile b/arch/x86/cpu/Makefile
index 41555abc34..415bc24989 100644
--- a/arch/x86/cpu/Makefile
+++ b/arch/x86/cpu/Makefile
@@ -8,28 +8,6 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(CPU).o
-
-START-y	= start.o
-START-$(CONFIG_X86_RESET_VECTOR) += resetvec.o start16.o
-COBJS	= interrupts.o cpu.o
-
-SRCS	:= $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS))
-START	:= $(addprefix $(obj),$(START-y))
-
-all:	$(obj).depend $(START) $(LIB)
-
-$(LIB):	$(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+extra-y	= start.o
+extra-$(CONFIG_X86_RESET_VECTOR) += resetvec.o start16.o
+obj-y	= interrupts.o cpu.o
diff --git a/arch/x86/cpu/coreboot/Makefile b/arch/x86/cpu/coreboot/Makefile
index 18fa115826..cd0bf4ed31 100644
--- a/arch/x86/cpu/coreboot/Makefile
+++ b/arch/x86/cpu/coreboot/Makefile
@@ -13,31 +13,10 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	:= $(obj)lib$(SOC).o
-
-SOBJS-$(CONFIG_SYS_COREBOOT) += car.o
-COBJS-$(CONFIG_SYS_COREBOOT) += coreboot.o
-COBJS-$(CONFIG_SYS_COREBOOT) += tables.o
-COBJS-$(CONFIG_SYS_COREBOOT) += ipchecksum.o
-COBJS-$(CONFIG_SYS_COREBOOT) += sdram.o
-COBJS-$(CONFIG_SYS_COREBOOT) += timestamp.o
-COBJS-$(CONFIG_PCI) += pci.o
-
-SRCS	:= $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
-OBJS	:= $(addprefix $(obj),$(SOBJS-y) $(COBJS-y))
-
-all: $(obj).depend $(LIB)
-
-$(LIB):	$(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-$(CONFIG_SYS_COREBOOT) += car.o
+obj-$(CONFIG_SYS_COREBOOT) += coreboot.o
+obj-$(CONFIG_SYS_COREBOOT) += tables.o
+obj-$(CONFIG_SYS_COREBOOT) += ipchecksum.o
+obj-$(CONFIG_SYS_COREBOOT) += sdram.o
+obj-$(CONFIG_SYS_COREBOOT) += timestamp.o
+obj-$(CONFIG_PCI) += pci.o
diff --git a/arch/x86/dts/.gitignore b/arch/x86/dts/.gitignore
new file mode 100644
index 0000000000..b60ed208c7
--- /dev/null
+++ b/arch/x86/dts/.gitignore
@@ -0,0 +1 @@
+*.dtb
diff --git a/arch/x86/dts/Makefile b/arch/x86/dts/Makefile
new file mode 100644
index 0000000000..48265ef6dd
--- /dev/null
+++ b/arch/x86/dts/Makefile
@@ -0,0 +1,12 @@
+dtb-y += link.dtb \
+	alex.dtb
+
+targets += $(dtb-y)
+
+DTC_FLAGS += -R 4 -p 0x1000
+
+PHONY += dtbs
+dtbs: $(addprefix $(obj)/, $(dtb-y))
+	@:
+
+clean-files := *.dtb
diff --git a/board/chromebook-x86/dts/alex.dts b/arch/x86/dts/alex.dts
index 2f13544612..2f13544612 100644
--- a/board/chromebook-x86/dts/alex.dts
+++ b/arch/x86/dts/alex.dts
diff --git a/board/chromebook-x86/dts/link.dts b/arch/x86/dts/link.dts
index 4a37dac4ea..4a37dac4ea 100644
--- a/board/chromebook-x86/dts/link.dts
+++ b/arch/x86/dts/link.dts
diff --git a/arch/x86/include/asm/mtrr.h b/arch/x86/include/asm/mtrr.h
deleted file mode 100644
index fac2e58502..0000000000
--- a/arch/x86/include/asm/mtrr.h
+++ /dev/null
@@ -1,193 +0,0 @@
-/*
- * Generic MTRR (Memory Type Range Register) ioctls.
- * Taken from the Linux kernel
- *
- * (C) Copyright 2012
- * Graeme Russ, <graeme.russ@gmail.com>
- *
- * Copyright (C) 1997-1999  Richard Gooch <rgooch@atnf.csiro.au>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef _ASM_X86_MTRR_H
-#define _ASM_X86_MTRR_H
-
-#define MTRRphysBase_MSR(reg) (0x200 + 2 * (reg))
-#define MTRRphysMask_MSR(reg) (0x200 + 2 * (reg) + 1)
-
-#ifndef __ASSEMBLY__
-
-#include <linux/types.h>
-#include <linux/ioctl.h>
-#include <errno.h>
-
-#define	MTRR_IOCTL_BASE	'M'
-
-struct mtrr_sentry {
-	unsigned long base;	/*  Base address     */
-	unsigned int size;	/*  Size of region   */
-	unsigned int type;	/*  Type of region   */
-};
-
-/*
- * Warning: this structure has a different order from i386
- * on x86-64. The 32bit emulation code takes care of that.
- * But you need to use this for 64bit, otherwise your X server
- * will break.
- */
-
-#ifdef __i386__
-struct mtrr_gentry {
-	unsigned int regnum;	/*  Register number  */
-	unsigned long base;	/*  Base address     */
-	unsigned int size;	/*  Size of region   */
-	unsigned int type;	/*  Type of region   */
-};
-
-#else /* __i386__ */
-
-struct mtrr_gentry {
-	unsigned long base;	/*  Base address     */
-	unsigned int size;	/*  Size of region   */
-	unsigned int regnum;	/*  Register number  */
-	unsigned int type;	/*  Type of region   */
-};
-#endif /* !__i386__ */
-
-struct mtrr_var_range {
-	__u32 base_lo;
-	__u32 base_hi;
-	__u32 mask_lo;
-	__u32 mask_hi;
-};
-
-/*
- * In the Intel processor's MTRR interface, the MTRR type is always held in
- * an 8 bit field:
- */
-typedef __u8 mtrr_type;
-
-#define MTRR_NUM_FIXED_RANGES 88
-#define MTRR_MAX_VAR_RANGES 256
-
-struct mtrr_state_type {
-	struct mtrr_var_range var_ranges[MTRR_MAX_VAR_RANGES];
-	mtrr_type fixed_ranges[MTRR_NUM_FIXED_RANGES];
-	unsigned char enabled;
-	unsigned char have_fixed;
-	mtrr_type def_type;
-};
-
-/*  These are the various ioctls  */
-#define MTRRIOC_ADD_ENTRY        _IOW(MTRR_IOCTL_BASE,  0, struct mtrr_sentry)
-#define MTRRIOC_SET_ENTRY        _IOW(MTRR_IOCTL_BASE,  1, struct mtrr_sentry)
-#define MTRRIOC_DEL_ENTRY        _IOW(MTRR_IOCTL_BASE,  2, struct mtrr_sentry)
-#define MTRRIOC_GET_ENTRY        _IOWR(MTRR_IOCTL_BASE, 3, struct mtrr_gentry)
-#define MTRRIOC_KILL_ENTRY       _IOW(MTRR_IOCTL_BASE,  4, struct mtrr_sentry)
-#define MTRRIOC_ADD_PAGE_ENTRY   _IOW(MTRR_IOCTL_BASE,  5, struct mtrr_sentry)
-#define MTRRIOC_SET_PAGE_ENTRY   _IOW(MTRR_IOCTL_BASE,  6, struct mtrr_sentry)
-#define MTRRIOC_DEL_PAGE_ENTRY   _IOW(MTRR_IOCTL_BASE,  7, struct mtrr_sentry)
-#define MTRRIOC_GET_PAGE_ENTRY   _IOWR(MTRR_IOCTL_BASE, 8, struct mtrr_gentry)
-#define MTRRIOC_KILL_PAGE_ENTRY  _IOW(MTRR_IOCTL_BASE,  9, struct mtrr_sentry)
-
-/*  These are the region types  */
-#define MTRR_TYPE_UNCACHABLE 0
-#define MTRR_TYPE_WRCOMB     1
-/*#define MTRR_TYPE_         2*/
-/*#define MTRR_TYPE_         3*/
-#define MTRR_TYPE_WRTHROUGH  4
-#define MTRR_TYPE_WRPROT     5
-#define MTRR_TYPE_WRBACK     6
-#define MTRR_NUM_TYPES       7
-
-#ifdef __KERNEL__
-
-/*  The following functions are for use by other drivers  */
-# ifdef CONFIG_MTRR
-extern u8 mtrr_type_lookup(u64 addr, u64 end);
-extern void mtrr_save_fixed_ranges(void *);
-extern void mtrr_save_state(void);
-extern int mtrr_add(unsigned long base, unsigned long size,
-		    unsigned int type, bool increment);
-extern int mtrr_add_page(unsigned long base, unsigned long size,
-			 unsigned int type, bool increment);
-extern int mtrr_del(int reg, unsigned long base, unsigned long size);
-extern int mtrr_del_page(int reg, unsigned long base, unsigned long size);
-extern void mtrr_centaur_report_mcr(int mcr, u32 lo, u32 hi);
-extern void mtrr_ap_init(void);
-extern void mtrr_bp_init(void);
-extern void set_mtrr_aps_delayed_init(void);
-extern void mtrr_aps_init(void);
-extern void mtrr_bp_restore(void);
-extern int mtrr_trim_uncached_memory(unsigned long end_pfn);
-extern int amd_special_default_mtrr(void);
-#  else
-static inline u8 mtrr_type_lookup(u64 addr, u64 end)
-{
-	/*
-	 * Return no-MTRRs:
-	 */
-	return 0xff;
-}
-#define mtrr_save_fixed_ranges(arg) do {} while (0)
-#define mtrr_save_state() do {} while (0)
-static inline int mtrr_del(int reg, unsigned long base, unsigned long size)
-{
-	return -ENODEV;
-}
-static inline int mtrr_del_page(int reg, unsigned long base, unsigned long size)
-{
-	return -ENODEV;
-}
-static inline int mtrr_trim_uncached_memory(unsigned long end_pfn)
-{
-	return 0;
-}
-static inline void mtrr_centaur_report_mcr(int mcr, u32 lo, u32 hi)
-{
-}
-
-#define mtrr_ap_init() do {} while (0)
-#define mtrr_bp_init() do {} while (0)
-#define set_mtrr_aps_delayed_init() do {} while (0)
-#define mtrr_aps_init() do {} while (0)
-#define mtrr_bp_restore() do {} while (0)
-#  endif
-
-#ifdef CONFIG_COMPAT
-#include <linux/compat.h>
-
-struct mtrr_sentry32 {
-	compat_ulong_t base;	/*  Base address     */
-	compat_uint_t size;	/*  Size of region   */
-	compat_uint_t type;	/*  Type of region   */
-};
-
-struct mtrr_gentry32 {
-	compat_ulong_t regnum;	/*  Register number  */
-	compat_uint_t base;	/*  Base address     */
-	compat_uint_t size;	/*  Size of region   */
-	compat_uint_t type;	/*  Type of region   */
-};
-
-#define MTRR_IOCTL_BASE 'M'
-
-#define MTRRIOC32_ADD_ENTRY      _IOW(MTRR_IOCTL_BASE,  0, struct mtrr_sentry32)
-#define MTRRIOC32_SET_ENTRY      _IOW(MTRR_IOCTL_BASE,  1, struct mtrr_sentry32)
-#define MTRRIOC32_DEL_ENTRY      _IOW(MTRR_IOCTL_BASE,  2, struct mtrr_sentry32)
-#define MTRRIOC32_GET_ENTRY      _IOWR(MTRR_IOCTL_BASE, 3, struct mtrr_gentry32)
-#define MTRRIOC32_KILL_ENTRY     _IOW(MTRR_IOCTL_BASE,  4, struct mtrr_sentry32)
-#define MTRRIOC32_ADD_PAGE_ENTRY _IOW(MTRR_IOCTL_BASE,  5, struct mtrr_sentry32)
-#define MTRRIOC32_SET_PAGE_ENTRY _IOW(MTRR_IOCTL_BASE,  6, struct mtrr_sentry32)
-#define MTRRIOC32_DEL_PAGE_ENTRY _IOW(MTRR_IOCTL_BASE,  7, struct mtrr_sentry32)
-#define MTRRIOC32_GET_PAGE_ENTRY _IOWR(MTRR_IOCTL_BASE, 8, struct mtrr_gentry32)
-#define MTRRIOC32_KILL_PAGE_ENTRY		\
-				 _IOW(MTRR_IOCTL_BASE,  9, struct mtrr_sentry32)
-#endif /* CONFIG_COMPAT */
-
-#endif /* __KERNEL__ */
-
-#endif /* __ASSEMBLY__ */
-
-#endif /* _ASM_X86_MTRR_H */
diff --git a/arch/x86/include/asm/pci.h b/arch/x86/include/asm/pci.h
index cbc4a9e2e9..6b161881e7 100644
--- a/arch/x86/include/asm/pci.h
+++ b/arch/x86/include/asm/pci.h
@@ -1,5 +1,4 @@
 
-
 /*
  * (C) Copyright 2002
  * Daniel Engström, Omicron Ceti AB, daniel@omicron.se
diff --git a/arch/x86/lib/Makefile b/arch/x86/lib/Makefile
index f389767fb9..f7303abccb 100644
--- a/arch/x86/lib/Makefile
+++ b/arch/x86/lib/Makefile
@@ -5,41 +5,24 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(ARCH).o
-
-COBJS-$(CONFIG_CMD_BOOTM) += bootm.o
-COBJS-y	+= cmd_boot.o
-COBJS-y	+= gcc.o
-COBJS-y	+= init_helpers.o
-COBJS-y	+= interrupts.o
-COBJS-$(CONFIG_SYS_PCAT_INTERRUPTS) += pcat_interrupts.o
-COBJS-$(CONFIG_SYS_PCAT_TIMER) += pcat_timer.o
-COBJS-$(CONFIG_PCI) += pci_type1.o
-COBJS-y	+= relocate.o
-COBJS-y += physmem.o
-COBJS-y	+= string.o
-COBJS-$(CONFIG_SYS_X86_TSC_TIMER)	+= tsc_timer.o
-COBJS-$(CONFIG_VIDEO_VGA)	+= video.o
-COBJS-$(CONFIG_CMD_ZBOOT)	+= zimage.o
-
-SRCS	:= $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
-OBJS	:= $(addprefix $(obj),$(SOBJS-y) $(COBJS-y))
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-$(PREFIXED_LIBGCC): $(NORMAL_LIBGCC)
-	$(OBJCOPY) $< $@ --prefix-symbols=__normal_
-
-$(LIB): $(PREFIXED_LIBGCC)
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-$(CONFIG_CMD_BOOTM) += bootm.o
+obj-y	+= cmd_boot.o
+obj-y	+= gcc.o
+obj-y	+= init_helpers.o
+obj-y	+= interrupts.o
+obj-$(CONFIG_SYS_PCAT_INTERRUPTS) += pcat_interrupts.o
+obj-$(CONFIG_SYS_PCAT_TIMER) += pcat_timer.o
+obj-$(CONFIG_PCI) += pci_type1.o
+obj-y	+= relocate.o
+obj-y += physmem.o
+obj-y	+= string.o
+obj-$(CONFIG_SYS_X86_TSC_TIMER)	+= tsc_timer.o
+obj-$(CONFIG_VIDEO_VGA)	+= video.o
+obj-$(CONFIG_CMD_ZBOOT)	+= zimage.o
+
+LIBGCC := $(notdir $(NORMAL_LIBGCC))
+extra-y := $(LIBGCC)
+
+OBJCOPYFLAGS := --prefix-symbols=__normal_
+$(obj)/$(LIBGCC): $(NORMAL_LIBGCC) FORCE
+	$(call if_changed,objcopy)
diff --git a/arch/x86/cpu/coreboot/asm-offsets.c b/arch/x86/lib/asm-offsets.c
index d65c6ab1b0..d65c6ab1b0 100644
--- a/arch/x86/cpu/coreboot/asm-offsets.c
+++ b/arch/x86/lib/asm-offsets.c
diff --git a/arch/x86/lib/init_helpers.c b/arch/x86/lib/init_helpers.c
index 582c0ffe24..b5d937feb3 100644
--- a/arch/x86/lib/init_helpers.c
+++ b/arch/x86/lib/init_helpers.c
@@ -92,7 +92,7 @@ int find_fdt(void)
 {
 #ifdef CONFIG_OF_EMBED
 	/* Get a pointer to the FDT */
-	gd->fdt_blob = _binary_dt_dtb_start;
+	gd->fdt_blob = __dtb_dt_begin;
 #elif defined CONFIG_OF_SEPARATE
 	/* FDT is at end of image */
 	gd->fdt_blob = (ulong *)&_end;
diff --git a/board/8dtech/eco5pk/Makefile b/board/8dtech/eco5pk/Makefile
index 2fafcb8682..3333781fb6 100644
--- a/board/8dtech/eco5pk/Makefile
+++ b/board/8dtech/eco5pk/Makefile
@@ -7,21 +7,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	:= eco5pk.o
-
-SRCS	:= $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
+obj-y	:= eco5pk.o
diff --git a/board/AndesTech/adp-ag101/Makefile b/board/AndesTech/adp-ag101/Makefile
index 826414f5b1..4cc590ff29 100644
--- a/board/AndesTech/adp-ag101/Makefile
+++ b/board/AndesTech/adp-ag101/Makefile
@@ -6,23 +6,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS-y	:= adp-ag101.o
-
-SRCS	:= $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS-y) $(SOBJS-y))
-
-$(LIB):	$(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	:= adp-ag101.o
diff --git a/board/AndesTech/adp-ag101p/Makefile b/board/AndesTech/adp-ag101p/Makefile
index 875fb9228c..2ba7da46da 100644
--- a/board/AndesTech/adp-ag101p/Makefile
+++ b/board/AndesTech/adp-ag101p/Makefile
@@ -6,23 +6,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS-y	:= adp-ag101p.o
-
-SRCS	:= $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS-y) $(SOBJS-y))
-
-$(LIB):	$(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	:= adp-ag101p.o
diff --git a/board/AndesTech/adp-ag102/Makefile b/board/AndesTech/adp-ag102/Makefile
index 6c187190b2..fc4bf88a5c 100644
--- a/board/AndesTech/adp-ag102/Makefile
+++ b/board/AndesTech/adp-ag102/Makefile
@@ -5,23 +5,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS-y	:= adp-ag102.o
-
-SRCS	:= $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS-y) $(SOBJS-y))
-
-$(LIB):	$(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	:= adp-ag102.o
diff --git a/board/Barix/ipam390/Makefile b/board/Barix/ipam390/Makefile
index c84ee05c83..1cb4b57c2c 100644
--- a/board/Barix/ipam390/Makefile
+++ b/board/Barix/ipam390/Makefile
@@ -7,23 +7,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	+= ipam390.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
-	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
-
-#########################################################################
-# This is for $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	+= ipam390.o
diff --git a/board/Barix/ipam390/ipam390-ais-uart.cfg b/board/Barix/ipam390/ipam390-ais-uart.cfg
index e1a99f278b..709cf231d0 100644
--- a/board/Barix/ipam390/ipam390-ais-uart.cfg
+++ b/board/Barix/ipam390/ipam390-ais-uart.cfg
@@ -109,7 +109,7 @@ CLK2XSRC = 0x00000000
 ;NANDFCR = 0x00000000
 [EMIF25ASYNC]
 A1CR = 0x00000000
-A2CR = 0x3FFFFFFE
+A2CR = 0x04202110
 A3CR = 0x00000000
 A4CR = 0x00000000
 NANDFCR = 0x00000012
diff --git a/board/Barix/ipam390/ipam390.c b/board/Barix/ipam390/ipam390.c
index f3f276ea8f..ae88b4230a 100644
--- a/board/Barix/ipam390/ipam390.c
+++ b/board/Barix/ipam390/ipam390.c
@@ -264,7 +264,7 @@ void show_boot_progress(int status)
 	static int green;
 
 	if (red == 0)
-		red = init_led(CONFIG_IPAM390_GPIO_LED_RED, "red", LED_OFF);
+		red = init_led(CONFIG_IPAM390_GPIO_LED_RED, "red", LED_ON);
 	if (red != CONFIG_IPAM390_GPIO_LED_RED)
 		return;
 	if (green == 0)
@@ -277,10 +277,10 @@ void show_boot_progress(int status)
 	case BOOTSTAGE_ID_RUN_OS:
 		/*
 		 * set normal state
-		 * LED Red  : off
+		 * LED Red  : on
 		 * LED green: off
 		 */
-		gpio_set_value(red, LED_OFF);
+		gpio_set_value(red, LED_ON);
 		gpio_set_value(green, LED_OFF);
 		break;
 	case BOOTSTAGE_ID_MAIN_LOOP:
@@ -326,23 +326,12 @@ int spl_start_uboot(void)
 	if (!bootmode)
 		if (ret == 0)
 			bootmode = 1;
-	if (bootmode) {
-		/*
-		 * Booting U-Boot
-		 * LED Red  : on
-		 * LED green: off
-		 */
-		init_led(CONFIG_IPAM390_GPIO_LED_RED, "red", LED_ON);
-		init_led(CONFIG_IPAM390_GPIO_LED_GREEN, "green", LED_OFF);
-	} else {
-		/*
-		 * Booting Linux
-		 * LED Red  : off
-		 * LED green: off
-		 */
-		init_led(CONFIG_IPAM390_GPIO_LED_RED, "red", LED_OFF);
-		init_led(CONFIG_IPAM390_GPIO_LED_GREEN, "green", LED_OFF);
-	}
+	/*
+	 * LED red  : on
+	 * LED green: off
+	 */
+	init_led(CONFIG_IPAM390_GPIO_LED_RED, "red", LED_ON);
+	init_led(CONFIG_IPAM390_GPIO_LED_GREEN, "green", LED_OFF);
 	return bootmode;
 }
 #endif
diff --git a/board/Barix/ipam390/u-boot-spl-ipam390.lds b/board/Barix/ipam390/u-boot-spl-ipam390.lds
index 5480d1f276..8604696be7 100644
--- a/board/Barix/ipam390/u-boot-spl-ipam390.lds
+++ b/board/Barix/ipam390/u-boot-spl-ipam390.lds
@@ -49,5 +49,9 @@ SECTIONS
 	} >.sram
 
 	__image_copy_end = .;
-	_end = .;
+
+	.end :
+	{
+		*(.__end)
+	} >.sram
 }
diff --git a/board/BuR/common/bur_common.h b/board/BuR/common/bur_common.h
new file mode 100644
index 0000000000..15225b0724
--- /dev/null
+++ b/board/BuR/common/bur_common.h
@@ -0,0 +1,22 @@
+/*
+ * bur_comon.h
+ *
+ * common board information header for B&R boards
+ *
+ * Copyright (C) 2013 Hannes Petermaier <oe5hpm@oevsv.at>
+ * Bernecker & Rainer Industrieelektronik GmbH - http://www.br-automation.com
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _BUR_COMMON_H_
+#define _BUR_COMMON_H_
+
+void blink(u32 blinks, u32 intervall, u32 pin);
+void pmicsetup(u32 mpupll);
+void enable_uart0_pin_mux(void);
+void enable_i2c0_pin_mux(void);
+void enable_board_pin_mux(void);
+int board_eth_init(bd_t *bis);
+
+#endif
diff --git a/board/BuR/common/common.c b/board/BuR/common/common.c
new file mode 100644
index 0000000000..4c926ce700
--- /dev/null
+++ b/board/BuR/common/common.c
@@ -0,0 +1,216 @@
+/*
+ * common.c
+ *
+ * common board functions for B&R boards
+ *
+ * Copyright (C) 2013 Hannes Petermaier <oe5hpm@oevsv.at>
+ * Bernecker & Rainer Industrieelektronik GmbH - http://www.br-automation.com
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ *
+ */
+
+#include <common.h>
+#include <errno.h>
+#include <spl.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/omap.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/io.h>
+#include <asm/gpio.h>
+#include <i2c.h>
+#include <miiphy.h>
+#include <cpsw.h>
+#include <power/tps65217.h>
+#include "bur_common.h"
+
+static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
+/* --------------------------------------------------------------------------*/
+void blink(u32 blinks, u32 intervall, u32 pin)
+{
+	gpio_direction_output(pin, 0);
+	int val = 0;
+
+	do {
+		val ^= 0x01;
+		gpio_set_value(pin, val);
+		mdelay(intervall);
+	} while (blinks--);
+
+	gpio_set_value(pin, 0);
+}
+#ifdef CONFIG_SPL_BUILD
+void pmicsetup(u32 mpupll)
+{
+	int mpu_vdd;
+	int usb_cur_lim;
+
+	/* setup I2C */
+	enable_i2c0_pin_mux();
+	i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE);
+
+	if (i2c_probe(TPS65217_CHIP_PM)) {
+		puts("PMIC (0x24) not found! skip further initalization.\n");
+		return;
+	}
+
+	/* Get the frequency which is defined by device fuses */
+	dpll_mpu_opp100.m = am335x_get_efuse_mpu_max_freq(cdev);
+	printf("detected max. frequency: %d - ", dpll_mpu_opp100.m);
+
+	if (0 != mpupll) {
+		dpll_mpu_opp100.m = MPUPLL_M_1000;
+		printf("retuning MPU-PLL to: %d MHz.\n", dpll_mpu_opp100.m);
+	} else {
+		puts("ok.\n");
+	}
+	/*
+	 * Increase USB current limit to 1300mA or 1800mA and set
+	 * the MPU voltage controller as needed.
+	 */
+	if (dpll_mpu_opp100.m == MPUPLL_M_1000) {
+		usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1800MA;
+		mpu_vdd = TPS65217_DCDC_VOLT_SEL_1325MV;
+	} else {
+		usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1300MA;
+		mpu_vdd = TPS65217_DCDC_VOLT_SEL_1275MV;
+	}
+
+	if (tps65217_reg_write(TPS65217_PROT_LEVEL_NONE, TPS65217_POWER_PATH,
+			       usb_cur_lim, TPS65217_USB_INPUT_CUR_LIMIT_MASK))
+		puts("tps65217_reg_write failure\n");
+
+	/* Set DCDC3 (CORE) voltage to 1.125V */
+	if (tps65217_voltage_update(TPS65217_DEFDCDC3,
+				    TPS65217_DCDC_VOLT_SEL_1125MV)) {
+		puts("tps65217_voltage_update failure\n");
+		return;
+	}
+
+	/* Set CORE Frequencies to OPP100 */
+	do_setup_dpll(&dpll_core_regs, &dpll_core_opp100);
+
+	/* Set DCDC2 (MPU) voltage */
+	if (tps65217_voltage_update(TPS65217_DEFDCDC2, mpu_vdd)) {
+		puts("tps65217_voltage_update failure\n");
+		return;
+	}
+
+	/* Set LDO3 to 1.8V */
+	if (tps65217_reg_write(TPS65217_PROT_LEVEL_2,
+			       TPS65217_DEFLS1,
+			       TPS65217_LDO_VOLTAGE_OUT_1_8,
+			       TPS65217_LDO_MASK))
+		puts("tps65217_reg_write failure\n");
+	/* Set LDO4 to 3.3V */
+	if (tps65217_reg_write(TPS65217_PROT_LEVEL_2,
+			       TPS65217_DEFLS2,
+			       TPS65217_LDO_VOLTAGE_OUT_3_3,
+			       TPS65217_LDO_MASK))
+		puts("tps65217_reg_write failure\n");
+
+	/* Set MPU Frequency to what we detected now that voltages are set */
+	do_setup_dpll(&dpll_mpu_regs, &dpll_mpu_opp100);
+}
+
+void set_uart_mux_conf(void)
+{
+	enable_uart0_pin_mux();
+}
+
+void set_mux_conf_regs(void)
+{
+	enable_board_pin_mux();
+}
+
+#endif /* CONFIG_SPL_BUILD */
+
+#if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
+	(defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
+static void cpsw_control(int enabled)
+{
+	/* VTP can be added here */
+	return;
+}
+
+/* describing port offsets of TI's CPSW block */
+static struct cpsw_slave_data cpsw_slaves[] = {
+	{
+		.slave_reg_ofs	= 0x208,
+		.sliver_reg_ofs	= 0xd80,
+		.phy_addr	= 1,
+	},
+	{
+		.slave_reg_ofs	= 0x308,
+		.sliver_reg_ofs	= 0xdc0,
+		.phy_addr	= 2,
+	},
+};
+
+static struct cpsw_platform_data cpsw_data = {
+	.mdio_base		= CPSW_MDIO_BASE,
+	.cpsw_base		= CPSW_BASE,
+	.mdio_div		= 0xff,
+	.channels		= 8,
+	.cpdma_reg_ofs		= 0x800,
+	.slaves			= 1,
+	.slave_data		= cpsw_slaves,
+	.ale_reg_ofs		= 0xd00,
+	.ale_entries		= 1024,
+	.host_port_reg_ofs	= 0x108,
+	.hw_stats_reg_ofs	= 0x900,
+	.bd_ram_ofs		= 0x2000,
+	.mac_control		= (1 << 5),
+	.control		= cpsw_control,
+	.host_port_num		= 0,
+	.version		= CPSW_CTRL_VERSION_2,
+};
+#endif /* CONFIG_DRIVER_TI_CPSW, ... */
+
+#if defined(CONFIG_DRIVER_TI_CPSW)
+
+int board_eth_init(bd_t *bis)
+{
+	int rv = 0;
+	uint8_t mac_addr[6];
+	uint32_t mac_hi, mac_lo;
+
+	/* try reading mac address from efuse */
+	mac_lo = readl(&cdev->macid0l);
+	mac_hi = readl(&cdev->macid0h);
+	mac_addr[0] = mac_hi & 0xFF;
+	mac_addr[1] = (mac_hi & 0xFF00) >> 8;
+	mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
+	mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
+	mac_addr[4] = mac_lo & 0xFF;
+	mac_addr[5] = (mac_lo & 0xFF00) >> 8;
+
+#if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
+	(defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
+	if (!getenv("ethaddr")) {
+		printf("<ethaddr> not set. Validating first E-fuse MAC ... ");
+
+		if (is_valid_ether_addr(mac_addr)) {
+			printf("using: %02X:%02X:%02X:%02X:%02X:%02X.\n",
+			       mac_addr[0], mac_addr[1], mac_addr[2],
+			       mac_addr[3], mac_addr[4], mac_addr[5]
+				);
+			eth_setenv_enetaddr("ethaddr", mac_addr);
+		}
+	}
+	writel(MII_MODE_ENABLE, &cdev->miisel);
+	cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_MII;
+	cpsw_slaves[1].phy_if =	PHY_INTERFACE_MODE_MII;
+
+	rv = cpsw_register(&cpsw_data);
+	if (rv < 0) {
+		printf("Error %d registering CPSW switch\n", rv);
+		return 0;
+	}
+#endif /* CONFIG_DRIVER_TI_CPSW, ... */
+	return rv;
+}
+#endif /* CONFIG_DRIVER_TI_CPSW */
diff --git a/board/BuR/kwb/Makefile b/board/BuR/kwb/Makefile
new file mode 100644
index 0000000000..7b04b26ae4
--- /dev/null
+++ b/board/BuR/kwb/Makefile
@@ -0,0 +1,12 @@
+#
+# Makefile
+#
+# Copyright (C) 2014 Hannes Petermaier <oe5hpm@oevsv.at> -
+# Bernecker & Rainer Industrielektronik GmbH - http://www.br-automation.com/
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-$(CONFIG_SPL_BUILD) += mux.o
+obj-y	+= ../common/common.o
+obj-y	+= board.o
diff --git a/board/BuR/kwb/board.c b/board/BuR/kwb/board.c
new file mode 100644
index 0000000000..804765a8de
--- /dev/null
+++ b/board/BuR/kwb/board.c
@@ -0,0 +1,240 @@
+/*
+ * board.c
+ *
+ * Board functions for B&R KWB Board
+ *
+ * Copyright (C) 2013 Hannes Petermaier <oe5hpm@oevsv.at>
+ * Bernecker & Rainer Industrieelektronik GmbH - http://www.br-automation.com
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ *
+ */
+#include <common.h>
+#include <errno.h>
+#include <spl.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/omap.h>
+#include <asm/arch/ddr_defs.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/mem.h>
+#include <asm/io.h>
+#include <asm/emif.h>
+#include <asm/gpio.h>
+#include <i2c.h>
+#include <power/tps65217.h>
+#include "../common/bur_common.h"
+
+/* -------------------------------------------------------------------------*/
+/* -- defines for used GPIO Hardware -- */
+#define KEY						(0+4)
+#define LCD_PWR						(0+5)
+#define PUSH_KEY					(0+31)
+#define USB2SD_NRST					(32+29)
+#define USB2SD_PWR					(96+13)
+/* -------------------------------------------------------------------------*/
+/* -- PSOC Resetcontroller Register defines -- */
+
+/* I2C Address of controller */
+#define	RSTCTRL_ADDR				0x75
+/* Register for CTRL-word */
+#define RSTCTRL_CTRLREG				0x01
+/* Register for giving some information to VxWorks OS */
+#define RSTCTRL_SCRATCHREG			0x04
+
+/* -- defines for RSTCTRL_CTRLREG  -- */
+#define	RSTCTRL_FORCE_PWR_NEN			0x0404
+
+#if defined(CONFIG_SPL_BUILD)
+/* TODO: check ram-timing ! */
+static const struct ddr_data ddr3_data = {
+	.datardsratio0 = MT41K256M16HA125E_RD_DQS,
+	.datawdsratio0 = MT41K256M16HA125E_WR_DQS,
+	.datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE,
+	.datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA,
+};
+static const struct cmd_control ddr3_cmd_ctrl_data = {
+	.cmd0csratio = MT41K256M16HA125E_RATIO,
+	.cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
+
+	.cmd1csratio = MT41K256M16HA125E_RATIO,
+	.cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
+
+	.cmd2csratio = MT41K256M16HA125E_RATIO,
+	.cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
+};
+static struct emif_regs ddr3_emif_reg_data = {
+	.sdram_config = MT41K256M16HA125E_EMIF_SDCFG,
+	.ref_ctrl = MT41K256M16HA125E_EMIF_SDREF,
+	.sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1,
+	.sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2,
+	.sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3,
+	.zq_config = MT41K256M16HA125E_ZQ_CFG,
+	.emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY,
+};
+
+static const struct ctrl_ioregs ddr3_ioregs = {
+	.cm0ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
+	.cm1ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
+	.cm2ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
+	.dt0ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
+	.dt1ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
+};
+
+#define OSC	(V_OSCK/1000000)
+const struct dpll_params dpll_ddr3 = { 400, OSC-1, 1, -1, -1, -1, -1};
+
+void am33xx_spl_board_init(void)
+{
+	unsigned int oldspeed;
+	unsigned short buf;
+
+	struct cm_perpll *const cmper = (struct cm_perpll *)CM_PER;
+	struct cm_wkuppll *const cmwkup = (struct cm_wkuppll *)CM_WKUP;
+	/*
+	 * enable additional clocks of modules which are accessed later from
+	 * VxWorks OS
+	 */
+	u32 *const clk_domains[] = { 0 };
+
+	u32 *const clk_modules_kwbspecific[] = {
+		&cmwkup->wkup_adctscctrl,
+		&cmper->spi1clkctrl,
+		&cmper->dcan0clkctrl,
+		&cmper->dcan1clkctrl,
+		&cmper->epwmss0clkctrl,
+		&cmper->epwmss1clkctrl,
+		&cmper->epwmss2clkctrl,
+		0
+	};
+	do_enable_clocks(clk_domains, clk_modules_kwbspecific, 1);
+
+	/* power-OFF LCD-Display */
+	gpio_direction_output(LCD_PWR, 0);
+
+	/* setup I2C */
+	enable_i2c0_pin_mux();
+	i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE);
+
+	/* power-ON  3V3 via Resetcontroller */
+	oldspeed = i2c_get_bus_speed();
+	if (i2c_set_bus_speed(CONFIG_SYS_OMAP24_I2C_SPEED_PSOC) >= 0) {
+		buf = RSTCTRL_FORCE_PWR_NEN;
+		i2c_write(RSTCTRL_ADDR, RSTCTRL_CTRLREG, 1,
+			  (uint8_t *)&buf, sizeof(buf));
+		i2c_set_bus_speed(oldspeed);
+	} else {
+		puts("ERROR: i2c_set_bus_speed failed! (turn on PWR_nEN)\n");
+	}
+
+#if defined(CONFIG_AM335X_USB0)
+	/* power on USB2SD Controller */
+	gpio_direction_output(USB2SD_PWR, 1);
+	mdelay(1);
+	/* give a reset Pulse to USB2SD Controller */
+	gpio_direction_output(USB2SD_NRST, 0);
+	mdelay(1);
+	gpio_set_value(USB2SD_NRST, 1);
+#endif
+	pmicsetup(0);
+}
+
+const struct dpll_params *get_dpll_ddr_params(void)
+{
+	return &dpll_ddr3;
+}
+
+void sdram_init(void)
+{
+	config_ddr(400, &ddr3_ioregs,
+		   &ddr3_data,
+		   &ddr3_cmd_ctrl_data,
+		   &ddr3_emif_reg_data, 0);
+}
+#endif /* CONFIG_SPL_BUILD */
+/*
+ * Basic board specific setup.  Pinmux has been handled already.
+ */
+int board_init(void)
+{
+	gpmc_init();
+	return 0;
+}
+
+#ifdef CONFIG_BOARD_LATE_INIT
+int board_late_init(void)
+{
+	const unsigned int ton  = 250;
+	const unsigned int toff = 1000;
+	unsigned int cnt  = 3;
+	unsigned short buf = 0xAAAA;
+	unsigned int oldspeed;
+
+	tps65217_reg_write(TPS65217_PROT_LEVEL_NONE,
+			   TPS65217_WLEDCTRL2, 0x32, 0xFF); /* 50% dimlevel */
+
+	if (gpio_get_value(KEY)) {
+		do {
+			/* turn on light */
+			tps65217_reg_write(TPS65217_PROT_LEVEL_NONE,
+					   TPS65217_WLEDCTRL1, 0x09, 0xFF);
+			mdelay(ton);
+			/* turn off light */
+			tps65217_reg_write(TPS65217_PROT_LEVEL_NONE,
+					   TPS65217_WLEDCTRL1, 0x01, 0xFF);
+			mdelay(toff);
+			cnt--;
+			if (!gpio_get_value(KEY) &&
+			    gpio_get_value(PUSH_KEY) && 1 == cnt) {
+				puts("updating from USB ...\n");
+				setenv("bootcmd", "run usbupdate");
+				break;
+			} else if (!gpio_get_value(KEY)) {
+				break;
+			}
+		} while (cnt);
+	}
+
+	switch (cnt) {
+	case 0:
+		puts("3 blinks ... entering BOOT mode.\n");
+		buf = 0x0000;
+		break;
+	case 1:
+		puts("2 blinks ... entering DIAGNOSE mode.\n");
+		buf = 0x0F0F;
+		break;
+	case 2:
+		puts("1 blinks ... entering SERVICE mode.\n");
+		buf = 0xB4B4;
+		break;
+	case 3:
+		puts("0 blinks ... entering RUN mode.\n");
+		buf = 0x0404;
+		break;
+	}
+	mdelay(ton);
+	/* turn on light */
+	tps65217_reg_write(TPS65217_PROT_LEVEL_NONE,
+			   TPS65217_WLEDCTRL1, 0x09, 0xFF);
+	/* write bootinfo into scratchregister of resetcontroller */
+	oldspeed = i2c_get_bus_speed();
+	if (i2c_set_bus_speed(CONFIG_SYS_OMAP24_I2C_SPEED_PSOC) >= 0) {
+		i2c_write(RSTCTRL_ADDR, RSTCTRL_SCRATCHREG, 1,
+			  (uint8_t *)&buf, sizeof(buf));
+		i2c_set_bus_speed(oldspeed);
+	} else {
+		puts("ERROR: i2c_set_bus_speed failed! (scratchregister)\n");
+	}
+	/*
+	 * reset VBAR registers to its reset location, VxWorks 6.9.3.2 does
+	 * expect that vectors are there, original u-boot moves them to _start
+	 */
+	__asm__("ldr r0,=0x20000");
+	__asm__("mcr p15, 0, r0, c12, c0, 0"); /* Set VBAR */
+
+	return 0;
+}
+#endif /* CONFIG_BOARD_LATE_INIT */
diff --git a/board/BuR/kwb/mux.c b/board/BuR/kwb/mux.c
new file mode 100644
index 0000000000..1a5ffd5709
--- /dev/null
+++ b/board/BuR/kwb/mux.c
@@ -0,0 +1,195 @@
+/*
+ * mux.c
+ *
+ * Pinmux Setting for B&R LEIT Board(s)
+ *
+ * Copyright (C) 2013 Hannes Petermaier <oe5hpm@oevsv.at>
+ * Bernecker & Rainer Industrieelektronik GmbH - http://www.br-automation.com
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/mux.h>
+#include <asm/io.h>
+#include <i2c.h>
+
+static struct module_pin_mux usb0_pin_mux[] = {
+	{OFFSET(usb0_id), (MODE(0) | RXACTIVE)},
+	/* USB0 DrvBus Receiver disable (from romcode 0x20) */
+	{OFFSET(usb0_drvvbus), (MODE(0))},
+	/* USB1 DrvBus as GPIO due to HW-Workaround */
+	{OFFSET(usb1_drvvbus), (MODE(7))},
+	{-1},
+};
+static struct module_pin_mux spi1_pin_mux[] = {
+	/* SPI1_SCLK */
+	{OFFSET(mcasp0_aclkx), MODE(3) | PULLUDEN |             RXACTIVE},
+	/* SPI1_D0 */
+	{OFFSET(mcasp0_fsx),   MODE(3) | PULLUDEN |		RXACTIVE},
+	/* SPI1_D1 */
+	{OFFSET(mcasp0_axr0),  MODE(3) | PULLUDEN |             RXACTIVE},
+	/* SPI1_CS0 */
+	{OFFSET(mcasp0_ahclkr), MODE(3) | PULLUDEN | PULLUP_EN | RXACTIVE},
+	{-1},
+};
+
+static struct module_pin_mux dcan0_pin_mux[] = {
+	/* DCAN0 TX */
+	{OFFSET(uart1_ctsn),   MODE(2) | PULLUDEN | PULLUP_EN},
+	/* DCAN0 RX */
+	{OFFSET(uart1_rtsn),   MODE(2) | RXACTIVE},
+	{-1},
+};
+
+static struct module_pin_mux dcan1_pin_mux[] = {
+	/* DCAN1 TX */
+	{OFFSET(uart1_rxd),   MODE(2) | PULLUDEN | PULLUP_EN},
+	/* DCAN1 RX */
+	{OFFSET(uart1_txd),   MODE(2) | RXACTIVE},
+	{-1},
+};
+
+static struct module_pin_mux gpios[] = {
+	/* GPIO0_29 (RMII1_REFCLK) - eMMC nRST */
+	{OFFSET(rmii1_refclk), (MODE(7) | PULLUDDIS)},
+	/* GPIO0_4  (SPI D1) - TA602 */
+	{OFFSET(spi0_d1), (MODE(7) | PULLUDDIS | RXACTIVE)},
+	/* GPIO0_5  (SPI CS0) - DISPLAY_ON_OFF */
+	{OFFSET(spi0_cs0), (MODE(7) | PULLUDDIS)},
+	/* GPIO0_7  (PWW0 OUT) - CAN TERM */
+	{OFFSET(ecap0_in_pwm0_out), (MODE(7) | PULLUDDIS | RXACTIVE)},
+	/* GPIO0_19 (DMA_INTR0) - CLKOUT SYS */
+	{OFFSET(xdma_event_intr0), (MODE(7) | RXACTIVE)},
+	/* GPIO0_20 (DMA_INTR1) - SPI1 nCS1 */
+	{OFFSET(xdma_event_intr1), (MODE(7) | PULLUDEN | PULLUP_EN)},
+	/* GPIO0_30 (GPMC_WAIT0) - TA601 */
+	{OFFSET(gpmc_wait0), (MODE(7) | PULLUDDIS | RXACTIVE)},
+	/* GPIO0_31 (GPMC_nWP) - SW601 PushButton */
+	{OFFSET(gpmc_wpn), (MODE(7) | PULLUDDIS | RXACTIVE)},
+	/* GPIO1_28 (GPMC_nWE) - FRAM_nWP */
+	{OFFSET(gpmc_be1n), (MODE(7) | PULLUDDIS)},
+	/* GPIO2_0  (GPMC_nCS3)	- VBAT_OK */
+	{OFFSET(gpmc_csn3), (MODE(7) | PULLUDDIS | RXACTIVE) },
+	/* GPIO2_2  (GPMC_nADV_ALE) - DCOK */
+	{OFFSET(gpmc_advn_ale), (MODE(7) | PULLUDDIS | RXACTIVE)},
+	/* GPIO2_4  (GPMC_nWE) - TST_BAST */
+	{OFFSET(gpmc_wen), (MODE(7) | PULLUDDIS)},
+	/* GPIO3_18 (MCASP0_ACLKR) - SW601 CNTup, mapped to Counter eQEB0A_in */
+	{OFFSET(mcasp0_aclkr), (MODE(1) | PULLUDDIS | RXACTIVE)},
+	/* GPIO3_19 (MCASP0_FSR) - SW601 CNTdown, mapped to Counter eQEB0B_in */
+	{OFFSET(mcasp0_fsr), (MODE(1) | PULLUDDIS | RXACTIVE)},
+	/* GPIO3_20 (MCASP0_AXR1) - SW601 CNTdown, map to Counter eQEB0_index */
+	{OFFSET(mcasp0_axr1), (MODE(1) | PULLUDDIS | RXACTIVE)},
+	{-1},
+};
+
+static struct module_pin_mux uart0_pin_mux[] = {
+	/* UART0_CTS */
+	{OFFSET(uart0_ctsn), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE)},
+	/* UART0_RXD */
+	{OFFSET(uart0_rxd), (MODE(0) | PULLUDEN | PULLUP_EN | RXACTIVE)},
+	/* UART0_TXD */
+	{OFFSET(uart0_txd), (MODE(0) | PULLUDEN)},
+	{-1},
+};
+
+static struct module_pin_mux i2c0_pin_mux[] = {
+	/* I2C_DATA */
+	{OFFSET(i2c0_sda), (MODE(0) | RXACTIVE | PULLUDEN | SLEWCTRL)},
+	/* I2C_SCLK */
+	{OFFSET(i2c0_scl), (MODE(0) | RXACTIVE | PULLUDEN | SLEWCTRL)},
+	{-1},
+};
+
+static struct module_pin_mux mii1_pin_mux[] = {
+	{OFFSET(mii1_rxerr), MODE(0) | RXACTIVE},	/* MII1_RXERR */
+	{OFFSET(mii1_txen), MODE(0)},			/* MII1_TXEN */
+	{OFFSET(mii1_rxdv), MODE(0) | RXACTIVE},	/* MII1_RXDV */
+	{OFFSET(mii1_txd3), MODE(0)},			/* MII1_TXD3 */
+	{OFFSET(mii1_txd2), MODE(0)},			/* MII1_TXD2 */
+	{OFFSET(mii1_txd1), MODE(0)},			/* MII1_TXD1 */
+	{OFFSET(mii1_txd0), MODE(0)},			/* MII1_TXD0 */
+	{OFFSET(mii1_txclk), MODE(0) | RXACTIVE},	/* MII1_TXCLK */
+	{OFFSET(mii1_rxclk), MODE(0) | RXACTIVE},	/* MII1_RXCLK */
+	{OFFSET(mii1_rxd3), MODE(0) | RXACTIVE},	/* MII1_RXD3 */
+	{OFFSET(mii1_rxd2), MODE(0) | RXACTIVE},	/* MII1_RXD2 */
+	{OFFSET(mii1_rxd1), MODE(0) | RXACTIVE},	/* MII1_RXD1 */
+	{OFFSET(mii1_rxd0), MODE(0) | RXACTIVE},	/* MII1_RXD0 */
+	{OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN}, /* MDIO_DATA */
+	{OFFSET(mdio_clk), MODE(0) | PULLUP_EN},	/* MDIO_CLK */
+	{-1},
+};
+
+static struct module_pin_mux mmc1_pin_mux[] = {
+	{OFFSET(gpmc_ad3), (MODE(1) | RXACTIVE | PULLUP_EN)},	/* MMC1_DAT3 */
+	{OFFSET(gpmc_ad2), (MODE(1) | RXACTIVE | PULLUP_EN)},	/* MMC1_DAT2 */
+	{OFFSET(gpmc_ad1), (MODE(1) | RXACTIVE | PULLUP_EN)},	/* MMC1_DAT1 */
+	{OFFSET(gpmc_ad0), (MODE(1) | RXACTIVE | PULLUP_EN)},	/* MMC1_DAT0 */
+	{OFFSET(gpmc_csn1), (MODE(2) | RXACTIVE | PULLUP_EN)},	/* MMC1_CLK */
+	{OFFSET(gpmc_csn2), (MODE(2) | RXACTIVE | PULLUP_EN)},	/* MMC1_CMD */
+	{OFFSET(gpmc_csn0), (MODE(7) | RXACTIVE | PULLUP_EN)},	/* MMC1_WP */
+	{OFFSET(gpmc_advn_ale), (MODE(7) | RXACTIVE | PULLUP_EN)},/* MMC1_CD */
+
+	{-1},
+};
+
+static struct module_pin_mux lcd_pin_mux[] = {
+	{OFFSET(lcd_data0), (MODE(0) | PULLUDDIS)},	/* LCD-Data(0) */
+	{OFFSET(lcd_data1), (MODE(0) | PULLUDDIS)},	/* LCD-Data(1) */
+	{OFFSET(lcd_data2), (MODE(0) | PULLUDDIS)},	/* LCD-Data(2) */
+	{OFFSET(lcd_data3), (MODE(0) | PULLUDDIS)},	/* LCD-Data(3) */
+	{OFFSET(lcd_data4), (MODE(0) | PULLUDDIS)},	/* LCD-Data(4) */
+	{OFFSET(lcd_data5), (MODE(0) | PULLUDDIS)},	/* LCD-Data(5) */
+	{OFFSET(lcd_data6), (MODE(0) | PULLUDDIS)},	/* LCD-Data(6) */
+	{OFFSET(lcd_data7), (MODE(0) | PULLUDDIS)},	/* LCD-Data(7) */
+	{OFFSET(lcd_data8), (MODE(0) | PULLUDDIS)},	/* LCD-Data(8) */
+	{OFFSET(lcd_data9), (MODE(0) | PULLUDDIS)},	/* LCD-Data(9) */
+	{OFFSET(lcd_data10), (MODE(0) | PULLUDDIS)},	/* LCD-Data(10) */
+	{OFFSET(lcd_data11), (MODE(0) | PULLUDDIS)},	/* LCD-Data(11) */
+	{OFFSET(lcd_data12), (MODE(0) | PULLUDDIS)},	/* LCD-Data(12) */
+	{OFFSET(lcd_data13), (MODE(0) | PULLUDDIS)},	/* LCD-Data(13) */
+	{OFFSET(lcd_data14), (MODE(0) | PULLUDDIS)},	/* LCD-Data(14) */
+	{OFFSET(lcd_data15), (MODE(0) | PULLUDDIS)},	/* LCD-Data(15) */
+
+	{OFFSET(gpmc_ad8), (MODE(1) | PULLUDDIS)},	/* LCD-Data(16) */
+	{OFFSET(gpmc_ad9), (MODE(1) | PULLUDDIS)},	/* LCD-Data(17) */
+	{OFFSET(gpmc_ad10), (MODE(1) | PULLUDDIS)},	/* LCD-Data(18) */
+	{OFFSET(gpmc_ad11), (MODE(1) | PULLUDDIS)},	/* LCD-Data(19) */
+	{OFFSET(gpmc_ad12), (MODE(1) | PULLUDDIS)},	/* LCD-Data(20) */
+	{OFFSET(gpmc_ad13), (MODE(1) | PULLUDDIS)},	/* LCD-Data(21) */
+	{OFFSET(gpmc_ad14), (MODE(1) | PULLUDDIS)},	/* LCD-Data(22) */
+	{OFFSET(gpmc_ad15), (MODE(1) | PULLUDDIS)},	/* LCD-Data(23) */
+
+	{OFFSET(lcd_vsync), (MODE(0) | PULLUDDIS)},	/* LCD-VSync */
+	{OFFSET(lcd_hsync), (MODE(0) | PULLUDDIS)},	/* LCD-HSync */
+	{OFFSET(lcd_ac_bias_en), (MODE(0) | PULLUDDIS)},/* LCD-DE */
+	{OFFSET(lcd_pclk), (MODE(0) | PULLUDDIS)},	/* LCD-CLK */
+
+	{-1},
+};
+
+void enable_uart0_pin_mux(void)
+{
+	configure_module_pin_mux(uart0_pin_mux);
+}
+
+void enable_i2c0_pin_mux(void)
+{
+	configure_module_pin_mux(i2c0_pin_mux);
+}
+
+void enable_board_pin_mux(void)
+{
+	configure_module_pin_mux(i2c0_pin_mux);
+	configure_module_pin_mux(mii1_pin_mux);
+	configure_module_pin_mux(usb0_pin_mux);
+	configure_module_pin_mux(spi1_pin_mux);
+	configure_module_pin_mux(dcan0_pin_mux);
+	configure_module_pin_mux(dcan1_pin_mux);
+	configure_module_pin_mux(mmc1_pin_mux);
+	configure_module_pin_mux(lcd_pin_mux);
+	configure_module_pin_mux(gpios);
+}
diff --git a/board/BuR/tseries/Makefile b/board/BuR/tseries/Makefile
new file mode 100644
index 0000000000..ec0d27a7aa
--- /dev/null
+++ b/board/BuR/tseries/Makefile
@@ -0,0 +1,14 @@
+#
+# Makefile
+#
+# Copyright (C) 2013 Hannes Petermaier <oe5hpm@oevsv.at>
+# Bernecker & Rainer Industrieelektronik GmbH - http://www.br-automation.com
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+ifeq ($(CONFIG_SPL_BUILD),y)
+obj-y	:= mux.o
+endif
+obj-y	+= ../common/common.o
+obj-y	+= board.o
diff --git a/board/BuR/tseries/board.c b/board/BuR/tseries/board.c
new file mode 100644
index 0000000000..f0510e599e
--- /dev/null
+++ b/board/BuR/tseries/board.c
@@ -0,0 +1,147 @@
+/*
+ * board.c
+ *
+ * Board functions for B&R LEIT Board
+ *
+ * Copyright (C) 2013 Hannes Petermaier <oe5hpm@oevsv.at>
+ * Bernecker & Rainer Industrieelektronik GmbH - http://www.br-automation.com
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ *
+ */
+
+#include <common.h>
+#include <errno.h>
+#include <spl.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/omap.h>
+#include <asm/arch/ddr_defs.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/mem.h>
+#include <asm/io.h>
+#include <asm/emif.h>
+#include <asm/gpio.h>
+#include <i2c.h>
+#include <power/tps65217.h>
+#include "../common/bur_common.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* --------------------------------------------------------------------------*/
+/* -- defines for GPIO -- */
+#define	ETHLED_ORANGE	(96+16)	/* GPIO3_16 */
+#define	REPSWITCH	(0+20)	/* GPIO0_20 */
+
+
+#if defined(CONFIG_SPL_BUILD)
+/* TODO: check ram-timing ! */
+static const struct ddr_data ddr3_data = {
+	.datardsratio0 = MT41K256M16HA125E_RD_DQS,
+	.datawdsratio0 = MT41K256M16HA125E_WR_DQS,
+	.datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE,
+	.datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA,
+};
+
+static const struct cmd_control ddr3_cmd_ctrl_data = {
+	.cmd0csratio = MT41K256M16HA125E_RATIO,
+	.cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
+
+	.cmd1csratio = MT41K256M16HA125E_RATIO,
+	.cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
+
+	.cmd2csratio = MT41K256M16HA125E_RATIO,
+	.cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
+};
+
+static struct emif_regs ddr3_emif_reg_data = {
+	.sdram_config = MT41K256M16HA125E_EMIF_SDCFG,
+	.ref_ctrl = MT41K256M16HA125E_EMIF_SDREF,
+	.sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1,
+	.sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2,
+	.sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3,
+	.zq_config = MT41K256M16HA125E_ZQ_CFG,
+	.emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY,
+};
+
+static const struct ctrl_ioregs ddr3_ioregs = {
+	.cm0ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
+	.cm1ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
+	.cm2ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
+	.dt0ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
+	.dt1ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
+};
+
+#ifdef CONFIG_SPL_OS_BOOT
+/*
+ * called from spl_nand.c
+ * return 0 for loading linux, return 1 for loading u-boot
+ */
+int spl_start_uboot(void)
+{
+	if (0 == gpio_get_value(REPSWITCH)) {
+		blink(5, 125, ETHLED_ORANGE);
+		mdelay(1000);
+		printf("SPL: entering u-boot instead kernel image.\n");
+		return 1;
+	}
+	return 0;
+}
+#endif /* CONFIG_SPL_OS_BOOT */
+
+#define OSC	(V_OSCK/1000000)
+static const struct dpll_params dpll_ddr3 = { 400, OSC-1, 1, -1, -1, -1, -1};
+
+void am33xx_spl_board_init(void)
+{
+	pmicsetup(1000);
+}
+
+const struct dpll_params *get_dpll_ddr_params(void)
+{
+	return &dpll_ddr3;
+}
+
+void sdram_init(void)
+{
+	config_ddr(400, &ddr3_ioregs,
+		   &ddr3_data,
+		   &ddr3_cmd_ctrl_data,
+		   &ddr3_emif_reg_data, 0);
+}
+#endif /* CONFIG_SPL_BUILD */
+
+/* Basic board specific setup.  Pinmux has been handled already. */
+int board_init(void)
+{
+	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+	gpmc_init();
+	return 0;
+}
+
+#ifdef CONFIG_BOARD_LATE_INIT
+int board_late_init(void)
+{
+	gpio_direction_output(ETHLED_ORANGE, 0);
+
+	if (0 == gpio_get_value(REPSWITCH)) {
+		printf("\n\n\n"
+		"!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!\n"
+		"!!!!!!! recovery switch activated !!!!!!!\n"
+		"!!!!!!!     running usbupdate     !!!!!!!\n"
+		"!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!\n\n\n");
+		setenv("bootcmd", "sleep 2; run netupdate;");
+	}
+
+	printf("turning on display power+backlight ... ");
+	tps65217_reg_write(TPS65217_PROT_LEVEL_NONE, TPS65217_WLEDCTRL1,
+			   0x09, TPS65217_MASK_ALL_BITS);	/* 200 Hz, ON */
+	tps65217_reg_write(TPS65217_PROT_LEVEL_NONE, TPS65217_WLEDCTRL2,
+			   0x62, TPS65217_MASK_ALL_BITS);	/* 100% */
+	printf("ok.\n");
+
+	return 0;
+}
+#endif /* CONFIG_BOARD_LATE_INIT */
diff --git a/board/BuR/tseries/mux.c b/board/BuR/tseries/mux.c
new file mode 100644
index 0000000000..3c76e96926
--- /dev/null
+++ b/board/BuR/tseries/mux.c
@@ -0,0 +1,225 @@
+/*
+ * mux.c
+ *
+ * Pinmux Setting for B&R LEIT Board(s)
+ *
+ * Copyright (C) 2013 Hannes Petermaier <oe5hpm@oevsv.at>
+ * Bernecker & Rainer Industrieelektronik GmbH - http://www.br-automation.com
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/mux.h>
+#include <asm/io.h>
+#include <i2c.h>
+
+static struct module_pin_mux uart0_pin_mux[] = {
+	/* UART0_CTS */
+	{OFFSET(uart0_ctsn), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE)},
+	/* UART0_RXD */
+	{OFFSET(uart0_rxd), (MODE(0) | PULLUDEN | PULLUP_EN | RXACTIVE)},
+	/* UART0_TXD */
+	{OFFSET(uart0_txd), (MODE(0) | PULLUDEN)},
+	{-1},
+};
+#ifdef CONFIG_MMC
+static struct module_pin_mux mmc1_pin_mux[] = {
+	{OFFSET(gpmc_ad3), (MODE(1) | RXACTIVE | PULLUP_EN)},	/* MMC1_DAT3 */
+	{OFFSET(gpmc_ad2), (MODE(1) | RXACTIVE | PULLUP_EN)},	/* MMC1_DAT2 */
+	{OFFSET(gpmc_ad1), (MODE(1) | RXACTIVE | PULLUP_EN)},	/* MMC1_DAT1 */
+	{OFFSET(gpmc_ad0), (MODE(1) | RXACTIVE | PULLUP_EN)},	/* MMC1_DAT0 */
+	{OFFSET(gpmc_csn1), (MODE(2) | RXACTIVE | PULLUP_EN)},	/* MMC1_CLK */
+	{OFFSET(gpmc_csn2), (MODE(2) | RXACTIVE | PULLUP_EN)},	/* MMC1_CMD */
+	{OFFSET(gpmc_csn0), (MODE(7) | RXACTIVE | PULLUP_EN)},	/* MMC1_WP */
+	{OFFSET(gpmc_advn_ale), (MODE(7) | RXACTIVE | PULLUP_EN)},/* MMC1_CD */
+	{-1},
+};
+#endif
+static struct module_pin_mux i2c0_pin_mux[] = {
+	/* I2C_DATA */
+	{OFFSET(i2c0_sda), (MODE(0) | RXACTIVE | PULLUDEN | SLEWCTRL)},
+	/* I2C_SCLK */
+	{OFFSET(i2c0_scl), (MODE(0) | RXACTIVE | PULLUDEN | SLEWCTRL)},
+	{-1},
+};
+
+static struct module_pin_mux spi0_pin_mux[] = {
+	/* SPI0_SCLK */
+	{OFFSET(spi0_sclk), (MODE(0) | RXACTIVE | PULLUDEN | PULLUP_EN)},
+	/* SPI0_D0 */
+	{OFFSET(spi0_d0), (MODE(0) | RXACTIVE |	PULLUDEN | PULLUP_EN)},
+	/* SPI0_D1 */
+	{OFFSET(spi0_d1), (MODE(0) | RXACTIVE | PULLUDEN | PULLUP_EN)},
+	/* SPI0_CS0 */
+	{OFFSET(spi0_cs0), (MODE(0) | RXACTIVE | PULLUDEN | PULLUP_EN)},
+	{-1},
+};
+
+static struct module_pin_mux mii1_pin_mux[] = {
+	{OFFSET(mii1_rxerr), MODE(0) | RXACTIVE},	/* MII1_RXERR */
+	{OFFSET(mii1_txen), MODE(0)},			/* MII1_TXEN */
+	{OFFSET(mii1_rxdv), MODE(0) | RXACTIVE},	/* MII1_RXDV */
+	{OFFSET(mii1_txd3), MODE(0)},			/* MII1_TXD3 */
+	{OFFSET(mii1_txd2), MODE(0)},			/* MII1_TXD2 */
+	{OFFSET(mii1_txd1), MODE(0)},			/* MII1_TXD1 */
+	{OFFSET(mii1_txd0), MODE(0)},			/* MII1_TXD0 */
+	{OFFSET(mii1_txclk), MODE(0) | RXACTIVE},	/* MII1_TXCLK */
+	{OFFSET(mii1_rxclk), MODE(0) | RXACTIVE},	/* MII1_RXCLK */
+	{OFFSET(mii1_rxd3), MODE(0) | RXACTIVE},	/* MII1_RXD3 */
+	{OFFSET(mii1_rxd2), MODE(0) | RXACTIVE},	/* MII1_RXD2 */
+	{OFFSET(mii1_rxd1), MODE(0) | RXACTIVE},	/* MII1_RXD1 */
+	{OFFSET(mii1_rxd0), MODE(0) | RXACTIVE},	/* MII1_RXD0 */
+	{OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN},/* MDIO_DATA */
+	{OFFSET(mdio_clk), MODE(0) | PULLUP_EN},	/* MDIO_CLK */
+	{-1},
+};
+
+static struct module_pin_mux mii2_pin_mux[] = {
+	{OFFSET(gpmc_a0), MODE(1)},		/* MII2_TXEN */
+	{OFFSET(gpmc_a1), MODE(1) | RXACTIVE},	/* MII2_RXDV */
+	{OFFSET(gpmc_a2), MODE(1)},		/* MII2_TXD3 */
+	{OFFSET(gpmc_a3), MODE(1)},		/* MII2_TXD2 */
+	{OFFSET(gpmc_a4), MODE(1)},		/* MII2_TXD1 */
+	{OFFSET(gpmc_a5), MODE(1)},		/* MII2_TXD0 */
+	{OFFSET(gpmc_a6), MODE(1) | RXACTIVE},	/* MII2_TXCLK */
+	{OFFSET(gpmc_a7), MODE(1) | RXACTIVE},	/* MII2_RXCLK */
+	{OFFSET(gpmc_a8), MODE(1) | RXACTIVE},	/* MII2_RXD3 */
+	{OFFSET(gpmc_a9), MODE(1) | RXACTIVE},	/* MII2_RXD2 */
+	{OFFSET(gpmc_a10), MODE(1) | RXACTIVE},	/* MII2_RXD1 */
+	{OFFSET(gpmc_a11), MODE(1) | RXACTIVE},	/* MII2_RXD0 */
+	{OFFSET(gpmc_wpn), (MODE(1) | RXACTIVE)},/* MII2_RXERR */
+						/*
+						 * MII2_CRS is shared with
+						 * NAND_WAIT0
+						 */
+	{OFFSET(gpmc_be1n), (MODE(1) | RXACTIVE)},/* MII1_COL */
+	{-1},
+};
+#ifdef CONFIG_NAND
+static struct module_pin_mux nand_pin_mux[] = {
+	{OFFSET(gpmc_ad0), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* NAND AD0 */
+	{OFFSET(gpmc_ad1), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* NAND AD1 */
+	{OFFSET(gpmc_ad2), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* NAND AD2 */
+	{OFFSET(gpmc_ad3), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* NAND AD3 */
+	{OFFSET(gpmc_ad4), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* NAND AD4 */
+	{OFFSET(gpmc_ad5), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* NAND AD5 */
+	{OFFSET(gpmc_ad6), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* NAND AD6 */
+	{OFFSET(gpmc_ad7), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* NAND AD7 */
+	{OFFSET(gpmc_wait0), (MODE(0) | RXACTIVE | PULLUP_EN)},	/* NAND WAIT */
+	{OFFSET(gpmc_wpn), (MODE(7) | PULLUP_EN | RXACTIVE)},	/* NAND_WPN */
+	{OFFSET(gpmc_csn0), (MODE(0) | PULLUDEN)},	/* NAND_CS0 */
+	{OFFSET(gpmc_advn_ale), (MODE(0) | PULLUDEN)},	/* NAND_ADV_ALE */
+	{OFFSET(gpmc_oen_ren), (MODE(0) | PULLUDEN)},	/* NAND_OE */
+	{OFFSET(gpmc_wen), (MODE(0) | PULLUDEN)},	/* NAND_WEN */
+	{OFFSET(gpmc_be0n_cle), (MODE(0) | PULLUDEN)},	/* NAND_BE_CLE */
+	{-1},
+};
+#endif
+static struct module_pin_mux gpIOs[] = {
+	/* GPIO0_6  (SPI0_CS1) - 3v3_PWR_nEN (Display Power Supply) */
+	{OFFSET(spi0_cs1),  (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE)},
+	/* TIMER5   (MMC0_DAT3) - TIMER5 (Buzzer) */
+	{OFFSET(mmc0_dat3), (MODE(3) | PULLUDEN | RXACTIVE)},
+	/* TIMER6   (MMC0_DAT2) - PWM_BACK_3V3, later used as MODE3 for PWM */
+	{OFFSET(mmc0_dat2), (MODE(7) | PULLUDEN | RXACTIVE)},
+	/* GPIO2_28 (MMC0_DAT1)	 - MII_nNAND */
+	{OFFSET(mmc0_dat1), (MODE(7) | PULLUDEN | RXACTIVE)},
+	/* GPIO2_29 (MMC0_DAT0)	 - NAND_1n0 */
+	{OFFSET(mmc0_dat0), (MODE(7) | PULLUDEN | RXACTIVE)},
+	/* GPIO2_30 (MMC0_CLK) - nRESET (PHY) */
+	{OFFSET(mmc0_clk), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE)},
+	/* GPIO3_18 (MCASP0_ACLKR) - CPLD JTAG TDI */
+	{OFFSET(mcasp0_aclkr), (MODE(7) | PULLUDEN | PULLUP_EN  | RXACTIVE)},
+	/* GPIO3_19 (MCASP0_FSR) - CPLD JTAG TMS */
+	{OFFSET(mcasp0_fsr), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE)},
+	/* GPIO3_20 (MCASP0_AXR1) - CPLD JTAG TCK */
+	{OFFSET(mcasp0_axr1), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE)},
+	/* GPIO3_21 (MCASP0_AHCLKX) - CPLD JTAG TDO */
+	{OFFSET(mcasp0_ahclkx), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE)},
+	/* GPIO2_0  (GPMC_nCS3) - DCOK */
+	{OFFSET(gpmc_csn3), (MODE(7) | PULLUDDIS | RXACTIVE) },
+	/* GPIO0_29 (RMII1_REFCLK) - eMMC nRST */
+	{OFFSET(rmii1_refclk), (MODE(7) | PULLUDDIS | RXACTIVE) },
+	/*
+	 * GPIO0_7 (PWW0 OUT)
+	 * DISPLAY_ONOFF (Backlight Enable at LVDS Versions)
+	 */
+	{OFFSET(ecap0_in_pwm0_out), (MODE(7) | PULLUDEN | RXACTIVE)},
+	/* GPIO0_19 (DMA_INTR0) - ISPLAY_MODE (CPLD) */
+	{OFFSET(xdma_event_intr0), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE)},
+	/* GPIO0_20 (DMA_INTR1) - REP-Switch */
+	{OFFSET(xdma_event_intr1), (MODE(7) | PULLUP_EN | RXACTIVE)},
+	/* GPIO3_14 (MCASP0_ACLKX) - frei / PP709 */
+	{OFFSET(mcasp0_aclkx), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE) },
+	/* GPIO3_15 (MCASP0_FSX) - PMIC_nRESET */
+	{OFFSET(mcasp0_fsx),   (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE) },
+	/* GPIO3_16 (MCASP0_AXR0) - ETH1_LEDY */
+	{OFFSET(mcasp0_axr0),  (MODE(7) | PULLUDDIS) },
+	/* GPIO3_17 (MCASP0_AHCLKR) - ETH2_LEDY */
+	{OFFSET(mcasp0_ahclkr), (MODE(7) | PULLUDDIS) },
+
+	{-1},
+};
+
+static struct module_pin_mux lcd_pin_mux[] = {
+	{OFFSET(lcd_data0), (MODE(0) | PULLUDDIS)},	/* LCD-Data(0) */
+	{OFFSET(lcd_data1), (MODE(0) | PULLUDDIS)},	/* LCD-Data(1) */
+	{OFFSET(lcd_data2), (MODE(0) | PULLUDDIS)},	/* LCD-Data(2) */
+	{OFFSET(lcd_data3), (MODE(0) | PULLUDDIS)},	/* LCD-Data(3) */
+	{OFFSET(lcd_data4), (MODE(0) | PULLUDDIS)},	/* LCD-Data(4) */
+	{OFFSET(lcd_data5), (MODE(0) | PULLUDDIS)},	/* LCD-Data(5) */
+	{OFFSET(lcd_data6), (MODE(0) | PULLUDDIS)},	/* LCD-Data(6) */
+	{OFFSET(lcd_data7), (MODE(0) | PULLUDDIS)},	/* LCD-Data(7) */
+	{OFFSET(lcd_data8), (MODE(0) | PULLUDDIS)},	/* LCD-Data(8) */
+	{OFFSET(lcd_data9), (MODE(0) | PULLUDDIS)},	/* LCD-Data(9) */
+	{OFFSET(lcd_data10), (MODE(0) | PULLUDDIS)},	/* LCD-Data(10) */
+	{OFFSET(lcd_data11), (MODE(0) | PULLUDDIS)},	/* LCD-Data(11) */
+	{OFFSET(lcd_data12), (MODE(0) | PULLUDDIS)},	/* LCD-Data(12) */
+	{OFFSET(lcd_data13), (MODE(0) | PULLUDDIS)},	/* LCD-Data(13) */
+	{OFFSET(lcd_data14), (MODE(0) | PULLUDDIS)},	/* LCD-Data(14) */
+	{OFFSET(lcd_data15), (MODE(0) | PULLUDDIS)},	/* LCD-Data(15) */
+
+	{OFFSET(gpmc_ad8), (MODE(1) | PULLUDDIS)},	/* LCD-Data(16) */
+	{OFFSET(gpmc_ad9), (MODE(1) | PULLUDDIS)},	/* LCD-Data(17) */
+	{OFFSET(gpmc_ad10), (MODE(1) | PULLUDDIS)},	/* LCD-Data(18) */
+	{OFFSET(gpmc_ad11), (MODE(1) | PULLUDDIS)},	/* LCD-Data(19) */
+	{OFFSET(gpmc_ad12), (MODE(1) | PULLUDDIS)},	/* LCD-Data(20) */
+	{OFFSET(gpmc_ad13), (MODE(1) | PULLUDDIS)},	/* LCD-Data(21) */
+	{OFFSET(gpmc_ad14), (MODE(1) | PULLUDDIS)},	/* LCD-Data(22) */
+	{OFFSET(gpmc_ad15), (MODE(1) | PULLUDDIS)},	/* LCD-Data(23) */
+
+	{OFFSET(lcd_vsync), (MODE(0) | PULLUDDIS)},	/* LCD-VSync */
+	{OFFSET(lcd_hsync), (MODE(0) | PULLUDDIS)},	/* LCD-HSync */
+	{OFFSET(lcd_ac_bias_en), (MODE(0) | PULLUDDIS)},/* LCD-DE */
+	{OFFSET(lcd_pclk), (MODE(0) | PULLUDDIS)},	/* LCD-CLK */
+
+	{-1},
+};
+
+void enable_uart0_pin_mux(void)
+{
+	configure_module_pin_mux(uart0_pin_mux);
+}
+
+void enable_i2c0_pin_mux(void)
+{
+	configure_module_pin_mux(i2c0_pin_mux);
+}
+
+void enable_board_pin_mux(void)
+{
+	configure_module_pin_mux(i2c0_pin_mux);
+	configure_module_pin_mux(mii1_pin_mux);
+	configure_module_pin_mux(mii2_pin_mux);
+#ifdef CONFIG_NAND
+	configure_module_pin_mux(nand_pin_mux);
+#elif defined(CONFIG_MMC)
+	configure_module_pin_mux(mmc1_pin_mux);
+#endif
+	configure_module_pin_mux(spi0_pin_mux);
+	configure_module_pin_mux(lcd_pin_mux);
+	configure_module_pin_mux(gpIOs);
+}
diff --git a/board/BuS/eb_cpu5282/Makefile b/board/BuS/eb_cpu5282/Makefile
index e7f4fb63b0..3eb7278988 100644
--- a/board/BuS/eb_cpu5282/Makefile
+++ b/board/BuS/eb_cpu5282/Makefile
@@ -5,24 +5,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	= $(BOARD).o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	= eb_cpu5282.o
diff --git a/board/BuS/eb_cpux9k2/Makefile b/board/BuS/eb_cpux9k2/Makefile
index d69195e1b6..b2ec389ab9 100644
--- a/board/BuS/eb_cpux9k2/Makefile
+++ b/board/BuS/eb_cpux9k2/Makefile
@@ -5,24 +5,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	:= cpux9k2.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
-	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	:= cpux9k2.o
diff --git a/board/BuS/vl_ma2sc/Makefile b/board/BuS/vl_ma2sc/Makefile
index 821c1a0ecb..d4b24ac8c2 100644
--- a/board/BuS/vl_ma2sc/Makefile
+++ b/board/BuS/vl_ma2sc/Makefile
@@ -9,24 +9,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS += vl_ma2sc.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
-	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y += vl_ma2sc.o
diff --git a/board/BuS/vl_ma2sc/vl_ma2sc.c b/board/BuS/vl_ma2sc/vl_ma2sc.c
index e2ae6fde6c..da39c86258 100644
--- a/board/BuS/vl_ma2sc/vl_ma2sc.c
+++ b/board/BuS/vl_ma2sc/vl_ma2sc.c
@@ -8,15 +8,15 @@
 
 #include <config.h>
 #include <common.h>
-#include <asm/sizes.h>
+#include <linux/sizes.h>
 #include <asm/io.h>
+#include <asm/gpio.h>
 #include <asm/arch/hardware.h>
 #include <asm/arch/clk.h>
 #include <asm/arch/at91_matrix.h>
 #include <asm/arch/at91sam9_smc.h>
 #include <asm/arch/at91_pmc.h>
 #include <asm/arch/at91_pio.h>
-#include <asm/arch/at91_rstc.h>
 #include <asm/arch/at91sam9263.h>
 #include <asm/arch/gpio.h>
 #include <asm/arch/at91_common.h>
@@ -66,35 +66,22 @@ static void vl_ma2sc_nand_hw_init(void)
 
 	/* Configure RDY/BSY */
 #ifdef CONFIG_SYS_NAND_READY_PIN
-	at91_set_pio_input(CONFIG_SYS_NAND_READY_PIN, 1);
+	gpio_direction_input(CONFIG_SYS_NAND_READY_PIN);
 #endif
 	/* Enable NandFlash */
-	at91_set_pio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
+	gpio_direction_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
 }
 #endif
 
 #ifdef CONFIG_MACB
 static void vl_ma2sc_macb_hw_init(void)
 {
-	unsigned long	erstl;
 	at91_pmc_t	*pmc	= (at91_pmc_t *) ATMEL_BASE_PMC;
-	at91_rstc_t	*rstc	= (at91_rstc_t *) ATMEL_BASE_RSTC;
+
 	/* Enable clock */
 	writel(1 << ATMEL_ID_EMAC, &pmc->pcer);
 
-	erstl = readl(&rstc->mr) & AT91_RSTC_MR_ERSTL_MASK;
-
-	/* Need to reset PHY -> 500ms reset */
-	writel(AT91_RSTC_KEY | AT91_RSTC_MR_ERSTL(0x0D) |
-		AT91_RSTC_MR_URSTEN, &rstc->mr);
-
-	writel(AT91_RSTC_KEY | AT91_RSTC_CR_EXTRST, &rstc->cr);
-	/* Wait for end hardware reset */
-	while (!(readl(&rstc->sr) & AT91_RSTC_SR_NRSTL))
-		;
-
-	/* Restore NRST value */
-	writel(AT91_RSTC_KEY | erstl | AT91_RSTC_MR_URSTEN, &rstc->mr);
+	at91_phy_reset();
 
 	at91_macb_hw_init();
 }
diff --git a/board/CarMediaLab/flea3/Makefile b/board/CarMediaLab/flea3/Makefile
index 82a2208c15..f34be748c2 100644
--- a/board/CarMediaLab/flea3/Makefile
+++ b/board/CarMediaLab/flea3/Makefile
@@ -6,31 +6,5 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	:= flea3.o
-SOBJS	:= lowlevel_init.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
-	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
-
-clean:
-	rm -f $(SOBJS) $(OBJS)
-
-distclean:	clean
-	rm -f $(LIB) core *.bak .depend
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	:= flea3.o
+obj-y	+= lowlevel_init.o
diff --git a/board/LEOX/elpt860/Makefile b/board/LEOX/elpt860/Makefile
index 0268f9ce48..b811adbf00 100644
--- a/board/LEOX/elpt860/Makefile
+++ b/board/LEOX/elpt860/Makefile
@@ -1,4 +1,3 @@
-
 #######################################################################
 #
 # Copyright (C) 2000, 2001, 2002, 2003
@@ -19,24 +18,4 @@
 #
 #######################################################################
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	= $(BOARD).o flash.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	= elpt860.o flash.o
diff --git a/board/LEOX/elpt860/u-boot.lds b/board/LEOX/elpt860/u-boot.lds
index f9c2bebd2d..c5e57ec03b 100644
--- a/board/LEOX/elpt860/u-boot.lds
+++ b/board/LEOX/elpt860/u-boot.lds
@@ -30,11 +30,10 @@ SECTIONS
 
     arch/powerpc/cpu/mpc8xx/start.o	(.text*)
     arch/powerpc/cpu/mpc8xx/traps.o	(.text*)
-    common/libcommon.o			(.text*)
-    arch/powerpc/cpu/mpc8xx/libmpc8xx.o	(.text*)
-    board/LEOX/elpt860/libelpt860.o	(.text*)
-    arch/powerpc/lib/libpowerpc.o	(.text*)
-/*    drivers/rtc/librtc.o		(.text*)	*/
+    common/built-in.o			(.text*)
+    arch/powerpc/cpu/mpc8xx/built-in.o	(.text*)
+    board/LEOX/elpt860/built-in.o	(.text*)
+    arch/powerpc/lib/built-in.o		(.text*)
 
     . = env_offset;
     common/env_embedded.o		(.text*)
diff --git a/board/LaCie/edminiv2/Makefile b/board/LaCie/edminiv2/Makefile
index 482f118185..035f6865d9 100644
--- a/board/LaCie/edminiv2/Makefile
+++ b/board/LaCie/edminiv2/Makefile
@@ -9,26 +9,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-ifneq ($(OBJTREE),$(SRCTREE))
-$(shell mkdir -p $(obj)../common)
-endif
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	:= edminiv2.o ../common/common.o
-
-SRCS	:= $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	:= edminiv2.o ../common/common.o
diff --git a/board/LaCie/net2big_v2/Makefile b/board/LaCie/net2big_v2/Makefile
index ad402318ff..f3074af256 100644
--- a/board/LaCie/net2big_v2/Makefile
+++ b/board/LaCie/net2big_v2/Makefile
@@ -9,36 +9,7 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-ifneq ($(OBJTREE),$(SRCTREE))
-$(shell mkdir -p $(obj)../common)
-endif
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	:= $(BOARD).o ../common/common.o
+obj-y	:= net2big_v2.o ../common/common.o
 ifneq ($(and $(CONFIG_KIRKWOOD_GPIO),$(CONFIG_NET2BIG_V2)),)
-COBJS	+= ../common/cpld-gpio-bus.o
+obj-y	+= ../common/cpld-gpio-bus.o
 endif
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
-	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
-
-clean:
-	rm -f $(SOBJS) $(OBJS)
-
-distclean:	clean
-	rm -f $(LIB) core *.bak .depend
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
diff --git a/board/LaCie/netspace_v2/Makefile b/board/LaCie/netspace_v2/Makefile
index a65b96506f..47778d8472 100644
--- a/board/LaCie/netspace_v2/Makefile
+++ b/board/LaCie/netspace_v2/Makefile
@@ -9,27 +9,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-ifneq ($(OBJTREE),$(SRCTREE))
-$(shell mkdir -p $(obj)../common)
-endif
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	:= $(BOARD).o ../common/common.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
-	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	:= netspace_v2.o ../common/common.o
diff --git a/board/LaCie/wireless_space/Makefile b/board/LaCie/wireless_space/Makefile
index a65b96506f..90a84f4892 100644
--- a/board/LaCie/wireless_space/Makefile
+++ b/board/LaCie/wireless_space/Makefile
@@ -9,27 +9,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-ifneq ($(OBJTREE),$(SRCTREE))
-$(shell mkdir -p $(obj)../common)
-endif
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	:= $(BOARD).o ../common/common.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
-	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	:= wireless_space.o ../common/common.o
diff --git a/board/Marvell/aspenite/Makefile b/board/Marvell/aspenite/Makefile
index 1ba7e2a05a..726d0e43d5 100644
--- a/board/Marvell/aspenite/Makefile
+++ b/board/Marvell/aspenite/Makefile
@@ -7,24 +7,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB     = $(obj)lib$(BOARD).o
-
-COBJS	:= aspenite.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
-	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	:= aspenite.o
diff --git a/board/Marvell/common/serial.c b/board/Marvell/common/serial.c
index 56ba0daa05..752492fc7d 100644
--- a/board/Marvell/common/serial.c
+++ b/board/Marvell/common/serial.c
@@ -20,7 +20,6 @@
 #include <linux/compiler.h>
 
 #include "../include/memory.h"
-#include "serial.h"
 
 #ifdef CONFIG_DB64360
 #include "../db64360/mpsc.h"
diff --git a/board/Marvell/common/serial.h b/board/Marvell/common/serial.h
deleted file mode 100644
index 264e2d236e..0000000000
--- a/board/Marvell/common/serial.h
+++ /dev/null
@@ -1,73 +0,0 @@
-/*
- * (C) Copyright 2001
- * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
- *
- * modified for marvell db64360 eval board by
- * Ingo Assmus <ingo.assmus@keymile.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-/* serial.h - mostly useful for DUART serial_init in serial.c */
-
-#ifndef __SERIAL_H__
-#define __SERIAL_H__
-
-#if 0
-
-#define B230400         1
-#define B115200         2
-#define B57600          4
-#define B38400          82
-#define B19200          163
-#define B9600           24
-#define B4800           651
-#define B2400           1302
-#define B1200           2604
-#define B600            5208
-#define B300            10417
-#define B150            20833
-#define B110            28409
-#define BDEFAULT        B115200
-
-				/* this stuff is important to initialize
-				the DUART channels */
-
-#define	Scale		0x01L		/* distance between port addresses */
-#define	COM1		0x000003f8		/* Keyboard */
-#define COM2		0x000002f8		/* Host */
-
-
-/* Port Definitions relative to base COM port addresses */
-#define DataIn	(0x00*Scale)	/* data input port */
-#define DataOut	(0x00*Scale)	/* data output port */
-#define BaudLsb	(0x00*Scale)	/* baud rate divisor least significant byte */
-#define BaudMsb	(0x01*Scale)	/* baud rate divisor most significant byte */
-#define	Ier	(0x01*Scale)	/* interrupt enable register */
-#define	Iir	(0x02*Scale)	/* interrupt identification register */
-#define	Lcr	(0x03*Scale)	/* line control register */
-#define	Mcr	(0x04*Scale)	/* modem control register */
-#define	Lsr	(0x05*Scale)	/* line status register */
-#define	Msr	(0x06*Scale)	/* modem status register */
-
-/* Bit Definitions for above ports */
-#define LcrDlab	0x80	/* b7:	 enable baud rate divisor registers */
-#define	LcrDflt	0x03	/* b6-0: no parity, 1 stop, 8 data */
-
-#define	McrRts	0x02	/* b1:	request to send (I am ready to xmit) */
-#define	McrDtr	0x01	/* b0:	data terminal ready (I am alive ready to rcv) */
-#define	McrDflt	(McrRts|McrDtr)
-
-#define LsrTxD	0x6000	/* b5: transmit holding register empty (i.e. xmit OK!)*/
-			/* b6: transmitter empty */
-#define LsrRxD	0x0100	/* b0: received data ready (i.e. got a byte!) */
-
-#define	MsrRi	0x0040	/* b6: ring indicator (other guy is ready to rcv) */
-#define	MsrDsr	0x0020	/* b5: data set ready (other guy is alive ready to rcv */
-#define	MsrCts	0x0010	/* b4: clear to send (other guy is ready to rcv) */
-
-#define IerRda	0xf	/* b0: Enable received data available interrupt */
-
-#endif
-
-#endif /* __SERIAL_H__ */
diff --git a/board/Marvell/db64360/Makefile b/board/Marvell/db64360/Makefile
index a5f2c54556..aefe0a789a 100644
--- a/board/Marvell/db64360/Makefile
+++ b/board/Marvell/db64360/Makefile
@@ -8,31 +8,6 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-ifneq ($(OBJTREE),$(SRCTREE))
-$(shell mkdir -p $(obj)../common)
-endif
-
-LIB	= $(obj)lib$(BOARD).o
-
-SOBJS	= ../common/misc.o
-
-COBJS	= $(BOARD).o ../common/flash.o ../common/serial.o ../common/memory.o pci.o \
+obj-y	= db64360.o ../common/flash.o ../common/serial.o ../common/memory.o pci.o \
 	  mv_eth.o ../common/ns16550.o mpsc.o ../common/i2c.o \
-	  sdram_init.o ../common/intel_flash.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
-	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+	  sdram_init.o ../common/intel_flash.o ../common/misc.o
diff --git a/board/Marvell/db64460/Makefile b/board/Marvell/db64460/Makefile
index a5f2c54556..a970f9afde 100644
--- a/board/Marvell/db64460/Makefile
+++ b/board/Marvell/db64460/Makefile
@@ -8,31 +8,6 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-ifneq ($(OBJTREE),$(SRCTREE))
-$(shell mkdir -p $(obj)../common)
-endif
-
-LIB	= $(obj)lib$(BOARD).o
-
-SOBJS	= ../common/misc.o
-
-COBJS	= $(BOARD).o ../common/flash.o ../common/serial.o ../common/memory.o pci.o \
+obj-y	+= db64460.o ../common/flash.o ../common/serial.o ../common/memory.o pci.o \
 	  mv_eth.o ../common/ns16550.o mpsc.o ../common/i2c.o \
-	  sdram_init.o ../common/intel_flash.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
-	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+	  sdram_init.o ../common/intel_flash.o ../common/misc.o
diff --git a/board/Marvell/dkb/Makefile b/board/Marvell/dkb/Makefile
index 9173154e06..9d88579120 100644
--- a/board/Marvell/dkb/Makefile
+++ b/board/Marvell/dkb/Makefile
@@ -6,24 +6,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB     = $(obj)lib$(BOARD).o
-
-COBJS	:= dkb.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
-	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	:= dkb.o
diff --git a/board/Marvell/dreamplug/Makefile b/board/Marvell/dreamplug/Makefile
index ef09f3b5d0..23e6c53184 100644
--- a/board/Marvell/dreamplug/Makefile
+++ b/board/Marvell/dreamplug/Makefile
@@ -9,30 +9,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	:= dreamplug.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
-	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
-
-clean:
-	rm -f $(SOBJS) $(OBJS)
-
-distclean:	clean
-	rm -f $(LIB) core *.bak .depend
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	:= dreamplug.o
diff --git a/board/Marvell/gplugd/Makefile b/board/Marvell/gplugd/Makefile
index 139f316ce5..b38457845d 100644
--- a/board/Marvell/gplugd/Makefile
+++ b/board/Marvell/gplugd/Makefile
@@ -12,24 +12,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB     = $(obj)lib$(BOARD).o
-
-COBJS	:= gplugd.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
-	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	:= gplugd.o
diff --git a/board/Marvell/guruplug/Makefile b/board/Marvell/guruplug/Makefile
index f835762cb4..974497a334 100644
--- a/board/Marvell/guruplug/Makefile
+++ b/board/Marvell/guruplug/Makefile
@@ -6,24 +6,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	:= guruplug.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
-	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	:= guruplug.o
diff --git a/board/Marvell/mv88f6281gtw_ge/Makefile b/board/Marvell/mv88f6281gtw_ge/Makefile
index ceb33491d9..e83bbf76e2 100644
--- a/board/Marvell/mv88f6281gtw_ge/Makefile
+++ b/board/Marvell/mv88f6281gtw_ge/Makefile
@@ -6,24 +6,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	:= mv88f6281gtw_ge.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
-	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	:= mv88f6281gtw_ge.o
diff --git a/board/Marvell/openrd/Makefile b/board/Marvell/openrd/Makefile
index f87fe7a6e9..8f95b7922e 100644
--- a/board/Marvell/openrd/Makefile
+++ b/board/Marvell/openrd/Makefile
@@ -11,24 +11,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	:= openrd.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
-	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	:= openrd.o
diff --git a/board/Marvell/rd6281a/Makefile b/board/Marvell/rd6281a/Makefile
index 67f7162c1e..cb773705e8 100644
--- a/board/Marvell/rd6281a/Makefile
+++ b/board/Marvell/rd6281a/Makefile
@@ -6,24 +6,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	:= rd6281a.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
-	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	:= rd6281a.o
diff --git a/board/Marvell/sheevaplug/Makefile b/board/Marvell/sheevaplug/Makefile
index 6ce57abd1e..e812545837 100644
--- a/board/Marvell/sheevaplug/Makefile
+++ b/board/Marvell/sheevaplug/Makefile
@@ -6,24 +6,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	:= sheevaplug.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
-	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	:= sheevaplug.o
diff --git a/board/RPXClassic/Makefile b/board/RPXClassic/Makefile
index c7c05a17e6..87db754faa 100644
--- a/board/RPXClassic/Makefile
+++ b/board/RPXClassic/Makefile
@@ -5,24 +5,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	= $(BOARD).o flash.o eccx.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	= RPXClassic.o flash.o eccx.o
diff --git a/board/RPXlite/Makefile b/board/RPXlite/Makefile
index 871865b6ee..c17cbacf32 100644
--- a/board/RPXlite/Makefile
+++ b/board/RPXlite/Makefile
@@ -5,24 +5,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	= $(BOARD).o flash.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	= RPXlite.o flash.o
diff --git a/board/RPXlite_dw/Makefile b/board/RPXlite_dw/Makefile
index 871865b6ee..eff33cff95 100644
--- a/board/RPXlite_dw/Makefile
+++ b/board/RPXlite_dw/Makefile
@@ -5,24 +5,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	= $(BOARD).o flash.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	= RPXlite_dw.o flash.o
diff --git a/board/RRvision/Makefile b/board/RRvision/Makefile
index 871865b6ee..908e8f8da5 100644
--- a/board/RRvision/Makefile
+++ b/board/RRvision/Makefile
@@ -5,24 +5,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	= $(BOARD).o flash.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	= RRvision.o flash.o
diff --git a/board/Seagate/dockstar/Makefile b/board/Seagate/dockstar/Makefile
index 1754c81733..2ef5093f06 100644
--- a/board/Seagate/dockstar/Makefile
+++ b/board/Seagate/dockstar/Makefile
@@ -9,24 +9,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	:= dockstar.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
-	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	:= dockstar.o
diff --git a/board/Seagate/goflexhome/Makefile b/board/Seagate/goflexhome/Makefile
index d97eb02186..e56230c71f 100644
--- a/board/Seagate/goflexhome/Makefile
+++ b/board/Seagate/goflexhome/Makefile
@@ -12,24 +12,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	:= goflexhome.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
-	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	:= goflexhome.o
diff --git a/board/a3000/Makefile b/board/a3000/Makefile
index e9558412e1..9b9b048be6 100644
--- a/board/a3000/Makefile
+++ b/board/a3000/Makefile
@@ -5,24 +5,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	= $(BOARD).o flash.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	= a3000.o flash.o
diff --git a/board/a3m071/Makefile b/board/a3m071/Makefile
index 5d2e4d162b..4e31e33936 100644
--- a/board/a3m071/Makefile
+++ b/board/a3m071/Makefile
@@ -2,24 +2,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	:= $(BOARD).o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	:= a3m071.o
diff --git a/board/a4m072/Makefile b/board/a4m072/Makefile
index 3acd06bba7..2a40e5799e 100644
--- a/board/a4m072/Makefile
+++ b/board/a4m072/Makefile
@@ -5,24 +5,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	:= $(BOARD).o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	:= a4m072.o
diff --git a/board/actux1/Makefile b/board/actux1/Makefile
deleted file mode 100644
index 9e581e3508..0000000000
--- a/board/actux1/Makefile
+++ /dev/null
@@ -1,28 +0,0 @@
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	:= actux1.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
diff --git a/board/actux1/actux1.c b/board/actux1/actux1.c
deleted file mode 100644
index 03ccd936b4..0000000000
--- a/board/actux1/actux1.c
+++ /dev/null
@@ -1,148 +0,0 @@
-/*
- * (C) Copyright 2007
- * Michael Schwingen, michael@schwingen.org
- *
- * (C) Copyright 2006
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * (C) Copyright 2002
- * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <command.h>
-#include <malloc.h>
-#include <asm/arch/ixp425.h>
-#include <asm/io.h>
-#include <miiphy.h>
-#ifdef CONFIG_PCI
-#include <pci.h>
-#include <asm/arch/ixp425pci.h>
-#endif
-
-#include "actux1_hw.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int board_early_init_f(void)
-{
-	/* CS5: Debug port */
-	writel(0x9d520003, IXP425_EXP_CS5);
-	/* CS6: HwRel */
-	writel(0x81860001, IXP425_EXP_CS6);
-	/* CS7: LEDs */
-	writel(0x80900003, IXP425_EXP_CS7);
-	return 0;
-}
-
-int board_init(void)
-{
-	/* adress of boot parameters */
-	gd->bd->bi_boot_params = 0x00000100;
-
-	GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_IORST);
-	GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_IORST);
-
-	/* Setup GPIOs for PCI INTA */
-	GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_PCI1_INTA);
-	GPIO_INT_ACT_LOW_SET(CONFIG_SYS_GPIO_PCI1_INTA);
-
-	/* Setup GPIOs for 33MHz clock output */
-	GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_PCI_CLK);
-	GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_EXTBUS_CLK);
-	writel(0x011001FF, IXP425_GPIO_GPCLKR);
-
-	udelay(533);
-	GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_IORST);
-
-	ACTUX1_LED1(2);
-	ACTUX1_LED2(2);
-	ACTUX1_LED3(0);
-	ACTUX1_LED4(0);
-	ACTUX1_LED5(0);
-	ACTUX1_LED6(0);
-	ACTUX1_LED7(0);
-
-	ACTUX1_HS(ACTUX1_HS_DCD);
-
-	return 0;
-}
-
-/*
- * Check Board Identity
- */
-int checkboard(void)
-{
-	char buf[64];
-	int i = getenv_f("serial#", buf, sizeof(buf));
-
-	puts("Board: AcTux-1 rev.");
-	putc(ACTUX1_BOARDREL + 'A' - 1);
-
-	if (i > 0) {
-		puts(", serial# ");
-		puts(buf);
-	}
-	putc('\n');
-
-	return 0;
-}
-
-/*************************************************************************
- * get_board_rev() - setup to pass kernel board revision information
- * 0 = reserved
- * 1 = Rev. A
- * 2 = Rev. B
- *************************************************************************/
-u32 get_board_rev(void)
-{
-	return ACTUX1_BOARDREL;
-}
-
-int dram_init(void)
-{
-	gd->ram_size = get_ram_size(CONFIG_SYS_SDRAM_BASE, 128<<20);
-	return 0;
-}
-
-
-#ifdef CONFIG_PCI
-struct pci_controller hose;
-
-void pci_init_board(void)
-{
-	pci_ixp_init(&hose);
-}
-#endif
-
-void reset_phy(void)
-{
-	u16 id1, id2;
-
-	/* initialize the PHY */
-	miiphy_reset("NPE0", CONFIG_PHY_ADDR);
-
-	miiphy_read("NPE0", CONFIG_PHY_ADDR, MII_PHYSID1, &id1);
-	miiphy_read("NPE0", CONFIG_PHY_ADDR, MII_PHYSID2, &id2);
-
-	id2 &= 0xFFF0;		/* mask out revision bits */
-
-	if (id1 == 0x13 && id2 == 0x78e0) {
-		/*
-		 * LXT971/LXT972 PHY: set LED outputs:
-		 * LED1(green) = Link/ACT,
-		 * LED2 (unused) = LINK,
-		 * LED3(red) = Coll
-		 */
-		miiphy_write("NPE0", CONFIG_PHY_ADDR, 20, 0xD432);
-	} else if (id1 == 0x143 && id2 == 0xbc30) {
-		/* BCM5241: default values are OK */
-	} else
-		printf("unknown ethernet PHY ID: %x %x\n", id1, id2);
-}
diff --git a/board/actux1/actux1_hw.h b/board/actux1/actux1_hw.h
deleted file mode 100644
index 5627f24796..0000000000
--- a/board/actux1/actux1_hw.h
+++ /dev/null
@@ -1,41 +0,0 @@
-/*
- * (C) Copyright 2007
- * Michael Schwingen, michael@schwingen.org
- *
- * hardware register definitions for the AcTux-1 board.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef _ACTUX1_HW_H
-#define _ACTUX1_HW_H
-
-/* 0 = LED off,1 = green, 2 = red, 3 = orange */
-#define ACTUX1_LED1(a)	writeb((a),   IXP425_EXP_BUS_CS7_BASE_PHYS + 0)
-#define ACTUX1_LED2(a)	writeb((a),   IXP425_EXP_BUS_CS7_BASE_PHYS + 1)
-#define ACTUX1_LED3(a)	writeb((a),   IXP425_EXP_BUS_CS7_BASE_PHYS + 2)
-#define ACTUX1_LED4(a)	writeb((a)^3, IXP425_EXP_BUS_CS7_BASE_PHYS + 3)
-#define ACTUX1_LED5(a)	writeb((a)^3, IXP425_EXP_BUS_CS7_BASE_PHYS + 4)
-#define ACTUX1_LED6(a)	writeb((a)^3, IXP425_EXP_BUS_CS7_BASE_PHYS + 5)
-#define ACTUX1_LED7(a)	writeb((a)^3, IXP425_EXP_BUS_CS7_BASE_PHYS + 6)
-#define ACTUX1_HS(a)	writeb((a),   IXP425_EXP_BUS_CS7_BASE_PHYS + 7)
-#define ACTUX1_HS_DCD	0x01
-#define ACTUX1_HS_DSR	0x02
-
-#define ACTUX1_DBG_PORT	IXP425_EXP_BUS_CS5_BASE_PHYS
-#define ACTUX1_BOARDREL	(readb(IXP425_EXP_BUS_CS6_BASE_PHYS) & 0x0F)
-
-/* GPIO settings */
-#define CONFIG_SYS_GPIO_PCI1_INTA		2
-#define CONFIG_SYS_GPIO_PCI2_INTA		3
-#define CONFIG_SYS_GPIO_I2C_SDA		4
-#define CONFIG_SYS_GPIO_I2C_SCL		5
-#define CONFIG_SYS_GPIO_DBGJUMPER		9
-#define CONFIG_SYS_GPIO_BUTTON1		10
-#define CONFIG_SYS_GPIO_DBGSENSE		11
-#define CONFIG_SYS_GPIO_DTR			12
-#define CONFIG_SYS_GPIO_IORST			13	/* Out */
-#define CONFIG_SYS_GPIO_PCI_CLK		14	/* Out */
-#define CONFIG_SYS_GPIO_EXTBUS_CLK		15	/* Out */
-
-#endif
diff --git a/board/actux1/u-boot.lds b/board/actux1/u-boot.lds
deleted file mode 100644
index a656fa99d1..0000000000
--- a/board/actux1/u-boot.lds
+++ /dev/null
@@ -1,96 +0,0 @@
-/*
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-OUTPUT_FORMAT ("elf32-bigarm", "elf32-bigarm", "elf32-bigarm")
-OUTPUT_ARCH (arm)
-ENTRY (_start)
-SECTIONS
-{
-	. = 0x00000000;
-
-	. = ALIGN (4);
-	.text : {
-		*(.__image_copy_start)
-		arch/arm/cpu/ixp/start.o(.text*)
-		net/libnet.o(.text*)
-		board/actux1/libactux1.o(.text*)
-		arch/arm/cpu/ixp/libixp.o(.text*)
-		drivers/input/libinput.o(.text*)
-
-		. = env_offset;
-		common/env_embedded.o(.ppcenv)
-		*(.text*)
-	}
-
-	. = ALIGN(4);
-	.rodata : {
-		*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
-	}
-	. = ALIGN(4);
-	.data : {
-		*(.data*)
-	}
-	. = ALIGN(4);
-	.got : {
-		*(.got)
-	}
-	. =.;
-
-	. = ALIGN(4);
-	.u_boot_list : {
-		KEEP(*(SORT(.u_boot_list*)));
-	}
-
-	. = ALIGN (4);
-
-	.image_copy_end :
-	{
-		*(.__image_copy_end)
-	}
-
-	.rel_dyn_start :
-	{
-		*(.__rel_dyn_start)
-	}
-
-	.rel.dyn : {
-		*(.rel*)
-	}
-
-	.rel_dyn_end :
-	{
-		*(.__rel_dyn_end)
-	}
-
-	_end = .;
-
-/*
- * Compiler-generated __bss_start and __bss_end, see arch/arm/lib/bss.c
- * __bss_base and __bss_limit are for linker only (overlay ordering)
- */
-
-	.bss_start __rel_dyn_start (OVERLAY) : {
-		KEEP(*(.__bss_start));
-		__bss_base = .;
-	}
-
-	.bss __bss_base (OVERLAY) : {
-		*(.bss*)
-		 . = ALIGN(4);
-		 __bss_limit = .;
-	}
-	.bss_end __bss_limit (OVERLAY) : {
-		KEEP(*(.__bss_end));
-	}
-
-	/DISCARD/ : { *(.dynsym) }
-	/DISCARD/ : { *(.dynstr*) }
-	/DISCARD/ : { *(.dynamic*) }
-	/DISCARD/ : { *(.plt*) }
-	/DISCARD/ : { *(.interp*) }
-	/DISCARD/ : { *(.gnu*) }
-}
diff --git a/board/actux2/Makefile b/board/actux2/Makefile
deleted file mode 100644
index dcb2bdabac..0000000000
--- a/board/actux2/Makefile
+++ /dev/null
@@ -1,28 +0,0 @@
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	:= actux2.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
diff --git a/board/actux2/actux2.c b/board/actux2/actux2.c
deleted file mode 100644
index e578cd0996..0000000000
--- a/board/actux2/actux2.c
+++ /dev/null
@@ -1,122 +0,0 @@
-/*
- * (C) Copyright 2007
- * Michael Schwingen, michael@schwingen.org
- *
- * (C) Copyright 2006
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * (C) Copyright 2002
- * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <command.h>
-#include <malloc.h>
-#include <asm/arch/ixp425.h>
-#include <asm/io.h>
-
-#include <miiphy.h>
-
-#include "actux2_hw.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int board_early_init_f(void)
-{
-	/* CS1: IPAC-X */
-	writel(0x94d10013, IXP425_EXP_CS1);
-	/* CS5: Debug port */
-	writel(0x9d520003, IXP425_EXP_CS5);
-	/* CS6: HW release register */
-	writel(0x81860001, IXP425_EXP_CS6);
-	/* CS7: LEDs */
-	writel(0x80900003, IXP425_EXP_CS7);
-
-	return 0;
-}
-
-int board_init(void)
-{
-	/* adress of boot parameters */
-	gd->bd->bi_boot_params = 0x00000100;
-
-	GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_IORST);
-	GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_ETHRST);
-	GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_DSR);
-	GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_DCD);
-
-	GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_IORST);
-	GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_ETHRST);
-
-	GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_DSR);
-	GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_DCD);
-
-	/* Setup GPIOs for Interrupt inputs */
-	GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_DBGINT);
-	GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_ETHINT);
-
-	/* Setup GPIOs for 33MHz clock output */
-	GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_PCI_CLK);
-	GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_EXTBUS_CLK);
-	writel(0x011001FF, IXP425_GPIO_GPCLKR);
-
-	udelay(533);
-	GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_IORST);
-	GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_ETHRST);
-
-	ACTUX2_LED1(1);
-	ACTUX2_LED2(0);
-	ACTUX2_LED3(0);
-	ACTUX2_LED4(0);
-
-	return 0;
-}
-
-/*
- * Check Board Identity
- */
-int checkboard(void)
-{
-	char buf[64];
-	int i = getenv_f("serial#", buf, sizeof(buf));
-
-	puts("Board: AcTux-2 rev.");
-	putc(ACTUX2_BOARDREL + 'A' - 1);
-
-	if (i > 0) {
-		puts(", serial# ");
-		puts(buf);
-	}
-	putc('\n');
-
-	return 0;
-}
-
-int dram_init(void)
-{
-	gd->ram_size = get_ram_size(CONFIG_SYS_SDRAM_BASE, 128<<20);
-	return 0;
-}
-
-/*************************************************************************
- * get_board_rev() - setup to pass kernel board revision information
- * 0 = reserved
- * 1 = Rev. A
- * 2 = Rev. B
- *************************************************************************/
-u32 get_board_rev(void)
-{
-	return ACTUX2_BOARDREL;
-}
-
-void reset_phy(void)
-{
-	/* init IcPlus IP175C ethernet switch to native IP175C mode */
-	miiphy_write("NPE0", 29, 31, 0x175C);
-}
diff --git a/board/actux2/actux2_hw.h b/board/actux2/actux2_hw.h
deleted file mode 100644
index 57c6fa7076..0000000000
--- a/board/actux2/actux2_hw.h
+++ /dev/null
@@ -1,43 +0,0 @@
-/*
- * (C) Copyright 2007
- * Michael Schwingen, michael@schwingen.org
- *
- * hardware register definitions for the AcTux-2 board.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef _ACTUX2_HW_H
-#define _ACTUX2_HW_H
-
-/* 0 = LED off,1 = green, 2 = red, 3 = orange */
-#define ACTUX2_LED1(a)	writeb((a ? 2 : 0), IXP425_EXP_BUS_CS7_BASE_PHYS + 0)
-#define ACTUX2_LED2(a)	writeb((a ? 2 : 0), IXP425_EXP_BUS_CS7_BASE_PHYS + 1)
-#define ACTUX2_LED3(a)	writeb((a ? 0 : 2), IXP425_EXP_BUS_CS7_BASE_PHYS + 2)
-#define ACTUX2_LED4(a)	writeb((a ? 0 : 2), IXP425_EXP_BUS_CS7_BASE_PHYS + 3)
-
-#define ACTUX2_DBG_PORT	IXP425_EXP_BUS_CS5_BASE_PHYS
-#define ACTUX2_BOARDREL	(readb(IXP425_EXP_BUS_CS6_BASE_PHYS) & 0x0F)
-#define ACTUX2_OPTION	(readb(IXP425_EXP_BUS_CS6_BASE_PHYS) & 0xF0)
-
-/*
- * GPIO settings
- */
-#define CONFIG_SYS_GPIO_DBGINT			0
-#define CONFIG_SYS_GPIO_ETHINT			1
-#define CONFIG_SYS_GPIO_ETHRST			2	/* Out */
-#define CONFIG_SYS_GPIO_LED5_GN		3	/* Out */
-#define CONFIG_SYS_GPIO_UNUSED4		4
-#define CONFIG_SYS_GPIO_UNUSED5		5
-#define CONFIG_SYS_GPIO_DSR			6	/* Out */
-#define CONFIG_SYS_GPIO_DCD			7	/* Out */
-#define CONFIG_SYS_GPIO_IPAC_INT		8
-#define CONFIG_SYS_GPIO_DBGJUMPER		9
-#define CONFIG_SYS_GPIO_BUTTON1		10
-#define CONFIG_SYS_GPIO_DBGSENSE		11
-#define CONFIG_SYS_GPIO_DTR			12
-#define CONFIG_SYS_GPIO_IORST			13	/* Out */
-#define CONFIG_SYS_GPIO_PCI_CLK		14	/* Out */
-#define CONFIG_SYS_GPIO_EXTBUS_CLK		15	/* Out */
-
-#endif
diff --git a/board/actux2/u-boot.lds b/board/actux2/u-boot.lds
deleted file mode 100644
index 7a1717640a..0000000000
--- a/board/actux2/u-boot.lds
+++ /dev/null
@@ -1,96 +0,0 @@
-/*
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-OUTPUT_FORMAT ("elf32-bigarm", "elf32-bigarm", "elf32-bigarm")
-OUTPUT_ARCH (arm)
-ENTRY (_start)
-SECTIONS
-{
-	. = 0x00000000;
-
-	. = ALIGN (4);
-	.text : {
-		*(.__image_copy_start)
-		arch/arm/cpu/ixp/start.o(.text*)
-		net/libnet.o(.text*)
-		board/actux2/libactux2.o(.text*)
-		arch/arm/cpu/ixp/libixp.o(.text*)
-		drivers/input/libinput.o(.text*)
-
-		. = env_offset;
-		common/env_embedded.o(.ppcenv)
-		*(.text*)
-	}
-
-	. = ALIGN(4);
-	.rodata : {
-		*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
-	}
-	. = ALIGN(4);
-	.data : {
-		*(.data*)
-	}
-	. = ALIGN(4);
-	.got : {
-		*(.got)
-	}
-	. =.;
-
-	. = ALIGN(4);
-	.u_boot_list : {
-		KEEP(*(SORT(.u_boot_list*)));
-	}
-
-	. = ALIGN (4);
-
-	.image_copy_end :
-	{
-		*(.__image_copy_end)
-	}
-
-	.rel_dyn_start :
-	{
-		*(.__rel_dyn_start)
-	}
-
-	.rel.dyn : {
-		*(.rel*)
-	}
-
-	.rel_dyn_end :
-	{
-		*(.__rel_dyn_end)
-	}
-
-	_end = .;
-
-/*
- * Compiler-generated __bss_start and __bss_end, see arch/arm/lib/bss.c
- * __bss_base and __bss_limit are for linker only (overlay ordering)
- */
-
-	.bss_start __rel_dyn_start (OVERLAY) : {
-		KEEP(*(.__bss_start));
-		__bss_base = .;
-	}
-
-	.bss __bss_base (OVERLAY) : {
-		*(.bss*)
-		 . = ALIGN(4);
-		 __bss_limit = .;
-	}
-	.bss_end __bss_limit (OVERLAY) : {
-		KEEP(*(.__bss_end));
-	}
-
-	/DISCARD/ : { *(.dynsym) }
-	/DISCARD/ : { *(.dynstr*) }
-	/DISCARD/ : { *(.dynamic*) }
-	/DISCARD/ : { *(.plt*) }
-	/DISCARD/ : { *(.interp*) }
-	/DISCARD/ : { *(.gnu*) }
-}
diff --git a/board/actux3/Makefile b/board/actux3/Makefile
deleted file mode 100644
index effa9a1e91..0000000000
--- a/board/actux3/Makefile
+++ /dev/null
@@ -1,28 +0,0 @@
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	:= actux3.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
diff --git a/board/actux3/actux3.c b/board/actux3/actux3.c
deleted file mode 100644
index 09c803ccd4..0000000000
--- a/board/actux3/actux3.c
+++ /dev/null
@@ -1,149 +0,0 @@
-/*
- * (C) Copyright 2007
- * Michael Schwingen, michael@schwingen.org
- *
- * (C) Copyright 2006
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * (C) Copyright 2002
- * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <command.h>
-#include <malloc.h>
-#include <asm/arch/ixp425.h>
-#include <asm/io.h>
-#include <miiphy.h>
-#include "actux3_hw.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int board_early_init_f(void)
-{
-	/* CS1: IPAC-X */
-	writel(0x94d10013, IXP425_EXP_CS1);
-	/* CS5: Debug port */
-	writel(0x9d520003, IXP425_EXP_CS5);
-	/* CS6: Release/Option register */
-	writel(0x81860001, IXP425_EXP_CS6);
-	/* CS7: LEDs */
-	writel(0x80900003, IXP425_EXP_CS7);
-
-	return 0;
-}
-
-int board_init(void)
-{
-	/* adress of boot parameters */
-	gd->bd->bi_boot_params = 0x00000100;
-
-	GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_IORST);
-	GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_ETHRST);
-	GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_DSR);
-	GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_DCD);
-	GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_LED5_GN);
-	GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_LED6_RT);
-	GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_LED6_GN);
-
-	GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_IORST);
-	GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_ETHRST);
-
-	GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_DSR);
-	GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_DCD);
-
-	GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_LED5_GN);
-	GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_LED6_RT);
-	GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_LED6_GN);
-
-	/*
-	 * Setup GPIO's for Interrupt inputs
-	 */
-	GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_DBGINT);
-	GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_ETHINT);
-
-	/*
-	 * Setup GPIO's for 33MHz clock output
-	 */
-	GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_PCI_CLK);
-	GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_EXTBUS_CLK);
-	writel(0x011001FF, IXP425_GPIO_GPCLKR);
-
-	/* we need a minimum PCI reset pulse width after enabling the clock */
-	udelay(533);
-	GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_IORST);
-	GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_ETHRST);
-
-	ACTUX3_LED1_RT(1);
-	ACTUX3_LED1_GN(0);
-	ACTUX3_LED2_RT(0);
-	ACTUX3_LED2_GN(0);
-	ACTUX3_LED3_RT(0);
-	ACTUX3_LED3_GN(0);
-	ACTUX3_LED4_GN(0);
-	ACTUX3_LED5_RT(0);
-
-	return 0;
-}
-
-/*
- * Check Board Identity
- */
-int checkboard(void)
-{
-	char buf[64];
-	int i = getenv_f("serial#", buf, sizeof(buf));
-
-	puts("Board: AcTux-3 rev.");
-	putc(ACTUX3_BOARDREL + 'A' - 1);
-
-	if (i > 0) {
-		puts (", serial# ");
-		puts (buf);
-	}
-	putc('\n');
-
-	return 0;
-}
-
-/*************************************************************************
- * get_board_rev() - setup to pass kernel board revision information
- * 0 = reserved
- * 1 = Rev. A
- * 2 = Rev. B
- *************************************************************************/
-u32 get_board_rev(void)
-{
-	return ACTUX3_BOARDREL;
-}
-
-int dram_init(void)
-{
-	gd->ram_size = get_ram_size(CONFIG_SYS_SDRAM_BASE, 128<<20);
-	return 0;
-}
-
-void reset_phy(void)
-{
-	int i;
-
-	/* initialize the PHY */
-	miiphy_reset("NPE0", CONFIG_PHY_ADDR);
-
-	/* all LED outputs = Link/Act */
-	miiphy_write("NPE0", CONFIG_PHY_ADDR, 0x16, 0x0AAA);
-
-	/*
-	 * The Marvell 88E6060 switch comes up with all ports disabled.
-	 * set all ethernet switch ports to forwarding state
-	*/
-	for (i = 1; i <= 5; i++)
-		miiphy_write("NPE0", CONFIG_PHY_ADDR + 8 + i, 0x04, 0x03);
-
-}
diff --git a/board/actux3/actux3_hw.h b/board/actux3/actux3_hw.h
deleted file mode 100644
index f8acb4d060..0000000000
--- a/board/actux3/actux3_hw.h
+++ /dev/null
@@ -1,44 +0,0 @@
-/*
- * (C) Copyright 2007
- * Michael Schwingen, michael@schwingen.org
- *
- * hardware register definitions for the AcTux-3 board.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef _ACTUX3_HW_H
-#define _ACTUX3_HW_H
-
-/* 0 = LED off,1 = ON */
-#define ACTUX3_LED1_RT(a)	writeb((a), IXP425_EXP_BUS_CS7_BASE_PHYS + 0)
-#define ACTUX3_LED1_GN(a)	writeb((a), IXP425_EXP_BUS_CS7_BASE_PHYS + 1)
-#define ACTUX3_LED2_RT(a)	writeb((a), IXP425_EXP_BUS_CS7_BASE_PHYS + 2)
-#define ACTUX3_LED2_GN(a)	writeb((a), IXP425_EXP_BUS_CS7_BASE_PHYS + 3)
-#define ACTUX3_LED3_RT(a)	writeb((a), IXP425_EXP_BUS_CS7_BASE_PHYS + 4)
-#define ACTUX3_LED3_GN(a)	writeb((a), IXP425_EXP_BUS_CS7_BASE_PHYS + 5)
-#define ACTUX3_LED4_GN(a)	writeb((a)^1, IXP425_EXP_BUS_CS7_BASE_PHYS + 6)
-#define ACTUX3_LED5_RT(a)	writeb((a), IXP425_EXP_BUS_CS7_BASE_PHYS + 7)
-
-#define ACTUX3_DBG_PORT		IXP425_EXP_BUS_CS5_BASE_PHYS
-#define ACTUX3_BOARDREL		(readb(IXP425_EXP_BUS_CS6_BASE_PHYS) & 0x0F)
-#define ACTUX3_OPTION		(readb(IXP425_EXP_BUS_CS6_BASE_PHYS) & 0xF0)
-
-/* GPIO settings */
-#define CONFIG_SYS_GPIO_DBGINT			0
-#define CONFIG_SYS_GPIO_ETHINT			1
-#define CONFIG_SYS_GPIO_ETHRST			2	/* Out */
-#define CONFIG_SYS_GPIO_LED5_GN		3	/* Out */
-#define CONFIG_SYS_GPIO_LED6_RT		4	/* Out */
-#define CONFIG_SYS_GPIO_LED6_GN		5	/* Out */
-#define CONFIG_SYS_GPIO_DSR			6	/* Out */
-#define CONFIG_SYS_GPIO_DCD			7	/* Out */
-#define CONFIG_SYS_GPIO_DBGJUMPER		9
-#define CONFIG_SYS_GPIO_BUTTON1		10
-#define CONFIG_SYS_GPIO_DBGSENSE		11
-#define CONFIG_SYS_GPIO_DTR			12
-#define CONFIG_SYS_GPIO_IORST			13	/* Out */
-#define CONFIG_SYS_GPIO_PCI_CLK		14	/* Out */
-#define CONFIG_SYS_GPIO_EXTBUS_CLK		15	/* Out */
-
-#endif
diff --git a/board/actux3/u-boot.lds b/board/actux3/u-boot.lds
deleted file mode 100644
index aadfdd2f57..0000000000
--- a/board/actux3/u-boot.lds
+++ /dev/null
@@ -1,96 +0,0 @@
-/*
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-OUTPUT_FORMAT ("elf32-bigarm", "elf32-bigarm", "elf32-bigarm")
-OUTPUT_ARCH (arm)
-ENTRY (_start)
-SECTIONS
-{
-	. = 0x00000000;
-
-	. = ALIGN (4);
-	.text : {
-		*(.__image_copy_start)
-		arch/arm/cpu/ixp/start.o(.text*)
-		net/libnet.o(.text*)
-		board/actux3/libactux3.o(.text*)
-		arch/arm/cpu/ixp/libixp.o(.text*)
-		drivers/input/libinput.o(.text*)
-
-		. = env_offset;
-		common/env_embedded.o(.ppcenv)
-		*(.text*)
-	}
-
-	. = ALIGN(4);
-	.rodata : {
-		*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
-	}
-	. = ALIGN(4);
-	.data : {
-		*(.data*)
-	}
-	. = ALIGN(4);
-	.got : {
-		*(.got)
-	}
-	. =.;
-
-	. = ALIGN(4);
-	.u_boot_list : {
-		KEEP(*(SORT(.u_boot_list*)));
-	}
-
-	. = ALIGN (4);
-
-	.image_copy_end :
-	{
-		*(.__image_copy_end)
-	}
-
-	.rel_dyn_start :
-	{
-		*(.__rel_dyn_start)
-	}
-
-	.rel.dyn : {
-		*(.rel*)
-	}
-
-	.rel_dyn_end :
-	{
-		*(.__rel_dyn_end)
-	}
-
-	_end = .;
-
-/*
- * Compiler-generated __bss_start and __bss_end, see arch/arm/lib/bss.c
- * __bss_base and __bss_limit are for linker only (overlay ordering)
- */
-
-	.bss_start __rel_dyn_start (OVERLAY) : {
-		KEEP(*(.__bss_start));
-		__bss_base = .;
-	}
-
-	.bss __bss_base (OVERLAY) : {
-		*(.bss*)
-		 . = ALIGN(4);
-		__bss_limit = .;
-	}
-	.bss_end __bss_limit (OVERLAY) : {
-		KEEP(*(.__bss_end));
-	}
-
-	/DISCARD/ : { *(.dynsym) }
-	/DISCARD/ : { *(.dynstr*) }
-	/DISCARD/ : { *(.dynamic*) }
-	/DISCARD/ : { *(.plt*) }
-	/DISCARD/ : { *(.interp*) }
-	/DISCARD/ : { *(.gnu*) }
-}
diff --git a/board/actux4/Makefile b/board/actux4/Makefile
deleted file mode 100644
index b96d385300..0000000000
--- a/board/actux4/Makefile
+++ /dev/null
@@ -1,28 +0,0 @@
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	:= actux4.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
diff --git a/board/actux4/actux4.c b/board/actux4/actux4.c
deleted file mode 100644
index 81c545884e..0000000000
--- a/board/actux4/actux4.c
+++ /dev/null
@@ -1,129 +0,0 @@
-/*
- * (C) Copyright 2007
- * Michael Schwingen, michael@schwingen.org
- *
- * (C) Copyright 2006
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * (C) Copyright 2002
- * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <command.h>
-#include <malloc.h>
-#include <asm/arch/ixp425.h>
-#include <asm/io.h>
-#include <miiphy.h>
-#ifdef CONFIG_PCI
-#include <pci.h>
-#include <asm/arch/ixp425pci.h>
-#endif
-
-#include "actux4_hw.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int board_early_init_f(void)
-{
-	writel(0xbd113c42, IXP425_EXP_CS1);
-	return 0;
-}
-
-int board_init(void)
-{
-	/* adress of boot parameters */
-	gd->bd->bi_boot_params = 0x00000100;
-
-	GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_nPWRON);
-	GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_nPWRON);
-
-	GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_IORST);
-	GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_IORST);
-
-	/* led not populated on board*/
-	GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_LED3);
-	GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_LED3);
-
-	/* middle LED */
-	GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_LED2);
-	GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_LED2);
-
-	/* right LED */
-	/* weak pulldown = LED weak on */
-	GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_LED1);
-	GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_LED1);
-
-	/* Setup GPIO's for Interrupt inputs */
-	GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_USBINTA);
-	GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_USBINTB);
-	GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_USBINTC);
-	GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_RTCINT);
-	GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_PCI_INTA);
-	GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_PCI_INTB);
-
-	GPIO_INT_ACT_LOW_SET(CONFIG_SYS_GPIO_USBINTA);
-	GPIO_INT_ACT_LOW_SET(CONFIG_SYS_GPIO_USBINTB);
-	GPIO_INT_ACT_LOW_SET(CONFIG_SYS_GPIO_USBINTC);
-	GPIO_INT_ACT_LOW_SET(CONFIG_SYS_GPIO_RTCINT);
-	GPIO_INT_ACT_LOW_SET(CONFIG_SYS_GPIO_PCI_INTA);
-	GPIO_INT_ACT_LOW_SET(CONFIG_SYS_GPIO_PCI_INTB);
-
-	/* Setup GPIO's for 33MHz clock output */
-	writel(0x011001FF, IXP425_GPIO_GPCLKR);
-	GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_EXTBUS_CLK);
-	GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_PCI_CLK);
-
-	udelay(10000);
-	GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_IORST);
-	udelay(10000);
-	GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_IORST);
-	udelay(10000);
-	GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_IORST);
-
-	return 0;
-}
-
-/* Check Board Identity */
-int checkboard(void)
-{
-	puts("Board: AcTux-4\n");
-	return 0;
-}
-
-int dram_init(void)
-{
-	gd->ram_size = get_ram_size(CONFIG_SYS_SDRAM_BASE, 128<<20);
-	return 0;
-}
-
-#ifdef CONFIG_PCI
-struct pci_controller hose;
-
-void pci_init_board(void)
-{
-	pci_ixp_init(&hose);
-}
-#endif
-
-/*
- * Hardcoded flash setup:
- * Flash 0 is a non-CFI SST 39VF020 flash, 8 bit flash / 8 bit bus.
- * Flash 1 is an Intel *16 flash using the CFI driver.
- */
-ulong board_flash_get_legacy(ulong base, int banknum, flash_info_t *info)
-{
-	if (banknum == 0) {	/* non-CFI boot flash */
-		info->portwidth = 1;
-		info->chipwidth = 1;
-		info->interface = FLASH_CFI_X8;
-		return 1;
-	} else
-		return 0;
-}
diff --git a/board/actux4/actux4_hw.h b/board/actux4/actux4_hw.h
deleted file mode 100644
index b936376de9..0000000000
--- a/board/actux4/actux4_hw.h
+++ /dev/null
@@ -1,33 +0,0 @@
-/*
- * (C) Copyright 2007
- * Michael Schwingen, michael@schwingen.org
- *
- * hardware register definitions for the AcTux-4 board.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef _ACTUX4_HW_H
-#define _ACTUX4_HW_H
-
-/*
- * GPIO settings
- */
-#define CONFIG_SYS_GPIO_USBINTA		0
-#define CONFIG_SYS_GPIO_USBINTB		1
-#define CONFIG_SYS_GPIO_USBINTC		2
-#define CONFIG_SYS_GPIO_nPWRON			3	/* Out */
-#define CONFIG_SYS_GPIO_I2C_SCL		4
-#define CONFIG_SYS_GPIO_I2C_SDA		5
-#define CONFIG_SYS_GPIO_PCI_INTB		6
-#define CONFIG_SYS_GPIO_BUTTON1		7
-#define CONFIG_SYS_GPIO_LED1			8	/* Out */
-#define CONFIG_SYS_GPIO_RTCINT			9
-#define CONFIG_SYS_GPIO_LED2			10	/* Out */
-#define CONFIG_SYS_GPIO_PCI_INTA		11
-#define CONFIG_SYS_GPIO_IORST			12	/* Out */
-#define CONFIG_SYS_GPIO_LED3			13	/* Out */
-#define CONFIG_SYS_GPIO_PCI_CLK		14	/* Out */
-#define CONFIG_SYS_GPIO_EXTBUS_CLK		15	/* Out */
-
-#endif
diff --git a/board/adder/Makefile b/board/adder/Makefile
index 07fa3f3a2f..8dc505a5fe 100644
--- a/board/adder/Makefile
+++ b/board/adder/Makefile
@@ -8,24 +8,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	:= $(BOARD).o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	:= adder.o
diff --git a/board/afeb9260/Makefile b/board/afeb9260/Makefile
index dcf926c75b..e0c3cd5422 100644
--- a/board/afeb9260/Makefile
+++ b/board/afeb9260/Makefile
@@ -9,25 +9,5 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS-y	+= afeb9260.o
-COBJS-y	+= partition.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS-y))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
-	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	+= afeb9260.o
+obj-y	+= partition.o
diff --git a/board/afeb9260/afeb9260.c b/board/afeb9260/afeb9260.c
index e1b1c10d52..ea9575d413 100644
--- a/board/afeb9260/afeb9260.c
+++ b/board/afeb9260/afeb9260.c
@@ -13,7 +13,6 @@
 #include <asm/arch/at91sam9_smc.h>
 #include <asm/arch/at91_common.h>
 #include <asm/arch/at91_pmc.h>
-#include <asm/arch/at91_rstc.h>
 #include <asm/arch/gpio.h>
 #include <asm/io.h>
 #include <asm/arch/hardware.h>
@@ -67,8 +66,6 @@ static void afeb9260_macb_hw_init(void)
 {
 	struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
 	struct at91_port *pioa = (struct at91_port *)ATMEL_BASE_PIOA;
-	struct at91_rstc *rstc = (struct at91_rstc *)ATMEL_BASE_RSTC;
-	unsigned long erstl;
 
 
 	/* Enable EMAC clock */
@@ -94,20 +91,7 @@ static void afeb9260_macb_hw_init(void)
 	       pin_to_mask(AT91_PIN_PA28),
 	       &pioa->pudr);
 
-	erstl = readl(&rstc->mr) & AT91_RSTC_MR_ERSTL_MASK;
-
-	/* Need to reset PHY -> 500ms reset */
-	writel(AT91_RSTC_KEY | AT91_RSTC_MR_ERSTL(13) |
-		AT91_RSTC_MR_URSTEN, &rstc->mr);
-	writel(AT91_RSTC_KEY | AT91_RSTC_CR_EXTRST, &rstc->cr);
-
-	/* Wait for end hardware reset */
-	while (!(readl(&rstc->sr) & AT91_RSTC_SR_NRSTL))
-		;
-	/* Restore NRST value */
-	writel(AT91_RSTC_KEY | erstl | AT91_RSTC_MR_URSTEN,
-		&rstc->mr);
-
+	at91_phy_reset();
 
 	/* Re-enable pull-up */
 	writel(pin_to_mask(AT91_PIN_PA14) |
diff --git a/board/ait/cam_enc_4xx/Makefile b/board/ait/cam_enc_4xx/Makefile
index 81eb7e72de..0d03ce003e 100644
--- a/board/ait/cam_enc_4xx/Makefile
+++ b/board/ait/cam_enc_4xx/Makefile
@@ -7,24 +7,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	:= $(BOARD).o
-SOBJS	:=
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
-	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
-
-#########################################################################
-# This is for $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	:= cam_enc_4xx.o
diff --git a/board/ait/cam_enc_4xx/config.mk b/board/ait/cam_enc_4xx/config.mk
index d7e7894831..2022151309 100644
--- a/board/ait/cam_enc_4xx/config.mk
+++ b/board/ait/cam_enc_4xx/config.mk
@@ -7,9 +7,9 @@
 # (mem base + reserved)
 #
 
-UBL_CONFIG = $(SRCTREE)/board/$(BOARDDIR)/ublimage.cfg
+UBL_CONFIG = $(srctree)/board/$(BOARDDIR)/ublimage.cfg
 ifndef CONFIG_SPL_BUILD
-ALL-y += $(obj)u-boot.ubl
+ALL-y += u-boot.ubl
 else
 # as SPL_TEXT_BASE is not page-aligned, we need for some
 # linkers the -n flag (Do not page align data), to prevent
diff --git a/board/ait/cam_enc_4xx/u-boot-spl.lds b/board/ait/cam_enc_4xx/u-boot-spl.lds
index fdfbfc38a9..c0d09adf7c 100644
--- a/board/ait/cam_enc_4xx/u-boot-spl.lds
+++ b/board/ait/cam_enc_4xx/u-boot-spl.lds
@@ -48,5 +48,9 @@ SECTIONS
 	} >.sram
 
 	__image_copy_end = .;
-	_end = .;
+
+	.end :
+	{
+		*(.__end)
+	}
 }
diff --git a/board/alphaproject/ap_sh4a_4a/Makefile b/board/alphaproject/ap_sh4a_4a/Makefile
index a9ba17568e..486d0ac550 100644
--- a/board/alphaproject/ap_sh4a_4a/Makefile
+++ b/board/alphaproject/ap_sh4a_4a/Makefile
@@ -3,25 +3,5 @@
 #
 # SPDX-License-Identifier:	GPL-2.0+
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	:= ap_sh4a_4a.o
-SOBJS	:= lowlevel_init.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB): $(obj).depend $(OBJS) $(SOBJS)
-	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	:= ap_sh4a_4a.o
+obj-y	+= lowlevel_init.o
diff --git a/board/altera/nios2-generic/Makefile b/board/altera/nios2-generic/Makefile
index ceaf45eb47..84690fe04d 100644
--- a/board/altera/nios2-generic/Makefile
+++ b/board/altera/nios2-generic/Makefile
@@ -6,32 +6,8 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-ifneq ($(OBJTREE),$(SRCTREE))
-$(shell mkdir -p $(obj)../common)
-endif
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS-y	:= $(BOARD).o
-COBJS-$(CONFIG_CMD_IDE) += ../common/cfide.o
-COBJS-$(CONFIG_EPLED) += ../common/epled.o
-COBJS-$(CONFIG_SEVENSEG) += ../common/sevenseg.o
-
-SOBJS-y	:= text_base.o
-
-SRCS	:= $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS-y))
-SOBJS	:= $(addprefix $(obj),$(SOBJS-y))
-
-$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
-	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	:= nios2-generic.o
+obj-$(CONFIG_CMD_IDE) += ../common/cfide.o
+obj-$(CONFIG_EPLED) += ../common/epled.o
+obj-$(CONFIG_SEVENSEG) += ../common/sevenseg.o
+obj-y	+= text_base.o
diff --git a/board/altera/nios2-generic/config.mk b/board/altera/nios2-generic/config.mk
index f9f317c440..a673525195 100644
--- a/board/altera/nios2-generic/config.mk
+++ b/board/altera/nios2-generic/config.mk
@@ -5,11 +5,7 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-# we get text_base from board config header, so do not use this
-#CONFIG_SYS_TEXT_BASE = do-not-use-me
-
 PLATFORM_CPPFLAGS += -mno-hw-div -mno-hw-mul
-PLATFORM_CPPFLAGS += -I$(TOPDIR)/board/$(VENDOR)/include
 
 ifeq ($(debug),1)
 PLATFORM_CPPFLAGS += -DDEBUG
diff --git a/board/altera/nios2-generic/nios2-generic.c b/board/altera/nios2-generic/nios2-generic.c
index 5c5b1b9148..5ab9471246 100644
--- a/board/altera/nios2-generic/nios2-generic.c
+++ b/board/altera/nios2-generic/nios2-generic.c
@@ -8,13 +8,16 @@
 
 #include <common.h>
 #include <netdev.h>
+#if defined(CONFIG_CFI_FLASH_MTD)
 #include <mtd/cfi_flash.h>
+#endif
 #include <asm/io.h>
 #include <asm/gpio.h>
 
 void text_base_hook(void); /* nop hook for text_base.S */
 
-#if defined(CONFIG_ENV_IS_IN_FLASH) && defined(CONFIG_ENV_ADDR)
+#if defined(CONFIG_ENV_IS_IN_FLASH) && defined(CONFIG_ENV_ADDR) && \
+    defined(CONFIG_CFI_FLASH_MTD)
 static void __early_flash_cmd_reset(void)
 {
 	/* reset flash before we read env */
@@ -35,7 +38,8 @@ int board_early_init_f(void)
 			"led");
 #endif
 #endif
-#if defined(CONFIG_ENV_IS_IN_FLASH) && defined(CONFIG_ENV_ADDR)
+#if defined(CONFIG_ENV_IS_IN_FLASH) && defined(CONFIG_ENV_ADDR) && \
+    defined(CONFIG_CFI_FLASH_MTD)
 	early_flash_cmd_reset();
 #endif
 	return 0;
diff --git a/board/altera/socfpga/Makefile b/board/altera/socfpga/Makefile
index 9dc45a9456..de339ec7f7 100644
--- a/board/altera/socfpga/Makefile
+++ b/board/altera/socfpga/Makefile
@@ -6,31 +6,5 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS-y	:= socfpga_cyclone5.o
-COBJS-$(CONFIG_SPL_BUILD) += pinmux_config.o
-
-COBJS	:= $(COBJS-y)
-SRCS	:= $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-clean:
-	rm -f $(OBJS)
-
-distclean:	clean
-	rm -f $(LIB) core *.bak $(obj).depend
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	:= socfpga_cyclone5.o
+obj-$(CONFIG_SPL_BUILD) += pinmux_config.o
diff --git a/board/altera/socfpga/pll_config.h b/board/altera/socfpga/pll_config.h
new file mode 100644
index 0000000000..9bd044230b
--- /dev/null
+++ b/board/altera/socfpga/pll_config.h
@@ -0,0 +1,118 @@
+/*
+ * Copyright Altera Corporation (C) 2012-2014. All rights reserved
+ *
+ * SPDX-License-Identifier:    BSD-3-Clause
+ */
+
+/* This file is generated by Preloader Generator */
+
+#ifndef _PRELOADER_PLL_CONFIG_H_
+#define _PRELOADER_PLL_CONFIG_H_
+
+/* PLL configuration data */
+/* Main PLL */
+#define CONFIG_HPS_MAINPLLGRP_VCO_DENOM			(0)
+#define CONFIG_HPS_MAINPLLGRP_VCO_NUMER			(63)
+#define CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT		(0)
+#define CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT		(0)
+#define CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT		(0)
+#define CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT		(3)
+#define CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT	(3)
+#define CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT	(12)
+#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK		(1)
+#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK		(1)
+#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK		(1)
+#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK		(1)
+#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK		(0)
+#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGCLK		(1)
+#define CONFIG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK		(0)
+/*
+ * To tell where is the clock source:
+ * 0 = MAINPLL
+ * 1 = PERIPHPLL
+ */
+#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4MP		(1)
+#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4SP		(1)
+
+/* Peripheral PLL */
+#define CONFIG_HPS_PERPLLGRP_VCO_DENOM			(1)
+#define CONFIG_HPS_PERPLLGRP_VCO_NUMER			(79)
+/*
+ * To tell where is the VCOs source:
+ * 0 = EOSC1
+ * 1 = EOSC2
+ * 2 = F2S
+ */
+#define CONFIG_HPS_PERPLLGRP_VCO_PSRC			(0)
+#define CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT		(3)
+#define CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT		(3)
+#define CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT		(1)
+#define CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT	(4)
+#define CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT		(4)
+#define CONFIG_HPS_PERPLLGRP_S2FUSER1CLK_CNT		(9)
+#define CONFIG_HPS_PERPLLGRP_DIV_USBCLK			(0)
+#define CONFIG_HPS_PERPLLGRP_DIV_SPIMCLK		(0)
+#define CONFIG_HPS_PERPLLGRP_DIV_CAN0CLK		(1)
+#define CONFIG_HPS_PERPLLGRP_DIV_CAN1CLK		(1)
+#define CONFIG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK		(6249)
+/*
+ * To tell where is the clock source:
+ * 0 = F2S_PERIPH_REF_CLK
+ * 1 = MAIN_CLK
+ * 2 = PERIPH_CLK
+ */
+#define CONFIG_HPS_PERPLLGRP_SRC_SDMMC			(2)
+#define CONFIG_HPS_PERPLLGRP_SRC_NAND			(2)
+#define CONFIG_HPS_PERPLLGRP_SRC_QSPI			(1)
+
+/* SDRAM PLL */
+#ifdef CONFIG_SOCFPGA_ARRIA5
+/* Arria V SDRAM will run at 533MHz while Cyclone V still at 400MHz
+ * This if..else... is not required if generated by tools */
+#define CONFIG_HPS_SDRPLLGRP_VCO_DENOM			(2)
+#define CONFIG_HPS_SDRPLLGRP_VCO_NUMER			(127)
+#else
+#define CONFIG_HPS_SDRPLLGRP_VCO_DENOM			(0)
+#define CONFIG_HPS_SDRPLLGRP_VCO_NUMER			(31)
+#endif /* CONFIG_SOCFPGA_ARRIA5 */
+
+/*
+ * To tell where is the VCOs source:
+ * 0 = EOSC1
+ * 1 = EOSC2
+ * 2 = F2S
+ */
+#define CONFIG_HPS_SDRPLLGRP_VCO_SSRC			(0)
+#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_CNT		(1)
+#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE		(0)
+#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT		(0)
+#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE		(0)
+#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_CNT		(1)
+#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_PHASE		(4)
+#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT		(5)
+#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE		(0)
+
+/* Info for driver */
+#define CONFIG_HPS_CLK_OSC1_HZ			(25000000)
+#define CONFIG_HPS_CLK_MAINVCO_HZ		(1600000000)
+#define CONFIG_HPS_CLK_PERVCO_HZ		(1000000000)
+#ifdef CONFIG_SOCFPGA_ARRIA5
+/* The if..else... is not required if generated by tools */
+#define CONFIG_HPS_CLK_SDRVCO_HZ		(1066000000)
+#else
+#define CONFIG_HPS_CLK_SDRVCO_HZ		(800000000)
+#endif
+#define CONFIG_HPS_CLK_EMAC0_HZ			(250000000)
+#define CONFIG_HPS_CLK_EMAC1_HZ			(250000000)
+#define CONFIG_HPS_CLK_USBCLK_HZ		(200000000)
+#define CONFIG_HPS_CLK_NAND_HZ			(50000000)
+#define CONFIG_HPS_CLK_SDMMC_HZ			(200000000)
+#define CONFIG_HPS_CLK_QSPI_HZ			(400000000)
+#define CONFIG_HPS_CLK_SPIM_HZ			(200000000)
+#define CONFIG_HPS_CLK_CAN0_HZ			(100000000)
+#define CONFIG_HPS_CLK_CAN1_HZ			(100000000)
+#define CONFIG_HPS_CLK_GPIODB_HZ		(32000)
+#define CONFIG_HPS_CLK_L4_MP_HZ			(100000000)
+#define CONFIG_HPS_CLK_L4_SP_HZ			(100000000)
+
+#endif /* _PRELOADER_PLL_CONFIG_H_ */
diff --git a/board/altera/socfpga/socfpga_cyclone5.c b/board/altera/socfpga/socfpga_cyclone5.c
index 576066bef1..a960eb6002 100644
--- a/board/altera/socfpga/socfpga_cyclone5.c
+++ b/board/altera/socfpga/socfpga_cyclone5.c
@@ -12,6 +12,7 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
+#if defined(CONFIG_DISPLAY_CPUINFO)
 /*
  * Print CPU information
  */
@@ -20,6 +21,7 @@ int print_cpuinfo(void)
 	puts("CPU   : Altera SOCFPGA Platform\n");
 	return 0;
 }
+#endif
 
 /*
  * Print Board information
diff --git a/board/amcc/acadia/Makefile b/board/amcc/acadia/Makefile
index 06f5c6ac61..035f407275 100644
--- a/board/amcc/acadia/Makefile
+++ b/board/amcc/acadia/Makefile
@@ -5,25 +5,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	= $(BOARD).o cmd_acadia.o memory.o pll.o
-SOBJS	=
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	= acadia.o cmd_acadia.o memory.o pll.o
diff --git a/board/amcc/acadia/memory.c b/board/amcc/acadia/memory.c
index 61bfea3fab..9673118857 100644
--- a/board/amcc/acadia/memory.c
+++ b/board/amcc/acadia/memory.c
@@ -17,7 +17,6 @@
 
 extern void board_pll_init_f(void);
 
-#if !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
 static void cram_bcr_write(u32 wr_val)
 {
 	wr_val <<= 2;
@@ -41,20 +40,9 @@ static void cram_bcr_write(u32 wr_val)
 
 	return;
 }
-#endif
 
 phys_size_t initdram(int board_type)
 {
-#if defined(CONFIG_NAND_SPL)
-	u32 reg;
-
-	/* don't reinit PLL when booting via I2C bootstrap option */
-	mfsdr(SDR0_PINSTP, reg);
-	if (reg != 0xf0000000)
-		board_pll_init_f();
-#endif
-
-#if !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
 	int i;
 	u32 val;
 
@@ -88,7 +76,6 @@ phys_size_t initdram(int board_type)
 	/* Wait a short while, since for NAND booting this is too fast */
 	for (i=0; i<200000; i++)
 		;
-#endif
 
 	return (CONFIG_SYS_MBYTES_RAM << 20);
 }
diff --git a/board/amcc/acadia/pll.c b/board/amcc/acadia/pll.c
index d74b725ae5..d868582ba9 100644
--- a/board/amcc/acadia/pll.c
+++ b/board/amcc/acadia/pll.c
@@ -135,45 +135,3 @@ void board_pll_init_f(void)
 	mtcpr(CPR0_CLKUP, 0x40000000);
 }
 #endif				/* CPU_<speed>_405EZ */
-
-#if defined(CONFIG_NAND_SPL) || defined(CONFIG_SPI_SPL)
-/*
- * Get timebase clock frequency
- */
-unsigned long get_tbclk(void)
-{
-	unsigned long cpr_plld;
-	unsigned long cpr_primad;
-	unsigned long primad_cpudv;
-	unsigned long pllFbkDiv;
-	unsigned long freqProcessor;
-
-	/*
-	 * Read PLL Mode registers
-	 */
-	mfcpr(CPR0_PLLD, cpr_plld);
-
-	/*
-	 * Read CPR_PRIMAD register
-	 */
-	mfcpr(CPR0_PRIMAD, cpr_primad);
-
-	/*
-	 * Determine CPU clock frequency
-	 */
-	primad_cpudv = ((cpr_primad & PRIMAD_CPUDV_MASK) >> 24);
-	if (primad_cpudv == 0)
-		primad_cpudv = 16;
-
-	/*
-	 * Determine FBK_DIV.
-	 */
-	pllFbkDiv = ((cpr_plld & PLLD_FBDV_MASK) >> 24);
-	if (pllFbkDiv == 0)
-		pllFbkDiv = 256;
-
-	freqProcessor = (CONFIG_SYS_CLK_FREQ * pllFbkDiv) / primad_cpudv;
-
-	return (freqProcessor);
-}
-#endif /* defined(CONFIG_NAND_SPL) || defined(CONFIG_SPI_SPL) */
diff --git a/board/amcc/bamboo/Makefile b/board/amcc/bamboo/Makefile
index 6a5464d597..4c0a1253f1 100644
--- a/board/amcc/bamboo/Makefile
+++ b/board/amcc/bamboo/Makefile
@@ -5,27 +5,5 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	= $(BOARD).o flash.o
-SOBJS	= init.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-all:	$(LIB) $(SOBJS)
-
-$(LIB):	$(OBJS)
-	$(call cmd_link_o_target, $^)
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	= bamboo.o flash.o
+extra-y	+= init.o
diff --git a/board/amcc/bamboo/bamboo.c b/board/amcc/bamboo/bamboo.c
index 84bbacf4c5..c8d09636ab 100644
--- a/board/amcc/bamboo/bamboo.c
+++ b/board/amcc/bamboo/bamboo.c
@@ -16,7 +16,6 @@ void ext_bus_cntlr_init(void);
 void configure_ppc440ep_pins(void);
 int is_nand_selected(void);
 
-#if !(defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL))
 /*************************************************************************
  *
  * Bamboo has one bank onboard sdram (plus DIMM)
@@ -178,7 +177,6 @@ const unsigned char cfg_simulate_spd_eeprom[128] = {
 	0,
 	0
 };
-#endif
 
 #if 0
 {	   /* GPIO   Alternate1	      Alternate2	Alternate3 */
@@ -440,15 +438,11 @@ int checkboard(void)
 
 phys_size_t initdram (int board_type)
 {
-#if !(defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL))
 	long dram_size;
 
 	dram_size = spd_sdram();
 
 	return dram_size;
-#else
-	return CONFIG_SYS_MBYTES_SDRAM << 20;
-#endif
 }
 
 /*----------------------------------------------------------------------------+
@@ -1794,23 +1788,12 @@ void configure_ppc440ep_pins(void)
 	if (ppc440ep_core_selection[NAND_FLASH] == CORE_SELECTED)
 	{
 		update_ndfc_ios(gpio_tab);
-
-#if !(defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL))
 		mtsdr(SDR0_CUST0, SDR0_CUST0_MUX_NDFC_SEL   |
 		      SDR0_CUST0_NDFC_ENABLE	|
 		      SDR0_CUST0_NDFC_BW_8_BIT	|
 		      SDR0_CUST0_NDFC_ARE_MASK	|
 		      SDR0_CUST0_CHIPSELGAT_EN1 |
 		      SDR0_CUST0_CHIPSELGAT_EN2);
-#else
-		mtsdr(SDR0_CUST0, SDR0_CUST0_MUX_NDFC_SEL   |
-		      SDR0_CUST0_NDFC_ENABLE	|
-		      SDR0_CUST0_NDFC_BW_8_BIT	|
-		      SDR0_CUST0_NDFC_ARE_MASK	|
-		      SDR0_CUST0_CHIPSELGAT_EN0 |
-		      SDR0_CUST0_CHIPSELGAT_EN2);
-#endif
-
 		ndfc_selection_in_fpga();
 	}
 	else
diff --git a/board/amcc/bamboo/init.S b/board/amcc/bamboo/init.S
index 48dbcbe2a1..5c7c839079 100644
--- a/board/amcc/bamboo/init.S
+++ b/board/amcc/bamboo/init.S
@@ -32,12 +32,7 @@ tlbtab:
 	 * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the
 	 * speed up boot process. It is patched after relocation to enable SA_I
 	 */
-#ifndef CONFIG_NAND_SPL
 	tlbentry(CONFIG_SYS_BOOT_BASE_ADDR, SZ_256M, CONFIG_SYS_BOOT_BASE_ADDR, 0, AC_RWX | SA_G)
-#else
-	tlbentry(CONFIG_SYS_NAND_BOOT_SPL_SRC, SZ_4K, CONFIG_SYS_NAND_BOOT_SPL_SRC, 0, AC_RWX | SA_G)
-	tlbentry(CONFIG_SYS_SDRAM_BASE, SZ_256M, CONFIG_SYS_SDRAM_BASE, 0, AC_RWX | SA_IG)
-#endif
 
 	/* TLB-entry for init-ram in dcache (SA_I must be turned off!) */
 	tlbentry(CONFIG_SYS_INIT_RAM_ADDR, SZ_4K, CONFIG_SYS_INIT_RAM_ADDR, 0, AC_RWX | SA_G)
@@ -58,31 +53,3 @@ tlbtab:
 	tlbentry(CONFIG_SYS_USB_DEVICE, SZ_1K, CONFIG_SYS_USB_DEVICE, 0, AC_RW | SA_IG)
 
 	tlbtab_end
-
-#if defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
-	/*
-	 * For NAND booting the first TLB has to be reconfigured to full size
-	 * and with caching disabled after running from RAM!
-	 */
-#define TLB00	TLB0(CONFIG_SYS_BOOT_BASE_ADDR, SZ_256M)
-#define TLB01	TLB1(CONFIG_SYS_BOOT_BASE_ADDR, 0)
-#define TLB02	TLB2(AC_RWX | SA_IG)
-
-	.globl	reconfig_tlb0
-reconfig_tlb0:
-	sync
-	isync
-	addi	r4,r0,0x0000		/* TLB entry #0 */
-	lis	r5,TLB00@h
-	ori	r5,r5,TLB00@l
-	tlbwe	r5,r4,0x0000		/* Save it out */
-	lis	r5,TLB01@h
-	ori	r5,r5,TLB01@l
-	tlbwe	r5,r4,0x0001		/* Save it out */
-	lis	r5,TLB02@h
-	ori	r5,r5,TLB02@l
-	tlbwe	r5,r4,0x0002		/* Save it out */
-	sync
-	isync
-	blr
-#endif
diff --git a/board/amcc/bluestone/Makefile b/board/amcc/bluestone/Makefile
index 289b3796ad..07320ce425 100644
--- a/board/amcc/bluestone/Makefile
+++ b/board/amcc/bluestone/Makefile
@@ -5,28 +5,5 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS-y	:= $(BOARD).o
-SOBJS	:= init.o
-
-COBJS   := $(COBJS-y)
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-all:	$(LIB) $(SOBJS)
-
-$(LIB):	$(OBJS)
-	$(call cmd_link_o_target, $^)
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	:= bluestone.o
+extra-y	+= init.o
diff --git a/board/amcc/bubinga/Makefile b/board/amcc/bubinga/Makefile
index bea58a7cae..0e7ebcaedd 100644
--- a/board/amcc/bubinga/Makefile
+++ b/board/amcc/bubinga/Makefile
@@ -5,24 +5,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	= $(BOARD).o flash.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(OBJS) $(SOBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	= bubinga.o flash.o
diff --git a/board/amcc/canyonlands/Makefile b/board/amcc/canyonlands/Makefile
index 415ec3298f..ba0765fe99 100644
--- a/board/amcc/canyonlands/Makefile
+++ b/board/amcc/canyonlands/Makefile
@@ -5,29 +5,6 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS-y	:= $(BOARD).o
-COBJS-$(CONFIG_CMD_CHIP_CONFIG) += chip_config.o
-SOBJS	:= init.o
-
-COBJS   := $(COBJS-y)
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-all:	$(LIB) $(SOBJS)
-
-$(LIB):	$(OBJS)
-	$(call cmd_link_o_target, $^)
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	:= canyonlands.o
+obj-$(CONFIG_CMD_CHIP_CONFIG) += chip_config.o
+extra-y	+= init.o
diff --git a/board/amcc/canyonlands/canyonlands.c b/board/amcc/canyonlands/canyonlands.c
index cc36f4587c..79d4babe06 100644
--- a/board/amcc/canyonlands/canyonlands.c
+++ b/board/amcc/canyonlands/canyonlands.c
@@ -16,6 +16,7 @@
 #include <asm/4xx_pcie.h>
 #include <asm/ppc4xx-gpio.h>
 #include <asm/errno.h>
+#include <usb.h>
 
 extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
 
@@ -188,7 +189,7 @@ int board_early_init_f(void)
 }
 
 #if defined(CONFIG_USB_OHCI_NEW) && defined(CONFIG_SYS_USB_OHCI_BOARD_INIT)
-int usb_board_init(void)
+int board_usb_init(int index, enum usb_init_type init)
 {
 	struct board_bcsr *bcsr_data =
 		(struct board_bcsr *)CONFIG_SYS_BCSR_BASE;
@@ -229,7 +230,7 @@ int usb_board_stop(void)
 	return 0;
 }
 
-int usb_board_init_fail(void)
+int board_usb_cleanup(int index, enum usb_init_type init)
 {
 	return usb_board_stop();
 }
@@ -378,11 +379,7 @@ int board_early_init_r (void)
 	 */
 
 	/* Remap the NOR FLASH to 0xcc00.0000 ... 0xcfff.ffff */
-#if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
-	mtebc(PB3CR, CONFIG_SYS_FLASH_BASE_PHYS_L | 0xda000);
-#else
 	mtebc(PB0CR, CONFIG_SYS_FLASH_BASE_PHYS_L | 0xda000);
-#endif
 
 	/* Remove TLB entry of boot EBC mapping */
 	remove_tlb(CONFIG_SYS_BOOT_BASE_ADDR, 16 << 20);
diff --git a/board/amcc/canyonlands/init.S b/board/amcc/canyonlands/init.S
index d83cd6e754..bf00bd6bca 100644
--- a/board/amcc/canyonlands/init.S
+++ b/board/amcc/canyonlands/init.S
@@ -31,13 +31,7 @@ tlbtab:
 	 * use the speed up boot process. It is patched after relocation to
 	 * enable SA_I
 	 */
-#ifndef CONFIG_NAND_SPL
 	tlbentry(CONFIG_SYS_BOOT_BASE_ADDR, SZ_16M, CONFIG_SYS_BOOT_BASE_ADDR, 4, AC_RWX | SA_G) /* TLB 0 */
-#else
-	tlbentry(CONFIG_SYS_NAND_BOOT_SPL_SRC, SZ_4K, CONFIG_SYS_NAND_BOOT_SPL_SRC, 4, AC_RWX | SA_G)
-	tlbentry(CONFIG_SYS_SDRAM_BASE, SZ_256M, CONFIG_SYS_SDRAM_BASE, 0, AC_RWX | SA_IG)
-	tlbentry(256 << 20, SZ_256M, 256 << 20, 0, AC_RWX | SA_IG)
-#endif
 
 	/*
 	 * TLB entries for SDRAM are not needed on this platform.
@@ -95,31 +89,3 @@ tlbtab:
 #endif
 
 	tlbtab_end
-
-#if defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
-	/*
-	 * For NAND booting the first TLB has to be reconfigured to full size
-	 * and with caching disabled after running from RAM!
-	 */
-#define TLB00	TLB0(CONFIG_SYS_BOOT_BASE_ADDR, SZ_256M)
-#define TLB01	TLB1(CONFIG_SYS_BOOT_BASE_ADDR, 1)
-#define TLB02	TLB2(AC_RWX | SA_IG)
-
-	.globl	reconfig_tlb0
-reconfig_tlb0:
-	sync
-	isync
-	addi	r4,r0,0x0000		/* TLB entry #0 */
-	lis	r5,TLB00@h
-	ori	r5,r5,TLB00@l
-	tlbwe	r5,r4,0x0000		/* Save it out */
-	lis	r5,TLB01@h
-	ori	r5,r5,TLB01@l
-	tlbwe	r5,r4,0x0001		/* Save it out */
-	lis	r5,TLB02@h
-	ori	r5,r5,TLB02@l
-	tlbwe	r5,r4,0x0002		/* Save it out */
-	sync
-	isync
-	blr
-#endif
diff --git a/board/amcc/ebony/Makefile b/board/amcc/ebony/Makefile
index 553fc6b14a..5876486f58 100644
--- a/board/amcc/ebony/Makefile
+++ b/board/amcc/ebony/Makefile
@@ -5,25 +5,5 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	= $(BOARD).o flash.o
-SOBJS	= init.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(OBJS) $(SOBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	= ebony.o flash.o
+extra-y	+= init.o
diff --git a/board/amcc/katmai/Makefile b/board/amcc/katmai/Makefile
index b190ebad2a..b738defc1e 100644
--- a/board/amcc/katmai/Makefile
+++ b/board/amcc/katmai/Makefile
@@ -5,27 +5,6 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS-y	:= $(BOARD).o
-COBJS-$(CONFIG_CMD_CHIP_CONFIG) += chip_config.o
-SOBJS	= init.o
-
-COBJS   := $(COBJS-y)
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	:= katmai.o
+obj-$(CONFIG_CMD_CHIP_CONFIG) += chip_config.o
+extra-y	+= init.o
diff --git a/board/amcc/kilauea/Makefile b/board/amcc/kilauea/Makefile
index 7e7ff2747a..754dadc66a 100644
--- a/board/amcc/kilauea/Makefile
+++ b/board/amcc/kilauea/Makefile
@@ -5,25 +5,5 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS-y	:= $(BOARD).o
-COBJS-$(CONFIG_CMD_CHIP_CONFIG) += chip_config.o
-
-COBJS   := $(COBJS-y)
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS))
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	:= kilauea.o
+obj-$(CONFIG_CMD_CHIP_CONFIG) += chip_config.o
diff --git a/board/amcc/luan/Makefile b/board/amcc/luan/Makefile
index 553fc6b14a..345ad564dc 100644
--- a/board/amcc/luan/Makefile
+++ b/board/amcc/luan/Makefile
@@ -5,25 +5,5 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	= $(BOARD).o flash.o
-SOBJS	= init.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(OBJS) $(SOBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	= luan.o flash.o
+extra-y	+= init.o
diff --git a/board/amcc/makalu/Makefile b/board/amcc/makalu/Makefile
index efc4bf8530..dcf162ca98 100644
--- a/board/amcc/makalu/Makefile
+++ b/board/amcc/makalu/Makefile
@@ -5,24 +5,5 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	= $(BOARD).o cmd_pll.o
-SOBJS	= init.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS))
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	= makalu.o cmd_pll.o
+obj-y	+= init.o
diff --git a/board/amcc/ocotea/Makefile b/board/amcc/ocotea/Makefile
index 553fc6b14a..7646bbb961 100644
--- a/board/amcc/ocotea/Makefile
+++ b/board/amcc/ocotea/Makefile
@@ -5,25 +5,5 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	= $(BOARD).o flash.o
-SOBJS	= init.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(OBJS) $(SOBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	= ocotea.o flash.o
+extra-y	+= init.o
diff --git a/board/amcc/redwood/Makefile b/board/amcc/redwood/Makefile
index 2ab3b20460..2bc632b240 100644
--- a/board/amcc/redwood/Makefile
+++ b/board/amcc/redwood/Makefile
@@ -5,24 +5,5 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	= $(BOARD).o
-SOBJS	= init.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	= redwood.o
+extra-y	+= init.o
diff --git a/board/amcc/sequoia/Makefile b/board/amcc/sequoia/Makefile
index c2a4c4b675..b4ab5daa85 100644
--- a/board/amcc/sequoia/Makefile
+++ b/board/amcc/sequoia/Makefile
@@ -5,29 +5,6 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS-y	= $(BOARD).o sdram.o
-COBJS-$(CONFIG_CMD_CHIP_CONFIG) += chip_config.o
-SOBJS	= init.o
-
-COBJS   := $(COBJS-y)
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-all:	$(LIB) $(SOBJS)
-
-$(LIB):	$(OBJS)
-	$(call cmd_link_o_target, $^)
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	= sequoia.o sdram.o
+obj-$(CONFIG_CMD_CHIP_CONFIG) += chip_config.o
+extra-y	+= init.o
diff --git a/board/amcc/sequoia/init.S b/board/amcc/sequoia/init.S
index b31e9db3f9..f876639d35 100644
--- a/board/amcc/sequoia/init.S
+++ b/board/amcc/sequoia/init.S
@@ -48,11 +48,7 @@ tlbtab:
 	/* BOOT_CS (FLASH) must be forth. Before relocation SA_I can be off to use the
 	 * speed up boot process. It is patched after relocation to enable SA_I
 	 */
-#ifndef CONFIG_NAND_SPL
 	tlbentry( CONFIG_SYS_BOOT_BASE_ADDR, SZ_256M, CONFIG_SYS_BOOT_BASE_ADDR, 1, AC_RWX | SA_G )
-#else
-	tlbentry( CONFIG_SYS_NAND_BOOT_SPL_SRC, SZ_4K, CONFIG_SYS_NAND_BOOT_SPL_SRC, 1, AC_RWX | SA_G )
-#endif
 
 #ifdef CONFIG_SYS_INIT_RAM_DCACHE
 	/* TLB-entry for init-ram in dcache (SA_I must be turned off!) */
@@ -81,31 +77,3 @@ tlbtab:
 	tlbentry(0xE8000000, SZ_64K, 0xE8000000, 1, AC_RWX | SA_IG)
 
 	tlbtab_end
-
-#if defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
-	/*
-	 * For NAND booting the first TLB has to be reconfigured to full size
-	 * and with caching disabled after running from RAM!
-	 */
-#define TLB00	TLB0(CONFIG_SYS_BOOT_BASE_ADDR, SZ_256M)
-#define TLB01	TLB1(CONFIG_SYS_BOOT_BASE_ADDR, 1)
-#define TLB02	TLB2(AC_RWX | SA_IG)
-
-	.globl	reconfig_tlb0
-reconfig_tlb0:
-	sync
-	isync
-	addi	r4,r0,CONFIG_SYS_TLB_FOR_BOOT_FLASH /* TLB entry # */
-	lis	r5,TLB00@h
-	ori	r5,r5,TLB00@l
-	tlbwe	r5,r4,0x0000		/* Save it out */
-	lis	r5,TLB01@h
-	ori	r5,r5,TLB01@l
-	tlbwe	r5,r4,0x0001		/* Save it out */
-	lis	r5,TLB02@h
-	ori	r5,r5,TLB02@l
-	tlbwe	r5,r4,0x0002		/* Save it out */
-	sync
-	isync
-	blr
-#endif
diff --git a/board/amcc/sequoia/sdram.c b/board/amcc/sequoia/sdram.c
index 2c5a21806a..67640d7edf 100644
--- a/board/amcc/sequoia/sdram.c
+++ b/board/amcc/sequoia/sdram.c
@@ -26,14 +26,6 @@
 extern int denali_wait_for_dlllock(void);
 extern void denali_core_search_data_eye(void);
 
-#if defined(CONFIG_NAND_SPL)
-/* Using arch/powerpc/cpu/ppc4xx/speed.c to calculate the bus frequency is too big
- * for the 4k NAND boot image so define bus_frequency to 133MHz here
- * which is save for the refresh counter setup.
- */
-#define get_bus_freq(val)	133333333
-#endif
-
 /*************************************************************************
  *
  * initdram -- 440EPx's DDR controller is a DENALI Core
@@ -41,8 +33,7 @@ extern void denali_core_search_data_eye(void);
  ************************************************************************/
 phys_size_t initdram (int board_type)
 {
-#if !(defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_SYS_RAMBOOT)) || \
-    defined(CONFIG_NAND_SPL)
+#if !defined(CONFIG_SYS_RAMBOOT)
 	ulong speed = get_bus_freq(0);
 
 	mtsdram(DDR0_02, 0x00000000);
@@ -81,7 +72,7 @@ phys_size_t initdram (int board_type)
 	mtsdram(DDR0_02, 0x00000001);
 
 	denali_wait_for_dlllock();
-#endif /* #ifndef CONFIG_NAND_U_BOOT */
+#endif /* #ifndef CONFIG_SYS_RAMBOOT */
 
 #ifdef CONFIG_DDR_DATA_EYE
 	/* -----------------------------------------------------------+
diff --git a/board/amcc/sequoia/sequoia.c b/board/amcc/sequoia/sequoia.c
index 73c65c56aa..53f9b3419f 100644
--- a/board/amcc/sequoia/sequoia.c
+++ b/board/amcc/sequoia/sequoia.c
@@ -142,8 +142,7 @@ int misc_init_r(void)
 	gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
 	gd->bd->bi_flashoffset = 0;
 
-#if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL) || \
-    defined(CONFIG_SYS_RAMBOOT)
+#if defined(CONFIG_SYS_RAMBOOT)
 	mtdcr(EBC0_CFGADDR, PB3CR);
 #else
 	mtdcr(EBC0_CFGADDR, PB0CR);
@@ -151,8 +150,7 @@ int misc_init_r(void)
 	pbcr = mfdcr(EBC0_CFGDATA);
 	size_val = ffs(gd->bd->bi_flashsize) - 21;
 	pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17);
-#if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL) || \
-    defined(CONFIG_SYS_RAMBOOT)
+#if defined(CONFIG_SYS_RAMBOOT)
 	mtdcr(EBC0_CFGADDR, PB3CR);
 #else
 	mtdcr(EBC0_CFGADDR, PB0CR);
@@ -360,7 +358,7 @@ void board_pci_fixup_irq(struct pci_controller *hose, pci_dev_t dev)
 }
 #endif
 
-#if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_SYS_RAMBOOT)
+#if defined(CONFIG_SYS_RAMBOOT)
 /*
  * On NAND-booting sequoia, we need to patch the chips select numbers
  * in the dtb (CS0 - NAND, CS3 - NOR)
@@ -411,4 +409,4 @@ void ft_board_setup(void *blob, bd_t *bd)
 		return;
 	}
 }
-#endif /* CONFIG_NAND_U_BOOT */
+#endif /* CONFIG_SYS_RAMBOOT */
diff --git a/board/amcc/taihu/Makefile b/board/amcc/taihu/Makefile
index 8a7bf4ad98..65606fe080 100644
--- a/board/amcc/taihu/Makefile
+++ b/board/amcc/taihu/Makefile
@@ -5,23 +5,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	= $(BOARD).o flash.o lcd.o update.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-
-$(LIB):	$(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	= taihu.o flash.o lcd.o update.o
diff --git a/board/amcc/taishan/Makefile b/board/amcc/taishan/Makefile
index 4bb14fe98b..04e93cc0da 100644
--- a/board/amcc/taishan/Makefile
+++ b/board/amcc/taishan/Makefile
@@ -5,25 +5,5 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	= $(BOARD).o lcd.o update.o showinfo.o
-SOBJS	= init.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(OBJS) $(SOBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	= taishan.o lcd.o update.o showinfo.o
+extra-y	+= init.o
diff --git a/board/amcc/walnut/Makefile b/board/amcc/walnut/Makefile
index bea58a7cae..922817076c 100644
--- a/board/amcc/walnut/Makefile
+++ b/board/amcc/walnut/Makefile
@@ -5,24 +5,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	= $(BOARD).o flash.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(OBJS) $(SOBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	= walnut.o flash.o
diff --git a/board/amcc/yosemite/Makefile b/board/amcc/yosemite/Makefile
index 1d80df8b74..daf020a5a9 100644
--- a/board/amcc/yosemite/Makefile
+++ b/board/amcc/yosemite/Makefile
@@ -5,25 +5,5 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	= $(BOARD).o
-SOBJS	= init.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(OBJS) $(SOBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	= yosemite.o
+extra-y	+= init.o
diff --git a/board/amcc/yucca/Makefile b/board/amcc/yucca/Makefile
index eaeb3871ef..5b1af3290f 100644
--- a/board/amcc/yucca/Makefile
+++ b/board/amcc/yucca/Makefile
@@ -5,25 +5,5 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	= $(BOARD).o flash.o cmd_yucca.o
-SOBJS	= init.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	= yucca.o flash.o cmd_yucca.o
+extra-y	+= init.o
diff --git a/board/armadeus/apf27/Makefile b/board/armadeus/apf27/Makefile
index 5fcda6e9cc..57129718d5 100644
--- a/board/armadeus/apf27/Makefile
+++ b/board/armadeus/apf27/Makefile
@@ -7,27 +7,6 @@
 # SPDX-License-Identifier:    GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	:= apf27.o
-SOBJS	:= lowlevel_init.o
-ifdef CONFIG_FPGA
-COBJS	+= fpga.o
-endif
-
-SRCS	:= $(COBJS:.o=.c) $(SOBJS:.o=.S)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
-	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
-
-#########################################################################
-
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	:= apf27.o
+obj-y	+= lowlevel_init.o
+obj-$(CONFIG_FPGA)	+= fpga.o
diff --git a/board/armltd/integrator/Makefile b/board/armltd/integrator/Makefile
index b86fbfbdad..7e5f6b03fd 100644
--- a/board/armltd/integrator/Makefile
+++ b/board/armltd/integrator/Makefile
@@ -9,28 +9,8 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
+obj-y	:= lowlevel_init.o
 
-LIB	= $(obj)lib$(BOARD).o
-
-SOBJS-y	:= lowlevel_init.o
-
-COBJS-y	:= integrator.o
-COBJS-$(CONFIG_PCI) += pci.o
-COBJS-y += timer.o
-
-SRCS	:= $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
-COBJS	:= $(addprefix $(obj),$(COBJS-y))
-SOBJS	:= $(addprefix $(obj),$(SOBJS-y))
-
-$(LIB):	$(obj).depend $(COBJS) $(SOBJS)
-	$(call cmd_link_o_target, $(COBJS) $(SOBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	+= integrator.o
+obj-$(CONFIG_PCI) += pci.o
+obj-y += timer.o
diff --git a/board/armltd/integrator/lowlevel_init.S b/board/armltd/integrator/lowlevel_init.S
index 389d5e9083..0fb42adc6f 100644
--- a/board/armltd/integrator/lowlevel_init.S
+++ b/board/armltd/integrator/lowlevel_init.S
@@ -183,7 +183,7 @@ cm_remap:
 
 	/* Now 0x00000000 is writeable, replace the vectors	*/
 	ldr	r0, =_start	/* r0 <- start of vectors	*/
-	ldr	r2, =_TEXT_BASE	/* r2 <- past vectors	*/
+	add	r2, r0, #64	/* r2 <- past vectors	*/
 	sub	r1,r1,r1		/* destination 0x00000000	*/
 
 copy_vec:
diff --git a/board/armltd/versatile/Makefile b/board/armltd/versatile/Makefile
index 89ae01f816..a09a0ae550 100644
--- a/board/armltd/versatile/Makefile
+++ b/board/armltd/versatile/Makefile
@@ -5,25 +5,5 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	:= versatile.o
-SOBJS	:= lowlevel_init.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
-	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	:= versatile.o
+obj-y	+= lowlevel_init.o
diff --git a/board/armltd/versatile/versatile.c b/board/armltd/versatile/versatile.c
index 30a3b904db..4e2d3421d8 100644
--- a/board/armltd/versatile/versatile.c
+++ b/board/armltd/versatile/versatile.c
@@ -52,7 +52,11 @@ int board_early_init_f (void)
 int board_init (void)
 {
 	/* arch number of Versatile Board */
+#ifdef CONFIG_ARCH_VERSATILE_AB
+	gd->bd->bi_arch_number = MACH_TYPE_VERSATILE_AB;
+#else
 	gd->bd->bi_arch_number = MACH_TYPE_VERSATILE_PB;
+#endif
 
 	/* adress of boot parameters */
 	gd->bd->bi_boot_params = 0x00000100;
diff --git a/board/armltd/vexpress/Makefile b/board/armltd/vexpress/Makefile
index e7dc3122ad..1dd6780708 100644
--- a/board/armltd/vexpress/Makefile
+++ b/board/armltd/vexpress/Makefile
@@ -5,23 +5,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	:= vexpress_common.o
-
-SRCS	:= $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	:= vexpress_common.o
diff --git a/board/armltd/vexpress/vexpress_common.c b/board/armltd/vexpress/vexpress_common.c
index 56febd9525..cb2de2f4dd 100644
--- a/board/armltd/vexpress/vexpress_common.c
+++ b/board/armltd/vexpress/vexpress_common.c
@@ -26,9 +26,6 @@
 #include <asm/arch/wdt.h>
 #include "../drivers/mmc/arm_pl180_mmci.h"
 
-static ulong timestamp;
-static ulong lastdec;
-
 static struct systimer *systimer_base = (struct systimer *)V2M_TIMER01;
 static struct sysctrl *sysctrl_base = (struct sysctrl *)SCTL_BASE;
 
@@ -122,11 +119,6 @@ void dram_init_banksize(void)
 			get_ram_size((long *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE);
 }
 
-int timer_init(void)
-{
-	return 0;
-}
-
 /*
  * Start timer:
  *    Setup a 32 bit timer, running at 1KHz
@@ -152,8 +144,6 @@ static void vexpress_timer_init(void)
 	writel(SYSTIMER_EN | SYSTIMER_32BIT |
 	       readl(&systimer_base->timer0control),
 	       &systimer_base->timer0control);
-
-	reset_timer_masked();
 }
 
 int v2m_cfg_write(u32 devfn, u32 data)
@@ -183,62 +173,6 @@ void reset_cpu(ulong addr)
 		printf("Unable to reboot\n");
 }
 
-/*
- * Delay x useconds AND perserve advance timstamp value
- *     assumes timer is ticking at 1 msec
- */
-void __udelay(ulong usec)
-{
-	ulong tmo, tmp;
-
-	tmo = usec / 1000;
-	tmp = get_timer(0);	/* get current timestamp */
-
-	/*
-	 * If setting this forward will roll time stamp	then
-	 * reset "advancing" timestamp to 0 and set lastdec value
-	 * otherwise set the advancing stamp to the wake up time
-	 */
-	if ((tmo + tmp + 1) < tmp)
-		reset_timer_masked();
-	else
-		tmo += tmp;
-
-	while (get_timer_masked() < tmo)
-		; /* loop till wakeup event */
-}
-
-ulong get_timer(ulong base)
-{
-	return get_timer_masked() - base;
-}
-
-void reset_timer_masked(void)
-{
-	lastdec = readl(&systimer_base->timer0value) / 1000;
-	timestamp = 0;
-}
-
-ulong get_timer_masked(void)
-{
-	ulong now = readl(&systimer_base->timer0value) / 1000;
-
-	if (lastdec >= now) {	/* normal mode (non roll) */
-		timestamp += lastdec - now;
-	} else {		/* count down timer overflowed */
-		/*
-		 * nts = ts + ld - now
-		 * ts = old stamp, ld = time before passing through - 1
-		 * now = amount of time after passing though - 1
-		 * nts = new "advancing time stamp"
-		 */
-		timestamp += lastdec + SYSTIMER_RELOAD - now;
-	}
-	lastdec = now;
-
-	return timestamp;
-}
-
 void lowlevel_init(void)
 {
 }
@@ -247,16 +181,6 @@ ulong get_board_rev(void){
 	return readl((u32 *)SYS_ID);
 }
 
-unsigned long long get_ticks(void)
-{
-	return get_timer(0);
-}
-
-ulong get_tbclk(void)
-{
-	return (ulong)CONFIG_SYS_HZ;
-}
-
 #if defined(CONFIG_ARMV7_NONSEC) || defined(CONFIG_ARMV7_VIRT)
 /* Setting the address at which secondary cores start from.
  * Versatile Express uses one address for all cores, so ignore corenr
diff --git a/board/armltd/vexpress64/Makefile b/board/armltd/vexpress64/Makefile
new file mode 100644
index 0000000000..e009141a42
--- /dev/null
+++ b/board/armltd/vexpress64/Makefile
@@ -0,0 +1,8 @@
+#
+# (C) Copyright 2000-2004
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y	:= vexpress64.o
diff --git a/board/armltd/vexpress64/vexpress64.c b/board/armltd/vexpress64/vexpress64.c
new file mode 100644
index 0000000000..2ec3bc9835
--- /dev/null
+++ b/board/armltd/vexpress64/vexpress64.c
@@ -0,0 +1,56 @@
+/*
+ * (C) Copyright 2013
+ * David Feng <fenghua@phytium.com.cn>
+ * Sharma Bhupesh <bhupesh.sharma@freescale.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+#include <common.h>
+#include <malloc.h>
+#include <errno.h>
+#include <netdev.h>
+#include <asm/io.h>
+#include <linux/compiler.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_init(void)
+{
+	return 0;
+}
+
+int dram_init(void)
+{
+	/*
+	 * Clear spin table so that secondary processors
+	 * observe the correct value after waken up from wfe.
+	 */
+	*(unsigned long *)CPU_RELEASE_ADDR = 0;
+
+	gd->ram_size = PHYS_SDRAM_1_SIZE;
+	return 0;
+}
+
+int timer_init(void)
+{
+	return 0;
+}
+
+/*
+ * Board specific reset that is system reset.
+ */
+void reset_cpu(ulong addr)
+{
+}
+
+/*
+ * Board specific ethernet initialization routine.
+ */
+int board_eth_init(bd_t *bis)
+{
+	int rc = 0;
+#ifdef CONFIG_SMC91111
+	rc = smc91111_initialize(0, CONFIG_SMC91111_BASE);
+#endif
+	return rc;
+}
diff --git a/board/astro/mcf5373l/Makefile b/board/astro/mcf5373l/Makefile
index b7497a0d7c..005d036975 100644
--- a/board/astro/mcf5373l/Makefile
+++ b/board/astro/mcf5373l/Makefile
@@ -5,24 +5,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	= $(BOARD).o fpga.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	= mcf5373l.o fpga.o
diff --git a/board/atc/Makefile b/board/atc/Makefile
index aa100e4213..3a163c4c6b 100644
--- a/board/atc/Makefile
+++ b/board/atc/Makefile
@@ -5,24 +5,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	= $(BOARD).o flash.o ti113x.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	= atc.o flash.o ti113x.o
diff --git a/board/atmark-techno/armadillo-800eva/Makefile b/board/atmark-techno/armadillo-800eva/Makefile
index a81e40b58b..2743809e57 100644
--- a/board/atmark-techno/armadillo-800eva/Makefile
+++ b/board/atmark-techno/armadillo-800eva/Makefile
@@ -16,30 +16,5 @@
 # Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 # MA 02111-1307 USA
 
-include $(TOPDIR)/config.mk
+obj-y	+= armadillo-800eva.o
 
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS-y	+= armadillo-800eva.o
-COBJS   := $(COBJS-y)
-
-SRCS	:= $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-clean:
-	rm -f $(OBJS)
-
-distclean:	clean
-	rm -f $(LIB) core *.bak $(obj).depend
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
diff --git a/board/atmel/at91rm9200ek/Makefile b/board/atmel/at91rm9200ek/Makefile
index 317920976e..0530830b99 100644
--- a/board/atmel/at91rm9200ek/Makefile
+++ b/board/atmel/at91rm9200ek/Makefile
@@ -5,25 +5,5 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS-y += $(BOARD).o
-COBJS-y += led.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS-y))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
-	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y += at91rm9200ek.o
+obj-y += led.o
diff --git a/board/atmel/at91sam9260ek/Makefile b/board/atmel/at91sam9260ek/Makefile
index a949000573..c6edbeee24 100644
--- a/board/atmel/at91sam9260ek/Makefile
+++ b/board/atmel/at91sam9260ek/Makefile
@@ -9,26 +9,6 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS-y	+= at91sam9260ek.o
-COBJS-y	+= led.o
-COBJS-$(CONFIG_HAS_DATAFLASH) += partition.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS-y))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
-	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	+= at91sam9260ek.o
+obj-y	+= led.o
+obj-$(CONFIG_HAS_DATAFLASH) += partition.o
diff --git a/board/atmel/at91sam9260ek/at91sam9260ek.c b/board/atmel/at91sam9260ek/at91sam9260ek.c
index 263de49c76..7f14af1011 100644
--- a/board/atmel/at91sam9260ek/at91sam9260ek.c
+++ b/board/atmel/at91sam9260ek/at91sam9260ek.c
@@ -12,7 +12,6 @@
 #include <asm/arch/at91sam9_smc.h>
 #include <asm/arch/at91_common.h>
 #include <asm/arch/at91_pmc.h>
-#include <asm/arch/at91_rstc.h>
 #include <asm/arch/gpio.h>
 #include <atmel_mci.h>
 
@@ -73,8 +72,6 @@ static void at91sam9260ek_macb_hw_init(void)
 {
 	struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
 	struct at91_port *pioa = (struct at91_port *)ATMEL_BASE_PIOA;
-	struct at91_rstc *rstc = (struct at91_rstc *)ATMEL_BASE_RSTC;
-	unsigned long erstl;
 
 	/* Enable EMAC clock */
 	writel(1 << ATMEL_ID_EMAC0, &pmc->pcer);
@@ -98,21 +95,7 @@ static void at91sam9260ek_macb_hw_init(void)
 		pin_to_mask(AT91_PIN_PA28),
 		&pioa->pudr);
 
-	erstl = readl(&rstc->mr) & AT91_RSTC_MR_ERSTL_MASK;
-
-	/* Need to reset PHY -> 500ms reset */
-	writel(AT91_RSTC_KEY | AT91_RSTC_MR_ERSTL(13) |
-		AT91_RSTC_MR_URSTEN, &rstc->mr);
-
-	writel(AT91_RSTC_KEY | AT91_RSTC_CR_EXTRST, &rstc->cr);
-
-	/* Wait for end hardware reset */
-	while (!(readl(&rstc->sr) & AT91_RSTC_SR_NRSTL))
-		;
-
-	/* Restore NRST value */
-	writel(AT91_RSTC_KEY | erstl | AT91_RSTC_MR_URSTEN,
-		&rstc->mr);
+	at91_phy_reset();
 
 	/* Re-enable pull-up */
 	writel(pin_to_mask(AT91_PIN_PA14) |
diff --git a/board/atmel/at91sam9261ek/Makefile b/board/atmel/at91sam9261ek/Makefile
index 1551aa2196..c547fed42a 100644
--- a/board/atmel/at91sam9261ek/Makefile
+++ b/board/atmel/at91sam9261ek/Makefile
@@ -9,26 +9,6 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS-y += at91sam9261ek.o
-COBJS-y += led.o
-COBJS-$(CONFIG_HAS_DATAFLASH) += partition.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS-y))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
-	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y += at91sam9261ek.o
+obj-y += led.o
+obj-$(CONFIG_HAS_DATAFLASH) += partition.o
diff --git a/board/atmel/at91sam9263ek/Makefile b/board/atmel/at91sam9263ek/Makefile
index fdb53d3417..7b31f18e4f 100644
--- a/board/atmel/at91sam9263ek/Makefile
+++ b/board/atmel/at91sam9263ek/Makefile
@@ -9,26 +9,6 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS-y += at91sam9263ek.o
-COBJS-y += led.o
-COBJS-$(CONFIG_HAS_DATAFLASH) += partition.o
-
-SRCS	:= $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS-y))
-SOBJS	:= $(addprefix $(obj),$(SOBJS-y))
-
-$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
-	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y += at91sam9263ek.o
+obj-y += led.o
+obj-$(CONFIG_HAS_DATAFLASH) += partition.o
diff --git a/board/atmel/at91sam9263ek/at91sam9263ek.c b/board/atmel/at91sam9263ek/at91sam9263ek.c
index 2e9246f31c..db29879801 100644
--- a/board/atmel/at91sam9263ek/at91sam9263ek.c
+++ b/board/atmel/at91sam9263ek/at91sam9263ek.c
@@ -7,12 +7,11 @@
  */
 
 #include <common.h>
-#include <asm/sizes.h>
+#include <linux/sizes.h>
 #include <asm/arch/at91sam9263.h>
 #include <asm/arch/at91sam9_smc.h>
 #include <asm/arch/at91_common.h>
 #include <asm/arch/at91_pmc.h>
-#include <asm/arch/at91_rstc.h>
 #include <asm/arch/at91_matrix.h>
 #include <asm/arch/at91_pio.h>
 #include <asm/arch/clk.h>
@@ -25,6 +24,7 @@
 #include <net.h>
 #endif
 #include <netdev.h>
+#include <atmel_mci.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -82,10 +82,9 @@ static void at91sam9263ek_nand_hw_init(void)
 #ifdef CONFIG_MACB
 static void at91sam9263ek_macb_hw_init(void)
 {
-	unsigned long 	erstl;
 	at91_pmc_t	*pmc	= (at91_pmc_t *) ATMEL_BASE_PMC;
 	at91_pio_t	*pio	= (at91_pio_t *) ATMEL_BASE_PIO;
-	at91_rstc_t	*rstc	= (at91_rstc_t *) ATMEL_BASE_RSTC;
+
 	/* Enable clock */
 	writel(1 << ATMEL_ID_EMAC, &pmc->pcer);
 
@@ -97,23 +96,10 @@ static void at91sam9263ek_macb_hw_init(void)
 	 *
 	 * PHY has internal pull-down
 	 */
-
 	writel(1 << 25, &pio->pioc.pudr);
 	writel((1 << 25) | (1 <<26), &pio->pioe.pudr);
 
-	erstl = readl(&rstc->mr) & AT91_RSTC_MR_ERSTL_MASK;
-
-	/* Need to reset PHY -> 500ms reset */
-	writel(AT91_RSTC_KEY | AT91_RSTC_MR_ERSTL(0x0D) |
-		AT91_RSTC_MR_URSTEN, &rstc->mr);
-
-	writel(AT91_RSTC_KEY | AT91_RSTC_CR_EXTRST, &rstc->cr);
-	/* Wait for end hardware reset */
-	while (!(readl(&rstc->sr) & AT91_RSTC_SR_NRSTL))
-		;
-
-	/* Restore NRST value */
-	writel(AT91_RSTC_KEY | erstl | AT91_RSTC_MR_URSTEN, &rstc->mr);
+	at91_phy_reset();
 
 	/* Re-enable pull-up */
 	writel(1 << 25, &pio->pioc.puer);
@@ -229,6 +215,15 @@ void lcd_show_board_info(void)
 #endif /* CONFIG_LCD_INFO */
 #endif
 
+#ifdef CONFIG_GENERIC_ATMEL_MCI
+int board_mmc_init(bd_t *bd)
+{
+	at91_mci_hw_init();
+
+	return atmel_mci_init((void *)ATMEL_BASE_MCI1);
+}
+#endif
+
 int board_early_init_f(void)
 {
 	struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
diff --git a/board/atmel/at91sam9m10g45ek/Makefile b/board/atmel/at91sam9m10g45ek/Makefile
index 84f613bcc9..e5448ecc67 100644
--- a/board/atmel/at91sam9m10g45ek/Makefile
+++ b/board/atmel/at91sam9m10g45ek/Makefile
@@ -9,25 +9,5 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS-y += at91sam9m10g45ek.o
-COBJS-y += led.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS-y))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
-	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y += at91sam9m10g45ek.o
+obj-y += led.o
diff --git a/board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c b/board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c
index 6a071f6b7d..b7e2efd2fc 100644
--- a/board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c
+++ b/board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c
@@ -12,7 +12,6 @@
 #include <asm/arch/at91sam9_smc.h>
 #include <asm/arch/at91_common.h>
 #include <asm/arch/at91_pmc.h>
-#include <asm/arch/at91_rstc.h>
 #include <asm/arch/gpio.h>
 #include <asm/arch/clk.h>
 #include <lcd.h>
@@ -88,8 +87,6 @@ static void at91sam9m10g45ek_macb_hw_init(void)
 {
 	struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
 	struct at91_port *pioa = (struct at91_port *)ATMEL_BASE_PIOA;
-	struct at91_rstc *rstc = (struct at91_rstc *)ATMEL_BASE_RSTC;
-	unsigned long erstl;
 
 	/* Enable clock */
 	writel(1 << ATMEL_ID_EMAC, &pmc->pcer);
@@ -107,21 +104,7 @@ static void at91sam9m10g45ek_macb_hw_init(void)
 	       pin_to_mask(AT91_PIN_PA13),
 	       &pioa->pudr);
 
-	erstl = readl(&rstc->mr) & AT91_RSTC_MR_ERSTL_MASK;
-
-	/* Need to reset PHY -> 500ms reset */
-	writel(AT91_RSTC_KEY | AT91_RSTC_MR_ERSTL(13) |
-		AT91_RSTC_MR_URSTEN, &rstc->mr);
-
-	writel(AT91_RSTC_KEY | AT91_RSTC_CR_EXTRST, &rstc->cr);
-
-	/* Wait for end hardware reset */
-	while (!(readl(&rstc->sr) & AT91_RSTC_SR_NRSTL))
-		;
-
-	/* Restore NRST value */
-	writel(AT91_RSTC_KEY | erstl | AT91_RSTC_MR_URSTEN,
-		&rstc->mr);
+	at91_phy_reset();
 
 	/* Re-enable pull-up */
 	writel(pin_to_mask(AT91_PIN_PA15) |
diff --git a/board/atmel/at91sam9n12ek/Makefile b/board/atmel/at91sam9n12ek/Makefile
index 859817f670..9f069ca74a 100644
--- a/board/atmel/at91sam9n12ek/Makefile
+++ b/board/atmel/at91sam9n12ek/Makefile
@@ -13,24 +13,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS-y	+= at91sam9n12ek.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS-y))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
-	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	+= at91sam9n12ek.o
diff --git a/board/atmel/at91sam9n12ek/at91sam9n12ek.c b/board/atmel/at91sam9n12ek/at91sam9n12ek.c
index 2ec32ebc21..9adc9920b4 100644
--- a/board/atmel/at91sam9n12ek/at91sam9n12ek.c
+++ b/board/atmel/at91sam9n12ek/at91sam9n12ek.c
@@ -199,6 +199,13 @@ void at91sam9n12ek_ks8851_hw_init(void)
 }
 #endif
 
+#ifdef CONFIG_USB_ATMEL
+void at91sam9n12ek_usb_hw_init(void)
+{
+	at91_set_pio_output(AT91_PIO_PORTB, 7, 0);
+}
+#endif
+
 int board_early_init_f(void)
 {
 	/* Enable clocks for all PIOs */
@@ -230,6 +237,10 @@ int board_init(void)
 	at91sam9n12ek_ks8851_hw_init();
 #endif
 
+#ifdef CONFIG_USB_ATMEL
+	at91sam9n12ek_usb_hw_init();
+#endif
+
 	return 0;
 }
 
diff --git a/board/atmel/at91sam9rlek/Makefile b/board/atmel/at91sam9rlek/Makefile
index 7f6ea90a25..51daf8d30c 100644
--- a/board/atmel/at91sam9rlek/Makefile
+++ b/board/atmel/at91sam9rlek/Makefile
@@ -9,26 +9,6 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS-y += at91sam9rlek.o
-COBJS-y += led.o
-COBJS-$(CONFIG_HAS_DATAFLASH) += partition.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS-y))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
-	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y += at91sam9rlek.o
+obj-y += led.o
+obj-$(CONFIG_HAS_DATAFLASH) += partition.o
diff --git a/board/atmel/at91sam9x5ek/Makefile b/board/atmel/at91sam9x5ek/Makefile
index e8f19ea0d4..5c42b6fe86 100644
--- a/board/atmel/at91sam9x5ek/Makefile
+++ b/board/atmel/at91sam9x5ek/Makefile
@@ -13,24 +13,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS-y += at91sam9x5ek.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS-y))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
-	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y += at91sam9x5ek.o
diff --git a/board/atmel/at91sam9x5ek/at91sam9x5ek.c b/board/atmel/at91sam9x5ek/at91sam9x5ek.c
index 6f67c34a53..17a2a40b4b 100644
--- a/board/atmel/at91sam9x5ek/at91sam9x5ek.c
+++ b/board/atmel/at91sam9x5ek/at91sam9x5ek.c
@@ -271,7 +271,6 @@ int board_init(void)
 #endif
 
 #ifdef CONFIG_ATMEL_SPI
-	at91_spi0_hw_init(1 << 0);
 	at91_spi0_hw_init(1 << 4);
 #endif
 
diff --git a/board/atmel/atngw100/Makefile b/board/atmel/atngw100/Makefile
index 955a9c558b..f9b93c9738 100644
--- a/board/atmel/atngw100/Makefile
+++ b/board/atmel/atngw100/Makefile
@@ -3,23 +3,4 @@
 #
 # SPDX-License-Identifier:	GPL-2.0+
 
-include $(TOPDIR)/config.mk
-
-LIB	:= $(obj)lib$(BOARD).o
-
-COBJS	:= $(BOARD).o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS))
-
-$(LIB): $(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	:= atngw100.o
diff --git a/board/atmel/atngw100mkii/Makefile b/board/atmel/atngw100mkii/Makefile
index 955a9c558b..90bf5bc84e 100644
--- a/board/atmel/atngw100mkii/Makefile
+++ b/board/atmel/atngw100mkii/Makefile
@@ -3,23 +3,4 @@
 #
 # SPDX-License-Identifier:	GPL-2.0+
 
-include $(TOPDIR)/config.mk
-
-LIB	:= $(obj)lib$(BOARD).o
-
-COBJS	:= $(BOARD).o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS))
-
-$(LIB): $(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	:= atngw100mkii.o
diff --git a/board/atmel/atstk1000/Makefile b/board/atmel/atstk1000/Makefile
index 4eab5a789e..ad76631b97 100644
--- a/board/atmel/atstk1000/Makefile
+++ b/board/atmel/atstk1000/Makefile
@@ -6,23 +6,4 @@
 #
 # SPDX-License-Identifier:	GPL-2.0+
 
-include $(TOPDIR)/config.mk
-
-LIB			:= $(obj)lib$(BOARD).o
-
-COBJS-y			+= $(BOARD).o
-
-SRCS			:= $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
-OBJS			:= $(addprefix $(obj),$(SOBJS-y) $(COBJS-y))
-
-$(LIB): $(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y			+= atstk1000.o
diff --git a/board/atmel/sama5d3_xplained/Makefile b/board/atmel/sama5d3_xplained/Makefile
new file mode 100644
index 0000000000..ec82b06990
--- /dev/null
+++ b/board/atmel/sama5d3_xplained/Makefile
@@ -0,0 +1,15 @@
+#
+# (C) Copyright 2003-2008
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# (C) Copyright 2008
+# Stelian Pop <stelian@popies.net>
+# Lead Tech Design <www.leadtechdesign.com>
+#
+# (C) Copyright 2014
+# Bo Shen <voice.shen@atmel.com>
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y += sama5d3_xplained.o
diff --git a/board/atmel/sama5d3_xplained/sama5d3_xplained.c b/board/atmel/sama5d3_xplained/sama5d3_xplained.c
new file mode 100644
index 0000000000..39f2dc6475
--- /dev/null
+++ b/board/atmel/sama5d3_xplained/sama5d3_xplained.c
@@ -0,0 +1,130 @@
+/*
+ * Copyright (C) 2014 Atmel Corporation
+ *		      Bo Shen <voice.shen@atmel.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <mmc.h>
+#include <asm/io.h>
+#include <asm/arch/sama5d3_smc.h>
+#include <asm/arch/at91_common.h>
+#include <asm/arch/at91_pmc.h>
+#include <asm/arch/at91_rstc.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/clk.h>
+#include <atmel_mci.h>
+#include <net.h>
+#include <netdev.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#ifdef CONFIG_NAND_ATMEL
+void sama5d3_xplained_nand_hw_init(void)
+{
+	struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
+
+	at91_periph_clk_enable(ATMEL_ID_SMC);
+
+	/* Configure SMC CS3 for NAND/SmartMedia */
+	writel(AT91_SMC_SETUP_NWE(2) | AT91_SMC_SETUP_NCS_WR(1) |
+	       AT91_SMC_SETUP_NRD(2) | AT91_SMC_SETUP_NCS_RD(1),
+	       &smc->cs[3].setup);
+	writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(5) |
+	       AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(5),
+	       &smc->cs[3].pulse);
+	writel(AT91_SMC_CYCLE_NWE(8) | AT91_SMC_CYCLE_NRD(8),
+	       &smc->cs[3].cycle);
+	writel(AT91_SMC_TIMINGS_TCLR(3) | AT91_SMC_TIMINGS_TADL(10) |
+	       AT91_SMC_TIMINGS_TAR(3)  | AT91_SMC_TIMINGS_TRR(4)   |
+	       AT91_SMC_TIMINGS_TWB(5)  | AT91_SMC_TIMINGS_RBNSEL(3)|
+	       AT91_SMC_TIMINGS_NFSEL(1), &smc->cs[3].timings);
+	writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
+	       AT91_SMC_MODE_EXNW_DISABLE |
+#ifdef CONFIG_SYS_NAND_DBW_16
+	       AT91_SMC_MODE_DBW_16 |
+#else /* CONFIG_SYS_NAND_DBW_8 */
+	       AT91_SMC_MODE_DBW_8 |
+#endif
+	       AT91_SMC_MODE_TDF_CYCLE(3),
+	       &smc->cs[3].mode);
+}
+#endif
+
+#ifdef CONFIG_CMD_USB
+static void sama5d3_xplained_usb_hw_init(void)
+{
+	at91_set_pio_output(AT91_PIO_PORTE, 3, 0);
+	at91_set_pio_output(AT91_PIO_PORTE, 4, 0);
+}
+#endif
+
+#ifdef CONFIG_GENERIC_ATMEL_MCI
+static void sama5d3_xplained_mci0_hw_init(void)
+{
+	at91_mci_hw_init();
+
+	at91_set_pio_output(AT91_PIO_PORTE, 2, 0);	/* MCI0 Power */
+}
+#endif
+
+int board_early_init_f(void)
+{
+	at91_periph_clk_enable(ATMEL_ID_PIOA);
+	at91_periph_clk_enable(ATMEL_ID_PIOB);
+	at91_periph_clk_enable(ATMEL_ID_PIOC);
+	at91_periph_clk_enable(ATMEL_ID_PIOD);
+	at91_periph_clk_enable(ATMEL_ID_PIOE);
+
+	at91_seriald_hw_init();
+
+	return 0;
+}
+
+int board_init(void)
+{
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+
+#ifdef CONFIG_NAND_ATMEL
+	sama5d3_xplained_nand_hw_init();
+#endif
+#ifdef CONFIG_CMD_USB
+	sama5d3_xplained_usb_hw_init();
+#endif
+#ifdef CONFIG_GENERIC_ATMEL_MCI
+	sama5d3_xplained_mci0_hw_init();
+#endif
+#ifdef CONFIG_MACB
+	at91_gmac_hw_init();
+	at91_macb_hw_init();
+#endif
+	return 0;
+}
+
+int dram_init(void)
+{
+	gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
+				    CONFIG_SYS_SDRAM_SIZE);
+
+	return 0;
+}
+
+int board_eth_init(bd_t *bis)
+{
+#ifdef CONFIG_MACB
+	macb_eth_initialize(0, (void *)ATMEL_BASE_GMAC, 0x00);
+	macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC, 0x00);
+#endif
+	return 0;
+}
+
+#ifdef CONFIG_GENERIC_ATMEL_MCI
+int board_mmc_init(bd_t *bis)
+{
+	atmel_mci_init((void *)ATMEL_BASE_MCI0);
+
+	return 0;
+}
+#endif
diff --git a/board/atmel/sama5d3xek/Makefile b/board/atmel/sama5d3xek/Makefile
index 384ca3f791..7ff74810ce 100644
--- a/board/atmel/sama5d3xek/Makefile
+++ b/board/atmel/sama5d3xek/Makefile
@@ -12,24 +12,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS-y += sama5d3xek.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS-y))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
-	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y += sama5d3xek.o
diff --git a/board/atmel/sama5d3xek/sama5d3xek.c b/board/atmel/sama5d3xek/sama5d3xek.c
index b0965ef211..c835c12d02 100644
--- a/board/atmel/sama5d3xek/sama5d3xek.c
+++ b/board/atmel/sama5d3xek/sama5d3xek.c
@@ -20,6 +20,9 @@
 #include <micrel.h>
 #include <net.h>
 #include <netdev.h>
+#include <spl.h>
+#include <asm/arch/atmel_mpddrc.h>
+#include <asm/arch/at91_wdt.h>
 
 #ifdef CONFIG_USB_GADGET_ATMEL_USBA
 #include <asm/arch/atmel_usba_udc.h>
@@ -131,7 +134,8 @@ static void sama5d3xek_lcd_hw_init(void)
 
 void lcd_show_board_info(void)
 {
-	ulong dram_size, nand_size;
+	ulong dram_size;
+	uint64_t nand_size;
 	int i;
 	char temp[32];
 
@@ -150,7 +154,7 @@ void lcd_show_board_info(void)
 	for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
 		nand_size += nand_info[i].size;
 #endif
-	lcd_printf("%ld MB SDRAM, %ld MB NAND\n",
+	lcd_printf("%ld MB SDRAM, %lld MB NAND\n",
 		   dram_size >> 20, nand_size >> 20);
 }
 #endif /* CONFIG_LCD_INFO */
@@ -158,6 +162,12 @@ void lcd_show_board_info(void)
 
 int board_early_init_f(void)
 {
+	at91_periph_clk_enable(ATMEL_ID_PIOA);
+	at91_periph_clk_enable(ATMEL_ID_PIOB);
+	at91_periph_clk_enable(ATMEL_ID_PIOC);
+	at91_periph_clk_enable(ATMEL_ID_PIOD);
+	at91_periph_clk_enable(ATMEL_ID_PIOE);
+
 	at91_seriald_hw_init();
 
 	return 0;
@@ -290,3 +300,89 @@ void spi_cs_deactivate(struct spi_slave *slave)
 	}
 }
 #endif /* CONFIG_ATMEL_SPI */
+
+/* SPL */
+#ifdef CONFIG_SPL_BUILD
+void spl_board_init(void)
+{
+#ifdef CONFIG_SYS_USE_MMC
+	sama5d3xek_mci_hw_init();
+#elif CONFIG_SYS_USE_NANDFLASH
+	sama5d3xek_nand_hw_init();
+#elif CONFIG_SYS_USE_SERIALFLASH
+	at91_spi0_hw_init(1 << 0);
+#endif
+}
+
+static void ddr2_conf(struct atmel_mpddr *ddr2)
+{
+	ddr2->md = (ATMEL_MPDDRC_MD_DBW_32_BITS | ATMEL_MPDDRC_MD_DDR2_SDRAM);
+
+	ddr2->cr = (ATMEL_MPDDRC_CR_NC_COL_10 |
+		    ATMEL_MPDDRC_CR_NR_ROW_14 |
+		    ATMEL_MPDDRC_CR_CAS_DDR_CAS3 |
+		    ATMEL_MPDDRC_CR_ENRDM_ON |
+		    ATMEL_MPDDRC_CR_NB_8BANKS |
+		    ATMEL_MPDDRC_CR_NDQS_DISABLED |
+		    ATMEL_MPDDRC_CR_DECOD_INTERLEAVED |
+		    ATMEL_MPDDRC_CR_UNAL_SUPPORTED);
+	/*
+	 * As the DDR2-SDRAm device requires a refresh time is 7.8125us
+	 * when DDR run at 133MHz, so it needs (7.8125us * 133MHz / 10^9) clocks
+	 */
+	ddr2->rtr = 0x411;
+
+	ddr2->tpr0 = (6 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET |
+		      2 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET |
+		      2 << ATMEL_MPDDRC_TPR0_TWR_OFFSET |
+		      8 << ATMEL_MPDDRC_TPR0_TRC_OFFSET |
+		      2 << ATMEL_MPDDRC_TPR0_TRP_OFFSET |
+		      2 << ATMEL_MPDDRC_TPR0_TRRD_OFFSET |
+		      2 << ATMEL_MPDDRC_TPR0_TWTR_OFFSET |
+		      2 << ATMEL_MPDDRC_TPR0_TMRD_OFFSET);
+
+	ddr2->tpr1 = (2 << ATMEL_MPDDRC_TPR1_TXP_OFFSET |
+		      200 << ATMEL_MPDDRC_TPR1_TXSRD_OFFSET |
+		      28 << ATMEL_MPDDRC_TPR1_TXSNR_OFFSET |
+		      26 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET);
+
+	ddr2->tpr2 = (7 << ATMEL_MPDDRC_TPR2_TFAW_OFFSET |
+		      2 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET |
+		      2 << ATMEL_MPDDRC_TPR2_TRPA_OFFSET |
+		      7 << ATMEL_MPDDRC_TPR2_TXARDS_OFFSET |
+		      8 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET);
+}
+
+void mem_init(void)
+{
+	struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
+	struct atmel_mpddr ddr2;
+
+	ddr2_conf(&ddr2);
+
+	/* enable MPDDR clock */
+	at91_periph_clk_enable(ATMEL_ID_MPDDRC);
+	writel(0x4, &pmc->scer);
+
+	/* DDRAM2 Controller initialize */
+	ddr2_init(ATMEL_BASE_DDRCS, &ddr2);
+}
+
+void at91_pmc_init(void)
+{
+	struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
+	u32 tmp;
+
+	tmp = AT91_PMC_PLLAR_29 |
+	      AT91_PMC_PLLXR_PLLCOUNT(0x3f) |
+	      AT91_PMC_PLLXR_MUL(43) |
+	      AT91_PMC_PLLXR_DIV(1);
+	at91_plla_init(tmp);
+
+	writel(0x3 << 8, &pmc->pllicpr);
+
+	tmp = AT91_PMC_MCKR_MDIV_4 |
+	      AT91_PMC_MCKR_CSS_PLLA;
+	at91_mck_init(tmp);
+}
+#endif
diff --git a/board/avionic-design/common/pinmux-config-tamonten-ng.h b/board/avionic-design/common/pinmux-config-tamonten-ng.h
new file mode 100644
index 0000000000..39df73138a
--- /dev/null
+++ b/board/avionic-design/common/pinmux-config-tamonten-ng.h
@@ -0,0 +1,385 @@
+/*
+ * (C) Copyright 2013
+ * Avionic Design GmbH <www.avionic-design.de>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _PINMUX_CONFIG_TAMONTEN_NG_H_
+#define _PINMUX_CONFIG_TAMONTEN_NG_H_
+
+#define DEFAULT_PINMUX(_pingroup, _mux, _pull, _tri, _io)	\
+	{							\
+		.pingroup	= PINGRP_##_pingroup,		\
+		.func		= PMUX_FUNC_##_mux,		\
+		.pull		= PMUX_PULL_##_pull,		\
+		.tristate	= PMUX_TRI_##_tri,		\
+		.io		= PMUX_PIN_##_io,		\
+		.lock		= PMUX_PIN_LOCK_DEFAULT,	\
+		.od		= PMUX_PIN_OD_DEFAULT,		\
+		.ioreset	= PMUX_PIN_IO_RESET_DEFAULT,	\
+	}
+
+#define I2C_PINMUX(_pingroup, _mux, _pull, _tri, _io, _lock, _od) \
+	{							\
+		.pingroup	= PINGRP_##_pingroup,		\
+		.func		= PMUX_FUNC_##_mux,		\
+		.pull		= PMUX_PULL_##_pull,		\
+		.tristate	= PMUX_TRI_##_tri,		\
+		.io		= PMUX_PIN_##_io,		\
+		.lock		= PMUX_PIN_LOCK_##_lock,	\
+		.od		= PMUX_PIN_OD_##_od,		\
+		.ioreset	= PMUX_PIN_IO_RESET_DEFAULT,	\
+	}
+
+#define LV_PINMUX(_pingroup, _mux, _pull, _tri, _io, _lock, _ioreset) \
+	{							\
+		.pingroup	= PINGRP_##_pingroup,		\
+		.func		= PMUX_FUNC_##_mux,		\
+		.pull		= PMUX_PULL_##_pull,		\
+		.tristate	= PMUX_TRI_##_tri,		\
+		.io		= PMUX_PIN_##_io,		\
+		.lock		= PMUX_PIN_LOCK_##_lock,	\
+		.od		= PMUX_PIN_OD_DEFAULT,		\
+		.ioreset	= PMUX_PIN_IO_RESET_##_ioreset	\
+	}
+
+#define DEFAULT_PADCFG(_padgrp, _slwf, _slwr, _drvup, _drvdn, _lpmd, _schmt, _hsm) \
+	{							\
+		.padgrp		= PDRIVE_PINGROUP_##_padgrp,	\
+		.slwf		= _slwf,			\
+		.slwr		= _slwr,			\
+		.drvup		= _drvup,			\
+		.drvdn		= _drvdn,			\
+		.lpmd		= PGRP_LPMD_##_lpmd,		\
+		.schmt		= PGRP_SCHMT_##_schmt,		\
+		.hsm		= PGRP_HSM_##_hsm,		\
+	}
+
+static struct pingroup_config tamonten_ng_pinmux_common[] = {
+	/* SDMMC1 pinmux */
+	DEFAULT_PINMUX(SDMMC1_CLK,  SDMMC1, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(SDMMC1_CMD,  SDMMC1, UP,     NORMAL, INPUT),
+	DEFAULT_PINMUX(SDMMC1_DAT0, SDMMC1, UP,     NORMAL, INPUT),
+	DEFAULT_PINMUX(SDMMC1_DAT1, SDMMC1, UP,     NORMAL, INPUT),
+	DEFAULT_PINMUX(SDMMC1_DAT2, SDMMC1, UP,     NORMAL, INPUT),
+	DEFAULT_PINMUX(SDMMC1_DAT3, SDMMC1, UP,     NORMAL, INPUT),
+
+	/* SDMMC3 pinmux */
+	DEFAULT_PINMUX(SDMMC3_CLK,  SDMMC3, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(SDMMC3_CMD,  SDMMC3, UP,     NORMAL, INPUT),
+	DEFAULT_PINMUX(SDMMC3_DAT0, SDMMC3, UP,     NORMAL, INPUT),
+	DEFAULT_PINMUX(SDMMC3_DAT1, SDMMC3, UP,     NORMAL, INPUT),
+	DEFAULT_PINMUX(SDMMC3_DAT2, SDMMC3, UP,     NORMAL, INPUT),
+	DEFAULT_PINMUX(SDMMC3_DAT3, SDMMC3, UP,     NORMAL, INPUT),
+	DEFAULT_PINMUX(SDMMC3_DAT4, SDMMC3, UP,     NORMAL, INPUT),
+	DEFAULT_PINMUX(SDMMC3_DAT5, SDMMC3, UP,     NORMAL, INPUT),
+	DEFAULT_PINMUX(SDMMC3_DAT6, SDMMC3, UP,     NORMAL, INPUT),
+	DEFAULT_PINMUX(SDMMC3_DAT7, SDMMC3, UP,     NORMAL, INPUT),
+	DEFAULT_PINMUX(GMI_IORDY,   RSVD1,  UP,     NORMAL, INPUT),
+	DEFAULT_PINMUX(GMI_CS6_N,   RSVD1,  UP,     NORMAL, INPUT),
+
+	/* SDMMC4 pinmux */
+	LV_PINMUX(SDMMC4_CLK,   SDMMC4, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+	LV_PINMUX(SDMMC4_CMD,   SDMMC4, UP,     NORMAL, INPUT, DISABLE, DISABLE),
+	LV_PINMUX(SDMMC4_DAT0,  SDMMC4, UP,     NORMAL, INPUT, DISABLE, DISABLE),
+	LV_PINMUX(SDMMC4_DAT1,  SDMMC4, UP,     NORMAL, INPUT, DISABLE, DISABLE),
+	LV_PINMUX(SDMMC4_DAT2,  SDMMC4, UP,     NORMAL, INPUT, DISABLE, DISABLE),
+	LV_PINMUX(SDMMC4_DAT3,  SDMMC4, UP,     NORMAL, INPUT, DISABLE, DISABLE),
+	LV_PINMUX(SDMMC4_DAT4,  SDMMC4, UP,     NORMAL, INPUT, DISABLE, DISABLE),
+	LV_PINMUX(SDMMC4_DAT5,  SDMMC4, UP,     NORMAL, INPUT, DISABLE, DISABLE),
+	LV_PINMUX(SDMMC4_DAT6,  SDMMC4, UP,     NORMAL, INPUT, DISABLE, DISABLE),
+	LV_PINMUX(SDMMC4_DAT7,  SDMMC4, UP,     NORMAL, INPUT, DISABLE, DISABLE),
+	LV_PINMUX(SDMMC4_RST_N, RSVD1,  DOWN,   NORMAL, INPUT, DISABLE, DISABLE),
+
+	/* I2C1 pinmux */
+	I2C_PINMUX(GEN1_I2C_SCL, I2C1, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
+	I2C_PINMUX(GEN1_I2C_SDA, I2C1, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
+
+	/* I2C2 pinmux */
+	I2C_PINMUX(GEN2_I2C_SCL, I2C2, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
+	I2C_PINMUX(GEN2_I2C_SDA, I2C2, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
+
+	/* I2C3 pinmux */
+	I2C_PINMUX(CAM_I2C_SCL, I2C3, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
+	I2C_PINMUX(CAM_I2C_SDA, I2C3, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
+
+	/* I2C4 pinmux */
+	I2C_PINMUX(DDC_SCL, I2C4, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
+	I2C_PINMUX(DDC_SDA, I2C4, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
+
+	/* Power I2C pinmux */
+	I2C_PINMUX(PWR_I2C_SCL, I2CPWR, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
+	I2C_PINMUX(PWR_I2C_SDA, I2CPWR, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
+
+	/* UART1 */
+	DEFAULT_PINMUX(ULPI_DATA0, UARTA, NORMAL, NORMAL, OUTPUT),
+	DEFAULT_PINMUX(ULPI_DATA1, UARTA, NORMAL, NORMAL, INPUT),
+
+	/* UART2 */
+	DEFAULT_PINMUX(UART2_RXD,   UARTB, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(UART2_TXD,   UARTB, NORMAL, NORMAL, OUTPUT),
+
+	/* UART3 */
+	DEFAULT_PINMUX(UART3_TXD,   UARTC, NORMAL, NORMAL, OUTPUT),
+	DEFAULT_PINMUX(UART3_RXD,   UARTC, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(UART3_CTS_N, UARTC, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(UART3_RTS_N, UARTC, NORMAL, NORMAL, OUTPUT),
+
+	/* UART4 */
+	DEFAULT_PINMUX(ULPI_CLK, UARTD, NORMAL, NORMAL, OUTPUT),
+	DEFAULT_PINMUX(ULPI_DIR, UARTD, UP,     NORMAL, INPUT),
+	DEFAULT_PINMUX(ULPI_NXT, UARTD, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(ULPI_STP, UARTD, NORMAL, NORMAL, OUTPUT),
+
+	/* DAP */
+	DEFAULT_PINMUX(CLK1_OUT, EXTPERIPH1, NORMAL, NORMAL, INPUT),
+
+	/* I2S1 */
+	DEFAULT_PINMUX(DAP2_FS,   I2S1, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(DAP2_DIN,  I2S1, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(DAP2_DOUT, I2S1, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(DAP2_SCLK, I2S1, NORMAL, NORMAL, INPUT),
+
+	/* SPDIF */
+	DEFAULT_PINMUX(SPDIF_IN,  SPDIF, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(SPDIF_OUT, SPDIF, NORMAL, NORMAL, OUTPUT),
+
+	/* I2S2 */
+	DEFAULT_PINMUX(DAP3_FS,   I2S2, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(DAP3_DIN,  I2S2, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(DAP3_DOUT, I2S2, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(DAP3_SCLK, I2S2, NORMAL, NORMAL, INPUT),
+
+	/* DAP4 */
+	DEFAULT_PINMUX(DAP4_FS,   I2S3, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(DAP4_DIN,  I2S3, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(DAP4_SCLK, I2S3, NORMAL, NORMAL, INPUT),
+
+	/* Tamonten GPIO */
+	DEFAULT_PINMUX(GPIO_PV2,   RSVD1, NORMAL, NORMAL, OUTPUT),
+	DEFAULT_PINMUX(GPIO_PV3,   RSVD1, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(SPI2_CS1_N, RSVD1, NORMAL, NORMAL, INPUT),
+
+	/* LCD */
+	DEFAULT_PINMUX(LCD_PWR1,  DISPA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_PWR2,  DISPA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_SDIN,  DISPA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_SDOUT, DISPA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_WR_N,  DISPA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_CS0_N, DISPA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_DC0,   DISPA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_SCK,   DISPA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_PWR0,  DISPA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_PCLK,  DISPA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_DE,    DISPA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_HSYNC, DISPA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_VSYNC, DISPA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_D0,    DISPA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_D1,    DISPA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_D2,    DISPA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_D3,    DISPA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_D4,    DISPA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_D5,    DISPA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_D6,    DISPA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_D7,    DISPA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_D8,    DISPA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_D9,    DISPA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_D10,   DISPA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_D11,   DISPA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_D12,   DISPA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_D13,   DISPA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_D14,   DISPA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_D15,   DISPA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_D16,   DISPA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_D17,   DISPA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_D18,   DISPA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_D19,   DISPA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_D20,   DISPA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_D21,   DISPA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_D22,   DISPA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_D23,   DISPA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_CS1_N, DISPA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_M1,    DISPA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_DC1,   DISPA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(CRT_HSYNC, CRT,   NORMAL, NORMAL, OUTPUT),
+	DEFAULT_PINMUX(CRT_VSYNC, CRT,   NORMAL, NORMAL, OUTPUT),
+
+	/* BT656 */
+	LV_PINMUX(VI_MCLK,  VI,    NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+	LV_PINMUX(VI_PCLK,  VI,    NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+	LV_PINMUX(VI_HSYNC, VI,    NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+	LV_PINMUX(VI_VSYNC, VI,    NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+	LV_PINMUX(VI_D2,    VI,    NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+	LV_PINMUX(VI_D3,    VI,    NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+	LV_PINMUX(VI_D4,    VI,    NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+	LV_PINMUX(VI_D5,    VI,    NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+	LV_PINMUX(VI_D6,    VI,    NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+	LV_PINMUX(VI_D7,    VI,    NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+	LV_PINMUX(VI_D8,    VI,    NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+	LV_PINMUX(VI_D9,    VI,    NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+	LV_PINMUX(VI_D11,   RSVD1, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+
+	/* GPIOs */
+	DEFAULT_PINMUX(GPIO_PU5, RSVD1, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(GPIO_PU6, RSVD1, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(GMI_AD12, RSVD1, NORMAL, NORMAL, INPUT),
+
+	/* LCD BL */
+	DEFAULT_PINMUX(GMI_AD8,  PWM0,  NORMAL, NORMAL, OUTPUT),
+	DEFAULT_PINMUX(GMI_AD10, RSVD4, NORMAL, NORMAL, OUTPUT),
+
+	/* SPI4 */
+	DEFAULT_PINMUX(GMI_A16, SPI4, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(GMI_A17, SPI4, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(GMI_A18, SPI4, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(GMI_A19, SPI4, NORMAL, NORMAL, INPUT),
+
+	/* Video input GPIO */
+	DEFAULT_PINMUX(GPIO_PCC1, RSVD1, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(GPIO_PBB0, RSVD1, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(GPIO_PBB7, RSVD1, NORMAL, NORMAL, INPUT),
+
+	/* Sensor GPIO */
+	DEFAULT_PINMUX(GPIO_PCC2, RSVD1, NORMAL, NORMAL, INPUT),
+
+	/* JTAG */
+	DEFAULT_PINMUX(JTAG_RTCK, RTCK, NORMAL, NORMAL, OUTPUT),
+
+	/* Power controls */
+	DEFAULT_PINMUX(GMI_CS2_N, RSVD1, NORMAL, NORMAL, INPUT),
+
+	/* SPI1 */
+	DEFAULT_PINMUX(SPI1_MOSI,  SPI1, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(SPI1_SCK,   SPI1, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(SPI1_CS0_N, SPI1, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(SPI1_MISO,  SPI1, NORMAL, NORMAL, INPUT),
+
+	/* PMU */
+	DEFAULT_PINMUX(GPIO_PV0,    RSVD1,  UP,     NORMAL, INPUT),
+	DEFAULT_PINMUX(SYS_CLK_REQ, SYSCLK, NORMAL, NORMAL, OUTPUT),
+	DEFAULT_PINMUX(CLK_32K_IN,  SYSCLK, NORMAL, NORMAL, INPUT),
+
+	/* PCI */
+	DEFAULT_PINMUX(PEX_L0_PRSNT_N,  PCIE, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(PEX_L0_RST_N,    PCIE, NORMAL, NORMAL, OUTPUT),
+	DEFAULT_PINMUX(PEX_L0_CLKREQ_N, PCIE, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(PEX_WAKE_N,      PCIE, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(PEX_L1_PRSNT_N,  PCIE, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(PEX_L1_RST_N,    PCIE, NORMAL, NORMAL, OUTPUT),
+	DEFAULT_PINMUX(PEX_L1_CLKREQ_N, PCIE, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(PEX_L2_PRSNT_N,  PCIE, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(PEX_L2_RST_N,    PCIE, NORMAL, NORMAL, OUTPUT),
+	DEFAULT_PINMUX(PEX_L2_CLKREQ_N, PCIE, NORMAL, NORMAL, INPUT),
+
+	/* HDMI */
+	DEFAULT_PINMUX(HDMI_CEC, CEC,   NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(HDMI_INT, RSVD1, NORMAL, TRISTATE, INPUT),
+};
+
+static struct pingroup_config unused_pins_lowpower[] = {
+	/* UART1 - NC */
+	DEFAULT_PINMUX(ULPI_DATA2, UARTA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(ULPI_DATA3, UARTA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(ULPI_DATA4, UARTA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(ULPI_DATA5, UARTA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(ULPI_DATA6, UARTA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(ULPI_DATA7, UARTA, NORMAL, NORMAL, INPUT),
+
+	/* UART2 - NC */
+	DEFAULT_PINMUX(UART2_RTS_N, UARTB, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(UART2_CTS_N, UARTB, NORMAL, NORMAL, INPUT),
+
+	/* DAP - NC */
+	DEFAULT_PINMUX(CLK1_REQ,  RSVD1, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(CLK3_OUT,  RSVD1, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(CLK3_REQ,  RSVD1, NORMAL, NORMAL, INPUT),
+
+	/* DAP4 - NC */
+	DEFAULT_PINMUX(DAP4_DOUT, I2S3, NORMAL, NORMAL, INPUT),
+
+	/* Tamonten GPIO - NC */
+	DEFAULT_PINMUX(CLK2_OUT, EXTPERIPH2, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(CLK2_REQ, DAP,        NORMAL, NORMAL, INPUT),
+
+	/* BT656 - NC */
+	LV_PINMUX(VI_D0,  RSVD1, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+	LV_PINMUX(VI_D1,  RSVD1, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+	LV_PINMUX(VI_D10, RSVD1, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+
+	/* GPIO - NC */
+	DEFAULT_PINMUX(GPIO_PU0, RSVD1, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(GPIO_PU1, RSVD1, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(GPIO_PU2, RSVD1, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(GPIO_PU3, RSVD1, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(GPIO_PU4, RSVD1, NORMAL, NORMAL, INPUT),
+
+	/* Video input - NC */
+	DEFAULT_PINMUX(CAM_MCLK,  RSVD1, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(GPIO_PBB3, RSVD1, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(GPIO_PBB5, RSVD1, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(GPIO_PBB6, RSVD1, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(KB_ROW11,  RSVD1, NORMAL, NORMAL, INPUT),
+
+	/* KBC keys - NC */
+	DEFAULT_PINMUX(KB_ROW0,  KBC, UP, NORMAL, INPUT),
+	DEFAULT_PINMUX(KB_ROW1,  KBC, UP, NORMAL, INPUT),
+	DEFAULT_PINMUX(KB_ROW2,  KBC, UP, NORMAL, INPUT),
+	DEFAULT_PINMUX(KB_ROW3,  KBC, UP, NORMAL, INPUT),
+	DEFAULT_PINMUX(KB_ROW4,  KBC, UP, NORMAL, INPUT),
+	DEFAULT_PINMUX(KB_ROW5,  KBC, UP, NORMAL, INPUT),
+	DEFAULT_PINMUX(KB_ROW6,  KBC, UP, NORMAL, INPUT),
+	DEFAULT_PINMUX(KB_ROW7,  KBC, UP, NORMAL, INPUT),
+	DEFAULT_PINMUX(KB_ROW8,  KBC, UP, NORMAL, INPUT),
+	DEFAULT_PINMUX(KB_ROW9,  KBC, UP, NORMAL, INPUT),
+	DEFAULT_PINMUX(KB_ROW10, KBC, UP, NORMAL, INPUT),
+	DEFAULT_PINMUX(KB_ROW12, KBC, UP, NORMAL, INPUT),
+	DEFAULT_PINMUX(KB_ROW13, KBC, UP, NORMAL, INPUT),
+	DEFAULT_PINMUX(KB_ROW14, KBC, UP, NORMAL, INPUT),
+	DEFAULT_PINMUX(KB_ROW15, KBC, UP, NORMAL, INPUT),
+	DEFAULT_PINMUX(KB_COL0,  KBC, UP, NORMAL, INPUT),
+	DEFAULT_PINMUX(KB_COL1,  KBC, UP, NORMAL, INPUT),
+	DEFAULT_PINMUX(KB_COL2,  KBC, UP, NORMAL, INPUT),
+	DEFAULT_PINMUX(KB_COL3,  KBC, UP, NORMAL, INPUT),
+	DEFAULT_PINMUX(KB_COL4,  KBC, UP, NORMAL, INPUT),
+	DEFAULT_PINMUX(KB_COL5,  KBC, UP, NORMAL, INPUT),
+	DEFAULT_PINMUX(KB_COL6,  KBC, UP, NORMAL, INPUT),
+	DEFAULT_PINMUX(KB_COL7,  KBC, UP, NORMAL, INPUT),
+
+	/* PMU - NC */
+	DEFAULT_PINMUX(CLK_32K_OUT, RSVD1, NORMAL, NORMAL, INPUT),
+
+	/* Power rails GPIO - NC */
+	DEFAULT_PINMUX(SPI2_SCK,  RSVD1, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(GPIO_PBB4, RSVD1, NORMAL, NORMAL, INPUT),
+
+	/* Others - NC */
+	DEFAULT_PINMUX(GMI_WP_N,   RSVD1, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(GPIO_PV1,   RSVD1, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(GMI_WAIT,   NAND, UP,     TRISTATE, OUTPUT),
+	DEFAULT_PINMUX(GMI_ADV_N,  NAND, NORMAL, TRISTATE, OUTPUT),
+	DEFAULT_PINMUX(GMI_CLK,    NAND, NORMAL, TRISTATE, OUTPUT),
+	DEFAULT_PINMUX(GMI_CS3_N,  NAND, NORMAL, NORMAL,   OUTPUT),
+	DEFAULT_PINMUX(GMI_CS7_N,  NAND, UP,     NORMAL,   INPUT),
+	DEFAULT_PINMUX(GMI_AD0,    NAND, NORMAL, TRISTATE, OUTPUT),
+	DEFAULT_PINMUX(GMI_AD1,    NAND, NORMAL, TRISTATE, OUTPUT),
+	DEFAULT_PINMUX(GMI_AD2,    NAND, NORMAL, TRISTATE, OUTPUT),
+	DEFAULT_PINMUX(GMI_AD3,    NAND, NORMAL, TRISTATE, OUTPUT),
+	DEFAULT_PINMUX(GMI_AD4,    NAND, NORMAL, TRISTATE, OUTPUT),
+	DEFAULT_PINMUX(GMI_AD5,    NAND, NORMAL, TRISTATE, OUTPUT),
+	DEFAULT_PINMUX(GMI_AD6,    NAND, NORMAL, TRISTATE, OUTPUT),
+	DEFAULT_PINMUX(GMI_AD7,    NAND, NORMAL, TRISTATE, OUTPUT),
+	DEFAULT_PINMUX(GMI_AD9,    PWM1, NORMAL, NORMAL,   OUTPUT),
+	DEFAULT_PINMUX(GMI_AD11,   NAND, NORMAL, NORMAL,   OUTPUT),
+	DEFAULT_PINMUX(GMI_AD13,   NAND, UP,     NORMAL,   INPUT),
+	DEFAULT_PINMUX(GMI_WR_N,   NAND, NORMAL, TRISTATE, OUTPUT),
+	DEFAULT_PINMUX(GMI_OE_N,   NAND, NORMAL, TRISTATE, OUTPUT),
+	DEFAULT_PINMUX(GMI_DQS,    NAND, NORMAL, TRISTATE, OUTPUT),
+};
+
+static struct padctrl_config tamonten_ng_padctrl[] = {
+	/* (_padgrp, _slwf, _slwr, _drvup, _drvdn, _lpmd, _schmt, _hsm) */
+	DEFAULT_PADCFG(SDIO1, SDIOCFG_DRVUP_SLWF, SDIOCFG_DRVDN_SLWR,
+		SDIOCFG_DRVUP, SDIOCFG_DRVDN, NONE, DISABLE, DISABLE),
+};
+#endif	/* _PINMUX_CONFIG_TAMONTEN_NG_H_ */
diff --git a/board/avionic-design/common/tamonten-ng.c b/board/avionic-design/common/tamonten-ng.c
new file mode 100644
index 0000000000..9d395c676e
--- /dev/null
+++ b/board/avionic-design/common/tamonten-ng.c
@@ -0,0 +1,85 @@
+/*
+ * (C) Copyright 2013
+ * Avionic Design GmbH <www.avionic-design.de>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/pinmux.h>
+#include <asm/arch/gp_padctrl.h>
+#include <asm/arch/gpio.h>
+#include <asm/gpio.h>
+#include "pinmux-config-tamonten-ng.h"
+#include <i2c.h>
+
+#define PMU_I2C_ADDRESS		0x2D
+
+#define PMU_REG_LDO5		0x32
+
+#define PMU_REG_LDO_HIGH_POWER	1
+
+/* Voltage selection for the LDOs with 100mV resolution */
+#define PMU_REG_LDO_SEL_100(mV)	((((mV - 1000) / 100) + 2) << 2)
+
+#define PMU_REG_LDO_100(st, mV)	(PMU_REG_LDO_##st | PMU_REG_LDO_SEL_100(mV))
+
+#define PMU_LDO5(st, mV)	PMU_REG_LDO_100(st, mV)
+
+void pinmux_init(void)
+{
+	pinmux_config_table(tamonten_ng_pinmux_common,
+			    ARRAY_SIZE(tamonten_ng_pinmux_common));
+	pinmux_config_table(unused_pins_lowpower,
+			    ARRAY_SIZE(unused_pins_lowpower));
+
+	/* Initialize any non-default pad configs (APB_MISC_GP regs) */
+	padgrp_config_table(tamonten_ng_padctrl,
+			    ARRAY_SIZE(tamonten_ng_padctrl));
+}
+
+void gpio_early_init(void)
+{
+	/* Turn on the alive signal */
+	gpio_request(GPIO_PV2, "ALIVE");
+	gpio_direction_output(GPIO_PV2, 1);
+
+	/* Remove the reset on the external periph */
+	gpio_request(GPIO_PI4, "nRST_PERIPH");
+	gpio_direction_output(GPIO_PI4, 1);
+}
+
+void pmu_write(uchar reg, uchar data)
+{
+	i2c_set_bus_num(4);	/* PMU is on bus 4 */
+	i2c_write(PMU_I2C_ADDRESS, reg, 1, &data, 1);
+}
+
+/*
+ * Do I2C/PMU writes to bring up SD card bus power
+ *
+ */
+void board_sdmmc_voltage_init(void)
+{
+	/* Enable LDO5 with 3.3v for SDMMC3 */
+	pmu_write(PMU_REG_LDO5, PMU_LDO5(HIGH_POWER, 3300));
+
+	/* Switch the power on */
+	gpio_request(GPIO_PJ2, "EN_3V3_EMMC");
+	gpio_direction_output(GPIO_PJ2, 1);
+}
+
+/*
+ * Routine: pin_mux_mmc
+ * Description: setup the MMC muxes, power rails, etc.
+ */
+void pin_mux_mmc(void)
+{
+	/*
+	 * NOTE: We don't do mmc-specific pin muxes here.
+	 * They were done globally in pinmux_init().
+	 */
+
+	/* Bring up the SDIO1 power rail */
+	board_sdmmc_voltage_init();
+}
diff --git a/board/avionic-design/medcom-wide/Makefile b/board/avionic-design/medcom-wide/Makefile
index 3077319ae2..bcf7ccfe2a 100644
--- a/board/avionic-design/medcom-wide/Makefile
+++ b/board/avionic-design/medcom-wide/Makefile
@@ -7,28 +7,6 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
+obj-y	:= ../common/tamonten.o
 
-$(shell mkdir -p $(obj)../common $(obj)../../nvidia/common)
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS-y	:= ../common/tamonten.o
-
-include ../../nvidia/common/common.mk
-
-COBJS	:= $(COBJS-y)
-SRCS	:= $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+include $(srctree)/board/nvidia/common/common.mk
diff --git a/board/avionic-design/plutux/Makefile b/board/avionic-design/plutux/Makefile
index 3077319ae2..bcf7ccfe2a 100644
--- a/board/avionic-design/plutux/Makefile
+++ b/board/avionic-design/plutux/Makefile
@@ -7,28 +7,6 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
+obj-y	:= ../common/tamonten.o
 
-$(shell mkdir -p $(obj)../common $(obj)../../nvidia/common)
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS-y	:= ../common/tamonten.o
-
-include ../../nvidia/common/common.mk
-
-COBJS	:= $(COBJS-y)
-SRCS	:= $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+include $(srctree)/board/nvidia/common/common.mk
diff --git a/board/avionic-design/tec-ng/Makefile b/board/avionic-design/tec-ng/Makefile
new file mode 100644
index 0000000000..a556b92e8e
--- /dev/null
+++ b/board/avionic-design/tec-ng/Makefile
@@ -0,0 +1,10 @@
+#
+# (C) Copyright 2013
+# Avionic Design GmbH <www.avionic-design.de>
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y	:= ../common/tamonten-ng.o
+
+include $(srctree)/board/nvidia/common/common.mk
diff --git a/board/avionic-design/tec/Makefile b/board/avionic-design/tec/Makefile
index 3077319ae2..bcf7ccfe2a 100644
--- a/board/avionic-design/tec/Makefile
+++ b/board/avionic-design/tec/Makefile
@@ -7,28 +7,6 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
+obj-y	:= ../common/tamonten.o
 
-$(shell mkdir -p $(obj)../common $(obj)../../nvidia/common)
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS-y	:= ../common/tamonten.o
-
-include ../../nvidia/common/common.mk
-
-COBJS	:= $(COBJS-y)
-SRCS	:= $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+include $(srctree)/board/nvidia/common/common.mk
diff --git a/board/avnet/fx12mm/.gitignore b/board/avnet/fx12mm/.gitignore
deleted file mode 100644
index b644f59941..0000000000
--- a/board/avnet/fx12mm/.gitignore
+++ /dev/null
@@ -1 +0,0 @@
-config.tmp
diff --git a/board/avnet/fx12mm/Makefile b/board/avnet/fx12mm/Makefile
index 2dd48b67f1..618b42f891 100644
--- a/board/avnet/fx12mm/Makefile
+++ b/board/avnet/fx12mm/Makefile
@@ -6,6 +6,6 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-COBJS	+= $(BOARD).o
+obj-y	+= fx12mm.o
 
-include $(SRCTREE)/board/xilinx/ppc405-generic/Makefile
+include $(srctree)/board/xilinx/ppc405-generic/Makefile
diff --git a/board/avnet/v5fx30teval/.gitignore b/board/avnet/v5fx30teval/.gitignore
deleted file mode 100644
index f6418a0c50..0000000000
--- a/board/avnet/v5fx30teval/.gitignore
+++ /dev/null
@@ -1 +0,0 @@
-/config.tmp
diff --git a/board/avnet/v5fx30teval/Makefile b/board/avnet/v5fx30teval/Makefile
index 51b777c234..8c41af02d4 100644
--- a/board/avnet/v5fx30teval/Makefile
+++ b/board/avnet/v5fx30teval/Makefile
@@ -6,6 +6,6 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-COBJS	+= $(BOARD).o
+obj-y	+= v5fx30teval.o
 
-include $(SRCTREE)/board/xilinx/ppc440-generic/Makefile
+include $(srctree)/board/xilinx/ppc440-generic/Makefile
diff --git a/board/balloon3/Makefile b/board/balloon3/Makefile
index 34e2542213..d7fb5e036e 100644
--- a/board/balloon3/Makefile
+++ b/board/balloon3/Makefile
@@ -6,23 +6,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	:= balloon3.o
-
-SRCS	:= $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	:= balloon3.o
diff --git a/board/balloon3/balloon3.c b/board/balloon3/balloon3.c
index ecbac16d59..04e0574658 100644
--- a/board/balloon3/balloon3.c
+++ b/board/balloon3/balloon3.c
@@ -13,6 +13,7 @@
 #include <asm/io.h>
 #include <spartan3.h>
 #include <command.h>
+#include <usb.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -59,7 +60,7 @@ void dram_init_banksize(void)
 }
 
 #ifdef	CONFIG_CMD_USB
-int usb_board_init(void)
+int board_usb_init(int index, enum usb_init_type init)
 {
 	writel((readl(UHCHR) | UHCHR_PCPL | UHCHR_PSPL) &
 		~(UHCHR_SSEP0 | UHCHR_SSEP1 | UHCHR_SSEP2 | UHCHR_SSE),
@@ -90,9 +91,9 @@ int usb_board_init(void)
 	return 0;
 }
 
-void usb_board_init_fail(void)
+int board_usb_cleanup(int index, enum usb_init_type init)
 {
-	return;
+	return 0;
 }
 
 void usb_board_stop(void)
diff --git a/board/barco/titanium/Makefile b/board/barco/titanium/Makefile
new file mode 100644
index 0000000000..0ad4cb9b15
--- /dev/null
+++ b/board/barco/titanium/Makefile
@@ -0,0 +1,9 @@
+#
+# Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
+#
+# (C) Copyright 2011 Freescale Semiconductor, Inc.
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y  := titanium.o
diff --git a/board/freescale/titanium/imximage.cfg b/board/barco/titanium/imximage.cfg
index 7219256ae0..7219256ae0 100644
--- a/board/freescale/titanium/imximage.cfg
+++ b/board/barco/titanium/imximage.cfg
diff --git a/board/barco/titanium/titanium.c b/board/barco/titanium/titanium.c
new file mode 100644
index 0000000000..84a7b849ad
--- /dev/null
+++ b/board/barco/titanium/titanium.c
@@ -0,0 +1,317 @@
+/*
+ * Copyright (C) 2013 Stefan Roese <sr@denx.de>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/iomux.h>
+#include <asm/arch/mx6-pins.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/gpio.h>
+#include <asm/imx-common/iomux-v3.h>
+#include <asm/imx-common/mxc_i2c.h>
+#include <asm/imx-common/boot_mode.h>
+#include <mmc.h>
+#include <fsl_esdhc.h>
+#include <micrel.h>
+#include <miiphy.h>
+#include <netdev.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define UART_PAD_CTRL  (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |	\
+			PAD_CTL_DSE_40ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
+
+#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP  | PAD_CTL_SPEED_LOW |	\
+			PAD_CTL_DSE_80ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
+
+#define ENET_PAD_CTRL  (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED	  |	\
+			PAD_CTL_DSE_40ohm   | PAD_CTL_HYS)
+
+#define I2C_PAD_CTRL	(PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |	\
+			 PAD_CTL_DSE_40ohm | PAD_CTL_HYS |		\
+			 PAD_CTL_ODE | PAD_CTL_SRE_FAST)
+
+int dram_init(void)
+{
+	gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
+
+	return 0;
+}
+
+iomux_v3_cfg_t const uart1_pads[] = {
+	MX6_PAD_SD3_DAT6__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
+	MX6_PAD_SD3_DAT7__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+iomux_v3_cfg_t const uart2_pads[] = {
+	MX6_PAD_EIM_D26__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
+	MX6_PAD_EIM_D27__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+iomux_v3_cfg_t const uart4_pads[] = {
+	MX6_PAD_CSI0_DAT12__UART4_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
+	MX6_PAD_CSI0_DAT13__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
+
+struct i2c_pads_info i2c_pad_info0 = {
+	.scl = {
+		.i2c_mode  = MX6_PAD_CSI0_DAT9__I2C1_SCL | PC,
+		.gpio_mode = MX6_PAD_CSI0_DAT9__GPIO5_IO27 | PC,
+		.gp = IMX_GPIO_NR(5, 27)
+	},
+	.sda = {
+		 .i2c_mode = MX6_PAD_CSI0_DAT8__I2C1_SDA | PC,
+		 .gpio_mode = MX6_PAD_CSI0_DAT8__GPIO5_IO26 | PC,
+		 .gp = IMX_GPIO_NR(5, 26)
+	 }
+};
+
+struct i2c_pads_info i2c_pad_info2 = {
+	.scl = {
+		.i2c_mode = MX6_PAD_GPIO_3__I2C3_SCL | PC,
+		.gpio_mode = MX6_PAD_GPIO_3__GPIO1_IO03 | PC,
+		.gp = IMX_GPIO_NR(1, 3)
+	},
+	.sda = {
+		 .i2c_mode = MX6_PAD_GPIO_16__I2C3_SDA | PC,
+		 .gpio_mode = MX6_PAD_GPIO_16__GPIO7_IO11 | PC,
+		 .gp = IMX_GPIO_NR(7, 11)
+	 }
+};
+
+iomux_v3_cfg_t const usdhc3_pads[] = {
+	MX6_PAD_SD3_CLK__SD3_CLK   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD3_CMD__SD3_CMD   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD3_DAT5__GPIO7_IO00    | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
+};
+
+iomux_v3_cfg_t const enet_pads1[] = {
+	MX6_PAD_ENET_MDIO__ENET_MDIO		| MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_ENET_MDC__ENET_MDC		| MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_RGMII_TXC__RGMII_TXC	| MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_RGMII_TD0__RGMII_TD0	| MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_RGMII_TD1__RGMII_TD1	| MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_RGMII_TD2__RGMII_TD2	| MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_RGMII_TD3__RGMII_TD3	| MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL	| MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_ENET_REF_CLK__ENET_TX_CLK	| MUX_PAD_CTRL(ENET_PAD_CTRL),
+	/* pin 35 - 1 (PHY_AD2) on reset */
+	MX6_PAD_RGMII_RXC__GPIO6_IO30		| MUX_PAD_CTRL(NO_PAD_CTRL),
+	/* pin 32 - 1 - (MODE0) all */
+	MX6_PAD_RGMII_RD0__GPIO6_IO25		| MUX_PAD_CTRL(NO_PAD_CTRL),
+	/* pin 31 - 1 - (MODE1) all */
+	MX6_PAD_RGMII_RD1__GPIO6_IO27		| MUX_PAD_CTRL(NO_PAD_CTRL),
+	/* pin 28 - 1 - (MODE2) all */
+	MX6_PAD_RGMII_RD2__GPIO6_IO28		| MUX_PAD_CTRL(NO_PAD_CTRL),
+	/* pin 27 - 1 - (MODE3) all */
+	MX6_PAD_RGMII_RD3__GPIO6_IO29		| MUX_PAD_CTRL(NO_PAD_CTRL),
+	/* pin 33 - 1 - (CLK125_EN) 125Mhz clockout enabled */
+	MX6_PAD_RGMII_RX_CTL__GPIO6_IO24		| MUX_PAD_CTRL(NO_PAD_CTRL),
+	/* pin 42 PHY nRST */
+	MX6_PAD_EIM_D23__GPIO3_IO23		| MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+iomux_v3_cfg_t const enet_pads2[] = {
+	MX6_PAD_RGMII_RXC__RGMII_RXC	| MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_RGMII_RD0__RGMII_RD0	| MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_RGMII_RD1__RGMII_RD1	| MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_RGMII_RD2__RGMII_RD2	| MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_RGMII_RD3__RGMII_RD3	| MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL	| MUX_PAD_CTRL(ENET_PAD_CTRL),
+};
+
+iomux_v3_cfg_t nfc_pads[] = {
+	MX6_PAD_NANDF_CLE__NAND_CLE		| MUX_PAD_CTRL(NO_PAD_CTRL),
+	MX6_PAD_NANDF_ALE__NAND_ALE		| MUX_PAD_CTRL(NO_PAD_CTRL),
+	MX6_PAD_NANDF_WP_B__NAND_WP_B	| MUX_PAD_CTRL(NO_PAD_CTRL),
+	MX6_PAD_NANDF_RB0__NAND_READY_B	| MUX_PAD_CTRL(NO_PAD_CTRL),
+	MX6_PAD_NANDF_CS0__NAND_CE0_B		| MUX_PAD_CTRL(NO_PAD_CTRL),
+	MX6_PAD_NANDF_CS1__NAND_CE1_B		| MUX_PAD_CTRL(NO_PAD_CTRL),
+	MX6_PAD_NANDF_CS2__NAND_CE2_B		| MUX_PAD_CTRL(NO_PAD_CTRL),
+	MX6_PAD_NANDF_CS3__NAND_CE3_B		| MUX_PAD_CTRL(NO_PAD_CTRL),
+	MX6_PAD_SD4_CMD__NAND_RE_B		| MUX_PAD_CTRL(NO_PAD_CTRL),
+	MX6_PAD_SD4_CLK__NAND_WE_B		| MUX_PAD_CTRL(NO_PAD_CTRL),
+	MX6_PAD_NANDF_D0__NAND_DATA00		| MUX_PAD_CTRL(NO_PAD_CTRL),
+	MX6_PAD_NANDF_D1__NAND_DATA01		| MUX_PAD_CTRL(NO_PAD_CTRL),
+	MX6_PAD_NANDF_D2__NAND_DATA02		| MUX_PAD_CTRL(NO_PAD_CTRL),
+	MX6_PAD_NANDF_D3__NAND_DATA03		| MUX_PAD_CTRL(NO_PAD_CTRL),
+	MX6_PAD_NANDF_D4__NAND_DATA04		| MUX_PAD_CTRL(NO_PAD_CTRL),
+	MX6_PAD_NANDF_D5__NAND_DATA05		| MUX_PAD_CTRL(NO_PAD_CTRL),
+	MX6_PAD_NANDF_D6__NAND_DATA06		| MUX_PAD_CTRL(NO_PAD_CTRL),
+	MX6_PAD_NANDF_D7__NAND_DATA07		| MUX_PAD_CTRL(NO_PAD_CTRL),
+	MX6_PAD_SD4_DAT0__NAND_DQS		| MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+static void setup_gpmi_nand(void)
+{
+	struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+
+	/* config gpmi nand iomux */
+	imx_iomux_v3_setup_multiple_pads(nfc_pads,
+					 ARRAY_SIZE(nfc_pads));
+
+	/* config gpmi and bch clock to 100 MHz */
+	clrsetbits_le32(&mxc_ccm->cs2cdr,
+			MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK |
+			MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK |
+			MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK,
+			MXC_CCM_CS2CDR_ENFC_CLK_PODF(0) |
+			MXC_CCM_CS2CDR_ENFC_CLK_PRED(3) |
+			MXC_CCM_CS2CDR_ENFC_CLK_SEL(3));
+
+	/* enable gpmi and bch clock gating */
+	setbits_le32(&mxc_ccm->CCGR4,
+		     MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
+		     MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
+		     MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
+		     MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
+		     MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET);
+
+	/* enable apbh clock gating */
+	setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK);
+}
+
+static void setup_iomux_enet(void)
+{
+	gpio_direction_output(IMX_GPIO_NR(3, 23), 0);
+	gpio_direction_output(IMX_GPIO_NR(6, 30), 1);
+	gpio_direction_output(IMX_GPIO_NR(6, 25), 1);
+	gpio_direction_output(IMX_GPIO_NR(6, 27), 1);
+	gpio_direction_output(IMX_GPIO_NR(6, 28), 1);
+	gpio_direction_output(IMX_GPIO_NR(6, 29), 1);
+	imx_iomux_v3_setup_multiple_pads(enet_pads1, ARRAY_SIZE(enet_pads1));
+	gpio_direction_output(IMX_GPIO_NR(6, 24), 1);
+
+	/* Need delay 10ms according to KSZ9021 spec */
+	udelay(1000 * 10);
+	gpio_set_value(IMX_GPIO_NR(3, 23), 1);
+
+	imx_iomux_v3_setup_multiple_pads(enet_pads2, ARRAY_SIZE(enet_pads2));
+}
+
+static void setup_iomux_uart(void)
+{
+	imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
+	imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads));
+	imx_iomux_v3_setup_multiple_pads(uart4_pads, ARRAY_SIZE(uart4_pads));
+}
+
+#ifdef CONFIG_USB_EHCI_MX6
+int board_ehci_hcd_init(int port)
+{
+	return 0;
+}
+
+#endif
+
+#ifdef CONFIG_FSL_ESDHC
+struct fsl_esdhc_cfg usdhc_cfg[1] = {
+	{ USDHC3_BASE_ADDR },
+};
+
+int board_mmc_getcd(struct mmc *mmc)
+{
+	struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
+
+	if (cfg->esdhc_base == USDHC3_BASE_ADDR) {
+		gpio_direction_input(IMX_GPIO_NR(7, 0));
+		return !gpio_get_value(IMX_GPIO_NR(7, 0));
+	}
+
+	return 0;
+}
+
+int board_mmc_init(bd_t *bis)
+{
+	/*
+	 * Only one USDHC controller on titianium
+	 */
+	imx_iomux_v3_setup_multiple_pads(usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
+	usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
+
+	return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
+}
+#endif
+
+int board_phy_config(struct phy_device *phydev)
+{
+	/* min rx data delay */
+	ksz9021_phy_extended_write(phydev,
+				   MII_KSZ9021_EXT_RGMII_RX_DATA_SKEW, 0x0);
+	/* min tx data delay */
+	ksz9021_phy_extended_write(phydev,
+				   MII_KSZ9021_EXT_RGMII_TX_DATA_SKEW, 0x0);
+	/* max rx/tx clock delay, min rx/tx control */
+	ksz9021_phy_extended_write(phydev,
+				   MII_KSZ9021_EXT_RGMII_CLOCK_SKEW, 0xf0f0);
+	if (phydev->drv->config)
+		phydev->drv->config(phydev);
+
+	return 0;
+}
+
+int board_eth_init(bd_t *bis)
+{
+	setup_iomux_enet();
+
+	return cpu_eth_init(bis);
+}
+
+int board_early_init_f(void)
+{
+	setup_iomux_uart();
+
+	return 0;
+}
+
+int board_init(void)
+{
+	/* address of boot parameters */
+	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+
+	setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info0);
+	setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
+
+	setup_gpmi_nand();
+
+	return 0;
+}
+
+int checkboard(void)
+{
+	puts("Board: Titanium\n");
+
+	return 0;
+}
+
+#ifdef CONFIG_CMD_BMODE
+static const struct boot_mode board_boot_modes[] = {
+	/* NAND */
+	{ "nand", MAKE_CFGVAL(0x80, 0x02, 0x00, 0x00) },
+	/* 4 bit bus width */
+	{ "mmc0", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00) },
+	{ "mmc1", MAKE_CFGVAL(0x40, 0x38, 0x00, 0x00) },
+	{ NULL, 0 },
+};
+#endif
+
+int misc_init_r(void)
+{
+#ifdef CONFIG_CMD_BMODE
+	add_board_boot_modes(board_boot_modes);
+#endif
+
+	return 0;
+}
diff --git a/board/bc3450/Makefile b/board/bc3450/Makefile
index 07970c65e3..b8d22bafed 100644
--- a/board/bc3450/Makefile
+++ b/board/bc3450/Makefile
@@ -5,24 +5,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	:= $(BOARD).o cmd_bc3450.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	:= bc3450.o cmd_bc3450.o
diff --git a/board/bct-brettl2/Makefile b/board/bct-brettl2/Makefile
index 6f9f701c06..12154b625e 100644
--- a/board/bct-brettl2/Makefile
+++ b/board/bct-brettl2/Makefile
@@ -9,21 +9,5 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS-y	:= $(BOARD).o gpio_cfi_flash.o cled.o
-COBJS-$(CONFIG_BFIN_MAC) += smsc9303.o
-
-SRCS	:= $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS-y))
-SOBJS	:= $(addprefix $(obj),$(SOBJS-y))
-
-$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
-	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
+obj-y	:= bct-brettl2.o gpio_cfi_flash.o cled.o
+obj-$(CONFIG_BFIN_MAC) += smsc9303.o
diff --git a/board/bct-brettl2/config.mk b/board/bct-brettl2/config.mk
deleted file mode 100644
index f1ef9bf682..0000000000
--- a/board/bct-brettl2/config.mk
+++ /dev/null
@@ -1,12 +0,0 @@
-#
-# Copyright (c) 2005-2008 Analog Device Inc.
-#
-# (C) Copyright 2001
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-CFLAGS_lib += -O2
-CFLAGS_lib/lzma += -O2
-CFLAGS_lib/zlib += -O2
diff --git a/board/bf506f-ezkit/Makefile b/board/bf506f-ezkit/Makefile
index b7275f49fe..0f134f9ac3 100644
--- a/board/bf506f-ezkit/Makefile
+++ b/board/bf506f-ezkit/Makefile
@@ -9,24 +9,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS-y	:= $(BOARD).o
-
-SRCS	:= $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS-y))
-SOBJS	:= $(addprefix $(obj),$(SOBJS-y))
-
-$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
-	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	:= bf506f-ezkit.o
diff --git a/board/bf518f-ezbrd/Makefile b/board/bf518f-ezbrd/Makefile
index b7275f49fe..3a6abaa63b 100644
--- a/board/bf518f-ezbrd/Makefile
+++ b/board/bf518f-ezbrd/Makefile
@@ -9,24 +9,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS-y	:= $(BOARD).o
-
-SRCS	:= $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS-y))
-SOBJS	:= $(addprefix $(obj),$(SOBJS-y))
-
-$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
-	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	:= bf518f-ezbrd.o
diff --git a/board/bf518f-ezbrd/config.mk b/board/bf518f-ezbrd/config.mk
deleted file mode 100644
index f1ef9bf682..0000000000
--- a/board/bf518f-ezbrd/config.mk
+++ /dev/null
@@ -1,12 +0,0 @@
-#
-# Copyright (c) 2005-2008 Analog Device Inc.
-#
-# (C) Copyright 2001
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-CFLAGS_lib += -O2
-CFLAGS_lib/lzma += -O2
-CFLAGS_lib/zlib += -O2
diff --git a/board/bf525-ucr2/Makefile b/board/bf525-ucr2/Makefile
index b7275f49fe..8de71a1886 100644
--- a/board/bf525-ucr2/Makefile
+++ b/board/bf525-ucr2/Makefile
@@ -9,24 +9,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS-y	:= $(BOARD).o
-
-SRCS	:= $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS-y))
-SOBJS	:= $(addprefix $(obj),$(SOBJS-y))
-
-$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
-	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	:= bf525-ucr2.o
diff --git a/board/bf526-ezbrd/Makefile b/board/bf526-ezbrd/Makefile
index b7275f49fe..34ac56323a 100644
--- a/board/bf526-ezbrd/Makefile
+++ b/board/bf526-ezbrd/Makefile
@@ -9,24 +9,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS-y	:= $(BOARD).o
-
-SRCS	:= $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS-y))
-SOBJS	:= $(addprefix $(obj),$(SOBJS-y))
-
-$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
-	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	:= bf526-ezbrd.o
diff --git a/board/bf526-ezbrd/config.mk b/board/bf526-ezbrd/config.mk
deleted file mode 100644
index f1ef9bf682..0000000000
--- a/board/bf526-ezbrd/config.mk
+++ /dev/null
@@ -1,12 +0,0 @@
-#
-# Copyright (c) 2005-2008 Analog Device Inc.
-#
-# (C) Copyright 2001
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-CFLAGS_lib += -O2
-CFLAGS_lib/lzma += -O2
-CFLAGS_lib/zlib += -O2
diff --git a/board/bf527-ad7160-eval/Makefile b/board/bf527-ad7160-eval/Makefile
index b7275f49fe..9d8ecf118d 100644
--- a/board/bf527-ad7160-eval/Makefile
+++ b/board/bf527-ad7160-eval/Makefile
@@ -9,24 +9,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS-y	:= $(BOARD).o
-
-SRCS	:= $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS-y))
-SOBJS	:= $(addprefix $(obj),$(SOBJS-y))
-
-$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
-	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	:= bf527-ad7160-eval.o
diff --git a/board/bf527-ad7160-eval/config.mk b/board/bf527-ad7160-eval/config.mk
deleted file mode 100644
index f1ef9bf682..0000000000
--- a/board/bf527-ad7160-eval/config.mk
+++ /dev/null
@@ -1,12 +0,0 @@
-#
-# Copyright (c) 2005-2008 Analog Device Inc.
-#
-# (C) Copyright 2001
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-CFLAGS_lib += -O2
-CFLAGS_lib/lzma += -O2
-CFLAGS_lib/zlib += -O2
diff --git a/board/bf527-ezkit/Makefile b/board/bf527-ezkit/Makefile
index 1a6ca64c72..cedd821b24 100644
--- a/board/bf527-ezkit/Makefile
+++ b/board/bf527-ezkit/Makefile
@@ -9,25 +9,5 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS-y	:= $(BOARD).o
-COBJS-$(CONFIG_VIDEO)      += video.o
-
-SRCS	:= $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS-y))
-SOBJS	:= $(addprefix $(obj),$(SOBJS-y))
-
-$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
-	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	:= bf527-ezkit.o
+obj-$(CONFIG_VIDEO)      += video.o
diff --git a/board/bf527-ezkit/config.mk b/board/bf527-ezkit/config.mk
deleted file mode 100644
index f1ef9bf682..0000000000
--- a/board/bf527-ezkit/config.mk
+++ /dev/null
@@ -1,12 +0,0 @@
-#
-# Copyright (c) 2005-2008 Analog Device Inc.
-#
-# (C) Copyright 2001
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-CFLAGS_lib += -O2
-CFLAGS_lib/lzma += -O2
-CFLAGS_lib/zlib += -O2
diff --git a/board/bf527-sdp/Makefile b/board/bf527-sdp/Makefile
index b7275f49fe..1ddb026cae 100644
--- a/board/bf527-sdp/Makefile
+++ b/board/bf527-sdp/Makefile
@@ -9,24 +9,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS-y	:= $(BOARD).o
-
-SRCS	:= $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS-y))
-SOBJS	:= $(addprefix $(obj),$(SOBJS-y))
-
-$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
-	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	:= bf527-sdp.o
diff --git a/board/bf527-sdp/config.mk b/board/bf527-sdp/config.mk
index 5f327a990e..1d46cfcd48 100644
--- a/board/bf527-sdp/config.mk
+++ b/board/bf527-sdp/config.mk
@@ -7,9 +7,5 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-CFLAGS_lib += -O2
-CFLAGS_lib/lzma += -O2
-CFLAGS_lib/zlib += -O2
-
 # Set some default LDR flags based on boot mode.
 LDR_FLAGS-BFIN_BOOT_PARA := --bits 16 --dma 6
diff --git a/board/bf533-ezkit/Makefile b/board/bf533-ezkit/Makefile
index 63a48b27c7..6838cf0451 100644
--- a/board/bf533-ezkit/Makefile
+++ b/board/bf533-ezkit/Makefile
@@ -9,24 +9,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS-y	:= $(BOARD).o flash.o
-
-SRCS	:= $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS-y))
-SOBJS	:= $(addprefix $(obj),$(SOBJS-y))
-
-$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
-	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	:= bf533-ezkit.o flash.o
diff --git a/board/bf533-ezkit/config.mk b/board/bf533-ezkit/config.mk
index 973d357559..7f9138b09b 100644
--- a/board/bf533-ezkit/config.mk
+++ b/board/bf533-ezkit/config.mk
@@ -7,9 +7,5 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-CFLAGS_lib += -O2
-CFLAGS_lib/lzma += -O2
-CFLAGS_lib/zlib += -O2
-
 # Set some default LDR flags based on boot mode.
 LDR_FLAGS-BFIN_BOOT_PARA := --bits 16 --dma 8
diff --git a/board/bf533-stamp/Makefile b/board/bf533-stamp/Makefile
index d2bc49ab56..244f9e0497 100644
--- a/board/bf533-stamp/Makefile
+++ b/board/bf533-stamp/Makefile
@@ -9,26 +9,6 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS-y	:= $(BOARD).o
-COBJS-$(CONFIG_STAMP_CF) += ide-cf.o
-COBJS-$(CONFIG_VIDEO) += video.o
-
-SRCS	:= $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS-y))
-SOBJS	:= $(addprefix $(obj),$(SOBJS-y))
-
-$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
-	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	:= bf533-stamp.o
+obj-$(CONFIG_STAMP_CF) += ide-cf.o
+obj-$(CONFIG_VIDEO) += video.o
diff --git a/board/bf533-stamp/config.mk b/board/bf533-stamp/config.mk
index 973d357559..7f9138b09b 100644
--- a/board/bf533-stamp/config.mk
+++ b/board/bf533-stamp/config.mk
@@ -7,9 +7,5 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-CFLAGS_lib += -O2
-CFLAGS_lib/lzma += -O2
-CFLAGS_lib/zlib += -O2
-
 # Set some default LDR flags based on boot mode.
 LDR_FLAGS-BFIN_BOOT_PARA := --bits 16 --dma 8
diff --git a/board/bf537-minotaur/Makefile b/board/bf537-minotaur/Makefile
index b7275f49fe..66d2f05f44 100644
--- a/board/bf537-minotaur/Makefile
+++ b/board/bf537-minotaur/Makefile
@@ -9,24 +9,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS-y	:= $(BOARD).o
-
-SRCS	:= $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS-y))
-SOBJS	:= $(addprefix $(obj),$(SOBJS-y))
-
-$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
-	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	:= bf537-minotaur.o
diff --git a/board/bf537-pnav/Makefile b/board/bf537-pnav/Makefile
index b7275f49fe..ffcdf1f0b0 100644
--- a/board/bf537-pnav/Makefile
+++ b/board/bf537-pnav/Makefile
@@ -9,24 +9,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS-y	:= $(BOARD).o
-
-SRCS	:= $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS-y))
-SOBJS	:= $(addprefix $(obj),$(SOBJS-y))
-
-$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
-	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	:= bf537-pnav.o
diff --git a/board/bf537-srv1/Makefile b/board/bf537-srv1/Makefile
index b7275f49fe..cd0da272a6 100644
--- a/board/bf537-srv1/Makefile
+++ b/board/bf537-srv1/Makefile
@@ -9,24 +9,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS-y	:= $(BOARD).o
-
-SRCS	:= $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS-y))
-SOBJS	:= $(addprefix $(obj),$(SOBJS-y))
-
-$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
-	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	:= bf537-srv1.o
diff --git a/board/bf537-stamp/Makefile b/board/bf537-stamp/Makefile
index 3e267edc0b..234119a52a 100644
--- a/board/bf537-stamp/Makefile
+++ b/board/bf537-stamp/Makefile
@@ -9,26 +9,6 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS-y	:= $(BOARD).o
-COBJS-$(CONFIG_BFIN_IDE)   += ide-cf.o
-COBJS-$(CONFIG_HAS_POST)   += post-memory.o
-
-SRCS	:= $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS-y))
-SOBJS	:= $(addprefix $(obj),$(SOBJS-y))
-
-$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
-	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	:= bf537-stamp.o
+obj-$(CONFIG_BFIN_IDE)   += ide-cf.o
+obj-$(CONFIG_HAS_POST)   += post-memory.o
diff --git a/board/bf537-stamp/config.mk b/board/bf537-stamp/config.mk
index ae2ea0b747..ab0fbecab9 100644
--- a/board/bf537-stamp/config.mk
+++ b/board/bf537-stamp/config.mk
@@ -7,10 +7,6 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-CFLAGS_lib += -O2
-CFLAGS_lib/lzma += -O2
-CFLAGS_lib/zlib += -O2
-
 # Set some default LDR flags based on boot mode.
 LDR_FLAGS-BFIN_BOOT_PARA := --bits 16 --dma 8
 LDR_FLAGS-BFIN_BOOT_UART := --port g --gpio 6
diff --git a/board/bf538f-ezkit/Makefile b/board/bf538f-ezkit/Makefile
index b7275f49fe..7c8cda05e9 100644
--- a/board/bf538f-ezkit/Makefile
+++ b/board/bf538f-ezkit/Makefile
@@ -9,24 +9,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS-y	:= $(BOARD).o
-
-SRCS	:= $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS-y))
-SOBJS	:= $(addprefix $(obj),$(SOBJS-y))
-
-$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
-	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	:= bf538f-ezkit.o
diff --git a/board/bf538f-ezkit/config.mk b/board/bf538f-ezkit/config.mk
index 973d357559..7f9138b09b 100644
--- a/board/bf538f-ezkit/config.mk
+++ b/board/bf538f-ezkit/config.mk
@@ -7,9 +7,5 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-CFLAGS_lib += -O2
-CFLAGS_lib/lzma += -O2
-CFLAGS_lib/zlib += -O2
-
 # Set some default LDR flags based on boot mode.
 LDR_FLAGS-BFIN_BOOT_PARA := --bits 16 --dma 8
diff --git a/board/bf548-ezkit/Makefile b/board/bf548-ezkit/Makefile
index 1a6ca64c72..6f4200bd46 100644
--- a/board/bf548-ezkit/Makefile
+++ b/board/bf548-ezkit/Makefile
@@ -9,25 +9,5 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS-y	:= $(BOARD).o
-COBJS-$(CONFIG_VIDEO)      += video.o
-
-SRCS	:= $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS-y))
-SOBJS	:= $(addprefix $(obj),$(SOBJS-y))
-
-$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
-	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	:= bf548-ezkit.o
+obj-$(CONFIG_VIDEO)      += video.o
diff --git a/board/bf548-ezkit/config.mk b/board/bf548-ezkit/config.mk
index ad3a7293df..7bb8e9c9ee 100644
--- a/board/bf548-ezkit/config.mk
+++ b/board/bf548-ezkit/config.mk
@@ -7,10 +7,6 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-CFLAGS_lib += -O2
-CFLAGS_lib/lzma += -O2
-CFLAGS_lib/zlib += -O2
-
 # Set some default LDR flags based on boot mode.
 LDR_FLAGS-BFIN_BOOT_PARA       := --dma 6
 LDR_FLAGS-BFIN_BOOT_FIFO       := --dma 1
diff --git a/board/bf561-acvilon/Makefile b/board/bf561-acvilon/Makefile
index 988cdd88c1..48bec2884d 100644
--- a/board/bf561-acvilon/Makefile
+++ b/board/bf561-acvilon/Makefile
@@ -11,24 +11,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS-y	:= $(BOARD).o
-
-SRCS	:= $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS-y))
-SOBJS	:= $(addprefix $(obj),$(SOBJS-y))
-
-$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
-	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	:= bf561-acvilon.o
diff --git a/board/bf561-acvilon/config.mk b/board/bf561-acvilon/config.mk
index c33aef9d28..854d7dbb86 100644
--- a/board/bf561-acvilon/config.mk
+++ b/board/bf561-acvilon/config.mk
@@ -7,9 +7,5 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-CFLAGS_lib += -O2
-CFLAGS_lib/lzma += -O2
-CFLAGS_lib/zlib += -O2
-
 # Set some default LDR flags based on boot mode.
 LDR_FLAGS-BFIN_BOOT_PARA := --bits 16
diff --git a/board/bf561-ezkit/Makefile b/board/bf561-ezkit/Makefile
index 099bcaf999..23c7101c20 100644
--- a/board/bf561-ezkit/Makefile
+++ b/board/bf561-ezkit/Makefile
@@ -9,24 +9,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS-y	:= $(BOARD).o
-
-SRCS	:= $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS-y))
-SOBJS	:= $(addprefix $(obj),$(SOBJS-y))
-
-$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
-	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	:= bf561-ezkit.o
diff --git a/board/bf561-ezkit/config.mk b/board/bf561-ezkit/config.mk
index c33aef9d28..854d7dbb86 100644
--- a/board/bf561-ezkit/config.mk
+++ b/board/bf561-ezkit/config.mk
@@ -7,9 +7,5 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-CFLAGS_lib += -O2
-CFLAGS_lib/lzma += -O2
-CFLAGS_lib/zlib += -O2
-
 # Set some default LDR flags based on boot mode.
 LDR_FLAGS-BFIN_BOOT_PARA := --bits 16
diff --git a/board/bf609-ezkit/Makefile b/board/bf609-ezkit/Makefile
index cd2fdc746c..3bfd0887bc 100644
--- a/board/bf609-ezkit/Makefile
+++ b/board/bf609-ezkit/Makefile
@@ -9,31 +9,5 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS-y	:= $(BOARD).o
-COBJS-$(CONFIG_BFIN_SOFT_SWITCH)   += soft_switch.o
-
-SRCS	:= $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS-y))
-SOBJS	:= $(addprefix $(obj),$(SOBJS-y))
-
-$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
-	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
-
-clean:
-	rm -f $(SOBJS) $(OBJS)
-
-distclean:	clean
-	rm -f $(LIB) core *.bak $(obj).depend
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	:= bf609-ezkit.o
+obj-$(CONFIG_BFIN_SOFT_SWITCH)   += soft_switch.o
diff --git a/board/bf609-ezkit/bf609-ezkit.c b/board/bf609-ezkit/bf609-ezkit.c
index 0388226db4..43a43306bb 100644
--- a/board/bf609-ezkit/bf609-ezkit.c
+++ b/board/bf609-ezkit/bf609-ezkit.c
@@ -10,6 +10,7 @@
 #include <netdev.h>
 #include <asm/blackfin.h>
 #include <asm/io.h>
+#include <asm/sdh.h>
 #include <asm/portmux.h>
 #include "soft_switch.h"
 
@@ -40,12 +41,12 @@ int board_eth_init(bd_t *bis)
 	if (CONFIG_DW_PORTS & 1) {
 		static const unsigned short pins[] = P_RMII0;
 		if (!peripheral_request_list(pins, "emac0"))
-			ret += designware_initialize(0, EMAC0_MACCFG, 1, 0);
+			ret += designware_initialize(EMAC0_MACCFG, 0);
 	}
 	if (CONFIG_DW_PORTS & 2) {
 		static const unsigned short pins[] = P_RMII1;
 		if (!peripheral_request_list(pins, "emac1"))
-			ret += designware_initialize(1, EMAC1_MACCFG, 1, 0);
+			ret += designware_initialize(EMAC1_MACCFG, 0);
 	}
 
 	return ret;
diff --git a/board/blackstamp/Makefile b/board/blackstamp/Makefile
index b7275f49fe..38e5da7469 100644
--- a/board/blackstamp/Makefile
+++ b/board/blackstamp/Makefile
@@ -9,24 +9,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS-y	:= $(BOARD).o
-
-SRCS	:= $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS-y))
-SOBJS	:= $(addprefix $(obj),$(SOBJS-y))
-
-$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
-	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	:= blackstamp.o
diff --git a/board/blackvme/Makefile b/board/blackvme/Makefile
index b7275f49fe..4ff989a140 100644
--- a/board/blackvme/Makefile
+++ b/board/blackvme/Makefile
@@ -9,24 +9,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS-y	:= $(BOARD).o
-
-SRCS	:= $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS-y))
-SOBJS	:= $(addprefix $(obj),$(SOBJS-y))
-
-$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
-	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	:= blackvme.o
diff --git a/board/bluegiga/apx4devkit/Makefile b/board/bluegiga/apx4devkit/Makefile
index 9c05b616f8..a7fcb63aed 100644
--- a/board/bluegiga/apx4devkit/Makefile
+++ b/board/bluegiga/apx4devkit/Makefile
@@ -5,27 +5,8 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
 ifndef	CONFIG_SPL_BUILD
-COBJS	:= apx4devkit.o
+obj-y	:= apx4devkit.o
 else
-COBJS	:= spl_boot.o
+obj-y	:= spl_boot.o
 endif
-
-SRCS	:= $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
diff --git a/board/bluewater/snapper9260/Makefile b/board/bluewater/snapper9260/Makefile
index d050473ac3..af7f0da84b 100644
--- a/board/bluewater/snapper9260/Makefile
+++ b/board/bluewater/snapper9260/Makefile
@@ -8,24 +8,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS-y	+= snapper9260.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS-y))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
-	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	+= snapper9260.o
diff --git a/board/bluewater/snapper9260/snapper9260.c b/board/bluewater/snapper9260/snapper9260.c
index 8a6919dbb1..bfde1291a5 100644
--- a/board/bluewater/snapper9260/snapper9260.c
+++ b/board/bluewater/snapper9260/snapper9260.c
@@ -14,7 +14,6 @@
 #include <asm/arch/at91sam9_smc.h>
 #include <asm/arch/at91_common.h>
 #include <asm/arch/at91_pmc.h>
-#include <asm/arch/at91_rstc.h>
 #include <asm/arch/gpio.h>
 #include <net.h>
 #include <netdev.h>
@@ -31,8 +30,6 @@ static void macb_hw_init(void)
 {
 	struct at91_pmc *pmc   = (struct at91_pmc  *)ATMEL_BASE_PMC;
 	struct at91_port *pioa = (struct at91_port *)ATMEL_BASE_PIOA;
-	struct at91_rstc *rstc = (struct at91_rstc *)ATMEL_BASE_RSTC;
-	unsigned long erstl;
 
 	/* Enable clock */
 	writel(1 << ATMEL_ID_EMAC0, &pmc->pcer);
@@ -54,18 +51,7 @@ static void macb_hw_init(void)
 	/* Enable ethernet power */
 	pca953x_set_val(0x28, IO_EXP_ETH_POWER, 0);
 
-	/* Need to reset PHY -> 500ms reset */
-	erstl = readl(&rstc->mr) & AT91_RSTC_MR_ERSTL_MASK;
-	writel(AT91_RSTC_KEY | AT91_RSTC_MR_ERSTL(13) |
-	       AT91_RSTC_MR_URSTEN, &rstc->mr);
-	writel(AT91_RSTC_KEY | AT91_RSTC_CR_EXTRST, &rstc->cr);
-
-	/* Wait for end hardware reset */
-	while (!(readl(&rstc->sr) & AT91_RSTC_SR_NRSTL))
-		;
-
-	/* Restore NRST value */
-	writel(AT91_RSTC_KEY | erstl | AT91_RSTC_MR_URSTEN, &rstc->mr);
+	at91_phy_reset();
 
 	/* Bring the ethernet out of reset */
 	pca953x_set_val(0x28, IO_EXP_ETH_RESET, 1);
diff --git a/board/boundary/nitrogen6x/6x_upgrade.txt b/board/boundary/nitrogen6x/6x_upgrade.txt
index 1f9a889554..1a62bbf12e 100644
--- a/board/boundary/nitrogen6x/6x_upgrade.txt
+++ b/board/boundary/nitrogen6x/6x_upgrade.txt
@@ -17,7 +17,7 @@ if ${fs}load ${dtype} ${disk}:1 12000000 u-boot.imx || ${fs}load ${dtype} ${disk
 			sleep 1 ;
 		   done
 		   echo "erasing" ;
-		   sf erase 0 0x50000 ;
+		   sf erase 0 0xC0000 ;
 		   # two steps to prevent bricking
 		   echo "programming" ;
 		   sf write 0x12000000 $offset $filesize ;
diff --git a/board/boundary/nitrogen6x/Makefile b/board/boundary/nitrogen6x/Makefile
index 066f60dd30..f875d68182 100644
--- a/board/boundary/nitrogen6x/Makefile
+++ b/board/boundary/nitrogen6x/Makefile
@@ -6,23 +6,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB    = $(obj)lib$(BOARD).o
-
-COBJS  := nitrogen6x.o
-
-SRCS   := $(COBJS:.o=.c)
-OBJS   := $(addprefix $(obj),$(COBJS))
-
-$(LIB):        $(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y  := nitrogen6x.o
diff --git a/board/boundary/nitrogen6x/README b/board/boundary/nitrogen6x/README
index 50490931e0..9d84265029 100644
--- a/board/boundary/nitrogen6x/README
+++ b/board/boundary/nitrogen6x/README
@@ -67,10 +67,10 @@ override auto-detection and force activation of the specified panel.
 To build U-Boot for one of the Nitrogen6x or SabreLite board:
 
 	make nitrogen6x_config
-	make u-boot.imx
+	make
 
 Note that 'nitrogen6x' is a placeholder. The complete list of supported
-board configurations is shown in tha MAINTAINERS file:
+board configurations is shown in the boards.cfg file:
 	nitrogen6q		i.MX6Q/6D	1GB
 	nitrogen6dl		i.MX6DL		1GB
 	nitrogen6s		i.MX6S		512MB
diff --git a/board/boundary/nitrogen6x/nitrogen6dl.cfg b/board/boundary/nitrogen6x/nitrogen6dl.cfg
index 97ae0c291b..1cdccad772 100644
--- a/board/boundary/nitrogen6x/nitrogen6dl.cfg
+++ b/board/boundary/nitrogen6x/nitrogen6dl.cfg
@@ -16,7 +16,7 @@ IMAGE_VERSION 2
  * Boot Device : one of
  * spi, sd (the board has no nand neither onenand)
  */
-BOOT_FROM      sd
+BOOT_FROM      spi
 
 #define __ASSEMBLY__
 #include <config.h>
diff --git a/board/boundary/nitrogen6x/nitrogen6dl2g.cfg b/board/boundary/nitrogen6x/nitrogen6dl2g.cfg
index 82f837e108..516d67e4be 100644
--- a/board/boundary/nitrogen6x/nitrogen6dl2g.cfg
+++ b/board/boundary/nitrogen6x/nitrogen6dl2g.cfg
@@ -16,7 +16,7 @@ IMAGE_VERSION 2
  * Boot Device : one of
  * spi, sd (the board has no nand neither onenand)
  */
-BOOT_FROM      sd
+BOOT_FROM      spi
 
 #define __ASSEMBLY__
 #include <config.h>
diff --git a/board/boundary/nitrogen6x/nitrogen6q.cfg b/board/boundary/nitrogen6x/nitrogen6q.cfg
index b6f1518ea9..b6642e6901 100644
--- a/board/boundary/nitrogen6x/nitrogen6q.cfg
+++ b/board/boundary/nitrogen6x/nitrogen6q.cfg
@@ -16,7 +16,7 @@ IMAGE_VERSION 2
  * Boot Device : one of
  * spi, sd (the board has no nand neither onenand)
  */
-BOOT_FROM      sd
+BOOT_FROM      spi
 
 #define __ASSEMBLY__
 #include <config.h>
diff --git a/board/boundary/nitrogen6x/nitrogen6q2g.cfg b/board/boundary/nitrogen6x/nitrogen6q2g.cfg
index 8d7ff25f7f..fe6dfc1f44 100644
--- a/board/boundary/nitrogen6x/nitrogen6q2g.cfg
+++ b/board/boundary/nitrogen6x/nitrogen6q2g.cfg
@@ -16,7 +16,7 @@ IMAGE_VERSION 2
  * Boot Device : one of
  * spi, sd (the board has no nand neither onenand)
  */
-BOOT_FROM      sd
+BOOT_FROM      spi
 
 #define __ASSEMBLY__
 #include <config.h>
diff --git a/board/boundary/nitrogen6x/nitrogen6s.cfg b/board/boundary/nitrogen6x/nitrogen6s.cfg
index 34fb9d0688..ca30cd6c46 100644
--- a/board/boundary/nitrogen6x/nitrogen6s.cfg
+++ b/board/boundary/nitrogen6x/nitrogen6s.cfg
@@ -16,7 +16,7 @@ IMAGE_VERSION 2
  * Boot Device : one of
  * spi, sd (the board has no nand neither onenand)
  */
-BOOT_FROM      sd
+BOOT_FROM      spi
 
 #define __ASSEMBLY__
 #include <config.h>
diff --git a/board/boundary/nitrogen6x/nitrogen6s1g.cfg b/board/boundary/nitrogen6x/nitrogen6s1g.cfg
index d61453c665..b1489fb907 100644
--- a/board/boundary/nitrogen6x/nitrogen6s1g.cfg
+++ b/board/boundary/nitrogen6x/nitrogen6s1g.cfg
@@ -16,7 +16,7 @@ IMAGE_VERSION 2
  * Boot Device : one of
  * spi, sd (the board has no nand neither onenand)
  */
-BOOT_FROM      sd
+BOOT_FROM      spi
 
 #define __ASSEMBLY__
 #include <config.h>
diff --git a/board/boundary/nitrogen6x/nitrogen6x.c b/board/boundary/nitrogen6x/nitrogen6x.c
index 17129081b7..d9c05b07bf 100644
--- a/board/boundary/nitrogen6x/nitrogen6x.c
+++ b/board/boundary/nitrogen6x/nitrogen6x.c
@@ -17,6 +17,7 @@
 #include <asm/gpio.h>
 #include <asm/imx-common/iomux-v3.h>
 #include <asm/imx-common/mxc_i2c.h>
+#include <asm/imx-common/sata.h>
 #include <asm/imx-common/boot_mode.h>
 #include <mmc.h>
 #include <fsl_esdhc.h>
@@ -30,6 +31,7 @@
 #include <i2c.h>
 
 DECLARE_GLOBAL_DATA_PTR;
+#define GP_USB_OTG_PWR	IMX_GPIO_NR(3, 22)
 
 #define UART_PAD_CTRL  (PAD_CTL_PUS_100K_UP |			\
 	PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |			\
@@ -70,13 +72,13 @@ int dram_init(void)
 }
 
 iomux_v3_cfg_t const uart1_pads[] = {
-	MX6_PAD_SD3_DAT6__UART1_RXD | MUX_PAD_CTRL(UART_PAD_CTRL),
-	MX6_PAD_SD3_DAT7__UART1_TXD | MUX_PAD_CTRL(UART_PAD_CTRL),
+	MX6_PAD_SD3_DAT6__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
+	MX6_PAD_SD3_DAT7__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
 };
 
 iomux_v3_cfg_t const uart2_pads[] = {
-	MX6_PAD_EIM_D26__UART2_TXD | MUX_PAD_CTRL(UART_PAD_CTRL),
-	MX6_PAD_EIM_D27__UART2_RXD | MUX_PAD_CTRL(UART_PAD_CTRL),
+	MX6_PAD_EIM_D26__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
+	MX6_PAD_EIM_D27__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
 };
 
 #define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
@@ -85,12 +87,12 @@ iomux_v3_cfg_t const uart2_pads[] = {
 struct i2c_pads_info i2c_pad_info0 = {
 	.scl = {
 		.i2c_mode = MX6_PAD_EIM_D21__I2C1_SCL | PC,
-		.gpio_mode = MX6_PAD_EIM_D21__GPIO_3_21 | PC,
+		.gpio_mode = MX6_PAD_EIM_D21__GPIO3_IO21 | PC,
 		.gp = IMX_GPIO_NR(3, 21)
 	},
 	.sda = {
 		.i2c_mode = MX6_PAD_EIM_D28__I2C1_SDA | PC,
-		.gpio_mode = MX6_PAD_EIM_D28__GPIO_3_28 | PC,
+		.gpio_mode = MX6_PAD_EIM_D28__GPIO3_IO28 | PC,
 		.gp = IMX_GPIO_NR(3, 28)
 	}
 };
@@ -99,12 +101,12 @@ struct i2c_pads_info i2c_pad_info0 = {
 struct i2c_pads_info i2c_pad_info1 = {
 	.scl = {
 		.i2c_mode = MX6_PAD_KEY_COL3__I2C2_SCL | PC,
-		.gpio_mode = MX6_PAD_KEY_COL3__GPIO_4_12 | PC,
+		.gpio_mode = MX6_PAD_KEY_COL3__GPIO4_IO12 | PC,
 		.gp = IMX_GPIO_NR(4, 12)
 	},
 	.sda = {
 		.i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA | PC,
-		.gpio_mode = MX6_PAD_KEY_ROW3__GPIO_4_13 | PC,
+		.gpio_mode = MX6_PAD_KEY_ROW3__GPIO4_IO13 | PC,
 		.gp = IMX_GPIO_NR(4, 13)
 	}
 };
@@ -113,79 +115,87 @@ struct i2c_pads_info i2c_pad_info1 = {
 struct i2c_pads_info i2c_pad_info2 = {
 	.scl = {
 		.i2c_mode = MX6_PAD_GPIO_5__I2C3_SCL | PC,
-		.gpio_mode = MX6_PAD_GPIO_5__GPIO_1_5 | PC,
+		.gpio_mode = MX6_PAD_GPIO_5__GPIO1_IO05 | PC,
 		.gp = IMX_GPIO_NR(1, 5)
 	},
 	.sda = {
 		.i2c_mode = MX6_PAD_GPIO_16__I2C3_SDA | PC,
-		.gpio_mode = MX6_PAD_GPIO_16__GPIO_7_11 | PC,
+		.gpio_mode = MX6_PAD_GPIO_16__GPIO7_IO11 | PC,
 		.gp = IMX_GPIO_NR(7, 11)
 	}
 };
 
 iomux_v3_cfg_t const usdhc3_pads[] = {
-	MX6_PAD_SD3_CLK__USDHC3_CLK   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD3_CMD__USDHC3_CMD   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD3_DAT0__USDHC3_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD3_DAT1__USDHC3_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD3_DAT2__USDHC3_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD3_DAT3__USDHC3_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD3_DAT5__GPIO_7_0    | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
+	MX6_PAD_SD3_CLK__SD3_CLK   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD3_CMD__SD3_CMD   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD3_DAT5__GPIO7_IO00    | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
 };
 
 iomux_v3_cfg_t const usdhc4_pads[] = {
-	MX6_PAD_SD4_CLK__USDHC4_CLK   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD4_CMD__USDHC4_CMD   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD4_DAT0__USDHC4_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD4_DAT1__USDHC4_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD4_DAT2__USDHC4_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD4_DAT3__USDHC4_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_NANDF_D6__GPIO_2_6    | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
+	MX6_PAD_SD4_CLK__SD4_CLK   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD4_CMD__SD4_CMD   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_NANDF_D6__GPIO2_IO06    | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
 };
 
 iomux_v3_cfg_t const enet_pads1[] = {
 	MX6_PAD_ENET_MDIO__ENET_MDIO		| MUX_PAD_CTRL(ENET_PAD_CTRL),
 	MX6_PAD_ENET_MDC__ENET_MDC		| MUX_PAD_CTRL(ENET_PAD_CTRL),
-	MX6_PAD_RGMII_TXC__ENET_RGMII_TXC	| MUX_PAD_CTRL(ENET_PAD_CTRL),
-	MX6_PAD_RGMII_TD0__ENET_RGMII_TD0	| MUX_PAD_CTRL(ENET_PAD_CTRL),
-	MX6_PAD_RGMII_TD1__ENET_RGMII_TD1	| MUX_PAD_CTRL(ENET_PAD_CTRL),
-	MX6_PAD_RGMII_TD2__ENET_RGMII_TD2	| MUX_PAD_CTRL(ENET_PAD_CTRL),
-	MX6_PAD_RGMII_TD3__ENET_RGMII_TD3	| MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_RGMII_TXC__RGMII_TXC	| MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_RGMII_TD0__RGMII_TD0	| MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_RGMII_TD1__RGMII_TD1	| MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_RGMII_TD2__RGMII_TD2	| MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_RGMII_TD3__RGMII_TD3	| MUX_PAD_CTRL(ENET_PAD_CTRL),
 	MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL	| MUX_PAD_CTRL(ENET_PAD_CTRL),
 	MX6_PAD_ENET_REF_CLK__ENET_TX_CLK	| MUX_PAD_CTRL(ENET_PAD_CTRL),
 	/* pin 35 - 1 (PHY_AD2) on reset */
-	MX6_PAD_RGMII_RXC__GPIO_6_30		| MUX_PAD_CTRL(NO_PAD_CTRL),
+	MX6_PAD_RGMII_RXC__GPIO6_IO30		| MUX_PAD_CTRL(NO_PAD_CTRL),
 	/* pin 32 - 1 - (MODE0) all */
-	MX6_PAD_RGMII_RD0__GPIO_6_25		| MUX_PAD_CTRL(NO_PAD_CTRL),
+	MX6_PAD_RGMII_RD0__GPIO6_IO25		| MUX_PAD_CTRL(NO_PAD_CTRL),
 	/* pin 31 - 1 - (MODE1) all */
-	MX6_PAD_RGMII_RD1__GPIO_6_27		| MUX_PAD_CTRL(NO_PAD_CTRL),
+	MX6_PAD_RGMII_RD1__GPIO6_IO27		| MUX_PAD_CTRL(NO_PAD_CTRL),
 	/* pin 28 - 1 - (MODE2) all */
-	MX6_PAD_RGMII_RD2__GPIO_6_28		| MUX_PAD_CTRL(NO_PAD_CTRL),
+	MX6_PAD_RGMII_RD2__GPIO6_IO28		| MUX_PAD_CTRL(NO_PAD_CTRL),
 	/* pin 27 - 1 - (MODE3) all */
-	MX6_PAD_RGMII_RD3__GPIO_6_29		| MUX_PAD_CTRL(NO_PAD_CTRL),
+	MX6_PAD_RGMII_RD3__GPIO6_IO29		| MUX_PAD_CTRL(NO_PAD_CTRL),
 	/* pin 33 - 1 - (CLK125_EN) 125Mhz clockout enabled */
-	MX6_PAD_RGMII_RX_CTL__GPIO_6_24	| MUX_PAD_CTRL(NO_PAD_CTRL),
+	MX6_PAD_RGMII_RX_CTL__GPIO6_IO24	| MUX_PAD_CTRL(NO_PAD_CTRL),
 	/* pin 42 PHY nRST */
-	MX6_PAD_EIM_D23__GPIO_3_23		| MUX_PAD_CTRL(NO_PAD_CTRL),
-	MX6_PAD_ENET_RXD0__GPIO_1_27		| MUX_PAD_CTRL(NO_PAD_CTRL),
+	MX6_PAD_EIM_D23__GPIO3_IO23		| MUX_PAD_CTRL(NO_PAD_CTRL),
+	MX6_PAD_ENET_RXD0__GPIO1_IO27		| MUX_PAD_CTRL(NO_PAD_CTRL),
 };
 
 iomux_v3_cfg_t const enet_pads2[] = {
-	MX6_PAD_RGMII_RXC__ENET_RGMII_RXC	| MUX_PAD_CTRL(ENET_PAD_CTRL),
-	MX6_PAD_RGMII_RD0__ENET_RGMII_RD0	| MUX_PAD_CTRL(ENET_PAD_CTRL),
-	MX6_PAD_RGMII_RD1__ENET_RGMII_RD1	| MUX_PAD_CTRL(ENET_PAD_CTRL),
-	MX6_PAD_RGMII_RD2__ENET_RGMII_RD2	| MUX_PAD_CTRL(ENET_PAD_CTRL),
-	MX6_PAD_RGMII_RD3__ENET_RGMII_RD3	| MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_RGMII_RXC__RGMII_RXC	| MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_RGMII_RD0__RGMII_RD0	| MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_RGMII_RD1__RGMII_RD1	| MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_RGMII_RD2__RGMII_RD2	| MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_RGMII_RD3__RGMII_RD3	| MUX_PAD_CTRL(ENET_PAD_CTRL),
 	MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL	| MUX_PAD_CTRL(ENET_PAD_CTRL),
 };
 
+static iomux_v3_cfg_t const misc_pads[] = {
+	MX6_PAD_GPIO_1__USB_OTG_ID		| MUX_PAD_CTRL(WEAK_PULLUP),
+	MX6_PAD_KEY_COL4__USB_OTG_OC		| MUX_PAD_CTRL(WEAK_PULLUP),
+	MX6_PAD_EIM_D30__USB_H1_OC		| MUX_PAD_CTRL(WEAK_PULLUP),
+	/* OTG Power enable */
+	MX6_PAD_EIM_D22__GPIO3_IO22		| MUX_PAD_CTRL(OUTPUT_40OHM),
+};
+
 /* wl1271 pads on nitrogen6x */
 iomux_v3_cfg_t const wl12xx_pads[] = {
-	(MX6_PAD_NANDF_CS1__GPIO_6_14 & ~MUX_PAD_CTRL_MASK)
+	(MX6_PAD_NANDF_CS1__GPIO6_IO14 & ~MUX_PAD_CTRL_MASK)
 		| MUX_PAD_CTRL(WEAK_PULLDOWN),
-	(MX6_PAD_NANDF_CS2__GPIO_6_15 & ~MUX_PAD_CTRL_MASK)
+	(MX6_PAD_NANDF_CS2__GPIO6_IO15 & ~MUX_PAD_CTRL_MASK)
 		| MUX_PAD_CTRL(OUTPUT_40OHM),
-	(MX6_PAD_NANDF_CS3__GPIO_6_16 & ~MUX_PAD_CTRL_MASK)
+	(MX6_PAD_NANDF_CS3__GPIO6_IO16 & ~MUX_PAD_CTRL_MASK)
 		| MUX_PAD_CTRL(OUTPUT_40OHM),
 };
 #define WL12XX_WL_IRQ_GP	IMX_GPIO_NR(6, 14)
@@ -195,17 +205,17 @@ iomux_v3_cfg_t const wl12xx_pads[] = {
 /* Button assignments for J14 */
 static iomux_v3_cfg_t const button_pads[] = {
 	/* Menu */
-	MX6_PAD_NANDF_D1__GPIO_2_1	| MUX_PAD_CTRL(BUTTON_PAD_CTRL),
+	MX6_PAD_NANDF_D1__GPIO2_IO01	| MUX_PAD_CTRL(BUTTON_PAD_CTRL),
 	/* Back */
-	MX6_PAD_NANDF_D2__GPIO_2_2	| MUX_PAD_CTRL(BUTTON_PAD_CTRL),
+	MX6_PAD_NANDF_D2__GPIO2_IO02	| MUX_PAD_CTRL(BUTTON_PAD_CTRL),
 	/* Labelled Search (mapped to Power under Android) */
-	MX6_PAD_NANDF_D3__GPIO_2_3	| MUX_PAD_CTRL(BUTTON_PAD_CTRL),
+	MX6_PAD_NANDF_D3__GPIO2_IO03	| MUX_PAD_CTRL(BUTTON_PAD_CTRL),
 	/* Home */
-	MX6_PAD_NANDF_D4__GPIO_2_4	| MUX_PAD_CTRL(BUTTON_PAD_CTRL),
+	MX6_PAD_NANDF_D4__GPIO2_IO04	| MUX_PAD_CTRL(BUTTON_PAD_CTRL),
 	/* Volume Down */
-	MX6_PAD_GPIO_19__GPIO_4_5	| MUX_PAD_CTRL(BUTTON_PAD_CTRL),
+	MX6_PAD_GPIO_19__GPIO4_IO05	| MUX_PAD_CTRL(BUTTON_PAD_CTRL),
 	/* Volume Up */
-	MX6_PAD_GPIO_18__GPIO_7_13	| MUX_PAD_CTRL(BUTTON_PAD_CTRL),
+	MX6_PAD_GPIO_18__GPIO7_IO13	| MUX_PAD_CTRL(BUTTON_PAD_CTRL),
 };
 
 static void setup_iomux_enet(void)
@@ -229,7 +239,7 @@ static void setup_iomux_enet(void)
 }
 
 iomux_v3_cfg_t const usb_pads[] = {
-	MX6_PAD_GPIO_17__GPIO_7_12 | MUX_PAD_CTRL(NO_PAD_CTRL),
+	MX6_PAD_GPIO_17__GPIO7_IO12 | MUX_PAD_CTRL(NO_PAD_CTRL),
 };
 
 static void setup_iomux_uart(void)
@@ -250,6 +260,15 @@ int board_ehci_hcd_init(int port)
 
 	return 0;
 }
+
+int board_ehci_power(int port, int on)
+{
+	if (port)
+		return 0;
+	gpio_set_value(GP_USB_OTG_PWR, on);
+	return 0;
+}
+
 #endif
 
 #ifdef CONFIG_FSL_ESDHC
@@ -312,7 +331,7 @@ int board_mmc_init(bd_t *bis)
 #ifdef CONFIG_MXC_SPI
 iomux_v3_cfg_t const ecspi1_pads[] = {
 	/* SS1 */
-	MX6_PAD_EIM_D19__GPIO_3_19   | MUX_PAD_CTRL(SPI_PAD_CTRL),
+	MX6_PAD_EIM_D19__GPIO3_IO19   | MUX_PAD_CTRL(SPI_PAD_CTRL),
 	MX6_PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
 	MX6_PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
 	MX6_PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
@@ -369,6 +388,11 @@ int board_eth_init(bd_t *bis)
 		free(bus);
 	}
 #endif
+
+#ifdef CONFIG_CI_UDC
+	/* For otg ethernet*/
+	usb_eth_initialize(bis);
+#endif
 	return 0;
 }
 
@@ -378,74 +402,48 @@ static void setup_buttons(void)
 					 ARRAY_SIZE(button_pads));
 }
 
-#ifdef CONFIG_CMD_SATA
-
-int setup_sata(void)
-{
-	struct iomuxc_base_regs *const iomuxc_regs
-		= (struct iomuxc_base_regs *) IOMUXC_BASE_ADDR;
-	int ret = enable_sata_clock();
-	if (ret)
-		return ret;
-
-	clrsetbits_le32(&iomuxc_regs->gpr[13],
-			IOMUXC_GPR13_SATA_MASK,
-			IOMUXC_GPR13_SATA_PHY_8_RXEQ_3P0DB
-			|IOMUXC_GPR13_SATA_PHY_7_SATA2M
-			|IOMUXC_GPR13_SATA_SPEED_3G
-			|(3<<IOMUXC_GPR13_SATA_PHY_6_SHIFT)
-			|IOMUXC_GPR13_SATA_SATA_PHY_5_SS_DISABLED
-			|IOMUXC_GPR13_SATA_SATA_PHY_4_ATTEN_9_16
-			|IOMUXC_GPR13_SATA_PHY_3_TXBOOST_0P00_DB
-			|IOMUXC_GPR13_SATA_PHY_2_TX_1P104V
-			|IOMUXC_GPR13_SATA_PHY_1_SLOW);
-
-	return 0;
-}
-#endif
-
 #if defined(CONFIG_VIDEO_IPUV3)
 
 static iomux_v3_cfg_t const backlight_pads[] = {
 	/* Backlight on RGB connector: J15 */
-	MX6_PAD_SD1_DAT3__GPIO_1_21 | MUX_PAD_CTRL(NO_PAD_CTRL),
+	MX6_PAD_SD1_DAT3__GPIO1_IO21 | MUX_PAD_CTRL(NO_PAD_CTRL),
 #define RGB_BACKLIGHT_GP IMX_GPIO_NR(1, 21)
 
 	/* Backlight on LVDS connector: J6 */
-	MX6_PAD_SD1_CMD__GPIO_1_18 | MUX_PAD_CTRL(NO_PAD_CTRL),
+	MX6_PAD_SD1_CMD__GPIO1_IO18 | MUX_PAD_CTRL(NO_PAD_CTRL),
 #define LVDS_BACKLIGHT_GP IMX_GPIO_NR(1, 18)
 };
 
 static iomux_v3_cfg_t const rgb_pads[] = {
 	MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK,
 	MX6_PAD_DI0_PIN15__IPU1_DI0_PIN15,
-	MX6_PAD_DI0_PIN2__IPU1_DI0_PIN2,
-	MX6_PAD_DI0_PIN3__IPU1_DI0_PIN3,
-	MX6_PAD_DI0_PIN4__GPIO_4_20,
-	MX6_PAD_DISP0_DAT0__IPU1_DISP0_DAT_0,
-	MX6_PAD_DISP0_DAT1__IPU1_DISP0_DAT_1,
-	MX6_PAD_DISP0_DAT2__IPU1_DISP0_DAT_2,
-	MX6_PAD_DISP0_DAT3__IPU1_DISP0_DAT_3,
-	MX6_PAD_DISP0_DAT4__IPU1_DISP0_DAT_4,
-	MX6_PAD_DISP0_DAT5__IPU1_DISP0_DAT_5,
-	MX6_PAD_DISP0_DAT6__IPU1_DISP0_DAT_6,
-	MX6_PAD_DISP0_DAT7__IPU1_DISP0_DAT_7,
-	MX6_PAD_DISP0_DAT8__IPU1_DISP0_DAT_8,
-	MX6_PAD_DISP0_DAT9__IPU1_DISP0_DAT_9,
-	MX6_PAD_DISP0_DAT10__IPU1_DISP0_DAT_10,
-	MX6_PAD_DISP0_DAT11__IPU1_DISP0_DAT_11,
-	MX6_PAD_DISP0_DAT12__IPU1_DISP0_DAT_12,
-	MX6_PAD_DISP0_DAT13__IPU1_DISP0_DAT_13,
-	MX6_PAD_DISP0_DAT14__IPU1_DISP0_DAT_14,
-	MX6_PAD_DISP0_DAT15__IPU1_DISP0_DAT_15,
-	MX6_PAD_DISP0_DAT16__IPU1_DISP0_DAT_16,
-	MX6_PAD_DISP0_DAT17__IPU1_DISP0_DAT_17,
-	MX6_PAD_DISP0_DAT18__IPU1_DISP0_DAT_18,
-	MX6_PAD_DISP0_DAT19__IPU1_DISP0_DAT_19,
-	MX6_PAD_DISP0_DAT20__IPU1_DISP0_DAT_20,
-	MX6_PAD_DISP0_DAT21__IPU1_DISP0_DAT_21,
-	MX6_PAD_DISP0_DAT22__IPU1_DISP0_DAT_22,
-	MX6_PAD_DISP0_DAT23__IPU1_DISP0_DAT_23,
+	MX6_PAD_DI0_PIN2__IPU1_DI0_PIN02,
+	MX6_PAD_DI0_PIN3__IPU1_DI0_PIN03,
+	MX6_PAD_DI0_PIN4__GPIO4_IO20,
+	MX6_PAD_DISP0_DAT0__IPU1_DISP0_DATA00,
+	MX6_PAD_DISP0_DAT1__IPU1_DISP0_DATA01,
+	MX6_PAD_DISP0_DAT2__IPU1_DISP0_DATA02,
+	MX6_PAD_DISP0_DAT3__IPU1_DISP0_DATA03,
+	MX6_PAD_DISP0_DAT4__IPU1_DISP0_DATA04,
+	MX6_PAD_DISP0_DAT5__IPU1_DISP0_DATA05,
+	MX6_PAD_DISP0_DAT6__IPU1_DISP0_DATA06,
+	MX6_PAD_DISP0_DAT7__IPU1_DISP0_DATA07,
+	MX6_PAD_DISP0_DAT8__IPU1_DISP0_DATA08,
+	MX6_PAD_DISP0_DAT9__IPU1_DISP0_DATA09,
+	MX6_PAD_DISP0_DAT10__IPU1_DISP0_DATA10,
+	MX6_PAD_DISP0_DAT11__IPU1_DISP0_DATA11,
+	MX6_PAD_DISP0_DAT12__IPU1_DISP0_DATA12,
+	MX6_PAD_DISP0_DAT13__IPU1_DISP0_DATA13,
+	MX6_PAD_DISP0_DAT14__IPU1_DISP0_DATA14,
+	MX6_PAD_DISP0_DAT15__IPU1_DISP0_DATA15,
+	MX6_PAD_DISP0_DAT16__IPU1_DISP0_DATA16,
+	MX6_PAD_DISP0_DAT17__IPU1_DISP0_DATA17,
+	MX6_PAD_DISP0_DAT18__IPU1_DISP0_DATA18,
+	MX6_PAD_DISP0_DAT19__IPU1_DISP0_DATA19,
+	MX6_PAD_DISP0_DAT20__IPU1_DISP0_DATA20,
+	MX6_PAD_DISP0_DAT21__IPU1_DISP0_DATA21,
+	MX6_PAD_DISP0_DAT22__IPU1_DISP0_DATA22,
+	MX6_PAD_DISP0_DAT23__IPU1_DISP0_DATA23,
 };
 
 struct display_info_t {
@@ -685,6 +683,7 @@ int board_early_init_f(void)
 	gpio_direction_input(WL12XX_WL_IRQ_GP);
 	gpio_direction_output(WL12XX_WL_ENABLE_GP, 0);
 	gpio_direction_output(WL12XX_BT_ENABLE_GP, 0);
+	gpio_direction_output(GP_USB_OTG_PWR, 0); /* OTG power off */
 
 	imx_iomux_v3_setup_multiple_pads(wl12xx_pads, ARRAY_SIZE(wl12xx_pads));
 	setup_buttons();
@@ -706,6 +705,15 @@ int overwrite_console(void)
 
 int board_init(void)
 {
+	struct iomuxc_base_regs *const iomuxc_regs
+		= (struct iomuxc_base_regs *)IOMUXC_BASE_ADDR;
+
+	clrsetbits_le32(&iomuxc_regs->gpr[1],
+			IOMUXC_GPR1_OTG_ID_MASK,
+			IOMUXC_GPR1_OTG_ID_GPIO1);
+
+	imx_iomux_v3_setup_multiple_pads(misc_pads, ARRAY_SIZE(misc_pads));
+
 	/* address of boot parameters */
 	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
 
diff --git a/board/br4/Makefile b/board/br4/Makefile
index f023abfee4..68e24ab83f 100644
--- a/board/br4/Makefile
+++ b/board/br4/Makefile
@@ -11,24 +11,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS-y	:= $(BOARD).o
-
-SRCS	:= $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS-y))
-SOBJS	:= $(addprefix $(obj),$(SOBJS-y))
-
-$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
-	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	:= br4.o
diff --git a/board/br4/config.mk b/board/br4/config.mk
deleted file mode 100644
index 5c18d5c9e4..0000000000
--- a/board/br4/config.mk
+++ /dev/null
@@ -1,14 +0,0 @@
-#
-# Copyright (c) Switchfin Org. <dpn@switchfin.org>
-#
-# Copyright (c) 2005-2008 Analog Device Inc.
-#
-# (C) Copyright 2001
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-CFLAGS_lib += -O2
-CFLAGS_lib/lzma += -O2
-CFLAGS_lib/zlib += -O2
diff --git a/board/broadcom/bcm28155_ap/Makefile b/board/broadcom/bcm28155_ap/Makefile
new file mode 100644
index 0000000000..b18785a078
--- /dev/null
+++ b/board/broadcom/bcm28155_ap/Makefile
@@ -0,0 +1,7 @@
+#
+# Copyright 2013 Broadcom Corporation.
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y	+= $(BOARD).o
diff --git a/board/broadcom/bcm28155_ap/bcm28155_ap.c b/board/broadcom/bcm28155_ap/bcm28155_ap.c
new file mode 100644
index 0000000000..940a1c2c50
--- /dev/null
+++ b/board/broadcom/bcm28155_ap/bcm28155_ap.c
@@ -0,0 +1,87 @@
+/*
+ * Copyright 2013 Broadcom Corporation.
+ *
+ * SPDX-License-Identifier:      GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/mach-types.h>
+#include <mmc.h>
+#include <asm/kona-common/kona_sdhci.h>
+#include <asm/kona-common/clk.h>
+#include <asm/arch/sysmap.h>
+
+#define SECWATCHDOG_SDOGCR_OFFSET	0x00000000
+#define SECWATCHDOG_SDOGCR_EN_SHIFT	27
+#define SECWATCHDOG_SDOGCR_SRSTEN_SHIFT	26
+#define SECWATCHDOG_SDOGCR_CLKS_SHIFT	20
+#define SECWATCHDOG_SDOGCR_LD_SHIFT	0
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * board_init - early hardware init
+ */
+int board_init(void)
+{
+	printf("Relocation Offset is: %08lx\n", gd->reloc_off);
+
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+
+	clk_init();
+
+	return 0;
+}
+
+/*
+ * misc_init_r - miscellaneous platform dependent initializations
+ */
+int misc_init_r(void)
+{
+	/* Disable watchdog reset - watchdog unused */
+	writel((0 << SECWATCHDOG_SDOGCR_EN_SHIFT) |
+	       (0 << SECWATCHDOG_SDOGCR_SRSTEN_SHIFT) |
+	       (4 << SECWATCHDOG_SDOGCR_CLKS_SHIFT) |
+	       (0x5a0 << SECWATCHDOG_SDOGCR_LD_SHIFT),
+	       (SECWD_BASE_ADDR + SECWATCHDOG_SDOGCR_OFFSET));
+
+	return 0;
+}
+
+/*
+ * dram_init - sets uboots idea of sdram size
+ */
+int dram_init(void)
+{
+	gd->ram_size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE,
+				    CONFIG_SYS_SDRAM_SIZE);
+	return 0;
+}
+
+/* This is called after dram_init() so use get_ram_size result */
+void dram_init_banksize(void)
+{
+	gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
+	gd->bd->bi_dram[0].size = gd->ram_size;
+}
+
+#ifdef CONFIG_KONA_SDHCI
+/*
+ * mmc_init - Initializes mmc
+ */
+int board_mmc_init(bd_t *bis)
+{
+	int ret = 0;
+
+	/* Register eMMC - SDIO2 */
+	ret = kona_sdhci_init(1, 400000, 0);
+	if (ret)
+		return ret;
+
+	/* Register SD Card - SDIO4 kona_mmc_init assumes 0 based index */
+	ret = kona_sdhci_init(3, 400000, 0);
+	return ret;
+}
+#endif
diff --git a/board/buffalo/lsxl/Makefile b/board/buffalo/lsxl/Makefile
index a8700e8430..1b01b4018c 100644
--- a/board/buffalo/lsxl/Makefile
+++ b/board/buffalo/lsxl/Makefile
@@ -5,24 +5,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	:= lsxl.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
-	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	:= lsxl.o
diff --git a/board/calao/sbc35_a9g20/Makefile b/board/calao/sbc35_a9g20/Makefile
index e385f8d370..9ae2d24c59 100644
--- a/board/calao/sbc35_a9g20/Makefile
+++ b/board/calao/sbc35_a9g20/Makefile
@@ -9,25 +9,5 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS-y	+= sbc35_a9g20.o
-COBJS-$(CONFIG_ATMEL_SPI)	+= spi.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS-y))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
-	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	+= sbc35_a9g20.o
+obj-$(CONFIG_ATMEL_SPI)	+= spi.o
diff --git a/board/calao/sbc35_a9g20/sbc35_a9g20.c b/board/calao/sbc35_a9g20/sbc35_a9g20.c
index ecf261c1ae..2074a93a12 100644
--- a/board/calao/sbc35_a9g20/sbc35_a9g20.c
+++ b/board/calao/sbc35_a9g20/sbc35_a9g20.c
@@ -15,7 +15,6 @@
 #include <asm/arch/at91sam9_smc.h>
 #include <asm/arch/at91_common.h>
 #include <asm/arch/at91_pmc.h>
-#include <asm/arch/at91_rstc.h>
 #include <asm/arch/gpio.h>
 
 #if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB)
@@ -77,8 +76,6 @@ static void sbc35_a9g20_macb_hw_init(void)
 {
 	struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
 	struct at91_port *pioa = (struct at91_port *)ATMEL_BASE_PIOA;
-	struct at91_rstc *rstc = (struct at91_rstc *)ATMEL_BASE_RSTC;
-	unsigned long erstl;
 
 	/* Enable EMAC clock */
 	writel(1 << ATMEL_ID_EMAC0, &pmc->pcer);
@@ -102,21 +99,7 @@ static void sbc35_a9g20_macb_hw_init(void)
 	       pin_to_mask(AT91_PIN_PA28),
 	       &pioa->pudr);
 
-	erstl = readl(&rstc->mr) & AT91_RSTC_MR_ERSTL_MASK;
-
-	/* Need to reset PHY -> 500ms reset */
-	writel(AT91_RSTC_KEY | AT91_RSTC_MR_ERSTL(13) |
-		AT91_RSTC_MR_URSTEN, &rstc->mr);
-
-	writel(AT91_RSTC_KEY | AT91_RSTC_CR_EXTRST, &rstc->cr);
-
-	/* Wait for end hardware reset */
-	while (!(readl(&rstc->sr) & AT91_RSTC_SR_NRSTL))
-		;
-
-	/* Restore NRST value */
-	writel(AT91_RSTC_KEY | erstl | AT91_RSTC_MR_URSTEN,
-		&rstc->mr);
+	at91_phy_reset();
 
 	/* Re-enable pull-up */
 	writel(pin_to_mask(AT91_PIN_PA14) |
diff --git a/board/calao/tny_a9260/Makefile b/board/calao/tny_a9260/Makefile
index 8a95ce252e..55a6157bac 100644
--- a/board/calao/tny_a9260/Makefile
+++ b/board/calao/tny_a9260/Makefile
@@ -9,25 +9,5 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS-y	+= tny_a9260.o
-COBJS-$(CONFIG_ATMEL_SPI)	+= spi.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS-y))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
-	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	+= tny_a9260.o
+obj-$(CONFIG_ATMEL_SPI)	+= spi.o
diff --git a/board/calao/usb_a9263/Makefile b/board/calao/usb_a9263/Makefile
new file mode 100644
index 0000000000..8a22b3eac7
--- /dev/null
+++ b/board/calao/usb_a9263/Makefile
@@ -0,0 +1,14 @@
+#
+# (C) Copyright 2003-2008
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# (C) Copyright 2008
+# Stelian Pop <stelian@popies.net>
+# Lead Tech Design <www.leadtechdesign.com>
+#
+# (C) Copyright 2013
+# Mateusz Kulikowski <mateusz.kulikowski@gmail.com>
+#
+# SPDX-License-Identifier:	GPL-2.0+
+
+obj-y	+= usb_a9263.o
diff --git a/board/calao/usb_a9263/usb_a9263.c b/board/calao/usb_a9263/usb_a9263.c
new file mode 100644
index 0000000000..266e9507ef
--- /dev/null
+++ b/board/calao/usb_a9263/usb_a9263.c
@@ -0,0 +1,148 @@
+/*
+ * (C) Copyright 2007-2013
+ * Stelian Pop <stelian.pop@leadtechdesign.com>
+ * Lead Tech Design <www.leadtechdesign.com>
+ * Thomas Petazzoni, Free Electrons, <thomas.petazzoni@free-electrons.com>
+ * Mateusz Kulikowski <mateusz.kulikowski@gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/at91sam9_smc.h>
+#include <asm/arch/at91_common.h>
+#include <asm/arch/at91_matrix.h>
+#include <asm/arch/at91_pmc.h>
+#include <asm/arch/gpio.h>
+#include <asm-generic/gpio.h>
+#include <asm/io.h>
+#include <net.h>
+#include <netdev.h>
+#include <dataflash.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#ifdef CONFIG_HAS_DATAFLASH
+AT91S_DATAFLASH_INFO dataflash_info[CONFIG_SYS_MAX_DATAFLASH_BANKS];
+
+struct dataflash_addr cs[CONFIG_SYS_MAX_DATAFLASH_BANKS] = {
+	{CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0, 0},	/* Logical adress, CS */
+};
+
+/*define the area offsets*/
+dataflash_protect_t area_list[NB_DATAFLASH_AREA] = {
+	{0x00000000, 0x00001FFF, FLAG_PROTECT_SET, 0, "Bootstrap"},
+	{0x00002000, 0x00003FFF, FLAG_PROTECT_CLEAR, 0, "Environment"},
+	{0x00004000, 0xFFFFFFFF, FLAG_PROTECT_CLEAR, 0, "U-Boot"},
+};
+#endif
+
+#ifdef CONFIG_CMD_NAND
+static void usb_a9263_nand_hw_init(void)
+{
+	unsigned long csa;
+	at91_smc_t *smc = (at91_smc_t *)ATMEL_BASE_SMC0;
+	at91_matrix_t *matrix = (at91_matrix_t *)ATMEL_BASE_MATRIX;
+	at91_pmc_t *pmc = (at91_pmc_t *)ATMEL_BASE_PMC;
+
+	/* Enable CS3 */
+	csa = readl(&matrix->csa[0]) | AT91_MATRIX_CSA_EBI_CS3A;
+	writel(csa, &matrix->csa[0]);
+
+	/* Configure SMC CS3 for NAND/SmartMedia */
+	writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) |
+	       AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0),
+	       &smc->cs[3].setup);
+
+	writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) |
+	       AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3),
+	       &smc->cs[3].pulse);
+
+	writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5),
+	       &smc->cs[3].cycle);
+
+	writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
+	       AT91_SMC_MODE_EXNW_DISABLE |
+	       AT91_SMC_MODE_DBW_8 |
+	       AT91_SMC_MODE_TDF_CYCLE(2), &smc->cs[3].mode);
+
+	writel(1 << ATMEL_ID_PIOA | 1 << ATMEL_ID_PIOCDE, &pmc->pcer);
+
+	/* Configure RDY/BSY */
+	gpio_request(CONFIG_SYS_NAND_READY_PIN, "NAND ready/busy");
+	gpio_direction_input(CONFIG_SYS_NAND_READY_PIN);
+
+	/* Enable NandFlash */
+	gpio_request(CONFIG_SYS_NAND_ENABLE_PIN, "NAND enable");
+	gpio_direction_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
+}
+#endif
+
+#ifdef CONFIG_MACB
+static void usb_a9263_macb_hw_init(void)
+{
+	at91_pmc_t *pmc = (at91_pmc_t *)ATMEL_BASE_PMC;
+
+	/* Enable clock */
+	writel(1 << ATMEL_ID_EMAC, &pmc->pcer);
+
+	/*
+	 * Disable pull-up on:
+	 *  RXDV (PC25) => PHY normal mode (not Test mode)
+	 *  ERX0 (PE25) => PHY ADDR0
+	 *  ERX1 (PE26) => PHY ADDR1 => PHYADDR = 0x0
+	 *
+	 * PHY has internal weak pull-up/pull-down
+	 */
+	gpio_request(GPIO_PIN_PC(25), "PHY mode");
+	gpio_direction_input(GPIO_PIN_PC(25));
+
+	gpio_request(GPIO_PIN_PE(25), "PHY ADDR0");
+	gpio_direction_input(GPIO_PIN_PE(25));
+
+	gpio_request(GPIO_PIN_PE(26), "PHY ADDR1");
+	gpio_direction_input(GPIO_PIN_PE(26));
+
+	at91_phy_reset();
+
+	/* It will set proper pinmux for ports PC25, PE25-26 */
+	at91_macb_hw_init();
+}
+#endif
+
+int board_init(void)
+{
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+
+#ifdef CONFIG_CMD_NAND
+	usb_a9263_nand_hw_init();
+#endif
+#ifdef CONFIG_HAS_DATAFLASH
+	at91_spi0_hw_init(1 << 0);
+#endif
+#ifdef CONFIG_MACB
+	usb_a9263_macb_hw_init();
+#endif
+#ifdef CONFIG_USB_OHCI_NEW
+	at91_uhp_hw_init();
+#endif
+	return 0;
+}
+
+int dram_init(void)
+{
+	gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
+				    CONFIG_SYS_SDRAM_SIZE);
+	return 0;
+}
+
+int board_eth_init(bd_t *bis)
+{
+	int rc = 0;
+
+#ifdef CONFIG_MACB
+	rc = macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC, 0x0001);
+#endif
+	return rc;
+}
diff --git a/board/canmb/Makefile b/board/canmb/Makefile
index 4698706bb9..4286a9123c 100644
--- a/board/canmb/Makefile
+++ b/board/canmb/Makefile
@@ -5,28 +5,5 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-#ifneq ($(OBJTREE),$(SRCTREE))
-#$(shell mkdir -p $(obj)../common)
-#endif
+obj-y	:= canmb.o
 
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	:= $(BOARD).o
-#../common/flash.o ../common/vpd.o ../common/am79c874.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
diff --git a/board/chromebook-x86/coreboot/Makefile b/board/chromebook-x86/coreboot/Makefile
index e2222ab674..4f2ac898eb 100644
--- a/board/chromebook-x86/coreboot/Makefile
+++ b/board/chromebook-x86/coreboot/Makefile
@@ -12,23 +12,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-SOBJS-y	+= coreboot_start.o
-
-SRCS	:= $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
-OBJS	:= $(addprefix $(obj),$(SOBJS-y) $(COBJS-y))
-
-$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
-	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	+= coreboot_start.o
diff --git a/board/chromebook-x86/coreboot/config.mk b/board/chromebook-x86/coreboot/config.mk
deleted file mode 100644
index 0c05dd03db..0000000000
--- a/board/chromebook-x86/coreboot/config.mk
+++ /dev/null
@@ -1,7 +0,0 @@
-#
-# Copyright (c) 2011 The Chromium OS Authors. All rights reserved.
-#
-# SPDX-License-Identifier:	GPL-2.0	BSD-3-Clause
-#
-
-HOSTCFLAGS_autoconf.mk.dep = -Wno-variadic-macros
diff --git a/board/cloudengines/pogo_e02/Makefile b/board/cloudengines/pogo_e02/Makefile
index 3bda5e1eb7..8ff0f4505c 100644
--- a/board/cloudengines/pogo_e02/Makefile
+++ b/board/cloudengines/pogo_e02/Makefile
@@ -6,24 +6,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	:= pogo_e02.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
-	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	:= pogo_e02.o
diff --git a/board/cm-bf527/Makefile b/board/cm-bf527/Makefile
index 57b0a7c83d..ff8ad43d51 100644
--- a/board/cm-bf527/Makefile
+++ b/board/cm-bf527/Makefile
@@ -9,24 +9,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS-y	:= $(BOARD).o gpio_cfi_flash.o
-
-SRCS	:= $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS-y))
-SOBJS	:= $(addprefix $(obj),$(SOBJS-y))
-
-$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
-	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	:= cm-bf527.o gpio_cfi_flash.o
diff --git a/board/cm-bf527/config.mk b/board/cm-bf527/config.mk
deleted file mode 100644
index f1ef9bf682..0000000000
--- a/board/cm-bf527/config.mk
+++ /dev/null
@@ -1,12 +0,0 @@
-#
-# Copyright (c) 2005-2008 Analog Device Inc.
-#
-# (C) Copyright 2001
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-CFLAGS_lib += -O2
-CFLAGS_lib/lzma += -O2
-CFLAGS_lib/zlib += -O2
diff --git a/board/cm-bf533/Makefile b/board/cm-bf533/Makefile
index b7275f49fe..ec99638d0a 100644
--- a/board/cm-bf533/Makefile
+++ b/board/cm-bf533/Makefile
@@ -9,24 +9,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS-y	:= $(BOARD).o
-
-SRCS	:= $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS-y))
-SOBJS	:= $(addprefix $(obj),$(SOBJS-y))
-
-$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
-	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	:= cm-bf533.o
diff --git a/board/cm-bf533/config.mk b/board/cm-bf533/config.mk
index 973d357559..7f9138b09b 100644
--- a/board/cm-bf533/config.mk
+++ b/board/cm-bf533/config.mk
@@ -7,9 +7,5 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-CFLAGS_lib += -O2
-CFLAGS_lib/lzma += -O2
-CFLAGS_lib/zlib += -O2
-
 # Set some default LDR flags based on boot mode.
 LDR_FLAGS-BFIN_BOOT_PARA := --bits 16 --dma 8
diff --git a/board/cm-bf537e/Makefile b/board/cm-bf537e/Makefile
index 57b0a7c83d..be8056f4ba 100644
--- a/board/cm-bf537e/Makefile
+++ b/board/cm-bf537e/Makefile
@@ -9,24 +9,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS-y	:= $(BOARD).o gpio_cfi_flash.o
-
-SRCS	:= $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS-y))
-SOBJS	:= $(addprefix $(obj),$(SOBJS-y))
-
-$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
-	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	:= cm-bf537e.o gpio_cfi_flash.o
diff --git a/board/cm-bf537e/config.mk b/board/cm-bf537e/config.mk
index 973d357559..7f9138b09b 100644
--- a/board/cm-bf537e/config.mk
+++ b/board/cm-bf537e/config.mk
@@ -7,9 +7,5 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-CFLAGS_lib += -O2
-CFLAGS_lib/lzma += -O2
-CFLAGS_lib/zlib += -O2
-
 # Set some default LDR flags based on boot mode.
 LDR_FLAGS-BFIN_BOOT_PARA := --bits 16 --dma 8
diff --git a/board/cm-bf537u/Makefile b/board/cm-bf537u/Makefile
index 57b0a7c83d..38dd3fbb21 100644
--- a/board/cm-bf537u/Makefile
+++ b/board/cm-bf537u/Makefile
@@ -9,24 +9,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS-y	:= $(BOARD).o gpio_cfi_flash.o
-
-SRCS	:= $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS-y))
-SOBJS	:= $(addprefix $(obj),$(SOBJS-y))
-
-$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
-	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	:= cm-bf537u.o gpio_cfi_flash.o
diff --git a/board/cm-bf537u/config.mk b/board/cm-bf537u/config.mk
index 973d357559..7f9138b09b 100644
--- a/board/cm-bf537u/config.mk
+++ b/board/cm-bf537u/config.mk
@@ -7,9 +7,5 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-CFLAGS_lib += -O2
-CFLAGS_lib/lzma += -O2
-CFLAGS_lib/zlib += -O2
-
 # Set some default LDR flags based on boot mode.
 LDR_FLAGS-BFIN_BOOT_PARA := --bits 16 --dma 8
diff --git a/board/cm-bf548/Makefile b/board/cm-bf548/Makefile
index 1a6ca64c72..98aca32b1f 100644
--- a/board/cm-bf548/Makefile
+++ b/board/cm-bf548/Makefile
@@ -9,25 +9,5 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS-y	:= $(BOARD).o
-COBJS-$(CONFIG_VIDEO)      += video.o
-
-SRCS	:= $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS-y))
-SOBJS	:= $(addprefix $(obj),$(SOBJS-y))
-
-$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
-	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	:= cm-bf548.o
+obj-$(CONFIG_VIDEO)      += video.o
diff --git a/board/cm-bf548/config.mk b/board/cm-bf548/config.mk
index c005afb881..beb9834649 100644
--- a/board/cm-bf548/config.mk
+++ b/board/cm-bf548/config.mk
@@ -7,10 +7,6 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-CFLAGS_lib += -O2
-CFLAGS_lib/lzma += -O2
-CFLAGS_lib/zlib += -O2
-
 # Set some default LDR flags based on boot mode.
 LDR_FLAGS-BFIN_BOOT_PARA       := --dma 6
 LDR_FLAGS-BFIN_BOOT_FIFO       := --dma 1
diff --git a/board/cm-bf548/video.c b/board/cm-bf548/video.c
index a43413e976..c35d285070 100644
--- a/board/cm-bf548/video.c
+++ b/board/cm-bf548/video.c
@@ -11,6 +11,7 @@
 #include <config.h>
 #include <malloc.h>
 #include <asm/blackfin.h>
+#include <asm/clock.h>
 #include <asm/gpio.h>
 #include <asm/portmux.h>
 #include <asm/mach-common/bits/dma.h>
diff --git a/board/cm-bf561/Makefile b/board/cm-bf561/Makefile
index b7275f49fe..c8764fb3ce 100644
--- a/board/cm-bf561/Makefile
+++ b/board/cm-bf561/Makefile
@@ -9,24 +9,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS-y	:= $(BOARD).o
-
-SRCS	:= $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS-y))
-SOBJS	:= $(addprefix $(obj),$(SOBJS-y))
-
-$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
-	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	:= cm-bf561.o
diff --git a/board/cm-bf561/config.mk b/board/cm-bf561/config.mk
index c33aef9d28..854d7dbb86 100644
--- a/board/cm-bf561/config.mk
+++ b/board/cm-bf561/config.mk
@@ -7,9 +7,5 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-CFLAGS_lib += -O2
-CFLAGS_lib/lzma += -O2
-CFLAGS_lib/zlib += -O2
-
 # Set some default LDR flags based on boot mode.
 LDR_FLAGS-BFIN_BOOT_PARA := --bits 16
diff --git a/board/cm4008/Makefile b/board/cm4008/Makefile
index d8f9d5400a..04b152917b 100644
--- a/board/cm4008/Makefile
+++ b/board/cm4008/Makefile
@@ -5,24 +5,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	:= cm4008.o flash.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
-	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	:= cm4008.o flash.o
diff --git a/board/cm4008/flash.c b/board/cm4008/flash.c
index 251192839e..8315a57ed9 100644
--- a/board/cm4008/flash.c
+++ b/board/cm4008/flash.c
@@ -57,7 +57,7 @@ unsigned long flash_init (void)
 	 */
 	flash_protect (FLAG_PROTECT_SET,
 		       CONFIG_SYS_FLASH_BASE,
-		       CONFIG_SYS_FLASH_BASE + _bss_start_ofs,
+		       CONFIG_SYS_FLASH_BASE + (__bss_end - __bss_start),
 		       &flash_info[0]);
 
 	return size;
diff --git a/board/cm41xx/Makefile b/board/cm41xx/Makefile
index 752bfdb2ff..b71ea05566 100644
--- a/board/cm41xx/Makefile
+++ b/board/cm41xx/Makefile
@@ -5,24 +5,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	:= cm41xx.o flash.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
-	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	:= cm41xx.o flash.o
diff --git a/board/cm41xx/flash.c b/board/cm41xx/flash.c
index 251192839e..8315a57ed9 100644
--- a/board/cm41xx/flash.c
+++ b/board/cm41xx/flash.c
@@ -57,7 +57,7 @@ unsigned long flash_init (void)
 	 */
 	flash_protect (FLAG_PROTECT_SET,
 		       CONFIG_SYS_FLASH_BASE,
-		       CONFIG_SYS_FLASH_BASE + _bss_start_ofs,
+		       CONFIG_SYS_FLASH_BASE + (__bss_end - __bss_start),
 		       &flash_info[0]);
 
 	return size;
diff --git a/board/cm5200/Makefile b/board/cm5200/Makefile
index 59353e9895..76f8b9fc05 100644
--- a/board/cm5200/Makefile
+++ b/board/cm5200/Makefile
@@ -5,24 +5,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	:= $(BOARD).o cmd_cm5200.o fwupdate.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	:= cm5200.o cmd_cm5200.o fwupdate.o
diff --git a/board/cmi/Makefile b/board/cmi/Makefile
index 0d1c6fbb21..cd3bb0db21 100644
--- a/board/cmi/Makefile
+++ b/board/cmi/Makefile
@@ -5,24 +5,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	:= flash.o cmi.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	:= flash.o cmi.o
diff --git a/board/cobra5272/Makefile b/board/cobra5272/Makefile
index 871865b6ee..fbbbb877c7 100644
--- a/board/cobra5272/Makefile
+++ b/board/cobra5272/Makefile
@@ -5,24 +5,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	= $(BOARD).o flash.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	= cobra5272.o flash.o
diff --git a/board/cogent/Makefile b/board/cogent/Makefile
index e7d69dffdc..30fe98d4dd 100644
--- a/board/cogent/Makefile
+++ b/board/cogent/Makefile
@@ -5,24 +5,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	:= mb.o flash.o dipsw.o lcd.o serial.o # pci.o rtc.o par.o kbm.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	:= mb.o flash.o dipsw.o lcd.o serial.o # pci.o rtc.o par.o kbm.o
diff --git a/board/cogent/config.mk b/board/cogent/config.mk
deleted file mode 100644
index 1452d46a9f..0000000000
--- a/board/cogent/config.mk
+++ /dev/null
@@ -1,12 +0,0 @@
-#
-# (C) Copyright 2000
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-#
-# Cogent Modular Architecture
-#
-
-PLATFORM_CPPFLAGS += -I$(TOPDIR)
diff --git a/board/cogent/dipsw.c b/board/cogent/dipsw.c
index d2027c9758..ecfbc25981 100644
--- a/board/cogent/dipsw.c
+++ b/board/cogent/dipsw.c
@@ -1,5 +1,5 @@
 #include <common.h>
-#include <board/cogent/dipsw.h>
+#include "dipsw.h"
 
 unsigned char
 dipsw_raw(void)
diff --git a/board/cogent/flash.c b/board/cogent/flash.c
index d4ae4d0a3c..1da8f10a1f 100644
--- a/board/cogent/flash.c
+++ b/board/cogent/flash.c
@@ -6,7 +6,7 @@
  */
 
 #include <common.h>
-#include <board/cogent/flash.h>
+#include "flash.h"
 #include <linux/compiler.h>
 
 flash_info_t	flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
diff --git a/board/cogent/kbm.h b/board/cogent/kbm.h
deleted file mode 100644
index 7eb419c1d6..0000000000
--- a/board/cogent/kbm.h
+++ /dev/null
@@ -1,79 +0,0 @@
-/* keyboard/mouse not implemented yet */
-
-extern int cma_kbm_not_implemented;
-
-/**************** DEFINES for H8542B Keyboard/Mouse Controller ***************/
-
-/*
- * note the auxillary port is used to control the mouse
- */
-
-/* 8542B Commands (Sent to the Command Port) */
-#define HT8542_CMD_SET_BYTE	0x60	/* Set the command byte */
-#define HT8542_CMD_GET_BYTE	0x20	/* Get the command byte */
-#define HT8542_CMD_KBD_OBUFF	0xD2	/* Write to HT8542 Kbd Output Buffer */
-#define HT8542_CMD_AUX_OBUFF	0xD3	/* Write to HT8542 Mse Output Buffer */
-#define HT8542_CMD_AUX_WRITE	0xD4	/* Write to Mouse Port */
-#define HT8542_CMD_AUX_OFF	0xA7	/* Disable Mouse Port */
-#define HT8542_CMD_AUX_ON	0xA8	/* Re-Enable Mouse Port */
-#define HT8542_CMD_AUX_TEST	0xA9	/* Test for the presence of a Mouse */
-#define HT8542_CMD_DIAG		0xAA	/* Start Diagnostics */
-#define HT8542_CMD_KBD_TEST	0xAB	/* Test for presence of a keyboard */
-#define HT8542_CMD_KBD_OFF	0xAD	/* Disable Kbd Port (use KBD_DAT_ON) */
-#define HT8542_CMD_KBD_ON	0xAE	/* Enable Kbd Port (use KBD_DAT_OFF) */
-
-/* HT8542B cmd byte set by KBD_CMD_SET_BYTE and retrieved by KBD_CMD_GET_BYTE */
-#define HT8542_CMD_BYTE_TRANS	0x40
-#define HT8542_CMD_BYTE_AUX_OFF	0x20	/* 1 = mse port disabled, 0 = enabled */
-#define HT8542_CMD_BYTE_KBD_OFF	0x10	/* 1 = kbd port disabled, 0 = enabled */
-#define HT8542_CMD_BYTE_OVER	0x08	/* 1 = override keyboard lock */
-#define HT8542_CMD_BYTE_RES	0x04	/* reserved */
-#define HT8542_CMD_BYTE_AUX_INT	0x02	/* 1 = enable mouse interrupt */
-#define HT8542_CMD_BYTE_KBD_INT	0x01	/* 1 = enable keyboard interrupt */
-
-/* Keyboard Commands (Sent to the Data Port) */
-#define KBD_CMD_LED		0xED	/* Set Keyboard LEDS with next byte */
-#define KBD_CMD_ECHO		0xEE	/* Echo - we get 0xFA, 0xEE back */
-#define KBD_CMD_MODE		0xF0	/* set scan code mode with next byte */
-#define KBD_CMD_ID		0xF2	/* get keyboard/mouse ID */
-#define KBD_CMD_RPT		0xF3	/* Set Repeat Rate and Delay 2nd Byte */
-#define KBD_CMD_ON		0xF4	/* Enable keyboard */
-#define KBD_CMD_OFF		0xF5	/* Disables Scanning, Resets to Def */
-#define KBD_CMD_DEF		0xF6	/* Reverts kbd to default settings */
-#define KBD_CMD_RST		0xFF	/* Reset - should get 0xFA, 0xAA back */
-
-/* Set LED second bit defines */
-#define KBD_CMD_LED_SCROLL	0x01	/* Set SCROLL LOCK LED on */
-#define KBD_CMD_LED_NUM		0x02	/* Set NUM LOCK LED on */
-#define KBD_CMD_LED_CAPS	0x04	/* Set CAPS LOCK LED on */
-
-/* Set Mode second byte defines */
-#define KBD_CMD_MODE_STAT	0x00	/* get current scan code mode */
-#define KBD_CMD_MODE_SCAN1	0x01	/* set mode to scan code 1 */
-#define KBD_CMD_MODE_SCAN2	0x02	/* set mode to scan code 2 */
-#define KBD_CMD_MODE_SCAN3	0x03	/* set mode to scan code 3 */
-
-/* Keyboard/Mouse ID Codes */
-#define KBD_CMD_ID_1ST		0xAB	/* 1st byte is 0xAB, 2nd is actual ID */
-#define KBD_CMD_ID_KBD		0x83	/* Keyboard */
-#define KBD_CMD_ID_MOUSE	0x00	/* Mouse */
-
-/* Keyboard Data Return Defines */
-#define KBD_STAT_OVER		0x00	/* Buffer Overrun */
-#define KBD_STAT_DIAG_OK	0x55	/* Internal Self Test OK */
-#define KBD_STAT_RST_OK		0xAA	/* Reset Complete */
-#define KBD_STAT_ECHO		0xEE	/* Echo Command Return */
-#define KBD_STAT_BRK		0xF0	/* Prefix for Break Key Code */
-#define KBD_STAT_ACK		0xFA	/* Received after all commands */
-#define KBD_STAT_DIAG_FAIL	0xFD	/* Internal Self Test Failed */
-#define KBD_STAT_RESEND		0xFE	/* Resend Last Command */
-
-/* HT8542B Status Register Bit Defines */
-#define HT8542_STAT_OBF		0x01	/* 1 = output buffer is full */
-#define HT8542_STAT_IBF		0x02	/* 1 = input buffer is full */
-#define HT8542_STAT_SYS		0x04	/* system flag - unused */
-#define HT8542_STAT_CMD		0x08	/* 1 = cmd in input buffer, 0 = data */
-#define HT8542_STAT_INH		0x10	/* 1 = Inhibit - unused */
-#define HT8542_STAT_TX		0x20	/* 1 = Transmit Timeout has occured */
-#define HT8542_STAT_RX		0x40	/* 1 = Receive Timeout has occured */
-#define HT8542_STAT_PERR	0x80	/* 1 = Parity Error from Keyboard */
diff --git a/board/cogent/lcd.c b/board/cogent/lcd.c
index 76f5ad103f..8e90f9853a 100644
--- a/board/cogent/lcd.c
+++ b/board/cogent/lcd.c
@@ -48,7 +48,7 @@
 
 #include <common.h>
 #include <stdarg.h>
-#include <board/cogent/lcd.h>
+#include "lcd.h"
 
 static char lines[2][LCD_LINE_LENGTH+1];
 static int curline;
diff --git a/board/cogent/mb.c b/board/cogent/mb.c
index 603f1235a4..c0256433ce 100644
--- a/board/cogent/mb.c
+++ b/board/cogent/mb.c
@@ -6,15 +6,15 @@
  */
 
 #include <common.h>
-#include <board/cogent/dipsw.h>
-#include <board/cogent/lcd.h>
-#include <board/cogent/rtc.h>
-#include <board/cogent/par.h>
-#include <board/cogent/pci.h>
+#include "dipsw.h"
+#include "lcd.h"
+#include "rtc.h"
+#include "par.h"
+#include "pci.h"
 
 /* ------------------------------------------------------------------------- */
 
-#if defined(CONFIG_8260)
+#if defined(CONFIG_MPC8260)
 
 #include <ioports.h>
 
@@ -186,7 +186,7 @@ const iop_conf_t iop_conf_tab[4][32] = {
 	 }
 };
 
-#endif /* CONFIG_8260 */
+#endif /* CONFIG_MPC8260 */
 
 /* ------------------------------------------------------------------------- */
 
diff --git a/board/cogent/serial.c b/board/cogent/serial.c
index 20631d162d..95c8120722 100644
--- a/board/cogent/serial.c
+++ b/board/cogent/serial.c
@@ -4,7 +4,7 @@
  */
 
 #include <common.h>
-#include <board/cogent/serial.h>
+#include "serial.h"
 #include <serial.h>
 #include <linux/compiler.h>
 
@@ -13,7 +13,7 @@ DECLARE_GLOBAL_DATA_PTR;
 #if (CMA_MB_CAPS & CMA_MB_CAP_SERPAR)
 
 #if (defined(CONFIG_8xx) && defined(CONFIG_8xx_CONS_NONE)) || \
-     (defined(CONFIG_8260) && defined(CONFIG_CONS_NONE))
+	(defined(CONFIG_MPC8260) && defined(CONFIG_CONS_NONE))
 
 #if CONFIG_CONS_INDEX == 1
 #define CMA_MB_SERIAL_BASE	CMA_MB_SERIALA_BASE
diff --git a/board/comelit/dig297/Makefile b/board/comelit/dig297/Makefile
index 1a5b598077..1c85b63bf3 100644
--- a/board/comelit/dig297/Makefile
+++ b/board/comelit/dig297/Makefile
@@ -5,23 +5,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	:= dig297.o
-
-SRCS	:= $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	:= dig297.o
diff --git a/board/compal/paz00/Makefile b/board/compal/paz00/Makefile
index fa5c510340..e6a0b29997 100644
--- a/board/compal/paz00/Makefile
+++ b/board/compal/paz00/Makefile
@@ -14,28 +14,6 @@
 # more details.
 #
 
-include $(TOPDIR)/config.mk
+obj-y	:= paz00.o
 
-$(shell mkdir -p $(obj)../../nvidia/common)
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS-y	:= $(BOARD).o
-
-include ../../nvidia/common/common.mk
-
-COBJS	:= $(COBJS-y)
-SRCS	:= $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+include $(srctree)/board/nvidia/common/common.mk
diff --git a/board/compulab/cm_t335/Makefile b/board/compulab/cm_t335/Makefile
new file mode 100644
index 0000000000..0e6e96e039
--- /dev/null
+++ b/board/compulab/cm_t335/Makefile
@@ -0,0 +1,10 @@
+#
+# Copyright (C) 2013 Compulab Ltd - http://compulab.co.il/
+#
+# Author: Ilya Ledvich <ilya@compulab.co.il>
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y	+= $(BOARD).o
+obj-$(CONFIG_SPL_BUILD) += mux.o spl.o
diff --git a/board/compulab/cm_t335/cm_t335.c b/board/compulab/cm_t335/cm_t335.c
new file mode 100644
index 0000000000..9583149bed
--- /dev/null
+++ b/board/compulab/cm_t335/cm_t335.c
@@ -0,0 +1,162 @@
+/*
+ * Board functions for Compulab CM-T335 board
+ *
+ * Copyright (C) 2013, Compulab Ltd - http://compulab.co.il/
+ *
+ * Author: Ilya Ledvich <ilya@compulab.co.il>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <errno.h>
+#include <miiphy.h>
+#include <cpsw.h>
+
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/hardware_am33xx.h>
+#include <asm/io.h>
+#include <asm/gpio.h>
+
+#include "../common/eeprom.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * Basic board specific setup.  Pinmux has been handled already.
+ */
+int board_init(void)
+{
+	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+
+	gpmc_init();
+
+#if defined(CONFIG_STATUS_LED) && defined(STATUS_LED_BOOT)
+	status_led_set(STATUS_LED_BOOT, STATUS_LED_OFF);
+#endif
+	return 0;
+}
+
+#if defined (CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)
+static void cpsw_control(int enabled)
+{
+	/* VTP can be added here */
+	return;
+}
+
+static struct cpsw_slave_data cpsw_slave = {
+	.slave_reg_ofs	= 0x208,
+	.sliver_reg_ofs	= 0xd80,
+	.phy_addr	= 0,
+	.phy_if		= PHY_INTERFACE_MODE_RGMII,
+};
+
+static struct cpsw_platform_data cpsw_data = {
+	.mdio_base		= CPSW_MDIO_BASE,
+	.cpsw_base		= CPSW_BASE,
+	.mdio_div		= 0xff,
+	.channels		= 8,
+	.cpdma_reg_ofs		= 0x800,
+	.slaves			= 1,
+	.slave_data		= &cpsw_slave,
+	.ale_reg_ofs		= 0xd00,
+	.ale_entries		= 1024,
+	.host_port_reg_ofs	= 0x108,
+	.hw_stats_reg_ofs	= 0x900,
+	.bd_ram_ofs		= 0x2000,
+	.mac_control		= (1 << 5),
+	.control		= cpsw_control,
+	.host_port_num		= 0,
+	.version		= CPSW_CTRL_VERSION_2,
+};
+
+/* PHY reset GPIO */
+#define GPIO_PHY_RST		GPIO_PIN(3, 7)
+
+static void board_phy_init(void)
+{
+	gpio_request(GPIO_PHY_RST, "phy_rst");
+	gpio_direction_output(GPIO_PHY_RST, 0);
+	mdelay(2);
+	gpio_set_value(GPIO_PHY_RST, 1);
+	mdelay(2);
+}
+
+static void get_efuse_mac_addr(uchar *enetaddr)
+{
+	uint32_t mac_hi, mac_lo;
+	struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
+
+	mac_lo = readl(&cdev->macid0l);
+	mac_hi = readl(&cdev->macid0h);
+	enetaddr[0] = mac_hi & 0xFF;
+	enetaddr[1] = (mac_hi & 0xFF00) >> 8;
+	enetaddr[2] = (mac_hi & 0xFF0000) >> 16;
+	enetaddr[3] = (mac_hi & 0xFF000000) >> 24;
+	enetaddr[4] = mac_lo & 0xFF;
+	enetaddr[5] = (mac_lo & 0xFF00) >> 8;
+}
+
+/*
+ * Routine: handle_mac_address
+ * Description: prepare MAC address for on-board Ethernet.
+ */
+static int handle_mac_address(void)
+{
+	uchar enetaddr[6];
+	int rv;
+
+	rv = eth_getenv_enetaddr("ethaddr", enetaddr);
+	if (rv)
+		return 0;
+
+	rv = cl_eeprom_read_mac_addr(enetaddr);
+	if (rv)
+		get_efuse_mac_addr(enetaddr);
+
+	if (!is_valid_ether_addr(enetaddr))
+		return -1;
+
+	return eth_setenv_enetaddr("ethaddr", enetaddr);
+}
+
+#define AR8051_PHY_DEBUG_ADDR_REG	0x1d
+#define AR8051_PHY_DEBUG_DATA_REG	0x1e
+#define AR8051_DEBUG_RGMII_CLK_DLY_REG	0x5
+#define AR8051_RGMII_TX_CLK_DLY		0x100
+
+int board_eth_init(bd_t *bis)
+{
+	int rv, n = 0;
+	const char *devname;
+	struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
+
+	rv = handle_mac_address();
+	if (rv)
+		printf("No MAC address found!\n");
+
+	writel(RGMII_MODE_ENABLE | RGMII_INT_DELAY, &cdev->miisel);
+
+	board_phy_init();
+
+	rv = cpsw_register(&cpsw_data);
+	if (rv < 0)
+		printf("Error %d registering CPSW switch\n", rv);
+	else
+		n += rv;
+
+	/*
+	 * CPSW RGMII Internal Delay Mode is not supported in all PVT
+	 * operating points.  So we must set the TX clock delay feature
+	 * in the AR8051 PHY.  Since we only support a single ethernet
+	 * device, we only do this for the first instance.
+	 */
+	devname = miiphy_get_current_dev();
+
+	miiphy_write(devname, 0x0, AR8051_PHY_DEBUG_ADDR_REG,
+		     AR8051_DEBUG_RGMII_CLK_DLY_REG);
+	miiphy_write(devname, 0x0, AR8051_PHY_DEBUG_DATA_REG,
+		     AR8051_RGMII_TX_CLK_DLY);
+	return n;
+}
+#endif /* CONFIG_DRIVER_TI_CPSW && !CONFIG_SPL_BUILD */
diff --git a/board/compulab/cm_t335/mux.c b/board/compulab/cm_t335/mux.c
new file mode 100644
index 0000000000..7d2beb01e5
--- /dev/null
+++ b/board/compulab/cm_t335/mux.c
@@ -0,0 +1,117 @@
+/*
+ * Pinmux configuration for Compulab CM-T335 board
+ *
+ * Copyright (C) 2013, Compulab Ltd - http://compulab.co.il/
+ *
+ * Author: Ilya Ledvich <ilya@compulab.co.il>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/mux.h>
+#include <asm/io.h>
+
+static struct module_pin_mux uart0_pin_mux[] = {
+	{OFFSET(uart0_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)},
+	{OFFSET(uart0_txd), (MODE(0) | PULLUDEN)},
+	{-1},
+};
+
+static struct module_pin_mux uart1_pin_mux[] = {
+	{OFFSET(uart1_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)},
+	{OFFSET(uart1_txd), (MODE(0) | PULLUDEN)},
+	{OFFSET(uart1_ctsn), (MODE(0) | PULLUP_EN | RXACTIVE)},
+	{OFFSET(uart1_rtsn), (MODE(0) | PULLUDEN)},
+	{-1},
+};
+
+static struct module_pin_mux mmc0_pin_mux[] = {
+	{OFFSET(mmc0_dat3), (MODE(0) | RXACTIVE | PULLUP_EN)},
+	{OFFSET(mmc0_dat2), (MODE(0) | RXACTIVE | PULLUP_EN)},
+	{OFFSET(mmc0_dat1), (MODE(0) | RXACTIVE | PULLUP_EN)},
+	{OFFSET(mmc0_dat0), (MODE(0) | RXACTIVE | PULLUP_EN)},
+	{OFFSET(mmc0_clk), (MODE(0) | RXACTIVE | PULLUP_EN)},
+	{OFFSET(mmc0_cmd), (MODE(0) | RXACTIVE | PULLUP_EN)},
+	{-1},
+};
+
+static struct module_pin_mux i2c0_pin_mux[] = {
+	{OFFSET(i2c0_sda), (MODE(0) | RXACTIVE | PULLUDDIS | SLEWCTRL)},
+	{OFFSET(i2c0_scl), (MODE(0) | RXACTIVE | PULLUDDIS | SLEWCTRL)},
+	{-1},
+};
+
+static struct module_pin_mux i2c1_pin_mux[] = {
+	/* I2C_DATA */
+	{OFFSET(uart0_ctsn), (MODE(3) | RXACTIVE | PULLUDDIS | SLEWCTRL)},
+	/* I2C_SCLK */
+	{OFFSET(uart0_rtsn), (MODE(3) | RXACTIVE | PULLUDDIS | SLEWCTRL)},
+	{-1},
+};
+
+static struct module_pin_mux rgmii1_pin_mux[] = {
+	{OFFSET(mii1_txen), MODE(2)},			/* RGMII1_TCTL */
+	{OFFSET(mii1_rxdv), MODE(2) | RXACTIVE},	/* RGMII1_RCTL */
+	{OFFSET(mii1_txd3), MODE(2)},			/* RGMII1_TD3 */
+	{OFFSET(mii1_txd2), MODE(2)},			/* RGMII1_TD2 */
+	{OFFSET(mii1_txd1), MODE(2)},			/* RGMII1_TD1 */
+	{OFFSET(mii1_txd0), MODE(2)},			/* RGMII1_TD0 */
+	{OFFSET(mii1_txclk), MODE(2)},			/* RGMII1_TCLK */
+	{OFFSET(mii1_rxclk), MODE(2) | RXACTIVE},	/* RGMII1_RCLK */
+	{OFFSET(mii1_rxd3), MODE(2) | RXACTIVE},	/* RGMII1_RD3 */
+	{OFFSET(mii1_rxd2), MODE(2) | RXACTIVE},	/* RGMII1_RD2 */
+	{OFFSET(mii1_rxd1), MODE(2) | RXACTIVE},	/* RGMII1_RD1 */
+	{OFFSET(mii1_rxd0), MODE(2) | RXACTIVE},	/* RGMII1_RD0 */
+	{OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN},/* MDIO_DATA */
+	{OFFSET(mdio_clk), MODE(0) | PULLUP_EN},	/* MDIO_CLK */
+	{-1},
+};
+
+static struct module_pin_mux nand_pin_mux[] = {
+	{OFFSET(gpmc_ad0), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* NAND AD0 */
+	{OFFSET(gpmc_ad1), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* NAND AD1 */
+	{OFFSET(gpmc_ad2), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* NAND AD2 */
+	{OFFSET(gpmc_ad3), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* NAND AD3 */
+	{OFFSET(gpmc_ad4), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* NAND AD4 */
+	{OFFSET(gpmc_ad5), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* NAND AD5 */
+	{OFFSET(gpmc_ad6), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* NAND AD6 */
+	{OFFSET(gpmc_ad7), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* NAND AD7 */
+	{OFFSET(gpmc_wait0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* NAND WAIT */
+	{OFFSET(gpmc_wpn), (MODE(7) | PULLUP_EN | RXACTIVE)},	/* NAND_WPN */
+	{OFFSET(gpmc_csn0), (MODE(0) | PULLUDEN)},		/* NAND_CS0 */
+	{OFFSET(gpmc_advn_ale), (MODE(0) | PULLUDEN)},	/* NAND_ADV_ALE */
+	{OFFSET(gpmc_oen_ren), (MODE(0) | PULLUDEN)},	/* NAND_OE */
+	{OFFSET(gpmc_wen), (MODE(0) | PULLUDEN)},	/* NAND_WEN */
+	{OFFSET(gpmc_be0n_cle), (MODE(0) | PULLUDEN)},	/* NAND_BE_CLE */
+	{-1},
+};
+
+static struct module_pin_mux eth_phy_rst_pin_mux[] = {
+	{OFFSET(emu0), (MODE(7) | PULLUDDIS)},	/* GPIO3_7 */
+	{-1},
+};
+
+static struct module_pin_mux status_led_pin_mux[] = {
+	{OFFSET(gpmc_csn3), (MODE(7) | PULLUDEN)},	/* GPIO2_0 */
+	{-1},
+};
+
+void set_uart_mux_conf(void)
+{
+	configure_module_pin_mux(uart0_pin_mux);
+	configure_module_pin_mux(uart1_pin_mux);
+}
+
+void set_mux_conf_regs(void)
+{
+	configure_module_pin_mux(i2c0_pin_mux);
+	configure_module_pin_mux(i2c1_pin_mux);
+	configure_module_pin_mux(rgmii1_pin_mux);
+	configure_module_pin_mux(eth_phy_rst_pin_mux);
+	configure_module_pin_mux(mmc0_pin_mux);
+	configure_module_pin_mux(nand_pin_mux);
+	configure_module_pin_mux(status_led_pin_mux);
+}
diff --git a/board/compulab/cm_t335/spl.c b/board/compulab/cm_t335/spl.c
new file mode 100644
index 0000000000..d57436445e
--- /dev/null
+++ b/board/compulab/cm_t335/spl.c
@@ -0,0 +1,114 @@
+/*
+ * SPL specific code for Compulab CM-T335 board
+ *
+ * Board functions for Compulab CM-T335 board
+ *
+ * Copyright (C) 2013, Compulab Ltd - http://compulab.co.il/
+ *
+ * Author: Ilya Ledvich <ilya@compulab.co.il>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <errno.h>
+
+#include <asm/arch/ddr_defs.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/clocks_am33xx.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/hardware_am33xx.h>
+#include <linux/sizes.h>
+
+const struct ctrl_ioregs ioregs = {
+	.cm0ioctl		= MT41J128MJT125_IOCTRL_VALUE,
+	.cm1ioctl		= MT41J128MJT125_IOCTRL_VALUE,
+	.cm2ioctl		= MT41J128MJT125_IOCTRL_VALUE,
+	.dt0ioctl		= MT41J128MJT125_IOCTRL_VALUE,
+	.dt1ioctl		= MT41J128MJT125_IOCTRL_VALUE,
+};
+
+static const struct ddr_data ddr3_data = {
+	.datardsratio0		= MT41J128MJT125_RD_DQS,
+	.datawdsratio0		= MT41J128MJT125_WR_DQS,
+	.datafwsratio0		= MT41J128MJT125_PHY_FIFO_WE,
+	.datawrsratio0		= MT41J128MJT125_PHY_WR_DATA,
+};
+
+static const struct cmd_control ddr3_cmd_ctrl_data = {
+	.cmd0csratio		= MT41J128MJT125_RATIO,
+	.cmd0iclkout		= MT41J128MJT125_INVERT_CLKOUT,
+
+	.cmd1csratio		= MT41J128MJT125_RATIO,
+	.cmd1iclkout		= MT41J128MJT125_INVERT_CLKOUT,
+
+	.cmd2csratio		= MT41J128MJT125_RATIO,
+	.cmd2iclkout		= MT41J128MJT125_INVERT_CLKOUT,
+};
+
+static struct emif_regs ddr3_emif_reg_data = {
+	.sdram_config		= MT41J128MJT125_EMIF_SDCFG,
+	.ref_ctrl		= MT41J128MJT125_EMIF_SDREF,
+	.sdram_tim1		= MT41J128MJT125_EMIF_TIM1,
+	.sdram_tim2		= MT41J128MJT125_EMIF_TIM2,
+	.sdram_tim3		= MT41J128MJT125_EMIF_TIM3,
+	.zq_config		= MT41J128MJT125_ZQ_CFG,
+	.emif_ddr_phy_ctlr_1	= MT41J128MJT125_EMIF_READ_LATENCY |
+					PHY_EN_DYN_PWRDN,
+};
+
+const struct dpll_params dpll_ddr = {
+/*       M           N            M2  M3  M4  M5  M6 */
+	303, (V_OSCK/1000000) - 1, 1, -1, -1, -1, -1};
+
+void am33xx_spl_board_init(void)
+{
+	struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
+
+	/* Get the frequency */
+	dpll_mpu_opp100.m = am335x_get_efuse_mpu_max_freq(cdev);
+
+	/* Set CORE Frequencies to OPP100 */
+	do_setup_dpll(&dpll_core_regs, &dpll_core_opp100);
+
+	/* Set MPU Frequency to what we detected now that voltages are set */
+	do_setup_dpll(&dpll_mpu_regs, &dpll_mpu_opp100);
+}
+
+const struct dpll_params *get_dpll_ddr_params(void)
+{
+	return &dpll_ddr;
+}
+
+static void probe_sdram_size(long size)
+{
+	switch (size) {
+	case SZ_512M:
+		ddr3_emif_reg_data.sdram_config = MT41J256MJT125_EMIF_SDCFG;
+		break;
+	case SZ_256M:
+		ddr3_emif_reg_data.sdram_config = MT41J128MJT125_EMIF_SDCFG;
+		break;
+	case SZ_128M:
+		ddr3_emif_reg_data.sdram_config = MT41J64MJT125_EMIF_SDCFG;
+		break;
+	default:
+		puts("Failed configuring DRAM, resetting...\n\n");
+		reset_cpu(0);
+	}
+	debug("%s: setting DRAM size to %ldM\n", __func__, size >> 20);
+	config_ddr(303, &ioregs, &ddr3_data,
+		   &ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0);
+}
+
+void sdram_init(void)
+{
+	long size = SZ_1G;
+
+	do {
+		size = size / 2;
+		probe_sdram_size(size);
+	} while (get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, size) < size);
+
+	return;
+}
diff --git a/board/compulab/cm_t335/u-boot.lds b/board/compulab/cm_t335/u-boot.lds
new file mode 100644
index 0000000000..0984dfe6ea
--- /dev/null
+++ b/board/compulab/cm_t335/u-boot.lds
@@ -0,0 +1,110 @@
+/*
+ * Copyright (c) 2004-2008 Texas Instruments
+ *
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+	. = 0x00000000;
+
+	. = ALIGN(4);
+	.text :
+	{
+		*(.__image_copy_start)
+		CPUDIR/start.o (.text*)
+		board/compulab/cm_t335/built-in.o (.text*)
+		*(.text*)
+	}
+
+	. = ALIGN(4);
+	.rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
+
+	. = ALIGN(4);
+	.data : {
+		*(.data*)
+	}
+
+	. = ALIGN(4);
+
+	. = .;
+
+	. = ALIGN(4);
+	.u_boot_list : {
+		KEEP(*(SORT(.u_boot_list*)));
+	}
+
+	. = ALIGN(4);
+
+	.image_copy_end :
+	{
+		*(.__image_copy_end)
+	}
+
+	.rel_dyn_start :
+	{
+		*(.__rel_dyn_start)
+	}
+
+	.rel.dyn : {
+		*(.rel*)
+	}
+
+	.rel_dyn_end :
+	{
+		*(.__rel_dyn_end)
+	}
+
+	.end :
+	{
+		*(.__end)
+	}
+
+	_image_binary_end = .;
+
+	/*
+	 * Deprecated: this MMU section is used by pxa at present but
+	 * should not be used by new boards/CPUs.
+	 */
+	. = ALIGN(4096);
+	.mmutable : {
+		*(.mmutable)
+	}
+
+/*
+ * Compiler-generated __bss_start and __bss_end, see arch/arm/lib/bss.c
+ * __bss_base and __bss_limit are for linker only (overlay ordering)
+ */
+
+	.bss_start __rel_dyn_start (OVERLAY) : {
+		KEEP(*(.__bss_start));
+		__bss_base = .;
+	}
+
+	.bss __bss_base (OVERLAY) : {
+		*(.bss*)
+		 . = ALIGN(4);
+		 __bss_limit = .;
+	}
+
+	.bss_end __bss_limit (OVERLAY) : {
+		KEEP(*(.__bss_end));
+	}
+
+	.dynsym _image_binary_end : { *(.dynsym) }
+	.hash : { *(.hash) }
+	.got.plt : { *(.got.plt) }
+	.dynbss : { *(.dynbss) }
+	.dynstr : { *(.dynstr*) }
+	.dynamic : { *(.dynamic*) }
+	.plt : { *(.plt*) }
+	.interp : { *(.interp*) }
+	.gnu : { *(.gnu*) }
+	.ARM.exidx : { *(.ARM.exidx*) }
+}
diff --git a/board/compulab/cm_t35/Makefile b/board/compulab/cm_t35/Makefile
index 6d07947d51..ede250b524 100644
--- a/board/compulab/cm_t35/Makefile
+++ b/board/compulab/cm_t35/Makefile
@@ -7,26 +7,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS-$(CONFIG_DRIVER_OMAP34XX_I2C) += eeprom.o
-COBJS-$(CONFIG_LCD) += display.o
-
-COBJS	:= cm_t35.o leds.o $(COBJS-y)
-
-SRCS	:= $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	+= cm_t35.o
diff --git a/board/compulab/cm_t35/cm_t35.c b/board/compulab/cm_t35/cm_t35.c
index 3caa5be845..00bcf41bb3 100644
--- a/board/compulab/cm_t35/cm_t35.c
+++ b/board/compulab/cm_t35/cm_t35.c
@@ -33,7 +33,7 @@
 #include <asm/ehci-omap.h>
 #include <asm/gpio.h>
 
-#include "eeprom.h"
+#include "../common/eeprom.h"
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -105,6 +105,22 @@ static inline int splash_load_from_nand(void)
 }
 #endif /* CONFIG_CMD_NAND */
 
+#ifdef CONFIG_SPL_BUILD
+/*
+ * Routine: get_board_mem_timings
+ * Description: If we use SPL then there is no x-loader nor config header
+ * so we have to setup the DDR timings ourself on both banks.
+ */
+void get_board_mem_timings(struct board_sdrc_timings *timings)
+{
+	timings->mr = MICRON_V_MR_165;
+	timings->mcfg = MICRON_V_MCFG_200(256 << 20); /* raswidth 14 needed */
+	timings->ctrla = MICRON_V_ACTIMA_165;
+	timings->ctrlb = MICRON_V_ACTIMB_165;
+	timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
+}
+#endif
+
 int splash_screen_prepare(void)
 {
 	char *env_splashimage_value;
@@ -160,7 +176,7 @@ static u32 cm_t3x_rev;
 u32 get_board_rev(void)
 {
 	if (!cm_t3x_rev)
-		cm_t3x_rev = cm_t3x_eeprom_get_board_rev();
+		cm_t3x_rev = cl_eeprom_get_board_rev();
 
 	return cm_t3x_rev;
 };
@@ -268,6 +284,9 @@ static void cm_t3x_set_common_muxconf(void)
 	/* DVI enable */
 	MUX_VAL(CP(GPMC_NCS3),		(IDIS  | PTU | DIS  | M4));/*GPMC_nCS3*/
 
+	/* DataImage backlight */
+	MUX_VAL(CP(GPMC_NCS7),		(IDIS  | PTU | DIS  | M4));/*GPIO_58*/
+
 	/* CM-T3x Ethernet */
 	MUX_VAL(CP(GPMC_NCS5),		(IDIS | PTU | DIS | M0)); /*GPMC_nCS5*/
 	MUX_VAL(CP(GPMC_CLK),		(IEN  | PTD | DIS | M4)); /*GPIO_59*/
@@ -374,6 +393,15 @@ static void cm_t3x_set_common_muxconf(void)
 	MUX_VAL(CP(MMC1_DAT1),		(IEN  | PTU | EN  | M0)); /*MMC1_DAT1*/
 	MUX_VAL(CP(MMC1_DAT2),		(IEN  | PTU | EN  | M0)); /*MMC1_DAT2*/
 	MUX_VAL(CP(MMC1_DAT3),		(IEN  | PTU | EN  | M0)); /*MMC1_DAT3*/
+
+	/* SPI */
+	MUX_VAL(CP(MCBSP1_CLKR),	(IEN | PTD | DIS | M1)); /*MCSPI4_CLK*/
+	MUX_VAL(CP(MCBSP1_DX),		(IEN | PTD | DIS | M1)); /*MCSPI4_SIMO*/
+	MUX_VAL(CP(MCBSP1_DR),		(IEN | PTD | DIS | M1)); /*MCSPI4_SOMI*/
+	MUX_VAL(CP(MCBSP1_FSX),		(IEN | PTU | EN  | M1)); /*MCSPI4_CS0*/
+
+	/* display controls */
+	MUX_VAL(CP(MCBSP1_FSR),		(IDIS | PTU | DIS | M4)); /*GPIO_157*/
 }
 
 static void cm_t35_set_muxconf(void)
@@ -428,7 +456,7 @@ void set_muxconf_regs(void)
 		cm_t3730_set_muxconf();
 }
 
-#ifdef CONFIG_GENERIC_MMC
+#if defined(CONFIG_GENERIC_MMC) && !defined(CONFIG_SPL_BUILD)
 int board_mmc_getcd(struct mmc *mmc)
 {
 	u8 val;
@@ -470,7 +498,7 @@ static void setup_net_chip_gmpc(void)
 		&ctrl_base->gpmc_nadv_ale);
 }
 
-#ifdef CONFIG_DRIVER_OMAP34XX_I2C
+#ifdef CONFIG_SYS_I2C_OMAP34XX
 /*
  * Routine: reset_net_chip
  * Description: reset the Ethernet controller via TPS65930 GPIO
@@ -509,7 +537,7 @@ static int handle_mac_address(void)
 	if (rc)
 		return 0;
 
-	rc = cm_t3x_eeprom_read_mac_addr(enetaddr);
+	rc = cl_eeprom_read_mac_addr(enetaddr);
 	if (rc)
 		return rc;
 
@@ -565,7 +593,8 @@ struct omap_usbhs_board_data usbhs_bdata = {
 };
 
 #define SB_T35_USB_HUB_RESET_GPIO	167
-int ehci_hcd_init(int index, struct ehci_hccr **hccr, struct ehci_hcor **hcor)
+int ehci_hcd_init(int index, enum usb_init_type init,
+		struct ehci_hccr **hccr, struct ehci_hcor **hcor)
 {
 	u8 val;
 	int offset;
@@ -591,12 +620,11 @@ int ehci_hcd_init(int index, struct ehci_hccr **hccr, struct ehci_hcor **hcor)
 	twl4030_i2c_write_u8(TWL4030_CHIP_GPIO, offset, 0xC0);
 	udelay(1);
 
-	return omap_ehci_hcd_init(&usbhs_bdata, hccr, hcor);
+	return omap_ehci_hcd_init(index, &usbhs_bdata, hccr, hcor);
 }
 
 int ehci_hcd_stop(void)
 {
 	return omap_ehci_hcd_stop();
 }
-
 #endif /* CONFIG_USB_EHCI_OMAP */
diff --git a/board/compulab/cm_t35/display.c b/board/compulab/cm_t35/display.c
deleted file mode 100644
index fae8d95403..0000000000
--- a/board/compulab/cm_t35/display.c
+++ /dev/null
@@ -1,406 +0,0 @@
-/*
- * (C) Copyright 2012 - 2013 CompuLab, Ltd. <www.compulab.co.il>
- *
- * Authors: Nikita Kiryanov <nikita@compulab.co.il>
- *
- * Parsing code based on linux/drivers/video/pxafb.c
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/gpio.h>
-#include <asm/io.h>
-#include <stdio_dev.h>
-#include <asm/arch/dss.h>
-#include <lcd.h>
-#include <asm/arch-omap3/dss.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-enum display_type {
-	NONE,
-	DVI,
-	DVI_CUSTOM,
-};
-
-#define CMAP_ADDR	0x80100000
-
-/*
- * The frame buffer is allocated before we have the chance to parse user input.
- * To make sure enough memory is allocated for all resolutions, we define
- * vl_{col | row} to the maximal resolution supported by OMAP3.
- */
-vidinfo_t panel_info = {
-	.vl_col  = 1400,
-	.vl_row  = 1050,
-	.vl_bpix = LCD_BPP,
-	.cmap = (ushort *)CMAP_ADDR,
-};
-
-static struct panel_config panel_cfg;
-static enum display_type lcd_def;
-
-/*
- * A note on DVI presets;
- * U-Boot can convert 8 bit BMP data to 16 bit BMP data, and OMAP DSS can
- * convert 16 bit data into 24 bit data. Thus, GFXFORMAT_RGB16 allows us to
- * support two BMP types with one setting.
- */
-static const struct panel_config preset_dvi_640X480 = {
-	.lcd_size	= PANEL_LCD_SIZE(640, 480),
-	.timing_h	= DSS_HBP(48) | DSS_HFP(16) | DSS_HSW(96),
-	.timing_v	= DSS_VBP(33) | DSS_VFP(10) | DSS_VSW(2),
-	.divisor	= 12 | (1 << 16),
-	.data_lines	= LCD_INTERFACE_24_BIT,
-	.panel_type	= ACTIVE_DISPLAY,
-	.load_mode	= 2,
-	.gfx_format	= GFXFORMAT_RGB16,
-};
-
-static const struct panel_config preset_dvi_800X600 = {
-	.lcd_size	= PANEL_LCD_SIZE(800, 600),
-	.timing_h	= DSS_HBP(88) | DSS_HFP(40) | DSS_HSW(128),
-	.timing_v	= DSS_VBP(23) | DSS_VFP(1) | DSS_VSW(4),
-	.divisor	= 8 | (1 << 16),
-	.data_lines	= LCD_INTERFACE_24_BIT,
-	.panel_type	= ACTIVE_DISPLAY,
-	.load_mode	= 2,
-	.gfx_format	= GFXFORMAT_RGB16,
-};
-
-static const struct panel_config preset_dvi_1024X768 = {
-	.lcd_size	= PANEL_LCD_SIZE(1024, 768),
-	.timing_h	= DSS_HBP(160) | DSS_HFP(24) | DSS_HSW(136),
-	.timing_v	= DSS_VBP(29) | DSS_VFP(3) | DSS_VSW(6),
-	.divisor	= 5 | (1 << 16),
-	.data_lines	= LCD_INTERFACE_24_BIT,
-	.panel_type	= ACTIVE_DISPLAY,
-	.load_mode	= 2,
-	.gfx_format	= GFXFORMAT_RGB16,
-};
-
-static const struct panel_config preset_dvi_1152X864 = {
-	.lcd_size	= PANEL_LCD_SIZE(1152, 864),
-	.timing_h	= DSS_HBP(256) | DSS_HFP(64) | DSS_HSW(128),
-	.timing_v	= DSS_VBP(32) | DSS_VFP(1) | DSS_VSW(3),
-	.divisor	= 3 | (1 << 16),
-	.data_lines	= LCD_INTERFACE_24_BIT,
-	.panel_type	= ACTIVE_DISPLAY,
-	.load_mode	= 2,
-	.gfx_format	= GFXFORMAT_RGB16,
-};
-
-static const struct panel_config preset_dvi_1280X960 = {
-	.lcd_size	= PANEL_LCD_SIZE(1280, 960),
-	.timing_h	= DSS_HBP(312) | DSS_HFP(96) | DSS_HSW(112),
-	.timing_v	= DSS_VBP(36) | DSS_VFP(1) | DSS_VSW(3),
-	.divisor	= 3 | (1 << 16),
-	.data_lines	= LCD_INTERFACE_24_BIT,
-	.panel_type	= ACTIVE_DISPLAY,
-	.load_mode	= 2,
-	.gfx_format	= GFXFORMAT_RGB16,
-};
-
-static const struct panel_config preset_dvi_1280X1024 = {
-	.lcd_size	= PANEL_LCD_SIZE(1280, 1024),
-	.timing_h	= DSS_HBP(248) | DSS_HFP(48) | DSS_HSW(112),
-	.timing_v	= DSS_VBP(38) | DSS_VFP(1) | DSS_VSW(3),
-	.divisor	= 3 | (1 << 16),
-	.data_lines	= LCD_INTERFACE_24_BIT,
-	.panel_type	= ACTIVE_DISPLAY,
-	.load_mode	= 2,
-	.gfx_format	= GFXFORMAT_RGB16,
-};
-
-/*
- * set_resolution_params()
- *
- * Due to usage of multiple display related APIs resolution data is located in
- * more than one place. This function updates them all.
- */
-static void set_resolution_params(int x, int y)
-{
-	panel_cfg.lcd_size = PANEL_LCD_SIZE(x, y);
-	panel_info.vl_col = x;
-	panel_info.vl_row = y;
-	lcd_line_length = (panel_info.vl_col * NBITS(panel_info.vl_bpix)) / 8;
-}
-
-static void set_preset(const struct panel_config preset, int x_res, int y_res)
-{
-	panel_cfg = preset;
-	set_resolution_params(x_res, y_res);
-}
-
-static enum display_type set_dvi_preset(const struct panel_config preset,
-					int x_res, int y_res)
-{
-	set_preset(preset, x_res, y_res);
-	return DVI;
-}
-
-/*
- * parse_mode() - parse the mode parameter of custom lcd settings
- *
- * @mode:	<res_x>x<res_y>
- *
- * Returns -1 on error, 0 on success.
- */
-static int parse_mode(const char *mode)
-{
-	unsigned int modelen = strlen(mode);
-	int res_specified = 0;
-	unsigned int xres = 0, yres = 0;
-	int yres_specified = 0;
-	int i;
-
-	for (i = modelen - 1; i >= 0; i--) {
-		switch (mode[i]) {
-		case 'x':
-			if (!yres_specified) {
-				yres = simple_strtoul(&mode[i + 1], NULL, 0);
-				yres_specified = 1;
-			} else {
-				goto done_parsing;
-			}
-
-			break;
-		case '0' ... '9':
-			break;
-		default:
-			goto done_parsing;
-		}
-	}
-
-	if (i < 0 && yres_specified) {
-		xres = simple_strtoul(mode, NULL, 0);
-		res_specified = 1;
-	}
-
-done_parsing:
-	if (res_specified) {
-		set_resolution_params(xres, yres);
-	} else {
-		printf("LCD: invalid mode: %s\n", mode);
-		return -1;
-	}
-
-	return 0;
-}
-
-#define PIXEL_CLK_NUMERATOR (26 * 432 / 39)
-/*
- * parse_pixclock() - Parse the pixclock parameter of custom lcd settings
- *
- * @pixclock:	the desired pixel clock
- *
- * Returns -1 on error, 0 on success.
- *
- * Handling the pixel_clock:
- *
- * Pixel clock is defined in the OMAP35x TRM as follows:
- * pixel_clock =
- * (SYS_CLK * 2 * PRCM.CM_CLKSEL2_PLL[18:8]) /
- * (DSS.DISPC_DIVISOR[23:16] * DSS.DISPC_DIVISOR[6:0] *
- * PRCM.CM_CLKSEL_DSS[4:0] * (PRCM.CM_CLKSEL2_PLL[6:0] + 1))
- *
- * In practice, this means that in order to set the
- * divisor for the desired pixel clock one needs to
- * solve the following equation:
- *
- * 26 * 432 / (39 * <pixel_clock>) = DSS.DISPC_DIVISOR[6:0]
- *
- * NOTE: the explicit equation above is reduced. Do not
- * try to infer anything from these numbers.
- */
-static int parse_pixclock(char *pixclock)
-{
-	int divisor, pixclock_val;
-	char *pixclk_start = pixclock;
-
-	pixclock_val = simple_strtoul(pixclock, &pixclock, 10);
-	divisor = DIV_ROUND_UP(PIXEL_CLK_NUMERATOR, pixclock_val);
-	/* 0 and 1 are illegal values for PCD */
-	if (divisor <= 1)
-		divisor = 2;
-
-	panel_cfg.divisor = divisor | (1 << 16);
-	if (pixclock[0] != '\0') {
-		printf("LCD: invalid value for pixclock:%s\n", pixclk_start);
-		return -1;
-	}
-
-	return 0;
-}
-
-/*
- * parse_setting() - parse a single setting of custom lcd parameters
- *
- * @setting:	The custom lcd setting <name>:<value>
- *
- * Returns -1 on failure, 0 on success.
- */
-static int parse_setting(char *setting)
-{
-	int num_val;
-	char *setting_start = setting;
-
-	if (!strncmp(setting, "mode:", 5)) {
-		return parse_mode(setting + 5);
-	} else if (!strncmp(setting, "pixclock:", 9)) {
-		return parse_pixclock(setting + 9);
-	} else if (!strncmp(setting, "left:", 5)) {
-		num_val = simple_strtoul(setting + 5, &setting, 0);
-		panel_cfg.timing_h |= DSS_HBP(num_val);
-	} else if (!strncmp(setting, "right:", 6)) {
-		num_val = simple_strtoul(setting + 6, &setting, 0);
-		panel_cfg.timing_h |= DSS_HFP(num_val);
-	} else if (!strncmp(setting, "upper:", 6)) {
-		num_val = simple_strtoul(setting + 6, &setting, 0);
-		panel_cfg.timing_v |= DSS_VBP(num_val);
-	} else if (!strncmp(setting, "lower:", 6)) {
-		num_val = simple_strtoul(setting + 6, &setting, 0);
-		panel_cfg.timing_v |= DSS_VFP(num_val);
-	} else if (!strncmp(setting, "hsynclen:", 9)) {
-		num_val = simple_strtoul(setting + 9, &setting, 0);
-		panel_cfg.timing_h |= DSS_HSW(num_val);
-	} else if (!strncmp(setting, "vsynclen:", 9)) {
-		num_val = simple_strtoul(setting + 9, &setting, 0);
-		panel_cfg.timing_v |= DSS_VSW(num_val);
-	} else if (!strncmp(setting, "hsync:", 6)) {
-		if (simple_strtoul(setting + 6, &setting, 0) == 0)
-			panel_cfg.pol_freq |= DSS_IHS;
-		else
-			panel_cfg.pol_freq &= ~DSS_IHS;
-	} else if (!strncmp(setting, "vsync:", 6)) {
-		if (simple_strtoul(setting + 6, &setting, 0) == 0)
-			panel_cfg.pol_freq |= DSS_IVS;
-		else
-			panel_cfg.pol_freq &= ~DSS_IVS;
-	} else if (!strncmp(setting, "outputen:", 9)) {
-		if (simple_strtoul(setting + 9, &setting, 0) == 0)
-			panel_cfg.pol_freq |= DSS_IEO;
-		else
-			panel_cfg.pol_freq &= ~DSS_IEO;
-	} else if (!strncmp(setting, "pixclockpol:", 12)) {
-		if (simple_strtoul(setting + 12, &setting, 0) == 0)
-			panel_cfg.pol_freq |= DSS_IPC;
-		else
-			panel_cfg.pol_freq &= ~DSS_IPC;
-	} else if (!strncmp(setting, "active", 6)) {
-		panel_cfg.panel_type = ACTIVE_DISPLAY;
-		return 0; /* Avoid sanity check below */
-	} else if (!strncmp(setting, "passive", 7)) {
-		panel_cfg.panel_type = PASSIVE_DISPLAY;
-		return 0; /* Avoid sanity check below */
-	} else if (!strncmp(setting, "display:", 8)) {
-		if (!strncmp(setting + 8, "dvi", 3)) {
-			lcd_def = DVI_CUSTOM;
-			return 0; /* Avoid sanity check below */
-		}
-	} else {
-		printf("LCD: unknown option %s\n", setting_start);
-		return -1;
-	}
-
-	if (setting[0] != '\0') {
-		printf("LCD: invalid value for %s\n", setting_start);
-		return -1;
-	}
-
-	return 0;
-}
-
-/*
- * env_parse_customlcd() - parse custom lcd params from an environment variable.
- *
- * @custom_lcd_params:	The environment variable containing the lcd params.
- *
- * Returns -1 on failure, 0 on success.
- */
-static int parse_customlcd(char *custom_lcd_params)
-{
-	char params_cpy[160];
-	char *setting;
-
-	strncpy(params_cpy, custom_lcd_params, 160);
-	setting = strtok(params_cpy, ",");
-	while (setting) {
-		if (parse_setting(setting) < 0)
-			return -1;
-
-		setting = strtok(NULL, ",");
-	}
-
-	/* Currently we don't support changing this via custom lcd params */
-	panel_cfg.data_lines = LCD_INTERFACE_24_BIT;
-	panel_cfg.gfx_format = GFXFORMAT_RGB16; /* See dvi predefines note */
-
-	return 0;
-}
-
-/*
- * env_parse_displaytype() - parse display type.
- *
- * Parses the environment variable "displaytype", which contains the
- * name of the display type or preset, in which case it applies its
- * configurations.
- *
- * Returns the type of display that was specified.
- */
-static enum display_type env_parse_displaytype(char *displaytype)
-{
-	if (!strncmp(displaytype, "dvi640x480", 10))
-		return set_dvi_preset(preset_dvi_640X480, 640, 480);
-	else if (!strncmp(displaytype, "dvi800x600", 10))
-		return set_dvi_preset(preset_dvi_800X600, 800, 600);
-	else if (!strncmp(displaytype, "dvi1024x768", 11))
-		return set_dvi_preset(preset_dvi_1024X768, 1024, 768);
-	else if (!strncmp(displaytype, "dvi1152x864", 11))
-		return set_dvi_preset(preset_dvi_1152X864, 1152, 864);
-	else if (!strncmp(displaytype, "dvi1280x960", 11))
-		return set_dvi_preset(preset_dvi_1280X960, 1280, 960);
-	else if (!strncmp(displaytype, "dvi1280x1024", 12))
-		return set_dvi_preset(preset_dvi_1280X1024, 1280, 1024);
-
-	return NONE;
-}
-
-void lcd_ctrl_init(void *lcdbase)
-{
-	struct prcm *prcm = (struct prcm *)PRCM_BASE;
-	char *custom_lcd;
-	char *displaytype = getenv("displaytype");
-
-	if (displaytype == NULL)
-		return;
-
-	lcd_def = env_parse_displaytype(displaytype);
-	/* If we did not recognize the preset, check if it's an env variable */
-	if (lcd_def == NONE) {
-		custom_lcd = getenv(displaytype);
-		if (custom_lcd == NULL || parse_customlcd(custom_lcd) < 0)
-			return;
-	}
-
-	panel_cfg.frame_buffer = lcdbase;
-	omap3_dss_panel_config(&panel_cfg);
-	/*
-	 * Pixel clock is defined with many divisions and only few
-	 * multiplications of the system clock. Since DSS FCLK divisor is set
-	 * to 16 by default, we need to set it to a smaller value, like 3
-	 * (chosen via trial and error).
-	 */
-	clrsetbits_le32(&prcm->clksel_dss, 0xF, 3);
-}
-
-void lcd_enable(void)
-{
-	if (lcd_def == DVI || lcd_def == DVI_CUSTOM) {
-		gpio_direction_output(54, 0); /* Turn on DVI */
-		omap3_dss_enable();
-	}
-}
-
-void lcd_setcolreg(ushort regno, ushort red, ushort green, ushort blue) {}
diff --git a/board/compulab/cm_t35/eeprom.c b/board/compulab/cm_t35/eeprom.c
deleted file mode 100644
index df91acd4a7..0000000000
--- a/board/compulab/cm_t35/eeprom.c
+++ /dev/null
@@ -1,118 +0,0 @@
-/*
- * (C) Copyright 2011 CompuLab, Ltd. <www.compulab.co.il>
- *
- * Authors: Nikita Kiryanov <nikita@compulab.co.il>
- *	    Igor Grinberg <grinberg@compulab.co.il>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <i2c.h>
-
-#define EEPROM_LAYOUT_VER_OFFSET	44
-#define BOARD_SERIAL_OFFSET		20
-#define BOARD_SERIAL_OFFSET_LEGACY	8
-#define BOARD_REV_OFFSET		0
-#define BOARD_REV_OFFSET_LEGACY		6
-#define BOARD_REV_SIZE			2
-#define MAC_ADDR_OFFSET			4
-#define MAC_ADDR_OFFSET_LEGACY		0
-
-#define LAYOUT_INVALID	0
-#define LAYOUT_LEGACY	0xff
-
-static int eeprom_layout; /* Implicitly LAYOUT_INVALID */
-
-static int cm_t3x_eeprom_read(uint offset, uchar *buf, int len)
-{
-	return i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, offset,
-			CONFIG_SYS_I2C_EEPROM_ADDR_LEN, buf, len);
-}
-
-static int eeprom_setup_layout(void)
-{
-	int res;
-
-	if (eeprom_layout != LAYOUT_INVALID)
-		return 0;
-
-	res = cm_t3x_eeprom_read(EEPROM_LAYOUT_VER_OFFSET,
-						(uchar *)&eeprom_layout, 1);
-	if (res) {
-		eeprom_layout = LAYOUT_INVALID;
-		return res;
-	}
-
-	if (eeprom_layout == 0 || eeprom_layout >= 0x20)
-		eeprom_layout = LAYOUT_LEGACY;
-
-	return 0;
-}
-
-void get_board_serial(struct tag_serialnr *serialnr)
-{
-	u32 serial[2];
-	uint offset;
-
-	memset(serialnr, 0, sizeof(*serialnr));
-	if (eeprom_setup_layout())
-		return;
-
-	offset = (eeprom_layout != LAYOUT_LEGACY) ?
-			BOARD_SERIAL_OFFSET : BOARD_SERIAL_OFFSET_LEGACY;
-	if (cm_t3x_eeprom_read(offset, (uchar *)serial, 8))
-		return;
-
-	if (serial[0] != 0xffffffff && serial[1] != 0xffffffff) {
-		serialnr->low = serial[0];
-		serialnr->high = serial[1];
-	}
-}
-
-/*
- * Routine: cm_t3x_eeprom_read_mac_addr
- * Description: read mac address and store it in buf.
- */
-int cm_t3x_eeprom_read_mac_addr(uchar *buf)
-{
-	uint offset;
-
-	if (eeprom_setup_layout())
-		return 0;
-
-	offset = (eeprom_layout != LAYOUT_LEGACY) ?
-			MAC_ADDR_OFFSET : MAC_ADDR_OFFSET_LEGACY;
-	return cm_t3x_eeprom_read(offset, buf, 6);
-}
-
-/*
- * Routine: cm_t3x_eeprom_get_board_rev
- * Description: read system revision from eeprom
- */
-u32 cm_t3x_eeprom_get_board_rev(void)
-{
-	u32 rev = 0;
-	char str[5]; /* Legacy representation can contain at most 4 digits */
-	uint offset = BOARD_REV_OFFSET_LEGACY;
-
-	if (eeprom_setup_layout())
-		return 0;
-
-	if (eeprom_layout != LAYOUT_LEGACY)
-		offset = BOARD_REV_OFFSET;
-
-	if (cm_t3x_eeprom_read(offset, (uchar *)&rev, BOARD_REV_SIZE))
-		return 0;
-
-	/*
-	 * Convert legacy syntactic representation to semantic
-	 * representation. i.e. for rev 1.00: 0x100 --> 0x64
-	 */
-	if (eeprom_layout == LAYOUT_LEGACY) {
-		sprintf(str, "%x", rev);
-		rev = simple_strtoul(str, NULL, 10);
-	}
-
-	return rev;
-};
diff --git a/board/compulab/cm_t35/eeprom.h b/board/compulab/cm_t35/eeprom.h
deleted file mode 100644
index 02ffbb1a99..0000000000
--- a/board/compulab/cm_t35/eeprom.h
+++ /dev/null
@@ -1,27 +0,0 @@
-/*
- * (C) Copyright 2011 CompuLab, Ltd. <www.compulab.co.il>
- *
- * Authors: Nikita Kiryanov <nikita@compulab.co.il>
- *	    Igor Grinberg <grinberg@compulab.co.il>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef _EEPROM_
-#define _EEPROM_
-
-#ifdef CONFIG_DRIVER_OMAP34XX_I2C
-int cm_t3x_eeprom_read_mac_addr(uchar *buf);
-u32 cm_t3x_eeprom_get_board_rev(void);
-#else
-static inline int cm_t3x_eeprom_read_mac_addr(uchar *buf)
-{
-	return 1;
-}
-static inline u32 cm_t3x_eeprom_get_board_rev(void)
-{
-	return 0;
-}
-#endif
-
-#endif
diff --git a/board/compulab/cm_t35/leds.c b/board/compulab/cm_t35/leds.c
deleted file mode 100644
index 7e2803e3b8..0000000000
--- a/board/compulab/cm_t35/leds.c
+++ /dev/null
@@ -1,33 +0,0 @@
-/*
- * (C) Copyright 2011 - 2013 CompuLab, Ltd. <www.compulab.co.il>
- *
- * Author: Igor Grinberg <grinberg@compulab.co.il>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <status_led.h>
-#include <asm/gpio.h>
-
-static unsigned int leds[] = { GREEN_LED_GPIO };
-
-void __led_init(led_id_t mask, int state)
-{
-	if (gpio_request(leds[mask], "") != 0) {
-		printf("%s: failed requesting GPIO%u\n", __func__, leds[mask]);
-		return;
-	}
-
-	gpio_direction_output(leds[mask], 0);
-}
-
-void __led_set(led_id_t mask, int state)
-{
-	gpio_set_value(leds[mask], state == STATUS_LED_ON);
-}
-
-void __led_toggle(led_id_t mask)
-{
-	gpio_set_value(leds[mask], !gpio_get_value(leds[mask]));
-}
diff --git a/board/compulab/common/Makefile b/board/compulab/common/Makefile
new file mode 100644
index 0000000000..6d7d06815c
--- /dev/null
+++ b/board/compulab/common/Makefile
@@ -0,0 +1,10 @@
+#
+# (C) Copyright 2011 - 2013 CompuLab, Ltd. <www.compulab.co.il>
+#
+# Author: Igor Grinberg <grinberg@compulab.co.il>
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-$(CONFIG_SYS_I2C_OMAP34XX) += eeprom.o
+obj-$(CONFIG_LCD) += omap3_display.o
diff --git a/board/compulab/common/eeprom.c b/board/compulab/common/eeprom.c
new file mode 100644
index 0000000000..5aa3dbd295
--- /dev/null
+++ b/board/compulab/common/eeprom.c
@@ -0,0 +1,121 @@
+/*
+ * (C) Copyright 2011 CompuLab, Ltd. <www.compulab.co.il>
+ *
+ * Authors: Nikita Kiryanov <nikita@compulab.co.il>
+ *	    Igor Grinberg <grinberg@compulab.co.il>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <i2c.h>
+
+#define EEPROM_LAYOUT_VER_OFFSET	44
+#define BOARD_SERIAL_OFFSET		20
+#define BOARD_SERIAL_OFFSET_LEGACY	8
+#define BOARD_REV_OFFSET		0
+#define BOARD_REV_OFFSET_LEGACY		6
+#define BOARD_REV_SIZE			2
+#define MAC_ADDR_OFFSET			4
+#define MAC_ADDR_OFFSET_LEGACY		0
+
+#define LAYOUT_INVALID	0
+#define LAYOUT_LEGACY	0xff
+
+static int cl_eeprom_layout; /* Implicitly LAYOUT_INVALID */
+
+static int cl_eeprom_read(uint offset, uchar *buf, int len)
+{
+	return i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, offset,
+			CONFIG_SYS_I2C_EEPROM_ADDR_LEN, buf, len);
+}
+
+static int cl_eeprom_setup_layout(void)
+{
+	int res;
+
+	if (cl_eeprom_layout != LAYOUT_INVALID)
+		return 0;
+
+	res = cl_eeprom_read(EEPROM_LAYOUT_VER_OFFSET,
+			     (uchar *)&cl_eeprom_layout, 1);
+	if (res) {
+		cl_eeprom_layout = LAYOUT_INVALID;
+		return res;
+	}
+
+	if (cl_eeprom_layout == 0 || cl_eeprom_layout >= 0x20)
+		cl_eeprom_layout = LAYOUT_LEGACY;
+
+	return 0;
+}
+
+void get_board_serial(struct tag_serialnr *serialnr)
+{
+	u32 serial[2];
+	uint offset;
+
+	memset(serialnr, 0, sizeof(*serialnr));
+
+	if (cl_eeprom_setup_layout())
+		return;
+
+	offset = (cl_eeprom_layout != LAYOUT_LEGACY) ?
+		BOARD_SERIAL_OFFSET : BOARD_SERIAL_OFFSET_LEGACY;
+
+	if (cl_eeprom_read(offset, (uchar *)serial, 8))
+		return;
+
+	if (serial[0] != 0xffffffff && serial[1] != 0xffffffff) {
+		serialnr->low = serial[0];
+		serialnr->high = serial[1];
+	}
+}
+
+/*
+ * Routine: cl_eeprom_read_mac_addr
+ * Description: read mac address and store it in buf.
+ */
+int cl_eeprom_read_mac_addr(uchar *buf)
+{
+	uint offset;
+
+	if (cl_eeprom_setup_layout())
+		return 0;
+
+	offset = (cl_eeprom_layout != LAYOUT_LEGACY) ?
+			MAC_ADDR_OFFSET : MAC_ADDR_OFFSET_LEGACY;
+
+	return cl_eeprom_read(offset, buf, 6);
+}
+
+/*
+ * Routine: cl_eeprom_get_board_rev
+ * Description: read system revision from eeprom
+ */
+u32 cl_eeprom_get_board_rev(void)
+{
+	u32 rev = 0;
+	char str[5]; /* Legacy representation can contain at most 4 digits */
+	uint offset = BOARD_REV_OFFSET_LEGACY;
+
+	if (cl_eeprom_setup_layout())
+		return 0;
+
+	if (cl_eeprom_layout != LAYOUT_LEGACY)
+		offset = BOARD_REV_OFFSET;
+
+	if (cl_eeprom_read(offset, (uchar *)&rev, BOARD_REV_SIZE))
+		return 0;
+
+	/*
+	 * Convert legacy syntactic representation to semantic
+	 * representation. i.e. for rev 1.00: 0x100 --> 0x64
+	 */
+	if (cl_eeprom_layout == LAYOUT_LEGACY) {
+		sprintf(str, "%x", rev);
+		rev = simple_strtoul(str, NULL, 10);
+	}
+
+	return rev;
+};
diff --git a/board/compulab/common/eeprom.h b/board/compulab/common/eeprom.h
new file mode 100644
index 0000000000..e87162930d
--- /dev/null
+++ b/board/compulab/common/eeprom.h
@@ -0,0 +1,27 @@
+/*
+ * (C) Copyright 2011 CompuLab, Ltd. <www.compulab.co.il>
+ *
+ * Authors: Nikita Kiryanov <nikita@compulab.co.il>
+ *	    Igor Grinberg <grinberg@compulab.co.il>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _EEPROM_
+#define _EEPROM_
+
+#ifdef CONFIG_SYS_I2C_OMAP34XX
+int cl_eeprom_read_mac_addr(uchar *buf);
+u32 cl_eeprom_get_board_rev(void);
+#else
+static inline int cl_eeprom_read_mac_addr(uchar *buf)
+{
+	return 1;
+}
+static inline u32 cl_eeprom_get_board_rev(void)
+{
+	return 0;
+}
+#endif
+
+#endif
diff --git a/board/compulab/common/omap3_display.c b/board/compulab/common/omap3_display.c
new file mode 100644
index 0000000000..61707f5b90
--- /dev/null
+++ b/board/compulab/common/omap3_display.c
@@ -0,0 +1,454 @@
+/*
+ * (C) Copyright 2012 - 2013 CompuLab, Ltd. <www.compulab.co.il>
+ *
+ * Authors: Nikita Kiryanov <nikita@compulab.co.il>
+ *
+ * Parsing code based on linux/drivers/video/pxafb.c
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/gpio.h>
+#include <asm/io.h>
+#include <stdio_dev.h>
+#include <asm/arch/dss.h>
+#include <lcd.h>
+#include <scf0403_lcd.h>
+#include <asm/arch-omap3/dss.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+enum display_type {
+	NONE,
+	DVI,
+	DVI_CUSTOM,
+	DATA_IMAGE, /* #define CONFIG_SCF0403_LCD to use */
+};
+
+#define CMAP_ADDR	0x80100000
+
+/*
+ * The frame buffer is allocated before we have the chance to parse user input.
+ * To make sure enough memory is allocated for all resolutions, we define
+ * vl_{col | row} to the maximal resolution supported by OMAP3.
+ */
+vidinfo_t panel_info = {
+	.vl_col  = 1400,
+	.vl_row  = 1050,
+	.vl_bpix = LCD_BPP,
+	.cmap = (ushort *)CMAP_ADDR,
+};
+
+static struct panel_config panel_cfg;
+static enum display_type lcd_def;
+
+/*
+ * A note on DVI presets;
+ * U-Boot can convert 8 bit BMP data to 16 bit BMP data, and OMAP DSS can
+ * convert 16 bit data into 24 bit data. Thus, GFXFORMAT_RGB16 allows us to
+ * support two BMP types with one setting.
+ */
+static const struct panel_config preset_dvi_640X480 = {
+	.lcd_size	= PANEL_LCD_SIZE(640, 480),
+	.timing_h	= DSS_HBP(48) | DSS_HFP(16) | DSS_HSW(96),
+	.timing_v	= DSS_VBP(33) | DSS_VFP(10) | DSS_VSW(2),
+	.pol_freq	= DSS_IHS | DSS_IVS | DSS_IPC,
+	.divisor	= 12 | (1 << 16),
+	.data_lines	= LCD_INTERFACE_24_BIT,
+	.panel_type	= ACTIVE_DISPLAY,
+	.load_mode	= 2,
+	.gfx_format	= GFXFORMAT_RGB16,
+};
+
+static const struct panel_config preset_dvi_800X600 = {
+	.lcd_size	= PANEL_LCD_SIZE(800, 600),
+	.timing_h	= DSS_HBP(88) | DSS_HFP(40) | DSS_HSW(128),
+	.timing_v	= DSS_VBP(23) | DSS_VFP(1) | DSS_VSW(4),
+	.pol_freq	= DSS_IHS | DSS_IVS | DSS_IPC,
+	.divisor	= 8 | (1 << 16),
+	.data_lines	= LCD_INTERFACE_24_BIT,
+	.panel_type	= ACTIVE_DISPLAY,
+	.load_mode	= 2,
+	.gfx_format	= GFXFORMAT_RGB16,
+};
+
+static const struct panel_config preset_dvi_1024X768 = {
+	.lcd_size	= PANEL_LCD_SIZE(1024, 768),
+	.timing_h	= DSS_HBP(160) | DSS_HFP(24) | DSS_HSW(136),
+	.timing_v	= DSS_VBP(29) | DSS_VFP(3) | DSS_VSW(6),
+	.pol_freq	= DSS_IHS | DSS_IVS | DSS_IPC,
+	.divisor	= 5 | (1 << 16),
+	.data_lines	= LCD_INTERFACE_24_BIT,
+	.panel_type	= ACTIVE_DISPLAY,
+	.load_mode	= 2,
+	.gfx_format	= GFXFORMAT_RGB16,
+};
+
+static const struct panel_config preset_dvi_1152X864 = {
+	.lcd_size	= PANEL_LCD_SIZE(1152, 864),
+	.timing_h	= DSS_HBP(256) | DSS_HFP(64) | DSS_HSW(128),
+	.timing_v	= DSS_VBP(32) | DSS_VFP(1) | DSS_VSW(3),
+	.pol_freq	= DSS_IHS | DSS_IVS | DSS_IPC,
+	.divisor	= 4 | (1 << 16),
+	.data_lines	= LCD_INTERFACE_24_BIT,
+	.panel_type	= ACTIVE_DISPLAY,
+	.load_mode	= 2,
+	.gfx_format	= GFXFORMAT_RGB16,
+};
+
+static const struct panel_config preset_dvi_1280X960 = {
+	.lcd_size	= PANEL_LCD_SIZE(1280, 960),
+	.timing_h	= DSS_HBP(312) | DSS_HFP(96) | DSS_HSW(112),
+	.timing_v	= DSS_VBP(36) | DSS_VFP(1) | DSS_VSW(3),
+	.pol_freq	= DSS_IHS | DSS_IVS | DSS_IPC,
+	.divisor	= 3 | (1 << 16),
+	.data_lines	= LCD_INTERFACE_24_BIT,
+	.panel_type	= ACTIVE_DISPLAY,
+	.load_mode	= 2,
+	.gfx_format	= GFXFORMAT_RGB16,
+};
+
+static const struct panel_config preset_dvi_1280X1024 = {
+	.lcd_size	= PANEL_LCD_SIZE(1280, 1024),
+	.timing_h	= DSS_HBP(248) | DSS_HFP(48) | DSS_HSW(112),
+	.timing_v	= DSS_VBP(38) | DSS_VFP(1) | DSS_VSW(3),
+	.pol_freq	= DSS_IHS | DSS_IVS | DSS_IPC,
+	.divisor	= 3 | (1 << 16),
+	.data_lines	= LCD_INTERFACE_24_BIT,
+	.panel_type	= ACTIVE_DISPLAY,
+	.load_mode	= 2,
+	.gfx_format	= GFXFORMAT_RGB16,
+};
+
+static const struct panel_config preset_dataimage_480X800 = {
+	.lcd_size	= PANEL_LCD_SIZE(480, 800),
+	.timing_h	= DSS_HBP(2) | DSS_HFP(2) | DSS_HSW(2),
+	.timing_v	= DSS_VBP(17) | DSS_VFP(20) | DSS_VSW(3),
+	.pol_freq	= DSS_IVS | DSS_IHS | DSS_IPC | DSS_ONOFF,
+	.divisor	= 10 | (1 << 10),
+	.data_lines	= LCD_INTERFACE_18_BIT,
+	.panel_type	= ACTIVE_DISPLAY,
+	.load_mode	= 2,
+	.gfx_format	= GFXFORMAT_RGB16,
+};
+
+/*
+ * set_resolution_params()
+ *
+ * Due to usage of multiple display related APIs resolution data is located in
+ * more than one place. This function updates them all.
+ */
+static void set_resolution_params(int x, int y)
+{
+	panel_cfg.lcd_size = PANEL_LCD_SIZE(x, y);
+	panel_info.vl_col = x;
+	panel_info.vl_row = y;
+	lcd_line_length = (panel_info.vl_col * NBITS(panel_info.vl_bpix)) / 8;
+}
+
+static void set_preset(const struct panel_config preset, int x_res, int y_res)
+{
+	panel_cfg = preset;
+	set_resolution_params(x_res, y_res);
+}
+
+static enum display_type set_dvi_preset(const struct panel_config preset,
+					int x_res, int y_res)
+{
+	set_preset(preset, x_res, y_res);
+	return DVI;
+}
+
+static enum display_type set_dataimage_preset(const struct panel_config preset,
+		int x_res, int y_res)
+{
+	set_preset(preset, x_res, y_res);
+	return DATA_IMAGE;
+}
+
+/*
+ * parse_mode() - parse the mode parameter of custom lcd settings
+ *
+ * @mode:	<res_x>x<res_y>
+ *
+ * Returns -1 on error, 0 on success.
+ */
+static int parse_mode(const char *mode)
+{
+	unsigned int modelen = strlen(mode);
+	int res_specified = 0;
+	unsigned int xres = 0, yres = 0;
+	int yres_specified = 0;
+	int i;
+
+	for (i = modelen - 1; i >= 0; i--) {
+		switch (mode[i]) {
+		case 'x':
+			if (!yres_specified) {
+				yres = simple_strtoul(&mode[i + 1], NULL, 0);
+				yres_specified = 1;
+			} else {
+				goto done_parsing;
+			}
+
+			break;
+		case '0' ... '9':
+			break;
+		default:
+			goto done_parsing;
+		}
+	}
+
+	if (i < 0 && yres_specified) {
+		xres = simple_strtoul(mode, NULL, 0);
+		res_specified = 1;
+	}
+
+done_parsing:
+	if (res_specified) {
+		set_resolution_params(xres, yres);
+	} else {
+		printf("LCD: invalid mode: %s\n", mode);
+		return -1;
+	}
+
+	return 0;
+}
+
+#define PIXEL_CLK_NUMERATOR (26 * 432 / 39)
+/*
+ * parse_pixclock() - Parse the pixclock parameter of custom lcd settings
+ *
+ * @pixclock:	the desired pixel clock
+ *
+ * Returns -1 on error, 0 on success.
+ *
+ * Handling the pixel_clock:
+ *
+ * Pixel clock is defined in the OMAP35x TRM as follows:
+ * pixel_clock =
+ * (SYS_CLK * 2 * PRCM.CM_CLKSEL2_PLL[18:8]) /
+ * (DSS.DISPC_DIVISOR[23:16] * DSS.DISPC_DIVISOR[6:0] *
+ * PRCM.CM_CLKSEL_DSS[4:0] * (PRCM.CM_CLKSEL2_PLL[6:0] + 1))
+ *
+ * In practice, this means that in order to set the
+ * divisor for the desired pixel clock one needs to
+ * solve the following equation:
+ *
+ * 26 * 432 / (39 * <pixel_clock>) = DSS.DISPC_DIVISOR[6:0]
+ *
+ * NOTE: the explicit equation above is reduced. Do not
+ * try to infer anything from these numbers.
+ */
+static int parse_pixclock(char *pixclock)
+{
+	int divisor, pixclock_val;
+	char *pixclk_start = pixclock;
+
+	pixclock_val = simple_strtoul(pixclock, &pixclock, 10);
+	divisor = DIV_ROUND_UP(PIXEL_CLK_NUMERATOR, pixclock_val);
+	/* 0 and 1 are illegal values for PCD */
+	if (divisor <= 1)
+		divisor = 2;
+
+	panel_cfg.divisor = divisor | (1 << 16);
+	if (pixclock[0] != '\0') {
+		printf("LCD: invalid value for pixclock:%s\n", pixclk_start);
+		return -1;
+	}
+
+	return 0;
+}
+
+/*
+ * parse_setting() - parse a single setting of custom lcd parameters
+ *
+ * @setting:	The custom lcd setting <name>:<value>
+ *
+ * Returns -1 on failure, 0 on success.
+ */
+static int parse_setting(char *setting)
+{
+	int num_val;
+	char *setting_start = setting;
+
+	if (!strncmp(setting, "mode:", 5)) {
+		return parse_mode(setting + 5);
+	} else if (!strncmp(setting, "pixclock:", 9)) {
+		return parse_pixclock(setting + 9);
+	} else if (!strncmp(setting, "left:", 5)) {
+		num_val = simple_strtoul(setting + 5, &setting, 0);
+		panel_cfg.timing_h |= DSS_HBP(num_val);
+	} else if (!strncmp(setting, "right:", 6)) {
+		num_val = simple_strtoul(setting + 6, &setting, 0);
+		panel_cfg.timing_h |= DSS_HFP(num_val);
+	} else if (!strncmp(setting, "upper:", 6)) {
+		num_val = simple_strtoul(setting + 6, &setting, 0);
+		panel_cfg.timing_v |= DSS_VBP(num_val);
+	} else if (!strncmp(setting, "lower:", 6)) {
+		num_val = simple_strtoul(setting + 6, &setting, 0);
+		panel_cfg.timing_v |= DSS_VFP(num_val);
+	} else if (!strncmp(setting, "hsynclen:", 9)) {
+		num_val = simple_strtoul(setting + 9, &setting, 0);
+		panel_cfg.timing_h |= DSS_HSW(num_val);
+	} else if (!strncmp(setting, "vsynclen:", 9)) {
+		num_val = simple_strtoul(setting + 9, &setting, 0);
+		panel_cfg.timing_v |= DSS_VSW(num_val);
+	} else if (!strncmp(setting, "hsync:", 6)) {
+		if (simple_strtoul(setting + 6, &setting, 0) == 0)
+			panel_cfg.pol_freq |= DSS_IHS;
+		else
+			panel_cfg.pol_freq &= ~DSS_IHS;
+	} else if (!strncmp(setting, "vsync:", 6)) {
+		if (simple_strtoul(setting + 6, &setting, 0) == 0)
+			panel_cfg.pol_freq |= DSS_IVS;
+		else
+			panel_cfg.pol_freq &= ~DSS_IVS;
+	} else if (!strncmp(setting, "outputen:", 9)) {
+		if (simple_strtoul(setting + 9, &setting, 0) == 0)
+			panel_cfg.pol_freq |= DSS_IEO;
+		else
+			panel_cfg.pol_freq &= ~DSS_IEO;
+	} else if (!strncmp(setting, "pixclockpol:", 12)) {
+		if (simple_strtoul(setting + 12, &setting, 0) == 0)
+			panel_cfg.pol_freq |= DSS_IPC;
+		else
+			panel_cfg.pol_freq &= ~DSS_IPC;
+	} else if (!strncmp(setting, "active", 6)) {
+		panel_cfg.panel_type = ACTIVE_DISPLAY;
+		return 0; /* Avoid sanity check below */
+	} else if (!strncmp(setting, "passive", 7)) {
+		panel_cfg.panel_type = PASSIVE_DISPLAY;
+		return 0; /* Avoid sanity check below */
+	} else if (!strncmp(setting, "display:", 8)) {
+		if (!strncmp(setting + 8, "dvi", 3)) {
+			lcd_def = DVI_CUSTOM;
+			return 0; /* Avoid sanity check below */
+		}
+	} else {
+		printf("LCD: unknown option %s\n", setting_start);
+		return -1;
+	}
+
+	if (setting[0] != '\0') {
+		printf("LCD: invalid value for %s\n", setting_start);
+		return -1;
+	}
+
+	return 0;
+}
+
+/*
+ * env_parse_customlcd() - parse custom lcd params from an environment variable.
+ *
+ * @custom_lcd_params:	The environment variable containing the lcd params.
+ *
+ * Returns -1 on failure, 0 on success.
+ */
+static int parse_customlcd(char *custom_lcd_params)
+{
+	char params_cpy[160];
+	char *setting;
+
+	strncpy(params_cpy, custom_lcd_params, 160);
+	setting = strtok(params_cpy, ",");
+	while (setting) {
+		if (parse_setting(setting) < 0)
+			return -1;
+
+		setting = strtok(NULL, ",");
+	}
+
+	/* Currently we don't support changing this via custom lcd params */
+	panel_cfg.data_lines = LCD_INTERFACE_24_BIT;
+	panel_cfg.gfx_format = GFXFORMAT_RGB16; /* See dvi predefines note */
+
+	return 0;
+}
+
+/*
+ * env_parse_displaytype() - parse display type.
+ *
+ * Parses the environment variable "displaytype", which contains the
+ * name of the display type or preset, in which case it applies its
+ * configurations.
+ *
+ * Returns the type of display that was specified.
+ */
+static enum display_type env_parse_displaytype(char *displaytype)
+{
+	if (!strncmp(displaytype, "dvi640x480", 10))
+		return set_dvi_preset(preset_dvi_640X480, 640, 480);
+	else if (!strncmp(displaytype, "dvi800x600", 10))
+		return set_dvi_preset(preset_dvi_800X600, 800, 600);
+	else if (!strncmp(displaytype, "dvi1024x768", 11))
+		return set_dvi_preset(preset_dvi_1024X768, 1024, 768);
+	else if (!strncmp(displaytype, "dvi1152x864", 11))
+		return set_dvi_preset(preset_dvi_1152X864, 1152, 864);
+	else if (!strncmp(displaytype, "dvi1280x960", 11))
+		return set_dvi_preset(preset_dvi_1280X960, 1280, 960);
+	else if (!strncmp(displaytype, "dvi1280x1024", 12))
+		return set_dvi_preset(preset_dvi_1280X1024, 1280, 1024);
+	else if (!strncmp(displaytype, "dataimage480x800", 16))
+		return set_dataimage_preset(preset_dataimage_480X800, 480, 800);
+
+	return NONE;
+}
+
+void lcd_ctrl_init(void *lcdbase)
+{
+	struct prcm *prcm = (struct prcm *)PRCM_BASE;
+	char *custom_lcd;
+	char *displaytype = getenv("displaytype");
+
+	if (displaytype == NULL)
+		return;
+
+	lcd_def = env_parse_displaytype(displaytype);
+	/* If we did not recognize the preset, check if it's an env variable */
+	if (lcd_def == NONE) {
+		custom_lcd = getenv(displaytype);
+		if (custom_lcd == NULL || parse_customlcd(custom_lcd) < 0)
+			return;
+	}
+
+	panel_cfg.frame_buffer = lcdbase;
+	omap3_dss_panel_config(&panel_cfg);
+	/*
+	 * Pixel clock is defined with many divisions and only few
+	 * multiplications of the system clock. Since DSS FCLK divisor is set
+	 * to 16 by default, we need to set it to a smaller value, like 3
+	 * (chosen via trial and error).
+	 */
+	clrsetbits_le32(&prcm->clksel_dss, 0xF, 3);
+}
+
+#ifdef CONFIG_SCF0403_LCD
+static void scf0403_enable(void)
+{
+	gpio_direction_output(58, 1);
+	scf0403_init(157);
+}
+#else
+static inline void scf0403_enable(void) {}
+#endif
+
+void lcd_enable(void)
+{
+	switch (lcd_def) {
+	case NONE:
+		return;
+	case DVI:
+	case DVI_CUSTOM:
+		gpio_direction_output(54, 0); /* Turn on DVI */
+		break;
+	case DATA_IMAGE:
+		scf0403_enable();
+		break;
+	}
+
+	omap3_dss_enable();
+}
+
+void lcd_setcolreg(ushort regno, ushort red, ushort green, ushort blue) {}
diff --git a/board/compulab/trimslice/Makefile b/board/compulab/trimslice/Makefile
index 3ce180cf01..311eb92d7b 100644
--- a/board/compulab/trimslice/Makefile
+++ b/board/compulab/trimslice/Makefile
@@ -5,28 +5,6 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
+obj-y	:= trimslice.o
 
-$(shell mkdir -p $(obj)../../nvidia/common)
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS-y	:= $(BOARD).o
-
-include ../../nvidia/common/common.mk
-
-COBJS	:= $(COBJS-y)
-SRCS	:= $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+include $(srctree)/board/nvidia/common/common.mk
diff --git a/board/congatec/cgtqmx6eval/Makefile b/board/congatec/cgtqmx6eval/Makefile
index 8668d97688..1bce4737f0 100644
--- a/board/congatec/cgtqmx6eval/Makefile
+++ b/board/congatec/cgtqmx6eval/Makefile
@@ -7,23 +7,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB    = $(obj)lib$(BOARD).o
-
-COBJS  := cgtqmx6eval.o
-
-SRCS   := $(COBJS:.o=.c)
-OBJS   := $(addprefix $(obj),$(COBJS))
-
-$(LIB):        $(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y  := cgtqmx6eval.o
diff --git a/board/congatec/cgtqmx6eval/cgtqmx6eval.c b/board/congatec/cgtqmx6eval/cgtqmx6eval.c
index 1ea68f4668..749253429b 100644
--- a/board/congatec/cgtqmx6eval/cgtqmx6eval.c
+++ b/board/congatec/cgtqmx6eval/cgtqmx6eval.c
@@ -35,32 +35,32 @@ int dram_init(void)
 }
 
 iomux_v3_cfg_t const uart2_pads[] = {
-	MX6_PAD_EIM_D26__UART2_TXD | MUX_PAD_CTRL(UART_PAD_CTRL),
-	MX6_PAD_EIM_D27__UART2_RXD | MUX_PAD_CTRL(UART_PAD_CTRL),
+	MX6_PAD_EIM_D26__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
+	MX6_PAD_EIM_D27__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
 };
 
 iomux_v3_cfg_t const usdhc2_pads[] = {
-	MX6_PAD_SD2_CLK__USDHC2_CLK   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD2_CMD__USDHC2_CMD   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD2_DAT0__USDHC2_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD2_DAT1__USDHC2_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD2_DAT2__USDHC2_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD2_DAT3__USDHC2_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_GPIO_4__GPIO_1_4      | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD2_CLK__SD2_CLK   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD2_CMD__SD2_CMD   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_GPIO_4__GPIO1_IO04      | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 };
 
 iomux_v3_cfg_t const usdhc4_pads[] = {
-	MX6_PAD_SD4_CLK__USDHC4_CLK   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD4_CMD__USDHC4_CMD   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD4_DAT0__USDHC4_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD4_DAT1__USDHC4_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD4_DAT2__USDHC4_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD4_DAT3__USDHC4_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD4_DAT4__USDHC4_DAT4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD4_DAT5__USDHC4_DAT5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD4_DAT6__USDHC4_DAT6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD4_DAT7__USDHC4_DAT7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_NANDF_D6__GPIO_2_6    | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
+	MX6_PAD_SD4_CLK__SD4_CLK   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD4_CMD__SD4_CMD   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD4_DAT4__SD4_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD4_DAT5__SD4_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD4_DAT6__SD4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD4_DAT7__SD4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_NANDF_D6__GPIO2_IO06    | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
 };
 
 static void setup_iomux_uart(void)
diff --git a/board/corscience/tricorder/Makefile b/board/corscience/tricorder/Makefile
index 2ab12bb954..266432dd2d 100644
--- a/board/corscience/tricorder/Makefile
+++ b/board/corscience/tricorder/Makefile
@@ -8,23 +8,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	:= tricorder.o
-
-SRCS	:= $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	:= tricorder.o tricorder-eeprom.o led.o
diff --git a/board/corscience/tricorder/led.c b/board/corscience/tricorder/led.c
new file mode 100644
index 0000000000..30f2f508f0
--- /dev/null
+++ b/board/corscience/tricorder/led.c
@@ -0,0 +1,80 @@
+/*
+ * Copyright (c) 2013 Corscience GmbH & Co.KG
+ * Andreas Bießmann <andreas.biessmann@corscience.de>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+#include <common.h>
+#include <status_led.h>
+#include <twl4030.h>
+#include <asm/arch/cpu.h>
+#include <asm/io.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/gpio.h>
+
+#define TRICORDER_STATUS_LED_YELLOW 42
+#define TRICORDER_STATUS_LED_GREEN  43
+
+void __led_init(led_id_t mask, int state)
+{
+	__led_set(mask, state);
+}
+
+void __led_toggle(led_id_t mask)
+{
+	int toggle_gpio = 0;
+#ifdef STATUS_LED_BIT
+	if (!toggle_gpio && STATUS_LED_BIT & mask)
+		toggle_gpio = TRICORDER_STATUS_LED_GREEN;
+#endif
+#ifdef STATUS_LED_BIT1
+	if (!toggle_gpio && STATUS_LED_BIT1 & mask)
+		toggle_gpio = TRICORDER_STATUS_LED_YELLOW;
+#endif
+#ifdef STATUS_LED_BIT2
+	if (!toggle_gpio && STATUS_LED_BIT2 & mask) {
+		uint8_t val;
+		twl4030_i2c_read_u8(TWL4030_CHIP_LED, TWL4030_LED_LEDEN,
+				    &val);
+		val ^= (TWL4030_LED_LEDEN_LEDAON | TWL4030_LED_LEDEN_LEDAPWM);
+		twl4030_i2c_write_u8(TWL4030_CHIP_LED, TWL4030_LED_LEDEN,
+				     val);
+	}
+#endif
+	if (toggle_gpio) {
+		int state;
+		gpio_request(toggle_gpio, "");
+		state = gpio_get_value(toggle_gpio);
+		gpio_set_value(toggle_gpio, !state);
+	}
+}
+
+void __led_set(led_id_t mask, int state)
+{
+#ifdef STATUS_LED_BIT
+	if (STATUS_LED_BIT & mask) {
+		gpio_request(TRICORDER_STATUS_LED_GREEN, "");
+		gpio_direction_output(TRICORDER_STATUS_LED_GREEN, 0);
+		gpio_set_value(TRICORDER_STATUS_LED_GREEN, state);
+	}
+#endif
+#ifdef STATUS_LED_BIT1
+	if (STATUS_LED_BIT1 & mask) {
+		gpio_request(TRICORDER_STATUS_LED_YELLOW, "");
+		gpio_direction_output(TRICORDER_STATUS_LED_YELLOW, 0);
+		gpio_set_value(TRICORDER_STATUS_LED_YELLOW, state);
+	}
+#endif
+#ifdef STATUS_LED_BIT2
+	if (STATUS_LED_BIT2 & mask) {
+		if (STATUS_LED_OFF == state)
+			twl4030_i2c_write_u8(TWL4030_CHIP_LED,
+					     TWL4030_LED_LEDEN, 0);
+		else
+			twl4030_i2c_write_u8(TWL4030_CHIP_LED,
+					     TWL4030_LED_LEDEN,
+					     (TWL4030_LED_LEDEN_LEDAON |
+					      TWL4030_LED_LEDEN_LEDAPWM));
+	}
+#endif
+}
diff --git a/board/corscience/tricorder/tricorder-eeprom.c b/board/corscience/tricorder/tricorder-eeprom.c
new file mode 100644
index 0000000000..1c74a0f7d0
--- /dev/null
+++ b/board/corscience/tricorder/tricorder-eeprom.c
@@ -0,0 +1,251 @@
+/*
+ * (C) Copyright 2013
+ * Corscience GmbH & Co. KG, <www.corscience.de>
+ * Andreas Bießmann <andreas.biessmann@corscience.de>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+#include <common.h>
+#include <i2c.h>
+
+#include "tricorder-eeprom.h"
+
+static inline void warn_wrong_value(const char *msg, unsigned int a,
+		unsigned int b)
+{
+	printf("Expected EEPROM %s %08x, got %08x\n", msg, a, b);
+}
+
+static int handle_eeprom_v0(struct tricorder_eeprom *eeprom)
+{
+	struct tricorder_eeprom_v0 {
+		uint32_t magic;
+		uint16_t length;
+		uint16_t version;
+		char board_name[TRICORDER_BOARD_NAME_LENGTH];
+		char board_version[TRICORDER_BOARD_VERSION_LENGTH];
+		char board_serial[TRICORDER_BOARD_SERIAL_LENGTH];
+		uint32_t crc32;
+	} __packed eepromv0;
+	uint32_t crc;
+
+	printf("Old EEPROM (v0), consider rewrite!\n");
+
+	if (be16_to_cpu(eeprom->length) != sizeof(eepromv0)) {
+		warn_wrong_value("length", sizeof(eepromv0),
+				 be16_to_cpu(eeprom->length));
+		return 1;
+	}
+
+	memcpy(&eepromv0, eeprom, sizeof(eepromv0));
+
+	crc = crc32(0L, (unsigned char *)&eepromv0,
+		    sizeof(eepromv0) - sizeof(eepromv0.crc32));
+	if (be32_to_cpu(eepromv0.crc32) != crc) {
+		warn_wrong_value("CRC", be32_to_cpu(eepromv0.crc32),
+				 crc);
+		return 1;
+	}
+
+	/* Ok the content is correct, do the conversion */
+	memset(eeprom->interface_version, 0x0,
+	       TRICORDER_INTERFACE_VERSION_LENGTH);
+	crc = crc32(0L, (unsigned char *)eeprom, TRICORDER_EEPROM_CRC_SIZE);
+	eeprom->crc32 = cpu_to_be32(crc);
+
+	return 0;
+}
+
+static int handle_eeprom_v1(struct tricorder_eeprom *eeprom)
+{
+	uint32_t crc;
+
+	if (be16_to_cpu(eeprom->length) != TRICORDER_EEPROM_SIZE) {
+		warn_wrong_value("length", TRICORDER_EEPROM_SIZE,
+				 be16_to_cpu(eeprom->length));
+		return 1;
+	}
+
+	crc = crc32(0L, (unsigned char *)eeprom, TRICORDER_EEPROM_CRC_SIZE);
+	if (be32_to_cpu(eeprom->crc32) != crc) {
+		warn_wrong_value("CRC", be32_to_cpu(eeprom->crc32), crc);
+		return 1;
+	}
+
+	return 0;
+}
+
+int tricorder_get_eeprom(int addr, struct tricorder_eeprom *eeprom)
+{
+#ifdef CONFIG_SYS_EEPROM_BUS_NUM
+	unsigned int bus = i2c_get_bus_num();
+	i2c_set_bus_num(CONFIG_SYS_EEPROM_BUS_NUM);
+#endif
+
+	memset(eeprom, 0, TRICORDER_EEPROM_SIZE);
+
+	i2c_read(addr, 0, 2, (unsigned char *)eeprom, TRICORDER_EEPROM_SIZE);
+#ifdef CONFIG_SYS_EEPROM_BUS_NUM
+	i2c_set_bus_num(bus);
+#endif
+
+	if (be32_to_cpu(eeprom->magic) != TRICORDER_EEPROM_MAGIC) {
+		warn_wrong_value("magic", TRICORDER_EEPROM_MAGIC,
+				 be32_to_cpu(eeprom->magic));
+		return 1;
+	}
+
+	switch (be16_to_cpu(eeprom->version)) {
+	case 0:
+		return handle_eeprom_v0(eeprom);
+	case 1:
+		return handle_eeprom_v1(eeprom);
+	default:
+		warn_wrong_value("version", TRICORDER_EEPROM_VERSION,
+				 be16_to_cpu(eeprom->version));
+		return 1;
+	}
+}
+
+#if !defined(CONFIG_SPL)
+int tricorder_eeprom_read(unsigned devaddr)
+{
+	struct tricorder_eeprom eeprom;
+	int ret = tricorder_get_eeprom(devaddr, &eeprom);
+
+	if (ret)
+		return ret;
+
+	printf("Board type:               %.*s\n",
+	       sizeof(eeprom.board_name), eeprom.board_name);
+	printf("Board version:            %.*s\n",
+	       sizeof(eeprom.board_version), eeprom.board_version);
+	printf("Board serial:             %.*s\n",
+	       sizeof(eeprom.board_serial), eeprom.board_serial);
+	printf("Board interface version:  %.*s\n",
+	       sizeof(eeprom.interface_version),
+	       eeprom.interface_version);
+
+	return ret;
+}
+
+int tricorder_eeprom_write(unsigned devaddr, const char *name,
+		const char *version, const char *serial, const char *interface)
+{
+	struct tricorder_eeprom eeprom, eeprom_verify;
+	size_t length;
+	uint32_t crc;
+	int ret;
+	unsigned char *p;
+	int i;
+#ifdef CONFIG_SYS_EEPROM_BUS_NUM
+	unsigned int bus;
+#endif
+
+	memset(eeprom, 0, TRICORDER_EEPROM_SIZE);
+	memset(eeprom_verify, 0, TRICORDER_EEPROM_SIZE);
+
+	eeprom.magic = cpu_to_be32(TRICORDER_EEPROM_MAGIC);
+	eeprom.length = cpu_to_be16(TRICORDER_EEPROM_SIZE);
+	eeprom.version = cpu_to_be16(TRICORDER_EEPROM_VERSION);
+
+	length = min(sizeof(eeprom.board_name), strlen(name));
+	strncpy(eeprom.board_name, name, length);
+
+	length = min(sizeof(eeprom.board_version), strlen(version));
+	strncpy(eeprom.board_version, version, length);
+
+	length = min(sizeof(eeprom.board_serial), strlen(serial));
+	strncpy(eeprom.board_serial, serial, length);
+
+	if (interface) {
+		length = min(sizeof(eeprom.interface_version),
+				strlen(interface));
+		strncpy(eeprom.interface_version, interface, length);
+	}
+
+	crc = crc32(0L, (unsigned char *)&eeprom, TRICORDER_EEPROM_CRC_SIZE);
+	eeprom.crc32 = cpu_to_be32(crc);
+
+#if defined(DEBUG)
+	puts("Tricorder EEPROM content:\n");
+	print_buffer(0, &eeprom, 1, sizeof(eeprom), 16);
+#endif
+
+#ifdef CONFIG_SYS_EEPROM_BUS_NUM
+	bus = i2c_get_bus_num();
+	i2c_set_bus_num(CONFIG_SYS_EEPROM_BUS_NUM);
+#endif
+
+	/* do page write to the eeprom */
+	for (i = 0, p = (unsigned char *)&eeprom;
+	     i < sizeof(eeprom);
+	     i += 32, p += 32) {
+		ret = i2c_write(devaddr, i, CONFIG_SYS_I2C_EEPROM_ADDR_LEN,
+				p, min(sizeof(eeprom) - i, 32));
+		if (ret)
+			break;
+		udelay(5000); /* 5ms write cycle timing */
+	}
+
+	ret = i2c_read(devaddr, 0, 2, (unsigned char *)&eeprom_verify,
+			TRICORDER_EEPROM_SIZE);
+
+	if (memcmp(&eeprom, &eeprom_verify, sizeof(eeprom)) != 0) {
+		printf("Tricorder: Could not verify EEPROM content!\n");
+		ret = 1;
+	}
+
+#ifdef CONFIG_SYS_EEPROM_BUS_NUM
+	i2c_set_bus_num(bus);
+#endif
+	return ret;
+}
+
+int do_tricorder_eeprom(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+	if (argc == 3) {
+		ulong dev_addr = simple_strtoul(argv[2], NULL, 16);
+		eeprom_init();
+		if (strcmp(argv[1], "read") == 0) {
+			int rcode;
+
+			rcode = tricorder_eeprom_read(dev_addr);
+
+			return rcode;
+		}
+	} else if (argc == 6 || argc == 7) {
+		ulong dev_addr = simple_strtoul(argv[2], NULL, 16);
+		char *name = argv[3];
+		char *version = argv[4];
+		char *serial = argv[5];
+		char *interface = NULL;
+		eeprom_init();
+
+		if (argc == 7)
+			interface = argv[6];
+
+		if (strcmp(argv[1], "write") == 0) {
+			int rcode;
+
+			rcode = tricorder_eeprom_write(dev_addr, name, version,
+					serial, interface);
+
+			return rcode;
+		}
+	}
+
+	return CMD_RET_USAGE;
+}
+
+U_BOOT_CMD(
+	tricordereeprom,	7,	1,	do_tricorder_eeprom,
+	"Tricorder EEPROM",
+	"read  devaddr\n"
+	"       - read Tricorder EEPROM at devaddr and print content\n"
+	"tricordereeprom write devaddr name version serial [interface]\n"
+	"       - write Tricorder EEPROM at devaddr with 'name', 'version'"
+	"and 'serial'\n"
+	"         optional add an HW interface parameter"
+);
+#endif /* CONFIG_SPL */
diff --git a/board/corscience/tricorder/tricorder-eeprom.h b/board/corscience/tricorder/tricorder-eeprom.h
new file mode 100644
index 0000000000..06ed9a5911
--- /dev/null
+++ b/board/corscience/tricorder/tricorder-eeprom.h
@@ -0,0 +1,41 @@
+/*
+ * (C) Copyright 2013
+ * Corscience GmbH & Co. KG, <www.corscience.de>
+ * Andreas Bießmann <andreas.biessmann@corscience.de>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+#ifndef TRICORDER_EEPROM_H_
+#define TRICORDER_EEPROM_H_
+
+#include <linux/compiler.h>
+
+#define TRICORDER_EEPROM_MAGIC 0xc2a94f52
+#define TRICORDER_EEPROM_VERSION 1
+
+#define TRICORDER_BOARD_NAME_LENGTH		12
+#define TRICORDER_BOARD_VERSION_LENGTH		4
+#define TRICORDER_BOARD_SERIAL_LENGTH		12
+#define TRICORDER_INTERFACE_VERSION_LENGTH	4
+
+struct tricorder_eeprom {
+	uint32_t magic;
+	uint16_t length;
+	uint16_t version;
+	char board_name[TRICORDER_BOARD_NAME_LENGTH];
+	char board_version[TRICORDER_BOARD_VERSION_LENGTH];
+	char board_serial[TRICORDER_BOARD_SERIAL_LENGTH];
+	char interface_version[TRICORDER_INTERFACE_VERSION_LENGTH];
+	uint32_t crc32;
+} __packed;
+
+#define TRICORDER_EEPROM_SIZE		sizeof(struct tricorder_eeprom)
+#define TRICORDER_EEPROM_CRC_SIZE	(TRICORDER_EEPROM_SIZE - \
+					 sizeof(uint32_t))
+
+/**
+ * @brief read eeprom information from a specific eeprom address
+ */
+int tricorder_get_eeprom(int addr, struct tricorder_eeprom *eeprom);
+
+#endif /* TRICORDER_EEPROM_H_ */
diff --git a/board/corscience/tricorder/tricorder.c b/board/corscience/tricorder/tricorder.c
index c7099e5e3a..9e81bf3f3f 100644
--- a/board/corscience/tricorder/tricorder.c
+++ b/board/corscience/tricorder/tricorder.c
@@ -13,11 +13,13 @@
 #include <common.h>
 #include <twl4030.h>
 #include <asm/io.h>
+#include <asm/gpio.h>
 #include <asm/arch/mmc_host_def.h>
 #include <asm/arch/mux.h>
 #include <asm/arch/sys_proto.h>
 #include <asm/arch/mem.h>
 #include "tricorder.h"
+#include "tricorder-eeprom.h"
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -34,16 +36,93 @@ int board_init(void)
 	return 0;
 }
 
+/**
+ * get_eeprom - read the eeprom
+ *
+ * @eeprom - pointer to a eeprom struct to fill
+ *
+ * This function will panic() on wrong EEPROM content
+ */
+static void get_eeprom(struct tricorder_eeprom *eeprom)
+{
+	int ret;
+
+	if (!eeprom)
+		panic("No eeprom given!\n");
+
+	ret = gpio_request(7, "BMS");
+	if (ret)
+		panic("gpio: requesting BMS pin failed\n");
+
+	ret = gpio_direction_input(7);
+	if (ret)
+		panic("gpio: set BMS as input failed\n");
+
+	ret = gpio_get_value(7);
+	if (ret < 0)
+		panic("gpio: get BMS pin state failed\n");
+
+	gpio_free(7);
+
+	if (ret == 0) {
+		/* BMS is _not_ set, do the EEPROM check */
+		ret = tricorder_get_eeprom(0x51, eeprom);
+		if (!ret) {
+			if (strncmp(eeprom->board_name, "CS10411", 7) != 0)
+				panic("Wrong board name '%.*s'\n",
+				      sizeof(eeprom->board_name),
+						eeprom->board_name);
+			if (eeprom->board_version[0] < 'D')
+				panic("Wrong board version '%.*s'\n",
+				      sizeof(eeprom->board_version),
+						eeprom->board_version);
+		} else {
+			panic("Could not get board revision\n");
+		}
+	} else {
+		memset(eeprom, 0, TRICORDER_EEPROM_SIZE);
+	}
+}
+
+/**
+ * print_hwversion - print out a HW version string
+ *
+ * @eeprom - pointer to the eeprom
+ */
+static void print_hwversion(struct tricorder_eeprom *eeprom)
+{
+	size_t len;
+	if (!eeprom)
+		panic("No eeprom given!");
+
+	printf("Board %.*s:%.*s serial %.*s",
+	       sizeof(eeprom->board_name), eeprom->board_name,
+	       sizeof(eeprom->board_version), eeprom->board_version,
+	       sizeof(eeprom->board_serial), eeprom->board_serial);
+
+	len = strnlen(eeprom->interface_version,
+		      sizeof(eeprom->interface_version));
+	if (len > 0)
+		printf(" HW interface version %.*s",
+		       sizeof(eeprom->interface_version),
+		       eeprom->interface_version);
+	puts("\n");
+}
+
 /*
  * Routine: misc_init_r
  * Description: Configure board specific parts
  */
 int misc_init_r(void)
 {
+	struct tricorder_eeprom eeprom;
+	get_eeprom(&eeprom);
+	print_hwversion(&eeprom);
+
 	twl4030_power_init();
-#ifdef CONFIG_TWL4030_LED
-	twl4030_led_init(TWL4030_LED_LEDEN_LEDAON | TWL4030_LED_LEDEN_LEDBON);
-#endif
+	status_led_set(0, STATUS_LED_ON);
+	status_led_set(1, STATUS_LED_ON);
+	status_led_set(2, STATUS_LED_ON);
 
 	dieid_num_r();
 
@@ -77,12 +156,43 @@ int board_mmc_init(bd_t *bis)
  */
 void get_board_mem_timings(struct board_sdrc_timings *timings)
 {
+	struct tricorder_eeprom eeprom;
+	get_eeprom(&eeprom);
+
 	/* General SDRC config */
-	timings->mcfg = MICRON_V_MCFG_165(128 << 20);
-	timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
+	if (eeprom.board_version[0] > 'D') {
+		/* use optimized timings for our SDRAM device */
+		timings->mcfg = MCFG((256 << 20), 14);
+#define MT46H64M32_TDAL  6	/* Twr/Tck + Trp/tck		*/
+				/* 15/6 + 18/6 = 5.5 -> 6	*/
+#define MT46H64M32_TDPL  3	/* 15/6 = 2.5 -> 3 (Twr)	*/
+#define MT46H64M32_TRRD  2	/* 12/6 = 2			*/
+#define MT46H64M32_TRCD  3	/* 18/6 = 3			*/
+#define MT46H64M32_TRP   3	/* 18/6 = 3			*/
+#define MT46H64M32_TRAS  7	/* 42/6 = 7			*/
+#define MT46H64M32_TRC  10	/* 60/6 = 10			*/
+#define MT46H64M32_TRFC 12	/* 72/6 = 12			*/
+		timings->ctrla = ACTIM_CTRLA(MT46H64M32_TRFC, MT46H64M32_TRC,
+					     MT46H64M32_TRAS, MT46H64M32_TRP,
+					     MT46H64M32_TRCD, MT46H64M32_TRRD,
+					     MT46H64M32_TDPL,
+					     MT46H64M32_TDAL);
+
+#define MT46H64M32_TWTR 1
+#define MT46H64M32_TCKE 1
+#define MT46H64M32_XSR 19	/* 112.5/6 = 18.75 => ~19	*/
+#define MT46H64M32_TXP 1
+		timings->ctrlb = ACTIM_CTRLB(MT46H64M32_TWTR, MT46H64M32_TCKE,
+					     MT46H64M32_TXP, MT46H64M32_XSR);
 
-	/* AC timings */
-	timings->ctrla = MICRON_V_ACTIMA_165;
-	timings->ctrlb = MICRON_V_ACTIMB_165;
-	timings->mr = MICRON_V_MR_165;
+		timings->mr = MICRON_V_MR_165;
+		timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
+	} else {
+		/* use conservative beagleboard timings as default */
+		timings->mcfg = MICRON_V_MCFG_165(128 << 20);
+		timings->ctrla = MICRON_V_ACTIMA_165;
+		timings->ctrlb = MICRON_V_ACTIMB_165;
+		timings->mr = MICRON_V_MR_165;
+		timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
+	}
 }
diff --git a/board/corscience/tricorder/tricorder.h b/board/corscience/tricorder/tricorder.h
index 820a50c9f7..67c35c56bc 100644
--- a/board/corscience/tricorder/tricorder.h
+++ b/board/corscience/tricorder/tricorder.h
@@ -75,8 +75,8 @@ const omap3_sysinfo sysinfo = {
 	MUX_VAL(CP(GPMC_A6),		(IDIS | PTD | DIS | M0)) /*GPMC_A6*/\
 	MUX_VAL(CP(GPMC_A7),		(IDIS | PTD | DIS | M0)) /*GPMC_A7*/\
 	MUX_VAL(CP(GPMC_A8),		(IDIS | PTD | DIS | M0)) /*GPMC_A8*/\
-	MUX_VAL(CP(GPMC_A9),		(IDIS | PTD | DIS | M0)) /*GPMC_A9*/\
-	MUX_VAL(CP(GPMC_A10),		(IDIS | PTD | DIS | M0)) /*GPMC_A10*/\
+	MUX_VAL(CP(GPMC_A9),		(IDIS | PTU | EN  | M4)) /*GPIO 42*/\
+	MUX_VAL(CP(GPMC_A10),		(IDIS | PTU | EN  | M4)) /*GPIO 43*/\
 	MUX_VAL(CP(GPMC_D0),		(IEN  | PTD | DIS | M0)) /*GPMC_D0*/\
 	MUX_VAL(CP(GPMC_D1),		(IEN  | PTD | DIS | M0)) /*GPMC_D1*/\
 	MUX_VAL(CP(GPMC_D2),		(IEN  | PTD | DIS | M0)) /*GPMC_D2*/\
diff --git a/board/cpc45/Makefile b/board/cpc45/Makefile
index 446585fc1d..1310f93877 100644
--- a/board/cpc45/Makefile
+++ b/board/cpc45/Makefile
@@ -5,24 +5,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	= $(BOARD).o flash.o plx9030.o pd67290.o ide.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	= cpc45.o flash.o plx9030.o pd67290.o ide.o
diff --git a/board/cpu86/Makefile b/board/cpu86/Makefile
index e9558412e1..da83afd700 100644
--- a/board/cpu86/Makefile
+++ b/board/cpu86/Makefile
@@ -5,24 +5,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	= $(BOARD).o flash.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	= cpu86.o flash.o
diff --git a/board/cpu87/Makefile b/board/cpu87/Makefile
index e9558412e1..0d59bbbb38 100644
--- a/board/cpu87/Makefile
+++ b/board/cpu87/Makefile
@@ -5,24 +5,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	= $(BOARD).o flash.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	= cpu87.o flash.o
diff --git a/board/cray/L1/.gitignore b/board/cray/L1/.gitignore
new file mode 100644
index 0000000000..cd76d660ef
--- /dev/null
+++ b/board/cray/L1/.gitignore
@@ -0,0 +1,2 @@
+bootscript.c
+bootscript.image
diff --git a/board/cray/L1/L1.h b/board/cray/L1/L1.h
deleted file mode 100644
index 42c34dd910..0000000000
--- a/board/cray/L1/L1.h
+++ /dev/null
@@ -1,28 +0,0 @@
-/*
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-/****************************************************************************
- * FLASH Memory Map as used by CRAY L1, 4MB AMD29F032B flash chip
- *
- *                          Start Address    Length
- * +++++++++++++++++++++++++ 0xFFC0_0000     Start of Flash -----------------
- * | Failsafe Linux Image  |	(1M)
- * +=======================+ 0xFFD0_0000
- * | (Reserved FlashFiles) |	(1M)
- * +=======================+ 0xFFE0_0000
- * | Failsafe RootFS       |	(1M)
- * +=======================+ 0xFFF0_0000
- * |                       |
- * | U N U S E D           |
- * |                       |
- * +-----------------------+ 0xFFFD_0000	U-Boot image header (64 bytes)
- * | environment settings  |	(64k)
- * +-----------------------+ 0xFFFE_0000	U-Boot image header (64 bytes)
- * | U-Boot                | 0xFFFE_0040    _start of U-Boot
- * |                       | 0xFFFE_FFFC    reset vector - branch to _start
- * +++++++++++++++++++++++++ 0xFFFF_FFFF     End of Flash -----------------
- *****************************************************************************/
diff --git a/board/cray/L1/Makefile b/board/cray/L1/Makefile
index 9e6461ace1..55402981fd 100644
--- a/board/cray/L1/Makefile
+++ b/board/cray/L1/Makefile
@@ -5,36 +5,23 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
+obj-y	= L1.o flash.o
+obj-y	+= init.o
+obj-y	+= bootscript.o
 
-LIB	= $(obj)lib$(BOARD).o
+quiet_cmd_awk = AWK     $@
+      cmd_awk = od -t x1 -v -A x $< | $(AWK) -f $(filter-out $<,$^) > $@
 
-COBJS	= $(BOARD).o flash.o
-SOBJS	= init.o
+$(obj)/bootscript.c: $(obj)/bootscript.image $(src)/x2c.awk
+	$(call cmd,awk)
 
+quiet_cmd_mkimage = MKIMAGE $@
+cmd_mkimage = $(objtree)/tools/mkimage $(MKIMAGEFLAGS_$(@F)) -d $< $@ \
+        $(if $(KBUILD_VERBOSE:1=), >/dev/null)
 
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
+MKIMAGEFLAGS_bootscript.image := -A ppc -O linux -T script -C none \
+						-a 0 -e 0 -n bootscript
+$(obj)/bootscript.image: $(src)/bootscript.hush
+	$(call cmd,mkimage)
 
-# HACK: depend needs bootscript.c, which needs tools/mkimage, which is not
-# built in the depend stage.  So... put bootscript.o here, not in OBJS
-$(LIB):	$(OBJS) $(SOBJS) $(obj)bootscript.o
-	$(call cmd_link_o_target, $^)
-
-$(obj)$(BOARD).o : $(src)$(BOARD).c $(obj)bootscript.o
-
-$(obj)bootscript.c: $(obj)bootscript.image
-	od -t x1 -v -A x $^ | awk -f x2c.awk > $@
-
-$(obj)bootscript.image: $(src)bootscript.hush $(src)Makefile
-	-$(OBJTREE)/tools/mkimage -A ppc -O linux -T script -C none -a 0 -e 0 -n bootscript -d $(src)bootscript.hush $@
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+clean-files := bootscript.c bootscript.image
\ No newline at end of file
diff --git a/board/cray/L1/init.S b/board/cray/L1/init.S
index 44c688d1f0..d4723c733f 100644
--- a/board/cray/L1/init.S
+++ b/board/cray/L1/init.S
@@ -22,8 +22,6 @@
 /*-----------------------------------------------------------------------------#include <config.h> */
 #include <asm/ppc4xx.h>
 
-#define _LINUX_CONFIG_H 1	/* avoid reading Linux autoconf.h file	*/
-
 #include <ppc_asm.tmpl>
 #include <ppc_defs.h>
 
diff --git a/board/creative/xfi3/Makefile b/board/creative/xfi3/Makefile
index 4dc2b48053..e8eb9ab26e 100644
--- a/board/creative/xfi3/Makefile
+++ b/board/creative/xfi3/Makefile
@@ -5,27 +5,8 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
 ifndef	CONFIG_SPL_BUILD
-COBJS	:= xfi3.o
+obj-y	:= xfi3.o
 else
-COBJS	:= spl_boot.o
+obj-y	:= spl_boot.o
 endif
-
-SRCS	:= $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
diff --git a/board/csb272/Makefile b/board/csb272/Makefile
index fdcbb43034..36ec9b6f4d 100644
--- a/board/csb272/Makefile
+++ b/board/csb272/Makefile
@@ -5,28 +5,5 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-#COBJS	= $(BOARD).o flash.o
-#COBJS	= $(BOARD).o strataflash.o
-COBJS	= $(BOARD).o
-
-SOBJS	= init.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(OBJS) $(SOBJS)
-	$(call cmd_link_o_target, $^)
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	= csb272.o
+obj-y	+= init.o
diff --git a/board/csb272/init.S b/board/csb272/init.S
index 5961978c86..bf1d98680d 100644
--- a/board/csb272/init.S
+++ b/board/csb272/init.S
@@ -4,8 +4,6 @@
 #include <config.h>
 #include <asm/ppc4xx.h>
 
-#define _LINUX_CONFIG_H 1	/* avoid reading Linux autoconf.h file	*/
-
 #include <ppc_asm.tmpl>
 #include <ppc_defs.h>
 
diff --git a/board/csb472/Makefile b/board/csb472/Makefile
index fdcbb43034..5f7e8b533e 100644
--- a/board/csb472/Makefile
+++ b/board/csb472/Makefile
@@ -5,28 +5,5 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-#COBJS	= $(BOARD).o flash.o
-#COBJS	= $(BOARD).o strataflash.o
-COBJS	= $(BOARD).o
-
-SOBJS	= init.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(OBJS) $(SOBJS)
-	$(call cmd_link_o_target, $^)
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	= csb472.o
+obj-y	+= init.o
diff --git a/board/csb472/init.S b/board/csb472/init.S
index 1ebc9ead3a..7383a708b0 100644
--- a/board/csb472/init.S
+++ b/board/csb472/init.S
@@ -4,8 +4,6 @@
 #include <config.h>
 #include <asm/ppc4xx.h>
 
-#define _LINUX_CONFIG_H 1	/* avoid reading Linux autoconf.h file	*/
-
 #include <ppc_asm.tmpl>
 #include <ppc_defs.h>
 
diff --git a/board/cu824/Makefile b/board/cu824/Makefile
index e9558412e1..e7bd7ca3a7 100644
--- a/board/cu824/Makefile
+++ b/board/cu824/Makefile
@@ -5,24 +5,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	= $(BOARD).o flash.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	= cu824.o flash.o
diff --git a/board/d-link/dns325/Makefile b/board/d-link/dns325/Makefile
index 8a8ec0b5c5..b8a5ea1d6a 100644
--- a/board/d-link/dns325/Makefile
+++ b/board/d-link/dns325/Makefile
@@ -10,24 +10,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	:= dns325.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
-	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	:= dns325.o
diff --git a/board/dave/PPChameleonEVB/Makefile b/board/dave/PPChameleonEVB/Makefile
index eafe6e3daf..31edc4a57d 100644
--- a/board/dave/PPChameleonEVB/Makefile
+++ b/board/dave/PPChameleonEVB/Makefile
@@ -5,24 +5,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	= $(BOARD).o flash.o nand.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(OBJS) $(SOBJS)
-	$(call cmd_link_o_target, $^)
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	= PPChameleonEVB.o flash.o nand.o
diff --git a/board/davedenx/aria/Makefile b/board/davedenx/aria/Makefile
index f78fe13d35..dd38b7f389 100644
--- a/board/davedenx/aria/Makefile
+++ b/board/davedenx/aria/Makefile
@@ -4,25 +4,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS-y	:= $(BOARD).o
-
-COBJS	:= $(COBJS-y)
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	:= aria.o
diff --git a/board/davedenx/qong/Makefile b/board/davedenx/qong/Makefile
index 06f63a7b20..48c443d760 100644
--- a/board/davedenx/qong/Makefile
+++ b/board/davedenx/qong/Makefile
@@ -7,25 +7,5 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	:= qong.o fpga.o
-SOBJS	:= lowlevel_init.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
-	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	:= qong.o fpga.o
+obj-y	+= lowlevel_init.o
diff --git a/board/davinci/da8xxevm/Makefile b/board/davinci/da8xxevm/Makefile
index 26dc72ce06..d3acacc33d 100644
--- a/board/davinci/da8xxevm/Makefile
+++ b/board/davinci/da8xxevm/Makefile
@@ -7,27 +7,6 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS-$(CONFIG_MACH_DAVINCI_DA830_EVM)	+= da830evm.o
-COBJS-$(CONFIG_MACH_DAVINCI_DA850_EVM)	+= da850evm.o
-COBJS-$(CONFIG_MACH_DAVINCI_HAWK)	+= hawkboard.o
-
-COBJS   := $(COBJS-y)
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
-	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
-
-#########################################################################
-# This is for $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-$(CONFIG_MACH_DAVINCI_DA830_EVM)	+= da830evm.o
+obj-$(CONFIG_MACH_DAVINCI_DA850_EVM)	+= da850evm.o
+obj-$(CONFIG_MACH_DAVINCI_HAWK)		+= hawkboard.o
diff --git a/board/davinci/da8xxevm/u-boot-spl-da850evm.lds b/board/davinci/da8xxevm/u-boot-spl-da850evm.lds
index 5480d1f276..de21a132b0 100644
--- a/board/davinci/da8xxevm/u-boot-spl-da850evm.lds
+++ b/board/davinci/da8xxevm/u-boot-spl-da850evm.lds
@@ -49,5 +49,9 @@ SECTIONS
 	} >.sram
 
 	__image_copy_end = .;
-	_end = .;
+
+	.end :
+	{
+		*(.__end)
+	}
 }
diff --git a/board/davinci/da8xxevm/u-boot-spl-hawk.lds b/board/davinci/da8xxevm/u-boot-spl-hawk.lds
index e43130aa67..299226b95f 100644
--- a/board/davinci/da8xxevm/u-boot-spl-hawk.lds
+++ b/board/davinci/da8xxevm/u-boot-spl-hawk.lds
@@ -19,8 +19,8 @@ SECTIONS
 	.text      :
 	{
 	  arch/arm/cpu/arm926ejs/start.o		(.text*)
-	  arch/arm/cpu/arm926ejs/davinci/libdavinci.o	(.text*)
-	  drivers/mtd/nand/libnand.o			(.text*)
+	  arch/arm/cpu/arm926ejs/davinci/built-in.o	(.text*)
+	  drivers/mtd/nand/built-in.o			(.text*)
 
 	  *(.text*)
 	}
@@ -61,5 +61,8 @@ SECTIONS
 		__bss_end = .;
 	}
 
-	_end = .;
+	.end :
+	{
+		*(.__end)
+	}
 }
diff --git a/board/davinci/dm355evm/Makefile b/board/davinci/dm355evm/Makefile
index 81eb7e72de..bcb7e6fed5 100644
--- a/board/davinci/dm355evm/Makefile
+++ b/board/davinci/dm355evm/Makefile
@@ -7,24 +7,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	:= $(BOARD).o
-SOBJS	:=
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
-	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
-
-#########################################################################
-# This is for $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	:= dm355evm.o
diff --git a/board/davinci/dm355leopard/Makefile b/board/davinci/dm355leopard/Makefile
index 81eb7e72de..7035429c92 100644
--- a/board/davinci/dm355leopard/Makefile
+++ b/board/davinci/dm355leopard/Makefile
@@ -7,24 +7,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	:= $(BOARD).o
-SOBJS	:=
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
-	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
-
-#########################################################################
-# This is for $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	:= dm355leopard.o
diff --git a/board/davinci/dm365evm/Makefile b/board/davinci/dm365evm/Makefile
index 81eb7e72de..d35d81c2bf 100644
--- a/board/davinci/dm365evm/Makefile
+++ b/board/davinci/dm365evm/Makefile
@@ -7,24 +7,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	:= $(BOARD).o
-SOBJS	:=
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
-	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
-
-#########################################################################
-# This is for $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	:= dm365evm.o
diff --git a/board/davinci/dm6467evm/Makefile b/board/davinci/dm6467evm/Makefile
index 81eb7e72de..acbbdd5032 100644
--- a/board/davinci/dm6467evm/Makefile
+++ b/board/davinci/dm6467evm/Makefile
@@ -7,24 +7,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	:= $(BOARD).o
-SOBJS	:=
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
-	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
-
-#########################################################################
-# This is for $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	:= dm6467evm.o
diff --git a/board/davinci/dvevm/Makefile b/board/davinci/dvevm/Makefile
index 870314a168..7ade325968 100644
--- a/board/davinci/dvevm/Makefile
+++ b/board/davinci/dvevm/Makefile
@@ -7,24 +7,5 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	:= $(BOARD).o
-SOBJS	:= board_init.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
-	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
-
-#########################################################################
-# This is for $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	:= dvevm.o
+obj-y	+= board_init.o
diff --git a/board/davinci/ea20/Makefile b/board/davinci/ea20/Makefile
index 9bdfa7cc74..a5311c40ae 100644
--- a/board/davinci/ea20/Makefile
+++ b/board/davinci/ea20/Makefile
@@ -7,25 +7,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS-y	+= ea20.o
-
-COBJS   := $(COBJS-y)
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
-	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
-
-#########################################################################
-# This is for $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	+= ea20.o
diff --git a/board/davinci/schmoogie/Makefile b/board/davinci/schmoogie/Makefile
index 870314a168..e170d551ff 100644
--- a/board/davinci/schmoogie/Makefile
+++ b/board/davinci/schmoogie/Makefile
@@ -7,24 +7,5 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	:= $(BOARD).o
-SOBJS	:= board_init.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
-	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
-
-#########################################################################
-# This is for $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	:= schmoogie.o
+obj-y	+= board_init.o
diff --git a/board/davinci/sffsdr/Makefile b/board/davinci/sffsdr/Makefile
index 870314a168..4ab30a4061 100644
--- a/board/davinci/sffsdr/Makefile
+++ b/board/davinci/sffsdr/Makefile
@@ -7,24 +7,5 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	:= $(BOARD).o
-SOBJS	:= board_init.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
-	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
-
-#########################################################################
-# This is for $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	:= sffsdr.o
+obj-y	+= board_init.o
diff --git a/board/davinci/sonata/Makefile b/board/davinci/sonata/Makefile
index 870314a168..92e1a180c0 100644
--- a/board/davinci/sonata/Makefile
+++ b/board/davinci/sonata/Makefile
@@ -7,24 +7,5 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	:= $(BOARD).o
-SOBJS	:= board_init.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
-	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
-
-#########################################################################
-# This is for $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	:= sonata.o
+obj-y	+= board_init.o
diff --git a/board/dbau1x00/Makefile b/board/dbau1x00/Makefile
index 9024919913..2f14402a60 100644
--- a/board/dbau1x00/Makefile
+++ b/board/dbau1x00/Makefile
@@ -5,25 +5,5 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	= $(BOARD).o
-SOBJS	= lowlevel_init.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
-	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	= dbau1x00.o
+obj-y	+= lowlevel_init.o
diff --git a/board/denx/m28evk/Makefile b/board/denx/m28evk/Makefile
index 8bdeeceaa0..5e890b1eaf 100644
--- a/board/denx/m28evk/Makefile
+++ b/board/denx/m28evk/Makefile
@@ -5,27 +5,8 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
 ifndef	CONFIG_SPL_BUILD
-COBJS	:= m28evk.o
+obj-y	:= m28evk.o
 else
-COBJS	:= spl_boot.o
+obj-y	:= spl_boot.o
 endif
-
-SRCS	:= $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
diff --git a/board/denx/m53evk/Makefile b/board/denx/m53evk/Makefile
index 1ae71dfaa9..19b8977ae7 100644
--- a/board/denx/m53evk/Makefile
+++ b/board/denx/m53evk/Makefile
@@ -5,23 +5,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	:= m53evk.o
-
-SRCS	:= $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	:= m53evk.o
diff --git a/board/denx/m53evk/m53evk.c b/board/denx/m53evk/m53evk.c
index 32751704b1..74f95011ad 100644
--- a/board/denx/m53evk/m53evk.c
+++ b/board/denx/m53evk/m53evk.c
@@ -13,6 +13,7 @@
 #include <asm/arch/crm_regs.h>
 #include <asm/arch/clock.h>
 #include <asm/arch/iomux-mx53.h>
+#include <asm/imx-common/mx5_video.h>
 #include <asm/arch/spl.h>
 #include <asm/errno.h>
 #include <netdev.h>
@@ -22,27 +23,49 @@
 #include <fsl_esdhc.h>
 #include <asm/gpio.h>
 #include <usb/ehci-fsl.h>
+#include <linux/fb.h>
+#include <ipu_pixfmt.h>
+
+/* Special MXCFB sync flags are here. */
+#include "../drivers/video/mxcfb.h"
 
 DECLARE_GLOBAL_DATA_PTR;
 
-int dram_init(void)
+static uint32_t mx53_dram_size[2];
+
+phys_size_t get_effective_memsize(void)
 {
-	u32 size1, size2;
+	/*
+	 * WARNING: We must override get_effective_memsize() function here
+	 * to report only the size of the first DRAM bank. This is to make
+	 * U-Boot relocator place U-Boot into valid memory, that is, at the
+	 * end of the first DRAM bank. If we did not override this function
+	 * like so, U-Boot would be placed at the address of the first DRAM
+	 * bank + total DRAM size - sizeof(uboot), which in the setup where
+	 * each DRAM bank contains 512MiB of DRAM would result in placing
+	 * U-Boot into invalid memory area close to the end of the first
+	 * DRAM bank.
+	 */
+	return mx53_dram_size[0];
+}
 
-	size1 = get_ram_size((void *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE);
-	size2 = get_ram_size((void *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE);
+int dram_init(void)
+{
+	mx53_dram_size[0] = get_ram_size((void *)PHYS_SDRAM_1, 1 << 30);
+	mx53_dram_size[1] = get_ram_size((void *)PHYS_SDRAM_2, 1 << 30);
 
-	gd->ram_size = size1 + size2;
+	gd->ram_size = mx53_dram_size[0] + mx53_dram_size[1];
 
 	return 0;
 }
+
 void dram_init_banksize(void)
 {
 	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
-	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+	gd->bd->bi_dram[0].size = mx53_dram_size[0];
 
 	gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
-	gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
+	gd->bd->bi_dram[1].size = mx53_dram_size[1];
 }
 
 static void setup_iomux_uart(void)
@@ -166,6 +189,32 @@ int board_mmc_init(bd_t *bis)
 }
 #endif
 
+#ifdef CONFIG_VIDEO
+static struct fb_videomode const ampire_wvga = {
+	.name		= "Ampire",
+	.refresh	= 60,
+	.xres		= 800,
+	.yres		= 480,
+	.pixclock	= 29851, /* picosecond (33.5 MHz) */
+	.left_margin	= 89,
+	.right_margin	= 164,
+	.upper_margin	= 23,
+	.lower_margin	= 10,
+	.hsync_len	= 10,
+	.vsync_len	= 10,
+	.sync		= FB_SYNC_CLK_LAT_FALL,
+};
+
+int board_video_skip(void)
+{
+	int ret;
+	ret = ipuv3_fb_init(&ampire_wvga, 1, IPU_PIX_FMT_RGB666);
+	if (ret)
+		printf("Ampire LCD cannot be configured: %d\n", ret);
+	return ret;
+}
+#endif
+
 #define I2C_PAD_CTRL	(PAD_CTL_SRE_FAST | PAD_CTL_DSE_HIGH | \
 			 PAD_CTL_PUS_100K_UP | PAD_CTL_ODE)
 
@@ -179,6 +228,46 @@ static void setup_iomux_i2c(void)
 	imx_iomux_v3_setup_multiple_pads(i2c_pads, ARRAY_SIZE(i2c_pads));
 }
 
+static void setup_iomux_video(void)
+{
+	static const iomux_v3_cfg_t lcd_pads[] = {
+		MX53_PAD_EIM_DA9__IPU_DISP1_DAT_0,
+		MX53_PAD_EIM_DA8__IPU_DISP1_DAT_1,
+		MX53_PAD_EIM_DA7__IPU_DISP1_DAT_2,
+		MX53_PAD_EIM_DA6__IPU_DISP1_DAT_3,
+		MX53_PAD_EIM_DA5__IPU_DISP1_DAT_4,
+		MX53_PAD_EIM_DA4__IPU_DISP1_DAT_5,
+		MX53_PAD_EIM_DA3__IPU_DISP1_DAT_6,
+		MX53_PAD_EIM_DA2__IPU_DISP1_DAT_7,
+		MX53_PAD_EIM_DA1__IPU_DISP1_DAT_8,
+		MX53_PAD_EIM_DA0__IPU_DISP1_DAT_9,
+		MX53_PAD_EIM_EB1__IPU_DISP1_DAT_10,
+		MX53_PAD_EIM_EB0__IPU_DISP1_DAT_11,
+		MX53_PAD_EIM_A17__IPU_DISP1_DAT_12,
+		MX53_PAD_EIM_A18__IPU_DISP1_DAT_13,
+		MX53_PAD_EIM_A19__IPU_DISP1_DAT_14,
+		MX53_PAD_EIM_A20__IPU_DISP1_DAT_15,
+		MX53_PAD_EIM_A21__IPU_DISP1_DAT_16,
+		MX53_PAD_EIM_A22__IPU_DISP1_DAT_17,
+		MX53_PAD_EIM_A23__IPU_DISP1_DAT_18,
+		MX53_PAD_EIM_A24__IPU_DISP1_DAT_19,
+		MX53_PAD_EIM_D31__IPU_DISP1_DAT_20,
+		MX53_PAD_EIM_D30__IPU_DISP1_DAT_21,
+		MX53_PAD_EIM_D26__IPU_DISP1_DAT_22,
+		MX53_PAD_EIM_D27__IPU_DISP1_DAT_23,
+		MX53_PAD_EIM_A16__IPU_DI1_DISP_CLK,
+		MX53_PAD_EIM_DA13__IPU_DI1_D0_CS,
+		MX53_PAD_EIM_DA14__IPU_DI1_D1_CS,
+		MX53_PAD_EIM_DA15__IPU_DI1_PIN1,
+		MX53_PAD_EIM_DA11__IPU_DI1_PIN2,
+		MX53_PAD_EIM_DA12__IPU_DI1_PIN3,
+		MX53_PAD_EIM_A25__IPU_DI1_PIN12,
+		MX53_PAD_EIM_DA10__IPU_DI1_PIN15,
+	};
+
+	imx_iomux_v3_setup_multiple_pads(lcd_pads, ARRAY_SIZE(lcd_pads));
+}
+
 static void setup_iomux_nand(void)
 {
 	static const iomux_v3_cfg_t nand_pads[] = {
@@ -269,6 +358,7 @@ int board_early_init_f(void)
 	setup_iomux_fec();
 	setup_iomux_i2c();
 	setup_iomux_nand();
+	setup_iomux_video();
 
 	m53_set_clock();
 
diff --git a/board/dnp5370/Makefile b/board/dnp5370/Makefile
index 099bcaf999..865522fd6d 100644
--- a/board/dnp5370/Makefile
+++ b/board/dnp5370/Makefile
@@ -9,24 +9,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS-y	:= $(BOARD).o
-
-SRCS	:= $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS-y))
-SOBJS	:= $(addprefix $(obj),$(SOBJS-y))
-
-$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
-	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	:= dnp5370.o
diff --git a/board/dvlhost/Makefile b/board/dvlhost/Makefile
deleted file mode 100644
index 19753b5932..0000000000
--- a/board/dvlhost/Makefile
+++ /dev/null
@@ -1,28 +0,0 @@
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	:= dvlhost.o watchdog.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
diff --git a/board/dvlhost/dvlhost.c b/board/dvlhost/dvlhost.c
deleted file mode 100644
index 087070f40d..0000000000
--- a/board/dvlhost/dvlhost.c
+++ /dev/null
@@ -1,112 +0,0 @@
-/*
- * (C) Copyright 2009
- * Michael Schwingen, michael@schwingen.org
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <config.h>
-#include <command.h>
-#include <malloc.h>
-#include <asm/arch/ixp425.h>
-#include <asm/io.h>
-#include <miiphy.h>
-#ifdef CONFIG_PCI
-#include <pci.h>
-#include <asm/arch/ixp425pci.h>
-#endif
-
-#include "dvlhost_hw.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int board_early_init_f(void)
-{
-	/* CS1: LED Latch */
-	writel(0xBFFF0002, IXP425_EXP_CS1);
-	return 0;
-}
-
-int board_init(void)
-{
-	/* adress of boot parameters */
-	gd->bd->bi_boot_params = 0x00000100;
-
-	/* Setup GPIOs used as output */
-	GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_WDGTRIGGER);
-	GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_DLAN_PAIRING);
-	GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_PCIRST);
-
-	/*
-	 * LED latch enable and watchdog enable are tied to the same GPIO,
-	 * so we need to trigger the watchdog if we want to enable the LEDs.
-	*/
-#ifdef CONFIG_HW_WATCHDOG
-	GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_WDG_LED_EN);
-#else
-	GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_WDG_LED_EN);
-#endif
-
-	GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_WDGTRIGGER);
-	GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_DLAN_PAIRING);
-	GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_WDG_LED_EN);
-	GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_PCIRST);
-
-	/* Setup GPIOs for Interrupt inputs */
-	GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_BTN_WLAN);
-	GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_BTN_PAIRING);
-	GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_BTN_RESET);
-	GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_IRQA);
-	GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_IRQB);
-
-	/* Setup GPIO's for 33MHz clock output */
-	GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_PCI_CLK);
-	GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_EXTBUS_CLK);
-	writel(0x01FF01FF, IXP425_GPIO_GPCLKR);
-
-	/* turn off all LEDs */
-	writew(0x0000, DVLHOST_LED_LATCH);
-
-	udelay(533);
-	GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_PCIRST);
-
-	return 0;
-}
-
-/* Check Board Identity */
-int checkboard(void)
-{
-	char *s = getenv("serial#");
-
-	puts("Board: dLAN 200AV (dvlhost)");
-
-	if (s != NULL) {
-		puts(", serial# ");
-		puts(s);
-	}
-	putc('\n');
-
-	return 0;
-}
-
-int dram_init(void)
-{
-	gd->ram_size = get_ram_size(CONFIG_SYS_SDRAM_BASE, 128<<20);
-	return 0;
-}
-
-#ifdef CONFIG_PCI
-struct pci_controller hose;
-
-void pci_init_board(void)
-{
-	pci_ixp_init(&hose);
-}
-#endif
-
-void reset_phy(void)
-{
-	/* init IcPlus IP175C ethernet switch to native IP175C mode */
-	miiphy_write("NPE1", 29, 31, 0x175C);
-}
diff --git a/board/dvlhost/dvlhost_hw.h b/board/dvlhost/dvlhost_hw.h
deleted file mode 100644
index 545099e9ea..0000000000
--- a/board/dvlhost/dvlhost_hw.h
+++ /dev/null
@@ -1,31 +0,0 @@
-/*
- * (C) Copyright 2009
- * Michael Schwingen, michael@schwingen.org
- *
- * hardware register definitions for the
- * dLAN200 AV Wireless G ("dvlhost") board.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef _DVLHOST_HW_H
-#define _DVLHOST_HW_H
-
-/*
- * GPIO settings
- */
-#define CONFIG_SYS_GPIO_WDGTRIGGER	0 /* Out */
-#define CONFIG_SYS_GPIO_BTN_WLAN	1
-#define CONFIG_SYS_GPIO_BTN_PAIRING	6
-#define CONFIG_SYS_GPIO_DLAN_PAIRING	7 /* Out */
-#define CONFIG_SYS_GPIO_BTN_RESET	9
-#define CONFIG_SYS_GPIO_IRQB		10
-#define CONFIG_SYS_GPIO_IRQA		11
-#define CONFIG_SYS_GPIO_WDG_LED_EN	12 /* Out */
-#define CONFIG_SYS_GPIO_PCIRST		13 /* Out */
-#define CONFIG_SYS_GPIO_PCI_CLK		14 /* Out */
-#define CONFIG_SYS_GPIO_EXTBUS_CLK	15 /* Out */
-
-#define DVLHOST_LED_LATCH	IXP425_EXP_BUS_CS1_BASE_PHYS
-
-#endif
diff --git a/board/dvlhost/u-boot.lds b/board/dvlhost/u-boot.lds
deleted file mode 100644
index 40c9c8038b..0000000000
--- a/board/dvlhost/u-boot.lds
+++ /dev/null
@@ -1,96 +0,0 @@
-/*
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-OUTPUT_FORMAT ("elf32-bigarm", "elf32-bigarm", "elf32-bigarm")
-OUTPUT_ARCH (arm)
-ENTRY (_start)
-SECTIONS
-{
-	. = 0x00000000;
-
-	. = ALIGN (4);
-	.text : {
-		*(.__image_copy_start)
-		arch/arm/cpu/ixp/start.o(.text*)
-		net/libnet.o(.text*)
-		board/dvlhost/libdvlhost.o(.text*)
-		arch/arm/cpu/ixp/libixp.o(.text*)
-		drivers/serial/libserial.o(.text*)
-
-		. = env_offset;
-		common/env_embedded.o(.ppcenv)
-		*(.text*)
-	}
-
-	. = ALIGN (4);
-	.rodata : {
-		*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
-	}
-	. = ALIGN (4);
-	.data : {
-		*(.data*)
-	}
-	. = ALIGN (4);
-	.got : {
-		*(.got)
-	}
-	. =.;
-
-	. = ALIGN(4);
-	.u_boot_list : {
-		KEEP(*(SORT(.u_boot_list*)));
-	}
-
-	. = ALIGN (4);
-
-	.image_copy_end :
-	{
-		*(.__image_copy_end)
-	}
-
-	.rel_dyn_start :
-	{
-		*(.__rel_dyn_start)
-	}
-
-	.rel.dyn : {
-		*(.rel*)
-	}
-
-	.rel_dyn_end :
-	{
-		*(.__rel_dyn_end)
-	}
-
-	_end = .;
-
-/*
- * Compiler-generated __bss_start and __bss_end, see arch/arm/lib/bss.c
- * __bss_base and __bss_limit are for linker only (overlay ordering)
- */
-
-	.bss_start __rel_dyn_start (OVERLAY) : {
-		KEEP(*(.__bss_start));
-		__bss_base = .;
-	}
-
-	.bss __bss_base (OVERLAY) : {
-		*(.bss*)
-		 . = ALIGN(4);
-		 __bss_limit = .;
-	}
-	.bss_end __bss_limit (OVERLAY) : {
-		KEEP(*(.__bss_end));
-	}
-
-	/DISCARD/ : { *(.dynsym) }
-	/DISCARD/ : { *(.dynstr*) }
-	/DISCARD/ : { *(.dynamic*) }
-	/DISCARD/ : { *(.plt*) }
-	/DISCARD/ : { *(.interp*) }
-	/DISCARD/ : { *(.gnu*) }
-}
diff --git a/board/dvlhost/watchdog.c b/board/dvlhost/watchdog.c
deleted file mode 100644
index 02ec35eb1a..0000000000
--- a/board/dvlhost/watchdog.c
+++ /dev/null
@@ -1,27 +0,0 @@
-/*
- * (C) Copyright 2009
- * Michael Schwingen, michael@schwingen.org
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <config.h>
-#include <asm/io.h>
-#include "dvlhost_hw.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#ifdef CONFIG_HW_WATCHDOG
-#include <watchdog.h>
-#include <asm/arch/ixp425.h>
-
-void hw_watchdog_reset(void)
-{
-	unsigned int x;
-	x = readl(IXP425_GPIO_GPOUTR);
-	x ^= (1 << (CONFIG_SYS_GPIO_WDGTRIGGER));
-	writel(x, IXP425_GPIO_GPOUTR);
-}
-
-#endif /* CONFIG_HW_WATCHDOG */
diff --git a/board/eXalion/Makefile b/board/eXalion/Makefile
index 5fd87809f0..9192e280f8 100644
--- a/board/eXalion/Makefile
+++ b/board/eXalion/Makefile
@@ -5,24 +5,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	= $(BOARD).o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	= eXalion.o
diff --git a/board/earthlcd/favr-32-ezkit/Makefile b/board/earthlcd/favr-32-ezkit/Makefile
index 0b3ebe3e67..f712ab9c7a 100644
--- a/board/earthlcd/favr-32-ezkit/Makefile
+++ b/board/earthlcd/favr-32-ezkit/Makefile
@@ -6,23 +6,4 @@
 #
 # SPDX-License-Identifier:	GPL-2.0+
 
-include $(TOPDIR)/config.mk
-
-LIB	:= $(obj)lib$(BOARD).o
-
-COBJS	:= $(BOARD).o flash.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS))
-
-$(LIB): $(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	:= favr-32-ezkit.o flash.o
diff --git a/board/egnite/ethernut5/Makefile b/board/egnite/ethernut5/Makefile
index 275be0a1a9..2513873840 100644
--- a/board/egnite/ethernut5/Makefile
+++ b/board/egnite/ethernut5/Makefile
@@ -8,25 +8,5 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS-y	+= $(BOARD).o
-COBJS-y	+= $(BOARD)_pwrman.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS-y))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
-	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	+= ethernut5.o
+obj-y	+= ethernut5_pwrman.o
diff --git a/board/egnite/ethernut5/ethernut5.c b/board/egnite/ethernut5/ethernut5.c
index 1f5eea56ac..b45213c245 100644
--- a/board/egnite/ethernut5/ethernut5.c
+++ b/board/egnite/ethernut5/ethernut5.c
@@ -71,6 +71,7 @@
 #include <asm/arch/at91_spi.h>
 #include <asm/arch/gpio.h>
 #include <asm/io.h>
+#include <asm/gpio.h>
 
 #include "ethernut5_pwrman.h"
 
@@ -141,7 +142,7 @@ static void ethernut5_nand_hw_init(void)
 	/* Ready pin is optional. */
 	at91_set_pio_input(CONFIG_SYS_NAND_READY_PIN, 1);
 #endif
-	at91_set_pio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
+	gpio_direction_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
 }
 #endif
 
diff --git a/board/eltec/elppc/Makefile b/board/eltec/elppc/Makefile
index 51179c08df..791f2fbe3d 100644
--- a/board/eltec/elppc/Makefile
+++ b/board/eltec/elppc/Makefile
@@ -5,26 +5,5 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	= $(BOARD).o flash.o pci.o misc.o mpc107_i2c.o eepro100_srom.o
-
-SOBJS	= asm_init.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
-	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	= elppc.o flash.o pci.o misc.o mpc107_i2c.o eepro100_srom.o
+obj-y	+= asm_init.o
diff --git a/board/eltec/mhpc/Makefile b/board/eltec/mhpc/Makefile
index 871865b6ee..f3fcc2f370 100644
--- a/board/eltec/mhpc/Makefile
+++ b/board/eltec/mhpc/Makefile
@@ -5,24 +5,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	= $(BOARD).o flash.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	= mhpc.o flash.o
diff --git a/board/emk/top5200/Makefile b/board/emk/top5200/Makefile
index 4b15bb6637..b455c26e17 100644
--- a/board/emk/top5200/Makefile
+++ b/board/emk/top5200/Makefile
@@ -1,4 +1,3 @@
-
 #
 # (C) Copyright 2003-2006
 # Wolfgang Denk, DENX Software Engineering, wd@denx.de.
@@ -6,27 +5,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-ifneq ($(OBJTREE),$(SRCTREE))
-$(shell mkdir -p $(obj)../common)
-endif
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	:= $(BOARD).o ../common/flash.o ../common/vpd.o ../common/am79c874.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	:= top5200.o ../common/flash.o ../common/vpd.o ../common/am79c874.o
diff --git a/board/emk/top860/Makefile b/board/emk/top860/Makefile
index a45f0ef26a..0401639ce3 100644
--- a/board/emk/top860/Makefile
+++ b/board/emk/top860/Makefile
@@ -5,27 +5,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-ifneq ($(OBJTREE),$(SRCTREE))
-$(shell mkdir -p $(obj)../common)
-endif
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	= $(BOARD).o ../common/flash.o ../common/vpd.o ../common/am79c874.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	= top860.o ../common/flash.o ../common/vpd.o ../common/am79c874.o
diff --git a/board/emk/top9000/Makefile b/board/emk/top9000/Makefile
index 3125164ca9..8725a6cf0d 100644
--- a/board/emk/top9000/Makefile
+++ b/board/emk/top9000/Makefile
@@ -8,25 +8,5 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS-y	+= $(BOARD).o
-COBJS-$(CONFIG_ATMEL_SPI)	+= spi.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS-y))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
-	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	+= top9000.o
+obj-$(CONFIG_ATMEL_SPI)	+= spi.o
diff --git a/board/enbw/enbw_cmc/Makefile b/board/enbw/enbw_cmc/Makefile
index 16e390d80b..054d6e7c83 100644
--- a/board/enbw/enbw_cmc/Makefile
+++ b/board/enbw/enbw_cmc/Makefile
@@ -7,23 +7,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS   := $(BOARD).o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
-	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
-
-#########################################################################
-# This is for $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y   := enbw_cmc.o
diff --git a/board/enbw/enbw_cmc/enbw_cmc.c b/board/enbw/enbw_cmc/enbw_cmc.c
index c477962f34..39efe20bfd 100644
--- a/board/enbw/enbw_cmc/enbw_cmc.c
+++ b/board/enbw/enbw_cmc/enbw_cmc.c
@@ -36,6 +36,7 @@
 #include <asm/arch/hardware.h>
 #include <asm/arch/sdmmc_defs.h>
 #include <asm/arch/timer_defs.h>
+#include <asm/davinci_rtc.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
diff --git a/board/ep8248/Makefile b/board/ep8248/Makefile
index c573be952c..bfaf1c89d8 100644
--- a/board/ep8248/Makefile
+++ b/board/ep8248/Makefile
@@ -5,24 +5,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	:= $(BOARD).o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	:= ep8248.o
diff --git a/board/ep8260/Makefile b/board/ep8260/Makefile
index 0a716f9535..dd08b74bfc 100644
--- a/board/ep8260/Makefile
+++ b/board/ep8260/Makefile
@@ -5,24 +5,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	= $(BOARD).o flash.o mii_phy.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	= ep8260.o flash.o mii_phy.o
diff --git a/board/ep82xxm/Makefile b/board/ep82xxm/Makefile
index 459d7b8ab1..f9d3891cc1 100644
--- a/board/ep82xxm/Makefile
+++ b/board/ep82xxm/Makefile
@@ -5,23 +5,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	:= $(BOARD).o
-
-SRCS	:= $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-
-$(LIB):	$(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	:= ep82xxm.o
diff --git a/board/ep88x/Makefile b/board/ep88x/Makefile
deleted file mode 100644
index 07fa3f3a2f..0000000000
--- a/board/ep88x/Makefile
+++ /dev/null
@@ -1,31 +0,0 @@
-#
-# (C) Copyright 2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# Copyright (C) 2004 Arabella Software Ltd.
-# Yuli Barcohen <yuli@arabellasw.com>
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	:= $(BOARD).o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
diff --git a/board/ep88x/ep88x.c b/board/ep88x/ep88x.c
deleted file mode 100644
index cad0bfc6ca..0000000000
--- a/board/ep88x/ep88x.c
+++ /dev/null
@@ -1,117 +0,0 @@
-/*
- * Copyright (C) 2005 Arabella Software Ltd.
- * Yuli Barcohen <yuli@arabellasw.com>
- *
- * Support for Embedded Planet EP88x boards.
- * Tested on EP88xC with MPC885 CPU, 64MB SDRAM and 16MB flash.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <mpc8xx.h>
-
-/*
- * SDRAM uses two Micron chips.
- * Minimal CPU frequency is 40MHz.
- */
-static uint sdram_table[] = {
-	/* Single read	(offset 0x00 in UPM RAM) */
-	0xEFCBCC04, 0x0F37C804, 0x0EEEC004, 0x01B98404,
-	0x1FF74C00, 0xFFFFCC05, 0xFFFFCC05, 0xFFFFCC05,
-
-	/* Burst read	(offset 0x08 in UPM RAM) */
-	0xEFCBCC04, 0x0F37C804, 0x0EEEC004, 0x00BDC404,
-	0x00FFCC00, 0x00FFCC00, 0x01FB8C00, 0x1FF74C00,
-	0xFFFFCC05, 0xFFFFCC05, 0xFFFFCC05, 0xFFFFCC05,
-	0xFFFFCC05, 0xFFFFCC05, 0xFFFFCC05, 0xFFFFCC05,
-
-	/* Single write (offset 0x18 in UPM RAM) */
-	0xEFCBCC04, 0x0F37C804, 0x0EEE8002, 0x01B90404,
-	0x1FF74C05, 0xFFFFCC05, 0xFFFFCC05, 0xFFFFCC05,
-
-	/* Burst write	(offset 0x20 in UPM RAM) */
-	0xEFCBCC04, 0x0F37C804, 0x0EEE8000, 0x00BD4400,
-	0x00FFCC00, 0x00FFCC02, 0x01FB8C04, 0x1FF74C05,
-	0xFFFFCC05, 0xFFFFCC05, 0xFFFFCC05, 0xFFFFCC05,
-	0xFFFFCC05, 0xFFFFCC05, 0xFFFFCC05, 0xFFFFCC05,
-
-	/* Refresh	(offset 0x30 in UPM RAM) */
-	0xEFFACC04, 0x0FF5CC04, 0x0FFFCC04, 0x1FFFCC04,
-	0xFFFFCC05, 0xFFFFCC05, 0xEFFB8C34, 0x0FF74C34,
-	0x0FFACCB4, 0x0FF5CC34, 0x0FFFC034, 0x0FFFC0B4,
-
-	/* Exception	(offset 0x3C in UPM RAM) */
-	0x0FEA8034, 0x1FB54034,	0xFFFFCC34, 0xFFFFCC05
-};
-
-int board_early_init_f (void)
-{
-	vu_char *bcsr = (vu_char *)CONFIG_SYS_BCSR;
-
-	bcsr[0] |= 0x0C; /* Turn the LEDs off */
-	bcsr[2] |= 0x08; /* Enable flash WE# line - necessary for
-			    flash detection by CFI driver
-			 */
-
-#if defined(CONFIG_8xx_CONS_SMC1)
-	bcsr[6] |= 0x10; /* Enables RS-232 transceiver */
-#endif
-#if defined(CONFIG_8xx_CONS_SCC2)
-	bcsr[7] |= 0x10; /* Enables RS-232 transceiver */
-#endif
-#ifdef CONFIG_ETHER_ON_FEC1
-	bcsr[8] |= 0xC0; /* Enable Ethernet 1 PHY */
-#endif
-#ifdef CONFIG_ETHER_ON_FEC2
-	bcsr[8] |= 0x30; /* Enable Ethernet 2 PHY */
-#endif
-
-	return 0;
-}
-
-phys_size_t initdram (int board_type)
-{
-	long int msize;
-	volatile immap_t     *immap  = (volatile immap_t *)CONFIG_SYS_IMMR;
-	volatile memctl8xx_t *memctl = &immap->im_memctl;
-
-	upmconfig(UPMA, sdram_table, sizeof(sdram_table) / sizeof(uint));
-
-	/* Configure SDRAM refresh */
-	memctl->memc_mptpr = MPTPR_PTP_DIV2; /* BRGCLK/2 */
-
-	memctl->memc_mamr = (65 << 24) | CONFIG_SYS_MAMR; /* No refresh */
-	udelay(100);
-
-	/* Run MRS pattern from location 0x36 */
-	memctl->memc_mar = 0x88;
-	memctl->memc_mcr = 0x80002236;
-	udelay(100);
-
-	memctl->memc_mamr |=  MAMR_PTAE; /* Enable refresh */
-	memctl->memc_or1   = ~(CONFIG_SYS_SDRAM_MAX_SIZE - 1) | OR_CSNT_SAM;
-	memctl->memc_br1   =  CONFIG_SYS_SDRAM_BASE | BR_PS_32 | BR_MS_UPMA | BR_V;
-
-	msize = get_ram_size(CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_SDRAM_MAX_SIZE);
-	memctl->memc_or1  |= ~(msize - 1);
-
-	return msize;
-}
-
-int checkboard( void )
-{
-	vu_char *bcsr = (vu_char *)CONFIG_SYS_BCSR;
-
-	puts("Board: ");
-	switch (bcsr[15]) {
-	case 0xE7:
-		puts("EP88xC 1.0");
-		break;
-	default:
-		printf("unknown ID=%02X", bcsr[15]);
-	}
-	printf("  CPLD revision %d\n", bcsr[14]);
-
-	return 0;
-}
diff --git a/board/ep88x/u-boot.lds b/board/ep88x/u-boot.lds
deleted file mode 100644
index cbb17d1aee..0000000000
--- a/board/ep88x/u-boot.lds
+++ /dev/null
@@ -1,79 +0,0 @@
-/*
- * (C) Copyright 2001-2010
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * Modified by Yuli Barcohen <yuli@arabellasw.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-OUTPUT_ARCH(powerpc)
-SECTIONS
-{
-  /* Read-only sections, merged into text segment: */
-  . = + SIZEOF_HEADERS;
-  .text          :
-  {
-    arch/powerpc/cpu/mpc8xx/start.o	(.text*)
-    arch/powerpc/cpu/mpc8xx/traps.o	(.text*)
-    *(.text*)
-    . = ALIGN(16);
-    *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
-  }
-
-  /* Read-write section, merged into data segment: */
-  . = (. + 0x0FFF) & 0xFFFFF000;
-  _erotext = .;
-  PROVIDE (erotext = .);
-  .reloc   :
-  {
-    _GOT2_TABLE_ = .;
-    KEEP(*(.got2))
-    KEEP(*(.got))
-    PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4);
-    _FIXUP_TABLE_ = .;
-    KEEP(*(.fixup))
-  }
-  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
-  __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
-
-  .data    :
-  {
-    *(.data*)
-    *(.sdata*)
-  }
-  _edata  =  .;
-  PROVIDE (edata = .);
-
-  . = .;
-
-  . = ALIGN(4);
-  .u_boot_list : {
-	KEEP(*(SORT(.u_boot_list*)));
-  }
-
-
-  . = .;
-  __start___ex_table = .;
-  __ex_table : { *(__ex_table) }
-  __stop___ex_table = .;
-
-  . = ALIGN(4096);
-  __init_begin = .;
-  .text.init : { *(.text.init) }
-  .data.init : { *(.data.init) }
-  . = ALIGN(4096);
-  __init_end = .;
-
-  __bss_start = .;
-  .bss (NOLOAD)       :
-  {
-   *(.bss*)
-   *(.sbss*)
-   *(COMMON)
-   . = ALIGN(4);
-  }
-  __bss_end = . ;
-  PROVIDE (end = .);
-}
-ENTRY(_start)
diff --git a/board/esd/adciop/Makefile b/board/esd/adciop/Makefile
index cbe2987ea2..d0e264de92 100644
--- a/board/esd/adciop/Makefile
+++ b/board/esd/adciop/Makefile
@@ -1,4 +1,3 @@
-
 #
 # (C) Copyright 2000-2006
 # Wolfgang Denk, DENX Software Engineering, wd@denx.de.
@@ -6,27 +5,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-ifneq ($(OBJTREE),$(SRCTREE))
-$(shell mkdir -p $(obj)../common)
-endif
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	= $(BOARD).o flash.o ../common/misc.o ../common/pci.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	= adciop.o flash.o ../common/misc.o ../common/pci.o
diff --git a/board/esd/apc405/Makefile b/board/esd/apc405/Makefile
index b84e6624bf..ada8bfd3d3 100644
--- a/board/esd/apc405/Makefile
+++ b/board/esd/apc405/Makefile
@@ -5,29 +5,6 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-ifneq ($(OBJTREE),$(SRCTREE))
-$(shell mkdir -p $(obj)../common)
-endif
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	= $(BOARD).o \
+obj-y	= apc405.o \
 	../common/misc.o \
 	../common/auto_update.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(OBJS) $(SOBJS)
-	$(call cmd_link_o_target, $^)
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
diff --git a/board/esd/apc405/apc405.c b/board/esd/apc405/apc405.c
index f13f088d55..5cc1d0d9d6 100644
--- a/board/esd/apc405/apc405.c
+++ b/board/esd/apc405/apc405.c
@@ -17,6 +17,7 @@
 #include <mtd/cfi_flash.h>
 #include <asm/4xx_pci.h>
 #include <pci.h>
+#include <usb.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -428,7 +429,7 @@ void reset_phy(void)
 }
 
 #if defined(CONFIG_USB_OHCI_NEW) && defined(CONFIG_SYS_USB_OHCI_BOARD_INIT)
-int usb_board_init(void)
+int board_usb_init(int index, enum usb_init_type init)
 {
 	return 0;
 }
@@ -453,9 +454,8 @@ int usb_board_stop(void)
 	return 0;
 }
 
-int usb_board_init_fail(void)
+int board_usb_cleanup(int index, enum usb_init_type init)
 {
-	usb_board_stop();
-	return 0;
+	return usb_board_stop();
 }
 #endif /* defined(CONFIG_USB_OHCI) && defined(CONFIG_SYS_USB_OHCI_BOARD_INIT) */
diff --git a/board/esd/ar405/Makefile b/board/esd/ar405/Makefile
index e5caf2331a..dd54f546a6 100644
--- a/board/esd/ar405/Makefile
+++ b/board/esd/ar405/Makefile
@@ -5,27 +5,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-ifneq ($(OBJTREE),$(SRCTREE))
-$(shell mkdir -p $(obj)../common)
-endif
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	= $(BOARD).o flash.o ../common/misc.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(OBJS) $(SOBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	= ar405.o flash.o ../common/misc.o
diff --git a/board/esd/ash405/Makefile b/board/esd/ash405/Makefile
index 17dd09783b..aab8de44bc 100644
--- a/board/esd/ash405/Makefile
+++ b/board/esd/ash405/Makefile
@@ -5,29 +5,6 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-ifneq ($(OBJTREE),$(SRCTREE))
-$(shell mkdir -p $(obj)../common)
-endif
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	= $(BOARD).o flash.o \
+obj-y	= ash405.o flash.o \
 	../common/misc.o \
 	../common/esd405ep_nand.o \
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(OBJS) $(SOBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
diff --git a/board/esd/cms700/Makefile b/board/esd/cms700/Makefile
index 4ae77271ea..2bf50066c4 100644
--- a/board/esd/cms700/Makefile
+++ b/board/esd/cms700/Makefile
@@ -5,35 +5,12 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-ifneq ($(OBJTREE),$(SRCTREE))
-$(shell mkdir -p $(obj)../common/xilinx_jtag)
-endif
-
-LIB	= $(obj)lib$(BOARD).o
-
 # Objects for Xilinx JTAG programming (CPLD)
 CPLD    = ../common/xilinx_jtag/lenval.o \
 	  ../common/xilinx_jtag/micro.o \
 	  ../common/xilinx_jtag/ports.o
 
-COBJS	= $(BOARD).o flash.o \
+obj-y	= cms700.o flash.o \
 	../common/misc.o \
 	$(CPLD) \
 	../common/esd405ep_nand.o \
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(OBJS) $(SOBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
diff --git a/board/esd/common/s1d13806_640_480_8bpp.h b/board/esd/common/s1d13806_640_480_8bpp.h
deleted file mode 100644
index ddc0289b2e..0000000000
--- a/board/esd/common/s1d13806_640_480_8bpp.h
+++ /dev/null
@@ -1,120 +0,0 @@
-/*
- * Copyright (c) 2000,2001 Epson Research and Development, Inc.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- *
- * File generated by S1D13806CFG.EXE
- * Panel:  (active)   640x480 59Hz TFT Single 18-bit (PCLK=CLKI2=25.000MHz)
- * Memory: Embedded SDRAM (MCLK=CLKI=49.152MHz) (BUSCLK=33.333MHz)
- */
-
-static S1D_REGS regs_13806_640_320_16bpp[] =
-{
-	{0x0001,0x00},   /* Miscellaneous Register */
-	{0x01FC,0x00},   /* Display Mode Register */
-	{0x0004,0x18},   /* General IO Pins Configuration Register 0 */
-	{0x0005,0x00},   /* General IO Pins Configuration Register 1 */
-	{0x0008,0x18},   /* General IO Pins Control Register 0 */
-	{0x0009,0x00},   /* General IO Pins Control Register 1 */
-	{0x0010,0x00},   /* Memory Clock Configuration Register */
-	{0x0014,0x02},   /* LCD Pixel Clock Configuration Register */
-	{0x0018,0x02},   /* CRT/TV Pixel Clock Configuration Register */
-	{0x001C,0x02},   /* MediaPlug Clock Configuration Register */
-	{0x001E,0x01},   /* CPU To Memory Wait State Select Register */
-	{0x0021,0x03},   /* DRAM Refresh Rate Register */
-	{0x002A,0x00},   /* DRAM Timings Control Register 0 */
-	{0x002B,0x01},   /* DRAM Timings Control Register 1 */
-	{0x0020,0x80},   /* Memory Configuration Register */
-	{0x0030,0x25},   /* Panel Type Register */
-	{0x0031,0x00},   /* MOD Rate Register */
-	{0x0032,0x4F},   /* LCD Horizontal Display Width Register */
-	{0x0034,0x13},   /* LCD Horizontal Non-Display Period Register */
-	{0x0035,0x00},   /* TFT FPLINE Start Position Register */
-	{0x0036,0x0B},   /* TFT FPLINE Pulse Width Register */
-	{0x0038,0xDF},   /* LCD Vertical Display Height Register 0 */
-	{0x0039,0x01},   /* LCD Vertical Display Height Register 1 */
-	{0x003A,0x24},   /* LCD Vertical Non-Display Period Register */
-	{0x003B,0x00},   /* TFT FPFRAME Start Position Register */
-	{0x003C,0x01},   /* TFT FPFRAME Pulse Width Register */
-	{0x0040,0x03},   /* LCD Display Mode Register (8bpp) */
-	{0x0041,0x00},   /* LCD Miscellaneous Register */
-	{0x0042,0x00},   /* LCD Display Start Address Register 0 */
-	{0x0043,0x00},   /* LCD Display Start Address Register 1 */
-	{0x0044,0x00},   /* LCD Display Start Address Register 2 */
-	{0x0046,0x80},   /* LCD Memory Address Offset Register 0 */
-	{0x0047,0x02},   /* LCD Memory Address Offset Register 1 */
-	{0x0048,0x00},   /* LCD Pixel Panning Register */
-	{0x004A,0x00},   /* LCD Display FIFO High Threshold Control Register */
-	{0x004B,0x00},   /* LCD Display FIFO Low Threshold Control Register */
-	{0x0050,0x4F},   /* CRT/TV Horizontal Display Width Register */
-	{0x0052,0x13},   /* CRT/TV Horizontal Non-Display Period Register */
-	{0x0053,0x01},   /* CRT/TV HRTC Start Position Register */
-	{0x0054,0x0B},   /* CRT/TV HRTC Pulse Width Register */
-	{0x0056,0xDF},   /* CRT/TV Vertical Display Height Register 0 */
-	{0x0057,0x01},   /* CRT/TV Vertical Display Height Register 1 */
-	{0x0058,0x2B},   /* CRT/TV Vertical Non-Display Period Register */
-	{0x0059,0x09},   /* CRT/TV VRTC Start Position Register */
-	{0x005A,0x01},   /* CRT/TV VRTC Pulse Width Register */
-	{0x005B,0x10},   /* TV Output Control Register */
-	{0x0060,0x05},   /* CRT/TV Display Mode Register */
-	{0x0062,0x00},   /* CRT/TV Display Start Address Register 0 */
-	{0x0063,0x00},   /* CRT/TV Display Start Address Register 1 */
-	{0x0064,0x00},   /* CRT/TV Display Start Address Register 2 */
-	{0x0066,0x80},   /* CRT/TV Memory Address Offset Register 0 */
-	{0x0067,0x02},   /* CRT/TV Memory Address Offset Register 1 */
-	{0x0068,0x00},   /* CRT/TV Pixel Panning Register */
-	{0x006A,0x00},   /* CRT/TV Display FIFO High Threshold Control Register */
-	{0x006B,0x00},   /* CRT/TV Display FIFO Low Threshold Control Register */
-	{0x0070,0x00},   /* LCD Ink/Cursor Control Register */
-	{0x0071,0x01},   /* LCD Ink/Cursor Start Address Register */
-	{0x0072,0x00},   /* LCD Cursor X Position Register 0 */
-	{0x0073,0x00},   /* LCD Cursor X Position Register 1 */
-	{0x0074,0x00},   /* LCD Cursor Y Position Register 0 */
-	{0x0075,0x00},   /* LCD Cursor Y Position Register 1 */
-	{0x0076,0x00},   /* LCD Ink/Cursor Blue Color 0 Register */
-	{0x0077,0x00},   /* LCD Ink/Cursor Green Color 0 Register */
-	{0x0078,0x00},   /* LCD Ink/Cursor Red Color 0 Register */
-	{0x007A,0x1F},   /* LCD Ink/Cursor Blue Color 1 Register */
-	{0x007B,0x3F},   /* LCD Ink/Cursor Green Color 1 Register */
-	{0x007C,0x1F},   /* LCD Ink/Cursor Red Color 1 Register */
-	{0x007E,0x00},   /* LCD Ink/Cursor FIFO Threshold Register */
-	{0x0080,0x00},   /* CRT/TV Ink/Cursor Control Register */
-	{0x0081,0x01},   /* CRT/TV Ink/Cursor Start Address Register */
-	{0x0082,0x00},   /* CRT/TV Cursor X Position Register 0 */
-	{0x0083,0x00},   /* CRT/TV Cursor X Position Register 1 */
-	{0x0084,0x00},   /* CRT/TV Cursor Y Position Register 0 */
-	{0x0085,0x00},   /* CRT/TV Cursor Y Position Register 1 */
-	{0x0086,0x00},   /* CRT/TV Ink/Cursor Blue Color 0 Register */
-	{0x0087,0x00},   /* CRT/TV Ink/Cursor Green Color 0 Register */
-	{0x0088,0x00},   /* CRT/TV Ink/Cursor Red Color 0 Register */
-	{0x008A,0x1F},   /* CRT/TV Ink/Cursor Blue Color 1 Register */
-	{0x008B,0x3F},   /* CRT/TV Ink/Cursor Green Color 1 Register */
-	{0x008C,0x1F},   /* CRT/TV Ink/Cursor Red Color 1 Register */
-	{0x008E,0x00},   /* CRT/TV Ink/Cursor FIFO Threshold Register */
-	{0x0100,0x00},   /* BitBlt Control Register 0 */
-	{0x0101,0x00},   /* BitBlt Control Register 1 */
-	{0x0102,0x00},   /* BitBlt ROP Code/Color Expansion Register */
-	{0x0103,0x00},   /* BitBlt Operation Register */
-	{0x0104,0x00},   /* BitBlt Source Start Address Register 0 */
-	{0x0105,0x00},   /* BitBlt Source Start Address Register 1 */
-	{0x0106,0x00},   /* BitBlt Source Start Address Register 2 */
-	{0x0108,0x00},   /* BitBlt Destination Start Address Register 0 */
-	{0x0109,0x00},   /* BitBlt Destination Start Address Register 1 */
-	{0x010A,0x00},   /* BitBlt Destination Start Address Register 2 */
-	{0x010C,0x00},   /* BitBlt Memory Address Offset Register 0 */
-	{0x010D,0x00},   /* BitBlt Memory Address Offset Register 1 */
-	{0x0110,0x00},   /* BitBlt Width Register 0 */
-	{0x0111,0x00},   /* BitBlt Width Register 1 */
-	{0x0112,0x00},   /* BitBlt Height Register 0 */
-	{0x0113,0x00},   /* BitBlt Height Register 1 */
-	{0x0114,0x00},   /* BitBlt Background Color Register 0 */
-	{0x0115,0x00},   /* BitBlt Background Color Register 1 */
-	{0x0118,0x00},   /* BitBlt Foreground Color Register 0 */
-	{0x0119,0x00},   /* BitBlt Foreground Color Register 1 */
-	{0x01E0,0x00},   /* Look-Up Table Mode Register */
-	{0x01E2,0x00},   /* Look-Up Table Address Register */
-	{0x01F0,0x10},   /* Power Save Configuration Register */
-	{0x01F1,0x00},   /* Power Save Status Register */
-	{0x01F4,0x00},   /* CPU-to-Memory Access Watchdog Timer Register */
-	{0x01FC,0x01},   /* Display Mode Register */
-};
diff --git a/board/esd/cpci2dp/Makefile b/board/esd/cpci2dp/Makefile
index a6edac0c6c..ce2c6dd912 100644
--- a/board/esd/cpci2dp/Makefile
+++ b/board/esd/cpci2dp/Makefile
@@ -5,27 +5,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-ifneq ($(OBJTREE),$(SRCTREE))
-$(shell mkdir -p $(obj)../common)
-endif
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	= $(BOARD).o flash.o ../common/misc.o ../common/cmd_loadpci.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(OBJS) $(SOBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	= cpci2dp.o flash.o ../common/misc.o ../common/cmd_loadpci.o
diff --git a/board/esd/cpci405/Makefile b/board/esd/cpci405/Makefile
index 6868e6886a..b140571796 100644
--- a/board/esd/cpci405/Makefile
+++ b/board/esd/cpci405/Makefile
@@ -5,28 +5,5 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-ifneq ($(OBJTREE),$(SRCTREE))
-$(shell mkdir -p $(obj)../common)
-endif
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	= $(BOARD).o flash.o ../common/misc.o ../common/auto_update.o
-COBJS	+= ../common/cmd_loadpci.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(OBJS) $(SOBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	= cpci405.o flash.o ../common/misc.o ../common/auto_update.o
+obj-y	+= ../common/cmd_loadpci.o
diff --git a/board/esd/cpci5200/Makefile b/board/esd/cpci5200/Makefile
index 80eb23d6f4..8421f54869 100644
--- a/board/esd/cpci5200/Makefile
+++ b/board/esd/cpci5200/Makefile
@@ -5,33 +5,10 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-# ifneq ($(OBJTREE),$(SRCTREE))
-# $(shell mkdir -p $(obj)../common/xilinx_jtag)
-# endif
-
-LIB	= $(obj)lib$(BOARD).o
-
 # Objects for Xilinx JTAG programming (CPLD)
 # CPLD  = ../common/xilinx_jtag/lenval.o \
 #	  ../common/xilinx_jtag/micro.o \
 #	  ../common/xilinx_jtag/ports.o
 
-# COBJS	= $(BOARD).o flash.o $(CPLD)
-COBJS	= $(BOARD).o strataflash.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+# obj-y	= cpci5200.o flash.o $(CPLD)
+obj-y	= cpci5200.o strataflash.o
diff --git a/board/esd/cpci750/Makefile b/board/esd/cpci750/Makefile
index 0be10fe1d4..a3300c9f4a 100644
--- a/board/esd/cpci750/Makefile
+++ b/board/esd/cpci750/Makefile
@@ -8,31 +8,7 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-ifneq ($(OBJTREE),$(SRCTREE))
-$(shell mkdir -p $(obj)../../Marvell/common)
-endif
-
-LIB	= $(obj)lib$(BOARD).o
-
-SOBJS	= misc.o
-
-COBJS	= $(BOARD).o serial.o ../../Marvell/common/memory.o pci.o \
+obj-y	= misc.o
+obj-y	+= cpci750.o serial.o ../../Marvell/common/memory.o pci.o \
 	  mv_eth.o  mpsc.o i2c.o \
 	  sdram_init.o ide.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
-	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
diff --git a/board/esd/cpci750/serial.c b/board/esd/cpci750/serial.c
index f42510545c..6c2cf215ac 100644
--- a/board/esd/cpci750/serial.c
+++ b/board/esd/cpci750/serial.c
@@ -23,7 +23,6 @@
 #include <linux/compiler.h>
 
 #include "../../Marvell/include/memory.h"
-#include "serial.h"
 
 #include "mpsc.h"
 
diff --git a/board/esd/cpci750/serial.h b/board/esd/cpci750/serial.h
deleted file mode 100644
index 264e2d236e..0000000000
--- a/board/esd/cpci750/serial.h
+++ /dev/null
@@ -1,73 +0,0 @@
-/*
- * (C) Copyright 2001
- * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
- *
- * modified for marvell db64360 eval board by
- * Ingo Assmus <ingo.assmus@keymile.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-/* serial.h - mostly useful for DUART serial_init in serial.c */
-
-#ifndef __SERIAL_H__
-#define __SERIAL_H__
-
-#if 0
-
-#define B230400         1
-#define B115200         2
-#define B57600          4
-#define B38400          82
-#define B19200          163
-#define B9600           24
-#define B4800           651
-#define B2400           1302
-#define B1200           2604
-#define B600            5208
-#define B300            10417
-#define B150            20833
-#define B110            28409
-#define BDEFAULT        B115200
-
-				/* this stuff is important to initialize
-				the DUART channels */
-
-#define	Scale		0x01L		/* distance between port addresses */
-#define	COM1		0x000003f8		/* Keyboard */
-#define COM2		0x000002f8		/* Host */
-
-
-/* Port Definitions relative to base COM port addresses */
-#define DataIn	(0x00*Scale)	/* data input port */
-#define DataOut	(0x00*Scale)	/* data output port */
-#define BaudLsb	(0x00*Scale)	/* baud rate divisor least significant byte */
-#define BaudMsb	(0x01*Scale)	/* baud rate divisor most significant byte */
-#define	Ier	(0x01*Scale)	/* interrupt enable register */
-#define	Iir	(0x02*Scale)	/* interrupt identification register */
-#define	Lcr	(0x03*Scale)	/* line control register */
-#define	Mcr	(0x04*Scale)	/* modem control register */
-#define	Lsr	(0x05*Scale)	/* line status register */
-#define	Msr	(0x06*Scale)	/* modem status register */
-
-/* Bit Definitions for above ports */
-#define LcrDlab	0x80	/* b7:	 enable baud rate divisor registers */
-#define	LcrDflt	0x03	/* b6-0: no parity, 1 stop, 8 data */
-
-#define	McrRts	0x02	/* b1:	request to send (I am ready to xmit) */
-#define	McrDtr	0x01	/* b0:	data terminal ready (I am alive ready to rcv) */
-#define	McrDflt	(McrRts|McrDtr)
-
-#define LsrTxD	0x6000	/* b5: transmit holding register empty (i.e. xmit OK!)*/
-			/* b6: transmitter empty */
-#define LsrRxD	0x0100	/* b0: received data ready (i.e. got a byte!) */
-
-#define	MsrRi	0x0040	/* b6: ring indicator (other guy is ready to rcv) */
-#define	MsrDsr	0x0020	/* b5: data set ready (other guy is alive ready to rcv */
-#define	MsrCts	0x0010	/* b4: clear to send (other guy is ready to rcv) */
-
-#define IerRda	0xf	/* b0: Enable received data available interrupt */
-
-#endif
-
-#endif /* __SERIAL_H__ */
diff --git a/board/esd/cpciiser4/Makefile b/board/esd/cpciiser4/Makefile
index e5caf2331a..b8d6bea6dc 100644
--- a/board/esd/cpciiser4/Makefile
+++ b/board/esd/cpciiser4/Makefile
@@ -5,27 +5,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-ifneq ($(OBJTREE),$(SRCTREE))
-$(shell mkdir -p $(obj)../common)
-endif
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	= $(BOARD).o flash.o ../common/misc.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(OBJS) $(SOBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	= cpciiser4.o flash.o ../common/misc.o
diff --git a/board/esd/dasa_sim/Makefile b/board/esd/dasa_sim/Makefile
index 3190a115f0..eb9f5f86d0 100644
--- a/board/esd/dasa_sim/Makefile
+++ b/board/esd/dasa_sim/Makefile
@@ -1,4 +1,3 @@
-
 #
 # (C) Copyright 2000-2006
 # Wolfgang Denk, DENX Software Engineering, wd@denx.de.
@@ -6,27 +5,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-ifneq ($(OBJTREE),$(SRCTREE))
-$(shell mkdir -p $(obj)../common)
-endif
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	= $(BOARD).o flash.o cmd_dasa_sim.o eeprom.o ../common/pci.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	= dasa_sim.o flash.o cmd_dasa_sim.o eeprom.o ../common/pci.o
diff --git a/board/esd/dp405/Makefile b/board/esd/dp405/Makefile
index 0fd6fe53cb..cfcfb66a15 100644
--- a/board/esd/dp405/Makefile
+++ b/board/esd/dp405/Makefile
@@ -5,32 +5,9 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-ifneq ($(OBJTREE),$(SRCTREE))
-$(shell mkdir -p $(obj)../common/xilinx_jtag)
-endif
-
-LIB	= $(obj)lib$(BOARD).o
-
 # Objects for Xilinx JTAG programming (CPLD)
 CPLD    = ../common/xilinx_jtag/lenval.o \
 	  ../common/xilinx_jtag/micro.o \
 	  ../common/xilinx_jtag/ports.o
 
-COBJS	= $(BOARD).o flash.o ../common/misc.o $(CPLD)
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(OBJS) $(SOBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	= dp405.o flash.o ../common/misc.o $(CPLD)
diff --git a/board/esd/du405/Makefile b/board/esd/du405/Makefile
index e5caf2331a..7914eab355 100644
--- a/board/esd/du405/Makefile
+++ b/board/esd/du405/Makefile
@@ -5,27 +5,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-ifneq ($(OBJTREE),$(SRCTREE))
-$(shell mkdir -p $(obj)../common)
-endif
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	= $(BOARD).o flash.o ../common/misc.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(OBJS) $(SOBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	= du405.o flash.o ../common/misc.o
diff --git a/board/esd/du440/Makefile b/board/esd/du440/Makefile
index 7ccd9a8574..ef41d94ac9 100644
--- a/board/esd/du440/Makefile
+++ b/board/esd/du440/Makefile
@@ -5,27 +5,5 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	= $(BOARD).o
-SOBJS	= init.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-all:	$(LIB) $(SOBJS)
-
-$(LIB):	$(OBJS)
-	$(call cmd_link_o_target, $^)
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	= du440.o
+extra-y	+= init.o
diff --git a/board/esd/hh405/Makefile b/board/esd/hh405/Makefile
index fdae010b1b..fba21a3ae2 100644
--- a/board/esd/hh405/Makefile
+++ b/board/esd/hh405/Makefile
@@ -5,30 +5,7 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-ifneq ($(OBJTREE),$(SRCTREE))
-$(shell mkdir -p $(obj)../common)
-endif
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	= $(BOARD).o flash.o \
+obj-y	= hh405.o flash.o \
 	../common/misc.o \
 	../common/esd405ep_nand.o \
 	../common/auto_update.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(OBJS) $(SOBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
diff --git a/board/esd/hub405/Makefile b/board/esd/hub405/Makefile
index 17dd09783b..99e18b567f 100644
--- a/board/esd/hub405/Makefile
+++ b/board/esd/hub405/Makefile
@@ -5,29 +5,6 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-ifneq ($(OBJTREE),$(SRCTREE))
-$(shell mkdir -p $(obj)../common)
-endif
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	= $(BOARD).o flash.o \
+obj-y	= hub405.o flash.o \
 	../common/misc.o \
 	../common/esd405ep_nand.o \
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(OBJS) $(SOBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
diff --git a/board/esd/mecp5123/Makefile b/board/esd/mecp5123/Makefile
index f78fe13d35..f5ebb0144f 100644
--- a/board/esd/mecp5123/Makefile
+++ b/board/esd/mecp5123/Makefile
@@ -4,25 +4,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS-y	:= $(BOARD).o
-
-COBJS	:= $(COBJS-y)
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	:= mecp5123.o
diff --git a/board/esd/mecp5200/Makefile b/board/esd/mecp5200/Makefile
index c85223385b..3d66c9f53d 100644
--- a/board/esd/mecp5200/Makefile
+++ b/board/esd/mecp5200/Makefile
@@ -1,4 +1,3 @@
-
 #
 # (C) Copyright 2003-2006
 # Wolfgang Denk, DENX Software Engineering, wd@denx.de.
@@ -6,24 +5,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	= $(BOARD).o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	= mecp5200.o
diff --git a/board/esd/meesc/Makefile b/board/esd/meesc/Makefile
index a7a16fe0a2..5d1673820d 100644
--- a/board/esd/meesc/Makefile
+++ b/board/esd/meesc/Makefile
@@ -9,25 +9,5 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS-y	+= $(BOARD).o
-COBJS-$(CONFIG_HAS_DATAFLASH) += partition.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS-y))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
-	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	+= meesc.o
+obj-$(CONFIG_HAS_DATAFLASH) += partition.o
diff --git a/board/esd/meesc/meesc.c b/board/esd/meesc/meesc.c
index 9bf6739081..c5994e0a4a 100644
--- a/board/esd/meesc/meesc.c
+++ b/board/esd/meesc/meesc.c
@@ -12,6 +12,7 @@
 
 #include <common.h>
 #include <asm/io.h>
+#include <asm/gpio.h>
 #include <asm/arch/at91sam9_smc.h>
 #include <asm/arch/at91_common.h>
 #include <asm/arch/at91_pmc.h>
@@ -74,10 +75,10 @@ static void meesc_nand_hw_init(void)
 		&smc->cs[3].mode);
 
 	/* Configure RDY/BSY */
-	at91_set_pio_input(CONFIG_SYS_NAND_READY_PIN, 1);
+	gpio_direction_input(CONFIG_SYS_NAND_READY_PIN);
 
 	/* Enable NandFlash */
-	at91_set_pio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
+	gpio_direction_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
 }
 #endif /* CONFIG_CMD_NAND */
 
diff --git a/board/esd/ocrtc/Makefile b/board/esd/ocrtc/Makefile
index b8452582be..44b7d5d072 100644
--- a/board/esd/ocrtc/Makefile
+++ b/board/esd/ocrtc/Makefile
@@ -5,27 +5,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-ifneq ($(OBJTREE),$(SRCTREE))
-$(shell mkdir -p $(obj)../common)
-endif
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	= $(BOARD).o flash.o ../common/misc.o cmd_ocrtc.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(OBJS) $(SOBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	= ocrtc.o flash.o ../common/misc.o cmd_ocrtc.o
diff --git a/board/esd/otc570/Makefile b/board/esd/otc570/Makefile
index 53179131c2..740bb0a282 100644
--- a/board/esd/otc570/Makefile
+++ b/board/esd/otc570/Makefile
@@ -9,25 +9,5 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS-y				+= $(BOARD).o
-COBJS-$(CONFIG_HAS_DATAFLASH)	+= partition.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS-y))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
-	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y				+= otc570.o
+obj-$(CONFIG_HAS_DATAFLASH)	+= partition.o
diff --git a/board/esd/otc570/otc570.c b/board/esd/otc570/otc570.c
index acc1b31b70..4751d0a9e9 100644
--- a/board/esd/otc570/otc570.c
+++ b/board/esd/otc570/otc570.c
@@ -12,6 +12,7 @@
 
 #include <common.h>
 #include <asm/io.h>
+#include <asm/gpio.h>
 #include <asm/arch/at91sam9_smc.h>
 #include <asm/arch/at91_common.h>
 #include <asm/arch/at91_pmc.h>
@@ -82,10 +83,10 @@ static void otc570_nand_hw_init(void)
 		&smc->cs[3].mode);
 
 	/* Configure RDY/BSY */
-	at91_set_pio_input(CONFIG_SYS_NAND_READY_PIN, 1);
+	gpio_direction_input(CONFIG_SYS_NAND_READY_PIN);
 
 	/* Enable NandFlash */
-	at91_set_pio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
+	gpio_direction_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
 }
 #endif /* CONFIG_CMD_NAND */
 
diff --git a/board/esd/pci405/Makefile b/board/esd/pci405/Makefile
index 9f01c56786..9e659c796c 100644
--- a/board/esd/pci405/Makefile
+++ b/board/esd/pci405/Makefile
@@ -5,29 +5,5 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-ifneq ($(OBJTREE),$(SRCTREE))
-$(shell mkdir -p $(obj)../common)
-endif
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	= $(BOARD).o flash.o ../common/misc.o cmd_pci405.o
-SOBJS	= writeibm.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(OBJS) $(SOBJS)
-#	$(call cmd_link_o_target, $(OBJS))
-	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	= pci405.o flash.o ../common/misc.o cmd_pci405.o
+obj-y	+= writeibm.o
diff --git a/board/esd/pf5200/Makefile b/board/esd/pf5200/Makefile
index 121f772806..a54289c073 100644
--- a/board/esd/pf5200/Makefile
+++ b/board/esd/pf5200/Makefile
@@ -1,4 +1,3 @@
-
 #
 # (C) Copyright 2003-2006
 # Wolfgang Denk, DENX Software Engineering, wd@denx.de.
@@ -6,33 +5,10 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-# ifneq ($(OBJTREE),$(SRCTREE))
-# $(shell mkdir -p $(obj)../common/xilinx_jtag)
-# endif
-
-LIB	= $(obj)lib$(BOARD).o
-
 # Objects for Xilinx JTAG programming (CPLD)
 # CPLD  = ../common/xilinx_jtag/lenval.o \
 #	  ../common/xilinx_jtag/micro.o \
 #	  ../common/xilinx_jtag/ports.o
 
-# COBJS	= $(BOARD).o flash.o $(CPLD)
-COBJS	= $(BOARD).o flash.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+# obj-y	= pf5200.o flash.o $(CPLD)
+obj-y	= pf5200.o flash.o
diff --git a/board/esd/plu405/Makefile b/board/esd/plu405/Makefile
index 17dd09783b..6ffae677b1 100644
--- a/board/esd/plu405/Makefile
+++ b/board/esd/plu405/Makefile
@@ -5,29 +5,6 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-ifneq ($(OBJTREE),$(SRCTREE))
-$(shell mkdir -p $(obj)../common)
-endif
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	= $(BOARD).o flash.o \
+obj-y	= plu405.o flash.o \
 	../common/misc.o \
 	../common/esd405ep_nand.o \
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(OBJS) $(SOBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
diff --git a/board/esd/pmc405/Makefile b/board/esd/pmc405/Makefile
index 225974d986..ad98207f3e 100644
--- a/board/esd/pmc405/Makefile
+++ b/board/esd/pmc405/Makefile
@@ -5,32 +5,9 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-ifneq ($(OBJTREE),$(SRCTREE))
-$(shell mkdir -p $(obj)../common/xilinx_jtag)
-endif
-
-LIB	= $(obj)lib$(BOARD).o
-
 # Objects for Xilinx JTAG programming (CPLD)
 CPLD    = ../common/xilinx_jtag/lenval.o \
 	  ../common/xilinx_jtag/micro.o \
 	  ../common/xilinx_jtag/ports.o
 
-COBJS	= $(BOARD).o ../common/misc.o ../common/cmd_loadpci.o $(CPLD)
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(OBJS) $(SOBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	= pmc405.o ../common/misc.o ../common/cmd_loadpci.o $(CPLD)
diff --git a/board/esd/pmc405de/Makefile b/board/esd/pmc405de/Makefile
index 997f07ec11..b3f6dcd1e7 100644
--- a/board/esd/pmc405de/Makefile
+++ b/board/esd/pmc405de/Makefile
@@ -5,30 +5,6 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-ifneq ($(OBJTREE),$(SRCTREE))
-$(shell mkdir -p $(obj)../common)
-endif
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS-y	= $(BOARD).o
-COBJS-$(CONFIG_CMD_CHIP_CONFIG) += chip_config.o
-COBJS-y += ../common/cmd_loadpci.o
-
-COBJS	:= $(COBJS-y)
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(OBJS) $(SOBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	= pmc405de.o
+obj-$(CONFIG_CMD_CHIP_CONFIG) += chip_config.o
+obj-y += ../common/cmd_loadpci.o
diff --git a/board/esd/pmc440/Makefile b/board/esd/pmc440/Makefile
index 6d6690a221..708e9d138e 100644
--- a/board/esd/pmc440/Makefile
+++ b/board/esd/pmc440/Makefile
@@ -5,32 +5,6 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-ifneq ($(OBJTREE),$(SRCTREE))
-$(shell mkdir -p $(obj)../common)
-endif
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	= $(BOARD).o cmd_pmc440.o sdram.o fpga.o \
+obj-y	= pmc440.o cmd_pmc440.o sdram.o fpga.o \
 	../common/cmd_loadpci.o
-
-SOBJS	= init.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-all:	$(LIB) $(SOBJS)
-
-$(LIB):	$(OBJS)
-	$(call cmd_link_o_target, $^)
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+extra-y	+= init.o
diff --git a/board/esd/pmc440/init.S b/board/esd/pmc440/init.S
index cc8030b5e5..1f26fad147 100644
--- a/board/esd/pmc440/init.S
+++ b/board/esd/pmc440/init.S
@@ -27,11 +27,7 @@ tlbtab:
 	 * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the
 	 * speed up boot process. It is patched after relocation to enable SA_I
 	 */
-#ifndef CONFIG_NAND_SPL
 	tlbentry( CONFIG_SYS_BOOT_BASE_ADDR, SZ_256M, CONFIG_SYS_BOOT_BASE_ADDR, 1, AC_RWX | SA_G )
-#else
-	tlbentry( CONFIG_SYS_NAND_BOOT_SPL_SRC, SZ_4K, CONFIG_SYS_NAND_BOOT_SPL_SRC, 1, AC_RWX | SA_G )
-#endif
 
 	/* TLB entries for DDR2 SDRAM are generated dynamically */
 
@@ -71,31 +67,3 @@ tlbtab:
 
 	/* TODO:  what about high IO space */
 	tlbtab_end
-
-#if defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
-	/*
-	 * For NAND booting the first TLB has to be reconfigured to full size
-	 * and with caching disabled after running from RAM!
-	 */
-#define TLB00	TLB0(CONFIG_SYS_BOOT_BASE_ADDR, SZ_256M)
-#define TLB01	TLB1(CONFIG_SYS_BOOT_BASE_ADDR, 1)
-#define TLB02	TLB2(AC_RWX | SA_IG)
-
-	.globl	reconfig_tlb0
-reconfig_tlb0:
-	sync
-	isync
-	addi	r4,r0,0x0000		/* TLB entry #0 */
-	lis	r5,TLB00@h
-	ori	r5,r5,TLB00@l
-	tlbwe	r5,r4,0x0000		/* Save it out */
-	lis	r5,TLB01@h
-	ori	r5,r5,TLB01@l
-	tlbwe	r5,r4,0x0001		/* Save it out */
-	lis	r5,TLB02@h
-	ori	r5,r5,TLB02@l
-	tlbwe	r5,r4,0x0002		/* Save it out */
-	sync
-	isync
-	blr
-#endif
diff --git a/board/esd/pmc440/pmc440.c b/board/esd/pmc440/pmc440.c
index 549b3b73ce..e86996c55f 100644
--- a/board/esd/pmc440/pmc440.c
+++ b/board/esd/pmc440/pmc440.c
@@ -27,6 +27,7 @@
 #endif
 #include <serial.h>
 #include <asm/4xx_pci.h>
+#include <usb.h>
 
 #include "fpga.h"
 #include "pmc440.h"
@@ -228,19 +229,11 @@ int misc_init_r(void)
 	gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
 	gd->bd->bi_flashoffset = 0;
 
-#if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
-	mtdcr(EBC0_CFGADDR, PB2CR);
-#else
 	mtdcr(EBC0_CFGADDR, PB0CR);
-#endif
 	pbcr = mfdcr(EBC0_CFGDATA);
 	size_val = ffs(gd->bd->bi_flashsize) - 21;
 	pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17);
-#if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
-	mtdcr(EBC0_CFGADDR, PB2CR);
-#else
 	mtdcr(EBC0_CFGADDR, PB0CR);
-#endif
 	mtdcr(EBC0_CFGDATA, pbcr);
 
 	/*
@@ -821,7 +814,7 @@ int bootstrap_eeprom_read (unsigned dev_addr, unsigned offset,
 }
 
 #if defined(CONFIG_USB_OHCI_NEW) && defined(CONFIG_SYS_USB_OHCI_BOARD_INIT)
-int usb_board_init(void)
+int board_usb_init(int index, enum usb_init_type init)
 {
 	char *act = getenv("usbact");
 	int i;
@@ -845,10 +838,9 @@ int usb_board_stop(void)
 	return 0;
 }
 
-int usb_board_init_fail(void)
+int board_usb_cleanup(int index, enum usb_init_type init)
 {
-	usb_board_stop();
-	return 0;
+	return usb_board_stop();
 }
 #endif /* defined(CONFIG_USB_OHCI) && defined(CONFIG_SYS_USB_OHCI_BOARD_INIT) */
 
diff --git a/board/esd/tasreg/Makefile b/board/esd/tasreg/Makefile
index 871865b6ee..46f25504d6 100644
--- a/board/esd/tasreg/Makefile
+++ b/board/esd/tasreg/Makefile
@@ -5,24 +5,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	= $(BOARD).o flash.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	= tasreg.o flash.o
diff --git a/board/esd/vme8349/Makefile b/board/esd/vme8349/Makefile
index 4dd47b7cdc..fa11d5d108 100644
--- a/board/esd/vme8349/Makefile
+++ b/board/esd/vme8349/Makefile
@@ -7,26 +7,5 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS-y += $(BOARD).o caddy.o
-COBJS-$(CONFIG_PCI) += pci.o
-
-COBJS	:= $(COBJS-y)
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y += vme8349.o caddy.o
+obj-$(CONFIG_PCI) += pci.o
diff --git a/board/esd/voh405/Makefile b/board/esd/voh405/Makefile
index 17dd09783b..3d82399ed1 100644
--- a/board/esd/voh405/Makefile
+++ b/board/esd/voh405/Makefile
@@ -5,29 +5,6 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-ifneq ($(OBJTREE),$(SRCTREE))
-$(shell mkdir -p $(obj)../common)
-endif
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	= $(BOARD).o flash.o \
+obj-y	= voh405.o flash.o \
 	../common/misc.o \
 	../common/esd405ep_nand.o \
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(OBJS) $(SOBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
diff --git a/board/esd/vom405/Makefile b/board/esd/vom405/Makefile
index 0fd6fe53cb..7cf5c0224c 100644
--- a/board/esd/vom405/Makefile
+++ b/board/esd/vom405/Makefile
@@ -5,32 +5,9 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-ifneq ($(OBJTREE),$(SRCTREE))
-$(shell mkdir -p $(obj)../common/xilinx_jtag)
-endif
-
-LIB	= $(obj)lib$(BOARD).o
-
 # Objects for Xilinx JTAG programming (CPLD)
 CPLD    = ../common/xilinx_jtag/lenval.o \
 	  ../common/xilinx_jtag/micro.o \
 	  ../common/xilinx_jtag/ports.o
 
-COBJS	= $(BOARD).o flash.o ../common/misc.o $(CPLD)
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(OBJS) $(SOBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	= vom405.o flash.o ../common/misc.o $(CPLD)
diff --git a/board/esd/wuh405/Makefile b/board/esd/wuh405/Makefile
index 17dd09783b..b9beeffc57 100644
--- a/board/esd/wuh405/Makefile
+++ b/board/esd/wuh405/Makefile
@@ -5,29 +5,6 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-ifneq ($(OBJTREE),$(SRCTREE))
-$(shell mkdir -p $(obj)../common)
-endif
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	= $(BOARD).o flash.o \
+obj-y	= wuh405.o flash.o \
 	../common/misc.o \
 	../common/esd405ep_nand.o \
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(OBJS) $(SOBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
diff --git a/board/esg/ima3-mx53/Makefile b/board/esg/ima3-mx53/Makefile
index f2cb873913..afb8925c74 100644
--- a/board/esg/ima3-mx53/Makefile
+++ b/board/esg/ima3-mx53/Makefile
@@ -6,23 +6,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	:= ima3-mx53.o
-
-SRCS	:= $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	:= ima3-mx53.o
diff --git a/board/espt/Makefile b/board/espt/Makefile
index 107e544774..8a8a2c992b 100644
--- a/board/espt/Makefile
+++ b/board/espt/Makefile
@@ -7,25 +7,5 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	:= espt.o
-SOBJS	:= lowlevel_init.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(OBJS) $(SOBJS)
-	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	:= espt.o
+obj-y	+= lowlevel_init.o
diff --git a/board/esteem192e/Makefile b/board/esteem192e/Makefile
index 871865b6ee..55d80b6874 100644
--- a/board/esteem192e/Makefile
+++ b/board/esteem192e/Makefile
@@ -5,24 +5,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	= $(BOARD).o flash.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	= esteem192e.o flash.o
diff --git a/board/esteem192e/u-boot.lds b/board/esteem192e/u-boot.lds
index 87642d6b40..59a86bfdc0 100644
--- a/board/esteem192e/u-boot.lds
+++ b/board/esteem192e/u-boot.lds
@@ -18,8 +18,8 @@ SECTIONS
 
     arch/powerpc/cpu/mpc8xx/start.o	(.text*)
     arch/powerpc/cpu/mpc8xx/traps.o	(.text*)
-    net/libnet.o			(.text*)
-    board/esteem192e/libesteem192e.o	(.text*)
+    net/built-in.o			(.text*)
+    board/esteem192e/built-in.o		(.text*)
 
     . = env_offset;
     common/env_embedded.o		(.text*)
diff --git a/board/etin/debris/Makefile b/board/etin/debris/Makefile
index d7da042c05..2e74823ea6 100644
--- a/board/etin/debris/Makefile
+++ b/board/etin/debris/Makefile
@@ -5,24 +5,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS =  $(BOARD).o flash.o phantom.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y =  debris.o flash.o phantom.o
diff --git a/board/etin/debris/speed.h b/board/etin/debris/speed.h
deleted file mode 100644
index f1b10bf25e..0000000000
--- a/board/etin/debris/speed.h
+++ /dev/null
@@ -1,38 +0,0 @@
-/*
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-/*-----------------------------------------------------------------------
- * Timer value for timer 2, ICLK = 10
- *
- * SPEED_FCOUNT2 =  GCLK / (16 * (TIMER_TMR_PS + 1))
- * SPEED_TMR3_PS = (GCLK / (16 * SPEED_FCOUNT3)) - 1
- *
- * SPEED_FCOUNT2	timer 2 counting frequency
- * GCLK			CPU clock
- * SPEED_TMR2_PS	prescaler
- */
-#define SPEED_TMR2_PS	(250 - 1)	/* divide by 250	*/
-
-/*-----------------------------------------------------------------------
- * Timer value for PIT
- *
- * PIT_TIME = SPEED_PITC / PITRTCLK
- * PITRTCLK = 8192
- */
-#define SPEED_PITC	(82 << 16)	/* start counting from 82	*/
-
-/*
- * The new value for PTA is calculated from
- *
- *	PTA = (gclk * Trefresh) / (2 ^ (2 * DFBRG) * PTP * NCS)
- *
- * gclk		CPU clock (not bus clock !)
- * Trefresh	Refresh cycle * 4 (four word bursts used)
- * DFBRG	For normal mode (no clock reduction) always 0
- * PTP		Prescaler (already adjusted for no. of banks and 4K / 8K refresh)
- * NCS		Number of SDRAM banks (chip selects) on this UPM.
- */
diff --git a/board/etin/kvme080/Makefile b/board/etin/kvme080/Makefile
index c0271d0d60..d1b6f30440 100644
--- a/board/etin/kvme080/Makefile
+++ b/board/etin/kvme080/Makefile
@@ -5,24 +5,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	= $(BOARD).o multiverse.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	= kvme080.o multiverse.o
diff --git a/board/eukrea/cpu9260/Makefile b/board/eukrea/cpu9260/Makefile
index bd89fe1f49..e34792ac42 100644
--- a/board/eukrea/cpu9260/Makefile
+++ b/board/eukrea/cpu9260/Makefile
@@ -13,25 +13,5 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS-y += $(BOARD).o
-COBJS-y += led.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS-y) $(SOBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y += cpu9260.o
+obj-y += led.o
diff --git a/board/eukrea/cpu9260/cpu9260.c b/board/eukrea/cpu9260/cpu9260.c
index 5e1524e07b..01ecccb8c9 100644
--- a/board/eukrea/cpu9260/cpu9260.c
+++ b/board/eukrea/cpu9260/cpu9260.c
@@ -12,12 +12,12 @@
 
 #include <common.h>
 #include <asm/io.h>
+#include <asm/gpio.h>
 #include <asm/arch/at91sam9260.h>
 #include <asm/arch/at91sam9_smc.h>
 #include <asm/arch/at91_common.h>
 #include <asm/arch/at91_matrix.h>
 #include <asm/arch/at91_pmc.h>
-#include <asm/arch/at91_rstc.h>
 #include <asm/arch/at91_pio.h>
 #include <asm/arch/clk.h>
 #include <asm/arch/hardware.h>
@@ -79,39 +79,24 @@ static void cpu9260_nand_hw_init(void)
 	writel(1 << ATMEL_ID_PIOC, &pmc->pcer);
 
 	/* Configure RDY/BSY */
-	at91_set_pio_input(CONFIG_SYS_NAND_READY_PIN, 1);
+	gpio_direction_input(CONFIG_SYS_NAND_READY_PIN);
 
 	/* Enable NandFlash */
-	at91_set_pio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
+	gpio_direction_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
 }
 #endif
 
 #ifdef CONFIG_MACB
 static void cpu9260_macb_hw_init(void)
 {
-	unsigned long rstcmr;
 	at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
-	at91_rstc_t *rstc = (at91_rstc_t *) ATMEL_BASE_RSTC;
 
 	/* Enable clock */
 	writel(1 << ATMEL_ID_EMAC0, &pmc->pcer);
 
 	at91_set_pio_pullup(AT91_PIO_PORTA, 17, 1);
 
-	rstcmr = readl(&rstc->mr) & AT91_RSTC_MR_ERSTL_MASK;
-
-	/* Need to reset PHY -> 500ms reset */
-	writel(AT91_RSTC_KEY | AT91_RSTC_MR_ERSTL(0xD) |
-				AT91_RSTC_MR_URSTEN, &rstc->mr);
-
-	writel(AT91_RSTC_KEY | AT91_RSTC_CR_EXTRST, &rstc->cr);
-
-	/* Wait for end hardware reset */
-	while (!(readl(&rstc->sr) & AT91_RSTC_SR_NRSTL))
-		;
-
-	/* Restore NRST value */
-	writel(AT91_RSTC_KEY | rstcmr | AT91_RSTC_MR_URSTEN, &rstc->mr);
+	at91_phy_reset();
 
 	at91_macb_hw_init();
 }
diff --git a/board/eukrea/cpuat91/Makefile b/board/eukrea/cpuat91/Makefile
index ed9d3e7285..59b80c267c 100644
--- a/board/eukrea/cpuat91/Makefile
+++ b/board/eukrea/cpuat91/Makefile
@@ -5,24 +5,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	:= $(BOARD).o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
-	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	:= cpuat91.o
diff --git a/board/evb64260/Makefile b/board/evb64260/Makefile
index 512f6d714b..ae2ebedb8e 100644
--- a/board/evb64260/Makefile
+++ b/board/evb64260/Makefile
@@ -8,27 +8,7 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-SOBJS	= misc.o
-COBJS	= $(BOARD).o flash.o serial.o memory.o pci.o \
+obj-y	= misc.o
+obj-y	+= evb64260.o flash.o serial.o memory.o pci.o \
 	  eth.o eth_addrtbl.o mpsc.o i2c.o \
 	  sdram_init.o zuma_pbb.o intel_flash.o zuma_pbb_mbox.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
-	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
diff --git a/board/evb64260/serial.c b/board/evb64260/serial.c
index 3081fad21a..83a421708b 100644
--- a/board/evb64260/serial.c
+++ b/board/evb64260/serial.c
@@ -21,8 +21,6 @@
 #include <ns16550.h>
 #endif
 
-#include "serial.h"
-
 #include "mpsc.h"
 
 DECLARE_GLOBAL_DATA_PTR;
diff --git a/board/evb64260/serial.h b/board/evb64260/serial.h
deleted file mode 100644
index bac9253852..0000000000
--- a/board/evb64260/serial.h
+++ /dev/null
@@ -1,63 +0,0 @@
-/* serial.h - mostly useful for DUART serial_init in serial.c */
-
-#ifndef __SERIAL_H__
-#define __SERIAL_H__
-
-#if 0
-
-#define B230400         1
-#define B115200         2
-#define B57600          4
-#define B38400          82
-#define B19200          163
-#define B9600           24
-#define B4800           651
-#define B2400           1302
-#define B1200           2604
-#define B600            5208
-#define B300            10417
-#define B150            20833
-#define B110            28409
-#define BDEFAULT        B115200
-
-				/* this stuff is important to initialize
-				the DUART channels */
-
-#define	Scale		0x01L		/* distance between port addresses */
-#define	COM1		0x000003f8		/* Keyboard */
-#define COM2		0x000002f8		/* Host */
-
-
-/* Port Definitions relative to base COM port addresses */
-#define DataIn	(0x00*Scale)	/* data input port */
-#define DataOut	(0x00*Scale)	/* data output port */
-#define BaudLsb	(0x00*Scale)	/* baud rate divisor least significant byte */
-#define BaudMsb	(0x01*Scale)	/* baud rate divisor most significant byte */
-#define	Ier	(0x01*Scale)	/* interrupt enable register */
-#define	Iir	(0x02*Scale)	/* interrupt identification register */
-#define	Lcr	(0x03*Scale)	/* line control register */
-#define	Mcr	(0x04*Scale)	/* modem control register */
-#define	Lsr	(0x05*Scale)	/* line status register */
-#define	Msr	(0x06*Scale)	/* modem status register */
-
-/* Bit Definitions for above ports */
-#define LcrDlab	0x80	/* b7:	 enable baud rate divisor registers */
-#define	LcrDflt	0x03	/* b6-0: no parity, 1 stop, 8 data */
-
-#define	McrRts	0x02	/* b1:	request to send (I am ready to xmit) */
-#define	McrDtr	0x01	/* b0:	data terminal ready (I am alive ready to rcv) */
-#define	McrDflt	(McrRts|McrDtr)
-
-#define LsrTxD	0x6000	/* b5: transmit holding register empty (i.e. xmit OK!)*/
-			/* b6: transmitter empty */
-#define LsrRxD	0x0100	/* b0: received data ready (i.e. got a byte!) */
-
-#define	MsrRi	0x0040	/* b6: ring indicator (other guy is ready to rcv) */
-#define	MsrDsr	0x0020	/* b5: data set ready (other guy is alive ready to rcv */
-#define	MsrCts	0x0010	/* b4: clear to send (other guy is ready to rcv) */
-
-#define IerRda	0xf	/* b0: Enable received data available interrupt */
-
-#endif
-
-#endif /* __SERIAL_H__ */
diff --git a/board/exmeritus/hww1u1a/Makefile b/board/exmeritus/hww1u1a/Makefile
index e441c14f9a..d0cd87828e 100644
--- a/board/exmeritus/hww1u1a/Makefile
+++ b/board/exmeritus/hww1u1a/Makefile
@@ -6,27 +6,7 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS-y	+= $(BOARD).o
-COBJS-y	+= law.o
-COBJS-y	+= tlb.o
-COBJS-$(CONFIG_DDR_SPD) += ddr.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS-y))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	+= hww1u1a.o
+obj-y	+= law.o
+obj-y	+= tlb.o
+obj-$(CONFIG_DDR_SPD) += ddr.o
diff --git a/board/exmeritus/hww1u1a/ddr.c b/board/exmeritus/hww1u1a/ddr.c
index 36d02ad5d8..e1f6865f42 100644
--- a/board/exmeritus/hww1u1a/ddr.c
+++ b/board/exmeritus/hww1u1a/ddr.c
@@ -9,8 +9,8 @@
 
 #include <common.h>
 
-#include <asm/fsl_ddr_sdram.h>
-#include <asm/fsl_ddr_dimm_params.h>
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr_dimm_params.h>
 
 void fsl_ddr_board_options(memctl_options_t *popts,
 				dimm_params_t *pdimm,
@@ -30,5 +30,5 @@ void fsl_ddr_board_options(memctl_options_t *popts,
 	popts->clk_adjust = 4;
 	popts->cpo_override = 4;
 	popts->write_data_delay = 2;
-	popts->twoT_en = 0;
+	popts->twot_en = 0;
 }
diff --git a/board/exmeritus/hww1u1a/hww1u1a.c b/board/exmeritus/hww1u1a/hww1u1a.c
index 7c11e38d1c..97b84b3224 100644
--- a/board/exmeritus/hww1u1a/hww1u1a.c
+++ b/board/exmeritus/hww1u1a/hww1u1a.c
@@ -13,7 +13,7 @@
 #include <asm/cache.h>
 #include <asm/immap_85xx.h>
 #include <asm/fsl_pci.h>
-#include <asm/fsl_ddr_sdram.h>
+#include <fsl_ddr_sdram.h>
 #include <asm/io.h>
 #include <miiphy.h>
 #include <libfdt.h>
@@ -37,6 +37,7 @@ int checkboard(void)
 	unsigned int gpio_low  = 0;
 	unsigned int gpio_in   = 0;
 	unsigned int i;
+	struct ccsr_ddr __iomem *ddr;
 
 	puts("Board: HWW-1U-1A ");
 
@@ -89,7 +90,7 @@ int checkboard(void)
 	 * and delay a while before we continue.
 	 */
 	if (mpc85xx_gpio_get(GPIO_RESETS)) {
-		ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_MPC8xxx_DDR_ADDR;
+		ddr = (struct ccsr_ddr __iomem *)CONFIG_SYS_FSL_DDR_ADDR;
 
 		puts("Debugger detected... extra device reset enabled!\n");
 
diff --git a/board/fads/Makefile b/board/fads/Makefile
index 4c70032306..ea8b5c0d81 100644
--- a/board/fads/Makefile
+++ b/board/fads/Makefile
@@ -5,24 +5,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	= $(BOARD).o flash.o lamp.o pcmcia.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	= fads.o flash.o lamp.o pcmcia.o
diff --git a/board/fads/fads.h b/board/fads/fads.h
index 2550529c8d..fa49080fb7 100644
--- a/board/fads/fads.h
+++ b/board/fads/fads.h
@@ -114,7 +114,6 @@
 /*
  * Miscellaneous configurable options
  */
-#define	CONFIG_SYS_PROMPT		"=>"		/* Monitor Command Prompt	*/
 #define CONFIG_SYS_HUSH_PARSER
 #define	CONFIG_SYS_LONGHELP				/* #undef to save memory	*/
 #if defined(CONFIG_CMD_KGDB)
@@ -128,8 +127,6 @@
 
 #define CONFIG_SYS_LOAD_ADDR		0x00100000
 
-#define	CONFIG_SYS_HZ		        1000	/* decrementer freq: 1 ms ticks */
-
 /*
  * Low Level Configuration Settings
  * (address mappings, register initial values, etc.)
diff --git a/board/faraday/a320evb/Makefile b/board/faraday/a320evb/Makefile
index 7446945f6f..518ce3fcb4 100644
--- a/board/faraday/a320evb/Makefile
+++ b/board/faraday/a320evb/Makefile
@@ -5,25 +5,5 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	:= a320evb.o
-SOBJS	:= lowlevel_init.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
-	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	:= a320evb.o
+obj-y	+= lowlevel_init.o
diff --git a/board/flagadm/Makefile b/board/flagadm/Makefile
index e9558412e1..f2377c8392 100644
--- a/board/flagadm/Makefile
+++ b/board/flagadm/Makefile
@@ -5,24 +5,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	= $(BOARD).o flash.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	= flagadm.o flash.o
diff --git a/board/freescale/b4860qds/Makefile b/board/freescale/b4860qds/Makefile
index a864c0b72d..e5cc054a01 100644
--- a/board/freescale/b4860qds/Makefile
+++ b/board/freescale/b4860qds/Makefile
@@ -4,35 +4,9 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS-y	+= $(BOARD).o
-COBJS-y	+= ddr.o
-COBJS-$(CONFIG_B4860QDS)+= eth_b4860qds.o
-COBJS-$(CONFIG_PCI)	+= pci.o
-COBJS-y	+= law.o
-COBJS-y	+= tlb.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS-y))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-clean:
-	rm -f $(OBJS) $(SOBJS)
-
-distclean:	clean
-	rm -f $(LIB) core *.bak .depend
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	+= b4860qds.o
+obj-y	+= ddr.o
+obj-$(CONFIG_B4860QDS)+= eth_b4860qds.o
+obj-$(CONFIG_PCI)	+= pci.o
+obj-y	+= law.o
+obj-y	+= tlb.o
diff --git a/board/freescale/b4860qds/b4860qds.c b/board/freescale/b4860qds/b4860qds.c
index f74651c520..d9c88a074f 100644
--- a/board/freescale/b4860qds/b4860qds.c
+++ b/board/freescale/b4860qds/b4860qds.c
@@ -11,6 +11,7 @@
 #include <linux/compiler.h>
 #include <asm/mmu.h>
 #include <asm/processor.h>
+#include <asm/errno.h>
 #include <asm/cache.h>
 #include <asm/immap_85xx.h>
 #include <asm/fsl_law.h>
@@ -28,7 +29,6 @@
 
 #define CLK_MUX_SEL_MASK	0x4
 #define ETH_PHY_CLK_OUT		0x4
-#define PLL_NUM			2
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -120,6 +120,7 @@ int configure_vsc3316_3308(void)
 	debug("Using SERDES2 Protocol: 0x%x:\n", serdes2_prtcl);
 
 	switch (serdes1_prtcl) {
+	case 0x29:
 	case 0x2a:
 	case 0x2C:
 	case 0x2D:
@@ -151,7 +152,55 @@ int configure_vsc3316_3308(void)
 		}
 		break;
 
+	case 0x02:
+	case 0x04:
+	case 0x05:
+	case 0x06:
+	case 0x08:
+	case 0x09:
+	case 0x0A:
+	case 0x0B:
+	case 0x0C:
+	case 0x30:
+	case 0x32:
+	case 0x33:
+	case 0x34:
+	case 0x39:
+	case 0x3A:
+	case 0x3C:
+	case 0x3D:
+	case 0x5C:
+	case 0x5D:
+			/*
+			 * Configuration:
+			 * SERDES: 1
+			 * Lanes: A,B: AURORA
+			 * Lanes: C,d: SGMII
+			 * Lanes: E,F,G,H: CPRI
+			 */
+		debug("Configuring crossbar for Aurora, SGMII 3 and 4,"
+				" and CPRI. srds_prctl:%x\n", serdes1_prtcl);
+		num_vsc16_con = NUM_CON_VSC3316;
+		/* Configure VSC3316 crossbar switch */
+		ret = select_i2c_ch_pca(I2C_CH_VSC3316);
+		if (!ret) {
+			ret = vsc3316_config(VSC3316_TX_ADDRESS,
+					vsc16_tx_sfp_sgmii_aurora,
+					num_vsc16_con);
+			if (ret)
+				return ret;
+			ret = vsc3316_config(VSC3316_RX_ADDRESS,
+					vsc16_rx_sfp_sgmii_aurora,
+					num_vsc16_con);
+			if (ret)
+				return ret;
+		} else {
+			return ret;
+		}
+		break;
+
 #ifdef CONFIG_PPC_B4420
+	case 0x17:
 	case 0x18:
 			/*
 			 * Configuration:
@@ -239,14 +288,191 @@ int configure_vsc3316_3308(void)
 	return 0;
 }
 
+static int calibrate_pll(serdes_corenet_t *srds_regs, int pll_num)
+{
+	u32 rst_err;
+
+	/* Steps For SerDes PLLs reset and reconfiguration
+	 * or PLL power-up procedure
+	 */
+	debug("CALIBRATE PLL:%d\n", pll_num);
+	clrbits_be32(&srds_regs->bank[pll_num].rstctl,
+			SRDS_RSTCTL_SDRST_B);
+	udelay(10);
+	clrbits_be32(&srds_regs->bank[pll_num].rstctl,
+		(SRDS_RSTCTL_SDEN | SRDS_RSTCTL_PLLRST_B));
+	udelay(10);
+	setbits_be32(&srds_regs->bank[pll_num].rstctl,
+			SRDS_RSTCTL_RST);
+	setbits_be32(&srds_regs->bank[pll_num].rstctl,
+		(SRDS_RSTCTL_SDEN | SRDS_RSTCTL_PLLRST_B
+		| SRDS_RSTCTL_SDRST_B));
+
+	udelay(20);
+
+	/* Check whether PLL has been locked or not */
+	rst_err = in_be32(&srds_regs->bank[pll_num].rstctl) &
+				SRDS_RSTCTL_RSTERR;
+	rst_err >>= SRDS_RSTCTL_RSTERR_SHIFT;
+	debug("RST_ERR value for PLL %d is: 0x%x:\n", pll_num, rst_err);
+	if (rst_err)
+		return rst_err;
+
+	return rst_err;
+}
+
+static int check_pll_locks(serdes_corenet_t *srds_regs, int pll_num)
+{
+	int ret = 0;
+	u32 fcap, dcbias, bcap, pllcr1, pllcr0;
+
+	if (calibrate_pll(srds_regs, pll_num)) {
+		/* STEP 1 */
+		/* Read fcap, dcbias and bcap value */
+		clrbits_be32(&srds_regs->bank[pll_num].pllcr0,
+				SRDS_PLLCR0_DCBIAS_OUT_EN);
+		fcap = in_be32(&srds_regs->bank[pll_num].pllsr2) &
+					SRDS_PLLSR2_FCAP;
+		fcap >>= SRDS_PLLSR2_FCAP_SHIFT;
+		bcap = in_be32(&srds_regs->bank[pll_num].pllsr2) &
+					SRDS_PLLSR2_BCAP_EN;
+		bcap >>= SRDS_PLLSR2_BCAP_EN_SHIFT;
+		setbits_be32(&srds_regs->bank[pll_num].pllcr0,
+				SRDS_PLLCR0_DCBIAS_OUT_EN);
+		dcbias = in_be32(&srds_regs->bank[pll_num].pllsr2) &
+					SRDS_PLLSR2_DCBIAS;
+		dcbias >>= SRDS_PLLSR2_DCBIAS_SHIFT;
+		debug("values of bcap:%x, fcap:%x and dcbias:%x\n",
+					bcap, fcap, dcbias);
+		if (fcap == 0 && bcap == 1) {
+			/* Step 3 */
+			clrbits_be32(&srds_regs->bank[pll_num].rstctl,
+				(SRDS_RSTCTL_SDEN | SRDS_RSTCTL_PLLRST_B
+				 | SRDS_RSTCTL_SDRST_B));
+			clrbits_be32(&srds_regs->bank[pll_num].pllcr1,
+					SRDS_PLLCR1_BCAP_EN);
+			setbits_be32(&srds_regs->bank[pll_num].pllcr1,
+					SRDS_PLLCR1_BCAP_OVD);
+			if (calibrate_pll(srds_regs, pll_num)) {
+				/*save the fcap, dcbias and bcap values*/
+				clrbits_be32(&srds_regs->bank[pll_num].pllcr0,
+						SRDS_PLLCR0_DCBIAS_OUT_EN);
+				fcap = in_be32(&srds_regs->bank[pll_num].pllsr2)
+					& SRDS_PLLSR2_FCAP;
+				fcap >>= SRDS_PLLSR2_FCAP_SHIFT;
+				bcap = in_be32(&srds_regs->bank[pll_num].pllsr2)
+					& SRDS_PLLSR2_BCAP_EN;
+				bcap >>= SRDS_PLLSR2_BCAP_EN_SHIFT;
+				setbits_be32(&srds_regs->bank[pll_num].pllcr0,
+						SRDS_PLLCR0_DCBIAS_OUT_EN);
+				dcbias = in_be32
+					(&srds_regs->bank[pll_num].pllsr2) &
+							SRDS_PLLSR2_DCBIAS;
+				dcbias >>= SRDS_PLLSR2_DCBIAS_SHIFT;
+
+				/* Step 4*/
+				clrbits_be32(&srds_regs->bank[pll_num].rstctl,
+				(SRDS_RSTCTL_SDEN | SRDS_RSTCTL_PLLRST_B
+				 | SRDS_RSTCTL_SDRST_B));
+				setbits_be32(&srds_regs->bank[pll_num].pllcr1,
+						SRDS_PLLCR1_BYP_CAL);
+				clrbits_be32(&srds_regs->bank[pll_num].pllcr1,
+						SRDS_PLLCR1_BCAP_EN);
+				setbits_be32(&srds_regs->bank[pll_num].pllcr1,
+						SRDS_PLLCR1_BCAP_OVD);
+				/* change the fcap and dcbias to the saved
+				 * values from Step 3 */
+				clrbits_be32(&srds_regs->bank[pll_num].pllcr1,
+							SRDS_PLLCR1_PLL_FCAP);
+				pllcr1 = (in_be32
+					(&srds_regs->bank[pll_num].pllcr1)|
+					(fcap << SRDS_PLLCR1_PLL_FCAP_SHIFT));
+				out_be32(&srds_regs->bank[pll_num].pllcr1,
+							pllcr1);
+				clrbits_be32(&srds_regs->bank[pll_num].pllcr0,
+						SRDS_PLLCR0_DCBIAS_OVRD);
+				pllcr0 = (in_be32
+				(&srds_regs->bank[pll_num].pllcr0)|
+				(dcbias << SRDS_PLLCR0_DCBIAS_OVRD_SHIFT));
+				out_be32(&srds_regs->bank[pll_num].pllcr0,
+							pllcr0);
+				ret = calibrate_pll(srds_regs, pll_num);
+				if (ret)
+					return ret;
+			} else {
+				goto out;
+			}
+		} else { /* Step 5 */
+			clrbits_be32(&srds_regs->bank[pll_num].rstctl,
+				(SRDS_RSTCTL_SDEN | SRDS_RSTCTL_PLLRST_B
+				 | SRDS_RSTCTL_SDRST_B));
+			udelay(10);
+			/* Change the fcap, dcbias, and bcap to the
+			 * values from Step 1 */
+			setbits_be32(&srds_regs->bank[pll_num].pllcr1,
+					SRDS_PLLCR1_BYP_CAL);
+			clrbits_be32(&srds_regs->bank[pll_num].pllcr1,
+						SRDS_PLLCR1_PLL_FCAP);
+			pllcr1 = (in_be32(&srds_regs->bank[pll_num].pllcr1)|
+				(fcap << SRDS_PLLCR1_PLL_FCAP_SHIFT));
+			out_be32(&srds_regs->bank[pll_num].pllcr1,
+						pllcr1);
+			clrbits_be32(&srds_regs->bank[pll_num].pllcr0,
+						SRDS_PLLCR0_DCBIAS_OVRD);
+			pllcr0 = (in_be32(&srds_regs->bank[pll_num].pllcr0)|
+				(dcbias << SRDS_PLLCR0_DCBIAS_OVRD_SHIFT));
+			out_be32(&srds_regs->bank[pll_num].pllcr0,
+						pllcr0);
+			clrbits_be32(&srds_regs->bank[pll_num].pllcr1,
+					SRDS_PLLCR1_BCAP_EN);
+			setbits_be32(&srds_regs->bank[pll_num].pllcr1,
+					SRDS_PLLCR1_BCAP_OVD);
+			ret = calibrate_pll(srds_regs, pll_num);
+			if (ret)
+				return ret;
+		}
+	}
+out:
+	return 0;
+}
+
+static int check_serdes_pll_locks(void)
+{
+	serdes_corenet_t *srds1_regs =
+		(void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
+	serdes_corenet_t *srds2_regs =
+		(void *)CONFIG_SYS_FSL_CORENET_SERDES2_ADDR;
+	int i, ret1, ret2;
+
+	debug("\nSerDes1 Lock check\n");
+	for (i = 0; i < CONFIG_SYS_FSL_SRDS_NUM_PLLS; i++) {
+		ret1 = check_pll_locks(srds1_regs, i);
+		if (ret1) {
+			printf("SerDes1, PLL:%d didnt lock\n", i);
+			return ret1;
+		}
+	}
+	debug("\nSerDes2 Lock check\n");
+	for (i = 0; i < CONFIG_SYS_FSL_SRDS_NUM_PLLS; i++) {
+		ret2 = check_pll_locks(srds2_regs, i);
+		if (ret2) {
+			printf("SerDes2, PLL:%d didnt lock\n", i);
+			return ret2;
+		}
+	}
+
+	return 0;
+}
+
 int config_serdes1_refclks(void)
 {
 	ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 	serdes_corenet_t *srds_regs =
 		(void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
 	u32 serdes1_prtcl, lane;
-	unsigned int flag_sgmii_prtcl = 0;
-	int ret, i;
+	unsigned int flag_sgmii_aurora_prtcl = 0;
+	int i;
+	int ret = 0;
 
 	serdes1_prtcl = in_be32(&gur->rcwsr[4]) &
 			FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
@@ -257,10 +483,12 @@ int config_serdes1_refclks(void)
 	serdes1_prtcl >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
 	debug("Using SERDES1 Protocol: 0x%x:\n", serdes1_prtcl);
 
-	/* Clear SRDS_RSTCTL_RST bit for both PLLs before changing refclks
+	/* To prevent generation of reset request from SerDes
+	 * while changing the refclks, By setting SRDS_RST_MSK bit,
+	 * SerDes reset event cannot cause a reset request
 	 */
-	for (i = 0; i < PLL_NUM; i++)
-		clrbits_be32(&srds_regs->bank[i].rstctl, SRDS_RSTCTL_RST);
+	setbits_be32(&gur->rstrqmr1, FSL_CORENET_RSTRQMR1_SRDS_RST_MSK);
+
 	/* Reconfigure IDT idt8t49n222a device for CPRI to work
 	 * For this SerDes1's Refclk1 and refclk2 need to be set
 	 * to 122.88MHz
@@ -270,6 +498,25 @@ int config_serdes1_refclks(void)
 	case 0x2C:
 	case 0x2D:
 	case 0x2E:
+	case 0x02:
+	case 0x04:
+	case 0x05:
+	case 0x06:
+	case 0x08:
+	case 0x09:
+	case 0x0A:
+	case 0x0B:
+	case 0x0C:
+	case 0x30:
+	case 0x32:
+	case 0x33:
+	case 0x34:
+	case 0x39:
+	case 0x3A:
+	case 0x3C:
+	case 0x3D:
+	case 0x5C:
+	case 0x5D:
 		debug("Configuring idt8t49n222a for CPRI SerDes clks:"
 			" for srds_prctl:%x\n", serdes1_prtcl);
 		ret = select_i2c_ch_pca(I2C_CH_IDT);
@@ -279,16 +526,16 @@ int config_serdes1_refclks(void)
 					SERDES_REFCLK_122_88, 0);
 			if (ret) {
 				printf("IDT8T49N222A configuration failed.\n");
-				return ret;
+				goto out;
 			} else
-				printf("IDT8T49N222A configured.\n");
+				debug("IDT8T49N222A configured.\n");
 		} else {
-			return ret;
+			goto out;
 		}
 		select_i2c_ch_pca(I2C_CH_DEFAULT);
 
 		/* Change SerDes1's Refclk1 to 125MHz for on board
-		 * SGMIIs to work
+		 * SGMIIs or Aurora to work
 		 */
 		for (lane = 0; lane < SRDS_MAX_LANES; lane++) {
 			enum srds_prtcl lane_prtcl = serdes_get_prtcl
@@ -300,20 +547,21 @@ int config_serdes1_refclks(void)
 			case SGMII_FM1_DTSEC4:
 			case SGMII_FM1_DTSEC5:
 			case SGMII_FM1_DTSEC6:
-				flag_sgmii_prtcl++;
+			case AURORA:
+				flag_sgmii_aurora_prtcl++;
 				break;
 			default:
 				break;
 			}
 		}
 
-		if (flag_sgmii_prtcl)
+		if (flag_sgmii_aurora_prtcl)
 			QIXIS_WRITE(brdcfg[4], QIXIS_SRDS1CLK_125);
 
 		/* Steps For SerDes PLLs reset and reconfiguration after
 		 * changing SerDes's refclks
 		 */
-		for (i = 0; i < PLL_NUM; i++) {
+		for (i = 0; i < CONFIG_SYS_FSL_SRDS_NUM_PLLS; i++) {
 			debug("For PLL%d reset and reconfiguration after"
 			       " changing refclks\n", i+1);
 			clrbits_be32(&srds_regs->bank[i].rstctl,
@@ -333,16 +581,101 @@ int config_serdes1_refclks(void)
 		printf("WARNING:IDT8T49N222A configuration not"
 			" supported for:%x SerDes1 Protocol.\n",
 			serdes1_prtcl);
-		return -1;
 	}
 
-	return 0;
+out:
+	/* Clearing SRDS_RST_MSK bit as now
+	 * SerDes reset event can cause a reset request
+	 */
+	clrbits_be32(&gur->rstrqmr1, FSL_CORENET_RSTRQMR1_SRDS_RST_MSK);
+	return ret;
+}
+
+int config_serdes2_refclks(void)
+{
+	ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+	serdes_corenet_t *srds2_regs =
+		(void *)CONFIG_SYS_FSL_CORENET_SERDES2_ADDR;
+	u32 serdes2_prtcl;
+	int ret = 0;
+	int i;
+
+	serdes2_prtcl = in_be32(&gur->rcwsr[4]) &
+			FSL_CORENET2_RCWSR4_SRDS2_PRTCL;
+	if (!serdes2_prtcl) {
+		debug("SERDES2 is not enabled\n");
+		return -ENODEV;
+	}
+	serdes2_prtcl >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT;
+	debug("Using SERDES2 Protocol: 0x%x:\n", serdes2_prtcl);
+
+	/* To prevent generation of reset request from SerDes
+	 * while changing the refclks, By setting SRDS_RST_MSK bit,
+	 * SerDes reset event cannot cause a reset request
+	 */
+	setbits_be32(&gur->rstrqmr1, FSL_CORENET_RSTRQMR1_SRDS_RST_MSK);
+
+	/* Reconfigure IDT idt8t49n222a device for PCIe SATA to work
+	 * For this SerDes2's Refclk1 need to be set to 100MHz
+	 */
+	switch (serdes2_prtcl) {
+	case 0x9E:
+	case 0x9A:
+	case 0xb2:
+		debug("Configuring IDT for PCIe SATA for srds_prctl:%x\n",
+			serdes2_prtcl);
+		ret = select_i2c_ch_pca(I2C_CH_IDT);
+		if (!ret) {
+			ret = set_serdes_refclk(IDT_SERDES2_ADDRESS, 2,
+					SERDES_REFCLK_100,
+					SERDES_REFCLK_156_25, 0);
+			if (ret) {
+				printf("IDT8T49N222A configuration failed.\n");
+				goto out;
+			} else
+				debug("IDT8T49N222A configured.\n");
+		} else {
+			goto out;
+		}
+		select_i2c_ch_pca(I2C_CH_DEFAULT);
+
+		/* Steps For SerDes PLLs reset and reconfiguration after
+		 * changing SerDes's refclks
+		 */
+		for (i = 0; i < CONFIG_SYS_FSL_SRDS_NUM_PLLS; i++) {
+			clrbits_be32(&srds2_regs->bank[i].rstctl,
+					SRDS_RSTCTL_SDRST_B);
+			udelay(10);
+			clrbits_be32(&srds2_regs->bank[i].rstctl,
+				(SRDS_RSTCTL_SDEN | SRDS_RSTCTL_PLLRST_B));
+			udelay(10);
+			setbits_be32(&srds2_regs->bank[i].rstctl,
+					SRDS_RSTCTL_RST);
+			setbits_be32(&srds2_regs->bank[i].rstctl,
+				(SRDS_RSTCTL_SDEN | SRDS_RSTCTL_PLLRST_B
+				| SRDS_RSTCTL_SDRST_B));
+
+			udelay(10);
+		}
+		break;
+	default:
+		printf("IDT configuration not supported for:%x S2 Protocol.\n",
+			serdes2_prtcl);
+	}
+
+out:
+	/* Clearing SRDS_RST_MSK bit as now
+	 * SerDes reset event can cause a reset request
+	 */
+	clrbits_be32(&gur->rstrqmr1, FSL_CORENET_RSTRQMR1_SRDS_RST_MSK);
+	return ret;
 }
 
 int board_early_init_r(void)
 {
 	const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
 	const u8 flash_esel = find_tlb_idx((void *)flashbase, 1);
+	int ret;
 
 	/*
 	 * Remap Boot flash + PROMJET region to caching-inhibited
@@ -375,6 +708,35 @@ int board_early_init_r(void)
 	else
 		printf("SerDes1 Refclks have been set.\n");
 
+	/* SerDes2 refclks need to be set again, as default clks
+	 * are not suitable for PCIe SATA to work
+	 * This function will set SerDes2's Refclk1 and refclk2
+	 * for SerDes2 protocols having PCIe in them
+	 * for PCIe SATA to work
+	 */
+	ret = config_serdes2_refclks();
+	if (!ret)
+		printf("SerDes2 Refclks have been set.\n");
+	else if (ret == -ENODEV)
+		printf("SerDes disable, Refclks couldn't change.\n");
+	else
+		printf("SerDes2 Refclk reconfiguring failed.\n");
+
+#if defined(CONFIG_SYS_FSL_ERRATUM_A006384) || \
+			defined(CONFIG_SYS_FSL_ERRATUM_A006475)
+	/* Rechecking the SerDes locks after all SerDes configurations
+	 * are done, As SerDes PLLs may not lock reliably at 5 G VCO
+	 * and at cold temperatures.
+	 * Following sequence ensure the proper locking of SerDes PLLs.
+	 */
+	if (SVR_MAJ(get_svr()) == 1) {
+		if (check_serdes_pll_locks())
+			printf("SerDes plls still not locked properly.\n");
+		else
+			printf("SerDes plls have been locked well.\n");
+	}
+#endif
+
 	/* Configure VSC3316 and VSC3308 crossbar switches */
 	if (configure_vsc3316_3308())
 		printf("VSC:failed to configure VSC3316/3308.\n");
@@ -457,22 +819,6 @@ static int serdes_refclock(u8 sw, u8 sdclk)
 	return ret;
 }
 
-static const char *serdes_clock_to_string(u32 clock)
-{
-	switch (clock) {
-	case SRDS_PLLCR0_RFCK_SEL_100:
-		return "100";
-	case SRDS_PLLCR0_RFCK_SEL_125:
-		return "125";
-	case SRDS_PLLCR0_RFCK_SEL_156_25:
-		return "156.25";
-	case SRDS_PLLCR0_RFCK_SEL_161_13:
-		return "161.13";
-	default:
-		return "122.88";
-	}
-}
-
 #define NUM_SRDS_BANKS	2
 
 int misc_init_r(void)
diff --git a/board/freescale/b4860qds/b4860qds_crossbar_con.h b/board/freescale/b4860qds/b4860qds_crossbar_con.h
index db0cf28fff..fcccb8f9b3 100644
--- a/board/freescale/b4860qds/b4860qds_crossbar_con.h
+++ b/board/freescale/b4860qds/b4860qds_crossbar_con.h
@@ -24,6 +24,10 @@ static const int8_t vsc16_tx_4sfp_sgmii_34[8][2] = { {15, 7}, {0, 1},
 				{7, 8}, {9, 0}, {5, 14}, {4, 15},
 				{-1, -1}, {-1, -1} };
 
+static int8_t vsc16_tx_sfp_sgmii_aurora[8][2] = { {15, 7}, {0, 1},
+				{7, 8}, {9, 0}, {5, 14},
+				{4, 15}, {2, 12}, {12, 13} };
+
 #ifdef CONFIG_PPC_B4420
 static int8_t vsc16_tx_sgmii_lane_cd[8][2] = { {5, 14}, {4, 15},
 		{-1, -1}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1} };
@@ -46,6 +50,10 @@ static const int8_t vsc16_rx_4sfp_sgmii_34[8][2] = { {8, 15}, {0, 1},
 				{7, 8}, {1, 9}, {14, 11}, {15, 10},
 				{-1, -1}, {-1, -1} };
 
+static int8_t vsc16_rx_sfp_sgmii_aurora[8][2] = { {8, 15}, {0, 1},
+				{7, 8}, {1, 9}, {14, 11},
+				{15, 10}, {13, 3}, {12, 12} };
+
 #ifdef CONFIG_PPC_B4420
 static int8_t vsc16_rx_sgmii_lane_cd[8][2] = { {14, 11}, {15, 10},
 		{-1, -1}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1} };
diff --git a/board/freescale/b4860qds/b4860qds_qixis.h b/board/freescale/b4860qds/b4860qds_qixis.h
index 2fabbc7b32..272afc1ae0 100644
--- a/board/freescale/b4860qds/b4860qds_qixis.h
+++ b/board/freescale/b4860qds/b4860qds_qixis.h
@@ -21,4 +21,9 @@
 
 #define QIXIS_SRDS1CLK_122		0x5a
 #define QIXIS_SRDS1CLK_125		0x5e
+
+/* SGMII */
+#define PHY_BASE_ADDR		0x18
+#define PORT_NUM		0x04
+#define REGNUM			0x00
 #endif
diff --git a/board/freescale/b4860qds/b4_pbi.cfg b/board/freescale/b4860qds/b4_pbi.cfg
new file mode 100644
index 0000000000..57b726eead
--- /dev/null
+++ b/board/freescale/b4860qds/b4_pbi.cfg
@@ -0,0 +1,27 @@
+#PBI commands
+#Initialize CPC1
+09010000 00200400
+09138000 00000000
+091380c0 00000100
+#Configure CPC1 as 512KB SRAM
+09010100 00000000
+09010104 fff80009
+09010f00 08000000
+09010000 80000000
+#Configure LAW for CPC1
+09000d00 00000000
+09000d04 fff80000
+09000d08 81000012
+#Configure alternate space
+09000010 00000000
+09000014 ff000000
+09000018 81000000
+#Configure SPI controller
+09110000 80000403
+09110020 2d170008
+09110024 00100008
+09110028 00100008
+0911002c 00100008
+#Flush PBL data
+09138000 00000000
+091380c0 00000000
diff --git a/board/freescale/b4860qds/b4_rcw.cfg b/board/freescale/b4860qds/b4_rcw.cfg
new file mode 100644
index 0000000000..597d3914ca
--- /dev/null
+++ b/board/freescale/b4860qds/b4_rcw.cfg
@@ -0,0 +1,7 @@
+#PBL preamble and RCW header
+aa55aa55 010e0100
+# serdes protocol 0x2A_0x98
+140e0018 0f001218 00000000 00000000
+54980000 9000a000 e8104000 a9000000
+01000000 00000000 00000000 0001b1f8
+00000000 14000020 00000000 00000011
diff --git a/board/freescale/b4860qds/ddr.c b/board/freescale/b4860qds/ddr.c
index b82b3d409e..187c3b3ebc 100644
--- a/board/freescale/b4860qds/ddr.c
+++ b/board/freescale/b4860qds/ddr.c
@@ -9,11 +9,11 @@
 #include <common.h>
 #include <i2c.h>
 #include <hwconfig.h>
+#include <fsl_ddr.h>
 #include <asm/mmu.h>
-#include <asm/fsl_ddr_sdram.h>
-#include <asm/fsl_ddr_dimm_params.h>
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr_dimm_params.h>
 #include <asm/fsl_law.h>
-#include <../arch/powerpc/cpu/mpc8xxx/ddr/ddr.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -31,20 +31,20 @@ dimm_params_t ddr_raw_timing = {
 	.edc_config = 2,	/* ECC */
 	.burst_lengths_bitmask = 0x0c,
 
-	.tCKmin_X_ps = 1071,
-	.caslat_X = 0x2fe << 4,	/* 5,6,7,8,9,10,11,13 */
-	.tAA_ps = 13910,
-	.tWR_ps = 15000,
-	.tRCD_ps = 13910,
-	.tRRD_ps = 6000,
-	.tRP_ps = 13910,
-	.tRAS_ps = 34000,
-	.tRC_ps = 48910,
-	.tRFC_ps = 260000,
-	.tWTR_ps = 7500,
-	.tRTP_ps = 7500,
+	.tckmin_x_ps = 1071,
+	.caslat_x = 0x2fe << 4,	/* 5,6,7,8,9,10,11,13 */
+	.taa_ps = 13910,
+	.twr_ps = 15000,
+	.trcd_ps = 13910,
+	.trrd_ps = 6000,
+	.trp_ps = 13910,
+	.tras_ps = 34000,
+	.trc_ps = 48910,
+	.trfc_ps = 260000,
+	.twtr_ps = 7500,
+	.trtp_ps = 7500,
 	.refresh_rate_ps = 7800000,
-	.tFAW_ps = 35000,
+	.tfaw_ps = 35000,
 };
 
 int fsl_ddr_get_dimm_params(dimm_params_t *pdimm,
@@ -71,7 +71,7 @@ struct board_specific_parameters {
 	u32 wrlvl_ctl_3;
 	u32 cpo;
 	u32 write_data_delay;
-	u32 force_2T;
+	u32 force_2t;
 };
 
 /*
@@ -129,7 +129,7 @@ void fsl_ddr_board_options(memctl_options_t *popts,
 				popts->wrlvl_start = pbsp->wrlvl_start;
 				popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
 				popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
-				popts->twoT_en = pbsp->force_2T;
+				popts->twot_en = pbsp->force_2t;
 				goto found;
 			}
 			pbsp_highest = pbsp;
@@ -146,7 +146,7 @@ void fsl_ddr_board_options(memctl_options_t *popts,
 		popts->write_data_delay = pbsp_highest->write_data_delay;
 		popts->clk_adjust = pbsp_highest->clk_adjust;
 		popts->wrlvl_start = pbsp_highest->wrlvl_start;
-		popts->twoT_en = pbsp_highest->force_2T;
+		popts->twot_en = pbsp_highest->force_2t;
 	} else {
 		panic("DIMM is not supported by this board");
 	}
diff --git a/board/freescale/b4860qds/eth_b4860qds.c b/board/freescale/b4860qds/eth_b4860qds.c
index dc4ef80fc8..12df9a8d9f 100644
--- a/board/freescale/b4860qds/eth_b4860qds.c
+++ b/board/freescale/b4860qds/eth_b4860qds.c
@@ -66,6 +66,7 @@ static void initialize_lane_to_slot(void)
 			serdes2_prtcl);
 
 	switch (serdes2_prtcl) {
+	case 0x17:
 	case 0x18:
 		/*
 		 * Configuration:
@@ -150,6 +151,8 @@ int board_eth_init(bd_t *bis)
 	struct memac_mdio_info tg_memac_mdio_info;
 	unsigned int i;
 	unsigned int  serdes1_prtcl, serdes2_prtcl;
+	int qsgmii;
+	struct mii_dev *bus;
 	ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 	serdes1_prtcl = in_be32(&gur->rcwsr[4]) &
 		FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
@@ -196,6 +199,7 @@ int board_eth_init(bd_t *bis)
 	fm_info_set_phy_address(FM1_DTSEC6, CONFIG_SYS_FM1_DTSEC6_PHY_ADDR);
 
 	switch (serdes1_prtcl) {
+	case 0x29:
 	case 0x2a:
 		/* Serdes 1: A-B SGMII, Configuring DTSEC 5 and 6 */
 		debug("Setting phy addresses for FM1_DTSEC5: %x and"
@@ -207,6 +211,7 @@ int board_eth_init(bd_t *bis)
 				CONFIG_SYS_FM1_DTSEC6_PHY_ADDR);
 		break;
 #ifdef CONFIG_PPC_B4420
+	case 0x17:
 	case 0x18:
 		/* Serdes 1: A-D SGMII, Configuring on board dual SGMII Phy */
 		debug("Setting phy addresses for FM1_DTSEC3: %x and"
@@ -226,6 +231,7 @@ int board_eth_init(bd_t *bis)
 		break;
 	}
 	switch (serdes2_prtcl) {
+	case 0x17:
 	case 0x18:
 		debug("Setting phy addresses on SGMII Riser card for"
 				"FM1_DTSEC ports: \n");
@@ -238,6 +244,7 @@ int board_eth_init(bd_t *bis)
 		fm_info_set_phy_address(FM1_DTSEC4,
 				CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR);
 		break;
+	case 0x48:
 	case 0x49:
 		debug("Setting phy addresses on SGMII Riser card for"
 				"FM1_DTSEC ports: \n");
@@ -281,6 +288,22 @@ int board_eth_init(bd_t *bis)
 		break;
 	}
 
+	/*set PHY address for QSGMII Riser Card on slot2*/
+	bus = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME);
+	qsgmii = is_qsgmii_riser_card(bus, PHY_BASE_ADDR, PORT_NUM, REGNUM);
+
+	if (qsgmii) {
+		switch (serdes2_prtcl) {
+		case 0xb2:
+		case 0x8d:
+			fm_info_set_phy_address(FM1_DTSEC3, PHY_BASE_ADDR);
+			fm_info_set_phy_address(FM1_DTSEC4, PHY_BASE_ADDR + 1);
+			break;
+		default:
+			break;
+		}
+	}
+
 	for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
 		int idx = i - FM1_DTSEC1;
 
diff --git a/board/freescale/bsc9131rdb/Makefile b/board/freescale/bsc9131rdb/Makefile
index e1a7d8b092..b26d3a1e63 100644
--- a/board/freescale/bsc9131rdb/Makefile
+++ b/board/freescale/bsc9131rdb/Makefile
@@ -4,10 +4,6 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB    = $(obj)lib$(BOARD).o
-
 MINIMAL=
 
 ifdef CONFIG_SPL_BUILD
@@ -18,36 +14,14 @@ endif
 
 ifdef MINIMAL
 
-COBJS-y	+= spl_minimal.o tlb.o law.o
+obj-y	+= spl_minimal.o tlb.o law.o
 
 else
 
-COBJS-y        += $(BOARD).o
-COBJS-y        += ddr.o
-COBJS-y        += law.o
-COBJS-y        += tlb.o
-#COBJS-y		+= bsc9131rdb_mux.o
+obj-y        += bsc9131rdb.o
+obj-y        += ddr.o
+obj-y        += law.o
+obj-y        += tlb.o
+#obj-y		+= bsc9131rdb_mux.o
 
 endif
-
-SRCS   := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
-OBJS   := $(addprefix $(obj),$(COBJS-y))
-SOBJS  := $(addprefix $(obj),$(SOBJS))
-
-$(LIB):		$(obj).depend $(OBJS) $(SOBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-clean:
-	rm -f $(OBJS) $(SOBJS)
-
-distclean:     clean
-	rm -f $(LIB) core *.bak .depend
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
diff --git a/board/freescale/bsc9131rdb/ddr.c b/board/freescale/bsc9131rdb/ddr.c
index c82fe0aab3..339c576256 100644
--- a/board/freescale/bsc9131rdb/ddr.c
+++ b/board/freescale/bsc9131rdb/ddr.c
@@ -8,8 +8,8 @@
 #include <asm/mmu.h>
 #include <asm/immap_85xx.h>
 #include <asm/processor.h>
-#include <asm/fsl_ddr_sdram.h>
-#include <asm/fsl_ddr_dimm_params.h>
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr_dimm_params.h>
 #include <asm/io.h>
 #include <asm/fsl_law.h>
 
@@ -114,20 +114,20 @@ dimm_params_t ddr_raw_timing = {
 	.edc_config = 0,
 	.burst_lengths_bitmask = 0x0c,
 
-	.tCKmin_X_ps = 1870,
-	.caslat_X = 0x1e << 4,	/* 5,6,7,8 */
-	.tAA_ps = 13125,
-	.tWR_ps = 15000,
-	.tRCD_ps = 13125,
-	.tRRD_ps = 7500,
-	.tRP_ps = 13125,
-	.tRAS_ps = 37500,
-	.tRC_ps = 50625,
-	.tRFC_ps = 160000,
-	.tWTR_ps = 7500,
-	.tRTP_ps = 7500,
+	.tckmin_x_ps = 1870,
+	.caslat_x = 0x1e << 4,	/* 5,6,7,8 */
+	.taa_ps = 13125,
+	.twr_ps = 15000,
+	.trcd_ps = 13125,
+	.trrd_ps = 7500,
+	.trp_ps = 13125,
+	.tras_ps = 37500,
+	.trc_ps = 50625,
+	.trfc_ps = 160000,
+	.twtr_ps = 7500,
+	.trtp_ps = 7500,
 	.refresh_rate_ps = 7800000,
-	.tFAW_ps = 37500,
+	.tfaw_ps = 37500,
 };
 
 int fsl_ddr_get_dimm_params(dimm_params_t *pdimm,
diff --git a/board/freescale/bsc9131rdb/spl_minimal.c b/board/freescale/bsc9131rdb/spl_minimal.c
index dd5ea95e33..bd8560b555 100644
--- a/board/freescale/bsc9131rdb/spl_minimal.c
+++ b/board/freescale/bsc9131rdb/spl_minimal.c
@@ -10,7 +10,7 @@
 #include <nand.h>
 #include <linux/compiler.h>
 #include <asm/fsl_law.h>
-#include <asm/fsl_ddr_sdram.h>
+#include <fsl_ddr_sdram.h>
 #include <asm/global_data.h>
 
 DECLARE_GLOBAL_DATA_PTR;
@@ -20,7 +20,8 @@ DECLARE_GLOBAL_DATA_PTR;
  */
 static void sdram_init(void)
 {
-	ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_MPC8xxx_DDR_ADDR;
+	struct ccsr_ddr __iomem *ddr =
+		(struct ccsr_ddr __iomem *)CONFIG_SYS_FSL_DDR_ADDR;
 
 	__raw_writel(CONFIG_SYS_DDR_CS0_BNDS, &ddr->cs0_bnds);
 	__raw_writel(CONFIG_SYS_DDR_CS0_CONFIG, &ddr->cs0_config);
diff --git a/board/freescale/bsc9131rdb/tlb.c b/board/freescale/bsc9131rdb/tlb.c
index 669fe8ad32..c8ecf5de59 100644
--- a/board/freescale/bsc9131rdb/tlb.c
+++ b/board/freescale/bsc9131rdb/tlb.c
@@ -30,7 +30,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
 	SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 0, BOOKE_PAGESZ_4K, 1),
-#ifdef CONFIG_SPL_NAND_MINIMAL
+#ifdef CONFIG_SPL_NAND_BOOT
 	SET_TLB_ENTRY(1, 0xffffe000, 0xffffe000,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 10, BOOKE_PAGESZ_4K, 1),
diff --git a/board/freescale/bsc9132qds/Makefile b/board/freescale/bsc9132qds/Makefile
index 330d35333e..2e4170f512 100644
--- a/board/freescale/bsc9132qds/Makefile
+++ b/board/freescale/bsc9132qds/Makefile
@@ -4,10 +4,6 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
 MINIMAL=
 
 ifdef CONFIG_SPL_BUILD
@@ -18,36 +14,13 @@ endif
 
 ifdef MINIMAL
 
-COBJS-y	+= spl_minimal.o tlb.o law.o
+obj-y	+= spl_minimal.o tlb.o law.o
 
 else
 
-
-COBJS-y	+= $(BOARD).o
-COBJS-y	+= ddr.o
-COBJS-y	+= law.o
-COBJS-y	+= tlb.o
+obj-y	+= bsc9132qds.o
+obj-y	+= ddr.o
+obj-y	+= law.o
+obj-y	+= tlb.o
 
 endif
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS-y))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-clean:
-	rm -f $(OBJS) $(SOBJS)
-
-distclean:	clean
-	rm -f $(LIB) core *.bak .depend
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
diff --git a/board/freescale/bsc9132qds/bsc9132qds.c b/board/freescale/bsc9132qds/bsc9132qds.c
index a895e4e297..9377280063 100644
--- a/board/freescale/bsc9132qds/bsc9132qds.c
+++ b/board/freescale/bsc9132qds/bsc9132qds.c
@@ -17,10 +17,10 @@
 #include <tsec.h>
 #include <mmc.h>
 #include <netdev.h>
-#include <asm/fsl_ifc.h>
+#include <fsl_ifc.h>
 #include <hwconfig.h>
 #include <i2c.h>
-#include <asm/fsl_ddr_sdram.h>
+#include <fsl_ddr_sdram.h>
 
 #ifdef CONFIG_PCI
 #include <pci.h>
@@ -133,16 +133,16 @@ void dsp_ddr_configure(void)
 	 *copy the ddr controller settings from PowerPC side DDR controller
 	 *to the DSP DDR controller as connected DDR memories are similar.
 	 */
-	ccsr_ddr_t __iomem *pa_ddr =
-			(ccsr_ddr_t __iomem *)CONFIG_SYS_MPC8xxx_DDR_ADDR;
-	ccsr_ddr_t temp_ddr;
-	ccsr_ddr_t __iomem *dsp_ddr =
-			(ccsr_ddr_t __iomem *)CONFIG_SYS_FSL_DSP_CCSR_DDR_ADDR;
+	struct ccsr_ddr __iomem *pa_ddr =
+			(struct ccsr_ddr __iomem *)CONFIG_SYS_FSL_DDR_ADDR;
+	struct ccsr_ddr temp_ddr;
+	struct ccsr_ddr __iomem *dsp_ddr =
+			(struct ccsr_ddr __iomem *)CONFIG_SYS_FSL_DSP_CCSR_DDR_ADDR;
 
-	memcpy(&temp_ddr, pa_ddr, sizeof(ccsr_ddr_t));
+	memcpy(&temp_ddr, pa_ddr, sizeof(struct ccsr_ddr));
 	temp_ddr.cs0_bnds = CONFIG_SYS_DDR1_CS0_BNDS;
 	temp_ddr.sdram_cfg &= ~SDRAM_CFG_MEM_EN;
-	memcpy(dsp_ddr, &temp_ddr, sizeof(ccsr_ddr_t));
+	memcpy(dsp_ddr, &temp_ddr, sizeof(struct ccsr_ddr));
 	dsp_ddr->sdram_cfg |= SDRAM_CFG_MEM_EN;
 }
 
diff --git a/board/freescale/bsc9132qds/ddr.c b/board/freescale/bsc9132qds/ddr.c
index fdea193129..43f163a2c6 100644
--- a/board/freescale/bsc9132qds/ddr.c
+++ b/board/freescale/bsc9132qds/ddr.c
@@ -8,8 +8,8 @@
 #include <asm/mmu.h>
 #include <asm/immap_85xx.h>
 #include <asm/processor.h>
-#include <asm/fsl_ddr_sdram.h>
-#include <asm/fsl_ddr_dimm_params.h>
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr_dimm_params.h>
 #include <asm/io.h>
 #include <asm/fsl_law.h>
 
@@ -136,20 +136,20 @@ dimm_params_t ddr_raw_timing = {
 	.edc_config = 0,
 	.burst_lengths_bitmask = 0x0c,
 
-	.tCKmin_X_ps = 1870,
-	.caslat_X = 0x1e << 4,	/* 5,6,7,8 */
-	.tAA_ps = 13125,
-	.tWR_ps = 15000,
-	.tRCD_ps = 13125,
-	.tRRD_ps = 7500,
-	.tRP_ps = 13125,
-	.tRAS_ps = 37500,
-	.tRC_ps = 50625,
-	.tRFC_ps = 160000,
-	.tWTR_ps = 7500,
-	.tRTP_ps = 7500,
+	.tckmin_x_ps = 1870,
+	.caslat_x = 0x1e << 4,	/* 5,6,7,8 */
+	.taa_ps = 13125,
+	.twr_ps = 15000,
+	.trcd_ps = 13125,
+	.trrd_ps = 7500,
+	.trp_ps = 13125,
+	.tras_ps = 37500,
+	.trc_ps = 50625,
+	.trfc_ps = 160000,
+	.twtr_ps = 7500,
+	.trtp_ps = 7500,
 	.refresh_rate_ps = 7800000,
-	.tFAW_ps = 37500,
+	.tfaw_ps = 37500,
 };
 
 int fsl_ddr_get_dimm_params(dimm_params_t *pdimm,
diff --git a/board/freescale/bsc9132qds/spl_minimal.c b/board/freescale/bsc9132qds/spl_minimal.c
index 2bf0a0cfa8..8f71431926 100644
--- a/board/freescale/bsc9132qds/spl_minimal.c
+++ b/board/freescale/bsc9132qds/spl_minimal.c
@@ -10,14 +10,15 @@
 #include <nand.h>
 #include <linux/compiler.h>
 #include <asm/fsl_law.h>
-#include <asm/fsl_ddr_sdram.h>
+#include <fsl_ddr_sdram.h>
 #include <asm/global_data.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
 static void sdram_init(void)
 {
-	ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_MPC8xxx_DDR_ADDR;
+	struct ccsr_ddr __iomem *ddr =
+		(struct ccsr_ddr __iomem *)CONFIG_SYS_FSL_DDR_ADDR;
 #if CONFIG_DDR_CLK_FREQ == 100000000
 	__raw_writel(CONFIG_SYS_DDR_CS0_BNDS, &ddr->cs0_bnds);
 	__raw_writel(CONFIG_SYS_DDR_CS0_CONFIG, &ddr->cs0_config);
diff --git a/board/freescale/bsc9132qds/tlb.c b/board/freescale/bsc9132qds/tlb.c
index 02655e9baf..07febc2b37 100644
--- a/board/freescale/bsc9132qds/tlb.c
+++ b/board/freescale/bsc9132qds/tlb.c
@@ -30,7 +30,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
 	SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 0, BOOKE_PAGESZ_4K, 1),
-#ifdef CONFIG_SPL_NAND_MINIMAL
+#ifdef CONFIG_SPL_NAND_BOOT
 	SET_TLB_ENTRY(1, 0xffffe000, 0xffffe000,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 10, BOOKE_PAGESZ_4K, 1),
diff --git a/board/freescale/c29xpcie/Makefile b/board/freescale/c29xpcie/Makefile
index ab8eb8f729..818484a57d 100644
--- a/board/freescale/c29xpcie/Makefile
+++ b/board/freescale/c29xpcie/Makefile
@@ -3,28 +3,23 @@
 #
 # SPDX-License-Identifier:	GPL-2.0+
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS-y	+= $(BOARD).o
-COBJS-y	+= cpld.o
-COBJS-y	+= ddr.o
-COBJS-y	+= law.o
-COBJS-y	+= tlb.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS-y))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+MINIMAL=
+ifdef CONFIG_SPL_BUILD
+ifdef CONFIG_SPL_INIT_MINIMAL
+MINIMAL=y
+endif
+endif
+
+ifdef MINIMAL
+obj-y	+= spl_minimal.o tlb.o law.o
+else
+ifdef CONFIG_SPL_BUILD
+obj-y	+= spl.o
+endif
+
+obj-y	+= c29xpcie.o
+obj-y	+= cpld.o
+obj-y	+= ddr.o
+obj-y	+= law.o
+obj-y	+= tlb.o
+endif
diff --git a/board/freescale/c29xpcie/README b/board/freescale/c29xpcie/README
index 430f08244a..3bc396b35a 100644
--- a/board/freescale/c29xpcie/README
+++ b/board/freescale/c29xpcie/README
@@ -62,9 +62,9 @@ Build and program u-boot to NOR flash
 
 2. Program u-boot.bin into NOR flash
 	=> tftp $loadaddr $uboot
-	=> protect off eff80000 +$filesize
-	=> erase eff80000 +$filesize
-	=> cp.b $loadaddr eff80000 $filesize
+	=> protect off eff40000 +$filesize
+	=> erase eff40000 +$filesize
+	=> cp.b $loadaddr eff40000 $filesize
 
 3. Check SW5[1:4]= 1111 and SW5[6]=0, then power on.
 
@@ -73,9 +73,9 @@ Alternate NOR bank
 There are four banks in C29XPCIE board, example to change bank booting:
 1. Program u-boot.bin into alternate NOR bank
 	=> tftp $loadaddr $uboot
-	=> protect off e9f80000 +$filesize
-	=> erase e9f80000 +$filesize
-	=> cp.b $loadaddr e9f80000 $filesize
+	=> protect off e9f40000 +$filesize
+	=> erase e9f40000 +$filesize
+	=> cp.b $loadaddr e9f40000 $filesize
 
 2. Switch to alternate NOR bank
 	=> cpld_cmd reset altbank [bank]
diff --git a/board/freescale/c29xpcie/c29xpcie.c b/board/freescale/c29xpcie/c29xpcie.c
index 48c4b308be..f964d6185a 100644
--- a/board/freescale/c29xpcie/c29xpcie.c
+++ b/board/freescale/c29xpcie/c29xpcie.c
@@ -18,7 +18,7 @@
 #include <mmc.h>
 #include <netdev.h>
 #include <pci.h>
-#include <asm/fsl_ifc.h>
+#include <fsl_ifc.h>
 #include <asm/fsl_pci.h>
 
 #include "cpld.h"
diff --git a/board/freescale/c29xpcie/cpld.c b/board/freescale/c29xpcie/cpld.c
index 5cbccff633..37722daf5b 100644
--- a/board/freescale/c29xpcie/cpld.c
+++ b/board/freescale/c29xpcie/cpld.c
@@ -89,6 +89,7 @@ static void cpld_dump_regs(void)
 }
 #endif
 
+#ifndef CONFIG_SPL_BUILD
 int cpld_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 {
 	int rc = 0;
@@ -129,3 +130,4 @@ U_BOOT_CMD(
 	"cpld_cmd dump - display the CPLD registers\n"
 #endif
 	);
+#endif
diff --git a/board/freescale/c29xpcie/ddr.c b/board/freescale/c29xpcie/ddr.c
index b017cfd961..7c915b036f 100644
--- a/board/freescale/c29xpcie/ddr.c
+++ b/board/freescale/c29xpcie/ddr.c
@@ -5,10 +5,14 @@
  */
 
 #include <common.h>
+#include <i2c.h>
 #include <asm/fsl_law.h>
-#include <asm/fsl_ddr_sdram.h>
-#include <asm/fsl_ddr_dimm_params.h>
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr_dimm_params.h>
 
+#include "cpld.h"
+
+#define C29XPCIE_HARDWARE_REVA	0x40
 /*
  * Micron MT41J128M16HA-15E
  * */
@@ -26,20 +30,20 @@ dimm_params_t ddr_raw_timing = {
 	.edc_config = 2,
 	.burst_lengths_bitmask = 0x0c,
 
-	.tCKmin_X_ps = 1650,
-	.caslat_X = 0x7e << 4,	/* 5,6,7,8,9,10 */
-	.tAA_ps = 14050,
-	.tWR_ps = 15000,
-	.tRCD_ps = 13500,
-	.tRRD_ps = 75000,
-	.tRP_ps = 13500,
-	.tRAS_ps = 40000,
-	.tRC_ps = 49500,
-	.tRFC_ps = 160000,
-	.tWTR_ps = 75000,
-	.tRTP_ps = 75000,
+	.tckmin_x_ps = 1650,
+	.caslat_x = 0x7e << 4,	/* 5,6,7,8,9,10 */
+	.taa_ps = 14050,
+	.twr_ps = 15000,
+	.trcd_ps = 13500,
+	.trrd_ps = 75000,
+	.trp_ps = 13500,
+	.tras_ps = 40000,
+	.trc_ps = 49500,
+	.trfc_ps = 160000,
+	.twtr_ps = 75000,
+	.trtp_ps = 75000,
 	.refresh_rate_ps = 7800000,
-	.tFAW_ps = 30000,
+	.tfaw_ps = 30000,
 };
 
 int fsl_ddr_get_dimm_params(dimm_params_t *pdimm,
@@ -61,8 +65,10 @@ void fsl_ddr_board_options(memctl_options_t *popts,
 				dimm_params_t *pdimm,
 				unsigned int ctrl_num)
 {
+	struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
 	int i;
-	popts->clk_adjust = 2;
+
+	popts->clk_adjust = 4;
 	popts->cpo_override = 0x1f;
 	popts->write_data_delay = 4;
 	popts->half_strength_driver_enable = 1;
@@ -79,8 +85,23 @@ void fsl_ddr_board_options(memctl_options_t *popts,
 	popts->trwt_override = 1;
 	popts->trwt = 0;
 
+	if (in_8(&cpld_data->hwver) == C29XPCIE_HARDWARE_REVA)
+		popts->ecc_mode = 0;
+
 	for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
 		popts->cs_local_opts[i].odt_rd_cfg = FSL_DDR_ODT_NEVER;
 		popts->cs_local_opts[i].odt_wr_cfg = FSL_DDR_ODT_CS;
 	}
 }
+
+void get_spd(generic_spd_eeprom_t *spd, u8 i2c_address)
+{
+	int ret = i2c_read(i2c_address, 0, 2, (uint8_t *)spd,
+				sizeof(generic_spd_eeprom_t));
+
+	if (ret) {
+		printf("DDR: failed to read SPD from address %u\n",
+				i2c_address);
+		memset(spd, 0, sizeof(generic_spd_eeprom_t));
+	}
+}
diff --git a/board/freescale/c29xpcie/law.c b/board/freescale/c29xpcie/law.c
index cd8fc2105d..80e5fff7c5 100644
--- a/board/freescale/c29xpcie/law.c
+++ b/board/freescale/c29xpcie/law.c
@@ -10,8 +10,8 @@
 
 struct law_entry law_table[] = {
 	SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_64M, LAW_TRGT_IF_IFC),
-	SET_LAW(CONFIG_SYS_CPLD_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_IFC),
-	SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_16K, LAW_TRGT_IF_IFC),
+	SET_LAW(CONFIG_SYS_CPLD_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_IFC),
+	SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_IFC),
 	SET_LAW(CONFIG_SYS_PLATFORM_SRAM_BASE_PHYS, LAW_SIZE_512K,
 					LAW_TRGT_IF_PLATFORM_SRAM),
 };
diff --git a/board/freescale/c29xpcie/spl.c b/board/freescale/c29xpcie/spl.c
new file mode 100644
index 0000000000..2111711400
--- /dev/null
+++ b/board/freescale/c29xpcie/spl.c
@@ -0,0 +1,77 @@
+/* Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#include <common.h>
+#include <ns16550.h>
+#include <malloc.h>
+#include <mmc.h>
+#include <nand.h>
+#include <i2c.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+phys_size_t get_effective_memsize(void)
+{
+	return CONFIG_SYS_L2_SIZE;
+}
+
+void board_init_f(ulong bootflag)
+{
+	u32 plat_ratio;
+	ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
+
+	console_init_f();
+
+	/* initialize selected port with appropriate baud rate */
+	plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO;
+	plat_ratio >>= 1;
+	gd->bus_clk = CONFIG_SYS_CLK_FREQ * plat_ratio;
+
+	NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
+		     gd->bus_clk / 16 / CONFIG_BAUDRATE);
+
+	/* copy code to RAM and jump to it - this should not return */
+	/* NOTE - code has to be copied out of NAND buffer before
+	 * other blocks can be read.
+	 */
+	relocate_code(CONFIG_SPL_RELOC_STACK, 0, CONFIG_SPL_RELOC_TEXT_BASE);
+}
+
+void board_init_r(gd_t *gd, ulong dest_addr)
+{
+	/* Pointer is writable since we allocated a register for it */
+	gd = (gd_t *)CONFIG_SPL_GD_ADDR;
+	bd_t *bd;
+
+	memset(gd, 0, sizeof(gd_t));
+	bd = (bd_t *)(CONFIG_SPL_GD_ADDR + sizeof(gd_t));
+	memset(bd, 0, sizeof(bd_t));
+	gd->bd = bd;
+	bd->bi_memstart = CONFIG_SYS_INIT_L2_ADDR;
+	bd->bi_memsize = CONFIG_SYS_L2_SIZE;
+
+	probecpu();
+	get_clocks();
+	mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR,
+			CONFIG_SPL_RELOC_MALLOC_SIZE);
+
+	/* relocate environment function pointers etc. */
+	nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
+			    (uchar *)CONFIG_ENV_ADDR);
+	gd->env_addr  = (ulong)(CONFIG_ENV_ADDR);
+	gd->env_valid = 1;
+
+	i2c_init_all();
+
+	gd->ram_size = initdram(0);
+
+#ifdef CONFIG_SPL_NAND_BOOT
+	puts("TPL\n");
+#else
+	puts("SPL\n");
+#endif
+
+	nand_boot();
+}
diff --git a/board/freescale/c29xpcie/spl_minimal.c b/board/freescale/c29xpcie/spl_minimal.c
new file mode 100644
index 0000000000..8f96b67e84
--- /dev/null
+++ b/board/freescale/c29xpcie/spl_minimal.c
@@ -0,0 +1,63 @@
+/* Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#include <common.h>
+#include <mpc85xx.h>
+#include <asm/io.h>
+#include <ns16550.h>
+#include <nand.h>
+#include <asm/mmu.h>
+#include <asm/immap_85xx.h>
+#include <asm/fsl_law.h>
+#include <asm/global_data.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void board_init_f(ulong bootflag)
+{
+	u32 plat_ratio;
+	ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
+
+#if defined(CONFIG_SYS_NAND_BR_PRELIM) && defined(CONFIG_SYS_NAND_OR_PRELIM)
+	set_lbc_br(0, CONFIG_SYS_NAND_BR_PRELIM);
+	set_lbc_or(0, CONFIG_SYS_NAND_OR_PRELIM);
+#endif
+
+	/* initialize selected port with appropriate baud rate */
+	plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO;
+	plat_ratio >>= 1;
+	gd->bus_clk = CONFIG_SYS_CLK_FREQ * plat_ratio;
+
+	NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
+		     gd->bus_clk / 16 / CONFIG_BAUDRATE);
+
+	puts("\nNAND boot...\n");
+
+	/* copy code to RAM and jump to it - this should not return */
+	/* NOTE - code has to be copied out of NAND buffer before
+	 * other blocks can be read.
+	 */
+	relocate_code(CONFIG_SPL_RELOC_STACK, 0, CONFIG_SPL_RELOC_TEXT_BASE);
+}
+
+void board_init_r(gd_t *gd, ulong dest_addr)
+{
+	puts("SPL\n");
+	nand_boot();
+}
+
+void putc(char c)
+{
+	if (c == '\n')
+		NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, '\r');
+
+	NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, c);
+}
+
+void puts(const char *str)
+{
+	while (*str)
+		putc(*str++);
+}
diff --git a/board/freescale/c29xpcie/tlb.c b/board/freescale/c29xpcie/tlb.c
index ddd1ef80b2..c5abed0504 100644
--- a/board/freescale/c29xpcie/tlb.c
+++ b/board/freescale/c29xpcie/tlb.c
@@ -30,6 +30,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
 			MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 			0, 0, BOOKE_PAGESZ_1M, 1),
 
+#ifndef CONFIG_SPL_BUILD
 	SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
 			MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
 			0, 1, BOOKE_PAGESZ_64M, 1),
@@ -43,14 +44,15 @@ struct fsl_e_tlb_entry tlb_table[] = {
 			MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 			0, 3, BOOKE_PAGESZ_256K, 1),
 #endif
+#endif
 
 	SET_TLB_ENTRY(1, CONFIG_SYS_CPLD_BASE, CONFIG_SYS_CPLD_BASE_PHYS,
 			MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-			0, 4, BOOKE_PAGESZ_4K, 1),
+			0, 4, BOOKE_PAGESZ_64K, 1),
 
 	SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
-			MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-			0, 5, BOOKE_PAGESZ_16K, 1),
+			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+			0, 5, BOOKE_PAGESZ_64K, 1),
 
 	SET_TLB_ENTRY(1, CONFIG_SYS_PLATFORM_SRAM_BASE,
 			CONFIG_SYS_PLATFORM_SRAM_BASE_PHYS,
@@ -61,7 +63,8 @@ struct fsl_e_tlb_entry tlb_table[] = {
 			MAS3_SX|MAS3_SW|MAS3_SR, 0,
 			0, 7, BOOKE_PAGESZ_256K, 1),
 
-#ifdef CONFIG_SYS_RAMBOOT
+#if defined(CONFIG_SYS_RAMBOOT) || \
+		(defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD))
 	SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE,
 			CONFIG_SYS_DDR_SDRAM_BASE,
 			MAS3_SX|MAS3_SW|MAS3_SR, 0,
@@ -71,6 +74,12 @@ struct fsl_e_tlb_entry tlb_table[] = {
 			MAS3_SX|MAS3_SW|MAS3_SR, 0,
 			0, 9, BOOKE_PAGESZ_256M, 1),
 #endif
+
+#ifdef CONFIG_SYS_INIT_L2_ADDR
+	SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR, CONFIG_SYS_INIT_L2_ADDR_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_G,
+		      0, 12, BOOKE_PAGESZ_256K, 1)
+#endif
 };
 
 int num_tlb_entries = ARRAY_SIZE(tlb_table);
diff --git a/board/freescale/common/Makefile b/board/freescale/common/Makefile
index f9550c48ce..f6a0879753 100644
--- a/board/freescale/common/Makefile
+++ b/board/freescale/common/Makefile
@@ -5,14 +5,6 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-ifneq ($(OBJTREE),$(SRCTREE))
-$(shell mkdir -p $(obj)board/freescale/common)
-endif
-
-LIB	= $(obj)libfreescale.o
-
 MINIMAL=
 
 ifdef CONFIG_SPL_BUILD
@@ -21,63 +13,46 @@ MINIMAL=y
 endif
 endif
 
-ifndef MINIMAL
-COBJS-$(CONFIG_FSL_CADMUS)	+= cadmus.o
-COBJS-$(CONFIG_FSL_VIA)		+= cds_via.o
-COBJS-$(CONFIG_FMAN_ENET)	+= fman.o
-COBJS-$(CONFIG_FSL_PIXIS)	+= pixis.o
+ifdef MINIMAL
+# necessary to create built-in.o
+obj- := __dummy__.o
+else
+obj-$(CONFIG_FSL_CADMUS)	+= cadmus.o
+obj-$(CONFIG_FSL_VIA)		+= cds_via.o
+obj-$(CONFIG_FMAN_ENET)	+= fman.o
+obj-$(CONFIG_FSL_PIXIS)	+= pixis.o
 ifndef CONFIG_SPL_BUILD
-COBJS-$(CONFIG_FSL_NGPIXIS)	+= ngpixis.o
+obj-$(CONFIG_FSL_NGPIXIS)	+= ngpixis.o
 endif
-COBJS-$(CONFIG_FSL_QIXIS)	+= qixis.o
-COBJS-$(CONFIG_PQ_MDS_PIB)	+= pq-mds-pib.o
+obj-$(CONFIG_FSL_QIXIS)	+= qixis.o
+obj-$(CONFIG_PQ_MDS_PIB)	+= pq-mds-pib.o
 ifndef CONFIG_SPL_BUILD
-COBJS-$(CONFIG_ID_EEPROM)	+= sys_eeprom.o
+obj-$(CONFIG_ID_EEPROM)	+= sys_eeprom.o
 endif
-COBJS-$(CONFIG_FSL_SGMII_RISER)	+= sgmii_riser.o
+obj-$(CONFIG_FSL_SGMII_RISER)	+= sgmii_riser.o
 ifndef CONFIG_RAMBOOT_PBL
-COBJS-$(CONFIG_FSL_FIXED_MMC_LOCATION)	+= sdhc_boot.o
+obj-$(CONFIG_FSL_FIXED_MMC_LOCATION)	+= sdhc_boot.o
 endif
 
-COBJS-$(CONFIG_MPC8541CDS)	+= cds_pci_ft.o
-COBJS-$(CONFIG_MPC8548CDS)	+= cds_pci_ft.o
-COBJS-$(CONFIG_MPC8555CDS)	+= cds_pci_ft.o
-
-COBJS-$(CONFIG_MPC8536DS)	+= ics307_clk.o
-COBJS-$(CONFIG_MPC8572DS)	+= ics307_clk.o
-COBJS-$(CONFIG_P1022DS)		+= ics307_clk.o
-COBJS-$(CONFIG_P2020DS)		+= ics307_clk.o
-COBJS-$(CONFIG_P3041DS)		+= ics307_clk.o
-COBJS-$(CONFIG_P4080DS)		+= ics307_clk.o
-COBJS-$(CONFIG_P5020DS)		+= ics307_clk.o
-COBJS-$(CONFIG_P5040DS)		+= ics307_clk.o
-COBJS-$(CONFIG_VSC_CROSSBAR)    += vsc3316_3308.o
-COBJS-$(CONFIG_IDT8T49N222A)	+= idt8t49n222a_serdes_clk.o
+obj-$(CONFIG_MPC8541CDS)	+= cds_pci_ft.o
+obj-$(CONFIG_MPC8548CDS)	+= cds_pci_ft.o
+obj-$(CONFIG_MPC8555CDS)	+= cds_pci_ft.o
+
+obj-$(CONFIG_MPC8536DS)	+= ics307_clk.o
+obj-$(CONFIG_MPC8572DS)	+= ics307_clk.o
+obj-$(CONFIG_P1022DS)		+= ics307_clk.o
+obj-$(CONFIG_P2020DS)		+= ics307_clk.o
+obj-$(CONFIG_P3041DS)		+= ics307_clk.o
+obj-$(CONFIG_P4080DS)		+= ics307_clk.o
+obj-$(CONFIG_P5020DS)		+= ics307_clk.o
+obj-$(CONFIG_P5040DS)		+= ics307_clk.o
+obj-$(CONFIG_VSC_CROSSBAR)    += vsc3316_3308.o
+obj-$(CONFIG_IDT8T49N222A)	+= idt8t49n222a_serdes_clk.o
 
 # deal with common files for P-series corenet based devices
-SUBLIB-$(CONFIG_P2041RDB)	+= p_corenet/libp_corenet.o
-SUBLIB-$(CONFIG_P3041DS)	+= p_corenet/libp_corenet.o
-SUBLIB-$(CONFIG_P4080DS)	+= p_corenet/libp_corenet.o
-SUBLIB-$(CONFIG_P5020DS)	+= p_corenet/libp_corenet.o
-SUBLIB-$(CONFIG_P5040DS)	+= p_corenet/libp_corenet.o
+obj-$(CONFIG_P2041RDB)	+= p_corenet/
+obj-$(CONFIG_P3041DS)	+= p_corenet/
+obj-$(CONFIG_P4080DS)	+= p_corenet/
+obj-$(CONFIG_P5020DS)	+= p_corenet/
+obj-$(CONFIG_P5040DS)	+= p_corenet/
 endif
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS-y))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-SUBLIB	:= $(addprefix $(obj),$(SUBLIB-y))
-
-$(LIB):	$(obj).depend $(OBJS) $(SUBLIB)
-	$(call cmd_link_o_target, $(OBJS) $(SUBLIB))
-
-$(SUBLIB): $(obj).depend
-	$(MAKE) -C $(dir $(subst $(obj),,$@))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
diff --git a/board/freescale/common/p_corenet/Makefile b/board/freescale/common/p_corenet/Makefile
index f37b25cf83..1f399d2496 100644
--- a/board/freescale/common/p_corenet/Makefile
+++ b/board/freescale/common/p_corenet/Makefile
@@ -4,12 +4,7 @@
 #
 # SPDX-License-Identifier:	GPL-2.0+
 #
-include $(TOPDIR)/config.mk
 
-LIB	= libp_corenet.o
-
-COBJS-y			+= law.o
-COBJS-$(CONFIG_PCI)	+= pci.o
-COBJS-y			+= tlb.o
-
-include $(TOPDIR)/post/rules.mk
+obj-y			+= law.o
+obj-$(CONFIG_PCI)	+= pci.o
+obj-y			+= tlb.o
diff --git a/board/freescale/common/qixis.h b/board/freescale/common/qixis.h
index 26e2eeb2ff..d8fed14ce9 100644
--- a/board/freescale/common/qixis.h
+++ b/board/freescale/common/qixis.h
@@ -79,7 +79,9 @@ struct qixis {
 	u8 clk_freq[6];	/* Clock Measurement Registers */
 	u8 res_c6[8];
 	u8 clk_base[2];	/* Clock Frequency Base Reg */
-	u8 res_d0[16];
+	u8 res_d0[8];
+	u8 cms[2];	/* Core Management Space Address Register, 0xD8 */
+	u8 res_c0[6];
 	u8 aux2[4];	/* Auxiliary Registers,0xE0 */
 	u8 res14[10];
 	u8 aux_ad;
diff --git a/board/freescale/common/sdhc_boot.c b/board/freescale/common/sdhc_boot.c
index f6e2b2bbd6..022f38b117 100644
--- a/board/freescale/common/sdhc_boot.c
+++ b/board/freescale/common/sdhc_boot.c
@@ -16,6 +16,8 @@
 #define ESDHC_BOOT_IMAGE_SIZE	0x48
 #define ESDHC_BOOT_IMAGE_ADDR	0x50
 
+#define ESDHC_DEFAULT_ENVADDR	0x400
+
 int mmc_get_env_addr(struct mmc *mmc, int copy, u32 *env_addr)
 {
 	u8 *tmp_buf;
@@ -39,6 +41,33 @@ int mmc_get_env_addr(struct mmc *mmc, int copy, u32 *env_addr)
 	/* Get the code size from offset 0x48 */
 	code_len = *(u32 *)(tmp_buf + ESDHC_BOOT_IMAGE_SIZE);
 
+#ifdef CONFIG_ESDHC_HC_BLK_ADDR
+	/*
+	 * On soc BSC9131, BSC9132:
+	 * In High Capacity SD Cards (> 2 GBytes), the 32-bit source address and
+	 * code length of these soc specify the memory address in block address
+	 * format. Block length is fixed to 512 bytes as per the SD High
+	 * Capacity specification.
+	 */
+	u64 tmp;
+
+	if (mmc->high_capacity) {
+		tmp = (u64)code_offset * blklen;
+		tmp += code_len * blklen;
+	} else
+		tmp = code_offset + code_len;
+
+	if ((tmp + CONFIG_ENV_SIZE > mmc->capacity) ||
+			(tmp > 0xFFFFFFFFU))
+		*env_addr = ESDHC_DEFAULT_ENVADDR;
+	else
+		*env_addr = tmp;
+
+	free(tmp_buf);
+
+	return 0;
+#endif
+
 	*env_addr = code_offset + code_len;
 
 	free(tmp_buf);
diff --git a/board/freescale/common/sys_eeprom.c b/board/freescale/common/sys_eeprom.c
index d7893644cd..9c18dd8242 100644
--- a/board/freescale/common/sys_eeprom.c
+++ b/board/freescale/common/sys_eeprom.c
@@ -18,7 +18,11 @@
 #endif
 
 #ifdef CONFIG_SYS_I2C_EEPROM_NXID
+/* some boards with non-256-bytes EEPROM have special define */
+/* for MAX_NUM_PORTS in board-specific file */
+#ifndef MAX_NUM_PORTS
 #define MAX_NUM_PORTS	23
+#endif
 #define NXID_VERSION	1
 #endif
 
diff --git a/board/freescale/corenet_ds/Makefile b/board/freescale/corenet_ds/Makefile
index 36813cbcec..9ade9472ea 100644
--- a/board/freescale/corenet_ds/Makefile
+++ b/board/freescale/corenet_ds/Makefile
@@ -6,33 +6,13 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS-y	+= $(BOARD).o
-COBJS-y	+= ddr.o
-COBJS-$(CONFIG_P3041DS)	+= eth_hydra.o
-COBJS-$(CONFIG_P4080DS)	+= eth_p4080.o
-COBJS-$(CONFIG_P5020DS)	+= eth_hydra.o
-COBJS-$(CONFIG_P5040DS)	+= eth_superhydra.o
-COBJS-$(CONFIG_P3041DS)	+= p3041ds_ddr.o
-COBJS-$(CONFIG_P4080DS)	+= p4080ds_ddr.o
-COBJS-$(CONFIG_P5020DS)	+= p5020ds_ddr.o
-COBJS-$(CONFIG_P5040DS)	+= p5040ds_ddr.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS-y))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	+= corenet_ds.o
+obj-y	+= ddr.o
+obj-$(CONFIG_P3041DS)	+= eth_hydra.o
+obj-$(CONFIG_P4080DS)	+= eth_p4080.o
+obj-$(CONFIG_P5020DS)	+= eth_hydra.o
+obj-$(CONFIG_P5040DS)	+= eth_superhydra.o
+obj-$(CONFIG_P3041DS)	+= p3041ds_ddr.o
+obj-$(CONFIG_P4080DS)	+= p4080ds_ddr.o
+obj-$(CONFIG_P5020DS)	+= p5020ds_ddr.o
+obj-$(CONFIG_P5040DS)	+= p5040ds_ddr.o
diff --git a/board/freescale/corenet_ds/corenet_ds.c b/board/freescale/corenet_ds/corenet_ds.c
index 60e2100af3..9212372fee 100644
--- a/board/freescale/corenet_ds/corenet_ds.c
+++ b/board/freescale/corenet_ds/corenet_ds.c
@@ -127,20 +127,6 @@ int board_early_init_r(void)
 	return 0;
 }
 
-static const char *serdes_clock_to_string(u32 clock)
-{
-	switch(clock) {
-	case SRDS_PLLCR0_RFCK_SEL_100:
-		return "100";
-	case SRDS_PLLCR0_RFCK_SEL_125:
-		return "125";
-	case SRDS_PLLCR0_RFCK_SEL_156_25:
-		return "156.25";
-	default:
-		return "150";
-	}
-}
-
 #define NUM_SRDS_BANKS	3
 
 int misc_init_r(void)
diff --git a/board/freescale/corenet_ds/ddr.c b/board/freescale/corenet_ds/ddr.c
index 517e87ff4c..e7e893a1ae 100644
--- a/board/freescale/corenet_ds/ddr.c
+++ b/board/freescale/corenet_ds/ddr.c
@@ -10,8 +10,8 @@
 #include <i2c.h>
 #include <hwconfig.h>
 #include <asm/mmu.h>
-#include <asm/fsl_ddr_sdram.h>
-#include <asm/fsl_ddr_dimm_params.h>
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr_dimm_params.h>
 #include <asm/fsl_law.h>
 
 DECLARE_GLOBAL_DATA_PTR;
@@ -114,7 +114,7 @@ struct board_specific_parameters {
 	u32 wrlvl_start;
 	u32 cpo;
 	u32 write_data_delay;
-	u32 force_2T;
+	u32 force_2t;
 };
 
 /*
@@ -217,7 +217,7 @@ void fsl_ddr_board_options(memctl_options_t *popts,
 					pbsp->write_data_delay;
 				popts->clk_adjust = pbsp->clk_adjust;
 				popts->wrlvl_start = pbsp->wrlvl_start;
-				popts->twoT_en = pbsp->force_2T;
+				popts->twot_en = pbsp->force_2t;
 				goto found;
 			}
 			pbsp_highest = pbsp;
@@ -234,7 +234,7 @@ void fsl_ddr_board_options(memctl_options_t *popts,
 		popts->write_data_delay = pbsp_highest->write_data_delay;
 		popts->clk_adjust = pbsp_highest->clk_adjust;
 		popts->wrlvl_start = pbsp_highest->wrlvl_start;
-		popts->twoT_en = pbsp_highest->force_2T;
+		popts->twot_en = pbsp_highest->force_2t;
 	} else {
 		panic("DIMM is not supported by this board");
 	}
diff --git a/board/freescale/corenet_ds/eth_hydra.c b/board/freescale/corenet_ds/eth_hydra.c
index a594efcada..35825c4ae9 100644
--- a/board/freescale/corenet_ds/eth_hydra.c
+++ b/board/freescale/corenet_ds/eth_hydra.c
@@ -76,6 +76,8 @@
 
 #define BRDCFG2_REG_GPIO_SEL	0x20
 
+#define PHY_BASE_ADDR		0x00
+
 /*
  * BRDCFG1 mask and value for each MAC
  *
@@ -365,6 +367,7 @@ int board_eth_init(bd_t *bis)
 	struct tgec_mdio_info tgec_mdio_info;
 	unsigned int i, slot;
 	int lane;
+	struct mii_dev *bus;
 
 	printf("Initializing Fman\n");
 
@@ -470,6 +473,9 @@ int board_eth_init(bd_t *bis)
 		}
 	}
 
+	bus = miiphy_get_dev_by_name("HYDRA_SGMII_MDIO");
+	set_sgmii_phy(bus, FM1_DTSEC1, CONFIG_SYS_NUM_FM1_DTSEC, PHY_BASE_ADDR);
+
 	/*
 	 * For 10G, we only support one XAUI card per Fman.  If present, then we
 	 * force its routing and never touch those bits again, which removes the
diff --git a/board/freescale/corenet_ds/eth_p4080.c b/board/freescale/corenet_ds/eth_p4080.c
index 597d0cbf2e..5cbec7f5f2 100644
--- a/board/freescale/corenet_ds/eth_p4080.c
+++ b/board/freescale/corenet_ds/eth_p4080.c
@@ -12,7 +12,7 @@
 #include <asm/cache.h>
 #include <asm/immap_85xx.h>
 #include <asm/fsl_law.h>
-#include <asm/fsl_ddr_sdram.h>
+#include <fsl_ddr_sdram.h>
 #include <asm/fsl_serdes.h>
 #include <asm/fsl_portals.h>
 #include <asm/fsl_liodn.h>
@@ -37,6 +37,9 @@
 #define EMI1_MASK	0xc0000000
 #define EMI2_MASK	0x30000000
 
+#define PHY_BASE_ADDR	0x00
+#define PHY_BASE_ADDR_SLOT5	0x10
+
 static int mdio_mux[NUM_FM_PORTS];
 
 static char *mdio_names[16] = {
@@ -290,6 +293,7 @@ int board_eth_init(bd_t *bis)
 	int i;
 	struct fsl_pq_mdio_info dtsec_mdio_info;
 	struct tgec_mdio_info tgec_mdio_info;
+	struct mii_dev *bus;
 
 	/* Initialize the mdio_mux array so we can recognize empty elements */
 	for (i = 0; i < NUM_FM_PORTS; i++)
@@ -370,6 +374,9 @@ int board_eth_init(bd_t *bis)
 			break;
 		}
 	}
+	bus = mii_dev_for_muxval(EMI1_SLOT5);
+	set_sgmii_phy(bus, FM1_DTSEC1,
+		      CONFIG_SYS_NUM_FM1_DTSEC, PHY_BASE_ADDR_SLOT5);
 
 	for (i = FM1_10GEC1; i < FM1_10GEC1 + CONFIG_SYS_NUM_FM1_10GEC; i++) {
 		int idx = i - FM1_10GEC1, lane, slot;
@@ -435,6 +442,11 @@ int board_eth_init(bd_t *bis)
 		}
 	}
 
+	bus = mii_dev_for_muxval(EMI1_SLOT3);
+	set_sgmii_phy(bus, FM2_DTSEC1, CONFIG_SYS_NUM_FM2_DTSEC, PHY_BASE_ADDR);
+	bus = mii_dev_for_muxval(EMI1_SLOT4);
+	set_sgmii_phy(bus, FM2_DTSEC1, CONFIG_SYS_NUM_FM2_DTSEC, PHY_BASE_ADDR);
+
 	for (i = FM2_10GEC1; i < FM2_10GEC1 + CONFIG_SYS_NUM_FM2_10GEC; i++) {
 		int idx = i - FM2_10GEC1, lane, slot;
 		switch (fm_info_get_enet_if(i)) {
diff --git a/board/freescale/corenet_ds/eth_superhydra.c b/board/freescale/corenet_ds/eth_superhydra.c
index fa07ff333e..ad1bffd74b 100644
--- a/board/freescale/corenet_ds/eth_superhydra.c
+++ b/board/freescale/corenet_ds/eth_superhydra.c
@@ -77,6 +77,12 @@
 
 #define BRDCFG2_REG_GPIO_SEL	0x20
 
+/* SGMII */
+#define PHY_BASE_ADDR		0x00
+#define REGNUM			0x00
+#define PORT_NUM_FM1		0x04
+#define PORT_NUM_FM2		0x02
+
 /*
  * BRDCFG1 mask and value for each MAC
  *
@@ -415,6 +421,9 @@ int board_eth_init(bd_t *bis)
 	struct tgec_mdio_info tgec_mdio_info;
 	unsigned int i, slot;
 	int lane;
+	struct mii_dev *bus;
+	int qsgmii;
+	int phy_real_addr;
 	ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 	int srds_prtcl = (in_be32(&gur->rcwsr[4]) &
 				FSL_CORENET_RCWSR4_SRDS_PRTCL) >> 26;
@@ -449,6 +458,8 @@ int board_eth_init(bd_t *bis)
 				"SUPER_HYDRA_FM1_SGMII_MDIO");
 	super_hydra_mdio_init(DEFAULT_FM_MDIO_NAME,
 				"SUPER_HYDRA_FM2_SGMII_MDIO");
+	super_hydra_mdio_init(DEFAULT_FM_MDIO_NAME,
+			      "SUPER_HYDRA_FM3_SGMII_MDIO");
 	super_hydra_mdio_init(DEFAULT_FM_TGEC_MDIO_NAME,
 				"SUPER_HYDRA_FM1_TGEC_MDIO");
 	super_hydra_mdio_init(DEFAULT_FM_TGEC_MDIO_NAME,
@@ -573,6 +584,42 @@ int board_eth_init(bd_t *bis)
 		}
 	}
 
+	bus = miiphy_get_dev_by_name("SUPER_HYDRA_FM1_SGMII_MDIO");
+	qsgmii = is_qsgmii_riser_card(bus, PHY_BASE_ADDR, PORT_NUM_FM1, REGNUM);
+
+	if (qsgmii) {
+		for (i = FM1_DTSEC1; i < FM1_DTSEC1 + PORT_NUM_FM1; i++) {
+			if (fm_info_get_enet_if(i) ==
+					PHY_INTERFACE_MODE_SGMII) {
+				phy_real_addr = PHY_BASE_ADDR + i - FM1_DTSEC1;
+				fm_info_set_phy_address(i, phy_real_addr);
+			}
+		}
+		switch (srds_prtcl) {
+		case 0x00:
+		case 0x03:
+		case 0x04:
+		case 0x06:
+		case 0x11:
+		case 0x2a:
+		case 0x34:
+		case 0x36:
+			fm_info_set_phy_address(FM1_DTSEC3, PHY_BASE_ADDR + 2);
+			fm_info_set_phy_address(FM1_DTSEC4, PHY_BASE_ADDR + 3);
+			break;
+		case 0x01:
+		case 0x02:
+		case 0x05:
+		case 0x07:
+		case 0x35:
+			fm_info_set_phy_address(FM1_DTSEC3, PHY_BASE_ADDR + 0);
+			fm_info_set_phy_address(FM1_DTSEC4, PHY_BASE_ADDR + 1);
+			break;
+		default:
+			break;
+		}
+	}
+
 	/*
 	 * For 10G, we only support one XAUI card per Fman.  If present, then we
 	 * force its routing and never touch those bits again, which removes the
@@ -638,10 +685,22 @@ int board_eth_init(bd_t *bis)
 				break;
 			};
 
-			super_hydra_mdio_set_mux("SUPER_HYDRA_FM2_SGMII_MDIO",
-					mdio_mux[i].mask, mdio_mux[i].val);
-			fm_info_set_mdio(i,
-			miiphy_get_dev_by_name("SUPER_HYDRA_FM2_SGMII_MDIO"));
+			if (i == FM2_DTSEC1 || i == FM2_DTSEC2) {
+				super_hydra_mdio_set_mux(
+						"SUPER_HYDRA_FM3_SGMII_MDIO",
+						mdio_mux[i].mask,
+						mdio_mux[i].val);
+				fm_info_set_mdio(i, miiphy_get_dev_by_name(
+						"SUPER_HYDRA_FM3_SGMII_MDIO"));
+			} else {
+				super_hydra_mdio_set_mux(
+						"SUPER_HYDRA_FM2_SGMII_MDIO",
+						mdio_mux[i].mask,
+						mdio_mux[i].val);
+				fm_info_set_mdio(i, miiphy_get_dev_by_name(
+						"SUPER_HYDRA_FM2_SGMII_MDIO"));
+			}
+
 			break;
 		case PHY_INTERFACE_MODE_RGMII:
 			/*
@@ -672,6 +731,11 @@ int board_eth_init(bd_t *bis)
 		}
 	}
 
+	bus = miiphy_get_dev_by_name("SUPER_HYDRA_FM2_SGMII_MDIO");
+	set_sgmii_phy(bus, FM2_DTSEC3, PORT_NUM_FM2, PHY_BASE_ADDR);
+	bus = miiphy_get_dev_by_name("SUPER_HYDRA_FM3_SGMII_MDIO");
+	set_sgmii_phy(bus, FM2_DTSEC1, PORT_NUM_FM2, PHY_BASE_ADDR);
+
 	/*
 	 * For 10G, we only support one XAUI card per Fman.  If present, then we
 	 * force its routing and never touch those bits again, which removes the
diff --git a/board/freescale/corenet_ds/p3041ds_ddr.c b/board/freescale/corenet_ds/p3041ds_ddr.c
index 5a8ed94b04..4dead9c045 100644
--- a/board/freescale/corenet_ds/p3041ds_ddr.c
+++ b/board/freescale/corenet_ds/p3041ds_ddr.c
@@ -7,7 +7,7 @@
  */
 
 #include <common.h>
-#include <asm/fsl_ddr_sdram.h>
+#include <fsl_ddr_sdram.h>
 
 fixed_ddr_parm_t fixed_ddr_parm_0[] = {
 	{0, 0, NULL}
diff --git a/board/freescale/corenet_ds/p4080ds_ddr.c b/board/freescale/corenet_ds/p4080ds_ddr.c
index 844e1d736a..d572a5fbed 100644
--- a/board/freescale/corenet_ds/p4080ds_ddr.c
+++ b/board/freescale/corenet_ds/p4080ds_ddr.c
@@ -7,7 +7,7 @@
  */
 
 #include <common.h>
-#include <asm/fsl_ddr_sdram.h>
+#include <fsl_ddr_sdram.h>
 
 #define CONFIG_SYS_DDR_TIMING_3_1200	0x01030000
 #define CONFIG_SYS_DDR_TIMING_0_1200	0xCC550104
diff --git a/board/freescale/corenet_ds/p5020ds_ddr.c b/board/freescale/corenet_ds/p5020ds_ddr.c
index e65de364d7..9aaf6db997 100644
--- a/board/freescale/corenet_ds/p5020ds_ddr.c
+++ b/board/freescale/corenet_ds/p5020ds_ddr.c
@@ -7,7 +7,7 @@
  */
 
 #include <common.h>
-#include <asm/fsl_ddr_sdram.h>
+#include <fsl_ddr_sdram.h>
 
 fixed_ddr_parm_t fixed_ddr_parm_0[] = {
 	{0, 0, NULL}
diff --git a/board/freescale/corenet_ds/p5040ds_ddr.c b/board/freescale/corenet_ds/p5040ds_ddr.c
index e65de364d7..9aaf6db997 100644
--- a/board/freescale/corenet_ds/p5040ds_ddr.c
+++ b/board/freescale/corenet_ds/p5040ds_ddr.c
@@ -7,7 +7,7 @@
  */
 
 #include <common.h>
-#include <asm/fsl_ddr_sdram.h>
+#include <fsl_ddr_sdram.h>
 
 fixed_ddr_parm_t fixed_ddr_parm_0[] = {
 	{0, 0, NULL}
diff --git a/board/freescale/m5208evbe/Makefile b/board/freescale/m5208evbe/Makefile
index d6be84f75f..1cb17fe39c 100644
--- a/board/freescale/m5208evbe/Makefile
+++ b/board/freescale/m5208evbe/Makefile
@@ -5,24 +5,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	= $(BOARD).o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	= m5208evbe.o
diff --git a/board/freescale/m52277evb/Makefile b/board/freescale/m52277evb/Makefile
index d6be84f75f..6b3b8aee60 100644
--- a/board/freescale/m52277evb/Makefile
+++ b/board/freescale/m52277evb/Makefile
@@ -5,24 +5,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	= $(BOARD).o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	= m52277evb.o
diff --git a/board/freescale/m52277evb/config.mk b/board/freescale/m52277evb/config.mk
deleted file mode 100644
index 0ffb0a204b..0000000000
--- a/board/freescale/m52277evb/config.mk
+++ /dev/null
@@ -1,11 +0,0 @@
-#
-# (C) Copyright 2000-2003
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-# Coldfire contribution by Bernhard Kuhn <bkuhn@metrowerks.com>
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp
-
-PLATFORM_CPPFLAGS += -DCONFIG_SYS_TEXT_BASE=$(CONFIG_SYS_TEXT_BASE)
diff --git a/board/freescale/m52277evb/u-boot.lds b/board/freescale/m52277evb/u-boot.lds
index f3337a3845..70121d9248 100644
--- a/board/freescale/m52277evb/u-boot.lds
+++ b/board/freescale/m52277evb/u-boot.lds
@@ -13,8 +13,8 @@ SECTIONS
   .text      :
   {
     arch/m68k/cpu/mcf5227x/start.o	(.text*)
-    arch/m68k/cpu/mcf5227x/libmcf5227x.o	(.text*)
-    arch/m68k/lib/libm68k.o		(.text*)
+    arch/m68k/cpu/mcf5227x/built-in.o	(.text*)
+    arch/m68k/lib/built-in.o		(.text*)
 
     *(.text*)
   }
diff --git a/board/freescale/m5235evb/Makefile b/board/freescale/m5235evb/Makefile
index d6be84f75f..e77d9d95b1 100644
--- a/board/freescale/m5235evb/Makefile
+++ b/board/freescale/m5235evb/Makefile
@@ -5,24 +5,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	= $(BOARD).o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	= m5235evb.o
diff --git a/board/freescale/m5235evb/config.mk b/board/freescale/m5235evb/config.mk
deleted file mode 100644
index 9ab4582bf8..0000000000
--- a/board/freescale/m5235evb/config.mk
+++ /dev/null
@@ -1,12 +0,0 @@
-#
-# (C) Copyright 2000-2003
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-# Coldfire contribution by Bernhard Kuhn <bkuhn@metrowerks.com>
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-/*CONFIG_SYS_TEXT_BASE = 0xFFC00000*/
-sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp
-
-PLATFORM_CPPFLAGS += -DCONFIG_SYS_TEXT_BASE=$(CONFIG_SYS_TEXT_BASE)
diff --git a/board/freescale/m5249evb/Makefile b/board/freescale/m5249evb/Makefile
index e7f4fb63b0..4267633f52 100644
--- a/board/freescale/m5249evb/Makefile
+++ b/board/freescale/m5249evb/Makefile
@@ -5,24 +5,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	= $(BOARD).o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	= m5249evb.o
diff --git a/board/freescale/m5253demo/Makefile b/board/freescale/m5253demo/Makefile
index 871865b6ee..62f3146fe3 100644
--- a/board/freescale/m5253demo/Makefile
+++ b/board/freescale/m5253demo/Makefile
@@ -5,24 +5,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	= $(BOARD).o flash.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	= m5253demo.o flash.o
diff --git a/board/freescale/m5253evbe/Makefile b/board/freescale/m5253evbe/Makefile
index e7f4fb63b0..8c55075c7a 100644
--- a/board/freescale/m5253evbe/Makefile
+++ b/board/freescale/m5253evbe/Makefile
@@ -5,24 +5,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	= $(BOARD).o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	= m5253evbe.o
diff --git a/board/freescale/m5271evb/Makefile b/board/freescale/m5271evb/Makefile
deleted file mode 100644
index e7f4fb63b0..0000000000
--- a/board/freescale/m5271evb/Makefile
+++ /dev/null
@@ -1,28 +0,0 @@
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	= $(BOARD).o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
diff --git a/board/freescale/m5271evb/config.mk b/board/freescale/m5271evb/config.mk
deleted file mode 100644
index 957f584887..0000000000
--- a/board/freescale/m5271evb/config.mk
+++ /dev/null
@@ -1,9 +0,0 @@
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-# Coldfire contribution by Bernhard Kuhn <bkuhn@metrowerks.com>
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-CONFIG_SYS_TEXT_BASE = 0xffe00000
diff --git a/board/freescale/m5271evb/m5271evb.c b/board/freescale/m5271evb/m5271evb.c
deleted file mode 100644
index 5981a2711a..0000000000
--- a/board/freescale/m5271evb/m5271evb.c
+++ /dev/null
@@ -1,115 +0,0 @@
-/*
- * (C) Copyright 2000-2006
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/immap.h>
-
-int checkboard (void) {
-	puts ("Board: Freescale M5271EVB\n");
-	return 0;
-};
-
-phys_size_t initdram (int board_type) {
-
-	int i;
-
-	/* Enable Address lines 23-21 and lower 16bits of data path */
-	mbar_writeByte(MCF_GPIO_PAR_AD, MCF_GPIO_AD_ADDR23 |
-			MCF_GPIO_AD_ADDR22 | MCF_GPIO_AD_ADDR21 |
-			MCF_GPIO_AD_DATAL);
-
-	/* Set CS2 pin to be SD_CS0 */
-	mbar_writeByte(MCF_GPIO_PAR_CS, mbar_readByte(MCF_GPIO_PAR_CS)
-			| MCF_GPIO_PAR_CS_PAR_CS2);
-
-	/* Configure SDRAM Control Pin Assignemnt Register */
-	mbar_writeByte(MCF_GPIO_PAR_SDRAM, MCF_GPIO_SDRAM_CSSDCS_00 |
-			MCF_GPIO_SDRAM_SDWE | MCF_GPIO_SDRAM_SCAS |
-			MCF_GPIO_SDRAM_SRAS | MCF_GPIO_SDRAM_SCKE |
-			MCF_GPIO_SDRAM_SDCS_11);
-	asm(" nop");
-
-	/*
-	 * Check to see if the SDRAM has already been initialized
-	 * by a run control tool
-	 */
-	if (!(mbar_readLong(MCF_SDRAMC_DACR0) & MCF_SDRAMC_DACRn_RE)) {
-		/* Initialize DRAM Control Register: DCR */
-		mbar_writeShort(MCF_SDRAMC_DCR,
-				MCF_SDRAMC_DCR_RTIM(2)
-				| MCF_SDRAMC_DCR_RC(0x2E));
-		asm(" nop");
-
-		/*
-		 * Initialize DACR0
-		 *
-		 * CASL: 01
-		 * CBM: cmd at A20, bank select bits 21 and up
-		 * PS: 32bit port size
-		 */
-		mbar_writeLong(MCF_SDRAMC_DACR0,
-				MCF_SDRAMC_DACRn_BA(CONFIG_SYS_SDRAM_BASE>>18)
-				| MCF_SDRAMC_DACRn_CASL(1)
-				| MCF_SDRAMC_DACRn_CBM(3)
-				| MCF_SDRAMC_DACRn_PS(0));
-		asm(" nop");
-
-		/* Initialize DMR0 */
-		mbar_writeLong(MCF_SDRAMC_DMR0,
-				MCF_SDRAMC_DMRn_BAM_16M
-				| MCF_SDRAMC_DMRn_V);
-		asm(" nop");
-
-		/* Set IP bit in DACR */
-		mbar_writeLong(MCF_SDRAMC_DACR0, mbar_readLong(MCF_SDRAMC_DACR0)
-				| MCF_SDRAMC_DACRn_IP);
-		asm(" nop");
-
-		/* Wait at least 20ns to allow banks to precharge */
-		for (i = 0; i < 5; i++)
-			asm(" nop");
-
-		/* Write to this block to initiate precharge */
-		*(u32 *)(CONFIG_SYS_SDRAM_BASE) = 0xa5a5a5a5;
-		asm(" nop");
-
-		/* Set RE bit in DACR */
-		mbar_writeLong(MCF_SDRAMC_DACR0, mbar_readLong(MCF_SDRAMC_DACR0)
-				| MCF_SDRAMC_DACRn_RE);
-
-		/* Wait for at least 8 auto refresh cycles to occur */
-		for (i = 0; i < 2000; i++)
-			asm(" nop");
-
-		/* Finish the configuration by issuing the MRS */
-		mbar_writeLong(MCF_SDRAMC_DACR0, mbar_readLong(MCF_SDRAMC_DACR0)
-				| MCF_SDRAMC_DACRn_MRS);
-		asm(" nop");
-
-		/*
-		 * Write to the SDRAM Mode Register A0-A11 = 0x400
-		 *
-		 * Write Burst Mode = Programmed Burst Length
-		 * Op Mode = Standard Op
-		 * CAS Latency = 2
-		 * Burst Type = Sequential
-		 * Burst Length = 1
-		 */
-		*(u32 *)(CONFIG_SYS_SDRAM_BASE + 0x400) = 0xa5a5a5a5;
-		asm(" nop");
-	}
-
-	return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
-};
-
-int testdram (void) {
-
-	/* TODO: XXX XXX XXX */
-	printf ("DRAM test not implemented!\n");
-
-	return (0);
-}
diff --git a/board/freescale/m5271evb/u-boot.lds b/board/freescale/m5271evb/u-boot.lds
deleted file mode 100644
index 3defcd25c1..0000000000
--- a/board/freescale/m5271evb/u-boot.lds
+++ /dev/null
@@ -1,85 +0,0 @@
-/*
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-OUTPUT_ARCH(m68k)
-
-SECTIONS
-{
-  .text      :
-  {
-    arch/m68k/cpu/mcf52x2/start.o		(.text*)
-
-    . = DEFINED(env_offset) ? env_offset : .;
-    common/env_embedded.o	(.ppcenv)
-
-    *(.text*)
-  }
-  _etext = .;
-  PROVIDE (etext = .);
-  .rodata    :
-  {
-    *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
-  }
-
-  /* Read-write section, merged into data segment: */
-  . = (. + 0x00FF) & 0xFFFFFF00;
-  _erotext = .;
-  PROVIDE (erotext = .);
-
-  .reloc   :
-  {
-    __got_start = .;
-    KEEP(*(.got))
-    __got_end = .;
-    _GOT2_TABLE_ = .;
-    KEEP(*(.got2))
-    _FIXUP_TABLE_ = .;
-    KEEP(*(.fixup))
-  }
-  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
-  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
-
-  .data    :
-  {
-    *(.data*)
-    *(.sdata*)
-  }
-  _edata  =  .;
-  PROVIDE (edata = .);
-
-  . = .;
-
-  . = ALIGN(4);
-  .u_boot_list : {
-	KEEP(*(SORT(.u_boot_list*)));
-  }
-
-  . = .;
-  __start___ex_table = .;
-  __ex_table : { *(__ex_table) }
-  __stop___ex_table = .;
-
-  . = ALIGN(256);
-  __init_begin = .;
-  .text.init : { *(.text.init) }
-  .data.init : { *(.data.init) }
-  . = ALIGN(256);
-  __init_end = .;
-
-  __bss_start = .;
-  .bss (NOLOAD)      :
-  {
-   _sbss = .;
-   *(.bss*)
-   *(.sbss*)
-   *(COMMON)
-   . = ALIGN(4);
-   _ebss = .;
-  }
-  __bss_end = . ;
-  PROVIDE (end = .);
-}
diff --git a/board/freescale/m5272c3/Makefile b/board/freescale/m5272c3/Makefile
index e7f4fb63b0..10a45f10fc 100644
--- a/board/freescale/m5272c3/Makefile
+++ b/board/freescale/m5272c3/Makefile
@@ -5,24 +5,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	= $(BOARD).o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	= m5272c3.o
diff --git a/board/freescale/m5275evb/Makefile b/board/freescale/m5275evb/Makefile
index d6be84f75f..d285c14598 100644
--- a/board/freescale/m5275evb/Makefile
+++ b/board/freescale/m5275evb/Makefile
@@ -5,24 +5,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	= $(BOARD).o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	= m5275evb.o
diff --git a/board/freescale/m5282evb/Makefile b/board/freescale/m5282evb/Makefile
index e7f4fb63b0..dab8f72e72 100644
--- a/board/freescale/m5282evb/Makefile
+++ b/board/freescale/m5282evb/Makefile
@@ -5,24 +5,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	= $(BOARD).o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	= m5282evb.o
diff --git a/board/freescale/m53017evb/Makefile b/board/freescale/m53017evb/Makefile
index d6be84f75f..bc4bf4a957 100644
--- a/board/freescale/m53017evb/Makefile
+++ b/board/freescale/m53017evb/Makefile
@@ -5,24 +5,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	= $(BOARD).o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	= m53017evb.o
diff --git a/board/freescale/m53017evb/u-boot.lds b/board/freescale/m53017evb/u-boot.lds
index ef21299ea9..de8d09bf66 100644
--- a/board/freescale/m53017evb/u-boot.lds
+++ b/board/freescale/m53017evb/u-boot.lds
@@ -12,9 +12,9 @@ SECTIONS
   /* Read-only sections, merged into text segment: */
   .text      :
   {
-    arch/m68k/cpu/mcf532x/start.o		(.text*)
-    arch/m68k/cpu/mcf532x/libmcf532x.o	(.text*)
-    arch/m68k/lib/libm68k.o		(.text*)
+    arch/m68k/cpu/mcf532x/start.o	(.text*)
+    arch/m68k/cpu/mcf532x/built-in.o	(.text*)
+    arch/m68k/lib/built-in.o		(.text*)
 
     . = DEFINED(env_offset) ? env_offset : .;
     common/env_embedded.o	(.text*)
diff --git a/board/freescale/m5329evb/Makefile b/board/freescale/m5329evb/Makefile
index 79aa8362ed..d8dbafaa8f 100644
--- a/board/freescale/m5329evb/Makefile
+++ b/board/freescale/m5329evb/Makefile
@@ -5,24 +5,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	= $(BOARD).o nand.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	= m5329evb.o nand.o
diff --git a/board/freescale/m5373evb/Makefile b/board/freescale/m5373evb/Makefile
index 79aa8362ed..d34e327597 100644
--- a/board/freescale/m5373evb/Makefile
+++ b/board/freescale/m5373evb/Makefile
@@ -5,24 +5,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	= $(BOARD).o nand.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	= m5373evb.o nand.o
diff --git a/board/freescale/m54418twr/Makefile b/board/freescale/m54418twr/Makefile
index dc40f300f9..371c04abe8 100644
--- a/board/freescale/m54418twr/Makefile
+++ b/board/freescale/m54418twr/Makefile
@@ -4,24 +4,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	= $(BOARD).o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	= m54418twr.o
diff --git a/board/freescale/m54418twr/config.mk b/board/freescale/m54418twr/config.mk
index b306d031b9..07f52e0255 100644
--- a/board/freescale/m54418twr/config.mk
+++ b/board/freescale/m54418twr/config.mk
@@ -4,6 +4,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp
-
 PLATFORM_CPPFLAGS += -DTEXT_BASE=$(CONFIG_SYS_TEXT_BASE)
diff --git a/board/freescale/m54451evb/Makefile b/board/freescale/m54451evb/Makefile
index d6be84f75f..700ea2a74c 100644
--- a/board/freescale/m54451evb/Makefile
+++ b/board/freescale/m54451evb/Makefile
@@ -5,24 +5,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	= $(BOARD).o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	= m54451evb.o
diff --git a/board/freescale/m54451evb/config.mk b/board/freescale/m54451evb/config.mk
deleted file mode 100644
index 0ffb0a204b..0000000000
--- a/board/freescale/m54451evb/config.mk
+++ /dev/null
@@ -1,11 +0,0 @@
-#
-# (C) Copyright 2000-2003
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-# Coldfire contribution by Bernhard Kuhn <bkuhn@metrowerks.com>
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp
-
-PLATFORM_CPPFLAGS += -DCONFIG_SYS_TEXT_BASE=$(CONFIG_SYS_TEXT_BASE)
diff --git a/board/freescale/m54455evb/Makefile b/board/freescale/m54455evb/Makefile
index d6be84f75f..1c775fadb8 100644
--- a/board/freescale/m54455evb/Makefile
+++ b/board/freescale/m54455evb/Makefile
@@ -5,24 +5,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	= $(BOARD).o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	= m54455evb.o
diff --git a/board/freescale/m54455evb/config.mk b/board/freescale/m54455evb/config.mk
deleted file mode 100644
index 0ffb0a204b..0000000000
--- a/board/freescale/m54455evb/config.mk
+++ /dev/null
@@ -1,11 +0,0 @@
-#
-# (C) Copyright 2000-2003
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-# Coldfire contribution by Bernhard Kuhn <bkuhn@metrowerks.com>
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp
-
-PLATFORM_CPPFLAGS += -DCONFIG_SYS_TEXT_BASE=$(CONFIG_SYS_TEXT_BASE)
diff --git a/board/freescale/m547xevb/Makefile b/board/freescale/m547xevb/Makefile
index d6be84f75f..816917734b 100644
--- a/board/freescale/m547xevb/Makefile
+++ b/board/freescale/m547xevb/Makefile
@@ -5,24 +5,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	= $(BOARD).o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	= m547xevb.o
diff --git a/board/freescale/m548xevb/Makefile b/board/freescale/m548xevb/Makefile
index d6be84f75f..4483d15981 100644
--- a/board/freescale/m548xevb/Makefile
+++ b/board/freescale/m548xevb/Makefile
@@ -5,24 +5,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	= $(BOARD).o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	= m548xevb.o
diff --git a/board/freescale/mpc5121ads/Makefile b/board/freescale/mpc5121ads/Makefile
index b5cd5f734c..67cf55546b 100644
--- a/board/freescale/mpc5121ads/Makefile
+++ b/board/freescale/mpc5121ads/Makefile
@@ -5,27 +5,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-$(shell mkdir -p $(OBJTREE)/board/freescale/common)
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS-y	:= $(BOARD).o
-
-COBJS	:= $(COBJS-y)
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	:= mpc5121ads.o
diff --git a/board/freescale/mpc7448hpc2/Makefile b/board/freescale/mpc7448hpc2/Makefile
index 03917463bc..2cc211bfd0 100644
--- a/board/freescale/mpc7448hpc2/Makefile
+++ b/board/freescale/mpc7448hpc2/Makefile
@@ -5,25 +5,5 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	:= $(BOARD).o tsi108_init.o
-SOBJS	:= asm_init.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
-	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude ($obj).depend
-
-#########################################################################
+obj-y	:= mpc7448hpc2.o tsi108_init.o
+obj-y	+= asm_init.o
diff --git a/board/freescale/mpc8260ads/Makefile b/board/freescale/mpc8260ads/Makefile
index c91b0886f2..007d9580ae 100644
--- a/board/freescale/mpc8260ads/Makefile
+++ b/board/freescale/mpc8260ads/Makefile
@@ -1,4 +1,3 @@
-
 #
 # (C) Copyright 2001-2006
 # Wolfgang Denk, DENX Software Engineering, wd@denx.de.
@@ -6,24 +5,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	:= $(BOARD).o flash.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	:= mpc8260ads.o flash.o
diff --git a/board/freescale/mpc8266ads/Makefile b/board/freescale/mpc8266ads/Makefile
index d1d2ecb11b..ee63dc0376 100644
--- a/board/freescale/mpc8266ads/Makefile
+++ b/board/freescale/mpc8266ads/Makefile
@@ -5,24 +5,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	:= $(BOARD).o flash.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	:= mpc8266ads.o flash.o
diff --git a/board/freescale/mpc8308rdb/Makefile b/board/freescale/mpc8308rdb/Makefile
index 31127f082b..ec2b85d9cd 100644
--- a/board/freescale/mpc8308rdb/Makefile
+++ b/board/freescale/mpc8308rdb/Makefile
@@ -7,24 +7,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	:= $(BOARD).o sdram.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	:= mpc8308rdb.o sdram.o
diff --git a/board/freescale/mpc8313erdb/Makefile b/board/freescale/mpc8313erdb/Makefile
index b9fa864bb5..77fad7574a 100644
--- a/board/freescale/mpc8313erdb/Makefile
+++ b/board/freescale/mpc8313erdb/Makefile
@@ -5,24 +5,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	:= $(BOARD).o sdram.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	:= mpc8313erdb.o sdram.o
diff --git a/board/freescale/mpc8315erdb/Makefile b/board/freescale/mpc8315erdb/Makefile
index b9fa864bb5..fbb68c579d 100644
--- a/board/freescale/mpc8315erdb/Makefile
+++ b/board/freescale/mpc8315erdb/Makefile
@@ -5,24 +5,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	:= $(BOARD).o sdram.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	:= mpc8315erdb.o sdram.o
diff --git a/board/freescale/mpc8323erdb/Makefile b/board/freescale/mpc8323erdb/Makefile
index ff0dbf869d..f2e7497210 100644
--- a/board/freescale/mpc8323erdb/Makefile
+++ b/board/freescale/mpc8323erdb/Makefile
@@ -5,24 +5,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	:= $(BOARD).o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	:= mpc8323erdb.o
diff --git a/board/freescale/mpc832xemds/Makefile b/board/freescale/mpc832xemds/Makefile
index 0c6e556a6d..66763519af 100644
--- a/board/freescale/mpc832xemds/Makefile
+++ b/board/freescale/mpc832xemds/Makefile
@@ -5,26 +5,5 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS-y += $(BOARD).o
-COBJS-$(CONFIG_PCI) += pci.o
-
-COBJS	:= $(COBJS-y)
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y += mpc832xemds.o
+obj-$(CONFIG_PCI) += pci.o
diff --git a/board/freescale/mpc8349emds/Makefile b/board/freescale/mpc8349emds/Makefile
index 9549badce4..5c315f9f68 100644
--- a/board/freescale/mpc8349emds/Makefile
+++ b/board/freescale/mpc8349emds/Makefile
@@ -5,27 +5,6 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS-y += $(BOARD).o
-COBJS-$(CONFIG_PCI) += pci.o
-COBJS-$(CONFIG_FSL_DDR2) += ddr.o
-
-COBJS	:= $(COBJS-y)
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y += mpc8349emds.o
+obj-$(CONFIG_PCI) += pci.o
+obj-$(CONFIG_SYS_FSL_DDR2) += ddr.o
diff --git a/board/freescale/mpc8349emds/ddr.c b/board/freescale/mpc8349emds/ddr.c
index c66750e2e3..aae003d121 100644
--- a/board/freescale/mpc8349emds/ddr.c
+++ b/board/freescale/mpc8349emds/ddr.c
@@ -6,8 +6,8 @@
 
 #include <common.h>
 
-#include <asm/fsl_ddr_sdram.h>
-#include <asm/fsl_ddr_dimm_params.h>
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr_dimm_params.h>
 
 struct board_specific_parameters {
 	u32 n_ranks;
@@ -15,7 +15,7 @@ struct board_specific_parameters {
 	u32 clk_adjust;
 	u32 cpo;
 	u32 write_data_delay;
-	u32 force_2T;
+	u32 force_2t;
 };
 
 /*
@@ -70,7 +70,7 @@ void fsl_ddr_board_options(memctl_options_t *popts,
 				popts->cpo_override = pbsp->cpo;
 				popts->write_data_delay =
 					pbsp->write_data_delay;
-				popts->twoT_en = pbsp->force_2T;
+				popts->twot_en = pbsp->force_2t;
 				goto found;
 			}
 			pbsp_highest = pbsp;
@@ -86,7 +86,7 @@ void fsl_ddr_board_options(memctl_options_t *popts,
 		popts->clk_adjust = pbsp_highest->clk_adjust;
 		popts->cpo_override = pbsp_highest->cpo;
 		popts->write_data_delay = pbsp_highest->write_data_delay;
-		popts->twoT_en = pbsp_highest->force_2T;
+		popts->twot_en = pbsp_highest->force_2t;
 	} else {
 		panic("DIMM is not supported by this board");
 	}
@@ -97,5 +97,5 @@ found:
 	 *	- number of DIMMs installed
 	 */
 	popts->half_strength_driver_enable = 0;
-	popts->DQS_config = 0;	/* only true DQS signal is used on board */
+	popts->dqs_config = 0;	/* only true DQS signal is used on board */
 }
diff --git a/board/freescale/mpc8349emds/mpc8349emds.c b/board/freescale/mpc8349emds/mpc8349emds.c
index ec48487294..d9092201aa 100644
--- a/board/freescale/mpc8349emds/mpc8349emds.c
+++ b/board/freescale/mpc8349emds/mpc8349emds.c
@@ -12,8 +12,8 @@
 #include <i2c.h>
 #include <spi.h>
 #include <miiphy.h>
-#ifdef CONFIG_FSL_DDR2
-#include <asm/fsl_ddr_sdram.h>
+#ifdef CONFIG_SYS_FSL_DDR2
+#include <fsl_ddr_sdram.h>
 #else
 #include <spd_sdram.h>
 #endif
@@ -57,7 +57,7 @@ phys_size_t initdram (int board_type)
 	/* DDR SDRAM - Main SODIMM */
 	im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_BASE & LAWBAR_BAR;
 #if defined(CONFIG_SPD_EEPROM)
-#ifndef CONFIG_FSL_DDR2
+#ifndef CONFIG_SYS_FSL_DDR2
 	msize = spd_sdram() * 1024 * 1024;
 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
 	ddr_enable_ecc(msize);
diff --git a/board/freescale/mpc8349itx/Makefile b/board/freescale/mpc8349itx/Makefile
index 9e3c891e17..e9092adba2 100644
--- a/board/freescale/mpc8349itx/Makefile
+++ b/board/freescale/mpc8349itx/Makefile
@@ -4,25 +4,5 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS-y += $(BOARD).o
-COBJS-$(CONFIG_PCI) += pci.o
-
-COBJS	:= $(COBJS-y)
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y += mpc8349itx.o
+obj-$(CONFIG_PCI) += pci.o
diff --git a/board/freescale/mpc8360emds/Makefile b/board/freescale/mpc8360emds/Makefile
index 0c6e556a6d..e8332cea3f 100644
--- a/board/freescale/mpc8360emds/Makefile
+++ b/board/freescale/mpc8360emds/Makefile
@@ -5,26 +5,5 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS-y += $(BOARD).o
-COBJS-$(CONFIG_PCI) += pci.o
-
-COBJS	:= $(COBJS-y)
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y += mpc8360emds.o
+obj-$(CONFIG_PCI) += pci.o
diff --git a/board/freescale/mpc8360erdk/Makefile b/board/freescale/mpc8360erdk/Makefile
index 8895cd010a..e2235c28fe 100644
--- a/board/freescale/mpc8360erdk/Makefile
+++ b/board/freescale/mpc8360erdk/Makefile
@@ -5,26 +5,5 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS-y += $(BOARD).o
-COBJS-$(CONFIG_CMD_NAND) += nand.o
-
-COBJS	:= $(COBJS-y)
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y += mpc8360erdk.o
+obj-$(CONFIG_CMD_NAND) += nand.o
diff --git a/board/freescale/mpc837xemds/Makefile b/board/freescale/mpc837xemds/Makefile
index 0c6e556a6d..70b2147c3d 100644
--- a/board/freescale/mpc837xemds/Makefile
+++ b/board/freescale/mpc837xemds/Makefile
@@ -5,26 +5,5 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS-y += $(BOARD).o
-COBJS-$(CONFIG_PCI) += pci.o
-
-COBJS	:= $(COBJS-y)
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y += mpc837xemds.o
+obj-$(CONFIG_PCI) += pci.o
diff --git a/board/freescale/mpc837xerdb/Makefile b/board/freescale/mpc837xerdb/Makefile
index 0c6e556a6d..c2d0bc4302 100644
--- a/board/freescale/mpc837xerdb/Makefile
+++ b/board/freescale/mpc837xerdb/Makefile
@@ -5,26 +5,5 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS-y += $(BOARD).o
-COBJS-$(CONFIG_PCI) += pci.o
-
-COBJS	:= $(COBJS-y)
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y += mpc837xerdb.o
+obj-$(CONFIG_PCI) += pci.o
diff --git a/board/freescale/mpc8536ds/Makefile b/board/freescale/mpc8536ds/Makefile
index bbb492d9ee..e36492f501 100644
--- a/board/freescale/mpc8536ds/Makefile
+++ b/board/freescale/mpc8536ds/Makefile
@@ -6,27 +6,7 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS-y	+= $(BOARD).o
-COBJS-y	+= ddr.o
-COBJS-y	+= law.o
-COBJS-y	+= tlb.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS-y))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	+= mpc8536ds.o
+obj-y	+= ddr.o
+obj-y	+= law.o
+obj-y	+= tlb.o
diff --git a/board/freescale/mpc8536ds/ddr.c b/board/freescale/mpc8536ds/ddr.c
index d10370c9f2..ebe3ba460c 100644
--- a/board/freescale/mpc8536ds/ddr.c
+++ b/board/freescale/mpc8536ds/ddr.c
@@ -8,8 +8,8 @@
 
 #include <common.h>
 
-#include <asm/fsl_ddr_sdram.h>
-#include <asm/fsl_ddr_dimm_params.h>
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr_dimm_params.h>
 
 void fsl_ddr_board_options(memctl_options_t *popts,
 				dimm_params_t *pdimm,
diff --git a/board/freescale/mpc8536ds/mpc8536ds.c b/board/freescale/mpc8536ds/mpc8536ds.c
index 5daab692c6..467f4f2013 100644
--- a/board/freescale/mpc8536ds/mpc8536ds.c
+++ b/board/freescale/mpc8536ds/mpc8536ds.c
@@ -12,7 +12,7 @@
 #include <asm/cache.h>
 #include <asm/immap_85xx.h>
 #include <asm/fsl_pci.h>
-#include <asm/fsl_ddr_sdram.h>
+#include <fsl_ddr_sdram.h>
 #include <asm/io.h>
 #include <asm/fsl_serdes.h>
 #include <spd.h>
@@ -90,7 +90,7 @@ int checkboard (void)
 phys_size_t fixed_sdram (void)
 {
 	volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
-	volatile ccsr_ddr_t *ddr= &immap->im_ddr;
+	struct ccsr_ddr __iomem *ddr = &immap->im_ddr;
 	uint d_init;
 
 	ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS;
diff --git a/board/freescale/mpc8540ads/Makefile b/board/freescale/mpc8540ads/Makefile
index 08dd14b64d..6f82c7f7ac 100644
--- a/board/freescale/mpc8540ads/Makefile
+++ b/board/freescale/mpc8540ads/Makefile
@@ -5,27 +5,7 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS-y	+= $(BOARD).o
-COBJS-y	+= ddr.o
-COBJS-y	+= law.o
-COBJS-y	+= tlb.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS-y))
-SOBJS	:= $(addprefix $(obj),$(SOBJS-y))
-
-$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	+= mpc8540ads.o
+obj-y	+= ddr.o
+obj-y	+= law.o
+obj-y	+= tlb.o
diff --git a/board/freescale/mpc8540ads/ddr.c b/board/freescale/mpc8540ads/ddr.c
index 571137443e..41d4cfe738 100644
--- a/board/freescale/mpc8540ads/ddr.c
+++ b/board/freescale/mpc8540ads/ddr.c
@@ -8,8 +8,8 @@
 
 #include <common.h>
 
-#include <asm/fsl_ddr_sdram.h>
-#include <asm/fsl_ddr_dimm_params.h>
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr_dimm_params.h>
 
 void fsl_ddr_board_options(memctl_options_t *popts,
 				dimm_params_t *pdimm,
@@ -36,7 +36,7 @@ void fsl_ddr_board_options(memctl_options_t *popts,
 	popts->write_data_delay = 3;
 
 	/* 2T timing enable */
-	popts->twoT_en = 1;
+	popts->twot_en = 1;
 
 	/*
 	 * Factors to consider for half-strength driver enable:
diff --git a/board/freescale/mpc8540ads/mpc8540ads.c b/board/freescale/mpc8540ads/mpc8540ads.c
index 175eefcc6b..93288c7e9c 100644
--- a/board/freescale/mpc8540ads/mpc8540ads.c
+++ b/board/freescale/mpc8540ads/mpc8540ads.c
@@ -14,7 +14,7 @@
 #include <asm/processor.h>
 #include <asm/mmu.h>
 #include <asm/immap_85xx.h>
-#include <asm/fsl_ddr_sdram.h>
+#include <fsl_ddr_sdram.h>
 #include <libfdt.h>
 #include <fdt_support.h>
 
@@ -168,7 +168,8 @@ void lbc_sdram_init(void)
 phys_size_t fixed_sdram(void)
 {
   #ifndef CONFIG_SYS_RAMBOOT
-	volatile ccsr_ddr_t *ddr= (void *)(CONFIG_SYS_MPC8xxx_DDR_ADDR);
+	struct ccsr_ddr __iomem *ddr =
+		(struct ccsr_ddr __iomem *)(CONFIG_SYS_FSL_DDR_ADDR);
 
 	ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS;
 	ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG;
diff --git a/board/freescale/mpc8541cds/Makefile b/board/freescale/mpc8541cds/Makefile
index 4f524b7b62..78af4b85fb 100644
--- a/board/freescale/mpc8541cds/Makefile
+++ b/board/freescale/mpc8541cds/Makefile
@@ -6,27 +6,7 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS-y	+= $(BOARD).o
-COBJS-y	+= ddr.o
-COBJS-y	+= law.o
-COBJS-y	+= tlb.o
-
-SRCS	:= $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS-y))
-SOBJS	:= $(addprefix $(obj),$(SOBJS-y))
-
-$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	+= mpc8541cds.o
+obj-y	+= ddr.o
+obj-y	+= law.o
+obj-y	+= tlb.o
diff --git a/board/freescale/mpc8541cds/ddr.c b/board/freescale/mpc8541cds/ddr.c
index 78d73b0ea8..d2ac6c4ad4 100644
--- a/board/freescale/mpc8541cds/ddr.c
+++ b/board/freescale/mpc8541cds/ddr.c
@@ -8,8 +8,8 @@
 
 #include <common.h>
 
-#include <asm/fsl_ddr_sdram.h>
-#include <asm/fsl_ddr_dimm_params.h>
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr_dimm_params.h>
 
 void fsl_ddr_board_options(memctl_options_t *popts,
 				dimm_params_t *pdimm,
diff --git a/board/freescale/mpc8541cds/mpc8541cds.c b/board/freescale/mpc8541cds/mpc8541cds.c
index 8115e5c69b..7b264dddd1 100644
--- a/board/freescale/mpc8541cds/mpc8541cds.c
+++ b/board/freescale/mpc8541cds/mpc8541cds.c
@@ -11,7 +11,7 @@
 #include <asm/processor.h>
 #include <asm/mmu.h>
 #include <asm/immap_85xx.h>
-#include <asm/fsl_ddr_sdram.h>
+#include <fsl_ddr_sdram.h>
 #include <ioports.h>
 #include <spd_sdram.h>
 #include <libfdt.h>
diff --git a/board/freescale/mpc8544ds/Makefile b/board/freescale/mpc8544ds/Makefile
index 009cceb5af..3359eea44f 100644
--- a/board/freescale/mpc8544ds/Makefile
+++ b/board/freescale/mpc8544ds/Makefile
@@ -6,27 +6,7 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS-y	+= $(BOARD).o
-COBJS-y	+= ddr.o
-COBJS-y	+= law.o
-COBJS-y	+= tlb.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS-y))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	+= mpc8544ds.o
+obj-y	+= ddr.o
+obj-y	+= law.o
+obj-y	+= tlb.o
diff --git a/board/freescale/mpc8544ds/ddr.c b/board/freescale/mpc8544ds/ddr.c
index 94219b9471..aa30cabb03 100644
--- a/board/freescale/mpc8544ds/ddr.c
+++ b/board/freescale/mpc8544ds/ddr.c
@@ -8,8 +8,8 @@
 
 #include <common.h>
 
-#include <asm/fsl_ddr_sdram.h>
-#include <asm/fsl_ddr_dimm_params.h>
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr_dimm_params.h>
 
 void fsl_ddr_board_options(memctl_options_t *popts,
 				dimm_params_t *pdimm,
@@ -49,7 +49,7 @@ void fsl_ddr_board_options(memctl_options_t *popts,
 	popts->write_data_delay = 3;
 
 	/* 2T timing enable */
-	popts->twoT_en = 1;
+	popts->twot_en = 1;
 
 	/*
 	 * Factors to consider for half-strength driver enable:
diff --git a/board/freescale/mpc8544ds/mpc8544ds.c b/board/freescale/mpc8544ds/mpc8544ds.c
index dfd8fa6522..1b33db6f31 100644
--- a/board/freescale/mpc8544ds/mpc8544ds.c
+++ b/board/freescale/mpc8544ds/mpc8544ds.c
@@ -11,7 +11,7 @@
 #include <asm/mmu.h>
 #include <asm/immap_85xx.h>
 #include <asm/fsl_pci.h>
-#include <asm/fsl_ddr_sdram.h>
+#include <fsl_ddr_sdram.h>
 #include <asm/fsl_serdes.h>
 #include <asm/io.h>
 #include <miiphy.h>
diff --git a/board/freescale/mpc8548cds/Makefile b/board/freescale/mpc8548cds/Makefile
index 4f524b7b62..f797df2273 100644
--- a/board/freescale/mpc8548cds/Makefile
+++ b/board/freescale/mpc8548cds/Makefile
@@ -6,27 +6,7 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS-y	+= $(BOARD).o
-COBJS-y	+= ddr.o
-COBJS-y	+= law.o
-COBJS-y	+= tlb.o
-
-SRCS	:= $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS-y))
-SOBJS	:= $(addprefix $(obj),$(SOBJS-y))
-
-$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	+= mpc8548cds.o
+obj-y	+= ddr.o
+obj-y	+= law.o
+obj-y	+= tlb.o
diff --git a/board/freescale/mpc8548cds/ddr.c b/board/freescale/mpc8548cds/ddr.c
index 996ffe206d..b31ea3432e 100644
--- a/board/freescale/mpc8548cds/ddr.c
+++ b/board/freescale/mpc8548cds/ddr.c
@@ -8,8 +8,8 @@
 
 #include <common.h>
 
-#include <asm/fsl_ddr_sdram.h>
-#include <asm/fsl_ddr_dimm_params.h>
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr_dimm_params.h>
 
 void fsl_ddr_board_options(memctl_options_t *popts,
 				dimm_params_t *pdimm,
diff --git a/board/freescale/mpc8548cds/mpc8548cds.c b/board/freescale/mpc8548cds/mpc8548cds.c
index 51e4bb5dcb..ca9b43c6b6 100644
--- a/board/freescale/mpc8548cds/mpc8548cds.c
+++ b/board/freescale/mpc8548cds/mpc8548cds.c
@@ -12,7 +12,7 @@
 #include <asm/mmu.h>
 #include <asm/immap_85xx.h>
 #include <asm/fsl_pci.h>
-#include <asm/fsl_ddr_sdram.h>
+#include <fsl_ddr_sdram.h>
 #include <asm/fsl_serdes.h>
 #include <miiphy.h>
 #include <libfdt.h>
diff --git a/board/freescale/mpc8555cds/Makefile b/board/freescale/mpc8555cds/Makefile
index 4f524b7b62..d32d005e88 100644
--- a/board/freescale/mpc8555cds/Makefile
+++ b/board/freescale/mpc8555cds/Makefile
@@ -6,27 +6,7 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS-y	+= $(BOARD).o
-COBJS-y	+= ddr.o
-COBJS-y	+= law.o
-COBJS-y	+= tlb.o
-
-SRCS	:= $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS-y))
-SOBJS	:= $(addprefix $(obj),$(SOBJS-y))
-
-$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	+= mpc8555cds.o
+obj-y	+= ddr.o
+obj-y	+= law.o
+obj-y	+= tlb.o
diff --git a/board/freescale/mpc8555cds/ddr.c b/board/freescale/mpc8555cds/ddr.c
index 78d73b0ea8..d2ac6c4ad4 100644
--- a/board/freescale/mpc8555cds/ddr.c
+++ b/board/freescale/mpc8555cds/ddr.c
@@ -8,8 +8,8 @@
 
 #include <common.h>
 
-#include <asm/fsl_ddr_sdram.h>
-#include <asm/fsl_ddr_dimm_params.h>
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr_dimm_params.h>
 
 void fsl_ddr_board_options(memctl_options_t *popts,
 				dimm_params_t *pdimm,
diff --git a/board/freescale/mpc8555cds/mpc8555cds.c b/board/freescale/mpc8555cds/mpc8555cds.c
index e2093d1bbc..de5f5669e6 100644
--- a/board/freescale/mpc8555cds/mpc8555cds.c
+++ b/board/freescale/mpc8555cds/mpc8555cds.c
@@ -9,7 +9,7 @@
 #include <asm/processor.h>
 #include <asm/mmu.h>
 #include <asm/immap_85xx.h>
-#include <asm/fsl_ddr_sdram.h>
+#include <fsl_ddr_sdram.h>
 #include <ioports.h>
 #include <spd_sdram.h>
 #include <libfdt.h>
diff --git a/board/freescale/mpc8560ads/Makefile b/board/freescale/mpc8560ads/Makefile
index 46e412b923..685168e08d 100644
--- a/board/freescale/mpc8560ads/Makefile
+++ b/board/freescale/mpc8560ads/Makefile
@@ -5,27 +5,7 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS-y	+= $(BOARD).o
-COBJS-y	+= ddr.o
-COBJS-y	+= law.o
-COBJS-y	+= tlb.o
-
-SRCS	:= $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS-y))
-SOBJS	:= $(addprefix $(obj),$(SOBJS-y))
-
-$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	+= mpc8560ads.o
+obj-y	+= ddr.o
+obj-y	+= law.o
+obj-y	+= tlb.o
diff --git a/board/freescale/mpc8560ads/ddr.c b/board/freescale/mpc8560ads/ddr.c
index 571137443e..41d4cfe738 100644
--- a/board/freescale/mpc8560ads/ddr.c
+++ b/board/freescale/mpc8560ads/ddr.c
@@ -8,8 +8,8 @@
 
 #include <common.h>
 
-#include <asm/fsl_ddr_sdram.h>
-#include <asm/fsl_ddr_dimm_params.h>
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr_dimm_params.h>
 
 void fsl_ddr_board_options(memctl_options_t *popts,
 				dimm_params_t *pdimm,
@@ -36,7 +36,7 @@ void fsl_ddr_board_options(memctl_options_t *popts,
 	popts->write_data_delay = 3;
 
 	/* 2T timing enable */
-	popts->twoT_en = 1;
+	popts->twot_en = 1;
 
 	/*
 	 * Factors to consider for half-strength driver enable:
diff --git a/board/freescale/mpc8560ads/mpc8560ads.c b/board/freescale/mpc8560ads/mpc8560ads.c
index 90a2522cb9..7104e33156 100644
--- a/board/freescale/mpc8560ads/mpc8560ads.c
+++ b/board/freescale/mpc8560ads/mpc8560ads.c
@@ -14,7 +14,7 @@
 #include <asm/processor.h>
 #include <asm/mmu.h>
 #include <asm/immap_85xx.h>
-#include <asm/fsl_ddr_sdram.h>
+#include <fsl_ddr_sdram.h>
 #include <ioports.h>
 #include <spd_sdram.h>
 #include <miiphy.h>
@@ -373,7 +373,7 @@ void lbc_sdram_init(void)
 phys_size_t fixed_sdram(void)
 {
   #ifndef CONFIG_SYS_RAMBOOT
-	volatile ccsr_ddr_t *ddr= (void *)(CONFIG_SYS_MPC8xxx_DDR_ADDR);
+	volatile ccsr_ddr_t *ddr = (void *)(CONFIG_SYS_FSL_DDR_ADDR);
 
 	ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS;
 	ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG;
diff --git a/board/freescale/mpc8568mds/Makefile b/board/freescale/mpc8568mds/Makefile
index 4cd711f106..612fb51548 100644
--- a/board/freescale/mpc8568mds/Makefile
+++ b/board/freescale/mpc8568mds/Makefile
@@ -6,28 +6,8 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS-y	+= $(BOARD).o
-COBJS-y	+= bcsr.o
-COBJS-y	+= ddr.o
-COBJS-y	+= law.o
-COBJS-y	+= tlb.o
-
-SRCS	:= $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS-y))
-SOBJS	:= $(addprefix $(obj),$(SOBJS-y))
-
-$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	+= mpc8568mds.o
+obj-y	+= bcsr.o
+obj-y	+= ddr.o
+obj-y	+= law.o
+obj-y	+= tlb.o
diff --git a/board/freescale/mpc8568mds/ddr.c b/board/freescale/mpc8568mds/ddr.c
index b1f4f1f848..6db92ef2da 100644
--- a/board/freescale/mpc8568mds/ddr.c
+++ b/board/freescale/mpc8568mds/ddr.c
@@ -8,8 +8,8 @@
 
 #include <common.h>
 
-#include <asm/fsl_ddr_sdram.h>
-#include <asm/fsl_ddr_dimm_params.h>
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr_dimm_params.h>
 
 void fsl_ddr_board_options(memctl_options_t *popts,
 				dimm_params_t *pdimm,
diff --git a/board/freescale/mpc8568mds/mpc8568mds.c b/board/freescale/mpc8568mds/mpc8568mds.c
index ae80697b38..a8fdcb5f91 100644
--- a/board/freescale/mpc8568mds/mpc8568mds.c
+++ b/board/freescale/mpc8568mds/mpc8568mds.c
@@ -12,7 +12,7 @@
 #include <asm/mmu.h>
 #include <asm/immap_85xx.h>
 #include <asm/fsl_pci.h>
-#include <asm/fsl_ddr_sdram.h>
+#include <fsl_ddr_sdram.h>
 #include <asm/fsl_serdes.h>
 #include <spd_sdram.h>
 #include <i2c.h>
diff --git a/board/freescale/mpc8569mds/Makefile b/board/freescale/mpc8569mds/Makefile
index ec318f0b1f..5f6e021759 100644
--- a/board/freescale/mpc8569mds/Makefile
+++ b/board/freescale/mpc8569mds/Makefile
@@ -6,28 +6,8 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS-y	+= $(BOARD).o
-COBJS-y	+= bcsr.o
-COBJS-y	+= ddr.o
-COBJS-y	+= law.o
-COBJS-y	+= tlb.o
-
-SRCS	:= $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS-y))
-SOBJS	:= $(addprefix $(obj),$(SOBJS-y))
-
-$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	+= mpc8569mds.o
+obj-y	+= bcsr.o
+obj-y	+= ddr.o
+obj-y	+= law.o
+obj-y	+= tlb.o
diff --git a/board/freescale/mpc8569mds/ddr.c b/board/freescale/mpc8569mds/ddr.c
index 68f686b7e6..ef404b1d6f 100644
--- a/board/freescale/mpc8569mds/ddr.c
+++ b/board/freescale/mpc8569mds/ddr.c
@@ -8,8 +8,8 @@
 
 #include <common.h>
 
-#include <asm/fsl_ddr_sdram.h>
-#include <asm/fsl_ddr_dimm_params.h>
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr_dimm_params.h>
 
 void fsl_ddr_board_options(memctl_options_t *popts,
 				dimm_params_t *pdimm,
diff --git a/board/freescale/mpc8569mds/mpc8569mds.c b/board/freescale/mpc8569mds/mpc8569mds.c
index c928a964f9..cb55e1c98c 100644
--- a/board/freescale/mpc8569mds/mpc8569mds.c
+++ b/board/freescale/mpc8569mds/mpc8569mds.c
@@ -14,7 +14,7 @@
 #include <asm/cache.h>
 #include <asm/immap_85xx.h>
 #include <asm/fsl_pci.h>
-#include <asm/fsl_ddr_sdram.h>
+#include <fsl_ddr_sdram.h>
 #include <asm/fsl_serdes.h>
 #include <asm/io.h>
 #include <spd_sdram.h>
@@ -231,7 +231,8 @@ int checkboard (void)
 #if !defined(CONFIG_SPD_EEPROM)
 phys_size_t fixed_sdram(void)
 {
-	volatile ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_MPC8xxx_DDR_ADDR;
+	struct ccsr_ddr __iomem *ddr =
+		(struct ccsr_ddr __iomem *)CONFIG_SYS_FSL_DDR_ADDR;
 	uint d_init;
 
 	out_be32(&ddr->cs0_bnds, CONFIG_SYS_DDR_CS0_BNDS);
diff --git a/board/freescale/mpc8572ds/Makefile b/board/freescale/mpc8572ds/Makefile
index 009cceb5af..902c900162 100644
--- a/board/freescale/mpc8572ds/Makefile
+++ b/board/freescale/mpc8572ds/Makefile
@@ -6,27 +6,7 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS-y	+= $(BOARD).o
-COBJS-y	+= ddr.o
-COBJS-y	+= law.o
-COBJS-y	+= tlb.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS-y))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	+= mpc8572ds.o
+obj-y	+= ddr.o
+obj-y	+= law.o
+obj-y	+= tlb.o
diff --git a/board/freescale/mpc8572ds/ddr.c b/board/freescale/mpc8572ds/ddr.c
index a7ff668b1b..2bfc1a170c 100644
--- a/board/freescale/mpc8572ds/ddr.c
+++ b/board/freescale/mpc8572ds/ddr.c
@@ -8,8 +8,8 @@
 
 #include <common.h>
 
-#include <asm/fsl_ddr_sdram.h>
-#include <asm/fsl_ddr_dimm_params.h>
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr_dimm_params.h>
 
 struct board_specific_parameters {
 	u32 n_ranks;
@@ -17,7 +17,7 @@ struct board_specific_parameters {
 	u32 clk_adjust;
 	u32 cpo;
 	u32 write_data_delay;
-	u32 force_2T;
+	u32 force_2t;
 };
 
 /*
@@ -139,7 +139,7 @@ void fsl_ddr_board_options(memctl_options_t *popts,
 				popts->cpo_override = pbsp->cpo;
 				popts->write_data_delay =
 					pbsp->write_data_delay;
-				popts->twoT_en = pbsp->force_2T;
+				popts->twot_en = pbsp->force_2t;
 				goto found;
 			}
 			pbsp_highest = pbsp;
@@ -155,7 +155,7 @@ void fsl_ddr_board_options(memctl_options_t *popts,
 		popts->clk_adjust = pbsp->clk_adjust;
 		popts->cpo_override = pbsp->cpo;
 		popts->write_data_delay = pbsp->write_data_delay;
-		popts->twoT_en = pbsp->force_2T;
+		popts->twot_en = pbsp->force_2t;
 	} else {
 		panic("DIMM is not supported by this board");
 	}
diff --git a/board/freescale/mpc8572ds/mpc8572ds.c b/board/freescale/mpc8572ds/mpc8572ds.c
index 657df6a718..56863222c8 100644
--- a/board/freescale/mpc8572ds/mpc8572ds.c
+++ b/board/freescale/mpc8572ds/mpc8572ds.c
@@ -12,7 +12,7 @@
 #include <asm/cache.h>
 #include <asm/immap_85xx.h>
 #include <asm/fsl_pci.h>
-#include <asm/fsl_ddr_sdram.h>
+#include <fsl_ddr_sdram.h>
 #include <asm/io.h>
 #include <asm/fsl_serdes.h>
 #include <miiphy.h>
@@ -62,7 +62,7 @@ int checkboard (void)
 phys_size_t fixed_sdram (void)
 {
 	volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
-	volatile ccsr_ddr_t *ddr= &immap->im_ddr;
+	struct ccsr_ddr __iomem *ddr = &immap->im_ddr;
 	uint d_init;
 
 	ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS;
diff --git a/board/freescale/mpc8610hpcd/Makefile b/board/freescale/mpc8610hpcd/Makefile
index 2009914588..2613004f89 100644
--- a/board/freescale/mpc8610hpcd/Makefile
+++ b/board/freescale/mpc8610hpcd/Makefile
@@ -3,28 +3,7 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS-y	+= $(BOARD).o
-COBJS-$(CONFIG_FSL_DDR2) += ddr.o
-COBJS-y	+= law.o
-
-COBJS-$(CONFIG_FSL_DIU_FB)	+= mpc8610hpcd_diu.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS-y))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	+= mpc8610hpcd.o
+obj-$(CONFIG_SYS_FSL_DDR2) += ddr.o
+obj-y	+= law.o
+obj-$(CONFIG_FSL_DIU_FB)	+= mpc8610hpcd_diu.o
diff --git a/board/freescale/mpc8610hpcd/ddr.c b/board/freescale/mpc8610hpcd/ddr.c
index 94219b9471..aa30cabb03 100644
--- a/board/freescale/mpc8610hpcd/ddr.c
+++ b/board/freescale/mpc8610hpcd/ddr.c
@@ -8,8 +8,8 @@
 
 #include <common.h>
 
-#include <asm/fsl_ddr_sdram.h>
-#include <asm/fsl_ddr_dimm_params.h>
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr_dimm_params.h>
 
 void fsl_ddr_board_options(memctl_options_t *popts,
 				dimm_params_t *pdimm,
@@ -49,7 +49,7 @@ void fsl_ddr_board_options(memctl_options_t *popts,
 	popts->write_data_delay = 3;
 
 	/* 2T timing enable */
-	popts->twoT_en = 1;
+	popts->twot_en = 1;
 
 	/*
 	 * Factors to consider for half-strength driver enable:
diff --git a/board/freescale/mpc8610hpcd/mpc8610hpcd.c b/board/freescale/mpc8610hpcd/mpc8610hpcd.c
index ffdcf2444c..d8740ddacc 100644
--- a/board/freescale/mpc8610hpcd/mpc8610hpcd.c
+++ b/board/freescale/mpc8610hpcd/mpc8610hpcd.c
@@ -10,7 +10,7 @@
 #include <asm/processor.h>
 #include <asm/immap_86xx.h>
 #include <asm/fsl_pci.h>
-#include <asm/fsl_ddr_sdram.h>
+#include <fsl_ddr_sdram.h>
 #include <asm/fsl_serdes.h>
 #include <i2c.h>
 #include <asm/io.h>
@@ -143,7 +143,7 @@ phys_size_t fixed_sdram(void)
 {
 #if !defined(CONFIG_SYS_RAMBOOT)
 	volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
-	volatile ccsr_ddr_t *ddr = &immap->im_ddr1;
+	struct ccsr_ddr __iomem *ddr = &immap->im_ddr1;
 	uint d_init;
 
 	ddr->cs0_bnds = 0x0000001f;
diff --git a/board/freescale/mpc8641hpcn/Makefile b/board/freescale/mpc8641hpcn/Makefile
index 0cbc0d0a90..86c70bcb9d 100644
--- a/board/freescale/mpc8641hpcn/Makefile
+++ b/board/freescale/mpc8641hpcn/Makefile
@@ -5,26 +5,6 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS-y	+= $(BOARD).o
-COBJS-y	+= law.o
-COBJS-$(CONFIG_FSL_DDR2) += ddr.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS-y))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude ($obj).depend
-
-#########################################################################
+obj-y	+= mpc8641hpcn.o
+obj-y	+= law.o
+obj-$(CONFIG_SYS_FSL_DDR2) += ddr.o
diff --git a/board/freescale/mpc8641hpcn/ddr.c b/board/freescale/mpc8641hpcn/ddr.c
index 5d3575738a..7cd0395651 100644
--- a/board/freescale/mpc8641hpcn/ddr.c
+++ b/board/freescale/mpc8641hpcn/ddr.c
@@ -8,8 +8,8 @@
 
 #include <common.h>
 
-#include <asm/fsl_ddr_sdram.h>
-#include <asm/fsl_ddr_dimm_params.h>
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr_dimm_params.h>
 
 struct board_specific_parameters {
 	u32 n_ranks;
@@ -106,5 +106,5 @@ void fsl_ddr_board_options(memctl_options_t *popts,
 
 found:
 	/* 2T timing enable */
-	popts->twoT_en = 1;
+	popts->twot_en = 1;
 }
diff --git a/board/freescale/mpc8641hpcn/mpc8641hpcn.c b/board/freescale/mpc8641hpcn/mpc8641hpcn.c
index 46a543ebcc..a58b5f9cd4 100644
--- a/board/freescale/mpc8641hpcn/mpc8641hpcn.c
+++ b/board/freescale/mpc8641hpcn/mpc8641hpcn.c
@@ -9,7 +9,7 @@
 #include <asm/processor.h>
 #include <asm/immap_86xx.h>
 #include <asm/fsl_pci.h>
-#include <asm/fsl_ddr_sdram.h>
+#include <fsl_ddr_sdram.h>
 #include <asm/fsl_serdes.h>
 #include <asm/io.h>
 #include <libfdt.h>
@@ -64,7 +64,7 @@ fixed_sdram(void)
 {
 #if !defined(CONFIG_SYS_RAMBOOT)
 	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
-	volatile ccsr_ddr_t *ddr = &immap->im_ddr1;
+	struct ccsr_ddr __iomem *ddr = &immap->im_ddr1;
 
 	ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS;
 	ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG;
diff --git a/board/freescale/mx23evk/Makefile b/board/freescale/mx23evk/Makefile
index 01e7de1210..c3a79ee004 100644
--- a/board/freescale/mx23evk/Makefile
+++ b/board/freescale/mx23evk/Makefile
@@ -5,27 +5,8 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
 ifndef	CONFIG_SPL_BUILD
-COBJS	:= mx23evk.o
+obj-y	:= mx23evk.o
 else
-COBJS	:= spl_boot.o
+obj-y	:= spl_boot.o
 endif
-
-SRCS	:= $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
diff --git a/board/freescale/mx25pdk/Makefile b/board/freescale/mx25pdk/Makefile
index a01a27deaa..0b288f2588 100644
--- a/board/freescale/mx25pdk/Makefile
+++ b/board/freescale/mx25pdk/Makefile
@@ -6,25 +6,5 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	:= mx25pdk.o
-SOBJS	:= lowlevel_init.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
-	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	:= mx25pdk.o
+obj-y	+= lowlevel_init.o
diff --git a/board/freescale/mx25pdk/mx25pdk.c b/board/freescale/mx25pdk/mx25pdk.c
index ebe3bcb6ed..71a395c226 100644
--- a/board/freescale/mx25pdk/mx25pdk.c
+++ b/board/freescale/mx25pdk/mx25pdk.c
@@ -138,7 +138,7 @@ int board_late_init(void)
 
 	mx25pdk_fec_init();
 
-	ret = pmic_init(I2C_PMIC);
+	ret = pmic_init(I2C_0);
 	if (ret)
 		return ret;
 
diff --git a/board/freescale/mx28evk/Makefile b/board/freescale/mx28evk/Makefile
index d3634c1d4d..5956d34a4f 100644
--- a/board/freescale/mx28evk/Makefile
+++ b/board/freescale/mx28evk/Makefile
@@ -5,27 +5,8 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
 ifndef	CONFIG_SPL_BUILD
-COBJS	:= mx28evk.o
+obj-y	:= mx28evk.o
 else
-COBJS	:= iomux.o
+obj-y	:= iomux.o
 endif
-
-SRCS	:= $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
diff --git a/board/freescale/mx31ads/Makefile b/board/freescale/mx31ads/Makefile
index b6c70b01e7..5e1440d596 100644
--- a/board/freescale/mx31ads/Makefile
+++ b/board/freescale/mx31ads/Makefile
@@ -4,25 +4,5 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	:= mx31ads.o
-SOBJS	:= lowlevel_init.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
-	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	:= mx31ads.o
+obj-y	+= lowlevel_init.o
diff --git a/board/freescale/mx31ads/u-boot.lds b/board/freescale/mx31ads/u-boot.lds
index 3acc4ca548..6da1d4b5f5 100644
--- a/board/freescale/mx31ads/u-boot.lds
+++ b/board/freescale/mx31ads/u-boot.lds
@@ -22,11 +22,11 @@ SECTIONS
 	  /* WARNING - the following is hand-optimized to fit within	*/
 	  /* the sector layout of our flash chips!	XXX FIXME XXX	*/
 
-	  arch/arm/cpu/arm1136/start.o			(.text*)
-	  board/freescale/mx31ads/libmx31ads.o	(.text*)
-	  arch/arm/lib/libarm.o			(.text*)
-	  net/libnet.o				(.text*)
-	  drivers/mtd/libmtd.o			(.text*)
+	  arch/arm/cpu/arm1136/start.o		(.text*)
+	  board/freescale/mx31ads/built-in.o	(.text*)
+	  arch/arm/lib/built-in.o		(.text*)
+	  net/built-in.o			(.text*)
+	  drivers/mtd/built-in.o		(.text*)
 
 	  . = DEFINED(env_offset) ? env_offset : .;
 	  common/env_embedded.o(.text*)
@@ -69,7 +69,12 @@ SECTIONS
 		*(.__rel_dyn_end)
 	}
 
-	_end = .;
+	.end :
+	{
+		*(.__end)
+	}
+
+	_image_binary_end = .;
 
 /*
  * Compiler-generated __bss_start and __bss_end, see arch/arm/lib/bss.c
@@ -90,13 +95,13 @@ SECTIONS
 		KEEP(*(.__bss_end));
 	}
 
-	/DISCARD/ : { *(.bss*) }
-	/DISCARD/ : { *(.dynsym) }
-	/DISCARD/ : { *(.dynstr*) }
-	/DISCARD/ : { *(.dynsym*) }
-	/DISCARD/ : { *(.dynamic*) }
-	/DISCARD/ : { *(.hash*) }
-	/DISCARD/ : { *(.plt*) }
-	/DISCARD/ : { *(.interp*) }
-	/DISCARD/ : { *(.gnu*) }
+	.dynsym _image_binary_end : { *(.dynsym) }
+	.dynbss : { *(.dynbss) }
+	.dynstr : { *(.dynstr*) }
+	.dynamic : { *(.dynamic*) }
+	.hash : { *(.hash*) }
+	.plt : { *(.plt*) }
+	.interp : { *(.interp*) }
+	.gnu : { *(.gnu*) }
+	.ARM.exidx : { *(.ARM.exidx*) }
 }
diff --git a/board/freescale/mx31pdk/Makefile b/board/freescale/mx31pdk/Makefile
index 860a8a658f..754b3ea93f 100644
--- a/board/freescale/mx31pdk/Makefile
+++ b/board/freescale/mx31pdk/Makefile
@@ -7,27 +7,7 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
 ifdef CONFIG_SPL_BUILD
-SOBJS	:= lowlevel_init.o
+obj-y	+= lowlevel_init.o
 endif
-COBJS	:= mx31pdk.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
-	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	+= mx31pdk.o
diff --git a/board/freescale/mx31pdk/mx31pdk.c b/board/freescale/mx31pdk/mx31pdk.c
index 148b4f47a5..13b9d51dd1 100644
--- a/board/freescale/mx31pdk/mx31pdk.c
+++ b/board/freescale/mx31pdk/mx31pdk.c
@@ -85,7 +85,7 @@ int board_late_init(void)
 	struct pmic *p;
 	int ret;
 
-	ret = pmic_init(I2C_PMIC);
+	ret = pmic_init(CONFIG_FSL_PMIC_BUS);
 	if (ret)
 		return ret;
 
diff --git a/board/freescale/mx35pdk/Makefile b/board/freescale/mx35pdk/Makefile
index 7caf52f115..5fa121912e 100644
--- a/board/freescale/mx35pdk/Makefile
+++ b/board/freescale/mx35pdk/Makefile
@@ -6,25 +6,5 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	:= mx35pdk.o
-SOBJS	:= lowlevel_init.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
-	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	:= mx35pdk.o
+obj-y	+= lowlevel_init.o
diff --git a/board/freescale/mx35pdk/mx35pdk.c b/board/freescale/mx35pdk/mx35pdk.c
index 9fabef5af5..12467a9ada 100644
--- a/board/freescale/mx35pdk/mx35pdk.c
+++ b/board/freescale/mx35pdk/mx35pdk.c
@@ -213,7 +213,7 @@ int board_late_init(void)
 	struct pmic *p;
 	int ret;
 
-	ret = pmic_init(I2C_PMIC);
+	ret = pmic_init(I2C_0);
 	if (ret)
 		return ret;
 
diff --git a/board/freescale/mx51evk/Makefile b/board/freescale/mx51evk/Makefile
index c9b145527b..b2de2d88ab 100644
--- a/board/freescale/mx51evk/Makefile
+++ b/board/freescale/mx51evk/Makefile
@@ -6,25 +6,5 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS-y			+= mx51evk.o
-COBJS-$(CONFIG_VIDEO)	+= mx51evk_video.o
-
-COBJS	:= $(COBJS-y)
-SRCS	:= $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y			+= mx51evk.o
+obj-$(CONFIG_VIDEO)	+= mx51evk_video.o
diff --git a/board/freescale/mx51evk/mx51evk.c b/board/freescale/mx51evk/mx51evk.c
index d01465ecae..9b43c84e79 100644
--- a/board/freescale/mx51evk/mx51evk.c
+++ b/board/freescale/mx51evk/mx51evk.c
@@ -174,7 +174,7 @@ static void power_init(void)
 	struct pmic *p;
 	int ret;
 
-	ret = pmic_init(I2C_PMIC);
+	ret = pmic_init(CONFIG_FSL_PMIC_BUS);
 	if (ret)
 		return;
 
diff --git a/board/freescale/mx53ard/Makefile b/board/freescale/mx53ard/Makefile
index 8bcb21c713..0b7d8398c8 100644
--- a/board/freescale/mx53ard/Makefile
+++ b/board/freescale/mx53ard/Makefile
@@ -6,23 +6,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	:= mx53ard.o
-
-SRCS	:= $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	:= mx53ard.o
diff --git a/board/freescale/mx53evk/Makefile b/board/freescale/mx53evk/Makefile
index f244069fb7..e03ac7946c 100644
--- a/board/freescale/mx53evk/Makefile
+++ b/board/freescale/mx53evk/Makefile
@@ -6,23 +6,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	:= mx53evk.o
-
-SRCS	:= $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	:= mx53evk.o
diff --git a/board/freescale/mx53evk/mx53evk.c b/board/freescale/mx53evk/mx53evk.c
index 3b398b6d76..13519e26da 100644
--- a/board/freescale/mx53evk/mx53evk.c
+++ b/board/freescale/mx53evk/mx53evk.c
@@ -81,7 +81,7 @@ void power_init(void)
 	struct pmic *p;
 	int ret;
 
-	ret = pmic_init(I2C_PMIC);
+	ret = pmic_init(I2C_0);
 	if (ret)
 		return;
 
diff --git a/board/freescale/mx53loco/Makefile b/board/freescale/mx53loco/Makefile
index 176a8b6e9f..70ac6db1f9 100644
--- a/board/freescale/mx53loco/Makefile
+++ b/board/freescale/mx53loco/Makefile
@@ -5,25 +5,5 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS-y			+= mx53loco.o
-COBJS-$(CONFIG_VIDEO)	+= mx53loco_video.o
-
-COBJS	:= $(COBJS-y)
-SRCS	:= $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y			+= mx53loco.o
+obj-$(CONFIG_VIDEO)	+= mx53loco_video.o
diff --git a/board/freescale/mx53loco/mx53loco.c b/board/freescale/mx53loco/mx53loco.c
index ae7eca85b0..b32a97ff1a 100644
--- a/board/freescale/mx53loco/mx53loco.c
+++ b/board/freescale/mx53loco/mx53loco.c
@@ -30,24 +30,41 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-int dram_init(void)
+static uint32_t mx53_dram_size[2];
+
+phys_size_t get_effective_memsize(void)
 {
-	u32 size1, size2;
+	/*
+	 * WARNING: We must override get_effective_memsize() function here
+	 * to report only the size of the first DRAM bank. This is to make
+	 * U-Boot relocator place U-Boot into valid memory, that is, at the
+	 * end of the first DRAM bank. If we did not override this function
+	 * like so, U-Boot would be placed at the address of the first DRAM
+	 * bank + total DRAM size - sizeof(uboot), which in the setup where
+	 * each DRAM bank contains 512MiB of DRAM would result in placing
+	 * U-Boot into invalid memory area close to the end of the first
+	 * DRAM bank.
+	 */
+	return mx53_dram_size[0];
+}
 
-	size1 = get_ram_size((void *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE);
-	size2 = get_ram_size((void *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE);
+int dram_init(void)
+{
+	mx53_dram_size[0] = get_ram_size((void *)PHYS_SDRAM_1, 1 << 30);
+	mx53_dram_size[1] = get_ram_size((void *)PHYS_SDRAM_2, 1 << 30);
 
-	gd->ram_size = size1 + size2;
+	gd->ram_size = mx53_dram_size[0] + mx53_dram_size[1];
 
 	return 0;
 }
+
 void dram_init_banksize(void)
 {
 	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
-	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+	gd->bd->bi_dram[0].size = mx53_dram_size[0];
 
 	gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
-	gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
+	gd->bd->bi_dram[1].size = mx53_dram_size[1];
 }
 
 u32 get_board_rev(void)
@@ -258,7 +275,7 @@ static int power_init(void)
 	}
 
 	if (!i2c_probe(CONFIG_SYS_FSL_PMIC_I2C_ADDR)) {
-		ret = pmic_init(I2C_PMIC);
+		ret = pmic_init(I2C_0);
 		if (ret)
 			return ret;
 
@@ -343,6 +360,7 @@ int board_early_init_f(void)
 	return 0;
 }
 
+#if defined(CONFIG_DISPLAY_CPUINFO)
 int print_cpuinfo(void)
 {
 	u32 cpurev;
@@ -356,6 +374,7 @@ int print_cpuinfo(void)
 	printf("Reset cause: %s\n", get_reset_cause());
 	return 0;
 }
+#endif
 
 /*
  * Do not overwrite the console
diff --git a/board/freescale/mx53smd/Makefile b/board/freescale/mx53smd/Makefile
index 488b2c8511..5da34c002d 100644
--- a/board/freescale/mx53smd/Makefile
+++ b/board/freescale/mx53smd/Makefile
@@ -6,23 +6,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	:= mx53smd.o
-
-SRCS	:= $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	:= mx53smd.o
diff --git a/board/freescale/mx6qarm2/Makefile b/board/freescale/mx6qarm2/Makefile
index bd37558475..79401f4edf 100644
--- a/board/freescale/mx6qarm2/Makefile
+++ b/board/freescale/mx6qarm2/Makefile
@@ -6,23 +6,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	:= mx6qarm2.o
-
-SRCS	:= $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	:= mx6qarm2.o
diff --git a/board/freescale/mx6qarm2/mx6qarm2.c b/board/freescale/mx6qarm2/mx6qarm2.c
index 05c938fcc9..6c51f3a182 100644
--- a/board/freescale/mx6qarm2/mx6qarm2.c
+++ b/board/freescale/mx6qarm2/mx6qarm2.c
@@ -7,7 +7,7 @@
 #include <common.h>
 #include <asm/io.h>
 #include <asm/arch/imx-regs.h>
-#include <asm/arch/mx6q_pins.h>
+#include <asm/arch/mx6-pins.h>
 #include <asm/arch/clock.h>
 #include <asm/errno.h>
 #include <asm/gpio.h>
@@ -38,52 +38,52 @@ int dram_init(void)
 }
 
 iomux_v3_cfg_t const uart4_pads[] = {
-	MX6_PAD_KEY_COL0__UART4_TXD | MUX_PAD_CTRL(UART_PAD_CTRL),
-	MX6_PAD_KEY_ROW0__UART4_RXD | MUX_PAD_CTRL(UART_PAD_CTRL),
+	MX6_PAD_KEY_COL0__UART4_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
+	MX6_PAD_KEY_ROW0__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
 };
 
 iomux_v3_cfg_t const usdhc3_pads[] = {
-	MX6_PAD_SD3_CLK__USDHC3_CLK   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD3_CMD__USDHC3_CMD   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD3_DAT0__USDHC3_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD3_DAT1__USDHC3_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD3_DAT2__USDHC3_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD3_DAT3__USDHC3_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD3_DAT4__USDHC3_DAT4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD3_DAT5__USDHC3_DAT5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD3_DAT6__USDHC3_DAT6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD3_DAT7__USDHC3_DAT7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_NANDF_CS0__GPIO_6_11  | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
+	MX6_PAD_SD3_CLK__SD3_CLK   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD3_CMD__SD3_CMD   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_NANDF_CS0__GPIO6_IO11  | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
 };
 
 iomux_v3_cfg_t const usdhc4_pads[] = {
-	MX6_PAD_SD4_CLK__USDHC4_CLK   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD4_CMD__USDHC4_CMD   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD4_DAT0__USDHC4_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD4_DAT1__USDHC4_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD4_DAT2__USDHC4_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD4_DAT3__USDHC4_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD4_DAT4__USDHC4_DAT4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD4_DAT5__USDHC4_DAT5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD4_DAT6__USDHC4_DAT6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD4_DAT7__USDHC4_DAT7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD4_CLK__SD4_CLK   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD4_CMD__SD4_CMD   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD4_DAT4__SD4_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD4_DAT5__SD4_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD4_DAT6__SD4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD4_DAT7__SD4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 };
 
 iomux_v3_cfg_t const enet_pads[] = {
 	MX6_PAD_KEY_COL1__ENET_MDIO        | MUX_PAD_CTRL(ENET_PAD_CTRL),
 	MX6_PAD_KEY_COL2__ENET_MDC         | MUX_PAD_CTRL(ENET_PAD_CTRL),
-	MX6_PAD_RGMII_TXC__ENET_RGMII_TXC  | MUX_PAD_CTRL(ENET_PAD_CTRL),
-	MX6_PAD_RGMII_TD0__ENET_RGMII_TD0  | MUX_PAD_CTRL(ENET_PAD_CTRL),
-	MX6_PAD_RGMII_TD1__ENET_RGMII_TD1  | MUX_PAD_CTRL(ENET_PAD_CTRL),
-	MX6_PAD_RGMII_TD2__ENET_RGMII_TD2  | MUX_PAD_CTRL(ENET_PAD_CTRL),
-	MX6_PAD_RGMII_TD3__ENET_RGMII_TD3  | MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_RGMII_TXC__RGMII_TXC  | MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_RGMII_TD0__RGMII_TD0  | MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_RGMII_TD1__RGMII_TD1  | MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_RGMII_TD2__RGMII_TD2  | MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_RGMII_TD3__RGMII_TD3  | MUX_PAD_CTRL(ENET_PAD_CTRL),
 	MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
 	MX6_PAD_ENET_REF_CLK__ENET_TX_CLK  | MUX_PAD_CTRL(ENET_PAD_CTRL),
-	MX6_PAD_RGMII_RXC__ENET_RGMII_RXC  | MUX_PAD_CTRL(ENET_PAD_CTRL),
-	MX6_PAD_RGMII_RD0__ENET_RGMII_RD0  | MUX_PAD_CTRL(ENET_PAD_CTRL),
-	MX6_PAD_RGMII_RD1__ENET_RGMII_RD1  | MUX_PAD_CTRL(ENET_PAD_CTRL),
-	MX6_PAD_RGMII_RD2__ENET_RGMII_RD2  | MUX_PAD_CTRL(ENET_PAD_CTRL),
-	MX6_PAD_RGMII_RD3__ENET_RGMII_RD3  | MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_RGMII_RXC__RGMII_RXC  | MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_RGMII_RD0__RGMII_RD0  | MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_RGMII_RD1__RGMII_RD1  | MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_RGMII_RD2__RGMII_RD2  | MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_RGMII_RD3__RGMII_RD3  | MUX_PAD_CTRL(ENET_PAD_CTRL),
 	MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
 };
 
@@ -186,13 +186,10 @@ int fecmxc_mii_postcall(int phy)
 int board_eth_init(bd_t *bis)
 {
 	struct eth_device *dev;
-	int ret;
+	int ret = cpu_eth_init(bis);
 
-	ret = cpu_eth_init(bis);
-	if (ret) {
-		printf("FEC MXC: %s:failed\n", __func__);
+	if (ret)
 		return ret;
-	}
 
 	dev = eth_get_dev_by_name("FEC");
 	if (!dev) {
diff --git a/board/freescale/mx6qsabreauto/Makefile b/board/freescale/mx6qsabreauto/Makefile
index e9c2eb4699..ac5bc81635 100644
--- a/board/freescale/mx6qsabreauto/Makefile
+++ b/board/freescale/mx6qsabreauto/Makefile
@@ -6,23 +6,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB    = $(obj)lib$(BOARD).o
-
-COBJS  := mx6qsabreauto.o
-
-SRCS   := $(COBJS:.o=.c)
-OBJS   := $(addprefix $(obj),$(COBJS))
-
-$(LIB):        $(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y  := mx6qsabreauto.o
diff --git a/board/freescale/mx6qsabreauto/imximage.cfg b/board/freescale/mx6qsabreauto/imximage.cfg
index 6d192a6b4b..16bf473164 100644
--- a/board/freescale/mx6qsabreauto/imximage.cfg
+++ b/board/freescale/mx6qsabreauto/imximage.cfg
@@ -29,119 +29,101 @@ BOOT_FROM	sd
  *	Address	  absolute address of the register
  *	value	  value to be stored in the register
  */
+DATA 4 0x020e0798 0x000C0000
+DATA 4 0x020e0758 0x00000000
+DATA 4 0x020e0588 0x00000030
+DATA 4 0x020e0594 0x00000030
+DATA 4 0x020e056c 0x00000030
+DATA 4 0x020e0578 0x00000030
+DATA 4 0x020e074c 0x00000030
+DATA 4 0x020e057c 0x00000030
+DATA 4 0x020e058c 0x00000000
+DATA 4 0x020e059c 0x00000030
+DATA 4 0x020e05a0 0x00000030
+DATA 4 0x020e078c 0x00000030
+DATA 4 0x020e0750 0x00020000
 DATA 4 0x020e05a8 0x00000028
 DATA 4 0x020e05b0 0x00000028
 DATA 4 0x020e0524 0x00000028
 DATA 4 0x020e051c 0x00000028
-
 DATA 4 0x020e0518 0x00000028
 DATA 4 0x020e050c 0x00000028
 DATA 4 0x020e05b8 0x00000028
 DATA 4 0x020e05c0 0x00000028
-
-DATA 4 0x020e05ac 0x00000028
-DATA 4 0x020e05b4 0x00000028
-DATA 4 0x020e0528 0x00000028
-DATA 4 0x020e0520 0x00000028
-
-DATA 4 0x020e0514 0x00000028
-DATA 4 0x020e0510 0x00000028
-DATA 4 0x020e05bc 0x00000028
-DATA 4 0x020e05c4 0x00000028
-
-DATA 4 0x020e056c 0x00000030
-DATA 4 0x020e0578 0x00000030
-DATA 4 0x020e0588 0x00000030
-DATA 4 0x020e0594 0x00000030
-
-DATA 4 0x020e057c 0x00000030
-DATA 4 0x020e0590 0x00000030
-DATA 4 0x020e0598 0x00000030
-DATA 4 0x020e058c 0x00000000
-
-DATA 4 0x020e059c 0x00003030
-DATA 4 0x020e05a0 0x00003030
+DATA 4 0x020e0774 0x00020000
 DATA 4 0x020e0784 0x00000028
 DATA 4 0x020e0788 0x00000028
-
 DATA 4 0x020e0794 0x00000028
 DATA 4 0x020e079c 0x00000028
 DATA 4 0x020e07a0 0x00000028
 DATA 4 0x020e07a4 0x00000028
-
 DATA 4 0x020e07a8 0x00000028
 DATA 4 0x020e0748 0x00000028
-DATA 4 0x020e074c 0x00000030
-DATA 4 0x020e0750 0x00020000
-
-DATA 4 0x020e0758 0x00000000
-DATA 4 0x020e0774 0x00020000
-DATA 4 0x020e078c 0x00000030
-DATA 4 0x020e0798 0x000C0000
-
+DATA 4 0x020e05ac 0x00000028
+DATA 4 0x020e05b4 0x00000028
+DATA 4 0x020e0528 0x00000028
+DATA 4 0x020e0520 0x00000028
+DATA 4 0x020e0514 0x00000028
+DATA 4 0x020e0510 0x00000028
+DATA 4 0x020e05bc 0x00000028
+DATA 4 0x020e05c4 0x00000028
+DATA 4 0x021b0800 0xa1390003
+DATA 4 0x021b080c 0x001F001F
+DATA 4 0x021b0810 0x001F001F
+DATA 4 0x021b480c 0x001F001F
+DATA 4 0x021b4810 0x001F001F
+DATA 4 0x021b083c 0x43260335
+DATA 4 0x021b0840 0x031A030B
+DATA 4 0x021b483c 0x4323033B
+DATA 4 0x021b4840 0x0323026F
+DATA 4 0x021b0848 0x483D4545
+DATA 4 0x021b4848 0x44433E48
+DATA 4 0x021b0850 0x41444840
+DATA 4 0x021b4850 0x4835483E
 DATA 4 0x021b081c 0x33333333
 DATA 4 0x021b0820 0x33333333
 DATA 4 0x021b0824 0x33333333
 DATA 4 0x021b0828 0x33333333
-
 DATA 4 0x021b481c 0x33333333
 DATA 4 0x021b4820 0x33333333
 DATA 4 0x021b4824 0x33333333
 DATA 4 0x021b4828 0x33333333
-
+DATA 4 0x021b08b8 0x00000800
+DATA 4 0x021b48b8 0x00000800
+DATA 4 0x021b0004 0x00020036
+DATA 4 0x021b0008 0x09444040
+DATA 4 0x021b000c 0x8A8F7955
+DATA 4 0x021b0010 0xFF328F64
+DATA 4 0x021b0014 0x01FF00DB
 DATA 4 0x021b0018 0x00001740
-
 DATA 4 0x021b001c 0x00008000
-DATA 4 0x021b000c 0x8A8F7975
-DATA 4 0x021b0010 0xFF538E64
-DATA 4 0x021b0014 0x01FF00DB
-DATA 4 0x021b002c 0x000026D2
-
-DATA 4 0x021b0030 0x008F0E21
-DATA 4 0x021b0008 0x09444040
-DATA 4 0x021b0004 0x00020036
+DATA 4 0x021b002c 0x000026d2
+DATA 4 0x021b0030 0x008F1023
 DATA 4 0x021b0040 0x00000047
 DATA 4 0x021b0000 0x841A0000
-
 DATA 4 0x021b001c 0x04088032
 DATA 4 0x021b001c 0x00008033
-DATA 4 0x021b001c 0x00428031
+DATA 4 0x021b001c 0x00048031
 DATA 4 0x021b001c 0x09408030
-
 DATA 4 0x021b001c 0x04008040
-DATA 4 0x021b0800 0xA1380003
 DATA 4 0x021b0020 0x00005800
-DATA 4 0x021b0818 0x00000007
-DATA 4 0x021b4818 0x00000007
-
-/* Calibration values based on ARD and 528MHz */
-DATA 4 0x021b083c 0x434B0358
-DATA 4 0x021b0840 0x033D033C
-DATA 4 0x021b483c 0x03520362
-DATA 4 0x021b4840 0x03480318
-DATA 4 0x021b0848 0x41383A3C
-DATA 4 0x021b4848 0x3F3C374A
-DATA 4 0x021b0850 0x42434444
-DATA 4 0x021b4850 0x4932473A
-
-DATA 4 0x021b080c 0x001F001F
-DATA 4 0x021b0810 0x001F001F
-
-DATA 4 0x021b480c 0x001F001F
-DATA 4 0x021b4810 0x001F001F
-
-DATA 4 0x021b08b8 0x00000800
-DATA 4 0x021b48b8 0x00000800
-
-DATA 4 0x021b0404 0x00011006
+DATA 4 0x021b0818 0x00011117
+DATA 4 0x021b4818 0x00011117
 DATA 4 0x021b0004 0x00025576
-
+DATA 4 0x021b0404 0x00011006
 DATA 4 0x021b001c 0x00000000
 
+/* set the default clock gate to save power */
 DATA 4 0x020c4068 0x00C03F3F
-DATA 4 0x020c406c 0x0030FC00
+DATA 4 0x020c406c 0x0030FC03
 DATA 4 0x020c4070 0x0FFFC000
 DATA 4 0x020c4074 0x3FF00000
-DATA 4 0x020c4078 0x00FFF300
-DATA 4 0x020c407c 0x0F0000C3
-DATA 4 0x020c4080 0x000003FF
+DATA 4 0x020c4078 0xFFFFF300
+DATA 4 0x020c407c 0x0F0000F3
+DATA 4 0x020c4080 0x00000FFF
+
+/* enable AXI cache for VDOA/VPU/IPU */
+DATA 4 0x020e0010 0xF00000CF
+/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
+DATA 4 0x020e0018 0x007F007F
+DATA 4 0x020e001c 0x007F007F
diff --git a/board/freescale/mx6qsabreauto/mx6qsabreauto.c b/board/freescale/mx6qsabreauto/mx6qsabreauto.c
index c55ee8783d..928dadf809 100644
--- a/board/freescale/mx6qsabreauto/mx6qsabreauto.c
+++ b/board/freescale/mx6qsabreauto/mx6qsabreauto.c
@@ -11,7 +11,7 @@
 #include <asm/arch/clock.h>
 #include <asm/arch/imx-regs.h>
 #include <asm/arch/iomux.h>
-#include <asm/arch/mx6q_pins.h>
+#include <asm/arch/mx6-pins.h>
 #include <asm/errno.h>
 #include <asm/gpio.h>
 #include <asm/imx-common/iomux-v3.h>
@@ -51,25 +51,25 @@ int dram_init(void)
 }
 
 iomux_v3_cfg_t const uart4_pads[] = {
-	MX6_PAD_KEY_COL0__UART4_TXD | MUX_PAD_CTRL(UART_PAD_CTRL),
-	MX6_PAD_KEY_ROW0__UART4_RXD | MUX_PAD_CTRL(UART_PAD_CTRL),
+	MX6_PAD_KEY_COL0__UART4_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
+	MX6_PAD_KEY_ROW0__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
 };
 
 iomux_v3_cfg_t const enet_pads[] = {
 	MX6_PAD_KEY_COL1__ENET_MDIO		| MUX_PAD_CTRL(ENET_PAD_CTRL),
 	MX6_PAD_KEY_COL2__ENET_MDC		| MUX_PAD_CTRL(ENET_PAD_CTRL),
-	MX6_PAD_RGMII_TXC__ENET_RGMII_TXC	| MUX_PAD_CTRL(ENET_PAD_CTRL),
-	MX6_PAD_RGMII_TD0__ENET_RGMII_TD0	| MUX_PAD_CTRL(ENET_PAD_CTRL),
-	MX6_PAD_RGMII_TD1__ENET_RGMII_TD1	| MUX_PAD_CTRL(ENET_PAD_CTRL),
-	MX6_PAD_RGMII_TD2__ENET_RGMII_TD2	| MUX_PAD_CTRL(ENET_PAD_CTRL),
-	MX6_PAD_RGMII_TD3__ENET_RGMII_TD3	| MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_RGMII_TXC__RGMII_TXC	| MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_RGMII_TD0__RGMII_TD0	| MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_RGMII_TD1__RGMII_TD1	| MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_RGMII_TD2__RGMII_TD2	| MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_RGMII_TD3__RGMII_TD3	| MUX_PAD_CTRL(ENET_PAD_CTRL),
 	MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL	| MUX_PAD_CTRL(ENET_PAD_CTRL),
 	MX6_PAD_ENET_REF_CLK__ENET_TX_CLK	| MUX_PAD_CTRL(ENET_PAD_CTRL),
-	MX6_PAD_RGMII_RXC__ENET_RGMII_RXC	| MUX_PAD_CTRL(ENET_PAD_CTRL),
-	MX6_PAD_RGMII_RD0__ENET_RGMII_RD0	| MUX_PAD_CTRL(ENET_PAD_CTRL),
-	MX6_PAD_RGMII_RD1__ENET_RGMII_RD1	| MUX_PAD_CTRL(ENET_PAD_CTRL),
-	MX6_PAD_RGMII_RD2__ENET_RGMII_RD2	| MUX_PAD_CTRL(ENET_PAD_CTRL),
-	MX6_PAD_RGMII_RD3__ENET_RGMII_RD3	| MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_RGMII_RXC__RGMII_RXC	| MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_RGMII_RD0__RGMII_RD0	| MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_RGMII_RD1__RGMII_RD1	| MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_RGMII_RD2__RGMII_RD2	| MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_RGMII_RD3__RGMII_RD3	| MUX_PAD_CTRL(ENET_PAD_CTRL),
 	MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL	| MUX_PAD_CTRL(ENET_PAD_CTRL),
 };
 
@@ -77,12 +77,12 @@ iomux_v3_cfg_t const enet_pads[] = {
 struct i2c_pads_info i2c_pad_info1 = {
 	.scl = {
 		.i2c_mode = MX6_PAD_EIM_EB2__I2C2_SCL | PC,
-		.gpio_mode = MX6_PAD_EIM_EB2__GPIO_2_30 | PC,
+		.gpio_mode = MX6_PAD_EIM_EB2__GPIO2_IO30 | PC,
 		.gp = IMX_GPIO_NR(2, 30)
 	},
 	.sda = {
 		.i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA | PC,
-		.gpio_mode = MX6_PAD_KEY_ROW3__GPIO_4_13 | PC,
+		.gpio_mode = MX6_PAD_KEY_ROW3__GPIO4_IO13 | PC,
 		.gp = IMX_GPIO_NR(4, 13)
 	}
 };
@@ -94,22 +94,22 @@ struct i2c_pads_info i2c_pad_info1 = {
 struct i2c_pads_info i2c_pad_info2 = {
 	.scl = {
 		.i2c_mode = MX6_PAD_GPIO_3__I2C3_SCL | PC,
-		.gpio_mode = MX6_PAD_GPIO_3__GPIO_1_3 | PC,
+		.gpio_mode = MX6_PAD_GPIO_3__GPIO1_IO03 | PC,
 		.gp = IMX_GPIO_NR(1, 3)
 	},
 	.sda = {
 		.i2c_mode = MX6_PAD_EIM_D18__I2C3_SDA | PC,
-		.gpio_mode = MX6_PAD_EIM_D18__GPIO_3_18 | PC,
+		.gpio_mode = MX6_PAD_EIM_D18__GPIO3_IO18 | PC,
 		.gp = IMX_GPIO_NR(3, 18)
 	}
 };
 
 iomux_v3_cfg_t const i2c3_pads[] = {
-	MX6_PAD_EIM_A24__GPIO_5_4		| MUX_PAD_CTRL(NO_PAD_CTRL),
+	MX6_PAD_EIM_A24__GPIO5_IO04		| MUX_PAD_CTRL(NO_PAD_CTRL),
 };
 
 iomux_v3_cfg_t const port_exp[] = {
-	MX6_PAD_SD2_DAT0__GPIO_1_15		| MUX_PAD_CTRL(NO_PAD_CTRL),
+	MX6_PAD_SD2_DAT0__GPIO1_IO15		| MUX_PAD_CTRL(NO_PAD_CTRL),
 };
 
 static void setup_iomux_enet(void)
@@ -118,18 +118,18 @@ static void setup_iomux_enet(void)
 }
 
 iomux_v3_cfg_t const usdhc3_pads[] = {
-	MX6_PAD_SD3_CLK__USDHC3_CLK	| MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD3_CMD__USDHC3_CMD	| MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD3_DAT0__USDHC3_DAT0	| MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD3_DAT1__USDHC3_DAT1	| MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD3_DAT2__USDHC3_DAT2	| MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD3_DAT3__USDHC3_DAT3	| MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD3_DAT4__USDHC3_DAT4	| MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD3_DAT5__USDHC3_DAT5	| MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD3_DAT6__USDHC3_DAT6	| MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD3_DAT7__USDHC3_DAT7	| MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_GPIO_18__USDHC3_VSELECT | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_NANDF_CS2__GPIO_6_15   | MUX_PAD_CTRL(NO_PAD_CTRL),
+	MX6_PAD_SD3_CLK__SD3_CLK	| MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD3_CMD__SD3_CMD	| MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD3_DAT0__SD3_DATA0	| MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD3_DAT1__SD3_DATA1	| MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD3_DAT2__SD3_DATA2	| MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD3_DAT3__SD3_DATA3	| MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD3_DAT4__SD3_DATA4	| MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD3_DAT5__SD3_DATA5	| MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD3_DAT6__SD3_DATA6	| MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD3_DAT7__SD3_DATA7	| MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_GPIO_18__SD3_VSELECT | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_NANDF_CS2__GPIO6_IO15   | MUX_PAD_CTRL(NO_PAD_CTRL),
 };
 
 static void setup_iomux_uart(void)
@@ -192,15 +192,9 @@ int board_phy_config(struct phy_device *phydev)
 
 int board_eth_init(bd_t *bis)
 {
-	int ret;
-
 	setup_iomux_enet();
 
-	ret = cpu_eth_init(bis);
-	if (ret)
-		printf("FEC MXC: %s:failed\n", __func__);
-
-	return ret;
+	return cpu_eth_init(bis);
 }
 
 #define BOARD_REV_B  0x200
diff --git a/board/freescale/mx6sabresd/Makefile b/board/freescale/mx6sabresd/Makefile
index 240fce99bd..cfca2ef79a 100644
--- a/board/freescale/mx6sabresd/Makefile
+++ b/board/freescale/mx6sabresd/Makefile
@@ -6,23 +6,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB    = $(obj)lib$(BOARD).o
-
-COBJS  := mx6sabresd.o
-
-SRCS   := $(COBJS:.o=.c)
-OBJS   := $(addprefix $(obj),$(COBJS))
-
-$(LIB):        $(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y  := mx6sabresd.o
diff --git a/board/freescale/mx6sabresd/mx6sabresd.c b/board/freescale/mx6sabresd/mx6sabresd.c
index 9dbe605cf4..d7d932eeb8 100644
--- a/board/freescale/mx6sabresd/mx6sabresd.c
+++ b/board/freescale/mx6sabresd/mx6sabresd.c
@@ -37,6 +37,9 @@ DECLARE_GLOBAL_DATA_PTR;
 #define ENET_PAD_CTRL  (PAD_CTL_PUS_100K_UP |			\
 	PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
 
+#define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \
+		      PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
+
 int dram_init(void)
 {
 	gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
@@ -45,28 +48,28 @@ int dram_init(void)
 }
 
 iomux_v3_cfg_t const uart1_pads[] = {
-	MX6_PAD_CSI0_DAT10__UART1_TXD | MUX_PAD_CTRL(UART_PAD_CTRL),
-	MX6_PAD_CSI0_DAT11__UART1_RXD | MUX_PAD_CTRL(UART_PAD_CTRL),
+	MX6_PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
+	MX6_PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
 };
 
 iomux_v3_cfg_t const enet_pads[] = {
 	MX6_PAD_ENET_MDIO__ENET_MDIO		| MUX_PAD_CTRL(ENET_PAD_CTRL),
 	MX6_PAD_ENET_MDC__ENET_MDC		| MUX_PAD_CTRL(ENET_PAD_CTRL),
-	MX6_PAD_RGMII_TXC__ENET_RGMII_TXC	| MUX_PAD_CTRL(ENET_PAD_CTRL),
-	MX6_PAD_RGMII_TD0__ENET_RGMII_TD0	| MUX_PAD_CTRL(ENET_PAD_CTRL),
-	MX6_PAD_RGMII_TD1__ENET_RGMII_TD1	| MUX_PAD_CTRL(ENET_PAD_CTRL),
-	MX6_PAD_RGMII_TD2__ENET_RGMII_TD2	| MUX_PAD_CTRL(ENET_PAD_CTRL),
-	MX6_PAD_RGMII_TD3__ENET_RGMII_TD3	| MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_RGMII_TXC__RGMII_TXC	| MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_RGMII_TD0__RGMII_TD0	| MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_RGMII_TD1__RGMII_TD1	| MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_RGMII_TD2__RGMII_TD2	| MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_RGMII_TD3__RGMII_TD3	| MUX_PAD_CTRL(ENET_PAD_CTRL),
 	MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL	| MUX_PAD_CTRL(ENET_PAD_CTRL),
 	MX6_PAD_ENET_REF_CLK__ENET_TX_CLK	| MUX_PAD_CTRL(ENET_PAD_CTRL),
-	MX6_PAD_RGMII_RXC__ENET_RGMII_RXC	| MUX_PAD_CTRL(ENET_PAD_CTRL),
-	MX6_PAD_RGMII_RD0__ENET_RGMII_RD0	| MUX_PAD_CTRL(ENET_PAD_CTRL),
-	MX6_PAD_RGMII_RD1__ENET_RGMII_RD1	| MUX_PAD_CTRL(ENET_PAD_CTRL),
-	MX6_PAD_RGMII_RD2__ENET_RGMII_RD2	| MUX_PAD_CTRL(ENET_PAD_CTRL),
-	MX6_PAD_RGMII_RD3__ENET_RGMII_RD3	| MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_RGMII_RXC__RGMII_RXC	| MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_RGMII_RD0__RGMII_RD0	| MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_RGMII_RD1__RGMII_RD1	| MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_RGMII_RD2__RGMII_RD2	| MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_RGMII_RD3__RGMII_RD3	| MUX_PAD_CTRL(ENET_PAD_CTRL),
 	MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL	| MUX_PAD_CTRL(ENET_PAD_CTRL),
 	/* AR8031 PHY Reset */
-	MX6_PAD_ENET_CRS_DV__GPIO_1_25		| MUX_PAD_CTRL(NO_PAD_CTRL),
+	MX6_PAD_ENET_CRS_DV__GPIO1_IO25		| MUX_PAD_CTRL(NO_PAD_CTRL),
 };
 
 static void setup_iomux_enet(void)
@@ -80,44 +83,72 @@ static void setup_iomux_enet(void)
 }
 
 iomux_v3_cfg_t const usdhc2_pads[] = {
-	MX6_PAD_SD2_CLK__USDHC2_CLK	| MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD2_CMD__USDHC2_CMD	| MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD2_DAT0__USDHC2_DAT0	| MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD2_DAT1__USDHC2_DAT1	| MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD2_DAT2__USDHC2_DAT2	| MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD2_DAT3__USDHC2_DAT3	| MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_NANDF_D4__USDHC2_DAT4	| MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_NANDF_D5__USDHC2_DAT5	| MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_NANDF_D6__USDHC2_DAT6	| MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_NANDF_D7__USDHC2_DAT7	| MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_NANDF_D2__GPIO_2_2	| MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
+	MX6_PAD_SD2_CLK__SD2_CLK	| MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD2_CMD__SD2_CMD	| MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD2_DAT0__SD2_DATA0	| MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD2_DAT1__SD2_DATA1	| MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD2_DAT2__SD2_DATA2	| MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD2_DAT3__SD2_DATA3	| MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_NANDF_D4__SD2_DATA4	| MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_NANDF_D5__SD2_DATA5	| MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_NANDF_D6__SD2_DATA6	| MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_NANDF_D7__SD2_DATA7	| MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_NANDF_D2__GPIO2_IO02	| MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
 };
 
 iomux_v3_cfg_t const usdhc3_pads[] = {
-	MX6_PAD_SD3_CLK__USDHC3_CLK   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD3_CMD__USDHC3_CMD   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD3_DAT0__USDHC3_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD3_DAT1__USDHC3_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD3_DAT2__USDHC3_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD3_DAT3__USDHC3_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD3_DAT4__USDHC3_DAT4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD3_DAT5__USDHC3_DAT5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD3_DAT6__USDHC3_DAT6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD3_DAT7__USDHC3_DAT7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_NANDF_D0__GPIO_2_0    | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
+	MX6_PAD_SD3_CLK__SD3_CLK   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD3_CMD__SD3_CMD   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_NANDF_D0__GPIO2_IO00    | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
 };
 
 iomux_v3_cfg_t const usdhc4_pads[] = {
-	MX6_PAD_SD4_CLK__USDHC4_CLK   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD4_CMD__USDHC4_CMD   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD4_DAT0__USDHC4_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD4_DAT1__USDHC4_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD4_DAT2__USDHC4_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD4_DAT3__USDHC4_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD4_DAT4__USDHC4_DAT4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD4_DAT5__USDHC4_DAT5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD4_DAT6__USDHC4_DAT6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD4_DAT7__USDHC4_DAT7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD4_CLK__SD4_CLK   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD4_CMD__SD4_CMD   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD4_DAT4__SD4_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD4_DAT5__SD4_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD4_DAT6__SD4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD4_DAT7__SD4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+};
+
+iomux_v3_cfg_t const ecspi1_pads[] = {
+	MX6_PAD_KEY_COL0__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
+	MX6_PAD_KEY_COL1__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
+	MX6_PAD_KEY_ROW0__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
+	MX6_PAD_KEY_ROW1__GPIO4_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+static void setup_spi(void)
+{
+	imx_iomux_v3_setup_multiple_pads(ecspi1_pads, ARRAY_SIZE(ecspi1_pads));
+}
+
+iomux_v3_cfg_t const pcie_pads[] = {
+	MX6_PAD_EIM_D19__GPIO3_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL),	/* POWER */
+	MX6_PAD_GPIO_17__GPIO7_IO12 | MUX_PAD_CTRL(NO_PAD_CTRL),	/* RESET */
+};
+
+static void setup_pcie(void)
+{
+	imx_iomux_v3_setup_multiple_pads(pcie_pads, ARRAY_SIZE(pcie_pads));
+}
+
+iomux_v3_cfg_t const di0_pads[] = {
+	MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK,	/* DISP0_CLK */
+	MX6_PAD_DI0_PIN2__IPU1_DI0_PIN02,		/* DISP0_HSYNC */
+	MX6_PAD_DI0_PIN3__IPU1_DI0_PIN03,		/* DISP0_VSYNC */
 };
 
 static void setup_iomux_uart(void)
@@ -249,8 +280,22 @@ static int detect_hdmi(struct display_info_t const *dev)
 	return readb(&hdmi->phy_stat0) & HDMI_DVI_STAT;
 }
 
+
+static void disable_lvds(struct display_info_t const *dev)
+{
+	struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
+
+	int reg = readl(&iomux->gpr[2]);
+
+	reg &= ~(IOMUXC_GPR2_LVDS_CH0_MODE_MASK |
+		 IOMUXC_GPR2_LVDS_CH1_MODE_MASK);
+
+	writel(reg, &iomux->gpr[2]);
+}
+
 static void do_enable_hdmi(struct display_info_t const *dev)
 {
+	disable_lvds(dev);
 	imx_enable_hdmi_phy();
 }
 
@@ -259,18 +304,19 @@ static void enable_lvds(struct display_info_t const *dev)
 	struct iomuxc *iomux = (struct iomuxc *)
 				IOMUXC_BASE_ADDR;
 	u32 reg = readl(&iomux->gpr[2]);
-	reg |= IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT |
-	       IOMUXC_GPR2_DATA_WIDTH_CH1_24BIT;
+	reg |= IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT |
+	       IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT;
 	writel(reg, &iomux->gpr[2]);
 }
+
 static struct display_info_t const displays[] = {{
 	.bus	= -1,
 	.addr	= 0,
-	.pixfmt	= IPU_PIX_FMT_RGB24,
-	.detect	= detect_hdmi,
-	.enable	= do_enable_hdmi,
+	.pixfmt	= IPU_PIX_FMT_RGB666,
+	.detect	= NULL,
+	.enable	= enable_lvds,
 	.mode	= {
-		.name           = "HDMI",
+		.name           = "Hannstar-XGA",
 		.refresh        = 60,
 		.xres           = 1024,
 		.yres           = 768,
@@ -286,11 +332,11 @@ static struct display_info_t const displays[] = {{
 } }, {
 	.bus	= -1,
 	.addr	= 0,
-	.pixfmt	= IPU_PIX_FMT_LVDS666,
-	.detect	= NULL,
-	.enable	= enable_lvds,
+	.pixfmt	= IPU_PIX_FMT_RGB24,
+	.detect	= detect_hdmi,
+	.enable	= do_enable_hdmi,
 	.mode	= {
-		.name           = "Hannstar-XGA",
+		.name           = "HDMI",
 		.refresh        = 60,
 		.xres           = 1024,
 		.yres           = 768,
@@ -356,11 +402,14 @@ static void setup_display(void)
 	struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
 	int reg;
 
+	/* Setup HSYNC, VSYNC, DISP_CLK for debugging purposes */
+	imx_iomux_v3_setup_multiple_pads(di0_pads, ARRAY_SIZE(di0_pads));
+
 	enable_ipu_clock();
 	imx_setup_hdmi();
 
 	/* Turn on LDB0, LDB1, IPU,IPU DI0 clocks */
-	reg = __raw_readl(&mxc_ccm->CCGR3);
+	reg = readl(&mxc_ccm->CCGR3);
 	reg |=  MXC_CCM_CCGR3_LDB_DI0_MASK | MXC_CCM_CCGR3_LDB_DI1_MASK;
 	writel(reg, &mxc_ccm->CCGR3);
 
@@ -414,15 +463,10 @@ int overwrite_console(void)
 
 int board_eth_init(bd_t *bis)
 {
-	int ret;
-
 	setup_iomux_enet();
+	setup_pcie();
 
-	ret = cpu_eth_init(bis);
-	if (ret)
-		printf("FEC MXC: %s:failed\n", __func__);
-
-	return ret;
+	return cpu_eth_init(bis);
 }
 
 int board_early_init_f(void)
@@ -440,6 +484,10 @@ int board_init(void)
 	/* address of boot parameters */
 	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
 
+#ifdef CONFIG_MXC_SPI
+	setup_spi();
+#endif
+
 	return 0;
 }
 
diff --git a/board/freescale/mx6slevk/Makefile b/board/freescale/mx6slevk/Makefile
index bcd8e4a3c2..6e1971ee27 100644
--- a/board/freescale/mx6slevk/Makefile
+++ b/board/freescale/mx6slevk/Makefile
@@ -3,23 +3,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB    = $(obj)lib$(BOARD).o
-
-COBJS  := mx6slevk.o
-
-SRCS   := $(COBJS:.o=.c)
-OBJS   := $(addprefix $(obj),$(COBJS))
-
-$(LIB):        $(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y  := mx6slevk.o
diff --git a/board/freescale/mx6slevk/mx6slevk.c b/board/freescale/mx6slevk/mx6slevk.c
index 643fdac2b3..aadad3266f 100644
--- a/board/freescale/mx6slevk/mx6slevk.c
+++ b/board/freescale/mx6slevk/mx6slevk.c
@@ -14,7 +14,7 @@
 #include <asm/gpio.h>
 #include <asm/imx-common/iomux-v3.h>
 #include <asm/io.h>
-#include <asm/sizes.h>
+#include <linux/sizes.h>
 #include <common.h>
 #include <fsl_esdhc.h>
 #include <mmc.h>
@@ -106,17 +106,9 @@ int board_mmc_init(bd_t *bis)
 #ifdef CONFIG_FEC_MXC
 int board_eth_init(bd_t *bis)
 {
-	int ret;
-
 	setup_iomux_fec();
 
-	ret = cpu_eth_init(bis);
-	if (ret) {
-		printf("FEC MXC: %s:failed\n", __func__);
-		return ret;
-	}
-
-	return 0;
+	return cpu_eth_init(bis);
 }
 
 static int setup_fec(void)
@@ -128,7 +120,7 @@ static int setup_fec(void)
 	/* clear gpr1[14], gpr1[18:17] to select anatop clock */
 	clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC_MASK, 0);
 
-	ret = enable_fec_anatop_clock();
+	ret = enable_fec_anatop_clock(ENET_50MHz);
 	if (ret)
 		return ret;
 
diff --git a/board/freescale/p1010rdb/Makefile b/board/freescale/p1010rdb/Makefile
index bdd7d68edc..660d1bbc2a 100644
--- a/board/freescale/p1010rdb/Makefile
+++ b/board/freescale/p1010rdb/Makefile
@@ -4,10 +4,6 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
 MINIMAL=
 
 ifdef CONFIG_SPL_BUILD
@@ -18,29 +14,17 @@ endif
 
 ifdef MINIMAL
 
-COBJS-y	+= spl_minimal.o tlb.o law.o
+obj-y	+= spl_minimal.o tlb.o law.o
 
 else
 
-COBJS-y	+= $(BOARD).o
-COBJS-y	+= ddr.o
-COBJS-y	+= law.o
-COBJS-y	+= tlb.o
-
+ifdef CONFIG_SPL_BUILD
+obj-y += spl.o
 endif
 
-SRCS	:= $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS-y))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
-	$(call cmd_link_o_target, $(OBJS))
+obj-y	+= p1010rdb.o
+obj-y	+= ddr.o
+obj-y	+= law.o
+obj-y	+= tlb.o
 
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+endif
diff --git a/board/freescale/p1010rdb/README b/board/freescale/p1010rdb/README
deleted file mode 100644
index 7f18aaa1b2..0000000000
--- a/board/freescale/p1010rdb/README
+++ /dev/null
@@ -1,208 +0,0 @@
-Overview
-=========
-The P1010RDB is a Freescale reference design board that hosts the P1010 SoC.
-
-The P1010 is a cost-effective, low-power, highly integrated host processor
-based on a Power Architecture e500v2 core (maximum core frequency 800/1000 MHz),
-that addresses the requirements of several routing, gateways, storage, consumer,
-and industrial applications. Applications of interest include the main CPUs and
-I/O processors in network attached storage (NAS), the voice over IP (VoIP)
-router/gateway, and wireless LAN (WLAN) and industrial controllers.
-
-The P1010RDB board features are as follows:
-Memory subsystem:
-	- 1Gbyte unbuffered DDR3 SDRAM discrete devices (32-bit bus)
-	- 32 Mbyte NOR flash single-chip memory
-	- 32 Mbyte NAND flash memory
-	- 256 Kbit M24256 I2C EEPROM
-	- 16 Mbyte SPI memory
-	- I2C Board EEPROM 128x8 bit memory
-	- SD/MMC connector to interface with the SD memory card
-Interfaces:
-	- PCIe:
-		- Lane0: x1 mini-PCIe slot
-		- Lane1: x1 PCIe standard slot
-	- SATA:
-		- 1 internal SATA connector to 2.5” 160G SATA2 HDD
-		- 1 eSATA connector to rear panel
-	- 10/100/1000 BaseT Ethernet ports:
-		- eTSEC1, RGMII: one 10/100/1000 port using Vitesse VSC8641XKO
-		- eTSEC2, SGMII: one 10/100/1000 port using Vitesse VSC8221
-		- eTSEC3, SGMII: one 10/100/1000 port using Vitesse VSC8221
-	- USB 2.0 port:
-		- x1 USB2.0 port via an external ULPI PHY to micro-AB connector
-		- x1 USB2.0 port via an internal UTMI PHY to micro-AB connector
-	- FlexCAN ports:
-		- 2 DB-9 female connectors for FlexCAN bus(revision 2.0B)
-		  interface;
-	- DUART interface:
-		- DUART interface: supports two UARTs up to 115200 bps for
-		   console display
-		- RJ45 connectors are used for these 2 UART ports.
-	- TDM
-		- 2 FXS ports connected via an external SLIC to the TDM interface.
-		  SLIC is controllled via SPI.
-		- 1 FXO port connected via a relay to FXS for switchover to POTS
-Board connectors:
-	- Mini-ITX power supply connector
-	- JTAG/COP for debugging
-IEEE Std. 1588 signals for test and measurement
-Real-time clock on I2C bus
-POR
-	- support critical POR setting changed via switch on board
-PCB
-	- 6-layer routing (4-layer signals, 2-layer power and ground)
-
-
-Physical Memory Map on P1010RDB
-===============================
-Address Start   Address End   Memory type	Attributes
-0x0000_0000	0x3fff_ffff   DDR		1G Cacheable
-0xa000_0000	0xdfff_ffff   PCI Express Mem	1G non-cacheable
-0xee00_0000	0xefff_ffff   NOR Flash		32M non-cacheable
-0xffc2_0000	0xffc5_ffff   PCI IO range	256K non-cacheable
-0xffa0_0000	0xffaf_ffff   NAND Flash	1M cacheable
-0xffb0_0000	0xffbf_ffff   Board CPLD	1M non-cacheable
-0xffd0_0000	0xffd0_3fff   L1 for Stack	16K Cacheable TLB0
-0xffe0_0000	0xffef_ffff   CCSR		1M non-cacheable
-
-
-Serial Port Configuration on P1010RDB
-=====================================
-Configure the serial port of the attached computer with the following values:
-	-Data rate: 115200 bps
-	-Number of data bits: 8
-	-Parity: None
-	-Number of Stop bits: 1
-	-Flow Control: Hardware/None
-
-
-Settings of DIP-switch
-======================
-  SW4[1:4]= 1111 and SW6[4]=0 for boot from 16bit NOR flash
-  SW4[1:4]= 1000 and SW6[4]=1 for boot from 8bit NAND flash
-  SW4[1:4]= 0110 and SW6[4]=0 for boot from SPI flash
-Note: 1 stands for 'on', 0 stands for 'off'
-
-
-Setting of hwconfig
-===================
-If FlexCAN or TDM is needed, please set "fsl_p1010mux:tdm_can=can" or
-"fsl_p1010mux:tdm_can=tdm" explicitly in u-booot prompt as below for example:
-setenv hwconfig "fsl_p1010mux:tdm_can=tdm;usb1:dr_mode=host,phy_type=utmi"
-By default, don't set fsl_p1010mux:tdm_can, in this case, spi chip selection
-is set to spi-flash instead of to SLIC/TDM/DAC and tdm_can_sel is set to TDM
-instead of to CAN/UART1.
-
-
-Build and burn u-boot to NOR flash
-==================================
-1. Build u-boot.bin image
-	export ARCH=powerpc
-	export CROSS_COMPILE=/your_path/powerpc-linux-gnu-
-	make P1010RDB_NOR
-
-2. Burn u-boot.bin into NOR flash
-	=> tftp $loadaddr $uboot
-	=> protect off eff80000 +$filesize
-	=> erase eff80000 +$filesize
-	=> cp.b $loadaddr eff80000 $filesize
-
-3. Check SW4[1:4]= 1111 and SW6[4]=0, then power on.
-
-
-Alternate NOR bank
-==================
-1. Burn u-boot.bin into alternate NOR bank
-	=> tftp $loadaddr $uboot
-	=> protect off eef80000 +$filesize
-	=> erase eef80000 +$filesize
-	=> cp.b $loadaddr eef80000 $filesize
-
-2. Switch to alternate NOR bank
-	=> mw.b ffb00009 1
-	=> reset
-	or set SW1[8]= ON
-
-SW1[8]= OFF: Upper bank used for booting start
-SW1[8]= ON:  Lower bank used for booting start
-CPLD NOR bank selection register address 0xFFB00009 Bit[0]:
-0 - boot from upper 4 sectors
-1 - boot from lower 4 sectors
-
-
-Build and burn u-boot to NAND flash
-===================================
-1. Build u-boot.bin image
-	export ARCH=powerpc
-	export CROSS_COMPILE=/your_path/powerpc-linux-gnu-
-	make P1010RDB_NAND
-
-2. Burn u-boot-nand.bin into NAND flash
-	=> tftp $loadaddr $uboot-nand
-	=> nand erase 0 $filesize
-	=> nand write $loadaddr 0 $filesize
-
-3. Check SW4[1:4]= 1000 and SW6[4]=1, then power on.
-
-
-Build and burn u-boot to SPI flash
-==================================
-1. Build u-boot-spi.bin image
-	make P1010RDB_SPIFLASH_config; make
-	Boot up kernel with rootfs.ext2.gz.uboot.p1010rdb
-	Download u-boot.bin to linux and you can find some config files
-	under /usr/share such as config_xx.dat. Do below command:
-	boot_format config_ddr3_1gb_p1010rdb_800M.dat u-boot.bin -spi \
-			u-boot-spi.bin
-	to generate u-boot-spi.bin.
-
-2. Burn u-boot-spi.bin into SPI flash
-	=> tftp $loadaddr $uboot-spi
-	=> sf erase 0 100000
-	=> sf write $loadaddr 0 $filesize
-
-3. Check SW4[1:4]= 0110 and SW6[4]=0, then power on.
-
-
-CPLD POR setting registers
-==========================
-1. Set POR switch selection register (addr 0xFFB00011) to 0.
-2. Write CPLD POR registers (BCSR0~BCSR3, addr 0xFFB00014~0xFFB00017) with
-   proper values.
-   If change boot ROM location to NOR or NAND flash, need write the IFC_CS0
-   switch command by I2C.
-3. Send reset command.
-   After reset, the new POR setting will be implemented.
-
-Two examples are given in below:
-Switch from NOR to NAND boot with default frequency:
-	=> i2c dev 0
-	=> i2c mw 18 1 f9
-	=> i2c mw 18 3 f0
-	=> mw.b ffb00011 0
-	=> mw.b ffb00017 1
-	=> reset
-Switch from NAND to NOR boot with Core/CCB/DDR (800/400/667 MHz):
-	=> i2c dev 0
-	=> i2c mw 18 1 f1
-	=> i2c mw 18 3 f0
-	=> mw.b ffb00011 0
-	=> mw.b ffb00014 2
-	=> mw.b ffb00015 5
-	=> mw.b ffb00016 3
-	=> mw.b ffb00017 f
-	=> reset
-
-
-Boot Linux from network using TFTP on P1010RDB
-==============================================
-Place uImage, p1010rdb.dtb and rootfs files in the TFTP disk area.
-	=> tftp 1000000 uImage
-	=> tftp 2000000 p1010rdb.dtb
-	=> tftp 3000000 rootfs.ext2.gz.uboot.p1010rdb
-	=> bootm 1000000 3000000 2000000
-
-
-Please contact your local field applications engineer or sales representative
-to obtain related documents, such as P1010-RDB User Guide for details.
diff --git a/board/freescale/p1010rdb/README.P1010RDB-PA b/board/freescale/p1010rdb/README.P1010RDB-PA
new file mode 100644
index 0000000000..cde246dde2
--- /dev/null
+++ b/board/freescale/p1010rdb/README.P1010RDB-PA
@@ -0,0 +1,208 @@
+Overview
+=========
+The P1010RDB is a Freescale reference design board that hosts the P1010 SoC.
+
+The P1010 is a cost-effective, low-power, highly integrated host processor
+based on a Power Architecture e500v2 core (maximum core frequency 800/1000 MHz),
+that addresses the requirements of several routing, gateways, storage, consumer,
+and industrial applications. Applications of interest include the main CPUs and
+I/O processors in network attached storage (NAS), the voice over IP (VoIP)
+router/gateway, and wireless LAN (WLAN) and industrial controllers.
+
+The P1010RDB board features are as follows:
+Memory subsystem:
+	- 1Gbyte unbuffered DDR3 SDRAM discrete devices (32-bit bus)
+	- 32 Mbyte NOR flash single-chip memory
+	- 32 Mbyte NAND flash memory
+	- 256 Kbit M24256 I2C EEPROM
+	- 16 Mbyte SPI memory
+	- I2C Board EEPROM 128x8 bit memory
+	- SD/MMC connector to interface with the SD memory card
+Interfaces:
+	- PCIe:
+		- Lane0: x1 mini-PCIe slot
+		- Lane1: x1 PCIe standard slot
+	- SATA:
+		- 1 internal SATA connector to 2.5” 160G SATA2 HDD
+		- 1 eSATA connector to rear panel
+	- 10/100/1000 BaseT Ethernet ports:
+		- eTSEC1, RGMII: one 10/100/1000 port using Vitesse VSC8641XKO
+		- eTSEC2, SGMII: one 10/100/1000 port using Vitesse VSC8221
+		- eTSEC3, SGMII: one 10/100/1000 port using Vitesse VSC8221
+	- USB 2.0 port:
+		- x1 USB2.0 port via an external ULPI PHY to micro-AB connector
+		- x1 USB2.0 port via an internal UTMI PHY to micro-AB connector
+	- FlexCAN ports:
+		- 2 DB-9 female connectors for FlexCAN bus(revision 2.0B)
+		  interface;
+	- DUART interface:
+		- DUART interface: supports two UARTs up to 115200 bps for
+		   console display
+		- RJ45 connectors are used for these 2 UART ports.
+	- TDM
+		- 2 FXS ports connected via an external SLIC to the TDM interface.
+		  SLIC is controllled via SPI.
+		- 1 FXO port connected via a relay to FXS for switchover to POTS
+Board connectors:
+	- Mini-ITX power supply connector
+	- JTAG/COP for debugging
+IEEE Std. 1588 signals for test and measurement
+Real-time clock on I2C bus
+POR
+	- support critical POR setting changed via switch on board
+PCB
+	- 6-layer routing (4-layer signals, 2-layer power and ground)
+
+
+Physical Memory Map on P1010RDB
+===============================
+Address Start   Address End   Memory type	Attributes
+0x0000_0000	0x3fff_ffff   DDR		1G Cacheable
+0xa000_0000	0xdfff_ffff   PCI Express Mem	1G non-cacheable
+0xee00_0000	0xefff_ffff   NOR Flash		32M non-cacheable
+0xffc2_0000	0xffc5_ffff   PCI IO range	256K non-cacheable
+0xffa0_0000	0xffaf_ffff   NAND Flash	1M cacheable
+0xffb0_0000	0xffbf_ffff   Board CPLD	1M non-cacheable
+0xffd0_0000	0xffd0_3fff   L1 for Stack	16K Cacheable TLB0
+0xffe0_0000	0xffef_ffff   CCSR		1M non-cacheable
+
+
+Serial Port Configuration on P1010RDB
+=====================================
+Configure the serial port of the attached computer with the following values:
+	-Data rate: 115200 bps
+	-Number of data bits: 8
+	-Parity: None
+	-Number of Stop bits: 1
+	-Flow Control: Hardware/None
+
+
+Settings of DIP-switch
+======================
+  SW4[1:4]= 1111 and SW6[4]=0 for boot from 16bit NOR flash
+  SW4[1:4]= 1000 and SW6[4]=1 for boot from 8bit NAND flash
+  SW4[1:4]= 0110 and SW6[4]=0 for boot from SPI flash
+Note: 1 stands for 'on', 0 stands for 'off'
+
+
+Setting of hwconfig
+===================
+If FlexCAN or TDM is needed, please set "fsl_p1010mux:tdm_can=can" or
+"fsl_p1010mux:tdm_can=tdm" explicitly in u-booot prompt as below for example:
+setenv hwconfig "fsl_p1010mux:tdm_can=tdm;usb1:dr_mode=host,phy_type=utmi"
+By default, don't set fsl_p1010mux:tdm_can, in this case, spi chip selection
+is set to spi-flash instead of to SLIC/TDM/DAC and tdm_can_sel is set to TDM
+instead of to CAN/UART1.
+
+
+Build and burn u-boot to NOR flash
+==================================
+1. Build u-boot.bin image
+	export ARCH=powerpc
+	export CROSS_COMPILE=/your_path/powerpc-linux-gnu-
+	make P1010RDB_NOR
+
+2. Burn u-boot.bin into NOR flash
+	=> tftp $loadaddr $uboot
+	=> protect off eff40000 +$filesize
+	=> erase eff40000 +$filesize
+	=> cp.b $loadaddr eff40000 $filesize
+
+3. Check SW4[1:4]= 1111 and SW6[4]=0, then power on.
+
+
+Alternate NOR bank
+==================
+1. Burn u-boot.bin into alternate NOR bank
+	=> tftp $loadaddr $uboot
+	=> protect off eef40000 +$filesize
+	=> erase eef40000 +$filesize
+	=> cp.b $loadaddr eef40000 $filesize
+
+2. Switch to alternate NOR bank
+	=> mw.b ffb00009 1
+	=> reset
+	or set SW1[8]= ON
+
+SW1[8]= OFF: Upper bank used for booting start
+SW1[8]= ON:  Lower bank used for booting start
+CPLD NOR bank selection register address 0xFFB00009 Bit[0]:
+0 - boot from upper 4 sectors
+1 - boot from lower 4 sectors
+
+
+Build and burn u-boot to NAND flash
+===================================
+1. Build u-boot.bin image
+	export ARCH=powerpc
+	export CROSS_COMPILE=/your_path/powerpc-linux-gnu-
+	make P1010RDB_NAND
+
+2. Burn u-boot-nand.bin into NAND flash
+	=> tftp $loadaddr $uboot-nand
+	=> nand erase 0 $filesize
+	=> nand write $loadaddr 0 $filesize
+
+3. Check SW4[1:4]= 1000 and SW6[4]=1, then power on.
+
+
+Build and burn u-boot to SPI flash
+==================================
+1. Build u-boot-spi.bin image
+	make P1010RDB_SPIFLASH_config; make
+	Boot up kernel with rootfs.ext2.gz.uboot.p1010rdb
+	Download u-boot.bin to linux and you can find some config files
+	under /usr/share such as config_xx.dat. Do below command:
+	boot_format config_ddr3_1gb_p1010rdb_800M.dat u-boot.bin -spi \
+			u-boot-spi.bin
+	to generate u-boot-spi.bin.
+
+2. Burn u-boot-spi.bin into SPI flash
+	=> tftp $loadaddr $uboot-spi
+	=> sf erase 0 100000
+	=> sf write $loadaddr 0 $filesize
+
+3. Check SW4[1:4]= 0110 and SW6[4]=0, then power on.
+
+
+CPLD POR setting registers
+==========================
+1. Set POR switch selection register (addr 0xFFB00011) to 0.
+2. Write CPLD POR registers (BCSR0~BCSR3, addr 0xFFB00014~0xFFB00017) with
+   proper values.
+   If change boot ROM location to NOR or NAND flash, need write the IFC_CS0
+   switch command by I2C.
+3. Send reset command.
+   After reset, the new POR setting will be implemented.
+
+Two examples are given in below:
+Switch from NOR to NAND boot with default frequency:
+	=> i2c dev 0
+	=> i2c mw 18 1 f9
+	=> i2c mw 18 3 f0
+	=> mw.b ffb00011 0
+	=> mw.b ffb00017 1
+	=> reset
+Switch from NAND to NOR boot with Core/CCB/DDR (800/400/667 MHz):
+	=> i2c dev 0
+	=> i2c mw 18 1 f1
+	=> i2c mw 18 3 f0
+	=> mw.b ffb00011 0
+	=> mw.b ffb00014 2
+	=> mw.b ffb00015 5
+	=> mw.b ffb00016 3
+	=> mw.b ffb00017 f
+	=> reset
+
+
+Boot Linux from network using TFTP on P1010RDB
+==============================================
+Place uImage, p1010rdb.dtb and rootfs files in the TFTP disk area.
+	=> tftp 1000000 uImage
+	=> tftp 2000000 p1010rdb.dtb
+	=> tftp 3000000 rootfs.ext2.gz.uboot.p1010rdb
+	=> bootm 1000000 3000000 2000000
+
+
+For more details, please refer to P1010RDB User Guide and access website
+www.freescale.com
diff --git a/board/freescale/p1010rdb/README.P1010RDB-PB b/board/freescale/p1010rdb/README.P1010RDB-PB
new file mode 100644
index 0000000000..c5d1419445
--- /dev/null
+++ b/board/freescale/p1010rdb/README.P1010RDB-PB
@@ -0,0 +1,188 @@
+Overview
+=========
+The P1010RDB-PB is a Freescale Reference Design Board that hosts the P1010 SoC.
+P1010RDB-PB is a variation of previous P1010RDB-PA board.
+
+The P1010 is a cost-effective, low-power, highly integrated host processor
+based on a Power Architecture e500v2 core (maximum core frequency 1GHz),that
+addresses the requirements of several routing, gateways, storage, consumer,
+and industrial applications. Applications of interest include the main CPUs and
+I/O processors in network attached storage (NAS), the voice over IP (VoIP)
+router/gateway, and wireless LAN (WLAN) and industrial controllers.
+
+The P1010RDB-PB board features are as following:
+Memory subsystem:
+	- 1G bytes unbuffered DDR3 SDRAM discrete devices (32-bit bus)
+	- 32M bytes NOR flash single-chip memory
+	- 2G bytes NAND flash memory
+	- 16M bytes SPI memory
+	- 256K bit M24256 I2C EEPROM
+	- I2C Board EEPROM 128x8 bit memory
+	- SD/MMC connector to interface with the SD memory card
+Interfaces:
+	- Three 10/100/1000 BaseT Ethernet ports (One RGMII and two SGMII)
+	- PCIe 2.0: two x1 mini-PCIe slots
+	- SATA 2.0: two SATA interfaces
+	- USB 2.0: one USB interface
+	- FlexCAN: two FlexCAN interfaces (revision 2.0B)
+	- UART: one USB-to-Serial interface
+	- TDM: 2 FXS ports connected via an external SLIC to the TDM interface.
+	       1 FXO port connected via a relay to FXS for switchover to POTS
+
+Board connectors:
+	- Mini-ITX power supply connector
+	- JTAG/COP for debugging
+
+POR: support critical POR setting changed via switch on board
+PCB: 6-layer routing (4-layer signals, 2-layer power and ground)
+
+Physical Memory Map on P1010RDB
+===============================
+Address Start   Address End   Memory type	Attributes
+0x0000_0000	0x3fff_ffff   DDR		1G Cacheable
+0xa000_0000	0xdfff_ffff   PCI Express Mem	1G non-cacheable
+0xee00_0000	0xefff_ffff   NOR Flash		32M non-cacheable
+0xffc2_0000	0xffc5_ffff   PCI IO range	256K non-cacheable
+0xffa0_0000	0xffaf_ffff   NAND Flash	1M cacheable
+0xffb0_0000	0xffbf_ffff   Board CPLD	1M non-cacheable
+0xffd0_0000	0xffd0_3fff   L1 for Stack	16K Cacheable TLB0
+0xffe0_0000	0xffef_ffff   CCSR		1M non-cacheable
+
+
+Serial Port Configuration on P1010RDB
+=====================================
+Configure the serial port of the attached computer with the following values:
+	-Data rate: 115200 bps
+	-Number of data bits: 8
+	-Parity: None
+	-Number of Stop bits: 1
+	-Flow Control: Hardware/None
+
+
+P1010RDB-PB default DIP-switch settings
+=======================================
+SW1[1:8]= 10101010
+SW2[1:8]= 11011000
+SW3[1:8]= 10010000
+SW4[1:4]= 1010
+SW5[1:8]= 11111010
+
+
+P1010RDB-PB boot mode settings via DIP-switch
+=============================================
+SW4[1:4]= 1111 and SW3[3:4]= 00 for 16bit NOR boot
+SW4[1:4]= 1010 and SW3[3:4]= 01 for 8bit NAND boot
+SW4[1:4]= 0110 and SW3[3:4]= 00 for SPI boot
+SW4[1:4]= 0111 and SW3[3:4]= 10 for SD boot
+Note: 1 stands for 'on', 0 stands for 'off'
+
+
+Switch P1010RDB-PB boot mode via software without setting DIP-switch
+====================================================================
+=> run boot_bank0    (boot from NOR bank0)
+=> run boot_bank1    (boot from NOR bank1)
+=> run boot_nand     (boot from NAND flash)
+=> run boot_spi      (boot from SPI flash)
+=> run boot_sd       (boot from SD card)
+
+
+Frequency combination support on P1010RDB-PB
+=============================================
+SW1[4:7] SW5[1] SW5[5:8] SW2[2] Core(MHz) Platform(MHz) DDR(MT/s)
+0101      1      1010     0       800       400		800
+1001      1      1010     0       800       400		667
+1010      1      1100     0       667       333		667
+1000      0      1010     0       533       266		667
+0101      1      1010     1       1000      400		800
+1001      1      1010     1       1000      400		667
+
+
+Setting of pin mux
+==================
+Since pins multiplexing, TDM and CAN are muxed with SPI flash.
+SDHC is muxed with IFC. IFC and SPI flash are enabled by default.
+
+To enable TDM:
+=> setenv hwconfig fsl_p1010mux:tdm_can=tdm
+=> save;reset
+
+To enable FlexCAN:
+=> setenv hwconfig fsl_p1010mux:tdm_can=can
+=> save;reset
+
+To enable SDHC in case of NOR/NAND/SPI boot
+   a) For temporary use case in runtime without reboot system
+      run 'mux sdhc' in u-boot to validate SDHC with invalidating IFC.
+
+   b) For long-term use case
+      set 'esdhc' in hwconfig and save it.
+
+To enable IFC in case of SD boot
+   a) For temporary use case in runtime without reboot system
+      run 'mux ifc' in u-boot to validate IFC with invalidating SDHC.
+
+   b) For long-term use case
+      set 'ifc' in hwconfig and save it.
+
+
+Build images for different boot mode
+====================================
+First setup cross compile environment on build host
+   $ export ARCH=powerpc
+   $ export CROSS_COMPILE=<your-compiler-path>/powerpc-linux-gnu-
+
+1. For NOR boot
+   $ make P1010RDB-PB_NOR
+
+2. For NAND boot
+   $ make P1010RDB-PB_NAND
+
+3. For SPI boot
+   $ make P1010RDB-PB_SPIFLASH
+
+4. For SD boot
+   $ make P1010RDB-PB_SDCARD
+
+
+Steps to program images to flash for different boot mode
+========================================================
+1. NOR boot
+   => tftp 1000000 u-boot.bin
+   For bank0
+   => pro off all;era eff40000 efffffff;cp.b 1000000 eff40000 $filesize
+   set SW1[8]=0, SW4[1:4]= 1111 and SW3[3:4]= 00, then power on the board
+
+   For bank1
+   => pro off all;era eef40000 eeffffff;cp.b 1000000 eef40000 $filesize
+   set SW1[8]=1, SW4[1:4]= 1111 and SW3[3:4]= 00, then power on the board
+
+2. NAND boot
+   => tftp 1000000 u-boot-nand.bin
+   => nand erase 0 $filesize; nand write $loadaddr 0 $filesize
+   Set SW4[1:4]= 1010 and SW3[3:4]= 01, then power on the board
+
+3. SPI boot
+   1)  cat p1010rdb-config-header.bin u-boot.bin > u-boot-spi-combined.bin
+   2)  =>  tftp 1000000 u-boot-spi-combined.bin
+   3)  =>  sf probe 0; sf erase 0 100000; sf write 1000000 0 100000
+   set SW4[1:4]= 0110 and SW3[3:4]= 00, then power on the board
+
+4. SD boot
+   1)	cat p1010rdb-config-header.bin u-boot.bin > u-boot-sd-combined.bin
+   2)	=> tftp 1000000 u-boot-sd-combined.bin
+   3)	=> mux sdhc
+   4)	=> mmc write 1000000 0 1050
+   set SW4[1:4]= 0111 and SW3[3:4]= 10, then power on the board
+
+
+Boot Linux from network using TFTP on P1010RDB-PB
+=================================================
+Place uImage, p1010rdb.dtb and rootfs files in the TFTP download path.
+	=> tftp 1000000 uImage
+	=> tftp 2000000 p1010rdb.dtb
+	=> tftp 3000000 rootfs.ext2.gz.uboot.p1010rdb
+	=> bootm 1000000 3000000 2000000
+
+
+For more details, please refer to P1010RDB-PB User Guide and access website
+www.freescale.com and Freescale QorIQ SDK Infocenter document.
diff --git a/board/freescale/p1010rdb/ddr.c b/board/freescale/p1010rdb/ddr.c
index 681f052e41..b0d95ea006 100644
--- a/board/freescale/p1010rdb/ddr.c
+++ b/board/freescale/p1010rdb/ddr.c
@@ -8,8 +8,8 @@
 #include <asm/mmu.h>
 #include <asm/immap_85xx.h>
 #include <asm/processor.h>
-#include <asm/fsl_ddr_sdram.h>
-#include <asm/fsl_ddr_dimm_params.h>
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr_dimm_params.h>
 #include <asm/io.h>
 #include <asm/fsl_law.h>
 
@@ -172,20 +172,20 @@ dimm_params_t ddr_raw_timing = {
 	.edc_config = 0,
 	.burst_lengths_bitmask = 0x0c,
 
-	.tCKmin_X_ps = 1875,
-	.caslat_X = 0x1e << 4,	/* 5,6,7,8 */
-	.tAA_ps = 13125,
-	.tWR_ps = 15000,
-	.tRCD_ps = 13125,
-	.tRRD_ps = 7500,
-	.tRP_ps = 13125,
-	.tRAS_ps = 37500,
-	.tRC_ps = 50625,
-	.tRFC_ps = 160000,
-	.tWTR_ps = 7500,
-	.tRTP_ps = 7500,
+	.tckmin_x_ps = 1875,
+	.caslat_x = 0x1e << 4,	/* 5,6,7,8 */
+	.taa_ps = 13125,
+	.twr_ps = 15000,
+	.trcd_ps = 13125,
+	.trrd_ps = 7500,
+	.trp_ps = 13125,
+	.tras_ps = 37500,
+	.trc_ps = 50625,
+	.trfc_ps = 160000,
+	.twtr_ps = 7500,
+	.trtp_ps = 7500,
 	.refresh_rate_ps = 7800000,
-	.tFAW_ps = 37500,
+	.tfaw_ps = 37500,
 };
 
 int fsl_ddr_get_dimm_params(dimm_params_t *pdimm,
diff --git a/board/freescale/p1010rdb/law.c b/board/freescale/p1010rdb/law.c
index 004512725f..ed41a056c5 100644
--- a/board/freescale/p1010rdb/law.c
+++ b/board/freescale/p1010rdb/law.c
@@ -9,11 +9,9 @@
 #include <asm/mmu.h>
 
 struct law_entry law_table[] = {
-#ifndef CONFIG_SDCARD
 	SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_IFC),
 	SET_LAW(CONFIG_SYS_CPLD_BASE_PHYS, LAW_SIZE_128K, LAW_TRGT_IF_IFC),
 	SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_IFC),
-#endif
 };
 
 int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/board/freescale/p1010rdb/p1010rdb.c b/board/freescale/p1010rdb/p1010rdb.c
index 06aa8009b5..62caf676c6 100644
--- a/board/freescale/p1010rdb/p1010rdb.c
+++ b/board/freescale/p1010rdb/p1010rdb.c
@@ -19,12 +19,10 @@
 #include <netdev.h>
 #include <pci.h>
 #include <asm/fsl_serdes.h>
-#include <asm/fsl_ifc.h>
+#include <fsl_ifc.h>
 #include <asm/fsl_pci.h>
-
-#ifndef CONFIG_SDCARD
 #include <hwconfig.h>
-#endif
+#include <i2c.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -33,10 +31,30 @@ DECLARE_GLOBAL_DATA_PTR;
 #define MUX_CPLD_TDM			0x01
 #define MUX_CPLD_SPICS0_FLASH		0x00
 #define MUX_CPLD_SPICS0_SLIC		0x02
+#define PMUXCR1_IFC_MASK       0x00ffff00
+#define PMUXCR1_SDHC_MASK      0x00fff000
+#define PMUXCR1_SDHC_ENABLE    0x00555000
+
+enum {
+	MUX_TYPE_IFC,
+	MUX_TYPE_SDHC,
+	MUX_TYPE_SPIFLASH,
+	MUX_TYPE_TDM,
+	MUX_TYPE_CAN,
+	MUX_TYPE_CS0_NOR,
+	MUX_TYPE_CS0_NAND,
+};
+
+enum {
+	I2C_READ_BANK,
+	I2C_READ_PCB_VER,
+};
+
+static uint sd_ifc_mux;
 
-#ifndef CONFIG_SDCARD
 struct cpld_data {
 	u8 cpld_ver; /* cpld revision */
+#if defined(CONFIG_P1010RDB_PA)
 	u8 pcba_ver; /* pcb revision number */
 	u8 twindie_ddr3;
 	u8 res1[6];
@@ -51,53 +69,18 @@ struct cpld_data {
 	u8 por1; /* POR Options */
 	u8 por2; /* POR Options */
 	u8 por3; /* POR Options */
-};
-
-void cpld_show(void)
-{
-	struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
-
-	printf("CPLD: V%x.%x PCBA: V%x.0\n",
-		in_8(&cpld_data->cpld_ver) & 0xF0,
-		in_8(&cpld_data->cpld_ver) & 0x0F,
-		in_8(&cpld_data->pcba_ver) & 0x0F);
-
-#ifdef CONFIG_DEBUG
-	printf("twindie_ddr =%x\n",
-		in_8(&cpld_data->twindie_ddr3));
-	printf("bank_sel =%x\n",
-		in_8(&cpld_data->bank_sel));
-	printf("usb2_sel =%x\n",
-		in_8(&cpld_data->usb2_sel));
-	printf("porsw_sel =%x\n",
-		in_8(&cpld_data->porsw_sel));
-	printf("tdm_can_sel =%x\n",
-		in_8(&cpld_data->tdm_can_sel));
-	printf("tdm_can_sel =%x\n",
-		in_8(&cpld_data->tdm_can_sel));
-	printf("spi_cs0_sel =%x\n",
-		in_8(&cpld_data->spi_cs0_sel));
-	printf("bcsr0 =%x\n",
-		in_8(&cpld_data->bcsr0));
-	printf("bcsr1 =%x\n",
-		in_8(&cpld_data->bcsr1));
-	printf("bcsr2 =%x\n",
-		in_8(&cpld_data->bcsr2));
-	printf("bcsr3 =%x\n",
-		in_8(&cpld_data->bcsr3));
-#endif
-}
+#elif defined(CONFIG_P1010RDB_PB)
+	u8 rom_loc;
 #endif
+};
 
 int board_early_init_f(void)
 {
 	ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR);
-#ifndef CONFIG_SDCARD
 	struct fsl_ifc *ifc = (void *)CONFIG_SYS_IFC_ADDR;
 
 	/* Clock configuration to access CPLD using IFC(GPCM) */
 	setbits_be32(&ifc->ifc_gcr, 1 << IFC_GCR_TBCTL_TRN_TIME_SHIFT);
-#endif
 	/*
 	* Reset PCIe slots via GPIO4
 	*/
@@ -109,7 +92,6 @@ int board_early_init_f(void)
 
 int board_early_init_r(void)
 {
-#ifndef CONFIG_SDCARD
 	const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
 	const u8 flash_esel = find_tlb_idx((void *)flashbase, 1);
 
@@ -133,7 +115,6 @@ int board_early_init_r(void)
 			CONFIG_SYS_FLASH_BASE_PHYS + 0x1000000,
 			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 			0, flash_esel+1, BOOKE_PAGESZ_16M, 1);
-#endif
 	return 0;
 }
 
@@ -144,13 +125,199 @@ void pci_init_board(void)
 }
 #endif /* ifdef CONFIG_PCI */
 
+int config_board_mux(int ctrl_type)
+{
+	ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+	u8 tmp;
+
+#if defined(CONFIG_P1010RDB_PA)
+	struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
+
+	switch (ctrl_type) {
+	case MUX_TYPE_IFC:
+		i2c_set_bus_num(I2C_PCA9557_BUS_NUM);
+		tmp = 0xf0;
+		i2c_write(I2C_PCA9557_ADDR1, 3, 1, &tmp, 1);
+		tmp = 0x01;
+		i2c_write(I2C_PCA9557_ADDR1, 1, 1, &tmp, 1);
+		sd_ifc_mux = MUX_TYPE_IFC;
+		clrbits_be32(&gur->pmuxcr, PMUXCR1_IFC_MASK);
+		break;
+	case MUX_TYPE_SDHC:
+		i2c_set_bus_num(I2C_PCA9557_BUS_NUM);
+		tmp = 0xf0;
+		i2c_write(I2C_PCA9557_ADDR1, 3, 1, &tmp, 1);
+		tmp = 0x05;
+		i2c_write(I2C_PCA9557_ADDR1, 1, 1, &tmp, 1);
+		sd_ifc_mux = MUX_TYPE_SDHC;
+		clrsetbits_be32(&gur->pmuxcr, PMUXCR1_SDHC_MASK,
+				PMUXCR1_SDHC_ENABLE);
+		break;
+	case MUX_TYPE_SPIFLASH:
+		out_8(&cpld_data->spi_cs0_sel, MUX_CPLD_SPICS0_FLASH);
+		break;
+	case MUX_TYPE_TDM:
+		out_8(&cpld_data->tdm_can_sel, MUX_CPLD_TDM);
+		out_8(&cpld_data->spi_cs0_sel, MUX_CPLD_SPICS0_SLIC);
+		break;
+	case MUX_TYPE_CAN:
+		out_8(&cpld_data->tdm_can_sel, MUX_CPLD_CAN_UART);
+		break;
+	default:
+		break;
+	}
+#elif defined(CONFIG_P1010RDB_PB)
+	uint orig_bus = i2c_get_bus_num();
+	i2c_set_bus_num(I2C_PCA9557_BUS_NUM);
+
+	switch (ctrl_type) {
+	case MUX_TYPE_IFC:
+		i2c_read(I2C_PCA9557_ADDR2, 0, 1, &tmp, 1);
+		clrbits_8(&tmp, 0x04);
+		i2c_write(I2C_PCA9557_ADDR2, 1, 1, &tmp, 1);
+		i2c_read(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
+		clrbits_8(&tmp, 0x04);
+		i2c_write(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
+		sd_ifc_mux = MUX_TYPE_IFC;
+		clrbits_be32(&gur->pmuxcr, PMUXCR1_IFC_MASK);
+		break;
+	case MUX_TYPE_SDHC:
+		i2c_read(I2C_PCA9557_ADDR2, 0, 1, &tmp, 1);
+		setbits_8(&tmp, 0x04);
+		i2c_write(I2C_PCA9557_ADDR2, 1, 1, &tmp, 1);
+		i2c_read(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
+		clrbits_8(&tmp, 0x04);
+		i2c_write(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
+		sd_ifc_mux = MUX_TYPE_SDHC;
+		clrsetbits_be32(&gur->pmuxcr, PMUXCR1_SDHC_MASK,
+				PMUXCR1_SDHC_ENABLE);
+		break;
+	case MUX_TYPE_SPIFLASH:
+		i2c_read(I2C_PCA9557_ADDR2, 0, 1, &tmp, 1);
+		clrbits_8(&tmp, 0x80);
+		i2c_write(I2C_PCA9557_ADDR2, 1, 1, &tmp, 1);
+		i2c_read(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
+		clrbits_8(&tmp, 0x80);
+		i2c_write(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
+		break;
+	case MUX_TYPE_TDM:
+		i2c_read(I2C_PCA9557_ADDR2, 0, 1, &tmp, 1);
+		setbits_8(&tmp, 0x82);
+		i2c_write(I2C_PCA9557_ADDR2, 1, 1, &tmp, 1);
+		i2c_read(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
+		clrbits_8(&tmp, 0x82);
+		i2c_write(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
+		break;
+	case MUX_TYPE_CAN:
+		i2c_read(I2C_PCA9557_ADDR2, 0, 1, &tmp, 1);
+		clrbits_8(&tmp, 0x02);
+		i2c_write(I2C_PCA9557_ADDR2, 1, 1, &tmp, 1);
+		i2c_read(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
+		clrbits_8(&tmp, 0x02);
+		i2c_write(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
+		break;
+	case MUX_TYPE_CS0_NOR:
+		i2c_read(I2C_PCA9557_ADDR2, 0, 1, &tmp, 1);
+		clrbits_8(&tmp, 0x08);
+		i2c_write(I2C_PCA9557_ADDR2, 1, 1, &tmp, 1);
+		i2c_read(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
+		clrbits_8(&tmp, 0x08);
+		i2c_write(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
+		break;
+	case MUX_TYPE_CS0_NAND:
+		i2c_read(I2C_PCA9557_ADDR2, 0, 1, &tmp, 1);
+		setbits_8(&tmp, 0x08);
+		i2c_write(I2C_PCA9557_ADDR2, 1, 1, &tmp, 1);
+		i2c_read(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
+		clrbits_8(&tmp, 0x08);
+		i2c_write(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
+		break;
+	default:
+		break;
+	}
+	i2c_set_bus_num(orig_bus);
+#endif
+	return 0;
+}
+
+#ifdef CONFIG_P1010RDB_PB
+int i2c_pca9557_read(int type)
+{
+	u8 val;
+
+	i2c_set_bus_num(I2C_PCA9557_BUS_NUM);
+	i2c_read(I2C_PCA9557_ADDR2, 0, 1, &val, 1);
+
+	switch (type) {
+	case I2C_READ_BANK:
+		val = (val & 0x10) >> 4;
+		break;
+	case I2C_READ_PCB_VER:
+		val = ((val & 0x60) >> 5) + 1;
+		break;
+	default:
+		break;
+	}
+
+	return val;
+}
+#endif
+
 int checkboard(void)
 {
 	struct cpu_type *cpu;
+	struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
+	u8 val;
 
 	cpu = gd->arch.cpu;
-	printf("Board: %sRDB\n", cpu->name);
+#if defined(CONFIG_P1010RDB_PA)
+	printf("Board: %sRDB-PA, ", cpu->name);
+#elif defined(CONFIG_P1010RDB_PB)
+	printf("Board: %sRDB-PB, ", cpu->name);
+	i2c_set_bus_num(I2C_PCA9557_BUS_NUM);
+	i2c_init(CONFIG_SYS_FSL_I2C_SPEED, CONFIG_SYS_FSL_I2C_SLAVE);
+	val = 0x0;  /* no polarity inversion */
+	i2c_write(I2C_PCA9557_ADDR2, 2, 1, &val, 1);
+#endif
 
+#ifdef CONFIG_SDCARD
+	/* switch to IFC to read info from CPLD */
+	config_board_mux(MUX_TYPE_IFC);
+#endif
+
+#if defined(CONFIG_P1010RDB_PA)
+	val = (in_8(&cpld_data->pcba_ver) & 0xf);
+	printf("PCB: v%x.0\n", val);
+#elif defined(CONFIG_P1010RDB_PB)
+	val = in_8(&cpld_data->cpld_ver);
+	printf("CPLD: v%x.%x, ", val >> 4, val & 0xf);
+	printf("PCB: v%x.0, ", i2c_pca9557_read(I2C_READ_PCB_VER));
+	val = in_8(&cpld_data->rom_loc) & 0xf;
+	puts("Boot from: ");
+	switch (val) {
+	case 0xf:
+		config_board_mux(MUX_TYPE_CS0_NOR);
+		printf("NOR vBank%d\n", i2c_pca9557_read(I2C_READ_BANK));
+		break;
+	case 0xe:
+		puts("SDHC\n");
+		val = 0x60; /* set pca9557 pin input/output */
+		i2c_write(I2C_PCA9557_ADDR2, 3, 1, &val, 1);
+		break;
+	case 0x5:
+		config_board_mux(MUX_TYPE_IFC);
+		config_board_mux(MUX_TYPE_CS0_NAND);
+		puts("NAND\n");
+		break;
+	case 0x6:
+		config_board_mux(MUX_TYPE_IFC);
+		puts("SPI\n");
+		break;
+	default:
+		puts("unknown\n");
+		break;
+	}
+#endif
 	return 0;
 }
 
@@ -246,6 +413,16 @@ void fdt_del_sdhc(void *blob)
 	}
 }
 
+void fdt_del_ifc(void *blob)
+{
+	int nodeoff = 0;
+
+	while ((nodeoff = fdt_node_offset_by_compatible(blob, 0,
+				"fsl,ifc")) >= 0) {
+		fdt_del_node(blob, nodeoff);
+	}
+}
+
 void fdt_disable_uart1(void *blob)
 {
 	int nodeoff;
@@ -289,9 +466,13 @@ void ft_board_setup(void *blob, bd_t *bd)
 		fdt_del_flexcan(blob);
 		fdt_del_node_and_alias(blob, "ethernet2");
 	}
-#ifndef CONFIG_SDCARD
-	/* disable sdhc due to sdhc bug */
-	fdt_del_sdhc(blob);
+
+	/* Delete IFC node as IFC pins are multiplexing with SDHC */
+	if (sd_ifc_mux != MUX_TYPE_IFC)
+		fdt_del_ifc(blob);
+	else
+		fdt_del_sdhc(blob);
+
 	if (hwconfig_subarg_cmp("fsl_p1010mux", "tdm_can", "can")) {
 		fdt_del_tdm(blob);
 		fdt_del_spi_slic(blob);
@@ -309,14 +490,27 @@ void ft_board_setup(void *blob, bd_t *bd)
 		fdt_del_flexcan(blob);
 		fdt_disable_uart1(blob);
 	}
+}
 #endif
+
+#ifdef CONFIG_SDCARD
+int board_mmc_init(bd_t *bis)
+{
+	config_board_mux(MUX_TYPE_SDHC);
+		return -1;
+}
+#else
+void board_reset(void)
+{
+	/* mux to IFC to enable CPLD for reset */
+	if (sd_ifc_mux != MUX_TYPE_IFC)
+		config_board_mux(MUX_TYPE_IFC);
 }
 #endif
 
-#ifndef CONFIG_SDCARD
+
 int misc_init_r(void)
 {
-	struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
 	ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 
 	if (hwconfig_subarg_cmp("fsl_p1010mux", "tdm_can", "can")) {
@@ -324,7 +518,7 @@ int misc_init_r(void)
 				MPC85xx_PMUXCR_CAN1_UART |
 				MPC85xx_PMUXCR_CAN2_TDM |
 				MPC85xx_PMUXCR_CAN2_UART);
-		out_8(&cpld_data->tdm_can_sel, MUX_CPLD_CAN_UART);
+		config_board_mux(MUX_TYPE_CAN);
 	} else if (hwconfig_subarg_cmp("fsl_p1010mux", "tdm_can", "tdm")) {
 		clrbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_CAN2_UART |
 				MPC85xx_PMUXCR_CAN1_UART);
@@ -332,13 +526,39 @@ int misc_init_r(void)
 				MPC85xx_PMUXCR_CAN1_TDM);
 		clrbits_be32(&gur->pmuxcr2, MPC85xx_PMUXCR2_UART_GPIO);
 		setbits_be32(&gur->pmuxcr2, MPC85xx_PMUXCR2_UART_TDM);
-		out_8(&cpld_data->tdm_can_sel, MUX_CPLD_TDM);
-		out_8(&cpld_data->spi_cs0_sel, MUX_CPLD_SPICS0_SLIC);
+		config_board_mux(MUX_TYPE_TDM);
 	} else {
 		/* defaultly spi_cs_sel to flash */
-		out_8(&cpld_data->spi_cs0_sel, MUX_CPLD_SPICS0_FLASH);
+		config_board_mux(MUX_TYPE_SPIFLASH);
 	}
 
+	if (hwconfig("esdhc"))
+		config_board_mux(MUX_TYPE_SDHC);
+	else if (hwconfig("ifc"))
+		config_board_mux(MUX_TYPE_IFC);
+
+#ifdef CONFIG_P1010RDB_PB
+	setbits_be32(&gur->pmuxcr2, MPC85xx_PMUXCR2_GPIO01_DRVVBUS);
+#endif
 	return 0;
 }
-#endif
+
+static int pin_mux_cmd(cmd_tbl_t *cmdtp, int flag, int argc,
+				char * const argv[])
+{
+	if (argc < 2)
+		return CMD_RET_USAGE;
+	if (strcmp(argv[1], "ifc") == 0)
+		config_board_mux(MUX_TYPE_IFC);
+	else if (strcmp(argv[1], "sdhc") == 0)
+		config_board_mux(MUX_TYPE_SDHC);
+	else
+		return CMD_RET_USAGE;
+	return 0;
+}
+
+U_BOOT_CMD(
+	mux, 2, 0, pin_mux_cmd,
+	"configure multiplexing pin for IFC/SDHC bus in runtime",
+	"bus_type (e.g. mux sdhc)"
+);
diff --git a/board/freescale/p1010rdb/spl.c b/board/freescale/p1010rdb/spl.c
new file mode 100644
index 0000000000..11bd9cfccc
--- /dev/null
+++ b/board/freescale/p1010rdb/spl.c
@@ -0,0 +1,108 @@
+/* Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#include <common.h>
+#include <ns16550.h>
+#include <malloc.h>
+#include <mmc.h>
+#include <nand.h>
+#include <i2c.h>
+#include <fsl_esdhc.h>
+#include <spi_flash.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+phys_size_t get_effective_memsize(void)
+{
+	return CONFIG_SYS_L2_SIZE;
+}
+
+void board_init_f(ulong bootflag)
+{
+	u32 plat_ratio;
+	ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
+	struct fsl_ifc *ifc = (void *)CONFIG_SYS_IFC_ADDR;
+
+	console_init_f();
+
+	/* Clock configuration to access CPLD using IFC(GPCM) */
+	setbits_be32(&ifc->ifc_gcr, 1 << IFC_GCR_TBCTL_TRN_TIME_SHIFT);
+
+#ifdef CONFIG_P1010RDB_PB
+	setbits_be32(&gur->pmuxcr2, MPC85xx_PMUXCR2_GPIO01_DRVVBUS);
+#endif
+
+	/* initialize selected port with appropriate baud rate */
+	plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO;
+	plat_ratio >>= 1;
+	gd->bus_clk = CONFIG_SYS_CLK_FREQ * plat_ratio;
+
+	NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
+		     gd->bus_clk / 16 / CONFIG_BAUDRATE);
+
+#ifdef CONFIG_SPL_MMC_BOOT
+	puts("\nSD boot...\n");
+#elif defined(CONFIG_SPL_SPI_BOOT)
+	puts("\nSPI Flash boot...\n");
+#endif
+	/* copy code to RAM and jump to it - this should not return */
+	/* NOTE - code has to be copied out of NAND buffer before
+	 * other blocks can be read.
+	*/
+	relocate_code(CONFIG_SPL_RELOC_STACK, 0, CONFIG_SPL_RELOC_TEXT_BASE);
+}
+
+void board_init_r(gd_t *gd, ulong dest_addr)
+{
+	/* Pointer is writable since we allocated a register for it */
+	gd = (gd_t *)CONFIG_SPL_GD_ADDR;
+	bd_t *bd;
+
+	memset(gd, 0, sizeof(gd_t));
+	bd = (bd_t *)(CONFIG_SPL_GD_ADDR + sizeof(gd_t));
+	memset(bd, 0, sizeof(bd_t));
+	gd->bd = bd;
+	bd->bi_memstart = CONFIG_SYS_INIT_L2_ADDR;
+	bd->bi_memsize = CONFIG_SYS_L2_SIZE;
+
+	probecpu();
+	get_clocks();
+	mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR,
+			CONFIG_SPL_RELOC_MALLOC_SIZE);
+
+#ifndef CONFIG_SPL_NAND_BOOT
+	env_init();
+#endif
+#ifdef CONFIG_SPL_MMC_BOOT
+	mmc_initialize(bd);
+#endif
+
+	/* relocate environment function pointers etc. */
+#ifdef CONFIG_SPL_NAND_BOOT
+	nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
+			    (uchar *)CONFIG_ENV_ADDR);
+			    gd->env_addr  = (ulong)(CONFIG_ENV_ADDR);
+	gd->env_valid = 1;
+#else
+	env_relocate();
+#endif
+
+	i2c_init_all();
+
+	gd->ram_size = initdram(0);
+#ifdef CONFIG_SPL_NAND_BOOT
+	puts("\nTertiary program loader running in sram...");
+#else
+	puts("\nSecond program loader running in sram...");
+#endif
+
+#ifdef CONFIG_SPL_MMC_BOOT
+	mmc_boot();
+#elif defined(CONFIG_SPL_SPI_BOOT)
+	spi_boot();
+#elif defined(CONFIG_SPL_NAND_BOOT)
+	nand_boot();
+#endif
+}
diff --git a/board/freescale/p1010rdb/spl_minimal.c b/board/freescale/p1010rdb/spl_minimal.c
index d0e712eb30..607957003d 100644
--- a/board/freescale/p1010rdb/spl_minimal.c
+++ b/board/freescale/p1010rdb/spl_minimal.c
@@ -10,83 +10,22 @@
 #include <nand.h>
 #include <asm/mmu.h>
 #include <asm/immap_85xx.h>
-#include <asm/fsl_ddr_sdram.h>
+#include <fsl_ddr_sdram.h>
 #include <asm/fsl_law.h>
 #include <asm/global_data.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
-
-void sdram_init(void)
-{
-	ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_MPC8xxx_DDR_ADDR;
-	ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
-	u32 ddr_ratio;
-	unsigned long ddr_freq_mhz;
-
-	ddr_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO;
-	ddr_ratio = ddr_ratio >> MPC85xx_PORPLLSR_DDR_RATIO_SHIFT;
-	ddr_freq_mhz = (CONFIG_SYS_CLK_FREQ * ddr_ratio) / 1000000;
-
-	/* mask off E bit */
-	u32 svr = SVR_SOC_VER(mfspr(SPRN_SVR));
-
-	__raw_writel(CONFIG_SYS_DDR_CONTROL | SDRAM_CFG_32_BE, &ddr->sdram_cfg);
-	__raw_writel(CONFIG_SYS_DDR_CS0_BNDS, &ddr->cs0_bnds);
-	__raw_writel(CONFIG_SYS_DDR_CS0_CONFIG, &ddr->cs0_config);
-	__raw_writel(CONFIG_SYS_DDR_CONTROL_2, &ddr->sdram_cfg_2);
-	__raw_writel(CONFIG_SYS_DDR_DATA_INIT, &ddr->sdram_data_init);
-
-	if (ddr_freq_mhz < 700) {
-		__raw_writel(CONFIG_SYS_DDR_TIMING_3_667, &ddr->timing_cfg_3);
-		__raw_writel(CONFIG_SYS_DDR_TIMING_0_667, &ddr->timing_cfg_0);
-		__raw_writel(CONFIG_SYS_DDR_TIMING_1_667, &ddr->timing_cfg_1);
-		__raw_writel(CONFIG_SYS_DDR_TIMING_2_667, &ddr->timing_cfg_2);
-		__raw_writel(CONFIG_SYS_DDR_MODE_1_667, &ddr->sdram_mode);
-		__raw_writel(CONFIG_SYS_DDR_MODE_2_667, &ddr->sdram_mode_2);
-		__raw_writel(CONFIG_SYS_DDR_INTERVAL_667, &ddr->sdram_interval);
-		__raw_writel(CONFIG_SYS_DDR_CLK_CTRL_667, &ddr->sdram_clk_cntl);
-		__raw_writel(CONFIG_SYS_DDR_WRLVL_CONTROL_667, &ddr->ddr_wrlvl_cntl);
-	} else {
-		__raw_writel(CONFIG_SYS_DDR_TIMING_3_800, &ddr->timing_cfg_3);
-		__raw_writel(CONFIG_SYS_DDR_TIMING_0_800, &ddr->timing_cfg_0);
-		__raw_writel(CONFIG_SYS_DDR_TIMING_1_800, &ddr->timing_cfg_1);
-		__raw_writel(CONFIG_SYS_DDR_TIMING_2_800, &ddr->timing_cfg_2);
-		__raw_writel(CONFIG_SYS_DDR_MODE_1_800, &ddr->sdram_mode);
-		__raw_writel(CONFIG_SYS_DDR_MODE_2_800, &ddr->sdram_mode_2);
-		__raw_writel(CONFIG_SYS_DDR_INTERVAL_800, &ddr->sdram_interval);
-		__raw_writel(CONFIG_SYS_DDR_CLK_CTRL_800, &ddr->sdram_clk_cntl);
-		__raw_writel(CONFIG_SYS_DDR_WRLVL_CONTROL_800, &ddr->ddr_wrlvl_cntl);
-	}
-
-	__raw_writel(CONFIG_SYS_DDR_TIMING_4, &ddr->timing_cfg_4);
-	__raw_writel(CONFIG_SYS_DDR_TIMING_5, &ddr->timing_cfg_5);
-	__raw_writel(CONFIG_SYS_DDR_ZQ_CONTROL, &ddr->ddr_zq_cntl);
-
-	/* P1014 and it's derivatives support max 16bit DDR width */
-	if (svr == SVR_P1014) {
-		__raw_writel(ddr->sdram_cfg & ~SDRAM_CFG_DBW_MASK, &ddr->sdram_cfg);
-		__raw_writel(ddr->sdram_cfg | SDRAM_CFG_16_BE, &ddr->sdram_cfg);
-		/* For CS0_BNDS we divide the start and end address by 2, so we can just
-		 * shift the entire register to achieve the desired result and the mask
-		 * the value so we don't write reserved fields */
-		__raw_writel((CONFIG_SYS_DDR_CS0_BNDS >> 1) & 0x0fff0fff, &ddr->cs0_bnds);
-	}
-
-	asm volatile("sync;isync");
-	udelay(500);
-
-	/* Let the controller go */
-	out_be32(&ddr->sdram_cfg, in_be32(&ddr->sdram_cfg) | SDRAM_CFG_MEM_EN);
-
-	set_next_law(CONFIG_SYS_NAND_DDR_LAW, LAW_SIZE_1G, LAW_TRGT_IF_DDR_1);
-}
-
 void board_init_f(ulong bootflag)
 {
 	u32 plat_ratio;
 	ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
 
+#if defined(CONFIG_SYS_NAND_BR_PRELIM) && defined(CONFIG_SYS_NAND_OR_PRELIM)
+	set_lbc_br(0, CONFIG_SYS_NAND_BR_PRELIM);
+	set_lbc_or(0, CONFIG_SYS_NAND_OR_PRELIM);
+#endif
+
 	/* initialize selected port with appropriate baud rate */
 	plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO;
 	plat_ratio >>= 1;
@@ -97,9 +36,6 @@ void board_init_f(ulong bootflag)
 
 	puts("\nNAND boot... ");
 
-	/* Initialize the DDR3 */
-	sdram_init();
-
 	/* copy code to RAM and jump to it - this should not return */
 	/* NOTE - code has to be copied out of NAND buffer before
 	 * other blocks can be read.
@@ -110,6 +46,7 @@ void board_init_f(ulong bootflag)
 
 void board_init_r(gd_t *gd, ulong dest_addr)
 {
+	puts("\nSecond program loader running in sram...");
 	nand_boot();
 }
 
diff --git a/board/freescale/p1010rdb/tlb.c b/board/freescale/p1010rdb/tlb.c
index 77a80435a2..af40f979d3 100644
--- a/board/freescale/p1010rdb/tlb.c
+++ b/board/freescale/p1010rdb/tlb.c
@@ -30,7 +30,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
 	SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 0, BOOKE_PAGESZ_4K, 1),
-#ifdef CONFIG_SPL_NAND_MINIMAL
+#ifdef CONFIG_SPL_NAND_BOOT
 	SET_TLB_ENTRY(1, 0xffffe000, 0xffffe000,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 10, BOOKE_PAGESZ_4K, 1),
@@ -42,7 +42,6 @@ struct fsl_e_tlb_entry tlb_table[] = {
 			0, 1, BOOKE_PAGESZ_1M, 1),
 
 #ifndef CONFIG_SPL_BUILD
-#ifndef CONFIG_SDCARD
 	SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
 			MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
 			0, 2, BOOKE_PAGESZ_16M, 1),
@@ -51,7 +50,6 @@ struct fsl_e_tlb_entry tlb_table[] = {
 			CONFIG_SYS_FLASH_BASE_PHYS + 0x1000000,
 			MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
 			0, 3, BOOKE_PAGESZ_16M, 1),
-#endif
 
 #ifdef CONFIG_PCI
 	/* *I*G* - PCI */
@@ -66,7 +64,6 @@ struct fsl_e_tlb_entry tlb_table[] = {
 #endif
 #endif
 
-#ifndef CONFIG_SDCARD
 	/* *I*G - Board CPLD  */
 	SET_TLB_ENTRY(1, CONFIG_SYS_CPLD_BASE, CONFIG_SYS_CPLD_BASE_PHYS,
 			MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
@@ -75,12 +72,19 @@ struct fsl_e_tlb_entry tlb_table[] = {
 	SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
 			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 			0, 7, BOOKE_PAGESZ_1M, 1),
-#endif
 
-#if defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_SPL)
+#if defined(CONFIG_SYS_RAMBOOT) || \
+	(defined(CONFIG_SPL) && !defined(CONFIG_SPL_COMMON_INIT_DDR))
 	SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
 			MAS3_SX|MAS3_SW|MAS3_SR, 0,
-			0, 8, BOOKE_PAGESZ_1G, 1)
+			0, 8, BOOKE_PAGESZ_1G, 1),
+#endif
+
+#ifdef CONFIG_SYS_INIT_L2_ADDR
+	/* *I*G - L2SRAM */
+	SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR, CONFIG_SYS_INIT_L2_ADDR_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_G,
+		      0, 11, BOOKE_PAGESZ_256K, 1)
 #endif
 };
 
diff --git a/board/freescale/p1022ds/Makefile b/board/freescale/p1022ds/Makefile
index 3bc4f4325f..a5821277ef 100644
--- a/board/freescale/p1022ds/Makefile
+++ b/board/freescale/p1022ds/Makefile
@@ -4,10 +4,6 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
 MINIMAL=
 
 ifdef CONFIG_SPL_BUILD
@@ -18,32 +14,16 @@ endif
 
 ifdef MINIMAL
 
-COBJS-y        += spl_minimal.o tlb.o law.o
+obj-y        += spl_minimal.o tlb.o law.o
 
 else
 ifdef CONFIG_SPL_BUILD
-COBJS-y += spl.o
+obj-y += spl.o
 endif
-COBJS-y	+= $(BOARD).o
-COBJS-y	+= ddr.o
-COBJS-y	+= law.o
-COBJS-y	+= tlb.o
+obj-y	+= p1022ds.o
+obj-y	+= ddr.o
+obj-y	+= law.o
+obj-y	+= tlb.o
 
-COBJS-$(CONFIG_FSL_DIU_FB) += diu.o
+obj-$(CONFIG_FSL_DIU_FB) += diu.o
 endif
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS-y))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
diff --git a/board/freescale/p1022ds/ddr.c b/board/freescale/p1022ds/ddr.c
index a639861dae..09212bcee8 100644
--- a/board/freescale/p1022ds/ddr.c
+++ b/board/freescale/p1022ds/ddr.c
@@ -8,8 +8,8 @@
 
 #include <common.h>
 
-#include <asm/fsl_ddr_sdram.h>
-#include <asm/fsl_ddr_dimm_params.h>
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr_dimm_params.h>
 
 struct board_specific_parameters {
 	u32 n_ranks;
@@ -17,7 +17,7 @@ struct board_specific_parameters {
 	u32 clk_adjust;		/* Range: 0-8 */
 	u32 cpo;		/* Range: 2-31 */
 	u32 write_data_delay;	/* Range: 0-6 */
-	u32 force_2T;
+	u32 force_2t;
 };
 
 /*
@@ -72,7 +72,7 @@ void fsl_ddr_board_options(memctl_options_t *popts, dimm_params_t *pdimm,
 				popts->cpo_override = pbsp->cpo;
 				popts->write_data_delay =
 					pbsp->write_data_delay;
-				popts->twoT_en = pbsp->force_2T;
+				popts->twot_en = pbsp->force_2t;
 				goto found;
 			}
 			pbsp_highest = pbsp;
@@ -88,7 +88,7 @@ void fsl_ddr_board_options(memctl_options_t *popts, dimm_params_t *pdimm,
 		popts->clk_adjust = pbsp->clk_adjust;
 		popts->cpo_override = pbsp->cpo;
 		popts->write_data_delay = pbsp->write_data_delay;
-		popts->twoT_en = pbsp->force_2T;
+		popts->twot_en = pbsp->force_2t;
 	} else {
 		panic("DIMM is not supported by this board");
 	}
diff --git a/board/freescale/p1022ds/p1022ds.c b/board/freescale/p1022ds/p1022ds.c
index 3d1951cdba..ba789a4daf 100644
--- a/board/freescale/p1022ds/p1022ds.c
+++ b/board/freescale/p1022ds/p1022ds.c
@@ -14,7 +14,7 @@
 #include <asm/cache.h>
 #include <asm/immap_85xx.h>
 #include <asm/fsl_pci.h>
-#include <asm/fsl_ddr_sdram.h>
+#include <fsl_ddr_sdram.h>
 #include <asm/fsl_serdes.h>
 #include <asm/io.h>
 #include <libfdt.h>
diff --git a/board/freescale/p1022ds/spl.c b/board/freescale/p1022ds/spl.c
index 7f151e38cf..7bd9d296ee 100644
--- a/board/freescale/p1022ds/spl.c
+++ b/board/freescale/p1022ds/spl.c
@@ -21,7 +21,7 @@ static const u32 sysclk_tbl[] = {
 	99999000, 11111000, 12499800, 13333200
 };
 
-ulong get_effective_memsize(void)
+phys_size_t get_effective_memsize(void)
 {
 	return CONFIG_SYS_L2_SIZE;
 }
diff --git a/board/freescale/p1022ds/spl_minimal.c b/board/freescale/p1022ds/spl_minimal.c
index 8b34396843..6c7e1ac3cb 100644
--- a/board/freescale/p1022ds/spl_minimal.c
+++ b/board/freescale/p1022ds/spl_minimal.c
@@ -9,7 +9,7 @@
 #include <asm/io.h>
 #include <nand.h>
 #include <asm/fsl_law.h>
-#include <asm/fsl_ddr_sdram.h>
+#include <fsl_ddr_sdram.h>
 
 
 const static u32 sysclk_tbl[] = {
diff --git a/board/freescale/p1023rdb/Makefile b/board/freescale/p1023rdb/Makefile
index edd2e6daa0..e4f1edf17d 100644
--- a/board/freescale/p1023rdb/Makefile
+++ b/board/freescale/p1023rdb/Makefile
@@ -4,27 +4,7 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS-y	+= $(BOARD).o
-COBJS-y	+= ddr.o
-COBJS-y	+= law.o
-COBJS-y	+= tlb.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS-y))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	+= p1023rdb.o
+obj-y	+= ddr.o
+obj-y	+= law.o
+obj-y	+= tlb.o
diff --git a/board/freescale/p1023rdb/ddr.c b/board/freescale/p1023rdb/ddr.c
index f027885100..d587df527a 100644
--- a/board/freescale/p1023rdb/ddr.c
+++ b/board/freescale/p1023rdb/ddr.c
@@ -8,8 +8,8 @@
 #include <asm/mmu.h>
 #include <asm/immap_85xx.h>
 #include <asm/processor.h>
-#include <asm/fsl_ddr_sdram.h>
-#include <asm/fsl_ddr_dimm_params.h>
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr_dimm_params.h>
 #include <asm/io.h>
 #include <asm/fsl_law.h>
 
@@ -33,20 +33,20 @@ dimm_params_t ddr_raw_timing = {
 	.edc_config = 0,
 	.burst_lengths_bitmask = 0x0c,
 
-	.tCKmin_X_ps = 1875,
-	.caslat_X = 0x1e << 4,	/* 5,6,7,8 */
-	.tAA_ps = 13125,
-	.tWR_ps = 18000,
-	.tRCD_ps = 13125,
-	.tRRD_ps = 7500,
-	.tRP_ps = 13125,
-	.tRAS_ps = 37500,
-	.tRC_ps = 50625,
-	.tRFC_ps = 160000,
-	.tWTR_ps = 7500,
-	.tRTP_ps = 7500,
+	.tckmin_x_ps = 1875,
+	.caslat_x = 0x1e << 4,	/* 5,6,7,8 */
+	.taa_ps = 13125,
+	.twr_ps = 18000,
+	.trcd_ps = 13125,
+	.trrd_ps = 7500,
+	.trp_ps = 13125,
+	.tras_ps = 37500,
+	.trc_ps = 50625,
+	.trfc_ps = 160000,
+	.twtr_ps = 7500,
+	.trtp_ps = 7500,
 	.refresh_rate_ps = 7800000,
-	.tFAW_ps = 37500,
+	.tfaw_ps = 37500,
 };
 
 int fsl_ddr_get_dimm_params(dimm_params_t *pdimm,
diff --git a/board/freescale/p1023rdb/p1023rdb.c b/board/freescale/p1023rdb/p1023rdb.c
index b52b092069..d2d4f8390a 100644
--- a/board/freescale/p1023rdb/p1023rdb.c
+++ b/board/freescale/p1023rdb/p1023rdb.c
@@ -16,7 +16,7 @@
 #include <asm/mmu.h>
 #include <asm/immap_85xx.h>
 #include <asm/fsl_pci.h>
-#include <asm/fsl_ddr_sdram.h>
+#include <fsl_ddr_sdram.h>
 #include <asm/fsl_portals.h>
 #include <libfdt.h>
 #include <fdt_support.h>
diff --git a/board/freescale/p1023rds/Makefile b/board/freescale/p1023rds/Makefile
index f987dc5650..fdbf365ea5 100644
--- a/board/freescale/p1023rds/Makefile
+++ b/board/freescale/p1023rds/Makefile
@@ -4,26 +4,6 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS-y	+= $(BOARD).o
-COBJS-y	+= law.o
-COBJS-y	+= tlb.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS-y))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	+= p1023rds.o
+obj-y	+= law.o
+obj-y	+= tlb.o
diff --git a/board/freescale/p1023rds/README b/board/freescale/p1023rds/README
index 685f5daa99..d382551c4d 100644
--- a/board/freescale/p1023rds/README
+++ b/board/freescale/p1023rds/README
@@ -62,8 +62,8 @@ To program the image in the boot flash bank:
 NOR flash boot:
 	=> tftp 1000000 u-boot.bin
 	=> protect off all
-	=> erase eff80000 efffffff
-	=> cp.b 1000000 eff80000 80000
+	=> erase eff40000 efffffff
+	=> cp.b 1000000 eff40000 c0000
 
 NAND flash boot:
 	=> tftp 1000000 u-boot-nand.bin
diff --git a/board/freescale/p1023rds/p1023rds.c b/board/freescale/p1023rds/p1023rds.c
index 7c54b65c1d..d8c87458e8 100644
--- a/board/freescale/p1023rds/p1023rds.c
+++ b/board/freescale/p1023rds/p1023rds.c
@@ -16,7 +16,7 @@
 #include <asm/mmu.h>
 #include <asm/immap_85xx.h>
 #include <asm/fsl_pci.h>
-#include <asm/fsl_ddr_sdram.h>
+#include <fsl_ddr_sdram.h>
 #include <asm/fsl_portals.h>
 #include <libfdt.h>
 #include <fdt_support.h>
@@ -58,7 +58,8 @@ int checkboard(void)
 phys_size_t fixed_sdram(void)
 {
 #ifndef CONFIG_SYS_RAMBOOT
-	ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_MPC8xxx_DDR_ADDR;
+	struct ccsr_ddr __iomem *ddr =
+		(struct ccsr_ddr __iomem *)CONFIG_SYS_FSL_DDR_ADDR;
 
 	set_next_law(0, LAW_SIZE_2G, LAW_TRGT_IF_DDR_1);
 
diff --git a/board/freescale/p1_p2_rdb/Makefile b/board/freescale/p1_p2_rdb/Makefile
index 36df225cf2..f7b568a021 100644
--- a/board/freescale/p1_p2_rdb/Makefile
+++ b/board/freescale/p1_p2_rdb/Makefile
@@ -4,28 +4,8 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS-y	+= $(BOARD).o
-COBJS-y	+= ddr.o
-COBJS-y	+= law.o
-COBJS-$(CONFIG_PCI)  += pci.o
-COBJS-y	+= tlb.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS-y))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	+= p1_p2_rdb.o
+obj-y	+= ddr.o
+obj-y	+= law.o
+obj-$(CONFIG_PCI)  += pci.o
+obj-y	+= tlb.o
diff --git a/board/freescale/p1_p2_rdb/README b/board/freescale/p1_p2_rdb/README
index cb664a5bd7..cd66e5878d 100644
--- a/board/freescale/p1_p2_rdb/README
+++ b/board/freescale/p1_p2_rdb/README
@@ -20,8 +20,8 @@ Memory Map
 0xef00_0000 - 0xef7f_ffff	Alternate bank		8MB
 0xe800_0000 - 0xefff_ffff	Boot bank		8MB
 
-0xef78_0000 - 0xef7f_ffff	Alternate u-boot address	512KB
-0xeff8_0000 - 0xefff_ffff	Boot u-boot address		512KB
+0xef74_0000 - 0xef7f_ffff	Alternate u-boot address	768KB
+0xeff4_0000 - 0xefff_ffff	Boot u-boot address		768KB
 
 Switch settings to boot from the NOR flash banks
 ------------------------------------------------
@@ -33,16 +33,16 @@ Flashing Images
 To place a new u-boot image in the alternate flash bank and then boot
 with that new image temporarily, use this:
 	tftp 1000000 u-boot.bin
-	erase ef780000 ef7fffff
-	cp.b 1000000 ef780000 80000
+	erase ef740000 ef7fffff
+	cp.b 1000000 ef740000 c0000
 
 Now to boot from the alternate bank change the SW4[8] from 0 to 1.
 
 To program the image in the boot flash bank:
 	tftp 1000000 u-boot.bin
 	protect off all
-	erase eff80000 ffffffff
-	cp.b 1000000 eff80000 80000
+	erase eff40000 ffffffff
+	cp.b 1000000 eff40000 c0000
 
 Using the Device Tree Source File
 ---------------------------------
diff --git a/board/freescale/p1_p2_rdb/ddr.c b/board/freescale/p1_p2_rdb/ddr.c
index 5bee22e638..17d3beac39 100644
--- a/board/freescale/p1_p2_rdb/ddr.c
+++ b/board/freescale/p1_p2_rdb/ddr.c
@@ -8,7 +8,7 @@
 #include <asm/mmu.h>
 #include <asm/immap_85xx.h>
 #include <asm/processor.h>
-#include <asm/fsl_ddr_sdram.h>
+#include <fsl_ddr_sdram.h>
 #include <asm/io.h>
 #include <asm/fsl_law.h>
 
diff --git a/board/freescale/p1_p2_rdb_pc/Makefile b/board/freescale/p1_p2_rdb_pc/Makefile
index f8d0b35aba..a2a1f92ce8 100644
--- a/board/freescale/p1_p2_rdb_pc/Makefile
+++ b/board/freescale/p1_p2_rdb_pc/Makefile
@@ -4,10 +4,6 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB    = $(obj)lib$(BOARD).o
-
 MINIMAL=
 
 ifdef CONFIG_SPL_BUILD
@@ -18,29 +14,16 @@ endif
 
 ifdef MINIMAL
 
-COBJS-y	+= spl_minimal.o tlb.o law.o
+obj-y	+= spl_minimal.o tlb.o law.o
 
 else
-
-COBJS-y        += $(BOARD).o
-COBJS-y        += ddr.o
-COBJS-y        += law.o
-COBJS-y        += tlb.o
-
+ifdef CONFIG_SPL_BUILD
+obj-y += spl.o
 endif
 
-SRCS   := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
-OBJS   := $(addprefix $(obj),$(COBJS-y))
-SOBJS  := $(addprefix $(obj),$(SOBJS))
+obj-y        += p1_p2_rdb_pc.o
+obj-y        += ddr.o
+obj-y        += law.o
+obj-y        += tlb.o
 
-$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+endif
diff --git a/board/freescale/p1_p2_rdb_pc/ddr.c b/board/freescale/p1_p2_rdb_pc/ddr.c
index c0b72e035e..946d5032e7 100644
--- a/board/freescale/p1_p2_rdb_pc/ddr.c
+++ b/board/freescale/p1_p2_rdb_pc/ddr.c
@@ -10,8 +10,8 @@
 #include <asm/mmu.h>
 #include <asm/immap_85xx.h>
 #include <asm/processor.h>
-#include <asm/fsl_ddr_sdram.h>
-#include <asm/fsl_ddr_dimm_params.h>
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr_dimm_params.h>
 #include <asm/io.h>
 #include <asm/fsl_law.h>
 
@@ -34,20 +34,20 @@ dimm_params_t ddr_raw_timing = {
 	.edc_config = 0,
 	.burst_lengths_bitmask = 0x0c,
 
-	.tCKmin_X_ps = 1870,
-	.caslat_X = 0x1e << 4,	/* 5,6,7,8 */
-	.tAA_ps = 13125,
-	.tWR_ps = 15000,
-	.tRCD_ps = 13125,
-	.tRRD_ps = 7500,
-	.tRP_ps = 13125,
-	.tRAS_ps = 37500,
-	.tRC_ps = 50625,
-	.tRFC_ps = 160000,
-	.tWTR_ps = 7500,
-	.tRTP_ps = 7500,
+	.tckmin_x_ps = 1870,
+	.caslat_x = 0x1e << 4,	/* 5,6,7,8 */
+	.taa_ps = 13125,
+	.twr_ps = 15000,
+	.trcd_ps = 13125,
+	.trrd_ps = 7500,
+	.trp_ps = 13125,
+	.tras_ps = 37500,
+	.trc_ps = 50625,
+	.trfc_ps = 160000,
+	.twtr_ps = 7500,
+	.trtp_ps = 7500,
 	.refresh_rate_ps = 7800000,
-	.tFAW_ps = 37500,
+	.tfaw_ps = 37500,
 };
 #elif defined(CONFIG_P2020RDB)
 /* Micron MT41J128M16_15E */
@@ -65,20 +65,20 @@ dimm_params_t ddr_raw_timing = {
 	.edc_config = 0,
 	.burst_lengths_bitmask = 0x0c,
 
-	.tCKmin_X_ps = 1500,
-	.caslat_X = 0x7e << 4,	/* 5,6,7,8,9,10 */
-	.tAA_ps = 13500,
-	.tWR_ps = 15000,
-	.tRCD_ps = 13500,
-	.tRRD_ps = 6000,
-	.tRP_ps = 13500,
-	.tRAS_ps = 36000,
-	.tRC_ps = 49500,
-	.tRFC_ps = 160000,
-	.tWTR_ps = 7500,
-	.tRTP_ps = 7500,
+	.tckmin_x_ps = 1500,
+	.caslat_x = 0x7e << 4,	/* 5,6,7,8,9,10 */
+	.taa_ps = 13500,
+	.twr_ps = 15000,
+	.trcd_ps = 13500,
+	.trrd_ps = 6000,
+	.trp_ps = 13500,
+	.tras_ps = 36000,
+	.trc_ps = 49500,
+	.trfc_ps = 160000,
+	.twtr_ps = 7500,
+	.trtp_ps = 7500,
 	.refresh_rate_ps = 7800000,
-	.tFAW_ps = 30000,
+	.tfaw_ps = 30000,
 };
 #elif (defined(CONFIG_P1020MBG) || defined(CONFIG_P1020RDB_PD))
 /* Micron MT41J512M8_187E */
@@ -96,20 +96,20 @@ dimm_params_t ddr_raw_timing = {
 	.edc_config = 0,
 	.burst_lengths_bitmask = 0x0c,
 
-	.tCKmin_X_ps = 1870,
-	.caslat_X = 0x1e << 4,	/* 5,6,7,8 */
-	.tAA_ps = 13125,
-	.tWR_ps = 15000,
-	.tRCD_ps = 13125,
-	.tRRD_ps = 7500,
-	.tRP_ps = 13125,
-	.tRAS_ps = 37500,
-	.tRC_ps = 50625,
-	.tRFC_ps = 160000,
-	.tWTR_ps = 7500,
-	.tRTP_ps = 7500,
+	.tckmin_x_ps = 1870,
+	.caslat_x = 0x1e << 4,	/* 5,6,7,8 */
+	.taa_ps = 13125,
+	.twr_ps = 15000,
+	.trcd_ps = 13125,
+	.trrd_ps = 7500,
+	.trp_ps = 13125,
+	.tras_ps = 37500,
+	.trc_ps = 50625,
+	.trfc_ps = 160000,
+	.twtr_ps = 7500,
+	.trtp_ps = 7500,
 	.refresh_rate_ps = 7800000,
-	.tFAW_ps = 37500,
+	.tfaw_ps = 37500,
 };
 #elif defined(CONFIG_P1020RDB_PC)
 /*
@@ -133,20 +133,20 @@ dimm_params_t ddr_raw_timing = {
 	.edc_config = 0,
 	.burst_lengths_bitmask = 0x0c,
 
-	.tCKmin_X_ps = 1875,
-	.caslat_X = 0x1e << 4,	/* 5,6,7,8 */
-	.tAA_ps = 13125,
-	.tWR_ps = 15000,
-	.tRCD_ps = 13125,
-	.tRRD_ps = 7500,
-	.tRP_ps = 13125,
-	.tRAS_ps = 37500,
-	.tRC_ps = 50625,
-	.tRFC_ps = 160000,
-	.tWTR_ps = 7500,
-	.tRTP_ps = 7500,
+	.tckmin_x_ps = 1875,
+	.caslat_x = 0x1e << 4,	/* 5,6,7,8 */
+	.taa_ps = 13125,
+	.twr_ps = 15000,
+	.trcd_ps = 13125,
+	.trrd_ps = 7500,
+	.trp_ps = 13125,
+	.tras_ps = 37500,
+	.trc_ps = 50625,
+	.trfc_ps = 160000,
+	.twtr_ps = 7500,
+	.trtp_ps = 7500,
 	.refresh_rate_ps = 7800000,
-	.tFAW_ps = 37500,
+	.tfaw_ps = 37500,
 };
 #elif	defined(CONFIG_P1024RDB) || \
 	defined(CONFIG_P1025RDB)
@@ -171,20 +171,20 @@ dimm_params_t ddr_raw_timing = {
 	.edc_config = 0,
 	.burst_lengths_bitmask = 0x0c,
 
-	.tCKmin_X_ps = 1500,
-	.caslat_X = 0x3e << 4,	/* 5,6,7,8,9 */
-	.tAA_ps = 13125,
-	.tWR_ps = 15000,
-	.tRCD_ps = 13125,
-	.tRRD_ps = 6000,
-	.tRP_ps = 13125,
-	.tRAS_ps = 36000,
-	.tRC_ps = 49125,
-	.tRFC_ps = 160000,
-	.tWTR_ps = 7500,
-	.tRTP_ps = 7500,
+	.tckmin_x_ps = 1500,
+	.caslat_x = 0x3e << 4,	/* 5,6,7,8,9 */
+	.taa_ps = 13125,
+	.twr_ps = 15000,
+	.trcd_ps = 13125,
+	.trrd_ps = 6000,
+	.trp_ps = 13125,
+	.tras_ps = 36000,
+	.trc_ps = 49125,
+	.trfc_ps = 160000,
+	.twtr_ps = 7500,
+	.trtp_ps = 7500,
 	.refresh_rate_ps = 7800000,
-	.tFAW_ps = 30000,
+	.tfaw_ps = 30000,
 };
 #else
 #error Missing raw timing data for this board
diff --git a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c
index 50553dacd9..5f3d6fd28b 100644
--- a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c
+++ b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c
@@ -1,5 +1,5 @@
 /*
- * Copyright 2010-2011 Freescale Semiconductor, Inc.
+ * Copyright 2010-2011, 2013 Freescale Semiconductor, Inc.
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */
@@ -14,7 +14,7 @@
 #include <asm/cache.h>
 #include <asm/immap_85xx.h>
 #include <asm/fsl_pci.h>
-#include <asm/fsl_ddr_sdram.h>
+#include <fsl_ddr_sdram.h>
 #include <asm/io.h>
 #include <asm/fsl_law.h>
 #include <asm/fsl_lbc.h>
@@ -354,7 +354,7 @@ int board_eth_init(bd_t *bis)
 		puts("No address specified for VSC7385 microcode.\n");
 #endif
 
-	mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR;
+	mdio_info.regs = TSEC_GET_MDIO_REGS_BASE(1);
 	mdio_info.name = DEFAULT_MII_NAME;
 
 	fsl_pq_mdio_init(bis, &mdio_info);
diff --git a/board/freescale/p1_p2_rdb_pc/spl.c b/board/freescale/p1_p2_rdb_pc/spl.c
new file mode 100644
index 0000000000..8d0d850480
--- /dev/null
+++ b/board/freescale/p1_p2_rdb_pc/spl.c
@@ -0,0 +1,122 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <ns16550.h>
+#include <malloc.h>
+#include <mmc.h>
+#include <nand.h>
+#include <i2c.h>
+#include <fsl_esdhc.h>
+#include <spi_flash.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static const u32 sysclk_tbl[] = {
+	66666000, 7499900, 83332500, 8999900,
+	99999000, 11111000, 12499800, 13333200
+};
+
+phys_size_t get_effective_memsize(void)
+{
+	return CONFIG_SYS_L2_SIZE;
+}
+
+void board_init_f(ulong bootflag)
+{
+	u32 plat_ratio, bus_clk;
+	ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
+
+	console_init_f();
+
+	/* Set pmuxcr to allow both i2c1 and i2c2 */
+	setbits_be32(&gur->pmuxcr, in_be32(&gur->pmuxcr) | 0x1000);
+	setbits_be32(&gur->pmuxcr,
+		     in_be32(&gur->pmuxcr) | MPC85xx_PMUXCR_SD_DATA);
+
+	/* Read back the register to synchronize the write. */
+	in_be32(&gur->pmuxcr);
+
+#ifdef CONFIG_SPL_SPI_BOOT
+	clrbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_SD_DATA);
+#endif
+
+	/* initialize selected port with appropriate baud rate */
+	plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO;
+	plat_ratio >>= 1;
+	bus_clk = CONFIG_SYS_CLK_FREQ * plat_ratio;
+	gd->bus_clk = bus_clk;
+
+	NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
+		     bus_clk / 16 / CONFIG_BAUDRATE);
+#ifdef CONFIG_SPL_MMC_BOOT
+	puts("\nSD boot...\n");
+#elif defined(CONFIG_SPL_SPI_BOOT)
+	puts("\nSPI Flash boot...\n");
+#endif
+
+	/* copy code to RAM and jump to it - this should not return */
+	/* NOTE - code has to be copied out of NAND buffer before
+	 * other blocks can be read.
+	 */
+	relocate_code(CONFIG_SPL_RELOC_STACK, 0, CONFIG_SPL_RELOC_TEXT_BASE);
+}
+
+void board_init_r(gd_t *gd, ulong dest_addr)
+{
+	/* Pointer is writable since we allocated a register for it */
+	gd = (gd_t *)CONFIG_SPL_GD_ADDR;
+	bd_t *bd;
+
+	memset(gd, 0, sizeof(gd_t));
+	bd = (bd_t *)(CONFIG_SPL_GD_ADDR + sizeof(gd_t));
+	memset(bd, 0, sizeof(bd_t));
+	gd->bd = bd;
+	bd->bi_memstart = CONFIG_SYS_INIT_L2_ADDR;
+	bd->bi_memsize = CONFIG_SYS_L2_SIZE;
+
+	probecpu();
+	get_clocks();
+	mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR,
+			CONFIG_SPL_RELOC_MALLOC_SIZE);
+
+#ifndef CONFIG_SPL_NAND_BOOT
+	env_init();
+#endif
+#ifdef CONFIG_SPL_MMC_BOOT
+	mmc_initialize(bd);
+#endif
+	/* relocate environment function pointers etc. */
+#ifdef CONFIG_SPL_NAND_BOOT
+	nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
+			    (uchar *)CONFIG_ENV_ADDR);
+	gd->env_addr  = (ulong)(CONFIG_ENV_ADDR);
+	gd->env_valid = 1;
+#else
+	env_relocate();
+#endif
+
+#ifdef CONFIG_SYS_I2C
+	i2c_init_all();
+#else
+	i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
+#endif
+
+	gd->ram_size = initdram(0);
+#ifdef CONFIG_SPL_NAND_BOOT
+	puts("Tertiary program loader running in sram...");
+#else
+	puts("Second program loader running in sram...\n");
+#endif
+
+#ifdef CONFIG_SPL_MMC_BOOT
+	mmc_boot();
+#elif defined(CONFIG_SPL_SPI_BOOT)
+	spi_boot();
+#elif defined(CONFIG_SPL_NAND_BOOT)
+	nand_boot();
+#endif
+}
diff --git a/board/freescale/p1_p2_rdb_pc/spl_minimal.c b/board/freescale/p1_p2_rdb_pc/spl_minimal.c
index ac07572c89..92437bc787 100644
--- a/board/freescale/p1_p2_rdb_pc/spl_minimal.c
+++ b/board/freescale/p1_p2_rdb_pc/spl_minimal.c
@@ -10,64 +10,19 @@
 #include <nand.h>
 #include <linux/compiler.h>
 #include <asm/fsl_law.h>
-#include <asm/fsl_ddr_sdram.h>
+#include <fsl_ddr_sdram.h>
 #include <asm/global_data.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
-#ifndef CONFIG_SYS_INIT_L2_ADDR
-/*
- * Fixed sdram init -- doesn't use serial presence detect.
- */
-static void sdram_init(void)
-{
-	ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_MPC8xxx_DDR_ADDR;
-
-	__raw_writel(CONFIG_SYS_DDR_CS0_BNDS, &ddr->cs0_bnds);
-	__raw_writel(CONFIG_SYS_DDR_CS0_CONFIG, &ddr->cs0_config);
-#if CONFIG_CHIP_SELECTS_PER_CTRL > 1
-	__raw_writel(CONFIG_SYS_DDR_CS1_BNDS, &ddr->cs1_bnds);
-	__raw_writel(CONFIG_SYS_DDR_CS1_CONFIG, &ddr->cs1_config);
-#endif
-	__raw_writel(CONFIG_SYS_DDR_TIMING_3, &ddr->timing_cfg_3);
-	__raw_writel(CONFIG_SYS_DDR_TIMING_0, &ddr->timing_cfg_0);
-	__raw_writel(CONFIG_SYS_DDR_TIMING_1, &ddr->timing_cfg_1);
-	__raw_writel(CONFIG_SYS_DDR_TIMING_2, &ddr->timing_cfg_2);
-
-	__raw_writel(CONFIG_SYS_DDR_CONTROL_2, &ddr->sdram_cfg_2);
-	__raw_writel(CONFIG_SYS_DDR_MODE_1, &ddr->sdram_mode);
-	__raw_writel(CONFIG_SYS_DDR_MODE_2, &ddr->sdram_mode_2);
-
-	__raw_writel(CONFIG_SYS_DDR_INTERVAL, &ddr->sdram_interval);
-	__raw_writel(CONFIG_SYS_DDR_DATA_INIT, &ddr->sdram_data_init);
-	__raw_writel(CONFIG_SYS_DDR_CLK_CTRL, &ddr->sdram_clk_cntl);
-
-	__raw_writel(CONFIG_SYS_DDR_TIMING_4, &ddr->timing_cfg_4);
-	__raw_writel(CONFIG_SYS_DDR_TIMING_5, &ddr->timing_cfg_5);
-	__raw_writel(CONFIG_SYS_DDR_ZQ_CONTROL, &ddr->ddr_zq_cntl);
-	__raw_writel(CONFIG_SYS_DDR_WRLVL_CONTROL, &ddr->ddr_wrlvl_cntl);
-
-	/* Set, but do not enable the memory */
-	__raw_writel(CONFIG_SYS_DDR_CONTROL & ~SDRAM_CFG_MEM_EN, &ddr->sdram_cfg);
-
-	asm volatile("sync;isync");
-	udelay(500);
-
-	/* Let the controller go */
-	out_be32(&ddr->sdram_cfg, in_be32(&ddr->sdram_cfg) | SDRAM_CFG_MEM_EN);
-
-	set_next_law(0, CONFIG_SYS_SDRAM_SIZE_LAW, LAW_TRGT_IF_DDR_1);
-}
-#endif
-
 void board_init_f(ulong bootflag)
 {
 	u32 plat_ratio;
 	ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
-#ifndef CONFIG_QE
-	ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR);
-#elif defined(CONFIG_P1021RDB)
-	par_io_t *par_io = (par_io_t *)&(gur->qe_par_io);
+
+#if defined(CONFIG_SYS_NAND_BR_PRELIM) && defined(CONFIG_SYS_NAND_OR_PRELIM)
+	set_lbc_br(0, CONFIG_SYS_NAND_BR_PRELIM);
+	set_lbc_or(0, CONFIG_SYS_NAND_OR_PRELIM);
 #endif
 
 	/* initialize selected port with appropriate baud rate */
@@ -80,35 +35,6 @@ void board_init_f(ulong bootflag)
 
 	puts("\nNAND boot... ");
 
-#ifndef CONFIG_QE
-	/* init DDR3 reset signal */
-	__raw_writel(0x02000000, &pgpio->gpdir);
-	__raw_writel(0x00200000, &pgpio->gpodr);
-	__raw_writel(0x00000000, &pgpio->gpdat);
-	udelay(1000);
-	__raw_writel(0x00200000, &pgpio->gpdat);
-	udelay(1000);
-	__raw_writel(0x00000000, &pgpio->gpdir);
-#elif defined(CONFIG_P1021RDB)
-	/* init DDR3 reset signal CE_PB8 */
-	out_be32(&par_io[1].cpdir1, 0x00004000);
-	out_be32(&par_io[1].cpodr, 0x00800000);
-	out_be32(&par_io[1].cppar1, 0x00000000);
-	/* reset DDR3 */
-	out_be32(&par_io[1].cpdat, 0x00800000);
-	udelay(1000);
-	out_be32(&par_io[1].cpdat, 0x00000000);
-	udelay(1000);
-	out_be32(&par_io[1].cpdat, 0x00800000);
-	/* disable the CE_PB8 */
-	out_be32(&par_io[1].cpdir1, 0x00000000);
-#endif
-
-#ifndef CONFIG_SYS_INIT_L2_ADDR
-	/* Initialize the DDR3 */
-	sdram_init();
-#endif
-
 	/* copy code to RAM and jump to it - this should not return */
 	/* NOTE - code has to be copied out of NAND buffer before
 	 * other blocks can be read.
@@ -118,6 +44,7 @@ void board_init_f(ulong bootflag)
 
 void board_init_r(gd_t *gd, ulong dest_addr)
 {
+	puts("\nSecond program loader running in sram...");
 	nand_boot();
 }
 
diff --git a/board/freescale/p1_p2_rdb_pc/tlb.c b/board/freescale/p1_p2_rdb_pc/tlb.c
index d4561c7643..1c0008b2e6 100644
--- a/board/freescale/p1_p2_rdb_pc/tlb.c
+++ b/board/freescale/p1_p2_rdb_pc/tlb.c
@@ -78,17 +78,8 @@ struct fsl_e_tlb_entry tlb_table[] = {
 			0, 7, BOOKE_PAGESZ_1M, 1),
 #endif
 
-#if defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_SPL)
-#ifdef CONFIG_SYS_INIT_L2_ADDR
-	/* L2SRAM */
-	SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR, CONFIG_SYS_INIT_L2_ADDR_PHYS,
-		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		      0, 8, BOOKE_PAGESZ_256K, 1),
-	SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR + 0x40000,
-		      CONFIG_SYS_INIT_L2_ADDR_PHYS + 0x40000,
-		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		      0, 12, BOOKE_PAGESZ_256K, 1),
-#else
+#if defined(CONFIG_SYS_RAMBOOT) || \
+	(defined(CONFIG_SPL) && !defined(CONFIG_SPL_COMMON_INIT_DDR))
 	/* *I*G - eSDHC/eSPI/NAND boot */
 	SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
 			MAS3_SX|MAS3_SW|MAS3_SR, 0,
@@ -101,8 +92,20 @@ struct fsl_e_tlb_entry tlb_table[] = {
 			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 			0, 9, BOOKE_PAGESZ_1G, 1),
 #endif /* P1020MBG */
-#endif /* not L2 SRAM */
 #endif /* RAMBOOT/SPL */
+
+#ifdef CONFIG_SYS_INIT_L2_ADDR
+	/* *I*G - L2SRAM */
+	SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR, CONFIG_SYS_INIT_L2_ADDR_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_G,
+		      0, 11, BOOKE_PAGESZ_256K, 1),
+#if CONFIG_SYS_L2_SIZE >= (256 << 10)
+	SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR + 0x40000,
+		      CONFIG_SYS_INIT_L2_ADDR_PHYS + 0x40000,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 12, BOOKE_PAGESZ_256K, 1)
+#endif
+#endif
 };
 
 int num_tlb_entries = ARRAY_SIZE(tlb_table);
diff --git a/board/freescale/p1_twr/Makefile b/board/freescale/p1_twr/Makefile
index 915b9bc895..70afac4088 100644
--- a/board/freescale/p1_twr/Makefile
+++ b/board/freescale/p1_twr/Makefile
@@ -3,33 +3,7 @@
 #
 # SPDX-License-Identifier:	GPL-2.0+
 
-include $(TOPDIR)/config.mk
-
-LIB    = $(obj)lib$(BOARD).o
-
-COBJS-y        += $(BOARD).o
-COBJS-y        += ddr.o
-COBJS-y        += law.o
-COBJS-y        += tlb.o
-
-SRCS   := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
-OBJS   := $(addprefix $(obj),$(COBJS-y))
-SOBJS  := $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-clean:
-	rm -f $(OBJS) $(SOBJS)
-
-distclean:	clean
-	rm -f $(LIB) core *.bak .depend
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y        += p1_twr.o
+obj-y        += ddr.o
+obj-y        += law.o
+obj-y        += tlb.o
diff --git a/board/freescale/p1_twr/ddr.c b/board/freescale/p1_twr/ddr.c
index 67f69d79bd..a2ce75a40d 100644
--- a/board/freescale/p1_twr/ddr.c
+++ b/board/freescale/p1_twr/ddr.c
@@ -8,8 +8,8 @@
 #include <asm/mmu.h>
 #include <asm/immap_85xx.h>
 #include <asm/processor.h>
-#include <asm/fsl_ddr_sdram.h>
-#include <asm/fsl_ddr_dimm_params.h>
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr_dimm_params.h>
 #include <asm/io.h>
 #include <asm/fsl_law.h>
 
diff --git a/board/freescale/p1_twr/p1_twr.c b/board/freescale/p1_twr/p1_twr.c
index ea8db6fc07..0e0d0587d7 100644
--- a/board/freescale/p1_twr/p1_twr.c
+++ b/board/freescale/p1_twr/p1_twr.c
@@ -14,7 +14,7 @@
 #include <asm/cache.h>
 #include <asm/immap_85xx.h>
 #include <asm/fsl_pci.h>
-#include <asm/fsl_ddr_sdram.h>
+#include <fsl_ddr_sdram.h>
 #include <asm/io.h>
 #include <asm/fsl_law.h>
 #include <asm/fsl_lbc.h>
diff --git a/board/freescale/p2020come/Makefile b/board/freescale/p2020come/Makefile
index 2e6b6f6c95..4857136f1f 100644
--- a/board/freescale/p2020come/Makefile
+++ b/board/freescale/p2020come/Makefile
@@ -4,27 +4,7 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB			= $(obj)lib$(BOARD).o
-
-COBJS-y			+= $(BOARD).o
-COBJS-y			+= ddr.o
-COBJS-y			+= law.o
-COBJS-y			+= tlb.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS-y))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB): $(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y			+= p2020come.o
+obj-y			+= ddr.o
+obj-y			+= law.o
+obj-y			+= tlb.o
diff --git a/board/freescale/p2020come/ddr.c b/board/freescale/p2020come/ddr.c
index da804771fb..b642e1255c 100644
--- a/board/freescale/p2020come/ddr.c
+++ b/board/freescale/p2020come/ddr.c
@@ -5,8 +5,8 @@
  */
 #include <common.h>
 
-#include <asm/fsl_ddr_sdram.h>
-#include <asm/fsl_ddr_dimm_params.h>
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr_dimm_params.h>
 
 void fsl_ddr_board_options(memctl_options_t *popts,
 				dimm_params_t *pdimm,
diff --git a/board/freescale/p2020ds/Makefile b/board/freescale/p2020ds/Makefile
index 0967b28420..ee00806d73 100644
--- a/board/freescale/p2020ds/Makefile
+++ b/board/freescale/p2020ds/Makefile
@@ -6,27 +6,7 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS-y	+= $(BOARD).o
-COBJS-y	+= ddr.o
-COBJS-y	+= law.o
-COBJS-y	+= tlb.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS-y))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	+= p2020ds.o
+obj-y	+= ddr.o
+obj-y	+= law.o
+obj-y	+= tlb.o
diff --git a/board/freescale/p2020ds/ddr.c b/board/freescale/p2020ds/ddr.c
index 59034f9f89..debe70b18b 100644
--- a/board/freescale/p2020ds/ddr.c
+++ b/board/freescale/p2020ds/ddr.c
@@ -8,8 +8,8 @@
 
 #include <common.h>
 
-#include <asm/fsl_ddr_sdram.h>
-#include <asm/fsl_ddr_dimm_params.h>
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr_dimm_params.h>
 
 struct board_specific_parameters {
 	u32 n_ranks;
@@ -17,7 +17,7 @@ struct board_specific_parameters {
 	u32 clk_adjust;
 	u32 cpo;
 	u32 write_data_delay;
-	u32 force_2T;
+	u32 force_2t;
 };
 
 
@@ -37,7 +37,7 @@ static const struct board_specific_parameters dimm0[] = {
 	 *   num|  hi|  clk| cpo|wrdata|2T
 	 * ranks| mhz|adjst|    | delay|
 	 */
-#ifdef CONFIG_FSL_DDR2
+#ifdef CONFIG_SYS_FSL_DDR2
 	{2,  549,    4,   0x1f,    2,  0},
 	{2,  680,    4,   0x1f,    3,  0},
 	{2,  850,    4,   0x1f,    4,  0},
@@ -90,7 +90,7 @@ void fsl_ddr_board_options(memctl_options_t *popts,
 				popts->cpo_override = pbsp->cpo;
 				popts->write_data_delay =
 					pbsp->write_data_delay;
-				popts->twoT_en = pbsp->force_2T;
+				popts->twot_en = pbsp->force_2t;
 				goto found;
 			}
 			pbsp_highest = pbsp;
@@ -106,7 +106,7 @@ void fsl_ddr_board_options(memctl_options_t *popts,
 		popts->clk_adjust = pbsp_highest->clk_adjust;
 		popts->cpo_override = pbsp_highest->cpo;
 		popts->write_data_delay = pbsp_highest->write_data_delay;
-		popts->twoT_en = pbsp_highest->force_2T;
+		popts->twot_en = pbsp_highest->force_2t;
 	} else {
 		panic("DIMM is not supported by this board");
 	}
diff --git a/board/freescale/p2020ds/p2020ds.c b/board/freescale/p2020ds/p2020ds.c
index 58a42231a9..a0cf927038 100644
--- a/board/freescale/p2020ds/p2020ds.c
+++ b/board/freescale/p2020ds/p2020ds.c
@@ -12,7 +12,7 @@
 #include <asm/cache.h>
 #include <asm/immap_85xx.h>
 #include <asm/fsl_pci.h>
-#include <asm/fsl_ddr_sdram.h>
+#include <fsl_ddr_sdram.h>
 #include <asm/io.h>
 #include <asm/fsl_serdes.h>
 #include <miiphy.h>
@@ -68,7 +68,8 @@ int checkboard(void)
 
 phys_size_t fixed_sdram(void)
 {
-	volatile ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_MPC8xxx_DDR_ADDR;
+	struct ccsr_ddr __iomem *ddr =
+		(struct ccsr_ddr __iomem *)CONFIG_SYS_FSL_DDR_ADDR;
 	uint d_init;
 
 	ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG;
diff --git a/board/freescale/p2041rdb/Makefile b/board/freescale/p2041rdb/Makefile
index 147f658b26..c74f4c62f8 100644
--- a/board/freescale/p2041rdb/Makefile
+++ b/board/freescale/p2041rdb/Makefile
@@ -6,27 +6,7 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS-y	+= $(BOARD).o
-COBJS-y += cpld.o
-COBJS-y	+= ddr.o
-COBJS-y	+= eth.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS-y))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	+= p2041rdb.o
+obj-y += cpld.o
+obj-y	+= ddr.o
+obj-y	+= eth.o
diff --git a/board/freescale/p2041rdb/README b/board/freescale/p2041rdb/README
index 292d0d39cf..9b5539fff3 100644
--- a/board/freescale/p2041rdb/README
+++ b/board/freescale/p2041rdb/README
@@ -18,8 +18,8 @@ Boot from NOR flash
 2. Program image
 	=> tftp 1000000 u-boot.bin
 	=> protect off all
-	=> erase eff80000 efffffff
-	=> cp.b 1000000 eff80000 80000
+	=> erase eff40000 efffffff
+	=> cp.b 1000000 eff40000 c0000
 
 3. Program RCW
 	=> tftp 1000000 rcw.bin
@@ -30,8 +30,8 @@ Boot from NOR flash
 4. Program FMAN Firmware ucode
 	=> tftp 1000000 ucode.bin
 	=> protect off all
-	=> erase ef000000 ef0fffff
-	=> cp.b 1000000 ef000000 2000
+	=> erase eff00000 eff3ffff
+	=> cp.b 1000000 eff00000 2000
 
 5. Change DIP-switch
 	SW1[1-5] = 10110
@@ -50,11 +50,11 @@ Boot from SDCard
 3. Program the PBL image to SDCard
 	=> tftp 1000000 pbl_sd.bin
 	=> mmcinfo
-	=> mmc write 1000000 8 441
+	=> mmc write 1000000 8 672
 
 4. Program FMAN Firmware ucode
 	=> tftp 1000000 ucode.bin
-	=> mmc write 1000000 46a 10
+	=> mmc write 1000000 690 10
 
 5. Change DIP-switch
 	SW1[1-5] = 01100
diff --git a/board/freescale/p2041rdb/ddr.c b/board/freescale/p2041rdb/ddr.c
index 6d9a5de1c5..b8bbcdf2a8 100644
--- a/board/freescale/p2041rdb/ddr.c
+++ b/board/freescale/p2041rdb/ddr.c
@@ -10,8 +10,8 @@
 #include <i2c.h>
 #include <hwconfig.h>
 #include <asm/mmu.h>
-#include <asm/fsl_ddr_sdram.h>
-#include <asm/fsl_ddr_dimm_params.h>
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr_dimm_params.h>
 #include <asm/fsl_law.h>
 
 struct board_specific_parameters {
@@ -21,7 +21,7 @@ struct board_specific_parameters {
 	u32 wrlvl_start;
 	u32 cpo;
 	u32 write_data_delay;
-	u32 force_2T;
+	u32 force_2t;
 };
 
 /*
@@ -76,7 +76,7 @@ void fsl_ddr_board_options(memctl_options_t *popts,
 					pbsp->write_data_delay;
 				popts->clk_adjust = pbsp->clk_adjust;
 				popts->wrlvl_start = pbsp->wrlvl_start;
-				popts->twoT_en = pbsp->force_2T;
+				popts->twot_en = pbsp->force_2t;
 				goto found;
 			}
 			pbsp_highest = pbsp;
@@ -93,7 +93,7 @@ void fsl_ddr_board_options(memctl_options_t *popts,
 		popts->write_data_delay = pbsp_highest->write_data_delay;
 		popts->clk_adjust = pbsp_highest->clk_adjust;
 		popts->wrlvl_start = pbsp_highest->wrlvl_start;
-		popts->twoT_en = pbsp_highest->force_2T;
+		popts->twot_en = pbsp_highest->force_2t;
 	} else {
 		panic("DIMM is not supported by this board");
 	}
diff --git a/board/freescale/p2041rdb/p2041rdb.c b/board/freescale/p2041rdb/p2041rdb.c
index 60694a6723..8554512df6 100644
--- a/board/freescale/p2041rdb/p2041rdb.c
+++ b/board/freescale/p2041rdb/p2041rdb.c
@@ -155,20 +155,6 @@ unsigned long get_board_sys_clk(unsigned long dummy)
 	}
 }
 
-static const char *serdes_clock_to_string(u32 clock)
-{
-	switch (clock) {
-	case SRDS_PLLCR0_RFCK_SEL_100:
-		return "100";
-	case SRDS_PLLCR0_RFCK_SEL_125:
-		return "125";
-	case SRDS_PLLCR0_RFCK_SEL_156_25:
-		return "156.25";
-	default:
-		return "150";
-	}
-}
-
 #define NUM_SRDS_BANKS	2
 
 int misc_init_r(void)
diff --git a/board/freescale/t1040qds/Makefile b/board/freescale/t1040qds/Makefile
new file mode 100644
index 0000000000..19ed21b7df
--- /dev/null
+++ b/board/freescale/t1040qds/Makefile
@@ -0,0 +1,13 @@
+#
+# Copyright 2013 Freescale Semiconductor, Inc.
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y	+= t1040qds.o
+obj-y	+= ddr.o
+obj-$(CONFIG_PCI)     += pci.o
+obj-y	+= law.o
+obj-y	+= tlb.o
+obj-y	+= eth.o
+obj-y	+= diu.o
diff --git a/board/freescale/t1040qds/README b/board/freescale/t1040qds/README
new file mode 100644
index 0000000000..8160ca0bc0
--- /dev/null
+++ b/board/freescale/t1040qds/README
@@ -0,0 +1,169 @@
+Overview
+--------
+The T1040QDS is a Freescale reference board that hosts the T1040 SoC
+(and variants).
+
+T1040 SoC Overview
+------------------
+The QorIQ T1040/T1042 processor support four integrated 64-bit e5500 PA
+processor cores with high-performance data path acceleration architecture
+and network peripheral interfaces required for networking & telecommunications.
+
+The T1040/T1042 SoC includes the following function and features:
+
+ - Four e5500 cores, each with a private 256 KB L2 cache
+ - 256 KB shared L3 CoreNet platform cache (CPC)
+ - Interconnect CoreNet platform
+ - 32-/64-bit DDR3L/DDR4 SDRAM memory controller with ECC and interleaving
+   support
+ - Data Path Acceleration Architecture (DPAA) incorporating acceleration
+ for the following functions:
+    -  Packet parsing, classification, and distribution
+    -  Queue management for scheduling, packet sequencing, and congestion
+    	management
+    -  Cryptography Acceleration (SEC 5.0)
+    - RegEx Pattern Matching Acceleration (PME 2.2)
+    - IEEE Std 1588 support
+    - Hardware buffer management for buffer allocation and deallocation
+ - Ethernet interfaces
+    - Integrated 8-port Gigabit Ethernet switch (T1040 only)
+    - Four 1 Gbps Ethernet controllers
+ - Two RGMII interfaces or one RGMII and one MII interfaces
+ - High speed peripheral interfaces
+   - Four PCI Express 2.0 controllers running at up to 5 GHz
+   - Two SATA controllers supporting 1.5 and 3.0 Gb/s operation
+   - Upto two QSGMII interface
+   - Upto six SGMII interface supporting 1000 Mbps
+   - One SGMII interface supporting upto 2500 Mbps
+ - Additional peripheral interfaces
+   - Two USB 2.0 controllers with integrated PHY
+   - SD/eSDHC/eMMC
+   -  eSPI controller
+   - Four I2C controllers
+   - Four UARTs
+   - Four GPIO controllers
+   - Integrated flash controller (IFC)
+   - LCD and HDMI interface (DIU) with 12 bit dual data rate
+   - TDM interface
+ - Multicore programmable interrupt controller (PIC)
+ - Two 8-channel DMA engines
+ - Single source clocking implementation
+ - Deep Sleep power implementaion (wakeup from GPIO/Timer/Ethernet/USB)
+
+ T1040QDS board Overview
+ -----------------------
+ - SERDES Connections, 8 lanes supporting:
+      — PCI Express: supporting Gen 1 and Gen 2;
+      — SGMII
+      — QSGMII
+      — SATA 2.0
+      — Aurora debug with dedicated connectors (T1040 only)
+ - DDR Controller
+     - Supports rates of up to 1600 MHz data-rate
+     - Supports one DDR3LP UDIMM/RDIMMs, of single-, dual- or quad-rank types.
+ -IFC/Local Bus
+     - NAND flash: 8-bit, async, up to 2GB.
+     - NOR: 8-bit or 16-bit, non-multiplexed, up to 512MB
+     - GASIC: Simple (minimal) target within Qixis FPGA
+     - PromJET rapid memory download support
+ - Ethernet
+     - Two on-board RGMII 10/100/1G ethernet ports.
+     - PHY #0 remains powered up during deep-sleep (T1040 only)
+ - QIXIS System Logic FPGA
+ - Clocks
+     - System and DDR clock (SYSCLK, “DDRCLK”)
+     - SERDES clocks
+ - Power Supplies
+ - Video
+     - DIU supports video at up to 1280x1024x32bpp
+ - USB
+     - Supports two USB 2.0 ports with integrated PHYs
+     — Two type A ports with 5V@1.5A per port.
+     — Second port can be converted to OTG mini-AB
+ - SDHC
+     - SDHC port connects directly to an adapter card slot, featuring:
+     - Supporting SD slots for: SD, SDHC (1x, 4x, 8x) and/or MMC
+     — Supporting eMMC memory devices
+ - SPI
+    -  On-board support of 3 different devices and sizes
+ - Other IO
+    - Two Serial ports
+    - ProfiBus port
+    - Four I2C ports
+
+Memory map on T1040QDS
+----------------------
+The addresses in brackets are physical addresses.
+
+Start Address  End Address      Description                     Size
+0xF_FFDF_0000  0xF_FFDF_0FFF    IFC - FPGA                      4KB
+0xF_FF80_0000  0xF_FF80_FFFF    IFC - NAND Flash                64KB
+0xF_FE00_0000  0xF_FEFF_FFFF    CCSRBAR                         16MB
+0xF_F803_0000  0xF_F803_FFFF    PCI Express 4 I/O Space         64KB
+0xF_F802_0000  0xF_F802_FFFF    PCI Express 3 I/O Space	        64KB
+0xF_F801_0000  0xF_F801_FFFF    PCI Express 2 I/O Space         64KB
+0xF_F800_0000  0xF_F800_FFFF    PCI Express 1 I/O Space	        64KB
+0xF_F600_0000  0xF_F7FF_FFFF    Queue manager software portal   32MB
+0xF_F400_0000  0xF_F5FF_FFFF    Buffer manager software portal  32MB
+0xF_E800_0000  0xF_EFFF_FFFF    IFC - NOR Flash                 128MB
+0xF_E000_0000  0xF_E7FF_FFFF    Promjet                         128MB
+0xF_0000_0000  0xF_003F_FFFF    DCSR                            4MB
+0xC_3000_0000  0xC_3FFF_FFFF    PCI Express 4 Mem Space         256MB
+0xC_2000_0000  0xC_2FFF_FFFF    PCI Express 3 Mem Space         256MB
+0xC_1000_0000  0xC_1FFF_FFFF    PCI Express 2 Mem Space         256MB
+0xC_0000_0000  0xC_0FFF_FFFF    PCI Express 1 Mem Space         256MB
+0x0_0000_0000  0x0_ffff_ffff    DDR                             2GB
+
+
+NOR Flash memory Map on T1040QDS
+--------------------------------
+ Start          End             Definition                       Size
+0xEFF40000      0xEFFFFFFF      u-boot (current bank)            768KB
+0xEFF20000      0xEFF3FFFF      u-boot env (current bank)        128KB
+0xEFF00000      0xEFF1FFFF      FMAN Ucode (current bank)        128KB
+0xED300000      0xEFEFFFFF      rootfs (alt bank)                44MB
+0xEC800000      0xEC8FFFFF      Hardware device tree (alt bank)  1MB
+0xEC020000      0xEC7FFFFF      Linux.uImage (alt bank)          7MB + 875KB
+0xEC000000      0xEC01FFFF      RCW (alt bank)                   128KB
+0xEBF40000      0xEBFFFFFF      u-boot (alt bank)                768KB
+0xEBF20000      0xEBF3FFFF      u-boot env (alt bank)            128KB
+0xEBF00000      0xEBF1FFFF      FMAN ucode (alt bank)            128KB
+0xE9300000      0xEBEFFFFF      rootfs (current bank)            44MB
+0xE8800000      0xE88FFFFF      Hardware device tree (cur bank)  11MB + 512KB
+0xE8020000      0xE86FFFFF      Linux.uImage (current bank)      7MB + 875KB
+0xE8000000      0xE801FFFF      RCW (current bank)               128KB
+
+
+Various Software configurations/environment variables/commands
+--------------------------------------------------------------
+The below commands apply to T1040QDS
+
+1. U-boot environment variable hwconfig
+   The default hwconfig is:
+	hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=cs0_cs1;usb1:
+					dr_mode=host,phy_type=utmi
+   Note: For USB gadget set "dr_mode=peripheral"
+
+2. FMAN Ucode versions
+   fsl_fman_ucode_t1040.bin
+
+3. Switching to alternate bank
+   Commands for switching to alternate bank.
+
+	1. To change from vbank0 to vbank4
+		=> qixis_reset altbank (it will boot using vbank4)
+
+	2.To change from vbank4 to vbank0
+		=> qixis reset (it will boot using vbank0)
+
+T1040 Personality
+--------------------
+
+T1022 Personality
+--------------------
+T1022 is a reduced personality of T1040 with less core/clusters.
+
+T1042 Personality
+--------------------
+T1042 is a reduced personality of T1040 without Integrated 8-port Gigabit
+Ethernet switch. Rest of the blocks are same as T1040
diff --git a/board/freescale/t1040qds/ddr.c b/board/freescale/t1040qds/ddr.c
new file mode 100644
index 0000000000..da89a36b96
--- /dev/null
+++ b/board/freescale/t1040qds/ddr.c
@@ -0,0 +1,117 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <i2c.h>
+#include <hwconfig.h>
+#include <asm/mmu.h>
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr_dimm_params.h>
+#include <asm/fsl_law.h>
+#include "ddr.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void fsl_ddr_board_options(memctl_options_t *popts,
+				dimm_params_t *pdimm,
+				unsigned int ctrl_num)
+{
+	const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
+	ulong ddr_freq;
+
+	if (ctrl_num > 2) {
+		printf("Not supported controller number %d\n", ctrl_num);
+		return;
+	}
+	if (!pdimm->n_ranks)
+		return;
+
+	pbsp = udimms[0];
+
+	/* Get clk_adjust, cpo, write_data_delay,2t, according to the board ddr
+	 * freqency and n_banks specified in board_specific_parameters table.
+	 */
+	ddr_freq = get_ddr_freq(0) / 1000000;
+	while (pbsp->datarate_mhz_high) {
+		if (pbsp->n_ranks == pdimm->n_ranks &&
+		    (pdimm->rank_density >> 30) >= pbsp->rank_gb) {
+			if (ddr_freq <= pbsp->datarate_mhz_high) {
+				popts->cpo_override = pbsp->cpo;
+				popts->write_data_delay =
+					pbsp->write_data_delay;
+				popts->clk_adjust = pbsp->clk_adjust;
+				popts->wrlvl_start = pbsp->wrlvl_start;
+				popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
+				popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
+				popts->twot_en = pbsp->force_2t;
+				goto found;
+			}
+			pbsp_highest = pbsp;
+		}
+		pbsp++;
+	}
+
+	if (pbsp_highest) {
+		printf("Error: board specific timing not found\n");
+		printf("for data rate %lu MT/s\n", ddr_freq);
+		printf("Trying to use the highest speed (%u) parameters\n",
+		       pbsp_highest->datarate_mhz_high);
+		popts->cpo_override = pbsp_highest->cpo;
+		popts->write_data_delay = pbsp_highest->write_data_delay;
+		popts->clk_adjust = pbsp_highest->clk_adjust;
+		popts->wrlvl_start = pbsp_highest->wrlvl_start;
+		popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
+		popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
+		popts->twot_en = pbsp_highest->force_2t;
+	} else {
+		panic("DIMM is not supported by this board");
+	}
+found:
+	debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n"
+		"\tclk_adjust %d, wrlvl_start %d, wrlvl_ctrl_2 0x%x, "
+		"wrlvl_ctrl_3 0x%x\n",
+		pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb,
+		pbsp->clk_adjust, pbsp->wrlvl_start, pbsp->wrlvl_ctl_2,
+		pbsp->wrlvl_ctl_3);
+
+	/*
+	 * Factors to consider for half-strength driver enable:
+	 *	- number of DIMMs installed
+	 */
+	popts->half_strength_driver_enable = 0;
+	/*
+	 * Write leveling override
+	 */
+	popts->wrlvl_override = 1;
+	popts->wrlvl_sample = 0xf;
+
+	/*
+	 * rtt and rtt_wr override
+	 */
+	popts->rtt_override = 0;
+
+	/* Enable ZQ calibration */
+	popts->zq_en = 1;
+
+	/* DHC_EN =1, ODT = 75 Ohm */
+	popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_75ohm);
+	popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm);
+}
+
+phys_size_t initdram(int board_type)
+{
+	phys_size_t dram_size;
+
+	puts("Initializing....using SPD\n");
+
+	dram_size = fsl_ddr_sdram();
+
+	dram_size = setup_ddr_tlbs(dram_size / 0x100000);
+	dram_size *= 0x100000;
+
+	puts("    DDR: ");
+	return dram_size;
+}
diff --git a/board/freescale/t1040qds/ddr.h b/board/freescale/t1040qds/ddr.h
new file mode 100644
index 0000000000..afa72af26a
--- /dev/null
+++ b/board/freescale/t1040qds/ddr.h
@@ -0,0 +1,52 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __DDR_H__
+#define __DDR_H__
+struct board_specific_parameters {
+	u32 n_ranks;
+	u32 datarate_mhz_high;
+	u32 rank_gb;
+	u32 clk_adjust;
+	u32 wrlvl_start;
+	u32 wrlvl_ctl_2;
+	u32 wrlvl_ctl_3;
+	u32 cpo;
+	u32 write_data_delay;
+	u32 force_2t;
+};
+
+/*
+ * These tables contain all valid speeds we want to override with board
+ * specific parameters. datarate_mhz_high values need to be in ascending order
+ * for each n_ranks group.
+ */
+
+static const struct board_specific_parameters udimm0[] = {
+	/*
+	 * memory controller 0
+	 *   num|  hi| rank|  clk| wrlvl |   wrlvl   |  wrlvl | cpo  |wrdata|2T
+	 * ranks| mhz| GB  |adjst| start |   ctl2    |  ctl3  |      |delay |
+	 */
+	{2,  833,  4, 4,     6, 0x06060607, 0x08080807,   0xff,    2,  0},
+	{2,  833,  0, 4,     6, 0x06060607, 0x08080807,   0xff,    2,  0},
+	{2,  1350, 4, 4,     7, 0x0708080A, 0x0A0B0C09,   0xff,    2,  0},
+	{2,  1350, 0, 4,     7, 0x0708080A, 0x0A0B0C09,   0xff,    2,  0},
+	{2,  1666, 4, 4,     7, 0x0808090B, 0x0C0D0E0A,   0xff,    2,  0},
+	{2,  1666, 0, 4,     7, 0x0808090B, 0x0C0D0E0A,   0xff,    2,  0},
+	{1,  833,  4, 4,     6, 0x06060607, 0x08080807,   0xff,    2,  0},
+	{1,  833,  0, 4,     6, 0x06060607, 0x08080807,   0xff,    2,  0},
+	{1,  1350, 4, 4,     7, 0x0708080A, 0x0A0B0C09,   0xff,    2,  0},
+	{1,  1350, 0, 4,     7, 0x0708080A, 0x0A0B0C09,   0xff,    2,  0},
+	{1,  1666, 4, 4,     7, 0x0808090B, 0x0C0D0E0A,   0xff,    2,  0},
+	{1,  1666, 0, 4,     7, 0x0808090B, 0x0C0D0E0A,   0xff,    2,  0},
+	{}
+};
+
+static const struct board_specific_parameters *udimms[] = {
+	udimm0,
+};
+#endif
diff --git a/board/freescale/t1040qds/diu.c b/board/freescale/t1040qds/diu.c
new file mode 100644
index 0000000000..ffd074b0f8
--- /dev/null
+++ b/board/freescale/t1040qds/diu.c
@@ -0,0 +1,215 @@
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ * Author: Priyanka Jain <Priyanka.Jain@freescale.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <command.h>
+#include <linux/ctype.h>
+#include <asm/io.h>
+#include <stdio_dev.h>
+#include <video_fb.h>
+#include <fsl_diu_fb.h>
+#include "../common/qixis.h"
+#include "t1040qds.h"
+#include "t1040qds_qixis.h"
+#include <i2c.h>
+
+
+#define I2C_DVI_INPUT_DATA_FORMAT_REG		0x1F
+#define I2C_DVI_PLL_CHARGE_CNTL_REG		0x33
+#define I2C_DVI_PLL_DIVIDER_REG			0x34
+#define I2C_DVI_PLL_SUPPLY_CNTL_REG		0x35
+#define I2C_DVI_PLL_FILTER_REG			0x36
+#define I2C_DVI_TEST_PATTERN_REG		0x48
+#define I2C_DVI_POWER_MGMT_REG			0x49
+#define I2C_DVI_LOCK_STATE_REG			0x4D
+#define I2C_DVI_SYNC_POLARITY_REG		0x56
+
+/*
+ * Set VSYNC/HSYNC to active high. This is polarity of sync signals
+ * from DIU->DVI. The DIU default is active igh, so DVI is set to
+ * active high.
+ */
+#define I2C_DVI_INPUT_DATA_FORMAT_VAL		0x98
+
+#define I2C_DVI_PLL_CHARGE_CNTL_HIGH_SPEED_VAL	0x06
+#define I2C_DVI_PLL_DIVIDER_HIGH_SPEED_VAL	0x26
+#define I2C_DVI_PLL_FILTER_HIGH_SPEED_VAL	0xA0
+#define I2C_DVI_PLL_CHARGE_CNTL_LOW_SPEED_VAL	0x08
+#define I2C_DVI_PLL_DIVIDER_LOW_SPEED_VAL	0x16
+#define I2C_DVI_PLL_FILTER_LOW_SPEED_VAL	0x60
+
+/* Clear test pattern */
+#define I2C_DVI_TEST_PATTERN_VAL		0x18
+/* Exit Power-down mode */
+#define I2C_DVI_POWER_MGMT_VAL			0xC0
+
+/* Monitor polarity is handled via DVI Sync Polarity Register */
+#define I2C_DVI_SYNC_POLARITY_VAL		0x00
+
+/*
+ * DIU Area Descriptor
+ *
+ * Note that we need to byte-swap the value before it's written to the AD
+ * register.  So even though the registers don't look like they're in the same
+ * bit positions as they are on the MPC8610, the same value is written to the
+ * AD register on the MPC8610 and on the P1022.
+ */
+#define AD_BYTE_F		0x10000000
+#define AD_ALPHA_C_SHIFT	25
+#define AD_BLUE_C_SHIFT		23
+#define AD_GREEN_C_SHIFT	21
+#define AD_RED_C_SHIFT		19
+#define AD_PIXEL_S_SHIFT	16
+#define AD_COMP_3_SHIFT		12
+#define AD_COMP_2_SHIFT		8
+#define AD_COMP_1_SHIFT		4
+#define AD_COMP_0_SHIFT		0
+
+/* Programming of HDMI Chrontel CH7301 connector */
+int diu_set_dvi_encoder(unsigned int pixclock)
+{
+	int ret;
+	u8 temp;
+	select_i2c_ch_pca9547(I2C_MUX_CH_DIU);
+
+	temp = I2C_DVI_TEST_PATTERN_VAL;
+	ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR, I2C_DVI_TEST_PATTERN_REG, 1,
+			&temp, 1);
+	if (ret) {
+		puts("I2C: failed to select proper dvi test pattern\n");
+		return ret;
+	}
+	temp = I2C_DVI_INPUT_DATA_FORMAT_VAL;
+	ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR, I2C_DVI_INPUT_DATA_FORMAT_REG,
+			1, &temp, 1);
+	if (ret) {
+		puts("I2C: failed to select dvi input data format\n");
+		return ret;
+	}
+
+	/* Set Sync polarity register */
+	temp = I2C_DVI_SYNC_POLARITY_VAL;
+	ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR, I2C_DVI_SYNC_POLARITY_REG, 1,
+			&temp, 1);
+	if (ret) {
+		puts("I2C: failed to select dvi syc polarity\n");
+		return ret;
+	}
+
+	/* Set PLL registers based on pixel clock rate*/
+	if (pixclock > 65000000) {
+		temp = I2C_DVI_PLL_CHARGE_CNTL_HIGH_SPEED_VAL;
+		ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR,
+				I2C_DVI_PLL_CHARGE_CNTL_REG, 1,	&temp, 1);
+		if (ret) {
+			puts("I2C: failed to select dvi pll charge_cntl\n");
+			return ret;
+		}
+		temp = I2C_DVI_PLL_DIVIDER_HIGH_SPEED_VAL;
+		ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR,
+				I2C_DVI_PLL_DIVIDER_REG, 1, &temp, 1);
+		if (ret) {
+			puts("I2C: failed to select dvi pll divider\n");
+			return ret;
+		}
+		temp = I2C_DVI_PLL_FILTER_HIGH_SPEED_VAL;
+		ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR,
+				I2C_DVI_PLL_FILTER_REG, 1, &temp, 1);
+		if (ret) {
+			puts("I2C: failed to select dvi pll filter\n");
+			return ret;
+		}
+	} else {
+		temp = I2C_DVI_PLL_CHARGE_CNTL_LOW_SPEED_VAL;
+		ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR,
+				I2C_DVI_PLL_CHARGE_CNTL_REG, 1, &temp, 1);
+		if (ret) {
+			puts("I2C: failed to select dvi pll charge_cntl\n");
+			return ret;
+		}
+		temp = I2C_DVI_PLL_DIVIDER_LOW_SPEED_VAL;
+		ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR,
+				I2C_DVI_PLL_DIVIDER_REG, 1, &temp, 1);
+		if (ret) {
+			puts("I2C: failed to select dvi pll divider\n");
+			return ret;
+		}
+		temp = I2C_DVI_PLL_FILTER_LOW_SPEED_VAL;
+		ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR,
+				I2C_DVI_PLL_FILTER_REG, 1, &temp, 1);
+		if (ret) {
+			puts("I2C: failed to select dvi pll filter\n");
+			return ret;
+		}
+	}
+
+	temp = I2C_DVI_POWER_MGMT_VAL;
+	ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR, I2C_DVI_POWER_MGMT_REG, 1,
+			&temp, 1);
+	if (ret) {
+		puts("I2C: failed to select dvi power mgmt\n");
+		return ret;
+	}
+
+	udelay(500);
+
+	select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
+	return 0;
+}
+
+void diu_set_pixel_clock(unsigned int pixclock)
+{
+	unsigned long speed_ccb, temp;
+	u32 pixval;
+	int ret = 0;
+	speed_ccb = get_bus_freq(0);
+	temp = 1000000000 / pixclock;
+	temp *= 1000;
+	pixval = speed_ccb / temp;
+
+	/* Program HDMI encoder */
+	ret = diu_set_dvi_encoder(temp);
+	if (ret) {
+		puts("Failed to set DVI encoder\n");
+		return;
+	}
+
+	/* Program pixel clock */
+	out_be32((unsigned *)CONFIG_SYS_FSL_SCFG_PIXCLK_ADDR,
+		 ((pixval << PXCK_BITS_START) & PXCK_MASK));
+	/* enable clock*/
+	out_be32((unsigned *)CONFIG_SYS_FSL_SCFG_PIXCLK_ADDR, PXCKEN_MASK |
+		 ((pixval << PXCK_BITS_START) & PXCK_MASK));
+}
+
+int platform_diu_init(unsigned int xres, unsigned int yres, const char *port)
+{
+	u32 pixel_format;
+	u8 sw;
+
+	/*Route I2C4 to DIU system as HSYNC/VSYNC*/
+	sw = QIXIS_READ(brdcfg[5]);
+	QIXIS_WRITE(brdcfg[5],
+		    ((sw & ~(BRDCFG5_IMX_MASK)) | (BRDCFG5_IMX_DIU)));
+
+	/*Configure Display ouput port as HDMI*/
+	sw = QIXIS_READ(brdcfg[15]);
+	QIXIS_WRITE(brdcfg[15],
+		    ((sw & ~(BRDCFG15_LCDPD_MASK | BRDCFG15_DIUSEL_MASK))
+		      | (BRDCFG15_LCDPD_ENABLED | BRDCFG15_DIUSEL_HDMI)));
+
+	pixel_format = cpu_to_le32(AD_BYTE_F | (3 << AD_ALPHA_C_SHIFT) |
+		(0 << AD_BLUE_C_SHIFT) | (1 << AD_GREEN_C_SHIFT) |
+		(2 << AD_RED_C_SHIFT) | (8 << AD_COMP_3_SHIFT) |
+		(8 << AD_COMP_2_SHIFT) | (8 << AD_COMP_1_SHIFT) |
+		(8 << AD_COMP_0_SHIFT) | (3 << AD_PIXEL_S_SHIFT));
+
+	printf("DIU:   Switching to monitor @ %ux%u\n",  xres, yres);
+
+
+	return fsl_diu_init(xres, yres, pixel_format, 0);
+}
diff --git a/board/freescale/t1040qds/eth.c b/board/freescale/t1040qds/eth.c
new file mode 100644
index 0000000000..3077b4ae2c
--- /dev/null
+++ b/board/freescale/t1040qds/eth.c
@@ -0,0 +1,492 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * The RGMII PHYs are provided by the two on-board PHY connected to
+ * dTSEC instances 4 and 5. The SGMII PHYs are provided by one on-board
+ * PHY or by the standard four-port SGMII riser card (VSC).
+ */
+
+#include <common.h>
+#include <netdev.h>
+#include <asm/fsl_serdes.h>
+#include <asm/immap_85xx.h>
+#include <fm_eth.h>
+#include <fsl_mdio.h>
+#include <malloc.h>
+#include <asm/fsl_dtsec.h>
+
+#include "../common/fman.h"
+#include "../common/qixis.h"
+
+#include "t1040qds_qixis.h"
+
+#ifdef CONFIG_FMAN_ENET
+ /* - In T1040 there are only 8 SERDES lanes, spread across 2 SERDES banks.
+ *   Bank 1 -> Lanes A, B, C, D
+ *   Bank 2 -> Lanes E, F, G, H
+ */
+
+ /* Mapping of 8 SERDES lanes to T1040 QDS board slots. A value of '0' here
+  * means that the mapping must be determined dynamically, or that the lane
+  * maps to something other than a board slot.
+  */
+static u8 lane_to_slot[] = {
+	0, 0, 0, 0, 0, 0, 0, 0
+};
+
+/* On the Vitesse VSC8234XHG SGMII riser card there are 4 SGMII PHYs
+ * housed.
+ */
+static int riser_phy_addr[] = {
+	CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR,
+	CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR,
+	CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR,
+	CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR,
+};
+
+/* Slot2 does not have EMI connections */
+#define EMI_NONE	0xFFFFFFFF
+#define EMI1_RGMII0	0
+#define EMI1_RGMII1	1
+#define EMI1_SLOT1	2
+#define EMI1_SLOT3	3
+#define EMI1_SLOT4	4
+#define EMI1_SLOT5	5
+#define EMI1_SLOT6	6
+#define EMI1_SLOT7	7
+#define EMI2		8
+
+static int mdio_mux[NUM_FM_PORTS];
+
+static const char * const mdio_names[] = {
+	"T1040_QDS_MDIO0",
+	"T1040_QDS_MDIO1",
+	"T1040_QDS_MDIO2",
+	"T1040_QDS_MDIO3",
+	"T1040_QDS_MDIO4",
+	"T1040_QDS_MDIO5",
+	"T1040_QDS_MDIO6",
+	"T1040_QDS_MDIO7",
+};
+
+struct t1040_qds_mdio {
+	u8 muxval;
+	struct mii_dev *realbus;
+};
+
+static const char *t1040_qds_mdio_name_for_muxval(u8 muxval)
+{
+	return mdio_names[muxval];
+}
+
+struct mii_dev *mii_dev_for_muxval(u8 muxval)
+{
+	struct mii_dev *bus;
+	const char *name = t1040_qds_mdio_name_for_muxval(muxval);
+
+	if (!name) {
+		printf("No bus for muxval %x\n", muxval);
+		return NULL;
+	}
+
+	bus = miiphy_get_dev_by_name(name);
+
+	if (!bus) {
+		printf("No bus by name %s\n", name);
+		return NULL;
+	}
+
+	return bus;
+}
+
+static void t1040_qds_mux_mdio(u8 muxval)
+{
+	u8 brdcfg4;
+	if (muxval <= 7) {
+		brdcfg4 = QIXIS_READ(brdcfg[4]);
+		brdcfg4 &= ~BRDCFG4_EMISEL_MASK;
+		brdcfg4 |= (muxval << BRDCFG4_EMISEL_SHIFT);
+		QIXIS_WRITE(brdcfg[4], brdcfg4);
+	}
+}
+
+static int t1040_qds_mdio_read(struct mii_dev *bus, int addr, int devad,
+				int regnum)
+{
+	struct t1040_qds_mdio *priv = bus->priv;
+
+	t1040_qds_mux_mdio(priv->muxval);
+
+	return priv->realbus->read(priv->realbus, addr, devad, regnum);
+}
+
+static int t1040_qds_mdio_write(struct mii_dev *bus, int addr, int devad,
+				int regnum, u16 value)
+{
+	struct t1040_qds_mdio *priv = bus->priv;
+
+	t1040_qds_mux_mdio(priv->muxval);
+
+	return priv->realbus->write(priv->realbus, addr, devad, regnum, value);
+}
+
+static int t1040_qds_mdio_reset(struct mii_dev *bus)
+{
+	struct t1040_qds_mdio *priv = bus->priv;
+
+	return priv->realbus->reset(priv->realbus);
+}
+
+static int t1040_qds_mdio_init(char *realbusname, u8 muxval)
+{
+	struct t1040_qds_mdio *pmdio;
+	struct mii_dev *bus = mdio_alloc();
+
+	if (!bus) {
+		printf("Failed to allocate t1040_qds MDIO bus\n");
+		return -1;
+	}
+
+	pmdio = malloc(sizeof(*pmdio));
+	if (!pmdio) {
+		printf("Failed to allocate t1040_qds private data\n");
+		free(bus);
+		return -1;
+	}
+
+	bus->read = t1040_qds_mdio_read;
+	bus->write = t1040_qds_mdio_write;
+	bus->reset = t1040_qds_mdio_reset;
+	sprintf(bus->name, t1040_qds_mdio_name_for_muxval(muxval));
+
+	pmdio->realbus = miiphy_get_dev_by_name(realbusname);
+
+	if (!pmdio->realbus) {
+		printf("No bus with name %s\n", realbusname);
+		free(bus);
+		free(pmdio);
+		return -1;
+	}
+
+	pmdio->muxval = muxval;
+	bus->priv = pmdio;
+
+	return mdio_register(bus);
+}
+
+/*
+ * Initialize the lane_to_slot[] array.
+ *
+ * On the T1040QDS board the mapping is controlled by ?? register.
+ */
+static void initialize_lane_to_slot(void)
+{
+	ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
+	int serdes1_prtcl = (in_be32(&gur->rcwsr[4]) &
+				FSL_CORENET2_RCWSR4_SRDS1_PRTCL)
+		>> FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
+
+	QIXIS_WRITE(cms[0], 0x07);
+
+	switch (serdes1_prtcl) {
+	case 0x60:
+	case 0x66:
+	case 0x67:
+	case 0x69:
+		lane_to_slot[1] = 7;
+		lane_to_slot[2] = 6;
+		lane_to_slot[3] = 5;
+		break;
+	case 0x86:
+		lane_to_slot[1] = 7;
+		lane_to_slot[2] = 7;
+		lane_to_slot[3] = 7;
+		break;
+	case 0x87:
+		lane_to_slot[1] = 7;
+		lane_to_slot[2] = 7;
+		lane_to_slot[3] = 7;
+		lane_to_slot[7] = 7;
+		break;
+	case 0x89:
+		lane_to_slot[1] = 7;
+		lane_to_slot[2] = 7;
+		lane_to_slot[3] = 7;
+		lane_to_slot[7] = 7;
+		break;
+	case 0x8d:
+		lane_to_slot[1] = 7;
+		lane_to_slot[2] = 7;
+		lane_to_slot[3] = 7;
+		lane_to_slot[5] = 3;
+		lane_to_slot[6] = 3;
+		lane_to_slot[7] = 3;
+		break;
+	case 0x8F:
+	case 0x85:
+		lane_to_slot[1] = 7;
+		lane_to_slot[2] = 6;
+		lane_to_slot[3] = 5;
+		lane_to_slot[6] = 3;
+		lane_to_slot[7] = 3;
+		break;
+	case 0xA5:
+		lane_to_slot[1] = 7;
+		lane_to_slot[6] = 3;
+		lane_to_slot[7] = 3;
+		break;
+	case 0xA7:
+		lane_to_slot[1] = 7;
+		lane_to_slot[7] = 7;
+		break;
+	case 0xAA:
+		lane_to_slot[1] = 7;
+		lane_to_slot[6] = 7;
+		lane_to_slot[7] = 7;
+		break;
+	case 0x40:
+		lane_to_slot[2] = 7;
+		lane_to_slot[3] = 7;
+		break;
+	default:
+		printf("qds: Fman: Unsupported SerDes Protocol 0x%02x\n",
+		       serdes1_prtcl);
+		break;
+	}
+}
+
+/*
+ * Given the following ...
+ *
+ * 1) A pointer to an Fman Ethernet node (as identified by the 'compat'
+ * compatible string and 'addr' physical address)
+ *
+ * 2) An Fman port
+ *
+ * ... update the phy-handle property of the Ethernet node to point to the
+ * right PHY. This assumes that we already know the PHY for each port.
+ *
+ * The offset of the Fman Ethernet node is also passed in for convenience, but
+ * it is not used, and we recalculate the offset anyway.
+ *
+ * Note that what we call "Fman ports" (enum fm_port) is really an Fman MAC.
+ * Inside the Fman, "ports" are things that connect to MACs. We only call them
+ * ports in U-Boot because on previous Ethernet devices (e.g. Gianfar), MACs
+ * and ports are the same thing.
+ *
+ */
+void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr,
+			      enum fm_port port, int offset)
+{
+	phy_interface_t intf = fm_info_get_enet_if(port);
+	char phy[16];
+
+	/* The RGMII PHY is identified by the MAC connected to it */
+	if (intf == PHY_INTERFACE_MODE_RGMII) {
+		sprintf(phy, "rgmii_phy%u", port == FM1_DTSEC4 ? 1 : 2);
+		fdt_set_phy_handle(fdt, compat, addr, phy);
+	}
+
+	/* The SGMII PHY is identified by the MAC connected to it */
+	if (intf == PHY_INTERFACE_MODE_SGMII) {
+		int lane = serdes_get_first_lane(FSL_SRDS_1, SGMII_FM1_DTSEC1
+						 + port);
+		u8 slot;
+		if (lane < 0)
+			return;
+		slot = lane_to_slot[lane];
+		if (slot) {
+			/* Slot housing a SGMII riser card */
+			sprintf(phy, "phy_s%x_%02x", slot,
+				(fm_info_get_phy_address(port - FM1_DTSEC1)-
+				CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR + 1));
+			fdt_set_phy_handle(fdt, compat, addr, phy);
+		}
+	}
+}
+
+void fdt_fixup_board_enet(void *fdt)
+{
+	int i, lane, idx;
+
+	for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
+		idx = i - FM1_DTSEC1;
+		switch (fm_info_get_enet_if(i)) {
+		case PHY_INTERFACE_MODE_SGMII:
+			lane = serdes_get_first_lane(FSL_SRDS_1,
+						     SGMII_FM1_DTSEC1 + idx);
+			if (lane < 0)
+				break;
+
+			switch (mdio_mux[i]) {
+			case EMI1_SLOT3:
+				fdt_status_okay_by_alias(fdt, "emi1_slot3");
+				break;
+			case EMI1_SLOT5:
+				fdt_status_okay_by_alias(fdt, "emi1_slot5");
+				break;
+			case EMI1_SLOT6:
+				fdt_status_okay_by_alias(fdt, "emi1_slot6");
+				break;
+			case EMI1_SLOT7:
+				fdt_status_okay_by_alias(fdt, "emi1_slot7");
+				break;
+			}
+		break;
+		case PHY_INTERFACE_MODE_RGMII:
+			if (i == FM1_DTSEC4)
+				fdt_status_okay_by_alias(fdt, "emi1_rgmii0");
+
+			if (i == FM1_DTSEC5)
+				fdt_status_okay_by_alias(fdt, "emi1_rgmii1");
+			break;
+		default:
+			break;
+		}
+	}
+}
+#endif /* #ifdef CONFIG_FMAN_ENET */
+
+static void set_brdcfg9_for_gtx_clk(void)
+{
+	u8 brdcfg9;
+	brdcfg9 = QIXIS_READ(brdcfg[9]);
+	brdcfg9 |= (1 << 5);
+	QIXIS_WRITE(brdcfg[9], brdcfg9);
+}
+
+void t1040_handle_phy_interface_sgmii(int i)
+{
+	int lane, idx, slot;
+	idx = i - FM1_DTSEC1;
+	lane = serdes_get_first_lane(FSL_SRDS_1,
+			SGMII_FM1_DTSEC1 + idx);
+
+	if (lane < 0)
+		return;
+	slot = lane_to_slot[lane];
+
+	switch (slot) {
+	case 1:
+		mdio_mux[i] = EMI1_SLOT1;
+		fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
+		break;
+	case 3:
+		if (FM1_DTSEC4 == i)
+			fm_info_set_phy_address(i, riser_phy_addr[0]);
+		if (FM1_DTSEC5 == i)
+			fm_info_set_phy_address(i, riser_phy_addr[1]);
+
+		mdio_mux[i] = EMI1_SLOT3;
+
+		fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
+		break;
+	case 4:
+		mdio_mux[i] = EMI1_SLOT4;
+		fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
+		break;
+	case 5:
+		/* Slot housing a SGMII riser card? */
+		fm_info_set_phy_address(i, riser_phy_addr[0]);
+		mdio_mux[i] = EMI1_SLOT5;
+		fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
+		break;
+	case 6:
+		/* Slot housing a SGMII riser card? */
+		fm_info_set_phy_address(i, riser_phy_addr[0]);
+		mdio_mux[i] = EMI1_SLOT6;
+		fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
+		break;
+	case 7:
+		if (FM1_DTSEC1 == i)
+			fm_info_set_phy_address(i, riser_phy_addr[0]);
+		if (FM1_DTSEC2 == i)
+			fm_info_set_phy_address(i, riser_phy_addr[1]);
+		if (FM1_DTSEC3 == i)
+			fm_info_set_phy_address(i, riser_phy_addr[2]);
+
+		mdio_mux[i] = EMI1_SLOT7;
+		fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
+		break;
+	default:
+		break;
+	}
+	fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
+}
+void t1040_handle_phy_interface_rgmii(int i)
+{
+	fm_info_set_phy_address(i, i == FM1_DTSEC5 ?
+			CONFIG_SYS_FM1_DTSEC5_PHY_ADDR :
+			CONFIG_SYS_FM1_DTSEC4_PHY_ADDR);
+	mdio_mux[i] = (i == FM1_DTSEC5) ? EMI1_RGMII1 :
+		EMI1_RGMII0;
+	fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
+}
+
+int board_eth_init(bd_t *bis)
+{
+#ifdef CONFIG_FMAN_ENET
+	struct memac_mdio_info memac_mdio_info;
+	unsigned int i;
+
+	printf("Initializing Fman\n");
+	set_brdcfg9_for_gtx_clk();
+
+	initialize_lane_to_slot();
+
+	/* Initialize the mdio_mux array so we can recognize empty elements */
+	for (i = 0; i < NUM_FM_PORTS; i++)
+		mdio_mux[i] = EMI_NONE;
+
+	memac_mdio_info.regs =
+		(struct memac_mdio_controller *)CONFIG_SYS_FM1_DTSEC_MDIO_ADDR;
+	memac_mdio_info.name = DEFAULT_FM_MDIO_NAME;
+
+	/* Register the real 1G MDIO bus */
+	fm_memac_mdio_init(bis, &memac_mdio_info);
+
+	/* Register the muxing front-ends to the MDIO buses */
+	t1040_qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII0);
+	t1040_qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII1);
+	t1040_qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT1);
+	t1040_qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT3);
+	t1040_qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT4);
+	t1040_qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT5);
+	t1040_qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT6);
+	t1040_qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT7);
+
+	/*
+	 * Program on board RGMII PHY addresses. If the SGMII Riser
+	 * card used, we'll override the PHY address later. For any DTSEC that
+	 * is RGMII, we'll also override its PHY address later. We assume that
+	 * DTSEC4 and DTSEC5 are used for RGMII.
+	 */
+	fm_info_set_phy_address(FM1_DTSEC4, CONFIG_SYS_FM1_DTSEC4_PHY_ADDR);
+	fm_info_set_phy_address(FM1_DTSEC5, CONFIG_SYS_FM1_DTSEC5_PHY_ADDR);
+
+	for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
+		switch (fm_info_get_enet_if(i)) {
+		case PHY_INTERFACE_MODE_QSGMII:
+			break;
+		case PHY_INTERFACE_MODE_SGMII:
+			t1040_handle_phy_interface_sgmii(i);
+			break;
+
+		case PHY_INTERFACE_MODE_RGMII:
+			/* Only DTSEC4 and DTSEC5 can be routed to RGMII */
+			t1040_handle_phy_interface_rgmii(i);
+			break;
+		default:
+			break;
+		}
+	}
+
+	cpu_eth_init(bis);
+#endif
+
+	return pci_eth_init(bis);
+}
diff --git a/board/freescale/t1040qds/law.c b/board/freescale/t1040qds/law.c
new file mode 100644
index 0000000000..a2dc027e4b
--- /dev/null
+++ b/board/freescale/t1040qds/law.c
@@ -0,0 +1,32 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/fsl_law.h>
+#include <asm/mmu.h>
+
+struct law_entry law_table[] = {
+#ifndef CONFIG_SYS_NO_FLASH
+	SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_IFC),
+#endif
+#ifdef CONFIG_SYS_BMAN_MEM_PHYS
+	SET_LAW(CONFIG_SYS_BMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_BMAN),
+#endif
+#ifdef CONFIG_SYS_QMAN_MEM_PHYS
+	SET_LAW(CONFIG_SYS_QMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_QMAN),
+#endif
+#ifdef QIXIS_BASE_PHYS
+	SET_LAW(QIXIS_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_IFC),
+#endif
+#ifdef CONFIG_SYS_DCSRBAR_PHYS
+	SET_LAW(CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_4M, LAW_TRGT_IF_DCSR),
+#endif
+#ifdef CONFIG_SYS_NAND_BASE_PHYS
+	SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_IFC),
+#endif
+};
+
+int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/board/freescale/t1040qds/pci.c b/board/freescale/t1040qds/pci.c
new file mode 100644
index 0000000000..c53e3b76a4
--- /dev/null
+++ b/board/freescale/t1040qds/pci.c
@@ -0,0 +1,23 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <command.h>
+#include <pci.h>
+#include <asm/fsl_pci.h>
+#include <libfdt.h>
+#include <fdt_support.h>
+#include <asm/fsl_serdes.h>
+
+void pci_init_board(void)
+{
+	fsl_pcie_init_board(0);
+}
+
+void pci_of_setup(void *blob, bd_t *bd)
+{
+	FT_FSL_PCI_SETUP;
+}
diff --git a/board/freescale/t1040qds/t1040_pbi.cfg b/board/freescale/t1040qds/t1040_pbi.cfg
new file mode 100644
index 0000000000..10b1a6d179
--- /dev/null
+++ b/board/freescale/t1040qds/t1040_pbi.cfg
@@ -0,0 +1,27 @@
+#PBI commands
+#Initialize CPC1
+09010000 00200400
+09138000 00000000
+091380c0 00000100
+#Configure CPC1 as 256KB SRAM
+09010100 00000000
+09010104 fffc0007
+09010f00 08000000
+09010000 80000000
+#Configure LAW for CPC1
+09000cf0 00000000
+09000cf4 fffc0000
+09000cf8 81000011
+#Configure alternate space
+09000010 00000000
+09000014 ff000000
+09000018 81000000
+#Configure SPI controller
+09110000 80000403
+09110020 2d170008
+09110024 00100008
+09110028 00100008
+0911002c 00100008
+#Flush PBL data
+09138000 00000000
+091380c0 00000000
diff --git a/board/freescale/t1040qds/t1040_rcw.cfg b/board/freescale/t1040qds/t1040_rcw.cfg
new file mode 100644
index 0000000000..0d0dfa5a46
--- /dev/null
+++ b/board/freescale/t1040qds/t1040_rcw.cfg
@@ -0,0 +1,7 @@
+#PBL preamble and RCW header
+aa55aa55 010e0100
+# serdes protocol 0x66
+0a10000c 0c000000 00000000 00000000
+66000002 00000000 fc027000 01000000
+00000000 00000000 00000000 00030810
+00000000 03fc500f 00000000 00000000
diff --git a/board/freescale/t1040qds/t1040qds.c b/board/freescale/t1040qds/t1040qds.c
new file mode 100644
index 0000000000..3dec4473e5
--- /dev/null
+++ b/board/freescale/t1040qds/t1040qds.c
@@ -0,0 +1,247 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <command.h>
+#include <i2c.h>
+#include <netdev.h>
+#include <linux/compiler.h>
+#include <asm/mmu.h>
+#include <asm/processor.h>
+#include <asm/cache.h>
+#include <asm/immap_85xx.h>
+#include <asm/fsl_law.h>
+#include <asm/fsl_serdes.h>
+#include <asm/fsl_portals.h>
+#include <asm/fsl_liodn.h>
+#include <fm_eth.h>
+
+#include "../common/qixis.h"
+#include "t1040qds.h"
+#include "t1040qds_qixis.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int checkboard(void)
+{
+	char buf[64];
+	u8 sw;
+	struct cpu_type *cpu = gd->arch.cpu;
+	static const char *const freq[] = {"100", "125", "156.25", "161.13",
+						"122.88", "122.88", "122.88"};
+	int clock;
+
+	printf("Board: %sQDS, ", cpu->name);
+	printf("Sys ID: 0x%02x, Sys Ver: 0x%02x, ",
+	       QIXIS_READ(id), QIXIS_READ(arch));
+
+	sw = QIXIS_READ(brdcfg[0]);
+	sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
+
+	if (sw < 0x8)
+		printf("vBank: %d\n", sw);
+	else if (sw == 0x8)
+		puts("PromJet\n");
+	else if (sw == 0x9)
+		puts("NAND\n");
+	else if (sw == 0x15)
+		printf("IFCCard\n");
+	else
+		printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
+
+	printf("FPGA: v%d (%s), build %d",
+	       (int)QIXIS_READ(scver), qixis_read_tag(buf),
+	       (int)qixis_read_minor());
+	/* the timestamp string contains "\n" at the end */
+	printf(" on %s", qixis_read_time(buf));
+
+	/*
+	 * Display the actual SERDES reference clocks as configured by the
+	 * dip switches on the board.  Note that the SWx registers could
+	 * technically be set to force the reference clocks to match the
+	 * values that the SERDES expects (or vice versa).  For now, however,
+	 * we just display both values and hope the user notices when they
+	 * don't match.
+	 */
+	puts("SERDES Reference: ");
+	sw = QIXIS_READ(brdcfg[2]);
+	clock = (sw >> 6) & 3;
+	printf("Clock1=%sMHz ", freq[clock]);
+	clock = (sw >> 4) & 3;
+	printf("Clock2=%sMHz\n", freq[clock]);
+
+	return 0;
+}
+
+int select_i2c_ch_pca9547(u8 ch)
+{
+	int ret;
+
+	ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
+	if (ret) {
+		puts("PCA: failed to select proper channel\n");
+		return ret;
+	}
+
+	return 0;
+}
+
+int board_early_init_r(void)
+{
+#ifdef CONFIG_SYS_FLASH_BASE
+	const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
+	const u8 flash_esel = find_tlb_idx((void *)flashbase, 1);
+
+	/*
+	 * Remap Boot flash + PROMJET region to caching-inhibited
+	 * so that flash can be erased properly.
+	 */
+
+	/* Flush d-cache and invalidate i-cache of any FLASH data */
+	flush_dcache();
+	invalidate_icache();
+
+	/* invalidate existing TLB entry for flash + promjet */
+	disable_tlb(flash_esel);
+
+	set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
+		MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		0, flash_esel, BOOKE_PAGESZ_256M, 1);
+#endif
+	set_liodns();
+#ifdef CONFIG_SYS_DPAA_QBMAN
+	setup_portals();
+#endif
+	select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
+
+	return 0;
+}
+
+unsigned long get_board_sys_clk(void)
+{
+	u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
+
+	switch (sysclk_conf & 0x0F) {
+	case QIXIS_SYSCLK_64:
+		return 64000000;
+	case QIXIS_SYSCLK_83:
+		return 83333333;
+	case QIXIS_SYSCLK_100:
+		return 100000000;
+	case QIXIS_SYSCLK_125:
+		return 125000000;
+	case QIXIS_SYSCLK_133:
+		return 133333333;
+	case QIXIS_SYSCLK_150:
+		return 150000000;
+	case QIXIS_SYSCLK_160:
+		return 160000000;
+	case QIXIS_SYSCLK_166:
+		return 166666666;
+	}
+	return 66666666;
+}
+
+unsigned long get_board_ddr_clk(void)
+{
+	u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
+
+	switch ((ddrclk_conf & 0x30) >> 4) {
+	case QIXIS_DDRCLK_100:
+		return 100000000;
+	case QIXIS_DDRCLK_125:
+		return 125000000;
+	case QIXIS_DDRCLK_133:
+		return 133333333;
+	}
+	return 66666666;
+}
+
+#define NUM_SRDS_BANKS	2
+int misc_init_r(void)
+{
+	u8 sw;
+	serdes_corenet_t *srds_regs =
+		(void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
+	u32 actual[NUM_SRDS_BANKS] = { 0 };
+	int i;
+
+	sw = QIXIS_READ(brdcfg[2]);
+	for (i = 0; i < NUM_SRDS_BANKS; i++) {
+		unsigned int clock = (sw >> (6 - 2 * i)) & 3;
+		switch (clock) {
+		case 0:
+			actual[i] = SRDS_PLLCR0_RFCK_SEL_100;
+			break;
+		case 1:
+			actual[i] = SRDS_PLLCR0_RFCK_SEL_125;
+			break;
+		case 2:
+			actual[i] = SRDS_PLLCR0_RFCK_SEL_156_25;
+			break;
+		}
+	}
+
+	puts("SerDes1");
+	for (i = 0; i < NUM_SRDS_BANKS; i++) {
+		u32 pllcr0 = srds_regs->bank[i].pllcr0;
+		u32 expected = pllcr0 & SRDS_PLLCR0_RFCK_SEL_MASK;
+		if (expected != actual[i]) {
+			printf("expects ref clk%d %sMHz, but actual is %sMHz\n",
+			       i + 1, serdes_clock_to_string(expected),
+			       serdes_clock_to_string(actual[i]));
+		}
+	}
+
+	return 0;
+}
+
+void ft_board_setup(void *blob, bd_t *bd)
+{
+	phys_addr_t base;
+	phys_size_t size;
+
+	ft_cpu_setup(blob, bd);
+
+	base = getenv_bootm_low();
+	size = getenv_bootm_size();
+
+	fdt_fixup_memory(blob, (u64)base, (u64)size);
+
+#ifdef CONFIG_PCI
+	pci_of_setup(blob, bd);
+#endif
+
+	fdt_fixup_liodn(blob);
+
+#ifdef CONFIG_HAS_FSL_DR_USB
+	fdt_fixup_dr_usb(blob, bd);
+#endif
+
+#ifdef CONFIG_SYS_DPAA_FMAN
+	fdt_fixup_fman_ethernet(blob);
+	fdt_fixup_board_enet(blob);
+#endif
+}
+
+void qixis_dump_switch(void)
+{
+	int i, nr_of_cfgsw;
+
+	QIXIS_WRITE(cms[0], 0x00);
+	nr_of_cfgsw = QIXIS_READ(cms[1]);
+
+	puts("DIP switch settings dump:\n");
+	for (i = 1; i <= nr_of_cfgsw; i++) {
+		QIXIS_WRITE(cms[0], i);
+		printf("SW%d = (0x%02x)\n", i, QIXIS_READ(cms[1]));
+	}
+}
+
+int board_need_mem_reset(void)
+{
+	return 1;
+}
diff --git a/board/freescale/t1040qds/t1040qds.h b/board/freescale/t1040qds/t1040qds.h
new file mode 100644
index 0000000000..5041f379de
--- /dev/null
+++ b/board/freescale/t1040qds/t1040qds.h
@@ -0,0 +1,14 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __T1040_QDS_H__
+#define __T1040_QDS_H__
+
+void fdt_fixup_board_enet(void *blob);
+void pci_of_setup(void *blob, bd_t *bd);
+int select_i2c_ch_pca9547(u8 ch);
+
+#endif
diff --git a/board/freescale/t1040qds/t1040qds_qixis.h b/board/freescale/t1040qds/t1040qds_qixis.h
new file mode 100644
index 0000000000..98d2d39e6d
--- /dev/null
+++ b/board/freescale/t1040qds/t1040qds_qixis.h
@@ -0,0 +1,48 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __T1040QDS_QIXIS_H__
+#define __T1040QDS_QIXIS_H__
+
+/* Definitions of QIXIS Registers for T1040QDS */
+
+/* BRDCFG4[4:7]] select EC1 and EC2 as a pair */
+#define BRDCFG4_EMISEL_MASK		0xE0
+#define BRDCFG4_EMISEL_SHIFT		5
+
+/* BRDCFG5[0:1] controls routing and use of I2C3 & I2C4 ports*/
+#define BRDCFG5_IMX_MASK		0xC0
+#define BRDCFG5_IMX_DIU			0x80
+
+/* BRDCFG15[3] controls LCD Panel Powerdown*/
+#define BRDCFG15_LCDPD_MASK		0x10
+#define BRDCFG15_LCDPD_ENABLED		0x00
+
+/* BRDCFG15[6:7] controls DIU MUX selction*/
+#define BRDCFG15_DIUSEL_MASK		0x03
+#define BRDCFG15_DIUSEL_HDMI		0x00
+
+/* SYSCLK */
+#define QIXIS_SYSCLK_66			0x0
+#define QIXIS_SYSCLK_83			0x1
+#define QIXIS_SYSCLK_100		0x2
+#define QIXIS_SYSCLK_125		0x3
+#define QIXIS_SYSCLK_133		0x4
+#define QIXIS_SYSCLK_150		0x5
+#define QIXIS_SYSCLK_160		0x6
+#define QIXIS_SYSCLK_166		0x7
+#define QIXIS_SYSCLK_64			0x8
+
+/* DDRCLK */
+#define QIXIS_DDRCLK_66			0x0
+#define QIXIS_DDRCLK_100		0x1
+#define QIXIS_DDRCLK_125		0x2
+#define QIXIS_DDRCLK_133		0x3
+
+
+#define QIXIS_SRDS1CLK_122		0x5a
+#define QIXIS_SRDS1CLK_125		0x5e
+#endif
diff --git a/board/freescale/t1040qds/tlb.c b/board/freescale/t1040qds/tlb.c
new file mode 100644
index 0000000000..412c591f1c
--- /dev/null
+++ b/board/freescale/t1040qds/tlb.c
@@ -0,0 +1,108 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/mmu.h>
+
+struct fsl_e_tlb_entry tlb_table[] = {
+	/* TLB 0 - for temp stack in cache */
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR,
+		      CONFIG_SYS_INIT_RAM_ADDR_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 0, BOOKE_PAGESZ_4K, 0),
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
+		      CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 0, BOOKE_PAGESZ_4K, 0),
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
+		      CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 0, BOOKE_PAGESZ_4K, 0),
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
+		      CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 0, BOOKE_PAGESZ_4K, 0),
+
+	/* TLB 1 */
+	/* *I*** - Covers boot page */
+#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L3_ADDR)
+	/*
+	 * *I*G - L3SRAM. When L3 is used as 256K SRAM, the address of the
+	 * SRAM is at 0xfffc0000, it covered the 0xfffff000.
+	 */
+	SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 0, BOOKE_PAGESZ_256K, 1),
+#else
+	SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 0, BOOKE_PAGESZ_4K, 1),
+#endif
+
+	/* *I*G* - CCSRBAR */
+	SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 1, BOOKE_PAGESZ_16M, 1),
+
+	/* *I*G* - Flash, localbus */
+	/* This will be changed to *I*G* after relocation to RAM. */
+	SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
+		      MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
+		      0, 2, BOOKE_PAGESZ_256M, 1),
+
+	/* *I*G* - PCI */
+	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 3, BOOKE_PAGESZ_1G, 1),
+
+	/* *I*G* - PCI I/O */
+	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 4, BOOKE_PAGESZ_256K, 1),
+
+	/* Bman/Qman */
+#ifdef CONFIG_SYS_BMAN_MEM_PHYS
+	SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE, CONFIG_SYS_BMAN_MEM_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 5, BOOKE_PAGESZ_16M, 1),
+	SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE + 0x01000000,
+		      CONFIG_SYS_BMAN_MEM_PHYS + 0x01000000,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 6, BOOKE_PAGESZ_16M, 1),
+#endif
+#ifdef CONFIG_SYS_QMAN_MEM_PHYS
+	SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE, CONFIG_SYS_QMAN_MEM_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 7, BOOKE_PAGESZ_16M, 1),
+	SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE + 0x01000000,
+		      CONFIG_SYS_QMAN_MEM_PHYS + 0x01000000,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 8, BOOKE_PAGESZ_16M, 1),
+#endif
+#ifdef CONFIG_SYS_DCSRBAR_PHYS
+	SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 9, BOOKE_PAGESZ_4M, 1),
+#endif
+#ifdef CONFIG_SYS_NAND_BASE
+	/*
+	 * *I*G - NAND
+	 * entry 14 and 15 has been used hard coded, they will be disabled
+	 * in cpu_init_f, so we use entry 16 for nand.
+	 */
+	SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 10, BOOKE_PAGESZ_64K, 1),
+#endif
+#ifdef QIXIS_BASE
+	SET_TLB_ENTRY(1, QIXIS_BASE, QIXIS_BASE_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 11, BOOKE_PAGESZ_4K, 1),
+#endif
+
+};
+
+int num_tlb_entries = ARRAY_SIZE(tlb_table);
diff --git a/board/freescale/t104xrdb/Makefile b/board/freescale/t104xrdb/Makefile
new file mode 100644
index 0000000000..e51fb7a7f4
--- /dev/null
+++ b/board/freescale/t104xrdb/Makefile
@@ -0,0 +1,13 @@
+#
+# Copyright 2013 Freescale Semiconductor, Inc.
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+
+obj-y	+= t104xrdb.o
+obj-y	+= ddr.o
+obj-y	+= eth.o
+obj-$(CONFIG_PCI)	+= pci.o
+obj-y	+= law.o
+obj-y	+= tlb.o
diff --git a/board/freescale/t104xrdb/README b/board/freescale/t104xrdb/README
new file mode 100644
index 0000000000..1da52bb0b0
--- /dev/null
+++ b/board/freescale/t104xrdb/README
@@ -0,0 +1,200 @@
+Overview
+--------
+The T1040RDB is a Freescale reference board that hosts the T1040 SoC
+(and variants). Variants inclued T1042 presonality of T1040, in which
+case T1040RDB can also be called T1042RDB.
+
+The T1042RDB_PI is a Freescale reference board that hosts the T1042 SoC.
+(a personality of T1040 SoC). The board is similar to T1040RDB but is
+designed specially with low power features targeted for Printing Image Market.
+
+T1040 SoC Overview
+------------------
+The QorIQ T1040/T1042 processor support four integrated 64-bit e5500 PA
+processor cores with high-performance data path acceleration architecture
+and network peripheral interfaces required for networking & telecommunications.
+
+The T1040/T1042 SoC includes the following function and features:
+
+ - Four e5500 cores, each with a private 256 KB L2 cache
+ - 256 KB shared L3 CoreNet platform cache (CPC)
+ - Interconnect CoreNet platform
+ - 32-/64-bit DDR3L/DDR4 SDRAM memory controller with ECC and interleaving
+   support
+ - Data Path Acceleration Architecture (DPAA) incorporating acceleration
+ for the following functions:
+    -  Packet parsing, classification, and distribution
+    -  Queue management for scheduling, packet sequencing, and congestion
+       management
+    -  Cryptography Acceleration (SEC 5.0)
+    - RegEx Pattern Matching Acceleration (PME 2.2)
+    - IEEE Std 1588 support
+    - Hardware buffer management for buffer allocation and deallocation
+ - Ethernet interfaces
+    - Integrated 8-port Gigabit Ethernet switch (T1040 only)
+    - Four 1 Gbps Ethernet controllers
+ - Two RGMII interfaces or one RGMII and one MII interfaces
+ - High speed peripheral interfaces
+   - Four PCI Express 2.0 controllers running at up to 5 GHz
+   - Two SATA controllers supporting 1.5 and 3.0 Gb/s operation
+   - Upto two QSGMII interface
+   - Upto six SGMII interface supporting 1000 Mbps
+   - One SGMII interface supporting upto 2500 Mbps
+ - Additional peripheral interfaces
+   - Two USB 2.0 controllers with integrated PHY
+   - SD/eSDHC/eMMC
+   - eSPI controller
+   - Four I2C controllers
+   - Four UARTs
+   - Four GPIO controllers
+   - Integrated flash controller (IFC)
+   - LCD and HDMI interface (DIU) with 12 bit dual data rate
+   - TDM interface
+ - Multicore programmable interrupt controller (PIC)
+ - Two 8-channel DMA engines
+ - Single source clocking implementation
+ - Deep Sleep power implementaion (wakeup from GPIO/Timer/Ethernet/USB)
+
+T1040 SoC Personalities
+-------------------------
+
+T1022 Personality:
+T1022 is a reduced personality of T1040 with less core/clusters.
+
+T1042 Personality:
+T1042 is a reduced personality of T1040 without Integrated 8-port Gigabit
+Ethernet switch. Rest of the blocks are same as T1040
+
+
+T1040RDB board Overview
+-------------------------
+ - SERDES Connections, 8 lanes information:
+	1: None
+	2: SGMII
+	3: QSGMII
+	4: QSGMII
+	5: PCIe1 x1 slot
+	6: mini PCIe connector
+	7: mini PCIe connector
+	8: SATA connector
+ - DDR Controller
+     - Supports rates of up to 1600 MHz data-rate
+     - Supports one DDR3LP UDIMM/RDIMMs, of single-, dual- or quad-rank types.
+ - IFC/Local Bus
+     - NAND flash: 1GB 8-bit NAND flash
+     - NOR: 128MB 16-bit NOR Flash
+ - Ethernet
+     - Two on-board RGMII 10/100/1G ethernet ports.
+ - CPLD
+ - Clocks
+     - System and DDR clock (SYSCLK, “DDRCLK”)
+     - SERDES clocks
+ - Power Supplies
+ - USB
+     - Supports two USB 2.0 ports with integrated PHYs
+     - Two type A ports with 5V@1.5A per port.
+ - SDHC
+     - SDHC/SDXC connector
+ - SPI
+    -  On-board 64MB SPI flash
+ - Other IO
+    - Two Serial ports
+    - Four I2C ports
+
+T1042RDB_PI board Overview
+-------------------------
+ - SERDES Connections, 8 lanes information:
+	1, 2, 3, 4 : PCIe x4 slot
+	5: mini PCIe connector
+	6: mini PCIe connector
+	7: NA
+	8: SATA connector
+ - DDR Controller
+     - Supports rates of up to 1600 MHz data-rate
+     - Supports one DDR3LP UDIMM/RDIMMs, of single-, dual- or quad-rank types.
+ - IFC/Local Bus
+     - NAND flash: 1GB 8-bit NAND flash
+     - NOR: 128MB 16-bit NOR Flash
+ - Ethernet
+     - Two on-board RGMII 10/100/1G ethernet ports.
+ - CPLD
+ - Clocks
+     - System and DDR clock (SYSCLK, “DDRCLK”)
+     - SERDES clocks
+ - Video
+     - DIU supports video at up to 1280x1024x32bpp
+ - Power Supplies
+ - USB
+     - Supports two USB 2.0 ports with integrated PHYs
+     - Two type A ports with 5V@1.5A per port.
+ - SDHC
+     - SDHC/SDXC connector
+ - SPI
+    -  On-board 64MB SPI flash
+ - Other IO
+    - Two Serial ports
+    - Four I2C ports
+
+Memory map
+-----------
+The addresses in brackets are physical addresses.
+
+Start Address  End Address      Description                     Size
+0xF_FFDF_0000  0xF_FFDF_0FFF    IFC - CPLD                      4KB
+0xF_FF80_0000  0xF_FF80_FFFF    IFC - NAND Flash                64KB
+0xF_FE00_0000  0xF_FEFF_FFFF    CCSRBAR                         16MB
+0xF_F803_0000  0xF_F803_FFFF    PCI Express 4 I/O Space         64KB
+0xF_F802_0000  0xF_F802_FFFF    PCI Express 3 I/O Space	        64KB
+0xF_F801_0000  0xF_F801_FFFF    PCI Express 2 I/O Space         64KB
+0xF_F800_0000  0xF_F800_FFFF    PCI Express 1 I/O Space	        64KB
+0xF_F600_0000  0xF_F7FF_FFFF    Queue manager software portal   32MB
+0xF_F400_0000  0xF_F5FF_FFFF    Buffer manager software portal  32MB
+0xF_E800_0000  0xF_EFFF_FFFF    IFC - NOR Flash                 128MB
+0xF_0000_0000  0xF_003F_FFFF    DCSR                            4MB
+0xC_3000_0000  0xC_3FFF_FFFF    PCI Express 4 Mem Space         256MB
+0xC_2000_0000  0xC_2FFF_FFFF    PCI Express 3 Mem Space         256MB
+0xC_1000_0000  0xC_1FFF_FFFF    PCI Express 2 Mem Space         256MB
+0xC_0000_0000  0xC_0FFF_FFFF    PCI Express 1 Mem Space         256MB
+0x0_0000_0000  0x0_ffff_ffff    DDR                             2GB
+
+
+NOR Flash memory Map
+---------------------
+ Start          End             Definition                       Size
+0xEFF40000      0xEFFFFFFF      u-boot (current bank)            768KB
+0xEFF20000      0xEFF3FFFF      u-boot env (current bank)        128KB
+0xEFF00000      0xEFF1FFFF      FMAN Ucode (current bank)        128KB
+0xED300000      0xEFEFFFFF      rootfs (alt bank)                44MB
+0xEC800000      0xEC8FFFFF      Hardware device tree (alt bank)  1MB
+0xEC020000      0xEC7FFFFF      Linux.uImage (alt bank)          7MB + 875KB
+0xEC000000      0xEC01FFFF      RCW (alt bank)                   128KB
+0xEBF40000      0xEBFFFFFF      u-boot (alt bank)                768KB
+0xEBF20000      0xEBF3FFFF      u-boot env (alt bank)            128KB
+0xEBF00000      0xEBF1FFFF      FMAN ucode (alt bank)            128KB
+0xE9300000      0xEBEFFFFF      rootfs (current bank)            44MB
+0xE8800000      0xE88FFFFF      Hardware device tree (cur bank)  11MB + 512KB
+0xE8020000      0xE86FFFFF      Linux.uImage (current bank)      7MB + 875KB
+0xE8000000      0xE801FFFF      RCW (current bank)               128KB
+
+
+Various Software configurations/environment variables/commands
+--------------------------------------------------------------
+The below commands apply to the board
+
+1. U-boot environment variable hwconfig
+   The default hwconfig is:
+	hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=cs0_cs1;usb1:
+					dr_mode=host,phy_type=utmi
+   Note: For USB gadget set "dr_mode=peripheral"
+
+2. FMAN Ucode versions
+   fsl_fman_ucode_t1040.bin
+
+3. Switching to alternate bank
+   Commands for switching to alternate bank.
+
+	1. To change from vbank0 to vbank4
+		=> qixis_reset altbank (it will boot using vbank4)
+
+	2.To change from vbank4 to vbank0
+		=> qixis reset (it will boot using vbank0)
diff --git a/board/freescale/t104xrdb/ddr.c b/board/freescale/t104xrdb/ddr.c
new file mode 100644
index 0000000000..57d0f9cfd8
--- /dev/null
+++ b/board/freescale/t104xrdb/ddr.c
@@ -0,0 +1,125 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <i2c.h>
+#include <hwconfig.h>
+#include <asm/mmu.h>
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr_dimm_params.h>
+#include <asm/fsl_law.h>
+#include "ddr.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int fsl_ddr_get_dimm_params(dimm_params_t *pdimm,
+		unsigned int controller_number,
+		unsigned int dimm_number)
+{
+	const char dimm_model[] = "RAW timing DDR";
+
+	if ((controller_number == 0) && (dimm_number == 0)) {
+		memcpy(pdimm, &ddr_raw_timing, sizeof(dimm_params_t));
+		memset(pdimm->mpart, 0, sizeof(pdimm->mpart));
+		memcpy(pdimm->mpart, dimm_model, sizeof(dimm_model) - 1);
+	}
+
+	return 0;
+}
+
+void fsl_ddr_board_options(memctl_options_t *popts,
+				dimm_params_t *pdimm,
+				unsigned int ctrl_num)
+{
+	const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
+	ulong ddr_freq;
+
+	if (ctrl_num > 1) {
+		printf("Not supported controller number %d\n", ctrl_num);
+		return;
+	}
+	if (!pdimm->n_ranks)
+		return;
+
+	pbsp = udimms[0];
+
+	/* Get clk_adjust according to the board ddr
+	 * freqency and n_banks specified in board_specific_parameters table.
+	 */
+	ddr_freq = get_ddr_freq(0) / 1000000;
+	while (pbsp->datarate_mhz_high) {
+		if (pbsp->n_ranks == pdimm->n_ranks &&
+		    (pdimm->rank_density >> 30) >= pbsp->rank_gb) {
+			if (ddr_freq <= pbsp->datarate_mhz_high) {
+				popts->clk_adjust = pbsp->clk_adjust;
+				popts->wrlvl_start = pbsp->wrlvl_start;
+				popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
+				popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
+				goto found;
+			}
+			pbsp_highest = pbsp;
+		}
+		pbsp++;
+	}
+
+	if (pbsp_highest) {
+		printf("Error: board specific timing not found\n");
+		printf("for data rate %lu MT/s\n", ddr_freq);
+		printf("Trying to use the highest speed (%u) parameters\n",
+		       pbsp_highest->datarate_mhz_high);
+		popts->clk_adjust = pbsp_highest->clk_adjust;
+		popts->wrlvl_start = pbsp_highest->wrlvl_start;
+		popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
+		popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
+	} else {
+		panic("DIMM is not supported by this board");
+	}
+found:
+	debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n"
+		"\tclk_adjust %d, wrlvl_start %d, wrlvl_ctrl_2 0x%x, "
+		"wrlvl_ctrl_3 0x%x\n",
+		pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb,
+		pbsp->clk_adjust, pbsp->wrlvl_start, pbsp->wrlvl_ctl_2,
+		pbsp->wrlvl_ctl_3);
+
+	/*
+	 * Factors to consider for half-strength driver enable:
+	 *	- number of DIMMs installed
+	 */
+	popts->half_strength_driver_enable = 0;
+	/*
+	 * Write leveling override
+	 */
+	popts->wrlvl_override = 1;
+	popts->wrlvl_sample = 0xf;
+
+	/*
+	 * rtt and rtt_wr override
+	 */
+	popts->rtt_override = 0;
+
+	/* Enable ZQ calibration */
+	popts->zq_en = 1;
+
+	/* DHC_EN =1, ODT = 75 Ohm */
+	popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_OFF);
+	popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_OFF);
+}
+
+phys_size_t initdram(int board_type)
+{
+	phys_size_t dram_size;
+
+	puts("Initializing....using SPD\n");
+
+	dram_size = fsl_ddr_sdram();
+
+	dram_size = setup_ddr_tlbs(dram_size / 0x100000);
+	dram_size *= 0x100000;
+
+	puts("    DDR: ");
+	return dram_size;
+}
diff --git a/board/freescale/t104xrdb/ddr.h b/board/freescale/t104xrdb/ddr.h
new file mode 100644
index 0000000000..09b30b9aac
--- /dev/null
+++ b/board/freescale/t104xrdb/ddr.h
@@ -0,0 +1,78 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __DDR_H__
+#define __DDR_H__
+dimm_params_t ddr_raw_timing = {
+	.n_ranks = 2,
+	.rank_density = 2147483648u,
+	.capacity = 4294967296u,
+	.primary_sdram_width = 64,
+	.ec_sdram_width = 8,
+	.registered_dimm = 0,
+	.mirrored_dimm = 0,
+	.n_row_addr = 15,
+	.n_col_addr = 10,
+	.n_banks_per_sdram_device = 8,
+	.edc_config = 2,	/* ECC */
+	.burst_lengths_bitmask = 0x0c,
+	.tckmin_x_ps = 1071,
+	.caslat_x = 0xfe << 4,	/* 5,6,7,8,9,10,11 */
+	.taa_ps = 13125,
+	.twr_ps = 15000,
+	.trcd_ps = 13125,
+	.trrd_ps = 6000,
+	.trp_ps = 13125,
+	.tras_ps = 34000,
+	.trc_ps = 48125,
+	.trfc_ps = 260000,
+	.twtr_ps = 7500,
+	.trtp_ps = 7500,
+	.refresh_rate_ps = 7800000,
+	.tfaw_ps = 35000,
+};
+
+struct board_specific_parameters {
+	u32 n_ranks;
+	u32 datarate_mhz_high;
+	u32 rank_gb;
+	u32 clk_adjust;
+	u32 wrlvl_start;
+	u32 wrlvl_ctl_2;
+	u32 wrlvl_ctl_3;
+};
+
+/*
+ * These tables contain all valid speeds we want to override with board
+ * specific parameters. datarate_mhz_high values need to be in ascending order
+ * for each n_ranks group.
+ */
+
+static const struct board_specific_parameters udimm0[] = {
+	/*
+	 * memory controller 0
+	 *   num|  hi| rank|  clk| wrlvl |   wrlvl
+	 * ranks| mhz| GB  |adjst| start |   ctl2
+	 */
+	{2,  833,  4, 4,     6, 0x06060607, 0x08080807},
+	{2,  833,  0, 4,     6, 0x06060607, 0x08080807},
+	{2,  1350, 4, 4,     7, 0x0708080A, 0x0A0B0C09},
+	{2,  1350, 0, 4,     7, 0x0708080A, 0x0A0B0C09},
+	{2,  1666, 4, 4,     7, 0x0808090B, 0x0C0D0E0A},
+	{2,  1666, 0, 4,     7, 0x0808090B, 0x0C0D0E0A},
+	{1,  833,  4, 4,     6, 0x06060607, 0x08080807},
+	{1,  833,  0, 4,     6, 0x06060607, 0x08080807},
+	{1,  1350, 4, 4,     7, 0x0708080A, 0x0A0B0C09},
+	{1,  1350, 0, 4,     7, 0x0708080A, 0x0A0B0C09},
+	{1,  1666, 4, 4,     7, 0x0808090B, 0x0C0D0E0A},
+	{1,  1666, 0, 4,     7, 0x0808090B, 0x0C0D0E0A},
+	{}
+};
+
+static const struct board_specific_parameters *udimms[] = {
+	udimm0,
+};
+#endif
diff --git a/board/freescale/t104xrdb/eth.c b/board/freescale/t104xrdb/eth.c
new file mode 100644
index 0000000000..0188fd4090
--- /dev/null
+++ b/board/freescale/t104xrdb/eth.c
@@ -0,0 +1,72 @@
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <netdev.h>
+#include <asm/immap_85xx.h>
+#include <fm_eth.h>
+#include <fsl_mdio.h>
+#include <malloc.h>
+#include <asm/fsl_dtsec.h>
+
+#include "../common/fman.h"
+
+int board_eth_init(bd_t *bis)
+{
+#ifdef CONFIG_FMAN_ENET
+	struct memac_mdio_info memac_mdio_info;
+	unsigned int i;
+	int phy_addr = 0;
+	printf("Initializing Fman\n");
+
+	memac_mdio_info.regs =
+		(struct memac_mdio_controller *)CONFIG_SYS_FM1_DTSEC_MDIO_ADDR;
+	memac_mdio_info.name = DEFAULT_FM_MDIO_NAME;
+
+	/* Register the real 1G MDIO bus */
+	fm_memac_mdio_init(bis, &memac_mdio_info);
+
+	/*
+	 * Program on board RGMII, SGMII PHY addresses.
+	 */
+	for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
+		int idx = i - FM1_DTSEC1;
+
+		switch (fm_info_get_enet_if(i)) {
+#ifdef CONFIG_T1040RDB
+		case PHY_INTERFACE_MODE_SGMII:
+			/* T1040RDB only supports SGMII on DTSEC3 */
+			fm_info_set_phy_address(FM1_DTSEC3,
+						CONFIG_SYS_SGMII1_PHY_ADDR);
+#endif
+		case PHY_INTERFACE_MODE_RGMII:
+			if (FM1_DTSEC4 == i)
+				phy_addr = CONFIG_SYS_RGMII1_PHY_ADDR;
+			if (FM1_DTSEC5 == i)
+				phy_addr = CONFIG_SYS_RGMII2_PHY_ADDR;
+			fm_info_set_phy_address(i, phy_addr);
+			break;
+		case PHY_INTERFACE_MODE_QSGMII:
+			fm_info_set_phy_address(i, 0);
+			break;
+		case PHY_INTERFACE_MODE_NONE:
+			fm_info_set_phy_address(i, 0);
+			break;
+		default:
+			printf("Fman1: DTSEC%u set to unknown interface %i\n",
+			       idx + 1, fm_info_get_enet_if(i));
+			fm_info_set_phy_address(i, 0);
+			break;
+		}
+		fm_info_set_mdio(i,
+				 miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME));
+	}
+
+	cpu_eth_init(bis);
+#endif
+
+	return pci_eth_init(bis);
+}
diff --git a/board/freescale/t104xrdb/law.c b/board/freescale/t104xrdb/law.c
new file mode 100644
index 0000000000..2362d4324b
--- /dev/null
+++ b/board/freescale/t104xrdb/law.c
@@ -0,0 +1,32 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/fsl_law.h>
+#include <asm/mmu.h>
+
+struct law_entry law_table[] = {
+#ifndef CONFIG_SYS_NO_FLASH
+	SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_IFC),
+#endif
+#ifdef CONFIG_SYS_BMAN_MEM_PHYS
+	SET_LAW(CONFIG_SYS_BMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_BMAN),
+#endif
+#ifdef CONFIG_SYS_QMAN_MEM_PHYS
+	SET_LAW(CONFIG_SYS_QMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_QMAN),
+#endif
+#ifdef CONFIG_SYS_CPLD_BASE_PHYS
+	SET_LAW(CONFIG_SYS_CPLD_BASE_PHYS, LAW_SIZE_128K, LAW_TRGT_IF_IFC),
+#endif
+#ifdef CONFIG_SYS_DCSRBAR_PHYS
+	SET_LAW(CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_4M, LAW_TRGT_IF_DCSR),
+#endif
+#ifdef CONFIG_SYS_NAND_BASE_PHYS
+	SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_IFC),
+#endif
+};
+
+int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/board/freescale/t104xrdb/pci.c b/board/freescale/t104xrdb/pci.c
new file mode 100644
index 0000000000..c53e3b76a4
--- /dev/null
+++ b/board/freescale/t104xrdb/pci.c
@@ -0,0 +1,23 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <command.h>
+#include <pci.h>
+#include <asm/fsl_pci.h>
+#include <libfdt.h>
+#include <fdt_support.h>
+#include <asm/fsl_serdes.h>
+
+void pci_init_board(void)
+{
+	fsl_pcie_init_board(0);
+}
+
+void pci_of_setup(void *blob, bd_t *bd)
+{
+	FT_FSL_PCI_SETUP;
+}
diff --git a/board/freescale/t104xrdb/t104xrdb.c b/board/freescale/t104xrdb/t104xrdb.c
new file mode 100644
index 0000000000..6e29d64107
--- /dev/null
+++ b/board/freescale/t104xrdb/t104xrdb.c
@@ -0,0 +1,93 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <command.h>
+#include <netdev.h>
+#include <linux/compiler.h>
+#include <asm/mmu.h>
+#include <asm/processor.h>
+#include <asm/cache.h>
+#include <asm/immap_85xx.h>
+#include <asm/fsl_law.h>
+#include <asm/fsl_serdes.h>
+#include <asm/fsl_portals.h>
+#include <asm/fsl_liodn.h>
+#include <fm_eth.h>
+
+#include "t104xrdb.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int checkboard(void)
+{
+	struct cpu_type *cpu = gd->arch.cpu;
+
+	printf("Board: %sRDB\n", cpu->name);
+	return 0;
+}
+
+int board_early_init_r(void)
+{
+#ifdef CONFIG_SYS_FLASH_BASE
+	const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
+	const u8 flash_esel = find_tlb_idx((void *)flashbase, 1);
+
+	/*
+	 * Remap Boot flash region to caching-inhibited
+	 * so that flash can be erased properly.
+	 */
+
+	/* Flush d-cache and invalidate i-cache of any FLASH data */
+	flush_dcache();
+	invalidate_icache();
+
+	/* invalidate existing TLB entry for flash */
+	disable_tlb(flash_esel);
+
+	set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
+		MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		0, flash_esel, BOOKE_PAGESZ_256M, 1);
+#endif
+	set_liodns();
+#ifdef CONFIG_SYS_DPAA_QBMAN
+	setup_portals();
+#endif
+
+	return 0;
+}
+
+int misc_init_r(void)
+{
+	return 0;
+}
+
+void ft_board_setup(void *blob, bd_t *bd)
+{
+	phys_addr_t base;
+	phys_size_t size;
+
+	ft_cpu_setup(blob, bd);
+
+	base = getenv_bootm_low();
+	size = getenv_bootm_size();
+
+	fdt_fixup_memory(blob, (u64)base, (u64)size);
+
+#ifdef CONFIG_PCI
+	pci_of_setup(blob, bd);
+#endif
+
+	fdt_fixup_liodn(blob);
+
+#ifdef CONFIG_HAS_FSL_DR_USB
+	fdt_fixup_dr_usb(blob, bd);
+#endif
+
+#ifdef CONFIG_SYS_DPAA_FMAN
+	fdt_fixup_fman_ethernet(blob);
+#endif
+}
diff --git a/board/freescale/t104xrdb/t104xrdb.h b/board/freescale/t104xrdb/t104xrdb.h
new file mode 100644
index 0000000000..e7cc0c7b5e
--- /dev/null
+++ b/board/freescale/t104xrdb/t104xrdb.h
@@ -0,0 +1,13 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __T104x_RDB_H__
+#define __T104x_RDB_H__
+
+void fdt_fixup_board_enet(void *blob);
+void pci_of_setup(void *blob, bd_t *bd);
+
+#endif
diff --git a/board/freescale/t104xrdb/tlb.c b/board/freescale/t104xrdb/tlb.c
new file mode 100644
index 0000000000..84f97a41e3
--- /dev/null
+++ b/board/freescale/t104xrdb/tlb.c
@@ -0,0 +1,107 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/mmu.h>
+
+struct fsl_e_tlb_entry tlb_table[] = {
+	/* TLB 0 - for temp stack in cache */
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR,
+		      CONFIG_SYS_INIT_RAM_ADDR_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 0, BOOKE_PAGESZ_4K, 0),
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
+		      CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 0, BOOKE_PAGESZ_4K, 0),
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
+		      CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 0, BOOKE_PAGESZ_4K, 0),
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
+		      CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 0, BOOKE_PAGESZ_4K, 0),
+
+	/* TLB 1 */
+	/* *I*** - Covers boot page */
+#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L3_ADDR)
+	/*
+	 * *I*G - L3SRAM. When L3 is used as 256K SRAM, the address of the
+	 * SRAM is at 0xfffc0000, it covered the 0xfffff000.
+	 */
+	SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 0, BOOKE_PAGESZ_256K, 1),
+#else
+	SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 0, BOOKE_PAGESZ_4K, 1),
+#endif
+
+	/* *I*G* - CCSRBAR */
+	SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 1, BOOKE_PAGESZ_16M, 1),
+
+	/* *I*G* - Flash, localbus */
+	/* This will be changed to *I*G* after relocation to RAM. */
+	SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
+		      MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
+		      0, 2, BOOKE_PAGESZ_256M, 1),
+
+	/* *I*G* - PCI */
+	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 3, BOOKE_PAGESZ_1G, 1),
+
+	/* *I*G* - PCI I/O */
+	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 4, BOOKE_PAGESZ_256K, 1),
+
+	/* Bman/Qman */
+#ifdef CONFIG_SYS_BMAN_MEM_PHYS
+	SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE, CONFIG_SYS_BMAN_MEM_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 5, BOOKE_PAGESZ_16M, 1),
+	SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE + 0x01000000,
+		      CONFIG_SYS_BMAN_MEM_PHYS + 0x01000000,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 6, BOOKE_PAGESZ_16M, 1),
+#endif
+#ifdef CONFIG_SYS_QMAN_MEM_PHYS
+	SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE, CONFIG_SYS_QMAN_MEM_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 7, BOOKE_PAGESZ_16M, 1),
+	SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE + 0x01000000,
+		      CONFIG_SYS_QMAN_MEM_PHYS + 0x01000000,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 8, BOOKE_PAGESZ_16M, 1),
+#endif
+#ifdef CONFIG_SYS_DCSRBAR_PHYS
+	SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 9, BOOKE_PAGESZ_4M, 1),
+#endif
+#ifdef CONFIG_SYS_NAND_BASE
+	/*
+	 * *I*G - NAND
+	 * entry 14 and 15 has been used hard coded, they will be disabled
+	 * in cpu_init_f, so we use entry 16 for nand.
+	 */
+	SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 10, BOOKE_PAGESZ_64K, 1),
+#endif
+#ifdef CONFIG_SYS_CPLD_BASE
+	SET_TLB_ENTRY(1, CONFIG_SYS_CPLD_BASE, CONFIG_SYS_CPLD_BASE_PHYS,
+		      MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 11, BOOKE_PAGESZ_256K, 1),
+#endif
+};
+
+int num_tlb_entries = ARRAY_SIZE(tlb_table);
diff --git a/board/freescale/t208xqds/Makefile b/board/freescale/t208xqds/Makefile
new file mode 100644
index 0000000000..947b7f7324
--- /dev/null
+++ b/board/freescale/t208xqds/Makefile
@@ -0,0 +1,14 @@
+#
+# Copyright 2013 Freescale Semiconductor, Inc.
+#
+# SPDX-License-Identifier:      GPL-2.0+
+#
+
+obj-$(CONFIG_T2080QDS) += t208xqds.o
+obj-$(CONFIG_T2080QDS) += eth_t208xqds.o
+obj-$(CONFIG_T2081QDS) += t208xqds.o
+obj-$(CONFIG_T2081QDS) += eth_t208xqds.o
+obj-$(CONFIG_PCI)      += pci.o
+obj-y   += ddr.o
+obj-y   += law.o
+obj-y   += tlb.o
diff --git a/board/freescale/t208xqds/ddr.c b/board/freescale/t208xqds/ddr.c
new file mode 100644
index 0000000000..ed1334d985
--- /dev/null
+++ b/board/freescale/t208xqds/ddr.c
@@ -0,0 +1,119 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * Version 2 or later as published by the Free Software Foundation.
+ */
+
+#include <common.h>
+#include <i2c.h>
+#include <hwconfig.h>
+#include <asm/mmu.h>
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr_dimm_params.h>
+#include <asm/fsl_law.h>
+#include "ddr.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void fsl_ddr_board_options(memctl_options_t *popts,
+				dimm_params_t *pdimm,
+				unsigned int ctrl_num)
+{
+	const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
+	ulong ddr_freq;
+
+	if (ctrl_num > 1) {
+		printf("Not supported controller number %d\n", ctrl_num);
+		return;
+	}
+	if (!pdimm->n_ranks)
+		return;
+
+	/*
+	 * we use identical timing for all slots. If needed, change the code
+	 * to  pbsp = rdimms[ctrl_num] or pbsp = udimms[ctrl_num];
+	 */
+	if (popts->registered_dimm_en)
+		pbsp = rdimms[0];
+	else
+		pbsp = udimms[0];
+
+	/* Get clk_adjust, wrlvl_start, wrlvl_ctl, according to the board ddr
+	 * freqency and n_banks specified in board_specific_parameters table.
+	 */
+	ddr_freq = get_ddr_freq(0) / 1000000;
+	while (pbsp->datarate_mhz_high) {
+		if (pbsp->n_ranks == pdimm->n_ranks &&
+		    (pdimm->rank_density >> 30) >= pbsp->rank_gb) {
+			if (ddr_freq <= pbsp->datarate_mhz_high) {
+				popts->clk_adjust = pbsp->clk_adjust;
+				popts->wrlvl_start = pbsp->wrlvl_start;
+				popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
+				popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
+				goto found;
+			}
+			pbsp_highest = pbsp;
+		}
+		pbsp++;
+	}
+
+	if (pbsp_highest) {
+		printf("Error: board specific timing not found");
+		printf("for data rate %lu MT/s\n", ddr_freq);
+		printf("Trying to use the highest speed (%u) parameters\n",
+		       pbsp_highest->datarate_mhz_high);
+		popts->clk_adjust = pbsp_highest->clk_adjust;
+		popts->wrlvl_start = pbsp_highest->wrlvl_start;
+		popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
+		popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
+	} else {
+		panic("DIMM is not supported by this board");
+	}
+found:
+	debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n"
+		"\tclk_adjust %d, wrlvl_start %d, wrlvl_ctrl_2 0x%x, "
+		"wrlvl_ctrl_3 0x%x\n",
+		pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb,
+		pbsp->clk_adjust, pbsp->wrlvl_start, pbsp->wrlvl_ctl_2,
+		pbsp->wrlvl_ctl_3);
+
+	/*
+	 * Factors to consider for half-strength driver enable:
+	 *	- number of DIMMs installed
+	 */
+	popts->half_strength_driver_enable = 0;
+	/*
+	 * Write leveling override
+	 */
+	popts->wrlvl_override = 1;
+	popts->wrlvl_sample = 0xf;
+
+	/*
+	 * Rtt and Rtt_WR override
+	 */
+	popts->rtt_override = 0;
+
+	/* Enable ZQ calibration */
+	popts->zq_en = 1;
+
+	/* DHC_EN =1, ODT = 75 Ohm */
+	popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_75ohm);
+	popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm);
+}
+
+phys_size_t initdram(int board_type)
+{
+	phys_size_t dram_size;
+
+	puts("Initializing....using SPD\n");
+
+	dram_size = fsl_ddr_sdram();
+
+	dram_size = setup_ddr_tlbs(dram_size / 0x100000);
+	dram_size *= 0x100000;
+
+	puts("    DDR: ");
+	return dram_size;
+}
diff --git a/board/freescale/t208xqds/ddr.h b/board/freescale/t208xqds/ddr.h
new file mode 100644
index 0000000000..9fc879a4ef
--- /dev/null
+++ b/board/freescale/t208xqds/ddr.h
@@ -0,0 +1,72 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#ifndef __DDR_H__
+#define __DDR_H__
+struct board_specific_parameters {
+	u32 n_ranks;
+	u32 datarate_mhz_high;
+	u32 rank_gb;
+	u32 clk_adjust;
+	u32 wrlvl_start;
+	u32 wrlvl_ctl_2;
+	u32 wrlvl_ctl_3;
+};
+
+/*
+ * These tables contain all valid speeds we want to override with board
+ * specific parameters. datarate_mhz_high values need to be in ascending order
+ * for each n_ranks group.
+ */
+
+static const struct board_specific_parameters udimm0[] = {
+	/*
+	 * memory controller 0
+	 *   num|  hi| rank|  clk| wrlvl |   wrlvl   |  wrlvl |
+	 * ranks| mhz| GB  |adjst| start |   ctl2    |  ctl3  |
+	 */
+	{2,  1200, 2, 5,     7, 0x0808090a, 0x0b0c0c0a},
+	{2,  1500, 2, 5,     6, 0x07070809, 0x0a0b0b09},
+	{2,  1600, 2, 5,     8, 0x090b0b0d, 0x0d0e0f0b},
+	{2,  1700, 2, 4,     7, 0x080a0a0c, 0x0c0d0e0a},
+	{2,  1900, 2, 5,     9, 0x0a0b0c0e, 0x0f10120c},
+	{2,  2140, 2, 4,     8, 0x090a0b0d, 0x0e0f110b},
+	{1,  1200, 2, 5,     7, 0x0808090a, 0x0b0c0c0a},
+	{1,  1500, 2, 5,     6, 0x07070809, 0x0a0b0b09},
+	{1,  1600, 2, 5,     8, 0x090b0b0d, 0x0d0e0f0b},
+	{1,  1700, 2, 4,     7, 0x080a0a0c, 0x0c0d0e0a},
+	{1,  1900, 2, 5,     9, 0x0a0b0c0e, 0x0f10120c},
+	{1,  2140, 2, 4,     8, 0x090a0b0d, 0x0e0f110b},
+	{}
+};
+
+static const struct board_specific_parameters rdimm0[] = {
+	/*
+	 * memory controller 0
+	 *   num|  hi| rank|  clk| wrlvl |   wrlvl   |  wrlvl |
+	 * ranks| mhz| GB  |adjst| start |   ctl2    |  ctl3  |
+	 */
+	/* TODO: need tuning these parameters if RDIMM is used */
+	{4,  1350, 0, 5,     9, 0x08070605, 0x06070806},
+	{4,  1666, 0, 5,    11, 0x0a080706, 0x07090906},
+	{4,  2140, 0, 5,    12, 0x0b090807, 0x080a0b07},
+	{2,  1350, 0, 5,     9, 0x08070605, 0x06070806},
+	{2,  1666, 0, 5,    11, 0x0a090806, 0x08090a06},
+	{2,  2140, 0, 5,    12, 0x0b090807, 0x080a0b07},
+	{1,  1350, 0, 5,     9, 0x08070605, 0x06070806},
+	{1,  1666, 0, 5,    11, 0x0a090806, 0x08090a06},
+	{1,  2140, 0, 4,    12, 0x0b090807, 0x080a0b07},
+	{}
+};
+
+static const struct board_specific_parameters *udimms[] = {
+	udimm0,
+};
+
+static const struct board_specific_parameters *rdimms[] = {
+	rdimm0,
+};
+#endif
diff --git a/board/freescale/t208xqds/eth_t208xqds.c b/board/freescale/t208xqds/eth_t208xqds.c
new file mode 100644
index 0000000000..d7a804d22a
--- /dev/null
+++ b/board/freescale/t208xqds/eth_t208xqds.c
@@ -0,0 +1,649 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * Shengzhou Liu <Shengzhou.Liu@freescale.com>
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#include <common.h>
+#include <command.h>
+#include <netdev.h>
+#include <asm/mmu.h>
+#include <asm/processor.h>
+#include <asm/immap_85xx.h>
+#include <asm/fsl_law.h>
+#include <asm/fsl_serdes.h>
+#include <asm/fsl_portals.h>
+#include <asm/fsl_liodn.h>
+#include <malloc.h>
+#include <fm_eth.h>
+#include <fsl_mdio.h>
+#include <miiphy.h>
+#include <phy.h>
+#include <asm/fsl_dtsec.h>
+#include <asm/fsl_serdes.h>
+#include "../common/qixis.h"
+#include "../common/fman.h"
+#include "t208xqds_qixis.h"
+
+#define EMI_NONE	0xFFFFFFFF
+#define EMI1_RGMII1	0
+#define EMI1_RGMII2     1
+#define EMI1_SLOT1	2
+#if defined(CONFIG_T2080QDS)
+#define EMI1_SLOT2	6
+#define EMI1_SLOT3	3
+#define EMI1_SLOT4	4
+#define EMI1_SLOT5	5
+#define EMI2            7
+#elif defined(CONFIG_T2081QDS)
+#define EMI1_SLOT2      3
+#define EMI1_SLOT3      4
+#define EMI1_SLOT5      5
+#define EMI1_SLOT6      6
+#define EMI1_SLOT7      7
+#define EMI2		8
+#endif
+
+static int mdio_mux[NUM_FM_PORTS];
+
+static const char * const mdio_names[] = {
+#if defined(CONFIG_T2080QDS)
+	"T2080QDS_MDIO_RGMII1",
+	"T2080QDS_MDIO_RGMII2",
+	"T2080QDS_MDIO_SLOT1",
+	"T2080QDS_MDIO_SLOT3",
+	"T2080QDS_MDIO_SLOT4",
+	"T2080QDS_MDIO_SLOT5",
+	"T2080QDS_MDIO_SLOT2",
+	"T2080QDS_MDIO_10GC",
+#elif defined(CONFIG_T2081QDS)
+	"T2081QDS_MDIO_RGMII1",
+	"T2081QDS_MDIO_RGMII2",
+	"T2081QDS_MDIO_SLOT1",
+	"T2081QDS_MDIO_SLOT2",
+	"T2081QDS_MDIO_SLOT3",
+	"T2081QDS_MDIO_SLOT5",
+	"T2081QDS_MDIO_SLOT6",
+	"T2081QDS_MDIO_SLOT7",
+	"T2081QDS_MDIO_10GC",
+#endif
+};
+
+/* Map SerDes1 8 lanes to default slot, will be initialized dynamically */
+#if defined(CONFIG_T2080QDS)
+static u8 lane_to_slot[] = {3, 3, 3, 3, 1, 1, 1, 1};
+#elif defined(CONFIG_T2081QDS)
+static u8 lane_to_slot[] = {2, 2, 2, 2, 1, 1, 1, 1};
+#endif
+
+static const char *t208xqds_mdio_name_for_muxval(u8 muxval)
+{
+	return mdio_names[muxval];
+}
+
+struct mii_dev *mii_dev_for_muxval(u8 muxval)
+{
+	struct mii_dev *bus;
+	const char *name = t208xqds_mdio_name_for_muxval(muxval);
+
+	if (!name) {
+		printf("No bus for muxval %x\n", muxval);
+		return NULL;
+	}
+
+	bus = miiphy_get_dev_by_name(name);
+
+	if (!bus) {
+		printf("No bus by name %s\n", name);
+		return NULL;
+	}
+
+	return bus;
+}
+
+struct t208xqds_mdio {
+	u8 muxval;
+	struct mii_dev *realbus;
+};
+
+static void t208xqds_mux_mdio(u8 muxval)
+{
+	u8 brdcfg4;
+	if (muxval < 8) {
+		brdcfg4 = QIXIS_READ(brdcfg[4]);
+		brdcfg4 &= ~BRDCFG4_EMISEL_MASK;
+		brdcfg4 |= (muxval << BRDCFG4_EMISEL_SHIFT);
+		QIXIS_WRITE(brdcfg[4], brdcfg4);
+	}
+}
+
+static int t208xqds_mdio_read(struct mii_dev *bus, int addr, int devad,
+				int regnum)
+{
+	struct t208xqds_mdio *priv = bus->priv;
+
+	t208xqds_mux_mdio(priv->muxval);
+
+	return priv->realbus->read(priv->realbus, addr, devad, regnum);
+}
+
+static int t208xqds_mdio_write(struct mii_dev *bus, int addr, int devad,
+				int regnum, u16 value)
+{
+	struct t208xqds_mdio *priv = bus->priv;
+
+	t208xqds_mux_mdio(priv->muxval);
+
+	return priv->realbus->write(priv->realbus, addr, devad, regnum, value);
+}
+
+static int t208xqds_mdio_reset(struct mii_dev *bus)
+{
+	struct t208xqds_mdio *priv = bus->priv;
+
+	return priv->realbus->reset(priv->realbus);
+}
+
+static int t208xqds_mdio_init(char *realbusname, u8 muxval)
+{
+	struct t208xqds_mdio *pmdio;
+	struct mii_dev *bus = mdio_alloc();
+
+	if (!bus) {
+		printf("Failed to allocate t208xqds MDIO bus\n");
+		return -1;
+	}
+
+	pmdio = malloc(sizeof(*pmdio));
+	if (!pmdio) {
+		printf("Failed to allocate t208xqds private data\n");
+		free(bus);
+		return -1;
+	}
+
+	bus->read = t208xqds_mdio_read;
+	bus->write = t208xqds_mdio_write;
+	bus->reset = t208xqds_mdio_reset;
+	sprintf(bus->name, t208xqds_mdio_name_for_muxval(muxval));
+
+	pmdio->realbus = miiphy_get_dev_by_name(realbusname);
+
+	if (!pmdio->realbus) {
+		printf("No bus with name %s\n", realbusname);
+		free(bus);
+		free(pmdio);
+		return -1;
+	}
+
+	pmdio->muxval = muxval;
+	bus->priv = pmdio;
+	return mdio_register(bus);
+}
+
+void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr,
+				enum fm_port port, int offset)
+{
+	int phy;
+	char alias[20];
+	struct fixed_link f_link;
+	ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+	u32 srds_s1 = in_be32(&gur->rcwsr[4]) &
+				FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
+
+	srds_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
+
+	if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII) {
+		phy = fm_info_get_phy_address(port);
+		switch (port) {
+#if defined(CONFIG_T2080QDS)
+		case FM1_DTSEC1:
+		case FM1_DTSEC2:
+		case FM1_DTSEC9:
+		case FM1_DTSEC10:
+			if (mdio_mux[port] == EMI1_SLOT2) {
+				sprintf(alias, "phy_sgmii_s2_%x", phy);
+				fdt_set_phy_handle(fdt, compat, addr, alias);
+				fdt_status_okay_by_alias(fdt, "emi1_slot2");
+			} else if (mdio_mux[port] == EMI1_SLOT3) {
+				sprintf(alias, "phy_sgmii_s3_%x", phy);
+				fdt_set_phy_handle(fdt, compat, addr, alias);
+				fdt_status_okay_by_alias(fdt, "emi1_slot3");
+			}
+			break;
+		case FM1_DTSEC5:
+		case FM1_DTSEC6:
+			if (mdio_mux[port] == EMI1_SLOT1) {
+				sprintf(alias, "phy_sgmii_s1_%x", phy);
+				fdt_set_phy_handle(fdt, compat, addr, alias);
+				fdt_status_okay_by_alias(fdt, "emi1_slot1");
+			} else if (mdio_mux[port] == EMI1_SLOT2) {
+				sprintf(alias, "phy_sgmii_s2_%x", phy);
+				fdt_set_phy_handle(fdt, compat, addr, alias);
+				fdt_status_okay_by_alias(fdt, "emi1_slot2");
+			}
+			break;
+#elif defined(CONFIG_T2081QDS)
+		case FM1_DTSEC1:
+		case FM1_DTSEC2:
+		case FM1_DTSEC5:
+		case FM1_DTSEC6:
+		case FM1_DTSEC9:
+		case FM1_DTSEC10:
+			if (mdio_mux[port] == EMI1_SLOT2) {
+				sprintf(alias, "phy_sgmii_s2_%x", phy);
+				fdt_set_phy_handle(fdt, compat, addr, alias);
+				fdt_status_okay_by_alias(fdt, "emi1_slot2");
+			} else if (mdio_mux[port] == EMI1_SLOT3) {
+				sprintf(alias, "phy_sgmii_s3_%x", phy);
+				fdt_set_phy_handle(fdt, compat, addr, alias);
+				fdt_status_okay_by_alias(fdt, "emi1_slot3");
+			} else if (mdio_mux[port] == EMI1_SLOT5) {
+				sprintf(alias, "phy_sgmii_s5_%x", phy);
+				fdt_set_phy_handle(fdt, compat, addr, alias);
+				fdt_status_okay_by_alias(fdt, "emi1_slot5");
+			} else if (mdio_mux[port] == EMI1_SLOT6) {
+				sprintf(alias, "phy_sgmii_s6_%x", phy);
+				fdt_set_phy_handle(fdt, compat, addr, alias);
+				fdt_status_okay_by_alias(fdt, "emi1_slot6");
+			} else if (mdio_mux[port] == EMI1_SLOT7) {
+				sprintf(alias, "phy_sgmii_s7_%x", phy);
+				fdt_set_phy_handle(fdt, compat, addr, alias);
+				fdt_status_okay_by_alias(fdt, "emi1_slot7");
+			}
+			break;
+#endif
+		default:
+			break;
+		}
+
+	} else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_XGMII) {
+		switch (srds_s1) {
+		case 0x66: /* XFI interface */
+		case 0x6b:
+		case 0x6c:
+		case 0x6d:
+		case 0x71:
+			f_link.phy_id = port;
+			f_link.duplex = 1;
+			f_link.link_speed = 10000;
+			f_link.pause = 0;
+			f_link.asym_pause = 0;
+			/* no PHY for XFI */
+			fdt_delprop(fdt, offset, "phy-handle");
+			fdt_setprop(fdt, offset, "fixed-link", &f_link,
+				    sizeof(f_link));
+			break;
+		default:
+			break;
+		}
+	}
+}
+
+void fdt_fixup_board_enet(void *fdt)
+{
+	return;
+}
+
+/*
+ * This function reads RCW to check if Serdes1{A:H} is configured
+ * to slot 1/2/3/4/5/6/7 and update the lane_to_slot[] array accordingly
+ */
+static void initialize_lane_to_slot(void)
+{
+	ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+	u32 srds_s1 = in_be32(&gur->rcwsr[4]) &
+				FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
+
+	srds_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
+
+	switch (srds_s1) {
+#if defined(CONFIG_T2080QDS)
+	case 0x51:
+	case 0x5f:
+	case 0x65:
+	case 0x6b:
+	case 0x71:
+		lane_to_slot[5] = 2;
+		lane_to_slot[6] = 2;
+		lane_to_slot[7] = 2;
+		break;
+	case 0xa6:
+	case 0x8e:
+	case 0x8f:
+	case 0x82:
+	case 0x83:
+	case 0xd3:
+	case 0xd9:
+	case 0xcb:
+		lane_to_slot[6] = 2;
+		lane_to_slot[7] = 2;
+		break;
+	case 0xda:
+		lane_to_slot[4] = 3;
+		lane_to_slot[5] = 3;
+		lane_to_slot[6] = 3;
+		lane_to_slot[7] = 3;
+		break;
+#elif defined(CONFIG_T2081QDS)
+	case 0x6b:
+		lane_to_slot[4] = 1;
+		lane_to_slot[5] = 3;
+		lane_to_slot[6] = 3;
+		lane_to_slot[7] = 3;
+		break;
+	case 0xca:
+	case 0xcb:
+		lane_to_slot[1] = 7;
+		lane_to_slot[2] = 6;
+		lane_to_slot[3] = 5;
+		lane_to_slot[5] = 3;
+		lane_to_slot[6] = 3;
+		lane_to_slot[7] = 3;
+		break;
+	case 0xf2:
+		lane_to_slot[1] = 7;
+		lane_to_slot[2] = 7;
+		lane_to_slot[3] = 7;
+		lane_to_slot[5] = 4;
+		lane_to_slot[6] = 3;
+		lane_to_slot[7] = 7;
+		break;
+#endif
+	default:
+		break;
+	}
+}
+
+int board_eth_init(bd_t *bis)
+{
+#if defined(CONFIG_FMAN_ENET)
+	int i, idx, lane, slot, interface;
+	struct memac_mdio_info dtsec_mdio_info;
+	struct memac_mdio_info tgec_mdio_info;
+	ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+	u32 rcwsr13 = in_be32(&gur->rcwsr[13]);
+	u32 srds_s1;
+
+	srds_s1 = in_be32(&gur->rcwsr[4]) &
+					FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
+	srds_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
+
+	initialize_lane_to_slot();
+
+	/* Initialize the mdio_mux array so we can recognize empty elements */
+	for (i = 0; i < NUM_FM_PORTS; i++)
+		mdio_mux[i] = EMI_NONE;
+
+	dtsec_mdio_info.regs =
+		(struct memac_mdio_controller *)CONFIG_SYS_FM1_DTSEC_MDIO_ADDR;
+
+	dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME;
+
+	/* Register the 1G MDIO bus */
+	fm_memac_mdio_init(bis, &dtsec_mdio_info);
+
+	tgec_mdio_info.regs =
+		(struct memac_mdio_controller *)CONFIG_SYS_FM1_TGEC_MDIO_ADDR;
+	tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME;
+
+	/* Register the 10G MDIO bus */
+	fm_memac_mdio_init(bis, &tgec_mdio_info);
+
+	/* Register the muxing front-ends to the MDIO buses */
+	t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII1);
+	t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII2);
+	t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT1);
+	t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT2);
+	t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT3);
+#if defined(CONFIG_T2080QDS)
+	t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT4);
+#endif
+	t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT5);
+#if defined(CONFIG_T2081QDS)
+	t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT6);
+	t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT7);
+#endif
+	t208xqds_mdio_init(DEFAULT_FM_TGEC_MDIO_NAME, EMI2);
+
+	/* Set the two on-board RGMII PHY address */
+	fm_info_set_phy_address(FM1_DTSEC3, RGMII_PHY1_ADDR);
+	if ((rcwsr13 & FSL_CORENET_RCWSR13_EC2) ==
+			FSL_CORENET_RCWSR13_EC2_DTSEC4_RGMII)
+		fm_info_set_phy_address(FM1_DTSEC4, RGMII_PHY2_ADDR);
+	else
+		fm_info_set_phy_address(FM1_DTSEC10, RGMII_PHY2_ADDR);
+
+	switch (srds_s1) {
+	case 0x1c:
+	case 0x95:
+	case 0xa2:
+	case 0x94:
+		/* T2080QDS: SGMII in Slot3;  T2081QDS: SGMII in Slot2 */
+		fm_info_set_phy_address(FM1_DTSEC9, SGMII_CARD_PORT1_PHY_ADDR);
+		fm_info_set_phy_address(FM1_DTSEC10, SGMII_CARD_PORT2_PHY_ADDR);
+		fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT3_PHY_ADDR);
+		fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT4_PHY_ADDR);
+		/* T2080QDS: SGMII in Slot2;  T2081QDS: SGMII in Slot1 */
+		fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT3_PHY_ADDR);
+		fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT4_PHY_ADDR);
+		break;
+	case 0x51:
+	case 0x5f:
+	case 0x65:
+		/* T2080QDS: XAUI/HiGig in Slot3;  T2081QDS: in Slot2 */
+		fm_info_set_phy_address(FM1_10GEC1, FM1_10GEC1_PHY_ADDR);
+		/* T2080QDS: SGMII in Slot2;  T2081QDS: in Slot3 */
+		fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT3_PHY_ADDR);
+		fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT4_PHY_ADDR);
+		break;
+	case 0x66:
+		/*
+		 * XFI does not need a PHY to work, but to avoid U-boot use
+		 * default PHY address which is zero to a MAC when it found
+		 * a MAC has no PHY address, we give a PHY address to XFI
+		 * MAC, and should not use a real XAUI PHY address, since
+		 * MDIO can access it successfully, and then MDIO thinks
+		 * the XAUI card is used for the XFI MAC, which will cause
+		 * error.
+		 */
+		fm_info_set_phy_address(FM1_10GEC1, 4);
+		fm_info_set_phy_address(FM1_10GEC2, 5);
+		fm_info_set_phy_address(FM1_10GEC3, 6);
+		fm_info_set_phy_address(FM1_10GEC4, 7);
+		break;
+	case 0x6b:
+		fm_info_set_phy_address(FM1_10GEC1, 4);
+		fm_info_set_phy_address(FM1_10GEC2, 5);
+		fm_info_set_phy_address(FM1_10GEC3, 6);
+		fm_info_set_phy_address(FM1_10GEC4, 7);
+		/* T2080QDS: SGMII in Slot2;  T2081QDS: in Slot3 */
+		fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT3_PHY_ADDR);
+		fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT2_PHY_ADDR);
+		break;
+	case 0x6c:
+	case 0x6d:
+		fm_info_set_phy_address(FM1_10GEC1, 4);
+		fm_info_set_phy_address(FM1_10GEC2, 5);
+		/* T2080QDS: SGMII in Slot3;  T2081QDS: in Slot2 */
+		fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT3_PHY_ADDR);
+		fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT4_PHY_ADDR);
+		break;
+	case 0x71:
+		/* SGMII in Slot3 */
+		fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT3_PHY_ADDR);
+		fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT4_PHY_ADDR);
+		/* SGMII in Slot2 */
+		fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT3_PHY_ADDR);
+		fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT2_PHY_ADDR);
+		break;
+	case 0xa6:
+	case 0x8e:
+	case 0x8f:
+	case 0x82:
+	case 0x83:
+		/* SGMII in Slot3 */
+		fm_info_set_phy_address(FM1_DTSEC9, SGMII_CARD_PORT1_PHY_ADDR);
+		fm_info_set_phy_address(FM1_DTSEC10, SGMII_CARD_PORT2_PHY_ADDR);
+		fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT3_PHY_ADDR);
+		fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT4_PHY_ADDR);
+		/* SGMII in Slot2 */
+		fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT3_PHY_ADDR);
+		fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT2_PHY_ADDR);
+		break;
+	case 0xa4:
+	case 0x96:
+	case 0x8a:
+		/* SGMII in Slot3 */
+		fm_info_set_phy_address(FM1_DTSEC9, SGMII_CARD_PORT1_PHY_ADDR);
+		fm_info_set_phy_address(FM1_DTSEC10, SGMII_CARD_PORT2_PHY_ADDR);
+		fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT3_PHY_ADDR);
+		fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT4_PHY_ADDR);
+		break;
+#if defined(CONFIG_T2080QDS)
+	case 0xd9:
+	case 0xd3:
+	case 0xcb:
+		/* SGMII in Slot3 */
+		fm_info_set_phy_address(FM1_DTSEC10, SGMII_CARD_PORT2_PHY_ADDR);
+		fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT3_PHY_ADDR);
+		fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT4_PHY_ADDR);
+		/* SGMII in Slot2 */
+		fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT3_PHY_ADDR);
+		fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT2_PHY_ADDR);
+		break;
+#elif defined(CONFIG_T2081QDS)
+	case 0xca:
+	case 0xcb:
+		/* SGMII in Slot3 */
+		fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT1_PHY_ADDR);
+		fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT2_PHY_ADDR);
+		/* SGMII in Slot5 */
+		fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT1_PHY_ADDR);
+		/* SGMII in Slot6 */
+		fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT1_PHY_ADDR);
+		/* SGMII in Slot7 */
+		fm_info_set_phy_address(FM1_DTSEC10, SGMII_CARD_PORT3_PHY_ADDR);
+		break;
+#endif
+	case 0xf2:
+		/* T2080QDS: SGMII in Slot3; T2081QDS: SGMII in Slot7 */
+		fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT1_PHY_ADDR);
+		fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT2_PHY_ADDR);
+		fm_info_set_phy_address(FM1_DTSEC10, SGMII_CARD_PORT3_PHY_ADDR);
+		fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT4_PHY_ADDR);
+		break;
+	default:
+		break;
+	}
+
+	for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
+		idx = i - FM1_DTSEC1;
+		interface = fm_info_get_enet_if(i);
+		switch (interface) {
+		case PHY_INTERFACE_MODE_SGMII:
+			lane = serdes_get_first_lane(FSL_SRDS_1,
+					SGMII_FM1_DTSEC1 + idx);
+			if (lane < 0)
+				break;
+			slot = lane_to_slot[lane];
+			debug("FM1@DTSEC%u expects SGMII in slot %u\n",
+			      idx + 1, slot);
+			if (QIXIS_READ(present2) & (1 << (slot - 1)))
+				fm_disable_port(i);
+
+			switch (slot) {
+			case 1:
+				mdio_mux[i] = EMI1_SLOT1;
+				fm_info_set_mdio(i, mii_dev_for_muxval(
+						 mdio_mux[i]));
+				break;
+			case 2:
+				mdio_mux[i] = EMI1_SLOT2;
+				fm_info_set_mdio(i, mii_dev_for_muxval(
+						 mdio_mux[i]));
+				break;
+			case 3:
+				mdio_mux[i] = EMI1_SLOT3;
+				fm_info_set_mdio(i, mii_dev_for_muxval(
+						 mdio_mux[i]));
+				break;
+#if defined(CONFIG_T2081QDS)
+			case 5:
+				mdio_mux[i] = EMI1_SLOT5;
+				fm_info_set_mdio(i, mii_dev_for_muxval(
+						 mdio_mux[i]));
+				break;
+			case 6:
+				mdio_mux[i] = EMI1_SLOT6;
+				fm_info_set_mdio(i, mii_dev_for_muxval(
+						 mdio_mux[i]));
+				break;
+			case 7:
+				mdio_mux[i] = EMI1_SLOT7;
+				fm_info_set_mdio(i, mii_dev_for_muxval(
+						 mdio_mux[i]));
+				break;
+#endif
+			}
+			break;
+		case PHY_INTERFACE_MODE_RGMII:
+			if (i == FM1_DTSEC3)
+				mdio_mux[i] = EMI1_RGMII1;
+			else if (i == FM1_DTSEC4 || FM1_DTSEC10)
+				mdio_mux[i] = EMI1_RGMII2;
+			fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
+			break;
+		default:
+			break;
+		}
+	}
+
+	for (i = FM1_10GEC1; i < FM1_10GEC1 + CONFIG_SYS_NUM_FM1_10GEC; i++) {
+		idx = i - FM1_10GEC1;
+		switch (fm_info_get_enet_if(i)) {
+		case PHY_INTERFACE_MODE_XGMII:
+			if (srds_s1 == 0x51) {
+				lane = serdes_get_first_lane(FSL_SRDS_1,
+						XAUI_FM1_MAC9 + idx);
+			} else if ((srds_s1 == 0x5f) || (srds_s1 == 0x65)) {
+				lane = serdes_get_first_lane(FSL_SRDS_1,
+						HIGIG_FM1_MAC9 + idx);
+			} else {
+				if (i == FM1_10GEC1 || i == FM1_10GEC2)
+					lane = serdes_get_first_lane(FSL_SRDS_1,
+						XFI_FM1_MAC9 + idx);
+				else
+					lane = serdes_get_first_lane(FSL_SRDS_1,
+						XFI_FM1_MAC1 + idx);
+			}
+
+			if (lane < 0)
+				break;
+			mdio_mux[i] = EMI2;
+			fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
+
+			if ((srds_s1 == 0x66) || (srds_s1 == 0x6b) ||
+			    (srds_s1 == 0x6c) || (srds_s1 == 0x6d) ||
+			    (srds_s1 == 0x71)) {
+				/* As XFI is in cage intead of a slot, so
+				 * ensure doesn't disable the corresponding port
+				 */
+				break;
+			}
+
+			slot = lane_to_slot[lane];
+			if (QIXIS_READ(present2) & (1 << (slot - 1)))
+				fm_disable_port(i);
+			break;
+		default:
+			break;
+		}
+	}
+
+	cpu_eth_init(bis);
+#endif /* CONFIG_FMAN_ENET */
+
+	return pci_eth_init(bis);
+}
diff --git a/board/freescale/t208xqds/law.c b/board/freescale/t208xqds/law.c
new file mode 100644
index 0000000000..74e2a53a8f
--- /dev/null
+++ b/board/freescale/t208xqds/law.c
@@ -0,0 +1,34 @@
+/*
+ * Copyright 2008-2012 Freescale Semiconductor, Inc.
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/fsl_law.h>
+#include <asm/mmu.h>
+
+struct law_entry law_table[] = {
+	SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_IFC),
+#ifdef CONFIG_SYS_BMAN_MEM_PHYS
+	SET_LAW(CONFIG_SYS_BMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_BMAN),
+#endif
+#ifdef CONFIG_SYS_QMAN_MEM_PHYS
+	SET_LAW(CONFIG_SYS_QMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_QMAN),
+#endif
+#ifdef QIXIS_BASE_PHYS
+	SET_LAW(QIXIS_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_IFC),
+#endif
+#ifdef CONFIG_SYS_DCSRBAR_PHYS
+	/* Limit DCSR to 32M to access NPC Trace Buffer */
+	SET_LAW(CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_DCSR),
+#endif
+#ifdef CONFIG_SYS_NAND_BASE_PHYS
+	SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_IFC),
+#endif
+};
+
+int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/board/freescale/t208xqds/pci.c b/board/freescale/t208xqds/pci.c
new file mode 100644
index 0000000000..84a89dad4f
--- /dev/null
+++ b/board/freescale/t208xqds/pci.c
@@ -0,0 +1,23 @@
+/*
+ * Copyright 2007-2013 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <command.h>
+#include <pci.h>
+#include <asm/fsl_pci.h>
+#include <libfdt.h>
+#include <fdt_support.h>
+#include <asm/fsl_serdes.h>
+
+void pci_init_board(void)
+{
+	fsl_pcie_init_board(0);
+}
+
+void pci_of_setup(void *blob, bd_t *bd)
+{
+	FT_FSL_PCI_SETUP;
+}
diff --git a/board/freescale/t208xqds/t2080_rcw.cfg b/board/freescale/t208xqds/t2080_rcw.cfg
new file mode 100644
index 0000000000..c2ad0fda55
--- /dev/null
+++ b/board/freescale/t208xqds/t2080_rcw.cfg
@@ -0,0 +1,8 @@
+#PBL preamble and RCW header
+aa55aa55 010e0100
+#SerDes Protocol: 0x66_0x16
+#Core/DDR: 1533Mhz/2133MT/s
+12100017 15000000 00000000 00000000
+66160002 00008400 e8104000 c1000000
+00000000 00000000 00000000 000307fc
+00000000 00000000 00000000 00000004
diff --git a/board/freescale/t208xqds/t2081_rcw.cfg b/board/freescale/t208xqds/t2081_rcw.cfg
new file mode 100644
index 0000000000..a2d5ecf4ad
--- /dev/null
+++ b/board/freescale/t208xqds/t2081_rcw.cfg
@@ -0,0 +1,8 @@
+#PBL preamble and RCW header
+aa55aa55 010e0100
+#Default SerDes Protocol: 0x6C
+#Core/DDR: 1533Mhz/2133MT/s
+12100017 15000000 00000000 00000000
+6c000002 00008000 e8104000 c1000000
+00000000 00000000 00000000 000307fc
+00000000 00000000 00000000 00000004
diff --git a/board/freescale/t208xqds/t208x_pbi.cfg b/board/freescale/t208xqds/t208x_pbi.cfg
new file mode 100644
index 0000000000..e200d926fb
--- /dev/null
+++ b/board/freescale/t208xqds/t208x_pbi.cfg
@@ -0,0 +1,41 @@
+#
+# Copyright 2013 Freescale Semiconductor, Inc.
+#
+# SPDX-License-Identifier:      GPL-2.0+
+#
+# Refer doc/README.pblimage for more details about how-to configure
+# and create PBL boot image
+#
+
+#PBI commands
+#Initialize CPC1
+09010000 00200400
+09138000 00000000
+091380c0 00000100
+#512KB SRAM
+09010100 00000000
+09010104 fff80009
+09010f00 08000000
+#enable CPC1
+09010000 80000000
+#Configure LAW for CPC1
+09000d00 00000000
+09000d04 fff80000
+09000d08 81000012
+#Initialize eSPI controller, default configuration is slow for eSPI to
+#load data, this configuration comes from u-boot eSPI driver.
+09110000 80000403
+09110020 2d170008
+09110024 00100008
+09110028 00100008
+0911002c 00100008
+#Errata for slowing down the MDC clock to make it <= 2.5 MHZ
+094fc030 00008148
+094fd030 00008148
+#Configure alternate space
+09000010 00000000
+09000014 ff000000
+09000018 81000000
+#Flush PBL data
+09138000 00000000
+091380c0 00000000
diff --git a/board/freescale/t208xqds/t208xqds.c b/board/freescale/t208xqds/t208xqds.c
new file mode 100644
index 0000000000..9cfc0bd7c3
--- /dev/null
+++ b/board/freescale/t208xqds/t208xqds.c
@@ -0,0 +1,459 @@
+/*
+ * Copyright 2009-2013 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#include <common.h>
+#include <command.h>
+#include <i2c.h>
+#include <netdev.h>
+#include <linux/compiler.h>
+#include <asm/mmu.h>
+#include <asm/processor.h>
+#include <asm/immap_85xx.h>
+#include <asm/fsl_law.h>
+#include <asm/fsl_serdes.h>
+#include <asm/fsl_portals.h>
+#include <asm/fsl_liodn.h>
+#include <fm_eth.h>
+
+#include "../common/qixis.h"
+#include "../common/vsc3316_3308.h"
+#include "t208xqds.h"
+#include "t208xqds_qixis.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int checkboard(void)
+{
+	char buf[64];
+	u8 sw;
+	struct cpu_type *cpu = gd->arch.cpu;
+	static const char *freq[4] = {
+		"100.00MHZ(from 8T49N222A)", "125.00MHz",
+		"156.25MHZ", "100.00MHz"
+	};
+
+	printf("Board: %sQDS, ", cpu->name);
+	sw = QIXIS_READ(arch);
+	printf("Sys ID: 0x%02x, Board Arch: V%d, ", QIXIS_READ(id), sw >> 4);
+	printf("Board Version: %c, boot from ", (sw & 0xf) + 'A' - 1);
+
+#ifdef CONFIG_SDCARD
+	puts("SD/MMC\n");
+#elif CONFIG_SPIFLASH
+	puts("SPI\n");
+#else
+	sw = QIXIS_READ(brdcfg[0]);
+	sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
+
+	if (sw < 0x8)
+		printf("vBank%d\n", sw);
+	else if (sw == 0x8)
+		puts("Promjet\n");
+	else if (sw == 0x9)
+		puts("NAND\n");
+	else
+		printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
+#endif
+
+	printf("FPGA: v%d (%s), build %d", (int)QIXIS_READ(scver),
+	       qixis_read_tag(buf), (int)qixis_read_minor());
+	/* the timestamp string contains "\n" at the end */
+	printf(" on %s", qixis_read_time(buf));
+
+	puts("SERDES Reference Clocks:\n");
+	sw = QIXIS_READ(brdcfg[2]);
+	printf("SD1_CLK1=%s, SD1_CLK2=%s\n", freq[sw >> 6],
+	       freq[(sw >> 4) & 0x3]);
+	printf("SD2_CLK1=%s, SD2_CLK2=%s\n", freq[(sw & 0xf) >> 2],
+	       freq[sw & 0x3]);
+
+	return 0;
+}
+
+int select_i2c_ch_pca9547(u8 ch)
+{
+	int ret;
+
+	ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
+	if (ret) {
+		puts("PCA: failed to select proper channel\n");
+		return ret;
+	}
+
+	return 0;
+}
+
+int brd_mux_lane_to_slot(void)
+{
+	ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+	u32 srds_prtcl_s1;
+
+	srds_prtcl_s1 = in_be32(&gur->rcwsr[4]) &
+				FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
+	srds_prtcl_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
+#if defined(CONFIG_T2080QDS)
+	u32 srds_prtcl_s2 = in_be32(&gur->rcwsr[4]) &
+				FSL_CORENET2_RCWSR4_SRDS2_PRTCL;
+	srds_prtcl_s2 >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT;
+#endif
+
+	switch (srds_prtcl_s1) {
+	case 0:
+		/* SerDes1 is not enabled */
+		break;
+#if defined(CONFIG_T2080QDS)
+	case 0x1c:
+	case 0xa2:
+		/* SD1(A:D) => SLOT3 SGMII
+		 * SD1(G:H) => SLOT1 SGMII
+		 */
+		QIXIS_WRITE(brdcfg[12], 0x1a);
+		break;
+	case 0x94:
+	case 0x95:
+		/* SD1(A:B) => SLOT3 SGMII@1.25bps
+		 * SD1(C:D) => SFP Module, SGMII@3.125bps
+		 * SD1(E:H) => SLOT1 SGMII@1.25bps
+		 */
+	case 0x96:
+		/* SD1(A:B) => SLOT3 SGMII@1.25bps
+		 * SD1(C)   => SFP Module, SGMII@3.125bps
+		 * SD1(D)   => SFP Module, SGMII@1.25bps
+		 * SD1(E:H) => SLOT1 PCIe4 x4
+		 */
+		QIXIS_WRITE(brdcfg[12], 0x3a);
+		break;
+	case 0x51:
+		/* SD1(A:D) => SLOT3 XAUI
+		 * SD1(E)   => SLOT1 PCIe4
+		 * SD1(F:H) => SLOT2 SGMII
+		 */
+		QIXIS_WRITE(brdcfg[12], 0x15);
+		break;
+	case 0x66:
+	case 0x67:
+		/* SD1(A:D) => XFI cage
+		 * SD1(E:H) => SLOT1 PCIe4
+		 */
+		QIXIS_WRITE(brdcfg[12], 0xfe);
+		break;
+	case 0x6b:
+		/* SD1(A:D) => XFI cage
+		 * SD1(E)   => SLOT1 PCIe4
+		 * SD1(F:H) => SLOT2 SGMII
+		 */
+		QIXIS_WRITE(brdcfg[12], 0xf1);
+		break;
+	case 0x6c:
+	case 0x6d:
+		/* SD1(A:B) => XFI cage
+		 * SD1(C:D) => SLOT3 SGMII
+		 * SD1(E:H) => SLOT1 PCIe4
+		 */
+		QIXIS_WRITE(brdcfg[12], 0xda);
+		break;
+	case 0x6e:
+		/* SD1(A:B) => SFP Module, XFI
+		 * SD1(C:D) => SLOT3 SGMII
+		 * SD1(E:F) => SLOT1 PCIe4 x2
+		 * SD1(G:H) => SLOT2 SGMII
+		 */
+		QIXIS_WRITE(brdcfg[12], 0xd9);
+		break;
+	case 0xda:
+		/* SD1(A:H) => SLOT3 PCIe3 x8
+		 */
+		 QIXIS_WRITE(brdcfg[12], 0x0);
+		 break;
+	case 0xc8:
+		/* SD1(A)   => SLOT3 PCIe3 x1
+		 * SD1(B)   => SFP Module, SGMII@1.25bps
+		 * SD1(C:D) => SFP Module, SGMII@3.125bps
+		 * SD1(E:F) => SLOT1 PCIe4 x2
+		 * SD1(G:H) => SLOT2 SGMII
+		 */
+		 QIXIS_WRITE(brdcfg[12], 0x79);
+		 break;
+	case 0xab:
+		/* SD1(A:D) => SLOT3 PCIe3 x4
+		 * SD1(E:H) => SLOT1 PCIe4 x4
+		 */
+		 QIXIS_WRITE(brdcfg[12], 0x1a);
+		 break;
+#elif defined(CONFIG_T2081QDS)
+	case 0x51:
+		/* SD1(A:D) => SLOT2 XAUI
+		 * SD1(E)   => SLOT1 PCIe4 x1
+		 * SD1(F:H) => SLOT3 SGMII
+		 */
+		QIXIS_WRITE(brdcfg[12], 0x98);
+		QIXIS_WRITE(brdcfg[13], 0x70);
+		break;
+	case 0x6b:
+		/* SD1(A:D) => XFI SFP Module
+		 * SD1(E)   => SLOT1 PCIe4 x1
+		 * SD1(F:H) => SLOT3 SGMII
+		 */
+		QIXIS_WRITE(brdcfg[12], 0x80);
+		QIXIS_WRITE(brdcfg[13], 0x70);
+		break;
+	case 0x6c:
+		/* SD1(A:B) => XFI SFP Module
+		 * SD1(C:D) => SLOT2 SGMII
+		 * SD1(E:H) => SLOT1 PCIe4 x4
+		 */
+		QIXIS_WRITE(brdcfg[12], 0xe8);
+		QIXIS_WRITE(brdcfg[13], 0x0);
+		break;
+	case 0x6d:
+		/* SD1(A:B) => XFI SFP Module
+		 * SD1(C:D) => SLOT2 SGMII
+		 * SD1(E:H) => SLOT1 PCIe4 x4
+		 */
+		QIXIS_WRITE(brdcfg[12], 0xe8);
+		QIXIS_WRITE(brdcfg[13], 0x0);
+		break;
+	case 0xaa:
+	case 0xab:
+		/* SD1(A:D) => SLOT2 PCIe3 x4
+		 * SD1(F:H) => SLOT1 SGMI4 x4
+		 */
+		QIXIS_WRITE(brdcfg[12], 0xf8);
+		QIXIS_WRITE(brdcfg[13], 0x0);
+		break;
+	case 0xca:
+	case 0xcb:
+		/* SD1(A)   => SLOT2 PCIe3 x1
+		 * SD1(B)   => SLOT7 SGMII
+		 * SD1(C)   => SLOT6 SGMII
+		 * SD1(D)   => SLOT5 SGMII
+		 * SD1(E)   => SLOT1 PCIe4 x1
+		 * SD1(F:H) => SLOT3 SGMII
+		 */
+		QIXIS_WRITE(brdcfg[12], 0x80);
+		QIXIS_WRITE(brdcfg[13], 0x70);
+		break;
+	case 0xde:
+	case 0xdf:
+		/* SD1(A:D) => SLOT2 PCIe3 x4
+		 * SD1(E)   => SLOT1 PCIe4 x1
+		 * SD1(F)   => SLOT4 PCIe1 x1
+		 * SD1(G)   => SLOT3 PCIe2 x1
+		 * SD1(H)   => SLOT7 SGMII
+		 */
+		QIXIS_WRITE(brdcfg[12], 0x98);
+		QIXIS_WRITE(brdcfg[13], 0x25);
+		break;
+	case 0xf2:
+		/* SD1(A)   => SLOT2 PCIe3 x1
+		 * SD1(B:D) => SLOT7 SGMII
+		 * SD1(E)   => SLOT1 PCIe4 x1
+		 * SD1(F)   => SLOT4 PCIe1 x1
+		 * SD1(G)   => SLOT3 PCIe2 x1
+		 * SD1(H)   => SLOT7 SGMII
+		 */
+		QIXIS_WRITE(brdcfg[12], 0x81);
+		QIXIS_WRITE(brdcfg[13], 0xa5);
+		break;
+#endif
+	default:
+		printf("WARNING: unsupported for SerDes1 Protocol %d\n",
+		       srds_prtcl_s1);
+		return -1;
+	}
+
+#ifdef CONFIG_T2080QDS
+	switch (srds_prtcl_s2) {
+	case 0:
+		/* SerDes2 is not enabled */
+		break;
+	case 0x01:
+	case 0x02:
+		/* SD2(A:H) => SLOT4 PCIe1 */
+		QIXIS_WRITE(brdcfg[13], 0x10);
+		break;
+	case 0x15:
+	case 0x16:
+		/*
+		 * SD2(A:D) => SLOT4 PCIe1
+		 * SD2(E:F) => SLOT5 PCIe2
+		 * SD2(G:H) => SATA1,SATA2
+		 */
+		QIXIS_WRITE(brdcfg[13], 0xb0);
+		break;
+	case 0x18:
+		/*
+		 * SD2(A:D) => SLOT4 PCIe1
+		 * SD2(E:F) => SLOT5 Aurora
+		 * SD2(G:H) => SATA1,SATA2
+		 */
+		QIXIS_WRITE(brdcfg[13], 0x78);
+		break;
+	case 0x1f:
+		/*
+		 * SD2(A:D) => SLOT4 PCIe1
+		 * SD2(E:H) => SLOT5 PCIe2
+		 */
+		QIXIS_WRITE(brdcfg[13], 0xa0);
+		break;
+	case 0x29:
+	case 0x2d:
+	case 0x2e:
+		/*
+		 * SD2(A:D) => SLOT4 SRIO2
+		 * SD2(E:H) => SLOT5 SRIO1
+		 */
+		QIXIS_WRITE(brdcfg[13], 0xa0);
+		break;
+	case 0x36:
+		/*
+		 * SD2(A:D) => SLOT4 SRIO2
+		 * SD2(E:F) => Aurora
+		 * SD2(G:H) => SATA1,SATA2
+		 */
+		QIXIS_WRITE(brdcfg[13], 0x78);
+		break;
+	default:
+		printf("WARNING: unsupported for SerDes2 Protocol %d\n",
+		       srds_prtcl_s2);
+		return -1;
+	}
+#endif
+	return 0;
+}
+
+int board_early_init_r(void)
+{
+	const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
+	const u8 flash_esel = find_tlb_idx((void *)flashbase, 1);
+
+	/*
+	 * Remap Boot flash + PROMJET region to caching-inhibited
+	 * so that flash can be erased properly.
+	 */
+
+	/* Flush d-cache and invalidate i-cache of any FLASH data */
+	flush_dcache();
+	invalidate_icache();
+
+	/* invalidate existing TLB entry for flash + promjet */
+	disable_tlb(flash_esel);
+
+	set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
+		MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		0, flash_esel, BOOKE_PAGESZ_256M, 1);
+
+	set_liodns();
+#ifdef CONFIG_SYS_DPAA_QBMAN
+	setup_portals();
+#endif
+
+	/* Disable remote I2C connection to qixis fpga */
+	QIXIS_WRITE(brdcfg[5], QIXIS_READ(brdcfg[5]) & ~BRDCFG5_IRE);
+
+	brd_mux_lane_to_slot();
+	select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
+
+	return 0;
+}
+
+unsigned long get_board_sys_clk(void)
+{
+	u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
+#ifdef CONFIG_FSL_QIXIS_CLOCK_MEASUREMENT
+	/* use accurate clock measurement */
+	int freq = QIXIS_READ(clk_freq[0]) << 8 | QIXIS_READ(clk_freq[1]);
+	int base = QIXIS_READ(clk_base[0]) << 8 | QIXIS_READ(clk_base[1]);
+	u32 val;
+
+	val =  freq * base;
+	if (val) {
+		debug("SYS Clock measurement is: %d\n", val);
+		return val;
+	} else {
+		printf("Warning: SYS clock measurement is invalid, ");
+		printf("using value from brdcfg1.\n");
+	}
+#endif
+
+	switch (sysclk_conf & 0x0F) {
+	case QIXIS_SYSCLK_83:
+		return 83333333;
+	case QIXIS_SYSCLK_100:
+		return 100000000;
+	case QIXIS_SYSCLK_125:
+		return 125000000;
+	case QIXIS_SYSCLK_133:
+		return 133333333;
+	case QIXIS_SYSCLK_150:
+		return 150000000;
+	case QIXIS_SYSCLK_160:
+		return 160000000;
+	case QIXIS_SYSCLK_166:
+		return 166666666;
+	}
+	return 66666666;
+}
+
+unsigned long get_board_ddr_clk(void)
+{
+	u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
+#ifdef CONFIG_FSL_QIXIS_CLOCK_MEASUREMENT
+	/* use accurate clock measurement */
+	int freq = QIXIS_READ(clk_freq[2]) << 8 | QIXIS_READ(clk_freq[3]);
+	int base = QIXIS_READ(clk_base[0]) << 8 | QIXIS_READ(clk_base[1]);
+	u32 val;
+
+	val =  freq * base;
+	if (val) {
+		debug("DDR Clock measurement is: %d\n", val);
+		return val;
+	} else {
+		printf("Warning: DDR clock measurement is invalid, ");
+		printf("using value from brdcfg1.\n");
+	}
+#endif
+
+	switch ((ddrclk_conf & 0x30) >> 4) {
+	case QIXIS_DDRCLK_100:
+		return 100000000;
+	case QIXIS_DDRCLK_125:
+		return 125000000;
+	case QIXIS_DDRCLK_133:
+		return 133333333;
+	}
+	return 66666666;
+}
+
+int misc_init_r(void)
+{
+	return 0;
+}
+
+void ft_board_setup(void *blob, bd_t *bd)
+{
+	phys_addr_t base;
+	phys_size_t size;
+
+	ft_cpu_setup(blob, bd);
+
+	base = getenv_bootm_low();
+	size = getenv_bootm_size();
+
+	fdt_fixup_memory(blob, (u64)base, (u64)size);
+
+#ifdef CONFIG_PCI
+	pci_of_setup(blob, bd);
+#endif
+
+	fdt_fixup_liodn(blob);
+	fdt_fixup_dr_usb(blob, bd);
+
+#ifdef CONFIG_SYS_DPAA_FMAN
+	fdt_fixup_fman_ethernet(blob);
+	fdt_fixup_board_enet(blob);
+#endif
+}
diff --git a/board/freescale/t208xqds/t208xqds.h b/board/freescale/t208xqds/t208xqds.h
new file mode 100644
index 0000000000..39fcef28c3
--- /dev/null
+++ b/board/freescale/t208xqds/t208xqds.h
@@ -0,0 +1,13 @@
+/*
+ * Copyright 2011-2013 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CORENET_DS_H__
+#define __CORENET_DS_H__
+
+void fdt_fixup_board_enet(void *blob);
+void pci_of_setup(void *blob, bd_t *bd);
+
+#endif
diff --git a/board/freescale/t208xqds/t208xqds_qixis.h b/board/freescale/t208xqds/t208xqds_qixis.h
new file mode 100644
index 0000000000..bdcdc12f59
--- /dev/null
+++ b/board/freescale/t208xqds/t208xqds_qixis.h
@@ -0,0 +1,49 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#ifndef __T208xQDS_QIXIS_H__
+#define __T208xQDS_QIXIS_H__
+
+/* Definitions of QIXIS Registers for T208xQDS */
+
+#define QIXIS_SRDS1CLK_122		0x5a
+#define QIXIS_SRDS1CLK_125		0x5e
+
+
+/* BRDCFG4[4:7]] select EC1 and EC2 as a pair */
+#define BRDCFG4_EMISEL_MASK             0xE0
+#define BRDCFG4_EMISEL_SHIFT            5
+
+/* SYSCLK */
+#define QIXIS_SYSCLK_66                 0x0
+#define QIXIS_SYSCLK_83                 0x1
+#define QIXIS_SYSCLK_100                0x2
+#define QIXIS_SYSCLK_125                0x3
+#define QIXIS_SYSCLK_133                0x4
+#define QIXIS_SYSCLK_150                0x5
+#define QIXIS_SYSCLK_160                0x6
+#define QIXIS_SYSCLK_166                0x7
+
+/* DDRCLK */
+#define QIXIS_DDRCLK_66                 0x0
+#define QIXIS_DDRCLK_100                0x1
+#define QIXIS_DDRCLK_125                0x2
+#define QIXIS_DDRCLK_133                0x3
+
+#define BRDCFG5_IRE                     0x20    /* i2c Remote i2c1 enable */
+
+#define BRDCFG9_SFP_TX_EN		0x10
+
+#define BRDCFG12_SD3EN_MASK             0x20
+#define BRDCFG12_SD3MX_MASK             0x08
+#define BRDCFG12_SD3MX_SLOT5            0x08
+#define BRDCFG12_SD3MX_SLOT6            0x00
+#define BRDCFG12_SD4EN_MASK             0x04
+#define BRDCFG12_SD4MX_MASK             0x03
+#define BRDCFG12_SD4MX_SLOT7            0x02
+#define BRDCFG12_SD4MX_SLOT8            0x01
+#define BRDCFG12_SD4MX_AURO_SATA        0x00
+#endif
diff --git a/board/freescale/t208xqds/tlb.c b/board/freescale/t208xqds/tlb.c
new file mode 100644
index 0000000000..62cd11033a
--- /dev/null
+++ b/board/freescale/t208xqds/tlb.c
@@ -0,0 +1,146 @@
+/*
+ * Copyright 2008-2013 Freescale Semiconductor, Inc.
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/mmu.h>
+
+struct fsl_e_tlb_entry tlb_table[] = {
+	/* TLB 0 - for temp stack in cache */
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR,
+		      CONFIG_SYS_INIT_RAM_ADDR_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 0, BOOKE_PAGESZ_4K, 0),
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
+		      CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 0, BOOKE_PAGESZ_4K, 0),
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
+		      CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 0, BOOKE_PAGESZ_4K, 0),
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
+		      CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 0, BOOKE_PAGESZ_4K, 0),
+
+	/* TLB 1 */
+	/* *I*** - Covers boot page */
+#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L3_ADDR)
+	/*
+	 * *I*G - L3SRAM. When L3 is used as 1M SRAM, the address of the
+	 * SRAM is at 0xfff00000, it covered the 0xfffff000.
+	 */
+	SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 0, BOOKE_PAGESZ_1M, 1),
+#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
+	/*
+	 * SRIO_PCIE_BOOT-SLAVE. When slave boot, the address of the
+	 * space is at 0xfff00000, it covered the 0xfffff000.
+	 */
+	SET_TLB_ENTRY(1, CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR,
+		      CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_W|MAS2_G,
+		      0, 0, BOOKE_PAGESZ_1M, 1),
+#else
+	SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 0, BOOKE_PAGESZ_4K, 1),
+#endif
+
+	/* *I*G* - CCSRBAR */
+	SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 1, BOOKE_PAGESZ_16M, 1),
+
+	/* *I*G* - Flash, localbus */
+	/* This will be changed to *I*G* after relocation to RAM. */
+	SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
+		      MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
+		      0, 2, BOOKE_PAGESZ_256M, 1),
+
+	/* *I*G* - PCIe 1, 0x80000000 */
+	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 3, BOOKE_PAGESZ_512M, 1),
+
+	/* *I*G* - PCIe 2, 0xa0000000 */
+	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE2_MEM_VIRT, CONFIG_SYS_PCIE2_MEM_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 4, BOOKE_PAGESZ_256M, 1),
+
+	/* *I*G* - PCIe 3, 0xb0000000 */
+	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT, CONFIG_SYS_PCIE3_MEM_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 5, BOOKE_PAGESZ_256M, 1),
+
+
+	/* *I*G* - PCIe 4, 0xc0000000 */
+	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE4_MEM_VIRT, CONFIG_SYS_PCIE4_MEM_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 6, BOOKE_PAGESZ_256M, 1),
+
+	/* *I*G* - PCI I/O */
+	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 7, BOOKE_PAGESZ_256K, 1),
+
+	/* Bman/Qman */
+#ifdef CONFIG_SYS_BMAN_MEM_PHYS
+	SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE, CONFIG_SYS_BMAN_MEM_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 9, BOOKE_PAGESZ_16M, 1),
+	SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE + 0x01000000,
+		      CONFIG_SYS_BMAN_MEM_PHYS + 0x01000000,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 10, BOOKE_PAGESZ_16M, 1),
+#endif
+#ifdef CONFIG_SYS_QMAN_MEM_PHYS
+	SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE, CONFIG_SYS_QMAN_MEM_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 11, BOOKE_PAGESZ_16M, 1),
+	SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE + 0x01000000,
+		      CONFIG_SYS_QMAN_MEM_PHYS + 0x01000000,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 12, BOOKE_PAGESZ_16M, 1),
+#endif
+#ifdef CONFIG_SYS_DCSRBAR_PHYS
+	SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 13, BOOKE_PAGESZ_32M, 1),
+#endif
+#ifdef CONFIG_SYS_NAND_BASE
+	/*
+	 * *I*G - NAND
+	 * entry 14 and 15 has been used hard coded, they will be disabled
+	 * in cpu_init_f, so we use entry 16 for nand.
+	 */
+	SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 16, BOOKE_PAGESZ_64K, 1),
+#endif
+#ifdef QIXIS_BASE_PHYS
+	SET_TLB_ENTRY(1, QIXIS_BASE, QIXIS_BASE_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 17, BOOKE_PAGESZ_4K, 1),
+#endif
+#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
+	/*
+	 * SRIO_PCIE_BOOT-SLAVE. 1M space from 0xffe00000 for
+	 * fetching ucode and ENV from master
+	 */
+	SET_TLB_ENTRY(1, CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR,
+		      CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_G,
+		      0, 18, BOOKE_PAGESZ_1M, 1),
+#endif
+
+};
+
+int num_tlb_entries = ARRAY_SIZE(tlb_table);
diff --git a/board/freescale/t208xrdb/Makefile b/board/freescale/t208xrdb/Makefile
new file mode 100644
index 0000000000..092c9ff0dc
--- /dev/null
+++ b/board/freescale/t208xrdb/Makefile
@@ -0,0 +1,13 @@
+#
+# Copyright 2014 Freescale Semiconductor, Inc.
+#
+# SPDX-License-Identifier:      GPL-2.0+
+#
+
+obj-$(CONFIG_T2080RDB) += t208xrdb.o
+obj-$(CONFIG_T2080RDB) += eth_t208xrdb.o
+obj-$(CONFIG_T2080RDB) += cpld.o
+obj-$(CONFIG_PCI)      += pci.o
+obj-y   += ddr.o
+obj-y   += law.o
+obj-y   += tlb.o
diff --git a/board/freescale/t208xrdb/README b/board/freescale/t208xrdb/README
new file mode 100644
index 0000000000..0012c6cb40
--- /dev/null
+++ b/board/freescale/t208xrdb/README
@@ -0,0 +1,208 @@
+T2080PCIe-RDB is a Freescale Reference Design Board that hosts the T2080 SoC.
+It can work in two mode: standalone mode and PCIe endpoint mode.
+
+T2080 SoC Overview
+------------------
+The T2080 QorIQ multicore processor combines four dual-threaded e6500 Power
+Architecture processor cores with high-performance datapath acceleration
+logic and network and peripheral bus interfaces required for networking,
+telecom/datacom, wireless infrastructure, and mil/aerospace applications.
+
+T2080 includes the following functions and features:
+ - Four dual-threads 64-bit Power architecture e6500 cores, up to 1.8GHz
+ - 2MB L2 cache and 512KB CoreNet platform cache (CPC)
+ - Hierarchical interconnect fabric
+ - One 32-/64-bit DDR3/3L SDRAM memory controllers with ECC and interleaving
+ - Data Path Acceleration Architecture (DPAA) incorporating acceleration
+ - 16 SerDes lanes up to 10.3125 GHz
+ - 8 Ethernet interfaces, supporting combinations of the following:
+   - Up to four 10 Gbps Ethernet MACs
+   - Up to eight 1 Gbps Ethernet MACs
+   - Up to four 2.5 Gbps Ethernet MACs
+ - High-speed peripheral interfaces
+   - Four PCI Express controllers (two PCIe 2.0 and two PCIe 3.0 with SR-IOV)
+   - Two Serial RapidIO 2.0 controllers/ports running at up to 5 GHz
+ - Additional peripheral interfaces
+   - Two serial ATA (SATA 2.0) controllers
+   - Two high-speed USB 2.0 controllers with integrated PHY
+   - Enhanced secure digital host controller (SD/SDHC/SDXC/eMMC)
+   - Enhanced serial peripheral interface (eSPI)
+   - Four I2C controllers
+   - Four 2-pin UARTs or two 4-pin UARTs
+   - Integrated Flash Controller supporting NAND and NOR flash
+ - Three eight-channel DMA engines
+ - Support for hardware virtualization and partitioning enforcement
+ - QorIQ Platform's Trust Architecture 2.0
+
+Differences between T2080 and T2081
+-----------------------------------
+  Feature		T2080	 T2081
+  1G Ethernet numbers:  8	 6
+  10G Ethernet numbers: 4	 2
+  SerDes lanes:		16	 8
+  Serial RapidIO,RMan:  2	 no
+  SATA Controller:	2	 no
+  Aurora:		yes	 no
+  SoC Package:		896-pins 780-pins
+
+
+T2080PCIe-RDB board Overview
+----------------------------
+ - SERDES Configuration
+     - SerDes-1 Lane A-B: to two 10G XFI fiber (MAC9 & MAC10)
+     - SerDes-1 Lane C-D: to two 10G Base-T (MAC1 & MAC2)
+     - SerDes-1 Lane E-H: to PCIe Goldfinger (PCIe4 x4, Gen3)
+     - SerDes-2 Lane A-D: to PCIe Slot (PCIe1 x4, Gen2)
+     - SerDes-2 Lane E-F: to C293 secure co-processor (PCIe2 x2)
+     - SerDes-2 Lane G-H: to SATA1 & SATA2
+ - Ethernet
+     - Two on-board 10M/100M/1G RGMII ethernet ports
+     - Two on-board 10Gbps XFI fiber ports
+     - Two on-board 10Gbps Base-T copper ports
+ - DDR Memory
+     - Supports 72bit 4GB DDR3-LP SODIMM
+ - PCIe
+     - One PCIe x4 gold-finger
+     - One PCIe x4 connector
+     - One PCIe x2 end-point device (C293 Crypto co-processor)
+ - IFC/Local Bus
+     - NOR:  128MB 16-bit NOR Flash
+     - NAND: 512MB 8-bit NAND flash
+     - CPLD: for system controlling with programable header on-board
+ - SATA
+     - Two SATA 2.0 onnectors on-board
+ - USB
+     - Supports two USB 2.0 ports with integrated PHYs
+     - Two type A ports with 5V@1.5A per port.
+ - SDHC
+     - one TF-card connector on-board
+ - SPI
+     -  On-board 64MB SPI flash
+ - Other
+     - Two Serial ports
+     - Four I2C ports
+
+
+System Memory map
+-----------------
+Start Address  End Address      Description			Size
+0xF_FFDF_0000  0xF_FFDF_0FFF    IFC - CPLD			4KB
+0xF_FF80_0000  0xF_FF80_FFFF    IFC - NAND Flash		64KB
+0xF_FE00_0000  0xF_FEFF_FFFF    CCSRBAR				16MB
+0xF_F803_0000  0xF_F803_FFFF    PCI Express 4 I/O Space		64KB
+0xF_F802_0000  0xF_F802_FFFF    PCI Express 3 I/O Space		64KB
+0xF_F801_0000  0xF_F801_FFFF    PCI Express 2 I/O Space		64KB
+0xF_F800_0000  0xF_F800_FFFF    PCI Express 1 I/O Space		64KB
+0xF_F600_0000  0xF_F7FF_FFFF    Queue manager software portal	32MB
+0xF_F400_0000  0xF_F5FF_FFFF    Buffer manager software portal	32MB
+0xF_E800_0000  0xF_EFFF_FFFF    IFC - NOR Flash			128MB
+0xF_0000_0000  0xF_003F_FFFF    DCSR				4MB
+0xC_4000_0000  0xC_4FFF_FFFF    PCI Express 4 Mem Space		256MB
+0xC_3000_0000  0xC_3FFF_FFFF    PCI Express 3 Mem Space		256MB
+0xC_2000_0000  0xC_2FFF_FFFF    PCI Express 2 Mem Space		256MB
+0xC_0000_0000  0xC_1FFF_FFFF    PCI Express 1 Mem Space		512MB
+0x0_0000_0000  0x0_ffff_ffff    DDR				4GB
+
+
+128M NOR Flash memory Map
+-------------------------
+Start Address   End Address	Definition			Max size
+0xEFF40000	0xEFFFFFFF	u-boot (current bank)		768KB
+0xEFF20000	0xEFF3FFFF	u-boot env (current bank)	128KB
+0xEFF00000	0xEFF1FFFF	FMAN Ucode (current bank)	128KB
+0xEFE00000	0xEFE3FFFF	PHY CS4315 firmware		256KB
+0xED300000	0xEFEFFFFF	rootfs (alt bank)		44MB
+0xEC800000	0xEC8FFFFF	Hardware device tree (alt bank)	1MB
+0xEC020000	0xEC7FFFFF	Linux.uImage (alt bank)		7MB + 875KB
+0xEC000000	0xEC01FFFF	RCW (alt bank)			128KB
+0xEBF40000	0xEBFFFFFF	u-boot (alt bank)		768KB
+0xEBF20000	0xEBF3FFFF	u-boot env (alt bank)		128KB
+0xEBF00000	0xEBF1FFFF	FMAN ucode (alt bank)		128KB
+0xEBE00000	0xEBE3FFFF	PHY CS4315 firmware (alt bank)	256KB
+0xE9300000	0xEBEFFFFF	rootfs (current bank)		44MB
+0xE8800000	0xE88FFFFF	Hardware device tree (cur bank)	11MB + 512KB
+0xE8020000	0xE86FFFFF	Linux.uImage (current bank)	7MB + 875KB
+0xE8000000	0xE801FFFF	RCW (current bank)		128KB
+
+
+T2080PCIe-RDB Ethernet Port Map
+-------------------------------
+Label    In Uboot      In Linux     FMan Address   Comments    PHY
+ETH0     FM1@GTEC1     fm1-mac9     0xfe4f0000     10G SFP+   (CS4315)
+ETH1     FM1@GTEC2     fm1-mac10    0xfe4f2000     10G SFP+   (CS4315)
+ETH2     FM1@GTEC3     fm1-mac1     0xfe4e0000     10G Base-T (AQ1202)
+ETH3     FM1@GTEC4     fm1-mac2     0xfe4e2000     10G Base-T (AQ1202)
+ETH4     FM1@DTSEC3    fm1-mac3     0xfe4e4000     1G  RGMII  (RTL8211E)
+ETH5     FM1@DTSEC4    fm1-mac4     0xfe4e6000     1G  RGMII  (RTL8211E)
+
+
+T2080PCIe-RDB Default DIP-Switch setting
+----------------------------------------
+SW1[1:8] = '00010011'
+SW2[1:8] = '10111111'
+SW3[1:8] = '11100001'
+
+Software configurations and board settings
+------------------------------------------
+1. NOR boot:
+   a. build NOR boot image
+	$ make T2080RDB
+   b. program u-boot.bin image to NOR flash
+	=> tftp 1000000 u-boot.bin
+	=> pro off all;era eff40000 efffffff;cp.b 1000000 eff40000 $filesize
+	set SW1[1:8] = '00010011', SW2[1] = '1', SW3[4] = '0' for NOR boot
+
+   Switching between default bank and alternate bank on NOR flash
+   To change boot source to vbank4:
+	via software:   run command 'cpld reset altbank' in u-boot.
+	via DIP-switch: set SW3[5:7] = '011'
+
+   To change boot source to vbank0:
+	via software:   run command 'cpld reset' in u-boot.
+	via DIP-Switch: set SW3[5:7] = '111'
+
+2. NAND Boot:
+   a. build PBL image for NAND boot
+	$ make T2080RDB_NAND_config
+	$ make u-boot.pbl
+   b. program u-boot.pbl to NAND flash
+	=> tftp 1000000 u-boot.pbl
+	=> nand erase 0 d0000
+	=> nand write 1000000 0 $filesize
+	set SW1[1:8] = '10000010', SW2[1] = '1', SW3[4] = '1' for NAND boot
+
+3. SPI Boot:
+   a. build PBL image for SPI boot
+	$ make T2080RDB_SPIFLASH_config
+	$ make u-boot.pbl
+   b. program u-boot.pbl to SPI flash
+	=> tftp 1000000 u-boot.pbl
+	=> sf probe 0
+	=> sf erase 0 d0000
+	=> sf write 1000000 0 $filesize
+	set SW1[1:8] = '00100010', SW2[1] ='1' for SPI boot
+
+4. SD Boot:
+   a. build PBL image for SD boot
+	$ make T2080RDB_SDCARD_config
+	$ make u-boot.pbl
+   b. program u-boot.pbl to TF card
+	=> tftp 1000000 u-boot.pbl
+	=> mmc write 1000000 8 1650
+	set SW1[1:8] = '00100000', SW2[1] = '0' for SD boot
+
+
+How to update the ucode of Cortina CS4315/CS4340 10G PHY
+--------------------------------------------------------
+=> tftp 1000000 CS4315-CS4340-PHY-ucode.txt
+=> pro off all;era 0xefe00000 0xefefffff;cp.b 1000000 0xefe00000 $filesize
+
+
+How to update the ucode of Freescale FMAN
+-----------------------------------------
+=> tftp 1000000 fsl_fman_ucode_t2080_r1.0.bin
+=> pro off all;erase 0xeff00000 0xeff1ffff;cp 1000000 0xeff00000 $filesize
+
+
+For more details, please refer to T2080PCIe-RDB User Guide and access
+website www.freescale.com and Freescale QorIQ SDK Infocenter document.
diff --git a/board/freescale/t208xrdb/cpld.c b/board/freescale/t208xrdb/cpld.c
new file mode 100644
index 0000000000..4aa126be54
--- /dev/null
+++ b/board/freescale/t208xrdb/cpld.c
@@ -0,0 +1,71 @@
+/*
+ * Copyright 2014 Freescale Semiconductor
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ *
+ * Freescale T2080RDB board-specific CPLD controlling supports.
+ */
+
+#include <common.h>
+#include <command.h>
+#include "cpld.h"
+
+u8 cpld_read(unsigned int reg)
+{
+	void *p = (void *)CONFIG_SYS_CPLD_BASE;
+
+	return in_8(p + reg);
+}
+
+void cpld_write(unsigned int reg, u8 value)
+{
+	void *p = (void *)CONFIG_SYS_CPLD_BASE;
+
+	out_8(p + reg, value);
+}
+
+/* Set the boot bank to the alternate bank */
+void cpld_set_altbank(void)
+{
+	u8 reg = CPLD_READ(flash_csr);
+
+	reg = (reg & ~CPLD_BANK_SEL_MASK) | CPLD_LBMAP_ALTBANK;
+	CPLD_WRITE(flash_csr, reg);
+	CPLD_WRITE(reset_ctl, CPLD_LBMAP_RESET);
+}
+
+/* Set the boot bank to the default bank */
+void cpld_set_defbank(void)
+{
+	u8 reg = CPLD_READ(flash_csr);
+
+	reg = (reg & ~CPLD_BANK_SEL_MASK) | CPLD_LBMAP_DFLTBANK;
+	CPLD_WRITE(flash_csr, reg);
+	CPLD_WRITE(reset_ctl, CPLD_LBMAP_RESET);
+}
+
+int do_cpld(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	int rc = 0;
+
+	if (argc <= 1)
+		return cmd_usage(cmdtp);
+
+	if (strcmp(argv[1], "reset") == 0) {
+		if (strcmp(argv[2], "altbank") == 0)
+			cpld_set_altbank();
+		else
+			cpld_set_defbank();
+	} else {
+		rc = cmd_usage(cmdtp);
+	}
+
+	return rc;
+}
+
+U_BOOT_CMD(
+	cpld, CONFIG_SYS_MAXARGS, 1, do_cpld,
+	"Reset the board or alternate bank",
+	"reset: reset to default bank\n"
+	"cpld reset altbank: reset to alternate bank\n"
+);
diff --git a/board/freescale/t208xrdb/cpld.h b/board/freescale/t208xrdb/cpld.h
new file mode 100644
index 0000000000..4cee4e55cf
--- /dev/null
+++ b/board/freescale/t208xrdb/cpld.h
@@ -0,0 +1,42 @@
+/*
+ * Copyright 2014 Freescale Semiconductor
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * CPLD register set of T2080RDB board-specific.
+ */
+struct cpld_data {
+	u8 chip_id1;		/* 0x00 - Chip ID1 register */
+	u8 chip_id2;		/* 0x01 - Chip ID2 register */
+	u8 hw_ver;		/* 0x02 - Hardware Revision Register */
+	u8 sw_ver;		/* 0x03 - Software Revision register */
+	u8 res0[12];		/* 0x04 - 0x0F - not used */
+	u8 reset_ctl;		/* 0x10 - Reset control Register */
+	u8 flash_csr;		/* 0x11 - Flash control and status register */
+	u8 thermal_csr;		/* 0x12 - Thermal control and status register */
+	u8 led_csr;		/* 0x13 - LED control and status register */
+	u8 sfp_csr;		/* 0x14 - SFP+ control and status register */
+	u8 misc_csr;		/* 0x15 - Misc control and status register */
+	u8 boot_or;		/* 0x16 - Boot config override register */
+	u8 boot_cfg1;		/* 0x17 - Boot configuration register 1 */
+	u8 boot_cfg2;		/* 0x18 - Boot configuration register 2 */
+} cpld_data_t;
+
+u8 cpld_read(unsigned int reg);
+void cpld_write(unsigned int reg, u8 value);
+
+#define CPLD_READ(reg) cpld_read(offsetof(struct cpld_data, reg))
+#define CPLD_WRITE(reg, value)  \
+	cpld_write(offsetof(struct cpld_data, reg), value)
+
+/* CPLD on IFC */
+#define CPLD_LBMAP_MASK		0x3F
+#define CPLD_BANK_SEL_MASK	0x07
+#define CPLD_BANK_OVERRIDE	0x40
+#define CPLD_LBMAP_ALTBANK	0x43 /* BANK OR | BANK 4 */
+#define CPLD_LBMAP_DFLTBANK	0x47 /* BANK OR | BANK 0 */
+#define CPLD_LBMAP_RESET	0xFF
+#define CPLD_LBMAP_SHIFT	0x03
+#define CPLD_BOOT_SEL		0x80
diff --git a/board/freescale/t208xrdb/ddr.c b/board/freescale/t208xrdb/ddr.c
new file mode 100644
index 0000000000..01e917398f
--- /dev/null
+++ b/board/freescale/t208xrdb/ddr.c
@@ -0,0 +1,112 @@
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * Version 2 or later as published by the Free Software Foundation.
+ */
+
+#include <common.h>
+#include <i2c.h>
+#include <hwconfig.h>
+#include <asm/mmu.h>
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr_dimm_params.h>
+#include <asm/fsl_law.h>
+#include "ddr.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void fsl_ddr_board_options(memctl_options_t *popts,
+				dimm_params_t *pdimm,
+				unsigned int ctrl_num)
+{
+	const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
+	ulong ddr_freq;
+
+	if (ctrl_num > 1) {
+		printf("Not supported controller number %d\n", ctrl_num);
+		return;
+	}
+	if (!pdimm->n_ranks)
+		return;
+
+	pbsp = udimms[0];
+
+	/* Get clk_adjust, wrlvl_start, wrlvl_ctl, according to the board ddr
+	 * freqency and n_banks specified in board_specific_parameters table.
+	 */
+	ddr_freq = get_ddr_freq(0) / 1000000;
+	while (pbsp->datarate_mhz_high) {
+		if (pbsp->n_ranks == pdimm->n_ranks &&
+		    (pdimm->rank_density >> 30) >= pbsp->rank_gb) {
+			if (ddr_freq <= pbsp->datarate_mhz_high) {
+				popts->clk_adjust = pbsp->clk_adjust;
+				popts->wrlvl_start = pbsp->wrlvl_start;
+				popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
+				popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
+				goto found;
+			}
+			pbsp_highest = pbsp;
+		}
+		pbsp++;
+	}
+
+	if (pbsp_highest) {
+		printf("Error: board specific timing not found");
+		printf("for data rate %lu MT/s\n", ddr_freq);
+		printf("Trying to use the highest speed (%u) parameters\n",
+		       pbsp_highest->datarate_mhz_high);
+		popts->clk_adjust = pbsp_highest->clk_adjust;
+		popts->wrlvl_start = pbsp_highest->wrlvl_start;
+		popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
+		popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
+	} else {
+		panic("DIMM is not supported by this board");
+	}
+found:
+	debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n"
+		"\tclk_adjust %d, wrlvl_start %d, wrlvl_ctrl_2 0x%x, "
+		"wrlvl_ctrl_3 0x%x\n",
+		pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb,
+		pbsp->clk_adjust, pbsp->wrlvl_start, pbsp->wrlvl_ctl_2,
+		pbsp->wrlvl_ctl_3);
+
+	/*
+	 * Factors to consider for half-strength driver enable:
+	 *	- number of DIMMs installed
+	 */
+	popts->half_strength_driver_enable = 0;
+	/*
+	 * Write leveling override
+	 */
+	popts->wrlvl_override = 1;
+	popts->wrlvl_sample = 0xf;
+
+	/*
+	 * Rtt and Rtt_WR override
+	 */
+	popts->rtt_override = 0;
+
+	/* Enable ZQ calibration */
+	popts->zq_en = 1;
+
+	/* DHC_EN =1, ODT = 75 Ohm */
+	popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_75ohm);
+	popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm);
+}
+
+phys_size_t initdram(int board_type)
+{
+	phys_size_t dram_size;
+
+	puts("Initializing....using SPD\n");
+
+	dram_size = fsl_ddr_sdram();
+
+	dram_size = setup_ddr_tlbs(dram_size / 0x100000);
+	dram_size *= 0x100000;
+
+	puts("    DDR: ");
+	return dram_size;
+}
diff --git a/board/freescale/t208xrdb/ddr.h b/board/freescale/t208xrdb/ddr.h
new file mode 100644
index 0000000000..b6d406219e
--- /dev/null
+++ b/board/freescale/t208xrdb/ddr.h
@@ -0,0 +1,47 @@
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#ifndef __DDR_H__
+#define __DDR_H__
+struct board_specific_parameters {
+	u32 n_ranks;
+	u32 datarate_mhz_high;
+	u32 rank_gb;
+	u32 clk_adjust;
+	u32 wrlvl_start;
+	u32 wrlvl_ctl_2;
+	u32 wrlvl_ctl_3;
+};
+
+/*
+ * These tables contain all valid speeds we want to override with board
+ * specific parameters. datarate_mhz_high values need to be in ascending order
+ * for each n_ranks group.
+ */
+
+static const struct board_specific_parameters udimm0[] = {
+	/*
+	 * memory controller 0
+	 *   num|  hi| rank|  clk| wrlvl |   wrlvl   |  wrlvl |
+	 * ranks| mhz| GB  |adjst| start |   ctl2    |  ctl3  |
+	 */
+	{2,  1200, 2, 5,     7, 0x0808090a, 0x0b0c0c0a},
+	{2,  1500, 2, 5,     6, 0x07070809, 0x0a0b0b09},
+	{2,  1600, 2, 5,     8, 0x0808070b, 0x0c0d0e0a},
+	{2,  1700, 2, 4,     7, 0x080a0a0c, 0x0c0d0e0a},
+	{2,  1900, 2, 5,     9, 0x0a0b0c0e, 0x0f10120c},
+	{1,  1200, 2, 5,     7, 0x0808090a, 0x0b0c0c0a},
+	{1,  1500, 2, 5,     6, 0x07070809, 0x0a0b0b09},
+	{1,  1600, 2, 5,     8, 0x0808070b, 0x0c0d0e0a},
+	{1,  1700, 2, 4,     7, 0x080a0a0c, 0x0c0d0e0a},
+	{1,  1900, 2, 5,     9, 0x0a0b0c0e, 0x0f10120c},
+	{}
+};
+
+static const struct board_specific_parameters *udimms[] = {
+	udimm0,
+};
+#endif
diff --git a/board/freescale/t208xrdb/eth_t208xrdb.c b/board/freescale/t208xrdb/eth_t208xrdb.c
new file mode 100644
index 0000000000..cbbc625831
--- /dev/null
+++ b/board/freescale/t208xrdb/eth_t208xrdb.c
@@ -0,0 +1,106 @@
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ *
+ * Shengzhou Liu <Shengzhou.Liu@freescale.com>
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#include <common.h>
+#include <command.h>
+#include <netdev.h>
+#include <asm/mmu.h>
+#include <asm/processor.h>
+#include <asm/immap_85xx.h>
+#include <asm/fsl_law.h>
+#include <asm/fsl_serdes.h>
+#include <asm/fsl_portals.h>
+#include <asm/fsl_liodn.h>
+#include <malloc.h>
+#include <fm_eth.h>
+#include <fsl_mdio.h>
+#include <miiphy.h>
+#include <phy.h>
+#include <asm/fsl_dtsec.h>
+#include <asm/fsl_serdes.h>
+
+int board_eth_init(bd_t *bis)
+{
+#if defined(CONFIG_FMAN_ENET)
+	int i, interface;
+	struct memac_mdio_info dtsec_mdio_info;
+	struct memac_mdio_info tgec_mdio_info;
+	struct mii_dev *dev;
+	ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+	u32 srds_s1;
+
+	srds_s1 = in_be32(&gur->rcwsr[4]) &
+					FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
+	srds_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
+
+	dtsec_mdio_info.regs =
+		(struct memac_mdio_controller *)CONFIG_SYS_FM1_DTSEC_MDIO_ADDR;
+
+	dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME;
+
+	/* Register the 1G MDIO bus */
+	fm_memac_mdio_init(bis, &dtsec_mdio_info);
+
+	tgec_mdio_info.regs =
+		(struct memac_mdio_controller *)CONFIG_SYS_FM1_TGEC_MDIO_ADDR;
+	tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME;
+
+	/* Register the 10G MDIO bus */
+	fm_memac_mdio_init(bis, &tgec_mdio_info);
+
+	/* Set the two on-board RGMII PHY address */
+	fm_info_set_phy_address(FM1_DTSEC3, RGMII_PHY1_ADDR);
+	fm_info_set_phy_address(FM1_DTSEC4, RGMII_PHY2_ADDR);
+
+	switch (srds_s1) {
+	case 0x66:
+	case 0x6b:
+		fm_info_set_phy_address(FM1_10GEC1, CORTINA_PHY_ADDR1);
+		fm_info_set_phy_address(FM1_10GEC2, CORTINA_PHY_ADDR2);
+		fm_info_set_phy_address(FM1_10GEC3, FM1_10GEC3_PHY_ADDR);
+		fm_info_set_phy_address(FM1_10GEC4, FM1_10GEC4_PHY_ADDR);
+		break;
+	default:
+		printf("SerDes1 protocol 0x%x is not supported on T208xRDB\n",
+		       srds_s1);
+		break;
+	}
+
+	for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
+		interface = fm_info_get_enet_if(i);
+		switch (interface) {
+		case PHY_INTERFACE_MODE_RGMII:
+			dev = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME);
+			fm_info_set_mdio(i, dev);
+			break;
+		default:
+			break;
+		}
+	}
+
+	for (i = FM1_10GEC1; i < FM1_10GEC1 + CONFIG_SYS_NUM_FM1_10GEC; i++) {
+		switch (fm_info_get_enet_if(i)) {
+		case PHY_INTERFACE_MODE_XGMII:
+			dev = miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME);
+			fm_info_set_mdio(i, dev);
+			break;
+		default:
+			break;
+		}
+	}
+
+	cpu_eth_init(bis);
+#endif /* CONFIG_FMAN_ENET */
+
+	return pci_eth_init(bis);
+}
+
+void fdt_fixup_board_enet(void *fdt)
+{
+	return;
+}
diff --git a/board/freescale/t208xrdb/law.c b/board/freescale/t208xrdb/law.c
new file mode 100644
index 0000000000..eb82431e22
--- /dev/null
+++ b/board/freescale/t208xrdb/law.c
@@ -0,0 +1,34 @@
+/*
+ * Copyright 2008-2014 Freescale Semiconductor, Inc.
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/fsl_law.h>
+#include <asm/mmu.h>
+
+struct law_entry law_table[] = {
+	SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_IFC),
+#ifdef CONFIG_SYS_BMAN_MEM_PHYS
+	SET_LAW(CONFIG_SYS_BMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_BMAN),
+#endif
+#ifdef CONFIG_SYS_QMAN_MEM_PHYS
+	SET_LAW(CONFIG_SYS_QMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_QMAN),
+#endif
+#ifdef CONFIG_SYS_CPLD_BASE_PHYS
+	SET_LAW(CONFIG_SYS_CPLD_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_IFC),
+#endif
+#ifdef CONFIG_SYS_DCSRBAR_PHYS
+	/* Limit DCSR to 32M to access NPC Trace Buffer */
+	SET_LAW(CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_DCSR),
+#endif
+#ifdef CONFIG_SYS_NAND_BASE_PHYS
+	SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_IFC),
+#endif
+};
+
+int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/board/freescale/t208xrdb/pci.c b/board/freescale/t208xrdb/pci.c
new file mode 100644
index 0000000000..ba7041af95
--- /dev/null
+++ b/board/freescale/t208xrdb/pci.c
@@ -0,0 +1,23 @@
+/*
+ * Copyright 2007-2014 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <command.h>
+#include <pci.h>
+#include <asm/fsl_pci.h>
+#include <libfdt.h>
+#include <fdt_support.h>
+#include <asm/fsl_serdes.h>
+
+void pci_init_board(void)
+{
+	fsl_pcie_init_board(0);
+}
+
+void pci_of_setup(void *blob, bd_t *bd)
+{
+	FT_FSL_PCI_SETUP;
+}
diff --git a/board/freescale/t208xrdb/t2080_pbi.cfg b/board/freescale/t208xrdb/t2080_pbi.cfg
new file mode 100644
index 0000000000..e200d926fb
--- /dev/null
+++ b/board/freescale/t208xrdb/t2080_pbi.cfg
@@ -0,0 +1,41 @@
+#
+# Copyright 2013 Freescale Semiconductor, Inc.
+#
+# SPDX-License-Identifier:      GPL-2.0+
+#
+# Refer doc/README.pblimage for more details about how-to configure
+# and create PBL boot image
+#
+
+#PBI commands
+#Initialize CPC1
+09010000 00200400
+09138000 00000000
+091380c0 00000100
+#512KB SRAM
+09010100 00000000
+09010104 fff80009
+09010f00 08000000
+#enable CPC1
+09010000 80000000
+#Configure LAW for CPC1
+09000d00 00000000
+09000d04 fff80000
+09000d08 81000012
+#Initialize eSPI controller, default configuration is slow for eSPI to
+#load data, this configuration comes from u-boot eSPI driver.
+09110000 80000403
+09110020 2d170008
+09110024 00100008
+09110028 00100008
+0911002c 00100008
+#Errata for slowing down the MDC clock to make it <= 2.5 MHZ
+094fc030 00008148
+094fd030 00008148
+#Configure alternate space
+09000010 00000000
+09000014 ff000000
+09000018 81000000
+#Flush PBL data
+09138000 00000000
+091380c0 00000000
diff --git a/board/freescale/t208xrdb/t2080_rcw.cfg b/board/freescale/t208xrdb/t2080_rcw.cfg
new file mode 100644
index 0000000000..cd62cc8641
--- /dev/null
+++ b/board/freescale/t208xrdb/t2080_rcw.cfg
@@ -0,0 +1,8 @@
+#PBL preamble and RCW header for T2080RDB
+aa55aa55 010e0100
+#SerDes Protocol: 0x66_0x16
+#Core/DDR: 1533Mhz/1600MT/s
+120c0017 15000000 00000000 00000000
+66160002 00008400 ec104000 c1000000
+00000000 00000000 00000000 000307fc
+00000000 00000000 00000000 00000004
diff --git a/board/freescale/t208xrdb/t208xrdb.c b/board/freescale/t208xrdb/t208xrdb.c
new file mode 100644
index 0000000000..f3fec2aa6e
--- /dev/null
+++ b/board/freescale/t208xrdb/t208xrdb.c
@@ -0,0 +1,124 @@
+/*
+ * Copyright 2009-2013 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#include <common.h>
+#include <command.h>
+#include <i2c.h>
+#include <netdev.h>
+#include <linux/compiler.h>
+#include <asm/mmu.h>
+#include <asm/processor.h>
+#include <asm/immap_85xx.h>
+#include <asm/fsl_law.h>
+#include <asm/fsl_serdes.h>
+#include <asm/fsl_portals.h>
+#include <asm/fsl_liodn.h>
+#include <fm_eth.h>
+#include "t208xrdb.h"
+#include "cpld.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int checkboard(void)
+{
+	struct cpu_type *cpu = gd->arch.cpu;
+	static const char *freq[3] = {"100.00MHZ", "125.00MHz", "156.25MHZ"};
+
+	printf("Board: %sRDB, ", cpu->name);
+	printf("Board rev: 0x%02x CPLD ver: 0x%02x, boot from ",
+	       CPLD_READ(hw_ver), CPLD_READ(sw_ver));
+
+#ifdef CONFIG_SDCARD
+	puts("SD/MMC\n");
+#elif CONFIG_SPIFLASH
+	puts("SPI\n");
+#else
+	u8 reg;
+
+	reg = CPLD_READ(flash_csr);
+
+	if (reg & CPLD_BOOT_SEL) {
+		puts("NAND\n");
+	} else {
+		reg = ((reg & CPLD_LBMAP_MASK) >> CPLD_LBMAP_SHIFT);
+		printf("NOR vBank%d\n", ~reg & 0x7);
+	}
+#endif
+
+	puts("SERDES Reference Clocks:\n");
+	printf("SD1_CLK1=%s, SD1_CLK2=%s\n", freq[2], freq[0]);
+	printf("SD2_CLK1=%s, SD2_CLK2=%s\n", freq[0], freq[0]);
+
+	return 0;
+}
+
+int board_early_init_r(void)
+{
+	const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
+	const u8 flash_esel = find_tlb_idx((void *)flashbase, 1);
+	/*
+	 * Remap Boot flash + PROMJET region to caching-inhibited
+	 * so that flash can be erased properly.
+	 */
+
+	/* Flush d-cache and invalidate i-cache of any FLASH data */
+	flush_dcache();
+	invalidate_icache();
+
+	/* invalidate existing TLB entry for flash + promjet */
+	disable_tlb(flash_esel);
+
+	set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
+		MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		0, flash_esel, BOOKE_PAGESZ_256M, 1);
+
+	set_liodns();
+#ifdef CONFIG_SYS_DPAA_QBMAN
+	setup_portals();
+#endif
+
+	return 0;
+}
+
+unsigned long get_board_sys_clk(void)
+{
+	return CONFIG_SYS_CLK_FREQ;
+}
+
+unsigned long get_board_ddr_clk(void)
+{
+	return CONFIG_DDR_CLK_FREQ;
+}
+
+int misc_init_r(void)
+{
+	return 0;
+}
+
+void ft_board_setup(void *blob, bd_t *bd)
+{
+	phys_addr_t base;
+	phys_size_t size;
+
+	ft_cpu_setup(blob, bd);
+
+	base = getenv_bootm_low();
+	size = getenv_bootm_size();
+
+	fdt_fixup_memory(blob, (u64)base, (u64)size);
+
+#ifdef CONFIG_PCI
+	pci_of_setup(blob, bd);
+#endif
+
+	fdt_fixup_liodn(blob);
+	fdt_fixup_dr_usb(blob, bd);
+
+#ifdef CONFIG_SYS_DPAA_FMAN
+	fdt_fixup_fman_ethernet(blob);
+	fdt_fixup_board_enet(blob);
+#endif
+}
diff --git a/board/freescale/t208xrdb/t208xrdb.h b/board/freescale/t208xrdb/t208xrdb.h
new file mode 100644
index 0000000000..13380d02a3
--- /dev/null
+++ b/board/freescale/t208xrdb/t208xrdb.h
@@ -0,0 +1,13 @@
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CORENET_DS_H__
+#define __CORENET_DS_H__
+
+void fdt_fixup_board_enet(void *blob);
+void pci_of_setup(void *blob, bd_t *bd);
+
+#endif
diff --git a/board/freescale/t208xrdb/tlb.c b/board/freescale/t208xrdb/tlb.c
new file mode 100644
index 0000000000..085d9f5c6a
--- /dev/null
+++ b/board/freescale/t208xrdb/tlb.c
@@ -0,0 +1,151 @@
+/*
+ * Copyright 2008-2014 Freescale Semiconductor, Inc.
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/mmu.h>
+
+struct fsl_e_tlb_entry tlb_table[] = {
+	/* TLB 0 - for temp stack in cache */
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR,
+		      CONFIG_SYS_INIT_RAM_ADDR_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 0, BOOKE_PAGESZ_4K, 0),
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
+		      CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 0, BOOKE_PAGESZ_4K, 0),
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
+		      CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 0, BOOKE_PAGESZ_4K, 0),
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
+		      CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 0, BOOKE_PAGESZ_4K, 0),
+
+	/* TLB 1 */
+	/* *I*** - Covers boot page */
+#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L3_ADDR)
+	/*
+	 * *I*G - L3SRAM. When L3 is used as 1M SRAM, the address of the
+	 * SRAM is at 0xfff00000, it covered the 0xfffff000.
+	 */
+	SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 0, BOOKE_PAGESZ_1M, 1),
+#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
+	/*
+	 * SRIO_PCIE_BOOT-SLAVE. When slave boot, the address of the
+	 * space is at 0xfff00000, it covered the 0xfffff000.
+	 */
+	SET_TLB_ENTRY(1, CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR,
+		      CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_W|MAS2_G,
+		      0, 0, BOOKE_PAGESZ_1M, 1),
+#else
+	SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 0, BOOKE_PAGESZ_4K, 1),
+#endif
+
+	/* *I*G* - CCSRBAR */
+	SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 1, BOOKE_PAGESZ_16M, 1),
+
+	/* *I*G* - Flash, localbus */
+	/* This will be changed to *I*G* after relocation to RAM. */
+	SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
+		      MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
+		      0, 2, BOOKE_PAGESZ_256M, 1),
+
+	/* *I*G* - PCIe 1, 0x80000000 */
+	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 3, BOOKE_PAGESZ_512M, 1),
+
+	/* *I*G* - PCIe 2, 0xa0000000 */
+	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE2_MEM_VIRT, CONFIG_SYS_PCIE2_MEM_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 4, BOOKE_PAGESZ_256M, 1),
+
+	/* *I*G* - PCIe 3, 0xb0000000 */
+	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT, CONFIG_SYS_PCIE3_MEM_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 5, BOOKE_PAGESZ_256M, 1),
+
+
+	/* *I*G* - PCIe 4, 0xc0000000 */
+	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE4_MEM_VIRT, CONFIG_SYS_PCIE4_MEM_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 6, BOOKE_PAGESZ_256M, 1),
+
+	/* *I*G* - PCI I/O */
+	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 7, BOOKE_PAGESZ_256K, 1),
+
+	/* Bman/Qman */
+#ifdef CONFIG_SYS_BMAN_MEM_PHYS
+	SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE, CONFIG_SYS_BMAN_MEM_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 9, BOOKE_PAGESZ_16M, 1),
+	SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE + 0x01000000,
+		      CONFIG_SYS_BMAN_MEM_PHYS + 0x01000000,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 10, BOOKE_PAGESZ_16M, 1),
+#endif
+#ifdef CONFIG_SYS_QMAN_MEM_PHYS
+	SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE, CONFIG_SYS_QMAN_MEM_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 11, BOOKE_PAGESZ_16M, 1),
+	SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE + 0x01000000,
+		      CONFIG_SYS_QMAN_MEM_PHYS + 0x01000000,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 12, BOOKE_PAGESZ_16M, 1),
+#endif
+#ifdef CONFIG_SYS_DCSRBAR_PHYS
+	SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 13, BOOKE_PAGESZ_32M, 1),
+#endif
+#ifdef CONFIG_SYS_NAND_BASE
+	/*
+	 * *I*G - NAND
+	 * entry 14 and 15 has been used hard coded, they will be disabled
+	 * in cpu_init_f, so we use entry 16 for nand.
+	 */
+	SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 16, BOOKE_PAGESZ_64K, 1),
+#endif
+#ifdef CONFIG_SYS_CPLD_BASE
+	SET_TLB_ENTRY(1, CONFIG_SYS_CPLD_BASE, CONFIG_SYS_CPLD_BASE_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 17, BOOKE_PAGESZ_4K, 1),
+#endif
+#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
+	/*
+	 * SRIO_PCIE_BOOT-SLAVE. 1M space from 0xffe00000 for
+	 * fetching ucode and ENV from master
+	 */
+	SET_TLB_ENTRY(1, CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR,
+		      CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_G,
+		      0, 18, BOOKE_PAGESZ_1M, 1),
+#endif
+#if defined(CONFIG_SYS_RAMBOOT)
+	SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 19, BOOKE_PAGESZ_2G, 1)
+#endif
+
+};
+
+int num_tlb_entries = ARRAY_SIZE(tlb_table);
diff --git a/board/freescale/t4qds/Makefile b/board/freescale/t4qds/Makefile
index a2167b377b..2b1f7aa301 100644
--- a/board/freescale/t4qds/Makefile
+++ b/board/freescale/t4qds/Makefile
@@ -4,36 +4,10 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS-$(CONFIG_T4240QDS) += t4240qds.o
-COBJS-$(CONFIG_T4240EMU) += t4240emu.o
-COBJS-y	+= ddr.o
-COBJS-$(CONFIG_T4240QDS)+= eth.o
-COBJS-$(CONFIG_PCI)	+= pci.o
-COBJS-y	+= law.o
-COBJS-y	+= tlb.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS-y))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-clean:
-	rm -f $(OBJS) $(SOBJS)
-
-distclean:	clean
-	rm -f $(LIB) core *.bak .depend
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-$(CONFIG_T4240QDS) += t4240qds.o
+obj-$(CONFIG_T4240EMU) += t4240emu.o
+obj-y	+= ddr.o
+obj-$(CONFIG_T4240QDS)+= eth.o
+obj-$(CONFIG_PCI)	+= pci.o
+obj-y	+= law.o
+obj-y	+= tlb.o
diff --git a/board/freescale/t4qds/ddr.c b/board/freescale/t4qds/ddr.c
index 26ac2a54d2..7586cc3c4b 100644
--- a/board/freescale/t4qds/ddr.c
+++ b/board/freescale/t4qds/ddr.c
@@ -10,8 +10,8 @@
 #include <i2c.h>
 #include <hwconfig.h>
 #include <asm/mmu.h>
-#include <asm/fsl_ddr_sdram.h>
-#include <asm/fsl_ddr_dimm_params.h>
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr_dimm_params.h>
 #include <asm/fsl_law.h>
 #include "ddr.h"
 
@@ -56,7 +56,7 @@ void fsl_ddr_board_options(memctl_options_t *popts,
 				popts->wrlvl_start = pbsp->wrlvl_start;
 				popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
 				popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
-				popts->twoT_en = pbsp->force_2T;
+				popts->twot_en = pbsp->force_2t;
 				goto found;
 			}
 			pbsp_highest = pbsp;
@@ -75,7 +75,7 @@ void fsl_ddr_board_options(memctl_options_t *popts,
 		popts->wrlvl_start = pbsp_highest->wrlvl_start;
 		popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
 		popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
-		popts->twoT_en = pbsp_highest->force_2T;
+		popts->twot_en = pbsp_highest->force_2t;
 	} else {
 		panic("DIMM is not supported by this board");
 	}
diff --git a/board/freescale/t4qds/ddr.h b/board/freescale/t4qds/ddr.h
index d0a0951af9..8183af78fe 100644
--- a/board/freescale/t4qds/ddr.h
+++ b/board/freescale/t4qds/ddr.h
@@ -16,7 +16,7 @@ struct board_specific_parameters {
 	u32 wrlvl_ctl_3;
 	u32 cpo;
 	u32 write_data_delay;
-	u32 force_2T;
+	u32 force_2t;
 };
 
 /*
diff --git a/board/freescale/t4qds/eth.c b/board/freescale/t4qds/eth.c
index b5f488bcba..24cf907430 100644
--- a/board/freescale/t4qds/eth.c
+++ b/board/freescale/t4qds/eth.c
@@ -12,7 +12,7 @@
 #include <asm/cache.h>
 #include <asm/immap_85xx.h>
 #include <asm/fsl_law.h>
-#include <asm/fsl_ddr_sdram.h>
+#include <fsl_ddr_sdram.h>
 #include <asm/fsl_serdes.h>
 #include <asm/fsl_portals.h>
 #include <asm/fsl_liodn.h>
diff --git a/board/freescale/t4qds/t4240qds.c b/board/freescale/t4qds/t4240qds.c
index 0c1a4fbd9f..79b770b488 100644
--- a/board/freescale/t4qds/t4240qds.c
+++ b/board/freescale/t4qds/t4240qds.c
@@ -608,22 +608,6 @@ unsigned long get_board_ddr_clk(void)
 	return 66666666;
 }
 
-static const char *serdes_clock_to_string(u32 clock)
-{
-	switch (clock) {
-	case SRDS_PLLCR0_RFCK_SEL_100:
-		return "100";
-	case SRDS_PLLCR0_RFCK_SEL_125:
-		return "125";
-	case SRDS_PLLCR0_RFCK_SEL_156_25:
-		return "156.25";
-	case SRDS_PLLCR0_RFCK_SEL_161_13:
-		return "161.1328125";
-	default:
-		return "???";
-	}
-}
-
 int misc_init_r(void)
 {
 	u8 sw;
diff --git a/board/freescale/t4qds/t4_rcw.cfg b/board/freescale/t4qds/t4_rcw.cfg
index 6ac95ffd52..74df01a70c 100644
--- a/board/freescale/t4qds/t4_rcw.cfg
+++ b/board/freescale/t4qds/t4_rcw.cfg
@@ -1,7 +1,7 @@
 #PBL preamble and RCW header
 aa55aa55 010e0100
 #serdes protocol  1_28_6_12
-14180019 0c101916 00000000 00000000
-04383060 30548c00 6c020000 19000000
-00000000 ee0000ee 00000000 000187fc
-00000000 00000000 00000000 00000018
+120c0019 0c101915 00000000 00000000
+04383063 30548c00 6c020000 1d000000
+00000000 ee0000ee 00000000 000307fc
+00000000 00000000 00000000 00000020
diff --git a/board/freescale/titanium/Makefile b/board/freescale/titanium/Makefile
deleted file mode 100644
index 29a98f60b3..0000000000
--- a/board/freescale/titanium/Makefile
+++ /dev/null
@@ -1,28 +0,0 @@
-#
-# Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
-#
-# (C) Copyright 2011 Freescale Semiconductor, Inc.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-include $(TOPDIR)/config.mk
-
-LIB    = $(obj)lib$(BOARD).o
-
-COBJS  := titanium.o
-
-SRCS   := $(COBJS:.o=.c)
-OBJS   := $(addprefix $(obj),$(COBJS))
-
-$(LIB):        $(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
diff --git a/board/freescale/titanium/titanium.c b/board/freescale/titanium/titanium.c
deleted file mode 100644
index 6025eb7315..0000000000
--- a/board/freescale/titanium/titanium.c
+++ /dev/null
@@ -1,323 +0,0 @@
-/*
- * Copyright (C) 2013 Stefan Roese <sr@denx.de>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/imx-regs.h>
-#include <asm/arch/iomux.h>
-#include <asm/arch/mx6q_pins.h>
-#include <asm/arch/crm_regs.h>
-#include <asm/arch/sys_proto.h>
-#include <asm/gpio.h>
-#include <asm/imx-common/iomux-v3.h>
-#include <asm/imx-common/mxc_i2c.h>
-#include <asm/imx-common/boot_mode.h>
-#include <mmc.h>
-#include <fsl_esdhc.h>
-#include <micrel.h>
-#include <miiphy.h>
-#include <netdev.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#define UART_PAD_CTRL  (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |	\
-			PAD_CTL_DSE_40ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
-
-#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP  | PAD_CTL_SPEED_LOW |	\
-			PAD_CTL_DSE_80ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
-
-#define ENET_PAD_CTRL  (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED	  |	\
-			PAD_CTL_DSE_40ohm   | PAD_CTL_HYS)
-
-#define I2C_PAD_CTRL	(PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |	\
-			 PAD_CTL_DSE_40ohm | PAD_CTL_HYS |		\
-			 PAD_CTL_ODE | PAD_CTL_SRE_FAST)
-
-int dram_init(void)
-{
-	gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
-
-	return 0;
-}
-
-iomux_v3_cfg_t const uart1_pads[] = {
-	MX6_PAD_SD3_DAT6__UART1_RXD | MUX_PAD_CTRL(UART_PAD_CTRL),
-	MX6_PAD_SD3_DAT7__UART1_TXD | MUX_PAD_CTRL(UART_PAD_CTRL),
-};
-
-iomux_v3_cfg_t const uart2_pads[] = {
-	MX6_PAD_EIM_D26__UART2_TXD | MUX_PAD_CTRL(UART_PAD_CTRL),
-	MX6_PAD_EIM_D27__UART2_RXD | MUX_PAD_CTRL(UART_PAD_CTRL),
-};
-
-iomux_v3_cfg_t const uart4_pads[] = {
-	MX6_PAD_CSI0_DAT12__UART4_TXD | MUX_PAD_CTRL(UART_PAD_CTRL),
-	MX6_PAD_CSI0_DAT13__UART4_RXD | MUX_PAD_CTRL(UART_PAD_CTRL),
-};
-
-#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
-
-struct i2c_pads_info i2c_pad_info0 = {
-	.scl = {
-		.i2c_mode  = MX6_PAD_CSI0_DAT9__I2C1_SCL | PC,
-		.gpio_mode = MX6_PAD_CSI0_DAT9__GPIO_5_27 | PC,
-		.gp = IMX_GPIO_NR(5, 27)
-	},
-	.sda = {
-		 .i2c_mode = MX6_PAD_CSI0_DAT8__I2C1_SDA | PC,
-		 .gpio_mode = MX6_PAD_CSI0_DAT8__GPIO_5_26 | PC,
-		 .gp = IMX_GPIO_NR(5, 26)
-	 }
-};
-
-struct i2c_pads_info i2c_pad_info2 = {
-	.scl = {
-		.i2c_mode = MX6_PAD_GPIO_3__I2C3_SCL | PC,
-		.gpio_mode = MX6_PAD_GPIO_3__GPIO_1_3 | PC,
-		.gp = IMX_GPIO_NR(1, 3)
-	},
-	.sda = {
-		 .i2c_mode = MX6_PAD_GPIO_16__I2C3_SDA | PC,
-		 .gpio_mode = MX6_PAD_GPIO_16__GPIO_7_11 | PC,
-		 .gp = IMX_GPIO_NR(7, 11)
-	 }
-};
-
-iomux_v3_cfg_t const usdhc3_pads[] = {
-	MX6_PAD_SD3_CLK__USDHC3_CLK   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD3_CMD__USDHC3_CMD   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD3_DAT0__USDHC3_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD3_DAT1__USDHC3_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD3_DAT2__USDHC3_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD3_DAT3__USDHC3_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD3_DAT5__GPIO_7_0    | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
-};
-
-iomux_v3_cfg_t const enet_pads1[] = {
-	MX6_PAD_ENET_MDIO__ENET_MDIO		| MUX_PAD_CTRL(ENET_PAD_CTRL),
-	MX6_PAD_ENET_MDC__ENET_MDC		| MUX_PAD_CTRL(ENET_PAD_CTRL),
-	MX6_PAD_RGMII_TXC__ENET_RGMII_TXC	| MUX_PAD_CTRL(ENET_PAD_CTRL),
-	MX6_PAD_RGMII_TD0__ENET_RGMII_TD0	| MUX_PAD_CTRL(ENET_PAD_CTRL),
-	MX6_PAD_RGMII_TD1__ENET_RGMII_TD1	| MUX_PAD_CTRL(ENET_PAD_CTRL),
-	MX6_PAD_RGMII_TD2__ENET_RGMII_TD2	| MUX_PAD_CTRL(ENET_PAD_CTRL),
-	MX6_PAD_RGMII_TD3__ENET_RGMII_TD3	| MUX_PAD_CTRL(ENET_PAD_CTRL),
-	MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL	| MUX_PAD_CTRL(ENET_PAD_CTRL),
-	MX6_PAD_ENET_REF_CLK__ENET_TX_CLK	| MUX_PAD_CTRL(ENET_PAD_CTRL),
-	/* pin 35 - 1 (PHY_AD2) on reset */
-	MX6_PAD_RGMII_RXC__GPIO_6_30		| MUX_PAD_CTRL(NO_PAD_CTRL),
-	/* pin 32 - 1 - (MODE0) all */
-	MX6_PAD_RGMII_RD0__GPIO_6_25		| MUX_PAD_CTRL(NO_PAD_CTRL),
-	/* pin 31 - 1 - (MODE1) all */
-	MX6_PAD_RGMII_RD1__GPIO_6_27		| MUX_PAD_CTRL(NO_PAD_CTRL),
-	/* pin 28 - 1 - (MODE2) all */
-	MX6_PAD_RGMII_RD2__GPIO_6_28		| MUX_PAD_CTRL(NO_PAD_CTRL),
-	/* pin 27 - 1 - (MODE3) all */
-	MX6_PAD_RGMII_RD3__GPIO_6_29		| MUX_PAD_CTRL(NO_PAD_CTRL),
-	/* pin 33 - 1 - (CLK125_EN) 125Mhz clockout enabled */
-	MX6_PAD_RGMII_RX_CTL__GPIO_6_24		| MUX_PAD_CTRL(NO_PAD_CTRL),
-	/* pin 42 PHY nRST */
-	MX6_PAD_EIM_D23__GPIO_3_23		| MUX_PAD_CTRL(NO_PAD_CTRL),
-};
-
-iomux_v3_cfg_t const enet_pads2[] = {
-	MX6_PAD_RGMII_RXC__ENET_RGMII_RXC	| MUX_PAD_CTRL(ENET_PAD_CTRL),
-	MX6_PAD_RGMII_RD0__ENET_RGMII_RD0	| MUX_PAD_CTRL(ENET_PAD_CTRL),
-	MX6_PAD_RGMII_RD1__ENET_RGMII_RD1	| MUX_PAD_CTRL(ENET_PAD_CTRL),
-	MX6_PAD_RGMII_RD2__ENET_RGMII_RD2	| MUX_PAD_CTRL(ENET_PAD_CTRL),
-	MX6_PAD_RGMII_RD3__ENET_RGMII_RD3	| MUX_PAD_CTRL(ENET_PAD_CTRL),
-	MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL	| MUX_PAD_CTRL(ENET_PAD_CTRL),
-};
-
-iomux_v3_cfg_t nfc_pads[] = {
-	MX6_PAD_NANDF_CLE__RAWNAND_CLE		| MUX_PAD_CTRL(NO_PAD_CTRL),
-	MX6_PAD_NANDF_ALE__RAWNAND_ALE		| MUX_PAD_CTRL(NO_PAD_CTRL),
-	MX6_PAD_NANDF_WP_B__RAWNAND_RESETN	| MUX_PAD_CTRL(NO_PAD_CTRL),
-	MX6_PAD_NANDF_RB0__RAWNAND_READY0	| MUX_PAD_CTRL(NO_PAD_CTRL),
-	MX6_PAD_NANDF_CS0__RAWNAND_CE0N		| MUX_PAD_CTRL(NO_PAD_CTRL),
-	MX6_PAD_NANDF_CS1__RAWNAND_CE1N		| MUX_PAD_CTRL(NO_PAD_CTRL),
-	MX6_PAD_NANDF_CS2__RAWNAND_CE2N		| MUX_PAD_CTRL(NO_PAD_CTRL),
-	MX6_PAD_NANDF_CS3__RAWNAND_CE3N		| MUX_PAD_CTRL(NO_PAD_CTRL),
-	MX6_PAD_SD4_CMD__RAWNAND_RDN		| MUX_PAD_CTRL(NO_PAD_CTRL),
-	MX6_PAD_SD4_CLK__RAWNAND_WRN		| MUX_PAD_CTRL(NO_PAD_CTRL),
-	MX6_PAD_NANDF_D0__RAWNAND_D0		| MUX_PAD_CTRL(NO_PAD_CTRL),
-	MX6_PAD_NANDF_D1__RAWNAND_D1		| MUX_PAD_CTRL(NO_PAD_CTRL),
-	MX6_PAD_NANDF_D2__RAWNAND_D2		| MUX_PAD_CTRL(NO_PAD_CTRL),
-	MX6_PAD_NANDF_D3__RAWNAND_D3		| MUX_PAD_CTRL(NO_PAD_CTRL),
-	MX6_PAD_NANDF_D4__RAWNAND_D4		| MUX_PAD_CTRL(NO_PAD_CTRL),
-	MX6_PAD_NANDF_D5__RAWNAND_D5		| MUX_PAD_CTRL(NO_PAD_CTRL),
-	MX6_PAD_NANDF_D6__RAWNAND_D6		| MUX_PAD_CTRL(NO_PAD_CTRL),
-	MX6_PAD_NANDF_D7__RAWNAND_D7		| MUX_PAD_CTRL(NO_PAD_CTRL),
-	MX6_PAD_SD4_DAT0__RAWNAND_DQS		| MUX_PAD_CTRL(NO_PAD_CTRL),
-};
-
-static void setup_gpmi_nand(void)
-{
-	struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
-
-	/* config gpmi nand iomux */
-	imx_iomux_v3_setup_multiple_pads(nfc_pads,
-					 ARRAY_SIZE(nfc_pads));
-
-	/* config gpmi and bch clock to 100 MHz */
-	clrsetbits_le32(&mxc_ccm->cs2cdr,
-			MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK |
-			MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK |
-			MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK,
-			MXC_CCM_CS2CDR_ENFC_CLK_PODF(0) |
-			MXC_CCM_CS2CDR_ENFC_CLK_PRED(3) |
-			MXC_CCM_CS2CDR_ENFC_CLK_SEL(3));
-
-	/* enable gpmi and bch clock gating */
-	setbits_le32(&mxc_ccm->CCGR4,
-		     MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
-		     MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
-		     MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
-		     MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
-		     MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET);
-
-	/* enable apbh clock gating */
-	setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK);
-}
-
-static void setup_iomux_enet(void)
-{
-	gpio_direction_output(IMX_GPIO_NR(3, 23), 0);
-	gpio_direction_output(IMX_GPIO_NR(6, 30), 1);
-	gpio_direction_output(IMX_GPIO_NR(6, 25), 1);
-	gpio_direction_output(IMX_GPIO_NR(6, 27), 1);
-	gpio_direction_output(IMX_GPIO_NR(6, 28), 1);
-	gpio_direction_output(IMX_GPIO_NR(6, 29), 1);
-	imx_iomux_v3_setup_multiple_pads(enet_pads1, ARRAY_SIZE(enet_pads1));
-	gpio_direction_output(IMX_GPIO_NR(6, 24), 1);
-
-	/* Need delay 10ms according to KSZ9021 spec */
-	udelay(1000 * 10);
-	gpio_set_value(IMX_GPIO_NR(3, 23), 1);
-
-	imx_iomux_v3_setup_multiple_pads(enet_pads2, ARRAY_SIZE(enet_pads2));
-}
-
-static void setup_iomux_uart(void)
-{
-	imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
-	imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads));
-	imx_iomux_v3_setup_multiple_pads(uart4_pads, ARRAY_SIZE(uart4_pads));
-}
-
-#ifdef CONFIG_USB_EHCI_MX6
-int board_ehci_hcd_init(int port)
-{
-	return 0;
-}
-
-#endif
-
-#ifdef CONFIG_FSL_ESDHC
-struct fsl_esdhc_cfg usdhc_cfg[1] = {
-	{ USDHC3_BASE_ADDR },
-};
-
-int board_mmc_getcd(struct mmc *mmc)
-{
-	struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
-
-	if (cfg->esdhc_base == USDHC3_BASE_ADDR) {
-		gpio_direction_input(IMX_GPIO_NR(7, 0));
-		return !gpio_get_value(IMX_GPIO_NR(7, 0));
-	}
-
-	return 0;
-}
-
-int board_mmc_init(bd_t *bis)
-{
-	/*
-	 * Only one USDHC controller on titianium
-	 */
-	imx_iomux_v3_setup_multiple_pads(usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
-	usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
-
-	return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
-}
-#endif
-
-int board_phy_config(struct phy_device *phydev)
-{
-	/* min rx data delay */
-	ksz9021_phy_extended_write(phydev,
-				   MII_KSZ9021_EXT_RGMII_RX_DATA_SKEW, 0x0);
-	/* min tx data delay */
-	ksz9021_phy_extended_write(phydev,
-				   MII_KSZ9021_EXT_RGMII_TX_DATA_SKEW, 0x0);
-	/* max rx/tx clock delay, min rx/tx control */
-	ksz9021_phy_extended_write(phydev,
-				   MII_KSZ9021_EXT_RGMII_CLOCK_SKEW, 0xf0f0);
-	if (phydev->drv->config)
-		phydev->drv->config(phydev);
-
-	return 0;
-}
-
-int board_eth_init(bd_t *bis)
-{
-	int ret;
-
-	setup_iomux_enet();
-
-	ret = cpu_eth_init(bis);
-	if (ret)
-		printf("FEC MXC: %s:failed\n", __func__);
-
-	return 0;
-}
-
-int board_early_init_f(void)
-{
-	setup_iomux_uart();
-
-	return 0;
-}
-
-int board_init(void)
-{
-	/* address of boot parameters */
-	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
-
-	setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info0);
-	setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
-
-	setup_gpmi_nand();
-
-	return 0;
-}
-
-int checkboard(void)
-{
-	puts("Board: Titanium\n");
-
-	return 0;
-}
-
-#ifdef CONFIG_CMD_BMODE
-static const struct boot_mode board_boot_modes[] = {
-	/* NAND */
-	{ "nand", MAKE_CFGVAL(0x80, 0x02, 0x00, 0x00) },
-	/* 4 bit bus width */
-	{ "mmc0", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00) },
-	{ "mmc1", MAKE_CFGVAL(0x40, 0x38, 0x00, 0x00) },
-	{ NULL, 0 },
-};
-#endif
-
-int misc_init_r(void)
-{
-#ifdef CONFIG_CMD_BMODE
-	add_board_boot_modes(board_boot_modes);
-#endif
-
-	return 0;
-}
diff --git a/board/freescale/vf610twr/Makefile b/board/freescale/vf610twr/Makefile
index 1541fd67d1..20b4a6be6b 100644
--- a/board/freescale/vf610twr/Makefile
+++ b/board/freescale/vf610twr/Makefile
@@ -4,23 +4,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	:= $(BOARD).o
-
-SRCS	:= $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	:= vf610twr.o
diff --git a/board/freescale/vf610twr/vf610twr.c b/board/freescale/vf610twr/vf610twr.c
index 699ea7f010..d64d3aa872 100644
--- a/board/freescale/vf610twr/vf610twr.c
+++ b/board/freescale/vf610twr/vf610twr.c
@@ -31,7 +31,6 @@ void setup_iomux_ddr(void)
 {
 	static const iomux_v3_cfg_t ddr_pads[] = {
 		VF610_PAD_DDR_A15__DDR_A_15,
-		VF610_PAD_DDR_A15__DDR_A_15,
 		VF610_PAD_DDR_A14__DDR_A_14,
 		VF610_PAD_DDR_A13__DDR_A_13,
 		VF610_PAD_DDR_A12__DDR_A_12,
@@ -218,7 +217,8 @@ void ddr_ctrl_init(void)
 		&ddrmr->cr[139]);
 
 	writel(DDRMC_CR154_PAD_ZQ_EARLY_CMP_EN_TIMER(13) |
-		DDRMC_CR154_PAD_ZQ_MODE(1), &ddrmr->cr[154]);
+		DDRMC_CR154_PAD_ZQ_MODE(1) |
+		DDRMC_CR154_DDR_SEL_PAD_CONTR(3), &ddrmr->cr[154]);
 	writel(DDRMC_CR155_AXI0_AWCACHE | DDRMC_CR155_PAD_ODT_BYTE1(2),
 		&ddrmr->cr[155]);
 	writel(DDRMC_CR158_TWR(6), &ddrmr->cr[158]);
diff --git a/board/friendlyarm/mini2440/Makefile b/board/friendlyarm/mini2440/Makefile
deleted file mode 100644
index d0d2add835..0000000000
--- a/board/friendlyarm/mini2440/Makefile
+++ /dev/null
@@ -1,28 +0,0 @@
-#
-# (C) Copyright 2012
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	:= mini2440.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
-	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
diff --git a/board/friendlyarm/mini2440/mini2440.c b/board/friendlyarm/mini2440/mini2440.c
deleted file mode 100644
index 59ed0548e7..0000000000
--- a/board/friendlyarm/mini2440/mini2440.c
+++ /dev/null
@@ -1,118 +0,0 @@
-/*
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- *
- * (C) Copyright 2002
- * David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
- *
- * (C) Copyright 2009
- * Michel Pollet <buserror@gmail.com>
- *
- * (C) Copyright 2012
- * Gabriel Huau <contact@huau-gabriel.fr>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/arch/s3c2440.h>
-#include <asm/arch/iomux.h>
-#include <asm/arch/gpio.h>
-#include <asm/io.h>
-#include <asm/gpio.h>
-#include <netdev.h>
-#include "mini2440.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-static inline void pll_delay(unsigned long loops)
-{
-	__asm__ volatile ("1:\n"
-	  "subs %0, %1, #1\n"
-	  "bne 1b" : "=r" (loops) : "0" (loops));
-}
-
-int board_early_init_f(void)
-{
-	struct s3c24x0_clock_power * const clk_power =
-					s3c24x0_get_base_clock_power();
-
-	/* to reduce PLL lock time, adjust the LOCKTIME register */
-	clk_power->locktime = 0xFFFFFF; /* Max PLL Lock time count */
-	clk_power->clkdivn = CLKDIVN_VAL;
-
-	/* configure UPLL */
-	clk_power->upllcon = ((U_M_MDIV << 12) + (U_M_PDIV << 4) + U_M_SDIV);
-	/* some delay between MPLL and UPLL */
-	pll_delay(100);
-
-	/* configure MPLL */
-	clk_power->mpllcon = ((M_MDIV << 12) + (M_PDIV << 4) + M_SDIV);
-
-	/* some delay between MPLL and UPLL */
-	pll_delay(10000);
-
-	return 0;
-}
-
-/*
- * Miscellaneous platform dependent initialisations
- */
-int board_init(void)
-{
-	struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio();
-
-	/* IOMUX Port H : UART Configuration */
-	gpio->gphcon = IOMUXH_nCTS0 | IOMUXH_nRTS0 | IOMUXH_TXD0 | IOMUXH_RXD0 |
-		IOMUXH_TXD1 | IOMUXH_RXD1 | IOMUXH_TXD2 | IOMUXH_RXD2;
-
-	gpio_direction_output(GPH8, 0);
-	gpio_direction_output(GPH9, 0);
-	gpio_direction_output(GPH10, 0);
-
-	/* adress of boot parameters */
-	gd->bd->bi_boot_params = CONFIG_BOOT_PARAM_ADDR;
-
-	return 0;
-}
-
-int dram_init(void)
-{
-	struct s3c24x0_memctl *memctl = s3c24x0_get_base_memctl();
-
-	/*
-	 * Configuring bus width and timing
-	 * Initialize clocks for each bank 0..5
-	 * Bank 3 and 4 are used for DM9000
-	 */
-	writel(BANK_CONF, &memctl->bwscon);
-	writel(B0_CONF, &memctl->bankcon[0]);
-	writel(B1_CONF, &memctl->bankcon[1]);
-	writel(B2_CONF, &memctl->bankcon[2]);
-	writel(B3_CONF, &memctl->bankcon[3]);
-	writel(B4_CONF, &memctl->bankcon[4]);
-	writel(B5_CONF, &memctl->bankcon[5]);
-
-	/* Bank 6 and 7 are used for DRAM */
-	writel(SDRAM_64MB, &memctl->bankcon[6]);
-	writel(SDRAM_64MB, &memctl->bankcon[7]);
-
-	writel(MEM_TIMING, &memctl->refresh);
-	writel(BANKSIZE_CONF, &memctl->banksize);
-	writel(B6_MRSR, &memctl->mrsrb6);
-	writel(B7_MRSR, &memctl->mrsrb7);
-
-	gd->ram_size = get_ram_size((void *) CONFIG_SYS_SDRAM_BASE,
-			PHYS_SDRAM_SIZE);
-	return 0;
-}
-
-int board_eth_init(bd_t *bis)
-{
-#ifdef CONFIG_DRIVER_DM9000
-	return dm9000_initialize(bis);
-#else
-	return 0;
-#endif
-}
diff --git a/board/friendlyarm/mini2440/mini2440.h b/board/friendlyarm/mini2440/mini2440.h
deleted file mode 100644
index db386eac01..0000000000
--- a/board/friendlyarm/mini2440/mini2440.h
+++ /dev/null
@@ -1,144 +0,0 @@
-#ifndef __MINI2440_BOARD_CONF_H__
-#define __MINI2440_BOARD_CONF_H__
-
-/* PLL Parameters */
-#define CLKDIVN_VAL	7
-#define M_MDIV		0x7f
-#define M_PDIV		0x2
-#define M_SDIV		0x1
-
-#define U_M_MDIV	0x38
-#define U_M_PDIV	0x2
-#define U_M_SDIV	0x2
-
-/* BWSCON */
-#define DW8				0x0
-#define DW16			0x1
-#define DW32			0x2
-#define WAIT			(0x1<<2)
-#define UBLB			(0x1<<3)
-
-#define B1_BWSCON		(DW32)
-#define B2_BWSCON		(DW16)
-#define B3_BWSCON		(DW16 + WAIT + UBLB)
-#define B4_BWSCON		(DW16 + WAIT + UBLB)
-#define B5_BWSCON		(DW16)
-#define B6_BWSCON		(DW32)
-#define B7_BWSCON		(DW32)
-
-/*
- * Bank Configuration
- */
-#define B0_Tacs			0x0	/*  0clk */
-#define B0_Tcos			0x0	/*  0clk */
-#define B0_Tacc			0x7	/* 14clk */
-#define B0_Tcoh			0x0	/*  0clk */
-#define B0_Tah			0x0	/*  0clk */
-#define B0_Tacp			0x0 /*  0clk */
-#define B0_PMC			0x0	/* normal */
-
-#define B1_Tacs			0x0
-#define B1_Tcos			0x0
-#define B1_Tacc			0x7
-#define B1_Tcoh			0x0
-#define B1_Tah			0x0
-#define B1_Tacp			0x0
-#define B1_PMC			0x0
-
-#define B2_Tacs			0x0
-#define B2_Tcos			0x0
-#define B2_Tacc			0x7
-#define B2_Tcoh			0x0
-#define B2_Tah			0x0
-#define B2_Tacp			0x0
-#define B2_PMC			0x0
-
-#define B3_Tacs			0x0
-#define B3_Tcos			0x3	/*  4clk */
-#define B3_Tacc			0x7
-#define B3_Tcoh			0x1	/*  1clk */
-#define B3_Tah			0x3	/*  4clk */
-#define B3_Tacp			0x0
-#define B3_PMC			0x0
-
-#define B4_Tacs			0x0
-#define B4_Tcos			0x3
-#define B4_Tacc			0x7
-#define B4_Tcoh			0x1
-#define B4_Tah			0x3
-#define B4_Tacp			0x0
-#define B4_PMC			0x0
-
-#define B5_Tacs			0x0
-#define B5_Tcos			0x0
-#define B5_Tacc			0x7
-#define B5_Tcoh			0x0
-#define B5_Tah			0x0
-#define B5_Tacp			0x0
-#define B5_PMC			0x0
-
-/*
- * SDRAM Configuration
- */
-#define SDRAM_MT		0x3	/* SDRAM */
-#define SDRAM_Trcd		0x0	/* 2clk */
-#define SDRAM_SCAN_9	0x1	/* 9bit */
-#define SDRAM_SCAN_10	0x2	/* 10bit */
-
-#define SDRAM_64MB	((SDRAM_MT<<15) + (SDRAM_Trcd<<2) + (SDRAM_SCAN_9))
-
-/*
- * Refresh Parameter
- */
-#define REFEN		0x1	/* Refresh enable */
-#define TREFMD		0x0	/* CBR(CAS before RAS)/Auto refresh */
-#define Trp			0x1	/* 3clk */
-#define Trc			0x3	/* 7clk */
-#define Tchr		0x0	/* unused */
-#define REFCNT	1012 /* period=10.37us, HCLK=100Mhz, (2048 + 1-10.37*100) */
-
-/*
- * MRSR Parameter
- */
-#define BL	0x0
-#define BT	0x0
-#define CL	0x3 /* 3 clocks */
-#define TM	0x0
-#define WBL	0x0
-
-/*
- * BankSize Parameter
- */
-#define BK76MAP	0x2 /* 128MB/128MB */
-#define SCLK_EN	0x1 /* SCLK active */
-#define SCKE_EN	0x1 /* SDRAM power down mode enable */
-#define BURST_EN	0x1 /* Burst enable */
-
-/*
- * Register values
- */
-#define BANK_CONF ((0 + (B1_BWSCON<<4) + (B2_BWSCON<<8) + (B3_BWSCON<<12) + \
-			(B4_BWSCON<<16) + (B5_BWSCON<<20) + (B6_BWSCON<<24) + \
-			(B7_BWSCON<<28)))
-
-#define B0_CONF	((B0_Tacs<<13) + (B0_Tcos<<11) + (B0_Tacc<<8) + \
-		(B0_Tcoh<<6) + (B0_Tah<<4) + (B0_Tacp<<2) + (B0_PMC))
-#define B1_CONF	((B1_Tacs<<13) + (B1_Tcos<<11) + (B1_Tacc<<8) + \
-		(B1_Tcoh<<6) + (B1_Tah<<4) + (B1_Tacp<<2) + (B1_PMC))
-#define B2_CONF	((B2_Tacs<<13) + (B2_Tcos<<11) + (B2_Tacc<<8) + \
-		(B2_Tcoh<<6) + (B2_Tah<<4) + (B2_Tacp<<2) + (B2_PMC))
-#define B3_CONF	((B3_Tacs<<13) + (B3_Tcos<<11) + (B3_Tacc<<8) + \
-		(B3_Tcoh<<6) + (B3_Tah<<4) + (B3_Tacp<<2) + (B3_PMC))
-#define B4_CONF	((B4_Tacs<<13) + (B4_Tcos<<11) + (B4_Tacc<<8) + \
-		(B4_Tcoh<<6) + (B4_Tah<<4) + (B4_Tacp<<2) + (B4_PMC))
-#define B5_CONF	((B5_Tacs<<13) + (B5_Tcos<<11) + (B5_Tacc<<8) + \
-		(B5_Tcoh<<6) + (B5_Tah<<4) + (B5_Tacp<<2) + (B5_PMC))
-
-#define MEM_TIMING (REFEN<<23) + (TREFMD<<22) + (Trp<<20) + \
-	(Trc<<18) + (Tchr<<16) + REFCNT
-
-#define BANKSIZE_CONF	(BK76MAP) + (SCLK_EN<<4) + (SCKE_EN<<5) + (BURST_EN<<7)
-#define B6_MRSR			(CL<<4)
-#define B7_MRSR			(CL<<4)
-
-#endif
diff --git a/board/funkwerk/vovpn-gw/Makefile b/board/funkwerk/vovpn-gw/Makefile
index 677a021170..325324782d 100644
--- a/board/funkwerk/vovpn-gw/Makefile
+++ b/board/funkwerk/vovpn-gw/Makefile
@@ -5,24 +5,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	:= $(BOARD).o flash.o m88e6060.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	:= vovpn-gw.o flash.o m88e6060.o
diff --git a/board/g2000/Makefile b/board/g2000/Makefile
index 0d202ac071..74c8053acc 100644
--- a/board/g2000/Makefile
+++ b/board/g2000/Makefile
@@ -5,24 +5,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	= $(BOARD).o strataflash.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(OBJS) $(SOBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	= g2000.o strataflash.o
diff --git a/board/gaisler/gr_cpci_ax2000/Makefile b/board/gaisler/gr_cpci_ax2000/Makefile
index baa067d9df..a08e04dbe8 100644
--- a/board/gaisler/gr_cpci_ax2000/Makefile
+++ b/board/gaisler/gr_cpci_ax2000/Makefile
@@ -1,4 +1,3 @@
-
 #
 # (C) Copyright 2003-2006
 # Wolfgang Denk, DENX Software Engineering, wd@denx.de.
@@ -6,25 +5,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	:= $(BOARD).o
-
-#flash.o
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	:= gr_cpci_ax2000.o
diff --git a/board/gaisler/gr_cpci_ax2000/config.mk b/board/gaisler/gr_cpci_ax2000/config.mk
index e9c60286ce..731a53905f 100644
--- a/board/gaisler/gr_cpci_ax2000/config.mk
+++ b/board/gaisler/gr_cpci_ax2000/config.mk
@@ -17,6 +17,3 @@ CONFIG_SYS_TEXT_BASE = 0x00000000
 
 # U-BOOT IN SDRAM
 #CONFIG_SYS_TEXT_BASE = 0x60000000
-
-PLATFORM_CPPFLAGS += -DCONFIG_SYS_TEXT_BASE=$(CONFIG_SYS_TEXT_BASE) \
-	-I$(TOPDIR)/board
diff --git a/board/gaisler/gr_ep2s60/Makefile b/board/gaisler/gr_ep2s60/Makefile
index baa067d9df..059a9c03c4 100644
--- a/board/gaisler/gr_ep2s60/Makefile
+++ b/board/gaisler/gr_ep2s60/Makefile
@@ -1,4 +1,3 @@
-
 #
 # (C) Copyright 2003-2006
 # Wolfgang Denk, DENX Software Engineering, wd@denx.de.
@@ -6,25 +5,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	:= $(BOARD).o
-
-#flash.o
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	:= gr_ep2s60.o
diff --git a/board/gaisler/gr_ep2s60/config.mk b/board/gaisler/gr_ep2s60/config.mk
index 6c31a17f8c..6e01f07c0c 100644
--- a/board/gaisler/gr_ep2s60/config.mk
+++ b/board/gaisler/gr_ep2s60/config.mk
@@ -15,6 +15,3 @@ CONFIG_SYS_TEXT_BASE = 0x00000000
 
 # U-BOOT IN SDRAM
 #CONFIG_SYS_TEXT_BASE = 0x40000000
-
-PLATFORM_CPPFLAGS += -DCONFIG_SYS_TEXT_BASE=$(CONFIG_SYS_TEXT_BASE) \
-	-I$(TOPDIR)/board
diff --git a/board/gaisler/gr_xc3s_1500/Makefile b/board/gaisler/gr_xc3s_1500/Makefile
index baa067d9df..302c4611e0 100644
--- a/board/gaisler/gr_xc3s_1500/Makefile
+++ b/board/gaisler/gr_xc3s_1500/Makefile
@@ -1,4 +1,3 @@
-
 #
 # (C) Copyright 2003-2006
 # Wolfgang Denk, DENX Software Engineering, wd@denx.de.
@@ -6,25 +5,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	:= $(BOARD).o
-
-#flash.o
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	:= gr_xc3s_1500.o
diff --git a/board/gaisler/gr_xc3s_1500/config.mk b/board/gaisler/gr_xc3s_1500/config.mk
index 3b59cca5e6..e4a66cbcf1 100644
--- a/board/gaisler/gr_xc3s_1500/config.mk
+++ b/board/gaisler/gr_xc3s_1500/config.mk
@@ -14,6 +14,3 @@ CONFIG_SYS_TEXT_BASE = 0x00000000
 
 # U-BOOT IN RAM
 #CONFIG_SYS_TEXT_BASE = 0x40000000
-
-PLATFORM_CPPFLAGS += -DCONFIG_SYS_TEXT_BASE=$(CONFIG_SYS_TEXT_BASE) \
-	-I$(TOPDIR)/board
diff --git a/board/gaisler/grsim/Makefile b/board/gaisler/grsim/Makefile
index 2c0119e9c4..4c93bdae83 100644
--- a/board/gaisler/grsim/Makefile
+++ b/board/gaisler/grsim/Makefile
@@ -5,24 +5,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	:= $(BOARD).o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	:= grsim.o
diff --git a/board/gaisler/grsim/config.mk b/board/gaisler/grsim/config.mk
index d98ed54c07..d1f61dac76 100644
--- a/board/gaisler/grsim/config.mk
+++ b/board/gaisler/grsim/config.mk
@@ -14,6 +14,3 @@ CONFIG_SYS_TEXT_BASE = 0x00000000
 
 # U-BOOT IN RAM
 #CONFIG_SYS_TEXT_BASE = 0x40000000
-
-PLATFORM_CPPFLAGS += -DCONFIG_SYS_TEXT_BASE=$(CONFIG_SYS_TEXT_BASE) \
-	-I$(TOPDIR)/board
diff --git a/board/gaisler/grsim_leon2/Makefile b/board/gaisler/grsim_leon2/Makefile
index 2c0119e9c4..5468305caa 100644
--- a/board/gaisler/grsim_leon2/Makefile
+++ b/board/gaisler/grsim_leon2/Makefile
@@ -5,24 +5,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	:= $(BOARD).o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	:= grsim_leon2.o
diff --git a/board/gaisler/grsim_leon2/config.mk b/board/gaisler/grsim_leon2/config.mk
index 59e4e31690..f98b23b800 100644
--- a/board/gaisler/grsim_leon2/config.mk
+++ b/board/gaisler/grsim_leon2/config.mk
@@ -14,6 +14,3 @@ CONFIG_SYS_TEXT_BASE = 0x00000000
 
 # RUN U-BOOT FROM RAM
 #CONFIG_SYS_TEXT_BASE = 0x40000000
-
-PLATFORM_CPPFLAGS += -DCONFIG_SYS_TEXT_BASE=$(CONFIG_SYS_TEXT_BASE) \
-	-I$(TOPDIR)/board
diff --git a/board/galaxy5200/Makefile b/board/galaxy5200/Makefile
index 4a7d872afa..e0fcd39515 100644
--- a/board/galaxy5200/Makefile
+++ b/board/galaxy5200/Makefile
@@ -5,24 +5,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	:= $(BOARD).o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	:= galaxy5200.o
diff --git a/board/gateworks/gw_ventana/Makefile b/board/gateworks/gw_ventana/Makefile
new file mode 100644
index 0000000000..e8dab89c65
--- /dev/null
+++ b/board/gateworks/gw_ventana/Makefile
@@ -0,0 +1,10 @@
+#
+# Copyright (C) 2012-2013, Guennadi Liakhovetski <lg@denx.de>
+# (C) Copyright 2012-2013 Freescale Semiconductor, Inc.
+# Copyright (C) 2013, Gateworks Corporation
+#
+# SPDX-License-Identifier:  GPL-2.0+
+#
+
+obj-y  := gw_ventana.o gsc.o
+
diff --git a/board/gateworks/gw_ventana/README b/board/gateworks/gw_ventana/README
new file mode 100644
index 0000000000..9e697d6199
--- /dev/null
+++ b/board/gateworks/gw_ventana/README
@@ -0,0 +1,55 @@
+U-Boot for the Gateworks Ventana Product Family boards
+
+This file contains information for the port of U-Boot to the Gateworks
+Ventana Product family boards.
+
+1. Boot source, boot from NAND
+------------------------------
+
+The i.MX6 BOOT ROM expects some structures that provide details of NAND layout
+and bad block information (referred to as 'bootstreams') which are replicated
+multiple times in NAND. The number of replications is configurable through
+board strapping options and eFUSE settings.  The Freescale 'kobs-ng'
+application from the Freescale LTIB BSP, which runs under Linux, must be used
+to program the bootstream in order to setup the replicated headers correctly.
+
+The Gateworks Ventana boards with NAND flash have been factory programmed
+such that their eFUSE settings expect 2 copies of the boostream (this is
+specified by providing kobs-ng with the --search_exponent=1 argument). Once in
+Linux with MTD support for the NAND on /dev/mtd0 you can program the boostream
+with:
+
+kobs-ng init -v -x --search_exponent=1 u-boot.imx
+
+The kobs-ng application uses an imximage (u-boot.imx) which contains the
+Image Vector Table (IVT) and Device Configuration Data (DCD) structures that
+the i.MX6 BOOT ROM requires to boot.  The kobs-ng adds the Firmware
+Configuration Block (FCB) and Discovered Bad Block Table (DBBT).
+
+This information is taken from:
+  http://trac.gateworks.com/wiki/ventana/bootloader#NANDFLASH
+
+More details about the i.MX6 BOOT ROM can be found in the IMX6 reference manual.
+
+2. Build
+--------
+
+There are several Gateworks Ventana boards that share a simliar design but
+vary based on CPU, Memory configuration, and subloaded devices.  Although
+the subloaded devices are handled dynamically in the bootloader using
+factory configured EEPROM data to modify the device-tree, the CPU choice
+(IMX6Q vs IMX6DL) and memory configurations are currently compile-time
+options.
+
+The following Gateworks Ventana configurations exist:
+ gwventanaq1gspi: MX6Q,1GB,SPI FLASH
+ gwventanaq     : MX6Q,512MB,NAND FLASH
+ gwventanaq1g   : MX6Q,1GB,NAND FLASH
+ gwventanadl    : MX6DL,512MB,NAND FLASH
+ gwventanadl1g  : MX6DL,1GB,NAND FLASH
+
+To build U-Boot for the MX6Q,1GB,NAND FLASH for example:
+
+ make gwventanaq1g_config
+ make
+
diff --git a/board/gateworks/gw_ventana/clocks.cfg b/board/gateworks/gw_ventana/clocks.cfg
new file mode 100644
index 0000000000..a8118a258e
--- /dev/null
+++ b/board/gateworks/gw_ventana/clocks.cfg
@@ -0,0 +1,42 @@
+/*
+ * Copyright (C) 2013 Boundary Devices
+ * Copyright (C) 2013 Gateworks Corporation
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ * Device Configuration Data (DCD)
+ *
+ * Each entry must have the format:
+ * Addr-type           Address        Value
+ *
+ * where:
+ *      Addr-type register length (1,2 or 4 bytes)
+ *      Address   absolute address of the register
+ *      value     value to be stored in the register
+ */
+
+/* set the default clock gate to save power */
+DATA 4, CCM_CCGR0, 0x00C03F3F
+DATA 4, CCM_CCGR1, 0x0030FC03
+DATA 4, CCM_CCGR2, 0x0FFFC000
+DATA 4, CCM_CCGR3, 0x3FF00000
+DATA 4, CCM_CCGR4, 0xFFFFF300 /* enable NAND/GPMI/BCH clocks */
+DATA 4, CCM_CCGR5, 0x0F0000C3
+DATA 4, CCM_CCGR6, 0x000003FF
+
+/* enable AXI cache for VDOA/VPU/IPU */
+DATA 4, MX6_IOMUXC_GPR4, 0xF00000CF
+/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
+DATA 4, MX6_IOMUXC_GPR6, 0x007F007F
+DATA 4, MX6_IOMUXC_GPR7, 0x007F007F
+
+/*
+ * Setup CCM_CCOSR register as follows:
+ *
+ * cko1_en  = 1    --> CKO1 enabled
+ * cko1_div = 111  --> divide by 8
+ * cko1_sel = 1011 --> ahb_clk_root
+ *
+ * This sets CKO1 at ahb_clk_root/8 = 132/8 = 16.5 MHz
+ */
+DATA 4, CCM_CCOSR, 0x000000fb
diff --git a/board/gateworks/gw_ventana/gsc.c b/board/gateworks/gw_ventana/gsc.c
new file mode 100644
index 0000000000..37966abba9
--- /dev/null
+++ b/board/gateworks/gw_ventana/gsc.c
@@ -0,0 +1,129 @@
+/*
+ * Copyright (C) 2013 Gateworks Corporation
+ *
+ * Author: Tim Harvey <tharvey@gateworks.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <asm/errno.h>
+#include <common.h>
+#include <i2c.h>
+#include <linux/ctype.h>
+
+#include "gsc.h"
+
+#define MINMAX(n, percent)	((n)*(100-percent)/100), ((n)*(100+percent)/100)
+
+/*
+ * The Gateworks System Controller will fail to ACK a master transaction if
+ * it is busy, which can occur during its 1HZ timer tick while reading ADC's.
+ * When this does occur, it will never be busy long enough to fail more than
+ * 2 back-to-back transfers.  Thus we wrap i2c_read and i2c_write with
+ * 3 retries.
+ */
+int gsc_i2c_read(uchar chip, uint addr, int alen, uchar *buf, int len)
+{
+	int retry = 3;
+	int n = 0;
+	int ret;
+
+	while (n++ < retry) {
+		ret = i2c_read(chip, addr, alen, buf, len);
+		if (!ret)
+			break;
+		debug("%s: 0x%02x 0x%02x retry%d: %d\n", __func__, chip, addr,
+		      n, ret);
+		if (ret != -ENODEV)
+			break;
+		mdelay(10);
+	}
+	return ret;
+}
+
+int gsc_i2c_write(uchar chip, uint addr, int alen, uchar *buf, int len)
+{
+	int retry = 3;
+	int n = 0;
+	int ret;
+
+	while (n++ < retry) {
+		ret = i2c_write(chip, addr, alen, buf, len);
+		if (!ret)
+			break;
+		debug("%s: 0x%02x 0x%02x retry%d: %d\n", __func__, chip, addr,
+		      n, ret);
+		if (ret != -ENODEV)
+			break;
+		mdelay(10);
+	}
+	mdelay(1);
+	return ret;
+}
+
+#ifdef CONFIG_CMD_GSC
+static void read_hwmon(const char *name, uint reg, uint size, uint low,
+		       uint high)
+{
+	unsigned char buf[3];
+	uint ui;
+
+	printf("%-8s:", name);
+	memset(buf, 0, sizeof(buf));
+	if (gsc_i2c_read(GSC_HWMON_ADDR, reg, 1, buf, size)) {
+		puts("fRD\n");
+	} else {
+		ui = buf[0] | (buf[1]<<8) | (buf[2]<<16);
+		if (ui == 0xffffff)
+			printf("invalid");
+		else if (ui < low)
+			printf("%d Failed - Low", ui);
+		else if (ui > high)
+			printf("%d Failed - High", ui);
+		else
+			printf("%d", ui);
+	}
+	puts("\n");
+}
+
+int do_gsc(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	const char *model = getenv("model");
+
+	i2c_set_bus_num(0);
+	read_hwmon("Temp",     GSC_HWMON_TEMP, 2, 0, 9000);
+	read_hwmon("VIN",      GSC_HWMON_VIN, 3, 8000, 60000);
+	read_hwmon("VBATT",    GSC_HWMON_VBATT, 3, 1800, 3500);
+	read_hwmon("VDD_3P3",  GSC_HWMON_VDD_3P3, 3, MINMAX(3300, 10));
+	read_hwmon("VDD_HIGH", GSC_HWMON_VDD_HIGH, 3, MINMAX(3000, 10));
+	read_hwmon("VDD_DDR",  GSC_HWMON_VDD_DDR, 3, MINMAX(1500, 10));
+	read_hwmon("VDD_5P0",  GSC_HWMON_VDD_5P0, 3, MINMAX(5000, 10));
+	read_hwmon("VDD_2P5",  GSC_HWMON_VDD_2P5, 3, MINMAX(2500, 10));
+	read_hwmon("VDD_1P8",  GSC_HWMON_VDD_1P8, 3, MINMAX(1800, 10));
+
+	switch (model[3]) {
+	case '1': /* GW51xx */
+		read_hwmon("VDD_CORE", GSC_HWMON_VDD_CORE, 3, MINMAX(1175, 10));
+		read_hwmon("VDD_SOC",  GSC_HWMON_VDD_SOC, 3, MINMAX(1175, 10));
+		break;
+	case '2': /* GW52xx */
+	case '3': /* GW53xx */
+		read_hwmon("VDD_CORE", GSC_HWMON_VDD_CORE, 3, MINMAX(1175, 10));
+		read_hwmon("VDD_SOC",  GSC_HWMON_VDD_SOC, 3, MINMAX(1175, 10));
+		read_hwmon("VDD_1P0",  GSC_HWMON_VDD_1P0, 3, MINMAX(1000, 10));
+		break;
+	case '4': /* GW54xx */
+		read_hwmon("VDD_CORE", GSC_HWMON_VDD_CORE, 3, MINMAX(1375, 10));
+		read_hwmon("VDD_SOC",  GSC_HWMON_VDD_SOC, 3, MINMAX(1375, 10));
+		read_hwmon("VDD_1P0",  GSC_HWMON_VDD_1P0, 3, MINMAX(1000, 10));
+		break;
+	}
+	return 0;
+}
+
+U_BOOT_CMD(gsc, 1, 1, do_gsc,
+	   "GSC test",
+	   ""
+);
+
+#endif /* CONFIG_CMD_GSC */
diff --git a/board/gateworks/gw_ventana/gsc.h b/board/gateworks/gw_ventana/gsc.h
new file mode 100644
index 0000000000..da970c39d6
--- /dev/null
+++ b/board/gateworks/gw_ventana/gsc.h
@@ -0,0 +1,64 @@
+/*
+ * Copyright (C) 2013 Gateworks Corporation
+ *
+ * Author: Tim Harvey <tharvey@gateworks.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __ASSEMBLY__
+
+/* i2c slave addresses */
+#define GSC_SC_ADDR		0x20
+#define GSC_RTC_ADDR		0x68
+#define GSC_HWMON_ADDR		0x29
+#define GSC_EEPROM_ADDR		0x51
+
+/* System Controller registers */
+enum {
+	GSC_SC_CTRL0		= 0x00,
+	GSC_SC_CTRL1		= 0x01,
+	GSC_SC_STATUS		= 0x0a,
+	GSC_SC_FWVER		= 0x0e,
+};
+
+/* System Controller Control1 bits */
+enum {
+	GSC_SC_CTRL1_WDDIS	= 7, /* 1 = disable watchdog */
+};
+
+/* System Controller Interrupt bits */
+enum {
+	GSC_SC_IRQ_PB		= 0, /* Pushbutton switch */
+	GSC_SC_IRQ_SECURE	= 1, /* Secure Key erase operation complete */
+	GSC_SC_IRQ_EEPROM_WP	= 2, /* EEPROM write violation */
+	GSC_SC_IRQ_GPIO		= 4, /* GPIO change */
+	GSC_SC_IRQ_TAMPER	= 5, /* Tamper detect */
+	GSC_SC_IRQ_WATCHDOG	= 6, /* Watchdog trip */
+	GSC_SC_IRQ_PBLONG	= 7, /* Pushbutton long hold */
+};
+
+/* Hardware Monitor registers */
+enum {
+	GSC_HWMON_TEMP		= 0x00,
+	GSC_HWMON_VIN		= 0x02,
+	GSC_HWMON_VDD_3P3	= 0x05,
+	GSC_HWMON_VBATT		= 0x08,
+	GSC_HWMON_VDD_5P0	= 0x0b,
+	GSC_HWMON_VDD_CORE	= 0x0e,
+	GSC_HWMON_VDD_HIGH	= 0x14,
+	GSC_HWMON_VDD_DDR	= 0x17,
+	GSC_HWMON_VDD_SOC	= 0x11,
+	GSC_HWMON_VDD_1P8	= 0x1d,
+	GSC_HWMON_VDD_2P5	= 0x23,
+	GSC_HWMON_VDD_1P0	= 0x20,
+};
+
+/*
+ * I2C transactions to the GSC are done via these functions which
+ * perform retries in the case of a busy GSC NAK'ing the transaction
+ */
+int gsc_i2c_read(uchar chip, uint addr, int alen, uchar *buf, int len);
+int gsc_i2c_write(uchar chip, uint addr, int alen, uchar *buf, int len);
+#endif
+
diff --git a/board/gateworks/gw_ventana/gw_ventana.c b/board/gateworks/gw_ventana/gw_ventana.c
new file mode 100644
index 0000000000..c130e2c1ed
--- /dev/null
+++ b/board/gateworks/gw_ventana/gw_ventana.c
@@ -0,0 +1,1263 @@
+/*
+ * Copyright (C) 2013 Gateworks Corporation
+ *
+ * Author: Tim Harvey <tharvey@gateworks.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/iomux.h>
+#include <asm/arch/mx6-pins.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/gpio.h>
+#include <asm/imx-common/iomux-v3.h>
+#include <asm/imx-common/mxc_i2c.h>
+#include <asm/imx-common/boot_mode.h>
+#include <asm/imx-common/sata.h>
+#include <jffs2/load_kernel.h>
+#include <hwconfig.h>
+#include <i2c.h>
+#include <linux/ctype.h>
+#include <fdt_support.h>
+#include <fsl_esdhc.h>
+#include <miiphy.h>
+#include <mmc.h>
+#include <mtd_node.h>
+#include <netdev.h>
+#include <power/pmic.h>
+#include <power/pfuze100_pmic.h>
+#include <i2c.h>
+#include <fdt_support.h>
+#include <jffs2/load_kernel.h>
+#include <spi_flash.h>
+
+#include "gsc.h"
+#include "ventana_eeprom.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* GPIO's common to all baseboards */
+#define GP_PHY_RST	IMX_GPIO_NR(1, 30)
+#define GP_USB_OTG_PWR	IMX_GPIO_NR(3, 22)
+#define GP_SD3_CD	IMX_GPIO_NR(7, 0)
+#define GP_RS232_EN	IMX_GPIO_NR(2, 11)
+#define GP_MSATA_SEL	IMX_GPIO_NR(2, 8)
+
+/* I2C bus numbers */
+#define I2C_GSC		0
+#define I2C_PMIC	1
+
+#define UART_PAD_CTRL  (PAD_CTL_PKE | PAD_CTL_PUE |		\
+	PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |		\
+	PAD_CTL_DSE_40ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
+
+#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE |		\
+	PAD_CTL_PUS_47K_UP  | PAD_CTL_SPEED_LOW |		\
+	PAD_CTL_DSE_80ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
+
+#define ENET_PAD_CTRL  (PAD_CTL_PKE | PAD_CTL_PUE |		\
+	PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED	  |		\
+	PAD_CTL_DSE_40ohm   | PAD_CTL_HYS)
+
+#define SPI_PAD_CTRL (PAD_CTL_HYS |				\
+	PAD_CTL_PUS_100K_DOWN | PAD_CTL_SPEED_MED |		\
+	PAD_CTL_DSE_40ohm     | PAD_CTL_SRE_FAST)
+
+#define DIO_PAD_CTRL  (PAD_CTL_PKE | PAD_CTL_PUE |		\
+	PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |		\
+	PAD_CTL_DSE_34ohm | PAD_CTL_HYS | PAD_CTL_SRE_FAST)
+
+#define I2C_PAD_CTRL  (PAD_CTL_PUS_100K_UP |			\
+	PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS |	\
+	PAD_CTL_ODE | PAD_CTL_SRE_FAST)
+
+/*
+ * EEPROM board info struct populated by read_eeprom so that we only have to
+ * read it once.
+ */
+static struct ventana_board_info ventana_info;
+
+enum {
+	GW54proto, /* original GW5400-A prototype */
+	GW51xx,
+	GW52xx,
+	GW53xx,
+	GW54xx,
+	GW_UNKNOWN,
+};
+
+int board_type;
+
+/* UART1: Function varies per baseboard */
+iomux_v3_cfg_t const uart1_pads[] = {
+	MX6_PAD_SD3_DAT6__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
+	MX6_PAD_SD3_DAT7__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+/* UART2: Serial Console */
+iomux_v3_cfg_t const uart2_pads[] = {
+	MX6_PAD_SD4_DAT7__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
+	MX6_PAD_SD4_DAT4__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
+
+/* I2C1: GSC */
+struct i2c_pads_info i2c_pad_info0 = {
+	.scl = {
+		.i2c_mode = MX6_PAD_EIM_D21__I2C1_SCL | PC,
+		.gpio_mode = MX6_PAD_EIM_D21__GPIO3_IO21 | PC,
+		.gp = IMX_GPIO_NR(3, 21)
+	},
+	.sda = {
+		.i2c_mode = MX6_PAD_EIM_D28__I2C1_SDA | PC,
+		.gpio_mode = MX6_PAD_EIM_D28__GPIO3_IO28 | PC,
+		.gp = IMX_GPIO_NR(3, 28)
+	}
+};
+
+/* I2C2: PMIC/PCIe Switch/PCIe Clock/Mezz */
+struct i2c_pads_info i2c_pad_info1 = {
+	.scl = {
+		.i2c_mode = MX6_PAD_KEY_COL3__I2C2_SCL | PC,
+		.gpio_mode = MX6_PAD_KEY_COL3__GPIO4_IO12 | PC,
+		.gp = IMX_GPIO_NR(4, 12)
+	},
+	.sda = {
+		.i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA | PC,
+		.gpio_mode = MX6_PAD_KEY_ROW3__GPIO4_IO13 | PC,
+		.gp = IMX_GPIO_NR(4, 13)
+	}
+};
+
+/* I2C3: Misc/Expansion */
+struct i2c_pads_info i2c_pad_info2 = {
+	.scl = {
+		.i2c_mode = MX6_PAD_GPIO_3__I2C3_SCL | PC,
+		.gpio_mode = MX6_PAD_GPIO_3__GPIO1_IO03 | PC,
+		.gp = IMX_GPIO_NR(1, 3)
+	},
+	.sda = {
+		.i2c_mode = MX6_PAD_GPIO_6__I2C3_SDA | PC,
+		.gpio_mode = MX6_PAD_GPIO_6__GPIO1_IO06 | PC,
+		.gp = IMX_GPIO_NR(1, 6)
+	}
+};
+
+/* MMC */
+iomux_v3_cfg_t const usdhc3_pads[] = {
+	MX6_PAD_SD3_CLK__SD3_CLK    | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD3_CMD__SD3_CMD    | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD3_DAT5__GPIO7_IO00  | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
+};
+
+/* ENET */
+iomux_v3_cfg_t const enet_pads[] = {
+	MX6_PAD_ENET_MDIO__ENET_MDIO		| MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_ENET_MDC__ENET_MDC		| MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_RGMII_TXC__RGMII_TXC		| MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_RGMII_TD0__RGMII_TD0		| MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_RGMII_TD1__RGMII_TD1		| MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_RGMII_TD2__RGMII_TD2		| MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_RGMII_TD3__RGMII_TD3		| MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL	| MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_ENET_REF_CLK__ENET_TX_CLK	| MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_RGMII_RXC__RGMII_RXC		| MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_RGMII_RD0__RGMII_RD0		| MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_RGMII_RD1__RGMII_RD1		| MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_RGMII_RD2__RGMII_RD2		| MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_RGMII_RD3__RGMII_RD3		| MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL	| MUX_PAD_CTRL(ENET_PAD_CTRL),
+	/* PHY nRST */
+	MX6_PAD_ENET_TXD0__GPIO1_IO30		| MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+/* NAND */
+iomux_v3_cfg_t const nfc_pads[] = {
+	MX6_PAD_NANDF_CLE__NAND_CLE     | MUX_PAD_CTRL(NO_PAD_CTRL),
+	MX6_PAD_NANDF_ALE__NAND_ALE     | MUX_PAD_CTRL(NO_PAD_CTRL),
+	MX6_PAD_NANDF_WP_B__NAND_WP_B   | MUX_PAD_CTRL(NO_PAD_CTRL),
+	MX6_PAD_NANDF_RB0__NAND_READY_B | MUX_PAD_CTRL(NO_PAD_CTRL),
+	MX6_PAD_NANDF_CS0__NAND_CE0_B   | MUX_PAD_CTRL(NO_PAD_CTRL),
+	MX6_PAD_SD4_CMD__NAND_RE_B      | MUX_PAD_CTRL(NO_PAD_CTRL),
+	MX6_PAD_SD4_CLK__NAND_WE_B      | MUX_PAD_CTRL(NO_PAD_CTRL),
+	MX6_PAD_NANDF_D0__NAND_DATA00   | MUX_PAD_CTRL(NO_PAD_CTRL),
+	MX6_PAD_NANDF_D1__NAND_DATA01   | MUX_PAD_CTRL(NO_PAD_CTRL),
+	MX6_PAD_NANDF_D2__NAND_DATA02   | MUX_PAD_CTRL(NO_PAD_CTRL),
+	MX6_PAD_NANDF_D3__NAND_DATA03   | MUX_PAD_CTRL(NO_PAD_CTRL),
+	MX6_PAD_NANDF_D4__NAND_DATA04   | MUX_PAD_CTRL(NO_PAD_CTRL),
+	MX6_PAD_NANDF_D5__NAND_DATA05   | MUX_PAD_CTRL(NO_PAD_CTRL),
+	MX6_PAD_NANDF_D6__NAND_DATA06   | MUX_PAD_CTRL(NO_PAD_CTRL),
+	MX6_PAD_NANDF_D7__NAND_DATA07   | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+#ifdef CONFIG_CMD_NAND
+static void setup_gpmi_nand(void)
+{
+	struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+
+	/* config gpmi nand iomux */
+	imx_iomux_v3_setup_multiple_pads(nfc_pads, ARRAY_SIZE(nfc_pads));
+
+	/* config gpmi and bch clock to 100 MHz */
+	clrsetbits_le32(&mxc_ccm->cs2cdr,
+			MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK |
+			MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK |
+			MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK,
+			MXC_CCM_CS2CDR_ENFC_CLK_PODF(0) |
+			MXC_CCM_CS2CDR_ENFC_CLK_PRED(3) |
+			MXC_CCM_CS2CDR_ENFC_CLK_SEL(3));
+
+	/* enable gpmi and bch clock gating */
+	setbits_le32(&mxc_ccm->CCGR4,
+		     MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
+		     MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
+		     MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
+		     MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
+		     MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET);
+
+	/* enable apbh clock gating */
+	setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK);
+}
+#endif
+
+static void setup_iomux_enet(void)
+{
+	imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
+
+	/* toggle PHY_RST# */
+	gpio_direction_output(GP_PHY_RST, 0);
+	mdelay(2);
+	gpio_set_value(GP_PHY_RST, 1);
+}
+
+static void setup_iomux_uart(void)
+{
+	imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
+	imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads));
+}
+
+#ifdef CONFIG_USB_EHCI_MX6
+iomux_v3_cfg_t const usb_pads[] = {
+	MX6_PAD_GPIO_1__USB_OTG_ID   | MUX_PAD_CTRL(DIO_PAD_CTRL),
+	MX6_PAD_KEY_COL4__USB_OTG_OC | MUX_PAD_CTRL(DIO_PAD_CTRL),
+	MX6_PAD_EIM_D22__GPIO3_IO22  | MUX_PAD_CTRL(DIO_PAD_CTRL), /* OTG PWR */
+};
+
+int board_ehci_hcd_init(int port)
+{
+	struct ventana_board_info *info = &ventana_info;
+
+	imx_iomux_v3_setup_multiple_pads(usb_pads, ARRAY_SIZE(usb_pads));
+
+	/* Reset USB HUB (present on GW54xx/GW53xx) */
+	switch (info->model[3]) {
+	case '3': /* GW53xx */
+		imx_iomux_v3_setup_pad(MX6_PAD_GPIO_9__GPIO1_IO09|
+				       MUX_PAD_CTRL(NO_PAD_CTRL));
+		gpio_direction_output(IMX_GPIO_NR(1, 9), 0);
+		mdelay(2);
+		gpio_set_value(IMX_GPIO_NR(1, 9), 1);
+		break;
+	case '4': /* GW54xx */
+		imx_iomux_v3_setup_pad(MX6_PAD_SD1_DAT0__GPIO1_IO16 |
+				       MUX_PAD_CTRL(NO_PAD_CTRL));
+		gpio_direction_output(IMX_GPIO_NR(1, 16), 0);
+		mdelay(2);
+		gpio_set_value(IMX_GPIO_NR(1, 16), 1);
+		break;
+	}
+
+	return 0;
+}
+
+int board_ehci_power(int port, int on)
+{
+	if (port)
+		return 0;
+	gpio_set_value(GP_USB_OTG_PWR, on);
+	return 0;
+}
+#endif /* CONFIG_USB_EHCI_MX6 */
+
+#ifdef CONFIG_FSL_ESDHC
+struct fsl_esdhc_cfg usdhc_cfg = { USDHC3_BASE_ADDR };
+
+int board_mmc_getcd(struct mmc *mmc)
+{
+	/* Card Detect */
+	gpio_direction_input(GP_SD3_CD);
+	return !gpio_get_value(GP_SD3_CD);
+}
+
+int board_mmc_init(bd_t *bis)
+{
+	/* Only one USDHC controller on Ventana */
+	imx_iomux_v3_setup_multiple_pads(usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
+	usdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
+	usdhc_cfg.max_bus_width = 4;
+
+	return fsl_esdhc_initialize(bis, &usdhc_cfg);
+}
+#endif /* CONFIG_FSL_ESDHC */
+
+#ifdef CONFIG_MXC_SPI
+iomux_v3_cfg_t const ecspi1_pads[] = {
+	/* SS1 */
+	MX6_PAD_EIM_D19__GPIO3_IO19  | MUX_PAD_CTRL(SPI_PAD_CTRL),
+	MX6_PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
+	MX6_PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
+	MX6_PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
+};
+
+static void setup_spi(void)
+{
+	gpio_direction_output(CONFIG_SF_DEFAULT_CS, 1);
+	imx_iomux_v3_setup_multiple_pads(ecspi1_pads,
+					 ARRAY_SIZE(ecspi1_pads));
+}
+#endif
+
+/* configure eth0 PHY board-specific LED behavior */
+int board_phy_config(struct phy_device *phydev)
+{
+	unsigned short val;
+
+	/* Marvel 88E1510 */
+	if (phydev->phy_id == 0x1410dd1) {
+		/*
+		 * Page 3, Register 16: LED[2:0] Function Control Register
+		 * LED[0] (SPD:Amber) R16_3.3:0 to 0111: on-GbE link
+		 * LED[1] (LNK:Green) R16_3.7:4 to 0001: on-link, blink-activity
+		 */
+		phy_write(phydev, MDIO_DEVAD_NONE, 22, 3);
+		val = phy_read(phydev, MDIO_DEVAD_NONE, 16);
+		val &= 0xff00;
+		val |= 0x0017;
+		phy_write(phydev, MDIO_DEVAD_NONE, 16, val);
+		phy_write(phydev, MDIO_DEVAD_NONE, 22, 0);
+	}
+
+	if (phydev->drv->config)
+		phydev->drv->config(phydev);
+
+	return 0;
+}
+
+int board_eth_init(bd_t *bis)
+{
+	setup_iomux_enet();
+
+#ifdef CONFIG_FEC_MXC
+	cpu_eth_init(bis);
+#endif
+
+#ifdef CONFIG_CI_UDC
+	/* For otg ethernet*/
+	usb_eth_initialize(bis);
+#endif
+
+	return 0;
+}
+
+/* read ventana EEPROM, check for validity, and return baseboard type */
+static int
+read_eeprom(void)
+{
+	int i;
+	int chksum;
+	char baseboard;
+	int type;
+	struct ventana_board_info *info = &ventana_info;
+	unsigned char *buf = (unsigned char *)&ventana_info;
+
+	memset(info, 0, sizeof(ventana_info));
+
+	/*
+	 * On a board with a missing/depleted backup battery for GSC, the
+	 * board may be ready to probe the GSC before its firmware is
+	 * running.  We will wait here indefinately for the GSC/EEPROM.
+	 */
+	while (1) {
+		if (0 == i2c_set_bus_num(I2C_GSC) &&
+		    0 == i2c_probe(GSC_EEPROM_ADDR))
+			break;
+		mdelay(1);
+	}
+
+	/* read eeprom config section */
+	if (gsc_i2c_read(GSC_EEPROM_ADDR, 0x00, 1, buf, sizeof(ventana_info))) {
+		puts("EEPROM: Failed to read EEPROM\n");
+		info->model[0] = 0;
+		return GW_UNKNOWN;
+	}
+
+	/* sanity checks */
+	if (info->model[0] != 'G' || info->model[1] != 'W') {
+		puts("EEPROM: Invalid Model in EEPROM\n");
+		info->model[0] = 0;
+		return GW_UNKNOWN;
+	}
+
+	/* validate checksum */
+	for (chksum = 0, i = 0; i < sizeof(*info)-2; i++)
+		chksum += buf[i];
+	if ((info->chksum[0] != chksum>>8) ||
+	    (info->chksum[1] != (chksum&0xff))) {
+		puts("EEPROM: Failed EEPROM checksum\n");
+		info->model[0] = 0;
+		return GW_UNKNOWN;
+	}
+
+	/* original GW5400-A prototype */
+	baseboard = info->model[3];
+	if (strncasecmp((const char *)info->model, "GW5400-A", 8) == 0)
+		baseboard = '0';
+
+	switch (baseboard) {
+	case '0': /* original GW5400-A prototype */
+		type = GW54proto;
+		break;
+	case '1':
+		type = GW51xx;
+		break;
+	case '2':
+		type = GW52xx;
+		break;
+	case '3':
+		type = GW53xx;
+		break;
+	case '4':
+		type = GW54xx;
+		break;
+	default:
+		printf("EEPROM: Unknown model in EEPROM: %s\n", info->model);
+		type = GW_UNKNOWN;
+		break;
+	}
+	return type;
+}
+
+/*
+ * Baseboard specific GPIO
+ */
+
+/* common to add baseboards */
+static iomux_v3_cfg_t const gw_gpio_pads[] = {
+	/* MSATA_EN */
+	MX6_PAD_SD4_DAT0__GPIO2_IO08 | MUX_PAD_CTRL(NO_PAD_CTRL),
+	/* RS232_EN# */
+	MX6_PAD_SD4_DAT3__GPIO2_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+/* prototype */
+static iomux_v3_cfg_t const gwproto_gpio_pads[] = {
+	/* PANLEDG# */
+	MX6_PAD_KEY_COL0__GPIO4_IO06 | MUX_PAD_CTRL(NO_PAD_CTRL),
+	/* PANLEDR# */
+	MX6_PAD_KEY_ROW0__GPIO4_IO07 | MUX_PAD_CTRL(NO_PAD_CTRL),
+	/* LOCLED# */
+	MX6_PAD_KEY_ROW4__GPIO4_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL),
+	/* RS485_EN */
+	MX6_PAD_SD3_DAT4__GPIO7_IO01 | MUX_PAD_CTRL(NO_PAD_CTRL),
+	/* IOEXP_PWREN# */
+	MX6_PAD_EIM_A19__GPIO2_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL),
+	/* IOEXP_IRQ# */
+	MX6_PAD_EIM_A20__GPIO2_IO18 | MUX_PAD_CTRL(NO_PAD_CTRL),
+	/* VID_EN */
+	MX6_PAD_EIM_D31__GPIO3_IO31 | MUX_PAD_CTRL(NO_PAD_CTRL),
+	/* DIOI2C_DIS# */
+	MX6_PAD_GPIO_19__GPIO4_IO05 | MUX_PAD_CTRL(NO_PAD_CTRL),
+	/* PCICK_SSON */
+	MX6_PAD_SD1_CLK__GPIO1_IO20 | MUX_PAD_CTRL(NO_PAD_CTRL),
+	/* PCI_RST# */
+	MX6_PAD_ENET_TXD1__GPIO1_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const gw51xx_gpio_pads[] = {
+	/* PANLEDG# */
+	MX6_PAD_KEY_COL0__GPIO4_IO06 | MUX_PAD_CTRL(NO_PAD_CTRL),
+	/* PANLEDR# */
+	MX6_PAD_KEY_ROW0__GPIO4_IO07 | MUX_PAD_CTRL(NO_PAD_CTRL),
+	/* IOEXP_PWREN# */
+	MX6_PAD_EIM_A19__GPIO2_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL),
+	/* IOEXP_IRQ# */
+	MX6_PAD_EIM_A20__GPIO2_IO18 | MUX_PAD_CTRL(NO_PAD_CTRL),
+
+	/* GPS_SHDN */
+	MX6_PAD_GPIO_2__GPIO1_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL),
+	/* VID_PWR */
+	MX6_PAD_CSI0_DATA_EN__GPIO5_IO20 | MUX_PAD_CTRL(NO_PAD_CTRL),
+	/* PCI_RST# */
+	MX6_PAD_GPIO_0__GPIO1_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const gw52xx_gpio_pads[] = {
+	/* PANLEDG# */
+	MX6_PAD_KEY_COL0__GPIO4_IO06 | MUX_PAD_CTRL(NO_PAD_CTRL),
+	/* PANLEDR# */
+	MX6_PAD_KEY_ROW0__GPIO4_IO07 | MUX_PAD_CTRL(NO_PAD_CTRL),
+	/* IOEXP_PWREN# */
+	MX6_PAD_EIM_A19__GPIO2_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL),
+	/* IOEXP_IRQ# */
+	MX6_PAD_EIM_A20__GPIO2_IO18 | MUX_PAD_CTRL(NO_PAD_CTRL),
+
+	/* MX6_LOCLED# */
+	MX6_PAD_KEY_ROW4__GPIO4_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL),
+	/* GPS_SHDN */
+	MX6_PAD_ENET_RXD0__GPIO1_IO27 | MUX_PAD_CTRL(NO_PAD_CTRL),
+	/* USBOTG_SEL */
+	MX6_PAD_GPIO_2__GPIO1_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL),
+	/* VID_PWR */
+	MX6_PAD_EIM_D31__GPIO3_IO31 | MUX_PAD_CTRL(NO_PAD_CTRL),
+	/* PCI_RST# */
+	MX6_PAD_ENET_TXD1__GPIO1_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const gw53xx_gpio_pads[] = {
+	/* PANLEDG# */
+	MX6_PAD_KEY_COL0__GPIO4_IO06 | MUX_PAD_CTRL(NO_PAD_CTRL),
+	/* PANLEDR# */
+	MX6_PAD_KEY_ROW0__GPIO4_IO07 | MUX_PAD_CTRL(NO_PAD_CTRL),
+	/* IOEXP_PWREN# */
+	MX6_PAD_EIM_A19__GPIO2_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL),
+	/* IOEXP_IRQ# */
+	MX6_PAD_EIM_A20__GPIO2_IO18 | MUX_PAD_CTRL(NO_PAD_CTRL),
+
+	/* MX6_LOCLED# */
+	MX6_PAD_KEY_ROW4__GPIO4_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL),
+	/* GPS_SHDN */
+	MX6_PAD_ENET_RXD0__GPIO1_IO27 | MUX_PAD_CTRL(NO_PAD_CTRL),
+	/* VID_EN */
+	MX6_PAD_EIM_D31__GPIO3_IO31 | MUX_PAD_CTRL(NO_PAD_CTRL),
+	/* PCI_RST# */
+	MX6_PAD_ENET_TXD1__GPIO1_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const gw54xx_gpio_pads[] = {
+	/* PANLEDG# */
+	MX6_PAD_KEY_COL0__GPIO4_IO06 | MUX_PAD_CTRL(NO_PAD_CTRL),
+	/* PANLEDR# */
+	MX6_PAD_KEY_COL2__GPIO4_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL),
+	/* MX6_LOCLED# */
+	MX6_PAD_KEY_ROW4__GPIO4_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL),
+	/* MIPI_DIO */
+	MX6_PAD_SD1_DAT3__GPIO1_IO21 | MUX_PAD_CTRL(NO_PAD_CTRL),
+	/* RS485_EN */
+	MX6_PAD_EIM_D24__GPIO3_IO24 | MUX_PAD_CTRL(NO_PAD_CTRL),
+	/* IOEXP_PWREN# */
+	MX6_PAD_KEY_ROW0__GPIO4_IO07 | MUX_PAD_CTRL(NO_PAD_CTRL),
+	/* IOEXP_IRQ# */
+	MX6_PAD_KEY_ROW1__GPIO4_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL),
+	/* DIOI2C_DIS# */
+	MX6_PAD_GPIO_19__GPIO4_IO05 | MUX_PAD_CTRL(NO_PAD_CTRL),
+	/* DIOI2C_DIS# */
+	MX6_PAD_GPIO_19__GPIO4_IO05 | MUX_PAD_CTRL(NO_PAD_CTRL),
+	/* PCICK_SSON */
+	MX6_PAD_SD1_CLK__GPIO1_IO20 | MUX_PAD_CTRL(NO_PAD_CTRL),
+	/* PCI_RST# */
+	MX6_PAD_ENET_TXD1__GPIO1_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+/*
+ * each baseboard has 4 user configurable Digital IO lines which can
+ * be pinmuxed as a GPIO or in some cases a PWM
+ */
+struct dio_cfg {
+	iomux_v3_cfg_t gpio_padmux;
+	unsigned gpio_param;
+	iomux_v3_cfg_t pwm_padmux;
+	unsigned pwm_param;
+};
+
+struct ventana {
+	/* pinmux */
+	iomux_v3_cfg_t const *gpio_pads;
+	int num_pads;
+	/* DIO pinmux/val */
+	struct dio_cfg dio_cfg[4];
+	/* various gpios (0 if non-existent) */
+	int leds[3];
+	int pcie_rst;
+	int mezz_pwren;
+	int mezz_irq;
+	int rs485en;
+	int gps_shdn;
+	int vidin_en;
+	int dioi2c_en;
+	int pcie_sson;
+	int usb_sel;
+};
+
+struct ventana gpio_cfg[] = {
+	/* GW5400proto */
+	{
+		.gpio_pads = gw54xx_gpio_pads,
+		.num_pads = ARRAY_SIZE(gw54xx_gpio_pads),
+		.dio_cfg = {
+			{ MX6_PAD_GPIO_9__GPIO1_IO09, IMX_GPIO_NR(1, 9),
+			  MX6_PAD_GPIO_9__PWM1_OUT, 1 },
+			{ MX6_PAD_SD1_DAT2__GPIO1_IO19, IMX_GPIO_NR(1, 19),
+			  MX6_PAD_SD1_DAT2__PWM2_OUT, 2 },
+			{ MX6_PAD_SD4_DAT1__GPIO2_IO09, IMX_GPIO_NR(2, 9),
+			  MX6_PAD_SD4_DAT1__PWM3_OUT, 3 },
+			{ MX6_PAD_SD4_DAT2__GPIO2_IO10, IMX_GPIO_NR(2, 10),
+			  MX6_PAD_SD4_DAT2__PWM4_OUT, 4 },
+		},
+		.leds = {
+			IMX_GPIO_NR(4, 6),
+			IMX_GPIO_NR(4, 10),
+			IMX_GPIO_NR(4, 15),
+		},
+		.pcie_rst = IMX_GPIO_NR(1, 29),
+		.mezz_pwren = IMX_GPIO_NR(4, 7),
+		.mezz_irq = IMX_GPIO_NR(4, 9),
+		.rs485en = IMX_GPIO_NR(3, 24),
+		.dioi2c_en = IMX_GPIO_NR(4,  5),
+		.pcie_sson = IMX_GPIO_NR(1, 20),
+	},
+
+	/* GW51xx */
+	{
+		.gpio_pads = gw51xx_gpio_pads,
+		.num_pads = ARRAY_SIZE(gw51xx_gpio_pads),
+		.dio_cfg = {
+			{ MX6_PAD_SD1_DAT0__GPIO1_IO16, IMX_GPIO_NR(1, 16),
+			  0, 0 },
+			{ MX6_PAD_SD1_DAT2__GPIO1_IO19, IMX_GPIO_NR(1, 19),
+			  MX6_PAD_SD1_DAT2__PWM2_OUT, 2 },
+			{ MX6_PAD_SD1_DAT1__GPIO1_IO17, IMX_GPIO_NR(1, 17),
+			  MX6_PAD_SD1_DAT1__PWM3_OUT, 3 },
+			{ MX6_PAD_SD1_CMD__GPIO1_IO18, IMX_GPIO_NR(1, 18),
+			  MX6_PAD_SD1_CMD__PWM4_OUT, 4 },
+		},
+		.leds = {
+			IMX_GPIO_NR(4, 6),
+			IMX_GPIO_NR(4, 10),
+		},
+		.pcie_rst = IMX_GPIO_NR(1, 0),
+		.mezz_pwren = IMX_GPIO_NR(2, 19),
+		.mezz_irq = IMX_GPIO_NR(2, 18),
+		.gps_shdn = IMX_GPIO_NR(1, 2),
+		.vidin_en = IMX_GPIO_NR(5, 20),
+	},
+
+	/* GW52xx */
+	{
+		.gpio_pads = gw52xx_gpio_pads,
+		.num_pads = ARRAY_SIZE(gw52xx_gpio_pads),
+		.dio_cfg = {
+			{ MX6_PAD_SD1_DAT0__GPIO1_IO16, IMX_GPIO_NR(1, 16),
+			  0, 0 },
+			{ MX6_PAD_SD1_DAT2__GPIO1_IO19, IMX_GPIO_NR(1, 19),
+			  MX6_PAD_SD1_DAT2__PWM2_OUT, 2 },
+			{ MX6_PAD_SD1_DAT1__GPIO1_IO17, IMX_GPIO_NR(1, 17),
+			  MX6_PAD_SD1_DAT1__PWM3_OUT, 3 },
+			{ MX6_PAD_SD1_CLK__GPIO1_IO20, IMX_GPIO_NR(1, 20),
+			  0, 0 },
+		},
+		.leds = {
+			IMX_GPIO_NR(4, 6),
+			IMX_GPIO_NR(4, 7),
+			IMX_GPIO_NR(4, 15),
+		},
+		.pcie_rst = IMX_GPIO_NR(1, 29),
+		.mezz_pwren = IMX_GPIO_NR(2, 19),
+		.mezz_irq = IMX_GPIO_NR(2, 18),
+		.gps_shdn = IMX_GPIO_NR(1, 27),
+		.vidin_en = IMX_GPIO_NR(3, 31),
+		.usb_sel = IMX_GPIO_NR(1, 2),
+	},
+
+	/* GW53xx */
+	{
+		.gpio_pads = gw53xx_gpio_pads,
+		.num_pads = ARRAY_SIZE(gw53xx_gpio_pads),
+		.dio_cfg = {
+			{ MX6_PAD_SD1_DAT0__GPIO1_IO16, IMX_GPIO_NR(1, 16),
+			  0, 0 },
+			{ MX6_PAD_SD1_DAT2__GPIO1_IO19, IMX_GPIO_NR(1, 19),
+			  MX6_PAD_SD1_DAT2__PWM2_OUT, 2 },
+			{ MX6_PAD_SD1_DAT1__GPIO1_IO17, IMX_GPIO_NR(1, 17),
+			  MX6_PAD_SD1_DAT1__PWM3_OUT, 3 },
+			{ MX6_PAD_SD1_CLK__GPIO1_IO20, IMX_GPIO_NR(1, 20),
+			  0, 0 },
+		},
+		.leds = {
+			IMX_GPIO_NR(4, 6),
+			IMX_GPIO_NR(4, 7),
+			IMX_GPIO_NR(4, 15),
+		},
+		.pcie_rst = IMX_GPIO_NR(1, 29),
+		.mezz_pwren = IMX_GPIO_NR(2, 19),
+		.mezz_irq = IMX_GPIO_NR(2, 18),
+		.gps_shdn = IMX_GPIO_NR(1, 27),
+		.vidin_en = IMX_GPIO_NR(3, 31),
+	},
+
+	/* GW54xx */
+	{
+		.gpio_pads = gw54xx_gpio_pads,
+		.num_pads = ARRAY_SIZE(gw54xx_gpio_pads),
+		.dio_cfg = {
+			{ MX6_PAD_GPIO_9__GPIO1_IO09, IMX_GPIO_NR(1, 9),
+			  MX6_PAD_GPIO_9__PWM1_OUT, 1 },
+			{ MX6_PAD_SD1_DAT2__GPIO1_IO19, IMX_GPIO_NR(1, 19),
+			  MX6_PAD_SD1_DAT2__PWM2_OUT, 2 },
+			{ MX6_PAD_SD4_DAT1__GPIO2_IO09, IMX_GPIO_NR(2, 9),
+			  MX6_PAD_SD4_DAT1__PWM3_OUT, 3 },
+			{ MX6_PAD_SD4_DAT2__GPIO2_IO10, IMX_GPIO_NR(2, 10),
+			  MX6_PAD_SD4_DAT2__PWM4_OUT, 4 },
+		},
+		.leds = {
+			IMX_GPIO_NR(4, 6),
+			IMX_GPIO_NR(4, 7),
+			IMX_GPIO_NR(4, 15),
+		},
+		.pcie_rst = IMX_GPIO_NR(1, 29),
+		.mezz_pwren = IMX_GPIO_NR(2, 19),
+		.mezz_irq = IMX_GPIO_NR(2, 18),
+		.rs485en = IMX_GPIO_NR(7, 1),
+		.vidin_en = IMX_GPIO_NR(3, 31),
+		.dioi2c_en = IMX_GPIO_NR(4,  5),
+		.pcie_sson = IMX_GPIO_NR(1, 20),
+	},
+};
+
+/* setup GPIO pinmux and default configuration per baseboard */
+static void setup_board_gpio(int board)
+{
+	struct ventana_board_info *info = &ventana_info;
+	const char *s;
+	char arg[10];
+	size_t len;
+	int i;
+	int quiet = simple_strtol(getenv("quiet"), NULL, 10);
+
+	if (board >= GW_UNKNOWN)
+		return;
+
+	/* RS232_EN# */
+	gpio_direction_output(GP_RS232_EN, (hwconfig("rs232")) ? 0 : 1);
+
+	/* MSATA Enable */
+	if (is_cpu_type(MXC_CPU_MX6Q) &&
+	    test_bit(EECONFIG_SATA, info->config)) {
+		gpio_direction_output(GP_MSATA_SEL,
+				      (hwconfig("msata")) ?  1 : 0);
+	} else {
+		gpio_direction_output(GP_MSATA_SEL, 0);
+	}
+
+	/*
+	 * assert PCI_RST# (released by OS when clock is valid)
+	 * TODO: figure out why leaving this de-asserted from PCI scan on boot
+	 *       causes linux pcie driver to hang during enumeration
+	 */
+	gpio_direction_output(gpio_cfg[board].pcie_rst, 0);
+
+	/* turn off (active-high) user LED's */
+	for (i = 0; i < 4; i++) {
+		if (gpio_cfg[board].leds[i])
+			gpio_direction_output(gpio_cfg[board].leds[i], 1);
+	}
+
+	/* Expansion Mezzanine IO */
+	gpio_direction_output(gpio_cfg[board].mezz_pwren, 0);
+	gpio_direction_input(gpio_cfg[board].mezz_irq);
+
+	/* RS485 Transmit Enable */
+	if (gpio_cfg[board].rs485en)
+		gpio_direction_output(gpio_cfg[board].rs485en, 0);
+
+	/* GPS_SHDN */
+	if (gpio_cfg[board].gps_shdn)
+		gpio_direction_output(gpio_cfg[board].gps_shdn, 1);
+
+	/* Analog video codec power enable */
+	if (gpio_cfg[board].vidin_en)
+		gpio_direction_output(gpio_cfg[board].vidin_en, 1);
+
+	/* DIOI2C_DIS# */
+	if (gpio_cfg[board].dioi2c_en)
+		gpio_direction_output(gpio_cfg[board].dioi2c_en, 0);
+
+	/* PCICK_SSON: disable spread-spectrum clock */
+	if (gpio_cfg[board].pcie_sson)
+		gpio_direction_output(gpio_cfg[board].pcie_sson, 0);
+
+	/* USBOTG Select (PCISKT or FrontPanel) */
+	if (gpio_cfg[board].usb_sel)
+		gpio_direction_output(gpio_cfg[board].usb_sel, 0);
+
+	/*
+	 * Configure DIO pinmux/padctl registers
+	 * see IMX6DQRM/IMX6SDLRM IOMUXC_SW_PAD_CTL_PAD_* register definitions
+	 */
+	for (i = 0; i < 4; i++) {
+		struct dio_cfg *cfg = &gpio_cfg[board].dio_cfg[i];
+		unsigned ctrl = DIO_PAD_CTRL;
+
+		sprintf(arg, "dio%d", i);
+		if (!hwconfig(arg))
+			continue;
+		s = hwconfig_subarg(arg, "padctrl", &len);
+		if (s)
+			ctrl = simple_strtoul(s, NULL, 16) & 0x3ffff;
+		if (hwconfig_subarg_cmp(arg, "mode", "gpio")) {
+			if (!quiet) {
+				printf("DIO%d:  GPIO%d_IO%02d (gpio-%d)\n", i,
+				       (cfg->gpio_param/32)+1,
+				       cfg->gpio_param%32,
+				       cfg->gpio_param);
+			}
+			imx_iomux_v3_setup_pad(cfg->gpio_padmux |
+					       MUX_PAD_CTRL(ctrl));
+			gpio_direction_input(cfg->gpio_param);
+		} else if (hwconfig_subarg_cmp("dio2", "mode", "pwm") &&
+			   cfg->pwm_padmux) {
+			if (!quiet)
+				printf("DIO%d:  pwm%d\n", i, cfg->pwm_param);
+			imx_iomux_v3_setup_pad(cfg->pwm_padmux |
+					       MUX_PAD_CTRL(ctrl));
+		}
+	}
+
+	if (!quiet) {
+		if (is_cpu_type(MXC_CPU_MX6Q) &&
+		    (test_bit(EECONFIG_SATA, info->config))) {
+			printf("MSATA: %s\n", (hwconfig("msata") ?
+			       "enabled" : "disabled"));
+		}
+		printf("RS232: %s\n", (hwconfig("rs232")) ?
+		       "enabled" : "disabled");
+	}
+}
+
+#if defined(CONFIG_CMD_PCI)
+int imx6_pcie_toggle_reset(void)
+{
+	if (board_type < GW_UNKNOWN) {
+		gpio_direction_output(gpio_cfg[board_type].pcie_rst, 0);
+		mdelay(50);
+		gpio_direction_output(gpio_cfg[board_type].pcie_rst, 1);
+	}
+	return 0;
+}
+#endif /* CONFIG_CMD_PCI */
+
+#ifdef CONFIG_SERIAL_TAG
+/*
+ * called when setting up ATAGS before booting kernel
+ * populate serialnum from the following (in order of priority):
+ *   serial# env var
+ *   eeprom
+ */
+void get_board_serial(struct tag_serialnr *serialnr)
+{
+	char *serial = getenv("serial#");
+
+	if (serial) {
+		serialnr->high = 0;
+		serialnr->low = simple_strtoul(serial, NULL, 10);
+	} else if (ventana_info.model[0]) {
+		serialnr->high = 0;
+		serialnr->low = ventana_info.serial;
+	} else {
+		serialnr->high = 0;
+		serialnr->low = 0;
+	}
+}
+#endif
+
+/*
+ * Board Support
+ */
+
+int board_early_init_f(void)
+{
+	setup_iomux_uart();
+	gpio_direction_output(GP_USB_OTG_PWR, 0); /* OTG power off */
+
+	return 0;
+}
+
+int dram_init(void)
+{
+	gd->ram_size = get_ram_size((void *)PHYS_SDRAM,
+				    CONFIG_DDR_MB*1024*1024);
+
+	return 0;
+}
+
+int board_init(void)
+{
+	struct iomuxc_base_regs *const iomuxc_regs
+		= (struct iomuxc_base_regs *)IOMUXC_BASE_ADDR;
+
+	clrsetbits_le32(&iomuxc_regs->gpr[1],
+			IOMUXC_GPR1_OTG_ID_MASK,
+			IOMUXC_GPR1_OTG_ID_GPIO1);
+
+	/* address of linux boot parameters */
+	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+
+#ifdef CONFIG_CMD_NAND
+	setup_gpmi_nand();
+#endif
+#ifdef CONFIG_MXC_SPI
+	setup_spi();
+#endif
+	setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info0);
+	setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
+	setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
+
+#ifdef CONFIG_CMD_SATA
+	setup_sata();
+#endif
+	/* read Gateworks EEPROM into global struct (used later) */
+	board_type = read_eeprom();
+
+	/* board-specifc GPIO iomux */
+	if (board_type < GW_UNKNOWN) {
+		imx_iomux_v3_setup_multiple_pads(gw_gpio_pads,
+						 ARRAY_SIZE(gw_gpio_pads));
+		imx_iomux_v3_setup_multiple_pads(gpio_cfg[board_type].gpio_pads,
+						 gpio_cfg[board_type].num_pads);
+	}
+
+	return 0;
+}
+
+#if defined(CONFIG_DISPLAY_BOARDINFO_LATE)
+/*
+ * called during late init (after relocation and after board_init())
+ * by virtue of CONFIG_DISPLAY_BOARDINFO_LATE as we needed i2c initialized and
+ * EEPROM read.
+ */
+int checkboard(void)
+{
+	struct ventana_board_info *info = &ventana_info;
+	unsigned char buf[4];
+	const char *p;
+	int quiet; /* Quiet or minimal output mode */
+
+	quiet = 0;
+	p = getenv("quiet");
+	if (p)
+		quiet = simple_strtol(p, NULL, 10);
+	else
+		setenv("quiet", "0");
+
+	puts("\nGateworks Corporation Copyright 2014\n");
+	if (info->model[0]) {
+		printf("Model: %s\n", info->model);
+		printf("MFGDate: %02x-%02x-%02x%02x\n",
+		       info->mfgdate[0], info->mfgdate[1],
+		       info->mfgdate[2], info->mfgdate[3]);
+		printf("Serial:%d\n", info->serial);
+	} else {
+		puts("Invalid EEPROM - board will not function fully\n");
+	}
+	if (quiet)
+		return 0;
+
+	/* Display GSC firmware revision/CRC/status */
+	i2c_set_bus_num(I2C_GSC);
+	if (!gsc_i2c_read(GSC_SC_ADDR, GSC_SC_FWVER, 1, buf, 1)) {
+		printf("GSC:   v%d", buf[0]);
+		if (!gsc_i2c_read(GSC_SC_ADDR, GSC_SC_STATUS, 1, buf, 4)) {
+			printf(" 0x%04x", buf[2] | buf[3]<<8); /* CRC */
+			printf(" 0x%02x", buf[0]); /* irq status */
+		}
+		puts("\n");
+	}
+	/* Display RTC */
+	if (!gsc_i2c_read(GSC_RTC_ADDR, 0x00, 1, buf, 4)) {
+		printf("RTC:   %d\n",
+		       buf[0] | buf[1]<<8 | buf[2]<<16 | buf[3]<<24);
+	}
+
+	return 0;
+}
+#endif
+
+#ifdef CONFIG_CMD_BMODE
+/*
+ * BOOT_CFG1, BOOT_CFG2, BOOT_CFG3, BOOT_CFG4
+ * see Table 8-11 and Table 5-9
+ *  BOOT_CFG1[7] = 1 (boot from NAND)
+ *  BOOT_CFG1[5] = 0 - raw NAND
+ *  BOOT_CFG1[4] = 0 - default pad settings
+ *  BOOT_CFG1[3:2] = 00 - devices = 1
+ *  BOOT_CFG1[1:0] = 00 - Row Address Cycles = 3
+ *  BOOT_CFG2[4:3] = 00 - Boot Search Count = 2
+ *  BOOT_CFG2[2:1] = 01 - Pages In Block = 64
+ *  BOOT_CFG2[0] = 0 - Reset time 12ms
+ */
+static const struct boot_mode board_boot_modes[] = {
+	/* NAND: 64pages per block, 3 row addr cycles, 2 copies of FCB/DBBT */
+	{ "nand", MAKE_CFGVAL(0x80, 0x02, 0x00, 0x00) },
+	{ NULL, 0 },
+};
+#endif
+
+/* late init */
+int misc_init_r(void)
+{
+	struct ventana_board_info *info = &ventana_info;
+	unsigned char reg;
+
+	/* set env vars based on EEPROM data */
+	if (ventana_info.model[0]) {
+		char str[16], fdt[36];
+		char *p;
+		const char *cputype = "";
+		int i;
+
+		/*
+		 * FDT name will be prefixed with CPU type.  Three versions
+		 * will be created each increasingly generic and bootloader
+		 * env scripts will try loading each from most specific to
+		 * least.
+		 */
+		if (is_cpu_type(MXC_CPU_MX6Q))
+			cputype = "imx6q";
+		else if (is_cpu_type(MXC_CPU_MX6DL))
+			cputype = "imx6dl";
+		memset(str, 0, sizeof(str));
+		for (i = 0; i < (sizeof(str)-1) && info->model[i]; i++)
+			str[i] = tolower(info->model[i]);
+		if (!getenv("model"))
+			setenv("model", str);
+		if (!getenv("fdt_file")) {
+			sprintf(fdt, "%s-%s.dtb", cputype, str);
+			setenv("fdt_file", fdt);
+		}
+		p = strchr(str, '-');
+		if (p) {
+			*p++ = 0;
+
+			setenv("model_base", str);
+			if (!getenv("fdt_file1")) {
+				sprintf(fdt, "%s-%s.dtb", cputype, str);
+				setenv("fdt_file1", fdt);
+			}
+			str[4] = 'x';
+			str[5] = 'x';
+			str[6] = 0;
+			if (!getenv("fdt_file2")) {
+				sprintf(fdt, "%s-%s.dtb", cputype, str);
+				setenv("fdt_file2", fdt);
+			}
+		}
+
+		/* initialize env from EEPROM */
+		if (test_bit(EECONFIG_ETH0, info->config) &&
+		    !getenv("ethaddr")) {
+			eth_setenv_enetaddr("ethaddr", info->mac0);
+		}
+		if (test_bit(EECONFIG_ETH1, info->config) &&
+		    !getenv("eth1addr")) {
+			eth_setenv_enetaddr("eth1addr", info->mac1);
+		}
+
+		/* board serial-number */
+		sprintf(str, "%6d", info->serial);
+		setenv("serial#", str);
+	}
+
+	/* configure PFUZE100 PMIC (not used on all Ventana baseboards) */
+	if ((board_type == GW54xx || board_type == GW54proto) &&
+	    !pmic_init(I2C_PMIC)) {
+		struct pmic *p = pmic_get("PFUZE100_PMIC");
+		u32 reg;
+		if (p && !pmic_probe(p)) {
+			pmic_reg_read(p, PFUZE100_DEVICEID, &reg);
+			printf("PMIC:  PFUZE100 ID=0x%02x\n", reg);
+
+			/* Set VGEN1 to 1.5V and enable */
+			pmic_reg_read(p, PFUZE100_VGEN1VOL, &reg);
+			reg &= ~(LDO_VOL_MASK);
+			reg |= (LDOA_1_50V | LDO_EN);
+			pmic_reg_write(p, PFUZE100_VGEN1VOL, reg);
+
+			/* Set SWBST to 5.0V and enable */
+			pmic_reg_read(p, PFUZE100_SWBSTCON1, &reg);
+			reg &= ~(SWBST_MODE_MASK | SWBST_VOL_MASK);
+			reg |= (SWBST_5_00V | SWBST_MODE_AUTO);
+			pmic_reg_write(p, PFUZE100_SWBSTCON1, reg);
+		}
+	}
+
+	/* setup baseboard specific GPIO pinmux and config */
+	setup_board_gpio(board_type);
+
+#ifdef CONFIG_CMD_BMODE
+	add_board_boot_modes(board_boot_modes);
+#endif
+
+	/*
+	 *  The Gateworks System Controller implements a boot
+	 *  watchdog (always enabled) as a workaround for IMX6 boot related
+	 *  errata such as:
+	 *    ERR005768 - no fix
+	 *    ERR006282 - fixed in silicon r1.3
+	 *    ERR007117 - fixed in silicon r1.3
+	 *    ERR007220 - fixed in silicon r1.3
+	 *  see http://cache.freescale.com/files/32bit/doc/errata/IMX6DQCE.pdf
+	 *
+	 * Disable the boot watchdog and display/clear the timeout flag if set
+	 */
+	i2c_set_bus_num(I2C_GSC);
+	if (!gsc_i2c_read(GSC_SC_ADDR, GSC_SC_CTRL1, 1, &reg, 1)) {
+		reg |= (1 << GSC_SC_CTRL1_WDDIS);
+		if (gsc_i2c_write(GSC_SC_ADDR, GSC_SC_CTRL1, 1, &reg, 1))
+			puts("Error: could not disable GSC Watchdog\n");
+	} else {
+		puts("Error: could not disable GSC Watchdog\n");
+	}
+	if (!gsc_i2c_read(GSC_SC_ADDR, GSC_SC_STATUS, 1, &reg, 1)) {
+		if (reg & (1 << GSC_SC_IRQ_WATCHDOG)) { /* watchdog timeout */
+			puts("GSC boot watchdog timeout detected");
+			reg &= ~(1 << GSC_SC_IRQ_WATCHDOG); /* clear flag */
+			gsc_i2c_write(GSC_SC_ADDR, GSC_SC_STATUS, 1, &reg, 1);
+		}
+	}
+
+	return 0;
+}
+
+#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
+
+/* FDT aliases associated with EEPROM config bits */
+const char *fdt_aliases[] = {
+	"ethernet0",
+	"ethernet1",
+	"hdmi_out",
+	"ahci0",
+	"pcie",
+	"ssi0",
+	"ssi1",
+	"lcd0",
+	"lvds0",
+	"lvds1",
+	"usb0",
+	"usb1",
+	"mmc0",
+	"mmc1",
+	"mmc2",
+	"mmc3",
+	"uart0",
+	"uart1",
+	"uart2",
+	"uart3",
+	"uart4",
+	"ipu0",
+	"ipu1",
+	"can0",
+	"mipi_dsi",
+	"mipi_csi",
+	"tzasc0",
+	"tzasc1",
+	"i2c0",
+	"i2c1",
+	"i2c2",
+	"vpu",
+	"csi0",
+	"csi1",
+	"caam",
+	NULL,
+	NULL,
+	NULL,
+	NULL,
+	NULL,
+	"spi0",
+	"spi1",
+	"spi2",
+	"spi3",
+	"spi4",
+	"spi5",
+	NULL,
+	NULL,
+	"pps",
+	NULL,
+	NULL,
+	NULL,
+	"hdmi_in",
+	"cvbs_out",
+	"cvbs_in",
+	"nand",
+	NULL,
+	NULL,
+	NULL,
+	NULL,
+	NULL,
+	NULL,
+	NULL,
+	NULL,
+};
+
+/*
+ * called prior to booting kernel or by 'fdt boardsetup' command
+ *
+ * unless 'fdt_noauto' env var is set we will update the following in the DTB:
+ *  - mtd partitions based on mtdparts/mtdids env
+ *  - system-serial (board serial num from EEPROM)
+ *  - board (full model from EEPROM)
+ *  - peripherals removed from DTB if not loaded on board (per EEPROM config)
+ */
+void ft_board_setup(void *blob, bd_t *bd)
+{
+	int bit;
+	struct ventana_board_info *info = &ventana_info;
+	struct node_info nodes[] = {
+		{ "sst,w25q256",          MTD_DEV_TYPE_NOR, },  /* SPI flash */
+		{ "fsl,imx6q-gpmi-nand",  MTD_DEV_TYPE_NAND, }, /* NAND flash */
+	};
+	const char *model = getenv("model");
+
+	if (getenv("fdt_noauto")) {
+		puts("   Skiping ft_board_setup (fdt_noauto defined)\n");
+		return;
+	}
+
+	/* Update partition nodes using info from mtdparts env var */
+	puts("   Updating MTD partitions...\n");
+	fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
+
+	if (!model) {
+		puts("invalid board info: Leaving FDT fully enabled\n");
+		return;
+	}
+	printf("   Adjusting FDT per EEPROM for %s...\n", model);
+
+	/* board serial number */
+	fdt_setprop(blob, 0, "system-serial", getenv("serial#"),
+		    strlen(getenv("serial#") + 1));
+
+	/* board (model contains model from device-tree) */
+	fdt_setprop(blob, 0, "board", info->model,
+		    strlen((const char *)info->model) + 1);
+
+	/*
+	 * Peripheral Config:
+	 *  remove nodes by alias path if EEPROM config tells us the
+	 *  peripheral is not loaded on the board.
+	 */
+	for (bit = 0; bit < 64; bit++) {
+		if (!test_bit(bit, info->config))
+			fdt_del_node_and_alias(blob, fdt_aliases[bit]);
+	}
+}
+#endif /* defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP) */
+
diff --git a/board/gateworks/gw_ventana/gw_ventana.cfg b/board/gateworks/gw_ventana/gw_ventana.cfg
new file mode 100644
index 0000000000..27f09745c1
--- /dev/null
+++ b/board/gateworks/gw_ventana/gw_ventana.cfg
@@ -0,0 +1,44 @@
+/*
+ * Copyright (C) 2013 Gateworks Corporation
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ * Refer doc/README.imximage for more details about how-to configure
+ * and create imximage boot image
+ *
+ * The syntax is taken as close as possible with the kwbimage
+ */
+
+/* image version */
+IMAGE_VERSION 2
+
+/*
+ * Boot Device : one of
+ * spi, sd, nand, sata
+ */
+#ifdef CONFIG_SPI_FLASH
+BOOT_FROM      spi
+#else
+BOOT_FROM      nand
+#endif
+
+#define __ASSEMBLY__
+#include <config.h>
+#include "asm/arch/mx6-ddr.h"
+#include "asm/arch/iomux.h"
+#include "asm/arch/crm_regs.h"
+
+/* Memory configuration (size is overridden via eeprom config) */
+#include "../../boundary/nitrogen6x/ddr-setup.cfg"
+#if defined(CONFIG_MX6Q) && CONFIG_DDR_MB == 1024
+  #include "../../boundary/nitrogen6x/1066mhz_4x128mx16.cfg"
+#elif defined(CONFIG_MX6DL) && CONFIG_DDR_MB == 1024
+  #include "../../boundary/nitrogen6x/800mhz_4x128mx16.cfg"
+#elif defined(CONFIG_MX6DL) && CONFIG_DDR_MB == 512
+  #include "../../boundary/nitrogen6x/800mhz_2x128mx16.cfg"
+#elif defined(CONFIG_MX6Q) && CONFIG_DDR_MB == 512
+  #include "../../boundary/nitrogen6x/800mhz_2x128mx16.cfg"
+#else
+  #error "Unsupported CPU/Memory configuration"
+#endif
+#include "clocks.cfg"
diff --git a/board/gateworks/gw_ventana/ventana_eeprom.h b/board/gateworks/gw_ventana/ventana_eeprom.h
new file mode 100644
index 0000000000..d310bfd994
--- /dev/null
+++ b/board/gateworks/gw_ventana/ventana_eeprom.h
@@ -0,0 +1,106 @@
+/*
+ * Copyright (C) 2013 Gateworks Corporation
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _VENTANA_EEPROM_
+#define _VENTANA_EEPROM_
+
+struct ventana_board_info {
+	u8 mac0[6];          /* 0x00: MAC1 */
+	u8 mac1[6];          /* 0x06: MAC2 */
+	u8 res0[12];         /* 0x0C: reserved */
+	u32 serial;          /* 0x18: Serial Number (read only) */
+	u8 res1[4];          /* 0x1C: reserved */
+	u8 mfgdate[4];       /* 0x20: MFG date (read only) */
+	u8 res2[7];          /* 0x24 */
+	/* sdram config */
+	u8 sdram_size;       /* 0x2B: enum (512,1024,2048) MB */
+	u8 sdram_speed;      /* 0x2C: enum (100,133,166,200,267,333,400) MHz */
+	u8 sdram_width;      /* 0x2D: enum (32,64) bit */
+	/* cpu config */
+	u8 cpu_speed;        /* 0x2E: enum (800,1000,1200) MHz */
+	u8 cpu_type;         /* 0x2F: enum (imx6q,imx6d,imx6dl,imx6s) */
+	u8 model[16];        /* 0x30: model string */
+	/* FLASH config */
+	u8 nand_flash_size;  /* 0x40: enum (4,8,16,32,64,128) MB */
+	u8 spi_flash_size;   /* 0x41: enum (4,8,16,32,64,128) MB */
+
+	/* Config1: SoC Peripherals */
+	u8 config[8];        /* 0x42: loading options */
+
+	u8 res3[4];          /* 0x4A */
+
+	u8 chksum[2];        /* 0x4E */
+};
+
+/* config bits */
+enum {
+	EECONFIG_ETH0,
+	EECONFIG_ETH1,
+	EECONFIG_HDMI_OUT,
+	EECONFIG_SATA,
+	EECONFIG_PCIE,
+	EECONFIG_SSI0,
+	EECONFIG_SSI1,
+	EECONFIG_LCD,
+	EECONFIG_LVDS0,
+	EECONFIG_LVDS1,
+	EECONFIG_USB0,
+	EECONFIG_USB1,
+	EECONFIG_SD0,
+	EECONFIG_SD1,
+	EECONFIG_SD2,
+	EECONFIG_SD3,
+	EECONFIG_UART0,
+	EECONFIG_UART1,
+	EECONFIG_UART2,
+	EECONFIG_UART3,
+	EECONFIG_UART4,
+	EECONFIG_IPU0,
+	EECONFIG_IPU1,
+	EECONFIG_FLEXCAN,
+	EECONFIG_MIPI_DSI,
+	EECONFIG_MIPI_CSI,
+	EECONFIG_TZASC0,
+	EECONFIG_TZASC1,
+	EECONFIG_I2C0,
+	EECONFIG_I2C1,
+	EECONFIG_I2C2,
+	EECONFIG_VPU,
+	EECONFIG_CSI0,
+	EECONFIG_CSI1,
+	EECONFIG_CAAM,
+	EECONFIG_MEZZ,
+	EECONFIG_RES1,
+	EECONFIG_RES2,
+	EECONFIG_RES3,
+	EECONFIG_RES4,
+	EECONFIG_ESPCI0,
+	EECONFIG_ESPCI1,
+	EECONFIG_ESPCI2,
+	EECONFIG_ESPCI3,
+	EECONFIG_ESPCI4,
+	EECONFIG_ESPCI5,
+	EECONFIG_RES5,
+	EECONFIG_RES6,
+	EECONFIG_GPS,
+	EECONFIG_SPIFL0,
+	EECONFIG_SPIFL1,
+	EECONFIG_GSPBATT,
+	EECONFIG_HDMI_IN,
+	EECONFIG_VID_OUT,
+	EECONFIG_VID_IN,
+	EECONFIG_NAND,
+	EECONFIG_RES8,
+	EECONFIG_RES9,
+	EECONFIG_RES10,
+	EECONFIG_RES11,
+	EECONFIG_RES12,
+	EECONFIG_RES13,
+	EECONFIG_RES14,
+	EECONFIG_RES15,
+};
+
+#endif
diff --git a/board/gdsys/405ep/Makefile b/board/gdsys/405ep/Makefile
index 81d23c58b6..857ec04fa8 100644
--- a/board/gdsys/405ep/Makefile
+++ b/board/gdsys/405ep/Makefile
@@ -5,30 +5,8 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS-$(CONFIG_NEO) += neo.o
-COBJS-$(CONFIG_IO) += io.o
-COBJS-$(CONFIG_IOCON) += iocon.o
-COBJS-$(CONFIG_DLVISION_10G) += dlvision-10g.o
-
-COBJS   := $(BOARD).o $(COBJS-y)
-SOBJS   =
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(OBJS) $(SOBJS)
-	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y := 405ep.o
+obj-$(CONFIG_NEO) += neo.o
+obj-$(CONFIG_IO) += io.o
+obj-$(CONFIG_IOCON) += iocon.o
+obj-$(CONFIG_DLVISION_10G) += dlvision-10g.o
diff --git a/board/gdsys/405ex/Makefile b/board/gdsys/405ex/Makefile
index 9846823e28..a668460119 100644
--- a/board/gdsys/405ex/Makefile
+++ b/board/gdsys/405ex/Makefile
@@ -5,33 +5,6 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS-$(CONFIG_IO64) += io64.o
-
-COBJS-$(CONFIG_CMD_CHIP_CONFIG) += chip_config.o
-
-COBJS   := $(BOARD).o $(COBJS-y)
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS))
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-clean:
-	rm -f $(OBJS)
-
-distclean:	clean
-	rm -f $(LIB) core *.bak $(obj).depend
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y := 405ex.o
+obj-$(CONFIG_IO64) += io64.o
+obj-$(CONFIG_CMD_CHIP_CONFIG) += chip_config.o
diff --git a/board/gdsys/common/Makefile b/board/gdsys/common/Makefile
index 216ad964af..fb841e0b8f 100644
--- a/board/gdsys/common/Makefile
+++ b/board/gdsys/common/Makefile
@@ -5,37 +5,9 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-ifneq ($(OBJTREE),$(SRCTREE))
-$(shell mkdir -p $(obj)board/$(VENDOR)/common)
-endif
-
-LIB	= $(obj)lib$(VENDOR).o
-
-COBJS-$(CONFIG_SYS_FPGA_COMMON) += fpga.o
-
-COBJS-$(CONFIG_IO) += miiphybb.o
-COBJS-$(CONFIG_IO64) += miiphybb.o
-COBJS-$(CONFIG_IOCON) += osd.o mclink.o
-COBJS-$(CONFIG_DLVISION_10G) += osd.o
-COBJS-$(CONFIG_CONTROLCENTERD) += dp501.o
-
-COBJS   := $(COBJS-y)
-SOBJS   =
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(OBJS) $(SOBJS)
-	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-$(CONFIG_SYS_FPGA_COMMON) += fpga.o
+obj-$(CONFIG_IO) += miiphybb.o
+obj-$(CONFIG_IO64) += miiphybb.o
+obj-$(CONFIG_IOCON) += osd.o mclink.o
+obj-$(CONFIG_DLVISION_10G) += osd.o
+obj-$(CONFIG_CONTROLCENTERD) += dp501.o
diff --git a/board/gdsys/dlvision/Makefile b/board/gdsys/dlvision/Makefile
index 126365ba66..755eb4cef9 100644
--- a/board/gdsys/dlvision/Makefile
+++ b/board/gdsys/dlvision/Makefile
@@ -5,25 +5,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	= $(BOARD).o
-SOBJS   =
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(OBJS) $(SOBJS)
-	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	= dlvision.o
diff --git a/board/gdsys/gdppc440etx/Makefile b/board/gdsys/gdppc440etx/Makefile
index 1d80df8b74..7e3fc384d4 100644
--- a/board/gdsys/gdppc440etx/Makefile
+++ b/board/gdsys/gdppc440etx/Makefile
@@ -5,25 +5,5 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	= $(BOARD).o
-SOBJS	= init.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(OBJS) $(SOBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	= gdppc440etx.o
+extra-y	+= init.o
diff --git a/board/gdsys/intip/Makefile b/board/gdsys/intip/Makefile
index 415ec3298f..2fbc983e3e 100644
--- a/board/gdsys/intip/Makefile
+++ b/board/gdsys/intip/Makefile
@@ -5,29 +5,6 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS-y	:= $(BOARD).o
-COBJS-$(CONFIG_CMD_CHIP_CONFIG) += chip_config.o
-SOBJS	:= init.o
-
-COBJS   := $(COBJS-y)
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-all:	$(LIB) $(SOBJS)
-
-$(LIB):	$(OBJS)
-	$(call cmd_link_o_target, $^)
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	:= intip.o
+obj-$(CONFIG_CMD_CHIP_CONFIG) += chip_config.o
+extra-y	+= init.o
diff --git a/board/gdsys/p1022/Makefile b/board/gdsys/p1022/Makefile
index 17f602f7ef..6e02447987 100644
--- a/board/gdsys/p1022/Makefile
+++ b/board/gdsys/p1022/Makefile
@@ -7,31 +7,9 @@
 # any later version.
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-# COBJS-y	+= $(BOARD).o
-COBJS-y	+= law.o
-COBJS-y	+= ddr.o
-COBJS-y	+= tlb.o
-COBJS-y	+= sdhc_boot.o
-COBJS-$(CONFIG_CONTROLCENTERD) += controlcenterd.o controlcenterd-id.o
-
-COBJS-$(CONFIG_FSL_DIU_FB) += diu.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS-y))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(OBJS) $(SOBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	+= law.o
+obj-y	+= ddr.o
+obj-y	+= tlb.o
+obj-y	+= sdhc_boot.o
+obj-$(CONFIG_CONTROLCENTERD) += controlcenterd.o controlcenterd-id.o
+obj-$(CONFIG_FSL_DIU_FB) += diu.o
diff --git a/board/gdsys/p1022/controlcenterd.c b/board/gdsys/p1022/controlcenterd.c
index 81c22bc94c..8ccd9ce6ba 100644
--- a/board/gdsys/p1022/controlcenterd.c
+++ b/board/gdsys/p1022/controlcenterd.c
@@ -29,7 +29,7 @@
 #include <asm/cache.h>
 #include <asm/immap_85xx.h>
 #include <asm/fsl_pci.h>
-#include <asm/fsl_ddr_sdram.h>
+#include <fsl_ddr_sdram.h>
 #include <asm/fsl_serdes.h>
 #include <asm/io.h>
 #include <libfdt.h>
diff --git a/board/gdsys/p1022/ddr.c b/board/gdsys/p1022/ddr.c
index 4a652de430..7596736bfd 100644
--- a/board/gdsys/p1022/ddr.c
+++ b/board/gdsys/p1022/ddr.c
@@ -12,8 +12,8 @@
 #include <common.h>
 #include <i2c.h>
 
-#include <asm/fsl_ddr_sdram.h>
-#include <asm/fsl_ddr_dimm_params.h>
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr_dimm_params.h>
 
 void fsl_ddr_board_options(memctl_options_t *popts, dimm_params_t *pdimm,
 			   unsigned int ctrl_num)
diff --git a/board/gen860t/Makefile b/board/gen860t/Makefile
index 03551852e9..86ae5e80e1 100644
--- a/board/gen860t/Makefile
+++ b/board/gen860t/Makefile
@@ -5,24 +5,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	= $(BOARD).o flash.o beeper.o fpga.o ioport.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	= gen860t.o flash.o beeper.o fpga.o ioport.o
diff --git a/board/genesi/mx51_efikamx/Makefile b/board/genesi/mx51_efikamx/Makefile
index 7ede567e0a..87f5f9ede1 100644
--- a/board/genesi/mx51_efikamx/Makefile
+++ b/board/genesi/mx51_efikamx/Makefile
@@ -10,23 +10,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	:= efikamx.o efikamx-usb.o
-
-SRCS	:= $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	:= efikamx.o efikamx-usb.o
diff --git a/board/genesi/mx51_efikamx/efikamx.c b/board/genesi/mx51_efikamx/efikamx.c
index 76753f90f6..16769e5332 100644
--- a/board/genesi/mx51_efikamx/efikamx.c
+++ b/board/genesi/mx51_efikamx/efikamx.c
@@ -159,7 +159,7 @@ static void power_init(void)
 	struct pmic *p;
 	int ret;
 
-	ret = pmic_init(I2C_PMIC);
+	ret = pmic_init(CONFIG_FSL_PMIC_BUS);
 	if (ret)
 		return;
 
diff --git a/board/genietv/Makefile b/board/genietv/Makefile
index 871865b6ee..fd11f14b3a 100644
--- a/board/genietv/Makefile
+++ b/board/genietv/Makefile
@@ -5,24 +5,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	= $(BOARD).o flash.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	= genietv.o flash.o
diff --git a/board/genietv/genietv.h b/board/genietv/genietv.h
deleted file mode 100644
index 7c95b566f9..0000000000
--- a/board/genietv/genietv.h
+++ /dev/null
@@ -1,25 +0,0 @@
-/*
- * The GENIETV is using the following physical memorymap (copied from
- * the FADS configuration):
- *
- * ff020000 -> ff02ffff : pcmcia
- * ff010000 -> ff01ffff : BCSR       connected to CS1, setup by 8xxROM
- * ff000000 -> ff00ffff : IMAP       internal in the cpu
- * 02800000 -> 0287ffff : flash      connected to CS0
- * 00000000 -> nnnnnnnn : sdram      setup by U-Boot
- *
- * CS pins are connected as follows:
- *
- * CS0 -512Kb boot flash
- * CS1 - SDRAM #1
- * CS2 - SDRAM #2
- * CS3 - Flash #1
- * CS4 - Flash #2
- * CS5 - LON (if present)
- * CS6 - PCMCIA #1
- * CS7 - PCMCIA #2
- *
- * Ports are configured as follows:
- *
- * PA7 - SDRAM banks enable
- */
diff --git a/board/genietv/u-boot.lds b/board/genietv/u-boot.lds
index e217f06819..70ab702fd9 100644
--- a/board/genietv/u-boot.lds
+++ b/board/genietv/u-boot.lds
@@ -18,11 +18,11 @@ SECTIONS
 
     arch/powerpc/cpu/mpc8xx/start.o	(.text*)
     arch/powerpc/cpu/mpc8xx/traps.o	(.text*)
-    lib/libgeneric.o			(.text*)
-    net/libnet.o			(.text*)
-    arch/powerpc/cpu/mpc8xx/libmpc8xx.o	(.text*)
-    board/genietv/libgenietv.o		(.text*)
-    arch/powerpc/lib/libpowerpc.o	(.text*)
+    lib/built-in.o			(.text*)
+    net/built-in.o			(.text*)
+    arch/powerpc/cpu/mpc8xx/built-in.o	(.text*)
+    board/genietv/built-in.o		(.text*)
+    arch/powerpc/lib/built-in.o		(.text*)
     *(.text.do_load_serial*)
     *(.text.do_mem_*)
     *(.text.do_bootm*)
diff --git a/board/gw8260/Makefile b/board/gw8260/Makefile
index ff9bd0f646..2e23f398af 100644
--- a/board/gw8260/Makefile
+++ b/board/gw8260/Makefile
@@ -5,25 +5,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	:= gw8260.o flash.o
-SOBJS   :=
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	:= gw8260.o flash.o
diff --git a/board/h2200/Makefile b/board/h2200/Makefile
index 26bf14483f..e516e916b4 100644
--- a/board/h2200/Makefile
+++ b/board/h2200/Makefile
@@ -6,31 +6,9 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
+obj-y	:= h2200.o
 
-LIB	= $(obj)lib$(BOARD).o
+extra-y := h2200-header.bin
 
-COBJS	:= h2200.o
-
-SRCS	:= $(COBJS:.o=.c) h2200-header.S
-OBJS	:= $(addprefix $(obj),$(COBJS))
-
-all: $(LIB) $(obj)h2200-header.bin
-
-$(obj)h2200-header.o: h2200-header.S
-	$(CC) $(CFLAGS) -c -o $@ $<
-
-$(obj)h2200-header.bin: $(obj)h2200-header.o
+$(obj)/h2200-header.bin: $(obj)/h2200-header.o
 	$(OBJCOPY) -O binary $< $@
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
diff --git a/board/hale/tt01/Makefile b/board/hale/tt01/Makefile
index afdc2c1213..e06a040422 100644
--- a/board/hale/tt01/Makefile
+++ b/board/hale/tt01/Makefile
@@ -6,30 +6,5 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-COBJS	:= tt01.o
-SOBJS	:= lowlevel_init.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
-	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
-
-clean:
-	rm -f $(SOBJS) $(OBJS)
-
-distclean:	clean
-	rm -f $(LIB) core *.bak $(obj).depend
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	:= tt01.o
+obj-y	+= lowlevel_init.o
diff --git a/board/hermes/Makefile b/board/hermes/Makefile
index 871865b6ee..ccca520e42 100644
--- a/board/hermes/Makefile
+++ b/board/hermes/Makefile
@@ -5,24 +5,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	= $(BOARD).o flash.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	= hermes.o flash.o
diff --git a/board/hermes/u-boot.lds b/board/hermes/u-boot.lds
index 9419f83a70..0309860391 100644
--- a/board/hermes/u-boot.lds
+++ b/board/hermes/u-boot.lds
@@ -17,7 +17,7 @@ SECTIONS
     /* the sector layout of our flash chips!	XXX FIXME XXX	*/
     arch/powerpc/cpu/mpc8xx/start.o	(.text*)
     arch/powerpc/cpu/mpc8xx/traps.o	(.text*)
-    board/hermes/libhermes.o		(.text*)
+    board/hermes/built-in.o		(.text*)
 
     . = env_offset;
     common/env_embedded.o		(.text*)
diff --git a/board/hidden_dragon/Makefile b/board/hidden_dragon/Makefile
index 9d46b9b0da..eb1c5fdf86 100644
--- a/board/hidden_dragon/Makefile
+++ b/board/hidden_dragon/Makefile
@@ -5,24 +5,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS =  $(BOARD).o flash.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y =  hidden_dragon.o flash.o
diff --git a/board/hidden_dragon/speed.h b/board/hidden_dragon/speed.h
deleted file mode 100644
index f1b10bf25e..0000000000
--- a/board/hidden_dragon/speed.h
+++ /dev/null
@@ -1,38 +0,0 @@
-/*
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-/*-----------------------------------------------------------------------
- * Timer value for timer 2, ICLK = 10
- *
- * SPEED_FCOUNT2 =  GCLK / (16 * (TIMER_TMR_PS + 1))
- * SPEED_TMR3_PS = (GCLK / (16 * SPEED_FCOUNT3)) - 1
- *
- * SPEED_FCOUNT2	timer 2 counting frequency
- * GCLK			CPU clock
- * SPEED_TMR2_PS	prescaler
- */
-#define SPEED_TMR2_PS	(250 - 1)	/* divide by 250	*/
-
-/*-----------------------------------------------------------------------
- * Timer value for PIT
- *
- * PIT_TIME = SPEED_PITC / PITRTCLK
- * PITRTCLK = 8192
- */
-#define SPEED_PITC	(82 << 16)	/* start counting from 82	*/
-
-/*
- * The new value for PTA is calculated from
- *
- *	PTA = (gclk * Trefresh) / (2 ^ (2 * DFBRG) * PTP * NCS)
- *
- * gclk		CPU clock (not bus clock !)
- * Trefresh	Refresh cycle * 4 (four word bursts used)
- * DFBRG	For normal mode (no clock reduction) always 0
- * PTP		Prescaler (already adjusted for no. of banks and 4K / 8K refresh)
- * NCS		Number of SDRAM banks (chip selects) on this UPM.
- */
diff --git a/board/highbank/Makefile b/board/highbank/Makefile
index 3aa134ab49..d3eb23220b 100644
--- a/board/highbank/Makefile
+++ b/board/highbank/Makefile
@@ -5,29 +5,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	:= highbank.o
-
-SRCS	:= $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-clean:
-	rm -f $(OBJS)
-
-distclean:	clean
-	rm -f $(LIB) core *.bak $(obj).depend
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	:= highbank.o
diff --git a/board/highbank/highbank.c b/board/highbank/highbank.c
index 4b272c780e..a1b67494f6 100644
--- a/board/highbank/highbank.c
+++ b/board/highbank/highbank.c
@@ -9,7 +9,7 @@
 #include <netdev.h>
 #include <scsi.h>
 
-#include <asm/sizes.h>
+#include <linux/sizes.h>
 #include <asm/io.h>
 
 #define HB_AHCI_BASE			0xffe08000
@@ -51,17 +51,23 @@ int board_eth_init(bd_t *bis)
 	return rc;
 }
 
-#ifdef CONFIG_MISC_INIT_R
-int misc_init_r(void)
+#ifdef CONFIG_SCSI_AHCI_PLAT
+void scsi_init(void)
 {
-	char envbuffer[16];
-	u32 boot_choice;
 	u32 reg = readl(HB_SREG_A9_PWRDOM_STAT);
 
 	if (reg & PWRDOM_STAT_SATA) {
 		ahci_init(HB_AHCI_BASE);
 		scsi_scan(1);
 	}
+}
+#endif
+
+#ifdef CONFIG_MISC_INIT_R
+int misc_init_r(void)
+{
+	char envbuffer[16];
+	u32 boot_choice;
 
 	boot_choice = readl(HB_SREG_A9_BOOT_SRC_STAT) & 0xff;
 	sprintf(envbuffer, "bootcmd%d", boot_choice);
diff --git a/board/htkw/mcx/Makefile b/board/htkw/mcx/Makefile
index 641e61e708..20149ba809 100644
--- a/board/htkw/mcx/Makefile
+++ b/board/htkw/mcx/Makefile
@@ -6,21 +6,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	:= $(BOARD).o
-
-SRCS	:= $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
+obj-y	:= mcx.o
diff --git a/board/htkw/mcx/mcx.c b/board/htkw/mcx/mcx.c
index 653d7ea71d..4330cf0ddb 100644
--- a/board/htkw/mcx/mcx.c
+++ b/board/htkw/mcx/mcx.c
@@ -40,9 +40,10 @@ static struct omap_usbhs_board_data usbhs_bdata = {
 	.port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED,
 };
 
-int ehci_hcd_init(int index, struct ehci_hccr **hccr, struct ehci_hcor **hcor)
+int ehci_hcd_init(int index, enum usb_init_type init,
+		struct ehci_hccr **hccr, struct ehci_hcor **hcor)
 {
-	return omap_ehci_hcd_init(&usbhs_bdata, hccr, hcor);
+	return omap_ehci_hcd_init(index, &usbhs_bdata, hccr, hcor);
 }
 
 int ehci_hcd_stop(int index)
diff --git a/board/htkw/mcx/mcx.h b/board/htkw/mcx/mcx.h
index 703dbeccfd..17c122cf50 100644
--- a/board/htkw/mcx/mcx.h
+++ b/board/htkw/mcx/mcx.h
@@ -325,8 +325,6 @@ const omap3_sysinfo sysinfo = {
 	MUX_VAL(CP(SYS_32K),		(IEN  | PTD | EN  | M4)) \
 	MUX_VAL(CP(SYS_CLKREQ),		(IEN  | PTD | DIS | M0)) \
 	MUX_VAL(CP(SYS_NIRQ),		(IEN  | PTD | EN  | M4)) \
-	MUX_VAL(CP(SYS_NRESWARM),	(IEN | PTU | DIS | M4)) \
-					/* SYS_nRESWARM */\
 	MUX_VAL(CP(SYS_BOOT0),		(IEN  | PTD | DIS | M4)) \
 	MUX_VAL(CP(SYS_BOOT1),		(IEN  | PTD | DIS | M4)) \
 	MUX_VAL(CP(SYS_BOOT2),		(IEN  | PTD | DIS | M4)) \
diff --git a/board/hymod/Makefile b/board/hymod/Makefile
index 6e9f436acb..b9080b0a96 100644
--- a/board/hymod/Makefile
+++ b/board/hymod/Makefile
@@ -5,24 +5,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	= $(BOARD).o flash.o bsp.o eeprom.o fetch.o input.o env.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	= hymod.o flash.o bsp.o eeprom.o fetch.o input.o env.o
diff --git a/board/hymod/config.mk b/board/hymod/config.mk
index abcd2d50ac..2eeea50377 100644
--- a/board/hymod/config.mk
+++ b/board/hymod/config.mk
@@ -9,6 +9,6 @@
 # HYMOD boards
 #
 
-PLATFORM_CPPFLAGS += -I$(TOPDIR)
+PLATFORM_CPPFLAGS += -I$(srctree)
 
-OBJCFLAGS = --remove-section=.ppcenv
+OBJCOPYFLAGS = --remove-section=.ppcenv
diff --git a/board/hymod/hymod.h b/board/hymod/hymod.h
index 2c58bfb6e0..7024d8a807 100644
--- a/board/hymod/hymod.h
+++ b/board/hymod/hymod.h
@@ -8,8 +8,7 @@
 #ifndef _HYMOD_H_
 #define _HYMOD_H_
 
-#include <linux/config.h>
-#ifdef CONFIG_8260
+#ifdef CONFIG_MPC8260
 #include <asm/iopin_8260.h>
 #endif
 
diff --git a/board/ibf-dsp561/Makefile b/board/ibf-dsp561/Makefile
index 099bcaf999..5b05ba8003 100644
--- a/board/ibf-dsp561/Makefile
+++ b/board/ibf-dsp561/Makefile
@@ -9,24 +9,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS-y	:= $(BOARD).o
-
-SRCS	:= $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS-y))
-SOBJS	:= $(addprefix $(obj),$(SOBJS-y))
-
-$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
-	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	:= ibf-dsp561.o
diff --git a/board/icecube/Makefile b/board/icecube/Makefile
index 4ff6b2d995..c3c2cd1c3e 100644
--- a/board/icecube/Makefile
+++ b/board/icecube/Makefile
@@ -1,4 +1,3 @@
-
 #
 # (C) Copyright 2003-2006
 # Wolfgang Denk, DENX Software Engineering, wd@denx.de.
@@ -6,24 +5,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	:= $(BOARD).o flash.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	:= icecube.o flash.o
diff --git a/board/icpdas/lp8x4x/Makefile b/board/icpdas/lp8x4x/Makefile
index 270bcac9af..88e0606e1e 100644
--- a/board/icpdas/lp8x4x/Makefile
+++ b/board/icpdas/lp8x4x/Makefile
@@ -6,23 +6,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	:= lp8x4x.o
-
-SRCS	:= $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	:= lp8x4x.o
diff --git a/board/icpdas/lp8x4x/lp8x4x.c b/board/icpdas/lp8x4x/lp8x4x.c
index 1b68ef332a..a136dc4c37 100644
--- a/board/icpdas/lp8x4x/lp8x4x.c
+++ b/board/icpdas/lp8x4x/lp8x4x.c
@@ -15,6 +15,7 @@
 #include <netdev.h>
 #include <serial.h>
 #include <asm/io.h>
+#include <usb.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -58,17 +59,26 @@ int board_mmc_init(bd_t *bis)
 #endif
 
 #ifdef	CONFIG_CMD_USB
-int usb_board_init(void)
+int board_usb_init(int index, enum usb_init_type init)
 {
-	writel((UHCHR | UHCHR_PCPL | UHCHR_PSPL) &
-		~(UHCHR_SSEP0 | UHCHR_SSEP1 | UHCHR_SSEP2 | UHCHR_SSE),
-		UHCHR);
+	if (index !=0 || init != USB_INIT_HOST)
+		return -1;
+
+	writel(readl(CKEN) | CKEN10_USBHOST, CKEN);
+
+	writel(readl(UHCHR) | UHCHR_FHR, UHCHR);
+	udelay(11);
+	writel(readl(UHCHR) & ~UHCHR_FHR, UHCHR);
 
 	writel(readl(UHCHR) | UHCHR_FSBIR, UHCHR);
 
 	while (readl(UHCHR) & UHCHR_FSBIR)
 		continue; /* required by checkpath.pl */
 
+	writel(readl(UHCHR) & ~UHCHR_SSEP0, UHCHR);
+	writel(readl(UHCRHDA) & ~(0x1000), UHCRHDA);
+	writel(readl(UHCRHDA) | 0x800, UHCRHDA);
+
 	writel(readl(UHCHR) & ~UHCHR_SSE, UHCHR);
 	writel((UHCHIE_UPRIE | UHCHIE_RWIE), UHCHIE);
 
@@ -82,19 +92,10 @@ int usb_board_init(void)
 	/* Set port power control mask bits, only 3 ports. */
 	writel(readl(UHCRHDB) | (0x7<<17), UHCRHDB);
 
-	/* enable port 2 */
-	writel(readl(UP2OCR) | UP2OCR_HXOE | UP2OCR_HXS |
-		UP2OCR_DMPDE | UP2OCR_DPPDE, UP2OCR);
-
 	return 0;
 }
 
-void usb_board_init_fail(void)
-{
-	return;
-}
-
-void usb_board_stop(void)
+int usb_board_stop(void)
 {
 	writel(readl(UHCHR) | UHCHR_FHR, UHCHR);
 	udelay(11);
@@ -103,32 +104,25 @@ void usb_board_stop(void)
 	writel(readl(UHCCOMS) | 1, UHCCOMS);
 	udelay(10);
 
+	writel(readl(UHCHR) | UHCHR_SSEP0 | UHCHR_SSE, UHCHR);
+
 	writel(readl(CKEN) & ~CKEN10_USBHOST, CKEN);
 
-	return;
+	return 0;
 }
-#endif
 
-#ifdef CONFIG_DRIVER_DM9000
-void lp8x4x_eth1_mac_init(void)
+int board_usb_cleanup(int index, enum usb_init_type init)
 {
-	u8 eth1addr[8];
-	int i;
-	u8 reg;
-
-	eth_getenv_enetaddr_by_index("eth", 1, eth1addr);
-	if (!is_valid_ether_addr(eth1addr))
-		return;
-
-	for (i = 0, reg = 0x10; i < 6; i++, reg++) {
-		writeb(reg, (u8 *)(DM9000_IO_2));
-		writeb(eth1addr[i], (u8 *)(DM9000_DATA_2));
-	}
+	if (index !=0 || init != USB_INIT_HOST)
+		return -1;
+
+	return usb_board_stop();
 }
+#endif
 
+#ifdef CONFIG_DRIVER_DM9000
 int board_eth_init(bd_t *bis)
 {
-	lp8x4x_eth1_mac_init();
 	return dm9000_initialize(bis);
 }
 #endif
diff --git a/board/icu862/Makefile b/board/icu862/Makefile
index e1ac275ccd..263f21b96e 100644
--- a/board/icu862/Makefile
+++ b/board/icu862/Makefile
@@ -5,24 +5,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	= $(BOARD).o flash.o pcmcia.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	= icu862.o flash.o pcmcia.o
diff --git a/board/idmr/Makefile b/board/idmr/Makefile
deleted file mode 100644
index 871865b6ee..0000000000
--- a/board/idmr/Makefile
+++ /dev/null
@@ -1,28 +0,0 @@
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	= $(BOARD).o flash.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
diff --git a/board/idmr/config.mk b/board/idmr/config.mk
deleted file mode 100644
index 840a37e856..0000000000
--- a/board/idmr/config.mk
+++ /dev/null
@@ -1,9 +0,0 @@
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-# Coldfire contribution by Bernhard Kuhn <bkuhn@metrowerks.com>
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-CONFIG_SYS_TEXT_BASE = 0xff800000
diff --git a/board/idmr/flash.c b/board/idmr/flash.c
deleted file mode 100644
index 52eb105c32..0000000000
--- a/board/idmr/flash.c
+++ /dev/null
@@ -1,342 +0,0 @@
-/*
- * (C) Copyright 2000-2006
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-
-#define PHYS_FLASH_1 CONFIG_SYS_FLASH_BASE
-#define FLASH_BANK_SIZE 0x800000
-#define EN29LV640 0x227e227e
-
-flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
-
-void flash_print_info (flash_info_t * info)
-{
-	int i;
-
-	switch (info->flash_id & FLASH_VENDMASK) {
-	case (AMD_MANUFACT & FLASH_VENDMASK):
-		printf ("AMD: ");
-		break;
-	default:
-		printf ("Unknown Vendor ");
-		break;
-	}
-
-	switch (info->flash_id & FLASH_TYPEMASK) {
-	case (EN29LV640 & FLASH_TYPEMASK):
-		printf ("EN29LV640 (16Mbit)\n");
-		break;
-	default:
-		printf ("Unknown Chip Type\n");
-		goto Done;
-		break;
-	}
-
-	printf ("  Size: %ld MB in %d Sectors\n",
-		info->size >> 20, info->sector_count);
-
-	printf ("  Sector Start Addresses:");
-	for (i = 0; i < info->sector_count; i++) {
-		if ((i % 5) == 0) {
-			printf ("\n   ");
-		}
-		printf (" %08lX%s", info->start[i],
-			info->protect[i] ? " (RO)" : "     ");
-	}
-	printf ("\n");
-
-      Done:
-	return;
-}
-
-
-unsigned long flash_init (void)
-{
-	int i, j;
-	ulong size = 0;
-
-	for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) {
-		ulong flashbase = 0;
-
-		flash_info[i].flash_id =
-			(AMD_MANUFACT & FLASH_VENDMASK) |
-			(EN29LV640 & FLASH_TYPEMASK);
-		flash_info[i].size = FLASH_BANK_SIZE;
-		flash_info[i].sector_count = CONFIG_SYS_MAX_FLASH_SECT;
-		memset (flash_info[i].protect, 0, CONFIG_SYS_MAX_FLASH_SECT);
-		if (i == 0)
-			flashbase = PHYS_FLASH_1;
-		else
-			panic ("configured to many flash banks!\n");
-
-		for (j = 0; j < flash_info[i].sector_count; j++) {
-			flash_info[i].start[j] = flashbase + 0x10000 * j;
-		}
-		size += flash_info[i].size;
-	}
-
-	flash_protect (FLAG_PROTECT_SET,
-		       CONFIG_SYS_FLASH_BASE,
-		       CONFIG_SYS_FLASH_BASE + 0x2ffff, &flash_info[0]);
-
-	return size;
-}
-
-
-#define CMD_READ_ARRAY		0x00F0
-#define CMD_UNLOCK1		0x00AA
-#define CMD_UNLOCK2		0x0055
-#define CMD_ERASE_SETUP		0x0080
-#define CMD_ERASE_CONFIRM	0x0030
-#define CMD_PROGRAM		0x00A0
-#define CMD_UNLOCK_BYPASS	0x0020
-
-#define MEM_FLASH_ADDR1		(*(volatile u16 *)(CONFIG_SYS_FLASH_BASE + (0x00000555<<1)))
-#define MEM_FLASH_ADDR2		(*(volatile u16 *)(CONFIG_SYS_FLASH_BASE + (0x000002AA<<1)))
-
-#define BIT_ERASE_DONE		0x0080
-#define BIT_RDY_MASK		0x0080
-#define BIT_PROGRAM_ERROR	0x0020
-#define BIT_TIMEOUT		0x80000000	/* our flag */
-
-#define READY 1
-#define ERR   2
-#define TMO   4
-
-
-int flash_erase (flash_info_t * info, int s_first, int s_last)
-{
-	ulong result;
-	int iflag, prot, sect;
-	int rc = ERR_OK;
-	int chip1;
-	ulong start;
-
-	/* first look for protection bits */
-
-	if (info->flash_id == FLASH_UNKNOWN)
-		return ERR_UNKNOWN_FLASH_TYPE;
-
-	if ((s_first < 0) || (s_first > s_last)) {
-		return ERR_INVAL;
-	}
-
-	if ((info->flash_id & FLASH_VENDMASK) !=
-	    (AMD_MANUFACT & FLASH_VENDMASK)) {
-		return ERR_UNKNOWN_FLASH_VENDOR;
-	}
-
-	prot = 0;
-	for (sect = s_first; sect <= s_last; ++sect) {
-		if (info->protect[sect]) {
-			prot++;
-		}
-	}
-	if (prot)
-		return ERR_PROTECTED;
-
-	/*
-	 * Disable interrupts which might cause a timeout
-	 * here. Remember that our exception vectors are
-	 * at address 0 in the flash, and we don't want a
-	 * (ticker) exception to happen while the flash
-	 * chip is in programming mode.
-	 */
-	iflag = disable_interrupts ();
-
-	printf ("\n");
-
-	/* Start erase on unprotected sectors */
-	for (sect = s_first; sect <= s_last && !ctrlc (); sect++) {
-		printf ("Erasing sector %2d ... ", sect);
-
-		/* arm simple, non interrupt dependent timer */
-		start = get_timer(0);
-
-		if (info->protect[sect] == 0) {	/* not protected */
-			volatile u16 *addr =
-				(volatile u16 *) (info->start[sect]);
-
-			MEM_FLASH_ADDR1 = CMD_UNLOCK1;
-			MEM_FLASH_ADDR2 = CMD_UNLOCK2;
-			MEM_FLASH_ADDR1 = CMD_ERASE_SETUP;
-
-			MEM_FLASH_ADDR1 = CMD_UNLOCK1;
-			MEM_FLASH_ADDR2 = CMD_UNLOCK2;
-			*addr = CMD_ERASE_CONFIRM;
-
-			/* wait until flash is ready */
-			chip1 = 0;
-
-			do {
-				result = *addr;
-
-				/* check timeout */
-				if (get_timer(start) > CONFIG_SYS_FLASH_ERASE_TOUT * CONFIG_SYS_HZ / 1000) {
-					MEM_FLASH_ADDR1 = CMD_READ_ARRAY;
-					chip1 = TMO;
-					break;
-				}
-
-				if (!chip1
-				    && (result & 0xFFFF) & BIT_ERASE_DONE)
-					chip1 = READY;
-
-			} while (!chip1);
-
-			MEM_FLASH_ADDR1 = CMD_READ_ARRAY;
-
-			if (chip1 == ERR) {
-				rc = ERR_PROG_ERROR;
-				goto outahere;
-			}
-			if (chip1 == TMO) {
-				rc = ERR_TIMOUT;
-				goto outahere;
-			}
-
-			printf ("ok.\n");
-		} else {	/* it was protected */
-
-			printf ("protected!\n");
-		}
-	}
-
-	if (ctrlc ())
-		printf ("User Interrupt!\n");
-
-      outahere:
-	/* allow flash to settle - wait 10 ms */
-	printf("Waiting 10 ms...");
-	 udelay (10000);
-
-/*	for (i = 0; i < 10 * 1000 * 1000; ++i)
-		asm(" nop");
-*/
-
-	printf("done\n");
-	if (iflag)
-		enable_interrupts ();
-
-
-	return rc;
-}
-
-static int write_word (flash_info_t * info, ulong dest, ulong data)
-{
-	volatile u16 *addr = (volatile u16 *) dest;
-	ulong result;
-	int rc = ERR_OK;
-	int iflag;
-	int chip1;
-	ulong start;
-
-	/*
-	 * Check if Flash is (sufficiently) erased
-	 */
-	result = *addr;
-	if ((result & data) != data)
-		return ERR_NOT_ERASED;
-
-
-	/*
-	 * Disable interrupts which might cause a timeout
-	 * here. Remember that our exception vectors are
-	 * at address 0 in the flash, and we don't want a
-	 * (ticker) exception to happen while the flash
-	 * chip is in programming mode.
-	 */
-	iflag = disable_interrupts ();
-
-	MEM_FLASH_ADDR1 = CMD_UNLOCK1;
-	MEM_FLASH_ADDR2 = CMD_UNLOCK2;
-	MEM_FLASH_ADDR1 = CMD_PROGRAM;
-	*addr = data;
-
-	/* arm simple, non interrupt dependent timer */
-	start = get_timer(0);
-
-	/* wait until flash is ready */
-	chip1 = 0;
-	do {
-		result = *addr;
-
-		/* check timeout */
-		if (get_timer(start) > CONFIG_SYS_FLASH_ERASE_TOUT * CONFIG_SYS_HZ / 1000) {
-			chip1 = ERR | TMO;
-			break;
-		}
-		if (!chip1 && ((result & 0x80) == (data & 0x80)))
-			chip1 = READY;
-
-	} while (!chip1);
-
-	*addr = CMD_READ_ARRAY;
-
-	if (chip1 == ERR || *addr != data)
-		rc = ERR_PROG_ERROR;
-
-	if (iflag)
-		enable_interrupts ();
-
-	return rc;
-}
-
-
-int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
-{
-	ulong wp, data;
-	int rc;
-
-	if (addr & 1) {
-		printf ("unaligned destination not supported\n");
-		return ERR_ALIGN;
-	}
-
-#if 0
-	if (cnt & 1) {
-		printf ("odd transfer sizes not supported\n");
-		return ERR_ALIGN;
-	}
-#endif
-
-	wp = addr;
-
-	if (addr & 1) {
-		data = (*((volatile u8 *) addr) << 8) | *((volatile u8 *)
-							  src);
-		if ((rc = write_word (info, wp - 1, data)) != 0) {
-			return (rc);
-		}
-		src += 1;
-		wp += 1;
-		cnt -= 1;
-	}
-
-	while (cnt >= 2) {
-		data = *((volatile u16 *) src);
-		if ((rc = write_word (info, wp, data)) != 0) {
-			return (rc);
-		}
-		src += 2;
-		wp += 2;
-		cnt -= 2;
-	}
-
-	if (cnt == 1) {
-		data = (*((volatile u8 *) src) << 8) |
-			*((volatile u8 *) (wp + 1));
-		if ((rc = write_word (info, wp, data)) != 0) {
-			return (rc);
-		}
-		src += 1;
-		wp += 1;
-		cnt -= 1;
-	}
-
-	return ERR_OK;
-}
diff --git a/board/idmr/idmr.c b/board/idmr/idmr.c
deleted file mode 100644
index 73660d802d..0000000000
--- a/board/idmr/idmr.c
+++ /dev/null
@@ -1,152 +0,0 @@
-/*
- * (C) Copyright 2000-2006
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/immap.h>
-
-int checkboard (void) {
-	puts ("Board: iDMR\n");
-	return 0;
-};
-
-phys_size_t initdram (int board_type) {
-	int i;
-
-	/*
-	 * After reset, CS0 is configured to cover entire address space. We
-	 * need to configure it to its proper values, so that writes to
-	 * CONFIG_SYS_SDRAM_BASE and vicinity during SDRAM controller setup below do
-	 * now fall under CS0 (see 16.3.1 of the MCF5271 Reference Manual).
-	 */
-
-	/* Flash chipselect, CS0 */
-	/* ;CSAR0: Flash at 0xFF800000 */
-	mbar_writeShort(0x0080, 0xFF80);
-
-	/* CSCR0: Flash 6 waits, 16bit */
-	mbar_writeShort(0x008A, 0x1980);
-
-	/* CSMR0: Flash 8MB, R/W, valid */
-	mbar_writeLong(0x0084, 0x007F0001);
-
-
-	/*
-	 * SDRAM configuration proper
-	 */
-
-	/*
-	 * Address/Data Pin Assignment Reg.: enable address lines 23-21; do
-	 * not enable data pins D[15:0], as we have 16 bit port to SDRAM
-	 */
-	mbar_writeByte(MCF_GPIO_PAR_AD,
-			MCF_GPIO_AD_ADDR23 |
-			MCF_GPIO_AD_ADDR22 |
-			MCF_GPIO_AD_ADDR21);
-
-	/* No need to configure BS pins - reset values are OK */
-
-	/* Chip Select Pin Assignment Reg.: set CS[1-7] to GPIO */
-	mbar_writeByte(MCF_GPIO_PAR_CS, 0x00);
-
-	/* SDRAM Control Pin Assignment Reg. */
-	mbar_writeByte(MCF_GPIO_PAR_SDRAM,
-			MCF_GPIO_SDRAM_CSSDCS_00 | /* no matter: PAR_CS=0 */
-			MCF_GPIO_SDRAM_SDWE |
-			MCF_GPIO_SDRAM_SCAS |
-			MCF_GPIO_SDRAM_SRAS |
-			MCF_GPIO_SDRAM_SCKE |
-			MCF_GPIO_SDRAM_SDCS_01);
-
-	/*
-	 * Wait 100us.  We run the bus at 50MHz, one cycle is 20ns. So 5
-	 * iterations will do, but we do 10 just to be safe.
-	 */
-	for (i = 0; i < 10; ++i)
-		asm(" nop");
-
-
-	/* 1. Initialize DRAM Control Register: DCR */
-	mbar_writeShort(MCF_SDRAMC_DCR,
-			MCF_SDRAMC_DCR_RTIM(0x10) |	/* 65ns */
-			MCF_SDRAMC_DCR_RC(0x60));	/* 1562 cycles */
-
-
-	/*
-	 * 2. Initialize DACR0
-	 *
-	 * CL: 11 (CL=3: 0x03, 0x02; CL=2: 0x1)
-	 * CBM: cmd at A20, bank select bits 21 and up
-	 * PS: 16 bit
-	 */
-	mbar_writeLong(MCF_SDRAMC_DACR0,
-			MCF_SDRAMC_DACRn_BA(CONFIG_SYS_SDRAM_BASE>>18) |
-			MCF_SDRAMC_DACRn_BA(0x00) |
-			MCF_SDRAMC_DACRn_CASL(0x03) |
-			MCF_SDRAMC_DACRn_CBM(0x03) |
-			MCF_SDRAMC_DACRn_PS(0x03));
-
-	/* Initialize DMR0 */
-	mbar_writeLong(MCF_SDRAMC_DMR0,
-			MCF_SDRAMC_DMRn_BAM_16M |
-			MCF_SDRAMC_DMRn_V);
-
-
-	/* 3. Set IP bit in DACR to initiate PALL command */
-	mbar_writeLong(MCF_SDRAMC_DACR0,
-			mbar_readLong(MCF_SDRAMC_DACR0) |
-			MCF_SDRAMC_DACRn_IP);
-
-	/* Write to this block to initiate precharge */
-	*(volatile u16 *)(CONFIG_SYS_SDRAM_BASE) = 0xa5a5;
-
-	/*
-	 * Wait at least 20ns to allow banks to precharge (t_RP = 20ns). We
-	 * wait a wee longer, just to be safe.
-	 */
-	for (i = 0; i < 5; ++i)
-		asm(" nop");
-
-
-	/* 4. Set RE bit in DACR */
-	mbar_writeLong(MCF_SDRAMC_DACR0,
-			mbar_readLong(MCF_SDRAMC_DACR0) |
-			MCF_SDRAMC_DACRn_RE);
-
-	/*
-	 * Wait for at least 8 auto refresh cycles to occur, i.e. at least
-	 * 781 bus cycles.
-	 */
-	for (i = 0; i < 1000; ++i)
-		asm(" nop");
-
-	/* Finish the configuration by issuing the MRS */
-	mbar_writeLong(MCF_SDRAMC_DACR0,
-			mbar_readLong(MCF_SDRAMC_DACR0) |
-			MCF_SDRAMC_DACRn_MRS);
-
-	/*
-	 * Write to the SDRAM Mode Register A0-A11 = 0x400
-	 *
-	 * Write Burst Mode = Programmed Burst Length
-	 * Op Mode = Standard Op
-	 * CAS Latency = 3
-	 * Burst Type = Sequential
-	 * Burst Length = 1
-	 */
-	*(volatile u32 *)(CONFIG_SYS_SDRAM_BASE + 0x1800) = 0xa5a5a5a5;
-
-	return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
-};
-
-
-int testdram (void) {
-
-	/* TODO: XXX XXX XXX */
-	printf ("DRAM test not implemented!\n");
-
-	return (0);
-}
diff --git a/board/idmr/u-boot.lds b/board/idmr/u-boot.lds
deleted file mode 100644
index 4071f70d45..0000000000
--- a/board/idmr/u-boot.lds
+++ /dev/null
@@ -1,82 +0,0 @@
-/*
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-OUTPUT_ARCH(m68k)
-
-SECTIONS
-{
-  .text      :
-  {
-    arch/m68k/cpu/mcf52x2/start.o	(.text*)
-
-    *(.text*)
-  }
-  _etext = .;
-  PROVIDE (etext = .);
-  .rodata    :
-  {
-    *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
-  }
-
-  /* Read-write section, merged into data segment: */
-  . = (. + 0x00FF) & 0xFFFFFF00;
-  _erotext = .;
-  PROVIDE (erotext = .);
-
-  .reloc   :
-  {
-    __got_start = .;
-    KEEP(*(.got))
-    __got_end = .;
-    _GOT2_TABLE_ = .;
-    KEEP(*(.got2))
-    _FIXUP_TABLE_ = .;
-    KEEP(*(.fixup))
-  }
-  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
-  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
-
-  .data    :
-  {
-    *(.data*)
-    *(.sdata*)
-  }
-  _edata  =  .;
-  PROVIDE (edata = .);
-
-  . = .;
-
-  . = ALIGN(4);
-  .u_boot_list : {
-	KEEP(*(SORT(.u_boot_list*)));
-  }
-
-  . = .;
-  __start___ex_table = .;
-  __ex_table : { *(__ex_table) }
-  __stop___ex_table = .;
-
-  . = ALIGN(256);
-  __init_begin = .;
-  .text.init : { *(.text.init) }
-  .data.init : { *(.data.init) }
-  . = ALIGN(256);
-  __init_end = .;
-
-  __bss_start = .;
-  .bss (NOLOAD)      :
-  {
-   _sbss = .;
-   *(.bss*)
-   *(.sbss*)
-   *(COMMON)
-   . = ALIGN(4);
-   _ebss = .;
-  }
-  __bss_end = . ;
-  PROVIDE (end = .);
-}
diff --git a/board/ids8247/Makefile b/board/ids8247/Makefile
index b2009e6eb1..99c47b6697 100644
--- a/board/ids8247/Makefile
+++ b/board/ids8247/Makefile
@@ -8,24 +8,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	= $(BOARD).o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	= ids8247.o
diff --git a/board/ifm/ac14xx/Makefile b/board/ifm/ac14xx/Makefile
index f78fe13d35..55def60417 100644
--- a/board/ifm/ac14xx/Makefile
+++ b/board/ifm/ac14xx/Makefile
@@ -4,25 +4,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS-y	:= $(BOARD).o
-
-COBJS	:= $(COBJS-y)
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	:= ac14xx.o
diff --git a/board/ifm/o2dnt2/Makefile b/board/ifm/o2dnt2/Makefile
index 1dd3fe9555..64d6ba8c55 100644
--- a/board/ifm/o2dnt2/Makefile
+++ b/board/ifm/o2dnt2/Makefile
@@ -5,24 +5,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS-y	:= $(BOARD).o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS-y))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	:= o2dnt2.o
diff --git a/board/imgtec/malta/Makefile b/board/imgtec/malta/Makefile
new file mode 100644
index 0000000000..19dd3a3c3b
--- /dev/null
+++ b/board/imgtec/malta/Makefile
@@ -0,0 +1,10 @@
+#
+# (C) Copyright 2003-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y	= malta.o
+obj-y	+= lowlevel_init.o
+obj-y	+= superio.o
diff --git a/board/imgtec/malta/flash-malta-boot.tcl b/board/imgtec/malta/flash-malta-boot.tcl
new file mode 100644
index 0000000000..0eedf07ace
--- /dev/null
+++ b/board/imgtec/malta/flash-malta-boot.tcl
@@ -0,0 +1,40 @@
+#
+# Copyright (C) 2013 Imagination Technologies
+#
+# Programs a MIPS Malta boot flash with a flat binary image.
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+proc flash-boot { binfile } {
+  puts "flash monitor binary $binfile"
+  config Coherent on
+  config CoherencyDuringLoad on
+
+  if {[endian]=="big"} {
+    puts "CPU in BE mode"
+    flash device sharp_16x32_be;
+  } else {
+    puts "CPU in LE mode"
+    flash device sharp_16x32;
+  }
+
+  flash clear all;
+  flash set 0xBE000000..0xBE0FFFFF
+  flash erase sector 0xbe000000;
+  flash erase sector 0xbe020000;
+  flash erase sector 0xbe040000;
+  flash erase sector 0xbe060000;
+  flash erase sector 0xbe080000;
+  flash erase sector 0xbe0a0000;
+  flash erase sector 0xbe0c0000;
+  flash erase sector 0xbe0e0000;
+  puts "finished erasing boot flash";
+
+  puts "programming flash, please be patient"
+  load bin 0xbe000000 $binfile size4
+
+  flash clear all
+  config CoherencyDuringLoad off
+  puts "finished programming boot flash";
+}
diff --git a/board/imgtec/malta/lowlevel_init.S b/board/imgtec/malta/lowlevel_init.S
new file mode 100644
index 0000000000..ae09c27d07
--- /dev/null
+++ b/board/imgtec/malta/lowlevel_init.S
@@ -0,0 +1,238 @@
+/*
+ * Copyright (C) 2013 Gabor Juhos <juhosg@openwrt.org>
+ *
+ * SPDX-License-Identifier:	GPL-2.0
+ */
+
+#include <config.h>
+#include <gt64120.h>
+#include <msc01.h>
+#include <pci.h>
+
+#include <asm/addrspace.h>
+#include <asm/regdef.h>
+#include <asm/malta.h>
+#include <asm/mipsregs.h>
+
+#ifdef CONFIG_SYS_BIG_ENDIAN
+#define CPU_TO_GT32(_x)		((_x))
+#else
+#define CPU_TO_GT32(_x) (					\
+	(((_x) & 0xff) << 24) | (((_x) & 0xff00) << 8) |	\
+	(((_x) & 0xff0000) >> 8) | (((_x) & 0xff000000) >> 24))
+#endif
+
+	.text
+	.set noreorder
+	.set mips32
+
+	.globl	lowlevel_init
+lowlevel_init:
+	/* disable any L2 cache for now */
+	sync
+	mfc0	t0, CP0_CONFIG, 2
+	ori	t0, t0, 0x1 << 12
+	mtc0	t0, CP0_CONFIG, 2
+
+	/* detect the core card */
+	li	t0, KSEG1ADDR(MALTA_REVISION)
+	lw	t0, 0(t0)
+	srl	t0, t0, MALTA_REVISION_CORID_SHF
+	andi	t0, t0, (MALTA_REVISION_CORID_MSK >> \
+			 MALTA_REVISION_CORID_SHF)
+
+	/* core cards using the gt64120 system controller */
+	li	t1, MALTA_REVISION_CORID_CORE_LV
+	beq	t0, t1, _gt64120
+
+	/* core cards using the MSC01 system controller */
+	 li	t1, MALTA_REVISION_CORID_CORE_FPGA6
+	beq	t0, t1, _msc01
+	 nop
+
+	/* unknown system controller */
+	b	.
+	 nop
+
+	/*
+	 * Load BAR registers of GT64120 as done by YAMON
+	 *
+	 * based on a patch sent by Antony Pavlov <antonynpavlov@gmail.com>
+	 * to the barebox mailing list.
+	 * The subject of the original patch:
+	 *   'MIPS: qemu-malta: add YAMON-style GT64120 memory map'
+	 * URL:
+	 * http://www.mail-archive.com/barebox@lists.infradead.org/msg06128.html
+	 *
+	 * based on write_bootloader() in qemu.git/hw/mips_malta.c
+	 * see GT64120 manual and qemu.git/hw/gt64xxx.c for details
+	 */
+_gt64120:
+	/* move GT64120 registers from 0x14000000 to 0x1be00000 */
+	li	t1, KSEG1ADDR(GT_DEF_BASE)
+	li	t0, CPU_TO_GT32(0xdf000000)
+	sw	t0, GT_ISD_OFS(t1)
+
+	/* setup MEM-to-PCI0 mapping */
+	li	t1, KSEG1ADDR(MALTA_GT_BASE)
+
+	/* setup PCI0 io window to 0x18000000-0x181fffff */
+	li	t0, CPU_TO_GT32(0xc0000000)
+	sw	t0, GT_PCI0IOLD_OFS(t1)
+	li	t0, CPU_TO_GT32(0x40000000)
+	sw	t0, GT_PCI0IOHD_OFS(t1)
+
+	/* setup PCI0 mem windows */
+	li	t0, CPU_TO_GT32(0x80000000)
+	sw	t0, GT_PCI0M0LD_OFS(t1)
+	li	t0, CPU_TO_GT32(0x3f000000)
+	sw	t0, GT_PCI0M0HD_OFS(t1)
+
+	li	t0, CPU_TO_GT32(0xc1000000)
+	sw	t0, GT_PCI0M1LD_OFS(t1)
+	li	t0, CPU_TO_GT32(0x5e000000)
+	sw	t0, GT_PCI0M1HD_OFS(t1)
+
+	jr	ra
+	 nop
+
+	/*
+	 *
+	 */
+_msc01:
+	/* setup peripheral bus controller clock divide */
+	li	t0, KSEG1ADDR(MALTA_MSC01_PBC_BASE)
+	li	t1, 0x1 << MSC01_PBC_CLKCFG_SHF
+	sw	t1, MSC01_PBC_CLKCFG_OFS(t0)
+
+	/* tweak peripheral bus controller timings */
+	li	t1, (0x1 << MSC01_PBC_CS0TIM_CDT_SHF) | \
+		    (0x1 << MSC01_PBC_CS0TIM_CAT_SHF)
+	sw	t1, MSC01_PBC_CS0TIM_OFS(t0)
+	li	t1, (0x0 << MSC01_PBC_CS0RW_RDT_SHF) | \
+		    (0x2 << MSC01_PBC_CS0RW_RAT_SHF) | \
+		    (0x0 << MSC01_PBC_CS0RW_WDT_SHF) | \
+		    (0x2 << MSC01_PBC_CS0RW_WAT_SHF)
+	sw	t1, MSC01_PBC_CS0RW_OFS(t0)
+	lw	t1, MSC01_PBC_CS0CFG_OFS(t0)
+	li	t2, MSC01_PBC_CS0CFG_DTYP_MSK
+	and	t1, t2
+	ori	t1, (0x0 << MSC01_PBC_CS0CFG_ADM_SHF) | \
+		    (0x3 << MSC01_PBC_CS0CFG_WSIDLE_SHF) | \
+		    (0x10 << MSC01_PBC_CS0CFG_WS_SHF)
+	sw	t1, MSC01_PBC_CS0CFG_OFS(t0)
+
+	/* setup basic address decode */
+	li	t0, KSEG1ADDR(MALTA_MSC01_BIU_BASE)
+	li	t1, 0x0
+	li	t2, -CONFIG_SYS_MEM_SIZE
+	sw	t1, MSC01_BIU_MCBAS1L_OFS(t0)
+	sw	t2, MSC01_BIU_MCMSK1L_OFS(t0)
+	sw	t1, MSC01_BIU_MCBAS2L_OFS(t0)
+	sw	t2, MSC01_BIU_MCMSK2L_OFS(t0)
+
+	/* initialise IP1 - unused */
+	li	t1, MALTA_MSC01_IP1_BASE
+	li	t2, -MALTA_MSC01_IP1_SIZE
+	sw	t1, MSC01_BIU_IP1BAS1L_OFS(t0)
+	sw	t2, MSC01_BIU_IP1MSK1L_OFS(t0)
+	sw	t1, MSC01_BIU_IP1BAS2L_OFS(t0)
+	sw	t2, MSC01_BIU_IP1MSK2L_OFS(t0)
+
+	/* initialise IP2 - PCI */
+	li	t1, MALTA_MSC01_IP2_BASE1
+	li	t2, -MALTA_MSC01_IP2_SIZE1
+	sw	t1, MSC01_BIU_IP2BAS1L_OFS(t0)
+	sw	t2, MSC01_BIU_IP2MSK1L_OFS(t0)
+	li	t1, MALTA_MSC01_IP2_BASE2
+	li	t2, -MALTA_MSC01_IP2_SIZE2
+	sw	t1, MSC01_BIU_IP2BAS2L_OFS(t0)
+	sw	t2, MSC01_BIU_IP2MSK2L_OFS(t0)
+
+	/* initialise IP3 - peripheral bus controller */
+	li	t1, MALTA_MSC01_IP3_BASE
+	li	t2, -MALTA_MSC01_IP3_SIZE
+	sw	t1, MSC01_BIU_IP3BAS1L_OFS(t0)
+	sw	t2, MSC01_BIU_IP3MSK1L_OFS(t0)
+	sw	t1, MSC01_BIU_IP3BAS2L_OFS(t0)
+	sw	t2, MSC01_BIU_IP3MSK2L_OFS(t0)
+
+	/* setup PCI memory */
+	li	t0, KSEG1ADDR(MALTA_MSC01_PCI_BASE)
+	li	t1, MALTA_MSC01_PCIMEM_BASE
+	li	t2, (-MALTA_MSC01_PCIMEM_SIZE) & MSC01_PCI_SC2PMMSKL_MSK_MSK
+	li	t3, MALTA_MSC01_PCIMEM_MAP
+	sw	t1, MSC01_PCI_SC2PMBASL_OFS(t0)
+	sw	t2, MSC01_PCI_SC2PMMSKL_OFS(t0)
+	sw	t3, MSC01_PCI_SC2PMMAPL_OFS(t0)
+
+	/* setup PCI I/O */
+	li	t1, MALTA_MSC01_PCIIO_BASE
+	li	t2, (-MALTA_MSC01_PCIIO_SIZE) & MSC01_PCI_SC2PIOMSKL_MSK_MSK
+	li	t3, MALTA_MSC01_PCIIO_MAP
+	sw	t1, MSC01_PCI_SC2PIOBASL_OFS(t0)
+	sw	t2, MSC01_PCI_SC2PIOMSKL_OFS(t0)
+	sw	t3, MSC01_PCI_SC2PIOMAPL_OFS(t0)
+
+	/* setup PCI_BAR0 memory window */
+	li	t1, -CONFIG_SYS_MEM_SIZE
+	sw	t1, MSC01_PCI_BAR0_OFS(t0)
+
+	/* setup PCI to SysCon/CPU translation */
+	sw	t1, MSC01_PCI_P2SCMSKL_OFS(t0)
+	sw	zero, MSC01_PCI_P2SCMAPL_OFS(t0)
+
+	/* setup PCI vendor & device IDs */
+	li	t1, (PCI_VENDOR_ID_MIPS << MSC01_PCI_HEAD0_VENDORID_SHF) | \
+		    (PCI_DEVICE_ID_MIPS_MSC01 << MSC01_PCI_HEAD0_DEVICEID_SHF)
+	sw	t1, MSC01_PCI_HEAD0_OFS(t0)
+
+	/* setup PCI subsystem vendor & device IDs */
+	sw	t1, MSC01_PCI_HEAD11_OFS(t0)
+
+	/* setup PCI class, revision */
+	li	t1, (PCI_CLASS_BRIDGE_HOST << MSC01_PCI_HEAD2_CLASS_SHF) | \
+		    (0x1 << MSC01_PCI_HEAD2_REV_SHF)
+	sw	t1, MSC01_PCI_HEAD2_OFS(t0)
+
+	/* ensure a sane setup */
+	sw	zero, MSC01_PCI_HEAD3_OFS(t0)
+	sw	zero, MSC01_PCI_HEAD4_OFS(t0)
+	sw	zero, MSC01_PCI_HEAD5_OFS(t0)
+	sw	zero, MSC01_PCI_HEAD6_OFS(t0)
+	sw	zero, MSC01_PCI_HEAD7_OFS(t0)
+	sw	zero, MSC01_PCI_HEAD8_OFS(t0)
+	sw	zero, MSC01_PCI_HEAD9_OFS(t0)
+	sw	zero, MSC01_PCI_HEAD10_OFS(t0)
+	sw	zero, MSC01_PCI_HEAD12_OFS(t0)
+	sw	zero, MSC01_PCI_HEAD13_OFS(t0)
+	sw	zero, MSC01_PCI_HEAD14_OFS(t0)
+	sw	zero, MSC01_PCI_HEAD15_OFS(t0)
+
+	/* setup PCI command register */
+	li	t1, (PCI_COMMAND_FAST_BACK | \
+		     PCI_COMMAND_SERR | \
+		     PCI_COMMAND_PARITY | \
+		     PCI_COMMAND_MASTER | \
+		     PCI_COMMAND_MEMORY)
+	sw	t1, MSC01_PCI_HEAD1_OFS(t0)
+
+	/* setup PCI byte swapping */
+#ifdef CONFIG_SYS_BIG_ENDIAN
+	li	t1, (0x1 << MSC01_PCI_SWAP_BAR0_BSWAP_SHF) | \
+		    (0x1 << MSC01_PCI_SWAP_IO_BSWAP_SHF)
+	sw	t1, MSC01_PCI_SWAP_OFS(t0)
+#else
+	sw	zero, MSC01_PCI_SWAP_OFS(t0)
+#endif
+
+	/* enable PCI host configuration cycles */
+	lw	t1, MSC01_PCI_CFG_OFS(t0)
+	li	t2, MSC01_PCI_CFG_RA_MSK | \
+		    MSC01_PCI_CFG_G_MSK | \
+		    MSC01_PCI_CFG_EN_MSK
+	or	t1, t1, t2
+	sw	t1, MSC01_PCI_CFG_OFS(t0)
+
+	jr	ra
+	 nop
diff --git a/board/imgtec/malta/malta.c b/board/imgtec/malta/malta.c
new file mode 100644
index 0000000000..d363e49919
--- /dev/null
+++ b/board/imgtec/malta/malta.c
@@ -0,0 +1,220 @@
+/*
+ * Copyright (C) 2013 Gabor Juhos <juhosg@openwrt.org>
+ * Copyright (C) 2013 Imagination Technologies
+ *
+ * SPDX-License-Identifier:	GPL-2.0
+ */
+
+#include <common.h>
+#include <netdev.h>
+#include <pci.h>
+#include <pci_gt64120.h>
+#include <pci_msc01.h>
+#include <rtc.h>
+#include <serial.h>
+
+#include <asm/addrspace.h>
+#include <asm/io.h>
+#include <asm/malta.h>
+
+#include "superio.h"
+
+enum core_card {
+	CORE_UNKNOWN,
+	CORE_LV,
+	CORE_FPGA6,
+};
+
+enum sys_con {
+	SYSCON_UNKNOWN,
+	SYSCON_GT64120,
+	SYSCON_MSC01,
+};
+
+static void malta_lcd_puts(const char *str)
+{
+	int i;
+	void *reg = (void *)CKSEG1ADDR(MALTA_ASCIIPOS0);
+
+	/* print up to 8 characters of the string */
+	for (i = 0; i < min(strlen(str), 8); i++) {
+		__raw_writel(str[i], reg);
+		reg += MALTA_ASCIIPOS1 - MALTA_ASCIIPOS0;
+	}
+
+	/* fill the rest of the display with spaces */
+	for (; i < 8; i++) {
+		__raw_writel(' ', reg);
+		reg += MALTA_ASCIIPOS1 - MALTA_ASCIIPOS0;
+	}
+}
+
+static enum core_card malta_core_card(void)
+{
+	u32 corid, rev;
+
+	rev = __raw_readl(CKSEG1ADDR(MALTA_REVISION));
+	corid = (rev & MALTA_REVISION_CORID_MSK) >> MALTA_REVISION_CORID_SHF;
+
+	switch (corid) {
+	case MALTA_REVISION_CORID_CORE_LV:
+		return CORE_LV;
+
+	case MALTA_REVISION_CORID_CORE_FPGA6:
+		return CORE_FPGA6;
+
+	default:
+		return CORE_UNKNOWN;
+	}
+}
+
+static enum sys_con malta_sys_con(void)
+{
+	switch (malta_core_card()) {
+	case CORE_LV:
+		return SYSCON_GT64120;
+
+	case CORE_FPGA6:
+		return SYSCON_MSC01;
+
+	default:
+		return SYSCON_UNKNOWN;
+	}
+}
+
+phys_size_t initdram(int board_type)
+{
+	return CONFIG_SYS_MEM_SIZE;
+}
+
+int checkboard(void)
+{
+	enum core_card core;
+
+	malta_lcd_puts("U-boot");
+	puts("Board: MIPS Malta");
+
+	core = malta_core_card();
+	switch (core) {
+	case CORE_LV:
+		puts(" CoreLV");
+		break;
+
+	case CORE_FPGA6:
+		puts(" CoreFPGA6");
+		break;
+
+	default:
+		puts(" CoreUnknown");
+	}
+
+	putc('\n');
+	return 0;
+}
+
+int board_eth_init(bd_t *bis)
+{
+	return pci_eth_init(bis);
+}
+
+void _machine_restart(void)
+{
+	void __iomem *reset_base;
+
+	reset_base = (void __iomem *)CKSEG1ADDR(MALTA_RESET_BASE);
+	__raw_writel(GORESET, reset_base);
+}
+
+int board_early_init_f(void)
+{
+	void *io_base;
+
+	/* choose correct PCI I/O base */
+	switch (malta_sys_con()) {
+	case SYSCON_GT64120:
+		io_base = (void *)CKSEG1ADDR(MALTA_GT_PCIIO_BASE);
+		break;
+
+	case SYSCON_MSC01:
+		io_base = (void *)CKSEG1ADDR(MALTA_MSC01_PCIIO_BASE);
+		break;
+
+	default:
+		return -1;
+	}
+
+	/* setup FDC37M817 super I/O controller */
+	malta_superio_init(io_base);
+
+	return 0;
+}
+
+int misc_init_r(void)
+{
+	rtc_reset();
+
+	return 0;
+}
+
+struct serial_device *default_serial_console(void)
+{
+	switch (malta_sys_con()) {
+	case SYSCON_GT64120:
+		return &eserial1_device;
+
+	default:
+	case SYSCON_MSC01:
+		return &eserial2_device;
+	}
+}
+
+void pci_init_board(void)
+{
+	pci_dev_t bdf;
+	u32 val32;
+	u8 val8;
+
+	switch (malta_sys_con()) {
+	case SYSCON_GT64120:
+		set_io_port_base(CKSEG1ADDR(MALTA_GT_PCIIO_BASE));
+
+		gt64120_pci_init((void *)CKSEG1ADDR(MALTA_GT_BASE),
+				 0x00000000, 0x00000000, CONFIG_SYS_MEM_SIZE,
+				 0x10000000, 0x10000000, 128 * 1024 * 1024,
+				 0x00000000, 0x00000000, 0x20000);
+		break;
+
+	default:
+	case SYSCON_MSC01:
+		set_io_port_base(CKSEG1ADDR(MALTA_MSC01_PCIIO_BASE));
+
+		msc01_pci_init((void *)CKSEG1ADDR(MALTA_MSC01_PCI_BASE),
+			       0x00000000, 0x00000000, CONFIG_SYS_MEM_SIZE,
+			       MALTA_MSC01_PCIMEM_MAP,
+			       CKSEG1ADDR(MALTA_MSC01_PCIMEM_BASE),
+			       MALTA_MSC01_PCIMEM_SIZE, MALTA_MSC01_PCIIO_MAP,
+			       0x00000000, MALTA_MSC01_PCIIO_SIZE);
+		break;
+	}
+
+	bdf = pci_find_device(PCI_VENDOR_ID_INTEL,
+			      PCI_DEVICE_ID_INTEL_82371AB_0, 0);
+	if (bdf == -1)
+		panic("Failed to find PIIX4 PCI bridge\n");
+
+	/* setup PCI interrupt routing */
+	pci_write_config_byte(bdf, PCI_CFG_PIIX4_PIRQRCA, 10);
+	pci_write_config_byte(bdf, PCI_CFG_PIIX4_PIRQRCB, 10);
+	pci_write_config_byte(bdf, PCI_CFG_PIIX4_PIRQRCC, 11);
+	pci_write_config_byte(bdf, PCI_CFG_PIIX4_PIRQRCD, 11);
+
+	/* mux SERIRQ onto SERIRQ pin */
+	pci_read_config_dword(bdf, PCI_CFG_PIIX4_GENCFG, &val32);
+	val32 |= PCI_CFG_PIIX4_GENCFG_SERIRQ;
+	pci_write_config_dword(bdf, PCI_CFG_PIIX4_GENCFG, val32);
+
+	/* enable SERIRQ - Linux currently depends upon this */
+	pci_read_config_byte(bdf, PCI_CFG_PIIX4_SERIRQC, &val8);
+	val8 |= PCI_CFG_PIIX4_SERIRQC_EN | PCI_CFG_PIIX4_SERIRQC_CONT;
+	pci_write_config_byte(bdf, PCI_CFG_PIIX4_SERIRQC, val8);
+}
diff --git a/board/imgtec/malta/superio.c b/board/imgtec/malta/superio.c
new file mode 100644
index 0000000000..eaa14df39e
--- /dev/null
+++ b/board/imgtec/malta/superio.c
@@ -0,0 +1,63 @@
+/*
+ * Copyright (C) 2013 Imagination Technologies
+ * Author: Paul Burton <paul.burton@imgtec.com>
+ *
+ * Setup code for the FDC37M817 super I/O controller
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+
+#define SIO_CONF_PORT		0x3f0
+#define SIO_DATA_PORT		0x3f1
+
+enum sio_conf_key {
+	SIOCONF_DEVNUM		= 0x07,
+	SIOCONF_ACTIVATE	= 0x30,
+	SIOCONF_ENTER_SETUP	= 0x55,
+	SIOCONF_BASE_HIGH	= 0x60,
+	SIOCONF_BASE_LOW	= 0x61,
+	SIOCONF_PRIMARY_INT	= 0x70,
+	SIOCONF_EXIT_SETUP	= 0xaa,
+	SIOCONF_MODE		= 0xf0,
+};
+
+static struct {
+	u8 key;
+	u8 data;
+} sio_config[] = {
+	/* tty0 */
+	{ SIOCONF_DEVNUM,	0x04 },
+	{ SIOCONF_BASE_HIGH,	0x03 },
+	{ SIOCONF_BASE_LOW,	0xf8 },
+	{ SIOCONF_MODE,		0x02 },
+	{ SIOCONF_PRIMARY_INT,	0x04 },
+	{ SIOCONF_ACTIVATE,	0x01 },
+
+	/* tty1 */
+	{ SIOCONF_DEVNUM,	0x05 },
+	{ SIOCONF_BASE_HIGH,	0x02 },
+	{ SIOCONF_BASE_LOW,	0xf8 },
+	{ SIOCONF_MODE,		0x02 },
+	{ SIOCONF_PRIMARY_INT,	0x03 },
+	{ SIOCONF_ACTIVATE,	0x01 },
+};
+
+void malta_superio_init(void *io_base)
+{
+	unsigned i;
+
+	/* enter config state */
+	writeb(SIOCONF_ENTER_SETUP, io_base + SIO_CONF_PORT);
+
+	/* configure peripherals */
+	for (i = 0; i < ARRAY_SIZE(sio_config); i++) {
+		writeb(sio_config[i].key, io_base + SIO_CONF_PORT);
+		writeb(sio_config[i].data, io_base + SIO_DATA_PORT);
+	}
+
+	/* exit config state */
+	writeb(SIOCONF_EXIT_SETUP, io_base + SIO_CONF_PORT);
+}
diff --git a/board/imgtec/malta/superio.h b/board/imgtec/malta/superio.h
new file mode 100644
index 0000000000..1450da56dd
--- /dev/null
+++ b/board/imgtec/malta/superio.h
@@ -0,0 +1,15 @@
+/*
+ * Copyright (C) 2013 Imagination Technologies
+ * Author: Paul Burton <paul.burton@imgtec.com>
+ *
+ * Setup code for the FDC37M817 super I/O controller
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __BOARD_MALTA_SUPERIO_H__
+#define __BOARD_MALTA_SUPERIO_H__
+
+extern void malta_superio_init(void *io_base);
+
+#endif /* __BOARD_MALTA_SUPERIO_H__ */
diff --git a/board/imx31_phycore/Makefile b/board/imx31_phycore/Makefile
index 5aaf766a0d..e781c13936 100644
--- a/board/imx31_phycore/Makefile
+++ b/board/imx31_phycore/Makefile
@@ -5,25 +5,5 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	:= imx31_phycore.o
-SOBJS	:= lowlevel_init.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
-	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	:= imx31_phycore.o
+obj-y	+= lowlevel_init.o
diff --git a/board/in-circuit/grasshopper/Makefile b/board/in-circuit/grasshopper/Makefile
index 1930e89cf1..04576358fd 100644
--- a/board/in-circuit/grasshopper/Makefile
+++ b/board/in-circuit/grasshopper/Makefile
@@ -7,23 +7,4 @@
 #
 # SPDX-License-Identifier:	GPL-2.0+
 
-include $(TOPDIR)/config.mk
-
-LIB     := $(obj)lib$(BOARD).o
-
-COBJS-y += $(BOARD).o
-
-SRCS    := $(COBJS-y:.o=.c)
-OBJS    := $(addprefix $(obj),$(COBJS-y))
-
-$(LIB): $(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y += grasshopper.o
diff --git a/board/incaip/Makefile b/board/incaip/Makefile
index ed7370f9a6..602d30ecee 100644
--- a/board/incaip/Makefile
+++ b/board/incaip/Makefile
@@ -5,25 +5,5 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	= $(BOARD).o flash.o
-SOBJS	= lowlevel_init.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
-	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	= incaip.o flash.o
+obj-y	+= lowlevel_init.o
diff --git a/board/inka4x0/Makefile b/board/inka4x0/Makefile
index 14ddfa5ebf..c9a3540799 100644
--- a/board/inka4x0/Makefile
+++ b/board/inka4x0/Makefile
@@ -5,24 +5,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	:= $(BOARD).o inkadiag.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	:= inka4x0.o inkadiag.o
diff --git a/board/inka4x0/hyb25d512160bf-5.h b/board/inka4x0/hyb25d512160bf-5.h
deleted file mode 100644
index f16f450d01..0000000000
--- a/board/inka4x0/hyb25d512160bf-5.h
+++ /dev/null
@@ -1,16 +0,0 @@
-/*
- * Copyright (C) 2007 Semihalf
- * Written by Marian Balakowicz <m8@semihalf.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#define SDRAM_DDR	1		/* is DDR */
-
-/* Settings for XLB = 132 MHz */
-#define SDRAM_MODE	0x018D0000
-#define SDRAM_EMODE	0x40090000
-#define SDRAM_CONTROL	0x714F0F00
-#define SDRAM_CONFIG1	0x73711930
-#define SDRAM_CONFIG2	0x46770000
-#define SDRAM_TAPDELAY	0x10000000
diff --git a/board/intercontrol/digsy_mtc/Makefile b/board/intercontrol/digsy_mtc/Makefile
index 877be48d61..44b7c0ae43 100644
--- a/board/intercontrol/digsy_mtc/Makefile
+++ b/board/intercontrol/digsy_mtc/Makefile
@@ -1,27 +1,6 @@
-
 #
 # Author: Grzegorz Bernacki, Semihalf, gjb@semihalf.com
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS-y	:= $(BOARD).o cmd_mtc.o
-COBJS-$(CONFIG_VIDEO) += cmd_disp.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS-y))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	:= digsy_mtc.o cmd_mtc.o
+obj-$(CONFIG_VIDEO) += cmd_disp.o
diff --git a/board/iomega/iconnect/Makefile b/board/iomega/iconnect/Makefile
index 8809c46bb4..65e357ac95 100644
--- a/board/iomega/iconnect/Makefile
+++ b/board/iomega/iconnect/Makefile
@@ -6,24 +6,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	:= iconnect.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
-	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	:= iconnect.o
diff --git a/board/ip04/Makefile b/board/ip04/Makefile
index 1d23b23f49..caba16f199 100644
--- a/board/ip04/Makefile
+++ b/board/ip04/Makefile
@@ -9,24 +9,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS-y	:= $(BOARD).o
-
-SRCS	:= $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS-y))
-SOBJS	:= $(addprefix $(obj),$(SOBJS-y))
-
-$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
-	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	:= ip04.o
diff --git a/board/ip04/config.mk b/board/ip04/config.mk
index ae2ea0b747..ab0fbecab9 100644
--- a/board/ip04/config.mk
+++ b/board/ip04/config.mk
@@ -7,10 +7,6 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-CFLAGS_lib += -O2
-CFLAGS_lib/lzma += -O2
-CFLAGS_lib/zlib += -O2
-
 # Set some default LDR flags based on boot mode.
 LDR_FLAGS-BFIN_BOOT_PARA := --bits 16 --dma 8
 LDR_FLAGS-BFIN_BOOT_UART := --port g --gpio 6
diff --git a/board/ip860/Makefile b/board/ip860/Makefile
index 871865b6ee..3c60006216 100644
--- a/board/ip860/Makefile
+++ b/board/ip860/Makefile
@@ -5,24 +5,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	= $(BOARD).o flash.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	= ip860.o flash.o
diff --git a/board/ipek01/Makefile b/board/ipek01/Makefile
index 3acd06bba7..a786ab2118 100644
--- a/board/ipek01/Makefile
+++ b/board/ipek01/Makefile
@@ -5,24 +5,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	:= $(BOARD).o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	:= ipek01.o
diff --git a/board/iphase4539/Makefile b/board/iphase4539/Makefile
index 52c03198a7..9197b84a80 100644
--- a/board/iphase4539/Makefile
+++ b/board/iphase4539/Makefile
@@ -7,24 +7,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	:= $(BOARD).o flash.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	:= iphase4539.o flash.o
diff --git a/board/isee/igep0033/Makefile b/board/isee/igep0033/Makefile
index 75f1b856d8..fc985b45b6 100644
--- a/board/isee/igep0033/Makefile
+++ b/board/isee/igep0033/Makefile
@@ -6,33 +6,8 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
 ifdef CONFIG_SPL_BUILD
-COBJS	:= mux.o
+obj-y	+= mux.o
 endif
 
-COBJS	+= board.o
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
-	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
-
-clean:
-	rm -f $(SOBJS) $(OBJS)
-
-distclean:	clean
-	rm -f $(LIB) core *.bak $(obj).depend
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	+= board.o
diff --git a/board/isee/igep0033/board.c b/board/isee/igep0033/board.c
index 0b8356dc47..9f8fcf2c1c 100644
--- a/board/isee/igep0033/board.c
+++ b/board/isee/igep0033/board.c
@@ -35,20 +35,16 @@ static const struct ddr_data ddr3_data = {
 	.datawdsratio0 = K4B2G1646EBIH9_WR_DQS,
 	.datafwsratio0 = K4B2G1646EBIH9_PHY_FIFO_WE,
 	.datawrsratio0 = K4B2G1646EBIH9_PHY_WR_DATA,
-	.datadldiff0 = PHY_DLL_LOCK_DIFF,
 };
 
 static const struct cmd_control ddr3_cmd_ctrl_data = {
 	.cmd0csratio = K4B2G1646EBIH9_RATIO,
-	.cmd0dldiff = K4B2G1646EBIH9_DLL_LOCK_DIFF,
 	.cmd0iclkout = K4B2G1646EBIH9_INVERT_CLKOUT,
 
 	.cmd1csratio = K4B2G1646EBIH9_RATIO,
-	.cmd1dldiff = K4B2G1646EBIH9_DLL_LOCK_DIFF,
 	.cmd1iclkout = K4B2G1646EBIH9_INVERT_CLKOUT,
 
 	.cmd2csratio = K4B2G1646EBIH9_RATIO,
-	.cmd2dldiff = K4B2G1646EBIH9_DLL_LOCK_DIFF,
 	.cmd2iclkout = K4B2G1646EBIH9_INVERT_CLKOUT,
 };
 
@@ -81,9 +77,17 @@ void set_mux_conf_regs(void)
 	enable_board_pin_mux();
 }
 
+const struct ctrl_ioregs ioregs = {
+	.cm0ioctl		= K4B2G1646EBIH9_IOCTRL_VALUE,
+	.cm1ioctl		= K4B2G1646EBIH9_IOCTRL_VALUE,
+	.cm2ioctl		= K4B2G1646EBIH9_IOCTRL_VALUE,
+	.dt0ioctl		= K4B2G1646EBIH9_IOCTRL_VALUE,
+	.dt1ioctl		= K4B2G1646EBIH9_IOCTRL_VALUE,
+};
+
 void sdram_init(void)
 {
-	config_ddr(400, K4B2G1646EBIH9_IOCTRL_VALUE, &ddr3_data,
+	config_ddr(400, &ioregs, &ddr3_data,
 		   &ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0);
 }
 #endif
@@ -112,7 +116,7 @@ static struct cpsw_slave_data cpsw_slaves[] = {
 	{
 		.slave_reg_ofs	= 0x208,
 		.sliver_reg_ofs	= 0xd80,
-		.phy_id		= 0,
+		.phy_addr	= 0,
 		.phy_if		= PHY_INTERFACE_MODE_RMII,
 	},
 };
diff --git a/board/isee/igep00x0/Makefile b/board/isee/igep00x0/Makefile
index 9ad0213bc6..68b151c3c5 100644
--- a/board/isee/igep00x0/Makefile
+++ b/board/isee/igep00x0/Makefile
@@ -5,23 +5,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	:= igep00x0.o
-
-SRCS	:= $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	:= igep00x0.o
diff --git a/board/isee/igep00x0/igep00x0.c b/board/isee/igep00x0/igep00x0.c
index 7a7500b342..3b2b1f15b8 100644
--- a/board/isee/igep00x0/igep00x0.c
+++ b/board/isee/igep00x0/igep00x0.c
@@ -8,7 +8,6 @@
 #include <twl4030.h>
 #include <netdev.h>
 #include <asm/gpio.h>
-#include <asm/omap_gpmc.h>
 #include <asm/io.h>
 #include <asm/arch/mem.h>
 #include <asm/arch/mmc_host_def.h>
diff --git a/board/ispan/Makefile b/board/ispan/Makefile
index 07fa3f3a2f..39931fdfd6 100644
--- a/board/ispan/Makefile
+++ b/board/ispan/Makefile
@@ -8,24 +8,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	:= $(BOARD).o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	:= ispan.o
diff --git a/board/ivm/Makefile b/board/ivm/Makefile
index 871865b6ee..e53a276d4d 100644
--- a/board/ivm/Makefile
+++ b/board/ivm/Makefile
@@ -5,24 +5,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	= $(BOARD).o flash.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	= ivm.o flash.o
diff --git a/board/jornada/Makefile b/board/jornada/Makefile
index 57cc460991..6a6fbf3551 100644
--- a/board/jornada/Makefile
+++ b/board/jornada/Makefile
@@ -7,25 +7,5 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	:= jornada.o
-SOBJS	:= setup.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
-	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	:= jornada.o
+obj-y	+= setup.o
diff --git a/board/jse/Makefile b/board/jse/Makefile
index c891040dc9..feac3a8834 100644
--- a/board/jse/Makefile
+++ b/board/jse/Makefile
@@ -8,25 +8,5 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	= $(BOARD).o sdram.o flash.o host_bridge.o
-SOBJS	= init.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(OBJS) $(SOBJS)
-	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	= jse.o sdram.o flash.o host_bridge.o
+obj-y	+= init.o
diff --git a/board/jupiter/Makefile b/board/jupiter/Makefile
index ea0b9b4d3a..4d3ef9ed7a 100644
--- a/board/jupiter/Makefile
+++ b/board/jupiter/Makefile
@@ -1,4 +1,3 @@
-
 #
 # (C) Copyright 2003-2006
 # Wolfgang Denk, DENX Software Engineering, wd@denx.de.
@@ -6,24 +5,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	:= $(BOARD).o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	:= jupiter.o
diff --git a/board/karo/tk71/Makefile b/board/karo/tk71/Makefile
index f23b56d878..0e0df770f7 100644
--- a/board/karo/tk71/Makefile
+++ b/board/karo/tk71/Makefile
@@ -6,24 +6,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	:= tk71.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
-	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	:= tk71.o
diff --git a/board/karo/tx25/Makefile b/board/karo/tx25/Makefile
index 257cdd21e4..add5dd3669 100644
--- a/board/karo/tx25/Makefile
+++ b/board/karo/tx25/Makefile
@@ -5,26 +5,7 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
 ifdef CONFIG_SPL_BUILD
-SOBJS	:= lowlevel_init.o
+obj-y	+= lowlevel_init.o
 endif
-COBJS	:= tx25.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
-	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
-
-#########################################################################
-
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	+= tx25.o
diff --git a/board/keymile/common/common.c b/board/keymile/common/common.c
index 136b2dee12..f941e44e83 100644
--- a/board/keymile/common/common.c
+++ b/board/keymile/common/common.c
@@ -24,10 +24,6 @@
 #include "common.h"
 #include <i2c.h>
 
-#if !defined(CONFIG_MPC83xx)
-static void i2c_write_start_seq(void);
-#endif
-
 DECLARE_GLOBAL_DATA_PTR;
 
 /*
@@ -78,7 +74,6 @@ int set_km_env(void)
 }
 
 #if defined(CONFIG_SYS_I2C_INIT_BOARD)
-#if !defined(CONFIG_MPC83xx)
 static void i2c_write_start_seq(void)
 {
 	set_sda(1);
@@ -101,21 +96,6 @@ static void i2c_write_start_seq(void)
  */
 int i2c_make_abort(void)
 {
-
-#if defined(CONFIG_HARD_I2C) && !defined(MACH_TYPE_KM_KIRKWOOD)
-	immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
-	i2c8260_t *i2c	= (i2c8260_t *)&immap->im_i2c;
-
-	/*
-	 * disable I2C controller first, otherwhise it thinks we want to
-	 * talk to the slave port...
-	 */
-	clrbits_8(&i2c->i2c_i2mod, 0x01);
-
-	/* Set the PortPins to GPIO */
-	setports(1);
-#endif
-
 	int	scl_state = 0;
 	int	sda_state = 0;
 	int	i = 0;
@@ -148,13 +128,8 @@ int i2c_make_abort(void)
 	set_sda(1);
 	get_sda();
 
-#if defined(CONFIG_HARD_I2C)
-	/* Set the PortPins back to use for I2C */
-	setports(0);
-#endif
 	return ret;
 }
-#endif
 
 /**
  * i2c_init_board - reset i2c bus. When the board is powercycled during a
@@ -167,6 +142,7 @@ void i2c_init_board(void)
 }
 #endif
 
+#if defined(CONFIG_KM_COMMON_ETH_INIT)
 int board_eth_init(bd_t *bis)
 {
 	if (ethernet_present())
@@ -174,6 +150,7 @@ int board_eth_init(bd_t *bis)
 
 	return -1;
 }
+#endif
 
 /*
  * do_setboardid command
diff --git a/board/keymile/km82xx/Makefile b/board/keymile/km82xx/Makefile
index bc428dff8a..20f193ab1d 100644
--- a/board/keymile/km82xx/Makefile
+++ b/board/keymile/km82xx/Makefile
@@ -5,27 +5,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-ifneq ($(OBJTREE),$(SRCTREE))
-$(shell mkdir -p $(obj)../common)
-endif
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	:= $(BOARD).o ../common/common.o ../common/ivm.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	:= km82xx.o ../common/common.o ../common/ivm.o
diff --git a/board/keymile/km83xx/Makefile b/board/keymile/km83xx/Makefile
index 073a7838d1..6c3268853e 100644
--- a/board/keymile/km83xx/Makefile
+++ b/board/keymile/km83xx/Makefile
@@ -5,27 +5,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-ifneq ($(OBJTREE),$(SRCTREE))
-$(shell mkdir -p $(obj)../common)
-endif
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	+= $(BOARD).o ../common/common.o ../common/ivm.o $(BOARD)_i2c.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	+= km83xx.o ../common/common.o ../common/ivm.o km83xx_i2c.o
diff --git a/board/keymile/km_arm/Makefile b/board/keymile/km_arm/Makefile
index 0f2018d734..a17d8d963a 100644
--- a/board/keymile/km_arm/Makefile
+++ b/board/keymile/km_arm/Makefile
@@ -6,31 +6,8 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-ifneq ($(OBJTREE),$(SRCTREE))
-$(shell mkdir -p $(obj)../common)
-endif
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	:= $(BOARD).o ../common/common.o ../common/ivm.o
+obj-y	:= km_arm.o ../common/common.o ../common/ivm.o
 
 ifdef CONFIG_KM_FPGA_CONFIG
-COBJS	+= fpga_config.o
+obj-y	+= fpga_config.o
 endif
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
-	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
diff --git a/board/keymile/km_arm/fpga_config.c b/board/keymile/km_arm/fpga_config.c
index cbfc7d2175..51a3cfe647 100644
--- a/board/keymile/km_arm/fpga_config.c
+++ b/board/keymile/km_arm/fpga_config.c
@@ -189,6 +189,31 @@ int wait_for_fpga_config(void)
 	return 0;
 }
 
+#if defined(KM_PCIE_RESET_MPP7)
+
+#define KM_PEX_RST_GPIO_PIN	7
+int fpga_reset(void)
+{
+	if (!check_boco2()) {
+		/* we do not have BOCO2, this is not really used */
+		return 0;
+	}
+
+	printf("PCIe reset through GPIO7: ");
+	/* apply PCIe reset via GPIO */
+	kw_gpio_set_valid(KM_PEX_RST_GPIO_PIN, 1);
+	kw_gpio_direction_output(KM_PEX_RST_GPIO_PIN, 1);
+	kw_gpio_set_value(KM_PEX_RST_GPIO_PIN, 0);
+	udelay(1000*10);
+	kw_gpio_set_value(KM_PEX_RST_GPIO_PIN, 1);
+
+	printf(" done\n");
+
+	return 0;
+}
+
+#else
+
 #define PRST1		0x4
 #define PCIE_RST	0x10
 #define TRAFFIC_RST	0x04
@@ -219,6 +244,7 @@ int fpga_reset(void)
 
 	return 0;
 }
+#endif
 
 /* the FPGA was configured, we configure the BOCO2 so that the EEPROM
  * is available from the Bobcat SPI bus */
diff --git a/board/keymile/km_arm/km_arm.c b/board/keymile/km_arm/km_arm.c
index 5620737bf0..35402c800b 100644
--- a/board/keymile/km_arm/km_arm.c
+++ b/board/keymile/km_arm/km_arm.c
@@ -46,7 +46,11 @@ static const u32 kwmpp_config[] = {
 	MPP4_NF_IO6,
 	MPP5_NF_IO7,
 	MPP6_SYSRST_OUTn,
+#if defined(KM_PCIE_RESET_MPP7)
+	MPP7_GPO,
+#else
 	MPP7_PEX_RST_OUTn,
+#endif
 #if defined(CONFIG_SYS_I2C_SOFT)
 	MPP8_GPIO,		/* SDA */
 	MPP9_GPIO,		/* SCL */
@@ -102,7 +106,7 @@ static const u32 kwmpp_config[] = {
 /*
  * Wait for startup OK from mgcoge3ne
  */
-int startup_allowed(void)
+static int startup_allowed(void)
 {
 	unsigned char buf;
 
@@ -164,7 +168,6 @@ static int initialize_unit_leds(void)
 	return 0;
 }
 
-#if defined(CONFIG_BOOTCOUNT_LIMIT)
 static void set_bootcount_addr(void)
 {
 	uchar buf[32];
@@ -173,7 +176,6 @@ static void set_bootcount_addr(void)
 	sprintf((char *)buf, "0x%x", bootcountaddr);
 	setenv("bootcountaddr", (char *)buf);
 }
-#endif
 
 int misc_init_r(void)
 {
@@ -210,9 +212,7 @@ int misc_init_r(void)
 
 	initialize_unit_leds();
 	set_km_env();
-#if defined(CONFIG_BOOTCOUNT_LIMIT)
 	set_bootcount_addr();
-#endif
 	return 0;
 }
 
@@ -322,15 +322,15 @@ void reset_phy(void)
 		return;
 
 	/* RGMII clk transition on data stable */
-	if (!miiphy_read(name, CONFIG_PHY_BASE_ADR, PHY_SPEC_CTRL_REG, &reg))
+	if (miiphy_read(name, CONFIG_PHY_BASE_ADR, PHY_SPEC_CTRL_REG, &reg))
 		printf("Error reading PHY spec ctrl reg\n");
-	if (!miiphy_write(name, CONFIG_PHY_BASE_ADR, PHY_SPEC_CTRL_REG,
-		reg | PHY_RGMII_CLK_STABLE | PHY_CLSA))
+	if (miiphy_write(name, CONFIG_PHY_BASE_ADR, PHY_SPEC_CTRL_REG,
+			 reg | PHY_RGMII_CLK_STABLE | PHY_CLSA))
 		printf("Error writing PHY spec ctrl reg\n");
 
 	/* leds setup */
-	if (!miiphy_write(name, CONFIG_PHY_BASE_ADR, PHY_LED_SEL_REG,
-		PHY_LED0_LINK | PHY_LED1_ACT | PHY_LED2_INT))
+	if (miiphy_write(name, CONFIG_PHY_BASE_ADR, PHY_LED_SEL_REG,
+			 PHY_LED0_LINK | PHY_LED1_ACT | PHY_LED2_INT))
 		printf("Error writing PHY LED reg\n");
 
 	/* reset the phy */
diff --git a/board/keymile/kmp204x/Makefile b/board/keymile/kmp204x/Makefile
new file mode 100644
index 0000000000..c57ca08e14
--- /dev/null
+++ b/board/keymile/kmp204x/Makefile
@@ -0,0 +1,12 @@
+#
+# (C) Copyright 2001-2007
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y	:= kmp204x.o ddr.o eth.o tlb.o pci.o law.o qrio.o \
+	../common/common.o ../common/ivm.o
diff --git a/board/keymile/kmp204x/ddr.c b/board/keymile/kmp204x/ddr.c
new file mode 100644
index 0000000000..34ac6979bd
--- /dev/null
+++ b/board/keymile/kmp204x/ddr.c
@@ -0,0 +1,64 @@
+/*
+ * (C) Copyright 2013 Keymile AG
+ * Valentin Longchamp <valentin.longchamp@keymile.com>
+ *
+ * Copyright 2009-2011 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+  */
+
+#include <common.h>
+#include <i2c.h>
+#include <hwconfig.h>
+#include <asm/mmu.h>
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr_dimm_params.h>
+
+void fsl_ddr_board_options(memctl_options_t *popts,
+				dimm_params_t *pdimm,
+				unsigned int ctrl_num)
+{
+	if (ctrl_num) {
+		printf("Wrong parameter for controller number %d", ctrl_num);
+		return;
+	}
+
+	/* automatic calibration for nb of cycles between read and DQS pre */
+	popts->cpo_override = 0xFF;
+
+	/* 1/2 clk delay between wr command and data strobe */
+	popts->write_data_delay = 4;
+	/* clk lauched 1/2 applied cylcle after address command */
+	popts->clk_adjust = 4;
+	/* 1T timing: command/address held for only 1 cycle */
+	popts->twot_en = 0;
+
+	/* we have only one module, half str should be OK */
+	popts->half_strength_driver_enable = 1;
+
+	/* wrlvl values overriden as recommended by ddr init func */
+	popts->wrlvl_override = 1;
+	popts->wrlvl_sample = 0xf;
+	popts->wrlvl_start = 0x6;
+
+	/* Enable ZQ calibration */
+	popts->zq_en = 1;
+
+	/* DHC_EN =1, ODT = 75 Ohm */
+	popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR_ODT_75ohm;
+}
+
+phys_size_t initdram(int board_type)
+{
+	phys_size_t dram_size = 0;
+
+	puts("Initializing with SPD\n");
+
+	dram_size = fsl_ddr_sdram();
+
+	dram_size = setup_ddr_tlbs(dram_size / 0x100000);
+	dram_size *= 0x100000;
+
+	debug("    DDR: ");
+	return dram_size;
+}
diff --git a/board/keymile/kmp204x/eth.c b/board/keymile/kmp204x/eth.c
new file mode 100644
index 0000000000..a0731055a2
--- /dev/null
+++ b/board/keymile/kmp204x/eth.c
@@ -0,0 +1,71 @@
+/*
+ * (C) Copyright 2013 Keymile AG
+ * Valentin Longchamp <valentin.longchamp@keymile.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <netdev.h>
+#include <fm_eth.h>
+#include <fsl_mdio.h>
+#include <phy.h>
+
+int board_eth_init(bd_t *bis)
+{
+	int ret = 0;
+#ifdef CONFIG_FMAN_ENET
+	struct fsl_pq_mdio_info dtsec_mdio_info;
+
+	printf("Initializing Fman\n");
+
+	dtsec_mdio_info.regs =
+		(struct tsec_mii_mng *)CONFIG_SYS_FM1_DTSEC1_MDIO_ADDR;
+	dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME;
+
+	/* Register the real 1G MDIO bus */
+	fsl_pq_mdio_init(bis, &dtsec_mdio_info);
+
+	/* DTESC1/2 don't have a PHY, they are temporarily disabled
+	 * so that u-boot doesn't try to unsuccessfuly enable them */
+	fm_disable_port(FM1_DTSEC1);
+	fm_disable_port(FM1_DTSEC2);
+
+	/*
+	 * Program RGMII DTSEC5 (FM1 MAC5) on the EC2 physical itf
+	 * This is the debug interface, the only one used in u-boot
+	 */
+	fm_info_set_phy_address(FM1_DTSEC5, CONFIG_SYS_FM1_DTSEC5_PHY_ADDR);
+	fm_info_set_mdio(FM1_DTSEC5,
+			 miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME));
+
+	ret = cpu_eth_init(bis);
+
+	/* reenable DTSEC1/2 for later (kernel) */
+	fm_enable_port(FM1_DTSEC1);
+	fm_enable_port(FM1_DTSEC2);
+#endif
+
+	return ret;
+}
+
+#if defined(CONFIG_PHYLIB) && defined(CONFIG_PHY_MARVELL)
+
+#define mv88E1118_PAGE_REG	22
+
+int board_phy_config(struct phy_device *phydev)
+{
+	if (phydev->addr == CONFIG_SYS_FM1_DTSEC5_PHY_ADDR) {
+		/* driver config is good */
+		if (phydev->drv->config)
+			phydev->drv->config(phydev);
+
+		/* but we still need to fix the LEDs */
+		phy_write(phydev, MDIO_DEVAD_NONE, mv88E1118_PAGE_REG, 0x0003);
+		phy_write(phydev, MDIO_DEVAD_NONE, 0x10, 0x0840);
+		phy_write(phydev, MDIO_DEVAD_NONE, mv88E1118_PAGE_REG, 0x0000);
+	}
+
+	return 0;
+}
+#endif
diff --git a/board/keymile/kmp204x/kmp204x.c b/board/keymile/kmp204x/kmp204x.c
new file mode 100644
index 0000000000..95a19cdb2c
--- /dev/null
+++ b/board/keymile/kmp204x/kmp204x.c
@@ -0,0 +1,234 @@
+/*
+ * (C) Copyright 2013 Keymile AG
+ * Valentin Longchamp <valentin.longchamp@keymile.com>
+ *
+ * Copyright 2011,2012 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <command.h>
+#include <netdev.h>
+#include <linux/compiler.h>
+#include <asm/mmu.h>
+#include <asm/processor.h>
+#include <asm/cache.h>
+#include <asm/immap_85xx.h>
+#include <asm/fsl_law.h>
+#include <asm/fsl_serdes.h>
+#include <asm/fsl_portals.h>
+#include <asm/fsl_liodn.h>
+#include <fm_eth.h>
+
+#include "../common/common.h"
+#include "kmp204x.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int checkboard(void)
+{
+	printf("Board: Keymile %s\n", CONFIG_KM_BOARD_NAME);
+
+	return 0;
+}
+
+/* I2C deblocking uses the algorithm defined in board/keymile/common/common.c
+ * 2 dedicated QRIO GPIOs externally pull the SCL and SDA lines
+ * For I2C only the low state is activly driven and high state is pulled-up
+ * by a resistor. Therefore the deblock GPIOs are used
+ *  -> as an active output to drive a low state
+ *  -> as an open-drain input to have a pulled-up high state
+ */
+
+/* QRIO GPIOs used for deblocking */
+#define DEBLOCK_PORT1	GPIO_A
+#define DEBLOCK_SCL1	20
+#define DEBLOCK_SDA1	21
+
+/* By default deblock GPIOs are floating */
+static void i2c_deblock_gpio_cfg(void)
+{
+	/* set I2C bus 1 deblocking GPIOs input, but 0 value for open drain */
+	qrio_gpio_direction_input(DEBLOCK_PORT1, DEBLOCK_SCL1);
+	qrio_gpio_direction_input(DEBLOCK_PORT1, DEBLOCK_SDA1);
+
+	qrio_set_gpio(DEBLOCK_PORT1, DEBLOCK_SCL1, 0);
+	qrio_set_gpio(DEBLOCK_PORT1, DEBLOCK_SDA1, 0);
+}
+
+void set_sda(int state)
+{
+	qrio_set_opendrain_gpio(DEBLOCK_PORT1, DEBLOCK_SDA1, state);
+}
+
+void set_scl(int state)
+{
+	qrio_set_opendrain_gpio(DEBLOCK_PORT1, DEBLOCK_SCL1, state);
+}
+
+int get_sda(void)
+{
+	return qrio_get_gpio(DEBLOCK_PORT1, DEBLOCK_SDA1);
+}
+
+int get_scl(void)
+{
+	return qrio_get_gpio(DEBLOCK_PORT1, DEBLOCK_SCL1);
+}
+
+
+#define ZL30158_RST	8
+#define ZL30343_RST	9
+
+int board_early_init_f(void)
+{
+	ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+
+	/* board only uses the DDR_MCK0, so disable the DDR_MCK1/2/3 */
+	setbits_be32(&gur->ddrclkdr, 0x001f000f);
+
+	/* take the Zarlinks out of reset as soon as possible */
+	qrio_prst(ZL30158_RST, false, false);
+	qrio_prst(ZL30343_RST, false, false);
+
+	/* and set their reset to power-up only */
+	qrio_prstcfg(ZL30158_RST, PRSTCFG_POWUP_RST);
+	qrio_prstcfg(ZL30343_RST, PRSTCFG_POWUP_RST);
+
+	return 0;
+}
+
+int board_early_init_r(void)
+{
+	int ret = 0;
+	/* Flush d-cache and invalidate i-cache of any FLASH data */
+	flush_dcache();
+	invalidate_icache();
+
+	set_liodns();
+	setup_portals();
+
+	ret = trigger_fpga_config();
+	if (ret)
+		printf("error triggering PCIe FPGA config\n");
+
+	return ret;
+}
+
+unsigned long get_board_sys_clk(unsigned long dummy)
+{
+	return 66666666;
+}
+
+int misc_init_f(void)
+{
+	/* configure QRIO pis for i2c deblocking */
+	i2c_deblock_gpio_cfg();
+
+	return 0;
+}
+
+#define NUM_SRDS_BANKS	2
+#define PHY_RST		15
+
+int misc_init_r(void)
+{
+	serdes_corenet_t *regs = (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
+	u32 expected[NUM_SRDS_BANKS] = {SRDS_PLLCR0_RFCK_SEL_100,
+		SRDS_PLLCR0_RFCK_SEL_125};
+	unsigned int i;
+
+	/* check SERDES reference clocks */
+	for (i = 0; i < NUM_SRDS_BANKS; i++) {
+		u32 actual = in_be32(&regs->bank[i].pllcr0);
+		actual &= SRDS_PLLCR0_RFCK_SEL_MASK;
+		if (actual != expected[i]) {
+			printf("Warning: SERDES bank %u expects reference \
+			       clock %sMHz, but actual is %sMHz\n", i + 1,
+			       serdes_clock_to_string(expected[i]),
+			       serdes_clock_to_string(actual));
+		}
+	}
+
+	/* take the mgmt eth phy out of reset */
+	qrio_prst(PHY_RST, false, false);
+
+	return 0;
+}
+
+#if defined(CONFIG_HUSH_INIT_VAR)
+int hush_init_var(void)
+{
+	ivm_read_eeprom();
+	return 0;
+}
+#endif
+
+#if defined(CONFIG_LAST_STAGE_INIT)
+int last_stage_init(void)
+{
+	set_km_env();
+	return 0;
+}
+#endif
+
+#ifdef CONFIG_SYS_DPAA_FMAN
+void fdt_fixup_fman_mac_addresses(void *blob)
+{
+	int node, i, ret;
+	char *tmp, *end;
+	unsigned char mac_addr[6];
+
+	/* get the mac addr from env */
+	tmp = getenv("ethaddr");
+	if (!tmp) {
+		printf("ethaddr env variable not defined\n");
+		return;
+	}
+	for (i = 0; i < 6; i++) {
+		mac_addr[i] = tmp ? simple_strtoul(tmp, &end, 16) : 0;
+		if (tmp)
+			tmp = (*end) ? end+1 : end;
+	}
+
+	/* find the correct fdt ethernet path and correct it */
+	node = fdt_path_offset(blob, "/soc/fman/ethernet@e8000");
+	if (node < 0) {
+		printf("no /soc/fman/ethernet path offset\n");
+		return;
+	}
+	ret = fdt_setprop(blob, node, "local-mac-address", &mac_addr, 6);
+	if (ret) {
+		printf("error setting local-mac-address property\n");
+		return;
+	}
+}
+#endif
+
+void ft_board_setup(void *blob, bd_t *bd)
+{
+	phys_addr_t base;
+	phys_size_t size;
+
+	ft_cpu_setup(blob, bd);
+
+	base = getenv_bootm_low();
+	size = getenv_bootm_size();
+
+	fdt_fixup_memory(blob, (u64)base, (u64)size);
+
+#if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB)
+	fdt_fixup_dr_usb(blob, bd);
+#endif
+
+#ifdef CONFIG_PCI
+	pci_of_setup(blob, bd);
+#endif
+
+	fdt_fixup_liodn(blob);
+#ifdef CONFIG_SYS_DPAA_FMAN
+	fdt_fixup_fman_ethernet(blob);
+	fdt_fixup_fman_mac_addresses(blob);
+#endif
+}
diff --git a/board/keymile/kmp204x/kmp204x.h b/board/keymile/kmp204x/kmp204x.h
new file mode 100644
index 0000000000..0267596e4e
--- /dev/null
+++ b/board/keymile/kmp204x/kmp204x.h
@@ -0,0 +1,25 @@
+/*
+ * (C) Copyright 2013 Keymile AG
+ * Valentin Longchamp <valentin.longchamp@keymile.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/* QRIO GPIO ports */
+#define GPIO_A			0x40
+#define GPIO_B			0x60
+
+int qrio_get_gpio(u8 port_off, u8 gpio_nr);
+void qrio_set_opendrain_gpio(u8 port_off, u8 gpio_nr, u8 val);
+void qrio_set_gpio(u8 port_off, u8 gpio_nr, bool value);
+void qrio_gpio_direction_output(u8 port_off, u8 gpio_nr, bool value);
+void qrio_gpio_direction_input(u8 port_off, u8 gpio_nr);
+
+#define PRSTCFG_POWUP_UNIT_CORE_RST	0x0
+#define PRSTCFG_POWUP_UNIT_RST		0x1
+#define PRSTCFG_POWUP_RST		0x3
+
+void qrio_prst(u8 bit, bool en, bool wden);
+void qrio_prstcfg(u8 bit, u8 mode);
+
+void pci_of_setup(void *blob, bd_t *bd);
diff --git a/board/keymile/kmp204x/law.c b/board/keymile/kmp204x/law.c
new file mode 100644
index 0000000000..75d69e8b48
--- /dev/null
+++ b/board/keymile/kmp204x/law.c
@@ -0,0 +1,40 @@
+/*
+ * (C) Copyright 2013 Keymile AG
+ * Valentin Longchamp <valentin.longchamp@keymile.com>
+ *
+ * Copyright 2008-2011 Freescale Semiconductor, Inc.
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/fsl_law.h>
+#include <asm/mmu.h>
+
+struct law_entry law_table[] = {
+#ifdef CONFIG_SYS_BMAN_MEM_PHYS
+	SET_LAW(CONFIG_SYS_BMAN_MEM_PHYS, LAW_SIZE_2M, LAW_TRGT_IF_BMAN),
+#endif
+#ifdef CONFIG_SYS_QMAN_MEM_PHYS
+	SET_LAW(CONFIG_SYS_QMAN_MEM_PHYS, LAW_SIZE_2M, LAW_TRGT_IF_QMAN),
+#endif
+#ifdef CONFIG_SYS_DCSRBAR_PHYS
+	/* Limit DCSR to 32M to access NPC Trace Buffer */
+	SET_LAW(CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_DCSR),
+#endif
+#ifdef CONFIG_SYS_NAND_BASE_PHYS
+	SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_32K, LAW_TRGT_IF_LBC),
+#endif
+	SET_LAW(CONFIG_SYS_QRIO_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_LBC),
+#ifdef CONFIG_SYS_LBAPP1_BASE_PHYS
+	SET_LAW(CONFIG_SYS_LBAPP1_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
+#endif
+#ifdef CONFIG_SYS_LBAPP2_BASE_PHYS
+	SET_LAW(CONFIG_SYS_LBAPP2_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
+#endif
+};
+
+int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/board/keymile/kmp204x/pbi.cfg b/board/keymile/kmp204x/pbi.cfg
new file mode 100644
index 0000000000..9af8bd5b57
--- /dev/null
+++ b/board/keymile/kmp204x/pbi.cfg
@@ -0,0 +1,45 @@
+#
+# Copyright 2012 Freescale Semiconductor, Inc.
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+# Refer docs/README.pblimage for more details about how-to configure
+# and create PBL boot image
+#
+
+#PBI commands
+#Workaround for A-006559 needed for rev 2.0 of P2041 silicon
+#Freescale's errarta sheet suggests it may be done with PBI
+09000010 00000000
+09000014 00000000
+09000018 81d00000
+09021008 0000f000
+09021028 0000f000
+09021048 0000f000
+09021068 0000f000
+09000018 00000000
+#Initialize CPC1 as 1MB SRAM
+09010000 00200400
+09138000 00000000
+091380c0 00000100
+09010100 00000000
+09010104 fff0000b
+09010f00 08000000
+09010000 80000000
+#Configure LAW for CPC1
+09000d00 00000000
+09000d04 fff00000
+09000d08 81000013
+09000010 00000000
+09000014 ff000000
+09000018 81000000
+#Initialize eSPI controller, default configuration is slow for eSPI to
+#load data, this configuration comes from u-boot eSPI driver.
+09110000 80000403
+09110020 27170008
+09110024 00100008
+09110028 00100008
+0911002c 00100008
+#Flush PBL data
+09138000 00000000
+091380c0 00000000
diff --git a/board/keymile/kmp204x/pci.c b/board/keymile/kmp204x/pci.c
new file mode 100644
index 0000000000..a484eb5749
--- /dev/null
+++ b/board/keymile/kmp204x/pci.c
@@ -0,0 +1,120 @@
+/*
+ * (C) Copyright 2013 Keymile AG
+ * Valentin Longchamp <valentin.longchamp@keymile.com>
+ *
+ * Copyright 2007-2011 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <command.h>
+#include <pci.h>
+#include <asm/fsl_pci.h>
+#include <libfdt.h>
+#include <fdt_support.h>
+#include <asm/fsl_serdes.h>
+#include <asm/errno.h>
+
+#include "kmp204x.h"
+
+#define PROM_SEL_L	11
+/* control the PROM_SEL_L signal*/
+static void toggle_fpga_eeprom_bus(bool cpu_own)
+{
+	qrio_gpio_direction_output(GPIO_A, PROM_SEL_L, !cpu_own);
+}
+
+#define CONF_SEL_L	10
+#define FPGA_PROG_L	19
+#define FPGA_DONE	18
+#define FPGA_INIT_L	17
+
+int trigger_fpga_config(void)
+{
+	int ret = 0, init_l;
+	/* approx 10ms */
+	u32 timeout = 10000;
+
+	/* make sure the FPGA_can access the EEPROM */
+	toggle_fpga_eeprom_bus(false);
+
+	/* assert CONF_SEL_L to be able to drive FPGA_PROG_L */
+	qrio_gpio_direction_output(GPIO_A, CONF_SEL_L, 0);
+
+	/* trigger the config start */
+	qrio_gpio_direction_output(GPIO_A, FPGA_PROG_L, 0);
+
+	/* small delay for INIT_L line */
+	udelay(10);
+
+	/* wait for FPGA_INIT to be asserted */
+	do {
+		init_l = qrio_get_gpio(GPIO_A, FPGA_INIT_L);
+		if (timeout-- == 0) {
+			printf("FPGA_INIT timeout\n");
+			ret = -EFAULT;
+			break;
+		}
+		udelay(10);
+	} while (init_l);
+
+	/* deassert FPGA_PROG, config should start */
+	qrio_set_gpio(GPIO_A, FPGA_PROG_L, 1);
+
+	return ret;
+}
+
+/* poll the FPGA_DONE signal and give the EEPROM back to the QorIQ */
+static int wait_for_fpga_config(void)
+{
+	int ret = 0, done;
+	/* approx 5 s */
+	u32 timeout = 500000;
+
+	printf("PCIe FPGA config:");
+	do {
+		done = qrio_get_gpio(GPIO_A, FPGA_DONE);
+		if (timeout-- == 0) {
+			printf(" FPGA_DONE timeout\n");
+			ret = -EFAULT;
+			goto err_out;
+		}
+		udelay(10);
+	} while (!done);
+
+	printf(" done\n");
+
+err_out:
+	/* deactive CONF_SEL and give the CPU conf EEPROM access */
+	qrio_set_gpio(GPIO_A, CONF_SEL_L, 1);
+	toggle_fpga_eeprom_bus(true);
+
+	return ret;
+}
+
+#define PCIE_SW_RST	14
+#define PEXHC_SW_RST	13
+#define HOOPER_SW_RST	12
+
+void pci_init_board(void)
+{
+	/* first wait for the PCIe FPGA to be configured
+	 * it has been triggered earlier in board_early_init_r */
+	int ret = wait_for_fpga_config();
+	if (ret)
+		printf("error finishing PCIe FPGA config\n");
+
+	qrio_prst(PCIE_SW_RST, false, false);
+	qrio_prst(PEXHC_SW_RST, false, false);
+	qrio_prst(HOOPER_SW_RST, false, false);
+	/* Hooper is not direcly PCIe capable */
+	mdelay(50);
+
+	fsl_pcie_init_board(0);
+}
+
+void pci_of_setup(void *blob, bd_t *bd)
+{
+	FT_FSL_PCI_SETUP;
+}
diff --git a/board/keymile/kmp204x/qrio.c b/board/keymile/kmp204x/qrio.c
new file mode 100644
index 0000000000..49f9aa2546
--- /dev/null
+++ b/board/keymile/kmp204x/qrio.c
@@ -0,0 +1,146 @@
+/*
+ * (C) Copyright 2013 Keymile AG
+ * Valentin Longchamp <valentin.longchamp@keymile.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+
+#include "../common/common.h"
+#include "kmp204x.h"
+
+/* QRIO GPIO register offsets */
+#define DIRECT_OFF		0x18
+#define GPRT_OFF		0x1c
+
+int qrio_get_gpio(u8 port_off, u8 gpio_nr)
+{
+	u32 gprt;
+
+	void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE;
+
+	gprt = in_be32(qrio_base + port_off + GPRT_OFF);
+
+	return (gprt >> gpio_nr) & 1U;
+}
+
+void qrio_set_gpio(u8 port_off, u8 gpio_nr, bool value)
+{
+	u32 gprt, mask;
+
+	void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE;
+
+	mask = 1U << gpio_nr;
+
+	gprt = in_be32(qrio_base + port_off + GPRT_OFF);
+	if (value)
+		gprt |= mask;
+	else
+		gprt &= ~mask;
+
+	out_be32(qrio_base + port_off + GPRT_OFF, gprt);
+}
+
+void qrio_gpio_direction_output(u8 port_off, u8 gpio_nr, bool value)
+{
+	u32 direct, mask;
+
+	void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE;
+
+	mask = 1U << gpio_nr;
+
+	direct = in_be32(qrio_base + port_off + DIRECT_OFF);
+	direct |= mask;
+	out_be32(qrio_base + port_off + DIRECT_OFF, direct);
+
+	qrio_set_gpio(port_off, gpio_nr, value);
+}
+
+void qrio_gpio_direction_input(u8 port_off, u8 gpio_nr)
+{
+	u32 direct, mask;
+
+	void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE;
+
+	mask = 1U << gpio_nr;
+
+	direct = in_be32(qrio_base + port_off + DIRECT_OFF);
+	direct &= ~mask;
+	out_be32(qrio_base + port_off + DIRECT_OFF, direct);
+}
+
+void qrio_set_opendrain_gpio(u8 port_off, u8 gpio_nr, u8 val)
+{
+	u32 direct, mask;
+
+	void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE;
+
+	mask = 1U << gpio_nr;
+
+	direct = in_be32(qrio_base + port_off + DIRECT_OFF);
+	if (val == 0)
+		/* set to output -> GPIO drives low */
+		direct |= mask;
+	else
+		/* set to input -> GPIO floating */
+		direct &= ~mask;
+
+	out_be32(qrio_base + port_off + DIRECT_OFF, direct);
+}
+
+#define WDMASK_OFF	0x16
+
+static void qrio_wdmask(u8 bit, bool wden)
+{
+	u16 wdmask;
+	void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE;
+
+	wdmask = in_be16(qrio_base + WDMASK_OFF);
+
+	if (wden)
+		wdmask |= (1 << bit);
+	else
+		wdmask &= ~(1 << bit);
+
+	out_be16(qrio_base + WDMASK_OFF, wdmask);
+}
+
+#define PRST_OFF	0x1a
+
+void qrio_prst(u8 bit, bool en, bool wden)
+{
+	u16 prst;
+	void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE;
+
+	qrio_wdmask(bit, wden);
+
+	prst = in_be16(qrio_base + PRST_OFF);
+
+	if (en)
+		prst &= ~(1 << bit);
+	else
+		prst |= (1 << bit);
+
+	out_be16(qrio_base + PRST_OFF, prst);
+}
+
+#define PRSTCFG_OFF	0x1c
+
+void qrio_prstcfg(u8 bit, u8 mode)
+{
+	u32 prstcfg;
+	u8 i;
+	void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE;
+
+	prstcfg = in_be32(qrio_base + PRSTCFG_OFF);
+
+	for (i = 0; i < 2; i++) {
+		if (mode & (1<<i))
+			set_bit(2*bit+i, &prstcfg);
+		else
+			clear_bit(2*bit+i, &prstcfg);
+	}
+
+	out_be32(qrio_base + PRSTCFG_OFF, prstcfg);
+}
diff --git a/board/keymile/kmp204x/rcw_kmp204x.cfg b/board/keymile/kmp204x/rcw_kmp204x.cfg
new file mode 100644
index 0000000000..2d4c48cb9c
--- /dev/null
+++ b/board/keymile/kmp204x/rcw_kmp204x.cfg
@@ -0,0 +1,11 @@
+#
+# Default RCW for kmp204x boards
+#
+
+#PBL preamble and RCW header
+aa55aa55 010e0100
+#64 bytes RCW data
+14600000 00000000 28200000 00000000
+148E70CF CFC02000 58000000 41000000
+00000000 00000000 00000000 F0428002
+00000000 00000000 00000000 00000000
diff --git a/board/keymile/kmp204x/tlb.c b/board/keymile/kmp204x/tlb.c
new file mode 100644
index 0000000000..d03ca802a4
--- /dev/null
+++ b/board/keymile/kmp204x/tlb.c
@@ -0,0 +1,110 @@
+/*
+ * (C) Copyright 2013 Keymile AG
+ * Valentin Longchamp <valentin.longchamp@keymile.com>
+ *
+ * Copyright 2008-2011 Freescale Semiconductor, Inc.
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/mmu.h>
+
+struct fsl_e_tlb_entry tlb_table[] = {
+	/* TLB 0 - for temp stack in cache */
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR,
+		      CONFIG_SYS_INIT_RAM_ADDR_PHYS,
+		      MAS3_SW|MAS3_SR, 0,
+		      0, 0, BOOKE_PAGESZ_4K, 0),
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
+		      CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024,
+		      MAS3_SW|MAS3_SR, 0,
+		      0, 0, BOOKE_PAGESZ_4K, 0),
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
+		      CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024,
+		      MAS3_SW|MAS3_SR, 0,
+		      0, 0, BOOKE_PAGESZ_4K, 0),
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
+		      CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024,
+		      MAS3_SW|MAS3_SR, 0,
+		      0, 0, BOOKE_PAGESZ_4K, 0),
+	/* TLB 1 */
+	/* *I*G - L3SRAM. When L3 is used as 1M SRAM, the address of the
+	 * SRAM is at 0xfff00000, it covered the 0xfffff000.
+	 */
+	SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 0, BOOKE_PAGESZ_1M, 1),
+
+	/* *I*G* - CCSRBAR */
+	SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
+		      MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 1, BOOKE_PAGESZ_16M, 1),
+	/* QRIO */
+	SET_TLB_ENTRY(1, CONFIG_SYS_QRIO_BASE, CONFIG_SYS_QRIO_BASE_PHYS,
+		      MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 2, BOOKE_PAGESZ_64K, 1),
+	/* *I*G* - PCI1 */
+	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
+		      MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 3, BOOKE_PAGESZ_512M, 1),
+	/* *I*G* - PCI3 */
+	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT, CONFIG_SYS_PCIE3_MEM_PHYS,
+		      MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 4, BOOKE_PAGESZ_512M, 1),
+	/* *I*G* - PCI1&3 I/O */
+	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS,
+		      MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 6, BOOKE_PAGESZ_128K, 1),
+#ifdef CONFIG_SYS_LBAPP1_BASE_PHYS
+	/* LBAPP1 */
+	SET_TLB_ENTRY(1, CONFIG_SYS_LBAPP1_BASE, CONFIG_SYS_LBAPP1_BASE_PHYS,
+		      MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 7, BOOKE_PAGESZ_256M, 1),
+#endif
+#ifdef CONFIG_SYS_LBAPP2_BASE_PHYS
+	/* LBAPP2 */
+	SET_TLB_ENTRY(1, CONFIG_SYS_LBAPP2_BASE, CONFIG_SYS_LBAPP2_BASE_PHYS,
+		      MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 8, BOOKE_PAGESZ_256M, 1),
+#endif
+	/* Bman/Qman */
+#ifdef CONFIG_SYS_BMAN_MEM_PHYS
+	SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE, CONFIG_SYS_BMAN_MEM_PHYS,
+		      MAS3_SW|MAS3_SR, 0,
+		      0, 9, BOOKE_PAGESZ_1M, 1),
+	SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE + 0x00100000,
+		      CONFIG_SYS_BMAN_MEM_PHYS + 0x00100000,
+		      MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 10, BOOKE_PAGESZ_1M, 1),
+#endif
+#ifdef CONFIG_SYS_QMAN_MEM_PHYS
+	SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE, CONFIG_SYS_QMAN_MEM_PHYS,
+		      MAS3_SW|MAS3_SR, 0,
+		      0, 11, BOOKE_PAGESZ_1M, 1),
+	SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE + 0x00100000,
+		      CONFIG_SYS_QMAN_MEM_PHYS + 0x00100000,
+		      MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 12, BOOKE_PAGESZ_1M, 1),
+#endif
+#ifdef CONFIG_SYS_DCSRBAR_PHYS
+	SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS,
+		      MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 13, BOOKE_PAGESZ_4M, 1),
+#endif
+#ifdef CONFIG_SYS_NAND_BASE
+	/*
+	 * *I*G - NAND
+	 * entry 14 and 15 has been used hard coded, they will be disabled
+	 * in cpu_init_f, so we use entry 16 for nand.
+	 */
+	SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
+		      MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 16, BOOKE_PAGESZ_32K, 1),
+#endif
+};
+
+int num_tlb_entries = ARRAY_SIZE(tlb_table);
diff --git a/board/keymile/scripts/develop-arm.txt b/board/keymile/scripts/develop-arm.txt
index 922afea277..d3c974f1f9 100644
--- a/board/keymile/scripts/develop-arm.txt
+++ b/board/keymile/scripts/develop-arm.txt
@@ -1,2 +1 @@
 setup_debug_env=tftpboot 0x200000 scripts/develop-common.txt && env import -t 0x200000 ${filesize} && run configure
-tftpfdt=true
diff --git a/board/keymile/scripts/develop-common.txt b/board/keymile/scripts/develop-common.txt
index a6bb1b1d4a..a80812a5d0 100644
--- a/board/keymile/scripts/develop-common.txt
+++ b/board/keymile/scripts/develop-common.txt
@@ -3,6 +3,7 @@ bootcmd=run ${subbootcmds}
 configure=run set_uimage; km_setboardid && saveenv && reset
 subbootcmds=tftpfdt tftpkernel nfsargs add_default boot
 nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${toolchain}/${arch}
+tftpfdt=if run set_fdthigh || test ${arch} != arm; then tftpboot ${fdt_addr_r} ${hostname}/${hostname}.dtb; else true; fi
 tftpkernel=tftpboot ${load_addr_r} ${hostname}/${uimage}
 toolchain=/opt/eldk
 rootfssize=0
diff --git a/board/keymile/scripts/develop-ppc_82xx.txt b/board/keymile/scripts/develop-ppc_82xx.txt
index 909f6a3cee..d3c974f1f9 100644
--- a/board/keymile/scripts/develop-ppc_82xx.txt
+++ b/board/keymile/scripts/develop-ppc_82xx.txt
@@ -1,2 +1 @@
 setup_debug_env=tftpboot 0x200000 scripts/develop-common.txt && env import -t 0x200000 ${filesize} && run configure
-tftpfdt=tftpboot ${fdt_addr_r} ${hostname}/${hostname}.dtb
diff --git a/board/keymile/scripts/develop-ppc_8xx.txt b/board/keymile/scripts/develop-ppc_8xx.txt
index 909f6a3cee..d3c974f1f9 100644
--- a/board/keymile/scripts/develop-ppc_8xx.txt
+++ b/board/keymile/scripts/develop-ppc_8xx.txt
@@ -1,2 +1 @@
 setup_debug_env=tftpboot 0x200000 scripts/develop-common.txt && env import -t 0x200000 ${filesize} && run configure
-tftpfdt=tftpboot ${fdt_addr_r} ${hostname}/${hostname}.dtb
diff --git a/board/keymile/scripts/ramfs-arm.txt b/board/keymile/scripts/ramfs-arm.txt
index 79974f1b70..87e984e179 100644
--- a/board/keymile/scripts/ramfs-arm.txt
+++ b/board/keymile/scripts/ramfs-arm.txt
@@ -1,2 +1 @@
 setup_debug_env=tftpboot 0x200000 scripts/ramfs-common.txt && env import -t 0x200000 ${filesize} && run configure
-tftpfdt=true
diff --git a/board/keymile/scripts/ramfs-common.txt b/board/keymile/scripts/ramfs-common.txt
index 502c8631f4..d79ad2e21b 100644
--- a/board/keymile/scripts/ramfs-common.txt
+++ b/board/keymile/scripts/ramfs-common.txt
@@ -7,6 +7,7 @@ nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath}
 configure=run set_uimage; km_setboardid && saveenv && reset
 rootfsfile=${hostname}/rootfsImage
 setrootfsaddr=setexpr value ${pnvramaddr} - ${rootfssize} && setenv rootfsaddr 0x${value}
+tftpfdt=if run set_fdthigh || test ${arch} != arm; then tftpboot ${fdt_addr_r} ${hostname}/${hostname}.dtb; else true; fi
 tftpkernel=tftpboot ${load_addr_r} ${hostname}/${uimage}
 tftpramfs=tftpboot ${rootfsaddr} ${hostname}/rootfsImage
 set_uimage=printenv uimage || setenv uimage uImage
diff --git a/board/keymile/scripts/ramfs-ppc_82xx.txt b/board/keymile/scripts/ramfs-ppc_82xx.txt
index 970927a2fa..87e984e179 100644
--- a/board/keymile/scripts/ramfs-ppc_82xx.txt
+++ b/board/keymile/scripts/ramfs-ppc_82xx.txt
@@ -1,2 +1 @@
 setup_debug_env=tftpboot 0x200000 scripts/ramfs-common.txt && env import -t 0x200000 ${filesize} && run configure
-tftpfdt=tftpboot ${fdt_addr_r} ${hostname}/${hostname}.dtb
diff --git a/board/keymile/scripts/ramfs-ppc_8xx.txt b/board/keymile/scripts/ramfs-ppc_8xx.txt
index 970927a2fa..87e984e179 100644
--- a/board/keymile/scripts/ramfs-ppc_8xx.txt
+++ b/board/keymile/scripts/ramfs-ppc_8xx.txt
@@ -1,2 +1 @@
 setup_debug_env=tftpboot 0x200000 scripts/ramfs-common.txt && env import -t 0x200000 ${filesize} && run configure
-tftpfdt=tftpboot ${fdt_addr_r} ${hostname}/${hostname}.dtb
diff --git a/board/kmc/kzm9g/Makefile b/board/kmc/kzm9g/Makefile
index 62fb3779ed..7989884940 100644
--- a/board/kmc/kzm9g/Makefile
+++ b/board/kmc/kzm9g/Makefile
@@ -5,30 +5,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	:= kzm9g.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
-	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
-
-clean:
-	rm -f $(SOBJS) $(OBJS)
-
-distclean:	clean
-	rm -f $(LIB) core *.bak $(obj) .depend
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	:= kzm9g.o
diff --git a/board/kmc/kzm9g/kzm9g.c b/board/kmc/kzm9g/kzm9g.c
index b669ffefec..ea36fa4e19 100644
--- a/board/kmc/kzm9g/kzm9g.c
+++ b/board/kmc/kzm9g/kzm9g.c
@@ -289,7 +289,6 @@ void adjust_core_voltage(void)
 {
 	u8 data;
 
-	i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
 	data = 0x35;
 	i2c_set_bus_num(0);
 	i2c_write(0x40, 3, 1, &data, 1);
diff --git a/board/korat/Makefile b/board/korat/Makefile
index 0e95230bf0..63914bc13b 100644
--- a/board/korat/Makefile
+++ b/board/korat/Makefile
@@ -5,27 +5,5 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	= $(BOARD).o
-SOBJS	= init.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-all:	$(LIB) $(SOBJS)
-
-$(LIB):	$(OBJS)
-	$(call cmd_link_o_target, $^)
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	= korat.o
+extra-y	+= init.o
diff --git a/board/korat/config.mk b/board/korat/config.mk
index f8dba2baae..42e0060094 100644
--- a/board/korat/config.mk
+++ b/board/korat/config.mk
@@ -23,5 +23,5 @@ PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8CFF0000
 endif
 
 ifndef CONFIG_KORAT_PERMANENT
-LDSCRIPT := $(TOPDIR)/board/$(BOARDDIR)/u-boot-F7FC.lds
+LDSCRIPT := $(srctree)/board/$(BOARDDIR)/u-boot-F7FC.lds
 endif
diff --git a/board/kup/Makefile b/board/kup/Makefile
deleted file mode 100644
index 05be72f484..0000000000
--- a/board/kup/Makefile
+++ /dev/null
@@ -1,28 +0,0 @@
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	= $(BOARD).o flash.o kup.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
diff --git a/board/kup/kup4k/Makefile b/board/kup/kup4k/Makefile
index 8ab0664443..c896fcd64d 100644
--- a/board/kup/kup4k/Makefile
+++ b/board/kup/kup4k/Makefile
@@ -5,27 +5,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-ifneq ($(OBJTREE),$(SRCTREE))
-$(shell mkdir -p $(obj)../common)
-endif
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	= $(BOARD).o ../common/flash.o ../common/kup.o ../common/load_sernum_ethaddr.o ../common/pcmcia.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	= kup4k.o ../common/flash.o ../common/kup.o ../common/load_sernum_ethaddr.o ../common/pcmcia.o
diff --git a/board/kup/kup4x/Makefile b/board/kup/kup4x/Makefile
index 8ab0664443..6945943d09 100644
--- a/board/kup/kup4x/Makefile
+++ b/board/kup/kup4x/Makefile
@@ -5,27 +5,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-ifneq ($(OBJTREE),$(SRCTREE))
-$(shell mkdir -p $(obj)../common)
-endif
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	= $(BOARD).o ../common/flash.o ../common/kup.o ../common/load_sernum_ethaddr.o ../common/pcmcia.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	= kup4x.o ../common/flash.o ../common/kup.o ../common/load_sernum_ethaddr.o ../common/pcmcia.o
diff --git a/board/linkstation/Makefile b/board/linkstation/Makefile
deleted file mode 100644
index 98f283e399..0000000000
--- a/board/linkstation/Makefile
+++ /dev/null
@@ -1,27 +0,0 @@
-#
-# (C) Copyright 2001
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-OBJS	= $(BOARD).o ide.o hwctl.o avr.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(OBJS))
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
diff --git a/board/linkstation/avr.c b/board/linkstation/avr.c
deleted file mode 100644
index 62e586ba09..0000000000
--- a/board/linkstation/avr.c
+++ /dev/null
@@ -1,280 +0,0 @@
-/*
- * avr.c
- *
- * AVR functions
- *
- * Copyright (C) 2006 Mihai Georgian <u-boot@linuxnotincluded.org.uk>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-#include <common.h>
-#include <ns16550.h>
-#include <stdio_dev.h>
-
-/* Button codes from the AVR */
-#define PWRR			0x20		/* Power button release	*/
-#define PWRP			0x21		/* Power button push	*/
-#define RESR			0x22		/* Reset button release	*/
-#define RESP			0x23		/* Reset button push	*/
-#define AVRINIT			0x33		/* Init complete	*/
-#define AVRRESET		0x31		/* Reset request	*/
-
-/* LED commands */
-#define PWRBLINKSTRT		'['		/* Blink power LED	*/
-#define PWRBLINKSTOP		'Z'		/* Solid power LED	*/
-#define HDDLEDON		'W'		/* HDD LED on		*/
-#define HDDLEDOFF		'V'		/* HDD LED off		*/
-#define HDDBLINKSTRT		'Y'		/* HDD LED start blink	*/
-#define HDDBLINKSTOP		'X'		/* HDD LED stop blink	*/
-
-/* Timings for LEDs blinking to show choice */
-#define PULSETIME		250		/* msecs		*/
-#define LONGPAUSE		(5 * PULSETIME)
-
-/* Button press times */
-#define PUSHHOLD		1000		/* msecs		*/
-#define NOBUTTON		(6 * (LONGPAUSE+PULSETIME))
-
-/* Boot and console choices */
-#define MAX_BOOT_CHOICE		3
-
-static char *consoles[] = {
-	"serial",
-#if defined(CONFIG_NETCONSOLE)
-	"nc",
-#endif
-};
-#define MAX_CONS_CHOICE		(sizeof(consoles)/sizeof(char *))
-
-#if !defined(CONFIG_NETCONSOLE)
-#define DEF_CONS_CHOICE		0
-#else
-#define DEF_CONS_CHOICE		1
-#endif
-
-#define perror(fmt, args...) printf("%s: " fmt, __FUNCTION__ , ##args)
-
-extern void miconCntl_SendCmd(unsigned char dat);
-extern void miconCntl_DisWDT(void);
-
-static int boot_stop;
-
-static int boot_choice = 1;
-static int cons_choice = DEF_CONS_CHOICE;
-
-static char envbuffer[16];
-
-void init_AVR_DUART (void)
-{
-	NS16550_t AVR_port = (NS16550_t) CONFIG_SYS_NS16550_COM2;
-	int clock_divisor = CONFIG_SYS_NS16550_CLK / 16 / 9600;
-
-	/*
-	 * AVR port init sequence taken from
-	 * the original Linkstation init code
-	 * Normal U-Boot serial reinit doesn't
-	 * work because the AVR uses even parity
-	 */
-	AVR_port->lcr = 0x00;
-	AVR_port->ier = 0x00;
-	AVR_port->lcr = UART_LCR_BKSE;
-	AVR_port->dll = clock_divisor & 0xff;
-	AVR_port->dlm = (clock_divisor >> 8) & 0xff;
-	AVR_port->lcr = UART_LCR_WLS_8 | UART_LCR_PEN | UART_LCR_EPS;
-	AVR_port->mcr = 0x00;
-	AVR_port->fcr = UART_FCR_FIFO_EN | UART_FCR_RXSR | UART_FCR_TXSR;
-
-	miconCntl_DisWDT();
-
-	boot_stop = 0;
-	miconCntl_SendCmd(PWRBLINKSTRT);
-}
-
-static inline int avr_tstc(void)
-{
-	return (NS16550_tstc((NS16550_t)CONFIG_SYS_NS16550_COM2));
-}
-
-static inline char avr_getc(void)
-{
-	return (NS16550_getc((NS16550_t)CONFIG_SYS_NS16550_COM2));
-}
-
-static int push_timeout(char button_code)
-{
-	ulong push_start = get_timer(0);
-	while (get_timer(push_start) <= PUSHHOLD)
-		if (avr_tstc() && avr_getc() == button_code)
-			return 0;
-	return 1;
-}
-
-static void next_boot_choice(void)
-{
-	ulong return_start;
-	ulong pulse_start;
-	int on_times;
-	int button_on;
-	int led_state;
-	char c;
-
-	button_on = 0;
-	return_start = get_timer(0);
-
-	on_times = boot_choice;
-	led_state = 0;
-	miconCntl_SendCmd(HDDLEDOFF);
-	pulse_start = get_timer(0);
-
-	while (get_timer(return_start) <= NOBUTTON || button_on) {
-		if (avr_tstc()) {
-			c = avr_getc();
-			if (c == PWRP)
-				button_on = 1;
-			else if (c == PWRR) {
-				button_on = 0;
-				return_start = get_timer(0);
-				if (++boot_choice > MAX_BOOT_CHOICE)
-					boot_choice = 1;
-				sprintf(envbuffer, "bootcmd%d", boot_choice);
-				if (getenv(envbuffer)) {
-					sprintf(envbuffer, "run bootcmd%d", boot_choice);
-					setenv("bootcmd", envbuffer);
-				}
-				on_times = boot_choice;
-				led_state = 1;
-				miconCntl_SendCmd(HDDLEDON);
-				pulse_start = get_timer(0);
-			} else {
-				perror("Unexpected code: 0x%02X\n", c);
-			}
-		}
-		if (on_times && get_timer(pulse_start) > PULSETIME) {
-			if (led_state == 1) {
-				--on_times;
-				led_state = 0;
-				miconCntl_SendCmd(HDDLEDOFF);
-			} else {
-				led_state = 1;
-				miconCntl_SendCmd(HDDLEDON);
-			}
-			pulse_start = get_timer(0);
-		}
-		if (!on_times && get_timer(pulse_start) > LONGPAUSE) {
-			on_times = boot_choice;
-			led_state = 1;
-			miconCntl_SendCmd(HDDLEDON);
-			pulse_start = get_timer(0);
-		}
-	}
-	if (led_state)
-		miconCntl_SendCmd(HDDLEDOFF);
-}
-
-void next_cons_choice(int console)
-{
-	ulong return_start;
-	ulong pulse_start;
-	int on_times;
-	int button_on;
-	int led_state;
-	char c;
-
-	button_on = 0;
-	cons_choice = console;
-	return_start = get_timer(0);
-
-	on_times = cons_choice+1;
-	led_state = 1;
-	miconCntl_SendCmd(HDDLEDON);
-	pulse_start = get_timer(0);
-
-	while (get_timer(return_start) <= NOBUTTON || button_on) {
-		if (avr_tstc()) {
-			c = avr_getc();
-			if (c == RESP)
-				button_on = 1;
-			else if (c == RESR) {
-				button_on = 0;
-				return_start = get_timer(0);
-				cons_choice = (cons_choice + 1) % MAX_CONS_CHOICE;
-				console_assign(stdin, consoles[cons_choice]);
-				console_assign(stdout, consoles[cons_choice]);
-				console_assign(stderr, consoles[cons_choice]);
-				on_times = cons_choice+1;
-				led_state = 0;
-				miconCntl_SendCmd(HDDLEDOFF);
-				pulse_start = get_timer(0);
-			} else {
-				perror("Unexpected code: 0x%02X\n", c);
-			}
-		}
-		if (on_times && get_timer(pulse_start) > PULSETIME) {
-			if (led_state == 0) {
-				--on_times;
-				led_state = 1;
-				miconCntl_SendCmd(HDDLEDON);
-			} else {
-				led_state = 0;
-				miconCntl_SendCmd(HDDLEDOFF);
-			}
-			pulse_start = get_timer(0);
-		}
-		if (!on_times && get_timer(pulse_start) > LONGPAUSE) {
-			on_times = cons_choice+1;
-			led_state = 0;
-			miconCntl_SendCmd(HDDLEDOFF);
-			pulse_start = get_timer(0);
-		}
-	}
-	if (led_state);
-	miconCntl_SendCmd(HDDLEDOFF);
-}
-
-int avr_input(void)
-{
-	char avr_button;
-
-	if (!avr_tstc())
-		return 0;
-
-	avr_button = avr_getc();
-	switch (avr_button) {
-	case PWRP:
-		if (push_timeout(PWRR)) {
-			/* Timeout before power button release */
-			boot_stop = ~boot_stop;
-			if (boot_stop)
-				miconCntl_SendCmd(PWRBLINKSTOP);
-			else
-				miconCntl_SendCmd(PWRBLINKSTRT);
-			/* Wait for power button release */
-			while (avr_getc() != PWRR)
-				;
-		} else
-			/* Power button released */
-			next_boot_choice();
-		break;
-	case RESP:
-		/* Wait for Reset button release */
-		while (avr_getc() != RESR)
-			;
-		next_cons_choice(cons_choice);
-		break;
-	case AVRINIT:
-		return 0;
-	default:
-		perror("Unexpected code: 0x%02X\n", avr_button);
-		return 0;
-	}
-	if (boot_stop)
-		return (-3);
-	else
-		return (-2);
-}
-
-void avr_StopBoot(void)
-{
-	boot_stop = ~0;
-	miconCntl_SendCmd(PWRBLINKSTOP);
-}
diff --git a/board/linkstation/hwctl.c b/board/linkstation/hwctl.c
deleted file mode 100644
index d2090be1ad..0000000000
--- a/board/linkstation/hwctl.c
+++ /dev/null
@@ -1,133 +0,0 @@
-/*
- * hwctl.c
- *
- * LinkStation HW Control Driver
- *
- * Copyright (C) 2001-2004  BUFFALO INC.
- *
- * This software may be used and distributed according to the terms of
- * the GNU General Public License (GPL), incorporated herein by reference.
- * Drivers based on or derived from this code fall under the GPL and must
- * retain the authorship, copyright and license notice.  This file is not
- * a complete program and may only be used when the entire operating
- * system is licensed under the GPL.
- *
- */
-
-#include <config.h>
-#include <common.h>
-#include <command.h>
-#include <asm/io.h>
-
-#define AVR_PORT CONFIG_SYS_NS16550_COM2
-
-/* 2005.5.10 BUFFALO add */
-/*--------------------------------------------------------------*/
-static inline void miconCntl_SendUart(unsigned char dat)
-{
-	out_8((unsigned char *)AVR_PORT, dat);
-	mdelay(1);
-}
-
-/*--------------------------------------------------------------*/
-void miconCntl_SendCmd(unsigned char dat)
-{
-	int i;
-
-	for (i=0; i<4; i++){
-		miconCntl_SendUart(dat);
-	}
-}
-
-/*--------------------------------------------------------------*/
-void miconCntl_FanLow(void)
-{
-#ifdef CONFIG_HTGL
-	miconCntl_SendCmd(0x5C);
-#endif
-}
-
-/*--------------------------------------------------------------*/
-void miconCntl_FanHigh(void)
-{
-#ifdef CONFIG_HTGL
-	miconCntl_SendCmd(0x5D);
-#endif
-}
-
-/*--------------------------------------------------------------*/
-/* 1000Mbps */
-void miconCntl_Eth1000M(int up)
-{
-#ifdef CONFIG_HTGL
-	if (up)
-		miconCntl_SendCmd(0x93);
-	else
-		miconCntl_SendCmd(0x92);
-#else
-	if (up)
-		miconCntl_SendCmd(0x5D);
-	else
-		miconCntl_SendCmd(0x5C);
-#endif
-}
-
-/*--------------------------------------------------------------*/
-/* 100Mbps */
-void miconCntl_Eth100M(int up)
-{
-#ifdef CONFIG_HTGL
-	if (up)
-		miconCntl_SendCmd(0x91);
-	else
-		miconCntl_SendCmd(0x90);
-#else
-	if (up)
-		miconCntl_SendCmd(0x5C);
-#endif
-}
-
-/*--------------------------------------------------------------*/
-/* 10Mbps */
-void miconCntl_Eth10M(int up)
-{
-#ifdef CONFIG_HTGL
-	if (up)
-		miconCntl_SendCmd(0x8F);
-	else
-		miconCntl_SendCmd(0x8E);
-#else
-	if (up)
-		miconCntl_SendCmd(0x5C);
-#endif
-}
-
-/*--------------------------------------------------------------*/
-/*  */
-void miconCntl_5f(void)
-{
-	miconCntl_SendCmd(0x5F);
-	mdelay(100);
-}
-
-/*--------------------------------------------------------------*/
-/* "reboot start" signal */
-void miconCntl_Reboot(void)
-{
-	miconCntl_SendCmd(0x43);
-}
-
-/*--------------------------------------------------------------*/
-/* Disable watchdog timer */
-void miconCntl_DisWDT(void)
-{
-	miconCntl_SendCmd(0x41); /* A */
-	miconCntl_SendCmd(0x46); /* F */
-	miconCntl_SendCmd(0x4A); /* J */
-	miconCntl_SendCmd(0x3E); /* > */
-	miconCntl_SendCmd(0x56); /* V */
-	miconCntl_SendCmd(0x3E); /* > */
-	miconCntl_SendCmd(0x5A); /* Z */
-	miconCntl_SendCmd(0x56); /* V */
-	miconCntl_SendCmd(0x4B); /* K */
-}
diff --git a/board/linkstation/ide.c b/board/linkstation/ide.c
deleted file mode 100644
index 7b3fe65cff..0000000000
--- a/board/linkstation/ide.c
+++ /dev/null
@@ -1,85 +0,0 @@
-/*
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-/* ide.c - ide support functions */
-
-
-#include <common.h>
-
-#ifdef CONFIG_CMD_IDE
-#include <ata.h>
-#include <ide.h>
-#include <pci.h>
-
-#define IT8212_PCI_CpuCONTROL		0x5e
-#define IT8212_PCI_PciModeCONTROL	0x50
-#define IT8212_PCI_IdeIoCONFIG		0x40
-#define IT8212_PCI_IdeBusSkewCONTROL	0x4c
-#define IT8212_PCI_IdeDrivingCURRENT	0x42
-
-extern struct pci_controller hose;
-
-int ide_preinit (void)
-{
-	int status;
-	pci_dev_t devbusfn;
-	int l;
-
-	status = 1;
-	for (l = 0; l < CONFIG_SYS_IDE_MAXBUS; l++) {
-		ide_bus_offset[l] = -ATA_STATUS;
-	}
-	devbusfn = pci_find_device(PCI_VENDOR_ID_CMD, PCI_DEVICE_ID_SII_680, 0);
-	if (devbusfn == -1)
-		devbusfn = pci_find_device(PCI_VENDOR_ID_ITE,PCI_DEVICE_ID_ITE_8212,0);
-	if (devbusfn != -1) {
-		u32 ide_bus_offset32;
-
-		status = 0;
-
-		pci_read_config_dword (devbusfn, PCI_BASE_ADDRESS_0,
-							   &ide_bus_offset32);
-		ide_bus_offset[0] = ide_bus_offset32 & 0xfffffffe;
-		ide_bus_offset[0] = pci_hose_bus_to_phys(&hose,
-						ide_bus_offset[0] & 0xfffffffe,
-						PCI_REGION_IO);
-		if (CONFIG_SYS_IDE_MAXBUS > 1) {
-			pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_2,
-					      (u32 *) &ide_bus_offset[1]);
-			ide_bus_offset[1] &= 0xfffffffe;
-			ide_bus_offset[1] = pci_hose_bus_to_phys(&hose,
-						ide_bus_offset[1] & 0xfffffffe,
-						PCI_REGION_IO);
-		}
-	}
-
-	if (pci_find_device (PCI_VENDOR_ID_ITE, PCI_DEVICE_ID_ITE_8212, 0) != -1) {
-		pci_write_config_byte(devbusfn, IT8212_PCI_CpuCONTROL, 0x01);
-		pci_write_config_byte(devbusfn, IT8212_PCI_PciModeCONTROL, 0x00);
-		pci_write_config_word(devbusfn, PCI_COMMAND, 0x0047);
-#ifdef CONFIG_IT8212_SECONDARY_ENABLE
-		pci_write_config_word(devbusfn, IT8212_PCI_IdeIoCONFIG, 0xA0F3);
-#else
-		pci_write_config_word(devbusfn, IT8212_PCI_IdeIoCONFIG, 0x8031);
-#endif
-		pci_write_config_dword(devbusfn, IT8212_PCI_IdeBusSkewCONTROL, 0x02040204);
-/* __LS_COMMENT__ BUFFALO changed 2004.11.10  changed for EMI */
-		pci_write_config_byte(devbusfn, IT8212_PCI_IdeDrivingCURRENT, 0x36); /* 10mA */
-/*		pci_write_config_byte(dev, IT8212_PCI_IdeDrivingCURRENT, 0x09); */ /* 4mA */
-/*		pci_write_config_byte(dev, IT8212_PCI_IdeDrivingCURRENT, 0x12); */ /* 6mA */
-/*		pci_write_config_byte(dev, IT8212_PCI_IdeDrivingCURRENT, 0x24); */ /* 6mA,2mA */
-/*		pci_write_config_byte(dev, IT8212_PCI_IdeDrivingCURRENT, 0x2D); */ /* 8mA,4mA */
-		pci_write_config_byte(devbusfn, PCI_LATENCY_TIMER, 0x00);
-	}
-
-	return (status);
-}
-
-void ide_set_reset (int flag) {
-	return;
-}
-
-#endif /* CONFIG_CMD_IDE */
diff --git a/board/linkstation/linkstation.c b/board/linkstation/linkstation.c
deleted file mode 100644
index 75cda8681f..0000000000
--- a/board/linkstation/linkstation.c
+++ /dev/null
@@ -1,124 +0,0 @@
-/*
- * linkstation.c
- *
- * Misc LinkStation specific functions
- *
- * Copyright (C) 2006 Mihai Georgian <u-boot@linuxnotincluded.org.uk>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <version.h>
-#include <mpc824x.h>
-#include <asm/io.h>
-#include <ns16550.h>
-#include <netdev.h>
-
-#ifdef CONFIG_PCI
-#include <pci.h>
-#endif
-
-DECLARE_GLOBAL_DATA_PTR;
-
-extern void init_AVR_DUART(void);
-
-int checkboard (void)
-{
-	char *p;
-	bd_t *bd = gd->bd;
-
-	init_AVR_DUART();
-
-	if ((p = getenv ("console_nr")) != NULL) {
-		unsigned long con_nr = simple_strtoul (p, NULL, 10) & 3;
-
-		bd->bi_baudrate &= ~3;
-		bd->bi_baudrate |= con_nr & 3;
-	}
-	return 0;
-}
-
-phys_size_t initdram (int board_type)
-{
-	return (get_ram_size(CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_MAX_RAM_SIZE));
-}
-
-/*
- * Initialize PCI Devices
- */
-#ifdef CONFIG_PCI
-
-#ifndef CONFIG_PCI_PNP
-
-static struct pci_config_table pci_linkstation_config_table[] = {
-	/* vendor, device, class */
-	/* bus, dev, func */
-	{ PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
-	  PCI_ANY_ID, 0x0b, 0,		/* AN983B or RTL8110S  */
-								/* ethernet controller */
-	  pci_cfgfunc_config_device, { PCI_ETH_IOADDR,
-				       PCI_ETH_MEMADDR,
-				       PCI_COMMAND_IO |
-				       PCI_COMMAND_MEMORY |
-				       PCI_COMMAND_MASTER }},
-	{ PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
-	  PCI_ANY_ID, 0x0c, 0,		/* SII680 or IT8211AF */
-								/* ide controller     */
-	  pci_cfgfunc_config_device, { PCI_IDE_IOADDR,
-				       PCI_IDE_MEMADDR,
-				       PCI_COMMAND_IO |
-				       PCI_COMMAND_MEMORY |
-				       PCI_COMMAND_MASTER }},
-	{ PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
-	  PCI_ANY_ID, 0x0e, 0,		/* D720101 USB controller, 1st USB 1.1 */
-	  pci_cfgfunc_config_device, { PCI_USB0_IOADDR,
-				       PCI_USB0_MEMADDR,
-				       PCI_COMMAND_MEMORY |
-				       PCI_COMMAND_MASTER }},
-	{ PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
-	  PCI_ANY_ID, 0x0e, 1,		/* D720101 USB controller, 2nd USB 1.1 */
-	  pci_cfgfunc_config_device, { PCI_USB1_IOADDR,
-				       PCI_USB1_MEMADDR,
-				       PCI_COMMAND_MEMORY |
-				       PCI_COMMAND_MASTER }},
-	{ PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
-	  PCI_ANY_ID, 0x0e, 2,		/* D720101 USB controller, USB 2.0 */
-	  pci_cfgfunc_config_device, { PCI_USB2_IOADDR,
-				       PCI_USB2_MEMADDR,
-				       PCI_COMMAND_MEMORY |
-				       PCI_COMMAND_MASTER }},
-	{ }
-};
-#endif
-
-struct pci_controller hose = {
-#ifndef CONFIG_PCI_PNP
-	config_table:pci_linkstation_config_table,
-#endif
-};
-
-void pci_init_board (void)
-{
-	pci_mpc824x_init (&hose);
-
-	/* Reset USB 1.1 */
-	/* Haven't seen any change without these on a HG, maybe it is
-	 * needed on other models */
-	out_le32((volatile unsigned*)(PCI_USB0_MEMADDR + 8), 1);
-	out_le32((volatile unsigned*)(PCI_USB1_MEMADDR + 8), 1);
-}
-#endif /* CONFIG_PCI */
-
-#define UART_DCR       0x80004511
-int board_early_init_f (void)
-{
-	/* set DUART mode */
-	out_8((volatile u8*)UART_DCR, 1);
-	return 0;
-}
-
-int board_eth_init(bd_t *bis)
-{
-	return pci_eth_init(bis);
-}
diff --git a/board/logicpd/am3517evm/Makefile b/board/logicpd/am3517evm/Makefile
index 2b4f0b6b2b..73b11dfbf0 100644
--- a/board/logicpd/am3517evm/Makefile
+++ b/board/logicpd/am3517evm/Makefile
@@ -8,21 +8,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	:= am3517evm.o
-
-SRCS	:= $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
+obj-y	:= am3517evm.o
diff --git a/board/logicpd/am3517evm/am3517evm.c b/board/logicpd/am3517evm/am3517evm.c
index b6c68da7a8..24be6eabfc 100644
--- a/board/logicpd/am3517evm/am3517evm.c
+++ b/board/logicpd/am3517evm/am3517evm.c
@@ -22,6 +22,7 @@
 #include <asm/arch/musb.h>
 #include <asm/mach-types.h>
 #include <asm/errno.h>
+#include <asm/gpio.h>
 #include <linux/usb/ch9.h>
 #include <linux/usb/gadget.h>
 #include <linux/usb/musb.h>
@@ -31,6 +32,9 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
+#define AM3517_IP_SW_RESET	0x48002598
+#define CPGMACSS_SW_RST		(1 << 1)
+
 /*
  * Routine: board_init
  * Description: Early hardware init.
@@ -98,14 +102,42 @@ static void am3517_evm_musb_init(void)
  */
 int misc_init_r(void)
 {
-#ifdef CONFIG_DRIVER_OMAP34XX_I2C
-	i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
+	volatile unsigned int ctr;
+	u32 reset;
+
+#ifdef CONFIG_SYS_I2C_OMAP34XX
+	i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE);
 #endif
 
 	dieid_num_r();
 
 	am3517_evm_musb_init();
 
+	/* activate PHY reset */
+	gpio_direction_output(30, 0);
+	gpio_set_value(30, 0);
+
+	ctr  = 0;
+	do {
+		udelay(1000);
+		ctr++;
+	} while (ctr < 300);
+
+	/* deactivate PHY reset */
+	gpio_set_value(30, 1);
+
+	/* allow the PHY to stabilize and settle down */
+	ctr = 0;
+	do {
+		udelay(1000);
+		ctr++;
+	} while (ctr < 300);
+
+	/* ensure that the module is out of reset */
+	reset = readl(AM3517_IP_SW_RESET);
+	reset &= (~CPGMACSS_SW_RST);
+	writel(reset,AM3517_IP_SW_RESET);
+
 	return 0;
 }
 
diff --git a/board/logicpd/am3517evm/am3517evm.h b/board/logicpd/am3517evm/am3517evm.h
index 704af847a7..d407d66ae6 100644
--- a/board/logicpd/am3517evm/am3517evm.h
+++ b/board/logicpd/am3517evm/am3517evm.h
@@ -315,7 +315,7 @@ const omap3_sysinfo sysinfo = {
 	MUX_VAL(CP(SYS_CLKREQ),		(IEN  | PTD | DIS | M0)) \
 	MUX_VAL(CP(SYS_NIRQ),		(IEN  | PTU | EN  | M0)) \
 	/*SYS_nRESWARM */\
-	MUX_VAL(CP(SYS_NRESWARM),     	(IDIS | PTU | DIS | M4)) \
+	MUX_VAL(CP(SYS_NRESWARM),     	(IDIS | PTU | EN | M4)) \
 							/* - GPIO30 */\
 	MUX_VAL(CP(SYS_BOOT0),		(IEN  | PTD | DIS | M4)) /*GPIO_2*/\
 							 /* - PEN_IRQ */\
diff --git a/board/logicpd/imx27lite/Makefile b/board/logicpd/imx27lite/Makefile
index c42bd4c15c..50a3da62ed 100644
--- a/board/logicpd/imx27lite/Makefile
+++ b/board/logicpd/imx27lite/Makefile
@@ -5,24 +5,5 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	:= imx27lite.o
-SOBJS	:= lowlevel_init.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
-	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
-
-#########################################################################
-
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	:= imx27lite.o
+obj-y	+= lowlevel_init.o
diff --git a/board/logicpd/imx31_litekit/Makefile b/board/logicpd/imx31_litekit/Makefile
index 33cacacc5f..3fd71c8deb 100644
--- a/board/logicpd/imx31_litekit/Makefile
+++ b/board/logicpd/imx31_litekit/Makefile
@@ -5,25 +5,5 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	:= imx31_litekit.o
-SOBJS	:= lowlevel_init.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
-	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	:= imx31_litekit.o
+obj-y	+= lowlevel_init.o
diff --git a/board/logicpd/omap3som/Makefile b/board/logicpd/omap3som/Makefile
index f8393fa045..87b86ad254 100644
--- a/board/logicpd/omap3som/Makefile
+++ b/board/logicpd/omap3som/Makefile
@@ -5,22 +5,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS-y	:= omap3logic.o
-
-COBJS	:= $(sort $(COBJS-y))
-SRCS	:= $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
+obj-y	:= omap3logic.o
diff --git a/board/logicpd/zoom1/Makefile b/board/logicpd/zoom1/Makefile
index 4afca20feb..7da0da031a 100644
--- a/board/logicpd/zoom1/Makefile
+++ b/board/logicpd/zoom1/Makefile
@@ -5,23 +5,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	:= zoom1.o
-
-SRCS	:= $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	:= zoom1.o
diff --git a/board/logicpd/zoom2/Makefile b/board/logicpd/zoom2/Makefile
deleted file mode 100644
index b1fbbbd0bb..0000000000
--- a/board/logicpd/zoom2/Makefile
+++ /dev/null
@@ -1,31 +0,0 @@
-#
-# (C) Copyright 2000, 2001, 2002
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS-y := $(BOARD).o
-COBJS-y += debug_board.o
-COBJS-y += zoom2_serial.o
-COBJS-$(CONFIG_STATUS_LED) += led.o
-
-COBJS	:= $(sort $(COBJS-y))
-SRCS	:= $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
diff --git a/board/logicpd/zoom2/config.mk b/board/logicpd/zoom2/config.mk
deleted file mode 100644
index 1c382f7189..0000000000
--- a/board/logicpd/zoom2/config.mk
+++ /dev/null
@@ -1,17 +0,0 @@
-#
-# (C) Copyright 2009
-# Texas Instruments, <www.ti.com>
-#
-# Zoom II uses OMAP3 (ARM-CortexA8) CPU
-# see http://www.ti.com/ for more information on Texas Instruments
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-# Physical Address:
-# 0x80000000 (bank0)
-# 0xA0000000 (bank1)
-# Linux-Kernel is expected to be at 0x80008000, entry 0x80008000
-# (mem base + reserved)
-
-# For use with external or internal boots.
-CONFIG_SYS_TEXT_BASE = 0x80008000
diff --git a/board/logicpd/zoom2/debug_board.c b/board/logicpd/zoom2/debug_board.c
deleted file mode 100644
index 071f41074b..0000000000
--- a/board/logicpd/zoom2/debug_board.c
+++ /dev/null
@@ -1,44 +0,0 @@
-/*
- * Copyright (c) 2009 Wind River Systems, Inc.
- * Tom Rix <Tom.Rix@windriver.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-#include <common.h>
-#include <asm/arch/cpu.h>
-#include <asm/io.h>
-#include <asm/arch/mux.h>
-#include <asm/gpio.h>
-
-#define DEBUG_BOARD_CONNECTED		1
-#define DEBUG_BOARD_NOT_CONNECTED	0
-
-static int debug_board_connected = DEBUG_BOARD_CONNECTED;
-
-static void zoom2_debug_board_detect (void)
-{
-	int val = 0;
-
-	if (!gpio_request(158, "")) {
-		/*
-		 * GPIO to query for debug board
-		 * 158 db board query
-		 */
-		gpio_direction_input(158);
-		val = gpio_get_value(158);
-	}
-
-	if (!val)
-		debug_board_connected = DEBUG_BOARD_NOT_CONNECTED;
-}
-
-int zoom2_debug_board_connected (void)
-{
-	static int first_time = 1;
-
-	if (first_time) {
-		zoom2_debug_board_detect ();
-		first_time = 0;
-	}
-	return debug_board_connected;
-}
diff --git a/board/logicpd/zoom2/led.c b/board/logicpd/zoom2/led.c
deleted file mode 100644
index 5d37ac15f2..0000000000
--- a/board/logicpd/zoom2/led.c
+++ /dev/null
@@ -1,116 +0,0 @@
-/*
- * Copyright (c) 2009 Wind River Systems, Inc.
- * Tom Rix <Tom.Rix@windriver.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-#include <common.h>
-#include <status_led.h>
-#include <asm/arch/cpu.h>
-#include <asm/io.h>
-#include <asm/arch/sys_proto.h>
-#include <asm/gpio.h>
-
-static unsigned int saved_state[2] = {STATUS_LED_OFF, STATUS_LED_OFF};
-
-/*
- * GPIO LEDs
- * 173 red
- * 154 blue
- * 61  blue2
- */
-#define ZOOM2_LED_RED	173
-#define ZOOM2_LED_BLUE	154
-#define ZOOM2_LED_BLUE2	61
-
-void red_led_off(void)
-{
-	/* red */
-	if (!gpio_request(ZOOM2_LED_RED, "")) {
-		gpio_direction_output(ZOOM2_LED_RED, 0);
-		gpio_set_value(ZOOM2_LED_RED, 0);
-	}
-	saved_state[STATUS_LED_RED] = STATUS_LED_OFF;
-}
-
-void blue_led_off(void)
-{
-	/* blue */
-	if (!gpio_request(ZOOM2_LED_BLUE, "")) {
-		gpio_direction_output(ZOOM2_LED_BLUE, 0);
-		gpio_set_value(ZOOM2_LED_BLUE, 0);
-	}
-
-	/* blue 2 */
-	if (!gpio_request(ZOOM2_LED_BLUE2, "")) {
-		gpio_direction_output(ZOOM2_LED_BLUE2, 0);
-		gpio_set_value(ZOOM2_LED_BLUE2, 0);
-	}
-	saved_state[STATUS_LED_BLUE] = STATUS_LED_OFF;
-}
-
-void red_led_on(void)
-{
-	blue_led_off();
-
-	/* red */
-	if (!gpio_request(ZOOM2_LED_RED, "")) {
-		gpio_direction_output(ZOOM2_LED_RED, 0);
-		gpio_set_value(ZOOM2_LED_RED, 1);
-	}
-	saved_state[STATUS_LED_RED] = STATUS_LED_ON;
-}
-
-void blue_led_on(void)
-{
-	red_led_off();
-
-	/* blue */
-	if (!gpio_request(ZOOM2_LED_BLUE, "")) {
-		gpio_direction_output(ZOOM2_LED_BLUE, 0);
-		gpio_set_value(ZOOM2_LED_BLUE, 1);
-	}
-
-	/* blue 2 */
-	if (!gpio_request(ZOOM2_LED_BLUE2, "")) {
-		gpio_direction_output(ZOOM2_LED_BLUE2, 0);
-		gpio_set_value(ZOOM2_LED_BLUE2, 1);
-	}
-
-	saved_state[STATUS_LED_BLUE] = STATUS_LED_ON;
-}
-
-void __led_init (led_id_t mask, int state)
-{
-	__led_set (mask, state);
-}
-
-void __led_toggle (led_id_t mask)
-{
-	if (STATUS_LED_BLUE == mask) {
-		if (STATUS_LED_ON == saved_state[STATUS_LED_BLUE])
-			blue_led_off();
-		else
-			blue_led_on();
-	} else if (STATUS_LED_RED == mask) {
-		if (STATUS_LED_ON == saved_state[STATUS_LED_RED])
-			red_led_off();
-		else
-			red_led_on();
-	}
-}
-
-void __led_set (led_id_t mask, int state)
-{
-	if (STATUS_LED_BLUE == mask) {
-		if (STATUS_LED_ON == state)
-			blue_led_on();
-		else
-			blue_led_off();
-	} else if (STATUS_LED_RED == mask) {
-		if (STATUS_LED_ON == state)
-			red_led_on();
-		else
-			red_led_off();
-	}
-}
diff --git a/board/logicpd/zoom2/zoom2.c b/board/logicpd/zoom2/zoom2.c
deleted file mode 100644
index e14de04695..0000000000
--- a/board/logicpd/zoom2/zoom2.c
+++ /dev/null
@@ -1,183 +0,0 @@
-/*
- * Copyright (c) 2009 Wind River Systems, Inc.
- * Tom Rix <Tom.Rix@windriver.com>
- *
- * Derived from Zoom1 code by
- *	Nishanth Menon <nm@ti.com>
- *	Sunil Kumar <sunilsaini05@gmail.com>
- *	Shashi Ranjan <shashiranjanmca05@gmail.com>
- *	Richard Woodruff <r-woodruff2@ti.com>
- *	Syed Mohammed Khasim <khasim@ti.com>
- *
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-#include <common.h>
-#include <netdev.h>
-#ifdef CONFIG_STATUS_LED
-#include <status_led.h>
-#endif
-#include <twl4030.h>
-#include <asm/io.h>
-#include <asm/arch/mmc_host_def.h>
-#include <asm/gpio.h>
-#include <asm/arch/mem.h>
-#include <asm/arch/mux.h>
-#include <asm/arch/sys_proto.h>
-#include <asm/mach-types.h>
-#include "zoom2.h"
-#include "zoom2_serial.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-/*
- * This the the zoom2, board specific, gpmc configuration for the
- * quad uart on the debug board.   The more general gpmc configurations
- * are setup at the cpu level in arch/arm/cpu/armv7/omap3/mem.c
- *
- * The details of the setting of the serial gpmc setup are not available.
- * The values were provided by another party.
- */
-static u32 gpmc_serial_TL16CP754C[GPMC_MAX_REG] = {
-	0x00011000,
-	0x001F1F01,
-	0x00080803,
-	0x1D091D09,
-	0x041D1F1F,
-	0x1D0904C4, 0
-};
-
-/* Used to track the revision of the board */
-static zoom2_revision revision = ZOOM2_REVISION_UNKNOWN;
-
-/*
- * Routine: zoom2_get_revision
- * Description: Return the revision of the Zoom2 this code is running on.
- */
-zoom2_revision zoom2_get_revision(void)
-{
-	return revision;
-}
-
-/*
- * Routine: zoom2_identify
- * Description: Detect which version of Zoom2 we are running on.
- */
-void zoom2_identify(void)
-{
-	/*
-	 * To check for production board vs beta board,
-	 * check if gpio 94 is clear.
-	 *
-	 * No way yet to check for alpha board identity.
-	 * Alpha boards were produced in very limited quantities
-	 * and they are not commonly used.  They are mentioned here
-	 * only for completeness.
-	 */
-	if (!gpio_request(94, "")) {
-		unsigned int val;
-
-		gpio_direction_input(94);
-		val = gpio_get_value(94);
-
-		if (val)
-			revision = ZOOM2_REVISION_BETA;
-		else
-			revision = ZOOM2_REVISION_PRODUCTION;
-	}
-
-	printf("Board revision ");
-	switch (revision) {
-	case ZOOM2_REVISION_PRODUCTION:
-		printf("Production\n");
-		break;
-	case ZOOM2_REVISION_BETA:
-		printf("Beta\n");
-		break;
-	default:
-		printf("Unknown\n");
-		break;
-	}
-}
-
-/*
- * Routine: board_init
- * Description: Early hardware init.
- */
-int board_init (void)
-{
-	u32 *gpmc_config;
-
-	gpmc_init ();		/* in SRAM or SDRAM, finish GPMC */
-
-	/* Configure console support on zoom2 */
-	gpmc_config = gpmc_serial_TL16CP754C;
-	enable_gpmc_cs_config(gpmc_config, &gpmc_cfg->cs[3],
-			SERIAL_TL16CP754C_BASE, GPMC_SIZE_16M);
-
-	/* board id for Linux */
-	gd->bd->bi_arch_number = MACH_TYPE_OMAP_ZOOM2;
-	/* boot param addr */
-	gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
-
-#if defined(CONFIG_STATUS_LED) && defined(STATUS_LED_BOOT)
-	status_led_set (STATUS_LED_BOOT, STATUS_LED_ON);
-#endif
-	return 0;
-}
-
-/*
- * Routine: misc_init_r
- * Description: Configure zoom board specific configurations
- */
-int misc_init_r(void)
-{
-	zoom2_identify();
-	twl4030_power_init();
-	twl4030_led_init(TWL4030_LED_LEDEN_LEDAON | TWL4030_LED_LEDEN_LEDBON);
-	dieid_num_r();
-
-	/*
-	 * Board Reset
-	 * The board is reset by holding the the large button
-	 * on the top right side of the main board for
-	 * eight seconds.
-	 *
-	 * There are reported problems of some beta boards
-	 * continously resetting.  For those boards, disable resetting.
-	 */
-	if (ZOOM2_REVISION_PRODUCTION <= zoom2_get_revision())
-		twl4030_power_reset_init();
-
-	return 0;
-}
-
-/*
- * Routine: set_muxconf_regs
- * Description: Setting up the configuration Mux registers specific to the
- *		hardware. Many pins need to be moved from protect to primary
- *		mode.
- */
-void set_muxconf_regs (void)
-{
-	/* platform specific muxes */
-	MUX_ZOOM2 ();
-}
-
-#ifdef CONFIG_GENERIC_MMC
-int board_mmc_init(bd_t *bis)
-{
-	return omap_mmc_init(0, 0, 0, -1, -1);
-}
-#endif
-
-#ifdef CONFIG_CMD_NET
-int board_eth_init(bd_t *bis)
-{
-	int rc = 0;
-#ifdef CONFIG_LAN91C96
-	rc = lan91c96_initialize(0, CONFIG_LAN91C96_BASE);
-#endif
-	return rc;
-}
-#endif
diff --git a/board/logicpd/zoom2/zoom2.h b/board/logicpd/zoom2/zoom2.h
deleted file mode 100644
index 850c790a08..0000000000
--- a/board/logicpd/zoom2/zoom2.h
+++ /dev/null
@@ -1,142 +0,0 @@
-/*
- * Copyright (c) 2009 Wind River Systems, Inc.
- * Tom Rix <Tom.Rix@windriver.com>
- *
- * Derived from: board/omap3/zoom1/zoom1.h
- * Nishanth Menon <nm@ti.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-#ifndef _BOARD_ZOOM2_H_
-#define _BOARD_ZOOM2_H_
-
-const omap3_sysinfo sysinfo = {
-	DDR_STACKED,
-	"OMAP3 Zoom2 ",
-	"NAND",
-};
-
-typedef enum {
-	ZOOM2_REVISION_UNKNOWN = 0,
-	ZOOM2_REVISION_ALPHA,
-	ZOOM2_REVISION_BETA,
-	ZOOM2_REVISION_PRODUCTION
-} zoom2_revision;
-
-zoom2_revision zoom2_get_revision(void);
-
-/*
- * IEN	- Input Enable
- * IDIS	- Input Disable
- * PTD	- Pull type Down
- * PTU	- Pull type Up
- * DIS	- Pull type selection is inactive
- * EN	- Pull type selection is active
- * M0	- Mode 0
- * The commented string gives the final mux configuration for that pin
- */
-#define MUX_ZOOM2() \
- /* SDRC*/\
-	MUX_VAL(CP(SDRC_D0),		(IEN  | PTD | DIS | M0)) /* SDRC_D0 */\
-	MUX_VAL(CP(SDRC_D1),		(IEN  | PTD | DIS | M0)) /* SDRC_D1 */\
-	MUX_VAL(CP(SDRC_D2),		(IEN  | PTD | DIS | M0)) /* SDRC_D2 */\
-	MUX_VAL(CP(SDRC_D3),		(IEN  | PTD | DIS | M0)) /* SDRC_D3 */\
-	MUX_VAL(CP(SDRC_D4),		(IEN  | PTD | DIS | M0)) /* SDRC_D4 */\
-	MUX_VAL(CP(SDRC_D5),		(IEN  | PTD | DIS | M0)) /* SDRC_D5 */\
-	MUX_VAL(CP(SDRC_D6),		(IEN  | PTD | DIS | M0)) /* SDRC_D6 */\
-	MUX_VAL(CP(SDRC_D7),		(IEN  | PTD | DIS | M0)) /* SDRC_D7 */\
-	MUX_VAL(CP(SDRC_D8),		(IEN  | PTD | DIS | M0)) /* SDRC_D8 */\
-	MUX_VAL(CP(SDRC_D9),		(IEN  | PTD | DIS | M0)) /* SDRC_D9 */\
-	MUX_VAL(CP(SDRC_D10),		(IEN  | PTD | DIS | M0)) /* SDRC_D10 */\
-	MUX_VAL(CP(SDRC_D11),		(IEN  | PTD | DIS | M0)) /* SDRC_D11 */\
-	MUX_VAL(CP(SDRC_D12),		(IEN  | PTD | DIS | M0)) /* SDRC_D12 */\
-	MUX_VAL(CP(SDRC_D13),		(IEN  | PTD | DIS | M0)) /* SDRC_D13 */\
-	MUX_VAL(CP(SDRC_D14),		(IEN  | PTD | DIS | M0)) /* SDRC_D14 */\
-	MUX_VAL(CP(SDRC_D15),		(IEN  | PTD | DIS | M0)) /* SDRC_D15 */\
-	MUX_VAL(CP(SDRC_D16),		(IEN  | PTD | DIS | M0)) /* SDRC_D16 */\
-	MUX_VAL(CP(SDRC_D17),		(IEN  | PTD | DIS | M0)) /* SDRC_D17 */\
-	MUX_VAL(CP(SDRC_D18),		(IEN  | PTD | DIS | M0)) /* SDRC_D18 */\
-	MUX_VAL(CP(SDRC_D19),		(IEN  | PTD | DIS | M0)) /* SDRC_D19 */\
-	MUX_VAL(CP(SDRC_D20),		(IEN  | PTD | DIS | M0)) /* SDRC_D20 */\
-	MUX_VAL(CP(SDRC_D21),		(IEN  | PTD | DIS | M0)) /* SDRC_D21 */\
-	MUX_VAL(CP(SDRC_D22),		(IEN  | PTD | DIS | M0)) /* SDRC_D22 */\
-	MUX_VAL(CP(SDRC_D23),		(IEN  | PTD | DIS | M0)) /* SDRC_D23 */\
-	MUX_VAL(CP(SDRC_D24),		(IEN  | PTD | DIS | M0)) /* SDRC_D24 */\
-	MUX_VAL(CP(SDRC_D25),		(IEN  | PTD | DIS | M0)) /* SDRC_D25 */\
-	MUX_VAL(CP(SDRC_D26),		(IEN  | PTD | DIS | M0)) /* SDRC_D26 */\
-	MUX_VAL(CP(SDRC_D27),		(IEN  | PTD | DIS | M0)) /* SDRC_D27 */\
-	MUX_VAL(CP(SDRC_D28),		(IEN  | PTD | DIS | M0)) /* SDRC_D28 */\
-	MUX_VAL(CP(SDRC_D29),		(IEN  | PTD | DIS | M0)) /* SDRC_D29 */\
-	MUX_VAL(CP(SDRC_D30),		(IEN  | PTD | DIS | M0)) /* SDRC_D30 */\
-	MUX_VAL(CP(SDRC_D31),		(IEN  | PTD | DIS | M0)) /* SDRC_D31 */\
-	MUX_VAL(CP(SDRC_CLK),		(IEN  | PTD | DIS | M0)) /* SDRC_CLK */\
-	MUX_VAL(CP(SDRC_DQS0),		(IEN  | PTD | DIS | M0)) /* SDRC_DQS0 */\
-	MUX_VAL(CP(SDRC_DQS1),		(IEN  | PTD | DIS | M0)) /* SDRC_DQS1 */\
-	MUX_VAL(CP(SDRC_DQS2),		(IEN  | PTD | DIS | M0)) /* SDRC_DQS2 */\
-	MUX_VAL(CP(SDRC_DQS3),		(IEN  | PTD | DIS | M0)) /* SDRC_DQS3 */\
-/* GPMC */\
-	MUX_VAL(CP(GPMC_A1),		(IDIS | PTD | DIS | M0)) /* GPMC_A1 */\
-	MUX_VAL(CP(GPMC_A2),		(IDIS | PTD | DIS | M0)) /* GPMC_A2 */\
-	MUX_VAL(CP(GPMC_A3),		(IDIS | PTD | DIS | M0)) /* GPMC_A3 */\
-	MUX_VAL(CP(GPMC_A4),		(IDIS | PTD | DIS | M0)) /* GPMC_A4 */\
-	MUX_VAL(CP(GPMC_A5),		(IDIS | PTD | DIS | M0)) /* GPMC_A5 */\
-	MUX_VAL(CP(GPMC_A6),		(IDIS | PTD | DIS | M0)) /* GPMC_A6 */\
-	MUX_VAL(CP(GPMC_A7),		(IDIS | PTD | DIS | M0)) /* GPMC_A7 */\
-	MUX_VAL(CP(GPMC_A8),		(IDIS | PTD | DIS | M0)) /* GPMC_A8 */\
-	MUX_VAL(CP(GPMC_A9),		(IDIS | PTD | DIS | M0)) /* GPMC_A9 */\
-	MUX_VAL(CP(GPMC_A10),		(IDIS | PTD | DIS | M0)) /* GPMC_A10 */\
-	MUX_VAL(CP(GPMC_D0),		(IEN  | PTD | DIS | M0)) /* GPMC_D0 */\
-	MUX_VAL(CP(GPMC_D1),		(IEN  | PTD | DIS | M0)) /* GPMC_D1 */\
-	MUX_VAL(CP(GPMC_D2),		(IEN  | PTD | DIS | M0)) /* GPMC_D2 */\
-	MUX_VAL(CP(GPMC_D3),		(IEN  | PTD | DIS | M0)) /* GPMC_D3 */\
-	MUX_VAL(CP(GPMC_D4),		(IEN  | PTD | DIS | M0)) /* GPMC_D4 */\
-	MUX_VAL(CP(GPMC_D5),		(IEN  | PTD | DIS | M0)) /* GPMC_D5 */\
-	MUX_VAL(CP(GPMC_D6),		(IEN  | PTD | DIS | M0)) /* GPMC_D6 */\
-	MUX_VAL(CP(GPMC_D7),		(IEN  | PTD | DIS | M0)) /* GPMC_D7 */\
-	MUX_VAL(CP(GPMC_D8),		(IEN  | PTD | DIS | M0)) /* GPMC_D8 */\
-	MUX_VAL(CP(GPMC_D9),		(IEN  | PTD | DIS | M0)) /* GPMC_D9 */\
-	MUX_VAL(CP(GPMC_D10),		(IEN  | PTD | DIS | M0)) /* GPMC_D10 */\
-	MUX_VAL(CP(GPMC_D11),		(IEN  | PTD | DIS | M0)) /* GPMC_D11 */\
-	MUX_VAL(CP(GPMC_D12),		(IEN  | PTD | DIS | M0)) /* GPMC_D12 */\
-	MUX_VAL(CP(GPMC_D13),		(IEN  | PTD | DIS | M0)) /* GPMC_D13 */\
-	MUX_VAL(CP(GPMC_D14),		(IEN  | PTD | DIS | M0)) /* GPMC_D14 */\
-	MUX_VAL(CP(GPMC_D15),		(IEN  | PTD | DIS | M0)) /* GPMC_D15 */\
-	MUX_VAL(CP(GPMC_NCS0),		(IDIS | PTU | EN  | M0)) /* GPMC_nCS0 */\
-	MUX_VAL(CP(GPMC_NCS1),		(IDIS | PTU | EN  | M7)) /* GPMC_nCS1 */\
-	MUX_VAL(CP(GPMC_NCS2),		(IDIS | PTU | EN  | M7)) /* GPMC_nCS2 */\
-	MUX_VAL(CP(GPMC_NCS3),		(IDIS | PTU | EN  | M7)) /* GPMC_nCS3 */\
-	MUX_VAL(CP(GPMC_NCS4),		(IDIS | PTU | EN  | M7)) /* GPMC_nCS4 */\
-	MUX_VAL(CP(GPMC_NCS5),		(IDIS | PTD | DIS | M7)) /* GPMC_nCS5 */\
-	MUX_VAL(CP(GPMC_NCS6),		(IEN  | PTD | DIS | M7)) /* GPMC_nCS6 */\
-	MUX_VAL(CP(GPMC_NCS7),		(IEN  | PTU | EN  | M7)) /* GPMC_nCS7 */\
-	MUX_VAL(CP(GPMC_CLK),		(IDIS | PTD | DIS | M0)) /* GPMC_CLK */\
-	MUX_VAL(CP(GPMC_NADV_ALE),	(IDIS | PTD | DIS | M0)) /* GPMC_nADV_ALE */\
-	MUX_VAL(CP(GPMC_NOE),		(IDIS | PTD | DIS | M0)) /* GPMC_nOE */\
-	MUX_VAL(CP(GPMC_NWE),		(IDIS | PTD | DIS | M0)) /* GPMC_nWE */\
-	MUX_VAL(CP(GPMC_NWP),		(IDIS | PTU | DIS | M0)) /* GPMC_nWP */\
-	MUX_VAL(CP(GPMC_NBE0_CLE),	(IDIS | PTD | DIS | M0)) /* GPMC_nBE0_CLE */\
-	MUX_VAL(CP(GPMC_NBE1),		(IEN  | PTD | DIS | M0)) /* GPMC_nBE1 */\
-	MUX_VAL(CP(GPMC_WAIT0),		(IEN  | PTD | EN  | M0)) /* GPMC_WAIT0 */\
-	MUX_VAL(CP(GPMC_WAIT1),		(IEN  | PTU | EN  | M0)) /* GPMC_WAIT1 */\
-	MUX_VAL(CP(GPMC_WAIT2),		(IEN  | PTU | EN  | M0)) /* GPMC_WAIT2 */\
-	MUX_VAL(CP(GPMC_WAIT3),		(IEN  | PTU | EN  | M0)) /* GPMC_WAIT3 */\
-/* IDCC modem Power On */\
-	MUX_VAL(CP(CAM_D11),		(IEN  | PTU | EN  | M4)) /* GPIO_110 */\
-	MUX_VAL(CP(CAM_D4),		(IEN  | PTU | EN  | M4)) /* GPIO_103 */\
-/* GPMC CS7 has LAN9211 device */\
-	MUX_VAL(CP(GPMC_NCS7),		(IDIS | PTU | EN  | M0)) /* GPMC_nCS7 */\
-	MUX_VAL(CP(MCBSP1_DX),		(IEN  | PTD | DIS | M4)) /* LAN9221 */\
-	MUX_VAL(CP(MCSPI1_CS2),		(IEN  | PTD | EN  | M0)) /* MCSPI1_CS2 */\
-/* GPMC CS3 has Serial TL16CP754C device */\
-	MUX_VAL(CP(GPMC_NCS3),		(IDIS | PTU | EN  | M0)) /* GPMC_nCS3 */\
-/* Toggle Reset pin of TL16CP754C device */\
-	MUX_VAL(CP(MCBSP4_CLKX),	(IEN  | PTU | EN  | M4)) /* GPIO_152 */\
- udelay(10);\
-	MUX_VAL(CP(MCBSP4_CLKX),	(IEN  | PTD | EN  | M4)) /* GPIO_152 */\
-	MUX_VAL(CP(SDRC_CKE1),		(IDIS | PTU | EN  | M0)) /* SDRC_CKE1 */\
-/* LEDS */\
-	MUX_VAL(CP(MCSPI1_SOMI),	(IEN  | PTD | EN  | M4)) /* GPIO_173 red  */\
-	MUX_VAL(CP(MCBSP4_DX),		(IEN  | PTD | EN  | M4)) /* GPIO_154 blue */\
-	MUX_VAL(CP(GPMC_NBE1),		(IEN  | PTD | EN  | M4)) /* GPIO_61 blue2 */
-
-#endif /* _BOARD_ZOOM2_H_ */
diff --git a/board/logicpd/zoom2/zoom2_serial.c b/board/logicpd/zoom2/zoom2_serial.c
deleted file mode 100644
index 2959276116..0000000000
--- a/board/logicpd/zoom2/zoom2_serial.c
+++ /dev/null
@@ -1,130 +0,0 @@
-/*
- * Copyright (c) 2009 Wind River Systems, Inc.
- * Tom Rix <Tom.Rix@windriver.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- *
- * This file was adapted from arch/powerpc/cpu/mpc5xxx/serial.c
- */
-
-#include <common.h>
-#include <serial.h>
-#include <ns16550.h>
-#include <asm/arch/cpu.h>
-#include "zoom2_serial.h"
-
-int quad_init_dev (unsigned long base)
-{
-	/*
-	 * The Quad UART is on the debug board.
-	 * Check if the debug board is attached before using the UART
-	 */
-	if (zoom2_debug_board_connected ()) {
-		NS16550_t com_port = (NS16550_t) base;
-		int baud_divisor = CONFIG_SYS_NS16550_CLK / 16 /
-			CONFIG_BAUDRATE;
-
-		/*
-		 * Zoom2 has a board specific initialization of its UART.
-		 * This generic initialization has been copied from
-		 * drivers/serial/ns16550.c. The macros have been expanded.
-		 *
-		 * Do the following instead of
-		 *
-		 * NS16550_init (com_port, clock_divisor);
-		 */
-		com_port->ier = 0x00;
-
-		/*
-		 * On Zoom2 board Set pre-scalar to 1
-		 * CLKSEL is GND => MCR[7] is 1 => preslr is 4
-		 * So change the prescl to 1
-		 */
-		com_port->lcr = 0xBF;
-		com_port->fcr |= 0x10;
-		com_port->mcr &= 0x7F;
-
-		/* This is generic ns16550.c setup */
-		com_port->lcr = UART_LCR_BKSE | UART_LCR_8N1;
-		com_port->dll = 0;
-		com_port->dlm = 0;
-		com_port->lcr = UART_LCR_8N1;
-		com_port->mcr = UART_MCR_DTR | UART_MCR_RTS;
-		com_port->fcr = UART_FCR_FIFO_EN | UART_FCR_RXSR |
-			UART_FCR_TXSR;
-		com_port->lcr = UART_LCR_BKSE | UART_LCR_8N1;
-		com_port->dll = baud_divisor & 0xff;
-		com_port->dlm = (baud_divisor >> 8) & 0xff;
-		com_port->lcr = UART_LCR_8N1;
-	}
-	/*
-	 * We have to lie here, otherwise the board init code will hang
-	 * on the check
-	 */
-	return 0;
-}
-
-void quad_putc_dev (unsigned long base, const char c)
-{
-	if (zoom2_debug_board_connected ()) {
-
-		if (c == '\n')
-			quad_putc_dev (base, '\r');
-
-		NS16550_putc ((NS16550_t) base, c);
-	} else {
-		usbtty_putc(c);
-	}
-}
-
-void quad_puts_dev (unsigned long base, const char *s)
-{
-	if (zoom2_debug_board_connected ()) {
-		while ((s != NULL) && (*s != '\0'))
-			quad_putc_dev (base, *s++);
-	} else {
-		usbtty_puts(s);
-	}
-}
-
-int quad_getc_dev (unsigned long base)
-{
-	if (zoom2_debug_board_connected ())
-		return NS16550_getc ((NS16550_t) base);
-
-	return usbtty_getc();
-}
-
-int quad_tstc_dev (unsigned long base)
-{
-	if (zoom2_debug_board_connected ())
-		return NS16550_tstc ((NS16550_t) base);
-
-	return usbtty_tstc();
-}
-
-void quad_setbrg_dev (unsigned long base)
-{
-	if (zoom2_debug_board_connected ()) {
-
-		int clock_divisor = CONFIG_SYS_NS16550_CLK / 16 /
-			CONFIG_BAUDRATE;
-
-		NS16550_reinit ((NS16550_t) base, clock_divisor);
-	}
-}
-
-QUAD_INIT (0)
-QUAD_INIT (1)
-QUAD_INIT (2)
-QUAD_INIT (3)
-
-struct serial_device *default_serial_console(void)
-{
-	switch (ZOOM2_DEFAULT_SERIAL_DEVICE) {
-	case 0: return &zoom2_serial_device0;
-	case 1: return &zoom2_serial_device1;
-	case 2: return &zoom2_serial_device2;
-	case 3: return &zoom2_serial_device3;
-	}
-}
diff --git a/board/logicpd/zoom2/zoom2_serial.h b/board/logicpd/zoom2/zoom2_serial.h
deleted file mode 100644
index 82244521ac..0000000000
--- a/board/logicpd/zoom2/zoom2_serial.h
+++ /dev/null
@@ -1,59 +0,0 @@
-/*
- * Copyright (c) 2009 Wind River Systems, Inc.
- * Tom Rix <Tom.Rix@windriver.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef ZOOM2_SERIAL_H
-#define ZOOM2_SERIAL_H
-
-#include <linux/stringify.h>
-
-extern int zoom2_debug_board_connected (void);
-
-#define SERIAL_TL16CP754C_BASE	0x10000000	/* Zoom2 Serial chip address */
-
-#define QUAD_BASE_0	SERIAL_TL16CP754C_BASE
-#define QUAD_BASE_1	(SERIAL_TL16CP754C_BASE + 0x100)
-#define QUAD_BASE_2	(SERIAL_TL16CP754C_BASE + 0x200)
-#define QUAD_BASE_3	(SERIAL_TL16CP754C_BASE + 0x300)
-
-#define QUAD_INIT(n)				\
-int quad_init_##n(void)				\
-{						\
-	return quad_init_dev(QUAD_BASE_##n);	\
-}						\
-void quad_setbrg_##n(void)			\
-{						\
-	quad_setbrg_dev(QUAD_BASE_##n);		\
-}						\
-void quad_putc_##n(const char c)		\
-{						\
-	quad_putc_dev(QUAD_BASE_##n, c);	\
-}						\
-void quad_puts_##n(const char *s)		\
-{						\
-	quad_puts_dev(QUAD_BASE_##n, s);	\
-}						\
-int quad_getc_##n(void)				\
-{						\
-	return quad_getc_dev(QUAD_BASE_##n);	\
-}						\
-int quad_tstc_##n(void)				\
-{						\
-	return quad_tstc_dev(QUAD_BASE_##n);	\
-}						\
-struct serial_device zoom2_serial_device##n =	\
-{						\
-	.name	= __stringify(n),		\
-	.start	= quad_init_##n,		\
-	.stop	= NULL,				\
-	.setbrg	= quad_setbrg_##n,		\
-	.getc	= quad_getc_##n,		\
-	.tstc	= quad_tstc_##n,		\
-	.putc	= quad_putc_##n,		\
-	.puts	= quad_puts_##n,		\
-};
-
-#endif /* ZOOM2_SERIAL_H */
diff --git a/board/lubbock/Makefile b/board/lubbock/Makefile
index 7b7f51a7bb..8aa513ac44 100644
--- a/board/lubbock/Makefile
+++ b/board/lubbock/Makefile
@@ -1,4 +1,3 @@
-
 #
 # (C) Copyright 2000-2006
 # Wolfgang Denk, DENX Software Engineering, wd@denx.de.
@@ -6,23 +5,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	:= lubbock.o flash.o
-
-SRCS	:= $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	:= lubbock.o flash.o
diff --git a/board/lwmon/Makefile b/board/lwmon/Makefile
index e1ac275ccd..599a61378e 100644
--- a/board/lwmon/Makefile
+++ b/board/lwmon/Makefile
@@ -5,24 +5,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	= $(BOARD).o flash.o pcmcia.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	= lwmon.o flash.o pcmcia.o
diff --git a/board/lwmon5/Makefile b/board/lwmon5/Makefile
index 05cb635c9f..02478ca0c8 100644
--- a/board/lwmon5/Makefile
+++ b/board/lwmon5/Makefile
@@ -5,27 +5,5 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	= $(BOARD).o kbd.o sdram.o
-SOBJS	= init.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-all:	$(LIB) $(SOBJS)
-
-$(LIB):	$(OBJS)
-	$(call cmd_link_o_target, $^)
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	= lwmon5.o kbd.o sdram.o
+extra-y	+= init.o
diff --git a/board/manroland/hmi1001/Makefile b/board/manroland/hmi1001/Makefile
index 3acd06bba7..c29a665cc3 100644
--- a/board/manroland/hmi1001/Makefile
+++ b/board/manroland/hmi1001/Makefile
@@ -5,24 +5,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	:= $(BOARD).o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	:= hmi1001.o
diff --git a/board/manroland/mucmc52/Makefile b/board/manroland/mucmc52/Makefile
index 0bec8af8d5..927fc3250a 100644
--- a/board/manroland/mucmc52/Makefile
+++ b/board/manroland/mucmc52/Makefile
@@ -8,24 +8,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	:= $(BOARD).o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	:= mucmc52.o
diff --git a/board/manroland/uc100/Makefile b/board/manroland/uc100/Makefile
index fe15aefa7e..8e69c52de1 100644
--- a/board/manroland/uc100/Makefile
+++ b/board/manroland/uc100/Makefile
@@ -5,25 +5,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-#COBJS	= $(BOARD).o flash.o pcmcia.o
-COBJS	= $(BOARD).o pcmcia.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	= uc100.o pcmcia.o
diff --git a/board/manroland/uc101/Makefile b/board/manroland/uc101/Makefile
index 3acd06bba7..9289d915d9 100644
--- a/board/manroland/uc101/Makefile
+++ b/board/manroland/uc101/Makefile
@@ -5,24 +5,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	:= $(BOARD).o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	:= uc101.o
diff --git a/board/matrix_vision/common/Makefile b/board/matrix_vision/common/Makefile
index 8593a8633e..699da1ca27 100644
--- a/board/matrix_vision/common/Makefile
+++ b/board/matrix_vision/common/Makefile
@@ -5,28 +5,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-ifneq ($(OBJTREE),$(SRCTREE))
-$(shell mkdir -p $(obj)board/$(VENDOR)/common)
-endif
-
-LIB	= $(obj)lib$(VENDOR).o
-
-COBJS-y	= mv_common.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS-y))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	= mv_common.o
diff --git a/board/matrix_vision/mergerbox/Makefile b/board/matrix_vision/mergerbox/Makefile
index 4df8ce20f9..11a7fd2c7c 100644
--- a/board/matrix_vision/mergerbox/Makefile
+++ b/board/matrix_vision/mergerbox/Makefile
@@ -5,25 +5,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS-y += $(BOARD).o pci.o fpga.o sm107.o
-
-COBJS	:= $(COBJS-y)
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y += mergerbox.o pci.o fpga.o sm107.o
diff --git a/board/matrix_vision/mvbc_p/Makefile b/board/matrix_vision/mvbc_p/Makefile
index 61474aaf8b..4c1994156f 100644
--- a/board/matrix_vision/mvbc_p/Makefile
+++ b/board/matrix_vision/mvbc_p/Makefile
@@ -8,21 +8,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	:= $(BOARD).o fpga.o
-
-SRCS    := $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS    := $(addprefix $(obj),$(COBJS))
-SOBJS   := $(addprefix $(obj),$(SOBJS))
-
-$(LIB): $(obj).depend $(OBJS)
-		$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
+obj-y	:= mvbc_p.o fpga.o
diff --git a/board/matrix_vision/mvblm7/.gitignore b/board/matrix_vision/mvblm7/.gitignore
new file mode 100644
index 0000000000..469f1bc4c1
--- /dev/null
+++ b/board/matrix_vision/mvblm7/.gitignore
@@ -0,0 +1 @@
+bootscript.img
diff --git a/board/matrix_vision/mvblm7/Makefile b/board/matrix_vision/mvblm7/Makefile
index b65728092d..9ed2837a78 100644
--- a/board/matrix_vision/mvblm7/Makefile
+++ b/board/matrix_vision/mvblm7/Makefile
@@ -4,24 +4,15 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
+obj-y	:= mvblm7.o pci.o fpga.o
 
-LIB	= $(obj)lib$(BOARD).o
+extra-y := bootscript.img
 
-COBJS	:= $(BOARD).o pci.o fpga.o
+quiet_cmd_mkimage = MKIMAGE $@
+cmd_mkimage = $(objtree)/tools/mkimage $(MKIMAGEFLAGS_$(@F)) -d $< $@ \
+        $(if $(KBUILD_VERBOSE:1=), >/dev/null)
 
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
+MKIMAGEFLAGS_bootscript.image := -T script -C none -n M7_script
 
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-	@mkimage -T script -C none -n M7_script -d bootscript $(obj)bootscript.img
-
-#########################################################################
-
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+$(obj)/bootscript.img: $(src)/bootscript
+	$(call cmd,mkimage)
diff --git a/board/matrix_vision/mvblx/Makefile b/board/matrix_vision/mvblx/Makefile
index 169376136a..c056ebaf78 100644
--- a/board/matrix_vision/mvblx/Makefile
+++ b/board/matrix_vision/mvblx/Makefile
@@ -5,27 +5,7 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
+obj-y += mvblx.o fpga.o
+obj-$(CONFIG_ID_EEPROM) += sys_eeprom.o
 
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS-y += mvblx.o fpga.o
-COBJS-$(CONFIG_ID_EEPROM) += sys_eeprom.o
-COBJS	:= $(COBJS-y)
-
-SRCS	:= $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-
-CFLAGS += -Werror
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+ccflags-y += -Werror
diff --git a/board/matrix_vision/mvsmr/.gitignore b/board/matrix_vision/mvsmr/.gitignore
new file mode 100644
index 0000000000..469f1bc4c1
--- /dev/null
+++ b/board/matrix_vision/mvsmr/.gitignore
@@ -0,0 +1 @@
+bootscript.img
diff --git a/board/matrix_vision/mvsmr/Makefile b/board/matrix_vision/mvsmr/Makefile
index ef768feb72..a9c794e21a 100644
--- a/board/matrix_vision/mvsmr/Makefile
+++ b/board/matrix_vision/mvsmr/Makefile
@@ -8,22 +8,15 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
+obj-y	:= mvsmr.o fpga.o
 
-LIB	= $(obj)lib$(BOARD).o
+extra-y := bootscript.img
 
-COBJS	:= $(BOARD).o fpga.o
+quiet_cmd_mkimage = MKIMAGE $@
+cmd_mkimage = $(objtree)/tools/mkimage $(MKIMAGEFLAGS_$(@F)) -d $< $@ \
+        $(if $(KBUILD_VERBOSE:1=), >/dev/null)
 
-SRCS    := $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS    := $(addprefix $(obj),$(COBJS))
-SOBJS   := $(addprefix $(obj),$(SOBJS))
+MKIMAGEFLAGS_bootscript.image := -T script -C none -n mvSMR_Script
 
-$(LIB): $(obj).depend $(OBJS)
-		$(call cmd_link_o_target, $(OBJS))
-	@mkimage -T script -C none -n mvSMR_Script -d bootscript $(obj)bootscript.img
-
-#########################################################################
-
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
+$(obj)/bootscript.img: $(src)/bootscript
+	$(call cmd,mkimage)
diff --git a/board/matrix_vision/mvsmr/u-boot.lds b/board/matrix_vision/mvsmr/u-boot.lds
index 08ce014aac..e885b7c160 100644
--- a/board/matrix_vision/mvsmr/u-boot.lds
+++ b/board/matrix_vision/mvsmr/u-boot.lds
@@ -18,7 +18,7 @@ SECTIONS
     /* the first two sectors (=8KB) of our S29GL flash chip */
     arch/powerpc/cpu/mpc5xxx/start.o	(.text*)
     arch/powerpc/cpu/mpc5xxx/traps.o	(.text*)
-    board/matrix_vision/common/libmatrix_vision.o (.text*)
+    board/matrix_vision/common/built-in.o	(.text*)
 
     /* This is only needed to force failure if size of above code will ever */
     /* increase and grow into reserved space. */
diff --git a/board/mbx8xx/Makefile b/board/mbx8xx/Makefile
index 1097314052..2074b6b904 100644
--- a/board/mbx8xx/Makefile
+++ b/board/mbx8xx/Makefile
@@ -5,24 +5,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	= $(BOARD).o flash.o vpd.o pcmcia.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	= mbx8xx.o flash.o vpd.o pcmcia.o
diff --git a/board/mcc200/Makefile b/board/mcc200/Makefile
index 5019b315f6..db3b39646a 100644
--- a/board/mcc200/Makefile
+++ b/board/mcc200/Makefile
@@ -5,24 +5,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	:= $(BOARD).o lcd.o auto_update.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	:= mcc200.o lcd.o auto_update.o
diff --git a/board/micronas/vct/Makefile b/board/micronas/vct/Makefile
index ff35a5a402..ed28cb81bf 100644
--- a/board/micronas/vct/Makefile
+++ b/board/micronas/vct/Makefile
@@ -4,32 +4,11 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS-y := $(BOARD).o
-COBJS-y += ebi.o
-COBJS-$(CONFIG_VCT_NOR) += ebi_nor_flash.o
-COBJS-$(CONFIG_VCT_ONENAND) += ebi_onenand.o
-COBJS-$(CONFIG_DRIVER_SMC911X) += ebi_smc911x.o smc_eeprom.o
-COBJS-y += gpio.o
-COBJS-y += top.o
-COBJS-$(CONFIG_USB_EHCI_VCT) += dcgu.o ehci.o scc.o
-
-COBJS	:= $(sort $(COBJS-y))
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(OBJS) $(SOBJS)
-	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y := vct.o
+obj-y += ebi.o
+obj-$(CONFIG_VCT_NOR) += ebi_nor_flash.o
+obj-$(CONFIG_VCT_ONENAND) += ebi_onenand.o
+obj-$(CONFIG_DRIVER_SMC911X) += ebi_smc911x.o smc_eeprom.o
+obj-y += gpio.o
+obj-y += top.o
+obj-$(CONFIG_USB_EHCI_VCT) += dcgu.o ehci.o scc.o
diff --git a/board/micronas/vct/config.mk b/board/micronas/vct/config.mk
index 0f004e0ee0..354d918474 100644
--- a/board/micronas/vct/config.mk
+++ b/board/micronas/vct/config.mk
@@ -8,8 +8,6 @@
 # vct_xxx boards with MIPS 4Kc CPU core
 #
 
-sinclude $(TOPDIR)/board/$(BOARDDIR)/config.tmp
-
 ifndef CONFIG_SYS_TEXT_BASE
 CONFIG_SYS_TEXT_BASE = 0x87000000
 endif
diff --git a/board/mimc/mimc200/Makefile b/board/mimc/mimc200/Makefile
index 955a9c558b..5c30c0dbca 100644
--- a/board/mimc/mimc200/Makefile
+++ b/board/mimc/mimc200/Makefile
@@ -3,23 +3,4 @@
 #
 # SPDX-License-Identifier:	GPL-2.0+
 
-include $(TOPDIR)/config.mk
-
-LIB	:= $(obj)lib$(BOARD).o
-
-COBJS	:= $(BOARD).o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS))
-
-$(LIB): $(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	:= mimc200.o
diff --git a/board/miromico/hammerhead/Makefile b/board/miromico/hammerhead/Makefile
index 3a2a8eba01..638a9df930 100644
--- a/board/miromico/hammerhead/Makefile
+++ b/board/miromico/hammerhead/Makefile
@@ -3,23 +3,4 @@
 #
 # SPDX-License-Identifier:	GPL-2.0+
 
-include $(TOPDIR)/config.mk
-
-LIB	:= $(obj)lib$(BOARD).o
-
-COBJS	:= $(BOARD).o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS))
-
-$(LIB): $(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	:= hammerhead.o
diff --git a/board/mosaixtech/icon/Makefile b/board/mosaixtech/icon/Makefile
index 23a8631eb0..d554a8bcb9 100644
--- a/board/mosaixtech/icon/Makefile
+++ b/board/mosaixtech/icon/Makefile
@@ -5,27 +5,6 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS-y	:= $(BOARD).o
-COBJS-$(CONFIG_CMD_CHIP_CONFIG) += chip_config.o
-SOBJS	= init.o
-
-COBJS   := $(COBJS-y)
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	:= icon.o
+obj-$(CONFIG_CMD_CHIP_CONFIG) += chip_config.o
+extra-y	+= init.o
diff --git a/board/motionpro/Makefile b/board/motionpro/Makefile
index 4a7d872afa..898a384c39 100644
--- a/board/motionpro/Makefile
+++ b/board/motionpro/Makefile
@@ -5,24 +5,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	:= $(BOARD).o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	:= motionpro.o
diff --git a/board/mousse/Makefile b/board/mousse/Makefile
index 9566cc86b2..e2951d54ad 100644
--- a/board/mousse/Makefile
+++ b/board/mousse/Makefile
@@ -1,4 +1,3 @@
-
 #
 # (C) Copyright 2001-2006
 # Wolfgang Denk, DENX Software Engineering, wd@denx.de.
@@ -6,23 +5,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	= $(BOARD).o m48t59y.o pci.o flash.o
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	= mousse.o m48t59y.o pci.o flash.o
diff --git a/board/mpc8308_p1m/Makefile b/board/mpc8308_p1m/Makefile
index 31127f082b..fb8ca3a007 100644
--- a/board/mpc8308_p1m/Makefile
+++ b/board/mpc8308_p1m/Makefile
@@ -7,24 +7,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	:= $(BOARD).o sdram.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	:= mpc8308_p1m.o sdram.o
diff --git a/board/mpl/common/usb_uhci.c b/board/mpl/common/usb_uhci.c
index ff7ce828c6..5590be1962 100644
--- a/board/mpl/common/usb_uhci.c
+++ b/board/mpl/common/usb_uhci.c
@@ -584,7 +584,7 @@ void handle_usb_interrupt(void)
 
 /* init uhci
  */
-int usb_lowlevel_init(int index, void **controller)
+int usb_lowlevel_init(int index, enum usb_init_type init, void **controller)
 {
 	unsigned char temp;
 	int	busdevfunc;
@@ -640,118 +640,9 @@ static void usb_display_wValue(unsigned short wValue,unsigned short wIndex) {}
 static void usb_display_Req(unsigned short req) {}
 #endif
 
-static unsigned char root_hub_dev_des[] =
-{
-	0x12,			/*  __u8  bLength; */
-	0x01,			/*  __u8  bDescriptorType; Device */
-	0x00,			/*  __u16 bcdUSB; v1.0 */
-	0x01,
-	0x09,			/*  __u8  bDeviceClass; HUB_CLASSCODE */
-	0x00,			/*  __u8  bDeviceSubClass; */
-	0x00,			/*  __u8  bDeviceProtocol; */
-	0x08,			/*  __u8  bMaxPacketSize0; 8 Bytes */
-	0x00,			/*  __u16 idVendor; */
-	0x00,
-	0x00,			/*  __u16 idProduct; */
-	0x00,
-	0x00,			/*  __u16 bcdDevice; */
-	0x00,
-	0x01,			/*  __u8  iManufacturer; */
-	0x00,			/*  __u8  iProduct; */
-	0x00,			/*  __u8  iSerialNumber; */
-	0x01			/*  __u8  bNumConfigurations; */
-};
-
-
-/* Configuration descriptor */
-static unsigned char root_hub_config_des[] =
-{
-	0x09,			/*  __u8  bLength; */
-	0x02,			/*  __u8  bDescriptorType; Configuration */
-	0x19,			/*  __u16 wTotalLength; */
-	0x00,
-	0x01,			/*  __u8  bNumInterfaces; */
-	0x01,			/*  __u8  bConfigurationValue; */
-	0x00,			/*  __u8  iConfiguration; */
-	0x40,			/*  __u8  bmAttributes;
-				   Bit 7: Bus-powered, 6: Self-powered, 5 Remote-wakwup, 4..0: resvd */
-	0x00,			/*  __u8  MaxPower; */
-
-     /* interface */
-	0x09,			/*  __u8  if_bLength; */
-	0x04,			/*  __u8  if_bDescriptorType; Interface */
-	0x00,			/*  __u8  if_bInterfaceNumber; */
-	0x00,			/*  __u8  if_bAlternateSetting; */
-	0x01,			/*  __u8  if_bNumEndpoints; */
-	0x09,			/*  __u8  if_bInterfaceClass; HUB_CLASSCODE */
-	0x00,			/*  __u8  if_bInterfaceSubClass; */
-	0x00,			/*  __u8  if_bInterfaceProtocol; */
-	0x00,			/*  __u8  if_iInterface; */
-
-     /* endpoint */
-	0x07,			/*  __u8  ep_bLength; */
-	0x05,			/*  __u8  ep_bDescriptorType; Endpoint */
-	0x81,			/*  __u8  ep_bEndpointAddress; IN Endpoint 1 */
-	0x03,			/*  __u8  ep_bmAttributes; Interrupt */
-	0x08,			/*  __u16 ep_wMaxPacketSize; 8 Bytes */
-	0x00,
-	0xff			/*  __u8  ep_bInterval; 255 ms */
-};
-
-
-static unsigned char root_hub_hub_des[] =
-{
-	0x09,			/*  __u8  bLength; */
-	0x29,			/*  __u8  bDescriptorType; Hub-descriptor */
-	0x02,			/*  __u8  bNbrPorts; */
-	0x00,			/* __u16  wHubCharacteristics; */
-	0x00,
-	0x01,			/*  __u8  bPwrOn2pwrGood; 2ms */
-	0x00,			/*  __u8  bHubContrCurrent; 0 mA */
-	0x00,			/*  __u8  DeviceRemovable; *** 7 Ports max *** */
-	0xff			/*  __u8  PortPwrCtrlMask; *** 7 ports max *** */
-};
-
-static unsigned char root_hub_str_index0[] =
-{
-	0x04,			/*  __u8  bLength; */
-	0x03,			/*  __u8  bDescriptorType; String-descriptor */
-	0x09,			/*  __u8  lang ID */
-	0x04,			/*  __u8  lang ID */
-};
-
-static unsigned char root_hub_str_index1[] =
-{
-	28,			/*  __u8  bLength; */
-	0x03,			/*  __u8  bDescriptorType; String-descriptor */
-	'U',			/*  __u8  Unicode */
-	0,				/*  __u8  Unicode */
-	'H',			/*  __u8  Unicode */
-	0,				/*  __u8  Unicode */
-	'C',			/*  __u8  Unicode */
-	0,				/*  __u8  Unicode */
-	'I',			/*  __u8  Unicode */
-	0,				/*  __u8  Unicode */
-	' ',			/*  __u8  Unicode */
-	0,				/*  __u8  Unicode */
-	'R',			/*  __u8  Unicode */
-	0,				/*  __u8  Unicode */
-	'o',			/*  __u8  Unicode */
-	0,				/*  __u8  Unicode */
-	'o',			/*  __u8  Unicode */
-	0,				/*  __u8  Unicode */
-	't',			/*  __u8  Unicode */
-	0,				/*  __u8  Unicode */
-	' ',			/*  __u8  Unicode */
-	0,				/*  __u8  Unicode */
-	'H',			/*  __u8  Unicode */
-	0,				/*  __u8  Unicode */
-	'u',			/*  __u8  Unicode */
-	0,				/*  __u8  Unicode */
-	'b',			/*  __u8  Unicode */
-	0,				/*  __u8  Unicode */
-};
-
+#define WANT_USB_ROOT_HUB_HUB_DES
+#include <usbroothubdes.h>
+#undef WANT_USB_ROOT_HUB_HUB_DES
 
 /*
  * Root Hub Control Pipe (interrupt Pipes are not supported)
diff --git a/board/mpl/mip405/Makefile b/board/mpl/mip405/Makefile
index 4eb997f164..5bcf130501 100644
--- a/board/mpl/mip405/Makefile
+++ b/board/mpl/mip405/Makefile
@@ -5,32 +5,8 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-ifneq ($(OBJTREE),$(SRCTREE))
-$(shell mkdir -p $(obj)../common)
-endif
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	= $(BOARD).o cmd_mip405.o \
+obj-y	= mip405.o cmd_mip405.o \
 		../common/pci.o \
 		../common/usb_uhci.o \
 		../common/common_util.o
-
-SOBJS	= init.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(OBJS) $(SOBJS)
-	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	+= init.o
diff --git a/board/mpl/mip405/init.S b/board/mpl/mip405/init.S
index 642f17c35b..2ea2e29c3b 100644
--- a/board/mpl/mip405/init.S
+++ b/board/mpl/mip405/init.S
@@ -19,7 +19,6 @@
  *	Bank 6 - not used
  *	Bank 7 - PLD Register
  *-----------------------------------------------------------------------------*/
-#define _LINUX_CONFIG_H 1	/* avoid reading Linux autoconf.h file	*/
 
 #include <configs/MIP405.h>
 #include <ppc_asm.tmpl>
diff --git a/board/mpl/pati/Makefile b/board/mpl/pati/Makefile
index bddf012a00..9822082612 100644
--- a/board/mpl/pati/Makefile
+++ b/board/mpl/pati/Makefile
@@ -5,28 +5,5 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-ifneq ($(OBJTREE),$(SRCTREE))
-$(shell mkdir -p $(obj)../common)
-endif
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	:=  $(BOARD).o cmd_pati.o \
+obj-y	:=  pati.o cmd_pati.o \
 		../common/common_util.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
diff --git a/board/mpl/pati/pci_eeprom.h b/board/mpl/pati/pci_eeprom.h
index af34b86c31..459c14381d 100644
--- a/board/mpl/pati/pci_eeprom.h
+++ b/board/mpl/pati/pci_eeprom.h
@@ -1,4 +1,3 @@
-
 #ifndef __PCI_EEPROM_H_
 #define __PCI_EEPROM_H_	1
 
diff --git a/board/mpl/pip405/Makefile b/board/mpl/pip405/Makefile
index 0d40d3ab5f..0a3d059e9c 100644
--- a/board/mpl/pip405/Makefile
+++ b/board/mpl/pip405/Makefile
@@ -5,34 +5,10 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-ifneq ($(OBJTREE),$(SRCTREE))
-$(shell mkdir -p $(obj)../common)
-endif
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	= $(BOARD).o cmd_pip405.o \
+obj-y	= pip405.o cmd_pip405.o \
 		../common/pci.o \
 		../common/isa.o \
 		../common/kbd.o \
 		../common/usb_uhci.o \
 		../common/common_util.o
-
-SOBJS	= init.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(OBJS) $(SOBJS)
-	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	+= init.o
diff --git a/board/mpl/pip405/init.S b/board/mpl/pip405/init.S
index 95fed34fcc..292393ec43 100644
--- a/board/mpl/pip405/init.S
+++ b/board/mpl/pip405/init.S
@@ -19,7 +19,6 @@
  *	Bank 6 - used to switch on the 12V for the Multipurpose socket
  *	Bank 7 - Config Register
  *-----------------------------------------------------------------------------*/
-#define _LINUX_CONFIG_H 1	/* avoid reading Linux autoconf.h file	*/
 
 #include <configs/PIP405.h>
 #include <ppc_asm.tmpl>
diff --git a/board/mpl/vcma9/Makefile b/board/mpl/vcma9/Makefile
index a6f924d09a..175a19fa36 100644
--- a/board/mpl/vcma9/Makefile
+++ b/board/mpl/vcma9/Makefile
@@ -5,30 +5,7 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-ifneq ($(OBJTREE),$(SRCTREE))
-$(shell mkdir -p $(obj)../common)
-endif
+obj-y	:= ../common/common_util.o
+obj-y	+= vcma9.o cmd_vcma9.o
 
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	:= ../common/common_util.o
-COBJS	+= $(BOARD).o cmd_$(BOARD).o
-
-SOBJS	:= lowlevel_init.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
-	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	+= lowlevel_init.o
diff --git a/board/mpl/vcma9/lowlevel_init.S b/board/mpl/vcma9/lowlevel_init.S
index b889cf94af..cca9c0c880 100644
--- a/board/mpl/vcma9/lowlevel_init.S
+++ b/board/mpl/vcma9/lowlevel_init.S
@@ -197,13 +197,10 @@
 #define REFCNT_266		0
 /**************************************/
 
-_TEXT_BASE:
-	.word	CONFIG_SYS_TEXT_BASE
-
 .globl lowlevel_init
 lowlevel_init:
 	/* use r0 to relocate DATA read/write to flash rather than memory ! */
-	ldr	r0, _TEXT_BASE
+	ldr	r0, =CONFIG_SYS_TEXT_BASE
 	ldr	r13, =BWSCON
 
 	/* enable minimal access to PLD */
diff --git a/board/mpr2/Makefile b/board/mpr2/Makefile
index 7920b01b49..b6cdeb4efa 100644
--- a/board/mpr2/Makefile
+++ b/board/mpr2/Makefile
@@ -15,25 +15,5 @@
 #
 # SPDX-License-Identifier:	GPL-2.0+
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	:= mpr2.o
-SOBJS	:= lowlevel_init.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(OBJS) $(SOBJS)
-	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	:= mpr2.o
+obj-y	+= lowlevel_init.o
diff --git a/board/ms7720se/Makefile b/board/ms7720se/Makefile
index 219649cd6b..1819c4c10d 100644
--- a/board/ms7720se/Makefile
+++ b/board/ms7720se/Makefile
@@ -12,25 +12,5 @@
 #
 # SPDX-License-Identifier:	GPL-2.0+
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	:= ms7720se.o
-SOBJS	:= lowlevel_init.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(OBJS) $(SOBJS)
-	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	:= ms7720se.o
+obj-y	+= lowlevel_init.o
diff --git a/board/ms7722se/Makefile b/board/ms7722se/Makefile
index e73ceb284f..9f7af78738 100644
--- a/board/ms7722se/Makefile
+++ b/board/ms7722se/Makefile
@@ -9,25 +9,5 @@
 #
 # SPDX-License-Identifier:	GPL-2.0+
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	:= ms7722se.o
-SOBJS	:= lowlevel_init.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(OBJS) $(SOBJS)
-	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	:= ms7722se.o
+obj-y	+= lowlevel_init.o
diff --git a/board/ms7750se/Makefile b/board/ms7750se/Makefile
index 481c8bb954..a8e3ca0acf 100644
--- a/board/ms7750se/Makefile
+++ b/board/ms7750se/Makefile
@@ -4,25 +4,6 @@
 #
 # SPDX-License-Identifier:	GPL-2.0+
 #
-include $(TOPDIR)/config.mk
 
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	:= ms7750se.o
-SOBJS	:= lowlevel_init.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(OBJS) $(SOBJS)
-	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	:= ms7750se.o
+obj-y	+= lowlevel_init.o
diff --git a/board/muas3001/Makefile b/board/muas3001/Makefile
index b4b784a742..ef04960931 100644
--- a/board/muas3001/Makefile
+++ b/board/muas3001/Makefile
@@ -5,24 +5,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	:= $(BOARD).o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	:= muas3001.o
diff --git a/board/munices/Makefile b/board/munices/Makefile
index 97fc2b6ce4..d16e2a1fa2 100644
--- a/board/munices/Makefile
+++ b/board/munices/Makefile
@@ -5,24 +5,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	:= $(BOARD).o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	:= munices.o
diff --git a/board/musenki/Makefile b/board/musenki/Makefile
index e9558412e1..d2b79ffd22 100644
--- a/board/musenki/Makefile
+++ b/board/musenki/Makefile
@@ -5,24 +5,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	= $(BOARD).o flash.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	= musenki.o flash.o
diff --git a/board/mvblue/Makefile b/board/mvblue/Makefile
index e9558412e1..76c10f8fd8 100644
--- a/board/mvblue/Makefile
+++ b/board/mvblue/Makefile
@@ -5,24 +5,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	= $(BOARD).o flash.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	= mvblue.o flash.o
diff --git a/board/mvblue/u-boot.lds b/board/mvblue/u-boot.lds
index 121354bfeb..5034a9675a 100644
--- a/board/mvblue/u-boot.lds
+++ b/board/mvblue/u-boot.lds
@@ -14,12 +14,12 @@ SECTIONS
   .text      :
   {
     arch/powerpc/cpu/mpc824x/start.o		(.text*)
-    lib/libgeneric.o				(.text*)
-    net/libnet.o				(.text*)
-    drivers/pci/libpci.o			(.text*)
-    arch/powerpc/cpu/mpc824x/libmpc824x.o	(.text*)
-    board/mvblue/libmvblue.o			(.text*)
-    arch/powerpc/lib/libpowerpc.o		(.text*)
+    lib/built-in.o				(.text*)
+    net/built-in.o				(.text*)
+    drivers/pci/built-in.o			(.text*)
+    arch/powerpc/cpu/mpc824x/built-in.o		(.text*)
+    board/mvblue/built-in.o			(.text*)
+    arch/powerpc/lib/built-in.o			(.text*)
 
     . = DEFINED(env_offset) ? env_offset : .;
     common/env_embedded.o	(.ppcenv*)
diff --git a/board/mx1ads/Makefile b/board/mx1ads/Makefile
deleted file mode 100644
index e34e18217f..0000000000
--- a/board/mx1ads/Makefile
+++ /dev/null
@@ -1,36 +0,0 @@
-#
-# board/mx1ads/Makefile
-#
-# (C) Copyright 2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# (c) Copyright 2004
-# Techware Information Technology, Inc.
-# http://www.techware.com.tw/
-#
-# Ming-Len Wu <minglen_wu@techware.com.tw>
-#
-# SPDX-License-Identifier:	GPL-2.0+
-
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	:= mx1ads.o syncflash.o
-SOBJS	:= lowlevel_init.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
-	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
diff --git a/board/mx1ads/lowlevel_init.S b/board/mx1ads/lowlevel_init.S
deleted file mode 100644
index d1e472a933..0000000000
--- a/board/mx1ads/lowlevel_init.S
+++ /dev/null
@@ -1,68 +0,0 @@
-/*
- * board/mx1ads/lowlevel_init.S
- *
- * (c) Copyright 2004
- * Techware Information Technology, Inc.
- * http://www.techware.com.tw/
- *
- * Ming-Len Wu <minglen_wu@techware.com.tw>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <config.h>
-#include <version.h>
-
-#define SDCTL0			0x221000
-#define SDCTL1			0x221004
-
-
-_TEXT_BASE:
-	.word	CONFIG_SYS_TEXT_BASE
-
-.globl lowlevel_init
-lowlevel_init:
-/* memory controller init		*/
-
-	ldr  r1, =SDCTL0
-
-/*  Set Precharge Command		*/
-
-	ldr  r3, =0x92120200
-/*	ldr  r3, =0x92120251
-*/
-	str  r3, [r1]
-
-/* Issue Precharge All Commad		*/
-	ldr  r3, =0x8200000
-	ldr  r2, [r3]
-
-/* Set AutoRefresh Command		*/
-	ldr  r3, =0xA2120200
-	str  r3, [r1]
-
-/* Issue AutoRefresh Command		*/
-	ldr  r3, =0x8000000
-	ldr  r2, [r3]
-	ldr  r2, [r3]
-	ldr  r2, [r3]
-	ldr  r2, [r3]
-	ldr  r2, [r3]
-	ldr  r2, [r3]
-	ldr  r2, [r3]
-	ldr  r2, [r3]
-
-/* Set Mode Register			*/
-	ldr  r3, =0xB2120200
-	str  r3, [r1]
-
-/* Issue Mode Register Command		*/
-	ldr  r3, =0x08111800	/* Mode Register Value		*/
-	ldr  r2, [r3]
-
-/* Set Normal Mode			*/
-	ldr  r3, =0x82124200
-	str  r3, [r1]
-
-/* everything is fine now		*/
-	mov	pc, lr
diff --git a/board/mx1ads/mx1ads.c b/board/mx1ads/mx1ads.c
deleted file mode 100644
index 4266048981..0000000000
--- a/board/mx1ads/mx1ads.c
+++ /dev/null
@@ -1,178 +0,0 @@
-/*
- * board/mx1ads/mx1ads.c
- *
- * (c) Copyright 2004
- * Techware Information Technology, Inc.
- * http://www.techware.com.tw/
- *
- * Ming-Len Wu <minglen_wu@techware.com.tw>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <netdev.h>
-/*#include <mc9328.h>*/
-#include <asm/arch/imx-regs.h>
-#include <asm/io.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#define FCLK_SPEED 1
-
-#if FCLK_SPEED==0		/* Fout = 203MHz, Fin = 12MHz for Audio */
-#define M_MDIV	0xC3
-#define M_PDIV	0x4
-#define M_SDIV	0x1
-#elif FCLK_SPEED==1		/* Fout = 202.8MHz */
-#define M_MDIV	0xA1
-#define M_PDIV	0x3
-#define M_SDIV	0x1
-#endif
-
-#define USB_CLOCK 1
-
-#if USB_CLOCK==0
-#define U_M_MDIV	0xA1
-#define U_M_PDIV	0x3
-#define U_M_SDIV	0x1
-#elif USB_CLOCK==1
-#define U_M_MDIV	0x48
-#define U_M_PDIV	0x3
-#define U_M_SDIV	0x2
-#endif
-
-#if 0
-
-static inline void delay (unsigned long loops)
-{
-	__asm__ volatile ("1:\n"
-			  "subs %0, %1, #1\n"
-			  "bne 1b":"=r" (loops):"0" (loops));
-}
-
-#endif
-
-/*
- * Miscellaneous platform dependent initialisations
- */
-
-void SetAsynchMode (void)
-{
-	__asm__ ("mrc p15,0,r0,c1,c0,0 \n"
-		 "mov r2, #0xC0000000 \n"
-		 "orr r0,r2,r0 \n" "mcr p15,0,r0,c1,c0,0 \n");
-}
-
-static u32 mc9328sid;
-
-int board_early_init_f(void)
-{
-	mc9328sid = SIDR;
-
-	GPCR = 0x000003AB;	/* I/O pad driving strength     */
-
-	/*	MX1_CS1U	= 0x00000A00;	*/ /* SRAM initialization          */
-/*	MX1_CS1L	= 0x11110601;	*/
-
-	MPCTL0 = 0x04632410;	/* setting for 150 MHz MCU PLL CLK      */
-
-/* set FCLK divider 1 (i.e. FCLK to MCU PLL CLK) and
- * BCLK divider to 2 (i.e. BCLK to 48 MHz)
- */
-	CSCR = 0xAF000403;
-
-	CSCR |= 0x00200000;	/* Trigger the restart bit(bit 21)      */
-	CSCR &= 0xFFFF7FFF;	/* Program PRESC bit(bit 15) to 0 to divide-by-1 */
-
-/* setup cs4 for cs8900 ethernet */
-
-	CS4U = 0x00000F00;	/* Initialize CS4 for CS8900 ethernet   */
-	CS4L = 0x00001501;
-
-	GIUS (0) &= 0xFF3FFFFF;
-	GPR (0) &= 0xFF3FFFFF;
-
-	readl(0x1500000C);
-	readl(0x1500000C);
-
-	SetAsynchMode ();
-
-	icache_enable ();
-	dcache_enable ();
-
-/* set PERCLKs				*/
-	PCDR = 0x00000055;	/* set PERCLKS                          */
-
-/* PERCLK3 is only used by SSI so the SSI driver can set it any value it likes
- * PERCLK1 and PERCLK2 are shared so DO NOT change it in any other place
- * all sources selected as normal interrupt
- */
-
-/*	MX1_INTTYPEH = 0;
-	MX1_INTTYPEL = 0;
-*/
-	return 0;
-}
-
-int board_init(void)
-{
-	gd->bd->bi_arch_number = MACH_TYPE_MX1ADS;
-
-	gd->bd->bi_boot_params = 0x08000100;	/* adress of boot parameters */
-
-	return 0;
-}
-
-int board_late_init (void)
-{
-
-	setenv ("stdout", "serial");
-	setenv ("stderr", "serial");
-
-	switch (mc9328sid) {
-	case 0x0005901d:
-		printf ("MX1ADS board with MC9328 MX1 (0L44N), Silicon ID 0x%08x \n\n",
-			mc9328sid);
-		break;
-	case 0x04d4c01d:
-		printf ("MX1ADS board with MC9328 MXL (1L45N), Silicon ID 0x%08x \n\n",
-			mc9328sid);
-		break;
-	case 0x00d4c01d:
-		printf ("MX1ADS board with MC9328 MXL (2L45N), Silicon ID 0x%08x \n\n",
-			mc9328sid);
-		break;
-
-	default:
-		printf ("MX1ADS board with UNKNOWN MC9328 cpu, Silicon ID 0x%08x \n",
-			mc9328sid);
-		break;
-	}
-	return 0;
-}
-
-int dram_init(void)
-{
-	/* dram_init must store complete ramsize in gd->ram_size */
-	gd->ram_size = get_ram_size((void *)PHYS_SDRAM_1,
-				PHYS_SDRAM_1_SIZE);
-	return 0;
-}
-
-void dram_init_banksize(void)
-{
-	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
-	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
-}
-
-#ifdef CONFIG_CMD_NET
-int board_eth_init(bd_t *bis)
-{
-	int rc = 0;
-#ifdef CONFIG_CS8900
-	rc = cs8900_initialize(0, CONFIG_CS8900_BASE);
-#endif
-	return rc;
-}
-#endif
diff --git a/board/mx1ads/syncflash.c b/board/mx1ads/syncflash.c
deleted file mode 100644
index 5d685338fb..0000000000
--- a/board/mx1ads/syncflash.c
+++ /dev/null
@@ -1,307 +0,0 @@
-/*
- * board/mx1ads/syncflash.c
- *
- * (c) Copyright 2004
- * Techware Information Technology, Inc.
- * http://www.techware.com.tw/
- *
- * Ming-Len Wu <minglen_wu@techware.com.tw>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-/*#include <mc9328.h>*/
-#include <asm/arch/imx-regs.h>
-
-typedef unsigned long * p_u32;
-
-/* 4Mx16x2 IAM=0 CSD1 */
-
-flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];	/* info for FLASH chips    */
-
-/*  Following Setting is for CSD1	*/
-#define SFCTL			0x00221004
-#define reg_SFCTL		__REG(SFCTL)
-
-#define SYNCFLASH_A10		(0x00100000)
-
-#define CMD_NORMAL		(0x81020300)			/* Normal Mode			*/
-#define CMD_PREC		(CMD_NORMAL + 0x10000000)	/* Precharge Command		*/
-#define CMD_AUTO		(CMD_NORMAL + 0x20000000)	/* Auto Refresh Command		*/
-#define CMD_LMR			(CMD_NORMAL + 0x30000000)	/* Load Mode Register Command	*/
-#define CMD_LCR			(CMD_NORMAL + 0x60000000)	/* LCR Command			*/
-#define CMD_PROGRAM		(CMD_NORMAL + 0x70000000)
-
-#define MODE_REG_VAL		(CONFIG_SYS_FLASH_BASE+0x0008CC00)	/* Cas Latency 3		*/
-
-/* LCR Command */
-#define LCR_READSTATUS		(0x0001C000)			/* 0x70				*/
-#define LCR_ERASE_CONFIRM	(0x00008000)			/* 0x20				*/
-#define LCR_ERASE_NVMODE	(0x0000C000)			/* 0x30				*/
-#define LCR_PROG_NVMODE		(0x00028000)			/* 0xA0				*/
-#define LCR_SR_CLEAR		(0x00014000)			/* 0x50				*/
-
-/* Get Status register			*/
-u32 SF_SR(void) {
-	u32 tmp;
-
-	reg_SFCTL	= CMD_PROGRAM;
-	tmp		= __REG(CONFIG_SYS_FLASH_BASE);
-
-	reg_SFCTL	= CMD_NORMAL;
-
-	reg_SFCTL	= CMD_LCR;			/* Activate LCR Mode		*/
-	__REG(CONFIG_SYS_FLASH_BASE + LCR_SR_CLEAR);
-
-	return tmp;
-}
-
-/* check if SyncFlash is ready		*/
-u8 SF_Ready(void) {
-	u32 tmp;
-
-	tmp	= SF_SR();
-
-	if ((tmp & 0x00800000) && (tmp & 0x001C0000)) {
-		printf ("SyncFlash Error code %08x\n",tmp);
-	};
-
-	if ((tmp & 0x00000080) && (tmp & 0x0000001C)) {
-		printf ("SyncFlash Error code %08x\n",tmp);
-	};
-
-	if (tmp == 0x00800080)		/* Test Bit 7 of SR	*/
-		return 1;
-	else
-		return 0;
-}
-
-/* Issue the precharge all command		*/
-void SF_PrechargeAll(void) {
-
-	/* Set Precharge Command	*/
-	reg_SFCTL	= CMD_PREC;
-	/* Issue Precharge All Command */
-	__REG(CONFIG_SYS_FLASH_BASE + SYNCFLASH_A10);
-}
-
-/* set SyncFlash to normal mode			*/
-void SF_Normal(void) {
-
-	SF_PrechargeAll();
-
-	reg_SFCTL	= CMD_NORMAL;
-}
-
-/* Erase SyncFlash				*/
-void SF_Erase(u32 RowAddress) {
-
-	reg_SFCTL	= CMD_NORMAL;
-	__REG(RowAddress);
-
-	reg_SFCTL	= CMD_PREC;
-	__REG(RowAddress);
-
-	reg_SFCTL	= CMD_LCR;			/* Set LCR mode		*/
-	__REG(RowAddress + LCR_ERASE_CONFIRM)	= 0;	/* Issue Erase Setup Command	*/
-
-	reg_SFCTL	= CMD_NORMAL;			/* return to Normal mode	*/
-	__REG(RowAddress)	= 0xD0D0D0D0;		/* Confirm			*/
-
-	while(!SF_Ready());
-}
-
-void SF_NvmodeErase(void) {
-	SF_PrechargeAll();
-
-	reg_SFCTL	= CMD_LCR;			/* Set to LCR mode		*/
-	__REG(CONFIG_SYS_FLASH_BASE + LCR_ERASE_NVMODE)  = 0;	/* Issue Erase Nvmode Reg Command */
-
-	reg_SFCTL	= CMD_NORMAL;			/* Return to Normal mode	*/
-	__REG(CONFIG_SYS_FLASH_BASE + LCR_ERASE_NVMODE) = 0xC0C0C0C0;	/* Confirm		*/
-
-	while(!SF_Ready());
-}
-
-void SF_NvmodeWrite(void) {
-	SF_PrechargeAll();
-
-	reg_SFCTL	= CMD_LCR;			/* Set to LCR mode		*/
-	__REG(CONFIG_SYS_FLASH_BASE+LCR_PROG_NVMODE) = 0;	/* Issue Program Nvmode reg command */
-
-	reg_SFCTL	= CMD_NORMAL;			/* Return to Normal mode	*/
-	__REG(CONFIG_SYS_FLASH_BASE+LCR_PROG_NVMODE) = 0xC0C0C0C0;	/* Confirm not needed	*/
-}
-
-/****************************************************************************************/
-
-ulong flash_init(void) {
-	int i, j;
-
-/* Turn on CSD1 for negating RESETSF of SyncFLash */
-
-	reg_SFCTL	|= 0x80000000;		/* enable CSD1 for SyncFlash		*/
-	udelay(200);
-
-	reg_SFCTL	= CMD_LMR;		/* Set Load Mode Register Command	*/
-	__REG(MODE_REG_VAL);	/* Issue Load Mode Register Command	*/
-
-	SF_Normal();
-
-	i = 0;
-
-	flash_info[i].flash_id	=  FLASH_MAN_MT | FLASH_MT28S4M16LC;
-
-	flash_info[i].size	= FLASH_BANK_SIZE;
-	flash_info[i].sector_count = CONFIG_SYS_MAX_FLASH_SECT;
-
-	memset(flash_info[i].protect, 0, CONFIG_SYS_MAX_FLASH_SECT);
-
-	for (j = 0; j < flash_info[i].sector_count; j++) {
-		flash_info[i].start[j] = CONFIG_SYS_FLASH_BASE + j * 0x00100000;
-	}
-
-	flash_protect(FLAG_PROTECT_SET,
-		CONFIG_SYS_FLASH_BASE,
-		CONFIG_SYS_FLASH_BASE + monitor_flash_len - 1,
-		&flash_info[0]);
-
-	flash_protect(FLAG_PROTECT_SET,
-		CONFIG_ENV_ADDR,
-		CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1,
-		&flash_info[0]);
-
-	return FLASH_BANK_SIZE;
-}
-
-void flash_print_info (flash_info_t *info) {
-
-	int i;
-
-	switch (info->flash_id & FLASH_VENDMASK) {
-		case (FLASH_MAN_MT & FLASH_VENDMASK):
-			printf("Micron: ");
-			break;
-		default:
-			printf("Unknown Vendor ");
-			break;
-	}
-
-	switch (info->flash_id & FLASH_TYPEMASK) {
-		case (FLASH_MT28S4M16LC & FLASH_TYPEMASK):
-			printf("2x FLASH_MT28S4M16LC (16MB Total)\n");
-			break;
-		default:
-			printf("Unknown Chip Type\n");
-			return;
-			break;
-	}
-
-	printf("  Size: %ld MB in %d Sectors\n",
-		info->size >> 20, info->sector_count);
-
-	printf("  Sector Start Addresses: ");
-
-	for (i = 0; i < info->sector_count; i++) {
-		if ((i % 5) == 0)
-			printf ("\n   ");
-
-		printf (" %08lX%s", info->start[i],
-			info->protect[i] ? " (RO)" : "     ");
-	}
-
-	printf ("\n");
-}
-
-/*-----------------------------------------------------------------------*/
-
-int flash_erase (flash_info_t *info, int s_first, int s_last) {
-	int iflag, cflag, prot, sect;
-	int rc = ERR_OK;
-
-/* first look for protection bits */
-
-	if (info->flash_id == FLASH_UNKNOWN)
-		return ERR_UNKNOWN_FLASH_TYPE;
-
-	if ((s_first < 0) || (s_first > s_last))
-		return ERR_INVAL;
-
-	if ((info->flash_id & FLASH_VENDMASK) != (FLASH_MAN_MT & FLASH_VENDMASK))
-		return ERR_UNKNOWN_FLASH_VENDOR;
-
-	prot = 0;
-
-	for (sect = s_first; sect <= s_last; ++sect) {
-		if (info->protect[sect])
-			prot++;
-	}
-
-	if (prot) {
-		printf("protected!\n");
-		return ERR_PROTECTED;
-	}
-/*
- * Disable interrupts which might cause a timeout
- * here. Remember that our exception vectors are
- * at address 0 in the flash, and we don't want a
- * (ticker) exception to happen while the flash
- * chip is in programming mode.
- */
-
-	cflag = icache_status();
-	icache_disable();
-	iflag = disable_interrupts();
-
-/* Start erase on unprotected sectors */
-	for (sect = s_first; sect <= s_last && !ctrlc(); sect++) {
-
-		printf("Erasing sector %2d ... ", sect);
-
-/* arm simple, non interrupt dependent timer */
-
-		get_timer(0);
-
-		SF_NvmodeErase();
-		SF_NvmodeWrite();
-
-		SF_Erase(CONFIG_SYS_FLASH_BASE + (0x0100000 * sect));
-		SF_Normal();
-
-		printf("ok.\n");
-	}
-
-	if (ctrlc())
-		printf("User Interrupt!\n");
-
-	if (iflag)
-		enable_interrupts();
-
-	if (cflag)
-		icache_enable();
-
-	return rc;
-}
-
-/*-----------------------------------------------------------------------
- * Copy memory to flash.
- */
-
-int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) {
-	int i;
-
-	for(i = 0; i < cnt; i += 4) {
-
-		SF_PrechargeAll();
-
-		reg_SFCTL	= CMD_PROGRAM;		/* Enter SyncFlash Program mode */
-		__REG(addr + i) = __REG((u32)src  + i);
-
-		while(!SF_Ready());
-	}
-
-	SF_Normal();
-
-	return ERR_OK;
-}
diff --git a/board/netphone/Makefile b/board/netphone/Makefile
index 4d86589d8e..ba3460577f 100644
--- a/board/netphone/Makefile
+++ b/board/netphone/Makefile
@@ -5,24 +5,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	= $(BOARD).o flash.o phone_console.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	= netphone.o flash.o phone_console.o
diff --git a/board/netta/Makefile b/board/netta/Makefile
index 3b5408868e..98bac7ed46 100644
--- a/board/netta/Makefile
+++ b/board/netta/Makefile
@@ -5,24 +5,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	= $(BOARD).o flash.o dsp.o codec.o pcmcia.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	= netta.o flash.o dsp.o codec.o pcmcia.o
diff --git a/board/netta2/Makefile b/board/netta2/Makefile
index 871865b6ee..c3bfb0d305 100644
--- a/board/netta2/Makefile
+++ b/board/netta2/Makefile
@@ -5,24 +5,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	= $(BOARD).o flash.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	= netta2.o flash.o
diff --git a/board/netvia/Makefile b/board/netvia/Makefile
index 871865b6ee..b667bc9b82 100644
--- a/board/netvia/Makefile
+++ b/board/netvia/Makefile
@@ -5,24 +5,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	= $(BOARD).o flash.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	= netvia.o flash.o
diff --git a/board/nokia/rx51/Makefile b/board/nokia/rx51/Makefile
index 2772a24dc6..8d4d97b9a9 100644
--- a/board/nokia/rx51/Makefile
+++ b/board/nokia/rx51/Makefile
@@ -5,26 +5,5 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS-y	:= $(BOARD).o
-SOBJS-y := lowlevel_init.o
-
-COBJS	:= $(sort $(COBJS-y))
-SOBJS	:= $(sort $(SOBJS-y))
-SRCS	:= $(COBJS:.o=.c) $(SOBJS:.o=.S)
-OBJS	:= $(addprefix $(obj),$(COBJS)) $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y := rx51.o
+obj-y += lowlevel_init.o
diff --git a/board/nokia/rx51/rx51.h b/board/nokia/rx51/rx51.h
index 4a230dd596..0d2f0a54c5 100644
--- a/board/nokia/rx51/rx51.h
+++ b/board/nokia/rx51/rx51.h
@@ -22,8 +22,6 @@ struct emu_hal_params_rx51 {
 	u32 param4;
 };
 
-int print_cpuinfo(void);
-
 /*
  * IEN  - Input Enable
  * IDIS - Input Disable
diff --git a/board/nvidia/beaver/Makefile b/board/nvidia/beaver/Makefile
index 9510f607ab..1f7c31d64b 100644
--- a/board/nvidia/beaver/Makefile
+++ b/board/nvidia/beaver/Makefile
@@ -14,25 +14,4 @@
 # along with this program.  If not, see <http://www.gnu.org/licenses/>.
 #
 
-include $(TOPDIR)/config.mk
-
-$(shell mkdir -p $(obj)../cardhu)
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	= ../cardhu/cardhu.o
-
-SRCS	:= $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	= ../cardhu/cardhu.o
diff --git a/board/nvidia/cardhu/Makefile b/board/nvidia/cardhu/Makefile
index 4a92d7a86d..3f9b55f6a7 100644
--- a/board/nvidia/cardhu/Makefile
+++ b/board/nvidia/cardhu/Makefile
@@ -5,23 +5,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	:= $(BOARD).o
-
-SRCS	:= $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	:= cardhu.o
diff --git a/board/nvidia/common/Makefile b/board/nvidia/common/Makefile
index 6215cafe25..e3b2651570 100644
--- a/board/nvidia/common/Makefile
+++ b/board/nvidia/common/Makefile
@@ -1,30 +1,4 @@
 # Copyright (c) 2011 The Chromium OS Authors.
 # SPDX-License-Identifier:	GPL-2.0+
 
-include $(TOPDIR)/config.mk
-
-ifneq ($(OBJTREE),$(SRCTREE))
-$(shell mkdir -p $(obj)board/$(VENDOR)/common)
-endif
-
-LIB	= $(obj)lib$(VENDOR).o
-
-include common.mk
-
-COBJS	:= $(COBJS-y)
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-all:	$(LIB)
-
-$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
-	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
-
-#########################################################################
-# This is for $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+include $(src)/common.mk
diff --git a/board/nvidia/common/board.c b/board/nvidia/common/board.c
index 126e56e97a..3b18e28cc4 100644
--- a/board/nvidia/common/board.c
+++ b/board/nvidia/common/board.c
@@ -32,6 +32,7 @@
 #ifdef CONFIG_USB_EHCI_TEGRA
 #include <asm/arch-tegra/usb.h>
 #include <asm/arch/usb.h>
+#include <usb.h>
 #endif
 #ifdef CONFIG_TEGRA_MMC
 #include <asm/arch-tegra/tegra_mmc.h>
@@ -47,17 +48,6 @@ const struct tegra_sysinfo sysinfo = {
 	CONFIG_TEGRA_BOARD_STRING
 };
 
-#ifndef CONFIG_SPL_BUILD
-/*
- * Routine: timer_init
- * Description: init the timestamp and lastinc value
- */
-int timer_init(void)
-{
-	return 0;
-}
-#endif
-
 void __pin_mux_usb(void)
 {
 }
@@ -77,12 +67,14 @@ void __gpio_early_init_uart(void)
 void gpio_early_init_uart(void)
 __attribute__((weak, alias("__gpio_early_init_uart")));
 
+#if defined(CONFIG_TEGRA_NAND)
 void __pin_mux_nand(void)
 {
 	funcmux_select(PERIPH_ID_NDFLASH, FUNCMUX_DEFAULT);
 }
 
 void pin_mux_nand(void) __attribute__((weak, alias("__pin_mux_nand")));
+#endif
 
 void __pin_mux_display(void)
 {
@@ -153,8 +145,9 @@ int board_init(void)
 
 #ifdef CONFIG_USB_EHCI_TEGRA
 	pin_mux_usb();
-	board_usb_init(gd->fdt_blob);
+	usb_process_devicetree(gd->fdt_blob);
 #endif
+
 #ifdef CONFIG_LCD
 	tegra_lcd_check_next_stage(gd->fdt_blob, 0);
 #endif
diff --git a/board/nvidia/common/common.mk b/board/nvidia/common/common.mk
index d9bcb85401..9a9b5298c7 100644
--- a/board/nvidia/common/common.mk
+++ b/board/nvidia/common/common.mk
@@ -1,3 +1,3 @@
 # common options for all tegra boards
-COBJS-y	+= ../../nvidia/common/board.o
-COBJS-$(CONFIG_TEGRA_CLOCK_SCALING) += ../../nvidia/common/emc.o
+obj-y	+= ../../nvidia/common/board.o
+obj-$(CONFIG_TEGRA_CLOCK_SCALING) += ../../nvidia/common/emc.o
diff --git a/board/nvidia/dalmore/Makefile b/board/nvidia/dalmore/Makefile
index 699b9f6cc6..7cdff9c61b 100644
--- a/board/nvidia/dalmore/Makefile
+++ b/board/nvidia/dalmore/Makefile
@@ -14,23 +14,4 @@
 # along with this program.  If not, see <http://www.gnu.org/licenses/>.
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	:= $(BOARD).o
-
-SRCS	:= $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	:= dalmore.o
diff --git a/board/nvidia/dalmore/pinmux-config-dalmore.h b/board/nvidia/dalmore/pinmux-config-dalmore.h
index 8c05a1517c..9dcd5e42af 100644
--- a/board/nvidia/dalmore/pinmux-config-dalmore.h
+++ b/board/nvidia/dalmore/pinmux-config-dalmore.h
@@ -132,8 +132,8 @@ static struct pingroup_config tegra114_pinmux_common[] = {
 	DEFAULT_PINMUX(ULPI_STP,      ULPI,        NORMAL,    NORMAL,   OUTPUT),
 
 	/* I2C3 pinmux */
-	I2C_PINMUX(CAM_I2C_SCL, I2C3, NORMAL, NORMAL, INPUT, DEFAULT, DISABLE),
-	I2C_PINMUX(CAM_I2C_SDA, I2C3, NORMAL, NORMAL, INPUT, DEFAULT, DISABLE),
+	I2C_PINMUX(CAM_I2C_SCL, I2C3, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE),
+	I2C_PINMUX(CAM_I2C_SDA, I2C3, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE),
 
 	/* VI pinmux */
 	VI_PINMUX(CAM_MCLK, VI_ALT3,  NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
@@ -145,8 +145,8 @@ static struct pingroup_config tegra114_pinmux_common[] = {
 	VI_PINMUX(GPIO_PBB4, VGP4,    NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
 
 	/* I2C2 pinmux */
-	I2C_PINMUX(GEN2_I2C_SCL, I2C2, NORMAL, NORMAL, INPUT, DEFAULT, DISABLE),
-	I2C_PINMUX(GEN2_I2C_SDA, I2C2, NORMAL, NORMAL, INPUT, DEFAULT, DISABLE),
+	I2C_PINMUX(GEN2_I2C_SCL, I2C2, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE),
+	I2C_PINMUX(GEN2_I2C_SDA, I2C2, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE),
 
 	/* UARTD pinmux */
 	DEFAULT_PINMUX(GMI_A16,       UARTD,       NORMAL,    NORMAL,   OUTPUT),
@@ -224,8 +224,8 @@ static struct pingroup_config tegra114_pinmux_common[] = {
 	DEFAULT_PINMUX(KB_ROW9,       UARTA,       NORMAL,    NORMAL,   OUTPUT),
 
 	/* I2CPWR pinmux (I2C5) */
-	I2C_PINMUX(PWR_I2C_SCL, I2CPWR, NORMAL, NORMAL, INPUT, DEFAULT, DISABLE),
-	I2C_PINMUX(PWR_I2C_SDA, I2CPWR, NORMAL, NORMAL, INPUT, DEFAULT, DISABLE),
+	I2C_PINMUX(PWR_I2C_SCL, I2CPWR, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE),
+	I2C_PINMUX(PWR_I2C_SDA, I2CPWR, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE),
 
 	/* SYSCLK pinmux */
 	DEFAULT_PINMUX(SYS_CLK_REQ,   SYSCLK,      NORMAL,    NORMAL,   OUTPUT),
@@ -252,8 +252,8 @@ static struct pingroup_config tegra114_pinmux_common[] = {
 	DEFAULT_PINMUX(CLK3_OUT,      EXTPERIPH3,  NORMAL,    NORMAL,   OUTPUT),
 
 	/* I2C1 pinmux */
-	I2C_PINMUX(GEN1_I2C_SCL, I2C1, NORMAL, NORMAL, INPUT, DEFAULT, DISABLE),
-	I2C_PINMUX(GEN1_I2C_SDA, I2C1, NORMAL, NORMAL, INPUT, DEFAULT, DISABLE),
+	I2C_PINMUX(GEN1_I2C_SCL, I2C1, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE),
+	I2C_PINMUX(GEN1_I2C_SDA, I2C1, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE),
 
 	/* UARTB pinmux */
 	DEFAULT_PINMUX(UART2_CTS_N,   UARTB,       NORMAL,    TRISTATE, INPUT),
diff --git a/board/nvidia/harmony/Makefile b/board/nvidia/harmony/Makefile
index a55c1f92e0..222b025e9c 100644
--- a/board/nvidia/harmony/Makefile
+++ b/board/nvidia/harmony/Makefile
@@ -5,23 +5,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	:= $(BOARD).o
-
-SRCS	:= $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	:= harmony.o
diff --git a/board/nvidia/seaboard/Makefile b/board/nvidia/seaboard/Makefile
index a55c1f92e0..9171418467 100644
--- a/board/nvidia/seaboard/Makefile
+++ b/board/nvidia/seaboard/Makefile
@@ -5,23 +5,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	:= $(BOARD).o
-
-SRCS	:= $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	:= seaboard.o
diff --git a/board/nvidia/venice2/Makefile b/board/nvidia/venice2/Makefile
new file mode 100644
index 0000000000..5fac5ab1f8
--- /dev/null
+++ b/board/nvidia/venice2/Makefile
@@ -0,0 +1,9 @@
+#
+# (C) Copyright 2013-2014
+# NVIDIA Corporation <www.nvidia.com>
+#
+# SPDX-License-Identifier:     GPL-2.0+
+#
+
+obj-y	+= as3722_init.o
+obj-y	+= venice2.o
diff --git a/board/nvidia/venice2/as3722_init.c b/board/nvidia/venice2/as3722_init.c
new file mode 100644
index 0000000000..960fea7ee7
--- /dev/null
+++ b/board/nvidia/venice2/as3722_init.c
@@ -0,0 +1,91 @@
+/*
+ * (C) Copyright 2013
+ * NVIDIA Corporation <www.nvidia.com>
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch-tegra/tegra_i2c.h>
+#include "as3722_init.h"
+
+/* AS3722-PMIC-specific early init code - get CPU rails up, etc */
+
+void tegra_i2c_ll_write_addr(uint addr, uint config)
+{
+	struct i2c_ctlr *reg = (struct i2c_ctlr *)TEGRA_DVC_BASE;
+
+	writel(addr, &reg->cmd_addr0);
+	writel(config, &reg->cnfg);
+}
+
+void tegra_i2c_ll_write_data(uint data, uint config)
+{
+	struct i2c_ctlr *reg = (struct i2c_ctlr *)TEGRA_DVC_BASE;
+
+	writel(data, &reg->cmd_data1);
+	writel(config, &reg->cnfg);
+}
+
+void pmic_enable_cpu_vdd(void)
+{
+	debug("%s entry\n", __func__);
+
+	/* Don't need to set up VDD_CORE - already done - by OTP */
+
+	debug("%s: Setting VDD_CPU to 1.0V via AS3722 reg 0/4D\n", __func__);
+	/*
+	 * Bring up VDD_CPU via the AS3722 PMIC on the PWR I2C bus.
+	 * First set VDD to 1.0V, then enable the VDD regulator.
+	 */
+	tegra_i2c_ll_write_addr(AS3722_I2C_ADDR, 2);
+	tegra_i2c_ll_write_data(AS3722_SD0VOLTAGE_DATA, I2C_SEND_2_BYTES);
+	/*
+	 * Don't write SDCONTROL - it's already 0x7F, i.e. all SDs enabled.
+	 * tegra_i2c_ll_write_data(AS3722_SD0CONTROL_DATA, I2C_SEND_2_BYTES);
+	 */
+	udelay(10 * 1000);
+
+	debug("%s: Setting VDD_GPU to 1.0V via AS3722 reg 6/4D\n", __func__);
+	/*
+	 * Bring up VDD_GPU via the AS3722 PMIC on the PWR I2C bus.
+	 * First set VDD to 1.0V, then enable the VDD regulator.
+	 */
+	tegra_i2c_ll_write_addr(AS3722_I2C_ADDR, 2);
+	tegra_i2c_ll_write_data(AS3722_SD6VOLTAGE_DATA, I2C_SEND_2_BYTES);
+	/*
+	 * Don't write SDCONTROL - it's already 0x7F, i.e. all SDs enabled.
+	 * tegra_i2c_ll_write_data(AS3722_SD6CONTROL_DATA, I2C_SEND_2_BYTES);
+	 */
+	udelay(10 * 1000);
+
+	debug("%s: Set VPP_FUSE to 1.2V via AS3722 reg 0x12/4E\n", __func__);
+	/*
+	 * Bring up VPP_FUSE via the AS3722 PMIC on the PWR I2C bus.
+	 * First set VDD to 1.2V, then enable the VDD regulator.
+	 */
+	tegra_i2c_ll_write_addr(AS3722_I2C_ADDR, 2);
+	tegra_i2c_ll_write_data(AS3722_LDO2VOLTAGE_DATA, I2C_SEND_2_BYTES);
+	/*
+	 * Don't write LDCONTROL - it's already 0xFF, i.e. all LDOs enabled.
+	 * tegra_i2c_ll_write_data(AS3722_LDO2CONTROL_DATA, I2C_SEND_2_BYTES);
+	 */
+	udelay(10 * 1000);
+
+	debug("%s: Set VDD_SDMMC to 3.3V via AS3722 reg 0x16/4E\n", __func__);
+	/*
+	 * Bring up VDD_SDMMC via the AS3722 PMIC on the PWR I2C bus.
+	 * First set it to bypass 3.3V straight thru, then enable the regulator
+	 *
+	 * NOTE: We do this early because doing it later seems to hose the CPU
+	 * power rail/partition startup. Need to debug.
+	 */
+	tegra_i2c_ll_write_addr(AS3722_I2C_ADDR, 2);
+	tegra_i2c_ll_write_data(AS3722_LDO6VOLTAGE_DATA, I2C_SEND_2_BYTES);
+	/*
+	 * Don't write LDCONTROL - it's already 0xFF, i.e. all LDOs enabled.
+	 * tegra_i2c_ll_write_data(AS3722_LDO6CONTROL_DATA, I2C_SEND_2_BYTES);
+	 */
+	udelay(10 * 1000);
+}
diff --git a/board/nvidia/venice2/as3722_init.h b/board/nvidia/venice2/as3722_init.h
new file mode 100644
index 0000000000..2a9e7cdf87
--- /dev/null
+++ b/board/nvidia/venice2/as3722_init.h
@@ -0,0 +1,38 @@
+/*
+ * (C) Copyright 2013
+ * NVIDIA Corporation <www.nvidia.com>
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+/* AS3722-PMIC-specific early init regs */
+
+#define AS3722_I2C_ADDR		0x80
+
+#define AS3722_SD0VOLTAGE_REG	0x00	/* CPU */
+#define AS3722_SD1VOLTAGE_REG	0x01	/* CORE, already set by OTP */
+#define AS3722_SD6VOLTAGE_REG	0x06	/* GPU */
+#define AS3722_SDCONTROL_REG	0x4D
+
+#define AS3722_LDO2VOLTAGE_REG	0x12	/* VPP_FUSE */
+#define AS3722_LDO6VOLTAGE_REG	0x16	/* VDD_SDMMC */
+#define AS3722_LDCONTROL_REG	0x4E
+
+#define AS3722_SD0VOLTAGE_DATA	(0x2800 | AS3722_SD0VOLTAGE_REG)
+#define AS3722_SD0CONTROL_DATA	(0x0100 | AS3722_SDCONTROL_REG)
+
+#define AS3722_SD1VOLTAGE_DATA	(0x3200 | AS3722_SD1VOLTAGE_REG)
+#define AS3722_SD1CONTROL_DATA	(0x0200 | AS3722_SDCONTROL_REG)
+
+#define AS3722_SD6CONTROL_DATA	(0x4000 | AS3722_SDCONTROL_REG)
+#define AS3722_SD6VOLTAGE_DATA	(0x2800 | AS3722_SD6VOLTAGE_REG)
+
+#define AS3722_LDO2CONTROL_DATA	(0x0400 | AS3722_LDCONTROL_REG)
+#define AS3722_LDO2VOLTAGE_DATA	(0x1000 | AS3722_LDO2VOLTAGE_REG)
+
+#define AS3722_LDO6CONTROL_DATA	(0x4000 | AS3722_LDCONTROL_REG)
+#define AS3722_LDO6VOLTAGE_DATA	(0x3F00 | AS3722_LDO6VOLTAGE_REG)
+
+#define I2C_SEND_2_BYTES	0x0A02
+
+void pmic_enable_cpu_vdd(void);
diff --git a/board/nvidia/venice2/pinmux-config-venice2.h b/board/nvidia/venice2/pinmux-config-venice2.h
new file mode 100644
index 0000000000..b3d68d589a
--- /dev/null
+++ b/board/nvidia/venice2/pinmux-config-venice2.h
@@ -0,0 +1,339 @@
+/*
+ * (C) Copyright 2013
+ * NVIDIA Corporation <www.nvidia.com>
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#ifndef _PINMUX_CONFIG_VENICE2_H_
+#define _PINMUX_CONFIG_VENICE2_H_
+
+#define DEFAULT_PINMUX(_pingroup, _mux, _pull, _tri, _io)	\
+	{							\
+		.pingroup	= PINGRP_##_pingroup,		\
+		.func		= PMUX_FUNC_##_mux,		\
+		.pull		= PMUX_PULL_##_pull,		\
+		.tristate	= PMUX_TRI_##_tri,		\
+		.io		= PMUX_PIN_##_io,		\
+		.lock		= PMUX_PIN_LOCK_DEFAULT,	\
+		.od		= PMUX_PIN_OD_DEFAULT,		\
+		.ioreset	= PMUX_PIN_IO_RESET_DEFAULT,	\
+	}
+
+#define I2C_PINMUX(_pingroup, _mux, _pull, _tri, _io, _lock, _od) \
+	{							\
+		.pingroup	= PINGRP_##_pingroup,		\
+		.func		= PMUX_FUNC_##_mux,		\
+		.pull		= PMUX_PULL_##_pull,		\
+		.tristate	= PMUX_TRI_##_tri,		\
+		.io		= PMUX_PIN_##_io,		\
+		.lock		= PMUX_PIN_LOCK_##_lock,	\
+		.od		= PMUX_PIN_OD_##_od,		\
+		.ioreset	= PMUX_PIN_IO_RESET_DEFAULT,	\
+	}
+
+#define DDC_PINMUX(_pingroup, _mux, _pull, _tri, _io, _lock, _rcv_sel) \
+	{							\
+		.pingroup	= PINGRP_##_pingroup,		\
+		.func		= PMUX_FUNC_##_mux,		\
+		.pull		= PMUX_PULL_##_pull,		\
+		.tristate	= PMUX_TRI_##_tri,		\
+		.io		= PMUX_PIN_##_io,		\
+		.lock		= PMUX_PIN_LOCK_##_lock,	\
+		.rcv_sel	= PMUX_PIN_RCV_SEL_##_rcv_sel,	\
+		.ioreset	= PMUX_PIN_IO_RESET_DEFAULT,	\
+	}
+
+#define VI_PINMUX(_pingroup, _mux, _pull, _tri, _io, _lock, _ioreset) \
+	{							\
+		.pingroup	= PINGRP_##_pingroup,		\
+		.func		= PMUX_FUNC_##_mux,		\
+		.pull		= PMUX_PULL_##_pull,		\
+		.tristate	= PMUX_TRI_##_tri,		\
+		.io		= PMUX_PIN_##_io,		\
+		.lock		= PMUX_PIN_LOCK_##_lock,	\
+		.od		= PMUX_PIN_OD_DEFAULT,		\
+		.ioreset	= PMUX_PIN_IO_RESET_##_ioreset	\
+	}
+
+#define CEC_PINMUX(_pingroup, _mux, _pull, _tri, _io, _lock, _od)	\
+	{								\
+		.pingroup   = PINGRP_##_pingroup,			\
+		.func       = PMUX_FUNC_##_mux,				\
+		.pull       = PMUX_PULL_##_pull,			\
+		.tristate   = PMUX_TRI_##_tri,				\
+		.io         = PMUX_PIN_##_io,				\
+		.lock       = PMUX_PIN_LOCK_##_lock,			\
+		.od         = PMUX_PIN_OD_##_od,			\
+		.ioreset    = PMUX_PIN_IO_RESET_DEFAULT,		\
+	}
+
+#define USB_PINMUX CEC_PINMUX
+
+#define DEFAULT_PADCFG(_padgrp, _slwf, _slwr, _drvup, _drvdn, _lpmd, _schmt, _hsm) \
+	{						\
+		.padgrp = PDRIVE_PINGROUP_##_padgrp,	\
+		.slwf   = _slwf,			\
+		.slwr   = _slwr,			\
+		.drvup  = _drvup,			\
+		.drvdn  = _drvdn,			\
+		.lpmd   = PGRP_LPMD_##_lpmd,		\
+		.schmt  = PGRP_SCHMT_##_schmt,		\
+		.hsm    = PGRP_HSM_##_hsm,		\
+	}
+
+static struct pingroup_config tegra124_pinmux_common[] = {
+	/* EXTPERIPH1 pinmux */
+	DEFAULT_PINMUX(CLK1_OUT,      EXTPERIPH1,  NORMAL,    NORMAL,   OUTPUT),
+
+	/* I2S0 pinmux */
+	DEFAULT_PINMUX(DAP1_DIN,      I2S0,        NORMAL,    TRISTATE, INPUT),
+	DEFAULT_PINMUX(DAP1_DOUT,     I2S0,        NORMAL,    NORMAL,   INPUT),
+	DEFAULT_PINMUX(DAP1_FS,       I2S0,        NORMAL,    NORMAL,   INPUT),
+	DEFAULT_PINMUX(DAP1_SCLK,     I2S0,        NORMAL,    NORMAL,   INPUT),
+
+	/* I2S1 pinmux */
+	DEFAULT_PINMUX(DAP2_DIN,      I2S1,        NORMAL,    TRISTATE, INPUT),
+	DEFAULT_PINMUX(DAP2_DOUT,     I2S1,        NORMAL,    NORMAL,   INPUT),
+	DEFAULT_PINMUX(DAP2_FS,       I2S1,        NORMAL,    NORMAL,   INPUT),
+	DEFAULT_PINMUX(DAP2_SCLK,     I2S1,        NORMAL,    NORMAL,   INPUT),
+
+	/* I2S3 pinmux */
+	DEFAULT_PINMUX(DAP4_DIN,      I2S3,        NORMAL,    NORMAL,   INPUT),
+	DEFAULT_PINMUX(DAP4_DOUT,     I2S3,        NORMAL,    NORMAL,   INPUT),
+	DEFAULT_PINMUX(DAP4_FS,       I2S3,        NORMAL,    NORMAL,   INPUT),
+	DEFAULT_PINMUX(DAP4_SCLK,     I2S3,        NORMAL,    NORMAL,   INPUT),
+
+	/* CLDVFS pinmux */
+	DEFAULT_PINMUX(DVFS_PWM,      CLDVFS,      NORMAL,    NORMAL,   OUTPUT),
+	DEFAULT_PINMUX(DVFS_CLK,      CLDVFS,      NORMAL,    NORMAL,   OUTPUT),
+
+	/* ULPI pinmux */
+	DEFAULT_PINMUX(ULPI_DATA0,    ULPI,        NORMAL,    NORMAL,   INPUT),
+	DEFAULT_PINMUX(ULPI_DATA1,    ULPI,        NORMAL,    NORMAL,   INPUT),
+	DEFAULT_PINMUX(ULPI_DATA2,    ULPI,        NORMAL,    NORMAL,   INPUT),
+	DEFAULT_PINMUX(ULPI_DATA3,    ULPI,        NORMAL,    NORMAL,   INPUT),
+	DEFAULT_PINMUX(ULPI_DATA4,    ULPI,        UP,        NORMAL,   INPUT),
+	DEFAULT_PINMUX(ULPI_DATA5,    ULPI,        UP,        NORMAL,   INPUT),
+	DEFAULT_PINMUX(ULPI_DATA6,    ULPI,        NORMAL,    NORMAL,   INPUT),
+
+	/* EC KBC/SPI */
+	DEFAULT_PINMUX(ULPI_CLK,      SPI1,        UP,        NORMAL,   INPUT),
+	DEFAULT_PINMUX(ULPI_DIR,      SPI1,        UP,        NORMAL,   INPUT),
+	DEFAULT_PINMUX(ULPI_NXT,      SPI1,        NORMAL,    NORMAL,   INPUT),
+	DEFAULT_PINMUX(ULPI_STP,      SPI1,        NORMAL,    NORMAL,   INPUT),
+
+	/* I2C3 (TPM) pinmux */
+	I2C_PINMUX(CAM_I2C_SCL, I2C3, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE),
+	I2C_PINMUX(CAM_I2C_SDA, I2C3, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE),
+
+	/* I2C2 pinmux */
+	I2C_PINMUX(GEN2_I2C_SCL, I2C2, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE),
+	I2C_PINMUX(GEN2_I2C_SDA, I2C2, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE),
+
+	/* UARTD pinmux (UART4 on Servo board, unused) */
+	DEFAULT_PINMUX(GPIO_PJ7,      UARTD,       NORMAL,    NORMAL,   OUTPUT),
+	DEFAULT_PINMUX(GPIO_PB0,      UARTD,       NORMAL,    TRISTATE, INPUT),
+	DEFAULT_PINMUX(GPIO_PB1,      UARTD,       NORMAL,    TRISTATE, INPUT),
+	DEFAULT_PINMUX(GPIO_PK7,      UARTD,       NORMAL,    NORMAL,   OUTPUT),
+
+	/* SPI4 (Winbond 'boot ROM') */
+	DEFAULT_PINMUX(GPIO_PG5,       SPI4,        NORMAL,    NORMAL,   INPUT),
+	DEFAULT_PINMUX(GPIO_PG6,       SPI4,        UP,        NORMAL,   INPUT),
+	DEFAULT_PINMUX(GPIO_PG7,       SPI4,        UP,        NORMAL,   INPUT),
+	DEFAULT_PINMUX(GPIO_PI3,       SPI4,        NORMAL,    NORMAL,   INPUT),
+
+	/* Touch IRQ */
+	DEFAULT_PINMUX(GPIO_W3_AUD,   RSVD1,       NORMAL,    NORMAL,   INPUT),
+
+	/* PWM1 pinmux */
+	DEFAULT_PINMUX(GPIO_PH1,       PWM1,       NORMAL,    NORMAL,   OUTPUT),
+
+	/* SDMMC1 pinmux */
+	DEFAULT_PINMUX(SDMMC1_CLK,    SDMMC1,      NORMAL,    NORMAL,   INPUT),
+	DEFAULT_PINMUX(SDMMC1_CMD,    SDMMC1,      UP,        NORMAL,   INPUT),
+	DEFAULT_PINMUX(SDMMC1_DAT0,   SDMMC1,      UP,        NORMAL,   INPUT),
+	DEFAULT_PINMUX(SDMMC1_DAT1,   SDMMC1,      UP,        NORMAL,   INPUT),
+	DEFAULT_PINMUX(SDMMC1_DAT2,   SDMMC1,      UP,        NORMAL,   INPUT),
+	DEFAULT_PINMUX(SDMMC1_DAT3,   SDMMC1,      UP,        NORMAL,   INPUT),
+
+	/* SDMMC3 pinmux */
+	DEFAULT_PINMUX(SDMMC3_CLK,    SDMMC3,      NORMAL,    NORMAL,   INPUT),
+	DEFAULT_PINMUX(SDMMC3_CMD,    SDMMC3,      UP,        NORMAL,   INPUT),
+	DEFAULT_PINMUX(SDMMC3_DAT0,   SDMMC3,      UP,        NORMAL,   INPUT),
+	DEFAULT_PINMUX(SDMMC3_DAT1,   SDMMC3,      UP,        NORMAL,   INPUT),
+	DEFAULT_PINMUX(SDMMC3_DAT2,   SDMMC3,      UP,        NORMAL,   INPUT),
+	DEFAULT_PINMUX(SDMMC3_DAT3,   SDMMC3,      UP,        NORMAL,   INPUT),
+	DEFAULT_PINMUX(SDMMC3_CLK_LB_IN,  SDMMC3,  UP,        TRISTATE, INPUT),
+	DEFAULT_PINMUX(SDMMC3_CLK_LB_OUT, SDMMC3,  DOWN,      NORMAL,   INPUT),
+
+	/* SDMMC4 pinmux */
+	DEFAULT_PINMUX(SDMMC4_CLK,    SDMMC4,      NORMAL,    NORMAL,   INPUT),
+	DEFAULT_PINMUX(SDMMC4_CMD,    SDMMC4,      UP,        NORMAL,   INPUT),
+	DEFAULT_PINMUX(SDMMC4_DAT0,   SDMMC4,      UP,        NORMAL,   INPUT),
+	DEFAULT_PINMUX(SDMMC4_DAT1,   SDMMC4,      UP,        NORMAL,   INPUT),
+	DEFAULT_PINMUX(SDMMC4_DAT2,   SDMMC4,      UP,        NORMAL,   INPUT),
+	DEFAULT_PINMUX(SDMMC4_DAT3,   SDMMC4,      UP,        NORMAL,   INPUT),
+	DEFAULT_PINMUX(SDMMC4_DAT4,   SDMMC4,      UP,        NORMAL,   INPUT),
+	DEFAULT_PINMUX(SDMMC4_DAT5,   SDMMC4,      UP,        NORMAL,   INPUT),
+	DEFAULT_PINMUX(SDMMC4_DAT6,   SDMMC4,      UP,        NORMAL,   INPUT),
+	DEFAULT_PINMUX(SDMMC4_DAT7,   SDMMC4,      UP,        NORMAL,   INPUT),
+
+	/* BLINK pinmux */
+	DEFAULT_PINMUX(CLK_32K_OUT,   BLINK,       NORMAL,    NORMAL,   OUTPUT),
+
+	/* KBC pinmux */
+	DEFAULT_PINMUX(KB_COL0,       KBC,         UP,        NORMAL,   INPUT),
+	DEFAULT_PINMUX(KB_COL1,       KBC,         UP,        NORMAL,   INPUT),
+	DEFAULT_PINMUX(KB_COL2,       KBC,         UP,        NORMAL,   INPUT),
+	DEFAULT_PINMUX(KB_ROW0,       KBC,         UP,        NORMAL,   INPUT),
+	DEFAULT_PINMUX(KB_ROW1,       KBC,         UP,        NORMAL,   INPUT),
+
+	/* Misc */
+	DEFAULT_PINMUX(GPIO_PV0,      RSVD1,       NORMAL,    TRISTATE, OUTPUT),
+	DEFAULT_PINMUX(KB_ROW7,       RSVD1,       UP,        NORMAL,   INPUT),
+
+	/* UARTA pinmux (BR_UART_TXD/RXD on Servo board) */
+	DEFAULT_PINMUX(KB_ROW9,       UARTA,       UP,        NORMAL,   OUTPUT),
+	DEFAULT_PINMUX(KB_ROW10,      UARTA,       UP,        TRISTATE, INPUT),
+
+	/* I2CPWR pinmux (I2C5) */
+	I2C_PINMUX(PWR_I2C_SCL, I2CPWR, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE),
+	I2C_PINMUX(PWR_I2C_SDA, I2CPWR, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE),
+
+	/* RTCK pinmux */
+	DEFAULT_PINMUX(JTAG_RTCK,     RTCK,        NORMAL,    NORMAL,   INPUT),
+
+	/* CLK pinmux */
+	DEFAULT_PINMUX(CLK_32K_IN,    CLK,         NORMAL,    TRISTATE, INPUT),
+
+	/* PWRON pinmux */
+	DEFAULT_PINMUX(CORE_PWR_REQ,  PWRON,       NORMAL,    NORMAL,   OUTPUT),
+
+	/* CPU pinmux */
+	DEFAULT_PINMUX(CPU_PWR_REQ,   CPU,         NORMAL,    NORMAL,   OUTPUT),
+
+	/* PMI pinmux */
+	DEFAULT_PINMUX(PWR_INT_N,     PMI,         NORMAL,    TRISTATE, INPUT),
+
+	/* RESET_OUT_N pinmux */
+	DEFAULT_PINMUX(RESET_OUT_N,   RESET_OUT_N, NORMAL,    NORMAL,   OUTPUT),
+
+	/* EXTPERIPH3 pinmux */
+	DEFAULT_PINMUX(CLK3_OUT,      EXTPERIPH3,  NORMAL,    NORMAL,   OUTPUT),
+
+	/* I2C1 pinmux */
+	I2C_PINMUX(GEN1_I2C_SCL, I2C1, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE),
+	I2C_PINMUX(GEN1_I2C_SDA, I2C1, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE),
+
+	/* UARTB, GPS */
+	DEFAULT_PINMUX(UART2_CTS_N,   UARTB,       NORMAL,    TRISTATE, INPUT),
+	DEFAULT_PINMUX(UART2_RTS_N,   UARTB,       NORMAL,    NORMAL,   OUTPUT),
+	DEFAULT_PINMUX(UART2_RXD,     UARTB,       NORMAL,    TRISTATE, INPUT),
+	DEFAULT_PINMUX(UART2_TXD,     UARTB,       NORMAL,    NORMAL,   OUTPUT),
+
+	/* UARTC (WIFI/BT) */
+	DEFAULT_PINMUX(UART3_CTS_N,   UARTC,       NORMAL,    TRISTATE, INPUT),
+	DEFAULT_PINMUX(UART3_RTS_N,   UARTC,       NORMAL,    NORMAL,   OUTPUT),
+	DEFAULT_PINMUX(UART3_RXD,     UARTC,       NORMAL,    TRISTATE, INPUT),
+	DEFAULT_PINMUX(UART3_TXD,     UARTC,       NORMAL,    NORMAL,   OUTPUT),
+
+	/* CEC pinmux */
+	CEC_PINMUX(HDMI_CEC, CEC, NORMAL, NORMAL, INPUT, DEFAULT, DISABLE),
+
+	/* I2C4 (HDMI_DDC) pinmux */
+	DDC_PINMUX(DDC_SCL, I2C4, NORMAL, NORMAL, INPUT, DEFAULT, HIGH),
+	DDC_PINMUX(DDC_SDA, I2C4, NORMAL, NORMAL, INPUT, DEFAULT, HIGH),
+
+	/* USB pinmux */
+	USB_PINMUX(USB_VBUS_EN0, USB, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE),
+	USB_PINMUX(USB_VBUS_EN1, USB, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE),
+
+	/* Unused, marked SNN_ on schematic, TRISTATE 'em */
+	DEFAULT_PINMUX(GPIO_PBB0,     RSVD3,       NORMAL,    TRISTATE, INPUT),
+	DEFAULT_PINMUX(GPIO_PBB3,     RSVD3,       NORMAL,    TRISTATE, INPUT),
+	DEFAULT_PINMUX(GPIO_PBB4,     RSVD3,       NORMAL,    TRISTATE, INPUT),
+	DEFAULT_PINMUX(GPIO_PBB5,     RSVD2,       NORMAL,    TRISTATE, INPUT),
+	DEFAULT_PINMUX(GPIO_PBB6,     RSVD1,       NORMAL,    TRISTATE, INPUT),
+	DEFAULT_PINMUX(GPIO_PBB7,     RSVD1,       NORMAL,    TRISTATE, INPUT),
+	DEFAULT_PINMUX(GPIO_PCC1,     RSVD1,       NORMAL,    TRISTATE, INPUT),
+	DEFAULT_PINMUX(GPIO_PCC2,     RSVD1,       NORMAL,    TRISTATE, INPUT),
+	DEFAULT_PINMUX(GPIO_PH3,      GMI,         NORMAL,    TRISTATE, INPUT),
+	DEFAULT_PINMUX(GPIO_PI7,      GMI,         NORMAL,    TRISTATE, INPUT),
+	DEFAULT_PINMUX(GPIO_PJ2,      RSVD1,       NORMAL,    TRISTATE, INPUT),
+	DEFAULT_PINMUX(GPIO_X5_AUD,   RSVD3,       NORMAL,    TRISTATE, INPUT),
+	DEFAULT_PINMUX(GPIO_X6_AUD,   GMI,         NORMAL,    TRISTATE, INPUT),
+	DEFAULT_PINMUX(GPIO_W2_AUD,   RSVD1,       NORMAL,    TRISTATE, INPUT),
+	DEFAULT_PINMUX(GPIO_PFF2,     RSVD1,       NORMAL,    TRISTATE, INPUT),
+	DEFAULT_PINMUX(USB_VBUS_EN2,  RSVD1,       NORMAL,    TRISTATE, INPUT),
+	DEFAULT_PINMUX(KB_COL5,       RSVD1,       NORMAL,    TRISTATE, INPUT),
+	DEFAULT_PINMUX(KB_ROW2,       RSVD1,       NORMAL,    TRISTATE, INPUT),
+	DEFAULT_PINMUX(KB_ROW3,       KBC,         NORMAL,    TRISTATE, INPUT),
+	DEFAULT_PINMUX(KB_ROW5,       RSVD2,       NORMAL,    TRISTATE, INPUT),
+	DEFAULT_PINMUX(KB_ROW6,       KBC,         NORMAL,    TRISTATE, INPUT),
+	DEFAULT_PINMUX(KB_ROW13,      RSVD1,       NORMAL,    TRISTATE, INPUT),
+	DEFAULT_PINMUX(KB_ROW14,      RSVD1,       NORMAL,    TRISTATE, INPUT),
+	DEFAULT_PINMUX(KB_ROW16,      RSVD1,       NORMAL,    TRISTATE, INPUT),
+	DEFAULT_PINMUX(OWR,           RSVD1,       NORMAL,    TRISTATE, INPUT),
+	DEFAULT_PINMUX(ULPI_DATA7,    ULPI,        NORMAL,    TRISTATE, INPUT),
+	DEFAULT_PINMUX(DAP3_DIN,      RSVD1,       NORMAL,    TRISTATE, INPUT),
+	DEFAULT_PINMUX(DAP3_FS,       RSVD1,       NORMAL,    TRISTATE, INPUT),
+	DEFAULT_PINMUX(DAP3_SCLK,     RSVD2,       NORMAL,    TRISTATE, INPUT),
+	DEFAULT_PINMUX(CLK2_OUT,      RSVD1,       NORMAL,    TRISTATE, INPUT),
+	DEFAULT_PINMUX(SDMMC1_WP_N,   RSVD1,       NORMAL,    TRISTATE, INPUT),
+	DEFAULT_PINMUX(CAM_MCLK,      RSVD1,       NORMAL,    TRISTATE, INPUT),
+	DEFAULT_PINMUX(CLK3_REQ,      RSVD1,       NORMAL,    TRISTATE, INPUT),
+	DEFAULT_PINMUX(SPDIF_OUT,     RSVD1,       NORMAL,    TRISTATE, INPUT),
+};
+
+static struct pingroup_config unused_pins_lowpower[] = {
+	DEFAULT_PINMUX(CLK1_REQ,      RSVD3,    DOWN, TRISTATE, OUTPUT),
+};
+
+/* Initially setting all used GPIO's to non-TRISTATE */
+static struct pingroup_config tegra124_pinmux_set_nontristate[] = {
+	DEFAULT_PINMUX(GPIO_X4_AUD,     RSVD1,  DOWN,    NORMAL,    OUTPUT),
+	DEFAULT_PINMUX(GPIO_X7_AUD,     RSVD1,  DOWN,    NORMAL,    OUTPUT),
+	DEFAULT_PINMUX(GPIO_W2_AUD,     RSVD1,  UP,      NORMAL,    INPUT),
+	DEFAULT_PINMUX(GPIO_X3_AUD,     RSVD3,  UP,      NORMAL,    INPUT),
+
+	/* EN_VDD_BL */
+	DEFAULT_PINMUX(DAP3_DOUT,       I2S2,   DOWN,    NORMAL,    OUTPUT),
+
+	/* MODEM */
+	DEFAULT_PINMUX(GPIO_PV0,        RSVD3,  NORMAL,  NORMAL,    INPUT),
+	DEFAULT_PINMUX(GPIO_PV1,        RSVD1,  NORMAL,  NORMAL,    INPUT),
+
+	/* BOOT_SEL0-3 */
+	DEFAULT_PINMUX(GPIO_PG0,         GMI,    NORMAL,  NORMAL,    INPUT),
+	DEFAULT_PINMUX(GPIO_PG1,         GMI,    NORMAL,  NORMAL,    INPUT),
+	DEFAULT_PINMUX(GPIO_PG2,         GMI,    NORMAL,  NORMAL,    INPUT),
+	DEFAULT_PINMUX(GPIO_PG3,         GMI,    NORMAL,  NORMAL,    INPUT),
+
+	DEFAULT_PINMUX(CLK2_REQ,        RSVD3,  NORMAL,  NORMAL,    OUTPUT),
+
+	DEFAULT_PINMUX(KB_COL3,         KBC,    UP,      NORMAL,    OUTPUT),
+	DEFAULT_PINMUX(KB_COL4,		SDMMC3, UP,	 NORMAL,    INPUT),
+	DEFAULT_PINMUX(KB_COL6,         KBC,    UP,      NORMAL,    OUTPUT),
+	DEFAULT_PINMUX(KB_COL7,         KBC,    UP,      NORMAL,    OUTPUT),
+	DEFAULT_PINMUX(KB_ROW4,         KBC,    DOWN,    NORMAL,    INPUT),
+	DEFAULT_PINMUX(KB_ROW8,         KBC,    UP,      NORMAL,    INPUT),
+
+	DEFAULT_PINMUX(GPIO_PU4,        RSVD3,  NORMAL,  NORMAL,    INPUT),
+	DEFAULT_PINMUX(GPIO_PU5,        RSVD3,  NORMAL,  NORMAL,    OUTPUT),
+	DEFAULT_PINMUX(GPIO_PU6,        RSVD3,  NORMAL,  NORMAL,    INPUT),
+
+	DEFAULT_PINMUX(HDMI_INT,        RSVD1,  DOWN,    NORMAL,   INPUT),
+	DEFAULT_PINMUX(SPDIF_IN,	USB,	NORMAL,   NORMAL,   INPUT),
+	DEFAULT_PINMUX(SDMMC3_CD_N,     SDMMC3, UP,       NORMAL,   INPUT),
+
+	/* TS_SHDN_L */
+	DEFAULT_PINMUX(GPIO_PK1,        GMI,    NORMAL,   NORMAL,   OUTPUT),
+};
+
+static struct padctrl_config venice2_padctrl[] = {
+	/* (_padgrp, _slwf, _slwr, _drvup, _drvdn, _lpmd, _schmt, _hsm) */
+	DEFAULT_PADCFG(SDIO3, SDIOCFG_DRVUP_SLWF, SDIOCFG_DRVDN_SLWR,
+		       SDIOCFG_DRVUP, SDIOCFG_DRVDN, NONE, NONE, NONE),
+};
+#endif /* PINMUX_CONFIG_VENICE2_H */
diff --git a/board/nvidia/venice2/venice2.c b/board/nvidia/venice2/venice2.c
new file mode 100644
index 0000000000..1ed2fd788e
--- /dev/null
+++ b/board/nvidia/venice2/venice2.c
@@ -0,0 +1,33 @@
+/*
+ * (C) Copyright 2013-2014
+ * NVIDIA Corporation <www.nvidia.com>
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm-generic/gpio.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/gp_padctrl.h>
+#include <asm/arch/pinmux.h>
+#include "pinmux-config-venice2.h"
+#include <i2c.h>
+
+/*
+ * Routine: pinmux_init
+ * Description: Do individual peripheral pinmux configs
+ */
+void pinmux_init(void)
+{
+	pinmux_config_table(tegra124_pinmux_set_nontristate,
+			    ARRAY_SIZE(tegra124_pinmux_set_nontristate));
+
+	pinmux_config_table(tegra124_pinmux_common,
+			    ARRAY_SIZE(tegra124_pinmux_common));
+
+	pinmux_config_table(unused_pins_lowpower,
+			    ARRAY_SIZE(unused_pins_lowpower));
+
+	/* Initialize any non-default pad configs (APB_MISC_GP regs) */
+	padgrp_config_table(venice2_padctrl, ARRAY_SIZE(venice2_padctrl));
+}
diff --git a/board/nvidia/ventana/Makefile b/board/nvidia/ventana/Makefile
index 9c2349dc6a..f67044f2cf 100644
--- a/board/nvidia/ventana/Makefile
+++ b/board/nvidia/ventana/Makefile
@@ -5,25 +5,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-$(shell mkdir -p $(obj)../seaboard)
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	= ../seaboard/seaboard.o
-
-SRCS	:= $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	= ../seaboard/seaboard.o
diff --git a/board/nvidia/whistler/Makefile b/board/nvidia/whistler/Makefile
index 4a92d7a86d..b54c5fd338 100644
--- a/board/nvidia/whistler/Makefile
+++ b/board/nvidia/whistler/Makefile
@@ -5,23 +5,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	:= $(BOARD).o
-
-SRCS	:= $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	:= whistler.o
diff --git a/board/nx823/Makefile b/board/nx823/Makefile
index e9558412e1..a22be5c3e6 100644
--- a/board/nx823/Makefile
+++ b/board/nx823/Makefile
@@ -5,24 +5,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	= $(BOARD).o flash.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	= nx823.o flash.o
diff --git a/board/olimex/mx23_olinuxino/Makefile b/board/olimex/mx23_olinuxino/Makefile
index c735e359c3..133114c08d 100644
--- a/board/olimex/mx23_olinuxino/Makefile
+++ b/board/olimex/mx23_olinuxino/Makefile
@@ -5,27 +5,8 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
 ifndef	CONFIG_SPL_BUILD
-COBJS	:= mx23_olinuxino.o
+obj-y	:= mx23_olinuxino.o
 else
-COBJS	:= spl_boot.o
+obj-y	:= spl_boot.o
 endif
-
-SRCS	:= $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
diff --git a/board/omicron/calimain/Makefile b/board/omicron/calimain/Makefile
index 16e390d80b..59c118d074 100644
--- a/board/omicron/calimain/Makefile
+++ b/board/omicron/calimain/Makefile
@@ -7,23 +7,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS   := $(BOARD).o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
-	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
-
-#########################################################################
-# This is for $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y   := calimain.o
diff --git a/board/openrisc/openrisc-generic/Makefile b/board/openrisc/openrisc-generic/Makefile
index bd15345b29..342bc80450 100644
--- a/board/openrisc/openrisc-generic/Makefile
+++ b/board/openrisc/openrisc-generic/Makefile
@@ -5,23 +5,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS-y	:= $(BOARD).o
-
-SRCS	:= $(COBJS-y:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS-y))
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	:= openrisc-generic.o
diff --git a/board/overo/Makefile b/board/overo/Makefile
index 694f317800..910948455b 100644
--- a/board/overo/Makefile
+++ b/board/overo/Makefile
@@ -5,22 +5,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	:= overo.o
-
-SRCS	:= $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-#########################################################################
-sinclude $(obj).depend
+obj-y	:= overo.o
diff --git a/board/overo/overo.c b/board/overo/overo.c
index aace42a8be..1192d02e91 100644
--- a/board/overo/overo.c
+++ b/board/overo/overo.c
@@ -21,7 +21,6 @@
 #include <asm/arch/mux.h>
 #include <asm/arch/mem.h>
 #include <asm/arch/sys_proto.h>
-#include <asm/omap_gpmc.h>
 #include <asm/gpio.h>
 #include <asm/mach-types.h>
 #include "overo.h"
@@ -92,7 +91,7 @@ int get_board_revision(void)
 {
 	int revision;
 
-#ifdef CONFIG_DRIVER_OMAP34XX_I2C
+#ifdef CONFIG_SYS_I2C_OMAP34XX
 	unsigned char data;
 
 	/* board revisions <= R2410 connect 4030 irq_1 to gpio112             */
diff --git a/board/palmld/Makefile b/board/palmld/Makefile
index 44a8ad8e01..ea93ca88e2 100644
--- a/board/palmld/Makefile
+++ b/board/palmld/Makefile
@@ -6,23 +6,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	:= palmld.o
-
-SRCS	:= $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	:= palmld.o
diff --git a/board/palmtc/Makefile b/board/palmtc/Makefile
index a87eb81fb8..b4a682d24d 100644
--- a/board/palmtc/Makefile
+++ b/board/palmtc/Makefile
@@ -6,24 +6,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	:= palmtc.o
-
-SRCS	:= $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	:= palmtc.o
diff --git a/board/palmtreo680/Makefile b/board/palmtreo680/Makefile
index 34ffb99d0c..4f79e4bf11 100644
--- a/board/palmtreo680/Makefile
+++ b/board/palmtreo680/Makefile
@@ -6,29 +6,4 @@
 # This file is released under the terms of GPL v2 and any later version.
 # See the file COPYING in the root directory of the source tree for details.
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	:= palmtreo680.o
-
-SRCS	:= $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-clean:
-	rm -f $(OBJS)
-
-distclean:	clean
-	rm -f $(LIB) core *.bak $(obj).depend
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	:= palmtreo680.o
diff --git a/board/pandora/Makefile b/board/pandora/Makefile
index 6e75133bf3..918b65691d 100644
--- a/board/pandora/Makefile
+++ b/board/pandora/Makefile
@@ -5,23 +5,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	:= pandora.o
-
-SRCS	:= $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	:= pandora.o
diff --git a/board/pb1x00/Makefile b/board/pb1x00/Makefile
index ed7370f9a6..647eb85d74 100644
--- a/board/pb1x00/Makefile
+++ b/board/pb1x00/Makefile
@@ -5,25 +5,5 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	= $(BOARD).o flash.o
-SOBJS	= lowlevel_init.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
-	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	= pb1x00.o flash.o
+obj-y	+= lowlevel_init.o
diff --git a/board/pcs440ep/Makefile b/board/pcs440ep/Makefile
index 851859d045..4fc24d6c5d 100644
--- a/board/pcs440ep/Makefile
+++ b/board/pcs440ep/Makefile
@@ -5,25 +5,5 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	= $(BOARD).o flash.o
-SOBJS	= init.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(OBJS) $(SOBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	= pcs440ep.o flash.o
+extra-y	+= init.o
diff --git a/board/pcs440ep/config.mk b/board/pcs440ep/config.mk
index 1e761284e4..b90d5d0ec1 100644
--- a/board/pcs440ep/config.mk
+++ b/board/pcs440ep/config.mk
@@ -10,7 +10,7 @@
 #
 
 # Check the U-Boot Image with a SHA1 checksum
-ALL-y += $(obj)u-boot.sha1
+ALL-y += u-boot.sha1
 
 PLATFORM_CPPFLAGS += -DCONFIG_440=1
 
diff --git a/board/pdm360ng/Makefile b/board/pdm360ng/Makefile
index 76f5be45f5..99201a41f6 100644
--- a/board/pdm360ng/Makefile
+++ b/board/pdm360ng/Makefile
@@ -5,25 +5,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS-y	:= $(BOARD).o
-
-COBJS	:= $(COBJS-y)
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	:= pdm360ng.o
diff --git a/board/phytec/pcm030/Makefile b/board/phytec/pcm030/Makefile
index 4a7d872afa..2bb49dc7aa 100644
--- a/board/phytec/pcm030/Makefile
+++ b/board/phytec/pcm030/Makefile
@@ -5,24 +5,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	:= $(BOARD).o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	:= pcm030.o
diff --git a/board/phytec/pcm051/Makefile b/board/phytec/pcm051/Makefile
index cb2b999025..ecb1d61669 100644
--- a/board/phytec/pcm051/Makefile
+++ b/board/phytec/pcm051/Makefile
@@ -6,33 +6,8 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
 ifdef CONFIG_SPL_BUILD
-COBJS	:= mux.o
+obj-y	+= mux.o
 endif
 
-COBJS	+= board.o
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
-	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
-
-clean:
-	rm -f $(SOBJS) $(OBJS)
-
-distclean:	clean
-	rm -f $(LIB) core *.bak $(obj).depend
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	+= board.o
diff --git a/board/phytec/pcm051/board.c b/board/phytec/pcm051/board.c
index dafb1eb8e6..1071662ea9 100644
--- a/board/phytec/pcm051/board.c
+++ b/board/phytec/pcm051/board.c
@@ -49,25 +49,30 @@ const struct dpll_params *get_dpll_ddr_params(void)
 	return &dpll_ddr;
 }
 
+#ifdef CONFIG_REV1
+const struct ctrl_ioregs ioregs = {
+	.cm0ioctl		= MT41J256M8HX15E_IOCTRL_VALUE,
+	.cm1ioctl		= MT41J256M8HX15E_IOCTRL_VALUE,
+	.cm2ioctl		= MT41J256M8HX15E_IOCTRL_VALUE,
+	.dt0ioctl		= MT41J256M8HX15E_IOCTRL_VALUE,
+	.dt1ioctl		= MT41J256M8HX15E_IOCTRL_VALUE,
+};
+
 static const struct ddr_data ddr3_data = {
 	.datardsratio0 = MT41J256M8HX15E_RD_DQS,
 	.datawdsratio0 = MT41J256M8HX15E_WR_DQS,
 	.datafwsratio0 = MT41J256M8HX15E_PHY_FIFO_WE,
 	.datawrsratio0 = MT41J256M8HX15E_PHY_WR_DATA,
-	.datadldiff0 = PHY_DLL_LOCK_DIFF,
 };
 
 static const struct cmd_control ddr3_cmd_ctrl_data = {
 	.cmd0csratio = MT41J256M8HX15E_RATIO,
-	.cmd0dldiff = MT41J256M8HX15E_DLL_LOCK_DIFF,
 	.cmd0iclkout = MT41J256M8HX15E_INVERT_CLKOUT,
 
 	.cmd1csratio = MT41J256M8HX15E_RATIO,
-	.cmd1dldiff = MT41J256M8HX15E_DLL_LOCK_DIFF,
 	.cmd1iclkout = MT41J256M8HX15E_INVERT_CLKOUT,
 
 	.cmd2csratio = MT41J256M8HX15E_RATIO,
-	.cmd2dldiff = MT41J256M8HX15E_DLL_LOCK_DIFF,
 	.cmd2iclkout = MT41J256M8HX15E_INVERT_CLKOUT,
 };
 
@@ -82,6 +87,56 @@ static struct emif_regs ddr3_emif_reg_data = {
 				PHY_EN_DYN_PWRDN,
 };
 
+void sdram_init(void)
+{
+	config_ddr(DDR_CLK_MHZ, &ioregs, &ddr3_data,
+		   &ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0);
+}
+#else
+const struct ctrl_ioregs ioregs = {
+	.cm0ioctl		= MT41K256M16HA125E_IOCTRL_VALUE,
+	.cm1ioctl		= MT41K256M16HA125E_IOCTRL_VALUE,
+	.cm2ioctl		= MT41K256M16HA125E_IOCTRL_VALUE,
+	.dt0ioctl		= MT41K256M16HA125E_IOCTRL_VALUE,
+	.dt1ioctl		= MT41K256M16HA125E_IOCTRL_VALUE,
+};
+
+static const struct ddr_data ddr3_data = {
+	.datardsratio0 = MT41K256M16HA125E_RD_DQS,
+	.datawdsratio0 = MT41K256M16HA125E_WR_DQS,
+	.datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE,
+	.datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA,
+};
+
+static const struct cmd_control ddr3_cmd_ctrl_data = {
+	.cmd0csratio = MT41K256M16HA125E_RATIO,
+	.cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
+
+	.cmd1csratio = MT41K256M16HA125E_RATIO,
+	.cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
+
+	.cmd2csratio = MT41K256M16HA125E_RATIO,
+	.cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
+};
+
+static struct emif_regs ddr3_emif_reg_data = {
+	.sdram_config = MT41K256M16HA125E_EMIF_SDCFG,
+	.ref_ctrl = MT41K256M16HA125E_EMIF_SDREF,
+	.sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1,
+	.sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2,
+	.sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3,
+	.zq_config = MT41K256M16HA125E_ZQ_CFG,
+	.emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY |
+				PHY_EN_DYN_PWRDN,
+};
+
+void sdram_init(void)
+{
+	config_ddr(DDR_CLK_MHZ, &ioregs, &ddr3_data,
+		   &ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0);
+}
+#endif
+
 void set_uart_mux_conf(void)
 {
 	enable_uart0_pin_mux();
@@ -91,16 +146,10 @@ void set_mux_conf_regs(void)
 {
 	/* Initalize the board header */
 	enable_i2c0_pin_mux();
-	i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
+	i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE);
 
 	enable_board_pin_mux();
 }
-
-void sdram_init(void)
-{
-	config_ddr(DDR_CLK_MHZ, MT41J256M8HX15E_IOCTRL_VALUE, &ddr3_data,
-			&ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0);
-}
 #endif
 
 /*
@@ -108,7 +157,7 @@ void sdram_init(void)
  */
 int board_init(void)
 {
-	i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
+	i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE);
 
 	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
 
@@ -127,13 +176,13 @@ static struct cpsw_slave_data cpsw_slaves[] = {
 	{
 		.slave_reg_ofs	= 0x208,
 		.sliver_reg_ofs	= 0xd80,
-		.phy_id		= 0,
+		.phy_addr	= 0,
 		.phy_if		= PHY_INTERFACE_MODE_RGMII,
 	},
 	{
 		.slave_reg_ofs	= 0x308,
 		.sliver_reg_ofs	= 0xdc0,
-		.phy_id		= 1,
+		.phy_addr	= 1,
 		.phy_if		= PHY_INTERFACE_MODE_RGMII,
 	},
 };
diff --git a/board/pm520/Makefile b/board/pm520/Makefile
index 4ff6b2d995..8b5a7eba71 100644
--- a/board/pm520/Makefile
+++ b/board/pm520/Makefile
@@ -1,4 +1,3 @@
-
 #
 # (C) Copyright 2003-2006
 # Wolfgang Denk, DENX Software Engineering, wd@denx.de.
@@ -6,24 +5,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	:= $(BOARD).o flash.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	:= pm520.o flash.o
diff --git a/board/pm826/Makefile b/board/pm826/Makefile
index e9558412e1..c515f8105d 100644
--- a/board/pm826/Makefile
+++ b/board/pm826/Makefile
@@ -5,24 +5,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	= $(BOARD).o flash.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	= pm826.o flash.o
diff --git a/board/pm828/Makefile b/board/pm828/Makefile
index e9558412e1..0afffb7bc6 100644
--- a/board/pm828/Makefile
+++ b/board/pm828/Makefile
@@ -5,24 +5,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	= $(BOARD).o flash.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	= pm828.o flash.o
diff --git a/board/pn62/Makefile b/board/pn62/Makefile
deleted file mode 100644
index 5fa6fc8ca6..0000000000
--- a/board/pn62/Makefile
+++ /dev/null
@@ -1,28 +0,0 @@
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	= $(BOARD).o cmd_pn62.o misc.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
diff --git a/board/pn62/cmd_pn62.c b/board/pn62/cmd_pn62.c
deleted file mode 100644
index a0326b40d6..0000000000
--- a/board/pn62/cmd_pn62.c
+++ /dev/null
@@ -1,146 +0,0 @@
-/*
- * (C) Copyright 2002
- * Wolfgang Grandegger, DENX Software Engineering, wg@denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <malloc.h>
-#include <net.h>
-#include <asm/io.h>
-#include <pci.h>
-#include <command.h>
-#include "pn62.h"
-
-#if defined(CONFIG_CMD_BSP)
-
-/*
- * Command led: controls the various LEDs 0..11 on the PN62 card.
- */
-int do_led(cmd_tbl_t * cmdtp, int flag, int argc, char *const argv[])
-{
-	unsigned int number, function;
-
-	if (argc != 3)
-		return cmd_usage(cmdtp);
-
-	number = simple_strtoul(argv[1], NULL, 10);
-	if (number > PN62_LED_MAX)
-		return 1;
-
-	function = simple_strtoul(argv[2], NULL, 16);
-	set_led(number, function);
-	return 0;
-}
-U_BOOT_CMD(
-	led    ,	3,	1,	do_led,
-	"set LED 0..11 on the PN62 board",
-	"i fun"
-	"    - set 'i'th LED to function 'fun'"
-);
-
-/*
- * Command loadpci: loads a image over PCI.
- */
-#define CMD_MOVE_WINDOW 0x1
-#define CMD_BOOT_IMAGE  0x2
-
-int do_loadpci (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
-    char *s;
-    ulong addr = 0, count = 0;
-    u32 off;
-    int cmd, rcode = 0;
-
-    /* pre-set load_addr */
-    if ((s = getenv("loadaddr")) != NULL) {
-	addr = simple_strtoul(s, NULL, 16);
-    }
-
-    switch (argc) {
-    case 1:
-	break;
-    case 2:
-	addr = simple_strtoul(argv[1], NULL, 16);
-	break;
-    default:
-	return cmd_usage(cmdtp);
-    }
-
-    printf ("## Ready for image download ...\n");
-
-    show_startup_phase(12);
-
-    while (1) {
-	/* Alive indicator */
-	i2155x_write_scrapad(BOOT_PROTO, BOOT_PROTO_READY);
-
-	/* Toggle status LEDs */
-	cmd = (count / 200) % 4; /* downscale */
-	set_led(4, cmd == 0 ? LED_1 : LED_0);
-	set_led(5, cmd == 1 ? LED_1 : LED_0);
-	set_led(6, cmd == 2 ? LED_1 : LED_0);
-	set_led(7, cmd == 3 ? LED_1 : LED_0);
-	udelay(1000);
-	count++;
-
-	cmd = i2155x_read_scrapad(BOOT_CMD);
-
-	if (cmd == BOOT_CMD_MOVE) {
-	    off = i2155x_read_scrapad(BOOT_DATA);
-	    off += addr;
-	    i2155x_set_bar_base(3, off);
-	    printf ("## BAR3 Addr moved = 0x%08x\n", off);
-	    i2155x_write_scrapad(BOOT_CMD, ~cmd);
-	    show_startup_phase(13);
-	}
-	else if (cmd == BOOT_CMD_BOOT) {
-	    set_led(4, LED_1);
-	    set_led(5, LED_1);
-	    set_led(6, LED_1);
-	    set_led(7, LED_1);
-
-	    i2155x_write_scrapad(BOOT_CMD, ~cmd);
-	    show_startup_phase(14);
-	    break;
-	}
-
-	/* Abort if ctrl-c was pressed */
-	if (ctrlc()) {
-	    printf("\nAbort\n");
-	    return 0;
-	}
-
-    }
-
-    /* Repoint to the default shared memory */
-    i2155x_set_bar_base(3, PN62_SMEM_DEFAULT);
-
-    load_addr = addr;
-    printf ("## Start Addr      = 0x%08lx\n", addr);
-
-    show_startup_phase(15);
-
-    /* Loading ok, check if we should attempt an auto-start */
-    if (((s = getenv("autostart")) != NULL) && (strcmp(s,"yes") == 0)) {
-	char *local_args[2];
-	local_args[0] = argv[0];
-	local_args[1] = NULL;
-
-	printf ("Automatic boot of image at addr 0x%08lX ...\n",
-		load_addr);
-	rcode = do_bootm (cmdtp, 0, 1, local_args);
-    }
-
-    return rcode;
-}
-
-U_BOOT_CMD(
-	loadpci,	2,	1,	do_loadpci,
-	"load binary file over PCI",
-	"[addr]\n"
-	"    - load binary file over PCI to address 'addr'"
-);
-
-#endif
diff --git a/board/pn62/misc.c b/board/pn62/misc.c
deleted file mode 100644
index 98e0dfa518..0000000000
--- a/board/pn62/misc.c
+++ /dev/null
@@ -1,219 +0,0 @@
-/*
- * (C) Copyright 2002 Wolfgang Grandegger <wg@denx.de>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <mpc824x.h>
-#include <asm/io.h>
-#include <pci.h>
-
-#include "pn62.h"
-
-typedef struct {
-    pci_dev_t    devno;
-    volatile u32 *csr;
-
-} i2155x_t;
-
-static i2155x_t i2155x = { 0, NULL };
-
-static struct pci_device_id i2155x_ids[] = {
-    { 0x1011, 0x0046 },		/* i21554 */
-    { 0x8086, 0xb555 }		/* i21555 */
-};
-
-int i2155x_init(void)
-{
-    pci_dev_t devno;
-    u32 val;
-    int i;
-
-    /*
-     * Find the Intel bridge.
-     */
-    if ((devno = pci_find_devices(i2155x_ids, 0)) < 0) {
-	printf("Error: Intel bridge 2155x not found!\n");
-	return -1;
-    }
-    i2155x.devno = devno;
-
-    /*
-     * Get auto-configured base address for CSR access.
-     */
-    pci_read_config_dword(devno, PCI_BASE_ADDRESS_1, &val);
-    if (val & PCI_BASE_ADDRESS_SPACE_IO) {
-	val &= PCI_BASE_ADDRESS_IO_MASK;
-	i2155x.csr = (volatile u32 *)(_IO_BASE + val);
-    } else {
-	val &= PCI_BASE_ADDRESS_MEM_MASK;
-	i2155x.csr =  (volatile u32 *)val;
-    }
-
-    /*
-     * Translate downstream memory 2 (bar3) to base of shared memory.
-     */
-    i2155x_set_bar_base(3, PN62_SMEM_DEFAULT);
-
-    /*
-     * Enable memory space, I/O space and bus master bits
-     * in both Primary and Secondary command registers.
-     */
-    val = PCI_COMMAND_MEMORY|PCI_COMMAND_MASTER|PCI_COMMAND_IO;
-    pci_write_config_word(devno, 0x44, val);
-    pci_write_config_word(devno, 0x04, val);
-
-    /*
-     * Clear scratchpad registers.
-     */
-    for (i = 0; i < (I2155X_SCRAPAD_MAX - 1); i++) {
-	i2155x_write_scrapad(i, 0x0);
-    }
-
-    /*
-     * Set interrupt line for Linux.
-     */
-    pci_write_config_byte(devno, PCI_INTERRUPT_LINE, 3);
-
-    return 0;
-}
-
-/*
- * Access the Scratchpad registers 0..7 of the Intel bridge.
- */
-void i2155x_write_scrapad(int idx, u32 val)
-{
-    if (idx >= 0 && idx < I2155X_SCRAPAD_MAX)
-	out_le32(i2155x.csr + (I2155X_SCRAPAD_ADDR/4) + idx, val);
-    else
-	printf("i2155x_write_scrapad: invalid index\n");
-}
-
-u32 i2155x_read_scrapad(int idx)
-{
-    if (idx >= 0 && idx < I2155X_SCRAPAD_MAX)
-	return in_le32(i2155x.csr + (I2155X_SCRAPAD_ADDR/4) + idx);
-    else
-	printf("i2155x_read_scrapad: invalid index\n");
-    return -1;
-}
-
-void i2155x_set_bar_base(int bar, u32 base)
-{
-    if (bar >= 2 && bar <= 4) {
-	pci_write_config_dword(i2155x.devno,
-			       I2155X_BAR2_BASE + (bar - 2) * 4,
-			       base);
-    }
-}
-
-/*
- * Read Vital Product Data (VPD) from the Serial EPROM attached
- * to the Intel bridge.
- */
-int i2155x_read_vpd(int offset, int size, unsigned char *data)
-{
-    int i, n;
-    u16 val16;
-
-    for (i = 0; i < size; i++) {
-	pci_write_config_word(i2155x.devno, I2155X_VPD_ADDR,
-			      offset + i - I2155X_VPD_START);
-	for (n = 10000; n > 0; n--) {
-	    pci_read_config_word(i2155x.devno, I2155X_VPD_ADDR, &val16);
-	    if ((val16 & 0x8000) != 0) /* wait for completion */
-		break;
-	    udelay(100);
-	}
-	if (n == 0) {
-	    printf("i2155x_read_vpd: TIMEOUT\n");
-	    return -1;
-	}
-
-	pci_read_config_byte(i2155x.devno, I2155X_VPD_DATA, &data[i]);
-    }
-
-    return i;
-}
-
-static struct pci_device_id am79c95x_ids [] = {
-	{ PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_LANCE },
-	{ }
-};
-
-
-/*
- * Initialize the AMD ethernet controllers.
- */
-int am79c95x_init(void)
-{
-    pci_dev_t devno;
-    int i;
-
-    /*
-     * Set interrupt line for Linux.
-     */
-    for (i = 0; i < 2; i++) {
-	if ((devno = pci_find_devices(am79c95x_ids, i)) < 0)
-	    break;
-	pci_write_config_byte(devno, PCI_INTERRUPT_LINE, 2+i);
-    }
-    if (i < 2)
-	printf("Error: Only %d AMD Ethernet Controller found!\n", i);
-
-    return 0;
-}
-
-
-void set_led(unsigned int number, unsigned int function)
-{
-    volatile u8 *addr;
-
-    if ((number >= 0) && (number < PN62_LED_MAX) &&
-	(function >= 0) && (function <= LED_LAST_FUNCTION)) {
-	addr = (volatile u8 *)(PN62_LED_BASE + number * 8);
-	out_8(addr, function&0xff);
-    }
-}
-
-/*
- * Show fatal error indicated by Kinght Rider(tm) effect
- * in LEDS 0-7. LEDS 8-11 contain 4 bit error code.
- * Note: this function will not terminate.
- */
-void fatal_error(unsigned int error_code)
-{
-    int i, d;
-
-    for (i = 0; i < 12; i++) {
-	set_led(i, LED_0);
-    }
-
-    /*
-     * Write error code.
-     */
-    set_led(8,  (error_code & 0x01) ? LED_1 : LED_0);
-    set_led(9,  (error_code & 0x02) ? LED_1 : LED_0);
-    set_led(10, (error_code & 0x04) ? LED_1 : LED_0);
-    set_led(11, (error_code & 0x08) ? LED_1 : LED_0);
-
-    /*
-     * Yay - Knight Rider effect!
-     */
-    while(1) {
-	unsigned int delay = 2000;
-
-	for (i = 0; i < 8; i++) {
-	    set_led(i, LED_1);
-	    for (d = 0; d < delay; d++);
-	    set_led(i, LED_0);
-	}
-
-	for (i = 7; i > 0; i--) {
-	    set_led(i, LED_1);
-	    for (d = 0; d < delay; d++);
-	    set_led(i, LED_0);
-	}
-    }
-}
diff --git a/board/pn62/pn62.c b/board/pn62/pn62.c
deleted file mode 100644
index 81829dd75f..0000000000
--- a/board/pn62/pn62.c
+++ /dev/null
@@ -1,171 +0,0 @@
-/*
- * (C) Copyright 2002 Wolfgang Grandegger <wg@denx.de>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <mpc824x.h>
-#include <net.h>
-#include <pci.h>
-#include <netdev.h>
-
-#include "pn62.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-static int get_serial_number (char *string, int size);
-static void get_mac_address(int id, u8 *mac);
-
-#ifdef CONFIG_SHOW_BOOT_PROGRESS
-void show_boot_progress (int phase)
-{
-	/*
-	 * Show phases of the bootm command on the front panel
-	 * LEDs and the scratchpad register #3 as well. We use
-	 * blinking LEDs for logical "1".
-	 */
-	if (phase > 0) {
-		set_led (8, (phase & 0x1) ? LED_SLOW_CLOCK : LED_0);
-		set_led (9, (phase & 0x2) ? LED_SLOW_CLOCK : LED_0);
-		set_led (10, (phase & 0x4) ? LED_SLOW_CLOCK : LED_0);
-		set_led (11, (phase & 0x8) ? LED_SLOW_CLOCK : LED_0);
-	}
-	i2155x_write_scrapad (BOOT_STATUS, phase);
-	if (phase < 0)
-		i2155x_write_scrapad (BOOT_DONE, BOOT_DONE_ERROR);
-}
-#endif
-
-void show_startup_phase (int phase)
-{
-	/*
-	 * Show the phase of U-Boot startup on the front panel
-	 * LEDs and the scratchpad register #3 as well.
-	 */
-	if (phase > 0) {
-		set_led (8, (phase & 0x1) ? LED_1 : LED_0);
-		set_led (9, (phase & 0x2) ? LED_1 : LED_0);
-		set_led (10, (phase & 0x4) ? LED_1 : LED_0);
-		set_led (11, (phase & 0x8) ? LED_1 : LED_0);
-	}
-	i2155x_write_scrapad (BOOT_STATUS, phase);
-	if (phase < 0)
-		i2155x_write_scrapad (BOOT_DONE, BOOT_DONE_ERROR);
-}
-
-int checkboard (void)
-{
-	show_startup_phase (1);
-	puts ("Board: PN62\n");
-	return 0;
-}
-
-phys_size_t initdram (int board_type)
-{
-	long size;
-	long new_bank0_end;
-	long mear1;
-	long emear1;
-
-	show_startup_phase (2);
-
-	size = get_ram_size(CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_MAX_RAM_SIZE);
-
-	new_bank0_end = size - 1;
-	mear1 = mpc824x_mpc107_getreg (MEAR1);
-	emear1 = mpc824x_mpc107_getreg (EMEAR1);
-	mear1 = (mear1 & 0xFFFFFF00) |
-		((new_bank0_end & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT);
-	emear1 = (emear1 & 0xFFFFFF00) |
-		((new_bank0_end & MICR_ADDR_MASK) >> MICR_EADDR_SHIFT);
-	mpc824x_mpc107_setreg (MEAR1, mear1);
-	mpc824x_mpc107_setreg (EMEAR1, emear1);
-
-	return (size);
-}
-
-/*
- * Initialize PCI Devices. We rely on auto-configuration.
- */
-#ifndef CONFIG_PCI_PNP
-#error "CONFIG_PCI_PNP is not defined, please correct!"
-#endif
-
-struct pci_controller hose = {
-};
-
-void pci_init_board (void)
-{
-	show_startup_phase (4);
-	pci_mpc824x_init (&hose);
-
-	show_startup_phase (5);
-	i2155x_init ();
-	show_startup_phase (6);
-	am79c95x_init ();
-	show_startup_phase (7);
-}
-
-int misc_init_r (void)
-{
-	char str[20];
-	u8 mac[6];
-
-	show_startup_phase (8);
-	/*
-	 * Get serial number and ethernet addresses if not already defined
-	 * and update the board info structure and the environment.
-	 */
-	if (getenv ("serial#") == NULL &&
-		get_serial_number (str, strlen (str)) > 0) {
-		setenv ("serial#", str);
-	}
-	show_startup_phase (9);
-
-	if (!eth_getenv_enetaddr("ethaddr", mac)) {
-		get_mac_address(0, mac);
-		eth_setenv_enetaddr("ethaddr", mac);
-	}
-	show_startup_phase (10);
-
-#ifdef CONFIG_HAS_ETH1
-	if (!eth_getenv_enetaddr("eth1addr", mac)) {
-		get_mac_address(1, mac);
-		eth_setenv_enetaddr("eth1addr", mac);
-	}
-#endif /* CONFIG_HAS_ETH1 */
-	show_startup_phase (11);
-
-	/* Tell everybody that U-Boot is up and runnig */
-	i2155x_write_scrapad (0, 0x12345678);
-	return (0);
-}
-
-static int get_serial_number (char *string, int size)
-{
-	int i;
-	char c;
-
-	if (size < I2155X_VPD_SN_SIZE)
-		size = I2155X_VPD_SN_SIZE;
-	for (i = 0; i < (size - 1); i++) {
-		i2155x_read_vpd (I2155X_VPD_SN_START + i, 1, (uchar *)&c);
-		if (c == '\0')
-			break;
-		string[i] = c;
-	}
-	string[i] = '\0';			/* make sure it's terminated */
-
-	return i;
-}
-
-static void get_mac_address(int id, u8 *mac)
-{
-	i2155x_read_vpd (I2155X_VPD_MAC0_START + 6 * id, 6, mac);
-}
-
-int board_eth_init(bd_t *bis)
-{
-	return pci_eth_init(bis);
-}
diff --git a/board/pn62/pn62.h b/board/pn62/pn62.h
deleted file mode 100644
index 10290c3142..0000000000
--- a/board/pn62/pn62.h
+++ /dev/null
@@ -1,145 +0,0 @@
-/*
- * (C) Copyright 2002 Wolfgang Grandegger <wg@denx.de>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef _PN62_H_
-#define _PN62_H_
-
-/*
- * Definitions for the Intel Bridge 21554 or 21555.
- */
-#define I2155X_VPD_ADDR		0xe6
-#define I2155X_VPD_DATA		0xe8
-
-#define I2155X_VPD_START	0x80
-#define I2155X_VPD_SN_START	0x80
-#define I2155X_VPD_SN_SIZE	0x10
-#define I2155X_VPD_MAC0_START	0x90
-#define I2155X_VPD_MAC1_START	0x96
-
-#define I2155X_SCRAPAD_ADDR	0xa8
-#define I2155X_SCRAPAD_MAX	8
-
-#define I2155X_BAR2_BASE	0x98
-#define I2155X_BAR3_BASE	0x9c
-#define I2155X_BAR4_BASE	0xa0
-
-#define I2155X_BAR2_SETUP	0xb0
-#define I2155X_BAR3_SETUP	0xb4
-#define I2155X_BAR4_SETUP	0xb8
-
-/*
- * Interrupt request numbers
- */
-#define PN62_IRQ_HOST		0x0
-#define PN62_IRQ_PLX9054	0x1
-#define PN62_IRQ_ETH0		0x2
-#define PN62_IRQ_ETH1		0x3
-#define PN62_IRQ_COM1		0x4
-#define PN62_IRQ_COM2		0x4
-
-/*
- * Miscellaneous definitons.
- */
-#define PN62_SMEM_DEFAULT	0x1f00000
-
-/*
- * Definitions for boot protocol using Scratchpad registers.
- */
-#define BOOT_DONE		0
-#define BOOT_DONE_CLEAR		0x00dead00
-#define BOOT_DONE_ERROR		0xbad0dead
-#define BOOT_DONE_U_BOOT	0x12345678
-#define BOOT_DONE_LINUX		0x87654321
-#define BOOT_CMD		1
-#define BOOT_CMD_MOVE		0x1
-#define BOOT_CMD_BOOT		0x2
-#define BOOT_DATA		2
-#define BOOT_PROTO		3
-#define BOOT_PROTO_READY	0x23456789
-#define BOOT_PROTO_CLEAR	0x00000000
-#define BOOT_STATUS		4
-
-/*
- * LED Definitions:
- */
-#define PN62_LED_BASE		0xff800300
-#define PN62_LED_MAX		12
-
-/*
- * LED0 - 7 mounted on top of board, D1 - D8
- * LED8 - 11 upper four LEDs on the front panel of the board.
- */
-#define LED_0			0x00	/* OFF */
-#define LED_1			0x01	/* ON */
-#define LED_SLOW_CLOCK		0x02	/* SLOW 1Hz ish */
-#define LED_nSLOW_CLOCK		0x03	/* inverse of above */
-#define LED_WATCHDOG_OUT	0x06	/* Reset Watchdog level */
-#define LED_WATCHDOG_CLOCK	0x07	/* clock to watchdog */
-
-/*
- * LED's currently setup in AMD79C973 device as the following:
- * LED0 100Mbit
- * LED1 LNKSE
- * LED2 TX Activity
- * LED3 RX Activity
- */
-#define LED_E0_LED0		0x08	/* Ethernet Port 0 LED 0 */
-#define LED_E0_LED1		0x09	/* Ethernet Port 0 LED 1 */
-#define LED_E0_LED2		0x0A	/* Ethernet Port 0 LED 2 */
-#define LED_E0_LED3		0x0B	/* Ethernet Port 0 LED 3 */
-#define LED_E1_LED0		0x0C	/* Ethernet Port 1 LED 0 */
-#define LED_E1_LED1		0x0D	/* Ethernet Port 1 LED 1 */
-#define LED_E1_LED2		0x0E	/* Ethernet Port 1 LED 2 */
-#define LED_E1_LED3		0x0F	/* Ethernet Port 1 LED 3 */
-#define LED_STROBE0		0x10	/* Processor Strobe 0 */
-#define LED_STROBE1		0x11	/* Processor Strobe 1 */
-#define LED_STROBE2		0x12	/* Processor Strobe 2 */
-#define LED_STROBE3		0x13	/* Processor Strobe 3 */
-#define LED_STROBE4		0x14	/* Processor Strobe 4 */
-#define LED_STROBE5		0x15	/* Processor Strobe 5 */
-#define LED_STROBE6		0x16	/* Processor Strobe 6 */
-#define LED_STROBE7		0x17	/* Processor Strobe 7 */
-#define LED_HOST_STROBE0	0x18	/* Host strobe 0 */
-#define LED_HOST_STROBE1	0x19	/* Host strobe 1 */
-#define LED_HOST_STROBE2	0x1A	/* Host strobe 2 */
-#define LED_HOST_STROBE3	0x1B	/* Host strobe 3 */
-#define LED_HOST_STROBE4	0x1C	/* Host strobe 4 */
-#define LED_HOST_STROBE5	0x1D	/* Host strobe 5 */
-#define LED_HOST_STROBE6	0x1E	/* Host strobe 6 */
-#define LED_HOST_STROBE7	0x1F	/* Host strobe 7 */
-#define LED_MPC_INT0		0x20	/* MPC8240 INT 0 */
-#define LED_MPC_INT1		0x21	/* MPC8240 INT 1 */
-#define	LED_MPC_INT2		0x22	/* MPC8240 INT 2 */
-#define	LED_MPC_INT3		0x23	/* MPC8240 INT 3 */
-#define	LED_MPC_INT4		0x24	/* MPC8240 INT 4 */
-#define	LED_UART0_CS		0x25	/* UART 0 Chip Select */
-#define	LED_UART1_CS		0x26	/* UART 1 Chip Select */
-#define	LED_SRAM_CS		0x27	/* SRAM Chip Select */
-#define	LED_SRAM_WR		0x28	/* SRAM WR Signal */
-#define	LED_SRAM_RD		0x29	/* SRAM RD Signal */
-#define	LED_MPC_RCS0		0x2A	/* MPC8240 RCS0 Signal */
-#define	LED_S_PCI_FRAME		0x2B	/* Secondary PCI Frame Signal */
-#define	LED_MPC_CS0		0x2C	/* MPC8240 CS0 Signal */
-#define	LED_HOST_INT		0x2D	/* MPC8240 to Host Interrupt signal */
-#define LED_LAST_FUNCTION	LED_HOST_INT	/* last function */
-
-/*
- * Forward declarations
- */
-int  i2155x_init	 (void);
-void i2155x_write_scrapad(int idx, u32 val);
-u32  i2155x_read_scrapad (int idx);
-void i2155x_set_bar_base (int bar, u32 addr);
-int  i2155x_read_vpd	 (int offset, int size, unsigned char *data);
-
-int  am79c95x_init	 (void);
-
-void set_led		 (unsigned int number, unsigned int function);
-void fatal_error	 (unsigned int error_code);
-void show_startup_phase  (int phase);
-
-
-#endif /* _PN62_H_ */
diff --git a/board/ppcag/bg0900/Makefile b/board/ppcag/bg0900/Makefile
new file mode 100644
index 0000000000..74c6db5b15
--- /dev/null
+++ b/board/ppcag/bg0900/Makefile
@@ -0,0 +1,12 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+ifndef	CONFIG_SPL_BUILD
+obj-y	:= bg0900.o
+else
+obj-y	:= spl_boot.o
+endif
diff --git a/board/ppcag/bg0900/bg0900.c b/board/ppcag/bg0900/bg0900.c
new file mode 100644
index 0000000000..06612fa34d
--- /dev/null
+++ b/board/ppcag/bg0900/bg0900.c
@@ -0,0 +1,86 @@
+/*
+ * PPC-AG BG0900 board
+ *
+ * Copyright (C) 2013 Marek Vasut <marex@denx.de>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/gpio.h>
+#include <asm/io.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/iomux-mx28.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/sys_proto.h>
+#include <linux/mii.h>
+#include <miiphy.h>
+#include <netdev.h>
+#include <errno.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * Functions
+ */
+int board_early_init_f(void)
+{
+	/* IO0 clock at 480MHz */
+	mxs_set_ioclk(MXC_IOCLK0, 480000);
+	/* IO1 clock at 480MHz */
+	mxs_set_ioclk(MXC_IOCLK1, 480000);
+
+	/* SSP2 clock at 160MHz */
+	mxs_set_sspclk(MXC_SSPCLK2, 160000, 0);
+
+	return 0;
+}
+
+int dram_init(void)
+{
+	return mxs_dram_init();
+}
+
+int board_init(void)
+{
+	/* Adress of boot parameters */
+	gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
+
+	return 0;
+}
+
+#ifdef CONFIG_CMD_NET
+int board_eth_init(bd_t *bis)
+{
+	struct mxs_clkctrl_regs *clkctrl_regs =
+		(struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
+	struct eth_device *dev;
+	int ret;
+
+	ret = cpu_eth_init(bis);
+
+	/* BG0900 uses ENET_CLK PAD to drive FEC clock */
+	writel(CLKCTRL_ENET_TIME_SEL_RMII_CLK | CLKCTRL_ENET_CLK_OUT_EN,
+	       &clkctrl_regs->hw_clkctrl_enet);
+
+	/* Reset FEC PHYs */
+	gpio_direction_output(MX28_PAD_ENET0_RX_CLK__GPIO_4_13, 0);
+	udelay(200);
+	gpio_set_value(MX28_PAD_ENET0_RX_CLK__GPIO_4_13, 1);
+
+	ret = fecmxc_initialize_multi(bis, 0, 0, MXS_ENET0_BASE);
+	if (ret) {
+		puts("FEC MXS: Unable to init FEC0\n");
+		return ret;
+	}
+
+	dev = eth_get_dev_by_name("FEC0");
+	if (!dev) {
+		puts("FEC MXS: Unable to get FEC0 device entry\n");
+		return -EINVAL;
+	}
+
+	return ret;
+}
+
+#endif
diff --git a/board/ppcag/bg0900/spl_boot.c b/board/ppcag/bg0900/spl_boot.c
new file mode 100644
index 0000000000..a04c9553e4
--- /dev/null
+++ b/board/ppcag/bg0900/spl_boot.c
@@ -0,0 +1,153 @@
+/*
+ * PPC-AG BG0900 Boot setup
+ *
+ * Copyright (C) 2013 Marek Vasut <marex@denx.de>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <config.h>
+#include <asm/io.h>
+#include <asm/arch/iomux-mx28.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/sys_proto.h>
+
+#define	MUX_CONFIG_GPMI	(MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_NOPULL)
+#define	MUX_CONFIG_ENET	(MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP)
+#define	MUX_CONFIG_EMI	(MXS_PAD_3V3 | MXS_PAD_12MA | MXS_PAD_NOPULL)
+#define	MUX_CONFIG_SSP2	(MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP)
+
+const iomux_cfg_t iomux_setup[] = {
+	/* DUART */
+	MX28_PAD_PWM0__DUART_RX,
+	MX28_PAD_PWM1__DUART_TX,
+
+	/* GPMI NAND */
+	MX28_PAD_GPMI_D00__GPMI_D0 | MUX_CONFIG_GPMI,
+	MX28_PAD_GPMI_D01__GPMI_D1 | MUX_CONFIG_GPMI,
+	MX28_PAD_GPMI_D02__GPMI_D2 | MUX_CONFIG_GPMI,
+	MX28_PAD_GPMI_D03__GPMI_D3 | MUX_CONFIG_GPMI,
+	MX28_PAD_GPMI_D04__GPMI_D4 | MUX_CONFIG_GPMI,
+	MX28_PAD_GPMI_D05__GPMI_D5 | MUX_CONFIG_GPMI,
+	MX28_PAD_GPMI_D06__GPMI_D6 | MUX_CONFIG_GPMI,
+	MX28_PAD_GPMI_D07__GPMI_D7 | MUX_CONFIG_GPMI,
+	MX28_PAD_GPMI_CE0N__GPMI_CE0N | MUX_CONFIG_GPMI,
+	MX28_PAD_GPMI_RDY0__GPMI_READY0 | MUX_CONFIG_GPMI,
+	MX28_PAD_GPMI_RDN__GPMI_RDN |
+		(MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP),
+	MX28_PAD_GPMI_WRN__GPMI_WRN | MUX_CONFIG_GPMI,
+	MX28_PAD_GPMI_ALE__GPMI_ALE | MUX_CONFIG_GPMI,
+	MX28_PAD_GPMI_CLE__GPMI_CLE | MUX_CONFIG_GPMI,
+	MX28_PAD_GPMI_RESETN__GPMI_RESETN | MUX_CONFIG_GPMI,
+
+	/* FEC0 */
+	MX28_PAD_ENET0_MDC__ENET0_MDC | MUX_CONFIG_ENET,
+	MX28_PAD_ENET0_MDIO__ENET0_MDIO | MUX_CONFIG_ENET,
+	MX28_PAD_ENET0_RX_EN__ENET0_RX_EN | MUX_CONFIG_ENET,
+	MX28_PAD_ENET0_TX_EN__ENET0_TX_EN | MUX_CONFIG_ENET,
+	MX28_PAD_ENET0_RXD0__ENET0_RXD0 | MUX_CONFIG_ENET,
+	MX28_PAD_ENET0_RXD1__ENET0_RXD1 | MUX_CONFIG_ENET,
+	MX28_PAD_ENET0_TXD0__ENET0_TXD0 | MUX_CONFIG_ENET,
+	MX28_PAD_ENET0_TXD1__ENET0_TXD1 | MUX_CONFIG_ENET,
+	MX28_PAD_ENET_CLK__CLKCTRL_ENET | MUX_CONFIG_ENET,
+
+	/* FEC0 Reset */
+	MX28_PAD_ENET0_RX_CLK__GPIO_4_13 |
+		(MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
+
+	/* EMI */
+	MX28_PAD_EMI_D00__EMI_DATA0 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_D01__EMI_DATA1 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_D02__EMI_DATA2 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_D03__EMI_DATA3 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_D04__EMI_DATA4 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_D05__EMI_DATA5 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_D06__EMI_DATA6 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_D07__EMI_DATA7 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_D08__EMI_DATA8 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_D09__EMI_DATA9 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_D10__EMI_DATA10 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_D11__EMI_DATA11 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_D12__EMI_DATA12 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_D13__EMI_DATA13 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_D14__EMI_DATA14 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_D15__EMI_DATA15 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_ODT0__EMI_ODT0 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_DQM0__EMI_DQM0 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_ODT1__EMI_ODT1 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_DQM1__EMI_DQM1 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_DDR_OPEN_FB__EMI_DDR_OPEN_FEEDBACK | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_CLK__EMI_CLK | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_DQS0__EMI_DQS0 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_DQS1__EMI_DQS1 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_DDR_OPEN__EMI_DDR_OPEN | MUX_CONFIG_EMI,
+
+	MX28_PAD_EMI_A00__EMI_ADDR0 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_A01__EMI_ADDR1 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_A02__EMI_ADDR2 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_A03__EMI_ADDR3 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_A04__EMI_ADDR4 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_A05__EMI_ADDR5 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_A06__EMI_ADDR6 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_A07__EMI_ADDR7 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_A08__EMI_ADDR8 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_A09__EMI_ADDR9 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_A10__EMI_ADDR10 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_A11__EMI_ADDR11 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_A12__EMI_ADDR12 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_A13__EMI_ADDR13 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_A14__EMI_ADDR14 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_BA0__EMI_BA0 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_BA1__EMI_BA1 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_BA2__EMI_BA2 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_CASN__EMI_CASN | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_RASN__EMI_RASN | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_WEN__EMI_WEN | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_CE0N__EMI_CE0N | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_CE1N__EMI_CE1N | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_CKE__EMI_CKE | MUX_CONFIG_EMI,
+
+	/* SPI2 (for SPI flash) */
+	MX28_PAD_SSP2_SCK__SSP2_SCK | MUX_CONFIG_SSP2,
+	MX28_PAD_SSP2_MOSI__SSP2_CMD | MUX_CONFIG_SSP2,
+	MX28_PAD_SSP2_MISO__SSP2_D0 | MUX_CONFIG_SSP2,
+	MX28_PAD_SSP2_SS0__SSP2_D3 |
+		(MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP),
+};
+
+void mxs_adjust_memory_params(uint32_t *dram_vals)
+{
+	/*
+	 * DDR Controller Registers
+	 * Manufacturer:	Winbond
+	 * Device Part Number:	W972GG6JB-25I
+	 * Clock Freq.:		200MHz
+	 * Density:		2Gb
+	 * Chip Selects:	1
+	 * Number of Banks:	8
+	 * Row address:		14
+	 * Column address:	10
+	 */
+
+	dram_vals[0x74 / 4] = 0x0102010A;
+	dram_vals[0x98 / 4] = 0x04005003;
+	dram_vals[0x9c / 4] = 0x090000c8;
+
+	dram_vals[0xa8 / 4] = 0x0036b009;
+	dram_vals[0xac / 4] = 0x03270612;
+
+	dram_vals[0xb0 / 4] = 0x02020202;
+	dram_vals[0xb4 / 4] = 0x00c80029;
+
+	dram_vals[0xc0 / 4] = 0x00011900;
+
+	dram_vals[0x12c / 4] = 0x07400300;
+	dram_vals[0x130 / 4] = 0x07400300;
+	dram_vals[0x2c4 / 4] = 0x02030303;
+}
+
+void board_init_ll(const uint32_t arg, const uint32_t *resptr)
+{
+	mxs_common_spl_init(arg, resptr, iomux_setup, ARRAY_SIZE(iomux_setup));
+}
diff --git a/board/ppmc7xx/Makefile b/board/ppmc7xx/Makefile
index c6abc77cee..f8957f352b 100644
--- a/board/ppmc7xx/Makefile
+++ b/board/ppmc7xx/Makefile
@@ -5,26 +5,5 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-SOBJS	:= init.o
-
-COBJS	:= ppmc7xx.o pci.o flash.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
-	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	:= init.o
+obj-y	+= ppmc7xx.o pci.o flash.o
diff --git a/board/ppmc8260/Makefile b/board/ppmc8260/Makefile
index d0e543cf29..3072fb4676 100644
--- a/board/ppmc8260/Makefile
+++ b/board/ppmc8260/Makefile
@@ -5,24 +5,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	:= ppmc8260.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	:= ppmc8260.o
diff --git a/board/pr1/Makefile b/board/pr1/Makefile
index f023abfee4..4f375a8b5c 100644
--- a/board/pr1/Makefile
+++ b/board/pr1/Makefile
@@ -11,24 +11,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS-y	:= $(BOARD).o
-
-SRCS	:= $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS-y))
-SOBJS	:= $(addprefix $(obj),$(SOBJS-y))
-
-$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
-	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	:= pr1.o
diff --git a/board/pr1/config.mk b/board/pr1/config.mk
deleted file mode 100644
index 5c18d5c9e4..0000000000
--- a/board/pr1/config.mk
+++ /dev/null
@@ -1,14 +0,0 @@
-#
-# Copyright (c) Switchfin Org. <dpn@switchfin.org>
-#
-# Copyright (c) 2005-2008 Analog Device Inc.
-#
-# (C) Copyright 2001
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-CFLAGS_lib += -O2
-CFLAGS_lib/lzma += -O2
-CFLAGS_lib/zlib += -O2
diff --git a/board/prodrive/alpr/Makefile b/board/prodrive/alpr/Makefile
index 5345df8c9f..812d041ef2 100644
--- a/board/prodrive/alpr/Makefile
+++ b/board/prodrive/alpr/Makefile
@@ -5,25 +5,5 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	= $(BOARD).o fpga.o nand.o
-SOBJS	= init.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(OBJS) $(SOBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	= alpr.o fpga.o nand.o
+extra-y	+= init.o
diff --git a/board/prodrive/p3mx/Makefile b/board/prodrive/p3mx/Makefile
index 63ee945d2a..6ddda2296d 100644
--- a/board/prodrive/p3mx/Makefile
+++ b/board/prodrive/p3mx/Makefile
@@ -5,29 +5,6 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-ifneq ($(OBJTREE),$(SRCTREE))
-$(shell mkdir -p $(obj)../../Marvell/common)
-endif
-
-LIB	= $(obj)lib$(BOARD).o
-
-SOBJS	= misc.o
-COBJS	= $(BOARD).o mpsc.o mv_eth.o pci.o sdram_init.o serial.o \
+obj-y	= misc.o
+obj-y	+= p3mx.o mpsc.o mv_eth.o pci.o sdram_init.o serial.o \
 		../../Marvell/common/i2c.o ../../Marvell/common/memory.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
-	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
diff --git a/board/prodrive/p3mx/ppc_error_no.h b/board/prodrive/p3mx/ppc_error_no.h
deleted file mode 100644
index 58a68b5d89..0000000000
--- a/board/prodrive/p3mx/ppc_error_no.h
+++ /dev/null
@@ -1,148 +0,0 @@
-/*
- * (C) Copyright 2003
- * Ingo Assmus <ingo.assmus@keymile.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-/*
- * BK Id: SCCS/s.errno.h 1.9 06/05/01 21:45:21 paulus
- */
-#ifndef _MV_PPC_ERRNO_H
-#define _MV_PPC_ERRNO_H
-
-#define	EPERM		 1	/* Operation not permitted */
-#define	ENOENT		 2	/* No such file or directory */
-#define	ESRCH		 3	/* No such process */
-#define	EINTR		 4	/* Interrupted system call */
-#define	EIO		 5	/* I/O error */
-#define	ENXIO		 6	/* No such device or address */
-#define	E2BIG		 7	/* Arg list too long */
-#define	ENOEXEC		 8	/* Exec format error */
-#define	EBADF		 9	/* Bad file number */
-#define	ECHILD		10	/* No child processes */
-#define	EAGAIN		11	/* Try again */
-#define	ENOMEM		12	/* Out of memory */
-#define	EACCES		13	/* Permission denied */
-#define	EFAULT		14	/* Bad address */
-#define	ENOTBLK		15	/* Block device required */
-#define	EBUSY		16	/* Device or resource busy */
-#define	EEXIST		17	/* File exists */
-#define	EXDEV		18	/* Cross-device link */
-#define	ENODEV		19	/* No such device */
-#define	ENOTDIR		20	/* Not a directory */
-#define	EISDIR		21	/* Is a directory */
-#define	EINVAL		22	/* Invalid argument */
-#define	ENFILE		23	/* File table overflow */
-#define	EMFILE		24	/* Too many open files */
-#define	ENOTTY		25	/* Not a typewriter */
-#define	ETXTBSY		26	/* Text file busy */
-#define	EFBIG		27	/* File too large */
-#define	ENOSPC		28	/* No space left on device */
-#define	ESPIPE		29	/* Illegal seek */
-#define	EROFS		30	/* Read-only file system */
-#define	EMLINK		31	/* Too many links */
-#define	EPIPE		32	/* Broken pipe */
-#define	EDOM		33	/* Math argument out of domain of func */
-#define	ERANGE		34	/* Math result not representable */
-#define	EDEADLK		35	/* Resource deadlock would occur */
-#define	ENAMETOOLONG	36	/* File name too long */
-#define	ENOLCK		37	/* No record locks available */
-#define	ENOSYS		38	/* Function not implemented */
-#define	ENOTEMPTY	39	/* Directory not empty */
-#define	ELOOP		40	/* Too many symbolic links encountered */
-#define	EWOULDBLOCK	EAGAIN	/* Operation would block */
-#define	ENOMSG		42	/* No message of desired type */
-#define	EIDRM		43	/* Identifier removed */
-#define	ECHRNG		44	/* Channel number out of range */
-#define	EL2NSYNC	45	/* Level 2 not synchronized */
-#define	EL3HLT		46	/* Level 3 halted */
-#define	EL3RST		47	/* Level 3 reset */
-#define	ELNRNG		48	/* Link number out of range */
-#define	EUNATCH		49	/* Protocol driver not attached */
-#define	ENOCSI		50	/* No CSI structure available */
-#define	EL2HLT		51	/* Level 2 halted */
-#define	EBADE		52	/* Invalid exchange */
-#define	EBADR		53	/* Invalid request descriptor */
-#define	EXFULL		54	/* Exchange full */
-#define	ENOANO		55	/* No anode */
-#define	EBADRQC		56	/* Invalid request code */
-#define	EBADSLT		57	/* Invalid slot */
-#define	EDEADLOCK	58	/* File locking deadlock error */
-#define	EBFONT		59	/* Bad font file format */
-#define	ENOSTR		60	/* Device not a stream */
-#define	ENODATA		61	/* No data available */
-#define	ETIME		62	/* Timer expired */
-#define	ENOSR		63	/* Out of streams resources */
-#define	ENONET		64	/* Machine is not on the network */
-#define	ENOPKG		65	/* Package not installed */
-#define	EREMOTE		66	/* Object is remote */
-#define	ENOLINK		67	/* Link has been severed */
-#define	EADV		68	/* Advertise error */
-#define	ESRMNT		69	/* Srmount error */
-#define	ECOMM		70	/* Communication error on send */
-#define	EPROTO		71	/* Protocol error */
-#define	EMULTIHOP	72	/* Multihop attempted */
-#define	EDOTDOT		73	/* RFS specific error */
-#define	EBADMSG		74	/* Not a data message */
-#define	EOVERFLOW	75	/* Value too large for defined data type */
-#define	ENOTUNIQ	76	/* Name not unique on network */
-#define	EBADFD		77	/* File descriptor in bad state */
-#define	EREMCHG		78	/* Remote address changed */
-#define	ELIBACC		79	/* Can not access a needed shared library */
-#define	ELIBBAD		80	/* Accessing a corrupted shared library */
-#define	ELIBSCN		81	/* .lib section in a.out corrupted */
-#define	ELIBMAX		82	/* Attempting to link in too many shared libraries */
-#define	ELIBEXEC	83	/* Cannot exec a shared library directly */
-#define	EILSEQ		84	/* Illegal byte sequence */
-#define	ERESTART	85	/* Interrupted system call should be restarted */
-#define	ESTRPIPE	86	/* Streams pipe error */
-#define	EUSERS		87	/* Too many users */
-#define	ENOTSOCK	88	/* Socket operation on non-socket */
-#define	EDESTADDRREQ	89	/* Destination address required */
-#define	EMSGSIZE	90	/* Message too long */
-#define	EPROTOTYPE	91	/* Protocol wrong type for socket */
-#define	ENOPROTOOPT	92	/* Protocol not available */
-#define	EPROTONOSUPPORT	93	/* Protocol not supported */
-#define	ESOCKTNOSUPPORT	94	/* Socket type not supported */
-#define	EOPNOTSUPP	95	/* Operation not supported on transport endpoint */
-#define	EPFNOSUPPORT	96	/* Protocol family not supported */
-#define	EAFNOSUPPORT	97	/* Address family not supported by protocol */
-#define	EADDRINUSE	98	/* Address already in use */
-#define	EADDRNOTAVAIL	99	/* Cannot assign requested address */
-#define	ENETDOWN	100	/* Network is down */
-#define	ENETUNREACH	101	/* Network is unreachable */
-#define	ENETRESET	102	/* Network dropped connection because of reset */
-#define	ECONNABORTED	103	/* Software caused connection abort */
-#define	ECONNRESET	104	/* Connection reset by peer */
-#define	ENOBUFS		105	/* No buffer space available */
-#define	EISCONN		106	/* Transport endpoint is already connected */
-#define	ENOTCONN	107	/* Transport endpoint is not connected */
-#define	ESHUTDOWN	108	/* Cannot send after transport endpoint shutdown */
-#define	ETOOMANYREFS	109	/* Too many references: cannot splice */
-#define	ETIMEDOUT	110	/* Connection timed out */
-#define	ECONNREFUSED	111	/* Connection refused */
-#define	EHOSTDOWN	112	/* Host is down */
-#define	EHOSTUNREACH	113	/* No route to host */
-#define	EALREADY	114	/* Operation already in progress */
-#define	EINPROGRESS	115	/* Operation now in progress */
-#define	ESTALE		116	/* Stale NFS file handle */
-#define	EUCLEAN		117	/* Structure needs cleaning */
-#define	ENOTNAM		118	/* Not a XENIX named type file */
-#define	ENAVAIL		119	/* No XENIX semaphores available */
-#define	EISNAM		120	/* Is a named type file */
-#define	EREMOTEIO	121	/* Remote I/O error */
-#define	EDQUOT		122	/* Quota exceeded */
-
-#define	ENOMEDIUM	123	/* No medium found */
-#define	EMEDIUMTYPE	124	/* Wrong medium type */
-
-/* Should never be seen by user programs */
-#define ERESTARTSYS	512
-#define ERESTARTNOINTR	513
-#define ERESTARTNOHAND	514	/* restart if no handler.. */
-#define ENOIOCTLCMD	515	/* No ioctl command */
-
-#define _LAST_ERRNO	515
-
-#endif
diff --git a/board/prodrive/p3mx/serial.c b/board/prodrive/p3mx/serial.c
index 89040a899e..5b7b989860 100644
--- a/board/prodrive/p3mx/serial.c
+++ b/board/prodrive/p3mx/serial.c
@@ -23,7 +23,6 @@
 #include <linux/compiler.h>
 
 #include "../../Marvell/include/memory.h"
-#include "serial.h"
 
 #include "mpsc.h"
 
diff --git a/board/prodrive/p3mx/serial.h b/board/prodrive/p3mx/serial.h
deleted file mode 100644
index 264e2d236e..0000000000
--- a/board/prodrive/p3mx/serial.h
+++ /dev/null
@@ -1,73 +0,0 @@
-/*
- * (C) Copyright 2001
- * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
- *
- * modified for marvell db64360 eval board by
- * Ingo Assmus <ingo.assmus@keymile.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-/* serial.h - mostly useful for DUART serial_init in serial.c */
-
-#ifndef __SERIAL_H__
-#define __SERIAL_H__
-
-#if 0
-
-#define B230400         1
-#define B115200         2
-#define B57600          4
-#define B38400          82
-#define B19200          163
-#define B9600           24
-#define B4800           651
-#define B2400           1302
-#define B1200           2604
-#define B600            5208
-#define B300            10417
-#define B150            20833
-#define B110            28409
-#define BDEFAULT        B115200
-
-				/* this stuff is important to initialize
-				the DUART channels */
-
-#define	Scale		0x01L		/* distance between port addresses */
-#define	COM1		0x000003f8		/* Keyboard */
-#define COM2		0x000002f8		/* Host */
-
-
-/* Port Definitions relative to base COM port addresses */
-#define DataIn	(0x00*Scale)	/* data input port */
-#define DataOut	(0x00*Scale)	/* data output port */
-#define BaudLsb	(0x00*Scale)	/* baud rate divisor least significant byte */
-#define BaudMsb	(0x01*Scale)	/* baud rate divisor most significant byte */
-#define	Ier	(0x01*Scale)	/* interrupt enable register */
-#define	Iir	(0x02*Scale)	/* interrupt identification register */
-#define	Lcr	(0x03*Scale)	/* line control register */
-#define	Mcr	(0x04*Scale)	/* modem control register */
-#define	Lsr	(0x05*Scale)	/* line status register */
-#define	Msr	(0x06*Scale)	/* modem status register */
-
-/* Bit Definitions for above ports */
-#define LcrDlab	0x80	/* b7:	 enable baud rate divisor registers */
-#define	LcrDflt	0x03	/* b6-0: no parity, 1 stop, 8 data */
-
-#define	McrRts	0x02	/* b1:	request to send (I am ready to xmit) */
-#define	McrDtr	0x01	/* b0:	data terminal ready (I am alive ready to rcv) */
-#define	McrDflt	(McrRts|McrDtr)
-
-#define LsrTxD	0x6000	/* b5: transmit holding register empty (i.e. xmit OK!)*/
-			/* b6: transmitter empty */
-#define LsrRxD	0x0100	/* b0: received data ready (i.e. got a byte!) */
-
-#define	MsrRi	0x0040	/* b6: ring indicator (other guy is ready to rcv) */
-#define	MsrDsr	0x0020	/* b5: data set ready (other guy is alive ready to rcv */
-#define	MsrCts	0x0010	/* b4: clear to send (other guy is ready to rcv) */
-
-#define IerRda	0xf	/* b0: Enable received data available interrupt */
-
-#endif
-
-#endif /* __SERIAL_H__ */
diff --git a/board/prodrive/p3p440/Makefile b/board/prodrive/p3p440/Makefile
index 1d80df8b74..d62f75d3e7 100644
--- a/board/prodrive/p3p440/Makefile
+++ b/board/prodrive/p3p440/Makefile
@@ -5,25 +5,5 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	= $(BOARD).o
-SOBJS	= init.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(OBJS) $(SOBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	= p3p440.o
+extra-y	+= init.o
diff --git a/board/prodrive/pdnb3/Makefile b/board/prodrive/pdnb3/Makefile
deleted file mode 100644
index 5e4a909589..0000000000
--- a/board/prodrive/pdnb3/Makefile
+++ /dev/null
@@ -1,28 +0,0 @@
-#
-# (C) Copyright 2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	:= flash.o pdnb3.o nand.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
diff --git a/board/prodrive/pdnb3/flash.c b/board/prodrive/pdnb3/flash.c
deleted file mode 100644
index 75b5d0544a..0000000000
--- a/board/prodrive/pdnb3/flash.c
+++ /dev/null
@@ -1,73 +0,0 @@
-/*
- * (C) Copyright 2006
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/arch/ixp425.h>
-
-#if !defined(CONFIG_FLASH_CFI_DRIVER)
-
-/*
- * include common flash code (for esd boards)
- */
-#include "../common/flash.c"
-
-/*
- * Prototypes
- */
-static ulong flash_get_size (vu_long * addr, flash_info_t * info);
-
-static inline ulong ld(ulong x)
-{
-	ulong k = 0;
-
-	while (x >>= 1)
-		++k;
-
-	return k;
-}
-
-unsigned long flash_init(void)
-{
-	unsigned long size;
-	int i;
-
-	/* Init: no FLASHes known */
-	for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; i++)
-		flash_info[i].flash_id = FLASH_UNKNOWN;
-
-	size = flash_get_size((vu_long *)FLASH_BASE0_PRELIM, &flash_info[0]);
-
-	if (flash_info[0].flash_id == FLASH_UNKNOWN)
-		printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
-			size, size<<20);
-
-	/* Reconfigure CS0 to actual FLASH size */
-	*IXP425_EXP_CS0 = (*IXP425_EXP_CS0 & ~0x00003C00) | ((ld(size) - 9) << 10);
-
-	/* Monitor protection ON by default */
-	flash_protect(FLAG_PROTECT_SET,
-		      CONFIG_SYS_MONITOR_BASE, CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1,
-		      &flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]);
-
-	/* Environment protection ON by default */
-	flash_protect(FLAG_PROTECT_SET,
-		      CONFIG_ENV_ADDR,
-		      CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE - 1,
-		      &flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]);
-
-	/* Redundant environment protection ON by default */
-	flash_protect(FLAG_PROTECT_SET,
-		      CONFIG_ENV_ADDR_REDUND,
-		      CONFIG_ENV_ADDR_REDUND + CONFIG_ENV_SECT_SIZE - 1,
-		      &flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]);
-
-	flash_info[0].size = size;
-
-	return size;
-}
-
-#endif /* CONFIG_FLASH_CFI_DRIVER */
diff --git a/board/prodrive/pdnb3/nand.c b/board/prodrive/pdnb3/nand.c
deleted file mode 100644
index e1d2c630bf..0000000000
--- a/board/prodrive/pdnb3/nand.c
+++ /dev/null
@@ -1,129 +0,0 @@
-/*
- * (C) Copyright 2006
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-
-#if defined(CONFIG_CMD_NAND)
-
-#include <nand.h>
-
-struct pdnb3_ndfc_regs {
-	uchar cmd;
-	uchar wait;
-	uchar addr;
-	uchar term;
-	uchar data;
-};
-
-static u8 hwctl;
-static struct pdnb3_ndfc_regs *pdnb3_ndfc;
-
-#define readb(addr)	*(volatile u_char *)(addr)
-#define readl(addr)	*(volatile u_long *)(addr)
-#define writeb(d,addr)	*(volatile u_char *)(addr) = (d)
-
-/*
- * The PDNB3 has a NAND Flash Controller (NDFC) that handles all accesses to
- * the NAND devices.  The NDFC has command, address and data registers that
- * when accessed will set up the NAND flash pins appropriately.  We'll use the
- * hwcontrol function to save the configuration in a global variable.
- * We can then use this information in the read and write functions to
- * determine which NDFC register to access.
- *
- * There is one NAND devices on the board, a Hynix HY27US08561A (32 MByte).
- */
-static void pdnb3_nand_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)
-{
-	struct nand_chip *this = mtd->priv;
-
-	if (ctrl & NAND_CTRL_CHANGE) {
-		if ( ctrl & NAND_CLE )
-			hwctl |= 0x1;
-		else
-			hwctl &= ~0x1;
-		if ( ctrl & NAND_ALE )
-			hwctl |= 0x2;
-		else
-			hwctl &= ~0x2;
-		if ( (ctrl & NAND_NCE) != NAND_NCE)
-			writeb(0x00, &(pdnb3_ndfc->term));
-	}
-	if (cmd != NAND_CMD_NONE)
-		writeb(cmd, this->IO_ADDR_W);
-}
-
-
-static u_char pdnb3_nand_read_byte(struct mtd_info *mtd)
-{
-	return readb(&(pdnb3_ndfc->data));
-}
-
-static void pdnb3_nand_write_buf(struct mtd_info *mtd, const u_char *buf, int len)
-{
-	int i;
-
-	for (i = 0; i < len; i++) {
-		if (hwctl & 0x1)
-			writeb(buf[i], &(pdnb3_ndfc->cmd));
-		else if (hwctl & 0x2)
-			writeb(buf[i], &(pdnb3_ndfc->addr));
-		else
-			writeb(buf[i], &(pdnb3_ndfc->data));
-	}
-}
-
-static void pdnb3_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len)
-{
-	int i;
-
-	for (i = 0; i < len; i++)
-		buf[i] = readb(&(pdnb3_ndfc->data));
-}
-
-static int pdnb3_nand_verify_buf(struct mtd_info *mtd, const u_char *buf, int len)
-{
-	int i;
-
-	for (i = 0; i < len; i++)
-		if (buf[i] != readb(&(pdnb3_ndfc->data)))
-			return i;
-
-	return 0;
-}
-
-static int pdnb3_nand_dev_ready(struct mtd_info *mtd)
-{
-	/*
-	 * Blocking read to wait for NAND to be ready
-	 */
-	readb(&(pdnb3_ndfc->wait));
-
-	/*
-	 * Return always true
-	 */
-	return 1;
-}
-
-int board_nand_init(struct nand_chip *nand)
-{
-	pdnb3_ndfc = (struct pdnb3_ndfc_regs *)CONFIG_SYS_NAND_BASE;
-
-	nand->ecc.mode = NAND_ECC_SOFT;
-
-	/* Set address of NAND IO lines (Using Linear Data Access Region) */
-	nand->IO_ADDR_R = (void __iomem *) ((ulong) pdnb3_ndfc + 0x4);
-	nand->IO_ADDR_W = (void __iomem *) ((ulong) pdnb3_ndfc + 0x4);
-	/* Reference hardware control function */
-	nand->cmd_ctrl   = pdnb3_nand_hwcontrol;
-	nand->read_byte  = pdnb3_nand_read_byte;
-	nand->write_buf  = pdnb3_nand_write_buf;
-	nand->read_buf   = pdnb3_nand_read_buf;
-	nand->verify_buf = pdnb3_nand_verify_buf;
-	nand->dev_ready  = pdnb3_nand_dev_ready;
-	return 0;
-}
-#endif
diff --git a/board/prodrive/pdnb3/pdnb3.c b/board/prodrive/pdnb3/pdnb3.c
deleted file mode 100644
index fa320da2d4..0000000000
--- a/board/prodrive/pdnb3/pdnb3.c
+++ /dev/null
@@ -1,220 +0,0 @@
-/*
- * (C) Copyright 2006
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <command.h>
-#include <malloc.h>
-#include <asm/arch/ixp425.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-/* predefine these here for FPGA programming (before including fpga.c) */
-#define SET_FPGA(data)	*IXP425_GPIO_GPOUTR = (data)
-#define FPGA_DONE_STATE (*IXP425_GPIO_GPINR & CONFIG_SYS_FPGA_DONE)
-#define FPGA_INIT_STATE (*IXP425_GPIO_GPINR & CONFIG_SYS_FPGA_INIT)
-#define OLD_VAL		old_val
-
-static unsigned long old_val = 0;
-
-/*
- * include common fpga code (for prodrive boards)
- */
-#include "../common/fpga.c"
-
-/*
- * Miscelaneous platform dependent initialisations
- */
-int board_init(void)
-{
-	/* adress of boot parameters */
-	gd->bd->bi_boot_params = 0x00000100;
-
-	GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_FPGA_RESET);
-	GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_FPGA_RESET);
-
-	GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_SYS_RUNNING);
-	GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_SYS_RUNNING);
-
-	/*
-	 * Setup GPIO's for FPGA programming
-	 */
-	GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_PRG);
-	GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_CLK);
-	GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_DATA);
-	GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_PRG);
-	GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_CLK);
-	GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_DATA);
-	GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_INIT);
-	GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_DONE);
-
-	/*
-	 * Setup GPIO's for interrupts
-	 */
-	GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_PCI_INTA);
-	GPIO_INT_ACT_LOW_SET(CONFIG_SYS_GPIO_PCI_INTA);
-	GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_PCI_INTB);
-	GPIO_INT_ACT_LOW_SET(CONFIG_SYS_GPIO_PCI_INTB);
-	GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_RESTORE_INT);
-	GPIO_INT_ACT_LOW_SET(CONFIG_SYS_GPIO_RESTORE_INT);
-	GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_RESTART_INT);
-	GPIO_INT_ACT_LOW_SET(CONFIG_SYS_GPIO_RESTART_INT);
-
-	/*
-	 * Setup GPIO's for 33MHz clock output
-	 */
-	*IXP425_GPIO_GPCLKR = 0x01FF0000;
-	GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_CLK_33M);
-
-	/*
-	 * Setup other chip select's
-	 */
-	*IXP425_EXP_CS1 = CONFIG_SYS_EXP_CS1;
-
-	return 0;
-}
-
-/*
- * Check Board Identity
- */
-int checkboard(void)
-{
-	char buf[64];
-	int i = getenv_f("serial#", buf, sizeof(buf));
-
-	puts("Board: PDNB3");
-
-	if (i > 0) {
-		puts(", serial# ");
-		puts(buf);
-	}
-	putc('\n');
-
-	return (0);
-}
-
-int dram_init(void)
-{
-	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
-	gd->bd->bi_dram[0].size  = PHYS_SDRAM_1_SIZE;
-
-	return (0);
-}
-
-int do_fpga_boot(unsigned char *fpgadata)
-{
-	unsigned char *dst;
-	int status;
-	int index;
-	int i;
-	ulong len = CONFIG_SYS_MALLOC_LEN;
-
-	/*
-	 * Setup GPIO's for FPGA programming
-	 */
-	GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_PRG);
-	GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_CLK);
-	GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_DATA);
-
-	/*
-	 * Save value so no readback is required upon programming
-	 */
-	old_val = *IXP425_GPIO_GPOUTR;
-
-	/*
-	 * First try to decompress fpga image (gzip compressed?)
-	 */
-	dst = malloc(CONFIG_SYS_FPGA_MAX_SIZE);
-	if (gunzip(dst, CONFIG_SYS_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) {
-		printf("Error: Image has to be gzipp'ed!\n");
-		return -1;
-	}
-
-	status = fpga_boot(dst, len);
-	if (status != 0) {
-		printf("\nFPGA: Booting failed ");
-		switch (status) {
-		case ERROR_FPGA_PRG_INIT_LOW:
-			printf("(Timeout: INIT not low after asserting PROGRAM*)\n ");
-			break;
-		case ERROR_FPGA_PRG_INIT_HIGH:
-			printf("(Timeout: INIT not high after deasserting PROGRAM*)\n ");
-			break;
-		case ERROR_FPGA_PRG_DONE:
-			printf("(Timeout: DONE not high after programming FPGA)\n ");
-			break;
-		}
-
-		/* display infos on fpgaimage */
-		index = 15;
-		for (i=0; i<4; i++) {
-			len = dst[index];
-			printf("FPGA: %s\n", &(dst[index+1]));
-			index += len+3;
-		}
-		putc ('\n');
-		/* delayed reboot */
-		for (i=5; i>0; i--) {
-			printf("Rebooting in %2d seconds \r",i);
-			for (index=0;index<1000;index++)
-				udelay(1000);
-		}
-		putc('\n');
-		do_reset(NULL, 0, 0, NULL);
-	}
-
-	puts("FPGA:  ");
-
-	/* display infos on fpgaimage */
-	index = 15;
-	for (i=0; i<4; i++) {
-		len = dst[index];
-		printf("%s ", &(dst[index+1]));
-		index += len+3;
-	}
-	putc('\n');
-
-	free(dst);
-
-	/*
-	 * Reset FPGA
-	 */
-	GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_FPGA_RESET);
-	udelay(10);
-	GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_FPGA_RESET);
-
-	return (0);
-}
-
-int do_fpga(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
-	ulong addr;
-
-	if (argc < 2)
-		return cmd_usage(cmdtp);
-
-	addr = simple_strtoul(argv[1], NULL, 16);
-
-	return do_fpga_boot((unsigned char *)addr);
-}
-
-U_BOOT_CMD(
-	fpga,     2,     0,      do_fpga,
-	"boot FPGA",
-	"address size\n    - boot FPGA with gzipped image at <address>"
-);
-
-#if defined(CONFIG_CMD_PCI) || defined(CONFIG_PCI)
-extern struct pci_controller hose;
-extern void pci_ixp_init(struct pci_controller * hose);
-
-void pci_init_board(void)
-{
-	extern void pci_ixp_init (struct pci_controller *hose);
-
-	pci_ixp_init(&hose);
-}
-#endif
diff --git a/board/psyent/pci5441/Makefile b/board/psyent/pci5441/Makefile
index 68c18b95c7..364f163e4f 100644
--- a/board/psyent/pci5441/Makefile
+++ b/board/psyent/pci5441/Makefile
@@ -5,29 +5,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-ifneq ($(OBJTREE),$(SRCTREE))
-$(shell mkdir -p $(obj)../common)
-endif
-
-LIB	= $(obj)lib$(BOARD).o
-
-COMOBJS := ../common/AMDLV065D.o
-
-COBJS	:= $(BOARD).o $(COMOBJS)
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	:= pci5441.o ../common/AMDLV065D.o
diff --git a/board/psyent/pci5441/config.mk b/board/psyent/pci5441/config.mk
index 00ff743c96..776fa8ab40 100644
--- a/board/psyent/pci5441/config.mk
+++ b/board/psyent/pci5441/config.mk
@@ -8,7 +8,6 @@
 CONFIG_SYS_TEXT_BASE = 0x018e0000
 
 PLATFORM_CPPFLAGS += -mno-hw-div -mno-hw-mul
-PLATFORM_CPPFLAGS += -I$(TOPDIR)/board/$(VENDOR)/include
 
 ifeq ($(debug),1)
 PLATFORM_CPPFLAGS += -DDEBUG
diff --git a/board/psyent/pk1c20/Makefile b/board/psyent/pk1c20/Makefile
index 0e704a5a5f..5450f93ac3 100644
--- a/board/psyent/pk1c20/Makefile
+++ b/board/psyent/pk1c20/Makefile
@@ -5,29 +5,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-ifneq ($(OBJTREE),$(SRCTREE))
-$(shell mkdir -p $(obj)../common)
-endif
-
-LIB	= $(obj)lib$(BOARD).o
-
-COMOBJS := ../common/AMDLV065D.o
-
-COBJS	:= $(BOARD).o led.o $(COMOBJS)
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	:= pk1c20.o led.o ../common/AMDLV065D.o
diff --git a/board/psyent/pk1c20/config.mk b/board/psyent/pk1c20/config.mk
index 7b0810a302..83cfadc113 100644
--- a/board/psyent/pk1c20/config.mk
+++ b/board/psyent/pk1c20/config.mk
@@ -8,7 +8,6 @@
 CONFIG_SYS_TEXT_BASE = 0x01fc0000
 
 PLATFORM_CPPFLAGS += -mno-hw-div -mno-hw-mul
-PLATFORM_CPPFLAGS += -I$(TOPDIR)/board/$(VENDOR)/include
 
 ifeq ($(debug),1)
 PLATFORM_CPPFLAGS += -DDEBUG
diff --git a/board/pxa255_idp/Makefile b/board/pxa255_idp/Makefile
index a57165cccb..59d696741d 100644
--- a/board/pxa255_idp/Makefile
+++ b/board/pxa255_idp/Makefile
@@ -1,4 +1,3 @@
-
 #
 # (C) Copyright 2000-2006
 # Wolfgang Denk, DENX Software Engineering, wd@denx.de.
@@ -6,23 +5,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	:= pxa_idp.o
-
-SRCS	:= $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	:= pxa_idp.o
diff --git a/board/qemu-malta/Makefile b/board/qemu-malta/Makefile
deleted file mode 100644
index 70603414f4..0000000000
--- a/board/qemu-malta/Makefile
+++ /dev/null
@@ -1,29 +0,0 @@
-#
-# (C) Copyright 2003-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	= $(BOARD).o
-SOBJS	= lowlevel_init.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	 $(OBJS) $(SOBJS)
-	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
diff --git a/board/qemu-malta/lowlevel_init.S b/board/qemu-malta/lowlevel_init.S
deleted file mode 100644
index fa0b6a7d13..0000000000
--- a/board/qemu-malta/lowlevel_init.S
+++ /dev/null
@@ -1,69 +0,0 @@
-/*
- * Copyright (C) 2013 Gabor Juhos <juhosg@openwrt.org>
- *
- * SPDX-License-Identifier:	GPL-2.0
- */
-
-#include <config.h>
-#include <gt64120.h>
-
-#include <asm/addrspace.h>
-#include <asm/regdef.h>
-#include <asm/malta.h>
-
-#ifdef CONFIG_SYS_BIG_ENDIAN
-#define CPU_TO_GT32(_x)		((_x))
-#else
-#define CPU_TO_GT32(_x) (					\
-	(((_x) & 0xff) << 24) | (((_x) & 0xff00) << 8) |	\
-	(((_x) & 0xff0000) >> 8) | (((_x) & 0xff000000) >> 24))
-#endif
-
-	.text
-	.set noreorder
-	.set mips32
-
-	.globl	lowlevel_init
-lowlevel_init:
-
-	/*
-	 * Load BAR registers of GT64120 as done by YAMON
-	 *
-	 * based on a patch sent by Antony Pavlov <antonynpavlov@gmail.com>
-	 * to the barebox mailing list.
-	 * The subject of the original patch:
-	 *   'MIPS: qemu-malta: add YAMON-style GT64120 memory map'
-	 * URL:
-	 * http://www.mail-archive.com/barebox@lists.infradead.org/msg06128.html
-	 *
-	 * based on write_bootloader() in qemu.git/hw/mips_malta.c
-	 * see GT64120 manual and qemu.git/hw/gt64xxx.c for details
-	 */
-
-	/* move GT64120 registers from 0x14000000 to 0x1be00000 */
-	li	t1, KSEG1ADDR(GT_DEF_BASE)
-	li	t0, CPU_TO_GT32(0xdf000000)
-	sw	t0, GT_ISD_OFS(t1)
-
-	/* setup MEM-to-PCI0 mapping */
-	li	t1, KSEG1ADDR(MALTA_GT_BASE)
-
-	/* setup PCI0 io window to 0x18000000-0x181fffff */
-	li	t0, CPU_TO_GT32(0xc0000000)
-	sw	t0, GT_PCI0IOLD_OFS(t1)
-	li	t0, CPU_TO_GT32(0x40000000)
-	sw	t0, GT_PCI0IOHD_OFS(t1)
-
-	/* setup PCI0 mem windows */
-	li	t0, CPU_TO_GT32(0x80000000)
-	sw	t0, GT_PCI0M0LD_OFS(t1)
-	li	t0, CPU_TO_GT32(0x3f000000)
-	sw	t0, GT_PCI0M0HD_OFS(t1)
-
-	li	t0, CPU_TO_GT32(0xc1000000)
-	sw	t0, GT_PCI0M1LD_OFS(t1)
-	li	t0, CPU_TO_GT32(0x5e000000)
-	sw	t0, GT_PCI0M1HD_OFS(t1)
-
-	jr	ra
-	 nop
diff --git a/board/qemu-malta/qemu-malta.c b/board/qemu-malta/qemu-malta.c
deleted file mode 100644
index 7eddf1ce66..0000000000
--- a/board/qemu-malta/qemu-malta.c
+++ /dev/null
@@ -1,47 +0,0 @@
-/*
- * Copyright (C) 2013 Gabor Juhos <juhosg@openwrt.org>
- *
- * SPDX-License-Identifier:	GPL-2.0
- */
-
-#include <common.h>
-#include <netdev.h>
-
-#include <asm/addrspace.h>
-#include <asm/io.h>
-#include <asm/malta.h>
-#include <pci_gt64120.h>
-
-phys_size_t initdram(int board_type)
-{
-	return CONFIG_SYS_MEM_SIZE;
-}
-
-int checkboard(void)
-{
-	puts("Board: MIPS Malta CoreLV (Qemu)\n");
-	return 0;
-}
-
-int board_eth_init(bd_t *bis)
-{
-	return pci_eth_init(bis);
-}
-
-void _machine_restart(void)
-{
-	void __iomem *reset_base;
-
-	reset_base = (void __iomem *)CKSEG1ADDR(MALTA_RESET_BASE);
-	__raw_writel(GORESET, reset_base);
-}
-
-void pci_init_board(void)
-{
-	set_io_port_base(CKSEG1ADDR(MALTA_IO_PORT_BASE));
-
-	gt64120_pci_init((void *)CKSEG1ADDR(MALTA_GT_BASE),
-			 0x00000000, 0x00000000, CONFIG_SYS_MEM_SIZE,
-			 0x10000000, 0x10000000, 128 * 1024 * 1024,
-			 0x00000000, 0x00000000, 0x20000);
-}
diff --git a/board/qemu-mips/Makefile b/board/qemu-mips/Makefile
index 70603414f4..8040573ff9 100644
--- a/board/qemu-mips/Makefile
+++ b/board/qemu-mips/Makefile
@@ -5,25 +5,5 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	= $(BOARD).o
-SOBJS	= lowlevel_init.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	 $(OBJS) $(SOBJS)
-	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	= qemu-mips.o
+obj-y	+= lowlevel_init.o
diff --git a/board/quad100hd/Makefile b/board/quad100hd/Makefile
index 9b936d06a8..b65e5ad471 100644
--- a/board/quad100hd/Makefile
+++ b/board/quad100hd/Makefile
@@ -5,25 +5,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	= $(BOARD).o nand.o
-SOBJS   =
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(OBJS) $(SOBJS)
-	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	= quad100hd.o nand.o
diff --git a/board/quantum/Makefile b/board/quantum/Makefile
index b7497a0d7c..6918f63c3e 100644
--- a/board/quantum/Makefile
+++ b/board/quantum/Makefile
@@ -5,24 +5,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	= $(BOARD).o fpga.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	= quantum.o fpga.o
diff --git a/board/r360mpi/Makefile b/board/r360mpi/Makefile
index 4720ac8132..f8f7fe75ea 100644
--- a/board/r360mpi/Makefile
+++ b/board/r360mpi/Makefile
@@ -5,24 +5,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	= $(BOARD).o flash.o pcmcia.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	= r360mpi.o flash.o pcmcia.o
diff --git a/board/raidsonic/ib62x0/Makefile b/board/raidsonic/ib62x0/Makefile
index 9d24ad0061..c3b4e69239 100644
--- a/board/raidsonic/ib62x0/Makefile
+++ b/board/raidsonic/ib62x0/Makefile
@@ -6,24 +6,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	:= ib62x0.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
-	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	:= ib62x0.o
diff --git a/board/raspberrypi/rpi_b/Makefile b/board/raspberrypi/rpi_b/Makefile
index 9d0c377c1b..7e9bfbff0c 100644
--- a/board/raspberrypi/rpi_b/Makefile
+++ b/board/raspberrypi/rpi_b/Makefile
@@ -12,23 +12,4 @@
 # GNU General Public License for more details.
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	:= $(BOARD).o
-
-SRCS	:= $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	:= rpi_b.o
diff --git a/board/raspberrypi/rpi_b/rpi_b.c b/board/raspberrypi/rpi_b/rpi_b.c
index 16d442aa62..f33fae9170 100644
--- a/board/raspberrypi/rpi_b/rpi_b.c
+++ b/board/raspberrypi/rpi_b/rpi_b.c
@@ -29,6 +29,12 @@ struct msg_get_arm_mem {
 	u32 end_tag;
 };
 
+struct msg_set_power_state {
+	struct bcm2835_mbox_hdr hdr;
+	struct bcm2835_mbox_tag_set_power_state set_power_state;
+	u32 end_tag;
+};
+
 struct msg_get_clock_rate {
 	struct bcm2835_mbox_hdr hdr;
 	struct bcm2835_mbox_tag_get_clock_rate get_clock_rate;
@@ -54,11 +60,35 @@ int dram_init(void)
 	return 0;
 }
 
+static int power_on_module(u32 module)
+{
+	ALLOC_ALIGN_BUFFER(struct msg_set_power_state, msg_pwr, 1, 16);
+	int ret;
+
+	BCM2835_MBOX_INIT_HDR(msg_pwr);
+	BCM2835_MBOX_INIT_TAG(&msg_pwr->set_power_state,
+			      SET_POWER_STATE);
+	msg_pwr->set_power_state.body.req.device_id = module;
+	msg_pwr->set_power_state.body.req.state =
+		BCM2835_MBOX_SET_POWER_STATE_REQ_ON |
+		BCM2835_MBOX_SET_POWER_STATE_REQ_WAIT;
+
+	ret = bcm2835_mbox_call_prop(BCM2835_MBOX_PROP_CHAN,
+				     &msg_pwr->hdr);
+	if (ret) {
+		printf("bcm2835: Could not set module %u power state\n",
+		       module);
+		return -1;
+	}
+
+	return 0;
+}
+
 int board_init(void)
 {
 	gd->bd->bi_boot_params = 0x100;
 
-	return 0;
+	return power_on_module(BCM2835_MBOX_POWER_DEVID_USB_HCD);
 }
 
 int board_mmc_init(void)
@@ -66,6 +96,8 @@ int board_mmc_init(void)
 	ALLOC_ALIGN_BUFFER(struct msg_get_clock_rate, msg_clk, 1, 16);
 	int ret;
 
+	power_on_module(BCM2835_MBOX_POWER_DEVID_SDHCI);
+
 	BCM2835_MBOX_INIT_HDR(msg_clk);
 	BCM2835_MBOX_INIT_TAG(&msg_clk->get_clock_rate, GET_CLOCK_RATE);
 	msg_clk->get_clock_rate.body.req.clock_id = BCM2835_MBOX_CLOCK_ID_EMMC;
diff --git a/board/rattler/Makefile b/board/rattler/Makefile
index c573be952c..9de89c8096 100644
--- a/board/rattler/Makefile
+++ b/board/rattler/Makefile
@@ -5,24 +5,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	:= $(BOARD).o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	:= rattler.o
diff --git a/board/rbc823/Makefile b/board/rbc823/Makefile
index 6e47cb5a26..060a144a92 100644
--- a/board/rbc823/Makefile
+++ b/board/rbc823/Makefile
@@ -5,24 +5,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	= $(BOARD).o flash.o kbd.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	= rbc823.o flash.o kbd.o
diff --git a/board/rbc823/u-boot.lds b/board/rbc823/u-boot.lds
index 191f9eb837..7676cf43b1 100644
--- a/board/rbc823/u-boot.lds
+++ b/board/rbc823/u-boot.lds
@@ -19,10 +19,10 @@ SECTIONS
     arch/powerpc/cpu/mpc8xx/start.o	(.text*)
     arch/powerpc/cpu/mpc8xx/traps.o	(.text*)
 
-    lib/libgeneric.o			(.text*)
-    net/libnet.o			(.text*)
-    arch/powerpc/cpu/mpc8xx/libmpc8xx.o	(.text*)
-    arch/powerpc/lib/libpowerpc.o	(.text*)
+    lib/built-in.o			(.text*)
+    net/built-in.o			(.text*)
+    arch/powerpc/cpu/mpc8xx/built-in.o	(.text*)
+    arch/powerpc/lib/built-in.o		(.text*)
 
     . = env_offset;
     common/env_embedded.o		(.text*)
diff --git a/board/renesas/MigoR/Makefile b/board/renesas/MigoR/Makefile
index 7725c449cd..b4691a1165 100644
--- a/board/renesas/MigoR/Makefile
+++ b/board/renesas/MigoR/Makefile
@@ -9,25 +9,5 @@
 #
 # SPDX-License-Identifier:	GPL-2.0+
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	:= migo_r.o
-SOBJS	:= lowlevel_init.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(OBJS) $(SOBJS)
-	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	:= migo_r.o
+obj-y	+= lowlevel_init.o
diff --git a/board/renesas/ap325rxa/Makefile b/board/renesas/ap325rxa/Makefile
index 0597d0fc5e..ff72de902c 100644
--- a/board/renesas/ap325rxa/Makefile
+++ b/board/renesas/ap325rxa/Makefile
@@ -8,25 +8,5 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	:= ap325rxa.o cpld-ap325rxa.o
-SOBJS	:= lowlevel_init.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(OBJS) $(SOBJS)
-	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	:= ap325rxa.o cpld-ap325rxa.o
+obj-y	+= lowlevel_init.o
diff --git a/board/renesas/ecovec/Makefile b/board/renesas/ecovec/Makefile
index f2a02f81b5..943fa4760d 100644
--- a/board/renesas/ecovec/Makefile
+++ b/board/renesas/ecovec/Makefile
@@ -4,26 +4,5 @@
 #
 # SPDX-License-Identifier:	GPL-2.0+
 
-
-include $(TOPDIR)/config.mk
-
-LIB = $(obj)lib$(BOARD).o
-
-COBJS   := ecovec.o
-SOBJS   := lowlevel_init.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB): $(OBJS) $(SOBJS)
-		$(call cmd_link_o_target, $(OBJS) $(SOBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y := ecovec.o
+obj-y += lowlevel_init.o
diff --git a/board/renesas/ecovec/ecovec.c b/board/renesas/ecovec/ecovec.c
index e2d365a187..2804d9133d 100644
--- a/board/renesas/ecovec/ecovec.c
+++ b/board/renesas/ecovec/ecovec.c
@@ -57,8 +57,7 @@ int board_late_init(void)
 
 	outl(inl(MSTPCR2) & ~0x10000000, MSTPCR2);
 
-	i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
-	i2c_set_bus_num(CONFIG_SYS_I2C_MODULE); /* Use I2C 1 */
+	i2c_set_bus_num(1); /* Use I2C 1 */
 
 	/* Read MAC address */
 	i2c_read(0x50, 0x10, 0, mac, 6);
@@ -77,7 +76,7 @@ int board_init(void)
 {
 
 	/* LED (PTG) */
-	outw((inw(PGCR) & ~0xFF) | 0x66, PGCR);
+	outw((inw(PGCR) & ~0xFF) | 0x55, PGCR);
 	outw((inw(HIZCRA) & ~0x02), HIZCRA);
 
 	debug_led(1 << 0);
@@ -98,7 +97,7 @@ int board_init(void)
 	/* USB host */
 	outw((inw(PBCR) & ~0x300) | 0x100, PBCR);
 	outb((inb(PBDR) & ~0x10) | 0x10, PBDR);
-	outl(inl(MSTPCR2) & 0x100000, MSTPCR2);
+	outl(inl(MSTPCR2) & ~0x100000, MSTPCR2);
 	outw(0x0600, UPONCR0);
 
 	debug_led(1 << 3);
diff --git a/board/renesas/ecovec/lowlevel_init.S b/board/renesas/ecovec/lowlevel_init.S
index eeebdd245f..e4c40c8616 100644
--- a/board/renesas/ecovec/lowlevel_init.S
+++ b/board/renesas/ecovec/lowlevel_init.S
@@ -20,7 +20,7 @@
 
 lowlevel_init:
 
-	/* jump to 0xA0020000 if bit 1 of PVDR_A */
+	/* jump to CONFIG_ECOVEC_ROMIMAGE_ADDR if bit 1 of PVDR_A */
 	mov.l	PVDR_A, r1
 	mov.l	PVDR_D, r2
 	mov.b	@r1, r0
diff --git a/board/renesas/koelsch/Makefile b/board/renesas/koelsch/Makefile
new file mode 100644
index 0000000000..b4d0183b3b
--- /dev/null
+++ b/board/renesas/koelsch/Makefile
@@ -0,0 +1,9 @@
+#
+# board/renesas/koelsch/Makefile
+#
+# Copyright (C) 2013 Renesas Electronics Corporation
+#
+# SPDX-License-Identifier: GPL-2.0
+#
+
+obj-y	:= koelsch.o qos.o
diff --git a/board/renesas/koelsch/koelsch.c b/board/renesas/koelsch/koelsch.c
new file mode 100644
index 0000000000..32d3b584bc
--- /dev/null
+++ b/board/renesas/koelsch/koelsch.c
@@ -0,0 +1,372 @@
+/*
+ * board/renesas/koelsch/koelsch.c
+ *
+ * Copyright (C) 2013 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ *
+ */
+
+#include <common.h>
+#include <malloc.h>
+#include <asm/processor.h>
+#include <asm/mach-types.h>
+#include <asm/io.h>
+#include <asm/errno.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/gpio.h>
+#include <asm/arch/rmobile.h>
+#include <netdev.h>
+#include <miiphy.h>
+#include <i2c.h>
+#include "qos.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define s_init_wait(cnt) \
+	({	\
+		u32 i = 0x10000 * cnt;	\
+		while (i > 0)	\
+			i--;	\
+	})
+
+
+#define dbpdrgd_check(bsc) \
+	({	\
+		while ((readl(&bsc->dbpdrgd) & 0x1) != 0x1)	\
+			;	\
+	})
+
+#if defined(CONFIG_NORFLASH)
+static void bsc_init(void)
+{
+	struct r8a7791_lbsc *lbsc = (struct r8a7791_lbsc *)LBSC_BASE;
+	struct r8a7791_dbsc3 *dbsc3_0 = (struct r8a7791_dbsc3 *)DBSC3_0_BASE;
+
+	/* LBSC */
+	writel(0x00000020, &lbsc->cs0ctrl);
+	writel(0x00000020, &lbsc->cs1ctrl);
+	writel(0x00002020, &lbsc->ecs0ctrl);
+	writel(0x00002020, &lbsc->ecs1ctrl);
+
+	writel(0x077F077F, &lbsc->cswcr0);
+	writel(0x077F077F, &lbsc->cswcr1);
+	writel(0x077F077F, &lbsc->ecswcr0);
+	writel(0x077F077F, &lbsc->ecswcr1);
+
+	/* DBSC3 */
+	s_init_wait(10);
+
+	writel(0x0000A55A, &dbsc3_0->dbpdlck);
+	writel(0x00000001, &dbsc3_0->dbpdrga);
+	writel(0x80000000, &dbsc3_0->dbpdrgd);
+	writel(0x00000004, &dbsc3_0->dbpdrga);
+	dbpdrgd_check(dbsc3_0);
+
+	writel(0x00000006, &dbsc3_0->dbpdrga);
+	writel(0x0001C000, &dbsc3_0->dbpdrgd);
+
+	writel(0x00000023, &dbsc3_0->dbpdrga);
+	writel(0x00FD2480, &dbsc3_0->dbpdrgd);
+
+	writel(0x00000010, &dbsc3_0->dbpdrga);
+	writel(0xF004649B, &dbsc3_0->dbpdrgd);
+
+	writel(0x0000000F, &dbsc3_0->dbpdrga);
+	writel(0x00181EE4, &dbsc3_0->dbpdrgd);
+
+	writel(0x0000000E, &dbsc3_0->dbpdrga);
+	writel(0x33C03812, &dbsc3_0->dbpdrgd);
+
+	writel(0x00000003, &dbsc3_0->dbpdrga);
+	writel(0x0300C481, &dbsc3_0->dbpdrgd);
+
+	writel(0x00000007, &dbsc3_0->dbkind);
+	writel(0x10030A02, &dbsc3_0->dbconf0);
+	writel(0x00000001, &dbsc3_0->dbphytype);
+	writel(0x00000000, &dbsc3_0->dbbl);
+	writel(0x0000000B, &dbsc3_0->dbtr0);
+	writel(0x00000008, &dbsc3_0->dbtr1);
+	writel(0x00000000, &dbsc3_0->dbtr2);
+	writel(0x0000000B, &dbsc3_0->dbtr3);
+	writel(0x000C000B, &dbsc3_0->dbtr4);
+	writel(0x00000027, &dbsc3_0->dbtr5);
+	writel(0x0000001C, &dbsc3_0->dbtr6);
+	writel(0x00000005, &dbsc3_0->dbtr7);
+	writel(0x00000018, &dbsc3_0->dbtr8);
+	writel(0x00000008, &dbsc3_0->dbtr9);
+	writel(0x0000000C, &dbsc3_0->dbtr10);
+	writel(0x00000009, &dbsc3_0->dbtr11);
+	writel(0x00000012, &dbsc3_0->dbtr12);
+	writel(0x000000D0, &dbsc3_0->dbtr13);
+	writel(0x00140005, &dbsc3_0->dbtr14);
+	writel(0x00050004, &dbsc3_0->dbtr15);
+	writel(0x70233005, &dbsc3_0->dbtr16);
+	writel(0x000C0000, &dbsc3_0->dbtr17);
+	writel(0x00000300, &dbsc3_0->dbtr18);
+	writel(0x00000040, &dbsc3_0->dbtr19);
+	writel(0x00000001, &dbsc3_0->dbrnk0);
+	writel(0x00020001, &dbsc3_0->dbadj0);
+	writel(0x20082008, &dbsc3_0->dbadj2);
+	writel(0x00020002, &dbsc3_0->dbwt0cnf0);
+	writel(0x0000000F, &dbsc3_0->dbwt0cnf4);
+
+	writel(0x00000015, &dbsc3_0->dbpdrga);
+	writel(0x00000D70, &dbsc3_0->dbpdrgd);
+
+	writel(0x00000016, &dbsc3_0->dbpdrga);
+	writel(0x00000006, &dbsc3_0->dbpdrgd);
+
+	writel(0x00000017, &dbsc3_0->dbpdrga);
+	writel(0x00000018, &dbsc3_0->dbpdrgd);
+
+	writel(0x00000012, &dbsc3_0->dbpdrga);
+	writel(0x9D5CBB66, &dbsc3_0->dbpdrgd);
+
+	writel(0x00000013, &dbsc3_0->dbpdrga);
+	writel(0x1A868300, &dbsc3_0->dbpdrgd);
+
+	writel(0x00000023, &dbsc3_0->dbpdrga);
+	writel(0x00FDB6C0, &dbsc3_0->dbpdrgd);
+
+	writel(0x00000014, &dbsc3_0->dbpdrga);
+	writel(0x300214D8, &dbsc3_0->dbpdrgd);
+
+	writel(0x0000001A, &dbsc3_0->dbpdrga);
+	writel(0x930035C7, &dbsc3_0->dbpdrgd);
+
+	writel(0x00000060, &dbsc3_0->dbpdrga);
+	writel(0x330657B2, &dbsc3_0->dbpdrgd);
+
+	writel(0x00000011, &dbsc3_0->dbpdrga);
+	writel(0x1000040B, &dbsc3_0->dbpdrgd);
+
+	writel(0x0000FA00, &dbsc3_0->dbcmd);
+	writel(0x00000001, &dbsc3_0->dbpdrga);
+	writel(0x00000071, &dbsc3_0->dbpdrgd);
+
+	writel(0x00000004, &dbsc3_0->dbpdrga);
+	dbpdrgd_check(dbsc3_0);
+
+	writel(0x0000FA00, &dbsc3_0->dbcmd);
+	writel(0x2100FA00, &dbsc3_0->dbcmd);
+	writel(0x0000FA00, &dbsc3_0->dbcmd);
+	writel(0x0000FA00, &dbsc3_0->dbcmd);
+	writel(0x0000FA00, &dbsc3_0->dbcmd);
+	writel(0x0000FA00, &dbsc3_0->dbcmd);
+	writel(0x0000FA00, &dbsc3_0->dbcmd);
+	writel(0x0000FA00, &dbsc3_0->dbcmd);
+	writel(0x0000FA00, &dbsc3_0->dbcmd);
+
+	writel(0x110000DB, &dbsc3_0->dbcmd);
+
+	writel(0x00000001, &dbsc3_0->dbpdrga);
+	writel(0x00000181, &dbsc3_0->dbpdrgd);
+
+	writel(0x00000004, &dbsc3_0->dbpdrga);
+	dbpdrgd_check(dbsc3_0);
+
+	writel(0x00000001, &dbsc3_0->dbpdrga);
+	writel(0x0000FE01, &dbsc3_0->dbpdrgd);
+
+	writel(0x00000004, &dbsc3_0->dbpdrga);
+	dbpdrgd_check(dbsc3_0);
+
+	writel(0x00000000, &dbsc3_0->dbbs0cnt1);
+	writel(0x01004C20, &dbsc3_0->dbcalcnf);
+	writel(0x014000AA, &dbsc3_0->dbcaltr);
+	writel(0x00000140, &dbsc3_0->dbrfcnf0);
+	writel(0x00081860, &dbsc3_0->dbrfcnf1);
+	writel(0x00010000, &dbsc3_0->dbrfcnf2);
+	writel(0x00000001, &dbsc3_0->dbrfen);
+	writel(0x00000001, &dbsc3_0->dbacen);
+}
+#else
+#define bsc_init() do {} while (0)
+#endif /* CONFIG_NORFLASH */
+
+void s_init(void)
+{
+	struct r8a7791_rwdt *rwdt = (struct r8a7791_rwdt *)RWDT_BASE;
+	struct r8a7791_swdt *swdt = (struct r8a7791_swdt *)SWDT_BASE;
+
+	/* Watchdog init */
+	writel(0xA5A5A500, &rwdt->rwtcsra);
+	writel(0xA5A5A500, &swdt->swtcsra);
+
+	/* QoS */
+	qos_init();
+
+	/* BSC */
+	bsc_init();
+}
+
+#define MSTPSR1		0xE6150038
+#define SMSTPCR1	0xE6150134
+#define TMU0_MSTP125	(1 << 25)
+
+#define MSTPSR7		0xE61501C4
+#define SMSTPCR7	0xE615014C
+#define SCIF0_MSTP721	(1 << 21)
+
+#define MSTPSR8		0xE61509A0
+#define SMSTPCR8	0xE6150990
+#define ETHER_MSTP813	(1 << 13)
+
+#define PMMR	0xE6060000
+#define GPSR4	0xE6060014
+#define IPSR14	0xE6060058
+
+#define set_guard_reg(addr, mask, value)	\
+{ \
+	u32 val; \
+	val = (readl(addr) & ~(mask)) | (value); \
+	writel(~val, PMMR); \
+	writel(val, addr); \
+}
+
+#define mstp_setbits(type, addr, saddr, set) \
+	out_##type((saddr), in_##type(addr) | (set))
+#define mstp_clrbits(type, addr, saddr, clear) \
+	out_##type((saddr), in_##type(addr) & ~(clear))
+#define mstp_setbits_le32(addr, saddr, set) \
+	mstp_setbits(le32, addr, saddr, set)
+#define mstp_clrbits_le32(addr, saddr, clear)   \
+	mstp_clrbits(le32, addr, saddr, clear)
+
+int board_early_init_f(void)
+{
+	mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125);
+
+#if defined(CONFIG_NORFLASH)
+	/* SCIF0 */
+	set_guard_reg(GPSR4, 0x34000000, 0x00000000);
+	set_guard_reg(IPSR14, 0x00000FC7, 0x00000481);
+	set_guard_reg(GPSR4, 0x00000000, 0x34000000);
+#endif
+
+	mstp_clrbits_le32(MSTPSR7, SMSTPCR7, SCIF0_MSTP721);
+
+	/* ETHER */
+	mstp_clrbits_le32(MSTPSR8, SMSTPCR8, ETHER_MSTP813);
+
+	return 0;
+}
+
+void arch_preboot_os(void)
+{
+	/* Disable TMU0 */
+	mstp_setbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125);
+}
+
+/* LSI pin pull-up control */
+#define PUPR5 0xe6060114
+#define PUPR5_ETH 0x3FFC0000
+#define PUPR5_ETH_MAGIC	(1 << 27)
+int board_init(void)
+{
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = KOELSCH_SDRAM_BASE + 0x100;
+
+	/* Init PFC controller */
+	r8a7791_pinmux_init();
+
+	/* ETHER Enable */
+	gpio_request(GPIO_FN_ETH_CRS_DV, NULL);
+	gpio_request(GPIO_FN_ETH_RX_ER, NULL);
+	gpio_request(GPIO_FN_ETH_RXD0, NULL);
+	gpio_request(GPIO_FN_ETH_RXD1, NULL);
+	gpio_request(GPIO_FN_ETH_LINK, NULL);
+	gpio_request(GPIO_FN_ETH_REFCLK, NULL);
+	gpio_request(GPIO_FN_ETH_MDIO, NULL);
+	gpio_request(GPIO_FN_ETH_TXD1, NULL);
+	gpio_request(GPIO_FN_ETH_TX_EN, NULL);
+	gpio_request(GPIO_FN_ETH_TXD0, NULL);
+	gpio_request(GPIO_FN_ETH_MDC, NULL);
+	gpio_request(GPIO_FN_IRQ0, NULL);
+
+	mstp_clrbits_le32(PUPR5, PUPR5, PUPR5_ETH & ~PUPR5_ETH_MAGIC);
+	gpio_request(GPIO_GP_5_22, NULL); /* PHY_RST */
+	mstp_clrbits_le32(PUPR5, PUPR5, PUPR5_ETH_MAGIC);
+
+	gpio_direction_output(GPIO_GP_5_22, 0);
+	mdelay(20);
+	gpio_set_value(GPIO_GP_5_22, 1);
+	udelay(1);
+
+	return 0;
+}
+
+#define CXR24 0xEE7003C0 /* MAC address high register */
+#define CXR25 0xEE7003C8 /* MAC address low register */
+int board_eth_init(bd_t *bis)
+{
+#ifdef CONFIG_SH_ETHER
+	int ret = -ENODEV;
+	u32 val;
+	unsigned char enetaddr[6];
+
+	ret = sh_eth_initialize(bis);
+	if (!eth_getenv_enetaddr("ethaddr", enetaddr))
+		return ret;
+
+	/* Set Mac address */
+	val = enetaddr[0] << 24 | enetaddr[1] << 16 |
+		enetaddr[2] << 8 | enetaddr[3];
+	writel(val, CXR24);
+
+	val = enetaddr[4] << 8 | enetaddr[5];
+	writel(val, CXR25);
+
+	return ret;
+#else
+	return 0;
+#endif
+}
+
+int dram_init(void)
+{
+	gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
+	gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
+
+	return 0;
+}
+
+/* koelsch has KSZ8041NL/RNL */
+#define PHY_CONTROL1	0x1E
+#define PHY_LED_MODE	0xC0000
+#define PHY_LED_MODE_ACK	0x4000
+int board_phy_config(struct phy_device *phydev)
+{
+	int ret = phy_read(phydev, MDIO_DEVAD_NONE, PHY_CONTROL1);
+	ret &= ~PHY_LED_MODE;
+	ret |= PHY_LED_MODE_ACK;
+	ret = phy_write(phydev, MDIO_DEVAD_NONE, PHY_CONTROL1, (u16)ret);
+
+	return 0;
+}
+
+const struct rmobile_sysinfo sysinfo = {
+	CONFIG_RMOBILE_BOARD_STRING
+};
+
+void dram_init_banksize(void)
+{
+	gd->bd->bi_dram[0].start = KOELSCH_SDRAM_BASE;
+	gd->bd->bi_dram[0].size = KOELSCH_SDRAM_SIZE;
+}
+
+int board_late_init(void)
+{
+	return 0;
+}
+
+void reset_cpu(ulong addr)
+{
+	u8 val;
+
+	i2c_set_bus_num(2); /* PowerIC connected to ch2 */
+	i2c_read(CONFIG_SYS_I2C_POWERIC_ADDR, 0x13, 1, &val, 1);
+	val |= 0x02;
+	i2c_write(CONFIG_SYS_I2C_POWERIC_ADDR, 0x13, 1, &val, 1);
+}
diff --git a/board/renesas/koelsch/qos.c b/board/renesas/koelsch/qos.c
new file mode 100644
index 0000000000..7f88f7da8d
--- /dev/null
+++ b/board/renesas/koelsch/qos.c
@@ -0,0 +1,1220 @@
+/*
+ * board/renesas/koelsch/qos.c
+ *
+ * Copyright (C) 2013 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ *
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+#include <asm/mach-types.h>
+#include <asm/io.h>
+#include <asm/arch/rmobile.h>
+
+/* QoS version 0.23 */
+
+enum {
+	DBSC3_00, DBSC3_01, DBSC3_02, DBSC3_03, DBSC3_04,
+	DBSC3_05, DBSC3_06, DBSC3_07, DBSC3_08, DBSC3_09,
+	DBSC3_10, DBSC3_11, DBSC3_12, DBSC3_13, DBSC3_14,
+	DBSC3_15,
+	DBSC3_NR,
+};
+
+static u32 dbsc3_0_r_qos_addr[DBSC3_NR] = {
+	[DBSC3_00] = DBSC3_0_QOS_R0_BASE,
+	[DBSC3_01] = DBSC3_0_QOS_R1_BASE,
+	[DBSC3_02] = DBSC3_0_QOS_R2_BASE,
+	[DBSC3_03] = DBSC3_0_QOS_R3_BASE,
+	[DBSC3_04] = DBSC3_0_QOS_R4_BASE,
+	[DBSC3_05] = DBSC3_0_QOS_R5_BASE,
+	[DBSC3_06] = DBSC3_0_QOS_R6_BASE,
+	[DBSC3_07] = DBSC3_0_QOS_R7_BASE,
+	[DBSC3_08] = DBSC3_0_QOS_R8_BASE,
+	[DBSC3_09] = DBSC3_0_QOS_R9_BASE,
+	[DBSC3_10] = DBSC3_0_QOS_R10_BASE,
+	[DBSC3_11] = DBSC3_0_QOS_R11_BASE,
+	[DBSC3_12] = DBSC3_0_QOS_R12_BASE,
+	[DBSC3_13] = DBSC3_0_QOS_R13_BASE,
+	[DBSC3_14] = DBSC3_0_QOS_R14_BASE,
+	[DBSC3_15] = DBSC3_0_QOS_R15_BASE,
+};
+
+static u32 dbsc3_0_w_qos_addr[DBSC3_NR] = {
+	[DBSC3_00] = DBSC3_0_QOS_W0_BASE,
+	[DBSC3_01] = DBSC3_0_QOS_W1_BASE,
+	[DBSC3_02] = DBSC3_0_QOS_W2_BASE,
+	[DBSC3_03] = DBSC3_0_QOS_W3_BASE,
+	[DBSC3_04] = DBSC3_0_QOS_W4_BASE,
+	[DBSC3_05] = DBSC3_0_QOS_W5_BASE,
+	[DBSC3_06] = DBSC3_0_QOS_W6_BASE,
+	[DBSC3_07] = DBSC3_0_QOS_W7_BASE,
+	[DBSC3_08] = DBSC3_0_QOS_W8_BASE,
+	[DBSC3_09] = DBSC3_0_QOS_W9_BASE,
+	[DBSC3_10] = DBSC3_0_QOS_W10_BASE,
+	[DBSC3_11] = DBSC3_0_QOS_W11_BASE,
+	[DBSC3_12] = DBSC3_0_QOS_W12_BASE,
+	[DBSC3_13] = DBSC3_0_QOS_W13_BASE,
+	[DBSC3_14] = DBSC3_0_QOS_W14_BASE,
+	[DBSC3_15] = DBSC3_0_QOS_W15_BASE,
+};
+
+static u32 dbsc3_1_r_qos_addr[DBSC3_NR] = {
+	[DBSC3_00] = DBSC3_1_QOS_R0_BASE,
+	[DBSC3_01] = DBSC3_1_QOS_R1_BASE,
+	[DBSC3_02] = DBSC3_1_QOS_R2_BASE,
+	[DBSC3_03] = DBSC3_1_QOS_R3_BASE,
+	[DBSC3_04] = DBSC3_1_QOS_R4_BASE,
+	[DBSC3_05] = DBSC3_1_QOS_R5_BASE,
+	[DBSC3_06] = DBSC3_1_QOS_R6_BASE,
+	[DBSC3_07] = DBSC3_1_QOS_R7_BASE,
+	[DBSC3_08] = DBSC3_1_QOS_R8_BASE,
+	[DBSC3_09] = DBSC3_1_QOS_R9_BASE,
+	[DBSC3_10] = DBSC3_1_QOS_R10_BASE,
+	[DBSC3_11] = DBSC3_1_QOS_R11_BASE,
+	[DBSC3_12] = DBSC3_1_QOS_R12_BASE,
+	[DBSC3_13] = DBSC3_1_QOS_R13_BASE,
+	[DBSC3_14] = DBSC3_1_QOS_R14_BASE,
+	[DBSC3_15] = DBSC3_1_QOS_R15_BASE,
+};
+
+static u32 dbsc3_1_w_qos_addr[DBSC3_NR] = {
+	[DBSC3_00] = DBSC3_1_QOS_W0_BASE,
+	[DBSC3_01] = DBSC3_1_QOS_W1_BASE,
+	[DBSC3_02] = DBSC3_1_QOS_W2_BASE,
+	[DBSC3_03] = DBSC3_1_QOS_W3_BASE,
+	[DBSC3_04] = DBSC3_1_QOS_W4_BASE,
+	[DBSC3_05] = DBSC3_1_QOS_W5_BASE,
+	[DBSC3_06] = DBSC3_1_QOS_W6_BASE,
+	[DBSC3_07] = DBSC3_1_QOS_W7_BASE,
+	[DBSC3_08] = DBSC3_1_QOS_W8_BASE,
+	[DBSC3_09] = DBSC3_1_QOS_W9_BASE,
+	[DBSC3_10] = DBSC3_1_QOS_W10_BASE,
+	[DBSC3_11] = DBSC3_1_QOS_W11_BASE,
+	[DBSC3_12] = DBSC3_1_QOS_W12_BASE,
+	[DBSC3_13] = DBSC3_1_QOS_W13_BASE,
+	[DBSC3_14] = DBSC3_1_QOS_W14_BASE,
+	[DBSC3_15] = DBSC3_1_QOS_W15_BASE,
+};
+
+void qos_init(void)
+{
+	int i;
+	struct r8a7791_s3c *s3c;
+	struct r8a7791_s3c_qos *s3c_qos;
+	struct r8a7791_dbsc3_qos *qos_addr;
+	struct r8a7791_mxi *mxi;
+	struct r8a7791_mxi_qos *mxi_qos;
+	struct r8a7791_axi_qos *axi_qos;
+
+	/* DBSC DBADJ2 */
+	writel(0x20042004, DBSC3_0_DBADJ2);
+
+	/* S3C -QoS */
+	s3c = (struct r8a7791_s3c *)S3C_BASE;
+	writel(0x00FF1B1D, &s3c->s3cadsplcr);
+	writel(0x1F0D0C0C, &s3c->s3crorr);
+	writel(0x1F0D0C0A, &s3c->s3cworr);
+
+	/* QoS Control Registers */
+	s3c_qos = (struct r8a7791_s3c_qos *)S3C_QOS_CCI0_BASE;
+	writel(0x00890089, &s3c_qos->s3cqos0);
+	writel(0x20960010, &s3c_qos->s3cqos1);
+	writel(0x20302030, &s3c_qos->s3cqos2);
+	writel(0x20AA2200, &s3c_qos->s3cqos3);
+	writel(0x00002032, &s3c_qos->s3cqos4);
+	writel(0x20960010, &s3c_qos->s3cqos5);
+	writel(0x20302030, &s3c_qos->s3cqos6);
+	writel(0x20AA2200, &s3c_qos->s3cqos7);
+	writel(0x00002032, &s3c_qos->s3cqos8);
+
+	s3c_qos = (struct r8a7791_s3c_qos *)S3C_QOS_CCI1_BASE;
+	writel(0x00890089, &s3c_qos->s3cqos0);
+	writel(0x20960010, &s3c_qos->s3cqos1);
+	writel(0x20302030, &s3c_qos->s3cqos2);
+	writel(0x20AA2200, &s3c_qos->s3cqos3);
+	writel(0x00002032, &s3c_qos->s3cqos4);
+	writel(0x20960010, &s3c_qos->s3cqos5);
+	writel(0x20302030, &s3c_qos->s3cqos6);
+	writel(0x20AA2200, &s3c_qos->s3cqos7);
+	writel(0x00002032, &s3c_qos->s3cqos8);
+
+	s3c_qos = (struct r8a7791_s3c_qos *)S3C_QOS_MXI_BASE;
+	writel(0x00820082, &s3c_qos->s3cqos0);
+	writel(0x20960020, &s3c_qos->s3cqos1);
+	writel(0x20302030, &s3c_qos->s3cqos2);
+	writel(0x20AA20DC, &s3c_qos->s3cqos3);
+	writel(0x00002032, &s3c_qos->s3cqos4);
+	writel(0x20960020, &s3c_qos->s3cqos5);
+	writel(0x20302030, &s3c_qos->s3cqos6);
+	writel(0x20AA20DC, &s3c_qos->s3cqos7);
+	writel(0x00002032, &s3c_qos->s3cqos8);
+
+	s3c_qos = (struct r8a7791_s3c_qos *)S3C_QOS_AXI_BASE;
+	writel(0x00820082, &s3c_qos->s3cqos0);
+	writel(0x20960020, &s3c_qos->s3cqos1);
+	writel(0x20302030, &s3c_qos->s3cqos2);
+	writel(0x20AA20FA, &s3c_qos->s3cqos3);
+	writel(0x00002032, &s3c_qos->s3cqos4);
+	writel(0x20960020, &s3c_qos->s3cqos5);
+	writel(0x20302030, &s3c_qos->s3cqos6);
+	writel(0x20AA20FA, &s3c_qos->s3cqos7);
+	writel(0x00002032, &s3c_qos->s3cqos8);
+
+	/* DBSC -QoS */
+	/* DBSC0 - Read */
+	for (i = DBSC3_00; i < DBSC3_NR; i++) {
+		qos_addr = (struct r8a7791_dbsc3_qos *)dbsc3_0_r_qos_addr[i];
+		writel(0x00000002, &qos_addr->dblgcnt);
+		writel(0x00002096, &qos_addr->dbtmval0);
+		writel(0x00002064, &qos_addr->dbtmval1);
+		writel(0x00002032, &qos_addr->dbtmval2);
+		writel(0x00001FB0, &qos_addr->dbtmval3);
+		writel(0x00000001, &qos_addr->dbrqctr);
+		writel(0x00002078, &qos_addr->dbthres0);
+		writel(0x0000204B, &qos_addr->dbthres1);
+		writel(0x00001FE7, &qos_addr->dbthres2);
+		writel(0x00000001, &qos_addr->dblgqon);
+	}
+
+	/* DBSC0 - Write */
+	for (i = DBSC3_00; i < DBSC3_NR; i++) {
+		qos_addr = (struct r8a7791_dbsc3_qos *)dbsc3_0_w_qos_addr[i];
+		writel(0x00000002, &qos_addr->dblgcnt);
+		writel(0x000020EB, &qos_addr->dbtmval0);
+		writel(0x0000206E, &qos_addr->dbtmval1);
+		writel(0x00002050, &qos_addr->dbtmval2);
+		writel(0x0000203A, &qos_addr->dbtmval3);
+		writel(0x00000001, &qos_addr->dbrqctr);
+		writel(0x00002078, &qos_addr->dbthres0);
+		writel(0x0000205A, &qos_addr->dbthres1);
+		writel(0x0000203C, &qos_addr->dbthres2);
+		writel(0x00000001, &qos_addr->dblgqon);
+	}
+
+	/* DBSC1 - Read */
+	for (i = DBSC3_00; i < DBSC3_NR; i++) {
+		qos_addr = (struct r8a7791_dbsc3_qos *)dbsc3_1_r_qos_addr[i];
+		writel(0x00000002, &qos_addr->dblgcnt);
+		writel(0x00002096, &qos_addr->dbtmval0);
+		writel(0x00002064, &qos_addr->dbtmval1);
+		writel(0x00002032, &qos_addr->dbtmval2);
+		writel(0x00001FB0, &qos_addr->dbtmval3);
+		writel(0x00000001, &qos_addr->dbrqctr);
+		writel(0x00002078, &qos_addr->dbthres0);
+		writel(0x0000204B, &qos_addr->dbthres1);
+		writel(0x00001FE7, &qos_addr->dbthres2);
+		writel(0x00000001, &qos_addr->dblgqon);
+	}
+
+	/* DBSC1 - Write */
+	for (i = DBSC3_00; i < DBSC3_NR; i++) {
+		qos_addr = (struct r8a7791_dbsc3_qos *)dbsc3_1_w_qos_addr[i];
+		writel(0x00000002, &qos_addr->dblgcnt);
+		writel(0x000020EB, &qos_addr->dbtmval0);
+		writel(0x0000206E, &qos_addr->dbtmval1);
+		writel(0x00002050, &qos_addr->dbtmval2);
+		writel(0x0000203A, &qos_addr->dbtmval3);
+		writel(0x00000001, &qos_addr->dbrqctr);
+		writel(0x00002078, &qos_addr->dbthres0);
+		writel(0x0000205A, &qos_addr->dbthres1);
+		writel(0x0000203C, &qos_addr->dbthres2);
+		writel(0x00000001, &qos_addr->dblgqon);
+	}
+
+	/* CCI-400 -QoS */
+	writel(0x20001000, CCI_400_MAXOT_1);
+	writel(0x20001000, CCI_400_MAXOT_2);
+	writel(0x0000000C, CCI_400_QOSCNTL_1);
+	writel(0x0000000C, CCI_400_QOSCNTL_2);
+
+	/* MXI -QoS */
+	/* Transaction Control (MXI) */
+	mxi = (struct r8a7791_mxi *)MXI_BASE;
+	writel(0x00000013, &mxi->mxrtcr);
+	writel(0x00000013, &mxi->mxwtcr);
+	writel(0x00780080, &mxi->mxsaar0);
+	writel(0x02000800, &mxi->mxsaar1);
+
+	/* QoS Control (MXI) */
+	mxi_qos = (struct r8a7791_mxi_qos *)MXI_QOS_BASE;
+	writel(0x0000000C, &mxi_qos->vspdu0);
+	writel(0x0000000C, &mxi_qos->vspdu1);
+	writel(0x0000000D, &mxi_qos->du0);
+	writel(0x0000000D, &mxi_qos->du1);
+
+	/* AXI -QoS */
+	/* Transaction Control (MXI) */
+	axi_qos = (struct r8a7791_axi_qos *)SYS_AXI_SYX64TO128_BASE;
+	writel(0x00000002, &axi_qos->qosconf);
+	writel(0x00002245, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7791_axi_qos *)SYS_AXI_AVB_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x000020A6, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7791_axi_qos *)SYS_AXI_G2D_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x000020A6, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7791_axi_qos *)SYS_AXI_IMP0_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x00002021, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7791_axi_qos *)SYS_AXI_IMP1_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x00002037, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7791_axi_qos *)SYS_AXI_IMUX0_BASE;
+	writel(0x00000002, &axi_qos->qosconf);
+	writel(0x00002245, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7791_axi_qos *)SYS_AXI_IMUX1_BASE;
+	writel(0x00000002, &axi_qos->qosconf);
+	writel(0x00002245, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7791_axi_qos *)SYS_AXI_IMUX2_BASE;
+	writel(0x00000002, &axi_qos->qosconf);
+	writel(0x00002245, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7791_axi_qos *)SYS_AXI_LBS_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x0000214C, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7791_axi_qos *)SYS_AXI_MMUDS_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002004, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7791_axi_qos *)SYS_AXI_MMUM_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002004, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7791_axi_qos *)SYS_AXI_MMUR_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002004, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7791_axi_qos *)SYS_AXI_MMUS0_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002004, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7791_axi_qos *)SYS_AXI_MMUS1_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002004, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7791_axi_qos *)SYS_AXI_MTSB0_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x00002021, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7791_axi_qos *)SYS_AXI_MTSB1_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x00002021, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7791_axi_qos *)SYS_AXI_PCI_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x0000214C, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7791_axi_qos *)SYS_AXI_RTX_BASE;
+	writel(0x00000002, &axi_qos->qosconf);
+	writel(0x00002245, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7791_axi_qos *)SYS_AXI_SDS0_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x000020A6, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7791_axi_qos *)SYS_AXI_SDS1_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x000020A6, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7791_axi_qos *)SYS_AXI_USB20_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x00002053, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7791_axi_qos *)SYS_AXI_USB21_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x00002053, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7791_axi_qos *)SYS_AXI_USB22_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x00002053, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7791_axi_qos *)SYS_AXI_USB30_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x0000214C, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7791_axi_qos *)SYS_AXI_AX2M_BASE;
+	writel(0x00000002, &axi_qos->qosconf);
+	writel(0x00002245, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7791_axi_qos *)SYS_AXI_CC50_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x00002029, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7791_axi_qos *)SYS_AXI_CCI_BASE;
+	writel(0x00000002, &axi_qos->qosconf);
+	writel(0x00002245, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7791_axi_qos *)SYS_AXI_CS_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x00002053, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7791_axi_qos *)SYS_AXI_DDM_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x000020A6, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7791_axi_qos *)SYS_AXI_ETH_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x00002053, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7791_axi_qos *)SYS_AXI_MPXM_BASE;
+	writel(0x00000002, &axi_qos->qosconf);
+	writel(0x00002245, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7791_axi_qos *)SYS_AXI_SAT0_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x00002053, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7791_axi_qos *)SYS_AXI_SAT1_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x00002053, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7791_axi_qos *)SYS_AXI_SDM0_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x0000214C, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7791_axi_qos *)SYS_AXI_SDM1_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x0000214C, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7791_axi_qos *)SYS_AXI_TRAB_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x000020A6, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7791_axi_qos *)SYS_AXI_UDM0_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x00002053, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7791_axi_qos *)SYS_AXI_UDM1_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x00002053, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	/* QoS Register (RT-AXI) */
+	axi_qos = (struct r8a7791_axi_qos *)RT_AXI_SHX_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x00002053, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7791_axi_qos *)RT_AXI_DBG_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x00002053, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7791_axi_qos *)RT_AXI_RDM_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x00002299, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7791_axi_qos *)RT_AXI_RDS_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x00002029, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7791_axi_qos *)RT_AXI_RTX64TO128_BASE;
+	writel(0x00000002, &axi_qos->qosconf);
+	writel(0x00002245, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7791_axi_qos *)RT_AXI_STPRO_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x00002029, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7791_axi_qos *)RT_AXI_SY2RT_BASE;
+	writel(0x00000002, &axi_qos->qosconf);
+	writel(0x00002245, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	/* QoS Register (MP-AXI) */
+	axi_qos = (struct r8a7791_axi_qos *)MP_AXI_ADSP_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x00002037, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7791_axi_qos *)MP_AXI_ASDS0_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002014, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7791_axi_qos *)MP_AXI_ASDS1_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002014, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7791_axi_qos *)MP_AXI_MLP_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x00002014, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7791_axi_qos *)MP_AXI_MMUMP_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002004, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7791_axi_qos *)MP_AXI_SPU_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x00002053, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7791_axi_qos *)MP_AXI_SPUC_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x0000206E, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	/* QoS Register (SYS-AXI256) */
+	axi_qos = (struct r8a7791_axi_qos *)SYS_AXI256_AXI128TO256_BASE;
+	writel(0x00000002, &axi_qos->qosconf);
+	writel(0x00002245, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7791_axi_qos *)SYS_AXI256_SYX_BASE;
+	writel(0x00000002, &axi_qos->qosconf);
+	writel(0x00002245, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7791_axi_qos *)SYS_AXI256_MPX_BASE;
+	writel(0x00000002, &axi_qos->qosconf);
+	writel(0x00002245, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7791_axi_qos *)SYS_AXI256_MXI_BASE;
+	writel(0x00000002, &axi_qos->qosconf);
+	writel(0x00002245, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	/* QoS Register (CCI-AXI) */
+	axi_qos = (struct r8a7791_axi_qos *)CCI_AXI_MMUS0_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002004, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7791_axi_qos *)CCI_AXI_SYX2_BASE;
+	writel(0x00000002, &axi_qos->qosconf);
+	writel(0x00002245, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7791_axi_qos *)CCI_AXI_MMUR_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002004, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7791_axi_qos *)CCI_AXI_MMUDS_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002004, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7791_axi_qos *)CCI_AXI_MMUM_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002004, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7791_axi_qos *)CCI_AXI_MXI_BASE;
+	writel(0x00000002, &axi_qos->qosconf);
+	writel(0x00002245, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7791_axi_qos *)CCI_AXI_MMUS1_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002004, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7791_axi_qos *)CCI_AXI_MMUMP_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002004, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	/* QoS Register (Media-AXI) */
+	axi_qos = (struct r8a7791_axi_qos *)MEDIA_AXI_MXR_BASE;
+	writel(0x00000002, &axi_qos->qosconf);
+	writel(0x000020DC, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x000020AA, &axi_qos->qosthres0);
+	writel(0x00002032, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+
+	axi_qos = (struct r8a7791_axi_qos *)MEDIA_AXI_MXW_BASE;
+	writel(0x00000002, &axi_qos->qosconf);
+	writel(0x000020DC, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x000020AA, &axi_qos->qosthres0);
+	writel(0x00002032, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+
+	axi_qos = (struct r8a7791_axi_qos *)MEDIA_AXI_JPR_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002190, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7791_axi_qos *)MEDIA_AXI_JPW_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002190, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7791_axi_qos *)MEDIA_AXI_TDMR_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002190, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7791_axi_qos *)MEDIA_AXI_TDMW_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002190, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7791_axi_qos *)MEDIA_AXI_VSP1CR_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002190, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7791_axi_qos *)MEDIA_AXI_VSP1CW_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002190, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7791_axi_qos *)MEDIA_AXI_VSPDU0CR_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002190, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7791_axi_qos *)MEDIA_AXI_VSPDU0CW_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002190, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7791_axi_qos *)MEDIA_AXI_VSPDU1CR_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002190, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7791_axi_qos *)MEDIA_AXI_VSPDU1CW_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002190, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7791_axi_qos *)MEDIA_AXI_VIN0W_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x000020C8, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7791_axi_qos *)MEDIA_AXI_FDP0R_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x000020C8, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7791_axi_qos *)MEDIA_AXI_FDP0W_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x000020C8, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7791_axi_qos *)MEDIA_AXI_IMSR_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x000020C8, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7791_axi_qos *)MEDIA_AXI_IMSW_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x000020C8, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7791_axi_qos *)MEDIA_AXI_VSP1R_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x000020C8, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7791_axi_qos *)MEDIA_AXI_VSP1W_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x000020C8, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7791_axi_qos *)MEDIA_AXI_FDP1R_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x000020C8, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7791_axi_qos *)MEDIA_AXI_FDP1W_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x000020C8, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7791_axi_qos *)MEDIA_AXI_IMRR_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x000020C8, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7791_axi_qos *)MEDIA_AXI_IMRW_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x000020C8, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7791_axi_qos *)MEDIA_AXI_VSPD0R_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x000020C8, &axi_qos->qosctset0);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7791_axi_qos *)MEDIA_AXI_VSPD0W_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x000020C8, &axi_qos->qosctset0);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7791_axi_qos *)MEDIA_AXI_VSPD1R_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x000020C8, &axi_qos->qosctset0);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7791_axi_qos *)MEDIA_AXI_VSPD1W_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x000020C8, &axi_qos->qosctset0);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7791_axi_qos *)MEDIA_AXI_DU0R_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x00002063, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7791_axi_qos *)MEDIA_AXI_DU0W_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x00002063, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7791_axi_qos *)MEDIA_AXI_VCP0CR_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002073, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7791_axi_qos *)MEDIA_AXI_VCP0CW_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002073, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7791_axi_qos *)MEDIA_AXI_VCP0VR_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002073, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7791_axi_qos *)MEDIA_AXI_VCP0VW_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002073, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7791_axi_qos *)MEDIA_AXI_VPC0R_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002073, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+}
diff --git a/board/renesas/koelsch/qos.h b/board/renesas/koelsch/qos.h
new file mode 100644
index 0000000000..9a6c0461be
--- /dev/null
+++ b/board/renesas/koelsch/qos.h
@@ -0,0 +1,12 @@
+/*
+ * Copyright (C) 2013 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#ifndef __QOS_H__
+#define __QOS_H__
+
+void qos_init(void);
+
+#endif
diff --git a/board/renesas/lager/Makefile b/board/renesas/lager/Makefile
new file mode 100644
index 0000000000..034c6f8c07
--- /dev/null
+++ b/board/renesas/lager/Makefile
@@ -0,0 +1,9 @@
+#
+# board/renesas/lager/Makefile
+#
+# Copyright (C) 2013 Renesas Electronics Corporation
+#
+# SPDX-License-Identifier: GPL-2.0
+#
+
+obj-y	:= lager.o qos.o
diff --git a/board/renesas/lager/lager.c b/board/renesas/lager/lager.c
new file mode 100644
index 0000000000..ad5289a23b
--- /dev/null
+++ b/board/renesas/lager/lager.c
@@ -0,0 +1,371 @@
+/*
+ * board/renesas/lager/lager.c
+ *     This file is lager board support.
+ *
+ * Copyright (C) 2013 Renesas Electronics Corporation
+ * Copyright (C) 2013 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <common.h>
+#include <malloc.h>
+#include <netdev.h>
+#include <asm/processor.h>
+#include <asm/mach-types.h>
+#include <asm/io.h>
+#include <asm/errno.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/gpio.h>
+#include <asm/arch/rmobile.h>
+#include <miiphy.h>
+#include <i2c.h>
+#include "qos.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define s_init_wait(cnt) \
+	({	\
+		u32 i = 0x10000 * cnt;	\
+		while (i > 0)	\
+			i--;	\
+	})
+
+#define dbpdrgd_check(bsc) \
+	({	\
+		while ((readl(&bsc->dbpdrgd) & 0x1) != 0x1)	\
+			;	\
+	})
+
+#if defined(CONFIG_NORFLASH)
+static void bsc_init(void)
+{
+	struct r8a7790_lbsc *lbsc = (struct r8a7790_lbsc *)LBSC_BASE;
+	struct r8a7790_dbsc3 *dbsc3_0 = (struct r8a7790_dbsc3 *)DBSC3_0_BASE;
+
+	/* LBSC */
+	writel(0x00000020, &lbsc->cs0ctrl);
+	writel(0x00000020, &lbsc->cs1ctrl);
+	writel(0x00002020, &lbsc->ecs0ctrl);
+	writel(0x00002020, &lbsc->ecs1ctrl);
+
+	writel(0x077F077F, &lbsc->cswcr0);
+	writel(0x077F077F, &lbsc->cswcr1);
+	writel(0x077F077F, &lbsc->ecswcr0);
+	writel(0x077F077F, &lbsc->ecswcr1);
+
+	/* DBSC3 */
+	s_init_wait(10);
+
+	writel(0x0000A55A, &dbsc3_0->dbpdlck);
+	writel(0x00000001, &dbsc3_0->dbpdrga);
+	writel(0x80000000, &dbsc3_0->dbpdrgd);
+	writel(0x00000004, &dbsc3_0->dbpdrga);
+	dbpdrgd_check(dbsc3_0);
+
+	writel(0x00000006, &dbsc3_0->dbpdrga);
+	writel(0x0001C000, &dbsc3_0->dbpdrgd);
+
+	writel(0x00000023, &dbsc3_0->dbpdrga);
+	writel(0x00FD2480, &dbsc3_0->dbpdrgd);
+
+	writel(0x00000010, &dbsc3_0->dbpdrga);
+	writel(0xF004649B, &dbsc3_0->dbpdrgd);
+
+	writel(0x0000000F, &dbsc3_0->dbpdrga);
+	writel(0x00181EE4, &dbsc3_0->dbpdrgd);
+
+	writel(0x0000000E, &dbsc3_0->dbpdrga);
+	writel(0x33C03812, &dbsc3_0->dbpdrgd);
+
+	writel(0x00000003, &dbsc3_0->dbpdrga);
+	writel(0x0300C481, &dbsc3_0->dbpdrgd);
+
+	writel(0x00000007, &dbsc3_0->dbkind);
+	writel(0x10030A02, &dbsc3_0->dbconf0);
+	writel(0x00000001, &dbsc3_0->dbphytype);
+	writel(0x00000000, &dbsc3_0->dbbl);
+	writel(0x0000000B, &dbsc3_0->dbtr0);
+	writel(0x00000008, &dbsc3_0->dbtr1);
+	writel(0x00000000, &dbsc3_0->dbtr2);
+	writel(0x0000000B, &dbsc3_0->dbtr3);
+	writel(0x000C000B, &dbsc3_0->dbtr4);
+	writel(0x00000027, &dbsc3_0->dbtr5);
+	writel(0x0000001C, &dbsc3_0->dbtr6);
+	writel(0x00000005, &dbsc3_0->dbtr7);
+	writel(0x00000018, &dbsc3_0->dbtr8);
+	writel(0x00000008, &dbsc3_0->dbtr9);
+	writel(0x0000000C, &dbsc3_0->dbtr10);
+	writel(0x00000009, &dbsc3_0->dbtr11);
+	writel(0x00000012, &dbsc3_0->dbtr12);
+	writel(0x000000D0, &dbsc3_0->dbtr13);
+	writel(0x00140005, &dbsc3_0->dbtr14);
+	writel(0x00050004, &dbsc3_0->dbtr15);
+	writel(0x70233005, &dbsc3_0->dbtr16);
+	writel(0x000C0000, &dbsc3_0->dbtr17);
+	writel(0x00000300, &dbsc3_0->dbtr18);
+	writel(0x00000040, &dbsc3_0->dbtr19);
+	writel(0x00000001, &dbsc3_0->dbrnk0);
+	writel(0x00020001, &dbsc3_0->dbadj0);
+	writel(0x20082008, &dbsc3_0->dbadj2);
+	writel(0x00020002, &dbsc3_0->dbwt0cnf0);
+	writel(0x0000000F, &dbsc3_0->dbwt0cnf4);
+
+	writel(0x00000015, &dbsc3_0->dbpdrga);
+	writel(0x00000D70, &dbsc3_0->dbpdrgd);
+
+	writel(0x00000016, &dbsc3_0->dbpdrga);
+	writel(0x00000006, &dbsc3_0->dbpdrgd);
+
+	writel(0x00000017, &dbsc3_0->dbpdrga);
+	writel(0x00000018, &dbsc3_0->dbpdrgd);
+
+	writel(0x00000012, &dbsc3_0->dbpdrga);
+	writel(0x9D5CBB66, &dbsc3_0->dbpdrgd);
+
+	writel(0x00000013, &dbsc3_0->dbpdrga);
+	writel(0x1A868300, &dbsc3_0->dbpdrgd);
+
+	writel(0x00000023, &dbsc3_0->dbpdrga);
+	writel(0x00FDB6C0, &dbsc3_0->dbpdrgd);
+
+	writel(0x00000014, &dbsc3_0->dbpdrga);
+	writel(0x300214D8, &dbsc3_0->dbpdrgd);
+
+	writel(0x0000001A, &dbsc3_0->dbpdrga);
+	writel(0x930035C7, &dbsc3_0->dbpdrgd);
+
+	writel(0x00000060, &dbsc3_0->dbpdrga);
+	writel(0x330657B2, &dbsc3_0->dbpdrgd);
+
+	writel(0x00000011, &dbsc3_0->dbpdrga);
+	writel(0x1000040B, &dbsc3_0->dbpdrgd);
+
+	writel(0x0000FA00, &dbsc3_0->dbcmd);
+	writel(0x00000001, &dbsc3_0->dbpdrga);
+	writel(0x00000071, &dbsc3_0->dbpdrgd);
+
+	writel(0x00000004, &dbsc3_0->dbpdrga);
+	dbpdrgd_check(dbsc3_0);
+
+	writel(0x0000FA00, &dbsc3_0->dbcmd);
+	writel(0x2100FA00, &dbsc3_0->dbcmd);
+	writel(0x0000FA00, &dbsc3_0->dbcmd);
+	writel(0x0000FA00, &dbsc3_0->dbcmd);
+	writel(0x0000FA00, &dbsc3_0->dbcmd);
+	writel(0x0000FA00, &dbsc3_0->dbcmd);
+	writel(0x0000FA00, &dbsc3_0->dbcmd);
+	writel(0x0000FA00, &dbsc3_0->dbcmd);
+	writel(0x0000FA00, &dbsc3_0->dbcmd);
+
+	writel(0x110000DB, &dbsc3_0->dbcmd);
+
+	writel(0x00000001, &dbsc3_0->dbpdrga);
+	writel(0x00000181, &dbsc3_0->dbpdrgd);
+
+	writel(0x00000004, &dbsc3_0->dbpdrga);
+	dbpdrgd_check(dbsc3_0);
+
+	writel(0x00000001, &dbsc3_0->dbpdrga);
+	writel(0x0000FE01, &dbsc3_0->dbpdrgd);
+
+	writel(0x00000004, &dbsc3_0->dbpdrga);
+	dbpdrgd_check(dbsc3_0);
+
+	writel(0x00000000, &dbsc3_0->dbbs0cnt1);
+	writel(0x01004C20, &dbsc3_0->dbcalcnf);
+	writel(0x014000AA, &dbsc3_0->dbcaltr);
+	writel(0x00000140, &dbsc3_0->dbrfcnf0);
+	writel(0x00081860, &dbsc3_0->dbrfcnf1);
+	writel(0x00010000, &dbsc3_0->dbrfcnf2);
+	writel(0x00000001, &dbsc3_0->dbrfen);
+	writel(0x00000001, &dbsc3_0->dbacen);
+}
+#else
+#define bsc_init() do {} while (0)
+#endif /* CONFIG_NORFLASH */
+
+void s_init(void)
+{
+	struct r8a7790_rwdt *rwdt = (struct r8a7790_rwdt *)RWDT_BASE;
+	struct r8a7790_swdt *swdt = (struct r8a7790_swdt *)SWDT_BASE;
+
+	/* Watchdog init */
+	writel(0xA5A5A500, &rwdt->rwtcsra);
+	writel(0xA5A5A500, &swdt->swtcsra);
+
+	/* QoS(Quality-of-Service) Init */
+	qos_init();
+
+	/* BSC init */
+	bsc_init();
+}
+
+#define MSTPSR1	0xE6150038
+#define SMSTPCR1	0xE6150134
+#define TMU0_MSTP125	(1 << 25)
+
+#define MSTPSR7	0xE61501C4
+#define SMSTPCR7	0xE615014C
+#define SCIF0_MSTP721	(1 << 21)
+
+#define MSTPSR8	0xE61509A0
+#define SMSTPCR8	0xE6150990
+#define ETHER_MSTP813	(1 << 13)
+
+#define PMMR	0xE6060000
+#define GPSR4	0xE6060014
+#define IPSR14	0xE6060058
+
+#define	set_guard_reg(addr, mask, value)	\
+{ \
+	u32	val; \
+	val = (readl(addr) & ~(mask)) | (value);	\
+	writel(~val, PMMR);	\
+	writel(val, addr);	\
+}
+
+#define mstp_setbits(type, addr, saddr, set) \
+	out_##type((saddr), in_##type(addr) | (set))
+#define mstp_clrbits(type, addr, saddr, clear) \
+	out_##type((saddr), in_##type(addr) & ~(clear))
+#define mstp_setbits_le32(addr, saddr, set)	\
+		mstp_setbits(le32, addr, saddr, set)
+#define mstp_clrbits_le32(addr, saddr, clear)	\
+		mstp_clrbits(le32, addr, saddr, clear)
+
+int board_early_init_f(void)
+{
+	/* TMU0 */
+	mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125);
+
+#if defined(CONFIG_NORFLASH)
+	/* SCIF0 */
+	set_guard_reg(GPSR4, 0x34000000, 0x00000000);
+	set_guard_reg(IPSR14, 0x00000FC7, 0x00000481);
+	set_guard_reg(GPSR4,  0x00000000, 0x34000000);
+#endif
+
+	mstp_clrbits_le32(MSTPSR7, SMSTPCR7, SCIF0_MSTP721);
+
+	/* ETHER */
+	mstp_clrbits_le32(MSTPSR8, SMSTPCR8, ETHER_MSTP813);
+
+	return 0;
+}
+
+void arch_preboot_os(void)
+{
+	/* Disable TMU0 */
+	mstp_setbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125);
+}
+
+DECLARE_GLOBAL_DATA_PTR;
+int board_init(void)
+{
+	/* board id for linux */
+	gd->bd->bi_arch_number = MACH_TYPE_LAGER;
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = LAGER_SDRAM_BASE + 0x100;
+
+	/* Init PFC controller */
+	r8a7790_pinmux_init();
+
+	/* ETHER Enable */
+	gpio_request(GPIO_FN_ETH_CRS_DV, NULL);
+	gpio_request(GPIO_FN_ETH_RX_ER, NULL);
+	gpio_request(GPIO_FN_ETH_RXD0, NULL);
+	gpio_request(GPIO_FN_ETH_RXD1, NULL);
+	gpio_request(GPIO_FN_ETH_LINK, NULL);
+	gpio_request(GPIO_FN_ETH_REF_CLK, NULL);
+	gpio_request(GPIO_FN_ETH_MDIO, NULL);
+	gpio_request(GPIO_FN_ETH_TXD1, NULL);
+	gpio_request(GPIO_FN_ETH_TX_EN, NULL);
+	gpio_request(GPIO_FN_ETH_MAGIC, NULL);
+	gpio_request(GPIO_FN_ETH_TXD0, NULL);
+	gpio_request(GPIO_FN_ETH_MDC, NULL);
+	gpio_request(GPIO_FN_IRQ0, NULL);
+
+	gpio_request(GPIO_GP_5_31, NULL);	/* PHY_RST */
+	gpio_direction_output(GPIO_GP_5_31, 0);
+	mdelay(20);
+	gpio_set_value(GPIO_GP_5_31, 1);
+	udelay(1);
+
+	return 0;
+}
+
+#define CXR24 0xEE7003C0 /* MAC address high register */
+#define CXR25 0xEE7003C8 /* MAC address low register */
+int board_eth_init(bd_t *bis)
+{
+	int ret = -ENODEV;
+
+#ifdef CONFIG_SH_ETHER
+	u32 val;
+	unsigned char enetaddr[6];
+
+	ret = sh_eth_initialize(bis);
+	if (!eth_getenv_enetaddr("ethaddr", enetaddr))
+		return ret;
+
+	/* Set Mac address */
+	val = enetaddr[0] << 24 | enetaddr[1] << 16 |
+	    enetaddr[2] << 8 | enetaddr[3];
+	writel(val, CXR24);
+
+	val = enetaddr[4] << 8 | enetaddr[5];
+	writel(val, CXR25);
+
+#endif
+
+	return ret;
+}
+
+/* lager has KSZ8041NL/RNL */
+#define PHY_CONTROL1	0x1E
+#define PHY_LED_MODE	0xC0000
+#define PHY_LED_MODE_ACK	0x4000
+int board_phy_config(struct phy_device *phydev)
+{
+	int ret = phy_read(phydev, MDIO_DEVAD_NONE, PHY_CONTROL1);
+	ret &= ~PHY_LED_MODE;
+	ret |= PHY_LED_MODE_ACK;
+	ret = phy_write(phydev, MDIO_DEVAD_NONE, PHY_CONTROL1, (u16)ret);
+
+	return 0;
+}
+
+int dram_init(void)
+{
+	gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
+	gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
+
+	return 0;
+}
+
+const struct rmobile_sysinfo sysinfo = {
+	CONFIG_RMOBILE_BOARD_STRING
+};
+
+void dram_init_banksize(void)
+{
+	gd->bd->bi_dram[0].start = LAGER_SDRAM_BASE;
+	gd->bd->bi_dram[0].size = LAGER_SDRAM_SIZE;
+}
+
+int board_late_init(void)
+{
+	return 0;
+}
+
+void reset_cpu(ulong addr)
+{
+	u8 val;
+
+	i2c_set_bus_num(3); /* PowerIC connected to ch3 */
+	i2c_init(400000, 0);
+	i2c_read(CONFIG_SYS_I2C_POWERIC_ADDR, 0x13, 1, &val, 1);
+	val |= 0x02;
+	i2c_write(CONFIG_SYS_I2C_POWERIC_ADDR, 0x13, 1, &val, 1);
+}
diff --git a/board/renesas/lager/qos.c b/board/renesas/lager/qos.c
new file mode 100644
index 0000000000..b88511a326
--- /dev/null
+++ b/board/renesas/lager/qos.c
@@ -0,0 +1,1119 @@
+/*
+ * board/renesas/lager/qos.c
+ *
+ * Copyright (C) 2013 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+#include <asm/mach-types.h>
+#include <asm/io.h>
+#include <asm/arch/rmobile.h>
+
+/* QoS version 0.954 */
+
+enum {
+	DBSC3_R00, DBSC3_R01, DBSC3_R02, DBSC3_R03, DBSC3_R04,
+	DBSC3_R05, DBSC3_R06, DBSC3_R07, DBSC3_R08, DBSC3_R09,
+	DBSC3_R10, DBSC3_R11, DBSC3_R12, DBSC3_R13, DBSC3_R14,
+	DBSC3_R15,
+	DBSC3_W00, DBSC3_W01, DBSC3_W02, DBSC3_W03, DBSC3_W04,
+	DBSC3_W05, DBSC3_W06, DBSC3_W07, DBSC3_W08, DBSC3_W09,
+	DBSC3_W10, DBSC3_W11, DBSC3_W12, DBSC3_W13, DBSC3_W14,
+	DBSC3_W15,
+	DBSC3_NR,
+};
+
+static const u32 dbsc3_qos_addr[DBSC3_NR] = {
+	[DBSC3_R00] = DBSC3_0_QOS_R0_BASE,
+	[DBSC3_R01] = DBSC3_0_QOS_R1_BASE,
+	[DBSC3_R02] = DBSC3_0_QOS_R2_BASE,
+	[DBSC3_R03] = DBSC3_0_QOS_R3_BASE,
+	[DBSC3_R04] = DBSC3_0_QOS_R4_BASE,
+	[DBSC3_R05] = DBSC3_0_QOS_R5_BASE,
+	[DBSC3_R06] = DBSC3_0_QOS_R6_BASE,
+	[DBSC3_R07] = DBSC3_0_QOS_R7_BASE,
+	[DBSC3_R08] = DBSC3_0_QOS_R8_BASE,
+	[DBSC3_R09] = DBSC3_0_QOS_R9_BASE,
+	[DBSC3_R10] = DBSC3_0_QOS_R10_BASE,
+	[DBSC3_R11] = DBSC3_0_QOS_R11_BASE,
+	[DBSC3_R12] = DBSC3_0_QOS_R12_BASE,
+	[DBSC3_R13] = DBSC3_0_QOS_R13_BASE,
+	[DBSC3_R14] = DBSC3_0_QOS_R14_BASE,
+	[DBSC3_R15] = DBSC3_0_QOS_R15_BASE,
+	[DBSC3_W00] = DBSC3_0_QOS_W0_BASE,
+	[DBSC3_W01] = DBSC3_0_QOS_W1_BASE,
+	[DBSC3_W02] = DBSC3_0_QOS_W2_BASE,
+	[DBSC3_W03] = DBSC3_0_QOS_W3_BASE,
+	[DBSC3_W04] = DBSC3_0_QOS_W4_BASE,
+	[DBSC3_W05] = DBSC3_0_QOS_W5_BASE,
+	[DBSC3_W06] = DBSC3_0_QOS_W6_BASE,
+	[DBSC3_W07] = DBSC3_0_QOS_W7_BASE,
+	[DBSC3_W08] = DBSC3_0_QOS_W8_BASE,
+	[DBSC3_W09] = DBSC3_0_QOS_W9_BASE,
+	[DBSC3_W10] = DBSC3_0_QOS_W10_BASE,
+	[DBSC3_W11] = DBSC3_0_QOS_W11_BASE,
+	[DBSC3_W12] = DBSC3_0_QOS_W12_BASE,
+	[DBSC3_W13] = DBSC3_0_QOS_W13_BASE,
+	[DBSC3_W14] = DBSC3_0_QOS_W14_BASE,
+	[DBSC3_W15] = DBSC3_0_QOS_W15_BASE,
+};
+
+void qos_init(void)
+{
+	int i;
+	struct r8a7790_s3c *s3c;
+	struct r8a7790_s3c_qos *s3c_qos;
+	struct r8a7790_dbsc3_qos *qos_addr;
+	struct r8a7790_mxi *mxi;
+	struct r8a7790_mxi_qos *mxi_qos;
+	struct r8a7790_axi_qos *axi_qos;
+
+	/* DBSC DBADJ2 */
+	writel(0x20042004, DBSC3_0_DBADJ2);
+
+	/* S3C -QoS */
+	s3c = (struct r8a7790_s3c *)S3C_BASE;
+	writel(0x80FF1C1E, &s3c->s3cadsplcr);
+	writel(0x1F060505, &s3c->s3crorr);
+	writel(0x1F020100, &s3c->s3cworr);
+
+	/* QoS Control Registers */
+	s3c_qos = (struct r8a7790_s3c_qos *)S3C_QOS_CCI0_BASE;
+	writel(0x00800080, &s3c_qos->s3cqos0);
+	writel(0x22000010, &s3c_qos->s3cqos1);
+	writel(0x22002200, &s3c_qos->s3cqos2);
+	writel(0x2F002200, &s3c_qos->s3cqos3);
+	writel(0x2F002F00, &s3c_qos->s3cqos4);
+	writel(0x22000010, &s3c_qos->s3cqos5);
+	writel(0x22002200, &s3c_qos->s3cqos6);
+	writel(0x2F002200, &s3c_qos->s3cqos7);
+	writel(0x2F002F00, &s3c_qos->s3cqos8);
+
+	s3c_qos = (struct r8a7790_s3c_qos *)S3C_QOS_CCI1_BASE;
+	writel(0x00800080, &s3c_qos->s3cqos0);
+	writel(0x22000010, &s3c_qos->s3cqos1);
+	writel(0x22002200, &s3c_qos->s3cqos2);
+	writel(0x2F002200, &s3c_qos->s3cqos3);
+	writel(0x2F002F00, &s3c_qos->s3cqos4);
+	writel(0x22000010, &s3c_qos->s3cqos5);
+	writel(0x22002200, &s3c_qos->s3cqos6);
+	writel(0x2F002200, &s3c_qos->s3cqos7);
+	writel(0x2F002F00, &s3c_qos->s3cqos8);
+
+	s3c_qos = (struct r8a7790_s3c_qos *)S3C_QOS_MXI_BASE;
+	writel(0x80918099, &s3c_qos->s3cqos0);
+	writel(0x20410010, &s3c_qos->s3cqos1);
+	writel(0x200A2023, &s3c_qos->s3cqos2);
+	writel(0x20502001, &s3c_qos->s3cqos3);
+	writel(0x00002032, &s3c_qos->s3cqos4);
+	writel(0x20410FFF, &s3c_qos->s3cqos5);
+	writel(0x200A2023, &s3c_qos->s3cqos6);
+	writel(0x20502001, &s3c_qos->s3cqos7);
+	writel(0x20142032, &s3c_qos->s3cqos8);
+
+	s3c_qos = (struct r8a7790_s3c_qos *)S3C_QOS_AXI_BASE;
+
+	writel(0x00810089, &s3c_qos->s3cqos0);
+	writel(0x20410001, &s3c_qos->s3cqos1);
+	writel(0x200A2023, &s3c_qos->s3cqos2);
+	writel(0x20502001, &s3c_qos->s3cqos3);
+	writel(0x00002032, &s3c_qos->s3cqos4);
+	writel(0x20410FFF, &s3c_qos->s3cqos5);
+	writel(0x200A2023, &s3c_qos->s3cqos6);
+	writel(0x20502001, &s3c_qos->s3cqos7);
+	writel(0x20142032, &s3c_qos->s3cqos8);
+
+	writel(0x00200808, &s3c->s3carcr11);
+
+	/* DBSC -QoS */
+	/* DBSC0 - Read/Write */
+	for (i = DBSC3_R00; i < DBSC3_NR; i++) {
+		qos_addr = (struct r8a7790_dbsc3_qos *)dbsc3_qos_addr[i];
+		writel(0x00000203, &qos_addr->dblgcnt);
+		writel(0x00002064, &qos_addr->dbtmval0);
+		writel(0x00002048, &qos_addr->dbtmval1);
+		writel(0x00002032, &qos_addr->dbtmval2);
+		writel(0x00002019, &qos_addr->dbtmval3);
+		writel(0x00000001, &qos_addr->dbrqctr);
+		writel(0x00002019, &qos_addr->dbthres0);
+		writel(0x00002019, &qos_addr->dbthres1);
+		writel(0x00002019, &qos_addr->dbthres2);
+		writel(0x00000000, &qos_addr->dblgqon);
+	}
+	/* CCI-400 -QoS */
+	writel(0x20001000, CCI_400_MAXOT_1);
+	writel(0x20001000, CCI_400_MAXOT_2);
+	writel(0x0000000C, CCI_400_QOSCNTL_1);
+	writel(0x0000000C, CCI_400_QOSCNTL_2);
+
+	/* MXI -QoS */
+	/* Transaction Control (MXI) */
+	mxi = (struct r8a7790_mxi *)MXI_BASE;
+	writel(0x00000013, &mxi->mxrtcr);
+	writel(0x00000013, &mxi->mxwtcr);
+	writel(0x00B800C0, &mxi->mxsaar0);
+	writel(0x02000800, &mxi->mxsaar1);
+	writel(0x00200000, &mxi->mxs3cracr);
+	writel(0x00200000, &mxi->mxs3cwacr);
+	writel(0x00200000, &mxi->mxaxiracr);
+	writel(0x00200000, &mxi->mxaxiwacr);
+
+	/* QoS Control (MXI) */
+	mxi_qos = (struct r8a7790_mxi_qos *)MXI_QOS_BASE;
+	writel(0x0000000C, &mxi_qos->vspdu0);
+	writel(0x0000000C, &mxi_qos->vspdu1);
+	writel(0x0000000D, &mxi_qos->du0);
+	writel(0x0000000D, &mxi_qos->du1);
+
+	/* AXI -QoS */
+	/* Transaction Control (MXI) */
+	axi_qos = (struct r8a7790_axi_qos *)SYS_AXI_SYX64TO128_BASE;
+	writel(0x00000002, &axi_qos->qosconf);
+	writel(0x0000200F, &axi_qos->qosctset0);
+	writel(0x00002009, &axi_qos->qosctset1);
+	writel(0x00002003, &axi_qos->qosctset2);
+	writel(0x00002003, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7790_axi_qos *)SYS_AXI_AVB_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x0000200A, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7790_axi_qos *)SYS_AXI_G2D_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x0000200A, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7790_axi_qos *)SYS_AXI_IMP0_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x00002002, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7790_axi_qos *)SYS_AXI_IMP1_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x00002004, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7790_axi_qos *)SYS_AXI_IMUX0_BASE;
+	writel(0x00000002, &axi_qos->qosconf);
+	writel(0x0000200F, &axi_qos->qosctset0);
+	writel(0x00002009, &axi_qos->qosctset1);
+	writel(0x00002003, &axi_qos->qosctset2);
+	writel(0x00002003, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7790_axi_qos *)SYS_AXI_IMUX1_BASE;
+	writel(0x00000002, &axi_qos->qosconf);
+	writel(0x0000200F, &axi_qos->qosctset0);
+	writel(0x00002009, &axi_qos->qosctset1);
+	writel(0x00002003, &axi_qos->qosctset2);
+	writel(0x00002003, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7790_axi_qos *)SYS_AXI_IMUX2_BASE;
+	writel(0x00000002, &axi_qos->qosconf);
+	writel(0x0000200F, &axi_qos->qosctset0);
+	writel(0x00002009, &axi_qos->qosctset1);
+	writel(0x00002003, &axi_qos->qosctset2);
+	writel(0x00002003, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7790_axi_qos *)SYS_AXI_LBS_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x00002014, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7790_axi_qos *)SYS_AXI_MMUDS_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002001, &axi_qos->qosctset0);
+	writel(0x00002009, &axi_qos->qosctset1);
+	writel(0x00002003, &axi_qos->qosctset2);
+	writel(0x00002003, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7790_axi_qos *)SYS_AXI_MMUM_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002001, &axi_qos->qosctset0);
+	writel(0x00002009, &axi_qos->qosctset1);
+	writel(0x00002003, &axi_qos->qosctset2);
+	writel(0x00002003, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7790_axi_qos *)SYS_AXI_MMUR_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002001, &axi_qos->qosctset0);
+	writel(0x00002009, &axi_qos->qosctset1);
+	writel(0x00002003, &axi_qos->qosctset2);
+	writel(0x00002003, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7790_axi_qos *)SYS_AXI_MMUS0_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002001, &axi_qos->qosctset0);
+	writel(0x00002009, &axi_qos->qosctset1);
+	writel(0x00002003, &axi_qos->qosctset2);
+	writel(0x00002003, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7790_axi_qos *)SYS_AXI_MMUS1_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002001, &axi_qos->qosctset0);
+	writel(0x00002009, &axi_qos->qosctset1);
+	writel(0x00002003, &axi_qos->qosctset2);
+	writel(0x00002003, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7790_axi_qos *)SYS_AXI_MTSB0_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x00002002, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7790_axi_qos *)SYS_AXI_MTSB1_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x00002002, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7790_axi_qos *)SYS_AXI_PCI_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x00002014, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7790_axi_qos *)SYS_AXI_RTX_BASE;
+	writel(0x00000002, &axi_qos->qosconf);
+	writel(0x0000200F, &axi_qos->qosctset0);
+	writel(0x00002009, &axi_qos->qosctset1);
+	writel(0x00002003, &axi_qos->qosctset2);
+	writel(0x00002003, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7790_axi_qos *)SYS_AXI_SDS0_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x0000200A, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7790_axi_qos *)SYS_AXI_SDS1_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x0000200A, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7790_axi_qos *)SYS_AXI_USB20_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x00002005, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7790_axi_qos *)SYS_AXI_USB21_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x00002005, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7790_axi_qos *)SYS_AXI_USB22_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x00002005, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7790_axi_qos *)SYS_AXI_USB30_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x00002014, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	/* QoS Register (RT-AXI) */
+	axi_qos = (struct r8a7790_axi_qos *)RT_AXI_SHX_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x00002005, &axi_qos->qosctset0);
+	writel(0x00002009, &axi_qos->qosctset1);
+	writel(0x00002003, &axi_qos->qosctset2);
+	writel(0x00002003, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7790_axi_qos *)RT_AXI_RDS_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x00002007, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7790_axi_qos *)RT_AXI_RTX64TO128_BASE;
+	writel(0x00000002, &axi_qos->qosconf);
+	writel(0x0000200F, &axi_qos->qosctset0);
+	writel(0x00002009, &axi_qos->qosctset1);
+	writel(0x00002003, &axi_qos->qosctset2);
+	writel(0x00002003, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7790_axi_qos *)RT_AXI_STPRO_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x00002003, &axi_qos->qosctset0);
+	writel(0x00002009, &axi_qos->qosctset1);
+	writel(0x00002003, &axi_qos->qosctset2);
+	writel(0x00002003, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	/* QoS Register (MP-AXI) */
+	axi_qos = (struct r8a7790_axi_qos *)MP_AXI_ADSP_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x00002007, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7790_axi_qos *)MP_AXI_ASDS0_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002014, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7790_axi_qos *)MP_AXI_ASDS1_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002014, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7790_axi_qos *)MP_AXI_MLP_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x00002002, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7790_axi_qos *)MP_AXI_MMUMP_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002001, &axi_qos->qosctset0);
+	writel(0x00002009, &axi_qos->qosctset1);
+	writel(0x00002003, &axi_qos->qosctset2);
+	writel(0x00002003, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7790_axi_qos *)MP_AXI_SPU_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x00002018, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7790_axi_qos *)MP_AXI_SPUC_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x0000200D, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	/* QoS Register (SYS-AXI256) */
+	axi_qos = (struct r8a7790_axi_qos *)SYS_AXI256_AXI128TO256_BASE;
+	writel(0x00000002, &axi_qos->qosconf);
+	writel(0x0000200F, &axi_qos->qosctset0);
+	writel(0x00002009, &axi_qos->qosctset1);
+	writel(0x00002003, &axi_qos->qosctset2);
+	writel(0x00002003, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7790_axi_qos *)SYS_AXI256_SYX_BASE;
+	writel(0x00000002, &axi_qos->qosconf);
+	writel(0x0000200F, &axi_qos->qosctset0);
+	writel(0x00002009, &axi_qos->qosctset1);
+	writel(0x00002003, &axi_qos->qosctset2);
+	writel(0x00002003, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7790_axi_qos *)SYS_AXI256_MPX_BASE;
+	writel(0x00000002, &axi_qos->qosconf);
+	writel(0x0000200F, &axi_qos->qosctset0);
+	writel(0x00002009, &axi_qos->qosctset1);
+	writel(0x00002003, &axi_qos->qosctset2);
+	writel(0x00002003, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7790_axi_qos *)SYS_AXI256_MXI_BASE;
+	writel(0x00000002, &axi_qos->qosconf);
+	writel(0x0000200F, &axi_qos->qosctset0);
+	writel(0x00002009, &axi_qos->qosctset1);
+	writel(0x00002003, &axi_qos->qosctset2);
+	writel(0x00002003, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	/* QoS Register (CCI-AXI) */
+	axi_qos = (struct r8a7790_axi_qos *)CCI_AXI_MMUS0_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002001, &axi_qos->qosctset0);
+	writel(0x00002009, &axi_qos->qosctset1);
+	writel(0x00002003, &axi_qos->qosctset2);
+	writel(0x00002003, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7790_axi_qos *)CCI_AXI_SYX2_BASE;
+	writel(0x00000002, &axi_qos->qosconf);
+	writel(0x0000200F, &axi_qos->qosctset0);
+	writel(0x00002009, &axi_qos->qosctset1);
+	writel(0x00002003, &axi_qos->qosctset2);
+	writel(0x00002003, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7790_axi_qos *)CCI_AXI_MMUR_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002001, &axi_qos->qosctset0);
+	writel(0x00002009, &axi_qos->qosctset1);
+	writel(0x00002003, &axi_qos->qosctset2);
+	writel(0x00002003, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7790_axi_qos *)CCI_AXI_MMUDS_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002001, &axi_qos->qosctset0);
+	writel(0x00002009, &axi_qos->qosctset1);
+	writel(0x00002003, &axi_qos->qosctset2);
+	writel(0x00002003, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7790_axi_qos *)CCI_AXI_MMUM_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002001, &axi_qos->qosctset0);
+	writel(0x00002009, &axi_qos->qosctset1);
+	writel(0x00002003, &axi_qos->qosctset2);
+	writel(0x00002003, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7790_axi_qos *)CCI_AXI_MXI_BASE;
+	writel(0x00000002, &axi_qos->qosconf);
+	writel(0x0000200F, &axi_qos->qosctset0);
+	writel(0x00002009, &axi_qos->qosctset1);
+	writel(0x00002003, &axi_qos->qosctset2);
+	writel(0x00002003, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7790_axi_qos *)CCI_AXI_MMUS1_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002001, &axi_qos->qosctset0);
+	writel(0x00002009, &axi_qos->qosctset1);
+	writel(0x00002003, &axi_qos->qosctset2);
+	writel(0x00002003, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7790_axi_qos *)CCI_AXI_MMUMP_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002001, &axi_qos->qosctset0);
+	writel(0x00002009, &axi_qos->qosctset1);
+	writel(0x00002003, &axi_qos->qosctset2);
+	writel(0x00002003, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	/* QoS Register (Media-AXI) */
+	axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_JPR_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002018, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_JPW_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002018, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_GCU0R_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002018, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_GCU0W_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002018, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_GCU1R_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002018, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_GCU1W_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002018, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_TDMR_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002018, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_TDMW_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002018, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_VSP0CR_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002018, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_VSP0CW_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002018, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_VSP1CR_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002018, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_VSP1CW_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002018, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_VSPDU0CR_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002018, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_VSPDU0CW_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002018, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_VSPDU1CR_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002018, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_VSPDU1CW_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002018, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_VIN0W_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x0000200C, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_VSP0R_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x0000200C, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_VSP0W_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x0000200C, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_FDP0R_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x0000200C, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_FDP0W_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x0000200C, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_IMSR_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x0000200C, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_IMSW_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x0000200C, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_VSP1R_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x0000200C, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_VSP1W_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x0000200C, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_FDP1R_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x0000200C, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_FDP1W_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x0000200C, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_IMRR_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x0000200C, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_IMRW_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x0000200C, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_FDP2R_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x0000200C, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_FDP2W_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x0000200C, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_VSPD0R_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x0000200C, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_VSPD0W_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x0000200C, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_VSPD1R_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x0000200C, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_VSPD1W_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x0000200C, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_DU0R_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x0000200C, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_DU0W_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x0000200C, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_DU1R_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x0000200C, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_DU1W_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x0000200C, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_VCP0CR_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002007, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_VCP0CW_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002007, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_VCP0VR_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002007, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_VCP0VW_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002007, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_VPC0R_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002007, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_VCP1CR_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002007, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_VCP1CW_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002007, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_VCP1VR_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002007, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_VCP1VW_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002007, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_VPC1R_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002007, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000000, &axi_qos->qosqon);
+}
diff --git a/board/renesas/lager/qos.h b/board/renesas/lager/qos.h
new file mode 100644
index 0000000000..9a6c0461be
--- /dev/null
+++ b/board/renesas/lager/qos.h
@@ -0,0 +1,12 @@
+/*
+ * Copyright (C) 2013 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#ifndef __QOS_H__
+#define __QOS_H__
+
+void qos_init(void);
+
+#endif
diff --git a/board/renesas/r0p7734/Makefile b/board/renesas/r0p7734/Makefile
index 24933cc491..1f24d92962 100644
--- a/board/renesas/r0p7734/Makefile
+++ b/board/renesas/r0p7734/Makefile
@@ -3,25 +3,5 @@
 #
 # SPDX-License-Identifier:	GPL-2.0+
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	:= r0p7734.o
-SOBJS	:= lowlevel_init.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB): $(obj).depend $(OBJS) $(SOBJS)
-	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	:= r0p7734.o
+obj-y	+= lowlevel_init.o
diff --git a/board/renesas/r2dplus/Makefile b/board/renesas/r2dplus/Makefile
index f0023abe86..acffb6d319 100644
--- a/board/renesas/r2dplus/Makefile
+++ b/board/renesas/r2dplus/Makefile
@@ -4,25 +4,6 @@
 #
 # SPDX-License-Identifier:	GPL-2.0+
 #
-include $(TOPDIR)/config.mk
 
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	:= r2dplus.o
-SOBJS	:= lowlevel_init.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(OBJS) $(SOBJS)
-	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	:= r2dplus.o
+obj-y	+= lowlevel_init.o
diff --git a/board/renesas/r7780mp/Makefile b/board/renesas/r7780mp/Makefile
index c95ac12f4d..8dab4358cd 100644
--- a/board/renesas/r7780mp/Makefile
+++ b/board/renesas/r7780mp/Makefile
@@ -5,25 +5,5 @@
 #
 # SPDX-License-Identifier:	GPL-2.0+
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	:= r7780mp.o
-SOBJS	:= lowlevel_init.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(OBJS) $(SOBJS)
-	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	:= r7780mp.o
+obj-y	+= lowlevel_init.o
diff --git a/board/renesas/rsk7203/Makefile b/board/renesas/rsk7203/Makefile
index 13ffa4f8b5..16acfaf40a 100644
--- a/board/renesas/rsk7203/Makefile
+++ b/board/renesas/rsk7203/Makefile
@@ -6,25 +6,5 @@
 #
 # SPDX-License-Identifier:	GPL-2.0+
 
-include $(TOPDIR)/config.mk
-
-LIB	= lib$(BOARD).o
-
-OBJS	:= rsk7203.o
-SOBJS	:= lowlevel_init.o
-
-LIB	:= $(addprefix $(obj),$(LIB))
-OBJS	:= $(addprefix $(obj),$(OBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
-	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	:= rsk7203.o
+obj-y	+= lowlevel_init.o
diff --git a/board/renesas/rsk7264/Makefile b/board/renesas/rsk7264/Makefile
index 476de43069..7ada697c88 100644
--- a/board/renesas/rsk7264/Makefile
+++ b/board/renesas/rsk7264/Makefile
@@ -3,23 +3,5 @@
 #
 # SPDX-License-Identifier:	GPL-2.0+
 
-include $(TOPDIR)/config.mk
-
-LIB	= lib$(BOARD).o
-
-OBJS	:= rsk7264.o
-SOBJS	:= lowlevel_init.o
-
-LIB	:= $(addprefix $(obj),$(LIB))
-OBJS	:= $(addprefix $(obj),$(OBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
-	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
+obj-y	:= rsk7264.o
+obj-y	+= lowlevel_init.o
diff --git a/board/renesas/rsk7269/Makefile b/board/renesas/rsk7269/Makefile
index 1a015573d1..0f053d8fa6 100644
--- a/board/renesas/rsk7269/Makefile
+++ b/board/renesas/rsk7269/Makefile
@@ -4,23 +4,5 @@
 #
 # SPDX-License-Identifier:	GPL-2.0+
 
-include $(TOPDIR)/config.mk
-
-LIB	= lib$(BOARD).o
-
-OBJS	:= rsk7269.o
-SOBJS	:= lowlevel_init.o
-
-LIB	:= $(addprefix $(obj),$(LIB))
-OBJS	:= $(addprefix $(obj),$(OBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
-	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
+obj-y	:= rsk7269.o
+obj-y	+= lowlevel_init.o
diff --git a/board/renesas/sh7752evb/Makefile b/board/renesas/sh7752evb/Makefile
index 70009ec8fd..856af81385 100644
--- a/board/renesas/sh7752evb/Makefile
+++ b/board/renesas/sh7752evb/Makefile
@@ -3,21 +3,5 @@
 #
 # SPDX-License-Identifier:	GPL-2.0+
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	:= sh7752evb.o spi-boot.o
-SOBJS	:= lowlevel_init.o
-
-$(LIB):	$(obj).depend $(COBJS) $(SOBJS)
-	$(call cmd_link_o_target, $(COBJS) $(SOBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	:= sh7752evb.o spi-boot.o
+obj-y	+= lowlevel_init.o
diff --git a/board/renesas/sh7753evb/Makefile b/board/renesas/sh7753evb/Makefile
new file mode 100644
index 0000000000..f7c8e949f9
--- /dev/null
+++ b/board/renesas/sh7753evb/Makefile
@@ -0,0 +1,7 @@
+#
+# Copyright (C) 2012  Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
+#
+# SPDX-License-Identifier:	GPL-2.0+
+
+obj-y	:= sh7753evb.o spi-boot.o
+obj-y	+= lowlevel_init.o
diff --git a/board/renesas/sh7753evb/lowlevel_init.S b/board/renesas/sh7753evb/lowlevel_init.S
new file mode 100644
index 0000000000..21987a51e8
--- /dev/null
+++ b/board/renesas/sh7753evb/lowlevel_init.S
@@ -0,0 +1,416 @@
+/*
+ * Copyright (C) 2013  Renesas Solutions Corp.
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#include <config.h>
+#include <version.h>
+#include <asm/processor.h>
+#include <asm/macro.h>
+
+.macro	or32, addr, data
+	mov.l \addr, r1
+	mov.l \data, r0
+	mov.l @r1, r2
+	or    r2, r0
+	mov.l r0, @r1
+.endm
+
+.macro	wait_DBCMD
+	mov.l	DBWAIT_A, r0
+	mov.l	@r0, r1
+.endm
+
+	.global lowlevel_init
+	.section	.spiboot1.text
+	.align  2
+
+lowlevel_init:
+	mov	#0, r14
+	mova	2f, r0
+	mov.l	PC_MASK, r1
+	tst	r0, r1
+	bf	2f
+
+	bra	exit_pmb
+	nop
+
+	.align	2
+
+/* If CPU runs on SDRAM (PC=0x5???????) or not. */
+PC_MASK:	.long	0x20000000
+
+2:
+	mov	#1, r14
+
+	mov.l	EXPEVT_A, r0
+	mov.l	@r0, r0
+	mov.l	EXPEVT_POWER_ON_RESET, r1
+	cmp/eq	r0, r1
+	bt	1f
+
+	/*
+	 * If EXPEVT value is manual reset or tlb multipul-hit,
+	 * initialization of DBSC3 is not necessary.
+	 */
+	bra	exit_ddr
+	nop
+
+1:
+	/*------- Reset -------*/
+	write32 MRSTCR0_A, MRSTCR0_D
+	write32 MRSTCR1_A, MRSTCR1_D
+
+	/* For Core Reset */
+	mov.l	DBACEN_A, r0
+	mov.l	@r0, r0
+	cmp/eq	#0, r0
+	bt	3f
+
+	/*
+	 * If DBACEN == 1(DBSC was already enabled), we have to avoid the
+	 * initialization of DDR3-SDRAM.
+	 */
+	bra	exit_ddr
+	nop
+
+3:
+	/*------- DBSC3 -------*/
+	/* oscillation stabilization time */
+	wait_timer	WAIT_OSC_TIME
+
+	/* step 3 */
+	write32 DBKIND_A, DBKIND_D
+
+	/* step 4 */
+	write32 DBCONF_A, DBCONF_D
+	write32 DBTR0_A, DBTR0_D
+	write32 DBTR1_A, DBTR1_D
+	write32 DBTR2_A, DBTR2_D
+	write32 DBTR3_A, DBTR3_D
+	write32 DBTR4_A, DBTR4_D
+	write32 DBTR5_A, DBTR5_D
+	write32 DBTR6_A, DBTR6_D
+	write32 DBTR7_A, DBTR7_D
+	write32 DBTR8_A, DBTR8_D
+	write32 DBTR9_A, DBTR9_D
+	write32 DBTR10_A, DBTR10_D
+	write32 DBTR11_A, DBTR11_D
+	write32 DBTR12_A, DBTR12_D
+	write32 DBTR13_A, DBTR13_D
+	write32 DBTR14_A, DBTR14_D
+	write32 DBTR15_A, DBTR15_D
+	write32 DBTR16_A, DBTR16_D
+	write32 DBTR17_A, DBTR17_D
+	write32 DBTR18_A, DBTR18_D
+	write32 DBTR19_A, DBTR19_D
+	write32 DBRNK0_A, DBRNK0_D
+	write32 DBADJ0_A, DBADJ0_D
+	write32 DBADJ2_A, DBADJ2_D
+
+	/* step 5 */
+	write32 DBCMD_A, DBCMD_RSTL_VAL
+	wait_timer	WAIT_30US
+
+	/* step 6 */
+	write32 DBCMD_A, DBCMD_PDEN_VAL
+
+	/* step 7 */
+	write32 DBPDCNT3_A, DBPDCNT3_D
+
+	/* step 8 */
+	write32 DBPDCNT1_A, DBPDCNT1_D
+	write32 DBPDCNT2_A, DBPDCNT2_D
+	write32 DBPDLCK_A, DBPDLCK_D
+	write32 DBPDRGA_A, DBPDRGA_D
+	write32 DBPDRGD_A, DBPDRGD_D
+
+	/* step 9 */
+	wait_timer	WAIT_30US
+
+	/* step 10 */
+	write32 DBPDCNT0_A, DBPDCNT0_D
+
+	/* step 11 */
+	wait_timer	WAIT_30US
+	wait_timer	WAIT_30US
+
+	/* step 12 */
+	write32 DBCMD_A, DBCMD_WAIT_VAL
+	wait_DBCMD
+
+	/* step 13 */
+	write32 DBCMD_A, DBCMD_RSTH_VAL
+	wait_DBCMD
+
+	/* step 14 */
+	write32 DBCMD_A, DBCMD_WAIT_VAL
+	write32 DBCMD_A, DBCMD_WAIT_VAL
+	write32 DBCMD_A, DBCMD_WAIT_VAL
+	write32 DBCMD_A, DBCMD_WAIT_VAL
+
+	/* step 15 */
+	write32 DBCMD_A, DBCMD_PDXT_VAL
+
+	/* step 16 */
+	write32 DBCMD_A, DBCMD_MRS2_VAL
+
+	/* step 17 */
+	write32 DBCMD_A, DBCMD_MRS3_VAL
+
+	/* step 18 */
+	write32 DBCMD_A, DBCMD_MRS1_VAL
+
+	/* step 19 */
+	write32 DBCMD_A, DBCMD_MRS0_VAL
+	write32 DBPDNCNF_A, DBPDNCNF_D
+
+	/* step 20 */
+	write32 DBCMD_A, DBCMD_ZQCL_VAL
+
+	write32 DBCMD_A, DBCMD_REF_VAL
+	write32 DBCMD_A, DBCMD_REF_VAL
+	wait_DBCMD
+
+	/* step 21 */
+	write32	DBCALTR_A, DBCALTR_D
+
+	/* step 22 */
+	write32 DBRFCNF0_A, DBRFCNF0_D
+	write32 DBRFCNF1_A, DBRFCNF1_D
+	write32 DBRFCNF2_A, DBRFCNF2_D
+
+	/* step 23 */
+	write32 DBCALCNF_A, DBCALCNF_D
+
+	/* step 24 */
+	write32 DBRFEN_A, DBRFEN_D
+	write32 DBCMD_A, DBCMD_SRXT_VAL
+
+	/* step 25 */
+	write32 DBACEN_A, DBACEN_D
+
+	/* step 26 */
+	wait_DBCMD
+
+	bra	exit_ddr
+	nop
+
+	.align 2
+
+EXPEVT_A:		.long	0xff000024
+EXPEVT_POWER_ON_RESET:	.long	0x00000000
+
+/*------- Reset -------*/
+MRSTCR0_A:	.long	0xffd50030
+MRSTCR0_D:	.long	0xfe1ffe7f
+MRSTCR1_A:	.long	0xffd50034
+MRSTCR1_D:	.long	0xfff3ffff
+
+/*------- DBSC3 -------*/
+DBCMD_A:	.long	0xfe800018
+DBKIND_A:	.long	0xfe800020
+DBCONF_A:	.long	0xfe800024
+DBTR0_A:	.long	0xfe800040
+DBTR1_A:	.long	0xfe800044
+DBTR2_A:	.long	0xfe800048
+DBTR3_A:	.long	0xfe800050
+DBTR4_A:	.long	0xfe800054
+DBTR5_A:	.long	0xfe800058
+DBTR6_A:	.long	0xfe80005c
+DBTR7_A:	.long	0xfe800060
+DBTR8_A:	.long	0xfe800064
+DBTR9_A:	.long	0xfe800068
+DBTR10_A:	.long	0xfe80006c
+DBTR11_A:	.long	0xfe800070
+DBTR12_A:	.long	0xfe800074
+DBTR13_A:	.long	0xfe800078
+DBTR14_A:	.long	0xfe80007c
+DBTR15_A:	.long	0xfe800080
+DBTR16_A:	.long	0xfe800084
+DBTR17_A:	.long	0xfe800088
+DBTR18_A:	.long	0xfe80008c
+DBTR19_A:	.long	0xfe800090
+DBRNK0_A:	.long	0xfe800100
+DBPDCNT0_A:	.long	0xfe800200
+DBPDCNT1_A:	.long	0xfe800204
+DBPDCNT2_A:	.long	0xfe800208
+DBPDCNT3_A:	.long	0xfe80020c
+DBPDLCK_A:	.long	0xfe800280
+DBPDRGA_A:	.long	0xfe800290
+DBPDRGD_A:	.long	0xfe8002a0
+DBADJ0_A:	.long	0xfe8000c0
+DBADJ2_A:	.long	0xfe8000c8
+DBRFCNF0_A:	.long	0xfe8000e0
+DBRFCNF1_A:	.long	0xfe8000e4
+DBRFCNF2_A:	.long	0xfe8000e8
+DBCALCNF_A:	.long	0xfe8000f4
+DBRFEN_A:	.long	0xfe800014
+DBACEN_A:	.long	0xfe800010
+DBWAIT_A:	.long	0xfe80001c
+DBCALTR_A:	.long	0xfe8000f8
+DBPDNCNF_A:	.long	0xfe800180
+
+WAIT_OSC_TIME:	.long	6000
+WAIT_30US:	.long	13333
+
+DBCMD_RSTL_VAL:	.long	0x20000000
+DBCMD_PDEN_VAL:	.long	0x1000d73c
+DBCMD_WAIT_VAL:	.long	0x0000d73c
+DBCMD_RSTH_VAL:	.long	0x2100d73c
+DBCMD_PDXT_VAL:	.long	0x110000c8
+DBCMD_MRS0_VAL:	.long	0x28000930
+DBCMD_MRS1_VAL:	.long	0x29000004
+DBCMD_MRS2_VAL:	.long	0x2a000008
+DBCMD_MRS3_VAL:	.long	0x2b000000
+DBCMD_ZQCL_VAL:	.long	0x03000200
+DBCMD_REF_VAL:	.long	0x0c000000
+DBCMD_SRXT_VAL:	.long	0x19000000
+DBKIND_D:	.long	0x00000007
+DBCONF_D:	.long	0x0f030a01
+DBTR0_D:	.long	0x00000007
+DBTR1_D:	.long	0x00000006
+DBTR2_D:	.long	0x00000000
+DBTR3_D:	.long	0x00000007
+DBTR4_D:	.long	0x00070007
+DBTR5_D:	.long	0x0000001b
+DBTR6_D:	.long	0x00000014
+DBTR7_D:	.long	0x00000004
+DBTR8_D:	.long	0x00000014
+DBTR9_D:	.long	0x00000004
+DBTR10_D:	.long	0x00000008
+DBTR11_D:	.long	0x00000007
+DBTR12_D:	.long	0x0000000e
+DBTR13_D:	.long	0x000000a0
+DBTR14_D:	.long	0x00060006
+DBTR15_D:	.long	0x00000003
+DBTR16_D:	.long	0x00160002
+DBTR17_D:	.long	0x000c0000
+DBTR18_D:	.long	0x00000200
+DBTR19_D:	.long	0x00000040
+DBRNK0_D:	.long	0x00000001
+DBPDCNT0_D:	.long	0x00000001
+DBPDCNT1_D:	.long	0x00000001
+DBPDCNT2_D:	.long	0x00000000
+DBPDCNT3_D:	.long	0x00004010
+DBPDLCK_D:	.long	0x0000a55a
+DBPDRGA_D:	.long	0x00000028
+DBPDRGD_D:	.long	0x00017100
+
+DBADJ0_D:	.long	0x00010000
+DBADJ2_D:	.long	0x18061806
+DBRFCNF0_D:	.long	0x000001ff
+DBRFCNF1_D:	.long	0x00081040
+DBRFCNF2_D:	.long	0x00000000
+DBCALCNF_D:	.long	0x0000ffff
+DBRFEN_D:	.long	0x00000001
+DBACEN_D:	.long	0x00000001
+DBCALTR_D:	.long	0x08200820
+DBPDNCNF_D:	.long	0x00000001
+
+	.align 2
+exit_ddr:
+#if defined(CONFIG_SH_32BIT)
+	/*------- set PMB -------*/
+	write32	PASCR_A,	PASCR_29BIT_D
+	write32	MMUCR_A,	MMUCR_D
+
+	/*****************************************************************
+	 * ent	virt		phys		v	sz	c	wt
+	 * 0	0xa0000000	0x00000000	1	128M	0	1
+	 * 1	0xa8000000	0x48000000	1	128M	0	1
+	 * 5	0x88000000	0x48000000	1	128M	1	1
+	 */
+	write32	PMB_ADDR_SPIBOOT_A,	PMB_ADDR_SPIBOOT_D
+	write32	PMB_DATA_SPIBOOT_A,	PMB_DATA_SPIBOOT_D
+	write32	PMB_ADDR_DDR_C1_A,	PMB_ADDR_DDR_C1_D
+	write32	PMB_DATA_DDR_C1_A,	PMB_DATA_DDR_C1_D
+	write32	PMB_ADDR_DDR_N1_A,	PMB_ADDR_DDR_N1_D
+	write32	PMB_DATA_DDR_N1_A,	PMB_DATA_DDR_N1_D
+
+	write32	PMB_ADDR_ENTRY2,	PMB_ADDR_NOT_USE_D
+	write32	PMB_ADDR_ENTRY3,	PMB_ADDR_NOT_USE_D
+	write32	PMB_ADDR_ENTRY4,	PMB_ADDR_NOT_USE_D
+	write32	PMB_ADDR_ENTRY6,	PMB_ADDR_NOT_USE_D
+	write32	PMB_ADDR_ENTRY7,	PMB_ADDR_NOT_USE_D
+	write32	PMB_ADDR_ENTRY8,	PMB_ADDR_NOT_USE_D
+	write32	PMB_ADDR_ENTRY9,	PMB_ADDR_NOT_USE_D
+	write32	PMB_ADDR_ENTRY10,	PMB_ADDR_NOT_USE_D
+	write32	PMB_ADDR_ENTRY11,	PMB_ADDR_NOT_USE_D
+	write32	PMB_ADDR_ENTRY12,	PMB_ADDR_NOT_USE_D
+	write32	PMB_ADDR_ENTRY13,	PMB_ADDR_NOT_USE_D
+	write32	PMB_ADDR_ENTRY14,	PMB_ADDR_NOT_USE_D
+	write32	PMB_ADDR_ENTRY15,	PMB_ADDR_NOT_USE_D
+
+	write32	PASCR_A,	PASCR_INIT
+	mov.l	DUMMY_ADDR, r0
+	icbi	@r0
+#endif	/* if defined(CONFIG_SH_32BIT) */
+
+exit_pmb:
+	/* CPU is running on ILRAM? */
+	mov	r14, r0
+	tst	#1, r0
+	bt	1f
+
+	mov.l	_stack_ilram, r15
+	mov.l	_spiboot_main, r0
+100:	bsrf	r0
+	nop
+
+	.align	2
+_spiboot_main:	.long	(spiboot_main - (100b + 4))
+_stack_ilram:	.long	0xe5204000
+
+1:
+	write32	CCR_A,	CCR_D
+
+	rts
+	 nop
+
+	.align 2
+
+#if defined(CONFIG_SH_32BIT)
+/*------- set PMB -------*/
+PMB_ADDR_SPIBOOT_A:	.long	PMB_ADDR_BASE(0)
+PMB_ADDR_DDR_N1_A:	.long	PMB_ADDR_BASE(1)
+PMB_ADDR_DDR_C1_A:	.long	PMB_ADDR_BASE(5)
+PMB_ADDR_ENTRY2:	.long	PMB_ADDR_BASE(2)
+PMB_ADDR_ENTRY3:	.long	PMB_ADDR_BASE(3)
+PMB_ADDR_ENTRY4:	.long	PMB_ADDR_BASE(4)
+PMB_ADDR_ENTRY6:	.long	PMB_ADDR_BASE(6)
+PMB_ADDR_ENTRY7:	.long	PMB_ADDR_BASE(7)
+PMB_ADDR_ENTRY8:	.long	PMB_ADDR_BASE(8)
+PMB_ADDR_ENTRY9:	.long	PMB_ADDR_BASE(9)
+PMB_ADDR_ENTRY10:	.long	PMB_ADDR_BASE(10)
+PMB_ADDR_ENTRY11:	.long	PMB_ADDR_BASE(11)
+PMB_ADDR_ENTRY12:	.long	PMB_ADDR_BASE(12)
+PMB_ADDR_ENTRY13:	.long	PMB_ADDR_BASE(13)
+PMB_ADDR_ENTRY14:	.long	PMB_ADDR_BASE(14)
+PMB_ADDR_ENTRY15:	.long	PMB_ADDR_BASE(15)
+
+PMB_ADDR_SPIBOOT_D:	.long	mk_pmb_addr_val(0xa0)
+PMB_ADDR_DDR_C1_D:	.long	mk_pmb_addr_val(0x88)
+PMB_ADDR_DDR_N1_D:	.long	mk_pmb_addr_val(0xa8)
+PMB_ADDR_NOT_USE_D:	.long	0x00000000
+
+PMB_DATA_SPIBOOT_A:	.long	PMB_DATA_BASE(0)
+PMB_DATA_DDR_N1_A:	.long	PMB_DATA_BASE(1)
+PMB_DATA_DDR_C1_A:	.long	PMB_DATA_BASE(5)
+
+/*						ppn   ub v s1 s0  c  wt */
+PMB_DATA_SPIBOOT_D:	.long	mk_pmb_data_val(0x00, 0, 1, 1, 0, 0, 1)
+PMB_DATA_DDR_C1_D:	.long	mk_pmb_data_val(0x48, 0, 1, 1, 0, 1, 1)
+PMB_DATA_DDR_N1_D:	.long	mk_pmb_data_val(0x48, 1, 1, 1, 0, 0, 1)
+
+PASCR_A:		.long	0xff000070
+DUMMY_ADDR:		.long	0xa0000000
+PASCR_29BIT_D:		.long	0x00000000
+PASCR_INIT:		.long	0x80000080
+MMUCR_A:		.long	0xff000010
+MMUCR_D:		.long	0x00000004	/* clear ITLB */
+#endif	/* CONFIG_SH_32BIT */
+
+CCR_A:		.long	CCR
+CCR_D:		.long	CCR_CACHE_INIT
diff --git a/board/renesas/sh7753evb/sh7753evb.c b/board/renesas/sh7753evb/sh7753evb.c
new file mode 100644
index 0000000000..42b920fb33
--- /dev/null
+++ b/board/renesas/sh7753evb/sh7753evb.c
@@ -0,0 +1,326 @@
+/*
+ * Copyright (C) 2012  Renesas Solutions Corp.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <malloc.h>
+#include <asm/processor.h>
+#include <asm/io.h>
+#include <asm/mmc.h>
+#include <spi_flash.h>
+
+int checkboard(void)
+{
+	puts("BOARD: SH7753 EVB\n");
+
+	return 0;
+}
+
+static void init_gpio(void)
+{
+	struct gpio_regs *gpio = GPIO_BASE;
+	struct sermux_regs *sermux = SERMUX_BASE;
+
+	/* GPIO */
+	writew(0x0000, &gpio->pacr);	/* GETHER */
+	writew(0x0001, &gpio->pbcr);	/* INTC */
+	writew(0x0000, &gpio->pccr);	/* PWMU, INTC */
+	writew(0x0000, &gpio->pdcr);	/* SPI0 */
+	writew(0xeaff, &gpio->pecr);	/* GPIO */
+	writew(0x0000, &gpio->pfcr);	/* WDT */
+	writew(0x0004, &gpio->pgcr);	/* SPI0, GETHER MDIO gate(PTG1) */
+	writew(0x0000, &gpio->phcr);	/* SPI1 */
+	writew(0x0000, &gpio->picr);	/* SDHI */
+	writew(0x0000, &gpio->pjcr);	/* SCIF4 */
+	writew(0x0003, &gpio->pkcr);	/* SerMux */
+	writew(0x0000, &gpio->plcr);	/* SerMux */
+	writew(0x0000, &gpio->pmcr);	/* RIIC */
+	writew(0x0000, &gpio->pncr);	/* USB, SGPIO */
+	writew(0x0000, &gpio->pocr);	/* SGPIO */
+	writew(0xd555, &gpio->pqcr);	/* GPIO */
+	writew(0x0000, &gpio->prcr);	/* RIIC */
+	writew(0x0000, &gpio->pscr);	/* RIIC */
+	writew(0x0000, &gpio->ptcr);	/* STATUS */
+	writeb(0x00, &gpio->pudr);
+	writew(0x5555, &gpio->pucr);	/* Debug LED */
+	writew(0x0000, &gpio->pvcr);	/* RSPI */
+	writew(0x0000, &gpio->pwcr);	/* EVC */
+	writew(0x0000, &gpio->pxcr);	/* LBSC */
+	writew(0x0000, &gpio->pycr);	/* LBSC */
+	writew(0x0000, &gpio->pzcr);	/* eMMC */
+	writew(0xfe00, &gpio->psel0);
+	writew(0x0000, &gpio->psel1);
+	writew(0x3000, &gpio->psel2);
+	writew(0xff00, &gpio->psel3);
+	writew(0x771f, &gpio->psel4);
+	writew(0x0ffc, &gpio->psel5);
+	writew(0x00ff, &gpio->psel6);
+	writew(0xfc00, &gpio->psel7);
+
+	writeb(0x10, &sermux->smr0);	/* SMR0: SerMux mode 0 */
+}
+
+static void init_usb_phy(void)
+{
+	struct usb_common_regs *common0 = USB0_COMMON_BASE;
+	struct usb_common_regs *common1 = USB1_COMMON_BASE;
+	struct usb0_phy_regs *phy = USB0_PHY_BASE;
+	struct usb1_port_regs *port = USB1_PORT_BASE;
+	struct usb1_alignment_regs *align = USB1_ALIGNMENT_BASE;
+
+	writew(0x0100, &phy->reset);		/* set reset */
+	/* port0 = USB0, port1 = USB1 */
+	writew(0x0002, &phy->portsel);
+	writel(0x0001, &port->port1sel);	/* port1 = Host */
+	writew(0x0111, &phy->reset);		/* clear reset */
+
+	writew(0x4000, &common0->suspmode);
+	writew(0x4000, &common1->suspmode);
+
+#if defined(__LITTLE_ENDIAN)
+	writel(0x00000000, &align->ehcidatac);
+	writel(0x00000000, &align->ohcidatac);
+#endif
+}
+
+static void init_gether_mdio(void)
+{
+	struct gpio_regs *gpio = GPIO_BASE;
+
+	writew(readw(&gpio->pgcr) | 0x0004, &gpio->pgcr);
+	writeb(readb(&gpio->pgdr) | 0x02, &gpio->pgdr);	/* Use ET0-MDIO */
+}
+
+static void set_mac_to_sh_giga_eth_register(int channel, char *mac_string)
+{
+	struct ether_mac_regs *ether;
+	unsigned char mac[6];
+	unsigned long val;
+
+	eth_parse_enetaddr(mac_string, mac);
+
+	if (!channel)
+		ether = GETHER0_MAC_BASE;
+	else
+		ether = GETHER1_MAC_BASE;
+
+	val = (mac[0] << 24) | (mac[1] << 16) | (mac[2] << 8) | mac[3];
+	writel(val, &ether->mahr);
+	val = (mac[4] << 8) | mac[5];
+	writel(val, &ether->malr);
+}
+
+/*****************************************************************
+ * This PMB must be set on this timing. The lowlevel_init is run on
+ * Area 0(phys 0x00000000), so we have to map it.
+ *
+ * The new PMB table is following:
+ * ent	virt		phys		v	sz	c	wt
+ * 0	0xa0000000	0x40000000	1	128M	0	1
+ * 1	0xa8000000	0x48000000	1	128M	0	1
+ * 2	0xb0000000	0x50000000	1	128M	0	1
+ * 3	0xb8000000	0x58000000	1	128M	0	1
+ * 4	0x80000000	0x40000000	1	128M	1	1
+ * 5	0x88000000	0x48000000	1	128M	1	1
+ * 6	0x90000000	0x50000000	1	128M	1	1
+ * 7	0x98000000	0x58000000	1	128M	1	1
+ */
+static void set_pmb_on_board_init(void)
+{
+	struct mmu_regs *mmu = MMU_BASE;
+
+	/* clear ITLB */
+	writel(0x00000004, &mmu->mmucr);
+
+	/* delete PMB for SPIBOOT */
+	writel(0, PMB_ADDR_BASE(0));
+	writel(0, PMB_DATA_BASE(0));
+
+	/* add PMB for SDRAM(0x40000000 - 0x47ffffff) */
+	/*			ppn  ub v s1 s0  c  wt */
+	writel(mk_pmb_addr_val(0xa0), PMB_ADDR_BASE(0));
+	writel(mk_pmb_data_val(0x40, 1, 1, 1, 0, 0, 1), PMB_DATA_BASE(0));
+	writel(mk_pmb_addr_val(0xb0), PMB_ADDR_BASE(2));
+	writel(mk_pmb_data_val(0x50, 1, 1, 1, 0, 0, 1), PMB_DATA_BASE(2));
+	writel(mk_pmb_addr_val(0xb8), PMB_ADDR_BASE(3));
+	writel(mk_pmb_data_val(0x58, 1, 1, 1, 0, 0, 1), PMB_DATA_BASE(3));
+	writel(mk_pmb_addr_val(0x80), PMB_ADDR_BASE(4));
+	writel(mk_pmb_data_val(0x40, 0, 1, 1, 0, 1, 1), PMB_DATA_BASE(4));
+	writel(mk_pmb_addr_val(0x90), PMB_ADDR_BASE(6));
+	writel(mk_pmb_data_val(0x50, 0, 1, 1, 0, 1, 1), PMB_DATA_BASE(6));
+	writel(mk_pmb_addr_val(0x98), PMB_ADDR_BASE(7));
+	writel(mk_pmb_data_val(0x58, 0, 1, 1, 0, 1, 1), PMB_DATA_BASE(7));
+}
+
+int board_init(void)
+{
+	struct gether_control_regs *gether = GETHER_CONTROL_BASE;
+
+	init_gpio();
+	set_pmb_on_board_init();
+
+	/* Sets TXnDLY to B'010 */
+	writel(0x00000202, &gether->gbecont);
+
+	init_usb_phy();
+	init_gether_mdio();
+
+	return 0;
+}
+
+int dram_init(void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE;
+	gd->bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE;
+	printf("DRAM:  %dMB\n", CONFIG_SYS_SDRAM_SIZE / (1024 * 1024));
+
+	return 0;
+}
+
+int board_mmc_init(bd_t *bis)
+{
+	struct gpio_regs *gpio = GPIO_BASE;
+
+	writew(readw(&gpio->pgcr) | 0x0040, &gpio->pgcr);
+	writeb(readb(&gpio->pgdr) & ~0x08, &gpio->pgdr); /* Reset */
+	udelay(1);
+	writeb(readb(&gpio->pgdr) | 0x08, &gpio->pgdr);	/* Release reset */
+	udelay(200);
+
+	return mmcif_mmc_init();
+}
+
+static int get_sh_eth_mac_raw(unsigned char *buf, int size)
+{
+	struct spi_flash *spi;
+	int ret;
+
+	spi = spi_flash_probe(0, 0, 1000000, SPI_MODE_3);
+	if (spi == NULL) {
+		printf("%s: spi_flash probe failed.\n", __func__);
+		return 1;
+	}
+
+	ret = spi_flash_read(spi, SH7753EVB_ETHERNET_MAC_BASE, size, buf);
+	if (ret) {
+		printf("%s: spi_flash read failed.\n", __func__);
+		spi_flash_free(spi);
+		return 1;
+	}
+	spi_flash_free(spi);
+
+	return 0;
+}
+
+static int get_sh_eth_mac(int channel, char *mac_string, unsigned char *buf)
+{
+	memcpy(mac_string, &buf[channel * (SH7753EVB_ETHERNET_MAC_SIZE + 1)],
+		SH7753EVB_ETHERNET_MAC_SIZE);
+	mac_string[SH7753EVB_ETHERNET_MAC_SIZE] = 0x00;	/* terminate */
+
+	return 0;
+}
+
+static void init_ethernet_mac(void)
+{
+	char mac_string[64];
+	char env_string[64];
+	int i;
+	unsigned char *buf;
+
+	buf = malloc(256);
+	if (!buf) {
+		printf("%s: malloc failed.\n", __func__);
+		return;
+	}
+	get_sh_eth_mac_raw(buf, 256);
+
+	/* Gigabit Ethernet */
+	for (i = 0; i < SH7753EVB_ETHERNET_NUM_CH; i++) {
+		get_sh_eth_mac(i, mac_string, buf);
+		if (i == 0)
+			setenv("ethaddr", mac_string);
+		else {
+			sprintf(env_string, "eth%daddr", i);
+			setenv(env_string, mac_string);
+		}
+		set_mac_to_sh_giga_eth_register(i, mac_string);
+	}
+
+	free(buf);
+}
+
+int board_late_init(void)
+{
+	init_ethernet_mac();
+
+	return 0;
+}
+
+int do_write_mac(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	int i, ret;
+	char mac_string[256];
+	struct spi_flash *spi;
+	unsigned char *buf;
+
+	if (argc != 3) {
+		buf = malloc(256);
+		if (!buf) {
+			printf("%s: malloc failed.\n", __func__);
+			return 1;
+		}
+
+		get_sh_eth_mac_raw(buf, 256);
+
+		/* print current MAC address */
+		for (i = 0; i < SH7753EVB_ETHERNET_NUM_CH; i++) {
+			get_sh_eth_mac(i, mac_string, buf);
+			printf("GETHERC ch%d = %s\n", i, mac_string);
+		}
+		free(buf);
+		return 0;
+	}
+
+	/* new setting */
+	memset(mac_string, 0xff, sizeof(mac_string));
+	sprintf(mac_string, "%s\t%s",
+		argv[1], argv[2]);
+
+	/* write MAC data to SPI rom */
+	spi = spi_flash_probe(0, 0, 1000000, SPI_MODE_3);
+	if (!spi) {
+		printf("%s: spi_flash probe failed.\n", __func__);
+		return 1;
+	}
+
+	ret = spi_flash_erase(spi, SH7753EVB_ETHERNET_MAC_BASE_SPI,
+				SH7753EVB_SPI_SECTOR_SIZE);
+	if (ret) {
+		printf("%s: spi_flash erase failed.\n", __func__);
+		return 1;
+	}
+
+	ret = spi_flash_write(spi, SH7753EVB_ETHERNET_MAC_BASE_SPI,
+				sizeof(mac_string), mac_string);
+	if (ret) {
+		printf("%s: spi_flash write failed.\n", __func__);
+		spi_flash_free(spi);
+		return 1;
+	}
+	spi_flash_free(spi);
+
+	puts("The writing of the MAC address to SPI ROM was completed.\n");
+
+	return 0;
+}
+
+U_BOOT_CMD(
+	write_mac,	3,	1,	do_write_mac,
+	"write MAC address for GETHERC",
+	"[GETHERC ch0] [GETHERC ch1]\n"
+);
diff --git a/board/renesas/sh7753evb/spi-boot.c b/board/renesas/sh7753evb/spi-boot.c
new file mode 100644
index 0000000000..21903d9c7b
--- /dev/null
+++ b/board/renesas/sh7753evb/spi-boot.c
@@ -0,0 +1,134 @@
+/*
+ * Copyright (C) 2013  Renesas Solutions Corp.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+
+#define CONFIG_SPI_ADDR		0x00000000
+#define PHYADDR(_addr)		((_addr & 0x1fffffff) | 0x40000000)
+#define CONFIG_RAM_BOOT_PHYS	PHYADDR(CONFIG_SYS_TEXT_BASE)
+
+#define SPIWDMADR	0xFE001018
+#define SPIWDMCNTR	0xFE001020
+#define SPIDMCOR	0xFE001028
+#define SPIDMINTSR	0xFE001188
+#define SPIDMINTMR	0xFE001190
+
+#define SPIDMINTSR_DMEND	0x00000004
+
+#define TBR	0xFE002000
+#define RBR	0xFE002000
+
+#define CR1	0xFE002008
+#define CR2	0xFE002010
+#define CR3	0xFE002018
+#define CR4	0xFE002020
+#define CR7	0xFE002038
+#define CR8	0xFE002040
+
+/* CR1 */
+#define SPI_TBE		0x80
+#define SPI_TBF		0x40
+#define SPI_RBE		0x20
+#define SPI_RBF		0x10
+#define SPI_PFONRD	0x08
+#define SPI_SSDB	0x04
+#define SPI_SSD		0x02
+#define SPI_SSA		0x01
+
+/* CR2 */
+#define SPI_RSTF	0x80
+#define SPI_LOOPBK	0x40
+#define SPI_CPOL	0x20
+#define SPI_CPHA	0x10
+#define SPI_L1M0	0x08
+
+/* CR4 */
+#define SPI_TBEI	0x80
+#define SPI_TBFI	0x40
+#define SPI_RBEI	0x20
+#define SPI_RBFI	0x10
+#define SPI_SpiS0	0x02
+#define SPI_SSS		0x01
+
+/* CR7 */
+#define CR7_IDX_OR12	0x12
+#define OR12_ADDR32	0x00000001
+
+#define spi_write(val, addr)	(*(volatile unsigned long *)(addr)) = val
+#define spi_read(addr)		(*(volatile unsigned long *)(addr))
+
+/* M25P80 */
+#define M25_READ	0x03
+#define M25_READ_4BYTE	0x13
+
+extern void bss_start(void);
+
+#define __uses_spiboot2	__attribute__((section(".spiboot2.text")))
+static void __uses_spiboot2 spi_reset(void)
+{
+	int timeout = 0x00100000;
+
+	/* Make sure the last transaction is finalized */
+	spi_write(0x00, CR3);
+	spi_write(0x02, CR1);
+	while (!(spi_read(CR4) & SPI_SpiS0)) {
+		if (timeout-- < 0)
+			break;
+	}
+	spi_write(0x00, CR1);
+
+	spi_write(spi_read(CR2) | SPI_RSTF, CR2);	/* fifo reset */
+	spi_write(spi_read(CR2) & ~SPI_RSTF, CR2);
+
+	spi_write(0, SPIDMCOR);
+}
+
+static void __uses_spiboot2 spi_read_flash(void *buf, unsigned long addr,
+					   unsigned long len)
+{
+	spi_write(CR7_IDX_OR12, CR7);
+	if (spi_read(CR8) & OR12_ADDR32) {
+		/* 4-bytes address mode */
+		spi_write(M25_READ_4BYTE, TBR);
+		spi_write((addr >> 24) & 0xFF, TBR);	/* ADDR31-24 */
+	} else {
+		/* 3-bytes address mode */
+		spi_write(M25_READ, TBR);
+	}
+	spi_write((addr >> 16) & 0xFF, TBR);	/* ADDR23-16 */
+	spi_write((addr >> 8) & 0xFF, TBR);	/* ADDR15-8 */
+	spi_write(addr & 0xFF, TBR);		/* ADDR7-0 */
+
+	spi_write(SPIDMINTSR_DMEND, SPIDMINTSR);
+	spi_write((unsigned long)buf, SPIWDMADR);
+	spi_write(len & 0xFFFFFFE0, SPIWDMCNTR);
+	spi_write(1, SPIDMCOR);
+
+	spi_write(0xff, CR3);
+	spi_write(spi_read(CR1) | SPI_SSDB, CR1);
+	spi_write(spi_read(CR1) | SPI_SSA, CR1);
+
+	while (!(spi_read(SPIDMINTSR) & SPIDMINTSR_DMEND))
+		;
+
+	/* Nagate SP0-SS0 */
+	spi_write(0, CR1);
+}
+
+void __uses_spiboot2 spiboot_main(void)
+{
+	/*
+	 * This code rounds len up for SPIWDMCNTR. We should set it to 0 in
+	 * lower 5-bits.
+	 */
+	void (*_start)(void) = (void *)CONFIG_SYS_TEXT_BASE;
+	volatile unsigned long len = (bss_start - _start + 31) & 0xffffffe0;
+
+	spi_reset();
+	spi_read_flash((void *)CONFIG_RAM_BOOT_PHYS, CONFIG_SPI_ADDR, len);
+
+	_start();
+}
diff --git a/board/renesas/sh7753evb/u-boot.lds b/board/renesas/sh7753evb/u-boot.lds
new file mode 100644
index 0000000000..053df642ea
--- /dev/null
+++ b/board/renesas/sh7753evb/u-boot.lds
@@ -0,0 +1,81 @@
+/*
+ * Copyright (C) 2007
+ * Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+ *
+ * Copyright (C) 2012
+ * Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+OUTPUT_FORMAT("elf32-sh-linux", "elf32-sh-linux", "elf32-sh-linux")
+OUTPUT_ARCH(sh)
+ENTRY(_start)
+
+SECTIONS
+{
+	/*
+	 * entry and reloct_dst will be provided via ldflags
+	 */
+	. = .;
+
+	PROVIDE (_ftext = .);
+	PROVIDE (_fcode = .);
+	PROVIDE (_start = .);
+
+	.text :
+	{
+		KEEP(arch/sh/cpu/sh4/start.o		(.text))
+		*(.spiboot1.text)
+		*(.spiboot2.text)
+		. = ALIGN(8192);
+		common/env_embedded.o	(.ppcenv)
+		. = ALIGN(8192);
+		common/env_embedded.o	(.ppcenvr)
+		. = ALIGN(8192);
+		*(.text)
+		. = ALIGN(4);
+	} =0xFF
+	PROVIDE (_ecode = .);
+	.rodata :
+	{
+		*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
+		. = ALIGN(4);
+	}
+	PROVIDE (_etext = .);
+
+
+	PROVIDE (_fdata = .);
+	.data :
+	{
+		*(.data)
+		. = ALIGN(4);
+	}
+	PROVIDE (_edata = .);
+
+	PROVIDE (_fgot = .);
+	.got :
+	{
+		*(.got)
+		. = ALIGN(4);
+	}
+	PROVIDE (_egot = .);
+
+	.u_boot_list : {
+		KEEP(*(SORT(.u_boot_list*)));
+	}
+
+	PROVIDE (reloc_dst_end = .);
+	/* _reloc_dst_end = .; */
+
+	PROVIDE (bss_start = .);
+	PROVIDE (__bss_start = .);
+	.bss (NOLOAD) :
+	{
+		*(.bss)
+		. = ALIGN(4);
+	}
+	PROVIDE (bss_end = .);
+
+	PROVIDE (__bss_end = .);
+}
diff --git a/board/renesas/sh7757lcr/Makefile b/board/renesas/sh7757lcr/Makefile
index 4bb6068a9d..1fa3992e1d 100644
--- a/board/renesas/sh7757lcr/Makefile
+++ b/board/renesas/sh7757lcr/Makefile
@@ -3,21 +3,5 @@
 #
 # SPDX-License-Identifier:	GPL-2.0+
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	:= sh7757lcr.o spi-boot.o
-SOBJS	:= lowlevel_init.o
-
-$(LIB):	$(obj).depend $(COBJS) $(SOBJS)
-	$(call cmd_link_o_target, $(COBJS) $(SOBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	:= sh7757lcr.o spi-boot.o
+obj-y	+= lowlevel_init.o
diff --git a/board/renesas/sh7763rdp/Makefile b/board/renesas/sh7763rdp/Makefile
index b311bcd032..cbf38bbc18 100644
--- a/board/renesas/sh7763rdp/Makefile
+++ b/board/renesas/sh7763rdp/Makefile
@@ -8,25 +8,5 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	:= sh7763rdp.o
-SOBJS	:= lowlevel_init.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(OBJS) $(SOBJS)
-	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	:= sh7763rdp.o
+obj-y	+= lowlevel_init.o
diff --git a/board/renesas/sh7785lcr/Makefile b/board/renesas/sh7785lcr/Makefile
index e577d566a9..e8cfb053ce 100644
--- a/board/renesas/sh7785lcr/Makefile
+++ b/board/renesas/sh7785lcr/Makefile
@@ -3,25 +3,5 @@
 #
 # SPDX-License-Identifier:	GPL-2.0+
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	:= sh7785lcr.o selfcheck.o rtl8169_mac.o
-SOBJS	:= lowlevel_init.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB): $(obj).depend $(OBJS) $(SOBJS)
-	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	:= sh7785lcr.o selfcheck.o rtl8169_mac.o
+obj-y	+= lowlevel_init.o
diff --git a/board/ronetix/pm9261/Makefile b/board/ronetix/pm9261/Makefile
index f627eaa383..3860283a3b 100644
--- a/board/ronetix/pm9261/Makefile
+++ b/board/ronetix/pm9261/Makefile
@@ -10,26 +10,6 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS-y += $(BOARD).o
-COBJS-y += led.o
-COBJS-$(CONFIG_HAS_DATAFLASH) += partition.o
-
-SRCS	:= $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS-y) $(SOBJS-y))
-SOBJS	:= $(addprefix $(obj),$(SOBJS-y))
-
-$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y += pm9261.o
+obj-y += led.o
+obj-$(CONFIG_HAS_DATAFLASH) += partition.o
diff --git a/board/ronetix/pm9261/led.c b/board/ronetix/pm9261/led.c
index 223a516179..cc4c2a072b 100644
--- a/board/ronetix/pm9261/led.c
+++ b/board/ronetix/pm9261/led.c
@@ -8,9 +8,9 @@
  */
 
 #include <common.h>
+#include <asm/gpio.h>
 #include <asm/arch/at91_pmc.h>
 #include <asm/arch/gpio.h>
-#include <asm/io.h>
 
 void coloured_LED_init(void)
 {
@@ -19,11 +19,11 @@ void coloured_LED_init(void)
 	/* Enable clock */
 	writel(1 << ATMEL_ID_PIOC, &pmc->pcer);
 
-	at91_set_pio_output(CONFIG_RED_LED, 1);
-	at91_set_pio_output(CONFIG_GREEN_LED, 1);
-	at91_set_pio_output(CONFIG_YELLOW_LED, 1);
+	gpio_direction_output(CONFIG_RED_LED, 1);
+	gpio_direction_output(CONFIG_GREEN_LED, 1);
+	gpio_direction_output(CONFIG_YELLOW_LED, 1);
 
-	at91_set_pio_value(CONFIG_RED_LED, 0);
-	at91_set_pio_value(CONFIG_GREEN_LED, 1);
-	at91_set_pio_value(CONFIG_YELLOW_LED, 1);
+	gpio_set_value(CONFIG_RED_LED, 0);
+	gpio_set_value(CONFIG_GREEN_LED, 1);
+	gpio_set_value(CONFIG_YELLOW_LED, 1);
 }
diff --git a/board/ronetix/pm9261/pm9261.c b/board/ronetix/pm9261/pm9261.c
index a2a569b0cd..ec3ac89593 100644
--- a/board/ronetix/pm9261/pm9261.c
+++ b/board/ronetix/pm9261/pm9261.c
@@ -9,8 +9,9 @@
  */
 
 #include <common.h>
-#include <asm/sizes.h>
+#include <linux/sizes.h>
 #include <asm/io.h>
+#include <asm/gpio.h>
 #include <asm/arch/at91sam9_smc.h>
 #include <asm/arch/at91_common.h>
 #include <asm/arch/at91_pmc.h>
@@ -73,10 +74,10 @@ static void pm9261_nand_hw_init(void)
 		&pmc->pcer);
 
 	/* Configure RDY/BSY */
-	at91_set_pio_input(CONFIG_SYS_NAND_READY_PIN, 1);
+	gpio_direction_input(CONFIG_SYS_NAND_READY_PIN);
 
 	/* Enable NandFlash */
-	at91_set_pio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
+	gpio_direction_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
 
 	at91_set_a_periph(AT91_PIO_PORTC, 0, 0);	/* NANDOE */
 	at91_set_a_periph(AT91_PIO_PORTC, 1, 0);	/* NANDWE */
diff --git a/board/ronetix/pm9263/Makefile b/board/ronetix/pm9263/Makefile
index 7cb6f0fba5..43ea599c4f 100644
--- a/board/ronetix/pm9263/Makefile
+++ b/board/ronetix/pm9263/Makefile
@@ -10,26 +10,6 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS-y += pm9263.o
-COBJS-y += led.o
-COBJS-$(CONFIG_HAS_DATAFLASH) += partition.o
-
-SRCS	:= $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS-y) $(SOBJS-y))
-SOBJS	:= $(addprefix $(obj),$(SOBJS-y))
-
-$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y += pm9263.o
+obj-y += led.o
+obj-$(CONFIG_HAS_DATAFLASH) += partition.o
diff --git a/board/ronetix/pm9263/led.c b/board/ronetix/pm9263/led.c
index 44e3430900..bfc2310b0e 100644
--- a/board/ronetix/pm9263/led.c
+++ b/board/ronetix/pm9263/led.c
@@ -8,9 +8,9 @@
  */
 
 #include <common.h>
+#include <asm/gpio.h>
 #include <asm/arch/at91_pmc.h>
 #include <asm/arch/gpio.h>
-#include <asm/io.h>
 
 void coloured_LED_init(void)
 {
@@ -19,9 +19,9 @@ void coloured_LED_init(void)
 	/* Enable clock */
 	writel(1 << ATMEL_ID_PIOB, &pmc->pcer);
 
-	at91_set_pio_output(CONFIG_RED_LED, 1);
-	at91_set_pio_output(CONFIG_GREEN_LED, 1);
+	gpio_direction_output(CONFIG_RED_LED, 1);
+	gpio_direction_output(CONFIG_GREEN_LED, 1);
 
-	at91_set_pio_value(CONFIG_RED_LED, 0);
-	at91_set_pio_value(CONFIG_GREEN_LED, 1);
+	gpio_set_value(CONFIG_RED_LED, 0);
+	gpio_set_value(CONFIG_GREEN_LED, 1);
 }
diff --git a/board/ronetix/pm9263/pm9263.c b/board/ronetix/pm9263/pm9263.c
index 48eba99d00..3aaffa803c 100644
--- a/board/ronetix/pm9263/pm9263.c
+++ b/board/ronetix/pm9263/pm9263.c
@@ -9,8 +9,9 @@
  */
 
 #include <common.h>
-#include <asm/sizes.h>
+#include <linux/sizes.h>
 #include <asm/io.h>
+#include <asm/gpio.h>
 #include <asm/arch/at91sam9_smc.h>
 #include <asm/arch/at91_common.h>
 #include <asm/arch/at91_pmc.h>
@@ -67,10 +68,10 @@ static void pm9263_nand_hw_init(void)
 		&smc->cs[3].mode);
 
 	/* Configure RDY/BSY */
-	at91_set_pio_input(CONFIG_SYS_NAND_READY_PIN, 1);
+	gpio_direction_input(CONFIG_SYS_NAND_READY_PIN);
 
 	/* Enable NandFlash */
-	at91_set_pio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
+	gpio_direction_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
 }
 #endif
 
diff --git a/board/ronetix/pm9g45/Makefile b/board/ronetix/pm9g45/Makefile
index 2810fcf8d7..0a00279900 100644
--- a/board/ronetix/pm9g45/Makefile
+++ b/board/ronetix/pm9g45/Makefile
@@ -9,24 +9,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS-y += pm9g45.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS-y))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
-	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y += pm9g45.o
diff --git a/board/ronetix/pm9g45/pm9g45.c b/board/ronetix/pm9g45/pm9g45.c
index 5bb5a3c102..15aa4acd11 100644
--- a/board/ronetix/pm9g45/pm9g45.c
+++ b/board/ronetix/pm9g45/pm9g45.c
@@ -12,8 +12,9 @@
  */
 
 #include <common.h>
-#include <asm/sizes.h>
+#include <linux/sizes.h>
 #include <asm/io.h>
+#include <asm/gpio.h>
 #include <asm/arch/at91sam9_smc.h>
 #include <asm/arch/at91_common.h>
 #include <asm/arch/at91_pmc.h>
@@ -66,11 +67,11 @@ static void pm9g45_nand_hw_init(void)
 
 #ifdef CONFIG_SYS_NAND_READY_PIN
 	/* Configure RDY/BSY */
-	at91_set_pio_input(CONFIG_SYS_NAND_READY_PIN, 1);
+	gpio_direction_input(CONFIG_SYS_NAND_READY_PIN);
 #endif
 
 	/* Enable NandFlash */
-	at91_set_pio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
+	gpio_direction_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
 }
 #endif
 
diff --git a/board/rpxsuper/Makefile b/board/rpxsuper/Makefile
index 3c08959dc5..239b419ab2 100644
--- a/board/rpxsuper/Makefile
+++ b/board/rpxsuper/Makefile
@@ -5,24 +5,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	:= rpxsuper.o flash.o mii_phy.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	:= rpxsuper.o flash.o mii_phy.o
diff --git a/board/rsdproto/Makefile b/board/rsdproto/Makefile
index 8799b50b0a..9351e94e74 100644
--- a/board/rsdproto/Makefile
+++ b/board/rsdproto/Makefile
@@ -5,25 +5,5 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	:= rsdproto.o flash.o
-SOBJS	:= flash_asm.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
-	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	:= rsdproto.o flash.o
+obj-y	+= flash_asm.o
diff --git a/board/sacsng/Makefile b/board/sacsng/Makefile
index 940a0168fd..95e6b8d0c4 100644
--- a/board/sacsng/Makefile
+++ b/board/sacsng/Makefile
@@ -5,24 +5,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	:= sacsng.o flash.o clkinit.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	:= sacsng.o flash.o clkinit.o
diff --git a/board/samsung/arndale/Makefile b/board/samsung/arndale/Makefile
index afd8db3cee..be2b3662ad 100644
--- a/board/samsung/arndale/Makefile
+++ b/board/samsung/arndale/Makefile
@@ -4,31 +4,8 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	+= arndale_spl.o
+obj-y	+= arndale_spl.o
 
 ifndef CONFIG_SPL_BUILD
-COBJS	+= arndale.o
+obj-y	+= arndale.o
 endif
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS) $(SOBJS))
-
-ALL	:=	 $(obj).depend $(LIB)
-
-all:	$(ALL)
-
-$(LIB):	$(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
diff --git a/board/samsung/arndale/arndale.c b/board/samsung/arndale/arndale.c
index 052fecdd5b..9efc355dab 100644
--- a/board/samsung/arndale/arndale.c
+++ b/board/samsung/arndale/arndale.c
@@ -5,12 +5,33 @@
  */
 
 #include <common.h>
+#include <usb.h>
 #include <asm/arch/pinmux.h>
 #include <asm/arch/dwmmc.h>
+#include <asm/arch/gpio.h>
 #include <asm/arch/power.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
+#ifdef CONFIG_USB_EHCI_EXYNOS
+int board_usb_init(int index, enum usb_init_type init)
+{
+	struct exynos5_gpio_part1 *gpio = (struct exynos5_gpio_part1 *)
+						samsung_get_base_gpio_part1();
+
+	/* Configure gpios for usb 3503 hub:
+	 * disconnect, toggle reset and connect
+	 */
+	s5p_gpio_direction_output(&gpio->d1, 7, 0);
+	s5p_gpio_direction_output(&gpio->x3, 5, 0);
+
+	s5p_gpio_direction_output(&gpio->x3, 5, 1);
+	s5p_gpio_direction_output(&gpio->d1, 7, 1);
+
+	return 0;
+}
+#endif
+
 int board_init(void)
 {
 	gd->bd->bi_boot_params = (PHYS_SDRAM_1 + 0x100UL);
diff --git a/board/samsung/common/Makefile b/board/samsung/common/Makefile
index 9e48a7b6e5..7d2bb8c4a2 100644
--- a/board/samsung/common/Makefile
+++ b/board/samsung/common/Makefile
@@ -5,23 +5,11 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)libsamsung.o
-
-COBJS-$(CONFIG_SOFT_I2C_MULTI_BUS) += multi_i2c.o
-
-SRCS    := $(COBJS-y:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS-y))
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-$(CONFIG_SOFT_I2C_MULTI_BUS) += multi_i2c.o
+obj-$(CONFIG_THOR_FUNCTION) += thor.o
+obj-$(CONFIG_CMD_USB_MASS_STORAGE) += ums.o
+obj-$(CONFIG_MISC_COMMON) += misc.o
+
+ifndef CONFIG_SPL_BUILD
+obj-$(CONFIG_BOARD_COMMON)	+= board.o
+endif
diff --git a/board/samsung/common/board.c b/board/samsung/common/board.c
new file mode 100644
index 0000000000..de154e0f64
--- /dev/null
+++ b/board/samsung/common/board.c
@@ -0,0 +1,324 @@
+/*
+ * (C) Copyright 2013 SAMSUNG Electronics
+ * Rajeshwari Shinde <rajeshwari.s@samsung.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <cros_ec.h>
+#include <errno.h>
+#include <fdtdec.h>
+#include <spi.h>
+#include <tmu.h>
+#include <netdev.h>
+#include <asm/io.h>
+#include <asm/arch/board.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/dwmmc.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/mmc.h>
+#include <asm/arch/pinmux.h>
+#include <asm/arch/power.h>
+#include <power/pmic.h>
+#include <asm/arch/sromc.h>
+#include <lcd.h>
+#include <samsung/misc.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int __exynos_early_init_f(void)
+{
+	return 0;
+}
+int exynos_early_init_f(void)
+	__attribute__((weak, alias("__exynos_early_init_f")));
+
+int __exynos_power_init(void)
+{
+	return 0;
+}
+int exynos_power_init(void)
+	__attribute__((weak, alias("__exynos_power_init")));
+
+#if defined CONFIG_EXYNOS_TMU
+/* Boot Time Thermal Analysis for SoC temperature threshold breach */
+static void boot_temp_check(void)
+{
+	int temp;
+
+	switch (tmu_monitor(&temp)) {
+	case TMU_STATUS_NORMAL:
+		break;
+	case TMU_STATUS_TRIPPED:
+		/*
+		 * Status TRIPPED ans WARNING means corresponding threshold
+		 * breach
+		 */
+		puts("EXYNOS_TMU: TRIPPING! Device power going down ...\n");
+		set_ps_hold_ctrl();
+		hang();
+		break;
+	case TMU_STATUS_WARNING:
+		puts("EXYNOS_TMU: WARNING! Temperature very high\n");
+		break;
+	case TMU_STATUS_INIT:
+		/*
+		 * TMU_STATUS_INIT means something is wrong with temperature
+		 * sensing and TMU status was changed back from NORMAL to INIT.
+		 */
+		puts("EXYNOS_TMU: WARNING! Temperature sensing not done\n");
+		break;
+	default:
+		debug("EXYNOS_TMU: Unknown TMU state\n");
+	}
+}
+#endif
+
+int board_init(void)
+{
+	gd->bd->bi_boot_params = (PHYS_SDRAM_1 + 0x100UL);
+#if defined CONFIG_EXYNOS_TMU
+	if (tmu_init(gd->fdt_blob) != TMU_STATUS_NORMAL) {
+		debug("%s: Failed to init TMU\n", __func__);
+		return -1;
+	}
+	boot_temp_check();
+#endif
+
+#ifdef CONFIG_EXYNOS_SPI
+	spi_init();
+#endif
+	return exynos_init();
+}
+
+int dram_init(void)
+{
+	int i;
+	u32 addr;
+
+	for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
+		addr = CONFIG_SYS_SDRAM_BASE + (i * SDRAM_BANK_SIZE);
+		gd->ram_size += get_ram_size((long *)addr, SDRAM_BANK_SIZE);
+	}
+	return 0;
+}
+
+void dram_init_banksize(void)
+{
+	int i;
+	u32 addr, size;
+
+	for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
+		addr = CONFIG_SYS_SDRAM_BASE + (i * SDRAM_BANK_SIZE);
+		size = get_ram_size((long *)addr, SDRAM_BANK_SIZE);
+
+		gd->bd->bi_dram[i].start = addr;
+		gd->bd->bi_dram[i].size = size;
+	}
+}
+
+static int board_uart_init(void)
+{
+	int err, uart_id, ret = 0;
+
+	for (uart_id = PERIPH_ID_UART0; uart_id <= PERIPH_ID_UART3; uart_id++) {
+		err = exynos_pinmux_config(uart_id, PINMUX_FLAG_NONE);
+		if (err) {
+			debug("UART%d not configured\n",
+			      (uart_id - PERIPH_ID_UART0));
+			ret |= err;
+		}
+	}
+	return ret;
+}
+
+#ifdef CONFIG_BOARD_EARLY_INIT_F
+int board_early_init_f(void)
+{
+	int err;
+
+	err = board_uart_init();
+	if (err) {
+		debug("UART init failed\n");
+		return err;
+	}
+
+#ifdef CONFIG_SYS_I2C_INIT_BOARD
+	board_i2c_init(gd->fdt_blob);
+#endif
+
+	return exynos_early_init_f();
+}
+#endif
+
+#if defined(CONFIG_POWER)
+int power_init_board(void)
+{
+	set_ps_hold_ctrl();
+
+	return exynos_power_init();
+}
+#endif
+
+#ifdef CONFIG_OF_CONTROL
+#ifdef CONFIG_SMC911X
+static int decode_sromc(const void *blob, struct fdt_sromc *config)
+{
+	int err;
+	int node;
+
+	node = fdtdec_next_compatible(blob, 0, COMPAT_SAMSUNG_EXYNOS5_SROMC);
+	if (node < 0) {
+		debug("Could not find SROMC node\n");
+		return node;
+	}
+
+	config->bank = fdtdec_get_int(blob, node, "bank", 0);
+	config->width = fdtdec_get_int(blob, node, "width", 2);
+
+	err = fdtdec_get_int_array(blob, node, "srom-timing", config->timing,
+			FDT_SROM_TIMING_COUNT);
+	if (err < 0) {
+		debug("Could not decode SROMC configuration Error: %s\n",
+		      fdt_strerror(err));
+		return -FDT_ERR_NOTFOUND;
+	}
+	return 0;
+}
+#endif
+
+int board_eth_init(bd_t *bis)
+{
+#ifdef CONFIG_SMC911X
+	u32 smc_bw_conf, smc_bc_conf;
+	struct fdt_sromc config;
+	fdt_addr_t base_addr;
+	int node;
+
+	node = decode_sromc(gd->fdt_blob, &config);
+	if (node < 0) {
+		debug("%s: Could not find sromc configuration\n", __func__);
+		return 0;
+	}
+	node = fdtdec_next_compatible(gd->fdt_blob, node, COMPAT_SMSC_LAN9215);
+	if (node < 0) {
+		debug("%s: Could not find lan9215 configuration\n", __func__);
+		return 0;
+	}
+
+	/* We now have a node, so any problems from now on are errors */
+	base_addr = fdtdec_get_addr(gd->fdt_blob, node, "reg");
+	if (base_addr == FDT_ADDR_T_NONE) {
+		debug("%s: Could not find lan9215 address\n", __func__);
+		return -1;
+	}
+
+	/* Ethernet needs data bus width of 16 bits */
+	if (config.width != 2) {
+		debug("%s: Unsupported bus width %d\n", __func__,
+		      config.width);
+		return -1;
+	}
+	smc_bw_conf = SROMC_DATA16_WIDTH(config.bank)
+			| SROMC_BYTE_ENABLE(config.bank);
+
+	smc_bc_conf = SROMC_BC_TACS(config.timing[FDT_SROM_TACS])   |
+			SROMC_BC_TCOS(config.timing[FDT_SROM_TCOS]) |
+			SROMC_BC_TACC(config.timing[FDT_SROM_TACC]) |
+			SROMC_BC_TCOH(config.timing[FDT_SROM_TCOH]) |
+			SROMC_BC_TAH(config.timing[FDT_SROM_TAH])   |
+			SROMC_BC_TACP(config.timing[FDT_SROM_TACP]) |
+			SROMC_BC_PMC(config.timing[FDT_SROM_PMC]);
+
+	/* Select and configure the SROMC bank */
+	exynos_pinmux_config(PERIPH_ID_SROMC, config.bank);
+	s5p_config_sromc(config.bank, smc_bw_conf, smc_bc_conf);
+	return smc911x_initialize(0, base_addr);
+#endif
+	return 0;
+}
+
+#ifdef CONFIG_GENERIC_MMC
+int board_mmc_init(bd_t *bis)
+{
+	int ret;
+
+#ifdef CONFIG_SDHCI
+	/* mmc initializattion for available channels */
+	ret = exynos_mmc_init(gd->fdt_blob);
+	if (ret)
+		debug("mmc init failed\n");
+#endif
+#ifdef CONFIG_DWMMC
+	/* dwmmc initializattion for available channels */
+	ret = exynos_dwmmc_init(gd->fdt_blob);
+	if (ret)
+		debug("dwmmc init failed\n");
+#endif
+
+	return ret;
+}
+#endif
+
+#ifdef CONFIG_DISPLAY_BOARDINFO
+int checkboard(void)
+{
+	const char *board_name;
+
+	board_name = fdt_getprop(gd->fdt_blob, 0, "model", NULL);
+	printf("Board: %s\n", board_name ? board_name : "unknown");
+
+	return 0;
+}
+#endif
+#endif /* CONFIG_OF_CONTROL */
+
+#ifdef CONFIG_BOARD_LATE_INIT
+int board_late_init(void)
+{
+	stdio_print_current_devices();
+
+	if (cros_ec_get_error()) {
+		/* Force console on */
+		gd->flags &= ~GD_FLG_SILENT;
+
+		printf("cros-ec communications failure %d\n",
+		       cros_ec_get_error());
+		puts("\nPlease reset with Power+Refresh\n\n");
+		panic("Cannot init cros-ec device");
+		return -1;
+	}
+	return 0;
+}
+#endif
+
+int arch_early_init_r(void)
+{
+#ifdef CONFIG_CROS_EC
+	if (cros_ec_board_init()) {
+		printf("%s: Failed to init EC\n", __func__);
+		return 0;
+	}
+#endif
+
+	return 0;
+}
+
+#ifdef CONFIG_MISC_INIT_R
+int misc_init_r(void)
+{
+#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+	set_board_info();
+#endif
+#ifdef CONFIG_LCD_MENU
+	keys_init();
+	check_boot_mode();
+#endif
+#ifdef CONFIG_CMD_BMP
+	if (panel_info.logo_on)
+		draw_logo();
+#endif
+	return 0;
+}
+#endif
diff --git a/board/samsung/common/dfu_sample_env.txt b/board/samsung/common/dfu_sample_env.txt
new file mode 100644
index 0000000000..d6ee8a228a
--- /dev/null
+++ b/board/samsung/common/dfu_sample_env.txt
@@ -0,0 +1,9 @@
+mmcboot=setenv bootargs root=/dev/mmcblk${mmcdev}p${mmcrootpart} ${rootfstype} rootwait ${console}; run loaduimage; bootm 0x40007FC0
+rootfstype=ext4
+loaduimage=ext4load mmc ${mmcdev}:${mmcbootpart} 0x40007FC0 uImage
+mmcdev=0
+mmcbootpart=2
+mmcrootpart=5
+console=console=ttySAC2,115200n8
+bootcmd=run mmcboot
+dfu_alt_info=u-boot mmc 80 800;params.bin mmc 0x38 0x8;uImage ext4 0 2
diff --git a/board/samsung/common/exynos-uboot-spl.lds b/board/samsung/common/exynos-uboot-spl.lds
index 8e3b73ecf7..b22f9e07bb 100644
--- a/board/samsung/common/exynos-uboot-spl.lds
+++ b/board/samsung/common/exynos-uboot-spl.lds
@@ -42,7 +42,11 @@ SECTIONS
 	. = ALIGN(4);
 
 	__image_copy_end = .;
-	_end = .;
+
+	.end :
+	{
+		*(.__end)
+	} >.sram
 
 	.bss :
 	{
diff --git a/board/samsung/common/misc.c b/board/samsung/common/misc.c
new file mode 100644
index 0000000000..3ff4289780
--- /dev/null
+++ b/board/samsung/common/misc.c
@@ -0,0 +1,411 @@
+/*
+ * Copyright (C) 2013 Samsung Electronics
+ * Przemyslaw Marczak <p.marczak@samsung.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <lcd.h>
+#include <libtizen.h>
+#include <samsung/misc.h>
+#include <errno.h>
+#include <version.h>
+#include <linux/sizes.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/gpio.h>
+#include <asm/gpio.h>
+#include <linux/input.h>
+#include <power/pmic.h>
+#include <mmc.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+void set_board_info(void)
+{
+	char info[64];
+
+	snprintf(info, ARRAY_SIZE(info), "%d.%d", s5p_cpu_rev & 0x0f,
+		 (s5p_cpu_rev & 0xf0) >> 0x04);
+	setenv("soc_rev", info);
+
+	snprintf(info, ARRAY_SIZE(info), "%x", s5p_cpu_id);
+	setenv("soc_id", info);
+
+#ifdef CONFIG_REVISION_TAG
+	snprintf(info, ARRAY_SIZE(info), "%x", get_board_rev());
+	setenv("board_rev", info);
+#endif
+#ifdef CONFIG_OF_LIBFDT
+	snprintf(info, ARRAY_SIZE(info),  "%s%x-%s.dtb",
+		 CONFIG_SYS_SOC, s5p_cpu_id, CONFIG_SYS_BOARD);
+	setenv("fdtfile", info);
+#endif
+}
+#endif /* CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG */
+
+#ifdef CONFIG_LCD_MENU
+static int power_key_pressed(u32 reg)
+{
+	struct pmic *pmic;
+	u32 status;
+	u32 mask;
+
+	pmic = pmic_get(KEY_PWR_PMIC_NAME);
+	if (!pmic) {
+		printf("%s: Not found\n", KEY_PWR_PMIC_NAME);
+		return 0;
+	}
+
+	if (pmic_probe(pmic))
+		return 0;
+
+	if (reg == KEY_PWR_STATUS_REG)
+		mask = KEY_PWR_STATUS_MASK;
+	else
+		mask = KEY_PWR_INTERRUPT_MASK;
+
+	if (pmic_reg_read(pmic, reg, &status))
+		return 0;
+
+	return !!(status & mask);
+}
+
+static int key_pressed(int key)
+{
+	int value;
+
+	switch (key) {
+	case KEY_POWER:
+		value = power_key_pressed(KEY_PWR_INTERRUPT_REG);
+		break;
+	case KEY_VOLUMEUP:
+		value = !gpio_get_value(KEY_VOL_UP_GPIO);
+		break;
+	case KEY_VOLUMEDOWN:
+		value = !gpio_get_value(KEY_VOL_DOWN_GPIO);
+		break;
+	default:
+		value = 0;
+		break;
+	}
+
+	return value;
+}
+
+static int check_keys(void)
+{
+	int keys = 0;
+
+	if (key_pressed(KEY_POWER))
+		keys += KEY_POWER;
+	if (key_pressed(KEY_VOLUMEUP))
+		keys += KEY_VOLUMEUP;
+	if (key_pressed(KEY_VOLUMEDOWN))
+		keys += KEY_VOLUMEDOWN;
+
+	return keys;
+}
+
+/*
+ * 0 BOOT_MODE_INFO
+ * 1 BOOT_MODE_THOR
+ * 2 BOOT_MODE_UMS
+ * 3 BOOT_MODE_DFU
+ * 4 BOOT_MODE_EXIT
+ */
+static char *
+mode_name[BOOT_MODE_EXIT + 1] = {
+	"DEVICE",
+	"THOR",
+	"UMS",
+	"DFU",
+	"EXIT"
+};
+
+static char *
+mode_info[BOOT_MODE_EXIT + 1] = {
+	"info",
+	"downloader",
+	"mass storage",
+	"firmware update",
+	"and run normal boot"
+};
+
+#define MODE_CMD_ARGC	4
+
+static char *
+mode_cmd[BOOT_MODE_EXIT + 1][MODE_CMD_ARGC] = {
+	{"", "", "", ""},
+	{"thor", "0", "mmc", "0"},
+	{"ums", "0", "mmc", "0"},
+	{"dfu", "0", "mmc", "0"},
+	{"", "", "", ""},
+};
+
+static void display_board_info(void)
+{
+#ifdef CONFIG_GENERIC_MMC
+	struct mmc *mmc = find_mmc_device(0);
+#endif
+	vidinfo_t *vid = &panel_info;
+
+	lcd_position_cursor(4, 4);
+
+	lcd_printf("%s\n\t", U_BOOT_VERSION);
+	lcd_puts("\n\t\tBoard Info:\n");
+#ifdef CONFIG_SYS_BOARD
+	lcd_printf("\tBoard name: %s\n", CONFIG_SYS_BOARD);
+#endif
+#ifdef CONFIG_REVISION_TAG
+	lcd_printf("\tBoard rev: %u\n", get_board_rev());
+#endif
+	lcd_printf("\tDRAM banks: %u\n", CONFIG_NR_DRAM_BANKS);
+	lcd_printf("\tDRAM size: %u MB\n", gd->ram_size / SZ_1M);
+
+#ifdef CONFIG_GENERIC_MMC
+	if (mmc) {
+		if (!mmc->capacity)
+			mmc_init(mmc);
+
+		lcd_printf("\teMMC size: %llu MB\n", mmc->capacity / SZ_1M);
+	}
+#endif
+	if (vid)
+		lcd_printf("\tDisplay resolution: %u x % u\n",
+			   vid->vl_col, vid->vl_row);
+
+	lcd_printf("\tDisplay BPP: %u\n", 1 << vid->vl_bpix);
+}
+
+static int mode_leave_menu(int mode)
+{
+	char *exit_option;
+	char *exit_boot = "boot";
+	char *exit_back = "back";
+	cmd_tbl_t *cmd;
+	int cmd_result;
+	int cmd_repeatable;
+	int leave;
+
+	lcd_clear();
+
+	switch (mode) {
+	case BOOT_MODE_EXIT:
+		return 1;
+	case BOOT_MODE_INFO:
+		display_board_info();
+		exit_option = exit_back;
+		leave = 0;
+		break;
+	default:
+		cmd = find_cmd(mode_cmd[mode][0]);
+		if (cmd) {
+			printf("Enter: %s %s\n", mode_name[mode],
+						 mode_info[mode]);
+			lcd_printf("\n\n\t%s %s\n", mode_name[mode],
+						    mode_info[mode]);
+			lcd_puts("\n\tDo not turn off device before finish!\n");
+
+			cmd_result = cmd_process(0, MODE_CMD_ARGC,
+						 *(mode_cmd + mode),
+						 &cmd_repeatable, NULL);
+
+			if (cmd_result == CMD_RET_SUCCESS) {
+				printf("Command finished\n");
+				lcd_clear();
+				lcd_printf("\n\n\t%s finished\n",
+					   mode_name[mode]);
+
+				exit_option = exit_boot;
+				leave = 1;
+			} else {
+				printf("Command error\n");
+				lcd_clear();
+				lcd_printf("\n\n\t%s command error\n",
+					   mode_name[mode]);
+
+				exit_option = exit_back;
+				leave = 0;
+			}
+		} else {
+			lcd_puts("\n\n\tThis mode is not supported.\n");
+			exit_option = exit_back;
+			leave = 0;
+		}
+	}
+
+	lcd_printf("\n\n\tPress POWER KEY to %s\n", exit_option);
+
+	/* Clear PWR button Rising edge interrupt status flag */
+	power_key_pressed(KEY_PWR_INTERRUPT_REG);
+
+	/* Wait for PWR key */
+	while (!key_pressed(KEY_POWER))
+		mdelay(1);
+
+	lcd_clear();
+	return leave;
+}
+
+static void display_download_menu(int mode)
+{
+	char *selection[BOOT_MODE_EXIT + 1];
+	int i;
+
+	for (i = 0; i <= BOOT_MODE_EXIT; i++)
+		selection[i] = "[  ]";
+
+	selection[mode] = "[=>]";
+
+	lcd_clear();
+	lcd_printf("\n\t\tDownload Mode Menu\n");
+
+	for (i = 0; i <= BOOT_MODE_EXIT; i++)
+		lcd_printf("\t%s  %s - %s\n\n", selection[i],
+						mode_name[i],
+						mode_info[i]);
+}
+
+static void download_menu(void)
+{
+	int mode = 0;
+	int last_mode = 0;
+	int run;
+	int key;
+
+	display_download_menu(mode);
+
+	while (1) {
+		run = 0;
+
+		if (mode != last_mode)
+			display_download_menu(mode);
+
+		last_mode = mode;
+		mdelay(100);
+
+		key = check_keys();
+		switch (key) {
+		case KEY_POWER:
+			run = 1;
+			break;
+		case KEY_VOLUMEUP:
+			if (mode > 0)
+				mode--;
+			break;
+		case KEY_VOLUMEDOWN:
+			if (mode < BOOT_MODE_EXIT)
+				mode++;
+			break;
+		default:
+			break;
+		}
+
+		if (run) {
+			if (mode_leave_menu(mode))
+				break;
+
+			display_download_menu(mode);
+		}
+	}
+
+	lcd_clear();
+}
+
+static void display_mode_info(void)
+{
+	lcd_position_cursor(4, 4);
+	lcd_printf("%s\n", U_BOOT_VERSION);
+	lcd_puts("\nDownload Mode Menu\n");
+#ifdef CONFIG_SYS_BOARD
+	lcd_printf("Board name: %s\n", CONFIG_SYS_BOARD);
+#endif
+	lcd_printf("Press POWER KEY to display MENU options.");
+}
+
+static int boot_menu(void)
+{
+	int key = 0;
+	int timeout = 10;
+
+	display_mode_info();
+
+	while (timeout--) {
+		lcd_printf("\rNormal boot will start in: %d seconds.", timeout);
+		mdelay(1000);
+
+		key = key_pressed(KEY_POWER);
+		if (key)
+			break;
+	}
+
+	lcd_clear();
+
+	/* If PWR pressed - show download menu */
+	if (key) {
+		printf("Power pressed - go to download menu\n");
+		download_menu();
+		printf("Download mode exit.\n");
+	}
+
+	return 0;
+}
+
+void check_boot_mode(void)
+{
+	int pwr_key;
+
+	pwr_key = power_key_pressed(KEY_PWR_STATUS_REG);
+	if (!pwr_key)
+		return;
+
+	/* Clear PWR button Rising edge interrupt status flag */
+	power_key_pressed(KEY_PWR_INTERRUPT_REG);
+
+	if (key_pressed(KEY_VOLUMEUP))
+		boot_menu();
+	else if (key_pressed(KEY_VOLUMEDOWN))
+		mode_leave_menu(BOOT_MODE_THOR);
+}
+
+void keys_init(void)
+{
+	/* Set direction to input */
+	gpio_direction_input(KEY_VOL_UP_GPIO);
+	gpio_direction_input(KEY_VOL_DOWN_GPIO);
+}
+#endif /* CONFIG_LCD_MENU */
+
+#ifdef CONFIG_CMD_BMP
+void draw_logo(void)
+{
+	int x, y;
+	ulong addr;
+
+	addr = panel_info.logo_addr;
+	if (!addr) {
+		error("There is no logo data.");
+		return;
+	}
+
+	if (panel_info.vl_width >= panel_info.logo_width) {
+		x = ((panel_info.vl_width - panel_info.logo_width) >> 1);
+		x += panel_info.logo_x_offset; /* For X center align */
+	} else {
+		x = 0;
+		printf("Warning: image width is bigger than display width\n");
+	}
+
+	if (panel_info.vl_height >= panel_info.logo_height) {
+		y = ((panel_info.vl_height - panel_info.logo_height) >> 1);
+		y += panel_info.logo_y_offset; /* For Y center align */
+	} else {
+		y = 0;
+		printf("Warning: image height is bigger than display height\n");
+	}
+
+	bmp_display(addr, x, y);
+}
+#endif /* CONFIG_CMD_BMP */
diff --git a/board/samsung/common/thor.c b/board/samsung/common/thor.c
new file mode 100644
index 0000000000..1c7630df08
--- /dev/null
+++ b/board/samsung/common/thor.c
@@ -0,0 +1,21 @@
+/*
+ *  Copyright (C) 2013 Samsung Electronics
+ *  Lukasz Majewski <l.majewski@samsung.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <linux/usb/ch9.h>
+
+int g_dnl_bind_fixup(struct usb_device_descriptor *dev, const char *name)
+{
+	if (!strcmp(name, "usb_dnl_thor")) {
+		put_unaligned(CONFIG_G_DNL_THOR_VENDOR_NUM, &dev->idVendor);
+		put_unaligned(CONFIG_G_DNL_THOR_PRODUCT_NUM, &dev->idProduct);
+	} else {
+		put_unaligned(CONFIG_G_DNL_VENDOR_NUM, &dev->idVendor);
+		put_unaligned(CONFIG_G_DNL_PRODUCT_NUM, &dev->idProduct);
+	}
+	return 0;
+}
diff --git a/board/samsung/common/ums.c b/board/samsung/common/ums.c
new file mode 100644
index 0000000000..dc155ad0e5
--- /dev/null
+++ b/board/samsung/common/ums.c
@@ -0,0 +1,76 @@
+/*
+ * Copyright (C) 2013 Samsung Electronics
+ * Lukasz Majewski <l.majewski@samsung.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <usb_mass_storage.h>
+#include <part.h>
+
+static int ums_read_sector(struct ums *ums_dev,
+			   ulong start, lbaint_t blkcnt, void *buf)
+{
+	block_dev_desc_t *block_dev = &ums_dev->mmc->block_dev;
+	lbaint_t blkstart = start + ums_dev->start_sector;
+	int dev_num = block_dev->dev;
+
+	return block_dev->block_read(dev_num, blkstart, blkcnt, buf);
+}
+
+static int ums_write_sector(struct ums *ums_dev,
+			    ulong start, lbaint_t blkcnt, const void *buf)
+{
+	block_dev_desc_t *block_dev = &ums_dev->mmc->block_dev;
+	lbaint_t blkstart = start + ums_dev->start_sector;
+	int dev_num = block_dev->dev;
+
+	return block_dev->block_write(dev_num, blkstart, blkcnt, buf);
+}
+
+static struct ums ums_dev = {
+	.read_sector = ums_read_sector,
+	.write_sector = ums_write_sector,
+	.name = "UMS disk",
+};
+
+static struct ums *ums_disk_init(struct mmc *mmc)
+{
+	uint64_t mmc_end_sector = mmc->capacity / SECTOR_SIZE;
+	uint64_t ums_end_sector = UMS_NUM_SECTORS + UMS_START_SECTOR;
+
+	if (!mmc_end_sector) {
+		error("MMC capacity is not valid");
+		return NULL;
+	}
+
+	ums_dev.mmc = mmc;
+
+	if (ums_end_sector <= mmc_end_sector) {
+		ums_dev.start_sector = UMS_START_SECTOR;
+		if (UMS_NUM_SECTORS)
+			ums_dev.num_sectors = UMS_NUM_SECTORS;
+		else
+			ums_dev.num_sectors = mmc_end_sector - UMS_START_SECTOR;
+	} else {
+		ums_dev.num_sectors = mmc_end_sector;
+		puts("UMS: defined bad disk parameters. Using default.\n");
+	}
+
+	printf("UMS: disk start sector: %#x, count: %#x\n",
+	       ums_dev.start_sector, ums_dev.num_sectors);
+
+	return &ums_dev;
+}
+
+struct ums *ums_init(unsigned int dev_num)
+{
+	struct mmc *mmc = NULL;
+
+	mmc = find_mmc_device(dev_num);
+	if (!mmc)
+		return NULL;
+
+	return ums_disk_init(mmc);
+}
diff --git a/board/samsung/dts/exynos5250-smdk5250.dts b/board/samsung/dts/exynos5250-smdk5250.dts
deleted file mode 100644
index b1bba9662e..0000000000
--- a/board/samsung/dts/exynos5250-smdk5250.dts
+++ /dev/null
@@ -1,147 +0,0 @@
-/*
- * SAMSUNG SMDK5250 board device tree source
- *
- * Copyright (c) 2012 Samsung Electronics Co., Ltd.
- *		http://www.samsung.com
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-/dts-v1/;
-/include/ "exynos5250.dtsi"
-
-/ {
-	model = "SAMSUNG SMDK5250 board based on EXYNOS5250";
-	compatible = "samsung,smdk5250", "samsung,exynos5250";
-
-	aliases {
-		i2c0 = "/i2c@12c60000";
-		i2c1 = "/i2c@12c70000";
-		i2c2 = "/i2c@12c80000";
-		i2c3 = "/i2c@12c90000";
-		i2c4 = "/i2c@12ca0000";
-		i2c5 = "/i2c@12cb0000";
-		i2c6 = "/i2c@12cc0000";
-		i2c7 = "/i2c@12cd0000";
-		spi0 = "/spi@12d20000";
-		spi1 = "/spi@12d30000";
-		spi2 = "/spi@12d40000";
-		spi3 = "/spi@131a0000";
-		spi4 = "/spi@131b0000";
-		mmc0 = "/mmc@12200000";
-		mmc1 = "/mmc@12210000";
-		mmc2 = "/mmc@12220000";
-		mmc3 = "/mmc@12230000";
-		serial0 = "/serial@12C30000";
-		console = "/serial@12C30000";
-		i2s = "/sound@3830000";
-	};
-
-	sromc@12250000 {
-		bank = <1>;
-		srom-timing = <1 9 12 1 6 1 1>;
-		width = <2>;
-		lan@5000000 {
-			compatible = "smsc,lan9215", "smsc,lan";
-			reg = <0x5000000 0x100>;
-			phy-mode = "mii";
-		};
-	};
-
-	sound@3830000 {
-		samsung,codec-type = "wm8994";
-	};
-
-	sound@12d60000 {
-		status = "disabled";
-	};
-
-	i2c@12c70000 {
-		soundcodec@1a {
-			reg = <0x1a>;
-			compatible = "wolfson,wm8994-codec";
-		};
-	};
-
-	i2c@12c60000 {
-		pmic@9 {
-			reg = <0x9>;
-			compatible = "maxim,max77686_pmic";
-		};
-	};
-
-	tmu@10060000 {
-		samsung,min-temp	= <25>;
-		samsung,max-temp	= <125>;
-		samsung,start-warning	= <95>;
-		samsung,start-tripping	= <105>;
-		samsung,hw-tripping	= <110>;
-		samsung,efuse-min-value	= <40>;
-		samsung,efuse-value	= <55>;
-		samsung,efuse-max-value	= <100>;
-		samsung,slope		= <274761730>;
-		samsung,dc-value	= <25>;
-	};
-
-	fimd@14400000 {
-		samsung,vl-freq = <60>;
-		samsung,vl-col = <2560>;
-		samsung,vl-row = <1600>;
-		samsung,vl-width = <2560>;
-		samsung,vl-height = <1600>;
-
-		samsung,vl-clkp;
-		samsung,vl-dp;
-		samsung,vl-bpix = <4>;
-
-		samsung,vl-hspw = <32>;
-		samsung,vl-hbpd = <80>;
-		samsung,vl-hfpd = <48>;
-		samsung,vl-vspw = <6>;
-		samsung,vl-vbpd = <37>;
-		samsung,vl-vfpd = <3>;
-		samsung,vl-cmd-allow-len = <0xf>;
-
-		samsung,winid = <3>;
-		samsung,interface-mode = <1>;
-		samsung,dp-enabled = <1>;
-		samsung,dual-lcd-enabled = <0>;
-	};
-
-	dp@145b0000 {
-		samsung,lt-status = <0>;
-
-		samsung,master-mode = <0>;
-		samsung,bist-mode = <0>;
-		samsung,bist-pattern = <0>;
-		samsung,h-sync-polarity = <0>;
-		samsung,v-sync-polarity = <0>;
-		samsung,interlaced = <0>;
-		samsung,color-space = <0>;
-		samsung,dynamic-range = <0>;
-		samsung,ycbcr-coeff = <0>;
-		samsung,color-depth = <1>;
-	};
-
-	mmc@12200000 {
-		samsung,bus-width = <8>;
-		samsung,timing = <1 3 3>;
-		samsung,removable = <0>;
-	};
-
-	mmc@12210000 {
-		status = "disabled";
-	};
-
-	mmc@12220000 {
-		samsung,bus-width = <4>;
-		samsung,timing = <1 2 3>;
-		samsung,removable = <1>;
-	};
-
-	mmc@12230000 {
-		status = "disabled";
-	};
-};
diff --git a/board/samsung/dts/exynos5250-snow.dts b/board/samsung/dts/exynos5250-snow.dts
deleted file mode 100644
index 12cd67e49c..0000000000
--- a/board/samsung/dts/exynos5250-snow.dts
+++ /dev/null
@@ -1,179 +0,0 @@
-/*
- * SAMSUNG Snow board device tree source
- *
- * Copyright (c) 2012 Samsung Electronics Co., Ltd.
- *		http://www.samsung.com
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-/dts-v1/;
-/include/ "exynos5250.dtsi"
-
-/ {
-	model = "Google Snow";
-	compatible = "google,snow", "samsung,exynos5250";
-
-	aliases {
-		i2c0 = "/i2c@12c60000";
-		i2c1 = "/i2c@12c70000";
-		i2c2 = "/i2c@12c80000";
-		i2c3 = "/i2c@12c90000";
-		i2c4 = "/i2c@12ca0000";
-		i2c5 = "/i2c@12cb0000";
-		i2c6 = "/i2c@12cc0000";
-		i2c7 = "/i2c@12cd0000";
-		spi0 = "/spi@12d20000";
-		spi1 = "/spi@12d30000";
-		spi2 = "/spi@12d40000";
-		spi3 = "/spi@131a0000";
-		spi4 = "/spi@131b0000";
-		mmc0 = "/mmc@12200000";
-		mmc1 = "/mmc@12210000";
-		mmc2 = "/mmc@12220000";
-		mmc3 = "/mmc@12230000";
-		serial0 = "/serial@12C30000";
-		console = "/serial@12C30000";
-		i2s = "/sound@3830000";
-	};
-
-	i2c4: i2c@12ca0000 {
-		cros-ec@1e {
-			reg = <0x1e>;
-			compatible = "google,cros-ec";
-			i2c-max-frequency = <100000>;
-			ec-interrupt = <&gpio 782 1>;
-		};
-
-		power-regulator@48 {
-			compatible = "ti,tps65090";
-			reg = <0x48>;
-		};
-	};
-
-	spi@131b0000 {
-		spi-max-frequency = <1000000>;
-		spi-deactivate-delay = <100>;
-		cros-ec@0 {
-			reg = <0>;
-			compatible = "google,cros-ec";
-			spi-max-frequency = <5000000>;
-			ec-interrupt = <&gpio 782 1>;
-			optimise-flash-write;
-			status = "disabled";
-		};
-	};
-
-	sound@3830000 {
-		samsung,codec-type = "max98095";
-		codec-enable-gpio = <&gpio 0xb7 0>;
-	};
-
-	sound@12d60000 {
-		status = "disabled";
-	};
-
-	i2c@12cd0000 {
-		soundcodec@22 {
-			reg = <0x22>;
-			compatible = "maxim,max98095-codec";
-		};
-	};
-
-	i2c@12c60000 {
-		pmic@9 {
-			reg = <0x9>;
-			compatible = "maxim,max77686_pmic";
-		};
-	};
-
-	mmc@12200000 {
-		samsung,bus-width = <8>;
-		samsung,timing = <1 3 3>;
-		samsung,removable = <0>;
-	};
-
-	mmc@12210000 {
-		status = "disabled";
-	};
-
-	mmc@12220000 {
-		samsung,bus-width = <4>;
-		samsung,timing = <1 2 3>;
-		samsung,removable = <1>;
-	};
-
-	mmc@12230000 {
-		status = "disabled";
-	};
-
-	tmu@10060000 {
-		samsung,min-temp	= <25>;
-		samsung,max-temp	= <125>;
-		samsung,start-warning	= <95>;
-		samsung,start-tripping	= <105>;
-		samsung,hw-tripping	= <110>;
-		samsung,efuse-min-value	= <40>;
-		samsung,efuse-value	= <55>;
-		samsung,efuse-max-value	= <100>;
-		samsung,slope		= <274761730>;
-		samsung,dc-value	= <25>;
-	};
-
-	cros-ec-keyb {
-		compatible = "google,cros-ec-keyb";
-		google,key-rows = <8>;
-		google,key-columns = <13>;
-		google,repeat-delay-ms = <240>;
-		google,repeat-rate-ms = <30>;
-		google,ghost-filter;
-		/*
-		 * Keymap entries take the form of 0xRRCCKKKK where
-		 * RR=Row CC=Column KKKK=Key Code
-		 * The values below are for a US keyboard layout and
-		 * are taken from the Linux driver. Note that the
-		 * 102ND key is not used for US keyboards.
-		 */
-		linux,keymap = <
-			/* CAPSLCK F1         B          F10     */
-			0x0001003a 0x0002003b 0x00030030 0x00040044
-			/* N       =          R_ALT      ESC     */
-			0x00060031 0x0008000d 0x000a0064 0x01010001
-			/* F4      G          F7         H       */
-			0x0102003e 0x01030022 0x01040041 0x01060023
-			/* '       F9         BKSPACE    L_CTRL  */
-			0x01080028 0x01090043 0x010b000e 0x0200001d
-			/* TAB     F3         T          F6      */
-			0x0201000f 0x0202003d 0x02030014 0x02040040
-			/* ]       Y          102ND      [       */
-			0x0205001b 0x02060015 0x02070056 0x0208001a
-			/* F8      GRAVE      F2         5       */
-			0x02090042 0x03010029 0x0302003c 0x03030006
-			/* F5      6          -          \       */
-			0x0304003f 0x03060007 0x0308000c 0x030b002b
-			/* R_CTRL  A          D          F       */
-			0x04000061 0x0401001e 0x04020020 0x04030021
-			/* S       K          J          ;       */
-			0x0404001f 0x04050025 0x04060024 0x04080027
-			/* L       ENTER      Z          C       */
-			0x04090026 0x040b001c 0x0501002c 0x0502002e
-			/* V       X          ,          M       */
-			0x0503002f 0x0504002d 0x05050033 0x05060032
-			/* L_SHIFT /          .          SPACE   */
-			0x0507002a 0x05080035 0x05090034 0x050B0039
-			/* 1       3          4          2       */
-			0x06010002 0x06020004 0x06030005 0x06040003
-			/* 8       7          0          9       */
-			0x06050009 0x06060008 0x0608000b 0x0609000a
-			/* L_ALT   DOWN       RIGHT      Q       */
-			0x060a0038 0x060b006c 0x060c006a 0x07010010
-			/* E       R          W          I       */
-			0x07020012 0x07030013 0x07040011 0x07050017
-			/* U       R_SHIFT    P          O       */
-			0x07060016 0x07070036 0x07080019 0x07090018
-			/* UP      LEFT    */
-			0x070b0067 0x070c0069>;
-	};
-};
diff --git a/board/samsung/goni/Makefile b/board/samsung/goni/Makefile
index cd91d66076..2cdc21d851 100644
--- a/board/samsung/goni/Makefile
+++ b/board/samsung/goni/Makefile
@@ -8,25 +8,5 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS-y	:= goni.o onenand.o
-SOBJS	:= lowlevel_init.o
-
-SRCS    := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS-y))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(SOBJS) $(OBJS)
-	$(call cmd_link_o_target, $(SOBJS) $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	:= goni.o onenand.o
+obj-y	+= lowlevel_init.o
diff --git a/board/samsung/goni/goni.c b/board/samsung/goni/goni.c
index 366f648d32..61b9ece038 100644
--- a/board/samsung/goni/goni.c
+++ b/board/samsung/goni/goni.c
@@ -13,10 +13,17 @@
 #include <usb/s3c_udc.h>
 #include <asm/arch/cpu.h>
 #include <power/max8998_pmic.h>
+#include <samsung/misc.h>
+
 DECLARE_GLOBAL_DATA_PTR;
 
 static struct s5pc110_gpio *s5pc110_gpio;
 
+u32 get_board_rev(void)
+{
+	return 0;
+}
+
 int board_init(void)
 {
 	/* Set Initial global variables */
@@ -173,3 +180,13 @@ struct s3c_plat_otg_data s5pc110_otg_data = {
 	.usb_phy_ctrl = S5PC110_USB_PHY_CONTROL,
 };
 #endif
+
+#ifdef CONFIG_MISC_INIT_R
+int misc_init_r(void)
+{
+#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+	set_board_info();
+#endif
+	return 0;
+}
+#endif
diff --git a/board/samsung/goni/lowlevel_init.S b/board/samsung/goni/lowlevel_init.S
index 726211a336..d52bc09f8d 100644
--- a/board/samsung/goni/lowlevel_init.S
+++ b/board/samsung/goni/lowlevel_init.S
@@ -22,9 +22,6 @@
  * r9 has Mobile DDR size, 1 means 1GiB, 2 means 2GiB and so on
  */
 
-_TEXT_BASE:
-	.word	CONFIG_SYS_TEXT_BASE
-
 	.globl lowlevel_init
 lowlevel_init:
 	mov	r11, lr
diff --git a/board/samsung/origen/Makefile b/board/samsung/origen/Makefile
index 0b1ae1bb51..1add9fe626 100644
--- a/board/samsung/origen/Makefile
+++ b/board/samsung/origen/Makefile
@@ -4,38 +4,19 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-ifndef CONFIG_SPL_BUILD
-COBJS	+= origen.o
-endif
-
-SRCS	:= $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-
-ALL	+=$(obj).depend $(LIB)
-
 ifdef CONFIG_SPL_BUILD
-ALL	+= $(OBJTREE)/tools/mk$(BOARD)spl
-endif
+# necessary to create built-in.o
+obj- := __dummy__.o
 
-all:	$(ALL)
+hostprogs-y := tools/mkorigenspl
+always := $(hostprogs-y)
 
-$(LIB):	$(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-ifdef CONFIG_SPL_BUILD
-$(OBJTREE)/tools/mk$(BOARD)spl:	tools/mkv310_image.c
-	$(HOSTCC) tools/mkv310_image.c -o $(OBJTREE)/tools/mk$(BOARD)spl
+# omit -O2 option to suppress
+#   warning: dereferencing type-punned pointer will break strict-aliasing rules
+#
+# TODO:
+# Fix the root cause in tools/mkorigenspl.c and delete the following work-around
+$(obj)/tools/mkorigenspl: HOSTCFLAGS:=$(filter-out -O2,$(HOSTCFLAGS))
+else
+obj-y	+= origen.o
 endif
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
diff --git a/board/samsung/origen/origen.c b/board/samsung/origen/origen.c
index 15f77cacbd..d502f02d3d 100644
--- a/board/samsung/origen/origen.c
+++ b/board/samsung/origen/origen.c
@@ -11,129 +11,35 @@
 #include <asm/arch/mmc.h>
 #include <asm/arch/periph.h>
 #include <asm/arch/pinmux.h>
+#include <usb.h>
 
 DECLARE_GLOBAL_DATA_PTR;
-struct exynos4_gpio_part1 *gpio1;
-struct exynos4_gpio_part2 *gpio2;
 
-int board_init(void)
+u32 get_board_rev(void)
 {
-	gpio1 = (struct exynos4_gpio_part1 *) EXYNOS4_GPIO_PART1_BASE;
-	gpio2 = (struct exynos4_gpio_part2 *) EXYNOS4_GPIO_PART2_BASE;
-
-	gd->bd->bi_boot_params = (PHYS_SDRAM_1 + 0x100UL);
 	return 0;
 }
 
-static int board_uart_init(void)
+int exynos_init(void)
 {
-	int err;
-
-	err = exynos_pinmux_config(PERIPH_ID_UART0, PINMUX_FLAG_NONE);
-	if (err) {
-		debug("UART0 not configured\n");
-		return err;
-	}
-
-	err = exynos_pinmux_config(PERIPH_ID_UART1, PINMUX_FLAG_NONE);
-	if (err) {
-		debug("UART1 not configured\n");
-		return err;
-	}
-
-	err = exynos_pinmux_config(PERIPH_ID_UART2, PINMUX_FLAG_NONE);
-	if (err) {
-		debug("UART2 not configured\n");
-		return err;
-	}
-
-	err = exynos_pinmux_config(PERIPH_ID_UART3, PINMUX_FLAG_NONE);
-	if (err) {
-		debug("UART3 not configured\n");
-		return err;
-	}
-
 	return 0;
 }
 
-#ifdef CONFIG_BOARD_EARLY_INIT_F
-int board_early_init_f(void)
-{
-	int err;
-	err = board_uart_init();
-	if (err) {
-		debug("UART init failed\n");
-		return err;
-	}
-	return err;
-}
-#endif
-
-int dram_init(void)
+int board_usb_init(int index, enum usb_init_type init)
 {
-	gd->ram_size	= get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE)
-			+ get_ram_size((long *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE)
-			+ get_ram_size((long *)PHYS_SDRAM_3, PHYS_SDRAM_3_SIZE)
-			+ get_ram_size((long *)PHYS_SDRAM_4, PHYS_SDRAM_4_SIZE);
-
 	return 0;
 }
 
-void dram_init_banksize(void)
-{
-	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
-	gd->bd->bi_dram[0].size = get_ram_size((long *)PHYS_SDRAM_1, \
-							PHYS_SDRAM_1_SIZE);
-	gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
-	gd->bd->bi_dram[1].size = get_ram_size((long *)PHYS_SDRAM_2, \
-							PHYS_SDRAM_2_SIZE);
-	gd->bd->bi_dram[2].start = PHYS_SDRAM_3;
-	gd->bd->bi_dram[2].size = get_ram_size((long *)PHYS_SDRAM_3, \
-							PHYS_SDRAM_3_SIZE);
-	gd->bd->bi_dram[3].start = PHYS_SDRAM_4;
-	gd->bd->bi_dram[3].size = get_ram_size((long *)PHYS_SDRAM_4, \
-							PHYS_SDRAM_4_SIZE);
-}
-
-#ifdef CONFIG_DISPLAY_BOARDINFO
-int checkboard(void)
+#ifdef CONFIG_USB_CABLE_CHECK
+int usb_cable_connected(void)
 {
-	printf("\nBoard: ORIGEN\n");
 	return 0;
 }
 #endif
 
-#ifdef CONFIG_GENERIC_MMC
-int board_mmc_init(bd_t *bis)
+#ifdef CONFIG_BOARD_EARLY_INIT_F
+int exynos_early_init_f(void)
 {
-	int i, err;
-
-	/*
-	 * MMC2 SD card GPIO:
-	 *
-	 * GPK2[0]	SD_2_CLK(2)
-	 * GPK2[1]	SD_2_CMD(2)
-	 * GPK2[2]	SD_2_CDn
-	 * GPK2[3:6]	SD_2_DATA[0:3](2)
-	 */
-	for (i = 0; i < 7; i++) {
-		/* GPK2[0:6] special function 2 */
-		s5p_gpio_cfg_pin(&gpio2->k2, i, GPIO_FUNC(0x2));
-
-		/* GPK2[0:6] drv 4x */
-		s5p_gpio_set_drv(&gpio2->k2, i, GPIO_DRV_4X);
-
-		/* GPK2[0:1] pull disable */
-		if (i == 0 || i == 1) {
-			s5p_gpio_set_pull(&gpio2->k2, i, GPIO_PULL_NONE);
-			continue;
-		}
-
-		/* GPK2[2:6] pull up */
-		s5p_gpio_set_pull(&gpio2->k2, i, GPIO_PULL_UP);
-	}
-
-	err = s5p_mmc_init(2, 4);
-	return err;
+	return 0;
 }
 #endif
diff --git a/board/samsung/origen/tools/mkv310_image.c b/board/samsung/origen/tools/mkorigenspl.c
index 3ed20efce3..3ed20efce3 100644
--- a/board/samsung/origen/tools/mkv310_image.c
+++ b/board/samsung/origen/tools/mkorigenspl.c
diff --git a/board/samsung/smdk2410/Makefile b/board/samsung/smdk2410/Makefile
index f52d0cd2de..1939a217a1 100644
--- a/board/samsung/smdk2410/Makefile
+++ b/board/samsung/smdk2410/Makefile
@@ -5,25 +5,5 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	:= smdk2410.o
-SOBJS	:= lowlevel_init.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
-	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	:= smdk2410.o
+obj-y	+= lowlevel_init.o
diff --git a/board/samsung/smdk2410/lowlevel_init.S b/board/samsung/smdk2410/lowlevel_init.S
index c7b78fd103..5de04f10e9 100644
--- a/board/samsung/smdk2410/lowlevel_init.S
+++ b/board/samsung/smdk2410/lowlevel_init.S
@@ -110,16 +110,13 @@
 #define REFCNT			1113	/* period=15.6us, HCLK=60Mhz, (2048+1-15.6*60) */
 /**************************************/
 
-_TEXT_BASE:
-	.word	CONFIG_SYS_TEXT_BASE
-
 .globl lowlevel_init
 lowlevel_init:
 	/* memory control configuration */
 	/* make r0 relative the current location so that it */
 	/* reads SMRDATA out of FLASH rather than memory ! */
 	ldr     r0, =SMRDATA
-	ldr	r1, _TEXT_BASE
+	ldr	r1, =CONFIG_SYS_TEXT_BASE
 	sub	r0, r0, r1
 	ldr	r1, =BWSCON	/* Bus Width Status Controller */
 	add     r2, r0, #13*4
diff --git a/board/samsung/smdk5250/Makefile b/board/samsung/smdk5250/Makefile
index 0463079935..6a586553e1 100644
--- a/board/samsung/smdk5250/Makefile
+++ b/board/samsung/smdk5250/Makefile
@@ -4,35 +4,12 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	+= smdk5250_spl.o
+obj-y	+= smdk5250_spl.o
 
 ifndef CONFIG_SPL_BUILD
 ifdef CONFIG_OF_CONTROL
-COBJS	+= exynos5-dt.o
+obj-y	+= exynos5-dt.o
 else
-COBJS	+= smdk5250.o
+obj-y	+= smdk5250.o
 endif
 endif
-
-SRCS	:= $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-
-ALL	:= $(obj).depend $(LIB)
-
-all:	$(ALL)
-
-$(LIB):	$(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
diff --git a/board/samsung/smdk5250/exynos5-dt.c b/board/samsung/smdk5250/exynos5-dt.c
index bb4a82f449..379a45cc23 100644
--- a/board/samsung/smdk5250/exynos5-dt.c
+++ b/board/samsung/smdk5250/exynos5-dt.c
@@ -5,7 +5,6 @@
  */
 
 #include <common.h>
-#include <cros_ec.h>
 #include <fdtdec.h>
 #include <asm/io.h>
 #include <errno.h>
@@ -25,60 +24,8 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-#if defined CONFIG_EXYNOS_TMU
-/*
- * Boot Time Thermal Analysis for SoC temperature threshold breach
- */
-static void boot_temp_check(void)
-{
-	int temp;
-
-	switch (tmu_monitor(&temp)) {
-	/* Status TRIPPED ans WARNING means corresponding threshold breach */
-	case TMU_STATUS_TRIPPED:
-		puts("EXYNOS_TMU: TRIPPING! Device power going down ...\n");
-		set_ps_hold_ctrl();
-		hang();
-		break;
-	case TMU_STATUS_WARNING:
-		puts("EXYNOS_TMU: WARNING! Temperature very high\n");
-		break;
-	/*
-	 * TMU_STATUS_INIT means something is wrong with temperature sensing
-	 * and TMU status was changed back from NORMAL to INIT.
-	 */
-	case TMU_STATUS_INIT:
-	default:
-		debug("EXYNOS_TMU: Unknown TMU state\n");
-	}
-}
-#endif
-
-struct local_info {
-	struct cros_ec_dev *cros_ec_dev;	/* Pointer to cros_ec device */
-	int cros_ec_err;			/* Error for cros_ec, 0 if ok */
-};
-
-static struct local_info local;
-
-#ifdef CONFIG_USB_EHCI_EXYNOS
-int board_usb_vbus_init(void)
-{
-	struct exynos5_gpio_part1 *gpio1 = (struct exynos5_gpio_part1 *)
-						samsung_get_base_gpio_part1();
-
-	/* Enable VBUS power switch */
-	s5p_gpio_direction_output(&gpio1->x2, 6, 1);
-
-	/* VBUS turn ON time */
-	mdelay(3);
-
-	return 0;
-}
-#endif
-
 #ifdef CONFIG_SOUND_MAX98095
-static void  board_enable_audio_codec(void)
+static void board_enable_audio_codec(void)
 {
 	struct exynos5_gpio_part1 *gpio1 = (struct exynos5_gpio_part1 *)
 						samsung_get_base_gpio_part1();
@@ -89,325 +36,14 @@ static void  board_enable_audio_codec(void)
 }
 #endif
 
-struct cros_ec_dev *board_get_cros_ec_dev(void)
+int exynos_init(void)
 {
-	return local.cros_ec_dev;
-}
-
-static int board_init_cros_ec_devices(const void *blob)
-{
-	local.cros_ec_err = cros_ec_init(blob, &local.cros_ec_dev);
-	if (local.cros_ec_err)
-		return -1;  /* Will report in board_late_init() */
-
-	return 0;
-}
-
-int board_init(void)
-{
-	gd->bd->bi_boot_params = (PHYS_SDRAM_1 + 0x100UL);
-
-#if defined CONFIG_EXYNOS_TMU
-	if (tmu_init(gd->fdt_blob) != TMU_STATUS_NORMAL) {
-		debug("%s: Failed to init TMU\n", __func__);
-		return -1;
-	}
-	boot_temp_check();
-#endif
-
-#ifdef CONFIG_EXYNOS_SPI
-	spi_init();
-#endif
-
-	if (board_init_cros_ec_devices(gd->fdt_blob))
-		return -1;
-
-#ifdef CONFIG_USB_EHCI_EXYNOS
-	board_usb_vbus_init();
-#endif
 #ifdef CONFIG_SOUND_MAX98095
 	board_enable_audio_codec();
 #endif
 	return 0;
 }
 
-int dram_init(void)
-{
-	int i;
-	u32 addr;
-
-	for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
-		addr = CONFIG_SYS_SDRAM_BASE + (i * SDRAM_BANK_SIZE);
-		gd->ram_size += get_ram_size((long *)addr, SDRAM_BANK_SIZE);
-	}
-	return 0;
-}
-
-#if defined(CONFIG_POWER)
-static int pmic_reg_update(struct pmic *p, int reg, uint regval)
-{
-	u32 val;
-	int ret = 0;
-
-	ret = pmic_reg_read(p, reg, &val);
-	if (ret) {
-		debug("%s: PMIC %d register read failed\n", __func__, reg);
-		return -1;
-	}
-	val |= regval;
-	ret = pmic_reg_write(p, reg, val);
-	if (ret) {
-		debug("%s: PMIC %d register write failed\n", __func__, reg);
-		return -1;
-	}
-	return 0;
-}
-
-int power_init_board(void)
-{
-	struct pmic *p;
-
-	set_ps_hold_ctrl();
-
-	i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
-
-	if (pmic_init(I2C_PMIC))
-		return -1;
-
-	p = pmic_get("MAX77686_PMIC");
-	if (!p)
-		return -ENODEV;
-
-	if (pmic_probe(p))
-		return -1;
-
-	if (pmic_reg_update(p, MAX77686_REG_PMIC_32KHZ, MAX77686_32KHCP_EN))
-		return -1;
-
-	if (pmic_reg_update(p, MAX77686_REG_PMIC_BBAT,
-			    MAX77686_BBCHOSTEN | MAX77686_BBCVS_3_5V))
-		return -1;
-
-	/* VDD_MIF */
-	if (pmic_reg_write(p, MAX77686_REG_PMIC_BUCK1OUT,
-			   MAX77686_BUCK1OUT_1V)) {
-		debug("%s: PMIC %d register write failed\n", __func__,
-		      MAX77686_REG_PMIC_BUCK1OUT);
-		return -1;
-	}
-
-	if (pmic_reg_update(p, MAX77686_REG_PMIC_BUCK1CRTL,
-			    MAX77686_BUCK1CTRL_EN))
-		return -1;
-
-	/* VDD_ARM */
-	if (pmic_reg_write(p, MAX77686_REG_PMIC_BUCK2DVS1,
-			   MAX77686_BUCK2DVS1_1_3V)) {
-		debug("%s: PMIC %d register write failed\n", __func__,
-		      MAX77686_REG_PMIC_BUCK2DVS1);
-		return -1;
-	}
-
-	if (pmic_reg_update(p, MAX77686_REG_PMIC_BUCK2CTRL1,
-			    MAX77686_BUCK2CTRL_ON))
-		return -1;
-
-	/* VDD_INT */
-	if (pmic_reg_write(p, MAX77686_REG_PMIC_BUCK3DVS1,
-			   MAX77686_BUCK3DVS1_1_0125V)) {
-		debug("%s: PMIC %d register write failed\n", __func__,
-		      MAX77686_REG_PMIC_BUCK3DVS1);
-		return -1;
-	}
-
-	if (pmic_reg_update(p, MAX77686_REG_PMIC_BUCK3CTRL,
-			    MAX77686_BUCK3CTRL_ON))
-		return -1;
-
-	/* VDD_G3D */
-	if (pmic_reg_write(p, MAX77686_REG_PMIC_BUCK4DVS1,
-			   MAX77686_BUCK4DVS1_1_2V)) {
-		debug("%s: PMIC %d register write failed\n", __func__,
-		      MAX77686_REG_PMIC_BUCK4DVS1);
-		return -1;
-	}
-
-	if (pmic_reg_update(p, MAX77686_REG_PMIC_BUCK4CTRL1,
-			    MAX77686_BUCK3CTRL_ON))
-		return -1;
-
-	/* VDD_LDO2 */
-	if (pmic_reg_update(p, MAX77686_REG_PMIC_LDO2CTRL1,
-			    MAX77686_LD02CTRL1_1_5V | EN_LDO))
-		return -1;
-
-	/* VDD_LDO3 */
-	if (pmic_reg_update(p, MAX77686_REG_PMIC_LDO3CTRL1,
-			    MAX77686_LD03CTRL1_1_8V | EN_LDO))
-		return -1;
-
-	/* VDD_LDO5 */
-	if (pmic_reg_update(p, MAX77686_REG_PMIC_LDO5CTRL1,
-			    MAX77686_LD05CTRL1_1_8V | EN_LDO))
-		return -1;
-
-	/* VDD_LDO10 */
-	if (pmic_reg_update(p, MAX77686_REG_PMIC_LDO10CTRL1,
-			    MAX77686_LD10CTRL1_1_8V | EN_LDO))
-		return -1;
-
-	return 0;
-}
-#endif
-
-void dram_init_banksize(void)
-{
-	int i;
-	u32 addr, size;
-
-	for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
-		addr = CONFIG_SYS_SDRAM_BASE + (i * SDRAM_BANK_SIZE);
-		size = get_ram_size((long *)addr, SDRAM_BANK_SIZE);
-
-		gd->bd->bi_dram[i].start = addr;
-		gd->bd->bi_dram[i].size = size;
-	}
-}
-
-static int decode_sromc(const void *blob, struct fdt_sromc *config)
-{
-	int err;
-	int node;
-
-	node = fdtdec_next_compatible(blob, 0, COMPAT_SAMSUNG_EXYNOS5_SROMC);
-	if (node < 0) {
-		debug("Could not find SROMC node\n");
-		return node;
-	}
-
-	config->bank = fdtdec_get_int(blob, node, "bank", 0);
-	config->width = fdtdec_get_int(blob, node, "width", 2);
-
-	err = fdtdec_get_int_array(blob, node, "srom-timing", config->timing,
-			FDT_SROM_TIMING_COUNT);
-	if (err < 0) {
-		debug("Could not decode SROMC configuration Error: %s\n",
-		      fdt_strerror(err));
-		return -FDT_ERR_NOTFOUND;
-	}
-	return 0;
-}
-
-int board_eth_init(bd_t *bis)
-{
-#ifdef CONFIG_SMC911X
-	u32 smc_bw_conf, smc_bc_conf;
-	struct fdt_sromc config;
-	fdt_addr_t base_addr;
-	int node;
-
-	node = decode_sromc(gd->fdt_blob, &config);
-	if (node < 0) {
-		debug("%s: Could not find sromc configuration\n", __func__);
-		return 0;
-	}
-	node = fdtdec_next_compatible(gd->fdt_blob, node, COMPAT_SMSC_LAN9215);
-	if (node < 0) {
-		debug("%s: Could not find lan9215 configuration\n", __func__);
-		return 0;
-	}
-
-	/* We now have a node, so any problems from now on are errors */
-	base_addr = fdtdec_get_addr(gd->fdt_blob, node, "reg");
-	if (base_addr == FDT_ADDR_T_NONE) {
-		debug("%s: Could not find lan9215 address\n", __func__);
-		return -1;
-	}
-
-	/* Ethernet needs data bus width of 16 bits */
-	if (config.width != 2) {
-		debug("%s: Unsupported bus width %d\n", __func__,
-		      config.width);
-		return -1;
-	}
-	smc_bw_conf = SROMC_DATA16_WIDTH(config.bank)
-			| SROMC_BYTE_ENABLE(config.bank);
-
-	smc_bc_conf = SROMC_BC_TACS(config.timing[FDT_SROM_TACS])   |
-			SROMC_BC_TCOS(config.timing[FDT_SROM_TCOS]) |
-			SROMC_BC_TACC(config.timing[FDT_SROM_TACC]) |
-			SROMC_BC_TCOH(config.timing[FDT_SROM_TCOH]) |
-			SROMC_BC_TAH(config.timing[FDT_SROM_TAH])   |
-			SROMC_BC_TACP(config.timing[FDT_SROM_TACP]) |
-			SROMC_BC_PMC(config.timing[FDT_SROM_PMC]);
-
-	/* Select and configure the SROMC bank */
-	exynos_pinmux_config(PERIPH_ID_SROMC, config.bank);
-	s5p_config_sromc(config.bank, smc_bw_conf, smc_bc_conf);
-	return smc911x_initialize(0, base_addr);
-#endif
-	return 0;
-}
-
-#ifdef CONFIG_DISPLAY_BOARDINFO
-int checkboard(void)
-{
-	const char *board_name;
-
-	board_name = fdt_getprop(gd->fdt_blob, 0, "model", NULL);
-	if (board_name == NULL)
-		printf("\nUnknown Board\n");
-	else
-		printf("\nBoard: %s\n", board_name);
-
-	return 0;
-}
-#endif
-
-#ifdef CONFIG_GENERIC_MMC
-int board_mmc_init(bd_t *bis)
-{
-	int ret;
-	/* dwmmc initializattion for available channels */
-	ret = exynos_dwmmc_init(gd->fdt_blob);
-	if (ret)
-		debug("dwmmc init failed\n");
-
-	return ret;
-}
-#endif
-
-static int board_uart_init(void)
-{
-	int err, uart_id, ret = 0;
-
-	for (uart_id = PERIPH_ID_UART0; uart_id <= PERIPH_ID_UART3; uart_id++) {
-		err = exynos_pinmux_config(uart_id, PINMUX_FLAG_NONE);
-		if (err) {
-			debug("UART%d not configured\n",
-			      (uart_id - PERIPH_ID_UART0));
-			ret |= err;
-		}
-	}
-	return ret;
-}
-
-#ifdef CONFIG_BOARD_EARLY_INIT_F
-int board_early_init_f(void)
-{
-	int err;
-	err = board_uart_init();
-	if (err) {
-		debug("UART init failed\n");
-		return err;
-	}
-#ifdef CONFIG_SYS_I2C_INIT_BOARD
-	board_i2c_init(gd->fdt_blob);
-#endif
-	return err;
-}
-#endif
-
 #ifdef CONFIG_LCD
 void exynos_cfg_lcd_gpio(void)
 {
@@ -431,22 +67,3 @@ void exynos_set_dp_phy(unsigned int onoff)
 	set_dp_phy_ctrl(onoff);
 }
 #endif
-
-#ifdef CONFIG_BOARD_LATE_INIT
-int board_late_init(void)
-{
-	stdio_print_current_devices();
-
-	if (local.cros_ec_err) {
-		/* Force console on */
-		gd->flags &= ~GD_FLG_SILENT;
-
-		printf("cros-ec communications failure %d\n",
-		       local.cros_ec_err);
-		puts("\nPlease reset with Power+Refresh\n\n");
-		panic("Cannot init cros-ec device");
-		return -1;
-	}
-	return 0;
-}
-#endif
diff --git a/board/samsung/smdk5250/lowlevel_init.S b/board/samsung/smdk5250/lowlevel_init.S
deleted file mode 100644
index 9003e2d007..0000000000
--- a/board/samsung/smdk5250/lowlevel_init.S
+++ /dev/null
@@ -1,82 +0,0 @@
-/*
- * Lowlevel setup for SMDK5250 board based on S5PC520
- *
- * Copyright (C) 2012 Samsung Electronics
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <config.h>
-#include <version.h>
-#include <asm/arch/cpu.h>
-
-_TEXT_BASE:
-	.word	CONFIG_SYS_TEXT_BASE
-
-	.globl lowlevel_init
-lowlevel_init:
-
-	/* use iRAM stack in bl2 */
-	ldr	sp, =CONFIG_IRAM_STACK
-	stmdb	r13!, {ip,lr}
-
-	/* check reset status */
-	ldr	r0, =(EXYNOS5_POWER_BASE + INFORM1_OFFSET)
-	ldr	r1, [r0]
-
-	/* AFTR wakeup reset */
-	ldr	r2, =S5P_CHECK_DIDLE
-	cmp	r1, r2
-	beq	exit_wakeup
-
-	/* LPA wakeup reset */
-	ldr	r2, =S5P_CHECK_LPA
-	cmp	r1, r2
-	beq	exit_wakeup
-
-	/* Sleep wakeup reset */
-	ldr	r2, =S5P_CHECK_SLEEP
-	cmp	r1, r2
-	beq	wakeup_reset
-
-	/*
-	 * If U-boot is already running in RAM, no need to relocate U-Boot.
-	 * Memory controller must be configured before relocating U-Boot
-	 * in ram.
-	 */
-	ldr	r0, =0x0ffffff		/* r0 <- Mask Bits*/
-	bic	r1, pc, r0		/* pc <- current addr of code */
-					/* r1 <- unmasked bits of pc */
-	ldr	r2, _TEXT_BASE		/* r2 <- original base addr in ram */
-	bic	r2, r2, r0		/* r2 <- unmasked bits of r2*/
-	cmp	r1, r2			/* compare r1, r2 */
-	beq	1f			/* r0 == r1 then skip sdram init */
-
-	/* init system clock */
-	bl	system_clock_init
-
-	/* Memory initialize */
-	bl	mem_ctrl_init
-
-1:
-	bl	arch_cpu_init
-	bl	tzpc_init
-	ldmia	r13!, {ip,pc}
-
-wakeup_reset:
-	bl	system_clock_init
-	bl	mem_ctrl_init
-	bl	arch_cpu_init
-	bl	tzpc_init
-
-exit_wakeup:
-	/* Load return address and jump to kernel */
-	ldr	r0, =(EXYNOS5_POWER_BASE + INFORM0_OFFSET)
-
-	/* r1 = physical address of exynos5_cpu_resume function*/
-	ldr	r1, [r0]
-
-	/* Jump to kernel */
-	mov	pc, r1
-	nop
-	nop
diff --git a/board/samsung/smdk5250/smdk5250.c b/board/samsung/smdk5250/smdk5250.c
index 97fe0adf54..28a6d9e718 100644
--- a/board/samsung/smdk5250/smdk5250.c
+++ b/board/samsung/smdk5250/smdk5250.c
@@ -5,6 +5,7 @@
  */
 
 #include <common.h>
+#include <cros_ec.h>
 #include <fdtdec.h>
 #include <asm/io.h>
 #include <errno.h>
@@ -25,22 +26,6 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-#ifdef CONFIG_USB_EHCI_EXYNOS
-int board_usb_vbus_init(void)
-{
-	struct exynos5_gpio_part1 *gpio1 = (struct exynos5_gpio_part1 *)
-						samsung_get_base_gpio_part1();
-
-	/* Enable VBUS power switch */
-	s5p_gpio_direction_output(&gpio1->x2, 6, 1);
-
-	/* VBUS turn ON time */
-	mdelay(3);
-
-	return 0;
-}
-#endif
-
 #ifdef CONFIG_SOUND_MAX98095
 static void  board_enable_audio_codec(void)
 {
@@ -53,163 +38,14 @@ static void  board_enable_audio_codec(void)
 }
 #endif
 
-int board_init(void)
+int exynos_init(void)
 {
-	gd->bd->bi_boot_params = (PHYS_SDRAM_1 + 0x100UL);
-
-#ifdef CONFIG_EXYNOS_SPI
-	spi_init();
-#endif
-#ifdef CONFIG_USB_EHCI_EXYNOS
-	board_usb_vbus_init();
-#endif
 #ifdef CONFIG_SOUND_MAX98095
 	board_enable_audio_codec();
 #endif
 	return 0;
 }
 
-int dram_init(void)
-{
-	int i;
-	u32 addr;
-
-	for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
-		addr = CONFIG_SYS_SDRAM_BASE + (i * SDRAM_BANK_SIZE);
-		gd->ram_size += get_ram_size((long *)addr, SDRAM_BANK_SIZE);
-	}
-	return 0;
-}
-
-#if defined(CONFIG_POWER)
-static int pmic_reg_update(struct pmic *p, int reg, uint regval)
-{
-	u32 val;
-	int ret = 0;
-
-	ret = pmic_reg_read(p, reg, &val);
-	if (ret) {
-		debug("%s: PMIC %d register read failed\n", __func__, reg);
-		return -1;
-	}
-	val |= regval;
-	ret = pmic_reg_write(p, reg, val);
-	if (ret) {
-		debug("%s: PMIC %d register write failed\n", __func__, reg);
-		return -1;
-	}
-	return 0;
-}
-
-int power_init_board(void)
-{
-	struct pmic *p;
-
-	set_ps_hold_ctrl();
-
-	i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
-
-	if (pmic_init(I2C_PMIC))
-		return -1;
-
-	p = pmic_get("MAX77686_PMIC");
-	if (!p)
-		return -ENODEV;
-
-	if (pmic_probe(p))
-		return -1;
-
-	if (pmic_reg_update(p, MAX77686_REG_PMIC_32KHZ, MAX77686_32KHCP_EN))
-		return -1;
-
-	if (pmic_reg_update(p, MAX77686_REG_PMIC_BBAT,
-				MAX77686_BBCHOSTEN | MAX77686_BBCVS_3_5V))
-		return -1;
-
-	/* VDD_MIF */
-	if (pmic_reg_write(p, MAX77686_REG_PMIC_BUCK1OUT,
-						MAX77686_BUCK1OUT_1_05V)) {
-		debug("%s: PMIC %d register write failed\n", __func__,
-						MAX77686_REG_PMIC_BUCK1OUT);
-		return -1;
-	}
-
-	if (pmic_reg_update(p, MAX77686_REG_PMIC_BUCK1CRTL,
-						MAX77686_BUCK1CTRL_EN))
-		return -1;
-
-	/* VDD_ARM */
-	if (pmic_reg_write(p, MAX77686_REG_PMIC_BUCK2DVS1,
-					MAX77686_BUCK2DVS1_1_3V)) {
-		debug("%s: PMIC %d register write failed\n", __func__,
-						MAX77686_REG_PMIC_BUCK2DVS1);
-		return -1;
-	}
-
-	if (pmic_reg_update(p, MAX77686_REG_PMIC_BUCK2CTRL1,
-					MAX77686_BUCK2CTRL_ON))
-		return -1;
-
-	/* VDD_INT */
-	if (pmic_reg_write(p, MAX77686_REG_PMIC_BUCK3DVS1,
-					MAX77686_BUCK3DVS1_1_0125V)) {
-		debug("%s: PMIC %d register write failed\n", __func__,
-						MAX77686_REG_PMIC_BUCK3DVS1);
-		return -1;
-	}
-
-	if (pmic_reg_update(p, MAX77686_REG_PMIC_BUCK3CTRL,
-					MAX77686_BUCK3CTRL_ON))
-		return -1;
-
-	/* VDD_G3D */
-	if (pmic_reg_write(p, MAX77686_REG_PMIC_BUCK4DVS1,
-					MAX77686_BUCK4DVS1_1_2V)) {
-		debug("%s: PMIC %d register write failed\n", __func__,
-						MAX77686_REG_PMIC_BUCK4DVS1);
-		return -1;
-	}
-
-	if (pmic_reg_update(p, MAX77686_REG_PMIC_BUCK4CTRL1,
-					MAX77686_BUCK3CTRL_ON))
-		return -1;
-
-	/* VDD_LDO2 */
-	if (pmic_reg_update(p, MAX77686_REG_PMIC_LDO2CTRL1,
-				MAX77686_LD02CTRL1_1_5V | EN_LDO))
-		return -1;
-
-	/* VDD_LDO3 */
-	if (pmic_reg_update(p, MAX77686_REG_PMIC_LDO3CTRL1,
-				MAX77686_LD03CTRL1_1_8V | EN_LDO))
-		return -1;
-
-	/* VDD_LDO5 */
-	if (pmic_reg_update(p, MAX77686_REG_PMIC_LDO5CTRL1,
-				MAX77686_LD05CTRL1_1_8V | EN_LDO))
-		return -1;
-
-	/* VDD_LDO10 */
-	if (pmic_reg_update(p, MAX77686_REG_PMIC_LDO10CTRL1,
-				MAX77686_LD10CTRL1_1_8V | EN_LDO))
-		return -1;
-
-	return 0;
-}
-#endif
-
-void dram_init_banksize(void)
-{
-	int i;
-	u32 addr, size;
-	for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
-		addr = CONFIG_SYS_SDRAM_BASE + (i * SDRAM_BANK_SIZE);
-		size = get_ram_size((long *)addr, SDRAM_BANK_SIZE);
-		gd->bd->bi_dram[i].start = addr;
-		gd->bd->bi_dram[i].size = size;
-	}
-}
-
 int board_eth_init(bd_t *bis)
 {
 #ifdef CONFIG_SMC911X
@@ -301,21 +137,6 @@ int board_mmc_init(bd_t *bis)
 }
 #endif
 
-static int board_uart_init(void)
-{
-	int err, uart_id, ret = 0;
-
-	for (uart_id = PERIPH_ID_UART0; uart_id <= PERIPH_ID_UART3; uart_id++) {
-		err = exynos_pinmux_config(uart_id, PINMUX_FLAG_NONE);
-		if (err) {
-			debug("UART%d not configured\n",
-			      (uart_id - PERIPH_ID_UART0));
-			ret |= err;
-		}
-	}
-	return ret;
-}
-
 void board_i2c_init(const void *blob)
 {
 	int i;
@@ -326,21 +147,130 @@ void board_i2c_init(const void *blob)
 	}
 }
 
-#ifdef CONFIG_BOARD_EARLY_INIT_F
-int board_early_init_f(void)
+#if defined(CONFIG_POWER)
+#ifdef CONFIG_POWER_MAX77686
+static int pmic_reg_update(struct pmic *p, int reg, uint regval)
 {
-	int err;
-	err = board_uart_init();
-	if (err) {
-		debug("UART init failed\n");
-		return err;
+	u32 val;
+	int ret = 0;
+
+	ret = pmic_reg_read(p, reg, &val);
+	if (ret) {
+		debug("%s: PMIC %d register read failed\n", __func__, reg);
+		return -1;
 	}
-#ifdef CONFIG_SYS_I2C_INIT_BOARD
-	board_i2c_init(NULL);
-#endif
-	return err;
+	val |= regval;
+	ret = pmic_reg_write(p, reg, val);
+	if (ret) {
+		debug("%s: PMIC %d register write failed\n", __func__, reg);
+		return -1;
+	}
+	return 0;
+}
+
+static int max77686_init(void)
+{
+	struct pmic *p;
+
+	if (pmic_init(I2C_PMIC))
+		return -1;
+
+	p = pmic_get("MAX77686_PMIC");
+	if (!p)
+		return -ENODEV;
+
+	if (pmic_probe(p))
+		return -1;
+
+	if (pmic_reg_update(p, MAX77686_REG_PMIC_32KHZ, MAX77686_32KHCP_EN))
+		return -1;
+
+	if (pmic_reg_update(p, MAX77686_REG_PMIC_BBAT,
+			    MAX77686_BBCHOSTEN | MAX77686_BBCVS_3_5V))
+		return -1;
+
+	/* VDD_MIF */
+	if (pmic_reg_write(p, MAX77686_REG_PMIC_BUCK1OUT,
+			   MAX77686_BUCK1OUT_1V)) {
+		debug("%s: PMIC %d register write failed\n", __func__,
+		      MAX77686_REG_PMIC_BUCK1OUT);
+		return -1;
+	}
+
+	if (pmic_reg_update(p, MAX77686_REG_PMIC_BUCK1CRTL,
+			    MAX77686_BUCK1CTRL_EN))
+		return -1;
+
+	/* VDD_ARM */
+	if (pmic_reg_write(p, MAX77686_REG_PMIC_BUCK2DVS1,
+			   MAX77686_BUCK2DVS1_1_3V)) {
+		debug("%s: PMIC %d register write failed\n", __func__,
+		      MAX77686_REG_PMIC_BUCK2DVS1);
+		return -1;
+	}
+
+	if (pmic_reg_update(p, MAX77686_REG_PMIC_BUCK2CTRL1,
+			    MAX77686_BUCK2CTRL_ON))
+		return -1;
+
+	/* VDD_INT */
+	if (pmic_reg_write(p, MAX77686_REG_PMIC_BUCK3DVS1,
+			   MAX77686_BUCK3DVS1_1_0125V)) {
+		debug("%s: PMIC %d register write failed\n", __func__,
+		      MAX77686_REG_PMIC_BUCK3DVS1);
+		return -1;
+	}
+
+	if (pmic_reg_update(p, MAX77686_REG_PMIC_BUCK3CTRL,
+			    MAX77686_BUCK3CTRL_ON))
+		return -1;
+
+	/* VDD_G3D */
+	if (pmic_reg_write(p, MAX77686_REG_PMIC_BUCK4DVS1,
+			   MAX77686_BUCK4DVS1_1_2V)) {
+		debug("%s: PMIC %d register write failed\n", __func__,
+		      MAX77686_REG_PMIC_BUCK4DVS1);
+		return -1;
+	}
+
+	if (pmic_reg_update(p, MAX77686_REG_PMIC_BUCK4CTRL1,
+			    MAX77686_BUCK3CTRL_ON))
+		return -1;
+
+	/* VDD_LDO2 */
+	if (pmic_reg_update(p, MAX77686_REG_PMIC_LDO2CTRL1,
+			    MAX77686_LD02CTRL1_1_5V | EN_LDO))
+		return -1;
+
+	/* VDD_LDO3 */
+	if (pmic_reg_update(p, MAX77686_REG_PMIC_LDO3CTRL1,
+			    MAX77686_LD03CTRL1_1_8V | EN_LDO))
+		return -1;
+
+	/* VDD_LDO5 */
+	if (pmic_reg_update(p, MAX77686_REG_PMIC_LDO5CTRL1,
+			    MAX77686_LD05CTRL1_1_8V | EN_LDO))
+		return -1;
+
+	/* VDD_LDO10 */
+	if (pmic_reg_update(p, MAX77686_REG_PMIC_LDO10CTRL1,
+			    MAX77686_LD10CTRL1_1_8V | EN_LDO))
+		return -1;
+
+	return 0;
 }
+#endif	/* CONFIG_POWER_MAX77686 */
+
+int exynos_power_init(void)
+{
+	int ret = 0;
+
+#ifdef CONFIG_POWER_MAX77686
+	ret = max77686_init();
 #endif
+	return ret;
+}
+#endif	/* CONFIG_POWER */
 
 #ifdef CONFIG_LCD
 void exynos_cfg_lcd_gpio(void)
diff --git a/board/samsung/smdk5420/Makefile b/board/samsung/smdk5420/Makefile
new file mode 100644
index 0000000000..c2f8886c99
--- /dev/null
+++ b/board/samsung/smdk5420/Makefile
@@ -0,0 +1,11 @@
+#
+# Copyright (C) 2013 Samsung Electronics
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y	+= smdk5420_spl.o
+
+ifndef CONFIG_SPL_BUILD
+obj-y	+= smdk5420.o
+endif
diff --git a/board/samsung/smdk5420/smdk5420.c b/board/samsung/smdk5420/smdk5420.c
new file mode 100644
index 0000000000..e4606ecd2a
--- /dev/null
+++ b/board/samsung/smdk5420/smdk5420.c
@@ -0,0 +1,144 @@
+/*
+ * Copyright (C) 2013 Samsung Electronics
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <fdtdec.h>
+#include <asm/io.h>
+#include <i2c.h>
+#include <lcd.h>
+#include <spi.h>
+#include <asm/arch/board.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/pinmux.h>
+#include <asm/arch/dp_info.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#ifdef CONFIG_USB_EHCI_EXYNOS
+static int board_usb_vbus_init(void)
+{
+	struct exynos5_gpio_part1 *gpio1 = (struct exynos5_gpio_part1 *)
+						samsung_get_base_gpio_part1();
+
+	/* Enable VBUS power switch */
+	s5p_gpio_direction_output(&gpio1->x2, 6, 1);
+
+	/* VBUS turn ON time */
+	mdelay(3);
+
+	return 0;
+}
+#endif
+
+int exynos_init(void)
+{
+#ifdef CONFIG_USB_EHCI_EXYNOS
+	board_usb_vbus_init();
+#endif
+	return 0;
+}
+
+#ifdef CONFIG_LCD
+void cfg_lcd_gpio(void)
+{
+	struct exynos5_gpio_part1 *gpio1 =
+		(struct exynos5_gpio_part1 *)samsung_get_base_gpio_part1();
+
+	/* For Backlight */
+	s5p_gpio_cfg_pin(&gpio1->b2, 0, GPIO_OUTPUT);
+	s5p_gpio_set_value(&gpio1->b2, 0, 1);
+
+	/* LCD power on */
+	s5p_gpio_cfg_pin(&gpio1->x1, 5, GPIO_OUTPUT);
+	s5p_gpio_set_value(&gpio1->x1, 5, 1);
+
+	/* Set Hotplug detect for DP */
+	s5p_gpio_cfg_pin(&gpio1->x0, 7, GPIO_FUNC(0x3));
+}
+
+vidinfo_t panel_info = {
+	.vl_freq	= 60,
+	.vl_col		= 2560,
+	.vl_row		= 1600,
+	.vl_width	= 2560,
+	.vl_height	= 1600,
+	.vl_clkp	= CONFIG_SYS_LOW,
+	.vl_hsp		= CONFIG_SYS_LOW,
+	.vl_vsp		= CONFIG_SYS_LOW,
+	.vl_dp		= CONFIG_SYS_LOW,
+	.vl_bpix	= 4,	/* LCD_BPP = 2^4, for output conosle on LCD */
+
+	/* wDP panel timing infomation */
+	.vl_hspw	= 32,
+	.vl_hbpd	= 80,
+	.vl_hfpd	= 48,
+
+	.vl_vspw	= 6,
+	.vl_vbpd	= 37,
+	.vl_vfpd	= 3,
+	.vl_cmd_allow_len = 0xf,
+
+	.win_id		= 3,
+	.cfg_gpio	= cfg_lcd_gpio,
+	.backlight_on	= NULL,
+	.lcd_power_on	= NULL,
+	.reset_lcd	= NULL,
+	.dual_lcd_enabled = 0,
+
+	.init_delay	= 0,
+	.power_on_delay = 0,
+	.reset_delay	= 0,
+	.interface_mode = FIMD_RGB_INTERFACE,
+	.dp_enabled	= 1,
+};
+
+static struct edp_device_info edp_info = {
+	.disp_info = {
+		.h_res = 2560,
+		.h_sync_width = 32,
+		.h_back_porch = 80,
+		.h_front_porch = 48,
+		.v_res = 1600,
+		.v_sync_width  = 6,
+		.v_back_porch = 37,
+		.v_front_porch = 3,
+		.v_sync_rate = 60,
+	},
+	.lt_info = {
+		.lt_status = DP_LT_NONE,
+	},
+	.video_info = {
+		.master_mode = 0,
+		.bist_mode = DP_DISABLE,
+		.bist_pattern = NO_PATTERN,
+		.h_sync_polarity = 0,
+		.v_sync_polarity = 0,
+		.interlaced = 0,
+		.color_space = COLOR_RGB,
+		.dynamic_range = VESA,
+		.ycbcr_coeff = COLOR_YCBCR601,
+		.color_depth = COLOR_8,
+	},
+};
+
+static struct exynos_dp_platform_data dp_platform_data = {
+	.phy_enable	= set_dp_phy_ctrl,
+	.edp_dev_info	= &edp_info,
+};
+
+void init_panel_info(vidinfo_t *vid)
+{
+	vid->rgb_mode   = MODE_RGB_P;
+
+	exynos_set_dp_platform_data(&dp_platform_data);
+}
+#endif
+
+int board_get_revision(void)
+{
+	return 0;
+}
diff --git a/board/samsung/smdk5420/smdk5420_spl.c b/board/samsung/smdk5420/smdk5420_spl.c
new file mode 100644
index 0000000000..73359f784c
--- /dev/null
+++ b/board/samsung/smdk5420/smdk5420_spl.c
@@ -0,0 +1,52 @@
+/*
+ * Copyright (C) 2013 The Chromium OS Authors.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/spl.h>
+#include <asm/arch/clk.h>
+
+#define SIGNATURE	0xdeadbeef
+
+/* Parameters of early board initialization in SPL */
+static struct spl_machine_param machine_param
+		__attribute__((section(".machine_param"))) = {
+	.signature	= SIGNATURE,
+	.version	= 1,
+	.params		= "vmubfasirM",
+	.size		= sizeof(machine_param),
+
+	.mem_iv_size	= 0x1f,
+	.mem_type	= DDR_MODE_DDR3,
+
+	/*
+	 * Set uboot_size to 0x100000 bytes.
+	 *
+	 * This is an overly conservative value chosen to accommodate all
+	 * possible U-Boot image.  You are advised to set this value to a
+	 * smaller realistic size via scripts that modifies the .machine_param
+	 * section of output U-Boot image.
+	 */
+	.uboot_size	= 0x100000,
+
+	.boot_source	= BOOT_MODE_OM,
+	.frequency_mhz	= 800,
+	.arm_freq_mhz	= 900,
+	.serial_base	= 0x12c30000,
+	.i2c_base	= 0x12c60000,
+	.mem_manuf	= MEM_MANUF_SAMSUNG,
+};
+
+struct spl_machine_param *spl_get_machine_params(void)
+{
+	if (machine_param.signature != SIGNATURE) {
+		/* Will hang if SIGNATURE dont match */
+		while (1)
+			;
+	}
+
+	return &machine_param;
+}
diff --git a/board/samsung/smdkc100/Makefile b/board/samsung/smdkc100/Makefile
index 7d4e984e3a..0bcf4e5de5 100644
--- a/board/samsung/smdkc100/Makefile
+++ b/board/samsung/smdkc100/Makefile
@@ -8,26 +8,6 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS-y	:= smdkc100.o
-COBJS-$(CONFIG_SAMSUNG_ONENAND)	+= onenand.o
-SOBJS	:= lowlevel_init.o
-
-SRCS    := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS-y))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(SOBJS) $(OBJS)
-	$(call cmd_link_o_target, $(SOBJS) $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	:= smdkc100.o
+obj-$(CONFIG_SAMSUNG_ONENAND)	+= onenand.o
+obj-y	+= lowlevel_init.o
diff --git a/board/samsung/smdkc100/lowlevel_init.S b/board/samsung/smdkc100/lowlevel_init.S
index 4df0974af5..65e6b7a73a 100644
--- a/board/samsung/smdkc100/lowlevel_init.S
+++ b/board/samsung/smdkc100/lowlevel_init.S
@@ -17,9 +17,6 @@
  * r5 has zero always
  */
 
-_TEXT_BASE:
-	.word	CONFIG_SYS_TEXT_BASE
-
 	.globl lowlevel_init
 lowlevel_init:
 	mov	r9, lr
diff --git a/board/samsung/smdkv310/Makefile b/board/samsung/smdkv310/Makefile
index 5806f0e399..de0da167be 100644
--- a/board/samsung/smdkv310/Makefile
+++ b/board/samsung/smdkv310/Makefile
@@ -4,38 +4,12 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-ifndef CONFIG_SPL_BUILD
-COBJS	+= smdkv310.o
-endif
-
-SRCS	:= $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-
-ALL	:=	 $(obj).depend $(LIB)
-
 ifdef CONFIG_SPL_BUILD
-ALL	+= $(OBJTREE)/tools/mk$(BOARD)spl
-endif
+# necessary to create built-in.o
+obj- := __dummy__.o
 
-all:	$(ALL)
-
-$(LIB):	$(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-ifdef CONFIG_SPL_BUILD
-$(OBJTREE)/tools/mk$(BOARD)spl:	tools/mkv310_image.c
-	$(HOSTCC) tools/mkv310_image.c -o $(OBJTREE)/tools/mk$(BOARD)spl
+hostprogs-y := tools/mksmdkv310spl
+always := $(hostprogs-y)
+else
+obj-y	+= smdkv310.o
 endif
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
diff --git a/board/samsung/smdkv310/tools/mkv310_image.c b/board/samsung/smdkv310/tools/mksmdkv310spl.c
index 9a64ca6ad6..9a64ca6ad6 100644
--- a/board/samsung/smdkv310/tools/mkv310_image.c
+++ b/board/samsung/smdkv310/tools/mksmdkv310spl.c
diff --git a/board/samsung/trats/Makefile b/board/samsung/trats/Makefile
index 5c78517b8d..5dc8a1f7d1 100644
--- a/board/samsung/trats/Makefile
+++ b/board/samsung/trats/Makefile
@@ -5,23 +5,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS-y	+= trats.o
-
-SRCS    := $(COBJS-y:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS-y))
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	+= trats.o
diff --git a/board/samsung/trats/trats.c b/board/samsung/trats/trats.c
index 7f61d17abb..7c79e7b73a 100644
--- a/board/samsung/trats/trats.c
+++ b/board/samsung/trats/trats.c
@@ -12,20 +12,19 @@
 #include <asm/io.h>
 #include <asm/arch/cpu.h>
 #include <asm/arch/gpio.h>
-#include <asm/arch/mmc.h>
 #include <asm/arch/pinmux.h>
 #include <asm/arch/clock.h>
-#include <asm/arch/clk.h>
 #include <asm/arch/mipi_dsim.h>
 #include <asm/arch/watchdog.h>
 #include <asm/arch/power.h>
 #include <power/pmic.h>
 #include <usb/s3c_udc.h>
 #include <power/max8997_pmic.h>
-#include <libtizen.h>
 #include <power/max8997_muic.h>
 #include <power/battery.h>
 #include <power/max17042_fg.h>
+#include <libtizen.h>
+#include <usb.h>
 #include <usb_mass_storage.h>
 
 #include "setup.h"
@@ -44,10 +43,8 @@ u32 get_board_rev(void)
 static void check_hw_revision(void);
 struct s3c_plat_otg_data s5pc210_otg_data;
 
-int board_init(void)
+int exynos_init(void)
 {
-	gd->bd->bi_boot_params = CONFIG_SYS_SPL_ARGS_ADDR;
-
 	check_hw_revision();
 	printf("HW Revision:\t0x%x\n", board_rev);
 
@@ -56,15 +53,18 @@ int board_init(void)
 
 void i2c_init_board(void)
 {
-	struct exynos4_gpio_part1 *gpio1 =
-		(struct exynos4_gpio_part1 *)samsung_get_base_gpio_part1();
+	int err;
 	struct exynos4_gpio_part2 *gpio2 =
 		(struct exynos4_gpio_part2 *)samsung_get_base_gpio_part2();
 
-	/* I2C_5 -> PMIC -> Adapter 0 */
-	s5p_gpio_direction_output(&gpio1->b, 7, 1);
-	s5p_gpio_direction_output(&gpio1->b, 6, 1);
-	/* I2C_9 -> FG -> Adapter 1 */
+	/* I2C_5 -> PMIC */
+	err = exynos_pinmux_config(PERIPH_ID_I2C5, PINMUX_FLAG_NONE);
+	if (err) {
+		debug("I2C%d not configured\n", (I2C_5));
+		return;
+	}
+
+	/* I2C_8 -> FG */
 	s5p_gpio_direction_output(&gpio2->y4, 0, 1);
 	s5p_gpio_direction_output(&gpio2->y4, 1, 1);
 }
@@ -276,7 +276,7 @@ static int pmic_init_max8997(void)
 	return 0;
 }
 
-int power_init_board(void)
+int exynos_power_init(void)
 {
 	int chrg, ret;
 	struct power_battery *pb;
@@ -289,10 +289,10 @@ int power_init_board(void)
 	 * The FUEL_GAUGE is marked as I2C9 on the schematic, but connected
 	 * to logical I2C adapter 1
 	 */
-	ret = pmic_init(I2C_0);
+	ret = pmic_init(I2C_5);
 	ret |= pmic_init_max8997();
-	ret |= power_fg_init(I2C_1);
-	ret |= power_muic_init(I2C_0);
+	ret |= power_fg_init(I2C_9);
+	ret |= power_muic_init(I2C_5);
 	ret |= power_bat_init(0);
 	if (ret)
 		return ret;
@@ -345,28 +345,6 @@ int power_init_board(void)
 	return 0;
 }
 
-int dram_init(void)
-{
-	gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE) +
-		get_ram_size((long *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE) +
-		get_ram_size((long *)PHYS_SDRAM_3, PHYS_SDRAM_3_SIZE) +
-		get_ram_size((long *)PHYS_SDRAM_4, PHYS_SDRAM_4_SIZE);
-
-	return 0;
-}
-
-void dram_init_banksize(void)
-{
-	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
-	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
-	gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
-	gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
-	gd->bd->bi_dram[2].start = PHYS_SDRAM_3;
-	gd->bd->bi_dram[2].size = PHYS_SDRAM_3_SIZE;
-	gd->bd->bi_dram[3].start = PHYS_SDRAM_4;
-	gd->bd->bi_dram[3].size = PHYS_SDRAM_4_SIZE;
-}
-
 static unsigned int get_hw_revision(void)
 {
 	struct exynos4_gpio_part1 *gpio =
@@ -399,55 +377,6 @@ static void check_hw_revision(void)
 	board_rev |= hwrev;
 }
 
-#ifdef CONFIG_DISPLAY_BOARDINFO
-int checkboard(void)
-{
-	puts("Board:\tTRATS\n");
-	return 0;
-}
-#endif
-
-#ifdef CONFIG_GENERIC_MMC
-int board_mmc_init(bd_t *bis)
-{
-	struct exynos4_gpio_part2 *gpio =
-		(struct exynos4_gpio_part2 *)samsung_get_base_gpio_part2();
-	int err;
-
-	/* eMMC_EN: SD_0_CDn: GPK0[2] Output High */
-	s5p_gpio_direction_output(&gpio->k0, 2, 1);
-	s5p_gpio_set_pull(&gpio->k0, 2, GPIO_PULL_NONE);
-
-	/*
-	 * MMC device init
-	 * mmc0	 : eMMC (8-bit buswidth)
-	 * mmc2	 : SD card (4-bit buswidth)
-	 */
-	err = exynos_pinmux_config(PERIPH_ID_SDMMC0, PINMUX_FLAG_8BIT_MODE);
-	if (err)
-		debug("SDMMC0 not configured\n");
-	else
-		err = s5p_mmc_init(0, 8);
-
-	/* T-flash detect */
-	s5p_gpio_cfg_pin(&gpio->x3, 4, 0xf);
-	s5p_gpio_set_pull(&gpio->x3, 4, GPIO_PULL_UP);
-
-	/*
-	 * Check the T-flash  detect pin
-	 * GPX3[4] T-flash detect pin
-	 */
-	if (!s5p_gpio_get_value(&gpio->x3, 4)) {
-		err = exynos_pinmux_config(PERIPH_ID_SDMMC2, PINMUX_FLAG_NONE);
-		if (err)
-			debug("SDMMC2 not configured\n");
-		else
-			err = s5p_mmc_init(2, 4);
-	}
-
-	return err;
-}
-#endif
 
 #ifdef CONFIG_USB_GADGET
 static int s5pc210_phy_control(int on)
@@ -495,12 +424,23 @@ struct s3c_plat_otg_data s5pc210_otg_data = {
 	.usb_flags	= PHY0_SLEEP,
 };
 
-void board_usb_init(void)
+int board_usb_init(int index, enum usb_init_type init)
 {
 	debug("USB_udc_probe\n");
-	s3c_udc_probe(&s5pc210_otg_data);
+	return s3c_udc_probe(&s5pc210_otg_data);
+}
+
+#ifdef CONFIG_USB_CABLE_CHECK
+int usb_cable_connected(void)
+{
+	struct pmic *muic = pmic_get("MAX8997_MUIC");
+	if (!muic)
+		return 0;
+
+	return !!muic->chrg->chrg_type(muic);
 }
 #endif
+#endif
 
 static void pmic_reset(void)
 {
@@ -583,38 +523,22 @@ static void board_power_init(void)
 	writel(0, (unsigned int)&pwr->arm_core1_configuration);
 }
 
-static void board_uart_init(void)
+static void exynos_uart_init(void)
 {
-	struct exynos4_gpio_part1 *gpio1 =
-		(struct exynos4_gpio_part1 *)samsung_get_base_gpio_part1();
 	struct exynos4_gpio_part2 *gpio2 =
 		(struct exynos4_gpio_part2 *)samsung_get_base_gpio_part2();
-	int i;
-
-	/*
-	 * UART2 GPIOs
-	 * GPA1CON[0] = UART_2_RXD(2)
-	 * GPA1CON[1] = UART_2_TXD(2)
-	 * GPA1CON[2] = I2C_3_SDA (3)
-	 * GPA1CON[3] = I2C_3_SCL (3)
-	 */
-
-	for (i = 0; i < 4; i++) {
-		s5p_gpio_set_pull(&gpio1->a1, i, GPIO_PULL_NONE);
-		s5p_gpio_cfg_pin(&gpio1->a1, i, GPIO_FUNC((i > 1) ? 0x3 : 0x2));
-	}
 
 	/* UART_SEL GPY4[7] (part2) at EXYNOS4 */
 	s5p_gpio_set_pull(&gpio2->y4, 7, GPIO_PULL_UP);
 	s5p_gpio_direction_output(&gpio2->y4, 7, 1);
 }
 
-int board_early_init_f(void)
+int exynos_early_init_f(void)
 {
 	wdt_stop();
 	pmic_reset();
 	board_clock_init();
-	board_uart_init();
+	exynos_uart_init();
 	board_power_init();
 
 	return 0;
@@ -632,7 +556,7 @@ void exynos_reset_lcd(void)
 	s5p_gpio_direction_output(&gpio2->y4, 5, 1);
 }
 
-static int lcd_power(void)
+int lcd_power(void)
 {
 	int ret = 0;
 	struct pmic *p = pmic_get("MAX8997_PMIC");
@@ -655,46 +579,7 @@ static int lcd_power(void)
 	return 0;
 }
 
-static struct mipi_dsim_config dsim_config = {
-	.e_interface		= DSIM_VIDEO,
-	.e_virtual_ch		= DSIM_VIRTUAL_CH_0,
-	.e_pixel_format		= DSIM_24BPP_888,
-	.e_burst_mode		= DSIM_BURST_SYNC_EVENT,
-	.e_no_data_lane		= DSIM_DATA_LANE_4,
-	.e_byte_clk		= DSIM_PLL_OUT_DIV8,
-	.hfp			= 1,
-
-	.p			= 3,
-	.m			= 120,
-	.s			= 1,
-
-	/* D-PHY PLL stable time spec :min = 200usec ~ max 400usec */
-	.pll_stable_time	= 500,
-
-	/* escape clk : 10MHz */
-	.esc_clk		= 20 * 1000000,
-
-	/* stop state holding counter after bta change count 0 ~ 0xfff */
-	.stop_holding_cnt	= 0x7ff,
-	/* bta timeout 0 ~ 0xff */
-	.bta_timeout		= 0xff,
-	/* lp rx timeout 0 ~ 0xffff */
-	.rx_timeout		= 0xffff,
-};
-
-static struct exynos_platform_mipi_dsim s6e8ax0_platform_data = {
-	.lcd_panel_info = NULL,
-	.dsim_config = &dsim_config,
-};
-
-static struct mipi_dsim_lcd_device mipi_lcd_device = {
-	.name	= "s6e8ax0",
-	.id	= -1,
-	.bus_id	= 0,
-	.platform_data	= (void *)&s6e8ax0_platform_data,
-};
-
-static int mipi_power(void)
+int mipi_power(void)
 {
 	int ret = 0;
 	struct pmic *p = pmic_get("MAX8997_PMIC");
@@ -717,119 +602,13 @@ static int mipi_power(void)
 	return 0;
 }
 
-vidinfo_t panel_info = {
-	.vl_freq	= 60,
-	.vl_col		= 720,
-	.vl_row		= 1280,
-	.vl_width	= 720,
-	.vl_height	= 1280,
-	.vl_clkp	= CONFIG_SYS_HIGH,
-	.vl_hsp		= CONFIG_SYS_LOW,
-	.vl_vsp		= CONFIG_SYS_LOW,
-	.vl_dp		= CONFIG_SYS_LOW,
-	.vl_bpix	= 5,	/* Bits per pixel, 2^5 = 32 */
-
-	/* s6e8ax0 Panel infomation */
-	.vl_hspw	= 5,
-	.vl_hbpd	= 10,
-	.vl_hfpd	= 10,
-
-	.vl_vspw	= 2,
-	.vl_vbpd	= 1,
-	.vl_vfpd	= 13,
-	.vl_cmd_allow_len = 0xf,
-
-	.win_id		= 3,
-	.dual_lcd_enabled = 0,
-
-	.init_delay	= 0,
-	.power_on_delay = 0,
-	.reset_delay	= 0,
-	.interface_mode = FIMD_RGB_INTERFACE,
-	.mipi_enabled	= 1,
-};
-
-void init_panel_info(vidinfo_t *vid)
+void exynos_lcd_misc_init(vidinfo_t *vid)
 {
-	vid->logo_on	= 1,
-	vid->resolution	= HD_RESOLUTION,
-	vid->rgb_mode	= MODE_RGB_P,
-
 #ifdef CONFIG_TIZEN
 	get_tizen_logo_info(vid);
 #endif
-	mipi_lcd_device.reverse_panel = 1;
-
-	strcpy(s6e8ax0_platform_data.lcd_panel_name, mipi_lcd_device.name);
-	s6e8ax0_platform_data.lcd_power = lcd_power;
-	s6e8ax0_platform_data.mipi_power = mipi_power;
-	s6e8ax0_platform_data.phy_enable = set_mipi_phy_ctrl;
-	s6e8ax0_platform_data.lcd_panel_info = (void *)vid;
-	exynos_mipi_dsi_register_lcd_device(&mipi_lcd_device);
+#ifdef CONFIG_S6E8AX0
 	s6e8ax0_init();
-	exynos_set_dsim_platform_data(&s6e8ax0_platform_data);
-
 	setenv("lcdinfo", "lcd=s6e8ax0");
-}
-
-#ifdef CONFIG_USB_GADGET_MASS_STORAGE
-static int ums_read_sector(struct ums_device *ums_dev,
-			   ulong start, lbaint_t blkcnt, void *buf)
-{
-	if (ums_dev->mmc->block_dev.block_read(ums_dev->dev_num,
-			start + ums_dev->offset, blkcnt, buf) != blkcnt)
-		return -1;
-
-	return 0;
-}
-
-static int ums_write_sector(struct ums_device *ums_dev,
-			    ulong start, lbaint_t blkcnt, const void *buf)
-{
-	if (ums_dev->mmc->block_dev.block_write(ums_dev->dev_num,
-			start + ums_dev->offset, blkcnt, buf) != blkcnt)
-		return -1;
-
-	return 0;
-}
-
-static void ums_get_capacity(struct ums_device *ums_dev,
-			     long long int *capacity)
-{
-	long long int tmp_capacity;
-
-	tmp_capacity = (long long int) ((ums_dev->offset + ums_dev->part_size)
-					* SECTOR_SIZE);
-	*capacity = ums_dev->mmc->capacity - tmp_capacity;
-}
-
-static struct ums_board_info ums_board = {
-	.read_sector = ums_read_sector,
-	.write_sector = ums_write_sector,
-	.get_capacity = ums_get_capacity,
-	.name = "TRATS UMS disk",
-	.ums_dev = {
-		.mmc = NULL,
-		.dev_num = 0,
-		.offset = 0,
-		.part_size = 0.
-	},
-};
-
-struct ums_board_info *board_ums_init(unsigned int dev_num, unsigned int offset,
-				      unsigned int part_size)
-{
-	struct mmc *mmc;
-
-	mmc = find_mmc_device(dev_num);
-	if (!mmc)
-		return NULL;
-
-	ums_board.ums_dev.mmc = mmc;
-	ums_board.ums_dev.dev_num = dev_num;
-	ums_board.ums_dev.offset = offset;
-	ums_board.ums_dev.part_size = part_size;
-
-	return &ums_board;
-}
 #endif
+}
diff --git a/board/samsung/trats2/Makefile b/board/samsung/trats2/Makefile
index 805fb8191a..f501761a41 100644
--- a/board/samsung/trats2/Makefile
+++ b/board/samsung/trats2/Makefile
@@ -5,30 +5,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS-y	:= trats2.o
-
-SRCS    := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS-y))
-
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-clean:
-	rm -f $(OBJS)
-
-distclean:	clean
-	rm -f $(LIB) core *.bak $(obj).depend
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	:= trats2.o
diff --git a/board/samsung/trats2/trats2.c b/board/samsung/trats2/trats2.c
index d44d825e80..f558ef97a9 100644
--- a/board/samsung/trats2/trats2.c
+++ b/board/samsung/trats2/trats2.c
@@ -8,15 +8,9 @@
 
 #include <common.h>
 #include <lcd.h>
-#include <asm/io.h>
-#include <asm/arch/gpio.h>
-#include <asm/arch/mmc.h>
-#include <asm/arch/power.h>
-#include <asm/arch/clk.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/mipi_dsim.h>
 #include <asm/arch/pinmux.h>
 #include <asm/arch/power.h>
+#include <asm/arch/mipi_dsim.h>
 #include <power/pmic.h>
 #include <power/max77686_pmic.h>
 #include <power/battery.h>
@@ -25,6 +19,9 @@
 #include <power/max77693_fg.h>
 #include <libtizen.h>
 #include <errno.h>
+#include <usb.h>
+#include <usb/s3c_udc.h>
+#include <usb_mass_storage.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -40,7 +37,7 @@ static void check_hw_revision(void)
 	int modelrev = 0;
 	int i;
 
-	gpio2 = (struct exynos4x12_gpio_part2 *)EXYNOS4X12_GPIO_PART2_BASE;
+	gpio2 = (struct exynos4x12_gpio_part2 *)samsung_get_base_gpio_part2();
 
 	/*
 	 * GPM1[1:0]: MODEL_REV[1:0]
@@ -65,19 +62,6 @@ static void check_hw_revision(void)
 	board_rev = modelrev << 8;
 }
 
-#ifdef CONFIG_DISPLAY_BOARDINFO
-int checkboard(void)
-{
-	puts("Board:\tTRATS2\n");
-	return 0;
-}
-#endif
-
-static void show_hw_revision(void)
-{
-	printf("HW Revision:\t0x%04x\n", board_rev);
-}
-
 u32 get_board_rev(void)
 {
 	return board_rev;
@@ -90,7 +74,7 @@ static inline u32 get_model_rev(void)
 
 static void board_external_gpio_init(void)
 {
-	gpio2 = (struct exynos4x12_gpio_part2 *)EXYNOS4X12_GPIO_PART2_BASE;
+	gpio2 = (struct exynos4x12_gpio_part2 *)samsung_get_base_gpio_part2();
 
 	/*
 	 * some pins which in alive block are connected with external pull-up
@@ -115,12 +99,17 @@ static void board_external_gpio_init(void)
 #ifdef CONFIG_SYS_I2C_INIT_BOARD
 static void board_init_i2c(void)
 {
-	gpio1 = (struct exynos4x12_gpio_part1 *)EXYNOS4X12_GPIO_PART1_BASE;
-	gpio2 = (struct exynos4x12_gpio_part2 *)EXYNOS4X12_GPIO_PART2_BASE;
+	int err;
+
+	gpio1 = (struct exynos4x12_gpio_part1 *)samsung_get_base_gpio_part1();
+	gpio2 = (struct exynos4x12_gpio_part2 *)samsung_get_base_gpio_part2();
 
 	/* I2C_7 */
-	s5p_gpio_direction_output(&gpio1->d0, 2, 1);
-	s5p_gpio_direction_output(&gpio1->d0, 3, 1);
+	err = exynos_pinmux_config(PERIPH_ID_I2C7, PINMUX_FLAG_NONE);
+	if (err) {
+		debug("I2C%d not configured\n", (I2C_7));
+		return;
+	}
 
 	/* I2C_8 */
 	s5p_gpio_direction_output(&gpio1->f1, 4, 1);
@@ -132,33 +121,55 @@ static void board_init_i2c(void)
 }
 #endif
 
-int board_early_init_f(void)
+#ifdef CONFIG_SYS_I2C_SOFT
+int get_soft_i2c_scl_pin(void)
 {
-	check_hw_revision();
-	board_external_gpio_init();
+	if (I2C_ADAP_HWNR)
+		return exynos4x12_gpio_get(2, m2, 1); /* I2C9 */
+	else
+		return exynos4x12_gpio_get(1, f1, 4); /* I2C8 */
+}
+
+int get_soft_i2c_sda_pin(void)
+{
+	if (I2C_ADAP_HWNR)
+		return exynos4x12_gpio_get(2, m2, 0); /* I2C9 */
+	else
+		return exynos4x12_gpio_get(1, f1, 5); /* I2C8 */
+}
+#endif
 
-	gd->flags |= GD_FLG_DISABLE_CONSOLE;
+int exynos_early_init_f(void)
+{
+	board_external_gpio_init();
 
 	return 0;
 }
 
 static int pmic_init_max77686(void);
 
-int board_init(void)
+int exynos_init(void)
 {
 	struct exynos4_power *pwr =
-		(struct exynos4_power *)EXYNOS4X12_POWER_BASE;
+		(struct exynos4_power *)samsung_get_base_power();
 
-	gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
+	check_hw_revision();
+	printf("HW Revision:\t0x%04x\n", board_rev);
 
-	/* workaround: clear INFORM4..5 */
-	writel(0, (unsigned int)&pwr->inform4);
-	writel(0, (unsigned int)&pwr->inform5);
+	/*
+	 * First bootloader on the TRATS2 platform uses
+	 * INFORM4 and INFORM5 registers for recovery
+	 *
+	 * To indicate correct boot chain - those two
+	 * registers must be cleared out
+	 */
+	writel(0, &pwr->inform4);
+	writel(0, &pwr->inform5);
 
 	return 0;
 }
 
-int power_init_board(void)
+int exynos_power_init(void)
 {
 	int chrg;
 	struct power_battery *pb;
@@ -167,11 +178,11 @@ int power_init_board(void)
 #ifdef CONFIG_SYS_I2C_INIT_BOARD
 	board_init_i2c();
 #endif
-	pmic_init(I2C_0);		/* I2C adapter 0 - bus name I2C_5 */
+	pmic_init(I2C_7);		/* I2C adapter 7 - bus name s3c24x0_7 */
 	pmic_init_max77686();
-	pmic_init_max77693(I2C_2);	/* I2C adapter 2 - bus name I2C_10 */
-	power_muic_init(I2C_2);		/* I2C adapter 2 - bus name I2C_10 */
-	power_fg_init(I2C_1);		/* I2C adapter 1 - bus name I2C_9 */
+	pmic_init_max77693(I2C_10);	/* I2C adapter 10 - bus name soft1 */
+	power_muic_init(I2C_10);	/* I2C adapter 10 - bus name soft1 */
+	power_fg_init(I2C_9);		/* I2C adapter 9 - bus name soft0 */
 	power_bat_init(0);
 
 	p_chrg = pmic_get("MAX77693_PMIC");
@@ -224,90 +235,95 @@ int power_init_board(void)
 	return 0;
 }
 
-int dram_init(void)
+#ifdef CONFIG_USB_GADGET
+static int s5pc210_phy_control(int on)
 {
-	u32 size_mb;
+	int ret = 0;
+	unsigned int val;
+	struct pmic *p, *p_pmic, *p_muic;
 
-	size_mb = (get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE) +
-		get_ram_size((long *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE) +
-		get_ram_size((long *)PHYS_SDRAM_3, PHYS_SDRAM_3_SIZE) +
-		get_ram_size((long *)PHYS_SDRAM_4, PHYS_SDRAM_4_SIZE)) >> 20;
+	p_pmic = pmic_get("MAX77686_PMIC");
+	if (!p_pmic)
+		return -ENODEV;
 
-	gd->ram_size = size_mb << 20;
+	if (pmic_probe(p_pmic))
+		return -1;
 
-	return 0;
-}
+	p_muic = pmic_get("MAX77693_MUIC");
+	if (!p_muic)
+		return -ENODEV;
 
-void dram_init_banksize(void)
-{
-	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
-	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
-	gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
-	gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
-	gd->bd->bi_dram[2].start = PHYS_SDRAM_3;
-	gd->bd->bi_dram[2].size = PHYS_SDRAM_3_SIZE;
-	gd->bd->bi_dram[3].start = PHYS_SDRAM_4;
-	gd->bd->bi_dram[3].size = PHYS_SDRAM_4_SIZE;
-}
+	if (pmic_probe(p_muic))
+		return -1;
 
-int board_mmc_init(bd_t *bis)
-{
-	int err0, err2 = 0;
+	if (on) {
+		ret = max77686_set_ldo_mode(p_pmic, 12, OPMODE_ON);
+		if (ret)
+			return -1;
 
-	gpio2 = (struct exynos4x12_gpio_part2 *)EXYNOS4X12_GPIO_PART2_BASE;
+		p = pmic_get("MAX77693_PMIC");
+		if (!p)
+			return -ENODEV;
 
-	/* eMMC_EN: SD_0_CDn: GPK0[2] Output High */
-	s5p_gpio_direction_output(&gpio2->k0, 2, 1);
-	s5p_gpio_set_pull(&gpio2->k0, 2, GPIO_PULL_NONE);
+		if (pmic_probe(p))
+			return -1;
 
-	/*
-	 * eMMC GPIO:
-	 * SDR 8-bit@48MHz at MMC0
-	 * GPK0[0]      SD_0_CLK(2)
-	 * GPK0[1]      SD_0_CMD(2)
-	 * GPK0[2]      SD_0_CDn        -> Not used
-	 * GPK0[3:6]    SD_0_DATA[0:3](2)
-	 * GPK1[3:6]    SD_0_DATA[0:3](3)
-	 *
-	 * DDR 4-bit@26MHz at MMC4
-	 * GPK0[0]      SD_4_CLK(3)
-	 * GPK0[1]      SD_4_CMD(3)
-	 * GPK0[2]      SD_4_CDn        -> Not used
-	 * GPK0[3:6]    SD_4_DATA[0:3](3)
-	 * GPK1[3:6]    SD_4_DATA[4:7](4)
-	 */
+		/* SAFEOUT */
+		ret = pmic_reg_read(p, MAX77693_SAFEOUT, &val);
+		if (ret)
+			return -1;
 
-	err0 = exynos_pinmux_config(PERIPH_ID_SDMMC0, PINMUX_FLAG_8BIT_MODE);
+		val |= MAX77693_ENSAFEOUT1;
+		ret = pmic_reg_write(p, MAX77693_SAFEOUT, val);
+		if (ret)
+			return -1;
 
-	/*
-	 * MMC device init
-	 * mmc0  : eMMC (8-bit buswidth)
-	 * mmc2  : SD card (4-bit buswidth)
-	 */
-	if (err0)
-		debug("SDMMC0 not configured\n");
-	else
-		err0 = s5p_mmc_init(0, 8);
+		/* PATH: USB */
+		ret = pmic_reg_write(p_muic, MAX77693_MUIC_CONTROL1,
+			MAX77693_MUIC_CTRL1_DN1DP2);
 
-	/* T-flash detect */
-	s5p_gpio_cfg_pin(&gpio2->x3, 4, 0xf);
-	s5p_gpio_set_pull(&gpio2->x3, 4, GPIO_PULL_UP);
+	} else {
+		ret = max77686_set_ldo_mode(p_pmic, 12, OPMODE_LPM);
+		if (ret)
+			return -1;
 
-	/*
-	 * Check the T-flash  detect pin
-	 * GPX3[4] T-flash detect pin
-	 */
-	if (!s5p_gpio_get_value(&gpio2->x3, 4)) {
-		err2 = exynos_pinmux_config(PERIPH_ID_SDMMC2, PINMUX_FLAG_NONE);
-		if (err2)
-			debug("SDMMC2 not configured\n");
-		else
-			err2 = s5p_mmc_init(2, 4);
+		/* PATH: UART */
+		ret = pmic_reg_write(p_muic, MAX77693_MUIC_CONTROL1,
+			MAX77693_MUIC_CTRL1_UT1UR2);
 	}
 
-	return err0 & err2;
+	if (ret)
+		return -1;
+
+	return 0;
 }
 
+struct s3c_plat_otg_data s5pc210_otg_data = {
+	.phy_control	= s5pc210_phy_control,
+	.regs_phy	= EXYNOS4X12_USBPHY_BASE,
+	.regs_otg	= EXYNOS4X12_USBOTG_BASE,
+	.usb_phy_ctrl	= EXYNOS4X12_USBPHY_CONTROL,
+	.usb_flags	= PHY0_SLEEP,
+};
+
+int board_usb_init(int index, enum usb_init_type init)
+{
+	debug("USB_udc_probe\n");
+	return s3c_udc_probe(&s5pc210_otg_data);
+}
+
+#ifdef CONFIG_USB_CABLE_CHECK
+int usb_cable_connected(void)
+{
+	struct pmic *muic = pmic_get("MAX77693_MUIC");
+	if (!muic)
+		return 0;
+
+	return !!muic->chrg->chrg_type(muic);
+}
+#endif
+#endif
+
 static int pmic_init_max77686(void)
 {
 	struct pmic *p = pmic_get("MAX77686_PMIC");
@@ -366,46 +382,7 @@ static int pmic_init_max77686(void)
  */
 
 #ifdef CONFIG_LCD
-static struct mipi_dsim_config dsim_config = {
-	.e_interface		= DSIM_VIDEO,
-	.e_virtual_ch		= DSIM_VIRTUAL_CH_0,
-	.e_pixel_format		= DSIM_24BPP_888,
-	.e_burst_mode		= DSIM_BURST_SYNC_EVENT,
-	.e_no_data_lane		= DSIM_DATA_LANE_4,
-	.e_byte_clk		= DSIM_PLL_OUT_DIV8,
-	.hfp			= 1,
-
-	.p			= 3,
-	.m			= 120,
-	.s			= 1,
-
-	/* D-PHY PLL stable time spec :min = 200usec ~ max 400usec */
-	.pll_stable_time	= 500,
-
-	/* escape clk : 10MHz */
-	.esc_clk		= 20 * 1000000,
-
-	/* stop state holding counter after bta change count 0 ~ 0xfff */
-	.stop_holding_cnt	= 0x7ff,
-	/* bta timeout 0 ~ 0xff */
-	.bta_timeout		= 0xff,
-	/* lp rx timeout 0 ~ 0xffff */
-	.rx_timeout		= 0xffff,
-};
-
-static struct exynos_platform_mipi_dsim dsim_platform_data = {
-	.lcd_panel_info = NULL,
-	.dsim_config = &dsim_config,
-};
-
-static struct mipi_dsim_lcd_device mipi_lcd_device = {
-	.name	= "s6e8ax0",
-	.id	= -1,
-	.bus_id	= 0,
-	.platform_data	= (void *)&dsim_platform_data,
-};
-
-static int mipi_power(void)
+int mipi_power(void)
 {
 	struct pmic *p = pmic_get("MAX77686_PMIC");
 
@@ -421,7 +398,7 @@ void exynos_lcd_power_on(void)
 {
 	struct pmic *p = pmic_get("MAX77686_PMIC");
 
-	gpio1 = (struct exynos4x12_gpio_part1 *)EXYNOS4X12_GPIO_PART1_BASE;
+	gpio1 = (struct exynos4x12_gpio_part1 *)samsung_get_base_gpio_part1();
 
 	/* LCD_2.2V_EN: GPC0[1] */
 	s5p_gpio_set_pull(&gpio1->c0, 1, GPIO_PULL_UP);
@@ -435,7 +412,7 @@ void exynos_lcd_power_on(void)
 
 void exynos_reset_lcd(void)
 {
-	gpio1 = (struct exynos4x12_gpio_part1 *)EXYNOS4X12_GPIO_PART1_BASE;
+	gpio1 = (struct exynos4x12_gpio_part1 *)samsung_get_base_gpio_part1();
 
 	/* reset lcd */
 	s5p_gpio_direction_output(&gpio1->f2, 1, 0);
@@ -443,71 +420,13 @@ void exynos_reset_lcd(void)
 	s5p_gpio_set_value(&gpio1->f2, 1, 1);
 }
 
-vidinfo_t panel_info = {
-	.vl_freq	= 60,
-	.vl_col		= 720,
-	.vl_row		= 1280,
-	.vl_width	= 720,
-	.vl_height	= 1280,
-	.vl_clkp	= CONFIG_SYS_HIGH,
-	.vl_hsp		= CONFIG_SYS_LOW,
-	.vl_vsp		= CONFIG_SYS_LOW,
-	.vl_dp		= CONFIG_SYS_LOW,
-	.vl_bpix	= 5,	/* Bits per pixel, 2^5 = 32 */
-
-	/* s6e8ax0 Panel infomation */
-	.vl_hspw	= 5,
-	.vl_hbpd	= 10,
-	.vl_hfpd	= 10,
-
-	.vl_vspw	= 2,
-	.vl_vbpd	= 1,
-	.vl_vfpd	= 13,
-	.vl_cmd_allow_len = 0xf,
-	.mipi_enabled = 1,
-
-	.dual_lcd_enabled = 0,
-
-	.init_delay	= 0,
-	.power_on_delay = 25,
-	.reset_delay	= 0,
-	.interface_mode = FIMD_RGB_INTERFACE,
-};
-
-void init_panel_info(vidinfo_t *vid)
+void exynos_lcd_misc_init(vidinfo_t *vid)
 {
-	vid->logo_on	= 1;
-	vid->resolution	= HD_RESOLUTION;
-	vid->rgb_mode	= MODE_RGB_P;
-
-	vid->power_on_delay = 30;
-
-	mipi_lcd_device.reverse_panel = 1;
-
 #ifdef CONFIG_TIZEN
 	get_tizen_logo_info(vid);
 #endif
-
-	strcpy(dsim_platform_data.lcd_panel_name, mipi_lcd_device.name);
-	dsim_platform_data.mipi_power = mipi_power;
-	dsim_platform_data.phy_enable = set_mipi_phy_ctrl;
-	dsim_platform_data.lcd_panel_info = (void *)vid;
-	exynos_mipi_dsi_register_lcd_device(&mipi_lcd_device);
-
+#ifdef CONFIG_S6E8AX0
 	s6e8ax0_init();
-
-	exynos_set_dsim_platform_data(&dsim_platform_data);
+#endif
 }
 #endif /* LCD */
-
-#ifdef CONFIG_MISC_INIT_R
-int misc_init_r(void)
-{
-	setenv("model", "GT-I8800");
-	setenv("board", "TRATS2");
-
-	show_hw_revision();
-
-	return 0;
-}
-#endif
diff --git a/board/samsung/universal_c210/Makefile b/board/samsung/universal_c210/Makefile
index 42bde81278..4ceeeb62b5 100644
--- a/board/samsung/universal_c210/Makefile
+++ b/board/samsung/universal_c210/Makefile
@@ -5,24 +5,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS-y	:= universal.o onenand.o
-
-SRCS    := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS-y))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(SOBJS) $(OBJS)
-	$(call cmd_link_o_target, $(SOBJS) $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	:= universal.o onenand.o
diff --git a/board/samsung/universal_c210/universal.c b/board/samsung/universal_c210/universal.c
index 54d0e1e0e3..f9d71b617d 100644
--- a/board/samsung/universal_c210/universal.c
+++ b/board/samsung/universal_c210/universal.c
@@ -13,15 +13,17 @@
 #include <asm/gpio.h>
 #include <asm/arch/adc.h>
 #include <asm/arch/gpio.h>
-#include <asm/arch/mmc.h>
 #include <asm/arch/pinmux.h>
 #include <asm/arch/watchdog.h>
-#include <libtizen.h>
 #include <ld9040.h>
 #include <power/pmic.h>
+#include <usb.h>
 #include <usb/s3c_udc.h>
 #include <asm/arch/cpu.h>
 #include <power/max8998_pmic.h>
+#include <libtizen.h>
+#include <samsung/misc.h>
+#include <usb_mass_storage.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -41,7 +43,7 @@ static int get_hwrev(void)
 
 static void init_pmic_lcd(void);
 
-int power_init_board(void)
+int exynos_power_init(void)
 {
 	int ret;
 
@@ -49,7 +51,7 @@ int power_init_board(void)
 	 * For PMIC the I2C bus is named as I2C5, but it is connected
 	 * to logical I2C adapter 0
 	 */
-	ret = pmic_init(I2C_5);
+	ret = pmic_init(I2C_0);
 	if (ret)
 		return ret;
 
@@ -58,22 +60,6 @@ int power_init_board(void)
 	return 0;
 }
 
-int dram_init(void)
-{
-	gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE) +
-		get_ram_size((long *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE);
-
-	return 0;
-}
-
-void dram_init_banksize(void)
-{
-	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
-	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
-	gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
-	gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
-}
-
 static unsigned short get_adc_value(int channel)
 {
 	struct s5p_adc *adc = (struct s5p_adc *)samsung_get_base_adc();
@@ -158,71 +144,6 @@ static void check_hw_revision(void)
 	board_rev |= hwrev;
 }
 
-#ifdef CONFIG_DISPLAY_BOARDINFO
-int checkboard(void)
-{
-	puts("Board:\tUniversal C210\n");
-	return 0;
-}
-#endif
-
-#ifdef CONFIG_GENERIC_MMC
-int board_mmc_init(bd_t *bis)
-{
-	int err;
-
-	switch (get_hwrev()) {
-	case 0:
-		/*
-		 * Set the low to enable LDO_EN
-		 * But when you use the test board for eMMC booting
-		 * you should set it HIGH since it removes the inverter
-		 */
-		/* MASSMEMORY_EN: XMDMDATA_6: GPE3[6] */
-		s5p_gpio_direction_output(&gpio1->e3, 6, 0);
-		break;
-	default:
-		/*
-		 * Default reset state is High and there's no inverter
-		 * But set it as HIGH to ensure
-		 */
-		/* MASSMEMORY_EN: XMDMADDR_3: GPE1[3] */
-		s5p_gpio_direction_output(&gpio1->e1, 3, 1);
-		break;
-	}
-
-	/*
-	 * MMC device init
-	 * mmc0	 : eMMC (8-bit buswidth)
-	 * mmc2	 : SD card (4-bit buswidth)
-	 */
-	err = exynos_pinmux_config(PERIPH_ID_SDMMC0, PINMUX_FLAG_8BIT_MODE);
-	if (err)
-		debug("SDMMC0 not configured\n");
-	else
-		err = s5p_mmc_init(0, 8);
-
-	/* T-flash detect */
-	s5p_gpio_cfg_pin(&gpio2->x3, 4, 0xf);
-	s5p_gpio_set_pull(&gpio2->x3, 4, GPIO_PULL_UP);
-
-	/*
-	 * Check the T-flash  detect pin
-	 * GPX3[4] T-flash detect pin
-	 */
-	if (!s5p_gpio_get_value(&gpio2->x3, 4)) {
-		err = exynos_pinmux_config(PERIPH_ID_SDMMC2, PINMUX_FLAG_NONE);
-		if (err)
-			debug("SDMMC2 not configured\n");
-		else
-			err = s5p_mmc_init(2, 4);
-	}
-
-	return err;
-
-}
-#endif
-
 #ifdef CONFIG_USB_GADGET
 static int s5pc210_phy_control(int on)
 {
@@ -270,7 +191,20 @@ struct s3c_plat_otg_data s5pc210_otg_data = {
 };
 #endif
 
-int board_early_init_f(void)
+int board_usb_init(int index, enum usb_init_type init)
+{
+	debug("USB_udc_probe\n");
+	return s3c_udc_probe(&s5pc210_otg_data);
+}
+
+#ifdef CONFIG_USB_CABLE_CHECK
+int usb_cable_connected(void)
+{
+	return 0;
+}
+#endif
+
+int exynos_early_init_f(void)
 {
 	wdt_stop();
 
@@ -411,6 +345,11 @@ void exynos_cfg_lcd_gpio(void)
 	spi_init();
 }
 
+int mipi_power(void)
+{
+	return 0;
+}
+
 void exynos_reset_lcd(void)
 {
 	s5p_gpio_set_value(&gpio2->y4, 5, 1);
@@ -435,39 +374,6 @@ void exynos_lcd_power_on(void)
 	pmic_set_output(p, MAX8998_REG_ONOFF2, MAX8998_LDO7, LDO_ON);
 }
 
-vidinfo_t panel_info = {
-	.vl_freq	= 60,
-	.vl_col		= 480,
-	.vl_row		= 800,
-	.vl_width	= 480,
-	.vl_height	= 800,
-	.vl_clkp	= CONFIG_SYS_HIGH,
-	.vl_hsp		= CONFIG_SYS_HIGH,
-	.vl_vsp		= CONFIG_SYS_HIGH,
-	.vl_dp		= CONFIG_SYS_HIGH,
-
-	.vl_bpix	= 5,	/* Bits per pixel */
-
-	/* LD9040 LCD Panel */
-	.vl_hspw	= 2,
-	.vl_hbpd	= 16,
-	.vl_hfpd	= 16,
-
-	.vl_vspw	= 2,
-	.vl_vbpd	= 8,
-	.vl_vfpd	= 8,
-	.vl_cmd_allow_len = 0xf,
-
-	.win_id		= 0,
-	.dual_lcd_enabled = 0,
-
-	.init_delay	= 0,
-	.power_on_delay = 10000,
-	.reset_delay	= 10000,
-	.interface_mode = FIMD_RGB_INTERFACE,
-	.mipi_enabled	= 0,
-};
-
 void exynos_cfg_ldo(void)
 {
 	ld9040_cfg_ldo();
@@ -478,30 +384,32 @@ void exynos_enable_ldo(unsigned int onoff)
 	ld9040_enable_ldo(onoff);
 }
 
-void init_panel_info(vidinfo_t *vid)
-{
-	vid->logo_on	= 1;
-	vid->resolution	= HD_RESOLUTION;
-	vid->rgb_mode	= MODE_RGB_P;
-
-#ifdef CONFIG_TIZEN
-	get_tizen_logo_info(vid);
-#endif
-
-	/* for LD9040. */
-	vid->pclk_name = 1;	/* MPLL */
-	vid->sclk_div = 1;
-
-	setenv("lcdinfo", "lcd=ld9040");
-}
-
-int board_init(void)
+int exynos_init(void)
 {
 	gpio1 = (struct exynos4_gpio_part1 *) EXYNOS4_GPIO_PART1_BASE;
 	gpio2 = (struct exynos4_gpio_part2 *) EXYNOS4_GPIO_PART2_BASE;
 
 	gd->bd->bi_arch_number = MACH_TYPE_UNIVERSAL_C210;
-	gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
+
+	switch (get_hwrev()) {
+	case 0:
+		/*
+		 * Set the low to enable LDO_EN
+		 * But when you use the test board for eMMC booting
+		 * you should set it HIGH since it removes the inverter
+		 */
+		/* MASSMEMORY_EN: XMDMDATA_6: GPE3[6] */
+		s5p_gpio_direction_output(&gpio1->e3, 6, 0);
+		break;
+	default:
+		/*
+		 * Default reset state is High and there's no inverter
+		 * But set it as HIGH to ensure
+		 */
+		/* MASSMEMORY_EN: XMDMADDR_3: GPE1[3] */
+		s5p_gpio_direction_output(&gpio1->e1, 3, 1);
+		break;
+	}
 
 #ifdef CONFIG_SOFT_SPI
 	soft_spi_init();
@@ -511,3 +419,16 @@ int board_init(void)
 
 	return 0;
 }
+
+void exynos_lcd_misc_init(vidinfo_t *vid)
+{
+#ifdef CONFIG_TIZEN
+	get_tizen_logo_info(vid);
+#endif
+
+	/* for LD9040. */
+	vid->pclk_name = 1;	/* MPLL */
+	vid->sclk_div = 1;
+
+	setenv("lcdinfo", "lcd=ld9040");
+}
diff --git a/board/sandbox/sandbox/Makefile b/board/sandbox/sandbox/Makefile
index 3d490b8ef8..a0b9880d6e 100644
--- a/board/sandbox/sandbox/Makefile
+++ b/board/sandbox/sandbox/Makefile
@@ -4,23 +4,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	:= $(BOARD).o
-
-SRCS	:= $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	:= sandbox.o
diff --git a/board/sandbox/sandbox/README.sandbox b/board/sandbox/sandbox/README.sandbox
index 30b05416a7..69895574ff 100644
--- a/board/sandbox/sandbox/README.sandbox
+++ b/board/sandbox/sandbox/README.sandbox
@@ -31,6 +31,60 @@ the console. It does not set the terminal into raw mode, so cursor keys and
 history will not work yet.
 
 
+SPI Emulation
+-------------
+
+Sandbox supports SPI and SPI flash emulation.
+
+This is controlled by the spi_sf argument, the format of which is:
+
+   bus:cs:device:file
+
+   bus    - SPI bus number
+   cs     - SPI chip select number
+   device - SPI device emulation name
+   file   - File on disk containing the data
+
+For example:
+
+ dd if=/dev/zero of=spi.bin bs=1M count=4
+ ./u-boot --spi_sf 0:0:M25P16:spi.bin
+
+With this setup you can issue SPI flash commands as normal:
+
+=>sf probe
+SF: Detected M25P16 with page size 64 KiB, total 2 MiB
+=>sf read 0 0 10000
+SF: 65536 bytes @ 0x0 Read: OK
+=>
+
+Since this is a full SPI emulation (rather than just flash), you can
+also use low-level SPI commands:
+
+=>sspi 0:0 32 9f
+FF202015
+
+This is issuing a READ_ID command and getting back 20 (ST Micro) part
+0x2015 (the M25P16).
+
+Drivers are connected to a particular bus/cs using sandbox's state
+structure (see the 'spi' member). A set of operations must be provided
+for each driver.
+
+
+Configuration settings for the curious are:
+
+CONFIG_SANDBOX_SPI_MAX_BUS
+	The maximum number of SPI buses supported by the driver (default 1).
+
+CONFIG_SANDBOX_SPI_MAX_CS
+	The maximum number of chip selects supported by the driver
+	(default 10).
+
+CONFIG_SPI_IDLE_VAL
+	The idle value on the SPI bus
+
+
 Tests
 -----
 
diff --git a/board/sandbox/sandbox/sandbox.c b/board/sandbox/sandbox/sandbox.c
index f471cb7212..e4d4e021bc 100644
--- a/board/sandbox/sandbox/sandbox.c
+++ b/board/sandbox/sandbox/sandbox.c
@@ -4,8 +4,10 @@
  */
 
 #include <common.h>
-
+#include <cros_ec.h>
+#include <dm.h>
 #include <os.h>
+#include <asm/u-boot-sandbox.h>
 
 /*
  * Pointer to initial global data area
@@ -14,32 +16,68 @@
  */
 gd_t *gd;
 
+/* Add a simple GPIO device */
+U_BOOT_DEVICE(gpio_sandbox) = {
+	.name = "gpio_sandbox",
+};
+
 void flush_cache(unsigned long start, unsigned long size)
 {
 }
 
-ulong get_tbclk(void)
+unsigned long timer_read_counter(void)
 {
-	return CONFIG_SYS_HZ;
+	return os_get_nsec() / 1000;
 }
 
-unsigned long long get_ticks(void)
+int dram_init(void)
 {
-	return get_timer(0);
+	gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
+	return 0;
 }
 
-ulong get_timer(ulong base)
+#ifdef CONFIG_BOARD_EARLY_INIT_F
+int board_early_init_f(void)
 {
-	return (os_get_nsec() / 1000000) - base;
+#ifdef CONFIG_VIDEO_SANDBOX_SDL
+	int ret;
+
+	ret = sandbox_lcd_sdl_early_init();
+	if (ret) {
+		puts("Could not init sandbox LCD emulation\n");
+		return ret;
+	}
+#endif
+
+	return 0;
 }
+#endif
 
-int timer_init(void)
+int arch_early_init_r(void)
 {
+#ifdef CONFIG_CROS_EC
+	if (cros_ec_board_init()) {
+		printf("%s: Failed to init EC\n", __func__);
+		return 0;
+	}
+#endif
+
 	return 0;
 }
 
-int dram_init(void)
+#ifdef CONFIG_BOARD_LATE_INIT
+int board_late_init(void)
 {
-	gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
+	if (cros_ec_get_error()) {
+		/* Force console on */
+		gd->flags &= ~GD_FLG_SILENT;
+
+		printf("cros-ec communications failure %d\n",
+		       cros_ec_get_error());
+		puts("\nPlease reset with Power+Refresh\n\n");
+		panic("Cannot init cros-ec device");
+		return -1;
+	}
 	return 0;
 }
+#endif
diff --git a/board/sandburst/karef/Makefile b/board/sandburst/karef/Makefile
index af758f947e..ce29b4100e 100644
--- a/board/sandburst/karef/Makefile
+++ b/board/sandburst/karef/Makefile
@@ -9,37 +9,8 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-ifneq ($(OBJTREE),$(SRCTREE))
-$(shell mkdir -p $(obj)../common)
-endif
-
 # TBS: add for debugging purposes
-BUILDUSER := $(shell whoami)
-FORCEBUILD := $(shell rm -f $(LIB) $(BOARD).o)
-
-CFLAGS += -DBUILDUSER='"$(BUILDUSER)"'
-# TBS: end debugging
-
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	= $(BOARD).o ../common/flash.o ../common/sb_common.o
-
-SOBJS	= init.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(OBJS) $(SOBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
+ccflags-y += -DBUILDUSER='"$(shell whoami)"'
 
-#########################################################################
+obj-y	= karef.o ../common/flash.o ../common/sb_common.o
+extra-y	+= init.o
diff --git a/board/sandburst/metrobox/Makefile b/board/sandburst/metrobox/Makefile
index 163f2b98da..2c1028bd2b 100644
--- a/board/sandburst/metrobox/Makefile
+++ b/board/sandburst/metrobox/Makefile
@@ -8,36 +8,8 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-ifneq ($(OBJTREE),$(SRCTREE))
-$(shell mkdir -p $(obj)../common)
-endif
-
 # TBS: add for debugging purposes
-BUILDUSER := $(shell whoami)
-FORCEBUILD := $(shell rm -f $(LIB) $(BOARD).o)
-
-CFLAGS += -DBUILDUSER='"$(BUILDUSER)"'
-# TBS: end debugging
-
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	= $(BOARD).o ../common/flash.o ../common/sb_common.o
-SOBJS	= init.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(OBJS) $(SOBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
+ccflags-y += -DBUILDUSER='"$(shell whoami)"'
 
-#########################################################################
+obj-y	= metrobox.o ../common/flash.o ../common/sb_common.o
+extra-y	+= init.o
diff --git a/board/sandisk/sansa_fuze_plus/Makefile b/board/sandisk/sansa_fuze_plus/Makefile
index 571cc077fa..667600d020 100644
--- a/board/sandisk/sansa_fuze_plus/Makefile
+++ b/board/sandisk/sansa_fuze_plus/Makefile
@@ -5,27 +5,8 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
 ifndef	CONFIG_SPL_BUILD
-COBJS	:= sfp.o
+obj-y	:= sfp.o
 else
-COBJS	:= spl_boot.o
+obj-y	:= spl_boot.o
 endif
-
-SRCS	:= $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
diff --git a/board/sandpoint/Makefile b/board/sandpoint/Makefile
index 871865b6ee..58f5a8905b 100644
--- a/board/sandpoint/Makefile
+++ b/board/sandpoint/Makefile
@@ -5,24 +5,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	= $(BOARD).o flash.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	= sandpoint.o flash.o
diff --git a/board/sandpoint/speed.h b/board/sandpoint/speed.h
deleted file mode 100644
index f1b10bf25e..0000000000
--- a/board/sandpoint/speed.h
+++ /dev/null
@@ -1,38 +0,0 @@
-/*
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-/*-----------------------------------------------------------------------
- * Timer value for timer 2, ICLK = 10
- *
- * SPEED_FCOUNT2 =  GCLK / (16 * (TIMER_TMR_PS + 1))
- * SPEED_TMR3_PS = (GCLK / (16 * SPEED_FCOUNT3)) - 1
- *
- * SPEED_FCOUNT2	timer 2 counting frequency
- * GCLK			CPU clock
- * SPEED_TMR2_PS	prescaler
- */
-#define SPEED_TMR2_PS	(250 - 1)	/* divide by 250	*/
-
-/*-----------------------------------------------------------------------
- * Timer value for PIT
- *
- * PIT_TIME = SPEED_PITC / PITRTCLK
- * PITRTCLK = 8192
- */
-#define SPEED_PITC	(82 << 16)	/* start counting from 82	*/
-
-/*
- * The new value for PTA is calculated from
- *
- *	PTA = (gclk * Trefresh) / (2 ^ (2 * DFBRG) * PTP * NCS)
- *
- * gclk		CPU clock (not bus clock !)
- * Trefresh	Refresh cycle * 4 (four word bursts used)
- * DFBRG	For normal mode (no clock reduction) always 0
- * PTP		Prescaler (already adjusted for no. of banks and 4K / 8K refresh)
- * NCS		Number of SDRAM banks (chip selects) on this UPM.
- */
diff --git a/board/sbc405/Makefile b/board/sbc405/Makefile
index 0d202ac071..3f2b0e24ca 100644
--- a/board/sbc405/Makefile
+++ b/board/sbc405/Makefile
@@ -5,24 +5,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	= $(BOARD).o strataflash.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(OBJS) $(SOBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	= sbc405.o strataflash.o
diff --git a/board/sbc8349/Makefile b/board/sbc8349/Makefile
index 9a5b84a5a7..3b2c389484 100644
--- a/board/sbc8349/Makefile
+++ b/board/sbc8349/Makefile
@@ -4,26 +4,5 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS-y += $(BOARD).o
-COBJS-$(CONFIG_PCI) += pci.o
-
-COBJS   := $(COBJS-y)
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y += sbc8349.o
+obj-$(CONFIG_PCI) += pci.o
diff --git a/board/sbc8548/Makefile b/board/sbc8548/Makefile
index ecffaa9033..4c9b6cd60c 100644
--- a/board/sbc8548/Makefile
+++ b/board/sbc8548/Makefile
@@ -8,27 +8,7 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS-y	+= $(BOARD).o
-COBJS-y	+= law.o
-COBJS-y	+= tlb.o
-COBJS-$(CONFIG_FSL_DDR2) += ddr.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS-y))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	+= sbc8548.o
+obj-y	+= law.o
+obj-y	+= tlb.o
+obj-$(CONFIG_SYS_FSL_DDR2) += ddr.o
diff --git a/board/sbc8548/ddr.c b/board/sbc8548/ddr.c
index 9508561133..24cc776a25 100644
--- a/board/sbc8548/ddr.c
+++ b/board/sbc8548/ddr.c
@@ -9,8 +9,8 @@
 #include <common.h>
 #include <i2c.h>
 
-#include <asm/fsl_ddr_sdram.h>
-#include <asm/fsl_ddr_dimm_params.h>
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr_dimm_params.h>
 
 void fsl_ddr_board_options(memctl_options_t *popts,
 				dimm_params_t *pdimm,
@@ -91,7 +91,8 @@ void get_spd(generic_spd_eeprom_t *spd, u8 i2c_address)
  */
 phys_size_t fixed_sdram(void)
 {
-	volatile ccsr_ddr_t *ddr = (void *)(CONFIG_SYS_MPC8xxx_DDR_ADDR);
+	struct ccsr_ddr __iomem *ddr =
+		(struct ccsr_ddr __iomem *)(CONFIG_SYS_FSL_DDR_ADDR);
 
 	out_be32(&ddr->cs0_bnds,	0x0000007f);
 	out_be32(&ddr->cs1_bnds,	0x008000ff);
diff --git a/board/sbc8548/sbc8548.c b/board/sbc8548/sbc8548.c
index 3cd945f2c2..d584276253 100644
--- a/board/sbc8548/sbc8548.c
+++ b/board/sbc8548/sbc8548.c
@@ -15,7 +15,7 @@
 #include <asm/processor.h>
 #include <asm/immap_85xx.h>
 #include <asm/fsl_pci.h>
-#include <asm/fsl_ddr_sdram.h>
+#include <fsl_ddr_sdram.h>
 #include <asm/fsl_serdes.h>
 #include <spd_sdram.h>
 #include <netdev.h>
diff --git a/board/sbc8641d/Makefile b/board/sbc8641d/Makefile
index 0cbc0d0a90..a9b20266bc 100644
--- a/board/sbc8641d/Makefile
+++ b/board/sbc8641d/Makefile
@@ -5,26 +5,6 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS-y	+= $(BOARD).o
-COBJS-y	+= law.o
-COBJS-$(CONFIG_FSL_DDR2) += ddr.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS-y))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude ($obj).depend
-
-#########################################################################
+obj-y	+= sbc8641d.o
+obj-y	+= law.o
+obj-$(CONFIG_SYS_FSL_DDR2) += ddr.o
diff --git a/board/sbc8641d/ddr.c b/board/sbc8641d/ddr.c
index 996ffe206d..b31ea3432e 100644
--- a/board/sbc8641d/ddr.c
+++ b/board/sbc8641d/ddr.c
@@ -8,8 +8,8 @@
 
 #include <common.h>
 
-#include <asm/fsl_ddr_sdram.h>
-#include <asm/fsl_ddr_dimm_params.h>
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr_dimm_params.h>
 
 void fsl_ddr_board_options(memctl_options_t *popts,
 				dimm_params_t *pdimm,
diff --git a/board/sbc8641d/sbc8641d.c b/board/sbc8641d/sbc8641d.c
index 0b5e8dc17e..4906be4889 100644
--- a/board/sbc8641d/sbc8641d.c
+++ b/board/sbc8641d/sbc8641d.c
@@ -18,7 +18,7 @@
 #include <asm/processor.h>
 #include <asm/immap_86xx.h>
 #include <asm/fsl_pci.h>
-#include <asm/fsl_ddr_sdram.h>
+#include <fsl_ddr_sdram.h>
 #include <asm/fsl_serdes.h>
 #include <libfdt.h>
 #include <fdt_support.h>
@@ -93,7 +93,7 @@ long int fixed_sdram (void)
 {
 #if !defined(CONFIG_SYS_RAMBOOT)
 	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
-	volatile ccsr_ddr_t *ddr = &immap->im_ddr1;
+	volatile struct ccsr_ddr *ddr = &immap->im_ddr1;
 
 	ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS;
 	ddr->cs1_bnds = CONFIG_SYS_DDR_CS1_BNDS;
@@ -111,7 +111,7 @@ long int fixed_sdram (void)
 	ddr->sdram_cfg_2 = CONFIG_SYS_DDR_CFG_2;
 	ddr->sdram_mode = CONFIG_SYS_DDR_MODE_1;
 	ddr->sdram_mode_2 = CONFIG_SYS_DDR_MODE_2;
-	ddr->sdram_mode_cntl = CONFIG_SYS_DDR_MODE_CTL;
+	ddr->sdram_md_cntl = CONFIG_SYS_DDR_MODE_CTL;
 	ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL;
 	ddr->sdram_data_init = CONFIG_SYS_DDR_DATA_INIT;
 	ddr->sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL;
@@ -142,7 +142,7 @@ long int fixed_sdram (void)
 	ddr->sdram_cfg_2 = CONFIG_SYS_DDR2_CFG_2;
 	ddr->sdram_mode = CONFIG_SYS_DDR2_MODE_1;
 	ddr->sdram_mode_2 = CONFIG_SYS_DDR2_MODE_2;
-	ddr->sdram_mode_cntl = CONFIG_SYS_DDR2_MODE_CTL;
+	ddr->sdram_md_cntl = CONFIG_SYS_DDR2_MODE_CTL;
 	ddr->sdram_interval = CONFIG_SYS_DDR2_INTERVAL;
 	ddr->sdram_data_init = CONFIG_SYS_DDR2_DATA_INIT;
 	ddr->sdram_clk_cntl = CONFIG_SYS_DDR2_CLK_CTRL;
diff --git a/board/sc3/Makefile b/board/sc3/Makefile
index 7369072617..c1d163ee42 100644
--- a/board/sc3/Makefile
+++ b/board/sc3/Makefile
@@ -5,25 +5,5 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	= $(BOARD).o sc3nand.o
-SOBJS	= init.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(OBJS) $(SOBJS)
-	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	= sc3.o sc3nand.o
+obj-y	+= init.o
diff --git a/board/sc3/init.S b/board/sc3/init.S
index 46323d2688..097aa4a5e7 100644
--- a/board/sc3/init.S
+++ b/board/sc3/init.S
@@ -4,8 +4,6 @@
 #include <config.h>
 #include <asm/ppc4xx.h>
 
-#define _LINUX_CONFIG_H 1	/* avoid reading Linux autoconf.h file	*/
-
 #include <ppc_asm.tmpl>
 #include <ppc_defs.h>
 
diff --git a/board/scb9328/Makefile b/board/scb9328/Makefile
index 779507d081..0b08f1a871 100644
--- a/board/scb9328/Makefile
+++ b/board/scb9328/Makefile
@@ -5,25 +5,5 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	:= scb9328.o flash.o
-SOBJS	:= lowlevel_init.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
-	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	:= scb9328.o flash.o
+obj-y	+= lowlevel_init.o
diff --git a/board/schulercontrol/sc_sps_1/Makefile b/board/schulercontrol/sc_sps_1/Makefile
index 81482e30da..df72fc9f55 100644
--- a/board/schulercontrol/sc_sps_1/Makefile
+++ b/board/schulercontrol/sc_sps_1/Makefile
@@ -5,27 +5,8 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
 ifndef	CONFIG_SPL_BUILD
-COBJS	:= sc_sps_1.o
+obj-y	:= sc_sps_1.o
 else
-COBJS	:= spl_boot.o
+obj-y	:= spl_boot.o
 endif
-
-SRCS	:= $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
diff --git a/board/sheldon/simpc8313/Makefile b/board/sheldon/simpc8313/Makefile
index b9fa864bb5..a824c41d9c 100644
--- a/board/sheldon/simpc8313/Makefile
+++ b/board/sheldon/simpc8313/Makefile
@@ -5,24 +5,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	:= $(BOARD).o sdram.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	:= simpc8313.o sdram.o
diff --git a/board/shmin/Makefile b/board/shmin/Makefile
index 0377723f23..daf36deed0 100644
--- a/board/shmin/Makefile
+++ b/board/shmin/Makefile
@@ -6,25 +6,5 @@
 #
 # SPDX-License-Identifier:	GPL-2.0+
 
-include $(TOPDIR)/config.mk
-
-LIB	= lib$(BOARD).o
-
-OBJS	:= shmin.o
-SOBJS	:= lowlevel_init.o
-
-LIB	:= $(addprefix $(obj),$(LIB))
-OBJS	:= $(addprefix $(obj),$(OBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
-	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	:= shmin.o
+obj-y	+= lowlevel_init.o
diff --git a/board/siemens/common/board.c b/board/siemens/common/board.c
index 6279c3281c..7e8731bb3b 100644
--- a/board/siemens/common/board.c
+++ b/board/siemens/common/board.c
@@ -42,7 +42,7 @@ void set_mux_conf_regs(void)
 {
 	/* Initalize the board header */
 	enable_i2c0_pin_mux();
-	i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
+	i2c_set_bus_num(0);
 	if (read_eeprom() < 0)
 		puts("Could not get board ID.\n");
 
@@ -67,7 +67,7 @@ int board_init(void)
 #if defined(CONFIG_HW_WATCHDOG)
 	hw_watchdog_init();
 #endif /* defined(CONFIG_HW_WATCHDOG) */
-	i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
+	i2c_set_bus_num(0);
 	if (read_eeprom() < 0)
 		puts("Could not get board ID.\n");
 
@@ -159,13 +159,4 @@ U_BOOT_CMD(
 	"Sends U-Boot into infinite loop",
 	""
 );
-
-#ifndef CONFIG_SYS_DCACHE_OFF
-void enable_caches(void)
-{
-	printf("Enable d-cache\n");
-	/* Enable D-cache. I-cache is already enabled in start.S */
-	dcache_enable();
-}
-#endif /* CONFIG_SYS_DCACHE_OFF */
 #endif /* !CONFIG_SPL_BUILD */
diff --git a/board/siemens/common/factoryset.c b/board/siemens/common/factoryset.c
index eda9141c54..266dbbbb5f 100644
--- a/board/siemens/common/factoryset.c
+++ b/board/siemens/common/factoryset.c
@@ -15,7 +15,8 @@
 #include <asm/arch/sys_proto.h>
 #include <asm/unaligned.h>
 #include <net.h>
-#include <usbdescriptors.h>
+#include <errno.h>
+#include <g_dnl.h>
 #include "factoryset.h"
 
 #define EEPR_PG_SZ		0x80
@@ -224,8 +225,20 @@ int factoryset_read_eeprom(int i2c_addr)
 					MAX_STRING_LENGTH)) {
 		debug("display name: %s\n", factory_dat.disp_name);
 	}
-
 #endif
+	if (0 <= get_factory_record_val(cp, size, (uchar *)"DEV",
+					(uchar *)"num", factory_dat.serial,
+					MAX_STRING_LENGTH)) {
+		debug("serial number: %s\n", factory_dat.serial);
+	}
+	if (0 <= get_factory_record_val(cp, size, (uchar *)"DEV",
+					(uchar *)"ver", buf,
+					MAX_STRING_LENGTH)) {
+		factory_dat.version = simple_strtoul((char *)buf,
+							    NULL, 16);
+		debug("version number: %d\n", factory_dat.version);
+	}
+
 	return 0;
 
 err:
@@ -275,10 +288,17 @@ int factoryset_setenv(void)
 	return ret;
 }
 
-int g_dnl_bind_fixup(struct usb_device_descriptor *dev)
+int g_dnl_bind_fixup(struct usb_device_descriptor *dev, const char *name)
 {
 	put_unaligned(factory_dat.usb_vendor_id, &dev->idVendor);
 	put_unaligned(factory_dat.usb_product_id, &dev->idProduct);
+	g_dnl_set_serialnumber((char *)factory_dat.serial);
+
 	return 0;
 }
+
+int g_dnl_get_board_bcd_device_number(int gcnum)
+{
+	return factory_dat.version;
+}
 #endif /* defined(CONFIG_SPL_BUILD) */
diff --git a/board/siemens/common/factoryset.h b/board/siemens/common/factoryset.h
index 445f3842da..4d6de10f52 100644
--- a/board/siemens/common/factoryset.h
+++ b/board/siemens/common/factoryset.h
@@ -18,6 +18,8 @@ struct factorysetcontainer {
 #if defined(CONFIG_VIDEO)
 	unsigned char disp_name[MAX_STRING_LENGTH];
 #endif
+	unsigned char serial[MAX_STRING_LENGTH];
+	int version;
 };
 
 int factoryset_read_eeprom(int i2c_addr);
diff --git a/board/siemens/corvus/Makefile b/board/siemens/corvus/Makefile
new file mode 100644
index 0000000000..f3ebf77f1b
--- /dev/null
+++ b/board/siemens/corvus/Makefile
@@ -0,0 +1,18 @@
+#
+# Makefile for siemens CORVUS (AT91SAM9G45) based board
+# (C) Copyright 2013 Siemens AG
+#
+# Based on:
+# U-Boot file: board/atmel/at91sam9m10g45ek/Makefile
+#
+# (C) Copyright 2003-2008
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# (C) Copyright 2008
+# Stelian Pop <stelian@popies.net>
+# Lead Tech Design <www.leadtechdesign.com>
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y += board.o
diff --git a/board/siemens/corvus/board.c b/board/siemens/corvus/board.c
new file mode 100644
index 0000000000..f1e93ef063
--- /dev/null
+++ b/board/siemens/corvus/board.c
@@ -0,0 +1,195 @@
+/*
+ * Board functions for Siemens CORVUS (AT91SAM9G45) based board
+ * (C) Copyright 2013 Siemens AG
+ *
+ * Based on:
+ * U-Boot file: board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c
+ * (C) Copyright 2007-2008
+ * Stelian Pop <stelian@popies.net>
+ * Lead Tech Design <www.leadtechdesign.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/at91sam9g45_matrix.h>
+#include <asm/arch/at91sam9_smc.h>
+#include <asm/arch/at91_common.h>
+#include <asm/arch/at91_pmc.h>
+#include <asm/arch/at91_rstc.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/clk.h>
+#include <lcd.h>
+#include <atmel_lcdc.h>
+#if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB)
+#include <net.h>
+#endif
+#include <netdev.h>
+#include <spi.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#ifdef CONFIG_CMD_NAND
+static void corvus_nand_hw_init(void)
+{
+	struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
+	struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
+	struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
+	unsigned long csa;
+
+	/* Enable CS3 */
+	csa = readl(&matrix->ebicsa);
+	csa |= AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA;
+	writel(csa, &matrix->ebicsa);
+
+	/* Configure SMC CS3 for NAND/SmartMedia */
+	writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) |
+	       AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0),
+	       &smc->cs[3].setup);
+	writel(AT91_SMC_PULSE_NWE(4) | AT91_SMC_PULSE_NCS_WR(3) |
+	       AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(2),
+	       &smc->cs[3].pulse);
+	writel(AT91_SMC_CYCLE_NWE(7) | AT91_SMC_CYCLE_NRD(4),
+	       &smc->cs[3].cycle);
+	writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
+	       AT91_SMC_MODE_EXNW_DISABLE |
+#ifdef CONFIG_SYS_NAND_DBW_16
+	       AT91_SMC_MODE_DBW_16 |
+#else /* CONFIG_SYS_NAND_DBW_8 */
+	       AT91_SMC_MODE_DBW_8 |
+#endif
+	       AT91_SMC_MODE_TDF_CYCLE(3),
+	       &smc->cs[3].mode);
+
+	writel(1 << ATMEL_ID_PIOC, &pmc->pcer);
+
+	/* Configure RDY/BSY */
+	at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
+
+	/* Enable NandFlash */
+	at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
+}
+#endif
+
+#ifdef CONFIG_CMD_USB
+static void taurus_usb_hw_init(void)
+{
+	struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
+
+	writel(1 << ATMEL_ID_PIODE, &pmc->pcer);
+
+	at91_set_gpio_output(AT91_PIN_PD1, 0);
+	at91_set_gpio_output(AT91_PIN_PD3, 0);
+}
+#endif
+
+#ifdef CONFIG_MACB
+static void corvus_macb_hw_init(void)
+{
+	struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
+
+	/* Enable clock */
+	writel(1 << ATMEL_ID_EMAC, &pmc->pcer);
+
+	/*
+	 * Disable pull-up on:
+	 *      RXDV (PA15) => PHY normal mode (not Test mode)
+	 *      ERX0 (PA12) => PHY ADDR0
+	 *      ERX1 (PA13) => PHY ADDR1 => PHYADDR = 0x0
+	 *
+	 * PHY has internal pull-down
+	 */
+	at91_set_pio_pullup(AT91_PIO_PORTA, 15, 0);
+	at91_set_pio_pullup(AT91_PIO_PORTA, 12, 0);
+	at91_set_pio_pullup(AT91_PIO_PORTA, 13, 0);
+
+	at91_phy_reset();
+
+	/* Re-enable pull-up */
+	at91_set_pio_pullup(AT91_PIO_PORTA, 15, 1);
+	at91_set_pio_pullup(AT91_PIO_PORTA, 12, 1);
+	at91_set_pio_pullup(AT91_PIO_PORTA, 13, 1);
+
+	/* And the pins. */
+	at91_macb_hw_init();
+}
+#endif
+
+int board_early_init_f(void)
+{
+	at91_seriald_hw_init();
+	return 0;
+}
+
+int board_init(void)
+{
+	/* address of boot parameters */
+	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+
+#ifdef CONFIG_CMD_NAND
+	corvus_nand_hw_init();
+#endif
+#ifdef CONFIG_ATMEL_SPI
+	at91_spi0_hw_init(1 << 4);
+#endif
+#ifdef CONFIG_HAS_DATAFLASH
+	at91_spi0_hw_init(1 << 0);
+#endif
+#ifdef CONFIG_MACB
+	corvus_macb_hw_init();
+#endif
+#ifdef CONFIG_CMD_USB
+	taurus_usb_hw_init();
+#endif
+	return 0;
+}
+
+int dram_init(void)
+{
+	gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
+				    CONFIG_SYS_SDRAM_SIZE);
+	return 0;
+}
+
+int board_eth_init(bd_t *bis)
+{
+	int rc = 0;
+#ifdef CONFIG_MACB
+	rc = macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC, 0x00);
+#endif
+	return rc;
+}
+
+/* SPI chip select control */
+int spi_cs_is_valid(unsigned int bus, unsigned int cs)
+{
+	return bus == 0 && cs < 2;
+}
+
+void spi_cs_activate(struct spi_slave *slave)
+{
+	switch (slave->cs) {
+	case 1:
+			at91_set_gpio_output(AT91_PIN_PB18, 0);
+			break;
+	case 0:
+	default:
+			at91_set_gpio_output(AT91_PIN_PB3, 0);
+			break;
+	}
+}
+
+void spi_cs_deactivate(struct spi_slave *slave)
+{
+	switch (slave->cs) {
+	case 1:
+			at91_set_gpio_output(AT91_PIN_PB18, 1);
+			break;
+	case 0:
+	default:
+			at91_set_gpio_output(AT91_PIN_PB3, 1);
+			break;
+	}
+}
diff --git a/board/siemens/dxr2/Makefile b/board/siemens/dxr2/Makefile
index a09b467d5a..f15993216b 100644
--- a/board/siemens/dxr2/Makefile
+++ b/board/siemens/dxr2/Makefile
@@ -11,39 +11,11 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-ifneq ($(OBJTREE),$(SRCTREE))
-$(shell mkdir -p $(obj)../common)
-endif
-
-LIB	= $(obj)lib$(BOARD).o
-
 ifdef CONFIG_SPL_BUILD
-COBJS	:= mux.o
+obj-y	:= mux.o
 endif
 
-COBJS	+= board.o
+obj-y	+= board.o
 ifndef CONFIG_SPL_BUILD
-COBJS += ../common/factoryset.o
+obj-y += ../common/factoryset.o
 endif
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
-	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
-
-clean:
-	rm -f $(SOBJS) $(OBJS)
-
-distclean:	clean
-	rm -f $(LIB) core *.bak $(obj).depend
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
diff --git a/board/siemens/dxr2/board.c b/board/siemens/dxr2/board.c
index af9d84f128..38ac93d795 100644
--- a/board/siemens/dxr2/board.c
+++ b/board/siemens/dxr2/board.c
@@ -38,11 +38,11 @@ DECLARE_GLOBAL_DATA_PTR;
 
 #ifdef CONFIG_SPL_BUILD
 static struct dxr2_baseboard_id __attribute__((section(".data"))) settings;
-
+/* @303MHz-i0 */
 const struct ddr3_data ddr3_default = {
-	0x33524444, 0x56312e33, 0x0100, 0x0001, 0x003A, 0x008A, 0x010B,
-	0x00C4, 0x0888A39B, 0x26247FDA, 0x501F821F, 0x0006, 0x61C04AB2,
-	0x00000618,
+	0x33524444, 0x56312e34, 0x0080, 0x0000, 0x0038, 0x003E, 0x00A4,
+	0x0075, 0x0888A39B, 0x26247FDA, 0x501F821F, 0x00100206, 0x61A44A32,
+	0x00000618, 0x0000014A,
 };
 
 static void set_default_ddr3_timings(void)
@@ -73,6 +73,7 @@ static void print_ddr3_timings(void)
 
 	PRINTARGS(sdram_config);
 	PRINTARGS(ref_ctrl);
+	PRINTARGS(ioctr_val);
 }
 
 static void print_chip_data(void)
@@ -139,14 +140,14 @@ struct emif_regs dxr2_ddr3_emif_reg_data = {
 };
 
 struct ddr_data dxr2_ddr3_data = {
-	.datadldiff0 = PHY_DLL_LOCK_DIFF,
 };
 
 struct cmd_control dxr2_ddr3_cmd_ctrl_data = {
-	.cmd0dldiff = 0,
-	.cmd1dldiff = 0,
-	.cmd2dldiff = 0,
 };
+
+struct ctrl_ioregs dxr2_ddr3_ioregs = {
+};
+
 	/* pass values from eeprom */
 	dxr2_ddr3_emif_reg_data.sdram_tim1 = settings.ddr3.sdram_tim1;
 	dxr2_ddr3_emif_reg_data.sdram_tim2 = settings.ddr3.sdram_tim2;
@@ -168,7 +169,13 @@ struct cmd_control dxr2_ddr3_cmd_ctrl_data = {
 	dxr2_ddr3_cmd_ctrl_data.cmd2csratio = settings.ddr3.ddr3_sratio;
 	dxr2_ddr3_cmd_ctrl_data.cmd2iclkout = settings.ddr3.iclkout;
 
-	config_ddr(DDR_PLL_FREQ, DXR2_IOCTRL_VAL, &dxr2_ddr3_data,
+	dxr2_ddr3_ioregs.cm0ioctl = settings.ddr3.ioctr_val,
+	dxr2_ddr3_ioregs.cm1ioctl = settings.ddr3.ioctr_val,
+	dxr2_ddr3_ioregs.cm2ioctl = settings.ddr3.ioctr_val,
+	dxr2_ddr3_ioregs.dt0ioctl = settings.ddr3.ioctr_val,
+	dxr2_ddr3_ioregs.dt1ioctl = settings.ddr3.ioctr_val,
+
+	config_ddr(DDR_PLL_FREQ, &dxr2_ddr3_ioregs, &dxr2_ddr3_data,
 		   &dxr2_ddr3_cmd_ctrl_data, &dxr2_ddr3_emif_reg_data, 0);
 }
 
@@ -191,7 +198,7 @@ static struct cpsw_slave_data cpsw_slaves[] = {
 	{
 		.slave_reg_ofs	= 0x208,
 		.sliver_reg_ofs	= 0xd80,
-		.phy_id		= 0,
+		.phy_addr	= 0,
 		.phy_if		= PHY_INTERFACE_MODE_MII,
 	},
 };
@@ -235,6 +242,25 @@ int board_eth_init(bd_t *bis)
 		n += rv;
 	return n;
 }
+
+static int do_switch_reset(cmd_tbl_t *cmdtp, int flag, int argc,
+			   char *const argv[])
+{
+	/* Reset SMSC LAN9303 switch for default configuration */
+	gpio_request(GPIO_LAN9303_NRST, "nRST");
+	gpio_direction_output(GPIO_LAN9303_NRST, 0);
+	/* assert active low reset for 200us */
+	udelay(200);
+	gpio_set_value(GPIO_LAN9303_NRST, 1);
+
+	return 0;
+};
+
+U_BOOT_CMD(
+	switch_rst, CONFIG_SYS_MAXARGS, 1,	do_switch_reset,
+	"Reset LAN9303 switch via its reset pin",
+	""
+);
 #endif /* #if defined(CONFIG_DRIVER_TI_CPSW) */
 #endif /* #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) */
 
diff --git a/board/siemens/dxr2/board.h b/board/siemens/dxr2/board.h
index 2be78fbab2..abf5432329 100644
--- a/board/siemens/dxr2/board.h
+++ b/board/siemens/dxr2/board.h
@@ -22,11 +22,11 @@
 #define MAGIC_CHIP	0x50494843
 
 /* Automatic generated definition */
-/* Wed, 19 Jun 2013 10:57:48 +0200 */
-/* From file: draco/ddr3-data-micron.txt */
+/* Wed, 18 Sep 2013 18:58:27 +0200 */
+/* From file: draco/ddr3-data-micron-v2.txt */
 struct ddr3_data {
 	unsigned int magic;			/* 0x33524444 */
-	unsigned int version;			/* 0x56312e33 */
+	unsigned int version;			/* 0x56312e34 */
 	unsigned short int ddr3_sratio;		/* 0x0100 */
 	unsigned short int iclkout;		/* 0x0001 */
 	unsigned short int dt0rdsratio0;	/* 0x003A */
@@ -36,9 +36,10 @@ struct ddr3_data {
 	unsigned int sdram_tim1;		/* 0x0888A39B */
 	unsigned int sdram_tim2;		/* 0x26247FDA */
 	unsigned int sdram_tim3;		/* 0x501F821F */
-	unsigned short int emif_ddr_phy_ctlr_1;	/* 0x0006 */
+	unsigned int emif_ddr_phy_ctlr_1;	/* 0x00100206 */
 	unsigned int sdram_config;		/* 0x61C04AB2 */
 	unsigned int ref_ctrl;			/* 0x00000618 */
+	unsigned int ioctr_val;			/* 0x0000018B */
 };
 
 struct chip_data {
diff --git a/board/siemens/dxr2/mux.c b/board/siemens/dxr2/mux.c
index bc80b79d7e..f2314b5d3e 100644
--- a/board/siemens/dxr2/mux.c
+++ b/board/siemens/dxr2/mux.c
@@ -63,6 +63,166 @@ static struct module_pin_mux gpios_pin_mux[] = {
 	{OFFSET(gpmc_ad11), (MODE(7) | PULLUDEN | RXACTIVE)},
 	{OFFSET(gpmc_csn3), MODE(7) },			/* LED0 GPIO2_0 */
 	{OFFSET(emu0), MODE(7)},			/* LED1 GPIO3_7 */
+	/* Triacs in HW Rev 2 */
+	{OFFSET(uart1_ctsn), MODE(7) | PULLUDDIS | RXACTIVE},	/* Y5 GPIO0_12*/
+	{OFFSET(mmc0_dat1), MODE(7) | PULLUDDIS | RXACTIVE},	/* Y3 GPIO2_28*/
+	{OFFSET(mmc0_dat2), MODE(7) | PULLUDDIS | RXACTIVE},	/* Y7 GPIO2_27*/
+	/* Triacs initial HW Rev */
+	{OFFSET(gpmc_csn1), MODE(7) | RXACTIVE | PULLUDDIS},	/* 1_30 Y0 */
+	{OFFSET(gpmc_be1n), MODE(7) | RXACTIVE | PULLUDDIS},	/* 1_28 Y1 */
+	{OFFSET(gpmc_csn2), MODE(7) | RXACTIVE | PULLUDDIS},	/* 1_31 Y2 */
+	{OFFSET(lcd_data15), MODE(7) | RXACTIVE | PULLUDDIS},	/* 0_11 Y3 */
+	{OFFSET(lcd_data14), MODE(7) | RXACTIVE | PULLUDDIS},	/* 0_10 Y4 */
+	{OFFSET(gpmc_clk), MODE(7) | RXACTIVE | PULLUDDIS},	/* 2_1  Y5 */
+	{OFFSET(emu1), MODE(7) | RXACTIVE | PULLUDDIS},		/* 3_8  Y6 */
+	{OFFSET(gpmc_ad15), MODE(7) | RXACTIVE | PULLUDDIS},	/* 1_15 Y7 */
+	/* Remaining pins that were not used in this file */
+	{OFFSET(gpmc_ad8), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(gpmc_ad9), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(gpmc_a0), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(gpmc_a1), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(gpmc_a2), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(gpmc_a3), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(gpmc_a4), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(gpmc_a5), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(gpmc_a6), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(gpmc_a7), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(gpmc_a8), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(gpmc_a9), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(gpmc_a10), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(gpmc_a11), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(lcd_data0), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(lcd_data2), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(lcd_data3), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(lcd_data4), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(lcd_data5), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(lcd_data6), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(lcd_data7), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(lcd_data8), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(lcd_data9), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(lcd_vsync), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(lcd_hsync), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(lcd_pclk), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(lcd_ac_bias_en), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(mmc0_dat3), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(mmc0_dat0), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(mmc0_clk), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(mmc0_cmd), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(spi0_sclk), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(spi0_d0), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(spi0_d1), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(spi0_cs0), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(uart0_ctsn), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(uart0_rtsn), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(uart1_rtsn), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(uart1_rxd), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(uart1_txd), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(mcasp0_aclkx), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(mcasp0_fsx), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(mcasp0_axr0), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(mcasp0_ahclkr), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(mcasp0_aclkr), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(mcasp0_fsr), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(mcasp0_axr1), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(mcasp0_ahclkx), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(xdma_event_intr0), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(xdma_event_intr1), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(nresetin_out), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(porz), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(nnmi), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(osc0_in), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(osc0_out), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(rsvd1), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(tms), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(tdi), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(tdo), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(tck), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(ntrst), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(osc1_in), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(osc1_out), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(pmic_power_en), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(rtc_porz), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(rsvd2), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(ext_wakeup), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(enz_kaldo_1p8v), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(usb0_dm), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(usb0_dp), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(usb0_ce), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(usb0_id), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(usb0_vbus), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(usb0_drvvbus), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(usb1_dm), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(usb1_dp), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(usb1_ce), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(usb1_id), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(usb1_vbus), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(usb1_drvvbus), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(ddr_resetn), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(ddr_csn0), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(ddr_cke), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(ddr_ck), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(ddr_nck), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(ddr_casn), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(ddr_rasn), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(ddr_wen), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(ddr_ba0), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(ddr_ba1), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(ddr_ba2), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(ddr_a0), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(ddr_a1), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(ddr_a2), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(ddr_a3), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(ddr_a4), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(ddr_a5), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(ddr_a6), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(ddr_a7), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(ddr_a8), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(ddr_a9), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(ddr_a10), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(ddr_a11), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(ddr_a12), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(ddr_a13), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(ddr_a14), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(ddr_a15), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(ddr_odt), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(ddr_d0), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(ddr_d1), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(ddr_d2), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(ddr_d3), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(ddr_d4), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(ddr_d5), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(ddr_d6), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(ddr_d7), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(ddr_d8), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(ddr_d9), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(ddr_d10), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(ddr_d11), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(ddr_d12), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(ddr_d13), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(ddr_d14), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(ddr_d15), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(ddr_dqm0), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(ddr_dqm1), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(ddr_dqs0), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(ddr_dqsn0), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(ddr_dqs1), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(ddr_dqsn1), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(ddr_vref), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(ddr_vtp), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(ddr_strben0), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(ddr_strben1), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(ain7), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(ain6), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(ain5), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(ain4), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(ain3), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(ain2), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(ain1), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(ain0), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(vrefp), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(vrefn), MODE(7) | RXACTIVE | PULLUDDIS},
+	/* nRST for SMSC LAN9303 switch - GPIO2_24 */
+	{OFFSET(lcd_pclk), MODE(7) },			/* LAN9303 nRST */
 	{-1},
 };
 
diff --git a/board/siemens/pxm2/Makefile b/board/siemens/pxm2/Makefile
index a09b467d5a..f15993216b 100644
--- a/board/siemens/pxm2/Makefile
+++ b/board/siemens/pxm2/Makefile
@@ -11,39 +11,11 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-ifneq ($(OBJTREE),$(SRCTREE))
-$(shell mkdir -p $(obj)../common)
-endif
-
-LIB	= $(obj)lib$(BOARD).o
-
 ifdef CONFIG_SPL_BUILD
-COBJS	:= mux.o
+obj-y	:= mux.o
 endif
 
-COBJS	+= board.o
+obj-y	+= board.o
 ifndef CONFIG_SPL_BUILD
-COBJS += ../common/factoryset.o
+obj-y += ../common/factoryset.o
 endif
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
-	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
-
-clean:
-	rm -f $(SOBJS) $(OBJS)
-
-distclean:	clean
-	rm -f $(LIB) core *.bak $(obj).depend
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
diff --git a/board/siemens/pxm2/board.c b/board/siemens/pxm2/board.c
index 2c1841f8ae..98083d52cd 100644
--- a/board/siemens/pxm2/board.c
+++ b/board/siemens/pxm2/board.c
@@ -58,23 +58,26 @@ struct ddr_data pxm2_ddr3_data = {
 	.datawdsratio0 = 0,
 	.datafwsratio0 = 0x8020080,
 	.datawrsratio0 = 0x4010040,
-	.datauserank0delay = 1,
-	.datadldiff0 = PHY_DLL_LOCK_DIFF,
 };
 
 struct cmd_control pxm2_ddr3_cmd_ctrl_data = {
 	.cmd0csratio = 0x80,
-	.cmd0dldiff = 0,
 	.cmd0iclkout = 0,
 	.cmd1csratio = 0x80,
-	.cmd1dldiff = 0,
 	.cmd1iclkout = 0,
 	.cmd2csratio = 0x80,
-	.cmd2dldiff = 0,
 	.cmd2iclkout = 0,
 };
 
-	config_ddr(DDR_PLL_FREQ, DXR2_IOCTRL_VAL, &pxm2_ddr3_data,
+const struct ctrl_ioregs ioregs = {
+	.cm0ioctl		= DXR2_IOCTRL_VAL,
+	.cm1ioctl		= DXR2_IOCTRL_VAL,
+	.cm2ioctl		= DXR2_IOCTRL_VAL,
+	.dt0ioctl		= DXR2_IOCTRL_VAL,
+	.dt1ioctl		= DXR2_IOCTRL_VAL,
+};
+
+	config_ddr(DDR_PLL_FREQ, &ioregs, &pxm2_ddr3_data,
 		   &pxm2_ddr3_cmd_ctrl_data, &pxm2_ddr3_emif_reg_data, 0);
 }
 
@@ -178,13 +181,13 @@ static struct cpsw_slave_data cpsw_slaves[] = {
 	{
 		.slave_reg_ofs	= 0x208,
 		.sliver_reg_ofs	= 0xd80,
-		.phy_id		= 0,
+		.phy_addr	= 0,
 		.phy_if		= PHY_INTERFACE_MODE_RMII,
 	},
 	{
 		.slave_reg_ofs	= 0x308,
 		.sliver_reg_ofs	= 0xdc0,
-		.phy_id		= 1,
+		.phy_addr	= 1,
 		.phy_if		= PHY_INTERFACE_MODE_RMII,
 	},
 };
@@ -413,8 +416,7 @@ static int conf_disp_pll(int m, int n)
 
 static int board_video_init(void)
 {
-	/* set 300 MHz */
-	conf_disp_pll(25, 2);
+	conf_disp_pll(24, 1);
 	if (factory_dat.pxm50)
 		da8xx_video_init(&lcd_panels[0], &lcd_cfg, lcd_cfg.bpp);
 	else
diff --git a/board/siemens/rut/Makefile b/board/siemens/rut/Makefile
index a09b467d5a..f15993216b 100644
--- a/board/siemens/rut/Makefile
+++ b/board/siemens/rut/Makefile
@@ -11,39 +11,11 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-ifneq ($(OBJTREE),$(SRCTREE))
-$(shell mkdir -p $(obj)../common)
-endif
-
-LIB	= $(obj)lib$(BOARD).o
-
 ifdef CONFIG_SPL_BUILD
-COBJS	:= mux.o
+obj-y	:= mux.o
 endif
 
-COBJS	+= board.o
+obj-y	+= board.o
 ifndef CONFIG_SPL_BUILD
-COBJS += ../common/factoryset.o
+obj-y += ../common/factoryset.o
 endif
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
-	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
-
-clean:
-	rm -f $(SOBJS) $(OBJS)
-
-distclean:	clean
-	rm -f $(LIB) core *.bak $(obj).depend
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
diff --git a/board/siemens/rut/board.c b/board/siemens/rut/board.c
index 5de8fc6cbf..e0ada3f6a5 100644
--- a/board/siemens/rut/board.c
+++ b/board/siemens/rut/board.c
@@ -63,29 +63,71 @@ struct ddr_data rut_ddr3_data = {
 	.datawdsratio0 = 0x85,
 	.datafwsratio0 = 0x100,
 	.datawrsratio0 = 0xc1,
-	.datauserank0delay = 1,
-	.datadldiff0 = PHY_DLL_LOCK_DIFF,
 };
 
 struct cmd_control rut_ddr3_cmd_ctrl_data = {
 	.cmd0csratio = 0x40,
-	.cmd0dldiff = 0,
 	.cmd0iclkout = 1,
 	.cmd1csratio = 0x40,
-	.cmd1dldiff = 0,
 	.cmd1iclkout = 1,
 	.cmd2csratio = 0x40,
-	.cmd2dldiff = 0,
 	.cmd2iclkout = 1,
 };
 
-	config_ddr(DDR_PLL_FREQ, RUT_IOCTRL_VAL, &rut_ddr3_data,
+const struct ctrl_ioregs ioregs = {
+	.cm0ioctl		= RUT_IOCTRL_VAL,
+	.cm1ioctl		= RUT_IOCTRL_VAL,
+	.cm2ioctl		= RUT_IOCTRL_VAL,
+	.dt0ioctl		= RUT_IOCTRL_VAL,
+	.dt1ioctl		= RUT_IOCTRL_VAL,
+};
+
+	config_ddr(DDR_PLL_FREQ, &ioregs, &rut_ddr3_data,
 		   &rut_ddr3_cmd_ctrl_data, &rut_ddr3_emif_reg_data, 0);
 }
 
+static int request_and_pulse_reset(int gpio, const char *name)
+{
+	int ret;
+	const int delay_us = 2000; /* 2ms */
+
+	ret = gpio_request(gpio, name);
+	if (ret < 0) {
+		printf("%s: Unable to request %s\n", __func__, name);
+		goto err;
+	}
+
+	ret = gpio_direction_output(gpio, 0);
+	if (ret < 0) {
+		printf("%s: Unable to set %s  as output\n", __func__, name);
+		goto err_free_gpio;
+	}
+
+	udelay(delay_us);
+
+	gpio_set_value(gpio, 1);
+
+	return 0;
+
+err_free_gpio:
+	gpio_free(gpio);
+err:
+	return ret;
+}
+
+#define GPIO_TO_PIN(bank, gpio)		(32 * (bank) + (gpio))
+#define ETH_PHY_RESET_GPIO		GPIO_TO_PIN(2, 18)
+#define MAXTOUCH_RESET_GPIO		GPIO_TO_PIN(3, 18)
+#define DISPLAY_RESET_GPIO		GPIO_TO_PIN(3, 19)
+
+#define REQUEST_AND_PULSE_RESET(N) \
+		request_and_pulse_reset(N, #N);
+
 static void spl_siemens_board_init(void)
 {
-	return;
+	REQUEST_AND_PULSE_RESET(ETH_PHY_RESET_GPIO);
+	REQUEST_AND_PULSE_RESET(MAXTOUCH_RESET_GPIO);
+	REQUEST_AND_PULSE_RESET(DISPLAY_RESET_GPIO);
 }
 #endif /* if def CONFIG_SPL_BUILD */
 
@@ -101,13 +143,13 @@ static struct cpsw_slave_data cpsw_slaves[] = {
 	{
 		.slave_reg_ofs	= 0x208,
 		.sliver_reg_ofs	= 0xd80,
-		.phy_id		= 1,
+		.phy_addr	= 1,
 		.phy_if		= PHY_INTERFACE_MODE_RMII,
 	},
 	{
 		.slave_reg_ofs	= 0x308,
 		.sliver_reg_ofs	= 0xdc0,
-		.phy_id		= 0,
+		.phy_addr	= 0,
 		.phy_if		= PHY_INTERFACE_MODE_RMII,
 	},
 };
@@ -336,7 +378,6 @@ int clk_get(int clk)
 static int conf_disp_pll(int m, int n)
 {
 	struct cm_perpll *cmper = (struct cm_perpll *)CM_PER;
-	struct cm_dpll *cmdpll = (struct cm_dpll *)CM_DPLL;
 	struct dpll_params dpll_lcd = {m, n, -1, -1, -1, -1, -1};
 #if defined(DISPL_PLL_SPREAD_SPECTRUM)
 	struct cm_wkuppll *cmwkup = (struct cm_wkuppll *)CM_WKUP;
@@ -353,8 +394,6 @@ static int conf_disp_pll(int m, int n)
 		0
 	};
 	do_enable_clocks(clk_domains, clk_modules_explicit_en, 1);
-	/* 0x44e0_0500 write lcdc pixel clock mux Linux hat hier 0 */
-	writel(0x0, &cmdpll->clklcdcpixelclk);
 
 	do_setup_dpll(&dpll_lcd_regs, &dpll_lcd);
 
@@ -380,10 +419,13 @@ static int enable_lcd(void)
 {
 	unsigned char buf[1];
 
+	set_gpio(BOARD_LCD_RESET, 0);
+	mdelay(1);
 	set_gpio(BOARD_LCD_RESET, 1);
+	mdelay(1);
 
 	/* spi lcd init */
-	kwh043st20_f01_spi_startup(1, 0, 5000000, SPI_MODE_3);
+	kwh043st20_f01_spi_startup(1, 0, 5000000, SPI_MODE_0);
 
 	/* backlight on */
 	buf[0] = 0xf;
@@ -418,7 +460,7 @@ static int board_video_init(void)
 		printf("%s: %s not found, using default %s\n", __func__,
 		       factory_dat.disp_name, lcd_panels[i].name);
 	}
-	conf_disp_pll(25, 2);
+	conf_disp_pll(24, 1);
 	da8xx_video_init(&lcd_panels[display], &lcd_cfgs[display],
 			 lcd_cfgs[display].bpp);
 
diff --git a/board/siemens/taurus/Makefile b/board/siemens/taurus/Makefile
new file mode 100644
index 0000000000..a26fb92147
--- /dev/null
+++ b/board/siemens/taurus/Makefile
@@ -0,0 +1,18 @@
+#
+# Makefile for Siemens TAURUS (AT91SAM9G20) based board
+# (C) Copyright 2013 Siemens AG
+#
+# Based on:
+# U-Boot file: board/atmel/at91sam9260ek/Makefile
+#
+# (C) Copyright 2003-2008
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# (C) Copyright 2008
+# Stelian Pop <stelian@popies.net>
+# Lead Tech Design <www.leadtechdesign.com>
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y	+= taurus.o
diff --git a/board/siemens/taurus/taurus.c b/board/siemens/taurus/taurus.c
new file mode 100644
index 0000000000..673b3029a6
--- /dev/null
+++ b/board/siemens/taurus/taurus.c
@@ -0,0 +1,160 @@
+/*
+ * Board functions for Siemens TAURUS (AT91SAM9G20) based boards
+ * (C) Copyright Siemens AG
+ *
+ * Based on:
+ * U-Boot file: board/atmel/at91sam9260ek/at91sam9260ek.c
+ *
+ * (C) Copyright 2007-2008
+ * Stelian Pop <stelian@popies.net>
+ * Lead Tech Design <www.leadtechdesign.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/at91sam9260_matrix.h>
+#include <asm/arch/at91sam9_smc.h>
+#include <asm/arch/at91_common.h>
+#include <asm/arch/at91_pmc.h>
+#include <asm/arch/at91_rstc.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/at91sam9_sdramc.h>
+#include <atmel_mci.h>
+
+#include <net.h>
+#include <netdev.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#ifdef CONFIG_CMD_NAND
+static void taurus_nand_hw_init(void)
+{
+	struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
+	struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
+	unsigned long csa;
+
+	/* Assign CS3 to NAND/SmartMedia Interface */
+	csa = readl(&matrix->ebicsa);
+	csa |= AT91_MATRIX_CS3A_SMC_SMARTMEDIA;
+	writel(csa, &matrix->ebicsa);
+
+	/* Configure SMC CS3 for NAND/SmartMedia */
+	writel(AT91_SMC_SETUP_NWE(2) | AT91_SMC_SETUP_NCS_WR(0) |
+	       AT91_SMC_SETUP_NRD(2) | AT91_SMC_SETUP_NCS_RD(0),
+	       &smc->cs[3].setup);
+	writel(AT91_SMC_PULSE_NWE(4) | AT91_SMC_PULSE_NCS_WR(3) |
+	       AT91_SMC_PULSE_NRD(4) | AT91_SMC_PULSE_NCS_RD(3),
+	       &smc->cs[3].pulse);
+	writel(AT91_SMC_CYCLE_NWE(7) | AT91_SMC_CYCLE_NRD(7),
+	       &smc->cs[3].cycle);
+	writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
+	       AT91_SMC_MODE_EXNW_DISABLE |
+	       AT91_SMC_MODE_DBW_8 |
+	       AT91_SMC_MODE_TDF_CYCLE(3),
+	       &smc->cs[3].mode);
+
+	/* Configure RDY/BSY */
+	at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
+
+	/* Enable NandFlash */
+	at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
+}
+#endif
+
+#ifdef CONFIG_MACB
+static void taurus_macb_hw_init(void)
+{
+	struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
+
+	/* Enable EMAC clock */
+	writel(1 << ATMEL_ID_EMAC0, &pmc->pcer);
+
+	/*
+	 * Disable pull-up on:
+	 *	RXDV (PA17) => PHY normal mode (not Test mode)
+	 *	ERX0 (PA14) => PHY ADDR0
+	 *	ERX1 (PA15) => PHY ADDR1
+	 *	ERX2 (PA25) => PHY ADDR2
+	 *	ERX3 (PA26) => PHY ADDR3
+	 *	ECRS (PA28) => PHY ADDR4  => PHYADDR = 0x0
+	 *
+	 * PHY has internal pull-down
+	 */
+	at91_set_pio_pullup(AT91_PIO_PORTA, 14, 0);
+	at91_set_pio_pullup(AT91_PIO_PORTA, 15, 0);
+	at91_set_pio_pullup(AT91_PIO_PORTA, 17, 0);
+	at91_set_pio_pullup(AT91_PIO_PORTA, 25, 0);
+	at91_set_pio_pullup(AT91_PIO_PORTA, 26, 0);
+	at91_set_pio_pullup(AT91_PIO_PORTA, 28, 0);
+
+	at91_phy_reset();
+
+	at91_set_gpio_input(AT91_PIN_PA25, 1);   /* ERST tri-state */
+
+	/* Re-enable pull-up */
+	at91_set_pio_pullup(AT91_PIO_PORTA, 14, 1);
+	at91_set_pio_pullup(AT91_PIO_PORTA, 15, 1);
+	at91_set_pio_pullup(AT91_PIO_PORTA, 17, 1);
+	at91_set_pio_pullup(AT91_PIO_PORTA, 25, 1);
+	at91_set_pio_pullup(AT91_PIO_PORTA, 26, 1);
+	at91_set_pio_pullup(AT91_PIO_PORTA, 28, 1);
+
+	/* Initialize EMAC=MACB hardware */
+	at91_macb_hw_init();
+}
+#endif
+
+#ifdef CONFIG_GENERIC_ATMEL_MCI
+int board_mmc_init(bd_t *bd)
+{
+	at91_mci_hw_init();
+
+	return atmel_mci_init((void *)ATMEL_BASE_MCI);
+}
+#endif
+
+int board_early_init_f(void)
+{
+	struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
+
+	/* Enable clocks for all PIOs */
+	writel((1 << ATMEL_ID_PIOA) | (1 << ATMEL_ID_PIOB) |
+		(1 << ATMEL_ID_PIOC),
+		&pmc->pcer);
+
+	return 0;
+}
+
+int board_init(void)
+{
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+
+	at91_seriald_hw_init();
+#ifdef CONFIG_CMD_NAND
+	taurus_nand_hw_init();
+#endif
+#ifdef CONFIG_MACB
+	taurus_macb_hw_init();
+#endif
+
+	return 0;
+}
+
+int dram_init(void)
+{
+	gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
+				    CONFIG_SYS_SDRAM_SIZE);
+	return 0;
+}
+
+int board_eth_init(bd_t *bis)
+{
+	int rc = 0;
+#ifdef CONFIG_MACB
+	rc = macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC0, 0x00);
+#endif
+	return rc;
+}
diff --git a/board/silica/pengwyn/Makefile b/board/silica/pengwyn/Makefile
new file mode 100644
index 0000000000..c8b4f9a280
--- /dev/null
+++ b/board/silica/pengwyn/Makefile
@@ -0,0 +1,13 @@
+#
+# Makefile
+#
+# Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+ifeq ($(CONFIG_SPL_BUILD)$(CONFIG_NOR_BOOT),y)
+obj-y	:= mux.o
+endif
+
+obj-y	+= board.o
diff --git a/board/silica/pengwyn/board.c b/board/silica/pengwyn/board.c
new file mode 100644
index 0000000000..ee88b6f399
--- /dev/null
+++ b/board/silica/pengwyn/board.c
@@ -0,0 +1,207 @@
+/*
+ * board.c
+ *
+ * Copyright (C) 2013 Lothar Felten <lothar.felten@gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/ddr_defs.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/sys_proto.h>
+#include <i2c.h>
+#include <phy.h>
+#include <cpsw.h>
+#include "board.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
+
+#if defined(CONFIG_SPL_BUILD)
+
+/* DDR3 RAM timings */
+static const struct ddr_data ddr3_data = {
+	.datardsratio0 = MT41K128MJT187E_RD_DQS,
+	.datawdsratio0 = MT41K128MJT187E_WR_DQS,
+	.datafwsratio0 = MT41K128MJT187E_PHY_FIFO_WE,
+	.datawrsratio0 = MT41K128MJT187E_PHY_WR_DATA,
+};
+
+static const struct cmd_control ddr3_cmd_ctrl_data = {
+	.cmd0csratio = MT41K128MJT187E_RATIO,
+	.cmd0iclkout = MT41K128MJT187E_INVERT_CLKOUT,
+	.cmd1csratio = MT41K128MJT187E_RATIO,
+	.cmd1iclkout = MT41K128MJT187E_INVERT_CLKOUT,
+	.cmd2csratio = MT41K128MJT187E_RATIO,
+	.cmd2iclkout = MT41K128MJT187E_INVERT_CLKOUT,
+};
+
+static struct emif_regs ddr3_emif_reg_data = {
+	.sdram_config = MT41K128MJT187E_EMIF_SDCFG,
+	.ref_ctrl = MT41K128MJT187E_EMIF_SDREF,
+	.sdram_tim1 = MT41K128MJT187E_EMIF_TIM1,
+	.sdram_tim2 = MT41K128MJT187E_EMIF_TIM2,
+	.sdram_tim3 = MT41K128MJT187E_EMIF_TIM3,
+	.zq_config = MT41K128MJT187E_ZQ_CFG,
+	.emif_ddr_phy_ctlr_1 = MT41K128MJT187E_EMIF_READ_LATENCY |
+				PHY_EN_DYN_PWRDN,
+};
+
+const struct ctrl_ioregs ddr3_ioregs = {
+	.cm0ioctl		= MT41K128MJT187E_IOCTRL_VALUE,
+	.cm1ioctl		= MT41K128MJT187E_IOCTRL_VALUE,
+	.cm2ioctl		= MT41K128MJT187E_IOCTRL_VALUE,
+	.dt0ioctl		= MT41K128MJT187E_IOCTRL_VALUE,
+	.dt1ioctl		= MT41K128MJT187E_IOCTRL_VALUE,
+};
+
+#ifdef CONFIG_SPL_OS_BOOT
+int spl_start_uboot(void)
+{
+	/* break into full u-boot on 'c' */
+	return serial_tstc() && serial_getc() == 'c';
+}
+#endif
+
+#define OSC	(V_OSCK/1000000)
+const struct dpll_params dpll_ddr_266 = {
+		266, OSC-1, 1, -1, -1, -1, -1};
+const struct dpll_params dpll_ddr_303 = {
+		303, OSC-1, 1, -1, -1, -1, -1};
+const struct dpll_params dpll_ddr_400 = {
+		400, OSC-1, 1, -1, -1, -1, -1};
+
+void am33xx_spl_board_init(void)
+{
+	/*
+	 * The pengwyn board uses the TPS650250 PMIC  without I2C
+	 * interface and will output the following fixed voltages:
+	 * DCDC1=3V3 (IO) DCDC2=1V5 (DDR) DCDC3=1V26 (Vmpu)
+	 * VLDO1=1V8 (IO) VLDO2=1V8(IO)
+	 * Vcore=1V1 is fixed, generated by TPS62231
+	 */
+
+	/* Get the frequency */
+	dpll_mpu_opp100.m = am335x_get_efuse_mpu_max_freq(cdev);
+
+	/* Set CORE Frequencies to OPP100 */
+	do_setup_dpll(&dpll_core_regs, &dpll_core_opp100);
+
+	/* 720MHz cpu, this might change on newer board revisions */
+	dpll_mpu_opp100.m = MPUPLL_M_720;
+	do_setup_dpll(&dpll_mpu_regs, &dpll_mpu_opp100);
+}
+
+const struct dpll_params *get_dpll_ddr_params(void)
+{
+	/* future configs can return other clock settings */
+	return &dpll_ddr_303;
+}
+
+void set_uart_mux_conf(void)
+{
+	enable_uart0_pin_mux();
+}
+
+void set_mux_conf_regs(void)
+{
+	enable_board_pin_mux();
+}
+
+void sdram_init(void)
+{
+	config_ddr(303, &ddr3_ioregs, &ddr3_data,
+		   &ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0);
+}
+#endif /* if CONFIG_SPL_BUILD */
+
+/*
+ * Basic board specific setup.  Pinmux has been handled already.
+ */
+int board_init(void)
+{
+	i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
+	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+	gpmc_init();
+	return 0;
+}
+
+#ifdef CONFIG_DRIVER_TI_CPSW
+static void cpsw_control(int enabled)
+{
+	/* VTP can be added here */
+	return;
+}
+
+static struct cpsw_slave_data cpsw_slaves[] = {
+	{
+		.slave_reg_ofs	= 0x208,
+		.sliver_reg_ofs	= 0xd80,
+		.phy_addr	= 0,
+		.phy_if		= PHY_INTERFACE_MODE_MII,
+	},
+	{
+		.slave_reg_ofs	= 0x308,
+		.sliver_reg_ofs	= 0xdc0,
+		.phy_addr	= 1,
+		.phy_if		= PHY_INTERFACE_MODE_MII,
+	},
+};
+
+static struct cpsw_platform_data cpsw_data = {
+	.mdio_base		= CPSW_MDIO_BASE,
+	.cpsw_base		= CPSW_BASE,
+	.mdio_div		= 0xff,
+	.channels		= 8,
+	.cpdma_reg_ofs		= 0x800,
+	.slaves			= 1,
+	.slave_data		= cpsw_slaves,
+	.ale_reg_ofs		= 0xd00,
+	.ale_entries		= 1024,
+	.host_port_reg_ofs	= 0x108,
+	.hw_stats_reg_ofs	= 0x900,
+	.bd_ram_ofs		= 0x2000,
+	.mac_control		= (1 << 5),
+	.control		= cpsw_control,
+	.host_port_num		= 0,
+	.version		= CPSW_CTRL_VERSION_2,
+};
+
+int board_eth_init(bd_t *bis)
+{
+	int rv, n = 0;
+	uint8_t mac_addr[6];
+	uint32_t mac_hi, mac_lo;
+
+	if (!eth_getenv_enetaddr("ethaddr", mac_addr)) {
+		printf("<ethaddr> not set. Reading from E-fuse\n");
+		/* try reading mac address from efuse */
+		mac_lo = readl(&cdev->macid0l);
+		mac_hi = readl(&cdev->macid0h);
+		mac_addr[0] = mac_hi & 0xFF;
+		mac_addr[1] = (mac_hi & 0xFF00) >> 8;
+		mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
+		mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
+		mac_addr[4] = mac_lo & 0xFF;
+		mac_addr[5] = (mac_lo & 0xFF00) >> 8;
+
+		if (is_valid_ether_addr(mac_addr))
+			eth_setenv_enetaddr("ethaddr", mac_addr);
+		else
+			return n;
+	}
+
+	writel(MII_MODE_ENABLE, &cdev->miisel);
+
+	rv = cpsw_register(&cpsw_data);
+	if (rv < 0)
+		printf("Error %d registering CPSW switch\n", rv);
+	else
+		n += rv;
+	return n;
+}
+#endif /* if CONFIG_DRIVER_TI_CPSW */
diff --git a/board/silica/pengwyn/board.h b/board/silica/pengwyn/board.h
new file mode 100644
index 0000000000..05addf6bb2
--- /dev/null
+++ b/board/silica/pengwyn/board.h
@@ -0,0 +1,15 @@
+/*
+ * board.h
+ *
+ * Copyright (C) 2013 Lothar Felten <lothar.felten@gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _BOARD_H_
+#define _BOARD_H_
+
+void enable_uart0_pin_mux(void);
+void enable_board_pin_mux(void);
+
+#endif
diff --git a/board/silica/pengwyn/mux.c b/board/silica/pengwyn/mux.c
new file mode 100644
index 0000000000..c8be440a20
--- /dev/null
+++ b/board/silica/pengwyn/mux.c
@@ -0,0 +1,98 @@
+/*
+ * mux.c
+ *
+ * Copyright (C) 2013 Lothar Felten <lothar.felten@gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/mux.h>
+#include <asm/io.h>
+#include "board.h"
+
+/* UART0 pins E15(rx),E16(tx) [E17(rts),E18(cts)] */
+static struct module_pin_mux uart0_pin_mux[] = {
+	{OFFSET(uart0_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* UART0_RXD */
+	{OFFSET(uart0_txd), (MODE(0) | PULLUDEN)},		/* UART0_TXD */
+	{-1},
+};
+
+/* unused: UART1 pins D15(tx),D16(rx),D17(cts),D18(rts) */
+
+/* I2C pins C16(scl)/C17(sda) */
+static struct module_pin_mux i2c0_pin_mux[] = {
+	{OFFSET(i2c0_sda), (MODE(0) | RXACTIVE |
+					PULLUDEN | SLEWCTRL)}, /* I2C0_DATA */
+	{OFFSET(i2c0_scl), (MODE(0) | RXACTIVE |
+					PULLUDEN | SLEWCTRL)}, /* I2C0_SCLK */
+	{-1},
+};
+
+/* MMC0 pins */
+static struct module_pin_mux mmc0_pin_mux[] = {
+	{OFFSET(mmc0_dat3), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT3 */
+	{OFFSET(mmc0_dat2), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT2 */
+	{OFFSET(mmc0_dat1), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT1 */
+	{OFFSET(mmc0_dat0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT0 */
+	{OFFSET(mmc0_clk), (MODE(0) | RXACTIVE | PULLUP_EN)},  /* MMC0_CLK */
+	{OFFSET(mmc0_cmd), (MODE(0) | RXACTIVE | PULLUP_EN)},  /* MMC0_CMD */
+	{OFFSET(spi0_cs1), (MODE(5) | RXACTIVE | PULLUP_EN)},  /* MMC0_CD */
+	{-1},
+};
+
+/* MII pins */
+static struct module_pin_mux mii1_pin_mux[] = {
+	{OFFSET(mii1_rxerr), MODE(0) | RXACTIVE},	/* MII1_RXERR */
+	{OFFSET(mii1_txen), MODE(0)},			/* MII1_TXEN */
+	{OFFSET(mii1_rxdv), MODE(0) | RXACTIVE},	/* MII1_RXDV */
+	{OFFSET(mii1_txd3), MODE(0)},			/* MII1_TXD3 */
+	{OFFSET(mii1_txd2), MODE(0)},			/* MII1_TXD2 */
+	{OFFSET(mii1_txd1), MODE(0)},			/* MII1_TXD1 */
+	{OFFSET(mii1_txd0), MODE(0)},			/* MII1_TXD0 */
+	{OFFSET(mii1_txclk), MODE(0) | RXACTIVE},	/* MII1_TXCLK */
+	{OFFSET(mii1_rxclk), MODE(0) | RXACTIVE},	/* MII1_RXCLK */
+	{OFFSET(mii1_rxd3), MODE(0) | RXACTIVE},	/* MII1_RXD3 */
+	{OFFSET(mii1_rxd2), MODE(0) | RXACTIVE},	/* MII1_RXD2 */
+	{OFFSET(mii1_rxd1), MODE(0) | RXACTIVE},	/* MII1_RXD1 */
+	{OFFSET(mii1_rxd0), MODE(0) | RXACTIVE},	/* MII1_RXD0 */
+	{OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN}, /* MDIO_DATA */
+	{OFFSET(mdio_clk), MODE(0) | PULLUP_EN},	/* MDIO_CLK */
+	{-1},
+};
+
+/* NAND pins */
+static struct module_pin_mux nand_pin_mux[] = {
+	{OFFSET(gpmc_ad0), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* NAND AD0 */
+	{OFFSET(gpmc_ad1), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* NAND AD1 */
+	{OFFSET(gpmc_ad2), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* NAND AD2 */
+	{OFFSET(gpmc_ad3), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* NAND AD3 */
+	{OFFSET(gpmc_ad4), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* NAND AD4 */
+	{OFFSET(gpmc_ad5), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* NAND AD5 */
+	{OFFSET(gpmc_ad6), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* NAND AD6 */
+	{OFFSET(gpmc_ad7), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* NAND AD7 */
+	{OFFSET(gpmc_wait0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* NAND WAIT */
+	{OFFSET(gpmc_wpn), (MODE(7) | PULLUP_EN | RXACTIVE)},	/* NAND_WPN */
+	{OFFSET(gpmc_csn0), (MODE(0) | PULLUDEN)},	/* NAND_CS0 */
+	{OFFSET(gpmc_advn_ale), (MODE(0) | PULLUDEN)}, /* NAND_ADV_ALE */
+	{OFFSET(gpmc_oen_ren), (MODE(0) | PULLUDEN)},	/* NAND_OE */
+	{OFFSET(gpmc_wen), (MODE(0) | PULLUDEN)},	/* NAND_WEN */
+	{OFFSET(gpmc_be0n_cle), (MODE(0) | PULLUDEN)},	/* NAND_BE_CLE */
+	{-1},
+};
+
+void enable_uart0_pin_mux(void)
+{
+	configure_module_pin_mux(uart0_pin_mux);
+}
+
+void enable_board_pin_mux()
+{
+	configure_module_pin_mux(i2c0_pin_mux);
+	configure_module_pin_mux(uart0_pin_mux);
+	configure_module_pin_mux(mii1_pin_mux);
+	configure_module_pin_mux(mmc0_pin_mux);
+	configure_module_pin_mux(nand_pin_mux);
+}
diff --git a/board/sixnet/Makefile b/board/sixnet/Makefile
index 871865b6ee..25a8d69536 100644
--- a/board/sixnet/Makefile
+++ b/board/sixnet/Makefile
@@ -5,24 +5,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	= $(BOARD).o flash.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	= sixnet.o flash.o
diff --git a/board/snmc/qs850/Makefile b/board/snmc/qs850/Makefile
index 871865b6ee..5867d900b7 100644
--- a/board/snmc/qs850/Makefile
+++ b/board/snmc/qs850/Makefile
@@ -5,24 +5,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	= $(BOARD).o flash.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	= qs850.o flash.o
diff --git a/board/snmc/qs860t/Makefile b/board/snmc/qs860t/Makefile
index 871865b6ee..802f67e384 100644
--- a/board/snmc/qs860t/Makefile
+++ b/board/snmc/qs860t/Makefile
@@ -5,24 +5,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	= $(BOARD).o flash.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	= qs860t.o flash.o
diff --git a/board/socrates/Makefile b/board/socrates/Makefile
index c2e282b952..79bda718d5 100644
--- a/board/socrates/Makefile
+++ b/board/socrates/Makefile
@@ -7,30 +7,9 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-#
-
-COBJS-y	+= $(BOARD).o
-COBJS-y	+= law.o
-COBJS-y	+= tlb.o
-COBJS-y	+= nand.o
-COBJS-y	+= sdram.o
-COBJS-$(CONFIG_FSL_DDR2) += ddr.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS-y))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	+= socrates.o
+obj-y	+= law.o
+obj-y	+= tlb.o
+obj-y	+= nand.o
+obj-y	+= sdram.o
+obj-$(CONFIG_SYS_FSL_DDR2) += ddr.o
diff --git a/board/socrates/ddr.c b/board/socrates/ddr.c
index e9db476f48..6bad4da394 100644
--- a/board/socrates/ddr.c
+++ b/board/socrates/ddr.c
@@ -8,8 +8,8 @@
 
 #include <common.h>
 
-#include <asm/fsl_ddr_sdram.h>
-#include <asm/fsl_ddr_dimm_params.h>
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr_dimm_params.h>
 
 void fsl_ddr_board_options(memctl_options_t *popts,
 				dimm_params_t *pdimm,
diff --git a/board/socrates/sdram.c b/board/socrates/sdram.c
index 313efae90f..aebd02f76c 100644
--- a/board/socrates/sdram.c
+++ b/board/socrates/sdram.c
@@ -8,7 +8,7 @@
 #include <common.h>
 #include <asm/processor.h>
 #include <asm/immap_85xx.h>
-#include <asm/fsl_ddr_sdram.h>
+#include <fsl_ddr_sdram.h>
 #include <asm/processor.h>
 #include <asm/mmu.h>
 #include <spd_sdram.h>
@@ -24,7 +24,8 @@
  */
 phys_size_t fixed_sdram(void)
 {
-	volatile ccsr_ddr_t *ddr = (void *)(CONFIG_SYS_MPC8xxx_DDR_ADDR);
+	struct ccsr_ddr __iomem *ddr =
+		(struct ccsr_ddr __iomem *)(CONFIG_SYS_FSL_DDR_ADDR);
 
 	/*
 	 * Disable memory controller.
diff --git a/board/solidrun/hummingboard/Makefile b/board/solidrun/hummingboard/Makefile
new file mode 100644
index 0000000000..042a2f0766
--- /dev/null
+++ b/board/solidrun/hummingboard/Makefile
@@ -0,0 +1,9 @@
+#
+# (C) Copyright 2013 Freescale Semiconductor, Inc.
+# Copyright (C) 2013, Boundary Devices <info@boundarydevices.com>
+# Copyright (C) 2013, Jon Nettleton <jon.nettleton@gmail.com>
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y  := hummingboard.o
diff --git a/board/solidrun/hummingboard/README b/board/solidrun/hummingboard/README
new file mode 100644
index 0000000000..cfd62d40be
--- /dev/null
+++ b/board/solidrun/hummingboard/README
@@ -0,0 +1,40 @@
+U-Boot for SolidRun Hummingboard
+--------------------------------
+
+This file contains information for the port of U-Boot to the Hummingboard.
+
+For more details about Hummingboard, please refer to:
+http://imx.solid-run.com/wiki/index.php?title=Carrier-One_Hardware
+
+(Carrier-One was the previous name of Hummingboard).
+
+Building U-boot for Hummingboard
+--------------------------------
+
+To build U-Boot for the Hummingboard Solo version:
+
+$ make hummingboard_solo_config
+$ make
+
+Flashing U-boot into the SD card
+--------------------------------
+
+- After the 'make' command completes, the generated 'u-boot.imx' binary must be
+flashed into the SD card:
+
+$ sudo dd if=u-boot.imx of=/dev/mmcblk0 bs=1k seek=1; sync
+
+(Note - the SD card node may vary, so adjust this as needed).
+
+Also, a more detailed explanation on how to format the SD card is available
+at doc/README.imximage.
+
+- Insert the micro SD card into the slot located in the bottom of the board
+
+- Connect a 3.3V USB to serial converter cable to the host PC. The MX6 UART
+signals are available in the 26 pin connector as shown at:
+http://imx.solid-run.com/wiki/index.php?title=Carrier-One_Hardware
+(Check for "26 pin header layout").
+
+- Power up the board via USB cable (CON201) and U-boot messages will appear in
+the serial console.
diff --git a/board/solidrun/hummingboard/hummingboard.c b/board/solidrun/hummingboard/hummingboard.c
new file mode 100644
index 0000000000..2e2fb2a5b7
--- /dev/null
+++ b/board/solidrun/hummingboard/hummingboard.c
@@ -0,0 +1,183 @@
+/*
+ * Copyright (C) 2013 Freescale Semiconductor, Inc.
+ * Copyright (C) 2013 SolidRun ltd.
+ * Copyright (C) 2013 Jon Nettleton <jon.nettleton@gmail.com>.
+ *
+ * Authors: Fabio Estevam <fabio.estevam@freescale.com>
+	    Jon Nettleton <jon.nettleton@gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <asm/arch/clock.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/iomux.h>
+#include <asm/arch/mx6-pins.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/errno.h>
+#include <asm/gpio.h>
+#include <asm/imx-common/iomux-v3.h>
+#include <asm/io.h>
+#include <mmc.h>
+#include <fsl_esdhc.h>
+#include <miiphy.h>
+#include <netdev.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define UART_PAD_CTRL  (PAD_CTL_PUS_100K_UP |			\
+	PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |			\
+	PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
+
+#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP |			\
+	PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm |			\
+	PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
+
+#define USDHC_PAD_CLK_CTRL (PAD_CTL_SPEED_LOW |			\
+	PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST |			\
+	PAD_CTL_HYS)
+
+#define USDHC_PAD_GPIO_CTRL (PAD_CTL_PUS_22K_UP |		\
+	PAD_CTL_SPEED_LOW | PAD_CTL_DSE_40ohm |			\
+	PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
+
+#define ENET_PAD_CTRL  (PAD_CTL_PUS_100K_UP |			\
+	PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
+
+#define ENET_PAD_CTRL_PD  (PAD_CTL_PUS_100K_DOWN |		\
+	PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
+
+#define ENET_PAD_CTRL_CLK  ((PAD_CTL_PUS_100K_UP & ~PAD_CTL_PKE) | \
+	PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
+
+#define ETH_PHY_RESET	IMX_GPIO_NR(4, 15)
+
+int dram_init(void)
+{
+	gd->ram_size = ((phys_size_t)CONFIG_DDR_MB * 1024 * 1024);
+
+	return 0;
+}
+
+static iomux_v3_cfg_t const uart1_pads[] = {
+	MX6_PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
+	MX6_PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+static void setup_iomux_uart(void)
+{
+	imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
+}
+
+static iomux_v3_cfg_t const usdhc2_pads[] = {
+	MX6_PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CLK_CTRL),
+	MX6_PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_GPIO_4__SD2_CD_B | MUX_PAD_CTRL(USDHC_PAD_GPIO_CTRL),
+};
+
+#ifdef CONFIG_FSL_ESDHC
+static struct fsl_esdhc_cfg usdhc_cfg[1] = {
+	{ USDHC2_BASE_ADDR },
+};
+
+int board_mmc_getcd(struct mmc *mmc)
+{
+	return 1; /* SD card is the boot medium, so always present */
+}
+
+int board_mmc_init(bd_t *bis)
+{
+	imx_iomux_v3_setup_multiple_pads(usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
+	usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
+
+	return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
+}
+#endif
+
+#ifdef CONFIG_FEC_MXC
+static iomux_v3_cfg_t const enet_pads[] = {
+	MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
+	/* AR8035 reset */
+	MX6_PAD_KEY_ROW4__GPIO4_IO15 | MUX_PAD_CTRL(ENET_PAD_CTRL_PD),
+	/* AR8035 interrupt */
+	MX6_PAD_DI0_PIN2__GPIO4_IO18 | MUX_PAD_CTRL(NO_PAD_CTRL),
+	/* GPIO16 -> AR8035 25MHz */
+	MX6_PAD_GPIO_16__ENET_REF_CLK	  | MUX_PAD_CTRL(NO_PAD_CTRL),
+	MX6_PAD_RGMII_TXC__RGMII_TXC	  | MUX_PAD_CTRL(NO_PAD_CTRL),
+	MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
+	/* AR8035 CLK_25M --> ENET_REF_CLK (V22) */
+	MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL_CLK),
+	MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL_PD),
+	MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL_PD),
+	MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL_PD),
+};
+
+static void setup_iomux_enet(void)
+{
+	imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
+
+	gpio_direction_output(ETH_PHY_RESET, 0);
+	mdelay(2);
+	gpio_set_value(ETH_PHY_RESET, 1);
+}
+
+int board_phy_config(struct phy_device *phydev)
+{
+	if (phydev->drv->config)
+		phydev->drv->config(phydev);
+
+	return 0;
+}
+
+int board_eth_init(bd_t *bis)
+{
+	struct iomuxc_base_regs *const iomuxc_regs =
+			(struct iomuxc_base_regs *)IOMUXC_BASE_ADDR;
+
+	int ret = enable_fec_anatop_clock(ENET_25MHz);
+	if (ret)
+		return ret;
+
+	/* set gpr1[ENET_CLK_SEL] */
+	setbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_ENET_CLK_SEL_MASK);
+
+	setup_iomux_enet();
+
+	return cpu_eth_init(bis);
+}
+#endif
+
+int board_early_init_f(void)
+{
+	setup_iomux_uart();
+
+	return 0;
+}
+
+int board_init(void)
+{
+	/* address of boot parameters */
+	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+
+	return 0;
+}
+
+int checkboard(void)
+{
+	puts("Board: Hummingboard\n");
+
+	return 0;
+}
diff --git a/board/solidrun/hummingboard/solo.cfg b/board/solidrun/hummingboard/solo.cfg
new file mode 100644
index 0000000000..28dd75065e
--- /dev/null
+++ b/board/solidrun/hummingboard/solo.cfg
@@ -0,0 +1,25 @@
+/*
+ * Copyright (C) 2013 Boundary Devices
+ * Copyright (C) 2013 Jon Nettleton <jon.nettleton@gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/* image version */
+IMAGE_VERSION 2
+
+/*
+ * Boot Device : one of
+ * spi, sd (the board has no nand neither onenand)
+ */
+BOOT_FROM      sd
+
+#define __ASSEMBLY__
+#include <config.h>
+#include "asm/arch/mx6-ddr.h"
+#include "asm/arch/iomux.h"
+#include "asm/arch/crm_regs.h"
+
+#include "../mx6-microsom/ddr-800mhz-32bit-setup.cfg"
+#include "../mx6-microsom/800mhz_2x128mx16.cfg"
+#include "../mx6-microsom/clocks.cfg"
diff --git a/board/solidrun/mx6-microsom/800mhz_2x128mx16.cfg b/board/solidrun/mx6-microsom/800mhz_2x128mx16.cfg
new file mode 100644
index 0000000000..40747abbdb
--- /dev/null
+++ b/board/solidrun/mx6-microsom/800mhz_2x128mx16.cfg
@@ -0,0 +1,74 @@
+/*
+ * Copyright (C) 2013 Boundary Devices
+ * Copyright (C) 2013 SolidRun ltd.
+ * Copyright (C) 2013 Jon Nettleton <jon.nettleton@gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/* ZQ Calibrations */
+DATA 4, MX6_MMDC_P0_MPZQHWCTRL, 0xa1390003
+DATA 4, MX6_MMDC_P1_MPZQHWCTRL, 0xa1390003
+/* write leveling */
+DATA 4, MX6_MMDC_P0_MPWLDECTRL0, 0x005a0057
+DATA 4, MX6_MMDC_P0_MPWLDECTRL1, 0x004a0052
+/*
+ * DQS gating, read delay, write delay calibration values
+ * based on calibration compare of 0x00ffff00
+ */
+DATA 4, MX6_MMDC_P0_MPDGCTRL0, 0x02480240
+DATA 4, MX6_MMDC_P0_MPDGCTRL1, 0x02340230
+DATA 4, MX6_MMDC_P0_MPRDDLCTL, 0x40404440
+DATA 4, MX6_MMDC_P0_MPWRDLCTL, 0x38343034
+/* read data bit delay */
+DATA 4, MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333
+DATA 4, MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333
+DATA 4, MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333
+DATA 4, MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333
+/* Complete calibration by forced measurement */
+DATA 4, MX6_MMDC_P0_MPMUR0, 0x00000800
+DATA 4, MX6_MMDC_P1_MPMUR0, 0x00000800
+
+/*
+ * MMDC init:
+ * in DDR3, 32-bit mode, only MMDC0 is initiated:
+ */
+DATA 4, MX6_MMDC_P0_MDPDC, 0x0002002d
+DATA 4, MX6_MMDC_P0_MDOTC, 0x00333040
+
+DATA 4, MX6_MMDC_P0_MDCFG0, 0x3f435313
+DATA 4, MX6_MMDC_P0_MDCFG1, 0xb66e8b63
+
+DATA 4, MX6_MMDC_P0_MDCFG2, 0x01ff00db
+DATA 4, MX6_MMDC_P0_MDMISC, 0x00011740
+DATA 4, MX6_MMDC_P0_MDSCR, 0x00008000
+DATA 4, MX6_MMDC_P0_MDRWD, 0x000026d2
+DATA 4, MX6_MMDC_P0_MDOR, 0x00431023
+/* CS0_END - 0x2fffffff, 512M  */
+DATA 4, MX6_MMDC_P0_MDASP, 0x00000017
+
+/* MMDC0_MAARCR ADOPT optimized priorities. Dyn jump disabled */
+DATA 4, 0x021b0400, 0x11420000
+
+/* MMDC0_MDCTL- row-14bits; col-10bits; burst length 8;32-bit data bus */
+DATA 4, MX6_MMDC_P0_MDCTL, 0x83190000
+
+/*
+ * Initialize 2GB DDR3 - Hynix H5TQ2G63BFR-H9C
+ * MR2
+ */
+DATA 4, MX6_MMDC_P0_MDSCR, 0x00008032
+/* MR3 */
+DATA 4, MX6_MMDC_P0_MDSCR, 0x00008033
+/* MR1 */
+DATA 4, MX6_MMDC_P0_MDSCR, 0x00008031
+/* MR0 */
+DATA 4, MX6_MMDC_P0_MDSCR, 0x05208030
+/* ZQ calibration */
+DATA 4, MX6_MMDC_P0_MDSCR, 0x04008040
+/* final DDR setup */
+DATA 4, MX6_MMDC_P0_MDREF, 0x00007800
+DATA 4, MX6_MMDC_P0_MPODTCTRL, 0x00000007
+DATA 4, MX6_MMDC_P0_MDPDC, 0x0002556d
+DATA 4, MX6_MMDC_P0_MAPSR, 0x00011006
+DATA 4, MX6_MMDC_P0_MDSCR, 0x00000000
diff --git a/board/solidrun/mx6-microsom/clocks.cfg b/board/solidrun/mx6-microsom/clocks.cfg
new file mode 100644
index 0000000000..12888113fb
--- /dev/null
+++ b/board/solidrun/mx6-microsom/clocks.cfg
@@ -0,0 +1,33 @@
+/*
+ * Copyright (C) 2013 Boundary Devices
+ * Copyright (C) 2013 SolidRun ltd.
+ * Copyright (C) 2013 Jon Nettleton <jon.nettleton@gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/* set the default clock gate to save power */
+DATA 4, CCM_CCGR0, 0x00C03F3F
+DATA 4, CCM_CCGR1, 0x0030FC03
+DATA 4, CCM_CCGR2, 0x0FFFC000
+DATA 4, CCM_CCGR3, 0x3FF00000
+DATA 4, CCM_CCGR4, 0x00FFF300
+DATA 4, CCM_CCGR5, 0x0F0000C3
+DATA 4, CCM_CCGR6, 0x000003FF
+
+/* enable AXI cache for VDOA/VPU/IPU */
+DATA 4, MX6_IOMUXC_GPR4, 0xF00000CF
+/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
+DATA 4, MX6_IOMUXC_GPR6, 0x007F007F
+DATA 4, MX6_IOMUXC_GPR7, 0x007F007F
+
+/*
+ * Setup CCM_CCOSR register as follows:
+ *
+ * cko1_en  = 1    --> CKO1 enabled
+ * cko1_div = 111  --> divide by 8
+ * cko1_sel = 1011 --> ahb_clk_root
+ *
+ * This sets CKO1 at ahb_clk_root/8 = 132/8 = 16.5 MHz
+ */
+DATA 4, CCM_CCOSR, 0x000000fb
diff --git a/board/solidrun/mx6-microsom/ddr-800mhz-32bit-setup.cfg b/board/solidrun/mx6-microsom/ddr-800mhz-32bit-setup.cfg
new file mode 100644
index 0000000000..f92fc19de4
--- /dev/null
+++ b/board/solidrun/mx6-microsom/ddr-800mhz-32bit-setup.cfg
@@ -0,0 +1,76 @@
+/*
+ * Copyright (C) 2013 Boundary Devices
+ * Copyright (C) 2013 SolidRun ltd.
+ * Copyright (C) 2013 Jon Nettleton <jon.nettleton@gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * DDR3 settings
+ * MX6Q    ddr is limited to 1066 Mhz	currently 1056 MHz(528 MHz clock),
+ *	   memory bus width: 64 bits	x16/x32/x64
+ * MX6DL   ddr is limited to 800 MHz(400 MHz clock)
+ *	   memory bus width: 64 bits	x16/x32/x64
+ * MX6SOLO ddr is limited to 800 MHz(400 MHz clock)
+ *	   memory bus width: 32 bits	x16/x32
+ */
+/* DDR IO TYPE */
+DATA 4, MX6_IOM_GRP_DDR_TYPE, 0x000c0000
+DATA 4, MX6_IOM_GRP_DDRPKE, 0x00000000
+/* Clock */
+DATA 4, MX6_IOM_DRAM_SDCLK_0, 0x00000028
+DATA 4, MX6_IOM_DRAM_SDCLK_1, 0x00000028
+/* Address */
+DATA 4, MX6_IOM_DRAM_CAS, 0x00000010
+DATA 4, MX6_IOM_DRAM_RAS, 0x00000010
+DATA 4, MX6_IOM_GRP_ADDDS, 0x00000010
+/* Control */
+DATA 4, MX6_IOM_DRAM_RESET, 0x00000010
+DATA 4, MX6_IOM_DRAM_SDCKE0, 0x00003000
+DATA 4, MX6_IOM_DRAM_SDCKE1, 0x00003000
+DATA 4, MX6_IOM_DRAM_SDBA2, 0x00000000
+DATA 4, MX6_IOM_DRAM_SDODT0, 0x00000010
+DATA 4, MX6_IOM_DRAM_SDODT1, 0x00000010
+DATA 4, MX6_IOM_GRP_CTLDS, 0x00000010
+
+/*
+ * Data Strobe: IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL - DDR_INPUT=0, CMOS,
+ * CMOS mode saves power, but have less timing margin in case of DDR
+ * timing issue on your board you can try DDR_MODE:  [= 0x00020000]
+ */
+DATA 4, MX6_IOM_DDRMODE_CTL, 0x00020000
+
+DATA 4, MX6_IOM_DRAM_SDQS0, 0x00000028
+DATA 4, MX6_IOM_DRAM_SDQS1, 0x00000028
+DATA 4, MX6_IOM_DRAM_SDQS2, 0x00000028
+DATA 4, MX6_IOM_DRAM_SDQS3, 0x00000028
+DATA 4, MX6_IOM_DRAM_SDQS4, 0x00000000
+DATA 4, MX6_IOM_DRAM_SDQS5, 0x00000000
+DATA 4, MX6_IOM_DRAM_SDQS6, 0x00000000
+DATA 4, MX6_IOM_DRAM_SDQS7, 0x00000000
+
+/*
+ * DATA:IOMUXC_SW_PAD_CTL_GRP_DDRMODE - DDR_INPUT=0, CMOS,
+ * CMOS mode saves power, but have less timing margin in case of DDR
+ * timing issue on your board you can try DDR_MODE:  [= 0x00020000]
+ */
+DATA 4, MX6_IOM_GRP_DDRMODE, 0x00020000
+
+DATA 4, MX6_IOM_GRP_B0DS, 0x00000028
+DATA 4, MX6_IOM_GRP_B1DS, 0x00000028
+DATA 4, MX6_IOM_GRP_B2DS, 0x00000028
+DATA 4, MX6_IOM_GRP_B3DS, 0x00000028
+DATA 4, MX6_IOM_GRP_B4DS, 0x00000000
+DATA 4, MX6_IOM_GRP_B5DS, 0x00000000
+DATA 4, MX6_IOM_GRP_B6DS, 0x00000000
+DATA 4, MX6_IOM_GRP_B7DS, 0x00000000
+
+DATA 4, MX6_IOM_DRAM_DQM0, 0x00000028
+DATA 4, MX6_IOM_DRAM_DQM1, 0x00000028
+DATA 4, MX6_IOM_DRAM_DQM2, 0x00000028
+DATA 4, MX6_IOM_DRAM_DQM3, 0x00000028
+DATA 4, MX6_IOM_DRAM_DQM4, 0x00000000
+DATA 4, MX6_IOM_DRAM_DQM5, 0x00000000
+DATA 4, MX6_IOM_DRAM_DQM6, 0x00000000
+DATA 4, MX6_IOM_DRAM_DQM7, 0x00000000
diff --git a/board/spc1920/Makefile b/board/spc1920/Makefile
index cadacee792..c0c9a32588 100644
--- a/board/spc1920/Makefile
+++ b/board/spc1920/Makefile
@@ -5,24 +5,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	= $(BOARD).o hpi.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	= spc1920.o hpi.o
diff --git a/board/spd8xx/Makefile b/board/spd8xx/Makefile
index 871865b6ee..c393f066cb 100644
--- a/board/spd8xx/Makefile
+++ b/board/spd8xx/Makefile
@@ -5,24 +5,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	= $(BOARD).o flash.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	= spd8xx.o flash.o
diff --git a/board/spd8xx/u-boot.lds b/board/spd8xx/u-boot.lds
index 2a68934c32..463af7eaa4 100644
--- a/board/spd8xx/u-boot.lds
+++ b/board/spd8xx/u-boot.lds
@@ -18,8 +18,8 @@ SECTIONS
 
     arch/powerpc/cpu/mpc8xx/start.o	(.text*)
     arch/powerpc/cpu/mpc8xx/traps.o	(.text*)
-    net/libnet.o			(.text*)
-    arch/powerpc/cpu/mpc8xx/libmpc8xx.o	(.text*)
+    net/built-in.o			(.text*)
+    arch/powerpc/cpu/mpc8xx/built-in.o	(.text*)
     *(.text.v*printf)
 
     . = DEFINED(env_offset) ? env_offset : .;
diff --git a/board/spear/common/Makefile b/board/spear/common/Makefile
index 6e397eeff0..b0ba320481 100644
--- a/board/spear/common/Makefile
+++ b/board/spear/common/Makefile
@@ -5,30 +5,10 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-ifneq ($(OBJTREE),$(SRCTREE))
-$(shell mkdir -p $(obj)board/$(VENDOR)/common)
+ifdef CONFIG_SPL_BUILD
+# necessary to create built-in.o
+obj- := __dummy__.o
+else
+obj-y	:= spr_misc.o
+obj-y	+= spr_lowlevel_init.o
 endif
-
-LIB	= $(obj)lib$(VENDOR).o
-
-ifndef CONFIG_SPL_BUILD
-COBJS	:= spr_misc.o
-SOBJS	:= spr_lowlevel_init.o
-endif
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
-	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
-
-#########################################################################
-# This is for $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
diff --git a/board/spear/spear300/Makefile b/board/spear/spear300/Makefile
index 63ff1d5e56..84d05e332e 100644
--- a/board/spear/spear300/Makefile
+++ b/board/spear/spear300/Makefile
@@ -5,25 +5,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	:= spear300.o
-SOBJS	:=
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
-	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	:= spear300.o
diff --git a/board/spear/spear300/spear300.c b/board/spear/spear300/spear300.c
index e25aba2f28..6b6bd9f29d 100644
--- a/board/spear/spear300/spear300.c
+++ b/board/spear/spear300/spear300.c
@@ -53,8 +53,7 @@ int board_eth_init(bd_t *bis)
 
 #if defined(CONFIG_DESIGNWARE_ETH)
 	u32 interface = PHY_INTERFACE_MODE_MII;
-	if (designware_initialize(0, CONFIG_SPEAR_ETHBASE, CONFIG_DW0_PHY,
-				interface) >= 0)
+	if (designware_initialize(CONFIG_SPEAR_ETHBASE, interface) >= 0)
 		ret++;
 #endif
 	return ret;
diff --git a/board/spear/spear310/Makefile b/board/spear/spear310/Makefile
index 5664097a7e..3a2e3ac086 100644
--- a/board/spear/spear310/Makefile
+++ b/board/spear/spear310/Makefile
@@ -5,25 +5,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	:= spear310.o
-SOBJS	:=
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
-	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	:= spear310.o
diff --git a/board/spear/spear310/spear310.c b/board/spear/spear310/spear310.c
index 70f9aa16ea..a4c6a8edb0 100644
--- a/board/spear/spear310/spear310.c
+++ b/board/spear/spear310/spear310.c
@@ -54,8 +54,7 @@ int board_eth_init(bd_t *bis)
 
 #if defined(CONFIG_DESIGNWARE_ETH)
 	u32 interface = PHY_INTERFACE_MODE_MII;
-	if (designware_initialize(0, CONFIG_SPEAR_ETHBASE, CONFIG_DW0_PHY,
-				interface) >= 0)
+	if (designware_initialize(CONFIG_SPEAR_ETHBASE, interface) >= 0)
 		ret++;
 #endif
 #if defined(CONFIG_MACB)
diff --git a/board/spear/spear320/Makefile b/board/spear/spear320/Makefile
index 986e495c70..f01116e6b1 100644
--- a/board/spear/spear320/Makefile
+++ b/board/spear/spear320/Makefile
@@ -5,25 +5,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	:= spear320.o
-SOBJS	:=
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
-	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	:= spear320.o
diff --git a/board/spear/spear320/spear320.c b/board/spear/spear320/spear320.c
index f6b1fdd0e6..ab732a724c 100644
--- a/board/spear/spear320/spear320.c
+++ b/board/spear/spear320/spear320.c
@@ -65,8 +65,7 @@ int board_eth_init(bd_t *bis)
 
 #if defined(CONFIG_DESIGNWARE_ETH)
 	u32 interface = PHY_INTERFACE_MODE_MII;
-	if (designware_initialize(0, CONFIG_SPEAR_ETHBASE, CONFIG_DW0_PHY,
-				interface) >= 0)
+	if (designware_initialize(CONFIG_SPEAR_ETHBASE, interface) >= 0)
 		ret++;
 #endif
 #if defined(CONFIG_MACB)
diff --git a/board/spear/spear600/Makefile b/board/spear/spear600/Makefile
index 123512b516..7abfb9ad50 100644
--- a/board/spear/spear600/Makefile
+++ b/board/spear/spear600/Makefile
@@ -5,27 +5,6 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
 ifndef CONFIG_SPL_BUILD
-COBJS	:= spear600.o
+obj-y	:= spear600.o
 endif
-SOBJS	:=
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
-	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
diff --git a/board/spear/spear600/spear600.c b/board/spear/spear600/spear600.c
index e996a0e381..8472002f74 100644
--- a/board/spear/spear600/spear600.c
+++ b/board/spear/spear600/spear600.c
@@ -51,8 +51,7 @@ int board_eth_init(bd_t *bis)
 #if defined(CONFIG_DW_AUTONEG)
 	interface = PHY_INTERFACE_MODE_GMII;
 #endif
-	if (designware_initialize(0, CONFIG_SPEAR_ETHBASE, CONFIG_DW0_PHY,
-				interface) >= 0)
+	if (designware_initialize(CONFIG_SPEAR_ETHBASE, interface) >= 0)
 		ret++;
 #endif
 	return ret;
diff --git a/board/spear/x600/Makefile b/board/spear/x600/Makefile
index 5524e4f5b1..18d3dd2e6f 100644
--- a/board/spear/x600/Makefile
+++ b/board/spear/x600/Makefile
@@ -5,27 +5,9 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-ifndef CONFIG_SPL_BUILD
-COBJS	:= fpga.o $(BOARD).o
+ifdef CONFIG_SPL_BUILD
+# necessary to create built-in.o
+obj- := __dummy__.o
+else
+obj-y	:= fpga.o x600.o
 endif
-SOBJS	:=
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
-	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
diff --git a/board/spear/x600/x600.c b/board/spear/x600/x600.c
index 044d2049ef..b8edfcd071 100644
--- a/board/spear/x600/x600.c
+++ b/board/spear/x600/x600.c
@@ -67,31 +67,32 @@ void board_nand_init(void)
 		fsmc_nand_init(nand);
 }
 
-int designware_board_phy_init(struct eth_device *dev, int phy_addr,
-	int (*mii_write)(struct eth_device *, u8, u8, u16),
-	int dw_reset_phy(struct eth_device *))
+int board_phy_config(struct phy_device *phydev)
 {
 	/* Extended PHY control 1, select GMII */
-	mii_write(dev, phy_addr, 23, 0x0020);
+	phy_write(phydev, MDIO_DEVAD_NONE, 23, 0x0020);
 
 	/* Software reset necessary after GMII mode selction */
-	dw_reset_phy(dev);
+	phy_reset(phydev);
 
 	/* Enable extended page register access */
-	mii_write(dev, phy_addr, 31, 0x0001);
+	phy_write(phydev, MDIO_DEVAD_NONE, 31, 0x0001);
 
 	/* 17e: Enhanced LED behavior, needs to be written twice */
-	mii_write(dev, phy_addr, 17, 0x09ff);
-	mii_write(dev, phy_addr, 17, 0x09ff);
+	phy_write(phydev, MDIO_DEVAD_NONE, 17, 0x09ff);
+	phy_write(phydev, MDIO_DEVAD_NONE, 17, 0x09ff);
 
 	/* 16e: Enhanced LED method select */
-	mii_write(dev, phy_addr, 16, 0xe0ea);
+	phy_write(phydev, MDIO_DEVAD_NONE, 16, 0xe0ea);
 
 	/* Disable extended page register access */
-	mii_write(dev, phy_addr, 31, 0x0000);
+	phy_write(phydev, MDIO_DEVAD_NONE, 31, 0x0000);
 
 	/* Enable clock output pin */
-	mii_write(dev, phy_addr, 18, 0x0049);
+	phy_write(phydev, MDIO_DEVAD_NONE, 18, 0x0049);
+
+	if (phydev->drv->config)
+		phydev->drv->config(phydev);
 
 	return 0;
 }
@@ -100,7 +101,7 @@ int board_eth_init(bd_t *bis)
 {
 	int ret = 0;
 
-	if (designware_initialize(0, CONFIG_SPEAR_ETHBASE, CONFIG_PHY_ADDR,
+	if (designware_initialize(CONFIG_SPEAR_ETHBASE,
 				  PHY_INTERFACE_MODE_GMII) >= 0)
 		ret++;
 
diff --git a/board/st-ericsson/snowball/Makefile b/board/st-ericsson/snowball/Makefile
index d6f45df3a5..f0605e2bcd 100644
--- a/board/st-ericsson/snowball/Makefile
+++ b/board/st-ericsson/snowball/Makefile
@@ -4,30 +4,6 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
+ccflags-y += -D__RELEASE -D__STN_8500
 
-CFLAGS += -D__RELEASE -D__STN_8500
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	:= snowball.o
-
-SRCS	:= $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-
-$(LIB): $(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-clean:
-	rm -f $(OBJS)
-
-distclean:	clean
-	rm -f $(LIB) core *.bak $(obj).depend
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	:= snowball.o
diff --git a/board/st-ericsson/u8500/Makefile b/board/st-ericsson/u8500/Makefile
index 4b901d25e8..d6c4280475 100644
--- a/board/st-ericsson/u8500/Makefile
+++ b/board/st-ericsson/u8500/Makefile
@@ -4,25 +4,6 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
+ccflags-y += -D__RELEASE -D__STN_8500
 
-CFLAGS += -D__RELEASE -D__STN_8500
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	:= u8500_href.o gpio.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB): $(obj).depend $(OBJS) $(SOBJS)
-	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	:= u8500_href.o gpio.o
diff --git a/board/st/nhk8815/Makefile b/board/st/nhk8815/Makefile
index b1c6197e0b..dd56944db1 100644
--- a/board/st/nhk8815/Makefile
+++ b/board/st/nhk8815/Makefile
@@ -9,25 +9,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	:= nhk8815.o
-SOBJS	:=
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB): $(obj).depend $(OBJS) $(SOBJS)
-	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	:= nhk8815.o
diff --git a/board/stx/stxgp3/Makefile b/board/stx/stxgp3/Makefile
index 0b0f26e724..78e2d6c96f 100644
--- a/board/stx/stxgp3/Makefile
+++ b/board/stx/stxgp3/Makefile
@@ -5,28 +5,8 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS-y	+= $(BOARD).o
-COBJS-y	+= law.o
-COBJS-y	+= tlb.o
-COBJS-y	+= flash.o
-COBJS-$(CONFIG_FSL_DDR1) += ddr.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS-y))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	+= stxgp3.o
+obj-y	+= law.o
+obj-y	+= tlb.o
+obj-y	+= flash.o
+obj-$(CONFIG_SYS_FSL_DDR1) += ddr.o
diff --git a/board/stx/stxgp3/ddr.c b/board/stx/stxgp3/ddr.c
index 571137443e..41d4cfe738 100644
--- a/board/stx/stxgp3/ddr.c
+++ b/board/stx/stxgp3/ddr.c
@@ -8,8 +8,8 @@
 
 #include <common.h>
 
-#include <asm/fsl_ddr_sdram.h>
-#include <asm/fsl_ddr_dimm_params.h>
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr_dimm_params.h>
 
 void fsl_ddr_board_options(memctl_options_t *popts,
 				dimm_params_t *pdimm,
@@ -36,7 +36,7 @@ void fsl_ddr_board_options(memctl_options_t *popts,
 	popts->write_data_delay = 3;
 
 	/* 2T timing enable */
-	popts->twoT_en = 1;
+	popts->twot_en = 1;
 
 	/*
 	 * Factors to consider for half-strength driver enable:
diff --git a/board/stx/stxgp3/stxgp3.c b/board/stx/stxgp3/stxgp3.c
index bd683f6af8..c80d5259ce 100644
--- a/board/stx/stxgp3/stxgp3.c
+++ b/board/stx/stxgp3/stxgp3.c
@@ -18,7 +18,7 @@
 #include <asm/processor.h>
 #include <asm/mmu.h>
 #include <asm/immap_85xx.h>
-#include <asm/fsl_ddr_sdram.h>
+#include <fsl_ddr_sdram.h>
 #include <ioports.h>
 #include <asm/io.h>
 #include <spd_sdram.h>
diff --git a/board/stx/stxssa/Makefile b/board/stx/stxssa/Makefile
index 8757a71a82..b1d4b0a270 100644
--- a/board/stx/stxssa/Makefile
+++ b/board/stx/stxssa/Makefile
@@ -5,27 +5,7 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS-y	+= $(BOARD).o
-COBJS-y	+= law.o
-COBJS-y	+= tlb.o
-COBJS-$(CONFIG_FSL_DDR1) += ddr.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS-y))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	+= stxssa.o
+obj-y	+= law.o
+obj-y	+= tlb.o
+obj-$(CONFIG_SYS_FSL_DDR1) += ddr.o
diff --git a/board/stx/stxssa/ddr.c b/board/stx/stxssa/ddr.c
index 56c87b2fc6..1ccd4c5183 100644
--- a/board/stx/stxssa/ddr.c
+++ b/board/stx/stxssa/ddr.c
@@ -9,8 +9,8 @@
 #include <common.h>
 #include <i2c.h>
 
-#include <asm/fsl_ddr_sdram.h>
-#include <asm/fsl_ddr_dimm_params.h>
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr_dimm_params.h>
 
 void fsl_ddr_board_options(memctl_options_t *popts,
 				dimm_params_t *pdimm,
@@ -37,7 +37,7 @@ void fsl_ddr_board_options(memctl_options_t *popts,
 	popts->write_data_delay = 3;
 
 	/* 2T timing enable */
-	popts->twoT_en = 1;
+	popts->twot_en = 1;
 
 	/*
 	 * Factors to consider for half-strength driver enable:
diff --git a/board/stx/stxssa/stxssa.c b/board/stx/stxssa/stxssa.c
index c08a18bffe..f5c3d750ce 100644
--- a/board/stx/stxssa/stxssa.c
+++ b/board/stx/stxssa/stxssa.c
@@ -19,7 +19,7 @@
 #include <asm/mmu.h>
 #include <asm/immap_85xx.h>
 #include <asm/fsl_pci.h>
-#include <asm/fsl_ddr_sdram.h>
+#include <fsl_ddr_sdram.h>
 #include <ioports.h>
 #include <asm/io.h>
 #include <spd_sdram.h>
diff --git a/board/stx/stxxtc/Makefile b/board/stx/stxxtc/Makefile
index e7f4fb63b0..6738d4e15d 100644
--- a/board/stx/stxxtc/Makefile
+++ b/board/stx/stxxtc/Makefile
@@ -5,24 +5,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	= $(BOARD).o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	= stxxtc.o
diff --git a/board/svm_sc8xx/Makefile b/board/svm_sc8xx/Makefile
index 871865b6ee..4c0b4a33e9 100644
--- a/board/svm_sc8xx/Makefile
+++ b/board/svm_sc8xx/Makefile
@@ -5,24 +5,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	= $(BOARD).o flash.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	= svm_sc8xx.o flash.o
diff --git a/board/svm_sc8xx/u-boot.lds b/board/svm_sc8xx/u-boot.lds
index 49226251b2..df564e9395 100644
--- a/board/svm_sc8xx/u-boot.lds
+++ b/board/svm_sc8xx/u-boot.lds
@@ -17,11 +17,11 @@ SECTIONS
     /* the sector layout of our flash chips!	XXX FIXME XXX	*/
     arch/powerpc/cpu/mpc8xx/start.o	(.text*)
     arch/powerpc/cpu/mpc8xx/traps.o	(.text*)
-    lib/libgeneric.o			(.text*)
-    net/libnet.o			(.text*)
-    arch/powerpc/cpu/mpc8xx/libmpc8xx.o	(.text*)
-    arch/powerpc/lib/libpowerpc.o	(.text*)
-    board/svm_sc8xx/libsvm_sc8xx.o	(.text*)
+    lib/built-in.o			(.text*)
+    net/built-in.o			(.text*)
+    arch/powerpc/cpu/mpc8xx/built-in.o	(.text*)
+    arch/powerpc/lib/built-in.o		(.text*)
+    board/svm_sc8xx/built-in.o		(.text*)
     *(.text.*printf)
     *(.text.do_mem_*)
     *(.text.flash*)
diff --git a/board/synopsys/axs101/Makefile b/board/synopsys/axs101/Makefile
new file mode 100644
index 0000000000..f0965f7841
--- /dev/null
+++ b/board/synopsys/axs101/Makefile
@@ -0,0 +1,8 @@
+#
+# Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y	+= axs101.o
+obj-$(CONFIG_CMD_NAND) += nand.o
diff --git a/board/synopsys/axs101/axs101.c b/board/synopsys/axs101/axs101.c
new file mode 100644
index 0000000000..d1271ffcca
--- /dev/null
+++ b/board/synopsys/axs101/axs101.c
@@ -0,0 +1,44 @@
+/*
+ * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <dwmmc.h>
+#include <malloc.h>
+#include <netdev.h>
+#include <phy.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_mmc_init(bd_t *bis)
+{
+	struct dwmci_host *host = NULL;
+
+	host = malloc(sizeof(struct dwmci_host));
+	if (!host) {
+		printf("dwmci_host malloc fail!\n");
+		return 1;
+	}
+
+	memset(host, 0, sizeof(struct dwmci_host));
+	host->name = "Synopsys Mobile storage";
+	host->ioaddr = (void *)ARC_DWMMC_BASE;
+	host->buswidth = 4;
+	host->dev_index = 0;
+	host->bus_hz = 25000000;
+
+	add_dwmci(host, 52000000, 400000);
+
+	return 0;
+}
+
+int board_eth_init(bd_t *bis)
+{
+	if (designware_initialize(ARC_DWGMAC_BASE,
+				  PHY_INTERFACE_MODE_RGMII) >= 0)
+		return 1;
+
+	return 0;
+}
diff --git a/board/synopsys/axs101/nand.c b/board/synopsys/axs101/nand.c
new file mode 100644
index 0000000000..c7f90c4400
--- /dev/null
+++ b/board/synopsys/axs101/nand.c
@@ -0,0 +1,234 @@
+/*
+ * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <bouncebuf.h>
+#include <common.h>
+#include <malloc.h>
+#include <nand.h>
+#include <asm/io.h>
+
+#define BUS_WIDTH	8		/* AXI data bus width in bytes	*/
+
+/* DMA buffer descriptor bits & masks */
+#define BD_STAT_OWN			(1 << 31)
+#define BD_STAT_BD_FIRST		(1 << 3)
+#define BD_STAT_BD_LAST			(1 << 2)
+#define BD_SIZES_BUFFER1_MASK		0xfff
+
+#define BD_STAT_BD_COMPLETE	(BD_STAT_BD_FIRST | BD_STAT_BD_LAST)
+
+/* Controller command flags */
+#define B_WFR		(1 << 19)	/* 1b - Wait for ready		*/
+#define B_LC		(1 << 18)	/* 1b - Last cycle		*/
+#define B_IWC		(1 << 13)	/* 1b - Interrupt when complete	*/
+
+/* NAND cycle types */
+#define B_CT_ADDRESS	(0x0 << 16)	/* Address operation		*/
+#define B_CT_COMMAND	(0x1 << 16)	/* Command operation		*/
+#define B_CT_WRITE	(0x2 << 16)	/* Write operation		*/
+#define B_CT_READ	(0x3 << 16)	/* Write operation		*/
+
+enum nand_isr_t {
+	NAND_ISR_DATAREQUIRED = 0,
+	NAND_ISR_TXUNDERFLOW,
+	NAND_ISR_TXOVERFLOW,
+	NAND_ISR_DATAAVAILABLE,
+	NAND_ISR_RXUNDERFLOW,
+	NAND_ISR_RXOVERFLOW,
+	NAND_ISR_TXDMACOMPLETE,
+	NAND_ISR_RXDMACOMPLETE,
+	NAND_ISR_DESCRIPTORUNAVAILABLE,
+	NAND_ISR_CMDDONE,
+	NAND_ISR_CMDAVAILABLE,
+	NAND_ISR_CMDERROR,
+	NAND_ISR_DATATRANSFEROVER,
+	NAND_ISR_NONE
+};
+
+enum nand_regs_t {
+	AC_FIFO = 0,		/* address and command fifo */
+	IDMAC_BDADDR = 0x18,	/* idmac descriptor list base address */
+	INT_STATUS = 0x118,	/* interrupt status register */
+	INT_CLR_STATUS = 0x120,	/* interrupt clear status register */
+};
+
+struct nand_bd {
+	uint32_t status;	/* DES0 */
+	uint32_t sizes;		/* DES1 */
+	uint32_t buffer_ptr0;	/* DES2 */
+	uint32_t buffer_ptr1;	/* DES3 */
+};
+
+#define NAND_REG_WRITE(r, v)	writel(v, CONFIG_SYS_NAND_BASE + r)
+#define NAND_REG_READ(r)	readl(CONFIG_SYS_NAND_BASE + r)
+
+static struct nand_bd *bd;	/* DMA buffer descriptors	*/
+
+/**
+ * axs101_nand_write_buf -  write buffer to chip
+ * @mtd:	MTD device structure
+ * @buf:	data buffer
+ * @len:	number of bytes to write
+ */
+static uint32_t nand_flag_is_set(uint32_t flag)
+{
+	uint32_t reg = NAND_REG_READ(INT_STATUS);
+
+	if (reg & (1 << NAND_ISR_CMDERROR))
+		return 0;
+
+	if (reg & (1 << flag)) {
+		NAND_REG_WRITE(INT_CLR_STATUS, 1 << flag);
+		return 1;
+	}
+
+	return 0;
+}
+
+/**
+ * axs101_nand_write_buf -  write buffer to chip
+ * @mtd:	MTD device structure
+ * @buf:	data buffer
+ * @len:	number of bytes to write
+ */
+static void axs101_nand_write_buf(struct mtd_info *mtd, const u_char *buf,
+				   int len)
+{
+	struct bounce_buffer bbstate;
+
+	bounce_buffer_start(&bbstate, (void *)buf, len, GEN_BB_READ);
+
+	/* Setup buffer descriptor */
+	writel(BD_STAT_OWN | BD_STAT_BD_COMPLETE, &bd->status);
+	writel(ALIGN(len, BUS_WIDTH) & BD_SIZES_BUFFER1_MASK, &bd->sizes);
+	writel(bbstate.bounce_buffer, &bd->buffer_ptr0);
+	writel(0, &bd->buffer_ptr1);
+
+	/* Flush modified buffer descriptor */
+	flush_dcache_range((unsigned long)bd,
+			   (unsigned long)bd + sizeof(struct nand_bd));
+
+	/* Issue "write" command */
+	NAND_REG_WRITE(AC_FIFO, B_CT_WRITE | B_WFR | B_IWC | B_LC | (len-1));
+
+	/* Wait for NAND command and DMA to complete */
+	while (!nand_flag_is_set(NAND_ISR_CMDDONE))
+		;
+	while (!nand_flag_is_set(NAND_ISR_TXDMACOMPLETE))
+		;
+
+	bounce_buffer_stop(&bbstate);
+}
+
+/**
+ * axs101_nand_read_buf -  read chip data into buffer
+ * @mtd:	MTD device structure
+ * @buf:	buffer to store data
+ * @len:	number of bytes to read
+ */
+static void axs101_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len)
+{
+	struct bounce_buffer bbstate;
+
+	bounce_buffer_start(&bbstate, buf, len, GEN_BB_WRITE);
+
+	/* Setup buffer descriptor */
+	writel(BD_STAT_OWN | BD_STAT_BD_COMPLETE, &bd->status);
+	writel(ALIGN(len, BUS_WIDTH) & BD_SIZES_BUFFER1_MASK, &bd->sizes);
+	writel(bbstate.bounce_buffer, &bd->buffer_ptr0);
+	writel(0, &bd->buffer_ptr1);
+
+	/* Flush modified buffer descriptor */
+	flush_dcache_range((unsigned long)bd,
+			   (unsigned long)bd + sizeof(struct nand_bd));
+
+	/* Issue "read" command */
+	NAND_REG_WRITE(AC_FIFO, B_CT_READ | B_WFR | B_IWC | B_LC | (len - 1));
+
+	/* Wait for NAND command and DMA to complete */
+	while (!nand_flag_is_set(NAND_ISR_CMDDONE))
+		;
+	while (!nand_flag_is_set(NAND_ISR_RXDMACOMPLETE))
+		;
+
+	bounce_buffer_stop(&bbstate);
+}
+
+/**
+ * axs101_nand_read_byte -  read one byte from the chip
+ * @mtd:	MTD device structure
+ */
+static u_char axs101_nand_read_byte(struct mtd_info *mtd)
+{
+	u8 byte;
+
+	axs101_nand_read_buf(mtd, (uchar *)&byte, sizeof(byte));
+	return byte;
+}
+
+/**
+ * axs101_nand_read_word -  read one word from the chip
+ * @mtd:	MTD device structure
+ */
+static u16 axs101_nand_read_word(struct mtd_info *mtd)
+{
+	u16 word;
+
+	axs101_nand_read_buf(mtd, (uchar *)&word, sizeof(word));
+	return word;
+}
+
+/**
+ * axs101_nand_hwcontrol - NAND control functions wrapper.
+ * @mtd:	MTD device structure
+ * @cmd:	Command
+ */
+static void axs101_nand_hwcontrol(struct mtd_info *mtdinfo, int cmd,
+				   unsigned int ctrl)
+{
+	if (cmd == NAND_CMD_NONE)
+		return;
+
+	cmd = cmd & 0xff;
+
+	switch (ctrl & (NAND_ALE | NAND_CLE)) {
+	/* Address */
+	case NAND_ALE:
+		cmd |= B_CT_ADDRESS;
+		break;
+
+	/* Command */
+	case NAND_CLE:
+		cmd |= B_CT_COMMAND | B_WFR;
+
+		break;
+
+	default:
+		debug("%s: unknown ctrl %#x\n", __func__, ctrl);
+	}
+
+	NAND_REG_WRITE(AC_FIFO, cmd | B_LC);
+	while (!nand_flag_is_set(NAND_ISR_CMDDONE))
+		;
+}
+
+int board_nand_init(struct nand_chip *nand)
+{
+	bd = (struct nand_bd *)memalign(ARCH_DMA_MINALIGN,
+					sizeof(struct nand_bd));
+
+	/* Set buffer descriptor address in IDMAC */
+	NAND_REG_WRITE(IDMAC_BDADDR, bd);
+
+	nand->ecc.mode = NAND_ECC_SOFT;
+	nand->cmd_ctrl = axs101_nand_hwcontrol;
+	nand->read_byte = axs101_nand_read_byte;
+	nand->read_word = axs101_nand_read_word;
+	nand->write_buf = axs101_nand_write_buf;
+	nand->read_buf = axs101_nand_read_buf;
+
+	return 0;
+}
diff --git a/board/syteco/jadecpu/Makefile b/board/syteco/jadecpu/Makefile
index 8e96c5e44a..74264361e5 100644
--- a/board/syteco/jadecpu/Makefile
+++ b/board/syteco/jadecpu/Makefile
@@ -9,25 +9,5 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS-y	+= jadecpu.o
-SOBJS	:= lowlevel_init.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS-y))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
-	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	+= jadecpu.o
+obj-y	+= lowlevel_init.o
diff --git a/board/syteco/zmx25/Makefile b/board/syteco/zmx25/Makefile
index 8c289bde30..d5edb48ab8 100644
--- a/board/syteco/zmx25/Makefile
+++ b/board/syteco/zmx25/Makefile
@@ -5,25 +5,5 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS-y	+= zmx25.o
-SOBJS	:= lowlevel_init.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS-y))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
-	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	+= zmx25.o
+obj-y	+= lowlevel_init.o
diff --git a/board/t3corp/Makefile b/board/t3corp/Makefile
index 093457f591..928d895d50 100644
--- a/board/t3corp/Makefile
+++ b/board/t3corp/Makefile
@@ -5,29 +5,6 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS-y	:= $(BOARD).o
-COBJS-$(CONFIG_CMD_CHIP_CONFIG) += chip_config.o
-SOBJS	:= init.o
-
-COBJS   := $(COBJS-y)
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-all:	$(LIB) $(SOBJS)
-
-$(LIB):	$(OBJS)
-	$(call cmd_link_o_target, $^)
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	:= t3corp.o
+obj-$(CONFIG_CMD_CHIP_CONFIG) += chip_config.o
+extra-y += init.o
diff --git a/board/taskit/stamp9g20/Makefile b/board/taskit/stamp9g20/Makefile
index 3909447de5..d015e0f740 100644
--- a/board/taskit/stamp9g20/Makefile
+++ b/board/taskit/stamp9g20/Makefile
@@ -13,25 +13,5 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS-y	+= stamp9g20.o
-COBJS-y	+= led.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS-y))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
-	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	+= stamp9g20.o
+obj-y	+= led.o
diff --git a/board/taskit/stamp9g20/stamp9g20.c b/board/taskit/stamp9g20/stamp9g20.c
index 704a63bad8..27cdf77f01 100644
--- a/board/taskit/stamp9g20/stamp9g20.c
+++ b/board/taskit/stamp9g20/stamp9g20.c
@@ -19,7 +19,6 @@
 #include <asm/arch/at91sam9_smc.h>
 #include <asm/arch/at91_common.h>
 #include <asm/arch/at91_pmc.h>
-#include <asm/arch/at91_rstc.h>
 #include <asm/arch/gpio.h>
 #include <watchdog.h>
 
@@ -67,8 +66,6 @@ static void stamp9G20_nand_hw_init(void)
 static void stamp9G20_macb_hw_init(void)
 {
 	struct at91_port *pioa = (struct at91_port *)ATMEL_BASE_PIOA;
-	struct at91_rstc *rstc = (struct at91_rstc *)ATMEL_BASE_RSTC;
-	unsigned long erstl;
 
 	/* Enable the PHY Chip via PA26 on the Stamp 2 Adaptor */
 	at91_set_gpio_output(AT91_PIN_PA26, 0);
@@ -91,33 +88,7 @@ static void stamp9G20_macb_hw_init(void)
 		pin_to_mask(AT91_PIN_PA28),
 		&pioa->pudr);
 
-	erstl = readl(&rstc->mr) & AT91_RSTC_MR_ERSTL_MASK;
-
-	/* Need to reset PHY -> 500ms reset */
-	writel(AT91_RSTC_KEY | (AT91_RSTC_MR_ERSTL(13) &
-				~AT91_RSTC_MR_URSTEN), &rstc->mr);
-	writel(AT91_RSTC_KEY | AT91_RSTC_CR_EXTRST, &rstc->cr);
-
-	/* Wait for end of hardware reset */
-	unsigned long start = get_timer(0);
-	unsigned long timeout = 1000; /* 1000ms */
-
-	while (!(readl(&rstc->sr) & AT91_RSTC_SR_NRSTL)) {
-
-		/* avoid shutdown by watchdog */
-		WATCHDOG_RESET();
-		mdelay(10);
-
-		/* timeout for not getting stuck in an endless loop */
-		if (get_timer(start) >= timeout) {
-			puts("*** ERROR: Timeout waiting for PHY reset!\n");
-			break;
-		};
-	};
-
-	/* Restore NRST value */
-	writel(AT91_RSTC_KEY | erstl | AT91_RSTC_MR_URSTEN,
-		&rstc->mr);
+	at91_phy_reset();
 
 	/* Re-enable pull-up */
 	writel(pin_to_mask(AT91_PIN_PA14) |
diff --git a/board/tcm-bf518/Makefile b/board/tcm-bf518/Makefile
index b7275f49fe..2e029f5ce8 100644
--- a/board/tcm-bf518/Makefile
+++ b/board/tcm-bf518/Makefile
@@ -9,24 +9,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS-y	:= $(BOARD).o
-
-SRCS	:= $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS-y))
-SOBJS	:= $(addprefix $(obj),$(SOBJS-y))
-
-$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
-	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	:= tcm-bf518.o
diff --git a/board/tcm-bf518/config.mk b/board/tcm-bf518/config.mk
deleted file mode 100644
index f1ef9bf682..0000000000
--- a/board/tcm-bf518/config.mk
+++ /dev/null
@@ -1,12 +0,0 @@
-#
-# Copyright (c) 2005-2008 Analog Device Inc.
-#
-# (C) Copyright 2001
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-CFLAGS_lib += -O2
-CFLAGS_lib/lzma += -O2
-CFLAGS_lib/zlib += -O2
diff --git a/board/tcm-bf537/Makefile b/board/tcm-bf537/Makefile
index 57b0a7c83d..93a01e4a3c 100644
--- a/board/tcm-bf537/Makefile
+++ b/board/tcm-bf537/Makefile
@@ -9,24 +9,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS-y	:= $(BOARD).o gpio_cfi_flash.o
-
-SRCS	:= $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS-y))
-SOBJS	:= $(addprefix $(obj),$(SOBJS-y))
-
-$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
-	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	:= tcm-bf537.o gpio_cfi_flash.o
diff --git a/board/tcm-bf537/config.mk b/board/tcm-bf537/config.mk
index 973d357559..7f9138b09b 100644
--- a/board/tcm-bf537/config.mk
+++ b/board/tcm-bf537/config.mk
@@ -7,9 +7,5 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-CFLAGS_lib += -O2
-CFLAGS_lib/lzma += -O2
-CFLAGS_lib/zlib += -O2
-
 # Set some default LDR flags based on boot mode.
 LDR_FLAGS-BFIN_BOOT_PARA := --bits 16 --dma 8
diff --git a/board/technexion/tao3530/Makefile b/board/technexion/tao3530/Makefile
new file mode 100644
index 0000000000..2aff38311c
--- /dev/null
+++ b/board/technexion/tao3530/Makefile
@@ -0,0 +1,5 @@
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y	:= tao3530.o
diff --git a/board/technexion/tao3530/tao3530.c b/board/technexion/tao3530/tao3530.c
new file mode 100644
index 0000000000..44a82406aa
--- /dev/null
+++ b/board/technexion/tao3530/tao3530.c
@@ -0,0 +1,215 @@
+/*
+ * Maintainer :
+ *      Tapani Utriainen <linuxfae@technexion.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+#include <common.h>
+#include <netdev.h>
+#include <twl4030.h>
+#include <asm/io.h>
+#include <asm/arch/mmc_host_def.h>
+#include <asm/arch/mem.h>
+#include <asm/arch/mux.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/gpio.h>
+#include <asm/gpio.h>
+#include <asm/mach-types.h>
+
+#include <usb.h>
+#include <asm/ehci-omap.h>
+
+#include "tao3530.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int tao3530_revision(void)
+{
+	int ret = 0;
+
+	/* char *label argument is unused in gpio_request() */
+	ret = gpio_request(65, "");
+	if (ret) {
+		puts("Error: GPIO 65 not available\n");
+		goto out;
+	}
+	MUX_VAL(CP(GPMC_WAIT3),	(IEN  | PTU | EN  | M4));
+
+	ret = gpio_request(1, "");
+	if (ret) {
+		puts("Error: GPIO 1 not available\n");
+		goto out2;
+	}
+	MUX_VAL(CP(SYS_CLKREQ), (IEN  | PTU | EN | M4));
+
+	ret = gpio_direction_input(65);
+	if (ret) {
+		puts("Error: GPIO 65 not available for input\n");
+		goto out3;
+	}
+
+	ret =  gpio_direction_input(1);
+	if (ret) {
+		puts("Error: GPIO 1 not available for input\n");
+		goto out3;
+	}
+
+	ret = gpio_get_value(65) << 1 | gpio_get_value(1);
+
+out3:
+	MUX_VAL(CP(SYS_CLKREQ), (IEN  | PTU | EN | M0));
+	gpio_free(1);
+out2:
+	MUX_VAL(CP(GPMC_WAIT3),	(IEN  | PTU | EN  | M0));
+	gpio_free(65);
+out:
+
+	return ret;
+}
+
+#ifdef CONFIG_SPL_BUILD
+/*
+ * Routine: get_board_mem_timings
+ * Description: If we use SPL then there is no x-loader nor config header
+ * so we have to setup the DDR timings ourself on both banks.
+ */
+void get_board_mem_timings(struct board_sdrc_timings *timings)
+{
+#if defined(CONFIG_SYS_BOARD_OMAP3_HA)
+	/*
+	 * Switch baseboard LED to red upon power-on
+	 */
+	MUX_OMAP3_HA();
+
+	/* Request a gpio before using it */
+	gpio_request(111, "");
+	/* Sets the gpio as output and its value to 1, switch LED to red */
+	gpio_direction_output(111, 1);
+#endif
+
+	if (tao3530_revision() < 3) {
+		/* 256MB / Bank */
+		timings->mcfg = MCFG(256 << 20, 14);	/* RAS-width 14 */
+		timings->ctrla = HYNIX_V_ACTIMA_165;
+		timings->ctrlb = HYNIX_V_ACTIMB_165;
+	} else {
+		/* 128MB / Bank */
+		timings->mcfg = MCFG(128 << 20, 13);	/* RAS-width 13 */
+		timings->ctrla = MICRON_V_ACTIMA_165;
+		timings->ctrlb = MICRON_V_ACTIMB_165;
+	}
+
+	timings->mr = MICRON_V_MR_165;
+	timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
+}
+#endif
+
+/*
+ * Routine: board_init
+ * Description: Early hardware init.
+ */
+int board_init(void)
+{
+	gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
+	/* board id for Linux */
+	gd->bd->bi_arch_number = MACH_TYPE_OMAP3_TAO3530;
+	/* boot param addr */
+	gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
+
+	return 0;
+}
+
+/*
+ * Routine: misc_init_r
+ * Description: Configure board specific parts
+ */
+int misc_init_r(void)
+{
+	struct gpio *gpio5_base = (struct gpio *)OMAP34XX_GPIO5_BASE;
+	struct gpio *gpio6_base = (struct gpio *)OMAP34XX_GPIO6_BASE;
+
+	twl4030_power_init();
+	twl4030_led_init(TWL4030_LED_LEDEN_LEDAON | TWL4030_LED_LEDEN_LEDBON);
+
+	/* Configure GPIOs to output */
+	/* GPIO23 */
+	writel(~(GPIO10 | GPIO8 | GPIO2 | GPIO1), &gpio6_base->oe);
+	writel(~(GPIO31 | GPIO30 | GPIO22 | GPIO21 |
+		 GPIO15 | GPIO14 | GPIO13 | GPIO12), &gpio5_base->oe);
+
+	/* Set GPIOs */
+	writel(GPIO10 | GPIO8 | GPIO2 | GPIO1,
+	       &gpio6_base->setdataout);
+	writel(GPIO31 | GPIO30 | GPIO29 | GPIO28 | GPIO22 | GPIO21 |
+	       GPIO15 | GPIO14 | GPIO13 | GPIO12, &gpio5_base->setdataout);
+
+	switch (tao3530_revision()) {
+	case 0:
+		puts("TAO-3530 REV Reserve 1\n");
+		break;
+	case 1:
+		puts("TAO-3530 REV Reserve 2\n");
+		break;
+	case 2:
+		puts("TAO-3530 REV Cx\n");
+		break;
+	case 3:
+		puts("TAO-3530 REV Ax/Bx\n");
+		break;
+	default:
+		puts("Unknown board revision\n");
+	}
+
+	dieid_num_r();
+
+	return 0;
+}
+
+/*
+ * Routine: set_muxconf_regs
+ * Description: Setting up the configuration Mux registers specific to the
+ *		hardware. Many pins need to be moved from protect to primary
+ *		mode.
+ */
+void set_muxconf_regs(void)
+{
+	MUX_TAO3530();
+#if defined(CONFIG_SYS_BOARD_OMAP3_HA)
+	MUX_OMAP3_HA();
+#endif
+}
+
+#if defined(CONFIG_GENERIC_MMC) && !defined(CONFIG_SPL_BUILD)
+int board_mmc_init(bd_t *bis)
+{
+	omap_mmc_init(0, 0, 0, -1, -1);
+
+	return 0;
+}
+#endif
+
+#if defined(CONFIG_USB_EHCI) && !defined(CONFIG_SPL_BUILD)
+/* Call usb_stop() before starting the kernel */
+void show_boot_progress(int val)
+{
+	if (val == BOOTSTAGE_ID_RUN_OS)
+		usb_stop();
+}
+
+static struct omap_usbhs_board_data usbhs_bdata = {
+	.port_mode[0] = OMAP_USBHS_PORT_MODE_UNUSED,
+	.port_mode[1] = OMAP_EHCI_PORT_MODE_PHY,
+	.port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED
+};
+
+int ehci_hcd_init(int index, enum usb_init_type init,
+		  struct ehci_hccr **hccr, struct ehci_hcor **hcor)
+{
+	return omap_ehci_hcd_init(index, &usbhs_bdata, hccr, hcor);
+}
+
+int ehci_hcd_stop(int index)
+{
+	return omap_ehci_hcd_stop();
+}
+#endif /* CONFIG_USB_EHCI */
diff --git a/board/technexion/tao3530/tao3530.h b/board/technexion/tao3530/tao3530.h
new file mode 100644
index 0000000000..daff109480
--- /dev/null
+++ b/board/technexion/tao3530/tao3530.h
@@ -0,0 +1,371 @@
+/*
+ * (C) Copyright TechNexion 2010
+ * Edward Lin <linuxfae@technexion.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+#ifndef _TAO3530_H_
+#define _TAO3530_H_
+
+const omap3_sysinfo sysinfo = {
+	DDR_STACKED,
+#if defined(CONFIG_SYS_BOARD_OMAP3_HA)
+	"HEAD acoustics OMAP3-HA",
+#else
+	"OMAP3 TAO-3530 board",
+#endif
+	"NAND",
+};
+
+/*
+ * IEN  - Input Enable
+ * IDIS - Input Disable
+ * PTD  - Pull type Down
+ * PTU  - Pull type Up
+ * DIS  - Pull type selection is inactive
+ * EN   - Pull type selection is active
+ * M0   - Mode 0
+ * The commented string gives the final mux configuration for that pin
+ */
+#define MUX_TAO3530() \
+ /*SDRC*/\
+	MUX_VAL(CP(SDRC_D0),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D1),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D2),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D3),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D4),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D5),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D6),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D7),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D8),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D9),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D10),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D11),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D12),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D13),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D14),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D15),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D16),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D17),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D18),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D19),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D20),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D21),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D22),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D23),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D24),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D25),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D26),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D27),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D28),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D29),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D30),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D31),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_CLK),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_DQS0),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_DQS1),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_DQS2),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_DQS3),	(IEN  | PTD | DIS | M0)) \
+ /*GPMC*/\
+	MUX_VAL(CP(GPMC_A1),	(IDIS | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_A2),	(IDIS | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_A3),	(IDIS | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_A4),	(IDIS | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_A5),	(IDIS | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_A6),	(IDIS | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_A7),	(IDIS | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_A8),	(IDIS | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_A9),	(IDIS | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_A10),	(IDIS | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_D0),	(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_D1),	(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_D2),	(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_D3),	(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_D4),	(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_D5),	(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_D6),	(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_D7),	(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_D8),	(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_D9),	(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_D10),	(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_D11),	(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_D12),	(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_D13),	(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_D14),	(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_D15),	(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_NCS0),	(IDIS | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_NCS1),	(IDIS | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_NCS2),	(IDIS | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_NCS3),	(IDIS | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_NCS4),	(IDIS | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_NCS5),	(IDIS | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_NCS6),	(IEN  | PTD | EN | M0)) \
+	MUX_VAL(CP(GPMC_NCS7),	(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_CLK),	(IDIS | PTU | EN | M0)) \
+	MUX_VAL(CP(GPMC_NADV_ALE), (IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(GPMC_NOE),	(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(GPMC_NWE),	(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(GPMC_NBE0_CLE), (IDIS | PTU | EN | M0)) \
+	MUX_VAL(CP(GPMC_NBE1),	(IEN  | PTU | EN | M0)) \
+	MUX_VAL(CP(GPMC_NWP),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(GPMC_WAIT0),	(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_WAIT1),	(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_WAIT2),	(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_WAIT3),	(IEN  | PTU | EN  | M0)) \
+ /*DSS*/\
+	MUX_VAL(CP(DSS_PCLK),	(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(DSS_HSYNC),	(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(DSS_VSYNC),	(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(DSS_ACBIAS),	(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(DSS_DATA0),	(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(DSS_DATA1),	(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(DSS_DATA2),	(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(DSS_DATA3),	(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(DSS_DATA4),	(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(DSS_DATA5),	(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(DSS_DATA6),	(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(DSS_DATA7),	(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(DSS_DATA8),	(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(DSS_DATA9),	(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(DSS_DATA10),	(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(DSS_DATA11),	(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(DSS_DATA12),	(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(DSS_DATA13),	(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(DSS_DATA14),	(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(DSS_DATA15),	(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(DSS_DATA16),	(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(DSS_DATA17),	(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(DSS_DATA18),	(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(DSS_DATA19),	(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(DSS_DATA20),	(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(DSS_DATA21),	(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(DSS_DATA22),	(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(DSS_DATA23),	(IDIS | PTD | DIS | M0)) \
+ /*CAMERA*/\
+	MUX_VAL(CP(CAM_HS),	(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(CAM_VS),	(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(CAM_XCLKA),	(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(CAM_PCLK),	(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(CAM_FLD),	(IDIS | PTD | DIS | M4)) \
+ /* - CAM_RESET*/\
+	MUX_VAL(CP(CAM_D0),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(CAM_D1),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(CAM_D2),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(CAM_D3),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(CAM_D4),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(CAM_D5),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(CAM_D6),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(CAM_D7),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(CAM_D8),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(CAM_D9),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(CAM_D10),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(CAM_D11),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(CAM_XCLKB),	(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(CAM_WEN),	(IEN  | PTD | DIS | M4)) \
+	MUX_VAL(CP(CAM_STROBE),	(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(CSI2_DX0),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(CSI2_DY0),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(CSI2_DX1),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(CSI2_DY1),	(IEN  | PTD | DIS | M0)) \
+ /*Audio Interface */\
+	MUX_VAL(CP(MCBSP2_FSX),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(MCBSP2_CLKX), (IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(MCBSP2_DR),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(MCBSP2_DX),	(IDIS | PTD | DIS | M0)) \
+ /*Expansion card */\
+	MUX_VAL(CP(MMC1_CLK),	(IDIS | PTU | EN  | M0)) \
+	MUX_VAL(CP(MMC1_CMD),	(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(MMC1_DAT0),	(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(MMC1_DAT1),	(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(MMC1_DAT2),	(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(MMC1_DAT3),	(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(MMC1_DAT4),	(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(MMC1_DAT5),	(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(MMC1_DAT6),	(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(MMC1_DAT7),	(IEN  | PTU | EN  | M0)) \
+ /* MMC2 WLAN */\
+	MUX_VAL(CP(MMC2_CLK),	(IEN  | PTD | DIS  | M0)) \
+	MUX_VAL(CP(MMC2_CMD),	(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(MMC2_DAT0),	(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(MMC2_DAT1),	(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(MMC2_DAT2),	(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(MMC2_DAT3),	(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(MMC2_DAT4),	(IEN  | PTU | EN  | M4)) \
+	MUX_VAL(CP(MMC2_DAT5),	(IEN  | PTU | EN  | M4)) \
+	MUX_VAL(CP(MMC2_DAT6),	(IDIS  | PTD | EN  | M4)) \
+	MUX_VAL(CP(MMC2_DAT7),	(IDIS  | PTU | EN  | M4)) \
+ /*Bluetooth*/\
+	MUX_VAL(CP(MCBSP3_DX),	(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(MCBSP3_DR),	(IEN  | PTD | DIS | M0)) \
+ /*LocalBus LAN Reset*/\
+	MUX_VAL(CP(MCBSP3_CLKX), (IEN  | PTD | DIS | M4)) \
+ /*LocalBus LAN IRQ*/\
+	MUX_VAL(CP(MCBSP3_FSX),	(IEN  | PTD | DIS | M4)) \
+	MUX_VAL(CP(UART2_CTS),	(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(UART2_RTS),	(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(UART2_TX),	(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(UART2_RX),	(IEN  | PTD | DIS | M0)) \
+ /*Modem Interface */\
+	MUX_VAL(CP(UART1_TX),	(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(UART1_RTS),	(IDIS | PTD | DIS | M0))  \
+	MUX_VAL(CP(UART1_CTS),	(IEN  | PTU | DIS | M0))  \
+	MUX_VAL(CP(UART1_RX),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(MCBSP4_CLKX), (IEN  | PTD | DIS | M1)) \
+	MUX_VAL(CP(MCBSP4_DR),	(IEN  | PTD | DIS | M1)) \
+	MUX_VAL(CP(MCBSP4_DX),	(IEN  | PTD | DIS | M1)) \
+	MUX_VAL(CP(MCBSP4_FSX),	(IEN  | PTD | DIS | M1)) \
+	MUX_VAL(CP(MCBSP1_CLKR),     (IEN | PTD | DIS | M1)) \
+	MUX_VAL(CP(MCBSP1_FSR),	(IDIS | PTU | EN  | M4)) \
+	MUX_VAL(CP(MCBSP1_DX),	(IEN | PTD | DIS | M1)) \
+	MUX_VAL(CP(MCBSP1_DR),		(IEN | PTD | DIS | M1)) \
+	MUX_VAL(CP(MCBSP_CLKS),	(IEN  | PTU | DIS | M0)) \
+	MUX_VAL(CP(MCBSP1_FSX),	(IEN | PTD | EN | M1)) \
+	MUX_VAL(CP(MCBSP1_CLKX), (IEN | PTU | EN | M4)) \
+ /*Serial Interface*/\
+	MUX_VAL(CP(UART3_CTS_RCTX), (IEN  | PTD | EN  | M0)) \
+	MUX_VAL(CP(UART3_RTS_SD), (IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(UART3_RX_IRRX), (IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(UART3_TX_IRTX), (IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(HSUSB0_CLK),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(HSUSB0_STP),	(IDIS | PTU | EN  | M0)) \
+	MUX_VAL(CP(HSUSB0_DIR),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(HSUSB0_NXT),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(HSUSB0_DATA0), (IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(HSUSB0_DATA1), (IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(HSUSB0_DATA2), (IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(HSUSB0_DATA3), (IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(HSUSB0_DATA4), (IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(HSUSB0_DATA5), (IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(HSUSB0_DATA6), (IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(HSUSB0_DATA7), (IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(I2C1_SCL),	(IEN  | PTU | EN | M0)) \
+	MUX_VAL(CP(I2C1_SDA),	(IEN  | PTU | EN | M0)) \
+	MUX_VAL(CP(I2C2_SCL),	(IEN  | PTU | EN | M0)) \
+	MUX_VAL(CP(I2C2_SDA),	(IEN  | PTU | EN | M0)) \
+	MUX_VAL(CP(I2C3_SCL),	(IEN  | PTU | EN | M0)) \
+	MUX_VAL(CP(I2C3_SDA),	(IEN  | PTU | EN | M0)) \
+	MUX_VAL(CP(I2C4_SCL),	(IEN  | PTU | EN | M0)) \
+	MUX_VAL(CP(I2C4_SDA),	(IEN  | PTU | EN | M0)) \
+	MUX_VAL(CP(HDQ_SIO),	(IEN  | PTU | EN | M0)) \
+	MUX_VAL(CP(MCSPI1_CLK),	(IEN  | PTD | EN | M0)) \
+	MUX_VAL(CP(MCSPI1_SIMO), (IEN | PTD | EN | M0)) \
+	MUX_VAL(CP(MCSPI1_SOMI), (IEN | PTD | EN | M0)) \
+	MUX_VAL(CP(MCSPI1_CS0),	(IEN  | PTD | EN | M0)) \
+	MUX_VAL(CP(MCSPI1_CS1),	(IEN  | PTD | EN | M0)) \
+	MUX_VAL(CP(MCSPI1_CS2),	(IEN  | PTD | EN | M4)) \
+ /* USB EHCI (port 2) */\
+	MUX_VAL(CP(MCSPI1_CS3),	(IEN  | PTU | DIS | M3)) \
+	MUX_VAL(CP(MCSPI2_CLK),	(IEN  | PTU | DIS | M3)) \
+	MUX_VAL(CP(MCSPI2_SIMO), (IEN | PTU | DIS | M3)) \
+	MUX_VAL(CP(MCSPI2_SOMI), (IEN | PTU | DIS | M3)) \
+	MUX_VAL(CP(MCSPI2_CS0),	(IEN  | PTU | DIS | M3)) \
+	MUX_VAL(CP(MCSPI2_CS1),	(IEN  | PTU | DIS | M3)) \
+ /*Control and debug */\
+	MUX_VAL(CP(SYS_32K),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SYS_CLKREQ),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SYS_NIRQ),	(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(SYS_BOOT0),	(IEN  | PTD | DIS | M4)) \
+	MUX_VAL(CP(SYS_BOOT1),	(IEN  | PTD | DIS | M4)) \
+	MUX_VAL(CP(SYS_BOOT2),	(IEN  | PTD | DIS | M4)) \
+	MUX_VAL(CP(SYS_BOOT3),	(IEN  | PTD | DIS | M4)) \
+	MUX_VAL(CP(SYS_BOOT4),	(IEN  | PTD | DIS | M4)) \
+	MUX_VAL(CP(SYS_BOOT5),	(IEN  | PTD | DIS | M4)) \
+	MUX_VAL(CP(SYS_BOOT6),	(IDIS | PTD | DIS | M4))  \
+	/* - VIO_1V8*/\
+	MUX_VAL(CP(SYS_OFF_MODE), (IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SYS_CLKOUT1), (IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SYS_CLKOUT2), (IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(JTAG_nTRST),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(JTAG_TCK),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(JTAG_TMS),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(JTAG_TDI),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(JTAG_EMU0),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(JTAG_EMU1),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(ETK_CLK_ES2), (IEN | PTU | EN  | M4)) \
+	MUX_VAL(CP(ETK_CTL_ES2), (IEN | PTU | EN | M4)) \
+	MUX_VAL(CP(ETK_D0_ES2),	(IEN  | PTU | DIS | M1)) \
+	MUX_VAL(CP(ETK_D1_ES2),	(IEN  | PTU | DIS | M1)) \
+	MUX_VAL(CP(ETK_D2_ES2),	(IEN  | PTU | DIS | M1)) \
+	MUX_VAL(CP(ETK_D3_ES2),	(IEN  | PTU | DIS | M1)) \
+	MUX_VAL(CP(ETK_D4_ES2),	(IEN  | PTU | EN | M4)) \
+	MUX_VAL(CP(ETK_D5_ES2),	(IEN  | PTU | EN | M4)) \
+	MUX_VAL(CP(ETK_D6_ES2),	(IEN  | PTU | EN | M4)) \
+	MUX_VAL(CP(ETK_D7_ES2),	(IEN  | PTU | DIS | M1)) \
+	MUX_VAL(CP(ETK_D8_ES2),	(IEN  | PTU | EN | M4)) \
+	MUX_VAL(CP(ETK_D9_ES2),	(IEN  | PTD | EN | M4)) \
+	MUX_VAL(CP(ETK_D10_ES2), (IDIS | PTU | DIS | M3)) \
+	MUX_VAL(CP(ETK_D11_ES2), (IDIS | PTU | DIS | M3)) \
+	MUX_VAL(CP(ETK_D12_ES2), (IEN  | PTU | DIS | M3)) \
+	MUX_VAL(CP(ETK_D13_ES2), (IEN  | PTU | DIS | M3)) \
+	MUX_VAL(CP(ETK_D14_ES2), (IEN|PTU|DIS|M3)) \
+	MUX_VAL(CP(ETK_D15_ES2), (IEN  | PTU | DIS | M3)) \
+	MUX_VAL(CP(D2D_MCAD1),	(IEN  | PTD | EN  | M0)) \
+	MUX_VAL(CP(D2D_MCAD2),	(IEN  | PTD | EN  | M0)) \
+	MUX_VAL(CP(D2D_MCAD3),	(IEN  | PTD | EN  | M0)) \
+	MUX_VAL(CP(D2D_MCAD4),	(IEN  | PTD | EN  | M0)) \
+	MUX_VAL(CP(D2D_MCAD5),	(IEN  | PTD | EN  | M0)) \
+	MUX_VAL(CP(D2D_MCAD6),	(IEN  | PTD | EN  | M0)) \
+	MUX_VAL(CP(D2D_MCAD7),	(IEN  | PTD | EN  | M0)) \
+	MUX_VAL(CP(D2D_MCAD8),	(IEN  | PTD | EN  | M0)) \
+	MUX_VAL(CP(D2D_MCAD9),	(IEN  | PTD | EN  | M0)) \
+	MUX_VAL(CP(D2D_MCAD10),	(IEN  | PTD | EN  | M0)) \
+	MUX_VAL(CP(D2D_MCAD11),	(IEN  | PTD | EN  | M0)) \
+	MUX_VAL(CP(D2D_MCAD12),	(IEN  | PTD | EN  | M0)) \
+	MUX_VAL(CP(D2D_MCAD13),	(IEN  | PTD | EN  | M0)) \
+	MUX_VAL(CP(D2D_MCAD14),	(IEN  | PTD | EN  | M0)) \
+	MUX_VAL(CP(D2D_MCAD15),	(IEN  | PTD | EN  | M0)) \
+	MUX_VAL(CP(D2D_MCAD16),	(IEN  | PTD | EN  | M0)) \
+	MUX_VAL(CP(D2D_MCAD17),	(IEN  | PTD | EN  | M0)) \
+	MUX_VAL(CP(D2D_MCAD18),	(IEN  | PTD | EN  | M0)) \
+	MUX_VAL(CP(D2D_MCAD19),	(IEN  | PTD | EN  | M0)) \
+	MUX_VAL(CP(D2D_MCAD20),	(IEN  | PTD | EN  | M0)) \
+	MUX_VAL(CP(D2D_MCAD21),	(IEN  | PTD | EN  | M0)) \
+	MUX_VAL(CP(D2D_MCAD22),	(IEN  | PTD | EN  | M0)) \
+	MUX_VAL(CP(D2D_MCAD23),	(IEN  | PTD | EN  | M0)) \
+	MUX_VAL(CP(D2D_MCAD24),	(IEN  | PTD | EN  | M0)) \
+	MUX_VAL(CP(D2D_MCAD25),	(IEN  | PTD | EN  | M0)) \
+	MUX_VAL(CP(D2D_MCAD26),	(IEN  | PTD | EN  | M0)) \
+	MUX_VAL(CP(D2D_MCAD27),	(IEN  | PTD | EN  | M0)) \
+	MUX_VAL(CP(D2D_MCAD28),	(IEN  | PTD | EN  | M0)) \
+	MUX_VAL(CP(D2D_MCAD29),	(IEN  | PTD | EN  | M0)) \
+	MUX_VAL(CP(D2D_MCAD30),	(IEN  | PTD | EN  | M0)) \
+	MUX_VAL(CP(D2D_MCAD31),	(IEN  | PTD | EN  | M0)) \
+	MUX_VAL(CP(D2D_MCAD32),	(IEN  | PTD | EN  | M0)) \
+	MUX_VAL(CP(D2D_MCAD33),	(IEN  | PTD | EN  | M0)) \
+	MUX_VAL(CP(D2D_MCAD34),	(IEN  | PTD | EN  | M0)) \
+	MUX_VAL(CP(D2D_MCAD35),	(IEN  | PTD | EN  | M0)) \
+	MUX_VAL(CP(D2D_MCAD36),	(IEN  | PTD | EN  | M0)) \
+	MUX_VAL(CP(D2D_CLK26MI), (IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(D2D_NRESPWRON), (IEN  | PTD | EN  | M0)) \
+	MUX_VAL(CP(D2D_NRESWARM), (IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(D2D_ARM9NIRQ), (IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(D2D_UMA2P6FIQ), (IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(D2D_SPINT),	(IEN  | PTD | EN  | M0)) \
+	MUX_VAL(CP(D2D_FRINT),	(IEN  | PTD | EN  | M0)) \
+	MUX_VAL(CP(D2D_DMAREQ0), (IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(D2D_DMAREQ1), (IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(D2D_DMAREQ2), (IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(D2D_DMAREQ3), (IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(D2D_N3GTRST), (IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(D2D_N3GTDI),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(D2D_N3GTDO),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(D2D_N3GTMS),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(D2D_N3GTCK),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(D2D_N3GRTCK), (IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(D2D_MSTDBY),	(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(D2D_SWAKEUP), (IEN  | PTD | EN  | M0)) \
+	MUX_VAL(CP(D2D_IDLEREQ), (IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(D2D_IDLEACK), (IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(D2D_MWRITE),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(D2D_SWRITE),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(D2D_MREAD),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(D2D_SREAD),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(D2D_MBUSFLAG), (IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(D2D_SBUSFLAG), (IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_CKE0),	(IDIS | PTU | EN  | M0)) \
+	MUX_VAL(CP(SDRC_CKE1),	(IDIS | PTU | EN  | M0))
+
+#define MUX_OMAP3_HA() \
+	MUX_VAL(CP(CAM_XCLKB),	(IDIS | PTD | DIS | M4)) /* GPIO_111 */
+
+#endif
diff --git a/board/technexion/twister/Makefile b/board/technexion/twister/Makefile
index 641e61e708..2a910211fd 100644
--- a/board/technexion/twister/Makefile
+++ b/board/technexion/twister/Makefile
@@ -6,21 +6,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	:= $(BOARD).o
-
-SRCS	:= $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
+obj-y	:= twister.o
diff --git a/board/technexion/twister/twister.c b/board/technexion/twister/twister.c
index cd91d8fea0..054e7ccded 100644
--- a/board/technexion/twister/twister.c
+++ b/board/technexion/twister/twister.c
@@ -51,9 +51,10 @@ static struct omap_usbhs_board_data usbhs_bdata = {
 	.port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED,
 };
 
-int ehci_hcd_init(int index, struct ehci_hccr **hccr, struct ehci_hcor **hcor)
+int ehci_hcd_init(int index, enum usb_init_type init,
+		struct ehci_hccr **hccr, struct ehci_hcor **hcor)
 {
-	return omap_ehci_hcd_init(&usbhs_bdata, hccr, hcor);
+	return omap_ehci_hcd_init(index, &usbhs_bdata, hccr, hcor);
 }
 
 int ehci_hcd_stop(int index)
diff --git a/board/teejet/mt_ventoux/Makefile b/board/teejet/mt_ventoux/Makefile
index 641e61e708..66f56fd219 100644
--- a/board/teejet/mt_ventoux/Makefile
+++ b/board/teejet/mt_ventoux/Makefile
@@ -6,21 +6,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	:= $(BOARD).o
-
-SRCS	:= $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
+obj-y	:= mt_ventoux.o
diff --git a/board/teejet/mt_ventoux/mt_ventoux.c b/board/teejet/mt_ventoux/mt_ventoux.c
index b4e01d1562..c32d554ea4 100644
--- a/board/teejet/mt_ventoux/mt_ventoux.c
+++ b/board/teejet/mt_ventoux/mt_ventoux.c
@@ -102,9 +102,10 @@ static struct omap_usbhs_board_data usbhs_bdata = {
 	.port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED,
 };
 
-int ehci_hcd_init(int index, struct ehci_hccr **hccr, struct ehci_hcor **hcor)
+int ehci_hcd_init(int index, enum usb_init_type init,
+		struct ehci_hccr **hccr, struct ehci_hcor **hcor)
 {
-	return omap_ehci_hcd_init(&usbhs_bdata, hccr, hcor);
+	return omap_ehci_hcd_init(index, &usbhs_bdata, hccr, hcor);
 }
 
 int ehci_hcd_stop(int index)
diff --git a/board/ti/am335x/Makefile b/board/ti/am335x/Makefile
index 3dbeedab1a..c8b4f9a280 100644
--- a/board/ti/am335x/Makefile
+++ b/board/ti/am335x/Makefile
@@ -6,33 +6,8 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
 ifeq ($(CONFIG_SPL_BUILD)$(CONFIG_NOR_BOOT),y)
-COBJS	:= mux.o
+obj-y	:= mux.o
 endif
 
-COBJS	+= board.o
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
-	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
-
-clean:
-	rm -f $(SOBJS) $(OBJS)
-
-distclean:	clean
-	rm -f $(LIB) core *.bak $(obj).depend
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	+= board.o
diff --git a/board/ti/am335x/README b/board/ti/am335x/README
index 2a30ab8981..947305b58d 100644
--- a/board/ti/am335x/README
+++ b/board/ti/am335x/README
@@ -46,23 +46,42 @@ NAND
 The AM335x GP EVM ships with a 256MiB NAND available in most profiles.  In
 this example to program the NAND we assume that an SD card has been
 inserted with the files to write in the first SD slot and that mtdparts
-have been configured correctly for the board.  As a time saving measure we
-load MLO into memory in one location, copy it into the three locatations
-that the ROM checks for additional valid copies, then load U-Boot into
-memory.  We then write that whole section of memory to NAND.
-
-U-Boot # mmc rescan
-U-Boot # env default -f -a
-U-Boot # nand erase.chip
-U-Boot # saveenv
-U-Boot # load mmc 0 81000000 MLO
-U-Boot # cp.b 81000000 81020000 20000
-U-Boot # cp.b 81000000 81040000 20000
-U-Boot # cp.b 81000000 81060000 20000
-U-Boot # load mmc 0 81080000 u-boot.img
-U-Boot # nand write 81000000 0 260000
-U-Boot # load mmc 0 ${loadaddr} uImage
-U-Boot # nand write ${loadaddr} kernel 500000
+have been configured correctly for the board. All images are first loaded
+into memory, then written to NAND.
+
+Step-1: Building u-boot for NAND boot
+	Set following CONFIGxx options for NAND device.
+	CONFIG_SYS_NAND_PAGE_SIZE	number of main bytes in NAND page
+	CONFIG_SYS_NAND_OOBSIZE		number of OOB bytes in NAND page
+	CONFIG_SYS_NAND_BLOCK_SIZE	number of bytes in NAND erase-block
+	CONFIG_SYS_NAND_ECCPOS		ECC map for NAND page
+	CONFIG_NAND_OMAP_ECCSCHEME	(refer doc/README.nand)
+
+Step-2: Flashing NAND via MMC/SD
+	# select BOOTSEL to MMC/SD boot and boot from MMC/SD card
+	U-Boot # mmc rescan
+	# erase flash
+	U-Boot # nand erase.chip
+	U-Boot # env default -f -a
+	U-Boot # saveenv
+	# flash MLO. Redundant copies of MLO are kept for failsafe
+	U-Boot # load mmc 0 0x82000000 MLO
+	U-Boot # nand write 0x82000000 0x00000 0x20000
+	U-Boot # nand write 0x82000000 0x20000 0x20000
+	U-Boot # nand write 0x82000000 0x40000 0x20000
+	U-Boot # nand write 0x82000000 0x60000 0x20000
+	# flash u-boot.img
+	U-Boot # load mmc 0 0x82000000 u-boot.img
+	U-Boot # nand write 0x82000000 0x80000 0x60000
+	# flash kernel image
+	U-Boot # load mmc 0 0x82000000 uImage
+	U-Boot # nand write 0x82000000 ${nandsrcaddr} ${nandimgsize}
+	# flash filesystem image
+	U-Boot # load mmc 0 0x82000000 filesystem.img
+	U-Boot # nand write 0x82000000 ${loadaddress} 0x300000
+
+Step-3: Set BOOTSEL pin to select NAND boot, and POR the device.
+	The device should boot from images flashed on NAND device.
 
 NOR
 ===
diff --git a/board/ti/am335x/board.c b/board/ti/am335x/board.c
index c2fc5a613b..554398f346 100644
--- a/board/ti/am335x/board.c
+++ b/board/ti/am335x/board.c
@@ -28,6 +28,8 @@
 #include <cpsw.h>
 #include <power/tps65217.h>
 #include <power/tps65910.h>
+#include <environment.h>
+#include <watchdog.h>
 #include "board.h"
 
 DECLARE_GLOBAL_DATA_PTR;
@@ -105,21 +107,16 @@ static const struct ddr_data ddr2_data = {
 			  (MT47H128M16RT25E_PHY_WR_DATA<<20) |
 			  (MT47H128M16RT25E_PHY_WR_DATA<<10) |
 			  (MT47H128M16RT25E_PHY_WR_DATA<<0)),
-	.datauserank0delay = MT47H128M16RT25E_PHY_RANK0_DELAY,
-	.datadldiff0 = PHY_DLL_LOCK_DIFF,
 };
 
 static const struct cmd_control ddr2_cmd_ctrl_data = {
 	.cmd0csratio = MT47H128M16RT25E_RATIO,
-	.cmd0dldiff = MT47H128M16RT25E_DLL_LOCK_DIFF,
 	.cmd0iclkout = MT47H128M16RT25E_INVERT_CLKOUT,
 
 	.cmd1csratio = MT47H128M16RT25E_RATIO,
-	.cmd1dldiff = MT47H128M16RT25E_DLL_LOCK_DIFF,
 	.cmd1iclkout = MT47H128M16RT25E_INVERT_CLKOUT,
 
 	.cmd2csratio = MT47H128M16RT25E_RATIO,
-	.cmd2dldiff = MT47H128M16RT25E_DLL_LOCK_DIFF,
 	.cmd2iclkout = MT47H128M16RT25E_INVERT_CLKOUT,
 };
 
@@ -137,7 +134,6 @@ static const struct ddr_data ddr3_data = {
 	.datawdsratio0 = MT41J128MJT125_WR_DQS,
 	.datafwsratio0 = MT41J128MJT125_PHY_FIFO_WE,
 	.datawrsratio0 = MT41J128MJT125_PHY_WR_DATA,
-	.datadldiff0 = PHY_DLL_LOCK_DIFF,
 };
 
 static const struct ddr_data ddr3_beagleblack_data = {
@@ -145,7 +141,6 @@ static const struct ddr_data ddr3_beagleblack_data = {
 	.datawdsratio0 = MT41K256M16HA125E_WR_DQS,
 	.datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE,
 	.datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA,
-	.datadldiff0 = PHY_DLL_LOCK_DIFF,
 };
 
 static const struct ddr_data ddr3_evm_data = {
@@ -153,48 +148,38 @@ static const struct ddr_data ddr3_evm_data = {
 	.datawdsratio0 = MT41J512M8RH125_WR_DQS,
 	.datafwsratio0 = MT41J512M8RH125_PHY_FIFO_WE,
 	.datawrsratio0 = MT41J512M8RH125_PHY_WR_DATA,
-	.datadldiff0 = PHY_DLL_LOCK_DIFF,
 };
 
 static const struct cmd_control ddr3_cmd_ctrl_data = {
 	.cmd0csratio = MT41J128MJT125_RATIO,
-	.cmd0dldiff = MT41J128MJT125_DLL_LOCK_DIFF,
 	.cmd0iclkout = MT41J128MJT125_INVERT_CLKOUT,
 
 	.cmd1csratio = MT41J128MJT125_RATIO,
-	.cmd1dldiff = MT41J128MJT125_DLL_LOCK_DIFF,
 	.cmd1iclkout = MT41J128MJT125_INVERT_CLKOUT,
 
 	.cmd2csratio = MT41J128MJT125_RATIO,
-	.cmd2dldiff = MT41J128MJT125_DLL_LOCK_DIFF,
 	.cmd2iclkout = MT41J128MJT125_INVERT_CLKOUT,
 };
 
 static const struct cmd_control ddr3_beagleblack_cmd_ctrl_data = {
 	.cmd0csratio = MT41K256M16HA125E_RATIO,
-	.cmd0dldiff = MT41K256M16HA125E_DLL_LOCK_DIFF,
 	.cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
 
 	.cmd1csratio = MT41K256M16HA125E_RATIO,
-	.cmd1dldiff = MT41K256M16HA125E_DLL_LOCK_DIFF,
 	.cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
 
 	.cmd2csratio = MT41K256M16HA125E_RATIO,
-	.cmd2dldiff = MT41K256M16HA125E_DLL_LOCK_DIFF,
 	.cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
 };
 
 static const struct cmd_control ddr3_evm_cmd_ctrl_data = {
 	.cmd0csratio = MT41J512M8RH125_RATIO,
-	.cmd0dldiff = MT41J512M8RH125_DLL_LOCK_DIFF,
 	.cmd0iclkout = MT41J512M8RH125_INVERT_CLKOUT,
 
 	.cmd1csratio = MT41J512M8RH125_RATIO,
-	.cmd1dldiff = MT41J512M8RH125_DLL_LOCK_DIFF,
 	.cmd1iclkout = MT41J512M8RH125_INVERT_CLKOUT,
 
 	.cmd2csratio = MT41J512M8RH125_RATIO,
-	.cmd2dldiff = MT41J512M8RH125_DLL_LOCK_DIFF,
 	.cmd2iclkout = MT41J512M8RH125_INVERT_CLKOUT,
 };
 
@@ -395,7 +380,7 @@ const struct dpll_params *get_dpll_ddr_params(void)
 	struct am335x_baseboard_id header;
 
 	enable_i2c0_pin_mux();
-	i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
+	i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE);
 	if (read_eeprom(&header) < 0)
 		puts("Could not get board ID.\n");
 
@@ -441,6 +426,38 @@ void set_mux_conf_regs(void)
 	enable_board_pin_mux(&header);
 }
 
+const struct ctrl_ioregs ioregs_evmsk = {
+	.cm0ioctl		= MT41J128MJT125_IOCTRL_VALUE,
+	.cm1ioctl		= MT41J128MJT125_IOCTRL_VALUE,
+	.cm2ioctl		= MT41J128MJT125_IOCTRL_VALUE,
+	.dt0ioctl		= MT41J128MJT125_IOCTRL_VALUE,
+	.dt1ioctl		= MT41J128MJT125_IOCTRL_VALUE,
+};
+
+const struct ctrl_ioregs ioregs_bonelt = {
+	.cm0ioctl		= MT41K256M16HA125E_IOCTRL_VALUE,
+	.cm1ioctl		= MT41K256M16HA125E_IOCTRL_VALUE,
+	.cm2ioctl		= MT41K256M16HA125E_IOCTRL_VALUE,
+	.dt0ioctl		= MT41K256M16HA125E_IOCTRL_VALUE,
+	.dt1ioctl		= MT41K256M16HA125E_IOCTRL_VALUE,
+};
+
+const struct ctrl_ioregs ioregs_evm15 = {
+	.cm0ioctl		= MT41J512M8RH125_IOCTRL_VALUE,
+	.cm1ioctl		= MT41J512M8RH125_IOCTRL_VALUE,
+	.cm2ioctl		= MT41J512M8RH125_IOCTRL_VALUE,
+	.dt0ioctl		= MT41J512M8RH125_IOCTRL_VALUE,
+	.dt1ioctl		= MT41J512M8RH125_IOCTRL_VALUE,
+};
+
+const struct ctrl_ioregs ioregs = {
+	.cm0ioctl		= MT47H128M16RT25E_IOCTRL_VALUE,
+	.cm1ioctl		= MT47H128M16RT25E_IOCTRL_VALUE,
+	.cm2ioctl		= MT47H128M16RT25E_IOCTRL_VALUE,
+	.dt0ioctl		= MT47H128M16RT25E_IOCTRL_VALUE,
+	.dt1ioctl		= MT47H128M16RT25E_IOCTRL_VALUE,
+};
+
 void sdram_init(void)
 {
 	__maybe_unused struct am335x_baseboard_id header;
@@ -458,18 +475,18 @@ void sdram_init(void)
 	}
 
 	if (board_is_evm_sk(&header))
-		config_ddr(303, MT41J128MJT125_IOCTRL_VALUE, &ddr3_data,
+		config_ddr(303, &ioregs_evmsk, &ddr3_data,
 			   &ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0);
 	else if (board_is_bone_lt(&header))
-		config_ddr(400, MT41K256M16HA125E_IOCTRL_VALUE,
+		config_ddr(400, &ioregs_bonelt,
 			   &ddr3_beagleblack_data,
 			   &ddr3_beagleblack_cmd_ctrl_data,
 			   &ddr3_beagleblack_emif_reg_data, 0);
 	else if (board_is_evm_15_or_later(&header))
-		config_ddr(303, MT41J512M8RH125_IOCTRL_VALUE, &ddr3_evm_data,
+		config_ddr(303, &ioregs_evm15, &ddr3_evm_data,
 			   &ddr3_evm_cmd_ctrl_data, &ddr3_evm_emif_reg_data, 0);
 	else
-		config_ddr(266, MT47H128M16RT25E_IOCTRL_VALUE, &ddr2_data,
+		config_ddr(266, &ioregs, &ddr2_data,
 			   &ddr2_cmd_ctrl_data, &ddr2_emif_reg_data, 0);
 }
 #endif
@@ -479,22 +496,14 @@ void sdram_init(void)
  */
 int board_init(void)
 {
-#ifdef CONFIG_NOR
-	const u32 gpmc_nor[GPMC_MAX_REG] = { STNOR_GPMC_CONFIG1,
-		STNOR_GPMC_CONFIG2, STNOR_GPMC_CONFIG3, STNOR_GPMC_CONFIG4,
-		STNOR_GPMC_CONFIG5, STNOR_GPMC_CONFIG6, STNOR_GPMC_CONFIG7 };
+#if defined(CONFIG_HW_WATCHDOG)
+	hw_watchdog_init();
 #endif
 
 	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
-
+#if defined(CONFIG_NOR) || defined(CONFIG_NAND)
 	gpmc_init();
-
-#ifdef CONFIG_NOR
-	/* Reconfigure CS0 for NOR instead of NAND. */
-	enable_gpmc_cs_config(gpmc_nor, &gpmc_cfg->cs[0],
-			      CONFIG_SYS_FLASH_BASE, GPMC_SIZE_16M);
 #endif
-
 	return 0;
 }
 
@@ -535,12 +544,12 @@ static struct cpsw_slave_data cpsw_slaves[] = {
 	{
 		.slave_reg_ofs	= 0x208,
 		.sliver_reg_ofs	= 0xd80,
-		.phy_id		= 0,
+		.phy_addr	= 0,
 	},
 	{
 		.slave_reg_ofs	= 0x308,
 		.sliver_reg_ofs	= 0xdc0,
-		.phy_id		= 1,
+		.phy_addr	= 1,
 	},
 };
 
@@ -564,8 +573,22 @@ static struct cpsw_platform_data cpsw_data = {
 };
 #endif
 
-#if defined(CONFIG_DRIVER_TI_CPSW) || \
-	(defined(CONFIG_USB_ETHER) && defined(CONFIG_MUSB_GADGET))
+/*
+ * This function will:
+ * Read the eFuse for MAC addresses, and set ethaddr/eth1addr/usbnet_devaddr
+ * in the environment
+ * Perform fixups to the PHY present on certain boards.  We only need this
+ * function in:
+ * - SPL with either CPSW or USB ethernet support
+ * - Full U-Boot, with either CPSW or USB ethernet
+ * Build in only these cases to avoid warnings about unused variables
+ * when we build an SPL that has neither option but full U-Boot will.
+ */
+#if ((defined(CONFIG_SPL_ETH_SUPPORT) || defined(CONFIG_SPL_USBETH_SUPPORT)) \
+		&& defined(CONFIG_SPL_BUILD)) || \
+	((defined(CONFIG_DRIVER_TI_CPSW) || \
+	  defined(CONFIG_USB_ETHER) && defined(CONFIG_MUSB_GADGET)) && \
+	 !defined(CONFIG_SPL_BUILD))
 int board_eth_init(bd_t *bis)
 {
 	int rv, n = 0;
@@ -593,6 +616,21 @@ int board_eth_init(bd_t *bis)
 	}
 
 #ifdef CONFIG_DRIVER_TI_CPSW
+
+	mac_lo = readl(&cdev->macid1l);
+	mac_hi = readl(&cdev->macid1h);
+	mac_addr[0] = mac_hi & 0xFF;
+	mac_addr[1] = (mac_hi & 0xFF00) >> 8;
+	mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
+	mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
+	mac_addr[4] = mac_lo & 0xFF;
+	mac_addr[5] = (mac_lo & 0xFF00) >> 8;
+
+	if (!getenv("eth1addr")) {
+		if (is_valid_ether_addr(mac_addr))
+			eth_setenv_enetaddr("eth1addr", mac_addr);
+	}
+
 	if (read_eeprom(&header) < 0)
 		puts("Could not get board ID.\n");
 
diff --git a/board/ti/am335x/u-boot.lds b/board/ti/am335x/u-boot.lds
index a173f620ef..a9e3d34df9 100644
--- a/board/ti/am335x/u-boot.lds
+++ b/board/ti/am335x/u-boot.lds
@@ -35,7 +35,7 @@ SECTIONS
 	{
 		*(.__image_copy_start)
 		CPUDIR/start.o (.text*)
-		board/ti/am335x/libam335x.o (.text*)
+		board/ti/am335x/built-in.o (.text*)
 		*(.text*)
 	}
 
@@ -77,7 +77,12 @@ SECTIONS
 		*(.__rel_dyn_end)
 	}
 
-	_end = .;
+	.end :
+	{
+		*(.__end)
+	}
+
+	_image_binary_end = .;
 
 	/*
 	 * Deprecated: this MMU section is used by pxa at present but
@@ -108,10 +113,14 @@ SECTIONS
 		KEEP(*(.__bss_end));
 	}
 
-	/DISCARD/ : { *(.dynsym) }
-	/DISCARD/ : { *(.dynstr*) }
-	/DISCARD/ : { *(.dynamic*) }
-	/DISCARD/ : { *(.plt*) }
-	/DISCARD/ : { *(.interp*) }
-	/DISCARD/ : { *(.gnu*) }
+	.dynsym _image_binary_end : { *(.dynsym) }
+	.dynbss : { *(.dynbss) }
+	.dynstr : { *(.dynstr*) }
+	.dynamic : { *(.dynamic*) }
+	.hash : { *(.hash*) }
+	.gnu.hash : { *(.gnu.hash) }
+	.plt : { *(.plt*) }
+	.interp : { *(.interp*) }
+	.gnu : { *(.gnu*) }
+	.ARM.exidx : { *(.ARM.exidx*) }
 }
diff --git a/board/ti/am3517crane/Makefile b/board/ti/am3517crane/Makefile
index d9ab72a620..9da795de95 100644
--- a/board/ti/am3517crane/Makefile
+++ b/board/ti/am3517crane/Makefile
@@ -8,21 +8,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	:= am3517crane.o
-
-SRCS	:= $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
+obj-y	:= am3517crane.o
diff --git a/board/ti/am3517crane/am3517crane.c b/board/ti/am3517crane/am3517crane.c
index 5eb97ff378..a649697257 100644
--- a/board/ti/am3517crane/am3517crane.c
+++ b/board/ti/am3517crane/am3517crane.c
@@ -43,8 +43,8 @@ int board_init(void)
  */
 int misc_init_r(void)
 {
-#ifdef CONFIG_DRIVER_OMAP34XX_I2C
-	i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
+#ifdef CONFIG_SYS_I2C_OMAP34XX
+	i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE);
 #endif
 
 	dieid_num_r();
diff --git a/board/ti/am43xx/Makefile b/board/ti/am43xx/Makefile
index 4a1bb7c47f..cb5fe88901 100644
--- a/board/ti/am43xx/Makefile
+++ b/board/ti/am43xx/Makefile
@@ -6,33 +6,8 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
 ifdef CONFIG_SPL_BUILD
-COBJS	:= mux.o
+obj-y	:= mux.o
 endif
 
-COBJS	+= board.o
-SRCS	:= $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
-	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
-
-clean:
-	rm -f $(SOBJS) $(OBJS)
-
-distclean:	clean
-	rm -f $(LIB) core *.bak $(obj).depend
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	+= board.o
diff --git a/board/ti/am43xx/board.c b/board/ti/am43xx/board.c
index 51b257683d..d7449770a3 100644
--- a/board/ti/am43xx/board.c
+++ b/board/ti/am43xx/board.c
@@ -9,22 +9,330 @@
  */
 
 #include <common.h>
+#include <i2c.h>
+#include <asm/errno.h>
 #include <spl.h>
 #include <asm/arch/clock.h>
 #include <asm/arch/sys_proto.h>
 #include <asm/arch/mux.h>
+#include <asm/arch/ddr_defs.h>
+#include <asm/arch/gpio.h>
+#include <asm/emif.h>
 #include "board.h"
+#include <miiphy.h>
+#include <cpsw.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
+static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
+
+/*
+ * Read header information from EEPROM into global structure.
+ */
+static int read_eeprom(struct am43xx_board_id *header)
+{
+	/* Check if baseboard eeprom is available */
+	if (i2c_probe(CONFIG_SYS_I2C_EEPROM_ADDR)) {
+		printf("Could not probe the EEPROM at 0x%x\n",
+		       CONFIG_SYS_I2C_EEPROM_ADDR);
+		return -ENODEV;
+	}
+
+	/* read the eeprom using i2c */
+	if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 2, (uchar *)header,
+		     sizeof(struct am43xx_board_id))) {
+		printf("Could not read the EEPROM\n");
+		return -EIO;
+	}
+
+	if (header->magic != 0xEE3355AA) {
+		/*
+		 * read the eeprom using i2c again,
+		 * but use only a 1 byte address
+		 */
+		if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 1, (uchar *)header,
+			     sizeof(struct am43xx_board_id))) {
+			printf("Could not read the EEPROM at 0x%x\n",
+			       CONFIG_SYS_I2C_EEPROM_ADDR);
+			return -EIO;
+		}
+
+		if (header->magic != 0xEE3355AA) {
+			printf("Incorrect magic number (0x%x) in EEPROM\n",
+			       header->magic);
+			return -EINVAL;
+		}
+	}
+
+	strncpy(am43xx_board_name, (char *)header->name, sizeof(header->name));
+	am43xx_board_name[sizeof(header->name)] = 0;
+
+	return 0;
+}
+
 #ifdef CONFIG_SPL_BUILD
 
-const struct dpll_params dpll_ddr = {
-		-1, -1, -1, -1, -1, -1, -1};
+#define NUM_OPPS	6
+
+const struct dpll_params dpll_mpu[NUM_CRYSTAL_FREQ][NUM_OPPS] = {
+	{	/* 19.2 MHz */
+		{-1, -1, -1, -1, -1, -1, -1},	/* OPP 50 */
+		{-1, -1, -1, -1, -1, -1, -1},	/* OPP RESERVED	*/
+		{-1, -1, -1, -1, -1, -1, -1},	/* OPP 100 */
+		{-1, -1, -1, -1, -1, -1, -1},	/* OPP 120 */
+		{-1, -1, -1, -1, -1, -1, -1},	/* OPP TB */
+		{-1, -1, -1, -1, -1, -1, -1}	/* OPP NT */
+	},
+	{	/* 24 MHz */
+		{300, 23, 1, -1, -1, -1, -1},	/* OPP 50 */
+		{-1, -1, -1, -1, -1, -1, -1},	/* OPP RESERVED	*/
+		{600, 23, 1, -1, -1, -1, -1},	/* OPP 100 */
+		{720, 23, 1, -1, -1, -1, -1},	/* OPP 120 */
+		{800, 23, 1, -1, -1, -1, -1},	/* OPP TB */
+		{1000, 23, 1, -1, -1, -1, -1}	/* OPP NT */
+	},
+	{	/* 25 MHz */
+		{300, 24, 1, -1, -1, -1, -1},	/* OPP 50 */
+		{-1, -1, -1, -1, -1, -1, -1},	/* OPP RESERVED	*/
+		{600, 24, 1, -1, -1, -1, -1},	/* OPP 100 */
+		{720, 24, 1, -1, -1, -1, -1},	/* OPP 120 */
+		{800, 24, 1, -1, -1, -1, -1},	/* OPP TB */
+		{1000, 24, 1, -1, -1, -1, -1}	/* OPP NT */
+	},
+	{	/* 26 MHz */
+		{300, 25, 1, -1, -1, -1, -1},	/* OPP 50 */
+		{-1, -1, -1, -1, -1, -1, -1},	/* OPP RESERVED	*/
+		{600, 25, 1, -1, -1, -1, -1},	/* OPP 100 */
+		{720, 25, 1, -1, -1, -1, -1},	/* OPP 120 */
+		{800, 25, 1, -1, -1, -1, -1},	/* OPP TB */
+		{1000, 25, 1, -1, -1, -1, -1}	/* OPP NT */
+	},
+};
+
+const struct dpll_params dpll_core[NUM_CRYSTAL_FREQ] = {
+		{-1, -1, -1, -1, -1, -1, -1},	/* 19.2 MHz */
+		{1000, 23, -1, -1, 10, 8, 4},	/* 24 MHz */
+		{1000, 24, -1, -1, 10, 8, 4},	/* 25 MHz */
+		{1000, 25, -1, -1, 10, 8, 4}	/* 26 MHz */
+};
+
+const struct dpll_params dpll_per[NUM_CRYSTAL_FREQ] = {
+		{-1, -1, -1, -1, -1, -1, -1},	/* 19.2 MHz */
+		{960, 23, 5, -1, -1, -1, -1},	/* 24 MHz */
+		{960, 24, 5, -1, -1, -1, -1},	/* 25 MHz */
+		{960, 25, 5, -1, -1, -1, -1}	/* 26 MHz */
+};
+
+const struct dpll_params epos_evm_dpll_ddr = {
+		266, 24, 1, -1, 1, -1, -1};
+
+const struct dpll_params gp_evm_dpll_ddr = {
+		400, 23, 1, -1, 1, -1, -1};
+
+const struct ctrl_ioregs ioregs_lpddr2 = {
+	.cm0ioctl		= LPDDR2_ADDRCTRL_IOCTRL_VALUE,
+	.cm1ioctl		= LPDDR2_ADDRCTRL_WD0_IOCTRL_VALUE,
+	.cm2ioctl		= LPDDR2_ADDRCTRL_WD1_IOCTRL_VALUE,
+	.dt0ioctl		= LPDDR2_DATA0_IOCTRL_VALUE,
+	.dt1ioctl		= LPDDR2_DATA0_IOCTRL_VALUE,
+	.dt2ioctrl		= LPDDR2_DATA0_IOCTRL_VALUE,
+	.dt3ioctrl		= LPDDR2_DATA0_IOCTRL_VALUE,
+	.emif_sdram_config_ext	= 0x1,
+};
+
+const struct emif_regs emif_regs_lpddr2 = {
+	.sdram_config			= 0x808012BA,
+	.ref_ctrl			= 0x0000040D,
+	.sdram_tim1			= 0xEA86B411,
+	.sdram_tim2			= 0x103A094A,
+	.sdram_tim3			= 0x0F6BA37F,
+	.read_idle_ctrl			= 0x00050000,
+	.zq_config			= 0x50074BE4,
+	.temp_alert_config		= 0x0,
+	.emif_rd_wr_lvl_rmp_win		= 0x0,
+	.emif_rd_wr_lvl_rmp_ctl		= 0x0,
+	.emif_rd_wr_lvl_ctl		= 0x0,
+	.emif_ddr_phy_ctlr_1		= 0x0E084006,
+	.emif_rd_wr_exec_thresh		= 0x00000405,
+	.emif_ddr_ext_phy_ctrl_1	= 0x04010040,
+	.emif_ddr_ext_phy_ctrl_2	= 0x00500050,
+	.emif_ddr_ext_phy_ctrl_3	= 0x00500050,
+	.emif_ddr_ext_phy_ctrl_4	= 0x00500050,
+	.emif_ddr_ext_phy_ctrl_5	= 0x00500050
+};
+
+const u32 ext_phy_ctrl_const_base_lpddr2[] = {
+	0x00500050,
+	0x00350035,
+	0x00350035,
+	0x00350035,
+	0x00350035,
+	0x00350035,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x40001000,
+	0x08102040
+};
+
+const struct ctrl_ioregs ioregs_ddr3 = {
+	.cm0ioctl		= DDR3_ADDRCTRL_IOCTRL_VALUE,
+	.cm1ioctl		= DDR3_ADDRCTRL_WD0_IOCTRL_VALUE,
+	.cm2ioctl		= DDR3_ADDRCTRL_WD1_IOCTRL_VALUE,
+	.dt0ioctl		= DDR3_DATA0_IOCTRL_VALUE,
+	.dt1ioctl		= DDR3_DATA0_IOCTRL_VALUE,
+	.dt2ioctrl		= DDR3_DATA0_IOCTRL_VALUE,
+	.dt3ioctrl		= DDR3_DATA0_IOCTRL_VALUE,
+	.emif_sdram_config_ext	= 0x0143,
+};
+
+const struct emif_regs ddr3_emif_regs_400Mhz = {
+	.sdram_config			= 0x638413B2,
+	.ref_ctrl			= 0x00000C30,
+	.sdram_tim1			= 0xEAAAD4DB,
+	.sdram_tim2			= 0x266B7FDA,
+	.sdram_tim3			= 0x107F8678,
+	.read_idle_ctrl			= 0x00050000,
+	.zq_config			= 0x50074BE4,
+	.temp_alert_config		= 0x0,
+	.emif_ddr_phy_ctlr_1		= 0x0E004008,
+	.emif_ddr_ext_phy_ctrl_1	= 0x08020080,
+	.emif_ddr_ext_phy_ctrl_2	= 0x00400040,
+	.emif_ddr_ext_phy_ctrl_3	= 0x00400040,
+	.emif_ddr_ext_phy_ctrl_4	= 0x00400040,
+	.emif_ddr_ext_phy_ctrl_5	= 0x00400040,
+	.emif_rd_wr_lvl_rmp_win		= 0x0,
+	.emif_rd_wr_lvl_rmp_ctl		= 0x0,
+	.emif_rd_wr_lvl_ctl		= 0x0,
+	.emif_rd_wr_exec_thresh		= 0x00000405
+};
+
+const u32 ext_phy_ctrl_const_base_ddr3[] = {
+	0x00400040,
+	0x00350035,
+	0x00350035,
+	0x00350035,
+	0x00350035,
+	0x00350035,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00340034,
+	0x00340034,
+	0x00340034,
+	0x00340034,
+	0x00340034,
+	0x0,
+	0x0,
+	0x40000000,
+	0x08102040
+};
+
+void emif_get_ext_phy_ctrl_const_regs(const u32 **regs, u32 *size)
+{
+	if (board_is_eposevm()) {
+		*regs = ext_phy_ctrl_const_base_lpddr2;
+		*size = ARRAY_SIZE(ext_phy_ctrl_const_base_lpddr2);
+	} else if (board_is_gpevm()) {
+		*regs = ext_phy_ctrl_const_base_ddr3;
+		*size = ARRAY_SIZE(ext_phy_ctrl_const_base_ddr3);
+	}
+
+	return;
+}
 
 const struct dpll_params *get_dpll_ddr_params(void)
 {
-	return &dpll_ddr;
+	struct am43xx_board_id header;
+
+	enable_i2c0_pin_mux();
+	i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE);
+	if (read_eeprom(&header) < 0)
+		puts("Could not get board ID.\n");
+
+	if (board_is_eposevm())
+		return &epos_evm_dpll_ddr;
+	else if (board_is_gpevm())
+		return &gp_evm_dpll_ddr;
+
+	puts(" Board not supported\n");
+	return NULL;
+}
+
+/*
+ * get_sys_clk_index : returns the index of the sys_clk read from
+ *			ctrl status register. This value is either
+ *			read from efuse or sysboot pins.
+ */
+static u32 get_sys_clk_index(void)
+{
+	struct ctrl_stat *ctrl = (struct ctrl_stat *)CTRL_BASE;
+	u32 ind = readl(&ctrl->statusreg), src;
+
+	src = (ind & CTRL_CRYSTAL_FREQ_SRC_MASK) >> CTRL_CRYSTAL_FREQ_SRC_SHIFT;
+	if (src == CTRL_CRYSTAL_FREQ_SRC_EFUSE) /* Value read from EFUSE */
+		return ((ind & CTRL_CRYSTAL_FREQ_SELECTION_MASK) >>
+			CTRL_CRYSTAL_FREQ_SELECTION_SHIFT);
+	else /* Value read from SYS BOOT pins */
+		return ((ind & CTRL_SYSBOOT_15_14_MASK) >>
+			CTRL_SYSBOOT_15_14_SHIFT);
+}
+
+/*
+ * get_opp_offset:
+ * Returns the index for safest OPP of the device to boot.
+ * max_off:	Index of the MAX OPP in DEV ATTRIBUTE register.
+ * min_off:	Index of the MIN OPP in DEV ATTRIBUTE register.
+ * This data is read from dev_attribute register which is e-fused.
+ * A'1' in bit indicates OPP disabled and not available, a '0' indicates
+ * OPP available. Lowest OPP starts with min_off. So returning the
+ * bit with rightmost '0'.
+ */
+static int get_opp_offset(int max_off, int min_off)
+{
+	struct ctrl_stat *ctrl = (struct ctrl_stat *)CTRL_BASE;
+	int opp = readl(&ctrl->dev_attr), offset, i;
+
+	for (i = max_off; i >= min_off; i--) {
+		offset = opp & (1 << i);
+		if (!offset)
+			return i;
+	}
+
+	return min_off;
+}
+
+const struct dpll_params *get_dpll_mpu_params(void)
+{
+	int opp = get_opp_offset(DEV_ATTR_MAX_OFFSET, DEV_ATTR_MIN_OFFSET);
+	u32 ind = get_sys_clk_index();
+
+	return &dpll_mpu[ind][opp];
+}
+
+const struct dpll_params *get_dpll_core_params(void)
+{
+	int ind = get_sys_clk_index();
+
+	return &dpll_core[ind];
+}
+
+const struct dpll_params *get_dpll_per_params(void)
+{
+	int ind = get_sys_clk_index();
+
+	return &dpll_per[ind];
 }
 
 void set_uart_mux_conf(void)
@@ -37,14 +345,41 @@ void set_mux_conf_regs(void)
 	enable_board_pin_mux();
 }
 
+static void enable_vtt_regulator(void)
+{
+	u32 temp;
+
+	/* enable module */
+	writel(GPIO_CTRL_ENABLEMODULE, AM33XX_GPIO5_BASE + OMAP_GPIO_CTRL);
+
+	/* enable output for GPIO5_7 */
+	writel(GPIO_SETDATAOUT(7),
+	       AM33XX_GPIO5_BASE + OMAP_GPIO_SETDATAOUT);
+	temp = readl(AM33XX_GPIO5_BASE + OMAP_GPIO_OE);
+	temp = temp & ~(GPIO_OE_ENABLE(7));
+	writel(temp, AM33XX_GPIO5_BASE + OMAP_GPIO_OE);
+}
+
 void sdram_init(void)
 {
+	/*
+	 * EPOS EVM has 1GB LPDDR2 connected to EMIF.
+	 * GP EMV has 1GB DDR3 connected to EMIF
+	 * along with VTT regulator.
+	 */
+	if (board_is_eposevm()) {
+		config_ddr(0, &ioregs_lpddr2, NULL, NULL, &emif_regs_lpddr2, 0);
+	} else if (board_is_gpevm()) {
+		enable_vtt_regulator();
+		config_ddr(0, &ioregs_ddr3, NULL, NULL,
+			   &ddr3_emif_regs_400Mhz, 0);
+	}
 }
 #endif
 
 int board_init(void)
 {
-	gd->bd->bi_boot_params = PHYS_DRAM_1 + 0x100;
+	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
 
 	return 0;
 }
@@ -52,6 +387,116 @@ int board_init(void)
 #ifdef CONFIG_BOARD_LATE_INIT
 int board_late_init(void)
 {
+#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+	char safe_string[HDR_NAME_LEN + 1];
+	struct am43xx_board_id header;
+
+	if (read_eeprom(&header) < 0)
+		puts("Could not get board ID.\n");
+
+	/* Now set variables based on the header. */
+	strncpy(safe_string, (char *)header.name, sizeof(header.name));
+	safe_string[sizeof(header.name)] = 0;
+	setenv("board_name", safe_string);
+
+	strncpy(safe_string, (char *)header.version, sizeof(header.version));
+	safe_string[sizeof(header.version)] = 0;
+	setenv("board_rev", safe_string);
+#endif
 	return 0;
 }
 #endif
+
+#ifdef CONFIG_DRIVER_TI_CPSW
+
+static void cpsw_control(int enabled)
+{
+	/* Additional controls can be added here */
+	return;
+}
+
+static struct cpsw_slave_data cpsw_slaves[] = {
+	{
+		.slave_reg_ofs	= 0x208,
+		.sliver_reg_ofs	= 0xd80,
+		.phy_addr	= 16,
+	},
+	{
+		.slave_reg_ofs	= 0x308,
+		.sliver_reg_ofs	= 0xdc0,
+		.phy_addr	= 1,
+	},
+};
+
+static struct cpsw_platform_data cpsw_data = {
+	.mdio_base		= CPSW_MDIO_BASE,
+	.cpsw_base		= CPSW_BASE,
+	.mdio_div		= 0xff,
+	.channels		= 8,
+	.cpdma_reg_ofs		= 0x800,
+	.slaves			= 1,
+	.slave_data		= cpsw_slaves,
+	.ale_reg_ofs		= 0xd00,
+	.ale_entries		= 1024,
+	.host_port_reg_ofs	= 0x108,
+	.hw_stats_reg_ofs	= 0x900,
+	.bd_ram_ofs		= 0x2000,
+	.mac_control		= (1 << 5),
+	.control		= cpsw_control,
+	.host_port_num		= 0,
+	.version		= CPSW_CTRL_VERSION_2,
+};
+
+int board_eth_init(bd_t *bis)
+{
+	int rv;
+	uint8_t mac_addr[6];
+	uint32_t mac_hi, mac_lo;
+
+	/* try reading mac address from efuse */
+	mac_lo = readl(&cdev->macid0l);
+	mac_hi = readl(&cdev->macid0h);
+	mac_addr[0] = mac_hi & 0xFF;
+	mac_addr[1] = (mac_hi & 0xFF00) >> 8;
+	mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
+	mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
+	mac_addr[4] = mac_lo & 0xFF;
+	mac_addr[5] = (mac_lo & 0xFF00) >> 8;
+
+	if (!getenv("ethaddr")) {
+		puts("<ethaddr> not set. Validating first E-fuse MAC\n");
+		if (is_valid_ether_addr(mac_addr))
+			eth_setenv_enetaddr("ethaddr", mac_addr);
+	}
+
+	mac_lo = readl(&cdev->macid1l);
+	mac_hi = readl(&cdev->macid1h);
+	mac_addr[0] = mac_hi & 0xFF;
+	mac_addr[1] = (mac_hi & 0xFF00) >> 8;
+	mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
+	mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
+	mac_addr[4] = mac_lo & 0xFF;
+	mac_addr[5] = (mac_lo & 0xFF00) >> 8;
+
+	if (!getenv("eth1addr")) {
+		if (is_valid_ether_addr(mac_addr))
+			eth_setenv_enetaddr("eth1addr", mac_addr);
+	}
+
+	if (board_is_eposevm()) {
+		writel(RMII_MODE_ENABLE | RMII_CHIPCKL_ENABLE, &cdev->miisel);
+		cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RMII;
+		cpsw_slaves[0].phy_addr = 16;
+	} else {
+		writel(RGMII_MODE_ENABLE, &cdev->miisel);
+		cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RGMII;
+		cpsw_slaves[0].phy_addr = 0;
+	}
+
+	rv = cpsw_register(&cpsw_data);
+	if (rv < 0)
+		printf("Error %d registering CPSW switch\n", rv);
+
+	return rv;
+}
+#endif
diff --git a/board/ti/am43xx/board.h b/board/ti/am43xx/board.h
index 8ca098b82a..091162ee20 100644
--- a/board/ti/am43xx/board.h
+++ b/board/ti/am43xx/board.h
@@ -12,6 +12,42 @@
 #ifndef _BOARD_H_
 #define _BOARD_H_
 
+#include <asm/arch/omap.h>
+
+static char *const am43xx_board_name = (char *)AM4372_BOARD_NAME_START;
+
+/*
+ * TI AM437x EVMs define a system EEPROM that defines certain sub-fields.
+ * We use these fields to in turn see what board we are on, and what
+ * that might require us to set or not set.
+ */
+#define HDR_NO_OF_MAC_ADDR	3
+#define HDR_ETH_ALEN		6
+#define HDR_NAME_LEN		8
+
+#define DEV_ATTR_MAX_OFFSET	5
+#define DEV_ATTR_MIN_OFFSET	0
+
+struct am43xx_board_id {
+	unsigned int  magic;
+	char name[HDR_NAME_LEN];
+	char version[4];
+	char serial[12];
+	char config[32];
+	char mac_addr[HDR_NO_OF_MAC_ADDR][HDR_ETH_ALEN];
+};
+
+static inline int board_is_eposevm(void)
+{
+	return !strncmp(am43xx_board_name, "AM43EPOS", HDR_NAME_LEN);
+}
+
+static inline int board_is_gpevm(void)
+{
+	return !strncmp(am43xx_board_name, "AM43__GP", HDR_NAME_LEN);
+}
+
 void enable_uart0_pin_mux(void);
 void enable_board_pin_mux(void);
+void enable_i2c0_pin_mux(void);
 #endif
diff --git a/board/ti/am43xx/mux.c b/board/ti/am43xx/mux.c
index 700e9a76ad..77c53d2e90 100644
--- a/board/ti/am43xx/mux.c
+++ b/board/ti/am43xx/mux.c
@@ -11,9 +11,75 @@
 #include <asm/arch/mux.h>
 #include "board.h"
 
+static struct module_pin_mux rmii1_pin_mux[] = {
+	{OFFSET(mii1_txen), MODE(1)},			/* RMII1_TXEN */
+	{OFFSET(mii1_txd1), MODE(1)},			/* RMII1_TD1 */
+	{OFFSET(mii1_txd0), MODE(1)},			/* RMII1_TD0 */
+	{OFFSET(mii1_rxd1), MODE(1) | RXACTIVE},	/* RMII1_RD1 */
+	{OFFSET(mii1_rxd0), MODE(1) | RXACTIVE},	/* RMII1_RD0 */
+	{OFFSET(mii1_rxdv), MODE(1) | RXACTIVE},	/* RMII1_RXDV */
+	{OFFSET(mii1_crs), MODE(1) | RXACTIVE},		/* RMII1_CRS_DV */
+	{OFFSET(mii1_rxerr), MODE(1) | RXACTIVE},	/* RMII1_RXERR */
+	{OFFSET(rmii1_refclk), MODE(0) | RXACTIVE},	/* RMII1_refclk */
+	{-1},
+};
+
+static struct module_pin_mux rgmii1_pin_mux[] = {
+	{OFFSET(mii1_txen), MODE(2)},			/* RGMII1_TCTL */
+	{OFFSET(mii1_rxdv), MODE(2) | RXACTIVE},	/* RGMII1_RCTL */
+	{OFFSET(mii1_txd3), MODE(2)},			/* RGMII1_TD3 */
+	{OFFSET(mii1_txd2), MODE(2)},			/* RGMII1_TD2 */
+	{OFFSET(mii1_txd1), MODE(2)},			/* RGMII1_TD1 */
+	{OFFSET(mii1_txd0), MODE(2)},			/* RGMII1_TD0 */
+	{OFFSET(mii1_txclk), MODE(2)},			/* RGMII1_TCLK */
+	{OFFSET(mii1_rxclk), MODE(2) | RXACTIVE},	/* RGMII1_RCLK */
+	{OFFSET(mii1_rxd3), MODE(2) | RXACTIVE},	/* RGMII1_RD3 */
+	{OFFSET(mii1_rxd2), MODE(2) | RXACTIVE},	/* RGMII1_RD2 */
+	{OFFSET(mii1_rxd1), MODE(2) | RXACTIVE},	/* RGMII1_RD1 */
+	{OFFSET(mii1_rxd0), MODE(2) | RXACTIVE},	/* RGMII1_RD0 */
+	{-1},
+};
+
+static struct module_pin_mux mdio_pin_mux[] = {
+	{OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN},/* MDIO_DATA */
+	{OFFSET(mdio_clk), MODE(0) | PULLUP_EN},	/* MDIO_CLK */
+	{-1},
+};
+
 static struct module_pin_mux uart0_pin_mux[] = {
-	{OFFSET(uart0_rxd), (MODE(0) | RXACTIVE)},	/* UART0_RXD */
-	{OFFSET(uart0_txd), (MODE(0))},			/* UART0_TXD */
+	{OFFSET(uart0_rxd), (MODE(0) | PULLUP_EN | RXACTIVE | SLEWCTRL)},
+	{OFFSET(uart0_txd), (MODE(0) | PULLUDDIS | PULLUP_EN | SLEWCTRL)},
+	{-1},
+};
+
+static struct module_pin_mux mmc0_pin_mux[] = {
+	{OFFSET(mmc0_clk), (MODE(0) | PULLUDDIS | RXACTIVE)},  /* MMC0_CLK */
+	{OFFSET(mmc0_cmd), (MODE(0) | PULLUP_EN | RXACTIVE)},  /* MMC0_CMD */
+	{OFFSET(mmc0_dat0), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* MMC0_DAT0 */
+	{OFFSET(mmc0_dat1), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* MMC0_DAT1 */
+	{OFFSET(mmc0_dat2), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* MMC0_DAT2 */
+	{OFFSET(mmc0_dat3), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* MMC0_DAT3 */
+	{-1},
+};
+
+static struct module_pin_mux i2c0_pin_mux[] = {
+	{OFFSET(i2c0_sda), (MODE(0) | PULLUP_EN | RXACTIVE | SLEWCTRL)},
+	{OFFSET(i2c0_scl), (MODE(0) | PULLUP_EN | RXACTIVE | SLEWCTRL)},
+	{-1},
+};
+
+static struct module_pin_mux gpio5_7_pin_mux[] = {
+	{OFFSET(spi0_cs0), (MODE(7) | PULLUP_EN)},	/* GPIO5_7 */
+	{-1},
+};
+
+static struct module_pin_mux qspi_pin_mux[] = {
+	{OFFSET(gpmc_csn0), (MODE(3) | PULLUP_EN | RXACTIVE)}, /* QSPI_CS0 */
+	{OFFSET(gpmc_csn3), (MODE(2) | PULLUP_EN | RXACTIVE)}, /* QSPI_CLK */
+	{OFFSET(gpmc_advn_ale), (MODE(3) | PULLUP_EN | RXACTIVE)}, /* QSPI_D0 */
+	{OFFSET(gpmc_oen_ren), (MODE(3) | PULLUP_EN | RXACTIVE)}, /* QSPI_D1 */
+	{OFFSET(gpmc_wen), (MODE(3) | PULLUP_EN | RXACTIVE)}, /* QSPI_D2 */
+	{OFFSET(gpmc_be0n_cle), (MODE(3) | PULLUP_EN | RXACTIVE)}, /* QSPI_D3 */
 	{-1},
 };
 
@@ -24,4 +90,20 @@ void enable_uart0_pin_mux(void)
 
 void enable_board_pin_mux(void)
 {
+	configure_module_pin_mux(mmc0_pin_mux);
+	configure_module_pin_mux(i2c0_pin_mux);
+	configure_module_pin_mux(mdio_pin_mux);
+
+	if (board_is_gpevm()) {
+		configure_module_pin_mux(gpio5_7_pin_mux);
+		configure_module_pin_mux(rgmii1_pin_mux);
+	} else if (board_is_eposevm()) {
+		configure_module_pin_mux(rmii1_pin_mux);
+		configure_module_pin_mux(qspi_pin_mux);
+	}
+}
+
+void enable_i2c0_pin_mux(void)
+{
+	configure_module_pin_mux(i2c0_pin_mux);
 }
diff --git a/board/ti/beagle/Makefile b/board/ti/beagle/Makefile
index 3018f6c63a..7a858be5e4 100644
--- a/board/ti/beagle/Makefile
+++ b/board/ti/beagle/Makefile
@@ -5,25 +5,5 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS-y	:= $(BOARD).o
-COBJS-$(CONFIG_STATUS_LED) += led.o
-
-COBJS	:= $(sort $(COBJS-y))
-SRCS	:= $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	:= beagle.o
+obj-$(CONFIG_STATUS_LED) += led.o
diff --git a/board/ti/beagle/beagle.c b/board/ti/beagle/beagle.c
index 62e9beaef3..9669a32fc1 100644
--- a/board/ti/beagle/beagle.c
+++ b/board/ti/beagle/beagle.c
@@ -521,9 +521,10 @@ static struct omap_usbhs_board_data usbhs_bdata = {
 	.port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED
 };
 
-int ehci_hcd_init(int index, struct ehci_hccr **hccr, struct ehci_hcor **hcor)
+int ehci_hcd_init(int index, enum usb_init_type init,
+		struct ehci_hccr **hccr, struct ehci_hcor **hcor)
 {
-	return omap_ehci_hcd_init(&usbhs_bdata, hccr, hcor);
+	return omap_ehci_hcd_init(index, &usbhs_bdata, hccr, hcor);
 }
 
 int ehci_hcd_stop(int index)
diff --git a/board/ti/dra7xx/Makefile b/board/ti/dra7xx/Makefile
index e558f4c89f..434e8d128e 100644
--- a/board/ti/dra7xx/Makefile
+++ b/board/ti/dra7xx/Makefile
@@ -5,29 +5,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	:= evm.o
-
-SRCS	:= $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-clean:
-	rm -f $(OBJS)
-
-distclean:	clean
-	rm -f $(LIB) core *.bak $(obj).depend
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	:= evm.o
diff --git a/board/ti/dra7xx/README b/board/ti/dra7xx/README
new file mode 100644
index 0000000000..533da01a34
--- /dev/null
+++ b/board/ti/dra7xx/README
@@ -0,0 +1,26 @@
+Summary
+=======
+
+This document covers various features of the 'dra7xx_evm' build and some
+related uses.
+
+eMMC boot partition use
+=======================
+
+It is possible, depending on SYSBOOT configuration to boot from the eMMC
+boot partitions using (name depending on documentation referenced)
+Alternative Boot operation mode or Boot Sequence Option 1/2.  In this
+example we load MLO and u-boot.img from the build into DDR and then use
+'mmc bootbus' to set the required rate (see TRM) and 'mmc partconfig' to
+set boot0 as the boot device.
+U-Boot # setenv autoload no
+U-Boot # usb start
+U-Boot # dhcp
+U-Boot # mmc dev 1 1
+U-Boot # tftp ${loadaddr} dra7xx/MLO
+U-Boot # mmc write ${loadaddr} 0 100
+U-Boot # tftp ${loadaddr} dra7xx/u-boot.img
+U-Boot # mmc write ${loadaddr} 300 400
+U-Boot # mmc bootbus 1 2 0 2
+U-Boot # mmc partconf 1 1 1 0
+U-Boot # mmc rst-function 1 1
diff --git a/board/ti/dra7xx/evm.c b/board/ti/dra7xx/evm.c
index 9a114e2a75..c6c4fd1743 100644
--- a/board/ti/dra7xx/evm.c
+++ b/board/ti/dra7xx/evm.c
@@ -12,17 +12,13 @@
  */
 #include <common.h>
 #include <palmas.h>
+#include <sata.h>
 #include <asm/arch/sys_proto.h>
 #include <asm/arch/mmc_host_def.h>
+#include <asm/arch/sata.h>
 
 #include "mux_data.h"
 
-#ifdef CONFIG_USB_EHCI
-#include <usb.h>
-#include <asm/arch/ehci.h>
-#include <asm/ehci-omap.h>
-#endif
-
 #ifdef CONFIG_DRIVER_TI_CPSW
 #include <cpsw.h>
 #endif
@@ -83,6 +79,12 @@ int board_init(void)
 	return 0;
 }
 
+int board_late_init(void)
+{
+	init_sata(0);
+	return 0;
+}
+
 /**
  * @brief misc_init_r - Configure EVM board specific configurations
  * such as power configurations, ethernet initialization as phase2 of
@@ -147,12 +149,12 @@ static struct cpsw_slave_data cpsw_slaves[] = {
 	{
 		.slave_reg_ofs	= 0x208,
 		.sliver_reg_ofs	= 0xd80,
-		.phy_id		= 0,
+		.phy_addr	= 2,
 	},
 	{
 		.slave_reg_ofs	= 0x308,
 		.sliver_reg_ofs	= 0xdc0,
-		.phy_id		= 1,
+		.phy_addr	= 3,
 	},
 };
 
@@ -201,12 +203,12 @@ int board_eth_init(bd_t *bis)
 	/* try reading mac address from efuse */
 	mac_lo = readl((*ctrl)->control_core_mac_id_0_lo);
 	mac_hi = readl((*ctrl)->control_core_mac_id_0_hi);
-	mac_addr[0] = mac_hi & 0xFF;
+	mac_addr[0] = (mac_hi & 0xFF0000) >> 16;
 	mac_addr[1] = (mac_hi & 0xFF00) >> 8;
-	mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
-	mac_addr[3] = mac_lo & 0xFF;
+	mac_addr[2] = mac_hi & 0xFF;
+	mac_addr[3] = (mac_lo & 0xFF0000) >> 16;
 	mac_addr[4] = (mac_lo & 0xFF00) >> 8;
-	mac_addr[5] = (mac_lo & 0xFF0000) >> 16;
+	mac_addr[5] = mac_lo & 0xFF;
 
 	if (!getenv("ethaddr")) {
 		printf("<ethaddr> not set. Validating first E-fuse MAC\n");
@@ -214,6 +216,21 @@ int board_eth_init(bd_t *bis)
 		if (is_valid_ether_addr(mac_addr))
 			eth_setenv_enetaddr("ethaddr", mac_addr);
 	}
+
+	mac_lo = readl((*ctrl)->control_core_mac_id_1_lo);
+	mac_hi = readl((*ctrl)->control_core_mac_id_1_hi);
+	mac_addr[0] = (mac_hi & 0xFF0000) >> 16;
+	mac_addr[1] = (mac_hi & 0xFF00) >> 8;
+	mac_addr[2] = mac_hi & 0xFF;
+	mac_addr[3] = (mac_lo & 0xFF0000) >> 16;
+	mac_addr[4] = (mac_lo & 0xFF00) >> 8;
+	mac_addr[5] = mac_lo & 0xFF;
+
+	if (!getenv("eth1addr")) {
+		if (is_valid_ether_addr(mac_addr))
+			eth_setenv_enetaddr("eth1addr", mac_addr);
+	}
+
 	ctrl_val = readl((*ctrl)->control_core_control_io1) & (~0x33);
 	ctrl_val |= 0x22;
 	writel(ctrl_val, (*ctrl)->control_core_control_io1);
diff --git a/board/ti/dra7xx/mux_data.h b/board/ti/dra7xx/mux_data.h
index 6965cc57d2..38de9d5a8b 100644
--- a/board/ti/dra7xx/mux_data.h
+++ b/board/ti/dra7xx/mux_data.h
@@ -61,5 +61,6 @@ const struct pad_conf_entry core_padconf_array_essential[] = {
 	{GPMC_A4, (IEN | PDIS | M1)},   /* QSPI1_CS3 */
 	{GPMC_CS2, (IEN | PTU | PDIS | M1)},    /* QSPI1_CS0 */
 	{GPMC_CS3, (IEN | PTU | PDIS | M1)},    /* QSPI1_CS1*/
+	{USB2_DRVVBUS, (M0 | IEN | FSC) },
 };
 #endif /* _MUX_DATA_DRA7XX_H_ */
diff --git a/board/ti/evm/Makefile b/board/ti/evm/Makefile
index 0f8cf446ba..b88ab8f517 100644
--- a/board/ti/evm/Makefile
+++ b/board/ti/evm/Makefile
@@ -5,21 +5,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	:= evm.o
-
-SRCS	:= $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
+obj-y	:= evm.o
diff --git a/board/ti/evm/evm.c b/board/ti/evm/evm.c
index c71c218529..81dd081d76 100644
--- a/board/ti/evm/evm.c
+++ b/board/ti/evm/evm.c
@@ -146,8 +146,8 @@ void get_board_mem_timings(struct board_sdrc_timings *timings)
 int misc_init_r(void)
 {
 
-#ifdef CONFIG_DRIVER_OMAP34XX_I2C
-	i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
+#ifdef CONFIG_SYS_I2C_OMAP34XX
+	i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE);
 #endif
 
 #if defined(CONFIG_CMD_NET)
diff --git a/board/ti/omap5912osk/Makefile b/board/ti/omap5912osk/Makefile
index b2727de687..d7c0ebd729 100644
--- a/board/ti/omap5912osk/Makefile
+++ b/board/ti/omap5912osk/Makefile
@@ -5,25 +5,5 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	:= omap5912osk.o
-SOBJS	:= lowlevel_init.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
-	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	:= omap5912osk.o
+obj-y	+= lowlevel_init.o
diff --git a/board/ti/omap5912osk/lowlevel_init.S b/board/ti/omap5912osk/lowlevel_init.S
index cad0a5acd8..e05a1c7b55 100644
--- a/board/ti/omap5912osk/lowlevel_init.S
+++ b/board/ti/omap5912osk/lowlevel_init.S
@@ -18,10 +18,6 @@
 #include <./configs/omap1510.h>
 #endif
 
-
-_TEXT_BASE:
-	.word	CONFIG_SYS_TEXT_BASE	/* sdram load addr from config.mk */
-
 .globl lowlevel_init
 lowlevel_init:
 
diff --git a/board/ti/omap5_uevm/Makefile b/board/ti/omap5_uevm/Makefile
index 2ab40e3ecf..b88ab8f517 100644
--- a/board/ti/omap5_uevm/Makefile
+++ b/board/ti/omap5_uevm/Makefile
@@ -5,29 +5,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	:= evm.o
-
-SRCS	:= $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-clean:
-	rm -f $(OBJS)
-
-distclean:	clean
-	rm -f $(LIB) core *.bak $(obj).depend
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	:= evm.o
diff --git a/board/ti/omap5_uevm/README b/board/ti/omap5_uevm/README
new file mode 100644
index 0000000000..970e2eceb7
--- /dev/null
+++ b/board/ti/omap5_uevm/README
@@ -0,0 +1,25 @@
+Summary
+=======
+
+This document covers various features of the 'omap5_uevm' build and some
+related uses.
+
+eMMC boot partition use
+=======================
+
+It is possible, depending on SYSBOOT configuration to boot from the eMMC
+boot partitions using (name depending on documentation referenced)
+Alternative Boot operation mode or Boot Sequence Option 1/2.  In this
+example we load MLO and u-boot.img from the build into DDR and then use
+'mmc bootbus' to set the required rate (see TRM) and 'mmc partconfig' to
+set boot0 as the boot device.
+U-Boot # setenv autoload no
+U-Boot # usb start
+U-Boot # dhcp
+U-Boot # mmc dev 1 1
+U-Boot # tftp ${loadaddr} omap5uevm/MLO
+U-Boot # mmc write ${loadaddr} 0 100
+U-Boot # tftp ${loadaddr} omap5uevm/u-boot.img
+U-Boot # mmc write ${loadaddr} 300 400
+U-Boot # mmc bootbus 1 2 0 2
+U-Boot # mmc partconf 1 1 1 0
diff --git a/board/ti/omap5_uevm/evm.c b/board/ti/omap5_uevm/evm.c
index 47063309e5..3eaa5ac398 100644
--- a/board/ti/omap5_uevm/evm.c
+++ b/board/ti/omap5_uevm/evm.c
@@ -14,12 +14,14 @@
 
 #include "mux_data.h"
 
-#ifdef CONFIG_USB_EHCI
+#if defined(CONFIG_USB_EHCI) || defined(CONFIG_USB_XHCI_OMAP)
+#include <sata.h>
 #include <usb.h>
 #include <asm/gpio.h>
 #include <asm/arch/clock.h>
 #include <asm/arch/ehci.h>
 #include <asm/ehci-omap.h>
+#include <asm/arch/sata.h>
 
 #define DIE_ID_REG_BASE     (OMAP54XX_L4_CORE_BASE + 0x2000)
 #define DIE_ID_REG_OFFSET	0x200
@@ -67,11 +69,46 @@ int board_init(void)
 	return 0;
 }
 
+int board_late_init(void)
+{
+	init_sata(0);
+	return 0;
+}
+
 int board_eth_init(bd_t *bis)
 {
 	return 0;
 }
 
+#if defined(CONFIG_USB_EHCI) || defined(CONFIG_USB_XHCI_OMAP)
+static void enable_host_clocks(void)
+{
+	int auxclk;
+	int hs_clk_ctrl_val = (OPTFCLKEN_HSIC60M_P3_CLK |
+				OPTFCLKEN_HSIC480M_P3_CLK |
+				OPTFCLKEN_HSIC60M_P2_CLK |
+				OPTFCLKEN_HSIC480M_P2_CLK |
+				OPTFCLKEN_UTMI_P3_CLK | OPTFCLKEN_UTMI_P2_CLK);
+
+	/* Enable port 2 and 3 clocks*/
+	setbits_le32((*prcm)->cm_l3init_hsusbhost_clkctrl, hs_clk_ctrl_val);
+
+	/* Enable port 2 and 3 usb host ports tll clocks*/
+	setbits_le32((*prcm)->cm_l3init_hsusbtll_clkctrl,
+			(OPTFCLKEN_USB_CH1_CLK_ENABLE | OPTFCLKEN_USB_CH2_CLK_ENABLE));
+#ifdef CONFIG_USB_XHCI_OMAP
+	/* Enable the USB OTG Super speed clocks */
+	setbits_le32((*prcm)->cm_l3init_usb_otg_ss_clkctrl,
+			(OPTFCLKEN_REFCLK960M | OTG_SS_CLKCTRL_MODULEMODE_HW));
+#endif
+
+	auxclk = readl((*prcm)->scrm_auxclk1);
+	/* Request auxilary clock */
+	auxclk |= AUXCLK_ENABLE_MASK;
+	writel(auxclk, (*prcm)->scrm_auxclk1);
+}
+#endif
+
 /**
  * @brief misc_init_r - Configure EVM board specific configurations
  * such as power configurations, ethernet initialization as phase2 of
@@ -81,9 +118,30 @@ int board_eth_init(bd_t *bis)
  */
 int misc_init_r(void)
 {
+	int reg;
+	uint8_t device_mac[6];
+
 #ifdef CONFIG_PALMAS_POWER
 	palmas_init_settings();
 #endif
+
+	if (!getenv("usbethaddr")) {
+		reg = DIE_ID_REG_BASE + DIE_ID_REG_OFFSET;
+
+		/*
+		 * create a fake MAC address from the processor ID code.
+		 * first byte is 0x02 to signify locally administered.
+		 */
+		device_mac[0] = 0x02;
+		device_mac[1] = readl(reg + 0x10) & 0xff;
+		device_mac[2] = readl(reg + 0xC) & 0xff;
+		device_mac[3] = readl(reg + 0x8) & 0xff;
+		device_mac[4] = readl(reg) & 0xff;
+		device_mac[5] = (readl(reg) >> 8) & 0xff;
+
+		eth_setenv_enetaddr("usbethaddr", device_mac);
+	}
+
 	return 0;
 }
 
@@ -100,19 +158,6 @@ void set_muxconf_regs_essential(void)
 		   sizeof(struct pad_conf_entry));
 }
 
-void set_muxconf_regs_non_essential(void)
-{
-	do_set_mux((*ctrl)->control_padconf_core_base,
-		   core_padconf_array_non_essential,
-		   sizeof(core_padconf_array_non_essential) /
-		   sizeof(struct pad_conf_entry));
-
-	do_set_mux((*ctrl)->control_padconf_wkup_base,
-		   wkup_padconf_array_non_essential,
-		   sizeof(wkup_padconf_array_non_essential) /
-		   sizeof(struct pad_conf_entry));
-}
-
 #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_GENERIC_MMC)
 int board_mmc_init(bd_t *bis)
 {
@@ -129,54 +174,14 @@ static struct omap_usbhs_board_data usbhs_bdata = {
 	.port_mode[2] = OMAP_EHCI_PORT_MODE_HSIC,
 };
 
-static void enable_host_clocks(void)
-{
-	int hs_clk_ctrl_val = (OPTFCLKEN_HSIC60M_P3_CLK |
-				OPTFCLKEN_HSIC480M_P3_CLK |
-				OPTFCLKEN_HSIC60M_P2_CLK |
-				OPTFCLKEN_HSIC480M_P2_CLK |
-				OPTFCLKEN_UTMI_P3_CLK | OPTFCLKEN_UTMI_P2_CLK);
-
-	/* Enable port 2 and 3 clocks*/
-	setbits_le32((*prcm)->cm_l3init_hsusbhost_clkctrl, hs_clk_ctrl_val);
-
-	/* Enable port 2 and 3 usb host ports tll clocks*/
-	setbits_le32((*prcm)->cm_l3init_hsusbtll_clkctrl,
-			(OPTFCLKEN_USB_CH1_CLK_ENABLE | OPTFCLKEN_USB_CH2_CLK_ENABLE));
-}
-
-int ehci_hcd_init(int index, struct ehci_hccr **hccr, struct ehci_hcor **hcor)
+int ehci_hcd_init(int index, enum usb_init_type init,
+		struct ehci_hccr **hccr, struct ehci_hcor **hcor)
 {
 	int ret;
-	int auxclk;
-	int reg;
-	uint8_t device_mac[6];
 
 	enable_host_clocks();
 
-	if (!getenv("usbethaddr")) {
-		reg = DIE_ID_REG_BASE + DIE_ID_REG_OFFSET;
-
-		/*
-		 * create a fake MAC address from the processor ID code.
-		 * first byte is 0x02 to signify locally administered.
-		 */
-		device_mac[0] = 0x02;
-		device_mac[1] = readl(reg + 0x10) & 0xff;
-		device_mac[2] = readl(reg + 0xC) & 0xff;
-		device_mac[3] = readl(reg + 0x8) & 0xff;
-		device_mac[4] = readl(reg) & 0xff;
-		device_mac[5] = (readl(reg) >> 8) & 0xff;
-
-		eth_setenv_enetaddr("usbethaddr", device_mac);
-	}
-
-	auxclk = readl((*prcm)->scrm_auxclk1);
-	/* Request auxilary clock */
-	auxclk |= AUXCLK_ENABLE_MASK;
-	writel(auxclk, (*prcm)->scrm_auxclk1);
-
-	ret = omap_ehci_hcd_init(&usbhs_bdata, hccr, hcor);
+	ret = omap_ehci_hcd_init(index, &usbhs_bdata, hccr, hcor);
 	if (ret < 0) {
 		puts("Failed to initialize ehci\n");
 		return ret;
@@ -203,3 +208,23 @@ void usb_hub_reset_devices(int port)
 	}
 }
 #endif
+
+#ifdef CONFIG_USB_XHCI_OMAP
+/**
+ * @brief board_usb_init - Configure EVM board specific configurations
+ * for the LDO's and clocks for the USB blocks.
+ *
+ * @return 0
+ */
+int board_usb_init(int index, enum usb_init_type init)
+{
+	int ret;
+#ifdef CONFIG_PALMAS_USB_SS_PWR
+	ret = palmas_enable_ss_ldo();
+#endif
+
+	enable_host_clocks();
+
+	return 0;
+}
+#endif
diff --git a/board/ti/omap5_uevm/mux_data.h b/board/ti/omap5_uevm/mux_data.h
index 31ce363b63..de7ce9fe0b 100644
--- a/board/ti/omap5_uevm/mux_data.h
+++ b/board/ti/omap5_uevm/mux_data.h
@@ -55,238 +55,4 @@ const struct pad_conf_entry wkup_padconf_array_essential[] = {
 
 };
 
-const struct pad_conf_entry core_padconf_array_non_essential[] = {
-
-	{C2C_DATAIN0, (IEN | M0)},    /*  C2C_DATAIN0   */
-	{C2C_DATAIN1, (IEN | M0)},    /*  C2C_DATAIN1   */
-	{C2C_DATAIN2, (IEN | M0)},    /*  C2C_DATAIN2   */
-	{C2C_DATAIN3, (IEN | M0)},    /*  C2C_DATAIN3   */
-	{C2C_DATAIN4, (IEN | M0)},    /*  C2C_DATAIN4   */
-	{C2C_DATAIN5, (IEN | M0)},    /*  C2C_DATAIN5   */
-	{C2C_DATAIN6, (IEN | M0)},    /*  C2C_DATAIN6   */
-	{C2C_DATAIN7, (IEN | M0)},    /*  C2C_DATAIN7   */
-	{C2C_CLKIN1,  (IEN | M0)},    /*  C2C_CLKIN1    */
-	{C2C_CLKIN0,  (IEN | M0)},    /*  C2C_CLKIN0    */
-	{C2C_CLKOUT0, (M0)},    /*  C2C_CLKOUT0   */
-	{C2C_CLKOUT1, (M0)},    /*  C2C_CLKOUT1   */
-	{C2C_DATAOUT0, (M0)},    /*  C2C_DATAOUT0  */
-	{C2C_DATAOUT1, (M0)},    /*  C2C_DATAOUT1  */
-	{C2C_DATAOUT2, (M0)},    /*  C2C_DATAOUT2  */
-	{C2C_DATAOUT3, (M0)},    /*  C2C_DATAOUT3  */
-	{C2C_DATAOUT4, (M0)},    /*  C2C_DATAOUT4  */
-	{C2C_DATAOUT5, (M0)},    /*  C2C_DATAOUT5  */
-	{C2C_DATAOUT6, (M0)},    /*  C2C_DATAOUT6  */
-	{C2C_DATAOUT7, (M0)},    /*  C2C_DATAOUT7  */
-	{C2C_DATA8, (IEN | M0)},    /*  C2C_DATA8     */
-	{C2C_DATA9, (IEN | M0)},    /*  C2C_DATA9     */
-	{C2C_DATA10, (IEN | M0)},    /*  C2C_DATA10    */
-	{C2C_DATA11, (IEN | M0)},    /*  C2C_DATA11    */
-	{C2C_DATA12, (IEN | M0)},    /*  C2C_DATA12    */
-	{C2C_DATA13, (IEN | M0)},    /*  C2C_DATA13    */
-	{C2C_DATA14, (IEN | M0)},    /*  C2C_DATA14    */
-	{C2C_DATA15, (IEN | M0)},    /*  C2C_DATA15    */
-	{LLIB_WAKEREQOUT, (PTU | IEN | M6)},    /*  GPIO2_32      */
-	{LLIA_WAKEREQOUT, (M1)},    /*  C2C_WAKEREQOUT */
-	{HSI1_ACREADY, (PTD | M6)},    /*  GPIO3_64  */
-	{HSI1_CAREADY, (PTD | M6)},    /*  GPIO3_65  */
-	{HSI1_ACWAKE,  (PTD | IEN | M6)},    /*  GPIO3_66  */
-	{HSI1_CAWAKE,  (PTU | IEN | M6)},    /*  GPIO3_67  */
-	{HSI1_ACFLAG,  (PTD | IEN | M6)},    /*  GPIO3_68  */
-	{HSI1_ACDATA,  (PTD | M6)},    /*  GPIO3_69  */
-	{HSI1_CAFLAG,  (M6)},    /*  GPIO3_70  */
-	{HSI1_CADATA,  (M6)},    /*  GPIO3_71  */
-	{UART1_TX, (M0)},    /*  UART1_TX  */
-	{UART1_CTS, (PTU | IEN | M0)},    /*  UART1_CTS */
-	{UART1_RX, (PTU | IEN | M0)},    /*  UART1_RX  */
-	{UART1_RTS, (M0)},    /*  UART1_RTS */
-	{HSI2_CAREADY, (IEN | M0)},    /*  HSI2_CAREADY */
-	{HSI2_ACREADY, (OFF_EN | M0)},    /*  HSI2_ACREADY */
-	{HSI2_CAWAKE, (IEN | PTD | M0)},    /*  HSI2_CAWAKE  */
-	{HSI2_ACWAKE, (M0)},    /*  HSI2_ACWAKE  */
-	{HSI2_CAFLAG, (IEN | PTD | M0)},    /*  HSI2_CAFLAG  */
-	{HSI2_CADATA, (IEN | PTD | M0)},    /*  HSI2_CADATA  */
-	{HSI2_ACFLAG, (M0)},    /*  HSI2_ACFLAG  */
-	{HSI2_ACDATA, (M0)},    /*  HSI2_ACDATA  */
-	{UART2_RTS, (IEN | M1)},    /*  MCSPI3_SOMI  */
-	{UART2_CTS, (IEN | M1)},    /*  MCSPI3_CS0   */
-	{UART2_RX, (IEN | M1)},    /*  MCSPI3_SIMO  */
-	{UART2_TX, (IEN | M1)},    /*  MCSPI3_CLK   */
-	{TIMER10_PWM_EVT, (IEN | M0)},    /*  TIMER10_PWM_EVT  */
-	{DSIPORTA_TE0, (IEN | M0)},    /*  DSIPORTA_TE0     */
-	{DSIPORTA_LANE0X, (IEN | M0)},    /*  DSIPORTA_LANE0X  */
-	{DSIPORTA_LANE0Y, (IEN | M0)},    /*  DSIPORTA_LANE0Y  */
-	{DSIPORTA_LANE1X, (IEN | M0)},    /*  DSIPORTA_LANE1X  */
-	{DSIPORTA_LANE1Y, (IEN | M0)},    /*  DSIPORTA_LANE1Y  */
-	{DSIPORTA_LANE2X, (IEN | M0)},    /*  DSIPORTA_LANE2X  */
-	{DSIPORTA_LANE2Y, (IEN | M0)},    /*  DSIPORTA_LANE2Y  */
-	{DSIPORTA_LANE3X, (IEN | M0)},    /*  DSIPORTA_LANE3X  */
-	{DSIPORTA_LANE3Y, (IEN | M0)},    /*  DSIPORTA_LANE3Y  */
-	{DSIPORTA_LANE4X, (IEN | M0)},    /*  DSIPORTA_LANE4X  */
-	{DSIPORTA_LANE4Y, (IEN | M0)},    /*  DSIPORTA_LANE4Y  */
-	{TIMER9_PWM_EVT, (IEN | M0)},    /*  TIMER9_PWM_EVT   */
-	{DSIPORTC_TE0, (IEN | M0)},    /*  DSIPORTC_TE0     */
-	{DSIPORTC_LANE0X, (IEN | M0)},    /*  DSIPORTC_LANE0X  */
-	{DSIPORTC_LANE0Y, (IEN | M0)},    /*  DSIPORTC_LANE0Y  */
-	{DSIPORTC_LANE1X, (IEN | M0)},    /*  DSIPORTC_LANE1X  */
-	{DSIPORTC_LANE1Y, (IEN | M0)},    /*  DSIPORTC_LANE1Y  */
-	{DSIPORTC_LANE2X, (IEN | M0)},    /*  DSIPORTC_LANE2X  */
-	{DSIPORTC_LANE2Y, (IEN | M0)},    /*  DSIPORTC_LANE2Y  */
-	{DSIPORTC_LANE3X, (IEN | M0)},    /*  DSIPORTC_LANE3X  */
-	{DSIPORTC_LANE3Y, (IEN | M0)},    /*  DSIPORTC_LANE3Y  */
-	{DSIPORTC_LANE4X, (IEN | M0)},    /*  DSIPORTC_LANE4X  */
-	{DSIPORTC_LANE4Y, (IEN | M0)},    /*  DSIPORTC_LANE4Y  */
-	{RFBI_HSYNC0, (M4)},    /*  KBD_COL5   */
-	{RFBI_TE_VSYNC0, (PTD | M6)},    /*  GPIO6_161  */
-	{RFBI_RE, (M4)},    /*  KBD_COL4   */
-	{RFBI_A0, (PTD | IEN | M6)},    /*  GPIO6_165  */
-	{RFBI_DATA8, (M4)},    /*  KBD_COL3   */
-	{RFBI_DATA9, (PTD | M6)},    /*  GPIO6_175  */
-	{RFBI_DATA10, (PTD | M6)},    /*  GPIO6_176  */
-	{RFBI_DATA11, (PTD | M6)},    /*  GPIO6_177  */
-	{RFBI_DATA12, (PTD | M6)},    /*  GPIO6_178  */
-	{RFBI_DATA13, (PTU | IEN | M6)},    /*  GPIO6_179  */
-	{RFBI_DATA14, (M4)},    /*  KBD_COL7   */
-	{RFBI_DATA15, (M4)},    /*  KBD_COL6   */
-	{GPIO6_182, (M6)},    /*  GPIO6_182  */
-	{GPIO6_183, (PTD | M6)},    /*  GPIO6_183  */
-	{GPIO6_184, (M4)},    /*  KBD_COL2   */
-	{GPIO6_185, (PTD | IEN | M6)},    /*  GPIO6_185  */
-	{GPIO6_186, (PTD | M6)},    /*  GPIO6_186  */
-	{GPIO6_187, (PTU | IEN | M4)},    /*  KBD_ROW2   */
-	{RFBI_DATA0, (PTD | M6)},    /*  GPIO6_166  */
-	{RFBI_DATA1, (PTD | M6)},    /*  GPIO6_167  */
-	{RFBI_DATA2, (PTD | M6)},    /*  GPIO6_168  */
-	{RFBI_DATA3, (PTD | IEN | M6)},    /*  GPIO6_169  */
-	{RFBI_DATA4, (IEN | M6)},    /*  GPIO6_170  */
-	{RFBI_DATA5, (IEN | M6)},    /*  GPIO6_171  */
-	{RFBI_DATA6, (PTD | M6)},    /*  GPIO6_172  */
-	{RFBI_DATA7, (PTD | M6)},    /*  GPIO6_173  */
-	{RFBI_CS0, (PTD | IEN | M6)},    /*  GPIO6_163  */
-	{RFBI_WE, (PTD | M6)},    /*  GPIO6_162  */
-	{MCSPI2_CS0, (M0)},    /*  MCSPI2_CS0 */
-	{MCSPI2_CLK, (IEN | M0)},    /*  MCSPI2_CLK */
-	{MCSPI2_SIMO, (IEN | M0)},    /*  MCSPI2_SIMO*/
-	{MCSPI2_SOMI, (PTU | IEN | M0)},    /*  MCSPI2_SOMI*/
-	{I2C4_SCL, (IEN | M0)},    /*  I2C4_SCL   */
-	{I2C4_SDA, (IEN | M0)},    /*  I2C4_SDA   */
-	{HDMI_CEC, (IEN | M0)},    /*  HDMI_CEC   */
-	{HDMI_HPD, (PTD | IEN | M0)},    /*  HDMI_HPD   */
-	{HDMI_DDC_SCL, (IEN | M0)},    /*  HDMI_DDC_SCL */
-	{HDMI_DDC_SDA, (IEN | M0)},    /*  HDMI_DDC_SDA */
-	{CSIPORTA_LANE0X, (IEN | M0)},    /*  CSIPORTA_LANE0X  */
-	{CSIPORTA_LANE0Y, (IEN | M0)},    /*  CSIPORTA_LANE0Y  */
-	{CSIPORTA_LANE1Y, (IEN | M0)},    /*  CSIPORTA_LANE1Y  */
-	{CSIPORTA_LANE1X, (IEN | M0)},    /*  CSIPORTA_LANE1X  */
-	{CSIPORTA_LANE2Y, (IEN | M0)},    /*  CSIPORTA_LANE2Y  */
-	{CSIPORTA_LANE2X, (IEN | M0)},    /*  CSIPORTA_LANE2X  */
-	{CSIPORTA_LANE3X, (IEN | M0)},    /*  CSIPORTA_LANE3X  */
-	{CSIPORTA_LANE3Y, (IEN | M0)},    /*  CSIPORTA_LANE3Y  */
-	{CSIPORTA_LANE4X, (IEN | M0)},    /*  CSIPORTA_LANE4X  */
-	{CSIPORTA_LANE4Y, (IEN | M0)},    /*  CSIPORTA_LANE4Y  */
-	{CSIPORTB_LANE0X, (IEN | M0)},    /*  CSIPORTB_LANE0X  */
-	{CSIPORTB_LANE0Y, (IEN | M0)},    /*  CSIPORTB_LANE0Y  */
-	{CSIPORTB_LANE1Y, (IEN | M0)},    /*  CSIPORTB_LANE1Y  */
-	{CSIPORTB_LANE1X, (IEN | M0)},    /*  CSIPORTB_LANE1X  */
-	{CSIPORTB_LANE2Y, (IEN | M0)},    /*  CSIPORTB_LANE2Y  */
-	{CSIPORTB_LANE2X, (IEN | M0)},    /*  CSIPORTB_LANE2X  */
-	{CSIPORTC_LANE0Y, (IEN | M0)},    /*  CSIPORTC_LANE0Y  */
-	{CSIPORTC_LANE0X, (IEN | M0)},    /*  CSIPORTC_LANE0X  */
-	{CSIPORTC_LANE1Y, (IEN | M0)},    /*  CSIPORTC_LANE1Y  */
-	{CSIPORTC_LANE1X, (IEN | M0)},    /*  CSIPORTC_LANE1X  */
-	{CAM_SHUTTER, (M0)},    /*  CAM_SHUTTER      */
-	{CAM_STROBE, (M0)},    /*  CAM_STROBE       */
-	{CAM_GLOBALRESET, (IEN | M0)},    /*  CAM_GLOBALRESET  */
-	{TIMER11_PWM_EVT, (PTD | M6)},    /*  GPIO8_227  */
-	{TIMER5_PWM_EVT, (PTD | M6)},    /*  GPIO8_228  */
-	{TIMER6_PWM_EVT, (PTD | M6)},    /*  GPIO8_229  */
-	{TIMER8_PWM_EVT,      (PTU | M6)},    /*  GPIO8_230  */
-	{I2C3_SCL, (IEN | M0)},    /*  I2C3_SCL   */
-	{I2C3_SDA, (IEN | M0)},    /*  I2C3_SDA   */
-	{GPIO8_233, (IEN | M2)},    /*  TIMER8_PWM_EVT   */
-	{ABE_CLKS, (IEN | M0)},    /*  ABE_CLKS  */
-	{ABEDMIC_DIN1, (IEN | M0)},    /*  ABEDMIC_DIN1 */
-	{ABEDMIC_DIN2, (IEN | M0)},    /*  ABEDMIC_DIN2 */
-	{ABEDMIC_DIN3, (IEN | M0)},    /*  ABEDMIC_DIN3 */
-	{ABEDMIC_CLK1, (M0)},    /*  ABEDMIC_CLK1 */
-	{ABEDMIC_CLK2, (IEN | M1)},    /*  ABEMCBSP1_FSX */
-	{ABEDMIC_CLK3, (M1)},    /*  ABEMCBSP1_DX  */
-	{ABESLIMBUS1_CLOCK, (IEN | M1)},    /*  ABEMCBSP1_CLKX   */
-	{ABESLIMBUS1_DATA, (IEN | M1)},    /*  ABEMCBSP1_DR */
-	{ABEMCBSP2_DR, (IEN | M0)},    /*  ABEMCBSP2_DR */
-	{ABEMCBSP2_DX, (M0)},    /*  ABEMCBSP2_DX */
-	{ABEMCBSP2_FSX, (IEN | M0)},    /*  ABEMCBSP2_FSX  */
-	{ABEMCBSP2_CLKX, (IEN | M0)},    /*  ABEMCBSP2_CLKX */
-	{ABEMCPDM_UL_DATA, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},    /*  ABEMCPDM_UL_DATA */
-	{ABEMCPDM_DL_DATA, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},    /*  ABEMCPDM_DL_DATA */
-	{ABEMCPDM_FRAME, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},    /*  ABEMCPDM_FRAME   */
-	{ABEMCPDM_LB_CLK, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},    /*  ABEMCPDM_LB_CLK  */
-	{WLSDIO_CLK, (PTU | IEN | M0)},    /*  WLSDIO_CLK  */
-	{WLSDIO_CMD, (PTU | IEN | M0)},    /*  WLSDIO_CMD  */
-	{WLSDIO_DATA0, (PTU | IEN | M0)},    /*  WLSDIO_DATA0*/
-	{WLSDIO_DATA1, (PTU | IEN | M0)},    /*  WLSDIO_DATA1*/
-	{WLSDIO_DATA2, (PTU | IEN | M0)},    /*  WLSDIO_DATA2*/
-	{WLSDIO_DATA3, (PTU | IEN | M0)},    /*  WLSDIO_DATA3*/
-	{UART5_RX, (PTU | IEN | M0)},    /*  UART5_RX    */
-	{UART5_TX, (M0)},    /*  UART5_TX    */
-	{UART5_CTS, (PTU | IEN | M0)},    /*  UART5_CTS   */
-	{UART5_RTS, (M0)},    /*  UART5_RTS   */
-	{I2C2_SCL, (IEN | M0)},    /*  I2C2_SCL    */
-	{I2C2_SDA, (IEN | M0)},    /*  I2C2_SDA    */
-	{MCSPI1_CLK, (M6)},    /*  GPIO5_140   */
-	{MCSPI1_SOMI, (IEN | M6)},    /*  GPIO5_141   */
-	{MCSPI1_SIMO, (PTD | M6)},    /*  GPIO5_142   */
-	{MCSPI1_CS0, (PTD | M6)},    /*  GPIO5_143   */
-	{MCSPI1_CS1, (PTD | IEN | M6)},    /*  GPIO5_144   */
-	{I2C5_SCL, (IEN | M0)},    /*  I2C5_SCL    */
-	{I2C5_SDA, (IEN | M0)},    /*  I2C5_SDA    */
-	{PERSLIMBUS2_CLOCK, (PTD | M6)},    /*  GPIO5_145   */
-	{PERSLIMBUS2_DATA, (PTD | IEN | M6)},    /*  GPIO5_146   */
-	{UART6_TX, (PTU | IEN | M6)},    /*  GPIO5_149   */
-	{UART6_RX, (PTU | IEN | M6)},    /*  GPIO5_150   */
-	{UART6_CTS, (PTU | IEN | M6)},    /*  GPIO5_151   */
-	{UART6_RTS, (PTU | M0)},    /*  UART6_RTS   */
-	{UART3_CTS_RCTX, (PTU | IEN | M6)},    /*  GPIO5_153   */
-	{UART3_RTS_IRSD, (PTU | IEN | M1)},    /*  HDQ_SIO     */
-	{I2C1_PMIC_SCL, (PTU | IEN | M0)},    /*  I2C1_PMIC_SCL  */
-	{I2C1_PMIC_SDA, (PTU | IEN | M0)},    /*  I2C1_PMIC_SDA  */
-
-};
-
-const struct pad_conf_entry wkup_padconf_array_non_essential[] = {
-
-/*
- * This pad keeps C2C Module always enabled.
- * Putting this in safe mode do not cause the issue.
- * C2C driver could enable this mux setting if needed.
- */
-	{LLIA_WAKEREQIN, (M7)},    /*  SAFE MODE  */
-	{LLIB_WAKEREQIN, (M7)},    /*  SAFE MODE  */
-	{DRM_EMU0, (PTU | IEN | M0)},    /*  DRM_EMU0    */
-	{DRM_EMU1, (PTU | IEN | M0)},    /*  DRM_EMU1    */
-	{JTAG_NTRST, (IEN | M0)},    /*  JTAG_NTRST  */
-	{JTAG_TCK, (IEN | M0)},    /*  JTAG_TCK    */
-	{JTAG_RTCK, (M0)},    /*  JTAG_RTCK   */
-	{JTAG_TMSC, (IEN | M0)},    /*  JTAG_TMSC   */
-	{JTAG_TDI, (IEN | M0)},    /*  JTAG_TDI    */
-	{JTAG_TDO, (M0)},    /*  JTAG_TDO    */
-	{FREF_CLK_IOREQ, (IEN | M0)},    /*  FREF_CLK_IOREQ */
-	{FREF_CLK0_OUT, (M0)},    /*  FREF_CLK0_OUT  */
-	{FREF_CLK1_OUT, (M0)},    /*  FREF_CLK1_OUT  */
-	{FREF_CLK2_OUT, (M0)},    /*  FREF_CLK2_OUT  */
-	{FREF_CLK2_REQ, (PTU | IEN | M6)},    /*  GPIO1_WK9      */
-	{FREF_CLK1_REQ, (PTD | IEN | M6)},    /*  GPIO1_WK8      */
-	{SYS_NRESPWRON, (IEN | M0)},    /*  SYS_NRESPWRON  */
-	{SYS_NRESWARM, (PTU | IEN | M0)},    /*  SYS_NRESWARM   */
-	{SYS_PWR_REQ, (M0)},    /*  SYS_PWR_REQ    */
-	{SYS_NIRQ1, (PTU | IEN | M0)},    /*  SYS_NIRQ1      */
-	{SYS_NIRQ2, (PTU | IEN | M0)},    /*  SYS_NIRQ2      */
-	{SYS_BOOT0, (IEN | M0)},    /*  SYS_BOOT0      */
-	{SYS_BOOT1, (IEN | M0)},    /*  SYS_BOOT1      */
-	{SYS_BOOT2, (IEN | M0)},    /*  SYS_BOOT2      */
-	{SYS_BOOT3, (IEN | M0)},    /*  SYS_BOOT3      */
-	{SYS_BOOT4, (IEN | M0)},    /*  SYS_BOOT4      */
-	{SYS_BOOT5, (IEN | M0)},    /*  SYS_BOOT5      */
-
-};
-
 #endif /* _EVM4430_MUX_DATA_H */
diff --git a/board/ti/omap730p2/Makefile b/board/ti/omap730p2/Makefile
deleted file mode 100644
index 37a4d3418b..0000000000
--- a/board/ti/omap730p2/Makefile
+++ /dev/null
@@ -1,29 +0,0 @@
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	:= omap730p2.o flash.o
-SOBJS	:= lowlevel_init.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
-	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
diff --git a/board/ti/omap730p2/README.omap730p2 b/board/ti/omap730p2/README.omap730p2
deleted file mode 100644
index 7c70916120..0000000000
--- a/board/ti/omap730p2/README.omap730p2
+++ /dev/null
@@ -1,91 +0,0 @@
-
-		     u-boot for the TI OMAP730 Perseus2
-
-		      Dave Peverley, MPC-Data Limited
-			 http://www.mpc-data.co.uk
-
-
-Overview :
-
- As the OMAP730 is similar to the OMAP1610 in many ways, this port was based
-on the u-boot port to the OMAP1610 Innovator. Supported features are :
-
-  - Serial terminal support
-  - Onboard NOR Flash
-  - Ethernet via the seperate debug board
-  - Tested on Rev4 and Rev5 boards
-
- It has also been tested to work correctly when built with a 'standard' GCC
-3.2.1 cross-compiler as well as Montavista Linux CEE 3.1's toolchain.
-
-
-Hardware Configuration :
-
- The main dips on the P2 board should be set to 2,3,7 and 9 on with all
-others off. On the debug board, dips 1 and 7 should be on with the rest off.
-The serial console has been set up to run from the DB9 connector on the
-P2 board at 115200 baud, 8 data bits, no stop bits, 1 parity bit.
-
- It should be noted that the P2 board has NOR flash that is addressable via
-either CS0 or CS3. This mode can be changed via DIP9 on the P2 board.
-
-
-Installing u-boot for the P2 :
-
- You can simply build u-boot for the Perseus by following the instructions
-in the main readme file. The target configuration is "omap730p2_config".
-Once u-boot has been built, you should strip the executable so it can be
-loaded via CCS (which cant cope with the symbols in the ELF binary) :
-  $ cp u-boot u-boot.out
-  $ arm-linux-strip u-boot.out
-
- The method we've used for installing u-boot the first time on a P2 is
-as follows :
-
-1) Configure TI Code Composer Studio to connect to the P2 board via JTAG
-   as described in the Users Guide.
-
-2) Set up the P2 to boot from CS3, and connect with CCS. Reset the CPU
-   and run the "init_mmu" GEL script.
-
-3) Use the "Load Program" option to send the u-boot.out file to the P2 and
-   run.
-
- At this point, u-boot should run and you will see the boot menu on your
-serial terminal. You can then load the u-boot image to memory :
-
-  # loadb 0x10000000
-
- Send the "u-boot.bin" binary via the serial using Kermit. Once loaded
-you can self-flash u-boot :
-
-  # protect off 1:0
-  # erase 1:0
-  # cp.b 0x10000000 0x0 0x20000
-
- You should now be able to reset the board and run u-boot from flash.
-
-
-Alternative flash option :
-
- Sometimes, if you've been silly, you can get the board into a state where
-whats in flash has upset the board so much that you can no longer connect
-to the P2 via JTAG. However, you can set DIP9 to off to swap the boot mode
-of the P2 so that you boot from RAM instead of NOR flash. This moves NOR
-flash up to 0x0C000000. You can build a special version of u-boot to
-utilise this by the following config :
-
-  $ make omap730p2_cs0boot_config
-
- If you load this up via CCS it will detect flash at its alternate location
-and allow you to programme your u-boot image (which, remember must be built
-for CS3 boot!) Once you do this, you can revert to CS3 boot and it will work
-fine again.
-
-
-Errata :
-
-1) It's been observed that sometimes the tftp transfer of kernels to the
-   board can have checksum errors or stall. This appears to be an issue
-   with the lan91c96.c driver, and can normally be worked around by
-   resetting the board and trying again.
diff --git a/board/ti/omap730p2/config.mk b/board/ti/omap730p2/config.mk
deleted file mode 100644
index 86188204ea..0000000000
--- a/board/ti/omap730p2/config.mk
+++ /dev/null
@@ -1,25 +0,0 @@
-#
-# (C) Copyright 2002
-# Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
-# David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
-#
-# (C) Copyright 2003
-# Texas Instruments, <www.ti.com>
-# Kshitij Gupta <Kshitij@ti.com>
-#
-# TI Perseus 2 board with OMAP720 (ARM925EJS) cpu
-# see http://www.ti.com/ for more information on Texas Instruments
-#
-# Innovator has 1 bank of 256 MB SDRAM
-# Physical Address:
-# 1000'0000 to 2000'0000
-#
-#
-# Linux-Kernel is expected to be at 1000'8000, entry 1000'8000
-# (mem base + reserved)
-#
-# we load ourself to 1108'0000
-#
-#
-
-CONFIG_SYS_TEXT_BASE = 0x11080000
diff --git a/board/ti/omap730p2/flash.c b/board/ti/omap730p2/flash.c
deleted file mode 100644
index 56f981c47b..0000000000
--- a/board/ti/omap730p2/flash.c
+++ /dev/null
@@ -1,463 +0,0 @@
-/*
- * (C) Copyright 2001
- * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
- *
- * (C) Copyright 2001
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * (C) Copyright 2003
- * Texas Instruments, <www.ti.com>
- * Kshitij Gupta <Kshitij@ti.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <linux/byteorder/swab.h>
-
-#define PHYS_FLASH_SECT_SIZE	0x00020000	/* 256 KB sectors (x2) */
-flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];	/* info for FLASH chips    */
-
-/* Board support for 1 or 2 flash devices */
-#undef FLASH_PORT_WIDTH32
-#define FLASH_PORT_WIDTH16
-
-#ifdef FLASH_PORT_WIDTH16
-#define FLASH_PORT_WIDTH		ushort
-#define FLASH_PORT_WIDTHV		vu_short
-#define SWAP(x)			__swab16(x)
-#else
-#define FLASH_PORT_WIDTH		ulong
-#define FLASH_PORT_WIDTHV		vu_long
-#define SWAP(x)			__swab32(x)
-#endif
-
-#define FPW	FLASH_PORT_WIDTH
-#define FPWV	FLASH_PORT_WIDTHV
-
-#define mb() __asm__ __volatile__ ("" : : : "memory")
-
-
-/* Flash Organization Structure */
-typedef struct OrgDef {
-	unsigned int sector_number;
-	unsigned int sector_size;
-} OrgDef;
-
-
-/* Flash Organizations */
-OrgDef OrgIntel_28F256L18T[] = {
-	{4, 32 * 1024},				/* 4 * 32kBytes sectors */
-	{255, 128 * 1024},			/* 255 * 128kBytes sectors */
-};
-
-
-/*-----------------------------------------------------------------------
- * Functions
- */
-unsigned long flash_init (void);
-static ulong flash_get_size (FPW * addr, flash_info_t * info);
-static int write_data (flash_info_t * info, ulong dest, FPW data);
-static void flash_get_offsets (ulong base, flash_info_t * info);
-void inline spin_wheel (void);
-void flash_print_info (flash_info_t * info);
-void flash_unprotect_sectors (FPWV * addr);
-int flash_erase (flash_info_t * info, int s_first, int s_last);
-int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt);
-
-/*-----------------------------------------------------------------------
- */
-
-unsigned long flash_init (void)
-{
-	int i;
-	ulong size = 0;
-	for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) {
-		switch (i) {
-		case 0:
-			flash_get_size ((FPW *) PHYS_FLASH_1, &flash_info[i]);
-			flash_get_offsets (PHYS_FLASH_1, &flash_info[i]);
-			break;
-		default:
-			panic ("configured too many flash banks!\n");
-			break;
-		}
-		size += flash_info[i].size;
-	}
-
-	/* Protect monitor and environment sectors
-	 */
-	flash_protect (FLAG_PROTECT_SET,
-			CONFIG_SYS_FLASH_BASE,
-			CONFIG_SYS_FLASH_BASE + monitor_flash_len - 1, &flash_info[0]);
-
-	flash_protect (FLAG_PROTECT_SET,
-			CONFIG_ENV_ADDR,
-			CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, &flash_info[0]);
-
-	return size;
-}
-
-/*-----------------------------------------------------------------------
- */
-static void flash_get_offsets (ulong base, flash_info_t * info)
-{
-	int i;
-
-	if (info->flash_id == FLASH_UNKNOWN) {
-		return;
-	}
-
-	if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) {
-		for (i = 0; i < info->sector_count; i++) {
-			if (i > 255) {
-				info->start[i] = base + (i * 0x8000);
-				info->protect[i] = 0;
-			} else {
-				info->start[i] = base +
-						(i * PHYS_FLASH_SECT_SIZE);
-				info->protect[i] = 0;
-			}
-		}
-	}
-}
-
-/*-----------------------------------------------------------------------
- */
-void flash_print_info (flash_info_t * info)
-{
-	int i;
-
-	if (info->flash_id == FLASH_UNKNOWN) {
-		printf ("missing or unknown FLASH type\n");
-		return;
-	}
-
-	switch (info->flash_id & FLASH_VENDMASK) {
-	case FLASH_MAN_INTEL:
-		printf ("INTEL ");
-		break;
-	default:
-		printf ("Unknown Vendor ");
-		break;
-	}
-
-	switch (info->flash_id & FLASH_TYPEMASK) {
-	case FLASH_28F256L18T:
-		printf ("FLASH 28F256L18T\n");
-		break;
-	default:
-		printf ("Unknown Chip Type\n");
-		break;
-	}
-
-	printf ("  Size: %ld MB in %d Sectors\n",
-			info->size >> 20, info->sector_count);
-
-	printf ("  Sector Start Addresses:");
-	for (i = 0; i < info->sector_count; ++i) {
-		if ((i % 5) == 0)
-			printf ("\n   ");
-		printf (" %08lX%s",
-			info->start[i], info->protect[i] ? " (RO)" : "     ");
-	}
-	printf ("\n");
-	return;
-}
-
-/*
- * The following code cannot be run from FLASH!
- */
-static ulong flash_get_size (FPW * addr, flash_info_t * info)
-{
-	volatile FPW value;
-
-	/* Write auto select command: read Manufacturer ID */
-	addr[0x5555] = (FPW) 0x00AA00AA;
-	addr[0x2AAA] = (FPW) 0x00550055;
-	addr[0x5555] = (FPW) 0x00900090;
-
-	mb ();
-	value = addr[0];
-
-	switch (value) {
-
-	case (FPW) INTEL_MANUFACT:
-		info->flash_id = FLASH_MAN_INTEL;
-		break;
-
-	default:
-		info->flash_id = FLASH_UNKNOWN;
-		info->sector_count = 0;
-		info->size = 0;
-		addr[0] = (FPW) 0x00FF00FF;	/* restore read mode */
-		return (0);		/* no or unknown flash  */
-	}
-
-	mb ();
-	value = addr[1];	/* device ID        */
-	switch (value) {
-
-	case (FPW) (INTEL_ID_28F256L18T):
-		info->flash_id += FLASH_28F256L18T;
-		info->sector_count = 259;
-		info->size = 0x02000000;
-		break;			/* => 32 MB     */
-
-	default:
-		info->flash_id = FLASH_UNKNOWN;
-		break;
-	}
-
-	if (info->sector_count > CONFIG_SYS_MAX_FLASH_SECT) {
-		printf ("** ERROR: sector count %d > max (%d) **\n",
-				info->sector_count, CONFIG_SYS_MAX_FLASH_SECT);
-		info->sector_count = CONFIG_SYS_MAX_FLASH_SECT;
-	}
-
-	addr[0] = (FPW) 0x00FF00FF;	/* restore read mode */
-
-	return (info->size);
-}
-
-
-/* unprotects a sector for write and erase
- * on some intel parts, this unprotects the entire chip, but it
- * wont hurt to call this additional times per sector...
- */
-void flash_unprotect_sectors (FPWV * addr)
-{
-#define PD_FINTEL_WSMS_READY_MASK    0x0080
-
-	*addr = (FPW) 0x00500050;	/* clear status register */
-
-	/* this sends the clear lock bit command */
-	*addr = (FPW) 0x00600060;
-	*addr = (FPW) 0x00D000D0;
-}
-
-
-/*-----------------------------------------------------------------------
- */
-
-int flash_erase (flash_info_t * info, int s_first, int s_last)
-{
-	int flag, prot, sect;
-	ulong type, start;
-	int rcode = 0;
-
-	if ((s_first < 0) || (s_first > s_last)) {
-		if (info->flash_id == FLASH_UNKNOWN) {
-			printf ("- missing\n");
-		} else {
-			printf ("- no sectors to erase\n");
-		}
-		return 1;
-	}
-
-	type = (info->flash_id & FLASH_VENDMASK);
-	if ((type != FLASH_MAN_INTEL)) {
-		printf ("Can't erase unknown flash type %08lx - aborted\n",
-				info->flash_id);
-		return 1;
-	}
-
-	prot = 0;
-	for (sect = s_first; sect <= s_last; ++sect) {
-		if (info->protect[sect]) {
-			prot++;
-		}
-	}
-
-	if (prot) {
-		printf ("- Warning: %d protected sectors will not be erased!\n",
-				prot);
-	} else {
-		printf ("\n");
-	}
-
-	/* Disable interrupts which might cause a timeout here */
-	flag = disable_interrupts ();
-
-	/* Start erase on unprotected sectors */
-	for (sect = s_first; sect <= s_last; sect++) {
-		if (info->protect[sect] == 0) {	/* not protected */
-			FPWV *addr = (FPWV *) (info->start[sect]);
-			FPW status;
-
-			printf ("Erasing sector %2d ... ", sect);
-
-			flash_unprotect_sectors (addr);
-
-			/* arm simple, non interrupt dependent timer */
-			start = get_timer(0);
-
-			*addr = (FPW) 0x00500050;/* clear status register */
-			*addr = (FPW) 0x00200020;/* erase setup */
-			*addr = (FPW) 0x00D000D0;/* erase confirm */
-
-			while (((status =
-				*addr) & (FPW) 0x00800080) !=
-				(FPW) 0x00800080) {
-					if (get_timer(start) >
-					CONFIG_SYS_FLASH_ERASE_TOUT) {
-					printf ("Timeout\n");
-					/* suspend erase     */
-					*addr = (FPW) 0x00B000B0;
-					/* reset to read mode */
-					*addr = (FPW) 0x00FF00FF;
-					rcode = 1;
-					break;
-				}
-			}
-
-			/* clear status register cmd.   */
-			*addr = (FPW) 0x00500050;
-			*addr = (FPW) 0x00FF00FF;/* resest to read mode */
-			printf (" done\n");
-		}
-	}
-
-	if (flag)
-		enable_interrupts();
-
-	return rcode;
-}
-
-/*-----------------------------------------------------------------------
- * Copy memory to flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- * 4 - Flash not identified
- */
-
-int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
-{
-	ulong cp, wp;
-	FPW data;
-	int count, i, l, rc, port_width;
-
-	if (info->flash_id == FLASH_UNKNOWN) {
-		return 4;
-	}
-/* get lower word aligned address */
-#ifdef FLASH_PORT_WIDTH16
-	wp = (addr & ~1);
-	port_width = 2;
-#else
-	wp = (addr & ~3);
-	port_width = 4;
-#endif
-
-	/*
-	 * handle unaligned start bytes
-	 */
-	if ((l = addr - wp) != 0) {
-		data = 0;
-		for (i = 0, cp = wp; i < l; ++i, ++cp) {
-			data = (data << 8) | (*(uchar *) cp);
-		}
-		for (; i < port_width && cnt > 0; ++i) {
-			data = (data << 8) | *src++;
-			--cnt;
-			++cp;
-		}
-		for (; cnt == 0 && i < port_width; ++i, ++cp) {
-			data = (data << 8) | (*(uchar *) cp);
-		}
-
-		if ((rc = write_data (info, wp, SWAP (data))) != 0) {
-			return (rc);
-		}
-		wp += port_width;
-	}
-
-	/*
-	 * handle word aligned part
-	 */
-	count = 0;
-	while (cnt >= port_width) {
-		data = 0;
-		for (i = 0; i < port_width; ++i) {
-			data = (data << 8) | *src++;
-		}
-		if ((rc = write_data (info, wp, SWAP (data))) != 0) {
-			return (rc);
-		}
-		wp += port_width;
-		cnt -= port_width;
-		if (count++ > 0x800) {
-			spin_wheel ();
-			count = 0;
-		}
-	}
-
-	if (cnt == 0) {
-		return (0);
-	}
-
-	/*
-	 * handle unaligned tail bytes
-	 */
-	data = 0;
-	for (i = 0, cp = wp; i < port_width && cnt > 0; ++i, ++cp) {
-		data = (data << 8) | *src++;
-		--cnt;
-	}
-	for (; i < port_width; ++i, ++cp) {
-		data = (data << 8) | (*(uchar *) cp);
-	}
-
-	return (write_data (info, wp, SWAP (data)));
-}
-
-/*-----------------------------------------------------------------------
- * Write a word or halfword to Flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-static int write_data (flash_info_t * info, ulong dest, FPW data)
-{
-	FPWV *addr = (FPWV *) dest;
-	ulong status;
-	int flag, rc = 0;
-	ulong start;
-
-	/* Check if Flash is (sufficiently) erased */
-	if ((*addr & data) != data) {
-		printf ("not erased at %08lx (%x)\n", (ulong) addr, *addr);
-		return (2);
-	}
-	flash_unprotect_sectors (addr);
-	/* Disable interrupts which might cause a timeout here */
-	flag = disable_interrupts ();
-	*addr = (FPW) 0x00400040;	/* write setup */
-	*addr = data;
-
-	/* arm simple, non interrupt dependent timer */
-	start = get_timer(0);
-
-	/* wait while polling the status register */
-	while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) {
-		if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
-			rc = 1;
-			goto done;
-		}
-	}
-done:
-	*addr = (FPW)0x00FF00FF;	/* restore read mode */
-	if (flag)
-		enable_interrupts();
-	return rc;
-}
-
-void inline spin_wheel (void)
-{
-	static int p = 0;
-	static char w[] = "\\/-";
-
-	printf ("\010%c", w[p]);
-	(++p == 3) ? (p = 0) : 0;
-}
diff --git a/board/ti/omap730p2/lowlevel_init.S b/board/ti/omap730p2/lowlevel_init.S
deleted file mode 100644
index 795c495372..0000000000
--- a/board/ti/omap730p2/lowlevel_init.S
+++ /dev/null
@@ -1,379 +0,0 @@
-/*
- * Board specific setup info
- *
- * (C) Copyright 2003-2004
- *
- * Texas Instruments, <www.ti.com>
- * Kshitij Gupta <Kshitij@ti.com>
- *
- * Modified for OMAP 1610 H2 board by Nishant Kamat, Jan 2004
- *
- * Modified for OMAP730 P2 Board by Dave Peverley, MPC-Data Limited
- * (http://www.mpc-data.co.uk)
- *
- * TODO : Tidy up and change to use system register defines
- *        from omap730.h where possible.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <config.h>
-#include <version.h>
-
-#if defined(CONFIG_OMAP730)
-#include <./configs/omap730.h>
-#endif
-
-_TEXT_BASE:
-	.word	CONFIG_SYS_TEXT_BASE	/* sdram load addr from config.mk */
-
-.globl lowlevel_init
-lowlevel_init:
-	/* Save callers address in r11 - r11 must never be modified */
-	mov r11, lr
-
-	/*------------------------------------------------------*
-	 *mask all IRQs by setting all bits in the INTMR default*
-	 *------------------------------------------------------*/
-	mov	r1,	#0xffffffff
-	ldr	r0,	=REG_IHL1_MIR
-	str	r1,	[r0]
-	ldr	r0,	=REG_IHL2_MIR
-	str	r1,	[r0]
-
-	/*------------------------------------------------------*
-	 * Set up ARM CLM registers (IDLECT1)                   *
-	 *------------------------------------------------------*/
-	ldr	r0,	REG_ARM_IDLECT1
-	ldr	r1,	VAL_ARM_IDLECT1
-	str	r1,	[r0]
-
-	/*------------------------------------------------------*
-	 * Set up ARM CLM registers (IDLECT2)		        *
-	 *------------------------------------------------------*/
-	ldr	r0,	REG_ARM_IDLECT2
-	ldr	r1,	VAL_ARM_IDLECT2
-	str	r1,	[r0]
-
-	/*------------------------------------------------------*
-	 * Set up ARM CLM registers (IDLECT3)		        *
-	 *------------------------------------------------------*/
-	ldr	r0,	REG_ARM_IDLECT3
-	ldr	r1,	VAL_ARM_IDLECT3
-	str	r1,	[r0]
-
-
-	mov	r1,	#0x01		/* PER_EN bit */
-	ldr	r0,	REG_ARM_RSTCT2
-	strh	r1,	[r0]		/* CLKM; Peripheral reset. */
-
-	/* Set CLKM to Sync-Scalable	*/
-	/* I supposedly need to enable the dsp clock before switching */
-	mov	r1,	#0x1000
-	ldr	r0,	REG_ARM_SYSST
-	strh	r1,	[r0]
-	mov	r0,	#0x400
-1:
-	subs	r0,	r0,	#0x1	/* wait for any bubbles to finish */
-	bne	1b
-	ldr	r1,	VAL_ARM_CKCTL
-	ldr	r0,	REG_ARM_CKCTL
-	strh	r1,	[r0]
-
-	/* a few nops to let settle */
-	nop
-	nop
-	nop
-	nop
-	nop
-	nop
-	nop
-	nop
-	nop
-	nop
-
-	/* setup DPLL 1 */
-	/* Ramp up the clock to 96Mhz */
-	ldr	r1,	VAL_DPLL1_CTL
-	ldr	r0,	REG_DPLL1_CTL
-	strh	r1,	[r0]
-	ands	r1,	r1,	#0x10	/* Check if PLL is enabled. */
-	beq	lock_end	/* Do not look for lock if BYPASS selected */
-2:
-	ldrh	r1,	[r0]
-	ands	r1,	r1,	#0x01	/*	Check the LOCK bit.*/
-	beq 2b			/*	loop until bit goes hi. */
-lock_end:
-
-	/*------------------------------------------------------*
-	 * Turn off the watchdog during init...			*
-	 *------------------------------------------------------*/
-	ldr	r0,	REG_WATCHDOG
-	ldr	r1,	WATCHDOG_VAL1
-	str	r1,	[r0]
-	ldr	r1,	WATCHDOG_VAL2
-	str	r1,	[r0]
-	ldr	r0,	REG_WSPRDOG
-	ldr	r1,	WSPRDOG_VAL1
-	str	r1,	[r0]
-	ldr	r0,	REG_WWPSDOG
-
-watch1Wait:
-	ldr	r1,	[r0]
-	tst	r1,	#0x10
-	bne	watch1Wait
-
-	ldr	r0,	REG_WSPRDOG
-	ldr	r1,	WSPRDOG_VAL2
-	str	r1,	[r0]
-	ldr	r0,	REG_WWPSDOG
-watch2Wait:
-	ldr	r1,	[r0]
-	tst	r1,	#0x10
-	bne	watch2Wait
-
-	/* Set memory timings corresponding to the new clock speed */
-
-	/* Check execution location to determine current execution location
-	 * and branch to appropriate initialization code.
-	 */
-	/* Compare physical SDRAM base & current execution location. */
-	and     r0, pc, #0xF0000000
-	/* Compare. */
-	cmp     r0, #0
-	/* Skip over EMIF-fast initialization if running from SDRAM. */
-	bne	skip_sdram
-
-	/*
-	* Delay for SDRAM initialization.
-	*/
-	mov	r3,	#0x1800		/* value should be checked */
-3:
-	subs	r3,	r3,	#0x1	/* Decrement count */
-	bne	3b
-
-	ldr	r0,	REG_SDRAM_CONFIG
-	ldr	r1,	SDRAM_CONFIG_VAL
-	str	r1,	[r0]
-
-	ldr	r0,	REG_SDRAM_MRS_LEGACY
-	ldr	r1,	SDRAM_MRS_VAL
-	str	r1,	[r0]
-
-skip_sdram:
-
-common_tc:
-	/* slow interface */
-	ldr	r1,	VAL_TC_EMIFS_CS0_CONFIG
-	ldr	r0,	REG_TC_EMIFS_CS0_CONFIG
-	str	r1,	[r0] /* Chip Select 0 */
-
-	ldr	r1,	VAL_TC_EMIFS_CS1_CONFIG
-	ldr	r0,	REG_TC_EMIFS_CS1_CONFIG
-	str	r1,	[r0] /* Chip Select 1 */
-	ldr	r1,	VAL_TC_EMIFS_CS2_CONFIG
-	ldr	r0,	REG_TC_EMIFS_CS2_CONFIG
-	str	r1,	[r0] /* Chip Select 2 */
-	ldr	r1,	VAL_TC_EMIFS_CS3_CONFIG
-	ldr	r0,	REG_TC_EMIFS_CS3_CONFIG
-	str	r1,	[r0] /* Chip Select 3 */
-
-	/* 48MHz clock request for UART1 */
-	ldr	r1,	PERSEUS2_CONFIG_BASE
-	ldrh	r0,	[r1, #CONFIG_PCC_CONF]
-	orr	r0,	r0, #CONF_MOD_UART1_CLK_MODE_R
-	strh	r0,	[r1, #CONFIG_PCC_CONF]
-
-	/* Initialize public and private rheas
-	 *  - set access factor 2 on both rhea / strobe
-	 *  - disable write buffer on strb0, enable write buffer on strb1
-	 */
-
-	ldr	R0,	REG_RHEA_PUB_CTL
-	ldr	R1,	REG_RHEA_PRIV_CTL
-	ldr	R2,	VAL_RHEA_CTL
-	strh	R2,	[R0]
-	strh	R2,	[R1]
-	mov	R3,	#2          /* disable write buffer on strb0, enable write buffer on strb1 */
-	strh	R3,	[R0, #0x08]	/* arm rhea control reg */
-	strh	R3,	[R1, #0x08]
-
-	/* enable IRQ and FIQ */
-
-	mrs	r4,	CPSR
-	bic	r4,	r4, #IRQ_MASK
-	bic	r4,	r4, #FIQ_MASK
-	msr	CPSR,	r4
-
-	/* set TAP CONF to TRI EMULATION */
-
-	ldr	r1,	[r0, #CONFIG_MODE2]
-	bic	r1,	r1, #0x18
-	orr	r1,	r1, #0x10
-	str	r1,	[r0, #CONFIG_MODE2]
-
-	/* set tdbgen to 1 */
-
-	ldr	r0,	PERSEUS2_CONFIG_BASE
-	ldr	r1,	[r0, #CONFIG_MODE1]
-	mov	r2,	#0x10000
-	orr	r1,	r1, r2
-	str	r1,	[r0, #CONFIG_MODE1]
-
-#ifdef CONFIG_P2_OMAP1610
-	/* inserting additional 2 clock cycle hold time for LAN */
-	ldr     r0,     REG_TC_EMIFS_CS1_ADVANCED
-	ldr	r1,     VAL_TC_EMIFS_CS1_ADVANCED
-	str     r1,     [r0]
-#endif
-	/* Start MPU Timer 1 */
-	ldr	r0,	REG_MPU_LOAD_TIMER
-	ldr	r1,	VAL_MPU_LOAD_TIMER
-	str	r1,	[r0]
-
-	ldr	r0,	REG_MPU_CNTL_TIMER
-	ldr	r1,	VAL_MPU_CNTL_TIMER
-	str	r1,	[r0]
-
-	/* back to arch calling code */
-	mov	pc,	r11
-
-	/* the literal pools origin */
-	.ltorg
-
-REG_TC_EMIFS_CONFIG:		/* 32 bits */
-	.word 0xfffecc0c
-REG_TC_EMIFS_CS0_CONFIG:	/* 32 bits */
-	.word 0xfffecc10
-REG_TC_EMIFS_CS1_CONFIG:	/* 32 bits */
-	.word 0xfffecc14
-REG_TC_EMIFS_CS2_CONFIG:	/* 32 bits */
-	.word 0xfffecc18
-REG_TC_EMIFS_CS3_CONFIG:	/* 32 bits */
-	.word 0xfffecc1c
-
-#ifdef CONFIG_P2_OMAP730
-REG_TC_EMIFS_CS1_ADVANCED:	/* 32 bits */
-	.word 0xfffecc54
-#endif
-
-/* MPU clock/reset/power mode control registers */
-REG_ARM_CKCTL:			/* 16 bits */
-	.word 0xfffece00
-
-REG_ARM_IDLECT3:		/* 16 bits */
-	.word 0xfffece24
-REG_ARM_IDLECT2:		/* 16 bits */
-	.word 0xfffece08
-REG_ARM_IDLECT1:		/* 16 bits */
-	.word 0xfffece04
-
-REG_ARM_RSTCT2:			/* 16 bits */
-	.word 0xfffece14
-REG_ARM_SYSST:			/* 16 bits */
-	.word 0xfffece18
-/* DPLL control registers */
-REG_DPLL1_CTL:			/* 16 bits */
-	.word 0xfffecf00
-
-/* Watch Dog register */
-/* secure watchdog stop */
-REG_WSPRDOG:
-	.word 0xfffeb048
-/* watchdog write pending */
-REG_WWPSDOG:
-	.word 0xfffeb034
-
-WSPRDOG_VAL1:
-	.word 0x0000aaaa
-WSPRDOG_VAL2:
-	.word 0x00005555
-
-/* SDRAM config is: auto refresh enabled, 16 bit 4 bank,
- counter @8192 rows, 10 ns, 8 burst */
-REG_SDRAM_CONFIG:
-	.word 0xfffecc20
-
-REG_SDRAM_MRS_LEGACY:
-	.word 0xfffecc24
-
-REG_WATCHDOG:
-	.word 0xfffec808
-
-REG_MPU_LOAD_TIMER:
-	.word 0xfffec504
-REG_MPU_CNTL_TIMER:
-	.word 0xfffec500
-
-/* Public and private rhea bridge registers definition */
-
-REG_RHEA_PUB_CTL:
-	.word 0xFFFECA00
-
-REG_RHEA_PRIV_CTL:
-	.word 0xFFFED300
-
-/* EMIFF SDRAM Configuration register
-   - self refresh disable
-   - auto refresh enabled
-   - SDRAM type 64 Mb, 16 bits bus 4 banks
-   - power down enabled
-   - SDRAM clock disabled
- */
-SDRAM_CONFIG_VAL:
-	.word 0x0C017DF4
-
-/* Burst full page length ; cas latency = 3 */
-SDRAM_MRS_VAL:
-	.word 0x00000037
-
-VAL_ARM_CKCTL:
-	.word 0x6505
-VAL_DPLL1_CTL:
-	.word 0x3412
-
-#ifdef CONFIG_P2_OMAP730
-VAL_TC_EMIFS_CS0_CONFIG:
-	.word 0x0000FFF3
-VAL_TC_EMIFS_CS1_CONFIG:
-	.word 0x00004278
-VAL_TC_EMIFS_CS2_CONFIG:
-	.word 0x00004278
-VAL_TC_EMIFS_CS3_CONFIG:
-	.word 0x00004278
-VAL_TC_EMIFS_CS1_ADVANCED:
-	.word 0x00000022
-#endif
-
-VAL_ARM_IDLECT1:
-	.word 0x00000400
-VAL_ARM_IDLECT2:
-	.word 0x00000886
-VAL_ARM_IDLECT3:
-	.word 0x00000015
-
-WATCHDOG_VAL1:
-	.word 0x000000f5
-WATCHDOG_VAL2:
-	.word 0x000000a0
-
-VAL_MPU_LOAD_TIMER:
-	.word 0xffffffff
-VAL_MPU_CNTL_TIMER:
-	.word 0xffffffa1
-
-VAL_RHEA_CTL:
-	.word			0xFF22
-
-/* Config Register vals */
-PERSEUS2_CONFIG_BASE:
-	.word			0xFFFE1000
-
-.equ	CONFIG_PCC_CONF,	0xB4
-.equ	CONFIG_MODE1,		0x10
-.equ	CONFIG_MODE2,		0x14
-.equ	CONF_MOD_UART1_CLK_MODE_R,	0x0A
-
-/* misc values */
-.equ	IRQ_MASK,		0x80           /* IRQ mask value */
-.equ	FIQ_MASK,		0x40           /* FIQ mask value */
diff --git a/board/ti/omap730p2/omap730p2.c b/board/ti/omap730p2/omap730p2.c
deleted file mode 100644
index 554019c207..0000000000
--- a/board/ti/omap730p2/omap730p2.c
+++ /dev/null
@@ -1,255 +0,0 @@
-/*
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- *
- * (C) Copyright 2002
- * David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
- *
- * (C) Copyright 2003
- * Texas Instruments, <www.ti.com>
- * Kshitij Gupta <Kshitij@ti.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <netdev.h>
-#if defined(CONFIG_OMAP730)
-#include <./configs/omap730.h>
-#endif
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int test_boot_mode(void);
-void spin_up_leds(void);
-void flash__init (void);
-void ether__init (void);
-void set_muxconf_regs (void);
-void peripheral_power_enable (void);
-
-#define FLASH_ON_CS0	1
-#define FLASH_ON_CS3	0
-
-static inline void delay (unsigned long loops)
-{
-	__asm__ volatile ("1:\n"
-			  "subs %0, %1, #1\n"
-			  "bne 1b":"=r" (loops):"0" (loops));
-}
-
-int test_boot_mode(void)
-{
-	/* Check for CS0 and CS3 address decode swapping */
-	if (*((volatile int *)EMIFS_CONFIG) & 0x00000002)
-		return(FLASH_ON_CS3);
-	else
-		return(FLASH_ON_CS0);
-}
-
-/* Toggle backup LED indication */
-void toggle_backup_led(void)
-{
-	static int  backupLEDState = 0;	 /* Init variable so that the LED will be ON the first time */
-	volatile unsigned int *IOConfReg;
-
-
-	IOConfReg = (volatile unsigned int *) ((unsigned int) OMAP730_GPIO_BASE_5 + GPIO_DATA_OUTPUT);
-
-	if (backupLEDState != 0) {
-		*IOConfReg &= (0xFFFFEFFF);
-		backupLEDState = 0;
-	} else {
-		*IOConfReg |= (0x00001000);
-		backupLEDState = 1;
-	}
-}
-
-/*
- * Miscellaneous platform dependent initialisations
- */
-
-int board_init (void)
-{
-	/* arch number of OMAP 730 P2 Board - Same as the Innovator! */
-	gd->bd->bi_arch_number = MACH_TYPE_OMAP_PERSEUS2;
-
-	/* adress of boot parameters */
-	gd->bd->bi_boot_params = 0x10000100;
-
-	/* Configure MUX settings */
-	set_muxconf_regs ();
-
-	peripheral_power_enable ();
-
-	/* Backup LED indication via GPIO_140 -> Red led if MUX correctly setup */
-	toggle_backup_led();
-
-	/* Hold GSM in reset until needed */
-	*((volatile unsigned short *)M_CTL) &= ~1;
-
-	/*
-	 *  CSx timings, GPIO Mux ... setup
-	 */
-
-	/* Flash: CS0 timings setup */
-	*((volatile unsigned int *) FLASH_CFG_0) = 0x0000fff3;
-	*((volatile unsigned int *) FLASH_ACFG_0_1) = 0x00000088;
-
-	/* Ethernet support trough the debug board */
-	/* CS1 timings setup */
-	*((volatile unsigned int *) FLASH_CFG_1) = 0x0000fff3;
-	*((volatile unsigned int *) FLASH_ACFG_0_1) = 0x00000000;
-
-	/* this speeds up your boot a quite a bit.  However to make it
-	 *  work, you need make sure your kernel startup flush bug is fixed.
-	 *  ... rkw ...
-	 */
-	icache_enable ();
-
-	flash__init ();
-	ether__init ();
-
-	return 0;
-}
-
-/******************************
- Routine:
- Description:
-******************************/
-void flash__init (void)
-{
-	unsigned int regval;
-
-	regval = *((volatile unsigned int *) EMIFS_CONFIG);
-	/* Turn off write protection for flash devices. */
-	regval = regval | 0x0001;
-	*((volatile unsigned int *) EMIFS_CONFIG) = regval;
-}
-
-/*************************************************************
- Routine:ether__init
- Description: take the Ethernet controller out of reset and wait
-			   for the EEPROM load to complete.
-*************************************************************/
-void ether__init (void)
-{
-#define LAN_RESET_REGISTER 0x0400001c
-
-	*((volatile unsigned short *) LAN_RESET_REGISTER) = 0x0000;
-	do {
-		*((volatile unsigned short *) LAN_RESET_REGISTER) = 0x0001;
-		udelay (100);
-	} while (*((volatile unsigned short *) LAN_RESET_REGISTER) != 0x0001);
-
-	do {
-		*((volatile unsigned short *) LAN_RESET_REGISTER) = 0x0000;
-		udelay (100);
-	} while (*((volatile unsigned short *) LAN_RESET_REGISTER) != 0x0000);
-
-#define ETH_CONTROL_REG 0x0400030b
-
-	*((volatile unsigned char *) ETH_CONTROL_REG) &= ~0x01;
-	udelay (100);
-}
-
-/******************************
- Routine:
- Description:
-******************************/
-int dram_init (void)
-{
-	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
-	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
-
-	return 0;
-}
-
-/******************************************************
- Routine: set_muxconf_regs
- Description: Setting up the configuration Mux registers
-			  specific to the hardware
-*******************************************************/
-void set_muxconf_regs (void)
-{
-	volatile unsigned int *MuxConfReg;
-	/* set each registers to its reset value; */
-
-	/*
-	 *  Backup LED Indication
-	 */
-
-	/* Configure MUXed pin. Mode 6: GPIO_140 */
-	MuxConfReg = (volatile unsigned int *) (PERSEUS2_IO_CONF10);
-	*MuxConfReg &= (0xFFFFFF1F);	     /* Clear D_MPU_LPG1 */
-	*MuxConfReg |= 0x000000C0;	     /* Set D_MPU_LPG1 to 0x6 */
-
-	/* Configure GPIO_140 as output */
-	MuxConfReg = (volatile unsigned int *) ((unsigned int) OMAP730_GPIO_BASE_5 + GPIO_DIRECTION_CONTROL);
-	*MuxConfReg &= (0xFFFFEFFF);	     /* Clear direction (output) for GPIO 140 */
-
-	/*
-	 * Configure GPIOs for battery charge & feedback
-	 */
-
-	/* Configure MUXed pin. Mode 6: GPIO_35 */
-	MuxConfReg = (volatile unsigned int *) (PERSEUS2_IO_CONF3);
-	*MuxConfReg &= 0xFFFFFFF1;	     /* Clear M_CLK_OUT */
-	*MuxConfReg |= 0x0000000C;	     /* Set M_CLK_OUT = 0x6 (GPIOs) */
-
-	/* Configure MUXed pin. Mode 6: GPIO_72,73,74 */
-	MuxConfReg = (volatile unsigned int *) (PERSEUS2_IO_CONF5);
-	*MuxConfReg &= 0xFFFF1FFF;	     /* Clear D_DDR */
-	*MuxConfReg |= 0x0000C000;	     /* Set D_DDR = 0x6 (GPIOs) */
-
-	MuxConfReg = (volatile unsigned int *) ((unsigned int) OMAP730_GPIO_BASE_3 + GPIO_DIRECTION_CONTROL);
-	*MuxConfReg |= 0x00000100;	     /* Configure GPIO_72 as input */
-	*MuxConfReg &= 0xFFFFFDFF;	     /* Configure GPIO_73 as output	*/
-
-	/*
-	 * Allow battery charge
-	 */
-
-	MuxConfReg = (volatile unsigned int *) ((unsigned int) OMAP730_GPIO_BASE_3 + GPIO_DATA_OUTPUT);
-	*MuxConfReg &= (0xFFFFFDFF);	     /* Clear GPIO_73 pin */
-
-	/*
-	 * Configure MPU_EXT_NIRQ IO in IO_CONF9 register,
-	 * It is used as the Ethernet controller interrupt
-	 */
-	MuxConfReg = (volatile unsigned int *) (PERSEUS2_IO_CONF9);
-	*MuxConfReg &= 0x1FFFFFFF;
-}
-
-/******************************************************
- Routine: peripheral_power_enable
- Description: Enable the power for UART1
-*******************************************************/
-void peripheral_power_enable (void)
-{
-	volatile unsigned int *MuxConfReg;
-
-
-	/* Set up pins used by UART */
-
-	/* Start UART clock (48MHz) */
-	MuxConfReg = (volatile unsigned int *) (PERSEUS_PCC_CONF_REG);
-	*MuxConfReg &= (0xFFFFFFF7);
-	*MuxConfReg |= (0x00000008);
-
-	/* Get the UART pin in mode0  */
-	MuxConfReg = (volatile unsigned int *) (PERSEUS2_IO_CONF3);
-	*MuxConfReg &= (0xFF1FFFFF);
-	*MuxConfReg &= (0xF1FFFFFF);
-}
-
-#ifdef CONFIG_CMD_NET
-int board_eth_init(bd_t *bis)
-{
-	int rc = 0;
-#ifdef CONFIG_LAN91C96
-	rc = lan91c96_initialize(0, CONFIG_LAN91C96_BASE);
-#endif
-	return rc;
-}
-#endif
diff --git a/board/ti/panda/Makefile b/board/ti/panda/Makefile
index 1e489d20b6..c89f80d806 100644
--- a/board/ti/panda/Makefile
+++ b/board/ti/panda/Makefile
@@ -5,23 +5,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	:= panda.o
-
-SRCS	:= $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	:= panda.o
diff --git a/board/ti/panda/panda.c b/board/ti/panda/panda.c
index bc3c29220e..5ab6db98ac 100644
--- a/board/ti/panda/panda.c
+++ b/board/ti/panda/panda.c
@@ -123,6 +123,66 @@ int get_board_revision(void)
 }
 
 /**
+ * is_panda_es_rev_b3() - Detect if we are running on rev B3 of panda board ES
+ *
+ *
+ * Detect if we are running on B3 version of ES panda board,
+ * This can be done by reading the level of GPIO 171 and checking the
+ * processor revisions.
+ * GPIO171: 1 => Panda ES Rev B3
+ *
+ * Return : return 1 if Panda ES Rev B3 , else return 0
+ */
+u8 is_panda_es_rev_b3(void)
+{
+        int processor_rev = omap_revision();
+        int ret = 0;
+
+        if ((processor_rev >= OMAP4460_ES1_0 &&
+             processor_rev <= OMAP4460_ES1_1)) {
+
+                /* Setup the mux for the common board ID pins (gpio 171) */
+                writew((IEN | M3),
+			(*ctrl)->control_padconf_core_base + UNIPRO_TX0);
+
+                /* if processor_rev is panda ES and GPIO171 is 1,it is rev b3 */
+                ret = gpio_get_value(PANDA_BOARD_ID_2_GPIO);
+        }
+        return ret;
+}
+
+#ifdef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
+/*
+ * emif_get_reg_dump() - emif_get_reg_dump strong function
+ *
+ * @emif_nr - emif base
+ * @regs - reg dump of timing values
+ *
+ * Strong function to override emif_get_reg_dump weak function in sdram_elpida.c
+ */
+void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs)
+{
+	u32 omap4_rev = omap_revision();
+
+	/* Same devices and geometry on both EMIFs */
+	if (omap4_rev == OMAP4430_ES1_0)
+		*regs = &emif_regs_elpida_380_mhz_1cs;
+	else if (omap4_rev == OMAP4430_ES2_0)
+		*regs = &emif_regs_elpida_200_mhz_2cs;
+	else if (omap4_rev == OMAP4430_ES2_3)
+		*regs = &emif_regs_elpida_400_mhz_1cs;
+	else if (omap4_rev < OMAP4470_ES1_0) {
+		if(is_panda_es_rev_b3())
+			*regs = &emif_regs_elpida_400_mhz_1cs;
+		else
+			*regs = &emif_regs_elpida_400_mhz_2cs;
+	}
+	else
+		*regs = &emif_regs_elpida_400_mhz_1cs;
+}
+#endif
+
+/**
  * @brief misc_init_r - Configure Panda board specific configurations
  * such as power configurations, ethernet initialization as phase2 of
  * boot sequence
@@ -224,36 +284,6 @@ void set_muxconf_regs_essential(void)
 			   sizeof(struct pad_conf_entry));
 }
 
-void set_muxconf_regs_non_essential(void)
-{
-	do_set_mux((*ctrl)->control_padconf_core_base,
-		   core_padconf_array_non_essential,
-		   sizeof(core_padconf_array_non_essential) /
-		   sizeof(struct pad_conf_entry));
-
-	if (omap_revision() < OMAP4460_ES1_0)
-		do_set_mux((*ctrl)->control_padconf_core_base,
-			   core_padconf_array_non_essential_4430,
-			   sizeof(core_padconf_array_non_essential_4430) /
-			   sizeof(struct pad_conf_entry));
-	else
-		do_set_mux((*ctrl)->control_padconf_core_base,
-			   core_padconf_array_non_essential_4460,
-			   sizeof(core_padconf_array_non_essential_4460) /
-			   sizeof(struct pad_conf_entry));
-
-	do_set_mux((*ctrl)->control_padconf_wkup_base,
-		   wkup_padconf_array_non_essential,
-		   sizeof(wkup_padconf_array_non_essential) /
-		   sizeof(struct pad_conf_entry));
-
-	if (omap_revision() < OMAP4460_ES1_0)
-		do_set_mux((*ctrl)->control_padconf_wkup_base,
-			   wkup_padconf_array_non_essential_4430,
-			   sizeof(wkup_padconf_array_non_essential_4430) /
-			   sizeof(struct pad_conf_entry));
-}
-
 #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_GENERIC_MMC)
 int board_mmc_init(bd_t *bis)
 {
@@ -269,7 +299,8 @@ static struct omap_usbhs_board_data usbhs_bdata = {
 	.port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED,
 };
 
-int ehci_hcd_init(int index, struct ehci_hccr **hccr, struct ehci_hcor **hcor)
+int ehci_hcd_init(int index, enum usb_init_type init,
+		struct ehci_hccr **hccr, struct ehci_hcor **hcor)
 {
 	int ret;
 	unsigned int utmi_clk;
@@ -279,7 +310,7 @@ int ehci_hcd_init(int index, struct ehci_hccr **hccr, struct ehci_hcor **hcor)
 	utmi_clk |= HSUSBHOST_CLKCTRL_CLKSEL_UTMI_P1_MASK;
 	sr32((void *)CM_L3INIT_HSUSBHOST_CLKCTRL, 0, 32, utmi_clk);
 
-	ret = omap_ehci_hcd_init(&usbhs_bdata, hccr, hcor);
+	ret = omap_ehci_hcd_init(index, &usbhs_bdata, hccr, hcor);
 	if (ret < 0)
 		return ret;
 
diff --git a/board/ti/panda/panda_mux_data.h b/board/ti/panda/panda_mux_data.h
index fb83eac9be..53c7080979 100644
--- a/board/ti/panda/panda_mux_data.h
+++ b/board/ti/panda/panda_mux_data.h
@@ -84,190 +84,4 @@ const struct pad_conf_entry wkup_padconf_array_essential_4460[] = {
 
 };
 
-const struct pad_conf_entry core_padconf_array_non_essential[] = {
-	{GPMC_AD8, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M3)},	/* gpio_32 */
-	{GPMC_AD9, (PTU | IEN | M3)},					/* gpio_33 */
-	{GPMC_AD10, (PTU | IEN | M3)},					/* gpio_34 */
-	{GPMC_AD11, (PTU | IEN | M3)},					/* gpio_35 */
-	{GPMC_AD12, (PTU | IEN | M3)},					/* gpio_36 */
-	{GPMC_AD13, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)},	/* gpio_37 */
-	{GPMC_AD14, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)},	/* gpio_38 */
-	{GPMC_AD15, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)},	/* gpio_39 */
-	{GPMC_A16, (M3)},						/* gpio_40 */
-	{GPMC_A17, (PTD | M3)},						/* gpio_41 */
-	{GPMC_A18, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)},	/* kpd_row6 */
-	{GPMC_A19, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)},	/* kpd_row7 */
-	{GPMC_A20, (IEN | M3)},						/* gpio_44 */
-	{GPMC_A21, (M3)},						/* gpio_45 */
-	{GPMC_A22, (M3)},						/* gpio_46 */
-	{GPMC_A23, (OFF_EN | OFF_PD | OFF_IN | M1)},			/* kpd_col7 */
-	{GPMC_A24, (PTD | M3)},						/* gpio_48 */
-	{GPMC_A25, (PTD | M3)},						/* gpio_49 */
-	{GPMC_NCS0, (M3)},						/* gpio_50 */
-	{GPMC_NCS1, (IEN | M3)},					/* gpio_51 */
-	{GPMC_NCS2, (IEN | M3)},					/* gpio_52 */
-	{GPMC_NCS3, (IEN | M3)},					/* gpio_53 */
-	{GPMC_NWP, (M3)},						/* gpio_54 */
-	{GPMC_CLK, (PTD | M3)},						/* gpio_55 */
-	{GPMC_NADV_ALE, (M3)},						/* gpio_56 */
-	{GPMC_NBE0_CLE, (M3)},						/* gpio_59 */
-	{GPMC_NBE1, (PTD | M3)},					/* gpio_60 */
-	{GPMC_WAIT0, (PTU | IEN | M3)},					/* gpio_61 */
-	{C2C_DATA11, (PTD | M3)},					/* gpio_100 */
-	{C2C_DATA12, (PTU | IEN | M3)},					/* gpio_101 */
-	{C2C_DATA13, (PTD | M3)},					/* gpio_102 */
-	{C2C_DATA14, (M1)},						/* dsi2_te0 */
-	{C2C_DATA15, (PTD | M3)},					/* gpio_104 */
-	{HDMI_HPD, (M0)},						/* hdmi_hpd */
-	{HDMI_CEC, (M0)},						/* hdmi_cec */
-	{HDMI_DDC_SCL, (PTU | M0)},					/* hdmi_ddc_scl */
-	{HDMI_DDC_SDA, (PTU | IEN | M0)},				/* hdmi_ddc_sda */
-	{CSI21_DX0, (IEN | M0)},					/* csi21_dx0 */
-	{CSI21_DY0, (IEN | M0)},					/* csi21_dy0 */
-	{CSI21_DX1, (IEN | M0)},					/* csi21_dx1 */
-	{CSI21_DY1, (IEN | M0)},					/* csi21_dy1 */
-	{CSI21_DX2, (IEN | M0)},					/* csi21_dx2 */
-	{CSI21_DY2, (IEN | M0)},					/* csi21_dy2 */
-	{CSI21_DX3, (PTD | M7)},					/* csi21_dx3 */
-	{CSI21_DY3, (PTD | M7)},					/* csi21_dy3 */
-	{CSI21_DX4, (PTD | OFF_EN | OFF_PD | OFF_IN | M7)},		/* csi21_dx4 */
-	{CSI21_DY4, (PTD | OFF_EN | OFF_PD | OFF_IN | M7)},		/* csi21_dy4 */
-	{CSI22_DX0, (IEN | M0)},					/* csi22_dx0 */
-	{CSI22_DY0, (IEN | M0)},					/* csi22_dy0 */
-	{CSI22_DX1, (IEN | M0)},					/* csi22_dx1 */
-	{CSI22_DY1, (IEN | M0)},					/* csi22_dy1 */
-	{CAM_SHUTTER, (OFF_EN | OFF_PD | OFF_OUT_PTD | M0)},		/* cam_shutter */
-	{CAM_STROBE, (OFF_EN | OFF_PD | OFF_OUT_PTD | M0)},		/* cam_strobe */
-	{CAM_GLOBALRESET, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)},	/* gpio_83 */
-	{ABE_MCBSP2_DR, (IEN | OFF_EN | OFF_OUT_PTD | M0)},		/* abe_mcbsp2_dr */
-	{ABE_MCBSP2_DX, (OFF_EN | OFF_OUT_PTD | M0)},			/* abe_mcbsp2_dx */
-	{ABE_MCBSP2_FSX, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* abe_mcbsp2_fsx */
-	{ABE_MCBSP1_CLKX, (IEN | M0)},					/* abe_mcbsp1_clkx */
-	{ABE_MCBSP1_DR, (IEN | M0)},					/* abe_mcbsp1_dr */
-	{ABE_MCBSP1_DX, (OFF_EN | OFF_OUT_PTD | M0)},			/* abe_mcbsp1_dx */
-	{ABE_MCBSP1_FSX, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* abe_mcbsp1_fsx */
-	{ABE_PDM_UL_DATA, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* abe_pdm_ul_data */
-	{ABE_PDM_DL_DATA, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* abe_pdm_dl_data */
-	{ABE_PDM_FRAME, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* abe_pdm_frame */
-	{ABE_PDM_LB_CLK, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* abe_pdm_lb_clk */
-	{ABE_CLKS, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* abe_clks */
-	{ABE_DMIC_CLK1, (M0)},						/* abe_dmic_clk1 */
-	{ABE_DMIC_DIN1, (IEN | M0)},					/* abe_dmic_din1 */
-	{ABE_DMIC_DIN2, (PTU | IEN | M3)},				/* gpio_121 */
-	{ABE_DMIC_DIN3, (IEN | M0)},					/* abe_dmic_din3 */
-	{UART2_CTS, (PTU | IEN | M7)},					/* uart2_cts */
-	{UART2_RTS, (M7)},						/* uart2_rts */
-	{UART2_RX, (PTU | IEN | M7)},					/* uart2_rx */
-	{UART2_TX, (M7)},						/* uart2_tx */
-	{HDQ_SIO, (M3)},						/* gpio_127 */
-	{MCSPI1_CLK, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},		/* mcspi1_clk */
-	{MCSPI1_SOMI, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},		/* mcspi1_somi */
-	{MCSPI1_SIMO, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},		/* mcspi1_simo */
-	{MCSPI1_CS0, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* mcspi1_cs0 */
-	{MCSPI1_CS1, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M3)},	/* mcspi1_cs1 */
-	{MCSPI1_CS2, (PTU | OFF_EN | OFF_OUT_PTU | M3)},		/* gpio_139 */
-	{MCSPI1_CS3, (PTU | IEN | M3)},					/* gpio_140 */
-	{SDMMC5_CLK, (PTU | IEN | OFF_EN | OFF_OUT_PTD | M0)},		/* sdmmc5_clk */
-	{SDMMC5_CMD, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* sdmmc5_cmd */
-	{SDMMC5_DAT0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* sdmmc5_dat0 */
-	{SDMMC5_DAT1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* sdmmc5_dat1 */
-	{SDMMC5_DAT2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* sdmmc5_dat2 */
-	{SDMMC5_DAT3, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* sdmmc5_dat3 */
-	{MCSPI4_CLK, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},		/* mcspi4_clk */
-	{MCSPI4_SIMO, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},		/* mcspi4_simo */
-	{MCSPI4_SOMI, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},		/* mcspi4_somi */
-	{MCSPI4_CS0, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* mcspi4_cs0 */
-	{UART4_RX, (IEN | M0)},						/* uart4_rx */
-	{UART4_TX, (M0)},						/* uart4_tx */
-	{USBB2_ULPITLL_CLK, (IEN | M3)},				/* gpio_157 */
-	{USBB2_ULPITLL_STP, (IEN | M5)},				/* dispc2_data23 */
-	{USBB2_ULPITLL_DIR, (IEN | M5)},				/* dispc2_data22 */
-	{USBB2_ULPITLL_NXT, (IEN | M5)},				/* dispc2_data21 */
-	{USBB2_ULPITLL_DAT0, (IEN | M5)},				/* dispc2_data20 */
-	{USBB2_ULPITLL_DAT1, (IEN | M5)},				/* dispc2_data19 */
-	{USBB2_ULPITLL_DAT2, (IEN | M5)},				/* dispc2_data18 */
-	{USBB2_ULPITLL_DAT3, (IEN | M5)},				/* dispc2_data15 */
-	{USBB2_ULPITLL_DAT4, (IEN | M5)},				/* dispc2_data14 */
-	{USBB2_ULPITLL_DAT5, (IEN | M5)},				/* dispc2_data13 */
-	{USBB2_ULPITLL_DAT6, (IEN | M5)},				/* dispc2_data12 */
-	{USBB2_ULPITLL_DAT7, (IEN | M5)},				/* dispc2_data11 */
-	{USBB2_HSIC_DATA, (PTD | OFF_EN | OFF_OUT_PTU | M3)},		/* gpio_169 */
-	{USBB2_HSIC_STROBE, (PTD | OFF_EN | OFF_OUT_PTU | M3)},		/* gpio_170 */
-	{UNIPRO_TX0, (PTD | IEN | M3)},					/* gpio_171 */
-	{UNIPRO_TY0, (OFF_EN | OFF_PD | OFF_IN | M1)},			/* kpd_col1 */
-	{UNIPRO_TX1, (OFF_EN | OFF_PD | OFF_IN | M1)},			/* kpd_col2 */
-	{UNIPRO_TY1, (OFF_EN | OFF_PD | OFF_IN | M1)},			/* kpd_col3 */
-	{UNIPRO_TX2, (PTU | IEN | M3)},					/* gpio_0 */
-	{UNIPRO_RX0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)},	/* kpd_row0 */
-	{UNIPRO_RY0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)},	/* kpd_row1 */
-	{UNIPRO_RX1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)},	/* kpd_row2 */
-	{UNIPRO_RY1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)},	/* kpd_row3 */
-	{UNIPRO_RX2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)},	/* kpd_row4 */
-	{UNIPRO_RY2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)},	/* kpd_row5 */
-	{USBA0_OTG_CE, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M0)},	/* usba0_otg_ce */
-	{USBA0_OTG_DP, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},		/* usba0_otg_dp */
-	{USBA0_OTG_DM, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},		/* usba0_otg_dm */
-	{FREF_CLK1_OUT, (M0)},						/* fref_clk1_out */
-	{SYS_NIRQ1, (PTU | IEN | M0)},					/* sys_nirq1 */
-	{SYS_NIRQ2, (PTU | IEN | M0)},					/* sys_nirq2 */
-	{SYS_BOOT0, (PTU | IEN | M3)},					/* gpio_184 */
-	{SYS_BOOT1, (M3)},						/* gpio_185 */
-	{SYS_BOOT2, (PTD | IEN | M3)},					/* gpio_186 */
-	{SYS_BOOT3, (M3)},						/* gpio_187 */
-	{SYS_BOOT4, (M3)},						/* gpio_188 */
-	{SYS_BOOT5, (PTD | IEN | M3)},					/* gpio_189 */
-	{DPM_EMU0, (IEN | M0)},						/* dpm_emu0 */
-	{DPM_EMU1, (IEN | M0)},						/* dpm_emu1 */
-	{DPM_EMU2, (IEN | M0)},						/* dpm_emu2 */
-	{DPM_EMU3, (IEN | M5)},						/* dispc2_data10 */
-	{DPM_EMU4, (IEN | M5)},						/* dispc2_data9 */
-	{DPM_EMU5, (IEN | M5)},						/* dispc2_data16 */
-	{DPM_EMU6, (IEN | M5)},						/* dispc2_data17 */
-	{DPM_EMU7, (IEN | M5)},						/* dispc2_hsync */
-	{DPM_EMU8, (IEN | M5)},						/* dispc2_pclk */
-	{DPM_EMU9, (IEN | M5)},						/* dispc2_vsync */
-	{DPM_EMU10, (IEN | M5)},					/* dispc2_de */
-	{DPM_EMU11, (IEN | M5)},					/* dispc2_data8 */
-	{DPM_EMU12, (IEN | M5)},					/* dispc2_data7 */
-	{DPM_EMU13, (IEN | M5)},					/* dispc2_data6 */
-	{DPM_EMU14, (IEN | M5)},					/* dispc2_data5 */
-	{DPM_EMU15, (IEN | M5)},					/* dispc2_data4 */
-	{DPM_EMU16, (M3)},						/* gpio_27 */
-	{DPM_EMU17, (IEN | M5)},					/* dispc2_data2 */
-	{DPM_EMU18, (IEN | M5)},					/* dispc2_data1 */
-	{DPM_EMU19, (IEN | M5)},					/* dispc2_data0 */
-};
-
-const struct pad_conf_entry core_padconf_array_non_essential_4430[] = {
-	{ABE_MCBSP2_CLKX, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* abe_mcbsp2_clkx */
-};
-
-const struct pad_conf_entry core_padconf_array_non_essential_4460[] = {
-	{ABE_MCBSP2_CLKX, (PTU | OFF_EN | OFF_OUT_PTU | M3)},		/* led status_1 */
-};
-
-const struct pad_conf_entry wkup_padconf_array_non_essential[] = {
-	{PAD0_SIM_IO, (IEN | M0)},		/* sim_io */
-	{PAD1_SIM_CLK, (M0)},			/* sim_clk */
-	{PAD0_SIM_RESET, (M0)},			/* sim_reset */
-	{PAD1_SIM_CD, (PTU | IEN | M0)},	/* sim_cd */
-	{PAD0_SIM_PWRCTRL, (M0)},		/* sim_pwrctrl */
-	{PAD1_FREF_XTAL_IN, (M0)},		/* # */
-	{PAD0_FREF_SLICER_IN, (M0)},		/* fref_slicer_in */
-	{PAD1_FREF_CLK_IOREQ, (M0)},		/* fref_clk_ioreq */
-	{PAD0_FREF_CLK0_OUT, (M2)},		/* sys_drm_msecure */
-	{PAD1_FREF_CLK3_REQ, M7},		/* safe mode */
-	{PAD0_FREF_CLK4_OUT, (PTU | M3)},	/* led status_2 */
-	{PAD0_SYS_NRESPWRON, (M0)},		/* sys_nrespwron */
-	{PAD1_SYS_NRESWARM, (M0)},		/* sys_nreswarm */
-	{PAD0_SYS_PWR_REQ, (PTU | M0)},		/* sys_pwr_req */
-	{PAD1_SYS_PWRON_RESET, (M3)},		/* gpio_wk29 */
-	{PAD0_SYS_BOOT6, (IEN | M3)},		/* gpio_wk9 */
-	{PAD1_SYS_BOOT7, (IEN | M3)},		/* gpio_wk10 */
-};
-
-const struct pad_conf_entry wkup_padconf_array_non_essential_4430[] = {
-	{PAD1_FREF_CLK4_REQ, (PTU | M3)},	/* led status_1 */
-};
-
 #endif /* _PANDA_MUX_DATA_H_ */
diff --git a/board/ti/sdp3430/Makefile b/board/ti/sdp3430/Makefile
index e72485c4b4..753f09979c 100644
--- a/board/ti/sdp3430/Makefile
+++ b/board/ti/sdp3430/Makefile
@@ -5,23 +5,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	:= sdp.o
-
-SRCS	:= $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	:= sdp.o
diff --git a/board/ti/sdp4430/Makefile b/board/ti/sdp4430/Makefile
index c522a2b84e..79e67b6e96 100644
--- a/board/ti/sdp4430/Makefile
+++ b/board/ti/sdp4430/Makefile
@@ -5,27 +5,8 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	:= sdp.o
+obj-y	:= sdp.o
 
 ifndef CONFIG_SPL_BUILD
-COBJS	+= cmd_bat.o
+obj-y	+= cmd_bat.o
 endif
-
-SRCS	:= $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
diff --git a/board/ti/sdp4430/sdp.c b/board/ti/sdp4430/sdp.c
index 79270a9e94..1e9ef9e38b 100644
--- a/board/ti/sdp4430/sdp.c
+++ b/board/ti/sdp4430/sdp.c
@@ -73,26 +73,6 @@ void set_muxconf_regs_essential(void)
 				 sizeof(struct pad_conf_entry));
 }
 
-void set_muxconf_regs_non_essential(void)
-{
-	do_set_mux((*ctrl)->control_padconf_core_base,
-		   core_padconf_array_non_essential,
-		   sizeof(core_padconf_array_non_essential) /
-		   sizeof(struct pad_conf_entry));
-
-	do_set_mux((*ctrl)->control_padconf_wkup_base,
-		   wkup_padconf_array_non_essential,
-		   sizeof(wkup_padconf_array_non_essential) /
-		   sizeof(struct pad_conf_entry));
-
-	if (omap_revision() < OMAP4460_ES1_0) {
-		do_set_mux((*ctrl)->control_padconf_wkup_base,
-			wkup_padconf_array_non_essential_4430,
-			sizeof(wkup_padconf_array_non_essential_4430) /
-			sizeof(struct pad_conf_entry));
-	}
-}
-
 #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_GENERIC_MMC)
 int board_mmc_init(bd_t *bis)
 {
diff --git a/board/ti/sdp4430/sdp4430_mux_data.h b/board/ti/sdp4430/sdp4430_mux_data.h
index 4394dbaa48..9a9efe7a54 100644
--- a/board/ti/sdp4430/sdp4430_mux_data.h
+++ b/board/ti/sdp4430/sdp4430_mux_data.h
@@ -65,201 +65,4 @@ const struct pad_conf_entry wkup_padconf_array_essential_4460[] = {
 
 };
 
-const struct pad_conf_entry core_padconf_array_non_essential[] = {
-	{GPMC_AD8, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M3)},	/* gpio_32 */
-	{GPMC_AD9, (PTU | IEN | M3)},					/* gpio_33 */
-	{GPMC_AD10, (PTU | IEN | M3)},					/* gpio_34 */
-	{GPMC_AD11, (PTU | IEN | M3)},					/* gpio_35 */
-	{GPMC_AD12, (PTU | IEN | M3)},					/* gpio_36 */
-	{GPMC_AD13, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)},	/* gpio_37 */
-	{GPMC_AD14, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)},	/* gpio_38 */
-	{GPMC_AD15, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)},	/* gpio_39 */
-	{GPMC_A16, (M3)},						/* gpio_40 */
-	{GPMC_A17, (PTD | M3)},						/* gpio_41 */
-	{GPMC_A18, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)},	/* kpd_row6 */
-	{GPMC_A19, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)},	/* kpd_row7 */
-	{GPMC_A20, (IEN | M3)},						/* gpio_44 */
-	{GPMC_A21, (M3)},						/* gpio_45 */
-	{GPMC_A22, (OFF_EN | OFF_PD | OFF_IN | M1)},			/* kpd_col6 */
-	{GPMC_A23, (OFF_EN | OFF_PD | OFF_IN | M1)},			/* kpd_col7 */
-	{GPMC_A24, (PTD | M3)},						/* gpio_48 */
-	{GPMC_A25, (PTD | M3)},						/* gpio_49 */
-	{GPMC_NCS0, (M3)},						/* gpio_50 */
-	{GPMC_NCS1, (IEN | M3)},					/* gpio_51 */
-	{GPMC_NCS2, (IEN | M3)},					/* gpio_52 */
-	{GPMC_NCS3, (IEN | M3)},					/* gpio_53 */
-	{GPMC_NWP, (M3)},						/* gpio_54 */
-	{GPMC_CLK, (PTD | M3)},						/* gpio_55 */
-	{GPMC_NADV_ALE, (M3)},						/* gpio_56 */
-	{GPMC_NBE0_CLE, (M3)},						/* gpio_59 */
-	{GPMC_NBE1, (PTD | M3)},					/* gpio_60 */
-	{GPMC_WAIT0, (PTU | IEN | M3)},					/* gpio_61 */
-	{GPMC_WAIT1, (IEN | M3)},					/* gpio_62 */
-	{C2C_DATA11, (PTD | M3)},					/* gpio_100 */
-	{C2C_DATA12, (M1)},						/* dsi1_te0 */
-	{C2C_DATA13, (PTD | M3)},					/* gpio_102 */
-	{C2C_DATA14, (M1)},						/* dsi2_te0 */
-	{C2C_DATA15, (PTD | M3)},					/* gpio_104 */
-	{HDMI_HPD, (M0)},						/* hdmi_hpd */
-	{HDMI_CEC, (M0)},						/* hdmi_cec */
-	{HDMI_DDC_SCL, (PTU | M0)},					/* hdmi_ddc_scl */
-	{HDMI_DDC_SDA, (PTU | IEN | M0)},				/* hdmi_ddc_sda */
-	{CSI21_DX0, (IEN | M0)},					/* csi21_dx0 */
-	{CSI21_DY0, (IEN | M0)},					/* csi21_dy0 */
-	{CSI21_DX1, (IEN | M0)},					/* csi21_dx1 */
-	{CSI21_DY1, (IEN | M0)},					/* csi21_dy1 */
-	{CSI21_DX2, (IEN | M0)},					/* csi21_dx2 */
-	{CSI21_DY2, (IEN | M0)},					/* csi21_dy2 */
-	{CSI21_DX3, (PTD | M7)},					/* csi21_dx3 */
-	{CSI21_DY3, (PTD | M7)},					/* csi21_dy3 */
-	{CSI21_DX4, (PTD | OFF_EN | OFF_PD | OFF_IN | M7)},		/* csi21_dx4 */
-	{CSI21_DY4, (PTD | OFF_EN | OFF_PD | OFF_IN | M7)},		/* csi21_dy4 */
-	{CSI22_DX0, (IEN | M0)},					/* csi22_dx0 */
-	{CSI22_DY0, (IEN | M0)},					/* csi22_dy0 */
-	{CSI22_DX1, (IEN | M0)},					/* csi22_dx1 */
-	{CSI22_DY1, (IEN | M0)},					/* csi22_dy1 */
-	{CAM_SHUTTER, (OFF_EN | OFF_PD | OFF_OUT_PTD | M0)},		/* cam_shutter */
-	{CAM_STROBE, (OFF_EN | OFF_PD | OFF_OUT_PTD | M0)},		/* cam_strobe */
-	{CAM_GLOBALRESET, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)},	/* gpio_83 */
-	{USBB1_ULPITLL_CLK, (IEN | OFF_EN | OFF_IN | M1)},		/* hsi1_cawake */
-	{USBB1_ULPITLL_STP, (IEN | OFF_EN | OFF_IN | M1)},		/* hsi1_cadata */
-	{USBB1_ULPITLL_DIR, (IEN | OFF_EN | OFF_IN | M1)},		/* hsi1_caflag */
-	{USBB1_ULPITLL_NXT, (OFF_EN | M1)},				/* hsi1_acready */
-	{USBB1_ULPITLL_DAT0, (OFF_EN | M1)},				/* hsi1_acwake */
-	{USBB1_ULPITLL_DAT1, (OFF_EN | M1)},				/* hsi1_acdata */
-	{USBB1_ULPITLL_DAT2, (OFF_EN | M1)},				/* hsi1_acflag */
-	{USBB1_ULPITLL_DAT3, (IEN | OFF_EN | OFF_IN | M1)},		/* hsi1_caready */
-	{ABE_MCBSP2_CLKX, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* abe_mcbsp2_clkx */
-	{ABE_MCBSP2_DR, (IEN | OFF_EN | OFF_OUT_PTD | M0)},		/* abe_mcbsp2_dr */
-	{ABE_MCBSP2_DX, (OFF_EN | OFF_OUT_PTD | M0)},			/* abe_mcbsp2_dx */
-	{ABE_MCBSP2_FSX, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* abe_mcbsp2_fsx */
-	{ABE_MCBSP1_CLKX, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* abe_mcbsp1_clkx */
-	{ABE_MCBSP1_DR, (IEN | OFF_EN | OFF_OUT_PTD | M0)},		/* abe_mcbsp1_dr */
-	{ABE_MCBSP1_DX, (OFF_EN | OFF_OUT_PTD | M0)},			/* abe_mcbsp1_dx */
-	{ABE_MCBSP1_FSX, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* abe_mcbsp1_fsx */
-	{ABE_PDM_UL_DATA, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* abe_pdm_ul_data */
-	{ABE_PDM_DL_DATA, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* abe_pdm_dl_data */
-	{ABE_PDM_FRAME, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* abe_pdm_frame */
-	{ABE_PDM_LB_CLK, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* abe_pdm_lb_clk */
-	{ABE_CLKS, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* abe_clks */
-	{ABE_DMIC_CLK1, (M0)},						/* abe_dmic_clk1 */
-	{ABE_DMIC_DIN1, (IEN | M0)},					/* abe_dmic_din1 */
-	{ABE_DMIC_DIN2, (IEN | M0)},					/* abe_dmic_din2 */
-	{ABE_DMIC_DIN3, (IEN | M0)},					/* abe_dmic_din3 */
-	{UART2_CTS, (PTU | IEN | M0)},					/* uart2_cts */
-	{UART2_RTS, (M0)},						/* uart2_rts */
-	{UART2_RX, (PTU | IEN | M0)},					/* uart2_rx */
-	{UART2_TX, (M0)},						/* uart2_tx */
-	{HDQ_SIO, (M3)},						/* gpio_127 */
-	{MCSPI1_CLK, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},		/* mcspi1_clk */
-	{MCSPI1_SOMI, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},		/* mcspi1_somi */
-	{MCSPI1_SIMO, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},		/* mcspi1_simo */
-	{MCSPI1_CS0, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* mcspi1_cs0 */
-	{MCSPI1_CS1, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M3)},	/* mcspi1_cs1 */
-	{MCSPI1_CS2, (PTU | OFF_EN | OFF_OUT_PTU | M3)},		/* gpio_139 */
-	{MCSPI1_CS3, (PTU | IEN | M3)},					/* gpio_140 */
-	{SDMMC5_CLK, (PTU | IEN | OFF_EN | OFF_OUT_PTD | M0)},		/* sdmmc5_clk */
-	{SDMMC5_CMD, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* sdmmc5_cmd */
-	{SDMMC5_DAT0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* sdmmc5_dat0 */
-	{SDMMC5_DAT1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* sdmmc5_dat1 */
-	{SDMMC5_DAT2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* sdmmc5_dat2 */
-	{SDMMC5_DAT3, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* sdmmc5_dat3 */
-	{MCSPI4_CLK, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},		/* mcspi4_clk */
-	{MCSPI4_SIMO, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},		/* mcspi4_simo */
-	{MCSPI4_SOMI, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},		/* mcspi4_somi */
-	{MCSPI4_CS0, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* mcspi4_cs0 */
-	{UART4_RX, (IEN | M0)},						/* uart4_rx */
-	{UART4_TX, (M0)},						/* uart4_tx */
-	{USBB2_ULPITLL_CLK, (PTD | IEN | M3)},				/* gpio_157 */
-	{USBB2_ULPITLL_STP, (IEN | M5)},				/* dispc2_data23 */
-	{USBB2_ULPITLL_DIR, (IEN | M5)},				/* dispc2_data22 */
-	{USBB2_ULPITLL_NXT, (IEN | M5)},				/* dispc2_data21 */
-	{USBB2_ULPITLL_DAT0, (IEN | M5)},				/* dispc2_data20 */
-	{USBB2_ULPITLL_DAT1, (IEN | M5)},				/* dispc2_data19 */
-	{USBB2_ULPITLL_DAT2, (IEN | M5)},				/* dispc2_data18 */
-	{USBB2_ULPITLL_DAT3, (IEN | M5)},				/* dispc2_data15 */
-	{USBB2_ULPITLL_DAT4, (IEN | M5)},				/* dispc2_data14 */
-	{USBB2_ULPITLL_DAT5, (IEN | M5)},				/* dispc2_data13 */
-	{USBB2_ULPITLL_DAT6, (IEN | M5)},				/* dispc2_data12 */
-	{USBB2_ULPITLL_DAT7, (IEN | M5)},				/* dispc2_data11 */
-	{USBB2_HSIC_DATA, (PTD | OFF_EN | OFF_OUT_PTU | M3)},		/* gpio_169 */
-	{USBB2_HSIC_STROBE, (PTD | OFF_EN | OFF_OUT_PTU | M3)},		/* gpio_170 */
-	{UNIPRO_TX0, (OFF_EN | OFF_PD | OFF_IN | M1)},			/* kpd_col0 */
-	{UNIPRO_TY0, (OFF_EN | OFF_PD | OFF_IN | M1)},			/* kpd_col1 */
-	{UNIPRO_TX1, (OFF_EN | OFF_PD | OFF_IN | M1)},			/* kpd_col2 */
-	{UNIPRO_TY1, (OFF_EN | OFF_PD | OFF_IN | M1)},			/* kpd_col3 */
-	{UNIPRO_TX2, (OFF_EN | OFF_PD | OFF_IN | M1)},			/* kpd_col4 */
-	{UNIPRO_TY2, (OFF_EN | OFF_PD | OFF_IN | M1)},			/* kpd_col5 */
-	{UNIPRO_RX0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)},	/* kpd_row0 */
-	{UNIPRO_RY0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)},	/* kpd_row1 */
-	{UNIPRO_RX1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)},	/* kpd_row2 */
-	{UNIPRO_RY1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)},	/* kpd_row3 */
-	{UNIPRO_RX2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)},	/* kpd_row4 */
-	{UNIPRO_RY2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)},	/* kpd_row5 */
-	{FREF_CLK1_OUT, (M0)},						/* fref_clk1_out */
-	{FREF_CLK2_OUT, (M0)},						/* fref_clk2_out */
-	{SYS_NIRQ1, (PTU | IEN | M0)},					/* sys_nirq1 */
-	{SYS_NIRQ2, (M7)},						/* sys_nirq2 */
-	{SYS_BOOT0, (PTU | IEN | M3)},					/* gpio_184 */
-	{SYS_BOOT1, (M3)},						/* gpio_185 */
-	{SYS_BOOT2, (PTD | IEN | M3)},					/* gpio_186 */
-	{SYS_BOOT3, (PTD | IEN | M3)},					/* gpio_187 */
-	{SYS_BOOT4, (M3)},						/* gpio_188 */
-	{SYS_BOOT5, (PTD | IEN | M3)},					/* gpio_189 */
-	{DPM_EMU0, (IEN | M0)},						/* dpm_emu0 */
-	{DPM_EMU1, (IEN | M0)},						/* dpm_emu1 */
-	{DPM_EMU2, (IEN | M0)},						/* dpm_emu2 */
-	{DPM_EMU3, (IEN | M5)},						/* dispc2_data10 */
-	{DPM_EMU4, (IEN | M5)},						/* dispc2_data9 */
-	{DPM_EMU5, (IEN | M5)},						/* dispc2_data16 */
-	{DPM_EMU6, (IEN | M5)},						/* dispc2_data17 */
-	{DPM_EMU7, (IEN | M5)},						/* dispc2_hsync */
-	{DPM_EMU8, (IEN | M5)},						/* dispc2_pclk */
-	{DPM_EMU9, (IEN | M5)},						/* dispc2_vsync */
-	{DPM_EMU10, (IEN | M5)},					/* dispc2_de */
-	{DPM_EMU11, (IEN | M5)},					/* dispc2_data8 */
-	{DPM_EMU12, (IEN | M5)},					/* dispc2_data7 */
-	{DPM_EMU13, (IEN | M5)},					/* dispc2_data6 */
-	{DPM_EMU14, (IEN | M5)},					/* dispc2_data5 */
-	{DPM_EMU15, (IEN | M5)},					/* dispc2_data4 */
-	{DPM_EMU16, (M3)},						/* gpio_27 */
-	{DPM_EMU17, (IEN | M5)},					/* dispc2_data2 */
-	{DPM_EMU18, (IEN | M5)},					/* dispc2_data1 */
-	{DPM_EMU19, (IEN | M5)},					/* dispc2_data0 */
-	{I2C1_SCL, (PTU | IEN | M0)},					/* i2c1_scl */
-	{I2C1_SDA, (PTU | IEN | M0)},					/* i2c1_sda */
-	{I2C2_SCL, (PTU | IEN | M0)},					/* i2c2_scl */
-	{I2C2_SDA, (PTU | IEN | M0)},					/* i2c2_sda */
-	{I2C3_SCL, (PTU | IEN | M0)},					/* i2c3_scl */
-	{I2C3_SDA, (PTU | IEN | M0)},					/* i2c3_sda */
-	{I2C4_SCL, (PTU | IEN | M0)},					/* i2c4_scl */
-	{I2C4_SDA, (PTU | IEN | M0)}					/* i2c4_sda */
-
-};
-
-const struct pad_conf_entry wkup_padconf_array_non_essential[] = {
-	{PAD0_SIM_IO, (IEN | M0)},		/* sim_io */
-	{PAD1_SIM_CLK, (M0)},			/* sim_clk */
-	{PAD0_SIM_RESET, (M0)},			/* sim_reset */
-	{PAD1_SIM_CD, (PTU | IEN | M0)},	/* sim_cd */
-	{PAD0_SIM_PWRCTRL, (M0)},		/* sim_pwrctrl */
-	{PAD1_FREF_XTAL_IN, (M0)},		/* # */
-	{PAD0_FREF_SLICER_IN, (M0)},		/* fref_slicer_in */
-	{PAD1_FREF_CLK_IOREQ, (M0)},		/* fref_clk_ioreq */
-	{PAD0_FREF_CLK0_OUT, (M2)},		/* sys_drm_msecure */
-	{PAD1_FREF_CLK3_REQ, (M3)},		/* gpio_wk30 - Debug led-1 */
-	{PAD0_FREF_CLK3_OUT, (M0)},		/* fref_clk3_out */
-	{PAD0_FREF_CLK4_OUT, (M3)},		/* gpio_wk8 - Debug led-3 */
-	{PAD0_SYS_NRESPWRON, (M0)},		/* sys_nrespwron */
-	{PAD1_SYS_NRESWARM, (M0)},		/* sys_nreswarm */
-	{PAD0_SYS_PWR_REQ, (PTU | M0)},		/* sys_pwr_req */
-	{PAD1_SYS_PWRON_RESET, (M3)},		/* gpio_wk29 */
-	{PAD0_SYS_BOOT6, (IEN | M3)},		/* gpio_wk9 */
-	{PAD1_SYS_BOOT7, (IEN | M3)},		/* gpio_wk10 */
-};
-
-const struct pad_conf_entry wkup_padconf_array_non_essential_4430[] = {
-	{PAD1_FREF_CLK4_REQ, (M3)}	/* gpio_wk7 - Debug led-2 */
-};
-
 #endif /* _SDP4430_MUX_DATA_H */
diff --git a/board/ti/ti814x/Makefile b/board/ti/ti814x/Makefile
index 6059e203f3..93155de533 100644
--- a/board/ti/ti814x/Makefile
+++ b/board/ti/ti814x/Makefile
@@ -6,33 +6,8 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
 ifdef CONFIG_SPL_BUILD
-COBJS	:= mux.o
+obj-y	:= mux.o
 endif
 
-COBJS	+= evm.o
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
-	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
-
-clean:
-	rm -f $(SOBJS) $(OBJS)
-
-distclean:	clean
-	rm -f $(LIB) core *.bak $(obj).depend
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	+= evm.o
diff --git a/board/ti/ti814x/evm.c b/board/ti/ti814x/evm.c
index e406326a11..54b3dfb82c 100644
--- a/board/ti/ti814x/evm.c
+++ b/board/ti/ti814x/evm.c
@@ -33,15 +33,12 @@ static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
 #ifdef CONFIG_SPL_BUILD
 static const struct cmd_control evm_ddr2_cctrl_data = {
 	.cmd0csratio	= 0x80,
-	.cmd0dldiff	= 0x04,
 	.cmd0iclkout	= 0x00,
 
 	.cmd1csratio	= 0x80,
-	.cmd1dldiff	= 0x04,
 	.cmd1iclkout	= 0x00,
 
 	.cmd2csratio	= 0x80,
-	.cmd2dldiff	= 0x04,
 	.cmd2iclkout	= 0x00,
 };
 
@@ -77,8 +74,6 @@ static const struct ddr_data evm_ddr2_data = {
 	.datagiratio0		= ((0<<10) | (0<<0)),
 	.datafwsratio0		= ((0x90<<10) | (0x90<<0)),
 	.datawrsratio0		= ((0x50<<10) | (0x50<<0)),
-	.datauserank0delay	= 1,
-	.datadldiff0		= 0x4,
 };
 
 void set_uart_mux_conf(void)
@@ -100,9 +95,9 @@ void sdram_init(void)
 {
 	config_dmm(&evm_lisa_map_regs);
 
-	config_ddr(0, 0, &evm_ddr2_data, &evm_ddr2_cctrl_data,
+	config_ddr(0, NULL, &evm_ddr2_data, &evm_ddr2_cctrl_data,
 		   &evm_ddr2_emif0_regs, 0);
-	config_ddr(0, 0, &evm_ddr2_data, &evm_ddr2_cctrl_data,
+	config_ddr(0, NULL, &evm_ddr2_data, &evm_ddr2_cctrl_data,
 		   &evm_ddr2_emif1_regs, 1);
 }
 #endif
@@ -137,12 +132,12 @@ static struct cpsw_slave_data cpsw_slaves[] = {
 	{
 		.slave_reg_ofs	= 0x50,
 		.sliver_reg_ofs	= 0x700,
-		.phy_id		= 1,
+		.phy_addr	= 1,
 	},
 	{
 		.slave_reg_ofs	= 0x90,
 		.sliver_reg_ofs	= 0x740,
-		.phy_id		= 0,
+		.phy_addr	= 0,
 	},
 };
 
diff --git a/board/ti/ti816x/Makefile b/board/ti/ti816x/Makefile
index 17ce72a3cc..f1cc3d5616 100644
--- a/board/ti/ti816x/Makefile
+++ b/board/ti/ti816x/Makefile
@@ -9,29 +9,4 @@
 # SPDX-License-Identifier:	GPL-2.0
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	:= evm.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-clean:
-	rm -f $(OBJS)
-
-distclean:	clean
-	rm -f $(LIB) core *.bak $(obj).depend
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	:= evm.o
diff --git a/board/ti/ti816x/evm.c b/board/ti/ti816x/evm.c
index 74d35e936d..b6bf16236f 100644
--- a/board/ti/ti816x/evm.c
+++ b/board/ti/ti816x/evm.c
@@ -59,21 +59,16 @@ static struct ddr_data ddr2_data = {
 	.datagiratio0		= ((0x0<<10) | (0x0<<0)),
 	.datafwsratio0		= ((0x13A<<10) | (0x13A<<0)),
 	.datawrsratio0		= ((0x8A<<10) | (0x8A<<0)),
-	.datauserank0delay	= 0x1,
-	.datadldiff0		= 0x0, /* depend on cpu rev, set later */
 };
 
 static struct cmd_control ddr2_ctrl = {
 	.cmd0csratio	= 0x80,
-	.cmd0dldiff	= 0x04, /* reset value is 0x4 */
 	.cmd0iclkout	= 0x00,
 
 	.cmd1csratio	= 0x80,
-	.cmd1dldiff	= 0x04, /* reset value is 0x4 */
 	.cmd1iclkout	= 0x00,
 
 	.cmd2csratio	= 0x80,
-	.cmd2dldiff	= 0x04, /* reset value is 0x4 */
 	.cmd2iclkout	= 0x00,
 
 };
@@ -150,21 +145,16 @@ static struct ddr_data ddr3_data = {
 	.datagiratio0		= ((0x20<<10) | 0x20<<0),
 	.datafwsratio0		= ((RD_DQS_GATE<<10) | (RD_DQS_GATE<<0)),
 	.datawrsratio0		= (((WR_DQS+0x40)<<10) | ((WR_DQS+0x40)<<0)),
-	.datauserank0delay	= 0x1,
-	.datadldiff0		= 0x0, /* depend on cpu rev, set later */
 };
 
 static const struct cmd_control ddr3_ctrl = {
 	.cmd0csratio	= 0x100,
-	.cmd0dldiff	= 0x004, /* reset value is 0x4 */
 	.cmd0iclkout	= 0x001,
 
 	.cmd1csratio	= 0x100,
-	.cmd1dldiff	= 0x004, /* reset value is 0x4 */
 	.cmd1iclkout	= 0x001,
 
 	.cmd2csratio	= 0x100,
-	.cmd2dldiff	= 0x004, /* reset value is 0x4 */
 	.cmd2iclkout	= 0x001,
 };
 
@@ -198,32 +188,29 @@ void sdram_init(void)
 	config_dmm(&evm_lisa_map_regs);
 
 #ifdef CONFIG_TI816X_EVM_DDR2
-	ddr2_data.datadldiff0 = (get_cpu_rev() == 0x1 ? 0x0 : 0xF);
-	ddr2_ctrl.cmd0dldiff = (get_cpu_rev() == 0x1 ? 0x0 : 0xF);
-	ddr2_ctrl.cmd1dldiff = (get_cpu_rev() == 0x1 ? 0x0 : 0xF);
-	ddr2_ctrl.cmd2dldiff = (get_cpu_rev() == 0x1 ? 0x0 : 0xF);
-
 	if (CONFIG_TI816X_USE_EMIF0) {
 		ddr2_emif0_regs.emif_ddr_phy_ctlr_1 =
 			(get_cpu_rev() == 0x1 ? 0x0000010B : 0x0000030B);
-		config_ddr(0, 0, &ddr2_data, &ddr2_ctrl, &ddr2_emif0_regs, 0);
+		config_ddr(0, NULL, &ddr2_data, &ddr2_ctrl, &ddr2_emif0_regs,
+			   0);
 	}
 
 	if (CONFIG_TI816X_USE_EMIF1) {
 		ddr2_emif1_regs.emif_ddr_phy_ctlr_1 =
 			(get_cpu_rev() == 0x1 ? 0x0000010B : 0x0000030B);
-		config_ddr(1, 0, &ddr2_data, &ddr2_ctrl, &ddr2_emif1_regs, 1);
+		config_ddr(1, NULL, &ddr2_data, &ddr2_ctrl, &ddr2_emif1_regs,
+			   1);
 	}
 #endif
 
 #ifdef CONFIG_TI816X_EVM_DDR3
-	ddr3_data.datadldiff0 = (get_cpu_rev() == 0x1 ? 0x0 : 0xF);
-
 	if (CONFIG_TI816X_USE_EMIF0)
-		config_ddr(0, 0, &ddr3_data, &ddr3_ctrl, &ddr3_emif0_regs, 0);
+		config_ddr(0, NULL, &ddr3_data, &ddr3_ctrl, &ddr3_emif0_regs,
+			   0);
 
 	if (CONFIG_TI816X_USE_EMIF1)
-		config_ddr(1, 0, &ddr3_data, &ddr3_ctrl, &ddr3_emif1_regs, 1);
+		config_ddr(1, NULL, &ddr3_data, &ddr3_ctrl, &ddr3_emif1_regs,
+			   1);
 #endif
 }
 #endif /* CONFIG_SPL_BUILD */
diff --git a/board/ti/tnetv107xevm/Makefile b/board/ti/tnetv107xevm/Makefile
index 5b82e483b5..0a6128f85f 100644
--- a/board/ti/tnetv107xevm/Makefile
+++ b/board/ti/tnetv107xevm/Makefile
@@ -2,27 +2,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS		+= sdb_board.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-.PHONY: all
-
-all: $(LIB)
-
-$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
-	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
-
-#########################################################################
-# This is for $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y		+= sdb_board.o
diff --git a/board/timll/devkit3250/Makefile b/board/timll/devkit3250/Makefile
index a1e69ad501..472298637f 100644
--- a/board/timll/devkit3250/Makefile
+++ b/board/timll/devkit3250/Makefile
@@ -5,24 +5,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	:= devkit3250.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
-	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	:= devkit3250.o
diff --git a/board/timll/devkit8000/Makefile b/board/timll/devkit8000/Makefile
index 553e699200..104b63b570 100644
--- a/board/timll/devkit8000/Makefile
+++ b/board/timll/devkit8000/Makefile
@@ -8,23 +8,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	:= devkit8000.o
-
-SRCS	:= $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	:= devkit8000.o
diff --git a/board/toradex/colibri_pxa270/Makefile b/board/toradex/colibri_pxa270/Makefile
index 60f4097bf0..57cfe9b789 100644
--- a/board/toradex/colibri_pxa270/Makefile
+++ b/board/toradex/colibri_pxa270/Makefile
@@ -6,23 +6,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	:= colibri_pxa270.o
-
-SRCS	:= $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	:= colibri_pxa270.o
diff --git a/board/toradex/colibri_pxa270/colibri_pxa270.c b/board/toradex/colibri_pxa270/colibri_pxa270.c
index c1e2562348..8d95e4d174 100644
--- a/board/toradex/colibri_pxa270/colibri_pxa270.c
+++ b/board/toradex/colibri_pxa270/colibri_pxa270.c
@@ -13,6 +13,7 @@
 #include <netdev.h>
 #include <asm/io.h>
 #include <serial.h>
+#include <usb.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -39,7 +40,7 @@ int dram_init(void)
 }
 
 #ifdef	CONFIG_CMD_USB
-int usb_board_init(void)
+int board_usb_init(int index, enum usb_init_type init)
 {
 	writel((readl(UHCHR) | UHCHR_PCPL | UHCHR_PSPL) &
 		~(UHCHR_SSEP0 | UHCHR_SSEP1 | UHCHR_SSEP2 | UHCHR_SSE),
@@ -70,9 +71,9 @@ int usb_board_init(void)
 	return 0;
 }
 
-void usb_board_init_fail(void)
+int board_usb_cleanup(int index, enum usb_init_type init)
 {
-	return;
+	return 0;
 }
 
 void usb_board_stop(void)
diff --git a/board/toradex/colibri_t20_iris/Makefile b/board/toradex/colibri_t20_iris/Makefile
index 40789f89f1..ebeac70ea1 100644
--- a/board/toradex/colibri_t20_iris/Makefile
+++ b/board/toradex/colibri_t20_iris/Makefile
@@ -4,28 +4,6 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-$(shell mkdir -p $(obj)../../nvidia/common)
-$(shell mkdir -p $(obj)../colibri_t20-common)
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	:= ../../nvidia/common/board.o
-COBJS	+= ../colibri_t20-common/colibri_t20-common.o
-COBJS	+= $(BOARD).o
-
-SRCS	:= $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	:= ../../nvidia/common/board.o
+obj-y	+= ../colibri_t20-common/colibri_t20-common.o
+obj-y	+= colibri_t20_iris.o
diff --git a/board/toradex/colibri_vf/Makefile b/board/toradex/colibri_vf/Makefile
new file mode 100644
index 0000000000..c7e5134ba1
--- /dev/null
+++ b/board/toradex/colibri_vf/Makefile
@@ -0,0 +1,7 @@
+#
+# Copyright 2013 Freescale Semiconductor, Inc.
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y	:= colibri_vf.o
diff --git a/board/toradex/colibri_vf/colibri_vf.c b/board/toradex/colibri_vf/colibri_vf.c
new file mode 100644
index 0000000000..7f5fad6ae8
--- /dev/null
+++ b/board/toradex/colibri_vf/colibri_vf.c
@@ -0,0 +1,592 @@
+/*
+ * Copyright 2013 Toradex, Inc.
+ *
+ * Based on vf610twr.c:
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/iomux-vf610.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/arch/clock.h>
+#include <mmc.h>
+#include <fsl_esdhc.h>
+#include <miiphy.h>
+#include <netdev.h>
+#include <i2c.h>
+#include <malloc.h>
+#include <nand.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define UART_PAD_CTRL	(PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
+			PAD_CTL_DSE_25ohm | PAD_CTL_OBE_IBE_ENABLE)
+
+#define ESDHC_PAD_CTRL	(PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_HIGH | \
+			PAD_CTL_DSE_20ohm | PAD_CTL_OBE_IBE_ENABLE)
+
+#define ENET_PAD_CTRL	(PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_HIGH | \
+			PAD_CTL_DSE_50ohm | PAD_CTL_OBE_IBE_ENABLE)
+
+void setup_iomux_ddr(void)
+{
+	static const iomux_v3_cfg_t ddr_pads[] = {
+		VF610_PAD_DDR_A15__DDR_A_15,
+		VF610_PAD_DDR_A14__DDR_A_14,
+		VF610_PAD_DDR_A13__DDR_A_13,
+		VF610_PAD_DDR_A12__DDR_A_12,
+		VF610_PAD_DDR_A11__DDR_A_11,
+		VF610_PAD_DDR_A10__DDR_A_10,
+		VF610_PAD_DDR_A9__DDR_A_9,
+		VF610_PAD_DDR_A8__DDR_A_8,
+		VF610_PAD_DDR_A7__DDR_A_7,
+		VF610_PAD_DDR_A6__DDR_A_6,
+		VF610_PAD_DDR_A5__DDR_A_5,
+		VF610_PAD_DDR_A4__DDR_A_4,
+		VF610_PAD_DDR_A3__DDR_A_3,
+		VF610_PAD_DDR_A2__DDR_A_2,
+		VF610_PAD_DDR_A1__DDR_A_1,
+		VF610_PAD_DDR_BA2__DDR_BA_2,
+		VF610_PAD_DDR_BA1__DDR_BA_1,
+		VF610_PAD_DDR_BA0__DDR_BA_0,
+		VF610_PAD_DDR_CAS__DDR_CAS_B,
+		VF610_PAD_DDR_CKE__DDR_CKE_0,
+		VF610_PAD_DDR_CLK__DDR_CLK_0,
+		VF610_PAD_DDR_CS__DDR_CS_B_0,
+		VF610_PAD_DDR_D15__DDR_D_15,
+		VF610_PAD_DDR_D14__DDR_D_14,
+		VF610_PAD_DDR_D13__DDR_D_13,
+		VF610_PAD_DDR_D12__DDR_D_12,
+		VF610_PAD_DDR_D11__DDR_D_11,
+		VF610_PAD_DDR_D10__DDR_D_10,
+		VF610_PAD_DDR_D9__DDR_D_9,
+		VF610_PAD_DDR_D8__DDR_D_8,
+		VF610_PAD_DDR_D7__DDR_D_7,
+		VF610_PAD_DDR_D6__DDR_D_6,
+		VF610_PAD_DDR_D5__DDR_D_5,
+		VF610_PAD_DDR_D4__DDR_D_4,
+		VF610_PAD_DDR_D3__DDR_D_3,
+		VF610_PAD_DDR_D2__DDR_D_2,
+		VF610_PAD_DDR_D1__DDR_D_1,
+		VF610_PAD_DDR_D0__DDR_D_0,
+		VF610_PAD_DDR_DQM1__DDR_DQM_1,
+		VF610_PAD_DDR_DQM0__DDR_DQM_0,
+		VF610_PAD_DDR_DQS1__DDR_DQS_1,
+		VF610_PAD_DDR_DQS0__DDR_DQS_0,
+		VF610_PAD_DDR_RAS__DDR_RAS_B,
+		VF610_PAD_DDR_WE__DDR_WE_B,
+		VF610_PAD_DDR_ODT1__DDR_ODT_0,
+		VF610_PAD_DDR_ODT0__DDR_ODT_1,
+	};
+
+	imx_iomux_v3_setup_multiple_pads(ddr_pads, ARRAY_SIZE(ddr_pads));
+}
+
+void ddr_phy_init(void)
+{
+	struct ddrmr_regs *ddrmr = (struct ddrmr_regs *)DDR_BASE_ADDR;
+
+	writel(DDRMC_PHY_DQ_TIMING, &ddrmr->phy[0]);
+	writel(DDRMC_PHY_DQ_TIMING, &ddrmr->phy[16]);
+	writel(DDRMC_PHY_DQ_TIMING, &ddrmr->phy[32]);
+	writel(DDRMC_PHY_DQ_TIMING, &ddrmr->phy[48]);
+
+	writel(DDRMC_PHY_DQS_TIMING, &ddrmr->phy[1]);
+	writel(DDRMC_PHY_DQS_TIMING, &ddrmr->phy[17]);
+	writel(DDRMC_PHY_DQS_TIMING, &ddrmr->phy[33]);
+	writel(DDRMC_PHY_DQS_TIMING, &ddrmr->phy[49]);
+
+	writel(DDRMC_PHY_CTRL, &ddrmr->phy[2]);
+	writel(DDRMC_PHY_CTRL, &ddrmr->phy[18]);
+	writel(DDRMC_PHY_CTRL, &ddrmr->phy[34]);
+	writel(DDRMC_PHY_CTRL, &ddrmr->phy[50]);
+
+	writel(DDRMC_PHY_MASTER_CTRL, &ddrmr->phy[3]);
+	writel(DDRMC_PHY_MASTER_CTRL, &ddrmr->phy[19]);
+	writel(DDRMC_PHY_MASTER_CTRL, &ddrmr->phy[35]);
+	writel(DDRMC_PHY_MASTER_CTRL, &ddrmr->phy[51]);
+
+	writel(DDRMC_PHY_SLAVE_CTRL, &ddrmr->phy[4]);
+	writel(DDRMC_PHY_SLAVE_CTRL, &ddrmr->phy[20]);
+	writel(DDRMC_PHY_SLAVE_CTRL, &ddrmr->phy[36]);
+	writel(DDRMC_PHY_SLAVE_CTRL, &ddrmr->phy[52]);
+
+	writel(DDRMC_PHY50_DDR3_MODE | DDRMC_PHY50_EN_SW_HALF_CYCLE,
+		&ddrmr->phy[50]);
+}
+
+void ddr_ctrl_init(void)
+{
+	struct ddrmr_regs *ddrmr = (struct ddrmr_regs *)DDR_BASE_ADDR;
+
+	writel(DDRMC_CR00_DRAM_CLASS_DDR3, &ddrmr->cr[0]);
+	writel(DDRMC_CR02_DRAM_TINIT(32), &ddrmr->cr[2]);
+	writel(DDRMC_CR10_TRST_PWRON(124), &ddrmr->cr[10]);
+
+	writel(DDRMC_CR11_CKE_INACTIVE(80000), &ddrmr->cr[11]);
+	writel(DDRMC_CR12_WRLAT(5) | DDRMC_CR12_CASLAT_LIN(12), &ddrmr->cr[12]);
+	writel(DDRMC_CR13_TRC(21) | DDRMC_CR13_TRRD(4) | DDRMC_CR13_TCCD(4) |
+		DDRMC_CR13_TBST_INT_INTERVAL(4), &ddrmr->cr[13]);
+	writel(DDRMC_CR14_TFAW(20) | DDRMC_CR14_TRP(6) | DDRMC_CR14_TWTR(4) |
+		DDRMC_CR14_TRAS_MIN(15), &ddrmr->cr[14]);
+	writel(DDRMC_CR16_TMRD(4) | DDRMC_CR16_TRTP(4), &ddrmr->cr[16]);
+	writel(DDRMC_CR17_TRAS_MAX(28080) | DDRMC_CR17_TMOD(12),
+		&ddrmr->cr[17]);
+	writel(DDRMC_CR18_TCKESR(4) | DDRMC_CR18_TCKE(3), &ddrmr->cr[18]);
+
+	writel(DDRMC_CR20_AP_EN, &ddrmr->cr[20]);
+	writel(DDRMC_CR21_TRCD_INT(6) | DDRMC_CR21_TRAS_LOCKOUT |
+		DDRMC_CR21_CCMAP_EN, &ddrmr->cr[21]);
+
+	writel(DDRMC_CR22_TDAL(11), &ddrmr->cr[22]);
+	writel(DDRMC_CR23_BSTLEN(3) | DDRMC_CR23_TDLL(512), &ddrmr->cr[23]);
+	writel(DDRMC_CR24_TRP_AB(6), &ddrmr->cr[24]);
+
+	writel(DDRMC_CR25_TREF_EN, &ddrmr->cr[25]);
+	writel(DDRMC_CR26_TREF(3112) | DDRMC_CR26_TRFC(64), &ddrmr->cr[26]);
+	writel(DDRMC_CR28_TREF_INT(5), &ddrmr->cr[28]);
+	writel(DDRMC_CR29_TPDEX(3), &ddrmr->cr[29]);
+
+	writel(DDRMC_CR30_TXPDLL(10), &ddrmr->cr[30]);
+	writel(DDRMC_CR31_TXSNR(68) | DDRMC_CR31_TXSR(512), &ddrmr->cr[31]);
+	writel(DDRMC_CR33_EN_QK_SREF, &ddrmr->cr[33]);
+	writel(DDRMC_CR34_CKSRX(5) | DDRMC_CR34_CKSRE(5), &ddrmr->cr[34]);
+
+	writel(DDRMC_CR38_FREQ_CHG_EN, &ddrmr->cr[38]);
+	writel(DDRMC_CR39_PHY_INI_COM(1024) | DDRMC_CR39_PHY_INI_STA(16) |
+		DDRMC_CR39_FRQ_CH_DLLOFF(2), &ddrmr->cr[39]);
+
+	writel(DDRMC_CR41_PHY_INI_STRT_INI_DIS, &ddrmr->cr[41]);
+	writel(DDRMC_CR48_MR1_DA_0(70) | DDRMC_CR48_MR0_DA_0(1056),
+		&ddrmr->cr[48]);
+
+	writel(DDRMC_CR66_ZQCL(256) | DDRMC_CR66_ZQINIT(512), &ddrmr->cr[66]);
+	writel(DDRMC_CR67_ZQCS(64), &ddrmr->cr[67]);
+	writel(DDRMC_CR69_ZQ_ON_SREF_EX(2), &ddrmr->cr[69]);
+
+	writel(DDRMC_CR70_REF_PER_ZQ(64), &ddrmr->cr[70]);
+	writel(DDRMC_CR72_ZQCS_ROTATE, &ddrmr->cr[72]);
+
+	writel(DDRMC_CR73_APREBIT(10) | DDRMC_CR73_COL_DIFF(1) |
+		DDRMC_CR73_ROW_DIFF(2), &ddrmr->cr[73]);
+	writel(DDRMC_CR74_BANKSPLT_EN | DDRMC_CR74_ADDR_CMP_EN |
+		DDRMC_CR74_CMD_AGE_CNT(255) | DDRMC_CR74_AGE_CNT(255),
+		&ddrmr->cr[74]);
+	writel(DDRMC_CR75_RW_PG_EN | DDRMC_CR75_RW_EN | DDRMC_CR75_PRI_EN |
+		DDRMC_CR75_PLEN, &ddrmr->cr[75]);
+	writel(DDRMC_CR76_NQENT_ACTDIS(3) | DDRMC_CR76_D_RW_G_BKCN(3) |
+		DDRMC_CR76_W2R_SPLT_EN | DDRMC_CR76_CS_EN, &ddrmr->cr[76]);
+	writel(DDRMC_CR77_CS_MAP | DDRMC_CR77_DI_RD_INTLEAVE |
+		DDRMC_CR77_SWAP_EN, &ddrmr->cr[77]);
+	writel(DDRMC_CR78_BUR_ON_FLY_BIT(12), &ddrmr->cr[78]);
+	writel(DDRMC_CR79_CTLUPD_AREF, &ddrmr->cr[79]);
+
+	writel(DDRMC_CR82_INT_MASK, &ddrmr->cr[82]);
+
+	writel(DDRMC_CR87_ODT_WR_MAPCS0 | DDRMC_CR87_ODT_RD_MAPCS0,
+		&ddrmr->cr[87]);
+	writel(DDRMC_CR88_TODTL_CMD(4), &ddrmr->cr[88]);
+	writel(DDRMC_CR89_AODT_RWSMCS(2), &ddrmr->cr[89]);
+
+	writel(DDRMC_CR91_R2W_SMCSDL(2), &ddrmr->cr[91]);
+	writel(DDRMC_CR96_WLMRD(40) | DDRMC_CR96_WLDQSEN(25), &ddrmr->cr[96]);
+
+	writel(DDRMC_CR105_RDLVL_DL_0(32), &ddrmr->cr[105]);
+	writel(DDRMC_CR110_RDLVL_DL_1(32), &ddrmr->cr[110]);
+	writel(DDRMC_CR114_RDLVL_GTDL_2(8224), &ddrmr->cr[114]);
+
+	writel(DDRMC_CR117_AXI0_W_PRI(1) | DDRMC_CR117_AXI0_R_PRI(1),
+		&ddrmr->cr[117]);
+	writel(DDRMC_CR118_AXI1_W_PRI(1) | DDRMC_CR118_AXI1_R_PRI(1),
+		&ddrmr->cr[118]);
+
+	writel(DDRMC_CR120_AXI0_PRI1_RPRI(2) | DDRMC_CR120_AXI0_PRI0_RPRI(2),
+		&ddrmr->cr[120]);
+	writel(DDRMC_CR121_AXI0_PRI3_RPRI(2) | DDRMC_CR121_AXI0_PRI2_RPRI(2),
+		&ddrmr->cr[121]);
+	writel(DDRMC_CR122_AXI1_PRI1_RPRI(1) | DDRMC_CR122_AXI1_PRI0_RPRI(1) |
+		DDRMC_CR122_AXI0_PRIRLX(100), &ddrmr->cr[122]);
+	writel(DDRMC_CR123_AXI1_PRI3_RPRI(1) | DDRMC_CR123_AXI1_PRI2_RPRI(1),
+		&ddrmr->cr[123]);
+	writel(DDRMC_CR124_AXI1_PRIRLX(100), &ddrmr->cr[124]);
+
+	writel(DDRMC_CR126_PHY_RDLAT(11), &ddrmr->cr[126]);
+	writel(DDRMC_CR132_WRLAT_ADJ(5) | DDRMC_CR132_RDLAT_ADJ(6),
+		&ddrmr->cr[132]);
+	writel(DDRMC_CR139_PHY_WRLV_RESPLAT(4) | DDRMC_CR139_PHY_WRLV_LOAD(7) |
+		DDRMC_CR139_PHY_WRLV_DLL(3) | DDRMC_CR139_PHY_WRLV_EN(3),
+		&ddrmr->cr[139]);
+
+	writel(DDRMC_CR154_PAD_ZQ_EARLY_CMP_EN_TIMER(13) |
+		DDRMC_CR154_PAD_ZQ_MODE(1) |
+		DDRMC_CR154_DDR_SEL_PAD_CONTR(3), &ddrmr->cr[154]);
+	writel(DDRMC_CR155_AXI0_COBUF | DDRMC_CR155_PAD_ODT_BYTE1(2),
+		&ddrmr->cr[155]);
+	writel(DDRMC_CR158_TWR(6), &ddrmr->cr[158]);
+
+	ddr_phy_init();
+
+	writel(DDRMC_CR00_DRAM_CLASS_DDR3 | DDRMC_CR00_START, &ddrmr->cr[0]);
+
+	udelay(200);
+}
+
+int dram_init(void)
+{
+	setup_iomux_ddr();
+
+	ddr_ctrl_init();
+	gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
+
+	return 0;
+}
+
+static void setup_iomux_uart(void)
+{
+	static const iomux_v3_cfg_t uart_pads[] = {
+		NEW_PAD_CTRL(VF610_PAD_PTB4__UART1_TX, UART_PAD_CTRL),	/* UART_C_TXD: SCI1_TX */
+		NEW_PAD_CTRL(VF610_PAD_PTB5__UART1_RX, UART_PAD_CTRL),	/* UART_C_RXD: SCI1_RX */
+		NEW_PAD_CTRL(VF610_PAD_PTB10__UART0_TX, UART_PAD_CTRL),	/* UART_A_TXD: SCI0_TX */
+		NEW_PAD_CTRL(VF610_PAD_PTB11__UART0_RX, UART_PAD_CTRL),	/* UART_A_RXD: SCI0_RX */
+	};
+
+	imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
+}
+
+static void setup_iomux_enet(void)
+{
+	static const iomux_v3_cfg_t enet0_pads[] = {
+		NEW_PAD_CTRL(VF610_PAD_PTA6__RMII0_CLKOUT, ENET_PAD_CTRL),
+		NEW_PAD_CTRL(VF610_PAD_PTC10__RMII1_MDIO, ENET_PAD_CTRL),
+		NEW_PAD_CTRL(VF610_PAD_PTC9__RMII1_MDC, ENET_PAD_CTRL),
+		NEW_PAD_CTRL(VF610_PAD_PTC11__RMII1_CRS_DV, ENET_PAD_CTRL),
+		NEW_PAD_CTRL(VF610_PAD_PTC12__RMII1_RD1, ENET_PAD_CTRL),
+		NEW_PAD_CTRL(VF610_PAD_PTC13__RMII1_RD0, ENET_PAD_CTRL),
+		NEW_PAD_CTRL(VF610_PAD_PTC14__RMII1_RXER, ENET_PAD_CTRL),
+		NEW_PAD_CTRL(VF610_PAD_PTC15__RMII1_TD1, ENET_PAD_CTRL),
+		NEW_PAD_CTRL(VF610_PAD_PTC16__RMII1_TD0, ENET_PAD_CTRL),
+		NEW_PAD_CTRL(VF610_PAD_PTC17__RMII1_TXEN, ENET_PAD_CTRL),
+	};
+
+	imx_iomux_v3_setup_multiple_pads(enet0_pads, ARRAY_SIZE(enet0_pads));
+}
+
+static void setup_iomux_i2c(void)
+{
+	static const iomux_v3_cfg_t i2c0_pads[] = {
+		VF610_PAD_PTB14__I2C0_SCL,
+		VF610_PAD_PTB15__I2C0_SDA,
+	};
+
+	imx_iomux_v3_setup_multiple_pads(i2c0_pads, ARRAY_SIZE(i2c0_pads));
+}
+
+#ifdef CONFIG_NAND_FSL_NFC
+static void setup_iomux_nfc(void)
+{
+	static const iomux_v3_cfg_t nfc_pads[] = {
+		VF610_PAD_PTD23__NF_IO7,
+		VF610_PAD_PTD22__NF_IO6,
+		VF610_PAD_PTD21__NF_IO5,
+		VF610_PAD_PTD20__NF_IO4,
+		VF610_PAD_PTD19__NF_IO3,
+		VF610_PAD_PTD18__NF_IO2,
+		VF610_PAD_PTD17__NF_IO1,
+		VF610_PAD_PTD16__NF_IO0,
+		VF610_PAD_PTB24__NF_WE_B,
+		VF610_PAD_PTB25__NF_CE0_B,
+		VF610_PAD_PTB27__NF_RE_B,
+		VF610_PAD_PTC26__NF_RB_B,
+		VF610_PAD_PTC27__NF_ALE,
+		VF610_PAD_PTC28__NF_CLE
+	};
+
+	imx_iomux_v3_setup_multiple_pads(nfc_pads, ARRAY_SIZE(nfc_pads));
+}
+#endif
+
+#ifdef CONFIG_FSL_ESDHC
+struct fsl_esdhc_cfg esdhc_cfg[1] = {
+	{ESDHC1_BASE_ADDR},
+};
+
+int board_mmc_getcd(struct mmc *mmc)
+{
+	/* eSDHC1 is always present */
+	return 1;
+}
+
+int board_mmc_init(bd_t *bis)
+{
+	static const iomux_v3_cfg_t esdhc1_pads[] = {
+		NEW_PAD_CTRL(VF610_PAD_PTA24__ESDHC1_CLK, ESDHC_PAD_CTRL),
+		NEW_PAD_CTRL(VF610_PAD_PTA25__ESDHC1_CMD, ESDHC_PAD_CTRL),
+		NEW_PAD_CTRL(VF610_PAD_PTA26__ESDHC1_DAT0, ESDHC_PAD_CTRL),
+		NEW_PAD_CTRL(VF610_PAD_PTA27__ESDHC1_DAT1, ESDHC_PAD_CTRL),
+		NEW_PAD_CTRL(VF610_PAD_PTA28__ESDHC1_DAT2, ESDHC_PAD_CTRL),
+		NEW_PAD_CTRL(VF610_PAD_PTA29__ESDHC1_DAT3, ESDHC_PAD_CTRL),
+	};
+
+	esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
+
+	imx_iomux_v3_setup_multiple_pads(
+		esdhc1_pads, ARRAY_SIZE(esdhc1_pads));
+
+	return fsl_esdhc_initialize(bis, &esdhc_cfg[0]);
+}
+#endif
+
+static inline int is_colibri_vf61(void)
+{
+	struct mscm *mscm = (struct mscm*)MSCM_BASE_ADDR;
+
+	/*
+	 * Detect board type by Level 2 Cache: VF50 don't have any
+	 * Level 2 Cache.
+	 */
+	return !!mscm->cpxcfg1;
+}
+
+static void clock_init(void)
+{
+	struct ccm_reg *ccm = (struct ccm_reg *)CCM_BASE_ADDR;
+	struct anadig_reg *anadig = (struct anadig_reg *)ANADIG_BASE_ADDR;
+	u32 pfd_clk_sel;
+
+	clrsetbits_le32(&ccm->ccgr0, CCM_REG_CTRL_MASK,
+		CCM_CCGR0_UART0_CTRL_MASK);
+	clrsetbits_le32(&ccm->ccgr1, CCM_REG_CTRL_MASK,
+		CCM_CCGR1_PIT_CTRL_MASK | CCM_CCGR1_WDOGA5_CTRL_MASK);
+	clrsetbits_le32(&ccm->ccgr2, CCM_REG_CTRL_MASK,
+		CCM_CCGR2_IOMUXC_CTRL_MASK | CCM_CCGR2_PORTA_CTRL_MASK |
+		CCM_CCGR2_PORTB_CTRL_MASK | CCM_CCGR2_PORTC_CTRL_MASK |
+		CCM_CCGR2_PORTD_CTRL_MASK | CCM_CCGR2_PORTE_CTRL_MASK);
+	clrsetbits_le32(&ccm->ccgr3, CCM_REG_CTRL_MASK,
+		CCM_CCGR3_ANADIG_CTRL_MASK);
+	clrsetbits_le32(&ccm->ccgr4, CCM_REG_CTRL_MASK,
+		CCM_CCGR4_WKUP_CTRL_MASK | CCM_CCGR4_CCM_CTRL_MASK |
+		CCM_CCGR4_GPC_CTRL_MASK | CCM_CCGR4_I2C0_CTRL_MASK);
+	clrsetbits_le32(&ccm->ccgr6, CCM_REG_CTRL_MASK,
+		CCM_CCGR6_OCOTP_CTRL_MASK | CCM_CCGR6_DDRMC_CTRL_MASK);
+	clrsetbits_le32(&ccm->ccgr7, CCM_REG_CTRL_MASK,
+		CCM_CCGR7_SDHC1_CTRL_MASK);
+	clrsetbits_le32(&ccm->ccgr9, CCM_REG_CTRL_MASK,
+		CCM_CCGR9_FEC0_CTRL_MASK | CCM_CCGR9_FEC1_CTRL_MASK);
+	clrsetbits_le32(&ccm->ccgr10, CCM_REG_CTRL_MASK,
+		CCM_CCGR10_NFC_CTRL_MASK);
+
+	clrsetbits_le32(&anadig->pll5_ctrl, ANADIG_PLL5_CTRL_BYPASS |
+		ANADIG_PLL5_CTRL_POWERDOWN, ANADIG_PLL5_CTRL_ENABLE |
+		ANADIG_PLL5_CTRL_DIV_SELECT);
+	clrsetbits_le32(&anadig->pll2_ctrl, ANADIG_PLL2_CTRL_POWERDOWN,
+		ANADIG_PLL2_CTRL_ENABLE | ANADIG_PLL2_CTRL_DIV_SELECT);
+	clrsetbits_le32(&anadig->pll1_ctrl, ANADIG_PLL1_CTRL_POWERDOWN,
+		ANADIG_PLL1_CTRL_ENABLE | ANADIG_PLL1_CTRL_DIV_SELECT);
+
+	clrsetbits_le32(&ccm->ccr, CCM_CCR_OSCNT_MASK,
+		CCM_CCR_FIRC_EN | CCM_CCR_OSCNT(5));
+
+	/* See "Typical PLL Configuration" */
+	pfd_clk_sel = is_colibri_vf61() ? CCM_CCSR_PLL1_PFD_CLK_SEL(1) :
+			CCM_CCSR_PLL1_PFD_CLK_SEL(3);
+	clrsetbits_le32(&ccm->ccsr, CCM_REG_CTRL_MASK, pfd_clk_sel |
+		CCM_CCSR_PLL2_PFD4_EN | CCM_CCSR_PLL2_PFD3_EN |
+		CCM_CCSR_PLL2_PFD2_EN | CCM_CCSR_PLL2_PFD1_EN |
+		CCM_CCSR_PLL1_PFD4_EN | CCM_CCSR_PLL1_PFD3_EN |
+		CCM_CCSR_PLL1_PFD2_EN | CCM_CCSR_PLL1_PFD1_EN |
+		CCM_CCSR_DDRC_CLK_SEL(1) | CCM_CCSR_FAST_CLK_SEL(1) |
+		CCM_CCSR_SYS_CLK_SEL(4));
+
+	clrsetbits_le32(&ccm->cacrr, CCM_REG_CTRL_MASK,
+		CCM_CACRR_IPG_CLK_DIV(1) | CCM_CACRR_BUS_CLK_DIV(2) |
+		CCM_CACRR_ARM_CLK_DIV(0));
+	clrsetbits_le32(&ccm->cscmr1, CCM_REG_CTRL_MASK,
+		CCM_CSCMR1_ESDHC1_CLK_SEL(3) | CCM_CSCMR1_NFC_CLK_SEL(0));
+	clrsetbits_le32(&ccm->cscdr1, CCM_REG_CTRL_MASK,
+		CCM_CSCDR1_RMII_CLK_EN);
+	clrsetbits_le32(&ccm->cscdr2, CCM_REG_CTRL_MASK,
+		CCM_CSCDR2_ESDHC1_EN | CCM_CSCDR2_ESDHC1_CLK_DIV(0) |
+		CCM_CSCDR2_NFC_EN);
+	clrsetbits_le32(&ccm->cscdr3, CCM_REG_CTRL_MASK,
+		CCM_CSCDR3_NFC_PRE_DIV(5));
+	clrsetbits_le32(&ccm->cscmr2, CCM_REG_CTRL_MASK,
+		CCM_CSCMR2_RMII_CLK_SEL(2));	/* PLL5 main clock */
+}
+
+static void mscm_init(void)
+{
+	struct mscm_ir *mscmir = (struct mscm_ir *)MSCM_IR_BASE_ADDR;
+	int i;
+
+	for (i = 0; i < MSCM_IRSPRC_NUM; i++)
+		writew(MSCM_IRSPRC_CP0_EN, &mscmir->irsprc[i]);
+}
+
+int board_phy_config(struct phy_device *phydev)
+{
+	if (phydev->drv->config)
+		phydev->drv->config(phydev);
+
+	return 0;
+}
+
+int board_early_init_f(void)
+{
+	clock_init();
+	mscm_init();
+
+	setup_iomux_uart();
+	setup_iomux_enet();
+	setup_iomux_i2c();
+#ifdef CONFIG_NAND_FSL_NFC
+	setup_iomux_nfc();
+#endif
+
+	return 0;
+}
+
+unsigned char *config_block = NULL;
+
+int read_cfb(void)
+{
+	unsigned char toradex_oui[3] = { 0x00, 0x14, 0x2d };
+	unsigned char ethaddr[6];
+	unsigned char *cfb_ethaddr;
+	size_t size = 0x800;
+
+	/* Allocate RAM area for config block */
+	config_block = malloc(size);
+
+	/* Clear it */
+	memset((void *)config_block, 0, size);
+
+	/* Read production parameter config block from first NAND */
+	if (nand_read_skip_bad(&nand_info[0], CONFIG_TRDX_CFG_BLOCK_OFFSET,
+			&size, NULL, nand_info[0].size, config_block))
+		return 1;
+	cfb_ethaddr = config_block + 8;
+	if (memcmp(cfb_ethaddr, toradex_oui, 3)) {
+		memset((void *)config_block, 0, size);
+		return 2;
+	}
+
+	/*
+	 * Check if Environment contains a valid MAC address, set the one from
+	 * config block if not
+	 */
+	if (!eth_getenv_enetaddr("ethaddr", ethaddr))
+		eth_setenv_enetaddr("ethaddr", cfb_ethaddr);
+
+	return 0;
+}
+
+#ifdef CONFIG_REVISION_TAG
+u32 get_board_rev(void)
+{
+	int i;
+	unsigned short major = 0, minor = 0, release = 0;
+	size_t size = 2048;
+
+	if(config_block == NULL)
+		return 0;
+
+	/* Parse revision information in config block */
+	for (i = 0; i < (size - 8); i++) {
+		if (config_block[i] == 0x02 && config_block[i+1] == 0x40 &&
+				config_block[i+2] == 0x08) {
+			break;
+		}
+	}
+
+	/* Parse revision information in config block */
+	major = (config_block[i+3] << 8) | config_block[i+4];
+	minor = (config_block[i+5] << 8) | config_block[i+6];
+	release = (config_block[i+7] << 8) | config_block[i+8];
+
+	/* Check validity */
+	if (major)
+		return ((major & 0xff) << 8) | ((minor & 0xf) << 4) |
+			((release & 0xf) + 0xa);
+	else
+		return 0;
+}
+#endif
+
+#ifdef CONFIG_SERIAL_TAG
+void get_board_serial(struct tag_serialnr *serialnr)
+{
+	int array[8];
+	int i;
+	unsigned int serial = 0;
+	unsigned int serial_offset = 11;
+
+	serialnr->low = 0;
+	serialnr->high = 0;
+
+	if (config_block == NULL)
+		return;
+
+	/* Get MAC address from config block */
+	memcpy(&serial, config_block + serial_offset, 3);
+	serial = ntohl(serial);
+	serial >>= 8;
+
+	/* Check validity */
+	if (serial) {
+		/* Convert to Linux serial number format (hexadecimal coded
+		 * decimal)
+		 */
+		i = 7;
+		while (serial) {
+			array[i--] = serial % 10;
+			serial /= 10;
+		}
+		while (i >= 0)
+			array[i--] = 0;
+		serial = array[0];
+		for (i = 1; i < 8; i++) {
+			serial *= 16;
+			serial += array[i];
+		}
+
+		serialnr->low = serial;
+	}
+}
+#endif
+
+#ifdef CONFIG_BOARD_LATE_INIT
+int board_late_init(void)
+{
+	if (read_cfb())
+		printf("Missing Toradex config block\n");
+
+	return 0;
+}
+#endif
+
+int board_init(void)
+{
+	/* address of boot parameters */
+	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+
+	if (is_colibri_vf61())
+		gd->bd->bi_arch_number = MACH_TYPE_COLIBRI_VF61;
+	else
+		gd->bd->bi_arch_number = MACH_TYPE_COLIBRI_VF50;
+
+	return 0;
+}
+
+int checkboard(void)
+{
+	if (is_colibri_vf61())
+		puts("Board: Colibri VF61\n");
+	else
+		puts("Board: Colibri VF50\n");
+
+	return 0;
+}
diff --git a/board/toradex/colibri_vf/imximage.cfg b/board/toradex/colibri_vf/imximage.cfg
new file mode 100644
index 0000000000..c4369d69c1
--- /dev/null
+++ b/board/toradex/colibri_vf/imximage.cfg
@@ -0,0 +1,17 @@
+/*
+ * Copyright 2013 Toradex, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ *
+ * Refer docs/README.imxmage for more details about how-to configure
+ * and create imximage boot image
+ *
+ * The syntax is taken as close as possible with the kwbimage
+ */
+#include <asm/imx-common/imximage.cfg>
+
+/* image version */
+IMAGE_VERSION	2
+
+/* Boot Offset 0x400, valid for both SD and NAND boot */
+BOOT_OFFSET	FLASH_OFFSET_STANDARD
diff --git a/board/total5200/Makefile b/board/total5200/Makefile
index 5c22b70f94..527557ca3c 100644
--- a/board/total5200/Makefile
+++ b/board/total5200/Makefile
@@ -5,24 +5,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	:= $(BOARD).o sdram.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	:= total5200.o sdram.o
diff --git a/board/tqc/tqm5200/Makefile b/board/tqc/tqm5200/Makefile
index 619e43f94d..80c1eba87c 100644
--- a/board/tqc/tqm5200/Makefile
+++ b/board/tqc/tqm5200/Makefile
@@ -5,27 +5,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	:= $(BOARD).o cmd_stk52xx.o cmd_tb5200.o cam5200_flash.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-cam5200_flash.o:	cam5200_flash.c
-	$(CC) $(CFLAGS) -c -o $@ $<
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	:= tqm5200.o cmd_stk52xx.o cmd_tb5200.o cam5200_flash.o
diff --git a/board/tqc/tqm8260/Makefile b/board/tqc/tqm8260/Makefile
index b92acdb34b..6b8573d9ab 100644
--- a/board/tqc/tqm8260/Makefile
+++ b/board/tqc/tqm8260/Makefile
@@ -5,27 +5,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-ifneq ($(OBJTREE),$(SRCTREE))
-$(shell mkdir -p $(obj)../tqm8xx/)
-endif
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	= $(BOARD).o ../tqm8xx/load_sernum_ethaddr.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	= tqm8260.o ../tqm8xx/load_sernum_ethaddr.o
diff --git a/board/tqc/tqm8272/Makefile b/board/tqc/tqm8272/Makefile
index 58f1b65ff6..8bf02414e3 100644
--- a/board/tqc/tqm8272/Makefile
+++ b/board/tqc/tqm8272/Makefile
@@ -5,27 +5,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-ifneq ($(OBJTREE),$(SRCTREE))
-$(shell mkdir -p $(obj)../tqm8xx/)
-endif
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	= $(BOARD).o ../tqm8xx/load_sernum_ethaddr.o nand.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	= tqm8272.o ../tqm8xx/load_sernum_ethaddr.o nand.o
diff --git a/board/tqc/tqm834x/Makefile b/board/tqc/tqm834x/Makefile
index 0692bb181f..12edc9af06 100644
--- a/board/tqc/tqm834x/Makefile
+++ b/board/tqc/tqm834x/Makefile
@@ -7,26 +7,5 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS-y += $(BOARD).o
-COBJS-$(CONFIG_PCI) += pci.o
-
-COBJS   := $(COBJS-y)
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y += tqm834x.o
+obj-$(CONFIG_PCI) += pci.o
diff --git a/board/tqc/tqm8xx/Makefile b/board/tqc/tqm8xx/Makefile
index 787ecc2b2d..2651a2f99f 100644
--- a/board/tqc/tqm8xx/Makefile
+++ b/board/tqc/tqm8xx/Makefile
@@ -5,24 +5,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	= $(BOARD).o load_sernum_ethaddr.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	= tqm8xx.o load_sernum_ethaddr.o
diff --git a/board/tqc/tqm8xx/u-boot.lds b/board/tqc/tqm8xx/u-boot.lds
index 1d905e9421..b77ae56c51 100644
--- a/board/tqc/tqm8xx/u-boot.lds
+++ b/board/tqc/tqm8xx/u-boot.lds
@@ -18,13 +18,13 @@ SECTIONS
 
     arch/powerpc/cpu/mpc8xx/start.o	(.text*)
     arch/powerpc/cpu/mpc8xx/traps.o	(.text*)
-    arch/powerpc/cpu/mpc8xx/libmpc8xx.o (.text*)
-    arch/powerpc/lib/libpowerpc.o	(.text*)
-    board/tqc/tqm8xx/libtqm8xx.o	(.text*)
-    disk/libdisk.o			(.text*)
-    drivers/net/libnet.o		(.text*)
-    drivers/pcmcia/libpcmcia.o		(.text.pcmcia_on)
-    drivers/pcmcia/libpcmcia.o		(.text.pcmcia_hardware_enable)
+    arch/powerpc/cpu/mpc8xx/built-in.o	(.text*)
+    arch/powerpc/lib/built-in.o		(.text*)
+    board/tqc/tqm8xx/built-in.o		(.text*)
+    disk/built-in.o			(.text*)
+    drivers/net/built-in.o		(.text*)
+    drivers/built-in.o			(.text.pcmcia_on)
+    drivers/built-in.o			(.text.pcmcia_hardware_enable)
 
     . = DEFINED(env_offset) ? env_offset : .;
     common/env_embedded.o	(.ppcenv*)
diff --git a/board/trizepsiv/Makefile b/board/trizepsiv/Makefile
index e71625ef40..c49686fc60 100644
--- a/board/trizepsiv/Makefile
+++ b/board/trizepsiv/Makefile
@@ -5,23 +5,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	:= conxs.o eeprom.o
-
-SRCS	:= $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	:= conxs.o eeprom.o
diff --git a/board/trizepsiv/conxs.c b/board/trizepsiv/conxs.c
index c0c318f328..1ddf05dcdd 100644
--- a/board/trizepsiv/conxs.c
+++ b/board/trizepsiv/conxs.c
@@ -21,6 +21,7 @@
 #include <asm/arch/regs-mmc.h>
 #include <netdev.h>
 #include <asm/io.h>
+#include <usb.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -42,7 +43,7 @@ extern struct serial_device serial_stuart_device;
  * Miscelaneous platform dependent initialisations
  */
 
-int usb_board_init(void)
+int board_usb_init(int index, enum usb_init_type init)
 {
 	writel((readl(UHCHR) | UHCHR_PCPL | UHCHR_PSPL) &
 		~(UHCHR_SSEP0 | UHCHR_SSEP1 | UHCHR_SSEP2 | UHCHR_SSE),
@@ -69,9 +70,9 @@ int usb_board_init(void)
 	return 0;
 }
 
-void usb_board_init_fail(void)
+int board_usb_cleanup(int index, enum usb_init_type init)
 {
-	return;
+	return 0;
 }
 
 void usb_board_stop(void)
diff --git a/board/ttcontrol/vision2/Makefile b/board/ttcontrol/vision2/Makefile
index dc4bbf2770..c3e1e87f3d 100644
--- a/board/ttcontrol/vision2/Makefile
+++ b/board/ttcontrol/vision2/Makefile
@@ -6,23 +6,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	:= vision2.o
-
-SRCS	:= $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-
-$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	:= vision2.o
diff --git a/board/udoo/1066mhz_4x256mx16.cfg b/board/udoo/1066mhz_4x256mx16.cfg
new file mode 100644
index 0000000000..1ac0aec773
--- /dev/null
+++ b/board/udoo/1066mhz_4x256mx16.cfg
@@ -0,0 +1,55 @@
+/*
+ * Copyright (C) 2013 Boundary Devices
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+DATA 4, MX6_MMDC_P0_MDPDC, 0x00020036
+DATA 4, MX6_MMDC_P0_MDOTC, 0x09444040
+
+DATA 4, MX6_MMDC_P0_MDCFG0, 0x54597955
+DATA 4, MX6_MMDC_P0_MDCFG1, 0xFF328F64
+DATA 4, MX6_MMDC_P0_MDCFG2, 0x01FF00DB
+
+DATA 4, MX6_MMDC_P0_MDMISC, 0x00001740
+DATA 4, MX6_MMDC_P0_MDSCR,  0x00008000
+DATA 4, MX6_MMDC_P0_MDRWD,  0x000026D2
+
+DATA 4, MX6_MMDC_P0_MDOR,  0x00591023
+DATA 4, MX6_MMDC_P0_MDASP, 0x00000027
+DATA 4, MX6_MMDC_P0_MDCTL, 0x831A0000
+
+DATA 4, MX6_MMDC_P0_MDSCR, 0x04088032
+DATA 4, MX6_MMDC_P0_MDSCR, 0x00008033
+
+DATA 4, MX6_MMDC_P0_MDSCR, 	0x00048031
+DATA 4, MX6_MMDC_P0_MDSCR,	0x09408030
+DATA 4, MX6_MMDC_P0_MDSCR, 	0x04008040
+DATA 4, MX6_MMDC_P0_MPZQHWCTRL, 0xA1380003
+DATA 4, MX6_MMDC_P1_MPZQHWCTRL, 0xA1380003
+DATA 4, MX6_MMDC_P0_MDREF, 	0x00005800
+DATA 4, MX6_MMDC_P0_MPODTCTRL, 	0x00011117
+DATA 4, MX6_MMDC_P1_MPODTCTRL, 	0x00011117
+
+DATA 4, MX6_MMDC_P0_MPDGCTRL0, 0x43510360
+DATA 4, MX6_MMDC_P0_MPDGCTRL1, 0x0342033F
+DATA 4, MX6_MMDC_P1_MPDGCTRL0, 0x033F033F
+DATA 4, MX6_MMDC_P1_MPDGCTRL1, 0x03290266
+
+DATA 4, MX6_MMDC_P0_MPRDDLCTL, 0x4B3E4141
+DATA 4, MX6_MMDC_P1_MPRDDLCTL, 0x47413B4A
+DATA 4, MX6_MMDC_P0_MPWRDLCTL, 0x42404843
+DATA 4, MX6_MMDC_P1_MPWRDLCTL, 0x4C3F4C45
+
+DATA 4, MX6_MMDC_P0_MPWLDECTRL0, 0x00350035
+DATA 4, MX6_MMDC_P0_MPWLDECTRL1, 0x001F001F
+DATA 4, MX6_MMDC_P1_MPWLDECTRL0, 0x00010001
+DATA 4, MX6_MMDC_P1_MPWLDECTRL1, 0x00010001
+
+DATA 4, MX6_MMDC_P0_MPMUR0, 0x00000800
+DATA 4, MX6_MMDC_P1_MPMUR0, 0x00000800
+
+DATA 4, MX6_MMDC_P0_MDPDC, 0x00025576
+DATA 4, MX6_MMDC_P0_MAPSR, 0x00011006
+DATA 4, MX6_MMDC_P0_MDSCR, 0x00000000
+
diff --git a/board/udoo/Makefile b/board/udoo/Makefile
new file mode 100644
index 0000000000..80efadaf0d
--- /dev/null
+++ b/board/udoo/Makefile
@@ -0,0 +1,7 @@
+#
+# (C) Copyright 2013 Freescale Semiconductor, Inc.
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y  := udoo.o
diff --git a/board/udoo/clocks.cfg b/board/udoo/clocks.cfg
new file mode 100644
index 0000000000..9cd1af128f
--- /dev/null
+++ b/board/udoo/clocks.cfg
@@ -0,0 +1,32 @@
+/*
+ * Copyright (C) 2013 Boundary Devices
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ *
+ * Device Configuration Data (DCD)
+ *
+ * Each entry must have the format:
+ * Addr-type           Address        Value
+ *
+ * where:
+ *      Addr-type register length (1,2 or 4 bytes)
+ *      Address   absolute address of the register
+ *      value     value to be stored in the register
+ */
+
+/* set the default clock gate to save power */
+DATA 4, CCM_CCGR0, 0x00C03F3F
+DATA 4, CCM_CCGR1, 0x0030FC03
+DATA 4, CCM_CCGR2, 0x0FFFC000
+DATA 4, CCM_CCGR3, 0x3FF00000
+DATA 4, CCM_CCGR4, 0x00FFF300
+DATA 4, CCM_CCGR5, 0x0F0000C3
+DATA 4, CCM_CCGR6, 0x000003FF
+
+/* enable AXI cache for VDOA/VPU/IPU */
+DATA 4, MX6_IOMUXC_GPR4, 0xF00000FF
+
+/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
+DATA 4, MX6_IOMUXC_GPR6, 0x007F007F
+DATA 4, MX6_IOMUXC_GPR7, 0x007F007F
+
diff --git a/board/udoo/ddr-setup.cfg b/board/udoo/ddr-setup.cfg
new file mode 100644
index 0000000000..78cbe17db4
--- /dev/null
+++ b/board/udoo/ddr-setup.cfg
@@ -0,0 +1,87 @@
+/*
+ * Copyright (C) 2013 Boundary Devices
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ *
+ * Device Configuration Data (DCD)
+ *
+ * Each entry must have the format:
+ * Addr-type           Address        Value
+ *
+ * where:
+ *      Addr-type register length (1,2 or 4 bytes)
+ *      Address   absolute address of the register
+ *      value     value to be stored in the register
+ */
+
+/*
+ * DDR3 settings
+ * MX6Q    ddr is limited to 1066 Mhz	currently 1056 MHz(528 MHz clock),
+ *	   memory bus width: 64 bits	x16/x32/x64
+ * MX6DL   ddr is limited to 800 MHz(400 MHz clock)
+ *	   memory bus width: 64 bits	x16/x32/x64
+ * MX6SOLO ddr is limited to 800 MHz(400 MHz clock)
+ *	   memory bus width: 32 bits	x16/x32
+ */
+DATA 4, MX6_IOM_DRAM_SDQS0, 0x00000030
+DATA 4, MX6_IOM_DRAM_SDQS1, 0x00000030
+DATA 4, MX6_IOM_DRAM_SDQS2, 0x00000030
+DATA 4, MX6_IOM_DRAM_SDQS3, 0x00000030
+DATA 4, MX6_IOM_DRAM_SDQS4, 0x00000030
+DATA 4, MX6_IOM_DRAM_SDQS5, 0x00000030
+DATA 4, MX6_IOM_DRAM_SDQS6, 0x00000030
+DATA 4, MX6_IOM_DRAM_SDQS7, 0x00000030
+
+DATA 4, MX6_IOM_GRP_B0DS, 0x00000030
+DATA 4, MX6_IOM_GRP_B1DS, 0x00000030
+DATA 4, MX6_IOM_GRP_B2DS, 0x00000030
+DATA 4, MX6_IOM_GRP_B3DS, 0x00000030
+DATA 4, MX6_IOM_GRP_B4DS, 0x00000030
+DATA 4, MX6_IOM_GRP_B5DS, 0x00000030
+DATA 4, MX6_IOM_GRP_B6DS, 0x00000030
+DATA 4, MX6_IOM_GRP_B7DS, 0x00000030
+DATA 4, MX6_IOM_GRP_ADDDS, 0x00000030
+/* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */
+DATA 4, MX6_IOM_GRP_CTLDS, 0x00000030
+
+DATA 4, MX6_IOM_DRAM_DQM0, 0x00020030
+DATA 4, MX6_IOM_DRAM_DQM1, 0x00020030
+DATA 4, MX6_IOM_DRAM_DQM2, 0x00020030
+DATA 4, MX6_IOM_DRAM_DQM3, 0x00020030
+DATA 4, MX6_IOM_DRAM_DQM4, 0x00020030
+DATA 4, MX6_IOM_DRAM_DQM5, 0x00020030
+DATA 4, MX6_IOM_DRAM_DQM6, 0x00020030
+DATA 4, MX6_IOM_DRAM_DQM7, 0x00020030
+
+DATA 4, MX6_IOM_DRAM_CAS, 0x00020030
+DATA 4, MX6_IOM_DRAM_RAS, 0x00020030
+DATA 4, MX6_IOM_DRAM_SDCLK_0, 0x00020030
+DATA 4, MX6_IOM_DRAM_SDCLK_1, 0x00020030
+
+DATA 4, MX6_IOM_DRAM_RESET, 0x00020030
+DATA 4, MX6_IOM_DRAM_SDCKE0, 0x00003000
+DATA 4, MX6_IOM_DRAM_SDCKE1, 0x00003000
+
+DATA 4, MX6_IOM_DRAM_SDODT0, 0x00003030
+DATA 4, MX6_IOM_DRAM_SDODT1, 0x00003030
+
+/* (differential input) */
+DATA 4, MX6_IOM_DDRMODE_CTL, 0x00020000
+/* (differential input) */
+DATA 4, MX6_IOM_GRP_DDRMODE, 0x00020000
+/* disable ddr pullups */
+DATA 4, MX6_IOM_GRP_DDRPKE, 0x00000000
+DATA 4, MX6_IOM_DRAM_SDBA2, 0x00000000
+/* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */
+DATA 4, MX6_IOM_GRP_DDR_TYPE, 0x000C0000
+
+/* Read data DQ Byte0-3 delay */
+DATA 4, MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333
+DATA 4, MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333
+DATA 4, MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333
+DATA 4, MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333
+DATA 4, MX6_MMDC_P1_MPRDDQBY0DL, 0x33333333
+DATA 4, MX6_MMDC_P1_MPRDDQBY1DL, 0x33333333
+DATA 4, MX6_MMDC_P1_MPRDDQBY2DL, 0x33333333
+DATA 4, MX6_MMDC_P1_MPRDDQBY3DL, 0x33333333
+
diff --git a/board/udoo/udoo.c b/board/udoo/udoo.c
new file mode 100644
index 0000000000..e9236d444c
--- /dev/null
+++ b/board/udoo/udoo.c
@@ -0,0 +1,255 @@
+/*
+ * Copyright (C) 2013 Freescale Semiconductor, Inc.
+ *
+ * Author: Fabio Estevam <fabio.estevam@freescale.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <asm/arch/clock.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/iomux.h>
+#include <malloc.h>
+#include <asm/arch/mx6-pins.h>
+#include <asm/errno.h>
+#include <asm/gpio.h>
+#include <asm/imx-common/iomux-v3.h>
+#include <asm/imx-common/sata.h>
+#include <mmc.h>
+#include <fsl_esdhc.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/io.h>
+#include <asm/arch/sys_proto.h>
+#include <micrel.h>
+#include <miiphy.h>
+#include <netdev.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define UART_PAD_CTRL  (PAD_CTL_PUS_100K_UP |			\
+	PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |			\
+	PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
+
+#define ENET_PAD_CTRL  (PAD_CTL_PUS_100K_UP |                   \
+	PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
+
+#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP |			\
+	PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm |			\
+	PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
+
+#define WDT_EN		IMX_GPIO_NR(5, 4)
+#define WDT_TRG		IMX_GPIO_NR(3, 19)
+
+int dram_init(void)
+{
+	gd->ram_size = (phys_size_t)CONFIG_DDR_MB * 1024 * 1024;
+
+	return 0;
+}
+
+static iomux_v3_cfg_t const uart2_pads[] = {
+	MX6_PAD_EIM_D26__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
+	MX6_PAD_EIM_D27__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const usdhc3_pads[] = {
+	MX6_PAD_SD3_CLK__SD3_CLK    | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD3_CMD__SD3_CMD    | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const wdog_pads[] = {
+	MX6_PAD_EIM_A24__GPIO5_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL),
+	MX6_PAD_EIM_D19__GPIO3_IO19,
+};
+
+int mx6_rgmii_rework(struct phy_device *phydev)
+{
+	/*
+	 * Bug: Apparently uDoo does not works with Gigabit switches...
+	 * Limiting speed to 10/100Mbps, and setting master mode, seems to
+	 * be the only way to have a successfull PHY auto negotiation.
+	 * How to fix: Understand why Linux kernel do not have this issue.
+	 */
+	phy_write(phydev, MDIO_DEVAD_NONE, MII_CTRL1000, 0x1c00);
+
+	/* control data pad skew - devaddr = 0x02, register = 0x04 */
+	ksz9031_phy_extended_write(phydev, 0x02,
+				   MII_KSZ9031_EXT_RGMII_CTRL_SIG_SKEW,
+				   MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x0000);
+	/* rx data pad skew - devaddr = 0x02, register = 0x05 */
+	ksz9031_phy_extended_write(phydev, 0x02,
+				   MII_KSZ9031_EXT_RGMII_RX_DATA_SKEW,
+				   MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x0000);
+	/* tx data pad skew - devaddr = 0x02, register = 0x05 */
+	ksz9031_phy_extended_write(phydev, 0x02,
+				   MII_KSZ9031_EXT_RGMII_TX_DATA_SKEW,
+				   MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x0000);
+	/* gtx and rx clock pad skew - devaddr = 0x02, register = 0x08 */
+	ksz9031_phy_extended_write(phydev, 0x02,
+				   MII_KSZ9031_EXT_RGMII_CLOCK_SKEW,
+				   MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x03FF);
+	return 0;
+}
+
+static iomux_v3_cfg_t const enet_pads1[] = {
+	MX6_PAD_ENET_MDIO__ENET_MDIO		| MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_ENET_MDC__ENET_MDC		| MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_RGMII_TXC__RGMII_TXC	| MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_RGMII_TD0__RGMII_TD0	| MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_RGMII_TD1__RGMII_TD1	| MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_RGMII_TD2__RGMII_TD2	| MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_RGMII_TD3__RGMII_TD3	| MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL	| MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_ENET_REF_CLK__ENET_TX_CLK	| MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_RGMII_RXC__RGMII_RXC	| MUX_PAD_CTRL(ENET_PAD_CTRL),
+	/* RGMII reset */
+	MX6_PAD_EIM_D23__GPIO3_IO23		| MUX_PAD_CTRL(NO_PAD_CTRL),
+	/* Ethernet power supply */
+	MX6_PAD_EIM_EB3__GPIO2_IO31		| MUX_PAD_CTRL(NO_PAD_CTRL),
+	/* pin 32 - 1 - (MODE0) all */
+	MX6_PAD_RGMII_RD0__GPIO6_IO25		| MUX_PAD_CTRL(NO_PAD_CTRL),
+	/* pin 31 - 1 - (MODE1) all */
+	MX6_PAD_RGMII_RD1__GPIO6_IO27		| MUX_PAD_CTRL(NO_PAD_CTRL),
+	/* pin 28 - 1 - (MODE2) all */
+	MX6_PAD_RGMII_RD2__GPIO6_IO28		| MUX_PAD_CTRL(NO_PAD_CTRL),
+	/* pin 27 - 1 - (MODE3) all */
+	MX6_PAD_RGMII_RD3__GPIO6_IO29		| MUX_PAD_CTRL(NO_PAD_CTRL),
+	/* pin 33 - 1 - (CLK125_EN) 125Mhz clockout enabled */
+	MX6_PAD_RGMII_RX_CTL__GPIO6_IO24	| MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const enet_pads2[] = {
+	MX6_PAD_RGMII_RD0__RGMII_RD0	| MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_RGMII_RD1__RGMII_RD1	| MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_RGMII_RD2__RGMII_RD2	| MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_RGMII_RD3__RGMII_RD3	| MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL	| MUX_PAD_CTRL(ENET_PAD_CTRL),
+};
+
+static void setup_iomux_enet(void)
+{
+	imx_iomux_v3_setup_multiple_pads(enet_pads1, ARRAY_SIZE(enet_pads1));
+	udelay(20);
+	gpio_direction_output(IMX_GPIO_NR(2, 31), 1); /* Power supply on */
+
+	gpio_direction_output(IMX_GPIO_NR(3, 23), 0); /* assert PHY rst */
+
+	gpio_direction_output(IMX_GPIO_NR(6, 24), 1);
+	gpio_direction_output(IMX_GPIO_NR(6, 25), 1);
+	gpio_direction_output(IMX_GPIO_NR(6, 27), 1);
+	gpio_direction_output(IMX_GPIO_NR(6, 28), 1);
+	gpio_direction_output(IMX_GPIO_NR(6, 29), 1);
+	udelay(1000);
+
+	gpio_set_value(IMX_GPIO_NR(3, 23), 1); /* deassert PHY rst */
+
+	/* Need 100ms delay to exit from reset. */
+	udelay(1000 * 100);
+
+	gpio_free(IMX_GPIO_NR(6, 24));
+	gpio_free(IMX_GPIO_NR(6, 25));
+	gpio_free(IMX_GPIO_NR(6, 27));
+	gpio_free(IMX_GPIO_NR(6, 28));
+	gpio_free(IMX_GPIO_NR(6, 29));
+
+	imx_iomux_v3_setup_multiple_pads(enet_pads2, ARRAY_SIZE(enet_pads2));
+}
+
+static void setup_iomux_uart(void)
+{
+	imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads));
+}
+
+static void setup_iomux_wdog(void)
+{
+	imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
+	gpio_direction_output(WDT_TRG, 0);
+	gpio_direction_output(WDT_EN, 1);
+	gpio_direction_input(WDT_TRG);
+}
+
+static struct fsl_esdhc_cfg usdhc_cfg = { USDHC3_BASE_ADDR };
+
+int board_mmc_getcd(struct mmc *mmc)
+{
+	return 1; /* Always present */
+}
+
+int board_eth_init(bd_t *bis)
+{
+	uint32_t base = IMX_FEC_BASE;
+	struct mii_dev *bus = NULL;
+	struct phy_device *phydev = NULL;
+	int ret;
+
+	setup_iomux_enet();
+
+#ifdef CONFIG_FEC_MXC
+	bus = fec_get_miibus(base, -1);
+	if (!bus)
+		return 0;
+	/* scan phy 4,5,6,7 */
+	phydev = phy_find_by_mask(bus, (0xf << 4), PHY_INTERFACE_MODE_RGMII);
+
+	if (!phydev) {
+		free(bus);
+		return 0;
+	}
+	printf("using phy at %d\n", phydev->addr);
+	ret  = fec_probe(bis, -1, base, bus, phydev);
+	if (ret) {
+		printf("FEC MXC: %s:failed\n", __func__);
+		free(phydev);
+		free(bus);
+	}
+#endif
+	return 0;
+}
+
+int board_mmc_init(bd_t *bis)
+{
+	imx_iomux_v3_setup_multiple_pads(usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
+	usdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
+	usdhc_cfg.max_bus_width = 4;
+
+	return fsl_esdhc_initialize(bis, &usdhc_cfg);
+}
+
+int board_early_init_f(void)
+{
+	setup_iomux_wdog();
+	setup_iomux_uart();
+
+	return 0;
+}
+
+int board_phy_config(struct phy_device *phydev)
+{
+	mx6_rgmii_rework(phydev);
+	if (phydev->drv->config)
+		phydev->drv->config(phydev);
+
+	return 0;
+}
+
+int board_init(void)
+{
+	/* address of boot parameters */
+	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+
+#ifdef CONFIG_CMD_SATA
+	setup_sata();
+#endif
+	return 0;
+}
+
+int checkboard(void)
+{
+	puts("Board: Udoo\n");
+
+	return 0;
+}
diff --git a/board/udoo/udoo.cfg b/board/udoo/udoo.cfg
new file mode 100644
index 0000000000..8d7ff25f7f
--- /dev/null
+++ b/board/udoo/udoo.cfg
@@ -0,0 +1,29 @@
+/*
+ * Copyright (C) 2013 Boundary Devices
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ *
+ * Refer doc/README.imximage for more details about how-to configure
+ * and create imximage boot image
+ *
+ * The syntax is taken as close as possible with the kwbimage
+ */
+
+/* image version */
+IMAGE_VERSION 2
+
+/*
+ * Boot Device : one of
+ * spi, sd (the board has no nand neither onenand)
+ */
+BOOT_FROM      sd
+
+#define __ASSEMBLY__
+#include <config.h>
+#include "asm/arch/mx6-ddr.h"
+#include "asm/arch/iomux.h"
+#include "asm/arch/crm_regs.h"
+
+#include "ddr-setup.cfg"
+#include "1066mhz_4x256mx16.cfg"
+#include "clocks.cfg"
diff --git a/board/utx8245/Makefile b/board/utx8245/Makefile
index 4cf57cea79..f12e5457b1 100644
--- a/board/utx8245/Makefile
+++ b/board/utx8245/Makefile
@@ -10,24 +10,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	= $(BOARD).o flash.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	= utx8245.o flash.o
diff --git a/board/v37/Makefile b/board/v37/Makefile
index 1284818686..2df4b82fb8 100644
--- a/board/v37/Makefile
+++ b/board/v37/Makefile
@@ -5,24 +5,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	= $(BOARD).o flash.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	= v37.o flash.o
diff --git a/board/v38b/Makefile b/board/v38b/Makefile
index 5c8bb6f505..a20a5ef0e9 100644
--- a/board/v38b/Makefile
+++ b/board/v38b/Makefile
@@ -5,24 +5,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	:= $(BOARD).o ethaddr.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	:= v38b.o ethaddr.o
diff --git a/board/ve8313/Makefile b/board/ve8313/Makefile
index ff0dbf869d..41258f9722 100644
--- a/board/ve8313/Makefile
+++ b/board/ve8313/Makefile
@@ -5,24 +5,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	:= $(BOARD).o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	:= ve8313.o
diff --git a/board/vpac270/Makefile b/board/vpac270/Makefile
index a138aa4da7..ad7f7d8d66 100644
--- a/board/vpac270/Makefile
+++ b/board/vpac270/Makefile
@@ -6,27 +6,8 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
 ifndef	CONFIG_SPL_BUILD
-COBJS	:= vpac270.o
+obj-y	:= vpac270.o
 else
-COBJS	:= onenand.o
+obj-y	:= onenand.o
 endif
-
-SRCS	:= $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
diff --git a/board/vpac270/u-boot-spl.lds b/board/vpac270/u-boot-spl.lds
index 7eac4975ba..5dbf94e44e 100644
--- a/board/vpac270/u-boot-spl.lds
+++ b/board/vpac270/u-boot-spl.lds
@@ -20,8 +20,9 @@ SECTIONS
 	.text.0	:
 	{
 		arch/arm/cpu/pxa/start.o		(.text*)
-		board/vpac270/libvpac270.o		(.text*)
-		drivers/mtd/onenand/libonenand.o	(.text*)
+		arch/arm/lib/built-in.o			(.text*)
+		board/vpac270/built-in.o		(.text*)
+		drivers/mtd/onenand/built-in.o		(.text*)
 	}
 
 
@@ -53,7 +54,12 @@ SECTIONS
 
 	. = ALIGN(0x800);
 
-	_end = .;
+	.end :
+	{
+		*(.__end)
+	}
+
+	_image_binary_end = .;
 
 	.bss __rel_dyn_start (OVERLAY) : {
 		__bss_start = .;
@@ -62,13 +68,13 @@ SECTIONS
 		__bss_end = .;
 	}
 
-	/DISCARD/ : { *(.bss*) }
-	/DISCARD/ : { *(.dynsym) }
-	/DISCARD/ : { *(.dynstr*) }
-	/DISCARD/ : { *(.dynsym*) }
-	/DISCARD/ : { *(.dynamic*) }
-	/DISCARD/ : { *(.hash*) }
-	/DISCARD/ : { *(.plt*) }
-	/DISCARD/ : { *(.interp*) }
-	/DISCARD/ : { *(.gnu*) }
+	.dynsym _image_binary_end : { *(.dynsym) }
+	.dynbss : { *(.dynbss) }
+	.dynstr : { *(.dynstr*) }
+	.dynamic : { *(.dynamic*) }
+	.hash : { *(.hash*) }
+	.plt : { *(.plt*) }
+	.interp : { *(.interp*) }
+	.gnu : { *(.gnu*) }
+	.ARM.exidx : { *(.ARM.exidx*) }
 }
diff --git a/board/vpac270/vpac270.c b/board/vpac270/vpac270.c
index 616736f5c4..8d777df846 100644
--- a/board/vpac270/vpac270.c
+++ b/board/vpac270/vpac270.c
@@ -13,6 +13,7 @@
 #include <netdev.h>
 #include <serial.h>
 #include <asm/io.h>
+#include <usb.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -66,7 +67,7 @@ int board_mmc_init(bd_t *bis)
 #endif
 
 #ifdef	CONFIG_CMD_USB
-int usb_board_init(void)
+int board_usb_init(int index, enum usb_init_type init)
 {
 	writel((UHCHR | UHCHR_PCPL | UHCHR_PSPL) &
 		~(UHCHR_SSEP0 | UHCHR_SSEP1 | UHCHR_SSEP2 | UHCHR_SSE),
@@ -97,9 +98,9 @@ int usb_board_init(void)
 	return 0;
 }
 
-void usb_board_init_fail(void)
+int board_usb_cleanup(int index, enum usb_init_type init)
 {
-	return;
+	return 0;
 }
 
 void usb_board_stop(void)
diff --git a/board/w7o/Makefile b/board/w7o/Makefile
index 85bebaccca..955de50e4f 100644
--- a/board/w7o/Makefile
+++ b/board/w7o/Makefile
@@ -8,26 +8,6 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	= $(BOARD).o flash.o fpga.o fsboot.o post2.o vpd.o cmd_vpd.o \
+obj-y	= w7o.o flash.o fpga.o fsboot.o post2.o vpd.o cmd_vpd.o \
 	  watchdog.o
-SOBJS	= init.o post1.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(OBJS) $(SOBJS)
-	$(call cmd_link_o_target, $^)
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	+= init.o post1.o
diff --git a/board/w7o/init.S b/board/w7o/init.S
index 54eda3299f..dfde149956 100644
--- a/board/w7o/init.S
+++ b/board/w7o/init.S
@@ -4,8 +4,6 @@
 #include <config.h>
 #include <asm/ppc4xx.h>
 
-#define _LINUX_CONFIG_H 1	/* avoid reading Linux autoconf.h file	*/
-
 #include <ppc_asm.tmpl>
 #include <ppc_defs.h>
 
diff --git a/board/w7o/post1.S b/board/w7o/post1.S
index 7a411a4920..aae5387212 100644
--- a/board/w7o/post1.S
+++ b/board/w7o/post1.S
@@ -13,8 +13,6 @@
 #include <config.h>
 #include <asm/ppc4xx.h>
 
-#define _LINUX_CONFIG_H 1       /* avoid reading Linux autoconf.h file  */
-
 #include <ppc_asm.tmpl>
 #include <ppc_defs.h>
 
diff --git a/board/wandboard/Makefile b/board/wandboard/Makefile
index d4782e0c79..5b50ecaf22 100644
--- a/board/wandboard/Makefile
+++ b/board/wandboard/Makefile
@@ -4,23 +4,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB    = $(obj)lib$(BOARD).o
-
-COBJS  := wandboard.o
-
-SRCS   := $(COBJS:.o=.c)
-OBJS   := $(addprefix $(obj),$(COBJS))
-
-$(LIB):        $(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y  := wandboard.o
diff --git a/board/wandboard/README b/board/wandboard/README
index 498db2fd47..1f678e16a9 100644
--- a/board/wandboard/README
+++ b/board/wandboard/README
@@ -3,8 +3,8 @@ U-Boot for Wandboard
 
 This file contains information for the port of U-Boot to the Wandboard.
 
-Wandboard is a development board that has two variants: one version based
-on mx6 dual lite and another one based on mx6 solo.
+Wandboard is a development board that has three variants based on the following
+SoCs: mx6 quad, mx6 dual lite and mx6 solo.
 
 For more details about Wandboard, please refer to:
 http://www.wandboard.org/
diff --git a/board/wandboard/wandboard.c b/board/wandboard/wandboard.c
index 23a78c1663..f1951dc5ef 100644
--- a/board/wandboard/wandboard.c
+++ b/board/wandboard/wandboard.c
@@ -17,7 +17,7 @@
 #include <asm/imx-common/iomux-v3.h>
 #include <asm/imx-common/boot_mode.h>
 #include <asm/io.h>
-#include <asm/sizes.h>
+#include <linux/sizes.h>
 #include <common.h>
 #include <fsl_esdhc.h>
 #include <ipu_pixfmt.h>
@@ -25,6 +25,8 @@
 #include <miiphy.h>
 #include <netdev.h>
 #include <linux/fb.h>
+#include <phy.h>
+#include <input.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -51,50 +53,50 @@ int dram_init(void)
 }
 
 static iomux_v3_cfg_t const uart1_pads[] = {
-	MX6_PAD_CSI0_DAT10__UART1_TXD | MUX_PAD_CTRL(UART_PAD_CTRL),
-	MX6_PAD_CSI0_DAT11__UART1_RXD | MUX_PAD_CTRL(UART_PAD_CTRL),
+	MX6_PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
+	MX6_PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
 };
 
-iomux_v3_cfg_t const usdhc1_pads[] = {
-	MX6_PAD_SD1_CLK__USDHC1_CLK   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD1_CMD__USDHC1_CMD   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD1_DAT0__USDHC1_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD1_DAT1__USDHC1_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD1_DAT2__USDHC1_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD1_DAT3__USDHC1_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+static iomux_v3_cfg_t const usdhc1_pads[] = {
+	MX6_PAD_SD1_CLK__SD1_CLK   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD1_CMD__SD1_CMD   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD1_DAT0__SD1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD1_DAT1__SD1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD1_DAT2__SD1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD1_DAT3__SD1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 	/* Carrier MicroSD Card Detect */
-	MX6_PAD_GPIO_2__GPIO_1_2      | MUX_PAD_CTRL(NO_PAD_CTRL),
+	MX6_PAD_GPIO_2__GPIO1_IO02      | MUX_PAD_CTRL(NO_PAD_CTRL),
 };
 
 static iomux_v3_cfg_t const usdhc3_pads[] = {
-	MX6_PAD_SD3_CLK__USDHC3_CLK   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD3_CMD__USDHC3_CMD   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD3_DAT0__USDHC3_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD3_DAT1__USDHC3_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD3_DAT2__USDHC3_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD3_DAT3__USDHC3_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD3_CLK__SD3_CLK   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD3_CMD__SD3_CMD   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 	/* SOM MicroSD Card Detect */
-	MX6_PAD_EIM_DA9__GPIO_3_9     | MUX_PAD_CTRL(NO_PAD_CTRL),
+	MX6_PAD_EIM_DA9__GPIO3_IO09     | MUX_PAD_CTRL(NO_PAD_CTRL),
 };
 
 static iomux_v3_cfg_t const enet_pads[] = {
 	MX6_PAD_ENET_MDIO__ENET_MDIO		| MUX_PAD_CTRL(ENET_PAD_CTRL),
 	MX6_PAD_ENET_MDC__ENET_MDC		| MUX_PAD_CTRL(ENET_PAD_CTRL),
-	MX6_PAD_RGMII_TXC__ENET_RGMII_TXC	| MUX_PAD_CTRL(ENET_PAD_CTRL),
-	MX6_PAD_RGMII_TD0__ENET_RGMII_TD0	| MUX_PAD_CTRL(ENET_PAD_CTRL),
-	MX6_PAD_RGMII_TD1__ENET_RGMII_TD1	| MUX_PAD_CTRL(ENET_PAD_CTRL),
-	MX6_PAD_RGMII_TD2__ENET_RGMII_TD2	| MUX_PAD_CTRL(ENET_PAD_CTRL),
-	MX6_PAD_RGMII_TD3__ENET_RGMII_TD3	| MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_RGMII_TXC__RGMII_TXC	| MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_RGMII_TD0__RGMII_TD0	| MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_RGMII_TD1__RGMII_TD1	| MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_RGMII_TD2__RGMII_TD2	| MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_RGMII_TD3__RGMII_TD3	| MUX_PAD_CTRL(ENET_PAD_CTRL),
 	MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL	| MUX_PAD_CTRL(ENET_PAD_CTRL),
 	MX6_PAD_ENET_REF_CLK__ENET_TX_CLK	| MUX_PAD_CTRL(ENET_PAD_CTRL),
-	MX6_PAD_RGMII_RXC__ENET_RGMII_RXC	| MUX_PAD_CTRL(ENET_PAD_CTRL),
-	MX6_PAD_RGMII_RD0__ENET_RGMII_RD0	| MUX_PAD_CTRL(ENET_PAD_CTRL),
-	MX6_PAD_RGMII_RD1__ENET_RGMII_RD1	| MUX_PAD_CTRL(ENET_PAD_CTRL),
-	MX6_PAD_RGMII_RD2__ENET_RGMII_RD2	| MUX_PAD_CTRL(ENET_PAD_CTRL),
-	MX6_PAD_RGMII_RD3__ENET_RGMII_RD3	| MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_RGMII_RXC__RGMII_RXC	| MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_RGMII_RD0__RGMII_RD0	| MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_RGMII_RD1__RGMII_RD1	| MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_RGMII_RD2__RGMII_RD2	| MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_RGMII_RD3__RGMII_RD3	| MUX_PAD_CTRL(ENET_PAD_CTRL),
 	MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL	| MUX_PAD_CTRL(ENET_PAD_CTRL),
 	/* AR8031 PHY Reset */
-	MX6_PAD_EIM_D29__GPIO_3_29		| MUX_PAD_CTRL(NO_PAD_CTRL),
+	MX6_PAD_EIM_D29__GPIO3_IO29		| MUX_PAD_CTRL(NO_PAD_CTRL),
 };
 
 static void setup_iomux_uart(void)
@@ -230,8 +232,10 @@ int board_video_skip(void)
 
 	ret = ipuv3_fb_init(&hdmi, 0, IPU_PIX_FMT_RGB24);
 
-	if (ret)
+	if (ret) {
 		printf("HDMI cannot be configured: %d\n", ret);
+		return ret;
+	}
 
 	imx_enable_hdmi_phy();
 
@@ -255,15 +259,9 @@ static void setup_display(void)
 
 int board_eth_init(bd_t *bis)
 {
-	int ret;
-
 	setup_iomux_enet();
 
-	ret = cpu_eth_init(bis);
-	if (ret)
-		printf("FEC MXC: %s:failed\n", __func__);
-
-	return 0;
+	return cpu_eth_init(bis);
 }
 
 int board_early_init_f(void)
diff --git a/board/woodburn/Makefile b/board/woodburn/Makefile
index 89e1f2499c..db2b2d54ed 100644
--- a/board/woodburn/Makefile
+++ b/board/woodburn/Makefile
@@ -6,25 +6,5 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	:= woodburn.o
-SOBJS	:= lowlevel_init.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
-	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	:= woodburn.o
+obj-y	+= lowlevel_init.o
diff --git a/board/xaeniax/Makefile b/board/xaeniax/Makefile
index 1081eb4ec3..e5f116debb 100644
--- a/board/xaeniax/Makefile
+++ b/board/xaeniax/Makefile
@@ -5,23 +5,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	:= xaeniax.o flash.o
-
-SRCS	:= $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	:= xaeniax.o flash.o
diff --git a/board/xes/common/Makefile b/board/xes/common/Makefile
index 2e5f1c522f..65d321abdd 100644
--- a/board/xes/common/Makefile
+++ b/board/xes/common/Makefile
@@ -5,34 +5,10 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-ifneq ($(OBJTREE),$(SRCTREE))
-$(shell mkdir -p $(obj)board/$(VENDOR)/common)
-endif
-
-LIB	= $(obj)lib$(VENDOR).o
-
-COBJS-$(CONFIG_FSL_PCI_INIT)	+= fsl_8xxx_pci.o
-COBJS-$(CONFIG_MPC8572)		+= fsl_8xxx_clk.o
-COBJS-$(CONFIG_MPC86xx)		+= fsl_8xxx_clk.o
-COBJS-$(CONFIG_P2020)		+= fsl_8xxx_clk.o
-COBJS-$(CONFIG_MPC85xx)		+= fsl_8xxx_misc.o board.o
-COBJS-$(CONFIG_MPC86xx)		+= fsl_8xxx_misc.o board.o
-COBJS-$(CONFIG_NAND_ACTL)	+= actl_nand.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS-y))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-$(CONFIG_FSL_PCI_INIT)	+= fsl_8xxx_pci.o
+obj-$(CONFIG_MPC8572)		+= fsl_8xxx_clk.o
+obj-$(CONFIG_MPC86xx)		+= fsl_8xxx_clk.o
+obj-$(CONFIG_P2020)		+= fsl_8xxx_clk.o
+obj-$(CONFIG_MPC85xx)		+= fsl_8xxx_misc.o board.o
+obj-$(CONFIG_MPC86xx)		+= fsl_8xxx_misc.o board.o
+obj-$(CONFIG_NAND_ACTL)	+= actl_nand.o
diff --git a/board/xes/xpedite1000/Makefile b/board/xes/xpedite1000/Makefile
index 1d80df8b74..308de91c9d 100644
--- a/board/xes/xpedite1000/Makefile
+++ b/board/xes/xpedite1000/Makefile
@@ -5,25 +5,5 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	= $(BOARD).o
-SOBJS	= init.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(OBJS) $(SOBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	= xpedite1000.o
+extra-y	+= init.o
diff --git a/board/xes/xpedite517x/Makefile b/board/xes/xpedite517x/Makefile
index 0105aa1915..d88c3d4b9a 100644
--- a/board/xes/xpedite517x/Makefile
+++ b/board/xes/xpedite517x/Makefile
@@ -5,26 +5,6 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS-y	+= $(BOARD).o
-COBJS-y	+= ddr.o
-COBJS-y	+= law.o
-
-SRCS	:= $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS-y))
-SOBJS	:= $(addprefix $(obj),$(SOBJS-y))
-
-$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude ($obj).depend
-
-#########################################################################
+obj-y	+= xpedite517x.o
+obj-y	+= ddr.o
+obj-y	+= law.o
diff --git a/board/xes/xpedite517x/ddr.c b/board/xes/xpedite517x/ddr.c
index f48c02fdae..fd602ea7e0 100644
--- a/board/xes/xpedite517x/ddr.c
+++ b/board/xes/xpedite517x/ddr.c
@@ -7,8 +7,8 @@
 
 #include <common.h>
 #include <i2c.h>
-#include <asm/fsl_ddr_sdram.h>
-#include <asm/fsl_ddr_dimm_params.h>
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr_dimm_params.h>
 
 void get_spd(ddr2_spd_eeprom_t *spd, u8 i2c_address)
 {
diff --git a/board/xes/xpedite517x/xpedite517x.c b/board/xes/xpedite517x/xpedite517x.c
index 1782042510..b7ad349502 100644
--- a/board/xes/xpedite517x/xpedite517x.c
+++ b/board/xes/xpedite517x/xpedite517x.c
@@ -6,7 +6,7 @@
 
 #include <common.h>
 #include <asm/processor.h>
-#include <asm/fsl_ddr_sdram.h>
+#include <fsl_ddr_sdram.h>
 #include <asm/mmu.h>
 #include <asm/io.h>
 #include <fdt_support.h>
diff --git a/board/xes/xpedite520x/Makefile b/board/xes/xpedite520x/Makefile
index 6c1b85b03b..14841b9c87 100644
--- a/board/xes/xpedite520x/Makefile
+++ b/board/xes/xpedite520x/Makefile
@@ -7,27 +7,7 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS-y	+= $(BOARD).o
-COBJS-y	+= ddr.o
-COBJS-y	+= law.o
-COBJS-y	+= tlb.o
-
-SRCS	:= $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS-y))
-SOBJS	:= $(addprefix $(obj),$(SOBJS-y))
-
-$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	+= xpedite520x.o
+obj-y	+= ddr.o
+obj-y	+= law.o
+obj-y	+= tlb.o
diff --git a/board/xes/xpedite520x/ddr.c b/board/xes/xpedite520x/ddr.c
index 3671cb8af9..5c5eadc93f 100644
--- a/board/xes/xpedite520x/ddr.c
+++ b/board/xes/xpedite520x/ddr.c
@@ -9,8 +9,8 @@
 #include <common.h>
 #include <i2c.h>
 
-#include <asm/fsl_ddr_sdram.h>
-#include <asm/fsl_ddr_dimm_params.h>
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr_dimm_params.h>
 
 void get_spd(ddr2_spd_eeprom_t *spd, unsigned char i2c_address)
 {
diff --git a/board/xes/xpedite537x/Makefile b/board/xes/xpedite537x/Makefile
index 64f996f5a9..2dca0d7517 100644
--- a/board/xes/xpedite537x/Makefile
+++ b/board/xes/xpedite537x/Makefile
@@ -7,27 +7,7 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS-y	+= $(BOARD).o
-COBJS-y	+= ddr.o
-COBJS-y	+= law.o
-COBJS-y	+= tlb.o
-
-SRCS	:= $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS-y))
-SOBJS	:= $(addprefix $(obj),$(SOBJS-y))
-
-$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	+= xpedite537x.o
+obj-y	+= ddr.o
+obj-y	+= law.o
+obj-y	+= tlb.o
diff --git a/board/xes/xpedite537x/ddr.c b/board/xes/xpedite537x/ddr.c
index f41ae73755..56b5a187d8 100644
--- a/board/xes/xpedite537x/ddr.c
+++ b/board/xes/xpedite537x/ddr.c
@@ -8,8 +8,8 @@
 #include <common.h>
 #include <i2c.h>
 
-#include <asm/fsl_ddr_sdram.h>
-#include <asm/fsl_ddr_dimm_params.h>
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr_dimm_params.h>
 
 void get_spd(ddr2_spd_eeprom_t *spd, u8 i2c_address)
 {
diff --git a/board/xes/xpedite550x/Makefile b/board/xes/xpedite550x/Makefile
index c9b2deaf59..1a3fe7635d 100644
--- a/board/xes/xpedite550x/Makefile
+++ b/board/xes/xpedite550x/Makefile
@@ -4,27 +4,7 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS-y	+= $(BOARD).o
-COBJS-y	+= ddr.o
-COBJS-y	+= law.o
-COBJS-y	+= tlb.o
-
-SRCS	:= $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS-y))
-SOBJS	:= $(addprefix $(obj),$(SOBJS-y))
-
-$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	+= xpedite550x.o
+obj-y	+= ddr.o
+obj-y	+= law.o
+obj-y	+= tlb.o
diff --git a/board/xes/xpedite550x/ddr.c b/board/xes/xpedite550x/ddr.c
index a03a96b182..0c0605e3a9 100644
--- a/board/xes/xpedite550x/ddr.c
+++ b/board/xes/xpedite550x/ddr.c
@@ -8,8 +8,8 @@
 #include <common.h>
 #include <i2c.h>
 
-#include <asm/fsl_ddr_sdram.h>
-#include <asm/fsl_ddr_dimm_params.h>
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr_dimm_params.h>
 
 void get_spd(ddr3_spd_eeprom_t *spd, u8 i2c_address)
 {
@@ -108,7 +108,7 @@ void fsl_ddr_board_options(memctl_options_t *popts,
 		    ddr_freq <= pbsp->datarate_mhz_high) {
 			popts->clk_adjust = pbsp->clk_adjust;
 			popts->cpo_override = pbsp->cpo;
-			popts->twoT_en = 0;
+			popts->twot_en = 0;
 			break;
 		}
 		pbsp++;
diff --git a/board/xilinx/microblaze-generic/Makefile b/board/xilinx/microblaze-generic/Makefile
index 6a25ce6c18..22c8bef117 100644
--- a/board/xilinx/microblaze-generic/Makefile
+++ b/board/xilinx/microblaze-generic/Makefile
@@ -5,24 +5,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	= $(BOARD).o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(OBJS) $(SOBJS)
-	$(call cmd_link_o_target, $^)
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	= microblaze-generic.o
diff --git a/board/xilinx/ml507/.gitignore b/board/xilinx/ml507/.gitignore
deleted file mode 100644
index f6418a0c50..0000000000
--- a/board/xilinx/ml507/.gitignore
+++ /dev/null
@@ -1 +0,0 @@
-/config.tmp
diff --git a/board/xilinx/ml507/Makefile b/board/xilinx/ml507/Makefile
index 51b777c234..9a3809f3c0 100644
--- a/board/xilinx/ml507/Makefile
+++ b/board/xilinx/ml507/Makefile
@@ -6,6 +6,6 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-COBJS	+= $(BOARD).o
+obj-y	+= ml507.o
 
-include $(SRCTREE)/board/xilinx/ppc440-generic/Makefile
+include $(srctree)/board/xilinx/ppc440-generic/Makefile
diff --git a/board/xilinx/ppc405-generic/.gitignore b/board/xilinx/ppc405-generic/.gitignore
deleted file mode 100644
index b644f59941..0000000000
--- a/board/xilinx/ppc405-generic/.gitignore
+++ /dev/null
@@ -1 +0,0 @@
-config.tmp
diff --git a/board/xilinx/ppc405-generic/Makefile b/board/xilinx/ppc405-generic/Makefile
index cc161ae39d..c9da870657 100644
--- a/board/xilinx/ppc405-generic/Makefile
+++ b/board/xilinx/ppc405-generic/Makefile
@@ -9,27 +9,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-ifneq ($(OBJTREE),$(SRCTREE))
-$(shell mkdir -p $(obj)../../xilinx/ppc405-generic)
-endif
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	+= ../../xilinx/ppc405-generic/xilinx_ppc405_generic.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	+= ../../xilinx/ppc405-generic/xilinx_ppc405_generic.o
diff --git a/board/xilinx/ppc440-generic/.gitignore b/board/xilinx/ppc440-generic/.gitignore
deleted file mode 100644
index f6418a0c50..0000000000
--- a/board/xilinx/ppc440-generic/.gitignore
+++ /dev/null
@@ -1 +0,0 @@
-/config.tmp
diff --git a/board/xilinx/ppc440-generic/Makefile b/board/xilinx/ppc440-generic/Makefile
index 597afdee67..0acd95d6e4 100644
--- a/board/xilinx/ppc440-generic/Makefile
+++ b/board/xilinx/ppc440-generic/Makefile
@@ -9,28 +9,5 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-ifneq ($(OBJTREE),$(SRCTREE))
-$(shell mkdir -p $(obj)../../xilinx/ppc440-generic)
-endif
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	+= ../../xilinx/ppc440-generic/xilinx_ppc440_generic.o
-SOBJS 	+= ../../xilinx/ppc440-generic/init.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	+= ../../xilinx/ppc440-generic/xilinx_ppc440_generic.o
+extra-y 	+= ../../xilinx/ppc440-generic/init.o
diff --git a/board/xilinx/zynq/Makefile b/board/xilinx/zynq/Makefile
index 98a5046f45..3f19a1cd8b 100644
--- a/board/xilinx/zynq/Makefile
+++ b/board/xilinx/zynq/Makefile
@@ -5,31 +5,5 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS-y	:= board.o
-
-COBJS	:= $(sort $(COBJS-y))
-
-SRCS	:= $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-clean:
-	rm -f $(OBJS)
-
-distclean:	clean
-	rm -f $(LIB) core *.bak $(obj).depend
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	:= board.o
+obj-$(CONFIG_SPL_BUILD)	+= ps7_init.o
diff --git a/board/xilinx/zynq/board.c b/board/xilinx/zynq/board.c
index 5119c09037..485a5e4a24 100644
--- a/board/xilinx/zynq/board.c
+++ b/board/xilinx/zynq/board.c
@@ -5,6 +5,7 @@
  */
 
 #include <common.h>
+#include <fdtdec.h>
 #include <netdev.h>
 #include <zynqpl.h>
 #include <asm/arch/hardware.h>
@@ -17,6 +18,7 @@ Xilinx_desc fpga;
 
 /* It can be done differently */
 Xilinx_desc fpga010 = XILINX_XC7Z010_DESC(0x10);
+Xilinx_desc fpga015 = XILINX_XC7Z015_DESC(0x15);
 Xilinx_desc fpga020 = XILINX_XC7Z020_DESC(0x20);
 Xilinx_desc fpga030 = XILINX_XC7Z030_DESC(0x30);
 Xilinx_desc fpga045 = XILINX_XC7Z045_DESC(0x45);
@@ -34,6 +36,9 @@ int board_init(void)
 	case XILINX_ZYNQ_7010:
 		fpga = fpga010;
 		break;
+	case XILINX_ZYNQ_7015:
+		fpga = fpga015;
+		break;
 	case XILINX_ZYNQ_7020:
 		fpga = fpga020;
 		break;
@@ -49,8 +54,6 @@ int board_init(void)
 	}
 #endif
 
-	icache_enable();
-
 #ifdef CONFIG_FPGA
 	fpga_init();
 	fpga_add(fpga_xilinx, &fpga);
@@ -59,8 +62,26 @@ int board_init(void)
 	return 0;
 }
 
+int board_late_init(void)
+{
+	switch ((zynq_slcr_get_boot_mode()) & ZYNQ_BM_MASK) {
+	case ZYNQ_BM_NOR:
+		setenv("modeboot", "norboot");
+		break;
+	case ZYNQ_BM_SD:
+		setenv("modeboot", "sdboot");
+		break;
+	case ZYNQ_BM_JTAG:
+		setenv("modeboot", "jtagboot");
+		break;
+	default:
+		setenv("modeboot", "");
+		break;
+	}
+
+	return 0;
+}
 
-#ifdef CONFIG_CMD_NET
 int board_eth_init(bd_t *bis)
 {
 	u32 ret = 0;
@@ -94,7 +115,6 @@ int board_eth_init(bd_t *bis)
 #endif
 	return ret;
 }
-#endif
 
 #ifdef CONFIG_CMD_MMC
 int board_mmc_init(bd_t *bd)
@@ -115,8 +135,27 @@ int board_mmc_init(bd_t *bd)
 
 int dram_init(void)
 {
+#ifdef CONFIG_OF_CONTROL
+	int node;
+	fdt_addr_t addr;
+	fdt_size_t size;
+	const void *blob = gd->fdt_blob;
+
+	node = fdt_node_offset_by_prop_value(blob, -1, "device_type",
+					     "memory", 7);
+	if (node == -FDT_ERR_NOTFOUND) {
+		debug("ZYNQ DRAM: Can't get memory node\n");
+		return -1;
+	}
+	addr = fdtdec_get_addr_size(blob, node, "reg", &size);
+	if (addr == FDT_ADDR_T_NONE || size == 0) {
+		debug("ZYNQ DRAM: Can't get base address or size\n");
+		return -1;
+	}
+	gd->ram_size = size;
+#else
 	gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
-
+#endif
 	zynq_ddrc_init();
 
 	return 0;
diff --git a/board/xilinx/zynq/ps7_init.c b/board/xilinx/zynq/ps7_init.c
new file mode 100644
index 0000000000..c47da09b9e
--- /dev/null
+++ b/board/xilinx/zynq/ps7_init.c
@@ -0,0 +1,12 @@
+/*
+ * (C) Copyright 2014 Xilinx, Inc. Michal Simek
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+#include <common.h>
+#include <asm/arch/spl.h>
+
+__weak void ps7_init(void)
+{
+	puts("Please copy ps7_init.c/h from hw project\n");
+}
diff --git a/board/zeus/Makefile b/board/zeus/Makefile
index 8d133e24a0..aa3658a370 100644
--- a/board/zeus/Makefile
+++ b/board/zeus/Makefile
@@ -5,25 +5,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	= $(BOARD).o update.o
-SOBJS   =
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(OBJS) $(SOBJS)
-	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	= zeus.o update.o
diff --git a/board/zipitz2/Makefile b/board/zipitz2/Makefile
index eed343b97a..855f6bcda8 100644
--- a/board/zipitz2/Makefile
+++ b/board/zipitz2/Makefile
@@ -1,4 +1,3 @@
-
 #
 # Copyright (C) 2009
 # Marek Vasut <marek.vasut@gmail.com>
@@ -8,23 +7,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	:= zipitz2.o
-
-SRCS	:= $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	:= zipitz2.o
diff --git a/board/zpc1900/Makefile b/board/zpc1900/Makefile
index c573be952c..e636365777 100644
--- a/board/zpc1900/Makefile
+++ b/board/zpc1900/Makefile
@@ -5,24 +5,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	:= $(BOARD).o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	:= zpc1900.o
diff --git a/boards.cfg b/boards.cfg
index 1eb079209c..8d33427759 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -43,6 +43,10 @@
 # Status, Arch, CPU:SPLCPU, SoC, Vendor, Board name, Target, Options, Maintainers
 ###########################################################################################################
 
+Active  aarch64     armv8          -           armltd          vexpress64          vexpress_aemv8a                      vexpress_aemv8a:ARM64                                                                                                             David Feng <fenghua@phytium.com.cn>
+Active  arc         arc700         -           synopsys        -                   axs101                               -                                                                                                                                 Alexey Brodkin <abrodkin@synopsys.com>
+Active  arc         arc700         -           synopsys        <none>              arcangel4                            -                                                                                                                                 Alexey Brodkin <abrodkin@synopsys.com>
+Active  arc         arc700         -           synopsys        <none>              arcangel4-be                         -                                                                                                                                 Alexey Brodkin <abrodkin@synopsys.com>
 Active  arm         arm1136        -           armltd          integrator          integratorcp_cm1136                  integratorcp:CM1136                                                                                                               Linus Walleij <linus.walleij@linaro.org>
 Active  arm         arm1136        mx31        -               -                   imx31_phycore                        -                                                                                                                                 -
 Active  arm         arm1136        mx31        davedenx        -                   qong                                 -                                                                                                                                 Wolfgang Denk <wd@denx.de>
@@ -59,17 +63,15 @@ Active  arm         arm720t        -           armltd          integrator
 Active  arm         arm920t        -           armltd          integrator          integratorap_cm920t                  integratorap:CM920T                                                                                                               Linus Walleij <linus.walleij@linaro.org>
 Active  arm         arm920t        -           armltd          integrator          integratorcp_cm920t                  integratorcp:CM920T                                                                                                               Linus Walleij <linus.walleij@linaro.org>
 Active  arm         arm920t        a320        faraday         -                   a320evb                              -                                                                                                                                 Po-Yu Chuang <ratbert@faraday-tech.com>
-Active  arm         arm920t        at91        atmel           at91rm9200ek        at91rm9200ek                         at91rm9200ek                                                                                                                      Andreas Bießmann <andreas.devel@gmail.com>
+Active  arm         arm920t        at91        atmel           at91rm9200ek        at91rm9200ek                         -                                                                                                                                 Andreas Bießmann <andreas.devel@gmail.com>
 Active  arm         arm920t        at91        atmel           at91rm9200ek        at91rm9200ek_ram                     at91rm9200ek:RAMBOOT                                                                                                              Andreas Bießmann <andreas.devel@gmail.com>
-Active  arm         arm920t        at91        BuS             eb_cpux9k2          eb_cpux9k2                           eb_cpux9k2                                                                                                                        Jens Scharsig <esw@bus-elektronik.de>
+Active  arm         arm920t        at91        BuS             eb_cpux9k2          eb_cpux9k2                           -                                                                                                                                 Jens Scharsig <esw@bus-elektronik.de>
 Active  arm         arm920t        at91        BuS             eb_cpux9k2          eb_cpux9k2_ram                       eb_cpux9k2:RAMBOOT                                                                                                                Jens Scharsig <esw@bus-elektronik.de>
-Active  arm         arm920t        at91        eukrea          cpuat91             cpuat91                              cpuat91                                                                                                                           Eric Benard <eric@eukrea.com>
+Active  arm         arm920t        at91        eukrea          cpuat91             cpuat91                              -                                                                                                                                 Eric Benard <eric@eukrea.com>
 Active  arm         arm920t        at91        eukrea          cpuat91             cpuat91_ram                          cpuat91:RAMBOOT                                                                                                                   Eric Benard <eric@eukrea.com>
-Active  arm         arm920t        imx         -               -                   mx1ads                               -                                                                                                                                 -
 Active  arm         arm920t        imx         -               -                   scb9328                              -                                                                                                                                 Torsten Koschorrek <koschorrek@synertronixx.de>
 Active  arm         arm920t        ks8695      -               -                   cm4008                               -                                                                                                                                 Greg Ungerer <greg.ungerer@opengear.com>
 Active  arm         arm920t        ks8695      -               -                   cm41xx                               -                                                                                                                                 -
-Active  arm         arm920t        s3c24x0     friendlyarm     mini2440            mini2440                             -                                                                                                                                 Gabriel Huau <contact@huau-gabriel.fr>
 Active  arm         arm920t        s3c24x0     mpl             vcma9               VCMA9                                -                                                                                                                                 David Müller <d.mueller@elsoft.ch>
 Active  arm         arm920t        s3c24x0     samsung         -                   smdk2410                             -                                                                                                                                 David Müller <d.mueller@elsoft.ch>
 Active  arm         arm926ejs      -           armltd          integrator          integratorap_cm926ejs                integratorap:CM926EJ_S                                                                                                            Linus Walleij <linus.walleij@linaro.org>
@@ -119,6 +121,7 @@ Active  arm         arm926ejs      at91        calao           tny_a9260
 Active  arm         arm926ejs      at91        calao           tny_a9260           tny_a9260_nandflash                  tny_a9260:AT91SAM9260,SYS_USE_NANDFLASH                                                                                           Albin Tonnerre <albin.tonnerre@free-electrons.com>
 Active  arm         arm926ejs      at91        calao           tny_a9260           tny_a9g20_eeprom                     tny_a9260:AT91SAM9G20,SYS_USE_EEPROM                                                                                              Albin Tonnerre <albin.tonnerre@free-electrons.com>
 Active  arm         arm926ejs      at91        calao           tny_a9260           tny_a9g20_nandflash                  tny_a9260:AT91SAM9G20,SYS_USE_NANDFLASH                                                                                           Albin Tonnerre <albin.tonnerre@free-electrons.com>
+Active  arm         arm926ejs      at91        calao           usb_a9263           usb_a9263_dataflash                  usb_a9263:AT91SAM9263,SYS_USE_DATAFLASH                                                                                           Mateusz Kulikowski <mateusz.kulikowski@gmail.com>
 Active  arm         arm926ejs      at91        egnite          ethernut5           ethernut5                            ethernut5:AT91SAM9XE                                                                                                              egnite GmbH <info@egnite.de>
 Active  arm         arm926ejs      at91        emk             top9000             top9000eval_xe                       top9000:EVAL9000                                                                                                                  Reinhard Meyer <reinhard.meyer@emk-elektronik.de>
 Active  arm         arm926ejs      at91        emk             top9000             top9000su_xe                         top9000:SU9000                                                                                                                    Reinhard Meyer <reinhard.meyer@emk-elektronik.de>
@@ -137,9 +140,12 @@ Active  arm         arm926ejs      at91        eukrea          cpu9260
 Active  arm         arm926ejs      at91        ronetix         pm9261              pm9261                               pm9261:AT91SAM9261                                                                                                                Ilko Iliev <iliev@ronetix.at>
 Active  arm         arm926ejs      at91        ronetix         pm9263              pm9263                               pm9263:AT91SAM9263                                                                                                                Ilko Iliev <iliev@ronetix.at>
 Active  arm         arm926ejs      at91        ronetix         pm9g45              pm9g45                               pm9g45:AT91SAM9G45                                                                                                                Ilko Iliev <iliev@ronetix.at>
+Active  arm         arm926ejs      at91        siemens         corvus              corvus                               corvus:AT91SAM9M10G45,SYS_USE_NANDFLASH                                                                                           Heiko Schocher <hs@denx.de>
+Active  arm         arm926ejs      at91        siemens         taurus              axm                                  taurus:AT91SAM9G20,MACH_TYPE=2068,BOARD_AXM                                                                                       Heiko Schocher <hs@denx.de>
+Active  arm         arm926ejs      at91        siemens         taurus              taurus                               taurus:AT91SAM9G20,MACH_TYPE=2067,BOARD_TAURUS                                                                                    Heiko Schocher <hs@denx.de>
 Active  arm         arm926ejs      at91        taskit          stamp9g20           portuxg20                            stamp9g20:AT91SAM9G20,PORTUXG20                                                                                                   Markus Hubig <mhubig@imko.de>
 Active  arm         arm926ejs      at91        taskit          stamp9g20           stamp9g20                            stamp9g20:AT91SAM9G20                                                                                                             Markus Hubig <mhubig@imko.de>
-Active  arm         arm926ejs      davinci     ait             cam_enc_4xx         cam_enc_4xx                          cam_enc_4xx                                                                                                                       Heiko Schocher <hs@denx.de>
+Active  arm         arm926ejs      davinci     ait             cam_enc_4xx         cam_enc_4xx                          -                                                                                                                                 Heiko Schocher <hs@denx.de>
 Active  arm         arm926ejs      davinci     Barix           ipam390             ipam390                              -                                                                                                                                 Heiko Schocher <hs@denx.de>
 Active  arm         arm926ejs      davinci     davinci         da8xxevm            da830evm                             -                                                                                                                                 Nick Thompson <nick.thompson@gefanuc.com>
 Active  arm         arm926ejs      davinci     davinci         da8xxevm            da850_am18xxevm                      da850evm:DA850_AM18X_EVM,MAC_ADDR_IN_EEPROM,SYS_I2C_EEPROM_ADDR_LEN=2,SYS_I2C_EEPROM_ADDR=0x50                                    Sudhakar Rajashekhara <sudhakar.raj@ti.com>
@@ -166,9 +172,11 @@ Active  arm         arm926ejs      kirkwood    d-link          -
 Active  arm         arm926ejs      kirkwood    iomega          -                   iconnect                             -                                                                                                                                 Luka Perkov <luka@openwrt.org>
 Active  arm         arm926ejs      kirkwood    karo            tk71                tk71                                 -                                                                                                                                 -
 Active  arm         arm926ejs      kirkwood    keymile         km_arm              km_kirkwood                          km_kirkwood:KM_KIRKWOOD                                                                                                           Valentin Longchamp <valentin.longchamp@keymile.com>
+Active  arm         arm926ejs      kirkwood    keymile         km_arm              km_kirkwood_128m16                   km_kirkwood:KM_KIRKWOOD_128M16                                                                                                    Valentin Longchamp <valentin.longchamp@keymile.com>
 Active  arm         arm926ejs      kirkwood    keymile         km_arm              km_kirkwood_pci                      km_kirkwood:KM_KIRKWOOD_PCI                                                                                                       Valentin Longchamp <valentin.longchamp@keymile.com>
 Active  arm         arm926ejs      kirkwood    keymile         km_arm              kmcoge5un                            km_kirkwood:KM_COGE5UN                                                                                                            Valentin Longchamp <valentin.longchamp@keymile.com>
 Active  arm         arm926ejs      kirkwood    keymile         km_arm              kmnusa                               km_kirkwood:KM_NUSA                                                                                                               Valentin Longchamp <valentin.longchamp@keymile.com>
+Active  arm         arm926ejs      kirkwood    keymile         km_arm              kmsugp1                              km_kirkwood:KM_SUGP1                                                                                                              Valentin Longchamp <valentin.longchamp@keymile.com>
 Active  arm         arm926ejs      kirkwood    keymile         km_arm              kmsuv31                              km_kirkwood:KM_SUV31                                                                                                              Valentin Longchamp <valentin.longchamp@keymile.com>
 Active  arm         arm926ejs      kirkwood    keymile         km_arm              mgcoge3un                            km_kirkwood:KM_MGCOGE3UN                                                                                                          Valentin Longchamp <valentin.longchamp@keymile.com>
 Active  arm         arm926ejs      kirkwood    keymile         km_arm              portl2                               km_kirkwood:KM_PORTL2                                                                                                             Valentin Longchamp <valentin.longchamp@keymile.com>
@@ -196,28 +204,26 @@ Active  arm         arm926ejs      mb86r0x     syteco          jadecpu
 Active  arm         arm926ejs      mx25        freescale       mx25pdk             mx25pdk                              mx25pdk:IMX_CONFIG=board/freescale/mx25pdk/imximage.cfg                                                                           Fabio Estevam <fabio.estevam@freescale.com>
 Active  arm         arm926ejs      mx25        karo            tx25                tx25                                 -                                                                                                                                 John Rigby <jcrigby@gmail.com>
 Active  arm         arm926ejs      mx25        syteco          zmx25               zmx25                                -                                                                                                                                 Matthias Weisser <weisserm@arcor.de>
-Active  arm         arm926ejs      mx27        armadeus        apf27               apf27                                -                                                                                                                                 Philippe Reynes <tremyfr@yahoo.fr>:Eric Jarrige <eric.jarrige@armadeus.org> 
+Active  arm         arm926ejs      mx27        armadeus        apf27               apf27                                -                                                                                                                                 Philippe Reynes <tremyfr@yahoo.fr>:Eric Jarrige <eric.jarrige@armadeus.org>
 Active  arm         arm926ejs      mx27        logicpd         imx27lite           imx27lite                            -                                                                                                                                 Wolfgang Denk <wd@denx.de>
 Active  arm         arm926ejs      mx27        logicpd         imx27lite           magnesium                            -                                                                                                                                 Heiko Schocher <hs@denx.de>
-Active  arm         arm926ejs      mxs         bluegiga        apx4devkit          apx4devkit                           apx4devkit                                                                                                                        Lauri Hintsala <lauri.hintsala@bluegiga.com>
+Active  arm         arm926ejs      mxs         bluegiga        apx4devkit          apx4devkit                           -                                                                                                                                 Lauri Hintsala <lauri.hintsala@bluegiga.com>
 Active  arm         arm926ejs      mxs         creative        xfi3                xfi3                                 -                                                                                                                                 Marek Vasut <marek.vasut@gmail.com>
-Active  arm         arm926ejs      mxs         denx            m28evk              m28evk                               m28evk                                                                                                                            Marek Vasut <marek.vasut@gmail.com>
-Active  arm         arm926ejs      mxs         freescale       mx23evk             mx23evk                              mx23evk                                                                                                                           Otavio Salvador <otavio@ossystems.com.br>
+Active  arm         arm926ejs      mxs         denx            m28evk              m28evk                               -                                                                                                                                 Marek Vasut <marek.vasut@gmail.com>
+Active  arm         arm926ejs      mxs         freescale       mx23evk             mx23evk                              -                                                                                                                                 Otavio Salvador <otavio@ossystems.com.br>
 Active  arm         arm926ejs      mxs         freescale       mx28evk             mx28evk                              mx28evk:ENV_IS_IN_MMC                                                                                                             Fabio Estevam <fabio.estevam@freescale.com>
 Active  arm         arm926ejs      mxs         freescale       mx28evk             mx28evk_auart_console                mx28evk:MXS_AUART,MXS_AUART_BASE=MXS_UARTAPP3_BASE,ENV_IS_IN_MMC                                                                  Fabio Estevam <fabio.estevam@freescale.com>
 Active  arm         arm926ejs      mxs         freescale       mx28evk             mx28evk_nand                         mx28evk:ENV_IS_IN_NAND                                                                                                            Fabio Estevam <fabio.estevam@freescale.com>
-Active  arm         arm926ejs      mxs         olimex          mx23_olinuxino      mx23_olinuxino                       mx23_olinuxino                                                                                                                    Marek Vasut <marek.vasut@gmail.com>
+Active  arm         arm926ejs      mxs         olimex          mx23_olinuxino      mx23_olinuxino                       -                                                                                                                                 Marek Vasut <marek.vasut@gmail.com>
+Active  arm         arm926ejs      mxs         ppcag           bg0900              bg0900                               -                                                                                                                                 Marek Vasut <marex@denx.de>
 Active  arm         arm926ejs      mxs         sandisk         sansa_fuze_plus     sansa_fuze_plus                      -                                                                                                                                 Marek Vasut <marek.vasut@gmail.com>
 Active  arm         arm926ejs      mxs         schulercontrol  sc_sps_1            sc_sps_1                             -                                                                                                                                 Marek Vasut <marek.vasut@gmail.com>
 Active  arm         arm926ejs      nomadik     st              nhk8815             nhk8815                              -                                                                                                                                 Nomadik Linux Team <STN_WMM_nomadik_linux@list.st.com>:Alessandro Rubini <rubini@unipv.it>
 Active  arm         arm926ejs      nomadik     st              nhk8815             nhk8815_onenand                      nhk8815:BOOT_ONENAND                                                                                                              Nomadik Linux Team <STN_WMM_nomadik_linux@list.st.com>:Alessandro Rubini <rubini@unipv.it>
 Active  arm         arm926ejs      omap        ti              -                   omap5912osk                          -                                                                                                                                 Rishi Bhattacharya <rishi@ti.com>
-Active  arm         arm926ejs      omap        ti              omap730p2           omap730p2                            omap730p2:CS3_BOOT                                                                                                                Dave Peverley <dpeverley@mpc-data.co.uk>
-Active  arm         arm926ejs      omap        ti              omap730p2           omap730p2_cs0boot                    omap730p2:CS0_BOOT                                                                                                                Dave Peverley <dpeverley@mpc-data.co.uk>
-Active  arm         arm926ejs      omap        ti              omap730p2           omap730p2_cs3boot                    omap730p2:CS3_BOOT                                                                                                                Dave Peverley <dpeverley@mpc-data.co.uk>
 Active  arm         arm926ejs      orion5x     LaCie           -                   edminiv2                             -                                                                                                                                 Albert ARIBAUD <albert.u.boot@aribaud.net>
 Active  arm         arm926ejs      pantheon    Marvell         -                   dkb                                  -                                                                                                                                 Lei Wen <leiwen@marvell.com>
-Active  arm         arm926ejs      spear       spear           -                   x600                                 x600                                                                                                                              Stefan Roese <sr@denx.de>
+Active  arm         arm926ejs      spear       spear           -                   x600                                 -                                                                                                                                 Stefan Roese <sr@denx.de>
 Active  arm         arm926ejs      spear       spear           spear300            spear300                             spear3xx_evb:spear300                                                                                                             Vipin Kumar <vipin.kumar@st.com>
 Active  arm         arm926ejs      spear       spear           spear300            spear300_nand                        spear3xx_evb:spear300,nand                                                                                                        -
 Active  arm         arm926ejs      spear       spear           spear300            spear300_usbtty                      spear3xx_evb:spear300,usbtty                                                                                                      -
@@ -246,36 +252,47 @@ Active  arm         arm946es       -           armltd          integrator
 Active  arm         armv7          -           armltd          vexpress            vexpress_ca15_tc2                    -                                                                                                                                 -
 Active  arm         armv7          -           armltd          vexpress            vexpress_ca5x2                       -                                                                                                                                 Matt Waddel <matt.waddel@linaro.org>
 Active  arm         armv7          -           armltd          vexpress            vexpress_ca9x4                       -                                                                                                                                 Matt Waddel <matt.waddel@linaro.org>
-Active  arm         armv7          am33xx      isee            igep0033            igep0033                             -                                                                                                                                 Enric Balletbo i Serra <eballetbo@iseebcn.com>
-Active  arm         armv7          am33xx      phytec          pcm051              pcm051                               pcm051                                                                                                                            Lars Poeschel <poeschel@lemonage.de>
+Active  arm         armv7          am33xx      BuR             kwb                 kwb                                  kwb:SERIAL1,CONS_INDEX=1                                                                                                          Hannes Petermaier <hannes.petermaier@br-automation.com>
+Active  arm         armv7          am33xx      BuR             tseries             tseries_mmc                          tseries:SERIAL1,CONS_INDEX=1,EMMC_BOOT                                                                                            Hannes Petermaier <hannes.petermaier@br-automation.com>
+Active  arm         armv7          am33xx      BuR             tseries             tseries_nand                         tseries:SERIAL1,CONS_INDEX=1,NAND                                                                                                 Hannes Petermaier <hannes.petermaier@br-automation.com>
+Active  arm         armv7          am33xx      BuR             tseries             tseries_spi                          tseries:SERIAL1,CONS_INDEX=1,SPI_BOOT,EMMC_BOOT                                                                                   Hannes Petermaier <hannes.petermaier@br-automation.com>
+Active  arm         armv7          am33xx      compulab        cm_t335             cm_t335                              -                                                                                                                                 Igor Grinberg <grinberg@compulab.co.il>
+Active  arm         armv7          am33xx      isee            igep0033            am335x_igep0033                      -                                                                                                                                 Enric Balletbo i Serra <eballetbo@iseebcn.com>
+Active  arm         armv7          am33xx      phytec          pcm051              pcm051_rev1                          pcm051:REV1                                                                                                                       Lars Poeschel <poeschel@lemonage.de>
+Active  arm         armv7          am33xx      phytec          pcm051              pcm051_rev3                          pcm051:REV3                                                                                                                       Lars Poeschel <poeschel@lemonage.de>
 Active  arm         armv7          am33xx      siemens         dxr2                dxr2                                 -                                                                                                                                 Roger Meier <r.meier@siemens.com>
 Active  arm         armv7          am33xx      siemens         pxm2                pxm2                                 -                                                                                                                                 Roger Meier <r.meier@siemens.com>
 Active  arm         armv7          am33xx      siemens         rut                 rut                                  -                                                                                                                                 Roger Meier <r.meier@siemens.com>
+Active  arm         armv7          am33xx      silica          pengwyn             pengwyn                              -                                                                                                                                 Lothar Felten <lothar.felten@gmail.com>
 Active  arm         armv7          am33xx      ti              am335x              am335x_boneblack                     am335x_evm:SERIAL1,CONS_INDEX=1,EMMC_BOOT                                                                                         Tom Rini <trini@ti.com>
 Active  arm         armv7          am33xx      ti              am335x              am335x_evm                           am335x_evm:SERIAL1,CONS_INDEX=1,NAND                                                                                              Tom Rini <trini@ti.com>
 Active  arm         armv7          am33xx      ti              am335x              am335x_evm_nor                       am335x_evm:SERIAL1,CONS_INDEX=1,NAND,NOR                                                                                          Tom Rini <trini@ti.com>
 Active  arm         armv7          am33xx      ti              am335x              am335x_evm_norboot                   am335x_evm:SERIAL1,CONS_INDEX=1,NOR,NOR_BOOT                                                                                      Tom Rini <trini@ti.com>
 Active  arm         armv7          am33xx      ti              am335x              am335x_evm_spiboot                   am335x_evm:SERIAL1,CONS_INDEX=1,SPI_BOOT                                                                                          Tom Rini <trini@ti.com>
-Active  arm         armv7          am33xx      ti              am335x              am335x_evm_uart1                     am335x_evm:SERIAL2,CONS_INDEX=1,NAND                                                                                              Tom Rini <trini@ti.com>
-Active  arm         armv7          am33xx      ti              am335x              am335x_evm_uart2                     am335x_evm:SERIAL3,CONS_INDEX=1,NAND                                                                                              Tom Rini <trini@ti.com>
-Active  arm         armv7          am33xx      ti              am335x              am335x_evm_uart3                     am335x_evm:SERIAL4,CONS_INDEX=1,NAND                                                                                              Tom Rini <trini@ti.com>
-Active  arm         armv7          am33xx      ti              am335x              am335x_evm_uart4                     am335x_evm:SERIAL5,CONS_INDEX=1,NAND                                                                                              Tom Rini <trini@ti.com>
-Active  arm         armv7          am33xx      ti              am335x              am335x_evm_uart5                     am335x_evm:SERIAL6,CONS_INDEX=1,NAND                                                                                              Tom Rini <trini@ti.com>
+Active  arm         armv7          am33xx      ti              am335x              am335x_evm_uart1                     am335x_evm:SERIAL2,CONS_INDEX=2,NAND                                                                                              Tom Rini <trini@ti.com>
+Active  arm         armv7          am33xx      ti              am335x              am335x_evm_uart2                     am335x_evm:SERIAL3,CONS_INDEX=3,NAND                                                                                              Tom Rini <trini@ti.com>
+Active  arm         armv7          am33xx      ti              am335x              am335x_evm_uart3                     am335x_evm:SERIAL4,CONS_INDEX=4,NAND                                                                                              Tom Rini <trini@ti.com>
+Active  arm         armv7          am33xx      ti              am335x              am335x_evm_uart4                     am335x_evm:SERIAL5,CONS_INDEX=5,NAND                                                                                              Tom Rini <trini@ti.com>
+Active  arm         armv7          am33xx      ti              am335x              am335x_evm_uart5                     am335x_evm:SERIAL6,CONS_INDEX=6,NAND                                                                                              Tom Rini <trini@ti.com>
 Active  arm         armv7          am33xx      ti              am335x              am335x_evm_usbspl                    am335x_evm:SERIAL1,CONS_INDEX=1,NAND,SPL_USBETH_SUPPORT                                                                           Tom Rini <trini@ti.com>
-Active  arm         armv7          am33xx      ti              am43xx              am43xx_evm                           am43xx_evm:SERIAL1,CONS_INDEX=1                                                                                                   -
-Active  arm         armv7          am33xx      ti              ti814x              ti814x_evm                           -                                                                                                                                 Matt Porter <mporter@ti.com>
+Active  arm         armv7          am33xx      ti              am43xx              am43xx_evm                           am43xx_evm:SERIAL1,CONS_INDEX=1                                                                                                   Lokesh Vutla <lokeshvutla@ti.com>
+Active  arm         armv7          am33xx      ti              ti814x              ti814x_evm                           -                                                                                                                                 Matt Porter <matt.porter@linaro.org>
 Active  arm         armv7          am33xx      ti              ti816x              ti816x_evm                           -                                                                                                                                 -
+Active  arm         armv7          at91        atmel           sama5d3_xplained    sama5d3_xplained_mmc                 sama5d3_xplained:SAMA5D3,SYS_USE_MMC                                                                                              Bo Shen <voice.shen@atmel.com>
+Active  arm         armv7          at91        atmel           sama5d3_xplained    sama5d3_xplained_nandflash           sama5d3_xplained:SAMA5D3,SYS_USE_NANDFLASH                                                                                        Bo Shen <voice.shen@atmel.com>
 Active  arm         armv7          at91        atmel           sama5d3xek          sama5d3xek_mmc                       sama5d3xek:SAMA5D3,SYS_USE_MMC                                                                                                    Bo Shen <voice.shen@atmel.com>
 Active  arm         armv7          at91        atmel           sama5d3xek          sama5d3xek_nandflash                 sama5d3xek:SAMA5D3,SYS_USE_NANDFLASH                                                                                              Bo Shen <voice.shen@atmel.com>
 Active  arm         armv7          at91        atmel           sama5d3xek          sama5d3xek_spiflash                  sama5d3xek:SAMA5D3,SYS_USE_SERIALFLASH                                                                                            Bo Shen <voice.shen@atmel.com>
+Active  arm         armv7          bcm281xx    broadcom        bcm28155_ap         bcm28155_ap                          bcm28155_ap                                                                                                                       Tim Kryger <tim.kryger@linaro.org>
 Active  arm         armv7          exynos      samsung         arndale             arndale                              -                                                                                                                                 Inderpal Singh <inderpal.singh@linaro.org>
 Active  arm         armv7          exynos      samsung         origen              origen                               -                                                                                                                                 Chander Kashyap <k.chander@samsung.com>
 Active  arm         armv7          exynos      samsung         smdk5250            smdk5250                             -                                                                                                                                 Chander Kashyap <k.chander@samsung.com>
 Active  arm         armv7          exynos      samsung         smdk5250            snow                                 -                                                                                                                                 Rajeshwari Shinde <rajeshwari.s@samsung.com>
+Active  arm         armv7          exynos      samsung         smdk5420            smdk5420                             -                                                                                                                                 Rajeshwari Shinde <rajeshwari.s@samsung.com>
 Active  arm         armv7          exynos      samsung         smdkv310            smdkv310                             -                                                                                                                                 Chander Kashyap <k.chander@samsung.com>
 Active  arm         armv7          exynos      samsung         trats               trats                                -                                                                                                                                 Lukasz Majewski <l.majewski@samsung.com>
 Active  arm         armv7          exynos      samsung         trats2              trats2                               -                                                                                                                                 Piotr Wilczek <p.wilczek@samsung.com>
-Active  arm         armv7          exynos      samsung         universal_c210      s5pc210_universal                    -                                                                                                                                 Minkyu Kang <mk7.kang@samsung.com>
+Active  arm         armv7          exynos      samsung         universal_c210      s5pc210_universal                    -                                                                                                                                 Przemyslaw Marczak <p.marczak@samsung.com>
 Active  arm         armv7          highbank    -               highbank            highbank                             -                                                                                                                                 Rob Herring <rob.herring@calxeda.com>
 Active  arm         armv7          mx5         denx            m53evk              m53evk                               m53evk:IMX_CONFIG=board/denx/m53evk/imximage.cfg                                                                                  Marek Vasut <marek.vasut@gmail.com>
 Active  arm         armv7          mx5         esg             ima3-mx53           ima3-mx53                            ima3-mx53:IMX_CONFIG=board/esg/ima3-mx53/imximage.cfg                                                                             -
@@ -287,9 +304,11 @@ Active  arm         armv7          mx5         freescale       mx53smd
 Active  arm         armv7          mx5         genesi          mx51_efikamx        mx51_efikamx                         mx51_efikamx:MACH_TYPE=MACH_TYPE_MX51_EFIKAMX,IMX_CONFIG=board/genesi/mx51_efikamx/imximage_mx.cfg                                -
 Active  arm         armv7          mx5         genesi          mx51_efikamx        mx51_efikasb                         mx51_efikamx:MACH_TYPE=MACH_TYPE_MX51_EFIKASB,IMX_CONFIG=board/genesi/mx51_efikamx/imximage_sb.cfg                                -
 Active  arm         armv7          mx5         ttcontrol       vision2             vision2                              vision2:IMX_CONFIG=board/ttcontrol/vision2/imximage_hynix.cfg                                                                     Stefano Babic <sbabic@denx.de>
+Active  arm         armv7          mx6         -               udoo                udoo_quad                            udoo:IMX_CONFIG=board/udoo/udoo.cfg,MX6Q,DDR_MB=1024                                                                              Fabio Estevam <fabio.estevam@freescale.com>
 Active  arm         armv7          mx6         -               wandboard           wandboard_dl                         wandboard:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6dl.cfg,MX6DL,DDR_MB=1024                                                  Fabio Estevam <fabio.estevam@freescale.com>
 Active  arm         armv7          mx6         -               wandboard           wandboard_quad                       wandboard:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6q2g.cfg,MX6Q,DDR_MB=2048                                                  Fabio Estevam <fabio.estevam@freescale.com>
 Active  arm         armv7          mx6         -               wandboard           wandboard_solo                       wandboard:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6s.cfg,MX6S,DDR_MB=512                                                     Fabio Estevam <fabio.estevam@freescale.com>
+Active  arm         armv7          mx6         barco           titanium            titanium                             titanium:IMX_CONFIG=board/barco/titanium/imximage.cfg                                                                             Stefan Roese <sr@denx.de>
 Active  arm         armv7          mx6         boundary        nitrogen6x          mx6qsabrelite                        nitrogen6x:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6q.cfg,MX6Q,DDR_MB=1024,SABRELITE                                         Eric Nelson <eric.nelson@boundarydevices.com>
 Active  arm         armv7          mx6         boundary        nitrogen6x          nitrogen6dl                          nitrogen6x:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6dl.cfg,MX6DL,DDR_MB=1024                                                 Eric Nelson <eric.nelson@boundarydevices.com>
 Active  arm         armv7          mx6         boundary        nitrogen6x          nitrogen6dl2g                        nitrogen6x:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6dl2g.cfg,MX6DL,DDR_MB=2048                                               Eric Nelson <eric.nelson@boundarydevices.com>
@@ -303,7 +322,12 @@ Active  arm         armv7          mx6         freescale       mx6qsabreauto
 Active  arm         armv7          mx6         freescale       mx6sabresd          mx6dlsabresd                         mx6sabresd:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6dl.cfg,MX6DL                                                             Fabio Estevam <fabio.estevam@freescale.com>
 Active  arm         armv7          mx6         freescale       mx6sabresd          mx6qsabresd                          mx6sabresd:IMX_CONFIG=board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg,MX6Q                                                           Fabio Estevam <fabio.estevam@freescale.com>
 Active  arm         armv7          mx6         freescale       mx6slevk            mx6slevk                             mx6slevk:IMX_CONFIG=board/freescale/mx6slevk/imximage.cfg,MX6SL                                                                   Fabio Estevam <fabio.estevam@freescale.com>
-Active  arm         armv7          mx6         freescale       titanium            titanium                             titanium:IMX_CONFIG=board/freescale/titanium/imximage.cfg                                                                         Stefan Roese <sr@denx.de>
+Active  arm         armv7          mx6         gateworks       gw_ventana          gwventanadl                          gw_ventana:IMX_CONFIG=board/gateworks/gw_ventana/gw_ventana.cfg,MX6DL,DDR_MB=512                                                  Tim Harvey <tharvey@gateworks.com>
+Active  arm         armv7          mx6         gateworks       gw_ventana          gwventanadl1g                        gw_ventana:IMX_CONFIG=board/gateworks/gw_ventana/gw_ventana.cfg,MX6DL,DDR_MB=1024                                                 Tim Harvey <tharvey@gateworks.com>
+Active  arm         armv7          mx6         gateworks       gw_ventana          gwventanaq                           gw_ventana:IMX_CONFIG=board/gateworks/gw_ventana/gw_ventana.cfg,MX6Q,DDR_MB=512                                                   Tim Harvey <tharvey@gateworks.com>
+Active  arm         armv7          mx6         gateworks       gw_ventana          gwventanaq1g                         gw_ventana:IMX_CONFIG=board/gateworks/gw_ventana/gw_ventana.cfg,MX6Q,DDR_MB=1024                                                  Tim Harvey <tharvey@gateworks.com>
+Active  arm         armv7          mx6         gateworks       gw_ventana          gwventanaq1gspi                      gw_ventana:IMX_CONFIG=board/gateworks/gw_ventana/gw_ventana.cfg,MX6Q,DDR_MB=1024,SPI_FLASH                                        Tim Harvey <tharvey@gateworks.com>
+Active  arm         armv7          mx6         solidrun        hummingboard        hummingboard_solo                    hummingboard:IMX_CONFIG=board/solidrun/hummingboard/solo.cfg,MX6S,DDR_MB=512                                                      Jon Nettleton <jon.nettleton@gmail.com>
 Active  arm         armv7          mx6         toradex         apalis_imx6         apalis_imx6q1g                       apalis-imx6:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6q.cfg,MX6Q,DDR_MB=1024
 Active  arm         armv7          omap3       -               overo               omap3_overo                          -                                                                                                                                 Steve Sakoman <sakoman@gmail.com>
 Active  arm         armv7          omap3       -               pandora             omap3_pandora                        -                                                                                                                                 Grazvydas Ignotas <notasas@gmail.com>
@@ -311,18 +335,20 @@ Active  arm         armv7          omap3       8dtech          eco5pk
 Active  arm         armv7          omap3       comelit         dig297              dig297                               -                                                                                                                                 Luca Ceresoli <luca.ceresoli@comelit.it>
 Active  arm         armv7          omap3       compulab        cm_t35              cm_t35                               -                                                                                                                                 Igor Grinberg <grinberg@compulab.co.il>
 Active  arm         armv7          omap3       corscience      tricorder           tricorder                            -                                                                                                                                 Thomas Weber <weber@corscience.de>
+Active  arm         armv7          omap3       corscience      tricorder           tricorder_flash                      tricorder:FLASHCARD                                                                                                               Thomas Weber <weber@corscience.de>
 Active  arm         armv7          omap3       htkw            mcx                 mcx                                  -                                                                                                                                 Ilya Yanok <yanok@emcraft.com>
-Active  arm         armv7          omap3       isee            igep00x0            igep0020                             igep00x0:MACH_TYPE=MACH_TYPE_IGEP0020,BOOT_ONENAND                                                                                Enric Balletbo i Serra <eballetbo@iseebcn.com>
-Active  arm         armv7          omap3       isee            igep00x0            igep0020_nand                        igep00x0:MACH_TYPE=MACH_TYPE_IGEP0020,BOOT_NAND                                                                                   -
-Active  arm         armv7          omap3       isee            igep00x0            igep0030                             igep00x0:MACH_TYPE=MACH_TYPE_IGEP0030,BOOT_ONENAND                                                                                Enric Balletbo i Serra <eballetbo@iseebcn.com>
-Active  arm         armv7          omap3       isee            igep00x0            igep0030_nand                        igep00x0:MACH_TYPE=MACH_TYPE_IGEP0030,BOOT_NAND                                                                                   -
-Active  arm         armv7          omap3       isee            igep00x0            igep0032                             igep00x0:MACH_TYPE=MACH_TYPE_IGEP0032,BOOT_ONENAND                                                                                Enric Balletbo i Serra <eballetbo@iseebcn.com>
+Active  arm         armv7          omap3       isee            igep00x0            igep0020                             omap3_igep00x0:MACH_TYPE=MACH_TYPE_IGEP0020,BOOT_ONENAND                                                                          Enric Balletbo i Serra <eballetbo@iseebcn.com>
+Active  arm         armv7          omap3       isee            igep00x0            igep0020_nand                        omap3_igep00x0:MACH_TYPE=MACH_TYPE_IGEP0020,BOOT_NAND                                                                             -
+Active  arm         armv7          omap3       isee            igep00x0            igep0030                             omap3_igep00x0:MACH_TYPE=MACH_TYPE_IGEP0030,BOOT_ONENAND                                                                          Enric Balletbo i Serra <eballetbo@iseebcn.com>
+Active  arm         armv7          omap3       isee            igep00x0            igep0030_nand                        omap3_igep00x0:MACH_TYPE=MACH_TYPE_IGEP0030,BOOT_NAND                                                                             -
+Active  arm         armv7          omap3       isee            igep00x0            igep0032                             omap3_igep00x0:MACH_TYPE=MACH_TYPE_IGEP0032,BOOT_ONENAND                                                                          Enric Balletbo i Serra <eballetbo@iseebcn.com>
 Active  arm         armv7          omap3       logicpd         am3517evm           am3517_evm                           -                                                                                                                                 Vaibhav Hiremath <hvaibhav@ti.com>
 Active  arm         armv7          omap3       logicpd         omap3som            omap3_logic                          -                                                                                                                                 Peter Barada <peter.barada@logicpd.com>
 Active  arm         armv7          omap3       logicpd         zoom1               omap3_zoom1                          -                                                                                                                                 Nishanth Menon <nm@ti.com>
-Active  arm         armv7          omap3       logicpd         zoom2               omap3_zoom2                          -                                                                                                                                 Tom Rix <Tom.Rix@windriver.com>
 Active  arm         armv7          omap3       matrix_vision   mvblx               omap3_mvblx                          -                                                                                                                                 Michael Jones <michael.jones@matrix-vision.de>
 Active  arm         armv7          omap3       nokia           rx51                nokia_rx51                           -                                                                                                                                 Pali Rohár <pali.rohar@gmail.com>
+Active  arm         armv7          omap3       technexion      tao3530             omap3_ha                             tao3530:SYS_BOARD_OMAP3_HA                                                                                                        Stefan Roese <sr@denx.de>
+Active  arm         armv7          omap3       technexion      tao3530             tao3530                              -                                                                                                                                 Tapani Utriainen <linuxfae@technexion.com>
 Active  arm         armv7          omap3       technexion      twister             twister                              -                                                                                                                                 Stefano Babic <sbabic@denx.de>
 Active  arm         armv7          omap3       teejet          mt_ventoux          mt_ventoux                           -                                                                                                                                 Stefano Babic <sbabic@denx.de>
 Active  arm         armv7          omap3       ti              am3517crane         am3517_crane                         -                                                                                                                                 Nagendra T S  <nagendra@mistralsolutions.com>
@@ -334,22 +360,33 @@ Active  arm         armv7          omap3       ti              sdp3430
 Active  arm         armv7          omap3       timll           devkit8000          devkit8000                           -                                                                                                                                 Thomas Weber <weber@corscience.de>
 Active  arm         armv7          omap4       ti              panda               omap4_panda                          -                                                                                                                                 Sricharan R <r.sricharan@ti.com>
 Active  arm         armv7          omap4       ti              sdp4430             omap4_sdp4430                        -                                                                                                                                 Sricharan R <r.sricharan@ti.com>
-Active  arm         armv7          omap5       ti              dra7xx              dra7xx_evm                           -                                                                                                                                 Lokesh Vutla <lokeshvutla@ti.com>
+Active  arm         armv7          omap5       ti              dra7xx              dra7xx_evm                           dra7xx_evm:CONS_INDEX=1                                                                                                           Lokesh Vutla <lokeshvutla@ti.com>
+Active  arm         armv7          omap5       ti              dra7xx              dra7xx_evm_uart3                     dra7xx_evm:CONS_INDEX=3,SPL_YMODEM_SUPPORT                                                                                        Lokesh Vutla <lokeshvutla@ti.com>
 Active  arm         armv7          omap5       ti              omap5_uevm          omap5_uevm                           -                                                                                                                                 -
 Active  arm         armv7          rmobile     atmark-techno   armadillo-800eva    armadillo-800eva                     -                                                                                                                                 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
 Active  arm         armv7          rmobile     kmc             kzm9g               kzm9g                                -                                                                                                                                 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>:Tetsuyuki Kobayashi <koba@kmckk.co.jp>
-Active  arm         armv7          s5pc1xx     samsung         goni                s5p_goni                             -                                                                                                                                 Minkyu Kang <mk7.kang@samsung.com>
+Active  arm         armv7          rmobile     renesas         koelsch             koelsch                              -                                                                                                                                 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
+Active  arm         armv7          rmobile     renesas         koelsch             koelsch_nor                          koelsch:NORFLASH                                                                                                                  Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
+Active  arm         armv7          rmobile     renesas         lager               lager                                -                                                                                                                                 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
+Active  arm         armv7          rmobile     renesas         lager               lager_nor                            lager:NORFLASH                                                                                                                    Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
+Active  arm         armv7          s5pc1xx     samsung         goni                s5p_goni                             -                                                                                                                                 Mateusz Zalega <m.zalega@samsung.com>
 Active  arm         armv7          s5pc1xx     samsung         smdkc100            smdkc100                             -                                                                                                                                 Minkyu Kang <mk7.kang@samsung.com>
 Active  arm         armv7          socfpga     altera          socfpga             socfpga_cyclone5                     -                                                                                                                                 -
 Active  arm         armv7          u8500       st-ericsson     snowball            snowball                             -                                                                                                                                 Mathieu Poirier <mathieu.poirier@linaro.org>
 Active  arm         armv7          u8500       st-ericsson     u8500               u8500_href                           -                                                                                                                                 -
 Active  arm         armv7          vf610       freescale       vf610twr            vf610twr                             vf610twr:IMX_CONFIG=board/freescale/vf610twr/imximage.cfg                                                                         Alison Wang <b18965@freescale.com>
-Active  arm         armv7          zynq        xilinx          zynq                zynq                                 -                                                                                                                                 Michal Simek <monstr@monstr.eu>
-Active  arm         armv7          zynq        xilinx          zynq                zynq_dcc                             zynq:ZYNQ_DCC                                                                                                                     Michal Simek <monstr@monstr.eu>
+Active  arm         armv7          vf610       toradex         colibri_vf          colibri_vf                           colibri_vf:IMX_CONFIG=board/toradex/colibri_vf/imximage.cfg,IMX_NAND                                                              Stefan Agner <stefan@agner.ch>
+Active  arm         armv7          zynq        xilinx          zynq                zynq_microzed                        -                                                                                                                                 Michal Simek <monstr@monstr.eu>:Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
+Active  arm         armv7          zynq        xilinx          zynq                zynq_zc70x                           -                                                                                                                                 Michal Simek <monstr@monstr.eu>:Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
+Active  arm         armv7          zynq        xilinx          zynq                zynq_zc770_xm010                     zynq_zc770:ZC770_XM010                                                                                                            Michal Simek <monstr@monstr.eu>:Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
+Active  arm         armv7          zynq        xilinx          zynq                zynq_zc770_xm012                     zynq_zc770:ZC770_XM012                                                                                                            Michal Simek <monstr@monstr.eu>:Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
+Active  arm         armv7          zynq        xilinx          zynq                zynq_zc770_xm013                     zynq_zc770:ZC770_XM013                                                                                                            Michal Simek <monstr@monstr.eu>:Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
+Active  arm         armv7          zynq        xilinx          zynq                zynq_zed                             -                                                                                                                                 Michal Simek <monstr@monstr.eu>:Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
 Active  arm         armv7:arm720t  tegra114    nvidia          dalmore             dalmore                              -                                                                                                                                 Tom Warren <twarren@nvidia.com>
-Active  arm         armv7:arm720t  tegra20     avionic-design  medcom-wide         medcom-wide                          -                                                                                                                                 Thierry Reding <thierry.reding@avionic-design.de>
-Active  arm         armv7:arm720t  tegra20     avionic-design  plutux              plutux                               -                                                                                                                                 Thierry Reding <thierry.reding@avionic-design.de>
-Active  arm         armv7:arm720t  tegra20     avionic-design  tec                 tec                                  -                                                                                                                                 Thierry Reding <thierry.reding@avionic-design.de>
+Active  arm         armv7:arm720t  tegra124    nvidia          venice2             venice2                              -                                                                                                                                 Tom Warren <twarren@nvidia.com>
+Active  arm         armv7:arm720t  tegra20     avionic-design  medcom-wide         medcom-wide                          -                                                                                                                                 Alban Bedel <alban.bedel@avionic-design.de>
+Active  arm         armv7:arm720t  tegra20     avionic-design  plutux              plutux                               -                                                                                                                                 Alban Bedel <alban.bedel@avionic-design.de>
+Active  arm         armv7:arm720t  tegra20     avionic-design  tec                 tec                                  -                                                                                                                                 Alban Bedel <alban.bedel@avionic-design.de>
 Active  arm         armv7:arm720t  tegra20     compal          paz00               paz00                                -                                                                                                                                 Tom Warren <twarren@nvidia.com>:Stephen Warren <swarren@nvidia.com>
 Active  arm         armv7:arm720t  tegra20     compulab        trimslice           trimslice                            -                                                                                                                                 Tom Warren <twarren@nvidia.com>:Stephen Warren <swarren@nvidia.com>
 Active  arm         armv7:arm720t  tegra20     nvidia          harmony             harmony                              -                                                                                                                                 Tom Warren <twarren@nvidia.com>
@@ -357,18 +394,9 @@ Active  arm         armv7:arm720t  tegra20     nvidia          seaboard
 Active  arm         armv7:arm720t  tegra20     nvidia          ventana             ventana                              -                                                                                                                                 Tom Warren <twarren@nvidia.com>:Stephen Warren <swarren@nvidia.com>
 Active  arm         armv7:arm720t  tegra20     nvidia          whistler            whistler                             -                                                                                                                                 Tom Warren <twarren@nvidia.com>:Stephen Warren <swarren@nvidia.com>
 Active  arm         armv7:arm720t  tegra20     toradex         colibri_t20_iris    colibri_t20_iris                     -                                                                                                                                 Lucas Stach <dev@lynxeye.de>
+Active  arm         armv7:arm720t  tegra30     avionic-design  tec-ng              tec-ng                               -                                                                                                                                 Alban Bedel <alban.bedel@avionic-design.de>
 Active  arm         armv7:arm720t  tegra30     nvidia          beaver              beaver                               -                                                                                                                                 Tom Warren <twarren@nvidia.com>:Stephen Warren <swarren@nvidia.com>
 Active  arm         armv7:arm720t  tegra30     nvidia          cardhu              cardhu                               -                                                                                                                                 Tom Warren <twarren@nvidia.com>
-Active  arm         ixp            -           -               -                   actux2                               -                                                                                                                                 Michael Schwingen <michael@schwingen.org>
-Active  arm         ixp            -           -               -                   actux3                               -                                                                                                                                 Michael Schwingen <michael@schwingen.org>
-Active  arm         ixp            -           -               -                   actux4                               -                                                                                                                                 Michael Schwingen <michael@schwingen.org>
-Active  arm         ixp            -           -               -                   dvlhost                              -                                                                                                                                 Michael Schwingen <michael@schwingen.org>
-Active  arm         ixp            -           -               actux1              actux1_4_16                          actux1:FLASH2X2                                                                                                                   Michael Schwingen <michael@schwingen.org>
-Active  arm         ixp            -           -               actux1              actux1_4_32                          actux1:FLASH2X2,RAM_32MB                                                                                                          Michael Schwingen <michael@schwingen.org>
-Active  arm         ixp            -           -               actux1              actux1_8_16                          actux1:FLASH1X8                                                                                                                   Michael Schwingen <michael@schwingen.org>
-Active  arm         ixp            -           -               actux1              actux1_8_32                          actux1:FLASH1X8,RAM_32MB                                                                                                          Michael Schwingen <michael@schwingen.org>
-Active  arm         ixp            -           prodrive        pdnb3               pdnb3                                -                                                                                                                                 Stefan Roese <sr@denx.de>
-Active  arm         ixp            -           prodrive        pdnb3               scpu                                 pdnb3:SCPU                                                                                                                        Stefan Roese <sr@denx.de>
 Active  arm         pxa            -           -               -                   balloon3                             -                                                                                                                                 Marek Vasut <marek.vasut@gmail.com>
 Active  arm         pxa            -           -               -                   h2200                                -                                                                                                                                 Lukasz Dalek <luk0104@gmail.com>
 Active  arm         pxa            -           -               -                   palmld                               -                                                                                                                                 Marek Vasut <marek.vasut@gmail.com>
@@ -396,45 +424,36 @@ Active  avr32       at32ap         at32ap700x  in-circuit      -
 Active  avr32       at32ap         at32ap700x  mimc            -                   mimc200                              -                                                                                                                                 Mark Jackson <mpfj@mimc.co.uk>
 Active  avr32       at32ap         at32ap700x  miromico        -                   hammerhead                           -                                                                                                                                 Julien May <julien.may@miromico.ch>:Alex Raimondi <alex.raimondi@miromico.ch>
 Active  blackfin    blackfin       -           -               -                   bct-brettl2                          -                                                                                                                                 Peter Meerwald <devel@bct-electronic.com>
-Active  blackfin    blackfin       -           -               -                   bf506f-ezkit                         -                                                                                                                                 Sonic Zhang <sonic.adi@gmail.com>:Blackfin Team <u-boot-devel@blackfin.uclinux.org>
-Active  blackfin    blackfin       -           -               -                   bf518f-ezbrd                         -                                                                                                                                 Sonic Zhang <sonic.adi@gmail.com>:Blackfin Team <u-boot-devel@blackfin.uclinux.org>
+Active  blackfin    blackfin       -           -               -                   bf506f-ezkit                         -                                                                                                                                 Sonic Zhang <sonic.adi@gmail.com>
+Active  blackfin    blackfin       -           -               -                   bf518f-ezbrd                         -                                                                                                                                 Sonic Zhang <sonic.adi@gmail.com>
 Active  blackfin    blackfin       -           -               -                   bf525-ucr2                           -                                                                                                                                 Haitao Zhang <hzhang@ucrobotics.com>:Chong Huang <chuang@ucrobotics.com>
-Active  blackfin    blackfin       -           -               -                   bf526-ezbrd                          -                                                                                                                                 Sonic Zhang <sonic.adi@gmail.com>:Blackfin Team <u-boot-devel@blackfin.uclinux.org>
-Active  blackfin    blackfin       -           -               -                   bf527-ad7160-eval                    -                                                                                                                                 Sonic Zhang <sonic.adi@gmail.com>:Blackfin Team <u-boot-devel@blackfin.uclinux.org>
-Active  blackfin    blackfin       -           -               -                   bf527-ezkit                          -                                                                                                                                 Sonic Zhang <sonic.adi@gmail.com>:Blackfin Team <u-boot-devel@blackfin.uclinux.org>
-Active  blackfin    blackfin       -           -               -                   bf527-sdp                            -                                                                                                                                 Sonic Zhang <sonic.adi@gmail.com>:Blackfin Team <u-boot-devel@blackfin.uclinux.org>
-Active  blackfin    blackfin       -           -               -                   bf533-ezkit                          -                                                                                                                                 Sonic Zhang <sonic.adi@gmail.com>:Blackfin Team <u-boot-devel@blackfin.uclinux.org>
-Active  blackfin    blackfin       -           -               -                   bf533-stamp                          -                                                                                                                                 Sonic Zhang <sonic.adi@gmail.com>:Blackfin Team <u-boot-devel@blackfin.uclinux.org>
+Active  blackfin    blackfin       -           -               -                   bf526-ezbrd                          -                                                                                                                                 Sonic Zhang <sonic.adi@gmail.com>
+Active  blackfin    blackfin       -           -               -                   bf527-ad7160-eval                    -                                                                                                                                 Sonic Zhang <sonic.adi@gmail.com>
+Active  blackfin    blackfin       -           -               -                   bf527-ezkit                          -                                                                                                                                 Sonic Zhang <sonic.adi@gmail.com>
+Active  blackfin    blackfin       -           -               -                   bf527-sdp                            -                                                                                                                                 Sonic Zhang <sonic.adi@gmail.com>
+Active  blackfin    blackfin       -           -               -                   bf533-ezkit                          -                                                                                                                                 Sonic Zhang <sonic.adi@gmail.com>
+Active  blackfin    blackfin       -           -               -                   bf533-stamp                          -                                                                                                                                 Sonic Zhang <sonic.adi@gmail.com>
 Active  blackfin    blackfin       -           -               -                   bf537-minotaur                       -                                                                                                                                 Martin Strubel <strubel@section5.ch>
-Active  blackfin    blackfin       -           -               -                   bf537-pnav                           -                                                                                                                                 Sonic Zhang <sonic.adi@gmail.com>:Blackfin Team <u-boot-devel@blackfin.uclinux.org>
+Active  blackfin    blackfin       -           -               -                   bf537-pnav                           -                                                                                                                                 Sonic Zhang <sonic.adi@gmail.com>
 Active  blackfin    blackfin       -           -               -                   bf537-srv1                           -                                                                                                                                 Martin Strubel <strubel@section5.ch>
-Active  blackfin    blackfin       -           -               -                   bf537-stamp                          -                                                                                                                                 Sonic Zhang <sonic.adi@gmail.com>:Blackfin Team <u-boot-devel@blackfin.uclinux.org>
-Active  blackfin    blackfin       -           -               -                   bf538f-ezkit                         -                                                                                                                                 Sonic Zhang <sonic.adi@gmail.com>:Blackfin Team <u-boot-devel@blackfin.uclinux.org>
-Active  blackfin    blackfin       -           -               -                   bf548-ezkit                          -                                                                                                                                 Sonic Zhang <sonic.adi@gmail.com>:Blackfin Team <u-boot-devel@blackfin.uclinux.org>
+Active  blackfin    blackfin       -           -               -                   bf537-stamp                          -                                                                                                                                 Sonic Zhang <sonic.adi@gmail.com>
+Active  blackfin    blackfin       -           -               -                   bf538f-ezkit                         -                                                                                                                                 Sonic Zhang <sonic.adi@gmail.com>
+Active  blackfin    blackfin       -           -               -                   bf548-ezkit                          -                                                                                                                                 Sonic Zhang <sonic.adi@gmail.com>
 Active  blackfin    blackfin       -           -               -                   bf561-acvilon                        -                                                                                                                                 Anton Shurpin <shurpin.aa@niistt.ru>:Valentin Yakovenkov <yakovenkov@niistt.ru>
-Active  blackfin    blackfin       -           -               -                   bf561-ezkit                          -                                                                                                                                 Sonic Zhang <sonic.adi@gmail.com>:Blackfin Team <u-boot-devel@blackfin.uclinux.org>
-Active  blackfin    blackfin       -           -               -                   bf609-ezkit                          -                                                                                                                                 Sonic Zhang <sonic.adi@gmail.com>:Blackfin Team <u-boot-devel@blackfin.uclinux.org>
+Active  blackfin    blackfin       -           -               -                   bf561-ezkit                          -                                                                                                                                 Sonic Zhang <sonic.adi@gmail.com>
+Active  blackfin    blackfin       -           -               -                   bf609-ezkit                          -                                                                                                                                 Sonic Zhang <sonic.adi@gmail.com>
 Active  blackfin    blackfin       -           -               -                   blackstamp                           -                                                                                                                                 Wojtek Skulski <skulski@pas.rochester.edu>:Wojtek Skulski <info@skutek.com>:Benjamin Matthews <mben12@gmail.com>
 Active  blackfin    blackfin       -           -               -                   blackvme                             -                                                                                                                                 Wojtek Skulski <skulski@pas.rochester.edu>:Wojtek Skulski <info@skutek.com>:Benjamin Matthews <mben12@gmail.com>
 Active  blackfin    blackfin       -           -               -                   br4                                  -                                                                                                                                 Dimitar Penev <dpn@switchfin.org>
-Active  blackfin    blackfin       -           -               -                   cm-bf527                             -                                                                                                                                 Bluetechnix Tinyboards <bluetechnix@blackfin.uclinux.org>
-Active  blackfin    blackfin       -           -               -                   cm-bf533                             -                                                                                                                                 Bluetechnix Tinyboards <bluetechnix@blackfin.uclinux.org>
-Active  blackfin    blackfin       -           -               -                   cm-bf537e                            -                                                                                                                                 Bluetechnix Tinyboards <bluetechnix@blackfin.uclinux.org>
-Active  blackfin    blackfin       -           -               -                   cm-bf537u                            -                                                                                                                                 Bluetechnix Tinyboards <bluetechnix@blackfin.uclinux.org>
-Active  blackfin    blackfin       -           -               -                   cm-bf548                             -                                                                                                                                 Bluetechnix Tinyboards <bluetechnix@blackfin.uclinux.org>
-Active  blackfin    blackfin       -           -               -                   cm-bf561                             -                                                                                                                                 Bluetechnix Tinyboards <bluetechnix@blackfin.uclinux.org>
 Active  blackfin    blackfin       -           -               -                   dnp5370                              -                                                                                                                                 M.Hasewinkel (MHA) <info@ssv-embedded.de>
 Active  blackfin    blackfin       -           -               -                   ibf-dsp561                           -                                                                                                                                 I-SYST Micromodule <support@i-syst.com>
 Active  blackfin    blackfin       -           -               -                   ip04                                 -                                                                                                                                 Brent Kandetzki <brentk@teleco.com>
 Active  blackfin    blackfin       -           -               -                   pr1                                  -                                                                                                                                 Dimitar Penev <dpn@switchfin.org>
-Active  blackfin    blackfin       -           -               -                   tcm-bf518                            -                                                                                                                                 Bluetechnix Tinyboards <bluetechnix@blackfin.uclinux.org>
-Active  blackfin    blackfin       -           -               -                   tcm-bf537                            -                                                                                                                                 Bluetechnix Tinyboards <bluetechnix@blackfin.uclinux.org>
-Active  blackfin    blackfin       -           -               bf527-ezkit         bf527-ezkit-v2                       bf527-ezkit:BF527_EZKIT_REV_2_1                                                                                                   Sonic Zhang <sonic.adi@gmail.com>:Blackfin Team <u-boot-devel@blackfin.uclinux.org>
+Active  blackfin    blackfin       -           -               bf527-ezkit         bf527-ezkit-v2                       bf527-ezkit:BF527_EZKIT_REV_2_1                                                                                                   Sonic Zhang <sonic.adi@gmail.com>
 Active  m68k        mcf5227x       -           freescale       m52277evb           M52277EVB                            M52277EVB:SYS_SPANSION_BOOT,SYS_TEXT_BASE=0x00000000                                                                              TsiChung Liew <Tsi-Chung.Liew@freescale.com>
 Active  m68k        mcf5227x       -           freescale       m52277evb           M52277EVB_stmicro                    M52277EVB:CF_SBF,SYS_STMICRO_BOOT,SYS_TEXT_BASE=0x43E00000                                                                        TsiChung Liew <Tsi-Chung.Liew@freescale.com>
 Active  m68k        mcf523x        -           freescale       m5235evb            M5235EVB                             M5235EVB:SYS_TEXT_BASE=0xFFE00000                                                                                                 TsiChung Liew <Tsi-Chung.Liew@freescale.com>
 Active  m68k        mcf523x        -           freescale       m5235evb            M5235EVB_Flash32                     M5235EVB:NORFLASH_PS32BIT,SYS_TEXT_BASE=0xFFC00000                                                                                TsiChung Liew <Tsi-Chung.Liew@freescale.com>
-Active  m68k        mcf52x2        -           -               -                   idmr                                 -                                                                                                                                 -
 Active  m68k        mcf52x2        -           -               cobra5272           cobra5272                            -                                                                                                                                 -
 Active  m68k        mcf52x2        -           BuS             eb_cpu5282          eb_cpu5282                           eb_cpu5282:SYS_TEXT_BASE=0xFF000000,SYS_MONITOR_BASE=0xFF000400                                                                   Jens Scharsig <esw@bus-elektronik.de>
 Active  m68k        mcf52x2        -           BuS             eb_cpu5282          eb_cpu5282_internal                  eb_cpu5282:SYS_TEXT_BASE=0xF0000000,SYS_MONITOR_BASE=0xF0000418                                                                   Jens Scharsig <esw@bus-elektronik.de>
@@ -443,7 +462,6 @@ Active  m68k        mcf52x2        -           freescale       m5208evbe
 Active  m68k        mcf52x2        -           freescale       m5249evb            M5249EVB                             -                                                                                                                                 -
 Active  m68k        mcf52x2        -           freescale       m5253demo           M5253DEMO                            -                                                                                                                                 TsiChung Liew <Tsi-Chung.Liew@freescale.com>
 Active  m68k        mcf52x2        -           freescale       m5253evbe           M5253EVBE                            -                                                                                                                                 Hayden Fraser <Hayden.Fraser@freescale.com>
-Active  m68k        mcf52x2        -           freescale       m5271evb            M5271EVB                             -                                                                                                                                 -
 Active  m68k        mcf52x2        -           freescale       m5272c3             M5272C3                              -                                                                                                                                 -
 Active  m68k        mcf52x2        -           freescale       m5275evb            M5275EVB                             -                                                                                                                                 -
 Active  m68k        mcf52x2        -           freescale       m5282evb            M5282EVB                             -                                                                                                                                 -
@@ -481,10 +499,10 @@ Active  m68k        mcf547x_8x     -           freescale       m548xevb
 Active  m68k        mcf547x_8x     -           freescale       m548xevb            M5485GFE                             M5485EVB:SYS_BUSCLK=100000000,SYS_BOOTSZ=4,SYS_DRAMSZ=64                                                                          TsiChung Liew <Tsi-Chung.Liew@freescale.com>
 Active  m68k        mcf547x_8x     -           freescale       m548xevb            M5485HFE                             M5485EVB:SYS_BUSCLK=100000000,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_NOR1SZ=16,SYS_VIDEO                                                  TsiChung Liew <Tsi-Chung.Liew@freescale.com>
 Active  microblaze  microblaze     -           xilinx          microblaze-generic  microblaze-generic                   -                                                                                                                                 Michal Simek <monstr@monstr.eu>
-Active  mips        mips32         -           -               qemu-malta          qemu_malta                           qemu-malta:MIPS32,SYS_BIG_ENDIAN                                                                                                  -
-Active  mips        mips32         -           -               qemu-malta          qemu_maltael                         qemu-malta:MIPS32,SYS_LITTLE_ENDIAN                                                                                               -
 Active  mips        mips32         -           -               qemu-mips           qemu_mips                            qemu-mips:SYS_BIG_ENDIAN                                                                                                          Vlad Lungu <vlad.lungu@windriver.com>
 Active  mips        mips32         -           -               qemu-mips           qemu_mipsel                          qemu-mips:SYS_LITTLE_ENDIAN                                                                                                       -
+Active  mips        mips32         -           imgtec          malta               malta                                malta:SYS_BIG_ENDIAN                                                                                                              Paul Burton <paul.burton@imgtec.com>
+Active  mips        mips32         -           imgtec          malta               maltael                              malta:SYS_LITTLE_ENDIAN                                                                                                           Paul Burton <paul.burton@imgtec.com>
 Active  mips        mips32         -           micronas        vct                 vct_platinum                         vct:VCT_PLATINUM                                                                                                                  -
 Active  mips        mips32         -           micronas        vct                 vct_platinum_onenand                 vct:VCT_PLATINUM,VCT_ONENAND                                                                                                      -
 Active  mips        mips32         -           micronas        vct                 vct_platinum_onenand_small           vct:VCT_PLATINUM,VCT_ONENAND,VCT_SMALL_IMAGE                                                                                      -
@@ -560,7 +578,7 @@ Active  powerpc     mpc5xxx        -           -               icecube
 Active  powerpc     mpc5xxx        -           -               icecube             lite5200b                            IceCube:MPC5200_DDR,LITE5200B                                                                                                     -
 Active  powerpc     mpc5xxx        -           -               icecube             lite5200b_LOWBOOT                    IceCube:MPC5200_DDR,LITE5200B,SYS_TEXT_BASE=0xFF000000                                                                            -
 Active  powerpc     mpc5xxx        -           -               icecube             lite5200b_PM                         IceCube:MPC5200_DDR,LITE5200B,LITE5200B_PM                                                                                        -
-Active  powerpc     mpc5xxx        -           -               mcc200              mcc200                               mcc200                                                                                                                            -
+Active  powerpc     mpc5xxx        -           -               mcc200              mcc200                               -                                                                                                                                 -
 Active  powerpc     mpc5xxx        -           -               mcc200              mcc200_COM12                         mcc200:CONSOLE_COM12                                                                                                              -
 Active  powerpc     mpc5xxx        -           -               mcc200              mcc200_COM12_highboot                mcc200:CONSOLE_COM12,SYS_TEXT_BASE=0xFFF00000                                                                                     -
 Active  powerpc     mpc5xxx        -           -               mcc200              mcc200_COM12_highboot_SDRAM          mcc200:CONSOLE_COM12,SYS_TEXT_BASE=0xFFF00000,MCC200_SDRAM                                                                        -
@@ -603,19 +621,17 @@ Active  powerpc     mpc5xxx        -           intercontrol    digsy_mtc
 Active  powerpc     mpc5xxx        -           manroland       -                   hmi1001                              -                                                                                                                                 -
 Active  powerpc     mpc5xxx        -           manroland       -                   mucmc52                              -                                                                                                                                 Heiko Schocher <hs@denx.de>
 Active  powerpc     mpc5xxx        -           manroland       -                   uc101                                -                                                                                                                                 Heiko Schocher <hs@denx.de>
-Active  powerpc     mpc5xxx        -           matrix_vision   mvbc_p              MVBC_P                               MVBC_P:MVBC_P                                                                                                                     Andre Schwarz <andre.schwarz@matrix-vision.de>
-Active  powerpc     mpc5xxx        -           matrix_vision   mvsmr               MVSMR                                -                                                                                                                                 Andre Schwarz <andre.schwarz@matrix-vision.de>
-Active  powerpc     mpc5xxx        -           phytec          pcm030              pcm030                               pcm030                                                                                                                            Jon Smirl <jonsmirl@gmail.com>
+Active  powerpc     mpc5xxx        -           phytec          pcm030              pcm030                               -                                                                                                                                 Jon Smirl <jonsmirl@gmail.com>
 Active  powerpc     mpc5xxx        -           phytec          pcm030              pcm030_LOWBOOT                       pcm030:SYS_TEXT_BASE=0xFF000000                                                                                                   Jon Smirl <jonsmirl@gmail.com>
 Active  powerpc     mpc5xxx        -           tqc             tqm5200             aev                                  -                                                                                                                                 -
 Active  powerpc     mpc5xxx        -           tqc             tqm5200             cam5200                              TQM5200:CAM5200,TQM5200S,TQM5200_B                                                                                                -
 Active  powerpc     mpc5xxx        -           tqc             tqm5200             cam5200_niosflash                    TQM5200:CAM5200,TQM5200S,TQM5200_B,CAM5200_NIOSFLASH                                                                              -
-Active  powerpc     mpc5xxx        -           tqc             tqm5200             charon                               charon                                                                                                                            Heiko Schocher <hs@denx.de>
+Active  powerpc     mpc5xxx        -           tqc             tqm5200             charon                               -                                                                                                                                 Heiko Schocher <hs@denx.de>
 Active  powerpc     mpc5xxx        -           tqc             tqm5200             fo300                                TQM5200:FO300                                                                                                                     -
 Active  powerpc     mpc5xxx        -           tqc             tqm5200             MiniFAP                              TQM5200:MINIFAP                                                                                                                   -
 Active  powerpc     mpc5xxx        -           tqc             tqm5200             TB5200                               -                                                                                                                                 -
 Active  powerpc     mpc5xxx        -           tqc             tqm5200             TB5200_B                             TB5200:TQM5200_B                                                                                                                  -
-Active  powerpc     mpc5xxx        -           tqc             tqm5200             TQM5200                              TQM5200:                                                                                                                          -
+Active  powerpc     mpc5xxx        -           tqc             tqm5200             TQM5200                              -                                                                                                                                 -
 Active  powerpc     mpc5xxx        -           tqc             tqm5200             TQM5200_B                            TQM5200:TQM5200_B                                                                                                                 -
 Active  powerpc     mpc5xxx        -           tqc             tqm5200             TQM5200_B_HIGHBOOT                   TQM5200:TQM5200_B,SYS_TEXT_BASE=0xFFF00000                                                                                        -
 Active  powerpc     mpc5xxx        -           tqc             tqm5200             TQM5200_STK100                       TQM5200:STK52XX_REV100                                                                                                            -
@@ -623,19 +639,14 @@ Active  powerpc     mpc5xxx        -           tqc             tqm5200
 Active  powerpc     mpc5xxx        -           tqc             tqm5200             TQM5200S_HIGHBOOT                    TQM5200:TQM5200_B,TQM5200S,SYS_TEXT_BASE=0xFFF00000                                                                               -
 Active  powerpc     mpc824x        -           -               -                   utx8245                              -                                                                                                                                 Greg Allen <gallen@arlut.utexas.edu>
 Active  powerpc     mpc824x        -           -               a3000               A3000                                -                                                                                                                                 -
-Active  powerpc     mpc824x        -           -               cpc45               CPC45                                CPC45                                                                                                                             Josef Wagner <Wagner@Microsys.de>
+Active  powerpc     mpc824x        -           -               cpc45               CPC45                                -                                                                                                                                 Josef Wagner <Wagner@Microsys.de>
 Active  powerpc     mpc824x        -           -               cpc45               CPC45_ROMBOOT                        CPC45:BOOT_ROM                                                                                                                    Josef Wagner <Wagner@Microsys.de>
 Active  powerpc     mpc824x        -           -               cu824               CU824                                -                                                                                                                                 Wolfgang Denk <wd@denx.de>
 Active  powerpc     mpc824x        -           -               eXalion             eXalion                              -                                                                                                                                 Torsten Demke <torsten.demke@fci.com>
-Active  powerpc     mpc824x        -           -               hidden_dragon       HIDDEN_DRAGON                        -                                                                                                                                 Yusdi Santoso <yusdi_santoso@adaptec.com>
-Active  powerpc     mpc824x        -           -               linkstation         linkstation_HGLAN                    linkstation:HGLAN=1                                                                                                               Guennadi Liakhovetski <g.liakhovetski@gmx.de>
 Active  powerpc     mpc824x        -           -               musenki             MUSENKI                              -                                                                                                                                 Jim Thompson <jim@musenki.com>
 Active  powerpc     mpc824x        -           -               mvblue              MVBLUE                               -                                                                                                                                 -
-Active  powerpc     mpc824x        -           -               pn62                PN62                                 -                                                                                                                                 Wolfgang Grandegger <wg@denx.de>
 Active  powerpc     mpc824x        -           -               sandpoint           Sandpoint8240                        -                                                                                                                                 Wolfgang Denk <wd@denx.de>
 Active  powerpc     mpc824x        -           -               sandpoint           Sandpoint8245                        -                                                                                                                                 Jim Thompson <jim@musenki.com>
-Active  powerpc     mpc824x        -           etin            -                   debris                               -                                                                                                                                 Sangmoon Kim <dogoil@etinsys.com>
-Active  powerpc     mpc824x        -           etin            -                   kvme080                              -                                                                                                                                 Sangmoon Kim <dogoil@etinsys.com>
 Active  powerpc     mpc8260        -           -               -                   atc                                  -                                                                                                                                 Wolfgang Denk <wd@denx.de>
 Active  powerpc     mpc8260        -           -               -                   ep8260                               -                                                                                                                                 Frank Panno <fpanno@delphintech.com>
 Active  powerpc     mpc8260        -           -               -                   ep82xxm                              -                                                                                                                                 -
@@ -644,16 +655,12 @@ Active  powerpc     mpc8260        -           -               -
 Active  powerpc     mpc8260        -           -               -                   ppmc8260                             -                                                                                                                                 Brad Kemp <Brad.Kemp@seranoa.com>
 Active  powerpc     mpc8260        -           -               -                   sacsng                               -                                                                                                                                 Jerry Van Baren <gerald.vanbaren@smiths-aerospace.com>
 Active  powerpc     mpc8260        -           -               cogent              cogent_mpc8260                       -                                                                                                                                 Murray Jensen <Murray.Jensen@csiro.au>
-Active  powerpc     mpc8260        -           -               cpu86               CPU86                                CPU86                                                                                                                             Wolfgang Denk <wd@denx.de>
+Active  powerpc     mpc8260        -           -               cpu86               CPU86                                -                                                                                                                                 Wolfgang Denk <wd@denx.de>
 Active  powerpc     mpc8260        -           -               cpu86               CPU86_ROMBOOT                        CPU86:BOOT_ROM                                                                                                                    Wolfgang Denk <wd@denx.de>
-Active  powerpc     mpc8260        -           -               cpu87               CPU87                                CPU87                                                                                                                             -
+Active  powerpc     mpc8260        -           -               cpu87               CPU87                                -                                                                                                                                 -
 Active  powerpc     mpc8260        -           -               cpu87               CPU87_ROMBOOT                        CPU87:BOOT_ROM                                                                                                                    -
-Active  powerpc     mpc8260        -           -               ep8248              ep8248                               -                                                                                                                                 Yuli Barcohen <yuli@arabellasw.com>
-Active  powerpc     mpc8260        -           -               ep8248              ep8248E                              ep8248                                                                                                                            Yuli Barcohen <yuli@arabellasw.com>
 Active  powerpc     mpc8260        -           -               ids8247             IDS8247                              -                                                                                                                                 Heiko Schocher <hs@denx.de>
 Active  powerpc     mpc8260        -           -               iphase4539          IPHASE4539                           -                                                                                                                                 Wolfgang Grandegger <wg@denx.de>
-Active  powerpc     mpc8260        -           -               ispan               ISPAN                                -                                                                                                                                 Yuli Barcohen <yuli@arabellasw.com>
-Active  powerpc     mpc8260        -           -               ispan               ISPAN_REVB                           ISPAN:SYS_REV_B                                                                                                                   Yuli Barcohen <yuli@arabellasw.com>
 Active  powerpc     mpc8260        -           -               muas3001            muas3001                             -                                                                                                                                 Heiko Schocher <hs@denx.de>
 Active  powerpc     mpc8260        -           -               muas3001            muas3001_dev                         muas3001:MUAS_DEV_BOARD                                                                                                           Heiko Schocher <hs@denx.de>
 Active  powerpc     mpc8260        -           -               pm826               PM825                                PM826:PCI,SYS_TEXT_BASE=0xFF000000                                                                                                Wolfgang Denk <wd@denx.de>
@@ -664,29 +671,10 @@ Active  powerpc     mpc8260        -           -               pm826
 Active  powerpc     mpc8260        -           -               pm826               PM826_BIGFLASH                       PM826:FLASH_32MB,SYS_TEXT_BASE=0x40000000                                                                                         Wolfgang Denk <wd@denx.de>
 Active  powerpc     mpc8260        -           -               pm826               PM826_ROMBOOT                        PM826:BOOT_ROM,SYS_TEXT_BASE=0xFF800000                                                                                           Wolfgang Denk <wd@denx.de>
 Active  powerpc     mpc8260        -           -               pm826               PM826_ROMBOOT_BIGFLASH               PM826:BOOT_ROM,FLASH_32MB,SYS_TEXT_BASE=0xFF800000                                                                                Wolfgang Denk <wd@denx.de>
-Active  powerpc     mpc8260        -           -               pm828               PM828                                PM828                                                                                                                             -
+Active  powerpc     mpc8260        -           -               pm828               PM828                                -                                                                                                                                 -
 Active  powerpc     mpc8260        -           -               pm828               PM828_PCI                            PM828:PCI                                                                                                                         -
 Active  powerpc     mpc8260        -           -               pm828               PM828_ROMBOOT                        PM828:BOOT_ROM,SYS_TEXT_BASE=0xFF800000                                                                                           -
 Active  powerpc     mpc8260        -           -               pm828               PM828_ROMBOOT_PCI                    PM828:PCI,BOOT_ROM,SYS_TEXT_BASE=0xFF800000                                                                                       -
-Active  powerpc     mpc8260        -           -               rattler             Rattler                              Rattler                                                                                                                           Yuli Barcohen <yuli@arabellasw.com>
-Active  powerpc     mpc8260        -           -               rattler             Rattler8248                          Rattler:MPC8248                                                                                                                   Yuli Barcohen <yuli@arabellasw.com>
-Active  powerpc     mpc8260        -           -               zpc1900             ZPC1900                              -                                                                                                                                 Yuli Barcohen <yuli@arabellasw.com>
-Active  powerpc     mpc8260        -           freescale       mpc8260ads          MPC8260ADS                           MPC8260ADS:ADSTYPE=CONFIG_SYS_8260ADS                                                                                             Yuli Barcohen <yuli@arabellasw.com>
-Active  powerpc     mpc8260        -           freescale       mpc8260ads          MPC8260ADS_33MHz                     MPC8260ADS:ADSTYPE=CONFIG_SYS_8260ADS,8260_CLKIN=33000000                                                                         Yuli Barcohen <yuli@arabellasw.com>
-Active  powerpc     mpc8260        -           freescale       mpc8260ads          MPC8260ADS_33MHz_lowboot             MPC8260ADS:ADSTYPE=CONFIG_SYS_8260ADS,8260_CLKIN=33000000,SYS_TEXT_BASE=0xFF800000                                                Yuli Barcohen <yuli@arabellasw.com>
-Active  powerpc     mpc8260        -           freescale       mpc8260ads          MPC8260ADS_40MHz                     MPC8260ADS:ADSTYPE=CONFIG_SYS_8260ADS,8260_CLKIN=40000000                                                                         Yuli Barcohen <yuli@arabellasw.com>
-Active  powerpc     mpc8260        -           freescale       mpc8260ads          MPC8260ADS_40MHz_lowboot             MPC8260ADS:ADSTYPE=CONFIG_SYS_8260ADS,8260_CLKIN=40000000,SYS_TEXT_BASE=0xFF800000                                                Yuli Barcohen <yuli@arabellasw.com>
-Active  powerpc     mpc8260        -           freescale       mpc8260ads          MPC8260ADS_lowboot                   MPC8260ADS:ADSTYPE=CONFIG_SYS_8260ADS,SYS_TEXT_BASE=0xFF800000                                                                    Yuli Barcohen <yuli@arabellasw.com>
-Active  powerpc     mpc8260        -           freescale       mpc8260ads          MPC8272ADS                           MPC8260ADS:ADSTYPE=CONFIG_SYS_8272ADS                                                                                             Yuli Barcohen <yuli@arabellasw.com>
-Active  powerpc     mpc8260        -           freescale       mpc8260ads          MPC8272ADS_lowboot                   MPC8260ADS:ADSTYPE=CONFIG_SYS_8272ADS,SYS_TEXT_BASE=0xFF800000                                                                    Yuli Barcohen <yuli@arabellasw.com>
-Active  powerpc     mpc8260        -           freescale       mpc8260ads          PQ2FADS                              MPC8260ADS:ADSTYPE=CONFIG_SYS_PQ2FADS                                                                                             Yuli Barcohen <yuli@arabellasw.com>
-Active  powerpc     mpc8260        -           freescale       mpc8260ads          PQ2FADS-VR                           MPC8260ADS:ADSTYPE=CONFIG_SYS_PQ2FADS,8260_CLKIN=66000000                                                                         Yuli Barcohen <yuli@arabellasw.com>
-Active  powerpc     mpc8260        -           freescale       mpc8260ads          PQ2FADS-VR_lowboot                   MPC8260ADS:ADSTYPE=CONFIG_SYS_PQ2FADS,8260_CLKIN=66000000,SYS_TEXT_BASE=0xFF800000                                                Yuli Barcohen <yuli@arabellasw.com>
-Active  powerpc     mpc8260        -           freescale       mpc8260ads          PQ2FADS-ZU                           MPC8260ADS:ADSTYPE=CONFIG_SYS_PQ2FADS                                                                                             Yuli Barcohen <yuli@arabellasw.com>
-Active  powerpc     mpc8260        -           freescale       mpc8260ads          PQ2FADS-ZU_66MHz                     MPC8260ADS:ADSTYPE=CONFIG_SYS_PQ2FADS,8260_CLKIN=66000000                                                                         Yuli Barcohen <yuli@arabellasw.com>
-Active  powerpc     mpc8260        -           freescale       mpc8260ads          PQ2FADS-ZU_66MHz_lowboot             MPC8260ADS:ADSTYPE=CONFIG_SYS_PQ2FADS,8260_CLKIN=66000000,SYS_TEXT_BASE=0xFF800000                                                Yuli Barcohen <yuli@arabellasw.com>
-Active  powerpc     mpc8260        -           freescale       mpc8260ads          PQ2FADS-ZU_lowboot                   MPC8260ADS:ADSTYPE=CONFIG_SYS_PQ2FADS,SYS_TEXT_BASE=0xFF800000                                                                    Yuli Barcohen <yuli@arabellasw.com>
-Active  powerpc     mpc8260        -           freescale       mpc8260ads          PQ2FADS_lowboot                      MPC8260ADS:ADSTYPE=CONFIG_SYS_PQ2FADS,SYS_TEXT_BASE=0xFF800000                                                                    Yuli Barcohen <yuli@arabellasw.com>
 Active  powerpc     mpc8260        -           freescale       mpc8266ads          MPC8266ADS                           -                                                                                                                                 Rune Torgersen <runet@innovsys.com>
 Active  powerpc     mpc8260        -           funkwerk        vovpn-gw            VoVPN-GW_66MHz                       VoVPN-GW:CLKIN_66MHz                                                                                                              -
 Active  powerpc     mpc8260        -           keymile         km82xx              mgcoge                               km82xx:MGCOGE                                                                                                                     Holger Brunck <holger.brunck@keymile.com>
@@ -704,21 +692,21 @@ Active  powerpc     mpc8260        -           tqc             tqm8260
 Active  powerpc     mpc8260        -           tqc             tqm8260             TQM8265_AA                           TQM8260:MPC8265,300MHz,BUSMODE_60x                                                                                                Wolfgang Denk <wd@denx.de>
 Active  powerpc     mpc8260        -           tqc             tqm8272             TQM8272                              -                                                                                                                                 -
 Active  powerpc     mpc83xx        -           -               -                   mpc8308_p1m                          -                                                                                                                                 Ilya Yanok <yanok@emcraft.com>
-Active  powerpc     mpc83xx        -           -               sbc8349             sbc8349                              sbc8349                                                                                                                           Paul Gortmaker <paul.gortmaker@windriver.com>
+Active  powerpc     mpc83xx        -           -               sbc8349             sbc8349                              -                                                                                                                                 Paul Gortmaker <paul.gortmaker@windriver.com>
 Active  powerpc     mpc83xx        -           -               sbc8349             sbc8349_PCI_33                       sbc8349:PCI,PCI_33M                                                                                                               Paul Gortmaker <paul.gortmaker@windriver.com>
 Active  powerpc     mpc83xx        -           -               sbc8349             sbc8349_PCI_66                       sbc8349:PCI,PCI_66M                                                                                                               Paul Gortmaker <paul.gortmaker@windriver.com>
 Active  powerpc     mpc83xx        -           -               ve8313              ve8313                               -                                                                                                                                 Heiko Schocher <hs@denx.de>
 Active  powerpc     mpc83xx        -           esd             vme8349             caddy2                               vme8349:CADDY2                                                                                                                    Reinhard Arlt <reinhard.arlt@esd-electronics.com>
-Active  powerpc     mpc83xx        -           esd             vme8349             vme8349                              vme8349                                                                                                                           Reinhard Arlt <reinhard.arlt@esd-electronics.com>
+Active  powerpc     mpc83xx        -           esd             vme8349             vme8349                              -                                                                                                                                 Reinhard Arlt <reinhard.arlt@esd-electronics.com>
 Active  powerpc     mpc83xx        -           freescale       mpc8308rdb          MPC8308RDB                           -                                                                                                                                 Ilya Yanok <yanok@emcraft.com>
 Active  powerpc     mpc83xx        -           freescale       mpc8313erdb         MPC8313ERDB_33                       MPC8313ERDB:SYS_33MHZ                                                                                                             -
 Active  powerpc     mpc83xx        -           freescale       mpc8313erdb         MPC8313ERDB_66                       MPC8313ERDB:SYS_66MHZ                                                                                                             -
 Active  powerpc     mpc83xx        -           freescale       mpc8313erdb         MPC8313ERDB_NAND_33                  MPC8313ERDB:SYS_33MHZ,NAND                                                                                                        -
 Active  powerpc     mpc83xx        -           freescale       mpc8313erdb         MPC8313ERDB_NAND_66                  MPC8313ERDB:SYS_66MHZ,NAND                                                                                                        -
-Active  powerpc     mpc83xx        -           freescale       mpc8315erdb         MPC8315ERDB                          MPC8315ERDB                                                                                                                       Dave Liu <daveliu@freescale.com>
+Active  powerpc     mpc83xx        -           freescale       mpc8315erdb         MPC8315ERDB                          -                                                                                                                                 Dave Liu <daveliu@freescale.com>
 Active  powerpc     mpc83xx        -           freescale       mpc8315erdb         MPC8315ERDB_NAND                     MPC8315ERDB:NAND_U_BOOT                                                                                                           Dave Liu <daveliu@freescale.com>
 Active  powerpc     mpc83xx        -           freescale       mpc8323erdb         MPC8323ERDB                          -                                                                                                                                 Michael Barkowski <michael.barkowski@freescale.com>
-Active  powerpc     mpc83xx        -           freescale       mpc832xemds         MPC832XEMDS                          MPC832XEMDS:                                                                                                                      Dave Liu <daveliu@freescale.com>
+Active  powerpc     mpc83xx        -           freescale       mpc832xemds         MPC832XEMDS                          -                                                                                                                                 Dave Liu <daveliu@freescale.com>
 Active  powerpc     mpc83xx        -           freescale       mpc832xemds         MPC832XEMDS_ATM                      MPC832XEMDS:PQ_MDS_PIB=1,PQ_MDS_PIB_ATM=1                                                                                         Dave Liu <daveliu@freescale.com>
 Active  powerpc     mpc83xx        -           freescale       mpc832xemds         MPC832XEMDS_HOST_33                  MPC832XEMDS:PCI,PCI_33M,PQ_MDS_PIB=1                                                                                              Dave Liu <daveliu@freescale.com>
 Active  powerpc     mpc83xx        -           freescale       mpc832xemds         MPC832XEMDS_HOST_66                  MPC832XEMDS:PCI,PCI_66M,PQ_MDS_PIB=1                                                                                              Dave Liu <daveliu@freescale.com>
@@ -737,10 +725,7 @@ Active  powerpc     mpc83xx        -           freescale       mpc8360emds
 Active  powerpc     mpc83xx        -           freescale       mpc8360emds         MPC8360EMDS_66_HOST_33               MPC8360EMDS:CLKIN_66MHZ,PCI,PCI_33M,PQ_MDS_PIB=1                                                                                  Dave Liu <daveliu@freescale.com>
 Active  powerpc     mpc83xx        -           freescale       mpc8360emds         MPC8360EMDS_66_HOST_66               MPC8360EMDS:CLKIN_66MHZ,PCI,PCI_66M,PQ_MDS_PIB=1                                                                                  Dave Liu <daveliu@freescale.com>
 Active  powerpc     mpc83xx        -           freescale       mpc8360emds         MPC8360EMDS_66_SLAVE                 MPC8360EMDS:CLKIN_66MHZ,PCI,PCISLAVE                                                                                              Dave Liu <daveliu@freescale.com>
-Active  powerpc     mpc83xx        -           freescale       mpc8360erdk         MPC8360ERDK                          MPC8360ERDK                                                                                                                       Anton Vorontsov <avorontsov@ru.mvista.com>
-Active  powerpc     mpc83xx        -           freescale       mpc8360erdk         MPC8360ERDK_33                       MPC8360ERDK:CLKIN_33MHZ                                                                                                           Anton Vorontsov <avorontsov@ru.mvista.com>
-Active  powerpc     mpc83xx        -           freescale       mpc8360erdk         MPC8360ERDK_66                       MPC8360ERDK                                                                                                                       Anton Vorontsov <avorontsov@ru.mvista.com>
-Active  powerpc     mpc83xx        -           freescale       mpc837xemds         MPC837XEMDS                          MPC837XEMDS                                                                                                                       Dave Liu <daveliu@freescale.com>
+Active  powerpc     mpc83xx        -           freescale       mpc837xemds         MPC837XEMDS                          -                                                                                                                                 Dave Liu <daveliu@freescale.com>
 Active  powerpc     mpc83xx        -           freescale       mpc837xemds         MPC837XEMDS_HOST                     MPC837XEMDS:PCI                                                                                                                   Dave Liu <daveliu@freescale.com>
 Active  powerpc     mpc83xx        -           freescale       mpc837xerdb         MPC837XERDB                          -                                                                                                                                 Joe D'Abbraccio <ljd015@freescale.com>
 Active  powerpc     mpc83xx        -           keymile         km83xx              kmcoge5ne                            km8360:KMCOGE5NE                                                                                                                  Holger Brunck <holger.brunck@keymile.com>
@@ -751,12 +736,10 @@ Active  powerpc     mpc83xx        -           keymile         km83xx
 Active  powerpc     mpc83xx        -           keymile         km83xx              suvd3                                suvd3:SUVD3                                                                                                                       Holger Brunck <holger.brunck@keymile.com>
 Active  powerpc     mpc83xx        -           keymile         km83xx              tuge1                                tuxx1:TUGE1                                                                                                                       Holger Brunck <holger.brunck@keymile.com>
 Active  powerpc     mpc83xx        -           keymile         km83xx              tuxx1                                tuxx1:TUXX1                                                                                                                       Holger Brunck <holger.brunck@keymile.com>
-Active  powerpc     mpc83xx        -           matrix_vision   mergerbox           MERGERBOX                            -                                                                                                                                 Andre Schwarz <andre.schwarz@matrix-vision.de>
-Active  powerpc     mpc83xx        -           matrix_vision   mvblm7              MVBLM7                               -                                                                                                                                 Andre Schwarz <andre.schwarz@matrix-vision.de>
 Active  powerpc     mpc83xx        -           sheldon         simpc8313           SIMPC8313_LP                         SIMPC8313:NAND_LP                                                                                                                 Ron Madrid <info@sheldoninst.com>
 Active  powerpc     mpc83xx        -           sheldon         simpc8313           SIMPC8313_SP                         SIMPC8313:NAND_SP                                                                                                                 Ron Madrid <info@sheldoninst.com>
 Active  powerpc     mpc83xx        -           tqc             tqm834x             TQM834x                              -                                                                                                                                 -
-Active  powerpc     mpc85xx        -           -               sbc8548             sbc8548                              sbc8548                                                                                                                           Paul Gortmaker <paul.gortmaker@windriver.com>
+Active  powerpc     mpc85xx        -           -               sbc8548             sbc8548                              -                                                                                                                                 Paul Gortmaker <paul.gortmaker@windriver.com>
 Active  powerpc     mpc85xx        -           -               sbc8548             sbc8548_PCI_33                       sbc8548:PCI,33                                                                                                                    Paul Gortmaker <paul.gortmaker@windriver.com>
 Active  powerpc     mpc85xx        -           -               sbc8548             sbc8548_PCI_33_PCIE                  sbc8548:PCI,33,PCIE                                                                                                               Paul Gortmaker <paul.gortmaker@windriver.com>
 Active  powerpc     mpc85xx        -           -               sbc8548             sbc8548_PCI_66                       sbc8548:PCI,66                                                                                                                    Paul Gortmaker <paul.gortmaker@windriver.com>
@@ -764,12 +747,12 @@ Active  powerpc     mpc85xx        -           -               sbc8548
 Active  powerpc     mpc85xx        -           -               socrates            socrates                             -                                                                                                                                 -
 Active  powerpc     mpc85xx        -           exmeritus       hww1u1a             HWW1U1A                              -                                                                                                                                 Kyle Moffett <Kyle.D.Moffett@boeing.com>
 Active  powerpc     mpc85xx        -           freescale       b4860qds            B4420QDS                             B4860QDS:PPC_B4420                                                                                                                -
-Active  powerpc     mpc85xx        -           freescale       b4860qds            B4420QDS_NAND                        B4860QDS:PPC_B4420,RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF80000                                                                      -
-Active  powerpc     mpc85xx        -           freescale       b4860qds            B4420QDS_SPIFLASH                    B4860QDS:PPC_B4420,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF80000                                                                  -
+Active  powerpc     mpc85xx        -           freescale       b4860qds            B4420QDS_NAND                        B4860QDS:PPC_B4420,RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF40000                                                                      -
+Active  powerpc     mpc85xx        -           freescale       b4860qds            B4420QDS_SPIFLASH                    B4860QDS:PPC_B4420,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000                                                                  -
 Active  powerpc     mpc85xx        -           freescale       b4860qds            B4860QDS                             B4860QDS:PPC_B4860                                                                                                                -
-Active  powerpc     mpc85xx        -           freescale       b4860qds            B4860QDS_NAND                        B4860QDS:PPC_B4860,RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF80000                                                                      -
-Active  powerpc     mpc85xx        -           freescale       b4860qds            B4860QDS_SPIFLASH                    B4860QDS:PPC_B4860,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF80000                                                                  -
-Active  powerpc     mpc85xx        -           freescale       b4860qds            B4860QDS_SRIO_PCIE_BOOT              B4860QDS:PPC_B4860,SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF80000                                                                  -
+Active  powerpc     mpc85xx        -           freescale       b4860qds            B4860QDS_NAND                        B4860QDS:PPC_B4860,RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF40000                                                                      -
+Active  powerpc     mpc85xx        -           freescale       b4860qds            B4860QDS_SPIFLASH                    B4860QDS:PPC_B4860,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000                                                                  -
+Active  powerpc     mpc85xx        -           freescale       b4860qds            B4860QDS_SRIO_PCIE_BOOT              B4860QDS:PPC_B4860,SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF40000                                                                  -
 Active  powerpc     mpc85xx        -           freescale       bsc9131rdb          BSC9131RDB_NAND                      BSC9131RDB:BSC9131RDB,NAND                                                                                                        Poonam Aggrwal <poonam.aggrwal@freescale.com>
 Active  powerpc     mpc85xx        -           freescale       bsc9131rdb          BSC9131RDB_NAND_SYSCLK100            BSC9131RDB:BSC9131RDB,NAND,SYS_CLK_100                                                                                            Poonam Aggrwal <poonam.aggrwal@freescale.com>
 Active  powerpc     mpc85xx        -           freescale       bsc9131rdb          BSC9131RDB_SPIFLASH                  BSC9131RDB:BSC9131RDB,SPIFLASH                                                                                                    Poonam Aggrwal <poonam.aggrwal@freescale.com>
@@ -783,64 +766,79 @@ Active  powerpc     mpc85xx        -           freescale       bsc9132qds
 Active  powerpc     mpc85xx        -           freescale       bsc9132qds          BSC9132QDS_SPIFLASH_DDRCLK100        BSC9132QDS:BSC9132QDS,SPIFLASH,SYS_CLK_100_DDR_100                                                                                Naveen Burmi <NaveenBurmi@freescale.com>
 Active  powerpc     mpc85xx        -           freescale       bsc9132qds          BSC9132QDS_SPIFLASH_DDRCLK133        BSC9132QDS:BSC9132QDS,SPIFLASH,SYS_CLK_100_DDR_133                                                                                Naveen Burmi <NaveenBurmi@freescale.com>
 Active  powerpc     mpc85xx        -           freescale       c29xpcie            C29XPCIE                             C29XPCIE:C29XPCIE,36BIT                                                                                                           Po Liu <po.liu@freescale.com>
+Active  powerpc     mpc85xx        -           freescale       c29xpcie            C29XPCIE_NAND                        C29XPCIE:C29XPCIE,36BIT,NAND                                                                                                      Po Liu <po.liu@freescale.com>
 Active  powerpc     mpc85xx        -           freescale       c29xpcie            C29XPCIE_SPIFLASH                    C29XPCIE:C29XPCIE,36BIT,SPIFLASH                                                                                                  Po Liu <po.liu@freescale.com>
 Active  powerpc     mpc85xx        -           freescale       corenet_ds          P3041DS                              -                                                                                                                                 -
-Active  powerpc     mpc85xx        -           freescale       corenet_ds          P3041DS_NAND                         P3041DS:RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF80000                                                                                 -
-Active  powerpc     mpc85xx        -           freescale       corenet_ds          P3041DS_SDCARD                       P3041DS:RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF80000                                                                               -
+Active  powerpc     mpc85xx        -           freescale       corenet_ds          P3041DS_NAND                         P3041DS:RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF40000                                                                                 -
+Active  powerpc     mpc85xx        -           freescale       corenet_ds          P3041DS_SDCARD                       P3041DS:RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF40000                                                                               -
 Active  powerpc     mpc85xx        -           freescale       corenet_ds          P3041DS_SECURE_BOOT                  P3041DS:SECURE_BOOT                                                                                                               -
-Active  powerpc     mpc85xx        -           freescale       corenet_ds          P3041DS_SPIFLASH                     P3041DS:RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF80000                                                                             -
-Active  powerpc     mpc85xx        -           freescale       corenet_ds          P3041DS_SRIO_PCIE_BOOT               P3041DS:SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF80000                                                                             -
+Active  powerpc     mpc85xx        -           freescale       corenet_ds          P3041DS_SPIFLASH                     P3041DS:RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000                                                                             -
+Active  powerpc     mpc85xx        -           freescale       corenet_ds          P3041DS_SRIO_PCIE_BOOT               P3041DS:SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF40000                                                                             -
 Active  powerpc     mpc85xx        -           freescale       corenet_ds          P4080DS                              -                                                                                                                                 -
-Active  powerpc     mpc85xx        -           freescale       corenet_ds          P4080DS_SDCARD                       P4080DS:RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF80000                                                                               -
+Active  powerpc     mpc85xx        -           freescale       corenet_ds          P4080DS_SDCARD                       P4080DS:RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF40000                                                                               -
 Active  powerpc     mpc85xx        -           freescale       corenet_ds          P4080DS_SECURE_BOOT                  P4080DS:SECURE_BOOT                                                                                                               -
-Active  powerpc     mpc85xx        -           freescale       corenet_ds          P4080DS_SPIFLASH                     P4080DS:RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF80000                                                                             -
-Active  powerpc     mpc85xx        -           freescale       corenet_ds          P4080DS_SRIO_PCIE_BOOT               P4080DS:SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF80000                                                                             -
+Active  powerpc     mpc85xx        -           freescale       corenet_ds          P4080DS_SPIFLASH                     P4080DS:RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000                                                                             -
+Active  powerpc     mpc85xx        -           freescale       corenet_ds          P4080DS_SRIO_PCIE_BOOT               P4080DS:SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF40000                                                                             -
 Active  powerpc     mpc85xx        -           freescale       corenet_ds          P5020DS                              -                                                                                                                                 -
-Active  powerpc     mpc85xx        -           freescale       corenet_ds          P5020DS_NAND                         P5020DS:RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF80000                                                                                 -
-Active  powerpc     mpc85xx        -           freescale       corenet_ds          P5020DS_SDCARD                       P5020DS:RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF80000                                                                               -
+Active  powerpc     mpc85xx        -           freescale       corenet_ds          P5020DS_NAND                         P5020DS:RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF40000                                                                                 -
+Active  powerpc     mpc85xx        -           freescale       corenet_ds          P5020DS_SDCARD                       P5020DS:RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF40000                                                                               -
 Active  powerpc     mpc85xx        -           freescale       corenet_ds          P5020DS_SECURE_BOOT                  P5020DS:SECURE_BOOT                                                                                                               -
-Active  powerpc     mpc85xx        -           freescale       corenet_ds          P5020DS_SPIFLASH                     P5020DS:RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF80000                                                                             -
-Active  powerpc     mpc85xx        -           freescale       corenet_ds          P5020DS_SRIO_PCIE_BOOT               P5020DS:SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF80000                                                                             -
+Active  powerpc     mpc85xx        -           freescale       corenet_ds          P5020DS_SPIFLASH                     P5020DS:RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000                                                                             -
+Active  powerpc     mpc85xx        -           freescale       corenet_ds          P5020DS_SRIO_PCIE_BOOT               P5020DS:SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF40000                                                                             -
 Active  powerpc     mpc85xx        -           freescale       corenet_ds          P5040DS                              -                                                                                                                                 -
-Active  powerpc     mpc85xx        -           freescale       corenet_ds          P5040DS_NAND                         P5040DS:RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF80000                                                                                 -
-Active  powerpc     mpc85xx        -           freescale       corenet_ds          P5040DS_SDCARD                       P5040DS:RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF80000                                                                               -
-Active  powerpc     mpc85xx        -           freescale       corenet_ds          P5040DS_SPIFLASH                     P5040DS:RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF80000                                                                             -
-Active  powerpc     mpc85xx        -           freescale       mpc8536ds           MPC8536DS                            MPC8536DS                                                                                                                         -
+Active  powerpc     mpc85xx        -           freescale       corenet_ds          P5040DS_NAND                         P5040DS:RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF40000                                                                                 -
+Active  powerpc     mpc85xx        -           freescale       corenet_ds          P5040DS_SDCARD                       P5040DS:RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF40000                                                                               -
+Active  powerpc     mpc85xx        -           freescale       corenet_ds          P5040DS_SPIFLASH                     P5040DS:RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000                                                                             -
+Active  powerpc     mpc85xx        -           freescale       mpc8536ds           MPC8536DS                            -                                                                                                                                 -
 Active  powerpc     mpc85xx        -           freescale       mpc8536ds           MPC8536DS_36BIT                      MPC8536DS:36BIT                                                                                                                   -
 Active  powerpc     mpc85xx        -           freescale       mpc8536ds           MPC8536DS_NAND                       MPC8536DS:NAND                                                                                                                    -
 Active  powerpc     mpc85xx        -           freescale       mpc8536ds           MPC8536DS_SDCARD                     MPC8536DS:SDCARD                                                                                                                  -
 Active  powerpc     mpc85xx        -           freescale       mpc8536ds           MPC8536DS_SPIFLASH                   MPC8536DS:SPIFLASH                                                                                                                -
 Active  powerpc     mpc85xx        -           freescale       mpc8540ads          MPC8540ADS                           -                                                                                                                                 Kumar Gala <kumar.gala@freescale.com>
-Active  powerpc     mpc85xx        -           freescale       mpc8541cds          MPC8541CDS                           MPC8541CDS                                                                                                                        Kumar Gala <kumar.gala@freescale.com>
+Active  powerpc     mpc85xx        -           freescale       mpc8541cds          MPC8541CDS                           -                                                                                                                                 Kumar Gala <kumar.gala@freescale.com>
 Active  powerpc     mpc85xx        -           freescale       mpc8541cds          MPC8541CDS_legacy                    MPC8541CDS:LEGACY                                                                                                                 Kumar Gala <kumar.gala@freescale.com>
 Active  powerpc     mpc85xx        -           freescale       mpc8544ds           MPC8544DS                            -                                                                                                                                 -
-Active  powerpc     mpc85xx        -           freescale       mpc8548cds          MPC8548CDS                           MPC8548CDS                                                                                                                        -
+Active  powerpc     mpc85xx        -           freescale       mpc8548cds          MPC8548CDS                           -                                                                                                                                 -
 Active  powerpc     mpc85xx        -           freescale       mpc8548cds          MPC8548CDS_36BIT                     MPC8548CDS:36BIT                                                                                                                  -
 Active  powerpc     mpc85xx        -           freescale       mpc8548cds          MPC8548CDS_legacy                    MPC8548CDS:LEGACY                                                                                                                 -
-Active  powerpc     mpc85xx        -           freescale       mpc8555cds          MPC8555CDS                           MPC8555CDS                                                                                                                        Kumar Gala <kumar.gala@freescale.com>
+Active  powerpc     mpc85xx        -           freescale       mpc8555cds          MPC8555CDS                           -                                                                                                                                 Kumar Gala <kumar.gala@freescale.com>
 Active  powerpc     mpc85xx        -           freescale       mpc8555cds          MPC8555CDS_legacy                    MPC8555CDS:LEGACY                                                                                                                 Kumar Gala <kumar.gala@freescale.com>
 Active  powerpc     mpc85xx        -           freescale       mpc8560ads          MPC8560ADS                           -                                                                                                                                 Kumar Gala <kumar.gala@freescale.com>
 Active  powerpc     mpc85xx        -           freescale       mpc8568mds          MPC8568MDS                           -                                                                                                                                 -
-Active  powerpc     mpc85xx        -           freescale       mpc8569mds          MPC8569MDS                           MPC8569MDS                                                                                                                        -
+Active  powerpc     mpc85xx        -           freescale       mpc8569mds          MPC8569MDS                           -                                                                                                                                 -
 Active  powerpc     mpc85xx        -           freescale       mpc8569mds          MPC8569MDS_ATM                       MPC8569MDS:ATM                                                                                                                    -
 Active  powerpc     mpc85xx        -           freescale       mpc8569mds          MPC8569MDS_NAND                      MPC8569MDS:NAND                                                                                                                   -
-Active  powerpc     mpc85xx        -           freescale       mpc8572ds           MPC8572DS                            MPC8572DS                                                                                                                         -
+Active  powerpc     mpc85xx        -           freescale       mpc8572ds           MPC8572DS                            -                                                                                                                                 -
 Active  powerpc     mpc85xx        -           freescale       mpc8572ds           MPC8572DS_36BIT                      MPC8572DS:36BIT                                                                                                                   -
 Active  powerpc     mpc85xx        -           freescale       mpc8572ds           MPC8572DS_NAND                       MPC8572DS:NAND                                                                                                                    -
-Active  powerpc     mpc85xx        -           freescale       p1010rdb            P1010RDB_36BIT_NAND                  P1010RDB:P1010RDB,36BIT,NAND                                                                                                      -
-Active  powerpc     mpc85xx        -           freescale       p1010rdb            P1010RDB_36BIT_NAND_SECBOOT          P1010RDB:P1010RDB,36BIT,NAND_SECBOOT,SECURE_BOOT                                                                                  -
-Active  powerpc     mpc85xx        -           freescale       p1010rdb            P1010RDB_36BIT_NOR                   P1010RDB:P1010RDB,36BIT                                                                                                           -
-Active  powerpc     mpc85xx        -           freescale       p1010rdb            P1010RDB_36BIT_NOR_SECBOOT           P1010RDB:P1010RDB,36BIT,SECURE_BOOT                                                                                               -
-Active  powerpc     mpc85xx        -           freescale       p1010rdb            P1010RDB_36BIT_SDCARD                P1010RDB:P1010RDB,36BIT,SDCARD                                                                                                    -
-Active  powerpc     mpc85xx        -           freescale       p1010rdb            P1010RDB_36BIT_SPIFLASH              P1010RDB:P1010RDB,36BIT,SPIFLASH                                                                                                  -
-Active  powerpc     mpc85xx        -           freescale       p1010rdb            P1010RDB_36BIT_SPIFLASH_SECBOOT      P1010RDB:P1010RDB,36BIT,SPIFLASH,SECURE_BOOT                                                                                      -
-Active  powerpc     mpc85xx        -           freescale       p1010rdb            P1010RDB_NAND                        P1010RDB:P1010RDB,NAND                                                                                                            -
-Active  powerpc     mpc85xx        -           freescale       p1010rdb            P1010RDB_NAND_SECBOOT                P1010RDB:P1010RDB,NAND_SECBOOT,SECURE_BOOT                                                                                        -
-Active  powerpc     mpc85xx        -           freescale       p1010rdb            P1010RDB_NOR                         P1010RDB:P1010RDB                                                                                                                 -
-Active  powerpc     mpc85xx        -           freescale       p1010rdb            P1010RDB_NOR_SECBOOT                 P1010RDB:P1010RDB,SECURE_BOOT                                                                                                     -
-Active  powerpc     mpc85xx        -           freescale       p1010rdb            P1010RDB_SDCARD                      P1010RDB:P1010RDB,SDCARD                                                                                                          -
-Active  powerpc     mpc85xx        -           freescale       p1010rdb            P1010RDB_SPIFLASH                    P1010RDB:P1010RDB,SPIFLASH                                                                                                        -
-Active  powerpc     mpc85xx        -           freescale       p1010rdb            P1010RDB_SPIFLASH_SECBOOT            P1010RDB:P1010RDB,SPIFLASH,SECURE_BOOT                                                                                            -
+Active  powerpc     mpc85xx        -           freescale       p1010rdb            P1010RDB-PA_36BIT_NAND               P1010RDB:P1010RDB_PA,36BIT,NAND                                                                                                   -
+Active  powerpc     mpc85xx        -           freescale       p1010rdb            P1010RDB-PA_36BIT_NAND_SECBOOT       P1010RDB:P1010RDB_PA,36BIT,NAND_SECBOOT,SECURE_BOOT                                                                               -
+Active  powerpc     mpc85xx        -           freescale       p1010rdb            P1010RDB-PA_36BIT_NOR                P1010RDB:P1010RDB_PA,36BIT                                                                                                        -
+Active  powerpc     mpc85xx        -           freescale       p1010rdb            P1010RDB-PA_36BIT_NOR_SECBOOT        P1010RDB:P1010RDB_PA,36BIT,SECURE_BOOT                                                                                            -
+Active  powerpc     mpc85xx        -           freescale       p1010rdb            P1010RDB-PA_36BIT_SDCARD             P1010RDB:P1010RDB_PA,36BIT,SDCARD                                                                                                 -
+Active  powerpc     mpc85xx        -           freescale       p1010rdb            P1010RDB-PA_36BIT_SPIFLASH           P1010RDB:P1010RDB_PA,36BIT,SPIFLASH                                                                                               -
+Active  powerpc     mpc85xx        -           freescale       p1010rdb            P1010RDB-PA_36BIT_SPIFLASH_SECBOOT   P1010RDB:P1010RDB_PA,36BIT,SPIFLASH,SECURE_BOOT                                                                                   -
+Active  powerpc     mpc85xx        -           freescale       p1010rdb            P1010RDB-PA_NAND                     P1010RDB:P1010RDB_PA,NAND                                                                                                         -
+Active  powerpc     mpc85xx        -           freescale       p1010rdb            P1010RDB-PA_NAND_SECBOOT             P1010RDB:P1010RDB_PA,NAND_SECBOOT,SECURE_BOOT                                                                                     -
+Active  powerpc     mpc85xx        -           freescale       p1010rdb            P1010RDB-PA_NOR                      P1010RDB:P1010RDB_PA                                                                                                              -
+Active  powerpc     mpc85xx        -           freescale       p1010rdb            P1010RDB-PA_NOR_SECBOOT              P1010RDB:P1010RDB_PA,SECURE_BOOT                                                                                                  -
+Active  powerpc     mpc85xx        -           freescale       p1010rdb            P1010RDB-PA_SDCARD                   P1010RDB:P1010RDB_PA,SDCARD                                                                                                       -
+Active  powerpc     mpc85xx        -           freescale       p1010rdb            P1010RDB-PA_SPIFLASH                 P1010RDB:P1010RDB_PA,SPIFLASH                                                                                                     -
+Active  powerpc     mpc85xx        -           freescale       p1010rdb            P1010RDB-PA_SPIFLASH_SECBOOT         P1010RDB:P1010RDB_PA,SPIFLASH,SECURE_BOOT                                                                                         -
+Active  powerpc     mpc85xx        -           freescale       p1010rdb            P1010RDB-PB_36BIT_NAND               P1010RDB:P1010RDB_PB,36BIT,NAND                                                                                                   -
+Active  powerpc     mpc85xx        -           freescale       p1010rdb            P1010RDB-PB_36BIT_NAND_SECBOOT       P1010RDB:P1010RDB_PB,36BIT,NAND_SECBOOT,SECURE_BOOT                                                                               -
+Active  powerpc     mpc85xx        -           freescale       p1010rdb            P1010RDB-PB_36BIT_NOR                P1010RDB:P1010RDB_PB,36BIT                                                                                                        -
+Active  powerpc     mpc85xx        -           freescale       p1010rdb            P1010RDB-PB_36BIT_NOR_SECBOOT        P1010RDB:P1010RDB_PB,36BIT,SECURE_BOOT                                                                                            -
+Active  powerpc     mpc85xx        -           freescale       p1010rdb            P1010RDB-PB_36BIT_SDCARD             P1010RDB:P1010RDB_PB,36BIT,SDCARD                                                                                                 -
+Active  powerpc     mpc85xx        -           freescale       p1010rdb            P1010RDB-PB_36BIT_SPIFLASH           P1010RDB:P1010RDB_PB,36BIT,SPIFLASH                                                                                               -
+Active  powerpc     mpc85xx        -           freescale       p1010rdb            P1010RDB-PB_36BIT_SPIFLASH_SECBOOT   P1010RDB:P1010RDB_PB,36BIT,SPIFLASH,SECURE_BOOT                                                                                   -
+Active  powerpc     mpc85xx        -           freescale       p1010rdb            P1010RDB-PB_NAND                     P1010RDB:P1010RDB_PB,NAND                                                                                                         -
+Active  powerpc     mpc85xx        -           freescale       p1010rdb            P1010RDB-PB_NAND_SECBOOT             P1010RDB:P1010RDB_PB,NAND_SECBOOT,SECURE_BOOT                                                                                     -
+Active  powerpc     mpc85xx        -           freescale       p1010rdb            P1010RDB-PB_NOR                      P1010RDB:P1010RDB_PB                                                                                                              -
+Active  powerpc     mpc85xx        -           freescale       p1010rdb            P1010RDB-PB_NOR_SECBOOT              P1010RDB:P1010RDB_PB,SECURE_BOOT                                                                                                  -
+Active  powerpc     mpc85xx        -           freescale       p1010rdb            P1010RDB-PB_SDCARD                   P1010RDB:P1010RDB_PB,SDCARD                                                                                                       -
+Active  powerpc     mpc85xx        -           freescale       p1010rdb            P1010RDB-PB_SPIFLASH                 P1010RDB:P1010RDB_PB,SPIFLASH                                                                                                     -
+Active  powerpc     mpc85xx        -           freescale       p1010rdb            P1010RDB-PB_SPIFLASH_SECBOOT         P1010RDB:P1010RDB_PB,SPIFLASH,SECURE_BOOT                                                                                         -
 Active  powerpc     mpc85xx        -           freescale       p1022ds             P1022DS                              -                                                                                                                                 Timur Tabi <timur@freescale.com>
 Active  powerpc     mpc85xx        -           freescale       p1022ds             P1022DS_36BIT                        P1022DS:36BIT                                                                                                                     Timur Tabi <timur@freescale.com>
 Active  powerpc     mpc85xx        -           freescale       p1022ds             P1022DS_36BIT_NAND                   P1022DS:36BIT,NAND                                                                                                                Timur Tabi <timur@freescale.com>
@@ -849,8 +847,8 @@ Active  powerpc     mpc85xx        -           freescale       p1022ds
 Active  powerpc     mpc85xx        -           freescale       p1022ds             P1022DS_NAND                         P1022DS:NAND                                                                                                                      Timur Tabi <timur@freescale.com>
 Active  powerpc     mpc85xx        -           freescale       p1022ds             P1022DS_SDCARD                       P1022DS:SDCARD                                                                                                                    Timur Tabi <timur@freescale.com>
 Active  powerpc     mpc85xx        -           freescale       p1022ds             P1022DS_SPIFLASH                     P1022DS:SPIFLASH                                                                                                                  Timur Tabi <timur@freescale.com>
-Active  powerpc     mpc85xx        -           freescale       p1023rdb            P1023RDB                             P1023RDB                                                                                                                          -
-Active  powerpc     mpc85xx        -           freescale       p1023rds            P1023RDS                             P1023RDS                                                                                                                          Roy Zang <tie-fei.zang@freescale.com>
+Active  powerpc     mpc85xx        -           freescale       p1023rdb            P1023RDB                             -                                                                                                                                 -
+Active  powerpc     mpc85xx        -           freescale       p1023rds            P1023RDS                             -                                                                                                                                 Roy Zang <tie-fei.zang@freescale.com>
 Active  powerpc     mpc85xx        -           freescale       p1023rds            P1023RDS_NAND                        P1023RDS:NAND                                                                                                                     Roy Zang <tie-fei.zang@freescale.com>
 Active  powerpc     mpc85xx        -           freescale       p1_p2_rdb           P1011RDB                             P1_P2_RDB:P1011RDB                                                                                                                -
 Active  powerpc     mpc85xx        -           freescale       p1_p2_rdb           P1011RDB_36BIT                       P1_P2_RDB:P1011RDB,36BIT                                                                                                          -
@@ -935,32 +933,53 @@ Active  powerpc     mpc85xx        -           freescale       p2020ds
 Active  powerpc     mpc85xx        -           freescale       p2020ds             P2020DS_SDCARD                       P2020DS:SDCARD                                                                                                                    -
 Active  powerpc     mpc85xx        -           freescale       p2020ds             P2020DS_SPIFLASH                     P2020DS:SPIFLASH                                                                                                                  -
 Active  powerpc     mpc85xx        -           freescale       p2041rdb            P2041RDB                             -                                                                                                                                 -
-Active  powerpc     mpc85xx        -           freescale       p2041rdb            P2041RDB_NAND                        P2041RDB:RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF80000                                                                                -
-Active  powerpc     mpc85xx        -           freescale       p2041rdb            P2041RDB_SDCARD                      P2041RDB:RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF80000                                                                              -
+Active  powerpc     mpc85xx        -           freescale       p2041rdb            P2041RDB_NAND                        P2041RDB:RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF40000                                                                                -
+Active  powerpc     mpc85xx        -           freescale       p2041rdb            P2041RDB_SDCARD                      P2041RDB:RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF40000                                                                              -
 Active  powerpc     mpc85xx        -           freescale       p2041rdb            P2041RDB_SECURE_BOOT                 P2041RDB:SECURE_BOOT                                                                                                              -
-Active  powerpc     mpc85xx        -           freescale       p2041rdb            P2041RDB_SPIFLASH                    P2041RDB:RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF80000                                                                            -
-Active  powerpc     mpc85xx        -           freescale       p2041rdb            P2041RDB_SRIO_PCIE_BOOT              P2041RDB:SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF80000                                                                            -
+Active  powerpc     mpc85xx        -           freescale       p2041rdb            P2041RDB_SPIFLASH                    P2041RDB:RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000                                                                            -
+Active  powerpc     mpc85xx        -           freescale       p2041rdb            P2041RDB_SRIO_PCIE_BOOT              P2041RDB:SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF40000                                                                            -
+Active  powerpc     mpc85xx        -           freescale       t1040qds            T1040QDS                             T1040QDS:PPC_T1040                                                                                                                Poonam Aggrwal <poonam.aggrwal@freescale.com>
+Active  powerpc     mpc85xx        -           freescale       t104xrdb            T1040RDB                             T1040RDB:PPC_T1040                                                                                                                Poonam Aggrwal  <poonam.aggrwal@freescale.com>
+Active  powerpc     mpc85xx        -           freescale       t104xrdb            T1042RDB_PI                          T1042RDB_PI:PPC_T1042                                                                                                             Poonam Aggrwal  <poonam.aggrwal@freescale.com>
+Active  powerpc     mpc85xx        -           freescale       t208xqds            T2080QDS                             T208xQDS:PPC_T2080                                                                                                                -
+Active  powerpc     mpc85xx        -           freescale       t208xqds            T2080QDS_NAND                        T208xQDS:PPC_T2080,RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF40000                                                                      -
+Active  powerpc     mpc85xx        -           freescale       t208xqds            T2080QDS_SDCARD                      T208xQDS:PPC_T2080,RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF40000                                                                    -
+Active  powerpc     mpc85xx        -           freescale       t208xqds            T2080QDS_SPIFLASH                    T208xQDS:PPC_T2080,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000                                                                  -
+Active  powerpc     mpc85xx        -           freescale       t208xqds            T2080QDS_SRIO_PCIE_BOOT              T208xQDS:PPC_T2080,SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF40000                                                                  -
+Active  powerpc     mpc85xx        -           freescale       t208xqds            T2081QDS                             T208xQDS:PPC_T2081                                                                                                                -
+Active  powerpc     mpc85xx        -           freescale       t208xqds            T2081QDS_NAND                        T208xQDS:PPC_T2081,RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF40000                                                                      -
+Active  powerpc     mpc85xx        -           freescale       t208xqds            T2081QDS_SDCARD                      T208xQDS:PPC_T2081,RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF40000                                                                    -
+Active  powerpc     mpc85xx        -           freescale       t208xqds            T2081QDS_SPIFLASH                    T208xQDS:PPC_T2081,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000                                                                  -
+Active  powerpc     mpc85xx        -           freescale       t208xqds            T2081QDS_SRIO_PCIE_BOOT              T208xQDS:PPC_T2081,SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF40000                                                                  -
+Active  powerpc     mpc85xx        -           freescale       t208xrdb            T2080RDB                             T208xRDB:PPC_T2080                                                                                                                -
+Active  powerpc     mpc85xx        -           freescale       t208xrdb            T2080RDB_NAND                        T208xRDB:PPC_T2080,RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF40000                                                                      -
+Active  powerpc     mpc85xx        -           freescale       t208xrdb            T2080RDB_SDCARD                      T208xRDB:PPC_T2080,RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF40000                                                                    -
+Active  powerpc     mpc85xx        -           freescale       t208xrdb            T2080RDB_SPIFLASH                    T208xRDB:PPC_T2080,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000                                                                  -
+Active  powerpc     mpc85xx        -           freescale       t208xrdb            T2080RDB_SRIO_PCIE_BOOT              T208xRDB:PPC_T2080,SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF40000                                                                  -
 Active  powerpc     mpc85xx        -           freescale       t4qds               T4160QDS                             T4240QDS:PPC_T4160                                                                                                                -
-Active  powerpc     mpc85xx        -           freescale       t4qds               T4160QDS_SDCARD                      T4240QDS:PPC_T4160,RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF80000                                                                    -
-Active  powerpc     mpc85xx        -           freescale       t4qds               T4160QDS_SPIFLASH                    T4240QDS:PPC_T4160,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF80000                                                                  -
+Active  powerpc     mpc85xx        -           freescale       t4qds               T4160QDS_SDCARD                      T4240QDS:PPC_T4160,RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF40000                                                                    -
+Active  powerpc     mpc85xx        -           freescale       t4qds               T4160QDS_SPIFLASH                    T4240QDS:PPC_T4160,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000                                                                  -
 Active  powerpc     mpc85xx        -           freescale       t4qds               T4240EMU                             T4240EMU:PPC_T4240                                                                                                                York Sun <yorksun@freescale.com>
 Active  powerpc     mpc85xx        -           freescale       t4qds               T4240QDS                             T4240QDS:PPC_T4240                                                                                                                -
-Active  powerpc     mpc85xx        -           freescale       t4qds               T4240QDS_SDCARD                      T4240QDS:PPC_T4240,RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF80000                                                                    -
-Active  powerpc     mpc85xx        -           freescale       t4qds               T4240QDS_SPIFLASH                    T4240QDS:PPC_T4240,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF80000                                                                  -
-Active  powerpc     mpc85xx        -           freescale       t4qds               T4240QDS_SRIO_PCIE_BOOT              T4240QDS:PPC_T4240,SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF80000                                                                  -
+Active  powerpc     mpc85xx        -           freescale       t4qds               T4240QDS_NAND                        T4240QDS:PPC_T4240,RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF40000                                                                      -
+Active  powerpc     mpc85xx        -           freescale       t4qds               T4240QDS_SDCARD                      T4240QDS:PPC_T4240,RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF40000                                                                    -
+Active  powerpc     mpc85xx        -           freescale       t4qds               T4240QDS_SPIFLASH                    T4240QDS:PPC_T4240,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000                                                                  -
+Active  powerpc     mpc85xx        -           freescale       t4qds               T4240QDS_SRIO_PCIE_BOOT              T4240QDS:PPC_T4240,SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF40000                                                                  -
 Active  powerpc     mpc85xx        -           gdsys           p1022               controlcenterd_36BIT_SDCARD          controlcenterd:36BIT,SDCARD                                                                                                       Dirk Eibach <eibach@gdsys.de>
 Active  powerpc     mpc85xx        -           gdsys           p1022               controlcenterd_36BIT_SDCARD_DEVELOP  controlcenterd:36BIT,SDCARD,DEVELOP                                                                                               Dirk Eibach <eibach@gdsys.de>
 Active  powerpc     mpc85xx        -           gdsys           p1022               controlcenterd_TRAILBLAZER           controlcenterd:TRAILBLAZER,SPIFLASH                                                                                               Dirk Eibach <eibach@gdsys.de>
 Active  powerpc     mpc85xx        -           gdsys           p1022               controlcenterd_TRAILBLAZER_DEVELOP   controlcenterd:TRAILBLAZER,SPIFLASH,DEVELOP                                                                                       Dirk Eibach <eibach@gdsys.de>
+Active  powerpc     mpc85xx        -           keymile         kmp204x             kmcoge4                              kmp204x:KMCOGE4                                                                                                                   Valentin Longchamp <valentin.longchamp@keymile.com>
+Active  powerpc     mpc85xx        -           keymile         kmp204x             kmlion1                              kmp204x:KMLION1                                                                                                                   Valentin Longchamp <valentin.longchamp@keymile.com>
 Active  powerpc     mpc85xx        -           stx             stxgp3              stxgp3                               -                                                                                                                                 Dan Malek <dan@embeddedalley.com>
-Active  powerpc     mpc85xx        -           stx             stxssa              stxssa                               stxssa                                                                                                                            Dan Malek <dan@embeddedalley.com>
+Active  powerpc     mpc85xx        -           stx             stxssa              stxssa                               -                                                                                                                                 Dan Malek <dan@embeddedalley.com>
 Active  powerpc     mpc85xx        -           stx             stxssa              stxssa_4M                            stxssa:STXSSA_4M                                                                                                                  Dan Malek <dan@embeddedalley.com>
 Active  powerpc     mpc85xx        -           xes             -                   xpedite520x                          -                                                                                                                                 -
 Active  powerpc     mpc85xx        -           xes             -                   xpedite537x                          -                                                                                                                                 -
 Active  powerpc     mpc85xx        -           xes             -                   xpedite550x                          -                                                                                                                                 -
 Active  powerpc     mpc86xx        -           -               -                   sbc8641d                             -                                                                                                                                 Paul Gortmaker <paul.gortmaker@windriver.com>
 Active  powerpc     mpc86xx        -           freescale       mpc8610hpcd         MPC8610HPCD                          -                                                                                                                                 -
-Active  powerpc     mpc86xx        -           freescale       mpc8641hpcn         MPC8641HPCN                          MPC8641HPCN                                                                                                                       Kumar Gala <kumar.gala@freescale.com>
+Active  powerpc     mpc86xx        -           freescale       mpc8641hpcn         MPC8641HPCN                          -                                                                                                                                 Kumar Gala <kumar.gala@freescale.com>
 Active  powerpc     mpc86xx        -           freescale       mpc8641hpcn         MPC8641HPCN_36BIT                    MPC8641HPCN:PHYS_64BIT                                                                                                            Kumar Gala <kumar.gala@freescale.com>
 Active  powerpc     mpc86xx        -           xes             -                   xpedite517x                          -                                                                                                                                 -
 Active  powerpc     mpc8xx         -           -               -                   hermes                               -                                                                                                                                 Wolfgang Denk <wd@denx.de>
@@ -970,10 +989,6 @@ Active  powerpc     mpc8xx         -           -               -
 Active  powerpc     mpc8xx         -           -               -                   spc1920                              -                                                                                                                                 -
 Active  powerpc     mpc8xx         -           -               -                   svm_sc8xx                            -                                                                                                                                 John Zhan <zhanz@sinovee.com>
 Active  powerpc     mpc8xx         -           -               -                   v37                                  -                                                                                                                                 -
-Active  powerpc     mpc8xx         -           -               adder               Adder                                -                                                                                                                                 Yuli Barcohen <yuli@arabellasw.com>
-Active  powerpc     mpc8xx         -           -               adder               Adder87x                             Adder                                                                                                                             Yuli Barcohen <yuli@arabellasw.com>
-Active  powerpc     mpc8xx         -           -               adder               AdderII                              Adder:MPC852T                                                                                                                     Yuli Barcohen <yuli@arabellasw.com>
-Active  powerpc     mpc8xx         -           -               adder               AdderUSB                             Adder                                                                                                                             Yuli Barcohen <yuli@arabellasw.com>
 Active  powerpc     mpc8xx         -           -               cogent              cogent_mpc8xx                        -                                                                                                                                 Murray Jensen <Murray.Jensen@csiro.au>
 Active  powerpc     mpc8xx         -           -               esteem192e          ESTEEM192E                           -                                                                                                                                 Conn Clark <clark@esteem.com>
 Active  powerpc     mpc8xx         -           -               fads                MPC86xADS                            -                                                                                                                                 -
@@ -992,7 +1007,7 @@ Active  powerpc     mpc8xx         -           -               ivm
 Active  powerpc     mpc8xx         -           -               ivm                 IVMS8_256                            IVMS8:IVMS8_64M                                                                                                                   Wolfgang Denk <wd@denx.de>
 Active  powerpc     mpc8xx         -           -               netphone            NETPHONE                             NETPHONE:NETPHONE_VERSION=1                                                                                                       -
 Active  powerpc     mpc8xx         -           -               netphone            NETPHONE_V2                          NETPHONE:NETPHONE_VERSION=2                                                                                                       -
-Active  powerpc     mpc8xx         -           -               netta               NETTA                                NETTA                                                                                                                             -
+Active  powerpc     mpc8xx         -           -               netta               NETTA                                -                                                                                                                                 -
 Active  powerpc     mpc8xx         -           -               netta               NETTA_6412                           NETTA:NETTA_6412=1                                                                                                                -
 Active  powerpc     mpc8xx         -           -               netta               NETTA_6412_SWAPHOOK                  NETTA:NETTA_6412=1,NETTA_SWAPHOOK=1                                                                                               -
 Active  powerpc     mpc8xx         -           -               netta               NETTA_ISDN                           NETTA:NETTA_ISDN=1                                                                                                                -
@@ -1006,7 +1021,7 @@ Active  powerpc     mpc8xx         -           -               netvia
 Active  powerpc     mpc8xx         -           -               netvia              NETVIA_V2                            NETVIA:NETVIA_VERSION=2                                                                                                           Pantelis Antoniou <panto@intracom.gr>
 Active  powerpc     mpc8xx         -           -               r360mpi             R360MPI                              -                                                                                                                                 Wolfgang Denk <wd@denx.de>
 Active  powerpc     mpc8xx         -           -               rbc823              RBC823                               -                                                                                                                                 -
-Active  powerpc     mpc8xx         -           -               RPXlite_dw          RPXlite_DW                           RPXlite_DW                                                                                                                        -
+Active  powerpc     mpc8xx         -           -               RPXlite_dw          RPXlite_DW                           -                                                                                                                                 -
 Active  powerpc     mpc8xx         -           -               RPXlite_dw          RPXlite_DW_64                        RPXlite_DW:RPXlite_64MHz                                                                                                          -
 Active  powerpc     mpc8xx         -           -               RPXlite_dw          RPXlite_DW_64_LCD                    RPXlite_DW:RPXlite_64MHz,LCD,NEC_NL6448BC20                                                                                       -
 Active  powerpc     mpc8xx         -           -               RPXlite_dw          RPXlite_DW_LCD                       RPXlite_DW:LCD,NEC_NL6448BC20                                                                                                     -
@@ -1066,7 +1081,6 @@ Active  powerpc     ppc4xx         -           -               w7o
 Active  powerpc     ppc4xx         -           -               w7o                 W7OLMG                               -                                                                                                                                 Erik Theisen <etheisen@mindspring.com>
 Active  powerpc     ppc4xx         -           amcc            -                   acadia                               -                                                                                                                                 Stefan Roese <sr@denx.de>
 Active  powerpc     ppc4xx         -           amcc            -                   bamboo                               -                                                                                                                                 Stefan Roese <sr@denx.de>
-Active  powerpc     ppc4xx         -           amcc            -                   bluestone                            -                                                                                                                                 Tirumala Marri <tmarri@apm.com>
 Active  powerpc     ppc4xx         -           amcc            -                   bubinga                              -                                                                                                                                 -
 Active  powerpc     ppc4xx         -           amcc            -                   ebony                                -                                                                                                                                 Stefan Roese <sr@denx.de>
 Active  powerpc     ppc4xx         -           amcc            -                   katmai                               -                                                                                                                                 Stefan Roese <sr@denx.de>
@@ -1077,22 +1091,14 @@ Active  powerpc     ppc4xx         -           amcc            -
 Active  powerpc     ppc4xx         -           amcc            -                   taihu                                -                                                                                                                                 John Otken <jotken@softadvances.com>
 Active  powerpc     ppc4xx         -           amcc            -                   taishan                              -                                                                                                                                 Stefan Roese <sr@denx.de>
 Active  powerpc     ppc4xx         -           amcc            -                   yucca                                -                                                                                                                                 -
-Active  powerpc     ppc4xx         -           amcc            acadia              acadia_nand                          acadia:NAND_U_BOOT,SYS_TEXT_BASE=0x01000000                                                                                       Stefan Roese <sr@denx.de>
-Active  powerpc     ppc4xx         -           amcc            bamboo              bamboo_nand                          bamboo:NAND_U_BOOT,SYS_TEXT_BASE=0x01000000                                                                                       Stefan Roese <sr@denx.de>
 Active  powerpc     ppc4xx         -           amcc            canyonlands         arches                               canyonlands:ARCHES                                                                                                                Stefan Roese <sr@denx.de>
 Active  powerpc     ppc4xx         -           amcc            canyonlands         canyonlands                          canyonlands:CANYONLANDS                                                                                                           Stefan Roese <sr@denx.de>
-Active  powerpc     ppc4xx         -           amcc            canyonlands         canyonlands_nand                     canyonlands:CANYONLANDS,NAND_U_BOOT,SYS_TEXT_BASE=0x01000000                                                                      Stefan Roese <sr@denx.de>
 Active  powerpc     ppc4xx         -           amcc            canyonlands         glacier                              canyonlands:GLACIER                                                                                                               Stefan Roese <sr@denx.de>
-Active  powerpc     ppc4xx         -           amcc            canyonlands         glacier_nand                         canyonlands:GLACIER,NAND_U_BOOT,SYS_TEXT_BASE=0x01000000                                                                          Stefan Roese <sr@denx.de>
 Active  powerpc     ppc4xx         -           amcc            kilauea             haleakala                            kilauea:HALEAKALA                                                                                                                 Stefan Roese <sr@denx.de>
-Active  powerpc     ppc4xx         -           amcc            kilauea             haleakala_nand                       kilauea:NAND_U_BOOT,SYS_TEXT_BASE=0x01000000                                                                                      Stefan Roese <sr@denx.de>
 Active  powerpc     ppc4xx         -           amcc            kilauea             kilauea                              kilauea:KILAUEA                                                                                                                   Stefan Roese <sr@denx.de>
-Active  powerpc     ppc4xx         -           amcc            kilauea             kilauea_nand                         kilauea:NAND_U_BOOT,SYS_TEXT_BASE=0x01000000                                                                                      Stefan Roese <sr@denx.de>
 Active  powerpc     ppc4xx         -           amcc            sequoia             rainier                              sequoia:RAINIER                                                                                                                   Stefan Roese <sr@denx.de>
-Active  powerpc     ppc4xx         -           amcc            sequoia             rainier_nand                         sequoia:RAINIER,NAND_U_BOOT,SYS_TEXT_BASE=0x01000000                                                                              Stefan Roese <sr@denx.de>
 Active  powerpc     ppc4xx         -           amcc            sequoia             rainier_ramboot                      sequoia:RAINIER,SYS_RAMBOOT,SYS_TEXT_BASE=0x01000000,SYS_LDSCRIPT=board/amcc/sequoia/u-boot-ram.lds                               Stefan Roese <sr@denx.de>
 Active  powerpc     ppc4xx         -           amcc            sequoia             sequoia                              sequoia:SEQUOIA                                                                                                                   Stefan Roese <sr@denx.de>
-Active  powerpc     ppc4xx         -           amcc            sequoia             sequoia_nand                         sequoia:SEQUOIA,NAND_U_BOOT,SYS_TEXT_BASE=0x01000000                                                                              Stefan Roese <sr@denx.de>
 Active  powerpc     ppc4xx         -           amcc            sequoia             sequoia_ramboot                      sequoia:SEQUOIA,SYS_RAMBOOT,SYS_TEXT_BASE=0x01000000,SYS_LDSCRIPT=board/amcc/sequoia/u-boot-ram.lds                               Stefan Roese <sr@denx.de>
 Active  powerpc     ppc4xx         -           amcc            walnut              sycamore                             walnut                                                                                                                            Stefan Roese <sr@denx.de>
 Active  powerpc     ppc4xx         -           amcc            walnut              walnut                               -                                                                                                                                 Stefan Roese <sr@denx.de>
@@ -1102,7 +1108,6 @@ Active  powerpc     ppc4xx         -           avnet           fx12mm
 Active  powerpc     ppc4xx         -           avnet           fx12mm              fx12mm_flash                         fx12mm:SYS_TEXT_BASE=0xF7F60000,RESET_VECTOR_ADDRESS=0xF7FFFFFC,INIT_TLB=board/xilinx/ppc405-generic/init.o                       Georg Schardt <schardt@team-ctech.de>
 Active  powerpc     ppc4xx         -           avnet           v5fx30teval         v5fx30teval                          v5fx30teval:SYS_TEXT_BASE=0x04000000,RESET_VECTOR_ADDRESS=0x04100000,BOOT_FROM_XMD=1,INIT_TLB=board/xilinx/ppc440-generic/init.o  Ricardo Ribalda <ricardo.ribalda@uam.es>
 Active  powerpc     ppc4xx         -           avnet           v5fx30teval         v5fx30teval_flash                    v5fx30teval:SYS_TEXT_BASE=0xF7F60000,RESET_VECTOR_ADDRESS=0xF7FFFFFC,INIT_TLB=board/xilinx/ppc440-generic/init.o                  Ricardo Ribalda <ricardo.ribalda@uam.es>
-Active  powerpc     ppc4xx         -           cray            L1                  CRAYL1                               -                                                                                                                                 David Updegraff <dave@cray.com>
 Active  powerpc     ppc4xx         -           dave            PPChameleonEVB      CATcenter                            CATcenter:PPCHAMELEON_MODULE_MODEL=1                                                                                              -
 Active  powerpc     ppc4xx         -           dave            PPChameleonEVB      CATcenter_25                         CATcenter:PPCHAMELEON_MODULE_MODEL=1,PPCHAMELEON_CLK_25                                                                           -
 Active  powerpc     ppc4xx         -           dave            PPChameleonEVB      CATcenter_33                         CATcenter:PPCHAMELEON_MODULE_MODEL=1,PPCHAMELEON_CLK_33                                                                           -
@@ -1152,8 +1157,6 @@ Active  powerpc     ppc4xx         -           mpl             mip405
 Active  powerpc     ppc4xx         -           mpl             pip405              PIP405                               -                                                                                                                                 Denis Peter <d.peter@mpl.ch>
 Active  powerpc     ppc4xx         -           prodrive        -                   alpr                                 -                                                                                                                                 Stefan Roese <sr@denx.de>
 Active  powerpc     ppc4xx         -           prodrive        -                   p3p440                               -                                                                                                                                 Stefan Roese <sr@denx.de>
-Active  powerpc     ppc4xx         -           sandburst       karef               KAREF                                -                                                                                                                                 Travis Sawyer (travis.sawyer@sandburst.com>
-Active  powerpc     ppc4xx         -           sandburst       metrobox            METROBOX                             -                                                                                                                                 Travis Sawyer (travis.sawyer@sandburst.com>
 Active  powerpc     ppc4xx         -           xes             -                   xpedite1000                          -                                                                                                                                 Peter Tyser <ptyser@xes-inc.com>
 Active  powerpc     ppc4xx         -           xilinx          ml507               ml507                                ml507:SYS_TEXT_BASE=0x04000000,RESET_VECTOR_ADDRESS=0x04100000,BOOT_FROM_XMD=1,INIT_TLB=board/xilinx/ppc440-generic/init.o        Ricardo Ribalda <ricardo.ribalda@uam.es>
 Active  powerpc     ppc4xx         -           xilinx          ml507               ml507_flash                          ml507:SYS_TEXT_BASE=0xF7F60000,RESET_VECTOR_ADDRESS=0xF7FFFFFC,INIT_TLB=board/xilinx/ppc440-generic/init.o                        Ricardo Ribalda <ricardo.ribalda@uam.es>
@@ -1179,6 +1182,7 @@ Active  sh          sh4            -           renesas         r0p7734
 Active  sh          sh4            -           renesas         r2dplus             r2dplus                              -                                                                                                                                 Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>:Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
 Active  sh          sh4            -           renesas         r7780mp             r7780mp                              -                                                                                                                                 Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>:Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
 Active  sh          sh4            -           renesas         sh7752evb           sh7752evb                            -                                                                                                                                 -
+Active  sh          sh4            -           renesas         sh7753evb           sh7753evb                            -                                                                                                                                 -
 Active  sh          sh4            -           renesas         sh7757lcr           sh7757lcr                            -                                                                                                                                 -
 Active  sh          sh4            -           renesas         sh7763rdp           sh7763rdp                            -                                                                                                                                 Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>:Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
 Active  sh          sh4            -           renesas         sh7785lcr           sh7785lcr                            -                                                                                                                                 -
@@ -1189,11 +1193,57 @@ Active  sparc       leon3          -           gaisler         -
 Active  sparc       leon3          -           gaisler         -                   gr_xc3s_1500                         -                                                                                                                                 -
 Active  sparc       leon3          -           gaisler         -                   grsim                                -                                                                                                                                 -
 Active  x86         x86            coreboot    chromebook-x86  coreboot            coreboot-x86                         coreboot:SYS_TEXT_BASE=0x01110000                                                                                                 -
+# The following were moved to "Orphan" in March, 2014
+Orphan  blackfin    blackfin       -           -               -                   cm-bf527                             -                                                                                                                                 Bluetechnix Tinyboards <bluetechnix@blackfin.uclinux.org>
+Orphan  blackfin    blackfin       -           -               -                   cm-bf533                             -                                                                                                                                 Bluetechnix Tinyboards <bluetechnix@blackfin.uclinux.org>
+Orphan  blackfin    blackfin       -           -               -                   cm-bf537e                            -                                                                                                                                 Bluetechnix Tinyboards <bluetechnix@blackfin.uclinux.org>
+Orphan  blackfin    blackfin       -           -               -                   cm-bf537u                            -                                                                                                                                 Bluetechnix Tinyboards <bluetechnix@blackfin.uclinux.org>
+Orphan  blackfin    blackfin       -           -               -                   cm-bf548                             -                                                                                                                                 Bluetechnix Tinyboards <bluetechnix@blackfin.uclinux.org>
+Orphan  blackfin    blackfin       -           -               -                   cm-bf561                             -                                                                                                                                 Bluetechnix Tinyboards <bluetechnix@blackfin.uclinux.org>
+Orphan  blackfin    blackfin       -           -               -                   tcm-bf518                            -                                                                                                                                 Bluetechnix Tinyboards <bluetechnix@blackfin.uclinux.org>
+Orphan  blackfin    blackfin       -           -               -                   tcm-bf537                            -                                                                                                                                 Bluetechnix Tinyboards <bluetechnix@blackfin.uclinux.org>
+Orphan  powerpc     mpc5xxx        -           matrix_vision   mvbc_p              MVBC_P                               MVBC_P:MVBC_P                                                                                                                     Andre Schwarz <andre.schwarz@matrix-vision.de>
+Orphan  powerpc     mpc5xxx        -           matrix_vision   mvsmr               MVSMR                                -                                                                                                                                 Andre Schwarz <andre.schwarz@matrix-vision.de>
+Orphan  powerpc     mpc824x        -           -               hidden_dragon       HIDDEN_DRAGON                        -                                                                                                                                 Yusdi Santoso <yusdi_santoso@adaptec.com>
+Orphan  powerpc     mpc824x        -           etin            -                   debris                               -                                                                                                                                 Sangmoon Kim <dogoil@etinsys.com>
+Orphan  powerpc     mpc824x        -           etin            -                   kvme080                              -                                                                                                                                 Sangmoon Kim <dogoil@etinsys.com>
+Orphan  powerpc     mpc8260        -           -               ep8248              ep8248                               -                                                                                                                                 Yuli Barcohen <yuli@arabellasw.com>
+Orphan  powerpc     mpc8260        -           -               ispan               ISPAN                                -                                                                                                                                 Yuli Barcohen <yuli@arabellasw.com>
+Orphan  powerpc     mpc8260        -           -               ispan               ISPAN_REVB                           ISPAN:SYS_REV_B                                                                                                                   Yuli Barcohen <yuli@arabellasw.com>
+Orphan  powerpc     mpc8260        -           -               rattler             Rattler                              -                                                                                                                                 Yuli Barcohen <yuli@arabellasw.com>
+Orphan  powerpc     mpc8260        -           -               rattler             Rattler8248                          Rattler:MPC8248                                                                                                                   Yuli Barcohen <yuli@arabellasw.com>
+Orphan  powerpc     mpc8260        -           -               zpc1900             ZPC1900                              -                                                                                                                                 Yuli Barcohen <yuli@arabellasw.com>
+Orphan  powerpc     mpc8260        -           freescale       mpc8260ads          MPC8260ADS                           MPC8260ADS:ADSTYPE=CONFIG_SYS_8260ADS                                                                                             Yuli Barcohen <yuli@arabellasw.com>
+Orphan  powerpc     mpc8260        -           freescale       mpc8260ads          MPC8260ADS_33MHz                     MPC8260ADS:ADSTYPE=CONFIG_SYS_8260ADS,8260_CLKIN=33000000                                                                         Yuli Barcohen <yuli@arabellasw.com>
+Orphan  powerpc     mpc8260        -           freescale       mpc8260ads          MPC8260ADS_33MHz_lowboot             MPC8260ADS:ADSTYPE=CONFIG_SYS_8260ADS,8260_CLKIN=33000000,SYS_TEXT_BASE=0xFF800000                                                Yuli Barcohen <yuli@arabellasw.com>
+Orphan  powerpc     mpc8260        -           freescale       mpc8260ads          MPC8260ADS_40MHz                     MPC8260ADS:ADSTYPE=CONFIG_SYS_8260ADS,8260_CLKIN=40000000                                                                         Yuli Barcohen <yuli@arabellasw.com>
+Orphan  powerpc     mpc8260        -           freescale       mpc8260ads          MPC8260ADS_40MHz_lowboot             MPC8260ADS:ADSTYPE=CONFIG_SYS_8260ADS,8260_CLKIN=40000000,SYS_TEXT_BASE=0xFF800000                                                Yuli Barcohen <yuli@arabellasw.com>
+Orphan  powerpc     mpc8260        -           freescale       mpc8260ads          MPC8260ADS_lowboot                   MPC8260ADS:ADSTYPE=CONFIG_SYS_8260ADS,SYS_TEXT_BASE=0xFF800000                                                                    Yuli Barcohen <yuli@arabellasw.com>
+Orphan  powerpc     mpc8260        -           freescale       mpc8260ads          MPC8272ADS                           MPC8260ADS:ADSTYPE=CONFIG_SYS_8272ADS                                                                                             Yuli Barcohen <yuli@arabellasw.com>
+Orphan  powerpc     mpc8260        -           freescale       mpc8260ads          MPC8272ADS_lowboot                   MPC8260ADS:ADSTYPE=CONFIG_SYS_8272ADS,SYS_TEXT_BASE=0xFF800000                                                                    Yuli Barcohen <yuli@arabellasw.com>
+Orphan  powerpc     mpc8260        -           freescale       mpc8260ads          PQ2FADS                              MPC8260ADS:ADSTYPE=CONFIG_SYS_PQ2FADS                                                                                             Yuli Barcohen <yuli@arabellasw.com>
+Orphan  powerpc     mpc8260        -           freescale       mpc8260ads          PQ2FADS-VR                           MPC8260ADS:ADSTYPE=CONFIG_SYS_PQ2FADS,8260_CLKIN=66000000                                                                         Yuli Barcohen <yuli@arabellasw.com>
+Orphan  powerpc     mpc8260        -           freescale       mpc8260ads          PQ2FADS-VR_lowboot                   MPC8260ADS:ADSTYPE=CONFIG_SYS_PQ2FADS,8260_CLKIN=66000000,SYS_TEXT_BASE=0xFF800000                                                Yuli Barcohen <yuli@arabellasw.com>
+Orphan  powerpc     mpc8260        -           freescale       mpc8260ads          PQ2FADS-ZU                           MPC8260ADS:ADSTYPE=CONFIG_SYS_PQ2FADS                                                                                             Yuli Barcohen <yuli@arabellasw.com>
+Orphan  powerpc     mpc8260        -           freescale       mpc8260ads          PQ2FADS-ZU_66MHz                     MPC8260ADS:ADSTYPE=CONFIG_SYS_PQ2FADS,8260_CLKIN=66000000                                                                         Yuli Barcohen <yuli@arabellasw.com>
+Orphan  powerpc     mpc8260        -           freescale       mpc8260ads          PQ2FADS-ZU_66MHz_lowboot             MPC8260ADS:ADSTYPE=CONFIG_SYS_PQ2FADS,8260_CLKIN=66000000,SYS_TEXT_BASE=0xFF800000                                                Yuli Barcohen <yuli@arabellasw.com>
+Orphan  powerpc     mpc8260        -           freescale       mpc8260ads          PQ2FADS-ZU_lowboot                   MPC8260ADS:ADSTYPE=CONFIG_SYS_PQ2FADS,SYS_TEXT_BASE=0xFF800000                                                                    Yuli Barcohen <yuli@arabellasw.com>
+Orphan  powerpc     mpc8260        -           freescale       mpc8260ads          PQ2FADS_lowboot                      MPC8260ADS:ADSTYPE=CONFIG_SYS_PQ2FADS,SYS_TEXT_BASE=0xFF800000                                                                    Yuli Barcohen <yuli@arabellasw.com>
+Orphan  powerpc     mpc83xx        -           freescale       mpc8360erdk         MPC8360ERDK                          -                                                                                                                                 Anton Vorontsov <avorontsov@ru.mvista.com>
+Orphan  powerpc     mpc83xx        -           freescale       mpc8360erdk         MPC8360ERDK_33                       MPC8360ERDK:CLKIN_33MHZ                                                                                                           Anton Vorontsov <avorontsov@ru.mvista.com>
+Orphan  powerpc     mpc83xx        -           matrix_vision   mergerbox           MERGERBOX                            -                                                                                                                                 Andre Schwarz <andre.schwarz@matrix-vision.de>
+Orphan  powerpc     mpc83xx        -           matrix_vision   mvblm7              MVBLM7                               -                                                                                                                                 Andre Schwarz <andre.schwarz@matrix-vision.de>
+Orphan  powerpc     mpc8xx         -           -               adder               Adder                                -                                                                                                                                 Yuli Barcohen <yuli@arabellasw.com>
+Orphan  powerpc     mpc8xx         -           -               adder               AdderII                              Adder:MPC852T                                                                                                                     Yuli Barcohen <yuli@arabellasw.com>
+Orphan  powerpc     ppc4xx         -           amcc            -                   bluestone                            -                                                                                                                                 Tirumala Marri <tmarri@apm.com>
+Orphan  powerpc     ppc4xx         -           cray            L1                  CRAYL1                               -                                                                                                                                 David Updegraff <dave@cray.com>
+Orphan  powerpc     ppc4xx         -           sandburst       karef               KAREF                                -                                                                                                                                 Travis Sawyer <travis.sawyer@sandburst.com>
+Orphan  powerpc     ppc4xx         -           sandburst       metrobox            METROBOX                             -                                                                                                                                 Travis Sawyer <travis.sawyer@sandburst.com>
+# The following were move to "Orphan" in September, 2013
 Orphan  arm         arm1136        mx31        -               imx31_phycore       imx31_phycore_eet                    imx31_phycore:IMX31_PHYCORE_EET                                                                                                   (resigned) Guennadi Liakhovetski <g.liakhovetski@gmx.de>
 Orphan  arm         arm1136        mx31        freescale       -                   mx31ads                              -                                                                                                                                 (resigned) Guennadi Liakhovetski <g.liakhovetski@gmx.de>
 Orphan  arm         pxa            -           -               -                   lubbock                              -                                                                                                                                 (dead address) Kyle Harris <kharris@nexus-tech.net>
-Orphan  powerpc     74xx_7xx       -           -               evb64260            EVB64260                             EVB64260                                                                                                                          -
-Orphan  powerpc     74xx_7xx       -           -               evb64260            EVB64260_750CX                       EVB64260                                                                                                                          Eran Man <eran@nbase.co.il>
+Orphan  powerpc     74xx_7xx       -           -               evb64260            EVB64260                             -                                                                                                                                 -
 Orphan  powerpc     mpc824x        -           -               mousse              MOUSSE                               -                                                                                                                                 -
 Orphan  powerpc     mpc8260        -           -               -                   rsdproto                             -                                                                                                                                 -
 Orphan  powerpc     mpc8260        -           -               rpxsuper            RPXsuper                             -                                                                                                                                 -
diff --git a/common/Makefile b/common/Makefile
index 288690bca5..cecd81a9a0 100644
--- a/common/Makefile
+++ b/common/Makefile
@@ -5,215 +5,223 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)libcommon.o
-
 # core
 ifndef CONFIG_SPL_BUILD
-COBJS-y += main.o
-COBJS-y += command.o
-COBJS-y += exports.o
-COBJS-y += hash.o
-COBJS-$(CONFIG_SYS_HUSH_PARSER) += hush.o
-COBJS-y += s_record.o
-COBJS-y += xyzModem.o
-COBJS-y += cmd_disk.o
+obj-y += main.o
+obj-y += command.o
+obj-y += exports.o
+obj-y += hash.o
+obj-$(CONFIG_SYS_HUSH_PARSER) += hush.o
+obj-y += s_record.o
+obj-y += xyzModem.o
+obj-y += cmd_disk.o
 
 # boards
-COBJS-$(CONFIG_SYS_GENERIC_BOARD) += board_f.o
-COBJS-$(CONFIG_SYS_GENERIC_BOARD) += board_r.o
+obj-$(CONFIG_SYS_GENERIC_BOARD) += board_f.o
+obj-$(CONFIG_SYS_GENERIC_BOARD) += board_r.o
 
 # core command
-COBJS-y += cmd_boot.o
-COBJS-$(CONFIG_CMD_BOOTM) += cmd_bootm.o
-COBJS-y += cmd_help.o
-COBJS-y += cmd_version.o
+obj-y += cmd_boot.o
+obj-$(CONFIG_CMD_BOOTM) += cmd_bootm.o
+obj-y += cmd_help.o
+obj-y += cmd_version.o
 
 # environment
-COBJS-y += env_attr.o
-COBJS-y += env_callback.o
-COBJS-y += env_flags.o
-COBJS-$(CONFIG_ENV_IS_IN_DATAFLASH) += env_dataflash.o
-COBJS-$(CONFIG_ENV_IS_IN_EEPROM) += env_eeprom.o
-XCOBJS-$(CONFIG_ENV_IS_EMBEDDED) += env_embedded.o
-COBJS-$(CONFIG_ENV_IS_IN_EEPROM) += env_embedded.o
-XCOBJS-$(CONFIG_ENV_IS_IN_FLASH) += env_embedded.o
-COBJS-$(CONFIG_ENV_IS_IN_NVRAM) += env_embedded.o
-COBJS-$(CONFIG_ENV_IS_IN_FLASH) += env_flash.o
-COBJS-$(CONFIG_ENV_IS_IN_MMC) += env_mmc.o
-COBJS-$(CONFIG_ENV_IS_IN_FAT) += env_fat.o
-COBJS-$(CONFIG_ENV_IS_IN_NAND) += env_nand.o
-COBJS-$(CONFIG_ENV_IS_IN_NVRAM) += env_nvram.o
-COBJS-$(CONFIG_ENV_IS_IN_ONENAND) += env_onenand.o
-COBJS-$(CONFIG_ENV_IS_IN_SPI_FLASH) += env_sf.o
-COBJS-$(CONFIG_ENV_IS_IN_REMOTE) += env_remote.o
-COBJS-$(CONFIG_ENV_IS_IN_UBI) += env_ubi.o
-COBJS-$(CONFIG_ENV_IS_NOWHERE) += env_nowhere.o
+obj-y += env_attr.o
+obj-y += env_callback.o
+obj-y += env_flags.o
+obj-$(CONFIG_ENV_IS_IN_DATAFLASH) += env_dataflash.o
+obj-$(CONFIG_ENV_IS_IN_EEPROM) += env_eeprom.o
+extra-$(CONFIG_ENV_IS_EMBEDDED) += env_embedded.o
+obj-$(CONFIG_ENV_IS_IN_EEPROM) += env_embedded.o
+extra-$(CONFIG_ENV_IS_IN_FLASH) += env_embedded.o
+obj-$(CONFIG_ENV_IS_IN_NVRAM) += env_embedded.o
+obj-$(CONFIG_ENV_IS_IN_FLASH) += env_flash.o
+obj-$(CONFIG_ENV_IS_IN_MMC) += env_mmc.o
+obj-$(CONFIG_ENV_IS_IN_FAT) += env_fat.o
+obj-$(CONFIG_ENV_IS_IN_NAND) += env_nand.o
+obj-$(CONFIG_ENV_IS_IN_NVRAM) += env_nvram.o
+obj-$(CONFIG_ENV_IS_IN_ONENAND) += env_onenand.o
+obj-$(CONFIG_ENV_IS_IN_SPI_FLASH) += env_sf.o
+obj-$(CONFIG_ENV_IS_IN_REMOTE) += env_remote.o
+obj-$(CONFIG_ENV_IS_IN_UBI) += env_ubi.o
+obj-$(CONFIG_ENV_IS_NOWHERE) += env_nowhere.o
 
 # command
-COBJS-$(CONFIG_CMD_AMBAPP) += cmd_ambapp.o
-COBJS-$(CONFIG_SOURCE) += cmd_source.o
-COBJS-$(CONFIG_CMD_SOURCE) += cmd_source.o
-COBJS-$(CONFIG_CMD_BDI) += cmd_bdinfo.o
-COBJS-$(CONFIG_CMD_BEDBUG) += bedbug.o cmd_bedbug.o
-COBJS-$(CONFIG_CMD_BMP) += cmd_bmp.o
-COBJS-$(CONFIG_CMD_BOOTMENU) += cmd_bootmenu.o
-COBJS-$(CONFIG_CMD_BOOTLDR) += cmd_bootldr.o
-COBJS-$(CONFIG_CMD_BOOTSTAGE) += cmd_bootstage.o
-COBJS-$(CONFIG_CMD_CACHE) += cmd_cache.o
-COBJS-$(CONFIG_CMD_CBFS) += cmd_cbfs.o
-COBJS-$(CONFIG_CMD_CONSOLE) += cmd_console.o
-COBJS-$(CONFIG_CMD_CPLBINFO) += cmd_cplbinfo.o
-COBJS-$(CONFIG_DATAFLASH_MMC_SELECT) += cmd_dataflash_mmc_mux.o
-COBJS-$(CONFIG_CMD_DATE) += cmd_date.o
-COBJS-$(CONFIG_CMD_SOUND) += cmd_sound.o
+obj-$(CONFIG_CMD_AMBAPP) += cmd_ambapp.o
+obj-$(CONFIG_SOURCE) += cmd_source.o
+obj-$(CONFIG_CMD_SOURCE) += cmd_source.o
+obj-$(CONFIG_CMD_BDI) += cmd_bdinfo.o
+obj-$(CONFIG_CMD_BEDBUG) += bedbug.o cmd_bedbug.o
+obj-$(CONFIG_CMD_BMP) += cmd_bmp.o
+obj-$(CONFIG_CMD_BOOTMENU) += cmd_bootmenu.o
+obj-$(CONFIG_CMD_BOOTLDR) += cmd_bootldr.o
+obj-$(CONFIG_CMD_BOOTSTAGE) += cmd_bootstage.o
+obj-$(CONFIG_CMD_CACHE) += cmd_cache.o
+obj-$(CONFIG_CMD_CBFS) += cmd_cbfs.o
+obj-$(CONFIG_CMD_CLK) += cmd_clk.o
+obj-$(CONFIG_CMD_CONSOLE) += cmd_console.o
+obj-$(CONFIG_CMD_CPLBINFO) += cmd_cplbinfo.o
+obj-$(CONFIG_DATAFLASH_MMC_SELECT) += cmd_dataflash_mmc_mux.o
+obj-$(CONFIG_CMD_DATE) += cmd_date.o
+obj-$(CONFIG_CMD_DEMO) += cmd_demo.o
+obj-$(CONFIG_CMD_SOUND) += cmd_sound.o
 ifdef CONFIG_4xx
-COBJS-$(CONFIG_CMD_SETGETDCR) += cmd_dcr.o
+obj-$(CONFIG_CMD_SETGETDCR) += cmd_dcr.o
 endif
 ifdef CONFIG_POST
-COBJS-$(CONFIG_CMD_DIAG) += cmd_diag.o
+obj-$(CONFIG_CMD_DIAG) += cmd_diag.o
 endif
-COBJS-$(CONFIG_CMD_DISPLAY) += cmd_display.o
-COBJS-$(CONFIG_CMD_DTT) += cmd_dtt.o
-COBJS-$(CONFIG_CMD_ECHO) += cmd_echo.o
-COBJS-$(CONFIG_ENV_IS_IN_EEPROM) += cmd_eeprom.o
-COBJS-$(CONFIG_CMD_EEPROM) += cmd_eeprom.o
-COBJS-$(CONFIG_CMD_ELF) += cmd_elf.o
-COBJS-$(CONFIG_SYS_HUSH_PARSER) += cmd_exit.o
-COBJS-$(CONFIG_CMD_EXT4) += cmd_ext4.o
-COBJS-$(CONFIG_CMD_EXT2) += cmd_ext2.o
-COBJS-$(CONFIG_CMD_FAT) += cmd_fat.o
-COBJS-$(CONFIG_CMD_FDC)$(CONFIG_CMD_FDOS) += cmd_fdc.o
-COBJS-$(CONFIG_OF_LIBFDT) += cmd_fdt.o fdt_support.o
-COBJS-$(CONFIG_CMD_FDOS) += cmd_fdos.o
-COBJS-$(CONFIG_CMD_FITUPD) += cmd_fitupd.o
-COBJS-$(CONFIG_CMD_FLASH) += cmd_flash.o
+obj-$(CONFIG_CMD_DISPLAY) += cmd_display.o
+obj-$(CONFIG_CMD_DTT) += cmd_dtt.o
+obj-$(CONFIG_CMD_ECHO) += cmd_echo.o
+obj-$(CONFIG_ENV_IS_IN_EEPROM) += cmd_eeprom.o
+obj-$(CONFIG_CMD_EEPROM) += cmd_eeprom.o
+obj-$(CONFIG_CMD_ELF) += cmd_elf.o
+obj-$(CONFIG_SYS_HUSH_PARSER) += cmd_exit.o
+obj-$(CONFIG_CMD_EXT4) += cmd_ext4.o
+obj-$(CONFIG_CMD_EXT2) += cmd_ext2.o
+obj-$(CONFIG_CMD_FAT) += cmd_fat.o
+obj-$(CONFIG_CMD_FDC) += cmd_fdc.o
+obj-$(CONFIG_OF_LIBFDT) += cmd_fdt.o fdt_support.o
+obj-$(CONFIG_CMD_FITUPD) += cmd_fitupd.o
+obj-$(CONFIG_CMD_FLASH) += cmd_flash.o
 ifdef CONFIG_FPGA
-COBJS-$(CONFIG_CMD_FPGA) += cmd_fpga.o
+obj-$(CONFIG_CMD_FPGA) += cmd_fpga.o
 endif
-COBJS-$(CONFIG_CMD_FPGAD) += cmd_fpgad.o
-COBJS-$(CONFIG_CMD_FS_GENERIC) += cmd_fs.o
-COBJS-$(CONFIG_CMD_FUSE) += cmd_fuse.o
-COBJS-$(CONFIG_CMD_GETTIME) += cmd_gettime.o
-COBJS-$(CONFIG_CMD_GPIO) += cmd_gpio.o
-COBJS-$(CONFIG_CMD_I2C) += cmd_i2c.o
-COBJS-$(CONFIG_CMD_HASH) += cmd_hash.o
-COBJS-$(CONFIG_CMD_IDE) += cmd_ide.o
-COBJS-$(CONFIG_CMD_IMMAP) += cmd_immap.o
-COBJS-$(CONFIG_CMD_INI) += cmd_ini.o
-COBJS-$(CONFIG_CMD_IRQ) += cmd_irq.o
-COBJS-$(CONFIG_CMD_ITEST) += cmd_itest.o
-COBJS-$(CONFIG_CMD_JFFS2) += cmd_jffs2.o
-COBJS-$(CONFIG_CMD_CRAMFS) += cmd_cramfs.o
-COBJS-$(CONFIG_CMD_LDRINFO) += cmd_ldrinfo.o
-COBJS-$(CONFIG_CMD_LED) += cmd_led.o
-COBJS-$(CONFIG_CMD_LICENSE) += cmd_license.o
-COBJS-y += cmd_load.o
-COBJS-$(CONFIG_LOGBUFFER) += cmd_log.o
-COBJS-$(CONFIG_ID_EEPROM) += cmd_mac.o
-COBJS-$(CONFIG_CMD_MD5SUM) += cmd_md5sum.o
-COBJS-$(CONFIG_CMD_MEMORY) += cmd_mem.o
-COBJS-$(CONFIG_CMD_IO) += cmd_io.o
-COBJS-$(CONFIG_CMD_MFSL) += cmd_mfsl.o
-COBJS-$(CONFIG_MII) += miiphyutil.o
-COBJS-$(CONFIG_CMD_MII) += miiphyutil.o
-COBJS-$(CONFIG_PHYLIB) += miiphyutil.o
-COBJS-$(CONFIG_CMD_MII) += cmd_mii.o
+obj-$(CONFIG_CMD_FPGAD) += cmd_fpgad.o
+obj-$(CONFIG_CMD_FS_GENERIC) += cmd_fs.o
+obj-$(CONFIG_CMD_FUSE) += cmd_fuse.o
+obj-$(CONFIG_CMD_GETTIME) += cmd_gettime.o
+obj-$(CONFIG_CMD_GPIO) += cmd_gpio.o
+obj-$(CONFIG_CMD_I2C) += cmd_i2c.o
+obj-$(CONFIG_CMD_HASH) += cmd_hash.o
+obj-$(CONFIG_CMD_IDE) += cmd_ide.o
+obj-$(CONFIG_CMD_IMMAP) += cmd_immap.o
+obj-$(CONFIG_CMD_INI) += cmd_ini.o
+obj-$(CONFIG_CMD_IRQ) += cmd_irq.o
+obj-$(CONFIG_CMD_ITEST) += cmd_itest.o
+obj-$(CONFIG_CMD_JFFS2) += cmd_jffs2.o
+obj-$(CONFIG_CMD_CRAMFS) += cmd_cramfs.o
+obj-$(CONFIG_CMD_LDRINFO) += cmd_ldrinfo.o
+obj-$(CONFIG_CMD_LED) += cmd_led.o
+obj-$(CONFIG_CMD_LICENSE) += cmd_license.o
+obj-y += cmd_load.o
+obj-$(CONFIG_LOGBUFFER) += cmd_log.o
+obj-$(CONFIG_ID_EEPROM) += cmd_mac.o
+obj-$(CONFIG_CMD_MD5SUM) += cmd_md5sum.o
+obj-$(CONFIG_CMD_MEMORY) += cmd_mem.o
+obj-$(CONFIG_CMD_IO) += cmd_io.o
+obj-$(CONFIG_CMD_MFSL) += cmd_mfsl.o
+obj-$(CONFIG_MII) += miiphyutil.o
+obj-$(CONFIG_CMD_MII) += miiphyutil.o
+obj-$(CONFIG_PHYLIB) += miiphyutil.o
+obj-$(CONFIG_CMD_MII) += cmd_mii.o
 ifdef CONFIG_PHYLIB
-COBJS-$(CONFIG_CMD_MII) += cmd_mdio.o
+obj-$(CONFIG_CMD_MII) += cmd_mdio.o
 endif
-COBJS-$(CONFIG_CMD_MISC) += cmd_misc.o
-COBJS-$(CONFIG_CMD_MMC) += cmd_mmc.o
-COBJS-$(CONFIG_CMD_MMC_SPI) += cmd_mmc_spi.o
-COBJS-$(CONFIG_MP) += cmd_mp.o
-COBJS-$(CONFIG_CMD_MTDPARTS) += cmd_mtdparts.o
-COBJS-$(CONFIG_CMD_NAND) += cmd_nand.o
-COBJS-$(CONFIG_CMD_NET) += cmd_net.o
-COBJS-$(CONFIG_CMD_ONENAND) += cmd_onenand.o
-COBJS-$(CONFIG_CMD_OTP) += cmd_otp.o
-COBJS-$(CONFIG_CMD_PART) += cmd_part.o
+obj-$(CONFIG_CMD_MISC) += cmd_misc.o
+obj-$(CONFIG_CMD_MMC) += cmd_mmc.o
+obj-$(CONFIG_CMD_MMC_SPI) += cmd_mmc_spi.o
+obj-$(CONFIG_MP) += cmd_mp.o
+obj-$(CONFIG_CMD_MTDPARTS) += cmd_mtdparts.o
+obj-$(CONFIG_CMD_NAND) += cmd_nand.o
+obj-$(CONFIG_CMD_NET) += cmd_net.o
+obj-$(CONFIG_CMD_ONENAND) += cmd_onenand.o
+obj-$(CONFIG_CMD_OTP) += cmd_otp.o
+obj-$(CONFIG_CMD_PART) += cmd_part.o
 ifdef CONFIG_PCI
-COBJS-$(CONFIG_CMD_PCI) += cmd_pci.o
+obj-$(CONFIG_CMD_PCI) += cmd_pci.o
+endif
+obj-y += cmd_pcmcia.o
+obj-$(CONFIG_CMD_PORTIO) += cmd_portio.o
+obj-$(CONFIG_CMD_PXE) += cmd_pxe.o
+obj-$(CONFIG_CMD_READ) += cmd_read.o
+obj-$(CONFIG_CMD_REGINFO) += cmd_reginfo.o
+obj-$(CONFIG_CMD_REISER) += cmd_reiser.o
+obj-$(CONFIG_SANDBOX) += cmd_sandbox.o
+obj-$(CONFIG_CMD_SATA) += cmd_sata.o
+obj-$(CONFIG_CMD_SF) += cmd_sf.o
+obj-$(CONFIG_CMD_SCSI) += cmd_scsi.o
+obj-$(CONFIG_CMD_SHA1SUM) += cmd_sha1sum.o
+obj-$(CONFIG_CMD_SETEXPR) += cmd_setexpr.o
+obj-$(CONFIG_CMD_SOFTSWITCH) += cmd_softswitch.o
+obj-$(CONFIG_CMD_SPI) += cmd_spi.o
+obj-$(CONFIG_CMD_SPIBOOTLDR) += cmd_spibootldr.o
+obj-$(CONFIG_CMD_STRINGS) += cmd_strings.o
+obj-$(CONFIG_CMD_TERMINAL) += cmd_terminal.o
+obj-$(CONFIG_CMD_TIME) += cmd_time.o
+obj-$(CONFIG_CMD_TRACE) += cmd_trace.o
+obj-$(CONFIG_SYS_HUSH_PARSER) += cmd_test.o
+obj-$(CONFIG_CMD_TPM) += cmd_tpm.o
+obj-$(CONFIG_CMD_TSI148) += cmd_tsi148.o
+obj-$(CONFIG_CMD_UBI) += cmd_ubi.o
+obj-$(CONFIG_CMD_UBIFS) += cmd_ubifs.o
+obj-$(CONFIG_CMD_UNIVERSE) += cmd_universe.o
+obj-$(CONFIG_CMD_UNZIP) += cmd_unzip.o
+ifdef CONFIG_LZMA
+obj-$(CONFIG_CMD_LZMADEC) += cmd_lzmadec.o
 endif
-COBJS-y += cmd_pcmcia.o
-COBJS-$(CONFIG_CMD_PORTIO) += cmd_portio.o
-COBJS-$(CONFIG_CMD_PXE) += cmd_pxe.o
-COBJS-$(CONFIG_CMD_READ) += cmd_read.o
-COBJS-$(CONFIG_CMD_REGINFO) += cmd_reginfo.o
-COBJS-$(CONFIG_CMD_REISER) += cmd_reiser.o
-COBJS-$(CONFIG_SANDBOX) += cmd_sandbox.o
-COBJS-$(CONFIG_CMD_SATA) += cmd_sata.o
-COBJS-$(CONFIG_CMD_SF) += cmd_sf.o
-COBJS-$(CONFIG_CMD_SCSI) += cmd_scsi.o
-COBJS-$(CONFIG_CMD_SHA1SUM) += cmd_sha1sum.o
-COBJS-$(CONFIG_CMD_SETEXPR) += cmd_setexpr.o
-COBJS-$(CONFIG_CMD_SOFTSWITCH) += cmd_softswitch.o
-COBJS-$(CONFIG_CMD_SPI) += cmd_spi.o
-COBJS-$(CONFIG_CMD_SPIBOOTLDR) += cmd_spibootldr.o
-COBJS-$(CONFIG_CMD_STRINGS) += cmd_strings.o
-COBJS-$(CONFIG_CMD_TERMINAL) += cmd_terminal.o
-COBJS-$(CONFIG_CMD_TIME) += cmd_time.o
-COBJS-$(CONFIG_CMD_TRACE) += cmd_trace.o
-COBJS-$(CONFIG_SYS_HUSH_PARSER) += cmd_test.o
-COBJS-$(CONFIG_CMD_TPM) += cmd_tpm.o
-COBJS-$(CONFIG_CMD_TSI148) += cmd_tsi148.o
-COBJS-$(CONFIG_CMD_UBI) += cmd_ubi.o
-COBJS-$(CONFIG_CMD_UBIFS) += cmd_ubifs.o
-COBJS-$(CONFIG_CMD_UNIVERSE) += cmd_universe.o
-COBJS-$(CONFIG_CMD_UNZIP) += cmd_unzip.o
 ifdef CONFIG_CMD_USB
-COBJS-y += cmd_usb.o
-COBJS-y += usb.o usb_hub.o
-COBJS-$(CONFIG_USB_STORAGE) += usb_storage.o
+obj-y += cmd_usb.o
+obj-y += usb.o usb_hub.o
+obj-$(CONFIG_USB_STORAGE) += usb_storage.o
 endif
-COBJS-$(CONFIG_CMD_USB_MASS_STORAGE) += cmd_usb_mass_storage.o
-COBJS-$(CONFIG_CMD_XIMG) += cmd_ximg.o
-COBJS-$(CONFIG_YAFFS2) += cmd_yaffs2.o
-COBJS-$(CONFIG_CMD_SPL) += cmd_spl.o
-COBJS-$(CONFIG_CMD_ZIP) += cmd_zip.o
-COBJS-$(CONFIG_CMD_ZFS) += cmd_zfs.o
+obj-$(CONFIG_CMD_USB_MASS_STORAGE) += cmd_usb_mass_storage.o
+obj-$(CONFIG_CMD_THOR_DOWNLOAD) += cmd_thordown.o
+obj-$(CONFIG_CMD_XIMG) += cmd_ximg.o
+obj-$(CONFIG_YAFFS2) += cmd_yaffs2.o
+obj-$(CONFIG_CMD_SPL) += cmd_spl.o
+obj-$(CONFIG_CMD_ZIP) += cmd_zip.o
+obj-$(CONFIG_CMD_ZFS) += cmd_zfs.o
 
 # others
-COBJS-$(CONFIG_BOOTSTAGE) += bootstage.o
-COBJS-$(CONFIG_CONSOLE_MUX) += iomux.o
-COBJS-y += flash.o
-COBJS-$(CONFIG_CMD_KGDB) += kgdb.o kgdb_stubs.o
-COBJS-$(CONFIG_I2C_EDID) += edid.o
-COBJS-$(CONFIG_KALLSYMS) += kallsyms.o
-COBJS-y += splash.o
-COBJS-$(CONFIG_LCD) += lcd.o
-COBJS-$(CONFIG_LYNXKDI) += lynxkdi.o
-COBJS-$(CONFIG_MENU) += menu.o
-COBJS-$(CONFIG_MODEM_SUPPORT) += modem.o
-COBJS-$(CONFIG_UPDATE_TFTP) += update.o
-COBJS-$(CONFIG_USB_KEYBOARD) += usb_kbd.o
-COBJS-$(CONFIG_CMD_DFU) += cmd_dfu.o
-COBJS-$(CONFIG_CMD_GPT) += cmd_gpt.o
+obj-$(CONFIG_BOOTSTAGE) += bootstage.o
+obj-$(CONFIG_CONSOLE_MUX) += iomux.o
+obj-y += flash.o
+obj-$(CONFIG_CMD_KGDB) += kgdb.o kgdb_stubs.o
+obj-$(CONFIG_I2C_EDID) += edid.o
+obj-$(CONFIG_KALLSYMS) += kallsyms.o
+obj-y += splash.o
+obj-$(CONFIG_LCD) += lcd.o
+obj-$(CONFIG_LYNXKDI) += lynxkdi.o
+obj-$(CONFIG_MENU) += menu.o
+obj-$(CONFIG_MODEM_SUPPORT) += modem.o
+obj-$(CONFIG_UPDATE_TFTP) += update.o
+obj-$(CONFIG_USB_KEYBOARD) += usb_kbd.o
+obj-$(CONFIG_CMD_DFU) += cmd_dfu.o
+obj-$(CONFIG_CMD_GPT) += cmd_gpt.o
 endif
 
 ifdef CONFIG_SPL_BUILD
-COBJS-$(CONFIG_ENV_IS_IN_FLASH) += env_flash.o
-COBJS-$(CONFIG_SPL_YMODEM_SUPPORT) += xyzModem.o
-COBJS-$(CONFIG_SPL_NET_SUPPORT) += miiphyutil.o
+obj-$(CONFIG_ENV_IS_IN_FLASH) += env_flash.o
+obj-$(CONFIG_SPL_YMODEM_SUPPORT) += xyzModem.o
+obj-$(CONFIG_SPL_NET_SUPPORT) += miiphyutil.o
 # environment
-COBJS-$(CONFIG_SPL_ENV_SUPPORT) += env_attr.o
-COBJS-$(CONFIG_SPL_ENV_SUPPORT) += env_flags.o
-COBJS-$(CONFIG_SPL_ENV_SUPPORT) += env_callback.o
+obj-$(CONFIG_SPL_ENV_SUPPORT) += env_attr.o
+obj-$(CONFIG_SPL_ENV_SUPPORT) += env_flags.o
+obj-$(CONFIG_SPL_ENV_SUPPORT) += env_callback.o
+ifdef CONFIG_SPL_USB_HOST_SUPPORT
+obj-$(CONFIG_SPL_USB_SUPPORT) += usb.o usb_hub.o
+obj-$(CONFIG_USB_STORAGE) += usb_storage.o
+endif
+ifdef CONFIG_SPL_SATA_SUPPORT
+obj-$(CONFIG_CMD_SCSI) += cmd_scsi.o
+endif
 ifneq ($(CONFIG_SPL_NET_SUPPORT),y)
-COBJS-$(CONFIG_ENV_IS_NOWHERE) += env_nowhere.o
-COBJS-$(CONFIG_ENV_IS_IN_MMC) += env_mmc.o
-COBJS-$(CONFIG_ENV_IS_IN_NAND) += env_nand.o
-COBJS-$(CONFIG_ENV_IS_IN_SPI_FLASH) += env_sf.o
-COBJS-$(CONFIG_ENV_IS_IN_FLASH) += env_flash.o
+obj-$(CONFIG_ENV_IS_NOWHERE) += env_nowhere.o
+obj-$(CONFIG_ENV_IS_IN_MMC) += env_mmc.o
+obj-$(CONFIG_ENV_IS_IN_NAND) += env_nand.o
+obj-$(CONFIG_ENV_IS_IN_SPI_FLASH) += env_sf.o
+obj-$(CONFIG_ENV_IS_IN_FLASH) += env_flash.o
 else
-COBJS-y += env_nowhere.o
+obj-y += env_nowhere.o
 endif
 endif
 # core command
-COBJS-y += cmd_nvedit.o
+obj-y += cmd_nvedit.o
 #environment
-COBJS-y += env_common.o
+obj-y += env_common.o
 #others
 ifdef CONFIG_DDR_SPD
 SPD := y
@@ -221,49 +229,17 @@ endif
 ifdef CONFIG_SPD_EEPROM
 SPD := y
 endif
-COBJS-$(SPD) += ddr_spd.o
-COBJS-$(CONFIG_HWCONFIG) += hwconfig.o
-COBJS-$(CONFIG_BOUNCE_BUFFER) += bouncebuf.o
-COBJS-y += console.o
-COBJS-y += dlmalloc.o
-COBJS-y += image.o
-COBJS-$(CONFIG_OF_LIBFDT) += image-fdt.o
-COBJS-$(CONFIG_FIT) += image-fit.o
-COBJS-$(CONFIG_FIT_SIGNATURE) += image-sig.o
-COBJS-y += memsize.o
-COBJS-y += stdio.o
-
-
-COBJS	:= $(sort $(COBJS-y))
-XCOBJS	:= $(sort $(XCOBJS-y))
-SRCS	:= $(COBJS:.o=.c) $(XCOBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-XOBJS	:= $(addprefix $(obj),$(XCOBJS))
-
-CPPFLAGS += -I..
-
-all:	$(LIB) $(XOBJS)
-
-$(LIB): $(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-$(obj)env_embedded.o: $(src)env_embedded.c $(obj)../tools/envcrc
-	$(CC) $(AFLAGS) -Wa,--no-warn \
-		-DENV_CRC=$(shell $(obj)../tools/envcrc) \
-		-c -o $@ $(src)env_embedded.c
-
-$(obj)../tools/envcrc:
-	$(MAKE) -C ../tools
-
-# SEE README.arm-unaligned-accesses
-$(obj)hush.o: CFLAGS += $(PLATFORM_NO_UNALIGNED)
-$(obj)fdt_support.o: CFLAGS += $(PLATFORM_NO_UNALIGNED)
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-$(SPD) += ddr_spd.o
+obj-$(CONFIG_HWCONFIG) += hwconfig.o
+obj-$(CONFIG_BOUNCE_BUFFER) += bouncebuf.o
+obj-y += console.o
+obj-$(CONFIG_CROS_EC) += cros_ec.o
+obj-y += dlmalloc.o
+obj-y += image.o
+obj-$(CONFIG_OF_LIBFDT) += image-fdt.o
+obj-$(CONFIG_FIT) += image-fit.o
+obj-$(CONFIG_FIT_SIGNATURE) += image-sig.o
+obj-y += memsize.o
+obj-y += stdio.o
+
+CFLAGS_env_embedded.o := -Wa,--no-warn -DENV_CRC=$(shell tools/envcrc 2>/dev/null)
diff --git a/common/board_f.c b/common/board_f.c
index 0ada1afe16..f285bad538 100644
--- a/common/board_f.c
+++ b/common/board_f.c
@@ -149,13 +149,9 @@ static int display_text_info(void)
 #ifndef CONFIG_SANDBOX
 	ulong bss_start, bss_end;
 
-#ifdef CONFIG_SYS_SYM_OFFSETS
-	bss_start = _bss_start_ofs + _TEXT_BASE;
-	bss_end = _bss_end_ofs + _TEXT_BASE;
-#else
 	bss_start = (ulong)&__bss_start;
 	bss_end = (ulong)&__bss_end;
-#endif
+
 	debug("U-Boot code: %08X -> %08lX  BSS: -> %08lX\n",
 	      CONFIG_SYS_TEXT_BASE, bss_start, bss_end);
 #endif
@@ -223,17 +219,6 @@ static int show_dram_config(void)
 	return 0;
 }
 
-ulong get_effective_memsize(void)
-{
-#ifndef	CONFIG_VERY_BIG_RAM
-	return gd->ram_size;
-#else
-	/* limit stack to what we can reasonable map */
-	return ((gd->ram_size > CONFIG_MAX_MEM_MAPPED) ?
-		CONFIG_MAX_MEM_MAPPED : gd->ram_size);
-#endif
-}
-
 void __dram_init_banksize(void)
 {
 #if defined(CONFIG_NR_DRAM_BANKS) && defined(CONFIG_SYS_SDRAM_BASE)
@@ -249,7 +234,11 @@ void dram_init_banksize(void)
 static int init_func_i2c(void)
 {
 	puts("I2C:   ");
+#ifdef CONFIG_SYS_I2C
+	i2c_init_all();
+#else
 	i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
+#endif
 	puts("ready\n");
 	return 0;
 }
@@ -275,8 +264,8 @@ static int zero_global_data(void)
 
 static int setup_mon_len(void)
 {
-#ifdef CONFIG_SYS_SYM_OFFSETS
-	gd->mon_len = _bss_end_ofs;
+#ifdef __ARM__
+	gd->mon_len = (ulong)&__bss_end - (ulong)_start;
 #elif defined(CONFIG_SANDBOX)
 	gd->mon_len = (ulong)&_end - (ulong)_init;
 #else
@@ -293,45 +282,39 @@ __weak int arch_cpu_init(void)
 
 #ifdef CONFIG_OF_HOSTFILE
 
-#define CHECK(x)		err = (x); if (err) goto failed;
-
-/* Create an empty device tree blob */
-static int make_empty_fdt(void *fdt)
-{
-	int err;
-
-	CHECK(fdt_create(fdt, 256));
-	CHECK(fdt_finish_reservemap(fdt));
-	CHECK(fdt_begin_node(fdt, ""));
-	CHECK(fdt_end_node(fdt));
-	CHECK(fdt_finish(fdt));
-
-	return 0;
-failed:
-	printf("Unable to create empty FDT: %s\n", fdt_strerror(err));
-	return -EACCES;
-}
-
 static int read_fdt_from_file(void)
 {
 	struct sandbox_state *state = state_get_current();
+	const char *fname = state->fdt_fname;
 	void *blob;
-	int size;
+	ssize_t size;
 	int err;
+	int fd;
 
 	blob = map_sysmem(CONFIG_SYS_FDT_LOAD_ADDR, 0);
 	if (!state->fdt_fname) {
-		err = make_empty_fdt(blob);
+		err = fdt_create_empty_tree(blob, 256);
 		if (!err)
 			goto done;
-		return err;
+		printf("Unable to create empty FDT: %s\n", fdt_strerror(err));
+		return -EINVAL;
+	}
+
+	size = os_get_filesize(fname);
+	if (size < 0) {
+		printf("Failed to file FDT file '%s'\n", fname);
+		return -ENOENT;
 	}
-	err = fs_set_blk_dev("host", NULL, FS_TYPE_SANDBOX);
-	if (err)
-		return err;
-	size = fs_read(state->fdt_fname, CONFIG_SYS_FDT_LOAD_ADDR, 0, 0);
-	if (size < 0)
+	fd = os_open(fname, OS_O_RDONLY);
+	if (fd < 0) {
+		printf("Failed to open FDT file '%s'\n", fname);
+		return -EACCES;
+	}
+	if (os_read(fd, blob, size) != size) {
+		os_close(fd);
 		return -EIO;
+	}
+	os_close(fd);
 
 done:
 	gd->fdt_blob = blob;
@@ -343,9 +326,10 @@ done:
 #ifdef CONFIG_SANDBOX
 static int setup_ram_buf(void)
 {
-	gd->arch.ram_buf = os_malloc(CONFIG_SYS_SDRAM_SIZE);
-	assert(gd->arch.ram_buf);
-	gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
+	struct sandbox_state *state = state_get_current();
+
+	gd->arch.ram_buf = state->ram_buf;
+	gd->ram_size = state->ram_size;
 
 	return 0;
 }
@@ -355,14 +339,10 @@ static int setup_fdt(void)
 {
 #ifdef CONFIG_OF_EMBED
 	/* Get a pointer to the FDT */
-	gd->fdt_blob = _binary_dt_dtb_start;
+	gd->fdt_blob = __dtb_dt_begin;
 #elif defined CONFIG_OF_SEPARATE
 	/* FDT is at end of image */
-# ifdef CONFIG_SYS_SYM_OFFSETS
-	gd->fdt_blob = (void *)(_end_ofs + CONFIG_SYS_TEXT_BASE);
-# else
 	gd->fdt_blob = (ulong *)&_end;
-# endif
 #elif defined(CONFIG_OF_HOSTFILE)
 	if (read_fdt_from_file()) {
 		puts("Failed to read control FDT\n");
@@ -458,7 +438,7 @@ static int reserve_round_4k(void)
 static int reserve_mmu(void)
 {
 	/* reserve TLB table */
-	gd->arch.tlb_size = 4096 * 4;
+	gd->arch.tlb_size = PGTABLE_SIZE;
 	gd->relocaddr -= gd->arch.tlb_size;
 
 	/* round down to next 64 kB limit */
@@ -610,7 +590,7 @@ static int reserve_stacks(void)
 	 * TODO(sjg@chromium.org): Perhaps create arch_reserve_stack()
 	 * to handle this and put in arch/xxx/lib/stack.c
 	 */
-# ifdef CONFIG_ARM
+# if defined(CONFIG_ARM) && !defined(CONFIG_ARM64)
 #  ifdef CONFIG_USE_IRQ
 	gd->start_addr_sp -= (CONFIG_STACKSIZE_IRQ + CONFIG_STACKSIZE_FIQ);
 	debug("Reserving %zu Bytes for IRQ stack at: %08lx\n",
@@ -656,7 +636,7 @@ static int setup_board_part1(void)
 	bd->bi_sramsize = CONFIG_SYS_SRAM_SIZE;		/* size  of SRAM */
 #endif
 
-#if defined(CONFIG_8xx) || defined(CONFIG_8260) || defined(CONFIG_5xx) || \
+#if defined(CONFIG_8xx) || defined(CONFIG_MPC8260) || defined(CONFIG_5xx) || \
 		defined(CONFIG_E500) || defined(CONFIG_MPC86xx)
 	bd->bi_immr_base = CONFIG_SYS_IMMR;	/* base  of IMMR register     */
 #endif
@@ -768,7 +748,7 @@ static int setup_reloc(void)
 }
 
 /* ARM calls relocate_code from its crt0.S */
-#if !defined(CONFIG_ARM)
+#if !defined(CONFIG_ARM) && !defined(CONFIG_SANDBOX)
 
 static int jump_to_copy(void)
 {
@@ -788,8 +768,6 @@ static int jump_to_copy(void)
 	 * (CPU cache)
 	 */
 	board_init_f_r_trampoline(gd->start_addr_sp);
-#elif defined(CONFIG_SANDBOX)
-	board_init_r(gd->new_gd, 0);
 #else
 	relocate_code(gd->start_addr_sp, gd->new_gd, gd->relocaddr);
 #endif
@@ -807,11 +785,6 @@ static int mark_bootstage(void)
 }
 
 static init_fnc_t init_sequence_f[] = {
-#if !defined(CONFIG_CPM2) && !defined(CONFIG_MPC512X) && \
-		!defined(CONFIG_MPC83xx) && !defined(CONFIG_MPC85xx) && \
-		!defined(CONFIG_MPC86xx) && !defined(CONFIG_X86)
-	zero_global_data,
-#endif
 #ifdef CONFIG_SANDBOX
 	setup_ram_buf,
 #endif
@@ -879,19 +852,17 @@ static init_fnc_t init_sequence_f[] = {
 #endif
 	display_options,	/* say that we are here */
 	display_text_info,	/* show debugging info if required */
-#if defined(CONFIG_8260)
+#if defined(CONFIG_MPC8260)
 	prt_8260_rsr,
 	prt_8260_clks,
-#endif /* CONFIG_8260 */
+#endif /* CONFIG_MPC8260 */
 #if defined(CONFIG_MPC83xx)
 	prt_83xx_rsr,
 #endif
 #ifdef CONFIG_PPC
 	checkcpu,
 #endif
-#if defined(CONFIG_DISPLAY_CPUINFO)
 	print_cpuinfo,		/* display cpu info (and speed) */
-#endif
 #if defined(CONFIG_MPC5xxx)
 	prt_mpc5xxx_clks,
 #endif /* CONFIG_MPC5xxx */
@@ -991,7 +962,7 @@ static init_fnc_t init_sequence_f[] = {
 	INIT_FUNC_WATCHDOG_RESET
 	reloc_fdt,
 	setup_reloc,
-#ifndef CONFIG_ARM
+#if !defined(CONFIG_ARM) && !defined(CONFIG_SANDBOX)
 	jump_to_copy,
 #endif
 	NULL,
@@ -1005,12 +976,24 @@ void board_init_f(ulong boot_flags)
 	gd = &data;
 #endif
 
+	/*
+	 * Clear global data before it is accessed at debug print
+	 * in initcall_run_list. Otherwise the debug print probably
+	 * get the wrong vaule of gd->have_console.
+	 */
+#if !defined(CONFIG_CPM2) && !defined(CONFIG_MPC512X) && \
+		!defined(CONFIG_MPC83xx) && !defined(CONFIG_MPC85xx) && \
+		!defined(CONFIG_MPC86xx) && !defined(CONFIG_X86)
+	zero_global_data();
+#endif
+
 	gd->flags = boot_flags;
+	gd->have_console = 0;
 
 	if (initcall_run_list(init_sequence_f))
 		hang();
 
-#ifndef CONFIG_ARM
+#if !defined(CONFIG_ARM) && !defined(CONFIG_SANDBOX)
 	/* NOTREACHED - jump_to_copy() does not return */
 	hang();
 #endif
diff --git a/common/board_r.c b/common/board_r.c
index 86ca1cbbd4..8629a656c2 100644
--- a/common/board_r.c
+++ b/common/board_r.c
@@ -18,6 +18,7 @@
 #ifdef CONFIG_HAS_DATAFLASH
 #include <dataflash.h>
 #endif
+#include <dm.h>
 #include <environment.h>
 #include <fdtdec.h>
 #if defined(CONFIG_CMD_IDE)
@@ -51,7 +52,9 @@
 #ifdef CONFIG_X86
 #include <asm/init_helpers.h>
 #endif
+#include <dm/root.h>
 #include <linux/compiler.h>
+#include <linux/err.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -128,8 +131,8 @@ __weak int fixup_cpu(void)
 
 static int initr_reloc_global_data(void)
 {
-#ifdef CONFIG_SYS_SYM_OFFSETS
-	monitor_flash_len = _end_ofs;
+#ifdef __ARM__
+	monitor_flash_len = _end - __image_copy_start;
 #elif !defined(CONFIG_SANDBOX)
 	monitor_flash_len = (ulong)&__init_end - gd->relocaddr;
 #endif
@@ -263,6 +266,33 @@ static int initr_malloc(void)
 	return 0;
 }
 
+#ifdef CONFIG_DM
+static int initr_dm(void)
+{
+	int ret;
+
+	ret = dm_init();
+	if (ret) {
+		debug("dm_init() failed: %d\n", ret);
+		return ret;
+	}
+	ret = dm_scan_platdata();
+	if (ret) {
+		debug("dm_scan_platdata() failed: %d\n", ret);
+		return ret;
+	}
+#ifdef CONFIG_OF_CONTROL
+	ret = dm_scan_fdt(gd->fdt_blob);
+	if (ret) {
+		debug("dm_scan_fdt() failed: %d\n", ret);
+		return ret;
+	}
+#endif
+
+	return 0;
+}
+#endif
+
 __weak int power_init_board(void)
 {
 	return 0;
@@ -761,6 +791,9 @@ init_fnc_t init_sequence_r[] = {
 	initr_barrier,
 	initr_malloc,
 	bootstage_relocate,
+#ifdef CONFIG_DM
+	initr_dm,
+#endif
 #ifdef CONFIG_ARCH_EARLY_INIT_R
 	arch_early_init_r,
 #endif
@@ -903,9 +936,19 @@ init_fnc_t init_sequence_r[] = {
 
 void board_init_r(gd_t *new_gd, ulong dest_addr)
 {
+#ifdef CONFIG_NEEDS_MANUAL_RELOC
+	int i;
+#endif
+
 #ifndef CONFIG_X86
 	gd = new_gd;
 #endif
+
+#ifdef CONFIG_NEEDS_MANUAL_RELOC
+	for (i = 0; i < ARRAY_SIZE(init_sequence_r); i++)
+		init_sequence_r[i] += gd->reloc_off;
+#endif
+
 	if (initcall_run_list(init_sequence_r))
 		hang();
 
diff --git a/common/cmd_bdinfo.c b/common/cmd_bdinfo.c
index 713de1464c..238cadb1e1 100644
--- a/common/cmd_bdinfo.c
+++ b/common/cmd_bdinfo.c
@@ -88,7 +88,7 @@ int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 	print_num("sramstart",		bd->bi_sramstart);
 	print_num("sramsize",		bd->bi_sramsize);
 #if	defined(CONFIG_5xx)  || defined(CONFIG_8xx) || \
-	defined(CONFIG_8260) || defined(CONFIG_E500)
+	defined(CONFIG_MPC8260) || defined(CONFIG_E500)
 	print_num("immr_base",		bd->bi_immr_base);
 #endif
 	print_num("bootflags",		bd->bi_bootflags);
@@ -517,6 +517,24 @@ int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 	return 0;
 }
 
+#elif defined(CONFIG_ARC700)
+
+int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	bd_t *bd = gd->bd;
+
+	print_num("mem start",		bd->bi_memstart);
+	print_lnum("mem size",		bd->bi_memsize);
+
+#if defined(CONFIG_CMD_NET)
+	print_eth(0);
+	printf("ip_addr     = %s\n", getenv("ipaddr"));
+#endif
+	printf("baudrate    = %d bps\n", bd->bi_baudrate);
+
+	return 0;
+}
+
 #else
  #error "a case for this architecture does not exist!"
 #endif
diff --git a/common/cmd_bootm.c b/common/cmd_bootm.c
index 166b901d76..9751edc907 100644
--- a/common/cmd_bootm.c
+++ b/common/cmd_bootm.c
@@ -23,6 +23,11 @@
 #include <asm/io.h>
 #include <linux/compiler.h>
 
+#if defined(CONFIG_BOOTM_VXWORKS) && \
+	(defined(CONFIG_PPC) || defined(CONFIG_ARM))
+#include <vxworks.h>
+#endif
+
 #if defined(CONFIG_CMD_USB)
 #include <usb.h>
 #endif
@@ -77,6 +82,9 @@ static int do_imls(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]);
 static void fixup_silent_linux(void);
 #endif
 
+static int do_bootm_standalone(int flag, int argc, char * const argv[],
+			       bootm_headers_t *images);
+
 static const void *boot_get_kernel(cmd_tbl_t *cmdtp, int flag, int argc,
 				char * const argv[], bootm_headers_t *images,
 				ulong *os_data, ulong *os_len);
@@ -120,8 +128,11 @@ static boot_os_fn do_bootm_ose;
 #if defined(CONFIG_BOOTM_PLAN9)
 static boot_os_fn do_bootm_plan9;
 #endif
-#if defined(CONFIG_CMD_ELF)
+#if defined(CONFIG_BOOTM_VXWORKS) && \
+	(defined(CONFIG_PPC) || defined(CONFIG_ARM))
 static boot_os_fn do_bootm_vxworks;
+#endif
+#if defined(CONFIG_CMD_ELF)
 static boot_os_fn do_bootm_qnxelf;
 int do_bootvx(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]);
 int do_bootelf(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]);
@@ -131,6 +142,7 @@ static boot_os_fn do_bootm_integrity;
 #endif
 
 static boot_os_fn *boot_os[] = {
+	[IH_OS_U_BOOT] = do_bootm_standalone,
 #ifdef CONFIG_BOOTM_LINUX
 	[IH_OS_LINUX] = do_bootm_linux,
 #endif
@@ -149,8 +161,11 @@ static boot_os_fn *boot_os[] = {
 #if defined(CONFIG_BOOTM_PLAN9)
 	[IH_OS_PLAN9] = do_bootm_plan9,
 #endif
-#if defined(CONFIG_CMD_ELF)
+#if defined(CONFIG_BOOTM_VXWORKS) && \
+	(defined(CONFIG_PPC) || defined(CONFIG_ARM))
 	[IH_OS_VXWORKS] = do_bootm_vxworks,
+#endif
+#if defined(CONFIG_CMD_ELF)
 	[IH_OS_QNX] = do_bootm_qnxelf,
 #endif
 #ifdef CONFIG_INTEGRITY
@@ -333,7 +348,8 @@ static int bootm_find_other(cmd_tbl_t *cmdtp, int flag, int argc,
 	if (((images.os.type == IH_TYPE_KERNEL) ||
 	     (images.os.type == IH_TYPE_KERNEL_NOLOAD) ||
 	     (images.os.type == IH_TYPE_MULTI)) &&
-	    (images.os.os == IH_OS_LINUX)) {
+	    (images.os.os == IH_OS_LINUX ||
+		 images.os.os == IH_OS_VXWORKS)) {
 		if (bootm_find_ramdisk(flag, argc, argv))
 			return 1;
 
@@ -487,18 +503,19 @@ static int bootm_load_os(bootm_headers_t *images, unsigned long *load_end,
 	return 0;
 }
 
-static int bootm_start_standalone(int argc, char * const argv[])
+static int do_bootm_standalone(int flag, int argc, char * const argv[],
+			       bootm_headers_t *images)
 {
 	char  *s;
 	int   (*appl)(int, char * const []);
 
 	/* Don't start if "autostart" is set to "no" */
 	if (((s = getenv("autostart")) != NULL) && (strcmp(s, "no") == 0)) {
-		setenv_hex("filesize", images.os.image_len);
+		setenv_hex("filesize", images->os.image_len);
 		return 0;
 	}
-	appl = (int (*)(int, char * const []))(ulong)ntohl(images.ep);
-	(*appl)(argc, argv);
+	appl = (int (*)(int, char * const []))images->ep;
+	appl(argc, argv);
 	return 0;
 }
 
@@ -523,14 +540,12 @@ static cmd_tbl_t cmd_bootm_sub[] = {
 static int boot_selected_os(int argc, char * const argv[], int state,
 		bootm_headers_t *images, boot_os_fn *boot_fn)
 {
-	if (images->os.type == IH_TYPE_STANDALONE) {
-		/* This may return when 'autostart' is 'no' */
-		bootm_start_standalone(argc, argv);
-		return 0;
-	}
 	arch_preboot_os();
 	boot_fn(state, argc, argv, images);
-	if (state == BOOTM_STATE_OS_FAKE_GO) /* We expect to return */
+
+	/* Stand-alone may return when 'autostart' is 'no' */
+	if (images->os.type == IH_TYPE_STANDALONE ||
+	    state == BOOTM_STATE_OS_FAKE_GO) /* We expect to return */
 		return 0;
 	bootstage_error(BOOTSTAGE_ID_BOOT_OS_RETURNED);
 #ifdef DEBUG
@@ -1469,10 +1484,8 @@ static int do_bootm_netbsd(int flag, int argc, char * const argv[],
 	char *consdev;
 	char *cmdline;
 
-	if (flag & BOOTM_STATE_OS_PREP)
+	if (flag != BOOTM_STATE_OS_GO)
 		return 0;
-	if ((flag != 0) && (flag != BOOTM_STATE_OS_GO))
-		return 1;
 
 #if defined(CONFIG_FIT)
 	if (!images->legacy_hdr_valid) {
@@ -1533,10 +1546,10 @@ static int do_bootm_netbsd(int flag, int argc, char * const argv[],
 
 	/*
 	 * NetBSD Stage-2 Loader Parameters:
-	 *   r3: ptr to board info data
-	 *   r4: image address
-	 *   r5: console device
-	 *   r6: boot args string
+	 *   arg[0]: pointer to board info data
+	 *   arg[1]: image load address
+	 *   arg[2]: char pointer to the console device to use
+	 *   arg[3]: char pointer to the boot arguments
 	 */
 	(*loader)(gd->bd, os_hdr, consdev, cmdline);
 
@@ -1550,10 +1563,8 @@ static int do_bootm_lynxkdi(int flag, int argc, char * const argv[],
 {
 	image_header_t *hdr = &images->legacy_hdr_os_copy;
 
-	if (flag & BOOTM_STATE_OS_PREP)
+	if (flag != BOOTM_STATE_OS_GO)
 		return 0;
-	if ((flag != 0) && (flag != BOOTM_STATE_OS_GO))
-		return 1;
 
 #if defined(CONFIG_FIT)
 	if (!images->legacy_hdr_valid) {
@@ -1574,10 +1585,8 @@ static int do_bootm_rtems(int flag, int argc, char * const argv[],
 {
 	void (*entry_point)(bd_t *);
 
-	if (flag & BOOTM_STATE_OS_PREP)
+	if (flag != BOOTM_STATE_OS_GO)
 		return 0;
-	if ((flag != 0) && (flag != BOOTM_STATE_OS_GO))
-		return 1;
 
 #if defined(CONFIG_FIT)
 	if (!images->legacy_hdr_valid) {
@@ -1609,10 +1618,8 @@ static int do_bootm_ose(int flag, int argc, char * const argv[],
 {
 	void (*entry_point)(void);
 
-	if (flag & BOOTM_STATE_OS_PREP)
+	if (flag != BOOTM_STATE_OS_GO)
 		return 0;
-	if ((flag != 0) && (flag != BOOTM_STATE_OS_GO))
-		return 1;
 
 #if defined(CONFIG_FIT)
 	if (!images->legacy_hdr_valid) {
@@ -1645,10 +1652,8 @@ static int do_bootm_plan9(int flag, int argc, char * const argv[],
 	void (*entry_point)(void);
 	char *s;
 
-	if (flag & BOOTM_STATE_OS_PREP)
+	if (flag != BOOTM_STATE_OS_GO)
 		return 0;
-	if ((flag != 0) && (flag != BOOTM_STATE_OS_GO))
-		return 1;
 
 #if defined(CONFIG_FIT)
 	if (!images->legacy_hdr_valid) {
@@ -1688,16 +1693,68 @@ static int do_bootm_plan9(int flag, int argc, char * const argv[],
 }
 #endif /* CONFIG_BOOTM_PLAN9 */
 
-#if defined(CONFIG_CMD_ELF)
+#if defined(CONFIG_BOOTM_VXWORKS) && \
+	(defined(CONFIG_PPC) || defined(CONFIG_ARM))
+
+void do_bootvx_fdt(bootm_headers_t *images)
+{
+#if defined(CONFIG_OF_LIBFDT)
+	int ret;
+	char *bootline;
+	ulong of_size = images->ft_len;
+	char **of_flat_tree = &images->ft_addr;
+	struct lmb *lmb = &images->lmb;
+
+	if (*of_flat_tree) {
+		boot_fdt_add_mem_rsv_regions(lmb, *of_flat_tree);
+
+		ret = boot_relocate_fdt(lmb, of_flat_tree, &of_size);
+		if (ret)
+			return;
+
+		ret = fdt_add_subnode(*of_flat_tree, 0, "chosen");
+		if ((ret >= 0 || ret == -FDT_ERR_EXISTS)) {
+			bootline = getenv("bootargs");
+			if (bootline) {
+				ret = fdt_find_and_setprop(*of_flat_tree,
+						"/chosen", "bootargs",
+						bootline,
+						strlen(bootline) + 1, 1);
+				if (ret < 0) {
+					printf("## ERROR: %s : %s\n", __func__,
+					       fdt_strerror(ret));
+					return;
+				}
+			}
+		} else {
+			printf("## ERROR: %s : %s\n", __func__,
+			       fdt_strerror(ret));
+			return;
+		}
+	}
+#endif
+
+	boot_prep_vxworks(images);
+
+	bootstage_mark(BOOTSTAGE_ID_RUN_OS);
+
+#if defined(CONFIG_OF_LIBFDT)
+	printf("## Starting vxWorks at 0x%08lx, device tree at 0x%08lx ...\n",
+	       (ulong)images->ep, (ulong)*of_flat_tree);
+#else
+	printf("## Starting vxWorks at 0x%08lx\n", (ulong)images->ep);
+#endif
+
+	boot_jump_vxworks(images);
+
+	puts("## vxWorks terminated\n");
+}
+
 static int do_bootm_vxworks(int flag, int argc, char * const argv[],
 			     bootm_headers_t *images)
 {
-	char str[80];
-
-	if (flag & BOOTM_STATE_OS_PREP)
+	if (flag != BOOTM_STATE_OS_GO)
 		return 0;
-	if ((flag != 0) && (flag != BOOTM_STATE_OS_GO))
-		return 1;
 
 #if defined(CONFIG_FIT)
 	if (!images->legacy_hdr_valid) {
@@ -1706,23 +1763,21 @@ static int do_bootm_vxworks(int flag, int argc, char * const argv[],
 	}
 #endif
 
-	sprintf(str, "%lx", images->ep); /* write entry-point into string */
-	setenv("loadaddr", str);
-	do_bootvx(NULL, 0, 0, NULL);
+	do_bootvx_fdt(images);
 
 	return 1;
 }
+#endif
 
+#if defined(CONFIG_CMD_ELF)
 static int do_bootm_qnxelf(int flag, int argc, char * const argv[],
 			    bootm_headers_t *images)
 {
 	char *local_args[2];
 	char str[16];
 
-	if (flag & BOOTM_STATE_OS_PREP)
+	if (flag != BOOTM_STATE_OS_GO)
 		return 0;
-	if ((flag != 0) && (flag != BOOTM_STATE_OS_GO))
-		return 1;
 
 #if defined(CONFIG_FIT)
 	if (!images->legacy_hdr_valid) {
@@ -1746,10 +1801,8 @@ static int do_bootm_integrity(int flag, int argc, char * const argv[],
 {
 	void (*entry_point)(void);
 
-	if (flag & BOOTM_STATE_OS_PREP)
+	if (flag != BOOTM_STATE_OS_GO)
 		return 0;
-	if ((flag != 0) && (flag != BOOTM_STATE_OS_GO))
-		return 1;
 
 #if defined(CONFIG_FIT)
 	if (!images->legacy_hdr_valid) {
diff --git a/common/cmd_clk.c b/common/cmd_clk.c
new file mode 100644
index 0000000000..6d3d46a184
--- /dev/null
+++ b/common/cmd_clk.c
@@ -0,0 +1,51 @@
+/*
+ * Copyright (C) 2013 Xilinx, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+#include <common.h>
+#include <command.h>
+#include <clk.h>
+
+int __weak soc_clk_dump(void)
+{
+	puts("Not implemented\n");
+	return 1;
+}
+
+static int do_clk_dump(cmd_tbl_t *cmdtp, int flag, int argc,
+		       char *const argv[])
+{
+	return soc_clk_dump();
+}
+
+static cmd_tbl_t cmd_clk_sub[] = {
+	U_BOOT_CMD_MKENT(dump, 1, 1, do_clk_dump, "", ""),
+};
+
+static int do_clk(cmd_tbl_t *cmdtp, int flag, int argc,
+		  char *const argv[])
+{
+	cmd_tbl_t *c;
+
+	if (argc < 2)
+		return CMD_RET_USAGE;
+
+	/* Strip off leading 'clk' command argument */
+	argc--;
+	argv++;
+
+	c = find_cmd_tbl(argv[0], &cmd_clk_sub[0], ARRAY_SIZE(cmd_clk_sub));
+
+	if (c)
+		return c->cmd(cmdtp, flag, argc, argv);
+	else
+		return CMD_RET_USAGE;
+}
+
+#ifdef CONFIG_SYS_LONGHELP
+static char clk_help_text[] =
+	"dump - Print clock frequencies";
+#endif
+
+U_BOOT_CMD(clk, 2, 1, do_clk, "CLK sub-system", clk_help_text);
diff --git a/common/cmd_demo.c b/common/cmd_demo.c
new file mode 100644
index 0000000000..a3bba7fdf3
--- /dev/null
+++ b/common/cmd_demo.c
@@ -0,0 +1,102 @@
+/*
+ * Copyright (c) 2013 Google, Inc
+ *
+ * (C) Copyright 2012
+ * Pavel Herrmann <morpheus.ibis@gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm-demo.h>
+#include <asm/io.h>
+
+struct device *demo_dev;
+
+static int do_demo_hello(cmd_tbl_t *cmdtp, int flag, int argc,
+			 char * const argv[])
+{
+	int ch = 0;
+
+	if (argc)
+		ch = *argv[0];
+
+	return demo_hello(demo_dev, ch);
+}
+
+static int do_demo_status(cmd_tbl_t *cmdtp, int flag, int argc,
+			  char * const argv[])
+{
+	int status;
+	int ret;
+
+	ret = demo_status(demo_dev, &status);
+	if (ret)
+		return ret;
+
+	printf("Status: %d\n", status);
+
+	return 0;
+}
+
+int do_demo_list(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	struct device *dev;
+	int i, ret;
+
+	puts("Demo uclass entries:\n");
+
+	for (i = 0, ret = uclass_first_device(UCLASS_DEMO, &dev);
+	     dev;
+	     ret = uclass_next_device(&dev)) {
+		printf("entry %d - instance %08x, ops %08x, platdata %08x\n",
+		       i++, map_to_sysmem(dev),
+		       map_to_sysmem(dev->driver->ops),
+		       map_to_sysmem(dev_get_platdata(dev)));
+	}
+
+	return cmd_process_error(cmdtp, ret);
+}
+
+static cmd_tbl_t demo_commands[] = {
+	U_BOOT_CMD_MKENT(list, 0, 1, do_demo_list, "", ""),
+	U_BOOT_CMD_MKENT(hello, 2, 1, do_demo_hello, "", ""),
+	U_BOOT_CMD_MKENT(status, 1, 1, do_demo_status, "", ""),
+};
+
+static int do_demo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	cmd_tbl_t *demo_cmd;
+	int devnum = 0;
+	int ret;
+
+	if (argc < 2)
+		return CMD_RET_USAGE;
+	demo_cmd = find_cmd_tbl(argv[1], demo_commands,
+				ARRAY_SIZE(demo_commands));
+	argc -= 2;
+	argv += 2;
+	if (!demo_cmd || argc > demo_cmd->maxargs)
+		return CMD_RET_USAGE;
+
+	if (argc) {
+		devnum = simple_strtoul(argv[0], NULL, 10);
+		ret = uclass_get_device(UCLASS_DEMO, devnum, &demo_dev);
+		if (ret)
+			return cmd_process_error(cmdtp, ret);
+		argc--;
+		argv++;
+	}
+
+	ret = demo_cmd->cmd(demo_cmd, flag, argc, argv);
+
+	return cmd_process_error(demo_cmd, ret);
+}
+
+U_BOOT_CMD(
+	demo,   4,      1,      do_demo,
+	"Driver model (dm) demo operations",
+	"list                     List available demo devices\n"
+	"demo hello <num> [<char>]     Say hello\n"
+	"demo status <num>             Get demo device status"
+);
diff --git a/common/cmd_dfu.c b/common/cmd_dfu.c
index 7ce92cec87..5547678208 100644
--- a/common/cmd_dfu.c
+++ b/common/cmd_dfu.c
@@ -11,27 +11,32 @@
 #include <common.h>
 #include <dfu.h>
 #include <g_dnl.h>
+#include <usb.h>
 
 static int do_dfu(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 {
+	if (argc < 4)
+		return CMD_RET_USAGE;
+
+	char *usb_controller = argv[1];
+	char *interface = argv[2];
+	char *devstring = argv[3];
+
 	char *s = "dfu";
 	int ret, i = 0;
 
-	if (argc < 3)
-		return CMD_RET_USAGE;
-
-	ret = dfu_init_env_entities(argv[1], simple_strtoul(argv[2], NULL, 10));
+	ret = dfu_init_env_entities(interface, simple_strtoul(devstring,
+							      NULL, 10));
 	if (ret)
 		return ret;
 
-	if (argc > 3 && strcmp(argv[3], "list") == 0) {
+	if (argc > 4 && strcmp(argv[4], "list") == 0) {
 		dfu_show_entities();
 		goto done;
 	}
 
-#ifdef CONFIG_TRATS
-	board_usb_init();
-#endif
+	int controller_index = simple_strtoul(usb_controller, NULL, 0);
+	board_usb_init(controller_index, USB_INIT_DEVICE);
 
 	g_dnl_register(s);
 	while (1) {
@@ -62,8 +67,9 @@ done:
 
 U_BOOT_CMD(dfu, CONFIG_SYS_MAXARGS, 1, do_dfu,
 	"Device Firmware Upgrade",
-	"<interface> <dev> [list]\n"
-	"  - device firmware upgrade on a device <dev>\n"
-	"    attached to interface <interface>\n"
-	"    [list] - list available alt settings"
+	"<USB_controller> <interface> <dev> [list]\n"
+	"  - device firmware upgrade via <USB_controller>\n"
+	"    on device <dev>, attached to interface\n"
+	"    <interface>\n"
+	"    [list] - list available alt settings\n"
 );
diff --git a/common/cmd_eeprom.c b/common/cmd_eeprom.c
index ef694d8f87..fad462fb34 100644
--- a/common/cmd_eeprom.c
+++ b/common/cmd_eeprom.c
@@ -161,7 +161,7 @@ int eeprom_read (unsigned dev_addr, unsigned offset, uchar *buffer, unsigned cnt
 #if defined(CONFIG_SPI) && !defined(CONFIG_ENV_EEPROM_IS_ON_I2C)
 		spi_read (addr, alen, buffer, len);
 #else
-		if (i2c_read (addr[0], offset, alen-1, buffer, len) != 0)
+		if (i2c_read(addr[0], offset, alen - 1, buffer, len))
 			rcode = 1;
 #endif
 		buffer += len;
@@ -339,7 +339,7 @@ int eeprom_write (unsigned dev_addr, unsigned offset, uchar *buffer, unsigned cn
 		/* Write is enabled ... now write eeprom value.
 		 */
 #endif
-		if (i2c_write (addr[0], offset, alen-1, buffer, len) != 0)
+		if (i2c_write(addr[0], offset, alen - 1, buffer, len))
 			rcode = 1;
 
 #endif
@@ -389,8 +389,13 @@ void eeprom_init  (void)
 #if defined(CONFIG_SPI) && !defined(CONFIG_ENV_EEPROM_IS_ON_I2C)
 	spi_init_f ();
 #endif
-#if defined(CONFIG_HARD_I2C) || defined(CONFIG_SYS_I2C_SOFT)
-	i2c_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
+#if defined(CONFIG_HARD_I2C) || defined(CONFIG_SYS_I2C_SOFT) || \
+	defined(CONFIG_SYS_I2C)
+#ifdef CONFIG_SYS_I2C
+	i2c_init_all();
+#else
+	i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
+#endif
 #endif
 }
 
diff --git a/common/cmd_elf.c b/common/cmd_elf.c
index f741f6b83f..ab9c7e332d 100644
--- a/common/cmd_elf.c
+++ b/common/cmd_elf.c
@@ -156,16 +156,16 @@ int do_bootvx(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 	 * If we don't know where the image is then we're done.
 	 */
 
-	if (argc < 1)
+	if (argc < 2)
 		addr = load_addr;
 	else
-		addr = simple_strtoul(argv[0], NULL, 16);
+		addr = simple_strtoul(argv[1], NULL, 16);
 
 #if defined(CONFIG_CMD_NET)
 	/*
 	 * Check to see if we need to tftp the image ourselves before starting
 	 */
-	if ((argc == 1) && (strcmp(argv[0], "tftp") == 0)) {
+	if ((argc == 2) && (strcmp(argv[1], "tftp") == 0)) {
 		if (NetLoop(TFTPGET) <= 0)
 			return 1;
 		printf("Automatic boot of VxWorks image at address 0x%08lx ...\n",
diff --git a/common/cmd_ext4.c b/common/cmd_ext4.c
index 8289d25b06..68b047ba6a 100644
--- a/common/cmd_ext4.c
+++ b/common/cmd_ext4.c
@@ -79,8 +79,8 @@ int do_ext4_write(cmd_tbl_t *cmdtp, int flag, int argc,
 	/* get the address in hexadecimal format (string to int) */
 	ram_address = simple_strtoul(argv[3], NULL, 16);
 
-	/* get the filesize in base 10 format */
-	file_size = simple_strtoul(argv[5], NULL, 10);
+	/* get the filesize in hexadecimal format */
+	file_size = simple_strtoul(argv[5], NULL, 16);
 
 	/* set the device as block device */
 	ext4fs_set_blk_dev(dev_desc, &info);
diff --git a/common/cmd_fdc.c b/common/cmd_fdc.c
index 98b3c4c001..1cfb656bc0 100644
--- a/common/cmd_fdc.c
+++ b/common/cmd_fdc.c
@@ -627,72 +627,6 @@ int fdc_setup(int drive, FDC_COMMAND_STRUCT *pCMD, FD_GEO_STRUCT *pFG)
 	return true;
 }
 
-#if defined(CONFIG_CMD_FDOS)
-
-/* Low level functions for the Floppy-DOS layer                              */
-
-/**************************************************************************
-* int fdc_fdos_init
-* initialize the FDC layer
-*
-*/
-int fdc_fdos_init (int drive)
-{
-	FD_GEO_STRUCT *pFG = (FD_GEO_STRUCT *)floppy_type;
-	FDC_COMMAND_STRUCT *pCMD = &cmd;
-
-	/* setup FDC and scan for drives  */
-	if (fdc_setup(drive, pCMD, pFG) == false) {
-		printf("\n** Error in setup FDC **\n");
-		return false;
-	}
-	if (fdc_check_drive(pCMD, pFG) == false) {
-		printf("\n** Error in check_drives **\n");
-		return false;
-	}
-	if((pCMD->flags&(1<<drive))==0) {
-		/* drive not available */
-		printf("\n** Drive %d not available **\n",drive);
-		return false;
-	}
-	if((pCMD->flags&(0x10<<drive))==0) {
-		/* no disk inserted */
-		printf("\n** No disk inserted in drive %d **\n",drive);
-		return false;
-	}
-	/* ok, we have a valid source */
-	pCMD->drive=drive;
-
-	/* read first block */
-	pCMD->blnr=0;
-	return true;
-}
-/**************************************************************************
-* int fdc_fdos_seek
-* parameter is a block number
-*/
-int fdc_fdos_seek (int where)
-{
-	FD_GEO_STRUCT *pFG = (FD_GEO_STRUCT *)floppy_type;
-	FDC_COMMAND_STRUCT *pCMD = &cmd;
-
-	pCMD -> blnr = where ;
-	return (fdc_seek (pCMD, pFG));
-}
-/**************************************************************************
-* int fdc_fdos_read
-*  the length is in block number
-*/
-int fdc_fdos_read (void *buffer, int len)
-{
-	FD_GEO_STRUCT *pFG = (FD_GEO_STRUCT *)floppy_type;
-	FDC_COMMAND_STRUCT *pCMD = &cmd;
-
-	return (fdc_read_data (buffer, len, pCMD, pFG));
-}
-#endif
-
-#if defined(CONFIG_CMD_FDC)
 /****************************************************************************
  * main routine do_fdcboot
  */
@@ -812,4 +746,3 @@ U_BOOT_CMD(
 	"boot from floppy device",
 	"loadAddr drive"
 );
-#endif
diff --git a/common/cmd_fpga.c b/common/cmd_fpga.c
index c4b3c8fc56..010cd24e63 100644
--- a/common/cmd_fpga.c
+++ b/common/cmd_fpga.c
@@ -160,9 +160,25 @@ int do_fpga(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
 				image_header_t *hdr =
 						(image_header_t *)fpga_data;
 				ulong data;
-
-				data = (ulong)image_get_data(hdr);
-				data_size = image_get_data_size(hdr);
+				uint8_t comp;
+
+				comp = image_get_comp(hdr);
+				if (comp == IH_COMP_GZIP) {
+					ulong image_buf = image_get_data(hdr);
+					data = image_get_load(hdr);
+					ulong image_size = ~0UL;
+
+					if (gunzip((void *)data, ~0UL,
+						   (void *)image_buf,
+						   &image_size) != 0) {
+						puts("GUNZIP: error\n");
+						return 1;
+					}
+					data_size = image_size;
+				} else {
+					data = (ulong)image_get_data(hdr);
+					data_size = image_get_data_size(hdr);
+				}
 				rc = fpga_load(dev, (void *)data, data_size);
 			}
 			break;
diff --git a/common/cmd_gpio.c b/common/cmd_gpio.c
index 47eee89221..778aa5f098 100644
--- a/common/cmd_gpio.c
+++ b/common/cmd_gpio.c
@@ -8,7 +8,7 @@
 
 #include <common.h>
 #include <command.h>
-
+#include <dm.h>
 #include <asm/gpio.h>
 
 #ifndef name_to_gpio
@@ -22,25 +22,115 @@ enum gpio_cmd {
 	GPIO_TOGGLE,
 };
 
+#if defined(CONFIG_DM_GPIO) && !defined(gpio_status)
+static const char * const gpio_function[] = {
+	"input",
+	"output",
+	"unknown",
+};
+
+static void show_gpio(struct device *dev, const char *bank_name, int offset)
+{
+	struct dm_gpio_ops *ops = gpio_get_ops(dev);
+	char buf[80];
+	int ret;
+
+	*buf = '\0';
+	if (ops->get_state) {
+		ret = ops->get_state(dev, offset, buf, sizeof(buf));
+		if (ret) {
+			puts("<unknown>");
+			return;
+		}
+	} else {
+		int func =  GPIOF_UNKNOWN;
+		int ret;
+
+		if (ops->get_function) {
+			ret = ops->get_function(dev, offset);
+			if (ret >= 0 && ret < ARRAY_SIZE(gpio_function))
+				func = ret;
+		}
+		sprintf(buf, "%s%u: %8s %d", bank_name, offset,
+			gpio_function[func], ops->get_value(dev, offset));
+	}
+
+	puts(buf);
+	puts("\n");
+}
+
+static int do_gpio_status(const char *gpio_name)
+{
+	struct device *dev;
+	int newline = 0;
+	int ret;
+
+	if (gpio_name && !*gpio_name)
+		gpio_name = NULL;
+	for (ret = uclass_first_device(UCLASS_GPIO, &dev);
+	     dev;
+	     ret = uclass_next_device(&dev)) {
+		const char *bank_name;
+		int num_bits;
+
+		bank_name = gpio_get_bank_info(dev, &num_bits);
+
+		if (!gpio_name || !bank_name ||
+		    !strncmp(gpio_name, bank_name, strlen(bank_name))) {
+			const char *p = NULL;
+			int offset;
+
+			if (bank_name) {
+				if (newline)
+					putc('\n');
+				printf("Bank %s:\n", bank_name);
+			}
+			newline = 1;
+			if (gpio_name && bank_name) {
+				p = gpio_name + strlen(bank_name);
+				offset = simple_strtoul(p, NULL, 10);
+				show_gpio(dev, bank_name, offset);
+			} else {
+				for (offset = 0; offset < num_bits; offset++)
+					show_gpio(dev, bank_name, offset);
+			}
+		}
+	}
+
+	return ret;
+}
+#endif
+
 static int do_gpio(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 {
-	int gpio;
+	unsigned int gpio;
 	enum gpio_cmd sub_cmd;
 	ulong value;
-	const char *str_cmd, *str_gpio;
+	const char *str_cmd, *str_gpio = NULL;
+#ifdef CONFIG_DM_GPIO
+	int ret;
+#endif
 
+	if (argc < 2)
+ show_usage:
+		return CMD_RET_USAGE;
+	str_cmd = argv[1];
+	if (argc > 2)
+		str_gpio = argv[2];
+	if (!strcmp(str_cmd, "status")) {
+		/* Support deprecated gpio_status() */
 #ifdef gpio_status
-	if (argc == 2 && !strcmp(argv[1], "status")) {
 		gpio_status();
 		return 0;
-	}
+#elif defined(CONFIG_DM_GPIO)
+		return cmd_process_error(cmdtp, do_gpio_status(str_gpio));
+#else
+		goto show_usage;
 #endif
+	}
 
-	if (argc != 3)
- show_usage:
-		return CMD_RET_USAGE;
-	str_cmd = argv[1];
-	str_gpio = argv[2];
+	if (!str_gpio)
+		goto show_usage;
 
 	/* parse the behavior */
 	switch (*str_cmd) {
@@ -51,11 +141,23 @@ static int do_gpio(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 		default:  goto show_usage;
 	}
 
+#if defined(CONFIG_DM_GPIO)
+	/*
+	 * TODO(sjg@chromium.org): For now we must fit into the existing GPIO
+	 * framework, so we look up the name here and convert it to a GPIO number.
+	 * Once all GPIO drivers are converted to driver model, we can change the
+	 * code here to use the GPIO uclass interface instead of the numbered
+	 * GPIO compatibility layer.
+	 */
+	ret = gpio_lookup_name(str_gpio, NULL, NULL, &gpio);
+	if (ret)
+		return cmd_process_error(cmdtp, ret);
+#else
 	/* turn the gpio name into a gpio number */
 	gpio = name_to_gpio(str_gpio);
 	if (gpio < 0)
 		goto show_usage;
-
+#endif
 	/* grab the pin before we tweak it */
 	if (gpio_request(gpio, "cmd_gpio")) {
 		printf("gpio: requesting pin %u failed\n", gpio);
@@ -84,6 +186,7 @@ static int do_gpio(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 }
 
 U_BOOT_CMD(gpio, 3, 0, do_gpio,
-	"input/set/clear/toggle gpio pins",
+	"query and control gpio pins",
 	"<input|set|clear|toggle> <pin>\n"
-	"    - input/set/clear/toggle the specified pin");
+	"    - input/set/clear/toggle the specified pin\n"
+	"gpio status [<bank> | <pin>]");
diff --git a/common/cmd_gpt.c b/common/cmd_gpt.c
index a46f5cc343..e38422d792 100644
--- a/common/cmd_gpt.c
+++ b/common/cmd_gpt.c
@@ -11,7 +11,6 @@
 #include <common.h>
 #include <malloc.h>
 #include <command.h>
-#include <mmc.h>
 #include <part_efi.h>
 #include <exports.h>
 #include <linux/ctype.h>
@@ -30,30 +29,53 @@
  *
  * @return - zero on successful expand and env is set
  */
-static char extract_env(const char *str, char **env)
+static int extract_env(const char *str, char **env)
 {
+	int ret = -1;
 	char *e, *s;
+#ifdef CONFIG_RANDOM_UUID
+	char uuid_str[UUID_STR_LEN + 1];
+#endif
 
 	if (!str || strlen(str) < 4)
 		return -1;
 
-	if ((strncmp(str, "${", 2) == 0) && (str[strlen(str) - 1] == '}')) {
-		s = strdup(str);
-		if (s == NULL)
-			return -1;
-		memset(s + strlen(s) - 1, '\0', 1);
-		memmove(s, s + 2, strlen(s) - 1);
+	if (!((strncmp(str, "${", 2) == 0) && (str[strlen(str) - 1] == '}')))
+		return -1;
+
+	s = strdup(str);
+	if (s == NULL)
+		return -1;
+
+	memset(s + strlen(s) - 1, '\0', 1);
+	memmove(s, s + 2, strlen(s) - 1);
+
+	e = getenv(s);
+	if (e == NULL) {
+#ifdef CONFIG_RANDOM_UUID
+		debug("%s unset. ", str);
+		gen_rand_uuid_str(uuid_str, UUID_STR_FORMAT_STD);
+		setenv(s, uuid_str);
+
 		e = getenv(s);
-		free(s);
-		if (e == NULL) {
-			printf("Environmental '%s' not set\n", str);
-			return -1; /* env not set */
+		if (e) {
+			debug("Set to random.\n");
+			ret = 0;
+		} else {
+			debug("Can't get random UUID.\n");
 		}
-		*env = e;
-		return 0;
+#else
+		debug("%s unset.\n", str);
+#endif
+	} else {
+		debug("%s get from environment.\n", str);
+		ret = 0;
 	}
 
-	return -1;
+	*env = e;
+	free(s);
+
+	return ret;
 }
 
 /**
@@ -122,7 +144,7 @@ static int set_gpt_info(block_dev_desc_t *dev_desc,
 	int errno = 0;
 	uint64_t size_ll, start_ll;
 
-	debug("%s: MMC lba num: 0x%x %d\n", __func__,
+	debug("%s:  lba num: 0x%x %d\n", __func__,
 	      (unsigned int)dev_desc->lba, (unsigned int)dev_desc->lba);
 
 	if (str_part == NULL)
@@ -235,25 +257,18 @@ err:
 	return errno;
 }
 
-static int gpt_mmc_default(int dev, const char *str_part)
+static int gpt_default(block_dev_desc_t *blk_dev_desc, const char *str_part)
 {
 	int ret;
 	char *str_disk_guid;
 	u8 part_count = 0;
 	disk_partition_t *partitions = NULL;
 
-	struct mmc *mmc = find_mmc_device(dev);
-
-	if (mmc == NULL) {
-		printf("%s: mmc dev %d NOT available\n", __func__, dev);
-		return CMD_RET_FAILURE;
-	}
-
 	if (!str_part)
 		return -1;
 
 	/* fill partitions */
-	ret = set_gpt_info(&mmc->block_dev, str_part,
+	ret = set_gpt_info(blk_dev_desc, str_part,
 			&str_disk_guid, &partitions, &part_count);
 	if (ret) {
 		if (ret == -1)
@@ -266,7 +281,7 @@ static int gpt_mmc_default(int dev, const char *str_part)
 	}
 
 	/* save partitions layout to disk */
-	gpt_restore(&mmc->block_dev, str_disk_guid, partitions, part_count);
+	gpt_restore(blk_dev_desc, str_disk_guid, partitions, part_count);
 	free(str_disk_guid);
 	free(partitions);
 
@@ -287,26 +302,35 @@ static int do_gpt(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 {
 	int ret = CMD_RET_SUCCESS;
 	int dev = 0;
-	char *pstr;
+	char *ep;
+	block_dev_desc_t *blk_dev_desc;
 
 	if (argc < 5)
 		return CMD_RET_USAGE;
 
 	/* command: 'write' */
 	if ((strcmp(argv[1], "write") == 0) && (argc == 5)) {
-		/* device: 'mmc' */
-		if (strcmp(argv[2], "mmc") == 0) {
-			/* check if 'dev' is a number */
-			for (pstr = argv[3]; *pstr != '\0'; pstr++)
-				if (!isdigit(*pstr)) {
-					printf("'%s' is not a number\n",
-						argv[3]);
-					return CMD_RET_USAGE;
-				}
-			dev = (int)simple_strtoul(argv[3], NULL, 10);
-			/* write to mmc */
-			if (gpt_mmc_default(dev, argv[4]))
-				return CMD_RET_FAILURE;
+		dev = (int)simple_strtoul(argv[3], &ep, 10);
+		if (!ep || ep[0] != '\0') {
+			printf("'%s' is not a number\n", argv[3]);
+			return CMD_RET_USAGE;
+		}
+		blk_dev_desc = get_dev(argv[2], dev);
+		if (!blk_dev_desc) {
+			printf("%s: %s dev %d NOT available\n",
+			       __func__, argv[2], dev);
+			return CMD_RET_FAILURE;
+		}
+
+		puts("Writing GPT: ");
+
+		ret = gpt_default(blk_dev_desc, argv[4]);
+		if (!ret) {
+			puts("success!\n");
+			return CMD_RET_SUCCESS;
+		} else {
+			puts("error!\n");
+			return CMD_RET_FAILURE;
 		}
 	} else {
 		return CMD_RET_USAGE;
diff --git a/common/cmd_immap.c b/common/cmd_immap.c
index bdf53a4dbb..1414f9ad55 100644
--- a/common/cmd_immap.c
+++ b/common/cmd_immap.c
@@ -12,13 +12,13 @@
 #include <common.h>
 #include <command.h>
 
-#if defined(CONFIG_8xx) || defined(CONFIG_8260)
+#if defined(CONFIG_8xx) || defined(CONFIG_MPC8260)
 
 #if defined(CONFIG_8xx)
 #include <asm/8xx_immap.h>
 #include <commproc.h>
 #include <asm/iopin_8xx.h>
-#elif defined(CONFIG_8260)
+#elif defined(CONFIG_MPC8260)
 #include <asm/immap_8260.h>
 #include <asm/cpm_8260.h>
 #include <asm/iopin_8260.h>
@@ -40,7 +40,7 @@ do_siuinfo (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 
 #if defined(CONFIG_8xx)
 	volatile sysconf8xx_t *sc = &immap->im_siu_conf;
-#elif defined(CONFIG_8260)
+#elif defined(CONFIG_MPC8260)
 	volatile sysconf8260_t *sc = &immap->im_siu_conf;
 #endif
 
@@ -50,7 +50,7 @@ do_siuinfo (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 	printf ("SIPEND= %08x SIMASK= %08x\n", sc->sc_sipend, sc->sc_simask);
 	printf ("SIEL  = %08x SIVEC = %08x\n", sc->sc_siel, sc->sc_sivec);
 	printf ("TESR  = %08x SDCR  = %08x\n", sc->sc_tesr, sc->sc_sdcr);
-#elif defined(CONFIG_8260)
+#elif defined(CONFIG_MPC8260)
 	printf ("BCR   = %08x\n", sc->sc_bcr);
 	printf ("P_ACR =       %02x P_ALRH= %08x P_ALRL= %08x\n",
 		sc->sc_ppc_acr, sc->sc_ppc_alrh, sc->sc_ppc_alrl);
@@ -72,7 +72,7 @@ do_memcinfo (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 #if defined(CONFIG_8xx)
 	volatile memctl8xx_t *memctl = &immap->im_memctl;
 	int nbanks = 8;
-#elif defined(CONFIG_8260)
+#elif defined(CONFIG_MPC8260)
 	volatile memctl8260_t *memctl = &immap->im_memctl;
 	int nbanks = 12;
 #endif
@@ -92,19 +92,19 @@ do_memcinfo (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 	printf ("MAR   = %08x", memctl->memc_mar);
 #if defined(CONFIG_8xx)
 	printf (" MCR   = %08x\n", memctl->memc_mcr);
-#elif defined(CONFIG_8260)
+#elif defined(CONFIG_MPC8260)
 	putc ('\n');
 #endif
 	printf ("MAMR  = %08x MBMR  = %08x",
 		memctl->memc_mamr, memctl->memc_mbmr);
 #if defined(CONFIG_8xx)
 	printf ("\nMSTAT =     %04x\n", memctl->memc_mstat);
-#elif defined(CONFIG_8260)
+#elif defined(CONFIG_MPC8260)
 	printf (" MCMR  = %08x\n", memctl->memc_mcmr);
 #endif
 	printf ("MPTPR =     %04x MDR   = %08x\n",
 		memctl->memc_mptpr, memctl->memc_mdr);
-#if defined(CONFIG_8260)
+#if defined(CONFIG_MPC8260)
 	printf ("PSDMR = %08x LSDMR = %08x\n",
 		memctl->memc_psdmr, memctl->memc_lsdmr);
 	printf ("PURT  =       %02x PSRT  =       %02x\n",
@@ -123,7 +123,7 @@ do_sitinfo (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 	return 0;
 }
 
-#ifdef CONFIG_8260
+#ifdef CONFIG_MPC8260
 int
 do_icinfo (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 {
@@ -139,7 +139,7 @@ do_carinfo (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 
 #if defined(CONFIG_8xx)
 	volatile car8xx_t *car = &immap->im_clkrst;
-#elif defined(CONFIG_8260)
+#elif defined(CONFIG_MPC8260)
 	volatile car8260_t *car = &immap->im_clkrst;
 #endif
 
@@ -147,7 +147,7 @@ do_carinfo (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 	printf ("SCCR  = %08x\n", car->car_sccr);
 	printf ("PLPRCR= %08x\n", car->car_plprcr);
 	printf ("RSR   = %08x\n", car->car_rsr);
-#elif defined(CONFIG_8260)
+#elif defined(CONFIG_MPC8260)
 	printf ("SCCR  = %08x\n", car->car_sccr);
 	printf ("SCMR  = %08x\n", car->car_scmr);
 	printf ("RSR   = %08x\n", car->car_rsr);
@@ -207,7 +207,7 @@ static void binary (char *label, uint value, int nbits)
 #define PB_NB_ODR	16
 #define PC_NBITS	12
 #define PD_NBITS	13
-#elif defined(CONFIG_8260)
+#elif defined(CONFIG_MPC8260)
 #define PA_NBITS	32
 #define PA_NB_ODR	32
 #define PB_NBITS	28
@@ -224,7 +224,7 @@ do_iopinfo (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 #if defined(CONFIG_8xx)
 	volatile iop8xx_t *iop = &immap->im_ioport;
 	volatile ushort *l, *r;
-#elif defined(CONFIG_8260)
+#elif defined(CONFIG_MPC8260)
 	volatile iop8260_t *iop = &immap->im_ioport;
 	volatile uint *l, *r;
 #endif
@@ -240,7 +240,7 @@ do_iopinfo (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 #if defined(CONFIG_8xx)
 	l = &iop->iop_padir;
 	R = &immap->im_cpm.cp_pbdir;
-#elif defined(CONFIG_8260)
+#elif defined(CONFIG_MPC8260)
 	l = &iop->iop_pdira;
 	R = &iop->iop_pdirb;
 #endif
@@ -248,7 +248,7 @@ do_iopinfo (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 	binary ("PB_DIR", *R++, PB_NBITS);
 	binary ("PA_PAR", *l++, PA_NBITS);
 	binary ("PB_PAR", *R++, PB_NBITS);
-#if defined(CONFIG_8260)
+#if defined(CONFIG_MPC8260)
 	binary ("PA_SOR", *l++, PA_NBITS);
 	binary ("PB_SOR", *R++, PB_NBITS);
 #endif
@@ -266,7 +266,7 @@ do_iopinfo (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 #if defined(CONFIG_8xx)
 	l = &iop->iop_pcdir;
 	r = &iop->iop_pddir;
-#elif defined(CONFIG_8260)
+#elif defined(CONFIG_MPC8260)
 	l = &iop->iop_pdirc;
 	r = &iop->iop_pdird;
 #endif
@@ -278,7 +278,7 @@ do_iopinfo (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 	binary ("PC_SO ", *l++, PC_NBITS);
 	binary ("      ", 0, 0);
 	r++;
-#elif defined(CONFIG_8260)
+#elif defined(CONFIG_MPC8260)
 	binary ("PC_SOR", *l++, PC_NBITS);
 	binary ("PD_SOR", *r++, PD_NBITS);
 	binary ("PC_ODR", *l++, PC_NBITS);
@@ -436,7 +436,7 @@ static void prbrg (int n, uint val)
 
 #if defined(CONFIG_8xx)
 	ulong clock = gd->cpu_clk;
-#elif defined(CONFIG_8260)
+#elif defined(CONFIG_MPC8260)
 	ulong clock = gd->arch.brg_clk;
 #endif
 
@@ -489,7 +489,7 @@ do_brginfo (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 #if defined(CONFIG_8xx)
 	volatile cpm8xx_t *cp = &immap->im_cpm;
 	volatile uint *p = &cp->cp_brgc1;
-#elif defined(CONFIG_8260)
+#elif defined(CONFIG_MPC8260)
 	volatile uint *p = &immap->im_brgc1;
 #endif
 	int i = 1;
@@ -497,7 +497,7 @@ do_brginfo (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 	while (i <= 4)
 		prbrg (i++, *p++);
 
-#if defined(CONFIG_8260)
+#if defined(CONFIG_MPC8260)
 	p = &immap->im_brgc5;
 	while (i <= 8)
 		prbrg (i++, *p++);
@@ -514,7 +514,7 @@ do_i2cinfo (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 	volatile i2c8xx_t *i2c = &immap->im_i2c;
 	volatile cpm8xx_t *cp = &immap->im_cpm;
 	volatile iic_t *iip = (iic_t *) & cp->cp_dparam[PROFF_IIC];
-#elif defined(CONFIG_8260)
+#elif defined(CONFIG_MPC8260)
 	volatile i2c8260_t *i2c = &immap->im_i2c;
 	volatile iic_t *iip;
 	uint dpaddr;
@@ -614,7 +614,7 @@ U_BOOT_CMD(
 	""
 );
 
-#ifdef CONFIG_8260
+#ifdef CONFIG_MPC8260
 U_BOOT_CMD(
 	icinfo,	1,	1,	do_icinfo,
 	"print Interrupt Controller registers",
diff --git a/common/cmd_itest.c b/common/cmd_itest.c
index 29f8076f82..ae2527bfec 100644
--- a/common/cmd_itest.c
+++ b/common/cmd_itest.c
@@ -71,6 +71,19 @@ static char * evalstr(char *s)
 	/* if the parameter starts with a * then assume a string pointer else its a literal */
 	if (s[0] == '*') {
 		return (char *)simple_strtoul(&s[1], NULL, 16);
+	} else if (s[0] == '$') {
+		int i = 2;
+
+		if (s[1] != '{')
+			return NULL;
+
+		while (s[i] != '}') {
+			if (s[i] == 0)
+				return NULL;
+			i++;
+		}
+		s[i] = 0;
+		return  getenv((const char *)&s[2]);
 	} else {
 		return s;
 	}
diff --git a/common/cmd_log.c b/common/cmd_log.c
index 8164bdf488..38d0f5edfd 100644
--- a/common/cmd_log.c
+++ b/common/cmd_log.c
@@ -52,7 +52,7 @@ static char *lbuf;
 
 unsigned long __logbuffer_base(void)
 {
-	return CONFIG_SYS_SDRAM_BASE + gd->ram_size - LOGBUFF_LEN;
+	return CONFIG_SYS_SDRAM_BASE + get_effective_memsize() - LOGBUFF_LEN;
 }
 unsigned long logbuffer_base(void)
 __attribute__((weak, alias("__logbuffer_base")));
diff --git a/common/cmd_lzmadec.c b/common/cmd_lzmadec.c
new file mode 100644
index 0000000000..7b0b3fdd90
--- /dev/null
+++ b/common/cmd_lzmadec.c
@@ -0,0 +1,52 @@
+/*
+ * (C) Copyright 2013 Patrice Bouchand <pbfwdlist_gmail_com>
+ * lzma uncompress command in Uboot
+ *
+ * made from existing cmd_unzip.c file of Uboot
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <command.h>
+#include <asm/io.h>
+
+#include <lzma/LzmaTools.h>
+
+static int do_lzmadec(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
+{
+	unsigned long src, dst;
+	unsigned long src_len = ~0UL, dst_len = ~0UL;
+	int ret;
+
+	switch (argc) {
+	case 4:
+		dst_len = simple_strtoul(argv[3], NULL, 16);
+		/* fall through */
+	case 3:
+		src = simple_strtoul(argv[1], NULL, 16);
+		dst = simple_strtoul(argv[2], NULL, 16);
+		break;
+	default:
+		return CMD_RET_USAGE;
+	}
+
+	ret = lzmaBuffToBuffDecompress(map_sysmem(dst, dst_len), &src_len,
+				       map_sysmem(src, 0), dst_len);
+
+	if (ret != SZ_OK)
+		return 1;
+	printf("Uncompressed size: %ld = 0x%lX\n", src_len, src_len);
+	setenv_hex("filesize", src_len);
+
+	return 0;
+}
+
+U_BOOT_CMD(
+	lzmadec,    4,    1,    do_lzmadec,
+	"lzma uncompress a memory region",
+	"srcaddr dstaddr [dstsize]"
+);
diff --git a/common/cmd_mdio.c b/common/cmd_mdio.c
index 65a1f10a9f..fb13d05075 100644
--- a/common/cmd_mdio.c
+++ b/common/cmd_mdio.c
@@ -41,9 +41,11 @@ static int extract_range(char *input, int *plo, int *phi)
 	return 0;
 }
 
-static int mdio_write_ranges(struct mii_dev *bus, int addrlo,
+static int mdio_write_ranges(struct phy_device *phydev, struct mii_dev *bus,
+			     int addrlo,
 			     int addrhi, int devadlo, int devadhi,
-			     int reglo, int reghi, unsigned short data)
+			     int reglo, int reghi, unsigned short data,
+			     int extended)
 {
 	int addr, devad, reg;
 	int err = 0;
@@ -51,7 +53,12 @@ static int mdio_write_ranges(struct mii_dev *bus, int addrlo,
 	for (addr = addrlo; addr <= addrhi; addr++) {
 		for (devad = devadlo; devad <= devadhi; devad++) {
 			for (reg = reglo; reg <= reghi; reg++) {
-				err = bus->write(bus, addr, devad, reg, data);
+				if (!extended)
+					err = bus->write(bus, addr, devad,
+							 reg, data);
+				else
+					err = phydev->drv->writeext(phydev,
+							addr, devad, reg, data);
 
 				if (err)
 					goto err_out;
@@ -63,9 +70,10 @@ err_out:
 	return err;
 }
 
-static int mdio_read_ranges(struct mii_dev *bus, int addrlo,
+static int mdio_read_ranges(struct phy_device *phydev, struct mii_dev *bus,
+			    int addrlo,
 			    int addrhi, int devadlo, int devadhi,
-			    int reglo, int reghi)
+			    int reglo, int reghi, int extended)
 {
 	int addr, devad, reg;
 
@@ -77,7 +85,12 @@ static int mdio_read_ranges(struct mii_dev *bus, int addrlo,
 			for (reg = reglo; reg <= reghi; reg++) {
 				int val;
 
-				val = bus->read(bus, addr, devad, reg);
+				if (!extended)
+					val = bus->read(bus, addr, devad, reg);
+				else
+					val = phydev->drv->readext(phydev, addr,
+						devad, reg);
+
 				if (val < 0) {
 					printf("Error\n");
 
@@ -126,9 +139,10 @@ static int extract_reg_range(char *input, int *devadlo, int *devadhi,
 }
 
 static int extract_phy_range(char *const argv[], int argc, struct mii_dev **bus,
+			     struct phy_device **phydev,
 			     int *addrlo, int *addrhi)
 {
-	struct phy_device *phydev;
+	struct phy_device *dev = *phydev;
 
 	if ((argc < 1) || (argc > 2))
 		return -1;
@@ -154,11 +168,11 @@ static int extract_phy_range(char *const argv[], int argc, struct mii_dev **bus,
 	 * device by the given name.  If none are found, we call
 	 * extract_range() on the string, and see if it's an address range.
 	 */
-	phydev = mdio_phydev_for_ethname(argv[0]);
+	dev = mdio_phydev_for_ethname(argv[0]);
 
-	if (phydev) {
-		*addrlo = *addrhi = phydev->addr;
-		*bus = phydev->bus;
+	if (dev) {
+		*addrlo = *addrhi = dev->addr;
+		*bus = dev->bus;
 
 		return 0;
 	}
@@ -175,6 +189,8 @@ static int do_mdio(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 	unsigned short	data;
 	int pos = argc - 1;
 	struct mii_dev *bus;
+	struct phy_device *phydev = NULL;
+	int extended = 0;
 
 	if (argc < 2)
 		return CMD_RET_USAGE;
@@ -197,6 +213,29 @@ static int do_mdio(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 	if (flag & CMD_FLAG_REPEAT)
 		op[0] = last_op[0];
 
+	if (strlen(argv[1]) > 1) {
+		op[1] = argv[1][1];
+		if (op[1] == 'x') {
+			phydev = mdio_phydev_for_ethname(argv[2]);
+
+			if (phydev) {
+				addrlo = phydev->addr;
+				addrhi = addrlo;
+				bus = phydev->bus;
+				extended = 1;
+			} else {
+				return -1;
+			}
+
+			if (!phydev->drv ||
+			    (!phydev->drv->writeext && (op[0] == 'w')) ||
+			    (!phydev->drv->readext && (op[0] == 'r'))) {
+				puts("PHY does not have extended functions\n");
+				return -1;
+			}
+		}
+	}
+
 	switch (op[0]) {
 	case 'w':
 		if (pos > 1)
@@ -210,7 +249,7 @@ static int do_mdio(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 	default:
 		if (pos > 1)
 			if (extract_phy_range(&(argv[2]), pos - 1, &bus,
-					&addrlo, &addrhi))
+					&phydev, &addrlo, &addrhi))
 				return -1;
 
 		break;
@@ -227,13 +266,13 @@ static int do_mdio(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 
 	switch (op[0]) {
 	case 'w':
-		mdio_write_ranges(bus, addrlo, addrhi, devadlo, devadhi,
-				reglo, reghi, data);
+		mdio_write_ranges(phydev, bus, addrlo, addrhi, devadlo, devadhi,
+				  reglo, reghi, data, extended);
 		break;
 
 	case 'r':
-		mdio_read_ranges(bus, addrlo, addrhi, devadlo, devadhi,
-				reglo, reghi);
+		mdio_read_ranges(phydev, bus, addrlo, addrhi, devadlo, devadhi,
+				 reglo, reghi, extended);
 		break;
 	}
 
@@ -262,6 +301,10 @@ U_BOOT_CMD(
 		"read PHY's register at <devad>.<reg>\n"
 	"mdio write <phydev> [<devad>.]<reg> <data> - "
 		"write PHY's register at <devad>.<reg>\n"
+	"mdio rx <phydev> [<devad>.]<reg> - "
+		"read PHY's extended register at <devad>.<reg>\n"
+	"mdio wx <phydev> [<devad>.]<reg> <data> - "
+		"write PHY's extended register at <devad>.<reg>\n"
 	"<phydev> may be:\n"
 	"   <busname>  <addr>\n"
 	"   <addr>\n"
diff --git a/common/cmd_mem.c b/common/cmd_mem.c
index c3aab3d4b5..5b03c2d5b1 100644
--- a/common/cmd_mem.c
+++ b/common/cmd_mem.c
@@ -41,7 +41,7 @@ static	ulong	base_address = 0;
 /* Memory Display
  *
  * Syntax:
- *	md{.b, .w, .l} {addr} {len}
+ *	md{.b, .w, .l, .q} {addr} {len}
  */
 #define DISP_LINE_LEN	16
 static int do_mem_md(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
@@ -155,7 +155,12 @@ static int do_mem_nm(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 
 static int do_mem_mw(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 {
-	ulong	addr, writeval, count;
+#ifdef CONFIG_SYS_SUPPORT_64BIT_DATA
+	u64 writeval;
+#else
+	ulong writeval;
+#endif
+	ulong	addr, count;
 	int	size;
 	void *buf;
 	ulong bytes;
@@ -175,7 +180,11 @@ static int do_mem_mw(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 
 	/* Get the value to write.
 	*/
+#ifdef CONFIG_SYS_SUPPORT_64BIT_DATA
+	writeval = simple_strtoull(argv[2], NULL, 16);
+#else
 	writeval = simple_strtoul(argv[2], NULL, 16);
+#endif
 
 	/* Count ? */
 	if (argc == 4) {
@@ -188,11 +197,15 @@ static int do_mem_mw(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 	buf = map_sysmem(addr, bytes);
 	while (count-- > 0) {
 		if (size == 4)
-			*((ulong *)buf) = (ulong)writeval;
+			*((u32 *)buf) = (u32)writeval;
+#ifdef CONFIG_SYS_SUPPORT_64BIT_DATA
+		else if (size == 8)
+			*((u64 *)buf) = (u64)writeval;
+#endif
 		else if (size == 2)
-			*((ushort *)buf) = (ushort)writeval;
+			*((u16 *)buf) = (u16)writeval;
 		else
-			*((u_char *)buf) = (u_char)writeval;
+			*((u8 *)buf) = (u8)writeval;
 		buf += size;
 	}
 	unmap_sysmem(buf);
@@ -262,6 +275,11 @@ static int do_mem_cmp(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 	int     rcode = 0;
 	const char *type;
 	const void *buf1, *buf2, *base;
+#ifdef CONFIG_SYS_SUPPORT_64BIT_DATA
+	u64 word1, word2;
+#else
+	ulong word1, word2;
+#endif
 
 	if (argc != 4)
 		return CMD_RET_USAGE;
@@ -270,7 +288,9 @@ static int do_mem_cmp(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 	*/
 	if ((size = cmd_get_data_size(argv[0], 4)) < 0)
 		return 1;
-	type = size == 4 ? "word" : size == 2 ? "halfword" : "byte";
+	type = size == 8 ? "double word" :
+	       size == 4 ? "word" :
+	       size == 2 ? "halfword" : "byte";
 
 	addr1 = simple_strtoul(argv[1], NULL, 16);
 	addr1 += base_address;
@@ -298,23 +318,32 @@ static int do_mem_cmp(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 	base = buf1 = map_sysmem(addr1, bytes);
 	buf2 = map_sysmem(addr2, bytes);
 	for (ngood = 0; ngood < count; ++ngood) {
-		ulong word1, word2;
 		if (size == 4) {
-			word1 = *(ulong *)buf1;
-			word2 = *(ulong *)buf2;
+			word1 = *(u32 *)buf1;
+			word2 = *(u32 *)buf2;
+#ifdef CONFIG_SYS_SUPPORT_64BIT_DATA
+		} else if (size == 8) {
+			word1 = *(u64 *)buf1;
+			word2 = *(u64 *)buf2;
+#endif
 		} else if (size == 2) {
-			word1 = *(ushort *)buf1;
-			word2 = *(ushort *)buf2;
+			word1 = *(u16 *)buf1;
+			word2 = *(u16 *)buf2;
 		} else {
-			word1 = *(u_char *)buf1;
-			word2 = *(u_char *)buf2;
+			word1 = *(u8 *)buf1;
+			word2 = *(u8 *)buf2;
 		}
 		if (word1 != word2) {
 			ulong offset = buf1 - base;
-
+#ifdef CONFIG_SYS_SUPPORT_64BIT_DATA
+			printf("%s at 0x%p (%#0*llx) != %s at 0x%p (%#0*llx)\n",
+			       type, (void *)(addr1 + offset), size, word1,
+			       type, (void *)(addr2 + offset), size, word2);
+#else
 			printf("%s at 0x%08lx (%#0*lx) != %s at 0x%08lx (%#0*lx)\n",
 				type, (ulong)(addr1 + offset), size, word1,
 				type, (ulong)(addr2 + offset), size, word2);
+#endif
 			rcode = 1;
 			break;
 		}
@@ -433,11 +462,15 @@ static int do_mem_cp(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 	src = map_sysmem(addr, bytes);
 	while (count-- > 0) {
 		if (size == 4)
-			*((ulong *)buf) = *((ulong  *)src);
+			*((u32 *)buf) = *((u32  *)src);
+#ifdef CONFIG_SYS_SUPPORT_64BIT_DATA
+		else if (size == 8)
+			*((u64 *)buf) = *((u64 *)src);
+#endif
 		else if (size == 2)
-			*((ushort *)buf) = *((ushort *)src);
+			*((u16 *)buf) = *((u16 *)src);
 		else
-			*((u_char *)buf) = *((u_char *)src);
+			*((u8 *)buf) = *((u8 *)src);
 		src += size;
 		buf += size;
 
@@ -467,9 +500,12 @@ static int do_mem_loop(cmd_tbl_t *cmdtp, int flag, int argc,
 {
 	ulong	addr, length, i, bytes;
 	int	size;
-	volatile uint	*longp;
-	volatile ushort *shortp;
-	volatile u_char	*cp;
+#ifdef CONFIG_SYS_SUPPORT_64BIT_DATA
+	volatile u64 *llp;
+#endif
+	volatile u32 *longp;
+	volatile u16 *shortp;
+	volatile u8 *cp;
 	const void *buf;
 
 	if (argc < 3)
@@ -497,24 +533,41 @@ static int do_mem_loop(cmd_tbl_t *cmdtp, int flag, int argc,
 	 * If we have only one object, just run infinite loops.
 	 */
 	if (length == 1) {
+#ifdef CONFIG_SYS_SUPPORT_64BIT_DATA
+		if (size == 8) {
+			llp = (u64 *)buf;
+			for (;;)
+				i = *llp;
+		}
+#endif
 		if (size == 4) {
-			longp = (uint *)buf;
+			longp = (u32 *)buf;
 			for (;;)
 				i = *longp;
 		}
 		if (size == 2) {
-			shortp = (ushort *)buf;
+			shortp = (u16 *)buf;
 			for (;;)
 				i = *shortp;
 		}
-		cp = (u_char *)buf;
+		cp = (u8 *)buf;
 		for (;;)
 			i = *cp;
 	}
 
+#ifdef CONFIG_SYS_SUPPORT_64BIT_DATA
+	if (size == 8) {
+		for (;;) {
+			llp = (u64 *)buf;
+			i = length;
+			while (i-- > 0)
+				*llp++;
+		}
+	}
+#endif
 	if (size == 4) {
 		for (;;) {
-			longp = (uint *)buf;
+			longp = (u32 *)buf;
 			i = length;
 			while (i-- > 0)
 				*longp++;
@@ -522,14 +575,14 @@ static int do_mem_loop(cmd_tbl_t *cmdtp, int flag, int argc,
 	}
 	if (size == 2) {
 		for (;;) {
-			shortp = (ushort *)buf;
+			shortp = (u16 *)buf;
 			i = length;
 			while (i-- > 0)
 				*shortp++;
 		}
 	}
 	for (;;) {
-		cp = (u_char *)buf;
+		cp = (u8 *)buf;
 		i = length;
 		while (i-- > 0)
 			*cp++;
@@ -542,11 +595,17 @@ static int do_mem_loop(cmd_tbl_t *cmdtp, int flag, int argc,
 #ifdef CONFIG_LOOPW
 int do_mem_loopw (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 {
-	ulong	addr, length, i, data, bytes;
+	ulong	addr, length, i, bytes;
 	int	size;
-	volatile uint	*longp;
-	volatile ushort *shortp;
-	volatile u_char	*cp;
+#ifdef CONFIG_SYS_SUPPORT_64BIT_DATA
+	volatile u64 *llp;
+	u64 data;
+#else
+	ulong	data;
+#endif
+	volatile u32 *longp;
+	volatile u16 *shortp;
+	volatile u8 *cp;
 	void *buf;
 
 	if (argc < 4)
@@ -568,7 +627,11 @@ int do_mem_loopw (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 	length = simple_strtoul(argv[2], NULL, 16);
 
 	/* data to write */
+#ifdef CONFIG_SYS_SUPPORT_64BIT_DATA
+	data = simple_strtoull(argv[3], NULL, 16);
+#else
 	data = simple_strtoul(argv[3], NULL, 16);
+#endif
 
 	bytes = size * length;
 	buf = map_sysmem(addr, bytes);
@@ -577,24 +640,41 @@ int do_mem_loopw (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 	 * If we have only one object, just run infinite loops.
 	 */
 	if (length == 1) {
+#ifdef CONFIG_SYS_SUPPORT_64BIT_DATA
+		if (size == 8) {
+			llp = (u64 *)buf;
+			for (;;)
+				*llp = data;
+		}
+#endif
 		if (size == 4) {
-			longp = (uint *)buf;
+			longp = (u32 *)buf;
 			for (;;)
 				*longp = data;
-					}
+		}
 		if (size == 2) {
-			shortp = (ushort *)buf;
+			shortp = (u16 *)buf;
 			for (;;)
 				*shortp = data;
 		}
-		cp = (u_char *)buf;
+		cp = (u8 *)buf;
 		for (;;)
 			*cp = data;
 	}
 
+#ifdef CONFIG_SYS_SUPPORT_64BIT_DATA
+	if (size == 8) {
+		for (;;) {
+			llp = (u64 *)buf;
+			i = length;
+			while (i-- > 0)
+				*llp++ = data;
+		}
+	}
+#endif
 	if (size == 4) {
 		for (;;) {
-			longp = (uint *)buf;
+			longp = (u32 *)buf;
 			i = length;
 			while (i-- > 0)
 				*longp++ = data;
@@ -602,14 +682,14 @@ int do_mem_loopw (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 	}
 	if (size == 2) {
 		for (;;) {
-			shortp = (ushort *)buf;
+			shortp = (u16 *)buf;
 			i = length;
 			while (i-- > 0)
 				*shortp++ = data;
 		}
 	}
 	for (;;) {
-		cp = (u_char *)buf;
+		cp = (u8 *)buf;
 		i = length;
 		while (i-- > 0)
 			*cp++ = data;
@@ -746,7 +826,8 @@ static ulong mem_test_alt(vu_long *buf, ulong start_addr, ulong end_addr,
 		if (temp != pattern) {
 			printf("\nFAILURE: Address bit stuck high @ 0x%.8lx:"
 				" expected 0x%.8lx, actual 0x%.8lx\n",
-				start_addr + offset, pattern, temp);
+				start_addr + offset*sizeof(vu_long),
+				pattern, temp);
 			errs++;
 			if (ctrlc())
 				return -1;
@@ -767,7 +848,8 @@ static ulong mem_test_alt(vu_long *buf, ulong start_addr, ulong end_addr,
 				printf("\nFAILURE: Address bit stuck low or"
 					" shorted @ 0x%.8lx: expected 0x%.8lx,"
 					" actual 0x%.8lx\n",
-					start_addr + offset, pattern, temp);
+					start_addr + offset*sizeof(vu_long),
+					pattern, temp);
 				errs++;
 				if (ctrlc())
 					return -1;
@@ -807,7 +889,8 @@ static ulong mem_test_alt(vu_long *buf, ulong start_addr, ulong end_addr,
 		if (temp != pattern) {
 			printf("\nFAILURE (read/write) @ 0x%.8lx:"
 				" expected 0x%.8lx, actual 0x%.8lx)\n",
-				start_addr + offset, pattern, temp);
+				start_addr + offset*sizeof(vu_long),
+				pattern, temp);
 			errs++;
 			if (ctrlc())
 				return -1;
@@ -827,7 +910,8 @@ static ulong mem_test_alt(vu_long *buf, ulong start_addr, ulong end_addr,
 		if (temp != anti_pattern) {
 			printf("\nFAILURE (read/write): @ 0x%.8lx:"
 				" expected 0x%.8lx, actual 0x%.8lx)\n",
-				start_addr + offset, anti_pattern, temp);
+				start_addr + offset*sizeof(vu_long),
+				anti_pattern, temp);
 			errs++;
 			if (ctrlc())
 				return -1;
@@ -885,7 +969,7 @@ static ulong mem_test_quick(vu_long *buf, ulong start_addr, ulong end_addr,
 
 			printf("\nMem error @ 0x%08X: "
 				"found %08lX, expected %08lX\n",
-				(uint)(uintptr_t)(start_addr + offset),
+				(uint)(uintptr_t)(start_addr + offset*sizeof(vu_long)),
 				readback, val);
 			errs++;
 			if (ctrlc())
@@ -994,13 +1078,18 @@ static int do_mem_mtest(cmd_tbl_t *cmdtp, int flag, int argc,
 /* Modify memory.
  *
  * Syntax:
- *	mm{.b, .w, .l} {addr}
- *	nm{.b, .w, .l} {addr}
+ *	mm{.b, .w, .l, .q} {addr}
+ *	nm{.b, .w, .l, .q} {addr}
  */
 static int
 mod_mem(cmd_tbl_t *cmdtp, int incrflag, int flag, int argc, char * const argv[])
 {
-	ulong	addr, i;
+	ulong	addr;
+#ifdef CONFIG_SYS_SUPPORT_64BIT_DATA
+	u64 i;
+#else
+	ulong i;
+#endif
 	int	nbytes, size;
 	void *ptr = NULL;
 
@@ -1050,11 +1139,15 @@ mod_mem(cmd_tbl_t *cmdtp, int incrflag, int flag, int argc, char * const argv[])
 		ptr = map_sysmem(addr, size);
 		printf("%08lx:", addr);
 		if (size == 4)
-			printf(" %08x", *((uint *)ptr));
+			printf(" %08x", *((u32 *)ptr));
+#ifdef CONFIG_SYS_SUPPORT_64BIT_DATA
+		else if (size == 8)
+			printf(" %016llx", *((u64 *)ptr));
+#endif
 		else if (size == 2)
-			printf(" %04x", *((ushort *)ptr));
+			printf(" %04x", *((u16 *)ptr));
 		else
-			printf(" %02x", *((u_char *)ptr));
+			printf(" %02x", *((u8 *)ptr));
 
 		nbytes = readline (" ? ");
 		if (nbytes == 0 || (nbytes == 1 && console_buffer[0] == '-')) {
@@ -1075,7 +1168,11 @@ mod_mem(cmd_tbl_t *cmdtp, int incrflag, int flag, int argc, char * const argv[])
 #endif
 		else {
 			char *endp;
+#ifdef CONFIG_SYS_SUPPORT_64BIT_DATA
+			i = simple_strtoull(console_buffer, &endp, 16);
+#else
 			i = simple_strtoul(console_buffer, &endp, 16);
+#endif
 			nbytes = endp - console_buffer;
 			if (nbytes) {
 #ifdef CONFIG_BOOT_RETRY_TIME
@@ -1084,11 +1181,15 @@ mod_mem(cmd_tbl_t *cmdtp, int incrflag, int flag, int argc, char * const argv[])
 				reset_cmd_timeout();
 #endif
 				if (size == 4)
-					*((uint *)ptr) = i;
+					*((u32 *)ptr) = i;
+#ifdef CONFIG_SYS_SUPPORT_64BIT_DATA
+				else if (size == 8)
+					*((u64 *)ptr) = i;
+#endif
 				else if (size == 2)
-					*((ushort *)ptr) = i;
+					*((u16 *)ptr) = i;
 				else
-					*((u_char *)ptr) = i;
+					*((u8 *)ptr) = i;
 				if (incrflag)
 					addr += size;
 			}
@@ -1132,39 +1233,63 @@ static int do_mem_crc(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 U_BOOT_CMD(
 	md,	3,	1,	do_mem_md,
 	"memory display",
+#ifdef CONFIG_SYS_SUPPORT_64BIT_DATA
+	"[.b, .w, .l, .q] address [# of objects]"
+#else
 	"[.b, .w, .l] address [# of objects]"
+#endif
 );
 
 
 U_BOOT_CMD(
 	mm,	2,	1,	do_mem_mm,
 	"memory modify (auto-incrementing address)",
+#ifdef CONFIG_SYS_SUPPORT_64BIT_DATA
+	"[.b, .w, .l, .q] address"
+#else
 	"[.b, .w, .l] address"
+#endif
 );
 
 
 U_BOOT_CMD(
 	nm,	2,	1,	do_mem_nm,
 	"memory modify (constant address)",
+#ifdef CONFIG_SYS_SUPPORT_64BIT_DATA
+	"[.b, .w, .l, .q] address"
+#else
 	"[.b, .w, .l] address"
+#endif
 );
 
 U_BOOT_CMD(
 	mw,	4,	1,	do_mem_mw,
 	"memory write (fill)",
+#ifdef CONFIG_SYS_SUPPORT_64BIT_DATA
+	"[.b, .w, .l, .q] address value [count]"
+#else
 	"[.b, .w, .l] address value [count]"
+#endif
 );
 
 U_BOOT_CMD(
 	cp,	4,	1,	do_mem_cp,
 	"memory copy",
+#ifdef CONFIG_SYS_SUPPORT_64BIT_DATA
+	"[.b, .w, .l, .q] source target count"
+#else
 	"[.b, .w, .l] source target count"
+#endif
 );
 
 U_BOOT_CMD(
 	cmp,	4,	1,	do_mem_cmp,
 	"memory compare",
+#ifdef CONFIG_SYS_SUPPORT_64BIT_DATA
+	"[.b, .w, .l, .q] addr1 addr2 count"
+#else
 	"[.b, .w, .l] addr1 addr2 count"
+#endif
 );
 
 #ifdef CONFIG_CMD_CRC32
@@ -1216,14 +1341,22 @@ U_BOOT_CMD(
 U_BOOT_CMD(
 	loop,	3,	1,	do_mem_loop,
 	"infinite loop on address range",
+#ifdef CONFIG_SYS_SUPPORT_64BIT_DATA
+	"[.b, .w, .l, .q] address number_of_objects"
+#else
 	"[.b, .w, .l] address number_of_objects"
+#endif
 );
 
 #ifdef CONFIG_LOOPW
 U_BOOT_CMD(
 	loopw,	4,	1,	do_mem_loopw,
 	"infinite write loop on address range",
+#ifdef CONFIG_SYS_SUPPORT_64BIT_DATA
+	"[.b, .w, .l, .q] address number_of_objects data_to_write"
+#else
 	"[.b, .w, .l] address number_of_objects data_to_write"
+#endif
 );
 #endif /* CONFIG_LOOPW */
 
@@ -1239,13 +1372,21 @@ U_BOOT_CMD(
 U_BOOT_CMD(
 	mdc,	4,	1,	do_mem_mdc,
 	"memory display cyclic",
+#ifdef CONFIG_SYS_SUPPORT_64BIT_DATA
+	"[.b, .w, .l, .q] address count delay(ms)"
+#else
 	"[.b, .w, .l] address count delay(ms)"
+#endif
 );
 
 U_BOOT_CMD(
 	mwc,	4,	1,	do_mem_mwc,
 	"memory write cyclic",
+#ifdef CONFIG_SYS_SUPPORT_64BIT_DATA
+	"[.b, .w, .l, .q] address value delay(ms)"
+#else
 	"[.b, .w, .l] address value delay(ms)"
+#endif
 );
 #endif /* CONFIG_MX_CYCLIC */
 
diff --git a/common/cmd_mii.c b/common/cmd_mii.c
index d3dd6b1c9e..b82a7ce612 100644
--- a/common/cmd_mii.c
+++ b/common/cmd_mii.c
@@ -78,9 +78,9 @@ static const MII_field_desc_t reg_3_desc_tbl[] = {
 
 static const MII_field_desc_t reg_4_desc_tbl[] = {
 	{ 15, 15, 0x01, "next page able"               },
-	{ 14, 14, 0x01, "reserved"                     },
+	{ 14, 14, 0x01, "(reserved)"                   },
 	{ 13, 13, 0x01, "remote fault"                 },
-	{ 12, 12, 0x01, "reserved"                     },
+	{ 12, 12, 0x01, "(reserved)"                   },
 	{ 11, 11, 0x01, "asymmetric pause"             },
 	{ 10, 10, 0x01, "pause enable"                 },
 	{  9,  9, 0x01, "100BASE-T4 able"              },
diff --git a/common/cmd_mmc.c b/common/cmd_mmc.c
index 67a94a7468..c1916c9b56 100644
--- a/common/cmd_mmc.c
+++ b/common/cmd_mmc.c
@@ -79,7 +79,7 @@ enum mmc_state {
 };
 static void print_mmcinfo(struct mmc *mmc)
 {
-	printf("Device: %s\n", mmc->name);
+	printf("Device: %s\n", mmc->cfg->name);
 	printf("Manufacturer ID: %x\n", mmc->cid[0] >> 24);
 	printf("OEM: %x\n", (mmc->cid[0] >> 8) & 0xffff);
 	printf("Name: %c%c%c%c%c \n", mmc->cid[0] & 0xff,
@@ -131,36 +131,6 @@ U_BOOT_CMD(
 	"- display info of the current MMC device"
 );
 
-#ifdef CONFIG_SUPPORT_EMMC_BOOT
-static int boot_part_access(struct mmc *mmc, u8 ack, u8 part_num, u8 access)
-{
-	int err;
-	err = mmc_boot_part_access(mmc, ack, part_num, access);
-
-	if ((err == 0) && (access != 0)) {
-		printf("\t\t\t!!!Notice!!!\n");
-
-		printf("!You must close EMMC boot Partition");
-		printf("after all images are written\n");
-
-		printf("!EMMC boot partition has continuity");
-		printf("at image writing time.\n");
-
-		printf("!So, do not close the boot partition");
-		printf("before all images are written.\n");
-		return 0;
-	} else if ((err == 0) && (access == 0))
-		return 0;
-	else if ((err != 0) && (access != 0)) {
-		printf("EMMC boot partition-%d OPEN Failed.\n", part_num);
-		return 1;
-	} else {
-		printf("EMMC boot partition-%d CLOSE Failed.\n", part_num);
-		return 1;
-	}
-}
-#endif
-
 static int do_mmcops(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 {
 	enum mmc_state state;
@@ -195,7 +165,7 @@ static int do_mmcops(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 			return 1;
 		else
 			return 0;
-	} else if (strncmp(argv[1], "part", 4) == 0) {
+	} else if (strcmp(argv[1], "part") == 0) {
 		block_dev_desc_t *mmc_dev;
 		struct mmc *mmc;
 
@@ -273,15 +243,16 @@ static int do_mmcops(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 
 		return 0;
 #ifdef CONFIG_SUPPORT_EMMC_BOOT
-	} else if ((strcmp(argv[1], "open") == 0) ||
-			(strcmp(argv[1], "close") == 0)) {
+	} else if (strcmp(argv[1], "partconf") == 0) {
 		int dev;
 		struct mmc *mmc;
-		u8 part_num, access = 0;
+		u8 ack, part_num, access;
 
-		if (argc == 4) {
+		if (argc == 6) {
 			dev = simple_strtoul(argv[2], NULL, 10);
-			part_num = simple_strtoul(argv[3], NULL, 10);
+			ack = simple_strtoul(argv[3], NULL, 10);
+			part_num = simple_strtoul(argv[4], NULL, 10);
+			access = simple_strtoul(argv[5], NULL, 10);
 		} else {
 			return CMD_RET_USAGE;
 		}
@@ -293,32 +264,53 @@ static int do_mmcops(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 		}
 
 		if (IS_SD(mmc)) {
-			printf("SD device cannot be opened/closed\n");
+			puts("PARTITION_CONFIG only exists on eMMC\n");
 			return 1;
 		}
 
-		if ((part_num <= 0) || (part_num > MMC_NUM_BOOT_PARTITION)) {
-			printf("Invalid boot partition number:\n");
-			printf("Boot partition number cannot be <= 0\n");
-			printf("EMMC44 supports only 2 boot partitions\n");
+		/* acknowledge to be sent during boot operation */
+		return mmc_set_part_conf(mmc, ack, part_num, access);
+	} else if (strcmp(argv[1], "bootbus") == 0) {
+		int dev;
+		struct mmc *mmc;
+		u8 width, reset, mode;
+
+		if (argc == 6) {
+			dev = simple_strtoul(argv[2], NULL, 10);
+			width = simple_strtoul(argv[3], NULL, 10);
+			reset = simple_strtoul(argv[4], NULL, 10);
+			mode = simple_strtoul(argv[5], NULL, 10);
+		} else {
+			return CMD_RET_USAGE;
+		}
+
+		mmc = find_mmc_device(dev);
+		if (!mmc) {
+			printf("no mmc device at slot %x\n", dev);
 			return 1;
 		}
 
-		if (strcmp(argv[1], "open") == 0)
-			access = part_num; /* enable R/W access to boot part*/
-		else
-			access = 0; /* No access to boot partition */
+		if (IS_SD(mmc)) {
+			puts("BOOT_BUS_WIDTH only exists on eMMC\n");
+			return 1;
+		}
 
 		/* acknowledge to be sent during boot operation */
-		return boot_part_access(mmc, 1, part_num, access);
-
-	} else if (strcmp(argv[1], "bootpart") == 0) {
+		return mmc_set_boot_bus_width(mmc, width, reset, mode);
+	} else if (strcmp(argv[1], "bootpart-resize") == 0) {
 		int dev;
-		dev = simple_strtoul(argv[2], NULL, 10);
+		struct mmc *mmc;
+		u32 bootsize, rpmbsize;
+
+		if (argc == 5) {
+			dev = simple_strtoul(argv[2], NULL, 10);
+			bootsize = simple_strtoul(argv[3], NULL, 10);
+			rpmbsize = simple_strtoul(argv[4], NULL, 10);
+		} else {
+			return CMD_RET_USAGE;
+		}
 
-		u32 bootsize = simple_strtoul(argv[3], NULL, 10);
-		u32 rpmbsize = simple_strtoul(argv[4], NULL, 10);
-		struct mmc *mmc = find_mmc_device(dev);
+		mmc = find_mmc_device(dev);
 		if (!mmc) {
 			printf("no mmc device at slot %x\n", dev);
 			return 1;
@@ -338,8 +330,64 @@ static int do_mmcops(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 			printf("EMMC boot partition Size change Failed.\n");
 			return 1;
 		}
+	} else if (strcmp(argv[1], "rst-function") == 0) {
+		/*
+		 * Set the RST_n_ENABLE bit of RST_n_FUNCTION
+		 * The only valid values are 0x0, 0x1 and 0x2 and writing
+		 * a value of 0x1 or 0x2 sets the value permanently.
+		 */
+		int dev;
+		struct mmc *mmc;
+		u8 enable;
+
+		if (argc == 4) {
+			dev = simple_strtoul(argv[2], NULL, 10);
+			enable = simple_strtoul(argv[3], NULL, 10);
+		} else {
+			return CMD_RET_USAGE;
+		}
+
+		if (enable > 2 || enable < 0) {
+			puts("Invalid RST_n_ENABLE value\n");
+			return CMD_RET_USAGE;
+		}
+
+		mmc = find_mmc_device(dev);
+		if (!mmc) {
+			printf("no mmc device at slot %x\n", dev);
+			return 1;
+		}
+
+		if (IS_SD(mmc)) {
+			puts("RST_n_FUNCTION only exists on eMMC\n");
+			return 1;
+		}
+
+		return mmc_set_rst_n_function(mmc, enable);
 #endif /* CONFIG_SUPPORT_EMMC_BOOT */
 	}
+
+	else if (argc == 3 && strcmp(argv[1], "setdsr") == 0) {
+		struct mmc *mmc = find_mmc_device(curr_device);
+		u32 val = simple_strtoul(argv[2], NULL, 16);
+		int ret;
+
+		if (!mmc) {
+			printf("no mmc device at slot %x\n", curr_device);
+			return 1;
+		}
+		ret = mmc_set_dsr(mmc, val);
+		printf("set dsr %s\n", (!ret) ? "OK, force rescan" : "ERROR");
+		if (!ret) {
+			mmc->has_init = 0;
+			if (mmc_init(mmc))
+				return 1;
+			else
+				return 0;
+		}
+		return ret;
+	}
+
 	state = MMC_INVALID;
 	if (argc == 5 && strcmp(argv[1], "read") == 0)
 		state = MMC_READ;
@@ -416,12 +464,16 @@ U_BOOT_CMD(
 	"mmc dev [dev] [part] - show or set current mmc device [partition]\n"
 	"mmc list - lists available devices\n"
 #ifdef CONFIG_SUPPORT_EMMC_BOOT
-	"mmc open <dev> <boot_partition>\n"
-	" - Enable boot_part for booting and enable R/W access of boot_part\n"
-	"mmc close <dev> <boot_partition>\n"
-	" - Enable boot_part for booting and disable access to boot_part\n"
-	"mmc bootpart <device num> <boot part size MB> <RPMB part size MB>\n"
-	" - change sizes of boot and RPMB partitions of specified device\n"
+	"mmc bootbus dev boot_bus_width reset_boot_bus_width boot_mode\n"
+	" - Set the BOOT_BUS_WIDTH field of the specified device\n"
+	"mmc bootpart-resize <dev> <boot part size MB> <RPMB part size MB>\n"
+	" - Change sizes of boot and RPMB partitions of specified device\n"
+	"mmc partconf dev boot_ack boot_partition partition_access\n"
+	" - Change the bits of the PARTITION_CONFIG field of the specified device\n"
+	"mmc rst-function dev value\n"
+	" - Change the RST_n_FUNCTION field of the specified device\n"
+	"   WARNING: This is a write-once field and 0 / 1 / 2 are the only valid values.\n"
 #endif
+	"mmc setdsr - set DSR register value\n"
 	);
 #endif /* !CONFIG_GENERIC_MMC */
diff --git a/common/cmd_mmc_spi.c b/common/cmd_mmc_spi.c
index 98cd788c76..a2138b8650 100644
--- a/common/cmd_mmc_spi.c
+++ b/common/cmd_mmc_spi.c
@@ -72,7 +72,7 @@ static int do_mmc_spi(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 		printf("Failed to create MMC Device\n");
 		return 1;
 	}
-	printf("%s: %d at %u:%u hz %u mode %u\n", mmc->name, mmc->block_dev.dev,
+	printf("%s: %d at %u:%u hz %u mode %u\n", mmc->cfg->name, mmc->block_dev.dev,
 	       bus, cs, speed, mode);
 	mmc_init(mmc);
 	return 0;
diff --git a/common/cmd_nvedit.c b/common/cmd_nvedit.c
index ba9ba16972..c53601cf74 100644
--- a/common/cmd_nvedit.c
+++ b/common/cmd_nvedit.c
@@ -157,10 +157,8 @@ static int do_env_grep(cmd_tbl_t *cmdtp, int flag,
 	grep_how  = H_MATCH_SUBSTR;	/* default: substring search	*/
 	grep_what = H_MATCH_BOTH;	/* default: grep names and values */
 
-	while (argc > 1 && **(argv + 1) == '-') {
-		char *arg = *++argv;
-
-		--argc;
+	while (--argc > 0 && **++argv == '-') {
+		char *arg = *argv;
 		while (*++arg) {
 			switch (*arg) {
 #ifdef CONFIG_REGEX
@@ -1010,6 +1008,9 @@ static int do_env_import(cmd_tbl_t *cmdtp, int flag,
 
 	if (argc == 2) {
 		size = simple_strtoul(argv[1], NULL, 16);
+	} else if (argc == 1 && chk) {
+		puts("## Error: external checksum format must pass size\n");
+		return CMD_RET_FAILURE;
 	} else {
 		char *s = addr;
 
@@ -1059,6 +1060,23 @@ sep_err:
 }
 #endif
 
+#if defined(CONFIG_CMD_ENV_EXISTS)
+static int do_env_exists(cmd_tbl_t *cmdtp, int flag, int argc,
+		       char * const argv[])
+{
+	ENTRY e, *ep;
+
+	if (argc < 2)
+		return CMD_RET_USAGE;
+
+	e.key = argv[1];
+	e.data = NULL;
+	hsearch_r(e, FIND, &ep, &env_htab, 0);
+
+	return (ep == NULL) ? 1 : 0;
+}
+#endif
+
 /*
  * New command line interface: "env" command with subcommands
  */
@@ -1094,6 +1112,9 @@ static cmd_tbl_t cmd_env_sub[] = {
 	U_BOOT_CMD_MKENT(save, 1, 0, do_env_save, "", ""),
 #endif
 	U_BOOT_CMD_MKENT(set, CONFIG_SYS_MAXARGS, 0, do_env_set, "", ""),
+#if defined(CONFIG_CMD_ENV_EXISTS)
+	U_BOOT_CMD_MKENT(exists, 2, 0, do_env_exists, "", ""),
+#endif
 };
 
 #if defined(CONFIG_NEEDS_MANUAL_RELOC)
@@ -1136,6 +1157,9 @@ static char env_help_text[] =
 #if defined(CONFIG_CMD_EDITENV)
 	"env edit name - edit environment variable\n"
 #endif
+#if defined(CONFIG_CMD_ENV_EXISTS)
+	"env exists name - tests for existence of variable\n"
+#endif
 #if defined(CONFIG_CMD_EXPORTENV)
 	"env export [-t | -b | -c] [-s size] addr [var ...] - export environment\n"
 #endif
diff --git a/common/cmd_otp.c b/common/cmd_otp.c
index 6f93335517..67808aa377 100644
--- a/common/cmd_otp.c
+++ b/common/cmd_otp.c
@@ -18,6 +18,7 @@
 #include <command.h>
 
 #include <asm/blackfin.h>
+#include <asm/clock.h>
 #include <asm/mach-common/bits/otp.h>
 
 static const char *otp_strerror(uint32_t err)
diff --git a/common/cmd_pxe.c b/common/cmd_pxe.c
index 79d3a061f5..348332874b 100644
--- a/common/cmd_pxe.c
+++ b/common/cmd_pxe.c
@@ -11,6 +11,7 @@
 #include <linux/ctype.h>
 #include <errno.h>
 #include <linux/list.h>
+#include <fs.h>
 
 #include "menu.h"
 
@@ -25,6 +26,8 @@ const char *pxe_default_paths[] = {
 	NULL
 };
 
+static bool is_pxe;
+
 /*
  * Like getenv, but prints an error if envvar isn't defined in the
  * environment.  It always returns what getenv does, so it can be used in
@@ -42,6 +45,7 @@ static char *from_env(const char *envvar)
 	return ret;
 }
 
+#ifdef CONFIG_CMD_NET
 /*
  * Convert an ethaddr from the environment to the format used by pxelinux
  * filenames based on mac addresses. Convert's ':' to '-', and adds "01-" to
@@ -57,7 +61,7 @@ static int format_mac_pxe(char *outbuf, size_t outbuf_len)
 	uchar ethaddr[6];
 
 	if (outbuf_len < 21) {
-		printf("outbuf is too small (%d < 21)\n", outbuf_len);
+		printf("outbuf is too small (%zd < 21)\n", outbuf_len);
 
 		return -EINVAL;
 	}
@@ -72,6 +76,7 @@ static int format_mac_pxe(char *outbuf, size_t outbuf_len)
 
 	return 1;
 }
+#endif
 
 /*
  * Returns the directory the file specified in the bootfile env variable is
@@ -84,7 +89,8 @@ static int get_bootfile_path(const char *file_path, char *bootfile_path,
 	char *bootfile, *last_slash;
 	size_t path_len = 0;
 
-	if (file_path[0] == '/')
+	/* Only syslinux allows absolute paths */
+	if (file_path[0] == '/' && !is_pxe)
 		goto ret;
 
 	bootfile = from_env("bootfile");
@@ -100,7 +106,7 @@ static int get_bootfile_path(const char *file_path, char *bootfile_path,
 	path_len = (last_slash - bootfile) + 1;
 
 	if (bootfile_path_size < path_len) {
-		printf("bootfile_path too small. (%d < %d)\n",
+		printf("bootfile_path too small. (%zd < %zd)\n",
 				bootfile_path_size, path_len);
 
 		return -1;
@@ -116,6 +122,7 @@ static int get_bootfile_path(const char *file_path, char *bootfile_path,
 
 static int (*do_getfile)(cmd_tbl_t *cmdtp, const char *file_path, char *file_addr);
 
+#ifdef CONFIG_CMD_NET
 static int do_get_tftp(cmd_tbl_t *cmdtp, const char *file_path, char *file_addr)
 {
 	char *tftp_argv[] = {"tftp", NULL, NULL, NULL};
@@ -128,6 +135,7 @@ static int do_get_tftp(cmd_tbl_t *cmdtp, const char *file_path, char *file_addr)
 
 	return 1;
 }
+#endif
 
 static char *fs_argv[5];
 
@@ -157,6 +165,19 @@ static int do_get_fat(cmd_tbl_t *cmdtp, const char *file_path, char *file_addr)
 	return -ENOENT;
 }
 
+static int do_get_any(cmd_tbl_t *cmdtp, const char *file_path, char *file_addr)
+{
+#ifdef CONFIG_CMD_FS_GENERIC
+	fs_argv[0] = "load";
+	fs_argv[3] = file_addr;
+	fs_argv[4] = (void *)file_path;
+
+	if (!do_load(cmdtp, 0, 5, fs_argv, FS_TYPE_ANY))
+		return 1;
+#endif
+	return -ENOENT;
+}
+
 /*
  * As in pxelinux, paths to files referenced from files we retrieve are
  * relative to the location of bootfile. get_relfile takes such a path and
@@ -232,6 +253,8 @@ static int get_pxe_file(cmd_tbl_t *cmdtp, const char *file_path, void *file_addr
 	return 1;
 }
 
+#ifdef CONFIG_CMD_NET
+
 #define PXELINUX_DIR "pxelinux.cfg/"
 
 /*
@@ -380,6 +403,7 @@ do_pxe_get(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 
 	return 1;
 }
+#endif
 
 /*
  * Wrapper to make it easier to store the file at file_path in the location
@@ -442,6 +466,7 @@ struct pxe_label {
 	char *append;
 	char *initrd;
 	char *fdt;
+	char *fdtdir;
 	int ipappend;
 	int attempted;
 	int localboot;
@@ -514,6 +539,9 @@ static void label_destroy(struct pxe_label *label)
 	if (label->fdt)
 		free(label->fdt);
 
+	if (label->fdtdir)
+		free(label->fdtdir);
+
 	free(label);
 }
 
@@ -626,6 +654,7 @@ static int label_boot(cmd_tbl_t *cmdtp, struct pxe_label *label)
 		len += strlen(ip_str);
 	}
 
+#ifdef CONFIG_CMD_NET
 	if (label->ipappend & 0x2) {
 		int err;
 		strcpy(mac_str, " BOOTIF=");
@@ -634,6 +663,7 @@ static int label_boot(cmd_tbl_t *cmdtp, struct pxe_label *label)
 			mac_str[0] = '\0';
 		len += strlen(mac_str);
 	}
+#endif
 
 	if (label->append)
 		len += strlen(label->append);
@@ -672,13 +702,70 @@ static int label_boot(cmd_tbl_t *cmdtp, struct pxe_label *label)
 	bootm_argv[3] = getenv("fdt_addr_r");
 
 	/* if fdt label is defined then get fdt from server */
-	if (bootm_argv[3] && label->fdt) {
-		if (get_relfile_envaddr(cmdtp, label->fdt, "fdt_addr_r") < 0) {
-			printf("Skipping %s for failure retrieving fdt\n",
-					label->name);
-			return 1;
+	if (bootm_argv[3]) {
+		char *fdtfile = NULL;
+		char *fdtfilefree = NULL;
+
+		if (label->fdt) {
+			fdtfile = label->fdt;
+		} else if (label->fdtdir) {
+			char *f1, *f2, *f3, *f4, *slash;
+
+			f1 = getenv("fdtfile");
+			if (f1) {
+				f2 = "";
+				f3 = "";
+				f4 = "";
+			} else {
+				/*
+				 * For complex cases where this code doesn't
+				 * generate the correct filename, the board
+				 * code should set $fdtfile during early boot,
+				 * or the boot scripts should set $fdtfile
+				 * before invoking "pxe" or "sysboot".
+				 */
+				f1 = getenv("soc");
+				f2 = "-";
+				f3 = getenv("board");
+				f4 = ".dtb";
+			}
+
+			len = strlen(label->fdtdir);
+			if (!len)
+				slash = "./";
+			else if (label->fdtdir[len - 1] != '/')
+				slash = "/";
+			else
+				slash = "";
+
+			len = strlen(label->fdtdir) + strlen(slash) +
+				strlen(f1) + strlen(f2) + strlen(f3) +
+				strlen(f4) + 1;
+			fdtfilefree = malloc(len);
+			if (!fdtfilefree) {
+				printf("malloc fail (FDT filename)\n");
+				return 1;
+			}
+
+			snprintf(fdtfilefree, len, "%s%s%s%s%s%s",
+				 label->fdtdir, slash, f1, f2, f3, f4);
+			fdtfile = fdtfilefree;
+		}
+
+		if (fdtfile) {
+			int err = get_relfile_envaddr(cmdtp, fdtfile, "fdt_addr_r");
+			free(fdtfilefree);
+			if (err < 0) {
+				printf("Skipping %s for failure retrieving fdt\n",
+						label->name);
+				return 1;
+			}
+		} else {
+			bootm_argv[3] = NULL;
 		}
-	} else
+	}
+
+	if (!bootm_argv[3])
 		bootm_argv[3] = getenv("fdt_addr");
 
 	if (bootm_argv[3])
@@ -713,6 +800,7 @@ enum token_type {
 	T_PROMPT,
 	T_INCLUDE,
 	T_FDT,
+	T_FDTDIR,
 	T_ONTIMEOUT,
 	T_IPAPPEND,
 	T_INVALID
@@ -742,7 +830,10 @@ static const struct token keywords[] = {
 	{"append", T_APPEND},
 	{"initrd", T_INITRD},
 	{"include", T_INCLUDE},
+	{"devicetree", T_FDT},
 	{"fdt", T_FDT},
+	{"devicetreedir", T_FDTDIR},
+	{"fdtdir", T_FDTDIR},
 	{"ontimeout", T_ONTIMEOUT,},
 	{"ipappend", T_IPAPPEND,},
 	{NULL, T_INVALID}
@@ -1131,6 +1222,11 @@ static int parse_label(char **c, struct pxe_menu *cfg)
 				err = parse_sliteral(c, &label->fdt);
 			break;
 
+		case T_FDTDIR:
+			if (!label->fdtdir)
+				err = parse_sliteral(c, &label->fdtdir);
+			break;
+
 		case T_LOCALBOOT:
 			label->localboot = 1;
 			err = parse_integer(c, &label->localboot_val);
@@ -1416,6 +1512,7 @@ static void handle_pxe_menu(cmd_tbl_t *cmdtp, struct pxe_menu *cfg)
 	boot_unattempted_labels(cmdtp, cfg);
 }
 
+#ifdef CONFIG_CMD_NET
 /*
  * Boots a system using a pxe file
  *
@@ -1472,6 +1569,8 @@ int do_pxe(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 	if (argc < 2)
 		return CMD_RET_USAGE;
 
+	is_pxe = true;
+
 	/* drop initial "pxe" arg */
 	argc--;
 	argv++;
@@ -1490,6 +1589,7 @@ U_BOOT_CMD(
 	"get - try to retrieve a pxe file using tftp\npxe "
 	"boot [pxefile_addr_r] - boot from the pxe file at pxefile_addr_r\n"
 );
+#endif
 
 /*
  * Boots a system using a local disk syslinux/extlinux file
@@ -1504,6 +1604,8 @@ int do_sysboot(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 	char *filename;
 	int prompt = 0;
 
+	is_pxe = false;
+
 	if (strstr(argv[1], "-p")) {
 		prompt = 1;
 		argc--;
@@ -1532,6 +1634,8 @@ int do_sysboot(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 		do_getfile = do_get_ext2;
 	else if (strstr(argv[3], "fat"))
 		do_getfile = do_get_fat;
+	else if (strstr(argv[3], "any"))
+		do_getfile = do_get_any;
 	else {
 		printf("Invalid filesystem: %s\n", argv[3]);
 		return 1;
@@ -1569,7 +1673,7 @@ int do_sysboot(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 U_BOOT_CMD(
 	sysboot, 7, 1, do_sysboot,
 	"command to get and boot from syslinux files",
-	"[-p] <interface> <dev[:part]> <ext2|fat> [addr] [filename]\n"
-	"    - load and parse syslinux menu file 'filename' from ext2 or fat\n"
-	"      filesystem on 'dev' on 'interface' to address 'addr'"
+	"[-p] <interface> <dev[:part]> <ext2|fat|any> [addr] [filename]\n"
+	"    - load and parse syslinux menu file 'filename' from ext2, fat\n"
+	"      or any filesystem on 'dev' on 'interface' to address 'addr'"
 );
diff --git a/common/cmd_reiser.c b/common/cmd_reiser.c
index b9d2449e33..887156486a 100644
--- a/common/cmd_reiser.c
+++ b/common/cmd_reiser.c
@@ -141,7 +141,7 @@ int do_reiserload (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 
 	filelen = reiserfs_open(filename);
 	if (filelen < 0) {
-		printf("** File not found %s\n", filename);
+		printf("** File not found %s **\n", filename);
 		return 1;
 	}
 	if ((count < filelen) && (count != 0)) {
diff --git a/common/cmd_sandbox.c b/common/cmd_sandbox.c
index 8d59364b63..00982b164d 100644
--- a/common/cmd_sandbox.c
+++ b/common/cmd_sandbox.c
@@ -6,6 +6,9 @@
 
 #include <common.h>
 #include <fs.h>
+#include <part.h>
+#include <sandboxblockdev.h>
+#include <asm/errno.h>
 
 static int do_sandbox_load(cmd_tbl_t *cmdtp, int flag, int argc,
 			   char * const argv[])
@@ -25,10 +28,69 @@ static int do_sandbox_save(cmd_tbl_t *cmdtp, int flag, int argc,
 	return do_save(cmdtp, flag, argc, argv, FS_TYPE_SANDBOX);
 }
 
+static int do_sandbox_bind(cmd_tbl_t *cmdtp, int flag, int argc,
+			   char * const argv[])
+{
+	if (argc < 2 || argc > 3)
+		return CMD_RET_USAGE;
+	char *ep;
+	char *dev_str = argv[1];
+	char *file = argc >= 3 ? argv[2] : NULL;
+	int dev = simple_strtoul(dev_str, &ep, 16);
+	if (*ep) {
+		printf("** Bad device specification %s **\n", dev_str);
+		return CMD_RET_USAGE;
+	}
+	return host_dev_bind(dev, file);
+}
+
+static int do_sandbox_info(cmd_tbl_t *cmdtp, int flag, int argc,
+			   char * const argv[])
+{
+	if (argc < 1 || argc > 2)
+		return CMD_RET_USAGE;
+	int min_dev = 0;
+	int max_dev = CONFIG_HOST_MAX_DEVICES - 1;
+	if (argc >= 2) {
+		char *ep;
+		char *dev_str = argv[1];
+		int dev = simple_strtoul(dev_str, &ep, 16);
+		if (*ep) {
+			printf("** Bad device specification %s **\n", dev_str);
+			return CMD_RET_USAGE;
+		}
+		min_dev = dev;
+		max_dev = dev;
+	}
+	int dev;
+	printf("%3s %12s %s\n", "dev", "blocks", "path");
+	for (dev = min_dev; dev <= max_dev; dev++) {
+		block_dev_desc_t *blk_dev;
+		int ret;
+
+		printf("%3d ", dev);
+		ret = host_get_dev_err(dev, &blk_dev);
+		if (ret) {
+			if (ret == -ENOENT)
+				puts("Not bound to a backing file\n");
+			else if (ret == -ENODEV)
+				puts("Invalid host device number\n");
+
+			continue;
+		}
+		struct host_block_dev *host_dev = blk_dev->priv;
+		printf("%12lu %s\n", (unsigned long)blk_dev->lba,
+		       host_dev->filename);
+	}
+	return 0;
+}
+
 static cmd_tbl_t cmd_sandbox_sub[] = {
 	U_BOOT_CMD_MKENT(load, 7, 0, do_sandbox_load, "", ""),
 	U_BOOT_CMD_MKENT(ls, 3, 0, do_sandbox_ls, "", ""),
 	U_BOOT_CMD_MKENT(save, 6, 0, do_sandbox_save, "", ""),
+	U_BOOT_CMD_MKENT(bind, 3, 0, do_sandbox_bind, "", ""),
+	U_BOOT_CMD_MKENT(info, 3, 0, do_sandbox_info, "", ""),
 };
 
 static int do_sandbox(cmd_tbl_t *cmdtp, int flag, int argc,
@@ -57,4 +119,6 @@ U_BOOT_CMD(
 	"sb ls host <filename>                      - list files on host\n"
 	"sb save host <dev> <filename> <addr> <bytes> [<offset>] - "
 		"save a file to host\n"
+	"sb bind <dev> [<filename>] - bind \"host\" device to file\n"
+	"sb info [<dev>]            - show device binding & info"
 );
diff --git a/common/cmd_scsi.c b/common/cmd_scsi.c
index 7b97dc9332..b3f7687aee 100644
--- a/common/cmd_scsi.c
+++ b/common/cmd_scsi.c
@@ -168,7 +168,9 @@ removable:
 		scsi_curr_dev = -1;
 
 	printf("Found %d device(s).\n", scsi_max_devs);
+#ifndef CONFIG_SPL_BUILD
 	setenv_ulong("scsidevs", scsi_max_devs);
+#endif
 }
 
 int scsi_get_disk_count(void)
diff --git a/common/cmd_sf.c b/common/cmd_sf.c
index 3994b0651c..b4ceb71466 100644
--- a/common/cmd_sf.c
+++ b/common/cmd_sf.c
@@ -358,7 +358,8 @@ static void show_time(struct test_info *test, int stage)
 	int bps;	/* Bits per second */
 
 	speed = (long long)test->bytes * 1000;
-	do_div(speed, test->time_ms[stage] * 1024);
+	if (test->time_ms[stage])
+		do_div(speed, test->time_ms[stage] * 1024);
 	bps = speed * 8;
 
 	printf("%d %s: %d ticks, %d KiB/s %d.%03d Mbps\n", stage,
@@ -446,11 +447,13 @@ static int do_spi_flash_test(int argc, char * const argv[])
 {
 	unsigned long offset;
 	unsigned long len;
-	uint8_t *buf = (uint8_t *)CONFIG_SYS_TEXT_BASE;
+	uint8_t *buf, *from;
 	char *endp;
 	uint8_t *vbuf;
 	int ret;
 
+	if (argc < 3)
+		return -1;
 	offset = simple_strtoul(argv[1], &endp, 16);
 	if (*argv[1] == 0 || *endp != 0)
 		return -1;
@@ -460,17 +463,18 @@ static int do_spi_flash_test(int argc, char * const argv[])
 
 	vbuf = malloc(len);
 	if (!vbuf) {
-		printf("Cannot allocate memory\n");
+		printf("Cannot allocate memory (%lu bytes)\n", len);
 		return 1;
 	}
 	buf = malloc(len);
 	if (!buf) {
 		free(vbuf);
-		printf("Cannot allocate memory\n");
+		printf("Cannot allocate memory (%lu bytes)\n", len);
 		return 1;
 	}
 
-	memcpy(buf, (char *)CONFIG_SYS_TEXT_BASE, len);
+	from = map_sysmem(CONFIG_SYS_TEXT_BASE, 0);
+	memcpy(buf, from, len);
 	ret = spi_flash_test(flash, buf, len, offset, vbuf);
 	free(vbuf);
 	free(buf);
diff --git a/common/cmd_test.c b/common/cmd_test.c
index bacc368406..c93fe78231 100644
--- a/common/cmd_test.c
+++ b/common/cmd_test.c
@@ -16,11 +16,54 @@
 
 #include <common.h>
 #include <command.h>
+#include <fs.h>
+
+#define OP_INVALID	0
+#define OP_NOT		1
+#define OP_OR		2
+#define OP_AND		3
+#define OP_STR_EMPTY	4
+#define OP_STR_NEMPTY	5
+#define OP_STR_EQ	6
+#define OP_STR_NEQ	7
+#define OP_STR_LT	8
+#define OP_STR_GT	9
+#define OP_INT_EQ	10
+#define OP_INT_NEQ	11
+#define OP_INT_LT	12
+#define OP_INT_LE	13
+#define OP_INT_GT	14
+#define OP_INT_GE	15
+#define OP_FILE_EXISTS	16
+
+const struct {
+	int arg;
+	const char *str;
+	int op;
+	int adv;
+} op_adv[] = {
+	{1, "=", OP_STR_EQ, 3},
+	{1, "!=", OP_STR_NEQ, 3},
+	{1, "<", OP_STR_LT, 3},
+	{1, ">", OP_STR_GT, 3},
+	{1, "-eq", OP_INT_EQ, 3},
+	{1, "-ne", OP_INT_NEQ, 3},
+	{1, "-lt", OP_INT_LT, 3},
+	{1, "-le", OP_INT_LE, 3},
+	{1, "-gt", OP_INT_GT, 3},
+	{1, "-ge", OP_INT_GE, 3},
+	{0, "!", OP_NOT, 1},
+	{0, "-o", OP_OR, 1},
+	{0, "-a", OP_AND, 1},
+	{0, "-z", OP_STR_EMPTY, 2},
+	{0, "-n", OP_STR_NEMPTY, 2},
+	{0, "-e", OP_FILE_EXISTS, 4},
+};
 
 static int do_test(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 {
 	char * const *ap;
-	int left, adv, expr, last_expr, neg, last_cmp;
+	int i, op, left, adv, expr, last_expr, last_unop, last_binop;
 
 	/* args? */
 	if (argc < 3)
@@ -35,101 +78,112 @@ static int do_test(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 	}
 #endif
 
-	last_expr = 0;
-	left = argc - 1; ap = argv + 1;
-	if (left > 0 && strcmp(ap[0], "!") == 0) {
-		neg = 1;
-		ap++;
-		left--;
-	} else
-		neg = 0;
-
-	expr = -1;
-	last_cmp = -1;
+	left = argc - 1;
+	ap = argv + 1;
+	expr = 0;
+	last_unop = OP_INVALID;
+	last_binop = OP_INVALID;
 	last_expr = -1;
 	while (left > 0) {
-
-		if (strcmp(ap[0], "-o") == 0 || strcmp(ap[0], "-a") == 0)
-			adv = 1;
-		else if (strcmp(ap[0], "-z") == 0 || strcmp(ap[0], "-n") == 0)
-			adv = 2;
-		else
-			adv = 3;
-
+		for (i = 0; i < ARRAY_SIZE(op_adv); i++) {
+			if (left <= op_adv[i].arg)
+				continue;
+			if (!strcmp(ap[op_adv[i].arg], op_adv[i].str)) {
+				op = op_adv[i].op;
+				adv = op_adv[i].adv;
+				break;
+			}
+		}
+		if (i == ARRAY_SIZE(op_adv)) {
+			expr = 1;
+			break;
+		}
 		if (left < adv) {
 			expr = 1;
 			break;
 		}
 
-		if (adv == 1) {
-			if (strcmp(ap[0], "-o") == 0) {
-				last_expr = expr;
-				last_cmp = 0;
-			} else if (strcmp(ap[0], "-a") == 0) {
-				last_expr = expr;
-				last_cmp = 1;
-			} else {
-				expr = 1;
-				break;
-			}
+		switch (op) {
+		case OP_STR_EMPTY:
+			expr = strlen(ap[1]) == 0 ? 1 : 0;
+			break;
+		case OP_STR_NEMPTY:
+			expr = strlen(ap[1]) == 0 ? 0 : 1;
+			break;
+		case OP_STR_EQ:
+			expr = strcmp(ap[0], ap[2]) == 0;
+			break;
+		case OP_STR_NEQ:
+			expr = strcmp(ap[0], ap[2]) != 0;
+			break;
+		case OP_STR_LT:
+			expr = strcmp(ap[0], ap[2]) < 0;
+			break;
+		case OP_STR_GT:
+			expr = strcmp(ap[0], ap[2]) > 0;
+			break;
+		case OP_INT_EQ:
+			expr = simple_strtol(ap[0], NULL, 10) ==
+					simple_strtol(ap[2], NULL, 10);
+			break;
+		case OP_INT_NEQ:
+			expr = simple_strtol(ap[0], NULL, 10) !=
+					simple_strtol(ap[2], NULL, 10);
+			break;
+		case OP_INT_LT:
+			expr = simple_strtol(ap[0], NULL, 10) <
+					simple_strtol(ap[2], NULL, 10);
+			break;
+		case OP_INT_LE:
+			expr = simple_strtol(ap[0], NULL, 10) <=
+					simple_strtol(ap[2], NULL, 10);
+			break;
+		case OP_INT_GT:
+			expr = simple_strtol(ap[0], NULL, 10) >
+					simple_strtol(ap[2], NULL, 10);
+			break;
+		case OP_INT_GE:
+			expr = simple_strtol(ap[0], NULL, 10) >=
+					simple_strtol(ap[2], NULL, 10);
+			break;
+		case OP_FILE_EXISTS:
+			expr = file_exists(ap[1], ap[2], ap[3], FS_TYPE_ANY);
+			break;
 		}
 
-		if (adv == 2) {
-			if (strcmp(ap[0], "-z") == 0)
-				expr = strlen(ap[1]) == 0 ? 1 : 0;
-			else if (strcmp(ap[0], "-n") == 0)
-				expr = strlen(ap[1]) == 0 ? 0 : 1;
-			else {
-				expr = 1;
-				break;
+		switch (op) {
+		case OP_OR:
+			last_expr = expr;
+			last_binop = OP_OR;
+			break;
+		case OP_AND:
+			last_expr = expr;
+			last_binop = OP_AND;
+			break;
+		case OP_NOT:
+			if (last_unop == OP_NOT)
+				last_unop = OP_INVALID;
+			else
+				last_unop = OP_NOT;
+			break;
+		default:
+			if (last_unop == OP_NOT) {
+				expr = !expr;
+				last_unop = OP_INVALID;
 			}
 
-			if (last_cmp == 0)
+			if (last_binop == OP_OR)
 				expr = last_expr || expr;
-			else if (last_cmp == 1)
+			else if (last_binop == OP_AND)
 				expr = last_expr && expr;
-			last_cmp = -1;
-		}
-
-		if (adv == 3) {
-			if (strcmp(ap[1], "=") == 0)
-				expr = strcmp(ap[0], ap[2]) == 0;
-			else if (strcmp(ap[1], "!=") == 0)
-				expr = strcmp(ap[0], ap[2]) != 0;
-			else if (strcmp(ap[1], ">") == 0)
-				expr = strcmp(ap[0], ap[2]) > 0;
-			else if (strcmp(ap[1], "<") == 0)
-				expr = strcmp(ap[0], ap[2]) < 0;
-			else if (strcmp(ap[1], "-eq") == 0)
-				expr = simple_strtol(ap[0], NULL, 10) == simple_strtol(ap[2], NULL, 10);
-			else if (strcmp(ap[1], "-ne") == 0)
-				expr = simple_strtol(ap[0], NULL, 10) != simple_strtol(ap[2], NULL, 10);
-			else if (strcmp(ap[1], "-lt") == 0)
-				expr = simple_strtol(ap[0], NULL, 10) < simple_strtol(ap[2], NULL, 10);
-			else if (strcmp(ap[1], "-le") == 0)
-				expr = simple_strtol(ap[0], NULL, 10) <= simple_strtol(ap[2], NULL, 10);
-			else if (strcmp(ap[1], "-gt") == 0)
-				expr = simple_strtol(ap[0], NULL, 10) > simple_strtol(ap[2], NULL, 10);
-			else if (strcmp(ap[1], "-ge") == 0)
-				expr = simple_strtol(ap[0], NULL, 10) >= simple_strtol(ap[2], NULL, 10);
-			else {
-				expr = 1;
-				break;
-			}
+			last_binop = OP_INVALID;
 
-			if (last_cmp == 0)
-				expr = last_expr || expr;
-			else if (last_cmp == 1)
-				expr = last_expr && expr;
-			last_cmp = -1;
+			break;
 		}
 
 		ap += adv; left -= adv;
 	}
 
-	if (neg)
-		expr = !expr;
-
 	expr = !expr;
 
 	debug (": returns %d\n", expr);
diff --git a/common/cmd_thordown.c b/common/cmd_thordown.c
new file mode 100644
index 0000000000..c4b3511458
--- /dev/null
+++ b/common/cmd_thordown.c
@@ -0,0 +1,72 @@
+/*
+ * cmd_thordown.c -- USB TIZEN "THOR" Downloader gadget
+ *
+ * Copyright (C) 2013 Lukasz Majewski <l.majewski@samsung.com>
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <thor.h>
+#include <dfu.h>
+#include <g_dnl.h>
+#include <usb.h>
+
+int do_thor_down(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	if (argc < 4)
+		return CMD_RET_USAGE;
+
+	char *usb_controller = argv[1];
+	char *interface = argv[2];
+	char *devstring = argv[3];
+
+	const char *s = "thor";
+	int ret;
+
+	puts("TIZEN \"THOR\" Downloader\n");
+
+	ret = dfu_init_env_entities(interface, simple_strtoul(devstring,
+							      NULL, 10));
+	if (ret)
+		return ret;
+
+	int controller_index = simple_strtoul(usb_controller, NULL, 0);
+	ret = board_usb_init(controller_index, USB_INIT_DEVICE);
+	if (ret) {
+		error("USB init failed: %d", ret);
+		ret = CMD_RET_FAILURE;
+		goto exit;
+	}
+
+	g_dnl_register(s);
+
+	ret = thor_init();
+	if (ret) {
+		error("THOR DOWNLOAD failed: %d", ret);
+		ret = CMD_RET_FAILURE;
+		goto exit;
+	}
+
+	ret = thor_handle();
+	if (ret) {
+		error("THOR failed: %d", ret);
+		ret = CMD_RET_FAILURE;
+		goto exit;
+	}
+
+exit:
+	g_dnl_unregister();
+	dfu_free_entities();
+
+	return ret;
+}
+
+U_BOOT_CMD(thordown, CONFIG_SYS_MAXARGS, 1, do_thor_down,
+	   "TIZEN \"THOR\" downloader",
+	   "<USB_controller> <interface> <dev>\n"
+	   "  - device software upgrade via LTHOR TIZEN dowload\n"
+	   "    program via <USB_controller> on device <dev>,\n"
+	   "	attached to interface <interface>\n"
+);
diff --git a/common/cmd_ubi.c b/common/cmd_ubi.c
index 122ba7e171..7c4d950e96 100644
--- a/common/cmd_ubi.c
+++ b/common/cmd_ubi.c
@@ -123,6 +123,27 @@ static int ubi_info(int layout)
 	return 0;
 }
 
+static int ubi_check_volumename(const struct ubi_volume *vol, char *name)
+{
+	return strcmp(vol->name, name);
+}
+
+static int ubi_check(char *name)
+{
+	int i;
+
+	for (i = 0; i < (ubi->vtbl_slots + 1); i++) {
+		if (!ubi->volumes[i])
+			continue;	/* Empty record */
+
+		if (!ubi_check_volumename(ubi->volumes[i], name))
+			return 0;
+	}
+
+	return -EEXIST;
+}
+
+
 static int verify_mkvol_req(const struct ubi_device *ubi,
 			    const struct ubi_mkvol_req *req)
 {
@@ -558,6 +579,14 @@ static int do_ubi(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 		return ubi_info(layout);
 	}
 
+	if (strcmp(argv[1], "check") == 0) {
+		if (argc > 2)
+			return ubi_check(argv[2]);
+
+		printf("Error, no volume name passed\n");
+		return 1;
+	}
+
 	if (strncmp(argv[1], "create", 6) == 0) {
 		int dynamic = 1;	/* default: dynamic volume */
 
@@ -663,6 +692,8 @@ U_BOOT_CMD(
 		" header offset)\n"
 	"ubi info [l[ayout]]"
 		" - Display volume and ubi layout information\n"
+	"ubi check volumename"
+		" - check if volumename exists\n"
 	"ubi create[vol] volume [size] [type]"
 		" - create volume name with size\n"
 	"ubi write[vol] address volume size"
diff --git a/common/cmd_ubifs.c b/common/cmd_ubifs.c
index eba54fd004..fdc8bfe46a 100644
--- a/common/cmd_ubifs.c
+++ b/common/cmd_ubifs.c
@@ -21,15 +21,6 @@
 static int ubifs_initialized;
 static int ubifs_mounted;
 
-extern struct super_block *ubifs_sb;
-
-/* Prototypes */
-int ubifs_init(void);
-int ubifs_mount(char *vol_name);
-void ubifs_umount(struct ubifs_info *c);
-int ubifs_ls(char *dir_name);
-int ubifs_load(char *filename, u32 addr, u32 size);
-
 int do_ubifs_mount(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 {
 	char *vol_name;
@@ -104,8 +95,10 @@ int do_ubifs_ls(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 	debug("Using filename %s\n", filename);
 
 	ret = ubifs_ls(filename);
-	if (ret)
-		printf("%s not found!\n", filename);
+	if (ret) {
+		printf("** File not found %s **\n", filename);
+		ret = CMD_RET_FAILURE;
+	}
 
 	return ret;
 }
@@ -140,8 +133,10 @@ int do_ubifs_load(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 	debug("Loading file '%s' to address 0x%08x (size %d)\n", filename, addr, size);
 
 	ret = ubifs_load(filename, addr, size);
-	if (ret)
-		printf("%s not found!\n", filename);
+	if (ret) {
+		printf("** File not found %s **\n", filename);
+		ret = CMD_RET_FAILURE;
+	}
 
 	return ret;
 }
diff --git a/common/cmd_usb_mass_storage.c b/common/cmd_usb_mass_storage.c
index ccf7195946..5f557d5f85 100644
--- a/common/cmd_usb_mass_storage.c
+++ b/common/cmd_usb_mass_storage.c
@@ -5,68 +5,89 @@
  * SPDX-License-Identifier:	GPL-2.0+
  */
 
+#include <errno.h>
 #include <common.h>
 #include <command.h>
 #include <g_dnl.h>
+#include <usb.h>
 #include <usb_mass_storage.h>
 
 int do_usb_mass_storage(cmd_tbl_t *cmdtp, int flag,
 			       int argc, char * const argv[])
 {
-	char *ep;
-	unsigned int dev_num = 0, offset = 0, part_size = 0;
-	int rc;
+	if (argc < 3)
+		return CMD_RET_USAGE;
 
-	struct ums_board_info *ums_info;
-	static char *s = "ums";
+	const char *usb_controller = argv[1];
+	const char *mmc_devstring  = argv[2];
 
-	if (argc < 2) {
-		printf("usage: ums <dev> - e.g. ums 0\n");
-		return 0;
-	}
+	unsigned int dev_num = simple_strtoul(mmc_devstring, NULL, 0);
 
-	dev_num = (int)simple_strtoul(argv[1], &ep, 16);
+	struct ums *ums = ums_init(dev_num);
+	if (!ums)
+		return CMD_RET_FAILURE;
 
-	if (dev_num) {
-		puts("\nSet eMMC device to 0! - e.g. ums 0\n");
-		goto fail;
+	unsigned int controller_index = (unsigned int)(simple_strtoul(
+					usb_controller,	NULL, 0));
+	if (board_usb_init(controller_index, USB_INIT_DEVICE)) {
+		error("Couldn't init USB controller.");
+		return CMD_RET_FAILURE;
 	}
 
-	board_usb_init();
-	ums_info = board_ums_init(dev_num, offset, part_size);
-
-	if (!ums_info) {
-		printf("MMC: %d -> NOT available\n", dev_num);
-		goto fail;
-	}
-	rc = fsg_init(ums_info);
+	int rc = fsg_init(ums);
 	if (rc) {
-		printf("cmd ums: fsg_init failed\n");
-		goto fail;
+		error("fsg_init failed");
+		return CMD_RET_FAILURE;
 	}
 
-	g_dnl_register(s);
+	g_dnl_register("ums");
 
-	while (1) {
-		/* Handle control-c and timeouts */
-		if (ctrlc()) {
-			printf("The remote end did not respond in time.\n");
-			goto exit;
+	/* Timeout unit: seconds */
+	int cable_ready_timeout = UMS_CABLE_READY_TIMEOUT;
+
+	if (!usb_cable_connected()) {
+		puts("Please connect USB cable.\n");
+
+		while (!usb_cable_connected()) {
+			if (ctrlc()) {
+				puts("\rCTRL+C - Operation aborted.\n");
+				goto exit;
+			}
+			if (!cable_ready_timeout) {
+				puts("\rUSB cable not detected.\n" \
+				     "Command exit.\n");
+				goto exit;
+			}
+
+			printf("\rAuto exit in: %.2d s.", cable_ready_timeout);
+			mdelay(1000);
+			cable_ready_timeout--;
 		}
+		puts("\r\n");
+	}
+
+	while (1) {
 		usb_gadget_handle_interrupts();
-		/* Check if USB cable has been detached */
-		if (fsg_main_thread(NULL) == EIO)
+
+		rc = fsg_main_thread(NULL);
+		if (rc) {
+			/* Check I/O error */
+			if (rc == -EIO)
+				printf("\rCheck USB cable connection\n");
+
+			/* Check CTRL+C */
+			if (rc == -EPIPE)
+				printf("\rCTRL+C - Operation aborted\n");
+
 			goto exit;
+		}
 	}
 exit:
 	g_dnl_unregister();
-	return 0;
-
-fail:
-	return -1;
+	return CMD_RET_SUCCESS;
 }
 
 U_BOOT_CMD(ums, CONFIG_SYS_MAXARGS, 1, do_usb_mass_storage,
 	"Use the UMS [User Mass Storage]",
-	"ums - User Mass Storage Gadget"
+	"ums <USB_controller> <mmc_dev>  e.g. ums 0 0"
 );
diff --git a/common/cmd_zfs.c b/common/cmd_zfs.c
index 911086809b..0aed29e9b2 100644
--- a/common/cmd_zfs.c
+++ b/common/cmd_zfs.c
@@ -95,7 +95,7 @@ static int do_zfs_load(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]
 	memset(&zfile, 0, sizeof(zfile));
 	zfile.device = &vdev;
 	if (zfs_open(&zfile, filename)) {
-		printf("** File not found %s\n", filename);
+		printf("** File not found %s **\n", filename);
 		return 1;
 	}
 
diff --git a/common/command.c b/common/command.c
index 625571dd4d..746b7e3f0e 100644
--- a/common/command.c
+++ b/common/command.c
@@ -184,10 +184,10 @@ static int complete_cmdv(int argc, char * const argv[], char last_char, int maxv
 		/* output full list of commands */
 		for (; cmdtp != cmdend; cmdtp++) {
 			if (n_found >= maxv - 2) {
-				cmdv[n_found] = "...";
+				cmdv[n_found++] = "...";
 				break;
 			}
-			cmdv[n_found] = cmdtp->name;
+			cmdv[n_found++] = cmdtp->name;
 		}
 		cmdv[n_found] = NULL;
 		return n_found;
@@ -421,6 +421,10 @@ int cmd_get_data_size(char* arg, int default_size)
 			return 2;
 		case 'l':
 			return 4;
+#ifdef CONFIG_SYS_SUPPORT_64BIT_DATA
+		case 'q':
+			return 8;
+#endif
 		case 's':
 			return -2;
 		default:
@@ -538,3 +542,13 @@ enum command_ret_t cmd_process(int flag, int argc, char * const argv[],
 		rc = cmd_usage(cmdtp);
 	return rc;
 }
+
+int cmd_process_error(cmd_tbl_t *cmdtp, int err)
+{
+	if (err) {
+		printf("Command '%s' failed: Error %d\n", cmdtp->name, err);
+		return 1;
+	}
+
+	return 0;
+}
diff --git a/common/console.c b/common/console.c
index cc55068c7c..2dfb788885 100644
--- a/common/console.c
+++ b/common/console.c
@@ -8,6 +8,7 @@
 #include <common.h>
 #include <stdarg.h>
 #include <malloc.h>
+#include <os.h>
 #include <serial.h>
 #include <stdio_dev.h>
 #include <exports.h>
@@ -415,6 +416,12 @@ static inline void print_pre_console_buffer(void) {}
 
 void putc(const char c)
 {
+#ifdef CONFIG_SANDBOX
+	if (!gd) {
+		os_putc(c);
+		return;
+	}
+#endif
 #ifdef CONFIG_SILENT_CONSOLE
 	if (gd->flags & GD_FLG_SILENT)
 		return;
@@ -439,6 +446,13 @@ void putc(const char c)
 
 void puts(const char *s)
 {
+#ifdef CONFIG_SANDBOX
+	if (!gd) {
+		os_puts(s);
+		return;
+	}
+#endif
+
 #ifdef CONFIG_SILENT_CONSOLE
 	if (gd->flags & GD_FLG_SILENT)
 		return;
@@ -467,7 +481,7 @@ int printf(const char *fmt, ...)
 	uint i;
 	char printbuffer[CONFIG_SYS_PBSIZE];
 
-#ifndef CONFIG_PRE_CONSOLE_BUFFER
+#if !defined(CONFIG_SANDBOX) && !defined(CONFIG_PRE_CONSOLE_BUFFER)
 	if (!gd->have_console)
 		return 0;
 #endif
diff --git a/common/cros_ec.c b/common/cros_ec.c
new file mode 100644
index 0000000000..b8ce1b581a
--- /dev/null
+++ b/common/cros_ec.c
@@ -0,0 +1,44 @@
+/*
+ * Copyright (c) 2012 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ *
+ * Alternatively, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") version 2 as published by the Free
+ * Software Foundation.
+ */
+
+#include <common.h>
+#include <cros_ec.h>
+DECLARE_GLOBAL_DATA_PTR;
+
+struct local_info {
+	struct cros_ec_dev *cros_ec_dev;	/* Pointer to cros_ec device */
+	int cros_ec_err;			/* Error for cros_ec, 0 if ok */
+};
+
+static struct local_info local;
+
+struct cros_ec_dev *board_get_cros_ec_dev(void)
+{
+	return local.cros_ec_dev;
+}
+
+static int board_init_cros_ec_devices(const void *blob)
+{
+	local.cros_ec_err = cros_ec_init(blob, &local.cros_ec_dev);
+	if (local.cros_ec_err)
+		return -1;  /* Will report in board_late_init() */
+
+	return 0;
+}
+
+int cros_ec_board_init(void)
+{
+	return board_init_cros_ec_devices(gd->fdt_blob);
+}
+
+int cros_ec_get_error(void)
+{
+	return local.cros_ec_err;
+}
diff --git a/common/env_callback.c b/common/env_callback.c
index 34bb58e4a9..d03fa03a43 100644
--- a/common/env_callback.c
+++ b/common/env_callback.c
@@ -35,6 +35,9 @@ static struct env_clbk_tbl *find_env_callback(const char *name)
 	return NULL;
 }
 
+static int first_call = 1;
+static const char *callback_list;
+
 /*
  * Look for a possible callback for a newly added variable
  * This is called specifically when the variable did not exist in the hash
@@ -43,11 +46,15 @@ static struct env_clbk_tbl *find_env_callback(const char *name)
 void env_callback_init(ENTRY *var_entry)
 {
 	const char *var_name = var_entry->key;
-	const char *callback_list = getenv(ENV_CALLBACK_VAR);
 	char callback_name[256] = "";
 	struct env_clbk_tbl *clbkp;
 	int ret = 1;
 
+	if (first_call) {
+		callback_list = getenv(ENV_CALLBACK_VAR);
+		first_call = 0;
+	}
+
 	/* look in the ".callbacks" var for a reference to this variable */
 	if (callback_list != NULL)
 		ret = env_attr_lookup(callback_list, var_name, callback_name);
diff --git a/common/env_eeprom.c b/common/env_eeprom.c
index 0dcdd1fc80..0db2bb63fe 100644
--- a/common/env_eeprom.c
+++ b/common/env_eeprom.c
@@ -24,7 +24,6 @@ DECLARE_GLOBAL_DATA_PTR;
 env_t *env_ptr;
 
 char *env_name_spec = "EEPROM";
-int env_eeprom_bus = -1;
 
 static int eeprom_bus_read(unsigned dev_addr, unsigned offset,
 			   uchar *buffer, unsigned cnt)
@@ -40,8 +39,7 @@ static int eeprom_bus_read(unsigned dev_addr, unsigned offset,
 	rcode = eeprom_read(dev_addr, offset, buffer, cnt);
 
 #if defined(CONFIG_I2C_ENV_EEPROM_BUS)
-	if (old_bus != env_eeprom_bus)
-		i2c_set_bus_num(old_bus);
+	i2c_set_bus_num(old_bus);
 #endif
 
 	return rcode;
@@ -63,6 +61,7 @@ static int eeprom_bus_write(unsigned dev_addr, unsigned offset,
 #if defined(CONFIG_I2C_ENV_EEPROM_BUS)
 	i2c_set_bus_num(old_bus);
 #endif
+
 	return rcode;
 }
 
diff --git a/common/env_flags.c b/common/env_flags.c
index e9b72e60a9..985f92e50e 100644
--- a/common/env_flags.c
+++ b/common/env_flags.c
@@ -395,6 +395,9 @@ static int env_parse_flags_to_bin(const char *flags)
 	return binflags;
 }
 
+static int first_call = 1;
+static const char *flags_list;
+
 /*
  * Look for possible flags for a newly added variable
  * This is called specifically when the variable did not exist in the hash
@@ -403,10 +406,13 @@ static int env_parse_flags_to_bin(const char *flags)
 void env_flags_init(ENTRY *var_entry)
 {
 	const char *var_name = var_entry->key;
-	const char *flags_list = getenv(ENV_FLAGS_VAR);
 	char flags[ENV_FLAGS_ATTR_MAX_LEN + 1] = "";
 	int ret = 1;
 
+	if (first_call) {
+		flags_list = getenv(ENV_FLAGS_VAR);
+		first_call = 0;
+	}
 	/* look in the ".flags" and static for a reference to this variable */
 	ret = env_flags_lookup(flags_list, var_name, flags);
 
diff --git a/common/env_sf.c b/common/env_sf.c
index 9f806fb090..be270f21bc 100644
--- a/common/env_sf.c
+++ b/common/env_sf.c
@@ -299,13 +299,16 @@ int saveenv(void)
 
 void env_relocate_spec(void)
 {
-	char buf[CONFIG_ENV_SIZE];
 	int ret;
+	char *buf = NULL;
 
+	buf = (char *)malloc(CONFIG_ENV_SIZE);
 	env_flash = spi_flash_probe(CONFIG_ENV_SPI_BUS, CONFIG_ENV_SPI_CS,
 			CONFIG_ENV_SPI_MAX_HZ, CONFIG_ENV_SPI_MODE);
 	if (!env_flash) {
 		set_default_env("!spi_flash_probe() failed");
+		if (buf)
+			free(buf);
 		return;
 	}
 
@@ -321,6 +324,8 @@ void env_relocate_spec(void)
 		gd->env_valid = 1;
 out:
 	spi_flash_free(env_flash);
+	if (buf)
+		free(buf);
 	env_flash = NULL;
 }
 #endif
diff --git a/common/fdt_support.c b/common/fdt_support.c
index 1f0d8f5fe9..f9f358e7e8 100644
--- a/common/fdt_support.c
+++ b/common/fdt_support.c
@@ -21,6 +21,34 @@
  */
 DECLARE_GLOBAL_DATA_PTR;
 
+/*
+ * Get cells len in bytes
+ *     if #NNNN-cells property is 2 then len is 8
+ *     otherwise len is 4
+ */
+static int get_cells_len(void *blob, char *nr_cells_name)
+{
+	const fdt32_t *cell;
+
+	cell = fdt_getprop(blob, 0, nr_cells_name, NULL);
+	if (cell && fdt32_to_cpu(*cell) == 2)
+		return 8;
+
+	return 4;
+}
+
+/*
+ * Write a 4 or 8 byte big endian cell
+ */
+static void write_cell(u8 *addr, u64 val, int size)
+{
+	int shift = (size - 1) * 8;
+	while (size-- > 0) {
+		*addr++ = (val >> shift) & 0xff;
+		shift -= 8;
+	}
+}
+
 /**
  * fdt_getprop_u32_default - Find a node and return it's property or a default
  *
@@ -131,9 +159,9 @@ static int fdt_fixup_stdout(void *fdt, int chosenoff)
 
 int fdt_initrd(void *fdt, ulong initrd_start, ulong initrd_end, int force)
 {
-	int   nodeoffset;
+	int   nodeoffset, addr_cell_len;
 	int   err, j, total;
-	fdt32_t  tmp;
+	fdt64_t  tmp;
 	const char *path;
 	uint64_t addr, size;
 
@@ -170,20 +198,22 @@ int fdt_initrd(void *fdt, ulong initrd_start, ulong initrd_end, int force)
 		return err;
 	}
 
+	addr_cell_len = get_cells_len(fdt, "#address-cells");
+
 	path = fdt_getprop(fdt, nodeoffset, "linux,initrd-start", NULL);
 	if ((path == NULL) || force) {
-		tmp = cpu_to_fdt32(initrd_start);
+		write_cell((u8 *)&tmp, initrd_start, addr_cell_len);
 		err = fdt_setprop(fdt, nodeoffset,
-			"linux,initrd-start", &tmp, sizeof(tmp));
+			"linux,initrd-start", &tmp, addr_cell_len);
 		if (err < 0) {
 			printf("WARNING: "
 				"could not set linux,initrd-start %s.\n",
 				fdt_strerror(err));
 			return err;
 		}
-		tmp = cpu_to_fdt32(initrd_end);
+		write_cell((u8 *)&tmp, initrd_end, addr_cell_len);
 		err = fdt_setprop(fdt, nodeoffset,
-			"linux,initrd-end", &tmp, sizeof(tmp));
+			"linux,initrd-end", &tmp, addr_cell_len);
 		if (err < 0) {
 			printf("WARNING: could not set linux,initrd-end %s.\n",
 				fdt_strerror(err));
@@ -343,34 +373,6 @@ void do_fixup_by_compat_u32(void *fdt, const char *compat,
 	do_fixup_by_compat(fdt, compat, prop, &tmp, 4, create);
 }
 
-/*
- * Get cells len in bytes
- *     if #NNNN-cells property is 2 then len is 8
- *     otherwise len is 4
- */
-static int get_cells_len(void *blob, char *nr_cells_name)
-{
-	const fdt32_t *cell;
-
-	cell = fdt_getprop(blob, 0, nr_cells_name, NULL);
-	if (cell && fdt32_to_cpu(*cell) == 2)
-		return 8;
-
-	return 4;
-}
-
-/*
- * Write a 4 or 8 byte big endian cell
- */
-static void write_cell(u8 *addr, u64 val, int size)
-{
-	int shift = (size - 1) * 8;
-	while (size-- > 0) {
-		*addr++ = (val >> shift) & 0xff;
-		shift -= 8;
-	}
-}
-
 #ifdef CONFIG_NR_DRAM_BANKS
 #define MEMORY_BANKS_MAX CONFIG_NR_DRAM_BANKS
 #else
@@ -400,10 +402,11 @@ int fdt_fixup_memory_banks(void *blob, u64 start[], u64 size[], int banks)
 	nodeoffset = fdt_path_offset(blob, "/memory");
 	if (nodeoffset < 0) {
 		nodeoffset = fdt_add_subnode(blob, 0, "memory");
-		if (nodeoffset < 0)
+		if (nodeoffset < 0) {
 			printf("WARNING: could not create /memory: %s.\n",
 					fdt_strerror(nodeoffset));
-		return nodeoffset;
+			return nodeoffset;
+		}
 	}
 	err = fdt_setprop(blob, nodeoffset, "device_type", "memory",
 			sizeof("memory"));
diff --git a/common/hash.c b/common/hash.c
index 722c40b3f3..872cd85428 100644
--- a/common/hash.c
+++ b/common/hash.c
@@ -325,8 +325,8 @@ int hash_command(const char *algo_name, int flags, cmd_tbl_t *cmdtp, int flag,
 		printf("CRC32 for %08lx ... %08lx ==> %08lx\n",
 				addr, addr + len - 1, crc);
 
-		if (argc > 3) {
-			ptr = (ulong *)simple_strtoul(argv[3], NULL, 16);
+		if (argc >= 3) {
+			ptr = (ulong *)simple_strtoul(argv[0], NULL, 16);
 			*ptr = crc;
 		}
 	}
diff --git a/common/hush.c b/common/hush.c
index 3f3a79c508..df10267d64 100644
--- a/common/hush.c
+++ b/common/hush.c
@@ -221,6 +221,8 @@ struct child_prog {
 	pid_t pid;					/* 0 if exited */
 #endif
 	char **argv;				/* program name and arguments */
+	/* was quoted when parsed; copy of struct o_string.nonnull field */
+	int *argv_nonnull;			
 #ifdef __U_BOOT__
 	int    argc;                            /* number of program arguments */
 #endif
@@ -467,7 +469,7 @@ static int process_command_subs(o_string *dest, struct p_context *ctx, struct in
 static int parse_group(o_string *dest, struct p_context *ctx, struct in_str *input, int ch);
 #endif
 static char *lookup_param(char *src);
-static char *make_string(char **inp);
+static char *make_string(char **inp, int *nonnull);
 static int handle_dollar(o_string *dest, struct p_context *ctx, struct in_str *input);
 #ifndef __U_BOOT__
 static int parse_string(o_string *dest, struct p_context *ctx, const char *src);
@@ -1613,7 +1615,8 @@ static int run_pipe_real(struct pipe *pi)
 		if (child->sp) {
 			char * str = NULL;
 
-			str = make_string((child->argv + i));
+			str = make_string(child->argv + i,
+					  child->argv_nonnull + i);
 			parse_string_outer(str, FLAG_EXIT_FROM_LOOP | FLAG_REPARSING);
 			free(str);
 			return last_return_code;
@@ -1940,7 +1943,8 @@ static int free_pipe(struct pipe *pi, int indent)
 			for (a = 0; a < child->argc; a++) {
 				free(child->argv[a]);
 			}
-					free(child->argv);
+			free(child->argv);
+			free(child->argv_nonnull);
 			child->argc = 0;
 #endif
 			child->argv=NULL;
@@ -2470,8 +2474,14 @@ static int done_word(o_string *dest, struct p_context *ctx)
 		argc = ++child->argc;
 		child->argv = realloc(child->argv, (argc+1)*sizeof(*child->argv));
 		if (child->argv == NULL) return 1;
+		child->argv_nonnull = realloc(child->argv_nonnull,
+					(argc+1)*sizeof(*child->argv_nonnull));
+		if (child->argv_nonnull == NULL)
+			return 1;
 		child->argv[argc-1]=str;
+		child->argv_nonnull[argc-1] = dest->nonnull;
 		child->argv[argc]=NULL;
+		child->argv_nonnull[argc] = 0;
 		for (s = dest->data; s && *s; s++,str++) {
 			if (*s == '\\') s++;
 			*str = *s;
@@ -2537,6 +2547,7 @@ static int done_command(struct p_context *ctx)
 	prog->redirects = NULL;
 #endif
 	prog->argv = NULL;
+	prog->argv_nonnull = NULL;
 #ifndef __U_BOOT__
 	prog->is_stopped = 0;
 #endif
@@ -3585,8 +3596,12 @@ static char **make_list_in(char **inp, char *name)
 	return list;
 }
 
-/* Make new string for parser */
-static char * make_string(char ** inp)
+/*
+ * Make new string for parser
+ * inp     - array of argument strings to flatten
+ * nonnull - indicates argument was quoted when originally parsed
+ */
+static char *make_string(char **inp, int *nonnull)
 {
 	char *p;
 	char *str = NULL;
@@ -3600,13 +3615,17 @@ static char * make_string(char ** inp)
 		noeval = 1;
 	for (n = 0; inp[n]; n++) {
 		p = insert_var_value_sub(inp[n], noeval);
-		str = xrealloc(str, (len + strlen(p)));
+		str = xrealloc(str, (len + strlen(p) + (2 * nonnull[n])));
 		if (n) {
 			strcat(str, " ");
 		} else {
 			*str = '\0';
 		}
+		if (nonnull[n])
+			strcat(str, "'");
 		strcat(str, p);
+		if (nonnull[n])
+			strcat(str, "'");
 		len = strlen(str) + 3;
 		if (p != inp[n]) free(p);
 	}
diff --git a/common/image-fdt.c b/common/image-fdt.c
index 6f9ce7d37c..a54a919a5b 100644
--- a/common/image-fdt.c
+++ b/common/image-fdt.c
@@ -463,7 +463,7 @@ int image_setup_libfdt(bootm_headers_t *images, void *blob,
 		return -1;
 	}
 	arch_fixup_memory_node(blob);
-	if (IMAAGE_OF_BOARD_SETUP)
+	if (IMAGE_OF_BOARD_SETUP)
 		ft_board_setup(blob, gd->bd);
 	fdt_fixup_ethernet(blob);
 
diff --git a/common/image-fit.c b/common/image-fit.c
index cf4b67e3e8..b94a3fe86d 100644
--- a/common/image-fit.c
+++ b/common/image-fit.c
@@ -1500,7 +1500,7 @@ int fit_image_load(bootm_headers_t *images, const char *prop_name, ulong addr,
 	}
 	bootstage_mark(bootstage_id + BOOTSTAGE_SUB_FORMAT_OK);
 	if (fit_uname) {
-		/* get ramdisk component image node offset */
+		/* get FIT component image node offset */
 		bootstage_mark(bootstage_id + BOOTSTAGE_SUB_UNIT_NAME);
 		noffset = fit_image_get_node(fit, fit_uname);
 	} else {
diff --git a/common/image.c b/common/image.c
index b0ae58ff3e..9c6bec5b76 100644
--- a/common/image.c
+++ b/common/image.c
@@ -81,6 +81,8 @@ static const table_entry_t uimage_arch[] = {
 	{	IH_ARCH_NDS32,		"nds32",	"NDS32",	},
 	{	IH_ARCH_OPENRISC,	"or1k",		"OpenRISC 1000",},
 	{	IH_ARCH_SANDBOX,	"sandbox",	"Sandbox",	},
+	{	IH_ARCH_ARM64,		"arm64",	"AArch64",	},
+	{	IH_ARCH_ARC,		"arc",		"ARC",		},
 	{	-1,			"",		"",		},
 };
 
@@ -95,9 +97,9 @@ static const table_entry_t uimage_os[] = {
 	{	IH_OS_PLAN9,	"plan9",	"Plan 9",		},
 	{	IH_OS_RTEMS,	"rtems",	"RTEMS",		},
 	{	IH_OS_U_BOOT,	"u-boot",	"U-Boot",		},
+	{	IH_OS_VXWORKS,	"vxworks",	"VxWorks",		},
 #if defined(CONFIG_CMD_ELF) || defined(USE_HOSTCC)
 	{	IH_OS_QNX,	"qnx",		"QNX",			},
-	{	IH_OS_VXWORKS,	"vxworks",	"VxWorks",		},
 #endif
 #if defined(CONFIG_INTEGRITY) || defined(USE_HOSTCC)
 	{	IH_OS_INTEGRITY,"integrity",	"INTEGRITY",		},
diff --git a/common/lcd.c b/common/lcd.c
index 5dd7948121..19b86b7c55 100644
--- a/common/lcd.c
+++ b/common/lcd.c
@@ -26,8 +26,10 @@
 #endif
 #include <lcd.h>
 #include <watchdog.h>
-
+#include <asm/unaligned.h>
 #include <splash.h>
+#include <asm/io.h>
+#include <asm/unaligned.h>
 
 #if defined(CONFIG_CPU_PXA25X) || defined(CONFIG_CPU_PXA27X) || \
 	defined(CONFIG_CPU_MONAHANS)
@@ -63,6 +65,10 @@
 # endif
 #endif
 
+#ifdef CONFIG_SANDBOX
+#include <asm/sdl.h>
+#endif
+
 #ifndef CONFIG_LCD_ALIGNMENT
 #define CONFIG_LCD_ALIGNMENT PAGE_SIZE
 #endif
@@ -144,6 +150,13 @@ void lcd_sync(void)
 	if (lcd_flush_dcache)
 		flush_dcache_range((u32)lcd_base,
 			(u32)(lcd_base + lcd_get_size(&line_length)));
+#elif defined(CONFIG_SANDBOX) && defined(CONFIG_VIDEO_SANDBOX_SDL)
+	static ulong last_sync;
+
+	if (get_timer(last_sync) > 10) {
+		sandbox_sdl_sync(lcd_base);
+		last_sync = get_timer(0);
+	}
 #endif
 }
 
@@ -386,8 +399,13 @@ static void test_pattern(void)
 /************************************************************************/
 /* ** GENERIC Initialization Routines					*/
 /************************************************************************/
-
-int lcd_get_size(int *line_length)
+/*
+ * With most lcd drivers the line length is set up
+ * by calculating it from panel_info parameters. Some
+ * drivers need to calculate the line length differently,
+ * so make the function weak to allow overriding it.
+ */
+__weak int lcd_get_size(int *line_length)
 {
 	*line_length = (panel_info.vl_col * NBITS(panel_info.vl_bpix)) / 8;
 	return *line_length * panel_info.vl_row;
@@ -398,7 +416,7 @@ int drv_lcd_init(void)
 	struct stdio_dev lcddev;
 	int rc;
 
-	lcd_base = (void *) gd->fb_base;
+	lcd_base = map_sysmem(gd->fb_base, 0);
 
 	lcd_init(lcd_base);		/* LCD initialization */
 
@@ -489,13 +507,12 @@ static int lcd_init(void *lcdbase)
 	 * by setting up gd->fb_base. Check for this condition and fixup
 	 * 'lcd_base' address.
 	 */
-	if ((unsigned long)lcdbase != gd->fb_base)
-		lcd_base = (void *)gd->fb_base;
+	if (map_to_sysmem(lcdbase) != gd->fb_base)
+		lcd_base = map_sysmem(gd->fb_base, 0);
 
 	debug("[LCD] Using LCD frambuffer at %p\n", lcd_base);
 
 	lcd_get_size(&lcd_line_length);
-	lcd_line_length = (panel_info.vl_col * NBITS(panel_info.vl_bpix)) / 8;
 	lcd_is_enabled = 1;
 	lcd_clear();
 	lcd_enable();
@@ -773,9 +790,9 @@ static void lcd_display_rle8_bitmap(bmp_image_t *bmp, ushort *cmap, uchar *fb,
 	int x, y;
 	int decode = 1;
 
-	width = le32_to_cpu(bmp->header.width);
-	height = le32_to_cpu(bmp->header.height);
-	bmap = (uchar *)bmp + le32_to_cpu(bmp->header.data_offset);
+	width = get_unaligned_le32(&bmp->header.width);
+	height = get_unaligned_le32(&bmp->header.height);
+	bmap = (uchar *)bmp + get_unaligned_le32(&bmp->header.data_offset);
 
 	x = 0;
 	y = height - 1;
@@ -882,7 +899,7 @@ int lcd_display_bitmap(ulong bmp_image, int x, int y)
 	ushort *cmap_base = NULL;
 	ushort i, j;
 	uchar *fb;
-	bmp_image_t *bmp=(bmp_image_t *)bmp_image;
+	bmp_image_t *bmp = (bmp_image_t *)map_sysmem(bmp_image, 0);
 	uchar *bmap;
 	ushort padded_width;
 	unsigned long width, height, byte_width;
@@ -896,9 +913,10 @@ int lcd_display_bitmap(ulong bmp_image, int x, int y)
 		return 1;
 	}
 
-	width = le32_to_cpu(bmp->header.width);
-	height = le32_to_cpu(bmp->header.height);
-	bmp_bpix = le16_to_cpu(bmp->header.bit_count);
+	width = get_unaligned_le32(&bmp->header.width);
+	height = get_unaligned_le32(&bmp->header.height);
+	bmp_bpix = get_unaligned_le16(&bmp->header.bit_count);
+
 	colors = 1 << bmp_bpix;
 
 	bpix = NBITS(panel_info.vl_bpix);
@@ -913,9 +931,7 @@ int lcd_display_bitmap(ulong bmp_image, int x, int y)
 	/* We support displaying 8bpp BMPs on 16bpp LCDs */
 	if (bpix != bmp_bpix && !(bmp_bpix == 8 && bpix == 16)) {
 		printf ("Error: %d bit/pixel mode, but BMP has %d bit/pixel\n",
-			bpix,
-			le16_to_cpu(bmp->header.bit_count));
-
+			bpix, get_unaligned_le16(&bmp->header.bit_count));
 		return 1;
 	}
 
@@ -952,7 +968,6 @@ int lcd_display_bitmap(ulong bmp_image, int x, int y)
 		}
 	}
 #endif
-
 	/*
 	 *  BMP format for Monochrome assumes that the state of a
 	 * pixel is described on a per Bit basis, not per Byte.
@@ -983,15 +998,16 @@ int lcd_display_bitmap(ulong bmp_image, int x, int y)
 	if ((y + height) > panel_info.vl_row)
 		height = panel_info.vl_row - y;
 
-	bmap = (uchar *) bmp + le32_to_cpu(bmp->header.data_offset);
-	fb   = (uchar *) (lcd_base +
+	bmap = (uchar *)bmp + get_unaligned_le32(&bmp->header.data_offset);
+	fb   = (uchar *)(lcd_base +
 		(y + height - 1) * lcd_line_length + x * bpix / 8);
 
 	switch (bmp_bpix) {
 	case 1: /* pass through */
 	case 8:
 #ifdef CONFIG_LCD_BMP_RLE8
-		if (le32_to_cpu(bmp->header.compression) == BMP_BI_RLE8) {
+		u32 compression = get_unaligned_le32(&bmp->header.compression);
+		if (compression == BMP_BI_RLE8) {
 			if (bpix != 16) {
 				/* TODO implement render code for bpix != 16 */
 				printf("Error: only support 16 bpix");
diff --git a/common/main.c b/common/main.c
index 6f475f0cca..8b6f274fa2 100644
--- a/common/main.c
+++ b/common/main.c
@@ -392,13 +392,13 @@ static void process_boot_delay(void)
 	debug ("### main_loop: bootcmd=\"%s\"\n", s ? s : "<UNDEFINED>");
 
 	if (bootdelay != -1 && s && !abortboot(bootdelay)) {
-#ifdef CONFIG_AUTOBOOT_KEYED
+#if defined(CONFIG_AUTOBOOT_KEYED) && !defined(CONFIG_AUTOBOOT_KEYED_CTRLC)
 		int prev = disable_ctrlc(1);	/* disable Control C checking */
 #endif
 
 		run_command_list(s, -1, 0);
 
-#ifdef CONFIG_AUTOBOOT_KEYED
+#if defined(CONFIG_AUTOBOOT_KEYED) && !defined(CONFIG_AUTOBOOT_KEYED_CTRLC)
 		disable_ctrlc(prev);	/* restore Control C checking */
 #endif
 	}
diff --git a/common/memsize.c b/common/memsize.c
index 73b92c8a00..589400d3b1 100644
--- a/common/memsize.c
+++ b/common/memsize.c
@@ -5,7 +5,10 @@
  * SPDX-License-Identifier:	GPL-2.0+
  */
 
-#include <config.h>
+#include <common.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
 #ifdef __PPC__
 /*
  * At least on G2 PowerPC cores, sequential accesses to non-existent
@@ -76,3 +79,14 @@ long get_ram_size(long *base, long maxsize)
 
 	return (maxsize);
 }
+
+phys_size_t __weak get_effective_memsize(void)
+{
+#ifndef CONFIG_VERY_BIG_RAM
+	return gd->ram_size;
+#else
+	/* limit stack to what we can reasonable map */
+	return ((gd->ram_size > CONFIG_MAX_MEM_MAPPED) ?
+		CONFIG_MAX_MEM_MAPPED : gd->ram_size);
+#endif
+}
diff --git a/common/spl/Makefile b/common/spl/Makefile
index e8144f7040..64569c2cc6 100644
--- a/common/spl/Makefile
+++ b/common/spl/Makefile
@@ -8,34 +8,15 @@
 # Based on common/Makefile.
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)libspl.o
-
 ifdef CONFIG_SPL_BUILD
-COBJS-$(CONFIG_SPL_FRAMEWORK) += spl.o
-COBJS-$(CONFIG_SPL_NOR_SUPPORT) += spl_nor.o
-COBJS-$(CONFIG_SPL_YMODEM_SUPPORT) += spl_ymodem.o
-COBJS-$(CONFIG_SPL_NAND_SUPPORT) += spl_nand.o
-COBJS-$(CONFIG_SPL_ONENAND_SUPPORT) += spl_onenand.o
-COBJS-$(CONFIG_SPL_NET_SUPPORT) += spl_net.o
-COBJS-$(CONFIG_SPL_MMC_SUPPORT) += spl_mmc.o
+obj-$(CONFIG_SPL_FRAMEWORK) += spl.o
+obj-$(CONFIG_SPL_NOR_SUPPORT) += spl_nor.o
+obj-$(CONFIG_SPL_YMODEM_SUPPORT) += spl_ymodem.o
+obj-$(CONFIG_SPL_NAND_SUPPORT) += spl_nand.o
+obj-$(CONFIG_SPL_ONENAND_SUPPORT) += spl_onenand.o
+obj-$(CONFIG_SPL_NET_SUPPORT) += spl_net.o
+obj-$(CONFIG_SPL_MMC_SUPPORT) += spl_mmc.o
+obj-$(CONFIG_SPL_USB_SUPPORT) += spl_usb.o
+obj-$(CONFIG_SPL_FAT_SUPPORT) += spl_fat.o
+obj-$(CONFIG_SPL_SATA_SUPPORT) += spl_sata.o
 endif
-
-COBJS	:= $(sort $(COBJS-y))
-SRCS	:= $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS-y))
-
-all:	$(obj).depend $(LIB)
-
-$(LIB):	$(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
diff --git a/common/spl/spl.c b/common/spl/spl.c
index da31457d5f..774fdad252 100644
--- a/common/spl/spl.c
+++ b/common/spl/spl.c
@@ -205,6 +205,16 @@ void board_init_r(gd_t *dummy1, ulong dummy2)
 		spl_net_load_image("usb_ether");
 		break;
 #endif
+#ifdef CONFIG_SPL_USB_SUPPORT
+	case BOOT_DEVICE_USB:
+		spl_usb_load_image();
+		break;
+#endif
+#ifdef CONFIG_SPL_SATA_SUPPORT
+	case BOOT_DEVICE_SATA:
+		spl_sata_load_image();
+		break;
+#endif
 	default:
 		debug("SPL: Un-supported Boot Device\n");
 		hang();
diff --git a/common/spl/spl_fat.c b/common/spl/spl_fat.c
new file mode 100644
index 0000000000..1e532d5963
--- /dev/null
+++ b/common/spl/spl_fat.c
@@ -0,0 +1,96 @@
+/*
+ * (C) Copyright 2014
+ * Texas Instruments, <www.ti.com>
+ *
+ * Dan Murphy <dmurphy@ti.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ *
+ * FAT Image Functions copied from spl_mmc.c
+ */
+
+#include <common.h>
+#include <spl.h>
+#include <asm/u-boot.h>
+#include <fat.h>
+#include <image.h>
+
+static int fat_registered;
+
+#ifdef CONFIG_SPL_FAT_SUPPORT
+static int spl_register_fat_device(block_dev_desc_t *block_dev, int partition)
+{
+	int err = 0;
+
+	if (fat_registered)
+		return err;
+
+	err = fat_register_device(block_dev, partition);
+	if (err) {
+#ifdef CONFIG_SPL_LIBCOMMON_SUPPORT
+		printf("%s: fat register err - %d\n", __func__, err);
+#endif
+		hang();
+	}
+
+	fat_registered = 1;
+
+	return err;
+}
+
+int spl_load_image_fat(block_dev_desc_t *block_dev,
+						int partition,
+						const char *filename)
+{
+	int err;
+	struct image_header *header;
+
+	err = spl_register_fat_device(block_dev, partition);
+	if (err)
+		goto end;
+
+	header = (struct image_header *)(CONFIG_SYS_TEXT_BASE -
+						sizeof(struct image_header));
+
+	err = file_fat_read(filename, header, sizeof(struct image_header));
+	if (err <= 0)
+		goto end;
+
+	spl_parse_image_header(header);
+
+	err = file_fat_read(filename, (u8 *)spl_image.load_addr, 0);
+
+end:
+#ifdef CONFIG_SPL_LIBCOMMON_SUPPORT
+	if (err <= 0)
+		printf("%s: error reading image %s, err - %d\n",
+		       __func__, filename, err);
+#endif
+
+	return (err <= 0);
+}
+
+#ifdef CONFIG_SPL_OS_BOOT
+int spl_load_image_fat_os(block_dev_desc_t *block_dev, int partition)
+{
+	int err;
+
+	err = spl_register_fat_device(block_dev, partition);
+	if (err)
+		return err;
+
+	err = file_fat_read(CONFIG_SPL_FAT_LOAD_ARGS_NAME,
+			    (void *)CONFIG_SYS_SPL_ARGS_ADDR, 0);
+	if (err <= 0) {
+#ifdef CONFIG_SPL_LIBCOMMON_SUPPORT
+		printf("%s: error reading image %s, err - %d\n",
+		       __func__, CONFIG_SPL_FAT_LOAD_ARGS_NAME, err);
+#endif
+		return -1;
+	}
+
+	return spl_load_image_fat(block_dev, partition,
+			CONFIG_SPL_FAT_LOAD_KERNEL_NAME);
+}
+#endif
+#endif
diff --git a/common/spl/spl_mmc.c b/common/spl/spl_mmc.c
index fc2f2260f8..fa6f891bc8 100644
--- a/common/spl/spl_mmc.c
+++ b/common/spl/spl_mmc.c
@@ -10,7 +10,6 @@
 #include <spl.h>
 #include <asm/u-boot.h>
 #include <mmc.h>
-#include <fat.h>
 #include <version.h>
 #include <image.h>
 
@@ -69,54 +68,6 @@ static int mmc_load_image_raw_os(struct mmc *mmc)
 }
 #endif
 
-#ifdef CONFIG_SPL_FAT_SUPPORT
-static int mmc_load_image_fat(struct mmc *mmc, const char *filename)
-{
-	int err;
-	struct image_header *header;
-
-	header = (struct image_header *)(CONFIG_SYS_TEXT_BASE -
-						sizeof(struct image_header));
-
-	err = file_fat_read(filename, header, sizeof(struct image_header));
-	if (err <= 0)
-		goto end;
-
-	spl_parse_image_header(header);
-
-	err = file_fat_read(filename, (u8 *)spl_image.load_addr, 0);
-
-end:
-#ifdef CONFIG_SPL_LIBCOMMON_SUPPORT
-	if (err <= 0)
-		printf("spl: error reading image %s, err - %d\n",
-		       filename, err);
-#endif
-
-	return (err <= 0);
-}
-
-#ifdef CONFIG_SPL_OS_BOOT
-static int mmc_load_image_fat_os(struct mmc *mmc)
-{
-	int err;
-
-	err = file_fat_read(CONFIG_SPL_FAT_LOAD_ARGS_NAME,
-			    (void *)CONFIG_SYS_SPL_ARGS_ADDR, 0);
-	if (err <= 0) {
-#ifdef CONFIG_SPL_LIBCOMMON_SUPPORT
-		printf("spl: error reading image %s, err - %d\n",
-		       CONFIG_SPL_FAT_LOAD_ARGS_NAME, err);
-#endif
-		return -1;
-	}
-
-	return mmc_load_image_fat(mmc, CONFIG_SPL_FAT_LOAD_KERNEL_NAME);
-}
-#endif
-
-#endif
-
 void spl_mmc_load_image(void)
 {
 	struct mmc *mmc;
@@ -148,24 +99,41 @@ void spl_mmc_load_image(void)
 		if (spl_start_uboot() || mmc_load_image_raw_os(mmc))
 #endif
 		err = mmc_load_image_raw(mmc,
-					 CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR);
+			CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR);
 #ifdef CONFIG_SPL_FAT_SUPPORT
 	} else if (boot_mode == MMCSD_MODE_FAT) {
 		debug("boot mode - FAT\n");
-
-		err = fat_register_device(&mmc->block_dev,
-					  CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION);
-		if (err) {
+#ifdef CONFIG_SPL_OS_BOOT
+		if (spl_start_uboot() || spl_load_image_fat_os(&mmc->block_dev,
+								CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION))
+#endif
+		err = spl_load_image_fat(&mmc->block_dev,
+					CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION,
+					CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME);
+#endif
+#ifdef CONFIG_SUPPORT_EMMC_BOOT
+	} else if (boot_mode == MMCSD_MODE_EMMCBOOT) {
+		/*
+		 * We need to check what the partition is configured to.
+		 * 1 and 2 match up to boot0 / boot1 and 7 is user data
+		 * which is the first physical partition (0).
+		 */
+		int part = (mmc->part_config >> 3) & PART_ACCESS_MASK;
+
+		if (part == 7)
+			part = 0;
+
+		if (mmc_switch_part(0, part)) {
 #ifdef CONFIG_SPL_LIBCOMMON_SUPPORT
-			printf("spl: fat register err - %d\n", err);
+			puts("MMC partition switch failed\n");
 #endif
 			hang();
 		}
-
 #ifdef CONFIG_SPL_OS_BOOT
-		if (spl_start_uboot() || mmc_load_image_fat_os(mmc))
+		if (spl_start_uboot() || mmc_load_image_raw_os(mmc))
 #endif
-		err = mmc_load_image_fat(mmc, CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME);
+		err = mmc_load_image_raw(mmc,
+			CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR);
 #endif
 	} else {
 #ifdef CONFIG_SPL_LIBCOMMON_SUPPORT
diff --git a/common/spl/spl_sata.c b/common/spl/spl_sata.c
new file mode 100644
index 0000000000..2e7adca0ca
--- /dev/null
+++ b/common/spl/spl_sata.c
@@ -0,0 +1,49 @@
+/*
+ * (C) Copyright 2013
+ * Texas Instruments, <www.ti.com>
+ *
+ * Dan Murphy <dmurphy@ti.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ *
+ * Derived work from spl_usb.c
+ */
+
+#include <common.h>
+#include <spl.h>
+#include <asm/u-boot.h>
+#include <sata.h>
+#include <fat.h>
+#include <version.h>
+#include <image.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void spl_sata_load_image(void)
+{
+	int err;
+	block_dev_desc_t *stor_dev;
+
+	err = init_sata(CONFIG_SPL_SATA_BOOT_DEVICE);
+	if (err) {
+#ifdef CONFIG_SPL_LIBCOMMON_SUPPORT
+		printf("spl: sata init failed: err - %d\n", err);
+#endif
+		hang();
+	} else {
+		/* try to recognize storage devices immediately */
+		stor_dev = scsi_get_dev(0);
+	}
+
+#ifdef CONFIG_SPL_OS_BOOT
+	if (spl_start_uboot() || spl_load_image_fat_os(stor_dev,
+									CONFIG_SYS_SATA_FAT_BOOT_PARTITION))
+#endif
+	err = spl_load_image_fat(stor_dev,
+				CONFIG_SYS_SATA_FAT_BOOT_PARTITION,
+				CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME);
+	if (err) {
+		puts("Error loading sata device\n");
+		hang();
+	}
+}
diff --git a/common/spl/spl_usb.c b/common/spl/spl_usb.c
new file mode 100644
index 0000000000..53a9043795
--- /dev/null
+++ b/common/spl/spl_usb.c
@@ -0,0 +1,58 @@
+/*
+ * (C) Copyright 2014
+ * Texas Instruments, <www.ti.com>
+ *
+ * Dan Murphy <dmurphy@ti.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ *
+ * Derived work from spl_mmc.c
+ */
+
+#include <common.h>
+#include <spl.h>
+#include <asm/u-boot.h>
+#include <usb.h>
+#include <fat.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#ifdef CONFIG_USB_STORAGE
+static int usb_stor_curr_dev = -1; /* current device */
+#endif
+
+void spl_usb_load_image(void)
+{
+	int err;
+	block_dev_desc_t *stor_dev;
+
+	usb_stop();
+	err = usb_init();
+	if (err) {
+#ifdef CONFIG_SPL_LIBCOMMON_SUPPORT
+		printf("%s: usb init failed: err - %d\n", __func__, err);
+#endif
+		hang();
+	}
+
+#ifdef CONFIG_USB_STORAGE
+	/* try to recognize storage devices immediately */
+	usb_stor_curr_dev = usb_stor_scan(1);
+	stor_dev = usb_stor_get_dev(usb_stor_curr_dev);
+#endif
+
+	debug("boot mode - FAT\n");
+
+#ifdef CONFIG_SPL_OS_BOOT
+		if (spl_start_uboot() || spl_load_image_fat_os(stor_dev,
+								CONFIG_SYS_USB_FAT_BOOT_PARTITION))
+#endif
+		err = spl_load_image_fat(stor_dev,
+				CONFIG_SYS_USB_FAT_BOOT_PARTITION,
+				CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME);
+
+		if (err) {
+			puts("Error loading USB device\n");
+			hang();
+		}
+}
diff --git a/common/usb.c b/common/usb.c
index c97f522bed..60daa10052 100644
--- a/common/usb.c
+++ b/common/usb.c
@@ -33,6 +33,7 @@
 #include <linux/ctype.h>
 #include <asm/byteorder.h>
 #include <asm/unaligned.h>
+#include <compiler.h>
 
 #include <usb.h>
 #ifdef CONFIG_4xx
@@ -74,7 +75,7 @@ int usb_init(void)
 	for (i = 0; i < CONFIG_USB_MAX_CONTROLLER_COUNT; i++) {
 		/* init low_level USB */
 		printf("USB%d:   ", i);
-		if (usb_lowlevel_init(i, &ctrl)) {
+		if (usb_lowlevel_init(i, USB_INIT_HOST, &ctrl)) {
 			puts("lowlevel init failed\n");
 			continue;
 		}
@@ -855,6 +856,16 @@ void usb_free_device(void)
 }
 
 /*
+ * XHCI issues Enable Slot command and thereafter
+ * allocates device contexts. Provide a weak alias
+ * function for the purpose, so that XHCI overrides it
+ * and EHCI/OHCI just work out of the box.
+ */
+__weak int usb_alloc_device(struct usb_device *udev)
+{
+	return 0;
+}
+/*
  * By the time we get here, the device has gotten a new device ID
  * and is in the default state. We need to identify the thing and
  * get the ball rolling..
@@ -867,6 +878,17 @@ int usb_new_device(struct usb_device *dev)
 	int tmp;
 	ALLOC_CACHE_ALIGN_BUFFER(unsigned char, tmpbuf, USB_BUFSIZ);
 
+	/*
+	 * Allocate usb 3.0 device context.
+	 * USB 3.0 (xHCI) protocol tries to allocate device slot
+	 * and related data structures first. This call does that.
+	 * Refer to sec 4.3.2 in xHCI spec rev1.0
+	 */
+	if (usb_alloc_device(dev)) {
+		printf("Cannot allocate device context to get SLOT_ID\n");
+		return -1;
+	}
+
 	/* We still haven't set the Address yet */
 	addr = dev->devnum;
 	dev->devnum = 0;
@@ -897,7 +919,7 @@ int usb_new_device(struct usb_device *dev)
 	 * http://sourceforge.net/mailarchive/forum.php?
 	 * thread_id=5729457&forum_id=5398
 	 */
-	struct usb_device_descriptor *desc;
+	__maybe_unused struct usb_device_descriptor *desc;
 	int port = -1;
 	struct usb_device *parent = dev->parent;
 	unsigned short portstatus;
@@ -914,6 +936,13 @@ int usb_new_device(struct usb_device *dev)
 	dev->epmaxpacketin[0] = 64;
 	dev->epmaxpacketout[0] = 64;
 
+	/*
+	 * XHCI needs to issue a Address device command to setup
+	 * proper device context structures, before it can interact
+	 * with the device. So a get_descriptor will fail before any
+	 * of that is done for XHCI unlike EHCI.
+	 */
+#ifndef CONFIG_USB_XHCI
 	err = usb_get_descriptor(dev, USB_DT_DEVICE, 0, desc, 64);
 	if (err < 0) {
 		debug("usb_new_device: usb_get_descriptor() failed\n");
@@ -926,11 +955,12 @@ int usb_new_device(struct usb_device *dev)
 	 * to differentiate between HUB and DEVICE.
 	 */
 	dev->descriptor.bDeviceClass = desc->bDeviceClass;
+#endif
 
-	/* find the port number we're at */
 	if (parent) {
 		int j;
 
+		/* find the port number we're at */
 		for (j = 0; j < parent->maxchild; j++) {
 			if (parent->children[j] == dev) {
 				port = j;
@@ -1037,4 +1067,9 @@ int usb_new_device(struct usb_device *dev)
 	return 0;
 }
 
+__weak
+int board_usb_init(int index, enum usb_init_type init)
+{
+	return 0;
+}
 /* EOF */
diff --git a/config.mk b/config.mk
index 91a8f2406b..05864aabb5 100644
--- a/config.mk
+++ b/config.mk
@@ -6,382 +6,59 @@
 #
 #########################################################################
 
-# Set shell to bash if possible, otherwise fall back to sh
-SHELL := $(shell if [ -x "$$BASH" ]; then echo $$BASH; \
-	else if [ -x /bin/bash ]; then echo /bin/bash; \
-	else echo sh; fi; fi)
-
-export	SHELL
-
-ifeq ($(CONFIG_TPL_BUILD),y)
-SPL_BIN := u-boot-tpl
-else
-SPL_BIN := u-boot-spl
-endif
-
-ifeq ($(CURDIR),$(SRCTREE))
-dir :=
-else
-dir := $(subst $(SRCTREE)/,,$(CURDIR))
-endif
-
-ifneq ($(OBJTREE),$(SRCTREE))
-# Create object files for SPL in a separate directory
-ifeq ($(CONFIG_SPL_BUILD),y)
-ifeq ($(CONFIG_TPL_BUILD),y)
-obj := $(if $(dir),$(TPLTREE)/$(dir)/,$(TPLTREE)/)
-else
-obj := $(if $(dir),$(SPLTREE)/$(dir)/,$(SPLTREE)/)
-endif
-else
-obj := $(if $(dir),$(OBJTREE)/$(dir)/,$(OBJTREE)/)
-endif
-src := $(if $(dir),$(SRCTREE)/$(dir)/,$(SRCTREE)/)
-
-$(shell mkdir -p $(obj))
-else
-# Create object files for SPL in a separate directory
-ifeq ($(CONFIG_SPL_BUILD),y)
-ifeq ($(CONFIG_TPL_BUILD),y)
-obj := $(if $(dir),$(TPLTREE)/$(dir)/,$(TPLTREE)/)
-else
-obj := $(if $(dir),$(SPLTREE)/$(dir)/,$(SPLTREE)/)
-
-endif
-$(shell mkdir -p $(obj))
-else
-obj :=
-endif
-src :=
-endif
-
-# clean the slate ...
-PLATFORM_RELFLAGS =
-PLATFORM_CPPFLAGS =
-PLATFORM_LDFLAGS =
-
-#########################################################################
-
-HOSTCFLAGS	= -Wall -Wstrict-prototypes -O2 -fomit-frame-pointer \
-		  $(HOSTCPPFLAGS)
-HOSTSTRIP	= strip
-
-#
-# Mac OS X / Darwin's C preprocessor is Apple specific.  It
-# generates numerous errors and warnings.  We want to bypass it
-# and use GNU C's cpp.	To do this we pass the -traditional-cpp
-# option to the compiler.  Note that the -traditional-cpp flag
-# DOES NOT have the same semantics as GNU C's flag, all it does
-# is invoke the GNU preprocessor in stock ANSI/ISO C fashion.
-#
-# Apple's linker is similar, thanks to the new 2 stage linking
-# multiple symbol definitions are treated as errors, hence the
-# -multiply_defined suppress option to turn off this error.
+# This file is included from ./Makefile and spl/Makefile.
+# Clean the state to avoid the same flags added twice.
 #
-
-ifeq ($(HOSTOS),darwin)
-# get major and minor product version (e.g. '10' and '6' for Snow Leopard)
-DARWIN_MAJOR_VERSION	= $(shell sw_vers -productVersion | cut -f 1 -d '.')
-DARWIN_MINOR_VERSION	= $(shell sw_vers -productVersion | cut -f 2 -d '.')
-
-os_x_before	= $(shell if [ $(DARWIN_MAJOR_VERSION) -le $(1) -a \
-	$(DARWIN_MINOR_VERSION) -le $(2) ] ; then echo "$(3)"; else echo "$(4)"; fi ;)
-
-# Snow Leopards build environment has no longer restrictions as described above
-HOSTCC		 = $(call os_x_before, 10, 5, "cc", "gcc")
-HOSTCFLAGS	+= $(call os_x_before, 10, 4, "-traditional-cpp")
-HOSTLDFLAGS	+= $(call os_x_before, 10, 5, "-multiply_defined suppress")
-else
-HOSTCC		= gcc
-endif
-
-ifeq ($(HOSTOS),cygwin)
-HOSTCFLAGS	+= -ansi
-endif
-
-# We build some files with extra pedantic flags to try to minimize things
-# that won't build on some weird host compiler -- though there are lots of
-# exceptions for files that aren't complaint.
-
-HOSTCFLAGS_NOPED = $(filter-out -pedantic,$(HOSTCFLAGS))
-HOSTCFLAGS	+= -pedantic
-
+# (Tegra needs different flags for SPL.
+#  That's the reason why this file must be included from spl/Makefile too.
+#  If we did not have Tegra SoCs, build system would be much simpler...)
+PLATFORM_RELFLAGS :=
+PLATFORM_CPPFLAGS :=
+PLATFORM_LDFLAGS :=
+LDFLAGS :=
+LDFLAGS_FINAL :=
+OBJCOPYFLAGS :=
 #########################################################################
-#
-# Option checker, gcc version (courtesy linux kernel) to ensure
-# only supported compiler options are used
-#
-CC_OPTIONS_CACHE_FILE := $(OBJTREE)/include/generated/cc_options.mk
-CC_TEST_OFILE := $(OBJTREE)/include/generated/cc_test_file.o
-
--include $(CC_OPTIONS_CACHE_FILE)
-
-cc-option-sys = $(shell mkdir -p $(dir $(CC_TEST_OFILE)); \
-		if $(CC) $(CFLAGS) $(1) -S -xc /dev/null -o $(CC_TEST_OFILE) \
-		> /dev/null 2>&1; then \
-		echo 'CC_OPTIONS += $(strip $1)' >> $(CC_OPTIONS_CACHE_FILE); \
-		echo "$(1)"; fi)
-
-ifeq ($(CONFIG_CC_OPT_CACHE_DISABLE),y)
-cc-option = $(strip $(if $(call cc-option-sys,$1),$1,$2))
-else
-cc-option = $(strip $(if $(findstring $1,$(CC_OPTIONS)),$1,\
-		$(if $(call cc-option-sys,$1),$1,$2)))
-endif
-
-# cc-version
-# Usage gcc-ver := $(call cc-version)
-cc-version = $(shell $(SHELL) $(SRCTREE)/tools/gcc-version.sh $(CC))
-binutils-version = $(shell $(SHELL) $(SRCTREE)/tools/binutils-version.sh $(AS))
-dtc-version = $(shell $(SHELL) $(SRCTREE)/tools/dtc-version.sh $(DTC))
-
-#
-# Include the make variables (CC, etc...)
-#
-AS	= $(CROSS_COMPILE)as
-
-# Always use GNU ld
-LD	= $(shell if $(CROSS_COMPILE)ld.bfd -v > /dev/null 2>&1; \
-		then echo "$(CROSS_COMPILE)ld.bfd"; else echo "$(CROSS_COMPILE)ld"; fi;)
-
-CC	= $(CROSS_COMPILE)gcc
-CPP	= $(CC) -E
-AR	= $(CROSS_COMPILE)ar
-NM	= $(CROSS_COMPILE)nm
-LDR	= $(CROSS_COMPILE)ldr
-STRIP	= $(CROSS_COMPILE)strip
-OBJCOPY = $(CROSS_COMPILE)objcopy
-OBJDUMP = $(CROSS_COMPILE)objdump
-RANLIB	= $(CROSS_COMPILE)RANLIB
-DTC	= dtc
-CHECK	= sparse
-
-#########################################################################
-
-# Load generated board configuration
-ifeq ($(CONFIG_TPL_BUILD),y)
-# Include TPL autoconf
-sinclude $(OBJTREE)/include/tpl-autoconf.mk
-else
-ifeq ($(CONFIG_SPL_BUILD),y)
-# Include SPL autoconf
-sinclude $(OBJTREE)/include/spl-autoconf.mk
-else
-# Include normal autoconf
-sinclude $(OBJTREE)/include/autoconf.mk
-endif
-endif
-sinclude $(OBJTREE)/include/config.mk
 
 # Some architecture config.mk files need to know what CPUDIR is set to,
 # so calculate CPUDIR before including ARCH/SOC/CPU config.mk files.
 # Check if arch/$ARCH/cpu/$CPU exists, otherwise assume arch/$ARCH/cpu contains
 # CPU-specific code.
 CPUDIR=arch/$(ARCH)/cpu/$(CPU)
-ifneq ($(SRCTREE)/$(CPUDIR),$(wildcard $(SRCTREE)/$(CPUDIR)))
+ifneq ($(srctree)/$(CPUDIR),$(wildcard $(srctree)/$(CPUDIR)))
 CPUDIR=arch/$(ARCH)/cpu
 endif
 
-sinclude $(TOPDIR)/arch/$(ARCH)/config.mk	# include architecture dependend rules
-sinclude $(TOPDIR)/$(CPUDIR)/config.mk		# include  CPU	specific rules
+sinclude $(srctree)/arch/$(ARCH)/config.mk	# include architecture dependend rules
+sinclude $(srctree)/$(CPUDIR)/config.mk		# include  CPU	specific rules
 
 ifdef	SOC
-sinclude $(TOPDIR)/$(CPUDIR)/$(SOC)/config.mk	# include  SoC	specific rules
+sinclude $(srctree)/$(CPUDIR)/$(SOC)/config.mk	# include  SoC	specific rules
 endif
+ifneq ($(BOARD),)
 ifdef	VENDOR
 BOARDDIR = $(VENDOR)/$(BOARD)
 else
 BOARDDIR = $(BOARD)
 endif
+endif
 ifdef	BOARD
-sinclude $(TOPDIR)/board/$(BOARDDIR)/config.mk	# include board specific rules
+sinclude $(srctree)/board/$(BOARDDIR)/config.mk	# include board specific rules
 endif
 
 #########################################################################
 
-# We don't actually use $(ARFLAGS) anywhere anymore, so catch people
-# who are porting old code to latest mainline but not updating $(AR).
-ARFLAGS = $(error update your Makefile to use cmd_link_o_target and not AR)
-RELFLAGS= $(PLATFORM_RELFLAGS)
-DBGFLAGS= -g # -DDEBUG
-OPTFLAGS= -Os #-fomit-frame-pointer
-
-OBJCFLAGS += --gap-fill=0xff
+RELFLAGS := $(PLATFORM_RELFLAGS)
 
-gccincdir := $(shell $(CC) -print-file-name=include)
+OBJCOPYFLAGS += --gap-fill=0xff
 
-CPPFLAGS := $(DBGFLAGS) $(OPTFLAGS) $(RELFLAGS)		\
-	-D__KERNEL__
-
-# Enable garbage collection of un-used sections for SPL
-ifeq ($(CONFIG_SPL_BUILD),y)
-CPPFLAGS += -ffunction-sections -fdata-sections
-LDFLAGS_FINAL += --gc-sections
-endif
-
-# TODO(sjg@chromium.org): Is this correct on Mac OS?
-
-# MXSImage needs LibSSL
-ifneq ($(CONFIG_MX23)$(CONFIG_MX28),)
-HOSTLIBS	+= -lssl -lcrypto
-# Add CONFIG_MXS into host CFLAGS, so we can check whether or not register
-# the mxsimage support within tools/mxsimage.c .
-HOSTCFLAGS	+= -DCONFIG_MXS
-endif
-
-ifdef CONFIG_FIT_SIGNATURE
-HOSTLIBS	+= -lssl -lcrypto
-
-# This affects include/image.h, but including the board config file
-# is tricky, so manually define this options here.
-HOSTCFLAGS	+= -DCONFIG_FIT_SIGNATURE
-endif
-
-ifneq ($(CONFIG_SYS_TEXT_BASE),)
-CPPFLAGS += -DCONFIG_SYS_TEXT_BASE=$(CONFIG_SYS_TEXT_BASE)
-endif
-
-ifeq ($(CONFIG_SPL_BUILD),y)
-CPPFLAGS += -DCONFIG_SPL_BUILD
-ifeq ($(CONFIG_TPL_BUILD),y)
-CPPFLAGS += -DCONFIG_TPL_BUILD
-endif
-endif
-
-# Does this architecture support generic board init?
-ifeq ($(__HAVE_ARCH_GENERIC_BOARD),)
-ifneq ($(CONFIG_SYS_GENERIC_BOARD),)
-CHECK_GENERIC_BOARD = $(error Your architecture does not support generic board. \
-Please undefined CONFIG_SYS_GENERIC_BOARD in your board config file)
-endif
-endif
-
-ifneq ($(OBJTREE),$(SRCTREE))
-CPPFLAGS += -I$(OBJTREE)/include2 -I$(OBJTREE)/include
-endif
-
-CPPFLAGS += -I$(TOPDIR)/include
-CPPFLAGS += -fno-builtin -ffreestanding -nostdinc	\
-	-isystem $(gccincdir) -pipe $(PLATFORM_CPPFLAGS)
-
-CFLAGS := $(CPPFLAGS) -Wall -Wstrict-prototypes
-
-ifdef BUILD_TAG
-CFLAGS += -DBUILD_TAG='"$(BUILD_TAG)"'
-endif
-
-CFLAGS_SSP := $(call cc-option,-fno-stack-protector)
-CFLAGS += $(CFLAGS_SSP)
-# Some toolchains enable security related warning flags by default,
-# but they don't make much sense in the u-boot world, so disable them.
-CFLAGS_WARN := $(call cc-option,-Wno-format-nonliteral) \
-	       $(call cc-option,-Wno-format-security)
-CFLAGS += $(CFLAGS_WARN)
-
-# Report stack usage if supported
-CFLAGS_STACK := $(call cc-option,-fstack-usage)
-CFLAGS += $(CFLAGS_STACK)
-
-BCURDIR = $(subst $(SRCTREE)/,,$(CURDIR:$(obj)%=%))
-
-ifeq ($(findstring examples/,$(BCURDIR)),)
-ifeq ($(CONFIG_SPL_BUILD),)
-ifdef FTRACE
-CFLAGS += -finstrument-functions -DFTRACE
-endif
-endif
-endif
-
-# $(CPPFLAGS) sets -g, which causes gcc to pass a suitable -g<format>
-# option to the assembler.
-AFLAGS_DEBUG :=
-
-# turn jbsr into jsr for m68k
-ifeq ($(ARCH),m68k)
-ifeq ($(findstring 3.4,$(shell $(CC) --version)),3.4)
-AFLAGS_DEBUG := -Wa,-gstabs,-S
-endif
-endif
-
-AFLAGS := $(AFLAGS_DEBUG) -D__ASSEMBLY__ $(CPPFLAGS)
+PLATFORM_CPPFLAGS += $(RELFLAGS)
+PLATFORM_CPPFLAGS += -pipe
 
 LDFLAGS += $(PLATFORM_LDFLAGS)
 LDFLAGS_FINAL += -Bstatic
 
-LDFLAGS_u-boot += -T $(obj)u-boot.lds $(LDFLAGS_FINAL)
-ifneq ($(CONFIG_SYS_TEXT_BASE),)
-LDFLAGS_u-boot += -Ttext $(CONFIG_SYS_TEXT_BASE)
-endif
-
-LDFLAGS_$(SPL_BIN) += -T $(obj)u-boot-spl.lds $(LDFLAGS_FINAL)
-ifneq ($(CONFIG_SPL_TEXT_BASE),)
-LDFLAGS_$(SPL_BIN) += -Ttext $(CONFIG_SPL_TEXT_BASE)
-endif
-
-# Linus' kernel sanity checking tool
-CHECKFLAGS     := -D__linux__ -Dlinux -D__STDC__ -Dunix -D__unix__ \
-		  -Wbitwise -Wno-return-void -D__CHECK_ENDIAN__ $(CF)
-
-# Location of a usable BFD library, where we define "usable" as
-# "built for ${HOST}, supports ${TARGET}".  Sensible values are
-# - When cross-compiling: the root of the cross-environment
-# - Linux/ppc (native): /usr
-# - NetBSD/ppc (native): you lose ... (must extract these from the
-#   binutils build directory, plus the native and U-Boot include
-#   files don't like each other)
-#
-# So far, this is used only by tools/gdb/Makefile.
-
-ifeq ($(HOSTOS),darwin)
-BFD_ROOT_DIR =		/usr/local/tools
-else
-ifeq ($(HOSTARCH),$(ARCH))
-# native
-BFD_ROOT_DIR =		/usr
-else
-#BFD_ROOT_DIR =		/LinuxPPC/CDK		# Linux/i386
-#BFD_ROOT_DIR =		/usr/pkg/cross		# NetBSD/i386
-BFD_ROOT_DIR =		/opt/powerpc
-endif
-endif
-
-#########################################################################
-
-export	HOSTCC HOSTCFLAGS HOSTLDFLAGS PEDCFLAGS HOSTSTRIP CROSS_COMPILE \
-	AS LD CC CPP AR NM STRIP OBJCOPY OBJDUMP MAKE
-export	CONFIG_SYS_TEXT_BASE PLATFORM_CPPFLAGS PLATFORM_RELFLAGS CPPFLAGS CFLAGS AFLAGS
-
-#########################################################################
-
-# Allow boards to use custom optimize flags on a per dir/file basis
-ALL_AFLAGS = $(AFLAGS) $(AFLAGS_$(BCURDIR)/$(@F)) $(AFLAGS_$(BCURDIR))
-ALL_CFLAGS = $(CFLAGS) $(CFLAGS_$(BCURDIR)/$(@F)) $(CFLAGS_$(BCURDIR))
-EXTRA_CPPFLAGS = $(CPPFLAGS_$(BCURDIR)/$(@F)) $(CPPFLAGS_$(BCURDIR))
-ALL_CFLAGS += $(EXTRA_CPPFLAGS)
-
-# The _DEP version uses the $< file target (for dependency generation)
-# See rules.mk
-EXTRA_CPPFLAGS_DEP = $(CPPFLAGS_$(BCURDIR)/$(addsuffix .o,$(basename $<))) \
-		$(CPPFLAGS_$(BCURDIR))
-$(obj)%.s:	%.S
-	$(CPP) $(ALL_AFLAGS) -o $@ $<
-$(obj)%.o:	%.S
-	$(CC)  $(ALL_AFLAGS) -o $@ $< -c
-$(obj)%.o:	%.c
-ifneq ($(CHECKSRC),0)
-	$(CHECK) $(CHECKFLAGS) $(ALL_CFLAGS) $<
-endif
-	$(CC)  $(ALL_CFLAGS) -o $@ $< -c
-$(obj)%.i:	%.c
-	$(CPP) $(ALL_CFLAGS) -o $@ $< -c
-$(obj)%.s:	%.c
-	$(CC)  $(ALL_CFLAGS) -o $@ $< -c -S
-
-#########################################################################
-
-# If the list of objects to link is empty, just create an empty built-in.o
-cmd_link_o_target = $(if $(strip $1),\
-		      $(LD) $(LDFLAGS) -r -o $@ $1,\
-		      rm -f $@; $(AR) rcs $@ )
-
-#########################################################################
+export PLATFORM_CPPFLAGS
+export RELFLAGS
+export LDFLAGS_FINAL
+export CONFIG_STANDALONE_LOAD_ADDR
diff --git a/disk/Makefile b/disk/Makefile
index 2b04e03dec..6970cecc71 100644
--- a/disk/Makefile
+++ b/disk/Makefile
@@ -5,33 +5,11 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-#CFLAGS += -DET_DEBUG -DDEBUG
-
-LIB	= $(obj)libdisk.o
-
-COBJS-$(CONFIG_PARTITIONS) 	+= part.o
-COBJS-$(CONFIG_MAC_PARTITION)   += part_mac.o
-COBJS-$(CONFIG_DOS_PARTITION)   += part_dos.o
-COBJS-$(CONFIG_ISO_PARTITION)   += part_iso.o
-COBJS-$(CONFIG_AMIGA_PARTITION) += part_amiga.o
-COBJS-$(CONFIG_EFI_PARTITION)   += part_efi.o
-
-COBJS	:= $(COBJS-y)
-SRCS	:= $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-
-all:	$(LIB)
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+#ccflags-y += -DET_DEBUG -DDEBUG
+
+obj-$(CONFIG_PARTITIONS) 	+= part.o
+obj-$(CONFIG_MAC_PARTITION)   += part_mac.o
+obj-$(CONFIG_DOS_PARTITION)   += part_dos.o
+obj-$(CONFIG_ISO_PARTITION)   += part_iso.o
+obj-$(CONFIG_AMIGA_PARTITION) += part_amiga.o
+obj-$(CONFIG_EFI_PARTITION)   += part_efi.o
diff --git a/disk/part.c b/disk/part.c
index d2e34cfcfa..b8c6aac801 100644
--- a/disk/part.c
+++ b/disk/part.c
@@ -43,6 +43,9 @@ static const struct block_drvr block_drvr[] = {
 #if defined(CONFIG_SYSTEMACE)
 	{ .name = "ace", .get_dev = systemace_get_dev, },
 #endif
+#if defined(CONFIG_SANDBOX)
+	{ .name = "host", .get_dev = host_get_dev, },
+#endif
 	{ },
 };
 
@@ -286,6 +289,9 @@ static void print_part_header (const char *type, block_dev_desc_t * dev_desc)
 	case IF_TYPE_MMC:
 		puts ("MMC");
 		break;
+	case IF_TYPE_HOST:
+		puts("HOST");
+		break;
 	default:
 		puts ("UNKNOWN");
 		break;
@@ -446,23 +452,6 @@ int get_device_and_partition(const char *ifname, const char *dev_part_str,
 	int part;
 	disk_partition_t tmpinfo;
 
-	/*
-	 * For now, we have a special case for sandbox, since there is no
-	 * real block device support.
-	 */
-	if (0 == strcmp(ifname, "host")) {
-		*dev_desc = NULL;
-		info->start = info->size =  info->blksz = 0;
-		info->bootable = 0;
-		strcpy((char *)info->type, BOOT_PART_TYPE);
-		strcpy((char *)info->name, "Sandbox host");
-#ifdef CONFIG_PARTITION_UUIDS
-		info->uuid[0] = 0;
-#endif
-
-		return 0;
-	}
-
 	/* If no dev_part_str, use bootdevice environment variable */
 	if (!dev_part_str || !strlen(dev_part_str) ||
 	    !strcmp(dev_part_str, "-"))
diff --git a/disk/part_efi.c b/disk/part_efi.c
index 9c33ae7a31..216a2920c2 100644
--- a/disk/part_efi.c
+++ b/disk/part_efi.c
@@ -63,26 +63,6 @@ static char *print_efiname(gpt_entry *pte)
 	return name;
 }
 
-static void uuid_string(unsigned char *uuid, char *str)
-{
-	static const u8 le[16] = {3, 2, 1, 0, 5, 4, 7, 6, 8, 9, 10, 11,
-				  12, 13, 14, 15};
-	int i;
-
-	for (i = 0; i < 16; i++) {
-		sprintf(str, "%02x", uuid[le[i]]);
-		str += 2;
-		switch (i) {
-		case 3:
-		case 5:
-		case 7:
-		case 9:
-			*str++ = '-';
-			break;
-		}
-	}
-}
-
 static efi_guid_t system_guid = PARTITION_SYSTEM_GUID;
 
 static inline int is_bootable(gpt_entry *p)
@@ -103,6 +83,7 @@ void print_part_efi(block_dev_desc_t * dev_desc)
 	gpt_entry *gpt_pte = NULL;
 	int i = 0;
 	char uuid[37];
+	unsigned char *uuid_bin;
 
 	if (!dev_desc) {
 		printf("%s: Invalid Argument(s)\n", __func__);
@@ -119,8 +100,8 @@ void print_part_efi(block_dev_desc_t * dev_desc)
 
 	printf("Part\tStart LBA\tEnd LBA\t\tName\n");
 	printf("\tAttributes\n");
-	printf("\tType UUID\n");
-	printf("\tPartition UUID\n");
+	printf("\tType GUID\n");
+	printf("\tPartition GUID\n");
 
 	for (i = 0; i < le32_to_cpu(gpt_head->num_partition_entries); i++) {
 		/* Stop at the first non valid PTE */
@@ -132,10 +113,12 @@ void print_part_efi(block_dev_desc_t * dev_desc)
 			le64_to_cpu(gpt_pte[i].ending_lba),
 			print_efiname(&gpt_pte[i]));
 		printf("\tattrs:\t0x%016llx\n", gpt_pte[i].attributes.raw);
-		uuid_string(gpt_pte[i].partition_type_guid.b, uuid);
+		uuid_bin = (unsigned char *)gpt_pte[i].partition_type_guid.b;
+		uuid_bin_to_str(uuid_bin, uuid, UUID_STR_FORMAT_GUID);
 		printf("\ttype:\t%s\n", uuid);
-		uuid_string(gpt_pte[i].unique_partition_guid.b, uuid);
-		printf("\tuuid:\t%s\n", uuid);
+		uuid_bin = (unsigned char *)gpt_pte[i].unique_partition_guid.b;
+		uuid_bin_to_str(uuid_bin, uuid, UUID_STR_FORMAT_GUID);
+		printf("\tguid:\t%s\n", uuid);
 	}
 
 	/* Remember to free pte */
@@ -182,7 +165,8 @@ int get_partition_info_efi(block_dev_desc_t * dev_desc, int part,
 	sprintf((char *)info->type, "U-Boot");
 	info->bootable = is_bootable(&gpt_pte[part - 1]);
 #ifdef CONFIG_PARTITION_UUIDS
-	uuid_string(gpt_pte[part - 1].unique_partition_guid.b, info->uuid);
+	uuid_bin_to_str(gpt_pte[part - 1].unique_partition_guid.b, info->uuid,
+			UUID_STR_FORMAT_GUID);
 #endif
 
 	debug("%s: start 0x" LBAF ", size 0x" LBAF ", name %s", __func__,
@@ -213,10 +197,10 @@ int test_part_efi(block_dev_desc_t * dev_desc)
  */
 static int set_protective_mbr(block_dev_desc_t *dev_desc)
 {
-	legacy_mbr *p_mbr;
-
 	/* Setup the Protective MBR */
-	p_mbr = calloc(1, sizeof(p_mbr));
+	ALLOC_CACHE_ALIGN_BUFFER(legacy_mbr, p_mbr, 1);
+	memset(p_mbr, 0, sizeof(*p_mbr));
+
 	if (p_mbr == NULL) {
 		printf("%s: calloc failed!\n", __func__);
 		return -1;
@@ -231,65 +215,9 @@ static int set_protective_mbr(block_dev_desc_t *dev_desc)
 	if (dev_desc->block_write(dev_desc->dev, 0, 1, p_mbr) != 1) {
 		printf("** Can't write to device %d **\n",
 			dev_desc->dev);
-		free(p_mbr);
-		return -1;
-	}
-
-	free(p_mbr);
-	return 0;
-}
-
-/**
- * string_uuid(); Convert UUID stored as string to bytes
- *
- * @param uuid - UUID represented as string
- * @param dst - GUID buffer
- *
- * @return return 0 on successful conversion
- */
-static int string_uuid(char *uuid, u8 *dst)
-{
-	efi_guid_t guid;
-	u16 b, c, d;
-	u64 e;
-	u32 a;
-	u8 *p;
-	u8 i;
-
-	const u8 uuid_str_len = 36;
-
-	/* The UUID is written in text: */
-	/* 1        9    14   19   24 */
-	/* xxxxxxxx-xxxx-xxxx-xxxx-xxxxxxxxxxxx */
-
-	debug("%s: uuid: %s\n", __func__, uuid);
-
-	if (strlen(uuid) != uuid_str_len)
 		return -1;
-
-	for (i = 0; i < uuid_str_len; i++) {
-		if ((i == 8) || (i == 13) || (i == 18) || (i == 23)) {
-			if (uuid[i] != '-')
-				return -1;
-		} else {
-			if (!isxdigit(uuid[i]))
-				return -1;
-		}
 	}
 
-	a = (u32)simple_strtoul(uuid, NULL, 16);
-	b = (u16)simple_strtoul(uuid + 9, NULL, 16);
-	c = (u16)simple_strtoul(uuid + 14, NULL, 16);
-	d = (u16)simple_strtoul(uuid + 19, NULL, 16);
-	e = (u64)simple_strtoull(uuid + 24, NULL, 16);
-
-	p = (u8 *) &e;
-	guid = EFI_GUID(a, b, c, d >> 8, d & 0xFF,
-			*(p + 5), *(p + 4), *(p + 3),
-			*(p + 2), *(p + 1) , *p);
-
-	memcpy(dst, guid.b, sizeof(efi_guid_t));
-
 	return 0;
 }
 
@@ -360,6 +288,7 @@ int gpt_fill_pte(gpt_header *gpt_h, gpt_entry *gpt_e,
 	size_t efiname_len, dosname_len;
 #ifdef CONFIG_PARTITION_UUIDS
 	char *str_uuid;
+	unsigned char *bin_uuid;
 #endif
 
 	for (i = 0; i < parts; i++) {
@@ -393,7 +322,9 @@ int gpt_fill_pte(gpt_header *gpt_h, gpt_entry *gpt_e,
 
 #ifdef CONFIG_PARTITION_UUIDS
 		str_uuid = partitions[i].uuid;
-		if (string_uuid(str_uuid, gpt_e[i].unique_partition_guid.b)) {
+		bin_uuid = gpt_e[i].unique_partition_guid.b;
+
+		if (uuid_str_to_bin(str_uuid, bin_uuid, UUID_STR_FORMAT_STD)) {
 			printf("Partition no. %d: invalid guid: %s\n",
 				i, str_uuid);
 			return -1;
@@ -440,7 +371,7 @@ int gpt_fill_header(block_dev_desc_t *dev_desc, gpt_header *gpt_h,
 	gpt_h->header_crc32 = 0;
 	gpt_h->partition_entry_array_crc32 = 0;
 
-	if (string_uuid(str_guid, gpt_h->disk_guid.b))
+	if (uuid_str_to_bin(str_guid, gpt_h->disk_guid.b, UUID_STR_FORMAT_GUID))
 		return -1;
 
 	return 0;
diff --git a/doc/DocBook/.gitignore b/doc/DocBook/.gitignore
index 90c1b112a1..720f245ceb 100644
--- a/doc/DocBook/.gitignore
+++ b/doc/DocBook/.gitignore
@@ -1,4 +1,3 @@
-*/
 *.xml
 *.ps
 *.pdf
diff --git a/doc/DocBook/Makefile b/doc/DocBook/Makefile
index 29b79d7cd1..9b4a9b6762 100644
--- a/doc/DocBook/Makefile
+++ b/doc/DocBook/Makefile
@@ -1,14 +1,12 @@
 ###
 # This makefile is used to generate the kernel documentation,
 # primarily based on in-line comments in various source files.
-# See doc/kernel-doc-nano-HOWTO.txt for instruction in how
+# See Documentation/kernel-doc-nano-HOWTO.txt for instruction in how
 # to document the SRC - and how to read it.
 # To add a new book the only step required is to add the book to the
 # list of DOCBOOKS.
 
-include $(TOPDIR)/config.mk
-
-DOCBOOKS := fs.xml linker_lists.xml stdio.xml
+DOCBOOKS := linker_lists.xml stdio.xml
 
 ###
 # The build process is as follows (targets):
@@ -26,9 +24,9 @@ PS_METHOD	= $(prefer-db2x)
 
 ###
 # The targets that may be used.
-PHONY += $(obj).depend xmldocs sgmldocs psdocs pdfdocs htmldocs mandocs installmandocs cleandocs
+PHONY += xmldocs sgmldocs psdocs pdfdocs htmldocs mandocs installmandocs cleandocs
 
-BOOKS := $(addprefix $(OBJTREE)/doc/DocBook/,$(DOCBOOKS))
+BOOKS := $(addprefix $(obj)/,$(DOCBOOKS))
 xmldocs: $(BOOKS)
 sgmldocs: xmldocs
 
@@ -53,10 +51,10 @@ installmandocs: mandocs
 
 ###
 #External programs used
-KERNELDOC = $(SRCTREE)/tools/kernel-doc/kernel-doc
-DOCPROC   = $(OBJTREE)/tools/kernel-doc/docproc
+KERNELDOC = $(srctree)/scripts/kernel-doc
+DOCPROC   = $(objtree)/scripts/docproc
 
-XMLTOFLAGS = -m $(SRCTREE)/doc/DocBook/stylesheet.xsl
+XMLTOFLAGS = -m $(srctree)/doc/DocBook/stylesheet.xsl
 XMLTOFLAGS += --skip-validation
 
 ###
@@ -66,28 +64,36 @@ XMLTOFLAGS += --skip-validation
 #     appropriate parameters.
 # The following rules are used to generate the .xml documentation
 # required to generate the final targets. (ps, pdf, html).
-%.xml: %.tmpl
-	$(DOCPROC) doc $< >$@
-
-ifeq ($@, "cleandocs")
-sinclude $(obj).depend
-$(obj).depend: $(patsubst %.xml, %.tmpl, $(DOCBOOKS))
-	rm -f $(obj).depend ;					\
-	touch $(obj).depend ;					\
-	for file in $^ ; do					\
-		xmlfile=`echo "$${file}" |			\
-			sed "s/tmpl$$/xml/"` ;			\
-		echo -n "$${xmlfile}: ">> $(obj).depend ;	\
-		$(DOCPROC) depend $$file >> $(obj).depend ;	\
-		echo -e "\n\t$(DOCPROC) doc $< >$${xmlfile} " >>	\
-			$(obj).depend ;				\
-	done
+quiet_cmd_docproc = DOCPROC $@
+      cmd_docproc = SRCTREE=$(srctree)/ $(DOCPROC) doc $< >$@
+define rule_docproc
+	set -e;								\
+        $(if $($(quiet)cmd_$(1)),echo '  $($(quiet)cmd_$(1))';) 	\
+        $(cmd_$(1)); 							\
+        ( 								\
+          echo 'cmd_$@ := $(cmd_$(1))'; 				\
+          echo $@: `SRCTREE=$(srctree) $(DOCPROC) depend $<`; 		\
+        ) > $(dir $@).$(notdir $@).cmd
+endef
+
+%.xml: %.tmpl FORCE
+	$(call if_changed_rule,docproc)
+
+###
+#Read in all saved dependency files
+cmd_files := $(wildcard $(foreach f,$(BOOKS),$(dir $(f)).$(notdir $(f)).cmd))
+
+ifneq ($(cmd_files),)
+  include $(cmd_files)
 endif
 
 ###
 # Changes in kernel-doc force a rebuild of all documentation
 $(BOOKS): $(KERNELDOC)
 
+# Tell kbuild to always build the programs
+always := $(hostprogs-y)
+
 notfoundtemplate = echo "*** You have to install docbook-utils or xmlto ***"; \
 		   exit 1
 db2xtemplate = db2TYPE -o $(dir $@) $<
@@ -113,37 +119,34 @@ endif
 quiet_cmd_db2ps = PS      $@
       cmd_db2ps = $(subst TYPE,ps, $($(PS_METHOD)template))
 %.ps : %.xml
-	$(call cmd_db2ps)
+	$(call cmd,db2ps)
 
 quiet_cmd_db2pdf = PDF     $@
       cmd_db2pdf = $(subst TYPE,pdf, $($(PDF_METHOD)template))
 %.pdf : %.xml
-	$(call cmd_db2pdf)
+	$(call cmd,db2pdf)
 
 
 index = index.html
-main_idx = $(index)
+main_idx = doc/DocBook/$(index)
 build_main_index = rm -rf $(main_idx); \
 		   echo '<h1>U-Boot Bootloader HTML Documentation</h1>' >> $(main_idx) && \
-		   echo '<h2>U-Boot Version: $(U_BOOT_VERSION)</h2>' >> $(main_idx) && \
+		   echo '<h2>U-Boot Version: $(UBOOTVERSION)</h2>' >> $(main_idx) && \
 		   cat $(HTML) >> $(main_idx)
 
-# To work around bug [1] in docbook-xsl-stylesheets 1.76.1 , generate only html
-# docs instead of xhtml with xmlto.
-# [1] http://bugs.debian.org/cgi-bin/bugreport.cgi?bug=654338
 quiet_cmd_db2html = HTML    $@
-      cmd_db2html = xmlto html $(XMLTOFLAGS) -o $(patsubst %.html,%,$@) $< && \
+      cmd_db2html = xmlto xhtml $(XMLTOFLAGS) -o $(patsubst %.html,%,$@) $< && \
 		echo '<a HREF="$(patsubst %.html,%,$(notdir $@))/index.html"> \
-	$(patsubst %.html,%,$(notdir $@))</a><p>' > $@
+        $(patsubst %.html,%,$(notdir $@))</a><p>' > $@
 
 %.html:	%.xml
 	@(which xmlto > /dev/null 2>&1) || \
 	 (echo "*** You need to install xmlto ***"; \
 	  exit 1)
 	@rm -rf $@ $(patsubst %.html,%,$@)
-	$(call cmd_db2html)
+	$(call cmd,db2html)
 	@if [ ! -z "$(PNG-$(basename $(notdir $@)))" ]; then \
-	    cp $(PNG-$(basename $(notdir $@))) $(patsubst %.html,%,$@); fi
+            cp $(PNG-$(basename $(notdir $@))) $(patsubst %.html,%,$@); fi
 
 quiet_cmd_db2man = MAN     $@
       cmd_db2man = if grep -q refentry $<; then xmlto man $(XMLTOFLAGS) -o $(obj)/man $< ; gzip -f $(obj)/man/*.9; fi
@@ -151,8 +154,8 @@ quiet_cmd_db2man = MAN     $@
 	@(which xmlto > /dev/null 2>&1) || \
 	 (echo "*** You need to install xmlto ***"; \
 	  exit 1)
-	$(Q)mkdir -p $(obj)man
-	$(call cmd_db2man)
+	$(Q)mkdir -p $(obj)/man
+	$(call cmd,db2man)
 	@touch $@
 
 ###
@@ -164,7 +167,7 @@ quiet_cmd_fig2eps = FIG2EPS $@
 	@(which fig2dev > /dev/null 2>&1) || \
 	 (echo "*** You need to install transfig ***"; \
 	  exit 1)
-	$(call cmd_fig2eps)
+	$(call cmd,fig2eps)
 
 quiet_cmd_fig2png = FIG2PNG $@
       cmd_fig2png = fig2dev -Lpng $< $@
@@ -173,7 +176,7 @@ quiet_cmd_fig2png = FIG2PNG $@
 	@(which fig2dev > /dev/null 2>&1) || \
 	 (echo "*** You need to install transfig ***"; \
 	  exit 1)
-	$(call cmd_fig2png)
+	$(call cmd,fig2png)
 
 ###
 # Rule to convert a .c file to inline XML documentation
@@ -219,9 +222,8 @@ clean-files := $(DOCBOOKS) \
 clean-dirs := $(patsubst %.xml,%,$(DOCBOOKS)) man
 
 cleandocs:
-	@rm -f $(obj).depend
-	@$(Q)rm -f $(call objectify, $(clean-files))
-	@$(Q)rm -rf $(call objectify, $(clean-dirs))
+	$(Q)rm -f $(call objectify, $(clean-files))
+	$(Q)rm -rf $(call objectify, $(clean-dirs))
 
 # Declare the contents of the .PHONY variable as phony.  We keep that
 # information in a variable se we can use it in if_changed and friends.
diff --git a/doc/DocBook/stylesheet.xsl b/doc/DocBook/stylesheet.xsl
index 8adce568b6..85b2527519 100644
--- a/doc/DocBook/stylesheet.xsl
+++ b/doc/DocBook/stylesheet.xsl
@@ -7,5 +7,4 @@
 <!-- <param name="paper.type">A4</param> -->
 <param name="generate.section.toc.level">2</param>
 <param name="use.id.as.filename">1</param>
-<param name="html.stylesheet">../docbook.css</param>
 </stylesheet>
diff --git a/doc/README.ARC b/doc/README.ARC
new file mode 100644
index 0000000000..5f414fb2fa
--- /dev/null
+++ b/doc/README.ARC
@@ -0,0 +1,27 @@
+Synopsys' DesignWare(r) ARC(r) Processors are a family of 32-bit CPUs
+that SoC designers can optimize for a wide range of uses, from deeply embedded
+to high-performance host applications.
+
+More information on ARC cores avaialble here:
+http://www.synopsys.com/IP/ProcessorIP/ARCProcessors/Pages/default.aspx
+
+Designers can differentiate their products by using patented configuration
+technology to tailor each ARC processor instance to meet specific performance,
+power and area requirements.
+
+The DesignWare ARC processors are also extendable, allowing designers to add
+their own custom instructions that dramatically increase performance.
+
+Synopsys' ARC processors have been used by over 170 customers worldwide who
+collectively ship more than 1 billion ARC-based chips annually.
+
+All DesignWare ARC processors utilize a 16-/32-bit ISA that provides excellent
+performance and code density for embedded and host SoC applications.
+
+The RISC microprocessors are synthesizable and can be implemented in any foundry
+or process, and are supported by a complete suite of development tools.
+
+The ARC GNU toolchain with support for all ARC Processors can be downloaded
+from here (available pre-built toolchains as well):
+
+https://github.com/foss-for-synopsys-dwc-arc-processors/toolchain/releases
diff --git a/doc/README.SPL b/doc/README.SPL
index 312a6a612e..57a39a489b 100644
--- a/doc/README.SPL
+++ b/doc/README.SPL
@@ -13,7 +13,7 @@ can be reused. No code duplication or symlinking is necessary anymore.
 How it works
 ------------
 
-There is a new directory TOPDIR/spl which contains only a Makefile.
+There is a new directory $(srctree)/spl which contains only a Makefile.
 The object files are built separately for SPL and placed in this directory.
 The final binaries which are generated are u-boot-spl, u-boot-spl.bin and
 u-boot-spl.map.
@@ -62,6 +62,7 @@ CONFIG_SPL_FAT_SUPPORT (fs/fat/libfat.o)
 CONFIG_SPL_LIBGENERIC_SUPPORT (lib/libgeneric.o)
 CONFIG_SPL_POWER_SUPPORT (drivers/power/libpower.o)
 CONFIG_SPL_NAND_SUPPORT (drivers/mtd/nand/libnand.o)
+CONFIG_SPL_DRIVERS_MISC_SUPPORT (drivers/misc)
 CONFIG_SPL_DMA_SUPPORT (drivers/dma/libdma.o)
 CONFIG_SPL_POST_MEM_SUPPORT (post/drivers/memory.o)
 CONFIG_SPL_NAND_LOAD (drivers/mtd/nand/nand_spl_load.o)
diff --git a/doc/README.TPL b/doc/README.TPL
index 1df03b958e..980debe777 100644
--- a/doc/README.TPL
+++ b/doc/README.TPL
@@ -19,7 +19,7 @@ board can be reused. No code duplication or symlinking is necessary anymore.
 How it works
 ------------
 
-There has been a directory TOPDIR/spl which contains only a Makefile. The
+There has been a directory $(srctree)/spl which contains only a Makefile. The
 Makefile is shared by SPL and TPL.
 
 The object files are built separately for SPL/TPL and placed in the
diff --git a/doc/README.arm-unaligned-accesses b/doc/README.arm-unaligned-accesses
deleted file mode 100644
index c37d135852..0000000000
--- a/doc/README.arm-unaligned-accesses
+++ /dev/null
@@ -1,122 +0,0 @@
-If you are reading this because of a data abort: the following MIGHT
-be relevant to your abort, if it was caused by an alignment violation.
-In order to determine this, use the PC from the abort dump along with
-an objdump -s -S of the u-boot ELF binary to locate the function where
-the abort happened; then compare this function with the examples below.
-If they match, then you've been hit with a compiler generated unaligned
-access, and you should rewrite your code or add -mno-unaligned-access
-to the command line of the offending file.
-
-Note that the PC shown in the abort message is relocated. In order to
-be able to match it to an address in the ELF binary dump, you will need
-to know the relocation offset. If your target defines CONFIG_CMD_BDI
-and if you can get to the prompt and enter commands before the abort
-happens, then command "bdinfo" will give you the offset. Otherwise you
-will need to try a build with DEBUG set, which will display the offset,
-or use a debugger and set a breakpoint at relocate_code() to see the
-offset (passed as an argument).
-
-*
-
-Since U-Boot runs on a variety of hardware, some only able to perform
-unaligned accesses with a strong penalty, some unable to perform them
-at all, the policy regarding unaligned accesses is to not perform any,
-unless absolutely necessary because of hardware or standards.
-
-Also, on hardware which permits it, the core is configured to throw
-data abort exceptions on unaligned accesses in order to catch these
-unallowed accesses as early as possible.
-
-Until version 4.7, the gcc default for performing unaligned accesses
-(-mno-unaligned-access) is to emulate unaligned accesses using aligned
-loads and stores plus shifts and masks. Emulated unaligned accesses
-will not be caught by hardware. These accesses may be costly and may
-be actually unnecessary. In order to catch these accesses and remove
-or optimize them, option -munaligned-access is explicitly set for all
-versions of gcc which support it.
-
-From gcc 4.7 onward starting at armv7 architectures, the default for
-performing unaligned accesses is to use unaligned native loads and
-stores (-munaligned-access), because the cost of unaligned accesses
-has dropped on armv7 and beyond. This should not affect U-Boot's
-policy of controlling unaligned accesses, however the compiler may
-generate uncontrolled unaligned accesses on its own in at least one
-known case: when declaring a local initialized char array, e.g.
-
-function foo()
-{
-	char buffer[] = "initial value";
-/* or */
-	char buffer[] = { 'i', 'n', 'i', 't', 0 };
-	...
-}
-
-Under -munaligned-accesses with optimizations on, this declaration
-causes the compiler to generate native loads from the literal string
-and native stores to the buffer, and the literal string alignment
-cannot be controlled. If it is misaligned, then the core will throw
-a data abort exception.
-
-Quite probably the same might happen for 16-bit array initializations
-where the constant is aligned on a boundary which is a multiple of 2
-but not of 4:
-
-function foo()
-{
-	u16 buffer[] = { 1, 2, 3 };
-	...
-}
-
-The long term solution to this issue is to add an option to gcc to
-allow controlling the general alignment of data, including constant
-initialization values.
-
-However this will only apply to the version of gcc which will have such
-an option. For other versions, there are four workarounds:
-
-a) Enforce as a rule that array initializations as described above
-   are forbidden. This is generally not acceptable as they are valid,
-   and usual, C constructs. The only case where they could be rejected
-   is when they actually equate to a const char* declaration, i.e. the
-   array is initialized and never modified in the function's scope.
-
-b) Drop the requirement on unaligned accesses at least for ARMv7,
-   i.e. do not throw a data abort exception upon unaligned accesses.
-   But that will allow adding badly aligned code to U-Boot, only for
-   it to fail when re-used with a stricter target, possibly once the
-   bad code is already in mainline.
-
-c) Relax the -munaligned-access rule globally. This will prevent native
-   unaligned accesses of course, but that will also hide any bug caused
-   by a bad unaligned access, making it much harder to diagnose it. It
-   is actually what already happens when building ARM targets with a
-   pre-4.7 gcc, and it may actually already hide some bugs yet unseen
-   until the target gets compiled with -munaligned-access.
-
-d) Relax the -munaligned-access rule only for for files susceptible to
-   the local initialized array issue and for armv7 architectures and
-   beyond. This minimizes the quantity of code which can hide unwanted
-   misaligned accesses.
-
-The option retained is d).
-
-Considering that actual occurrences of the issue are rare (as of this
-writing, 5 files out of 7840 in U-Boot, or .3%, contain an initialized
-local char array which cannot actually be replaced with a const char*),
-contributors should not be required to systematically try and detect
-the issue in their patches.
-
-Detecting files susceptible to the issue can be automated through a
-filter installed as a hook in .git which recognizes local char array
-initializations. Automation should err on the false positive side, for
-instance flagging non-local arrays as if they were local if they cannot
-be told apart.
-
-In any case, detection shall not prevent committing the patch, but
-shall pre-populate the commit message with a note to the effect that
-this patch contains an initialized local char or 16-bit array and thus
-should be protected from the gcc 4.7 issue.
-
-Upon a positive detection, either $(PLATFORM_NO_UNALIGNED) should be
-added to CFLAGS for the affected file(s), or if the array is a pseudo
-const char*, it should be replaced by an actual one.
diff --git a/doc/README.arm64 b/doc/README.arm64
new file mode 100644
index 0000000000..75586dbaa7
--- /dev/null
+++ b/doc/README.arm64
@@ -0,0 +1,46 @@
+U-boot for arm64
+
+Summary
+=======
+No hardware platform of arm64 is available now. The u-boot is
+simulated on Foundation Model and Fast Model for ARMv8.
+
+Notes
+=====
+
+1. Currenly, u-boot run at the highest exception level processor
+   supported and jump to EL2 or optionally EL1 before enter OS.
+
+2. U-boot for arm64 is compiled with AArch64-gcc. AArch64-gcc
+   use rela relocation format, a tool(tools/relocate-rela) by Scott Wood
+   is used to encode the initial addend of rela to u-boot.bin. After running,
+   the u-boot will be relocated to destination again.
+
+3. Fdt should be placed at a 2-megabyte boundary and within the first 512
+   megabytes from the start of the kernel image. So, fdt_high should be
+   defined specially.
+   Please reference linux/Documentation/arm64/booting.txt for detail.
+
+4. Spin-table is used to wake up secondary processors. One location
+   (or per processor location) is defined to hold the kernel entry point
+   for secondary processors. It must be ensured that the location is
+   accessible and zero immediately after secondary processor
+   enter slave_cpu branch execution in start.S. The location address
+   is encoded in cpu node of DTS. Linux kernel store the entry point
+   of secondary processors to it and send event to wakeup secondary
+   processors.
+   Please reference linux/Documentation/arm64/booting.txt for detail.
+
+5. Generic board is supported.
+
+6. CONFIG_ARM64 instead of CONFIG_ARMV8 is used to distinguish aarch64 and
+   aarch32 specific codes.
+
+Contributor
+===========
+   Tom Rini       <trini@ti.com>
+   Scott Wood     <scottwood@freescale.com>
+   York Sun       <yorksun@freescale.com>
+   Simon Glass    <sjg@chromium.org>
+   Sharma Bhupesh <bhupesh.sharma@freescale.com>
+   Rob Herring    <robherring2@gmail.com>
diff --git a/doc/README.at91-soc b/doc/README.at91-soc
index bed035c88d..ab3f713422 100644
--- a/doc/README.at91-soc
+++ b/doc/README.at91-soc
@@ -39,3 +39,10 @@ The method for updating
 3. add new structures for SoC access
 4. Convert arch, driver and boards file to new SoC
 5. remove legacy code, if all boards and drives are ready
+
+2013-10-30 Andreas Bießmann <andreas.devel@googlemail.com>:
+
+The goal is almost reached, we could remove the CONFIG_AT91_LEGACY switch but
+remain the CONFIG_ATMEL_LEGACY switch until the GPIO disaster is fixed. The
+AT91 spi driver has also some CONFIG_ATMEL_LEGACY stuff left, so another point
+to fix until this README can be removed.
diff --git a/doc/README.autoboot b/doc/README.autoboot
index ff58a79e49..14e3660dd8 100644
--- a/doc/README.autoboot
+++ b/doc/README.autoboot
@@ -74,6 +74,7 @@ What they do
 	"bootretry" is >= 0.
 
   CONFIG_AUTOBOOT_KEYED
+  CONFIG_AUTOBOOT_KEYED_CTRLC
   CONFIG_AUTOBOOT_PROMPT
   CONFIG_AUTOBOOT_DELAY_STR
   CONFIG_AUTOBOOT_STOP_STR
@@ -135,6 +136,13 @@ What they do
 	environment variable you can specify a second, alternate
 	string (which allows you to have two "password" strings).
 
+	The CONFIG_AUTOBOOT_KEYED_CTRLC #define allows for the boot
+	sequence to be interrupted by ctrl-c, in addition to the
+	"bootdelaykey" and "bootstopkey". Setting this variable
+	provides an escape sequence from the limited "password"
+	strings.
+
+
   CONFIG_ZERO_BOOTDELAY_CHECK
 
 	If this option is defined, you can stop the autoboot process
diff --git a/doc/README.b4860qds b/doc/README.b4860qds
index 48ece4b835..3da77d9f0f 100644
--- a/doc/README.b4860qds
+++ b/doc/README.b4860qds
@@ -227,17 +227,17 @@ Start Address	End Address	Description	Size
 NOR Flash memory Map on B4860 and B4420QDS
 ------------------------------------------
  Start		 End		Definition			Size
-0xEFF80000	0xEFFFFFFF	u-boot (current bank)		512KB
-0xEFF60000	0xEFF7FFFF	u-boot env (current bank)	128KB
-0xEFF40000	0xEFF5FFFF	FMAN Ucode (current bank)	128KB
-0xEF300000	0xEFF3FFFF	rootfs (alternate bank)		12MB + 256KB
+0xEFF40000	0xEFFFFFFF	u-boot (current bank)		768KB
+0xEFF20000	0xEFF3FFFF	u-boot env (current bank)	128KB
+0xEFF00000	0xEFF1FFFF	FMAN Ucode (current bank)	128KB
+0xEF300000	0xEFEFFFFF	rootfs (alternate bank)		12MB
 0xEE800000	0xEE8FFFFF	device tree (alternate bank)	1MB
 0xEE020000	0xEE6FFFFF	Linux.uImage (alternate bank)	6MB+896KB
 0xEE000000	0xEE01FFFF	RCW (alternate bank)		128KB
-0xEDF80000	0xEDFFFFFF	u-boot (alternate bank)		512KB
-0xEDF60000	0xEDF7FFFF	u-boot env (alternate bank)	128KB
-0xEDF40000	0xEDF5FFFF	FMAN ucode (alternate bank)	128KB
-0xED300000	0xEDF3FFFF	rootfs (current bank)		12MB+256MB
+0xEDF40000	0xEDFFFFFF	u-boot (alternate bank)		768KB
+0xEDF20000	0xEDF3FFFF	u-boot env (alternate bank)	128KB
+0xEDF00000	0xEDF1FFFF	FMAN ucode (alternate bank)	128KB
+0xED300000	0xEDEFFFFF	rootfs (current bank)		12MB
 0xEC800000	0xEC8FFFFF	device tree (current bank)	1MB
 0xEC020000	0xEC6FFFFF	Linux.uImage (current bank)	6MB+896KB
 0xEC000000	0xEC01FFFF	RCW (current bank)		128KB
diff --git a/doc/README.commands b/doc/README.commands
index 9eb367104f..afd5577b0a 100644
--- a/doc/README.commands
+++ b/doc/README.commands
@@ -28,7 +28,7 @@ these symbols when linking full U-Boot even though they are not
 referenced in the source code as such.
 
 If a new board is defined do not forget to define the command section
-by writing in u-boot.lds ($(TOPDIR)/board/boardname/u-boot.lds) these
+by writing in u-boot.lds ($(srctree)/board/boardname/u-boot.lds) these
 3 lines:
 
 	.u_boot_list : {
diff --git a/doc/README.designware_eth b/doc/README.designware_eth
deleted file mode 100644
index 25ec6bd969..0000000000
--- a/doc/README.designware_eth
+++ /dev/null
@@ -1,25 +0,0 @@
-This driver supports Designware Ethernet Controller provided by Synopsis.
-
-The driver is enabled by CONFIG_DESIGNWARE_ETH.
-
-The driver has been developed and tested on SPEAr platforms. By default, the
-MDIO interface works at 100/Full. #defining the below options in board
-configuration file changes this behavior.
-
-Call an subroutine from respective board/.../board.c
-designware_initialize(u32 id, ulong base_addr, u32 phy_addr);
-
-The various options suported by the driver are
-1. CONFIG_DW_ALTDESCRIPTOR
-	Define this to use the Alternate/Enhanced Descriptor configurations.
-1. CONFIG_DW_AUTONEG
-	Define this to autonegotiate with the host before proceeding with mac
-	level configuration. This obviates the definitions of CONFIG_DW_SPEED10M
-	and CONFIG_DW_DUPLEXHALF.
-2. CONFIG_DW_SPEED10M
-	Define this to change the default behavior from 100Mbps to 10Mbps.
-3. CONFIG_DW_DUPLEXHALF
-	Define this to change the default behavior from Full Duplex to Half.
-4. CONFIG_DW_SEARCH_PHY
-	Define this to search the phy address. This would overwrite the value
-	passed as 3rd arg from designware_initialize routine.
diff --git a/doc/README.gpt b/doc/README.gpt
index 5c133f3321..f822894709 100644
--- a/doc/README.gpt
+++ b/doc/README.gpt
@@ -132,8 +132,8 @@ of the Primary.
 	   ----------------------
 	   Offset  Size    Description
 
-	   0       16 B    Partition type GUID
-	   16      16 B    Unique partition GUID
+	   0       16 B    Partition type GUID (Big Endian)
+	   16      16 B    Unique partition GUID in (Big Endian)
 	   32      8  B    First LBA (Little Endian)
 	   40      8  B    Last LBA (inclusive)
 	   48      8  B    Attribute flags [+]
@@ -160,6 +160,9 @@ To restore GUID partition table one needs to:
    Fields 'name', 'size' and 'uuid' are mandatory for every partition.
    The field 'start' is optional.
 
+   option: CONFIG_RANDOM_UUID
+   If any partition "UUID" no exists then it is randomly generated.
+
 2. Define 'CONFIG_EFI_PARTITION' and 'CONFIG_CMD_GPT'
 
 2. From u-boot prompt type:
@@ -168,11 +171,20 @@ To restore GUID partition table one needs to:
 Useful info:
 ============
 
-Two programs, namely: 'fdisk' and 'parted' are recommended to work with GPT
-recovery. Parted is able to handle GUID partitions. Unfortunately the 'fdisk'
-hasn't got such ability.
+Two programs, namely: 'gdisk' and 'parted' are recommended to work with GPT
+recovery. Both are able to handle GUID partitions.
 Please, pay attention at -l switch for parted.
 
 "uuid" program is recommended to generate UUID string. Moreover it can decode
 (-d switch) passed in UUID string. It can be used to generate partitions UUID
 passed to u-boot environment variables.
+If optional CONFIG_RANDOM_UUID is defined then for any partition which environment
+uuid is unset, uuid is randomly generated and stored in correspond environment
+variable.
+
+note:
+Each string block of UUID generated by program "uuid" is in big endian and it is
+also stored in big endian in disk GPT.
+Partitions layout can be printed by typing "mmc part". Note that each partition
+GUID has different byte order than UUID generated before, this is because first
+three blocks of GUID string are in Little Endian.
diff --git a/doc/README.imx6 b/doc/README.imx6
index 513a06ee86..437af2fd9a 100644
--- a/doc/README.imx6
+++ b/doc/README.imx6
@@ -8,3 +8,79 @@ SoC.
 
 1.1 MAC Address: It is stored in fuse bank 4, with the 32 lsbs in word 2 and the
     16 msbs in word 3.
+
+Example:
+
+For reading the MAC address fuses on a MX6Q:
+
+- The MAC address is stored in two fuse addresses (the fuse addresses are
+described in the Fusemap Descriptions table from the mx6q Reference Manual):
+
+0x620[31:0] - MAC_ADDR[31:0]
+0x630[15:0] - MAC_ADDR[47:32]
+
+In order to use the fuse API, we need to pass the bank and word values, which
+are calculated as below:
+
+Fuse address for the lower MAC address: 0x620
+Base address for the fuses: 0x400
+
+(0x620 - 0x400)/0x10 = 0x22 = 34 decimal
+
+As the fuses are arranged in banks of 8 words:
+
+34 / 8 = 4 and the remainder is 2, so in this case:
+
+bank = 4
+word = 2
+
+And the U-boot command would be:
+
+=> fuse read 4 2
+Reading bank 4:
+
+Word 0x00000002: 9f027772
+
+Doing the same for the upper MAC address:
+
+Fuse address for the upper MAC address: 0x630
+Base address for the fuses: 0x400
+
+(0x630 - 0x400)/0x10 = 0x23 = 35 decimal
+
+As the fuses are arranged in banks of 8 words:
+
+35 / 8 = 4 and the remainder is 3, so in this case:
+
+bank = 4
+word = 3
+
+And the U-boot command would be:
+
+=> fuse read 4 3
+Reading bank 4:
+
+Word 0x00000003: 00000004
+
+,which matches the ethaddr value:
+=> echo ${ethaddr}
+00:04:9f:02:77:72
+
+Some other useful hints:
+
+- The 'bank' and 'word' numbers can be easily obtained from the mx6 Reference
+Manual. For the mx6quad case, please check the "46.5 OCOTP Memory Map/Register
+Definition" from the "i.MX 6Dual/6Quad Applications Processor Reference Manual,
+Rev. 1, 04/2013" document. For example, for the MAC fuses we have:
+
+Address:
+21B_C620	Value of OTP Bank4 Word2 (MAC Address)(OCOTP_MAC0)
+
+21B_C630	Value of OTP Bank4 Word3 (MAC Address)(OCOTP_MAC1)
+
+- The command '=> fuse read 4 2 2' reads the whole MAC addresses at once:
+
+=> fuse read 4 2 2
+Reading bank 4:
+
+Word 0x00000002: 9f027772 00000004
diff --git a/doc/README.kwbimage b/doc/README.kwbimage
index 8ed708c356..13f6f92f68 100644
--- a/doc/README.kwbimage
+++ b/doc/README.kwbimage
@@ -42,7 +42,7 @@ Board specific configuration file specifications:
 	kwbimage.cfg.  The name can be set as part of the full path
 	to the file using CONFIG_SYS_KWD_CONFIG (probably in
 	include/configs/<yourboard>.h).   The path should look like:
-	$(SRCTREE)/$(CONFIG_BOARDDIR)/<yourkwbimagename>.cfg
+	$(CONFIG_BOARDDIR)/<yourkwbimagename>.cfg
 2. This file can have empty lines and lines starting with "#" as first
 	character to put comments
 3. This file can have configuration command lines as mentioned below,
diff --git a/doc/README.malta b/doc/README.malta
new file mode 100644
index 0000000000..c8db8a0c39
--- /dev/null
+++ b/doc/README.malta
@@ -0,0 +1,16 @@
+MIPS Malta board
+
+How to flash using a MIPS Navigator Probe:
+
+  - Ensure that your Malta has jumper JP1 fitted. Without this jumper you will
+    be unable to flash your Malta using a Navigator Probe.
+
+  - Connect Navigator Console to your probe and Malta as usual.
+
+  - Within Navigator Console run the following commands:
+
+      source /path/to/u-boot/board/imgtec/malta/flash-malta-boot.tcl
+      reset
+      flash-boot /path/to/u-boot/u-boot.bin
+
+  - You should now be able to reboot your Malta to a U-boot shell.
diff --git a/doc/README.mini2440 b/doc/README.mini2440
deleted file mode 100644
index 311ca52862..0000000000
--- a/doc/README.mini2440
+++ /dev/null
@@ -1,28 +0,0 @@
-U-Boot for FriendlyARM Mini2440 (s3c2440)
-
-This file contains information for the port of U-Boot to FriendlyARM
-mini2440
-
-All information about the board can be found on :
-http://www.friendlyarm.net/products/mini2440
-
-To build u-boot : ./MAKEALL mini2440
-
-Overview :
---------
-FriendlyARM Mini 2440 SBC (Single-Board Computer) with 400 MHz Samsung S3C2440
-ARM9 processor. The board measures 100 x 100 mm, ideal for learning about ARM9
-systems. It's a low cost board.
-
-Boot Methods :
-------------
-Mini2440 can boot from NOR or NAND.
-
-Build :
------
-./MAKEALL mini2440
-
-or
-
-make mini2440_config
-make
diff --git a/doc/README.mxs b/doc/README.mxs
index 2919bbfee1..0235a5aeaf 100644
--- a/doc/README.mxs
+++ b/doc/README.mxs
@@ -27,9 +27,25 @@ Contents
 1) Prerequisites
 ----------------
 
-To make a MXS based board bootable, some tools are necessary. The first one is
-the "elftosb" tool distributed by Freescale Semiconductor. The other one is the
-"mxsboot" tool found in U-Boot source tree.
+To make a MXS based board bootable, some tools are necessary. The only
+mandatory tool is the "mxsboot" tool found in U-Boot source tree. The
+tool is built automatically when compiling U-Boot for i.MX23 or i.MX28.
+
+The production of BootStream image is handled via "mkimage", which is
+also part of the U-Boot source tree. The "mkimage" requires OpenSSL
+development libraries to be installed. In case of Debian and derivates,
+this is installed by running:
+
+	$ sudo apt-get install libssl-dev
+
+NOTE: The "elftosb" tool distributed by Freescale Semiconductor is no
+      longer necessary for general use of U-Boot on i.MX23 and i.MX28.
+      The mkimage supports generation of BootStream images encrypted
+      with a zero key, which is the vast majority of use-cases. In
+      case you do need to produce image encrypted with non-zero key
+      or other special features, please use the "elftosb" tool,
+      otherwise continue to section 2). The installation procedure of
+      the "elftosb" is outlined below:
 
 Firstly, obtain the elftosb archive from the following location:
 
@@ -63,11 +79,6 @@ copy the binary by hand:
 Make sure the "elftosb" binary can be found in your $PATH, in this case this
 means "/usr/local/bin/" has to be in your $PATH.
 
-Install the 'libssl-dev' package as well. On a Debian-based distribution, this
-package can be installed as follows:
-
-	$ sudo apt-get install libssl-dev
-
 2) Compiling U-Boot for a MXS based board
 -------------------------------------------
 
@@ -112,6 +123,18 @@ The code produces "u-boot.sb" file. This file needs to be augmented with a
 proper header to allow successful boot from SD or NAND. Adding the header is
 discussed in the following chapters.
 
+NOTE: The process that produces u-boot.sb uses the mkimage to generate the
+      BootStream. The BootStream is encrypted with zero key. In case you need
+      some special features of the BootStream and plan on using the "elftosb"
+      tool instead, the invocation to produce a compatible BootStream with the
+      one produced by mkimage is outlined below. For further details, refer to
+      the documentation bundled with the "elftosb" package.
+
+	$ elftosb -zf imx23 -c arch/arm/cpu/arm926ejs/mxs/u-boot-imx23.bd \
+		-o u-boot.sb
+	$ elftosb -zf imx28 -c arch/arm/cpu/arm926ejs/mxs/u-boot-imx28.bd \
+		-o u-boot.sb
+
 3) Installation of U-Boot for a MXS based board to SD card
 ----------------------------------------------------------
 
diff --git a/doc/README.nand b/doc/README.nand
index 913e9b50b8..b91f1985d1 100644
--- a/doc/README.nand
+++ b/doc/README.nand
@@ -104,6 +104,16 @@ Configuration Options:
    CONFIG_SYS_MAX_NAND_DEVICE
       The maximum number of NAND devices you want to support.
 
+   CONFIG_SYS_NAND_MAX_ECCPOS
+      If specified, overrides the maximum number of ECC bytes
+      supported.  Useful for reducing image size, especially with SPL.
+      This must be at least 48 if nand_base.c is used.
+
+   CONFIG_SYS_NAND_MAX_OOBFREE
+      If specified, overrides the maximum number of free OOB regions
+      supported.  Useful for reducing image size, especially with SPL.
+      This must be at least 2 if nand_base.c is used.
+
    CONFIG_SYS_NAND_MAX_CHIPS
       The maximum number of NAND chips per device to be supported.
 
@@ -169,6 +179,59 @@ Configuration Options:
       Please convert your driver even if you don't need the extra
       flexibility, so that one day we can eliminate the old mechanism.
 
+
+   CONFIG_SYS_NAND_ONFI_DETECTION
+	Enables detection of ONFI compliant devices during probe.
+	And fetching device parameters flashed on device, by parsing
+	ONFI parameter page.
+
+   CONFIG_BCH
+	Enables software based BCH ECC algorithm present in lib/bch.c
+	This is used by SoC platforms which do not have built-in ELM
+	hardware engine required for BCH ECC correction.
+
+
+Platform specific options
+=========================
+   CONFIG_NAND_OMAP_GPMC
+	Enables omap_gpmc.c driver for OMAPx and AMxxxx platforms.
+	GPMC controller is used for parallel NAND flash devices, and can
+	do ECC calculation (not ECC error detection) for HAM1, BCH4, BCH8
+	and BCH16 ECC algorithms.
+
+   CONFIG_NAND_OMAP_ELM
+	Enables omap_elm.c driver for OMAPx and AMxxxx platforms.
+	ELM controller is used for ECC error detection (not ECC calculation)
+	of BCH4, BCH8 and BCH16 ECC algorithms.
+	Some legacy platforms like OMAP3xx do not have in-built ELM h/w engine,
+	thus such SoC platforms need to depend on software library for ECC error
+	detection. However ECC calculation on such plaforms would still be
+	done by GPMC controller.
+
+   CONFIG_NAND_OMAP_ECCSCHEME
+	On OMAP platforms, this CONFIG specifies NAND ECC scheme.
+	It can take following values:
+	OMAP_ECC_HAM1_CODE_SW
+		1-bit Hamming code using software lib.
+		(for legacy devices only)
+	OMAP_ECC_HAM1_CODE_HW
+		1-bit Hamming code using GPMC hardware.
+		(for legacy devices only)
+	OMAP_ECC_BCH4_CODE_HW_DETECTION_SW
+		4-bit BCH code (unsupported)
+	OMAP_ECC_BCH4_CODE_HW
+		4-bit BCH code (unsupported)
+	OMAP_ECC_BCH8_CODE_HW_DETECTION_SW
+		8-bit BCH code with
+		- ecc calculation using GPMC hardware engine,
+		- error detection using software library.
+		- requires CONFIG_BCH to enable software BCH library
+		(For legacy device which do not have ELM h/w engine)
+	OMAP_ECC_BCH8_CODE_HW
+		8-bit BCH code with
+		- ecc calculation using GPMC hardware engine,
+		- error detection using ELM hardware engine.
+
 NOTE:
 =====
 
diff --git a/doc/README.omap3 b/doc/README.omap3
index 1fbe79db37..a62c357405 100644
--- a/doc/README.omap3
+++ b/doc/README.omap3
@@ -161,8 +161,7 @@ BCH8
 
 To enable hardware assisted BCH8 (8-bit BCH [Bose, Chaudhuri, Hocquenghem]) on
 OMAP3 devices we can use the BCH library in lib/bch.c. To do so add CONFIG_BCH
-to enable the library and CONFIG_NAND_OMAP_BCH8 to to enable hardware assisted
-syndrom generation to your board config.
+and set CONFIG_NAND_OMAP_ECCSCHEME=5 (refer README.nand) for selecting BCH8_SW.
 The NAND OOB layout is the same as in linux kernel, if the linux kernel BCH8
 implementation for OMAP3 works for you so the u-boot version should also.
 When you require the SPL to read with BCH8 there are two more configs to
diff --git a/doc/README.p1010rdb b/doc/README.p1010rdb
deleted file mode 100644
index 6b2b5ff3fb..0000000000
--- a/doc/README.p1010rdb
+++ /dev/null
@@ -1,198 +0,0 @@
-Overview
-=========
-The P1010RDB is a Freescale reference design board that hosts the P1010 SoC.
-
-The P1010 is a cost-effective, low-power, highly integrated host processor
-based on a Power Architecture e500v2 core (maximum core frequency 800/1000 MHz),
-that addresses the requirements of several routing, gateways, storage, consumer,
-and industrial applications. Applications of interest include the main CPUs and
-I/O processors in network attached storage (NAS), the voice over IP (VoIP)
-router/gateway, and wireless LAN (WLAN) and industrial controllers.
-
-The P1010RDB board features are as follows:
-Memory subsystem:
-	- 1Gbyte unbuffered DDR3 SDRAM discrete devices (32-bit bus)
-	- 32 Mbyte NOR flash single-chip memory
-	- 32 Mbyte NAND flash memory
-	- 256 Kbit M24256 I2C EEPROM
-	- 16 Mbyte SPI memory
-	- I2C Board EEPROM 128x8 bit memory
-	- SD/MMC connector to interface with the SD memory card
-Interfaces:
-	- PCIe:
-		- Lane0: x1 mini-PCIe slot
-		- Lane1: x1 PCIe standard slot
-	- SATA:
-		- 1 internal SATA connector to 2.5" 160G SATA2 HDD
-		- 1 eSATA connector to rear panel
-	- 10/100/1000 BaseT Ethernet ports:
-		- eTSEC1, RGMII: one 10/100/1000 port using Vitesse VSC8641XKO
-		- eTSEC2, SGMII: one 10/100/1000 port using Vitesse VSC8221
-		- eTSEC3, SGMII: one 10/100/1000 port using Vitesse VSC8221
-	- USB 2.0 port:
-		- x1 USB2.0 port: via an ULPI PHY to micro-AB connector
-		- x1 USB2.0 poort via an internal PHY to micro-AB connector
-	- FlexCAN ports:
-		- x2 DB-9 female connectors for FlexCAN bus(revision 2.0B)
-		   interface;
-	- DUART interface:
-		- DUART interface: supports two UARTs up to 115200 bps for
-		  console display
-		- J45 connectors are used for these 2 UART ports.
-	- TDM
-		- 2 FXS ports connected via an external SLIC to the TDM
-		   interface. SLIC is controllled via SPI.
-		- 1 FXO port connected via a relay to FXS for switchover to
-		   POTS
-Board connectors:
-	- Mini-ITX power supply connector
-	- JTAG/COP for debugging
-IEEE Std. 1588 signals for test and measurement
-Real-time clock on I2C bus
-POR
-	- support critical POR setting changed via switch on board
-PCB
-	- 6-layer routing (4-layer signals, 2-layer power and ground)
-
-
-Serial Port Configuration on P1010RDB
-=====================================
-Configure the serial port of the attached computer with the following values:
-	-Data rate: 115200 bps
-	-Number of data bits: 8
-	-Parity: None
-	-Number of Stop bits: 1
-	-Flow Control: Hardware/None
-
-
-Settings of DIP-switch
-======================
-  SW4[1:4]= 1111 and SW6[4]=0 for boot from 16bit NOR flash
-  SW4[1:4]= 1000 and SW6[4]=1 for boot from 8bit NAND flash
-  SW4[1:4]= 0110 and SW6[4]=0 for boot from SPI flash
-Note: 1 stands for 'on', 0 stands for 'off'
-
-
-Setting of hwconfig
-===================
-If FlexCAN or TDM is needed, please set "fsl_p1010mux:tdm_can=can" or
-"fsl_p1010mux:tdm_can=tdm" explicitly in u-booot prompt as below for example:
-setenv hwconfig "fsl_p1010mux:tdm_can=tdm;usb1:dr_mode=host,phy_type=utmi"
-By default, don't set fsl_p1010mux:tdm_can, in this case, spi chip selection
-is set to spi-flash instead of to SLIC/TDM/DAC and tdm_can_sel is set to TDM
-instead of to CAN/UART1.
-
-
-Build and burn u-boot to NOR flash
-==================================
-1. Build u-boot.bin image
-	export ARCH=powerpc
-	export CROSS_COMPILE=/your_path/powerpc-linux-gnu-
-	make P1010RDB_NOR
-
-2. Burn u-boot.bin into NOR flash
-	=> tftp $loadaddr $uboot
-	=> protect off eff80000 +$filesize
-	=> erase eff80000 +$filesize
-	=> cp.b $loadaddr eff80000 $filesize
-
-3. Check SW4[1:4]= 1111 and SW6[4]=0, then power on.
-
-
-Alternate NOR bank
-============================
-1. Burn u-boot.bin into alternate NOR bank
-	=> tftp $loadaddr $uboot
-	=> protect off eef80000 +$filesize
-	=> erase eef80000 +$filesize
-	=> cp.b $loadaddr eef80000 $filesize
-
-2. Switch to alternate NOR bank
-	=> mw.b ffb00009 1
-	=> reset
-	or set SW1[8]= ON
-
-SW1[8]= OFF: Upper bank used for booting start
-SW1[8]= ON:  Lower bank used for booting start
-CPLD NOR bank selection register address 0xFFB00009 Bit[0]:
-0 - boot from upper 4 sectors
-1 - boot from lower 4 sectors
-
-
-Build and burn u-boot to NAND flash
-===================================
-1. Build u-boot.bin image
-	export ARCH=powerpc
-	export CROSS_COMPILE=/your_path/powerpc-linux-gnu-
-	make P1010RDB_NAND
-
-2. Burn u-boot-nand.bin into NAND flash
-	=> tftp $loadaddr $uboot-nand
-	=> nand erase 0 $filesize
-	=> nand write $loadaddr 0 $filesize
-
-3. Check SW4[1:4]= 1000 and SW6[4]=1, then power on.
-
-
-
-Build and burn u-boot to SPI flash
-==================================
-1. Build u-boot-spi.bin image
-	make P1010RDB_SPIFLASH_config; make
-	Boot up kernel with rootfs.ext2.gz.uboot.p1010rdb
-	Download u-boot.bin to linux and you can find some config files
-	under /usr/share such as config_xx.dat. Do below command:
-	boot_format config_ddr3_1gb_p1010rdb_800M.dat u-boot.bin -spi \
-			u-boot-spi.bin
-	to generate u-boot-spi.bin.
-
-2. Burn u-boot-spi.bin into SPI flash
-	=> tftp $loadaddr $uboot-spi
-	=> sf erase 0 100000
-	=> sf write $loadaddr 0 $filesize
-
-3. Check SW4[1:4]= 0110 and SW6[4]=0, then power on.
-
-
-
-CPLD POR setting registers
-==========================
-1. Set POR switch selection register (addr 0xFFB00011) to 0.
-2. Write CPLD POR registers (BCSR0~BCSR3, addr 0xFFB00014~0xFFB00017) with
-   proper values.
-   If change boot ROM location to NOR or NAND flash, need write the IFC_CS0
-   switch command by I2C.
-3. Send reset command.
-   After reset, the new POR setting will be implemented.
-
-Two examples are given in below:
-Switch from NOR to NAND boot with default frequency:
-	=> i2c dev 0
-	=> i2c mw 18 1 f9
-	=> i2c mw 18 3 f0
-	=> mw.b ffb00011 0
-	=> mw.b ffb00017 1
-	=> reset
-Switch from NAND to NOR boot with Core/CCB/DDR (800/400/667 MHz):
-	=> i2c dev 0
-	=> i2c mw 18 1 f1
-	=> i2c mw 18 3 f0
-	=> mw.b ffb00011 0
-	=> mw.b ffb00014 2
-	=> mw.b ffb00015 5
-	=> mw.b ffb00016 3
-	=> mw.b ffb00017 f
-	=> reset
-
-
-Boot Linux from network using TFTP on P1010RDB
-==============================================
-Place uImage, p1010rdb.dtb and rootfs files in the TFTP disk area.
-	=> tftp 1000000 uImage
-	=> tftp 2000000 p1010rdb.dtb
-	=> tftp 3000000 rootfs.ext2.gz.uboot.p1010rdb
-	=> bootm 1000000 3000000 2000000
-
-
-Please contact your local field applications engineer or sales representative
-to obtain related documents, such as P1010-RDB User Guide for details.
diff --git a/doc/README.pblimage b/doc/README.pblimage
index 2b9bb5c5f5..7fdd26b71b 100644
--- a/doc/README.pblimage
+++ b/doc/README.pblimage
@@ -14,20 +14,17 @@ Building PBL Boot Image and boot steps
 1. Building PBL Boot Image.
    The default Image is u-boot.pbl.
 
-   For eSPI boot(available on P3041/P4080/P5020):
+   For eSPI boot(available on P2041/P3041/P4080/P5020/P5040/T4240):
 	To build the eSPI boot image:
-	make <board_name>_SPIFLASH_config
-	make u-boot.pbl
+	make <board_name>_SPIFLASH
 
-   For SD boot(available on P3041/P4080/P5020):
+   For SD boot(available on P2041/P3041/P4080/P5020/P5040/T4240):
 	To build the SD boot image:
-	make <board_name>_SDCARD_config
-	make u-boot.pbl
+	make <board_name>_SDCARD
 
-   For Nand boot(available on P3041/P5020):
+   For Nand boot(available on P2041/P3041/P5020/P5040):
 	To build the NAND boot image:
-	make <board_name>_NAND_config
-	make u-boot.pbl
+	make <board_name>_NAND
 
 
 2. pblimage support available with mkimage utility will generate Freescale PBL
diff --git a/doc/README.rmobile b/doc/README.rmobile
index 7ec63f13ce..4fbbcb3ef7 100644
--- a/doc/README.rmobile
+++ b/doc/README.rmobile
@@ -2,13 +2,15 @@ Summary
 =======
 
 This README is about U-Boot support for Renesas's ARM Cortex-A9 based RMOBILE[1]
-family of SoCs. Renesas's RMOBILE SoC family contains an ARM Cortex-A9.
+and R-Car[2]family of SoCs. Renesas's RMOBILE/R-Car SoC family contains an ARM
+Cortex-A9.
 
 Currently the following boards are supported:
 
-* KMC KZM-A9-GT [2]
-
-* Atmark-Techno Armadillo-800-EVA [3]
+* KMC KZM-A9-GT [3]
+* Atmark-Techno Armadillo-800-EVA [4]
+* Renesas Electronics Lager
+* Renesas Electronics Koelsch
 
 Toolchain
 =========
@@ -17,7 +19,7 @@ ARM Cortex-A9 support ARM v7 instruction set (-march=armv7a).
 But currently we compile with -march=armv5 to allow more compilers to work.
 (For U-Boot code this has no performance impact.)
 Because there was no compiler which is supporting armv7a not much before.
-Currently, ELDK[4], Linaro[5], CodeSourcey[6] and Emdebian[7] supports -march=armv7a
+Currently, ELDK[5], Linaro[6], CodeSourcey[7] and Emdebian[8] supports -march=armv7a
 and you can get.
 
 Build
@@ -25,13 +27,26 @@ Build
 
 * KZM-A9-GT
 
-make kzm9g_config
-make
+  make kzm9g_config
+  make
 
 * Armadillo-800-EVA
 
-make armadillo-800eva_config
-make
+  make armadillo-800eva_config
+  make
+
+  Note: Armadillo-800-EVA's U-Boot supports booting from SDcard only.
+        Please see "B.2 Appendix B Boot Specifications" in hardware manual.
+
+* Lager
+
+  make lager_config
+  make
+
+* Koelsch
+
+  make koelsch_config
+  make
 
 Links
 =====
@@ -40,26 +55,30 @@ Links
 
 http://am.renesas.com/products/soc/assp/mobile/r_mobile/index.jsp
 
-[2] KZM-A9-GT
+[2] Renesas R-Car:
+
+http://am.renesas.com/products/soc/assp/automotive/index.jsp
+
+[3] KZM-A9-GT
 
 http://www.kmckk.co.jp/kzma9-gt/index.html
 
-[3] Armadillo-800-EVA
+[4] Armadillo-800-EVA
 
 http://armadillo.atmark-techno.com/armadillo-800-EVA
 
-[4] ELDK
+[5] ELDK
 
 http://www.denx.de/wiki/view/ELDK-5/WebHome#Section_1.6.
 
-[5] Linaro
+[6] Linaro
 
 http://www.linaro.org/downloads/
 
-[6] CodeSourcey
+[7] CodeSourcey
 
 http://www.mentor.com/embedded-software/codesourcery
 
-[7] Emdebian
+[8] Emdebian
 
 http://www.emdebian.org/crosstools.html
diff --git a/doc/README.scrapyard b/doc/README.scrapyard
index 0f9a486185..7d670339dd 100644
--- a/doc/README.scrapyard
+++ b/doc/README.scrapyard
@@ -11,15 +11,29 @@ easily if here is something they might want to dig for...
 
 Board            Arch        CPU            Commit      Removed     Last known maintainer/contact
 =================================================================================================
-omap1510inn      arm         arm925t        -           -           Kshitij Gupta <kshitij@ti.com>
+idmr             m68k        mcf52x2        -           2014-01-28
+M5271EVB         m68k        mcf52x2        -           2014-01-28
+dvl_host         arm         ixp            e317de6b    2014-01-28  Michael Schwingen <michael@schwingen.org>
+actux4           arm         ixp            6ff7aafa    2014-01-28  Michael Schwingen <michael@schwingen.org>
+actux3           arm         ixp            38da33f3    2014-01-28  Michael Schwingen <michael@schwingen.org>
+actux2           arm         ixp            13e0ee7f    2014-01-28  Michael Schwingen <michael@schwingen.org>
+actux1           arm         ixp            373ee048    2014-01-28  Michael Schwingen <michael@schwingen.org>
+mx1ads           arm         arm920t        e570aca9    2014-01-13
+mini2440         arm         arm920t        af5b9b1f    2014-01-13  Gabriel Huau <contact@huau-gabriel.fr>
+omap730p2        arm         arm926ejs      79c5c08d    2013-11-11
+pn62             powerpc     mpc824x        649acfe1    2013-11-11  Wolfgang Grandegger <wg@grandegger.com>
+pdnb3            arm         ixp            304db0b     2013-09-24  Stefan Roese <sr@denx.de>
+scpu             arm         ixp            304db0b     2013-09-24  Stefan Roese <sr@denx.de>
+omap1510inn      arm         arm925t        0610a16     2013-09-23  Kshitij Gupta <kshitij@ti.com>
 CANBT            powerpc     405CR          fb8f4fd     2013-08-07  Matthias Fuchs <matthias.fuchs@esd.eu>
 Alaska8220       powerpc     mpc8220        d6ed322     2013-05-11
 Yukon8220        powerpc     mpc8220        d6ed322     2013-05-11
 sorcery          powerpc     mpc8220        d6ed322     2013-05-11
-smdk6400         arm         arm1176        52587f1	2013-04-12  Zhong Hongbo <bocui107@gmail.com>
-ns9750dev        arm         arm926ejs      4cfc611	2013-02-28  Markus Pietrek <mpietrek@fsforth.de>
+smdk6400         arm         arm1176        52587f1     2013-04-12  Zhong Hongbo <bocui107@gmail.com>
+ns9750dev        arm         arm926ejs      4cfc611     2013-02-28  Markus Pietrek <mpietrek@fsforth.de>
 AMX860           powerpc     mpc860         1b0757e     2012-10-28  Wolfgang Denk <wd@denx.de>
 c2mon            powerpc     mpc855         1b0757e     2012-10-28  Wolfgang Denk <wd@denx.de>
+EP88x            powerpc     mpc885         1b0757e     2012-10-28
 ETX094           powerpc     mpc850         1b0757e     2012-10-28  Wolfgang Denk <wd@denx.de>
 IAD210           powerpc     mpc860         1b0757e     2012-10-28  -
 LANTEC           powerpc     mpc850         1b0757e     2012-10-28  Wolfgang Denk <wd@denx.de>
@@ -97,5 +111,6 @@ adsvix           ARM         PXA27x         7610db1     2008-07-30  Adrian Filip
 R5200            ColdFire    -              48ead7a     2008-03-31  Zachary P. Landau <zachary.landau@labxtechnologies.com>
 CPCI440          powerpc     440GP          b568fd2     2007-12-27  Matthias Fuchs <matthias.fuchs@esd-electronics.com>
 PCIPPC2          powerpc     MPC740/MPC750  7c9e89b     2013-02-07  Wolfgang Denk <wd@denx.de>
-PCIPPC6	powerpc	MPC740/MPC750 -	  -		Wolfgang Denk <wd@denx.de>
+PCIPPC6          powerpc     MPC740/MPC750  -           -           Wolfgang Denk <wd@denx.de>
 omap2420h4       arm         omap24xx       -           2013-06-04  Richard Woodruff <r-woodruff2@ti.com>
+eNET             x86         x86            7e8c53d     2013-02-14  Graeme Russ <graeme.russ@gmail.com>
diff --git a/doc/README.sh7753evb b/doc/README.sh7753evb
new file mode 100644
index 0000000000..5fe178c53f
--- /dev/null
+++ b/doc/README.sh7753evb
@@ -0,0 +1,67 @@
+========================================
+Renesas SH7753 EVB board
+========================================
+
+This board specification:
+=========================
+
+The SH7753 EVB (board config name:sh7753evb) has the following device:
+
+ - SH7753 (SH-4A)
+ - DDR3-SDRAM 512MB
+ - SPI ROM 8MB
+ - Gigabit Ethernet controllers
+ - eMMC 4GB
+
+
+Configuration for This board:
+=============================
+
+You can select the configuration as follows:
+
+ - make sh7753evb_config
+
+
+This board specific command:
+============================
+
+This board has the following its specific command:
+
+ - write_mac
+
+
+1. write_mac
+
+You can write MAC address to SPI ROM.
+
+ Usage 1) Write MAC address
+
+   write_mac [GETHERC ch0] [GETHERC ch1]
+
+	For example)
+	 => write_mac 74:90:50:00:33:9e 74:90:50:00:33:9f
+		*) We have to input the command as a single line
+		   (without carriage return)
+		*) We have to reset after input the command.
+
+ Usage 2) Show current data
+
+   write_mac
+
+	For example)
+		=> write_mac
+		GETHERC ch0 = 74:90:50:00:33:9e
+		GETHERC ch1 = 74:90:50:00:33:9f
+
+
+Update SPI ROM:
+============================
+
+1. Copy u-boot image to RAM area.
+2. Probe SPI device.
+   => sf probe 0
+   SF: Detected MX25L6405D with page size 64KiB, total 8 MiB
+3. Erase SPI ROM.
+   => sf erase 0 80000
+4. Write u-boot image to SPI ROM.
+   => sf write 0x48000000 0 80000
diff --git a/doc/README.socfpga b/doc/README.socfpga
new file mode 100644
index 0000000000..cfcbbfe379
--- /dev/null
+++ b/doc/README.socfpga
@@ -0,0 +1,53 @@
+
+--------------------------------------------
+SOCFPGA Documentation for U-Boot and SPL
+--------------------------------------------
+
+This README is about U-Boot and SPL support for Altera's ARM Cortex-A9MPCore
+based SOCFPGA. To know more about the hardware itself, please refer to
+www.altera.com.
+
+
+--------------------------------------------
+socfpga_dw_mmc
+--------------------------------------------
+Here are macro and detailed configuration required to enable DesignWare SDMMC
+controller support within SOCFPGA
+
+#define CONFIG_MMC
+-> To enable the SD MMC framework support
+
+#define CONFIG_SDMMC_BASE		(SOCFPGA_SDMMC_ADDRESS)
+-> The base address of CSR register for DesignWare SDMMC controller
+
+#define CONFIG_GENERIC_MMC
+-> Enable the generic MMC driver
+
+#define CONFIG_SYS_MMC_MAX_BLK_COUNT	256
+-> Using smaller max blk cnt to avoid flooding the limited stack in OCRAM
+
+#define CONFIG_DWMMC
+-> Enable the common DesignWare SDMMC controller framework
+
+#define CONFIG_SOCFPGA_DWMMC
+-> Enable the SOCFPGA specific driver for DesignWare SDMMC controller
+
+#define CONFIG_SOCFPGA_DWMMC_FIFO_DEPTH		1024
+-> The FIFO depth for SOCFPGA DesignWare SDMMC controller
+
+#define CONFIG_SOCFPGA_DWMMC_DRVSEL	3
+-> Phase-shifted clock of sdmmc_clk for controller to drive command and data to
+the card to meet hold time requirements. SD clock is running at 50MHz and
+drvsel is set to shift 135 degrees (3 * 45 degrees). With that, the hold time
+is 135 / 360 * 20ns = 7.5ns.
+
+#define CONFIG_SOCFPGA_DWMMC_SMPSEL	0
+-> Phase-shifted clock of sdmmc_clk used to sample the command and data from
+the card
+
+#define CONFIG_SOCFPGA_DWMMC_BUS_WIDTH	4
+-> Bus width of data line which either 1, 4 or 8 and based on board routing.
+
+#define CONFIG_SOCFPGA_DWMMC_BUS_HZ	50000000
+-> The clock rate to controller. Do note the controller have a wrapper which
+divide the clock from PLL by 4.
diff --git a/doc/README.unaligned-memory-access.txt b/doc/README.unaligned-memory-access.txt
new file mode 100644
index 0000000000..00529f5dac
--- /dev/null
+++ b/doc/README.unaligned-memory-access.txt
@@ -0,0 +1,240 @@
+Editors note: This document is _heavily_ cribbed from the Linux Kernel, with
+really only the section about "Alignment vs. Networking" removed.
+
+UNALIGNED MEMORY ACCESSES
+=========================
+
+Linux runs on a wide variety of architectures which have varying behaviour
+when it comes to memory access. This document presents some details about
+unaligned accesses, why you need to write code that doesn't cause them,
+and how to write such code!
+
+
+The definition of an unaligned access
+=====================================
+
+Unaligned memory accesses occur when you try to read N bytes of data starting
+from an address that is not evenly divisible by N (i.e. addr % N != 0).
+For example, reading 4 bytes of data from address 0x10004 is fine, but
+reading 4 bytes of data from address 0x10005 would be an unaligned memory
+access.
+
+The above may seem a little vague, as memory access can happen in different
+ways. The context here is at the machine code level: certain instructions read
+or write a number of bytes to or from memory (e.g. movb, movw, movl in x86
+assembly). As will become clear, it is relatively easy to spot C statements
+which will compile to multiple-byte memory access instructions, namely when
+dealing with types such as u16, u32 and u64.
+
+
+Natural alignment
+=================
+
+The rule mentioned above forms what we refer to as natural alignment:
+When accessing N bytes of memory, the base memory address must be evenly
+divisible by N, i.e. addr % N == 0.
+
+When writing code, assume the target architecture has natural alignment
+requirements.
+
+In reality, only a few architectures require natural alignment on all sizes
+of memory access. However, we must consider ALL supported architectures;
+writing code that satisfies natural alignment requirements is the easiest way
+to achieve full portability.
+
+
+Why unaligned access is bad
+===========================
+
+The effects of performing an unaligned memory access vary from architecture
+to architecture. It would be easy to write a whole document on the differences
+here; a summary of the common scenarios is presented below:
+
+ - Some architectures are able to perform unaligned memory accesses
+   transparently, but there is usually a significant performance cost.
+ - Some architectures raise processor exceptions when unaligned accesses
+   happen. The exception handler is able to correct the unaligned access,
+   at significant cost to performance.
+ - Some architectures raise processor exceptions when unaligned accesses
+   happen, but the exceptions do not contain enough information for the
+   unaligned access to be corrected.
+ - Some architectures are not capable of unaligned memory access, but will
+   silently perform a different memory access to the one that was requested,
+   resulting in a subtle code bug that is hard to detect!
+
+It should be obvious from the above that if your code causes unaligned
+memory accesses to happen, your code will not work correctly on certain
+platforms and will cause performance problems on others.
+
+
+Code that does not cause unaligned access
+=========================================
+
+At first, the concepts above may seem a little hard to relate to actual
+coding practice. After all, you don't have a great deal of control over
+memory addresses of certain variables, etc.
+
+Fortunately things are not too complex, as in most cases, the compiler
+ensures that things will work for you. For example, take the following
+structure:
+
+	struct foo {
+		u16 field1;
+		u32 field2;
+		u8 field3;
+	};
+
+Let us assume that an instance of the above structure resides in memory
+starting at address 0x10000. With a basic level of understanding, it would
+not be unreasonable to expect that accessing field2 would cause an unaligned
+access. You'd be expecting field2 to be located at offset 2 bytes into the
+structure, i.e. address 0x10002, but that address is not evenly divisible
+by 4 (remember, we're reading a 4 byte value here).
+
+Fortunately, the compiler understands the alignment constraints, so in the
+above case it would insert 2 bytes of padding in between field1 and field2.
+Therefore, for standard structure types you can always rely on the compiler
+to pad structures so that accesses to fields are suitably aligned (assuming
+you do not cast the field to a type of different length).
+
+Similarly, you can also rely on the compiler to align variables and function
+parameters to a naturally aligned scheme, based on the size of the type of
+the variable.
+
+At this point, it should be clear that accessing a single byte (u8 or char)
+will never cause an unaligned access, because all memory addresses are evenly
+divisible by one.
+
+On a related topic, with the above considerations in mind you may observe
+that you could reorder the fields in the structure in order to place fields
+where padding would otherwise be inserted, and hence reduce the overall
+resident memory size of structure instances. The optimal layout of the
+above example is:
+
+	struct foo {
+		u32 field2;
+		u16 field1;
+		u8 field3;
+	};
+
+For a natural alignment scheme, the compiler would only have to add a single
+byte of padding at the end of the structure. This padding is added in order
+to satisfy alignment constraints for arrays of these structures.
+
+Another point worth mentioning is the use of __attribute__((packed)) on a
+structure type. This GCC-specific attribute tells the compiler never to
+insert any padding within structures, useful when you want to use a C struct
+to represent some data that comes in a fixed arrangement 'off the wire'.
+
+You might be inclined to believe that usage of this attribute can easily
+lead to unaligned accesses when accessing fields that do not satisfy
+architectural alignment requirements. However, again, the compiler is aware
+of the alignment constraints and will generate extra instructions to perform
+the memory access in a way that does not cause unaligned access. Of course,
+the extra instructions obviously cause a loss in performance compared to the
+non-packed case, so the packed attribute should only be used when avoiding
+structure padding is of importance.
+
+
+Code that causes unaligned access
+=================================
+
+With the above in mind, let's move onto a real life example of a function
+that can cause an unaligned memory access. The following function taken
+from the Linux Kernel's include/linux/etherdevice.h is an optimized routine
+to compare two ethernet MAC addresses for equality.
+
+bool ether_addr_equal(const u8 *addr1, const u8 *addr2)
+{
+#ifdef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
+	u32 fold = ((*(const u32 *)addr1) ^ (*(const u32 *)addr2)) |
+		   ((*(const u16 *)(addr1 + 4)) ^ (*(const u16 *)(addr2 + 4)));
+
+	return fold == 0;
+#else
+	const u16 *a = (const u16 *)addr1;
+	const u16 *b = (const u16 *)addr2;
+	return ((a[0] ^ b[0]) | (a[1] ^ b[1]) | (a[2] ^ b[2])) != 0;
+#endif
+}
+
+In the above function, when the hardware has efficient unaligned access
+capability, there is no issue with this code.  But when the hardware isn't
+able to access memory on arbitrary boundaries, the reference to a[0] causes
+2 bytes (16 bits) to be read from memory starting at address addr1.
+
+Think about what would happen if addr1 was an odd address such as 0x10003.
+(Hint: it'd be an unaligned access.)
+
+Despite the potential unaligned access problems with the above function, it
+is included in the kernel anyway but is understood to only work normally on
+16-bit-aligned addresses. It is up to the caller to ensure this alignment or
+not use this function at all. This alignment-unsafe function is still useful
+as it is a decent optimization for the cases when you can ensure alignment,
+which is true almost all of the time in ethernet networking context.
+
+
+Here is another example of some code that could cause unaligned accesses:
+	void myfunc(u8 *data, u32 value)
+	{
+		[...]
+		*((u32 *) data) = cpu_to_le32(value);
+		[...]
+	}
+
+This code will cause unaligned accesses every time the data parameter points
+to an address that is not evenly divisible by 4.
+
+In summary, the 2 main scenarios where you may run into unaligned access
+problems involve:
+ 1. Casting variables to types of different lengths
+ 2. Pointer arithmetic followed by access to at least 2 bytes of data
+
+
+Avoiding unaligned accesses
+===========================
+
+The easiest way to avoid unaligned access is to use the get_unaligned() and
+put_unaligned() macros provided by the <asm/unaligned.h> header file.
+
+Going back to an earlier example of code that potentially causes unaligned
+access:
+
+	void myfunc(u8 *data, u32 value)
+	{
+		[...]
+		*((u32 *) data) = cpu_to_le32(value);
+		[...]
+	}
+
+To avoid the unaligned memory access, you would rewrite it as follows:
+
+	void myfunc(u8 *data, u32 value)
+	{
+		[...]
+		value = cpu_to_le32(value);
+		put_unaligned(value, (u32 *) data);
+		[...]
+	}
+
+The get_unaligned() macro works similarly. Assuming 'data' is a pointer to
+memory and you wish to avoid unaligned access, its usage is as follows:
+
+	u32 value = get_unaligned((u32 *) data);
+
+These macros work for memory accesses of any length (not just 32 bits as
+in the examples above). Be aware that when compared to standard access of
+aligned memory, using these macros to access unaligned memory can be costly in
+terms of performance.
+
+If use of such macros is not convenient, another option is to use memcpy(),
+where the source or destination (or both) are of type u8* or unsigned char*.
+Due to the byte-wise nature of this operation, unaligned accesses are avoided.
+
+--
+In the Linux Kernel,
+Authors: Daniel Drake <dsd@gentoo.org>,
+         Johannes Berg <johannes@sipsolutions.net>
+With help from: Alan Cox, Avuton Olrich, Heikki Orsila, Jan Engelhardt,
+Kyle McMartin, Kyle Moffett, Randy Dunlap, Robert Hancock, Uli Kunitz,
+Vadim Lobanov
diff --git a/doc/README.usb b/doc/README.usb
index 65fb2886d9..bc768a3854 100644
--- a/doc/README.usb
+++ b/doc/README.usb
@@ -127,8 +127,14 @@ To enable USB Host Ethernet in U-Boot, your platform must of course
 support USB with CONFIG_CMD_USB enabled and working. You will need to
 add some config settings to your board header file:
 
+#define CONFIG_CMD_USB		/* the 'usb' interactive command */
 #define CONFIG_USB_HOST_ETHER	/* Enable USB Ethernet adapters */
-#define CONFIG_USB_ETHER_ASIX	/* Asix, or whatever driver(s) you want */
+
+and one or more of the following for individual adapter hardware:
+
+#define CONFIG_USB_ETHER_ASIX
+#define CONFIG_USB_ETHER_MCS7830
+#define CONFIG_USB_ETHER_SMSC95XX
 
 As with built-in networking, you will also want to enable some network
 commands, for example:
@@ -148,7 +154,10 @@ settings should start you off:
 
 You can also set the default IP address of your board and the server
 as well as the default file to load when a 'bootp' command is issued.
-All of these can be obtained from the bootp server if not set.
+However note that encoding these individual network settings into a
+common exectuable is discouraged, as it leads to potential conflicts,
+and all the parameters can either get stored in the board's external
+environment, or get obtained from the bootp server if not set.
 
 #define CONFIG_IPADDR		10.0.0.2  (replace with your value)
 #define CONFIG_SERVERIP		10.0.0.1  (replace with your value)
diff --git a/doc/README.vxworks b/doc/README.vxworks
new file mode 100644
index 0000000000..4cb302e7f4
--- /dev/null
+++ b/doc/README.vxworks
@@ -0,0 +1,19 @@
+From VxWorks 6.9+ (not include 6.9), VxWorks starts adopting device tree as its hardware
+decription mechansim (for PowerPC and ARM), thus requiring boot interface changes.
+This section will describe the new interface.
+
+For PowerPC, the calling convention of the new VxWorks entry point conforms to the ePAPR standard,
+which is shown below (see ePAPR for more details):
+
+    void (*kernel_entry)(fdt_addr,
+              0, 0, EPAPR_MAGIC, boot_IMA, 0, 0)
+
+For ARM, the calling convention is show below:
+
+    void (*kernel_entry)(void *fdt_addr)
+
+When booting new VxWorks kernel (uImage format), the parameters passed to bootm is like below:
+
+    bootm <kernel image address> - <device tree address>
+
+The do_bootvx command still works as it was for older VxWorks kernels.
diff --git a/doc/README.zynq b/doc/README.zynq
new file mode 100644
index 0000000000..043c970140
--- /dev/null
+++ b/doc/README.zynq
@@ -0,0 +1,94 @@
+#
+# Xilinx ZYNQ U-Boot
+#
+# (C) Copyright 2013 Xilinx, Inc.
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+1. About this
+
+This document describes the information about Xilinx Zynq U-Boot -
+like supported boards, ML status and TODO list.
+
+2. Zynq boards
+
+Xilinx Zynq-7000 All Programmable SoCs enable extensive system level
+differentiation, integration, and flexibility through hardware, software,
+and I/O programmability.
+
+* zc70x
+  - zc702 (single qspi, gem0, mmc) [1]
+  - zc706 (dual parallel qspi, gem0, mmc) [2]
+* zed (single qspi, gem0, mmc) [3]
+* microzed (single qspi, gem0, mmc) [4]
+* zc770
+  - zc770-xm010 (single qspi, gem0, mmc)
+  - zc770-xm011 (8 or 16 bit nand)
+  - zc770-xm012 (nor)
+  - zc770-xm013 (dual parallel qspi, gem1)
+
+3. Building
+
+ # Configure for zc70x board
+   $ make zynq_zc70x_config
+     Configuring for zynq_zc70x board...
+
+ # Building default dts for zc702 board
+   $ make
+
+ # Building specified dts for zc706 board
+   $ make DEVICE_TREE=zynq-zc706
+
+4. Bootmode
+
+Zynq has a facility to read the bootmode from the slcr bootmode register
+once user is setting through jumpers on the board - see page no:1546 on [5]
+
+All possible bootmode values are defined in Table 6-2:Boot_Mode MIO Pins
+on [5].
+
+board_late_init() will read the bootmode values using slcr bootmode register
+at runtime and assign the modeboot variable to specific bootmode string which
+is intern used in autoboot.
+
+SLCR bootmode register Bit[3:0] values
+#define ZYNQ_BM_NOR		0x02
+#define ZYNQ_BM_SD		0x05
+#define ZYNQ_BM_JTAG		0x0
+
+"modeboot" variable can assign any of "norboot", "sdboot" or "jtagboot"
+bootmode strings at runtime.
+
+5. Mainline status
+
+- Added basic board configurations support.
+- Added zynq u-boot bsp code - arch/arm/cpu/armv7/zynq
+- Added zynq boards named - zc70x, zed, microzed, zc770_xm010, zc770_xm012, zc770_xm013
+- Added zynq drivers:
+  serial - drivers/serial/serial_zynq.c
+  net - drivers/net/zynq_gem.c
+  mmc - drivers/mmc/zynq_sdhci.c
+  mmc - drivers/mmc/zynq_sdhci.c
+  spi-  drivers/spi/zynq_spi.c
+  i2c - drivers/i2c/zynq_i2c.c
+- Done proper cleanups on board configurations
+- Added basic FDT support for zynq boards
+- d-cache support for zynq_gem.c
+
+6. TODO
+
+- Add zynq boards support - zc770_xm011
+- Add zynq qspi controller driver
+- Add zynq nand controller driver
+- Add FDT support on individual drivers
+
+[1] http://www.xilinx.com/products/boards-and-kits/EK-Z7-ZC702-G.htm
+[2] http://www.xilinx.com/products/boards-and-kits/EK-Z7-ZC706-G.htm
+[3] http://zedboard.org/product/zedboard
+[4] http://zedboard.org/product/microzed
+[5] http://www.xilinx.com/support/documentation/user_guides/ug585-Zynq-7000-TRM.pdf
+
+--
+Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
+Sun Dec 15 14:52:41 IST 2013
diff --git a/doc/SPI/README.dual-flash b/doc/SPI/README.dual-flash
new file mode 100644
index 0000000000..6c88d65dd4
--- /dev/null
+++ b/doc/SPI/README.dual-flash
@@ -0,0 +1,92 @@
+SPI/QSPI Dual flash connection modes:
+=====================================
+
+This describes how SPI/QSPI flash memories are connected to a given
+controller in a single chip select line.
+
+Current spi_flash framework supports, single flash memory connected
+to a given controller with single chip select line, but there are some
+hw logics(ex: xilinx zynq qspi) that describes two/dual memories are
+connected with a single chip select line from a controller.
+
+"dual_flash" from include/spi.h describes these types of connection mode
+
+Possible connections:
+--------------------
+SF_SINGLE_FLASH:
+       - single spi flash memory connected with single chip select line.
+
+  +------------+             CS         +---------------+
+  |            |----------------------->|               |
+  | Controller |         I0[3:0]        | Flash memory  |
+  | SPI/QSPI   |<======================>| (SPI/QSPI)    |
+  |            |           CLK          |               |
+  |            |----------------------->|               |
+  +------------+                        +---------------+
+
+SF_DUAL_STACKED_FLASH:
+       - dual spi/qspi flash memories are connected with a single chipselect
+         line and these two memories are operating stacked fasion with shared buses.
+       - xilinx zynq qspi controller has implemented this feature [1]
+
+  +------------+        CS             +---------------+
+  |            |---------------------->|               |
+  |            |              I0[3:0]  | Upper Flash   |
+  |            |            +=========>| memory        |
+  |            |            |     CLK  | (SPI/QSPI)    |
+  |            |            |    +---->|               |
+  | Controller |        CS  |    |     +---------------+
+  | SPI/QSPI   |------------|----|---->|               |
+  |            |    I0[3:0] |    |     | Lower Flash   |
+  |            |<===========+====|====>| memory        |
+  |            |          CLK    |     | (SPI/QSPI)    |
+  |            |-----------------+---->|               |
+  +------------+                       +---------------+
+
+       - two memory flash devices should has same hw part attributes (like size,
+         vendor..etc)
+       - Configurations:
+               on LQSPI_CFG register, Enable TWO_MEM[BIT:30] on LQSPI_CFG
+               Enable U_PAGE[BIT:28] if U_PAGE flag set - upper memory
+               Disable U_PAGE[BIT:28] if U_PAGE flag unset - lower memory
+       - Operation:
+               accessing memories serially like one after another.
+               by default, if U_PAGE is unset lower memory should accessible,
+               once user wants to access upper memory need to set U_PAGE.
+
+SPI_FLASH_CONN_DUALPARALLEL:
+	- dual spi/qspi flash memories are connected with a single chipselect
+	  line and these two memories are operating parallel with separate buses.
+	- xilinx zynq qspi controller has implemented this feature [1]
+
+  +-------------+           CS		+---------------+
+  |		|---------------------->|		|
+  | 		|        I0[3:0]	| Upper Flash	|
+  | 		|<=====================>| memory	|
+  |		|	   CLK		| (SPI/QSPI)	|
+  |		|---------------------->|		|
+  | Controller	|	    CS		+---------------+
+  | SPI/QSPI	|---------------------->|		|
+  | 		|        I0[3:0]	| Lower Flash	|
+  | 		|<=====================>| memory	|
+  |		|	   CLK		| (SPI/QSPI)	|
+  |		|---------------------->|		|
+  +-------------+			+---------------+
+
+	- two memory flash devices should has same hw part attributes (like size,
+	  vendor..etc)
+	- Configurations:
+		Need to enable SEP_BUS[BIT:29],TWO_MEM[BIT:30] on LQSPI_CFG register.
+	- Operation:
+		Even bits, i.e. bit 0, 2, 4 ., of a data word is located in the lower memory
+		and odd bits, i.e. bit 1, 3, 5, ., of a data word is located in the upper memory.
+
+Note: Technically there is only one CS line from the controller, but
+zynq qspi controller has an internal hw logic to enable additional CS
+when controller is configured for dual memories.
+
+[1] http://www.xilinx.com/support/documentation/user_guides/ug585-Zynq-7000-TRM.pdf
+
+--
+Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
+05-01-2014.
diff --git a/doc/SPI/README.ftssp010_spi_test b/doc/SPI/README.ftssp010_spi_test
new file mode 100644
index 0000000000..1d86f3623f
--- /dev/null
+++ b/doc/SPI/README.ftssp010_spi_test
@@ -0,0 +1,41 @@
+SPI Flash test on Faraday A369 EVB:
+==================================
+
+U-Boot 2014.01-rc2-g3444b6f (Dec 20 2013 - 10:58:40)
+
+CPU:   FA626TE 528 MHz
+AHB:   132 MHz
+APB:   66 MHz
+I2C:   ready
+DRAM:  256 MiB
+MMU:   on
+NAND:  512 MiB
+MMC:   ftsdc010: 0
+*** Warning - bad CRC, using default environment
+
+In:    serial
+Out:   serial
+Err:   serial
+Net:   FTGMAC100#0
+Hit any key to stop autoboot:  0
+=> sf probe 0:0
+SF: Detected MX25L1605D with page size 256 Bytes, erase size 64 KiB, total 2 MiB
+=> sf read 0x10800000 0 0x400
+SF: 1024 bytes @ 0x0 Read: OK
+=> md 0x10800000
+10800000: ea000013 e59ff014 e59ff014 e59ff014    ................
+10800010: e59ff014 e59ff014 e59ff014 e59ff014    ................
+10800020: 1ff7b0c0 1ff7b120 1ff7b180 1ff7b1e0    .... ...........
+10800030: 1ff7b240 1ff7b2a0 1ff7b300 deadbeef    @...............
+10800040: 10800000 0002c1f0 0007409c 00032048    .........@..H ..
+10800050: 1fd6af40 e10f0000 e3c0001f e38000d3    @...............
+10800060: e129f000 eb000001 eb000223 e12fff1e    ..).....#...../.
+10800070: e3a00000 ee070f1e ee080f17 ee070f15    ................
+10800080: ee070f9a ee110f10 e3c00c03 e3c00087    ................
+10800090: e3c00a02 e3800002 e3800a01 ee010f10    ................
+108000a0: e1a0c00e eb007a68 e1a0e00c e1a0f00e    ....hz..........
+108000b0: e1a00000 e1a00000 e1a00000 e1a00000    ................
+108000c0: e51fd078 e58de000 e14fe000 e58de004    x.........O.....
+108000d0: e3a0d013 e169f00d e1a0e00f e1b0f00e    ......i.........
+108000e0: e24dd048 e88d1fff e51f20a0 e892000c    H.M...... ......
+108000f0: e28d0048 e28d5034 e1a0100e e885000f    H...4P..........
diff --git a/doc/SPI/README.sandbox-spi b/doc/SPI/README.sandbox-spi
new file mode 100644
index 0000000000..bb73eaf288
--- /dev/null
+++ b/doc/SPI/README.sandbox-spi
@@ -0,0 +1,64 @@
+Sandbox SPI/SPI Flash Implementation
+====================================
+
+U-Boot supports SPI and SPI flash emuation in sandbox. This must be enabled
+using the --spi_sf paramter when starting U-Boot.
+
+For example:
+
+$ make O=sandbox sandbox_config
+$ make O=sandbox
+$ ./sandbox/u-boot --spi_sf 0:0:W25Q128:b/chromeos_peach/out/image.bin
+
+The four parameters to spi_sf are:
+
+   SPI bus number (typically 0)
+   SPI chip select number (typically 0)
+   SPI chip to emulate
+   File containing emulated data
+
+Supported chips are W25Q16 (2MB), W25Q32 (4MB) and W25Q128 (16MB). Once
+U-Boot it started you can use 'sf' commands as normal. For example:
+
+$ ./b/sandbox/u-boot --spi_sf 0:0:W25Q128:b/chromeos_peach/out/image.bin \
+	-c "sf probe; sf test 0 100000; sf read 0 1000 1000; \
+		sf erase 1000 1000; sf write 0 1000 1000"
+
+
+U-Boot 2013.10-00237-gd4e0fdb (Nov 07 2013 - 20:08:15)
+
+DRAM:  128 MiB
+Using default environment
+
+In:    serial
+Out:   serial
+Err:   serial
+SF: Detected W25Q128BV with page size 256 Bytes, erase size 4 KiB, total 16 MiB
+SPI flash test:
+0 erase: 1 ticks, 1024000 KiB/s 8192.000 Mbps
+1 check: 2 ticks, 512000 KiB/s 4096.000 Mbps
+2 write: 6 ticks, 170666 KiB/s 1365.328 Mbps
+3 read: 0 ticks, 1048576000 KiB/s -201326.-592 Mbps
+Test passed
+0 erase: 1 ticks, 1024000 KiB/s 8192.000 Mbps
+1 check: 2 ticks, 512000 KiB/s 4096.000 Mbps
+2 write: 6 ticks, 170666 KiB/s 1365.328 Mbps
+3 read: 0 ticks, 1048576000 KiB/s -201326.-592 Mbps
+SF: 4096 bytes @ 0x1000 Read: OK
+SF: 4096 bytes @ 0x1000 Erased: OK
+SF: 4096 bytes @ 0x1000 Written: OK
+
+
+Since the SPI bus is fully implemented as well as the SPI flash connected to
+it, you can also use low-level SPI commands to access the flash. For example
+this reads the device ID from the emulated chip:
+
+=> sspi 0 32 9f
+FFEF4018
+
+
+Simon Glass
+sjg@chromium.org
+7/11/2013
+Note that the sandbox SPI implementation was written by Mike Frysinger
+<vapier@gentoo.org>.
diff --git a/doc/SPI/README.sh_qspi_test b/doc/SPI/README.sh_qspi_test
new file mode 100644
index 0000000000..8a33fec32f
--- /dev/null
+++ b/doc/SPI/README.sh_qspi_test
@@ -0,0 +1,38 @@
+-------------------------------------------------
+   Simple steps used to test the SH-QSPI at U-Boot
+-------------------------------------------------
+
+#0, Currently, SH-QSPI is used by lager board (Renesas ARM SoC R8A7790)
+    and koelsch board (Renesas ARM SoC R8A7791). These boot from SPI ROM
+    basically. Thus, U-Boot start, SH-QSPI will is operating normally.
+
+#1, build U-Boot and load u-boot.bin
+
+  => tftpboot 40000000 u-boot.bin
+  sh_eth Waiting for PHY auto negotiation to complete.. done
+  sh_eth: 100Base/Half
+  Using sh_eth device
+  TFTP from server 192.168.169.1; our IP address is 192.168.169.79
+  Filename 'u-boot.bin'.
+  Load address: 0x40000000
+  Loading: ############
+    2.5 MiB/s
+  done
+  Bytes transferred = 175364 (2ad04 hex)
+
+#2, Commands to erase/write u-boot to flash device
+
+  Note: This method is description of the lager board. If you want to use the
+  other boards, please change the value according to each environment.
+
+  =>  sf probe 0
+  SF: Detected S25FL512S_256K with page size 512 Bytes, erase size 64 KiB, total 64 MiB
+  => sf erase 80000 40000
+  SF: 262144 bytes @ 0x80000 Erased: OK
+  => sf write 40000000 80000 175364
+  SF: 1528676 bytes @ 0x80000 Written: OK
+  =>
+
+#3, Push reset button.
+
+  If you're written correctly and driver works properly, U-Boot starts.
diff --git a/doc/SPI/README.ti_qspi_am43x_test b/doc/SPI/README.ti_qspi_am43x_test
new file mode 100644
index 0000000000..8fbf10b57a
--- /dev/null
+++ b/doc/SPI/README.ti_qspi_am43x_test
@@ -0,0 +1,76 @@
+Testing details-
+----------------
+
+This doc simply illustrated the testing details of qspi flash
+driver with Macronix M25L51235 flash device.
+
+The test includes
+- probing the flash device
+- erasing the flash device
+- Writing to flash
+- Reading the contents of the flash.
+
+Test Log
+--------
+
+Hit any key to stop autoboot:  0
+U-Boot# sf probe 0
+SF: Detected MX25L51235F with page size 256 Bytes, erase size 64 KiB, total 64 MiB, mapped at 30000000
+U-Boot# sf erase 0 0x80000
+SF: 524288 bytes @ 0x0 Erased: OK
+U-Boot# mw 81000000 0xdededede 0x40000
+U-Boot# sf write 81000000 0 0x40000
+SF: 262144 bytes @ 0x0 Written: OK
+U-Boot# sf read 82000000 0 0x40000
+SF: 262144 bytes @ 0x0 Read: OK
+U-Boot# md 0x82000000
+82000000: dededede dededede dededede dededede    ................
+82000010: dededede dededede dededede dededede    ................
+82000020: dededede dededede dededede dededede    ................
+82000030: dededede dededede dededede dededede    ................
+82000040: dededede dededede dededede dededede    ................
+82000050: dededede dededede dededede dededede    ................
+82000060: dededede dededede dededede dededede    ................
+82000070: dededede dededede dededede dededede    ................
+82000080: dededede dededede dededede dededede    ................
+82000090: dededede dededede dededede dededede    ................
+820000a0: dededede dededede dededede dededede    ................
+820000b0: dededede dededede dededede dededede    ................
+820000c0: dededede dededede dededede dededede    ................
+820000d0: dededede dededede dededede dededede    ................
+820000e0: dededede dededede dededede dededede    ................
+820000f0: dededede dededede dededede dededede    ................
+U-Boot# md 0x82010000
+82010000: dededede dededede dededede dededede    ................
+82010010: dededede dededede dededede dededede    ................
+82010020: dededede dededede dededede dededede    ................
+82010030: dededede dededede dededede dededede    ................
+82010040: dededede dededede dededede dededede    ................
+82010050: dededede dededede dededede dededede    ................
+82010060: dededede dededede dededede dededede    ................
+82010070: dededede dededede dededede dededede    ................
+82010080: dededede dededede dededede dededede    ................
+82010090: dededede dededede dededede dededede    ................
+820100a0: dededede dededede dededede dededede    ................
+820100b0: dededede dededede dededede dededede    ................
+820100c0: dededede dededede dededede dededede    ................
+820100d0: dededede dededede dededede dededede    ................
+820100e0: dededede dededede dededede dededede    ................
+820100f0: dededede dededede dededede dededede    ................
+U-Boot# md 0x82030000
+82030000: dededede dededede dededede dededede    ................
+82030010: dededede dededede dededede dededede    ................
+82030020: dededede dededede dededede dededede    ................
+82030030: dededede dededede dededede dededede    ................
+82030040: dededede dededede dededede dededede    ................
+82030050: dededede dededede dededede dededede    ................
+82030060: dededede dededede dededede dededede    ................
+82030070: dededede dededede dededede dededede    ................
+82030080: dededede dededede dededede dededede    ................
+82030090: dededede dededede dededede dededede    ................
+820300a0: dededede dededede dededede dededede    ................
+820300b0: dededede dededede dededede dededede    ................
+820300c0: dededede dededede dededede dededede    ................
+820300d0: dededede dededede dededede dededede    ................
+820300e0: dededede dededede dededede dededede    ................
+820300f0: dededede dededede dededede dededede    ................
diff --git a/doc/SPI/status.txt b/doc/SPI/status.txt
index 62c3c85417..13889f5455 100644
--- a/doc/SPI/status.txt
+++ b/doc/SPI/status.txt
@@ -11,6 +11,11 @@ SPI FLASH (drivers/mtd/spi):
 - Bank Address Register (Accessing flashes > 16Mbytes in 3-byte addressing)
 - Added memory_mapped support for read operations.
 - Common probe support for all supported flash vendors except, ramtron.
+- Extended read commands support(dual read, dual IO read)
+- Quad Page Program support.
+- Quad Read support(quad fast read, quad IO read)
+- Dual flash connection topology support(accessing two spi flash memories with single cs)
+- Banking support on dual flash connection topology.
 
 SPI DRIVERS (drivers/spi):
 -
@@ -18,14 +23,10 @@ SPI DRIVERS (drivers/spi):
 TODO:
 - Runtime detection of spi_flash params, SFDP(if possible)
 - Add support for multibus build/accessing.
-- Extended read commands support(dual read, dual IO read)
-- Quad Page Program support.
-- Quad Read support(quad fast read, quad IO read)
-- Dual flash connection topology support(accessing two spi flash memories with single cs)
-- Banking support on dual flash connection topology.
 - Need proper cleanups on spi_flash and drivers.
 
 --
 Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
 18-09-2013.
 07-10-2013.
+08-01-2014.
diff --git a/doc/device-tree-bindings/spi/spi-bus.txt b/doc/device-tree-bindings/spi/spi-bus.txt
new file mode 100644
index 0000000000..800dafe5b0
--- /dev/null
+++ b/doc/device-tree-bindings/spi/spi-bus.txt
@@ -0,0 +1,92 @@
+SPI (Serial Peripheral Interface) busses
+
+SPI busses can be described with a node for the SPI master device
+and a set of child nodes for each SPI slave on the bus.  For this
+discussion, it is assumed that the system's SPI controller is in
+SPI master mode.  This binding does not describe SPI controllers
+in slave mode.
+
+The SPI master node requires the following properties:
+- #address-cells  - number of cells required to define a chip select
+    		address on the SPI bus.
+- #size-cells     - should be zero.
+- compatible      - name of SPI bus controller following generic names
+    		recommended practice.
+- cs-gpios	  - (optional) gpios chip select.
+No other properties are required in the SPI bus node.  It is assumed
+that a driver for an SPI bus device will understand that it is an SPI bus.
+However, the binding does not attempt to define the specific method for
+assigning chip select numbers.  Since SPI chip select configuration is
+flexible and non-standardized, it is left out of this binding with the
+assumption that board specific platform code will be used to manage
+chip selects.  Individual drivers can define additional properties to
+support describing the chip select layout.
+
+Optional property:
+- num-cs : total number of chipselects
+
+If cs-gpios is used the number of chip select will automatically increased
+with max(cs-gpios > hw cs)
+
+So if for example the controller has 2 CS lines, and the cs-gpios
+property looks like this:
+
+cs-gpios = <&gpio1 0 0> <0> <&gpio1 1 0> <&gpio1 2 0>;
+
+Then it should be configured so that num_chipselect = 4 with the
+following mapping:
+
+cs0 : &gpio1 0 0
+cs1 : native
+cs2 : &gpio1 1 0
+cs3 : &gpio1 2 0
+
+SPI slave nodes must be children of the SPI master node and can
+contain the following properties.
+- reg             - (required) chip select address of device.
+- compatible      - (required) name of SPI device following generic names
+    		recommended practice
+- spi-max-frequency - (required) Maximum SPI clocking speed of device in Hz
+- spi-cpol        - (optional) Empty property indicating device requires
+    		inverse clock polarity (CPOL) mode
+- spi-cpha        - (optional) Empty property indicating device requires
+    		shifted clock phase (CPHA) mode
+- spi-cs-high     - (optional) Empty property indicating device requires
+    		chip select active high
+- spi-3wire       - (optional) Empty property indicating device requires
+    		    3-wire mode.
+- spi-tx-bus-width - (optional) The bus width(number of data wires) that
+                      used for MOSI. Defaults to 1 if not present.
+- spi-rx-bus-width - (optional) The bus width(number of data wires) that
+                      used for MISO. Defaults to 1 if not present.
+
+Some SPI controllers and devices support Dual and Quad SPI transfer mode.
+It allows data in SPI system transfered in 2 wires(DUAL) or 4 wires(QUAD).
+Now the value that spi-tx-bus-width and spi-rx-bus-width can receive is
+only 1(SINGLE), 2(DUAL) and 4(QUAD).
+Dual/Quad mode is not allowed when 3-wire mode is used.
+
+If a gpio chipselect is used for the SPI slave the gpio number will be passed
+via the cs_gpio
+
+SPI example for an MPC5200 SPI bus:
+	spi@f00 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "fsl,mpc5200b-spi","fsl,mpc5200-spi";
+		reg = <0xf00 0x20>;
+		interrupts = <2 13 0 2 14 0>;
+		interrupt-parent = <&mpc5200_pic>;
+
+		ethernet-switch@0 {
+			compatible = "micrel,ks8995m";
+			spi-max-frequency = <1000000>;
+			reg = <0>;
+		};
+
+		codec@1 {
+			compatible = "ti,tlv320aic26";
+			spi-max-frequency = <100000>;
+			reg = <1>;
+		};
+	};
diff --git a/doc/device-tree-bindings/video/exynos_mipi_dsi.txt b/doc/device-tree-bindings/video/exynos_mipi_dsi.txt
new file mode 100644
index 0000000000..4938ea01ec
--- /dev/null
+++ b/doc/device-tree-bindings/video/exynos_mipi_dsi.txt
@@ -0,0 +1,82 @@
+Exynos MIPI-DSIM Controller
+=========================
+
+Required properties:
+SOC specific:
+	compatible: should be "samsung,exynos-mipi-dsi"
+	reg: Base address of MIPI-DSIM IP.
+
+Board specific:
+	samsung,dsim-config-e-interface: interface to be used (RGB interface
+		for main display or CPU interface for main or sub display).
+	samsung,dsim-config-e-virtual-ch: virtual channel number that main
+		or sub display uses.
+	samsung,dsim-config-e-pixel-format: pixel stream format for main
+		or sub display.
+	samsung,dsim-config-e-burst-mode: selects Burst mode in Video mode.
+		in Non-burst mode, RGB data area is filled with RGB data and
+		NULL packets, according to input bandwidth of RGB interface.
+	samsung,dsim-config-e-no-data-lane: data lane count used by Master.
+	samsung,dsim-config-e-byte-clk: select byte clock source.
+		It must be DSIM_PLL_OUT_DIV8.
+		DSIM_EXT_CLK_DIV8 and DSIM_EXT_CLK_BYPASSS are not supported.
+	samsung,dsim-config-hfp: HFP disable mode.
+		If set, DSI master ignores HFP area in VIDEO mode.
+		In command mode, this variable is ignored.
+	samsung,dsim-config-p: P value for PMS setting.
+	samsung,dsim-config-m: M value for PMS setting.
+	samsung,dsim-config-s: S value for PMS setting.
+	samsung,dsim-config-pll-stable-time: the PLL Timer for stability
+		of the ganerated clock.
+	samsung,dsim-config-esc-clk: escape clock frequency for getting
+		the escape clock prescaler value.
+	samsung,dsim-config-stop-holding-cnt: the interval value between
+		transmitting read packet (or write "set_tear_on" command)
+		and BTA request. After transmitting read packet or write
+		"set_tear_on" command, BTA requests to D-PHY automatically.
+		This counter value specifies the interval between them.
+	samsung,dsim-config-bta-timeout: the timer for BTA. This register
+		specifies time out from BTA request to change the direction
+		with respect to Tx escape clock.
+	samsung,dsim-config-rx-timeout: the timer for LP Rx mode timeout.
+		this register specifies time out on how long RxValid deasserts,
+		after RxLpdt asserts with respect to Tx escape clock.
+		- RxValid specifies Rx data valid indicator.
+		- RxLpdt specifies an indicator that D-PHY is under RxLpdt mode
+		- RxValid and RxLpdt specifies signal from D-PHY.
+	samsung,dsim-device-name: name of the device.
+	samsung,dsim-device-id: unique device id.
+	samsung,dsim-device-bus_id: bus id for identifing connected bus
+		and this bus id should be same as id of mipi_dsim_device.
+
+Optional properties:
+	samsung,dsim-device-reverse-panel: reverse panel.
+
+Example:
+	mipidsi@11c80000 {
+		compatible = "samsung,exynos-mipi-dsi";
+		reg = <0x11c80000 0x5c>;
+
+		samsung,dsim-config-e-interface = <1>;
+		samsung,dsim-config-e-virtual-ch = <0>;
+		samsung,dsim-config-e-pixel-format = <7>;
+		samsung,dsim-config-e-burst-mode = <1>;
+		samsung,dsim-config-e-no-data-lane = <3>;
+		samsung,dsim-config-e-byte-clk = <0>;
+		samsung,dsim-config-hfp = <1>;
+
+		samsung,dsim-config-p = <3>;
+		samsung,dsim-config-m = <120>;
+		samsung,dsim-config-s = <1>;
+
+		samsung,dsim-config-pll-stable-time = <500>;
+		samsung,dsim-config-esc-clk = <20000000>;
+		samsung,dsim-config-stop-holding-cnt = <0x7ff>;
+		samsung,dsim-config-bta-timeout = <0xff>;
+		samsung,dsim-config-rx-timeout = <0xffff>;
+
+		samsung,dsim-device-id = <0xffffffff>;
+		samsung,dsim-device-bus-id = <0>;
+
+		samsung,dsim-device-reverse-panel = <1>;
+	};
diff --git a/doc/device-tree-bindings/video/sandbox-fb.txt b/doc/device-tree-bindings/video/sandbox-fb.txt
new file mode 100644
index 0000000000..eb91b30e3f
--- /dev/null
+++ b/doc/device-tree-bindings/video/sandbox-fb.txt
@@ -0,0 +1,13 @@
+Sandbox LCD
+===========
+
+This uses the displaymode.txt binding except that only xres and yres are
+required properties.
+
+Example:
+
+	lcd {
+		compatible = "sandbox,lcd-sdl";
+		xres = <800>;
+		yres = <600>;
+	};
diff --git a/doc/driver-model/README.txt b/doc/driver-model/README.txt
new file mode 100644
index 0000000000..e0b395a618
--- /dev/null
+++ b/doc/driver-model/README.txt
@@ -0,0 +1,368 @@
+Driver Model
+============
+
+This README contains high-level information about driver model, a unified
+way of declaring and accessing drivers in U-Boot. The original work was done
+by:
+
+   Marek Vasut <marex@denx.de>
+   Pavel Herrmann <morpheus.ibis@gmail.com>
+   Viktor Křivák <viktor.krivak@gmail.com>
+   Tomas Hlavacek <tmshlvck@gmail.com>
+
+This has been both simplified and extended into the current implementation
+by:
+
+   Simon Glass <sjg@chromium.org>
+
+
+Terminology
+-----------
+
+Uclass - a group of devices which operate in the same way. A uclass provides
+	a way of accessing invidual devices within the group, but always
+	using the same interface. For example a GPIO uclass provides
+	operations for get/set value. An I2C uclass may have 10 I2C ports,
+	4 with one driver, and 6 with another.
+
+Driver - some code which talks to a peripheral and presents a higher-level
+	interface to it.
+
+Device - an instance of a driver, tied to a particular port or peripheral.
+
+
+How to try it
+-------------
+
+Build U-Boot sandbox and run it:
+
+   make sandbox_config
+   make
+   ./u-boot
+
+   (type 'reset' to exit U-Boot)
+
+
+There is a uclass called 'demo'. This uclass handles
+saying hello, and reporting its status. There are two drivers in this
+uclass:
+
+   - simple: Just prints a message for hello, doesn't implement status
+   - shape: Prints shapes and reports number of characters printed as status
+
+The demo class is pretty simple, but not trivial. The intention is that it
+can be used for testing, so it will implement all driver model features and
+provide good code coverage of them. It does have multiple drivers, it
+handles parameter data and platdata (data which tells the driver how
+to operate on a particular platform) and it uses private driver data.
+
+To try it, see the example session below:
+
+=>demo hello 1
+Hello '@' from 07981110: red 4
+=>demo status 2
+Status: 0
+=>demo hello 2
+g
+r@
+e@@
+e@@@
+n@@@@
+g@@@@@
+=>demo status 2
+Status: 21
+=>demo hello 4 ^
+  y^^^
+ e^^^^^
+l^^^^^^^
+l^^^^^^^
+ o^^^^^
+  w^^^
+=>demo status 4
+Status: 36
+=>
+
+
+Running the tests
+-----------------
+
+The intent with driver model is that the core portion has 100% test coverage
+in sandbox, and every uclass has its own test. As a move towards this, tests
+are provided in test/dm. To run them, try:
+
+   ./test/dm/test-dm.sh
+
+You should see something like this:
+
+    <...U-Boot banner...>
+    Running 12 driver model tests
+    Test: dm_test_autobind
+    Test: dm_test_autoprobe
+    Test: dm_test_children
+    Test: dm_test_fdt
+    Test: dm_test_gpio
+    sandbox_gpio: sb_gpio_get_value: error: offset 4 not reserved
+    Test: dm_test_leak
+    Warning: Please add '#define DEBUG' to the top of common/dlmalloc.c
+    Warning: Please add '#define DEBUG' to the top of common/dlmalloc.c
+    Test: dm_test_lifecycle
+    Test: dm_test_operations
+    Test: dm_test_ordering
+    Test: dm_test_platdata
+    Test: dm_test_remove
+    Test: dm_test_uclass
+    Failures: 0
+
+(You can add '#define DEBUG' as suggested to check for memory leaks)
+
+
+What is going on?
+-----------------
+
+Let's start at the top. The demo command is in common/cmd_demo.c. It does
+the usual command procesing and then:
+
+	struct device *demo_dev;
+
+	ret = uclass_get_device(UCLASS_DEMO, devnum, &demo_dev);
+
+UCLASS_DEMO means the class of devices which implement 'demo'. Other
+classes might be MMC, or GPIO, hashing or serial. The idea is that the
+devices in the class all share a particular way of working. The class
+presents a unified view of all these devices to U-Boot.
+
+This function looks up a device for the demo uclass. Given a device
+number we can find the device because all devices have registered with
+the UCLASS_DEMO uclass.
+
+The device is automatically activated ready for use by uclass_get_device().
+
+Now that we have the device we can do things like:
+
+	return demo_hello(demo_dev, ch);
+
+This function is in the demo uclass. It takes care of calling the 'hello'
+method of the relevant driver. Bearing in mind that there are two drivers,
+this particular device may use one or other of them.
+
+The code for demo_hello() is in drivers/demo/demo-uclass.c:
+
+int demo_hello(struct device *dev, int ch)
+{
+	const struct demo_ops *ops = device_get_ops(dev);
+
+	if (!ops->hello)
+		return -ENOSYS;
+
+	return ops->hello(dev, ch);
+}
+
+As you can see it just calls the relevant driver method. One of these is
+in drivers/demo/demo-simple.c:
+
+static int simple_hello(struct device *dev, int ch)
+{
+	const struct dm_demo_pdata *pdata = dev_get_platdata(dev);
+
+	printf("Hello from %08x: %s %d\n", map_to_sysmem(dev),
+	       pdata->colour, pdata->sides);
+
+	return 0;
+}
+
+
+So that is a trip from top (command execution) to bottom (driver action)
+but it leaves a lot of topics to address.
+
+
+Declaring Drivers
+-----------------
+
+A driver declaration looks something like this (see
+drivers/demo/demo-shape.c):
+
+static const struct demo_ops shape_ops = {
+	.hello = shape_hello,
+	.status = shape_status,
+};
+
+U_BOOT_DRIVER(demo_shape_drv) = {
+	.name	= "demo_shape_drv",
+	.id	= UCLASS_DEMO,
+	.ops	= &shape_ops,
+	.priv_data_size = sizeof(struct shape_data),
+};
+
+
+This driver has two methods (hello and status) and requires a bit of
+private data (accessible through dev_get_priv(dev) once the driver has
+been probed). It is a member of UCLASS_DEMO so will register itself
+there.
+
+In U_BOOT_DRIVER it is also possible to specify special methods for bind
+and unbind, and these are called at appropriate times. For many drivers
+it is hoped that only 'probe' and 'remove' will be needed.
+
+The U_BOOT_DRIVER macro creates a data structure accessible from C,
+so driver model can find the drivers that are available.
+
+The methods a device can provide are documented in the device.h header.
+Briefly, they are:
+
+    bind - make the driver model aware of a device (bind it to its driver)
+    unbind - make the driver model forget the device
+    ofdata_to_platdata - convert device tree data to platdata - see later
+    probe - make a device ready for use
+    remove - remove a device so it cannot be used until probed again
+
+The sequence to get a device to work is bind, ofdata_to_platdata (if using
+device tree) and probe.
+
+
+Platform Data
+-------------
+
+Where does the platform data come from? See demo-pdata.c which
+sets up a table of driver names and their associated platform data.
+The data can be interpreted by the drivers however they like - it is
+basically a communication scheme between the board-specific code and
+the generic drivers, which are intended to work on any board.
+
+Drivers can acceess their data via dev->info->platdata. Here is
+the declaration for the platform data, which would normally appear
+in the board file.
+
+	static const struct dm_demo_cdata red_square = {
+		.colour = "red",
+		.sides = 4.
+	};
+	static const struct driver_info info[] = {
+		{
+			.name = "demo_shape_drv",
+			.platdata = &red_square,
+		},
+	};
+
+	demo1 = driver_bind(root, &info[0]);
+
+
+Device Tree
+-----------
+
+While platdata is useful, a more flexible way of providing device data is
+by using device tree. With device tree we replace the above code with the
+following device tree fragment:
+
+	red-square {
+		compatible = "demo-shape";
+		colour = "red";
+		sides = <4>;
+	};
+
+
+The easiest way to make this work it to add a few members to the driver:
+
+	.platdata_auto_alloc_size = sizeof(struct dm_test_pdata),
+	.ofdata_to_platdata = testfdt_ofdata_to_platdata,
+	.probe	= testfdt_drv_probe,
+
+The 'auto_alloc' feature allowed space for the platdata to be allocated
+and zeroed before the driver's ofdata_to_platdata method is called. This
+method reads the information out of the device tree and puts it in
+dev->platdata. Then the probe method is called to set up the device.
+
+Note that both methods are optional. If you provide an ofdata_to_platdata
+method then it wlil be called first (after bind). If you provide a probe
+method it will be called next.
+
+If you don't want to have the platdata automatically allocated then you
+can leave out platdata_auto_alloc_size. In this case you can use malloc
+in your ofdata_to_platdata (or probe) method to allocate the required memory,
+and you should free it in the remove method.
+
+
+Declaring Uclasses
+------------------
+
+The demo uclass is declared like this:
+
+U_BOOT_CLASS(demo) = {
+	.id		= UCLASS_DEMO,
+};
+
+It is also possible to specify special methods for probe, etc. The uclass
+numbering comes from include/dm/uclass.h. To add a new uclass, add to the
+end of the enum there, then declare your uclass as above.
+
+
+Data Structures
+---------------
+
+Driver model uses a doubly-linked list as the basic data structure. Some
+nodes have several lists running through them. Creating a more efficient
+data structure might be worthwhile in some rare cases, once we understand
+what the bottlenecks are.
+
+
+Changes since v1
+----------------
+
+For the record, this implementation uses a very similar approach to the
+original patches, but makes at least the following changes:
+
+- Tried to agressively remove boilerplate, so that for most drivers there
+is little or no 'driver model' code to write.
+- Moved some data from code into data structure - e.g. store a pointer to
+the driver operations structure in the driver, rather than passing it
+to the driver bind function.
+- Rename some structures to make them more similar to Linux (struct device
+instead of struct instance, struct platdata, etc.)
+- Change the name 'core' to 'uclass', meaning U-Boot class. It seems that
+this concept relates to a class of drivers (or a subsystem). We shouldn't
+use 'class' since it is a C++ reserved word, so U-Boot class (uclass) seems
+better than 'core'.
+- Remove 'struct driver_instance' and just use a single 'struct device'.
+This removes a level of indirection that doesn't seem necessary.
+- Built in device tree support, to avoid the need for platdata
+- Removed the concept of driver relocation, and just make it possible for
+the new driver (created after relocation) to access the old driver data.
+I feel that relocation is a very special case and will only apply to a few
+drivers, many of which can/will just re-init anyway. So the overhead of
+dealing with this might not be worth it.
+- Implemented a GPIO system, trying to keep it simple
+
+
+Things to punt for later
+------------------------
+
+- SPL support - this will have to be present before many drivers can be
+converted, but it seems like we can add it once we are happy with the
+core implementation.
+- Pre-relocation support - similar story
+
+That is not to say that no thinking has gone into these - in fact there
+is quite a lot there. However, getting these right is non-trivial and
+there is a high cost associated with going down the wrong path.
+
+For SPL, it may be possible to fit in a simplified driver model with only
+bind and probe methods, to reduce size.
+
+For pre-relocation we can simply call the driver model init function. Then
+post relocation we throw that away and re-init driver model again. For drivers
+which require some sort of continuity between pre- and post-relocation
+devices, we can provide access to the pre-relocation device pointers.
+
+Uclasses are statically numbered at compile time. It would be possible to
+change this to dynamic numbering, but then we would require some sort of
+lookup service, perhaps searching by name. This is slightly less efficient
+so has been left out for now. One small advantage of dynamic numbering might
+be fewer merge conflicts in uclass-id.h.
+
+
+Simon Glass
+sjg@chromium.org
+April 2013
+Updated 7-May-13
+Updated 14-Jun-13
+Updated 18-Oct-13
+Updated 5-Nov-13
diff --git a/doc/driver-model/UDM-block.txt b/doc/driver-model/UDM-block.txt
deleted file mode 100644
index ffbbdf3a7a..0000000000
--- a/doc/driver-model/UDM-block.txt
+++ /dev/null
@@ -1,278 +0,0 @@
-The U-Boot Driver Model Project
-===============================
-Block device subsystem analysis
-===============================
-
-Pavel Herrmann <morpheus.ibis@gmail.com>
-2012-03-08
-
-I) Overview
------------
-
-  U-Boot currently implements several distinct APIs for block devices - some
-  drivers use the SATA API, some drivers use the IDE API, sym53c8xx and
-  AHCI use the SCSI API, mg_disk has a separate API, and systemace also has a
-  separate API. There are also MMC and USB APIs used outside of drivers/block,
-  those will be detailed in their specific documents.
-
-  Block devices are described by block_dev_desc structure, that holds, among
-  other things, the read/write/erase callbacks. Block device structures are
-  stored in any way depending on the API, but can be accessed by
-
-    block_dev_desc_t * $api_get_dev(int dev)
-
-  function, as seen in disk/part.c.
-
-  1) SATA interface
-  -----------------
-
-    The SATA interface drivers implement the following functions:
-
-      int   init_sata(int dev)
-      int   scan_sata(int dev)
-      ulong sata_read(int dev, ulong blknr, ulong blkcnt, void *buffer)
-      ulong sata_write(int dev, ulong blknr, ulong blkcnt, const void *buffer)
-
-    Block devices are kept in sata_dev_desc[], which is prefilled with values
-    common to all SATA devices in cmd_sata.c, and then modified in init_sata
-    function in the drivers. Callbacks of the block device use SATA API
-    directly. The sata_get_dev function is defined in cmd_sata.c.
-
-  2) SCSI interface
-  -----------------
-
-    The SCSI interface drivers implement the following functions:
-
-      void scsi_print_error(ccb *pccb)
-      int  scsi_exec(ccb *pccb)
-      void scsi_bus_reset(void)
-      void scsi_low_level_init(int busdevfunc)
-
-    The SCSI API works through the scsi_exec function, the actual operation
-    requested is found in the ccb structure.
-
-    Block devices are kept in scsi_dev_desc[], which lives only in cmd_scsi.c.
-    Callbacks of the block device use functions from cmd_scsi.c, which in turn
-    call scsi_exec of the controller. The scsi_get_dev function is also defined
-    in cmd_scsi.c.
-
-  3) mg_disk interface
-  --------------------
-
-    The mg_disk interface drivers implement the following functions:
-
-      struct mg_drv_data* mg_get_drv_data (void)
-      uint   mg_disk_init (void)
-      uint   mg_disk_read (u32 addr, u8 *buff, u32 len)
-      uint   mg_disk_write(u32 addr, u8 *buff, u32 len)
-      uint   mg_disk_write_sects(void *buff, u32 sect_num, u32 sect_cnt)
-      uint   mg_disk_read_sects(void *buff, u32 sect_num, u32 sect_cnt)
-
-    The mg_get_drv_data function is to be overridden per-board, but there are no
-    board in-tree that do this.
-
-    Only one driver for this API exists, and it only supports one block device.
-    Callbacks for this device are implemented in mg_disk.c and call the mg_disk
-    API. The mg_disk_get_dev function is defined in mg_disk.c and ignores the
-    device number, always returning the same device.
-
-  4) systemace interface
-  ----------------------
-
-    The systemace interface does not define any driver API, and has no command
-    itself. The single defined function is systemace_get_devs() from
-    systemace.c, which returns a single static structure for the only supported
-    block device. Callbacks for this device are also implemented in systemace.c.
-
-  5) IDE interface
-  ----------------
-
-    The IDE interface drivers implement the following functions, but only if
-    CONFIG_IDE_AHB is set:
-
-      uchar ide_read_register(int dev, unsigned int port);
-      void  ide_write_register(int dev, unsigned int port, unsigned char val);
-      void  ide_read_data(int dev, ulong *sect_buf, int words);
-      void  ide_write_data(int dev, const ulong *sect_buf, int words);
-
-    The first two functions are called from ide_inb()/ide_outb(), and will
-    default to direct memory access if CONFIG_IDE_AHB is not set, or
-    ide_inb()/ide_outb() functions will get overridden by the board altogether.
-
-    The second two functions are called from input_data()/output_data()
-    functions, and also default to direct memory access, but cannot be
-    overridden by the board.
-
-    One function shared by IDE drivers (but not defined in ide.h) is
-      int ide_preinit(void)
-    This function gets called from ide_init in cmd_ide.c if CONFIG_IDE_PREINIT
-    is defined, and will do the driver-specific initialization of the device.
-
-    Block devices are kept in ide_dev_desc[], which is filled in cmd_ide.c.
-    Callbacks of the block device are defined in cmd_ide.c, and use the
-    ide_inb()/ide_outb()/input_data()/output_data() functions mentioned above.
-    The ide_get_dev function is defined in cmd_ide.c.
-
-II) Approach
-------------
-
-  A new block controller core and an associated API will be created to mimic the
-  current SATA API, its drivers will have the following ops:
-
-  struct block_ctrl_ops {
-    int scan(instance *i);
-    int reset(instance *i, int port);
-    lbaint_t read(instance *i, int port, lbaint_t start, lbatin_t length,
-		  void *buffer);
-    lbaint_t write(instance *i, int port, lbaint_t start, lbatin_t length,
-		   void*buffer);
-  }
-
-  The current sata_init() function will be changed into the driver probe()
-  function. The read() and write() functions should never be called directly,
-  instead they should be called by block device driver for disks.
-
-  Other block APIs would either be transformed into this API, or be kept as
-  legacy for old drivers, or be dropped altogether.
-
-  Legacy driver APIs will each have its own driver core that will contain the
-  shared logic, which is currently located mostly in cmd_* files. Callbacks for
-  block device drivers will then probably be implemented as a part of the core
-  logic, and will use the driver ops (which will copy current state of
-  respective APIs) to do the work.
-
-  All drivers will be cleaned up, most ifdefs should be converted into
-  platform_data, to enable support for multiple devices with different settings.
-
-  A new block device core will also be created, and will keep track of all
-  block devices on all interfaces.
-
-  Current block_dev_desc structure will be changed to fit the driver model, all
-  identification and configuration will be placed in private data, and
-  a single accessor and modifier will be defined, to accommodate the need for
-  different sets of options for different interfaces, while keeping the
-  structure small. The new block device drivers will have the following ops
-  structure (lbaint_t is either 32bit or 64bit unsigned, depending on
-  CONFIG_LBA48):
-
-  struct blockdev_ops {
-    lbaint_t (*block_read)(struct instance *i, lbaint_t start, lbaint_t blkcnt,
-			   void *buffer);
-    lbaint_t (*block_write)(struct instance *i, lbaint_t start, lbaint_t blkcnt,
-			    void *buffer);
-    lbaint_t (*block_erase)(struct instance *i, lbaint_t start, lbaint_t blkcnt
-			    );
-    int	     (*get_option)(struct instance *i, enum blockdev_option_code op,
-			   struct option *res);
-    int	     (*set_option)(struct instance *i, enum blockdev_option_code op,
-			   struct option *val);
-  }
-
-  struct option {
-    uint32_t flags
-    union data {
-      uint64_t data_u;
-      char*    data_s;
-      void*    data_p;
-    }
-  }
-
-  enum blockdev_option_code {
-    BLKD_OPT_IFTYPE=0,
-    BLKD_OPT_TYPE,
-    BLKD_OPT_BLOCKSIZE,
-    BLKD_OPT_BLOCKCOUNT,
-    BLKD_OPT_REMOVABLE,
-    BLKD_OPT_LBA48,
-    BLKD_OPT_VENDOR,
-    BLKD_OPT_PRODICT,
-    BLKD_OPT_REVISION,
-    BLKD_OPT_SCSILUN,
-    BLKD_OPT_SCSITARGET,
-    BLKD_OPT_OFFSET
-  }
-
-  Flags in option above will contain the type of returned data (which should be
-  checked against what is expected, even though the option requested should
-  specify it), and a flag to indicate whether the returned pointer needs to be
-  free()'d.
-
-  The block device core will contain the logic now located in disk/part.c and
-  related files, and will be used to forward requests to block devices. The API
-  for the block device core will copy the ops of a block device (with a string
-  identifier instead of instance pointer). This means that partitions will also
-  be handled by the block device core, and exported as block devices, making
-  them transparent to the rest of the code.
-
-  Sadly, this will change how file systems can access the devices, and thus will
-  affect a lot of places. However, these changes should be localized and easy to
-  implement.
-
-  AHCI driver will be rewritten to fit the new unified block controller API,
-  making SCSI API easy to merge with sym53c8xx, or remove it once the device
-  driver has died.
-
-  Optionally, IDE core may be changed into one driver with unified block
-  controller API, as most of it is already in one place and device drivers are
-  just sets of hooks. Additionally, mg_disk driver is unused and may be removed
-  in near future.
-
-
-III) Analysis of in-tree drivers
---------------------------------
-
-  1) ahci.c
-  ---------
-    SCSI API, will be rewritten for a different API.
-
-  2) ata_piix.c
-  -------------
-    SATA API, easy to port.
-
-  3) fsl_sata.c
-  -------------
-    SATA API, few CONFIG macros, easy to port.
-
-  4) ftide020.c
-  -------------
-    IDE API, defines CONFIG_IDE_AHB and ide_preinit hook functions.
-
-  5) mg_disk.c
-  ------------
-    Single driver with mg_disk API, not much to change, easy to port.
-
-  6) mvsata_ide.c
-  ---------------
-    IDE API, only defines ide_preinit hook function.
-
-  7) mxc_ata.c
-  ------------
-    IDE API, only defines ide_preinit hook function.
-
-  8) pata_bfin.c
-  --------------
-    SATA API, easy to port.
-
-  9) sata_dwc.c
-  -------------
-    SATA API, easy to port.
-
-  10) sata_sil3114.c
-  ------------------
-    SATA API, easy to port.
-
-  11) sata_sil.c
-  --------------
-    SATA API, easy to port.
-
-  12) sil680.c
-  ------------
-    IDE API, only defines ide_preinit hook function.
-
-  13) sym53c8xx.c
-  ---------------
-    SCSI API, may be merged with code from cmd_scsi.
-
-  14) systemace.c
-  ---------------
-    Single driver with systemace API, not much to change, easy to port.
diff --git a/doc/driver-model/UDM-cores.txt b/doc/driver-model/UDM-cores.txt
deleted file mode 100644
index 60323335b8..0000000000
--- a/doc/driver-model/UDM-cores.txt
+++ /dev/null
@@ -1,126 +0,0 @@
-The U-Boot Driver Model Project
-===============================
-Driver cores API document
-=========================
-
-Pavel Herrmann <morpheus.ibis@gmail.com>
-
-1) Overview
------------
-  Driver cores will be used as a wrapper for devices of the same type, and as
-  an abstraction for device driver APIs. For each driver API (which roughly
-  correspond to device types), there will be one driver core. Each driver core
-  will implement three APIs - a driver API (which will be the same as API of
-  drivers the core wraps around), a core API (which will be implemented by all
-  cores) and a command API (core-specific API which will be exposed to
-  commands).
-
-  A) Command API
-    The command API will provide access to shared functionality for a specific
-    device, which is currently located mostly in commands. Commands will be
-    rewritten to be more lightweight by using this API. As this API will be
-    different for each core, it is out of scope of this document.
-
-  B) Driver API
-    The driver API will act as a wrapper around actual device drivers,
-    providing a single entrypoint for device access. All functions in this API
-    have an instance* argument (probably called "this" or "i"), which will be
-    examined by the core, and a correct function for the specified driver will
-    get called.
-
-    If the core gets called with a group instance pointer (as discussed in
-    design), it will automatically select the instance that is associated
-    with this core, and use it as target of the call. if the group contains
-    multiple instances of a single type, the caller must explicitly use an
-    accessor to select the correct instance.
-
-    This accessor will look like:
-      struct instance *get_instance_from_group(struct instance *group, int i)
-
-    When called with a non-group instance, it will simply return the instance.
-
-  C) Core API
-    The core API will be implemented by all cores, and will provide
-    functionality for getting driver instances from non-driver code. This API
-    will consist of following functions:
-
-      int get_count(struct instance *core);
-      struct instance* get_instance(struct instance *core, int index);
-      int init(struct instance *core);
-      int bind(struct instance *core, struct instance *dev, void *ops,
-	       void *hint);
-      int unbind(struct instance *core, instance *dev);
-      int replace(struct instance *core, struct_instance *new_dev,
-		  struct instance *old_dev);
-      int destroy(struct instance *core);
-      int reloc(struct instance *new_core, struct instance *old_core);
-
-      The 'hint' parameter of bind() serves for additional data a driver can
-      pass to the core, to help it create the correct internal state for this
-      instance. the replace() function will get called during instance
-      relocation, and will replace the old instance with the new one, keeping
-      the internal state untouched.
-
-
-2) Lifetime of a driver core
-----------------------------
-  Driver cores will be initialized at runtime, to limit memory footprint in
-  early-init stage, when we have to fit into ~1KB of memory. All active cores
-  will be stored in a tree structure (referenced as "Core tree") in global data,
-  which provides good tradeoff between size and access time.
-  Every core will have a number constant associated with it, which will be used
-  to find the instance in Core tree, and to refer to the core in all calls
-  working with the Core tree.
-  The Core Tree should be implemented using B-tree (or a similar structure)
-  to guarantee acceptable time overhead in all cases.
-
-  Code for working with the core (i2c in this example) follows:
-
-    core_init(CORE_I2C);
-      This will check whether we already have a i2c core, and if not it creates
-      a new instance and adds it into the Core tree. This will not be exported,
-      all code should depend on get_core_instance to init the core when
-      necessary.
-
-    get_core_instance(CORE_I2C);
-      This is an accessor into the Core tree, which will return the instance
-      of i2c core, creating it if necessary
-
-    core_bind(CORE_I2C, instance, driver_ops);
-      This will get called in bind() function of a driver, and will add the
-      instance into cores internal list of devices. If the core is not found, it
-      will get created.
-
-    driver_activate(instance *inst);
-      This call will recursively activate all devices necessary for using the
-      specified device. the code could be simplified as:
-	{
-	if (is_activated(inst))
-	  return;
-	driver_activate(inst->bus);
-	get_driver(inst)->probe(inst);
-	}
-
-      The case with multiple parents will need to be handled here as well.
-      get_driver is an accessor to available drivers, which will get struct
-      driver based on a name in the instance.
-
-    i2c_write(instance *inst, ...);
-      An actual call to some method of the driver. This code will look like:
-	{
-	driver_activate(inst);
-	struct instance *core = get_core_instance(CORE_I2C);
-	device_ops = get_ops(inst);
-	device_ops->write(...);
-	}
-
-      get_ops will not be an exported function, it will be internal and specific
-      to the core, as it needs to know how are the ops stored, and what type
-      they are.
-
-  Please note that above examples represent the algorithm, not the actual code,
-  as they are missing checks for validity of return values.
-
-  core_init() function will get called the first time the core is requested,
-  either by core_link() or core_get_instance(). This way, the cores will get
-  created only when they are necessary, which will reduce our memory footprint.
diff --git a/doc/driver-model/UDM-design.txt b/doc/driver-model/UDM-design.txt
deleted file mode 100644
index 9f03bbaad3..0000000000
--- a/doc/driver-model/UDM-design.txt
+++ /dev/null
@@ -1,315 +0,0 @@
-The U-Boot Driver Model Project
-===============================
-Design document
-===============
-Marek Vasut <marek.vasut@gmail.com>
-Pavel Herrmann <morpheus.ibis@gmail.com>
-2012-05-17
-
-I) The modular concept
-----------------------
-
-The driver core design is done with modularity in mind. The long-term plan is to
-extend this modularity to allow loading not only drivers, but various other
-objects into U-Boot at runtime -- like commands, support for other boards etc.
-
-II) Driver core initialization stages
--------------------------------------
-
-The drivers have to be initialized in two stages, since the U-Boot bootloader
-runs in two stages itself. The first stage is the one which is executed before
-the bootloader itself is relocated. The second stage then happens after
-relocation.
-
-  1) First stage
-  --------------
-
-  The first stage runs after the bootloader did very basic hardware init. This
-  means the stack pointer was configured, caches disabled and that's about it.
-  The problem with this part is the memory management isn't running at all. To
-  make things even worse, at this point, the RAM is still likely uninitialized
-  and therefore unavailable.
-
-  2) Second stage
-  ---------------
-
-  At this stage, the bootloader has initialized RAM and is running from it's
-  final location. Dynamic memory allocations are working at this point. Most of
-  the driver initialization is executed here.
-
-III) The drivers
-----------------
-
-  1) The structure of a driver
-  ----------------------------
-
-  The driver will contain a structure located in a separate section, which
-  will allow linker to create a list of compiled-in drivers at compile time.
-  Let's call this list "driver_list".
-
-  struct driver __attribute__((section(driver_list))) {
-    /* The name of the driver */
-    char		name[STATIC_CONFIG_DRIVER_NAME_LENGTH];
-
-    /*
-     * This function should connect this driver with cores it depends on and
-     * with other drivers, likely bus drivers
-     */
-    int			(*bind)(struct instance *i);
-
-    /* This function actually initializes the hardware. */
-    int			(*probe)(struct instance *i);
-
-    /*
-     * The function of the driver called when U-Boot finished relocation.
-     * This is particularly important to eg. move pointers to DMA buffers
-     * and such from the location before relocation to their final location.
-     */
-    int			(*reloc)(struct instance *i);
-
-    /*
-     * This is called when the driver is shuting down, to deinitialize the
-     * hardware.
-     */
-    int			(*remove)(struct instance *i);
-
-    /* This is called to remove the driver from the driver tree */
-    int			(*unbind)(struct instance *i);
-
-    /* This is a list of cores this driver depends on */
-    struct driver	*cores[];
-  };
-
-  The cores[] array in here is very important. It allows u-boot to figure out,
-  in compile-time, which possible cores can be activated at runtime. Therefore
-  if there are cores that won't be ever activated, GCC LTO might remove them
-  from the final binary. Actually, this information might be used to drive build
-  of the cores.
-
-  FIXME: Should *cores[] be really struct driver, pointing to drivers that
-	 represent the cores? Shouldn't it be core instance pointer?
-
-  2) Instantiation of a driver
-  ----------------------------
-
-  The driver is instantiated by calling:
-
-    driver_bind(struct instance *bus, const struct driver_info *di)
-
-  The "struct instance *bus" is a pointer to a bus with which this driver should
-  be registered with. The "root" bus pointer is supplied to the board init
-  functions.
-
-  FIXME: We need some functions that will return list of busses of certain type
-	 registered with the system so the user can find proper instance even if
-	 he has no bus pointer (this will come handy if the user isn't
-	 registering the driver from board init function, but somewhere else).
-
-  The "const struct driver_info *di" pointer points to a structure defining the
-  driver to be registered. The structure is defined as follows:
-
-  struct driver_info {
-	char			name[STATIC_CONFIG_DRIVER_NAME_LENGTH];
-	void			*platform_data;
-  }
-
-  The instantiation of a driver by calling driver_bind() creates an instance
-  of the driver by allocating "struct driver_instance". Note that only struct
-  instance is passed to the driver. The wrapping struct driver_instance is there
-  for purposes of the driver core:
-
-  struct driver_instance {
-    uint32_t          flags;
-    struct instance   i;
-  };
-
-  struct instance {
-	/* Pointer to a driver information passed by driver_register() */
-	const struct driver_info	*info;
-	/* Pointer to a bus this driver is bound with */
-	struct instance			*bus;
-	/* Pointer to this driver's own private data */
-	void				*private_data;
-	/* Pointer to the first block of successor nodes (optional) */
-	struct successor_block 		*succ;
-  }
-
-  The instantiation of a driver does not mean the hardware is initialized. The
-  driver_bind() call only creates the instance of the driver, fills in the "bus"
-  pointer and calls the drivers' .bind() function. The .bind() function of the
-  driver should hook the driver with the remaining cores and/or drivers it
-  depends on.
-
-  It's important to note here, that in case the driver instance has multiple
-  parents, such parent can be connected with this instance by calling:
-
-    driver_link(struct instance *parent, struct instance *dev);
-
-  This will connect the other parent driver with the newly instantiated driver.
-  Note that this must be called after driver_bind() and before driver_acticate()
-  (driver_activate() will be explained below). To allow struct instance to have
-  multiple parent pointer, the struct instance *bus will utilize it's last bit
-  to indicate if this is a pointer to struct instance or to an array if
-  instances, struct successor block. The approach is similar as the approach to
-  *succ in struct instance, described in the following paragraph.
-
-  The last pointer of the struct instance, the pointer to successor nodes, is
-  used only in case of a bus driver. Otherwise the pointer contains NULL value.
-  The last bit of this field indicates if this is a bus having a single child
-  node (so the last bit is 0) or if this bus has multiple child nodes (the last
-  bit is 1). In the former case, the driver core should clear the last bit and
-  this pointer points directly to the child node. In the later case of a bus
-  driver, the pointer points to an instance of structure:
-
-  struct successor_block {
-    /* Array of pointers to instances of devices attached to this bus */
-    struct instance                     *dev[BLOCKING_FACTOR];
-    /* Pointer to next block of successors */
-    struct successor_block              *next;
-  }
-
-  Some of the *dev[] array members might be NULL in case there are no more
-  devices attached. The *next is NULL in case the list of attached devices
-  doesn't continue anymore. The BLOCKING_FACTOR is used to allocate multiple
-  slots for successor devices at once to avoid fragmentation of memory.
-
-  3) The bind() function of a driver
-  ----------------------------------
-
-  The bind function of a driver connects the driver with various cores the
-  driver provides functions for. The driver model related part will look like
-  the following example for a bus driver:
-
-  int driver_bind(struct instance *in)
-  {
-	...
-	core_bind(&core_i2c_static_instance, in, i2c_bus_funcs);
-	...
-  }
-
-  FIXME: What if we need to run-time determine, depending on some hardware
-	 register, what kind of i2c_bus_funcs to pass?
-
-  This makes the i2c core aware of a new bus. The i2c_bus_funcs is a constant
-  structure of functions any i2c bus driver must provide to work. This will
-  allow the i2c command operate with the bus. The core_i2c_static_instance is
-  the pointer to the instance of a core this driver provides function to.
-
-  FIXME: Maybe replace "core-i2c" with CORE_I2C global pointer to an instance of
-	 the core?
-
-  4) The instantiation of a core driver
-  -------------------------------------
-
-  The core driver is special in the way that it's single-instance driver. It is
-  always present in the system, though it might not be activated. The fact that
-  it's single instance allows it to be instantiated at compile time.
-
-  Therefore, all possible structures of this driver can be in read-only memory,
-  especially struct driver and struct driver_instance. But the successor list,
-  which needs special treatment.
-
-  To solve the problem with a successor list and the core driver flags, a new
-  entry in struct gd (global data) will be introduced. This entry will point to
-  runtime allocated array of struct driver_instance. It will be possible to
-  allocate the exact amount of struct driver_instance necessary, as the number
-  of cores that might be activated will be known at compile time. The cores will
-  then behave like any usual driver.
-
-  Pointers to the struct instance of cores can be computed at compile time,
-  therefore allowing the resulting u-boot binary to save some overhead.
-
-  5) The probe() function of a driver
-  -----------------------------------
-
-  The probe function of a driver allocates necessary resources and does required
-  initialization of the hardware itself. This is usually called only when the
-  driver is needed, as a part of the defered probe mechanism.
-
-  The driver core should implement a function called
-
-    int driver_activate(struct instance *in);
-
-  which should call the .probe() function of the driver and then configure the
-  state of the driver instance to "ACTIVATED". This state of a driver instance
-  should be stored in a wrap-around structure for the structure instance, the
-  struct driver_instance.
-
-  6) The command side interface to a driver
-  -----------------------------------------
-
-  The U-Boot command shall communicate only with the specific driver core. The
-  driver core in turn exports necessary API towards the command.
-
-  7) Demonstration imaginary board
-  --------------------------------
-
-  Consider the following computer:
-
-  *
-  |
-  +-- System power management logic
-  |
-  +-- CPU clock controlling logc
-  |
-  +-- NAND controller
-  |   |
-  |   +-- NAND flash chip
-  |
-  +-- 128MB of DDR DRAM
-  |
-  +-- I2C bus #0
-  |   |
-  |   +-- RTC
-  |   |
-  |   +-- EEPROM #0
-  |   |
-  |   +-- EEPROM #1
-  |
-  +-- USB host-only IP core
-  |   |
-  |   +-- USB storage device
-  |
-  +-- USB OTG-capable IP core
-  |   |
-  |   +-- connection to the host PC
-  |
-  +-- GPIO
-  |   |
-  |   +-- User LED #0
-  |   |
-  |   +-- User LED #1
-  |
-  +-- UART0
-  |
-  +-- UART1
-  |
-  +-- Ethernet controller #0
-  |
-  +-- Ethernet controller #1
-  |
-  +-- Audio codec
-  |
-  +-- PCI bridge
-  |   |
-  |   +-- Ethernet controller #2
-  |   |
-  |   +-- SPI host card
-  |   |   |
-  |   |   +-- Audio amplifier (must be operational before codec)
-  |   |
-  |   +-- GPIO host card
-  |       |
-  |       +-- User LED #2
-  |
-  +-- LCD controller
-  |
-  +-- PWM controller (must be enabled after LCD controller)
-  |
-  +-- SPI host controller
-  |   |
-  |   +-- SD/MMC connected via SPI
-  |   |
-  |   +-- SPI flash
-  |
-  +-- CPLD/FPGA with stored configuration of the board
diff --git a/doc/driver-model/UDM-fpga.txt b/doc/driver-model/UDM-fpga.txt
deleted file mode 100644
index 4f9df940ed..0000000000
--- a/doc/driver-model/UDM-fpga.txt
+++ /dev/null
@@ -1,115 +0,0 @@
-The U-Boot Driver Model Project
-===============================
-I/O system analysis
-===================
-Marek Vasut <marek.vasut@gmail.com>
-2012-02-21
-
-I) Overview
------------
-
-The current FPGA implementation is handled by command "fpga". This command in
-turn calls the following functions:
-
-fpga_info()
-fpga_load()
-fpga_dump()
-
-These functions are implemented by what appears to be FPGA multiplexer, located
-in drivers/fpga/fpga.c . This code determines which device to operate with
-depending on the device ID.
-
-The fpga_info() function is multiplexer of the functions providing information
-about the particular FPGA device. These functions are implemented in the drivers
-for the particular FPGA device:
-
-xilinx_info()
-altera_info()
-lattice_info()
-
-Similar approach is used for fpga_load(), which multiplexes "xilinx_load()",
-"altera_load()" and "lattice_load()" and is used to load firmware into the FPGA
-device.
-
-The fpga_dump() function, which prints the contents of the FPGA device, is no
-different either, by multiplexing "xilinx_dump()", "altera_dump()" and
-"lattice_dump()" functions.
-
-Finally, each new FPGA device is registered by calling "fpga_add()" function.
-This function takes two arguments, the second one being particularly important,
-because it's basically what will become platform_data. Currently, it's data that
-are passed to the driver from the board/platform code.
-
-II) Approach
-------------
-
-The path to conversion of the FPGA subsystem will be very straightforward, since
-the FPGA subsystem is already quite dynamic. Multiple things will need to be
-modified though.
-
-First is the registration of the new FPGA device towards the FPGA core. This
-will be achieved by calling:
-
-  fpga_device_register(struct instance *i, const struct fpga_ops *ops);
-
-The particularly interesting part is the struct fpga_ops, which contains
-operations supported by the FPGA device. These are basically the already used
-calls in the current implementation:
-
-struct fpga_ops {
-  int info(struct instance *i);
-  int load(struct instance *i, const char *buf, size_t size);
-  int dump(struct instance *i, const char *buf, size_t size);
-}
-
-The other piece that'll have to be modified is how the devices are tracked.
-It'll be necessary to introduce a linked list of devices within the FPGA core
-instead of tracking them by ID number.
-
-Next, the "Xilinx_desc", "Lattice_desc" and "Altera_desc" structures will have
-to be moved to driver's private_data. Finally, structures passed from the board
-and/or platform files, like "Xilinx_Virtex2_Slave_SelectMap_fns" would be passed
-via platform_data to the driver.
-
-III) Analysis of in-tree drivers
---------------------------------
-
-  1) Altera driver
-  ----------------
-  The driver is realized using the following files:
-
-    drivers/fpga/altera.c
-    drivers/fpga/ACEX1K.c
-    drivers/fpga/cyclon2.c
-    drivers/fpga/stratixII.c
-
-  All of the sub-drivers implement basically the same info-load-dump interface
-  and there's no expected problem during the conversion. The driver itself will
-  be realised by altera.c and all the sub-drivers will be linked in. The
-  distinction will be done by passing different platform data.
-
-  2) Lattice driver
-  -----------------
-  The driver is realized using the following files:
-
-    drivers/fpga/lattice.c
-    drivers/fpga/ivm_core.c
-
-  This driver also implements the standard interface, but to realise the
-  operations with the FPGA device, uses functions from "ivm_core.c" file. This
-  file implements the main communications logic and has to be linked in together
-  with "lattice.c". No problem converting is expected here.
-
-  3) Xilinx driver
-  ----------------
-  The driver is realized using the following files:
-
-    drivers/fpga/xilinx.c
-    drivers/fpga/spartan2.c
-    drivers/fpga/spartan3.c
-    drivers/fpga/virtex2.c
-
-  This set of sub-drivers is special by defining a big set of macros in
-  "include/spartan3.h" and similar files. These macros would need to be either
-  rewritten or replaced. Otherwise, there are no problems expected during the
-  conversion process.
diff --git a/doc/driver-model/UDM-gpio.txt b/doc/driver-model/UDM-gpio.txt
deleted file mode 100644
index 87554dde68..0000000000
--- a/doc/driver-model/UDM-gpio.txt
+++ /dev/null
@@ -1,106 +0,0 @@
-The U-Boot Driver Model Project
-===============================
-GPIO analysis
-=============
-Viktor Krivak <viktor.krivak@gmail.com>
-2012-02-24
-
-I) Overview
------------
-
-  At this moment U-Boot provides standard API that consists of 7 functions.
-
-    int  gpio_request(unsigned gpio, const char *label)
-    int  gpio_free(unsigned gpio)
-    int  gpio_direction_input(unsigned gpio)
-    int  gpio_direction_output(unsigned gpio, int value)
-    int  gpio_get_value(unsigned gpio)
-    void gpio_set_value(unsigned gpio, int value)
-
-  Methods "gpio_request()" and "gpio_free()" are used for claiming and releasing
-  GPIOs. First one should check if the desired pin exists and if the pin wasn't
-  requested already elsewhere. The method also has a label argument that can be
-  used for debug purposes. The label argument should be copied into the internal
-  memory, but only if the DEBUG macro is set. The "gpio_free()" is the exact
-  opposite. It releases the particular pin. Other methods are used for setting
-  input or output direction and obtaining or setting values of the pins.
-
-II) Approach
-------------
-
-  1) Request and free GPIO
-  ------------------------
-
-    The "gpio_request()" implementation is basically the same for all boards.
-    The function checks if the particular GPIO is correct and checks if the
-    GPIO pin is still free. If the conditions are met, the method marks the
-    GPIO claimed in it's internal structure. If macro DEBUG is defined, the
-    function also copies the label argument to the structure. If the pin is
-    already locked, the function returns -1 and if DEBUG is defined, certain
-    debug output is generated, including the contents of the label argument.
-    The "gpio_free()" function releases the lock and eventually deallocates
-    data used by the copied label argument.
-
-  2) Internal data
-  ----------------
-
-  Internal data are driver specific. They have to contain some mechanism to
-  realise the locking though. This can be done for example using a bit field.
-
-  3) Operations provided by the driver
-  ------------------------------------
-
-  The driver operations basically meet API that is already defined and used.
-  Except for "gpio_request()" and "gpio_free()", all methods can be converted in
-  a simple manner. The driver provides the following structure:
-
-  struct gpio_driver_ops {
-    int  (*gpio_request)(struct instance *i, unsigned gpio,
-			 const char *label);
-    int  (*gpio_free)(struct instance *i, unsigned gpio);
-    int  (*gpio_direction_input)(struct instance *i, unsigned gpio);
-    int  (*gpio_direction_output)(struct instance *i, unsigned gpio,
-				  int value);
-    int  (*gpio_get_value)(struct instance *i, unsigned gpio);
-    void (*gpio_set_value)(struct instance *i, unsigned gpio, int value);
-  }
-
-III) Analysis of in-tree drivers
---------------------------------
-
-  1) altera_pio.c
-  ---------------
-  Meets standard API. Implements gpio_request() properly. Simple conversion
-  possible.
-
-  2) at91_gpio.c
-  --------------
-  Don't meet standard API. Need some other methods to implement.
-
-  3) da8xx_gpio.c
-  ---------------
-  Meets standard API. Implements gpio_request() properly. Simple conversion
-  possible.
-
-  4) kw_gpio.c
-  ------------
-  Doesn't meet standard API. Needs some other methods to implement and move some
-  methods to another file.
-
-  5) mpc83xx_gpio.c
-  -----------------
-  Meets standard API. Doesn't implement gpio_request() properly (only checks
-  if the pin is valid). Simple conversion possible.
-
-  6) mvgpio.c
-  -----------
-  Meets standard API. Doesn't implement gpio_request() properly (only checks
-  if the pin is valid). Simple conversion possible.
-
-  7) mvgpio.h
-  -----------
-  Wrong placement. Will be moved to another location.
-
-  8) mvmfp.c
-  ----------
-  Wrong placement. Will be moved to another location.
diff --git a/doc/driver-model/UDM-hwmon.txt b/doc/driver-model/UDM-hwmon.txt
deleted file mode 100644
index 9048cc0f00..0000000000
--- a/doc/driver-model/UDM-hwmon.txt
+++ /dev/null
@@ -1,118 +0,0 @@
-The U-Boot Driver Model Project
-===============================
-Hwmon device subsystem analysis
-===============================
-
-Tomas Hlavacek <tmshlvck@gmail.com>
-2012-03-02
-
-I) Overview
------------
-
-U-Boot currently implements one API for HW monitoring devices. The
-interface is defined in include/dtt.h and comprises of functions:
-
-    void dtt_init(void);
-    int dtt_init_one(int);
-    int dtt_read(int sensor, int reg);
-    int dtt_write(int sensor, int reg, int val);
-    int dtt_get_temp(int sensor);
-
-The functions are implemented by a proper device driver in drivers/hwmon
-directory and the driver to be compiled in is selected in a Makefile.
-Drivers are mutually exclusive.
-
-Drivers depends on I2O code and naturally on board specific data. There are
-few ad-hoc constants put in dtt.h file and driver headers and code. This
-has to be consolidated into board specific data or driver headers if those
-constants makes sense globally.
-
-
-II) Approach
-------------
-
-  1) New API
-  ----------
-  In the UDM each hwmon driver would register itself by a function
-
-    int hwmon_device_register(struct instance *i,
-			      struct hwmon_device_ops *o);
-
-  The structure being defined as follows:
-
-    struct hwmon_device_ops {
-	int  (*read)(struct instance *i, int sensor, int reg);
-	int  (*write)(struct instance *i, int sensor, int reg,
-		      int val);
-	int  (*get_temp)(struct instance *i, int sensor);
-    };
-
-
-  2) Conversion thougths
-  ----------------------
-  U-Boot hwmon drivers exports virtually the same functions (with exceptions)
-  and we are considering low number of drivers and code anyway. The interface
-  is already similar and unified by the interface defined in dtt.h.
-  Current initialization functions dtt_init() and dtt_init_one() will be
-  converted into probe() and hwmon_device_register(), so the funcionality will
-  be kept in more proper places. Besides implementing core registration and
-  initialization we need to do code cleanup, especially separate
-  driver-specific and HW specific constants.
-
-  3) Special consideration due to early initialization
-  ----------------------------------------------------
-  The dtt_init() function call is used during early initialization in
-  board/gdsys/405ex/io64.c for starting up fans. The dtt code is perfectly
-  usable in the early stage because it uses only local variables and no heap
-  memory is required at this level. However the underlying code of I2C has to
-  keep the same properties with regard to possibility of running in early
-  initialization stage.
-
-III) Analysis of in-tree drivers
---------------------------------
-
-  1) drivers/hwmon/lm81.c
-  -----------------------
-  The driver is standard dtt. Simple conversion is possible.
-
-
-  2) drivers/hwmon/ds1722.c
-  -------------------------
-  The driver is not standard dtt, but interface is similar to dtt.
-  The interface has to be changed in order to comply to above mentioned
-  specification.
-
-
-  3) drivers/hwmon/ds1775.c
-  -------------------------
-  The driver is standard dtt. Simple conversion is possible.
-
-
-  4) drivers/hwmon/lm73.c
-  -----------------------
-  The driver is standard dtt. Simple conversion is possible.
-
-
-  5) drivers/hwmon/lm63.c
-  -----------------------
-  The driver is standard dtt. Simple conversion is possible.
-
-
-  6) drivers/hwmon/adt7460.c
-  --------------------------
-  The driver is standard dtt. Simple conversion is possible.
-
-
-  7) drivers/hwmon/lm75.c
-  -----------------------
-  The driver is standard dtt. Simple conversion is possible.
-
-
-  8) drivers/hwmon/ds1621.c
-  -------------------------
-  The driver is standard dtt. Simple conversion is possible.
-
-
-  9) drivers/hwmon/adm1021.c
-  --------------------------
-  The driver is standard dtt. Simple conversion is possible.
diff --git a/doc/driver-model/UDM-keyboard.txt b/doc/driver-model/UDM-keyboard.txt
deleted file mode 100644
index ef3761dc24..0000000000
--- a/doc/driver-model/UDM-keyboard.txt
+++ /dev/null
@@ -1,47 +0,0 @@
-The U-Boot Driver Model Project
-===============================
-Keyboard input analysis
-=======================
-Marek Vasut <marek.vasut@gmail.com>
-2012-02-20
-
-I) Overview
------------
-
-The keyboard drivers are most often registered with STDIO subsystem. There are
-components of the keyboard drivers though, which operate in severe ad-hoc
-manner, often being related to interrupt-driven keypress reception. This
-components will require the most sanitization of all parts of keyboard input
-subsystem.
-
-Otherwise, the keyboard is no different from other standard input but with the
-necessity to decode scancodes. These are decoded using tables provided by
-keyboard drivers. These tables are often driver specific.
-
-II) Approach
-------------
-
-The most problematic part is the interrupt driven keypress reception. For this,
-the buffers that are currently shared throughout the whole U-Boot would need to
-be converted into driver's private data.
-
-III) Analysis of in-tree drivers
---------------------------------
-
-  1) board/mpl/common/kbd.c
-  -------------------------
-  This driver is a classic STDIO driver, no problem with conversion is expected.
-  Only necessary change will be to move this driver to a proper location.
-
-  2) board/rbc823/kbd.c
-  ---------------------
-  This driver is a classic STDIO driver, no problem with conversion is expected.
-  Only necessary change will be to move this driver to a proper location.
-
-  3) drivers/input/keyboard.c
-  ---------------------------
-  This driver is special in many ways. Firstly because this is a universal stub
-  driver for converting scancodes from i8042 and the likes. Secondly because the
-  buffer is filled by various other ad-hoc implementations of keyboard input by
-  using this buffer as an extern. This will need to be fixed by allowing drivers
-  to pass certain routines to this driver via platform data.
diff --git a/doc/driver-model/UDM-mmc.txt b/doc/driver-model/UDM-mmc.txt
deleted file mode 100644
index 1f07d874ea..0000000000
--- a/doc/driver-model/UDM-mmc.txt
+++ /dev/null
@@ -1,319 +0,0 @@
-The U-Boot Driver Model Project
-===============================
-MMC system analysis
-===================
-Marek Vasut <marek.vasut@gmail.com>
-2012-02-25
-
-I) Overview
------------
-
-The MMC subsystem is already quite dynamic in it's nature. It's only necessary
-to flip the subsystem to properly defined API.
-
-The probing process of MMC drivers start by calling "mmc_initialize()",
-implemented by MMC framework, from the architecture initialization file. The
-"mmc_initialize()" function in turn calls "board_mmc_init()" function and if
-this doesn't succeed, "cpu_mmc_init()" function is called. It is important to
-note that both of the "*_mmc_init()" functions have weak aliases to functions
-which automatically fail.
-
-Both of the "*_mmc_init()" functions though serve only one purpose. To call
-driver specific probe function, which in turn actually registers the driver with
-MMC subsystem. Each of the driver specific probe functions is currently done in
-very ad-hoc manner.
-
-The registration with the MMC subsystem is done by calling "mmc_register()",
-whose argument is a runtime configured structure of information about the MMC
-driver. Currently, the information structure is intermixed with driver's internal
-data. The description of the structure follows:
-
-struct mmc {
- /*
-  * API: Allows this driver to be a member of the linked list of all MMC drivers
-  *      registered with MMC subsystem
-  */
-  struct list_head link;
-
-  /* DRIVER: Name of the registered driver */
-  char name[32];
-
-  /* DRIVER: Driver's private data */
-  void *priv;
-
-  /* DRIVER: Voltages the host bus can provide */
-  uint voltages;
-
-  /* API: Version of the card */
-  uint version;
-
-  /* API: Test if the driver was already initialized */
-  uint has_init;
-
-  /* DRIVER: Minimum frequency the host bus can provide */
-  uint f_min;
-
-  /* DRIVER: Maximum frequency the host bus can provide */
-  uint f_max;
-
-  /* API: Is the card SDHC */
-  int high_capacity;
-
-  /* API: Actual width of the bus used by the current card */
-  uint bus_width;
-
-  /*
-   * DRIVER: Clock frequency to be configured on the host bus, this is read-only
-   *         for the driver.
-   */
-  uint clock;
-
-  /* API: Capabilities of the card */
-  uint card_caps;
-
-  /* DRIVER: MMC bus capabilities */
-  uint host_caps;
-
-  /* API: Configuration and ID data retrieved from the card */
-  uint ocr;
-  uint scr[2];
-  uint csd[4];
-  uint cid[4];
-  ushort rca;
-
-  /* API: Partition configuration */
-  char part_config;
-
-  /* API: Number of partitions */
-  char part_num;
-
-  /* API: Transmission speed */
-  uint tran_speed;
-
-  /* API: Read block length */
-  uint read_bl_len;
-
-  /* API: Write block length */
-  uint write_bl_len;
-
-  /* API: Erase group size */
-  uint erase_grp_size;
-
-  /* API: Capacity of the card */
-  u64 capacity;
-
-  /* API: Descriptor of this block device */
-  block_dev_desc_t block_dev;
-
-  /* DRIVER: Function used to submit command to the card */
-  int (*send_cmd)(struct mmc *mmc,
-		  struct mmc_cmd *cmd, struct mmc_data *data);
-
-  /* DRIVER: Function used to configure the host */
-  void (*set_ios)(struct mmc *mmc);
-
-  /* DRIVER: Function used to initialize the host */
-  int (*init)(struct mmc *mmc);
-
-  /* DRIVER: Function used to report the status of Card Detect pin */
-  int (*getcd)(struct mmc *mmc);
-
-  /*
-   * DRIVER: Maximum amount of blocks sent during multiblock xfer,
-   *         set to 0 to autodetect.
-   */
-  uint b_max;
-};
-
-The API above is the new API used by most of the drivers. There're still drivers
-in the tree that use old, legacy API though.
-
-2) Approach
------------
-
-To convert the MMC subsystem to a proper driver model, the "struct mmc"
-structure will have to be properly split in the first place. The result will
-consist of multiple parts, first will be the structure defining operations
-provided by the MMC driver:
-
-struct mmc_driver_ops {
-  /* Function used to submit command to the card */
-  int  (*send_cmd)(struct mmc *mmc,
-		  struct mmc_cmd *cmd, struct mmc_data *data);
-  /* DRIVER: Function used to configure the host */
-  void (*set_ios)(struct mmc *mmc);
-  /* Function used to initialize the host */
-  int  (*init)(struct mmc *mmc);
-  /* Function used to report the status of Card Detect pin */
-  int  (*getcd)(struct mmc *mmc);
-}
-
-The second part will define the parameters of the MMC driver:
-
-struct mmc_driver_params {
-  /* Voltages the host bus can provide */
-  uint32_t voltages;
-  /* Minimum frequency the host bus can provide */
-  uint32_t f_min;
-  /* Maximum frequency the host bus can provide */
-  uint32_t f_max;
-  /* MMC bus capabilities */
-  uint32_t host_caps;
-  /*
-   * Maximum amount of blocks sent during multiblock xfer,
-   * set to 0 to autodetect.
-   */
-  uint32_t b_max;
-}
-
-And finally, the internal per-card data of the MMC subsystem core:
-
-struct mmc_card_props {
-  /* Version of the card */
-  uint32_t version;
-  /* Test if the driver was already initializes */
-  bool     has_init;
-  /* Is the card SDHC */
-  bool     high_capacity;
-  /* Actual width of the bus used by the current card */
-  uint8_t  bus_width;
-  /* Capabilities of the card */
-  uint32_t card_caps;
-  /* Configuration and ID data retrieved from the card */
-  uint32_t ocr;
-  uint32_t scr[2];
-  uint32_t csd[4];
-  uint32_t cid[4];
-  uint16_t rca;
-  /* Partition configuration */
-  uint8_t  part_config;
-  /* Number of partitions */
-  uint8_t  part_num;
-  /* Transmission speed */
-  uint32_t tran_speed;
-  /* Read block length */
-  uint32_t read_bl_len;
-  /* Write block length */
-  uint32_t write_bl_len;
-  /* Erase group size */
-  uint32_t erase_grp_size;
-  /* Capacity of the card */
-  uint64_t capacity;
-  /* Descriptor of this block device */
-  block_dev_desc_t block_dev;
-}
-
-The probe() function will then register the MMC driver by calling:
-
-  mmc_device_register(struct instance *i, struct mmc_driver_ops *o,
-					  struct mmc_driver_params *p);
-
-The struct mmc_driver_params will have to be dynamic in some cases, but the
-driver shouldn't modify it's contents elsewhere than in probe() call.
-
-Next, since the MMC drivers will now be consistently registered into the driver
-tree from board file, the functions "board_mmc_init()" and "cpu_mmc_init()" will
-disappear altogether.
-
-As for the legacy drivers, these will either be converted or removed altogether.
-
-III) Analysis of in-tree drivers
---------------------------------
-
-  1) arm_pl180_mmci.c
-  -------------------
-  Follows the new API and also has a good encapsulation of the whole driver. The
-  conversion here will be simple.
-
-  2) atmel_mci.c
-  --------------
-  This driver uses the legacy API and should be removed unless converted. It is
-  probably possbible to replace this driver with gen_atmel_mci.c . No conversion
-  will be done on this driver.
-
-  3) bfin_sdh.c
-  -------------
-  Follows the new API and also has a good encapsulation of the whole driver. The
-  conversion here will be simple.
-
-  4) davinci_mmc.c
-  ----------------
-  Follows the new API and also has a good encapsulation of the whole driver. The
-  conversion here will be simple.
-
-  5) fsl_esdhc.c
-  --------------
-  Follows the new API and also has a good encapsulation of the whole driver. The
-  conversion here will be simple, unless some problem appears due to the FDT
-  component of the driver.
-
-  6) ftsdc010_esdhc.c
-  -------------------
-  Follows the new API and also has a good encapsulation of the whole driver. The
-  conversion here will be simple.
-
-  7) gen_atmel_mci.c
-  ------------------
-  Follows the new API and also has a good encapsulation of the whole driver. The
-  conversion here will be simple.
-
-  8) mmc_spi.c
-  ------------
-  Follows the new API and also has a good encapsulation of the whole driver. The
-  conversion here will be simple.
-
-  9) mv_sdhci.c
-  -------------
-  This is a component of the SDHCI support, allowing it to run on Marvell
-  Kirkwood chip. It is probable the SDHCI support will have to be modified to
-  allow calling functions from this file based on information passed via
-  platform_data.
-
-  10) mxcmmc.c
-  ------------
-  Follows the new API and also has a good encapsulation of the whole driver. The
-  conversion here will be simple.
-
-  11) mxsmmc.c
-  ------------
-  Follows the new API and also has a good encapsulation of the whole driver. The
-  conversion here will be simple.
-
-  12) omap_hsmmc.c
-  ----------------
-  Follows the new API and also has a good encapsulation of the whole driver. The
-  conversion here will be simple.
-
-  13) pxa_mmc.c
-  -------------
-  This driver uses the legacy API and is written in a severely ad-hoc manner.
-  This driver will be removed in favor of pxa_mmc_gen.c, which is proved to work
-  better and is already well tested. No conversion will be done on this driver
-  anymore.
-
-  14) pxa_mmc_gen.c
-  -----------------
-  Follows the new API and also has a good encapsulation of the whole driver. The
-  conversion here will be simple.
-
-  15) s5p_mmc.c
-  -------------
-  Follows the new API and also has a good encapsulation of the whole driver. The
-  conversion here will be simple.
-
-  16) sdhci.c
-  -----------
-  Follows the new API and also has a good encapsulation of the whole driver. The
-  conversion here will be simple, though it'd be necessary to modify this driver
-  to also support the Kirkwood series and probably also Tegra series of CPUs.
-  See the respective parts of this section for details.
-
-  17) sh_mmcif.c
-  --------------
-  Follows the new API and also has a good encapsulation of the whole driver. The
-  conversion here will be simple.
-
-  18) tegra2_mmc.c
-  ----------------
-  Follows the new API and also has a good encapsulation of the whole driver. The
-  conversion here will be simple.
diff --git a/doc/driver-model/UDM-net.txt b/doc/driver-model/UDM-net.txt
deleted file mode 100644
index e2ea8f5a60..0000000000
--- a/doc/driver-model/UDM-net.txt
+++ /dev/null
@@ -1,434 +0,0 @@
-The U-Boot Driver Model Project
-===============================
-Net system analysis
-===================
-Marek Vasut <marek.vasut@gmail.com>
-2012-03-03
-
-I) Overview
------------
-
-The networking subsystem already supports multiple devices. Therefore the
-conversion shall not be very hard.
-
-The network subsystem is operated from net/eth.c, which tracks all registered
-ethernet interfaces and calls their particular functions registered via
-eth_register().
-
-The eth_register() is called from the network driver initialization function,
-which in turn is called most often either from "board_net_init()" or
-"cpu_net_init()". This function has one important argument, which is the
-"struct eth_device", defined at include/net.h:
-
-struct eth_device {
-  /* DRIVER: Name of the device */
-  char name[NAMESIZE];
-  /* DRIVER: MAC address */
-  unsigned char enetaddr[6];
-  /* DRIVER: Register base address */
-  int iobase;
-  /* CORE: state of the device */
-  int state;
-
-  /* DRIVER: Device initialization function */
-  int  (*init) (struct eth_device*, bd_t*);
-  /* DRIVER: Function for sending packets */
-  int  (*send) (struct eth_device*, volatile void* packet, int length);
-  /* DRIVER: Function for receiving packets */
-  int  (*recv) (struct eth_device*);
-  /* DRIVER: Function to cease operation of the device */
-  void (*halt) (struct eth_device*);
-  /* DRIVER: Function to send multicast packet (OPTIONAL) */
-  int (*mcast) (struct eth_device*, u32 ip, u8 set);
-  /* DRIVER: Function to change ethernet MAC address */
-  int  (*write_hwaddr) (struct eth_device*);
-  /* CORE: Next device in the linked list of devices managed by net core */
-  struct eth_device *next;
-  /* CORE: Device index */
-  int index;
-  /* DRIVER: Driver's private data */
-  void *priv;
-};
-
-This structure defines the particular driver, though also contains elements that
-should not be exposed to the driver, like core state.
-
-Small, but important part of the networking subsystem is the PHY management
-layer, whose drivers are contained in drivers/net/phy. These drivers register in
-a very similar manner to network drivers, by calling "phy_register()" with the
-argument of "struct phy_driver":
-
-struct phy_driver {
-  /* DRIVER: Name of the PHY driver */
-  char *name;
-  /* DRIVER: UID of the PHY driver */
-  unsigned int uid;
-  /* DRIVER: Mask for UID of the PHY driver */
-  unsigned int mask;
-  /* DRIVER: MMDS of the PHY driver */
-  unsigned int mmds;
-  /* DRIVER: Features the PHY driver supports */
-  u32 features;
-  /* DRIVER: Initialize the PHY hardware */
-  int (*probe)(struct phy_device *phydev);
-  /* DRIVER: Reconfigure the PHY hardware */
-  int (*config)(struct phy_device *phydev);
-  /* DRIVER: Turn on the PHY hardware, allow it to send/receive */
-  int (*startup)(struct phy_device *phydev);
-  /* DRIVER: Turn off the PHY hardware */
-  int (*shutdown)(struct phy_device *phydev);
-  /* CORE: Allows this driver to be part of list of drivers */
-  struct list_head list;
-};
-
-II) Approach
-------------
-
-To convert the elements of network subsystem to proper driver model method, the
-"struct eth_device" will have to be split into multiple components. The first
-will be a structure defining the driver operations:
-
-struct eth_driver_ops {
-  int  (*init)(struct instance*, bd_t*);
-  int  (*send)(struct instance*, void *packet, int length);
-  int  (*recv)(struct instance*);
-  void (*halt)(struct instance*);
-  int  (*mcast)(struct instance*, u32 ip, u8 set);
-  int  (*write_hwaddr)(struct instance*);
-};
-
-Next, there'll be platform data which will be per-driver and will replace the
-"priv" part of "struct eth_device". Last part will be the per-device core state.
-
-With regards to the PHY part of the API, the "struct phy_driver" is almost ready
-to be used with the new driver model approach. The only change will be the
-replacement of per-driver initialization functions and removal of
-"phy_register()" function in favor or driver model approach.
-
-III) Analysis of in-tree drivers
---------------------------------
-
-  1) drivers/net/4xx_enet.c
-  -------------------------
-
-  This driver uses the standard new networking API, therefore there should be no
-  obstacles throughout the conversion process.
-
-  2) drivers/net/altera_tse.c
-  ---------------------------
-
-  This driver uses the standard new networking API, therefore there should be no
-  obstacles throughout the conversion process.
-
-  3) drivers/net/armada100_fec.c
-  ------------------------------
-
-  This driver uses the standard new networking API, therefore there should be no
-  obstacles throughout the conversion process.
-
-  4) drivers/net/at91_emac.c
-  --------------------------
-
-  This driver uses the standard new networking API, therefore there should be no
-  obstacles throughout the conversion process.
-
-  5) drivers/net/ax88180.c
-  ------------------------
-
-  This driver uses the standard new networking API, therefore there should be no
-  obstacles throughout the conversion process.
-
-  6) drivers/net/ax88796.c
-  ------------------------
-
-  This file contains a components of the NE2000 driver, implementing only
-  different parts on the NE2000 clone AX88796. This being no standalone driver,
-  no conversion will be done here.
-
-  7) drivers/net/bfin_mac.c
-  -------------------------
-
-  This driver uses the standard new networking API, therefore there should be no
-  obstacles throughout the conversion process.
-
-  8) drivers/net/calxedaxgmac.c
-  -----------------------------
-
-  This driver uses the standard new networking API, therefore there should be no
-  obstacles throughout the conversion process.
-
-  9) drivers/net/cs8900.c
-  -----------------------
-
-  This driver uses the standard new networking API, therefore there should be no
-  obstacles throughout the conversion process.
-
-  10) drivers/net/davinci_emac.c
-  ------------------------------
-
-  This driver uses the standard new networking API, therefore there should be no
-  obstacles throughout the conversion process.
-
-  11) drivers/net/dc2114x.c
-  -------------------------
-
-  This driver uses the standard new networking API, therefore there should be no
-  obstacles throughout the conversion process.
-
-  12) drivers/net/designware.c
-  ----------------------------
-
-  This driver uses the standard new networking API, therefore there should be no
-  obstacles throughout the conversion process.
-
-  13) drivers/net/dm9000x.c
-  -------------------------
-
-  This driver uses the standard new networking API, therefore there should be no
-  obstacles throughout the conversion process.
-
-  14) drivers/net/dnet.c
-  ----------------------
-
-  This driver uses the standard new networking API, therefore there should be no
-  obstacles throughout the conversion process.
-
-  15) drivers/net/e1000.c
-  -----------------------
-
-  This driver uses the standard new networking API, therefore there should be no
-  obstacles throughout the conversion process.
-
-  16) drivers/net/e1000_spi.c
-  ---------------------------
-
-  Driver for the SPI bus integrated on the Intel E1000. This is not part of the
-  network stack.
-
-  17) drivers/net/eepro100.c
-  --------------------------
-
-  This driver uses the standard new networking API, therefore there should be no
-  obstacles throughout the conversion process.
-
-  18) drivers/net/enc28j60.c
-  --------------------------
-
-  This driver uses the standard new networking API, therefore there should be no
-  obstacles throughout the conversion process.
-
-  19) drivers/net/ep93xx_eth.c
-  ----------------------------
-
-  This driver uses the standard new networking API, therefore there should be no
-  obstacles throughout the conversion process.
-
-  20) drivers/net/ethoc.c
-  -----------------------
-
-  This driver uses the standard new networking API, therefore there should be no
-  obstacles throughout the conversion process.
-
-  21) drivers/net/fec_mxc.c
-  -------------------------
-
-  This driver uses the standard new networking API, therefore there should be no
-  obstacles throughout the conversion process.
-
-  22) drivers/net/fsl_mcdmafec.c
-  ------------------------------
-
-  This driver uses the standard new networking API, therefore there should be no
-  obstacles throughout the conversion process.
-
-  23) drivers/net/fsl_mdio.c
-  --------------------------
-
-  This file contains driver for FSL MDIO interface, which is not part of the
-  networking stack.
-
-  24) drivers/net/ftgmac100.c
-  ---------------------------
-
-  This driver uses the standard new networking API, therefore there should be no
-  obstacles throughout the conversion process.
-
-  25) drivers/net/ftmac100.c
-  --------------------------
-
-  This driver uses the standard new networking API, therefore there should be no
-  obstacles throughout the conversion process.
-
-  26) drivers/net/greth.c
-  -----------------------
-
-  This driver uses the standard new networking API, therefore there should be no
-  obstacles throughout the conversion process.
-
-  27) drivers/net/inca-ip_sw.c
-  ----------------------------
-
-  This driver uses the standard new networking API, therefore there should be no
-  obstacles throughout the conversion process.
-
-  28) drivers/net/ks8695eth.c
-  ---------------------------
-
-  This driver uses the standard new networking API, therefore there should be no
-  obstacles throughout the conversion process.
-
-  29) drivers/net/lan91c96.c
-  --------------------------
-
-  This driver uses the standard new networking API, therefore there should be no
-  obstacles throughout the conversion process.
-
-  30) drivers/net/macb.c
-  ----------------------
-
-  This driver uses the standard new networking API, therefore there should be no
-  obstacles throughout the conversion process.
-
-  31) drivers/net/mcffec.c
-  ------------------------
-
-  This driver uses the standard new networking API, therefore there should be no
-  obstacles throughout the conversion process.
-
-  32) drivers/net/mcfmii.c
-  ------------------------
-
-  This file contains MII interface driver for MCF FEC.
-
-  33) drivers/net/mpc512x_fec.c
-  -----------------------------
-
-  This driver uses the standard new networking API, therefore there should be no
-  obstacles throughout the conversion process.
-
-  34) drivers/net/mpc5xxx_fec.c
-  -----------------------------
-
-  This driver uses the standard new networking API, therefore there should be no
-  obstacles throughout the conversion process.
-
-  35) drivers/net/mvgbe.c
-  -----------------------
-
-  This driver uses the standard new networking API, therefore there should be no
-  obstacles throughout the conversion process.
-
-  36) drivers/net/natsemi.c
-  -------------------------
-
-  This driver uses the standard new networking API, therefore there should be no
-  obstacles throughout the conversion process.
-
-  37) drivers/net/ne2000_base.c
-  -----------------------------
-
-  This driver uses the standard new networking API, therefore there should be no
-  obstacles throughout the conversion process. This driver contains the core
-  implementation of NE2000, which needs a few external functions, implemented by
-  AX88796, NE2000 etc.
-
-  38) drivers/net/ne2000.c
-  ------------------------
-
-  This file implements external functions necessary for native NE2000 compatible
-  networking card to work.
-
-  39) drivers/net/netarm_eth.c
-  ----------------------------
-
-  This driver uses the old, legacy, network API and will either have to be
-  converted or removed.
-
-  40) drivers/net/netconsole.c
-  ----------------------------
-
-  This is actually an STDIO driver.
-
-  41) drivers/net/ns8382x.c
-  -------------------------
-
-  This driver uses the standard new networking API, therefore there should be no
-  obstacles throughout the conversion process.
-
-  42) drivers/net/pcnet.c
-  -----------------------
-
-  This driver uses the standard new networking API, therefore there should be no
-  obstacles throughout the conversion process.
-
-  43) drivers/net/plb2800_eth.c
-  -----------------------------
-
-  This driver uses the standard new networking API, therefore there should be no
-  obstacles throughout the conversion process.
-
-  44) drivers/net/rtl8139.c
-  -------------------------
-
-  This driver uses the standard new networking API, therefore there should be no
-  obstacles throughout the conversion process.
-
-  45) drivers/net/rtl8169.c
-  -------------------------
-
-  This driver uses the standard new networking API, therefore there should be no
-  obstacles throughout the conversion process.
-
-  46) drivers/net/sh_eth.c
-  ------------------------
-
-  This driver uses the standard new networking API, therefore there should be no
-  obstacles throughout the conversion process.
-
-  47) drivers/net/smc91111.c
-  --------------------------
-
-  This driver uses the standard new networking API, therefore there should be no
-  obstacles throughout the conversion process.
-
-  48) drivers/net/smc911x.c
-  -------------------------
-
-  This driver uses the standard new networking API, therefore there should be no
-  obstacles throughout the conversion process.
-
-  49) drivers/net/tsec.c
-  ----------------------
-
-  This driver uses the standard new networking API, therefore there should be no
-  obstacles throughout the conversion process.
-
-  50) drivers/net/tsi108_eth.c
-  ----------------------------
-
-  This driver uses the standard new networking API, therefore there should be no
-  obstacles throughout the conversion process.
-
-  51) drivers/net/uli526x.c
-  -------------------------
-
-  This driver uses the standard new networking API, therefore there should be no
-  obstacles throughout the conversion process.
-
-  52) drivers/net/vsc7385.c
-  -------------------------
-
-  This is a driver that only uploads firmware to a switch. This is not subject
-  of conversion.
-
-  53) drivers/net/xilinx_axi_emac.c
-  ---------------------------------
-
-  This driver uses the standard new networking API, therefore there should be no
-  obstacles throughout the conversion process.
-
-  54) drivers/net/xilinx_emaclite.c
-  ---------------------------------
-
-  This driver uses the standard new networking API, therefore there should be no
-  obstacles throughout the conversion process.
diff --git a/doc/driver-model/UDM-pci.txt b/doc/driver-model/UDM-pci.txt
deleted file mode 100644
index 6a592b3368..0000000000
--- a/doc/driver-model/UDM-pci.txt
+++ /dev/null
@@ -1,257 +0,0 @@
-The U-Boot Driver Model Project
-===============================
-PCI subsystem analysis
-======================
-
-Pavel Herrmann <morpheus.ibis@gmail.com>
-2012-03-17
-
-I) Overview
------------
-
-  U-Boot already supports multiple PCI busses, stored in a linked-list of
-  pci_controller structures. This structure contains generic driver data, bus
-  interface operations and private data for the driver.
-
-  Bus interface operations for PCI are (names are self-explanatory):
-
-    read_byte()
-    read_word()
-    read_dword()
-    write_byte()
-    write_word()
-    write_dword()
-
-  Each driver has to implement dword operations, and either implement word and
-  byte operations, or use shared $operation_config_$type_via_dword (eg.
-  read_config_byte_via_dword and similar) function. These functions are used
-  for config space I/O (read_config_dword and similar functions of the PCI
-  subsystem), which is used to configure the connected devices for standard MMIO
-  operations. All data transfers by respective device drivers are then done by
-  MMIO
-
-  Each driver also defines a separate init function, which has unique symbol
-  name, and thus more drivers can be compiled in without colliding. This init
-  function is typically called from pci_init_board(), different for each
-  particular board.
-
-  Some boards also define a function called fixup_irq, which gets called after
-  scanning the PCI bus for devices, and should dismiss any interrupts.
-
-  Several drivers are also located in arch/ and should be moved to drivers/pci.
-
-II) Approach
-------------
-
-  The pci_controller structure needs to be broken down to fit the new driver
-  model. Due to a large number of members, this will be done through three
-  distinct accessors, one for memory regions, one for config table and one for
-  everything else. That will make the pci_ops structure look like this:
-
-    struct pci_ops {
-      int (*read_byte)(struct instance *bus, pci_dev_t *dev, int addr,
-		       u8 *buf);
-      int (*read_word)(struct instance *bus, pci_dev_t *dev, int addr,
-		       u16 *buf);
-      int (*read_dword)(struct instance *bus, pci_dev_t *dev, int addr,
-			u32 *buf);
-      int (*write_byte)(struct instance *bus, pci_dev_t *dev, int addr,
-			u8 val);
-      int (*write_byte)(struct instance *bus, pci_dev_t *dev, int addr,
-			u8 val);
-      int (*write_dword)(struct instance *bus, pci_dev_t *dev, int addr,
-			 u32 val);
-      void (*fixup_irq)(struct instance *bus, pci_dev_t *dev);
-      struct pci_region* (*get_region)(struct instance *, uint num);
-      struct pci_config_table* (*get_cfg_table)(struct instance *bus);
-      uint (*get_option)(struct instance * bus, enum pci_option_code op);
-    }
-
-    enum pci_option_code {
-      PCI_OPT_BUS_NUMBER=0,
-      PCI_OPT_REGION_COUNT,
-      PCI_OPT_INDIRECT_TYPE,
-      PCI_OPT_AUTO_MEM,
-      PCI_OPT_AUTO_IO,
-      PCI_OPT_AUTO_PREFETCH,
-      PCI_OPT_AUTO_FB,
-      PCI_OPT_CURRENT_BUS,
-      PCI_OPT_CFG_ADDR,
-    }
-
-  The return value for get_option will be an unsigned integer value for any
-  option code. If the option currently is a pointer to pci_region, it will
-  return an index for get_region function. Special case has to be made for
-  PCI_OPT_CFG_ADDR, which should be interpreted as a pointer, but it is only
-  used for equality in find_hose_by_cfg_addr, and thus can be returned as an
-  uint. Other function using cfg_addr value are read/write functions for
-  specific drivers (especially ops for indirect bridges), and thus have access
-  to private_data of the driver instance.
-
-  The config table accessor will return a pointer to a NULL-terminated array of
-  pci_config_table, which is supplied by the board in platform_data, or NULL if
-  the board didn't specify one. This table is used to override PnP
-  auto-initialization, or to specific initialization functions for non-PNP
-  devices.
-
-  Transparent PCI-PCI bridges will get their own driver, and will forward all
-  operations to operations of their parent bus. This however makes it
-  impossible to use instances to identify devices, as not all devices will be
-  directly visible to the respective bus driver.
-
-  Init functions of controller drivers will be moved to their respective
-  probe() functions, in accordance to the driver model.
-
-  The PCI core will handle all mapping functions currently found in pci.c, as
-  well as proxy functions for read/write operations of the drivers. The PCI
-  core will also handle bus scanning and device configuration.
-
-  The PnP helper functions currently in pci_auto.c will also be a part of PCI
-  core, but they will be exposed only to PCI controller drivers, not to other
-  device drivers.
-
-  The PCI API for device drivers will remain largely unchanged, most drivers
-  will require no changes at all, and all modifications will be limited to
-  changing the pci_controlle into instance*.
-
-III) Analysis of in-tree drivers
---------------------------------
-
-  A) drivers in drivers/pci/
-  --------------------------
-
-    1) pci_indirect.c
-    -----------------
-      Shared driver for indirect PCI bridges, several CONFIG macros - will
-      require significant cleanup.
-
-    2) pci_ixp.c
-    ------------
-      Standard driver, specifies all read/write functions separately.
-
-    3) pci_sh4.c
-    ------------
-      Shared init function for SH4 drivers, uses dword for read/write ops.
-
-    4) pci_sh7751.c
-    ---------------
-      Standard driver, uses SH4 shared init.
-
-    5) pci_sh7780.c
-    ---------------
-      Standard driver, uses SH4 shared init.
-
-    6) tsi108_pci.c
-    ---------------
-      Standard driver, uses dword for read/write ops.
-
-    7) fsl_pci_init.c
-    -----------------
-      Driver for PCI and PCI-e, uses indirect functions.
-
-    8) pci_ftpci100.c
-    -----------------
-      Standard driver, uses indirect functions, has separate scan/setup
-      functions.
-
-  B) driver in arch/
-  ------------------
-
-    1) x86/lib/pci_type1.c
-    ----------------------
-      Standard driver, specifies all read/write functions separately.
-
-    2) m68k/cpu/mcf5445x/pci.c
-    --------------------------
-      Standard driver, specifies all read/write functions separately.
-
-    3) m68k/cpu/mcf547x_8x/pci.c
-    ----------------------------
-      Standard driver, specifies all read/write functions separately.
-
-    4) powerpc/cpu/mpc824x/pci.c
-    ----------------------------
-      Standard driver, uses indirect functions, does not setup HW.
-
-    5) powerpc/cpu/mpc8260/pci.c
-    ----------------------------
-      Standard driver, uses indirect functions.
-
-    6) powerpc/cpu/ppc4xx/4xx_pci.c
-    -------------------------------
-      Standard driver, uses indirect functions.
-
-    7) powerpc/cpu/ppc4xx/4xx_pcie.c
-    --------------------------------
-      PCI-e driver, specifies all read/write functions separately.
-
-    8) powerpc/cpu/mpc83xx/pci.c
-    ----------------------------
-      Standard driver, uses indirect functions.
-
-    9) powerpc/cpu/mpc83xx/pcie.c
-    -----------------------------
-      PCI-e driver, specifies all read/write functions separately.
-
-    10) powerpc/cpu/mpc5xxx/pci_mpc5200.c
-    -------------------------------------
-      Standard driver, uses dword for read/write ops.
-
-    11) powerpc/cpu/mpc512x/pci.c
-    -----------------------------
-      Standard driver, uses indirect functions.
-
-    12) powerpc/cpu/mpc85xx/pci.c
-    -----------------------------
-      Standard driver, uses indirect functions, has two busses.
-
-  C) drivers in board/
-  --------------------
-
-    1) eltec/elppc/pci.c
-    --------------------
-      Standard driver, uses indirect functions.
-
-    2) amirix/ap1000/pci.c
-    ----------------------
-      Standard driver, specifies all read/write functions separately.
-
-    3) prodrive/p3mx/pci.c
-    ----------------------
-      Standard driver, uses dword for read/write ops, has two busses.
-
-    4) esd/cpci750/pci.c
-    --------------------
-      Standard driver, uses dword for read/write ops, has two busses.
-
-    5) esd/common/pci.c
-    -------------------
-      Standard driver, uses dword for read/write ops.
-
-    6) dave/common/pci.c
-    --------------------
-      Standard driver, uses dword for read/write ops.
-
-    7) ppmc7xx/pci.c
-    ----------------
-      Standard driver, uses indirect functions.
-
-    9) Marvell/db64360/pci.c
-    ------------------------
-      Standard driver, uses dword for read/write ops, has two busses.
-
-    10) Marvell/db64460/pci.c
-    -------------------------
-      Standard driver, uses dword for read/write ops, has two busses.
-
-    11) evb64260/pci.c
-    ------------------
-      Standard driver, uses dword for read/write ops, has two busses.
-
-    12) armltd/integrator/pci.c
-    ---------------------------
-      Standard driver, specifies all read/write functions separately.
-
-  All drivers will be moved to drivers/pci. Several drivers seem
-  similar/identical, especially those located under board, and may be merged
-  into one.
diff --git a/doc/driver-model/UDM-pcmcia.txt b/doc/driver-model/UDM-pcmcia.txt
deleted file mode 100644
index fc31461ca7..0000000000
--- a/doc/driver-model/UDM-pcmcia.txt
+++ /dev/null
@@ -1,78 +0,0 @@
-The U-Boot Driver Model Project
-===============================
-PCMCIA analysis
-===============
-Viktor Krivak <viktor.krivak@gmail.com>
-2012-03-17
-
-I) Overview
------------
-
-  U-boot implements only 2 methods to interoperate with pcmcia. One to turn
-  device on and other to turn device off. Names of these methods are usually
-  pcmcia_on() and pcmcia_off() without any parameters. Some files in driver
-  directory implements only internal API. These methods aren't used outside
-  driver directory and they are not converted to new driver model.
-
-II) Approach
------------
-
-  1) New API
-  ----------
-
-    Current API is preserved and all internal methods are hiden.
-
-    struct ops {
-      void (*pcmcia_on)(struct instance *i);
-      void (*pcmcia_off)(struct instance *i);
-    }
-
-  2) Conversion
-  -------------
-
-    In header file pcmcia.h are some other variables which are used for
-    additional configuration. But all have to be moved to platform data or to
-    specific driver implementation.
-
-  3) Platform data
-  ----------------
-
-    Many boards have custom implementation of internal API. Pointers to these
-    methods are stored in platform_data. But the most implementations for Intel
-    82365 and compatible PC Card controllers and Yenta-compatible
-    PCI-to-CardBus controllers implement whole API per board. In these cases
-    pcmcia_on() and pcmcia_off() behave only as wrappers and call specific
-    board methods.
-
-III) Analysis of in-tree drivers
---------------------------------
-
-  1) i82365.c
-  -----------
-    Driver methods have different name i82365_init() and i82365_exit but
-    all functionality is the same. Board files board/atc/ti113x.c and
-    board/cpc45/pd67290.c use their own implementation of these method.
-    In this case all methods in driver behave only as wrappers.
-
-  2) marubun_pcmcia.c
-  -------------------
-    Meets standard API behaviour. Simple conversion.
-
-  3) mpc8xx_pcmcia.c
-  ------------------
-    Meets standard API behaviour. Simple conversion.
-
-  4) rpx_pcmcia.c
-  ---------------
-    Implements only internal API used in other drivers. Non of methods
-    implemented here are used outside driver model.
-
-  5) ti_pci1410a.c
-  ----------------
-    Has different API but methods in this file are never called. Probably
-    dead code.
-
-  6)tqm8xx_pcmcia.c
-  -----------------
-    Implements only internal API used in other drivers. Non of methods
-    implemented here are used outside driver model.
diff --git a/doc/driver-model/UDM-power.txt b/doc/driver-model/UDM-power.txt
deleted file mode 100644
index 015c7737f6..0000000000
--- a/doc/driver-model/UDM-power.txt
+++ /dev/null
@@ -1,88 +0,0 @@
-The U-Boot Driver Model Project
-===============================
-POWER analysis
-==============
-Viktor Krivak <viktor.krivak@gmail.com>
-2012-03-09
-
-I) Overview
------------
-
-  1) Actual state
-  ---------------
-
-  At this moment power doesn't contain API. There are many methods for
-  initialization of some board specific functions but only few does what is
-  expected. Basically only one file contains something meaningful for this
-  driver.
-
-  2) Current implementation
-  -------------------------
-
-  In file twl6030.c are methods twl6030_stop_usb_charging() and
-  twl6030_start_usb_charging() for start and stop charging from USB. There are
-  also methods to get information about battery state and initialization of
-  battery charging. Only these methods are used in converted API.
-
-
-II) Approach
-------------
-
-  1) New API
-  ----------
-
-  New API implements only functions specific for managing power. All board
-  specific init methods are moved to other files. Name of methods are
-  self-explanatory.
-
-  struct ops {
-    void (*start_usb_charging)(struct instance *i);
-    void (*stop_usb_charging)(struct instance *i);
-    int  (*get_battery_current)(struct instance *i);
-    int  (*get_battery_voltage)(struct instance *i);
-    void (*init_battery_charging)(struct instance *i);
-  }
-
-  2) Conversions of other methods
-  -------------------------------
-
-  Methods that can't be converted to new API are moved to board file or to
-  special file for board hacks.
-
-III) Analysis of in-tree drivers
---------------------------------
-
-  1) ftpmu010.c
-  -------------
-  All methods of this file are moved to another location.
-    void ftpmu010_32768osc_enable(void): Move to boards hacks
-    void ftpmu010_mfpsr_select_dev(unsigned int dev): Move to board file
-						      arch/nds32/lib/board.c
-    void ftpmu010_mfpsr_diselect_dev(unsigned int dev): Dead code
-    void ftpmu010_dlldis_disable(void): Dead code
-    void ftpmu010_sdram_clk_disable(unsigned int cr0): Move to board file
-						       arch/nds32/lib/board.c
-    void ftpmu010_sdramhtc_set(unsigned int val): Move to board file
-						  arch/nds32/lib/board.c
-
-  2) twl4030.c
-  ------------
-  All methods of this file are moved to another location.
-    void twl4030_power_reset_init(void): Move to board hacks
-    void twl4030_pmrecv_vsel_cfg(u8 vsel_reg, u8 vsel_val, u8 dev_grp,
-				 u8 dev_grp_sel): Move to board hacks
-    void twl4030_power_init(void): Move to board hacks
-    void twl4030_power_mmc_init(void): Move to board hacks
-
-  3) twl6030.c
-  ------------
-  Some methods are converted to new API and rest are moved to another location.
-    void twl6030_stop_usb_charging(void): Convert to new API
-    void twl6030_start_usb_charging(void): Convert to new API
-    int twl6030_get_battery_current(void): Convert to new API
-    int twl6030_get_battery_voltage(void): Convert to new API
-    void twl6030_init_battery_charging(void): Convert to new API
-    void twl6030_power_mmc_init(): Move to board file
-				   drivers/mmc/omap_hsmmc.c
-    void twl6030_usb_device_settings(): Move to board file
-					drivers/usb/musb/omap3.c
diff --git a/doc/driver-model/UDM-rtc.txt b/doc/driver-model/UDM-rtc.txt
deleted file mode 100644
index 8391f38723..0000000000
--- a/doc/driver-model/UDM-rtc.txt
+++ /dev/null
@@ -1,253 +0,0 @@
-=============================
-RTC device subsystem analysis
-=============================
-
-Tomas Hlavacek <tmshlvck@gmail.com>
-2012-03-10
-
-I) Overview
------------
-
-U-Boot currently implements one common API for RTC devices. The interface
-is defined in include/rtc.h and comprises of functions and structures:
-
-    struct rtc_time {
-	int tm_sec;
-	int tm_min;
-	int tm_hour;
-	int tm_mday;
-	int tm_mon;
-	int tm_year;
-	int tm_wday;
-	int tm_yday;
-	int tm_isdst;
-    };
-
-    int rtc_get (struct rtc_time *);
-    int rtc_set (struct rtc_time *);
-    void rtc_reset (void);
-
-The functions are implemented by a proper device driver in drivers/rtc
-directory and the driver to be compiled in is selected in a Makefile.
-Drivers are mutually exclusive.
-
-Drivers depends on date code in drivers/rtc/date.c and naturally on board
-specific data.
-
-II) Approach
-------------
-
-  1) New API
-  ----------
-  In the UDM each rtc driver would register itself by a function
-
-    int rtc_device_register(struct instance *i,
-			    struct rtc_device_ops *o);
-
-  The structure being defined as follows:
-
-    struct rtc_device_ops {
-	int  (*get_time)(struct instance *i, struct rtc_time *t);
-	int  (*set_time)(struct instance *i, struct rtc_time *t);
-	int  (*reset)(struct instance *i);
-    };
-
-
-  2) Conversion thougths
-  ----------------------
-  U-Boot RTC drivers exports the same functions and therefore the conversion
-  of the drivers is straight-forward. There is no initialization needed.
-
-
-III) Analysis of in-tree drivers
---------------------------------
-
-  1) drivers/rtc/rv3029.c
-  -----------------------
-  The driver is standard rtc. Simple conversion is possible.
-
-
-  2) drivers/rtc/s3c24x0_rtc.c
-  ----------------------------
-  The driver is standard rtc. Simple conversion is possible.
-
-
-  3) drivers/rtc/pt7c4338.c
-  -------------------------
-  The driver is standard rtc. Simple conversion is possible.
-
-
-  4) drivers/rtc/mvrtc.c
-  ----------------------
-  The driver is standard rtc. Simple conversion is possible.
-
-
-  5) drivers/rtc/ftrtc010.c
-  -------------------------
-  The driver is standard rtc. Simple conversion is possible.
-
-
-  6) drivers/rtc/mpc5xxx.c
-  ------------------------
-  The driver is standard rtc. Simple conversion is possible.
-
-
-  7) drivers/rtc/ds164x.c
-  -----------------------
-  The driver is standard rtc. Simple conversion is possible.
-
-
-  8) drivers/rtc/rs5c372.c
-  ------------------------
-  The driver is standard rtc. Simple conversion is possible.
-
-
-  9) drivers/rtc/m41t94.c
-  -----------------------
-  The driver is standard rtc. Simple conversion is possible.
-
-
-  10) drivers/rtc/mc13xxx-rtc.c
-  -----------------------------
-  The driver is standard rtc. Simple conversion is possible.
-
-
-  11) drivers/rtc/mcfrtc.c
-  ------------------------
-  The driver is standard rtc. Simple conversion is possible.
-
-
-  12) drivers/rtc/davinci.c
-  -------------------------
-  The driver is standard rtc. Simple conversion is possible.
-
-
-  13) drivers/rtc/rx8025.c
-  ------------------------
-  The driver is standard rtc. Simple conversion is possible.
-
-
-  14) drivers/rtc/bfin_rtc.c
-  --------------------------
-  The driver is standard rtc. Simple conversion is possible.
-
-
-  15) drivers/rtc/m41t62.c
-  ------------------------
-  The driver is standard rtc. Simple conversion is possible.
-
-
-  16) drivers/rtc/ds1306.c
-  ------------------------
-  The driver is standard rtc. Simple conversion is possible.
-
-
-  17) drivers/rtc/mpc8xx.c
-  ------------------------
-  The driver is standard rtc. Simple conversion is possible.
-
-
-  18) drivers/rtc/ds3231.c
-  ------------------------
-  The driver is standard rtc. Simple conversion is possible.
-
-
-  19) drivers/rtc/ds12887.c
-  -------------------------
-  The driver is standard rtc. Simple conversion is possible.
-
-
-  20) drivers/rtc/ds1302.c
-  ------------------------
-  The driver is standard rtc. Simple conversion is possible.
-
-
-  21) drivers/rtc/ds1374.c
-  ------------------------
-  The driver is standard rtc. Simple conversion is possible.
-
-
-  22) drivers/rtc/ds174x.c
-  ------------------------
-  The driver is standard rtc. Simple conversion is possible.
-
-
-  23) drivers/rtc/m41t60.c
-  ------------------------
-  The driver is standard rtc. Simple conversion is possible.
-
-
-  24) drivers/rtc/m48t35ax.c
-  --------------------------
-  The driver is standard rtc. Simple conversion is possible.
-
-
-  25) drivers/rtc/pl031.c
-  -----------------------
-  The driver is standard rtc. Simple conversion is possible.
-
-
-  26) drivers/rtc/x1205.c
-  -----------------------
-  The driver is standard rtc. Simple conversion is possible.
-
-
-  27) drivers/rtc/m41t11.c
-  ------------------------
-  The driver is standard rtc. Simple conversion is possible.
-
-
-  28) drivers/rtc/pcf8563.c
-  -------------------------
-  The driver is standard rtc. Simple conversion is possible.
-
-
-  29) drivers/rtc/mk48t59.c
-  -------------------------
-  Macros needs cleanup. Besides that the driver is standard rtc.
-  Simple conversion is possible.
-
-
-  30) drivers/rtc/mxsrtc.c
-  ------------------------
-  The driver is standard rtc. Simple conversion is possible.
-
-
-  31) drivers/rtc/ds1307.c
-  ------------------------
-  The driver is standard rtc. Simple conversion is possible.
-
-
-  32) drivers/rtc/ds1556.c
-  ------------------------
-  The driver is standard rtc. Simple conversion is possible.
-
-
-  33) drivers/rtc/rtc4543.c
-  -------------------------
-  The driver is standard rtc. Simple conversion is possible.
-
-
-  34) drivers/rtc/ds1337.c
-  ------------------------
-  The driver is standard rtc. Simple conversion is possible.
-
-
-  35) drivers/rtc/isl1208.c
-  -------------------------
-  The driver is standard rtc. Simple conversion is possible.
-
-
-  36) drivers/rtc/max6900.c
-  -------------------------
-  The driver is standard rtc. Simple conversion is possible.
-
-
-  37) drivers/rtc/mc146818.c
-  --------------------------
-  The driver is standard rtc. Simple conversion is possible.
-
-
-  38) drivers/rtc/at91sam9_rtt.c
-  ------------------------------
-  The driver is standard rtc. Simple conversion is possible.
diff --git a/doc/driver-model/UDM-serial.txt b/doc/driver-model/UDM-serial.txt
deleted file mode 100644
index 54f853e0e4..0000000000
--- a/doc/driver-model/UDM-serial.txt
+++ /dev/null
@@ -1,175 +0,0 @@
-The U-Boot Driver Model Project
-===============================
-Serial I/O analysis
-===================
-Marek Vasut <marek.vasut@gmail.com>
-2012-02-20
-
-I) Overview
------------
-
-The serial port support currently requires the driver to export the following
-functions:
-
-  serial_putc() ...... Output a character
-  serial_puts() ...... Output string, often done using serial_putc()
-  serial_tstc() ...... Test if incoming character is in a buffer
-  serial_getc() ...... Retrieve incoming character
-  serial_setbrg() .... Configure port options
-  serial_init() ...... Initialize the hardware
-
-The simpliest implementation, supporting only one port, simply defines these six
-functions and calls them. Such calls are scattered all around U-Boot, especiall
-serial_putc(), serial_puts(), serial_tstc() and serial_getc(). The serial_init()
-and serial_setbrg() are often called from platform-dependent places.
-
-It's important to consider current implementation of CONFIG_SERIAL_MULTI though.
-This resides in common/serial.c and behaves as a multiplexer for serial ports.
-This, by calling serial_assign(), allows user to switch I/O from one serial port
-to another. Though the environmental variables "stdin", "stdout", "stderr"
-remain set to "serial".
-
-These variables are managed by the IOMUX. This resides in common/iomux.c and
-manages all console input/output from U-Boot. For serial port, only one IOMUX is
-always registered, called "serial" and the switching of different serial ports
-is done by code in common/serial.c.
-
-On a final note, it's important to mention function default_serial_console(),
-which is platform specific and reports the default serial console for the
-platform, unless proper environment variable overrides this.
-
-II) Approach
-------------
-
-Drivers not using CONFIG_SERIAL_MULTI already will have to be converted to
-similar approach. The probe() function of a driver will call a function
-registering the driver with a STDIO subsystem core, stdio_device_register().
-
-The serial_init() function will now be replaced by probe() function of the
-driver, the rest of the components of the driver will be converted to standard
-STDIO driver calls. See [ UDM-stdio.txt ] for details.
-
-The serial_setbrg() function depends on global data pointer. This is wrong,
-since there is likely to be user willing to configure different baudrate on two
-different serial ports. The function will be replaced with STDIO's "conf()"
-call, with STDIO_CONFIG_SERIAL_BAUDRATE argument.
-
-III) Analysis of in-tree drivers
---------------------------------
-
-  1) altera_jtag_uart.c
-  ---------------------
-  No support for CONFIG_SERIAL_MULTI. Simple conversion possible.
-
-  2) altera_uart.c
-  ----------------
-  No support for CONFIG_SERIAL_MULTI. Simple conversion possible.
-
-  3) arm_dcc.c
-  ------------
-  No support for CONFIG_SERIAL_MULTI. Simple conversion possible, unless used
-  with CONFIG_ARM_DCC_MULTI. Then it registers another separate IOMUX.
-
-  4) atmel_usart.c
-  ----------------
-  No support for CONFIG_SERIAL_MULTI. Simple conversion possible.
-
-  5) mcfuart.c
-  ------------
-  No support for CONFIG_SERIAL_MULTI. Simple conversion possible.
-
-  6) ns16550.c
-  ------------
-  This driver seems complicated and certain consideration will need to be made
-  during conversion. This driver is implemented in very universal manner,
-  therefore it'll be necessary to properly design it's platform_data.
-
-  7) ns9750_serial.c
-  ------------------
-  Unmaintained port. Code got removed.
-
-  8) opencores_yanu.c
-  -------------------
-  No support for CONFIG_SERIAL_MULTI. Simple conversion possible.
-
-  9) s3c4510b_uart.c
-  ------------------
-  No support for CONFIG_SERIAL_MULTI. Simple conversion possible.
-
-  10) sandbox.c
-  -------------
-  No support for CONFIG_SERIAL_MULTI. Simple conversion possible.
-
-  11) serial.c
-  ------------
-  This is a complementary part of NS16550 UART driver, see above.
-
-  12) serial_clps7111.c
-  ---------------------
-  No support for CONFIG_SERIAL_MULTI. Simple conversion possible.
-
-  13) serial_imx.c
-  ----------------
-  No support for CONFIG_SERIAL_MULTI. Simple conversion possible. This driver
-  might be removed in favor of serial_mxc.c .
-
-  14) serial_ixp.c
-  ----------------
-  No support for CONFIG_SERIAL_MULTI. Simple conversion possible.
-
-  15) serial_ks8695.c
-  -------------------
-  No support for CONFIG_SERIAL_MULTI. Simple conversion possible.
-
-  16) serial_max3100.c
-  --------------------
-  No support for CONFIG_SERIAL_MULTI. Simple conversion possible.
-
-  17) serial_mxc.c
-  ----------------
-  No support for CONFIG_SERIAL_MULTI. Simple conversion possible.
-
-  18) serial_netarm.c
-  -------------------
-  No support for CONFIG_SERIAL_MULTI. Simple conversion possible.
-
-  19) serial_pl01x.c
-  ------------------
-  No support for CONFIG_SERIAL_MULTI. Simple conversion possible, though this
-  driver in fact contains two drivers in total.
-
-  20) serial_pxa.c
-  ----------------
-  This driver is a bit complicated, but due to clean support for
-  CONFIG_SERIAL_MULTI, there are no expected obstructions throughout the
-  conversion process.
-
-  21) serial_s3c24x0.c
-  --------------------
-  This driver, being quite ad-hoc might need some work to bring back to shape.
-
-  22) serial_s5p.c
-  ----------------
-  No support for CONFIG_SERIAL_MULTI. Simple conversion possible.
-
-  23) serial_sa1100.c
-  -------------------
-  No support for CONFIG_SERIAL_MULTI. Simple conversion possible.
-
-  24) serial_sh.c
-  ---------------
-  No support for CONFIG_SERIAL_MULTI. Simple conversion possible.
-
-  25) serial_xuartlite.c
-  ----------------------
-  No support for CONFIG_SERIAL_MULTI. Simple conversion possible.
-
-  26) usbtty.c
-  ------------
-  This driver seems very complicated and entangled with USB framework. The
-  conversion might be complicated here.
-
-  27) arch/powerpc/cpu/mpc512x/serial.c
-  -------------------------------------
-  This driver supports CONFIG_SERIAL_MULTI. This driver will need to be moved to
-  proper place.
diff --git a/doc/driver-model/UDM-spi.txt b/doc/driver-model/UDM-spi.txt
deleted file mode 100644
index 6e6acc8787..0000000000
--- a/doc/driver-model/UDM-spi.txt
+++ /dev/null
@@ -1,200 +0,0 @@
-The U-Boot Driver Model Project
-===============================
-SPI analysis
-============
-Viktor Krivak <viktor.krivak@gmail.com>
-2012-03-03
-
-I) Overview
------------
-
-  1) The SPI driver
-  -----------------
-
-  At this moment U-Boot provides standard API that consist of 7 functions:
-
-  void spi_init(void);
-  struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
-				    unsigned int max_hz, unsigned int mode);
-  void spi_free_slave(struct spi_slave *slave);
-  int  spi_claim_bus(struct spi_slave *slave);
-  void spi_release_bus(struct spi_slave *slave);
-  int  spi_xfer(struct spi_slave *slave, unsigned int bitlen,
-		const void *dout, void *din, unsigned long flags);
-  int  spi_cs_is_valid(unsigned int bus, unsigned int cs);
-  void spi_cs_activate(struct spi_slave *slave);
-  void spi_cs_deactivate(struct spi_slave *slave);
-  void spi_set_speed(struct spi_slave *slave, uint hz);
-
-  Method spi_init() is usually empty. All necessary configuration are sets by
-  spi_setup_slave(). But this configuration is usually stored only in memory.
-  No real hardware sets are made. All hardware settings are provided by method
-  spi_claim_bus(). This method claims the bus and it can't be claimed again
-  until it's release. That's mean all calls of method spi_claim_bus() will
-  fail. But lots of cpu implementation don't meet this behaviour.
-  Method spi_release_bus() does exact opposite. It release bus directly by
-  some hardware sets. spi_free_slave() only free memory allocated by
-  spi_setup_slave(). Method spi_xfer() do actually read and write operation
-  throw specified bus and cs. Other methods are self explanatory.
-
-  2) Current limitations
-  ----------------------
-
-  Theoretically at this moment api allows use more then one bus per device at
-  the time. But in real this can be achieved only when all buses have their
-  own base addresses in memory.
-
-
-II) Approach
-------------
-
-  1) Claiming bus
-  ---------------
-
-  The current api cannot be used because struct spi_slave have to be in
-  private data. In that case user are prohibited to use different bus on one
-  device at same time. But when base memory address for bus are different.
-  It's possible make more instance of this driver. Otherwise it can't can be
-  done because of hardware limitation.
-
-  2) API change
-  -------------
-
-  Method spi_init() is moved to probe. Methods spi_setup_slave() and
-  spi_claim_bus() are joined to one method. This method checks if desired bus
-  exists and is available then configure necessary hardware and claims bus.
-  Method spi_release_bus() and spi_free_slave() are also joined to meet this
-  new approach. Other function remain same. Only struct spi_slave was change
-  to instance.
-
-  struct ops {
-    int  (*spi_request_bus)(struct instance *i, unsigned int bus,
-			    unsigned int cs, unsigned int max_hz,
-			    unsigned int mode);
-    void (*spi_release_bus)(struct instance *i);
-    int  (*spi_xfer) (struct instance *i, unsigned int bitlen,
-		      const void *dout, void *din, unsigned long flags);
-    int  (*spi_cs_is_valid)(struct instance *i, unsigned int bus,
-			    unsigned int cs);
-    void (*spi_cs_activate)(struct instance *i);
-    void (*spi_cs_deactivate)(struct instance *i);
-    void (*spi_set_speed)(struct instance *i, uint hz);
-  }
-
-  3) Legacy API
-  -------------
-
-  To easy conversion of the whole driver. Original and new api can exist next
-  to each other. New API is designed to be only a wrapper that extracts
-  necessary information from private_data and use old api. When driver can
-  use more than one bus at the time. New API require multiple instance. One
-  for each bus. In this case spi_slave have to be copied in each instance.
-
-  4) Conversion TIME-LINE
-  -----------------------
-
-  To prevent build corruption api conversion have to be processed in several
-  independent steps. In first step all old API methods are renamed. After that
-  new API and core function are implemented. Next step is conversion of all
-  board init methods to set platform data. After all these steps it is possible
-  to start conversion of all remaining calls. This procedure guarantees that
-  build procedure and binaries are never broken.
-
-III) Analysis of in-tree drivers
---------------------------------
-
-  1) altera_spi.c
-  ---------------
-  All methods have designated structure. Simple conversion possible.
-
-  2) andes_spi.c
-  --------------
-  All methods have designated structure. Simple conversion possible.
-
-  3) andes_spi.h
-  --------------
-  Support file for andes_spi.c. No conversion is needed.
-
-  4) armada100_spi.c
-  ------------------
-  All methods have designated structure. Simple conversion possible.
-
-  5) atmel_dataflash_spi.c
-  ------------------------
-  Wrong placement. Will be moved to another location.
-
-  6) atmel_spi.c
-  --------------
-  Supports more than one bus. Need some minor change.
-
-  7) atmel_spi.h
-  --------------
-  Support file for andes_spi.c. No conversion is needed.
-
-  8) bfin_spi.c
-  -------------
-  Supports more than one bus. Need some minor change.
-
-  9) cf_spi.c
-  -----------
-  Cooperate with some cpu specific methods from other files. Hard conversion.
-
-  10) davinci_spi.c
-  -----------------
-  All methods have designated structure. Simple conversion possible.
-
-  11) davinci_spi.h
-  -----------------
-  Support file for davinci_spi.h. No conversion is needed.
-
-  12) fsl_espi.c
-  --------------
-  All methods have designated structure. Simple conversion possible.
-
-  13) kirkwood_spi.c
-  ------------------
-  All methods have designated structure. Simple conversion possible.
-
-  14) mpc8xxx_spi.c
-  -----------------
-  All methods have designated structure. Simple conversion possible.
-
-  15) mpc52xx_spi.c
-  -----------------
-  All methods have designated structure. Simple conversion possible.
-
-  16) mxc_spi.c
-  -------------
-  All methods have designated structure. Simple conversion possible.
-
-  17) mxs_spi.c
-  -------------
-  All methods have designated structure. Simple conversion possible.
-
-  18) oc_tiny_spi.c
-  -----------------
-  Supports more than one bus. Need some minor change.
-
-  19) omap3_spi.c
-  ---------------
-  Supports more than one bus. Need some minor change.
-
-  20) omap3_spi.h
-  ---------------
-  Support file for omap3_spi.c. No conversion is needed.
-
-  21) sh_spi.c
-  ------------
-  All methods have designated structure. Simple conversion possible.
-
-  22) sh_spi.h
-  ------------
-  Support file for sh_spi.h. No conversion is needed.
-
-  23) soft_spi.c
-  --------------
-  Use many board specific method linked from other files. Need careful debugging.
-
-  24) tegra2_spi.c
-  ----------------
-  Some hardware specific problem when releasing bus.
diff --git a/doc/driver-model/UDM-stdio.txt b/doc/driver-model/UDM-stdio.txt
deleted file mode 100644
index c0b1c90b29..0000000000
--- a/doc/driver-model/UDM-stdio.txt
+++ /dev/null
@@ -1,191 +0,0 @@
-The U-Boot Driver Model Project
-===============================
-I/O system analysis
-===================
-Marek Vasut <marek.vasut@gmail.com>
-2012-02-20
-
-I) Overview
------------
-
-The console input and output is currently done using the STDIO subsystem in
-U-Boot. The design of this subsystem is already flexible enough to be easily
-converted to new driver model approach. Minor changes will need to be done
-though.
-
-Each device that wants to register with STDIO subsystem has to define struct
-stdio_dev, defined in include/stdio_dev.h and containing the following fields:
-
-struct stdio_dev {
-	int     flags;                  /* Device flags: input/output/system */
-	int     ext;                    /* Supported extensions              */
-	char    name[16];               /* Device name                       */
-
-/* GENERAL functions */
-
-	int (*start) (void);            /* To start the device               */
-	int (*stop) (void);             /* To stop the device                */
-
-/* OUTPUT functions */
-
-	void (*putc) (const char c);    /* To put a char                     */
-	void (*puts) (const char *s);   /* To put a string (accelerator)     */
-
-/* INPUT functions */
-
-	int (*tstc) (void);             /* To test if a char is ready...     */
-	int (*getc) (void);             /* To get that char                  */
-
-/* Other functions */
-
-	void *priv;                     /* Private extensions                */
-	struct list_head list;
-};
-
-Currently used flags are DEV_FLAGS_INPUT, DEV_FLAGS_OUTPUT and DEV_FLAGS_SYSTEM,
-extensions being only one, the DEV_EXT_VIDEO.
-
-The private extensions are now used as a per-device carrier of private data and
-finally list allows this structure to be a member of linked list of STDIO
-devices.
-
-The STDIN, STDOUT and STDERR routing is handled by environment variables
-"stdin", "stdout" and "stderr". By configuring the variable to the name of a
-driver, functions of such driver are called to execute that particular
-operation.
-
-II) Approach
-------------
-
-  1) Similarity of serial, video and keyboard drivers
-  ---------------------------------------------------
-
-  All of these drivers can be unified under the STDIO subsystem if modified
-  slightly. The serial drivers basically define both input and output functions
-  and need function to configure baudrate. The keyboard drivers provide only
-  input. On the other hand, video drivers provide output, but need to be
-  configured in certain way. This configuration might be dynamic, therefore the
-  STDIO has to be modified to provide such flexibility.
-
-  2) Unification of serial, video and keyboard drivers
-  ----------------------------------------------------
-
-  Every STDIO device would register a structure containing operation it supports
-  with the STDIO core by calling:
-
-    int stdio_device_register(struct instance *i, struct stdio_device_ops *o);
-
-  The structure being defined as follows:
-
-  struct stdio_device_ops {
-    void (*putc)(struct instance *i, const char c);
-    void (*puts)(struct instance *i, const char *s);    /* OPTIONAL */
-
-    int  (*tstc)(struct instance *i);
-    int  (*getc)(struct instance *i);
-
-    int  (*init)(struct instance *i);
-    int  (*exit)(struct instance *i);
-    int  (*conf)(struct instance *i, enum stdio_config c, const void *data);
-  };
-
-  The "putc()" function will emit a character, the "puts()" function will emit a
-  string. If both of these are set to NULL, the device is considered STDIN only,
-  aka input only device.
-
-  The "getc()" retrieves a character from a STDIN device, while "tstc()" tests
-  if there is a character in the buffer of STDIN device. In case these two are
-  set to NULL, this device is STDOUT / STDERR device.
-
-  Setting all "putc()", "puts()", "getc()" and "tstc()" calls to NULL isn't an
-  error condition, though such device does nothing. By instroducing tests for
-  these functions being NULL, the "flags" and "ext" fields from original struct
-  stdio_dev can be eliminated.
-
-  The "init()" and "exit()" calls are replacement for "start()" and "exit()"
-  calls in the old approach. The "priv" part of the old struct stdio_dev will be
-  replaced by common private data in the driver model and the struct list_head
-  list will be eliminated by introducing common STDIO core, that tracks all the
-  STDIO devices.
-
-  Lastly, the "conf()" call will allow the user to configure various options of
-  the driver. The enum stdio_config contains all possible configuration options
-  available to the STDIO devices, const void *data being the argument to be
-  configured. Currently, the enum stdio_config will contain at least the
-  following options:
-
-  enum stdio_config {
-    STDIO_CONFIG_SERIAL_BAUDRATE,
-  };
-
-  3) Transformation of stdio routing
-  ----------------------------------
-
-  By allowing multiple instances of drivers, the environment variables "stdin",
-  "stdout" and "stderr" can no longer be set to the name of the driver.
-  Therefore the STDIO core, tracking all of the STDIO devices in the system will
-  need to have a small amount of internal data for each device:
-
-  struct stdio_device_node {
-    struct instance          *i;
-    struct stdio_device_ops  *ops;
-    uint8_t                  id;
-    uint8_t                  flags;
-    struct list_head         list;
-  }
-
-  The "id" is the order of the instance of the same driver. The "flags" variable
-  allows multiple drivers to be used at the same time and even for different
-  purpose. The following flags will be defined:
-
-    STDIO_FLG_STDIN ..... This device will be used as an input device. All input
-			  from all devices with this flag set will be received
-			  and passed to the upper layers.
-    STDIO_FLG_STDOUT .... This device will be used as an output device. All
-			  output sent to stdout will be routed to all devices
-			  with this flag set.
-    STDIO_FLG_STDERR .... This device will be used as an standard error output
-			  device. All output sent to stderr will be routed to
-			  all devices with this flag set.
-
-  The "list" member of this structure allows to have a linked list of all
-  registered STDIO devices.
-
-III) Analysis of in-tree drivers
---------------------------------
-
-For in-depth analysis of serial port drivers, refer to [ UDM-serial.txt ].
-For in-depth analysis of keyboard drivers, refer to [ UDM-keyboard.txt ].
-For in-depth analysis of video drivers, refer to [ UDM-video.txt ].
-
-  1) arch/blackfin/cpu/jtag-console.c
-  -----------------------------------
-  This driver is a classic STDIO driver, no problem with conversion is expected.
-
-  2) board/mpl/pati/pati.c
-  ------------------------
-  This driver registers with the STDIO framework, though it uses a lot of ad-hoc
-  stuff which will need to be sorted out.
-
-  3) board/netphone/phone_console.c
-  ---------------------------------
-  This driver is a classic STDIO driver, no problem with conversion is expected.
-
-  4) drivers/net/netconsole.c
-  ---------------------------
-  This driver is a classic STDIO driver, no problem with conversion is expected.
-
-IV) Other involved files (To be removed)
-----------------------------------------
-
-common/cmd_console.c
-common/cmd_log.c
-common/cmd_terminal.c
-common/console.c
-common/fdt_support.c
-common/iomux.c
-common/lcd.c
-common/serial.c
-common/stdio.c
-common/usb_kbd.c
-doc/README.iomux
diff --git a/doc/driver-model/UDM-tpm.txt b/doc/driver-model/UDM-tpm.txt
deleted file mode 100644
index 0beff4a857..0000000000
--- a/doc/driver-model/UDM-tpm.txt
+++ /dev/null
@@ -1,48 +0,0 @@
-The U-Boot Driver Model Project
-===============================
-TPM system analysis
-===================
-Marek Vasut <marek.vasut@gmail.com>
-2012-02-23
-
-I) Overview
------------
-
-There is currently only one TPM chip driver available and therefore the API
-controlling it is very much based on this. The API is very simple:
-
-  int tis_open(void);
-  int tis_close(void);
-  int tis_sendrecv(const u8 *sendbuf, size_t send_size,
-			 u8 *recvbuf, size_t *recv_len);
-
-The command operating the TPM chip only provides operations to send and receive
-bytes from the chip.
-
-II) Approach
-------------
-
-The API can't be generalised too much considering there's only one TPM chip
-supported. But it's a good idea to split the tis_sendrecv() function in two
-functions. Therefore the new API will use register the TPM chip by calling:
-
-  tpm_device_register(struct instance *i, const struct tpm_ops *ops);
-
-And the struct tpm_ops will contain the following members:
-
-  struct tpm_ops {
-    int (*tpm_open)(struct instance *i);
-    int (*tpm_close)(struct instance *i);
-    int (*tpm_send)(const uint8_t *buf, const size_t size);
-    int (*tpm_recv)(uint8_t *buf, size_t *size);
-  };
-
-The behaviour of "tpm_open()" and "tpm_close()" will basically copy the
-behaviour of "tis_open()" and "tis_close()". The "tpm_send()" will be based on
-the "tis_senddata()" and "tis_recv()" will be based on "tis_readresponse()".
-
-III) Analysis of in-tree drivers
---------------------------------
-
-There is only one in-tree driver present, the "drivers/tpm/generic_lpc_tpm.c",
-which will be simply converted as outlined in previous chapter.
diff --git a/doc/driver-model/UDM-twserial.txt b/doc/driver-model/UDM-twserial.txt
deleted file mode 100644
index 289416acde..0000000000
--- a/doc/driver-model/UDM-twserial.txt
+++ /dev/null
@@ -1,47 +0,0 @@
-==================================
-TWserial device subsystem analysis
-==================================
-
-Tomas Hlavacek<tmshlvck@gmail.com>
-2012-03-21
-
-I) Overview
------------
-
-U-Boot currently implements one common API for TWSerial devices. The interface
-is defined in include/tws.h and comprises of functions:
-
-    int tws_read(uchar *buffer, int len);
-    int tws_write(uchar *buffer, int len);
-
-The functions are implemented by a proper device driver in drivers/twserial
-directory and the driver to be compiled in is selected in a Makefile. There is
-only one driver present now.
-
-The driver depends on ad-hoc code in board specific data, namely functions:
-
-    void tws_ce(unsigned bit);
-    void tws_wr(unsigned bit);
-    void tws_clk(unsigned bit);
-    void tws_data(unsigned bit);
-    unsigned tws_data_read(void);
-    void tws_data_config_output(unsigned output);
-
-implemented in include/configs/inka4x0.h .
-
-II) Approach
-------------
-
-  U-Boot TWserial drivers exports two simple functions and therefore the conversion
-  of the driver and creating a core for it is not needed. It should be consolidated
-  with include/configs/inka4x0.h and taken to the misc/ dir.
-
-
-III) Analysis of in-tree drivers
---------------------------------
-
-  1) drivers/twserial/soft_tws.c
-  ------------------------------
-  The driver is the only TWserial driver. The ad-hoc part in
-  include/configs/inka4x0.h and the core soft_tws driver should be consolidated
-  to one compact driver and moved to misc/ .
diff --git a/doc/driver-model/UDM-usb.txt b/doc/driver-model/UDM-usb.txt
deleted file mode 100644
index 5ce85b5d60..0000000000
--- a/doc/driver-model/UDM-usb.txt
+++ /dev/null
@@ -1,94 +0,0 @@
-The U-Boot Driver Model Project
-===============================
-USB analysis
-============
-Marek Vasut <marek.vasut@gmail.com>
-2012-02-16
-
-I) Overview
------------
-
-  1) The USB Host driver
-  ----------------------
-  There are basically four or five USB host drivers. All such drivers currently
-  provide at least the following fuctions:
-
-    usb_lowlevel_init() ... Do the initialization of the USB controller hardware
-    usb_lowlevel_stop() ... Do the shutdown of the USB controller hardware
-
-    usb_event_poll() ...... Poll interrupt from USB device, often used by KBD
-
-    submit_control_msg() .. Submit message via Control endpoint
-    submit_int_msg() ...... Submit message via Interrupt endpoint
-    submit_bulk_msg() ..... Submit message via Bulk endpoint
-
-
-    This allows for the host driver to be easily abstracted.
-
-  2) The USB hierarchy
-  --------------------
-
-  In the current implementation, the USB Host driver provides operations to
-  communicate via the USB bus. This is realised by providing access to a USB
-  root port to which an USB root hub is attached. The USB bus is scanned and for
-  each newly found device, a struct usb_device is allocated. See common/usb.c
-  and include/usb.h for details.
-
-II) Approach
-------------
-
-  1) The USB Host driver
-  ----------------------
-
-  Converting the host driver will follow the classic driver model consideration.
-  Though, the host driver will have to call a function that registers a root
-  port with the USB core in it's probe() function, let's call this function
-
-    usb_register_root_port(&ops);
-
-  This will allow the USB core to track all available root ports. The ops
-  parameter will contain structure describing operations supported by the root
-  port:
-
-  struct usb_port_ops {
-    void   (*usb_event_poll)();
-    int    (*submit_control_msg)();
-    int    (*submit_int_msg)();
-    int    (*submit_bulk_msg)();
-  }
-
-  2) The USB hierarchy and hub drivers
-  ------------------------------------
-
-  Converting the USB heirarchy should be fairy simple, considering the already
-  dynamic nature of the implementation. The current usb_hub_device structure
-  will have to be converted to a struct instance. Every such instance will
-  contain components of struct usb_device and struct usb_hub_device in it's
-  private data, providing only accessors in order to properly encapsulate the
-  driver.
-
-  By registering the root port, the USB framework will instantiate a USB hub
-  driver, which is always present, the root hub. The root hub and any subsequent
-  hub instance is represented by struct instance and it's private data contain
-  amongst others common bits from struct usb_device.
-
-  Note the USB hub driver is partly defying the usual method of registering a
-  set of callbacks to a particular core driver. Instead, a static set of
-  functions is defined and the USB hub instance is passed to those. This creates
-  certain restrictions as of how the USB hub driver looks, but considering the
-  specification for USB hub is given and a different type of USB hub won't ever
-  exist, this approach is ok:
-
-  - Report how many ports does this hub have:
-      uint get_nr_ports(struct instance *hub);
-  - Get pointer to device connected to a port:
-      struct instance *(*get_child)(struct instance *hub, int port);
-  - Instantiate and configure device on port:
-      struct instance *(*enum_dev_on_port)(struct instance *hub, int port);
-
-  3) USB device drivers
-  ---------------------
-
-  The USB device driver, in turn, will have to register various ops structures
-  with certain cores. For example, USB disc driver will have to register it's
-  ops with core handling USB discs etc.
diff --git a/doc/driver-model/UDM-video.txt b/doc/driver-model/UDM-video.txt
deleted file mode 100644
index 342aeee485..0000000000
--- a/doc/driver-model/UDM-video.txt
+++ /dev/null
@@ -1,74 +0,0 @@
-The U-Boot Driver Model Project
-===============================
-Video output analysis
-=====================
-Marek Vasut <marek.vasut@gmail.com>
-2012-02-20
-
-I) Overview
------------
-
-The video drivers are most often registered with video subsystem. This subsystem
-often expects to be allowed access to framebuffer of certain parameters. This
-subsystem also provides calls for STDIO subsystem to allow it to output
-characters on the screen. For this part, see [ UDM-stdio.txt ].
-
-Therefore the API has two parts, the video driver part and the part where the
-video driver core registers with STDIO API.
-
-The video driver part will follow the current cfb_console approach, though
-allowing it to be more dynamic.
-
-II) Approach
-------------
-
-Registering the video driver into the video driver core is done by calling the
-following function from the driver probe() function:
-
-  video_device_register(struct instance *i, GraphicDevice *gd);
-
-Because the video driver core is in charge or rendering characters as well as
-bitmaps on the screen, it will in turn call stdio_device_register(i, so), where
-"i" is the same instance as the video driver's one. But "so" will be special
-static struct stdio_device_ops handling the character output.
-
-
-III) Analysis of in-tree drivers
---------------------------------
-
-  1) arch/powerpc/cpu/mpc8xx/video.c
-  ----------------------------------
-  This driver copies the cfb_console [ see drivers/video/cfb_console.c ]
-  approach and acts only as a STDIO device. Therefore there are currently two
-  possible approaches, first being the conversion of this driver to usual STDIO
-  device and second, long-term one, being conversion of this driver to video
-  driver that provides console.
-
-  2) arch/x86/lib/video.c
-  -----------------------
-  This driver registers two separate STDIO devices and should be therefore
-  converted as such.
-
-  3) board/bf527-ezkit/video.c
-  ----------------------------
-  This driver seems bogus as it behaves as STDIO device, but provides no input
-  or output capabilities. It relies on DEV_EXT_VIDEO, which is no longer in use
-  or present otherwise than as a dead code/define.
-
-  4) board/bf533-stamp/video.c
-  ----------------------------
-  This driver seems bogus as it behaves as STDIO device, but provides no input
-  or output capabilities. It relies on DEV_EXT_VIDEO, which is no longer in use
-  or present otherwise than as a dead code/define.
-
-  5) board/bf548-ezkit/video.c
-  ----------------------------
-  This driver seems bogus as it behaves as STDIO device, but provides no input
-  or output capabilities. It relies on DEV_EXT_VIDEO, which is no longer in use
-  or present otherwise than as a dead code/define.
-
-  6) board/cm-bf548/video.c
-  ----------------------------
-  This driver seems bogus as it behaves as STDIO device, but provides no input
-  or output capabilities. It relies on DEV_EXT_VIDEO, which is no longer in use
-  or present otherwise than as a dead code/define.
diff --git a/doc/driver-model/UDM-watchdog.txt b/doc/driver-model/UDM-watchdog.txt
deleted file mode 100644
index 7948e59260..0000000000
--- a/doc/driver-model/UDM-watchdog.txt
+++ /dev/null
@@ -1,329 +0,0 @@
-The U-Boot Driver Model Project
-===============================
-Watchdog device subsystem analysis
-==================================
-
-Tomas Hlavacek <tmshlvck@gmail.com>
-2012-03-09
-
-I) Overview
------------
-
-U-Boot currently implements an API for HW watchdog devices as explicit drivers
-in drivers/watchdog directory. There are also drivers for both hardware and
-software watchdog on particular CPUs implemented in arch/*/cpu/*/cpu.c. There
-are macros in include/watchdog.h that selects between SW and HW watchdog and
-assembly SW implementation.
-
-The current common interface comprises of one set out of these two possible
-variants:
-
-    1)
-    void watchdog_reset(void);
-    int watchdog_disable(void);
-    int watchdog_init(void);
-
-    2)
-    void hw_watchdog_reset(void);
-    void hw_watchdog_init(void);
-
-The watchdog implementations are also spread through board/*/*.c that in
-some cases. The API and semantics is in most cases same as the above
-mentioned common functions.
-
-
-II) Approach
-------------
-
-  1) New API
-  ----------
-
-  In the UDM each watchdog driver would register itself by a function
-
-    int watchdog_device_register(struct instance *i,
-				 const struct watchdog_device_ops *o);
-
-  The structure being defined as follows:
-
-    struct watchdog_device_ops {
-	int (*disable)(struct instance *i);
-	void (*reset)(struct instance *i);
-    };
-
-  The watchdog_init() function will be dissolved into probe() function.
-
-  2) Conversion thougths
-  ----------------------
-
-  Conversion of watchdog implementations to a new API could be divided
-  to three subsections: a) HW implementations, which are mostly compliant
-  to the above mentioned API; b) SW implementations, which are compliant
-  to the above mentioned API and c) SW implementations that are not compliant
-  to the API and has to be rectified or partially rewritten.
-
-III) Analysis of in-tree drivers
---------------------------------
-
-  1) drivers/watchdog/at91sam9_wdt.c
-  ----------------------------------
-  The driver is standard HW watchdog. Simple conversion is possible.
-
-
-  2) drivers/watchdog/ftwdt010_wdt.c
-  ----------------------------------
-  The driver is ad-hoc HW watchdog. Conversion has to take into account
-  driver parts spread in include/faraday/*. Restructuring the driver and
-  code cleanup has to be considered.
-
-
-  3) arch/arm/cpu/arm1136/mx31/timer.c
-  ------------------------------------
-  The driver is semi-standard ad-hoc HW watchdog. Conversion has to take
-  into account driver parts spread in the timer.c file.
-
-
-  4) arch/arm/cpu/arm926ejs/davinci/timer.c
-  -----------------------------------------
-  The driver is ad-hoc semi-standard HW watchdog. Conversion has to take
-  into account driver parts spread in the timer.c file.
-
-
-  5) arch/arm/cpu/armv7/omap-common/hwinit-common.c
-  -------------------------------------------------
-  The driver is non-standard ad-hoc HW watchdog. Conversion is possible
-  but functions has to be renamed and constants moved to another places.
-
-
-  6) arch/arm/cpu/armv7/omap3/board.c
-  -----------------------------------
-  The driver is non-standard ad-hoc HW watchdog. Conversion is possible
-  but functions has to be renamed and constants moved to another places.
-
-
-  7) arch/blackfin/cpu/watchdog.c
-  -------------------------------
-  The driver is standard HW watchdog. Simple conversion is possible.
-
-
-  8) arch/m68k/cpu/mcf523x/cpu.c
-  ------------------------------
-  The driver is standard HW watchdog. Simple conversion is possible.
-
-
-  9) arch/m68k/cpu/mcf52x2/cpu.c
-  ------------------------------
-  The driver is standard HW watchdog. Simple conversion is possible.
-
-
-  10) arch/m68k/cpu/mcf532x/cpu.c
-  -------------------------------
-  The driver is standard HW watchdog. Simple conversion is possible.
-
-
-  11) arch/m68k/cpu/mcf547x_8x/cpu.c
-  ----------------------------------
-  The driver is standard HW watchdog (there is slight naming convention
-  violation that has to be rectified). Simple conversion is possible.
-
-
-  12) arch/powerpc/cpu/74xx_7xx/cpu.c
-  -----------------------------------
-  The driver is standard HW watchdog. Simple conversion is possible.
-
-
-  13) arch/powerpc/cpu/mpc512x/cpu.c
-  ----------------------------------
-  The driver is standard HW watchdog. Simple conversion is possible.
-
-
-  14) arch/powerpc/cpu/mpc5xx/cpu.c
-  ---------------------------------
-  The driver is standard HW watchdog. Simple conversion is possible.
-
-
-  15) arch/powerpc/cpu/mpc5xxx/cpu.c
-  ----------------------------------
-  The driver is standard HW watchdog. Simple conversion is possible.
-
-
-  16) arch/powerpc/cpu/mpc8260/cpu.c
-  ----------------------------------
-  The driver is standard HW watchdog. Simple conversion is possible.
-
-
-  17) arch/powerpc/cpu/mpc83xx/cpu.c
-  ----------------------------------
-  The driver is standard HW watchdog. Simple conversion is possible.
-
-
-  18) arch/powerpc/cpu/mpc85xx/cpu.c
-  ----------------------------------
-  The driver is standard HW watchdog. Simple conversion is possible.
-
-
-  19) arch/powerpc/cpu/mpc86xx/cpu.c
-  ----------------------------------
-  The driver is standard HW watchdog. Simple conversion is possible.
-
-
-  20) arch/powerpc/cpu/mpc8xx/cpu.c
-
-  The driver is standard HW watchdog. Simple conversion is possible.
-
-
-  21) arch/powerpc/cpu/ppc4xx/cpu.c
-  ---------------------------------
-  The driver is standard HW watchdog. Simple conversion is possible.
-
-
-  22) arch/sh/cpu/sh2/watchdog.c
-  ------------------------------
-  The driver is standard HW watchdog. Simple conversion is possible.
-
-
-  23) arch/sh/cpu/sh3/watchdog.c
-  ------------------------------
-  The driver is standard HW watchdog. Simple conversion is possible.
-
-
-  24) arch/sh/cpu/sh4/watchdog.c
-  ------------------------------
-  The driver is standard HW watchdog. Simple conversion is possible.
-
-
-  25) board/amcc/luan/luan.c
-  --------------------------
-  The driver is standard HW watchdog. Simple conversion is possible.
-
-
-  26) board/amcc/yosemite/yosemite.c
-  ----------------------------------
-  The driver is standard HW watchdog. Simple conversion is possible.
-
-
-  27) board/apollon/apollon.c
-  ---------------------------
-  The driver is standard HW watchdog however the watchdog_init()
-  function is called in early initialization. Simple conversion is possible.
-
-
-  28) board/bmw/m48t59y.c
-  -----------------------
-  Special watchdog driver. Dead code. To be removed.
-
-
-  29) board/davedenx/qong/qong.c
-  ------------------------------
-  The driver is standard HW watchdog. Simple conversion is possible.
-
-
-  30) board/dvlhost/watchdog.c
-  ----------------------------
-  The driver is standard HW watchdog. Simple conversion is possible.
-
-
-  31) board/eNET/eNET.c
-  ---------------------
-  The driver is standard HW watchdog. Simple conversion is possible.
-
-
-  32) board/eltec/elppc/elppc.c
-  -----------------------------
-  The driver is standard HW watchdog. Simple conversion is possible.
-
-
-  33) board/enbw/enbw_cmc/enbw_cmc.c
-  ----------------------------------
-  Only function proxy call. Code cleanup needed.
-
-
-  34) board/freescale/mx31pdk/mx31pdk.c
-  -------------------------------------
-  Only function proxy call. Code cleanup needed.
-
-
-  35) board/gth2/gth2.c
-  ---------------------
-  The driver is standard HW watchdog. Simple conversion is possible.
-
-
-  36) board/lwmon5/lwmon5.c
-  -------------------------
-  The driver is standard HW watchdog. Simple conversion is possible.
-
-
-  37) board/manroland/mucmc52/mucmc52.c
-  -------------------------------------
-  The driver is standard HW watchdog. Simple conversion is possible.
-
-
-  38) board/manroland/uc101/uc101.c
-  ---------------------------------
-  The driver is standard HW watchdog. Simple conversion is possible.
-
-
-  39) board/mousse/m48t59y.c
-  --------------------------
-  Special watchdog driver. Dead code. To be removed.
-
-
-  40) board/mvblue/mvblue.c
-  -------------------------
-  The driver is standard HW watchdog. Simple conversion is possible.
-
-
-  41) board/netphone/netphone.c
-  -----------------------------
-  The driver is standard HW watchdog. Simple conversion is possible.
-
-
-  42) board/netta/netta.c
-  -----------------------
-  The driver is standard HW watchdog. Simple conversion is possible.
-
-
-  43) board/netta2/netta2.c
-  -------------------------
-  The driver is standard HW watchdog. Simple conversion is possible.
-
-
-  44) board/omicron/calimain/calimain.c
-  -------------------------------------
-  Only function proxy call. Code cleanup needed.
-
-
-  46) board/pcs440ep/pcs440ep.c
-  -----------------------------
-  The driver is standard HW watchdog. Simple conversion is possible.
-
-
-  47) board/stx/stxxtc/stxxtc.c
-  -----------------------------
-  The driver is standard HW watchdog. Simple conversion is possible.
-
-
-  48) board/ti/omap2420h4/omap2420h4.c
-  ------------------------------------
-  The driver is standard HW watchdog. Simple conversion is possible.
-
-
-  49) board/ttcontrol/vision2/vision2.c
-  -------------------------------------
-  The driver is standard HW watchdog but namespace is polluted by
-  non-standard macros. Simple conversion is possible, code cleanup
-  needed.
-
-
-  50) board/v38b/v38b.c
-  ---------------------
-  The driver is standard HW watchdog. Simple conversion is possible.
-
-
-  51) board/ve8313/ve8313.c
-  -------------------------
-  The driver is standard HW watchdog. Simple conversion is possible.
-
-
-  52) board/w7o/watchdog.c
-  ------------------------
-  The driver is standard HW watchdog. Simple conversion is possible.
diff --git a/doc/feature-removal-schedule.txt b/doc/feature-removal-schedule.txt
index 1c79c14a3b..16819c7754 100644
--- a/doc/feature-removal-schedule.txt
+++ b/doc/feature-removal-schedule.txt
@@ -19,22 +19,6 @@ Who:	Tom Rini <trini@ti.com>
 
 ---------------------------
 
-What:	Remove CONFIG_SYS_ENABLE_PADS_ALL and CONFIG_SYS_CLOCKS_ENABLE_ALL
-When:	Release v2013.07
-
-Why:	When set these options enable "all" of the pads and clocks found
-	on OMAP4/5 platforms, so that the Linux Kernel does not have to.
-	It has been agreed that this goes against the U-Boot design
-	philosophy and since f3f98bb0 we have not enabled more than is
-	used in U-Boot.  The kernel has been updating drivers to enable
-	rather than assume pads/clocks have been enabled already.  Our
-	expectation is that by v2013.07 a suitable kernel shall exist that
-	does not need these options set for a reasonable I/O set to function.
-
-Who:	Tom Rini <trini@ti.com> and Sricharan R <r.sricharan@ti.com>
-
----------------------------
-
 What:	Users of the legacy miiphy_* code
 When:	undetermined
 
diff --git a/doc/uImage.FIT/howto.txt b/doc/uImage.FIT/howto.txt
index 59e21e91e3..526be55a57 100644
--- a/doc/uImage.FIT/howto.txt
+++ b/doc/uImage.FIT/howto.txt
@@ -20,8 +20,8 @@ www.jdl.com for its latest version. mkimage (together with dtc) takes as input
 an image source file, which describes the contents of the image and defines
 its various properties used during booting. By convention, image source file
 has the ".its" extension, also, the details of its format are given in
-doc/source_file_format.txt. The actual data that is to be included in the
-uImage (kernel, ramdisk, etc.) is specified in the image source file in the
+doc/uImage.FIT/source_file_format.txt. The actual data that is to be included in
+the uImage (kernel, ramdisk, etc.) is specified in the image source file in the
 form of paths to appropriate data files. The outcome of the image creation
 process is a binary file (by convention with the ".itb" extension) that
 contains all the referenced data (kernel, ramdisk, etc.) and other information
@@ -39,7 +39,7 @@ Here's a graphical overview of the image creation and booting process:
 
 image source file     mkimage + dtc		  transfer to target
 	+	     ---------------> image file --------------------> bootm
-image data files(s)
+image data file(s)
 
 
 Example 1 -- old-style (non-FDT) kernel booting
diff --git a/doc/uImage.FIT/source_file_format.txt b/doc/uImage.FIT/source_file_format.txt
index 160b2d05f8..9ed6f65e59 100644
--- a/doc/uImage.FIT/source_file_format.txt
+++ b/doc/uImage.FIT/source_file_format.txt
@@ -159,7 +159,7 @@ the '/images' node should have the following layout:
   - description : Textual description of the component sub-image
   - type : Name of component sub-image type, supported types are:
     "standalone", "kernel", "ramdisk", "firmware", "script", "filesystem",
-    "fdt".
+    "flat_dt".
   - data : Path to the external file which contains this node's binary data.
   - compression : Compression used by included data. Supported compressions
     are "gzip" and "bzip2". If no compression is used compression property
diff --git a/drivers/Makefile b/drivers/Makefile
new file mode 100644
index 0000000000..5d03f37a18
--- /dev/null
+++ b/drivers/Makefile
@@ -0,0 +1,16 @@
+obj-$(CONFIG_BIOSEMU) += bios_emulator/
+obj-y += block/
+obj-$(CONFIG_BOOTCOUNT_LIMIT) += bootcount/
+obj-y += crypto/
+obj-$(CONFIG_FPGA) += fpga/
+obj-y += hwmon/
+obj-y += misc/
+obj-y += pcmcia/
+obj-y += dfu/
+obj-y += rtc/
+obj-y += sound/
+obj-y += tpm/
+obj-y += twserial/
+obj-y += video/
+obj-y += watchdog/
+obj-$(CONFIG_QE) += qe/
diff --git a/drivers/bios_emulator/Makefile b/drivers/bios_emulator/Makefile
index d94a144292..e56356ee86 100644
--- a/drivers/bios_emulator/Makefile
+++ b/drivers/bios_emulator/Makefile
@@ -1,12 +1,6 @@
-include $(TOPDIR)/config.mk
-
-LIB := $(obj)libatibiosemu.o
-
 X86DIR  = x86emu
 
-$(shell mkdir -p $(obj)$(X86DIR))
-
-COBJS-$(CONFIG_BIOSEMU)	= atibios.o biosemu.o besys.o bios.o \
+obj-y = atibios.o biosemu.o besys.o bios.o \
 	$(X86DIR)/decode.o \
 	$(X86DIR)/ops2.o \
 	$(X86DIR)/ops.o \
@@ -14,26 +8,5 @@ COBJS-$(CONFIG_BIOSEMU)	= atibios.o biosemu.o besys.o bios.o \
 	$(X86DIR)/sys.o \
 	$(X86DIR)/debug.o
 
-COBJS	:= $(COBJS-y)
-SRCS	:= $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-
-EXTRA_CFLAGS += -I. -I./include -I$(TOPDIR)/include \
+ccflags-y := -I$(srctree)/$(src) -I$(srctree)/$(src)/include \
 	-D__PPC__  -D__BIG_ENDIAN__
-
-CFLAGS += $(EXTRA_CFLAGS)
-HOSTCFLAGS += $(EXTRA_CFLAGS)
-CPPFLAGS += $(EXTRA_CFLAGS)
-
-all:	$(LIB)
-
-$(LIB): $(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
diff --git a/drivers/bios_emulator/include/x86emu/prim_asm.h b/drivers/bios_emulator/include/x86emu/prim_asm.h
deleted file mode 100644
index 4cb4cab5d5..0000000000
--- a/drivers/bios_emulator/include/x86emu/prim_asm.h
+++ /dev/null
@@ -1,970 +0,0 @@
-/****************************************************************************
-*
-*                       Realmode X86 Emulator Library
-*
-*               Copyright (C) 1991-2004 SciTech Software, Inc.
-*                    Copyright (C) David Mosberger-Tang
-*                      Copyright (C) 1999 Egbert Eich
-*
-*  ========================================================================
-*
-*  Permission to use, copy, modify, distribute, and sell this software and
-*  its documentation for any purpose is hereby granted without fee,
-*  provided that the above copyright notice appear in all copies and that
-*  both that copyright notice and this permission notice appear in
-*  supporting documentation, and that the name of the authors not be used
-*  in advertising or publicity pertaining to distribution of the software
-*  without specific, written prior permission.  The authors makes no
-*  representations about the suitability of this software for any purpose.
-*  It is provided "as is" without express or implied warranty.
-*
-*  THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
-*  INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO
-*  EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR
-*  CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF
-*  USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR
-*  OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
-*  PERFORMANCE OF THIS SOFTWARE.
-*
-*  ========================================================================
-*
-* Language:     Watcom C++ 10.6 or later
-* Environment:  Any
-* Developer:    Kendall Bennett
-*
-* Description:  Inline assembler versions of the primitive operand
-*               functions for faster performance. At the moment this is
-*               x86 inline assembler, but these functions could be replaced
-*               with native inline assembler for each supported processor
-*               platform.
-*
-****************************************************************************/
-
-#ifndef __X86EMU_PRIM_ASM_H
-#define __X86EMU_PRIM_ASM_H
-
-#ifdef  __WATCOMC__
-
-#ifndef VALIDATE
-#define __HAVE_INLINE_ASSEMBLER__
-#endif
-
-u32 get_flags_asm(void);
-#pragma aux get_flags_asm =         \
-    "pushf"                         \
-    "pop    eax"                    \
-    value [eax]                     \
-    modify exact [eax];
-
-u16 aaa_word_asm(u32 * flags, u16 d);
-#pragma aux aaa_word_asm =          \
-    "push   [edi]"                  \
-    "popf"                          \
-    "aaa"                           \
-    "pushf"                         \
-    "pop    [edi]"                  \
-    parm [edi] [ax]                 \
-    value [ax]                      \
-    modify exact [ax];
-
-u16 aas_word_asm(u32 * flags, u16 d);
-#pragma aux aas_word_asm =          \
-    "push   [edi]"                  \
-    "popf"                          \
-    "aas"                           \
-    "pushf"                         \
-    "pop    [edi]"                  \
-    parm [edi] [ax]                 \
-    value [ax]                      \
-    modify exact [ax];
-
-u16 aad_word_asm(u32 * flags, u16 d);
-#pragma aux aad_word_asm =          \
-    "push   [edi]"                  \
-    "popf"                          \
-    "aad"                           \
-    "pushf"                         \
-    "pop    [edi]"                  \
-    parm [edi] [ax]                 \
-    value [ax]                      \
-    modify exact [ax];
-
-u16 aam_word_asm(u32 * flags, u8 d);
-#pragma aux aam_word_asm =          \
-    "push   [edi]"                  \
-    "popf"                          \
-    "aam"                           \
-    "pushf"                         \
-    "pop    [edi]"                  \
-    parm [edi] [al]                 \
-    value [ax]                      \
-    modify exact [ax];
-
-u8 adc_byte_asm(u32 * flags, u8 d, u8 s);
-#pragma aux adc_byte_asm =          \
-    "push   [edi]"                  \
-    "popf"                          \
-    "adc    al,bl"                  \
-    "pushf"                         \
-    "pop    [edi]"                  \
-    parm [edi] [al] [bl]            \
-    value [al]                      \
-    modify exact [al bl];
-
-u16 adc_word_asm(u32 * flags, u16 d, u16 s);
-#pragma aux adc_word_asm =          \
-    "push   [edi]"                  \
-    "popf"                          \
-    "adc    ax,bx"                  \
-    "pushf"                         \
-    "pop    [edi]"                  \
-    parm [edi] [ax] [bx]            \
-    value [ax]                      \
-    modify exact [ax bx];
-
-u32 adc_long_asm(u32 * flags, u32 d, u32 s);
-#pragma aux adc_long_asm =          \
-    "push   [edi]"                  \
-    "popf"                          \
-    "adc    eax,ebx"                \
-    "pushf"                         \
-    "pop    [edi]"                  \
-    parm [edi] [eax] [ebx]          \
-    value [eax]                     \
-    modify exact [eax ebx];
-
-u8 add_byte_asm(u32 * flags, u8 d, u8 s);
-#pragma aux add_byte_asm =          \
-    "push   [edi]"                  \
-    "popf"                          \
-    "add    al,bl"                  \
-    "pushf"                         \
-    "pop    [edi]"                  \
-    parm [edi] [al] [bl]            \
-    value [al]                      \
-    modify exact [al bl];
-
-u16 add_word_asm(u32 * flags, u16 d, u16 s);
-#pragma aux add_word_asm =          \
-    "push   [edi]"                  \
-    "popf"                          \
-    "add    ax,bx"                  \
-    "pushf"                         \
-    "pop    [edi]"                  \
-    parm [edi] [ax] [bx]            \
-    value [ax]                      \
-    modify exact [ax bx];
-
-u32 add_long_asm(u32 * flags, u32 d, u32 s);
-#pragma aux add_long_asm =          \
-    "push   [edi]"                  \
-    "popf"                          \
-    "add    eax,ebx"                \
-    "pushf"                         \
-    "pop    [edi]"                  \
-    parm [edi] [eax] [ebx]          \
-    value [eax]                     \
-    modify exact [eax ebx];
-
-u8 and_byte_asm(u32 * flags, u8 d, u8 s);
-#pragma aux and_byte_asm =          \
-    "push   [edi]"                  \
-    "popf"                          \
-    "and    al,bl"                  \
-    "pushf"                         \
-    "pop    [edi]"                  \
-    parm [edi] [al] [bl]            \
-    value [al]                      \
-    modify exact [al bl];
-
-u16 and_word_asm(u32 * flags, u16 d, u16 s);
-#pragma aux and_word_asm =          \
-    "push   [edi]"                  \
-    "popf"                          \
-    "and    ax,bx"                  \
-    "pushf"                         \
-    "pop    [edi]"                  \
-    parm [edi] [ax] [bx]            \
-    value [ax]                      \
-    modify exact [ax bx];
-
-u32 and_long_asm(u32 * flags, u32 d, u32 s);
-#pragma aux and_long_asm =          \
-    "push   [edi]"                  \
-    "popf"                          \
-    "and    eax,ebx"                \
-    "pushf"                         \
-    "pop    [edi]"                  \
-    parm [edi] [eax] [ebx]          \
-    value [eax]                     \
-    modify exact [eax ebx];
-
-u8 cmp_byte_asm(u32 * flags, u8 d, u8 s);
-#pragma aux cmp_byte_asm =          \
-    "push   [edi]"                  \
-    "popf"                          \
-    "cmp    al,bl"                  \
-    "pushf"                         \
-    "pop    [edi]"                  \
-    parm [edi] [al] [bl]            \
-    value [al]                      \
-    modify exact [al bl];
-
-u16 cmp_word_asm(u32 * flags, u16 d, u16 s);
-#pragma aux cmp_word_asm =          \
-    "push   [edi]"                  \
-    "popf"                          \
-    "cmp    ax,bx"                  \
-    "pushf"                         \
-    "pop    [edi]"                  \
-    parm [edi] [ax] [bx]            \
-    value [ax]                      \
-    modify exact [ax bx];
-
-u32 cmp_long_asm(u32 * flags, u32 d, u32 s);
-#pragma aux cmp_long_asm =          \
-    "push   [edi]"                  \
-    "popf"                          \
-    "cmp    eax,ebx"                \
-    "pushf"                         \
-    "pop    [edi]"                  \
-    parm [edi] [eax] [ebx]          \
-    value [eax]                     \
-    modify exact [eax ebx];
-
-u8 daa_byte_asm(u32 * flags, u8 d);
-#pragma aux daa_byte_asm =          \
-    "push   [edi]"                  \
-    "popf"                          \
-    "daa"                           \
-    "pushf"                         \
-    "pop    [edi]"                  \
-    parm [edi] [al]                 \
-    value [al]                      \
-    modify exact [al];
-
-u8 das_byte_asm(u32 * flags, u8 d);
-#pragma aux das_byte_asm =          \
-    "push   [edi]"                  \
-    "popf"                          \
-    "das"                           \
-    "pushf"                         \
-    "pop    [edi]"                  \
-    parm [edi] [al]                 \
-    value [al]                      \
-    modify exact [al];
-
-u8 dec_byte_asm(u32 * flags, u8 d);
-#pragma aux dec_byte_asm =          \
-    "push   [edi]"                  \
-    "popf"                          \
-    "dec    al"                     \
-    "pushf"                         \
-    "pop    [edi]"                  \
-    parm [edi] [al]                 \
-    value [al]                      \
-    modify exact [al];
-
-u16 dec_word_asm(u32 * flags, u16 d);
-#pragma aux dec_word_asm =          \
-    "push   [edi]"                  \
-    "popf"                          \
-    "dec    ax"                     \
-    "pushf"                         \
-    "pop    [edi]"                  \
-    parm [edi] [ax]                 \
-    value [ax]                      \
-    modify exact [ax];
-
-u32 dec_long_asm(u32 * flags, u32 d);
-#pragma aux dec_long_asm =          \
-    "push   [edi]"                  \
-    "popf"                          \
-    "dec    eax"                    \
-    "pushf"                         \
-    "pop    [edi]"                  \
-    parm [edi] [eax]                \
-    value [eax]                     \
-    modify exact [eax];
-
-u8 inc_byte_asm(u32 * flags, u8 d);
-#pragma aux inc_byte_asm =          \
-    "push   [edi]"                  \
-    "popf"                          \
-    "inc    al"                     \
-    "pushf"                         \
-    "pop    [edi]"                  \
-    parm [edi] [al]                 \
-    value [al]                      \
-    modify exact [al];
-
-u16 inc_word_asm(u32 * flags, u16 d);
-#pragma aux inc_word_asm =          \
-    "push   [edi]"                  \
-    "popf"                          \
-    "inc    ax"                     \
-    "pushf"                         \
-    "pop    [edi]"                  \
-    parm [edi] [ax]                 \
-    value [ax]                      \
-    modify exact [ax];
-
-u32 inc_long_asm(u32 * flags, u32 d);
-#pragma aux inc_long_asm =          \
-    "push   [edi]"                  \
-    "popf"                          \
-    "inc    eax"                    \
-    "pushf"                         \
-    "pop    [edi]"                  \
-    parm [edi] [eax]                \
-    value [eax]                     \
-    modify exact [eax];
-
-u8 or_byte_asm(u32 * flags, u8 d, u8 s);
-#pragma aux or_byte_asm =           \
-    "push   [edi]"                  \
-    "popf"                          \
-    "or al,bl"                      \
-    "pushf"                         \
-    "pop    [edi]"                  \
-    parm [edi] [al] [bl]            \
-    value [al]                      \
-    modify exact [al bl];
-
-u16 or_word_asm(u32 * flags, u16 d, u16 s);
-#pragma aux or_word_asm =           \
-    "push   [edi]"                  \
-    "popf"                          \
-    "or ax,bx"                      \
-    "pushf"                         \
-    "pop    [edi]"                  \
-    parm [edi] [ax] [bx]            \
-    value [ax]                      \
-    modify exact [ax bx];
-
-u32 or_long_asm(u32 * flags, u32 d, u32 s);
-#pragma aux or_long_asm =           \
-    "push   [edi]"                  \
-    "popf"                          \
-    "or eax,ebx"                    \
-    "pushf"                         \
-    "pop    [edi]"                  \
-    parm [edi] [eax] [ebx]          \
-    value [eax]                     \
-    modify exact [eax ebx];
-
-u8 neg_byte_asm(u32 * flags, u8 d);
-#pragma aux neg_byte_asm =          \
-    "push   [edi]"                  \
-    "popf"                          \
-    "neg    al"                     \
-    "pushf"                         \
-    "pop    [edi]"                  \
-    parm [edi] [al]                 \
-    value [al]                      \
-    modify exact [al];
-
-u16 neg_word_asm(u32 * flags, u16 d);
-#pragma aux neg_word_asm =          \
-    "push   [edi]"                  \
-    "popf"                          \
-    "neg    ax"                     \
-    "pushf"                         \
-    "pop    [edi]"                  \
-    parm [edi] [ax]                 \
-    value [ax]                      \
-    modify exact [ax];
-
-u32 neg_long_asm(u32 * flags, u32 d);
-#pragma aux neg_long_asm =          \
-    "push   [edi]"                  \
-    "popf"                          \
-    "neg    eax"                    \
-    "pushf"                         \
-    "pop    [edi]"                  \
-    parm [edi] [eax]                \
-    value [eax]                     \
-    modify exact [eax];
-
-u8 not_byte_asm(u32 * flags, u8 d);
-#pragma aux not_byte_asm =          \
-    "push   [edi]"                  \
-    "popf"                          \
-    "not    al"                     \
-    "pushf"                         \
-    "pop    [edi]"                  \
-    parm [edi] [al]                 \
-    value [al]                      \
-    modify exact [al];
-
-u16 not_word_asm(u32 * flags, u16 d);
-#pragma aux not_word_asm =          \
-    "push   [edi]"                  \
-    "popf"                          \
-    "not    ax"                     \
-    "pushf"                         \
-    "pop    [edi]"                  \
-    parm [edi] [ax]                 \
-    value [ax]                      \
-    modify exact [ax];
-
-u32 not_long_asm(u32 * flags, u32 d);
-#pragma aux not_long_asm =          \
-    "push   [edi]"                  \
-    "popf"                          \
-    "not    eax"                    \
-    "pushf"                         \
-    "pop    [edi]"                  \
-    parm [edi] [eax]                \
-    value [eax]                     \
-    modify exact [eax];
-
-u8 rcl_byte_asm(u32 * flags, u8 d, u8 s);
-#pragma aux rcl_byte_asm =          \
-    "push   [edi]"                  \
-    "popf"                          \
-    "rcl    al,cl"                  \
-    "pushf"                         \
-    "pop    [edi]"                  \
-    parm [edi] [al] [cl]            \
-    value [al]                      \
-    modify exact [al cl];
-
-u16 rcl_word_asm(u32 * flags, u16 d, u8 s);
-#pragma aux rcl_word_asm =          \
-    "push   [edi]"                  \
-    "popf"                          \
-    "rcl    ax,cl"                  \
-    "pushf"                         \
-    "pop    [edi]"                  \
-    parm [edi] [ax] [cl]            \
-    value [ax]                      \
-    modify exact [ax cl];
-
-u32 rcl_long_asm(u32 * flags, u32 d, u8 s);
-#pragma aux rcl_long_asm =          \
-    "push   [edi]"                  \
-    "popf"                          \
-    "rcl    eax,cl"                 \
-    "pushf"                         \
-    "pop    [edi]"                  \
-    parm [edi] [eax] [cl]           \
-    value [eax]                     \
-    modify exact [eax cl];
-
-u8 rcr_byte_asm(u32 * flags, u8 d, u8 s);
-#pragma aux rcr_byte_asm =          \
-    "push   [edi]"                  \
-    "popf"                          \
-    "rcr    al,cl"                  \
-    "pushf"                         \
-    "pop    [edi]"                  \
-    parm [edi] [al] [cl]            \
-    value [al]                      \
-    modify exact [al cl];
-
-u16 rcr_word_asm(u32 * flags, u16 d, u8 s);
-#pragma aux rcr_word_asm =          \
-    "push   [edi]"                  \
-    "popf"                          \
-    "rcr    ax,cl"                  \
-    "pushf"                         \
-    "pop    [edi]"                  \
-    parm [edi] [ax] [cl]            \
-    value [ax]                      \
-    modify exact [ax cl];
-
-u32 rcr_long_asm(u32 * flags, u32 d, u8 s);
-#pragma aux rcr_long_asm =          \
-    "push   [edi]"                  \
-    "popf"                          \
-    "rcr    eax,cl"                 \
-    "pushf"                         \
-    "pop    [edi]"                  \
-    parm [edi] [eax] [cl]           \
-    value [eax]                     \
-    modify exact [eax cl];
-
-u8 rol_byte_asm(u32 * flags, u8 d, u8 s);
-#pragma aux rol_byte_asm =          \
-    "push   [edi]"                  \
-    "popf"                          \
-    "rol    al,cl"                  \
-    "pushf"                         \
-    "pop    [edi]"                  \
-    parm [edi] [al] [cl]            \
-    value [al]                      \
-    modify exact [al cl];
-
-u16 rol_word_asm(u32 * flags, u16 d, u8 s);
-#pragma aux rol_word_asm =          \
-    "push   [edi]"                  \
-    "popf"                          \
-    "rol    ax,cl"                  \
-    "pushf"                         \
-    "pop    [edi]"                  \
-    parm [edi] [ax] [cl]            \
-    value [ax]                      \
-    modify exact [ax cl];
-
-u32 rol_long_asm(u32 * flags, u32 d, u8 s);
-#pragma aux rol_long_asm =          \
-    "push   [edi]"                  \
-    "popf"                          \
-    "rol    eax,cl"                 \
-    "pushf"                         \
-    "pop    [edi]"                  \
-    parm [edi] [eax] [cl]           \
-    value [eax]                     \
-    modify exact [eax cl];
-
-u8 ror_byte_asm(u32 * flags, u8 d, u8 s);
-#pragma aux ror_byte_asm =          \
-    "push   [edi]"                  \
-    "popf"                          \
-    "ror    al,cl"                  \
-    "pushf"                         \
-    "pop    [edi]"                  \
-    parm [edi] [al] [cl]            \
-    value [al]                      \
-    modify exact [al cl];
-
-u16 ror_word_asm(u32 * flags, u16 d, u8 s);
-#pragma aux ror_word_asm =          \
-    "push   [edi]"                  \
-    "popf"                          \
-    "ror    ax,cl"                  \
-    "pushf"                         \
-    "pop    [edi]"                  \
-    parm [edi] [ax] [cl]            \
-    value [ax]                      \
-    modify exact [ax cl];
-
-u32 ror_long_asm(u32 * flags, u32 d, u8 s);
-#pragma aux ror_long_asm =          \
-    "push   [edi]"                  \
-    "popf"                          \
-    "ror    eax,cl"                 \
-    "pushf"                         \
-    "pop    [edi]"                  \
-    parm [edi] [eax] [cl]           \
-    value [eax]                     \
-    modify exact [eax cl];
-
-u8 shl_byte_asm(u32 * flags, u8 d, u8 s);
-#pragma aux shl_byte_asm =          \
-    "push   [edi]"                  \
-    "popf"                          \
-    "shl    al,cl"                  \
-    "pushf"                         \
-    "pop    [edi]"                  \
-    parm [edi] [al] [cl]            \
-    value [al]                      \
-    modify exact [al cl];
-
-u16 shl_word_asm(u32 * flags, u16 d, u8 s);
-#pragma aux shl_word_asm =          \
-    "push   [edi]"                  \
-    "popf"                          \
-    "shl    ax,cl"                  \
-    "pushf"                         \
-    "pop    [edi]"                  \
-    parm [edi] [ax] [cl]            \
-    value [ax]                      \
-    modify exact [ax cl];
-
-u32 shl_long_asm(u32 * flags, u32 d, u8 s);
-#pragma aux shl_long_asm =          \
-    "push   [edi]"                  \
-    "popf"                          \
-    "shl    eax,cl"                 \
-    "pushf"                         \
-    "pop    [edi]"                  \
-    parm [edi] [eax] [cl]           \
-    value [eax]                     \
-    modify exact [eax cl];
-
-u8 shr_byte_asm(u32 * flags, u8 d, u8 s);
-#pragma aux shr_byte_asm =          \
-    "push   [edi]"                  \
-    "popf"                          \
-    "shr    al,cl"                  \
-    "pushf"                         \
-    "pop    [edi]"                  \
-    parm [edi] [al] [cl]            \
-    value [al]                      \
-    modify exact [al cl];
-
-u16 shr_word_asm(u32 * flags, u16 d, u8 s);
-#pragma aux shr_word_asm =          \
-    "push   [edi]"                  \
-    "popf"                          \
-    "shr    ax,cl"                  \
-    "pushf"                         \
-    "pop    [edi]"                  \
-    parm [edi] [ax] [cl]            \
-    value [ax]                      \
-    modify exact [ax cl];
-
-u32 shr_long_asm(u32 * flags, u32 d, u8 s);
-#pragma aux shr_long_asm =          \
-    "push   [edi]"                  \
-    "popf"                          \
-    "shr    eax,cl"                 \
-    "pushf"                         \
-    "pop    [edi]"                  \
-    parm [edi] [eax] [cl]           \
-    value [eax]                     \
-    modify exact [eax cl];
-
-u8 sar_byte_asm(u32 * flags, u8 d, u8 s);
-#pragma aux sar_byte_asm =          \
-    "push   [edi]"                  \
-    "popf"                          \
-    "sar    al,cl"                  \
-    "pushf"                         \
-    "pop    [edi]"                  \
-    parm [edi] [al] [cl]            \
-    value [al]                      \
-    modify exact [al cl];
-
-u16 sar_word_asm(u32 * flags, u16 d, u8 s);
-#pragma aux sar_word_asm =          \
-    "push   [edi]"                  \
-    "popf"                          \
-    "sar    ax,cl"                  \
-    "pushf"                         \
-    "pop    [edi]"                  \
-    parm [edi] [ax] [cl]            \
-    value [ax]                      \
-    modify exact [ax cl];
-
-u32 sar_long_asm(u32 * flags, u32 d, u8 s);
-#pragma aux sar_long_asm =          \
-    "push   [edi]"                  \
-    "popf"                          \
-    "sar    eax,cl"                 \
-    "pushf"                         \
-    "pop    [edi]"                  \
-    parm [edi] [eax] [cl]           \
-    value [eax]                     \
-    modify exact [eax cl];
-
-u16 shld_word_asm(u32 * flags, u16 d, u16 fill, u8 s);
-#pragma aux shld_word_asm =         \
-    "push   [edi]"                  \
-    "popf"                          \
-    "shld   ax,dx,cl"               \
-    "pushf"                         \
-    "pop    [edi]"                  \
-    parm [edi] [ax] [dx] [cl]       \
-    value [ax]                      \
-    modify exact [ax dx cl];
-
-u32 shld_long_asm(u32 * flags, u32 d, u32 fill, u8 s);
-#pragma aux shld_long_asm =         \
-    "push   [edi]"                  \
-    "popf"                          \
-    "shld   eax,edx,cl"             \
-    "pushf"                         \
-    "pop    [edi]"                  \
-    parm [edi] [eax] [edx] [cl]     \
-    value [eax]                     \
-    modify exact [eax edx cl];
-
-u16 shrd_word_asm(u32 * flags, u16 d, u16 fill, u8 s);
-#pragma aux shrd_word_asm =         \
-    "push   [edi]"                  \
-    "popf"                          \
-    "shrd   ax,dx,cl"               \
-    "pushf"                         \
-    "pop    [edi]"                  \
-    parm [edi] [ax] [dx] [cl]       \
-    value [ax]                      \
-    modify exact [ax dx cl];
-
-u32 shrd_long_asm(u32 * flags, u32 d, u32 fill, u8 s);
-#pragma aux shrd_long_asm =         \
-    "push   [edi]"                  \
-    "popf"                          \
-    "shrd   eax,edx,cl"             \
-    "pushf"                         \
-    "pop    [edi]"                  \
-    parm [edi] [eax] [edx] [cl]     \
-    value [eax]                     \
-    modify exact [eax edx cl];
-
-u8 sbb_byte_asm(u32 * flags, u8 d, u8 s);
-#pragma aux sbb_byte_asm =          \
-    "push   [edi]"                  \
-    "popf"                          \
-    "sbb    al,bl"                  \
-    "pushf"                         \
-    "pop    [edi]"                  \
-    parm [edi] [al] [bl]            \
-    value [al]                      \
-    modify exact [al bl];
-
-u16 sbb_word_asm(u32 * flags, u16 d, u16 s);
-#pragma aux sbb_word_asm =          \
-    "push   [edi]"                  \
-    "popf"                          \
-    "sbb    ax,bx"                  \
-    "pushf"                         \
-    "pop    [edi]"                  \
-    parm [edi] [ax] [bx]            \
-    value [ax]                      \
-    modify exact [ax bx];
-
-u32 sbb_long_asm(u32 * flags, u32 d, u32 s);
-#pragma aux sbb_long_asm =          \
-    "push   [edi]"                  \
-    "popf"                          \
-    "sbb    eax,ebx"                \
-    "pushf"                         \
-    "pop    [edi]"                  \
-    parm [edi] [eax] [ebx]          \
-    value [eax]                     \
-    modify exact [eax ebx];
-
-u8 sub_byte_asm(u32 * flags, u8 d, u8 s);
-#pragma aux sub_byte_asm =          \
-    "push   [edi]"                  \
-    "popf"                          \
-    "sub    al,bl"                  \
-    "pushf"                         \
-    "pop    [edi]"                  \
-    parm [edi] [al] [bl]            \
-    value [al]                      \
-    modify exact [al bl];
-
-u16 sub_word_asm(u32 * flags, u16 d, u16 s);
-#pragma aux sub_word_asm =          \
-    "push   [edi]"                  \
-    "popf"                          \
-    "sub    ax,bx"                  \
-    "pushf"                         \
-    "pop    [edi]"                  \
-    parm [edi] [ax] [bx]            \
-    value [ax]                      \
-    modify exact [ax bx];
-
-u32 sub_long_asm(u32 * flags, u32 d, u32 s);
-#pragma aux sub_long_asm =          \
-    "push   [edi]"                  \
-    "popf"                          \
-    "sub    eax,ebx"                \
-    "pushf"                         \
-    "pop    [edi]"                  \
-    parm [edi] [eax] [ebx]          \
-    value [eax]                     \
-    modify exact [eax ebx];
-
-void test_byte_asm(u32 * flags, u8 d, u8 s);
-#pragma aux test_byte_asm =         \
-    "push   [edi]"                  \
-    "popf"                          \
-    "test   al,bl"                  \
-    "pushf"                         \
-    "pop    [edi]"                  \
-    parm [edi] [al] [bl]            \
-    modify exact [al bl];
-
-void test_word_asm(u32 * flags, u16 d, u16 s);
-#pragma aux test_word_asm =         \
-    "push   [edi]"                  \
-    "popf"                          \
-    "test   ax,bx"                  \
-    "pushf"                         \
-    "pop    [edi]"                  \
-    parm [edi] [ax] [bx]            \
-    modify exact [ax bx];
-
-void test_long_asm(u32 * flags, u32 d, u32 s);
-#pragma aux test_long_asm =         \
-    "push   [edi]"                  \
-    "popf"                          \
-    "test   eax,ebx"                \
-    "pushf"                         \
-    "pop    [edi]"                  \
-    parm [edi] [eax] [ebx]          \
-    modify exact [eax ebx];
-
-u8 xor_byte_asm(u32 * flags, u8 d, u8 s);
-#pragma aux xor_byte_asm =          \
-    "push   [edi]"                  \
-    "popf"                          \
-    "xor    al,bl"                  \
-    "pushf"                         \
-    "pop    [edi]"                  \
-    parm [edi] [al] [bl]            \
-    value [al]                      \
-    modify exact [al bl];
-
-u16 xor_word_asm(u32 * flags, u16 d, u16 s);
-#pragma aux xor_word_asm =          \
-    "push   [edi]"                  \
-    "popf"                          \
-    "xor    ax,bx"                  \
-    "pushf"                         \
-    "pop    [edi]"                  \
-    parm [edi] [ax] [bx]            \
-    value [ax]                      \
-    modify exact [ax bx];
-
-u32 xor_long_asm(u32 * flags, u32 d, u32 s);
-#pragma aux xor_long_asm =          \
-    "push   [edi]"                  \
-    "popf"                          \
-    "xor    eax,ebx"                \
-    "pushf"                         \
-    "pop    [edi]"                  \
-    parm [edi] [eax] [ebx]          \
-    value [eax]                     \
-    modify exact [eax ebx];
-
-void imul_byte_asm(u32 * flags, u16 * ax, u8 d, u8 s);
-#pragma aux imul_byte_asm =         \
-    "push   [edi]"                  \
-    "popf"                          \
-    "imul   bl"                     \
-    "pushf"                         \
-    "pop    [edi]"                  \
-    "mov    [esi],ax"               \
-    parm [edi] [esi] [al] [bl]      \
-    modify exact [esi ax bl];
-
-void imul_word_asm(u32 * flags, u16 * ax, u16 * dx, u16 d, u16 s);
-#pragma aux imul_word_asm =         \
-    "push   [edi]"                  \
-    "popf"                          \
-    "imul   bx"                     \
-    "pushf"                         \
-    "pop    [edi]"                  \
-    "mov    [esi],ax"               \
-    "mov    [ecx],dx"               \
-    parm [edi] [esi] [ecx] [ax] [bx]\
-    modify exact [esi edi ax bx dx];
-
-void imul_long_asm(u32 * flags, u32 * eax, u32 * edx, u32 d, u32 s);
-#pragma aux imul_long_asm =         \
-    "push   [edi]"                  \
-    "popf"                          \
-    "imul   ebx"                    \
-    "pushf"                         \
-    "pop    [edi]"                  \
-    "mov    [esi],eax"              \
-    "mov    [ecx],edx"              \
-    parm [edi] [esi] [ecx] [eax] [ebx] \
-    modify exact [esi edi eax ebx edx];
-
-void mul_byte_asm(u32 * flags, u16 * ax, u8 d, u8 s);
-#pragma aux mul_byte_asm =          \
-    "push   [edi]"                  \
-    "popf"                          \
-    "mul    bl"                     \
-    "pushf"                         \
-    "pop    [edi]"                  \
-    "mov    [esi],ax"               \
-    parm [edi] [esi] [al] [bl]      \
-    modify exact [esi ax bl];
-
-void mul_word_asm(u32 * flags, u16 * ax, u16 * dx, u16 d, u16 s);
-#pragma aux mul_word_asm =          \
-    "push   [edi]"                  \
-    "popf"                          \
-    "mul    bx"                     \
-    "pushf"                         \
-    "pop    [edi]"                  \
-    "mov    [esi],ax"               \
-    "mov    [ecx],dx"               \
-    parm [edi] [esi] [ecx] [ax] [bx]\
-    modify exact [esi edi ax bx dx];
-
-void mul_long_asm(u32 * flags, u32 * eax, u32 * edx, u32 d, u32 s);
-#pragma aux mul_long_asm =          \
-    "push   [edi]"                  \
-    "popf"                          \
-    "mul    ebx"                    \
-    "pushf"                         \
-    "pop    [edi]"                  \
-    "mov    [esi],eax"              \
-    "mov    [ecx],edx"              \
-    parm [edi] [esi] [ecx] [eax] [ebx] \
-    modify exact [esi edi eax ebx edx];
-
-void idiv_byte_asm(u32 * flags, u8 * al, u8 * ah, u16 d, u8 s);
-#pragma aux idiv_byte_asm =         \
-    "push   [edi]"                  \
-    "popf"                          \
-    "idiv   bl"                     \
-    "pushf"                         \
-    "pop    [edi]"                  \
-    "mov    [esi],al"               \
-    "mov    [ecx],ah"               \
-    parm [edi] [esi] [ecx] [ax] [bl]\
-    modify exact [esi edi ax bl];
-
-void idiv_word_asm(u32 * flags, u16 * ax, u16 * dx, u16 dlo, u16 dhi, u16 s);
-#pragma aux idiv_word_asm =         \
-    "push   [edi]"                  \
-    "popf"                          \
-    "idiv   bx"                     \
-    "pushf"                         \
-    "pop    [edi]"                  \
-    "mov    [esi],ax"               \
-    "mov    [ecx],dx"               \
-    parm [edi] [esi] [ecx] [ax] [dx] [bx]\
-    modify exact [esi edi ax dx bx];
-
-void idiv_long_asm(u32 * flags, u32 * eax, u32 * edx, u32 dlo, u32 dhi, u32 s);
-#pragma aux idiv_long_asm =         \
-    "push   [edi]"                  \
-    "popf"                          \
-    "idiv   ebx"                    \
-    "pushf"                         \
-    "pop    [edi]"                  \
-    "mov    [esi],eax"              \
-    "mov    [ecx],edx"              \
-    parm [edi] [esi] [ecx] [eax] [edx] [ebx]\
-    modify exact [esi edi eax edx ebx];
-
-void div_byte_asm(u32 * flags, u8 * al, u8 * ah, u16 d, u8 s);
-#pragma aux div_byte_asm =          \
-    "push   [edi]"                  \
-    "popf"                          \
-    "div    bl"                     \
-    "pushf"                         \
-    "pop    [edi]"                  \
-    "mov    [esi],al"               \
-    "mov    [ecx],ah"               \
-    parm [edi] [esi] [ecx] [ax] [bl]\
-    modify exact [esi edi ax bl];
-
-void div_word_asm(u32 * flags, u16 * ax, u16 * dx, u16 dlo, u16 dhi, u16 s);
-#pragma aux div_word_asm =          \
-    "push   [edi]"                  \
-    "popf"                          \
-    "div    bx"                     \
-    "pushf"                         \
-    "pop    [edi]"                  \
-    "mov    [esi],ax"               \
-    "mov    [ecx],dx"               \
-    parm [edi] [esi] [ecx] [ax] [dx] [bx]\
-    modify exact [esi edi ax dx bx];
-
-void div_long_asm(u32 * flags, u32 * eax, u32 * edx, u32 dlo, u32 dhi, u32 s);
-#pragma aux div_long_asm =          \
-    "push   [edi]"                  \
-    "popf"                          \
-    "div    ebx"                    \
-    "pushf"                         \
-    "pop    [edi]"                  \
-    "mov    [esi],eax"              \
-    "mov    [ecx],edx"              \
-    parm [edi] [esi] [ecx] [eax] [edx] [ebx]\
-    modify exact [esi edi eax edx ebx];
-
-#endif
-
-#endif				/* __X86EMU_PRIM_ASM_H */
diff --git a/drivers/block/Makefile b/drivers/block/Makefile
index 2016e98440..8697da4262 100644
--- a/drivers/block/Makefile
+++ b/drivers/block/Makefile
@@ -5,40 +5,19 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	:= $(obj)libblock.o
-
-COBJS-$(CONFIG_SCSI_AHCI) += ahci.o
-COBJS-$(CONFIG_ATA_PIIX) += ata_piix.o
-COBJS-$(CONFIG_DWC_AHSATA) += dwc_ahsata.o
-COBJS-$(CONFIG_FSL_SATA) += fsl_sata.o
-COBJS-$(CONFIG_IDE_FTIDE020) += ftide020.o
-COBJS-$(CONFIG_LIBATA) += libata.o
-COBJS-$(CONFIG_MVSATA_IDE) += mvsata_ide.o
-COBJS-$(CONFIG_MX51_PATA) += mxc_ata.o
-COBJS-$(CONFIG_PATA_BFIN) += pata_bfin.o
-COBJS-$(CONFIG_SATA_DWC) += sata_dwc.o
-COBJS-$(CONFIG_SATA_SIL3114) += sata_sil3114.o
-COBJS-$(CONFIG_SATA_SIL) += sata_sil.o
-COBJS-$(CONFIG_IDE_SIL680) += sil680.o
-COBJS-$(CONFIG_SCSI_SYM53C8XX) += sym53c8xx.o
-COBJS-$(CONFIG_SYSTEMACE) += systemace.o
-
-COBJS	:= $(COBJS-y)
-SRCS	:= $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-
-all:	$(LIB)
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-$(CONFIG_SCSI_AHCI) += ahci.o
+obj-$(CONFIG_ATA_PIIX) += ata_piix.o
+obj-$(CONFIG_DWC_AHSATA) += dwc_ahsata.o
+obj-$(CONFIG_FSL_SATA) += fsl_sata.o
+obj-$(CONFIG_IDE_FTIDE020) += ftide020.o
+obj-$(CONFIG_LIBATA) += libata.o
+obj-$(CONFIG_MVSATA_IDE) += mvsata_ide.o
+obj-$(CONFIG_MX51_PATA) += mxc_ata.o
+obj-$(CONFIG_PATA_BFIN) += pata_bfin.o
+obj-$(CONFIG_SATA_DWC) += sata_dwc.o
+obj-$(CONFIG_SATA_SIL3114) += sata_sil3114.o
+obj-$(CONFIG_SATA_SIL) += sata_sil.o
+obj-$(CONFIG_IDE_SIL680) += sil680.o
+obj-$(CONFIG_SANDBOX) += sandbox.o
+obj-$(CONFIG_SCSI_SYM53C8XX) += sym53c8xx.o
+obj-$(CONFIG_SYSTEMACE) += systemace.o
diff --git a/drivers/block/ahci.c b/drivers/block/ahci.c
index 0daad364d7..c8f65739e9 100644
--- a/drivers/block/ahci.c
+++ b/drivers/block/ahci.c
@@ -41,7 +41,7 @@ u16 *ataid[AHCI_MAX_PORTS];
 #define WAIT_MS_SPINUP	20000
 #define WAIT_MS_DATAIO	5000
 #define WAIT_MS_FLUSH	5000
-#define WAIT_MS_LINKUP	4
+#define WAIT_MS_LINKUP	40
 
 static inline u32 ahci_port_base(u32 base, u32 port)
 {
@@ -379,6 +379,11 @@ static int ahci_init_one(pci_dev_t pdev)
 	int rc;
 
 	probe_ent = malloc(sizeof(struct ahci_probe_ent));
+	if (!probe_ent) {
+		printf("%s: No memory for probe_ent\n", __func__);
+		return -ENOMEM;
+	}
+
 	memset(probe_ent, 0, sizeof(struct ahci_probe_ent));
 	probe_ent->dev = pdev;
 
@@ -503,7 +508,7 @@ static int ahci_port_start(u8 port)
 	mem = (u32) malloc(AHCI_PORT_PRIV_DMA_SZ + 2048);
 	if (!mem) {
 		free(pp);
-		printf("No mem for table!\n");
+		printf("%s: No mem for table!\n", __func__);
 		return -ENOMEM;
 	}
 
@@ -618,7 +623,8 @@ static int ata_scsiop_inquiry(ccb *pccb)
 		95 - 4,
 	};
 	u8 fis[20];
-	u16 *tmpid;
+	u16 *idbuf;
+	ALLOC_CACHE_ALIGN_BUFFER(u16, tmpid, ATA_ID_WORDS);
 	u8 port;
 
 	/* Clean ccb data buffer */
@@ -637,28 +643,32 @@ static int ata_scsiop_inquiry(ccb *pccb)
 
 	/* Read id from sata */
 	port = pccb->target;
-	tmpid = malloc(ATA_ID_WORDS * 2);
-	if (!tmpid)
-		return -ENOMEM;
 
 	if (ahci_device_data_io(port, (u8 *) &fis, sizeof(fis), (u8 *)tmpid,
 				ATA_ID_WORDS * 2, 0)) {
 		debug("scsi_ahci: SCSI inquiry command failure.\n");
-		free(tmpid);
 		return -EIO;
 	}
 
-	if (ataid[port])
-		free(ataid[port]);
-	ataid[port] = tmpid;
-	ata_swap_buf_le16(tmpid, ATA_ID_WORDS);
+	if (!ataid[port]) {
+		ataid[port] = malloc(ATA_ID_WORDS * 2);
+		if (!ataid[port]) {
+			printf("%s: No memory for ataid[port]\n", __func__);
+			return -ENOMEM;
+		}
+	}
+
+	idbuf = ataid[port];
+
+	memcpy(idbuf, tmpid, ATA_ID_WORDS * 2);
+	ata_swap_buf_le16(idbuf, ATA_ID_WORDS);
 
 	memcpy(&pccb->pdata[8], "ATA     ", 8);
-	ata_id_strcpy((u16 *) &pccb->pdata[16], &tmpid[ATA_ID_PROD], 16);
-	ata_id_strcpy((u16 *) &pccb->pdata[32], &tmpid[ATA_ID_FW_REV], 4);
+	ata_id_strcpy((u16 *)&pccb->pdata[16], &idbuf[ATA_ID_PROD], 16);
+	ata_id_strcpy((u16 *)&pccb->pdata[32], &idbuf[ATA_ID_FW_REV], 4);
 
 #ifdef DEBUG
-	ata_dump_id(tmpid);
+	ata_dump_id(idbuf);
 #endif
 	return 0;
 }
@@ -889,6 +899,11 @@ int ahci_init(u32 base)
 	u32 linkmap;
 
 	probe_ent = malloc(sizeof(struct ahci_probe_ent));
+	if (!probe_ent) {
+		printf("%s: No memory for probe_ent\n", __func__);
+		return -ENOMEM;
+	}
+
 	memset(probe_ent, 0, sizeof(struct ahci_probe_ent));
 
 	probe_ent->host_flags = ATA_FLAG_SATA
@@ -924,6 +939,11 @@ int ahci_init(u32 base)
 err_out:
 	return rc;
 }
+
+void __weak scsi_init(void)
+{
+}
+
 #endif
 
 /*
diff --git a/drivers/block/pata_bfin.c b/drivers/block/pata_bfin.c
index 27ecaf4f9e..b7fd1cd634 100644
--- a/drivers/block/pata_bfin.c
+++ b/drivers/block/pata_bfin.c
@@ -12,6 +12,7 @@
 #include <command.h>
 #include <config.h>
 #include <asm/byteorder.h>
+#include <asm/clock.h>
 #include <asm/io.h>
 #include <asm/errno.h>
 #include <asm/portmux.h>
diff --git a/drivers/block/sandbox.c b/drivers/block/sandbox.c
new file mode 100644
index 0000000000..73f4c4a9e9
--- /dev/null
+++ b/drivers/block/sandbox.c
@@ -0,0 +1,124 @@
+/*
+ * Copyright (C) 2013 Henrik Nordstrom <henrik@henriknordstrom.net>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <config.h>
+#include <common.h>
+#include <part.h>
+#include <os.h>
+#include <malloc.h>
+#include <sandboxblockdev.h>
+#include <asm/errno.h>
+
+static struct host_block_dev host_devices[CONFIG_HOST_MAX_DEVICES];
+
+static struct host_block_dev *find_host_device(int dev)
+{
+	if (dev >= 0 && dev < CONFIG_HOST_MAX_DEVICES)
+		return &host_devices[dev];
+
+	return NULL;
+}
+
+static unsigned long host_block_read(int dev, unsigned long start,
+				     lbaint_t blkcnt, void *buffer)
+{
+	struct host_block_dev *host_dev = find_host_device(dev);
+
+	if (!host_dev)
+		return -1;
+	if (os_lseek(host_dev->fd,
+		     start * host_dev->blk_dev.blksz,
+		     OS_SEEK_SET) == -1) {
+		printf("ERROR: Invalid position\n");
+		return -1;
+	}
+	ssize_t len = os_read(host_dev->fd, buffer,
+			      blkcnt * host_dev->blk_dev.blksz);
+	if (len >= 0)
+		return len / host_dev->blk_dev.blksz;
+	return -1;
+}
+
+static unsigned long host_block_write(int dev, unsigned long start,
+				      lbaint_t blkcnt, const void *buffer)
+{
+	struct host_block_dev *host_dev = find_host_device(dev);
+	if (os_lseek(host_dev->fd,
+		     start * host_dev->blk_dev.blksz,
+		     OS_SEEK_SET) == -1) {
+		printf("ERROR: Invalid position\n");
+		return -1;
+	}
+	ssize_t len = os_write(host_dev->fd, buffer, blkcnt *
+			       host_dev->blk_dev.blksz);
+	if (len >= 0)
+		return len / host_dev->blk_dev.blksz;
+	return -1;
+}
+
+int host_dev_bind(int dev, char *filename)
+{
+	struct host_block_dev *host_dev = find_host_device(dev);
+
+	if (!host_dev)
+		return -1;
+	if (host_dev->blk_dev.priv) {
+		os_close(host_dev->fd);
+		host_dev->blk_dev.priv = NULL;
+	}
+	if (host_dev->filename)
+		free(host_dev->filename);
+	if (filename && *filename) {
+		host_dev->filename = strdup(filename);
+	} else {
+		host_dev->filename = NULL;
+		return 0;
+	}
+
+	host_dev->fd = os_open(host_dev->filename, OS_O_RDWR);
+	if (host_dev->fd == -1) {
+		printf("Failed to access host backing file '%s'\n",
+		       host_dev->filename);
+		return 1;
+	}
+
+	block_dev_desc_t *blk_dev = &host_dev->blk_dev;
+	blk_dev->if_type = IF_TYPE_HOST;
+	blk_dev->priv = host_dev;
+	blk_dev->blksz = 512;
+	blk_dev->lba = os_lseek(host_dev->fd, 0, OS_SEEK_END) / blk_dev->blksz;
+	blk_dev->block_read = host_block_read;
+	blk_dev->block_write = host_block_write;
+	blk_dev->dev = dev;
+	blk_dev->part_type = PART_TYPE_UNKNOWN;
+	init_part(blk_dev);
+
+	return 0;
+}
+
+int host_get_dev_err(int dev, block_dev_desc_t **blk_devp)
+{
+	struct host_block_dev *host_dev = find_host_device(dev);
+
+	if (!host_dev)
+		return -ENODEV;
+
+	if (!host_dev->blk_dev.priv)
+		return -ENOENT;
+
+	*blk_devp = &host_dev->blk_dev;
+	return 0;
+}
+
+block_dev_desc_t *host_get_dev(int dev)
+{
+	block_dev_desc_t *blk_dev;
+
+	if (host_get_dev_err(dev, &blk_dev))
+		return NULL;
+
+	return blk_dev;
+}
diff --git a/drivers/bootcount/Makefile b/drivers/bootcount/Makefile
index 2b517b6dfb..6f1c419c7a 100644
--- a/drivers/bootcount/Makefile
+++ b/drivers/bootcount/Makefile
@@ -2,28 +2,11 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB 	:= $(obj)libbootcount.o
-
-COBJS-y				+= bootcount.o
-COBJS-$(CONFIG_AT91SAM9XE)	+= bootcount_at91.o
-COBJS-$(CONFIG_BLACKFIN)	+= bootcount_blackfin.o
-COBJS-$(CONFIG_SOC_DA8XX)	+= bootcount_davinci.o
-COBJS-$(CONFIG_BOOTCOUNT_RAM)	+= bootcount_ram.o
-
-COBJS	:= $(COBJS-y)
-SRCS 	:= $(COBJS:.o=.c)
-OBJS 	:= $(addprefix $(obj),$(COBJS))
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-########################################################################
+obj-y				+= bootcount.o
+obj-$(CONFIG_AT91SAM9XE)	+= bootcount_at91.o
+obj-$(CONFIG_BLACKFIN)		+= bootcount_blackfin.o
+obj-$(CONFIG_SOC_DA8XX)		+= bootcount_davinci.o
+obj-$(CONFIG_BOOTCOUNT_AM33XX)	+= bootcount_davinci.o
+obj-$(CONFIG_BOOTCOUNT_RAM)	+= bootcount_ram.o
+obj-$(CONFIG_BOOTCOUNT_ENV)	+= bootcount_env.o
+obj-$(CONFIG_BOOTCOUNT_I2C)	+= bootcount_i2c.o
diff --git a/drivers/bootcount/bootcount_davinci.c b/drivers/bootcount/bootcount_davinci.c
index efa4d42cbf..fa87b5e7b9 100644
--- a/drivers/bootcount/bootcount_davinci.c
+++ b/drivers/bootcount/bootcount_davinci.c
@@ -2,12 +2,15 @@
  * (C) Copyright 2011
  * Heiko Schocher, DENX Software Engineering, hs@denx.de.
  *
+ * A bootcount driver for the RTC IP block found on many TI platforms.
+ * This requires the RTC clocks, etc, to be enabled prior to use and
+ * not all boards with this IP block on it will have the RTC in use.
+ *
  * SPDX-License-Identifier:	GPL-2.0+
  */
 
 #include <bootcount.h>
-#include <asm/arch/da850_lowlevel.h>
-#include <asm/arch/davinci_misc.h>
+#include <asm/davinci_rtc.h>
 
 void bootcount_store(ulong a)
 {
@@ -21,17 +24,19 @@ void bootcount_store(ulong a)
 	 */
 	writel(RTC_KICK0R_WE, &reg->kick0r);
 	writel(RTC_KICK1R_WE, &reg->kick1r);
-	raw_bootcount_store(&reg->scratch0, a);
-	raw_bootcount_store(&reg->scratch1, BOOTCOUNT_MAGIC);
+	raw_bootcount_store(&reg->scratch2,
+			    (BOOTCOUNT_MAGIC & 0xffff0000) | (a & 0x0000ffff));
 }
 
 ulong bootcount_load(void)
 {
+	unsigned long val;
 	struct davinci_rtc *reg =
 		(struct davinci_rtc *)CONFIG_SYS_BOOTCOUNT_ADDR;
 
-	if (raw_bootcount_load(&reg->scratch1) != BOOTCOUNT_MAGIC)
+	val = raw_bootcount_load(&reg->scratch2);
+	if ((val & 0xffff0000) != (BOOTCOUNT_MAGIC & 0xffff0000))
 		return 0;
 	else
-		return raw_bootcount_load(&reg->scratch0);
+		return val & 0x0000ffff;
 }
diff --git a/drivers/bootcount/bootcount_env.c b/drivers/bootcount/bootcount_env.c
new file mode 100644
index 0000000000..2d6e8db126
--- /dev/null
+++ b/drivers/bootcount/bootcount_env.c
@@ -0,0 +1,29 @@
+/*
+ * (C) Copyright 2013
+ * Heiko Schocher, DENX Software Engineering, hs@denx.de.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+
+void bootcount_store(ulong a)
+{
+	int upgrade_available = getenv_ulong("upgrade_available", 10, 0);
+
+	if (upgrade_available) {
+		setenv_ulong("bootcount", a);
+		saveenv();
+	}
+}
+
+ulong bootcount_load(void)
+{
+	int upgrade_available = getenv_ulong("upgrade_available", 10, 0);
+	ulong val = 0;
+
+	if (upgrade_available)
+		val = getenv_ulong("bootcount", 10, 0);
+
+	return val;
+}
diff --git a/drivers/bootcount/bootcount_i2c.c b/drivers/bootcount/bootcount_i2c.c
new file mode 100644
index 0000000000..e27b168c55
--- /dev/null
+++ b/drivers/bootcount/bootcount_i2c.c
@@ -0,0 +1,44 @@
+/*
+ * (C) Copyright 2013
+ * Heiko Schocher, DENX Software Engineering, hs@denx.de.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <bootcount.h>
+#include <linux/compiler.h>
+#include <i2c.h>
+
+#define BC_MAGIC	0xbc
+
+void bootcount_store(ulong a)
+{
+	unsigned char buf[3];
+	int ret;
+
+	buf[0] = BC_MAGIC;
+	buf[1] = (a & 0xff);
+	ret = i2c_write(CONFIG_SYS_I2C_RTC_ADDR, CONFIG_SYS_BOOTCOUNT_ADDR,
+		  CONFIG_BOOTCOUNT_ALEN, buf, 2);
+	if (ret != 0)
+		puts("Error writing bootcount\n");
+}
+
+ulong bootcount_load(void)
+{
+	unsigned char buf[3];
+	int ret;
+
+	ret = i2c_read(CONFIG_SYS_I2C_RTC_ADDR, CONFIG_SYS_BOOTCOUNT_ADDR,
+		       CONFIG_BOOTCOUNT_ALEN, buf, 2);
+	if (ret != 0) {
+		puts("Error loading bootcount\n");
+		return 0;
+	}
+	if (buf[0] == BC_MAGIC)
+		return buf[1];
+
+	bootcount_store(0);
+
+	return 0;
+}
diff --git a/drivers/core/Makefile b/drivers/core/Makefile
new file mode 100644
index 0000000000..90b2a7f068
--- /dev/null
+++ b/drivers/core/Makefile
@@ -0,0 +1,7 @@
+#
+# Copyright (c) 2013 Google, Inc
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-$(CONFIG_DM)	:= device.o lists.o root.o uclass.o util.o
diff --git a/drivers/core/device.c b/drivers/core/device.c
new file mode 100644
index 0000000000..55ba281be0
--- /dev/null
+++ b/drivers/core/device.c
@@ -0,0 +1,348 @@
+/*
+ * Device manager
+ *
+ * Copyright (c) 2013 Google, Inc
+ *
+ * (C) Copyright 2012
+ * Pavel Herrmann <morpheus.ibis@gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <malloc.h>
+#include <dm/device.h>
+#include <dm/device-internal.h>
+#include <dm/lists.h>
+#include <dm/platdata.h>
+#include <dm/uclass.h>
+#include <dm/uclass-internal.h>
+#include <dm/util.h>
+#include <linux/err.h>
+#include <linux/list.h>
+
+/**
+ * device_chld_unbind() - Unbind all device's children from the device
+ *
+ * On error, the function continues to unbind all children, and reports the
+ * first error.
+ *
+ * @dev:	The device that is to be stripped of its children
+ * @return 0 on success, -ve on error
+ */
+static int device_chld_unbind(struct device *dev)
+{
+	struct device *pos, *n;
+	int ret, saved_ret = 0;
+
+	assert(dev);
+
+	list_for_each_entry_safe(pos, n, &dev->child_head, sibling_node) {
+		ret = device_unbind(pos);
+		if (ret && !saved_ret)
+			saved_ret = ret;
+	}
+
+	return saved_ret;
+}
+
+/**
+ * device_chld_remove() - Stop all device's children
+ * @dev:	The device whose children are to be removed
+ * @return 0 on success, -ve on error
+ */
+static int device_chld_remove(struct device *dev)
+{
+	struct device *pos, *n;
+	int ret;
+
+	assert(dev);
+
+	list_for_each_entry_safe(pos, n, &dev->child_head, sibling_node) {
+		ret = device_remove(pos);
+		if (ret)
+			return ret;
+	}
+
+	return 0;
+}
+
+int device_bind(struct device *parent, struct driver *drv, const char *name,
+		void *platdata, int of_offset, struct device **devp)
+{
+	struct device *dev;
+	struct uclass *uc;
+	int ret = 0;
+
+	*devp = NULL;
+	if (!name)
+		return -EINVAL;
+
+	ret = uclass_get(drv->id, &uc);
+	if (ret)
+		return ret;
+
+	dev = calloc(1, sizeof(struct device));
+	if (!dev)
+		return -ENOMEM;
+
+	INIT_LIST_HEAD(&dev->sibling_node);
+	INIT_LIST_HEAD(&dev->child_head);
+	INIT_LIST_HEAD(&dev->uclass_node);
+	dev->platdata = platdata;
+	dev->name = name;
+	dev->of_offset = of_offset;
+	dev->parent = parent;
+	dev->driver = drv;
+	dev->uclass = uc;
+	if (!dev->platdata && drv->platdata_auto_alloc_size)
+		dev->flags |= DM_FLAG_ALLOC_PDATA;
+
+	/* put dev into parent's successor list */
+	if (parent)
+		list_add_tail(&dev->sibling_node, &parent->child_head);
+
+	ret = uclass_bind_device(dev);
+	if (ret)
+		goto fail_bind;
+
+	/* if we fail to bind we remove device from successors and free it */
+	if (drv->bind) {
+		ret = drv->bind(dev);
+		if (ret) {
+			if (uclass_unbind_device(dev)) {
+				dm_warn("Failed to unbind dev '%s' on error path\n",
+					dev->name);
+			}
+			goto fail_bind;
+		}
+	}
+	if (parent)
+		dm_dbg("Bound device %s to %s\n", dev->name, parent->name);
+	*devp = dev;
+
+	return 0;
+
+fail_bind:
+	list_del(&dev->sibling_node);
+	free(dev);
+	return ret;
+}
+
+int device_bind_by_name(struct device *parent, const struct driver_info *info,
+			struct device **devp)
+{
+	struct driver *drv;
+
+	drv = lists_driver_lookup_name(info->name);
+	if (!drv)
+		return -ENOENT;
+
+	return device_bind(parent, drv, info->name, (void *)info->platdata,
+			   -1, devp);
+}
+
+int device_unbind(struct device *dev)
+{
+	struct driver *drv;
+	int ret;
+
+	if (!dev)
+		return -EINVAL;
+
+	if (dev->flags & DM_FLAG_ACTIVATED)
+		return -EINVAL;
+
+	drv = dev->driver;
+	assert(drv);
+
+	if (drv->unbind) {
+		ret = drv->unbind(dev);
+		if (ret)
+			return ret;
+	}
+
+	ret = device_chld_unbind(dev);
+	if (ret)
+		return ret;
+
+	ret = uclass_unbind_device(dev);
+	if (ret)
+		return ret;
+
+	if (dev->parent)
+		list_del(&dev->sibling_node);
+	free(dev);
+
+	return 0;
+}
+
+/**
+ * device_free() - Free memory buffers allocated by a device
+ * @dev:	Device that is to be started
+ */
+static void device_free(struct device *dev)
+{
+	int size;
+
+	if (dev->driver->priv_auto_alloc_size) {
+		free(dev->priv);
+		dev->priv = NULL;
+	}
+	if (dev->flags & DM_FLAG_ALLOC_PDATA) {
+		free(dev->platdata);
+		dev->platdata = NULL;
+	}
+	size = dev->uclass->uc_drv->per_device_auto_alloc_size;
+	if (size) {
+		free(dev->uclass_priv);
+		dev->uclass_priv = NULL;
+	}
+}
+
+int device_probe(struct device *dev)
+{
+	struct driver *drv;
+	int size = 0;
+	int ret;
+
+	if (!dev)
+		return -EINVAL;
+
+	if (dev->flags & DM_FLAG_ACTIVATED)
+		return 0;
+
+	drv = dev->driver;
+	assert(drv);
+
+	/* Allocate private data and platdata if requested */
+	if (drv->priv_auto_alloc_size) {
+		dev->priv = calloc(1, drv->priv_auto_alloc_size);
+		if (!dev->priv) {
+			ret = -ENOMEM;
+			goto fail;
+		}
+	}
+	/* Allocate private data if requested */
+	if (dev->flags & DM_FLAG_ALLOC_PDATA) {
+		dev->platdata = calloc(1, drv->platdata_auto_alloc_size);
+		if (!dev->platdata) {
+			ret = -ENOMEM;
+			goto fail;
+		}
+	}
+	size = dev->uclass->uc_drv->per_device_auto_alloc_size;
+	if (size) {
+		dev->uclass_priv = calloc(1, size);
+		if (!dev->uclass_priv) {
+			ret = -ENOMEM;
+			goto fail;
+		}
+	}
+
+	/* Ensure all parents are probed */
+	if (dev->parent) {
+		ret = device_probe(dev->parent);
+		if (ret)
+			goto fail;
+	}
+
+	if (drv->ofdata_to_platdata && dev->of_offset >= 0) {
+		ret = drv->ofdata_to_platdata(dev);
+		if (ret)
+			goto fail;
+	}
+
+	if (drv->probe) {
+		ret = drv->probe(dev);
+		if (ret)
+			goto fail;
+	}
+
+	dev->flags |= DM_FLAG_ACTIVATED;
+
+	ret = uclass_post_probe_device(dev);
+	if (ret) {
+		dev->flags &= ~DM_FLAG_ACTIVATED;
+		goto fail_uclass;
+	}
+
+	return 0;
+fail_uclass:
+	if (device_remove(dev)) {
+		dm_warn("%s: Device '%s' failed to remove on error path\n",
+			__func__, dev->name);
+	}
+fail:
+	device_free(dev);
+
+	return ret;
+}
+
+int device_remove(struct device *dev)
+{
+	struct driver *drv;
+	int ret;
+
+	if (!dev)
+		return -EINVAL;
+
+	if (!(dev->flags & DM_FLAG_ACTIVATED))
+		return 0;
+
+	drv = dev->driver;
+	assert(drv);
+
+	ret = uclass_pre_remove_device(dev);
+	if (ret)
+		return ret;
+
+	ret = device_chld_remove(dev);
+	if (ret)
+		goto err;
+
+	if (drv->remove) {
+		ret = drv->remove(dev);
+		if (ret)
+			goto err_remove;
+	}
+
+	device_free(dev);
+
+	dev->flags &= ~DM_FLAG_ACTIVATED;
+
+	return 0;
+
+err_remove:
+	/* We can't put the children back */
+	dm_warn("%s: Device '%s' failed to remove, but children are gone\n",
+		__func__, dev->name);
+err:
+	ret = uclass_post_probe_device(dev);
+	if (ret) {
+		dm_warn("%s: Device '%s' failed to post_probe on error path\n",
+			__func__, dev->name);
+	}
+
+	return ret;
+}
+
+void *dev_get_platdata(struct device *dev)
+{
+	if (!dev) {
+		dm_warn("%s: null device", __func__);
+		return NULL;
+	}
+
+	return dev->platdata;
+}
+
+void *dev_get_priv(struct device *dev)
+{
+	if (!dev) {
+		dm_warn("%s: null device", __func__);
+		return NULL;
+	}
+
+	return dev->priv;
+}
diff --git a/drivers/core/lists.c b/drivers/core/lists.c
new file mode 100644
index 0000000000..4f2c12631d
--- /dev/null
+++ b/drivers/core/lists.c
@@ -0,0 +1,155 @@
+/*
+ * Copyright (c) 2013 Google, Inc
+ *
+ * (C) Copyright 2012
+ * Marek Vasut <marex@denx.de>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <errno.h>
+#include <dm/device.h>
+#include <dm/device-internal.h>
+#include <dm/platdata.h>
+#include <dm/uclass.h>
+#include <dm/util.h>
+#include <linux/compiler.h>
+
+struct driver *lists_driver_lookup_name(const char *name)
+{
+	struct driver *drv =
+		ll_entry_start(struct driver, driver);
+	const int n_ents = ll_entry_count(struct driver, driver);
+	struct driver *entry;
+	int len;
+
+	if (!drv || !n_ents)
+		return NULL;
+
+	len = strlen(name);
+
+	for (entry = drv; entry != drv + n_ents; entry++) {
+		if (strncmp(name, entry->name, len))
+			continue;
+
+		/* Full match */
+		if (len == strlen(entry->name))
+			return entry;
+	}
+
+	/* Not found */
+	return NULL;
+}
+
+struct uclass_driver *lists_uclass_lookup(enum uclass_id id)
+{
+	struct uclass_driver *uclass =
+		ll_entry_start(struct uclass_driver, uclass);
+	const int n_ents = ll_entry_count(struct uclass_driver, uclass);
+	struct uclass_driver *entry;
+
+	if ((id == UCLASS_INVALID) || !uclass)
+		return NULL;
+
+	for (entry = uclass; entry != uclass + n_ents; entry++) {
+		if (entry->id == id)
+			return entry;
+	}
+
+	return NULL;
+}
+
+int lists_bind_drivers(struct device *parent)
+{
+	struct driver_info *info =
+		ll_entry_start(struct driver_info, driver_info);
+	const int n_ents = ll_entry_count(struct driver_info, driver_info);
+	struct driver_info *entry;
+	struct device *dev;
+	int result = 0;
+	int ret;
+
+	for (entry = info; entry != info + n_ents; entry++) {
+		ret = device_bind_by_name(parent, entry, &dev);
+		if (ret) {
+			dm_warn("No match for driver '%s'\n", entry->name);
+			if (!result || ret != -ENOENT)
+				result = ret;
+		}
+	}
+
+	return result;
+}
+
+#ifdef CONFIG_OF_CONTROL
+/**
+ * driver_check_compatible() - Check if a driver is compatible with this node
+ *
+ * @param blob:		Device tree pointer
+ * @param offset:	Offset of node in device tree
+ * @param of_matchL	List of compatible strings to match
+ * @return 0 if there is a match, -ENOENT if no match, -ENODEV if the node
+ * does not have a compatible string, other error <0 if there is a device
+ * tree error
+ */
+static int driver_check_compatible(const void *blob, int offset,
+				   const struct device_id *of_match)
+{
+	int ret;
+
+	if (!of_match)
+		return -ENOENT;
+
+	while (of_match->compatible) {
+		ret = fdt_node_check_compatible(blob, offset,
+						of_match->compatible);
+		if (!ret)
+			return 0;
+		else if (ret == -FDT_ERR_NOTFOUND)
+			return -ENODEV;
+		else if (ret < 0)
+			return -EINVAL;
+		of_match++;
+	}
+
+	return -ENOENT;
+}
+
+int lists_bind_fdt(struct device *parent, const void *blob, int offset)
+{
+	struct driver *driver = ll_entry_start(struct driver, driver);
+	const int n_ents = ll_entry_count(struct driver, driver);
+	struct driver *entry;
+	struct device *dev;
+	const char *name;
+	int result = 0;
+	int ret;
+
+	dm_dbg("bind node %s\n", fdt_get_name(blob, offset, NULL));
+	for (entry = driver; entry != driver + n_ents; entry++) {
+		ret = driver_check_compatible(blob, offset, entry->of_match);
+		if (ret == -ENOENT) {
+			continue;
+		} else if (ret == -ENODEV) {
+			break;
+		} else if (ret) {
+			dm_warn("Device tree error at offset %d\n", offset);
+			if (!result || ret != -ENOENT)
+				result = ret;
+			break;
+		}
+
+		name = fdt_get_name(blob, offset, NULL);
+		dm_dbg("   - found match at '%s'\n", entry->name);
+		ret = device_bind(parent, entry, name, NULL, offset, &dev);
+		if (ret) {
+			dm_warn("No match for driver '%s'\n", entry->name);
+			if (!result || ret != -ENOENT)
+				result = ret;
+		}
+	}
+
+	return result;
+}
+#endif
diff --git a/drivers/core/root.c b/drivers/core/root.c
new file mode 100644
index 0000000000..407bc0d046
--- /dev/null
+++ b/drivers/core/root.c
@@ -0,0 +1,102 @@
+/*
+ * Copyright (c) 2013 Google, Inc
+ *
+ * (C) Copyright 2012
+ * Pavel Herrmann <morpheus.ibis@gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <errno.h>
+#include <malloc.h>
+#include <dm/device.h>
+#include <dm/device-internal.h>
+#include <dm/lists.h>
+#include <dm/platdata.h>
+#include <dm/uclass.h>
+#include <dm/util.h>
+#include <linux/list.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static const struct driver_info root_info = {
+	.name		= "root_driver",
+};
+
+struct device *dm_root(void)
+{
+	if (!gd->dm_root) {
+		dm_warn("Virtual root driver does not exist!\n");
+		return NULL;
+	}
+
+	return gd->dm_root;
+}
+
+int dm_init(void)
+{
+	int ret;
+
+	if (gd->dm_root) {
+		dm_warn("Virtual root driver already exists!\n");
+		return -EINVAL;
+	}
+	INIT_LIST_HEAD(&gd->uclass_root);
+
+	ret = device_bind_by_name(NULL, &root_info, &gd->dm_root);
+	if (ret)
+		return ret;
+
+	return 0;
+}
+
+int dm_scan_platdata(void)
+{
+	int ret;
+
+	ret = lists_bind_drivers(gd->dm_root);
+	if (ret == -ENOENT) {
+		dm_warn("Some drivers were not found\n");
+		ret = 0;
+	}
+	if (ret)
+		return ret;
+
+	return 0;
+}
+
+#ifdef CONFIG_OF_CONTROL
+int dm_scan_fdt(const void *blob)
+{
+	int offset = 0;
+	int ret = 0, err;
+	int depth = 0;
+
+	do {
+		offset = fdt_next_node(blob, offset, &depth);
+		if (offset > 0 && depth == 1) {
+			err = lists_bind_fdt(gd->dm_root, blob, offset);
+			if (err && !ret)
+				ret = err;
+		}
+	} while (offset > 0);
+
+	if (ret)
+		dm_warn("Some drivers failed to bind\n");
+
+	return ret;
+}
+#endif
+
+/* This is the root driver - all drivers are children of this */
+U_BOOT_DRIVER(root_driver) = {
+	.name	= "root_driver",
+	.id	= UCLASS_ROOT,
+};
+
+/* This is the root uclass */
+UCLASS_DRIVER(root) = {
+	.name	= "root",
+	.id	= UCLASS_ROOT,
+};
diff --git a/drivers/core/uclass.c b/drivers/core/uclass.c
new file mode 100644
index 0000000000..4df5a8bd39
--- /dev/null
+++ b/drivers/core/uclass.c
@@ -0,0 +1,285 @@
+/*
+ * Copyright (c) 2013 Google, Inc
+ *
+ * (C) Copyright 2012
+ * Pavel Herrmann <morpheus.ibis@gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <errno.h>
+#include <malloc.h>
+#include <dm/device.h>
+#include <dm/device-internal.h>
+#include <dm/lists.h>
+#include <dm/uclass.h>
+#include <dm/uclass-internal.h>
+#include <dm/util.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct uclass *uclass_find(enum uclass_id key)
+{
+	struct uclass *uc;
+
+	/*
+	 * TODO(sjg@chromium.org): Optimise this, perhaps moving the found
+	 * node to the start of the list, or creating a linear array mapping
+	 * id to node.
+	 */
+	list_for_each_entry(uc, &gd->uclass_root, sibling_node) {
+		if (uc->uc_drv->id == key)
+			return uc;
+	}
+
+	return NULL;
+}
+
+/**
+ * uclass_add() - Create new uclass in list
+ * @id: Id number to create
+ * @ucp: Returns pointer to uclass, or NULL on error
+ * @return 0 on success, -ve on error
+ *
+ * The new uclass is added to the list. There must be only one uclass for
+ * each id.
+ */
+static int uclass_add(enum uclass_id id, struct uclass **ucp)
+{
+	struct uclass_driver *uc_drv;
+	struct uclass *uc;
+	int ret;
+
+	*ucp = NULL;
+	uc_drv = lists_uclass_lookup(id);
+	if (!uc_drv) {
+		dm_warn("Cannot find uclass for id %d: please add the UCLASS_DRIVER() declaration for this UCLASS_... id\n",
+			id);
+		return -ENOENT;
+	}
+	if (uc_drv->ops) {
+		dm_warn("No ops for uclass id %d\n", id);
+		return -EINVAL;
+	}
+	uc = calloc(1, sizeof(*uc));
+	if (!uc)
+		return -ENOMEM;
+	if (uc_drv->priv_auto_alloc_size) {
+		uc->priv = calloc(1, uc_drv->priv_auto_alloc_size);
+		if (!uc->priv) {
+			ret = -ENOMEM;
+			goto fail_mem;
+		}
+	}
+	uc->uc_drv = uc_drv;
+	INIT_LIST_HEAD(&uc->sibling_node);
+	INIT_LIST_HEAD(&uc->dev_head);
+	list_add(&uc->sibling_node, &gd->uclass_root);
+
+	if (uc_drv->init) {
+		ret = uc_drv->init(uc);
+		if (ret)
+			goto fail;
+	}
+
+	*ucp = uc;
+
+	return 0;
+fail:
+	if (uc_drv->priv_auto_alloc_size) {
+		free(uc->priv);
+		uc->priv = NULL;
+	}
+	list_del(&uc->sibling_node);
+fail_mem:
+	free(uc);
+
+	return ret;
+}
+
+int uclass_destroy(struct uclass *uc)
+{
+	struct uclass_driver *uc_drv;
+	struct device *dev, *tmp;
+	int ret;
+
+	list_for_each_entry_safe(dev, tmp, &uc->dev_head, uclass_node) {
+		ret = device_remove(dev);
+		if (ret)
+			return ret;
+		ret = device_unbind(dev);
+		if (ret)
+			return ret;
+	}
+
+	uc_drv = uc->uc_drv;
+	if (uc_drv->destroy)
+		uc_drv->destroy(uc);
+	list_del(&uc->sibling_node);
+	if (uc_drv->priv_auto_alloc_size)
+		free(uc->priv);
+	free(uc);
+
+	return 0;
+}
+
+int uclass_get(enum uclass_id id, struct uclass **ucp)
+{
+	struct uclass *uc;
+
+	*ucp = NULL;
+	uc = uclass_find(id);
+	if (!uc)
+		return uclass_add(id, ucp);
+	*ucp = uc;
+
+	return 0;
+}
+
+int uclass_find_device(enum uclass_id id, int index, struct device **devp)
+{
+	struct uclass *uc;
+	struct device *dev;
+	int ret;
+
+	*devp = NULL;
+	ret = uclass_get(id, &uc);
+	if (ret)
+		return ret;
+
+	list_for_each_entry(dev, &uc->dev_head, uclass_node) {
+		if (!index--) {
+			*devp = dev;
+			return 0;
+		}
+	}
+
+	return -ENODEV;
+}
+
+int uclass_get_device(enum uclass_id id, int index, struct device **devp)
+{
+	struct device *dev;
+	int ret;
+
+	*devp = NULL;
+	ret = uclass_find_device(id, index, &dev);
+	if (ret)
+		return ret;
+
+	ret = device_probe(dev);
+	if (ret)
+		return ret;
+
+	*devp = dev;
+
+	return 0;
+}
+
+int uclass_first_device(enum uclass_id id, struct device **devp)
+{
+	struct uclass *uc;
+	struct device *dev;
+	int ret;
+
+	*devp = NULL;
+	ret = uclass_get(id, &uc);
+	if (ret)
+		return ret;
+	if (list_empty(&uc->dev_head))
+		return 0;
+
+	dev = list_first_entry(&uc->dev_head, struct device, uclass_node);
+	ret = device_probe(dev);
+	if (ret)
+		return ret;
+	*devp = dev;
+
+	return 0;
+}
+
+int uclass_next_device(struct device **devp)
+{
+	struct device *dev = *devp;
+	int ret;
+
+	*devp = NULL;
+	if (list_is_last(&dev->uclass_node, &dev->uclass->dev_head))
+		return 0;
+
+	dev = list_entry(dev->uclass_node.next, struct device, uclass_node);
+	ret = device_probe(dev);
+	if (ret)
+		return ret;
+	*devp = dev;
+
+	return 0;
+}
+
+int uclass_bind_device(struct device *dev)
+{
+	struct uclass *uc;
+	int ret;
+
+	uc = dev->uclass;
+
+	list_add_tail(&dev->uclass_node, &uc->dev_head);
+
+	if (uc->uc_drv->post_bind) {
+		ret = uc->uc_drv->post_bind(dev);
+		if (ret) {
+			list_del(&dev->uclass_node);
+			return ret;
+		}
+	}
+
+	return 0;
+}
+
+int uclass_unbind_device(struct device *dev)
+{
+	struct uclass *uc;
+	int ret;
+
+	uc = dev->uclass;
+	if (uc->uc_drv->pre_unbind) {
+		ret = uc->uc_drv->pre_unbind(dev);
+		if (ret)
+			return ret;
+	}
+
+	list_del(&dev->uclass_node);
+	return 0;
+}
+
+int uclass_post_probe_device(struct device *dev)
+{
+	struct uclass_driver *uc_drv = dev->uclass->uc_drv;
+
+	if (uc_drv->post_probe)
+		return uc_drv->post_probe(dev);
+
+	return 0;
+}
+
+int uclass_pre_remove_device(struct device *dev)
+{
+	struct uclass_driver *uc_drv;
+	struct uclass *uc;
+	int ret;
+
+	uc = dev->uclass;
+	uc_drv = uc->uc_drv;
+	if (uc->uc_drv->pre_remove) {
+		ret = uc->uc_drv->pre_remove(dev);
+		if (ret)
+			return ret;
+	}
+	if (uc_drv->per_device_auto_alloc_size) {
+		free(dev->uclass_priv);
+		dev->uclass_priv = NULL;
+	}
+
+	return 0;
+}
diff --git a/drivers/core/util.c b/drivers/core/util.c
new file mode 100644
index 0000000000..e01dd06d28
--- /dev/null
+++ b/drivers/core/util.c
@@ -0,0 +1,37 @@
+/*
+ * Copyright (c) 2013 Google, Inc
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <vsprintf.h>
+
+void dm_warn(const char *fmt, ...)
+{
+	va_list args;
+
+	va_start(args, fmt);
+	vprintf(fmt, args);
+	va_end(args);
+}
+
+void dm_dbg(const char *fmt, ...)
+{
+	va_list args;
+
+	va_start(args, fmt);
+	vprintf(fmt, args);
+	va_end(args);
+}
+
+int list_count_items(struct list_head *head)
+{
+	struct list_head *node;
+	int count = 0;
+
+	list_for_each(node, head)
+		count++;
+
+	return count;
+}
diff --git a/drivers/crypto/Makefile b/drivers/crypto/Makefile
index 02c53bffd1..b8077953c5 100644
--- a/drivers/crypto/Makefile
+++ b/drivers/crypto/Makefile
@@ -5,27 +5,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	:= $(obj)libcrypto.o
-
-COBJS-$(CONFIG_EXYNOS_ACE_SHA)	+= ace_sha.o
-
-COBJS	:= $(COBJS-y)
-SRCS	:= $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-
-all:	$(LIB)
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-########################################################################
+obj-$(CONFIG_EXYNOS_ACE_SHA)	+= ace_sha.o
diff --git a/drivers/crypto/ace_sha.c b/drivers/crypto/ace_sha.c
index acbafde97c..ed4f541823 100644
--- a/drivers/crypto/ace_sha.c
+++ b/drivers/crypto/ace_sha.c
@@ -5,10 +5,12 @@
  * SPDX-License-Identifier:	GPL-2.0+
  */
 #include <common.h>
+#include "ace_sha.h"
+
+#ifdef CONFIG_SHA_HW_ACCEL
 #include <sha256.h>
 #include <sha1.h>
 #include <asm/errno.h>
-#include "ace_sha.h"
 
 /* SHA1 value for the message of zero length */
 static const unsigned char sha1_digest_emptymsg[SHA1_SUM_LEN] = {
@@ -111,3 +113,72 @@ void hw_sha1(const unsigned char *pbuf, unsigned int buf_len,
 	if (ace_sha_hash_digest(pbuf, buf_len, pout, ACE_SHA_TYPE_SHA1))
 		debug("ACE was not setup properly or it is faulty\n");
 }
+#endif /* CONFIG_SHA_HW_ACCEL */
+
+#ifdef CONFIG_LIB_HW_RAND
+static unsigned int seed_done;
+
+void srand(unsigned int seed)
+{
+	struct exynos_ace_sfr *reg =
+		(struct exynos_ace_sfr *)samsung_get_base_ace_sfr();
+	int i, status;
+
+	/* Seed data */
+	for (i = 0; i < ACE_HASH_PRNG_REG_NUM; i++)
+		writel(seed << i, &reg->hash_seed[i]);
+
+	/* Wait for seed setup done */
+	while (1) {
+		status = readl(&reg->hash_status);
+		if ((status & ACE_HASH_SEEDSETTING_MASK) ||
+		    (status & ACE_HASH_PRNGERROR_MASK))
+			break;
+	}
+
+	seed_done = 1;
+}
+
+unsigned int rand(void)
+{
+	struct exynos_ace_sfr *reg =
+		(struct exynos_ace_sfr *)samsung_get_base_ace_sfr();
+	int i, status;
+	unsigned int seed = (unsigned int)&status;
+	unsigned int ret = 0;
+
+	if (!seed_done)
+		srand(seed);
+
+	/* Start PRNG */
+	writel(ACE_HASH_ENGSEL_PRNG | ACE_HASH_STARTBIT_ON, &reg->hash_control);
+
+	/* Wait for PRNG done */
+	while (1) {
+		status = readl(&reg->hash_status);
+		if (status & ACE_HASH_PRNGDONE_MASK)
+			break;
+		if (status & ACE_HASH_PRNGERROR_MASK) {
+			seed_done = 0;
+			return 0;
+		}
+	}
+
+	/* Clear Done IRQ */
+	writel(ACE_HASH_PRNGDONE_MASK, &reg->hash_status);
+
+	/* Read a PRNG result */
+	for (i = 0; i < ACE_HASH_PRNG_REG_NUM; i++)
+		ret += readl(&reg->hash_prng[i]);
+
+	seed_done = 0;
+	return ret;
+}
+
+unsigned int rand_r(unsigned int *seedp)
+{
+	srand(*seedp);
+
+	return rand();
+}
+#endif /* CONFIG_LIB_HW_RAND */
diff --git a/drivers/crypto/ace_sha.h b/drivers/crypto/ace_sha.h
index a426d52372..f1097f72dc 100644
--- a/drivers/crypto/ace_sha.h
+++ b/drivers/crypto/ace_sha.h
@@ -72,9 +72,10 @@ struct exynos_ace_sfr {
 	unsigned char   res12[0x30];
 	unsigned int	hash_result[8];
 	unsigned char   res13[0x20];
-	unsigned int	hash_seed[8];
-	unsigned int	hash_prng[8];
-	unsigned char   res14[0x180];
+	unsigned int	hash_seed[5];
+	unsigned char	res14[12];
+	unsigned int	hash_prng[5];
+	unsigned char	res15[0x18c];
 
 	unsigned int	pka_sfr[5];		/* base + 0x700 */
 };
@@ -291,6 +292,7 @@ struct exynos_ace_sfr {
 #define ACE_HASH_PRNGERROR_MASK	(1 << 7)
 #define ACE_HASH_PRNGERROR_OFF		(0 << 7)
 #define ACE_HASH_PRNGERROR_ON		(1 << 7)
+#define ACE_HASH_PRNG_REG_NUM		5
 
 #define ACE_SHA_TYPE_SHA1		1
 #define ACE_SHA_TYPE_SHA256		2
diff --git a/drivers/ddr/fsl/Makefile b/drivers/ddr/fsl/Makefile
new file mode 100644
index 0000000000..265204f311
--- /dev/null
+++ b/drivers/ddr/fsl/Makefile
@@ -0,0 +1,34 @@
+#
+# Copyright 2008-2011 Freescale Semiconductor, Inc.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License
+# Version 2 as published by the Free Software Foundation.
+#
+
+obj-$(CONFIG_SYS_FSL_DDR1)	+= main.o util.o ctrl_regs.o options.o \
+				   lc_common_dimm_params.o
+
+obj-$(CONFIG_SYS_FSL_DDR2)	+= main.o util.o ctrl_regs.o options.o \
+				   lc_common_dimm_params.o
+
+obj-$(CONFIG_SYS_FSL_DDR3)	+= main.o util.o ctrl_regs.o options.o \
+				   lc_common_dimm_params.o
+ifdef CONFIG_DDR_SPD
+SPD := y
+endif
+ifdef CONFIG_SPD_EEPROM
+SPD := y
+endif
+ifdef SPD
+obj-$(CONFIG_SYS_FSL_DDR1)	+= ddr1_dimm_params.o
+obj-$(CONFIG_SYS_FSL_DDR2)	+= ddr2_dimm_params.o
+obj-$(CONFIG_SYS_FSL_DDR3)	+= ddr3_dimm_params.o
+endif
+
+obj-$(CONFIG_FSL_DDR_INTERACTIVE)	+= interactive.o
+obj-$(CONFIG_SYS_FSL_DDRC_GEN1)	+= mpc85xx_ddr_gen1.o
+obj-$(CONFIG_SYS_FSL_DDRC_GEN2)	+= mpc85xx_ddr_gen2.o
+obj-$(CONFIG_SYS_FSL_DDRC_GEN3)	+= mpc85xx_ddr_gen3.o
+obj-$(CONFIG_SYS_FSL_DDR_86XX)		+= mpc86xx_ddr.o
+obj-$(CONFIG_SYS_FSL_DDRC_ARM_GEN3)	+= arm_ddr_gen3.o
diff --git a/drivers/ddr/fsl/arm_ddr_gen3.c b/drivers/ddr/fsl/arm_ddr_gen3.c
new file mode 100644
index 0000000000..d4ed9aec2a
--- /dev/null
+++ b/drivers/ddr/fsl/arm_ddr_gen3.c
@@ -0,0 +1,214 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ *
+ * Derived from mpc85xx_ddr_gen3.c, removed all workarounds
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <fsl_ddr_sdram.h>
+#include <asm/processor.h>
+#include <fsl_immap.h>
+#include <fsl_ddr.h>
+
+#if (CONFIG_CHIP_SELECTS_PER_CTRL > 4)
+#error Invalid setting for CONFIG_CHIP_SELECTS_PER_CTRL
+#endif
+
+
+/*
+ * regs has the to-be-set values for DDR controller registers
+ * ctrl_num is the DDR controller number
+ * step: 0 goes through the initialization in one pass
+ *       1 sets registers and returns before enabling controller
+ *       2 resumes from step 1 and continues to initialize
+ * Dividing the initialization to two steps to deassert DDR reset signal
+ * to comply with JEDEC specs for RDIMMs.
+ */
+void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
+			     unsigned int ctrl_num, int step)
+{
+	unsigned int i, bus_width;
+	struct ccsr_ddr __iomem *ddr;
+	u32 temp_sdram_cfg;
+	u32 total_gb_size_per_controller;
+	int timeout;
+
+	switch (ctrl_num) {
+	case 0:
+		ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
+		break;
+#if defined(CONFIG_SYS_FSL_DDR2_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 1)
+	case 1:
+		ddr = (void *)CONFIG_SYS_FSL_DDR2_ADDR;
+		break;
+#endif
+#if defined(CONFIG_SYS_FSL_DDR3_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 2)
+	case 2:
+		ddr = (void *)CONFIG_SYS_FSL_DDR3_ADDR;
+		break;
+#endif
+#if defined(CONFIG_SYS_FSL_DDR4_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 3)
+	case 3:
+		ddr = (void *)CONFIG_SYS_FSL_DDR4_ADDR;
+		break;
+#endif
+	default:
+		printf("%s unexpected ctrl_num = %u\n", __func__, ctrl_num);
+		return;
+	}
+
+	if (step == 2)
+		goto step2;
+
+	if (regs->ddr_eor)
+		ddr_out32(&ddr->eor, regs->ddr_eor);
+	for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
+		if (i == 0) {
+			ddr_out32(&ddr->cs0_bnds, regs->cs[i].bnds);
+			ddr_out32(&ddr->cs0_config, regs->cs[i].config);
+			ddr_out32(&ddr->cs0_config_2, regs->cs[i].config_2);
+
+		} else if (i == 1) {
+			ddr_out32(&ddr->cs1_bnds, regs->cs[i].bnds);
+			ddr_out32(&ddr->cs1_config, regs->cs[i].config);
+			ddr_out32(&ddr->cs1_config_2, regs->cs[i].config_2);
+
+		} else if (i == 2) {
+			ddr_out32(&ddr->cs2_bnds, regs->cs[i].bnds);
+			ddr_out32(&ddr->cs2_config, regs->cs[i].config);
+			ddr_out32(&ddr->cs2_config_2, regs->cs[i].config_2);
+
+		} else if (i == 3) {
+			ddr_out32(&ddr->cs3_bnds, regs->cs[i].bnds);
+			ddr_out32(&ddr->cs3_config, regs->cs[i].config);
+			ddr_out32(&ddr->cs3_config_2, regs->cs[i].config_2);
+		}
+	}
+
+	ddr_out32(&ddr->timing_cfg_3, regs->timing_cfg_3);
+	ddr_out32(&ddr->timing_cfg_0, regs->timing_cfg_0);
+	ddr_out32(&ddr->timing_cfg_1, regs->timing_cfg_1);
+	ddr_out32(&ddr->timing_cfg_2, regs->timing_cfg_2);
+	ddr_out32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2);
+	ddr_out32(&ddr->sdram_mode, regs->ddr_sdram_mode);
+	ddr_out32(&ddr->sdram_mode_2, regs->ddr_sdram_mode_2);
+	ddr_out32(&ddr->sdram_mode_3, regs->ddr_sdram_mode_3);
+	ddr_out32(&ddr->sdram_mode_4, regs->ddr_sdram_mode_4);
+	ddr_out32(&ddr->sdram_mode_5, regs->ddr_sdram_mode_5);
+	ddr_out32(&ddr->sdram_mode_6, regs->ddr_sdram_mode_6);
+	ddr_out32(&ddr->sdram_mode_7, regs->ddr_sdram_mode_7);
+	ddr_out32(&ddr->sdram_mode_8, regs->ddr_sdram_mode_8);
+	ddr_out32(&ddr->sdram_md_cntl, regs->ddr_sdram_md_cntl);
+	ddr_out32(&ddr->sdram_interval, regs->ddr_sdram_interval);
+	ddr_out32(&ddr->sdram_data_init, regs->ddr_data_init);
+	ddr_out32(&ddr->sdram_clk_cntl, regs->ddr_sdram_clk_cntl);
+	ddr_out32(&ddr->init_addr, regs->ddr_init_addr);
+	ddr_out32(&ddr->init_ext_addr, regs->ddr_init_ext_addr);
+
+	ddr_out32(&ddr->timing_cfg_4, regs->timing_cfg_4);
+	ddr_out32(&ddr->timing_cfg_5, regs->timing_cfg_5);
+	ddr_out32(&ddr->ddr_zq_cntl, regs->ddr_zq_cntl);
+	ddr_out32(&ddr->ddr_wrlvl_cntl, regs->ddr_wrlvl_cntl);
+#ifndef CONFIG_SYS_FSL_DDR_EMU
+	/*
+	 * Skip these two registers if running on emulator
+	 * because emulator doesn't have skew between bytes.
+	 */
+
+	if (regs->ddr_wrlvl_cntl_2)
+		ddr_out32(&ddr->ddr_wrlvl_cntl_2, regs->ddr_wrlvl_cntl_2);
+	if (regs->ddr_wrlvl_cntl_3)
+		ddr_out32(&ddr->ddr_wrlvl_cntl_3, regs->ddr_wrlvl_cntl_3);
+#endif
+
+	ddr_out32(&ddr->ddr_sr_cntr, regs->ddr_sr_cntr);
+	ddr_out32(&ddr->ddr_sdram_rcw_1, regs->ddr_sdram_rcw_1);
+	ddr_out32(&ddr->ddr_sdram_rcw_2, regs->ddr_sdram_rcw_2);
+	ddr_out32(&ddr->ddr_cdr1, regs->ddr_cdr1);
+	ddr_out32(&ddr->ddr_cdr2, regs->ddr_cdr2);
+	ddr_out32(&ddr->err_disable, regs->err_disable);
+	ddr_out32(&ddr->err_int_en, regs->err_int_en);
+	for (i = 0; i < 32; i++) {
+		if (regs->debug[i]) {
+			debug("Write to debug_%d as %08x\n", i + 1,
+			      regs->debug[i]);
+			ddr_out32(&ddr->debug[i], regs->debug[i]);
+		}
+	}
+
+	/*
+	 * For RDIMMs, JEDEC spec requires clocks to be stable before reset is
+	 * deasserted. Clocks start when any chip select is enabled and clock
+	 * control register is set. Because all DDR components are connected to
+	 * one reset signal, this needs to be done in two steps. Step 1 is to
+	 * get the clocks started. Step 2 resumes after reset signal is
+	 * deasserted.
+	 */
+	if (step == 1) {
+		udelay(200);
+		return;
+	}
+
+step2:
+	/* Set, but do not enable the memory */
+	temp_sdram_cfg = regs->ddr_sdram_cfg;
+	temp_sdram_cfg &= ~(SDRAM_CFG_MEM_EN);
+	ddr_out32(&ddr->sdram_cfg, temp_sdram_cfg);
+
+	/*
+	 * 500 painful micro-seconds must elapse between
+	 * the DDR clock setup and the DDR config enable.
+	 * DDR2 need 200 us, and DDR3 need 500 us from spec,
+	 * we choose the max, that is 500 us for all of case.
+	 */
+	udelay(500);
+	asm volatile("dsb sy;isb");
+
+	/* Let the controller go */
+	temp_sdram_cfg = ddr_in32(&ddr->sdram_cfg) & ~SDRAM_CFG_BI;
+	ddr_out32(&ddr->sdram_cfg, temp_sdram_cfg | SDRAM_CFG_MEM_EN);
+	asm volatile("dsb sy;isb");
+
+	total_gb_size_per_controller = 0;
+	for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
+		if (!(regs->cs[i].config & 0x80000000))
+			continue;
+		total_gb_size_per_controller += 1 << (
+			((regs->cs[i].config >> 14) & 0x3) + 2 +
+			((regs->cs[i].config >> 8) & 0x7) + 12 +
+			((regs->cs[i].config >> 0) & 0x7) + 8 +
+			3 - ((regs->ddr_sdram_cfg >> 19) & 0x3) -
+			26);			/* minus 26 (count of 64M) */
+	}
+	if (regs->cs[0].config & 0x20000000) {
+		/* 2-way interleaving */
+		total_gb_size_per_controller <<= 1;
+	}
+	/*
+	 * total memory / bus width = transactions needed
+	 * transactions needed / data rate = seconds
+	 * to add plenty of buffer, double the time
+	 * For example, 2GB on 666MT/s 64-bit bus takes about 402ms
+	 * Let's wait for 800ms
+	 */
+	bus_width = 3 - ((ddr->sdram_cfg & SDRAM_CFG_DBW_MASK)
+			>> SDRAM_CFG_DBW_SHIFT);
+	timeout = ((total_gb_size_per_controller << (6 - bus_width)) * 100 /
+		(get_ddr_freq(0) >> 20)) << 1;
+	total_gb_size_per_controller >>= 4;	/* shift down to gb size */
+	debug("total %d GB\n", total_gb_size_per_controller);
+	debug("Need to wait up to %d * 10ms\n", timeout);
+
+	/* Poll DDR_SDRAM_CFG_2[D_INIT] bit until auto-data init is done.  */
+	while ((ddr_in32(&ddr->sdram_cfg_2) & SDRAM_CFG2_D_INIT) &&
+		(timeout >= 0)) {
+		udelay(10000);		/* throttle polling rate */
+		timeout--;
+	}
+
+	if (timeout <= 0)
+		printf("Waiting for D_INIT timeout. Memory may not work.\n");
+}
diff --git a/drivers/ddr/fsl/ctrl_regs.c b/drivers/ddr/fsl/ctrl_regs.c
new file mode 100644
index 0000000000..0882932b07
--- /dev/null
+++ b/drivers/ddr/fsl/ctrl_regs.c
@@ -0,0 +1,1663 @@
+/*
+ * Copyright 2008-2012 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * Generic driver for Freescale DDR/DDR2/DDR3 memory controller.
+ * Based on code from spd_sdram.c
+ * Author: James Yang [at freescale.com]
+ */
+
+#include <common.h>
+#include <fsl_ddr_sdram.h>
+
+#include <fsl_ddr.h>
+#include <fsl_immap.h>
+#include <asm/io.h>
+
+#define _DDR_ADDR CONFIG_SYS_FSL_DDR_ADDR
+
+static u32 fsl_ddr_get_version(void)
+{
+	struct ccsr_ddr __iomem *ddr;
+	u32 ver_major_minor_errata;
+
+	ddr = (void *)_DDR_ADDR;
+	ver_major_minor_errata = (ddr_in32(&ddr->ip_rev1) & 0xFFFF) << 8;
+	ver_major_minor_errata |= (ddr_in32(&ddr->ip_rev2) & 0xFF00) >> 8;
+
+	return ver_major_minor_errata;
+}
+
+unsigned int picos_to_mclk(unsigned int picos);
+
+/*
+ * Determine Rtt value.
+ *
+ * This should likely be either board or controller specific.
+ *
+ * Rtt(nominal) - DDR2:
+ *	0 = Rtt disabled
+ *	1 = 75 ohm
+ *	2 = 150 ohm
+ *	3 = 50 ohm
+ * Rtt(nominal) - DDR3:
+ *	0 = Rtt disabled
+ *	1 = 60 ohm
+ *	2 = 120 ohm
+ *	3 = 40 ohm
+ *	4 = 20 ohm
+ *	5 = 30 ohm
+ *
+ * FIXME: Apparently 8641 needs a value of 2
+ * FIXME: Old code seys if 667 MHz or higher, use 3 on 8572
+ *
+ * FIXME: There was some effort down this line earlier:
+ *
+ *	unsigned int i;
+ *	for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL/2; i++) {
+ *		if (popts->dimmslot[i].num_valid_cs
+ *		    && (popts->cs_local_opts[2*i].odt_rd_cfg
+ *			|| popts->cs_local_opts[2*i].odt_wr_cfg)) {
+ *			rtt = 2;
+ *			break;
+ *		}
+ *	}
+ */
+static inline int fsl_ddr_get_rtt(void)
+{
+	int rtt;
+
+#if defined(CONFIG_SYS_FSL_DDR1)
+	rtt = 0;
+#elif defined(CONFIG_SYS_FSL_DDR2)
+	rtt = 3;
+#else
+	rtt = 0;
+#endif
+
+	return rtt;
+}
+
+/*
+ * compute the CAS write latency according to DDR3 spec
+ * CWL = 5 if tCK >= 2.5ns
+ *       6 if 2.5ns > tCK >= 1.875ns
+ *       7 if 1.875ns > tCK >= 1.5ns
+ *       8 if 1.5ns > tCK >= 1.25ns
+ *       9 if 1.25ns > tCK >= 1.07ns
+ *       10 if 1.07ns > tCK >= 0.935ns
+ *       11 if 0.935ns > tCK >= 0.833ns
+ *       12 if 0.833ns > tCK >= 0.75ns
+ */
+static inline unsigned int compute_cas_write_latency(void)
+{
+	unsigned int cwl;
+	const unsigned int mclk_ps = get_memory_clk_period_ps();
+
+	if (mclk_ps >= 2500)
+		cwl = 5;
+	else if (mclk_ps >= 1875)
+		cwl = 6;
+	else if (mclk_ps >= 1500)
+		cwl = 7;
+	else if (mclk_ps >= 1250)
+		cwl = 8;
+	else if (mclk_ps >= 1070)
+		cwl = 9;
+	else if (mclk_ps >= 935)
+		cwl = 10;
+	else if (mclk_ps >= 833)
+		cwl = 11;
+	else if (mclk_ps >= 750)
+		cwl = 12;
+	else {
+		cwl = 12;
+		printf("Warning: CWL is out of range\n");
+	}
+	return cwl;
+}
+
+/* Chip Select Configuration (CSn_CONFIG) */
+static void set_csn_config(int dimm_number, int i, fsl_ddr_cfg_regs_t *ddr,
+			       const memctl_options_t *popts,
+			       const dimm_params_t *dimm_params)
+{
+	unsigned int cs_n_en = 0; /* Chip Select enable */
+	unsigned int intlv_en = 0; /* Memory controller interleave enable */
+	unsigned int intlv_ctl = 0; /* Interleaving control */
+	unsigned int ap_n_en = 0; /* Chip select n auto-precharge enable */
+	unsigned int odt_rd_cfg = 0; /* ODT for reads configuration */
+	unsigned int odt_wr_cfg = 0; /* ODT for writes configuration */
+	unsigned int ba_bits_cs_n = 0; /* Num of bank bits for SDRAM on CSn */
+	unsigned int row_bits_cs_n = 0; /* Num of row bits for SDRAM on CSn */
+	unsigned int col_bits_cs_n = 0; /* Num of ocl bits for SDRAM on CSn */
+	int go_config = 0;
+
+	/* Compute CS_CONFIG only for existing ranks of each DIMM.  */
+	switch (i) {
+	case 0:
+		if (dimm_params[dimm_number].n_ranks > 0) {
+			go_config = 1;
+			/* These fields only available in CS0_CONFIG */
+			if (!popts->memctl_interleaving)
+				break;
+			switch (popts->memctl_interleaving_mode) {
+			case FSL_DDR_256B_INTERLEAVING:
+			case FSL_DDR_CACHE_LINE_INTERLEAVING:
+			case FSL_DDR_PAGE_INTERLEAVING:
+			case FSL_DDR_BANK_INTERLEAVING:
+			case FSL_DDR_SUPERBANK_INTERLEAVING:
+				intlv_en = popts->memctl_interleaving;
+				intlv_ctl = popts->memctl_interleaving_mode;
+				break;
+			default:
+				break;
+			}
+		}
+		break;
+	case 1:
+		if ((dimm_number == 0 && dimm_params[0].n_ranks > 1) || \
+		    (dimm_number == 1 && dimm_params[1].n_ranks > 0))
+			go_config = 1;
+		break;
+	case 2:
+		if ((dimm_number == 0 && dimm_params[0].n_ranks > 2) || \
+		   (dimm_number >= 1 && dimm_params[dimm_number].n_ranks > 0))
+			go_config = 1;
+		break;
+	case 3:
+		if ((dimm_number == 0 && dimm_params[0].n_ranks > 3) || \
+		    (dimm_number == 1 && dimm_params[1].n_ranks > 1) || \
+		    (dimm_number == 3 && dimm_params[3].n_ranks > 0))
+			go_config = 1;
+		break;
+	default:
+		break;
+	}
+	if (go_config) {
+		unsigned int n_banks_per_sdram_device;
+		cs_n_en = 1;
+		ap_n_en = popts->cs_local_opts[i].auto_precharge;
+		odt_rd_cfg = popts->cs_local_opts[i].odt_rd_cfg;
+		odt_wr_cfg = popts->cs_local_opts[i].odt_wr_cfg;
+		n_banks_per_sdram_device
+			= dimm_params[dimm_number].n_banks_per_sdram_device;
+		ba_bits_cs_n = __ilog2(n_banks_per_sdram_device) - 2;
+		row_bits_cs_n = dimm_params[dimm_number].n_row_addr - 12;
+		col_bits_cs_n = dimm_params[dimm_number].n_col_addr - 8;
+	}
+	ddr->cs[i].config = (0
+		| ((cs_n_en & 0x1) << 31)
+		| ((intlv_en & 0x3) << 29)
+		| ((intlv_ctl & 0xf) << 24)
+		| ((ap_n_en & 0x1) << 23)
+
+		/* XXX: some implementation only have 1 bit starting at left */
+		| ((odt_rd_cfg & 0x7) << 20)
+
+		/* XXX: Some implementation only have 1 bit starting at left */
+		| ((odt_wr_cfg & 0x7) << 16)
+
+		| ((ba_bits_cs_n & 0x3) << 14)
+		| ((row_bits_cs_n & 0x7) << 8)
+		| ((col_bits_cs_n & 0x7) << 0)
+		);
+	debug("FSLDDR: cs[%d]_config = 0x%08x\n", i,ddr->cs[i].config);
+}
+
+/* Chip Select Configuration 2 (CSn_CONFIG_2) */
+/* FIXME: 8572 */
+static void set_csn_config_2(int i, fsl_ddr_cfg_regs_t *ddr)
+{
+	unsigned int pasr_cfg = 0;	/* Partial array self refresh config */
+
+	ddr->cs[i].config_2 = ((pasr_cfg & 7) << 24);
+	debug("FSLDDR: cs[%d]_config_2 = 0x%08x\n", i, ddr->cs[i].config_2);
+}
+
+/* -3E = 667 CL5, -25 = CL6 800, -25E = CL5 800 */
+
+#if !defined(CONFIG_SYS_FSL_DDR1)
+static inline int avoid_odt_overlap(const dimm_params_t *dimm_params)
+{
+#if CONFIG_DIMM_SLOTS_PER_CTLR == 1
+	if (dimm_params[0].n_ranks == 4)
+		return 1;
+#endif
+
+#if CONFIG_DIMM_SLOTS_PER_CTLR == 2
+	if ((dimm_params[0].n_ranks == 2) &&
+		(dimm_params[1].n_ranks == 2))
+		return 1;
+
+#ifdef CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
+	if (dimm_params[0].n_ranks == 4)
+		return 1;
+#endif
+#endif
+	return 0;
+}
+
+/*
+ * DDR SDRAM Timing Configuration 0 (TIMING_CFG_0)
+ *
+ * Avoid writing for DDR I.  The new PQ38 DDR controller
+ * dreams up non-zero default values to be backwards compatible.
+ */
+static void set_timing_cfg_0(fsl_ddr_cfg_regs_t *ddr,
+				const memctl_options_t *popts,
+				const dimm_params_t *dimm_params)
+{
+	unsigned char trwt_mclk = 0;   /* Read-to-write turnaround */
+	unsigned char twrt_mclk = 0;   /* Write-to-read turnaround */
+	/* 7.5 ns on -3E; 0 means WL - CL + BL/2 + 1 */
+	unsigned char trrt_mclk = 0;   /* Read-to-read turnaround */
+	unsigned char twwt_mclk = 0;   /* Write-to-write turnaround */
+
+	/* Active powerdown exit timing (tXARD and tXARDS). */
+	unsigned char act_pd_exit_mclk;
+	/* Precharge powerdown exit timing (tXP). */
+	unsigned char pre_pd_exit_mclk;
+	/* ODT powerdown exit timing (tAXPD). */
+	unsigned char taxpd_mclk;
+	/* Mode register set cycle time (tMRD). */
+	unsigned char tmrd_mclk;
+
+#ifdef CONFIG_SYS_FSL_DDR3
+	/*
+	 * (tXARD and tXARDS). Empirical?
+	 * The DDR3 spec has not tXARD,
+	 * we use the tXP instead of it.
+	 * tXP=max(3nCK, 7.5ns) for DDR3.
+	 * spec has not the tAXPD, we use
+	 * tAXPD=1, need design to confirm.
+	 */
+	int tXP = max((get_memory_clk_period_ps() * 3), 7500); /* unit=ps */
+	unsigned int data_rate = get_ddr_freq(0);
+	tmrd_mclk = 4;
+	/* set the turnaround time */
+
+	/*
+	 * for single quad-rank DIMM and two dual-rank DIMMs
+	 * to avoid ODT overlap
+	 */
+	if (avoid_odt_overlap(dimm_params)) {
+		twwt_mclk = 2;
+		trrt_mclk = 1;
+	}
+	/* for faster clock, need more time for data setup */
+	trwt_mclk = (data_rate/1000000 > 1800) ? 2 : 1;
+
+	if ((data_rate/1000000 > 1150) || (popts->memctl_interleaving))
+		twrt_mclk = 1;
+
+	if (popts->dynamic_power == 0) {	/* powerdown is not used */
+		act_pd_exit_mclk = 1;
+		pre_pd_exit_mclk = 1;
+		taxpd_mclk = 1;
+	} else {
+		/* act_pd_exit_mclk = tXARD, see above */
+		act_pd_exit_mclk = picos_to_mclk(tXP);
+		/* Mode register MR0[A12] is '1' - fast exit */
+		pre_pd_exit_mclk = act_pd_exit_mclk;
+		taxpd_mclk = 1;
+	}
+#else /* CONFIG_SYS_FSL_DDR2 */
+	/*
+	 * (tXARD and tXARDS). Empirical?
+	 * tXARD = 2 for DDR2
+	 * tXP=2
+	 * tAXPD=8
+	 */
+	act_pd_exit_mclk = 2;
+	pre_pd_exit_mclk = 2;
+	taxpd_mclk = 8;
+	tmrd_mclk = 2;
+#endif
+
+	if (popts->trwt_override)
+		trwt_mclk = popts->trwt;
+
+	ddr->timing_cfg_0 = (0
+		| ((trwt_mclk & 0x3) << 30)	/* RWT */
+		| ((twrt_mclk & 0x3) << 28)	/* WRT */
+		| ((trrt_mclk & 0x3) << 26)	/* RRT */
+		| ((twwt_mclk & 0x3) << 24)	/* WWT */
+		| ((act_pd_exit_mclk & 0xf) << 20)  /* ACT_PD_EXIT */
+		| ((pre_pd_exit_mclk & 0xF) << 16)  /* PRE_PD_EXIT */
+		| ((taxpd_mclk & 0xf) << 8)	/* ODT_PD_EXIT */
+		| ((tmrd_mclk & 0x1f) << 0)	/* MRS_CYC */
+		);
+	debug("FSLDDR: timing_cfg_0 = 0x%08x\n", ddr->timing_cfg_0);
+}
+#endif	/* defined(CONFIG_SYS_FSL_DDR2) */
+
+/* DDR SDRAM Timing Configuration 3 (TIMING_CFG_3) */
+static void set_timing_cfg_3(fsl_ddr_cfg_regs_t *ddr,
+			       const memctl_options_t *popts,
+			       const common_timing_params_t *common_dimm,
+			       unsigned int cas_latency,
+			       unsigned int additive_latency)
+{
+	/* Extended precharge to activate interval (tRP) */
+	unsigned int ext_pretoact = 0;
+	/* Extended Activate to precharge interval (tRAS) */
+	unsigned int ext_acttopre = 0;
+	/* Extended activate to read/write interval (tRCD) */
+	unsigned int ext_acttorw = 0;
+	/* Extended refresh recovery time (tRFC) */
+	unsigned int ext_refrec;
+	/* Extended MCAS latency from READ cmd */
+	unsigned int ext_caslat = 0;
+	/* Extended additive latency */
+	unsigned int ext_add_lat = 0;
+	/* Extended last data to precharge interval (tWR) */
+	unsigned int ext_wrrec = 0;
+	/* Control Adjust */
+	unsigned int cntl_adj = 0;
+
+	ext_pretoact = picos_to_mclk(common_dimm->trp_ps) >> 4;
+	ext_acttopre = picos_to_mclk(common_dimm->tras_ps) >> 4;
+	ext_acttorw = picos_to_mclk(common_dimm->trcd_ps) >> 4;
+	ext_caslat = (2 * cas_latency - 1) >> 4;
+	ext_add_lat = additive_latency >> 4;
+	ext_refrec = (picos_to_mclk(common_dimm->trfc_ps) - 8) >> 4;
+	/* ext_wrrec only deals with 16 clock and above, or 14 with OTF */
+	ext_wrrec = (picos_to_mclk(common_dimm->twr_ps) +
+		(popts->otf_burst_chop_en ? 2 : 0)) >> 4;
+
+	ddr->timing_cfg_3 = (0
+		| ((ext_pretoact & 0x1) << 28)
+		| ((ext_acttopre & 0x3) << 24)
+		| ((ext_acttorw & 0x1) << 22)
+		| ((ext_refrec & 0x1F) << 16)
+		| ((ext_caslat & 0x3) << 12)
+		| ((ext_add_lat & 0x1) << 10)
+		| ((ext_wrrec & 0x1) << 8)
+		| ((cntl_adj & 0x7) << 0)
+		);
+	debug("FSLDDR: timing_cfg_3 = 0x%08x\n", ddr->timing_cfg_3);
+}
+
+/* DDR SDRAM Timing Configuration 1 (TIMING_CFG_1) */
+static void set_timing_cfg_1(fsl_ddr_cfg_regs_t *ddr,
+			       const memctl_options_t *popts,
+			       const common_timing_params_t *common_dimm,
+			       unsigned int cas_latency)
+{
+	/* Precharge-to-activate interval (tRP) */
+	unsigned char pretoact_mclk;
+	/* Activate to precharge interval (tRAS) */
+	unsigned char acttopre_mclk;
+	/*  Activate to read/write interval (tRCD) */
+	unsigned char acttorw_mclk;
+	/* CASLAT */
+	unsigned char caslat_ctrl;
+	/*  Refresh recovery time (tRFC) ; trfc_low */
+	unsigned char refrec_ctrl;
+	/* Last data to precharge minimum interval (tWR) */
+	unsigned char wrrec_mclk;
+	/* Activate-to-activate interval (tRRD) */
+	unsigned char acttoact_mclk;
+	/* Last write data pair to read command issue interval (tWTR) */
+	unsigned char wrtord_mclk;
+	/* DDR_SDRAM_MODE doesn't support 9,11,13,15 */
+	static const u8 wrrec_table[] = {
+		1, 2, 3, 4, 5, 6, 7, 8, 10, 10, 12, 12, 14, 14, 0, 0};
+
+	pretoact_mclk = picos_to_mclk(common_dimm->trp_ps);
+	acttopre_mclk = picos_to_mclk(common_dimm->tras_ps);
+	acttorw_mclk = picos_to_mclk(common_dimm->trcd_ps);
+
+	/*
+	 * Translate CAS Latency to a DDR controller field value:
+	 *
+	 *      CAS Lat DDR I   DDR II  Ctrl
+	 *      Clocks  SPD Bit SPD Bit Value
+	 *      ------- ------- ------- -----
+	 *      1.0     0               0001
+	 *      1.5     1               0010
+	 *      2.0     2       2       0011
+	 *      2.5     3               0100
+	 *      3.0     4       3       0101
+	 *      3.5     5               0110
+	 *      4.0             4       0111
+	 *      4.5                     1000
+	 *      5.0             5       1001
+	 */
+#if defined(CONFIG_SYS_FSL_DDR1)
+	caslat_ctrl = (cas_latency + 1) & 0x07;
+#elif defined(CONFIG_SYS_FSL_DDR2)
+	caslat_ctrl = 2 * cas_latency - 1;
+#else
+	/*
+	 * if the CAS latency more than 8 cycle,
+	 * we need set extend bit for it at
+	 * TIMING_CFG_3[EXT_CASLAT]
+	 */
+	caslat_ctrl = 2 * cas_latency - 1;
+#endif
+
+	refrec_ctrl = picos_to_mclk(common_dimm->trfc_ps) - 8;
+	wrrec_mclk = picos_to_mclk(common_dimm->twr_ps);
+
+	if (wrrec_mclk > 16)
+		printf("Error: WRREC doesn't support more than 16 clocks\n");
+	else
+		wrrec_mclk = wrrec_table[wrrec_mclk - 1];
+	if (popts->otf_burst_chop_en)
+		wrrec_mclk += 2;
+
+	acttoact_mclk = picos_to_mclk(common_dimm->trrd_ps);
+	/*
+	 * JEDEC has min requirement for tRRD
+	 */
+#if defined(CONFIG_SYS_FSL_DDR3)
+	if (acttoact_mclk < 4)
+		acttoact_mclk = 4;
+#endif
+	wrtord_mclk = picos_to_mclk(common_dimm->twtr_ps);
+	/*
+	 * JEDEC has some min requirements for tWTR
+	 */
+#if defined(CONFIG_SYS_FSL_DDR2)
+	if (wrtord_mclk < 2)
+		wrtord_mclk = 2;
+#elif defined(CONFIG_SYS_FSL_DDR3)
+	if (wrtord_mclk < 4)
+		wrtord_mclk = 4;
+#endif
+	if (popts->otf_burst_chop_en)
+		wrtord_mclk += 2;
+
+	ddr->timing_cfg_1 = (0
+		| ((pretoact_mclk & 0x0F) << 28)
+		| ((acttopre_mclk & 0x0F) << 24)
+		| ((acttorw_mclk & 0xF) << 20)
+		| ((caslat_ctrl & 0xF) << 16)
+		| ((refrec_ctrl & 0xF) << 12)
+		| ((wrrec_mclk & 0x0F) << 8)
+		| ((acttoact_mclk & 0x0F) << 4)
+		| ((wrtord_mclk & 0x0F) << 0)
+		);
+	debug("FSLDDR: timing_cfg_1 = 0x%08x\n", ddr->timing_cfg_1);
+}
+
+/* DDR SDRAM Timing Configuration 2 (TIMING_CFG_2) */
+static void set_timing_cfg_2(fsl_ddr_cfg_regs_t *ddr,
+			       const memctl_options_t *popts,
+			       const common_timing_params_t *common_dimm,
+			       unsigned int cas_latency,
+			       unsigned int additive_latency)
+{
+	/* Additive latency */
+	unsigned char add_lat_mclk;
+	/* CAS-to-preamble override */
+	unsigned short cpo;
+	/* Write latency */
+	unsigned char wr_lat;
+	/*  Read to precharge (tRTP) */
+	unsigned char rd_to_pre;
+	/* Write command to write data strobe timing adjustment */
+	unsigned char wr_data_delay;
+	/* Minimum CKE pulse width (tCKE) */
+	unsigned char cke_pls;
+	/* Window for four activates (tFAW) */
+	unsigned short four_act;
+
+	/* FIXME add check that this must be less than acttorw_mclk */
+	add_lat_mclk = additive_latency;
+	cpo = popts->cpo_override;
+
+#if defined(CONFIG_SYS_FSL_DDR1)
+	/*
+	 * This is a lie.  It should really be 1, but if it is
+	 * set to 1, bits overlap into the old controller's
+	 * otherwise unused ACSM field.  If we leave it 0, then
+	 * the HW will magically treat it as 1 for DDR 1.  Oh Yea.
+	 */
+	wr_lat = 0;
+#elif defined(CONFIG_SYS_FSL_DDR2)
+	wr_lat = cas_latency - 1;
+#else
+	wr_lat = compute_cas_write_latency();
+#endif
+
+	rd_to_pre = picos_to_mclk(common_dimm->trtp_ps);
+	/*
+	 * JEDEC has some min requirements for tRTP
+	 */
+#if defined(CONFIG_SYS_FSL_DDR2)
+	if (rd_to_pre  < 2)
+		rd_to_pre  = 2;
+#elif defined(CONFIG_SYS_FSL_DDR3)
+	if (rd_to_pre < 4)
+		rd_to_pre = 4;
+#endif
+	if (popts->otf_burst_chop_en)
+		rd_to_pre += 2; /* according to UM */
+
+	wr_data_delay = popts->write_data_delay;
+	cke_pls = picos_to_mclk(popts->tcke_clock_pulse_width_ps);
+	four_act = picos_to_mclk(popts->tfaw_window_four_activates_ps);
+
+	ddr->timing_cfg_2 = (0
+		| ((add_lat_mclk & 0xf) << 28)
+		| ((cpo & 0x1f) << 23)
+		| ((wr_lat & 0xf) << 19)
+		| ((rd_to_pre & RD_TO_PRE_MASK) << RD_TO_PRE_SHIFT)
+		| ((wr_data_delay & WR_DATA_DELAY_MASK) << WR_DATA_DELAY_SHIFT)
+		| ((cke_pls & 0x7) << 6)
+		| ((four_act & 0x3f) << 0)
+		);
+	debug("FSLDDR: timing_cfg_2 = 0x%08x\n", ddr->timing_cfg_2);
+}
+
+/* DDR SDRAM Register Control Word */
+static void set_ddr_sdram_rcw(fsl_ddr_cfg_regs_t *ddr,
+			       const memctl_options_t *popts,
+			       const common_timing_params_t *common_dimm)
+{
+	if (common_dimm->all_dimms_registered &&
+	    !common_dimm->all_dimms_unbuffered)	{
+		if (popts->rcw_override) {
+			ddr->ddr_sdram_rcw_1 = popts->rcw_1;
+			ddr->ddr_sdram_rcw_2 = popts->rcw_2;
+		} else {
+			ddr->ddr_sdram_rcw_1 =
+				common_dimm->rcw[0] << 28 | \
+				common_dimm->rcw[1] << 24 | \
+				common_dimm->rcw[2] << 20 | \
+				common_dimm->rcw[3] << 16 | \
+				common_dimm->rcw[4] << 12 | \
+				common_dimm->rcw[5] << 8 | \
+				common_dimm->rcw[6] << 4 | \
+				common_dimm->rcw[7];
+			ddr->ddr_sdram_rcw_2 =
+				common_dimm->rcw[8] << 28 | \
+				common_dimm->rcw[9] << 24 | \
+				common_dimm->rcw[10] << 20 | \
+				common_dimm->rcw[11] << 16 | \
+				common_dimm->rcw[12] << 12 | \
+				common_dimm->rcw[13] << 8 | \
+				common_dimm->rcw[14] << 4 | \
+				common_dimm->rcw[15];
+		}
+		debug("FSLDDR: ddr_sdram_rcw_1 = 0x%08x\n", ddr->ddr_sdram_rcw_1);
+		debug("FSLDDR: ddr_sdram_rcw_2 = 0x%08x\n", ddr->ddr_sdram_rcw_2);
+	}
+}
+
+/* DDR SDRAM control configuration (DDR_SDRAM_CFG) */
+static void set_ddr_sdram_cfg(fsl_ddr_cfg_regs_t *ddr,
+			       const memctl_options_t *popts,
+			       const common_timing_params_t *common_dimm)
+{
+	unsigned int mem_en;		/* DDR SDRAM interface logic enable */
+	unsigned int sren;		/* Self refresh enable (during sleep) */
+	unsigned int ecc_en;		/* ECC enable. */
+	unsigned int rd_en;		/* Registered DIMM enable */
+	unsigned int sdram_type;	/* Type of SDRAM */
+	unsigned int dyn_pwr;		/* Dynamic power management mode */
+	unsigned int dbw;		/* DRAM dta bus width */
+	unsigned int eight_be = 0;	/* 8-beat burst enable, DDR2 is zero */
+	unsigned int ncap = 0;		/* Non-concurrent auto-precharge */
+	unsigned int threet_en;		/* Enable 3T timing */
+	unsigned int twot_en;		/* Enable 2T timing */
+	unsigned int ba_intlv_ctl;	/* Bank (CS) interleaving control */
+	unsigned int x32_en = 0;	/* x32 enable */
+	unsigned int pchb8 = 0;		/* precharge bit 8 enable */
+	unsigned int hse;		/* Global half strength override */
+	unsigned int mem_halt = 0;	/* memory controller halt */
+	unsigned int bi = 0;		/* Bypass initialization */
+
+	mem_en = 1;
+	sren = popts->self_refresh_in_sleep;
+	if (common_dimm->all_dimms_ecc_capable) {
+		/* Allow setting of ECC only if all DIMMs are ECC. */
+		ecc_en = popts->ecc_mode;
+	} else {
+		ecc_en = 0;
+	}
+
+	if (common_dimm->all_dimms_registered &&
+	    !common_dimm->all_dimms_unbuffered)	{
+		rd_en = 1;
+		twot_en = 0;
+	} else {
+		rd_en = 0;
+		twot_en = popts->twot_en;
+	}
+
+	sdram_type = CONFIG_FSL_SDRAM_TYPE;
+
+	dyn_pwr = popts->dynamic_power;
+	dbw = popts->data_bus_width;
+	/* 8-beat burst enable DDR-III case
+	 * we must clear it when use the on-the-fly mode,
+	 * must set it when use the 32-bits bus mode.
+	 */
+	if (sdram_type == SDRAM_TYPE_DDR3) {
+		if (popts->burst_length == DDR_BL8)
+			eight_be = 1;
+		if (popts->burst_length == DDR_OTF)
+			eight_be = 0;
+		if (dbw == 0x1)
+			eight_be = 1;
+	}
+
+	threet_en = popts->threet_en;
+	ba_intlv_ctl = popts->ba_intlv_ctl;
+	hse = popts->half_strength_driver_enable;
+
+	ddr->ddr_sdram_cfg = (0
+			| ((mem_en & 0x1) << 31)
+			| ((sren & 0x1) << 30)
+			| ((ecc_en & 0x1) << 29)
+			| ((rd_en & 0x1) << 28)
+			| ((sdram_type & 0x7) << 24)
+			| ((dyn_pwr & 0x1) << 21)
+			| ((dbw & 0x3) << 19)
+			| ((eight_be & 0x1) << 18)
+			| ((ncap & 0x1) << 17)
+			| ((threet_en & 0x1) << 16)
+			| ((twot_en & 0x1) << 15)
+			| ((ba_intlv_ctl & 0x7F) << 8)
+			| ((x32_en & 0x1) << 5)
+			| ((pchb8 & 0x1) << 4)
+			| ((hse & 0x1) << 3)
+			| ((mem_halt & 0x1) << 1)
+			| ((bi & 0x1) << 0)
+			);
+	debug("FSLDDR: ddr_sdram_cfg = 0x%08x\n", ddr->ddr_sdram_cfg);
+}
+
+/* DDR SDRAM control configuration 2 (DDR_SDRAM_CFG_2) */
+static void set_ddr_sdram_cfg_2(fsl_ddr_cfg_regs_t *ddr,
+			       const memctl_options_t *popts,
+			       const unsigned int unq_mrs_en)
+{
+	unsigned int frc_sr = 0;	/* Force self refresh */
+	unsigned int sr_ie = 0;		/* Self-refresh interrupt enable */
+	unsigned int dll_rst_dis;	/* DLL reset disable */
+	unsigned int dqs_cfg;		/* DQS configuration */
+	unsigned int odt_cfg = 0;	/* ODT configuration */
+	unsigned int num_pr;		/* Number of posted refreshes */
+	unsigned int slow = 0;		/* DDR will be run less than 1250 */
+	unsigned int x4_en = 0;		/* x4 DRAM enable */
+	unsigned int obc_cfg;		/* On-The-Fly Burst Chop Cfg */
+	unsigned int ap_en;		/* Address Parity Enable */
+	unsigned int d_init;		/* DRAM data initialization */
+	unsigned int rcw_en = 0;	/* Register Control Word Enable */
+	unsigned int md_en = 0;		/* Mirrored DIMM Enable */
+	unsigned int qd_en = 0;		/* quad-rank DIMM Enable */
+	int i;
+
+	dll_rst_dis = 1;	/* Make this configurable */
+	dqs_cfg = popts->dqs_config;
+	for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
+		if (popts->cs_local_opts[i].odt_rd_cfg
+			|| popts->cs_local_opts[i].odt_wr_cfg) {
+			odt_cfg = SDRAM_CFG2_ODT_ONLY_READ;
+			break;
+		}
+	}
+
+	num_pr = 1;	/* Make this configurable */
+
+	/*
+	 * 8572 manual says
+	 *     {TIMING_CFG_1[PRETOACT]
+	 *      + [DDR_SDRAM_CFG_2[NUM_PR]
+	 *        * ({EXT_REFREC || REFREC} + 8 + 2)]}
+	 *      << DDR_SDRAM_INTERVAL[REFINT]
+	 */
+#if defined(CONFIG_SYS_FSL_DDR3)
+	obc_cfg = popts->otf_burst_chop_en;
+#else
+	obc_cfg = 0;
+#endif
+
+#if (CONFIG_SYS_FSL_DDR_VER >= FSL_DDR_VER_4_7)
+	slow = get_ddr_freq(0) < 1249000000;
+#endif
+
+	if (popts->registered_dimm_en) {
+		rcw_en = 1;
+		ap_en = popts->ap_en;
+	} else {
+		ap_en = 0;
+	}
+
+	x4_en = popts->x4_en ? 1 : 0;
+
+#if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
+	/* Use the DDR controller to auto initialize memory. */
+	d_init = popts->ecc_init_using_memctl;
+	ddr->ddr_data_init = CONFIG_MEM_INIT_VALUE;
+	debug("DDR: ddr_data_init = 0x%08x\n", ddr->ddr_data_init);
+#else
+	/* Memory will be initialized via DMA, or not at all. */
+	d_init = 0;
+#endif
+
+#if defined(CONFIG_SYS_FSL_DDR3)
+	md_en = popts->mirrored_dimm;
+#endif
+	qd_en = popts->quad_rank_present ? 1 : 0;
+	ddr->ddr_sdram_cfg_2 = (0
+		| ((frc_sr & 0x1) << 31)
+		| ((sr_ie & 0x1) << 30)
+		| ((dll_rst_dis & 0x1) << 29)
+		| ((dqs_cfg & 0x3) << 26)
+		| ((odt_cfg & 0x3) << 21)
+		| ((num_pr & 0xf) << 12)
+		| ((slow & 1) << 11)
+		| (x4_en << 10)
+		| (qd_en << 9)
+		| (unq_mrs_en << 8)
+		| ((obc_cfg & 0x1) << 6)
+		| ((ap_en & 0x1) << 5)
+		| ((d_init & 0x1) << 4)
+		| ((rcw_en & 0x1) << 2)
+		| ((md_en & 0x1) << 0)
+		);
+	debug("FSLDDR: ddr_sdram_cfg_2 = 0x%08x\n", ddr->ddr_sdram_cfg_2);
+}
+
+/* DDR SDRAM Mode configuration 2 (DDR_SDRAM_MODE_2) */
+static void set_ddr_sdram_mode_2(fsl_ddr_cfg_regs_t *ddr,
+				const memctl_options_t *popts,
+				const common_timing_params_t *common_dimm,
+				const unsigned int unq_mrs_en)
+{
+	unsigned short esdmode2 = 0;	/* Extended SDRAM mode 2 */
+	unsigned short esdmode3 = 0;	/* Extended SDRAM mode 3 */
+
+#if defined(CONFIG_SYS_FSL_DDR3)
+	int i;
+	unsigned int rtt_wr = 0;	/* Rtt_WR - dynamic ODT off */
+	unsigned int srt = 0;	/* self-refresh temerature, normal range */
+	unsigned int asr = 0;	/* auto self-refresh disable */
+	unsigned int cwl = compute_cas_write_latency() - 5;
+	unsigned int pasr = 0;	/* partial array self refresh disable */
+
+	if (popts->rtt_override)
+		rtt_wr = popts->rtt_wr_override_value;
+	else
+		rtt_wr = popts->cs_local_opts[0].odt_rtt_wr;
+
+	if (common_dimm->extended_op_srt)
+		srt = common_dimm->extended_op_srt;
+
+	esdmode2 = (0
+		| ((rtt_wr & 0x3) << 9)
+		| ((srt & 0x1) << 7)
+		| ((asr & 0x1) << 6)
+		| ((cwl & 0x7) << 3)
+		| ((pasr & 0x7) << 0));
+#endif
+	ddr->ddr_sdram_mode_2 = (0
+				 | ((esdmode2 & 0xFFFF) << 16)
+				 | ((esdmode3 & 0xFFFF) << 0)
+				 );
+	debug("FSLDDR: ddr_sdram_mode_2 = 0x%08x\n", ddr->ddr_sdram_mode_2);
+
+#ifdef CONFIG_SYS_FSL_DDR3
+	if (unq_mrs_en) {	/* unique mode registers are supported */
+		for (i = 1; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
+			if (popts->rtt_override)
+				rtt_wr = popts->rtt_wr_override_value;
+			else
+				rtt_wr = popts->cs_local_opts[i].odt_rtt_wr;
+
+			esdmode2 &= 0xF9FF;	/* clear bit 10, 9 */
+			esdmode2 |= (rtt_wr & 0x3) << 9;
+			switch (i) {
+			case 1:
+				ddr->ddr_sdram_mode_4 = (0
+					| ((esdmode2 & 0xFFFF) << 16)
+					| ((esdmode3 & 0xFFFF) << 0)
+					);
+				break;
+			case 2:
+				ddr->ddr_sdram_mode_6 = (0
+					| ((esdmode2 & 0xFFFF) << 16)
+					| ((esdmode3 & 0xFFFF) << 0)
+					);
+				break;
+			case 3:
+				ddr->ddr_sdram_mode_8 = (0
+					| ((esdmode2 & 0xFFFF) << 16)
+					| ((esdmode3 & 0xFFFF) << 0)
+					);
+				break;
+			}
+		}
+		debug("FSLDDR: ddr_sdram_mode_4 = 0x%08x\n",
+			ddr->ddr_sdram_mode_4);
+		debug("FSLDDR: ddr_sdram_mode_6 = 0x%08x\n",
+			ddr->ddr_sdram_mode_6);
+		debug("FSLDDR: ddr_sdram_mode_8 = 0x%08x\n",
+			ddr->ddr_sdram_mode_8);
+	}
+#endif
+}
+
+/* DDR SDRAM Interval Configuration (DDR_SDRAM_INTERVAL) */
+static void set_ddr_sdram_interval(fsl_ddr_cfg_regs_t *ddr,
+			       const memctl_options_t *popts,
+			       const common_timing_params_t *common_dimm)
+{
+	unsigned int refint;	/* Refresh interval */
+	unsigned int bstopre;	/* Precharge interval */
+
+	refint = picos_to_mclk(common_dimm->refresh_rate_ps);
+
+	bstopre = popts->bstopre;
+
+	/* refint field used 0x3FFF in earlier controllers */
+	ddr->ddr_sdram_interval = (0
+				   | ((refint & 0xFFFF) << 16)
+				   | ((bstopre & 0x3FFF) << 0)
+				   );
+	debug("FSLDDR: ddr_sdram_interval = 0x%08x\n", ddr->ddr_sdram_interval);
+}
+
+#if defined(CONFIG_SYS_FSL_DDR3)
+/* DDR SDRAM Mode configuration set (DDR_SDRAM_MODE) */
+static void set_ddr_sdram_mode(fsl_ddr_cfg_regs_t *ddr,
+			       const memctl_options_t *popts,
+			       const common_timing_params_t *common_dimm,
+			       unsigned int cas_latency,
+			       unsigned int additive_latency,
+			       const unsigned int unq_mrs_en)
+{
+	unsigned short esdmode;		/* Extended SDRAM mode */
+	unsigned short sdmode;		/* SDRAM mode */
+
+	/* Mode Register - MR1 */
+	unsigned int qoff = 0;		/* Output buffer enable 0=yes, 1=no */
+	unsigned int tdqs_en = 0;	/* TDQS Enable: 0=no, 1=yes */
+	unsigned int rtt;
+	unsigned int wrlvl_en = 0;	/* Write level enable: 0=no, 1=yes */
+	unsigned int al = 0;		/* Posted CAS# additive latency (AL) */
+	unsigned int dic = 0;		/* Output driver impedance, 40ohm */
+	unsigned int dll_en = 0;	/* DLL Enable  0=Enable (Normal),
+						       1=Disable (Test/Debug) */
+
+	/* Mode Register - MR0 */
+	unsigned int dll_on;	/* DLL control for precharge PD, 0=off, 1=on */
+	unsigned int wr = 0;	/* Write Recovery */
+	unsigned int dll_rst;	/* DLL Reset */
+	unsigned int mode;	/* Normal=0 or Test=1 */
+	unsigned int caslat = 4;/* CAS# latency, default set as 6 cycles */
+	/* BT: Burst Type (0=Nibble Sequential, 1=Interleaved) */
+	unsigned int bt;
+	unsigned int bl;	/* BL: Burst Length */
+
+	unsigned int wr_mclk;
+	/*
+	 * DDR_SDRAM_MODE doesn't support 9,11,13,15
+	 * Please refer JEDEC Standard No. 79-3E for Mode Register MR0
+	 * for this table
+	 */
+	static const u8 wr_table[] = {1, 2, 3, 4, 5, 5, 6, 6, 7, 7, 0, 0};
+
+	const unsigned int mclk_ps = get_memory_clk_period_ps();
+	int i;
+
+	if (popts->rtt_override)
+		rtt = popts->rtt_override_value;
+	else
+		rtt = popts->cs_local_opts[0].odt_rtt_norm;
+
+	if (additive_latency == (cas_latency - 1))
+		al = 1;
+	if (additive_latency == (cas_latency - 2))
+		al = 2;
+
+	if (popts->quad_rank_present)
+		dic = 1;	/* output driver impedance 240/7 ohm */
+
+	/*
+	 * The esdmode value will also be used for writing
+	 * MR1 during write leveling for DDR3, although the
+	 * bits specifically related to the write leveling
+	 * scheme will be handled automatically by the DDR
+	 * controller. so we set the wrlvl_en = 0 here.
+	 */
+	esdmode = (0
+		| ((qoff & 0x1) << 12)
+		| ((tdqs_en & 0x1) << 11)
+		| ((rtt & 0x4) << 7)   /* rtt field is split */
+		| ((wrlvl_en & 0x1) << 7)
+		| ((rtt & 0x2) << 5)   /* rtt field is split */
+		| ((dic & 0x2) << 4)   /* DIC field is split */
+		| ((al & 0x3) << 3)
+		| ((rtt & 0x1) << 2)  /* rtt field is split */
+		| ((dic & 0x1) << 1)   /* DIC field is split */
+		| ((dll_en & 0x1) << 0)
+		);
+
+	/*
+	 * DLL control for precharge PD
+	 * 0=slow exit DLL off (tXPDLL)
+	 * 1=fast exit DLL on (tXP)
+	 */
+	dll_on = 1;
+
+	wr_mclk = (common_dimm->twr_ps + mclk_ps - 1) / mclk_ps;
+	if (wr_mclk <= 16) {
+		wr = wr_table[wr_mclk - 5];
+	} else {
+		printf("Error: unsupported write recovery for mode register "
+		       "wr_mclk = %d\n", wr_mclk);
+	}
+
+	dll_rst = 0;	/* dll no reset */
+	mode = 0;	/* normal mode */
+
+	/* look up table to get the cas latency bits */
+	if (cas_latency >= 5 && cas_latency <= 16) {
+		unsigned char cas_latency_table[] = {
+			0x2,	/* 5 clocks */
+			0x4,	/* 6 clocks */
+			0x6,	/* 7 clocks */
+			0x8,	/* 8 clocks */
+			0xa,	/* 9 clocks */
+			0xc,	/* 10 clocks */
+			0xe,	/* 11 clocks */
+			0x1,	/* 12 clocks */
+			0x3,	/* 13 clocks */
+			0x5,	/* 14 clocks */
+			0x7,	/* 15 clocks */
+			0x9,	/* 16 clocks */
+		};
+		caslat = cas_latency_table[cas_latency - 5];
+	} else {
+		printf("Error: unsupported cas latency for mode register\n");
+	}
+
+	bt = 0;	/* Nibble sequential */
+
+	switch (popts->burst_length) {
+	case DDR_BL8:
+		bl = 0;
+		break;
+	case DDR_OTF:
+		bl = 1;
+		break;
+	case DDR_BC4:
+		bl = 2;
+		break;
+	default:
+		printf("Error: invalid burst length of %u specified. "
+			" Defaulting to on-the-fly BC4 or BL8 beats.\n",
+			popts->burst_length);
+		bl = 1;
+		break;
+	}
+
+	sdmode = (0
+		  | ((dll_on & 0x1) << 12)
+		  | ((wr & 0x7) << 9)
+		  | ((dll_rst & 0x1) << 8)
+		  | ((mode & 0x1) << 7)
+		  | (((caslat >> 1) & 0x7) << 4)
+		  | ((bt & 0x1) << 3)
+		  | ((caslat & 1) << 2)
+		  | ((bl & 0x3) << 0)
+		  );
+
+	ddr->ddr_sdram_mode = (0
+			       | ((esdmode & 0xFFFF) << 16)
+			       | ((sdmode & 0xFFFF) << 0)
+			       );
+
+	debug("FSLDDR: ddr_sdram_mode = 0x%08x\n", ddr->ddr_sdram_mode);
+
+	if (unq_mrs_en) {	/* unique mode registers are supported */
+		for (i = 1; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
+			if (popts->rtt_override)
+				rtt = popts->rtt_override_value;
+			else
+				rtt = popts->cs_local_opts[i].odt_rtt_norm;
+
+			esdmode &= 0xFDBB;	/* clear bit 9,6,2 */
+			esdmode |= (0
+				| ((rtt & 0x4) << 7)   /* rtt field is split */
+				| ((rtt & 0x2) << 5)   /* rtt field is split */
+				| ((rtt & 0x1) << 2)  /* rtt field is split */
+				);
+			switch (i) {
+			case 1:
+				ddr->ddr_sdram_mode_3 = (0
+				       | ((esdmode & 0xFFFF) << 16)
+				       | ((sdmode & 0xFFFF) << 0)
+				       );
+				break;
+			case 2:
+				ddr->ddr_sdram_mode_5 = (0
+				       | ((esdmode & 0xFFFF) << 16)
+				       | ((sdmode & 0xFFFF) << 0)
+				       );
+				break;
+			case 3:
+				ddr->ddr_sdram_mode_7 = (0
+				       | ((esdmode & 0xFFFF) << 16)
+				       | ((sdmode & 0xFFFF) << 0)
+				       );
+				break;
+			}
+		}
+		debug("FSLDDR: ddr_sdram_mode_3 = 0x%08x\n",
+			ddr->ddr_sdram_mode_3);
+		debug("FSLDDR: ddr_sdram_mode_5 = 0x%08x\n",
+			ddr->ddr_sdram_mode_5);
+		debug("FSLDDR: ddr_sdram_mode_5 = 0x%08x\n",
+			ddr->ddr_sdram_mode_5);
+	}
+}
+
+#else /* !CONFIG_SYS_FSL_DDR3 */
+
+/* DDR SDRAM Mode configuration set (DDR_SDRAM_MODE) */
+static void set_ddr_sdram_mode(fsl_ddr_cfg_regs_t *ddr,
+			       const memctl_options_t *popts,
+			       const common_timing_params_t *common_dimm,
+			       unsigned int cas_latency,
+			       unsigned int additive_latency,
+			       const unsigned int unq_mrs_en)
+{
+	unsigned short esdmode;		/* Extended SDRAM mode */
+	unsigned short sdmode;		/* SDRAM mode */
+
+	/*
+	 * FIXME: This ought to be pre-calculated in a
+	 * technology-specific routine,
+	 * e.g. compute_DDR2_mode_register(), and then the
+	 * sdmode and esdmode passed in as part of common_dimm.
+	 */
+
+	/* Extended Mode Register */
+	unsigned int mrs = 0;		/* Mode Register Set */
+	unsigned int outputs = 0;	/* 0=Enabled, 1=Disabled */
+	unsigned int rdqs_en = 0;	/* RDQS Enable: 0=no, 1=yes */
+	unsigned int dqs_en = 0;	/* DQS# Enable: 0=enable, 1=disable */
+	unsigned int ocd = 0;		/* 0x0=OCD not supported,
+					   0x7=OCD default state */
+	unsigned int rtt;
+	unsigned int al;		/* Posted CAS# additive latency (AL) */
+	unsigned int ods = 0;		/* Output Drive Strength:
+						0 = Full strength (18ohm)
+						1 = Reduced strength (4ohm) */
+	unsigned int dll_en = 0;	/* DLL Enable  0=Enable (Normal),
+						       1=Disable (Test/Debug) */
+
+	/* Mode Register (MR) */
+	unsigned int mr;	/* Mode Register Definition */
+	unsigned int pd;	/* Power-Down Mode */
+	unsigned int wr;	/* Write Recovery */
+	unsigned int dll_res;	/* DLL Reset */
+	unsigned int mode;	/* Normal=0 or Test=1 */
+	unsigned int caslat = 0;/* CAS# latency */
+	/* BT: Burst Type (0=Sequential, 1=Interleaved) */
+	unsigned int bt;
+	unsigned int bl;	/* BL: Burst Length */
+
+#if defined(CONFIG_SYS_FSL_DDR2)
+	const unsigned int mclk_ps = get_memory_clk_period_ps();
+#endif
+	dqs_en = !popts->dqs_config;
+	rtt = fsl_ddr_get_rtt();
+
+	al = additive_latency;
+
+	esdmode = (0
+		| ((mrs & 0x3) << 14)
+		| ((outputs & 0x1) << 12)
+		| ((rdqs_en & 0x1) << 11)
+		| ((dqs_en & 0x1) << 10)
+		| ((ocd & 0x7) << 7)
+		| ((rtt & 0x2) << 5)   /* rtt field is split */
+		| ((al & 0x7) << 3)
+		| ((rtt & 0x1) << 2)   /* rtt field is split */
+		| ((ods & 0x1) << 1)
+		| ((dll_en & 0x1) << 0)
+		);
+
+	mr = 0;		 /* FIXME: CHECKME */
+
+	/*
+	 * 0 = Fast Exit (Normal)
+	 * 1 = Slow Exit (Low Power)
+	 */
+	pd = 0;
+
+#if defined(CONFIG_SYS_FSL_DDR1)
+	wr = 0;       /* Historical */
+#elif defined(CONFIG_SYS_FSL_DDR2)
+	wr = (common_dimm->twr_ps + mclk_ps - 1) / mclk_ps - 1;
+#endif
+	dll_res = 0;
+	mode = 0;
+
+#if defined(CONFIG_SYS_FSL_DDR1)
+	if (1 <= cas_latency && cas_latency <= 4) {
+		unsigned char mode_caslat_table[4] = {
+			0x5,	/* 1.5 clocks */
+			0x2,	/* 2.0 clocks */
+			0x6,	/* 2.5 clocks */
+			0x3	/* 3.0 clocks */
+		};
+		caslat = mode_caslat_table[cas_latency - 1];
+	} else {
+		printf("Warning: unknown cas_latency %d\n", cas_latency);
+	}
+#elif defined(CONFIG_SYS_FSL_DDR2)
+	caslat = cas_latency;
+#endif
+	bt = 0;
+
+	switch (popts->burst_length) {
+	case DDR_BL4:
+		bl = 2;
+		break;
+	case DDR_BL8:
+		bl = 3;
+		break;
+	default:
+		printf("Error: invalid burst length of %u specified. "
+			" Defaulting to 4 beats.\n",
+			popts->burst_length);
+		bl = 2;
+		break;
+	}
+
+	sdmode = (0
+		  | ((mr & 0x3) << 14)
+		  | ((pd & 0x1) << 12)
+		  | ((wr & 0x7) << 9)
+		  | ((dll_res & 0x1) << 8)
+		  | ((mode & 0x1) << 7)
+		  | ((caslat & 0x7) << 4)
+		  | ((bt & 0x1) << 3)
+		  | ((bl & 0x7) << 0)
+		  );
+
+	ddr->ddr_sdram_mode = (0
+			       | ((esdmode & 0xFFFF) << 16)
+			       | ((sdmode & 0xFFFF) << 0)
+			       );
+	debug("FSLDDR: ddr_sdram_mode = 0x%08x\n", ddr->ddr_sdram_mode);
+}
+#endif
+
+/* DDR SDRAM Data Initialization (DDR_DATA_INIT) */
+static void set_ddr_data_init(fsl_ddr_cfg_regs_t *ddr)
+{
+	unsigned int init_value;	/* Initialization value */
+
+#ifdef CONFIG_MEM_INIT_VALUE
+	init_value = CONFIG_MEM_INIT_VALUE;
+#else
+	init_value = 0xDEADBEEF;
+#endif
+	ddr->ddr_data_init = init_value;
+}
+
+/*
+ * DDR SDRAM Clock Control (DDR_SDRAM_CLK_CNTL)
+ * The old controller on the 8540/60 doesn't have this register.
+ * Hope it's OK to set it (to 0) anyway.
+ */
+static void set_ddr_sdram_clk_cntl(fsl_ddr_cfg_regs_t *ddr,
+					 const memctl_options_t *popts)
+{
+	unsigned int clk_adjust;	/* Clock adjust */
+
+	clk_adjust = popts->clk_adjust;
+	ddr->ddr_sdram_clk_cntl = (clk_adjust & 0xF) << 23;
+	debug("FSLDDR: clk_cntl = 0x%08x\n", ddr->ddr_sdram_clk_cntl);
+}
+
+/* DDR Initialization Address (DDR_INIT_ADDR) */
+static void set_ddr_init_addr(fsl_ddr_cfg_regs_t *ddr)
+{
+	unsigned int init_addr = 0;	/* Initialization address */
+
+	ddr->ddr_init_addr = init_addr;
+}
+
+/* DDR Initialization Address (DDR_INIT_EXT_ADDR) */
+static void set_ddr_init_ext_addr(fsl_ddr_cfg_regs_t *ddr)
+{
+	unsigned int uia = 0;	/* Use initialization address */
+	unsigned int init_ext_addr = 0;	/* Initialization address */
+
+	ddr->ddr_init_ext_addr = (0
+				  | ((uia & 0x1) << 31)
+				  | (init_ext_addr & 0xF)
+				  );
+}
+
+/* DDR SDRAM Timing Configuration 4 (TIMING_CFG_4) */
+static void set_timing_cfg_4(fsl_ddr_cfg_regs_t *ddr,
+				const memctl_options_t *popts)
+{
+	unsigned int rwt = 0; /* Read-to-write turnaround for same CS */
+	unsigned int wrt = 0; /* Write-to-read turnaround for same CS */
+	unsigned int rrt = 0; /* Read-to-read turnaround for same CS */
+	unsigned int wwt = 0; /* Write-to-write turnaround for same CS */
+	unsigned int dll_lock = 0; /* DDR SDRAM DLL Lock Time */
+
+#if defined(CONFIG_SYS_FSL_DDR3)
+	if (popts->burst_length == DDR_BL8) {
+		/* We set BL/2 for fixed BL8 */
+		rrt = 0;	/* BL/2 clocks */
+		wwt = 0;	/* BL/2 clocks */
+	} else {
+		/* We need to set BL/2 + 2 to BC4 and OTF */
+		rrt = 2;	/* BL/2 + 2 clocks */
+		wwt = 2;	/* BL/2 + 2 clocks */
+	}
+	dll_lock = 1;	/* tDLLK = 512 clocks from spec */
+#endif
+	ddr->timing_cfg_4 = (0
+			     | ((rwt & 0xf) << 28)
+			     | ((wrt & 0xf) << 24)
+			     | ((rrt & 0xf) << 20)
+			     | ((wwt & 0xf) << 16)
+			     | (dll_lock & 0x3)
+			     );
+	debug("FSLDDR: timing_cfg_4 = 0x%08x\n", ddr->timing_cfg_4);
+}
+
+/* DDR SDRAM Timing Configuration 5 (TIMING_CFG_5) */
+static void set_timing_cfg_5(fsl_ddr_cfg_regs_t *ddr, unsigned int cas_latency)
+{
+	unsigned int rodt_on = 0;	/* Read to ODT on */
+	unsigned int rodt_off = 0;	/* Read to ODT off */
+	unsigned int wodt_on = 0;	/* Write to ODT on */
+	unsigned int wodt_off = 0;	/* Write to ODT off */
+
+#if defined(CONFIG_SYS_FSL_DDR3)
+	/* rodt_on = timing_cfg_1[caslat] - timing_cfg_2[wrlat] + 1 */
+	rodt_on = cas_latency - ((ddr->timing_cfg_2 & 0x00780000) >> 19) + 1;
+	rodt_off = 4;	/*  4 clocks */
+	wodt_on = 1;	/*  1 clocks */
+	wodt_off = 4;	/*  4 clocks */
+#endif
+
+	ddr->timing_cfg_5 = (0
+			     | ((rodt_on & 0x1f) << 24)
+			     | ((rodt_off & 0x7) << 20)
+			     | ((wodt_on & 0x1f) << 12)
+			     | ((wodt_off & 0x7) << 8)
+			     );
+	debug("FSLDDR: timing_cfg_5 = 0x%08x\n", ddr->timing_cfg_5);
+}
+
+/* DDR ZQ Calibration Control (DDR_ZQ_CNTL) */
+static void set_ddr_zq_cntl(fsl_ddr_cfg_regs_t *ddr, unsigned int zq_en)
+{
+	unsigned int zqinit = 0;/* POR ZQ Calibration Time (tZQinit) */
+	/* Normal Operation Full Calibration Time (tZQoper) */
+	unsigned int zqoper = 0;
+	/* Normal Operation Short Calibration Time (tZQCS) */
+	unsigned int zqcs = 0;
+
+	if (zq_en) {
+		zqinit = 9;	/* 512 clocks */
+		zqoper = 8;	/* 256 clocks */
+		zqcs = 6;	/* 64 clocks */
+	}
+
+	ddr->ddr_zq_cntl = (0
+			    | ((zq_en & 0x1) << 31)
+			    | ((zqinit & 0xF) << 24)
+			    | ((zqoper & 0xF) << 16)
+			    | ((zqcs & 0xF) << 8)
+			    );
+	debug("FSLDDR: zq_cntl = 0x%08x\n", ddr->ddr_zq_cntl);
+}
+
+/* DDR Write Leveling Control (DDR_WRLVL_CNTL) */
+static void set_ddr_wrlvl_cntl(fsl_ddr_cfg_regs_t *ddr, unsigned int wrlvl_en,
+				const memctl_options_t *popts)
+{
+	/*
+	 * First DQS pulse rising edge after margining mode
+	 * is programmed (tWL_MRD)
+	 */
+	unsigned int wrlvl_mrd = 0;
+	/* ODT delay after margining mode is programmed (tWL_ODTEN) */
+	unsigned int wrlvl_odten = 0;
+	/* DQS/DQS_ delay after margining mode is programmed (tWL_DQSEN) */
+	unsigned int wrlvl_dqsen = 0;
+	/* WRLVL_SMPL: Write leveling sample time */
+	unsigned int wrlvl_smpl = 0;
+	/* WRLVL_WLR: Write leveling repeition time */
+	unsigned int wrlvl_wlr = 0;
+	/* WRLVL_START: Write leveling start time */
+	unsigned int wrlvl_start = 0;
+
+	/* suggest enable write leveling for DDR3 due to fly-by topology */
+	if (wrlvl_en) {
+		/* tWL_MRD min = 40 nCK, we set it 64 */
+		wrlvl_mrd = 0x6;
+		/* tWL_ODTEN 128 */
+		wrlvl_odten = 0x7;
+		/* tWL_DQSEN min = 25 nCK, we set it 32 */
+		wrlvl_dqsen = 0x5;
+		/*
+		 * Write leveling sample time at least need 6 clocks
+		 * higher than tWLO to allow enough time for progagation
+		 * delay and sampling the prime data bits.
+		 */
+		wrlvl_smpl = 0xf;
+		/*
+		 * Write leveling repetition time
+		 * at least tWLO + 6 clocks clocks
+		 * we set it 64
+		 */
+		wrlvl_wlr = 0x6;
+		/*
+		 * Write leveling start time
+		 * The value use for the DQS_ADJUST for the first sample
+		 * when write leveling is enabled. It probably needs to be
+		 * overriden per platform.
+		 */
+		wrlvl_start = 0x8;
+		/*
+		 * Override the write leveling sample and start time
+		 * according to specific board
+		 */
+		if (popts->wrlvl_override) {
+			wrlvl_smpl = popts->wrlvl_sample;
+			wrlvl_start = popts->wrlvl_start;
+		}
+	}
+
+	ddr->ddr_wrlvl_cntl = (0
+			       | ((wrlvl_en & 0x1) << 31)
+			       | ((wrlvl_mrd & 0x7) << 24)
+			       | ((wrlvl_odten & 0x7) << 20)
+			       | ((wrlvl_dqsen & 0x7) << 16)
+			       | ((wrlvl_smpl & 0xf) << 12)
+			       | ((wrlvl_wlr & 0x7) << 8)
+			       | ((wrlvl_start & 0x1F) << 0)
+			       );
+	debug("FSLDDR: wrlvl_cntl = 0x%08x\n", ddr->ddr_wrlvl_cntl);
+	ddr->ddr_wrlvl_cntl_2 = popts->wrlvl_ctl_2;
+	debug("FSLDDR: wrlvl_cntl_2 = 0x%08x\n", ddr->ddr_wrlvl_cntl_2);
+	ddr->ddr_wrlvl_cntl_3 = popts->wrlvl_ctl_3;
+	debug("FSLDDR: wrlvl_cntl_3 = 0x%08x\n", ddr->ddr_wrlvl_cntl_3);
+
+}
+
+/* DDR Self Refresh Counter (DDR_SR_CNTR) */
+static void set_ddr_sr_cntr(fsl_ddr_cfg_regs_t *ddr, unsigned int sr_it)
+{
+	/* Self Refresh Idle Threshold */
+	ddr->ddr_sr_cntr = (sr_it & 0xF) << 16;
+}
+
+static void set_ddr_eor(fsl_ddr_cfg_regs_t *ddr, const memctl_options_t *popts)
+{
+	if (popts->addr_hash) {
+		ddr->ddr_eor = 0x40000000;	/* address hash enable */
+		puts("Address hashing enabled.\n");
+	}
+}
+
+static void set_ddr_cdr1(fsl_ddr_cfg_regs_t *ddr, const memctl_options_t *popts)
+{
+	ddr->ddr_cdr1 = popts->ddr_cdr1;
+	debug("FSLDDR: ddr_cdr1 = 0x%08x\n", ddr->ddr_cdr1);
+}
+
+static void set_ddr_cdr2(fsl_ddr_cfg_regs_t *ddr, const memctl_options_t *popts)
+{
+	ddr->ddr_cdr2 = popts->ddr_cdr2;
+	debug("FSLDDR: ddr_cdr2 = 0x%08x\n", ddr->ddr_cdr2);
+}
+
+unsigned int
+check_fsl_memctl_config_regs(const fsl_ddr_cfg_regs_t *ddr)
+{
+	unsigned int res = 0;
+
+	/*
+	 * Check that DDR_SDRAM_CFG[RD_EN] and DDR_SDRAM_CFG[2T_EN] are
+	 * not set at the same time.
+	 */
+	if (ddr->ddr_sdram_cfg & 0x10000000
+	    && ddr->ddr_sdram_cfg & 0x00008000) {
+		printf("Error: DDR_SDRAM_CFG[RD_EN] and DDR_SDRAM_CFG[2T_EN] "
+				" should not be set at the same time.\n");
+		res++;
+	}
+
+	return res;
+}
+
+unsigned int
+compute_fsl_memctl_config_regs(const memctl_options_t *popts,
+			       fsl_ddr_cfg_regs_t *ddr,
+			       const common_timing_params_t *common_dimm,
+			       const dimm_params_t *dimm_params,
+			       unsigned int dbw_cap_adj,
+			       unsigned int size_only)
+{
+	unsigned int i;
+	unsigned int cas_latency;
+	unsigned int additive_latency;
+	unsigned int sr_it;
+	unsigned int zq_en;
+	unsigned int wrlvl_en;
+	unsigned int ip_rev = 0;
+	unsigned int unq_mrs_en = 0;
+	int cs_en = 1;
+
+	memset(ddr, 0, sizeof(fsl_ddr_cfg_regs_t));
+
+	if (common_dimm == NULL) {
+		printf("Error: subset DIMM params struct null pointer\n");
+		return 1;
+	}
+
+	/*
+	 * Process overrides first.
+	 *
+	 * FIXME: somehow add dereated caslat to this
+	 */
+	cas_latency = (popts->cas_latency_override)
+		? popts->cas_latency_override_value
+		: common_dimm->lowest_common_SPD_caslat;
+
+	additive_latency = (popts->additive_latency_override)
+		? popts->additive_latency_override_value
+		: common_dimm->additive_latency;
+
+	sr_it = (popts->auto_self_refresh_en)
+		? popts->sr_it
+		: 0;
+	/* ZQ calibration */
+	zq_en = (popts->zq_en) ? 1 : 0;
+	/* write leveling */
+	wrlvl_en = (popts->wrlvl_en) ? 1 : 0;
+
+	/* Chip Select Memory Bounds (CSn_BNDS) */
+	for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
+		unsigned long long ea, sa;
+		unsigned int cs_per_dimm
+			= CONFIG_CHIP_SELECTS_PER_CTRL / CONFIG_DIMM_SLOTS_PER_CTLR;
+		unsigned int dimm_number
+			= i / cs_per_dimm;
+		unsigned long long rank_density
+			= dimm_params[dimm_number].rank_density >> dbw_cap_adj;
+
+		if (dimm_params[dimm_number].n_ranks == 0) {
+			debug("Skipping setup of CS%u "
+				"because n_ranks on DIMM %u is 0\n", i, dimm_number);
+			continue;
+		}
+		if (popts->memctl_interleaving) {
+			switch (popts->ba_intlv_ctl & FSL_DDR_CS0_CS1_CS2_CS3) {
+			case FSL_DDR_CS0_CS1_CS2_CS3:
+				break;
+			case FSL_DDR_CS0_CS1:
+			case FSL_DDR_CS0_CS1_AND_CS2_CS3:
+				if (i > 1)
+					cs_en = 0;
+				break;
+			case FSL_DDR_CS2_CS3:
+			default:
+				if (i > 0)
+					cs_en = 0;
+				break;
+			}
+			sa = common_dimm->base_address;
+			ea = sa + common_dimm->total_mem - 1;
+		} else if (!popts->memctl_interleaving) {
+			/*
+			 * If memory interleaving between controllers is NOT
+			 * enabled, the starting address for each memory
+			 * controller is distinct.  However, because rank
+			 * interleaving is enabled, the starting and ending
+			 * addresses of the total memory on that memory
+			 * controller needs to be programmed into its
+			 * respective CS0_BNDS.
+			 */
+			switch (popts->ba_intlv_ctl & FSL_DDR_CS0_CS1_CS2_CS3) {
+			case FSL_DDR_CS0_CS1_CS2_CS3:
+				sa = common_dimm->base_address;
+				ea = sa + common_dimm->total_mem - 1;
+				break;
+			case FSL_DDR_CS0_CS1_AND_CS2_CS3:
+				if ((i >= 2) && (dimm_number == 0)) {
+					sa = dimm_params[dimm_number].base_address +
+					      2 * rank_density;
+					ea = sa + 2 * rank_density - 1;
+				} else {
+					sa = dimm_params[dimm_number].base_address;
+					ea = sa + 2 * rank_density - 1;
+				}
+				break;
+			case FSL_DDR_CS0_CS1:
+				if (dimm_params[dimm_number].n_ranks > (i % cs_per_dimm)) {
+					sa = dimm_params[dimm_number].base_address;
+					ea = sa + rank_density - 1;
+					if (i != 1)
+						sa += (i % cs_per_dimm) * rank_density;
+					ea += (i % cs_per_dimm) * rank_density;
+				} else {
+					sa = 0;
+					ea = 0;
+				}
+				if (i == 0)
+					ea += rank_density;
+				break;
+			case FSL_DDR_CS2_CS3:
+				if (dimm_params[dimm_number].n_ranks > (i % cs_per_dimm)) {
+					sa = dimm_params[dimm_number].base_address;
+					ea = sa + rank_density - 1;
+					if (i != 3)
+						sa += (i % cs_per_dimm) * rank_density;
+					ea += (i % cs_per_dimm) * rank_density;
+				} else {
+					sa = 0;
+					ea = 0;
+				}
+				if (i == 2)
+					ea += (rank_density >> dbw_cap_adj);
+				break;
+			default:  /* No bank(chip-select) interleaving */
+				sa = dimm_params[dimm_number].base_address;
+				ea = sa + rank_density - 1;
+				if (dimm_params[dimm_number].n_ranks > (i % cs_per_dimm)) {
+					sa += (i % cs_per_dimm) * rank_density;
+					ea += (i % cs_per_dimm) * rank_density;
+				} else {
+					sa = 0;
+					ea = 0;
+				}
+				break;
+			}
+		}
+
+		sa >>= 24;
+		ea >>= 24;
+
+		if (cs_en) {
+			ddr->cs[i].bnds = (0
+				| ((sa & 0xffff) << 16) /* starting address */
+				| ((ea & 0xffff) << 0)	/* ending address */
+				);
+		} else {
+			/* setting bnds to 0xffffffff for inactive CS */
+			ddr->cs[i].bnds = 0xffffffff;
+		}
+
+		debug("FSLDDR: cs[%d]_bnds = 0x%08x\n", i, ddr->cs[i].bnds);
+		set_csn_config(dimm_number, i, ddr, popts, dimm_params);
+		set_csn_config_2(i, ddr);
+	}
+
+	/*
+	 * In the case we only need to compute the ddr sdram size, we only need
+	 * to set csn registers, so return from here.
+	 */
+	if (size_only)
+		return 0;
+
+	set_ddr_eor(ddr, popts);
+
+#if !defined(CONFIG_SYS_FSL_DDR1)
+	set_timing_cfg_0(ddr, popts, dimm_params);
+#endif
+
+	set_timing_cfg_3(ddr, popts, common_dimm, cas_latency,
+			 additive_latency);
+	set_timing_cfg_1(ddr, popts, common_dimm, cas_latency);
+	set_timing_cfg_2(ddr, popts, common_dimm,
+				cas_latency, additive_latency);
+
+	set_ddr_cdr1(ddr, popts);
+	set_ddr_cdr2(ddr, popts);
+	set_ddr_sdram_cfg(ddr, popts, common_dimm);
+	ip_rev = fsl_ddr_get_version();
+	if (ip_rev > 0x40400)
+		unq_mrs_en = 1;
+
+	set_ddr_sdram_cfg_2(ddr, popts, unq_mrs_en);
+	set_ddr_sdram_mode(ddr, popts, common_dimm,
+				cas_latency, additive_latency, unq_mrs_en);
+	set_ddr_sdram_mode_2(ddr, popts, common_dimm, unq_mrs_en);
+	set_ddr_sdram_interval(ddr, popts, common_dimm);
+	set_ddr_data_init(ddr);
+	set_ddr_sdram_clk_cntl(ddr, popts);
+	set_ddr_init_addr(ddr);
+	set_ddr_init_ext_addr(ddr);
+	set_timing_cfg_4(ddr, popts);
+	set_timing_cfg_5(ddr, cas_latency);
+
+	set_ddr_zq_cntl(ddr, zq_en);
+	set_ddr_wrlvl_cntl(ddr, wrlvl_en, popts);
+
+	set_ddr_sr_cntr(ddr, sr_it);
+
+	set_ddr_sdram_rcw(ddr, popts, common_dimm);
+
+#ifdef CONFIG_SYS_FSL_DDR_EMU
+	/* disble DDR training for emulator */
+	ddr->debug[2] = 0x00000400;
+	ddr->debug[4] = 0xff800000;
+#endif
+	return check_fsl_memctl_config_regs(ddr);
+}
diff --git a/drivers/ddr/fsl/ddr1_dimm_params.c b/drivers/ddr/fsl/ddr1_dimm_params.c
new file mode 100644
index 0000000000..7df27b90b7
--- /dev/null
+++ b/drivers/ddr/fsl/ddr1_dimm_params.c
@@ -0,0 +1,343 @@
+/*
+ * Copyright 2008 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * Version 2 as published by the Free Software Foundation.
+ */
+
+#include <common.h>
+#include <fsl_ddr_sdram.h>
+
+#include <fsl_ddr.h>
+
+/*
+ * Calculate the Density of each Physical Rank.
+ * Returned size is in bytes.
+ *
+ * Study these table from Byte 31 of JEDEC SPD Spec.
+ *
+ *		DDR I	DDR II
+ *	Bit	Size	Size
+ *	---	-----	------
+ *	7 high	512MB	512MB
+ *	6	256MB	256MB
+ *	5	128MB	128MB
+ *	4	 64MB	 16GB
+ *	3	 32MB	  8GB
+ *	2	 16MB	  4GB
+ *	1	  2GB	  2GB
+ *	0 low	  1GB	  1GB
+ *
+ * Reorder Table to be linear by stripping the bottom
+ * 2 or 5 bits off and shifting them up to the top.
+ */
+
+static unsigned long long
+compute_ranksize(unsigned int mem_type, unsigned char row_dens)
+{
+	unsigned long long bsize;
+
+	/* Bottom 2 bits up to the top. */
+	bsize = ((row_dens >> 2) | ((row_dens & 3) << 6));
+	bsize <<= 24ULL;
+	debug("DDR: DDR I rank density = 0x%16llx\n", bsize);
+
+	return bsize;
+}
+
+/*
+ * Convert a two-nibble BCD value into a cycle time.
+ * While the spec calls for nano-seconds, picos are returned.
+ *
+ * This implements the tables for bytes 9, 23 and 25 for both
+ * DDR I and II.  No allowance for distinguishing the invalid
+ * fields absent for DDR I yet present in DDR II is made.
+ * (That is, cycle times of .25, .33, .66 and .75 ns are
+ * allowed for both DDR II and I.)
+ */
+static unsigned int
+convert_bcd_tenths_to_cycle_time_ps(unsigned int spd_val)
+{
+	/* Table look up the lower nibble, allow DDR I & II. */
+	unsigned int tenths_ps[16] = {
+		0,
+		100,
+		200,
+		300,
+		400,
+		500,
+		600,
+		700,
+		800,
+		900,
+		250,	/* This and the next 3 entries valid ... */
+		330,	/* ...  only for tCK calculations. */
+		660,
+		750,
+		0,	/* undefined */
+		0	/* undefined */
+	};
+
+	unsigned int whole_ns = (spd_val & 0xF0) >> 4;
+	unsigned int tenth_ns = spd_val & 0x0F;
+	unsigned int ps = whole_ns * 1000 + tenths_ps[tenth_ns];
+
+	return ps;
+}
+
+static unsigned int
+convert_bcd_hundredths_to_cycle_time_ps(unsigned int spd_val)
+{
+	unsigned int tenth_ns = (spd_val & 0xF0) >> 4;
+	unsigned int hundredth_ns = spd_val & 0x0F;
+	unsigned int ps = tenth_ns * 100 + hundredth_ns * 10;
+
+	return ps;
+}
+
+static unsigned int byte40_table_ps[8] = {
+	0,
+	250,
+	330,
+	500,
+	660,
+	750,
+	0,	/* supposed to be RFC, but not sure what that means */
+	0	/* Undefined */
+};
+
+static unsigned int
+compute_trfc_ps_from_spd(unsigned char trctrfc_ext, unsigned char trfc)
+{
+	unsigned int trfc_ps;
+
+	trfc_ps = (((trctrfc_ext & 0x1) * 256) + trfc) * 1000
+		+ byte40_table_ps[(trctrfc_ext >> 1) & 0x7];
+
+	return trfc_ps;
+}
+
+static unsigned int
+compute_trc_ps_from_spd(unsigned char trctrfc_ext, unsigned char trc)
+{
+	unsigned int trc_ps;
+
+	trc_ps = trc * 1000 + byte40_table_ps[(trctrfc_ext >> 4) & 0x7];
+
+	return trc_ps;
+}
+
+/*
+ * tCKmax from DDR I SPD Byte 43
+ *
+ * Bits 7:2 == whole ns
+ * Bits 1:0 == quarter ns
+ *    00    == 0.00 ns
+ *    01    == 0.25 ns
+ *    10    == 0.50 ns
+ *    11    == 0.75 ns
+ *
+ * Returns picoseconds.
+ */
+static unsigned int
+compute_tckmax_from_spd_ps(unsigned int byte43)
+{
+	return (byte43 >> 2) * 1000 + (byte43 & 0x3) * 250;
+}
+
+/*
+ * Determine Refresh Rate.  Ignore self refresh bit on DDR I.
+ * Table from SPD Spec, Byte 12, converted to picoseconds and
+ * filled in with "default" normal values.
+ */
+static unsigned int
+determine_refresh_rate_ps(const unsigned int spd_refresh)
+{
+	unsigned int refresh_time_ps[8] = {
+		15625000,	/* 0 Normal    1.00x */
+		3900000,	/* 1 Reduced    .25x */
+		7800000,	/* 2 Extended   .50x */
+		31300000,	/* 3 Extended  2.00x */
+		62500000,	/* 4 Extended  4.00x */
+		125000000,	/* 5 Extended  8.00x */
+		15625000,	/* 6 Normal    1.00x  filler */
+		15625000,	/* 7 Normal    1.00x  filler */
+	};
+
+	return refresh_time_ps[spd_refresh & 0x7];
+}
+
+/*
+ * The purpose of this function is to compute a suitable
+ * CAS latency given the DRAM clock period.  The SPD only
+ * defines at most 3 CAS latencies.  Typically the slower in
+ * frequency the DIMM runs at, the shorter its CAS latency can be.
+ * If the DIMM is operating at a sufficiently low frequency,
+ * it may be able to run at a CAS latency shorter than the
+ * shortest SPD-defined CAS latency.
+ *
+ * If a CAS latency is not found, 0 is returned.
+ *
+ * Do this by finding in the standard speed bin table the longest
+ * tCKmin that doesn't exceed the value of mclk_ps (tCK).
+ *
+ * An assumption made is that the SDRAM device allows the
+ * CL to be programmed for a value that is lower than those
+ * advertised by the SPD.  This is not always the case,
+ * as those modes not defined in the SPD are optional.
+ *
+ * CAS latency de-rating based upon values JEDEC Standard No. 79-E
+ * Table 11.
+ *
+ * ordinal 2, ddr1_speed_bins[1] contains tCK for CL=2
+ */
+				  /*   CL2.0 CL2.5 CL3.0  */
+unsigned short ddr1_speed_bins[] = {0, 7500, 6000, 5000 };
+
+unsigned int
+compute_derated_DDR1_CAS_latency(unsigned int mclk_ps)
+{
+	const unsigned int num_speed_bins = ARRAY_SIZE(ddr1_speed_bins);
+	unsigned int lowest_tCKmin_found = 0;
+	unsigned int lowest_tCKmin_CL = 0;
+	unsigned int i;
+
+	debug("mclk_ps = %u\n", mclk_ps);
+
+	for (i = 0; i < num_speed_bins; i++) {
+		unsigned int x = ddr1_speed_bins[i];
+		debug("i=%u, x = %u, lowest_tCKmin_found = %u\n",
+		      i, x, lowest_tCKmin_found);
+		if (x && lowest_tCKmin_found <= x && x <= mclk_ps) {
+			lowest_tCKmin_found = x;
+			lowest_tCKmin_CL = i + 1;
+		}
+	}
+
+	debug("lowest_tCKmin_CL = %u\n", lowest_tCKmin_CL);
+
+	return lowest_tCKmin_CL;
+}
+
+/*
+ * ddr_compute_dimm_parameters for DDR1 SPD
+ *
+ * Compute DIMM parameters based upon the SPD information in spd.
+ * Writes the results to the dimm_params_t structure pointed by pdimm.
+ *
+ * FIXME: use #define for the retvals
+ */
+unsigned int
+ddr_compute_dimm_parameters(const ddr1_spd_eeprom_t *spd,
+			     dimm_params_t *pdimm,
+			     unsigned int dimm_number)
+{
+	unsigned int retval;
+
+	if (spd->mem_type) {
+		if (spd->mem_type != SPD_MEMTYPE_DDR) {
+			printf("DIMM %u: is not a DDR1 SPD.\n", dimm_number);
+			return 1;
+		}
+	} else {
+		memset(pdimm, 0, sizeof(dimm_params_t));
+		return 1;
+	}
+
+	retval = ddr1_spd_check(spd);
+	if (retval) {
+		printf("DIMM %u: failed checksum\n", dimm_number);
+		return 2;
+	}
+
+	/*
+	 * The part name in ASCII in the SPD EEPROM is not null terminated.
+	 * Guarantee null termination here by presetting all bytes to 0
+	 * and copying the part name in ASCII from the SPD onto it
+	 */
+	memset(pdimm->mpart, 0, sizeof(pdimm->mpart));
+	memcpy(pdimm->mpart, spd->mpart, sizeof(pdimm->mpart) - 1);
+
+	/* DIMM organization parameters */
+	pdimm->n_ranks = spd->nrows;
+	pdimm->rank_density = compute_ranksize(spd->mem_type, spd->bank_dens);
+	pdimm->capacity = pdimm->n_ranks * pdimm->rank_density;
+	pdimm->data_width = spd->dataw_lsb;
+	pdimm->primary_sdram_width = spd->primw;
+	pdimm->ec_sdram_width = spd->ecw;
+
+	/*
+	 * FIXME: Need to determine registered_dimm status.
+	 *     1 == register buffered
+	 *     0 == unbuffered
+	 */
+	pdimm->registered_dimm = 0;	/* unbuffered */
+
+	/* SDRAM device parameters */
+	pdimm->n_row_addr = spd->nrow_addr;
+	pdimm->n_col_addr = spd->ncol_addr;
+	pdimm->n_banks_per_sdram_device = spd->nbanks;
+	pdimm->edc_config = spd->config;
+	pdimm->burst_lengths_bitmask = spd->burstl;
+	pdimm->row_density = spd->bank_dens;
+
+	/*
+	 * Calculate the Maximum Data Rate based on the Minimum Cycle time.
+	 * The SPD clk_cycle field (tCKmin) is measured in tenths of
+	 * nanoseconds and represented as BCD.
+	 */
+	pdimm->tckmin_x_ps
+		= convert_bcd_tenths_to_cycle_time_ps(spd->clk_cycle);
+	pdimm->tckmin_x_minus_1_ps
+		= convert_bcd_tenths_to_cycle_time_ps(spd->clk_cycle2);
+	pdimm->tckmin_x_minus_2_ps
+		= convert_bcd_tenths_to_cycle_time_ps(spd->clk_cycle3);
+
+	pdimm->tckmax_ps = compute_tckmax_from_spd_ps(spd->tckmax);
+
+	/*
+	 * Compute CAS latencies defined by SPD
+	 * The SPD caslat_x should have at least 1 and at most 3 bits set.
+	 *
+	 * If cas_lat after masking is 0, the __ilog2 function returns
+	 * 255 into the variable.   This behavior is abused once.
+	 */
+	pdimm->caslat_x  = __ilog2(spd->cas_lat);
+	pdimm->caslat_x_minus_1 = __ilog2(spd->cas_lat
+					  & ~(1 << pdimm->caslat_x));
+	pdimm->caslat_x_minus_2 = __ilog2(spd->cas_lat
+					  & ~(1 << pdimm->caslat_x)
+					  & ~(1 << pdimm->caslat_x_minus_1));
+
+	/* Compute CAS latencies below that defined by SPD */
+	pdimm->caslat_lowest_derated
+		= compute_derated_DDR1_CAS_latency(get_memory_clk_period_ps());
+
+	/* Compute timing parameters */
+	pdimm->trcd_ps = spd->trcd * 250;
+	pdimm->trp_ps = spd->trp * 250;
+	pdimm->tras_ps = spd->tras * 1000;
+
+	pdimm->twr_ps = mclk_to_picos(3);
+	pdimm->twtr_ps = mclk_to_picos(1);
+	pdimm->trfc_ps = compute_trfc_ps_from_spd(0, spd->trfc);
+
+	pdimm->trrd_ps = spd->trrd * 250;
+	pdimm->trc_ps = compute_trc_ps_from_spd(0, spd->trc);
+
+	pdimm->refresh_rate_ps = determine_refresh_rate_ps(spd->refresh);
+
+	pdimm->tis_ps = convert_bcd_hundredths_to_cycle_time_ps(spd->ca_setup);
+	pdimm->tih_ps = convert_bcd_hundredths_to_cycle_time_ps(spd->ca_hold);
+	pdimm->tds_ps
+		= convert_bcd_hundredths_to_cycle_time_ps(spd->data_setup);
+	pdimm->tdh_ps
+		= convert_bcd_hundredths_to_cycle_time_ps(spd->data_hold);
+
+	pdimm->trtp_ps = mclk_to_picos(2);	/* By the book. */
+	pdimm->tdqsq_max_ps = spd->tdqsq * 10;
+	pdimm->tqhs_ps = spd->tqhs * 10;
+
+	return 0;
+}
diff --git a/drivers/ddr/fsl/ddr2_dimm_params.c b/drivers/ddr/fsl/ddr2_dimm_params.c
new file mode 100644
index 0000000000..d865df78a8
--- /dev/null
+++ b/drivers/ddr/fsl/ddr2_dimm_params.c
@@ -0,0 +1,342 @@
+/*
+ * Copyright 2008 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * Version 2 as published by the Free Software Foundation.
+ */
+
+#include <common.h>
+#include <fsl_ddr_sdram.h>
+
+#include <fsl_ddr.h>
+/*
+ * Calculate the Density of each Physical Rank.
+ * Returned size is in bytes.
+ *
+ * Study these table from Byte 31 of JEDEC SPD Spec.
+ *
+ *		DDR I	DDR II
+ *	Bit	Size	Size
+ *	---	-----	------
+ *	7 high	512MB	512MB
+ *	6	256MB	256MB
+ *	5	128MB	128MB
+ *	4	 64MB	 16GB
+ *	3	 32MB	  8GB
+ *	2	 16MB	  4GB
+ *	1	  2GB	  2GB
+ *	0 low	  1GB	  1GB
+ *
+ * Reorder Table to be linear by stripping the bottom
+ * 2 or 5 bits off and shifting them up to the top.
+ *
+ */
+static unsigned long long
+compute_ranksize(unsigned int mem_type, unsigned char row_dens)
+{
+	unsigned long long bsize;
+
+	/* Bottom 5 bits up to the top. */
+	bsize = ((row_dens >> 5) | ((row_dens & 31) << 3));
+	bsize <<= 27ULL;
+	debug("DDR: DDR II rank density = 0x%16llx\n", bsize);
+
+	return bsize;
+}
+
+/*
+ * Convert a two-nibble BCD value into a cycle time.
+ * While the spec calls for nano-seconds, picos are returned.
+ *
+ * This implements the tables for bytes 9, 23 and 25 for both
+ * DDR I and II.  No allowance for distinguishing the invalid
+ * fields absent for DDR I yet present in DDR II is made.
+ * (That is, cycle times of .25, .33, .66 and .75 ns are
+ * allowed for both DDR II and I.)
+ */
+static unsigned int
+convert_bcd_tenths_to_cycle_time_ps(unsigned int spd_val)
+{
+	/* Table look up the lower nibble, allow DDR I & II. */
+	unsigned int tenths_ps[16] = {
+		0,
+		100,
+		200,
+		300,
+		400,
+		500,
+		600,
+		700,
+		800,
+		900,
+		250,	/* This and the next 3 entries valid ... */
+		330,	/* ...  only for tCK calculations. */
+		660,
+		750,
+		0,	/* undefined */
+		0	/* undefined */
+	};
+
+	unsigned int whole_ns = (spd_val & 0xF0) >> 4;
+	unsigned int tenth_ns = spd_val & 0x0F;
+	unsigned int ps = whole_ns * 1000 + tenths_ps[tenth_ns];
+
+	return ps;
+}
+
+static unsigned int
+convert_bcd_hundredths_to_cycle_time_ps(unsigned int spd_val)
+{
+	unsigned int tenth_ns = (spd_val & 0xF0) >> 4;
+	unsigned int hundredth_ns = spd_val & 0x0F;
+	unsigned int ps = tenth_ns * 100 + hundredth_ns * 10;
+
+	return ps;
+}
+
+static unsigned int byte40_table_ps[8] = {
+	0,
+	250,
+	330,
+	500,
+	660,
+	750,
+	0,	/* supposed to be RFC, but not sure what that means */
+	0	/* Undefined */
+};
+
+static unsigned int
+compute_trfc_ps_from_spd(unsigned char trctrfc_ext, unsigned char trfc)
+{
+	unsigned int trfc_ps;
+
+	trfc_ps = (((trctrfc_ext & 0x1) * 256) + trfc) * 1000
+		+ byte40_table_ps[(trctrfc_ext >> 1) & 0x7];
+
+	return trfc_ps;
+}
+
+static unsigned int
+compute_trc_ps_from_spd(unsigned char trctrfc_ext, unsigned char trc)
+{
+	unsigned int trc_ps;
+
+	trc_ps = trc * 1000 + byte40_table_ps[(trctrfc_ext >> 4) & 0x7];
+
+	return trc_ps;
+}
+
+/*
+ * Determine Refresh Rate.  Ignore self refresh bit on DDR I.
+ * Table from SPD Spec, Byte 12, converted to picoseconds and
+ * filled in with "default" normal values.
+ */
+static unsigned int
+determine_refresh_rate_ps(const unsigned int spd_refresh)
+{
+	unsigned int refresh_time_ps[8] = {
+		15625000,	/* 0 Normal    1.00x */
+		3900000,	/* 1 Reduced    .25x */
+		7800000,	/* 2 Extended   .50x */
+		31300000,	/* 3 Extended  2.00x */
+		62500000,	/* 4 Extended  4.00x */
+		125000000,	/* 5 Extended  8.00x */
+		15625000,	/* 6 Normal    1.00x  filler */
+		15625000,	/* 7 Normal    1.00x  filler */
+	};
+
+	return refresh_time_ps[spd_refresh & 0x7];
+}
+
+/*
+ * The purpose of this function is to compute a suitable
+ * CAS latency given the DRAM clock period.  The SPD only
+ * defines at most 3 CAS latencies.  Typically the slower in
+ * frequency the DIMM runs at, the shorter its CAS latency can.
+ * be.  If the DIMM is operating at a sufficiently low frequency,
+ * it may be able to run at a CAS latency shorter than the
+ * shortest SPD-defined CAS latency.
+ *
+ * If a CAS latency is not found, 0 is returned.
+ *
+ * Do this by finding in the standard speed bin table the longest
+ * tCKmin that doesn't exceed the value of mclk_ps (tCK).
+ *
+ * An assumption made is that the SDRAM device allows the
+ * CL to be programmed for a value that is lower than those
+ * advertised by the SPD.  This is not always the case,
+ * as those modes not defined in the SPD are optional.
+ *
+ * CAS latency de-rating based upon values JEDEC Standard No. 79-2C
+ * Table 40, "DDR2 SDRAM stanadard speed bins and tCK, tRCD, tRP, tRAS,
+ * and tRC for corresponding bin"
+ *
+ * ordinal 2, ddr2_speed_bins[1] contains tCK for CL=3
+ * Not certain if any good value exists for CL=2
+ */
+				 /* CL2   CL3   CL4   CL5   CL6  CL7*/
+unsigned short ddr2_speed_bins[] = {   0, 5000, 3750, 3000, 2500, 1875 };
+
+unsigned int
+compute_derated_DDR2_CAS_latency(unsigned int mclk_ps)
+{
+	const unsigned int num_speed_bins = ARRAY_SIZE(ddr2_speed_bins);
+	unsigned int lowest_tCKmin_found = 0;
+	unsigned int lowest_tCKmin_CL = 0;
+	unsigned int i;
+
+	debug("mclk_ps = %u\n", mclk_ps);
+
+	for (i = 0; i < num_speed_bins; i++) {
+		unsigned int x = ddr2_speed_bins[i];
+		debug("i=%u, x = %u, lowest_tCKmin_found = %u\n",
+		      i, x, lowest_tCKmin_found);
+		if (x && x <= mclk_ps && x >= lowest_tCKmin_found ) {
+			lowest_tCKmin_found = x;
+			lowest_tCKmin_CL = i + 2;
+		}
+	}
+
+	debug("lowest_tCKmin_CL = %u\n", lowest_tCKmin_CL);
+
+	return lowest_tCKmin_CL;
+}
+
+/*
+ * ddr_compute_dimm_parameters for DDR2 SPD
+ *
+ * Compute DIMM parameters based upon the SPD information in spd.
+ * Writes the results to the dimm_params_t structure pointed by pdimm.
+ *
+ * FIXME: use #define for the retvals
+ */
+unsigned int
+ddr_compute_dimm_parameters(const ddr2_spd_eeprom_t *spd,
+			     dimm_params_t *pdimm,
+			     unsigned int dimm_number)
+{
+	unsigned int retval;
+
+	if (spd->mem_type) {
+		if (spd->mem_type != SPD_MEMTYPE_DDR2) {
+			printf("DIMM %u: is not a DDR2 SPD.\n", dimm_number);
+			return 1;
+		}
+	} else {
+		memset(pdimm, 0, sizeof(dimm_params_t));
+		return 1;
+	}
+
+	retval = ddr2_spd_check(spd);
+	if (retval) {
+		printf("DIMM %u: failed checksum\n", dimm_number);
+		return 2;
+	}
+
+	/*
+	 * The part name in ASCII in the SPD EEPROM is not null terminated.
+	 * Guarantee null termination here by presetting all bytes to 0
+	 * and copying the part name in ASCII from the SPD onto it
+	 */
+	memset(pdimm->mpart, 0, sizeof(pdimm->mpart));
+	memcpy(pdimm->mpart, spd->mpart, sizeof(pdimm->mpart) - 1);
+
+	/* DIMM organization parameters */
+	pdimm->n_ranks = (spd->mod_ranks & 0x7) + 1;
+	pdimm->rank_density = compute_ranksize(spd->mem_type, spd->rank_dens);
+	pdimm->capacity = pdimm->n_ranks * pdimm->rank_density;
+	pdimm->data_width = spd->dataw;
+	pdimm->primary_sdram_width = spd->primw;
+	pdimm->ec_sdram_width = spd->ecw;
+
+	/* These are all the types defined by the JEDEC DDR2 SPD 1.3 spec */
+	switch (spd->dimm_type) {
+	case DDR2_SPD_DIMMTYPE_RDIMM:
+	case DDR2_SPD_DIMMTYPE_72B_SO_RDIMM:
+	case DDR2_SPD_DIMMTYPE_MINI_RDIMM:
+		/* Registered/buffered DIMMs */
+		pdimm->registered_dimm = 1;
+		break;
+
+	case DDR2_SPD_DIMMTYPE_UDIMM:
+	case DDR2_SPD_DIMMTYPE_SO_DIMM:
+	case DDR2_SPD_DIMMTYPE_MICRO_DIMM:
+	case DDR2_SPD_DIMMTYPE_MINI_UDIMM:
+		/* Unbuffered DIMMs */
+		pdimm->registered_dimm = 0;
+		break;
+
+	case DDR2_SPD_DIMMTYPE_72B_SO_CDIMM:
+	default:
+		printf("unknown dimm_type 0x%02X\n", spd->dimm_type);
+		return 1;
+	}
+
+	/* SDRAM device parameters */
+	pdimm->n_row_addr = spd->nrow_addr;
+	pdimm->n_col_addr = spd->ncol_addr;
+	pdimm->n_banks_per_sdram_device = spd->nbanks;
+	pdimm->edc_config = spd->config;
+	pdimm->burst_lengths_bitmask = spd->burstl;
+	pdimm->row_density = spd->rank_dens;
+
+	/*
+	 * Calculate the Maximum Data Rate based on the Minimum Cycle time.
+	 * The SPD clk_cycle field (tCKmin) is measured in tenths of
+	 * nanoseconds and represented as BCD.
+	 */
+	pdimm->tckmin_x_ps
+		= convert_bcd_tenths_to_cycle_time_ps(spd->clk_cycle);
+	pdimm->tckmin_x_minus_1_ps
+		= convert_bcd_tenths_to_cycle_time_ps(spd->clk_cycle2);
+	pdimm->tckmin_x_minus_2_ps
+		= convert_bcd_tenths_to_cycle_time_ps(spd->clk_cycle3);
+
+	pdimm->tckmax_ps = convert_bcd_tenths_to_cycle_time_ps(spd->tckmax);
+
+	/*
+	 * Compute CAS latencies defined by SPD
+	 * The SPD caslat_x should have at least 1 and at most 3 bits set.
+	 *
+	 * If cas_lat after masking is 0, the __ilog2 function returns
+	 * 255 into the variable.   This behavior is abused once.
+	 */
+	pdimm->caslat_x  = __ilog2(spd->cas_lat);
+	pdimm->caslat_x_minus_1 = __ilog2(spd->cas_lat
+					  & ~(1 << pdimm->caslat_x));
+	pdimm->caslat_x_minus_2 = __ilog2(spd->cas_lat
+					  & ~(1 << pdimm->caslat_x)
+					  & ~(1 << pdimm->caslat_x_minus_1));
+
+	/* Compute CAS latencies below that defined by SPD */
+	pdimm->caslat_lowest_derated
+		= compute_derated_DDR2_CAS_latency(get_memory_clk_period_ps());
+
+	/* Compute timing parameters */
+	pdimm->trcd_ps = spd->trcd * 250;
+	pdimm->trp_ps = spd->trp * 250;
+	pdimm->tras_ps = spd->tras * 1000;
+
+	pdimm->twr_ps = spd->twr * 250;
+	pdimm->twtr_ps = spd->twtr * 250;
+	pdimm->trfc_ps = compute_trfc_ps_from_spd(spd->trctrfc_ext, spd->trfc);
+
+	pdimm->trrd_ps = spd->trrd * 250;
+	pdimm->trc_ps = compute_trc_ps_from_spd(spd->trctrfc_ext, spd->trc);
+
+	pdimm->refresh_rate_ps = determine_refresh_rate_ps(spd->refresh);
+
+	pdimm->tis_ps = convert_bcd_hundredths_to_cycle_time_ps(spd->ca_setup);
+	pdimm->tih_ps = convert_bcd_hundredths_to_cycle_time_ps(spd->ca_hold);
+	pdimm->tds_ps
+		= convert_bcd_hundredths_to_cycle_time_ps(spd->data_setup);
+	pdimm->tdh_ps
+		= convert_bcd_hundredths_to_cycle_time_ps(spd->data_hold);
+
+	pdimm->trtp_ps = spd->trtp * 250;
+	pdimm->tdqsq_max_ps = spd->tdqsq * 10;
+	pdimm->tqhs_ps = spd->tqhs * 10;
+
+	return 0;
+}
diff --git a/drivers/ddr/fsl/ddr3_dimm_params.c b/drivers/ddr/fsl/ddr3_dimm_params.c
new file mode 100644
index 0000000000..a4b8c101f5
--- /dev/null
+++ b/drivers/ddr/fsl/ddr3_dimm_params.c
@@ -0,0 +1,341 @@
+/*
+ * Copyright 2008-2012 Freescale Semiconductor, Inc.
+ *	Dave Liu <daveliu@freescale.com>
+ *
+ * calculate the organization and timing parameter
+ * from ddr3 spd, please refer to the spec
+ * JEDEC standard No.21-C 4_01_02_11R18.pdf
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * Version 2 as published by the Free Software Foundation.
+ */
+
+#include <common.h>
+#include <fsl_ddr_sdram.h>
+
+#include <fsl_ddr.h>
+
+/*
+ * Calculate the Density of each Physical Rank.
+ * Returned size is in bytes.
+ *
+ * each rank size =
+ * sdram capacity(bit) / 8 * primary bus width / sdram width
+ *
+ * where: sdram capacity  = spd byte4[3:0]
+ *        primary bus width = spd byte8[2:0]
+ *        sdram width = spd byte7[2:0]
+ *
+ * SPD byte4 - sdram density and banks
+ *	bit[3:0]	size(bit)	size(byte)
+ *	0000		256Mb		32MB
+ *	0001		512Mb		64MB
+ *	0010		1Gb		128MB
+ *	0011		2Gb		256MB
+ *	0100		4Gb		512MB
+ *	0101		8Gb		1GB
+ *	0110		16Gb		2GB
+ *
+ * SPD byte8 - module memory bus width
+ * 	bit[2:0]	primary bus width
+ *	000		8bits
+ * 	001		16bits
+ * 	010		32bits
+ * 	011		64bits
+ *
+ * SPD byte7 - module organiztion
+ * 	bit[2:0]	sdram device width
+ * 	000		4bits
+ * 	001		8bits
+ * 	010		16bits
+ * 	011		32bits
+ *
+ */
+static unsigned long long
+compute_ranksize(const ddr3_spd_eeprom_t *spd)
+{
+	unsigned long long bsize;
+
+	int nbit_sdram_cap_bsize = 0;
+	int nbit_primary_bus_width = 0;
+	int nbit_sdram_width = 0;
+
+	if ((spd->density_banks & 0xf) < 7)
+		nbit_sdram_cap_bsize = (spd->density_banks & 0xf) + 28;
+	if ((spd->bus_width & 0x7) < 4)
+		nbit_primary_bus_width = (spd->bus_width & 0x7) + 3;
+	if ((spd->organization & 0x7) < 4)
+		nbit_sdram_width = (spd->organization & 0x7) + 2;
+
+	bsize = 1ULL << (nbit_sdram_cap_bsize - 3
+		    + nbit_primary_bus_width - nbit_sdram_width);
+
+	debug("DDR: DDR III rank density = 0x%16llx\n", bsize);
+
+	return bsize;
+}
+
+/*
+ * ddr_compute_dimm_parameters for DDR3 SPD
+ *
+ * Compute DIMM parameters based upon the SPD information in spd.
+ * Writes the results to the dimm_params_t structure pointed by pdimm.
+ *
+ */
+unsigned int
+ddr_compute_dimm_parameters(const ddr3_spd_eeprom_t *spd,
+			     dimm_params_t *pdimm,
+			     unsigned int dimm_number)
+{
+	unsigned int retval;
+	unsigned int mtb_ps;
+	int ftb_10th_ps;
+	int i;
+
+	if (spd->mem_type) {
+		if (spd->mem_type != SPD_MEMTYPE_DDR3) {
+			printf("DIMM %u: is not a DDR3 SPD.\n", dimm_number);
+			return 1;
+		}
+	} else {
+		memset(pdimm, 0, sizeof(dimm_params_t));
+		return 1;
+	}
+
+	retval = ddr3_spd_check(spd);
+	if (retval) {
+		printf("DIMM %u: failed checksum\n", dimm_number);
+		return 2;
+	}
+
+	/*
+	 * The part name in ASCII in the SPD EEPROM is not null terminated.
+	 * Guarantee null termination here by presetting all bytes to 0
+	 * and copying the part name in ASCII from the SPD onto it
+	 */
+	memset(pdimm->mpart, 0, sizeof(pdimm->mpart));
+	if ((spd->info_size_crc & 0xF) > 1)
+		memcpy(pdimm->mpart, spd->mpart, sizeof(pdimm->mpart) - 1);
+
+	/* DIMM organization parameters */
+	pdimm->n_ranks = ((spd->organization >> 3) & 0x7) + 1;
+	pdimm->rank_density = compute_ranksize(spd);
+	pdimm->capacity = pdimm->n_ranks * pdimm->rank_density;
+	pdimm->primary_sdram_width = 1 << (3 + (spd->bus_width & 0x7));
+	if ((spd->bus_width >> 3) & 0x3)
+		pdimm->ec_sdram_width = 8;
+	else
+		pdimm->ec_sdram_width = 0;
+	pdimm->data_width = pdimm->primary_sdram_width
+			  + pdimm->ec_sdram_width;
+	pdimm->device_width = 1 << ((spd->organization & 0x7) + 2);
+
+	/* These are the types defined by the JEDEC DDR3 SPD spec */
+	pdimm->mirrored_dimm = 0;
+	pdimm->registered_dimm = 0;
+	switch (spd->module_type & DDR3_SPD_MODULETYPE_MASK) {
+	case DDR3_SPD_MODULETYPE_RDIMM:
+	case DDR3_SPD_MODULETYPE_MINI_RDIMM:
+	case DDR3_SPD_MODULETYPE_72B_SO_RDIMM:
+		/* Registered/buffered DIMMs */
+		pdimm->registered_dimm = 1;
+		for (i = 0; i < 16; i += 2) {
+			u8 rcw = spd->mod_section.registered.rcw[i/2];
+			pdimm->rcw[i]   = (rcw >> 0) & 0x0F;
+			pdimm->rcw[i+1] = (rcw >> 4) & 0x0F;
+		}
+		break;
+
+	case DDR3_SPD_MODULETYPE_UDIMM:
+	case DDR3_SPD_MODULETYPE_SO_DIMM:
+	case DDR3_SPD_MODULETYPE_MICRO_DIMM:
+	case DDR3_SPD_MODULETYPE_MINI_UDIMM:
+	case DDR3_SPD_MODULETYPE_MINI_CDIMM:
+	case DDR3_SPD_MODULETYPE_72B_SO_UDIMM:
+	case DDR3_SPD_MODULETYPE_72B_SO_CDIMM:
+	case DDR3_SPD_MODULETYPE_LRDIMM:
+	case DDR3_SPD_MODULETYPE_16B_SO_DIMM:
+	case DDR3_SPD_MODULETYPE_32B_SO_DIMM:
+		/* Unbuffered DIMMs */
+		if (spd->mod_section.unbuffered.addr_mapping & 0x1)
+			pdimm->mirrored_dimm = 1;
+		break;
+
+	default:
+		printf("unknown module_type 0x%02X\n", spd->module_type);
+		return 1;
+	}
+
+	/* SDRAM device parameters */
+	pdimm->n_row_addr = ((spd->addressing >> 3) & 0x7) + 12;
+	pdimm->n_col_addr = (spd->addressing & 0x7) + 9;
+	pdimm->n_banks_per_sdram_device = 8 << ((spd->density_banks >> 4) & 0x7);
+
+	/*
+	 * The SPD spec has not the ECC bit,
+	 * We consider the DIMM as ECC capability
+	 * when the extension bus exist
+	 */
+	if (pdimm->ec_sdram_width)
+		pdimm->edc_config = 0x02;
+	else
+		pdimm->edc_config = 0x00;
+
+	/*
+	 * The SPD spec has not the burst length byte
+	 * but DDR3 spec has nature BL8 and BC4,
+	 * BL8 -bit3, BC4 -bit2
+	 */
+	pdimm->burst_lengths_bitmask = 0x0c;
+	pdimm->row_density = __ilog2(pdimm->rank_density);
+
+	/* MTB - medium timebase
+	 * The unit in the SPD spec is ns,
+	 * We convert it to ps.
+	 * eg: MTB = 0.125ns (125ps)
+	 */
+	mtb_ps = (spd->mtb_dividend * 1000) /spd->mtb_divisor;
+	pdimm->mtb_ps = mtb_ps;
+
+	/*
+	 * FTB - fine timebase
+	 * use 1/10th of ps as our unit to avoid floating point
+	 * eg, 10 for 1ps, 25 for 2.5ps, 50 for 5ps
+	 */
+	ftb_10th_ps =
+		((spd->ftb_div & 0xf0) >> 4) * 10 / (spd->ftb_div & 0x0f);
+	pdimm->ftb_10th_ps = ftb_10th_ps;
+	/*
+	 * sdram minimum cycle time
+	 * we assume the MTB is 0.125ns
+	 * eg:
+	 * tck_min=15 MTB (1.875ns) ->DDR3-1066
+	 *        =12 MTB (1.5ns) ->DDR3-1333
+	 *        =10 MTB (1.25ns) ->DDR3-1600
+	 */
+	pdimm->tckmin_x_ps = spd->tck_min * mtb_ps +
+		(spd->fine_tck_min * ftb_10th_ps) / 10;
+
+	/*
+	 * CAS latency supported
+	 * bit4 - CL4
+	 * bit5 - CL5
+	 * bit18 - CL18
+	 */
+	pdimm->caslat_x  = ((spd->caslat_msb << 8) | spd->caslat_lsb) << 4;
+
+	/*
+	 * min CAS latency time
+	 * eg: taa_min =
+	 * DDR3-800D	100 MTB (12.5ns)
+	 * DDR3-1066F	105 MTB (13.125ns)
+	 * DDR3-1333H	108 MTB (13.5ns)
+	 * DDR3-1600H	90 MTB (11.25ns)
+	 */
+	pdimm->taa_ps = spd->taa_min * mtb_ps +
+		(spd->fine_taa_min * ftb_10th_ps) / 10;
+
+	/*
+	 * min write recovery time
+	 * eg:
+	 * twr_min = 120 MTB (15ns) -> all speed grades.
+	 */
+	pdimm->twr_ps = spd->twr_min * mtb_ps;
+
+	/*
+	 * min RAS to CAS delay time
+	 * eg: trcd_min =
+	 * DDR3-800	100 MTB (12.5ns)
+	 * DDR3-1066F	105 MTB (13.125ns)
+	 * DDR3-1333H	108 MTB (13.5ns)
+	 * DDR3-1600H	90 MTB (11.25)
+	 */
+	pdimm->trcd_ps = spd->trcd_min * mtb_ps +
+		(spd->fine_trcd_min * ftb_10th_ps) / 10;
+
+	/*
+	 * min row active to row active delay time
+	 * eg: trrd_min =
+	 * DDR3-800(1KB page)	80 MTB (10ns)
+	 * DDR3-1333(1KB page)	48 MTB (6ns)
+	 */
+	pdimm->trrd_ps = spd->trrd_min * mtb_ps;
+
+	/*
+	 * min row precharge delay time
+	 * eg: trp_min =
+	 * DDR3-800D	100 MTB (12.5ns)
+	 * DDR3-1066F	105 MTB (13.125ns)
+	 * DDR3-1333H	108 MTB (13.5ns)
+	 * DDR3-1600H	90 MTB (11.25ns)
+	 */
+	pdimm->trp_ps = spd->trp_min * mtb_ps +
+		(spd->fine_trp_min * ftb_10th_ps) / 10;
+
+	/* min active to precharge delay time
+	 * eg: tRAS_min =
+	 * DDR3-800D	300 MTB (37.5ns)
+	 * DDR3-1066F	300 MTB (37.5ns)
+	 * DDR3-1333H	288 MTB (36ns)
+	 * DDR3-1600H	280 MTB (35ns)
+	 */
+	pdimm->tras_ps = (((spd->tras_trc_ext & 0xf) << 8) | spd->tras_min_lsb)
+			* mtb_ps;
+	/*
+	 * min active to actice/refresh delay time
+	 * eg: tRC_min =
+	 * DDR3-800D	400 MTB (50ns)
+	 * DDR3-1066F	405 MTB (50.625ns)
+	 * DDR3-1333H	396 MTB (49.5ns)
+	 * DDR3-1600H	370 MTB (46.25ns)
+	 */
+	pdimm->trc_ps = (((spd->tras_trc_ext & 0xf0) << 4) | spd->trc_min_lsb)
+			* mtb_ps + (spd->fine_trc_min * ftb_10th_ps) / 10;
+	/*
+	 * min refresh recovery delay time
+	 * eg: tRFC_min =
+	 * 512Mb	720 MTB (90ns)
+	 * 1Gb		880 MTB (110ns)
+	 * 2Gb		1280 MTB (160ns)
+	 */
+	pdimm->trfc_ps = ((spd->trfc_min_msb << 8) | spd->trfc_min_lsb)
+			* mtb_ps;
+	/*
+	 * min internal write to read command delay time
+	 * eg: twtr_min = 40 MTB (7.5ns) - all speed bins.
+	 * tWRT is at least 4 mclk independent of operating freq.
+	 */
+	pdimm->twtr_ps = spd->twtr_min * mtb_ps;
+
+	/*
+	 * min internal read to precharge command delay time
+	 * eg: trtp_min = 40 MTB (7.5ns) - all speed bins.
+	 * tRTP is at least 4 mclk independent of operating freq.
+	 */
+	pdimm->trtp_ps = spd->trtp_min * mtb_ps;
+
+	/*
+	 * Average periodic refresh interval
+	 * tREFI = 7.8 us at normal temperature range
+	 *       = 3.9 us at ext temperature range
+	 */
+	pdimm->refresh_rate_ps = 7800000;
+	if ((spd->therm_ref_opt & 0x1) && !(spd->therm_ref_opt & 0x2)) {
+		pdimm->refresh_rate_ps = 3900000;
+		pdimm->extended_op_srt = 1;
+	}
+
+	/*
+	 * min four active window delay time
+	 * eg: tfaw_min =
+	 * DDR3-800(1KB page)	320 MTB (40ns)
+	 * DDR3-1066(1KB page)	300 MTB (37.5ns)
+	 * DDR3-1333(1KB page)	240 MTB (30ns)
+	 * DDR3-1600(1KB page)	240 MTB (30ns)
+	 */
+	pdimm->tfaw_ps = (((spd->tfaw_msb & 0xf) << 8) | spd->tfaw_min)
+			* mtb_ps;
+
+	return 0;
+}
diff --git a/drivers/ddr/fsl/interactive.c b/drivers/ddr/fsl/interactive.c
new file mode 100644
index 0000000000..ebf3ed6f38
--- /dev/null
+++ b/drivers/ddr/fsl/interactive.c
@@ -0,0 +1,1871 @@
+/*
+ * Copyright 2010-2012 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * Generic driver for Freescale DDR/DDR2/DDR3 memory controller.
+ * Based on code from spd_sdram.c
+ * Author: James Yang [at freescale.com]
+ *         York Sun [at freescale.com]
+ */
+
+#include <common.h>
+#include <linux/ctype.h>
+#include <asm/types.h>
+#include <asm/io.h>
+
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr.h>
+
+/* Option parameter Structures */
+struct options_string {
+	const char *option_name;
+	size_t offset;
+	unsigned int size;
+	const char printhex;
+};
+
+static unsigned int picos_to_mhz(unsigned int picos)
+{
+	return 1000000 / picos;
+}
+
+static void print_option_table(const struct options_string *table,
+			 int table_size,
+			 const void *base)
+{
+	unsigned int i;
+	unsigned int *ptr;
+	unsigned long long *ptr_l;
+
+	for (i = 0; i < table_size; i++) {
+		switch (table[i].size) {
+		case 4:
+			ptr = (unsigned int *) (base + table[i].offset);
+			if (table[i].printhex) {
+				printf("%s = 0x%08X\n",
+					table[i].option_name, *ptr);
+			} else {
+				printf("%s = %u\n",
+					table[i].option_name, *ptr);
+			}
+			break;
+		case 8:
+			ptr_l = (unsigned long long *) (base + table[i].offset);
+			printf("%s = %llu\n",
+				table[i].option_name, *ptr_l);
+			break;
+		default:
+			printf("Unrecognized size!\n");
+			break;
+		}
+	}
+}
+
+static int handle_option_table(const struct options_string *table,
+			 int table_size,
+			 void *base,
+			 const char *opt,
+			 const char *val)
+{
+	unsigned int i;
+	unsigned int value, *ptr;
+	unsigned long long value_l, *ptr_l;
+
+	for (i = 0; i < table_size; i++) {
+		if (strcmp(table[i].option_name, opt) != 0)
+			continue;
+		switch (table[i].size) {
+		case 4:
+			value = simple_strtoul(val, NULL, 0);
+			ptr = base + table[i].offset;
+			*ptr = value;
+			break;
+		case 8:
+			value_l = simple_strtoull(val, NULL, 0);
+			ptr_l = base + table[i].offset;
+			*ptr_l = value_l;
+			break;
+		default:
+			printf("Unrecognized size!\n");
+			break;
+		}
+		return 1;
+	}
+
+	return 0;
+}
+
+static void fsl_ddr_generic_edit(void *pdata,
+			   void *pend,
+			   unsigned int element_size,
+			   unsigned int element_num,
+			   unsigned int value)
+{
+	char *pcdata = (char *)pdata;		/* BIG ENDIAN ONLY */
+
+	pcdata += element_num * element_size;
+	if ((pcdata + element_size) > (char *) pend) {
+		printf("trying to write past end of data\n");
+		return;
+	}
+
+	switch (element_size) {
+	case 1:
+		__raw_writeb(value, pcdata);
+		break;
+	case 2:
+		__raw_writew(value, pcdata);
+		break;
+	case 4:
+		__raw_writel(value, pcdata);
+		break;
+	default:
+		printf("unexpected element size %u\n", element_size);
+		break;
+	}
+}
+
+static void fsl_ddr_spd_edit(fsl_ddr_info_t *pinfo,
+		       unsigned int ctrl_num,
+		       unsigned int dimm_num,
+		       unsigned int element_num,
+		       unsigned int value)
+{
+	generic_spd_eeprom_t *pspd;
+
+	pspd = &(pinfo->spd_installed_dimms[ctrl_num][dimm_num]);
+	fsl_ddr_generic_edit(pspd, pspd + 1, 1, element_num, value);
+}
+
+#define COMMON_TIMING(x) {#x, offsetof(common_timing_params_t, x), \
+	sizeof((common_timing_params_t *)0)->x, 0}
+
+static void lowest_common_dimm_parameters_edit(fsl_ddr_info_t *pinfo,
+					unsigned int ctrl_num,
+					const char *optname_str,
+					const char *value_str)
+{
+	common_timing_params_t *p = &pinfo->common_timing_params[ctrl_num];
+
+	static const struct options_string options[] = {
+		COMMON_TIMING(tckmin_x_ps),
+		COMMON_TIMING(tckmax_ps),
+		COMMON_TIMING(tckmax_max_ps),
+		COMMON_TIMING(trcd_ps),
+		COMMON_TIMING(trp_ps),
+		COMMON_TIMING(tras_ps),
+		COMMON_TIMING(twr_ps),
+		COMMON_TIMING(twtr_ps),
+		COMMON_TIMING(trfc_ps),
+		COMMON_TIMING(trrd_ps),
+		COMMON_TIMING(trc_ps),
+		COMMON_TIMING(refresh_rate_ps),
+		COMMON_TIMING(tis_ps),
+		COMMON_TIMING(tih_ps),
+		COMMON_TIMING(tds_ps),
+		COMMON_TIMING(tdh_ps),
+		COMMON_TIMING(trtp_ps),
+		COMMON_TIMING(tdqsq_max_ps),
+		COMMON_TIMING(tqhs_ps),
+		COMMON_TIMING(ndimms_present),
+		COMMON_TIMING(lowest_common_SPD_caslat),
+		COMMON_TIMING(highest_common_derated_caslat),
+		COMMON_TIMING(additive_latency),
+		COMMON_TIMING(all_dimms_burst_lengths_bitmask),
+		COMMON_TIMING(all_dimms_registered),
+		COMMON_TIMING(all_dimms_unbuffered),
+		COMMON_TIMING(all_dimms_ecc_capable),
+		COMMON_TIMING(total_mem),
+		COMMON_TIMING(base_address),
+	};
+	static const unsigned int n_opts = ARRAY_SIZE(options);
+
+	if (handle_option_table(options, n_opts, p, optname_str, value_str))
+		return;
+
+	printf("Error: couldn't find option string %s\n", optname_str);
+}
+
+#define DIMM_PARM(x) {#x, offsetof(dimm_params_t, x), \
+	sizeof((dimm_params_t *)0)->x, 0}
+
+static void fsl_ddr_dimm_parameters_edit(fsl_ddr_info_t *pinfo,
+				   unsigned int ctrl_num,
+				   unsigned int dimm_num,
+				   const char *optname_str,
+				   const char *value_str)
+{
+	dimm_params_t *p = &(pinfo->dimm_params[ctrl_num][dimm_num]);
+
+	static const struct options_string options[] = {
+		DIMM_PARM(n_ranks),
+		DIMM_PARM(data_width),
+		DIMM_PARM(primary_sdram_width),
+		DIMM_PARM(ec_sdram_width),
+		DIMM_PARM(registered_dimm),
+		DIMM_PARM(device_width),
+
+		DIMM_PARM(n_row_addr),
+		DIMM_PARM(n_col_addr),
+		DIMM_PARM(edc_config),
+		DIMM_PARM(n_banks_per_sdram_device),
+		DIMM_PARM(burst_lengths_bitmask),
+		DIMM_PARM(row_density),
+
+		DIMM_PARM(tckmin_x_ps),
+		DIMM_PARM(tckmin_x_minus_1_ps),
+		DIMM_PARM(tckmin_x_minus_2_ps),
+		DIMM_PARM(tckmax_ps),
+
+		DIMM_PARM(caslat_x),
+		DIMM_PARM(caslat_x_minus_1),
+		DIMM_PARM(caslat_x_minus_2),
+
+		DIMM_PARM(caslat_lowest_derated),
+
+		DIMM_PARM(trcd_ps),
+		DIMM_PARM(trp_ps),
+		DIMM_PARM(tras_ps),
+		DIMM_PARM(twr_ps),
+		DIMM_PARM(twtr_ps),
+		DIMM_PARM(trfc_ps),
+		DIMM_PARM(trrd_ps),
+		DIMM_PARM(trc_ps),
+		DIMM_PARM(refresh_rate_ps),
+
+		DIMM_PARM(tis_ps),
+		DIMM_PARM(tih_ps),
+		DIMM_PARM(tds_ps),
+		DIMM_PARM(tdh_ps),
+		DIMM_PARM(trtp_ps),
+		DIMM_PARM(tdqsq_max_ps),
+		DIMM_PARM(tqhs_ps),
+
+		DIMM_PARM(rank_density),
+		DIMM_PARM(capacity),
+		DIMM_PARM(base_address),
+	};
+
+	static const unsigned int n_opts = ARRAY_SIZE(options);
+
+	if (handle_option_table(options, n_opts, p, optname_str, value_str))
+		return;
+
+	printf("couldn't find option string %s\n", optname_str);
+}
+
+static void print_dimm_parameters(const dimm_params_t *pdimm)
+{
+	static const struct options_string options[] = {
+		DIMM_PARM(n_ranks),
+		DIMM_PARM(data_width),
+		DIMM_PARM(primary_sdram_width),
+		DIMM_PARM(ec_sdram_width),
+		DIMM_PARM(registered_dimm),
+		DIMM_PARM(device_width),
+
+		DIMM_PARM(n_row_addr),
+		DIMM_PARM(n_col_addr),
+		DIMM_PARM(edc_config),
+		DIMM_PARM(n_banks_per_sdram_device),
+
+		DIMM_PARM(tckmin_x_ps),
+		DIMM_PARM(tckmin_x_minus_1_ps),
+		DIMM_PARM(tckmin_x_minus_2_ps),
+		DIMM_PARM(tckmax_ps),
+
+		DIMM_PARM(caslat_x),
+		DIMM_PARM(taa_ps),
+		DIMM_PARM(caslat_x_minus_1),
+		DIMM_PARM(caslat_x_minus_2),
+		DIMM_PARM(caslat_lowest_derated),
+
+		DIMM_PARM(trcd_ps),
+		DIMM_PARM(trp_ps),
+		DIMM_PARM(tras_ps),
+		DIMM_PARM(twr_ps),
+		DIMM_PARM(twtr_ps),
+		DIMM_PARM(trfc_ps),
+		DIMM_PARM(trrd_ps),
+		DIMM_PARM(trc_ps),
+		DIMM_PARM(refresh_rate_ps),
+
+		DIMM_PARM(tis_ps),
+		DIMM_PARM(tih_ps),
+		DIMM_PARM(tds_ps),
+		DIMM_PARM(tdh_ps),
+		DIMM_PARM(trtp_ps),
+		DIMM_PARM(tdqsq_max_ps),
+		DIMM_PARM(tqhs_ps),
+	};
+	static const unsigned int n_opts = ARRAY_SIZE(options);
+
+	if (pdimm->n_ranks == 0) {
+		printf("DIMM not present\n");
+		return;
+	}
+	printf("DIMM organization parameters:\n");
+	printf("module part name = %s\n", pdimm->mpart);
+	printf("rank_density = %llu bytes (%llu megabytes)\n",
+	       pdimm->rank_density, pdimm->rank_density / 0x100000);
+	printf("capacity = %llu bytes (%llu megabytes)\n",
+	       pdimm->capacity, pdimm->capacity / 0x100000);
+	printf("burst_lengths_bitmask = %02X\n",
+	       pdimm->burst_lengths_bitmask);
+	printf("base_addresss = %llu (%08llX %08llX)\n",
+	       pdimm->base_address,
+	       (pdimm->base_address >> 32),
+	       pdimm->base_address & 0xFFFFFFFF);
+	print_option_table(options, n_opts, pdimm);
+}
+
+static void print_lowest_common_dimm_parameters(
+		const common_timing_params_t *plcd_dimm_params)
+{
+	static const struct options_string options[] = {
+		COMMON_TIMING(tckmax_max_ps),
+		COMMON_TIMING(trcd_ps),
+		COMMON_TIMING(trp_ps),
+		COMMON_TIMING(tras_ps),
+		COMMON_TIMING(twr_ps),
+		COMMON_TIMING(twtr_ps),
+		COMMON_TIMING(trfc_ps),
+		COMMON_TIMING(trrd_ps),
+		COMMON_TIMING(trc_ps),
+		COMMON_TIMING(refresh_rate_ps),
+		COMMON_TIMING(tis_ps),
+		COMMON_TIMING(tds_ps),
+		COMMON_TIMING(tdh_ps),
+		COMMON_TIMING(trtp_ps),
+		COMMON_TIMING(tdqsq_max_ps),
+		COMMON_TIMING(tqhs_ps),
+		COMMON_TIMING(lowest_common_SPD_caslat),
+		COMMON_TIMING(highest_common_derated_caslat),
+		COMMON_TIMING(additive_latency),
+		COMMON_TIMING(ndimms_present),
+		COMMON_TIMING(all_dimms_registered),
+		COMMON_TIMING(all_dimms_unbuffered),
+		COMMON_TIMING(all_dimms_ecc_capable),
+	};
+	static const unsigned int n_opts = ARRAY_SIZE(options);
+
+	/* Clock frequencies */
+	printf("tckmin_x_ps = %u (%u MHz)\n",
+	       plcd_dimm_params->tckmin_x_ps,
+	       picos_to_mhz(plcd_dimm_params->tckmin_x_ps));
+	printf("tckmax_ps = %u (%u MHz)\n",
+	       plcd_dimm_params->tckmax_ps,
+	       picos_to_mhz(plcd_dimm_params->tckmax_ps));
+	printf("all_dimms_burst_lengths_bitmask = %02X\n",
+	       plcd_dimm_params->all_dimms_burst_lengths_bitmask);
+
+	print_option_table(options, n_opts, plcd_dimm_params);
+
+	printf("total_mem = %llu (%llu megabytes)\n",
+	       plcd_dimm_params->total_mem,
+	       plcd_dimm_params->total_mem / 0x100000);
+	printf("base_address = %llu (%llu megabytes)\n",
+	       plcd_dimm_params->base_address,
+	       plcd_dimm_params->base_address / 0x100000);
+}
+
+#define CTRL_OPTIONS(x) {#x, offsetof(memctl_options_t, x), \
+	sizeof((memctl_options_t *)0)->x, 0}
+#define CTRL_OPTIONS_CS(x, y) {"cs" #x "_" #y, \
+	offsetof(memctl_options_t, cs_local_opts[x].y), \
+	sizeof((memctl_options_t *)0)->cs_local_opts[x].y, 0}
+
+static void fsl_ddr_options_edit(fsl_ddr_info_t *pinfo,
+			   unsigned int ctl_num,
+			   const char *optname_str,
+			   const char *value_str)
+{
+	memctl_options_t *p = &(pinfo->memctl_opts[ctl_num]);
+	/*
+	 * This array all on the stack and *computed* each time this
+	 * function is rung.
+	 */
+	static const struct options_string options[] = {
+		CTRL_OPTIONS_CS(0, odt_rd_cfg),
+		CTRL_OPTIONS_CS(0, odt_wr_cfg),
+#if (CONFIG_CHIP_SELECTS_PER_CTRL > 1)
+		CTRL_OPTIONS_CS(1, odt_rd_cfg),
+		CTRL_OPTIONS_CS(1, odt_wr_cfg),
+#endif
+#if (CONFIG_CHIP_SELECTS_PER_CTRL > 2)
+		CTRL_OPTIONS_CS(2, odt_rd_cfg),
+		CTRL_OPTIONS_CS(2, odt_wr_cfg),
+#endif
+#if (CONFIG_CHIP_SELECTS_PER_CTRL > 2)
+		CTRL_OPTIONS_CS(3, odt_rd_cfg),
+		CTRL_OPTIONS_CS(3, odt_wr_cfg),
+#endif
+#if defined(CONFIG_SYS_FSL_DDR3)
+		CTRL_OPTIONS_CS(0, odt_rtt_norm),
+		CTRL_OPTIONS_CS(0, odt_rtt_wr),
+#if (CONFIG_CHIP_SELECTS_PER_CTRL > 1)
+		CTRL_OPTIONS_CS(1, odt_rtt_norm),
+		CTRL_OPTIONS_CS(1, odt_rtt_wr),
+#endif
+#if (CONFIG_CHIP_SELECTS_PER_CTRL > 2)
+		CTRL_OPTIONS_CS(2, odt_rtt_norm),
+		CTRL_OPTIONS_CS(2, odt_rtt_wr),
+#endif
+#if (CONFIG_CHIP_SELECTS_PER_CTRL > 2)
+		CTRL_OPTIONS_CS(3, odt_rtt_norm),
+		CTRL_OPTIONS_CS(3, odt_rtt_wr),
+#endif
+#endif
+		CTRL_OPTIONS(memctl_interleaving),
+		CTRL_OPTIONS(memctl_interleaving_mode),
+		CTRL_OPTIONS(ba_intlv_ctl),
+		CTRL_OPTIONS(ecc_mode),
+		CTRL_OPTIONS(ecc_init_using_memctl),
+		CTRL_OPTIONS(dqs_config),
+		CTRL_OPTIONS(self_refresh_in_sleep),
+		CTRL_OPTIONS(dynamic_power),
+		CTRL_OPTIONS(data_bus_width),
+		CTRL_OPTIONS(burst_length),
+		CTRL_OPTIONS(cas_latency_override),
+		CTRL_OPTIONS(cas_latency_override_value),
+		CTRL_OPTIONS(use_derated_caslat),
+		CTRL_OPTIONS(additive_latency_override),
+		CTRL_OPTIONS(additive_latency_override_value),
+		CTRL_OPTIONS(clk_adjust),
+		CTRL_OPTIONS(cpo_override),
+		CTRL_OPTIONS(write_data_delay),
+		CTRL_OPTIONS(half_strength_driver_enable),
+
+		/*
+		 * These can probably be changed to 2T_EN and 3T_EN
+		 * (using a leading numerical character) without problem
+		 */
+		CTRL_OPTIONS(twot_en),
+		CTRL_OPTIONS(threet_en),
+		CTRL_OPTIONS(ap_en),
+		CTRL_OPTIONS(x4_en),
+		CTRL_OPTIONS(bstopre),
+		CTRL_OPTIONS(wrlvl_override),
+		CTRL_OPTIONS(wrlvl_sample),
+		CTRL_OPTIONS(wrlvl_start),
+		CTRL_OPTIONS(rcw_override),
+		CTRL_OPTIONS(rcw_1),
+		CTRL_OPTIONS(rcw_2),
+		CTRL_OPTIONS(ddr_cdr1),
+		CTRL_OPTIONS(ddr_cdr2),
+		CTRL_OPTIONS(tcke_clock_pulse_width_ps),
+		CTRL_OPTIONS(tfaw_window_four_activates_ps),
+		CTRL_OPTIONS(trwt_override),
+		CTRL_OPTIONS(trwt),
+	};
+
+	static const unsigned int n_opts = ARRAY_SIZE(options);
+
+	if (handle_option_table(options, n_opts, p,
+					optname_str, value_str))
+		return;
+
+	printf("couldn't find option string %s\n", optname_str);
+}
+
+#define CFG_REGS(x) {#x, offsetof(fsl_ddr_cfg_regs_t, x), \
+	sizeof((fsl_ddr_cfg_regs_t *)0)->x, 1}
+#define CFG_REGS_CS(x, y) {"cs" #x "_" #y, \
+	offsetof(fsl_ddr_cfg_regs_t, cs[x].y), \
+	sizeof((fsl_ddr_cfg_regs_t *)0)->cs[x].y, 1}
+
+static void print_fsl_memctl_config_regs(const fsl_ddr_cfg_regs_t *ddr)
+{
+	unsigned int i;
+	static const struct options_string options[] = {
+		CFG_REGS_CS(0, bnds),
+		CFG_REGS_CS(0, config),
+		CFG_REGS_CS(0, config_2),
+#if (CONFIG_CHIP_SELECTS_PER_CTRL > 1)
+		CFG_REGS_CS(1, bnds),
+		CFG_REGS_CS(1, config),
+		CFG_REGS_CS(1, config_2),
+#endif
+#if (CONFIG_CHIP_SELECTS_PER_CTRL > 2)
+		CFG_REGS_CS(2, bnds),
+		CFG_REGS_CS(2, config),
+		CFG_REGS_CS(2, config_2),
+#endif
+#if (CONFIG_CHIP_SELECTS_PER_CTRL > 2)
+		CFG_REGS_CS(3, bnds),
+		CFG_REGS_CS(3, config),
+		CFG_REGS_CS(3, config_2),
+#endif
+		CFG_REGS(timing_cfg_3),
+		CFG_REGS(timing_cfg_0),
+		CFG_REGS(timing_cfg_1),
+		CFG_REGS(timing_cfg_2),
+		CFG_REGS(ddr_sdram_cfg),
+		CFG_REGS(ddr_sdram_cfg_2),
+		CFG_REGS(ddr_sdram_mode),
+		CFG_REGS(ddr_sdram_mode_2),
+		CFG_REGS(ddr_sdram_mode_3),
+		CFG_REGS(ddr_sdram_mode_4),
+		CFG_REGS(ddr_sdram_mode_5),
+		CFG_REGS(ddr_sdram_mode_6),
+		CFG_REGS(ddr_sdram_mode_7),
+		CFG_REGS(ddr_sdram_mode_8),
+		CFG_REGS(ddr_sdram_interval),
+		CFG_REGS(ddr_data_init),
+		CFG_REGS(ddr_sdram_clk_cntl),
+		CFG_REGS(ddr_init_addr),
+		CFG_REGS(ddr_init_ext_addr),
+		CFG_REGS(timing_cfg_4),
+		CFG_REGS(timing_cfg_5),
+		CFG_REGS(ddr_zq_cntl),
+		CFG_REGS(ddr_wrlvl_cntl),
+		CFG_REGS(ddr_wrlvl_cntl_2),
+		CFG_REGS(ddr_wrlvl_cntl_3),
+		CFG_REGS(ddr_sr_cntr),
+		CFG_REGS(ddr_sdram_rcw_1),
+		CFG_REGS(ddr_sdram_rcw_2),
+		CFG_REGS(ddr_cdr1),
+		CFG_REGS(ddr_cdr2),
+		CFG_REGS(err_disable),
+		CFG_REGS(err_int_en),
+		CFG_REGS(ddr_eor),
+	};
+	static const unsigned int n_opts = ARRAY_SIZE(options);
+
+	print_option_table(options, n_opts, ddr);
+
+	for (i = 0; i < 32; i++)
+		printf("debug_%02d = 0x%08X\n", i+1, ddr->debug[i]);
+}
+
+static void fsl_ddr_regs_edit(fsl_ddr_info_t *pinfo,
+			unsigned int ctrl_num,
+			const char *regname,
+			const char *value_str)
+{
+	unsigned int i;
+	fsl_ddr_cfg_regs_t *ddr;
+	char buf[20];
+	static const struct options_string options[] = {
+		CFG_REGS_CS(0, bnds),
+		CFG_REGS_CS(0, config),
+		CFG_REGS_CS(0, config_2),
+#if (CONFIG_CHIP_SELECTS_PER_CTRL > 1)
+		CFG_REGS_CS(1, bnds),
+		CFG_REGS_CS(1, config),
+		CFG_REGS_CS(1, config_2),
+#endif
+#if (CONFIG_CHIP_SELECTS_PER_CTRL > 2)
+		CFG_REGS_CS(2, bnds),
+		CFG_REGS_CS(2, config),
+		CFG_REGS_CS(2, config_2),
+#endif
+#if (CONFIG_CHIP_SELECTS_PER_CTRL > 3)
+		CFG_REGS_CS(3, bnds),
+		CFG_REGS_CS(3, config),
+		CFG_REGS_CS(3, config_2),
+#endif
+		CFG_REGS(timing_cfg_3),
+		CFG_REGS(timing_cfg_0),
+		CFG_REGS(timing_cfg_1),
+		CFG_REGS(timing_cfg_2),
+		CFG_REGS(ddr_sdram_cfg),
+		CFG_REGS(ddr_sdram_cfg_2),
+		CFG_REGS(ddr_sdram_mode),
+		CFG_REGS(ddr_sdram_mode_2),
+		CFG_REGS(ddr_sdram_mode_3),
+		CFG_REGS(ddr_sdram_mode_4),
+		CFG_REGS(ddr_sdram_mode_5),
+		CFG_REGS(ddr_sdram_mode_6),
+		CFG_REGS(ddr_sdram_mode_7),
+		CFG_REGS(ddr_sdram_mode_8),
+		CFG_REGS(ddr_sdram_interval),
+		CFG_REGS(ddr_data_init),
+		CFG_REGS(ddr_sdram_clk_cntl),
+		CFG_REGS(ddr_init_addr),
+		CFG_REGS(ddr_init_ext_addr),
+		CFG_REGS(timing_cfg_4),
+		CFG_REGS(timing_cfg_5),
+		CFG_REGS(ddr_zq_cntl),
+		CFG_REGS(ddr_wrlvl_cntl),
+		CFG_REGS(ddr_wrlvl_cntl_2),
+		CFG_REGS(ddr_wrlvl_cntl_3),
+		CFG_REGS(ddr_sr_cntr),
+		CFG_REGS(ddr_sdram_rcw_1),
+		CFG_REGS(ddr_sdram_rcw_2),
+		CFG_REGS(ddr_cdr1),
+		CFG_REGS(ddr_cdr2),
+		CFG_REGS(err_disable),
+		CFG_REGS(err_int_en),
+		CFG_REGS(ddr_sdram_rcw_2),
+		CFG_REGS(ddr_sdram_rcw_2),
+		CFG_REGS(ddr_eor),
+	};
+	static const unsigned int n_opts = ARRAY_SIZE(options);
+
+	debug("fsl_ddr_regs_edit: ctrl_num = %u, "
+		"regname = %s, value = %s\n",
+		ctrl_num, regname, value_str);
+	if (ctrl_num > CONFIG_NUM_DDR_CONTROLLERS)
+		return;
+
+	ddr = &(pinfo->fsl_ddr_config_reg[ctrl_num]);
+
+	if (handle_option_table(options, n_opts, ddr, regname, value_str))
+		return;
+
+	for (i = 0; i < 32; i++) {
+		unsigned int value = simple_strtoul(value_str, NULL, 0);
+		sprintf(buf, "debug_%u", i + 1);
+		if (strcmp(buf, regname) == 0) {
+			ddr->debug[i] = value;
+			return;
+		}
+	}
+	printf("Error: couldn't find register string %s\n", regname);
+}
+
+#define CTRL_OPTIONS_HEX(x) {#x, offsetof(memctl_options_t, x), \
+	sizeof((memctl_options_t *)0)->x, 1}
+
+static void print_memctl_options(const memctl_options_t *popts)
+{
+	static const struct options_string options[] = {
+		CTRL_OPTIONS_CS(0, odt_rd_cfg),
+		CTRL_OPTIONS_CS(0, odt_wr_cfg),
+#if (CONFIG_CHIP_SELECTS_PER_CTRL > 1)
+		CTRL_OPTIONS_CS(1, odt_rd_cfg),
+		CTRL_OPTIONS_CS(1, odt_wr_cfg),
+#endif
+#if (CONFIG_CHIP_SELECTS_PER_CTRL > 2)
+		CTRL_OPTIONS_CS(2, odt_rd_cfg),
+		CTRL_OPTIONS_CS(2, odt_wr_cfg),
+#endif
+#if (CONFIG_CHIP_SELECTS_PER_CTRL > 3)
+		CTRL_OPTIONS_CS(3, odt_rd_cfg),
+		CTRL_OPTIONS_CS(3, odt_wr_cfg),
+#endif
+#if defined(CONFIG_SYS_FSL_DDR3)
+		CTRL_OPTIONS_CS(0, odt_rtt_norm),
+		CTRL_OPTIONS_CS(0, odt_rtt_wr),
+#if (CONFIG_CHIP_SELECTS_PER_CTRL > 1)
+		CTRL_OPTIONS_CS(1, odt_rtt_norm),
+		CTRL_OPTIONS_CS(1, odt_rtt_wr),
+#endif
+#if (CONFIG_CHIP_SELECTS_PER_CTRL > 2)
+		CTRL_OPTIONS_CS(2, odt_rtt_norm),
+		CTRL_OPTIONS_CS(2, odt_rtt_wr),
+#endif
+#if (CONFIG_CHIP_SELECTS_PER_CTRL > 3)
+		CTRL_OPTIONS_CS(3, odt_rtt_norm),
+		CTRL_OPTIONS_CS(3, odt_rtt_wr),
+#endif
+#endif
+		CTRL_OPTIONS(memctl_interleaving),
+		CTRL_OPTIONS(memctl_interleaving_mode),
+		CTRL_OPTIONS_HEX(ba_intlv_ctl),
+		CTRL_OPTIONS(ecc_mode),
+		CTRL_OPTIONS(ecc_init_using_memctl),
+		CTRL_OPTIONS(dqs_config),
+		CTRL_OPTIONS(self_refresh_in_sleep),
+		CTRL_OPTIONS(dynamic_power),
+		CTRL_OPTIONS(data_bus_width),
+		CTRL_OPTIONS(burst_length),
+		CTRL_OPTIONS(cas_latency_override),
+		CTRL_OPTIONS(cas_latency_override_value),
+		CTRL_OPTIONS(use_derated_caslat),
+		CTRL_OPTIONS(additive_latency_override),
+		CTRL_OPTIONS(additive_latency_override_value),
+		CTRL_OPTIONS(clk_adjust),
+		CTRL_OPTIONS(cpo_override),
+		CTRL_OPTIONS(write_data_delay),
+		CTRL_OPTIONS(half_strength_driver_enable),
+		/*
+		 * These can probably be changed to 2T_EN and 3T_EN
+		 * (using a leading numerical character) without problem
+		 */
+		CTRL_OPTIONS(twot_en),
+		CTRL_OPTIONS(threet_en),
+		CTRL_OPTIONS(registered_dimm_en),
+		CTRL_OPTIONS(ap_en),
+		CTRL_OPTIONS(x4_en),
+		CTRL_OPTIONS(bstopre),
+		CTRL_OPTIONS(wrlvl_override),
+		CTRL_OPTIONS(wrlvl_sample),
+		CTRL_OPTIONS(wrlvl_start),
+		CTRL_OPTIONS(rcw_override),
+		CTRL_OPTIONS(rcw_1),
+		CTRL_OPTIONS(rcw_2),
+		CTRL_OPTIONS_HEX(ddr_cdr1),
+		CTRL_OPTIONS_HEX(ddr_cdr2),
+		CTRL_OPTIONS(tcke_clock_pulse_width_ps),
+		CTRL_OPTIONS(tfaw_window_four_activates_ps),
+		CTRL_OPTIONS(trwt_override),
+		CTRL_OPTIONS(trwt),
+	};
+	static const unsigned int n_opts = ARRAY_SIZE(options);
+
+	print_option_table(options, n_opts, popts);
+}
+
+#ifdef CONFIG_SYS_FSL_DDR1
+void ddr1_spd_dump(const ddr1_spd_eeprom_t *spd)
+{
+	unsigned int i;
+
+	printf("%-3d    : %02x %s\n", 0, spd->info_size,
+	       " spd->info_size,   *  0 # bytes written into serial memory *");
+	printf("%-3d    : %02x %s\n", 1, spd->chip_size,
+	       " spd->chip_size,   *  1 Total # bytes of SPD memory device *");
+	printf("%-3d    : %02x %s\n", 2, spd->mem_type,
+	       " spd->mem_type,    *  2 Fundamental memory type *");
+	printf("%-3d    : %02x %s\n", 3, spd->nrow_addr,
+	       " spd->nrow_addr,   *  3 # of Row Addresses on this assembly *");
+	printf("%-3d    : %02x %s\n", 4, spd->ncol_addr,
+	       " spd->ncol_addr,   *  4 # of Column Addrs on this assembly *");
+	printf("%-3d    : %02x %s\n", 5, spd->nrows,
+	       " spd->nrows        *  5 # of DIMM Banks *");
+	printf("%-3d    : %02x %s\n", 6, spd->dataw_lsb,
+	       " spd->dataw_lsb,   *  6 Data Width lsb of this assembly *");
+	printf("%-3d    : %02x %s\n", 7, spd->dataw_msb,
+	       " spd->dataw_msb,   *  7 Data Width msb of this assembly *");
+	printf("%-3d    : %02x %s\n", 8, spd->voltage,
+	       " spd->voltage,     *  8 Voltage intf std of this assembly *");
+	printf("%-3d    : %02x %s\n", 9, spd->clk_cycle,
+	       " spd->clk_cycle,   *  9 SDRAM Cycle time at CL=X *");
+	printf("%-3d    : %02x %s\n", 10, spd->clk_access,
+	       " spd->clk_access,  * 10 SDRAM Access from Clock at CL=X *");
+	printf("%-3d    : %02x %s\n", 11, spd->config,
+	       " spd->config,      * 11 DIMM Configuration type *");
+	printf("%-3d    : %02x %s\n", 12, spd->refresh,
+	       " spd->refresh,     * 12 Refresh Rate/Type *");
+	printf("%-3d    : %02x %s\n", 13, spd->primw,
+	       " spd->primw,       * 13 Primary SDRAM Width *");
+	printf("%-3d    : %02x %s\n", 14, spd->ecw,
+	       " spd->ecw,         * 14 Error Checking SDRAM width *");
+	printf("%-3d    : %02x %s\n", 15, spd->min_delay,
+	       " spd->min_delay,   * 15 Back to Back Random Access *");
+	printf("%-3d    : %02x %s\n", 16, spd->burstl,
+	       " spd->burstl,      * 16 Burst Lengths Supported *");
+	printf("%-3d    : %02x %s\n", 17, spd->nbanks,
+	       " spd->nbanks,      * 17 # of Banks on Each SDRAM Device *");
+	printf("%-3d    : %02x %s\n", 18, spd->cas_lat,
+	       " spd->cas_lat,     * 18 CAS# Latencies Supported *");
+	printf("%-3d    : %02x %s\n", 19, spd->cs_lat,
+	       " spd->cs_lat,      * 19 Chip Select Latency *");
+	printf("%-3d    : %02x %s\n", 20, spd->write_lat,
+	       " spd->write_lat,   * 20 Write Latency/Recovery *");
+	printf("%-3d    : %02x %s\n", 21, spd->mod_attr,
+	       " spd->mod_attr,    * 21 SDRAM Module Attributes *");
+	printf("%-3d    : %02x %s\n", 22, spd->dev_attr,
+	       " spd->dev_attr,    * 22 SDRAM Device Attributes *");
+	printf("%-3d    : %02x %s\n", 23, spd->clk_cycle2,
+	       " spd->clk_cycle2,  * 23 Min SDRAM Cycle time at CL=X-1 *");
+	printf("%-3d    : %02x %s\n", 24, spd->clk_access2,
+	       " spd->clk_access2, * 24 SDRAM Access from Clock at CL=X-1 *");
+	printf("%-3d    : %02x %s\n", 25, spd->clk_cycle3,
+	       " spd->clk_cycle3,  * 25 Min SDRAM Cycle time at CL=X-2 *");
+	printf("%-3d    : %02x %s\n", 26, spd->clk_access3,
+	       " spd->clk_access3, * 26 Max Access from Clock at CL=X-2 *");
+	printf("%-3d    : %02x %s\n", 27, spd->trp,
+	       " spd->trp,         * 27 Min Row Precharge Time (tRP)*");
+	printf("%-3d    : %02x %s\n", 28, spd->trrd,
+	       " spd->trrd,        * 28 Min Row Active to Row Active (tRRD) *");
+	printf("%-3d    : %02x %s\n", 29, spd->trcd,
+	       " spd->trcd,        * 29 Min RAS to CAS Delay (tRCD) *");
+	printf("%-3d    : %02x %s\n", 30, spd->tras,
+	       " spd->tras,        * 30 Minimum RAS Pulse Width (tRAS) *");
+	printf("%-3d    : %02x %s\n", 31, spd->bank_dens,
+	       " spd->bank_dens,   * 31 Density of each bank on module *");
+	printf("%-3d    : %02x %s\n", 32, spd->ca_setup,
+	       " spd->ca_setup,    * 32 Cmd + Addr signal input setup time *");
+	printf("%-3d    : %02x %s\n", 33, spd->ca_hold,
+	       " spd->ca_hold,     * 33 Cmd and Addr signal input hold time *");
+	printf("%-3d    : %02x %s\n", 34, spd->data_setup,
+	       " spd->data_setup,  * 34 Data signal input setup time *");
+	printf("%-3d    : %02x %s\n", 35, spd->data_hold,
+	       " spd->data_hold,   * 35 Data signal input hold time *");
+	printf("%-3d    : %02x %s\n", 36, spd->res_36_40[0],
+	       " spd->res_36_40[0], * 36 Reserved / tWR *");
+	printf("%-3d    : %02x %s\n", 37, spd->res_36_40[1],
+	       " spd->res_36_40[1], * 37 Reserved / tWTR *");
+	printf("%-3d    : %02x %s\n", 38, spd->res_36_40[2],
+	       " spd->res_36_40[2], * 38 Reserved / tRTP *");
+	printf("%-3d    : %02x %s\n", 39, spd->res_36_40[3],
+	       " spd->res_36_40[3], * 39 Reserved / mem_probe *");
+	printf("%-3d    : %02x %s\n", 40, spd->res_36_40[4],
+	       " spd->res_36_40[4], * 40 Reserved / trc,trfc extensions *");
+	printf("%-3d    : %02x %s\n", 41, spd->trc,
+	       " spd->trc,         * 41 Min Active to Auto refresh time tRC *");
+	printf("%-3d    : %02x %s\n", 42, spd->trfc,
+	       " spd->trfc,        * 42 Min Auto to Active period tRFC *");
+	printf("%-3d    : %02x %s\n", 43, spd->tckmax,
+	       " spd->tckmax,      * 43 Max device cycle time tCKmax *");
+	printf("%-3d    : %02x %s\n", 44, spd->tdqsq,
+	       " spd->tdqsq,       * 44 Max DQS to DQ skew *");
+	printf("%-3d    : %02x %s\n", 45, spd->tqhs,
+	       " spd->tqhs,        * 45 Max Read DataHold skew tQHS *");
+	printf("%-3d    : %02x %s\n", 46, spd->res_46,
+	       " spd->res_46,  * 46 Reserved/ PLL Relock time *");
+	printf("%-3d    : %02x %s\n", 47, spd->dimm_height,
+	       " spd->dimm_height  * 47 SDRAM DIMM Height *");
+
+	printf("%-3d-%3d: ",  48, 61);
+
+	for (i = 0; i < 14; i++)
+		printf("%02x", spd->res_48_61[i]);
+
+	printf(" * 48-61 IDD in SPD and Reserved space *\n");
+
+	printf("%-3d    : %02x %s\n", 62, spd->spd_rev,
+	       " spd->spd_rev,     * 62 SPD Data Revision Code *");
+	printf("%-3d    : %02x %s\n", 63, spd->cksum,
+	       " spd->cksum,       * 63 Checksum for bytes 0-62 *");
+	printf("%-3d-%3d: ",  64, 71);
+
+	for (i = 0; i < 8; i++)
+		printf("%02x", spd->mid[i]);
+
+	printf("* 64 Mfr's JEDEC ID code per JEP-108E *\n");
+	printf("%-3d    : %02x %s\n", 72, spd->mloc,
+	       " spd->mloc,        * 72 Manufacturing Location *");
+
+	printf("%-3d-%3d: >>",  73, 90);
+
+	for (i = 0; i < 18; i++)
+		printf("%c", spd->mpart[i]);
+
+	printf("<<* 73 Manufacturer's Part Number *\n");
+
+	printf("%-3d-%3d: %02x %02x %s\n", 91, 92, spd->rev[0], spd->rev[1],
+	       "* 91 Revision Code *");
+	printf("%-3d-%3d: %02x %02x %s\n", 93, 94, spd->mdate[0], spd->mdate[1],
+	       "* 93 Manufacturing Date *");
+	printf("%-3d-%3d: ", 95, 98);
+
+	for (i = 0; i < 4; i++)
+		printf("%02x", spd->sernum[i]);
+
+	printf("* 95 Assembly Serial Number *\n");
+
+	printf("%-3d-%3d: ", 99, 127);
+
+	for (i = 0; i < 27; i++)
+		printf("%02x", spd->mspec[i]);
+
+	printf("* 99 Manufacturer Specific Data *\n");
+}
+#endif
+
+#ifdef CONFIG_SYS_FSL_DDR2
+void ddr2_spd_dump(const ddr2_spd_eeprom_t *spd)
+{
+	unsigned int i;
+
+	printf("%-3d    : %02x %s\n", 0, spd->info_size,
+	       " spd->info_size,   *  0 # bytes written into serial memory *");
+	printf("%-3d    : %02x %s\n", 1, spd->chip_size,
+	       " spd->chip_size,   *  1 Total # bytes of SPD memory device *");
+	printf("%-3d    : %02x %s\n", 2, spd->mem_type,
+	       " spd->mem_type,    *  2 Fundamental memory type *");
+	printf("%-3d    : %02x %s\n", 3, spd->nrow_addr,
+	       " spd->nrow_addr,   *  3 # of Row Addresses on this assembly *");
+	printf("%-3d    : %02x %s\n", 4, spd->ncol_addr,
+	       " spd->ncol_addr,   *  4 # of Column Addrs on this assembly *");
+	printf("%-3d    : %02x %s\n", 5, spd->mod_ranks,
+	       " spd->mod_ranks    *  5 # of Module Rows on this assembly *");
+	printf("%-3d    : %02x %s\n", 6, spd->dataw,
+	       " spd->dataw,       *  6 Data Width of this assembly *");
+	printf("%-3d    : %02x %s\n", 7, spd->res_7,
+	       " spd->res_7,       *  7 Reserved *");
+	printf("%-3d    : %02x %s\n", 8, spd->voltage,
+	       " spd->voltage,     *  8 Voltage intf std of this assembly *");
+	printf("%-3d    : %02x %s\n", 9, spd->clk_cycle,
+	       " spd->clk_cycle,   *  9 SDRAM Cycle time at CL=X *");
+	printf("%-3d    : %02x %s\n", 10, spd->clk_access,
+	       " spd->clk_access,  * 10 SDRAM Access from Clock at CL=X *");
+	printf("%-3d    : %02x %s\n", 11, spd->config,
+	       " spd->config,      * 11 DIMM Configuration type *");
+	printf("%-3d    : %02x %s\n", 12, spd->refresh,
+	       " spd->refresh,     * 12 Refresh Rate/Type *");
+	printf("%-3d    : %02x %s\n", 13, spd->primw,
+	       " spd->primw,       * 13 Primary SDRAM Width *");
+	printf("%-3d    : %02x %s\n", 14, spd->ecw,
+	       " spd->ecw,         * 14 Error Checking SDRAM width *");
+	printf("%-3d    : %02x %s\n", 15, spd->res_15,
+	       " spd->res_15,      * 15 Reserved *");
+	printf("%-3d    : %02x %s\n", 16, spd->burstl,
+	       " spd->burstl,      * 16 Burst Lengths Supported *");
+	printf("%-3d    : %02x %s\n", 17, spd->nbanks,
+	       " spd->nbanks,      * 17 # of Banks on Each SDRAM Device *");
+	printf("%-3d    : %02x %s\n", 18, spd->cas_lat,
+	       " spd->cas_lat,     * 18 CAS# Latencies Supported *");
+	printf("%-3d    : %02x %s\n", 19, spd->mech_char,
+	       " spd->mech_char,   * 19 Mechanical Characteristics *");
+	printf("%-3d    : %02x %s\n", 20, spd->dimm_type,
+	       " spd->dimm_type,   * 20 DIMM type *");
+	printf("%-3d    : %02x %s\n", 21, spd->mod_attr,
+	       " spd->mod_attr,    * 21 SDRAM Module Attributes *");
+	printf("%-3d    : %02x %s\n", 22, spd->dev_attr,
+	       " spd->dev_attr,    * 22 SDRAM Device Attributes *");
+	printf("%-3d    : %02x %s\n", 23, spd->clk_cycle2,
+	       " spd->clk_cycle2,  * 23 Min SDRAM Cycle time at CL=X-1 *");
+	printf("%-3d    : %02x %s\n", 24, spd->clk_access2,
+	       " spd->clk_access2, * 24 SDRAM Access from Clock at CL=X-1 *");
+	printf("%-3d    : %02x %s\n", 25, spd->clk_cycle3,
+	       " spd->clk_cycle3,  * 25 Min SDRAM Cycle time at CL=X-2 *");
+	printf("%-3d    : %02x %s\n", 26, spd->clk_access3,
+	       " spd->clk_access3, * 26 Max Access from Clock at CL=X-2 *");
+	printf("%-3d    : %02x %s\n", 27, spd->trp,
+	       " spd->trp,         * 27 Min Row Precharge Time (tRP)*");
+	printf("%-3d    : %02x %s\n", 28, spd->trrd,
+	       " spd->trrd,        * 28 Min Row Active to Row Active (tRRD) *");
+	printf("%-3d    : %02x %s\n", 29, spd->trcd,
+	       " spd->trcd,        * 29 Min RAS to CAS Delay (tRCD) *");
+	printf("%-3d    : %02x %s\n", 30, spd->tras,
+	       " spd->tras,        * 30 Minimum RAS Pulse Width (tRAS) *");
+	printf("%-3d    : %02x %s\n", 31, spd->rank_dens,
+	       " spd->rank_dens,   * 31 Density of each rank on module *");
+	printf("%-3d    : %02x %s\n", 32, spd->ca_setup,
+	       " spd->ca_setup,    * 32 Cmd + Addr signal input setup time *");
+	printf("%-3d    : %02x %s\n", 33, spd->ca_hold,
+	       " spd->ca_hold,     * 33 Cmd and Addr signal input hold time *");
+	printf("%-3d    : %02x %s\n", 34, spd->data_setup,
+	       " spd->data_setup,  * 34 Data signal input setup time *");
+	printf("%-3d    : %02x %s\n", 35, spd->data_hold,
+	       " spd->data_hold,   * 35 Data signal input hold time *");
+	printf("%-3d    : %02x %s\n", 36, spd->twr,
+	       " spd->twr,         * 36 Write Recovery time tWR *");
+	printf("%-3d    : %02x %s\n", 37, spd->twtr,
+	       " spd->twtr,        * 37 Int write to read delay tWTR *");
+	printf("%-3d    : %02x %s\n", 38, spd->trtp,
+	       " spd->trtp,        * 38 Int read to precharge delay tRTP *");
+	printf("%-3d    : %02x %s\n", 39, spd->mem_probe,
+	       " spd->mem_probe,   * 39 Mem analysis probe characteristics *");
+	printf("%-3d    : %02x %s\n", 40, spd->trctrfc_ext,
+	       " spd->trctrfc_ext, * 40 Extensions to trc and trfc *");
+	printf("%-3d    : %02x %s\n", 41, spd->trc,
+	       " spd->trc,         * 41 Min Active to Auto refresh time tRC *");
+	printf("%-3d    : %02x %s\n", 42, spd->trfc,
+	       " spd->trfc,        * 42 Min Auto to Active period tRFC *");
+	printf("%-3d    : %02x %s\n", 43, spd->tckmax,
+	       " spd->tckmax,      * 43 Max device cycle time tCKmax *");
+	printf("%-3d    : %02x %s\n", 44, spd->tdqsq,
+	       " spd->tdqsq,       * 44 Max DQS to DQ skew *");
+	printf("%-3d    : %02x %s\n", 45, spd->tqhs,
+	       " spd->tqhs,        * 45 Max Read DataHold skew tQHS *");
+	printf("%-3d    : %02x %s\n", 46, spd->pll_relock,
+	       " spd->pll_relock,  * 46 PLL Relock time *");
+	printf("%-3d    : %02x %s\n", 47, spd->t_casemax,
+	       " spd->t_casemax,    * 47 t_casemax *");
+	printf("%-3d    : %02x %s\n", 48, spd->psi_ta_dram,
+	       " spd->psi_ta_dram,   * 48 Thermal Resistance of DRAM Package "
+	       "from Top (Case) to Ambient (Psi T-A DRAM) *");
+	printf("%-3d    : %02x %s\n", 49, spd->dt0_mode,
+	       " spd->dt0_mode,    * 49 DRAM Case Temperature Rise from "
+	       "Ambient due to Activate-Precharge/Mode Bits "
+	       "(DT0/Mode Bits) *)");
+	printf("%-3d    : %02x %s\n", 50, spd->dt2n_dt2q,
+	       " spd->dt2n_dt2q,   * 50 DRAM Case Temperature Rise from "
+	       "Ambient due to Precharge/Quiet Standby "
+	       "(DT2N/DT2Q) *");
+	printf("%-3d    : %02x %s\n", 51, spd->dt2p,
+	       " spd->dt2p,        * 51 DRAM Case Temperature Rise from "
+	       "Ambient due to Precharge Power-Down (DT2P) *");
+	printf("%-3d    : %02x %s\n", 52, spd->dt3n,
+	       " spd->dt3n,        * 52 DRAM Case Temperature Rise from "
+	       "Ambient due to Active Standby (DT3N) *");
+	printf("%-3d    : %02x %s\n", 53, spd->dt3pfast,
+	       " spd->dt3pfast,    * 53 DRAM Case Temperature Rise from "
+	       "Ambient due to Active Power-Down with Fast PDN Exit "
+	       "(DT3Pfast) *");
+	printf("%-3d    : %02x %s\n", 54, spd->dt3pslow,
+	       " spd->dt3pslow,    * 54 DRAM Case Temperature Rise from "
+	       "Ambient due to Active Power-Down with Slow PDN Exit "
+	       "(DT3Pslow) *");
+	printf("%-3d    : %02x %s\n", 55, spd->dt4r_dt4r4w,
+	       " spd->dt4r_dt4r4w, * 55 DRAM Case Temperature Rise from "
+	       "Ambient due to Page Open Burst Read/DT4R4W Mode Bit "
+	       "(DT4R/DT4R4W Mode Bit) *");
+	printf("%-3d    : %02x %s\n", 56, spd->dt5b,
+	       " spd->dt5b,        * 56 DRAM Case Temperature Rise from "
+	       "Ambient due to Burst Refresh (DT5B) *");
+	printf("%-3d    : %02x %s\n", 57, spd->dt7,
+	       " spd->dt7,         * 57 DRAM Case Temperature Rise from "
+	       "Ambient due to Bank Interleave Reads with "
+	       "Auto-Precharge (DT7) *");
+	printf("%-3d    : %02x %s\n", 58, spd->psi_ta_pll,
+	       " spd->psi_ta_pll,    * 58 Thermal Resistance of PLL Package form"
+	       " Top (Case) to Ambient (Psi T-A PLL) *");
+	printf("%-3d    : %02x %s\n", 59, spd->psi_ta_reg,
+	       " spd->psi_ta_reg,    * 59 Thermal Reisitance of Register Package"
+	       " from Top (Case) to Ambient (Psi T-A Register) *");
+	printf("%-3d    : %02x %s\n", 60, spd->dtpllactive,
+	       " spd->dtpllactive, * 60 PLL Case Temperature Rise from "
+	       "Ambient due to PLL Active (DT PLL Active) *");
+	printf("%-3d    : %02x %s\n", 61, spd->dtregact,
+	       " spd->dtregact,    "
+	       "* 61 Register Case Temperature Rise from Ambient due to "
+	       "Register Active/Mode Bit (DT Register Active/Mode Bit) *");
+	printf("%-3d    : %02x %s\n", 62, spd->spd_rev,
+	       " spd->spd_rev,     * 62 SPD Data Revision Code *");
+	printf("%-3d    : %02x %s\n", 63, spd->cksum,
+	       " spd->cksum,       * 63 Checksum for bytes 0-62 *");
+
+	printf("%-3d-%3d: ",  64, 71);
+
+	for (i = 0; i < 8; i++)
+		printf("%02x", spd->mid[i]);
+
+	printf("* 64 Mfr's JEDEC ID code per JEP-108E *\n");
+
+	printf("%-3d    : %02x %s\n", 72, spd->mloc,
+	       " spd->mloc,        * 72 Manufacturing Location *");
+
+	printf("%-3d-%3d: >>",  73, 90);
+	for (i = 0; i < 18; i++)
+		printf("%c", spd->mpart[i]);
+
+
+	printf("<<* 73 Manufacturer's Part Number *\n");
+
+	printf("%-3d-%3d: %02x %02x %s\n", 91, 92, spd->rev[0], spd->rev[1],
+	       "* 91 Revision Code *");
+	printf("%-3d-%3d: %02x %02x %s\n", 93, 94, spd->mdate[0], spd->mdate[1],
+	       "* 93 Manufacturing Date *");
+	printf("%-3d-%3d: ", 95, 98);
+
+	for (i = 0; i < 4; i++)
+		printf("%02x", spd->sernum[i]);
+
+	printf("* 95 Assembly Serial Number *\n");
+
+	printf("%-3d-%3d: ", 99, 127);
+	for (i = 0; i < 27; i++)
+		printf("%02x", spd->mspec[i]);
+
+
+	printf("* 99 Manufacturer Specific Data *\n");
+}
+#endif
+
+#ifdef CONFIG_SYS_FSL_DDR3
+void ddr3_spd_dump(const ddr3_spd_eeprom_t *spd)
+{
+	unsigned int i;
+
+	/* General Section: Bytes 0-59 */
+
+#define PRINT_NXS(x, y, z...) printf("%-3d    : %02x " z "\n", x, (u8)y);
+#define PRINT_NNXXS(n0, n1, x0, x1, s) \
+	printf("%-3d-%3d: %02x %02x " s "\n", n0, n1, x0, x1);
+
+	PRINT_NXS(0, spd->info_size_crc,
+		"info_size_crc  bytes written into serial memory, "
+		"CRC coverage");
+	PRINT_NXS(1, spd->spd_rev,
+		"spd_rev        SPD Revision");
+	PRINT_NXS(2, spd->mem_type,
+		"mem_type       Key Byte / DRAM Device Type");
+	PRINT_NXS(3, spd->module_type,
+		"module_type    Key Byte / Module Type");
+	PRINT_NXS(4, spd->density_banks,
+		"density_banks  SDRAM Density and Banks");
+	PRINT_NXS(5, spd->addressing,
+		"addressing     SDRAM Addressing");
+	PRINT_NXS(6, spd->module_vdd,
+		"module_vdd     Module Nominal Voltage, VDD");
+	PRINT_NXS(7, spd->organization,
+		"organization   Module Organization");
+	PRINT_NXS(8, spd->bus_width,
+		"bus_width      Module Memory Bus Width");
+	PRINT_NXS(9, spd->ftb_div,
+		"ftb_div        Fine Timebase (FTB) Dividend / Divisor");
+	PRINT_NXS(10, spd->mtb_dividend,
+		"mtb_dividend   Medium Timebase (MTB) Dividend");
+	PRINT_NXS(11, spd->mtb_divisor,
+		"mtb_divisor    Medium Timebase (MTB) Divisor");
+	PRINT_NXS(12, spd->tck_min,
+		  "tck_min        SDRAM Minimum Cycle Time");
+	PRINT_NXS(13, spd->res_13,
+		"res_13         Reserved");
+	PRINT_NXS(14, spd->caslat_lsb,
+		"caslat_lsb     CAS Latencies Supported, LSB");
+	PRINT_NXS(15, spd->caslat_msb,
+		"caslat_msb     CAS Latencies Supported, MSB");
+	PRINT_NXS(16, spd->taa_min,
+		  "taa_min        Min CAS Latency Time");
+	PRINT_NXS(17, spd->twr_min,
+		  "twr_min        Min Write REcovery Time");
+	PRINT_NXS(18, spd->trcd_min,
+		  "trcd_min       Min RAS# to CAS# Delay Time");
+	PRINT_NXS(19, spd->trrd_min,
+		  "trrd_min       Min Row Active to Row Active Delay Time");
+	PRINT_NXS(20, spd->trp_min,
+		  "trp_min        Min Row Precharge Delay Time");
+	PRINT_NXS(21, spd->tras_trc_ext,
+		  "tras_trc_ext   Upper Nibbles for tRAS and tRC");
+	PRINT_NXS(22, spd->tras_min_lsb,
+		  "tras_min_lsb   Min Active to Precharge Delay Time, LSB");
+	PRINT_NXS(23, spd->trc_min_lsb,
+		  "trc_min_lsb Min Active to Active/Refresh Delay Time, LSB");
+	PRINT_NXS(24, spd->trfc_min_lsb,
+		  "trfc_min_lsb   Min Refresh Recovery Delay Time LSB");
+	PRINT_NXS(25, spd->trfc_min_msb,
+		  "trfc_min_msb   Min Refresh Recovery Delay Time MSB");
+	PRINT_NXS(26, spd->twtr_min,
+		  "twtr_min Min Internal Write to Read Command Delay Time");
+	PRINT_NXS(27, spd->trtp_min,
+		  "trtp_min "
+		  "Min Internal Read to Precharge Command Delay Time");
+	PRINT_NXS(28, spd->tfaw_msb,
+		  "tfaw_msb       Upper Nibble for tFAW");
+	PRINT_NXS(29, spd->tfaw_min,
+		  "tfaw_min       Min Four Activate Window Delay Time");
+	PRINT_NXS(30, spd->opt_features,
+		"opt_features   SDRAM Optional Features");
+	PRINT_NXS(31, spd->therm_ref_opt,
+		"therm_ref_opt  SDRAM Thermal and Refresh Opts");
+	PRINT_NXS(32, spd->therm_sensor,
+		"therm_sensor  SDRAM Thermal Sensor");
+	PRINT_NXS(33, spd->device_type,
+		"device_type  SDRAM Device Type");
+	PRINT_NXS(34, spd->fine_tck_min,
+		  "fine_tck_min  Fine offset for tCKmin");
+	PRINT_NXS(35, spd->fine_taa_min,
+		  "fine_taa_min  Fine offset for tAAmin");
+	PRINT_NXS(36, spd->fine_trcd_min,
+		  "fine_trcd_min Fine offset for tRCDmin");
+	PRINT_NXS(37, spd->fine_trp_min,
+		  "fine_trp_min  Fine offset for tRPmin");
+	PRINT_NXS(38, spd->fine_trc_min,
+		  "fine_trc_min  Fine offset for tRCmin");
+
+	printf("%-3d-%3d: ",  39, 59);  /* Reserved, General Section */
+
+	for (i = 39; i <= 59; i++)
+		printf("%02x ", spd->res_39_59[i - 39]);
+
+	puts("\n");
+
+	switch (spd->module_type) {
+	case 0x02:  /* UDIMM */
+	case 0x03:  /* SO-DIMM */
+	case 0x04:  /* Micro-DIMM */
+	case 0x06:  /* Mini-UDIMM */
+		PRINT_NXS(60, spd->mod_section.unbuffered.mod_height,
+			"mod_height    (Unbuffered) Module Nominal Height");
+		PRINT_NXS(61, spd->mod_section.unbuffered.mod_thickness,
+			"mod_thickness (Unbuffered) Module Maximum Thickness");
+		PRINT_NXS(62, spd->mod_section.unbuffered.ref_raw_card,
+			"ref_raw_card  (Unbuffered) Reference Raw Card Used");
+		PRINT_NXS(63, spd->mod_section.unbuffered.addr_mapping,
+			"addr_mapping  (Unbuffered) Address mapping from "
+			"Edge Connector to DRAM");
+		break;
+	case 0x01:  /* RDIMM */
+	case 0x05:  /* Mini-RDIMM */
+		PRINT_NXS(60, spd->mod_section.registered.mod_height,
+			"mod_height    (Registered) Module Nominal Height");
+		PRINT_NXS(61, spd->mod_section.registered.mod_thickness,
+			"mod_thickness (Registered) Module Maximum Thickness");
+		PRINT_NXS(62, spd->mod_section.registered.ref_raw_card,
+			"ref_raw_card  (Registered) Reference Raw Card Used");
+		PRINT_NXS(63, spd->mod_section.registered.modu_attr,
+			"modu_attr     (Registered) DIMM Module Attributes");
+		PRINT_NXS(64, spd->mod_section.registered.thermal,
+			"thermal       (Registered) Thermal Heat "
+			"Spreader Solution");
+		PRINT_NXS(65, spd->mod_section.registered.reg_id_lo,
+			"reg_id_lo     (Registered) Register Manufacturer ID "
+			"Code, LSB");
+		PRINT_NXS(66, spd->mod_section.registered.reg_id_hi,
+			"reg_id_hi     (Registered) Register Manufacturer ID "
+			"Code, MSB");
+		PRINT_NXS(67, spd->mod_section.registered.reg_rev,
+			"reg_rev       (Registered) Register "
+			"Revision Number");
+		PRINT_NXS(68, spd->mod_section.registered.reg_type,
+			"reg_type      (Registered) Register Type");
+		for (i = 69; i <= 76; i++) {
+			printf("%-3d    : %02x rcw[%d]\n", i,
+				spd->mod_section.registered.rcw[i-69], i-69);
+		}
+		break;
+	default:
+		/* Module-specific Section, Unsupported Module Type */
+		printf("%-3d-%3d: ", 60, 116);
+
+		for (i = 60; i <= 116; i++)
+			printf("%02x", spd->mod_section.uc[i - 60]);
+
+		break;
+	}
+
+	/* Unique Module ID: Bytes 117-125 */
+	PRINT_NXS(117, spd->mmid_lsb, "Module MfgID Code LSB - JEP-106");
+	PRINT_NXS(118, spd->mmid_msb, "Module MfgID Code MSB - JEP-106");
+	PRINT_NXS(119, spd->mloc,     "Mfg Location");
+	PRINT_NNXXS(120, 121, spd->mdate[0], spd->mdate[1], "Mfg Date");
+
+	printf("%-3d-%3d: ", 122, 125);
+
+	for (i = 122; i <= 125; i++)
+		printf("%02x ", spd->sernum[i - 122]);
+	printf("   Module Serial Number\n");
+
+	/* CRC: Bytes 126-127 */
+	PRINT_NNXXS(126, 127, spd->crc[0], spd->crc[1], "  SPD CRC");
+
+	/* Other Manufacturer Fields and User Space: Bytes 128-255 */
+	printf("%-3d-%3d: ", 128, 145);
+	for (i = 128; i <= 145; i++)
+		printf("%02x ", spd->mpart[i - 128]);
+	printf("   Mfg's Module Part Number\n");
+
+	PRINT_NNXXS(146, 147, spd->mrev[0], spd->mrev[1],
+		"Module Revision code");
+
+	PRINT_NXS(148, spd->dmid_lsb, "DRAM MfgID Code LSB - JEP-106");
+	PRINT_NXS(149, spd->dmid_msb, "DRAM MfgID Code MSB - JEP-106");
+
+	printf("%-3d-%3d: ", 150, 175);
+	for (i = 150; i <= 175; i++)
+		printf("%02x ", spd->msd[i - 150]);
+	printf("   Mfg's Specific Data\n");
+
+	printf("%-3d-%3d: ", 176, 255);
+	for (i = 176; i <= 255; i++)
+		printf("%02x", spd->cust[i - 176]);
+	printf("   Mfg's Specific Data\n");
+
+}
+#endif
+
+static inline void generic_spd_dump(const generic_spd_eeprom_t *spd)
+{
+#if defined(CONFIG_SYS_FSL_DDR1)
+	ddr1_spd_dump(spd);
+#elif defined(CONFIG_SYS_FSL_DDR2)
+	ddr2_spd_dump(spd);
+#elif defined(CONFIG_SYS_FSL_DDR3)
+	ddr3_spd_dump(spd);
+#endif
+}
+
+static void fsl_ddr_printinfo(const fsl_ddr_info_t *pinfo,
+			unsigned int ctrl_mask,
+			unsigned int dimm_mask,
+			unsigned int do_mask)
+{
+	unsigned int i, j, retval;
+
+	/* STEP 1:  DIMM SPD data */
+	if (do_mask & STEP_GET_SPD) {
+		for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
+			if (!(ctrl_mask & (1 << i)))
+				continue;
+
+			for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
+				if (!(dimm_mask & (1 << j)))
+					continue;
+
+				printf("SPD info:  Controller=%u "
+						"DIMM=%u\n", i, j);
+				generic_spd_dump(
+					&(pinfo->spd_installed_dimms[i][j]));
+				printf("\n");
+			}
+			printf("\n");
+		}
+		printf("\n");
+	}
+
+	/* STEP 2:  DIMM Parameters */
+	if (do_mask & STEP_COMPUTE_DIMM_PARMS) {
+		for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
+			if (!(ctrl_mask & (1 << i)))
+				continue;
+			for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
+				if (!(dimm_mask & (1 << j)))
+					continue;
+				printf("DIMM parameters:  Controller=%u "
+						"DIMM=%u\n", i, j);
+				print_dimm_parameters(
+					&(pinfo->dimm_params[i][j]));
+				printf("\n");
+			}
+			printf("\n");
+		}
+		printf("\n");
+	}
+
+	/* STEP 3:  Common Parameters */
+	if (do_mask & STEP_COMPUTE_COMMON_PARMS) {
+		for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
+			if (!(ctrl_mask & (1 << i)))
+				continue;
+			printf("\"lowest common\" DIMM parameters:  "
+					"Controller=%u\n", i);
+			print_lowest_common_dimm_parameters(
+				&pinfo->common_timing_params[i]);
+			printf("\n");
+		}
+		printf("\n");
+	}
+
+	/* STEP 4:  User Configuration Options */
+	if (do_mask & STEP_GATHER_OPTS) {
+		for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
+			if (!(ctrl_mask & (1 << i)))
+				continue;
+			printf("User Config Options: Controller=%u\n", i);
+			print_memctl_options(&pinfo->memctl_opts[i]);
+			printf("\n");
+		}
+		printf("\n");
+	}
+
+	/* STEP 5:  Address assignment */
+	if (do_mask & STEP_ASSIGN_ADDRESSES) {
+		for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
+			if (!(ctrl_mask & (1 << i)))
+				continue;
+			for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
+				printf("Address Assignment: Controller=%u "
+						"DIMM=%u\n", i, j);
+				printf("Don't have this functionality yet\n");
+			}
+			printf("\n");
+		}
+		printf("\n");
+	}
+
+	/* STEP 6:  computed controller register values */
+	if (do_mask & STEP_COMPUTE_REGS) {
+		for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
+			if (!(ctrl_mask & (1 << i)))
+				continue;
+			printf("Computed Register Values: Controller=%u\n", i);
+			print_fsl_memctl_config_regs(
+				&pinfo->fsl_ddr_config_reg[i]);
+			retval = check_fsl_memctl_config_regs(
+				&pinfo->fsl_ddr_config_reg[i]);
+			if (retval) {
+				printf("check_fsl_memctl_config_regs "
+					"result = %u\n", retval);
+			}
+			printf("\n");
+		}
+		printf("\n");
+	}
+}
+
+struct data_strings {
+	const char *data_name;
+	unsigned int step_mask;
+	unsigned int dimm_number_required;
+};
+
+#define DATA_OPTIONS(name, step, dimm) {#name, step, dimm}
+
+static unsigned int fsl_ddr_parse_interactive_cmd(
+	char **argv,
+	int argc,
+	unsigned int *pstep_mask,
+	unsigned int *pctlr_mask,
+	unsigned int *pdimm_mask,
+	unsigned int *pdimm_number_required
+	 ) {
+
+	static const struct data_strings options[] = {
+		DATA_OPTIONS(spd, STEP_GET_SPD, 1),
+		DATA_OPTIONS(dimmparms, STEP_COMPUTE_DIMM_PARMS, 1),
+		DATA_OPTIONS(commonparms, STEP_COMPUTE_COMMON_PARMS, 0),
+		DATA_OPTIONS(opts, STEP_GATHER_OPTS, 0),
+		DATA_OPTIONS(addresses, STEP_ASSIGN_ADDRESSES, 0),
+		DATA_OPTIONS(regs, STEP_COMPUTE_REGS, 0),
+	};
+	static const unsigned int n_opts = ARRAY_SIZE(options);
+
+	unsigned int i, j;
+	unsigned int error = 0;
+
+	for (i = 1; i < argc; i++) {
+		unsigned int matched = 0;
+
+		for (j = 0; j < n_opts; j++) {
+			if (strcmp(options[j].data_name, argv[i]) != 0)
+				continue;
+			*pstep_mask |= options[j].step_mask;
+			*pdimm_number_required =
+				options[j].dimm_number_required;
+			matched = 1;
+			break;
+		}
+
+		if (matched)
+			continue;
+
+		if (argv[i][0] == 'c') {
+			char c = argv[i][1];
+			if (isdigit(c))
+				*pctlr_mask |= 1 << (c - '0');
+			continue;
+		}
+
+		if (argv[i][0] == 'd') {
+			char c = argv[i][1];
+			if (isdigit(c))
+				*pdimm_mask |= 1 << (c - '0');
+			continue;
+		}
+
+		printf("unknown arg %s\n", argv[i]);
+		*pstep_mask = 0;
+		error = 1;
+		break;
+	}
+
+	return error;
+}
+
+int fsl_ddr_interactive_env_var_exists(void)
+{
+	char buffer[CONFIG_SYS_CBSIZE];
+
+	if (getenv_f("ddr_interactive", buffer, CONFIG_SYS_CBSIZE) >= 0)
+		return 1;
+
+	return 0;
+}
+
+unsigned long long fsl_ddr_interactive(fsl_ddr_info_t *pinfo, int var_is_set)
+{
+	unsigned long long ddrsize;
+	const char *prompt = "FSL DDR>";
+	char buffer[CONFIG_SYS_CBSIZE];
+	char buffer2[CONFIG_SYS_CBSIZE];
+	char *p = NULL;
+	char *argv[CONFIG_SYS_MAXARGS + 1];	/* NULL terminated */
+	int argc;
+	unsigned int next_step = STEP_GET_SPD;
+	const char *usage = {
+		"commands:\n"
+		"print      print SPD and intermediate computed data\n"
+		"reset      reboot machine\n"
+		"recompute  reload SPD and options to default and recompute regs\n"
+		"edit       modify spd, parameter, or option\n"
+		"compute    recompute registers from current next_step to end\n"
+		"copy       copy parameters\n"
+		"next_step  shows current next_step\n"
+		"help       this message\n"
+		"go         program the memory controller and continue with u-boot\n"
+	};
+
+	if (var_is_set) {
+		if (getenv_f("ddr_interactive", buffer2, CONFIG_SYS_CBSIZE) > 0) {
+			p = buffer2;
+		} else {
+			var_is_set = 0;
+		}
+	}
+
+	/*
+	 * The strategy for next_step is that it points to the next
+	 * step in the computation process that needs to be done.
+	 */
+	while (1) {
+		if (var_is_set) {
+			char *pend = strchr(p, ';');
+			if (pend) {
+				/* found command separator, copy sub-command */
+				*pend = '\0';
+				strcpy(buffer, p);
+				p = pend + 1;
+			} else {
+				/* separator not found, copy whole string */
+				strcpy(buffer, p);
+				p = NULL;
+				var_is_set = 0;
+			}
+		} else {
+			/*
+			 * No need to worry for buffer overflow here in
+			 * this function;  readline() maxes out at CFG_CBSIZE
+			 */
+			readline_into_buffer(prompt, buffer, 0);
+		}
+		argc = parse_line(buffer, argv);
+		if (argc == 0)
+			continue;
+
+
+		if (strcmp(argv[0], "help") == 0) {
+			puts(usage);
+			continue;
+		}
+
+		if (strcmp(argv[0], "next_step") == 0) {
+			printf("next_step = 0x%02X (%s)\n",
+			       next_step,
+			       step_to_string(next_step));
+			continue;
+		}
+
+		if (strcmp(argv[0], "copy") == 0) {
+			unsigned int error = 0;
+			unsigned int step_mask = 0;
+			unsigned int src_ctlr_mask = 0;
+			unsigned int src_dimm_mask = 0;
+			unsigned int dimm_number_required = 0;
+			unsigned int src_ctlr_num = 0;
+			unsigned int src_dimm_num = 0;
+			unsigned int dst_ctlr_num = -1;
+			unsigned int dst_dimm_num = -1;
+			unsigned int i, num_dest_parms;
+
+			if (argc == 1) {
+				printf("copy <src c#> <src d#> <spd|dimmparms|commonparms|opts|addresses|regs> <dst c#> <dst d#>\n");
+				continue;
+			}
+
+			error = fsl_ddr_parse_interactive_cmd(
+				argv, argc,
+				&step_mask,
+				&src_ctlr_mask,
+				&src_dimm_mask,
+				&dimm_number_required
+			);
+
+			/* XXX: only dimm_number_required and step_mask will
+			   be used by this function.  Parse the controller and
+			   DIMM number separately because it is easier.  */
+
+			if (error)
+				continue;
+
+			/* parse source destination controller / DIMM */
+
+			num_dest_parms = dimm_number_required ? 2 : 1;
+
+			for (i = 0; i < argc; i++) {
+				if (argv[i][0] == 'c') {
+					char c = argv[i][1];
+					if (isdigit(c)) {
+						src_ctlr_num = (c - '0');
+						break;
+					}
+				}
+			}
+
+			for (i = 0; i < argc; i++) {
+				if (argv[i][0] == 'd') {
+					char c = argv[i][1];
+					if (isdigit(c)) {
+						src_dimm_num = (c - '0');
+						break;
+					}
+				}
+			}
+
+			/* parse destination controller / DIMM */
+
+			for (i = argc - 1; i >= argc - num_dest_parms; i--) {
+				if (argv[i][0] == 'c') {
+					char c = argv[i][1];
+					if (isdigit(c)) {
+						dst_ctlr_num = (c - '0');
+						break;
+					}
+				}
+			}
+
+			for (i = argc - 1; i >= argc - num_dest_parms; i--) {
+				if (argv[i][0] == 'd') {
+					char c = argv[i][1];
+					if (isdigit(c)) {
+						dst_dimm_num = (c - '0');
+						break;
+					}
+				}
+			}
+
+			/* TODO: validate inputs */
+
+			debug("src_ctlr_num = %u, src_dimm_num = %u, dst_ctlr_num = %u, dst_dimm_num = %u, step_mask = %x\n",
+				src_ctlr_num, src_dimm_num, dst_ctlr_num, dst_dimm_num, step_mask);
+
+
+			switch (step_mask) {
+
+			case STEP_GET_SPD:
+				memcpy(&(pinfo->spd_installed_dimms[dst_ctlr_num][dst_dimm_num]),
+					&(pinfo->spd_installed_dimms[src_ctlr_num][src_dimm_num]),
+					sizeof(pinfo->spd_installed_dimms[0][0]));
+				break;
+
+			case STEP_COMPUTE_DIMM_PARMS:
+				memcpy(&(pinfo->dimm_params[dst_ctlr_num][dst_dimm_num]),
+					&(pinfo->dimm_params[src_ctlr_num][src_dimm_num]),
+					sizeof(pinfo->dimm_params[0][0]));
+				break;
+
+			case STEP_COMPUTE_COMMON_PARMS:
+				memcpy(&(pinfo->common_timing_params[dst_ctlr_num]),
+					&(pinfo->common_timing_params[src_ctlr_num]),
+					sizeof(pinfo->common_timing_params[0]));
+				break;
+
+			case STEP_GATHER_OPTS:
+				memcpy(&(pinfo->memctl_opts[dst_ctlr_num]),
+					&(pinfo->memctl_opts[src_ctlr_num]),
+					sizeof(pinfo->memctl_opts[0]));
+				break;
+
+			/* someday be able to have addresses to copy addresses... */
+
+			case STEP_COMPUTE_REGS:
+				memcpy(&(pinfo->fsl_ddr_config_reg[dst_ctlr_num]),
+					&(pinfo->fsl_ddr_config_reg[src_ctlr_num]),
+					sizeof(pinfo->memctl_opts[0]));
+				break;
+
+			default:
+				printf("unexpected step_mask value\n");
+			}
+
+			continue;
+
+		}
+
+		if (strcmp(argv[0], "edit") == 0) {
+			unsigned int error = 0;
+			unsigned int step_mask = 0;
+			unsigned int ctlr_mask = 0;
+			unsigned int dimm_mask = 0;
+			char *p_element = NULL;
+			char *p_value = NULL;
+			unsigned int dimm_number_required = 0;
+			unsigned int ctrl_num;
+			unsigned int dimm_num;
+
+			if (argc == 1) {
+				/* Only the element and value must be last */
+				printf("edit <c#> <d#> "
+					"<spd|dimmparms|commonparms|opts|"
+					"addresses|regs> <element> <value>\n");
+				printf("for spd, specify byte number for "
+					"element\n");
+				continue;
+			}
+
+			error = fsl_ddr_parse_interactive_cmd(
+				argv, argc - 2,
+				&step_mask,
+				&ctlr_mask,
+				&dimm_mask,
+				&dimm_number_required
+			);
+
+			if (error)
+				continue;
+
+
+			/* Check arguments */
+
+			/* ERROR: If no steps were found */
+			if (step_mask == 0) {
+				printf("Error: No valid steps were specified "
+						"in argument.\n");
+				continue;
+			}
+
+			/* ERROR: If multiple steps were found */
+			if (step_mask & (step_mask - 1)) {
+				printf("Error: Multiple steps specified in "
+						"argument.\n");
+				continue;
+			}
+
+			/* ERROR: Controller not specified */
+			if (ctlr_mask == 0) {
+				printf("Error: controller number not "
+					"specified or no element and "
+					"value specified\n");
+				continue;
+			}
+
+			if (ctlr_mask & (ctlr_mask - 1)) {
+				printf("Error: multiple controllers "
+						"specified, %X\n", ctlr_mask);
+				continue;
+			}
+
+			/* ERROR: DIMM number not specified */
+			if (dimm_number_required && dimm_mask == 0) {
+				printf("Error: DIMM number number not "
+					"specified or no element and "
+					"value specified\n");
+				continue;
+			}
+
+			if (dimm_mask & (dimm_mask - 1)) {
+				printf("Error: multipled DIMMs specified\n");
+				continue;
+			}
+
+			p_element = argv[argc - 2];
+			p_value = argv[argc - 1];
+
+			ctrl_num = __ilog2(ctlr_mask);
+			dimm_num = __ilog2(dimm_mask);
+
+			switch (step_mask) {
+			case STEP_GET_SPD:
+				{
+					unsigned int element_num;
+					unsigned int value;
+
+					element_num = simple_strtoul(p_element,
+								     NULL, 0);
+					value = simple_strtoul(p_value,
+							       NULL, 0);
+					fsl_ddr_spd_edit(pinfo,
+							       ctrl_num,
+							       dimm_num,
+							       element_num,
+							       value);
+					next_step = STEP_COMPUTE_DIMM_PARMS;
+				}
+				break;
+
+			case STEP_COMPUTE_DIMM_PARMS:
+				fsl_ddr_dimm_parameters_edit(
+						 pinfo, ctrl_num, dimm_num,
+						 p_element, p_value);
+				next_step = STEP_COMPUTE_COMMON_PARMS;
+				break;
+
+			case STEP_COMPUTE_COMMON_PARMS:
+				lowest_common_dimm_parameters_edit(pinfo,
+						ctrl_num, p_element, p_value);
+				next_step = STEP_GATHER_OPTS;
+				break;
+
+			case STEP_GATHER_OPTS:
+				fsl_ddr_options_edit(pinfo, ctrl_num,
+							   p_element, p_value);
+				next_step = STEP_ASSIGN_ADDRESSES;
+				break;
+
+			case STEP_ASSIGN_ADDRESSES:
+				printf("editing of address assignment "
+						"not yet implemented\n");
+				break;
+
+			case STEP_COMPUTE_REGS:
+				{
+					fsl_ddr_regs_edit(pinfo,
+								ctrl_num,
+								p_element,
+								p_value);
+					next_step = STEP_PROGRAM_REGS;
+				}
+				break;
+
+			default:
+				printf("programming error\n");
+				while (1)
+					;
+				break;
+			}
+			continue;
+		}
+
+		if (strcmp(argv[0], "reset") == 0) {
+			/*
+			 * Reboot machine.
+			 * Args don't seem to matter because this
+			 * doesn't return
+			 */
+			do_reset(NULL, 0, 0, NULL);
+			printf("Reset didn't work\n");
+		}
+
+		if (strcmp(argv[0], "recompute") == 0) {
+			/*
+			 * Recalculate everything, starting with
+			 * loading SPD EEPROM from DIMMs
+			 */
+			next_step = STEP_GET_SPD;
+			ddrsize = fsl_ddr_compute(pinfo, next_step, 0);
+			continue;
+		}
+
+		if (strcmp(argv[0], "compute") == 0) {
+			/*
+			 * Compute rest of steps starting at
+			 * the current next_step/
+			 */
+			ddrsize = fsl_ddr_compute(pinfo, next_step, 0);
+			continue;
+		}
+
+		if (strcmp(argv[0], "print") == 0) {
+			unsigned int error = 0;
+			unsigned int step_mask = 0;
+			unsigned int ctlr_mask = 0;
+			unsigned int dimm_mask = 0;
+			unsigned int dimm_number_required = 0;
+
+			if (argc == 1) {
+				printf("print [c<n>] [d<n>] [spd] [dimmparms] "
+				  "[commonparms] [opts] [addresses] [regs]\n");
+				continue;
+			}
+
+			error = fsl_ddr_parse_interactive_cmd(
+				argv, argc,
+				&step_mask,
+				&ctlr_mask,
+				&dimm_mask,
+				&dimm_number_required
+			);
+
+			if (error)
+				continue;
+
+			/* If no particular controller was found, print all */
+			if (ctlr_mask == 0)
+				ctlr_mask = 0xFF;
+
+			/* If no particular dimm was found, print all dimms. */
+			if (dimm_mask == 0)
+				dimm_mask = 0xFF;
+
+			/* If no steps were found, print all steps. */
+			if (step_mask == 0)
+				step_mask = STEP_ALL;
+
+			fsl_ddr_printinfo(pinfo, ctlr_mask,
+						dimm_mask, step_mask);
+			continue;
+		}
+
+		if (strcmp(argv[0], "go") == 0) {
+			if (next_step)
+				ddrsize = fsl_ddr_compute(pinfo, next_step, 0);
+			break;
+		}
+
+		printf("unknown command %s\n", argv[0]);
+	}
+
+	debug("end of memory = %llu\n", (u64)ddrsize);
+
+	return ddrsize;
+}
diff --git a/drivers/ddr/fsl/lc_common_dimm_params.c b/drivers/ddr/fsl/lc_common_dimm_params.c
new file mode 100644
index 0000000000..610318ad1e
--- /dev/null
+++ b/drivers/ddr/fsl/lc_common_dimm_params.c
@@ -0,0 +1,526 @@
+/*
+ * Copyright 2008-2012 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * Version 2 as published by the Free Software Foundation.
+ */
+
+#include <common.h>
+#include <fsl_ddr_sdram.h>
+
+#include <fsl_ddr.h>
+
+#if defined(CONFIG_SYS_FSL_DDR3)
+static unsigned int
+compute_cas_latency_ddr3(const dimm_params_t *dimm_params,
+			 common_timing_params_t *outpdimm,
+			 unsigned int number_of_dimms)
+{
+	unsigned int i;
+	unsigned int taamin_ps = 0;
+	unsigned int tckmin_x_ps = 0;
+	unsigned int common_caslat;
+	unsigned int caslat_actual;
+	unsigned int retry = 16;
+	unsigned int tmp;
+	const unsigned int mclk_ps = get_memory_clk_period_ps();
+
+	/* compute the common CAS latency supported between slots */
+	tmp = dimm_params[0].caslat_x;
+	for (i = 1; i < number_of_dimms; i++) {
+		if (dimm_params[i].n_ranks)
+			tmp &= dimm_params[i].caslat_x;
+	}
+	common_caslat = tmp;
+
+	/* compute the max tAAmin tCKmin between slots */
+	for (i = 0; i < number_of_dimms; i++) {
+		taamin_ps = max(taamin_ps, dimm_params[i].taa_ps);
+		tckmin_x_ps = max(tckmin_x_ps, dimm_params[i].tckmin_x_ps);
+	}
+	/* validate if the memory clk is in the range of dimms */
+	if (mclk_ps < tckmin_x_ps) {
+		printf("DDR clock (MCLK cycle %u ps) is faster than "
+			"the slowest DIMM(s) (tCKmin %u ps) can support.\n",
+			mclk_ps, tckmin_x_ps);
+	}
+	/* determine the acutal cas latency */
+	caslat_actual = (taamin_ps + mclk_ps - 1) / mclk_ps;
+	/* check if the dimms support the CAS latency */
+	while (!(common_caslat & (1 << caslat_actual)) && retry > 0) {
+		caslat_actual++;
+		retry--;
+	}
+	/* once the caculation of caslat_actual is completed
+	 * we must verify that this CAS latency value does not
+	 * exceed tAAmax, which is 20 ns for all DDR3 speed grades
+	 */
+	if (caslat_actual * mclk_ps > 20000) {
+		printf("The choosen cas latency %d is too large\n",
+			caslat_actual);
+	}
+	outpdimm->lowest_common_SPD_caslat = caslat_actual;
+
+	return 0;
+}
+#endif
+
+/*
+ * compute_lowest_common_dimm_parameters()
+ *
+ * Determine the worst-case DIMM timing parameters from the set of DIMMs
+ * whose parameters have been computed into the array pointed to
+ * by dimm_params.
+ */
+unsigned int
+compute_lowest_common_dimm_parameters(const dimm_params_t *dimm_params,
+				      common_timing_params_t *outpdimm,
+				      const unsigned int number_of_dimms)
+{
+	unsigned int i, j;
+
+	unsigned int tckmin_x_ps = 0;
+	unsigned int tckmax_ps = 0xFFFFFFFF;
+	unsigned int tckmax_max_ps = 0;
+	unsigned int trcd_ps = 0;
+	unsigned int trp_ps = 0;
+	unsigned int tras_ps = 0;
+	unsigned int twr_ps = 0;
+	unsigned int twtr_ps = 0;
+	unsigned int trfc_ps = 0;
+	unsigned int trrd_ps = 0;
+	unsigned int trc_ps = 0;
+	unsigned int refresh_rate_ps = 0;
+	unsigned int extended_op_srt = 1;
+	unsigned int tis_ps = 0;
+	unsigned int tih_ps = 0;
+	unsigned int tds_ps = 0;
+	unsigned int tdh_ps = 0;
+	unsigned int trtp_ps = 0;
+	unsigned int tdqsq_max_ps = 0;
+	unsigned int tqhs_ps = 0;
+
+	unsigned int temp1, temp2;
+	unsigned int additive_latency = 0;
+#if !defined(CONFIG_SYS_FSL_DDR3)
+	const unsigned int mclk_ps = get_memory_clk_period_ps();
+	unsigned int lowest_good_caslat;
+	unsigned int not_ok;
+
+	debug("using mclk_ps = %u\n", mclk_ps);
+#endif
+
+	temp1 = 0;
+	for (i = 0; i < number_of_dimms; i++) {
+		/*
+		 * If there are no ranks on this DIMM,
+		 * it probably doesn't exist, so skip it.
+		 */
+		if (dimm_params[i].n_ranks == 0) {
+			temp1++;
+			continue;
+		}
+		if (dimm_params[i].n_ranks == 4 && i != 0) {
+			printf("Found Quad-rank DIMM in wrong bank, ignored."
+				" Software may not run as expected.\n");
+			temp1++;
+			continue;
+		}
+
+		/*
+		 * check if quad-rank DIMM is plugged if
+		 * CONFIG_CHIP_SELECT_QUAD_CAPABLE is not defined
+		 * Only the board with proper design is capable
+		 */
+#ifndef CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
+		if (dimm_params[i].n_ranks == 4 && \
+		  CONFIG_CHIP_SELECTS_PER_CTRL/CONFIG_DIMM_SLOTS_PER_CTLR < 4) {
+			printf("Found Quad-rank DIMM, not able to support.");
+			temp1++;
+			continue;
+		}
+#endif
+		/*
+		 * Find minimum tckmax_ps to find fastest slow speed,
+		 * i.e., this is the slowest the whole system can go.
+		 */
+		tckmax_ps = min(tckmax_ps, dimm_params[i].tckmax_ps);
+
+		/* Either find maximum value to determine slowest
+		 * speed, delay, time, period, etc */
+		tckmin_x_ps = max(tckmin_x_ps, dimm_params[i].tckmin_x_ps);
+		tckmax_max_ps = max(tckmax_max_ps, dimm_params[i].tckmax_ps);
+		trcd_ps = max(trcd_ps, dimm_params[i].trcd_ps);
+		trp_ps = max(trp_ps, dimm_params[i].trp_ps);
+		tras_ps = max(tras_ps, dimm_params[i].tras_ps);
+		twr_ps = max(twr_ps, dimm_params[i].twr_ps);
+		twtr_ps = max(twtr_ps, dimm_params[i].twtr_ps);
+		trfc_ps = max(trfc_ps, dimm_params[i].trfc_ps);
+		trrd_ps = max(trrd_ps, dimm_params[i].trrd_ps);
+		trc_ps = max(trc_ps, dimm_params[i].trc_ps);
+		tis_ps = max(tis_ps, dimm_params[i].tis_ps);
+		tih_ps = max(tih_ps, dimm_params[i].tih_ps);
+		tds_ps = max(tds_ps, dimm_params[i].tds_ps);
+		tdh_ps = max(tdh_ps, dimm_params[i].tdh_ps);
+		trtp_ps = max(trtp_ps, dimm_params[i].trtp_ps);
+		tqhs_ps = max(tqhs_ps, dimm_params[i].tqhs_ps);
+		refresh_rate_ps = max(refresh_rate_ps,
+				      dimm_params[i].refresh_rate_ps);
+		/* extended_op_srt is either 0 or 1, 0 having priority */
+		extended_op_srt = min(extended_op_srt,
+				      dimm_params[i].extended_op_srt);
+
+		/*
+		 * Find maximum tdqsq_max_ps to find slowest.
+		 *
+		 * FIXME: is finding the slowest value the correct
+		 * strategy for this parameter?
+		 */
+		tdqsq_max_ps = max(tdqsq_max_ps, dimm_params[i].tdqsq_max_ps);
+	}
+
+	outpdimm->ndimms_present = number_of_dimms - temp1;
+
+	if (temp1 == number_of_dimms) {
+		debug("no dimms this memory controller\n");
+		return 0;
+	}
+
+	outpdimm->tckmin_x_ps = tckmin_x_ps;
+	outpdimm->tckmax_ps = tckmax_ps;
+	outpdimm->tckmax_max_ps = tckmax_max_ps;
+	outpdimm->trcd_ps = trcd_ps;
+	outpdimm->trp_ps = trp_ps;
+	outpdimm->tras_ps = tras_ps;
+	outpdimm->twr_ps = twr_ps;
+	outpdimm->twtr_ps = twtr_ps;
+	outpdimm->trfc_ps = trfc_ps;
+	outpdimm->trrd_ps = trrd_ps;
+	outpdimm->trc_ps = trc_ps;
+	outpdimm->refresh_rate_ps = refresh_rate_ps;
+	outpdimm->extended_op_srt = extended_op_srt;
+	outpdimm->tis_ps = tis_ps;
+	outpdimm->tih_ps = tih_ps;
+	outpdimm->tds_ps = tds_ps;
+	outpdimm->tdh_ps = tdh_ps;
+	outpdimm->trtp_ps = trtp_ps;
+	outpdimm->tdqsq_max_ps = tdqsq_max_ps;
+	outpdimm->tqhs_ps = tqhs_ps;
+
+	/* Determine common burst length for all DIMMs. */
+	temp1 = 0xff;
+	for (i = 0; i < number_of_dimms; i++) {
+		if (dimm_params[i].n_ranks) {
+			temp1 &= dimm_params[i].burst_lengths_bitmask;
+		}
+	}
+	outpdimm->all_dimms_burst_lengths_bitmask = temp1;
+
+	/* Determine if all DIMMs registered buffered. */
+	temp1 = temp2 = 0;
+	for (i = 0; i < number_of_dimms; i++) {
+		if (dimm_params[i].n_ranks) {
+			if (dimm_params[i].registered_dimm) {
+				temp1 = 1;
+#ifndef CONFIG_SPL_BUILD
+				printf("Detected RDIMM %s\n",
+					dimm_params[i].mpart);
+#endif
+			} else {
+				temp2 = 1;
+#ifndef CONFIG_SPL_BUILD
+				printf("Detected UDIMM %s\n",
+					dimm_params[i].mpart);
+#endif
+			}
+		}
+	}
+
+	outpdimm->all_dimms_registered = 0;
+	outpdimm->all_dimms_unbuffered = 0;
+	if (temp1 && !temp2) {
+		outpdimm->all_dimms_registered = 1;
+	} else if (!temp1 && temp2) {
+		outpdimm->all_dimms_unbuffered = 1;
+	} else {
+		printf("ERROR:  Mix of registered buffered and unbuffered "
+				"DIMMs detected!\n");
+	}
+
+	temp1 = 0;
+	if (outpdimm->all_dimms_registered)
+		for (j = 0; j < 16; j++) {
+			outpdimm->rcw[j] = dimm_params[0].rcw[j];
+			for (i = 1; i < number_of_dimms; i++) {
+				if (!dimm_params[i].n_ranks)
+					continue;
+				if (dimm_params[i].rcw[j] != dimm_params[0].rcw[j]) {
+					temp1 = 1;
+					break;
+				}
+			}
+		}
+
+	if (temp1 != 0)
+		printf("ERROR: Mix different RDIMM detected!\n");
+
+#if defined(CONFIG_SYS_FSL_DDR3)
+	if (compute_cas_latency_ddr3(dimm_params, outpdimm, number_of_dimms))
+		return 1;
+#else
+	/*
+	 * Compute a CAS latency suitable for all DIMMs
+	 *
+	 * Strategy for SPD-defined latencies: compute only
+	 * CAS latency defined by all DIMMs.
+	 */
+
+	/*
+	 * Step 1: find CAS latency common to all DIMMs using bitwise
+	 * operation.
+	 */
+	temp1 = 0xFF;
+	for (i = 0; i < number_of_dimms; i++) {
+		if (dimm_params[i].n_ranks) {
+			temp2 = 0;
+			temp2 |= 1 << dimm_params[i].caslat_x;
+			temp2 |= 1 << dimm_params[i].caslat_x_minus_1;
+			temp2 |= 1 << dimm_params[i].caslat_x_minus_2;
+			/*
+			 * FIXME: If there was no entry for X-2 (X-1) in
+			 * the SPD, then caslat_x_minus_2
+			 * (caslat_x_minus_1) contains either 255 or
+			 * 0xFFFFFFFF because that's what the glorious
+			 * __ilog2 function returns for an input of 0.
+			 * On 32-bit PowerPC, left shift counts with bit
+			 * 26 set (that the value of 255 or 0xFFFFFFFF
+			 * will have), cause the destination register to
+			 * be 0.  That is why this works.
+			 */
+			temp1 &= temp2;
+		}
+	}
+
+	/*
+	 * Step 2: check each common CAS latency against tCK of each
+	 * DIMM's SPD.
+	 */
+	lowest_good_caslat = 0;
+	temp2 = 0;
+	while (temp1) {
+		not_ok = 0;
+		temp2 =  __ilog2(temp1);
+		debug("checking common caslat = %u\n", temp2);
+
+		/* Check if this CAS latency will work on all DIMMs at tCK. */
+		for (i = 0; i < number_of_dimms; i++) {
+			if (!dimm_params[i].n_ranks) {
+				continue;
+			}
+			if (dimm_params[i].caslat_x == temp2) {
+				if (mclk_ps >= dimm_params[i].tckmin_x_ps) {
+					debug("CL = %u ok on DIMM %u at tCK=%u"
+					    " ps with its tCKmin_X_ps of %u\n",
+					       temp2, i, mclk_ps,
+					       dimm_params[i].tckmin_x_ps);
+					continue;
+				} else {
+					not_ok++;
+				}
+			}
+
+			if (dimm_params[i].caslat_x_minus_1 == temp2) {
+				unsigned int tckmin_x_minus_1_ps
+					= dimm_params[i].tckmin_x_minus_1_ps;
+				if (mclk_ps >= tckmin_x_minus_1_ps) {
+					debug("CL = %u ok on DIMM %u at "
+						"tCK=%u ps with its "
+						"tckmin_x_minus_1_ps of %u\n",
+					       temp2, i, mclk_ps,
+					       tckmin_x_minus_1_ps);
+					continue;
+				} else {
+					not_ok++;
+				}
+			}
+
+			if (dimm_params[i].caslat_x_minus_2 == temp2) {
+				unsigned int tckmin_x_minus_2_ps
+					= dimm_params[i].tckmin_x_minus_2_ps;
+				if (mclk_ps >= tckmin_x_minus_2_ps) {
+					debug("CL = %u ok on DIMM %u at "
+						"tCK=%u ps with its "
+						"tckmin_x_minus_2_ps of %u\n",
+					       temp2, i, mclk_ps,
+					       tckmin_x_minus_2_ps);
+					continue;
+				} else {
+					not_ok++;
+				}
+			}
+		}
+
+		if (!not_ok) {
+			lowest_good_caslat = temp2;
+		}
+
+		temp1 &= ~(1 << temp2);
+	}
+
+	debug("lowest common SPD-defined CAS latency = %u\n",
+	       lowest_good_caslat);
+	outpdimm->lowest_common_SPD_caslat = lowest_good_caslat;
+
+
+	/*
+	 * Compute a common 'de-rated' CAS latency.
+	 *
+	 * The strategy here is to find the *highest* dereated cas latency
+	 * with the assumption that all of the DIMMs will support a dereated
+	 * CAS latency higher than or equal to their lowest dereated value.
+	 */
+	temp1 = 0;
+	for (i = 0; i < number_of_dimms; i++) {
+		temp1 = max(temp1, dimm_params[i].caslat_lowest_derated);
+	}
+	outpdimm->highest_common_derated_caslat = temp1;
+	debug("highest common dereated CAS latency = %u\n", temp1);
+#endif /* #if defined(CONFIG_SYS_FSL_DDR3) */
+
+	/* Determine if all DIMMs ECC capable. */
+	temp1 = 1;
+	for (i = 0; i < number_of_dimms; i++) {
+		if (dimm_params[i].n_ranks &&
+			!(dimm_params[i].edc_config & EDC_ECC)) {
+			temp1 = 0;
+			break;
+		}
+	}
+	if (temp1) {
+		debug("all DIMMs ECC capable\n");
+	} else {
+		debug("Warning: not all DIMMs ECC capable, cant enable ECC\n");
+	}
+	outpdimm->all_dimms_ecc_capable = temp1;
+
+#ifndef CONFIG_SYS_FSL_DDR3
+	/* FIXME: move to somewhere else to validate. */
+	if (mclk_ps > tckmax_max_ps) {
+		printf("Warning: some of the installed DIMMs "
+				"can not operate this slowly.\n");
+		return 1;
+	}
+#endif
+	/*
+	 * Compute additive latency.
+	 *
+	 * For DDR1, additive latency should be 0.
+	 *
+	 * For DDR2, with ODT enabled, use "a value" less than ACTTORW,
+	 *	which comes from Trcd, and also note that:
+	 *	    add_lat + caslat must be >= 4
+	 *
+	 * For DDR3, we use the AL=0
+	 *
+	 * When to use additive latency for DDR2:
+	 *
+	 * I. Because you are using CL=3 and need to do ODT on writes and
+	 *    want functionality.
+	 *    1. Are you going to use ODT? (Does your board not have
+	 *      additional termination circuitry for DQ, DQS, DQS_,
+	 *      DM, RDQS, RDQS_ for x4/x8 configs?)
+	 *    2. If so, is your lowest supported CL going to be 3?
+	 *    3. If so, then you must set AL=1 because
+	 *
+	 *       WL >= 3 for ODT on writes
+	 *       RL = AL + CL
+	 *       WL = RL - 1
+	 *       ->
+	 *       WL = AL + CL - 1
+	 *       AL + CL - 1 >= 3
+	 *       AL + CL >= 4
+	 *  QED
+	 *
+	 *  RL >= 3 for ODT on reads
+	 *  RL = AL + CL
+	 *
+	 *  Since CL aren't usually less than 2, AL=0 is a minimum,
+	 *  so the WL-derived AL should be the  -- FIXME?
+	 *
+	 * II. Because you are using auto-precharge globally and want to
+	 *     use additive latency (posted CAS) to get more bandwidth.
+	 *     1. Are you going to use auto-precharge mode globally?
+	 *
+	 *        Use addtivie latency and compute AL to be 1 cycle less than
+	 *        tRCD, i.e. the READ or WRITE command is in the cycle
+	 *        immediately following the ACTIVATE command..
+	 *
+	 * III. Because you feel like it or want to do some sort of
+	 *      degraded-performance experiment.
+	 *     1.  Do you just want to use additive latency because you feel
+	 *         like it?
+	 *
+	 * Validation:  AL is less than tRCD, and within the other
+	 * read-to-precharge constraints.
+	 */
+
+	additive_latency = 0;
+
+#if defined(CONFIG_SYS_FSL_DDR2)
+	if (lowest_good_caslat < 4) {
+		additive_latency = (picos_to_mclk(trcd_ps) > lowest_good_caslat)
+			? picos_to_mclk(trcd_ps) - lowest_good_caslat : 0;
+		if (mclk_to_picos(additive_latency) > trcd_ps) {
+			additive_latency = picos_to_mclk(trcd_ps);
+			debug("setting additive_latency to %u because it was "
+				" greater than tRCD_ps\n", additive_latency);
+		}
+	}
+
+#elif defined(CONFIG_SYS_FSL_DDR3)
+	/*
+	 * The system will not use the global auto-precharge mode.
+	 * However, it uses the page mode, so we set AL=0
+	 */
+	additive_latency = 0;
+#endif
+
+	/*
+	 * Validate additive latency
+	 * FIXME: move to somewhere else to validate
+	 *
+	 * AL <= tRCD(min)
+	 */
+	if (mclk_to_picos(additive_latency) > trcd_ps) {
+		printf("Error: invalid additive latency exceeds tRCD(min).\n");
+		return 1;
+	}
+
+	/*
+	 * RL = CL + AL;  RL >= 3 for ODT_RD_CFG to be enabled
+	 * WL = RL - 1;  WL >= 3 for ODT_WL_CFG to be enabled
+	 * ADD_LAT (the register) must be set to a value less
+	 * than ACTTORW if WL = 1, then AL must be set to 1
+	 * RD_TO_PRE (the register) must be set to a minimum
+	 * tRTP + AL if AL is nonzero
+	 */
+
+	/*
+	 * Additive latency will be applied only if the memctl option to
+	 * use it.
+	 */
+	outpdimm->additive_latency = additive_latency;
+
+	debug("tCKmin_ps = %u\n", outpdimm->tckmin_x_ps);
+	debug("trcd_ps   = %u\n", outpdimm->trcd_ps);
+	debug("trp_ps    = %u\n", outpdimm->trp_ps);
+	debug("tras_ps   = %u\n", outpdimm->tras_ps);
+	debug("twr_ps    = %u\n", outpdimm->twr_ps);
+	debug("twtr_ps   = %u\n", outpdimm->twtr_ps);
+	debug("trfc_ps   = %u\n", outpdimm->trfc_ps);
+	debug("trrd_ps   = %u\n", outpdimm->trrd_ps);
+	debug("trc_ps    = %u\n", outpdimm->trc_ps);
+
+	return 0;
+}
diff --git a/drivers/ddr/fsl/main.c b/drivers/ddr/fsl/main.c
new file mode 100644
index 0000000000..d62ca63c77
--- /dev/null
+++ b/drivers/ddr/fsl/main.c
@@ -0,0 +1,737 @@
+/*
+ * Copyright 2008-2012 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * Version 2 as published by the Free Software Foundation.
+ */
+
+/*
+ * Generic driver for Freescale DDR/DDR2/DDR3 memory controller.
+ * Based on code from spd_sdram.c
+ * Author: James Yang [at freescale.com]
+ */
+
+#include <common.h>
+#include <i2c.h>
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr.h>
+
+/*
+ * CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY is the physical address from the view
+ * of DDR controllers. It is the same as CONFIG_SYS_DDR_SDRAM_BASE for
+ * all Power SoCs. But it could be different for ARM SoCs. For example,
+ * fsl_lsch3 has a mapping mechanism to map DDR memory to ranges (in order) of
+ * 0x00_8000_0000 ~ 0x00_ffff_ffff
+ * 0x80_8000_0000 ~ 0xff_ffff_ffff
+ */
+#ifndef CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY
+#define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY CONFIG_SYS_DDR_SDRAM_BASE
+#endif
+
+#ifdef CONFIG_PPC
+#include <asm/fsl_law.h>
+
+void fsl_ddr_set_lawbar(
+		const common_timing_params_t *memctl_common_params,
+		unsigned int memctl_interleaved,
+		unsigned int ctrl_num);
+#endif
+
+void fsl_ddr_set_intl3r(const unsigned int granule_size);
+#if defined(SPD_EEPROM_ADDRESS) || \
+    defined(SPD_EEPROM_ADDRESS1) || defined(SPD_EEPROM_ADDRESS2) || \
+    defined(SPD_EEPROM_ADDRESS3) || defined(SPD_EEPROM_ADDRESS4)
+#if (CONFIG_NUM_DDR_CONTROLLERS == 1) && (CONFIG_DIMM_SLOTS_PER_CTLR == 1)
+u8 spd_i2c_addr[CONFIG_NUM_DDR_CONTROLLERS][CONFIG_DIMM_SLOTS_PER_CTLR] = {
+	[0][0] = SPD_EEPROM_ADDRESS,
+};
+#elif (CONFIG_NUM_DDR_CONTROLLERS == 1) && (CONFIG_DIMM_SLOTS_PER_CTLR == 2)
+u8 spd_i2c_addr[CONFIG_NUM_DDR_CONTROLLERS][CONFIG_DIMM_SLOTS_PER_CTLR] = {
+	[0][0] = SPD_EEPROM_ADDRESS1,	/* controller 1 */
+	[0][1] = SPD_EEPROM_ADDRESS2,	/* controller 1 */
+};
+#elif (CONFIG_NUM_DDR_CONTROLLERS == 2) && (CONFIG_DIMM_SLOTS_PER_CTLR == 1)
+u8 spd_i2c_addr[CONFIG_NUM_DDR_CONTROLLERS][CONFIG_DIMM_SLOTS_PER_CTLR] = {
+	[0][0] = SPD_EEPROM_ADDRESS1,	/* controller 1 */
+	[1][0] = SPD_EEPROM_ADDRESS2,	/* controller 2 */
+};
+#elif (CONFIG_NUM_DDR_CONTROLLERS == 2) && (CONFIG_DIMM_SLOTS_PER_CTLR == 2)
+u8 spd_i2c_addr[CONFIG_NUM_DDR_CONTROLLERS][CONFIG_DIMM_SLOTS_PER_CTLR] = {
+	[0][0] = SPD_EEPROM_ADDRESS1,	/* controller 1 */
+	[0][1] = SPD_EEPROM_ADDRESS2,	/* controller 1 */
+	[1][0] = SPD_EEPROM_ADDRESS3,	/* controller 2 */
+	[1][1] = SPD_EEPROM_ADDRESS4,	/* controller 2 */
+};
+#elif (CONFIG_NUM_DDR_CONTROLLERS == 3) && (CONFIG_DIMM_SLOTS_PER_CTLR == 1)
+u8 spd_i2c_addr[CONFIG_NUM_DDR_CONTROLLERS][CONFIG_DIMM_SLOTS_PER_CTLR] = {
+	[0][0] = SPD_EEPROM_ADDRESS1,	/* controller 1 */
+	[1][0] = SPD_EEPROM_ADDRESS2,	/* controller 2 */
+	[2][0] = SPD_EEPROM_ADDRESS3,	/* controller 3 */
+};
+#elif (CONFIG_NUM_DDR_CONTROLLERS == 3) && (CONFIG_DIMM_SLOTS_PER_CTLR == 2)
+u8 spd_i2c_addr[CONFIG_NUM_DDR_CONTROLLERS][CONFIG_DIMM_SLOTS_PER_CTLR] = {
+	[0][0] = SPD_EEPROM_ADDRESS1,	/* controller 1 */
+	[0][1] = SPD_EEPROM_ADDRESS2,	/* controller 1 */
+	[1][0] = SPD_EEPROM_ADDRESS3,	/* controller 2 */
+	[1][1] = SPD_EEPROM_ADDRESS4,	/* controller 2 */
+	[2][0] = SPD_EEPROM_ADDRESS5,	/* controller 3 */
+	[2][1] = SPD_EEPROM_ADDRESS6,	/* controller 3 */
+};
+
+#endif
+
+static void __get_spd(generic_spd_eeprom_t *spd, u8 i2c_address)
+{
+	int ret;
+
+	i2c_set_bus_num(CONFIG_SYS_SPD_BUS_NUM);
+
+	ret = i2c_read(i2c_address, 0, 1, (uchar *)spd,
+				sizeof(generic_spd_eeprom_t));
+
+	if (ret) {
+		if (i2c_address ==
+#ifdef SPD_EEPROM_ADDRESS
+				SPD_EEPROM_ADDRESS
+#elif defined(SPD_EEPROM_ADDRESS1)
+				SPD_EEPROM_ADDRESS1
+#endif
+				) {
+			printf("DDR: failed to read SPD from address %u\n",
+				i2c_address);
+		} else {
+			debug("DDR: failed to read SPD from address %u\n",
+				i2c_address);
+		}
+		memset(spd, 0, sizeof(generic_spd_eeprom_t));
+	}
+}
+
+__attribute__((weak, alias("__get_spd")))
+void get_spd(generic_spd_eeprom_t *spd, u8 i2c_address);
+
+void fsl_ddr_get_spd(generic_spd_eeprom_t *ctrl_dimms_spd,
+		      unsigned int ctrl_num)
+{
+	unsigned int i;
+	unsigned int i2c_address = 0;
+
+	if (ctrl_num >= CONFIG_NUM_DDR_CONTROLLERS) {
+		printf("%s unexpected ctrl_num = %u\n", __FUNCTION__, ctrl_num);
+		return;
+	}
+
+	for (i = 0; i < CONFIG_DIMM_SLOTS_PER_CTLR; i++) {
+		i2c_address = spd_i2c_addr[ctrl_num][i];
+		get_spd(&(ctrl_dimms_spd[i]), i2c_address);
+	}
+}
+#else
+void fsl_ddr_get_spd(generic_spd_eeprom_t *ctrl_dimms_spd,
+		      unsigned int ctrl_num)
+{
+}
+#endif /* SPD_EEPROM_ADDRESSx */
+
+/*
+ * ASSUMPTIONS:
+ *    - Same number of CONFIG_DIMM_SLOTS_PER_CTLR on each controller
+ *    - Same memory data bus width on all controllers
+ *
+ * NOTES:
+ *
+ * The memory controller and associated documentation use confusing
+ * terminology when referring to the orgranization of DRAM.
+ *
+ * Here is a terminology translation table:
+ *
+ * memory controller/documention  |industry   |this code  |signals
+ * -------------------------------|-----------|-----------|-----------------
+ * physical bank/bank		  |rank       |rank	  |chip select (CS)
+ * logical bank/sub-bank	  |bank       |bank	  |bank address (BA)
+ * page/row			  |row	      |page	  |row address
+ * ???				  |column     |column	  |column address
+ *
+ * The naming confusion is further exacerbated by the descriptions of the
+ * memory controller interleaving feature, where accesses are interleaved
+ * _BETWEEN_ two seperate memory controllers.  This is configured only in
+ * CS0_CONFIG[INTLV_CTL] of each memory controller.
+ *
+ * memory controller documentation | number of chip selects
+ *				   | per memory controller supported
+ * --------------------------------|-----------------------------------------
+ * cache line interleaving	   | 1 (CS0 only)
+ * page interleaving		   | 1 (CS0 only)
+ * bank interleaving		   | 1 (CS0 only)
+ * superbank interleraving	   | depends on bank (chip select)
+ *				   |   interleraving [rank interleaving]
+ *				   |   mode used on every memory controller
+ *
+ * Even further confusing is the existence of the interleaving feature
+ * _WITHIN_ each memory controller.  The feature is referred to in
+ * documentation as chip select interleaving or bank interleaving,
+ * although it is configured in the DDR_SDRAM_CFG field.
+ *
+ * Name of field		| documentation name	| this code
+ * -----------------------------|-----------------------|------------------
+ * DDR_SDRAM_CFG[BA_INTLV_CTL]	| Bank (chip select)	| rank interleaving
+ *				|  interleaving
+ */
+
+const char *step_string_tbl[] = {
+	"STEP_GET_SPD",
+	"STEP_COMPUTE_DIMM_PARMS",
+	"STEP_COMPUTE_COMMON_PARMS",
+	"STEP_GATHER_OPTS",
+	"STEP_ASSIGN_ADDRESSES",
+	"STEP_COMPUTE_REGS",
+	"STEP_PROGRAM_REGS",
+	"STEP_ALL"
+};
+
+const char * step_to_string(unsigned int step) {
+
+	unsigned int s = __ilog2(step);
+
+	if ((1 << s) != step)
+		return step_string_tbl[7];
+
+	return step_string_tbl[s];
+}
+
+static unsigned long long __step_assign_addresses(fsl_ddr_info_t *pinfo,
+			  unsigned int dbw_cap_adj[])
+{
+	int i, j;
+	unsigned long long total_mem, current_mem_base, total_ctlr_mem;
+	unsigned long long rank_density, ctlr_density = 0;
+
+	/*
+	 * If a reduced data width is requested, but the SPD
+	 * specifies a physically wider device, adjust the
+	 * computed dimm capacities accordingly before
+	 * assigning addresses.
+	 */
+	for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
+		unsigned int found = 0;
+
+		switch (pinfo->memctl_opts[i].data_bus_width) {
+		case 2:
+			/* 16-bit */
+			for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
+				unsigned int dw;
+				if (!pinfo->dimm_params[i][j].n_ranks)
+					continue;
+				dw = pinfo->dimm_params[i][j].primary_sdram_width;
+				if ((dw == 72 || dw == 64)) {
+					dbw_cap_adj[i] = 2;
+					break;
+				} else if ((dw == 40 || dw == 32)) {
+					dbw_cap_adj[i] = 1;
+					break;
+				}
+			}
+			break;
+
+		case 1:
+			/* 32-bit */
+			for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
+				unsigned int dw;
+				dw = pinfo->dimm_params[i][j].data_width;
+				if (pinfo->dimm_params[i][j].n_ranks
+				    && (dw == 72 || dw == 64)) {
+					/*
+					 * FIXME: can't really do it
+					 * like this because this just
+					 * further reduces the memory
+					 */
+					found = 1;
+					break;
+				}
+			}
+			if (found) {
+				dbw_cap_adj[i] = 1;
+			}
+			break;
+
+		case 0:
+			/* 64-bit */
+			break;
+
+		default:
+			printf("unexpected data bus width "
+				"specified controller %u\n", i);
+			return 1;
+		}
+		debug("dbw_cap_adj[%d]=%d\n", i, dbw_cap_adj[i]);
+	}
+
+	current_mem_base = CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY;
+	total_mem = 0;
+	if (pinfo->memctl_opts[0].memctl_interleaving) {
+		rank_density = pinfo->dimm_params[0][0].rank_density >>
+					dbw_cap_adj[0];
+		switch (pinfo->memctl_opts[0].ba_intlv_ctl &
+					FSL_DDR_CS0_CS1_CS2_CS3) {
+		case FSL_DDR_CS0_CS1_CS2_CS3:
+			ctlr_density = 4 * rank_density;
+			break;
+		case FSL_DDR_CS0_CS1:
+		case FSL_DDR_CS0_CS1_AND_CS2_CS3:
+			ctlr_density = 2 * rank_density;
+			break;
+		case FSL_DDR_CS2_CS3:
+		default:
+			ctlr_density = rank_density;
+			break;
+		}
+		debug("rank density is 0x%llx, ctlr density is 0x%llx\n",
+			rank_density, ctlr_density);
+		for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
+			if (pinfo->memctl_opts[i].memctl_interleaving) {
+				switch (pinfo->memctl_opts[i].memctl_interleaving_mode) {
+				case FSL_DDR_256B_INTERLEAVING:
+				case FSL_DDR_CACHE_LINE_INTERLEAVING:
+				case FSL_DDR_PAGE_INTERLEAVING:
+				case FSL_DDR_BANK_INTERLEAVING:
+				case FSL_DDR_SUPERBANK_INTERLEAVING:
+					total_ctlr_mem = 2 * ctlr_density;
+					break;
+				case FSL_DDR_3WAY_1KB_INTERLEAVING:
+				case FSL_DDR_3WAY_4KB_INTERLEAVING:
+				case FSL_DDR_3WAY_8KB_INTERLEAVING:
+					total_ctlr_mem = 3 * ctlr_density;
+					break;
+				case FSL_DDR_4WAY_1KB_INTERLEAVING:
+				case FSL_DDR_4WAY_4KB_INTERLEAVING:
+				case FSL_DDR_4WAY_8KB_INTERLEAVING:
+					total_ctlr_mem = 4 * ctlr_density;
+					break;
+				default:
+					panic("Unknown interleaving mode");
+				}
+				pinfo->common_timing_params[i].base_address =
+							current_mem_base;
+				pinfo->common_timing_params[i].total_mem =
+							total_ctlr_mem;
+				total_mem = current_mem_base + total_ctlr_mem;
+				debug("ctrl %d base 0x%llx\n", i, current_mem_base);
+				debug("ctrl %d total 0x%llx\n", i, total_ctlr_mem);
+			} else {
+				/* when 3rd controller not interleaved */
+				current_mem_base = total_mem;
+				total_ctlr_mem = 0;
+				pinfo->common_timing_params[i].base_address =
+							current_mem_base;
+				for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
+					unsigned long long cap =
+						pinfo->dimm_params[i][j].capacity >> dbw_cap_adj[i];
+					pinfo->dimm_params[i][j].base_address =
+						current_mem_base;
+					debug("ctrl %d dimm %d base 0x%llx\n", i, j, current_mem_base);
+					current_mem_base += cap;
+					total_ctlr_mem += cap;
+				}
+				debug("ctrl %d total 0x%llx\n", i, total_ctlr_mem);
+				pinfo->common_timing_params[i].total_mem =
+							total_ctlr_mem;
+				total_mem += total_ctlr_mem;
+			}
+		}
+	} else {
+		/*
+		 * Simple linear assignment if memory
+		 * controllers are not interleaved.
+		 */
+		for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
+			total_ctlr_mem = 0;
+			pinfo->common_timing_params[i].base_address =
+						current_mem_base;
+			for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
+				/* Compute DIMM base addresses. */
+				unsigned long long cap =
+					pinfo->dimm_params[i][j].capacity >> dbw_cap_adj[i];
+				pinfo->dimm_params[i][j].base_address =
+					current_mem_base;
+				debug("ctrl %d dimm %d base 0x%llx\n", i, j, current_mem_base);
+				current_mem_base += cap;
+				total_ctlr_mem += cap;
+			}
+			debug("ctrl %d total 0x%llx\n", i, total_ctlr_mem);
+			pinfo->common_timing_params[i].total_mem =
+							total_ctlr_mem;
+			total_mem += total_ctlr_mem;
+		}
+	}
+	debug("Total mem by %s is 0x%llx\n", __func__, total_mem);
+
+	return total_mem;
+}
+
+/* Use weak function to allow board file to override the address assignment */
+__attribute__((weak, alias("__step_assign_addresses")))
+unsigned long long step_assign_addresses(fsl_ddr_info_t *pinfo,
+			  unsigned int dbw_cap_adj[]);
+
+unsigned long long
+fsl_ddr_compute(fsl_ddr_info_t *pinfo, unsigned int start_step,
+				       unsigned int size_only)
+{
+	unsigned int i, j;
+	unsigned long long total_mem = 0;
+	int assert_reset;
+
+	fsl_ddr_cfg_regs_t *ddr_reg = pinfo->fsl_ddr_config_reg;
+	common_timing_params_t *timing_params = pinfo->common_timing_params;
+	assert_reset = board_need_mem_reset();
+
+	/* data bus width capacity adjust shift amount */
+	unsigned int dbw_capacity_adjust[CONFIG_NUM_DDR_CONTROLLERS];
+
+	for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
+		dbw_capacity_adjust[i] = 0;
+	}
+
+	debug("starting at step %u (%s)\n",
+	      start_step, step_to_string(start_step));
+
+	switch (start_step) {
+	case STEP_GET_SPD:
+#if defined(CONFIG_DDR_SPD) || defined(CONFIG_SPD_EEPROM)
+		/* STEP 1:  Gather all DIMM SPD data */
+		for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
+			fsl_ddr_get_spd(pinfo->spd_installed_dimms[i], i);
+		}
+
+	case STEP_COMPUTE_DIMM_PARMS:
+		/* STEP 2:  Compute DIMM parameters from SPD data */
+
+		for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
+			for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
+				unsigned int retval;
+				generic_spd_eeprom_t *spd =
+					&(pinfo->spd_installed_dimms[i][j]);
+				dimm_params_t *pdimm =
+					&(pinfo->dimm_params[i][j]);
+
+				retval = compute_dimm_parameters(spd, pdimm, i);
+#ifdef CONFIG_SYS_DDR_RAW_TIMING
+				if (!i && !j && retval) {
+					printf("SPD error on controller %d! "
+					"Trying fallback to raw timing "
+					"calculation\n", i);
+					fsl_ddr_get_dimm_params(pdimm, i, j);
+				}
+#else
+				if (retval == 2) {
+					printf("Error: compute_dimm_parameters"
+					" non-zero returned FATAL value "
+					"for memctl=%u dimm=%u\n", i, j);
+					return 0;
+				}
+#endif
+				if (retval) {
+					debug("Warning: compute_dimm_parameters"
+					" non-zero return value for memctl=%u "
+					"dimm=%u\n", i, j);
+				}
+			}
+		}
+
+#elif defined(CONFIG_SYS_DDR_RAW_TIMING)
+	case STEP_COMPUTE_DIMM_PARMS:
+		for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
+			for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
+				dimm_params_t *pdimm =
+					&(pinfo->dimm_params[i][j]);
+				fsl_ddr_get_dimm_params(pdimm, i, j);
+			}
+		}
+		debug("Filling dimm parameters from board specific file\n");
+#endif
+	case STEP_COMPUTE_COMMON_PARMS:
+		/*
+		 * STEP 3: Compute a common set of timing parameters
+		 * suitable for all of the DIMMs on each memory controller
+		 */
+		for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
+			debug("Computing lowest common DIMM"
+				" parameters for memctl=%u\n", i);
+			compute_lowest_common_dimm_parameters(
+				pinfo->dimm_params[i],
+				&timing_params[i],
+				CONFIG_DIMM_SLOTS_PER_CTLR);
+		}
+
+	case STEP_GATHER_OPTS:
+		/* STEP 4:  Gather configuration requirements from user */
+		for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
+			debug("Reloading memory controller "
+				"configuration options for memctl=%u\n", i);
+			/*
+			 * This "reloads" the memory controller options
+			 * to defaults.  If the user "edits" an option,
+			 * next_step points to the step after this,
+			 * which is currently STEP_ASSIGN_ADDRESSES.
+			 */
+			populate_memctl_options(
+					timing_params[i].all_dimms_registered,
+					&pinfo->memctl_opts[i],
+					pinfo->dimm_params[i], i);
+			/*
+			 * For RDIMMs, JEDEC spec requires clocks to be stable
+			 * before reset signal is deasserted. For the boards
+			 * using fixed parameters, this function should be
+			 * be called from board init file.
+			 */
+			if (timing_params[i].all_dimms_registered)
+				assert_reset = 1;
+		}
+		if (assert_reset) {
+			debug("Asserting mem reset\n");
+			board_assert_mem_reset();
+		}
+
+	case STEP_ASSIGN_ADDRESSES:
+		/* STEP 5:  Assign addresses to chip selects */
+		check_interleaving_options(pinfo);
+		total_mem = step_assign_addresses(pinfo, dbw_capacity_adjust);
+
+	case STEP_COMPUTE_REGS:
+		/* STEP 6:  compute controller register values */
+		debug("FSL Memory ctrl register computation\n");
+		for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
+			if (timing_params[i].ndimms_present == 0) {
+				memset(&ddr_reg[i], 0,
+					sizeof(fsl_ddr_cfg_regs_t));
+				continue;
+			}
+
+			compute_fsl_memctl_config_regs(
+					&pinfo->memctl_opts[i],
+					&ddr_reg[i], &timing_params[i],
+					pinfo->dimm_params[i],
+					dbw_capacity_adjust[i],
+					size_only);
+		}
+
+	default:
+		break;
+	}
+
+	{
+		/*
+		 * Compute the amount of memory available just by
+		 * looking for the highest valid CSn_BNDS value.
+		 * This allows us to also experiment with using
+		 * only CS0 when using dual-rank DIMMs.
+		 */
+		unsigned int max_end = 0;
+
+		for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
+			for (j = 0; j < CONFIG_CHIP_SELECTS_PER_CTRL; j++) {
+				fsl_ddr_cfg_regs_t *reg = &ddr_reg[i];
+				if (reg->cs[j].config & 0x80000000) {
+					unsigned int end;
+					/*
+					 * 0xfffffff is a special value we put
+					 * for unused bnds
+					 */
+					if (reg->cs[j].bnds == 0xffffffff)
+						continue;
+					end = reg->cs[j].bnds & 0xffff;
+					if (end > max_end) {
+						max_end = end;
+					}
+				}
+			}
+		}
+
+		total_mem = 1 + (((unsigned long long)max_end << 24ULL) |
+			    0xFFFFFFULL) - CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY;
+	}
+
+	return total_mem;
+}
+
+/*
+ * fsl_ddr_sdram() -- this is the main function to be called by
+ *	initdram() in the board file.
+ *
+ * It returns amount of memory configured in bytes.
+ */
+phys_size_t fsl_ddr_sdram(void)
+{
+	unsigned int i;
+#ifdef CONFIG_PPC
+	unsigned int law_memctl = LAW_TRGT_IF_DDR_1;
+#endif
+	unsigned long long total_memory;
+	fsl_ddr_info_t info;
+	int deassert_reset;
+
+	/* Reset info structure. */
+	memset(&info, 0, sizeof(fsl_ddr_info_t));
+
+	/* Compute it once normally. */
+#ifdef CONFIG_FSL_DDR_INTERACTIVE
+	if (tstc() && (getc() == 'd')) {	/* we got a key press of 'd' */
+		total_memory = fsl_ddr_interactive(&info, 0);
+	} else if (fsl_ddr_interactive_env_var_exists()) {
+		total_memory = fsl_ddr_interactive(&info, 1);
+	} else
+#endif
+		total_memory = fsl_ddr_compute(&info, STEP_GET_SPD, 0);
+
+	/* setup 3-way interleaving before enabling DDRC */
+	if (info.memctl_opts[0].memctl_interleaving) {
+		switch (info.memctl_opts[0].memctl_interleaving_mode) {
+		case FSL_DDR_3WAY_1KB_INTERLEAVING:
+		case FSL_DDR_3WAY_4KB_INTERLEAVING:
+		case FSL_DDR_3WAY_8KB_INTERLEAVING:
+			fsl_ddr_set_intl3r(
+				info.memctl_opts[0].memctl_interleaving_mode);
+			break;
+		default:
+			break;
+		}
+	}
+
+	/*
+	 * Program configuration registers.
+	 * JEDEC specs requires clocks to be stable before deasserting reset
+	 * for RDIMMs. Clocks start after chip select is enabled and clock
+	 * control register is set. During step 1, all controllers have their
+	 * registers set but not enabled. Step 2 proceeds after deasserting
+	 * reset through board FPGA or GPIO.
+	 * For non-registered DIMMs, initialization can go through but it is
+	 * also OK to follow the same flow.
+	 */
+	deassert_reset = board_need_mem_reset();
+	for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
+		if (info.common_timing_params[i].all_dimms_registered)
+			deassert_reset = 1;
+	}
+	for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
+		debug("Programming controller %u\n", i);
+		if (info.common_timing_params[i].ndimms_present == 0) {
+			debug("No dimms present on controller %u; "
+					"skipping programming\n", i);
+			continue;
+		}
+		/*
+		 * The following call with step = 1 returns before enabling
+		 * the controller. It has to finish with step = 2 later.
+		 */
+		fsl_ddr_set_memctl_regs(&(info.fsl_ddr_config_reg[i]), i,
+					deassert_reset ? 1 : 0);
+	}
+	if (deassert_reset) {
+		/* Use board FPGA or GPIO to deassert reset signal */
+		debug("Deasserting mem reset\n");
+		board_deassert_mem_reset();
+		for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
+			/* Call with step = 2 to continue initialization */
+			fsl_ddr_set_memctl_regs(&(info.fsl_ddr_config_reg[i]),
+						i, 2);
+		}
+	}
+
+#ifdef CONFIG_PPC
+	/* program LAWs */
+	for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
+		if (info.memctl_opts[i].memctl_interleaving) {
+			switch (info.memctl_opts[i].memctl_interleaving_mode) {
+			case FSL_DDR_CACHE_LINE_INTERLEAVING:
+			case FSL_DDR_PAGE_INTERLEAVING:
+			case FSL_DDR_BANK_INTERLEAVING:
+			case FSL_DDR_SUPERBANK_INTERLEAVING:
+				if (i == 0) {
+					law_memctl = LAW_TRGT_IF_DDR_INTRLV;
+					fsl_ddr_set_lawbar(&info.common_timing_params[i],
+						law_memctl, i);
+				} else if (i == 2) {
+					law_memctl = LAW_TRGT_IF_DDR_INTLV_34;
+					fsl_ddr_set_lawbar(&info.common_timing_params[i],
+						law_memctl, i);
+				}
+				break;
+			case FSL_DDR_3WAY_1KB_INTERLEAVING:
+			case FSL_DDR_3WAY_4KB_INTERLEAVING:
+			case FSL_DDR_3WAY_8KB_INTERLEAVING:
+				law_memctl = LAW_TRGT_IF_DDR_INTLV_123;
+				if (i == 0) {
+					fsl_ddr_set_lawbar(&info.common_timing_params[i],
+						law_memctl, i);
+				}
+				break;
+			case FSL_DDR_4WAY_1KB_INTERLEAVING:
+			case FSL_DDR_4WAY_4KB_INTERLEAVING:
+			case FSL_DDR_4WAY_8KB_INTERLEAVING:
+				law_memctl = LAW_TRGT_IF_DDR_INTLV_1234;
+				if (i == 0)
+					fsl_ddr_set_lawbar(&info.common_timing_params[i],
+						law_memctl, i);
+				/* place holder for future 4-way interleaving */
+				break;
+			default:
+				break;
+			}
+		} else {
+			switch (i) {
+			case 0:
+				law_memctl = LAW_TRGT_IF_DDR_1;
+				break;
+			case 1:
+				law_memctl = LAW_TRGT_IF_DDR_2;
+				break;
+			case 2:
+				law_memctl = LAW_TRGT_IF_DDR_3;
+				break;
+			case 3:
+				law_memctl = LAW_TRGT_IF_DDR_4;
+				break;
+			default:
+				break;
+			}
+			fsl_ddr_set_lawbar(&info.common_timing_params[i],
+					law_memctl, i);
+		}
+	}
+#endif
+
+	debug("total_memory by %s = %llu\n", __func__, total_memory);
+
+#if !defined(CONFIG_PHYS_64BIT)
+	/* Check for 4G or more.  Bad. */
+	if (total_memory >= (1ull << 32)) {
+		puts("Detected ");
+		print_size(total_memory, " of memory\n");
+		printf("       This U-Boot only supports < 4G of DDR\n");
+		printf("       You could rebuild it with CONFIG_PHYS_64BIT\n");
+		printf("       "); /* re-align to match init_func_ram print */
+		total_memory = CONFIG_MAX_MEM_MAPPED;
+	}
+#endif
+
+	return total_memory;
+}
+
+/*
+ * fsl_ddr_sdram_size() - This function only returns the size of the total
+ * memory without setting ddr control registers.
+ */
+phys_size_t
+fsl_ddr_sdram_size(void)
+{
+	fsl_ddr_info_t  info;
+	unsigned long long total_memory = 0;
+
+	memset(&info, 0 , sizeof(fsl_ddr_info_t));
+
+	/* Compute it once normally. */
+	total_memory = fsl_ddr_compute(&info, STEP_GET_SPD, 1);
+
+	return total_memory;
+}
diff --git a/drivers/ddr/fsl/mpc85xx_ddr_gen1.c b/drivers/ddr/fsl/mpc85xx_ddr_gen1.c
new file mode 100644
index 0000000000..8dd4a9136c
--- /dev/null
+++ b/drivers/ddr/fsl/mpc85xx_ddr_gen1.c
@@ -0,0 +1,91 @@
+/*
+ * Copyright 2008 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * Version 2 as published by the Free Software Foundation.
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <fsl_ddr_sdram.h>
+
+#if (CONFIG_CHIP_SELECTS_PER_CTRL > 4)
+#error Invalid setting for CONFIG_CHIP_SELECTS_PER_CTRL
+#endif
+
+void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
+			     unsigned int ctrl_num, int step)
+{
+	unsigned int i;
+	struct ccsr_ddr __iomem *ddr =
+		(struct ccsr_ddr __iomem *)CONFIG_SYS_FSL_DDR_ADDR;
+
+	if (ctrl_num != 0) {
+		printf("%s unexpected ctrl_num = %u\n", __FUNCTION__, ctrl_num);
+		return;
+	}
+
+	for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
+		if (i == 0) {
+			out_be32(&ddr->cs0_bnds, regs->cs[i].bnds);
+			out_be32(&ddr->cs0_config, regs->cs[i].config);
+
+		} else if (i == 1) {
+			out_be32(&ddr->cs1_bnds, regs->cs[i].bnds);
+			out_be32(&ddr->cs1_config, regs->cs[i].config);
+
+		} else if (i == 2) {
+			out_be32(&ddr->cs2_bnds, regs->cs[i].bnds);
+			out_be32(&ddr->cs2_config, regs->cs[i].config);
+
+		} else if (i == 3) {
+			out_be32(&ddr->cs3_bnds, regs->cs[i].bnds);
+			out_be32(&ddr->cs3_config, regs->cs[i].config);
+		}
+	}
+
+	out_be32(&ddr->timing_cfg_1, regs->timing_cfg_1);
+	out_be32(&ddr->timing_cfg_2, regs->timing_cfg_2);
+	out_be32(&ddr->sdram_mode, regs->ddr_sdram_mode);
+	out_be32(&ddr->sdram_interval, regs->ddr_sdram_interval);
+#if defined(CONFIG_MPC8555) || defined(CONFIG_MPC8541)
+	out_be32(&ddr->sdram_clk_cntl, regs->ddr_sdram_clk_cntl);
+#endif
+
+	/*
+	 * 200 painful micro-seconds must elapse between
+	 * the DDR clock setup and the DDR config enable.
+	 */
+	udelay(200);
+	asm volatile("sync;isync");
+
+	out_be32(&ddr->sdram_cfg, regs->ddr_sdram_cfg);
+
+	asm("sync;isync;msync");
+	udelay(500);
+}
+
+#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
+/*
+ * Initialize all of memory for ECC, then enable errors.
+ */
+
+void
+ddr_enable_ecc(unsigned int dram_size)
+{
+	struct ccsr_ddr __iomem *ddr =
+		(struct ccsr_ddr __iomem *)(CONFIG_SYS_FSL_DDR_ADDR);
+
+	dma_meminit(CONFIG_MEM_INIT_VALUE, dram_size);
+
+	/*
+	 * Enable errors for ECC.
+	 */
+	debug("DMA DDR: err_disable = 0x%08x\n", ddr->err_disable);
+	ddr->err_disable = 0x00000000;
+	asm("sync;isync;msync");
+	debug("DMA DDR: err_disable = 0x%08x\n", ddr->err_disable);
+}
+
+#endif	/* CONFIG_DDR_ECC  && ! CONFIG_ECC_INIT_VIA_DDRCONTROLLER */
diff --git a/drivers/ddr/fsl/mpc85xx_ddr_gen2.c b/drivers/ddr/fsl/mpc85xx_ddr_gen2.c
new file mode 100644
index 0000000000..988b4a4941
--- /dev/null
+++ b/drivers/ddr/fsl/mpc85xx_ddr_gen2.c
@@ -0,0 +1,96 @@
+/*
+ * Copyright 2008-2011 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * Version 2 as published by the Free Software Foundation.
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/processor.h>
+#include <fsl_ddr_sdram.h>
+
+#if (CONFIG_CHIP_SELECTS_PER_CTRL > 4)
+#error Invalid setting for CONFIG_CHIP_SELECTS_PER_CTRL
+#endif
+
+void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
+			     unsigned int ctrl_num, int step)
+{
+	unsigned int i;
+	struct ccsr_ddr __iomem *ddr =
+		(struct ccsr_ddr __iomem *)CONFIG_SYS_FSL_DDR_ADDR;
+
+#if defined(CONFIG_SYS_FSL_ERRATUM_NMG_DDR120) && defined(CONFIG_MPC85xx)
+	ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+	uint svr;
+#endif
+
+	if (ctrl_num) {
+		printf("%s unexpected ctrl_num = %u\n", __FUNCTION__, ctrl_num);
+		return;
+	}
+
+#ifdef CONFIG_SYS_FSL_ERRATUM_NMG_DDR120
+	/*
+	 * Set the DDR IO receiver to an acceptable bias point.
+	 * Fixed in Rev 2.1.
+	 */
+	svr = get_svr();
+	if ((SVR_MAJ(svr) == 1) || IS_SVR_REV(svr, 2, 0)) {
+		if ((regs->ddr_sdram_cfg & SDRAM_CFG_SDRAM_TYPE_MASK) ==
+		   SDRAM_CFG_SDRAM_TYPE_DDR2)
+			out_be32(&gur->ddrioovcr, 0x90000000);
+		else
+			out_be32(&gur->ddrioovcr, 0xA8000000);
+	}
+#endif
+
+	for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
+		if (i == 0) {
+			out_be32(&ddr->cs0_bnds, regs->cs[i].bnds);
+			out_be32(&ddr->cs0_config, regs->cs[i].config);
+
+		} else if (i == 1) {
+			out_be32(&ddr->cs1_bnds, regs->cs[i].bnds);
+			out_be32(&ddr->cs1_config, regs->cs[i].config);
+
+		} else if (i == 2) {
+			out_be32(&ddr->cs2_bnds, regs->cs[i].bnds);
+			out_be32(&ddr->cs2_config, regs->cs[i].config);
+
+		} else if (i == 3) {
+			out_be32(&ddr->cs3_bnds, regs->cs[i].bnds);
+			out_be32(&ddr->cs3_config, regs->cs[i].config);
+		}
+	}
+
+	out_be32(&ddr->timing_cfg_3, regs->timing_cfg_3);
+	out_be32(&ddr->timing_cfg_0, regs->timing_cfg_0);
+	out_be32(&ddr->timing_cfg_1, regs->timing_cfg_1);
+	out_be32(&ddr->timing_cfg_2, regs->timing_cfg_2);
+	out_be32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2);
+	out_be32(&ddr->sdram_mode, regs->ddr_sdram_mode);
+	out_be32(&ddr->sdram_mode_2, regs->ddr_sdram_mode_2);
+	out_be32(&ddr->sdram_md_cntl, regs->ddr_sdram_md_cntl);
+	out_be32(&ddr->sdram_interval, regs->ddr_sdram_interval);
+	out_be32(&ddr->sdram_data_init, regs->ddr_data_init);
+	out_be32(&ddr->sdram_clk_cntl, regs->ddr_sdram_clk_cntl);
+	out_be32(&ddr->init_addr, regs->ddr_init_addr);
+	out_be32(&ddr->init_ext_addr, regs->ddr_init_ext_addr);
+
+	/*
+	 * 200 painful micro-seconds must elapse between
+	 * the DDR clock setup and the DDR config enable.
+	 */
+	udelay(200);
+	asm volatile("sync;isync");
+
+	out_be32(&ddr->sdram_cfg, regs->ddr_sdram_cfg);
+
+	/* Poll DDR_SDRAM_CFG_2[D_INIT] bit until auto-data init is done.  */
+	while (in_be32(&ddr->sdram_cfg_2) & 0x10) {
+		udelay(10000);		/* throttle polling rate */
+	}
+}
diff --git a/drivers/ddr/fsl/mpc85xx_ddr_gen3.c b/drivers/ddr/fsl/mpc85xx_ddr_gen3.c
new file mode 100644
index 0000000000..c805086416
--- /dev/null
+++ b/drivers/ddr/fsl/mpc85xx_ddr_gen3.c
@@ -0,0 +1,529 @@
+/*
+ * Copyright 2008-2012 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * Version 2 as published by the Free Software Foundation.
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <fsl_ddr_sdram.h>
+#include <asm/processor.h>
+
+#if (CONFIG_CHIP_SELECTS_PER_CTRL > 4)
+#error Invalid setting for CONFIG_CHIP_SELECTS_PER_CTRL
+#endif
+
+
+/*
+ * regs has the to-be-set values for DDR controller registers
+ * ctrl_num is the DDR controller number
+ * step: 0 goes through the initialization in one pass
+ *       1 sets registers and returns before enabling controller
+ *       2 resumes from step 1 and continues to initialize
+ * Dividing the initialization to two steps to deassert DDR reset signal
+ * to comply with JEDEC specs for RDIMMs.
+ */
+void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
+			     unsigned int ctrl_num, int step)
+{
+	unsigned int i, bus_width;
+	struct ccsr_ddr __iomem *ddr;
+	u32 temp_sdram_cfg;
+	u32 total_gb_size_per_controller;
+	int timeout;
+#ifdef CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134
+	int timeout_save;
+	volatile ccsr_local_ecm_t *ecm = (void *)CONFIG_SYS_MPC85xx_ECM_ADDR;
+	unsigned int csn_bnds_backup = 0, cs_sa, cs_ea, *csn_bnds_t;
+	int csn = -1;
+#endif
+#ifdef CONFIG_SYS_FSL_ERRATUM_DDR_A003
+	u32 save1, save2;
+#endif
+
+	switch (ctrl_num) {
+	case 0:
+		ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
+		break;
+#if defined(CONFIG_SYS_FSL_DDR2_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 1)
+	case 1:
+		ddr = (void *)CONFIG_SYS_FSL_DDR2_ADDR;
+		break;
+#endif
+#if defined(CONFIG_SYS_FSL_DDR3_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 2)
+	case 2:
+		ddr = (void *)CONFIG_SYS_FSL_DDR3_ADDR;
+		break;
+#endif
+#if defined(CONFIG_SYS_FSL_DDR4_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 3)
+	case 3:
+		ddr = (void *)CONFIG_SYS_FSL_DDR4_ADDR;
+		break;
+#endif
+	default:
+		printf("%s unexpected ctrl_num = %u\n", __FUNCTION__, ctrl_num);
+		return;
+	}
+
+	if (step == 2)
+		goto step2;
+
+	if (regs->ddr_eor)
+		out_be32(&ddr->eor, regs->ddr_eor);
+#ifdef CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134
+	debug("Workaround for ERRATUM_DDR111_DDR134\n");
+	for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
+		cs_sa = (regs->cs[i].bnds >> 16) & 0xfff;
+		cs_ea = regs->cs[i].bnds & 0xfff;
+		if ((cs_sa <= 0xff) && (cs_ea >= 0xff)) {
+			csn = i;
+			csn_bnds_backup = regs->cs[i].bnds;
+			csn_bnds_t = (unsigned int *) &regs->cs[i].bnds;
+			if (cs_ea > 0xeff)
+				*csn_bnds_t = regs->cs[i].bnds + 0x01000000;
+			else
+				*csn_bnds_t = regs->cs[i].bnds + 0x01000100;
+			debug("Found cs%d_bns (0x%08x) covering 0xff000000, "
+				"change it to 0x%x\n",
+				csn, csn_bnds_backup, regs->cs[i].bnds);
+			break;
+		}
+	}
+#endif
+	for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
+		if (i == 0) {
+			out_be32(&ddr->cs0_bnds, regs->cs[i].bnds);
+			out_be32(&ddr->cs0_config, regs->cs[i].config);
+			out_be32(&ddr->cs0_config_2, regs->cs[i].config_2);
+
+		} else if (i == 1) {
+			out_be32(&ddr->cs1_bnds, regs->cs[i].bnds);
+			out_be32(&ddr->cs1_config, regs->cs[i].config);
+			out_be32(&ddr->cs1_config_2, regs->cs[i].config_2);
+
+		} else if (i == 2) {
+			out_be32(&ddr->cs2_bnds, regs->cs[i].bnds);
+			out_be32(&ddr->cs2_config, regs->cs[i].config);
+			out_be32(&ddr->cs2_config_2, regs->cs[i].config_2);
+
+		} else if (i == 3) {
+			out_be32(&ddr->cs3_bnds, regs->cs[i].bnds);
+			out_be32(&ddr->cs3_config, regs->cs[i].config);
+			out_be32(&ddr->cs3_config_2, regs->cs[i].config_2);
+		}
+	}
+
+	out_be32(&ddr->timing_cfg_3, regs->timing_cfg_3);
+	out_be32(&ddr->timing_cfg_0, regs->timing_cfg_0);
+	out_be32(&ddr->timing_cfg_1, regs->timing_cfg_1);
+	out_be32(&ddr->timing_cfg_2, regs->timing_cfg_2);
+	out_be32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2);
+	out_be32(&ddr->sdram_mode, regs->ddr_sdram_mode);
+	out_be32(&ddr->sdram_mode_2, regs->ddr_sdram_mode_2);
+	out_be32(&ddr->sdram_mode_3, regs->ddr_sdram_mode_3);
+	out_be32(&ddr->sdram_mode_4, regs->ddr_sdram_mode_4);
+	out_be32(&ddr->sdram_mode_5, regs->ddr_sdram_mode_5);
+	out_be32(&ddr->sdram_mode_6, regs->ddr_sdram_mode_6);
+	out_be32(&ddr->sdram_mode_7, regs->ddr_sdram_mode_7);
+	out_be32(&ddr->sdram_mode_8, regs->ddr_sdram_mode_8);
+	out_be32(&ddr->sdram_md_cntl, regs->ddr_sdram_md_cntl);
+	out_be32(&ddr->sdram_interval, regs->ddr_sdram_interval);
+	out_be32(&ddr->sdram_data_init, regs->ddr_data_init);
+	out_be32(&ddr->sdram_clk_cntl, regs->ddr_sdram_clk_cntl);
+	out_be32(&ddr->init_addr, regs->ddr_init_addr);
+	out_be32(&ddr->init_ext_addr, regs->ddr_init_ext_addr);
+
+	out_be32(&ddr->timing_cfg_4, regs->timing_cfg_4);
+	out_be32(&ddr->timing_cfg_5, regs->timing_cfg_5);
+	out_be32(&ddr->ddr_zq_cntl, regs->ddr_zq_cntl);
+	out_be32(&ddr->ddr_wrlvl_cntl, regs->ddr_wrlvl_cntl);
+#ifndef CONFIG_SYS_FSL_DDR_EMU
+	/*
+	 * Skip these two registers if running on emulator
+	 * because emulator doesn't have skew between bytes.
+	 */
+
+	if (regs->ddr_wrlvl_cntl_2)
+		out_be32(&ddr->ddr_wrlvl_cntl_2, regs->ddr_wrlvl_cntl_2);
+	if (regs->ddr_wrlvl_cntl_3)
+		out_be32(&ddr->ddr_wrlvl_cntl_3, regs->ddr_wrlvl_cntl_3);
+#endif
+
+	out_be32(&ddr->ddr_sr_cntr, regs->ddr_sr_cntr);
+	out_be32(&ddr->ddr_sdram_rcw_1, regs->ddr_sdram_rcw_1);
+	out_be32(&ddr->ddr_sdram_rcw_2, regs->ddr_sdram_rcw_2);
+	out_be32(&ddr->ddr_cdr1, regs->ddr_cdr1);
+	out_be32(&ddr->ddr_cdr2, regs->ddr_cdr2);
+	out_be32(&ddr->err_disable, regs->err_disable);
+	out_be32(&ddr->err_int_en, regs->err_int_en);
+	for (i = 0; i < 32; i++) {
+		if (regs->debug[i]) {
+			debug("Write to debug_%d as %08x\n", i+1, regs->debug[i]);
+			out_be32(&ddr->debug[i], regs->debug[i]);
+		}
+	}
+#ifdef CONFIG_SYS_FSL_ERRATUM_A_004934
+	out_be32(&ddr->debug[28], 0x30003000);
+#endif
+
+#ifdef CONFIG_SYS_FSL_ERRATUM_DDR_A003474
+	out_be32(&ddr->debug[12], 0x00000015);
+	out_be32(&ddr->debug[21], 0x24000000);
+#endif /* CONFIG_SYS_FSL_ERRATUM_DDR_A003474 */
+
+	/*
+	 * For RDIMMs, JEDEC spec requires clocks to be stable before reset is
+	 * deasserted. Clocks start when any chip select is enabled and clock
+	 * control register is set. Because all DDR components are connected to
+	 * one reset signal, this needs to be done in two steps. Step 1 is to
+	 * get the clocks started. Step 2 resumes after reset signal is
+	 * deasserted.
+	 */
+	if (step == 1) {
+		udelay(200);
+		return;
+	}
+
+step2:
+	/* Set, but do not enable the memory */
+	temp_sdram_cfg = regs->ddr_sdram_cfg;
+	temp_sdram_cfg &= ~(SDRAM_CFG_MEM_EN);
+	out_be32(&ddr->sdram_cfg, temp_sdram_cfg);
+#ifdef CONFIG_SYS_FSL_ERRATUM_DDR_A003
+	debug("Workaround for ERRATUM_DDR_A003\n");
+	if (regs->ddr_sdram_rcw_2 & 0x00f00000) {
+		out_be32(&ddr->timing_cfg_2, regs->timing_cfg_2 & 0xf07fffff);
+		out_be32(&ddr->debug[2], 0x00000400);
+		out_be32(&ddr->ddr_zq_cntl, regs->ddr_zq_cntl & 0x7fffffff);
+		out_be32(&ddr->ddr_wrlvl_cntl, regs->ddr_wrlvl_cntl & 0x7fffffff);
+		out_be32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2 & 0xffffffeb);
+		out_be32(&ddr->mtcr, 0);
+		save1 = in_be32(&ddr->debug[12]);
+		save2 = in_be32(&ddr->debug[21]);
+		out_be32(&ddr->debug[12], 0x00000015);
+		out_be32(&ddr->debug[21], 0x24000000);
+		out_be32(&ddr->sdram_interval, regs->ddr_sdram_interval & 0xffff);
+		out_be32(&ddr->sdram_cfg, temp_sdram_cfg | SDRAM_CFG_BI | SDRAM_CFG_MEM_EN);
+
+		asm volatile("sync;isync");
+		while (!(in_be32(&ddr->debug[1]) & 0x2))
+			;
+
+		switch (regs->ddr_sdram_rcw_2 & 0x00f00000) {
+		case 0x00000000:
+			out_be32(&ddr->sdram_md_cntl,
+				MD_CNTL_MD_EN		|
+				MD_CNTL_CS_SEL_CS0_CS1	|
+				0x04000000		|
+				MD_CNTL_WRCW		|
+				MD_CNTL_MD_VALUE(0x02));
+#if (CONFIG_DIMM_SLOTS_PER_CTLR == 2)
+			if (!(regs->cs[2].config & SDRAM_CS_CONFIG_EN))
+				break;
+			while (in_be32(&ddr->sdram_md_cntl) & MD_CNTL_MD_EN)
+				;
+			out_be32(&ddr->sdram_md_cntl,
+				 MD_CNTL_MD_EN		|
+				 MD_CNTL_CS_SEL_CS2_CS3	|
+				 0x04000000		|
+				 MD_CNTL_WRCW		|
+				 MD_CNTL_MD_VALUE(0x02));
+#endif
+			break;
+		case 0x00100000:
+			out_be32(&ddr->sdram_md_cntl,
+				MD_CNTL_MD_EN		|
+				MD_CNTL_CS_SEL_CS0_CS1	|
+				0x04000000		|
+				MD_CNTL_WRCW		|
+				MD_CNTL_MD_VALUE(0x0a));
+#if (CONFIG_DIMM_SLOTS_PER_CTLR == 2)
+			if (!(regs->cs[2].config & SDRAM_CS_CONFIG_EN))
+				break;
+			while (in_be32(&ddr->sdram_md_cntl) & MD_CNTL_MD_EN)
+				;
+			out_be32(&ddr->sdram_md_cntl,
+				 MD_CNTL_MD_EN		|
+				 MD_CNTL_CS_SEL_CS2_CS3	|
+				 0x04000000		|
+				 MD_CNTL_WRCW		|
+				 MD_CNTL_MD_VALUE(0x0a));
+#endif
+			break;
+		case 0x00200000:
+			out_be32(&ddr->sdram_md_cntl,
+				MD_CNTL_MD_EN		|
+				MD_CNTL_CS_SEL_CS0_CS1	|
+				0x04000000		|
+				MD_CNTL_WRCW		|
+				MD_CNTL_MD_VALUE(0x12));
+#if (CONFIG_DIMM_SLOTS_PER_CTLR == 2)
+			if (!(regs->cs[2].config & SDRAM_CS_CONFIG_EN))
+				break;
+			while (in_be32(&ddr->sdram_md_cntl) & MD_CNTL_MD_EN)
+				;
+			out_be32(&ddr->sdram_md_cntl,
+				 MD_CNTL_MD_EN		|
+				 MD_CNTL_CS_SEL_CS2_CS3	|
+				 0x04000000		|
+				 MD_CNTL_WRCW		|
+				 MD_CNTL_MD_VALUE(0x12));
+#endif
+			break;
+		case 0x00300000:
+			out_be32(&ddr->sdram_md_cntl,
+				MD_CNTL_MD_EN		|
+				MD_CNTL_CS_SEL_CS0_CS1	|
+				0x04000000		|
+				MD_CNTL_WRCW		|
+				MD_CNTL_MD_VALUE(0x1a));
+#if (CONFIG_DIMM_SLOTS_PER_CTLR == 2)
+			if (!(regs->cs[2].config & SDRAM_CS_CONFIG_EN))
+				break;
+			while (in_be32(&ddr->sdram_md_cntl) & MD_CNTL_MD_EN)
+				;
+			out_be32(&ddr->sdram_md_cntl,
+				 MD_CNTL_MD_EN		|
+				 MD_CNTL_CS_SEL_CS2_CS3	|
+				 0x04000000		|
+				 MD_CNTL_WRCW		|
+				 MD_CNTL_MD_VALUE(0x1a));
+#endif
+			break;
+		default:
+			out_be32(&ddr->sdram_md_cntl,
+				MD_CNTL_MD_EN		|
+				MD_CNTL_CS_SEL_CS0_CS1	|
+				0x04000000		|
+				MD_CNTL_WRCW		|
+				MD_CNTL_MD_VALUE(0x02));
+#if (CONFIG_DIMM_SLOTS_PER_CTLR == 2)
+			if (!(regs->cs[2].config & SDRAM_CS_CONFIG_EN))
+				break;
+			while (in_be32(&ddr->sdram_md_cntl) & MD_CNTL_MD_EN)
+				;
+			out_be32(&ddr->sdram_md_cntl,
+				 MD_CNTL_MD_EN		|
+				 MD_CNTL_CS_SEL_CS2_CS3	|
+				 0x04000000		|
+				 MD_CNTL_WRCW		|
+				 MD_CNTL_MD_VALUE(0x02));
+#endif
+			printf("Unsupported RC10\n");
+			break;
+		}
+
+		while (in_be32(&ddr->sdram_md_cntl) & 0x80000000)
+			;
+		udelay(6);
+		out_be32(&ddr->sdram_cfg, temp_sdram_cfg);
+		out_be32(&ddr->timing_cfg_2, regs->timing_cfg_2);
+		out_be32(&ddr->debug[2], 0x0);
+		out_be32(&ddr->ddr_zq_cntl, regs->ddr_zq_cntl);
+		out_be32(&ddr->ddr_wrlvl_cntl, regs->ddr_wrlvl_cntl);
+		out_be32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2);
+		out_be32(&ddr->debug[12], save1);
+		out_be32(&ddr->debug[21], save2);
+		out_be32(&ddr->sdram_interval, regs->ddr_sdram_interval);
+
+	}
+#endif
+	/*
+	 * For 8572 DDR1 erratum - DDR controller may enter illegal state
+	 * when operatiing in 32-bit bus mode with 4-beat bursts,
+	 * This erratum does not affect DDR3 mode, only for DDR2 mode.
+	 */
+#ifdef CONFIG_SYS_FSL_ERRATUM_DDR_115
+	debug("Workaround for ERRATUM_DDR_115\n");
+	if ((((in_be32(&ddr->sdram_cfg) >> 24) & 0x7) == SDRAM_TYPE_DDR2)
+	    && in_be32(&ddr->sdram_cfg) & 0x80000) {
+		/* set DEBUG_1[31] */
+		setbits_be32(&ddr->debug[0], 1);
+	}
+#endif
+#ifdef CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134
+	debug("Workaround for ERRATUM_DDR111_DDR134\n");
+	/*
+	 * This is the combined workaround for DDR111 and DDR134
+	 * following the published errata for MPC8572
+	 */
+
+	/* 1. Set EEBACR[3] */
+	setbits_be32(&ecm->eebacr, 0x10000000);
+	debug("Setting EEBACR[3] to 0x%08x\n", in_be32(&ecm->eebacr));
+
+	/* 2. Set DINIT in SDRAM_CFG_2*/
+	setbits_be32(&ddr->sdram_cfg_2, SDRAM_CFG2_D_INIT);
+	debug("Setting sdram_cfg_2[D_INIT] to 0x%08x\n",
+		in_be32(&ddr->sdram_cfg_2));
+
+	/* 3. Set DEBUG_3[21] */
+	setbits_be32(&ddr->debug[2], 0x400);
+	debug("Setting DEBUG_3[21] to 0x%08x\n", in_be32(&ddr->debug[2]));
+
+#endif	/* part 1 of the workaound */
+
+	/*
+	 * 500 painful micro-seconds must elapse between
+	 * the DDR clock setup and the DDR config enable.
+	 * DDR2 need 200 us, and DDR3 need 500 us from spec,
+	 * we choose the max, that is 500 us for all of case.
+	 */
+	udelay(500);
+	asm volatile("sync;isync");
+
+	/* Let the controller go */
+	temp_sdram_cfg = in_be32(&ddr->sdram_cfg) & ~SDRAM_CFG_BI;
+	out_be32(&ddr->sdram_cfg, temp_sdram_cfg | SDRAM_CFG_MEM_EN);
+	asm volatile("sync;isync");
+
+	total_gb_size_per_controller = 0;
+	for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
+		if (!(regs->cs[i].config & 0x80000000))
+			continue;
+		total_gb_size_per_controller += 1 << (
+			((regs->cs[i].config >> 14) & 0x3) + 2 +
+			((regs->cs[i].config >> 8) & 0x7) + 12 +
+			((regs->cs[i].config >> 0) & 0x7) + 8 +
+			3 - ((regs->ddr_sdram_cfg >> 19) & 0x3) -
+			26);			/* minus 26 (count of 64M) */
+	}
+	if (fsl_ddr_get_intl3r() & 0x80000000)	/* 3-way interleaving */
+		total_gb_size_per_controller *= 3;
+	else if (regs->cs[0].config & 0x20000000) /* 2-way interleaving */
+		total_gb_size_per_controller <<= 1;
+	/*
+	 * total memory / bus width = transactions needed
+	 * transactions needed / data rate = seconds
+	 * to add plenty of buffer, double the time
+	 * For example, 2GB on 666MT/s 64-bit bus takes about 402ms
+	 * Let's wait for 800ms
+	 */
+	bus_width = 3 - ((ddr->sdram_cfg & SDRAM_CFG_DBW_MASK)
+			>> SDRAM_CFG_DBW_SHIFT);
+	timeout = ((total_gb_size_per_controller << (6 - bus_width)) * 100 /
+		(get_ddr_freq(0) >> 20)) << 1;
+#ifdef CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134
+	timeout_save = timeout;
+#endif
+	total_gb_size_per_controller >>= 4;	/* shift down to gb size */
+	debug("total %d GB\n", total_gb_size_per_controller);
+	debug("Need to wait up to %d * 10ms\n", timeout);
+
+	/* Poll DDR_SDRAM_CFG_2[D_INIT] bit until auto-data init is done.  */
+	while ((in_be32(&ddr->sdram_cfg_2) & SDRAM_CFG2_D_INIT) &&
+		(timeout >= 0)) {
+		udelay(10000);		/* throttle polling rate */
+		timeout--;
+	}
+
+	if (timeout <= 0)
+		printf("Waiting for D_INIT timeout. Memory may not work.\n");
+
+#ifdef CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134
+	/* continue this workaround */
+
+	/* 4. Clear DEBUG3[21] */
+	clrbits_be32(&ddr->debug[2], 0x400);
+	debug("Clearing D3[21] to 0x%08x\n", in_be32(&ddr->debug[2]));
+
+	/* DDR134 workaround starts */
+	/* A: Clear sdram_cfg_2[odt_cfg] */
+	clrbits_be32(&ddr->sdram_cfg_2, SDRAM_CFG2_ODT_CFG_MASK);
+	debug("Clearing SDRAM_CFG2[ODT_CFG] to 0x%08x\n",
+		in_be32(&ddr->sdram_cfg_2));
+
+	/* B: Set DEBUG1[15] */
+	setbits_be32(&ddr->debug[0], 0x10000);
+	debug("Setting D1[15] to 0x%08x\n", in_be32(&ddr->debug[0]));
+
+	/* C: Set timing_cfg_2[cpo] to 0b11111 */
+	setbits_be32(&ddr->timing_cfg_2, TIMING_CFG_2_CPO_MASK);
+	debug("Setting TMING_CFG_2[CPO] to 0x%08x\n",
+		in_be32(&ddr->timing_cfg_2));
+
+	/* D: Set D6 to 0x9f9f9f9f */
+	out_be32(&ddr->debug[5], 0x9f9f9f9f);
+	debug("Setting D6 to 0x%08x\n", in_be32(&ddr->debug[5]));
+
+	/* E: Set D7 to 0x9f9f9f9f */
+	out_be32(&ddr->debug[6], 0x9f9f9f9f);
+	debug("Setting D7 to 0x%08x\n", in_be32(&ddr->debug[6]));
+
+	/* F: Set D2[20] */
+	setbits_be32(&ddr->debug[1], 0x800);
+	debug("Setting D2[20] to 0x%08x\n", in_be32(&ddr->debug[1]));
+
+	/* G: Poll on D2[20] until cleared */
+	while (in_be32(&ddr->debug[1]) & 0x800)
+		udelay(10000);          /* throttle polling rate */
+
+	/* H: Clear D1[15] */
+	clrbits_be32(&ddr->debug[0], 0x10000);
+	debug("Setting D1[15] to 0x%08x\n", in_be32(&ddr->debug[0]));
+
+	/* I: Set sdram_cfg_2[odt_cfg] */
+	setbits_be32(&ddr->sdram_cfg_2,
+		regs->ddr_sdram_cfg_2 & SDRAM_CFG2_ODT_CFG_MASK);
+	debug("Setting sdram_cfg_2 to 0x%08x\n", in_be32(&ddr->sdram_cfg_2));
+
+	/* Continuing with the DDR111 workaround */
+	/* 5. Set D2[21] */
+	setbits_be32(&ddr->debug[1], 0x400);
+	debug("Setting D2[21] to 0x%08x\n", in_be32(&ddr->debug[1]));
+
+	/* 6. Poll D2[21] until its cleared */
+	while (in_be32(&ddr->debug[1]) & 0x400)
+		udelay(10000);          /* throttle polling rate */
+
+	/* 7. Wait for state machine 2nd run, roughly 400ms/GB */
+	debug("Wait for %d * 10ms\n", timeout_save);
+	udelay(timeout_save * 10000);
+
+	/* 8. Set sdram_cfg_2[dinit] if options requires */
+	setbits_be32(&ddr->sdram_cfg_2,
+		regs->ddr_sdram_cfg_2 & SDRAM_CFG2_D_INIT);
+	debug("Setting sdram_cfg_2 to 0x%08x\n", in_be32(&ddr->sdram_cfg_2));
+
+	/* 9. Poll until dinit is cleared */
+	timeout = timeout_save;
+	debug("Need to wait up to %d * 10ms\n", timeout);
+	while ((in_be32(&ddr->sdram_cfg_2) & SDRAM_CFG2_D_INIT) &&
+		(timeout >= 0)) {
+		udelay(10000);		/* throttle polling rate */
+		timeout--;
+	}
+
+	if (timeout <= 0)
+		printf("Waiting for D_INIT timeout. Memory may not work.\n");
+
+	/* 10. Clear EEBACR[3] */
+	clrbits_be32(&ecm->eebacr, 10000000);
+	debug("Clearing EEBACR[3] to 0x%08x\n", in_be32(&ecm->eebacr));
+
+	if (csn != -1) {
+		csn_bnds_t = (unsigned int *) &regs->cs[csn].bnds;
+		*csn_bnds_t = csn_bnds_backup;
+		debug("Change cs%d_bnds back to 0x%08x\n",
+			csn, regs->cs[csn].bnds);
+		setbits_be32(&ddr->sdram_cfg, 0x2);	/* MEM_HALT */
+		switch (csn) {
+		case 0:
+			out_be32(&ddr->cs0_bnds, regs->cs[csn].bnds);
+			break;
+		case 1:
+			out_be32(&ddr->cs1_bnds, regs->cs[csn].bnds);
+			break;
+		case 2:
+			out_be32(&ddr->cs2_bnds, regs->cs[csn].bnds);
+			break;
+		case 3:
+			out_be32(&ddr->cs3_bnds, regs->cs[csn].bnds);
+			break;
+		}
+		clrbits_be32(&ddr->sdram_cfg, 0x2);
+	}
+#endif /* CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134 */
+}
diff --git a/drivers/ddr/fsl/mpc86xx_ddr.c b/drivers/ddr/fsl/mpc86xx_ddr.c
new file mode 100644
index 0000000000..4551ed87db
--- /dev/null
+++ b/drivers/ddr/fsl/mpc86xx_ddr.c
@@ -0,0 +1,85 @@
+/*
+ * Copyright 2008 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * Version 2 as published by the Free Software Foundation.
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <fsl_ddr_sdram.h>
+
+#if (CONFIG_CHIP_SELECTS_PER_CTRL > 4)
+#error Invalid setting for CONFIG_CHIP_SELECTS_PER_CTRL
+#endif
+
+void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
+			     unsigned int ctrl_num, int step)
+{
+	unsigned int i;
+	struct ccsr_ddr __iomem *ddr;
+
+	switch (ctrl_num) {
+	case 0:
+		ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
+		break;
+	case 1:
+		ddr = (void *)CONFIG_SYS_FSL_DDR2_ADDR;
+		break;
+	default:
+		printf("%s unexpected ctrl_num = %u\n", __FUNCTION__, ctrl_num);
+		return;
+	}
+
+	for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
+		if (i == 0) {
+			out_be32(&ddr->cs0_bnds, regs->cs[i].bnds);
+			out_be32(&ddr->cs0_config, regs->cs[i].config);
+
+		} else if (i == 1) {
+			out_be32(&ddr->cs1_bnds, regs->cs[i].bnds);
+			out_be32(&ddr->cs1_config, regs->cs[i].config);
+
+		} else if (i == 2) {
+			out_be32(&ddr->cs2_bnds, regs->cs[i].bnds);
+			out_be32(&ddr->cs2_config, regs->cs[i].config);
+
+		} else if (i == 3) {
+			out_be32(&ddr->cs3_bnds, regs->cs[i].bnds);
+			out_be32(&ddr->cs3_config, regs->cs[i].config);
+		}
+	}
+
+	out_be32(&ddr->timing_cfg_3, regs->timing_cfg_3);
+	out_be32(&ddr->timing_cfg_0, regs->timing_cfg_0);
+	out_be32(&ddr->timing_cfg_1, regs->timing_cfg_1);
+	out_be32(&ddr->timing_cfg_2, regs->timing_cfg_2);
+	out_be32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2);
+	out_be32(&ddr->sdram_mode, regs->ddr_sdram_mode);
+	out_be32(&ddr->sdram_mode_2, regs->ddr_sdram_mode_2);
+	out_be32(&ddr->sdram_md_cntl, regs->ddr_sdram_md_cntl);
+	out_be32(&ddr->sdram_interval, regs->ddr_sdram_interval);
+	out_be32(&ddr->sdram_data_init, regs->ddr_data_init);
+	out_be32(&ddr->sdram_clk_cntl, regs->ddr_sdram_clk_cntl);
+	out_be32(&ddr->init_addr, regs->ddr_init_addr);
+	out_be32(&ddr->init_ext_addr, regs->ddr_init_ext_addr);
+
+	debug("before go\n");
+
+	/*
+	 * 200 painful micro-seconds must elapse between
+	 * the DDR clock setup and the DDR config enable.
+	 */
+	udelay(200);
+	asm volatile("sync;isync");
+
+	out_be32(&ddr->sdram_cfg, regs->ddr_sdram_cfg);
+
+	/*
+	 * Poll DDR_SDRAM_CFG_2[D_INIT] bit until auto-data init is done
+	 */
+	while (in_be32(&ddr->sdram_cfg_2) & 0x10) {
+		udelay(10000);		/* throttle polling rate */
+	}
+}
diff --git a/drivers/ddr/fsl/options.c b/drivers/ddr/fsl/options.c
new file mode 100644
index 0000000000..b0cf046fdc
--- /dev/null
+++ b/drivers/ddr/fsl/options.c
@@ -0,0 +1,1160 @@
+/*
+ * Copyright 2008, 2010-2012 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <hwconfig.h>
+#include <fsl_ddr_sdram.h>
+
+#include <fsl_ddr.h>
+
+/*
+ * Use our own stack based buffer before relocation to allow accessing longer
+ * hwconfig strings that might be in the environment before we've relocated.
+ * This is pretty fragile on both the use of stack and if the buffer is big
+ * enough. However we will get a warning from getenv_f for the later.
+ */
+
+/* Board-specific functions defined in each board's ddr.c */
+extern void fsl_ddr_board_options(memctl_options_t *popts,
+		dimm_params_t *pdimm,
+		unsigned int ctrl_num);
+
+struct dynamic_odt {
+	unsigned int odt_rd_cfg;
+	unsigned int odt_wr_cfg;
+	unsigned int odt_rtt_norm;
+	unsigned int odt_rtt_wr;
+};
+
+#ifdef CONFIG_SYS_FSL_DDR3
+static const struct dynamic_odt single_Q[4] = {
+	{	/* cs0 */
+		FSL_DDR_ODT_NEVER,
+		FSL_DDR_ODT_CS_AND_OTHER_DIMM,
+		DDR3_RTT_20_OHM,
+		DDR3_RTT_120_OHM
+	},
+	{	/* cs1 */
+		FSL_DDR_ODT_NEVER,
+		FSL_DDR_ODT_NEVER,	/* tied high */
+		DDR3_RTT_OFF,
+		DDR3_RTT_120_OHM
+	},
+	{	/* cs2 */
+		FSL_DDR_ODT_NEVER,
+		FSL_DDR_ODT_CS_AND_OTHER_DIMM,
+		DDR3_RTT_20_OHM,
+		DDR3_RTT_120_OHM
+	},
+	{	/* cs3 */
+		FSL_DDR_ODT_NEVER,
+		FSL_DDR_ODT_NEVER,	/* tied high */
+		DDR3_RTT_OFF,
+		DDR3_RTT_120_OHM
+	}
+};
+
+static const struct dynamic_odt single_D[4] = {
+	{	/* cs0 */
+		FSL_DDR_ODT_NEVER,
+		FSL_DDR_ODT_ALL,
+		DDR3_RTT_40_OHM,
+		DDR3_RTT_OFF
+	},
+	{	/* cs1 */
+		FSL_DDR_ODT_NEVER,
+		FSL_DDR_ODT_NEVER,
+		DDR3_RTT_OFF,
+		DDR3_RTT_OFF
+	},
+	{0, 0, 0, 0},
+	{0, 0, 0, 0}
+};
+
+static const struct dynamic_odt single_S[4] = {
+	{	/* cs0 */
+		FSL_DDR_ODT_NEVER,
+		FSL_DDR_ODT_ALL,
+		DDR3_RTT_40_OHM,
+		DDR3_RTT_OFF
+	},
+	{0, 0, 0, 0},
+	{0, 0, 0, 0},
+	{0, 0, 0, 0},
+};
+
+static const struct dynamic_odt dual_DD[4] = {
+	{	/* cs0 */
+		FSL_DDR_ODT_NEVER,
+		FSL_DDR_ODT_SAME_DIMM,
+		DDR3_RTT_120_OHM,
+		DDR3_RTT_OFF
+	},
+	{	/* cs1 */
+		FSL_DDR_ODT_OTHER_DIMM,
+		FSL_DDR_ODT_OTHER_DIMM,
+		DDR3_RTT_30_OHM,
+		DDR3_RTT_OFF
+	},
+	{	/* cs2 */
+		FSL_DDR_ODT_NEVER,
+		FSL_DDR_ODT_SAME_DIMM,
+		DDR3_RTT_120_OHM,
+		DDR3_RTT_OFF
+	},
+	{	/* cs3 */
+		FSL_DDR_ODT_OTHER_DIMM,
+		FSL_DDR_ODT_OTHER_DIMM,
+		DDR3_RTT_30_OHM,
+		DDR3_RTT_OFF
+	}
+};
+
+static const struct dynamic_odt dual_DS[4] = {
+	{	/* cs0 */
+		FSL_DDR_ODT_NEVER,
+		FSL_DDR_ODT_SAME_DIMM,
+		DDR3_RTT_120_OHM,
+		DDR3_RTT_OFF
+	},
+	{	/* cs1 */
+		FSL_DDR_ODT_OTHER_DIMM,
+		FSL_DDR_ODT_OTHER_DIMM,
+		DDR3_RTT_30_OHM,
+		DDR3_RTT_OFF
+	},
+	{	/* cs2 */
+		FSL_DDR_ODT_OTHER_DIMM,
+		FSL_DDR_ODT_ALL,
+		DDR3_RTT_20_OHM,
+		DDR3_RTT_120_OHM
+	},
+	{0, 0, 0, 0}
+};
+static const struct dynamic_odt dual_SD[4] = {
+	{	/* cs0 */
+		FSL_DDR_ODT_OTHER_DIMM,
+		FSL_DDR_ODT_ALL,
+		DDR3_RTT_20_OHM,
+		DDR3_RTT_120_OHM
+	},
+	{0, 0, 0, 0},
+	{	/* cs2 */
+		FSL_DDR_ODT_NEVER,
+		FSL_DDR_ODT_SAME_DIMM,
+		DDR3_RTT_120_OHM,
+		DDR3_RTT_OFF
+	},
+	{	/* cs3 */
+		FSL_DDR_ODT_OTHER_DIMM,
+		FSL_DDR_ODT_OTHER_DIMM,
+		DDR3_RTT_20_OHM,
+		DDR3_RTT_OFF
+	}
+};
+
+static const struct dynamic_odt dual_SS[4] = {
+	{	/* cs0 */
+		FSL_DDR_ODT_OTHER_DIMM,
+		FSL_DDR_ODT_ALL,
+		DDR3_RTT_30_OHM,
+		DDR3_RTT_120_OHM
+	},
+	{0, 0, 0, 0},
+	{	/* cs2 */
+		FSL_DDR_ODT_OTHER_DIMM,
+		FSL_DDR_ODT_ALL,
+		DDR3_RTT_30_OHM,
+		DDR3_RTT_120_OHM
+	},
+	{0, 0, 0, 0}
+};
+
+static const struct dynamic_odt dual_D0[4] = {
+	{	/* cs0 */
+		FSL_DDR_ODT_NEVER,
+		FSL_DDR_ODT_SAME_DIMM,
+		DDR3_RTT_40_OHM,
+		DDR3_RTT_OFF
+	},
+	{	/* cs1 */
+		FSL_DDR_ODT_NEVER,
+		FSL_DDR_ODT_NEVER,
+		DDR3_RTT_OFF,
+		DDR3_RTT_OFF
+	},
+	{0, 0, 0, 0},
+	{0, 0, 0, 0}
+};
+
+static const struct dynamic_odt dual_0D[4] = {
+	{0, 0, 0, 0},
+	{0, 0, 0, 0},
+	{	/* cs2 */
+		FSL_DDR_ODT_NEVER,
+		FSL_DDR_ODT_SAME_DIMM,
+		DDR3_RTT_40_OHM,
+		DDR3_RTT_OFF
+	},
+	{	/* cs3 */
+		FSL_DDR_ODT_NEVER,
+		FSL_DDR_ODT_NEVER,
+		DDR3_RTT_OFF,
+		DDR3_RTT_OFF
+	}
+};
+
+static const struct dynamic_odt dual_S0[4] = {
+	{	/* cs0 */
+		FSL_DDR_ODT_NEVER,
+		FSL_DDR_ODT_CS,
+		DDR3_RTT_40_OHM,
+		DDR3_RTT_OFF
+	},
+	{0, 0, 0, 0},
+	{0, 0, 0, 0},
+	{0, 0, 0, 0}
+
+};
+
+static const struct dynamic_odt dual_0S[4] = {
+	{0, 0, 0, 0},
+	{0, 0, 0, 0},
+	{	/* cs2 */
+		FSL_DDR_ODT_NEVER,
+		FSL_DDR_ODT_CS,
+		DDR3_RTT_40_OHM,
+		DDR3_RTT_OFF
+	},
+	{0, 0, 0, 0}
+
+};
+
+static const struct dynamic_odt odt_unknown[4] = {
+	{	/* cs0 */
+		FSL_DDR_ODT_NEVER,
+		FSL_DDR_ODT_CS,
+		DDR3_RTT_120_OHM,
+		DDR3_RTT_OFF
+	},
+	{	/* cs1 */
+		FSL_DDR_ODT_NEVER,
+		FSL_DDR_ODT_CS,
+		DDR3_RTT_120_OHM,
+		DDR3_RTT_OFF
+	},
+	{	/* cs2 */
+		FSL_DDR_ODT_NEVER,
+		FSL_DDR_ODT_CS,
+		DDR3_RTT_120_OHM,
+		DDR3_RTT_OFF
+	},
+	{	/* cs3 */
+		FSL_DDR_ODT_NEVER,
+		FSL_DDR_ODT_CS,
+		DDR3_RTT_120_OHM,
+		DDR3_RTT_OFF
+	}
+};
+#else	/* CONFIG_SYS_FSL_DDR3 */
+static const struct dynamic_odt single_Q[4] = {
+	{0, 0, 0, 0},
+	{0, 0, 0, 0},
+	{0, 0, 0, 0},
+	{0, 0, 0, 0}
+};
+
+static const struct dynamic_odt single_D[4] = {
+	{	/* cs0 */
+		FSL_DDR_ODT_NEVER,
+		FSL_DDR_ODT_ALL,
+		DDR2_RTT_150_OHM,
+		DDR2_RTT_OFF
+	},
+	{	/* cs1 */
+		FSL_DDR_ODT_NEVER,
+		FSL_DDR_ODT_NEVER,
+		DDR2_RTT_OFF,
+		DDR2_RTT_OFF
+	},
+	{0, 0, 0, 0},
+	{0, 0, 0, 0}
+};
+
+static const struct dynamic_odt single_S[4] = {
+	{	/* cs0 */
+		FSL_DDR_ODT_NEVER,
+		FSL_DDR_ODT_ALL,
+		DDR2_RTT_150_OHM,
+		DDR2_RTT_OFF
+	},
+	{0, 0, 0, 0},
+	{0, 0, 0, 0},
+	{0, 0, 0, 0},
+};
+
+static const struct dynamic_odt dual_DD[4] = {
+	{	/* cs0 */
+		FSL_DDR_ODT_OTHER_DIMM,
+		FSL_DDR_ODT_OTHER_DIMM,
+		DDR2_RTT_75_OHM,
+		DDR2_RTT_OFF
+	},
+	{	/* cs1 */
+		FSL_DDR_ODT_NEVER,
+		FSL_DDR_ODT_NEVER,
+		DDR2_RTT_OFF,
+		DDR2_RTT_OFF
+	},
+	{	/* cs2 */
+		FSL_DDR_ODT_OTHER_DIMM,
+		FSL_DDR_ODT_OTHER_DIMM,
+		DDR2_RTT_75_OHM,
+		DDR2_RTT_OFF
+	},
+	{	/* cs3 */
+		FSL_DDR_ODT_NEVER,
+		FSL_DDR_ODT_NEVER,
+		DDR2_RTT_OFF,
+		DDR2_RTT_OFF
+	}
+};
+
+static const struct dynamic_odt dual_DS[4] = {
+	{	/* cs0 */
+		FSL_DDR_ODT_OTHER_DIMM,
+		FSL_DDR_ODT_OTHER_DIMM,
+		DDR2_RTT_75_OHM,
+		DDR2_RTT_OFF
+	},
+	{	/* cs1 */
+		FSL_DDR_ODT_NEVER,
+		FSL_DDR_ODT_NEVER,
+		DDR2_RTT_OFF,
+		DDR2_RTT_OFF
+	},
+	{	/* cs2 */
+		FSL_DDR_ODT_OTHER_DIMM,
+		FSL_DDR_ODT_OTHER_DIMM,
+		DDR2_RTT_75_OHM,
+		DDR2_RTT_OFF
+	},
+	{0, 0, 0, 0}
+};
+
+static const struct dynamic_odt dual_SD[4] = {
+	{	/* cs0 */
+		FSL_DDR_ODT_OTHER_DIMM,
+		FSL_DDR_ODT_OTHER_DIMM,
+		DDR2_RTT_75_OHM,
+		DDR2_RTT_OFF
+	},
+	{0, 0, 0, 0},
+	{	/* cs2 */
+		FSL_DDR_ODT_OTHER_DIMM,
+		FSL_DDR_ODT_OTHER_DIMM,
+		DDR2_RTT_75_OHM,
+		DDR2_RTT_OFF
+	},
+	{	/* cs3 */
+		FSL_DDR_ODT_NEVER,
+		FSL_DDR_ODT_NEVER,
+		DDR2_RTT_OFF,
+		DDR2_RTT_OFF
+	}
+};
+
+static const struct dynamic_odt dual_SS[4] = {
+	{	/* cs0 */
+		FSL_DDR_ODT_OTHER_DIMM,
+		FSL_DDR_ODT_OTHER_DIMM,
+		DDR2_RTT_75_OHM,
+		DDR2_RTT_OFF
+	},
+	{0, 0, 0, 0},
+	{	/* cs2 */
+		FSL_DDR_ODT_OTHER_DIMM,
+		FSL_DDR_ODT_OTHER_DIMM,
+		DDR2_RTT_75_OHM,
+		DDR2_RTT_OFF
+	},
+	{0, 0, 0, 0}
+};
+
+static const struct dynamic_odt dual_D0[4] = {
+	{	/* cs0 */
+		FSL_DDR_ODT_NEVER,
+		FSL_DDR_ODT_ALL,
+		DDR2_RTT_150_OHM,
+		DDR2_RTT_OFF
+	},
+	{	/* cs1 */
+		FSL_DDR_ODT_NEVER,
+		FSL_DDR_ODT_NEVER,
+		DDR2_RTT_OFF,
+		DDR2_RTT_OFF
+	},
+	{0, 0, 0, 0},
+	{0, 0, 0, 0}
+};
+
+static const struct dynamic_odt dual_0D[4] = {
+	{0, 0, 0, 0},
+	{0, 0, 0, 0},
+	{	/* cs2 */
+		FSL_DDR_ODT_NEVER,
+		FSL_DDR_ODT_ALL,
+		DDR2_RTT_150_OHM,
+		DDR2_RTT_OFF
+	},
+	{	/* cs3 */
+		FSL_DDR_ODT_NEVER,
+		FSL_DDR_ODT_NEVER,
+		DDR2_RTT_OFF,
+		DDR2_RTT_OFF
+	}
+};
+
+static const struct dynamic_odt dual_S0[4] = {
+	{	/* cs0 */
+		FSL_DDR_ODT_NEVER,
+		FSL_DDR_ODT_CS,
+		DDR2_RTT_150_OHM,
+		DDR2_RTT_OFF
+	},
+	{0, 0, 0, 0},
+	{0, 0, 0, 0},
+	{0, 0, 0, 0}
+
+};
+
+static const struct dynamic_odt dual_0S[4] = {
+	{0, 0, 0, 0},
+	{0, 0, 0, 0},
+	{	/* cs2 */
+		FSL_DDR_ODT_NEVER,
+		FSL_DDR_ODT_CS,
+		DDR2_RTT_150_OHM,
+		DDR2_RTT_OFF
+	},
+	{0, 0, 0, 0}
+
+};
+
+static const struct dynamic_odt odt_unknown[4] = {
+	{	/* cs0 */
+		FSL_DDR_ODT_NEVER,
+		FSL_DDR_ODT_CS,
+		DDR2_RTT_75_OHM,
+		DDR2_RTT_OFF
+	},
+	{	/* cs1 */
+		FSL_DDR_ODT_NEVER,
+		FSL_DDR_ODT_NEVER,
+		DDR2_RTT_OFF,
+		DDR2_RTT_OFF
+	},
+	{	/* cs2 */
+		FSL_DDR_ODT_NEVER,
+		FSL_DDR_ODT_CS,
+		DDR2_RTT_75_OHM,
+		DDR2_RTT_OFF
+	},
+	{	/* cs3 */
+		FSL_DDR_ODT_NEVER,
+		FSL_DDR_ODT_NEVER,
+		DDR2_RTT_OFF,
+		DDR2_RTT_OFF
+	}
+};
+#endif
+
+/*
+ * Automatically seleect bank interleaving mode based on DIMMs
+ * in this order: cs0_cs1_cs2_cs3, cs0_cs1, null.
+ * This function only deal with one or two slots per controller.
+ */
+static inline unsigned int auto_bank_intlv(dimm_params_t *pdimm)
+{
+#if (CONFIG_DIMM_SLOTS_PER_CTLR == 1)
+	if (pdimm[0].n_ranks == 4)
+		return FSL_DDR_CS0_CS1_CS2_CS3;
+	else if (pdimm[0].n_ranks == 2)
+		return FSL_DDR_CS0_CS1;
+#elif (CONFIG_DIMM_SLOTS_PER_CTLR == 2)
+#ifdef CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
+	if (pdimm[0].n_ranks == 4)
+		return FSL_DDR_CS0_CS1_CS2_CS3;
+#endif
+	if (pdimm[0].n_ranks == 2) {
+		if (pdimm[1].n_ranks == 2)
+			return FSL_DDR_CS0_CS1_CS2_CS3;
+		else
+			return FSL_DDR_CS0_CS1;
+	}
+#endif
+	return 0;
+}
+
+unsigned int populate_memctl_options(int all_dimms_registered,
+			memctl_options_t *popts,
+			dimm_params_t *pdimm,
+			unsigned int ctrl_num)
+{
+	unsigned int i;
+	char buffer[HWCONFIG_BUFFER_SIZE];
+	char *buf = NULL;
+#if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR2)
+	const struct dynamic_odt *pdodt = odt_unknown;
+#endif
+	ulong ddr_freq;
+
+	/*
+	 * Extract hwconfig from environment since we have not properly setup
+	 * the environment but need it for ddr config params
+	 */
+	if (getenv_f("hwconfig", buffer, sizeof(buffer)) > 0)
+		buf = buffer;
+
+#if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR2)
+	/* Chip select options. */
+	if (CONFIG_DIMM_SLOTS_PER_CTLR == 1) {
+		switch (pdimm[0].n_ranks) {
+		case 1:
+			pdodt = single_S;
+			break;
+		case 2:
+			pdodt = single_D;
+			break;
+		case 4:
+			pdodt = single_Q;
+			break;
+		}
+	} else if (CONFIG_DIMM_SLOTS_PER_CTLR == 2) {
+		switch (pdimm[0].n_ranks) {
+#ifdef CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
+		case 4:
+			pdodt = single_Q;
+			if (pdimm[1].n_ranks)
+				printf("Error: Quad- and Dual-rank DIMMs "
+					"cannot be used together\n");
+			break;
+#endif
+		case 2:
+			switch (pdimm[1].n_ranks) {
+			case 2:
+				pdodt = dual_DD;
+				break;
+			case 1:
+				pdodt = dual_DS;
+				break;
+			case 0:
+				pdodt = dual_D0;
+				break;
+			}
+			break;
+		case 1:
+			switch (pdimm[1].n_ranks) {
+			case 2:
+				pdodt = dual_SD;
+				break;
+			case 1:
+				pdodt = dual_SS;
+				break;
+			case 0:
+				pdodt = dual_S0;
+				break;
+			}
+			break;
+		case 0:
+			switch (pdimm[1].n_ranks) {
+			case 2:
+				pdodt = dual_0D;
+				break;
+			case 1:
+				pdodt = dual_0S;
+				break;
+			}
+			break;
+		}
+	}
+#endif
+
+	/* Pick chip-select local options. */
+	for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
+#if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR2)
+		popts->cs_local_opts[i].odt_rd_cfg = pdodt[i].odt_rd_cfg;
+		popts->cs_local_opts[i].odt_wr_cfg = pdodt[i].odt_wr_cfg;
+		popts->cs_local_opts[i].odt_rtt_norm = pdodt[i].odt_rtt_norm;
+		popts->cs_local_opts[i].odt_rtt_wr = pdodt[i].odt_rtt_wr;
+#else
+		popts->cs_local_opts[i].odt_rd_cfg = FSL_DDR_ODT_NEVER;
+		popts->cs_local_opts[i].odt_wr_cfg = FSL_DDR_ODT_CS;
+#endif
+		popts->cs_local_opts[i].auto_precharge = 0;
+	}
+
+	/* Pick interleaving mode. */
+
+	/*
+	 * 0 = no interleaving
+	 * 1 = interleaving between 2 controllers
+	 */
+	popts->memctl_interleaving = 0;
+
+	/*
+	 * 0 = cacheline
+	 * 1 = page
+	 * 2 = (logical) bank
+	 * 3 = superbank (only if CS interleaving is enabled)
+	 */
+	popts->memctl_interleaving_mode = 0;
+
+	/*
+	 * 0: cacheline: bit 30 of the 36-bit physical addr selects the memctl
+	 * 1: page:      bit to the left of the column bits selects the memctl
+	 * 2: bank:      bit to the left of the bank bits selects the memctl
+	 * 3: superbank: bit to the left of the chip select selects the memctl
+	 *
+	 * NOTE: ba_intlv (rank interleaving) is independent of memory
+	 * controller interleaving; it is only within a memory controller.
+	 * Must use superbank interleaving if rank interleaving is used and
+	 * memory controller interleaving is enabled.
+	 */
+
+	/*
+	 * 0 = no
+	 * 0x40 = CS0,CS1
+	 * 0x20 = CS2,CS3
+	 * 0x60 = CS0,CS1 + CS2,CS3
+	 * 0x04 = CS0,CS1,CS2,CS3
+	 */
+	popts->ba_intlv_ctl = 0;
+
+	/* Memory Organization Parameters */
+	popts->registered_dimm_en = all_dimms_registered;
+
+	/* Operational Mode Paramters */
+
+	/* Pick ECC modes */
+	popts->ecc_mode = 0;		  /* 0 = disabled, 1 = enabled */
+#ifdef CONFIG_DDR_ECC
+	if (hwconfig_sub_f("fsl_ddr", "ecc", buf)) {
+		if (hwconfig_subarg_cmp_f("fsl_ddr", "ecc", "on", buf))
+			popts->ecc_mode = 1;
+	} else
+		popts->ecc_mode = 1;
+#endif
+	popts->ecc_init_using_memctl = 1; /* 0 = use DMA, 1 = use memctl */
+
+	/*
+	 * Choose DQS config
+	 * 0 for DDR1
+	 * 1 for DDR2
+	 */
+#if defined(CONFIG_SYS_FSL_DDR1)
+	popts->dqs_config = 0;
+#elif defined(CONFIG_SYS_FSL_DDR2) || defined(CONFIG_SYS_FSL_DDR3)
+	popts->dqs_config = 1;
+#endif
+
+	/* Choose self-refresh during sleep. */
+	popts->self_refresh_in_sleep = 1;
+
+	/* Choose dynamic power management mode. */
+	popts->dynamic_power = 0;
+
+	/*
+	 * check first dimm for primary sdram width
+	 * presuming all dimms are similar
+	 * 0 = 64-bit, 1 = 32-bit, 2 = 16-bit
+	 */
+#if defined(CONFIG_SYS_FSL_DDR1) || defined(CONFIG_SYS_FSL_DDR2)
+	if (pdimm[0].n_ranks != 0) {
+		if ((pdimm[0].data_width >= 64) && \
+			(pdimm[0].data_width <= 72))
+			popts->data_bus_width = 0;
+		else if ((pdimm[0].data_width >= 32) || \
+			(pdimm[0].data_width <= 40))
+			popts->data_bus_width = 1;
+		else {
+			panic("Error: data width %u is invalid!\n",
+				pdimm[0].data_width);
+		}
+	}
+#else
+	if (pdimm[0].n_ranks != 0) {
+		if (pdimm[0].primary_sdram_width == 64)
+			popts->data_bus_width = 0;
+		else if (pdimm[0].primary_sdram_width == 32)
+			popts->data_bus_width = 1;
+		else if (pdimm[0].primary_sdram_width == 16)
+			popts->data_bus_width = 2;
+		else {
+			panic("Error: primary sdram width %u is invalid!\n",
+				pdimm[0].primary_sdram_width);
+		}
+	}
+#endif
+
+	popts->x4_en = (pdimm[0].device_width == 4) ? 1 : 0;
+
+	/* Choose burst length. */
+#if defined(CONFIG_SYS_FSL_DDR3)
+#if defined(CONFIG_E500MC)
+	popts->otf_burst_chop_en = 0;	/* on-the-fly burst chop disable */
+	popts->burst_length = DDR_BL8;	/* Fixed 8-beat burst len */
+#else
+	if ((popts->data_bus_width == 1) || (popts->data_bus_width == 2)) {
+		/* 32-bit or 16-bit bus */
+		popts->otf_burst_chop_en = 0;
+		popts->burst_length = DDR_BL8;
+	} else {
+		popts->otf_burst_chop_en = 1;	/* on-the-fly burst chop */
+		popts->burst_length = DDR_OTF;	/* on-the-fly BC4 and BL8 */
+	}
+#endif
+#else
+	popts->burst_length = DDR_BL4;	/* has to be 4 for DDR2 */
+#endif
+
+	/* Choose ddr controller address mirror mode */
+#if defined(CONFIG_SYS_FSL_DDR3)
+	popts->mirrored_dimm = pdimm[0].mirrored_dimm;
+#endif
+
+	/* Global Timing Parameters. */
+	debug("mclk_ps = %u ps\n", get_memory_clk_period_ps());
+
+	/* Pick a caslat override. */
+	popts->cas_latency_override = 0;
+	popts->cas_latency_override_value = 3;
+	if (popts->cas_latency_override) {
+		debug("using caslat override value = %u\n",
+		       popts->cas_latency_override_value);
+	}
+
+	/* Decide whether to use the computed derated latency */
+	popts->use_derated_caslat = 0;
+
+	/* Choose an additive latency. */
+	popts->additive_latency_override = 0;
+	popts->additive_latency_override_value = 3;
+	if (popts->additive_latency_override) {
+		debug("using additive latency override value = %u\n",
+		       popts->additive_latency_override_value);
+	}
+
+	/*
+	 * 2T_EN setting
+	 *
+	 * Factors to consider for 2T_EN:
+	 *	- number of DIMMs installed
+	 *	- number of components, number of active ranks
+	 *	- how much time you want to spend playing around
+	 */
+	popts->twot_en = 0;
+	popts->threet_en = 0;
+
+	/* for RDIMM, address parity enable */
+	popts->ap_en = 1;
+
+	/*
+	 * BSTTOPRE precharge interval
+	 *
+	 * Set this to 0 for global auto precharge
+	 *
+	 * FIXME: Should this be configured in picoseconds?
+	 * Why it should be in ps:  better understanding of this
+	 * relative to actual DRAM timing parameters such as tRAS.
+	 * e.g. tRAS(min) = 40 ns
+	 */
+	popts->bstopre = 0x100;
+
+	/* Minimum CKE pulse width -- tCKE(MIN) */
+	popts->tcke_clock_pulse_width_ps
+		= mclk_to_picos(FSL_DDR_MIN_TCKE_PULSE_WIDTH_DDR);
+
+	/*
+	 * Window for four activates -- tFAW
+	 *
+	 * FIXME: UM: applies only to DDR2/DDR3 with eight logical banks only
+	 * FIXME: varies depending upon number of column addresses or data
+	 * FIXME: width, was considering looking at pdimm->primary_sdram_width
+	 */
+#if defined(CONFIG_SYS_FSL_DDR1)
+	popts->tfaw_window_four_activates_ps = mclk_to_picos(1);
+
+#elif defined(CONFIG_SYS_FSL_DDR2)
+	/*
+	 * x4/x8;  some datasheets have 35000
+	 * x16 wide columns only?  Use 50000?
+	 */
+	popts->tfaw_window_four_activates_ps = 37500;
+
+#elif defined(CONFIG_SYS_FSL_DDR3)
+	popts->tfaw_window_four_activates_ps = pdimm[0].tfaw_ps;
+#endif
+	popts->zq_en = 0;
+	popts->wrlvl_en = 0;
+#if defined(CONFIG_SYS_FSL_DDR3)
+	/*
+	 * due to ddr3 dimm is fly-by topology
+	 * we suggest to enable write leveling to
+	 * meet the tQDSS under different loading.
+	 */
+	popts->wrlvl_en = 1;
+	popts->zq_en = 1;
+	popts->wrlvl_override = 0;
+#endif
+
+	/*
+	 * Check interleaving configuration from environment.
+	 * Please refer to doc/README.fsl-ddr for the detail.
+	 *
+	 * If memory controller interleaving is enabled, then the data
+	 * bus widths must be programmed identically for all memory controllers.
+	 *
+	 * Attempt to set all controllers to the same chip select
+	 * interleaving mode. It will do a best effort to get the
+	 * requested ranks interleaved together such that the result
+	 * should be a subset of the requested configuration.
+	 *
+	 * if CONFIG_SYS_FSL_DDR_INTLV_256B is defined, mandatory interleaving
+	 * with 256 Byte is enabled.
+	 */
+#if (CONFIG_NUM_DDR_CONTROLLERS > 1)
+	if (!hwconfig_sub_f("fsl_ddr", "ctlr_intlv", buf))
+#ifdef CONFIG_SYS_FSL_DDR_INTLV_256B
+		;
+#else
+		goto done;
+#endif
+	if (pdimm[0].n_ranks == 0) {
+		printf("There is no rank on CS0 for controller %d.\n", ctrl_num);
+		popts->memctl_interleaving = 0;
+		goto done;
+	}
+	popts->memctl_interleaving = 1;
+#ifdef CONFIG_SYS_FSL_DDR_INTLV_256B
+	popts->memctl_interleaving_mode = FSL_DDR_256B_INTERLEAVING;
+	popts->memctl_interleaving = 1;
+	debug("256 Byte interleaving\n");
+	goto done;
+#endif
+	/*
+	 * test null first. if CONFIG_HWCONFIG is not defined
+	 * hwconfig_arg_cmp returns non-zero
+	 */
+	if (hwconfig_subarg_cmp_f("fsl_ddr", "ctlr_intlv",
+				    "null", buf)) {
+		popts->memctl_interleaving = 0;
+		debug("memory controller interleaving disabled.\n");
+	} else if (hwconfig_subarg_cmp_f("fsl_ddr",
+					"ctlr_intlv",
+					"cacheline", buf)) {
+		popts->memctl_interleaving_mode =
+			((CONFIG_NUM_DDR_CONTROLLERS == 3) && ctrl_num == 2) ?
+			0 : FSL_DDR_CACHE_LINE_INTERLEAVING;
+		popts->memctl_interleaving =
+			((CONFIG_NUM_DDR_CONTROLLERS == 3) && ctrl_num == 2) ?
+			0 : 1;
+	} else if (hwconfig_subarg_cmp_f("fsl_ddr",
+					"ctlr_intlv",
+					"page", buf)) {
+		popts->memctl_interleaving_mode =
+			((CONFIG_NUM_DDR_CONTROLLERS == 3) && ctrl_num == 2) ?
+			0 : FSL_DDR_PAGE_INTERLEAVING;
+		popts->memctl_interleaving =
+			((CONFIG_NUM_DDR_CONTROLLERS == 3) && ctrl_num == 2) ?
+			0 : 1;
+	} else if (hwconfig_subarg_cmp_f("fsl_ddr",
+					"ctlr_intlv",
+					"bank", buf)) {
+		popts->memctl_interleaving_mode =
+			((CONFIG_NUM_DDR_CONTROLLERS == 3) && ctrl_num == 2) ?
+			0 : FSL_DDR_BANK_INTERLEAVING;
+		popts->memctl_interleaving =
+			((CONFIG_NUM_DDR_CONTROLLERS == 3) && ctrl_num == 2) ?
+			0 : 1;
+	} else if (hwconfig_subarg_cmp_f("fsl_ddr",
+					"ctlr_intlv",
+					"superbank", buf)) {
+		popts->memctl_interleaving_mode =
+			((CONFIG_NUM_DDR_CONTROLLERS == 3) && ctrl_num == 2) ?
+			0 : FSL_DDR_SUPERBANK_INTERLEAVING;
+		popts->memctl_interleaving =
+			((CONFIG_NUM_DDR_CONTROLLERS == 3) && ctrl_num == 2) ?
+			0 : 1;
+#if (CONFIG_NUM_DDR_CONTROLLERS == 3)
+	} else if (hwconfig_subarg_cmp_f("fsl_ddr",
+					"ctlr_intlv",
+					"3way_1KB", buf)) {
+		popts->memctl_interleaving_mode =
+			FSL_DDR_3WAY_1KB_INTERLEAVING;
+	} else if (hwconfig_subarg_cmp_f("fsl_ddr",
+					"ctlr_intlv",
+					"3way_4KB", buf)) {
+		popts->memctl_interleaving_mode =
+			FSL_DDR_3WAY_4KB_INTERLEAVING;
+	} else if (hwconfig_subarg_cmp_f("fsl_ddr",
+					"ctlr_intlv",
+					"3way_8KB", buf)) {
+		popts->memctl_interleaving_mode =
+			FSL_DDR_3WAY_8KB_INTERLEAVING;
+#elif (CONFIG_NUM_DDR_CONTROLLERS == 4)
+	} else if (hwconfig_subarg_cmp_f("fsl_ddr",
+					"ctlr_intlv",
+					"4way_1KB", buf)) {
+		popts->memctl_interleaving_mode =
+			FSL_DDR_4WAY_1KB_INTERLEAVING;
+	} else if (hwconfig_subarg_cmp_f("fsl_ddr",
+					"ctlr_intlv",
+					"4way_4KB", buf)) {
+		popts->memctl_interleaving_mode =
+			FSL_DDR_4WAY_4KB_INTERLEAVING;
+	} else if (hwconfig_subarg_cmp_f("fsl_ddr",
+					"ctlr_intlv",
+					"4way_8KB", buf)) {
+		popts->memctl_interleaving_mode =
+			FSL_DDR_4WAY_8KB_INTERLEAVING;
+#endif
+	} else {
+		popts->memctl_interleaving = 0;
+		printf("hwconfig has unrecognized parameter for ctlr_intlv.\n");
+	}
+done:
+#endif
+	if ((hwconfig_sub_f("fsl_ddr", "bank_intlv", buf)) &&
+		(CONFIG_CHIP_SELECTS_PER_CTRL > 1)) {
+		/* test null first. if CONFIG_HWCONFIG is not defined,
+		 * hwconfig_subarg_cmp_f returns non-zero */
+		if (hwconfig_subarg_cmp_f("fsl_ddr", "bank_intlv",
+					    "null", buf))
+			debug("bank interleaving disabled.\n");
+		else if (hwconfig_subarg_cmp_f("fsl_ddr", "bank_intlv",
+						 "cs0_cs1", buf))
+			popts->ba_intlv_ctl = FSL_DDR_CS0_CS1;
+		else if (hwconfig_subarg_cmp_f("fsl_ddr", "bank_intlv",
+						 "cs2_cs3", buf))
+			popts->ba_intlv_ctl = FSL_DDR_CS2_CS3;
+		else if (hwconfig_subarg_cmp_f("fsl_ddr", "bank_intlv",
+						 "cs0_cs1_and_cs2_cs3", buf))
+			popts->ba_intlv_ctl = FSL_DDR_CS0_CS1_AND_CS2_CS3;
+		else if (hwconfig_subarg_cmp_f("fsl_ddr", "bank_intlv",
+						 "cs0_cs1_cs2_cs3", buf))
+			popts->ba_intlv_ctl = FSL_DDR_CS0_CS1_CS2_CS3;
+		else if (hwconfig_subarg_cmp_f("fsl_ddr", "bank_intlv",
+						"auto", buf))
+			popts->ba_intlv_ctl = auto_bank_intlv(pdimm);
+		else
+			printf("hwconfig has unrecognized parameter for bank_intlv.\n");
+		switch (popts->ba_intlv_ctl & FSL_DDR_CS0_CS1_CS2_CS3) {
+		case FSL_DDR_CS0_CS1_CS2_CS3:
+#if (CONFIG_DIMM_SLOTS_PER_CTLR == 1)
+			if (pdimm[0].n_ranks < 4) {
+				popts->ba_intlv_ctl = 0;
+				printf("Not enough bank(chip-select) for "
+					"CS0+CS1+CS2+CS3 on controller %d, "
+					"interleaving disabled!\n", ctrl_num);
+			}
+#elif (CONFIG_DIMM_SLOTS_PER_CTLR == 2)
+#ifdef CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
+			if (pdimm[0].n_ranks == 4)
+				break;
+#endif
+			if ((pdimm[0].n_ranks < 2) && (pdimm[1].n_ranks < 2)) {
+				popts->ba_intlv_ctl = 0;
+				printf("Not enough bank(chip-select) for "
+					"CS0+CS1+CS2+CS3 on controller %d, "
+					"interleaving disabled!\n", ctrl_num);
+			}
+			if (pdimm[0].capacity != pdimm[1].capacity) {
+				popts->ba_intlv_ctl = 0;
+				printf("Not identical DIMM size for "
+					"CS0+CS1+CS2+CS3 on controller %d, "
+					"interleaving disabled!\n", ctrl_num);
+			}
+#endif
+			break;
+		case FSL_DDR_CS0_CS1:
+			if (pdimm[0].n_ranks < 2) {
+				popts->ba_intlv_ctl = 0;
+				printf("Not enough bank(chip-select) for "
+					"CS0+CS1 on controller %d, "
+					"interleaving disabled!\n", ctrl_num);
+			}
+			break;
+		case FSL_DDR_CS2_CS3:
+#if (CONFIG_DIMM_SLOTS_PER_CTLR == 1)
+			if (pdimm[0].n_ranks < 4) {
+				popts->ba_intlv_ctl = 0;
+				printf("Not enough bank(chip-select) for CS2+CS3 "
+					"on controller %d, interleaving disabled!\n", ctrl_num);
+			}
+#elif (CONFIG_DIMM_SLOTS_PER_CTLR == 2)
+			if (pdimm[1].n_ranks < 2) {
+				popts->ba_intlv_ctl = 0;
+				printf("Not enough bank(chip-select) for CS2+CS3 "
+					"on controller %d, interleaving disabled!\n", ctrl_num);
+			}
+#endif
+			break;
+		case FSL_DDR_CS0_CS1_AND_CS2_CS3:
+#if (CONFIG_DIMM_SLOTS_PER_CTLR == 1)
+			if (pdimm[0].n_ranks < 4) {
+				popts->ba_intlv_ctl = 0;
+				printf("Not enough bank(CS) for CS0+CS1 and "
+					"CS2+CS3 on controller %d, "
+					"interleaving disabled!\n", ctrl_num);
+			}
+#elif (CONFIG_DIMM_SLOTS_PER_CTLR == 2)
+			if ((pdimm[0].n_ranks < 2) || (pdimm[1].n_ranks < 2)) {
+				popts->ba_intlv_ctl = 0;
+				printf("Not enough bank(CS) for CS0+CS1 and "
+					"CS2+CS3 on controller %d, "
+					"interleaving disabled!\n", ctrl_num);
+			}
+#endif
+			break;
+		default:
+			popts->ba_intlv_ctl = 0;
+			break;
+		}
+	}
+
+	if (hwconfig_sub_f("fsl_ddr", "addr_hash", buf)) {
+		if (hwconfig_subarg_cmp_f("fsl_ddr", "addr_hash", "null", buf))
+			popts->addr_hash = 0;
+		else if (hwconfig_subarg_cmp_f("fsl_ddr", "addr_hash",
+					       "true", buf))
+			popts->addr_hash = 1;
+	}
+
+	if (pdimm[0].n_ranks == 4)
+		popts->quad_rank_present = 1;
+
+	ddr_freq = get_ddr_freq(0) / 1000000;
+	if (popts->registered_dimm_en) {
+		popts->rcw_override = 1;
+		popts->rcw_1 = 0x000a5a00;
+		if (ddr_freq <= 800)
+			popts->rcw_2 = 0x00000000;
+		else if (ddr_freq <= 1066)
+			popts->rcw_2 = 0x00100000;
+		else if (ddr_freq <= 1333)
+			popts->rcw_2 = 0x00200000;
+		else
+			popts->rcw_2 = 0x00300000;
+	}
+
+	fsl_ddr_board_options(popts, pdimm, ctrl_num);
+
+	return 0;
+}
+
+void check_interleaving_options(fsl_ddr_info_t *pinfo)
+{
+	int i, j, k, check_n_ranks, intlv_invalid = 0;
+	unsigned int check_intlv, check_n_row_addr, check_n_col_addr;
+	unsigned long long check_rank_density;
+	struct dimm_params_s *dimm;
+	/*
+	 * Check if all controllers are configured for memory
+	 * controller interleaving. Identical dimms are recommended. At least
+	 * the size, row and col address should be checked.
+	 */
+	j = 0;
+	check_n_ranks = pinfo->dimm_params[0][0].n_ranks;
+	check_rank_density = pinfo->dimm_params[0][0].rank_density;
+	check_n_row_addr =  pinfo->dimm_params[0][0].n_row_addr;
+	check_n_col_addr = pinfo->dimm_params[0][0].n_col_addr;
+	check_intlv = pinfo->memctl_opts[0].memctl_interleaving_mode;
+	for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
+		dimm = &pinfo->dimm_params[i][0];
+		if (!pinfo->memctl_opts[i].memctl_interleaving) {
+			continue;
+		} else if (((check_rank_density != dimm->rank_density) ||
+		     (check_n_ranks != dimm->n_ranks) ||
+		     (check_n_row_addr != dimm->n_row_addr) ||
+		     (check_n_col_addr != dimm->n_col_addr) ||
+		     (check_intlv !=
+			pinfo->memctl_opts[i].memctl_interleaving_mode))){
+			intlv_invalid = 1;
+			break;
+		} else {
+			j++;
+		}
+
+	}
+	if (intlv_invalid) {
+		for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++)
+			pinfo->memctl_opts[i].memctl_interleaving = 0;
+		printf("Not all DIMMs are identical. "
+			"Memory controller interleaving disabled.\n");
+	} else {
+		switch (check_intlv) {
+		case FSL_DDR_256B_INTERLEAVING:
+		case FSL_DDR_CACHE_LINE_INTERLEAVING:
+		case FSL_DDR_PAGE_INTERLEAVING:
+		case FSL_DDR_BANK_INTERLEAVING:
+		case FSL_DDR_SUPERBANK_INTERLEAVING:
+			if (3 == CONFIG_NUM_DDR_CONTROLLERS)
+				k = 2;
+			else
+				k = CONFIG_NUM_DDR_CONTROLLERS;
+			break;
+		case FSL_DDR_3WAY_1KB_INTERLEAVING:
+		case FSL_DDR_3WAY_4KB_INTERLEAVING:
+		case FSL_DDR_3WAY_8KB_INTERLEAVING:
+		case FSL_DDR_4WAY_1KB_INTERLEAVING:
+		case FSL_DDR_4WAY_4KB_INTERLEAVING:
+		case FSL_DDR_4WAY_8KB_INTERLEAVING:
+		default:
+			k = CONFIG_NUM_DDR_CONTROLLERS;
+			break;
+		}
+		debug("%d of %d controllers are interleaving.\n", j, k);
+		if (j && (j != k)) {
+			for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++)
+				pinfo->memctl_opts[i].memctl_interleaving = 0;
+			printf("Not all controllers have compatible "
+				"interleaving mode. All disabled.\n");
+		}
+	}
+	debug("Checking interleaving options completed\n");
+}
+
+int fsl_use_spd(void)
+{
+	int use_spd = 0;
+
+#ifdef CONFIG_DDR_SPD
+	char buffer[HWCONFIG_BUFFER_SIZE];
+	char *buf = NULL;
+
+	/*
+	 * Extract hwconfig from environment since we have not properly setup
+	 * the environment but need it for ddr config params
+	 */
+	if (getenv_f("hwconfig", buffer, sizeof(buffer)) > 0)
+		buf = buffer;
+
+	/* if hwconfig is not enabled, or "sdram" is not defined, use spd */
+	if (hwconfig_sub_f("fsl_ddr", "sdram", buf)) {
+		if (hwconfig_subarg_cmp_f("fsl_ddr", "sdram", "spd", buf))
+			use_spd = 1;
+		else if (hwconfig_subarg_cmp_f("fsl_ddr", "sdram",
+					       "fixed", buf))
+			use_spd = 0;
+		else
+			use_spd = 1;
+	} else
+		use_spd = 1;
+#endif
+
+	return use_spd;
+}
diff --git a/drivers/ddr/fsl/util.c b/drivers/ddr/fsl/util.c
new file mode 100644
index 0000000000..ad53658fc9
--- /dev/null
+++ b/drivers/ddr/fsl/util.c
@@ -0,0 +1,274 @@
+/*
+ * Copyright 2008-2012 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * Version 2 as published by the Free Software Foundation.
+ */
+
+#include <common.h>
+#ifdef CONFIG_PPC
+#include <asm/fsl_law.h>
+#endif
+#include <div64.h>
+
+#include <fsl_ddr.h>
+#include <fsl_immap.h>
+#include <asm/io.h>
+
+/* To avoid 64-bit full-divides, we factor this here */
+#define ULL_2E12 2000000000000ULL
+#define UL_5POW12 244140625UL
+#define UL_2POW13 (1UL << 13)
+
+#define ULL_8FS 0xFFFFFFFFULL
+
+/*
+ * Round up mclk_ps to nearest 1 ps in memory controller code
+ * if the error is 0.5ps or more.
+ *
+ * If an imprecise data rate is too high due to rounding error
+ * propagation, compute a suitably rounded mclk_ps to compute
+ * a working memory controller configuration.
+ */
+unsigned int get_memory_clk_period_ps(void)
+{
+	unsigned int data_rate = get_ddr_freq(0);
+	unsigned int result;
+
+	/* Round to nearest 10ps, being careful about 64-bit multiply/divide */
+	unsigned long long rem, mclk_ps = ULL_2E12;
+
+	/* Now perform the big divide, the result fits in 32-bits */
+	rem = do_div(mclk_ps, data_rate);
+	result = (rem >= (data_rate >> 1)) ? mclk_ps + 1 : mclk_ps;
+
+	return result;
+}
+
+/* Convert picoseconds into DRAM clock cycles (rounding up if needed). */
+unsigned int picos_to_mclk(unsigned int picos)
+{
+	unsigned long long clks, clks_rem;
+	unsigned long data_rate = get_ddr_freq(0);
+
+	/* Short circuit for zero picos */
+	if (!picos)
+		return 0;
+
+	/* First multiply the time by the data rate (32x32 => 64) */
+	clks = picos * (unsigned long long)data_rate;
+	/*
+	 * Now divide by 5^12 and track the 32-bit remainder, then divide
+	 * by 2*(2^12) using shifts (and updating the remainder).
+	 */
+	clks_rem = do_div(clks, UL_5POW12);
+	clks_rem += (clks & (UL_2POW13-1)) * UL_5POW12;
+	clks >>= 13;
+
+	/* If we had a remainder greater than the 1ps error, then round up */
+	if (clks_rem > data_rate)
+		clks++;
+
+	/* Clamp to the maximum representable value */
+	if (clks > ULL_8FS)
+		clks = ULL_8FS;
+	return (unsigned int) clks;
+}
+
+unsigned int mclk_to_picos(unsigned int mclk)
+{
+	return get_memory_clk_period_ps() * mclk;
+}
+
+#ifdef CONFIG_PPC
+void
+__fsl_ddr_set_lawbar(const common_timing_params_t *memctl_common_params,
+			   unsigned int law_memctl,
+			   unsigned int ctrl_num)
+{
+	unsigned long long base = memctl_common_params->base_address;
+	unsigned long long size = memctl_common_params->total_mem;
+
+	/*
+	 * If no DIMMs on this controller, do not proceed any further.
+	 */
+	if (!memctl_common_params->ndimms_present) {
+		return;
+	}
+
+#if !defined(CONFIG_PHYS_64BIT)
+	if (base >= CONFIG_MAX_MEM_MAPPED)
+		return;
+	if ((base + size) >= CONFIG_MAX_MEM_MAPPED)
+		size = CONFIG_MAX_MEM_MAPPED - base;
+#endif
+	if (set_ddr_laws(base, size, law_memctl) < 0) {
+		printf("%s: ERROR (ctrl #%d, TRGT ID=%x)\n", __func__, ctrl_num,
+			law_memctl);
+		return ;
+	}
+	debug("setup ddr law base = 0x%llx, size 0x%llx, TRGT_ID 0x%x\n",
+		base, size, law_memctl);
+}
+
+__attribute__((weak, alias("__fsl_ddr_set_lawbar"))) void
+fsl_ddr_set_lawbar(const common_timing_params_t *memctl_common_params,
+			 unsigned int memctl_interleaved,
+			 unsigned int ctrl_num);
+#endif
+
+void fsl_ddr_set_intl3r(const unsigned int granule_size)
+{
+#ifdef CONFIG_E6500
+	u32 *mcintl3r = (void *) (CONFIG_SYS_IMMR + 0x18004);
+	*mcintl3r = 0x80000000 | (granule_size & 0x1f);
+	debug("Enable MCINTL3R with granule size 0x%x\n", granule_size);
+#endif
+}
+
+u32 fsl_ddr_get_intl3r(void)
+{
+	u32 val = 0;
+#ifdef CONFIG_E6500
+	u32 *mcintl3r = (void *) (CONFIG_SYS_IMMR + 0x18004);
+	val = *mcintl3r;
+#endif
+	return val;
+}
+
+void board_add_ram_info(int use_default)
+{
+	struct ccsr_ddr __iomem *ddr =
+		(struct ccsr_ddr __iomem *)(CONFIG_SYS_FSL_DDR_ADDR);
+
+#if	defined(CONFIG_E6500) && (CONFIG_NUM_DDR_CONTROLLERS == 3)
+	u32 *mcintl3r = (void *) (CONFIG_SYS_IMMR + 0x18004);
+#endif
+#if (CONFIG_NUM_DDR_CONTROLLERS > 1)
+	uint32_t cs0_config = ddr_in32(&ddr->cs0_config);
+#endif
+	uint32_t sdram_cfg = ddr_in32(&ddr->sdram_cfg);
+	int cas_lat;
+
+#if CONFIG_NUM_DDR_CONTROLLERS >= 2
+	if (!(sdram_cfg & SDRAM_CFG_MEM_EN)) {
+		ddr = (void __iomem *)CONFIG_SYS_FSL_DDR2_ADDR;
+		sdram_cfg = ddr_in32(&ddr->sdram_cfg);
+	}
+#endif
+#if CONFIG_NUM_DDR_CONTROLLERS >= 3
+	if (!(sdram_cfg & SDRAM_CFG_MEM_EN)) {
+		ddr = (void __iomem *)CONFIG_SYS_FSL_DDR3_ADDR;
+		sdram_cfg = ddr_in32(&ddr->sdram_cfg);
+	}
+#endif
+	puts(" (DDR");
+	switch ((sdram_cfg & SDRAM_CFG_SDRAM_TYPE_MASK) >>
+		SDRAM_CFG_SDRAM_TYPE_SHIFT) {
+	case SDRAM_TYPE_DDR1:
+		puts("1");
+		break;
+	case SDRAM_TYPE_DDR2:
+		puts("2");
+		break;
+	case SDRAM_TYPE_DDR3:
+		puts("3");
+		break;
+	default:
+		puts("?");
+		break;
+	}
+
+	if (sdram_cfg & SDRAM_CFG_32_BE)
+		puts(", 32-bit");
+	else if (sdram_cfg & SDRAM_CFG_16_BE)
+		puts(", 16-bit");
+	else
+		puts(", 64-bit");
+
+	/* Calculate CAS latency based on timing cfg values */
+	cas_lat = ((ddr_in32(&ddr->timing_cfg_1) >> 16) & 0xf) + 1;
+	if ((ddr_in32(&ddr->timing_cfg_3) >> 12) & 1)
+		cas_lat += (8 << 1);
+	printf(", CL=%d", cas_lat >> 1);
+	if (cas_lat & 0x1)
+		puts(".5");
+
+	if (sdram_cfg & SDRAM_CFG_ECC_EN)
+		puts(", ECC on)");
+	else
+		puts(", ECC off)");
+
+#if (CONFIG_NUM_DDR_CONTROLLERS == 3)
+#ifdef CONFIG_E6500
+	if (*mcintl3r & 0x80000000) {
+		puts("\n");
+		puts("       DDR Controller Interleaving Mode: ");
+		switch (*mcintl3r & 0x1f) {
+		case FSL_DDR_3WAY_1KB_INTERLEAVING:
+			puts("3-way 1KB");
+			break;
+		case FSL_DDR_3WAY_4KB_INTERLEAVING:
+			puts("3-way 4KB");
+			break;
+		case FSL_DDR_3WAY_8KB_INTERLEAVING:
+			puts("3-way 8KB");
+			break;
+		default:
+			puts("3-way UNKNOWN");
+			break;
+		}
+	}
+#endif
+#endif
+#if (CONFIG_NUM_DDR_CONTROLLERS >= 2)
+	if (cs0_config & 0x20000000) {
+		puts("\n");
+		puts("       DDR Controller Interleaving Mode: ");
+
+		switch ((cs0_config >> 24) & 0xf) {
+		case FSL_DDR_256B_INTERLEAVING:
+			puts("256B");
+			break;
+		case FSL_DDR_CACHE_LINE_INTERLEAVING:
+			puts("cache line");
+			break;
+		case FSL_DDR_PAGE_INTERLEAVING:
+			puts("page");
+			break;
+		case FSL_DDR_BANK_INTERLEAVING:
+			puts("bank");
+			break;
+		case FSL_DDR_SUPERBANK_INTERLEAVING:
+			puts("super-bank");
+			break;
+		default:
+			puts("invalid");
+			break;
+		}
+	}
+#endif
+
+	if ((sdram_cfg >> 8) & 0x7f) {
+		puts("\n");
+		puts("       DDR Chip-Select Interleaving Mode: ");
+		switch(sdram_cfg >> 8 & 0x7f) {
+		case FSL_DDR_CS0_CS1_CS2_CS3:
+			puts("CS0+CS1+CS2+CS3");
+			break;
+		case FSL_DDR_CS0_CS1:
+			puts("CS0+CS1");
+			break;
+		case FSL_DDR_CS2_CS3:
+			puts("CS2+CS3");
+			break;
+		case FSL_DDR_CS0_CS1_AND_CS2_CS3:
+			puts("CS0+CS1 and CS2+CS3");
+			break;
+		default:
+			puts("invalid");
+			break;
+		}
+	}
+}
diff --git a/drivers/demo/Makefile b/drivers/demo/Makefile
new file mode 100644
index 0000000000..baaa2baa4e
--- /dev/null
+++ b/drivers/demo/Makefile
@@ -0,0 +1,9 @@
+#
+# Copyright (c) 2013 Google, Inc
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-$(CONFIG_DM_DEMO) += demo-uclass.o demo-pdata.o
+obj-$(CONFIG_DM_DEMO_SIMPLE) += demo-simple.o
+obj-$(CONFIG_DM_DEMO_SHAPE) += demo-shape.o
diff --git a/drivers/demo/demo-pdata.c b/drivers/demo/demo-pdata.c
new file mode 100644
index 0000000000..e92841db69
--- /dev/null
+++ b/drivers/demo/demo-pdata.c
@@ -0,0 +1,47 @@
+/*
+ * Copyright (c) 2013 Google, Inc
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <dm-demo.h>
+
+static const struct dm_demo_pdata red_square = {
+	.colour = "red",
+	.sides = 4.
+};
+static const struct dm_demo_pdata green_triangle = {
+	.colour = "green",
+	.sides = 3.
+};
+static const struct dm_demo_pdata yellow_hexagon = {
+	.colour = "yellow",
+	.sides = 6.
+};
+
+U_BOOT_DEVICE(demo0) = {
+	.name = "demo_shape_drv",
+	.platdata = &red_square,
+};
+
+U_BOOT_DEVICE(demo1) = {
+	.name = "demo_simple_drv",
+	.platdata = &red_square,
+};
+
+U_BOOT_DEVICE(demo2) = {
+	.name = "demo_shape_drv",
+	.platdata = &green_triangle,
+};
+
+U_BOOT_DEVICE(demo3) = {
+	.name = "demo_simple_drv",
+	.platdata = &yellow_hexagon,
+};
+
+U_BOOT_DEVICE(demo4) = {
+	.name = "demo_shape_drv",
+	.platdata = &yellow_hexagon,
+};
diff --git a/drivers/demo/demo-shape.c b/drivers/demo/demo-shape.c
new file mode 100644
index 0000000000..2f0eb96bb6
--- /dev/null
+++ b/drivers/demo/demo-shape.c
@@ -0,0 +1,127 @@
+/*
+ * Copyright (c) 2013 Google, Inc
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <errno.h>
+#include <fdtdec.h>
+#include <malloc.h>
+#include <dm-demo.h>
+#include <asm/io.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* Shape size */
+#define WIDTH	8
+#define HEIGHT	6
+
+struct shape_data {
+	int num_chars;	/* Number of non-space characters output so far */
+};
+
+/* Crazy little function to draw shapes on the console */
+static int shape_hello(struct device *dev, int ch)
+{
+	const struct dm_demo_pdata *pdata = dev_get_platdata(dev);
+	struct shape_data *data = dev_get_priv(dev);
+	static const struct shape {
+		int start;
+		int end;
+		int dstart;
+		int dend;
+	} shapes[3] = {
+		{ 0, 1, 0, 1 },
+		{ 0, WIDTH, 0, 0 },
+		{ HEIGHT / 2 - 1, WIDTH - HEIGHT / 2 + 1, -1, 1},
+	};
+	struct shape shape;
+	unsigned int index;
+	int line, pos, inside;
+	const char *colour = pdata->colour;
+	int first = 0;
+
+	if (!ch)
+		ch = pdata->default_char;
+	if (!ch)
+		ch = '@';
+
+	index = (pdata->sides / 2) - 1;
+	if (index >= ARRAY_SIZE(shapes))
+		return -EIO;
+	shape = shapes[index];
+
+	for (line = 0; line < HEIGHT; line++) {
+		first = 1;
+		for (pos = 0; pos < WIDTH; pos++) {
+			inside = pos >= shape.start && pos < shape.end;
+			if (inside) {
+				putc(first ? *colour++ : ch);
+				data->num_chars++;
+				first = 0;
+				if (!*colour)
+					colour = pdata->colour;
+			} else {
+				putc(' ');
+			}
+		}
+		putc('\n');
+		shape.start += shape.dstart;
+		shape.end += shape.dend;
+		if (shape.start < 0) {
+			shape.dstart = -shape.dstart;
+			shape.dend = -shape.dend;
+			shape.start += shape.dstart;
+			shape.end += shape.dend;
+		}
+	}
+
+	return 0;
+}
+
+static int shape_status(struct device *dev, int *status)
+{
+	struct shape_data *data = dev_get_priv(dev);
+
+	*status = data->num_chars;
+	return 0;
+}
+
+static const struct demo_ops shape_ops = {
+	.hello = shape_hello,
+	.status = shape_status,
+};
+
+static int shape_ofdata_to_platdata(struct device *dev)
+{
+	struct dm_demo_pdata *pdata = dev_get_platdata(dev);
+	int ret;
+
+	/* Parse the data that is common with all demo devices */
+	ret = demo_parse_dt(dev);
+	if (ret)
+		return ret;
+
+	/* Parse the data that only we need */
+	pdata->default_char = fdtdec_get_int(gd->fdt_blob, dev->of_offset,
+					     "character", '@');
+
+	return 0;
+}
+
+static const struct device_id demo_shape_id[] = {
+	{ "demo-shape", 0 },
+	{ },
+};
+
+U_BOOT_DRIVER(demo_shape_drv) = {
+	.name	= "demo_shape_drv",
+	.of_match = demo_shape_id,
+	.id	= UCLASS_DEMO,
+	.ofdata_to_platdata = shape_ofdata_to_platdata,
+	.ops	= &shape_ops,
+	.priv_auto_alloc_size = sizeof(struct shape_data),
+	.platdata_auto_alloc_size = sizeof(struct dm_demo_pdata),
+};
diff --git a/drivers/demo/demo-simple.c b/drivers/demo/demo-simple.c
new file mode 100644
index 0000000000..6ba8131728
--- /dev/null
+++ b/drivers/demo/demo-simple.c
@@ -0,0 +1,47 @@
+/*
+ * Copyright (c) 2013 Google, Inc
+ *
+ * (C) Copyright 2012
+ * Pavel Herrmann <morpheus.ibis@gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <dm-demo.h>
+#include <asm/io.h>
+
+static int simple_hello(struct device *dev, int ch)
+{
+	const struct dm_demo_pdata *pdata = dev_get_platdata(dev);
+
+	printf("Hello from %08x: %s %d\n", map_to_sysmem(dev), pdata->colour,
+	       pdata->sides);
+
+	return 0;
+}
+
+static const struct demo_ops simple_ops = {
+	.hello = simple_hello,
+};
+
+static int demo_shape_ofdata_to_platdata(struct device *dev)
+{
+	/* Parse the data that is common with all demo devices */
+	return demo_parse_dt(dev);
+}
+
+static const struct device_id demo_shape_id[] = {
+	{ "demo-simple", 0 },
+	{ },
+};
+
+U_BOOT_DRIVER(demo_simple_drv) = {
+	.name	= "demo_simple_drv",
+	.of_match = demo_shape_id,
+	.id	= UCLASS_DEMO,
+	.ofdata_to_platdata = demo_shape_ofdata_to_platdata,
+	.ops	= &simple_ops,
+	.platdata_auto_alloc_size = sizeof(struct dm_demo_pdata),
+};
diff --git a/drivers/demo/demo-uclass.c b/drivers/demo/demo-uclass.c
new file mode 100644
index 0000000000..48588be907
--- /dev/null
+++ b/drivers/demo/demo-uclass.c
@@ -0,0 +1,58 @@
+/*
+ * Copyright (c) 2013 Google, Inc
+ *
+ * (C) Copyright 2012
+ * Pavel Herrmann <morpheus.ibis@gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <dm-demo.h>
+#include <errno.h>
+#include <fdtdec.h>
+#include <malloc.h>
+#include <asm/io.h>
+#include <linux/list.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+UCLASS_DRIVER(demo) = {
+	.id		= UCLASS_DEMO,
+};
+
+int demo_hello(struct device *dev, int ch)
+{
+	const struct demo_ops *ops = device_get_ops(dev);
+
+	if (!ops->hello)
+		return -ENOSYS;
+
+	return ops->hello(dev, ch);
+}
+
+int demo_status(struct device *dev, int *status)
+{
+	const struct demo_ops *ops = device_get_ops(dev);
+
+	if (!ops->status)
+		return -ENOSYS;
+
+	return ops->status(dev, status);
+}
+
+int demo_parse_dt(struct device *dev)
+{
+	struct dm_demo_pdata *pdata = dev_get_platdata(dev);
+	int dn = dev->of_offset;
+
+	pdata->sides = fdtdec_get_int(gd->fdt_blob, dn, "sides", 0);
+	pdata->colour = fdt_getprop(gd->fdt_blob, dn, "colour", NULL);
+	if (!pdata->sides || !pdata->colour) {
+		debug("%s: Invalid device tree data\n", __func__);
+		return -EINVAL;
+	}
+
+	return 0;
+}
diff --git a/drivers/dfu/Makefile b/drivers/dfu/Makefile
index de9e44e1ef..def628dcdc 100644
--- a/drivers/dfu/Makefile
+++ b/drivers/dfu/Makefile
@@ -5,26 +5,7 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)libdfu.o
-
-COBJS-$(CONFIG_DFU_FUNCTION) += dfu.o
-COBJS-$(CONFIG_DFU_MMC) += dfu_mmc.o
-COBJS-$(CONFIG_DFU_NAND) += dfu_nand.o
-COBJS-$(CONFIG_DFU_RAM) += dfu_ram.o
-
-SRCS    := $(COBJS-y:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS-y))
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-$(CONFIG_DFU_FUNCTION) += dfu.o
+obj-$(CONFIG_DFU_MMC) += dfu_mmc.o
+obj-$(CONFIG_DFU_NAND) += dfu_nand.o
+obj-$(CONFIG_DFU_RAM) += dfu_ram.o
diff --git a/drivers/dfu/dfu.c b/drivers/dfu/dfu.c
index 56b21c78ab..8a09aafbf2 100644
--- a/drivers/dfu/dfu.c
+++ b/drivers/dfu/dfu.c
@@ -19,6 +19,7 @@
 static bool dfu_reset_request;
 static LIST_HEAD(dfu_list);
 static int dfu_alt_num;
+static int alt_num_cnt;
 
 bool dfu_reset(void)
 {
@@ -67,14 +68,19 @@ int dfu_init_env_entities(char *interface, int dev)
 static unsigned char *dfu_buf;
 static unsigned long dfu_buf_size = CONFIG_SYS_DFU_DATA_BUF_SIZE;
 
-static unsigned char *dfu_free_buf(void)
+unsigned char *dfu_free_buf(void)
 {
 	free(dfu_buf);
 	dfu_buf = NULL;
 	return dfu_buf;
 }
 
-static unsigned char *dfu_get_buf(void)
+unsigned long dfu_get_buf_size(void)
+{
+	return dfu_buf_size;
+}
+
+unsigned char *dfu_get_buf(void)
 {
 	char *s;
 
@@ -121,6 +127,28 @@ static int dfu_write_buffer_drain(struct dfu_entity *dfu)
 	return ret;
 }
 
+int dfu_flush(struct dfu_entity *dfu, void *buf, int size, int blk_seq_num)
+{
+	int ret = 0;
+
+	if (dfu->flush_medium)
+		ret = dfu->flush_medium(dfu);
+
+	printf("\nDFU complete CRC32: 0x%08x\n", dfu->crc);
+
+	/* clear everything */
+	dfu_free_buf();
+	dfu->crc = 0;
+	dfu->offset = 0;
+	dfu->i_blk_seq_num = 0;
+	dfu->i_buf_start = dfu_buf;
+	dfu->i_buf_end = dfu_buf;
+	dfu->i_buf = dfu->i_buf_start;
+	dfu->inited = 0;
+
+	return ret;
+}
+
 int dfu_write(struct dfu_entity *dfu, void *buf, int size, int blk_seq_num)
 {
 	int ret = 0;
@@ -191,26 +219,6 @@ int dfu_write(struct dfu_entity *dfu, void *buf, int size, int blk_seq_num)
 			ret = tret;
 	}
 
-	/* end? */
-	if (size == 0) {
-		/* Now try and flush to the medium if needed. */
-		if (dfu->flush_medium)
-			ret = dfu->flush_medium(dfu);
-		printf("\nDFU complete CRC32: 0x%08x\n", dfu->crc);
-
-		/* clear everything */
-		dfu_free_buf();
-		dfu->crc = 0;
-		dfu->offset = 0;
-		dfu->i_blk_seq_num = 0;
-		dfu->i_buf_start = dfu_buf;
-		dfu->i_buf_end = dfu_buf;
-		dfu->i_buf = dfu->i_buf_start;
-
-		dfu->inited = 0;
-
-	}
-
 	return ret = 0 ? size : ret;
 }
 
@@ -229,6 +237,7 @@ static int dfu_read_buffer_fill(struct dfu_entity *dfu, void *buf, int size)
 			dfu->crc = crc32(dfu->crc, buf, chunk);
 			dfu->i_buf += chunk;
 			dfu->b_left -= chunk;
+			dfu->r_left -= chunk;
 			size -= chunk;
 			buf += chunk;
 			readn += chunk;
@@ -287,7 +296,7 @@ int dfu_read(struct dfu_entity *dfu, void *buf, int size, int blk_seq_num)
 		dfu->offset = 0;
 		dfu->i_buf_end = dfu_get_buf() + dfu_buf_size;
 		dfu->i_buf = dfu->i_buf_start;
-		dfu->b_left = 0;
+		dfu->b_left = min(dfu_buf_size, dfu->r_left);
 
 		dfu->bad_skip = 0;
 
@@ -330,7 +339,7 @@ int dfu_read(struct dfu_entity *dfu, void *buf, int size, int blk_seq_num)
 }
 
 static int dfu_fill_entity(struct dfu_entity *dfu, char *s, int alt,
-			    char *interface, int num)
+			   char *interface, int num)
 {
 	char *st;
 
@@ -371,6 +380,8 @@ void dfu_free_entities(void)
 	if (t)
 		free(t);
 	INIT_LIST_HEAD(&dfu_list);
+
+	alt_num_cnt = 0;
 }
 
 int dfu_config_entities(char *env, char *interface, int num)
@@ -388,11 +399,12 @@ int dfu_config_entities(char *env, char *interface, int num)
 	for (i = 0; i < dfu_alt_num; i++) {
 
 		s = strsep(&env, ";");
-		ret = dfu_fill_entity(&dfu[i], s, i, interface, num);
+		ret = dfu_fill_entity(&dfu[i], s, alt_num_cnt, interface, num);
 		if (ret)
 			return -1;
 
 		list_add_tail(&dfu[i].list, &dfu_list);
+		alt_num_cnt++;
 	}
 
 	return 0;
@@ -440,3 +452,15 @@ struct dfu_entity *dfu_get_entity(int alt)
 
 	return NULL;
 }
+
+int dfu_get_alt(char *name)
+{
+	struct dfu_entity *dfu;
+
+	list_for_each_entry(dfu, &dfu_list, list) {
+		if (!strncmp(dfu->name, name, strlen(dfu->name)))
+			return dfu->alt;
+	}
+
+	return -ENODEV;
+}
diff --git a/drivers/dfu/dfu_mmc.c b/drivers/dfu/dfu_mmc.c
index f942758696..651cfff5b3 100644
--- a/drivers/dfu/dfu_mmc.c
+++ b/drivers/dfu/dfu_mmc.c
@@ -12,6 +12,7 @@
 #include <errno.h>
 #include <div64.h>
 #include <dfu.h>
+#include <mmc.h>
 
 static unsigned char __aligned(CONFIG_SYS_CACHELINE_SIZE)
 				dfu_file_buf[CONFIG_SYS_DFU_MAX_FILE_SIZE];
@@ -20,8 +21,8 @@ static long dfu_file_buf_len;
 static int mmc_block_op(enum dfu_op op, struct dfu_entity *dfu,
 			u64 offset, void *buf, long *len)
 {
-	char cmd_buf[DFU_CMD_BUF_SIZE];
-	u32 blk_start, blk_count;
+	struct mmc *mmc = find_mmc_device(dfu->dev_num);
+	u32 blk_start, blk_count, n = 0;
 
 	/*
 	 * We must ensure that we work in lba_blk_size chunks, so ALIGN
@@ -38,12 +39,28 @@ static int mmc_block_op(enum dfu_op op, struct dfu_entity *dfu,
 		return -EINVAL;
 	}
 
-	sprintf(cmd_buf, "mmc %s %p %x %x",
-		op == DFU_OP_READ ? "read" : "write",
-		 buf, blk_start, blk_count);
+	debug("%s: %s dev: %d start: %d cnt: %d buf: 0x%p\n", __func__,
+	      op == DFU_OP_READ ? "MMC READ" : "MMC WRITE", dfu->dev_num,
+	      blk_start, blk_count, buf);
+	switch (op) {
+	case DFU_OP_READ:
+		n = mmc->block_dev.block_read(dfu->dev_num, blk_start,
+					      blk_count, buf);
+		break;
+	case DFU_OP_WRITE:
+		n = mmc->block_dev.block_write(dfu->dev_num, blk_start,
+					       blk_count, buf);
+		break;
+	default:
+		error("Operation not supported\n");
+	}
+
+	if (n != blk_count) {
+		error("MMC operation failed");
+		return -EIO;
+	}
 
-	debug("%s: %s 0x%p\n", __func__, cmd_buf, cmd_buf);
-	return run_command(cmd_buf, 0);
+	return 0;
 }
 
 static int mmc_file_buffer(struct dfu_entity *dfu, void *buf, long *len)
@@ -73,16 +90,12 @@ static int mmc_file_op(enum dfu_op op, struct dfu_entity *dfu,
 			op == DFU_OP_READ ? "load" : "write",
 			dfu->data.mmc.dev, dfu->data.mmc.part,
 			(unsigned int) buf, dfu->name);
-		if (op == DFU_OP_WRITE)
-			sprintf(cmd_buf + strlen(cmd_buf), " %lx", *len);
 		break;
 	case DFU_FS_EXT4:
 		sprintf(cmd_buf, "ext4%s mmc %d:%d 0x%x /%s",
 			op == DFU_OP_READ ? "load" : "write",
 			dfu->data.mmc.dev, dfu->data.mmc.part,
 			(unsigned int) buf, dfu->name);
-		if (op == DFU_OP_WRITE)
-			sprintf(cmd_buf + strlen(cmd_buf), " %ld", *len);
 		break;
 	default:
 		printf("%s: Layout (%s) not (yet) supported!\n", __func__,
@@ -90,6 +103,9 @@ static int mmc_file_op(enum dfu_op op, struct dfu_entity *dfu,
 		return -1;
 	}
 
+	if (op == DFU_OP_WRITE)
+		sprintf(cmd_buf + strlen(cmd_buf), " %lx", *len);
+
 	debug("%s: %s 0x%p\n", __func__, cmd_buf, cmd_buf);
 
 	ret = run_command(cmd_buf, 0);
diff --git a/drivers/dfu/dfu_nand.c b/drivers/dfu/dfu_nand.c
index edbf5a97b9..2d07097e85 100644
--- a/drivers/dfu/dfu_nand.c
+++ b/drivers/dfu/dfu_nand.c
@@ -121,6 +121,7 @@ static int dfu_read_medium_nand(struct dfu_entity *dfu, u64 offset, void *buf,
 
 	switch (dfu->layout) {
 	case DFU_RAW_ADDR:
+		*len = dfu->data.nand.size;
 		ret = nand_block_read(dfu, offset, buf, len);
 		break;
 	default:
diff --git a/drivers/dma/Makefile b/drivers/dma/Makefile
index a6132e22e7..8b2821b762 100644
--- a/drivers/dma/Makefile
+++ b/drivers/dma/Makefile
@@ -5,29 +5,7 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	:= $(obj)libdma.o
-
-COBJS-$(CONFIG_FSLDMAFEC) += MCD_tasksInit.o MCD_dmaApi.o MCD_tasks.o
-COBJS-$(CONFIG_APBH_DMA) += apbh_dma.o
-COBJS-$(CONFIG_FSL_DMA) += fsl_dma.o
-COBJS-$(CONFIG_OMAP3_DMA) += omap3_dma.o
-
-COBJS	:= $(COBJS-y)
-SRCS	:= $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-
-all:	$(LIB)
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-$(CONFIG_FSLDMAFEC) += MCD_tasksInit.o MCD_dmaApi.o MCD_tasks.o
+obj-$(CONFIG_APBH_DMA) += apbh_dma.o
+obj-$(CONFIG_FSL_DMA) += fsl_dma.o
+obj-$(CONFIG_OMAP3_DMA) += omap3_dma.o
diff --git a/drivers/fpga/Makefile b/drivers/fpga/Makefile
index a1a0602ab2..dfb2e7fc76 100644
--- a/drivers/fpga/Makefile
+++ b/drivers/fpga/Makefile
@@ -5,40 +5,16 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	:= $(obj)libfpga.o
-
-ifdef CONFIG_FPGA
-COBJS-y += fpga.o
-COBJS-$(CONFIG_FPGA_SPARTAN2) += spartan2.o
-COBJS-$(CONFIG_FPGA_SPARTAN3) += spartan3.o
-COBJS-$(CONFIG_FPGA_VIRTEX2) += virtex2.o
-COBJS-$(CONFIG_FPGA_ZYNQPL) += zynqpl.o
-COBJS-$(CONFIG_FPGA_XILINX) += xilinx.o
-COBJS-$(CONFIG_FPGA_LATTICE) += ivm_core.o lattice.o
+obj-y += fpga.o
+obj-$(CONFIG_FPGA_SPARTAN2) += spartan2.o
+obj-$(CONFIG_FPGA_SPARTAN3) += spartan3.o
+obj-$(CONFIG_FPGA_VIRTEX2) += virtex2.o
+obj-$(CONFIG_FPGA_ZYNQPL) += zynqpl.o
+obj-$(CONFIG_FPGA_XILINX) += xilinx.o
+obj-$(CONFIG_FPGA_LATTICE) += ivm_core.o lattice.o
 ifdef CONFIG_FPGA_ALTERA
-COBJS-y += altera.o
-COBJS-$(CONFIG_FPGA_ACEX1K) += ACEX1K.o
-COBJS-$(CONFIG_FPGA_CYCLON2) += cyclon2.o
-COBJS-$(CONFIG_FPGA_STRATIX_II) += stratixII.o
-endif
+obj-y += altera.o
+obj-$(CONFIG_FPGA_ACEX1K) += ACEX1K.o
+obj-$(CONFIG_FPGA_CYCLON2) += cyclon2.o
+obj-$(CONFIG_FPGA_STRATIX_II) += stratixII.o
 endif
-
-COBJS	:= $(COBJS-y)
-SRCS	:= $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-
-all:	$(LIB)
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
diff --git a/drivers/fpga/zynqpl.c b/drivers/fpga/zynqpl.c
index 717c0394ca..923a1586d8 100644
--- a/drivers/fpga/zynqpl.c
+++ b/drivers/fpga/zynqpl.c
@@ -10,6 +10,7 @@
 #include <common.h>
 #include <asm/io.h>
 #include <zynqpl.h>
+#include <linux/sizes.h>
 #include <asm/arch/hardware.h>
 #include <asm/arch/sys_proto.h>
 
@@ -177,8 +178,24 @@ int zynq_load(Xilinx_desc *desc, const void *buf, size_t bsize)
 		return FPGA_FAIL;
 	}
 
-	if ((u32)buf_start & 0x3) {
-		u32 *new_buf = (u32 *)((u32)buf & ~0x3);
+	if ((u32)buf < SZ_1M) {
+		printf("%s: Bitstream has to be placed up to 1MB (%x)\n",
+		       __func__, (u32)buf);
+		return FPGA_FAIL;
+	}
+
+	if ((u32)buf != ALIGN((u32)buf, ARCH_DMA_MINALIGN)) {
+		u32 *new_buf = (u32 *)ALIGN((u32)buf, ARCH_DMA_MINALIGN);
+
+		/*
+		 * This might be dangerous but permits to flash if
+		 * ARCH_DMA_MINALIGN is greater than header size
+		 */
+		if (new_buf > buf_start) {
+			debug("%s: Aligned buffer is after buffer start\n",
+			      __func__);
+			new_buf -= ARCH_DMA_MINALIGN;
+		}
 
 		printf("%s: Align buffer at %x to %x(swap %d)\n", __func__,
 		       (u32)buf_start, (u32)new_buf, swap);
@@ -284,6 +301,10 @@ int zynq_load(Xilinx_desc *desc, const void *buf, size_t bsize)
 	debug("%s: Source = 0x%08X\n", __func__, (u32)buf);
 	debug("%s: Size = %zu\n", __func__, bsize);
 
+	/* flush(clean & invalidate) d-cache range buf */
+	flush_dcache_range((u32)buf, (u32)buf +
+			   roundup(bsize, ARCH_DMA_MINALIGN));
+
 	/* Set up the transfer */
 	writel((u32)buf | 1, &devcfg_base->dma_src_addr);
 	writel(0xFFFFFFFF, &devcfg_base->dma_dst_addr);
diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
index 71ddb00bb5..4e001e12bd 100644
--- a/drivers/gpio/Makefile
+++ b/drivers/gpio/Makefile
@@ -5,51 +5,32 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB 	:= $(obj)libgpio.o
-
-COBJS-$(CONFIG_AT91_GPIO)	+= at91_gpio.o
-COBJS-$(CONFIG_INTEL_ICH6_GPIO)	+= intel_ich6_gpio.o
-COBJS-$(CONFIG_KIRKWOOD_GPIO)	+= kw_gpio.o
-COBJS-$(CONFIG_MARVELL_GPIO)	+= mvgpio.o
-COBJS-$(CONFIG_MARVELL_MFP)	+= mvmfp.o
-COBJS-$(CONFIG_MXC_GPIO)	+= mxc_gpio.o
-COBJS-$(CONFIG_MXS_GPIO)	+= mxs_gpio.o
-COBJS-$(CONFIG_PCA953X)		+= pca953x.o
-COBJS-$(CONFIG_PCA9698)		+= pca9698.o
-COBJS-$(CONFIG_S5P)		+= s5p_gpio.o
-COBJS-$(CONFIG_SANDBOX_GPIO)	+= sandbox.o
-COBJS-$(CONFIG_SPEAR_GPIO)	+= spear_gpio.o
-COBJS-$(CONFIG_TEGRA_GPIO)	+= tegra_gpio.o
-COBJS-$(CONFIG_DA8XX_GPIO)	+= da8xx_gpio.o
-COBJS-$(CONFIG_DM644X_GPIO)	+= da8xx_gpio.o
-COBJS-$(CONFIG_ALTERA_PIO)	+= altera_pio.o
-COBJS-$(CONFIG_MPC83XX_GPIO)	+= mpc83xx_gpio.o
-COBJS-$(CONFIG_SH_GPIO_PFC)	+= sh_pfc.o
-COBJS-$(CONFIG_OMAP_GPIO)	+= omap_gpio.o
-COBJS-$(CONFIG_DB8500_GPIO)	+= db8500_gpio.o
-COBJS-$(CONFIG_BCM2835_GPIO)	+= bcm2835_gpio.o
-COBJS-$(CONFIG_S3C2440_GPIO)	+= s3c2440_gpio.o
-COBJS-$(CONFIG_XILINX_GPIO)	+= xilinx_gpio.o
-COBJS-$(CONFIG_ADI_GPIO2)	+= adi_gpio2.o
-COBJS-$(CONFIG_TCA642X)		+= tca642x.o
-
-COBJS	:= $(COBJS-y)
-SRCS 	:= $(COBJS:.o=.c)
-OBJS 	:= $(addprefix $(obj),$(COBJS))
-
-all:	$(LIB)
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-########################################################################
+obj-$(CONFIG_DM_GPIO)		+= gpio-uclass.o
+
+obj-$(CONFIG_AT91_GPIO)	+= at91_gpio.o
+obj-$(CONFIG_INTEL_ICH6_GPIO)	+= intel_ich6_gpio.o
+obj-$(CONFIG_KIRKWOOD_GPIO)	+= kw_gpio.o
+obj-$(CONFIG_KONA_GPIO)	+= kona_gpio.o
+obj-$(CONFIG_MARVELL_GPIO)	+= mvgpio.o
+obj-$(CONFIG_MARVELL_MFP)	+= mvmfp.o
+obj-$(CONFIG_MXC_GPIO)	+= mxc_gpio.o
+obj-$(CONFIG_MXS_GPIO)	+= mxs_gpio.o
+obj-$(CONFIG_PCA953X)		+= pca953x.o
+obj-$(CONFIG_PCA9698)		+= pca9698.o
+obj-$(CONFIG_S5P)		+= s5p_gpio.o
+obj-$(CONFIG_SANDBOX_GPIO)	+= sandbox.o
+obj-$(CONFIG_SPEAR_GPIO)	+= spear_gpio.o
+obj-$(CONFIG_TEGRA_GPIO)	+= tegra_gpio.o
+obj-$(CONFIG_DA8XX_GPIO)	+= da8xx_gpio.o
+obj-$(CONFIG_DM644X_GPIO)	+= da8xx_gpio.o
+obj-$(CONFIG_ALTERA_PIO)	+= altera_pio.o
+obj-$(CONFIG_MPC83XX_GPIO)	+= mpc83xx_gpio.o
+obj-$(CONFIG_SH_GPIO_PFC)	+= sh_pfc.o
+obj-$(CONFIG_OMAP_GPIO)	+= omap_gpio.o
+obj-$(CONFIG_DB8500_GPIO)	+= db8500_gpio.o
+obj-$(CONFIG_BCM2835_GPIO)	+= bcm2835_gpio.o
+obj-$(CONFIG_S3C2440_GPIO)	+= s3c2440_gpio.o
+obj-$(CONFIG_XILINX_GPIO)	+= xilinx_gpio.o
+obj-$(CONFIG_ADI_GPIO2)	+= adi_gpio2.o
+obj-$(CONFIG_TCA642X)		+= tca642x.o
+oby-$(CONFIG_SX151X)		+= sx151x.o
diff --git a/drivers/gpio/adi_gpio2.c b/drivers/gpio/adi_gpio2.c
index 051073cee3..88cd65b87f 100644
--- a/drivers/gpio/adi_gpio2.c
+++ b/drivers/gpio/adi_gpio2.c
@@ -10,22 +10,6 @@
 #include <common.h>
 #include <asm/errno.h>
 #include <asm/gpio.h>
-#include <asm/portmux.h>
-
-static struct gpio_port_t * const gpio_array[] = {
-	(struct gpio_port_t *)PORTA_FER,
-	(struct gpio_port_t *)PORTB_FER,
-	(struct gpio_port_t *)PORTC_FER,
-	(struct gpio_port_t *)PORTD_FER,
-	(struct gpio_port_t *)PORTE_FER,
-	(struct gpio_port_t *)PORTF_FER,
-	(struct gpio_port_t *)PORTG_FER,
-#if defined(CONFIG_BF54x)
-	(struct gpio_port_t *)PORTH_FER,
-	(struct gpio_port_t *)PORTI_FER,
-	(struct gpio_port_t *)PORTJ_FER,
-#endif
-};
 
 #define RESOURCE_LABEL_SIZE	16
 
@@ -98,7 +82,6 @@ static void port_setup(unsigned gpio, unsigned short usage)
 	else
 		gpio_array[gpio_bank(gpio)]->port_fer_set = gpio_bit(gpio);
 #endif
-	SSYNC();
 }
 
 inline void portmux_setup(unsigned short per)
diff --git a/drivers/gpio/at91_gpio.c b/drivers/gpio/at91_gpio.c
index af0978675e..0b70071871 100644
--- a/drivers/gpio/at91_gpio.c
+++ b/drivers/gpio/at91_gpio.c
@@ -11,9 +11,10 @@
 #include <config.h>
 #include <common.h>
 #include <asm/io.h>
-#include <asm/sizes.h>
+#include <linux/sizes.h>
 #include <asm/arch/hardware.h>
 #include <asm/arch/at91_pio.h>
+#include <asm/arch/gpio.h>
 
 static struct at91_port *at91_pio_get_port(unsigned port)
 {
@@ -356,9 +357,6 @@ int at91_get_pio_value(unsigned port, unsigned pin)
 
 /* Common GPIO API */
 
-#define at91_gpio_to_port(gpio)		(gpio / 32)
-#define at91_gpio_to_pin(gpio)		(gpio % 32)
-
 int gpio_request(unsigned gpio, const char *label)
 {
 	return 0;
diff --git a/drivers/gpio/gpio-uclass.c b/drivers/gpio/gpio-uclass.c
new file mode 100644
index 0000000000..56bfd11466
--- /dev/null
+++ b/drivers/gpio/gpio-uclass.c
@@ -0,0 +1,266 @@
+/*
+ * Copyright (c) 2013 Google, Inc
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <errno.h>
+#include <asm/gpio.h>
+
+/**
+ * gpio_to_device() - Convert global GPIO number to device, number
+ * gpio:	The numeric representation of the GPIO
+ *
+ * Convert the GPIO number to an entry in the list of GPIOs
+ * or GPIO blocks registered with the GPIO controller. Returns
+ * entry on success, NULL on error.
+ */
+static int gpio_to_device(unsigned int gpio, struct device **devp,
+			  unsigned int *offset)
+{
+	struct gpio_dev_priv *uc_priv;
+	struct device *dev;
+	int ret;
+
+	for (ret = uclass_first_device(UCLASS_GPIO, &dev);
+	     dev;
+	     ret = uclass_next_device(&dev)) {
+		uc_priv = dev->uclass_priv;
+		if (gpio >= uc_priv->gpio_base &&
+		    gpio < uc_priv->gpio_base + uc_priv->gpio_count) {
+			*devp = dev;
+			*offset = gpio - uc_priv->gpio_base;
+			return 0;
+		}
+	}
+
+	/* No such GPIO */
+	return ret ? ret : -EINVAL;
+}
+
+int gpio_lookup_name(const char *name, struct device **devp,
+		     unsigned int *offsetp, unsigned int *gpiop)
+{
+	struct gpio_dev_priv *uc_priv;
+	struct device *dev;
+	int ret;
+
+	if (devp)
+		*devp = NULL;
+	for (ret = uclass_first_device(UCLASS_GPIO, &dev);
+	     dev;
+	     ret = uclass_next_device(&dev)) {
+		ulong offset;
+		int len;
+
+		uc_priv = dev->uclass_priv;
+		len = uc_priv->bank_name ? strlen(uc_priv->bank_name) : 0;
+
+		if (!strncmp(name, uc_priv->bank_name, len)) {
+			if (strict_strtoul(name + len, 10, &offset))
+				continue;
+			if (devp)
+				*devp = dev;
+			if (offsetp)
+				*offsetp = offset;
+			if (gpiop)
+				*gpiop = uc_priv->gpio_base + offset;
+			return 0;
+		}
+	}
+
+	return ret ? ret : -EINVAL;
+}
+
+/**
+ * gpio_request() - [COMPAT] Request GPIO
+ * gpio:	GPIO number
+ * label:	Name for the requested GPIO
+ *
+ * This function implements the API that's compatible with current
+ * GPIO API used in U-Boot. The request is forwarded to particular
+ * GPIO driver. Returns 0 on success, negative value on error.
+ */
+int gpio_request(unsigned gpio, const char *label)
+{
+	unsigned int offset;
+	struct device *dev;
+	int ret;
+
+	ret = gpio_to_device(gpio, &dev, &offset);
+	if (ret)
+		return ret;
+
+	if (!gpio_get_ops(dev)->request)
+		return 0;
+
+	return gpio_get_ops(dev)->request(dev, offset, label);
+}
+
+/**
+ * gpio_free() - [COMPAT] Relinquish GPIO
+ * gpio:	GPIO number
+ *
+ * This function implements the API that's compatible with current
+ * GPIO API used in U-Boot. The request is forwarded to particular
+ * GPIO driver. Returns 0 on success, negative value on error.
+ */
+int gpio_free(unsigned gpio)
+{
+	unsigned int offset;
+	struct device *dev;
+	int ret;
+
+	ret = gpio_to_device(gpio, &dev, &offset);
+	if (ret)
+		return ret;
+
+	if (!gpio_get_ops(dev)->free)
+		return 0;
+	return gpio_get_ops(dev)->free(dev, offset);
+}
+
+/**
+ * gpio_direction_input() - [COMPAT] Set GPIO direction to input
+ * gpio:	GPIO number
+ *
+ * This function implements the API that's compatible with current
+ * GPIO API used in U-Boot. The request is forwarded to particular
+ * GPIO driver. Returns 0 on success, negative value on error.
+ */
+int gpio_direction_input(unsigned gpio)
+{
+	unsigned int offset;
+	struct device *dev;
+	int ret;
+
+	ret = gpio_to_device(gpio, &dev, &offset);
+	if (ret)
+		return ret;
+
+	return gpio_get_ops(dev)->direction_input(dev, offset);
+}
+
+/**
+ * gpio_direction_output() - [COMPAT] Set GPIO direction to output and set value
+ * gpio:	GPIO number
+ * value:	Logical value to be set on the GPIO pin
+ *
+ * This function implements the API that's compatible with current
+ * GPIO API used in U-Boot. The request is forwarded to particular
+ * GPIO driver. Returns 0 on success, negative value on error.
+ */
+int gpio_direction_output(unsigned gpio, int value)
+{
+	unsigned int offset;
+	struct device *dev;
+	int ret;
+
+	ret = gpio_to_device(gpio, &dev, &offset);
+	if (ret)
+		return ret;
+
+	return gpio_get_ops(dev)->direction_output(dev, offset, value);
+}
+
+/**
+ * gpio_get_value() - [COMPAT] Sample GPIO pin and return it's value
+ * gpio:	GPIO number
+ *
+ * This function implements the API that's compatible with current
+ * GPIO API used in U-Boot. The request is forwarded to particular
+ * GPIO driver. Returns the value of the GPIO pin, or negative value
+ * on error.
+ */
+int gpio_get_value(unsigned gpio)
+{
+	unsigned int offset;
+	struct device *dev;
+	int ret;
+
+	ret = gpio_to_device(gpio, &dev, &offset);
+	if (ret)
+		return ret;
+
+	return gpio_get_ops(dev)->get_value(dev, offset);
+}
+
+/**
+ * gpio_set_value() - [COMPAT] Configure logical value on GPIO pin
+ * gpio:	GPIO number
+ * value:	Logical value to be set on the GPIO pin.
+ *
+ * This function implements the API that's compatible with current
+ * GPIO API used in U-Boot. The request is forwarded to particular
+ * GPIO driver. Returns 0 on success, negative value on error.
+ */
+int gpio_set_value(unsigned gpio, int value)
+{
+	unsigned int offset;
+	struct device *dev;
+	int ret;
+
+	ret = gpio_to_device(gpio, &dev, &offset);
+	if (ret)
+		return ret;
+
+	return gpio_get_ops(dev)->set_value(dev, offset, value);
+}
+
+const char *gpio_get_bank_info(struct device *dev, int *bit_count)
+{
+	struct gpio_dev_priv *priv;
+
+	/* Must be called on an active device */
+	priv = dev->uclass_priv;
+	assert(priv);
+
+	*bit_count = priv->gpio_count;
+	return priv->bank_name;
+}
+
+/* We need to renumber the GPIOs when any driver is probed/removed */
+static int gpio_renumber(void)
+{
+	struct gpio_dev_priv *uc_priv;
+	struct device *dev;
+	struct uclass *uc;
+	unsigned base;
+	int ret;
+
+	ret = uclass_get(UCLASS_GPIO, &uc);
+	if (ret)
+		return ret;
+
+	/* Ensure that we have a base for each bank */
+	base = 0;
+	uclass_foreach_dev(dev, uc) {
+		if (device_active(dev)) {
+			uc_priv = dev->uclass_priv;
+			uc_priv->gpio_base = base;
+			base += uc_priv->gpio_count;
+		}
+	}
+
+	return 0;
+}
+
+static int gpio_post_probe(struct device *dev)
+{
+	return gpio_renumber();
+}
+
+static int gpio_pre_remove(struct device *dev)
+{
+	return gpio_renumber();
+}
+
+UCLASS_DRIVER(gpio) = {
+	.id		= UCLASS_GPIO,
+	.name		= "gpio",
+	.post_probe	= gpio_post_probe,
+	.pre_remove	= gpio_pre_remove,
+	.per_device_auto_alloc_size = sizeof(struct gpio_dev_priv),
+};
diff --git a/drivers/gpio/kona_gpio.c b/drivers/gpio/kona_gpio.c
new file mode 100644
index 0000000000..65117438c5
--- /dev/null
+++ b/drivers/gpio/kona_gpio.c
@@ -0,0 +1,141 @@
+/*
+ * Copyright 2013 Broadcom Corporation.
+ *
+ * SPDX-License-Identifier:      GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/sysmap.h>
+
+#define GPIO_BASE				(void *)GPIO2_BASE_ADDR
+
+#define GPIO_PASSWD				0x00a5a501
+#define GPIO_PER_BANK				32
+#define GPIO_MAX_BANK_NUM			8
+
+#define GPIO_BANK(gpio)				((gpio) >> 5)
+#define GPIO_BITMASK(gpio)	\
+	(1UL << ((gpio) & (GPIO_PER_BANK - 1)))
+
+#define GPIO_OUT_STATUS(bank)			(0x00000000 + ((bank) << 2))
+#define GPIO_IN_STATUS(bank)			(0x00000020 + ((bank) << 2))
+#define GPIO_OUT_SET(bank)			(0x00000040 + ((bank) << 2))
+#define GPIO_OUT_CLEAR(bank)			(0x00000060 + ((bank) << 2))
+#define GPIO_INT_STATUS(bank)			(0x00000080 + ((bank) << 2))
+#define GPIO_INT_MASK(bank)			(0x000000a0 + ((bank) << 2))
+#define GPIO_INT_MSKCLR(bank)			(0x000000c0 + ((bank) << 2))
+#define GPIO_CONTROL(bank)			(0x00000100 + ((bank) << 2))
+#define GPIO_PWD_STATUS(bank)			(0x00000500 + ((bank) << 2))
+
+#define GPIO_GPPWR_OFFSET			0x00000520
+
+#define GPIO_GPCTR0_DBR_SHIFT			5
+#define GPIO_GPCTR0_DBR_MASK			0x000001e0
+
+#define GPIO_GPCTR0_ITR_SHIFT			3
+#define GPIO_GPCTR0_ITR_MASK			0x00000018
+#define GPIO_GPCTR0_ITR_CMD_RISING_EDGE		0x00000001
+#define GPIO_GPCTR0_ITR_CMD_FALLING_EDGE	0x00000002
+#define GPIO_GPCTR0_ITR_CMD_BOTH_EDGE		0x00000003
+
+#define GPIO_GPCTR0_IOTR_MASK			0x00000001
+#define GPIO_GPCTR0_IOTR_CMD_0UTPUT		0x00000000
+#define GPIO_GPCTR0_IOTR_CMD_INPUT		0x00000001
+
+int gpio_request(unsigned gpio, const char *label)
+{
+	unsigned int value, off;
+
+	writel(GPIO_PASSWD, GPIO_BASE + GPIO_GPPWR_OFFSET);
+	off = GPIO_PWD_STATUS(GPIO_BANK(gpio));
+	value = readl(GPIO_BASE + off) & ~GPIO_BITMASK(gpio);
+	writel(value, GPIO_BASE + off);
+
+	return 0;
+}
+
+int gpio_free(unsigned gpio)
+{
+	unsigned int value, off;
+
+	writel(GPIO_PASSWD, GPIO_BASE + GPIO_GPPWR_OFFSET);
+	off = GPIO_PWD_STATUS(GPIO_BANK(gpio));
+	value = readl(GPIO_BASE + off) | GPIO_BITMASK(gpio);
+	writel(value, GPIO_BASE + off);
+
+	return 0;
+}
+
+int gpio_direction_input(unsigned gpio)
+{
+	u32 val;
+
+	val = readl(GPIO_BASE + GPIO_CONTROL(gpio));
+	val &= ~GPIO_GPCTR0_IOTR_MASK;
+	val |= GPIO_GPCTR0_IOTR_CMD_INPUT;
+	writel(val, GPIO_BASE + GPIO_CONTROL(gpio));
+
+	return 0;
+}
+
+int gpio_direction_output(unsigned gpio, int value)
+{
+	int bank_id = GPIO_BANK(gpio);
+	int bitmask = GPIO_BITMASK(gpio);
+	u32 val, off;
+
+	val = readl(GPIO_BASE + GPIO_CONTROL(gpio));
+	val &= ~GPIO_GPCTR0_IOTR_MASK;
+	val |= GPIO_GPCTR0_IOTR_CMD_0UTPUT;
+	writel(val, GPIO_BASE + GPIO_CONTROL(gpio));
+	off = value ? GPIO_OUT_SET(bank_id) : GPIO_OUT_CLEAR(bank_id);
+
+	val = readl(GPIO_BASE + off);
+	val |= bitmask;
+	writel(val, GPIO_BASE + off);
+
+	return 0;
+}
+
+int gpio_get_value(unsigned gpio)
+{
+	int bank_id = GPIO_BANK(gpio);
+	int bitmask = GPIO_BITMASK(gpio);
+	u32 val, off;
+
+	/* determine the GPIO pin direction */
+	val = readl(GPIO_BASE + GPIO_CONTROL(gpio));
+	val &= GPIO_GPCTR0_IOTR_MASK;
+
+	/* read the GPIO bank status */
+	off = (GPIO_GPCTR0_IOTR_CMD_INPUT == val) ?
+	    GPIO_IN_STATUS(bank_id) : GPIO_OUT_STATUS(bank_id);
+	val = readl(GPIO_BASE + off);
+
+	/* return the specified bit status */
+	return !!(val & bitmask);
+}
+
+void gpio_set_value(unsigned gpio, int value)
+{
+	int bank_id = GPIO_BANK(gpio);
+	int bitmask = GPIO_BITMASK(gpio);
+	u32 val, off;
+
+	/* determine the GPIO pin direction */
+	val = readl(GPIO_BASE + GPIO_CONTROL(gpio));
+	val &= GPIO_GPCTR0_IOTR_MASK;
+
+	/* this function only applies to output pin */
+	if (GPIO_GPCTR0_IOTR_CMD_INPUT == val) {
+		printf("%s: Cannot set an input pin %d\n", __func__, gpio);
+		return;
+	}
+
+	off = value ? GPIO_OUT_SET(bank_id) : GPIO_OUT_CLEAR(bank_id);
+
+	val = readl(GPIO_BASE + off);
+	val |= bitmask;
+	writel(val, GPIO_BASE + off);
+}
diff --git a/drivers/gpio/mxs_gpio.c b/drivers/gpio/mxs_gpio.c
index d9a7a3aaf6..da0199b168 100644
--- a/drivers/gpio/mxs_gpio.c
+++ b/drivers/gpio/mxs_gpio.c
@@ -95,10 +95,10 @@ int gpio_direction_output(unsigned gpio, int value)
 	struct mxs_register_32 *reg =
 		(struct mxs_register_32 *)(MXS_PINCTRL_BASE + offset);
 
-	writel(1 << PAD_PIN(gpio), &reg->reg_set);
-
 	gpio_set_value(gpio, value);
 
+	writel(1 << PAD_PIN(gpio), &reg->reg_set);
+
 	return 0;
 }
 
diff --git a/drivers/gpio/s5p_gpio.c b/drivers/gpio/s5p_gpio.c
index 7eeb96d19f..11a0472c69 100644
--- a/drivers/gpio/s5p_gpio.c
+++ b/drivers/gpio/s5p_gpio.c
@@ -9,6 +9,11 @@
 #include <asm/io.h>
 #include <asm/gpio.h>
 
+#define S5P_GPIO_GET_BANK(x)	((x >> S5P_GPIO_BANK_SHIFT) \
+				& S5P_GPIO_BANK_MASK)
+
+#define S5P_GPIO_GET_PIN(x)	(x & S5P_GPIO_PIN_MASK)
+
 #define CON_MASK(x)		(0xf << ((x) << 2))
 #define CON_SFR(x, v)		((v) << ((x) << 2))
 
@@ -124,17 +129,15 @@ void s5p_gpio_set_rate(struct s5p_gpio_bank *bank, int gpio, int mode)
 
 struct s5p_gpio_bank *s5p_gpio_get_bank(unsigned gpio)
 {
-	int bank;
-	unsigned g = gpio - s5p_gpio_part_max(gpio);
+	unsigned bank = S5P_GPIO_GET_BANK(gpio);
+	unsigned base = s5p_gpio_base(gpio);
 
-	bank = g / GPIO_PER_BANK;
-	bank *= sizeof(struct s5p_gpio_bank);
-	return (struct s5p_gpio_bank *) (s5p_gpio_base(gpio) + bank);
+	return (struct s5p_gpio_bank *)(base + bank);
 }
 
 int s5p_gpio_get_pin(unsigned gpio)
 {
-	return gpio % GPIO_PER_BANK;
+	return S5P_GPIO_GET_PIN(gpio);
 }
 
 /* Common GPIO API */
diff --git a/drivers/gpio/sandbox.c b/drivers/gpio/sandbox.c
index 3c6cfec179..22b6a5f794 100644
--- a/drivers/gpio/sandbox.c
+++ b/drivers/gpio/sandbox.c
@@ -4,8 +4,13 @@
  */
 
 #include <common.h>
+#include <dm.h>
+#include <fdtdec.h>
+#include <malloc.h>
 #include <asm/gpio.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 /* Flags for each GPIO */
 #define GPIOF_OUTPUT	(1 << 0)	/* Currently set as an output */
 #define GPIOF_HIGH	(1 << 1)	/* Currently set high */
@@ -16,34 +21,30 @@ struct gpio_state {
 	u8 flags;		/* flags (GPIOF_...) */
 };
 
-/*
- * State of GPIOs
- * TODO: Put this into sandbox state
- */
-static struct gpio_state state[CONFIG_SANDBOX_GPIO_COUNT];
-
 /* Access routines for GPIO state */
-static u8 *get_gpio_flags(unsigned gp)
+static u8 *get_gpio_flags(struct device *dev, unsigned offset)
 {
-	/* assert()'s could be disabled, so make sure we handle that */
-	assert(gp < ARRAY_SIZE(state));
-	if (gp >= ARRAY_SIZE(state)) {
+	struct gpio_dev_priv *uc_priv = dev->uclass_priv;
+	struct gpio_state *state = dev_get_priv(dev);
+
+	if (offset >= uc_priv->gpio_count) {
 		static u8 invalid_flags;
-		printf("sandbox_gpio: error: invalid gpio %u\n", gp);
+		printf("sandbox_gpio: error: invalid gpio %u\n", offset);
 		return &invalid_flags;
 	}
 
-	return &state[gp].flags;
+	return &state[offset].flags;
 }
 
-static int get_gpio_flag(unsigned gp, int flag)
+static int get_gpio_flag(struct device *dev, unsigned offset, int flag)
 {
-	return (*get_gpio_flags(gp) & flag) != 0;
+	return (*get_gpio_flags(dev, offset) & flag) != 0;
 }
 
-static int set_gpio_flag(unsigned gp, int flag, int value)
+static int set_gpio_flag(struct device *dev, unsigned offset, int flag,
+			 int value)
 {
-	u8 *gpio = get_gpio_flags(gp);
+	u8 *gpio = get_gpio_flags(dev, offset);
 
 	if (value)
 		*gpio |= flag;
@@ -53,11 +54,12 @@ static int set_gpio_flag(unsigned gp, int flag, int value)
 	return 0;
 }
 
-static int check_reserved(unsigned gpio, const char *func)
+static int check_reserved(struct device *dev, unsigned offset,
+			  const char *func)
 {
-	if (!get_gpio_flag(gpio, GPIOF_RESERVED)) {
-		printf("sandbox_gpio: %s: error: gpio %u not reserved\n",
-			func, gpio);
+	if (!get_gpio_flag(dev, offset, GPIOF_RESERVED)) {
+		printf("sandbox_gpio: %s: error: offset %u not reserved\n",
+		       func, offset);
 		return -1;
 	}
 
@@ -68,126 +70,185 @@ static int check_reserved(unsigned gpio, const char *func)
  * Back-channel sandbox-internal-only access to GPIO state
  */
 
-int sandbox_gpio_get_value(unsigned gp)
+int sandbox_gpio_get_value(struct device *dev, unsigned offset)
 {
-	if (get_gpio_flag(gp, GPIOF_OUTPUT))
-		debug("sandbox_gpio: get_value on output gpio %u\n", gp);
-	return get_gpio_flag(gp, GPIOF_HIGH);
+	if (get_gpio_flag(dev, offset, GPIOF_OUTPUT))
+		debug("sandbox_gpio: get_value on output gpio %u\n", offset);
+	return get_gpio_flag(dev, offset, GPIOF_HIGH);
 }
 
-int sandbox_gpio_set_value(unsigned gp, int value)
+int sandbox_gpio_set_value(struct device *dev, unsigned offset, int value)
 {
-	return set_gpio_flag(gp, GPIOF_HIGH, value);
+	return set_gpio_flag(dev, offset, GPIOF_HIGH, value);
 }
 
-int sandbox_gpio_get_direction(unsigned gp)
+int sandbox_gpio_get_direction(struct device *dev, unsigned offset)
 {
-	return get_gpio_flag(gp, GPIOF_OUTPUT);
+	return get_gpio_flag(dev, offset, GPIOF_OUTPUT);
 }
 
-int sandbox_gpio_set_direction(unsigned gp, int output)
+int sandbox_gpio_set_direction(struct device *dev, unsigned offset, int output)
 {
-	return set_gpio_flag(gp, GPIOF_OUTPUT, output);
+	return set_gpio_flag(dev, offset, GPIOF_OUTPUT, output);
 }
 
 /*
  * These functions implement the public interface within U-Boot
  */
 
-/* set GPIO port 'gp' as an input */
-int gpio_direction_input(unsigned gp)
+/* set GPIO port 'offset' as an input */
+static int sb_gpio_direction_input(struct device *dev, unsigned offset)
 {
-	debug("%s: gp:%u\n", __func__, gp);
+	debug("%s: offset:%u\n", __func__, offset);
 
-	if (check_reserved(gp, __func__))
+	if (check_reserved(dev, offset, __func__))
 		return -1;
 
-	return sandbox_gpio_set_direction(gp, 0);
+	return sandbox_gpio_set_direction(dev, offset, 0);
 }
 
-/* set GPIO port 'gp' as an output, with polarity 'value' */
-int gpio_direction_output(unsigned gp, int value)
+/* set GPIO port 'offset' as an output, with polarity 'value' */
+static int sb_gpio_direction_output(struct device *dev, unsigned offset,
+				    int value)
 {
-	debug("%s: gp:%u, value = %d\n", __func__, gp, value);
+	debug("%s: offset:%u, value = %d\n", __func__, offset, value);
 
-	if (check_reserved(gp, __func__))
+	if (check_reserved(dev, offset, __func__))
 		return -1;
 
-	return sandbox_gpio_set_direction(gp, 1) |
-		sandbox_gpio_set_value(gp, value);
+	return sandbox_gpio_set_direction(dev, offset, 1) |
+		sandbox_gpio_set_value(dev, offset, value);
 }
 
-/* read GPIO IN value of port 'gp' */
-int gpio_get_value(unsigned gp)
+/* read GPIO IN value of port 'offset' */
+static int sb_gpio_get_value(struct device *dev, unsigned offset)
 {
-	debug("%s: gp:%u\n", __func__, gp);
+	debug("%s: offset:%u\n", __func__, offset);
 
-	if (check_reserved(gp, __func__))
+	if (check_reserved(dev, offset, __func__))
 		return -1;
 
-	return sandbox_gpio_get_value(gp);
+	return sandbox_gpio_get_value(dev, offset);
 }
 
-/* write GPIO OUT value to port 'gp' */
-int gpio_set_value(unsigned gp, int value)
+/* write GPIO OUT value to port 'offset' */
+static int sb_gpio_set_value(struct device *dev, unsigned offset, int value)
 {
-	debug("%s: gp:%u, value = %d\n", __func__, gp, value);
+	debug("%s: offset:%u, value = %d\n", __func__, offset, value);
 
-	if (check_reserved(gp, __func__))
+	if (check_reserved(dev, offset, __func__))
 		return -1;
 
-	if (!sandbox_gpio_get_direction(gp)) {
-		printf("sandbox_gpio: error: set_value on input gpio %u\n", gp);
+	if (!sandbox_gpio_get_direction(dev, offset)) {
+		printf("sandbox_gpio: error: set_value on input gpio %u\n",
+		       offset);
 		return -1;
 	}
 
-	return sandbox_gpio_set_value(gp, value);
+	return sandbox_gpio_set_value(dev, offset, value);
 }
 
-int gpio_request(unsigned gp, const char *label)
+static int sb_gpio_request(struct device *dev, unsigned offset,
+			   const char *label)
 {
-	debug("%s: gp:%u, label:%s\n", __func__, gp, label);
+	struct gpio_dev_priv *uc_priv = dev->uclass_priv;
+	struct gpio_state *state = dev_get_priv(dev);
+
+	debug("%s: offset:%u, label:%s\n", __func__, offset, label);
 
-	if (gp >= ARRAY_SIZE(state)) {
-		printf("sandbox_gpio: error: invalid gpio %u\n", gp);
+	if (offset >= uc_priv->gpio_count) {
+		printf("sandbox_gpio: error: invalid gpio %u\n", offset);
 		return -1;
 	}
 
-	if (get_gpio_flag(gp, GPIOF_RESERVED)) {
-		printf("sandbox_gpio: error: gpio %u already reserved\n", gp);
+	if (get_gpio_flag(dev, offset, GPIOF_RESERVED)) {
+		printf("sandbox_gpio: error: gpio %u already reserved\n",
+		       offset);
 		return -1;
 	}
 
-	state[gp].label = label;
-	return set_gpio_flag(gp, GPIOF_RESERVED, 1);
+	state[offset].label = label;
+	return set_gpio_flag(dev, offset, GPIOF_RESERVED, 1);
 }
 
-int gpio_free(unsigned gp)
+static int sb_gpio_free(struct device *dev, unsigned offset)
 {
-	debug("%s: gp:%u\n", __func__, gp);
+	struct gpio_state *state = dev_get_priv(dev);
+
+	debug("%s: offset:%u\n", __func__, offset);
 
-	if (check_reserved(gp, __func__))
+	if (check_reserved(dev, offset, __func__))
 		return -1;
 
-	state[gp].label = NULL;
-	return set_gpio_flag(gp, GPIOF_RESERVED, 0);
+	state[offset].label = NULL;
+	return set_gpio_flag(dev, offset, GPIOF_RESERVED, 0);
 }
 
-/* Display GPIO information */
-void gpio_info(void)
+static int sb_gpio_get_state(struct device *dev, unsigned int offset,
+			     char *buf, int bufsize)
 {
-	unsigned gpio;
+	struct gpio_dev_priv *uc_priv = dev->uclass_priv;
+	struct gpio_state *state = dev_get_priv(dev);
+	const char *label;
+
+	label = state[offset].label;
+	snprintf(buf, bufsize, "%s%d: %s: %d [%c]%s%s",
+		 uc_priv->bank_name ? uc_priv->bank_name : "", offset,
+		 sandbox_gpio_get_direction(dev, offset) ? "out" : " in",
+		 sandbox_gpio_get_value(dev, offset),
+		 get_gpio_flag(dev, offset, GPIOF_RESERVED) ? 'x' : ' ',
+		 label ? " " : "",
+		 label ? label : "");
 
-	puts("Sandbox GPIOs\n");
+	return 0;
+}
+
+static const struct dm_gpio_ops gpio_sandbox_ops = {
+	.request		= sb_gpio_request,
+	.free			= sb_gpio_free,
+	.direction_input	= sb_gpio_direction_input,
+	.direction_output	= sb_gpio_direction_output,
+	.get_value		= sb_gpio_get_value,
+	.set_value		= sb_gpio_set_value,
+	.get_state		= sb_gpio_get_state,
+};
+
+static int sandbox_gpio_ofdata_to_platdata(struct device *dev)
+{
+	struct gpio_dev_priv *uc_priv = dev->uclass_priv;
 
-	for (gpio = 0; gpio < ARRAY_SIZE(state); ++gpio) {
-		const char *label = state[gpio].label;
+	uc_priv->gpio_count = fdtdec_get_int(gd->fdt_blob, dev->of_offset,
+					     "num-gpios", 0);
+	uc_priv->bank_name = fdt_getprop(gd->fdt_blob, dev->of_offset,
+					 "gpio-bank-name", NULL);
 
-		printf("%4d: %s: %d [%c] %s\n",
-			gpio,
-			sandbox_gpio_get_direction(gpio) ? "out" : " in",
-			sandbox_gpio_get_value(gpio),
-			get_gpio_flag(gpio, GPIOF_RESERVED) ? 'x' : ' ',
-			label ? label : "");
+	return 0;
+}
+
+static int gpio_sandbox_probe(struct device *dev)
+{
+	struct gpio_dev_priv *uc_priv = dev->uclass_priv;
+
+	if (dev->of_offset == -1) {
+		/* Tell the uclass how many GPIOs we have */
+		uc_priv->gpio_count = CONFIG_SANDBOX_GPIO_COUNT;
 	}
+
+	dev->priv = calloc(sizeof(struct gpio_state), uc_priv->gpio_count);
+
+	return 0;
 }
+
+static const struct device_id sandbox_gpio_ids[] = {
+	{ .compatible = "sandbox,gpio" },
+	{ }
+};
+
+U_BOOT_DRIVER(gpio_sandbox) = {
+	.name	= "gpio_sandbox",
+	.id	= UCLASS_GPIO,
+	.of_match = sandbox_gpio_ids,
+	.ofdata_to_platdata = sandbox_gpio_ofdata_to_platdata,
+	.probe	= gpio_sandbox_probe,
+	.ops	= &gpio_sandbox_ops,
+};
diff --git a/drivers/gpio/sx151x.c b/drivers/gpio/sx151x.c
new file mode 100644
index 0000000000..167cf40c71
--- /dev/null
+++ b/drivers/gpio/sx151x.c
@@ -0,0 +1,242 @@
+/*
+ * (C) Copyright 2013
+ * Viktar Palstsiuk, Promwad, viktar.palstsiuk@promwad.com
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * Driver for Semtech SX151x SPI GPIO Expanders
+ */
+
+#include <common.h>
+#include <spi.h>
+#include <sx151x.h>
+
+#ifndef CONFIG_SX151X_SPI_BUS
+#define CONFIG_SX151X_SPI_BUS 0
+#endif
+
+/*
+ * The SX151x registers
+ */
+
+#ifdef CONFIG_SX151X_GPIO_COUNT_8
+/* 8bit: SX1511 */
+#define SX151X_REG_DIR		0x07
+#define SX151X_REG_DATA		0x08
+#else
+/* 16bit: SX1512 */
+#define SX151X_REG_DIR		0x0F
+#define SX151X_REG_DATA		0x11
+#endif
+#define SX151X_REG_RESET	0x7D
+
+static int sx151x_spi_write(int chip, unsigned char reg, unsigned char val)
+{
+	struct spi_slave *slave;
+	unsigned char buf[2];
+	int ret;
+
+	slave = spi_setup_slave(CONFIG_SX151X_SPI_BUS, chip, 1000000,
+				SPI_MODE_0);
+	if (!slave)
+		return 0;
+
+	spi_claim_bus(slave);
+
+	buf[0] = reg;
+	buf[1] = val;
+
+	ret = spi_xfer(slave, 16, buf, NULL, SPI_XFER_BEGIN | SPI_XFER_END);
+	if (ret < 0)
+		printf("spi%d.%d write fail: can't write %02x to %02x: %d\n",
+			CONFIG_SX151X_SPI_BUS, chip, val, reg, ret);
+	else
+		printf("spi%d.%d write 0x%02x to register 0x%02x\n",
+		       CONFIG_SX151X_SPI_BUS, chip, val, reg);
+	spi_release_bus(slave);
+	spi_free_slave(slave);
+
+	return ret;
+}
+
+static int sx151x_spi_read(int chip, unsigned char reg)
+{
+	struct spi_slave *slave;
+	int ret;
+
+	slave = spi_setup_slave(CONFIG_SX151X_SPI_BUS, chip, 1000000,
+				SPI_MODE_0);
+	if (!slave)
+		return 0;
+
+	spi_claim_bus(slave);
+
+	ret = spi_w8r8(slave, reg | 0x80);
+	if (ret < 0)
+		printf("spi%d.%d read fail: can't read %02x: %d\n",
+			CONFIG_SX151X_SPI_BUS, chip, reg, ret);
+	else
+		printf("spi%d.%d read register 0x%02x: 0x%02x\n",
+		       CONFIG_SX151X_SPI_BUS, chip, reg, ret);
+
+	spi_release_bus(slave);
+	spi_free_slave(slave);
+
+	return ret;
+}
+
+static inline void sx151x_find_cfg(int gpio, unsigned char *reg, unsigned char *mask)
+{
+	*reg   -= gpio / 8;
+	*mask   = 1 << (gpio % 8);
+}
+
+static int sx151x_write_cfg(int chip, unsigned char gpio, unsigned char reg, int val)
+{
+	unsigned char  mask;
+	unsigned char  data;
+	int ret;
+
+	sx151x_find_cfg(gpio, &reg, &mask);
+	ret = sx151x_spi_read(chip, reg);
+	if (ret < 0)
+		return ret;
+	else
+		data = ret;
+	data &= ~mask;
+	data |= (val << (gpio % 8)) & mask;
+	return sx151x_spi_write(chip, reg, data);
+}
+
+int sx151x_get_value(int chip, int gpio)
+{
+	unsigned char  reg = SX151X_REG_DATA;
+	unsigned char  mask;
+	int ret;
+
+	sx151x_find_cfg(gpio, &reg, &mask);
+	ret = sx151x_spi_read(chip, reg);
+	if (ret >= 0)
+		ret = (ret & mask) != 0 ? 1 : 0;
+
+	return ret;
+}
+
+int sx151x_set_value(int chip, int gpio, int val)
+{
+	return sx151x_write_cfg(chip, gpio, SX151X_REG_DATA, (val ? 1 : 0));
+}
+
+int sx151x_direction_input(int chip, int gpio)
+{
+	return sx151x_write_cfg(chip, gpio, SX151X_REG_DIR, 1);
+}
+
+int sx151x_direction_output(int chip, int gpio)
+{
+	return sx151x_write_cfg(chip, gpio, SX151X_REG_DIR, 0);
+}
+
+int sx151x_reset(int chip)
+{
+	int err;
+
+	err = sx151x_spi_write(chip, SX151X_REG_RESET, 0x12);
+	if (err < 0)
+		return err;
+
+	err = sx151x_spi_write(chip, SX151X_REG_RESET, 0x34);
+	return err;
+}
+
+#ifdef CONFIG_CMD_SX151X
+
+int do_sx151x(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	int ret = CMD_RET_USAGE, chip = 0, gpio = 0, val = 0;
+
+	if (argc < 3)
+		return CMD_RET_USAGE;
+
+	/* arg2 used as chip number */
+	chip = simple_strtoul(argv[2], NULL, 10);
+
+	if (strcmp(argv[1], "reset") == 0) {
+		ret = sx151x_reset(chip);
+		if (!ret) {
+			printf("Device at spi%d.%d was reset\n",
+			       CONFIG_SX151X_SPI_BUS, chip);
+		}
+		return ret;
+	}
+
+	if (argc < 4)
+		return CMD_RET_USAGE;
+
+	/* arg3 used as gpio number */
+	gpio = simple_strtoul(argv[3], NULL, 10);
+
+	if (strcmp(argv[1], "get") == 0) {
+		ret = sx151x_get_value(chip, gpio);
+		if (ret < 0)
+			printf("Failed to get value at spi%d.%d gpio %d\n",
+			       CONFIG_SX151X_SPI_BUS, chip, gpio);
+		else {
+			printf("Value at spi%d.%d gpio %d is %d\n",
+			       CONFIG_SX151X_SPI_BUS, chip, gpio, ret);
+			ret = 0;
+		}
+		return ret;
+	}
+
+	if (argc < 5)
+		return CMD_RET_USAGE;
+
+	/* arg4 used as value or direction */
+	val = simple_strtoul(argv[4], NULL, 10);
+
+	if (strcmp(argv[1], "set") == 0) {
+		ret = sx151x_set_value(chip, gpio, val);
+		if (ret < 0)
+			printf("Failed to set value at spi%d.%d gpio %d\n",
+			       CONFIG_SX151X_SPI_BUS, chip, gpio);
+		else
+			printf("New value at spi%d.%d gpio %d is %d\n",
+			       CONFIG_SX151X_SPI_BUS, chip, gpio, val);
+		return ret;
+	} else if (strcmp(argv[1], "dir") == 0) {
+		if (val == 0)
+			ret = sx151x_direction_output(chip, gpio);
+		else
+			ret = sx151x_direction_input(chip, gpio);
+
+		if (ret < 0)
+			printf("Failed to set direction of spi%d.%d gpio %d\n",
+			       CONFIG_SX151X_SPI_BUS, chip, gpio);
+		else
+			printf("New direction of spi%d.%d gpio %d is %d\n",
+			       CONFIG_SX151X_SPI_BUS, chip, gpio, val);
+		return ret;
+	}
+
+	printf("Please see usage\n");
+
+	return ret;
+}
+
+U_BOOT_CMD(
+	sx151x,	5,	1,	do_sx151x,
+	"sx151x gpio access",
+	"dir chip gpio 0|1\n"
+	"	- set gpio direction (0 for output, 1 for input)\n"
+	"sx151x get chip gpio\n"
+	"	- get gpio value\n"
+	"sx151x set chip gpio 0|1\n"
+	"	- set gpio value\n"
+	"sx151x reset chip\n"
+	"	- reset chip"
+);
+
+#endif /* CONFIG_CMD_SX151X */
diff --git a/drivers/hwmon/Makefile b/drivers/hwmon/Makefile
index 6e203a34a2..25b8e8a2d7 100644
--- a/drivers/hwmon/Makefile
+++ b/drivers/hwmon/Makefile
@@ -8,36 +8,14 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-#CFLAGS += -DDEBUG
-
-LIB	= $(obj)libhwmon.o
-
-COBJS-$(CONFIG_DTT_ADM1021) += adm1021.o
-COBJS-$(CONFIG_DTT_ADT7460) += adt7460.o
-COBJS-$(CONFIG_DTT_DS1621) += ds1621.o
-COBJS-$(CONFIG_DTT_DS1722) += ds1722.o
-COBJS-$(CONFIG_DTT_DS1775) += ds1775.o
-COBJS-$(CONFIG_DTT_LM63) += lm63.o
-COBJS-$(CONFIG_DTT_LM73) += lm73.o
-COBJS-$(CONFIG_DTT_LM75) += lm75.o
-COBJS-$(CONFIG_DTT_LM81) += lm81.o
-
-COBJS	:= $(COBJS-y)
-SRCS	:= $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-
-all:	$(LIB)
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+#ccflags-y += -DDEBUG
+
+obj-$(CONFIG_DTT_ADM1021) += adm1021.o
+obj-$(CONFIG_DTT_ADT7460) += adt7460.o
+obj-$(CONFIG_DTT_DS1621) += ds1621.o
+obj-$(CONFIG_DTT_DS1722) += ds1722.o
+obj-$(CONFIG_DTT_DS1775) += ds1775.o
+obj-$(CONFIG_DTT_LM63) += lm63.o
+obj-$(CONFIG_DTT_LM73) += lm73.o
+obj-$(CONFIG_DTT_LM75) += lm75.o
+obj-$(CONFIG_DTT_LM81) += lm81.o
diff --git a/drivers/hwmon/ds1722.c b/drivers/hwmon/ds1722.c
index a46cd4dfb5..c46958846c 100644
--- a/drivers/hwmon/ds1722.c
+++ b/drivers/hwmon/ds1722.c
@@ -1,4 +1,3 @@
-
 #include <common.h>
 #include <asm/ic/ssi.h>
 #include <ds1722.h>
diff --git a/drivers/i2c/Makefile b/drivers/i2c/Makefile
index df3092eaf0..36d5e5f1a2 100644
--- a/drivers/i2c/Makefile
+++ b/drivers/i2c/Makefile
@@ -5,48 +5,27 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	:= $(obj)libi2c.o
-
-COBJS-$(CONFIG_BFIN_TWI_I2C) += bfin-twi_i2c.o
-COBJS-$(CONFIG_DRIVER_DAVINCI_I2C) += davinci_i2c.o
-COBJS-$(CONFIG_DW_I2C) += designware_i2c.o
-COBJS-$(CONFIG_I2C_MVTWSI) += mvtwsi.o
-COBJS-$(CONFIG_I2C_MV) += mv_i2c.o
-COBJS-$(CONFIG_I2C_MXC) += mxc_i2c.o
-COBJS-$(CONFIG_I2C_MXS) += mxs_i2c.o
-COBJS-$(CONFIG_DRIVER_OMAP1510_I2C) += omap1510_i2c.o
-COBJS-$(CONFIG_DRIVER_OMAP24XX_I2C) += omap24xx_i2c.o
-COBJS-$(CONFIG_DRIVER_OMAP34XX_I2C) += omap24xx_i2c.o
-COBJS-$(CONFIG_PCA9564_I2C) += pca9564_i2c.o
-COBJS-$(CONFIG_DRIVER_S3C24X0_I2C) += s3c24x0_i2c.o
-COBJS-$(CONFIG_TSI108_I2C) += tsi108_i2c.o
-COBJS-$(CONFIG_U8500_I2C) += u8500_i2c.o
-COBJS-$(CONFIG_SH_I2C) += sh_i2c.o
-COBJS-$(CONFIG_SH_SH7734_I2C) += sh_sh7734_i2c.o
-COBJS-$(CONFIG_SYS_I2C) += i2c_core.o
-COBJS-$(CONFIG_SYS_I2C_FSL) += fsl_i2c.o
-COBJS-$(CONFIG_SYS_I2C_FTI2C010) += fti2c010.o
-COBJS-$(CONFIG_SYS_I2C_PPC4XX) += ppc4xx_i2c.o
-COBJS-$(CONFIG_SYS_I2C_SOFT) += soft_i2c.o
-COBJS-$(CONFIG_SYS_I2C_TEGRA) += tegra_i2c.o
-COBJS-$(CONFIG_ZYNQ_I2C) += zynq_i2c.o
-
-COBJS	:= $(COBJS-y)
-SRCS	:= $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-
-all:	$(LIB)
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-$(CONFIG_BFIN_TWI_I2C) += bfin-twi_i2c.o
+obj-$(CONFIG_DRIVER_DAVINCI_I2C) += davinci_i2c.o
+obj-$(CONFIG_DW_I2C) += designware_i2c.o
+obj-$(CONFIG_I2C_MVTWSI) += mvtwsi.o
+obj-$(CONFIG_I2C_MV) += mv_i2c.o
+obj-$(CONFIG_I2C_MXS) += mxs_i2c.o
+obj-$(CONFIG_PCA9564_I2C) += pca9564_i2c.o
+obj-$(CONFIG_TSI108_I2C) += tsi108_i2c.o
+obj-$(CONFIG_U8500_I2C) += u8500_i2c.o
+obj-$(CONFIG_SH_SH7734_I2C) += sh_sh7734_i2c.o
+obj-$(CONFIG_SYS_I2C) += i2c_core.o
+obj-$(CONFIG_SYS_I2C_FSL) += fsl_i2c.o
+obj-$(CONFIG_SYS_I2C_FTI2C010) += fti2c010.o
+obj-$(CONFIG_SYS_I2C_KONA) += kona_i2c.o
+obj-$(CONFIG_SYS_I2C_MXC) += mxc_i2c.o
+obj-$(CONFIG_SYS_I2C_OMAP24XX) += omap24xx_i2c.o
+obj-$(CONFIG_SYS_I2C_OMAP34XX) += omap24xx_i2c.o
+obj-$(CONFIG_SYS_I2C_PPC4XX) += ppc4xx_i2c.o
+obj-$(CONFIG_SYS_I2C_RCAR) += rcar_i2c.o
+obj-$(CONFIG_SYS_I2C_S3C24X0) += s3c24x0_i2c.o
+obj-$(CONFIG_SYS_I2C_SH) += sh_i2c.o
+obj-$(CONFIG_SYS_I2C_SOFT) += soft_i2c.o
+obj-$(CONFIG_SYS_I2C_TEGRA) += tegra_i2c.o
+obj-$(CONFIG_SYS_I2C_ZYNQ) += zynq_i2c.o
diff --git a/drivers/i2c/bfin-twi_i2c.c b/drivers/i2c/bfin-twi_i2c.c
index b3a04d3207..cfab064dfa 100644
--- a/drivers/i2c/bfin-twi_i2c.c
+++ b/drivers/i2c/bfin-twi_i2c.c
@@ -10,6 +10,7 @@
 #include <i2c.h>
 
 #include <asm/blackfin.h>
+#include <asm/clock.h>
 #include <asm/mach-common/bits/twi.h>
 
 /* Every register is 32bit aligned, but only 16bits in size */
@@ -274,7 +275,7 @@ unsigned int i2c_get_bus_speed(void)
  */
 void i2c_init(int speed, int slaveaddr)
 {
-	uint8_t prescale = ((get_sclk() / 1024 / 1024 + 5) / 10) & 0x7F;
+	uint8_t prescale = ((get_i2c_clk() / 1000 / 1000 + 5) / 10) & 0x7F;
 
 	/* Set TWI internal clock as 10MHz */
 	twi->control = prescale;
diff --git a/drivers/i2c/designware_i2c.c b/drivers/i2c/designware_i2c.c
index c2f06627d3..c891ebd39e 100644
--- a/drivers/i2c/designware_i2c.c
+++ b/drivers/i2c/designware_i2c.c
@@ -7,7 +7,6 @@
 
 #include <common.h>
 #include <asm/io.h>
-#include <asm/arch/hardware.h>
 #include "designware_i2c.h"
 
 #ifdef CONFIG_I2C_MULTI_BUS
@@ -151,7 +150,19 @@ void i2c_init(int speed, int slaveadd)
  */
 static void i2c_setaddress(unsigned int i2c_addr)
 {
+	unsigned int enbl;
+
+	/* Disable i2c */
+	enbl = readl(&i2c_regs_p->ic_enable);
+	enbl &= ~IC_ENABLE_0B;
+	writel(enbl, &i2c_regs_p->ic_enable);
+
 	writel(i2c_addr, &i2c_regs_p->ic_tar);
+
+	/* Enable i2c */
+	enbl = readl(&i2c_regs_p->ic_enable);
+	enbl |= IC_ENABLE_0B;
+	writel(enbl, &i2c_regs_p->ic_enable);
 }
 
 /*
@@ -185,35 +196,18 @@ static int i2c_wait_for_bb(void)
 	return 0;
 }
 
-/* check parameters for i2c_read and i2c_write */
-static int check_params(uint addr, int alen, uchar *buffer, int len)
-{
-	if (buffer == NULL) {
-		printf("Buffer is invalid\n");
-		return 1;
-	}
-
-	if (alen > 1) {
-		printf("addr len %d not supported\n", alen);
-		return 1;
-	}
-
-	if (addr + len > 256) {
-		printf("address out of range\n");
-		return 1;
-	}
-
-	return 0;
-}
-
-static int i2c_xfer_init(uchar chip, uint addr)
+static int i2c_xfer_init(uchar chip, uint addr, int alen)
 {
 	if (i2c_wait_for_bb())
 		return 1;
 
 	i2c_setaddress(chip);
-	writel(addr, &i2c_regs_p->ic_cmd_data);
-
+	while (alen) {
+		alen--;
+		/* high byte address going out first */
+		writel((addr >> (alen * 8)) & 0xff,
+		       &i2c_regs_p->ic_cmd_data);
+	}
 	return 0;
 }
 
@@ -237,9 +231,6 @@ static int i2c_xfer_finish(void)
 
 	i2c_flush_rxfifo();
 
-	/* Wait for read/write operation to complete on actual memory */
-	udelay(10000);
-
 	return 0;
 }
 
@@ -257,10 +248,26 @@ int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len)
 {
 	unsigned long start_time_rx;
 
-	if (check_params(addr, alen, buffer, len))
-		return 1;
+#ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
+	/*
+	 * EEPROM chips that implement "address overflow" are ones
+	 * like Catalyst 24WC04/08/16 which has 9/10/11 bits of
+	 * address and the extra bits end up in the "chip address"
+	 * bit slots. This makes a 24WC08 (1Kbyte) chip look like
+	 * four 256 byte chips.
+	 *
+	 * Note that we consider the length of the address field to
+	 * still be one byte because the extra address bits are
+	 * hidden in the chip address.
+	 */
+	chip |= ((addr >> (alen * 8)) & CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW);
+	addr &= ~(CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW << (alen * 8));
 
-	if (i2c_xfer_init(chip, addr))
+	debug("%s: fix addr_overflow: chip %02x addr %02x\n", __func__, chip,
+	      addr);
+#endif
+
+	if (i2c_xfer_init(chip, addr, alen))
 		return 1;
 
 	start_time_rx = get_timer(0);
@@ -298,10 +305,26 @@ int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len)
 	int nb = len;
 	unsigned long start_time_tx;
 
-	if (check_params(addr, alen, buffer, len))
-		return 1;
+#ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
+	/*
+	 * EEPROM chips that implement "address overflow" are ones
+	 * like Catalyst 24WC04/08/16 which has 9/10/11 bits of
+	 * address and the extra bits end up in the "chip address"
+	 * bit slots. This makes a 24WC08 (1Kbyte) chip look like
+	 * four 256 byte chips.
+	 *
+	 * Note that we consider the length of the address field to
+	 * still be one byte because the extra address bits are
+	 * hidden in the chip address.
+	 */
+	chip |= ((addr >> (alen * 8)) & CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW);
+	addr &= ~(CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW << (alen * 8));
+
+	debug("%s: fix addr_overflow: chip %02x addr %02x\n", __func__, chip,
+	      addr);
+#endif
 
-	if (i2c_xfer_init(chip, addr))
+	if (i2c_xfer_init(chip, addr, alen))
 		return 1;
 
 	start_time_tx = get_timer(0);
diff --git a/drivers/i2c/fti2c010.c b/drivers/i2c/fti2c010.c
index ddeb941faf..68d9a42912 100644
--- a/drivers/i2c/fti2c010.c
+++ b/drivers/i2c/fti2c010.c
@@ -13,67 +13,78 @@
 
 #include "fti2c010.h"
 
-#ifndef CONFIG_HARD_I2C
-#error "fti2c010: CONFIG_HARD_I2C is not defined"
+#ifndef CONFIG_SYS_I2C_SPEED
+#define CONFIG_SYS_I2C_SPEED    5000
 #endif
 
-#ifndef CONFIG_SYS_I2C_SPEED
-#define CONFIG_SYS_I2C_SPEED    50000
+#ifndef CONFIG_SYS_I2C_SLAVE
+#define CONFIG_SYS_I2C_SLAVE    0
 #endif
 
-#ifndef CONFIG_FTI2C010_FREQ
-#define CONFIG_FTI2C010_FREQ    clk_get_rate("I2C")
+#ifndef CONFIG_FTI2C010_CLOCK
+#define CONFIG_FTI2C010_CLOCK   clk_get_rate("I2C")
 #endif
 
-/* command timeout */
-#define CFG_CMD_TIMEOUT         10 /* ms */
+#ifndef CONFIG_FTI2C010_TIMEOUT
+#define CONFIG_FTI2C010_TIMEOUT 10 /* ms */
+#endif
 
-/* 7-bit chip address + 1-bit read/write */
-#define I2C_RD(chip)            ((((chip) << 1) & 0xff) | 1)
-#define I2C_WR(chip)            (((chip) << 1) & 0xff)
+/* 7-bit dev address + 1-bit read/write */
+#define I2C_RD(dev)             ((((dev) << 1) & 0xfe) | 1)
+#define I2C_WR(dev)             (((dev) << 1) & 0xfe)
 
 struct fti2c010_chip {
-	void __iomem *regs;
-	uint bus;
-	uint speed;
+	struct fti2c010_regs *regs;
 };
 
 static struct fti2c010_chip chip_list[] = {
 	{
-		.bus  = 0,
-		.regs = (void __iomem *)CONFIG_FTI2C010_BASE,
+		.regs = (struct fti2c010_regs *)CONFIG_FTI2C010_BASE,
 	},
-#ifdef CONFIG_I2C_MULTI_BUS
-# ifdef CONFIG_FTI2C010_BASE1
+#ifdef CONFIG_FTI2C010_BASE1
 	{
-		.bus  = 1,
-		.regs = (void __iomem *)CONFIG_FTI2C010_BASE1,
+		.regs = (struct fti2c010_regs *)CONFIG_FTI2C010_BASE1,
 	},
-# endif
-# ifdef CONFIG_FTI2C010_BASE2
+#endif
+#ifdef CONFIG_FTI2C010_BASE2
 	{
-		.bus  = 2,
-		.regs = (void __iomem *)CONFIG_FTI2C010_BASE2,
+		.regs = (struct fti2c010_regs *)CONFIG_FTI2C010_BASE2,
 	},
-# endif
-# ifdef CONFIG_FTI2C010_BASE3
+#endif
+#ifdef CONFIG_FTI2C010_BASE3
 	{
-		.bus  = 3,
-		.regs = (void __iomem *)CONFIG_FTI2C010_BASE3,
+		.regs = (struct fti2c010_regs *)CONFIG_FTI2C010_BASE3,
 	},
-# endif
-#endif  /* #ifdef CONFIG_I2C_MULTI_BUS */
+#endif
 };
 
-static struct fti2c010_chip *curr = chip_list;
+static int fti2c010_reset(struct fti2c010_chip *chip)
+{
+	ulong ts;
+	int ret = -1;
+	struct fti2c010_regs *regs = chip->regs;
+
+	writel(CR_I2CRST, &regs->cr);
+	for (ts = get_timer(0); get_timer(ts) < CONFIG_FTI2C010_TIMEOUT; ) {
+		if (!(readl(&regs->cr) & CR_I2CRST)) {
+			ret = 0;
+			break;
+		}
+	}
 
-static int fti2c010_wait(uint32_t mask)
+	if (ret)
+		printf("fti2c010: reset timeout\n");
+
+	return ret;
+}
+
+static int fti2c010_wait(struct fti2c010_chip *chip, uint32_t mask)
 {
 	int ret = -1;
 	uint32_t stat, ts;
-	struct fti2c010_regs *regs = curr->regs;
+	struct fti2c010_regs *regs = chip->regs;
 
-	for (ts = get_timer(0); get_timer(ts) < CFG_CMD_TIMEOUT; ) {
+	for (ts = get_timer(0); get_timer(ts) < CONFIG_FTI2C010_TIMEOUT; ) {
 		stat = readl(&regs->sr);
 		if ((stat & mask) == mask) {
 			ret = 0;
@@ -84,88 +95,124 @@ static int fti2c010_wait(uint32_t mask)
 	return ret;
 }
 
-/*
- * u-boot I2C API
- */
+static unsigned int set_i2c_bus_speed(struct fti2c010_chip *chip,
+	unsigned int speed)
+{
+	struct fti2c010_regs *regs = chip->regs;
+	unsigned int clk = CONFIG_FTI2C010_CLOCK;
+	unsigned int gsr = 0;
+	unsigned int tsr = 32;
+	unsigned int div, rate;
+
+	for (div = 0; div < 0x3ffff; ++div) {
+		/* SCLout = PCLK/(2*(COUNT + 2) + GSR) */
+		rate = clk / (2 * (div + 2) + gsr);
+		if (rate <= speed)
+			break;
+	}
+
+	writel(TGSR_GSR(gsr) | TGSR_TSR(tsr), &regs->tgsr);
+	writel(CDR_DIV(div), &regs->cdr);
+
+	return rate;
+}
 
 /*
  * Initialization, must be called once on start up, may be called
  * repeatedly to change the speed and slave addresses.
  */
-void i2c_init(int speed, int slaveaddr)
+static void fti2c010_init(struct i2c_adapter *adap, int speed, int slaveaddr)
 {
-	if (speed || !curr->speed)
-		i2c_set_bus_speed(speed);
+	struct fti2c010_chip *chip = chip_list + adap->hwadapnr;
 
-	/* if slave mode disabled */
-	if (!slaveaddr)
+	if (adap->init_done)
 		return;
 
-	/*
-	 * TODO:
-	 * Implement slave mode, but is it really necessary?
-	 */
+#ifdef CONFIG_SYS_I2C_INIT_BOARD
+	/* Call board specific i2c bus reset routine before accessing the
+	 * environment, which might be in a chip on that bus. For details
+	 * about this problem see doc/I2C_Edge_Conditions.
+	*/
+	i2c_init_board();
+#endif
+
+	/* master init */
+
+	fti2c010_reset(chip);
+
+	set_i2c_bus_speed(chip, speed);
+
+	/* slave init, don't care */
+
+#ifdef CONFIG_SYS_I2C_BOARD_LATE_INIT
+	/* Call board specific i2c bus reset routine AFTER the bus has been
+	 * initialized. Use either this callpoint or i2c_init_board;
+	 * which is called before fti2c010_init operations.
+	 * For details about this problem see doc/I2C_Edge_Conditions.
+	*/
+	i2c_board_late_init();
+#endif
 }
 
 /*
  * Probe the given I2C chip address.  Returns 0 if a chip responded,
  * not 0 on failure.
  */
-int i2c_probe(uchar chip)
+static int fti2c010_probe(struct i2c_adapter *adap, u8 dev)
 {
+	struct fti2c010_chip *chip = chip_list + adap->hwadapnr;
+	struct fti2c010_regs *regs = chip->regs;
 	int ret;
-	struct fti2c010_regs *regs = curr->regs;
-
-	i2c_init(0, 0);
 
 	/* 1. Select slave device (7bits Address + 1bit R/W) */
-	writel(I2C_WR(chip), &regs->dr);
+	writel(I2C_WR(dev), &regs->dr);
 	writel(CR_ENABLE | CR_TBEN | CR_START, &regs->cr);
-	ret = fti2c010_wait(SR_DT);
+	ret = fti2c010_wait(chip, SR_DT);
 	if (ret)
 		return ret;
 
 	/* 2. Select device register */
 	writel(0, &regs->dr);
 	writel(CR_ENABLE | CR_TBEN, &regs->cr);
-	ret = fti2c010_wait(SR_DT);
+	ret = fti2c010_wait(chip, SR_DT);
 
 	return ret;
 }
 
-/*
- * Read/Write interface:
- *   chip:    I2C chip address, range 0..127
- *   addr:    Memory (register) address within the chip
- *   alen:    Number of bytes to use for addr (typically 1, 2 for larger
- *              memories, 0 for register type devices with only one
- *              register)
- *   buffer:  Where to read/write the data
- *   len:     How many bytes to read/write
- *
- *   Returns: 0 on success, not 0 on failure
- */
-int i2c_read(uchar chip, uint addr, int alen, uchar *buf, int len)
+static void to_i2c_addr(u8 *buf, uint32_t addr, int alen)
 {
-	int ret, pos;
-	uchar paddr[4];
-	struct fti2c010_regs *regs = curr->regs;
+	int i, shift;
 
-	i2c_init(0, 0);
+	if (!buf || alen <= 0)
+		return;
+
+	/* MSB first */
+	i = 0;
+	shift = (alen - 1) * 8;
+	while (alen-- > 0) {
+		buf[i] = (u8)(addr >> shift);
+		shift -= 8;
+	}
+}
 
-	paddr[0] = (addr >> 0)  & 0xFF;
-	paddr[1] = (addr >> 8)  & 0xFF;
-	paddr[2] = (addr >> 16) & 0xFF;
-	paddr[3] = (addr >> 24) & 0xFF;
+static int fti2c010_read(struct i2c_adapter *adap,
+			u8 dev, uint addr, int alen, uchar *buf, int len)
+{
+	struct fti2c010_chip *chip = chip_list + adap->hwadapnr;
+	struct fti2c010_regs *regs = chip->regs;
+	int ret, pos;
+	uchar paddr[4] = { 0 };
+
+	to_i2c_addr(paddr, addr, alen);
 
 	/*
 	 * Phase A. Set register address
 	 */
 
 	/* A.1 Select slave device (7bits Address + 1bit R/W) */
-	writel(I2C_WR(chip), &regs->dr);
+	writel(I2C_WR(dev), &regs->dr);
 	writel(CR_ENABLE | CR_TBEN | CR_START, &regs->cr);
-	ret = fti2c010_wait(SR_DT);
+	ret = fti2c010_wait(chip, SR_DT);
 	if (ret)
 		return ret;
 
@@ -175,7 +222,7 @@ int i2c_read(uchar chip, uint addr, int alen, uchar *buf, int len)
 
 		writel(paddr[pos], &regs->dr);
 		writel(ctrl, &regs->cr);
-		ret = fti2c010_wait(SR_DT);
+		ret = fti2c010_wait(chip, SR_DT);
 		if (ret)
 			return ret;
 	}
@@ -185,9 +232,9 @@ int i2c_read(uchar chip, uint addr, int alen, uchar *buf, int len)
 	 */
 
 	/* B.1 Select slave device (7bits Address + 1bit R/W) */
-	writel(I2C_RD(chip), &regs->dr);
+	writel(I2C_RD(dev), &regs->dr);
 	writel(CR_ENABLE | CR_TBEN | CR_START, &regs->cr);
-	ret = fti2c010_wait(SR_DT);
+	ret = fti2c010_wait(chip, SR_DT);
 	if (ret)
 		return ret;
 
@@ -201,7 +248,7 @@ int i2c_read(uchar chip, uint addr, int alen, uchar *buf, int len)
 			stat |= SR_ACK;
 		}
 		writel(ctrl, &regs->cr);
-		ret = fti2c010_wait(stat);
+		ret = fti2c010_wait(chip, stat);
 		if (ret)
 			break;
 		buf[pos] = (uchar)(readl(&regs->dr) & 0xFF);
@@ -210,39 +257,24 @@ int i2c_read(uchar chip, uint addr, int alen, uchar *buf, int len)
 	return ret;
 }
 
-/*
- * Read/Write interface:
- *   chip:    I2C chip address, range 0..127
- *   addr:    Memory (register) address within the chip
- *   alen:    Number of bytes to use for addr (typically 1, 2 for larger
- *              memories, 0 for register type devices with only one
- *              register)
- *   buffer:  Where to read/write the data
- *   len:     How many bytes to read/write
- *
- *   Returns: 0 on success, not 0 on failure
- */
-int i2c_write(uchar chip, uint addr, int alen, uchar *buf, int len)
+static int fti2c010_write(struct i2c_adapter *adap,
+			u8 dev, uint addr, int alen, u8 *buf, int len)
 {
+	struct fti2c010_chip *chip = chip_list + adap->hwadapnr;
+	struct fti2c010_regs *regs = chip->regs;
 	int ret, pos;
-	uchar paddr[4];
-	struct fti2c010_regs *regs = curr->regs;
+	uchar paddr[4] = { 0 };
 
-	i2c_init(0, 0);
-
-	paddr[0] = (addr >> 0)  & 0xFF;
-	paddr[1] = (addr >> 8)  & 0xFF;
-	paddr[2] = (addr >> 16) & 0xFF;
-	paddr[3] = (addr >> 24) & 0xFF;
+	to_i2c_addr(paddr, addr, alen);
 
 	/*
 	 * Phase A. Set register address
 	 *
 	 * A.1 Select slave device (7bits Address + 1bit R/W)
 	 */
-	writel(I2C_WR(chip), &regs->dr);
+	writel(I2C_WR(dev), &regs->dr);
 	writel(CR_ENABLE | CR_TBEN | CR_START, &regs->cr);
-	ret = fti2c010_wait(SR_DT);
+	ret = fti2c010_wait(chip, SR_DT);
 	if (ret)
 		return ret;
 
@@ -252,7 +284,7 @@ int i2c_write(uchar chip, uint addr, int alen, uchar *buf, int len)
 
 		writel(paddr[pos], &regs->dr);
 		writel(ctrl, &regs->cr);
-		ret = fti2c010_wait(SR_DT);
+		ret = fti2c010_wait(chip, SR_DT);
 		if (ret)
 			return ret;
 	}
@@ -267,7 +299,7 @@ int i2c_write(uchar chip, uint addr, int alen, uchar *buf, int len)
 			ctrl |= CR_STOP;
 		writel(buf[pos], &regs->dr);
 		writel(ctrl, &regs->cr);
-		ret = fti2c010_wait(SR_DT);
+		ret = fti2c010_wait(chip, SR_DT);
 		if (ret)
 			break;
 	}
@@ -275,94 +307,40 @@ int i2c_write(uchar chip, uint addr, int alen, uchar *buf, int len)
 	return ret;
 }
 
-/*
- * Functions for setting the current I2C bus and its speed
- */
-#ifdef CONFIG_I2C_MULTI_BUS
-
-/*
- * i2c_set_bus_num:
- *
- *  Change the active I2C bus.  Subsequent read/write calls will
- *  go to this one.
- *
- *    bus - bus index, zero based
- *
- *    Returns: 0 on success, not 0 on failure
- */
-int i2c_set_bus_num(uint bus)
-{
-	if (bus >= ARRAY_SIZE(chip_list))
-		return -1;
-	curr = chip_list + bus;
-	i2c_init(0, 0);
-	return 0;
-}
-
-/*
- * i2c_get_bus_num:
- *
- *  Returns index of currently active I2C bus.  Zero-based.
- */
-
-uint i2c_get_bus_num(void)
-{
-	return curr->bus;
-}
-
-#endif    /* #ifdef CONFIG_I2C_MULTI_BUS */
-
-/*
- * i2c_set_bus_speed:
- *
- *  Change the speed of the active I2C bus
- *
- *    speed - bus speed in Hz
- *
- *    Returns: 0 on success, not 0 on failure
- */
-int i2c_set_bus_speed(uint speed)
+static unsigned int fti2c010_set_bus_speed(struct i2c_adapter *adap,
+			unsigned int speed)
 {
-	struct fti2c010_regs *regs = curr->regs;
-	uint clk = CONFIG_FTI2C010_FREQ;
-	uint gsr = 0, tsr = 32;
-	uint spd, div;
-
-	if (!speed)
-		speed = CONFIG_SYS_I2C_SPEED;
-
-	for (div = 0; div < 0x3ffff; ++div) {
-		/* SCLout = PCLK/(2*(COUNT + 2) + GSR) */
-		spd = clk / (2 * (div + 2) + gsr);
-		if (spd <= speed)
-			break;
-	}
-
-	if (curr->speed == spd)
-		return 0;
-
-	writel(CR_I2CRST, &regs->cr);
-	mdelay(100);
-	if (readl(&regs->cr) & CR_I2CRST) {
-		printf("fti2c010: reset timeout\n");
-		return -1;
-	}
+	struct fti2c010_chip *chip = chip_list + adap->hwadapnr;
+	int ret;
 
-	curr->speed = spd;
+	fti2c010_reset(chip);
+	ret = set_i2c_bus_speed(chip, speed);
 
-	writel(TGSR_GSR(gsr) | TGSR_TSR(tsr), &regs->tgsr);
-	writel(CDR_DIV(div), &regs->cdr);
-
-	return 0;
+	return ret;
 }
 
 /*
- * i2c_get_bus_speed:
- *
- *  Returns speed of currently active I2C bus in Hz
+ * Register i2c adapters
  */
-
-uint i2c_get_bus_speed(void)
-{
-	return curr->speed;
-}
+U_BOOT_I2C_ADAP_COMPLETE(i2c_0, fti2c010_init, fti2c010_probe, fti2c010_read,
+			fti2c010_write, fti2c010_set_bus_speed,
+			CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE,
+			0)
+#ifdef CONFIG_FTI2C010_BASE1
+U_BOOT_I2C_ADAP_COMPLETE(i2c_1, fti2c010_init, fti2c010_probe, fti2c010_read,
+			fti2c010_write, fti2c010_set_bus_speed,
+			CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE,
+			1)
+#endif
+#ifdef CONFIG_FTI2C010_BASE2
+U_BOOT_I2C_ADAP_COMPLETE(i2c_2, fti2c010_init, fti2c010_probe, fti2c010_read,
+			fti2c010_write, fti2c010_set_bus_speed,
+			CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE,
+			2)
+#endif
+#ifdef CONFIG_FTI2C010_BASE3
+U_BOOT_I2C_ADAP_COMPLETE(i2c_3, fti2c010_init, fti2c010_probe, fti2c010_read,
+			fti2c010_write, fti2c010_set_bus_speed,
+			CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE,
+			3)
+#endif
diff --git a/drivers/i2c/i2c_core.c b/drivers/i2c/i2c_core.c
index d1072e819b..18d6736601 100644
--- a/drivers/i2c/i2c_core.c
+++ b/drivers/i2c/i2c_core.c
@@ -53,32 +53,26 @@ void i2c_reloc_fixup(void)
 		return;
 
 	for (i = 0; i < max; i++) {
-		/* adapter itself */
-		addr = (unsigned long)i2c_adap_p;
-		addr += gd->reloc_off;
-		i2c_adap_p = (struct i2c_adapter *)addr;
 		/* i2c_init() */
 		addr = (unsigned long)i2c_adap_p->init;
 		addr += gd->reloc_off;
-		i2c_adap_p->init = (void (*)(int, int))addr;
+		i2c_adap_p->init = (void *)addr;
 		/* i2c_probe() */
 		addr = (unsigned long)i2c_adap_p->probe;
 		addr += gd->reloc_off;
-		i2c_adap_p->probe = (int (*)(uint8_t))addr;
+		i2c_adap_p->probe = (void *)addr;
 		/* i2c_read() */
 		addr = (unsigned long)i2c_adap_p->read;
 		addr += gd->reloc_off;
-		i2c_adap_p->read = (int (*)(uint8_t, uint, int, uint8_t *,
-					int))addr;
+		i2c_adap_p->read = (void *)addr;
 		/* i2c_write() */
 		addr = (unsigned long)i2c_adap_p->write;
 		addr += gd->reloc_off;
-		i2c_adap_p->write = (int (*)(uint8_t, uint, int, uint8_t *,
-					int))addr;
+		i2c_adap_p->write = (void *)addr;
 		/* i2c_set_bus_speed() */
 		addr = (unsigned long)i2c_adap_p->set_bus_speed;
 		addr += gd->reloc_off;
-		i2c_adap_p->set_bus_speed = (uint (*)(uint))addr;
+		i2c_adap_p->set_bus_speed = (void *)addr;
 		/* name */
 		addr = (unsigned long)i2c_adap_p->name;
 		addr += gd->reloc_off;
@@ -138,6 +132,11 @@ static int i2c_mux_set(struct i2c_adapter *adap, int mux_id, int chip,
 			return -1;
 		buf = (uint8_t)((channel & 0x07) | (1 << 3));
 		break;
+	case I2C_MUX_PCA9548_ID:
+		if (channel > 7)
+			return -1;
+		buf = (uint8_t)(0x01 << channel);
+		break;
 	default:
 		printf("%s: wrong mux id: %d\n", __func__, mux_id);
 		return -1;
@@ -278,20 +277,22 @@ unsigned int i2c_get_bus_num(void)
  */
 int i2c_set_bus_num(unsigned int bus)
 {
-	int max = ll_entry_count(struct i2c_adapter, i2c);
+	int max;
+
+	if ((bus == I2C_BUS) && (I2C_ADAP->init_done > 0))
+		return 0;
 
-	if (I2C_ADAPTER(bus) >= max) {
-		printf("Error, wrong i2c adapter %d max %d possible\n",
-		       I2C_ADAPTER(bus), max);
-		return -2;
-	}
 #ifndef CONFIG_SYS_I2C_DIRECT_BUS
 	if (bus >= CONFIG_SYS_NUM_I2C_BUSES)
 		return -1;
 #endif
 
-	if ((bus == I2C_BUS) && (I2C_ADAP->init_done > 0))
-		return 0;
+	max = ll_entry_count(struct i2c_adapter, i2c);
+	if (I2C_ADAPTER(bus) >= max) {
+		printf("Error, wrong i2c adapter %d max %d possible\n",
+		       I2C_ADAPTER(bus), max);
+		return -2;
+	}
 
 #ifndef CONFIG_SYS_I2C_DIRECT_BUS
 	i2c_mux_disconnet_all();
@@ -348,7 +349,7 @@ unsigned int i2c_set_bus_speed(unsigned int speed)
 		return 0;
 	ret = I2C_ADAP->set_bus_speed(I2C_ADAP, speed);
 	if (gd->flags & GD_FLG_RELOC)
-		I2C_ADAP->speed = ret;
+		I2C_ADAP->speed = (ret == 0) ? speed : 0;
 
 	return ret;
 }
diff --git a/drivers/i2c/kona_i2c.c b/drivers/i2c/kona_i2c.c
new file mode 100644
index 0000000000..0b1715abf0
--- /dev/null
+++ b/drivers/i2c/kona_i2c.c
@@ -0,0 +1,730 @@
+/*
+ * Copyright 2013 Broadcom Corporation.
+ *
+ * SPDX-License-Identifier:      GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/errno.h>
+#include <asm/arch/sysmap.h>
+#include <asm/kona-common/clk.h>
+#include <i2c.h>
+
+/* Hardware register offsets and field defintions */
+#define CS_OFFSET				0x00000020
+#define CS_ACK_SHIFT				3
+#define CS_ACK_MASK				0x00000008
+#define CS_ACK_CMD_GEN_START			0x00000000
+#define CS_ACK_CMD_GEN_RESTART			0x00000001
+#define CS_CMD_SHIFT				1
+#define CS_CMD_CMD_NO_ACTION			0x00000000
+#define CS_CMD_CMD_START_RESTART		0x00000001
+#define CS_CMD_CMD_STOP				0x00000002
+#define CS_EN_SHIFT				0
+#define CS_EN_CMD_ENABLE_BSC			0x00000001
+
+#define TIM_OFFSET				0x00000024
+#define TIM_PRESCALE_SHIFT			6
+#define TIM_P_SHIFT				3
+#define TIM_NO_DIV_SHIFT			2
+#define TIM_DIV_SHIFT				0
+
+#define DAT_OFFSET				0x00000028
+
+#define TOUT_OFFSET				0x0000002c
+
+#define TXFCR_OFFSET				0x0000003c
+#define TXFCR_FIFO_FLUSH_MASK			0x00000080
+#define TXFCR_FIFO_EN_MASK			0x00000040
+
+#define IER_OFFSET				0x00000044
+#define IER_READ_COMPLETE_INT_MASK		0x00000010
+#define IER_I2C_INT_EN_MASK			0x00000008
+#define IER_FIFO_INT_EN_MASK			0x00000002
+#define IER_NOACK_EN_MASK			0x00000001
+
+#define ISR_OFFSET				0x00000048
+#define ISR_RESERVED_MASK			0xffffff60
+#define ISR_CMDBUSY_MASK			0x00000080
+#define ISR_READ_COMPLETE_MASK			0x00000010
+#define ISR_SES_DONE_MASK			0x00000008
+#define ISR_ERR_MASK				0x00000004
+#define ISR_TXFIFOEMPTY_MASK			0x00000002
+#define ISR_NOACK_MASK				0x00000001
+
+#define CLKEN_OFFSET				0x0000004c
+#define CLKEN_AUTOSENSE_OFF_MASK		0x00000080
+#define CLKEN_M_SHIFT				4
+#define CLKEN_N_SHIFT				1
+#define CLKEN_CLKEN_MASK			0x00000001
+
+#define FIFO_STATUS_OFFSET			0x00000054
+#define FIFO_STATUS_RXFIFO_EMPTY_MASK		0x00000004
+#define FIFO_STATUS_TXFIFO_EMPTY_MASK		0x00000010
+
+#define HSTIM_OFFSET				0x00000058
+#define HSTIM_HS_MODE_MASK			0x00008000
+#define HSTIM_HS_HOLD_SHIFT			10
+#define HSTIM_HS_HIGH_PHASE_SHIFT		5
+#define HSTIM_HS_SETUP_SHIFT			0
+
+#define PADCTL_OFFSET				0x0000005c
+#define PADCTL_PAD_OUT_EN_MASK			0x00000004
+
+#define RXFCR_OFFSET				0x00000068
+#define RXFCR_NACK_EN_SHIFT			7
+#define RXFCR_READ_COUNT_SHIFT			0
+#define RXFIFORDOUT_OFFSET			0x0000006c
+
+/* Locally used constants */
+#define MAX_RX_FIFO_SIZE		64U	/* bytes */
+#define MAX_TX_FIFO_SIZE		64U	/* bytes */
+
+#define I2C_TIMEOUT			100000	/* usecs */
+
+#define WAIT_INT_CHK			100	/* usecs */
+#if I2C_TIMEOUT % WAIT_INT_CHK
+#error I2C_TIMEOUT must be a multiple of WAIT_INT_CHK
+#endif
+
+/* Operations that can be commanded to the controller */
+enum bcm_kona_cmd_t {
+	BCM_CMD_NOACTION = 0,
+	BCM_CMD_START,
+	BCM_CMD_RESTART,
+	BCM_CMD_STOP,
+};
+
+enum bus_speed_index {
+	BCM_SPD_100K = 0,
+	BCM_SPD_400K,
+	BCM_SPD_1MHZ,
+};
+
+/* Internal divider settings for standard mode, fast mode and fast mode plus */
+struct bus_speed_cfg {
+	uint8_t time_m;		/* Number of cycles for setup time */
+	uint8_t time_n;		/* Number of cycles for hold time */
+	uint8_t prescale;	/* Prescale divider */
+	uint8_t time_p;		/* Timing coefficient */
+	uint8_t no_div;		/* Disable clock divider */
+	uint8_t time_div;	/* Post-prescale divider */
+};
+
+static const struct bus_speed_cfg std_cfg_table[] = {
+	[BCM_SPD_100K] = {0x01, 0x01, 0x03, 0x06, 0x00, 0x02},
+	[BCM_SPD_400K] = {0x05, 0x01, 0x03, 0x05, 0x01, 0x02},
+	[BCM_SPD_1MHZ] = {0x01, 0x01, 0x03, 0x01, 0x01, 0x03},
+};
+
+struct bcm_kona_i2c_dev {
+	void *base;
+	uint speed;
+	const struct bus_speed_cfg *std_cfg;
+};
+
+/* Keep these two defines in sync */
+#define DEF_SPD 100000
+#define DEF_SPD_ENUM BCM_SPD_100K
+
+#define DEF_DEVICE(num) \
+{(void *)CONFIG_SYS_I2C_BASE##num, DEF_SPD, &std_cfg_table[DEF_SPD_ENUM]}
+
+static struct bcm_kona_i2c_dev g_i2c_devs[CONFIG_SYS_MAX_I2C_BUS] = {
+#ifdef CONFIG_SYS_I2C_BASE0
+	DEF_DEVICE(0),
+#endif
+#ifdef CONFIG_SYS_I2C_BASE1
+	DEF_DEVICE(1),
+#endif
+#ifdef CONFIG_SYS_I2C_BASE2
+	DEF_DEVICE(2),
+#endif
+#ifdef CONFIG_SYS_I2C_BASE3
+	DEF_DEVICE(3),
+#endif
+#ifdef CONFIG_SYS_I2C_BASE4
+	DEF_DEVICE(4),
+#endif
+#ifdef CONFIG_SYS_I2C_BASE5
+	DEF_DEVICE(5),
+#endif
+};
+
+#define I2C_M_TEN	0x0010	/* ten bit address */
+#define I2C_M_RD	0x0001	/* read data */
+#define I2C_M_NOSTART	0x4000	/* no restart between msgs */
+
+struct i2c_msg {
+	uint16_t addr;
+	uint16_t flags;
+	uint16_t len;
+	uint8_t *buf;
+};
+
+static void bcm_kona_i2c_send_cmd_to_ctrl(struct bcm_kona_i2c_dev *dev,
+					  enum bcm_kona_cmd_t cmd)
+{
+	debug("%s, %d\n", __func__, cmd);
+
+	switch (cmd) {
+	case BCM_CMD_NOACTION:
+		writel((CS_CMD_CMD_NO_ACTION << CS_CMD_SHIFT) |
+		       (CS_EN_CMD_ENABLE_BSC << CS_EN_SHIFT),
+		       dev->base + CS_OFFSET);
+		break;
+
+	case BCM_CMD_START:
+		writel((CS_ACK_CMD_GEN_START << CS_ACK_SHIFT) |
+		       (CS_CMD_CMD_START_RESTART << CS_CMD_SHIFT) |
+		       (CS_EN_CMD_ENABLE_BSC << CS_EN_SHIFT),
+		       dev->base + CS_OFFSET);
+		break;
+
+	case BCM_CMD_RESTART:
+		writel((CS_ACK_CMD_GEN_RESTART << CS_ACK_SHIFT) |
+		       (CS_CMD_CMD_START_RESTART << CS_CMD_SHIFT) |
+		       (CS_EN_CMD_ENABLE_BSC << CS_EN_SHIFT),
+		       dev->base + CS_OFFSET);
+		break;
+
+	case BCM_CMD_STOP:
+		writel((CS_CMD_CMD_STOP << CS_CMD_SHIFT) |
+		       (CS_EN_CMD_ENABLE_BSC << CS_EN_SHIFT),
+		       dev->base + CS_OFFSET);
+		break;
+
+	default:
+		printf("Unknown command %d\n", cmd);
+	}
+}
+
+static void bcm_kona_i2c_enable_clock(struct bcm_kona_i2c_dev *dev)
+{
+	writel(readl(dev->base + CLKEN_OFFSET) | CLKEN_CLKEN_MASK,
+	       dev->base + CLKEN_OFFSET);
+}
+
+static void bcm_kona_i2c_disable_clock(struct bcm_kona_i2c_dev *dev)
+{
+	writel(readl(dev->base + CLKEN_OFFSET) & ~CLKEN_CLKEN_MASK,
+	       dev->base + CLKEN_OFFSET);
+}
+
+/* Wait until at least one of the mask bit(s) are set */
+static unsigned long wait_for_int_timeout(struct bcm_kona_i2c_dev *dev,
+					  unsigned long time_left,
+					  uint32_t mask)
+{
+	uint32_t status;
+
+	while (time_left) {
+		status = readl(dev->base + ISR_OFFSET);
+
+		if ((status & ~ISR_RESERVED_MASK) == 0) {
+			debug("Bogus I2C interrupt 0x%x\n", status);
+			continue;
+		}
+
+		/* Must flush the TX FIFO when NAK detected */
+		if (status & ISR_NOACK_MASK)
+			writel(TXFCR_FIFO_FLUSH_MASK | TXFCR_FIFO_EN_MASK,
+			       dev->base + TXFCR_OFFSET);
+
+		writel(status & ~ISR_RESERVED_MASK, dev->base + ISR_OFFSET);
+
+		if (status & mask) {
+			/* We are done since one of the mask bits are set */
+			return time_left;
+		}
+		udelay(WAIT_INT_CHK);
+		time_left -= WAIT_INT_CHK;
+	}
+	return 0;
+}
+
+/* Send command to I2C bus */
+static int bcm_kona_send_i2c_cmd(struct bcm_kona_i2c_dev *dev,
+				 enum bcm_kona_cmd_t cmd)
+{
+	int rc = 0;
+	unsigned long time_left = I2C_TIMEOUT;
+
+	/* Send the command */
+	bcm_kona_i2c_send_cmd_to_ctrl(dev, cmd);
+
+	/* Wait for transaction to finish or timeout */
+	time_left = wait_for_int_timeout(dev, time_left, IER_I2C_INT_EN_MASK);
+
+	if (!time_left) {
+		printf("controller timed out\n");
+		rc = -ETIMEDOUT;
+	}
+
+	/* Clear command */
+	bcm_kona_i2c_send_cmd_to_ctrl(dev, BCM_CMD_NOACTION);
+
+	return rc;
+}
+
+/* Read a single RX FIFO worth of data from the i2c bus */
+static int bcm_kona_i2c_read_fifo_single(struct bcm_kona_i2c_dev *dev,
+					 uint8_t *buf, unsigned int len,
+					 unsigned int last_byte_nak)
+{
+	unsigned long time_left = I2C_TIMEOUT;
+
+	/* Start the RX FIFO */
+	writel((last_byte_nak << RXFCR_NACK_EN_SHIFT) |
+	       (len << RXFCR_READ_COUNT_SHIFT), dev->base + RXFCR_OFFSET);
+
+	/* Wait for FIFO read to complete */
+	time_left =
+	    wait_for_int_timeout(dev, time_left, IER_READ_COMPLETE_INT_MASK);
+
+	if (!time_left) {
+		printf("RX FIFO time out\n");
+		return -EREMOTEIO;
+	}
+
+	/* Read data from FIFO */
+	for (; len > 0; len--, buf++)
+		*buf = readl(dev->base + RXFIFORDOUT_OFFSET);
+
+	return 0;
+}
+
+/* Read any amount of data using the RX FIFO from the i2c bus */
+static int bcm_kona_i2c_read_fifo(struct bcm_kona_i2c_dev *dev,
+				  struct i2c_msg *msg)
+{
+	unsigned int bytes_to_read = MAX_RX_FIFO_SIZE;
+	unsigned int last_byte_nak = 0;
+	unsigned int bytes_read = 0;
+	int rc;
+
+	uint8_t *tmp_buf = msg->buf;
+
+	while (bytes_read < msg->len) {
+		if (msg->len - bytes_read <= MAX_RX_FIFO_SIZE) {
+			last_byte_nak = 1;	/* NAK last byte of transfer */
+			bytes_to_read = msg->len - bytes_read;
+		}
+
+		rc = bcm_kona_i2c_read_fifo_single(dev, tmp_buf, bytes_to_read,
+						   last_byte_nak);
+		if (rc < 0)
+			return -EREMOTEIO;
+
+		bytes_read += bytes_to_read;
+		tmp_buf += bytes_to_read;
+	}
+
+	return 0;
+}
+
+/* Write a single byte of data to the i2c bus */
+static int bcm_kona_i2c_write_byte(struct bcm_kona_i2c_dev *dev, uint8_t data,
+				   unsigned int nak_expected)
+{
+	unsigned long time_left = I2C_TIMEOUT;
+	unsigned int nak_received;
+
+	/* Clear pending session done interrupt */
+	writel(ISR_SES_DONE_MASK, dev->base + ISR_OFFSET);
+
+	/* Send one byte of data */
+	writel(data, dev->base + DAT_OFFSET);
+
+	time_left = wait_for_int_timeout(dev, time_left, IER_I2C_INT_EN_MASK);
+
+	if (!time_left) {
+		debug("controller timed out\n");
+		return -ETIMEDOUT;
+	}
+
+	nak_received = readl(dev->base + CS_OFFSET) & CS_ACK_MASK ? 1 : 0;
+
+	if (nak_received ^ nak_expected) {
+		debug("unexpected NAK/ACK\n");
+		return -EREMOTEIO;
+	}
+
+	return 0;
+}
+
+/* Write a single TX FIFO worth of data to the i2c bus */
+static int bcm_kona_i2c_write_fifo_single(struct bcm_kona_i2c_dev *dev,
+					  uint8_t *buf, unsigned int len)
+{
+	int k;
+	unsigned long time_left = I2C_TIMEOUT;
+	unsigned int fifo_status;
+
+	/* Write data into FIFO */
+	for (k = 0; k < len; k++)
+		writel(buf[k], (dev->base + DAT_OFFSET));
+
+	/* Wait for FIFO to empty */
+	do {
+		time_left =
+		    wait_for_int_timeout(dev, time_left,
+					 (IER_FIFO_INT_EN_MASK |
+					  IER_NOACK_EN_MASK));
+		fifo_status = readl(dev->base + FIFO_STATUS_OFFSET);
+	} while (time_left && !(fifo_status & FIFO_STATUS_TXFIFO_EMPTY_MASK));
+
+	/* Check if there was a NAK */
+	if (readl(dev->base + CS_OFFSET) & CS_ACK_MASK) {
+		printf("unexpected NAK\n");
+		return -EREMOTEIO;
+	}
+
+	/* Check if a timeout occured */
+	if (!time_left) {
+		printf("completion timed out\n");
+		return -EREMOTEIO;
+	}
+
+	return 0;
+}
+
+/* Write any amount of data using TX FIFO to the i2c bus */
+static int bcm_kona_i2c_write_fifo(struct bcm_kona_i2c_dev *dev,
+				   struct i2c_msg *msg)
+{
+	unsigned int bytes_to_write = MAX_TX_FIFO_SIZE;
+	unsigned int bytes_written = 0;
+	int rc;
+
+	uint8_t *tmp_buf = msg->buf;
+
+	while (bytes_written < msg->len) {
+		if (msg->len - bytes_written <= MAX_TX_FIFO_SIZE)
+			bytes_to_write = msg->len - bytes_written;
+
+		rc = bcm_kona_i2c_write_fifo_single(dev, tmp_buf,
+						    bytes_to_write);
+		if (rc < 0)
+			return -EREMOTEIO;
+
+		bytes_written += bytes_to_write;
+		tmp_buf += bytes_to_write;
+	}
+
+	return 0;
+}
+
+/* Send i2c address */
+static int bcm_kona_i2c_do_addr(struct bcm_kona_i2c_dev *dev,
+				struct i2c_msg *msg)
+{
+	unsigned char addr;
+
+	if (msg->flags & I2C_M_TEN) {
+		/* First byte is 11110XX0 where XX is upper 2 bits */
+		addr = 0xf0 | ((msg->addr & 0x300) >> 7);
+		if (bcm_kona_i2c_write_byte(dev, addr, 0) < 0)
+			return -EREMOTEIO;
+
+		/* Second byte is the remaining 8 bits */
+		addr = msg->addr & 0xff;
+		if (bcm_kona_i2c_write_byte(dev, addr, 0) < 0)
+			return -EREMOTEIO;
+
+		if (msg->flags & I2C_M_RD) {
+			/* For read, send restart command */
+			if (bcm_kona_send_i2c_cmd(dev, BCM_CMD_RESTART) < 0)
+				return -EREMOTEIO;
+
+			/* Then re-send the first byte with the read bit set */
+			addr = 0xf0 | ((msg->addr & 0x300) >> 7) | 0x01;
+			if (bcm_kona_i2c_write_byte(dev, addr, 0) < 0)
+				return -EREMOTEIO;
+		}
+	} else {
+		addr = msg->addr << 1;
+
+		if (msg->flags & I2C_M_RD)
+			addr |= 1;
+
+		if (bcm_kona_i2c_write_byte(dev, addr, 0) < 0)
+			return -EREMOTEIO;
+	}
+
+	return 0;
+}
+
+static void bcm_kona_i2c_enable_autosense(struct bcm_kona_i2c_dev *dev)
+{
+	writel(readl(dev->base + CLKEN_OFFSET) & ~CLKEN_AUTOSENSE_OFF_MASK,
+	       dev->base + CLKEN_OFFSET);
+}
+
+static void bcm_kona_i2c_config_timing(struct bcm_kona_i2c_dev *dev)
+{
+	writel(readl(dev->base + HSTIM_OFFSET) & ~HSTIM_HS_MODE_MASK,
+	       dev->base + HSTIM_OFFSET);
+
+	writel((dev->std_cfg->prescale << TIM_PRESCALE_SHIFT) |
+	       (dev->std_cfg->time_p << TIM_P_SHIFT) |
+	       (dev->std_cfg->no_div << TIM_NO_DIV_SHIFT) |
+	       (dev->std_cfg->time_div << TIM_DIV_SHIFT),
+	       dev->base + TIM_OFFSET);
+
+	writel((dev->std_cfg->time_m << CLKEN_M_SHIFT) |
+	       (dev->std_cfg->time_n << CLKEN_N_SHIFT) |
+	       CLKEN_CLKEN_MASK, dev->base + CLKEN_OFFSET);
+}
+
+/* Master transfer function */
+static int bcm_kona_i2c_xfer(struct bcm_kona_i2c_dev *dev,
+			     struct i2c_msg msgs[], int num)
+{
+	struct i2c_msg *pmsg;
+	int rc = 0;
+	int i;
+
+	/* Enable pad output */
+	writel(0, dev->base + PADCTL_OFFSET);
+
+	/* Enable internal clocks */
+	bcm_kona_i2c_enable_clock(dev);
+
+	/* Send start command */
+	rc = bcm_kona_send_i2c_cmd(dev, BCM_CMD_START);
+	if (rc < 0) {
+		printf("Start command failed rc = %d\n", rc);
+		goto xfer_disable_pad;
+	}
+
+	/* Loop through all messages */
+	for (i = 0; i < num; i++) {
+		pmsg = &msgs[i];
+
+		/* Send restart for subsequent messages */
+		if ((i != 0) && ((pmsg->flags & I2C_M_NOSTART) == 0)) {
+			rc = bcm_kona_send_i2c_cmd(dev, BCM_CMD_RESTART);
+			if (rc < 0) {
+				printf("restart cmd failed rc = %d\n", rc);
+				goto xfer_send_stop;
+			}
+		}
+
+		/* Send slave address */
+		if (!(pmsg->flags & I2C_M_NOSTART)) {
+			rc = bcm_kona_i2c_do_addr(dev, pmsg);
+			if (rc < 0) {
+				debug("NAK from addr %2.2x msg#%d rc = %d\n",
+				      pmsg->addr, i, rc);
+				goto xfer_send_stop;
+			}
+		}
+
+		/* Perform data transfer */
+		if (pmsg->flags & I2C_M_RD) {
+			rc = bcm_kona_i2c_read_fifo(dev, pmsg);
+			if (rc < 0) {
+				printf("read failure\n");
+				goto xfer_send_stop;
+			}
+		} else {
+			rc = bcm_kona_i2c_write_fifo(dev, pmsg);
+			if (rc < 0) {
+				printf("write failure");
+				goto xfer_send_stop;
+			}
+		}
+	}
+
+	rc = num;
+
+xfer_send_stop:
+	/* Send a STOP command */
+	bcm_kona_send_i2c_cmd(dev, BCM_CMD_STOP);
+
+xfer_disable_pad:
+	/* Disable pad output */
+	writel(PADCTL_PAD_OUT_EN_MASK, dev->base + PADCTL_OFFSET);
+
+	/* Stop internal clock */
+	bcm_kona_i2c_disable_clock(dev);
+
+	return rc;
+}
+
+static uint bcm_kona_i2c_assign_bus_speed(struct bcm_kona_i2c_dev *dev,
+					  uint speed)
+{
+	switch (speed) {
+	case 100000:
+		dev->std_cfg = &std_cfg_table[BCM_SPD_100K];
+		break;
+	case 400000:
+		dev->std_cfg = &std_cfg_table[BCM_SPD_400K];
+		break;
+	case 1000000:
+		dev->std_cfg = &std_cfg_table[BCM_SPD_1MHZ];
+		break;
+	default:
+		printf("%d hz bus speed not supported\n", speed);
+		return -EINVAL;
+	}
+	dev->speed = speed;
+	return 0;
+}
+
+static void bcm_kona_i2c_init(struct bcm_kona_i2c_dev *dev)
+{
+	/* Parse bus speed */
+	bcm_kona_i2c_assign_bus_speed(dev, dev->speed);
+
+	/* Enable internal clocks */
+	bcm_kona_i2c_enable_clock(dev);
+
+	/* Configure internal dividers */
+	bcm_kona_i2c_config_timing(dev);
+
+	/* Disable timeout */
+	writel(0, dev->base + TOUT_OFFSET);
+
+	/* Enable autosense */
+	bcm_kona_i2c_enable_autosense(dev);
+
+	/* Enable TX FIFO */
+	writel(TXFCR_FIFO_FLUSH_MASK | TXFCR_FIFO_EN_MASK,
+	       dev->base + TXFCR_OFFSET);
+
+	/* Mask all interrupts */
+	writel(0, dev->base + IER_OFFSET);
+
+	/* Clear all pending interrupts */
+	writel(ISR_CMDBUSY_MASK |
+	       ISR_READ_COMPLETE_MASK |
+	       ISR_SES_DONE_MASK |
+	       ISR_ERR_MASK |
+	       ISR_TXFIFOEMPTY_MASK | ISR_NOACK_MASK, dev->base + ISR_OFFSET);
+
+	/* Enable the controller but leave it idle */
+	bcm_kona_i2c_send_cmd_to_ctrl(dev, BCM_CMD_NOACTION);
+
+	/* Disable pad output */
+	writel(PADCTL_PAD_OUT_EN_MASK, dev->base + PADCTL_OFFSET);
+}
+
+/*
+ * uboot layer
+ */
+struct bcm_kona_i2c_dev *kona_get_dev(struct i2c_adapter *adap)
+{
+	return &g_i2c_devs[adap->hwadapnr];
+}
+
+static void kona_i2c_init(struct i2c_adapter *adap, int speed, int slaveaddr)
+{
+	struct bcm_kona_i2c_dev *dev = kona_get_dev(adap);
+
+	if (clk_bsc_enable(dev->base))
+		return;
+
+	bcm_kona_i2c_init(dev);
+}
+
+static int kona_i2c_read(struct i2c_adapter *adap, uchar chip, uint addr,
+			 int alen, uchar *buffer, int len)
+{
+	/* msg[0] writes the addr, msg[1] reads the data */
+	struct i2c_msg msg[2];
+	unsigned char msgbuf0[64];
+	struct bcm_kona_i2c_dev *dev = kona_get_dev(adap);
+
+	msg[0].addr = chip;
+	msg[0].flags = 0;
+	msg[0].len = 1;
+	msg[0].buf = msgbuf0;	/* msgbuf0 contains incrementing reg addr */
+
+	msg[1].addr = chip;
+	msg[1].flags = I2C_M_RD;
+	/* msg[1].buf dest ptr increments each read */
+
+	msgbuf0[0] = (unsigned char)addr;
+	msg[1].buf = buffer;
+	msg[1].len = len;
+	if (bcm_kona_i2c_xfer(dev, msg, 2) < 0) {
+		/* Sending 2 i2c messages */
+		kona_i2c_init(adap, adap->speed, adap->slaveaddr);
+		debug("I2C read: I/O error\n");
+		return -EIO;
+	}
+	return 0;
+}
+
+static int kona_i2c_write(struct i2c_adapter *adap, uchar chip, uint addr,
+			  int alen, uchar *buffer, int len)
+{
+	struct i2c_msg msg[0];
+	unsigned char msgbuf0[64];
+	unsigned int i;
+	struct bcm_kona_i2c_dev *dev = kona_get_dev(adap);
+
+	msg[0].addr = chip;
+	msg[0].flags = 0;
+	msg[0].len = 2;		/* addr byte plus data */
+	msg[0].buf = msgbuf0;
+
+	for (i = 0; i < len; i++) {
+		msgbuf0[0] = addr++;
+		msgbuf0[1] = buffer[i];
+		if (bcm_kona_i2c_xfer(dev, msg, 1) < 0) {
+			kona_i2c_init(adap, adap->speed, adap->slaveaddr);
+			debug("I2C write: I/O error\n");
+			return -EIO;
+		}
+	}
+	return 0;
+}
+
+static int kona_i2c_probe(struct i2c_adapter *adap, uchar chip)
+{
+	uchar tmp;
+
+	/*
+	 * read addr 0x0 of the given chip.
+	 */
+	return kona_i2c_read(adap, chip, 0x0, 1, &tmp, 1);
+}
+
+static uint kona_i2c_set_bus_speed(struct i2c_adapter *adap, uint speed)
+{
+	struct bcm_kona_i2c_dev *dev = kona_get_dev(adap);
+	return bcm_kona_i2c_assign_bus_speed(dev, speed);
+}
+
+/*
+ * Register kona i2c adapters. Keep the order below so
+ * that the bus number matches the adapter number.
+ */
+#define DEF_ADAPTER(num) \
+U_BOOT_I2C_ADAP_COMPLETE(kona##num, kona_i2c_init, kona_i2c_probe, \
+			 kona_i2c_read, kona_i2c_write, \
+			 kona_i2c_set_bus_speed, DEF_SPD, 0x00, num)
+
+#ifdef CONFIG_SYS_I2C_BASE0
+	DEF_ADAPTER(0)
+#endif
+#ifdef CONFIG_SYS_I2C_BASE1
+	DEF_ADAPTER(1)
+#endif
+#ifdef CONFIG_SYS_I2C_BASE2
+	DEF_ADAPTER(2)
+#endif
+#ifdef CONFIG_SYS_I2C_BASE3
+	DEF_ADAPTER(3)
+#endif
+#ifdef CONFIG_SYS_I2C_BASE4
+	DEF_ADAPTER(4)
+#endif
+#ifdef CONFIG_SYS_I2C_BASE5
+	DEF_ADAPTER(5)
+#endif
diff --git a/drivers/i2c/mxc_i2c.c b/drivers/i2c/mxc_i2c.c
index 06ba4e39f1..595019b3b8 100644
--- a/drivers/i2c/mxc_i2c.c
+++ b/drivers/i2c/mxc_i2c.c
@@ -102,6 +102,28 @@ static u16 i2c_clk_div[50][2] = {
 };
 #endif
 
+
+#ifndef CONFIG_SYS_MXC_I2C1_SPEED
+#define CONFIG_SYS_MXC_I2C1_SPEED 100000
+#endif
+#ifndef CONFIG_SYS_MXC_I2C2_SPEED
+#define CONFIG_SYS_MXC_I2C2_SPEED 100000
+#endif
+#ifndef CONFIG_SYS_MXC_I2C3_SPEED
+#define CONFIG_SYS_MXC_I2C3_SPEED 100000
+#endif
+
+#ifndef CONFIG_SYS_MXC_I2C1_SLAVE
+#define CONFIG_SYS_MXC_I2C1_SLAVE 0
+#endif
+#ifndef CONFIG_SYS_MXC_I2C2_SLAVE
+#define CONFIG_SYS_MXC_I2C2_SLAVE 0
+#endif
+#ifndef CONFIG_SYS_MXC_I2C3_SLAVE
+#define CONFIG_SYS_MXC_I2C3_SLAVE 0
+#endif
+
+
 /*
  * Calculate and set proper clock divider
  */
@@ -153,21 +175,6 @@ static int bus_i2c_set_bus_speed(void *base, int speed)
 	return 0;
 }
 
-/*
- * Get I2C Speed
- */
-static unsigned int bus_i2c_get_bus_speed(void *base)
-{
-	struct mxc_i2c_regs *i2c_regs = (struct mxc_i2c_regs *)base;
-	u8 clk_idx = readb(&i2c_regs->ifdr);
-	u8 clk_div;
-
-	for (clk_div = 0; i2c_clk_div[clk_div][1] != clk_idx; clk_div++)
-		;
-
-	return mxc_get_clock(MXC_I2C_CLK) / i2c_clk_div[clk_div][0];
-}
-
 #define ST_BUS_IDLE (0 | (I2SR_IBB << 8))
 #define ST_BUS_BUSY (I2SR_IBB | (I2SR_IBB << 8))
 #define ST_IIF (I2SR_IIF | (I2SR_IIF << 8))
@@ -410,20 +417,30 @@ struct sram_data {
  */
 static struct sram_data __attribute__((section(".data"))) srdata;
 
-void *get_base(void)
-{
-#ifdef CONFIG_SYS_I2C_BASE
-#ifdef CONFIG_I2C_MULTI_BUS
-	void *ret = srdata.i2c_data[srdata.curr_i2c_bus].base;
-	if (ret)
-		return ret;
-#endif
-	return (void *)CONFIG_SYS_I2C_BASE;
-#elif defined(CONFIG_I2C_MULTI_BUS)
-	return srdata.i2c_data[srdata.curr_i2c_bus].base;
+static void * const i2c_bases[] = {
+#if defined(CONFIG_MX25)
+	(void *)IMX_I2C_BASE,
+	(void *)IMX_I2C2_BASE,
+	(void *)IMX_I2C3_BASE
+#elif defined(CONFIG_MX27)
+	(void *)IMX_I2C1_BASE,
+	(void *)IMX_I2C2_BASE
+#elif defined(CONFIG_MX31) || defined(CONFIG_MX35) || \
+	defined(CONFIG_MX51) || defined(CONFIG_MX53) ||	\
+	defined(CONFIG_MX6)
+	(void *)I2C1_BASE_ADDR,
+	(void *)I2C2_BASE_ADDR,
+	(void *)I2C3_BASE_ADDR
+#elif defined(CONFIG_VF610)
+	(void *)I2C0_BASE_ADDR
 #else
-	return srdata.i2c_data[0].base;
+#error "architecture not supported"
 #endif
+};
+
+void *i2c_get_base(struct i2c_adapter *adap)
+{
+	return i2c_bases[adap->hwadapnr];
 }
 
 static struct i2c_parms *i2c_get_parms(void *base)
@@ -448,39 +465,26 @@ static int i2c_idle_bus(void *base)
 	return 0;
 }
 
-#ifdef CONFIG_I2C_MULTI_BUS
-unsigned int i2c_get_bus_num(void)
-{
-	return srdata.curr_i2c_bus;
-}
-
-int i2c_set_bus_num(unsigned bus_idx)
-{
-	if (bus_idx >= ARRAY_SIZE(srdata.i2c_data))
-		return -1;
-	if (!srdata.i2c_data[bus_idx].base)
-		return -1;
-	srdata.curr_i2c_bus = bus_idx;
-	return 0;
-}
-#endif
-
-int i2c_read(uchar chip, uint addr, int alen, uchar *buf, int len)
+static int mxc_i2c_read(struct i2c_adapter *adap, uint8_t chip,
+				uint addr, int alen, uint8_t *buffer,
+				int len)
 {
-	return bus_i2c_read(get_base(), chip, addr, alen, buf, len);
+	return bus_i2c_read(i2c_get_base(adap), chip, addr, alen, buffer, len);
 }
 
-int i2c_write(uchar chip, uint addr, int alen, uchar *buf, int len)
+static int mxc_i2c_write(struct i2c_adapter *adap, uint8_t chip,
+				uint addr, int alen, uint8_t *buffer,
+				int len)
 {
-	return bus_i2c_write(get_base(), chip, addr, alen, buf, len);
+	return bus_i2c_write(i2c_get_base(adap), chip, addr, alen, buffer, len);
 }
 
 /*
  * Test if a chip at a given address responds (probe the chip)
  */
-int i2c_probe(uchar chip)
+static int mxc_i2c_probe(struct i2c_adapter *adap, uint8_t chip)
 {
-	return bus_i2c_write(get_base(), chip, 0, 0, NULL, 0);
+	return bus_i2c_write(i2c_get_base(adap), chip, 0, 0, NULL, 0);
 }
 
 void bus_i2c_init(void *base, int speed, int unused,
@@ -510,23 +514,38 @@ void bus_i2c_init(void *base, int speed, int unused,
 /*
  * Init I2C Bus
  */
-void i2c_init(int speed, int unused)
+static void mxc_i2c_init(struct i2c_adapter *adap, int speed, int slaveaddr)
 {
-	bus_i2c_init(get_base(), speed, unused, NULL, NULL);
+	bus_i2c_init(i2c_get_base(adap), speed, slaveaddr, NULL, NULL);
 }
 
 /*
  * Set I2C Speed
  */
-int i2c_set_bus_speed(unsigned int speed)
+static uint mxc_i2c_set_bus_speed(struct i2c_adapter *adap, uint speed)
 {
-	return bus_i2c_set_bus_speed(get_base(), speed);
+	return bus_i2c_set_bus_speed(i2c_get_base(adap), speed);
 }
 
 /*
- * Get I2C Speed
+ * Register mxc i2c adapters
  */
-unsigned int i2c_get_bus_speed(void)
-{
-	return bus_i2c_get_bus_speed(get_base());
-}
+U_BOOT_I2C_ADAP_COMPLETE(mxc0, mxc_i2c_init, mxc_i2c_probe,
+			 mxc_i2c_read, mxc_i2c_write,
+			 mxc_i2c_set_bus_speed,
+			 CONFIG_SYS_MXC_I2C1_SPEED,
+			 CONFIG_SYS_MXC_I2C1_SLAVE, 0)
+U_BOOT_I2C_ADAP_COMPLETE(mxc1, mxc_i2c_init, mxc_i2c_probe,
+			 mxc_i2c_read, mxc_i2c_write,
+			 mxc_i2c_set_bus_speed,
+			 CONFIG_SYS_MXC_I2C2_SPEED,
+			 CONFIG_SYS_MXC_I2C2_SLAVE, 1)
+#if defined(CONFIG_MX31) || defined(CONFIG_MX35) ||\
+	defined(CONFIG_MX51) || defined(CONFIG_MX53) ||\
+	defined(CONFIG_MX6)
+U_BOOT_I2C_ADAP_COMPLETE(mxc2, mxc_i2c_init, mxc_i2c_probe,
+			 mxc_i2c_read, mxc_i2c_write,
+			 mxc_i2c_set_bus_speed,
+			 CONFIG_SYS_MXC_I2C3_SPEED,
+			 CONFIG_SYS_MXC_I2C3_SLAVE, 2)
+#endif
diff --git a/drivers/i2c/mxs_i2c.c b/drivers/i2c/mxs_i2c.c
index 46106b7712..de3b19402b 100644
--- a/drivers/i2c/mxs_i2c.c
+++ b/drivers/i2c/mxs_i2c.c
@@ -64,16 +64,17 @@ static void mxs_i2c_setup_read(uint8_t chip, int len)
 	writel(I2C_QUEUECTRL_QUEUE_RUN, &i2c_regs->hw_i2c_queuectrl_set);
 }
 
-static void mxs_i2c_write(uchar chip, uint addr, int alen,
+static int mxs_i2c_write(uchar chip, uint addr, int alen,
 			uchar *buf, int blen, int stop)
 {
 	struct mxs_i2c_regs *i2c_regs = (struct mxs_i2c_regs *)MXS_I2C0_BASE;
-	uint32_t data;
+	uint32_t data, tmp;
 	int i, remain, off;
+	int timeout = MXS_I2C_MAX_TIMEOUT;
 
 	if ((alen > 4) || (alen == 0)) {
 		debug("MXS I2C: Invalid address length\n");
-		return;
+		return -EINVAL;
 	}
 
 	if (stop)
@@ -106,6 +107,19 @@ static void mxs_i2c_write(uchar chip, uint addr, int alen,
 		writel(data >> remain, &i2c_regs->hw_i2c_data);
 
 	writel(I2C_QUEUECTRL_QUEUE_RUN, &i2c_regs->hw_i2c_queuectrl_set);
+
+	while (--timeout) {
+		tmp = readl(&i2c_regs->hw_i2c_queuestat);
+		if (tmp & I2C_QUEUESTAT_WR_QUEUE_EMPTY)
+			break;
+	}
+
+	if (!timeout) {
+		debug("MXS I2C: Failed transmitting data!\n");
+		return -EINVAL;
+	}
+
+	return 0;
 }
 
 static int mxs_i2c_wait_for_ack(void)
@@ -150,10 +164,16 @@ int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len)
 {
 	struct mxs_i2c_regs *i2c_regs = (struct mxs_i2c_regs *)MXS_I2C0_BASE;
 	uint32_t tmp = 0;
+	int timeout = MXS_I2C_MAX_TIMEOUT;
 	int ret;
 	int i;
 
-	mxs_i2c_write(chip, addr, alen, NULL, 0, 0);
+	ret = mxs_i2c_write(chip, addr, alen, NULL, 0, 0);
+	if (ret) {
+		debug("MXS I2C: Failed writing address\n");
+		return ret;
+	}
+
 	ret = mxs_i2c_wait_for_ack();
 	if (ret) {
 		debug("MXS I2C: Failed writing address\n");
@@ -169,9 +189,17 @@ int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len)
 
 	for (i = 0; i < len; i++) {
 		if (!(i & 3)) {
-			while (readl(&i2c_regs->hw_i2c_queuestat) &
-				I2C_QUEUESTAT_RD_QUEUE_EMPTY)
-				;
+			while (--timeout) {
+				tmp = readl(&i2c_regs->hw_i2c_queuestat);
+				if (!(tmp & I2C_QUEUESTAT_RD_QUEUE_EMPTY))
+					break;
+			}
+
+			if (!timeout) {
+				debug("MXS I2C: Failed receiving data!\n");
+				return -ETIMEDOUT;
+			}
+
 			tmp = readl(&i2c_regs->hw_i2c_queuedata);
 		}
 		buffer[i] = tmp & 0xff;
@@ -184,7 +212,12 @@ int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len)
 int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len)
 {
 	int ret;
-	mxs_i2c_write(chip, addr, alen, buffer, len, 1);
+	ret = mxs_i2c_write(chip, addr, alen, buffer, len, 1);
+	if (ret) {
+		debug("MXS I2C: Failed writing address\n");
+		return ret;
+	}
+
 	ret = mxs_i2c_wait_for_ack();
 	if (ret)
 		debug("MXS I2C: Failed writing address\n");
@@ -195,8 +228,9 @@ int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len)
 int i2c_probe(uchar chip)
 {
 	int ret;
-	mxs_i2c_write(chip, 0, 1, NULL, 0, 1);
-	ret = mxs_i2c_wait_for_ack();
+	ret = mxs_i2c_write(chip, 0, 1, NULL, 0, 1);
+	if (!ret)
+		ret = mxs_i2c_wait_for_ack();
 	mxs_i2c_reset();
 	return ret;
 }
diff --git a/drivers/i2c/omap1510_i2c.c b/drivers/i2c/omap1510_i2c.c
deleted file mode 100644
index f91ee8884a..0000000000
--- a/drivers/i2c/omap1510_i2c.c
+++ /dev/null
@@ -1,277 +0,0 @@
-/*
- * Basic I2C functions
- *
- * Copyright (c) 2003 Texas Instruments
- *
- * This package is free software;  you can redistribute it and/or
- * modify it under the terms of the license found in the file
- * named COPYING that should have accompanied this file.
- *
- * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
- * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
- *
- * Author: Jian Zhang jzhang@ti.com, Texas Instruments
- *
- * Copyright (c) 2003 Wolfgang Denk, wd@denx.de
- * Rewritten to fit into the current U-Boot framework
- *
- */
-
-#include <common.h>
-
-static void wait_for_bb (void);
-static u16 wait_for_pin (void);
-
-void i2c_init (int speed, int slaveadd)
-{
-	u16 scl;
-
-	if (inw (I2C_CON) & I2C_CON_EN) {
-		outw (0, I2C_CON);
-		udelay (5000);
-	}
-
-	/* 12MHz I2C module clock */
-	outw (0, I2C_PSC);
-	outw (I2C_CON_EN, I2C_CON);
-	outw (0, I2C_SYSTEST);
-	/* have to enable intrrupts or OMAP i2c module doesn't work */
-	outw (I2C_IE_XRDY_IE | I2C_IE_RRDY_IE | I2C_IE_ARDY_IE |
-	      I2C_IE_NACK_IE | I2C_IE_AL_IE, I2C_IE);
-	scl = (12000000 / 2) / speed - 6;
-	outw (scl, I2C_SCLL);
-	outw (scl, I2C_SCLH);
-	/* own address */
-	outw (slaveadd, I2C_OA);
-	outw (0, I2C_CNT);
-	udelay (1000);
-}
-
-static int i2c_read_byte (u8 devaddr, u8 regoffset, u8 * value)
-{
-	int i2c_error = 0;
-	u16 status;
-
-	/* wait until bus not busy */
-	wait_for_bb ();
-
-	/* one byte only */
-	outw (1, I2C_CNT);
-	/* set slave address */
-	outw (devaddr, I2C_SA);
-	/* no stop bit needed here */
-	outw (I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_TRX, I2C_CON);
-
-	status = wait_for_pin ();
-
-	if (status & I2C_STAT_XRDY) {
-		/* Important: have to use byte access */
-		*(volatile u8 *) (I2C_DATA) = regoffset;
-		udelay (20000);
-		if (inw (I2C_STAT) & I2C_STAT_NACK) {
-			i2c_error = 1;
-		}
-	} else {
-		i2c_error = 1;
-	}
-
-	if (!i2c_error) {
-		/* free bus, otherwise we can't use a combined transction */
-		outw (0, I2C_CON);
-		while (inw (I2C_STAT) || (inw (I2C_CON) & I2C_CON_MST)) {
-			udelay (10000);
-			/* Have to clear pending interrupt to clear I2C_STAT */
-			inw (I2C_IV);
-		}
-
-		wait_for_bb ();
-		/* set slave address */
-		outw (devaddr, I2C_SA);
-		/* read one byte from slave */
-		outw (1, I2C_CNT);
-		/* need stop bit here */
-		outw (I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_STP,
-		      I2C_CON);
-
-		status = wait_for_pin ();
-		if (status & I2C_STAT_RRDY) {
-			*value = inw (I2C_DATA);
-			udelay (20000);
-		} else {
-			i2c_error = 1;
-		}
-
-		if (!i2c_error) {
-			outw (I2C_CON_EN, I2C_CON);
-			while (inw (I2C_STAT)
-			       || (inw (I2C_CON) & I2C_CON_MST)) {
-				udelay (10000);
-				inw (I2C_IV);
-			}
-		}
-	}
-
-	return i2c_error;
-}
-
-static int i2c_write_byte (u8 devaddr, u8 regoffset, u8 value)
-{
-	int i2c_error = 0;
-	u16 status;
-
-	/* wait until bus not busy */
-	wait_for_bb ();
-
-	/* two bytes */
-	outw (2, I2C_CNT);
-	/* set slave address */
-	outw (devaddr, I2C_SA);
-	/* stop bit needed here */
-	outw (I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_TRX |
-	      I2C_CON_STP, I2C_CON);
-
-	/* wait until state change */
-	status = wait_for_pin ();
-
-	if (status & I2C_STAT_XRDY) {
-		/* send out two bytes */
-		outw ((value << 8) + regoffset, I2C_DATA);
-		/* must have enough delay to allow BB bit to go low */
-		udelay (30000);
-		if (inw (I2C_STAT) & I2C_STAT_NACK) {
-			i2c_error = 1;
-		}
-	} else {
-		i2c_error = 1;
-	}
-
-	if (!i2c_error) {
-		outw (I2C_CON_EN, I2C_CON);
-		while (inw (I2C_STAT) || (inw (I2C_CON) & I2C_CON_MST)) {
-			udelay (1000);
-			/* have to read to clear intrrupt */
-			inw (I2C_IV);
-		}
-	}
-
-	return i2c_error;
-}
-
-int i2c_probe (uchar chip)
-{
-	int res = 1;
-
-	if (chip == inw (I2C_OA)) {
-		return res;
-	}
-
-	/* wait until bus not busy */
-	wait_for_bb ();
-
-	/* try to read one byte */
-	outw (1, I2C_CNT);
-	/* set slave address */
-	outw (chip, I2C_SA);
-	/* stop bit needed here */
-	outw (I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_STP, I2C_CON);
-	/* enough delay for the NACK bit set */
-	udelay (2000);
-	if (!(inw (I2C_STAT) & I2C_STAT_NACK)) {
-		res = 0;
-	} else {
-		outw (inw (I2C_CON) | I2C_CON_STP, I2C_CON);
-		udelay (20);
-		wait_for_bb ();
-	}
-
-	return res;
-}
-
-int i2c_read (uchar chip, uint addr, int alen, uchar * buffer, int len)
-{
-	int i;
-
-	if (alen > 1) {
-		printf ("I2C read: addr len %d not supported\n", alen);
-		return 1;
-	}
-
-	if (addr + len > 256) {
-		printf ("I2C read: address out of range\n");
-		return 1;
-	}
-
-	for (i = 0; i < len; i++) {
-		if (i2c_read_byte (chip, addr + i, &buffer[i])) {
-			printf ("I2C read: I/O error\n");
-			i2c_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
-			return 1;
-		}
-	}
-
-	return 0;
-}
-
-int i2c_write (uchar chip, uint addr, int alen, uchar * buffer, int len)
-{
-	int i;
-
-	if (alen > 1) {
-		printf ("I2C read: addr len %d not supported\n", alen);
-		return 1;
-	}
-
-	if (addr + len > 256) {
-		printf ("I2C read: address out of range\n");
-		return 1;
-	}
-
-	for (i = 0; i < len; i++) {
-		if (i2c_write_byte (chip, addr + i, buffer[i])) {
-			printf ("I2C read: I/O error\n");
-			i2c_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
-			return 1;
-		}
-	}
-
-	return 0;
-}
-
-static void wait_for_bb (void)
-{
-	int timeout = 10;
-
-	while ((inw (I2C_STAT) & I2C_STAT_BB) && timeout--) {
-		inw (I2C_IV);
-		udelay (1000);
-	}
-
-	if (timeout <= 0) {
-		printf ("timed out in wait_for_bb: I2C_STAT=%x\n",
-			inw (I2C_STAT));
-	}
-}
-
-static u16 wait_for_pin (void)
-{
-	u16 status, iv;
-	int timeout = 10;
-
-	do {
-		udelay (1000);
-		status = inw (I2C_STAT);
-		iv = inw (I2C_IV);
-	} while (!iv &&
-		 !(status &
-		   (I2C_STAT_ROVR | I2C_STAT_XUDF | I2C_STAT_XRDY |
-		    I2C_STAT_RRDY | I2C_STAT_ARDY | I2C_STAT_NACK |
-		    I2C_STAT_AL)) && timeout--);
-
-	if (timeout <= 0) {
-		printf ("timed out in wait_for_pin: I2C_STAT=%x\n",
-			inw (I2C_STAT));
-	}
-
-	return status;
-}
diff --git a/drivers/i2c/omap24xx_i2c.c b/drivers/i2c/omap24xx_i2c.c
index ef38d71725..a39b5917ec 100644
--- a/drivers/i2c/omap24xx_i2c.c
+++ b/drivers/i2c/omap24xx_i2c.c
@@ -32,9 +32,14 @@
  * - Status functions now read irqstatus_raw as per TRM guidelines
  *   (except for OMAP243X and OMAP34XX).
  * - Driver now supports up to I2C5 (OMAP5).
+ *
+ * Copyright (c) 2014 Hannes Petermaier <oe5hpm@oevsv.at>, B&R
+ * - Added support for set_speed
+ *
  */
 
 #include <common.h>
+#include <i2c.h>
 
 #include <asm/arch/i2c.h>
 #include <asm/io.h>
@@ -48,55 +53,70 @@ DECLARE_GLOBAL_DATA_PTR;
 /* Absolutely safe for status update at 100 kHz I2C: */
 #define I2C_WAIT	200
 
-static int wait_for_bb(void);
-static u16 wait_for_event(void);
-static void flush_fifo(void);
+static int wait_for_bb(struct i2c_adapter *adap);
+static struct i2c *omap24_get_base(struct i2c_adapter *adap);
+static u16 wait_for_event(struct i2c_adapter *adap);
+static void flush_fifo(struct i2c_adapter *adap);
+static int omap24_i2c_findpsc(u32 *pscl, u32 *psch, uint speed)
+{
+	unsigned int sampleclk, prescaler;
+	int fsscll, fssclh;
 
-/*
- * For SPL boot some boards need i2c before SDRAM is initialised so force
- * variables to live in SRAM
- */
-static struct i2c __attribute__((section (".data"))) *i2c_base =
-					(struct i2c *)I2C_DEFAULT_BASE;
-static unsigned int __attribute__((section (".data"))) bus_initialized[I2C_BUS_MAX] =
-					{ [0 ... (I2C_BUS_MAX-1)] = 0 };
-static unsigned int __attribute__((section (".data"))) current_bus = 0;
+	speed <<= 1;
+	prescaler = 0;
+	/*
+	 * some divisors may cause a precission loss, but shouldn't
+	 * be a big thing, because i2c_clk is then allready very slow.
+	 */
+	while (prescaler <= 0xFF) {
+		sampleclk = I2C_IP_CLK / (prescaler+1);
 
-void i2c_init(int speed, int slaveadd)
-{
-	int psc, fsscll, fssclh;
-	int hsscll = 0, hssclh = 0;
-	u32 scll, sclh;
-	int timeout = I2C_TIMEOUT;
+		fsscll = sampleclk / speed;
+		fssclh = fsscll;
+		fsscll -= I2C_FASTSPEED_SCLL_TRIM;
+		fssclh -= I2C_FASTSPEED_SCLH_TRIM;
 
-	/* Only handle standard, fast and high speeds */
-	if ((speed != OMAP_I2C_STANDARD) &&
-	    (speed != OMAP_I2C_FAST_MODE) &&
-	    (speed != OMAP_I2C_HIGH_SPEED)) {
-		printf("Error : I2C unsupported speed %d\n", speed);
-		return;
-	}
+		if (((fsscll > 0) && (fssclh > 0)) &&
+		    ((fsscll <= (255-I2C_FASTSPEED_SCLL_TRIM)) &&
+		    (fssclh <= (255-I2C_FASTSPEED_SCLH_TRIM)))) {
+			if (pscl)
+				*pscl = fsscll;
+			if (psch)
+				*psch = fssclh;
 
-	psc = I2C_IP_CLK / I2C_INTERNAL_SAMPLING_CLK;
-	psc -= 1;
-	if (psc < I2C_PSC_MIN) {
-		printf("Error : I2C unsupported prescalar %d\n", psc);
-		return;
+			return prescaler;
+		}
+		prescaler++;
 	}
+	return -1;
+}
+static uint omap24_i2c_setspeed(struct i2c_adapter *adap, uint speed)
+{
+	struct i2c *i2c_base = omap24_get_base(adap);
+	int psc, fsscll = 0, fssclh = 0;
+	int hsscll = 0, hssclh = 0;
+	u32 scll = 0, sclh = 0;
 
-	if (speed == OMAP_I2C_HIGH_SPEED) {
+	if (speed >= OMAP_I2C_HIGH_SPEED) {
 		/* High speed */
+		psc = I2C_IP_CLK / I2C_INTERNAL_SAMPLING_CLK;
+		psc -= 1;
+		if (psc < I2C_PSC_MIN) {
+			printf("Error : I2C unsupported prescaler %d\n", psc);
+			return -1;
+		}
 
 		/* For first phase of HS mode */
-		fsscll = fssclh = I2C_INTERNAL_SAMPLING_CLK /
-			(2 * OMAP_I2C_FAST_MODE);
+		fsscll = I2C_INTERNAL_SAMPLING_CLK / (2 * speed);
+
+		fssclh = fsscll;
 
 		fsscll -= I2C_HIGHSPEED_PHASE_ONE_SCLL_TRIM;
 		fssclh -= I2C_HIGHSPEED_PHASE_ONE_SCLH_TRIM;
 		if (((fsscll < 0) || (fssclh < 0)) ||
 		    ((fsscll > 255) || (fssclh > 255))) {
 			puts("Error : I2C initializing first phase clock\n");
-			return;
+			return -1;
 		}
 
 		/* For second phase of HS mode */
@@ -107,7 +127,7 @@ void i2c_init(int speed, int slaveadd)
 		if (((fsscll < 0) || (fssclh < 0)) ||
 		    ((fsscll > 255) || (fssclh > 255))) {
 			puts("Error : I2C initializing second phase clock\n");
-			return;
+			return -1;
 		}
 
 		scll = (unsigned int)hsscll << 8 | (unsigned int)fsscll;
@@ -115,20 +135,29 @@ void i2c_init(int speed, int slaveadd)
 
 	} else {
 		/* Standard and fast speed */
-		fsscll = fssclh = I2C_INTERNAL_SAMPLING_CLK / (2 * speed);
-
-		fsscll -= I2C_FASTSPEED_SCLL_TRIM;
-		fssclh -= I2C_FASTSPEED_SCLH_TRIM;
-		if (((fsscll < 0) || (fssclh < 0)) ||
-		    ((fsscll > 255) || (fssclh > 255))) {
+		psc = omap24_i2c_findpsc(&scll, &sclh, speed);
+		if (0 > psc) {
 			puts("Error : I2C initializing clock\n");
-			return;
+			return -1;
 		}
-
-		scll = (unsigned int)fsscll;
-		sclh = (unsigned int)fssclh;
 	}
 
+	adap->speed	= speed;
+	adap->waitdelay = (10000000 / speed) * 2; /* wait for 20 clkperiods */
+	writew(0, &i2c_base->con);
+	writew(psc, &i2c_base->psc);
+	writew(scll, &i2c_base->scll);
+	writew(sclh, &i2c_base->sclh);
+	writew(I2C_CON_EN, &i2c_base->con);
+	writew(0xFFFF, &i2c_base->stat);	/* clear all pending status */
+
+	return 0;
+}
+static void omap24_i2c_init(struct i2c_adapter *adap, int speed, int slaveadd)
+{
+	struct i2c *i2c_base = omap24_get_base(adap);
+	int timeout = I2C_TIMEOUT;
+
 	if (readw(&i2c_base->con) & I2C_CON_EN) {
 		writew(0, &i2c_base->con);
 		udelay(50000);
@@ -146,14 +175,14 @@ void i2c_init(int speed, int slaveadd)
 		udelay(1000);
 	}
 
-	writew(0, &i2c_base->con);
-	writew(psc, &i2c_base->psc);
-	writew(scll, &i2c_base->scll);
-	writew(sclh, &i2c_base->sclh);
+	if (0 != omap24_i2c_setspeed(adap, speed)) {
+		printf("ERROR: failed to setup I2C bus-speed!\n");
+		return;
+	}
 
 	/* own address */
 	writew(slaveadd, &i2c_base->oa);
-	writew(I2C_CON_EN, &i2c_base->con);
+
 #if defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX)
 	/*
 	 * Have to enable interrupts for OMAP2/3, these IPs don't have
@@ -163,18 +192,17 @@ void i2c_init(int speed, int slaveadd)
 	       I2C_IE_NACK_IE | I2C_IE_AL_IE, &i2c_base->ie);
 #endif
 	udelay(1000);
-	flush_fifo();
+	flush_fifo(adap);
 	writew(0xFFFF, &i2c_base->stat);
-	writew(0, &i2c_base->cnt);
-
-	if (gd->flags & GD_FLG_RELOC)
-		bus_initialized[current_bus] = 1;
 }
 
-static void flush_fifo(void)
-{	u16 stat;
+static void flush_fifo(struct i2c_adapter *adap)
+{
+	struct i2c *i2c_base = omap24_get_base(adap);
+	u16 stat;
 
-	/* note: if you try and read data when its not there or ready
+	/*
+	 * note: if you try and read data when its not there or ready
 	 * you get a bus error
 	 */
 	while (1) {
@@ -192,8 +220,9 @@ static void flush_fifo(void)
  * i2c_probe: Use write access. Allows to identify addresses that are
  *            write-only (like the config register of dual-port EEPROMs)
  */
-int i2c_probe(uchar chip)
+static int omap24_i2c_probe(struct i2c_adapter *adap, uchar chip)
 {
+	struct i2c *i2c_base = omap24_get_base(adap);
 	u16 status;
 	int res = 1; /* default = fail */
 
@@ -201,18 +230,16 @@ int i2c_probe(uchar chip)
 		return res;
 
 	/* Wait until bus is free */
-	if (wait_for_bb())
+	if (wait_for_bb(adap))
 		return res;
 
 	/* No data transfer, slave addr only */
-	writew(0, &i2c_base->cnt);
-	/* Set slave address */
 	writew(chip, &i2c_base->sa);
 	/* Stop bit needed here */
 	writew(I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_TRX |
 	       I2C_CON_STP, &i2c_base->con);
 
-	status = wait_for_event();
+	status = wait_for_event(adap);
 
 	if ((status & ~I2C_STAT_XRDY) == 0 || (status & I2C_STAT_AL)) {
 		/*
@@ -223,15 +250,15 @@ int i2c_probe(uchar chip)
 		 */
 		if (status == I2C_STAT_XRDY)
 			printf("i2c_probe: pads on bus %d probably not configured (status=0x%x)\n",
-			       current_bus, status);
+			       adap->hwadapnr, status);
 
 		goto pr_exit;
 	}
 
 	/* Check for ACK (!NAK) */
 	if (!(status & I2C_STAT_NACK)) {
-		res = 0;			/* Device found */
-		udelay(I2C_WAIT);		/* Required by AM335X in SPL */
+		res = 0;				/* Device found */
+		udelay(adap->waitdelay);/* Required by AM335X in SPL */
 		/* Abort transfer (force idle state) */
 		writew(I2C_CON_MST | I2C_CON_TRX, &i2c_base->con); /* Reset */
 		udelay(1000);
@@ -239,9 +266,8 @@ int i2c_probe(uchar chip)
 		       I2C_CON_STP, &i2c_base->con);		/* STP */
 	}
 pr_exit:
-	flush_fifo();
+	flush_fifo(adap);
 	writew(0xFFFF, &i2c_base->stat);
-	writew(0, &i2c_base->cnt);
 	return res;
 }
 
@@ -258,8 +284,10 @@ pr_exit:
  *           or that do not need a register address at all (such as some clock
  *           distributors).
  */
-int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len)
+static int omap24_i2c_read(struct i2c_adapter *adap, uchar chip, uint addr,
+			   int alen, uchar *buffer, int len)
 {
+	struct i2c *i2c_base = omap24_get_base(adap);
 	int i2c_error = 0;
 	u16 status;
 
@@ -287,7 +315,7 @@ int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len)
 	}
 
 	/* Wait until bus not busy */
-	if (wait_for_bb())
+	if (wait_for_bb(adap))
 		return 1;
 
 	/* Zero, one or two bytes reg address (offset) */
@@ -308,15 +336,15 @@ int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len)
 #endif
 		/* Send register offset */
 		while (1) {
-			status = wait_for_event();
+			status = wait_for_event(adap);
 			/* Try to identify bus that is not padconf'd for I2C */
 			if (status == I2C_STAT_XRDY) {
 				i2c_error = 2;
 				printf("i2c_read (addr phase): pads on bus %d probably not configured (status=0x%x)\n",
-				       current_bus, status);
+				       adap->hwadapnr, status);
 				goto rd_exit;
 			}
-			if (status == 0 || status & I2C_STAT_NACK) {
+			if (status == 0 || (status & I2C_STAT_NACK)) {
 				i2c_error = 1;
 				printf("i2c_read: error waiting for addr ACK (status=0x%x)\n",
 				       status);
@@ -348,7 +376,7 @@ int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len)
 
 	/* Receive data */
 	while (1) {
-		status = wait_for_event();
+		status = wait_for_event(adap);
 		/*
 		 * Try to identify bus that is not padconf'd for I2C. This
 		 * state could be left over from previous transactions if
@@ -357,10 +385,10 @@ int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len)
 		if (status == I2C_STAT_XRDY) {
 			i2c_error = 2;
 			printf("i2c_read (data phase): pads on bus %d probably not configured (status=0x%x)\n",
-			       current_bus, status);
+			       adap->hwadapnr, status);
 			goto rd_exit;
 		}
-		if (status == 0 || status & I2C_STAT_NACK) {
+		if (status == 0 || (status & I2C_STAT_NACK)) {
 			i2c_error = 1;
 			goto rd_exit;
 		}
@@ -375,18 +403,20 @@ int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len)
 	}
 
 rd_exit:
-	flush_fifo();
+	flush_fifo(adap);
 	writew(0xFFFF, &i2c_base->stat);
-	writew(0, &i2c_base->cnt);
 	return i2c_error;
 }
 
 /* i2c_write: Address (reg offset) may be 0, 1 or 2 bytes long. */
-int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len)
+static int omap24_i2c_write(struct i2c_adapter *adap, uchar chip, uint addr,
+			    int alen, uchar *buffer, int len)
 {
+	struct i2c *i2c_base = omap24_get_base(adap);
 	int i;
 	u16 status;
 	int i2c_error = 0;
+	int timeout = I2C_TIMEOUT;
 
 	if (alen < 0) {
 		puts("I2C write: addr len < 0\n");
@@ -415,7 +445,7 @@ int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len)
 	}
 
 	/* Wait until bus not busy */
-	if (wait_for_bb())
+	if (wait_for_bb(adap))
 		return 1;
 
 	/* Start address phase - will write regoffset + len bytes data */
@@ -428,15 +458,15 @@ int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len)
 
 	while (alen) {
 		/* Must write reg offset (one or two bytes) */
-		status = wait_for_event();
+		status = wait_for_event(adap);
 		/* Try to identify bus that is not padconf'd for I2C */
 		if (status == I2C_STAT_XRDY) {
 			i2c_error = 2;
 			printf("i2c_write: pads on bus %d probably not configured (status=0x%x)\n",
-			       current_bus, status);
+			       adap->hwadapnr, status);
 			goto wr_exit;
 		}
-		if (status == 0 || status & I2C_STAT_NACK) {
+		if (status == 0 || (status & I2C_STAT_NACK)) {
 			i2c_error = 1;
 			printf("i2c_write: error waiting for addr ACK (status=0x%x)\n",
 			       status);
@@ -455,8 +485,8 @@ int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len)
 	}
 	/* Address phase is over, now write data */
 	for (i = 0; i < len; i++) {
-		status = wait_for_event();
-		if (status == 0 || status & I2C_STAT_NACK) {
+		status = wait_for_event(adap);
+		if (status == 0 || (status & I2C_STAT_NACK)) {
 			i2c_error = 1;
 			printf("i2c_write: error waiting for data ACK (status=0x%x)\n",
 			       status);
@@ -472,11 +502,19 @@ int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len)
 			goto wr_exit;
 		}
 	}
+	/*
+	 * poll ARDY bit for making sure that last byte really has been
+	 * transferred on the bus.
+	 */
+	do {
+		status = wait_for_event(adap);
+	} while (!(status & I2C_STAT_ARDY) && timeout--);
+	if (timeout <= 0)
+		printf("i2c_write: timed out writig last byte!\n");
 
 wr_exit:
-	flush_fifo();
+	flush_fifo(adap);
 	writew(0xFFFF, &i2c_base->stat);
-	writew(0, &i2c_base->cnt);
 	return i2c_error;
 }
 
@@ -484,8 +522,9 @@ wr_exit:
  * Wait for the bus to be free by checking the Bus Busy (BB)
  * bit to become clear
  */
-static int wait_for_bb(void)
+static int wait_for_bb(struct i2c_adapter *adap)
 {
+	struct i2c *i2c_base = omap24_get_base(adap);
 	int timeout = I2C_TIMEOUT;
 	u16 stat;
 
@@ -498,7 +537,7 @@ static int wait_for_bb(void)
 		I2C_STAT_BB) && timeout--) {
 #endif
 		writew(stat, &i2c_base->stat);
-		udelay(I2C_WAIT);
+		udelay(adap->waitdelay);
 	}
 
 	if (timeout <= 0) {
@@ -514,13 +553,14 @@ static int wait_for_bb(void)
  * Wait for the I2C controller to complete current action
  * and update status
  */
-static u16 wait_for_event(void)
+static u16 wait_for_event(struct i2c_adapter *adap)
 {
+	struct i2c *i2c_base = omap24_get_base(adap);
 	u16 status;
 	int timeout = I2C_TIMEOUT;
 
 	do {
-		udelay(I2C_WAIT);
+		udelay(adap->waitdelay);
 #if defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX)
 		status = readw(&i2c_base->stat);
 #else
@@ -540,7 +580,7 @@ static u16 wait_for_event(void)
 		 * not been configured for I2C, and/or pull-ups are missing.
 		 */
 		printf("Check if pads/pull-ups of bus %d are properly configured\n",
-		       current_bus);
+		       adap->hwadapnr);
 		writew(0xFFFF, &i2c_base->stat);
 		status = 0;
 	}
@@ -548,48 +588,93 @@ static u16 wait_for_event(void)
 	return status;
 }
 
-int i2c_set_bus_num(unsigned int bus)
+static struct i2c *omap24_get_base(struct i2c_adapter *adap)
 {
-	if (bus >= I2C_BUS_MAX) {
-		printf("Bad bus: %x\n", bus);
-		return -1;
-	}
-
-	switch (bus) {
-	default:
-		bus = 0;	/* Fall through */
+	switch (adap->hwadapnr) {
 	case 0:
-		i2c_base = (struct i2c *)I2C_BASE1;
+		return (struct i2c *)I2C_BASE1;
 		break;
 	case 1:
-		i2c_base = (struct i2c *)I2C_BASE2;
+		return (struct i2c *)I2C_BASE2;
 		break;
 #if (I2C_BUS_MAX > 2)
 	case 2:
-		i2c_base = (struct i2c *)I2C_BASE3;
+		return (struct i2c *)I2C_BASE3;
 		break;
 #if (I2C_BUS_MAX > 3)
 	case 3:
-		i2c_base = (struct i2c *)I2C_BASE4;
+		return (struct i2c *)I2C_BASE4;
 		break;
 #if (I2C_BUS_MAX > 4)
 	case 4:
-		i2c_base = (struct i2c *)I2C_BASE5;
+		return (struct i2c *)I2C_BASE5;
 		break;
 #endif
 #endif
 #endif
+	default:
+		printf("wrong hwadapnr: %d\n", adap->hwadapnr);
+		break;
 	}
+	return NULL;
+}
 
-	current_bus = bus;
+#if !defined(CONFIG_SYS_OMAP24_I2C_SPEED1)
+#define CONFIG_SYS_OMAP24_I2C_SPEED1 CONFIG_SYS_OMAP24_I2C_SPEED
+#endif
+#if !defined(CONFIG_SYS_OMAP24_I2C_SLAVE1)
+#define CONFIG_SYS_OMAP24_I2C_SLAVE1 CONFIG_SYS_OMAP24_I2C_SLAVE
+#endif
 
-	if (!bus_initialized[current_bus])
-		i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
+U_BOOT_I2C_ADAP_COMPLETE(omap24_0, omap24_i2c_init, omap24_i2c_probe,
+			 omap24_i2c_read, omap24_i2c_write, omap24_i2c_setspeed,
+			 CONFIG_SYS_OMAP24_I2C_SPEED,
+			 CONFIG_SYS_OMAP24_I2C_SLAVE,
+			 0)
+U_BOOT_I2C_ADAP_COMPLETE(omap24_1, omap24_i2c_init, omap24_i2c_probe,
+			 omap24_i2c_read, omap24_i2c_write, omap24_i2c_setspeed,
+			 CONFIG_SYS_OMAP24_I2C_SPEED1,
+			 CONFIG_SYS_OMAP24_I2C_SLAVE1,
+			 1)
+#if (I2C_BUS_MAX > 2)
+#if !defined(CONFIG_SYS_OMAP24_I2C_SPEED2)
+#define CONFIG_SYS_OMAP24_I2C_SPEED2 CONFIG_SYS_OMAP24_I2C_SPEED
+#endif
+#if !defined(CONFIG_SYS_OMAP24_I2C_SLAVE2)
+#define CONFIG_SYS_OMAP24_I2C_SLAVE2 CONFIG_SYS_OMAP24_I2C_SLAVE
+#endif
 
-	return 0;
-}
+U_BOOT_I2C_ADAP_COMPLETE(omap24_2, omap24_i2c_init, omap24_i2c_probe,
+			 omap24_i2c_read, omap24_i2c_write, NULL,
+			 CONFIG_SYS_OMAP24_I2C_SPEED2,
+			 CONFIG_SYS_OMAP24_I2C_SLAVE2,
+			 2)
+#if (I2C_BUS_MAX > 3)
+#if !defined(CONFIG_SYS_OMAP24_I2C_SPEED3)
+#define CONFIG_SYS_OMAP24_I2C_SPEED3 CONFIG_SYS_OMAP24_I2C_SPEED
+#endif
+#if !defined(CONFIG_SYS_OMAP24_I2C_SLAVE3)
+#define CONFIG_SYS_OMAP24_I2C_SLAVE3 CONFIG_SYS_OMAP24_I2C_SLAVE
+#endif
 
-int i2c_get_bus_num(void)
-{
-	return (int) current_bus;
-}
+U_BOOT_I2C_ADAP_COMPLETE(omap24_3, omap24_i2c_init, omap24_i2c_probe,
+			 omap24_i2c_read, omap24_i2c_write, NULL,
+			 CONFIG_SYS_OMAP24_I2C_SPEED3,
+			 CONFIG_SYS_OMAP24_I2C_SLAVE3,
+			 3)
+#if (I2C_BUS_MAX > 4)
+#if !defined(CONFIG_SYS_OMAP24_I2C_SPEED4)
+#define CONFIG_SYS_OMAP24_I2C_SPEED4 CONFIG_SYS_OMAP24_I2C_SPEED
+#endif
+#if !defined(CONFIG_SYS_OMAP24_I2C_SLAVE4)
+#define CONFIG_SYS_OMAP24_I2C_SLAVE4 CONFIG_SYS_OMAP24_I2C_SLAVE
+#endif
+
+U_BOOT_I2C_ADAP_COMPLETE(omap24_4, omap24_i2c_init, omap24_i2c_probe,
+			 omap24_i2c_read, omap24_i2c_write, NULL,
+			 CONFIG_SYS_OMAP24_I2C_SPEED4,
+			 CONFIG_SYS_OMAP24_I2C_SLAVE4,
+			 4)
+#endif
+#endif
+#endif
diff --git a/drivers/i2c/rcar_i2c.c b/drivers/i2c/rcar_i2c.c
new file mode 100644
index 0000000000..50cebd622b
--- /dev/null
+++ b/drivers/i2c/rcar_i2c.c
@@ -0,0 +1,290 @@
+/*
+ * drivers/i2c/rcar_i2c.c
+ *
+ * Copyright (C) 2013 Renesas Electronics Corporation
+ * Copyright (C) 2013 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <common.h>
+#include <i2c.h>
+#include <asm/io.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct rcar_i2c {
+	u32 icscr;
+	u32 icmcr;
+	u32 icssr;
+	u32 icmsr;
+	u32 icsier;
+	u32 icmier;
+	u32 icccr;
+	u32 icsar;
+	u32 icmar;
+	u32 icrxdtxd;
+	u32 icccr2;
+	u32 icmpr;
+	u32 ichpr;
+	u32 iclpr;
+};
+
+#define MCR_MDBS	0x80	/* non-fifo mode switch	*/
+#define MCR_FSCL	0x40	/* override SCL pin	*/
+#define MCR_FSDA	0x20	/* override SDA pin	*/
+#define MCR_OBPC	0x10	/* override pins	*/
+#define MCR_MIE		0x08	/* master if enable	*/
+#define MCR_TSBE	0x04
+#define MCR_FSB		0x02	/* force stop bit	*/
+#define MCR_ESG		0x01	/* en startbit gen.	*/
+
+#define MSR_MASK	0x7f
+#define MSR_MNR		0x40	/* nack received	*/
+#define MSR_MAL		0x20	/* arbitration lost	*/
+#define MSR_MST		0x10	/* sent a stop		*/
+#define MSR_MDE		0x08
+#define MSR_MDT		0x04
+#define MSR_MDR		0x02
+#define MSR_MAT		0x01	/* slave addr xfer done	*/
+
+static const struct rcar_i2c *i2c_dev[CONFIF_SYS_RCAR_I2C_NUM_CONTROLLERS] = {
+	(struct rcar_i2c *)CONFIG_SYS_RCAR_I2C0_BASE,
+	(struct rcar_i2c *)CONFIG_SYS_RCAR_I2C1_BASE,
+	(struct rcar_i2c *)CONFIG_SYS_RCAR_I2C2_BASE,
+	(struct rcar_i2c *)CONFIG_SYS_RCAR_I2C3_BASE,
+};
+
+static void rcar_i2c_raw_rw_common(struct rcar_i2c *dev, u8 chip, uint addr)
+{
+	/* set slave address */
+	writel(chip << 1, &dev->icmar);
+	/* set register address */
+	writel(addr, &dev->icrxdtxd);
+	/* clear status */
+	writel(0, &dev->icmsr);
+	/* start master send */
+	writel(MCR_MDBS | MCR_MIE | MCR_ESG, &dev->icmcr);
+
+	while ((readl(&dev->icmsr) & (MSR_MAT | MSR_MDE))
+		!= (MSR_MAT | MSR_MDE))
+		udelay(10);
+
+	/* clear ESG */
+	writel(MCR_MDBS | MCR_MIE, &dev->icmcr);
+	/* start SCLclk */
+	writel(~(MSR_MAT | MSR_MDE), &dev->icmsr);
+
+	while (!(readl(&dev->icmsr) & MSR_MDE))
+		udelay(10);
+}
+
+static void rcar_i2c_raw_rw_finish(struct rcar_i2c *dev)
+{
+	while (!(readl(&dev->icmsr) & MSR_MST))
+		udelay(10);
+
+	writel(0, &dev->icmcr);
+}
+
+static int
+rcar_i2c_raw_write(struct rcar_i2c *dev, u8 chip, uint addr, u8 *val, int size)
+{
+	rcar_i2c_raw_rw_common(dev, chip, addr);
+
+	/* set send date */
+	writel(*val, &dev->icrxdtxd);
+	/* start SCLclk */
+	writel(~MSR_MDE, &dev->icmsr);
+
+	while (!(readl(&dev->icmsr) & MSR_MDE))
+		udelay(10);
+
+	/* set stop condition */
+	writel(MCR_MDBS | MCR_MIE | MCR_FSB, &dev->icmcr);
+	/* start SCLclk */
+	writel(~MSR_MDE, &dev->icmsr);
+
+	rcar_i2c_raw_rw_finish(dev);
+
+	return 0;
+}
+
+static u8
+rcar_i2c_raw_read(struct rcar_i2c *dev, u8 chip, uint addr)
+{
+	u8 ret;
+
+	rcar_i2c_raw_rw_common(dev, chip, addr);
+
+	/* set slave address, receive */
+	writel((chip << 1) | 1, &dev->icmar);
+	/* clear status */
+	writel(0, &dev->icmsr);
+	/* start master receive */
+	writel(MCR_MDBS | MCR_MIE | MCR_ESG, &dev->icmcr);
+
+	while ((readl(&dev->icmsr) & (MSR_MAT | MSR_MDR))
+		!= (MSR_MAT | MSR_MDR))
+		udelay(10);
+
+	/* clear ESG */
+	writel(MCR_MDBS | MCR_MIE, &dev->icmcr);
+	/* prepare stop condition */
+	writel(MCR_MDBS | MCR_MIE | MCR_FSB, &dev->icmcr);
+	/* start SCLclk */
+	writel(~(MSR_MAT | MSR_MDR), &dev->icmsr);
+
+	while (!(readl(&dev->icmsr) & MSR_MDR))
+		udelay(10);
+
+	/* get receive data */
+	ret = (u8)readl(&dev->icrxdtxd);
+	/* start SCLclk */
+	writel(~MSR_MDR, &dev->icmsr);
+
+	rcar_i2c_raw_rw_finish(dev);
+
+	return ret;
+}
+
+/*
+ * SCL  = iicck / (20 + SCGD * 8 + F[(ticf + tr + intd) * iicck])
+ * iicck  : I2C internal clock < 20 MHz
+ * ticf : I2C SCL falling time: 35 ns
+ * tr   : I2C SCL rising time:  200 ns
+ * intd : LSI internal delay:   I2C0: 50 ns I2C1-3: 5
+ * F[n] : n rounded up to an integer
+ */
+static u32 rcar_clock_gen(int i2c_no, u32 bus_speed)
+{
+	u32 iicck, f, scl, scgd;
+	u32 intd = 5;
+
+	int bit = 0, cdf_width = 3;
+	for (bit = 0; bit < (1 << cdf_width); bit++) {
+		iicck = CONFIG_HP_CLK_FREQ / (1 + bit);
+		if (iicck < 20000000)
+			break;
+	}
+
+	if (bit > (1 << cdf_width)) {
+		puts("rcar-i2c: Can not get CDF\n");
+		return 0;
+	}
+
+	if (i2c_no == 0)
+		intd = 50;
+
+	f = (35 + 200 + intd) * (iicck / 1000000000);
+
+	for (scgd = 0; scgd < 0x40; scgd++) {
+		scl = iicck / (20 + (scgd * 8) + f);
+		if (scl <= bus_speed)
+			break;
+	}
+
+	if (scgd > 0x40) {
+		puts("rcar-i2c: Can not get SDGB\n");
+		return 0;
+	}
+
+	debug("%s: scl: %d\n", __func__, scl);
+	debug("%s: bit %x\n", __func__, bit);
+	debug("%s: scgd %x\n", __func__, scgd);
+	debug("%s: iccr %x\n", __func__, (scgd << (cdf_width) | bit));
+
+	return scgd << (cdf_width) | bit;
+}
+
+static void
+rcar_i2c_init(struct i2c_adapter *adap, int speed, int slaveadd)
+{
+	struct rcar_i2c *dev = (struct rcar_i2c *)i2c_dev[adap->hwadapnr];
+	u32 icccr = 0;
+
+	/* No i2c support prior to relocation */
+	if (!(gd->flags & GD_FLG_RELOC))
+		return;
+
+	/*
+	 * reset slave mode.
+	 * slave mode is not used on this driver
+	 */
+	writel(0, &dev->icsier);
+	writel(0, &dev->icsar);
+	writel(0, &dev->icscr);
+	writel(0, &dev->icssr);
+
+	/* reset master mode */
+	writel(0, &dev->icmier);
+	writel(0, &dev->icmcr);
+	writel(0, &dev->icmsr);
+	writel(0, &dev->icmar);
+
+	icccr = rcar_clock_gen(adap->hwadapnr, adap->speed);
+	if (icccr == 0)
+		puts("I2C: Init failed\n");
+	else
+		writel(icccr, &dev->icccr);
+}
+
+static int rcar_i2c_read(struct i2c_adapter *adap, uint8_t chip,
+			uint addr, int alen, u8 *data, int len)
+{
+	struct rcar_i2c *dev = (struct rcar_i2c *)i2c_dev[adap->hwadapnr];
+	int i;
+
+	for (i = 0; i < len; i++)
+		data[i] = rcar_i2c_raw_read(dev, chip, addr + i);
+
+	return 0;
+}
+
+static int rcar_i2c_write(struct i2c_adapter *adap, uint8_t chip, uint addr,
+			int alen, u8 *data, int len)
+{
+	struct rcar_i2c *dev = (struct rcar_i2c *)i2c_dev[adap->hwadapnr];
+	return rcar_i2c_raw_write(dev, chip, addr, data, len);
+}
+
+static int
+rcar_i2c_probe(struct i2c_adapter *adap, u8 dev)
+{
+	return rcar_i2c_read(adap, dev, 0, 0, NULL, 0);
+}
+
+static unsigned int rcar_i2c_set_bus_speed(struct i2c_adapter *adap,
+			unsigned int speed)
+{
+	struct rcar_i2c *dev = (struct rcar_i2c *)i2c_dev[adap->hwadapnr];
+	u32 icccr;
+	int ret = 0;
+
+	rcar_i2c_raw_rw_finish(dev);
+
+	icccr = rcar_clock_gen(adap->hwadapnr, speed);
+	if (icccr == 0) {
+		puts("I2C: Init failed\n");
+		ret = -1;
+	} else {
+		writel(icccr, &dev->icccr);
+	}
+	return ret;
+}
+
+/*
+ * Register RCAR i2c adapters
+ */
+U_BOOT_I2C_ADAP_COMPLETE(rcar_0, rcar_i2c_init, rcar_i2c_probe, rcar_i2c_read,
+			 rcar_i2c_write, rcar_i2c_set_bus_speed,
+			 CONFIG_SYS_RCAR_I2C0_SPEED, 0, 0)
+U_BOOT_I2C_ADAP_COMPLETE(rcar_1, rcar_i2c_init, rcar_i2c_probe, rcar_i2c_read,
+			 rcar_i2c_write, rcar_i2c_set_bus_speed,
+			 CONFIG_SYS_RCAR_I2C1_SPEED, 0, 1)
+U_BOOT_I2C_ADAP_COMPLETE(rcar_2, rcar_i2c_init, rcar_i2c_probe, rcar_i2c_read,
+			 rcar_i2c_write, rcar_i2c_set_bus_speed,
+			 CONFIG_SYS_RCAR_I2C2_SPEED, 0, 2)
+U_BOOT_I2C_ADAP_COMPLETE(rcar_3, rcar_i2c_init, rcar_i2c_probe, rcar_i2c_read,
+			 rcar_i2c_write, rcar_i2c_set_bus_speed,
+			 CONFIG_SYS_RCAR_I2C3_SPEED, 0, 3)
diff --git a/drivers/i2c/s3c24x0_i2c.c b/drivers/i2c/s3c24x0_i2c.c
index cd09c788be..fd328f0549 100644
--- a/drivers/i2c/s3c24x0_i2c.c
+++ b/drivers/i2c/s3c24x0_i2c.c
@@ -23,8 +23,6 @@
 #include <i2c.h>
 #include "s3c24x0_i2c.h"
 
-#ifdef CONFIG_HARD_I2C
-
 #define	I2C_WRITE	0
 #define I2C_READ	1
 
@@ -34,6 +32,76 @@
 #define I2C_NOK_LA	3	/* Lost arbitration */
 #define I2C_NOK_TOUT	4	/* time out */
 
+/* HSI2C specific register description */
+
+/* I2C_CTL Register bits */
+#define HSI2C_FUNC_MODE_I2C		(1u << 0)
+#define HSI2C_MASTER			(1u << 3)
+#define HSI2C_RXCHON			(1u << 6)	/* Write/Send */
+#define HSI2C_TXCHON			(1u << 7)	/* Read/Receive */
+#define HSI2C_SW_RST			(1u << 31)
+
+/* I2C_FIFO_CTL Register bits */
+#define HSI2C_RXFIFO_EN			(1u << 0)
+#define HSI2C_TXFIFO_EN			(1u << 1)
+#define HSI2C_TXFIFO_TRIGGER_LEVEL	(0x20 << 16)
+#define HSI2C_RXFIFO_TRIGGER_LEVEL	(0x20 << 4)
+
+/* I2C_TRAILING_CTL Register bits */
+#define HSI2C_TRAILING_COUNT		(0xff)
+
+/* I2C_INT_EN Register bits */
+#define HSI2C_TX_UNDERRUN_EN		(1u << 2)
+#define HSI2C_TX_OVERRUN_EN		(1u << 3)
+#define HSI2C_RX_UNDERRUN_EN		(1u << 4)
+#define HSI2C_RX_OVERRUN_EN		(1u << 5)
+#define HSI2C_INT_TRAILING_EN		(1u << 6)
+#define HSI2C_INT_I2C_EN		(1u << 9)
+
+#define HSI2C_INT_ERROR_MASK	(HSI2C_TX_UNDERRUN_EN |\
+				 HSI2C_TX_OVERRUN_EN  |\
+				 HSI2C_RX_UNDERRUN_EN |\
+				 HSI2C_RX_OVERRUN_EN  |\
+				 HSI2C_INT_TRAILING_EN)
+
+/* I2C_CONF Register bits */
+#define HSI2C_AUTO_MODE			(1u << 31)
+#define HSI2C_10BIT_ADDR_MODE		(1u << 30)
+#define HSI2C_HS_MODE			(1u << 29)
+
+/* I2C_AUTO_CONF Register bits */
+#define HSI2C_READ_WRITE		(1u << 16)
+#define HSI2C_STOP_AFTER_TRANS		(1u << 17)
+#define HSI2C_MASTER_RUN		(1u << 31)
+
+/* I2C_TIMEOUT Register bits */
+#define HSI2C_TIMEOUT_EN		(1u << 31)
+
+/* I2C_TRANS_STATUS register bits */
+#define HSI2C_MASTER_BUSY		(1u << 17)
+#define HSI2C_SLAVE_BUSY		(1u << 16)
+#define HSI2C_TIMEOUT_AUTO		(1u << 4)
+#define HSI2C_NO_DEV			(1u << 3)
+#define HSI2C_NO_DEV_ACK		(1u << 2)
+#define HSI2C_TRANS_ABORT		(1u << 1)
+#define HSI2C_TRANS_SUCCESS		(1u << 0)
+#define HSI2C_TRANS_ERROR_MASK	(HSI2C_TIMEOUT_AUTO |\
+				 HSI2C_NO_DEV | HSI2C_NO_DEV_ACK |\
+				 HSI2C_TRANS_ABORT)
+#define HSI2C_TRANS_FINISHED_MASK (HSI2C_TRANS_ERROR_MASK | HSI2C_TRANS_SUCCESS)
+
+
+/* I2C_FIFO_STAT Register bits */
+#define HSI2C_RX_FIFO_EMPTY		(1u << 24)
+#define HSI2C_RX_FIFO_FULL		(1u << 23)
+#define HSI2C_TX_FIFO_EMPTY		(1u << 8)
+#define HSI2C_TX_FIFO_FULL		(1u << 7)
+#define HSI2C_RX_FIFO_LEVEL(x)		(((x) >> 16) & 0x7f)
+#define HSI2C_TX_FIFO_LEVEL(x)		((x) & 0x7f)
+
+#define HSI2C_SLV_ADDR_MAS(x)		((x & 0x3ff) << 10)
+
+/* S3C I2C Controller bits */
 #define I2CSTAT_BSY	0x20	/* Busy bit */
 #define I2CSTAT_NACK	0x01	/* Nack bit */
 #define I2CCON_ACKGEN	0x80	/* Acknowledge generation */
@@ -43,19 +111,42 @@
 #define I2C_START_STOP	0x20	/* START / STOP */
 #define I2C_TXRX_ENA	0x10	/* I2C Tx/Rx enable */
 
-#define I2C_TIMEOUT 1		/* 1 second */
+#define I2C_TIMEOUT_MS 1000		/* 1 second */
+
+#define	HSI2C_TIMEOUT_US 100000 /* 100 ms, finer granularity */
 
 
+/* To support VCMA9 boards and other who dont define max_i2c_num */
+#ifndef CONFIG_MAX_I2C_NUM
+#define CONFIG_MAX_I2C_NUM 1
+#endif
+
 /*
  * For SPL boot some boards need i2c before SDRAM is initialised so force
  * variables to live in SRAM
  */
-static unsigned int g_current_bus __attribute__((section(".data")));
-#ifdef CONFIG_OF_CONTROL
-static int i2c_busses __attribute__((section(".data")));
 static struct s3c24x0_i2c_bus i2c_bus[CONFIG_MAX_I2C_NUM]
 			__attribute__((section(".data")));
-#endif
+
+/**
+ * Get a pointer to the given bus index
+ *
+ * @bus_idx: Bus index to look up
+ * @return pointer to bus, or NULL if invalid or not available
+ */
+static struct s3c24x0_i2c_bus *get_bus(unsigned int bus_idx)
+{
+	if (bus_idx < ARRAY_SIZE(i2c_bus)) {
+		struct s3c24x0_i2c_bus *bus;
+
+		bus = &i2c_bus[bus_idx];
+		if (bus->active)
+			return bus;
+	}
+
+	debug("Undefined bus: %d\n", bus_idx);
+	return NULL;
+}
 
 #if !(defined CONFIG_EXYNOS4 || defined CONFIG_EXYNOS5)
 static int GetI2CSDA(void)
@@ -84,22 +175,75 @@ static void SetI2CSCL(int x)
 }
 #endif
 
+/*
+ * Wait til the byte transfer is completed.
+ *
+ * @param i2c- pointer to the appropriate i2c register bank.
+ * @return I2C_OK, if transmission was ACKED
+ *         I2C_NACK, if transmission was NACKED
+ *         I2C_NOK_TIMEOUT, if transaction did not complete in I2C_TIMEOUT_MS
+ */
+
 static int WaitForXfer(struct s3c24x0_i2c *i2c)
 {
-	int i;
+	ulong start_time = get_timer(0);
 
-	i = I2C_TIMEOUT * 10000;
-	while (!(readl(&i2c->iiccon) & I2CCON_IRPND) && (i > 0)) {
-		udelay(100);
-		i--;
-	}
+	do {
+		if (readl(&i2c->iiccon) & I2CCON_IRPND)
+			return (readl(&i2c->iicstat) & I2CSTAT_NACK) ?
+				I2C_NACK : I2C_OK;
+	} while (get_timer(start_time) < I2C_TIMEOUT_MS);
 
-	return (readl(&i2c->iiccon) & I2CCON_IRPND) ? I2C_OK : I2C_NOK_TOUT;
+	return I2C_NOK_TOUT;
 }
 
-static int IsACK(struct s3c24x0_i2c *i2c)
+/*
+ * Wait for transfer completion.
+ *
+ * This function reads the interrupt status register waiting for the INT_I2C
+ * bit to be set, which indicates copletion of a transaction.
+ *
+ * @param i2c: pointer to the appropriate register bank
+ *
+ * @return: I2C_OK in case of successful completion, I2C_NOK_TIMEOUT in case
+ *          the status bits do not get set in time, or an approrpiate error
+ *          value in case of transfer errors.
+ */
+static int hsi2c_wait_for_trx(struct exynos5_hsi2c *i2c)
 {
-	return !(readl(&i2c->iicstat) & I2CSTAT_NACK);
+	int i = HSI2C_TIMEOUT_US;
+
+	while (i-- > 0) {
+		u32 int_status = readl(&i2c->usi_int_stat);
+
+		if (int_status & HSI2C_INT_I2C_EN) {
+			u32 trans_status = readl(&i2c->usi_trans_status);
+
+			/* Deassert pending interrupt. */
+			writel(int_status, &i2c->usi_int_stat);
+
+			if (trans_status & HSI2C_NO_DEV_ACK) {
+				debug("%s: no ACK from device\n", __func__);
+				return I2C_NACK;
+			}
+			if (trans_status & HSI2C_NO_DEV) {
+				debug("%s: no device\n", __func__);
+				return I2C_NOK;
+			}
+			if (trans_status & HSI2C_TRANS_ABORT) {
+				debug("%s: arbitration lost\n", __func__);
+				return I2C_NOK_LA;
+			}
+			if (trans_status & HSI2C_TIMEOUT_AUTO) {
+				debug("%s: device timed out\n", __func__);
+				return I2C_NOK_TOUT;
+			}
+			return I2C_OK;
+		}
+		udelay(1);
+	}
+	debug("%s: transaction timeout!\n", __func__);
+	return I2C_NOK_TOUT;
 }
 
 static void ReadWriteByte(struct s3c24x0_i2c *i2c)
@@ -107,17 +251,17 @@ static void ReadWriteByte(struct s3c24x0_i2c *i2c)
 	writel(readl(&i2c->iiccon) & ~I2CCON_IRPND, &i2c->iiccon);
 }
 
-static struct s3c24x0_i2c *get_base_i2c(void)
+static struct s3c24x0_i2c *get_base_i2c(int bus)
 {
 #ifdef CONFIG_EXYNOS4
 	struct s3c24x0_i2c *i2c = (struct s3c24x0_i2c *)(samsung_get_base_i2c()
 							+ (EXYNOS4_I2C_SPACING
-							* g_current_bus));
+							* bus));
 	return i2c;
 #elif defined CONFIG_EXYNOS5
 	struct s3c24x0_i2c *i2c = (struct s3c24x0_i2c *)(samsung_get_base_i2c()
 							+ (EXYNOS5_I2C_SPACING
-							* g_current_bus));
+							* bus));
 	return i2c;
 #else
 	return s3c24x0_get_base_i2c();
@@ -151,53 +295,137 @@ static void i2c_ch_init(struct s3c24x0_i2c *i2c, int speed, int slaveadd)
 	writel(I2C_MODE_MT | I2C_TXRX_ENA, &i2c->iicstat);
 }
 
-/*
- * MULTI BUS I2C support
- */
-
-#ifdef CONFIG_I2C_MULTI_BUS
-int i2c_set_bus_num(unsigned int bus)
+static int hsi2c_get_clk_details(struct s3c24x0_i2c_bus *i2c_bus)
 {
-	struct s3c24x0_i2c *i2c;
+	struct exynos5_hsi2c *hsregs = i2c_bus->hsregs;
+	ulong clkin;
+	unsigned int op_clk = i2c_bus->clock_frequency;
+	unsigned int i = 0, utemp0 = 0, utemp1 = 0;
+	unsigned int t_ftl_cycle;
 
-	if ((bus < 0) || (bus >= CONFIG_MAX_I2C_NUM)) {
-		debug("Bad bus: %d\n", bus);
-		return -1;
+#if (defined CONFIG_EXYNOS4 || defined CONFIG_EXYNOS5)
+	clkin = get_i2c_clk();
+#else
+	clkin = get_PCLK();
+#endif
+	/* FPCLK / FI2C =
+	 * (CLK_DIV + 1) * (TSCLK_L + TSCLK_H + 2) + 8 + 2 * FLT_CYCLE
+	 * uTemp0 = (CLK_DIV + 1) * (TSCLK_L + TSCLK_H + 2)
+	 * uTemp1 = (TSCLK_L + TSCLK_H + 2)
+	 * uTemp2 = TSCLK_L + TSCLK_H
+	 */
+	t_ftl_cycle = (readl(&hsregs->usi_conf) >> 16) & 0x7;
+	utemp0 = (clkin / op_clk) - 8 - 2 * t_ftl_cycle;
+
+	/* CLK_DIV max is 256 */
+	for (i = 0; i < 256; i++) {
+		utemp1 = utemp0 / (i + 1);
+		if ((utemp1 < 512) && (utemp1 > 4)) {
+			i2c_bus->clk_cycle = utemp1 - 2;
+			i2c_bus->clk_div = i;
+			return 0;
+		}
 	}
+	return -1;
+}
 
-	g_current_bus = bus;
-	i2c = get_base_i2c();
-	i2c_ch_init(i2c, CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
-
-	return 0;
+static void hsi2c_ch_init(struct s3c24x0_i2c_bus *i2c_bus)
+{
+	struct exynos5_hsi2c *hsregs = i2c_bus->hsregs;
+	unsigned int t_sr_release;
+	unsigned int n_clkdiv;
+	unsigned int t_start_su, t_start_hd;
+	unsigned int t_stop_su;
+	unsigned int t_data_su, t_data_hd;
+	unsigned int t_scl_l, t_scl_h;
+	u32 i2c_timing_s1;
+	u32 i2c_timing_s2;
+	u32 i2c_timing_s3;
+	u32 i2c_timing_sla;
+
+	n_clkdiv = i2c_bus->clk_div;
+	t_scl_l = i2c_bus->clk_cycle / 2;
+	t_scl_h = i2c_bus->clk_cycle / 2;
+	t_start_su = t_scl_l;
+	t_start_hd = t_scl_l;
+	t_stop_su = t_scl_l;
+	t_data_su = t_scl_l / 2;
+	t_data_hd = t_scl_l / 2;
+	t_sr_release = i2c_bus->clk_cycle;
+
+	i2c_timing_s1 = t_start_su << 24 | t_start_hd << 16 | t_stop_su << 8;
+	i2c_timing_s2 = t_data_su << 24 | t_scl_l << 8 | t_scl_h << 0;
+	i2c_timing_s3 = n_clkdiv << 16 | t_sr_release << 0;
+	i2c_timing_sla = t_data_hd << 0;
+
+	writel(HSI2C_TRAILING_COUNT, &hsregs->usi_trailing_ctl);
+
+	/* Clear to enable Timeout */
+	clrsetbits_le32(&hsregs->usi_timeout, HSI2C_TIMEOUT_EN, 0);
+
+	/* set AUTO mode */
+	writel(readl(&hsregs->usi_conf) | HSI2C_AUTO_MODE, &hsregs->usi_conf);
+
+	/* Enable completion conditions' reporting. */
+	writel(HSI2C_INT_I2C_EN, &hsregs->usi_int_en);
+
+	/* Enable FIFOs */
+	writel(HSI2C_RXFIFO_EN | HSI2C_TXFIFO_EN, &hsregs->usi_fifo_ctl);
+
+	/* Currently operating in Fast speed mode. */
+	writel(i2c_timing_s1, &hsregs->usi_timing_fs1);
+	writel(i2c_timing_s2, &hsregs->usi_timing_fs2);
+	writel(i2c_timing_s3, &hsregs->usi_timing_fs3);
+	writel(i2c_timing_sla, &hsregs->usi_timing_sla);
 }
 
-unsigned int i2c_get_bus_num(void)
+/* SW reset for the high speed bus */
+static void exynos5_i2c_reset(struct s3c24x0_i2c_bus *i2c_bus)
 {
-	return g_current_bus;
+	struct exynos5_hsi2c *i2c = i2c_bus->hsregs;
+	u32 i2c_ctl;
+
+	/* Set and clear the bit for reset */
+	i2c_ctl = readl(&i2c->usi_ctl);
+	i2c_ctl |= HSI2C_SW_RST;
+	writel(i2c_ctl, &i2c->usi_ctl);
+
+	i2c_ctl = readl(&i2c->usi_ctl);
+	i2c_ctl &= ~HSI2C_SW_RST;
+	writel(i2c_ctl, &i2c->usi_ctl);
+
+	/* Initialize the configure registers */
+	hsi2c_ch_init(i2c_bus);
 }
-#endif
 
-void i2c_init(int speed, int slaveadd)
+static void s3c24x0_i2c_init(struct i2c_adapter *adap, int speed, int slaveadd)
 {
 	struct s3c24x0_i2c *i2c;
+	struct s3c24x0_i2c_bus *bus;
+
 #if !(defined CONFIG_EXYNOS4 || defined CONFIG_EXYNOS5)
 	struct s3c24x0_gpio *gpio = s3c24x0_get_base_gpio();
 #endif
-	int i;
+	ulong start_time = get_timer(0);
 
 	/* By default i2c channel 0 is the current bus */
-	g_current_bus = 0;
-	i2c = get_base_i2c();
+	i2c = get_base_i2c(adap->hwadapnr);
 
-	/* wait for some time to give previous transfer a chance to finish */
-	i = I2C_TIMEOUT * 1000;
-	while ((readl(&i2c->iicstat) & I2CSTAT_BSY) && (i > 0)) {
-		udelay(1000);
-		i--;
+	/*
+	 * In case the previous transfer is still going, wait to give it a
+	 * chance to finish.
+	 */
+	while (readl(&i2c->iicstat) & I2CSTAT_BSY) {
+		if (get_timer(start_time) > I2C_TIMEOUT_MS) {
+			printf("%s: I2C bus busy for %p\n", __func__,
+			       &i2c->iicstat);
+			return;
+		}
 	}
 
 #if !(defined CONFIG_EXYNOS4 || defined CONFIG_EXYNOS5)
+	int i;
+
 	if ((readl(&i2c->iicstat) & I2CSTAT_BSY) || GetI2CSDA() == 0) {
 #ifdef CONFIG_S3C2410
 		ulong old_gpecon = readl(&gpio->gpecon);
@@ -243,8 +471,267 @@ void i2c_init(int speed, int slaveadd)
 	}
 #endif /* #if !(defined CONFIG_EXYNOS4 || defined CONFIG_EXYNOS5) */
 	i2c_ch_init(i2c, speed, slaveadd);
+
+	bus = &i2c_bus[adap->hwadapnr];
+	bus->active = true;
+	bus->regs = i2c;
+}
+
+/*
+ * Poll the appropriate bit of the fifo status register until the interface is
+ * ready to process the next byte or timeout expires.
+ *
+ * In addition to the FIFO status register this function also polls the
+ * interrupt status register to be able to detect unexpected transaction
+ * completion.
+ *
+ * When FIFO is ready to process the next byte, this function returns I2C_OK.
+ * If in course of polling the INT_I2C assertion is detected, the function
+ * returns I2C_NOK. If timeout happens before any of the above conditions is
+ * met - the function returns I2C_NOK_TOUT;
+
+ * @param i2c: pointer to the appropriate i2c register bank.
+ * @param rx_transfer: set to True if the receive transaction is in progress.
+ * @return: as described above.
+ */
+static unsigned hsi2c_poll_fifo(struct exynos5_hsi2c *i2c, bool rx_transfer)
+{
+	u32 fifo_bit = rx_transfer ? HSI2C_RX_FIFO_EMPTY : HSI2C_TX_FIFO_FULL;
+	int i = HSI2C_TIMEOUT_US;
+
+	while (readl(&i2c->usi_fifo_stat) & fifo_bit) {
+		if (readl(&i2c->usi_int_stat) & HSI2C_INT_I2C_EN) {
+			/*
+			 * There is a chance that assertion of
+			 * HSI2C_INT_I2C_EN and deassertion of
+			 * HSI2C_RX_FIFO_EMPTY happen simultaneously. Let's
+			 * give FIFO status priority and check it one more
+			 * time before reporting interrupt. The interrupt will
+			 * be reported next time this function is called.
+			 */
+			if (rx_transfer &&
+			    !(readl(&i2c->usi_fifo_stat) & fifo_bit))
+				break;
+			return I2C_NOK;
+		}
+		if (!i--) {
+			debug("%s: FIFO polling timeout!\n", __func__);
+			return I2C_NOK_TOUT;
+		}
+		udelay(1);
+	}
+	return I2C_OK;
+}
+
+/*
+ * Preapre hsi2c transaction, either read or write.
+ *
+ * Set up transfer as described in section 27.5.1.2 'I2C Channel Auto Mode' of
+ * the 5420 UM.
+ *
+ * @param i2c: pointer to the appropriate i2c register bank.
+ * @param chip: slave address on the i2c bus (with read/write bit exlcuded)
+ * @param len: number of bytes expected to be sent or received
+ * @param rx_transfer: set to true for receive transactions
+ * @param: issue_stop: set to true if i2c stop condition should be generated
+ *         after this transaction.
+ * @return: I2C_NOK_TOUT in case the bus remained busy for HSI2C_TIMEOUT_US,
+ *          I2C_OK otherwise.
+ */
+static int hsi2c_prepare_transaction(struct exynos5_hsi2c *i2c,
+				     u8 chip,
+				     u16 len,
+				     bool rx_transfer,
+				     bool issue_stop)
+{
+	u32 conf;
+
+	conf = len | HSI2C_MASTER_RUN;
+
+	if (issue_stop)
+		conf |= HSI2C_STOP_AFTER_TRANS;
+
+	/* Clear to enable Timeout */
+	writel(readl(&i2c->usi_timeout) & ~HSI2C_TIMEOUT_EN, &i2c->usi_timeout);
+
+	/* Set slave address */
+	writel(HSI2C_SLV_ADDR_MAS(chip), &i2c->i2c_addr);
+
+	if (rx_transfer) {
+		/* i2c master, read transaction */
+		writel((HSI2C_RXCHON | HSI2C_FUNC_MODE_I2C | HSI2C_MASTER),
+		       &i2c->usi_ctl);
+
+		/* read up to len bytes, stop after transaction is finished */
+		writel(conf | HSI2C_READ_WRITE, &i2c->usi_auto_conf);
+	} else {
+		/* i2c master, write transaction */
+		writel((HSI2C_TXCHON | HSI2C_FUNC_MODE_I2C | HSI2C_MASTER),
+		       &i2c->usi_ctl);
+
+		/* write up to len bytes, stop after transaction is finished */
+		writel(conf, &i2c->usi_auto_conf);
+	}
+
+	/* Reset all pending interrupt status bits we care about, if any */
+	writel(HSI2C_INT_I2C_EN, &i2c->usi_int_stat);
+
+	return I2C_OK;
+}
+
+/*
+ * Wait while i2c bus is settling down (mostly stop gets completed).
+ */
+static int hsi2c_wait_while_busy(struct exynos5_hsi2c *i2c)
+{
+	int i = HSI2C_TIMEOUT_US;
+
+	while (readl(&i2c->usi_trans_status) & HSI2C_MASTER_BUSY) {
+		if (!i--) {
+			debug("%s: bus busy\n", __func__);
+			return I2C_NOK_TOUT;
+		}
+		udelay(1);
+	}
+	return I2C_OK;
+}
+
+static int hsi2c_write(struct exynos5_hsi2c *i2c,
+		       unsigned char chip,
+		       unsigned char addr[],
+		       unsigned char alen,
+		       unsigned char data[],
+		       unsigned short len,
+		       bool issue_stop)
+{
+	int i, rv = 0;
+
+	if (!(len + alen)) {
+		/* Writes of zero length not supported in auto mode. */
+		debug("%s: zero length writes not supported\n", __func__);
+		return I2C_NOK;
+	}
+
+	rv = hsi2c_prepare_transaction
+		(i2c, chip, len + alen, false, issue_stop);
+	if (rv != I2C_OK)
+		return rv;
+
+	/* Move address, if any, and the data, if any, into the FIFO. */
+	for (i = 0; i < alen; i++) {
+		rv = hsi2c_poll_fifo(i2c, false);
+		if (rv != I2C_OK) {
+			debug("%s: address write failed\n", __func__);
+			goto write_error;
+		}
+		writel(addr[i], &i2c->usi_txdata);
+	}
+
+	for (i = 0; i < len; i++) {
+		rv = hsi2c_poll_fifo(i2c, false);
+		if (rv != I2C_OK) {
+			debug("%s: data write failed\n", __func__);
+			goto write_error;
+		}
+		writel(data[i], &i2c->usi_txdata);
+	}
+
+	rv = hsi2c_wait_for_trx(i2c);
+
+ write_error:
+	if (issue_stop) {
+		int tmp_ret = hsi2c_wait_while_busy(i2c);
+		if (rv == I2C_OK)
+			rv = tmp_ret;
+	}
+
+	writel(HSI2C_FUNC_MODE_I2C, &i2c->usi_ctl); /* done */
+	return rv;
 }
 
+static int hsi2c_read(struct exynos5_hsi2c *i2c,
+		      unsigned char chip,
+		      unsigned char addr[],
+		      unsigned char alen,
+		      unsigned char data[],
+		      unsigned short len)
+{
+	int i, rv, tmp_ret;
+	bool drop_data = false;
+
+	if (!len) {
+		/* Reads of zero length not supported in auto mode. */
+		debug("%s: zero length read adjusted\n", __func__);
+		drop_data = true;
+		len = 1;
+	}
+
+	if (alen) {
+		/* Internal register adress needs to be written first. */
+		rv = hsi2c_write(i2c, chip, addr, alen, NULL, 0, false);
+		if (rv != I2C_OK)
+			return rv;
+	}
+
+	rv = hsi2c_prepare_transaction(i2c, chip, len, true, true);
+
+	if (rv != I2C_OK)
+		return rv;
+
+	for (i = 0; i < len; i++) {
+		rv = hsi2c_poll_fifo(i2c, true);
+		if (rv != I2C_OK)
+			goto read_err;
+		if (drop_data)
+			continue;
+		data[i] = readl(&i2c->usi_rxdata);
+	}
+
+	rv = hsi2c_wait_for_trx(i2c);
+
+ read_err:
+	tmp_ret = hsi2c_wait_while_busy(i2c);
+	if (rv == I2C_OK)
+		rv = tmp_ret;
+
+	writel(HSI2C_FUNC_MODE_I2C, &i2c->usi_ctl); /* done */
+	return rv;
+}
+
+static unsigned int s3c24x0_i2c_set_bus_speed(struct i2c_adapter *adap,
+					  unsigned int speed)
+{
+	struct s3c24x0_i2c_bus *i2c_bus;
+
+	i2c_bus = get_bus(adap->hwadapnr);
+	if (!i2c_bus)
+		return -1;
+
+	i2c_bus->clock_frequency = speed;
+
+	if (i2c_bus->is_highspeed) {
+		if (hsi2c_get_clk_details(i2c_bus))
+			return -1;
+		hsi2c_ch_init(i2c_bus);
+	} else {
+		i2c_ch_init(i2c_bus->regs, i2c_bus->clock_frequency,
+			    CONFIG_SYS_I2C_S3C24X0_SLAVE);
+	}
+
+	return 0;
+}
+
+#ifdef CONFIG_EXYNOS5
+static void exynos_i2c_init(struct i2c_adapter *adap, int speed, int slaveaddr)
+{
+	/* This will override the speed selected in the fdt for that port */
+	debug("i2c_init(speed=%u, slaveaddr=0x%x)\n", speed, slaveaddr);
+	if (i2c_set_bus_speed(speed))
+		printf("i2c_init: failed to init bus %d for speed = %d\n",
+						adap->hwadapnr, speed);
+}
+#endif
+
 /*
  * cmd_type is 0 for write, 1 for read.
  *
@@ -260,7 +747,8 @@ static int i2c_transfer(struct s3c24x0_i2c *i2c,
 			unsigned char data[],
 			unsigned short data_len)
 {
-	int i, result;
+	int i = 0, result;
+	ulong start_time = get_timer(0);
 
 	if (data == 0 || data_len == 0) {
 		/*Don't support data transfer of no length or to address 0 */
@@ -268,128 +756,78 @@ static int i2c_transfer(struct s3c24x0_i2c *i2c,
 		return I2C_NOK;
 	}
 
-	/* Check I2C bus idle */
-	i = I2C_TIMEOUT * 1000;
-	while ((readl(&i2c->iicstat) & I2CSTAT_BSY) && (i > 0)) {
-		udelay(1000);
-		i--;
+	while (readl(&i2c->iicstat) & I2CSTAT_BSY) {
+		if (get_timer(start_time) > I2C_TIMEOUT_MS)
+			return I2C_NOK_TOUT;
 	}
 
-	if (readl(&i2c->iicstat) & I2CSTAT_BSY)
-		return I2C_NOK_TOUT;
-
 	writel(readl(&i2c->iiccon) | I2CCON_ACKGEN, &i2c->iiccon);
-	result = I2C_OK;
 
-	switch (cmd_type) {
-	case I2C_WRITE:
-		if (addr && addr_len) {
-			writel(chip, &i2c->iicds);
-			/* send START */
-			writel(I2C_MODE_MT | I2C_TXRX_ENA | I2C_START_STOP,
-			       &i2c->iicstat);
-			i = 0;
-			while ((i < addr_len) && (result == I2C_OK)) {
-				result = WaitForXfer(i2c);
-				writel(addr[i], &i2c->iicds);
-				ReadWriteByte(i2c);
-				i++;
-			}
-			i = 0;
-			while ((i < data_len) && (result == I2C_OK)) {
-				result = WaitForXfer(i2c);
-				writel(data[i], &i2c->iicds);
-				ReadWriteByte(i2c);
-				i++;
-			}
-		} else {
-			writel(chip, &i2c->iicds);
-			/* send START */
-			writel(I2C_MODE_MT | I2C_TXRX_ENA | I2C_START_STOP,
-			       &i2c->iicstat);
-			i = 0;
-			while ((i < data_len) && (result == I2C_OK)) {
-				result = WaitForXfer(i2c);
-				writel(data[i], &i2c->iicds);
-				ReadWriteByte(i2c);
-				i++;
-			}
+	/* Get the slave chip address going */
+	writel(chip, &i2c->iicds);
+	if ((cmd_type == I2C_WRITE) || (addr && addr_len))
+		writel(I2C_MODE_MT | I2C_TXRX_ENA | I2C_START_STOP,
+		       &i2c->iicstat);
+	else
+		writel(I2C_MODE_MR | I2C_TXRX_ENA | I2C_START_STOP,
+		       &i2c->iicstat);
+
+	/* Wait for chip address to transmit. */
+	result = WaitForXfer(i2c);
+	if (result != I2C_OK)
+		goto bailout;
+
+	/* If register address needs to be transmitted - do it now. */
+	if (addr && addr_len) {
+		while ((i < addr_len) && (result == I2C_OK)) {
+			writel(addr[i++], &i2c->iicds);
+			ReadWriteByte(i2c);
+			result = WaitForXfer(i2c);
 		}
+		i = 0;
+		if (result != I2C_OK)
+			goto bailout;
+	}
 
-		if (result == I2C_OK)
+	switch (cmd_type) {
+	case I2C_WRITE:
+		while ((i < data_len) && (result == I2C_OK)) {
+			writel(data[i++], &i2c->iicds);
+			ReadWriteByte(i2c);
 			result = WaitForXfer(i2c);
-
-		/* send STOP */
-		writel(I2C_MODE_MT | I2C_TXRX_ENA, &i2c->iicstat);
-		ReadWriteByte(i2c);
+		}
 		break;
 
 	case I2C_READ:
 		if (addr && addr_len) {
+			/*
+			 * Register address has been sent, now send slave chip
+			 * address again to start the actual read transaction.
+			 */
 			writel(chip, &i2c->iicds);
-			/* send START */
-			writel(I2C_MODE_MT | I2C_TXRX_ENA | I2C_START_STOP,
-				&i2c->iicstat);
-			result = WaitForXfer(i2c);
-			if (IsACK(i2c)) {
-				i = 0;
-				while ((i < addr_len) && (result == I2C_OK)) {
-					writel(addr[i], &i2c->iicds);
-					ReadWriteByte(i2c);
-					result = WaitForXfer(i2c);
-					i++;
-				}
-
-				writel(chip, &i2c->iicds);
-				/* resend START */
-				writel(I2C_MODE_MR | I2C_TXRX_ENA |
-				       I2C_START_STOP, &i2c->iicstat);
-			ReadWriteByte(i2c);
-			result = WaitForXfer(i2c);
-				i = 0;
-				while ((i < data_len) && (result == I2C_OK)) {
-					/* disable ACK for final READ */
-					if (i == data_len - 1)
-						writel(readl(&i2c->iiccon)
-							& ~I2CCON_ACKGEN,
-							&i2c->iiccon);
-				ReadWriteByte(i2c);
-				result = WaitForXfer(i2c);
-					data[i] = readl(&i2c->iicds);
-					i++;
-				}
-			} else {
-				result = I2C_NACK;
-			}
 
-		} else {
-			writel(chip, &i2c->iicds);
-			/* send START */
+			/* Generate a re-START. */
 			writel(I2C_MODE_MR | I2C_TXRX_ENA | I2C_START_STOP,
 				&i2c->iicstat);
+			ReadWriteByte(i2c);
 			result = WaitForXfer(i2c);
 
-			if (IsACK(i2c)) {
-				i = 0;
-				while ((i < data_len) && (result == I2C_OK)) {
-					/* disable ACK for final READ */
-					if (i == data_len - 1)
-						writel(readl(&i2c->iiccon) &
-							~I2CCON_ACKGEN,
-							&i2c->iiccon);
-					ReadWriteByte(i2c);
-					result = WaitForXfer(i2c);
-					data[i] = readl(&i2c->iicds);
-					i++;
-				}
-			} else {
-				result = I2C_NACK;
-			}
+			if (result != I2C_OK)
+				goto bailout;
 		}
 
-		/* send STOP */
-		writel(I2C_MODE_MR | I2C_TXRX_ENA, &i2c->iicstat);
-		ReadWriteByte(i2c);
+		while ((i < data_len) && (result == I2C_OK)) {
+			/* disable ACK for final READ */
+			if (i == data_len - 1)
+				writel(readl(&i2c->iiccon)
+				       & ~I2CCON_ACKGEN,
+				       &i2c->iiccon);
+			ReadWriteByte(i2c);
+			result = WaitForXfer(i2c);
+			data[i++] = readl(&i2c->iicds);
+		}
+		if (result == I2C_NACK)
+			result = I2C_OK; /* Normal terminated read. */
 		break;
 
 	default:
@@ -398,15 +836,23 @@ static int i2c_transfer(struct s3c24x0_i2c *i2c,
 		break;
 	}
 
+bailout:
+	/* Send STOP. */
+	writel(I2C_MODE_MR | I2C_TXRX_ENA, &i2c->iicstat);
+	ReadWriteByte(i2c);
+
 	return result;
 }
 
-int i2c_probe(uchar chip)
+static int s3c24x0_i2c_probe(struct i2c_adapter *adap, uchar chip)
 {
-	struct s3c24x0_i2c *i2c;
+	struct s3c24x0_i2c_bus *i2c_bus;
 	uchar buf[1];
+	int ret;
 
-	i2c = get_base_i2c();
+	i2c_bus = get_bus(adap->hwadapnr);
+	if (!i2c_bus)
+		return -1;
 	buf[0] = 0;
 
 	/*
@@ -414,12 +860,21 @@ int i2c_probe(uchar chip)
 	 * address was <ACK>ed (i.e. there was a chip at that address which
 	 * drove the data line low).
 	 */
-	return i2c_transfer(i2c, I2C_READ, chip << 1, 0, 0, buf, 1) != I2C_OK;
+	if (i2c_bus->is_highspeed) {
+		ret = hsi2c_read(i2c_bus->hsregs,
+				chip, 0, 0, buf, 1);
+	} else {
+		ret = i2c_transfer(i2c_bus->regs,
+				I2C_READ, chip << 1, 0, 0, buf, 1);
+	}
+
+	return ret != I2C_OK;
 }
 
-int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len)
+static int s3c24x0_i2c_read(struct i2c_adapter *adap, uchar chip, uint addr,
+			    int alen, uchar *buffer, int len)
 {
-	struct s3c24x0_i2c *i2c;
+	struct s3c24x0_i2c_bus *i2c_bus;
 	uchar xaddr[4];
 	int ret;
 
@@ -451,20 +906,32 @@ int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len)
 		chip |= ((addr >> (alen * 8)) &
 			 CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW);
 #endif
-	i2c = get_base_i2c();
-	ret = i2c_transfer(i2c, I2C_READ, chip << 1, &xaddr[4 - alen], alen,
-			buffer, len);
-	if (ret != 0) {
-		debug("I2c read: failed %d\n", ret);
+	i2c_bus = get_bus(adap->hwadapnr);
+	if (!i2c_bus)
+		return -1;
+
+	if (i2c_bus->is_highspeed)
+		ret = hsi2c_read(i2c_bus->hsregs, chip, &xaddr[4 - alen],
+				 alen, buffer, len);
+	else
+		ret = i2c_transfer(i2c_bus->regs, I2C_READ, chip << 1,
+				&xaddr[4 - alen], alen, buffer, len);
+
+	if (ret) {
+		if (i2c_bus->is_highspeed)
+			exynos5_i2c_reset(i2c_bus);
+		debug("I2c read failed %d\n", ret);
 		return 1;
 	}
 	return 0;
 }
 
-int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len)
+static int s3c24x0_i2c_write(struct i2c_adapter *adap, uchar chip, uint addr,
+			 int alen, uchar *buffer, int len)
 {
-	struct s3c24x0_i2c *i2c;
+	struct s3c24x0_i2c_bus *i2c_bus;
 	uchar xaddr[4];
+	int ret;
 
 	if (alen > 4) {
 		debug("I2C write: addr len %d not supported\n", alen);
@@ -493,53 +960,87 @@ int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len)
 		chip |= ((addr >> (alen * 8)) &
 			 CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW);
 #endif
-	i2c = get_base_i2c();
-	return (i2c_transfer
-		(i2c, I2C_WRITE, chip << 1, &xaddr[4 - alen], alen, buffer,
-		 len) != 0);
+	i2c_bus = get_bus(adap->hwadapnr);
+	if (!i2c_bus)
+		return -1;
+
+	if (i2c_bus->is_highspeed)
+		ret = hsi2c_write(i2c_bus->hsregs, chip, &xaddr[4 - alen],
+				  alen, buffer, len, true);
+	else
+		ret = i2c_transfer(i2c_bus->regs, I2C_WRITE, chip << 1,
+				&xaddr[4 - alen], alen, buffer, len);
+
+	if (ret != 0) {
+		if (i2c_bus->is_highspeed)
+			exynos5_i2c_reset(i2c_bus);
+		return 1;
+	} else {
+		return 0;
+	}
 }
 
 #ifdef CONFIG_OF_CONTROL
-void board_i2c_init(const void *blob)
+static void process_nodes(const void *blob, int node_list[], int count,
+			 int is_highspeed)
 {
+	struct s3c24x0_i2c_bus *bus;
 	int i;
-	int node_list[CONFIG_MAX_I2C_NUM];
-	int count;
-
-	count = fdtdec_find_aliases_for_id(blob, "i2c",
-		COMPAT_SAMSUNG_S3C2440_I2C, node_list,
-		CONFIG_MAX_I2C_NUM);
 
 	for (i = 0; i < count; i++) {
-		struct s3c24x0_i2c_bus *bus;
 		int node = node_list[i];
 
 		if (node <= 0)
 			continue;
+
 		bus = &i2c_bus[i];
-		bus->regs = (struct s3c24x0_i2c *)
-			fdtdec_get_addr(blob, node, "reg");
+		bus->active = true;
+		bus->is_highspeed = is_highspeed;
+
+		if (is_highspeed)
+			bus->hsregs = (struct exynos5_hsi2c *)
+					fdtdec_get_addr(blob, node, "reg");
+		else
+			bus->regs = (struct s3c24x0_i2c *)
+					fdtdec_get_addr(blob, node, "reg");
+
 		bus->id = pinmux_decode_periph_id(blob, node);
+		bus->clock_frequency = fdtdec_get_int(blob, node,
+						"clock-frequency",
+						CONFIG_SYS_I2C_S3C24X0_SPEED);
 		bus->node = node;
-		bus->bus_num = i2c_busses++;
+		bus->bus_num = i;
 		exynos_pinmux_config(bus->id, 0);
+
+		/* Mark position as used */
+		node_list[i] = -1;
 	}
 }
 
-static struct s3c24x0_i2c_bus *get_bus(unsigned int bus_idx)
+void board_i2c_init(const void *blob)
 {
-	if (bus_idx < i2c_busses)
-		return &i2c_bus[bus_idx];
+	int node_list[CONFIG_MAX_I2C_NUM];
+	int count;
+
+	/* First get the normal i2c ports */
+	count = fdtdec_find_aliases_for_id(blob, "i2c",
+		COMPAT_SAMSUNG_S3C2440_I2C, node_list,
+		CONFIG_MAX_I2C_NUM);
+	process_nodes(blob, node_list, count, 0);
+
+	/* Now look for high speed i2c ports */
+	count = fdtdec_find_aliases_for_id(blob, "i2c",
+		COMPAT_SAMSUNG_EXYNOS5_I2C, node_list,
+		CONFIG_MAX_I2C_NUM);
+	process_nodes(blob, node_list, count, 1);
 
-	debug("Undefined bus: %d\n", bus_idx);
-	return NULL;
 }
 
 int i2c_get_bus_num_fdt(int node)
 {
 	int i;
 
-	for (i = 0; i < i2c_busses; i++) {
+	for (i = 0; i < ARRAY_SIZE(i2c_bus); i++) {
 		if (node == i2c_bus[i].node)
 			return i;
 	}
@@ -550,7 +1051,7 @@ int i2c_get_bus_num_fdt(int node)
 
 int i2c_reset_port_fdt(const void *blob, int node)
 {
-	struct s3c24x0_i2c_bus *i2c;
+	struct s3c24x0_i2c_bus *i2c_bus;
 	int bus;
 
 	bus = i2c_get_bus_num_fdt(node);
@@ -559,16 +1060,190 @@ int i2c_reset_port_fdt(const void *blob, int node)
 		return -1;
 	}
 
-	i2c = get_bus(bus);
-	if (!i2c) {
+	i2c_bus = get_bus(bus);
+	if (!i2c_bus) {
 		debug("get_bus() failed for node node %d\n", node);
 		return -1;
 	}
 
-	i2c_ch_init(i2c->regs, CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
+	if (i2c_bus->is_highspeed) {
+		if (hsi2c_get_clk_details(i2c_bus))
+			return -1;
+		hsi2c_ch_init(i2c_bus);
+	} else {
+		i2c_ch_init(i2c_bus->regs, i2c_bus->clock_frequency,
+			    CONFIG_SYS_I2C_S3C24X0_SLAVE);
+	}
 
 	return 0;
 }
 #endif
 
-#endif /* CONFIG_HARD_I2C */
+/*
+ * Register s3c24x0 i2c adapters
+ */
+#if defined(CONFIG_EXYNOS5420)
+U_BOOT_I2C_ADAP_COMPLETE(i2c00, s3c24x0_i2c_init, s3c24x0_i2c_probe,
+			s3c24x0_i2c_read, s3c24x0_i2c_write,
+			s3c24x0_i2c_set_bus_speed,
+			CONFIG_SYS_I2C_S3C24X0_SPEED,
+			CONFIG_SYS_I2C_S3C24X0_SLAVE, 0)
+U_BOOT_I2C_ADAP_COMPLETE(i2c01, s3c24x0_i2c_init, s3c24x0_i2c_probe,
+			s3c24x0_i2c_read, s3c24x0_i2c_write,
+			s3c24x0_i2c_set_bus_speed,
+			CONFIG_SYS_I2C_S3C24X0_SPEED,
+			CONFIG_SYS_I2C_S3C24X0_SLAVE, 1)
+U_BOOT_I2C_ADAP_COMPLETE(i2c02, s3c24x0_i2c_init, s3c24x0_i2c_probe,
+			s3c24x0_i2c_read, s3c24x0_i2c_write,
+			s3c24x0_i2c_set_bus_speed,
+			CONFIG_SYS_I2C_S3C24X0_SPEED,
+			CONFIG_SYS_I2C_S3C24X0_SLAVE, 2)
+U_BOOT_I2C_ADAP_COMPLETE(i2c03, exynos_i2c_init, s3c24x0_i2c_probe,
+			s3c24x0_i2c_read, s3c24x0_i2c_write,
+			s3c24x0_i2c_set_bus_speed,
+			CONFIG_SYS_I2C_S3C24X0_SPEED,
+			CONFIG_SYS_I2C_S3C24X0_SLAVE, 3)
+U_BOOT_I2C_ADAP_COMPLETE(i2c04, exynos_i2c_init, s3c24x0_i2c_probe,
+			s3c24x0_i2c_read, s3c24x0_i2c_write,
+			s3c24x0_i2c_set_bus_speed,
+			CONFIG_SYS_I2C_S3C24X0_SPEED,
+			CONFIG_SYS_I2C_S3C24X0_SLAVE, 4)
+U_BOOT_I2C_ADAP_COMPLETE(i2c05, exynos_i2c_init, s3c24x0_i2c_probe,
+			s3c24x0_i2c_read, s3c24x0_i2c_write,
+			s3c24x0_i2c_set_bus_speed,
+			CONFIG_SYS_I2C_S3C24X0_SPEED,
+			CONFIG_SYS_I2C_S3C24X0_SLAVE, 5)
+U_BOOT_I2C_ADAP_COMPLETE(i2c06, exynos_i2c_init, s3c24x0_i2c_probe,
+			s3c24x0_i2c_read, s3c24x0_i2c_write,
+			s3c24x0_i2c_set_bus_speed,
+			CONFIG_SYS_I2C_S3C24X0_SPEED,
+			CONFIG_SYS_I2C_S3C24X0_SLAVE, 6)
+U_BOOT_I2C_ADAP_COMPLETE(i2c07, exynos_i2c_init, s3c24x0_i2c_probe,
+			s3c24x0_i2c_read, s3c24x0_i2c_write,
+			s3c24x0_i2c_set_bus_speed,
+			CONFIG_SYS_I2C_S3C24X0_SPEED,
+			CONFIG_SYS_I2C_S3C24X0_SLAVE, 7)
+U_BOOT_I2C_ADAP_COMPLETE(i2c08, exynos_i2c_init, s3c24x0_i2c_probe,
+			s3c24x0_i2c_read, s3c24x0_i2c_write,
+			s3c24x0_i2c_set_bus_speed,
+			CONFIG_SYS_I2C_S3C24X0_SPEED,
+			CONFIG_SYS_I2C_S3C24X0_SLAVE, 8)
+U_BOOT_I2C_ADAP_COMPLETE(i2c09, exynos_i2c_init, s3c24x0_i2c_probe,
+			s3c24x0_i2c_read, s3c24x0_i2c_write,
+			s3c24x0_i2c_set_bus_speed,
+			CONFIG_SYS_I2C_S3C24X0_SPEED,
+			CONFIG_SYS_I2C_S3C24X0_SLAVE, 9)
+U_BOOT_I2C_ADAP_COMPLETE(i2c10, exynos_i2c_init, s3c24x0_i2c_probe,
+			s3c24x0_i2c_read, s3c24x0_i2c_write,
+			s3c24x0_i2c_set_bus_speed,
+			CONFIG_SYS_I2C_S3C24X0_SPEED,
+			CONFIG_SYS_I2C_S3C24X0_SLAVE, 10)
+#elif defined(CONFIG_EXYNOS5250)
+U_BOOT_I2C_ADAP_COMPLETE(i2c00, exynos_i2c_init, s3c24x0_i2c_probe,
+			s3c24x0_i2c_read, s3c24x0_i2c_write,
+			s3c24x0_i2c_set_bus_speed,
+			CONFIG_SYS_I2C_S3C24X0_SPEED,
+			CONFIG_SYS_I2C_S3C24X0_SLAVE, 0)
+U_BOOT_I2C_ADAP_COMPLETE(i2c01, exynos_i2c_init, s3c24x0_i2c_probe,
+			s3c24x0_i2c_read, s3c24x0_i2c_write,
+			s3c24x0_i2c_set_bus_speed,
+			CONFIG_SYS_I2C_S3C24X0_SPEED,
+			CONFIG_SYS_I2C_S3C24X0_SLAVE, 1)
+U_BOOT_I2C_ADAP_COMPLETE(i2c02, exynos_i2c_init, s3c24x0_i2c_probe,
+			s3c24x0_i2c_read, s3c24x0_i2c_write,
+			s3c24x0_i2c_set_bus_speed,
+			CONFIG_SYS_I2C_S3C24X0_SPEED,
+			CONFIG_SYS_I2C_S3C24X0_SLAVE, 2)
+U_BOOT_I2C_ADAP_COMPLETE(i2c03, exynos_i2c_init, s3c24x0_i2c_probe,
+			s3c24x0_i2c_read, s3c24x0_i2c_write,
+			s3c24x0_i2c_set_bus_speed,
+			CONFIG_SYS_I2C_S3C24X0_SPEED,
+			CONFIG_SYS_I2C_S3C24X0_SLAVE, 3)
+U_BOOT_I2C_ADAP_COMPLETE(i2c04, s3c24x0_i2c_init, s3c24x0_i2c_probe,
+			s3c24x0_i2c_read, s3c24x0_i2c_write,
+			s3c24x0_i2c_set_bus_speed,
+			CONFIG_SYS_I2C_S3C24X0_SPEED,
+			CONFIG_SYS_I2C_S3C24X0_SLAVE, 4)
+U_BOOT_I2C_ADAP_COMPLETE(i2c05, s3c24x0_i2c_init, s3c24x0_i2c_probe,
+			s3c24x0_i2c_read, s3c24x0_i2c_write,
+			s3c24x0_i2c_set_bus_speed,
+			CONFIG_SYS_I2C_S3C24X0_SPEED,
+			CONFIG_SYS_I2C_S3C24X0_SLAVE, 5)
+U_BOOT_I2C_ADAP_COMPLETE(i2c06, s3c24x0_i2c_init, s3c24x0_i2c_probe,
+			s3c24x0_i2c_read, s3c24x0_i2c_write,
+			s3c24x0_i2c_set_bus_speed,
+			CONFIG_SYS_I2C_S3C24X0_SPEED,
+			CONFIG_SYS_I2C_S3C24X0_SLAVE, 6)
+U_BOOT_I2C_ADAP_COMPLETE(i2c07, s3c24x0_i2c_init, s3c24x0_i2c_probe,
+			s3c24x0_i2c_read, s3c24x0_i2c_write,
+			s3c24x0_i2c_set_bus_speed,
+			CONFIG_SYS_I2C_S3C24X0_SPEED,
+			CONFIG_SYS_I2C_S3C24X0_SLAVE, 7)
+U_BOOT_I2C_ADAP_COMPLETE(i2c08, s3c24x0_i2c_init, s3c24x0_i2c_probe,
+			s3c24x0_i2c_read, s3c24x0_i2c_write,
+			s3c24x0_i2c_set_bus_speed,
+			CONFIG_SYS_I2C_S3C24X0_SPEED,
+			CONFIG_SYS_I2C_S3C24X0_SLAVE, 8)
+U_BOOT_I2C_ADAP_COMPLETE(i2c09, s3c24x0_i2c_init, s3c24x0_i2c_probe,
+			s3c24x0_i2c_read, s3c24x0_i2c_write,
+			s3c24x0_i2c_set_bus_speed,
+			CONFIG_SYS_I2C_S3C24X0_SPEED,
+			CONFIG_SYS_I2C_S3C24X0_SLAVE, 9)
+U_BOOT_I2C_ADAP_COMPLETE(s3c10, s3c24x0_i2c_init, s3c24x0_i2c_probe,
+			s3c24x0_i2c_read, s3c24x0_i2c_write,
+			s3c24x0_i2c_set_bus_speed,
+			CONFIG_SYS_I2C_S3C24X0_SPEED,
+			CONFIG_SYS_I2C_S3C24X0_SLAVE, 10)
+#elif defined(CONFIG_EXYNOS4)
+U_BOOT_I2C_ADAP_COMPLETE(i2c00, s3c24x0_i2c_init, s3c24x0_i2c_probe,
+			s3c24x0_i2c_read, s3c24x0_i2c_write,
+			s3c24x0_i2c_set_bus_speed,
+			CONFIG_SYS_I2C_S3C24X0_SPEED,
+			CONFIG_SYS_I2C_S3C24X0_SLAVE, 0)
+U_BOOT_I2C_ADAP_COMPLETE(i2c01, s3c24x0_i2c_init, s3c24x0_i2c_probe,
+			s3c24x0_i2c_read, s3c24x0_i2c_write,
+			s3c24x0_i2c_set_bus_speed,
+			CONFIG_SYS_I2C_S3C24X0_SPEED,
+			CONFIG_SYS_I2C_S3C24X0_SLAVE, 1)
+U_BOOT_I2C_ADAP_COMPLETE(i2c02, s3c24x0_i2c_init, s3c24x0_i2c_probe,
+			s3c24x0_i2c_read, s3c24x0_i2c_write,
+			s3c24x0_i2c_set_bus_speed,
+			CONFIG_SYS_I2C_S3C24X0_SPEED,
+			CONFIG_SYS_I2C_S3C24X0_SLAVE, 2)
+U_BOOT_I2C_ADAP_COMPLETE(i2c03, s3c24x0_i2c_init, s3c24x0_i2c_probe,
+			s3c24x0_i2c_read, s3c24x0_i2c_write,
+			s3c24x0_i2c_set_bus_speed,
+			CONFIG_SYS_I2C_S3C24X0_SPEED,
+			CONFIG_SYS_I2C_S3C24X0_SLAVE, 3)
+U_BOOT_I2C_ADAP_COMPLETE(i2c04, s3c24x0_i2c_init, s3c24x0_i2c_probe,
+			s3c24x0_i2c_read, s3c24x0_i2c_write,
+			s3c24x0_i2c_set_bus_speed,
+			CONFIG_SYS_I2C_S3C24X0_SPEED,
+			CONFIG_SYS_I2C_S3C24X0_SLAVE, 4)
+U_BOOT_I2C_ADAP_COMPLETE(i2c05, s3c24x0_i2c_init, s3c24x0_i2c_probe,
+			s3c24x0_i2c_read, s3c24x0_i2c_write,
+			s3c24x0_i2c_set_bus_speed,
+			CONFIG_SYS_I2C_S3C24X0_SPEED,
+			CONFIG_SYS_I2C_S3C24X0_SLAVE, 5)
+U_BOOT_I2C_ADAP_COMPLETE(i2c06, s3c24x0_i2c_init, s3c24x0_i2c_probe,
+			s3c24x0_i2c_read, s3c24x0_i2c_write,
+			s3c24x0_i2c_set_bus_speed,
+			CONFIG_SYS_I2C_S3C24X0_SPEED,
+			CONFIG_SYS_I2C_S3C24X0_SLAVE, 6)
+U_BOOT_I2C_ADAP_COMPLETE(i2c07, s3c24x0_i2c_init, s3c24x0_i2c_probe,
+			s3c24x0_i2c_read, s3c24x0_i2c_write,
+			s3c24x0_i2c_set_bus_speed,
+			CONFIG_SYS_I2C_S3C24X0_SPEED,
+			CONFIG_SYS_I2C_S3C24X0_SLAVE, 7)
+U_BOOT_I2C_ADAP_COMPLETE(i2c08, s3c24x0_i2c_init, s3c24x0_i2c_probe,
+			s3c24x0_i2c_read, s3c24x0_i2c_write,
+			s3c24x0_i2c_set_bus_speed,
+			CONFIG_SYS_I2C_S3C24X0_SPEED,
+			CONFIG_SYS_I2C_S3C24X0_SLAVE, 8)
+#else
+U_BOOT_I2C_ADAP_COMPLETE(s3c0, s3c24x0_i2c_init, s3c24x0_i2c_probe,
+			s3c24x0_i2c_read, s3c24x0_i2c_write,
+			s3c24x0_i2c_set_bus_speed,
+			CONFIG_SYS_I2C_S3C24X0_SPEED,
+			CONFIG_SYS_I2C_S3C24X0_SLAVE, 0)
+#endif
diff --git a/drivers/i2c/s3c24x0_i2c.h b/drivers/i2c/s3c24x0_i2c.h
index b4a337a57b..1ae73d2777 100644
--- a/drivers/i2c/s3c24x0_i2c.h
+++ b/drivers/i2c/s3c24x0_i2c.h
@@ -15,10 +15,48 @@ struct s3c24x0_i2c {
 	u32	iiclc;
 };
 
+struct exynos5_hsi2c {
+	u32	usi_ctl;
+	u32	usi_fifo_ctl;
+	u32	usi_trailing_ctl;
+	u32	usi_clk_ctl;
+	u32	usi_clk_slot;
+	u32	spi_ctl;
+	u32	uart_ctl;
+	u32	res1;
+	u32	usi_int_en;
+	u32	usi_int_stat;
+	u32	usi_modem_stat;
+	u32	usi_error_stat;
+	u32	usi_fifo_stat;
+	u32	usi_txdata;
+	u32	usi_rxdata;
+	u32	res2;
+	u32	usi_conf;
+	u32	usi_auto_conf;
+	u32	usi_timeout;
+	u32	usi_manual_cmd;
+	u32	usi_trans_status;
+	u32	usi_timing_hs1;
+	u32	usi_timing_hs2;
+	u32	usi_timing_hs3;
+	u32	usi_timing_fs1;
+	u32	usi_timing_fs2;
+	u32	usi_timing_fs3;
+	u32	usi_timing_sla;
+	u32	i2c_addr;
+};
+
 struct s3c24x0_i2c_bus {
+	bool active;	/* port is active and available */
 	int node;	/* device tree node */
 	int bus_num;	/* i2c bus number */
 	struct s3c24x0_i2c *regs;
+	struct exynos5_hsi2c *hsregs;
+	int is_highspeed;	/* High speed type, rather than I2C */
+	unsigned clock_frequency;
 	int id;
+	unsigned clk_cycle;
+	unsigned clk_div;
 };
 #endif /* _S3C24X0_I2C_H */
diff --git a/drivers/i2c/sh_i2c.c b/drivers/i2c/sh_i2c.c
index 58f8bf1bd5..e7e96921d2 100644
--- a/drivers/i2c/sh_i2c.c
+++ b/drivers/i2c/sh_i2c.c
@@ -1,13 +1,16 @@
 /*
- * Copyright (C) 2011 Renesas Solutions Corp.
- * Copyright (C) 2011 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
+ * Copyright (C) 2011, 2013 Renesas Solutions Corp.
+ * Copyright (C) 2011, 2013 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */
 
 #include <common.h>
+#include <i2c.h>
 #include <asm/io.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 /* Every register is 32bit aligned, but only 8bits in size */
 #define ureg(name) u8 name; u8 __pad_##name##0; u16 __pad_##name##1;
 struct sh_i2c {
@@ -20,8 +23,6 @@ struct sh_i2c {
 };
 #undef ureg
 
-static struct sh_i2c *base;
-
 /* ICCR */
 #define SH_I2C_ICCR_ICE		(1 << 7)
 #define SH_I2C_ICCR_RACK	(1 << 6)
@@ -41,209 +42,171 @@ static struct sh_i2c *base;
 #define SH_I2C_ICIC_ICCHB8	(1 << 6)
 #endif
 
+static const struct sh_i2c *i2c_dev[CONFIG_SYS_I2C_SH_NUM_CONTROLLERS] = {
+	(struct sh_i2c *)CONFIG_SYS_I2C_SH_BASE0,
+#ifdef CONFIG_SYS_I2C_SH_BASE1
+	(struct sh_i2c *)CONFIG_SYS_I2C_SH_BASE1,
+#endif
+#ifdef CONFIG_SYS_I2C_SH_BASE2
+	(struct sh_i2c *)CONFIG_SYS_I2C_SH_BASE2,
+#endif
+#ifdef CONFIG_SYS_I2C_SH_BASE3
+	(struct sh_i2c *)CONFIG_SYS_I2C_SH_BASE3,
+#endif
+#ifdef CONFIG_SYS_I2C_SH_BASE4
+	(struct sh_i2c *)CONFIG_SYS_I2C_SH_BASE4,
+#endif
+};
+
 static u16 iccl, icch;
 
 #define IRQ_WAIT 1000
 
-static void irq_dte(struct sh_i2c *base)
+static void sh_irq_dte(struct sh_i2c *dev)
 {
 	int i;
 
-	for (i = 0 ; i < IRQ_WAIT ; i++) {
-		if (SH_IC_DTE & readb(&base->icsr))
+	for (i = 0; i < IRQ_WAIT; i++) {
+		if (SH_IC_DTE & readb(&dev->icsr))
 			break;
 		udelay(10);
 	}
 }
 
-static int irq_dte_with_tack(struct sh_i2c *base)
+static int sh_irq_dte_with_tack(struct sh_i2c *dev)
 {
 	int i;
 
-	for (i = 0 ; i < IRQ_WAIT ; i++) {
-		if (SH_IC_DTE & readb(&base->icsr))
+	for (i = 0; i < IRQ_WAIT; i++) {
+		if (SH_IC_DTE & readb(&dev->icsr))
 			break;
-		if (SH_IC_TACK & readb(&base->icsr))
+		if (SH_IC_TACK & readb(&dev->icsr))
 			return -1;
 		udelay(10);
 	}
 	return 0;
 }
 
-static void irq_busy(struct sh_i2c *base)
+static void sh_irq_busy(struct sh_i2c *dev)
 {
 	int i;
 
-	for (i = 0 ; i < IRQ_WAIT ; i++) {
-		if (!(SH_IC_BUSY & readb(&base->icsr)))
+	for (i = 0; i < IRQ_WAIT; i++) {
+		if (!(SH_IC_BUSY & readb(&dev->icsr)))
 			break;
 		udelay(10);
 	}
 }
 
-static int i2c_set_addr(struct sh_i2c *base, u8 id, u8 reg, int stop)
+static int sh_i2c_set_addr(struct sh_i2c *dev, u8 chip, u8 addr, int stop)
 {
 	u8 icic = SH_IC_TACK;
 
-	clrbits_8(&base->iccr, SH_I2C_ICCR_ICE);
-	setbits_8(&base->iccr, SH_I2C_ICCR_ICE);
+	debug("%s: chip: %x, addr: %x iccl: %x, icch %x\n",
+				__func__, chip, addr, iccl, icch);
+	clrbits_8(&dev->iccr, SH_I2C_ICCR_ICE);
+	setbits_8(&dev->iccr, SH_I2C_ICCR_ICE);
 
-	writeb(iccl & 0xff, &base->iccl);
-	writeb(icch & 0xff, &base->icch);
+	writeb(iccl & 0xff, &dev->iccl);
+	writeb(icch & 0xff, &dev->icch);
 #ifdef CONFIG_SH_I2C_8BIT
 	if (iccl > 0xff)
 		icic |= SH_I2C_ICIC_ICCLB8;
 	if (icch > 0xff)
 		icic |= SH_I2C_ICIC_ICCHB8;
 #endif
-	writeb(icic, &base->icic);
+	writeb(icic, &dev->icic);
 
-	writeb((SH_I2C_ICCR_ICE|SH_I2C_ICCR_RTS|SH_I2C_ICCR_BUSY), &base->iccr);
-	irq_dte(base);
+	writeb((SH_I2C_ICCR_ICE|SH_I2C_ICCR_RTS|SH_I2C_ICCR_BUSY), &dev->iccr);
+	sh_irq_dte(dev);
 
-	clrbits_8(&base->icsr, SH_IC_TACK);
-	writeb(id << 1, &base->icdr);
-	if (irq_dte_with_tack(base) != 0)
+	clrbits_8(&dev->icsr, SH_IC_TACK);
+	writeb(chip << 1, &dev->icdr);
+	if (sh_irq_dte_with_tack(dev) != 0)
 		return -1;
 
-	writeb(reg, &base->icdr);
+	writeb(addr, &dev->icdr);
 	if (stop)
-		writeb((SH_I2C_ICCR_ICE|SH_I2C_ICCR_RTS), &base->iccr);
+		writeb((SH_I2C_ICCR_ICE|SH_I2C_ICCR_RTS), &dev->iccr);
 
-	if (irq_dte_with_tack(base) != 0)
+	if (sh_irq_dte_with_tack(dev) != 0)
 		return -1;
 	return 0;
 }
 
-static void i2c_finish(struct sh_i2c *base)
+static void sh_i2c_finish(struct sh_i2c *dev)
 {
-	writeb(0, &base->icsr);
-	clrbits_8(&base->iccr, SH_I2C_ICCR_ICE);
+	writeb(0, &dev->icsr);
+	clrbits_8(&dev->iccr, SH_I2C_ICCR_ICE);
 }
 
-static int i2c_raw_write(struct sh_i2c *base, u8 id, u8 reg, u8 val)
+static int
+sh_i2c_raw_write(struct sh_i2c *dev, u8 chip, uint addr, u8 val)
 {
 	int ret = -1;
-	if (i2c_set_addr(base, id, reg, 0) != 0)
+	if (sh_i2c_set_addr(dev, chip, addr, 0) != 0)
 		goto exit0;
 	udelay(10);
 
-	writeb(val, &base->icdr);
-	if (irq_dte_with_tack(base) != 0)
+	writeb(val, &dev->icdr);
+	if (sh_irq_dte_with_tack(dev) != 0)
 		goto exit0;
 
-	writeb((SH_I2C_ICCR_ICE | SH_I2C_ICCR_RTS), &base->iccr);
-	if (irq_dte_with_tack(base) != 0)
+	writeb((SH_I2C_ICCR_ICE | SH_I2C_ICCR_RTS), &dev->iccr);
+	if (sh_irq_dte_with_tack(dev) != 0)
 		goto exit0;
-	irq_busy(base);
+	sh_irq_busy(dev);
 	ret = 0;
+
 exit0:
-	i2c_finish(base);
+	sh_i2c_finish(dev);
 	return ret;
 }
 
-static int i2c_raw_read(struct sh_i2c *base, u8 id, u8 reg)
+static int sh_i2c_raw_read(struct sh_i2c *dev, u8 chip, u8 addr)
 {
 	int ret = -1;
 
 #if defined(CONFIG_SH73A0)
-	if (i2c_set_addr(base, id, reg, 0) != 0)
+	if (sh_i2c_set_addr(dev, chip, addr, 0) != 0)
 		goto exit0;
 #else
-	if (i2c_set_addr(base, id, reg, 1) != 0)
+	if (sh_i2c_set_addr(dev, chip, addr, 1) != 0)
 		goto exit0;
 	udelay(100);
 #endif
 
-	writeb((SH_I2C_ICCR_ICE|SH_I2C_ICCR_RTS|SH_I2C_ICCR_BUSY), &base->iccr);
-	irq_dte(base);
+	writeb((SH_I2C_ICCR_ICE|SH_I2C_ICCR_RTS|SH_I2C_ICCR_BUSY), &dev->iccr);
+	sh_irq_dte(dev);
 
-	writeb(id << 1 | 0x01, &base->icdr);
-	if (irq_dte_with_tack(base) != 0)
+	writeb(chip << 1 | 0x01, &dev->icdr);
+	if (sh_irq_dte_with_tack(dev) != 0)
 		goto exit0;
 
-	writeb((SH_I2C_ICCR_ICE|SH_I2C_ICCR_SCP), &base->iccr);
-	if (irq_dte_with_tack(base) != 0)
+	writeb((SH_I2C_ICCR_ICE|SH_I2C_ICCR_SCP), &dev->iccr);
+	if (sh_irq_dte_with_tack(dev) != 0)
 		goto exit0;
 
-	ret = readb(&base->icdr) & 0xff;
+	ret = readb(&dev->icdr) & 0xff;
+
+	writeb((SH_I2C_ICCR_ICE|SH_I2C_ICCR_RACK), &dev->iccr);
+	readb(&dev->icdr); /* Dummy read */
+	sh_irq_busy(dev);
 
-	writeb((SH_I2C_ICCR_ICE|SH_I2C_ICCR_RACK), &base->iccr);
-	readb(&base->icdr); /* Dummy read */
-	irq_busy(base);
 exit0:
-	i2c_finish(base);
+	sh_i2c_finish(dev);
 
 	return ret;
 }
 
-#ifdef CONFIG_I2C_MULTI_BUS
-static unsigned int current_bus;
-
-/**
- * i2c_set_bus_num - change active I2C bus
- *	@bus: bus index, zero based
- *	@returns: 0 on success, non-0 on failure
- */
-int i2c_set_bus_num(unsigned int bus)
-{
-	if ((bus < 0) || (bus >= CONFIG_SYS_MAX_I2C_BUS)) {
-		printf("Bad bus: %d\n", bus);
-		return -1;
-	}
-
-	switch (bus) {
-	case 0:
-		base = (void *)CONFIG_SH_I2C_BASE0;
-		break;
-	case 1:
-		base = (void *)CONFIG_SH_I2C_BASE1;
-		break;
-#ifdef CONFIG_SH_I2C_BASE2
-	case 2:
-		base = (void *)CONFIG_SH_I2C_BASE2;
-		break;
-#endif
-#ifdef CONFIG_SH_I2C_BASE3
-	case 3:
-		base = (void *)CONFIG_SH_I2C_BASE3;
-		break;
-#endif
-#ifdef CONFIG_SH_I2C_BASE4
-	case 4:
-		base = (void *)CONFIG_SH_I2C_BASE4;
-		break;
-#endif
-	default:
-		return -1;
-	}
-	current_bus = bus;
-
-	return 0;
-}
-
-/**
- * i2c_get_bus_num - returns index of active I2C bus
- */
-unsigned int i2c_get_bus_num(void)
-{
-	return current_bus;
-}
-#endif
-
-#define SH_I2C_ICCL_CALC(clk, date, t_low, t_high) \
-		((clk / rate) * (t_low / t_low + t_high))
-#define SH_I2C_ICCH_CALC(clk, date, t_low, t_high) \
-		((clk / rate) * (t_high / t_low + t_high))
-
-void i2c_init(int speed, int slaveaddr)
+static void
+sh_i2c_init(struct i2c_adapter *adap, int speed, int slaveadd)
 {
 	int num, denom, tmp;
 
-#ifdef CONFIG_I2C_MULTI_BUS
-	current_bus = 0;
-#endif
-	base = (struct sh_i2c *)CONFIG_SH_I2C_BASE0;
+	/* No i2c support prior to relocation */
+	if (!(gd->flags & GD_FLG_RELOC))
+		return;
 
 	/*
 	 * Calculate the value for iccl. From the data sheet:
@@ -266,67 +229,80 @@ void i2c_init(int speed, int slaveaddr)
 		icch = (u16)((num/denom) + 1);
 	else
 		icch = (u16)(num/denom);
+
+	debug("clock: %d, speed %d, iccl: %x, icch: %x\n",
+			CONFIG_SH_I2C_CLOCK, speed, iccl, icch);
 }
 
-/*
- * i2c_read: - Read multiple bytes from an i2c device
- *
- * The higher level routines take into account that this function is only
- * called with len < page length of the device (see configuration file)
- *
- * @chip:   address of the chip which is to be read
- * @addr:   i2c data address within the chip
- * @alen:   length of the i2c data address (1..2 bytes)
- * @buffer: where to write the data
- * @len:    how much byte do we want to read
- * @return: 0 in case of success
- */
-int i2c_read(u8 chip, u32 addr, int alen, u8 *buffer, int len)
+static int sh_i2c_read(struct i2c_adapter *adap, uint8_t chip,
+				uint addr, int alen, u8 *data, int len)
 {
-	int ret;
-	int i = 0;
-	for (i = 0 ; i < len ; i++) {
-		ret = i2c_raw_read(base, chip, addr + i);
+	int ret, i;
+	struct sh_i2c *dev = (struct sh_i2c *)i2c_dev[adap->hwadapnr];
+
+	for (i = 0; i < len; i++) {
+		ret = sh_i2c_raw_read(dev, chip, addr + i);
 		if (ret < 0)
 			return -1;
-		buffer[i] = ret & 0xff;
+
+		data[i] = ret & 0xff;
+		debug("%s: data[%d]: %02x\n", __func__, i, data[i]);
 	}
+
 	return 0;
 }
 
-/*
- * i2c_write: -  Write multiple bytes to an i2c device
- *
- * The higher level routines take into account that this function is only
- * called with len < page length of the device (see configuration file)
- *
- * @chip:   address of the chip which is to be written
- * @addr:   i2c data address within the chip
- * @alen:   length of the i2c data address (1..2 bytes)
- * @buffer: where to find the data to be written
- * @len:    how much byte do we want to read
- * @return: 0 in case of success
- */
-int i2c_write(u8 chip, u32 addr, int alen, u8 *buffer, int len)
+static int sh_i2c_write(struct i2c_adapter *adap, uint8_t chip, uint addr,
+				int alen, u8 *data, int len)
 {
-	int i = 0;
-	for (i = 0; i < len ; i++)
-		if (i2c_raw_write(base, chip, addr + i, buffer[i]) != 0)
+	struct sh_i2c *dev = (struct sh_i2c *)i2c_dev[adap->hwadapnr];
+	int i;
+
+	for (i = 0; i < len; i++) {
+		debug("%s: data[%d]: %02x\n", __func__, i, data[i]);
+		if (sh_i2c_raw_write(dev, chip, addr + i, data[i]) != 0)
 			return -1;
+	}
 	return 0;
 }
 
-/*
- * i2c_probe: - Test if a chip answers for a given i2c address
- *
- * @chip:   address of the chip which is searched for
- * @return: 0 if a chip was found, -1 otherwhise
- */
-int i2c_probe(u8 chip)
+static int
+sh_i2c_probe(struct i2c_adapter *adap, u8 dev)
 {
-	int ret;
+	u8 dummy[1];
 
-	ret = i2c_set_addr(base, chip, 0, 1);
-	i2c_finish(base);
-	return ret;
+	return sh_i2c_read(adap, dev, 0, 0, dummy, sizeof dummy);
+}
+
+static unsigned int sh_i2c_set_bus_speed(struct i2c_adapter *adap,
+			unsigned int speed)
+{
+	struct sh_i2c *dev = (struct sh_i2c *)i2c_dev[adap->hwadapnr];
+
+	sh_i2c_finish(dev);
+	sh_i2c_init(adap, speed, 0);
+
+	return 0;
 }
+
+/*
+ * Register RCAR i2c adapters
+ */
+U_BOOT_I2C_ADAP_COMPLETE(sh_0, sh_i2c_init, sh_i2c_probe, sh_i2c_read,
+	sh_i2c_write, sh_i2c_set_bus_speed, CONFIG_SYS_I2C_SH_SPEED0, 0, 0)
+#ifdef CONFIG_SYS_I2C_SH_BASE1
+U_BOOT_I2C_ADAP_COMPLETE(sh_1, sh_i2c_init, sh_i2c_probe, sh_i2c_read,
+	sh_i2c_write, sh_i2c_set_bus_speed, CONFIG_SYS_I2C_SH_SPEED1, 0, 1)
+#endif
+#ifdef CONFIG_SYS_I2C_SH_BASE2
+U_BOOT_I2C_ADAP_COMPLETE(sh_2, sh_i2c_init, sh_i2c_probe, sh_i2c_read,
+	sh_i2c_write, sh_i2c_set_bus_speed, CONFIG_SYS_I2C_SH_SPEED2, 0, 2)
+#endif
+#ifdef CONFIG_SYS_I2C_SH_BASE3
+U_BOOT_I2C_ADAP_COMPLETE(sh_3, sh_i2c_init, sh_i2c_probe, sh_i2c_read,
+	sh_i2c_write, sh_i2c_set_bus_speed, CONFIG_SYS_I2C_SH_SPEED3, 0, 3)
+#endif
+#ifdef CONFIG_SYS_I2C_SH_BASE4
+U_BOOT_I2C_ADAP_COMPLETE(sh_4, sh_i2c_init, sh_i2c_probe, sh_i2c_read,
+	sh_i2c_write, sh_i2c_set_bus_speed, CONFIG_SYS_I2C_SH_SPEED4, 0, 4)
+#endif
diff --git a/drivers/i2c/soft_i2c.c b/drivers/i2c/soft_i2c.c
index 396fea89af..db9b4026b3 100644
--- a/drivers/i2c/soft_i2c.c
+++ b/drivers/i2c/soft_i2c.c
@@ -25,13 +25,10 @@
 #include <asm/io.h>
 #include <asm/arch/hardware.h>
 #include <asm/arch/at91_pio.h>
-#ifdef CONFIG_AT91_LEGACY
+#ifdef CONFIG_ATMEL_LEGACY
 #include <asm/arch/gpio.h>
 #endif
 #endif
-#ifdef	CONFIG_IXP425			/* only valid for IXP425 */
-#include <asm/arch/ixp425.h>
-#endif
 #if defined(CONFIG_MPC852T) || defined(CONFIG_MPC866)
 #include <asm/io.h>
 #endif
diff --git a/drivers/i2c/tegra_i2c.c b/drivers/i2c/tegra_i2c.c
index 9847cf126b..594e5ddeb4 100644
--- a/drivers/i2c/tegra_i2c.c
+++ b/drivers/i2c/tegra_i2c.c
@@ -629,3 +629,8 @@ U_BOOT_I2C_ADAP_COMPLETE(tegra2, tegra_i2c_init, tegra_i2c_probe,
 U_BOOT_I2C_ADAP_COMPLETE(tegra3, tegra_i2c_init, tegra_i2c_probe,
 			 tegra_i2c_read, tegra_i2c_write,
 			 tegra_i2c_set_bus_speed, 100000, 0, 3)
+#if TEGRA_I2C_NUM_CONTROLLERS > 4
+U_BOOT_I2C_ADAP_COMPLETE(tegra4, tegra_i2c_init, tegra_i2c_probe,
+			 tegra_i2c_read, tegra_i2c_write,
+			 tegra_i2c_set_bus_speed, 100000, 0, 4)
+#endif
diff --git a/drivers/i2c/zynq_i2c.c b/drivers/i2c/zynq_i2c.c
index ce2d23f725..f1f65131a2 100644
--- a/drivers/i2c/zynq_i2c.c
+++ b/drivers/i2c/zynq_i2c.c
@@ -64,18 +64,21 @@ struct zynq_i2c_registers {
 #define ZYNQ_I2C_FIFO_DEPTH		16
 #define ZYNQ_I2C_TRANSFERT_SIZE_MAX	255 /* Controller transfer limit */
 
-#if defined(CONFIG_ZYNQ_I2C0)
-# define ZYNQ_I2C_BASE	ZYNQ_I2C_BASEADDR0
-#else
-# define ZYNQ_I2C_BASE	ZYNQ_I2C_BASEADDR1
-#endif
-
-static struct zynq_i2c_registers *zynq_i2c =
-	(struct zynq_i2c_registers *)ZYNQ_I2C_BASE;
+static struct zynq_i2c_registers *i2c_select(struct i2c_adapter *adap)
+{
+	return adap->hwadapnr ?
+		/* Zynq PS I2C1 */
+		(struct zynq_i2c_registers *)ZYNQ_I2C_BASEADDR1 :
+		/* Zynq PS I2C0 */
+		(struct zynq_i2c_registers *)ZYNQ_I2C_BASEADDR0;
+}
 
 /* I2C init called by cmd_i2c when doing 'i2c reset'. */
-void i2c_init(int requested_speed, int slaveadd)
+static void zynq_i2c_init(struct i2c_adapter *adap, int requested_speed,
+			  int slaveadd)
 {
+	struct zynq_i2c_registers *zynq_i2c = i2c_select(adap);
+
 	/* 111MHz / ( (3 * 17) * 22 ) = ~100KHz */
 	writel((16 << ZYNQ_I2C_CONTROL_DIV_B_SHIFT) |
 		(2 << ZYNQ_I2C_CONTROL_DIV_A_SHIFT), &zynq_i2c->control);
@@ -86,7 +89,7 @@ void i2c_init(int requested_speed, int slaveadd)
 }
 
 #ifdef DEBUG
-static void zynq_i2c_debug_status(void)
+static void zynq_i2c_debug_status(struct zynq_i2c_registers *zynq_i2c)
 {
 	int int_status;
 	int status;
@@ -128,7 +131,7 @@ static void zynq_i2c_debug_status(void)
 #endif
 
 /* Wait for an interrupt */
-static u32 zynq_i2c_wait(u32 mask)
+static u32 zynq_i2c_wait(struct zynq_i2c_registers *zynq_i2c, u32 mask)
 {
 	int timeout, int_status;
 
@@ -139,7 +142,7 @@ static u32 zynq_i2c_wait(u32 mask)
 			break;
 	}
 #ifdef DEBUG
-	zynq_i2c_debug_status();
+	zynq_i2c_debug_status(zynq_i2c));
 #endif
 	/* Clear interrupt status flags */
 	writel(int_status & mask, &zynq_i2c->interrupt_status);
@@ -151,8 +154,10 @@ static u32 zynq_i2c_wait(u32 mask)
  * I2C probe called by cmd_i2c when doing 'i2c probe'.
  * Begin read, nak data byte, end.
  */
-int i2c_probe(u8 dev)
+static int zynq_i2c_probe(struct i2c_adapter *adap, u8 dev)
 {
+	struct zynq_i2c_registers *zynq_i2c = i2c_select(adap);
+
 	/* Attempt to read a byte */
 	setbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_CLR_FIFO |
 		ZYNQ_I2C_CONTROL_RW);
@@ -161,7 +166,7 @@ int i2c_probe(u8 dev)
 	writel(dev, &zynq_i2c->address);
 	writel(1, &zynq_i2c->transfer_size);
 
-	return (zynq_i2c_wait(ZYNQ_I2C_INTERRUPT_COMP |
+	return (zynq_i2c_wait(zynq_i2c, ZYNQ_I2C_INTERRUPT_COMP |
 		ZYNQ_I2C_INTERRUPT_NACK) &
 		ZYNQ_I2C_INTERRUPT_COMP) ? 0 : -ETIMEDOUT;
 }
@@ -170,11 +175,13 @@ int i2c_probe(u8 dev)
  * I2C read called by cmd_i2c when doing 'i2c read' and by cmd_eeprom.c
  * Begin write, send address byte(s), begin read, receive data bytes, end.
  */
-int i2c_read(u8 dev, uint addr, int alen, u8 *data, int length)
+static int zynq_i2c_read(struct i2c_adapter *adap, u8 dev, uint addr,
+			 int alen, u8 *data, int length)
 {
 	u32 status;
 	u32 i = 0;
 	u8 *cur_data = data;
+	struct zynq_i2c_registers *zynq_i2c = i2c_select(adap);
 
 	/* Check the hardware can handle the requested bytes */
 	if ((length < 0) || (length > ZYNQ_I2C_TRANSFERT_SIZE_MAX))
@@ -187,20 +194,22 @@ int i2c_read(u8 dev, uint addr, int alen, u8 *data, int length)
 	 * Temporarily disable restart (by clearing hold)
 	 * It doesn't seem to work.
 	 */
-	clrbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_RW |
-		ZYNQ_I2C_CONTROL_HOLD);
+	clrbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_HOLD);
 	writel(0xFF, &zynq_i2c->interrupt_status);
-	while (alen--)
-		writel(addr >> (8*alen), &zynq_i2c->data);
-	writel(dev, &zynq_i2c->address);
+	if (alen) {
+		clrbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_RW);
+		writel(dev, &zynq_i2c->address);
+		while (alen--)
+			writel(addr >> (8 * alen), &zynq_i2c->data);
 
-	/* Wait for the address to be sent */
-	if (!zynq_i2c_wait(ZYNQ_I2C_INTERRUPT_COMP)) {
-		/* Release the bus */
-		clrbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_HOLD);
-		return -ETIMEDOUT;
+		/* Wait for the address to be sent */
+		if (!zynq_i2c_wait(zynq_i2c, ZYNQ_I2C_INTERRUPT_COMP)) {
+			/* Release the bus */
+			clrbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_HOLD);
+			return -ETIMEDOUT;
+		}
+		debug("Device acked address\n");
 	}
-	debug("Device acked address\n");
 
 	setbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_CLR_FIFO |
 		ZYNQ_I2C_CONTROL_RW);
@@ -210,7 +219,7 @@ int i2c_read(u8 dev, uint addr, int alen, u8 *data, int length)
 
 	/* Wait for data */
 	do {
-		status = zynq_i2c_wait(ZYNQ_I2C_INTERRUPT_COMP |
+		status = zynq_i2c_wait(zynq_i2c, ZYNQ_I2C_INTERRUPT_COMP |
 			ZYNQ_I2C_INTERRUPT_DATA);
 		if (!status) {
 			/* Release the bus */
@@ -235,30 +244,34 @@ int i2c_read(u8 dev, uint addr, int alen, u8 *data, int length)
  * I2C write called by cmd_i2c when doing 'i2c write' and by cmd_eeprom.c
  * Begin write, send address byte(s), send data bytes, end.
  */
-int i2c_write(u8 dev, uint addr, int alen, u8 *data, int length)
+static int zynq_i2c_write(struct i2c_adapter *adap, u8 dev, uint addr,
+			  int alen, u8 *data, int length)
 {
 	u8 *cur_data = data;
+	struct zynq_i2c_registers *zynq_i2c = i2c_select(adap);
 
 	/* Write the register address */
 	setbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_CLR_FIFO |
 		ZYNQ_I2C_CONTROL_HOLD);
 	clrbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_RW);
 	writel(0xFF, &zynq_i2c->interrupt_status);
-	while (alen--)
-		writel(addr >> (8*alen), &zynq_i2c->data);
-	/* Start the tranfer */
 	writel(dev, &zynq_i2c->address);
-	if (!zynq_i2c_wait(ZYNQ_I2C_INTERRUPT_COMP)) {
-		/* Release the bus */
-		clrbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_HOLD);
-		return -ETIMEDOUT;
+	if (alen) {
+		while (alen--)
+			writel(addr >> (8 * alen), &zynq_i2c->data);
+		/* Start the tranfer */
+		if (!zynq_i2c_wait(zynq_i2c, ZYNQ_I2C_INTERRUPT_COMP)) {
+			/* Release the bus */
+			clrbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_HOLD);
+			return -ETIMEDOUT;
+		}
+		debug("Device acked address\n");
 	}
 
-	debug("Device acked address\n");
 	while (length--) {
 		writel(*(cur_data++), &zynq_i2c->data);
 		if (readl(&zynq_i2c->transfer_size) == ZYNQ_I2C_FIFO_DEPTH) {
-			if (!zynq_i2c_wait(ZYNQ_I2C_INTERRUPT_COMP)) {
+			if (!zynq_i2c_wait(zynq_i2c, ZYNQ_I2C_INTERRUPT_COMP)) {
 				/* Release the bus */
 				clrbits_le32(&zynq_i2c->control,
 					     ZYNQ_I2C_CONTROL_HOLD);
@@ -270,21 +283,25 @@ int i2c_write(u8 dev, uint addr, int alen, u8 *data, int length)
 	/* All done... release the bus */
 	clrbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_HOLD);
 	/* Wait for the address and data to be sent */
-	if (!zynq_i2c_wait(ZYNQ_I2C_INTERRUPT_COMP))
+	if (!zynq_i2c_wait(zynq_i2c, ZYNQ_I2C_INTERRUPT_COMP))
 		return -ETIMEDOUT;
 	return 0;
 }
 
-int i2c_set_bus_num(unsigned int bus)
+static unsigned int zynq_i2c_set_bus_speed(struct i2c_adapter *adap,
+			unsigned int speed)
 {
-	/* Only support bus 0 */
-	if (bus > 0)
-		return -1;
-	return 0;
-}
+	if (speed != 1000000)
+		return -EINVAL;
 
-unsigned int i2c_get_bus_num(void)
-{
-	/* Only support bus 0 */
 	return 0;
 }
+
+U_BOOT_I2C_ADAP_COMPLETE(zynq_0, zynq_i2c_init, zynq_i2c_probe, zynq_i2c_read,
+			 zynq_i2c_write, zynq_i2c_set_bus_speed,
+			 CONFIG_SYS_I2C_ZYNQ_SPEED, CONFIG_SYS_I2C_ZYNQ_SLAVE,
+			 0)
+U_BOOT_I2C_ADAP_COMPLETE(zynq_1, zynq_i2c_init, zynq_i2c_probe, zynq_i2c_read,
+			 zynq_i2c_write, zynq_i2c_set_bus_speed,
+			 CONFIG_SYS_I2C_ZYNQ_SPEED, CONFIG_SYS_I2C_ZYNQ_SLAVE,
+			 1)
diff --git a/drivers/input/Makefile b/drivers/input/Makefile
index 788540342d..a8e9be2f7f 100644
--- a/drivers/input/Makefile
+++ b/drivers/input/Makefile
@@ -5,34 +5,12 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	:= $(obj)libinput.o
-
-COBJS-$(CONFIG_I8042_KBD) += i8042.o
-COBJS-$(CONFIG_TEGRA_KEYBOARD) += tegra-kbc.o
-COBJS-$(CONFIG_CROS_EC_KEYB) += cros_ec_keyb.o
+obj-$(CONFIG_I8042_KBD) += i8042.o
+obj-$(CONFIG_TEGRA_KEYBOARD) += tegra-kbc.o
+obj-$(CONFIG_CROS_EC_KEYB) += cros_ec_keyb.o
 ifdef CONFIG_PS2KBD
-COBJS-y += keyboard.o pc_keyb.o
-COBJS-$(CONFIG_PS2MULT) += ps2mult.o ps2ser.o
+obj-y += keyboard.o pc_keyb.o
+obj-$(CONFIG_PS2MULT) += ps2mult.o ps2ser.o
 endif
-COBJS-y += input.o
-COBJS-$(CONFIG_OF_CONTROL) += key_matrix.o
-
-COBJS	:= $(COBJS-y)
-SRCS	:= $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-
-all:	$(LIB)
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y += input.o
+obj-$(CONFIG_OF_CONTROL) += key_matrix.o
diff --git a/drivers/input/cros_ec_keyb.c b/drivers/input/cros_ec_keyb.c
index e8dac237a9..a2501e0206 100644
--- a/drivers/input/cros_ec_keyb.c
+++ b/drivers/input/cros_ec_keyb.c
@@ -8,6 +8,7 @@
 
 #include <common.h>
 #include <cros_ec.h>
+#include <errno.h>
 #include <fdtdec.h>
 #include <input.h>
 #include <key_matrix.h>
@@ -39,20 +40,34 @@ static struct keyb {
  * @param config	Keyboard config
  * @param keys		List of keys that we have detected
  * @param max_count	Maximum number of keys to return
- * @return number of pressed keys, 0 for none
+ * @param samep		Set to true if this scan repeats the last, else false
+ * @return number of pressed keys, 0 for none, -EIO on error
  */
 static int check_for_keys(struct keyb *config,
-			   struct key_matrix_key *keys, int max_count)
+			   struct key_matrix_key *keys, int max_count,
+			   bool *samep)
 {
 	struct key_matrix_key *key;
+	static struct mbkp_keyscan last_scan;
+	static bool last_scan_valid;
 	struct mbkp_keyscan scan;
 	unsigned int row, col, bit, data;
 	int num_keys;
 
 	if (cros_ec_scan_keyboard(config->dev, &scan)) {
 		debug("%s: keyboard scan failed\n", __func__);
-		return -1;
+		return -EIO;
 	}
+	*samep = last_scan_valid && !memcmp(&last_scan, &scan, sizeof(scan));
+
+	/*
+	 * This is a bit odd. The EC has no way to tell us that it has run
+	 * out of key scans. It just returns the same scan over and over
+	 * again. So the only way to detect that we have run out is to detect
+	 * that this scan is the same as the last.
+	 */
+	last_scan_valid = true;
+	memcpy(&last_scan, &scan, sizeof(last_scan));
 
 	for (col = num_keys = bit = 0; col < config->matrix.num_cols;
 			col++) {
@@ -112,6 +127,7 @@ int cros_ec_kbc_check(struct input_config *input)
 	int keycodes[KBC_MAX_KEYS];
 	int num_keys, num_keycodes;
 	int irq_pending, sent;
+	bool same = false;
 
 	/*
 	 * Loop until the EC has no more keyscan records, or we have
@@ -125,7 +141,10 @@ int cros_ec_kbc_check(struct input_config *input)
 	do {
 		irq_pending = cros_ec_interrupt_pending(config.dev);
 		if (irq_pending) {
-			num_keys = check_for_keys(&config, keys, KBC_MAX_KEYS);
+			num_keys = check_for_keys(&config, keys, KBC_MAX_KEYS,
+						  &same);
+			if (num_keys < 0)
+				return 0;
 			last_num_keys = num_keys;
 			memcpy(last_keys, keys, sizeof(keys));
 		} else {
@@ -142,6 +161,13 @@ int cros_ec_kbc_check(struct input_config *input)
 		num_keycodes = key_matrix_decode(&config.matrix, keys,
 				num_keys, keycodes, KBC_MAX_KEYS);
 		sent = input_send_keycodes(input, keycodes, num_keycodes);
+
+		/*
+		 * For those ECs without an interrupt, stop scanning when we
+		 * see that the scan is the same as last time.
+		 */
+		if ((irq_pending < 0) && same)
+			break;
 	} while (irq_pending && !sent);
 
 	return 1;
diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile
index 08828ee31c..2f2e48f979 100644
--- a/drivers/misc/Makefile
+++ b/drivers/misc/Makefile
@@ -5,40 +5,21 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	:= $(obj)libmisc.o
-
-COBJS-$(CONFIG_ALI152X) += ali512x.o
-COBJS-$(CONFIG_DS4510)  += ds4510.o
-COBJS-$(CONFIG_CBMEM_CONSOLE) += cbmem_console.o
-COBJS-$(CONFIG_CROS_EC) += cros_ec.o
-COBJS-$(CONFIG_CROS_EC_LPC) += cros_ec_lpc.o
-COBJS-$(CONFIG_CROS_EC_I2C) += cros_ec_i2c.o
-COBJS-$(CONFIG_CROS_EC_SPI) += cros_ec_spi.o
-COBJS-$(CONFIG_FSL_IIM) += fsl_iim.o
-COBJS-$(CONFIG_GPIO_LED) += gpio_led.o
-COBJS-$(CONFIG_FSL_MC9SDZ60) += mc9sdz60.o
-COBJS-$(CONFIG_MXC_OCOTP) += mxc_ocotp.o
-COBJS-$(CONFIG_NS87308) += ns87308.o
-COBJS-$(CONFIG_PDSP188x) += pdsp188x.o
-COBJS-$(CONFIG_STATUS_LED) += status_led.o
-COBJS-$(CONFIG_TWL4030_LED) += twl4030_led.o
-
-COBJS	:= $(COBJS-y)
-SRCS	:= $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-
-all:	$(LIB)
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-$(CONFIG_ALI152X) += ali512x.o
+obj-$(CONFIG_DS4510)  += ds4510.o
+obj-$(CONFIG_CBMEM_CONSOLE) += cbmem_console.o
+obj-$(CONFIG_CROS_EC) += cros_ec.o
+obj-$(CONFIG_CROS_EC_LPC) += cros_ec_lpc.o
+obj-$(CONFIG_CROS_EC_I2C) += cros_ec_i2c.o
+obj-$(CONFIG_CROS_EC_SANDBOX) += cros_ec_sandbox.o
+obj-$(CONFIG_CROS_EC_SPI) += cros_ec_spi.o
+obj-$(CONFIG_FSL_IIM) += fsl_iim.o
+obj-$(CONFIG_GPIO_LED) += gpio_led.o
+obj-$(CONFIG_FSL_MC9SDZ60) += mc9sdz60.o
+obj-$(CONFIG_MXC_OCOTP) += mxc_ocotp.o
+obj-$(CONFIG_MXS_OCOTP) += mxs_ocotp.o
+obj-$(CONFIG_NS87308) += ns87308.o
+obj-$(CONFIG_PDSP188x) += pdsp188x.o
+obj-$(CONFIG_STATUS_LED) += status_led.o
+obj-$(CONFIG_TWL4030_LED) += twl4030_led.o
+obj-$(CONFIG_FSL_IFC) += fsl_ifc.o
diff --git a/drivers/misc/cros_ec.c b/drivers/misc/cros_ec.c
index 301e8ebbf5..068373b942 100644
--- a/drivers/misc/cros_ec.c
+++ b/drivers/misc/cros_ec.c
@@ -7,10 +7,11 @@
  */
 
 /*
- * The Matrix Keyboard Protocol driver handles talking to the keyboard
- * controller chip. Mostly this is for keyboard functions, but some other
- * things have slipped in, so we provide generic services to talk to the
- * KBC.
+ * This is the interface to the Chrome OS EC. It provides keyboard functions,
+ * power control and battery management. Quite a few other functions are
+ * provided to enable the EC software to be updated, talk to the EC's I2C bus
+ * and store a small amount of data in a memory which persists while the EC
+ * is not reset.
  */
 
 #include <common.h>
@@ -20,6 +21,7 @@
 #include <fdtdec.h>
 #include <malloc.h>
 #include <spi.h>
+#include <asm/errno.h>
 #include <asm/io.h>
 #include <asm-generic/gpio.h>
 
@@ -73,11 +75,184 @@ int cros_ec_calc_checksum(const uint8_t *data, int size)
 	return csum & 0xff;
 }
 
+/**
+ * Create a request packet for protocol version 3.
+ *
+ * The packet is stored in the device's internal output buffer.
+ *
+ * @param dev		CROS-EC device
+ * @param cmd		Command to send (EC_CMD_...)
+ * @param cmd_version	Version of command to send (EC_VER_...)
+ * @param dout          Output data (may be NULL If dout_len=0)
+ * @param dout_len      Size of output data in bytes
+ * @return packet size in bytes, or <0 if error.
+ */
+static int create_proto3_request(struct cros_ec_dev *dev,
+				 int cmd, int cmd_version,
+				 const void *dout, int dout_len)
+{
+	struct ec_host_request *rq = (struct ec_host_request *)dev->dout;
+	int out_bytes = dout_len + sizeof(*rq);
+
+	/* Fail if output size is too big */
+	if (out_bytes > (int)sizeof(dev->dout)) {
+		debug("%s: Cannot send %d bytes\n", __func__, dout_len);
+		return -EC_RES_REQUEST_TRUNCATED;
+	}
+
+	/* Fill in request packet */
+	rq->struct_version = EC_HOST_REQUEST_VERSION;
+	rq->checksum = 0;
+	rq->command = cmd;
+	rq->command_version = cmd_version;
+	rq->reserved = 0;
+	rq->data_len = dout_len;
+
+	/* Copy data after header */
+	memcpy(rq + 1, dout, dout_len);
+
+	/* Write checksum field so the entire packet sums to 0 */
+	rq->checksum = (uint8_t)(-cros_ec_calc_checksum(dev->dout, out_bytes));
+
+	cros_ec_dump_data("out", cmd, dev->dout, out_bytes);
+
+	/* Return size of request packet */
+	return out_bytes;
+}
+
+/**
+ * Prepare the device to receive a protocol version 3 response.
+ *
+ * @param dev		CROS-EC device
+ * @param din_len       Maximum size of response in bytes
+ * @return maximum expected number of bytes in response, or <0 if error.
+ */
+static int prepare_proto3_response_buffer(struct cros_ec_dev *dev, int din_len)
+{
+	int in_bytes = din_len + sizeof(struct ec_host_response);
+
+	/* Fail if input size is too big */
+	if (in_bytes > (int)sizeof(dev->din)) {
+		debug("%s: Cannot receive %d bytes\n", __func__, din_len);
+		return -EC_RES_RESPONSE_TOO_BIG;
+	}
+
+	/* Return expected size of response packet */
+	return in_bytes;
+}
+
+/**
+ * Handle a protocol version 3 response packet.
+ *
+ * The packet must already be stored in the device's internal input buffer.
+ *
+ * @param dev		CROS-EC device
+ * @param dinp          Returns pointer to response data
+ * @param din_len       Maximum size of response in bytes
+ * @return number of bytes of response data, or <0 if error
+ */
+static int handle_proto3_response(struct cros_ec_dev *dev,
+				  uint8_t **dinp, int din_len)
+{
+	struct ec_host_response *rs = (struct ec_host_response *)dev->din;
+	int in_bytes;
+	int csum;
+
+	cros_ec_dump_data("in-header", -1, dev->din, sizeof(*rs));
+
+	/* Check input data */
+	if (rs->struct_version != EC_HOST_RESPONSE_VERSION) {
+		debug("%s: EC response version mismatch\n", __func__);
+		return -EC_RES_INVALID_RESPONSE;
+	}
+
+	if (rs->reserved) {
+		debug("%s: EC response reserved != 0\n", __func__);
+		return -EC_RES_INVALID_RESPONSE;
+	}
+
+	if (rs->data_len > din_len) {
+		debug("%s: EC returned too much data\n", __func__);
+		return -EC_RES_RESPONSE_TOO_BIG;
+	}
+
+	cros_ec_dump_data("in-data", -1, dev->din + sizeof(*rs), rs->data_len);
+
+	/* Update in_bytes to actual data size */
+	in_bytes = sizeof(*rs) + rs->data_len;
+
+	/* Verify checksum */
+	csum = cros_ec_calc_checksum(dev->din, in_bytes);
+	if (csum) {
+		debug("%s: EC response checksum invalid: 0x%02x\n", __func__,
+		      csum);
+		return -EC_RES_INVALID_CHECKSUM;
+	}
+
+	/* Return error result, if any */
+	if (rs->result)
+		return -(int)rs->result;
+
+	/* If we're still here, set response data pointer and return length */
+	*dinp = (uint8_t *)(rs + 1);
+
+	return rs->data_len;
+}
+
+static int send_command_proto3(struct cros_ec_dev *dev,
+			       int cmd, int cmd_version,
+			       const void *dout, int dout_len,
+			       uint8_t **dinp, int din_len)
+{
+	int out_bytes, in_bytes;
+	int rv;
+
+	/* Create request packet */
+	out_bytes = create_proto3_request(dev, cmd, cmd_version,
+					  dout, dout_len);
+	if (out_bytes < 0)
+		return out_bytes;
+
+	/* Prepare response buffer */
+	in_bytes = prepare_proto3_response_buffer(dev, din_len);
+	if (in_bytes < 0)
+		return in_bytes;
+
+	switch (dev->interface) {
+#ifdef CONFIG_CROS_EC_SPI
+	case CROS_EC_IF_SPI:
+		rv = cros_ec_spi_packet(dev, out_bytes, in_bytes);
+		break;
+#endif
+#ifdef CONFIG_CROS_EC_SANDBOX
+	case CROS_EC_IF_SANDBOX:
+		rv = cros_ec_sandbox_packet(dev, out_bytes, in_bytes);
+		break;
+#endif
+	case CROS_EC_IF_NONE:
+	/* TODO: support protocol 3 for LPC, I2C; for now fall through */
+	default:
+		debug("%s: Unsupported interface\n", __func__);
+		rv = -1;
+	}
+	if (rv < 0)
+		return rv;
+
+	/* Process the response */
+	return handle_proto3_response(dev, dinp, din_len);
+}
+
 static int send_command(struct cros_ec_dev *dev, uint8_t cmd, int cmd_version,
 			const void *dout, int dout_len,
 			uint8_t **dinp, int din_len)
 {
-	int ret;
+	int ret = -1;
+
+	/* Handle protocol version 3 support */
+	if (dev->protocol_version == 3) {
+		return send_command_proto3(dev, cmd, cmd_version,
+					   dout, dout_len, dinp, din_len);
+	}
 
 	switch (dev->interface) {
 #ifdef CONFIG_CROS_EC_SPI
@@ -129,19 +304,15 @@ static int ec_command_inptr(struct cros_ec_dev *dev, uint8_t cmd,
 		int cmd_version, const void *dout, int dout_len, uint8_t **dinp,
 		int din_len)
 {
-	uint8_t *din;
+	uint8_t *din = NULL;
 	int len;
 
-	if (cmd_version != 0 && !dev->cmd_version_is_supported) {
-		debug("%s: Command version >0 unsupported\n", __func__);
-		return -1;
-	}
 	len = send_command(dev, cmd, cmd_version, dout, dout_len,
 				&din, din_len);
 
 	/* If the command doesn't complete, wait a while */
 	if (len == -EC_RES_IN_PROGRESS) {
-		struct ec_response_get_comms_status *resp;
+		struct ec_response_get_comms_status *resp = NULL;
 		ulong start;
 
 		/* Wait for command to complete */
@@ -169,7 +340,8 @@ static int ec_command_inptr(struct cros_ec_dev *dev, uint8_t cmd,
 				NULL, 0, &din, din_len);
 	}
 
-	debug("%s: len=%d, dinp=%p, *dinp=%p\n", __func__, len, dinp, *dinp);
+	debug("%s: len=%d, dinp=%p, *dinp=%p\n", __func__, len, dinp,
+	      dinp ? *dinp : NULL);
 	if (dinp) {
 		/* If we have any data to return, it must be 64bit-aligned */
 		assert(len <= 0 || !((uintptr_t)din & 7));
@@ -220,8 +392,8 @@ static int ec_command(struct cros_ec_dev *dev, uint8_t cmd, int cmd_version,
 
 int cros_ec_scan_keyboard(struct cros_ec_dev *dev, struct mbkp_keyscan *scan)
 {
-	if (ec_command(dev, EC_CMD_CROS_EC_STATE, 0, NULL, 0, scan,
-		       sizeof(scan->data)) < sizeof(scan->data))
+	if (ec_command(dev, EC_CMD_MKBP_STATE, 0, NULL, 0, scan,
+		       sizeof(scan->data)) != sizeof(scan->data))
 		return -1;
 
 	return 0;
@@ -232,10 +404,10 @@ int cros_ec_read_id(struct cros_ec_dev *dev, char *id, int maxlen)
 	struct ec_response_get_version *r;
 
 	if (ec_command_inptr(dev, EC_CMD_GET_VERSION, 0, NULL, 0,
-			(uint8_t **)&r, sizeof(*r)) < sizeof(*r))
+			(uint8_t **)&r, sizeof(*r)) != sizeof(*r))
 		return -1;
 
-	if (maxlen > sizeof(r->version_string_ro))
+	if (maxlen > (int)sizeof(r->version_string_ro))
 		maxlen = sizeof(r->version_string_ro);
 
 	switch (r->current_image) {
@@ -258,7 +430,7 @@ int cros_ec_read_version(struct cros_ec_dev *dev,
 {
 	if (ec_command_inptr(dev, EC_CMD_GET_VERSION, 0, NULL, 0,
 			(uint8_t **)versionp, sizeof(**versionp))
-			< sizeof(**versionp))
+			!= sizeof(**versionp))
 		return -1;
 
 	return 0;
@@ -267,7 +439,7 @@ int cros_ec_read_version(struct cros_ec_dev *dev,
 int cros_ec_read_build_info(struct cros_ec_dev *dev, char **strp)
 {
 	if (ec_command_inptr(dev, EC_CMD_GET_BUILD_INFO, 0, NULL, 0,
-			(uint8_t **)strp, EC_HOST_PARAM_SIZE) < 0)
+			(uint8_t **)strp, EC_PROTO2_MAX_PARAM_SIZE) < 0)
 		return -1;
 
 	return 0;
@@ -279,7 +451,7 @@ int cros_ec_read_current_image(struct cros_ec_dev *dev,
 	struct ec_response_get_version *r;
 
 	if (ec_command_inptr(dev, EC_CMD_GET_VERSION, 0, NULL, 0,
-			(uint8_t **)&r, sizeof(*r)) < sizeof(*r))
+			(uint8_t **)&r, sizeof(*r)) != sizeof(*r))
 		return -1;
 
 	*image = r->current_image;
@@ -336,7 +508,7 @@ int cros_ec_read_hash(struct cros_ec_dev *dev,
 	debug("%s: No valid hash (status=%d size=%d). Compute one...\n",
 	      __func__, hash->status, hash->size);
 
-	p.cmd = EC_VBOOT_HASH_RECALC;
+	p.cmd = EC_VBOOT_HASH_START;
 	p.hash_type = EC_VBOOT_HASH_TYPE_SHA256;
 	p.nonce_size = 0;
 	p.offset = EC_VBOOT_HASH_OFFSET_RW;
@@ -413,15 +585,15 @@ int cros_ec_interrupt_pending(struct cros_ec_dev *dev)
 {
 	/* no interrupt support : always poll */
 	if (!fdt_gpio_isvalid(&dev->ec_int))
-		return 1;
+		return -ENOENT;
 
 	return !gpio_get_value(dev->ec_int.gpio);
 }
 
-int cros_ec_info(struct cros_ec_dev *dev, struct ec_response_cros_ec_info *info)
+int cros_ec_info(struct cros_ec_dev *dev, struct ec_response_mkbp_info *info)
 {
-	if (ec_command(dev, EC_CMD_CROS_EC_INFO, 0, NULL, 0, info,
-			sizeof(*info)) < sizeof(*info))
+	if (ec_command(dev, EC_CMD_MKBP_INFO, 0, NULL, 0, info,
+		       sizeof(*info)) != sizeof(*info))
 		return -1;
 
 	return 0;
@@ -436,7 +608,7 @@ int cros_ec_get_host_events(struct cros_ec_dev *dev, uint32_t *events_ptr)
 	 * used by ACPI/SMI.
 	 */
 	if (ec_command_inptr(dev, EC_CMD_HOST_EVENT_GET_B, 0, NULL, 0,
-		       (uint8_t **)&resp, sizeof(*resp)) < sizeof(*resp))
+		       (uint8_t **)&resp, sizeof(*resp)) < (int)sizeof(*resp))
 		return -1;
 
 	if (resp->mask & EC_HOST_EVENT_MASK(EC_HOST_EVENT_INVALID))
@@ -474,7 +646,7 @@ int cros_ec_flash_protect(struct cros_ec_dev *dev,
 
 	if (ec_command(dev, EC_CMD_FLASH_PROTECT, EC_VER_FLASH_PROTECT,
 		       &params, sizeof(params),
-		       resp, sizeof(*resp)) < sizeof(*resp))
+		       resp, sizeof(*resp)) != sizeof(*resp))
 		return -1;
 
 	return 0;
@@ -504,23 +676,30 @@ static int cros_ec_check_version(struct cros_ec_dev *dev)
 	 *
 	 * So for now, just read all the data anyway.
 	 */
-	dev->cmd_version_is_supported = 1;
+
+	/* Try sending a version 3 packet */
+	dev->protocol_version = 3;
+	if (ec_command_inptr(dev, EC_CMD_HELLO, 0, &req, sizeof(req),
+			     (uint8_t **)&resp, sizeof(*resp)) > 0) {
+		return 0;
+	}
+
+	/* Try sending a version 2 packet */
+	dev->protocol_version = 2;
 	if (ec_command_inptr(dev, EC_CMD_HELLO, 0, &req, sizeof(req),
 		       (uint8_t **)&resp, sizeof(*resp)) > 0) {
-		/* It appears to understand new version commands */
-		dev->cmd_version_is_supported = 1;
-	} else {
-		dev->cmd_version_is_supported = 0;
-		if (ec_command_inptr(dev, EC_CMD_HELLO, 0, &req,
-			      sizeof(req), (uint8_t **)&resp,
-			      sizeof(*resp)) < 0) {
-			debug("%s: Failed both old and new command style\n",
-				__func__);
-			return -1;
-		}
+		return 0;
 	}
 
-	return 0;
+	/*
+	 * Fail if we're still here, since the EC doesn't understand any
+	 * protcol version we speak.  Version 1 interface without command
+	 * version is no longer supported, and we don't know about any new
+	 * protocol versions.
+	 */
+	dev->protocol_version = 0;
+	printf("%s: ERROR: old EC interface not supported\n", __func__);
+	return -1;
 }
 
 int cros_ec_test(struct cros_ec_dev *dev)
@@ -599,8 +778,8 @@ static int cros_ec_flash_write_block(struct cros_ec_dev *dev,
 
 	p.offset = offset;
 	p.size = size;
-	assert(data && p.size <= sizeof(p.data));
-	memcpy(p.data, data, p.size);
+	assert(data && p.size <= EC_FLASH_WRITE_VER0_SIZE);
+	memcpy(&p + 1, data, p.size);
 
 	return ec_command_inptr(dev, EC_CMD_FLASH_WRITE, 0,
 			  &p, sizeof(p), NULL, 0) >= 0 ? 0 : -1;
@@ -611,8 +790,7 @@ static int cros_ec_flash_write_block(struct cros_ec_dev *dev,
  */
 static int cros_ec_flash_write_burst_size(struct cros_ec_dev *dev)
 {
-	struct ec_params_flash_write p;
-	return sizeof(p.data);
+	return EC_FLASH_WRITE_VER0_SIZE;
 }
 
 /**
@@ -718,7 +896,7 @@ int cros_ec_flash_update_rw(struct cros_ec_dev *dev,
 
 	if (cros_ec_flash_offset(dev, EC_FLASH_REGION_RW, &rw_offset, &rw_size))
 		return -1;
-	if (image_size > rw_size)
+	if (image_size > (int)rw_size)
 		return -1;
 
 	/* Invalidate the existing hash, just in case the AP reboots
@@ -804,7 +982,7 @@ int cros_ec_get_ldo(struct cros_ec_dev *dev, uint8_t index, uint8_t *state)
 
 	if (ec_command_inptr(dev, EC_CMD_LDO_GET, 0,
 		       &params, sizeof(params),
-		       (uint8_t **)&resp, sizeof(*resp)) < sizeof(*resp))
+		       (uint8_t **)&resp, sizeof(*resp)) != sizeof(*resp))
 		return -1;
 
 	*state = resp->state;
@@ -813,7 +991,8 @@ int cros_ec_get_ldo(struct cros_ec_dev *dev, uint8_t index, uint8_t *state)
 }
 
 /**
- * Decode MBKP details from the device tree and allocate a suitable device.
+ * Decode EC interface details from the device tree and allocate a suitable
+ * device.
  *
  * @param blob		Device tree blob
  * @param node		Node to decode from
@@ -859,6 +1038,11 @@ static int cros_ec_decode_fdt(const void *blob, int node,
 		dev->interface = CROS_EC_IF_LPC;
 		break;
 #endif
+#ifdef CONFIG_CROS_EC_SANDBOX
+	case COMPAT_SANDBOX_HOST_EMULATION:
+		dev->interface = CROS_EC_IF_SANDBOX;
+		break;
+#endif
 	default:
 		debug("%s: Unknown compat id %d\n", __func__, compat);
 		return -1;
@@ -914,6 +1098,12 @@ int cros_ec_init(const void *blob, struct cros_ec_dev **cros_ecp)
 			return -CROS_EC_ERR_DEV_INIT;
 		break;
 #endif
+#ifdef CONFIG_CROS_EC_SANDBOX
+	case CROS_EC_IF_SANDBOX:
+		if (cros_ec_sandbox_init(dev, blob))
+			return -CROS_EC_ERR_DEV_INIT;
+		break;
+#endif
 	case CROS_EC_IF_NONE:
 	default:
 		return 0;
@@ -941,7 +1131,6 @@ int cros_ec_init(const void *blob, struct cros_ec_dev **cros_ecp)
 	return 0;
 }
 
-#ifdef CONFIG_CMD_CROS_EC
 int cros_ec_decode_region(int argc, char * const argv[])
 {
 	if (argc > 0) {
@@ -958,6 +1147,139 @@ int cros_ec_decode_region(int argc, char * const argv[])
 	return -1;
 }
 
+int cros_ec_decode_ec_flash(const void *blob, struct fdt_cros_ec *config)
+{
+	int flash_node, node;
+
+	node = fdtdec_next_compatible(blob, 0, COMPAT_GOOGLE_CROS_EC);
+	if (node < 0) {
+		debug("Failed to find chrome-ec node'\n");
+		return -1;
+	}
+
+	flash_node = fdt_subnode_offset(blob, node, "flash");
+	if (flash_node < 0) {
+		debug("Failed to find flash node\n");
+		return -1;
+	}
+
+	if (fdtdec_read_fmap_entry(blob, flash_node, "flash",
+				   &config->flash)) {
+		debug("Failed to decode flash node in chrome-ec'\n");
+		return -1;
+	}
+
+	config->flash_erase_value = fdtdec_get_int(blob, flash_node,
+						    "erase-value", -1);
+	for (node = fdt_first_subnode(blob, flash_node); node >= 0;
+	     node = fdt_next_subnode(blob, node)) {
+		const char *name = fdt_get_name(blob, node, NULL);
+		enum ec_flash_region region;
+
+		if (0 == strcmp(name, "ro")) {
+			region = EC_FLASH_REGION_RO;
+		} else if (0 == strcmp(name, "rw")) {
+			region = EC_FLASH_REGION_RW;
+		} else if (0 == strcmp(name, "wp-ro")) {
+			region = EC_FLASH_REGION_WP_RO;
+		} else {
+			debug("Unknown EC flash region name '%s'\n", name);
+			return -1;
+		}
+
+		if (fdtdec_read_fmap_entry(blob, node, "reg",
+					   &config->region[region])) {
+			debug("Failed to decode flash region in chrome-ec'\n");
+			return -1;
+		}
+	}
+
+	return 0;
+}
+
+int cros_ec_i2c_xfer(struct cros_ec_dev *dev, uchar chip, uint addr,
+		     int alen, uchar *buffer, int len, int is_read)
+{
+	union {
+		struct ec_params_i2c_passthru p;
+		uint8_t outbuf[EC_PROTO2_MAX_PARAM_SIZE];
+	} params;
+	union {
+		struct ec_response_i2c_passthru r;
+		uint8_t inbuf[EC_PROTO2_MAX_PARAM_SIZE];
+	} response;
+	struct ec_params_i2c_passthru *p = &params.p;
+	struct ec_response_i2c_passthru *r = &response.r;
+	struct ec_params_i2c_passthru_msg *msg = p->msg;
+	uint8_t *pdata;
+	int read_len, write_len;
+	int size;
+	int rv;
+
+	p->port = 0;
+
+	if (alen != 1) {
+		printf("Unsupported address length %d\n", alen);
+		return -1;
+	}
+	if (is_read) {
+		read_len = len;
+		write_len = alen;
+		p->num_msgs = 2;
+	} else {
+		read_len = 0;
+		write_len = alen + len;
+		p->num_msgs = 1;
+	}
+
+	size = sizeof(*p) + p->num_msgs * sizeof(*msg);
+	if (size + write_len > sizeof(params)) {
+		puts("Params too large for buffer\n");
+		return -1;
+	}
+	if (sizeof(*r) + read_len > sizeof(response)) {
+		puts("Read length too big for buffer\n");
+		return -1;
+	}
+
+	/* Create a message to write the register address and optional data */
+	pdata = (uint8_t *)p + size;
+	msg->addr_flags = chip;
+	msg->len = write_len;
+	pdata[0] = addr;
+	if (!is_read)
+		memcpy(pdata + 1, buffer, len);
+	msg++;
+
+	if (read_len) {
+		msg->addr_flags = chip | EC_I2C_FLAG_READ;
+		msg->len = read_len;
+	}
+
+	rv = ec_command(dev, EC_CMD_I2C_PASSTHRU, 0, p, size + write_len,
+			r, sizeof(*r) + read_len);
+	if (rv < 0)
+		return rv;
+
+	/* Parse response */
+	if (r->i2c_status & EC_I2C_STATUS_ERROR) {
+		printf("Transfer failed with status=0x%x\n", r->i2c_status);
+		return -1;
+	}
+
+	if (rv < sizeof(*r) + read_len) {
+		puts("Truncated read response\n");
+		return -1;
+	}
+
+	if (read_len)
+		memcpy(buffer, r->data, read_len);
+
+	return 0;
+}
+
+#ifdef CONFIG_CMD_CROS_EC
+
 /**
  * Perform a flash read or write command
  *
@@ -1011,6 +1333,187 @@ static int do_read_write(struct cros_ec_dev *dev, int is_write, int argc,
 	return 0;
 }
 
+/**
+ * get_alen() - Small parser helper function to get address length
+ *
+ * Returns the address length.
+ */
+static uint get_alen(char *arg)
+{
+	int	j;
+	int	alen;
+
+	alen = 1;
+	for (j = 0; j < 8; j++) {
+		if (arg[j] == '.') {
+			alen = arg[j+1] - '0';
+			break;
+		} else if (arg[j] == '\0') {
+			break;
+		}
+	}
+	return alen;
+}
+
+#define DISP_LINE_LEN	16
+
+/*
+ * TODO(sjg@chromium.org): This code copied almost verbatim from cmd_i2c.c
+ * so we can remove it later.
+ */
+static int cros_ec_i2c_md(struct cros_ec_dev *dev, int flag, int argc,
+			  char * const argv[])
+{
+	u_char	chip;
+	uint	addr, alen, length = 0x10;
+	int	j, nbytes, linebytes;
+
+	if (argc < 2)
+		return CMD_RET_USAGE;
+
+	if (1 || (flag & CMD_FLAG_REPEAT) == 0) {
+		/*
+		 * New command specified.
+		 */
+
+		/*
+		 * I2C chip address
+		 */
+		chip = simple_strtoul(argv[0], NULL, 16);
+
+		/*
+		 * I2C data address within the chip.  This can be 1 or
+		 * 2 bytes long.  Some day it might be 3 bytes long :-).
+		 */
+		addr = simple_strtoul(argv[1], NULL, 16);
+		alen = get_alen(argv[1]);
+		if (alen > 3)
+			return CMD_RET_USAGE;
+
+		/*
+		 * If another parameter, it is the length to display.
+		 * Length is the number of objects, not number of bytes.
+		 */
+		if (argc > 2)
+			length = simple_strtoul(argv[2], NULL, 16);
+	}
+
+	/*
+	 * Print the lines.
+	 *
+	 * We buffer all read data, so we can make sure data is read only
+	 * once.
+	 */
+	nbytes = length;
+	do {
+		unsigned char	linebuf[DISP_LINE_LEN];
+		unsigned char	*cp;
+
+		linebytes = (nbytes > DISP_LINE_LEN) ? DISP_LINE_LEN : nbytes;
+
+		if (cros_ec_i2c_xfer(dev, chip, addr, alen, linebuf, linebytes,
+				     1))
+			puts("Error reading the chip.\n");
+		else {
+			printf("%04x:", addr);
+			cp = linebuf;
+			for (j = 0; j < linebytes; j++) {
+				printf(" %02x", *cp++);
+				addr++;
+			}
+			puts("    ");
+			cp = linebuf;
+			for (j = 0; j < linebytes; j++) {
+				if ((*cp < 0x20) || (*cp > 0x7e))
+					puts(".");
+				else
+					printf("%c", *cp);
+				cp++;
+			}
+			putc('\n');
+		}
+		nbytes -= linebytes;
+	} while (nbytes > 0);
+
+	return 0;
+}
+
+static int cros_ec_i2c_mw(struct cros_ec_dev *dev, int flag, int argc,
+			  char * const argv[])
+{
+	uchar	chip;
+	ulong	addr;
+	uint	alen;
+	uchar	byte;
+	int	count;
+
+	if ((argc < 3) || (argc > 4))
+		return CMD_RET_USAGE;
+
+	/*
+	 * Chip is always specified.
+	 */
+	chip = simple_strtoul(argv[0], NULL, 16);
+
+	/*
+	 * Address is always specified.
+	 */
+	addr = simple_strtoul(argv[1], NULL, 16);
+	alen = get_alen(argv[1]);
+	if (alen > 3)
+		return CMD_RET_USAGE;
+
+	/*
+	 * Value to write is always specified.
+	 */
+	byte = simple_strtoul(argv[2], NULL, 16);
+
+	/*
+	 * Optional count
+	 */
+	if (argc == 4)
+		count = simple_strtoul(argv[3], NULL, 16);
+	else
+		count = 1;
+
+	while (count-- > 0) {
+		if (cros_ec_i2c_xfer(dev, chip, addr++, alen, &byte, 1, 0))
+			puts("Error writing the chip.\n");
+		/*
+		 * Wait for the write to complete.  The write can take
+		 * up to 10mSec (we allow a little more time).
+		 */
+/*
+ * No write delay with FRAM devices.
+ */
+#if !defined(CONFIG_SYS_I2C_FRAM)
+		udelay(11000);
+#endif
+	}
+
+	return 0;
+}
+
+/* Temporary code until we have driver model and can use the i2c command */
+static int cros_ec_i2c_passthrough(struct cros_ec_dev *dev, int flag,
+				   int argc, char * const argv[])
+{
+	const char *cmd;
+
+	if (argc < 1)
+		return CMD_RET_USAGE;
+	cmd = *argv++;
+	argc--;
+	if (0 == strcmp("md", cmd))
+		cros_ec_i2c_md(dev, flag, argc, argv);
+	else if (0 == strcmp("mw", cmd))
+		cros_ec_i2c_mw(dev, flag, argc, argv);
+	else
+		return CMD_RET_USAGE;
+
+	return 0;
+}
+
 static int do_cros_ec(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 {
 	struct cros_ec_dev *dev = last_dev;
@@ -1044,7 +1547,7 @@ static int do_cros_ec(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 		}
 		printf("%s\n", id);
 	} else if (0 == strcmp("info", cmd)) {
-		struct ec_response_cros_ec_info info;
+		struct ec_response_mkbp_info info;
 
 		if (cros_ec_info(dev, &info)) {
 			debug("%s: Could not read KBC info\n", __func__);
@@ -1213,10 +1716,10 @@ static int do_cros_ec(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 		if (!ret) {
 			/* Print versions */
 			printf("RO version:    %1.*s\n",
-			       sizeof(p->version_string_ro),
+			       (int)sizeof(p->version_string_ro),
 			       p->version_string_ro);
 			printf("RW version:    %1.*s\n",
-			       sizeof(p->version_string_rw),
+			       (int)sizeof(p->version_string_rw),
 			       p->version_string_rw);
 			printf("Firmware copy: %s\n",
 				(p->current_image <
@@ -1254,6 +1757,8 @@ static int do_cros_ec(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 			debug("%s: Could not access LDO%d\n", __func__, index);
 			return ret;
 		}
+	} else if (0 == strcmp("i2c", cmd)) {
+		ret = cros_ec_i2c_passthrough(dev, flag, argc - 2, argv + 2);
 	} else {
 		return CMD_RET_USAGE;
 	}
@@ -1267,7 +1772,7 @@ static int do_cros_ec(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 }
 
 U_BOOT_CMD(
-	crosec,	5,	1,	do_cros_ec,
+	crosec,	6,	1,	do_cros_ec,
 	"CROS-EC utility command",
 	"init                Re-init CROS-EC (done on startup automatically)\n"
 	"crosec id                  Read CROS-EC ID\n"
@@ -1284,6 +1789,8 @@ U_BOOT_CMD(
 	"crosec vbnvcontext [hexstring]        Read [write] VbNvContext from EC\n"
 	"crosec ldo <idx> [<state>] Switch/Read LDO state\n"
 	"crosec test                run tests on cros_ec\n"
-	"crosec version             Read CROS-EC version"
+	"crosec version             Read CROS-EC version\n"
+	"crosec i2c md chip address[.0, .1, .2] [# of objects] - read from I2C passthru\n"
+	"crosec i2c mw chip address[.0, .1, .2] value [count] - write to I2C passthru (fill)"
 );
 #endif
diff --git a/drivers/misc/cros_ec_i2c.c b/drivers/misc/cros_ec_i2c.c
index 0fbab991b5..513cdb1cb0 100644
--- a/drivers/misc/cros_ec_i2c.c
+++ b/drivers/misc/cros_ec_i2c.c
@@ -35,7 +35,7 @@ int cros_ec_i2c_command(struct cros_ec_dev *dev, uint8_t cmd, int cmd_version,
 	uint8_t *ptr;
 	/* Receive input data, so that args will be dword aligned */
 	uint8_t *in_ptr;
-	int ret;
+	int len, csum, ret;
 
 	old_bus = i2c_get_bus_num();
 
@@ -67,24 +67,24 @@ int cros_ec_i2c_command(struct cros_ec_dev *dev, uint8_t cmd, int cmd_version,
 	 * will be dword aligned.
 	 */
 	in_ptr = dev->din + sizeof(int64_t);
-	if (!dev->cmd_version_is_supported) {
-		/* Send an old-style command */
-		*ptr++ = cmd;
-		out_bytes = dout_len + 1;
-		in_bytes = din_len + 2;
-		in_ptr--;	/* Expect just a status byte */
-	} else {
-		*ptr++ = EC_CMD_VERSION0 + cmd_version;
-		*ptr++ = cmd;
-		*ptr++ = dout_len;
-		in_ptr -= 2;	/* Expect status, length bytes */
+
+	if (dev->protocol_version != 2) {
+		/* Something we don't support */
+		debug("%s: Protocol version %d unsupported\n",
+		      __func__, dev->protocol_version);
+		return -1;
 	}
+
+	*ptr++ = EC_CMD_VERSION0 + cmd_version;
+	*ptr++ = cmd;
+	*ptr++ = dout_len;
+	in_ptr -= 2;	/* Expect status, length bytes */
+
 	memcpy(ptr, dout, dout_len);
 	ptr += dout_len;
 
-	if (dev->cmd_version_is_supported)
-		*ptr++ = (uint8_t)
-			 cros_ec_calc_checksum(dev->dout, dout_len + 3);
+	*ptr++ = (uint8_t)
+		cros_ec_calc_checksum(dev->dout, dout_len + 3);
 
 	/* Set to the proper i2c bus */
 	if (i2c_set_bus_num(dev->bus_num)) {
@@ -121,26 +121,20 @@ int cros_ec_i2c_command(struct cros_ec_dev *dev, uint8_t cmd, int cmd_version,
 		return -(int)*in_ptr;
 	}
 
-	if (dev->cmd_version_is_supported) {
-		int len, csum;
-
-		len = in_ptr[1];
-		if (len + 3 > sizeof(dev->din)) {
-			debug("%s: Received length %#02x too large\n",
-			      __func__, len);
-			return -1;
-		}
-		csum = cros_ec_calc_checksum(in_ptr, 2 + len);
-		if (csum != in_ptr[2 + len]) {
-			debug("%s: Invalid checksum rx %#02x, calced %#02x\n",
-			      __func__, in_ptr[2 + din_len], csum);
-			return -1;
-		}
-		din_len = min(din_len, len);
-		cros_ec_dump_data("in", -1, in_ptr, din_len + 3);
-	} else {
-		cros_ec_dump_data("in (old)", -1, in_ptr, in_bytes);
+	len = in_ptr[1];
+	if (len + 3 > sizeof(dev->din)) {
+		debug("%s: Received length %#02x too large\n",
+		      __func__, len);
+		return -1;
 	}
+	csum = cros_ec_calc_checksum(in_ptr, 2 + len);
+	if (csum != in_ptr[2 + len]) {
+		debug("%s: Invalid checksum rx %#02x, calced %#02x\n",
+		      __func__, in_ptr[2 + din_len], csum);
+		return -1;
+	}
+	din_len = min(din_len, len);
+	cros_ec_dump_data("in", -1, in_ptr, din_len + 3);
 
 	/* Return pointer to dword-aligned input data, if any */
 	*dinp = dev->din + sizeof(int64_t);
@@ -178,7 +172,5 @@ int cros_ec_i2c_init(struct cros_ec_dev *dev, const void *blob)
 {
 	i2c_init(dev->max_frequency, dev->addr);
 
-	dev->cmd_version_is_supported = 0;
-
 	return 0;
 }
diff --git a/drivers/misc/cros_ec_lpc.c b/drivers/misc/cros_ec_lpc.c
index 725747693d..0e02671c93 100644
--- a/drivers/misc/cros_ec_lpc.c
+++ b/drivers/misc/cros_ec_lpc.c
@@ -40,71 +40,6 @@ static int wait_for_sync(struct cros_ec_dev *dev)
 	return 0;
 }
 
-/**
- * Send a command to a LPC CROS_EC device and return the reply.
- *
- * The device's internal input/output buffers are used.
- *
- * @param dev		CROS_EC device
- * @param cmd		Command to send (EC_CMD_...)
- * @param cmd_version	Version of command to send (EC_VER_...)
- * @param dout          Output data (may be NULL If dout_len=0)
- * @param dout_len      Size of output data in bytes
- * @param dinp          Place to put pointer to response data
- * @param din_len       Maximum size of response in bytes
- * @return number of bytes in response, or -1 on error
- */
-static int old_lpc_command(struct cros_ec_dev *dev, uint8_t cmd,
-		     const uint8_t *dout, int dout_len,
-		     uint8_t **dinp, int din_len)
-{
-	int ret, i;
-
-	if (dout_len > EC_OLD_PARAM_SIZE) {
-		debug("%s: Cannot send %d bytes\n", __func__, dout_len);
-		return -1;
-	}
-
-	if (din_len > EC_OLD_PARAM_SIZE) {
-		debug("%s: Cannot receive %d bytes\n", __func__, din_len);
-		return -1;
-	}
-
-	if (wait_for_sync(dev)) {
-		debug("%s: Timeout waiting ready\n", __func__);
-		return -1;
-	}
-
-	debug_trace("cmd: %02x, ", cmd);
-	for (i = 0; i < dout_len; i++) {
-		debug_trace("%02x ", dout[i]);
-		outb(dout[i], EC_LPC_ADDR_OLD_PARAM + i);
-	}
-	outb(cmd, EC_LPC_ADDR_HOST_CMD);
-	debug_trace("\n");
-
-	if (wait_for_sync(dev)) {
-		debug("%s: Timeout waiting ready\n", __func__);
-		return -1;
-	}
-
-	ret = inb(EC_LPC_ADDR_HOST_DATA);
-	if (ret) {
-		debug("%s: CROS_EC result code %d\n", __func__, ret);
-		return -ret;
-	}
-
-	debug_trace("resp: %02x, ", ret);
-	for (i = 0; i < din_len; i++) {
-		dev->din[i] = inb(EC_LPC_ADDR_OLD_PARAM + i);
-		debug_trace("%02x ", dev->din[i]);
-	}
-	debug_trace("\n");
-	*dinp = dev->din;
-
-	return din_len;
-}
-
 int cros_ec_lpc_command(struct cros_ec_dev *dev, uint8_t cmd, int cmd_version,
 		     const uint8_t *dout, int dout_len,
 		     uint8_t **dinp, int din_len)
@@ -119,11 +54,6 @@ int cros_ec_lpc_command(struct cros_ec_dev *dev, uint8_t cmd, int cmd_version,
 	int csum;
 	int i;
 
-	/* Fall back to old-style command interface if args aren't supported */
-	if (!dev->cmd_version_is_supported)
-		return old_lpc_command(dev, cmd, dout, dout_len, dinp,
-				       din_len);
-
 	if (dout_len > EC_HOST_PARAM_SIZE) {
 		debug("%s: Cannot send %d bytes\n", __func__, dout_len);
 		return -1;
@@ -256,13 +186,9 @@ int cros_ec_lpc_check_version(struct cros_ec_dev *dev)
 			(inb(EC_LPC_ADDR_MEMMAP +
 				EC_MEMMAP_HOST_CMD_FLAGS) &
 				EC_HOST_CMD_FLAG_LPC_ARGS_SUPPORTED)) {
-		dev->cmd_version_is_supported = 1;
-	} else {
-		/* We are going to use the old IO ports */
-		dev->cmd_version_is_supported = 0;
+		return 0;
 	}
-	debug("lpc: version %s\n", dev->cmd_version_is_supported ?
-			"new" : "old");
 
-	return 0;
+	printf("%s: ERROR: old EC interface not supported\n", __func__);
+	return -1;
 }
diff --git a/drivers/misc/cros_ec_sandbox.c b/drivers/misc/cros_ec_sandbox.c
new file mode 100644
index 0000000000..4bb1d60e5a
--- /dev/null
+++ b/drivers/misc/cros_ec_sandbox.c
@@ -0,0 +1,559 @@
+/*
+ * Chromium OS cros_ec driver - sandbox emulation
+ *
+ * Copyright (c) 2013 The Chromium OS Authors.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <cros_ec.h>
+#include <ec_commands.h>
+#include <errno.h>
+#include <hash.h>
+#include <malloc.h>
+#include <os.h>
+#include <sha256.h>
+#include <spi.h>
+#include <asm/state.h>
+#include <asm/sdl.h>
+#include <linux/input.h>
+
+/*
+ * Ultimately it shold be possible to connect an Chrome OS EC emulation
+ * to U-Boot and remove all of this code. But this provides a test
+ * environment for bringing up chromeos_sandbox and demonstrating its
+ * utility.
+ *
+ * This emulation includes the following:
+ *
+ * 1. Emulation of the keyboard, by converting keypresses received from SDL
+ * into key scan data, passed back from the EC as key scan messages. The
+ * key layout is read from the device tree.
+ *
+ * 2. Emulation of vboot context - so this can be read/written as required.
+ *
+ * 3. Save/restore of EC state, so that the vboot context, flash memory
+ * contents and current image can be preserved across boots. This is important
+ * since the EC is supposed to continue running even if the AP resets.
+ *
+ * 4. Some event support, in particular allowing Escape to be pressed on boot
+ * to enter recovery mode. The EC passes this to U-Boot through the normal
+ * event message.
+ *
+ * 5. Flash read/write/erase support, so that software sync works. The
+ * protect messages are supported but no protection is implemented.
+ *
+ * 6. Hashing of the EC image, again to support software sync.
+ *
+ * Other features can be added, although a better path is probably to link
+ * the EC image in with U-Boot (Vic has demonstrated a prototype for this).
+ */
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define KEYBOARD_ROWS	8
+#define KEYBOARD_COLS	13
+
+/* A single entry of the key matrix */
+struct ec_keymatrix_entry {
+	int row;	/* key matrix row */
+	int col;	/* key matrix column */
+	int keycode;	/* corresponding linux key code */
+};
+
+/**
+ * struct ec_state - Information about the EC state
+ *
+ * @vbnv_context: Vboot context data stored by EC
+ * @ec_config: FDT config information about the EC (e.g. flashmap)
+ * @flash_data: Contents of flash memory
+ * @flash_data_len: Size of flash memory
+ * @current_image: Current image the EC is running
+ * @matrix_count: Number of keys to decode in matrix
+ * @matrix: Information about keyboard matrix
+ * @keyscan: Current keyscan information (bit set for each row/column pressed)
+ * @recovery_req: Keyboard recovery requested
+ */
+struct ec_state {
+	uint8_t vbnv_context[EC_VBNV_BLOCK_SIZE];
+	struct fdt_cros_ec ec_config;
+	uint8_t *flash_data;
+	int flash_data_len;
+	enum ec_current_image current_image;
+	int matrix_count;
+	struct ec_keymatrix_entry *matrix;	/* the key matrix info */
+	uint8_t keyscan[KEYBOARD_COLS];
+	bool recovery_req;
+} s_state, *state;
+
+/**
+ * cros_ec_read_state() - read the sandbox EC state from the state file
+ *
+ * If data is available, then blob and node will provide access to it. If
+ * not this function sets up an empty EC.
+ *
+ * @param blob: Pointer to device tree blob, or NULL if no data to read
+ * @param node: Node offset to read from
+ */
+static int cros_ec_read_state(const void *blob, int node)
+{
+	struct ec_state *ec = &s_state;
+	const char *prop;
+	int len;
+
+	/* Set everything to defaults */
+	ec->current_image = EC_IMAGE_RO;
+	if (!blob)
+		return 0;
+
+	/* Read the data if available */
+	ec->current_image = fdtdec_get_int(blob, node, "current-image",
+					   EC_IMAGE_RO);
+	prop = fdt_getprop(blob, node, "vbnv-context", &len);
+	if (prop && len == sizeof(ec->vbnv_context))
+		memcpy(ec->vbnv_context, prop, len);
+
+	prop = fdt_getprop(blob, node, "flash-data", &len);
+	if (prop) {
+		ec->flash_data_len = len;
+		ec->flash_data = os_malloc(len);
+		if (!ec->flash_data)
+			return -ENOMEM;
+		memcpy(ec->flash_data, prop, len);
+		debug("%s: Loaded EC flash data size %#x\n", __func__, len);
+	}
+
+	return 0;
+}
+
+/**
+ * cros_ec_write_state() - Write out our state to the state file
+ *
+ * The caller will ensure that there is a node ready for the state. The node
+ * may already contain the old state, in which case it is overridden.
+ *
+ * @param blob: Device tree blob holding state
+ * @param node: Node to write our state into
+ */
+static int cros_ec_write_state(void *blob, int node)
+{
+	struct ec_state *ec = &s_state;
+
+	/* We are guaranteed enough space to write basic properties */
+	fdt_setprop_u32(blob, node, "current-image", ec->current_image);
+	fdt_setprop(blob, node, "vbnv-context", ec->vbnv_context,
+		    sizeof(ec->vbnv_context));
+	return state_setprop(node, "flash-data", ec->flash_data,
+			     ec->ec_config.flash.length);
+}
+
+SANDBOX_STATE_IO(cros_ec, "google,cros-ec", cros_ec_read_state,
+		 cros_ec_write_state);
+
+/**
+ * Return the number of bytes used in the specified image.
+ *
+ * This is the actual size of code+data in the image, as opposed to the
+ * amount of space reserved in flash for that image. This code is similar to
+ * that used by the real EC code base.
+ *
+ * @param ec	Current emulated EC state
+ * @param entry	Flash map entry containing the image to check
+ * @return actual image size in bytes, 0 if the image contains no content or
+ * error.
+ */
+static int get_image_used(struct ec_state *ec, struct fmap_entry *entry)
+{
+	int size;
+
+	/*
+	 * Scan backwards looking for 0xea byte, which is by definition the
+	 * last byte of the image.  See ec.lds.S for how this is inserted at
+	 * the end of the image.
+	 */
+	for (size = entry->length - 1;
+	     size > 0 && ec->flash_data[entry->offset + size] != 0xea;
+	     size--)
+		;
+
+	return size ? size + 1 : 0;  /* 0xea byte IS part of the image */
+}
+
+/**
+ * Read the key matrix from the device tree
+ *
+ * Keymap entries in the fdt take the form of 0xRRCCKKKK where
+ * RR=Row CC=Column KKKK=Key Code
+ *
+ * @param ec	Current emulated EC state
+ * @param blob	Device tree blob containing keyscan information
+ * @param node	Keyboard node of device tree containing keyscan information
+ * @return 0 if ok, -1 on error
+ */
+static int keyscan_read_fdt_matrix(struct ec_state *ec, const void *blob,
+				   int node)
+{
+	const u32 *cell;
+	int upto;
+	int len;
+
+	cell = fdt_getprop(blob, node, "linux,keymap", &len);
+	ec->matrix_count = len / 4;
+	ec->matrix = calloc(ec->matrix_count, sizeof(*ec->matrix));
+	if (!ec->matrix) {
+		debug("%s: Out of memory for key matrix\n", __func__);
+		return -1;
+	}
+
+	/* Now read the data */
+	for (upto = 0; upto < ec->matrix_count; upto++) {
+		struct ec_keymatrix_entry *matrix = &ec->matrix[upto];
+		u32 word;
+
+		word = fdt32_to_cpu(*cell++);
+		matrix->row = word >> 24;
+		matrix->col = (word >> 16) & 0xff;
+		matrix->keycode = word & 0xffff;
+
+		/* Hard-code some sanity limits for now */
+		if (matrix->row >= KEYBOARD_ROWS ||
+		    matrix->col >= KEYBOARD_COLS) {
+			debug("%s: Matrix pos out of range (%d,%d)\n",
+			      __func__, matrix->row, matrix->col);
+			return -1;
+		}
+	}
+
+	if (upto != ec->matrix_count) {
+		debug("%s: Read mismatch from key matrix\n", __func__);
+		return -1;
+	}
+
+	return 0;
+}
+
+/**
+ * Return the next keyscan message contents
+ *
+ * @param ec	Current emulated EC state
+ * @param scan	Place to put keyscan bytes for the keyscan message (must hold
+ *		enough space for a full keyscan)
+ * @return number of bytes of valid scan data
+ */
+static int cros_ec_keyscan(struct ec_state *ec, uint8_t *scan)
+{
+	const struct ec_keymatrix_entry *matrix;
+	int bytes = KEYBOARD_COLS;
+	int key[8];	/* allow up to 8 keys to be pressed at once */
+	int count;
+	int i;
+
+	memset(ec->keyscan, '\0', bytes);
+	count = sandbox_sdl_scan_keys(key, ARRAY_SIZE(key));
+
+	/* Look up keycode in matrix */
+	for (i = 0, matrix = ec->matrix; i < ec->matrix_count; i++, matrix++) {
+		bool found;
+		int j;
+
+		for (found = false, j = 0; j < count; j++) {
+			if (matrix->keycode == key[j])
+				found = true;
+		}
+
+		if (found) {
+			debug("%d: %d,%d\n", matrix->keycode, matrix->row,
+			      matrix->col);
+			ec->keyscan[matrix->col] |= 1 << matrix->row;
+		}
+	}
+
+	memcpy(scan, ec->keyscan, bytes);
+	return bytes;
+}
+
+/**
+ * Process an emulated EC command
+ *
+ * @param ec		Current emulated EC state
+ * @param req_hdr	Pointer to request header
+ * @param req_data	Pointer to body of request
+ * @param resp_hdr	Pointer to place to put response header
+ * @param resp_data	Pointer to place to put response data, if any
+ * @return length of response data, or 0 for no response data, or -1 on error
+ */
+static int process_cmd(struct ec_state *ec,
+		       struct ec_host_request *req_hdr, const void *req_data,
+		       struct ec_host_response *resp_hdr, void *resp_data)
+{
+	int len;
+
+	/* TODO(sjg@chromium.org): Check checksums */
+	debug("EC command %#0x\n", req_hdr->command);
+
+	switch (req_hdr->command) {
+	case EC_CMD_HELLO: {
+		const struct ec_params_hello *req = req_data;
+		struct ec_response_hello *resp = resp_data;
+
+		resp->out_data = req->in_data + 0x01020304;
+		len = sizeof(*resp);
+		break;
+	}
+	case EC_CMD_GET_VERSION: {
+		struct ec_response_get_version *resp = resp_data;
+
+		strcpy(resp->version_string_ro, "sandbox_ro");
+		strcpy(resp->version_string_rw, "sandbox_rw");
+		resp->current_image = ec->current_image;
+		debug("Current image %d\n", resp->current_image);
+		len = sizeof(*resp);
+		break;
+	}
+	case EC_CMD_VBNV_CONTEXT: {
+		const struct ec_params_vbnvcontext *req = req_data;
+		struct ec_response_vbnvcontext *resp = resp_data;
+
+		switch (req->op) {
+		case EC_VBNV_CONTEXT_OP_READ:
+			memcpy(resp->block, ec->vbnv_context,
+			       sizeof(resp->block));
+			len = sizeof(*resp);
+			break;
+		case EC_VBNV_CONTEXT_OP_WRITE:
+			memcpy(ec->vbnv_context, resp->block,
+			       sizeof(resp->block));
+			len = 0;
+			break;
+		default:
+			printf("   ** Unknown vbnv_context command %#02x\n",
+			       req->op);
+			return -1;
+		}
+		break;
+	}
+	case EC_CMD_REBOOT_EC: {
+		const struct ec_params_reboot_ec *req = req_data;
+
+		printf("Request reboot type %d\n", req->cmd);
+		switch (req->cmd) {
+		case EC_REBOOT_DISABLE_JUMP:
+			len = 0;
+			break;
+		case EC_REBOOT_JUMP_RW:
+			ec->current_image = EC_IMAGE_RW;
+			len = 0;
+			break;
+		default:
+			puts("   ** Unknown type");
+			return -1;
+		}
+		break;
+	}
+	case EC_CMD_HOST_EVENT_GET_B: {
+		struct ec_response_host_event_mask *resp = resp_data;
+
+		resp->mask = 0;
+		if (ec->recovery_req) {
+			resp->mask |= EC_HOST_EVENT_MASK(
+					EC_HOST_EVENT_KEYBOARD_RECOVERY);
+		}
+
+		len = sizeof(*resp);
+		break;
+	}
+	case EC_CMD_VBOOT_HASH: {
+		const struct ec_params_vboot_hash *req = req_data;
+		struct ec_response_vboot_hash *resp = resp_data;
+		struct fmap_entry *entry;
+		int ret, size;
+
+		entry = &state->ec_config.region[EC_FLASH_REGION_RW];
+
+		switch (req->cmd) {
+		case EC_VBOOT_HASH_RECALC:
+		case EC_VBOOT_HASH_GET:
+			size = SHA256_SUM_LEN;
+			len = get_image_used(ec, entry);
+			ret = hash_block("sha256",
+					 ec->flash_data + entry->offset,
+					 len, resp->hash_digest, &size);
+			if (ret) {
+				printf("   ** hash_block() failed\n");
+				return -1;
+			}
+			resp->status = EC_VBOOT_HASH_STATUS_DONE;
+			resp->hash_type = EC_VBOOT_HASH_TYPE_SHA256;
+			resp->digest_size = size;
+			resp->reserved0 = 0;
+			resp->offset = entry->offset;
+			resp->size = len;
+			len = sizeof(*resp);
+			break;
+		default:
+			printf("   ** EC_CMD_VBOOT_HASH: Unknown command %d\n",
+			       req->cmd);
+			return -1;
+		}
+		break;
+	}
+	case EC_CMD_FLASH_PROTECT: {
+		const struct ec_params_flash_protect *req = req_data;
+		struct ec_response_flash_protect *resp = resp_data;
+		uint32_t expect = EC_FLASH_PROTECT_ALL_NOW |
+				EC_FLASH_PROTECT_ALL_AT_BOOT;
+
+		printf("mask=%#x, flags=%#x\n", req->mask, req->flags);
+		if (req->flags == expect || req->flags == 0) {
+			resp->flags = req->flags ? EC_FLASH_PROTECT_ALL_NOW :
+								0;
+			resp->valid_flags = EC_FLASH_PROTECT_ALL_NOW;
+			resp->writable_flags = 0;
+			len = sizeof(*resp);
+		} else {
+			puts("   ** unexpected flash protect request\n");
+			return -1;
+		}
+		break;
+	}
+	case EC_CMD_FLASH_REGION_INFO: {
+		const struct ec_params_flash_region_info *req = req_data;
+		struct ec_response_flash_region_info *resp = resp_data;
+		struct fmap_entry *entry;
+
+		switch (req->region) {
+		case EC_FLASH_REGION_RO:
+		case EC_FLASH_REGION_RW:
+		case EC_FLASH_REGION_WP_RO:
+			entry = &state->ec_config.region[req->region];
+			resp->offset = entry->offset;
+			resp->size = entry->length;
+			len = sizeof(*resp);
+			printf("EC flash region %d: offset=%#x, size=%#x\n",
+			       req->region, resp->offset, resp->size);
+			break;
+		default:
+			printf("** Unknown flash region %d\n", req->region);
+			return -1;
+		}
+		break;
+	}
+	case EC_CMD_FLASH_ERASE: {
+		const struct ec_params_flash_erase *req = req_data;
+
+		memset(ec->flash_data + req->offset,
+		       ec->ec_config.flash_erase_value,
+		       req->size);
+		len = 0;
+		break;
+	}
+	case EC_CMD_FLASH_WRITE: {
+		const struct ec_params_flash_write *req = req_data;
+
+		memcpy(ec->flash_data + req->offset, req + 1, req->size);
+		len = 0;
+		break;
+	}
+	case EC_CMD_MKBP_STATE:
+		len = cros_ec_keyscan(ec, resp_data);
+		break;
+	default:
+		printf("   ** Unknown EC command %#02x\n", req_hdr->command);
+		return -1;
+	}
+
+	return len;
+}
+
+int cros_ec_sandbox_packet(struct cros_ec_dev *dev, int out_bytes,
+			   int in_bytes)
+{
+	struct ec_host_request *req_hdr = (struct ec_host_request *)dev->dout;
+	const void *req_data = req_hdr + 1;
+	struct ec_host_response *resp_hdr = (struct ec_host_response *)dev->din;
+	void *resp_data = resp_hdr + 1;
+	int len;
+
+	len = process_cmd(&s_state, req_hdr, req_data, resp_hdr, resp_data);
+	if (len < 0)
+		return len;
+
+	resp_hdr->struct_version = 3;
+	resp_hdr->result = EC_RES_SUCCESS;
+	resp_hdr->data_len = len;
+	resp_hdr->reserved = 0;
+	len += sizeof(*resp_hdr);
+	resp_hdr->checksum = 0;
+	resp_hdr->checksum = (uint8_t)
+		-cros_ec_calc_checksum((const uint8_t *)resp_hdr, len);
+
+	return in_bytes;
+}
+
+int cros_ec_sandbox_decode_fdt(struct cros_ec_dev *dev, const void *blob)
+{
+	return 0;
+}
+
+void cros_ec_check_keyboard(struct cros_ec_dev *dev)
+{
+	struct ec_state *ec = &s_state;
+	ulong start;
+
+	printf("Press keys for EC to detect on reset (ESC=recovery)...");
+	start = get_timer(0);
+	while (get_timer(start) < 1000)
+		;
+	putc('\n');
+	if (!sandbox_sdl_key_pressed(KEY_ESC)) {
+		ec->recovery_req = true;
+		printf("   - EC requests recovery\n");
+	}
+}
+
+/**
+ * Initialize sandbox EC emulation.
+ *
+ * @param dev		CROS_EC device
+ * @param blob		Device tree blob
+ * @return 0 if ok, -1 on error
+ */
+int cros_ec_sandbox_init(struct cros_ec_dev *dev, const void *blob)
+{
+	struct ec_state *ec = &s_state;
+	int node;
+	int err;
+
+	state = &s_state;
+	err = cros_ec_decode_ec_flash(blob, &ec->ec_config);
+	if (err)
+		return err;
+
+	node = fdtdec_next_compatible(blob, 0, COMPAT_GOOGLE_CROS_EC_KEYB);
+	if (node < 0) {
+		debug("%s: No cros_ec keyboard found\n", __func__);
+	} else if (keyscan_read_fdt_matrix(ec, blob, node)) {
+		debug("%s: Could not read key matrix\n", __func__);
+		return -1;
+	}
+
+	/* If we loaded EC data, check that the length matches */
+	if (ec->flash_data &&
+	    ec->flash_data_len != ec->ec_config.flash.length) {
+		printf("EC data length is %x, expected %x, discarding data\n",
+		       ec->flash_data_len, ec->ec_config.flash.length);
+		os_free(ec->flash_data);
+		ec->flash_data = NULL;
+	}
+
+	/* Otherwise allocate the memory */
+	if (!ec->flash_data) {
+		ec->flash_data_len = ec->ec_config.flash.length;
+		ec->flash_data = os_malloc(ec->flash_data_len);
+		if (!ec->flash_data)
+			return -ENOMEM;
+	}
+
+	return 0;
+}
diff --git a/drivers/misc/cros_ec_spi.c b/drivers/misc/cros_ec_spi.c
index 202acf258b..7df709cc71 100644
--- a/drivers/misc/cros_ec_spi.c
+++ b/drivers/misc/cros_ec_spi.c
@@ -17,6 +17,30 @@
 #include <cros_ec.h>
 #include <spi.h>
 
+int cros_ec_spi_packet(struct cros_ec_dev *dev, int out_bytes, int in_bytes)
+{
+	int rv;
+
+	/* Do the transfer */
+	if (spi_claim_bus(dev->spi)) {
+		debug("%s: Cannot claim SPI bus\n", __func__);
+		return -1;
+	}
+
+	rv = spi_xfer(dev->spi, max(out_bytes, in_bytes) * 8,
+		      dev->dout, dev->din,
+		      SPI_XFER_BEGIN | SPI_XFER_END);
+
+	spi_release_bus(dev->spi);
+
+	if (rv) {
+		debug("%s: Cannot complete SPI transfer\n", __func__);
+		return -1;
+	}
+
+	return in_bytes;
+}
+
 /**
  * Send a command to a LPC CROS_EC device and return the reply.
  *
@@ -42,6 +66,12 @@ int cros_ec_spi_command(struct cros_ec_dev *dev, uint8_t cmd, int cmd_version,
 	int csum, len;
 	int rv;
 
+	if (dev->protocol_version != 2) {
+		debug("%s: Unsupported EC protcol version %d\n",
+		      __func__, dev->protocol_version);
+		return -1;
+	}
+
 	/*
 	 * Sanity-check input size to make sure it plus transaction overhead
 	 * fits in the internal device buffer.
@@ -135,8 +165,7 @@ int cros_ec_spi_decode_fdt(struct cros_ec_dev *dev, const void *blob)
  */
 int cros_ec_spi_init(struct cros_ec_dev *dev, const void *blob)
 {
-	dev->spi = spi_setup_slave_fdt(blob, dev->parent_node,
-				       dev->cs, dev->max_frequency, 0);
+	dev->spi = spi_setup_slave_fdt(blob, dev->parent_node, dev->node);
 	if (!dev->spi) {
 		debug("%s: Could not setup SPI slave\n", __func__);
 		return -1;
diff --git a/drivers/misc/fsl_ifc.c b/drivers/misc/fsl_ifc.c
new file mode 100644
index 0000000000..be61973667
--- /dev/null
+++ b/drivers/misc/fsl_ifc.c
@@ -0,0 +1,164 @@
+/*
+ * Copyright 2010-2011 Freescale Semiconductor, Inc.
+ * Author: Dipen Dudhat <dipen.dudhat@freescale.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <fsl_ifc.h>
+
+void print_ifc_regs(void)
+{
+	int i, j;
+
+	printf("IFC Controller Registers\n");
+	for (i = 0; i < CONFIG_SYS_FSL_IFC_BANK_COUNT; i++) {
+		printf("CSPR%d:0x%08X\tAMASK%d:0x%08X\tCSOR%d:0x%08X\n",
+			i, get_ifc_cspr(i), i, get_ifc_amask(i),
+			i, get_ifc_csor(i));
+		for (j = 0; j < 4; j++)
+			printf("IFC_FTIM%d:0x%08X\n", j, get_ifc_ftim(i, j));
+	}
+}
+
+void init_early_memctl_regs(void)
+{
+#if defined(CONFIG_SYS_CSPR0) && defined(CONFIG_SYS_CSOR0)
+	set_ifc_ftim(IFC_CS0, IFC_FTIM0, CONFIG_SYS_CS0_FTIM0);
+	set_ifc_ftim(IFC_CS0, IFC_FTIM1, CONFIG_SYS_CS0_FTIM1);
+	set_ifc_ftim(IFC_CS0, IFC_FTIM2, CONFIG_SYS_CS0_FTIM2);
+	set_ifc_ftim(IFC_CS0, IFC_FTIM3, CONFIG_SYS_CS0_FTIM3);
+
+#ifndef CONFIG_A003399_NOR_WORKAROUND
+#ifdef CONFIG_SYS_CSPR0_EXT
+	set_ifc_cspr_ext(IFC_CS0, CONFIG_SYS_CSPR0_EXT);
+#endif
+#ifdef CONFIG_SYS_CSOR0_EXT
+	set_ifc_csor_ext(IFC_CS0, CONFIG_SYS_CSOR0_EXT);
+#endif
+	set_ifc_cspr(IFC_CS0, CONFIG_SYS_CSPR0);
+	set_ifc_amask(IFC_CS0, CONFIG_SYS_AMASK0);
+	set_ifc_csor(IFC_CS0, CONFIG_SYS_CSOR0);
+#endif
+#endif
+
+#ifdef CONFIG_SYS_CSPR1_EXT
+	set_ifc_cspr_ext(IFC_CS1, CONFIG_SYS_CSPR1_EXT);
+#endif
+#ifdef CONFIG_SYS_CSOR1_EXT
+	set_ifc_csor_ext(IFC_CS1, CONFIG_SYS_CSOR1_EXT);
+#endif
+#if defined(CONFIG_SYS_CSPR1) && defined(CONFIG_SYS_CSOR1)
+	set_ifc_ftim(IFC_CS1, IFC_FTIM0, CONFIG_SYS_CS1_FTIM0);
+	set_ifc_ftim(IFC_CS1, IFC_FTIM1, CONFIG_SYS_CS1_FTIM1);
+	set_ifc_ftim(IFC_CS1, IFC_FTIM2, CONFIG_SYS_CS1_FTIM2);
+	set_ifc_ftim(IFC_CS1, IFC_FTIM3, CONFIG_SYS_CS1_FTIM3);
+
+	set_ifc_csor(IFC_CS1, CONFIG_SYS_CSOR1);
+	set_ifc_amask(IFC_CS1, CONFIG_SYS_AMASK1);
+	set_ifc_cspr(IFC_CS1, CONFIG_SYS_CSPR1);
+#endif
+
+#ifdef CONFIG_SYS_CSPR2_EXT
+	set_ifc_cspr_ext(IFC_CS2, CONFIG_SYS_CSPR2_EXT);
+#endif
+#ifdef CONFIG_SYS_CSOR2_EXT
+	set_ifc_csor_ext(IFC_CS2, CONFIG_SYS_CSOR2_EXT);
+#endif
+#if defined(CONFIG_SYS_CSPR2) && defined(CONFIG_SYS_CSOR2)
+	set_ifc_ftim(IFC_CS2, IFC_FTIM0, CONFIG_SYS_CS2_FTIM0);
+	set_ifc_ftim(IFC_CS2, IFC_FTIM1, CONFIG_SYS_CS2_FTIM1);
+	set_ifc_ftim(IFC_CS2, IFC_FTIM2, CONFIG_SYS_CS2_FTIM2);
+	set_ifc_ftim(IFC_CS2, IFC_FTIM3, CONFIG_SYS_CS2_FTIM3);
+
+	set_ifc_csor(IFC_CS2, CONFIG_SYS_CSOR2);
+	set_ifc_amask(IFC_CS2, CONFIG_SYS_AMASK2);
+	set_ifc_cspr(IFC_CS2, CONFIG_SYS_CSPR2);
+#endif
+
+#ifdef CONFIG_SYS_CSPR3_EXT
+	set_ifc_cspr_ext(IFC_CS3, CONFIG_SYS_CSPR3_EXT);
+#endif
+#ifdef CONFIG_SYS_CSOR3_EXT
+	set_ifc_csor_ext(IFC_CS3, CONFIG_SYS_CSOR3_EXT);
+#endif
+#if defined(CONFIG_SYS_CSPR3) && defined(CONFIG_SYS_CSOR3)
+	set_ifc_ftim(IFC_CS3, IFC_FTIM0, CONFIG_SYS_CS3_FTIM0);
+	set_ifc_ftim(IFC_CS3, IFC_FTIM1, CONFIG_SYS_CS3_FTIM1);
+	set_ifc_ftim(IFC_CS3, IFC_FTIM2, CONFIG_SYS_CS3_FTIM2);
+	set_ifc_ftim(IFC_CS3, IFC_FTIM3, CONFIG_SYS_CS3_FTIM3);
+
+	set_ifc_cspr(IFC_CS3, CONFIG_SYS_CSPR3);
+	set_ifc_amask(IFC_CS3, CONFIG_SYS_AMASK3);
+	set_ifc_csor(IFC_CS3, CONFIG_SYS_CSOR3);
+#endif
+
+#ifdef CONFIG_SYS_CSPR4_EXT
+	set_ifc_cspr_ext(IFC_CS4, CONFIG_SYS_CSPR4_EXT);
+#endif
+#ifdef CONFIG_SYS_CSOR4_EXT
+	set_ifc_csor_ext(IFC_CS4, CONFIG_SYS_CSOR4_EXT);
+#endif
+#if defined(CONFIG_SYS_CSPR4) && defined(CONFIG_SYS_CSOR4)
+	set_ifc_ftim(IFC_CS4, IFC_FTIM0, CONFIG_SYS_CS4_FTIM0);
+	set_ifc_ftim(IFC_CS4, IFC_FTIM1, CONFIG_SYS_CS4_FTIM1);
+	set_ifc_ftim(IFC_CS4, IFC_FTIM2, CONFIG_SYS_CS4_FTIM2);
+	set_ifc_ftim(IFC_CS4, IFC_FTIM3, CONFIG_SYS_CS4_FTIM3);
+
+	set_ifc_cspr(IFC_CS4, CONFIG_SYS_CSPR4);
+	set_ifc_amask(IFC_CS4, CONFIG_SYS_AMASK4);
+	set_ifc_csor(IFC_CS4, CONFIG_SYS_CSOR4);
+#endif
+
+#ifdef CONFIG_SYS_CSPR5_EXT
+	set_ifc_cspr_ext(IFC_CS5, CONFIG_SYS_CSPR5_EXT);
+#endif
+#ifdef CONFIG_SYS_CSOR5_EXT
+	set_ifc_csor_ext(IFC_CS5, CONFIG_SYS_CSOR5_EXT);
+#endif
+#if defined(CONFIG_SYS_CSPR5) && defined(CONFIG_SYS_CSOR5)
+	set_ifc_ftim(IFC_CS5, IFC_FTIM0, CONFIG_SYS_CS5_FTIM0);
+	set_ifc_ftim(IFC_CS5, IFC_FTIM1, CONFIG_SYS_CS5_FTIM1);
+	set_ifc_ftim(IFC_CS5, IFC_FTIM2, CONFIG_SYS_CS5_FTIM2);
+	set_ifc_ftim(IFC_CS5, IFC_FTIM3, CONFIG_SYS_CS5_FTIM3);
+
+	set_ifc_cspr(IFC_CS5, CONFIG_SYS_CSPR5);
+	set_ifc_amask(IFC_CS5, CONFIG_SYS_AMASK5);
+	set_ifc_csor(IFC_CS5, CONFIG_SYS_CSOR5);
+#endif
+
+#ifdef CONFIG_SYS_CSPR6_EXT
+	set_ifc_cspr_ext(IFC_CS6, CONFIG_SYS_CSPR6_EXT);
+#endif
+#ifdef CONFIG_SYS_CSOR6_EXT
+	set_ifc_csor_ext(IFC_CS6, CONFIG_SYS_CSOR6_EXT);
+#endif
+#if defined(CONFIG_SYS_CSPR6) && defined(CONFIG_SYS_CSOR6)
+	set_ifc_ftim(IFC_CS6, IFC_FTIM0, CONFIG_SYS_CS6_FTIM0);
+	set_ifc_ftim(IFC_CS6, IFC_FTIM1, CONFIG_SYS_CS6_FTIM1);
+	set_ifc_ftim(IFC_CS6, IFC_FTIM2, CONFIG_SYS_CS6_FTIM2);
+	set_ifc_ftim(IFC_CS6, IFC_FTIM3, CONFIG_SYS_CS6_FTIM3);
+
+	set_ifc_cspr(IFC_CS6, CONFIG_SYS_CSPR6);
+	set_ifc_amask(IFC_CS6, CONFIG_SYS_AMASK6);
+	set_ifc_csor(IFC_CS6, CONFIG_SYS_CSOR6);
+#endif
+
+#ifdef CONFIG_SYS_CSPR7_EXT
+	set_ifc_cspr_ext(IFC_CS7, CONFIG_SYS_CSPR7_EXT);
+#endif
+#ifdef CONFIG_SYS_CSOR7_EXT
+	set_ifc_csor_ext(IFC_CS7, CONFIG_SYS_CSOR7_EXT);
+#endif
+#if defined(CONFIG_SYS_CSPR7) && defined(CONFIG_SYS_CSOR7)
+	set_ifc_ftim(IFC_CS7, IFC_FTIM0, CONFIG_SYS_CS7_FTIM0);
+	set_ifc_ftim(IFC_CS7, IFC_FTIM1, CONFIG_SYS_CS7_FTIM1);
+	set_ifc_ftim(IFC_CS7, IFC_FTIM2, CONFIG_SYS_CS7_FTIM2);
+	set_ifc_ftim(IFC_CS7, IFC_FTIM3, CONFIG_SYS_CS7_FTIM3);
+
+	set_ifc_cspr(IFC_CS7, CONFIG_SYS_CSPR7);
+	set_ifc_amask(IFC_CS7, CONFIG_SYS_AMASK7);
+	set_ifc_csor(IFC_CS7, CONFIG_SYS_CSOR7);
+#endif
+}
diff --git a/drivers/misc/fsl_iim.c b/drivers/misc/fsl_iim.c
index 44ae7b1028..36433a74f8 100644
--- a/drivers/misc/fsl_iim.c
+++ b/drivers/misc/fsl_iim.c
@@ -16,6 +16,9 @@
 #ifndef CONFIG_MPC512X
 #include <asm/arch/imx-regs.h>
 #endif
+#if defined(CONFIG_MX51) || defined(CONFIG_MX53)
+#include <asm/arch/clock.h>
+#endif
 
 /* FSL IIM-specific constants */
 #define STAT_BUSY		0x80
@@ -93,6 +96,10 @@ struct fsl_iim {
 	} bank[8];
 };
 
+#if !defined(CONFIG_MX51) && !defined(CONFIG_MX53)
+#define enable_efuse_prog_supply(enable)
+#endif
+
 static int prepare_access(struct fsl_iim **regs, u32 bank, u32 word, int assert,
 				const char *caller)
 {
@@ -237,12 +244,16 @@ int fuse_prog(u32 bank, u32 word, u32 val)
 	if (ret)
 		return ret;
 
+	enable_efuse_prog_supply(1);
 	for (bit = 0; val; bit++, val >>= 1)
 		if (val & 0x01) {
 			ret = prog_bit(regs, bank, word, bit);
-			if (ret)
+			if (ret) {
+				enable_efuse_prog_supply(0);
 				return ret;
+			}
 		}
+	enable_efuse_prog_supply(0);
 
 	return 0;
 }
diff --git a/drivers/misc/gpio_led.c b/drivers/misc/gpio_led.c
index 3fedddc8b5..3e95727d79 100644
--- a/drivers/misc/gpio_led.c
+++ b/drivers/misc/gpio_led.c
@@ -9,15 +9,42 @@
 #include <status_led.h>
 #include <asm/gpio.h>
 
+#ifndef CONFIG_GPIO_LED_INVERTED_TABLE
+#define CONFIG_GPIO_LED_INVERTED_TABLE {}
+#endif
+
+static led_id_t gpio_led_inv[] = CONFIG_GPIO_LED_INVERTED_TABLE;
+
+static int gpio_led_gpio_value(led_id_t mask, int state)
+{
+	int i, gpio_value = (state == STATUS_LED_ON);
+
+	for (i = 0; i < ARRAY_SIZE(gpio_led_inv); i++) {
+		if (gpio_led_inv[i] == mask)
+			gpio_value = !gpio_value;
+	}
+
+	return gpio_value;
+}
+
 void __led_init(led_id_t mask, int state)
 {
-	gpio_request(mask, "gpio_led");
-	gpio_direction_output(mask, state == STATUS_LED_ON);
+	int gpio_value;
+
+	if (gpio_request(mask, "gpio_led") != 0) {
+		printf("%s: failed requesting GPIO%lu!\n", __func__, mask);
+		return;
+	}
+
+	gpio_value = gpio_led_gpio_value(mask, state);
+	gpio_direction_output(mask, gpio_value);
 }
 
 void __led_set(led_id_t mask, int state)
 {
-	gpio_set_value(mask, state == STATUS_LED_ON);
+	int gpio_value = gpio_led_gpio_value(mask, state);
+
+	gpio_set_value(mask, gpio_value);
 }
 
 void __led_toggle(led_id_t mask)
diff --git a/drivers/misc/mxs_ocotp.c b/drivers/misc/mxs_ocotp.c
new file mode 100644
index 0000000000..545d3ebf52
--- /dev/null
+++ b/drivers/misc/mxs_ocotp.c
@@ -0,0 +1,311 @@
+/*
+ * Freescale i.MX28 OCOTP Driver
+ *
+ * Copyright (C) 2014 Marek Vasut <marex@denx.de>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ *
+ * Note: The i.MX23/i.MX28 OCOTP block is a predecessor to the OCOTP block
+ *       used in i.MX6 . While these blocks are very similar at the first
+ *       glance, by digging deeper, one will notice differences (like the
+ *       tight dependence on MXS power block, some completely new registers
+ *       etc.) which would make common driver an ifdef nightmare :-(
+ */
+
+#include <common.h>
+#include <fuse.h>
+#include <asm/errno.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/sys_proto.h>
+
+#define MXS_OCOTP_TIMEOUT	100000
+
+static struct mxs_ocotp_regs *ocotp_regs =
+	(struct mxs_ocotp_regs *)MXS_OCOTP_BASE;
+static struct mxs_power_regs *power_regs =
+	(struct mxs_power_regs *)MXS_POWER_BASE;
+static struct mxs_clkctrl_regs *clkctrl_regs =
+	(struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
+
+static int mxs_ocotp_wait_busy_clear(void)
+{
+	uint32_t reg;
+	int timeout = MXS_OCOTP_TIMEOUT;
+
+	while (--timeout) {
+		reg = readl(&ocotp_regs->hw_ocotp_ctrl);
+		if (!(reg & OCOTP_CTRL_BUSY))
+			break;
+		udelay(10);
+	}
+
+	if (!timeout)
+		return -EINVAL;
+
+	/* Wait a little as per FSL datasheet's 'write postamble' section. */
+	udelay(10);
+
+	return 0;
+}
+
+static void mxs_ocotp_clear_error(void)
+{
+	writel(OCOTP_CTRL_ERROR, &ocotp_regs->hw_ocotp_ctrl_clr);
+}
+
+static int mxs_ocotp_read_bank_open(bool open)
+{
+	int ret = 0;
+
+	if (open) {
+		writel(OCOTP_CTRL_RD_BANK_OPEN,
+		       &ocotp_regs->hw_ocotp_ctrl_set);
+
+		/*
+		 * Wait before polling the BUSY bit, since the BUSY bit might
+		 * be asserted only after a few HCLK cycles and if we were to
+		 * poll immediatelly, we could miss the busy bit.
+		 */
+		udelay(10);
+		ret = mxs_ocotp_wait_busy_clear();
+	} else {
+		writel(OCOTP_CTRL_RD_BANK_OPEN,
+		       &ocotp_regs->hw_ocotp_ctrl_clr);
+	}
+
+	return ret;
+}
+
+static void mxs_ocotp_scale_vddio(bool enter, uint32_t *val)
+{
+	uint32_t scale_val;
+
+	if (enter) {
+		/*
+		 * Enter the fuse programming VDDIO voltage setup. We start
+		 * scaling the voltage from it's current value down to 2.8V
+		 * which is the one and only correct voltage for programming
+		 * the OCOTP fuses (according to datasheet).
+		 */
+		scale_val = readl(&power_regs->hw_power_vddioctrl);
+		scale_val &= POWER_VDDIOCTRL_TRG_MASK;
+
+		/* Return the original voltage. */
+		*val = scale_val;
+
+		/*
+		 * Start scaling VDDIO down to 0x2, which is 2.8V . Actually,
+		 * the value 0x0 should be 2.8V, but that's not the case on
+		 * most designs due to load etc., so we play safe. Undervolt
+		 * can actually cause incorrect programming of the fuses and
+		 * or reboots of the board.
+		 */
+		while (scale_val > 2) {
+			clrsetbits_le32(&power_regs->hw_power_vddioctrl,
+					POWER_VDDIOCTRL_TRG_MASK, --scale_val);
+			udelay(500);
+		}
+	} else {
+		/* Start scaling VDDIO up to original value . */
+		for (scale_val = 2; scale_val <= *val; scale_val++) {
+			clrsetbits_le32(&power_regs->hw_power_vddioctrl,
+					POWER_VDDIOCTRL_TRG_MASK, scale_val);
+			udelay(500);
+		}
+	}
+
+	mdelay(10);
+}
+
+static int mxs_ocotp_wait_hclk_ready(void)
+{
+	uint32_t reg, timeout = MXS_OCOTP_TIMEOUT;
+
+	while (--timeout) {
+		reg = readl(&clkctrl_regs->hw_clkctrl_hbus);
+		if (!(reg & CLKCTRL_HBUS_ASM_BUSY))
+			break;
+	}
+
+	if (!timeout)
+		return -EINVAL;
+
+	return 0;
+}
+
+static int mxs_ocotp_scale_hclk(bool enter, uint32_t *val)
+{
+	uint32_t scale_val;
+	int ret;
+
+	ret = mxs_ocotp_wait_hclk_ready();
+	if (ret)
+		return ret;
+
+	/* Set CPU bypass */
+	writel(CLKCTRL_CLKSEQ_BYPASS_CPU,
+	       &clkctrl_regs->hw_clkctrl_clkseq_set);
+
+	if (enter) {
+		/* Return the original HCLK clock speed. */
+		*val = readl(&clkctrl_regs->hw_clkctrl_hbus);
+		*val &= CLKCTRL_HBUS_DIV_MASK;
+
+		/* Scale the HCLK to 454/19 = 23.9 MHz . */
+		scale_val = (~19) << CLKCTRL_HBUS_DIV_OFFSET;
+		scale_val &= CLKCTRL_HBUS_DIV_MASK;
+	} else {
+		/* Scale the HCLK back to original frequency. */
+		scale_val = (~(*val)) << CLKCTRL_HBUS_DIV_OFFSET;
+		scale_val &= CLKCTRL_HBUS_DIV_MASK;
+	}
+
+	writel(CLKCTRL_HBUS_DIV_MASK,
+	       &clkctrl_regs->hw_clkctrl_hbus_set);
+	writel(scale_val,
+	       &clkctrl_regs->hw_clkctrl_hbus_clr);
+
+	mdelay(10);
+
+	ret = mxs_ocotp_wait_hclk_ready();
+	if (ret)
+		return ret;
+
+	/* Disable CPU bypass */
+	writel(CLKCTRL_CLKSEQ_BYPASS_CPU,
+	       &clkctrl_regs->hw_clkctrl_clkseq_clr);
+
+	mdelay(10);
+
+	return 0;
+}
+
+static int mxs_ocotp_write_fuse(uint32_t addr, uint32_t mask)
+{
+	uint32_t hclk_val, vddio_val;
+	int ret;
+
+	/* Make sure the banks are closed for reading. */
+	ret = mxs_ocotp_read_bank_open(0);
+	if (ret) {
+		puts("Failed closing banks for reading!\n");
+		return ret;
+	}
+
+	ret = mxs_ocotp_scale_hclk(1, &hclk_val);
+	if (ret) {
+		puts("Failed scaling down the HCLK!\n");
+		return ret;
+	}
+	mxs_ocotp_scale_vddio(1, &vddio_val);
+
+	ret = mxs_ocotp_wait_busy_clear();
+	if (ret) {
+		puts("Failed waiting for ready state!\n");
+		goto fail;
+	}
+
+	/* Program the fuse address */
+	writel(addr | OCOTP_CTRL_WR_UNLOCK_KEY, &ocotp_regs->hw_ocotp_ctrl);
+
+	/* Program the data. */
+	writel(mask, &ocotp_regs->hw_ocotp_data);
+
+	udelay(10);
+
+	ret = mxs_ocotp_wait_busy_clear();
+	if (ret) {
+		puts("Failed waiting for ready state!\n");
+		goto fail;
+	}
+
+fail:
+	mxs_ocotp_scale_vddio(0, &vddio_val);
+	ret = mxs_ocotp_scale_hclk(0, &hclk_val);
+	if (ret) {
+		puts("Failed scaling up the HCLK!\n");
+		return ret;
+	}
+
+	return ret;
+}
+
+static int mxs_ocotp_read_fuse(uint32_t reg, uint32_t *val)
+{
+	int ret;
+
+	/* Register offset from CUST0 */
+	reg = ((uint32_t)&ocotp_regs->hw_ocotp_cust0) + (reg << 4);
+
+	ret = mxs_ocotp_wait_busy_clear();
+	if (ret) {
+		puts("Failed waiting for ready state!\n");
+		return ret;
+	}
+
+	mxs_ocotp_clear_error();
+
+	ret = mxs_ocotp_read_bank_open(1);
+	if (ret) {
+		puts("Failed opening banks for reading!\n");
+		return ret;
+	}
+
+	*val = readl(reg);
+
+	ret = mxs_ocotp_read_bank_open(0);
+	if (ret) {
+		puts("Failed closing banks for reading!\n");
+		return ret;
+	}
+
+	return ret;
+}
+
+static int mxs_ocotp_valid(u32 bank, u32 word)
+{
+	if (bank > 4)
+		return -EINVAL;
+	if (word > 7)
+		return -EINVAL;
+	return 0;
+}
+
+/*
+ * The 'fuse' command API
+ */
+int fuse_read(u32 bank, u32 word, u32 *val)
+{
+	int ret;
+
+	ret = mxs_ocotp_valid(bank, word);
+	if (ret)
+		return ret;
+
+	return mxs_ocotp_read_fuse((bank << 3) | word, val);
+}
+
+int fuse_prog(u32 bank, u32 word, u32 val)
+{
+	int ret;
+
+	ret = mxs_ocotp_valid(bank, word);
+	if (ret)
+		return ret;
+
+	return mxs_ocotp_write_fuse((bank << 3) | word, val);
+}
+
+int fuse_sense(u32 bank, u32 word, u32 *val)
+{
+	/* We do not support sensing :-( */
+	return -EINVAL;
+}
+
+int fuse_override(u32 bank, u32 word, u32 val)
+{
+	/* We do not support overriding :-( */
+	return -EINVAL;
+}
diff --git a/drivers/mmc/Makefile b/drivers/mmc/Makefile
index 06280d1fa6..931922bc4a 100644
--- a/drivers/mmc/Makefile
+++ b/drivers/mmc/Makefile
@@ -5,53 +5,33 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	:= $(obj)libmmc.o
-
-
-COBJS-$(CONFIG_BFIN_SDH) += bfin_sdh.o
-COBJS-$(CONFIG_DAVINCI_MMC) += davinci_mmc.o
-COBJS-$(CONFIG_FSL_ESDHC) += fsl_esdhc.o
-COBJS-$(CONFIG_FTSDC010) += ftsdc010_mci.o
-COBJS-$(CONFIG_GENERIC_MMC) += mmc.o
-COBJS-$(CONFIG_GENERIC_ATMEL_MCI) += gen_atmel_mci.o
-COBJS-$(CONFIG_MMC_SPI) += mmc_spi.o
-COBJS-$(CONFIG_ARM_PL180_MMCI) += arm_pl180_mmci.o
-COBJS-$(CONFIG_MV_SDHCI) += mv_sdhci.o
-COBJS-$(CONFIG_MXC_MMC) += mxcmmc.o
-COBJS-$(CONFIG_MXS_MMC) += mxsmmc.o
-COBJS-$(CONFIG_OMAP_HSMMC) += omap_hsmmc.o
-COBJS-$(CONFIG_PXA_MMC_GENERIC) += pxa_mmc_gen.o
-COBJS-$(CONFIG_SDHCI) += sdhci.o
-COBJS-$(CONFIG_BCM2835_SDHCI) += bcm2835_sdhci.o
-COBJS-$(CONFIG_S5P_SDHCI) += s5p_sdhci.o
-COBJS-$(CONFIG_SH_MMCIF) += sh_mmcif.o
-COBJS-$(CONFIG_SPEAR_SDHCI) += spear_sdhci.o
-COBJS-$(CONFIG_TEGRA_MMC) += tegra_mmc.o
-COBJS-$(CONFIG_DWMMC) += dw_mmc.o
-COBJS-$(CONFIG_EXYNOS_DWMMC) += exynos_dw_mmc.o
-COBJS-$(CONFIG_ZYNQ_SDHCI) += zynq_sdhci.o
+obj-$(CONFIG_BFIN_SDH) += bfin_sdh.o
+obj-$(CONFIG_DAVINCI_MMC) += davinci_mmc.o
+obj-$(CONFIG_FSL_ESDHC) += fsl_esdhc.o
+obj-$(CONFIG_FTSDC010) += ftsdc010_mci.o
+obj-$(CONFIG_FTSDC021) += ftsdc021_sdhci.o
+obj-$(CONFIG_GENERIC_MMC) += mmc.o
+obj-$(CONFIG_GENERIC_ATMEL_MCI) += gen_atmel_mci.o
+obj-$(CONFIG_MMC_SPI) += mmc_spi.o
+obj-$(CONFIG_ARM_PL180_MMCI) += arm_pl180_mmci.o
+obj-$(CONFIG_MV_SDHCI) += mv_sdhci.o
+obj-$(CONFIG_MXC_MMC) += mxcmmc.o
+obj-$(CONFIG_MXS_MMC) += mxsmmc.o
+obj-$(CONFIG_OMAP_HSMMC) += omap_hsmmc.o
+obj-$(CONFIG_PXA_MMC_GENERIC) += pxa_mmc_gen.o
+obj-$(CONFIG_SDHCI) += sdhci.o
+obj-$(CONFIG_BCM2835_SDHCI) += bcm2835_sdhci.o
+obj-$(CONFIG_KONA_SDHCI) += kona_sdhci.o
+obj-$(CONFIG_S5P_SDHCI) += s5p_sdhci.o
+obj-$(CONFIG_SH_MMCIF) += sh_mmcif.o
+obj-$(CONFIG_SPEAR_SDHCI) += spear_sdhci.o
+obj-$(CONFIG_TEGRA_MMC) += tegra_mmc.o
+obj-$(CONFIG_DWMMC) += dw_mmc.o
+obj-$(CONFIG_EXYNOS_DWMMC) += exynos_dw_mmc.o
+obj-$(CONFIG_ZYNQ_SDHCI) += zynq_sdhci.o
+obj-$(CONFIG_SOCFPGA_DWMMC) += socfpga_dw_mmc.o
 ifdef CONFIG_SPL_BUILD
-COBJS-$(CONFIG_SPL_MMC_BOOT) += fsl_esdhc_spl.o
+obj-$(CONFIG_SPL_MMC_BOOT) += fsl_esdhc_spl.o
 else
-COBJS-$(CONFIG_GENERIC_MMC) += mmc_write.o
+obj-$(CONFIG_GENERIC_MMC) += mmc_write.o
 endif
-
-COBJS	:= $(COBJS-y)
-SRCS	:= $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-
-all:	$(LIB)
-
-$(LIB): $(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
diff --git a/drivers/mmc/arm_pl180_mmci.c b/drivers/mmc/arm_pl180_mmci.c
index 5a55fe73b7..5ef7ff7ff2 100644
--- a/drivers/mmc/arm_pl180_mmci.c
+++ b/drivers/mmc/arm_pl180_mmci.c
@@ -287,9 +287,9 @@ static void host_set_ios(struct mmc *dev)
 		u32 clkdiv = 0;
 		u32 tmp_clock;
 
-		if (dev->clock >= dev->f_max) {
+		if (dev->clock >= dev->cfg->f_max) {
 			clkdiv = 0;
-			dev->clock = dev->f_max;
+			dev->clock = dev->cfg->f_max;
 		} else {
 			clkdiv = (host->clock_in / dev->clock) - 2;
 		}
@@ -335,6 +335,12 @@ static void host_set_ios(struct mmc *dev)
 	udelay(CLK_CHANGE_DELAY);
 }
 
+static const struct mmc_ops arm_pl180_mmci_ops = {
+	.send_cmd = host_request,
+	.set_ios = host_set_ios,
+	.init = mmc_host_reset,
+};
+
 /*
  * mmc_host_init - initialize the mmc controller.
  * Set initial clock and power for mmc slot.
@@ -342,16 +348,9 @@ static void host_set_ios(struct mmc *dev)
  */
 int arm_pl180_mmci_init(struct pl180_mmc_host *host)
 {
-	struct mmc *dev;
+	struct mmc *mmc;
 	u32 sdi_u32;
 
-	dev = malloc(sizeof(struct mmc));
-	if (!dev)
-		return -ENOMEM;
-
-	memset(dev, 0, sizeof(struct mmc));
-	dev->priv = host;
-
 	writel(host->pwr_init, &host->base->power);
 	writel(host->clkdiv_init, &host->base->clock);
 	udelay(CLK_CHANGE_DELAY);
@@ -359,19 +358,24 @@ int arm_pl180_mmci_init(struct pl180_mmc_host *host)
 	/* Disable mmc interrupts */
 	sdi_u32 = readl(&host->base->mask0) & ~SDI_MASK0_MASK;
 	writel(sdi_u32, &host->base->mask0);
-	strncpy(dev->name, host->name, sizeof(dev->name));
-	dev->send_cmd = host_request;
-	dev->set_ios = host_set_ios;
-	dev->init = mmc_host_reset;
-	dev->getcd = NULL;
-	dev->getwp = NULL;
-	dev->host_caps = host->caps;
-	dev->voltages = host->voltages;
-	dev->f_min = host->clock_min;
-	dev->f_max = host->clock_max;
-	dev->b_max = host->b_max;
-	mmc_register(dev);
-	debug("registered mmc interface number is:%d\n", dev->block_dev.dev);
+
+	host->cfg.name = host->name;
+	host->cfg.ops = &arm_pl180_mmci_ops;
+	/* TODO remove the duplicates */
+	host->cfg.host_caps = host->caps;
+	host->cfg.voltages = host->voltages;
+	host->cfg.f_min = host->clock_min;
+	host->cfg.f_max = host->clock_max;
+	if (host->b_max != 0)
+		host->cfg.b_max = host->b_max;
+	else
+		host->cfg.b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
+
+	mmc = mmc_create(&host->cfg, host);
+	if (mmc == NULL)
+		return -1;
+
+	debug("registered mmc interface number is:%d\n", mmc->block_dev.dev);
 
 	return 0;
 }
diff --git a/drivers/mmc/arm_pl180_mmci.h b/drivers/mmc/arm_pl180_mmci.h
index 72344498d6..f23bd391ee 100644
--- a/drivers/mmc/arm_pl180_mmci.h
+++ b/drivers/mmc/arm_pl180_mmci.h
@@ -13,6 +13,9 @@
 #ifndef __ARM_PL180_MMCI_H__
 #define __ARM_PL180_MMCI_H__
 
+/* need definition of struct mmc_config */
+#include <mmc.h>
+
 #define COMMAND_REG_DELAY	300
 #define DATA_REG_DELAY		1000
 #define CLK_CHANGE_DELAY	2000
@@ -184,6 +187,7 @@ struct pl180_mmc_host {
 	unsigned int clkdiv_init;
 	unsigned int pwr_init;
 	int version2;
+	struct mmc_config cfg;
 };
 
 int arm_pl180_mmci_init(struct pl180_mmc_host *);
diff --git a/drivers/mmc/bfin_sdh.c b/drivers/mmc/bfin_sdh.c
index 26311741f5..bcd6a3e52f 100644
--- a/drivers/mmc/bfin_sdh.c
+++ b/drivers/mmc/bfin_sdh.c
@@ -15,6 +15,7 @@
 #include <asm/errno.h>
 #include <asm/byteorder.h>
 #include <asm/blackfin.h>
+#include <asm/clock.h>
 #include <asm/portmux.h>
 #include <asm/mach-common/bits/sdh.h>
 #include <asm/mach-common/bits/dma.h>
@@ -273,30 +274,30 @@ static int bfin_sdh_init(struct mmc *mmc)
 	return 0;
 }
 
+static const struct mmc_ops bfin_mmc_ops = {
+	.send_cmd	= bfin_sdh_request,
+	.set_ios	= bfin_sdh_set_ios,
+	.init		= bfin_sdh_init,
+};
+
+static struct mmc_config bfin_mmc_cfg = {
+	.name		= "Blackfin SDH",
+	.ops		= &bfin_mmc_ops,
+	.host_caps	= MMC_MODE_4BIT,
+	.voltages	= MMC_VDD_32_33 | MMC_VDD_33_34,
+	.b_max		= CONFIG_SYS_MMC_MAX_BLK_COUNT,
+};
 
 int bfin_mmc_init(bd_t *bis)
 {
-	struct mmc *mmc = NULL;
-
-	mmc = malloc(sizeof(struct mmc));
-
-	if (!mmc)
-		return -ENOMEM;
-	sprintf(mmc->name, "Blackfin SDH");
-	mmc->send_cmd = bfin_sdh_request;
-	mmc->set_ios = bfin_sdh_set_ios;
-	mmc->init = bfin_sdh_init;
-	mmc->getcd = NULL;
-	mmc->getwp = NULL;
-	mmc->host_caps = MMC_MODE_4BIT;
-
-	mmc->voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
-	mmc->f_max = get_sclk();
-	mmc->f_min = mmc->f_max >> 9;
+	struct mmc *mmc;
 
-	mmc->b_max = 0;
+	bfin_mmc_cfg.f_max = get_sclk();
+	bfin_mmc_cfg.f_min = bfin_mmc_cfg.f_max >> 9;
 
-	mmc_register(mmc);
+	mmc = mmc_create(&bfin_mmc_cfg, NULL);
+	if (mmc == NULL)
+		return -1;
 
 	return 0;
 }
diff --git a/drivers/mmc/davinci_mmc.c b/drivers/mmc/davinci_mmc.c
index b380961188..aae00e9dab 100644
--- a/drivers/mmc/davinci_mmc.c
+++ b/drivers/mmc/davinci_mmc.c
@@ -30,10 +30,10 @@ static void dmmc_set_clock(struct mmc *mmc, uint clock)
 	struct davinci_mmc_regs *regs = host->reg_base;
 	uint clkrt, sysclk2, act_clock;
 
-	if (clock < mmc->f_min)
-		clock = mmc->f_min;
-	if (clock > mmc->f_max)
-		clock = mmc->f_max;
+	if (clock < mmc->cfg->f_min)
+		clock = mmc->cfg->f_min;
+	if (clock > mmc->cfg->f_max)
+		clock = mmc->cfg->f_max;
 
 	set_val(&regs->mmcclk, 0);
 	sysclk2 = host->input_clk;
@@ -363,32 +363,27 @@ static void dmmc_set_ios(struct mmc *mmc)
 		dmmc_set_clock(mmc, mmc->clock);
 }
 
+static const struct mmc_ops dmmc_ops = {
+	.send_cmd	= dmmc_send_cmd,
+	.set_ios	= dmmc_set_ios,
+	.init		= dmmc_init,
+};
+
 /* Called from board_mmc_init during startup. Can be called multiple times
  * depending on the number of slots available on board and controller
  */
 int davinci_mmc_init(bd_t *bis, struct davinci_mmc *host)
 {
-	struct mmc *mmc;
-
-	mmc = malloc(sizeof(struct mmc));
-	memset(mmc, 0, sizeof(struct mmc));
-
-	sprintf(mmc->name, "davinci");
-	mmc->priv = host;
-	mmc->send_cmd = dmmc_send_cmd;
-	mmc->set_ios = dmmc_set_ios;
-	mmc->init = dmmc_init;
-	mmc->getcd = NULL;
-	mmc->getwp = NULL;
-
-	mmc->f_min = 200000;
-	mmc->f_max = 25000000;
-	mmc->voltages = host->voltages;
-	mmc->host_caps = host->host_caps;
+	host->cfg.name = "davinci";
+	host->cfg.ops = &dmmc_ops;
+	host->cfg.f_min = 200000;
+	host->cfg.f_max = 25000000;
+	host->cfg.voltages = host->voltages;
+	host->cfg.host_caps = host->host_caps;
 
-	mmc->b_max = DAVINCI_MAX_BLOCKS;
+	host->cfg.b_max = DAVINCI_MAX_BLOCKS;
 
-	mmc_register(mmc);
+	mmc_create(&host->cfg, host);
 
 	return 0;
 }
diff --git a/drivers/mmc/dw_mmc.c b/drivers/mmc/dw_mmc.c
index 9a803a02d4..eb4e2be514 100644
--- a/drivers/mmc/dw_mmc.c
+++ b/drivers/mmc/dw_mmc.c
@@ -6,6 +6,7 @@
  * SPDX-License-Identifier:	GPL-2.0+
  */
 
+#include <bouncebuf.h>
 #include <common.h>
 #include <malloc.h>
 #include <mmc.h>
@@ -41,11 +42,13 @@ static void dwmci_set_idma_desc(struct dwmci_idmac *idmac,
 }
 
 static void dwmci_prepare_data(struct dwmci_host *host,
-		struct mmc_data *data, struct dwmci_idmac *cur_idmac)
+			       struct mmc_data *data,
+			       struct dwmci_idmac *cur_idmac,
+			       void *bounce_buffer)
 {
 	unsigned long ctrl;
 	unsigned int i = 0, flags, cnt, blk_cnt;
-	ulong data_start, data_end, start_addr;
+	ulong data_start, data_end;
 
 
 	blk_cnt = data->blocks;
@@ -55,11 +58,6 @@ static void dwmci_prepare_data(struct dwmci_host *host,
 	data_start = (ulong)cur_idmac;
 	dwmci_writel(host, DWMCI_DBADDR, (unsigned int)cur_idmac);
 
-	if (data->flags == MMC_DATA_READ)
-		start_addr = (unsigned int)data->dest;
-	else
-		start_addr = (unsigned int)data->src;
-
 	do {
 		flags = DWMCI_IDMAC_OWN | DWMCI_IDMAC_CH ;
 		flags |= (i == 0) ? DWMCI_IDMAC_FS : 0;
@@ -70,7 +68,7 @@ static void dwmci_prepare_data(struct dwmci_host *host,
 			cnt = data->blocksize * 8;
 
 		dwmci_set_idma_desc(cur_idmac, flags, cnt,
-				start_addr + (i * PAGE_SIZE));
+				    (u32)bounce_buffer + (i * PAGE_SIZE));
 
 		if (blk_cnt <= 8)
 			break;
@@ -109,7 +107,7 @@ static int dwmci_set_transfer_mode(struct dwmci_host *host,
 static int dwmci_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
 		struct mmc_data *data)
 {
-	struct dwmci_host *host = (struct dwmci_host *)mmc->priv;
+	struct dwmci_host *host = mmc->priv;
 	ALLOC_CACHE_ALIGN_BUFFER(struct dwmci_idmac, cur_idmac,
 				 data ? DIV_ROUND_UP(data->blocks, 8) : 0);
 	int flags = 0, i;
@@ -117,6 +115,7 @@ static int dwmci_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
 	u32 retry = 10000;
 	u32 mask, ctrl;
 	ulong start = get_timer(0);
+	struct bounce_buffer bbstate;
 
 	while (dwmci_readl(host, DWMCI_STATUS) & DWMCI_BUSY) {
 		if (get_timer(start) > timeout) {
@@ -127,8 +126,19 @@ static int dwmci_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
 
 	dwmci_writel(host, DWMCI_RINTSTS, DWMCI_INTMSK_ALL);
 
-	if (data)
-		dwmci_prepare_data(host, data, cur_idmac);
+	if (data) {
+		if (data->flags == MMC_DATA_READ) {
+			bounce_buffer_start(&bbstate, (void*)data->dest,
+					    data->blocksize *
+					    data->blocks, GEN_BB_WRITE);
+		} else {
+			bounce_buffer_start(&bbstate, (void*)data->src,
+					    data->blocksize *
+					    data->blocks, GEN_BB_READ);
+		}
+		dwmci_prepare_data(host, data, cur_idmac,
+				   bbstate.bounce_buffer);
+	}
 
 	dwmci_writel(host, DWMCI_CMDARG, cmd->cmdarg);
 
@@ -204,6 +214,8 @@ static int dwmci_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
 		ctrl = dwmci_readl(host, DWMCI_CTRL);
 		ctrl &= ~(DWMCI_DMA_EN);
 		dwmci_writel(host, DWMCI_CTRL, ctrl);
+
+		bounce_buffer_stop(&bbstate);
 	}
 
 	udelay(100);
@@ -220,12 +232,12 @@ static int dwmci_setup_bus(struct dwmci_host *host, u32 freq)
 	if ((freq == host->clock) || (freq == 0))
 		return 0;
 	/*
-	 * If host->mmc_clk didn't define,
+	 * If host->get_mmc_clk didn't define,
 	 * then assume that host->bus_hz is source clock value.
 	 * host->bus_hz should be set from user.
 	 */
-	if (host->mmc_clk)
-		sclk = host->mmc_clk(host->dev_index);
+	if (host->get_mmc_clk)
+		sclk = host->get_mmc_clk(host);
 	else if (host->bus_hz)
 		sclk = host->bus_hz;
 	else {
@@ -272,7 +284,7 @@ static int dwmci_setup_bus(struct dwmci_host *host, u32 freq)
 
 static void dwmci_set_ios(struct mmc *mmc)
 {
-	struct dwmci_host *host = (struct dwmci_host *)mmc->priv;
+	struct dwmci_host *host = mmc->priv;
 	u32 ctype;
 
 	debug("Buswidth = %d, clock: %d\n",mmc->bus_width, mmc->clock);
@@ -298,8 +310,10 @@ static void dwmci_set_ios(struct mmc *mmc)
 
 static int dwmci_init(struct mmc *mmc)
 {
-	struct dwmci_host *host = (struct dwmci_host *)mmc->priv;
-	u32 fifo_size;
+	struct dwmci_host *host = mmc->priv;
+
+	if (host->board_init)
+		host->board_init(host);
 
 	dwmci_writel(host, DWMCI_PWREN, 1);
 
@@ -309,7 +323,7 @@ static int dwmci_init(struct mmc *mmc)
 	}
 
 	/* Enumerate at 400KHz */
-	dwmci_setup_bus(host, mmc->f_min);
+	dwmci_setup_bus(host, mmc->cfg->f_min);
 
 	dwmci_writel(host, DWMCI_RINTSTS, 0xFFFFFFFF);
 	dwmci_writel(host, DWMCI_INTMASK, 0);
@@ -319,13 +333,9 @@ static int dwmci_init(struct mmc *mmc)
 	dwmci_writel(host, DWMCI_IDINTEN, 0);
 	dwmci_writel(host, DWMCI_BMOD, 1);
 
-	if (!host->fifoth_val) {
-		fifo_size = dwmci_readl(host, DWMCI_FIFOTH);
-		fifo_size = ((fifo_size & RX_WMARK_MASK) >> RX_WMARK_SHIFT) + 1;
-		host->fifoth_val = MSIZE(0x2) | RX_WMARK(fifo_size / 2 - 1) |
-			TX_WMARK(fifo_size / 2);
+	if (host->fifoth_val) {
+		dwmci_writel(host, DWMCI_FIFOTH, host->fifoth_val);
 	}
-	dwmci_writel(host, DWMCI_FIFOTH, host->fifoth_val);
 
 	dwmci_writel(host, DWMCI_CLKENA, 0);
 	dwmci_writel(host, DWMCI_CLKSRC, 0);
@@ -333,41 +343,37 @@ static int dwmci_init(struct mmc *mmc)
 	return 0;
 }
 
+static const struct mmc_ops dwmci_ops = {
+	.send_cmd	= dwmci_send_cmd,
+	.set_ios	= dwmci_set_ios,
+	.init		= dwmci_init,
+};
+
 int add_dwmci(struct dwmci_host *host, u32 max_clk, u32 min_clk)
 {
-	struct mmc *mmc;
-	int err = 0;
-
-	mmc = malloc(sizeof(struct mmc));
-	if (!mmc) {
-		printf("mmc malloc fail!\n");
-		return -1;
-	}
-
-	mmc->priv = host;
-	host->mmc = mmc;
+	host->cfg.name = host->name;
+	host->cfg.ops = &dwmci_ops;
+	host->cfg.f_min = min_clk;
+	host->cfg.f_max = max_clk;
 
-	sprintf(mmc->name, "%s", host->name);
-	mmc->send_cmd = dwmci_send_cmd;
-	mmc->set_ios = dwmci_set_ios;
-	mmc->init = dwmci_init;
-	mmc->f_min = min_clk;
-	mmc->f_max = max_clk;
+	host->cfg.voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
 
-	mmc->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
-
-	mmc->host_caps = host->caps;
+	host->cfg.host_caps = host->caps;
 
 	if (host->buswidth == 8) {
-		mmc->host_caps |= MMC_MODE_8BIT;
-		mmc->host_caps &= ~MMC_MODE_4BIT;
+		host->cfg.host_caps |= MMC_MODE_8BIT;
+		host->cfg.host_caps &= ~MMC_MODE_4BIT;
 	} else {
-		mmc->host_caps |= MMC_MODE_4BIT;
-		mmc->host_caps &= ~MMC_MODE_8BIT;
+		host->cfg.host_caps |= MMC_MODE_4BIT;
+		host->cfg.host_caps &= ~MMC_MODE_8BIT;
 	}
-	mmc->host_caps |= MMC_MODE_HS | MMC_MODE_HS_52MHz | MMC_MODE_HC;
+	host->cfg.host_caps |= MMC_MODE_HS | MMC_MODE_HS_52MHz | MMC_MODE_HC;
+
+	host->cfg.b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
 
-	err = mmc_register(mmc);
+	host->mmc = mmc_create(&host->cfg, host);
+	if (host->mmc == NULL)
+		return -1;
 
-	return err;
+	return 0;
 }
diff --git a/drivers/mmc/exynos_dw_mmc.c b/drivers/mmc/exynos_dw_mmc.c
index 4ef9fec0e4..de8cdcc42b 100644
--- a/drivers/mmc/exynos_dw_mmc.c
+++ b/drivers/mmc/exynos_dw_mmc.c
@@ -29,9 +29,35 @@ static void exynos_dwmci_clksel(struct dwmci_host *host)
 	dwmci_writel(host, DWMCI_CLKSEL, host->clksel_val);
 }
 
-unsigned int exynos_dwmci_get_clk(int dev_index)
+unsigned int exynos_dwmci_get_clk(struct dwmci_host *host)
 {
-	return get_mmc_clk(dev_index);
+	unsigned long sclk;
+	int8_t clk_div;
+
+	/*
+	 * Since SDCLKIN is divided inside controller by the DIVRATIO
+	 * value set in the CLKSEL register, we need to use the same output
+	 * clock value to calculate the CLKDIV value.
+	 * as per user manual:cclk_in = SDCLKIN / (DIVRATIO + 1)
+	 */
+	clk_div = ((dwmci_readl(host, DWMCI_CLKSEL) >> DWMCI_DIVRATIO_BIT)
+			& DWMCI_DIVRATIO_MASK) + 1;
+	sclk = get_mmc_clk(host->dev_index);
+
+	return sclk / clk_div;
+}
+
+static void exynos_dwmci_board_init(struct dwmci_host *host)
+{
+	if (host->quirks & DWMCI_QUIRK_DISABLE_SMU) {
+		dwmci_writel(host, EMMCP_MPSBEGIN0, 0);
+		dwmci_writel(host, EMMCP_SEND0, 0);
+		dwmci_writel(host, EMMCP_CTRL0,
+			     MPSCTRL_SECURE_READ_BIT |
+			     MPSCTRL_SECURE_WRITE_BIT |
+			     MPSCTRL_NON_SECURE_READ_BIT |
+			     MPSCTRL_NON_SECURE_WRITE_BIT | MPSCTRL_VALID);
+	}
 }
 
 /*
@@ -62,6 +88,10 @@ int exynos_dwmci_add_port(int index, u32 regbase, int bus_width, u32 clksel)
 	host->name = "EXYNOS DWMMC";
 	host->ioaddr = (void *)regbase;
 	host->buswidth = bus_width;
+#ifdef CONFIG_EXYNOS5420
+	host->quirks = DWMCI_QUIRK_DISABLE_SMU;
+#endif
+	host->board_init = exynos_dwmci_board_init;
 
 	if (clksel) {
 		host->clksel_val = clksel;
@@ -74,7 +104,7 @@ int exynos_dwmci_add_port(int index, u32 regbase, int bus_width, u32 clksel)
 
 	host->clksel = exynos_dwmci_clksel;
 	host->dev_index = index;
-	host->mmc_clk = exynos_dwmci_get_clk;
+	host->get_mmc_clk = exynos_dwmci_get_clk;
 	/* Add the mmc channel to be registered with mmc core */
 	if (add_dwmci(host, DWMMC_MAX_FREQ, DWMMC_MIN_FREQ)) {
 		debug("dwmmc%d registration failed\n", index);
diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c
index a7170b49db..4c3b93d413 100644
--- a/drivers/mmc/fsl_esdhc.c
+++ b/drivers/mmc/fsl_esdhc.c
@@ -24,31 +24,43 @@
 DECLARE_GLOBAL_DATA_PTR;
 
 struct fsl_esdhc {
-	uint	dsaddr;
-	uint	blkattr;
-	uint	cmdarg;
-	uint	xfertyp;
-	uint	cmdrsp0;
-	uint	cmdrsp1;
-	uint	cmdrsp2;
-	uint	cmdrsp3;
-	uint	datport;
-	uint	prsstat;
-	uint	proctl;
-	uint	sysctl;
-	uint	irqstat;
-	uint	irqstaten;
-	uint	irqsigen;
-	uint	autoc12err;
-	uint	hostcapblt;
-	uint	wml;
-	uint    mixctrl;
-	char    reserved1[4];
-	uint	fevt;
-	char	reserved2[168];
-	uint	hostver;
-	char	reserved3[780];
-	uint	scr;
+	uint    dsaddr;		/* SDMA system address register */
+	uint    blkattr;	/* Block attributes register */
+	uint    cmdarg;		/* Command argument register */
+	uint    xfertyp;	/* Transfer type register */
+	uint    cmdrsp0;	/* Command response 0 register */
+	uint    cmdrsp1;	/* Command response 1 register */
+	uint    cmdrsp2;	/* Command response 2 register */
+	uint    cmdrsp3;	/* Command response 3 register */
+	uint    datport;	/* Buffer data port register */
+	uint    prsstat;	/* Present state register */
+	uint    proctl;		/* Protocol control register */
+	uint    sysctl;		/* System Control Register */
+	uint    irqstat;	/* Interrupt status register */
+	uint    irqstaten;	/* Interrupt status enable register */
+	uint    irqsigen;	/* Interrupt signal enable register */
+	uint    autoc12err;	/* Auto CMD error status register */
+	uint    hostcapblt;	/* Host controller capabilities register */
+	uint    wml;		/* Watermark level register */
+	uint    mixctrl;	/* For USDHC */
+	char    reserved1[4];	/* reserved */
+	uint    fevt;		/* Force event register */
+	uint    admaes;		/* ADMA error status register */
+	uint    adsaddr;	/* ADMA system address register */
+	char    reserved2[160];	/* reserved */
+	uint    hostver;	/* Host controller version register */
+	char    reserved3[4];	/* reserved */
+	uint    dmaerraddr;	/* DMA error address register */
+	char    reserved4[4];	/* reserved */
+	uint    dmaerrattr;	/* DMA error attribute register */
+	char    reserved5[4];	/* reserved */
+	uint    hostcapblt2;	/* Host controller capabilities register 2 */
+	char    reserved6[8];	/* reserved */
+	uint    tcr;		/* Tuning control register */
+	char    reserved7[28];	/* reserved */
+	uint    sddirctl;	/* SD direction control register */
+	char    reserved8[712];	/* reserved */
+	uint    scr;		/* eSDHC control register */
 };
 
 /* Return the XFERTYP flags for a given command and data packet */
@@ -160,7 +172,7 @@ esdhc_pio_read_write(struct mmc *mmc, struct mmc_data *data)
 static int esdhc_setup_data(struct mmc *mmc, struct mmc_data *data)
 {
 	int timeout;
-	struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
+	struct fsl_esdhc_cfg *cfg = mmc->priv;
 	struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base;
 #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
 	uint wml_value;
@@ -209,16 +221,16 @@ static int esdhc_setup_data(struct mmc *mmc, struct mmc_data *data)
 	 * 2)Timeout period should be minimum 0.250sec as per SD Card spec
 	 *  So, Number of SD Clock cycles for 0.25sec should be minimum
 	 *		(SD Clock/sec * 0.25 sec) SD Clock cycles
-	 *		= (mmc->tran_speed * 1/4) SD Clock cycles
+	 *		= (mmc->clock * 1/4) SD Clock cycles
 	 * As 1) >=  2)
-	 * => (2^(timeout+13)) >= mmc->tran_speed * 1/4
+	 * => (2^(timeout+13)) >= mmc->clock * 1/4
 	 * Taking log2 both the sides
-	 * => timeout + 13 >= log2(mmc->tran_speed/4)
+	 * => timeout + 13 >= log2(mmc->clock/4)
 	 * Rounding up to next power of 2
-	 * => timeout + 13 = log2(mmc->tran_speed/4) + 1
-	 * => timeout + 13 = fls(mmc->tran_speed/4)
+	 * => timeout + 13 = log2(mmc->clock/4) + 1
+	 * => timeout + 13 = fls(mmc->clock/4)
 	 */
-	timeout = fls(mmc->tran_speed/4);
+	timeout = fls(mmc->clock/4);
 	timeout -= 13;
 
 	if (timeout > 14)
@@ -232,6 +244,9 @@ static int esdhc_setup_data(struct mmc *mmc, struct mmc_data *data)
 		timeout++;
 #endif
 
+#ifdef ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE
+	timeout = 0xE;
+#endif
 	esdhc_clrsetbits32(&regs->sysctl, SYSCTL_TIMEOUT_MASK, timeout << 16);
 
 	return 0;
@@ -253,9 +268,10 @@ static void check_and_invalidate_dcache_range
 static int
 esdhc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data)
 {
+	int	err = 0;
 	uint	xfertyp;
 	uint	irqstat;
-	struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
+	struct fsl_esdhc_cfg *cfg = mmc->priv;
 	volatile struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base;
 
 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC111
@@ -284,8 +300,6 @@ esdhc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data)
 
 	/* Set up for a data transfer if we have one */
 	if (data) {
-		int err;
-
 		err = esdhc_setup_data(mmc, data);
 		if(err)
 			return err;
@@ -313,27 +327,15 @@ esdhc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data)
 
 	irqstat = esdhc_read32(&regs->irqstat);
 
-	/* Reset CMD and DATA portions on error */
-	if (irqstat & (CMD_ERR | IRQSTAT_CTOE)) {
-		esdhc_write32(&regs->sysctl, esdhc_read32(&regs->sysctl) |
-			      SYSCTL_RSTC);
-		while (esdhc_read32(&regs->sysctl) & SYSCTL_RSTC)
-			;
-
-		if (data) {
-			esdhc_write32(&regs->sysctl,
-				      esdhc_read32(&regs->sysctl) |
-				      SYSCTL_RSTD);
-			while ((esdhc_read32(&regs->sysctl) & SYSCTL_RSTD))
-				;
-		}
+	if (irqstat & CMD_ERR) {
+		err = COMM_ERR;
+		goto out;
 	}
 
-	if (irqstat & CMD_ERR)
-		return COMM_ERR;
-
-	if (irqstat & IRQSTAT_CTOE)
-		return TIMEOUT;
+	if (irqstat & IRQSTAT_CTOE) {
+		err = TIMEOUT;
+		goto out;
+	}
 
 	/* Workaround for ESDHC errata ENGcm03648 */
 	if (!data && (cmd->resp_type & MMC_RSP_BUSY)) {
@@ -348,7 +350,8 @@ esdhc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data)
 
 		if (timeout <= 0) {
 			printf("Timeout waiting for DAT0 to go high!\n");
-			return TIMEOUT;
+			err = TIMEOUT;
+			goto out;
 		}
 	}
 
@@ -375,32 +378,53 @@ esdhc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data)
 		do {
 			irqstat = esdhc_read32(&regs->irqstat);
 
-			if (irqstat & IRQSTAT_DTOE)
-				return TIMEOUT;
+			if (irqstat & IRQSTAT_DTOE) {
+				err = TIMEOUT;
+				goto out;
+			}
 
-			if (irqstat & DATA_ERR)
-				return COMM_ERR;
+			if (irqstat & DATA_ERR) {
+				err = COMM_ERR;
+				goto out;
+			}
 		} while ((irqstat & DATA_COMPLETE) != DATA_COMPLETE);
 #endif
 		if (data->flags & MMC_DATA_READ)
 			check_and_invalidate_dcache_range(cmd, data);
 	}
 
+out:
+	/* Reset CMD and DATA portions on error */
+	if (err) {
+		esdhc_write32(&regs->sysctl, esdhc_read32(&regs->sysctl) |
+			      SYSCTL_RSTC);
+		while (esdhc_read32(&regs->sysctl) & SYSCTL_RSTC)
+			;
+
+		if (data) {
+			esdhc_write32(&regs->sysctl,
+				      esdhc_read32(&regs->sysctl) |
+				      SYSCTL_RSTD);
+			while ((esdhc_read32(&regs->sysctl) & SYSCTL_RSTD))
+				;
+		}
+	}
+
 	esdhc_write32(&regs->irqstat, -1);
 
-	return 0;
+	return err;
 }
 
 static void set_sysctl(struct mmc *mmc, uint clock)
 {
 	int div, pre_div;
-	struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
+	struct fsl_esdhc_cfg *cfg = mmc->priv;
 	volatile struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base;
 	int sdhc_clk = cfg->sdhc_clk;
 	uint clk;
 
-	if (clock < mmc->f_min)
-		clock = mmc->f_min;
+	if (clock < mmc->cfg->f_min)
+		clock = mmc->cfg->f_min;
 
 	if (sdhc_clk / 16 > clock) {
 		for (pre_div = 2; pre_div < 256; pre_div *= 2)
@@ -431,7 +455,7 @@ static void set_sysctl(struct mmc *mmc, uint clock)
 
 static void esdhc_set_ios(struct mmc *mmc)
 {
-	struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
+	struct fsl_esdhc_cfg *cfg = mmc->priv;
 	struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base;
 
 	/* Set the clock speed */
@@ -449,7 +473,7 @@ static void esdhc_set_ios(struct mmc *mmc)
 
 static int esdhc_init(struct mmc *mmc)
 {
-	struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
+	struct fsl_esdhc_cfg *cfg = mmc->priv;
 	struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base;
 	int timeout = 1000;
 
@@ -484,10 +508,14 @@ static int esdhc_init(struct mmc *mmc)
 
 static int esdhc_getcd(struct mmc *mmc)
 {
-	struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
+	struct fsl_esdhc_cfg *cfg = mmc->priv;
 	struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base;
 	int timeout = 1000;
 
+#ifdef CONFIG_ESDHC_DETECT_QUIRK
+	if (CONFIG_ESDHC_DETECT_QUIRK)
+		return 1;
+#endif
 	while (!(esdhc_read32(&regs->prsstat) & PRSSTAT_CINS) && --timeout)
 		udelay(1000);
 
@@ -508,6 +536,13 @@ static void esdhc_reset(struct fsl_esdhc *regs)
 		printf("MMC/SD: Reset never completed.\n");
 }
 
+static const struct mmc_ops esdhc_ops = {
+	.send_cmd	= esdhc_send_cmd,
+	.set_ios	= esdhc_set_ios,
+	.init		= esdhc_init,
+	.getcd		= esdhc_getcd,
+};
+
 int fsl_esdhc_initialize(bd_t *bis, struct fsl_esdhc_cfg *cfg)
 {
 	struct fsl_esdhc *regs;
@@ -517,11 +552,6 @@ int fsl_esdhc_initialize(bd_t *bis, struct fsl_esdhc_cfg *cfg)
 	if (!cfg)
 		return -1;
 
-	mmc = malloc(sizeof(struct mmc));
-	if (!mmc)
-		return -ENOMEM;
-
-	sprintf(mmc->name, "FSL_SDHC");
 	regs = (struct fsl_esdhc *)cfg->esdhc_base;
 
 	/* First reset the eSDHC controller */
@@ -530,12 +560,7 @@ int fsl_esdhc_initialize(bd_t *bis, struct fsl_esdhc_cfg *cfg)
 	esdhc_setbits32(&regs->sysctl, SYSCTL_PEREN | SYSCTL_HCKEN
 				| SYSCTL_IPGEN | SYSCTL_CKEN);
 
-	mmc->priv = cfg;
-	mmc->send_cmd = esdhc_send_cmd;
-	mmc->set_ios = esdhc_set_ios;
-	mmc->init = esdhc_init;
-	mmc->getcd = esdhc_getcd;
-	mmc->getwp = NULL;
+	memset(&cfg->cfg, 0, sizeof(cfg->cfg));
 
 	voltage_caps = 0;
 	caps = regs->hostcapblt;
@@ -544,6 +569,12 @@ int fsl_esdhc_initialize(bd_t *bis, struct fsl_esdhc_cfg *cfg)
 	caps = caps & ~(ESDHC_HOSTCAPBLT_SRS |
 			ESDHC_HOSTCAPBLT_VS18 | ESDHC_HOSTCAPBLT_VS30);
 #endif
+
+/* T4240 host controller capabilities register should have VS33 bit */
+#ifdef CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
+	caps = caps | ESDHC_HOSTCAPBLT_VS33;
+#endif
+
 	if (caps & ESDHC_HOSTCAPBLT_VS18)
 		voltage_caps |= MMC_VDD_165_195;
 	if (caps & ESDHC_HOSTCAPBLT_VS30)
@@ -551,33 +582,43 @@ int fsl_esdhc_initialize(bd_t *bis, struct fsl_esdhc_cfg *cfg)
 	if (caps & ESDHC_HOSTCAPBLT_VS33)
 		voltage_caps |= MMC_VDD_32_33 | MMC_VDD_33_34;
 
+	cfg->cfg.name = "FSL_SDHC";
+	cfg->cfg.ops = &esdhc_ops;
 #ifdef CONFIG_SYS_SD_VOLTAGE
-	mmc->voltages = CONFIG_SYS_SD_VOLTAGE;
+	cfg->cfg.voltages = CONFIG_SYS_SD_VOLTAGE;
 #else
-	mmc->voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
+	cfg->cfg.voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
 #endif
-	if ((mmc->voltages & voltage_caps) == 0) {
+	if ((cfg->cfg.voltages & voltage_caps) == 0) {
 		printf("voltage not supported by controller\n");
 		return -1;
 	}
 
-	mmc->host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT | MMC_MODE_HC;
+	cfg->cfg.host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT | MMC_MODE_HC;
 
 	if (cfg->max_bus_width > 0) {
 		if (cfg->max_bus_width < 8)
-			mmc->host_caps &= ~MMC_MODE_8BIT;
+			cfg->cfg.host_caps &= ~MMC_MODE_8BIT;
 		if (cfg->max_bus_width < 4)
-			mmc->host_caps &= ~MMC_MODE_4BIT;
+			cfg->cfg.host_caps &= ~MMC_MODE_4BIT;
 	}
 
 	if (caps & ESDHC_HOSTCAPBLT_HSS)
-		mmc->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
+		cfg->cfg.host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
+
+#ifdef CONFIG_ESDHC_DETECT_8_BIT_QUIRK
+	if (CONFIG_ESDHC_DETECT_8_BIT_QUIRK)
+		cfg->cfg.host_caps &= ~MMC_MODE_8BIT;
+#endif
+
+	cfg->cfg.f_min = 400000;
+	cfg->cfg.f_max = MIN(gd->arch.sdhc_clk, 52000000);
 
-	mmc->f_min = 400000;
-	mmc->f_max = MIN(gd->arch.sdhc_clk, 52000000);
+	cfg->cfg.b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
 
-	mmc->b_max = 0;
-	mmc_register(mmc);
+	mmc = mmc_create(&cfg->cfg, cfg);
+	if (mmc == NULL)
+		return -1;
 
 	return 0;
 }
diff --git a/drivers/mmc/fsl_esdhc_spl.c b/drivers/mmc/fsl_esdhc_spl.c
index 65c52a22db..8fc263f4f4 100644
--- a/drivers/mmc/fsl_esdhc_spl.c
+++ b/drivers/mmc/fsl_esdhc_spl.c
@@ -42,6 +42,10 @@ void __noreturn mmc_boot(void)
 		hang();
 	}
 
+#ifdef CONFIG_FSL_CORENET
+	offset = CONFIG_SYS_MMC_U_BOOT_OFFS;
+	code_len = CONFIG_SYS_MMC_U_BOOT_SIZE;
+#else
 	blklen = mmc->read_bl_len;
 	tmp_buf = malloc(blklen);
 	if (!tmp_buf) {
@@ -91,6 +95,7 @@ void __noreturn mmc_boot(void)
 	/*
 	* Load U-Boot image from mmc into RAM
 	*/
+#endif
 	blk_start = ALIGN(offset, mmc->read_bl_len) / mmc->read_bl_len;
 	blk_cnt = ALIGN(code_len, mmc->read_bl_len) / mmc->read_bl_len;
 	err = mmc->block_dev.block_read(0, blk_start, blk_cnt,
diff --git a/drivers/mmc/ftsdc010_mci.c b/drivers/mmc/ftsdc010_mci.c
index 7600d5ce55..a620678e5f 100644
--- a/drivers/mmc/ftsdc010_mci.c
+++ b/drivers/mmc/ftsdc010_mci.c
@@ -27,6 +27,7 @@ struct ftsdc010_chip {
 	uint32_t sclk;    /* FTSDC010 source clock in Hz */
 	uint32_t fifo;    /* fifo depth in bytes */
 	uint32_t acmd;
+	struct mmc_config cfg;	/* mmc configuration */
 };
 
 static inline int ftsdc010_send_cmd(struct mmc *mmc, struct mmc_cmd *mmc_cmd)
@@ -123,14 +124,6 @@ static void ftsdc010_clkset(struct mmc *mmc, uint32_t rate)
 	}
 }
 
-static inline int ftsdc010_is_ro(struct mmc *mmc)
-{
-	struct ftsdc010_chip *chip = mmc->priv;
-	const uint8_t *csd = (const uint8_t *)mmc->csd;
-
-	return chip->wprot || (csd[1] & 0x30);
-}
-
 static int ftsdc010_wait(struct ftsdc010_mmc __iomem *regs, uint32_t mask)
 {
 	int ret = TIMEOUT;
@@ -316,6 +309,12 @@ static int ftsdc010_init(struct mmc *mmc)
 	return 0;
 }
 
+static const struct mmc_ops ftsdc010_ops = {
+	.send_cmd	= ftsdc010_request,
+	.set_ios	= ftsdc010_set_ios,
+	.init		= ftsdc010_init,
+};
+
 int ftsdc010_mmc_init(int devid)
 {
 	struct mmc *mmc;
@@ -331,50 +330,44 @@ int ftsdc010_mmc_init(int devid)
 	regs = (void __iomem *)(CONFIG_FTSDC010_BASE + (devid << 20));
 #endif
 
-	mmc = malloc(sizeof(struct mmc));
-	if (!mmc)
-		return -ENOMEM;
-	memset(mmc, 0, sizeof(struct mmc));
-
 	chip = malloc(sizeof(struct ftsdc010_chip));
-	if (!chip) {
-		free(mmc);
+	if (!chip)
 		return -ENOMEM;
-	}
 	memset(chip, 0, sizeof(struct ftsdc010_chip));
 
 	chip->regs = regs;
-	mmc->priv  = chip;
-
-	sprintf(mmc->name, "ftsdc010");
-	mmc->send_cmd  = ftsdc010_request;
-	mmc->set_ios   = ftsdc010_set_ios;
-	mmc->init      = ftsdc010_init;
+#ifdef CONFIG_SYS_CLK_FREQ
+	chip->sclk = CONFIG_SYS_CLK_FREQ;
+#else
+	chip->sclk = clk_get_rate("SDC");
+#endif
 
-	mmc->host_caps = MMC_MODE_HS | MMC_MODE_HS_52MHz;
+	chip->cfg.name = "ftsdc010";
+	chip->cfg.ops = &ftsdc010_ops;
+	chip->cfg.host_caps = MMC_MODE_HS | MMC_MODE_HS_52MHz;
 	switch (readl(&regs->bwr) & FTSDC010_BWR_CAPS_MASK) {
 	case FTSDC010_BWR_CAPS_4BIT:
-		mmc->host_caps |= MMC_MODE_4BIT;
+		chip->cfg.host_caps |= MMC_MODE_4BIT;
 		break;
 	case FTSDC010_BWR_CAPS_8BIT:
-		mmc->host_caps |= MMC_MODE_4BIT | MMC_MODE_8BIT;
+		chip->cfg.host_caps |= MMC_MODE_4BIT | MMC_MODE_8BIT;
 		break;
 	default:
 		break;
 	}
 
-#ifdef CONFIG_SYS_CLK_FREQ
-	chip->sclk = CONFIG_SYS_CLK_FREQ;
-#else
-	chip->sclk = clk_get_rate("SDC");
-#endif
+	chip->cfg.voltages  = MMC_VDD_32_33 | MMC_VDD_33_34;
+	chip->cfg.f_max     = chip->sclk / 2;
+	chip->cfg.f_min     = chip->sclk / 0x100;
 
-	mmc->voltages  = MMC_VDD_32_33 | MMC_VDD_33_34;
-	mmc->f_max     = chip->sclk / 2;
-	mmc->f_min     = chip->sclk / 0x100;
-	mmc->block_dev.part_type = PART_TYPE_DOS;
+	chip->cfg.part_type = PART_TYPE_DOS;
+	chip->cfg.b_max	    = CONFIG_SYS_MMC_MAX_BLK_COUNT;
 
-	mmc_register(mmc);
+	mmc = mmc_create(&chip->cfg, chip);
+	if (mmc == NULL) {
+		free(chip);
+		return -ENOMEM;
+	}
 
 	return 0;
 }
diff --git a/drivers/mmc/ftsdc021_sdhci.c b/drivers/mmc/ftsdc021_sdhci.c
new file mode 100644
index 0000000000..1f6cdba173
--- /dev/null
+++ b/drivers/mmc/ftsdc021_sdhci.c
@@ -0,0 +1,33 @@
+/*
+ * (C) Copyright 2013 Faraday Technology
+ * Kuo-Jung Su <dantesu@faraday-tech.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <malloc.h>
+#include <sdhci.h>
+
+#ifndef CONFIG_FTSDC021_CLOCK
+#define CONFIG_FTSDC021_CLOCK   clk_get_rate("MMC")
+#endif
+
+int ftsdc021_sdhci_init(u32 regbase)
+{
+	struct sdhci_host *host = NULL;
+	uint32_t freq = CONFIG_FTSDC021_CLOCK;
+
+	host = calloc(1, sizeof(struct sdhci_host));
+	if (!host) {
+		puts("sdh_host malloc fail!\n");
+		return 1;
+	}
+
+	host->name = "FTSDC021";
+	host->ioaddr = (void __iomem *)regbase;
+	host->quirks = 0;
+	add_sdhci(host, freq, 0);
+
+	return 0;
+}
diff --git a/drivers/mmc/gen_atmel_mci.c b/drivers/mmc/gen_atmel_mci.c
index c11dcd0f97..acca0269e5 100644
--- a/drivers/mmc/gen_atmel_mci.c
+++ b/drivers/mmc/gen_atmel_mci.c
@@ -55,7 +55,7 @@ static void dump_cmd(u32 cmdr, u32 arg, u32 status, const char* msg)
 /* Setup for MCI Clock and Block Size */
 static void mci_set_mode(struct mmc *mmc, u32 hz, u32 blklen)
 {
-	atmel_mci_t *mci = (atmel_mci_t *)mmc->priv;
+	atmel_mci_t *mci = mmc->priv;
 	u32 bus_hz = get_mci_clk_rate();
 	u32 clkdiv = 255;
 
@@ -165,7 +165,7 @@ io_fail:
 static int
 mci_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data)
 {
-	atmel_mci_t *mci = (atmel_mci_t *)mmc->priv;
+	atmel_mci_t *mci = mmc->priv;
 	u32 cmdr;
 	u32 error_flags = 0;
 	u32 status;
@@ -289,7 +289,7 @@ mci_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data)
 /* Entered into mmc structure during driver init */
 static void mci_set_ios(struct mmc *mmc)
 {
-	atmel_mci_t *mci = (atmel_mci_t *)mmc->priv;
+	atmel_mci_t *mci = mmc->priv;
 	int bus_width = mmc->bus_width;
 	unsigned int version = atmel_mci_get_version(mci);
 	int busw;
@@ -325,7 +325,7 @@ static void mci_set_ios(struct mmc *mmc)
 /* Entered into mmc structure during driver init */
 static int mci_init(struct mmc *mmc)
 {
-	atmel_mci_t *mci = (atmel_mci_t *)mmc->priv;
+	atmel_mci_t *mci = mmc->priv;
 
 	/* Initialize controller */
 	writel(MMCI_BIT(SWRST), &mci->cr);	/* soft reset */
@@ -344,6 +344,12 @@ static int mci_init(struct mmc *mmc)
 	return 0;
 }
 
+static const struct mmc_ops atmel_mci_ops = {
+	.send_cmd	= mci_send_cmd,
+	.set_ios	= mci_set_ios,
+	.init		= mci_init,
+};
+
 /*
  * This is the only exported function
  *
@@ -351,40 +357,45 @@ static int mci_init(struct mmc *mmc)
  */
 int atmel_mci_init(void *regs)
 {
-	struct mmc *mmc = malloc(sizeof(struct mmc));
+	struct mmc *mmc;
+	struct mmc_config *cfg;
 	struct atmel_mci *mci;
 	unsigned int version;
 
-	if (!mmc)
+	cfg = malloc(sizeof(*cfg));
+	if (cfg == NULL)
 		return -1;
+	memset(cfg, 0, sizeof(*cfg));
+
+	mci = (struct atmel_mci *)regs;
 
-	strcpy(mmc->name, "mci");
-	mmc->priv = regs;
-	mmc->send_cmd = mci_send_cmd;
-	mmc->set_ios = mci_set_ios;
-	mmc->init = mci_init;
-	mmc->getcd = NULL;
-	mmc->getwp = NULL;
+	cfg->name = "mci";
+	cfg->ops = &atmel_mci_ops;
 
 	/* need to be able to pass these in on a board by board basis */
-	mmc->voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
-	mci = (struct atmel_mci *)mmc->priv;
+	cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
 	version = atmel_mci_get_version(mci);
 	if ((version & 0xf00) >= 0x300)
-		mmc->host_caps = MMC_MODE_8BIT;
+		cfg->host_caps = MMC_MODE_8BIT;
 
-	mmc->host_caps |= MMC_MODE_4BIT;
+	cfg->host_caps |= MMC_MODE_4BIT;
 
 	/*
 	 * min and max frequencies determined by
 	 * max and min of clock divider
 	 */
-	mmc->f_min = get_mci_clk_rate() / (2*256);
-	mmc->f_max = get_mci_clk_rate() / (2*1);
+	cfg->f_min = get_mci_clk_rate() / (2*256);
+	cfg->f_max = get_mci_clk_rate() / (2*1);
+
+	cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
 
-	mmc->b_max = 0;
+	mmc = mmc_create(cfg, regs);
 
-	mmc_register(mmc);
+	if (mmc == NULL) {
+		free(cfg);
+		return -1;
+	}
+	/* NOTE: possibly leaking the cfg structure */
 
 	return 0;
 }
diff --git a/drivers/mmc/kona_sdhci.c b/drivers/mmc/kona_sdhci.c
new file mode 100644
index 0000000000..77e42c8afe
--- /dev/null
+++ b/drivers/mmc/kona_sdhci.c
@@ -0,0 +1,134 @@
+/*
+ * Copyright 2013 Broadcom Corporation.
+ *
+ * SPDX-License-Identifier:      GPL-2.0+
+ */
+
+#include <common.h>
+#include <malloc.h>
+#include <sdhci.h>
+#include <asm/errno.h>
+#include <asm/kona-common/clk.h>
+
+#define SDHCI_CORECTRL_OFFSET		0x00008000
+#define SDHCI_CORECTRL_EN		0x01
+#define SDHCI_CORECTRL_RESET		0x02
+
+#define SDHCI_CORESTAT_OFFSET		0x00008004
+#define SDHCI_CORESTAT_CD_SW		0x01
+
+#define SDHCI_COREIMR_OFFSET		0x00008008
+#define SDHCI_COREIMR_IP		0x01
+
+static int init_kona_mmc_core(struct sdhci_host *host)
+{
+	unsigned int mask;
+	unsigned int timeout;
+
+	if (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & SDHCI_RESET_ALL) {
+		printf("%s: sd host controller reset error\n", __func__);
+		return 1;
+	}
+
+	/* For kona a hardware reset before anything else. */
+	mask = sdhci_readl(host, SDHCI_CORECTRL_OFFSET) | SDHCI_CORECTRL_RESET;
+	sdhci_writel(host, mask, SDHCI_CORECTRL_OFFSET);
+
+	/* Wait max 100 ms */
+	timeout = 1000;
+	do {
+		if (timeout == 0) {
+			printf("%s: reset timeout error\n", __func__);
+			return 1;
+		}
+		timeout--;
+		udelay(100);
+	} while (0 ==
+		 (sdhci_readl(host, SDHCI_CORECTRL_OFFSET) &
+		  SDHCI_CORECTRL_RESET));
+
+	/* Clear the reset bit. */
+	mask = mask & ~SDHCI_CORECTRL_RESET;
+	sdhci_writel(host, mask, SDHCI_CORECTRL_OFFSET);
+
+	/* Enable AHB clock */
+	mask = sdhci_readl(host, SDHCI_CORECTRL_OFFSET);
+	sdhci_writel(host, mask | SDHCI_CORECTRL_EN, SDHCI_CORECTRL_OFFSET);
+
+	/* Enable interrupts */
+	sdhci_writel(host, SDHCI_COREIMR_IP, SDHCI_COREIMR_OFFSET);
+
+	/* Make sure Card is detected in controller */
+	mask = sdhci_readl(host, SDHCI_CORESTAT_OFFSET);
+	sdhci_writel(host, mask | SDHCI_CORESTAT_CD_SW, SDHCI_CORESTAT_OFFSET);
+
+	/* Wait max 100 ms */
+	timeout = 1000;
+	while (!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT)) {
+		if (timeout == 0) {
+			printf("%s: CARD DETECT timeout error\n", __func__);
+			return 1;
+		}
+		timeout--;
+		udelay(100);
+	}
+	return 0;
+}
+
+int kona_sdhci_init(int dev_index, u32 min_clk, u32 quirks)
+{
+	int ret = 0;
+	u32 max_clk;
+	void *reg_base;
+	struct sdhci_host *host = NULL;
+
+	host = (struct sdhci_host *)malloc(sizeof(struct sdhci_host));
+	if (!host) {
+		printf("%s: sdhci host malloc fail!\n", __func__);
+		return -ENOMEM;
+	}
+	switch (dev_index) {
+	case 0:
+		reg_base = (void *)CONFIG_SYS_SDIO_BASE0;
+		ret = clk_sdio_enable(reg_base, CONFIG_SYS_SDIO0_MAX_CLK,
+				      &max_clk);
+		break;
+	case 1:
+		reg_base = (void *)CONFIG_SYS_SDIO_BASE1;
+		ret = clk_sdio_enable(reg_base, CONFIG_SYS_SDIO1_MAX_CLK,
+				      &max_clk);
+		break;
+	case 2:
+		reg_base = (void *)CONFIG_SYS_SDIO_BASE2;
+		ret = clk_sdio_enable(reg_base, CONFIG_SYS_SDIO2_MAX_CLK,
+				      &max_clk);
+		break;
+	case 3:
+		reg_base = (void *)CONFIG_SYS_SDIO_BASE3;
+		ret = clk_sdio_enable(reg_base, CONFIG_SYS_SDIO3_MAX_CLK,
+				      &max_clk);
+		break;
+	default:
+		printf("%s: sdio dev index %d not supported\n",
+		       __func__, dev_index);
+		ret = -EINVAL;
+	}
+	if (ret)
+		return ret;
+
+	host->name = "kona-sdhci";
+	host->ioaddr = reg_base;
+	host->quirks = quirks;
+	host->host_caps = MMC_MODE_HC;
+
+	if (init_kona_mmc_core(host))
+		return -EINVAL;
+
+	if (quirks & SDHCI_QUIRK_REG32_RW)
+		host->version = sdhci_readl(host, SDHCI_HOST_VERSION - 2) >> 16;
+	else
+		host->version = sdhci_readw(host, SDHCI_HOST_VERSION);
+
+	add_sdhci(host, max_clk, min_clk);
+	return ret;
+}
diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c
index 84dae4d8bd..16051e52ff 100644
--- a/drivers/mmc/mmc.c
+++ b/drivers/mmc/mmc.c
@@ -17,11 +17,6 @@
 #include <div64.h>
 #include "mmc_private.h"
 
-/* Set block count limit because of 16 bit register limit on some hardware*/
-#ifndef CONFIG_SYS_MMC_MAX_BLK_COUNT
-#define CONFIG_SYS_MMC_MAX_BLK_COUNT 65535
-#endif
-
 static struct list_head mmc_devices;
 static int cur_dev_num = -1;
 
@@ -37,8 +32,8 @@ int mmc_getwp(struct mmc *mmc)
 	wp = board_mmc_getwp(mmc);
 
 	if (wp < 0) {
-		if (mmc->getwp)
-			wp = mmc->getwp(mmc);
+		if (mmc->cfg->ops->getwp)
+			wp = mmc->cfg->ops->getwp(mmc);
 		else
 			wp = 0;
 	}
@@ -63,7 +58,7 @@ int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data)
 
 	printf("CMD_SEND:%d\n", cmd->cmdidx);
 	printf("\t\tARG\t\t\t 0x%08X\n", cmd->cmdarg);
-	ret = mmc->send_cmd(mmc, cmd, data);
+	ret = mmc->cfg->ops->send_cmd(mmc, cmd, data);
 	switch (cmd->resp_type) {
 		case MMC_RSP_NONE:
 			printf("\t\tMMC_RSP_NONE\n");
@@ -106,7 +101,7 @@ int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data)
 			break;
 	}
 #else
-	ret = mmc->send_cmd(mmc, cmd, data);
+	ret = mmc->cfg->ops->send_cmd(mmc, cmd, data);
 #endif
 	return ret;
 }
@@ -253,7 +248,8 @@ static ulong mmc_bread(int dev_num, lbaint_t start, lbaint_t blkcnt, void *dst)
 		return 0;
 
 	do {
-		cur = (blocks_todo > mmc->b_max) ?  mmc->b_max : blocks_todo;
+		cur = (blocks_todo > mmc->cfg->b_max) ?
+			mmc->cfg->b_max : blocks_todo;
 		if(mmc_read_blocks(mmc, dst, start, cur) != cur)
 			return 0;
 		blocks_todo -= cur;
@@ -312,7 +308,7 @@ static int sd_send_op_cond(struct mmc *mmc)
 		 * specified.
 		 */
 		cmd.cmdarg = mmc_host_is_spi(mmc) ? 0 :
-			(mmc->voltages & 0xff8000);
+			(mmc->cfg->voltages & 0xff8000);
 
 		if (mmc->version == SD_VERSION_2)
 			cmd.cmdarg |= OCR_HCS;
@@ -361,11 +357,11 @@ static int mmc_send_op_cond_iter(struct mmc *mmc, struct mmc_cmd *cmd,
 	cmd->cmdarg = 0;
 	if (use_arg && !mmc_host_is_spi(mmc)) {
 		cmd->cmdarg =
-			(mmc->voltages &
+			(mmc->cfg->voltages &
 			(mmc->op_cond_response & OCR_VOLTAGE_MASK)) |
 			(mmc->op_cond_response & OCR_ACCESS_MODE);
 
-		if (mmc->host_caps & MMC_MODE_HC)
+		if (mmc->cfg->host_caps & MMC_MODE_HC)
 			cmd->cmdarg |= OCR_HCS;
 	}
 	err = mmc_send_cmd(mmc, cmd, NULL);
@@ -430,7 +426,7 @@ int mmc_complete_op_cond(struct mmc *mmc)
 	mmc->ocr = cmd.response[0];
 
 	mmc->high_capacity = ((mmc->ocr & OCR_HCS) == OCR_HCS);
-	mmc->rca = 0;
+	mmc->rca = 1;
 
 	return 0;
 }
@@ -578,8 +574,8 @@ int mmc_getcd(struct mmc *mmc)
 	cd = board_mmc_getcd(mmc);
 
 	if (cd < 0) {
-		if (mmc->getcd)
-			cd = mmc->getcd(mmc);
+		if (mmc->cfg->ops->getcd)
+			cd = mmc->cfg->ops->getcd(mmc);
 		else
 			cd = 1;
 	}
@@ -703,8 +699,8 @@ retry_scr:
 	 * This can avoid furthur problem when the card runs in different
 	 * mode between the host.
 	 */
-	if (!((mmc->host_caps & MMC_MODE_HS_52MHz) &&
-		(mmc->host_caps & MMC_MODE_HS)))
+	if (!((mmc->cfg->host_caps & MMC_MODE_HS_52MHz) &&
+		(mmc->cfg->host_caps & MMC_MODE_HS)))
 		return 0;
 
 	err = sd_switch(mmc, SD_SWITCH_SWITCH, 0, 1, (u8 *)switch_status);
@@ -751,16 +747,17 @@ static const int multipliers[] = {
 
 static void mmc_set_ios(struct mmc *mmc)
 {
-	mmc->set_ios(mmc);
+	if (mmc->cfg->ops->set_ios)
+		mmc->cfg->ops->set_ios(mmc);
 }
 
 void mmc_set_clock(struct mmc *mmc, uint clock)
 {
-	if (clock > mmc->f_max)
-		clock = mmc->f_max;
+	if (clock > mmc->cfg->f_max)
+		clock = mmc->cfg->f_max;
 
-	if (clock < mmc->f_min)
-		clock = mmc->f_min;
+	if (clock < mmc->cfg->f_min)
+		clock = mmc->cfg->f_min;
 
 	mmc->clock = clock;
 
@@ -877,6 +874,7 @@ static int mmc_startup(struct mmc *mmc)
 
 	mmc->tran_speed = freq * mult;
 
+	mmc->dsr_imp = ((cmd.response[1] >> 12) & 0x1);
 	mmc->read_bl_len = 1 << ((cmd.response[1] >> 16) & 0xf);
 
 	if (IS_SD(mmc))
@@ -907,6 +905,14 @@ static int mmc_startup(struct mmc *mmc)
 	if (mmc->write_bl_len > MMC_MAX_BLOCK_LEN)
 		mmc->write_bl_len = MMC_MAX_BLOCK_LEN;
 
+	if ((mmc->dsr_imp) && (0xffffffff != mmc->dsr)) {
+		cmd.cmdidx = MMC_CMD_SET_DSR;
+		cmd.cmdarg = (mmc->dsr & 0xffff) << 16;
+		cmd.resp_type = MMC_RSP_NONE;
+		if (mmc_send_cmd(mmc, &cmd, NULL))
+			printf("MMC: SET_DSR failed\n");
+	}
+
 	/* Select the card, and put it into Transfer Mode */
 	if (!mmc_host_is_spi(mmc)) { /* cmd not supported in spi */
 		cmd.cmdidx = MMC_CMD_SELECT_CARD;
@@ -960,15 +966,24 @@ static int mmc_startup(struct mmc *mmc)
 		}
 
 		/*
-		 * Check whether GROUP_DEF is set, if yes, read out
-		 * group size from ext_csd directly, or calculate
-		 * the group size from the csd value.
+		 * Host needs to enable ERASE_GRP_DEF bit if device is
+		 * partitioned. This bit will be lost every time after a reset
+		 * or power off. This will affect erase size.
 		 */
-		if (ext_csd[EXT_CSD_ERASE_GROUP_DEF]) {
+		if ((ext_csd[EXT_CSD_PARTITIONING_SUPPORT] & PART_SUPPORT) &&
+		    (ext_csd[EXT_CSD_PARTITIONS_ATTRIBUTE] & PART_ENH_ATTRIB)) {
+			err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
+				EXT_CSD_ERASE_GROUP_DEF, 1);
+
+			if (err)
+				return err;
+
+			/* Read out group size from ext_csd */
 			mmc->erase_grp_size =
 				ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE] *
 					MMC_MAX_BLOCK_LEN * 1024;
 		} else {
+			/* Calculate the group size from the csd value. */
 			int erase_gsz, erase_gmul;
 			erase_gsz = (mmc->csd[2] & 0x00007c00) >> 10;
 			erase_gmul = (mmc->csd[2] & 0x000003e0) >> 5;
@@ -1008,7 +1023,7 @@ static int mmc_startup(struct mmc *mmc)
 		return err;
 
 	/* Restrict card's capabilities by what the host can do */
-	mmc->card_caps &= mmc->host_caps;
+	mmc->card_caps &= mmc->cfg->host_caps;
 
 	if (IS_SD(mmc)) {
 		if (mmc->card_caps & MMC_MODE_4BIT) {
@@ -1063,7 +1078,7 @@ static int mmc_startup(struct mmc *mmc)
 			 * this bus width, if it's more than 1
 			 */
 			if (extw != EXT_CSD_BUS_WIDTH_1 &&
-					!(mmc->host_caps & ext_to_hostcaps[extw]))
+					!(mmc->cfg->host_caps & ext_to_hostcaps[extw]))
 				continue;
 
 			err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
@@ -1136,7 +1151,7 @@ static int mmc_send_if_cond(struct mmc *mmc)
 
 	cmd.cmdidx = SD_CMD_SEND_IF_COND;
 	/* We set the bit if the host supports voltages between 2.7 and 3.6 V */
-	cmd.cmdarg = ((mmc->voltages & 0xff8000) != 0) << 8 | 0xaa;
+	cmd.cmdarg = ((mmc->cfg->voltages & 0xff8000) != 0) << 8 | 0xaa;
 	cmd.resp_type = MMC_RSP_R7;
 
 	err = mmc_send_cmd(mmc, &cmd, NULL);
@@ -1152,8 +1167,36 @@ static int mmc_send_if_cond(struct mmc *mmc)
 	return 0;
 }
 
-int mmc_register(struct mmc *mmc)
+/* not used any more */
+int __deprecated mmc_register(struct mmc *mmc)
+{
+#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
+	printf("%s is deprecated! use mmc_create() instead.\n", __func__);
+#endif
+	return -1;
+}
+
+struct mmc *mmc_create(const struct mmc_config *cfg, void *priv)
 {
+	struct mmc *mmc;
+
+	/* quick validation */
+	if (cfg == NULL || cfg->ops == NULL || cfg->ops->send_cmd == NULL ||
+			cfg->f_min == 0 || cfg->f_max == 0 || cfg->b_max == 0)
+		return NULL;
+
+	mmc = calloc(1, sizeof(*mmc));
+	if (mmc == NULL)
+		return NULL;
+
+	mmc->cfg = cfg;
+	mmc->priv = priv;
+
+	/* the following chunk was mmc_register() */
+
+	/* Setup dsr related values */
+	mmc->dsr_imp = 0;
+	mmc->dsr = 0xffffffff;
 	/* Setup the universal parts of the block interface just once */
 	mmc->block_dev.if_type = IF_TYPE_MMC;
 	mmc->block_dev.dev = cur_dev_num++;
@@ -1161,14 +1204,21 @@ int mmc_register(struct mmc *mmc)
 	mmc->block_dev.block_read = mmc_bread;
 	mmc->block_dev.block_write = mmc_bwrite;
 	mmc->block_dev.block_erase = mmc_berase;
-	if (!mmc->b_max)
-		mmc->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
 
-	INIT_LIST_HEAD (&mmc->link);
+	/* setup initial part type */
+	mmc->block_dev.part_type = mmc->cfg->part_type;
 
-	list_add_tail (&mmc->link, &mmc_devices);
+	INIT_LIST_HEAD(&mmc->link);
 
-	return 0;
+	list_add_tail(&mmc->link, &mmc_devices);
+
+	return mmc;
+}
+
+void mmc_destroy(struct mmc *mmc)
+{
+	/* only freeing memory for now */
+	free(mmc);
 }
 
 #ifdef CONFIG_PARTITIONS
@@ -1186,7 +1236,8 @@ int mmc_start_init(struct mmc *mmc)
 {
 	int err;
 
-	if (mmc_getcd(mmc) == 0) {
+	/* we pretend there's no card when init is NULL */
+	if (mmc_getcd(mmc) == 0 || mmc->cfg->ops->init == NULL) {
 		mmc->has_init = 0;
 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
 		printf("MMC: no card present\n");
@@ -1197,7 +1248,8 @@ int mmc_start_init(struct mmc *mmc)
 	if (mmc->has_init)
 		return 0;
 
-	err = mmc->init(mmc);
+	/* made sure it's not NULL earlier */
+	err = mmc->cfg->ops->init(mmc);
 
 	if (err)
 		return err;
@@ -1271,6 +1323,12 @@ int mmc_init(struct mmc *mmc)
 	return err;
 }
 
+int mmc_set_dsr(struct mmc *mmc, u16 val)
+{
+	mmc->dsr = val;
+	return 0;
+}
+
 /*
  * CPU and board-specific MMC initializations.  Aliased function
  * signals caller to move on
@@ -1293,7 +1351,7 @@ void print_mmc_devices(char separator)
 	list_for_each(entry, &mmc_devices) {
 		m = list_entry(entry, struct mmc, link);
 
-		printf("%s: %d", m->name, m->block_dev.dev);
+		printf("%s: %d", m->cfg->name, m->block_dev.dev);
 
 		if (entry->next != &mmc_devices)
 			printf("%c ", separator);
@@ -1415,67 +1473,56 @@ int mmc_boot_partition_size_change(struct mmc *mmc, unsigned long bootsize,
 }
 
 /*
- * This function shall form and send the commands to open / close the
- * boot partition specified by user.
- *
- * Input Parameters:
- * ack: 0x0 - No boot acknowledge sent (default)
- *	0x1 - Boot acknowledge sent during boot operation
- * part_num: User selects boot data that will be sent to master
- *	0x0 - Device not boot enabled (default)
- *	0x1 - Boot partition 1 enabled for boot
- *	0x2 - Boot partition 2 enabled for boot
- * access: User selects partitions to access
- *	0x0 : No access to boot partition (default)
- *	0x1 : R/W boot partition 1
- *	0x2 : R/W boot partition 2
- *	0x3 : R/W Replay Protected Memory Block (RPMB)
+ * Modify EXT_CSD[177] which is BOOT_BUS_WIDTH
+ * based on the passed in values for BOOT_BUS_WIDTH, RESET_BOOT_BUS_WIDTH
+ * and BOOT_MODE.
  *
  * Returns 0 on success.
  */
-int mmc_boot_part_access(struct mmc *mmc, u8 ack, u8 part_num, u8 access)
+int mmc_set_boot_bus_width(struct mmc *mmc, u8 width, u8 reset, u8 mode)
 {
 	int err;
-	struct mmc_cmd cmd;
 
-	/* Boot ack enable, boot partition enable , boot partition access */
-	cmd.cmdidx = MMC_CMD_SWITCH;
-	cmd.resp_type = MMC_RSP_R1b;
-
-	cmd.cmdarg = (MMC_SWITCH_MODE_WRITE_BYTE << 24) |
-			(EXT_CSD_PART_CONF << 16) |
-			((EXT_CSD_BOOT_ACK(ack) |
-			EXT_CSD_BOOT_PART_NUM(part_num) |
-			EXT_CSD_PARTITION_ACCESS(access)) << 8);
+	err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_BOOT_BUS_WIDTH,
+			 EXT_CSD_BOOT_BUS_WIDTH_MODE(mode) |
+			 EXT_CSD_BOOT_BUS_WIDTH_RESET(reset) |
+			 EXT_CSD_BOOT_BUS_WIDTH_WIDTH(width));
 
-	err = mmc_send_cmd(mmc, &cmd, NULL);
-	if (err) {
-		if (access) {
-			debug("mmc boot partition#%d open fail:Error1 = %d\n",
-			      part_num, err);
-		} else {
-			debug("mmc boot partition#%d close fail:Error = %d\n",
-			      part_num, err);
-		}
+	if (err)
 		return err;
-	}
+	return 0;
+}
 
-	if (access) {
-		/* 4bit transfer mode at booting time. */
-		cmd.cmdidx = MMC_CMD_SWITCH;
-		cmd.resp_type = MMC_RSP_R1b;
+/*
+ * Modify EXT_CSD[179] which is PARTITION_CONFIG (formerly BOOT_CONFIG)
+ * based on the passed in values for BOOT_ACK, BOOT_PARTITION_ENABLE and
+ * PARTITION_ACCESS.
+ *
+ * Returns 0 on success.
+ */
+int mmc_set_part_conf(struct mmc *mmc, u8 ack, u8 part_num, u8 access)
+{
+	int err;
 
-		cmd.cmdarg = (MMC_SWITCH_MODE_WRITE_BYTE << 24) |
-				(EXT_CSD_BOOT_BUS_WIDTH << 16) |
-				((1 << 0) << 8);
+	err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_PART_CONF,
+			 EXT_CSD_BOOT_ACK(ack) |
+			 EXT_CSD_BOOT_PART_NUM(part_num) |
+			 EXT_CSD_PARTITION_ACCESS(access));
 
-		err = mmc_send_cmd(mmc, &cmd, NULL);
-		if (err) {
-			debug("mmc boot partition#%d open fail:Error2 = %d\n",
-			      part_num, err);
-			return err;
-		}
-	}
+	if (err)
+		return err;
 	return 0;
 }
+
+/*
+ * Modify EXT_CSD[162] which is RST_n_FUNCTION based on the given value
+ * for enable.  Note that this is a write-once field for non-zero values.
+ *
+ * Returns 0 on success.
+ */
+int mmc_set_rst_n_function(struct mmc *mmc, u8 enable)
+{
+	return mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_RST_N_FUNCTION,
+			  enable);
+}
 #endif
diff --git a/drivers/mmc/mmc_spi.c b/drivers/mmc/mmc_spi.c
index fe6a5a166d..5b5b33a4b2 100644
--- a/drivers/mmc/mmc_spi.c
+++ b/drivers/mmc/mmc_spi.c
@@ -92,7 +92,7 @@ static uint mmc_spi_readdata(struct mmc *mmc, void *xbuf,
 			spi_xfer(spi, 2 * 8, NULL, &crc, 0);
 #ifdef CONFIG_MMC_SPI_CRC_ON
 			if (swab16(cyg_crc16(buf, bsize)) != crc) {
-				debug("%s: CRC error\n", mmc->name);
+				debug("%s: CRC error\n", mmc->cfg->name);
 				r1 = R1_SPI_COM_CRC;
 				break;
 			}
@@ -238,6 +238,7 @@ done:
 static void mmc_spi_set_ios(struct mmc *mmc)
 {
 	struct spi_slave *spi = mmc->priv;
+
 	debug("%s: clock %u\n", __func__, mmc->clock);
 	if (mmc->clock)
 		spi_set_speed(spi, mmc->clock);
@@ -246,7 +247,6 @@ static void mmc_spi_set_ios(struct mmc *mmc)
 static int mmc_spi_init_p(struct mmc *mmc)
 {
 	struct spi_slave *spi = mmc->priv;
-	mmc->clock = 0;
 	spi_set_speed(spi, MMC_SPI_MIN_CLOCK);
 	spi_claim_bus(spi);
 	/* cs deactivated for 100+ clock */
@@ -255,33 +255,37 @@ static int mmc_spi_init_p(struct mmc *mmc)
 	return 0;
 }
 
+static const struct mmc_ops mmc_spi_ops = {
+	.send_cmd	= mmc_spi_request,
+	.set_ios	= mmc_spi_set_ios,
+	.init		= mmc_spi_init_p,
+};
+
+static struct mmc_config mmc_spi_cfg = {
+	.name		= "MMC_SPI",
+	.ops		= &mmc_spi_ops,
+	.host_caps	= MMC_MODE_SPI,
+	.voltages	= MMC_SPI_VOLTAGE,
+	.f_min		= MMC_SPI_MIN_CLOCK,
+	.part_type	= PART_TYPE_DOS,
+	.b_max		= CONFIG_SYS_MMC_MAX_BLK_COUNT,
+};
+
 struct mmc *mmc_spi_init(uint bus, uint cs, uint speed, uint mode)
 {
 	struct mmc *mmc;
+	struct spi_slave *spi;
 
-	mmc = malloc(sizeof(*mmc));
-	if (!mmc)
-		return NULL;
-	memset(mmc, 0, sizeof(*mmc));
-	mmc->priv = spi_setup_slave(bus, cs, speed, mode);
-	if (!mmc->priv) {
-		free(mmc);
+	spi = spi_setup_slave(bus, cs, speed, mode);
+	if (spi == NULL)
 		return NULL;
-	}
-	sprintf(mmc->name, "MMC_SPI");
-	mmc->send_cmd = mmc_spi_request;
-	mmc->set_ios = mmc_spi_set_ios;
-	mmc->init = mmc_spi_init_p;
-	mmc->getcd = NULL;
-	mmc->getwp = NULL;
-	mmc->host_caps = MMC_MODE_SPI;
-
-	mmc->voltages = MMC_SPI_VOLTAGE;
-	mmc->f_max = speed;
-	mmc->f_min = MMC_SPI_MIN_CLOCK;
-	mmc->block_dev.part_type = PART_TYPE_DOS;
 
-	mmc_register(mmc);
+	mmc_spi_cfg.f_max = speed;
 
+	mmc = mmc_create(&mmc_spi_cfg, spi);
+	if (mmc == NULL) {
+		spi_free_slave(spi);
+		return NULL;
+	}
 	return mmc;
 }
diff --git a/drivers/mmc/mmc_write.c b/drivers/mmc/mmc_write.c
index aa2fdefa75..3db9669c82 100644
--- a/drivers/mmc/mmc_write.c
+++ b/drivers/mmc/mmc_write.c
@@ -167,7 +167,8 @@ ulong mmc_bwrite(int dev_num, lbaint_t start, lbaint_t blkcnt, const void *src)
 		return 0;
 
 	do {
-		cur = (blocks_todo > mmc->b_max) ?  mmc->b_max : blocks_todo;
+		cur = (blocks_todo > mmc->cfg->b_max) ?
+			mmc->cfg->b_max : blocks_todo;
 		if (mmc_write_blocks(mmc, start, cur, src) != cur)
 			return 0;
 		blocks_todo -= cur;
diff --git a/drivers/mmc/mxcmmc.c b/drivers/mmc/mxcmmc.c
index 4f99617b9a..561b204598 100644
--- a/drivers/mmc/mxcmmc.c
+++ b/drivers/mmc/mxcmmc.c
@@ -122,6 +122,8 @@ struct mxcmci_host {
 };
 
 static struct mxcmci_host mxcmci_host;
+
+/* maintainer note: do we really want to have a global host pointer? */
 static struct mxcmci_host *host = &mxcmci_host;
 
 static inline int mxcmci_use_dma(struct mxcmci_host *host)
@@ -485,35 +487,30 @@ static int mxcmci_init(struct mmc *mmc)
 	return 0;
 }
 
-static int mxcmci_initialize(bd_t *bis)
-{
-	struct mmc *mmc = NULL;
-
-	mmc = malloc(sizeof(struct mmc));
-
-	if (!mmc)
-		return -ENOMEM;
+static const struct mmc_ops mxcmci_ops = {
+	.send_cmd	= mxcmci_request,
+	.set_ios	= mxcmci_set_ios,
+	.init		= mxcmci_init,
+};
 
-	sprintf(mmc->name, "MXC MCI");
-	mmc->send_cmd = mxcmci_request;
-	mmc->set_ios = mxcmci_set_ios;
-	mmc->init = mxcmci_init;
-	mmc->getcd = NULL;
-	mmc->getwp = NULL;
-	mmc->host_caps = MMC_MODE_4BIT;
+static struct mmc_config mxcmci_cfg = {
+	.name		= "MXC MCI",
+	.ops		= &mxcmci_ops,
+	.host_caps	= MMC_MODE_4BIT,
+	.voltages	= MMC_VDD_32_33 | MMC_VDD_33_34,
+	.b_max		= CONFIG_SYS_MMC_MAX_BLK_COUNT,
+};
 
+static int mxcmci_initialize(bd_t *bis)
+{
 	host->base = (struct mxcmci_regs *)CONFIG_MXC_MCI_REGS_BASE;
-	mmc->priv = host;
-	host->mmc = mmc;
-
-	mmc->voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
-
-	mmc->f_min = mxc_get_clock(MXC_ESDHC_CLK) >> 7;
-	mmc->f_max = mxc_get_clock(MXC_ESDHC_CLK) >> 1;
 
-	mmc->b_max = 0;
+	mxcmci_cfg.f_min = mxc_get_clock(MXC_ESDHC_CLK) >> 7;
+	mxcmci_cfg.f_max = mxc_get_clock(MXC_ESDHC_CLK) >> 1;
 
-	mmc_register(mmc);
+	host->mmc = mmc_create(&mxcmci_cfg, host);
+	if (host->mmc == NULL)
+		return -1;
 
 	return 0;
 }
diff --git a/drivers/mmc/mxsmmc.c b/drivers/mmc/mxsmmc.c
index 245f9d0c67..2fa4eeef44 100644
--- a/drivers/mmc/mxsmmc.c
+++ b/drivers/mmc/mxsmmc.c
@@ -35,6 +35,7 @@ struct mxsmmc_priv {
 	int			(*mmc_is_wp)(int);
 	int			(*mmc_cd)(int);
 	struct mxs_dma_desc	*desc;
+	struct mmc_config	cfg;	/* mmc configuration */
 };
 
 #define	MXSMMC_MAX_TIMEOUT	10000
@@ -134,7 +135,7 @@ static int mxsmmc_send_cmd_dma(struct mxsmmc_priv *priv, struct mmc_data *data)
 static int
 mxsmmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data)
 {
-	struct mxsmmc_priv *priv = (struct mxsmmc_priv *)mmc->priv;
+	struct mxsmmc_priv *priv = mmc->priv;
 	struct mxs_ssp_regs *ssp_regs = priv->regs;
 	uint32_t reg;
 	int timeout;
@@ -305,7 +306,7 @@ mxsmmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data)
 
 static void mxsmmc_set_ios(struct mmc *mmc)
 {
-	struct mxsmmc_priv *priv = (struct mxsmmc_priv *)mmc->priv;
+	struct mxsmmc_priv *priv = mmc->priv;
 	struct mxs_ssp_regs *ssp_regs = priv->regs;
 
 	/* Set the clock speed */
@@ -334,7 +335,7 @@ static void mxsmmc_set_ios(struct mmc *mmc)
 
 static int mxsmmc_init(struct mmc *mmc)
 {
-	struct mxsmmc_priv *priv = (struct mxsmmc_priv *)mmc->priv;
+	struct mxsmmc_priv *priv = mmc->priv;
 	struct mxs_ssp_regs *ssp_regs = priv->regs;
 
 	/* Reset SSP */
@@ -363,6 +364,12 @@ static int mxsmmc_init(struct mmc *mmc)
 	return 0;
 }
 
+static const struct mmc_ops mxsmmc_ops = {
+	.send_cmd	= mxsmmc_send_cmd,
+	.set_ios	= mxsmmc_set_ios,
+	.init		= mxsmmc_init,
+};
+
 int mxsmmc_initialize(bd_t *bis, int id, int (*wp)(int), int (*cd)(int))
 {
 	struct mmc *mmc = NULL;
@@ -373,20 +380,13 @@ int mxsmmc_initialize(bd_t *bis, int id, int (*wp)(int), int (*cd)(int))
 	if (!mxs_ssp_bus_id_valid(id))
 		return -ENODEV;
 
-	mmc = malloc(sizeof(struct mmc));
-	if (!mmc)
-		return -ENOMEM;
-
 	priv = malloc(sizeof(struct mxsmmc_priv));
-	if (!priv) {
-		free(mmc);
+	if (!priv)
 		return -ENOMEM;
-	}
 
 	priv->desc = mxs_dma_desc_alloc();
 	if (!priv->desc) {
 		free(priv);
-		free(mmc);
 		return -ENOMEM;
 	}
 
@@ -399,17 +399,12 @@ int mxsmmc_initialize(bd_t *bis, int id, int (*wp)(int), int (*cd)(int))
 	priv->id = id;
 	priv->regs = mxs_ssp_regs_by_bus(id);
 
-	sprintf(mmc->name, "MXS MMC");
-	mmc->send_cmd = mxsmmc_send_cmd;
-	mmc->set_ios = mxsmmc_set_ios;
-	mmc->init = mxsmmc_init;
-	mmc->getcd = NULL;
-	mmc->getwp = NULL;
-	mmc->priv = priv;
+	priv->cfg.name = "MXS MMC";
+	priv->cfg.ops = &mxsmmc_ops;
 
-	mmc->voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
+	priv->cfg.voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
 
-	mmc->host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT |
+	priv->cfg.host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT |
 			 MMC_MODE_HS_52MHz | MMC_MODE_HS |
 			 MMC_MODE_HC;
 
@@ -419,10 +414,15 @@ int mxsmmc_initialize(bd_t *bis, int id, int (*wp)(int), int (*cd)(int))
 	 * CLOCK_DIVIDE has to be an even value from 2 to 254, and
 	 * CLOCK_RATE could be any integer from 0 to 255.
 	 */
-	mmc->f_min = 400000;
-	mmc->f_max = mxc_get_clock(MXC_SSP0_CLK + mxsmmc_clk_id) * 1000 / 2;
-	mmc->b_max = 0x20;
+	priv->cfg.f_min = 400000;
+	priv->cfg.f_max = mxc_get_clock(MXC_SSP0_CLK + mxsmmc_clk_id) * 1000 / 2;
+	priv->cfg.b_max = 0x20;
 
-	mmc_register(mmc);
+	mmc = mmc_create(&priv->cfg, priv);
+	if (mmc == NULL) {
+		mxs_dma_desc_free(priv->desc);
+		free(priv);
+		return -ENOMEM;
+	}
 	return 0;
 }
diff --git a/drivers/mmc/omap_hsmmc.c b/drivers/mmc/omap_hsmmc.c
index d3a8b5303d..17cbb0983d 100644
--- a/drivers/mmc/omap_hsmmc.c
+++ b/drivers/mmc/omap_hsmmc.c
@@ -24,6 +24,7 @@
 
 #include <config.h>
 #include <common.h>
+#include <malloc.h>
 #include <mmc.h>
 #include <part.h>
 #include <i2c.h>
@@ -35,14 +36,25 @@
 #include <asm/arch/mmc_host_def.h>
 #include <asm/arch/sys_proto.h>
 
+/* simplify defines to OMAP_HSMMC_USE_GPIO */
+#if (defined(CONFIG_OMAP_GPIO) && !defined(CONFIG_SPL_BUILD)) || \
+	(defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_GPIO_SUPPORT))
+#define OMAP_HSMMC_USE_GPIO
+#else
+#undef OMAP_HSMMC_USE_GPIO
+#endif
+
 /* common definitions for all OMAPs */
 #define SYSCTL_SRC	(1 << 25)
 #define SYSCTL_SRD	(1 << 26)
 
 struct omap_hsmmc_data {
 	struct hsmmc *base_addr;
+	struct mmc_config cfg;
+#ifdef OMAP_HSMMC_USE_GPIO
 	int cd_gpio;
 	int wp_gpio;
+#endif
 };
 
 /* If we fail after 1 second wait, something is really bad */
@@ -51,11 +63,8 @@ struct omap_hsmmc_data {
 static int mmc_read_data(struct hsmmc *mmc_base, char *buf, unsigned int size);
 static int mmc_write_data(struct hsmmc *mmc_base, const char *buf,
 			unsigned int siz);
-static struct mmc hsmmc_dev[3];
-static struct omap_hsmmc_data hsmmc_dev_data[3];
 
-#if (defined(CONFIG_OMAP_GPIO) && !defined(CONFIG_SPL_BUILD)) || \
-	(defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_GPIO_SUPPORT))
+#ifdef OMAP_HSMMC_USE_GPIO
 static int omap_mmc_setup_gpio_in(int gpio, const char *label)
 {
 	if (!gpio_is_valid(gpio))
@@ -69,26 +78,6 @@ static int omap_mmc_setup_gpio_in(int gpio, const char *label)
 
 	return gpio;
 }
-
-static int omap_mmc_getcd(struct mmc *mmc)
-{
-	int cd_gpio = ((struct omap_hsmmc_data *)mmc->priv)->cd_gpio;
-	return gpio_get_value(cd_gpio);
-}
-
-static int omap_mmc_getwp(struct mmc *mmc)
-{
-	int wp_gpio = ((struct omap_hsmmc_data *)mmc->priv)->wp_gpio;
-	return gpio_get_value(wp_gpio);
-}
-#else
-static inline int omap_mmc_setup_gpio_in(int gpio, const char *label)
-{
-	return -1;
-}
-
-#define omap_mmc_getcd NULL
-#define omap_mmc_getwp NULL
 #endif
 
 #if defined(CONFIG_OMAP44XX) && defined(CONFIG_TWL6030_POWER)
@@ -158,7 +147,7 @@ unsigned char mmc_board_init(struct mmc *mmc)
 		&t2_base->devconf1);
 
 	/* Change from default of 52MHz to 26MHz if necessary */
-	if (!(mmc->host_caps & MMC_MODE_HS_52MHz))
+	if (!(mmc->cfg->host_caps & MMC_MODE_HS_52MHz))
 		writel(readl(&t2_base->ctl_prog_io1) & ~CTLPROGIO1SPEEDCTRL,
 			&t2_base->ctl_prog_io1);
 
@@ -213,7 +202,7 @@ void mmc_init_stream(struct hsmmc *mmc_base)
 }
 
 
-static int mmc_init_setup(struct mmc *mmc)
+static int omap_hsmmc_init_setup(struct mmc *mmc)
 {
 	struct hsmmc *mmc_base;
 	unsigned int reg_val;
@@ -322,7 +311,7 @@ static void mmc_reset_controller_fsm(struct hsmmc *mmc_base, u32 bit)
 	}
 }
 
-static int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
+static int omap_hsmmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
 			struct mmc_data *data)
 {
 	struct hsmmc *mmc_base;
@@ -552,7 +541,7 @@ static int mmc_write_data(struct hsmmc *mmc_base, const char *buf,
 	return 0;
 }
 
-static void mmc_set_ios(struct mmc *mmc)
+static void omap_hsmmc_set_ios(struct mmc *mmc)
 {
 	struct hsmmc *mmc_base;
 	unsigned int dsor = 0;
@@ -606,19 +595,58 @@ static void mmc_set_ios(struct mmc *mmc)
 	writel(readl(&mmc_base->sysctl) | CEN_ENABLE, &mmc_base->sysctl);
 }
 
+#ifdef OMAP_HSMMC_USE_GPIO
+static int omap_hsmmc_getcd(struct mmc *mmc)
+{
+	struct omap_hsmmc_data *priv_data = mmc->priv;
+	int cd_gpio;
+
+	/* if no CD return as 1 */
+	cd_gpio = priv_data->cd_gpio;
+	if (cd_gpio < 0)
+		return 1;
+
+	return gpio_get_value(cd_gpio);
+}
+
+static int omap_hsmmc_getwp(struct mmc *mmc)
+{
+	struct omap_hsmmc_data *priv_data = mmc->priv;
+	int wp_gpio;
+
+	/* if no WP return as 0 */
+	wp_gpio = priv_data->wp_gpio;
+	if (wp_gpio < 0)
+		return 0;
+
+	return gpio_get_value(wp_gpio);
+}
+#endif
+
+static const struct mmc_ops omap_hsmmc_ops = {
+	.send_cmd	= omap_hsmmc_send_cmd,
+	.set_ios	= omap_hsmmc_set_ios,
+	.init		= omap_hsmmc_init_setup,
+#ifdef OMAP_HSMMC_USE_GPIO
+	.getcd		= omap_hsmmc_getcd,
+	.getwp		= omap_hsmmc_getwp,
+#endif
+};
+
 int omap_mmc_init(int dev_index, uint host_caps_mask, uint f_max, int cd_gpio,
 		int wp_gpio)
 {
-	struct mmc *mmc = &hsmmc_dev[dev_index];
-	struct omap_hsmmc_data *priv_data = &hsmmc_dev_data[dev_index];
-	uint host_caps_val = MMC_MODE_4BIT | MMC_MODE_HS_52MHz | MMC_MODE_HS |
-			     MMC_MODE_HC;
+	struct mmc *mmc;
+	struct omap_hsmmc_data *priv_data;
+	struct mmc_config *cfg;
+	uint host_caps_val;
 
-	sprintf(mmc->name, "OMAP SD/MMC");
-	mmc->send_cmd = mmc_send_cmd;
-	mmc->set_ios = mmc_set_ios;
-	mmc->init = mmc_init_setup;
-	mmc->priv = priv_data;
+	priv_data = malloc(sizeof(*priv_data));
+	if (priv_data == NULL)
+		return -1;
+
+	host_caps_val = MMC_MODE_4BIT | MMC_MODE_HS_52MHz | MMC_MODE_HS |
+			     MMC_MODE_HC;
 
 	switch (dev_index) {
 	case 0:
@@ -647,42 +675,46 @@ int omap_mmc_init(int dev_index, uint host_caps_mask, uint f_max, int cd_gpio,
 		priv_data->base_addr = (struct hsmmc *)OMAP_HSMMC1_BASE;
 		return 1;
 	}
+#ifdef OMAP_HSMMC_USE_GPIO
+	/* on error gpio values are set to -1, which is what we want */
 	priv_data->cd_gpio = omap_mmc_setup_gpio_in(cd_gpio, "mmc_cd");
-	if (priv_data->cd_gpio != -1)
-		mmc->getcd = omap_mmc_getcd;
-
 	priv_data->wp_gpio = omap_mmc_setup_gpio_in(wp_gpio, "mmc_wp");
-	if (priv_data->wp_gpio != -1)
-		mmc->getwp = omap_mmc_getwp;
+#endif
+
+	cfg = &priv_data->cfg;
 
-	mmc->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
-	mmc->host_caps = host_caps_val & ~host_caps_mask;
+	cfg->name = "OMAP SD/MMC";
+	cfg->ops = &omap_hsmmc_ops;
 
-	mmc->f_min = 400000;
+	cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
+	cfg->host_caps = host_caps_val & ~host_caps_mask;
+
+	cfg->f_min = 400000;
 
 	if (f_max != 0)
-		mmc->f_max = f_max;
+		cfg->f_max = f_max;
 	else {
-		if (mmc->host_caps & MMC_MODE_HS) {
-			if (mmc->host_caps & MMC_MODE_HS_52MHz)
-				mmc->f_max = 52000000;
+		if (cfg->host_caps & MMC_MODE_HS) {
+			if (cfg->host_caps & MMC_MODE_HS_52MHz)
+				cfg->f_max = 52000000;
 			else
-				mmc->f_max = 26000000;
+				cfg->f_max = 26000000;
 		} else
-			mmc->f_max = 20000000;
+			cfg->f_max = 20000000;
 	}
 
-	mmc->b_max = 0;
+	cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
 
 #if defined(CONFIG_OMAP34XX)
 	/*
 	 * Silicon revs 2.1 and older do not support multiblock transfers.
 	 */
 	if ((get_cpu_family() == CPU_OMAP34XX) && (get_cpu_rev() <= CPU_3XX_ES21))
-		mmc->b_max = 1;
+		cfg->b_max = 1;
 #endif
-
-	mmc_register(mmc);
+	mmc = mmc_create(cfg, priv_data);
+	if (mmc == NULL)
+		return -1;
 
 	return 0;
 }
diff --git a/drivers/mmc/pxa_mmc.h b/drivers/mmc/pxa_mmc.h
deleted file mode 100644
index 6fa42686e6..0000000000
--- a/drivers/mmc/pxa_mmc.h
+++ /dev/null
@@ -1,138 +0,0 @@
-/*
- *  linux/drivers/mmc/mmc_pxa.h
- *
- *  Author: Vladimir Shebordaev, Igor Oblakov
- *  Copyright:  MontaVista Software Inc.
- *
- *  $Id: mmc_pxa.h,v 0.3.1.6 2002/09/25 19:25:48 ted Exp ted $
- *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License version 2 as
- *  published by the Free Software Foundation.
- */
-#ifndef __MMC_PXA_P_H__
-#define __MMC_PXA_P_H__
-
-/* PXA-250 MMC controller registers */
-
-/* MMC_STRPCL */
-#define MMC_STRPCL_STOP_CLK		(0x0001UL)
-#define MMC_STRPCL_START_CLK		(0x0002UL)
-
-/* MMC_STAT */
-#define MMC_STAT_END_CMD_RES		(0x0001UL << 13)
-#define MMC_STAT_PRG_DONE		(0x0001UL << 12)
-#define MMC_STAT_DATA_TRAN_DONE		(0x0001UL << 11)
-#define MMC_STAT_CLK_EN			(0x0001UL << 8)
-#define MMC_STAT_RECV_FIFO_FULL		(0x0001UL << 7)
-#define MMC_STAT_XMIT_FIFO_EMPTY	(0x0001UL << 6)
-#define MMC_STAT_RES_CRC_ERROR		(0x0001UL << 5)
-#define MMC_STAT_SPI_READ_ERROR_TOKEN   (0x0001UL << 4)
-#define MMC_STAT_CRC_READ_ERROR		(0x0001UL << 3)
-#define MMC_STAT_CRC_WRITE_ERROR	(0x0001UL << 2)
-#define MMC_STAT_TIME_OUT_RESPONSE	(0x0001UL << 1)
-#define MMC_STAT_READ_TIME_OUT		(0x0001UL)
-
-#define MMC_STAT_ERRORS (MMC_STAT_RES_CRC_ERROR|MMC_STAT_SPI_READ_ERROR_TOKEN\
-	|MMC_STAT_CRC_READ_ERROR|MMC_STAT_TIME_OUT_RESPONSE\
-	|MMC_STAT_READ_TIME_OUT|MMC_STAT_CRC_WRITE_ERROR)
-
-/* MMC_CLKRT */
-#define MMC_CLKRT_20MHZ			(0x0000UL)
-#define MMC_CLKRT_10MHZ			(0x0001UL)
-#define MMC_CLKRT_5MHZ			(0x0002UL)
-#define MMC_CLKRT_2_5MHZ		(0x0003UL)
-#define MMC_CLKRT_1_25MHZ		(0x0004UL)
-#define MMC_CLKRT_0_625MHZ		(0x0005UL)
-#define MMC_CLKRT_0_3125MHZ		(0x0006UL)
-
-/* MMC_SPI */
-#define MMC_SPI_DISABLE			(0x00UL)
-#define MMC_SPI_EN			(0x01UL)
-#define MMC_SPI_CS_EN			(0x01UL << 2)
-#define MMC_SPI_CS_ADDRESS		(0x01UL << 3)
-#define MMC_SPI_CRC_ON			(0x01UL << 1)
-
-/* MMC_CMDAT */
-#define MMC_CMDAT_SD_4DAT		(0x0001UL << 8)
-#define MMC_CMDAT_MMC_DMA_EN		(0x0001UL << 7)
-#define MMC_CMDAT_INIT			(0x0001UL << 6)
-#define MMC_CMDAT_BUSY			(0x0001UL << 5)
-#define MMC_CMDAT_BCR			(0x0003UL << 5)
-#define MMC_CMDAT_STREAM		(0x0001UL << 4)
-#define MMC_CMDAT_BLOCK			(0x0000UL << 4)
-#define MMC_CMDAT_WRITE			(0x0001UL << 3)
-#define MMC_CMDAT_READ			(0x0000UL << 3)
-#define MMC_CMDAT_DATA_EN		(0x0001UL << 2)
-#define MMC_CMDAT_R0			(0)
-#define MMC_CMDAT_R1			(0x0001UL)
-#define MMC_CMDAT_R2			(0x0002UL)
-#define MMC_CMDAT_R3			(0x0003UL)
-
-/* MMC_RESTO */
-#define MMC_RES_TO_MAX			(0x007fUL) /* [6:0] */
-
-/* MMC_RDTO */
-#define MMC_READ_TO_MAX			(0x0ffffUL) /* [15:0] */
-
-/* MMC_BLKLEN */
-#define MMC_BLK_LEN_MAX			(0x03ffUL) /* [9:0] */
-
-/* MMC_PRTBUF */
-#define MMC_PRTBUF_BUF_PART_FULL	(0x01UL)
-#define MMC_PRTBUF_BUF_FULL		(0x00UL    )
-
-/* MMC_I_MASK */
-#define MMC_I_MASK_TXFIFO_WR_REQ	(0x01UL << 6)
-#define MMC_I_MASK_RXFIFO_RD_REQ	(0x01UL << 5)
-#define MMC_I_MASK_CLK_IS_OFF		(0x01UL << 4)
-#define MMC_I_MASK_STOP_CMD		(0x01UL << 3)
-#define MMC_I_MASK_END_CMD_RES		(0x01UL << 2)
-#define MMC_I_MASK_PRG_DONE		(0x01UL << 1)
-#define MMC_I_MASK_DATA_TRAN_DONE       (0x01UL)
-#define MMC_I_MASK_ALL			(0x07fUL)
-
-
-/* MMC_I_REG */
-#define MMC_I_REG_TXFIFO_WR_REQ		(0x01UL << 6)
-#define MMC_I_REG_RXFIFO_RD_REQ		(0x01UL << 5)
-#define MMC_I_REG_CLK_IS_OFF		(0x01UL << 4)
-#define MMC_I_REG_STOP_CMD		(0x01UL << 3)
-#define MMC_I_REG_END_CMD_RES		(0x01UL << 2)
-#define MMC_I_REG_PRG_DONE		(0x01UL << 1)
-#define MMC_I_REG_DATA_TRAN_DONE	(0x01UL)
-#define MMC_I_REG_ALL			(0x007fUL)
-
-/* MMC_CMD */
-#define MMC_CMD_INDEX_MAX		(0x006fUL)  /* [5:0] */
-#define CMD(x)  (x)
-
-#define MMC_DEFAULT_RCA			1
-
-#define MMC_BLOCK_SIZE			512
-#define MMC_MAX_BLOCK_SIZE		512
-
-#define MMC_R1_IDLE_STATE		0x01
-#define MMC_R1_ERASE_STATE		0x02
-#define MMC_R1_ILLEGAL_CMD		0x04
-#define MMC_R1_COM_CRC_ERR		0x08
-#define MMC_R1_ERASE_SEQ_ERR		0x01
-#define MMC_R1_ADDR_ERR			0x02
-#define MMC_R1_PARAM_ERR		0x04
-
-#define MMC_R1B_WP_ERASE_SKIP		0x0002
-#define MMC_R1B_ERR			0x0004
-#define MMC_R1B_CC_ERR			0x0008
-#define MMC_R1B_CARD_ECC_ERR		0x0010
-#define MMC_R1B_WP_VIOLATION		0x0020
-#define MMC_R1B_ERASE_PARAM		0x0040
-#define MMC_R1B_OOR			0x0080
-#define MMC_R1B_IDLE_STATE		0x0100
-#define MMC_R1B_ERASE_RESET		0x0200
-#define MMC_R1B_ILLEGAL_CMD		0x0400
-#define MMC_R1B_COM_CRC_ERR		0x0800
-#define MMC_R1B_ERASE_SEQ_ERR		0x1000
-#define MMC_R1B_ADDR_ERR		0x2000
-#define MMC_R1B_PARAM_ERR		0x4000
-
-#endif /* __MMC_PXA_P_H__ */
diff --git a/drivers/mmc/pxa_mmc_gen.c b/drivers/mmc/pxa_mmc_gen.c
index 29f3eaf30b..1f297571e5 100644
--- a/drivers/mmc/pxa_mmc_gen.c
+++ b/drivers/mmc/pxa_mmc_gen.c
@@ -52,7 +52,7 @@ struct pxa_mmc_priv {
 /* Wait for bit to be set */
 static int pxa_mmc_wait(struct mmc *mmc, uint32_t mask)
 {
-	struct pxa_mmc_priv *priv = (struct pxa_mmc_priv *)mmc->priv;
+	struct pxa_mmc_priv *priv = mmc->priv;
 	struct pxa_mmc_regs *regs = priv->regs;
 	unsigned int timeout = PXA_MMC_TIMEOUT;
 
@@ -71,7 +71,7 @@ static int pxa_mmc_wait(struct mmc *mmc, uint32_t mask)
 
 static int pxa_mmc_stop_clock(struct mmc *mmc)
 {
-	struct pxa_mmc_priv *priv = (struct pxa_mmc_priv *)mmc->priv;
+	struct pxa_mmc_priv *priv = mmc->priv;
 	struct pxa_mmc_regs *regs = priv->regs;
 	unsigned int timeout = PXA_MMC_TIMEOUT;
 
@@ -100,7 +100,7 @@ static int pxa_mmc_stop_clock(struct mmc *mmc)
 static int pxa_mmc_start_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
 				uint32_t cmdat)
 {
-	struct pxa_mmc_priv *priv = (struct pxa_mmc_priv *)mmc->priv;
+	struct pxa_mmc_priv *priv = mmc->priv;
 	struct pxa_mmc_regs *regs = priv->regs;
 	int ret;
 
@@ -143,7 +143,7 @@ static int pxa_mmc_start_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
 
 static int pxa_mmc_cmd_done(struct mmc *mmc, struct mmc_cmd *cmd)
 {
-	struct pxa_mmc_priv *priv = (struct pxa_mmc_priv *)mmc->priv;
+	struct pxa_mmc_priv *priv = mmc->priv;
 	struct pxa_mmc_regs *regs = priv->regs;
 	uint32_t a, b, c;
 	int i;
@@ -185,7 +185,7 @@ static int pxa_mmc_cmd_done(struct mmc *mmc, struct mmc_cmd *cmd)
 
 static int pxa_mmc_do_read_xfer(struct mmc *mmc, struct mmc_data *data)
 {
-	struct pxa_mmc_priv *priv = (struct pxa_mmc_priv *)mmc->priv;
+	struct pxa_mmc_priv *priv = mmc->priv;
 	struct pxa_mmc_regs *regs = priv->regs;
 	uint32_t len;
 	uint32_t *buf = (uint32_t *)data->dest;
@@ -221,7 +221,7 @@ static int pxa_mmc_do_read_xfer(struct mmc *mmc, struct mmc_data *data)
 
 static int pxa_mmc_do_write_xfer(struct mmc *mmc, struct mmc_data *data)
 {
-	struct pxa_mmc_priv *priv = (struct pxa_mmc_priv *)mmc->priv;
+	struct pxa_mmc_priv *priv = mmc->priv;
 	struct pxa_mmc_regs *regs = priv->regs;
 	uint32_t len;
 	uint32_t *buf = (uint32_t *)data->src;
@@ -264,7 +264,7 @@ static int pxa_mmc_do_write_xfer(struct mmc *mmc, struct mmc_data *data)
 static int pxa_mmc_request(struct mmc *mmc, struct mmc_cmd *cmd,
 				struct mmc_data *data)
 {
-	struct pxa_mmc_priv *priv = (struct pxa_mmc_priv *)mmc->priv;
+	struct pxa_mmc_priv *priv = mmc->priv;
 	struct pxa_mmc_regs *regs = priv->regs;
 	uint32_t cmdat = 0;
 	int ret;
@@ -317,7 +317,7 @@ static int pxa_mmc_request(struct mmc *mmc, struct mmc_cmd *cmd,
 
 static void pxa_mmc_set_ios(struct mmc *mmc)
 {
-	struct pxa_mmc_priv *priv = (struct pxa_mmc_priv *)mmc->priv;
+	struct pxa_mmc_priv *priv = mmc->priv;
 	struct pxa_mmc_regs *regs = priv->regs;
 	uint32_t tmp;
 	uint32_t pxa_mmc_clock;
@@ -335,7 +335,7 @@ static void pxa_mmc_set_ios(struct mmc *mmc)
 
 	/* Set clock to the card the usual way. */
 	pxa_mmc_clock = 0;
-	tmp = mmc->f_max / mmc->clock;
+	tmp = mmc->cfg->f_max / mmc->clock;
 	tmp += tmp % 2;
 
 	while (tmp > 1) {
@@ -348,7 +348,7 @@ static void pxa_mmc_set_ios(struct mmc *mmc)
 
 static int pxa_mmc_init(struct mmc *mmc)
 {
-	struct pxa_mmc_priv *priv = (struct pxa_mmc_priv *)mmc->priv;
+	struct pxa_mmc_priv *priv = mmc->priv;
 	struct pxa_mmc_regs *regs = priv->regs;
 
 	/* Make sure the clock are stopped */
@@ -366,6 +366,22 @@ static int pxa_mmc_init(struct mmc *mmc)
 	return 0;
 }
 
+static const struct mmc_ops pxa_mmc_ops = {
+	.send_cmd	= pxa_mmc_request,
+	.set_ios	= pxa_mmc_set_ios,
+	.init		= pxa_mmc_init,
+};
+
+static struct mmc_config pxa_mmc_cfg = {
+	.name		= "PXA MMC",
+	.ops		= &pxa_mmc_ops,
+	.voltages	= MMC_VDD_32_33 | MMC_VDD_33_34,
+	.f_max		= PXAMMC_MAX_SPEED,
+	.f_min		= PXAMMC_MIN_SPEED,
+	.host_caps	= PXAMMC_HOST_CAPS,
+	.b_max		= CONFIG_SYS_MMC_MAX_BLK_COUNT,
+};
+
 int pxa_mmc_register(int card_index)
 {
 	struct mmc *mmc;
@@ -373,13 +389,11 @@ int pxa_mmc_register(int card_index)
 	uint32_t reg;
 	int ret = -ENOMEM;
 
-	mmc = malloc(sizeof(struct mmc));
-	if (!mmc)
-		goto err0;
-
 	priv = malloc(sizeof(struct pxa_mmc_priv));
 	if (!priv)
-		goto err1;
+		goto err0;
+
+	memset(priv, 0, sizeof(*priv));
 
 	switch (card_index) {
 	case 0:
@@ -389,26 +403,12 @@ int pxa_mmc_register(int card_index)
 		priv->regs = (struct pxa_mmc_regs *)MMC1_BASE;
 		break;
 	default:
+		ret = -EINVAL;
 		printf("PXA MMC: Invalid MMC controller ID (card_index = %d)\n",
 			card_index);
-		goto err2;
+		goto err1;
 	}
 
-	mmc->priv = priv;
-
-	sprintf(mmc->name, "PXA MMC");
-	mmc->send_cmd	= pxa_mmc_request;
-	mmc->set_ios	= pxa_mmc_set_ios;
-	mmc->init	= pxa_mmc_init;
-	mmc->getcd	= NULL;
-
-	mmc->voltages	= MMC_VDD_32_33 | MMC_VDD_33_34;
-	mmc->f_max	= PXAMMC_MAX_SPEED;
-	mmc->f_min	= PXAMMC_MIN_SPEED;
-	mmc->host_caps	= PXAMMC_HOST_CAPS;
-
-	mmc->b_max = 0;
-
 #ifndef	CONFIG_CPU_MONAHANS	/* PXA2xx */
 	reg = readl(CKEN);
 	reg |= CKEN12_MMC;
@@ -419,14 +419,14 @@ int pxa_mmc_register(int card_index)
 	writel(reg, CKENA);
 #endif
 
-	mmc_register(mmc);
+	mmc = mmc_create(&pxa_mmc_cfg, priv);
+	if (mmc == NULL)
+		goto err1;
 
 	return 0;
 
-err2:
-	free(priv);
 err1:
-	free(mmc);
+	free(priv);
 err0:
 	return ret;
 }
diff --git a/drivers/mmc/s5p_sdhci.c b/drivers/mmc/s5p_sdhci.c
index 40ff8739bf..ccae4ccae1 100644
--- a/drivers/mmc/s5p_sdhci.c
+++ b/drivers/mmc/s5p_sdhci.c
@@ -8,8 +8,15 @@
 #include <common.h>
 #include <malloc.h>
 #include <sdhci.h>
+#include <fdtdec.h>
+#include <libfdt.h>
+#include <asm/gpio.h>
 #include <asm/arch/mmc.h>
 #include <asm/arch/clk.h>
+#include <errno.h>
+#ifdef CONFIG_OF_CONTROL
+#include <asm/arch/pinmux.h>
+#endif
 
 static char *S5P_NAME = "SAMSUNG SDHCI";
 static void s5p_sdhci_set_control_reg(struct sdhci_host *host)
@@ -86,3 +93,125 @@ int s5p_sdhci_init(u32 regbase, int index, int bus_width)
 
 	return add_sdhci(host, 52000000, 400000);
 }
+
+#ifdef CONFIG_OF_CONTROL
+struct sdhci_host sdhci_host[SDHCI_MAX_HOSTS];
+
+static int do_sdhci_init(struct sdhci_host *host)
+{
+	int dev_id, flag;
+	int err = 0;
+
+	flag = host->bus_width == 8 ? PINMUX_FLAG_8BIT_MODE : PINMUX_FLAG_NONE;
+	dev_id = host->index + PERIPH_ID_SDMMC0;
+
+	if (fdt_gpio_isvalid(&host->pwr_gpio)) {
+		gpio_direction_output(host->pwr_gpio.gpio, 1);
+		err = exynos_pinmux_config(dev_id, flag);
+		if (err) {
+			debug("MMC not configured\n");
+			return err;
+		}
+	}
+
+	if (fdt_gpio_isvalid(&host->cd_gpio)) {
+		gpio_direction_output(host->cd_gpio.gpio, 0xf);
+		if (gpio_get_value(host->cd_gpio.gpio))
+			return -ENODEV;
+
+		err = exynos_pinmux_config(dev_id, flag);
+		if (err) {
+			printf("external SD not configured\n");
+			return err;
+		}
+	}
+
+	host->name = S5P_NAME;
+
+	host->quirks = SDHCI_QUIRK_NO_HISPD_BIT | SDHCI_QUIRK_BROKEN_VOLTAGE |
+		SDHCI_QUIRK_BROKEN_R1B | SDHCI_QUIRK_32BIT_DMA_ADDR |
+		SDHCI_QUIRK_WAIT_SEND_CMD;
+	host->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
+	host->version = sdhci_readw(host, SDHCI_HOST_VERSION);
+
+	host->set_control_reg = &s5p_sdhci_set_control_reg;
+	host->set_clock = set_mmc_clk;
+
+	host->host_caps = MMC_MODE_HC;
+
+	return add_sdhci(host, 52000000, 400000);
+}
+
+static int sdhci_get_config(const void *blob, int node, struct sdhci_host *host)
+{
+	int bus_width, dev_id;
+	unsigned int base;
+
+	/* Get device id */
+	dev_id = pinmux_decode_periph_id(blob, node);
+	if (dev_id < PERIPH_ID_SDMMC0 && dev_id > PERIPH_ID_SDMMC3) {
+		debug("MMC: Can't get device id\n");
+		return -1;
+	}
+	host->index = dev_id - PERIPH_ID_SDMMC0;
+
+	/* Get bus width */
+	bus_width = fdtdec_get_int(blob, node, "samsung,bus-width", 0);
+	if (bus_width <= 0) {
+		debug("MMC: Can't get bus-width\n");
+		return -1;
+	}
+	host->bus_width = bus_width;
+
+	/* Get the base address from the device node */
+	base = fdtdec_get_addr(blob, node, "reg");
+	if (!base) {
+		debug("MMC: Can't get base address\n");
+		return -1;
+	}
+	host->ioaddr = (void *)base;
+
+	fdtdec_decode_gpio(blob, node, "pwr-gpios", &host->pwr_gpio);
+	fdtdec_decode_gpio(blob, node, "cd-gpios", &host->cd_gpio);
+
+	return 0;
+}
+
+static int process_nodes(const void *blob, int node_list[], int count)
+{
+	struct sdhci_host *host;
+	int i, node;
+
+	debug("%s: count = %d\n", __func__, count);
+
+	/* build sdhci_host[] for each controller */
+	for (i = 0; i < count; i++) {
+		node = node_list[i];
+		if (node <= 0)
+			continue;
+
+		host = &sdhci_host[i];
+
+		if (sdhci_get_config(blob, node, host)) {
+			printf("%s: failed to decode dev %d\n",	__func__, i);
+			return -1;
+		}
+		do_sdhci_init(host);
+	}
+	return 0;
+}
+
+int exynos_mmc_init(const void *blob)
+{
+	int count;
+	int node_list[SDHCI_MAX_HOSTS];
+
+	count = fdtdec_find_aliases_for_id(blob, "mmc",
+			COMPAT_SAMSUNG_EXYNOS_MMC, node_list,
+			SDHCI_MAX_HOSTS);
+
+	process_nodes(blob, node_list, count);
+
+	return 1;
+}
+#endif
diff --git a/drivers/mmc/sdhci.c b/drivers/mmc/sdhci.c
index dfb2eeeb4d..3125d13ba3 100644
--- a/drivers/mmc/sdhci.c
+++ b/drivers/mmc/sdhci.c
@@ -24,7 +24,8 @@ static void sdhci_reset(struct sdhci_host *host, u8 mask)
 	sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET);
 	while (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask) {
 		if (timeout == 0) {
-			printf("Reset 0x%x never completed.\n", (int)mask);
+			printf("%s: Reset 0x%x never completed.\n",
+			       __func__, (int)mask);
 			return;
 		}
 		timeout--;
@@ -79,7 +80,8 @@ static int sdhci_transfer_data(struct sdhci_host *host, struct mmc_data *data,
 	do {
 		stat = sdhci_readl(host, SDHCI_INT_STATUS);
 		if (stat & SDHCI_INT_ERROR) {
-			printf("Error detected in status(0x%X)!\n", stat);
+			printf("%s: Error detected in status(0x%X)!\n",
+			       __func__, stat);
 			return -1;
 		}
 		if (stat & rdy) {
@@ -102,26 +104,40 @@ static int sdhci_transfer_data(struct sdhci_host *host, struct mmc_data *data,
 		if (timeout-- > 0)
 			udelay(10);
 		else {
-			printf("Transfer data timeout\n");
+			printf("%s: Transfer data timeout\n", __func__);
 			return -1;
 		}
 	} while (!(stat & SDHCI_INT_DATA_END));
 	return 0;
 }
 
+/*
+ * No command will be sent by driver if card is busy, so driver must wait
+ * for card ready state.
+ * Every time when card is busy after timeout then (last) timeout value will be
+ * increased twice but only if it doesn't exceed global defined maximum.
+ * Each function call will use last timeout value. Max timeout can be redefined
+ * in board config file.
+ */
+#ifndef CONFIG_SDHCI_CMD_MAX_TIMEOUT
+#define CONFIG_SDHCI_CMD_MAX_TIMEOUT		3200
+#endif
+#define CONFIG_SDHCI_CMD_DEFAULT_TIMEOUT	100
+
 int sdhci_send_command(struct mmc *mmc, struct mmc_cmd *cmd,
 		       struct mmc_data *data)
 {
-	struct sdhci_host *host = (struct sdhci_host *)mmc->priv;
+	struct sdhci_host *host = mmc->priv;
 	unsigned int stat = 0;
 	int ret = 0;
 	int trans_bytes = 0, is_aligned = 1;
 	u32 mask, flags, mode;
-	unsigned int timeout, start_addr = 0;
+	unsigned int time = 0, start_addr = 0;
 	unsigned int retry = 10000;
+	int mmc_dev = mmc->block_dev.dev;
 
-	/* Wait max 10 ms */
-	timeout = 10;
+	/* Timeout unit - ms */
+	static unsigned int cmd_timeout = CONFIG_SDHCI_CMD_DEFAULT_TIMEOUT;
 
 	sdhci_writel(host, SDHCI_INT_ALL_MASK, SDHCI_INT_STATUS);
 	mask = SDHCI_CMD_INHIBIT | SDHCI_DATA_INHIBIT;
@@ -132,11 +148,18 @@ int sdhci_send_command(struct mmc *mmc, struct mmc_cmd *cmd,
 		mask &= ~SDHCI_DATA_INHIBIT;
 
 	while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
-		if (timeout == 0) {
-			printf("Controller never released inhibit bit(s).\n");
-			return COMM_ERR;
+		if (time >= cmd_timeout) {
+			printf("%s: MMC: %d busy ", __func__, mmc_dev);
+			if (2 * cmd_timeout <= CONFIG_SDHCI_CMD_MAX_TIMEOUT) {
+				cmd_timeout += cmd_timeout;
+				printf("timeout increasing to: %u ms.\n",
+				       cmd_timeout);
+			} else {
+				puts("timeout.\n");
+				return COMM_ERR;
+			}
 		}
-		timeout--;
+		time++;
 		udelay(1000);
 	}
 
@@ -158,7 +181,7 @@ int sdhci_send_command(struct mmc *mmc, struct mmc_cmd *cmd,
 	if (data)
 		flags |= SDHCI_CMD_DATA;
 
-	/*Set Transfer mode regarding to data flag*/
+	/* Set Transfer mode regarding to data flag */
 	if (data != 0) {
 		sdhci_writeb(host, 0xe, SDHCI_TIMEOUT_CONTROL);
 		mode = SDHCI_TRNS_BLK_CNT_EN;
@@ -209,7 +232,7 @@ int sdhci_send_command(struct mmc *mmc, struct mmc_cmd *cmd,
 		if (host->quirks & SDHCI_QUIRK_BROKEN_R1B)
 			return 0;
 		else {
-			printf("Timeout for status update!\n");
+			printf("%s: Timeout for status update!\n", __func__);
 			return TIMEOUT;
 		}
 	}
@@ -245,7 +268,7 @@ int sdhci_send_command(struct mmc *mmc, struct mmc_cmd *cmd,
 
 static int sdhci_set_clock(struct mmc *mmc, unsigned int clock)
 {
-	struct sdhci_host *host = (struct sdhci_host *)mmc->priv;
+	struct sdhci_host *host = mmc->priv;
 	unsigned int div, clk, timeout;
 
 	sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
@@ -255,18 +278,18 @@ static int sdhci_set_clock(struct mmc *mmc, unsigned int clock)
 
 	if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) {
 		/* Version 3.00 divisors must be a multiple of 2. */
-		if (mmc->f_max <= clock)
+		if (mmc->cfg->f_max <= clock)
 			div = 1;
 		else {
 			for (div = 2; div < SDHCI_MAX_DIV_SPEC_300; div += 2) {
-				if ((mmc->f_max / div) <= clock)
+				if ((mmc->cfg->f_max / div) <= clock)
 					break;
 			}
 		}
 	} else {
 		/* Version 2.00 divisors must be a power of 2. */
 		for (div = 1; div < SDHCI_MAX_DIV_SPEC_200; div *= 2) {
-			if ((mmc->f_max / div) <= clock)
+			if ((mmc->cfg->f_max / div) <= clock)
 				break;
 		}
 	}
@@ -286,7 +309,8 @@ static int sdhci_set_clock(struct mmc *mmc, unsigned int clock)
 	while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
 		& SDHCI_CLOCK_INT_STABLE)) {
 		if (timeout == 0) {
-			printf("Internal clock never stabilised.\n");
+			printf("%s: Internal clock never stabilised.\n",
+			       __func__);
 			return -1;
 		}
 		timeout--;
@@ -334,7 +358,7 @@ static void sdhci_set_power(struct sdhci_host *host, unsigned short power)
 void sdhci_set_ios(struct mmc *mmc)
 {
 	u32 ctrl;
-	struct sdhci_host *host = (struct sdhci_host *)mmc->priv;
+	struct sdhci_host *host = mmc->priv;
 
 	if (host->set_control_reg)
 		host->set_control_reg(host);
@@ -371,17 +395,18 @@ void sdhci_set_ios(struct mmc *mmc)
 
 int sdhci_init(struct mmc *mmc)
 {
-	struct sdhci_host *host = (struct sdhci_host *)mmc->priv;
+	struct sdhci_host *host = mmc->priv;
 
 	if ((host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) && !aligned_buffer) {
 		aligned_buffer = memalign(8, 512*1024);
 		if (!aligned_buffer) {
-			printf("Aligned buffer alloc failed!!!");
+			printf("%s: Aligned buffer alloc failed!!!\n",
+			       __func__);
 			return -1;
 		}
 	}
 
-	sdhci_set_power(host, fls(mmc->voltages) - 1);
+	sdhci_set_power(host, fls(mmc->cfg->voltages) - 1);
 
 	if (host->quirks & SDHCI_QUIRK_NO_CD) {
 		unsigned int status;
@@ -397,88 +422,92 @@ int sdhci_init(struct mmc *mmc)
 	}
 
 	/* Enable only interrupts served by the SD controller */
-	sdhci_writel(host, SDHCI_INT_DATA_MASK | SDHCI_INT_CMD_MASK
-		     , SDHCI_INT_ENABLE);
+	sdhci_writel(host, SDHCI_INT_DATA_MASK | SDHCI_INT_CMD_MASK,
+		     SDHCI_INT_ENABLE);
 	/* Mask all sdhci interrupt sources */
 	sdhci_writel(host, 0x0, SDHCI_SIGNAL_ENABLE);
 
 	return 0;
 }
 
+
+static const struct mmc_ops sdhci_ops = {
+	.send_cmd	= sdhci_send_command,
+	.set_ios	= sdhci_set_ios,
+	.init		= sdhci_init,
+};
+
 int add_sdhci(struct sdhci_host *host, u32 max_clk, u32 min_clk)
 {
-	struct mmc *mmc;
 	unsigned int caps;
 
-	mmc = malloc(sizeof(struct mmc));
-	if (!mmc) {
-		printf("mmc malloc fail!\n");
-		return -1;
-	}
-
-	mmc->priv = host;
-	host->mmc = mmc;
-
-	sprintf(mmc->name, "%s", host->name);
-	mmc->send_cmd = sdhci_send_command;
-	mmc->set_ios = sdhci_set_ios;
-	mmc->init = sdhci_init;
-	mmc->getcd = NULL;
-	mmc->getwp = NULL;
+	host->cfg.name = host->name;
+	host->cfg.ops = &sdhci_ops;
 
 	caps = sdhci_readl(host, SDHCI_CAPABILITIES);
 #ifdef CONFIG_MMC_SDMA
 	if (!(caps & SDHCI_CAN_DO_SDMA)) {
-		printf("Your controller don't support sdma!!\n");
+		printf("%s: Your controller doesn't support SDMA!!\n",
+		       __func__);
 		return -1;
 	}
 #endif
 
 	if (max_clk)
-		mmc->f_max = max_clk;
+		host->cfg.f_max = max_clk;
 	else {
 		if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300)
-			mmc->f_max = (caps & SDHCI_CLOCK_V3_BASE_MASK)
+			host->cfg.f_max = (caps & SDHCI_CLOCK_V3_BASE_MASK)
 				>> SDHCI_CLOCK_BASE_SHIFT;
 		else
-			mmc->f_max = (caps & SDHCI_CLOCK_BASE_MASK)
+			host->cfg.f_max = (caps & SDHCI_CLOCK_BASE_MASK)
 				>> SDHCI_CLOCK_BASE_SHIFT;
-		mmc->f_max *= 1000000;
+		host->cfg.f_max *= 1000000;
 	}
-	if (mmc->f_max == 0) {
-		printf("Hardware doesn't specify base clock frequency\n");
+	if (host->cfg.f_max == 0) {
+		printf("%s: Hardware doesn't specify base clock frequency\n",
+		       __func__);
 		return -1;
 	}
 	if (min_clk)
-		mmc->f_min = min_clk;
+		host->cfg.f_min = min_clk;
 	else {
 		if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300)
-			mmc->f_min = mmc->f_max / SDHCI_MAX_DIV_SPEC_300;
+			host->cfg.f_min = host->cfg.f_max /
+				SDHCI_MAX_DIV_SPEC_300;
 		else
-			mmc->f_min = mmc->f_max / SDHCI_MAX_DIV_SPEC_200;
+			host->cfg.f_min = host->cfg.f_max /
+				SDHCI_MAX_DIV_SPEC_200;
 	}
 
-	mmc->voltages = 0;
+	host->cfg.voltages = 0;
 	if (caps & SDHCI_CAN_VDD_330)
-		mmc->voltages |= MMC_VDD_32_33 | MMC_VDD_33_34;
+		host->cfg.voltages |= MMC_VDD_32_33 | MMC_VDD_33_34;
 	if (caps & SDHCI_CAN_VDD_300)
-		mmc->voltages |= MMC_VDD_29_30 | MMC_VDD_30_31;
+		host->cfg.voltages |= MMC_VDD_29_30 | MMC_VDD_30_31;
 	if (caps & SDHCI_CAN_VDD_180)
-		mmc->voltages |= MMC_VDD_165_195;
+		host->cfg.voltages |= MMC_VDD_165_195;
 
 	if (host->quirks & SDHCI_QUIRK_BROKEN_VOLTAGE)
-		mmc->voltages |= host->voltages;
+		host->cfg.voltages |= host->voltages;
 
-	mmc->host_caps = MMC_MODE_HS | MMC_MODE_HS_52MHz | MMC_MODE_4BIT;
+	host->cfg.host_caps = MMC_MODE_HS | MMC_MODE_HS_52MHz | MMC_MODE_4BIT;
 	if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) {
 		if (caps & SDHCI_CAN_DO_8BIT)
-			mmc->host_caps |= MMC_MODE_8BIT;
+			host->cfg.host_caps |= MMC_MODE_8BIT;
 	}
 	if (host->host_caps)
-		mmc->host_caps |= host->host_caps;
+		host->cfg.host_caps |= host->host_caps;
+
+	host->cfg.b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
 
 	sdhci_reset(host, SDHCI_RESET_ALL);
-	mmc_register(mmc);
+
+	host->mmc = mmc_create(&host->cfg, host);
+	if (host->mmc == NULL) {
+		printf("%s: mmc create fail!\n", __func__);
+		return -1;
+	}
 
 	return 0;
 }
diff --git a/drivers/mmc/sh_mmcif.c b/drivers/mmc/sh_mmcif.c
index 011d4f3e63..ed83a14c2d 100644
--- a/drivers/mmc/sh_mmcif.c
+++ b/drivers/mmc/sh_mmcif.c
@@ -20,11 +20,6 @@
 
 #define DRIVER_NAME	"sh_mmcif"
 
-static void *mmc_priv(struct mmc *mmc)
-{
-	return (void *)mmc->priv;
-}
-
 static int sh_mmcif_intr(void *dev_id)
 {
 	struct sh_mmcif_host *host = dev_id;
@@ -522,7 +517,7 @@ static int sh_mmcif_start_cmd(struct sh_mmcif_host *host,
 static int sh_mmcif_request(struct mmc *mmc, struct mmc_cmd *cmd,
 			    struct mmc_data *data)
 {
-	struct sh_mmcif_host *host = mmc_priv(mmc);
+	struct sh_mmcif_host *host = mmc->priv;
 	int ret;
 
 	WATCHDOG_RESET();
@@ -550,7 +545,7 @@ static int sh_mmcif_request(struct mmc *mmc, struct mmc_cmd *cmd,
 
 static void sh_mmcif_set_ios(struct mmc *mmc)
 {
-	struct sh_mmcif_host *host = mmc_priv(mmc);
+	struct sh_mmcif_host *host = mmc->priv;
 
 	if (mmc->clock)
 		sh_mmcif_clock_control(host, mmc->clock);
@@ -567,44 +562,48 @@ static void sh_mmcif_set_ios(struct mmc *mmc)
 
 static int sh_mmcif_init(struct mmc *mmc)
 {
-	struct sh_mmcif_host *host = mmc_priv(mmc);
+	struct sh_mmcif_host *host = mmc->priv;
 
 	sh_mmcif_sync_reset(host);
 	sh_mmcif_write(MASK_ALL, &host->regs->ce_int_mask);
 	return 0;
 }
 
+static const struct mmc_ops sh_mmcif_ops = {
+	.send_cmd	= sh_mmcif_request,
+	.set_ios	= sh_mmcif_set_ios,
+	.init		= sh_mmcif_init,
+};
+
+static struct mmc_config sh_mmcif_cfg = {
+	.name		= DRIVER_NAME,
+	.ops		= &sh_mmcif_ops,
+	.host_caps	= MMC_MODE_HS | MMC_MODE_HS_52MHz | MMC_MODE_4BIT |
+			  MMC_MODE_8BIT | MMC_MODE_HC,
+	.voltages	= MMC_VDD_32_33 | MMC_VDD_33_34,
+	.f_min		= CLKDEV_MMC_INIT,
+	.f_max		= CLKDEV_EMMC_DATA,
+	.b_max		= CONFIG_SYS_MMC_MAX_BLK_COUNT,
+};
+
 int mmcif_mmc_init(void)
 {
-	int ret = 0;
 	struct mmc *mmc;
 	struct sh_mmcif_host *host = NULL;
 
-	mmc = malloc(sizeof(struct mmc));
-	if (!mmc)
-		ret = -ENOMEM;
-	memset(mmc, 0, sizeof(*mmc));
 	host = malloc(sizeof(struct sh_mmcif_host));
 	if (!host)
-		ret = -ENOMEM;
+		return -ENOMEM;
 	memset(host, 0, sizeof(*host));
 
-	mmc->f_min = CLKDEV_MMC_INIT;
-	mmc->f_max = CLKDEV_EMMC_DATA;
-	mmc->voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
-	mmc->host_caps = MMC_MODE_HS | MMC_MODE_HS_52MHz | MMC_MODE_4BIT |
-			 MMC_MODE_8BIT | MMC_MODE_HC;
-	memcpy(mmc->name, DRIVER_NAME, sizeof(DRIVER_NAME));
-	mmc->send_cmd = sh_mmcif_request;
-	mmc->set_ios = sh_mmcif_set_ios;
-	mmc->init = sh_mmcif_init;
-	mmc->getcd = NULL;
-	mmc->getwp = NULL;
 	host->regs = (struct sh_mmcif_regs *)CONFIG_SH_MMCIF_ADDR;
 	host->clk = CONFIG_SH_MMCIF_CLK;
-	mmc->priv = host;
 
-	mmc_register(mmc);
+	mmc = mmc_create(&sh_mmcif_cfg, host);
+	if (mmc == NULL) {
+		free(host);
+		return -ENOMEM;
+	}
 
-	return ret;
+	return 0;
 }
diff --git a/drivers/mmc/socfpga_dw_mmc.c b/drivers/mmc/socfpga_dw_mmc.c
new file mode 100644
index 0000000000..bc53a5da27
--- /dev/null
+++ b/drivers/mmc/socfpga_dw_mmc.c
@@ -0,0 +1,68 @@
+/*
+ * (C) Copyright 2013 Altera Corporation <www.altera.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <malloc.h>
+#include <dwmmc.h>
+#include <asm/arch/dwmmc.h>
+#include <asm/arch/clock_manager.h>
+#include <asm/arch/system_manager.h>
+
+static const struct socfpga_clock_manager *clock_manager_base =
+		(void *)SOCFPGA_CLKMGR_ADDRESS;
+static const struct socfpga_system_manager *system_manager_base =
+		(void *)SOCFPGA_SYSMGR_ADDRESS;
+
+static char *SOCFPGA_NAME = "SOCFPGA DWMMC";
+
+static void socfpga_dwmci_clksel(struct dwmci_host *host)
+{
+	unsigned int drvsel;
+	unsigned int smplsel;
+
+	/* Disable SDMMC clock. */
+	clrbits_le32(&clock_manager_base->per_pll_en,
+		CLKMGR_PERPLLGRP_EN_SDMMCCLK_MASK);
+
+	/* Configures drv_sel and smpl_sel */
+	drvsel = CONFIG_SOCFPGA_DWMMC_DRVSEL;
+	smplsel = CONFIG_SOCFPGA_DWMMC_SMPSEL;
+
+	debug("%s: drvsel %d smplsel %d\n", __func__, drvsel, smplsel);
+	writel(SYSMGR_SDMMC_CTRL_SET(smplsel, drvsel),
+		&system_manager_base->sdmmcgrp_ctrl);
+
+	debug("%s: SYSMGR_SDMMCGRP_CTRL_REG = 0x%x\n", __func__,
+		readl(&system_manager_base->sdmmcgrp_ctrl));
+
+	/* Enable SDMMC clock */
+	setbits_le32(&clock_manager_base->per_pll_en,
+		CLKMGR_PERPLLGRP_EN_SDMMCCLK_MASK);
+}
+
+int socfpga_dwmmc_init(u32 regbase, int bus_width, int index)
+{
+	struct dwmci_host *host = NULL;
+	host = calloc(sizeof(struct dwmci_host), 1);
+	if (!host) {
+		printf("dwmci_host calloc fail!\n");
+		return -1;
+	}
+
+	host->name = SOCFPGA_NAME;
+	host->ioaddr = (void *)regbase;
+	host->buswidth = bus_width;
+	host->clksel = socfpga_dwmci_clksel;
+	host->dev_index = index;
+	/* fixed clock divide by 4 which due to the SDMMC wrapper */
+	host->bus_hz = CONFIG_SOCFPGA_DWMMC_BUS_HZ;
+	host->fifoth_val = MSIZE(0x2) |
+		RX_WMARK(CONFIG_SOCFPGA_DWMMC_FIFO_DEPTH / 2 - 1) |
+		TX_WMARK(CONFIG_SOCFPGA_DWMMC_FIFO_DEPTH / 2);
+
+	return add_dwmci(host, host->bus_hz, 400000);
+}
+
diff --git a/drivers/mmc/tegra_mmc.c b/drivers/mmc/tegra_mmc.c
index e1817e24f6..ed67eec252 100644
--- a/drivers/mmc/tegra_mmc.c
+++ b/drivers/mmc/tegra_mmc.c
@@ -18,7 +18,6 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-struct mmc mmc_dev[MAX_HOSTS];
 struct mmc_host mmc_host[MAX_HOSTS];
 
 #ifndef CONFIG_OF_CONTROL
@@ -145,7 +144,7 @@ static int mmc_wait_inhibit(struct mmc_host *host,
 static int mmc_send_cmd_bounced(struct mmc *mmc, struct mmc_cmd *cmd,
 			struct mmc_data *data, struct bounce_buffer *bbstate)
 {
-	struct mmc_host *host = (struct mmc_host *)mmc->priv;
+	struct mmc_host *host = mmc->priv;
 	int flags, i;
 	int result;
 	unsigned int mask = 0;
@@ -314,7 +313,7 @@ static int mmc_send_cmd_bounced(struct mmc *mmc, struct mmc_cmd *cmd,
 	return 0;
 }
 
-static int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
+static int tegra_mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
 			struct mmc_data *data)
 {
 	void *buf;
@@ -396,7 +395,7 @@ out:
 	host->clock = clock;
 }
 
-static void mmc_set_ios(struct mmc *mmc)
+static void tegra_mmc_set_ios(struct mmc *mmc)
 {
 	struct mmc_host *host = mmc->priv;
 	unsigned char ctrl;
@@ -456,7 +455,7 @@ static void mmc_reset(struct mmc_host *host, struct mmc *mmc)
 	}
 
 	/* Set SD bus voltage & enable bus power */
-	mmc_set_power(host, fls(mmc->voltages) - 1);
+	mmc_set_power(host, fls(mmc->cfg->voltages) - 1);
 	debug("%s: power control = %02X, host control = %02X\n", __func__,
 		readb(&host->reg->pwrcon), readb(&host->reg->hostctl));
 
@@ -464,9 +463,9 @@ static void mmc_reset(struct mmc_host *host, struct mmc *mmc)
 	pad_init_mmc(host);
 }
 
-static int mmc_core_init(struct mmc *mmc)
+static int tegra_mmc_core_init(struct mmc *mmc)
 {
-	struct mmc_host *host = (struct mmc_host *)mmc->priv;
+	struct mmc_host *host = mmc->priv;
 	unsigned int mask;
 	debug(" mmc_core_init called\n");
 
@@ -511,7 +510,7 @@ static int mmc_core_init(struct mmc *mmc)
 
 int tegra_mmc_getcd(struct mmc *mmc)
 {
-	struct mmc_host *host = (struct mmc_host *)mmc->priv;
+	struct mmc_host *host = mmc->priv;
 
 	debug("tegra_mmc_getcd called\n");
 
@@ -521,6 +520,13 @@ int tegra_mmc_getcd(struct mmc *mmc)
 	return 1;
 }
 
+static const struct mmc_ops tegra_mmc_ops = {
+	.send_cmd	= tegra_mmc_send_cmd,
+	.set_ios	= tegra_mmc_set_ios,
+	.init		= tegra_mmc_core_init,
+	.getcd		= tegra_mmc_getcd,
+};
+
 static int do_mmc_init(int dev_index)
 {
 	struct mmc_host *host;
@@ -554,23 +560,18 @@ static int do_mmc_init(int dev_index)
 		debug(" CD GPIO name = %s\n", host->cd_gpio.name);
 	}
 
-	mmc = &mmc_dev[dev_index];
+	memset(&host->cfg, 0, sizeof(host->cfg));
 
-	sprintf(mmc->name, "Tegra SD/MMC");
-	mmc->priv = host;
-	mmc->send_cmd = mmc_send_cmd;
-	mmc->set_ios = mmc_set_ios;
-	mmc->init = mmc_core_init;
-	mmc->getcd = tegra_mmc_getcd;
-	mmc->getwp = NULL;
+	host->cfg.name = "Tegra SD/MMC";
+	host->cfg.ops = &tegra_mmc_ops;
 
-	mmc->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
-	mmc->host_caps = 0;
+	host->cfg.voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
+	host->cfg.host_caps = 0;
 	if (host->width == 8)
-		mmc->host_caps |= MMC_MODE_8BIT;
+		host->cfg.host_caps |= MMC_MODE_8BIT;
 	if (host->width >= 4)
-		mmc->host_caps |= MMC_MODE_4BIT;
-	mmc->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS | MMC_MODE_HC;
+		host->cfg.host_caps |= MMC_MODE_4BIT;
+	host->cfg.host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS | MMC_MODE_HC;
 
 	/*
 	 * min freq is for card identification, and is the highest
@@ -578,10 +579,14 @@ static int do_mmc_init(int dev_index)
 	 * max freq is highest HS eMMC clock as per the SD/MMC spec
 	 *  (actually 52MHz)
 	 */
-	mmc->f_min = 375000;
-	mmc->f_max = 48000000;
+	host->cfg.f_min = 375000;
+	host->cfg.f_max = 48000000;
+
+	host->cfg.b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
 
-	mmc_register(mmc);
+	mmc = mmc_create(&host->cfg, host);
+	if (mmc == NULL)
+		return -1;
 
 	return 0;
 }
@@ -668,6 +673,15 @@ void tegra_mmc_init(void)
 	const void *blob = gd->fdt_blob;
 	debug("%s entry\n", __func__);
 
+	/* See if any Tegra124 MMC controllers are present */
+	count = fdtdec_find_aliases_for_id(blob, "sdhci",
+		COMPAT_NVIDIA_TEGRA124_SDMMC, node_list, MAX_HOSTS);
+	debug("%s: count of Tegra124 sdhci nodes is %d\n", __func__, count);
+	if (process_nodes(blob, node_list, count)) {
+		printf("%s: Error processing T30 mmc node(s)!\n", __func__);
+		return;
+	}
+
 	/* See if any Tegra30 MMC controllers are present */
 	count = fdtdec_find_aliases_for_id(blob, "sdhci",
 		COMPAT_NVIDIA_TEGRA30_SDMMC, node_list, MAX_HOSTS);
diff --git a/drivers/mmc/zynq_sdhci.c b/drivers/mmc/zynq_sdhci.c
index 610bef5cba..fdce2c2c10 100644
--- a/drivers/mmc/zynq_sdhci.c
+++ b/drivers/mmc/zynq_sdhci.c
@@ -7,6 +7,8 @@
  */
 
 #include <common.h>
+#include <fdtdec.h>
+#include <libfdt.h>
 #include <malloc.h>
 #include <sdhci.h>
 #include <asm/arch/sys_proto.h>
@@ -23,7 +25,8 @@ int zynq_sdhci_init(u32 regbase)
 
 	host->name = "zynq_sdhci";
 	host->ioaddr = (void *)regbase;
-	host->quirks = SDHCI_QUIRK_NO_CD | SDHCI_QUIRK_WAIT_SEND_CMD;
+	host->quirks = SDHCI_QUIRK_NO_CD | SDHCI_QUIRK_WAIT_SEND_CMD |
+		       SDHCI_QUIRK_BROKEN_R1B;
 	host->version = sdhci_readw(host, SDHCI_HOST_VERSION);
 
 	host->host_caps = MMC_MODE_HC;
@@ -31,3 +34,30 @@ int zynq_sdhci_init(u32 regbase)
 	add_sdhci(host, 52000000, 52000000 >> 9);
 	return 0;
 }
+
+#ifdef CONFIG_OF_CONTROL
+int zynq_sdhci_of_init(const void *blob)
+{
+	int offset = 0;
+	u32 ret = 0;
+	u32 reg;
+
+	debug("ZYNQ SDHCI: Initialization\n");
+
+	do {
+		offset = fdt_node_offset_by_compatible(blob, offset,
+					"arasan,sdhci-8.9a");
+		if (offset != -1) {
+			reg = fdtdec_get_addr(blob, offset, "reg");
+			if (reg != FDT_ADDR_T_NONE) {
+				ret |= zynq_sdhci_init(reg);
+			} else {
+				debug("ZYNQ SDHCI: Can't get base address\n");
+				return -1;
+			}
+		}
+	} while (offset != -1);
+
+	return ret;
+}
+#endif
diff --git a/drivers/mtd/Makefile b/drivers/mtd/Makefile
index d2c3bdab96..5467a951bb 100644
--- a/drivers/mtd/Makefile
+++ b/drivers/mtd/Makefile
@@ -5,38 +5,16 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	:= $(obj)libmtd.o
-
 ifneq (,$(findstring y,$(CONFIG_MTD_DEVICE)$(CONFIG_CMD_NAND)$(CONFIG_CMD_ONENAND)))
-COBJS-y += mtdcore.o
+obj-y += mtdcore.o
 endif
-COBJS-$(CONFIG_MTD_PARTITIONS) += mtdpart.o
-COBJS-$(CONFIG_MTD_CONCAT) += mtdconcat.o
-COBJS-$(CONFIG_HAS_DATAFLASH) += at45.o
-COBJS-$(CONFIG_FLASH_CFI_DRIVER) += cfi_flash.o
-COBJS-$(CONFIG_FLASH_CFI_MTD) += cfi_mtd.o
-COBJS-$(CONFIG_HAS_DATAFLASH) += dataflash.o
-COBJS-$(CONFIG_FTSMC020) += ftsmc020.o
-COBJS-$(CONFIG_FLASH_CFI_LEGACY) += jedec_flash.o
-COBJS-$(CONFIG_MW_EEPROM) += mw_eeprom.o
-COBJS-$(CONFIG_ST_SMI) += st_smi.o
-
-COBJS	:= $(COBJS-y)
-SRCS	:= $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-
-all:	$(LIB)
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-$(CONFIG_MTD_PARTITIONS) += mtdpart.o
+obj-$(CONFIG_MTD_CONCAT) += mtdconcat.o
+obj-$(CONFIG_HAS_DATAFLASH) += at45.o
+obj-$(CONFIG_FLASH_CFI_DRIVER) += cfi_flash.o
+obj-$(CONFIG_FLASH_CFI_MTD) += cfi_mtd.o
+obj-$(CONFIG_HAS_DATAFLASH) += dataflash.o
+obj-$(CONFIG_FTSMC020) += ftsmc020.o
+obj-$(CONFIG_FLASH_CFI_LEGACY) += jedec_flash.o
+obj-$(CONFIG_MW_EEPROM) += mw_eeprom.o
+obj-$(CONFIG_ST_SMI) += st_smi.o
diff --git a/drivers/mtd/nand/Makefile b/drivers/mtd/nand/Makefile
index 366dee6670..650cbdcfce 100644
--- a/drivers/mtd/nand/Makefile
+++ b/drivers/mtd/nand/Makefile
@@ -5,89 +5,66 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	:= $(obj)libnand.o
-
-ifdef CONFIG_CMD_NAND
-
 ifdef CONFIG_SPL_BUILD
 
 ifdef CONFIG_SPL_NAND_DRIVERS
 NORMAL_DRIVERS=y
 endif
 
-COBJS-$(CONFIG_SPL_NAND_AM33XX_BCH) += am335x_spl_bch.o
-COBJS-$(CONFIG_SPL_NAND_DOCG4) += docg4_spl.o
-COBJS-$(CONFIG_SPL_NAND_SIMPLE) += nand_spl_simple.o
-COBJS-$(CONFIG_SPL_NAND_LOAD) += nand_spl_load.o
-COBJS-$(CONFIG_SPL_NAND_ECC) += nand_ecc.o
-COBJS-$(CONFIG_SPL_NAND_BASE) += nand_base.o
-COBJS-$(CONFIG_SPL_NAND_INIT) += nand.o
+obj-$(CONFIG_SPL_NAND_AM33XX_BCH) += am335x_spl_bch.o
+obj-$(CONFIG_SPL_NAND_DOCG4) += docg4_spl.o
+obj-$(CONFIG_SPL_NAND_SIMPLE) += nand_spl_simple.o
+obj-$(CONFIG_SPL_NAND_LOAD) += nand_spl_load.o
+obj-$(CONFIG_SPL_NAND_ECC) += nand_ecc.o
+obj-$(CONFIG_SPL_NAND_BASE) += nand_base.o
+obj-$(CONFIG_SPL_NAND_INIT) += nand.o
 
 else # not spl
 
 NORMAL_DRIVERS=y
 
-COBJS-y += nand.o
-COBJS-y += nand_bbt.o
-COBJS-y += nand_ids.o
-COBJS-y += nand_util.o
-COBJS-y += nand_ecc.o
-COBJS-y += nand_base.o
+obj-y += nand.o
+obj-y += nand_bbt.o
+obj-y += nand_ids.o
+obj-y += nand_util.o
+obj-y += nand_ecc.o
+obj-y += nand_base.o
 
 endif # not spl
 
 ifdef NORMAL_DRIVERS
 
-COBJS-$(CONFIG_NAND_ECC_BCH) += nand_bch.o
-
-COBJS-$(CONFIG_NAND_ATMEL) += atmel_nand.o
-COBJS-$(CONFIG_DRIVER_NAND_BFIN) += bfin_nand.o
-COBJS-$(CONFIG_NAND_DAVINCI) += davinci_nand.o
-COBJS-$(CONFIG_NAND_FSL_ELBC) += fsl_elbc_nand.o
-COBJS-$(CONFIG_NAND_FSL_IFC) += fsl_ifc_nand.o
-COBJS-$(CONFIG_NAND_FSL_UPM) += fsl_upm.o
-COBJS-$(CONFIG_NAND_FSMC) += fsmc_nand.o
-COBJS-$(CONFIG_NAND_JZ4740) += jz4740_nand.o
-COBJS-$(CONFIG_NAND_KB9202) += kb9202_nand.o
-COBJS-$(CONFIG_NAND_KIRKWOOD) += kirkwood_nand.o
-COBJS-$(CONFIG_NAND_KMETER1) += kmeter1_nand.o
-COBJS-$(CONFIG_NAND_MPC5121_NFC) += mpc5121_nfc.o
-COBJS-$(CONFIG_NAND_MXC) += mxc_nand.o
-COBJS-$(CONFIG_NAND_MXS) += mxs_nand.o
-COBJS-$(CONFIG_NAND_NDFC) += ndfc.o
-COBJS-$(CONFIG_NAND_NOMADIK) += nomadik.o
-COBJS-$(CONFIG_NAND_S3C2410) += s3c2410_nand.o
-COBJS-$(CONFIG_NAND_SPEAR) += spr_nand.o
-COBJS-$(CONFIG_TEGRA_NAND) += tegra_nand.o
-COBJS-$(CONFIG_NAND_OMAP_GPMC) += omap_gpmc.o
-COBJS-$(CONFIG_NAND_PLAT) += nand_plat.o
-COBJS-$(CONFIG_NAND_DOCG4) += docg4.o
+obj-$(CONFIG_NAND_ECC_BCH) += nand_bch.o
+
+obj-$(CONFIG_NAND_ATMEL) += atmel_nand.o
+obj-$(CONFIG_DRIVER_NAND_BFIN) += bfin_nand.o
+obj-$(CONFIG_NAND_DAVINCI) += davinci_nand.o
+obj-$(CONFIG_NAND_FSL_ELBC) += fsl_elbc_nand.o
+obj-$(CONFIG_NAND_FSL_IFC) += fsl_ifc_nand.o
+obj-$(CONFIG_NAND_FSL_UPM) += fsl_upm.o
+obj-$(CONFIG_NAND_FSMC) += fsmc_nand.o
+obj-$(CONFIG_NAND_JZ4740) += jz4740_nand.o
+obj-$(CONFIG_NAND_KB9202) += kb9202_nand.o
+obj-$(CONFIG_NAND_KIRKWOOD) += kirkwood_nand.o
+obj-$(CONFIG_NAND_KMETER1) += kmeter1_nand.o
+obj-$(CONFIG_NAND_MPC5121_NFC) += mpc5121_nfc.o
+obj-$(CONFIG_NAND_FSL_NFC) += fsl_nfc.o
+obj-$(CONFIG_NAND_MXC) += mxc_nand.o
+obj-$(CONFIG_NAND_MXS) += mxs_nand.o
+obj-$(CONFIG_NAND_NDFC) += ndfc.o
+obj-$(CONFIG_NAND_NOMADIK) += nomadik.o
+obj-$(CONFIG_NAND_S3C2410) += s3c2410_nand.o
+obj-$(CONFIG_NAND_SPEAR) += spr_nand.o
+obj-$(CONFIG_TEGRA_NAND) += tegra_nand.o
+obj-$(CONFIG_NAND_OMAP_GPMC) += omap_gpmc.o
+obj-$(CONFIG_NAND_OMAP_ELM) += omap_elm.o
+obj-$(CONFIG_NAND_PLAT) += nand_plat.o
+obj-$(CONFIG_NAND_DOCG4) += docg4.o
 
 else  # minimal SPL drivers
 
-COBJS-$(CONFIG_NAND_FSL_ELBC) += fsl_elbc_spl.o
-COBJS-$(CONFIG_NAND_FSL_IFC) += fsl_ifc_spl.o
-COBJS-$(CONFIG_NAND_MXC) += mxc_nand_spl.o
+obj-$(CONFIG_NAND_FSL_ELBC) += fsl_elbc_spl.o
+obj-$(CONFIG_NAND_FSL_IFC) += fsl_ifc_spl.o
+obj-$(CONFIG_NAND_MXC) += mxc_nand_spl.o
 
 endif # drivers
-endif # nand
-
-COBJS	:= $(COBJS-y)
-SRCS	:= $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-
-all:	$(LIB)
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
diff --git a/drivers/mtd/nand/atmel_nand.c b/drivers/mtd/nand/atmel_nand.c
index da83f06e47..e1fc48fca4 100644
--- a/drivers/mtd/nand/atmel_nand.c
+++ b/drivers/mtd/nand/atmel_nand.c
@@ -12,9 +12,8 @@
  */
 
 #include <common.h>
-#include <asm/arch/hardware.h>
+#include <asm/gpio.h>
 #include <asm/arch/gpio.h>
-#include <asm/arch/at91_pio.h>
 
 #include <malloc.h>
 #include <nand.h>
@@ -32,6 +31,10 @@
 
 #ifdef CONFIG_ATMEL_NAND_HW_PMECC
 
+#ifdef CONFIG_SPL_BUILD
+#undef CONFIG_SYS_NAND_ONFI_DETECTION
+#endif
+
 struct atmel_nand_host {
 	struct pmecc_regs __iomem *pmecc;
 	struct pmecc_errloc_regs __iomem *pmerrloc;
@@ -412,7 +415,7 @@ static int pmecc_err_location(struct mtd_info *mtd)
 	}
 
 	if (!timeout) {
-		printk(KERN_ERR "atmel_nand : Timeout to calculate PMECC error location\n");
+		dev_err(host->dev, "atmel_nand : Timeout to calculate PMECC error location\n");
 		return -1;
 	}
 
@@ -452,7 +455,7 @@ static void pmecc_correct_data(struct mtd_info *mtd, uint8_t *buf, uint8_t *ecc,
 			*(buf + byte_pos) ^= (1 << bit_pos);
 
 			pos = sector_num * host->pmecc_sector_size + byte_pos;
-			printk(KERN_INFO "Bit flip in data area, byte_pos: %d, bit_pos: %d, 0x%02x -> 0x%02x\n",
+			dev_dbg(host->dev, "Bit flip in data area, byte_pos: %d, bit_pos: %d, 0x%02x -> 0x%02x\n",
 				pos, bit_pos, err_byte, *(buf + byte_pos));
 		} else {
 			/* Bit flip in OOB area */
@@ -462,7 +465,7 @@ static void pmecc_correct_data(struct mtd_info *mtd, uint8_t *buf, uint8_t *ecc,
 			ecc[tmp] ^= (1 << bit_pos);
 
 			pos = tmp + nand_chip->ecc.layout->eccpos[0];
-			printk(KERN_INFO "Bit flip in OOB, oob_byte_pos: %d, bit_pos: %d, 0x%02x -> 0x%02x\n",
+			dev_dbg(host->dev, "Bit flip in OOB, oob_byte_pos: %d, bit_pos: %d, 0x%02x -> 0x%02x\n",
 				pos, bit_pos, err_byte, ecc[tmp]);
 		}
 
@@ -500,7 +503,7 @@ normal_check:
 
 			err_nbr = pmecc_err_location(mtd);
 			if (err_nbr == -1) {
-				printk(KERN_ERR "PMECC: Too many errors\n");
+				dev_err(host->dev, "PMECC: Too many errors\n");
 				mtd->ecc_stats.failed++;
 				return -EIO;
 			} else {
@@ -544,7 +547,7 @@ static int atmel_nand_pmecc_read_page(struct mtd_info *mtd,
 	}
 
 	if (!timeout) {
-		printk(KERN_ERR "atmel_nand : Timeout to read PMECC page\n");
+		dev_err(host->dev, "atmel_nand : Timeout to read PMECC page\n");
 		return -1;
 	}
 
@@ -584,7 +587,7 @@ static int atmel_nand_pmecc_write_page(struct mtd_info *mtd,
 	}
 
 	if (!timeout) {
-		printk(KERN_ERR "atmel_nand : Timeout to read PMECC status, fail to write PMECC in oob\n");
+		dev_err(host->dev, "atmel_nand : Timeout to read PMECC status, fail to write PMECC in oob\n");
 		goto out;
 	}
 
@@ -827,6 +830,7 @@ static int atmel_pmecc_nand_init_params(struct nand_chip *nand,
 	switch (mtd->writesize) {
 	case 2048:
 	case 4096:
+	case 8192:
 		host->pmecc_degree = (sector_size == 512) ?
 			PMECC_GF_DIMENSION_13 : PMECC_GF_DIMENSION_14;
 		host->pmecc_cw_len = (1 << host->pmecc_degree) - 1;
@@ -840,8 +844,15 @@ static int atmel_pmecc_nand_init_params(struct nand_chip *nand,
 		nand->ecc.steps = 1;
 		nand->ecc.bytes = host->pmecc_bytes_per_sector *
 				       host->pmecc_sector_number;
+
+		if (nand->ecc.bytes > MTD_MAX_ECCPOS_ENTRIES_LARGE) {
+			dev_err(host->dev, "too large eccpos entries. max support ecc.bytes is %d\n",
+					MTD_MAX_ECCPOS_ENTRIES_LARGE);
+			return -EINVAL;
+		}
+
 		if (nand->ecc.bytes > mtd->oobsize - 2) {
-			printk(KERN_ERR "No room for ECC bytes\n");
+			dev_err(host->dev, "No room for ECC bytes\n");
 			return -EINVAL;
 		}
 		pmecc_config_ecc_layout(&atmel_pmecc_oobinfo,
@@ -852,7 +863,7 @@ static int atmel_pmecc_nand_init_params(struct nand_chip *nand,
 	case 512:
 	case 1024:
 		/* TODO */
-		printk(KERN_ERR "Unsupported page size for PMECC, use Software ECC\n");
+		dev_err(host->dev, "Unsupported page size for PMECC, use Software ECC\n");
 	default:
 		/* page size not handled by HW ECC */
 		/* switching back to soft ECC */
@@ -1035,7 +1046,7 @@ static int atmel_nand_correct(struct mtd_info *mtd, u_char *dat,
 		/* it doesn't seems to be a freshly
 		 * erased block.
 		 * We can't correct so many errors */
-		printk(KERN_WARNING "atmel_nand : multiple errors detected."
+		dev_warn(host->dev, "atmel_nand : multiple errors detected."
 				" Unable to correct.\n");
 		return -EIO;
 	}
@@ -1045,12 +1056,12 @@ static int atmel_nand_correct(struct mtd_info *mtd, u_char *dat,
 		/* there's nothing much to do here.
 		 * the bit error is on the ECC itself.
 		 */
-		printk(KERN_WARNING "atmel_nand : one bit error on ECC code."
+		dev_warn(host->dev, "atmel_nand : one bit error on ECC code."
 				" Nothing to correct\n");
 		return 0;
 	}
 
-	printk(KERN_WARNING "atmel_nand : one bit error on data."
+	dev_warn(host->dev, "atmel_nand : one bit error on data."
 			" (word offset in the page :"
 			" 0x%x bit offset : 0x%x)\n",
 			ecc_word, ecc_bit);
@@ -1062,7 +1073,7 @@ static int atmel_nand_correct(struct mtd_info *mtd, u_char *dat,
 		/* 8 bits words */
 		dat[ecc_word] ^= (1 << ecc_bit);
 	}
-	printk(KERN_WARNING "atmel_nand : error corrected\n");
+	dev_warn(host->dev, "atmel_nand : error corrected\n");
 	return 1;
 }
 
@@ -1146,8 +1157,7 @@ static void at91_nand_hwcontrol(struct mtd_info *mtd,
 			IO_ADDR_W |= CONFIG_SYS_NAND_MASK_ALE;
 
 #ifdef CONFIG_SYS_NAND_ENABLE_PIN
-		at91_set_gpio_value(CONFIG_SYS_NAND_ENABLE_PIN,
-				    !(ctrl & NAND_NCE));
+		gpio_set_value(CONFIG_SYS_NAND_ENABLE_PIN, !(ctrl & NAND_NCE));
 #endif
 		this->IO_ADDR_W = (void *) IO_ADDR_W;
 	}
@@ -1159,10 +1169,213 @@ static void at91_nand_hwcontrol(struct mtd_info *mtd,
 #ifdef CONFIG_SYS_NAND_READY_PIN
 static int at91_nand_ready(struct mtd_info *mtd)
 {
-	return at91_get_gpio_value(CONFIG_SYS_NAND_READY_PIN);
+	return gpio_get_value(CONFIG_SYS_NAND_READY_PIN);
 }
 #endif
 
+#ifdef CONFIG_SPL_BUILD
+/* The following code is for SPL */
+static nand_info_t mtd;
+static struct nand_chip nand_chip;
+
+static int nand_command(int block, int page, uint32_t offs, u8 cmd)
+{
+	struct nand_chip *this = mtd.priv;
+	int page_addr = page + block * CONFIG_SYS_NAND_PAGE_COUNT;
+	void (*hwctrl)(struct mtd_info *mtd, int cmd,
+			unsigned int ctrl) = this->cmd_ctrl;
+
+	while (this->dev_ready(&mtd))
+		;
+
+	if (cmd == NAND_CMD_READOOB) {
+		offs += CONFIG_SYS_NAND_PAGE_SIZE;
+		cmd = NAND_CMD_READ0;
+	}
+
+	hwctrl(&mtd, cmd, NAND_CTRL_CLE | NAND_CTRL_CHANGE);
+
+	if (this->options & NAND_BUSWIDTH_16)
+		offs >>= 1;
+
+	hwctrl(&mtd, offs & 0xff, NAND_CTRL_ALE | NAND_CTRL_CHANGE);
+	hwctrl(&mtd, (offs >> 8) & 0xff, NAND_CTRL_ALE);
+	hwctrl(&mtd, (page_addr & 0xff), NAND_CTRL_ALE);
+	hwctrl(&mtd, ((page_addr >> 8) & 0xff), NAND_CTRL_ALE);
+#ifdef CONFIG_SYS_NAND_5_ADDR_CYCLE
+	hwctrl(&mtd, (page_addr >> 16) & 0x0f, NAND_CTRL_ALE);
+#endif
+	hwctrl(&mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
+
+	hwctrl(&mtd, NAND_CMD_READSTART, NAND_CTRL_CLE | NAND_CTRL_CHANGE);
+	hwctrl(&mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
+
+	while (this->dev_ready(&mtd))
+		;
+
+	return 0;
+}
+
+static int nand_is_bad_block(int block)
+{
+	struct nand_chip *this = mtd.priv;
+
+	nand_command(block, 0, CONFIG_SYS_NAND_BAD_BLOCK_POS, NAND_CMD_READOOB);
+
+	if (this->options & NAND_BUSWIDTH_16) {
+		if (readw(this->IO_ADDR_R) != 0xffff)
+			return 1;
+	} else {
+		if (readb(this->IO_ADDR_R) != 0xff)
+			return 1;
+	}
+
+	return 0;
+}
+
+#ifdef CONFIG_SPL_NAND_ECC
+static int nand_ecc_pos[] = CONFIG_SYS_NAND_ECCPOS;
+#define ECCSTEPS (CONFIG_SYS_NAND_PAGE_SIZE / \
+		  CONFIG_SYS_NAND_ECCSIZE)
+#define ECCTOTAL (ECCSTEPS * CONFIG_SYS_NAND_ECCBYTES)
+
+static int nand_read_page(int block, int page, void *dst)
+{
+	struct nand_chip *this = mtd.priv;
+	u_char ecc_calc[ECCTOTAL];
+	u_char ecc_code[ECCTOTAL];
+	u_char oob_data[CONFIG_SYS_NAND_OOBSIZE];
+	int eccsize = CONFIG_SYS_NAND_ECCSIZE;
+	int eccbytes = CONFIG_SYS_NAND_ECCBYTES;
+	int eccsteps = ECCSTEPS;
+	int i;
+	uint8_t *p = dst;
+	nand_command(block, page, 0, NAND_CMD_READ0);
+
+	for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
+		if (this->ecc.mode != NAND_ECC_SOFT)
+			this->ecc.hwctl(&mtd, NAND_ECC_READ);
+		this->read_buf(&mtd, p, eccsize);
+		this->ecc.calculate(&mtd, p, &ecc_calc[i]);
+	}
+	this->read_buf(&mtd, oob_data, CONFIG_SYS_NAND_OOBSIZE);
+
+	for (i = 0; i < ECCTOTAL; i++)
+		ecc_code[i] = oob_data[nand_ecc_pos[i]];
+
+	eccsteps = ECCSTEPS;
+	p = dst;
+
+	for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
+		this->ecc.correct(&mtd, p, &ecc_code[i], &ecc_calc[i]);
+
+	return 0;
+}
+#else
+static int nand_read_page(int block, int page, void *dst)
+{
+	struct nand_chip *this = mtd.priv;
+
+	nand_command(block, page, 0, NAND_CMD_READ0);
+	atmel_nand_pmecc_read_page(&mtd, this, dst, 0, page);
+
+	return 0;
+}
+#endif /* CONFIG_SPL_NAND_ECC */
+
+int nand_spl_load_image(uint32_t offs, unsigned int size, void *dst)
+{
+	unsigned int block, lastblock;
+	unsigned int page;
+
+	block = offs / CONFIG_SYS_NAND_BLOCK_SIZE;
+	lastblock = (offs + size - 1) / CONFIG_SYS_NAND_BLOCK_SIZE;
+	page = (offs % CONFIG_SYS_NAND_BLOCK_SIZE) / CONFIG_SYS_NAND_PAGE_SIZE;
+
+	while (block <= lastblock) {
+		if (!nand_is_bad_block(block)) {
+			while (page < CONFIG_SYS_NAND_PAGE_COUNT) {
+				nand_read_page(block, page, dst);
+				dst += CONFIG_SYS_NAND_PAGE_SIZE;
+				page++;
+			}
+
+			page = 0;
+		} else {
+			lastblock++;
+		}
+
+		block++;
+	}
+
+	return 0;
+}
+
+int at91_nand_wait_ready(struct mtd_info *mtd)
+{
+	struct nand_chip *this = mtd->priv;
+
+	udelay(this->chip_delay);
+
+	return 0;
+}
+
+int board_nand_init(struct nand_chip *nand)
+{
+	int ret = 0;
+
+	nand->ecc.mode = NAND_ECC_SOFT;
+#ifdef CONFIG_SYS_NAND_DBW_16
+	nand->options = NAND_BUSWIDTH_16;
+	nand->read_buf = nand_read_buf16;
+#else
+	nand->read_buf = nand_read_buf;
+#endif
+	nand->cmd_ctrl = at91_nand_hwcontrol;
+#ifdef CONFIG_SYS_NAND_READY_PIN
+	nand->dev_ready = at91_nand_ready;
+#else
+	nand->dev_ready = at91_nand_wait_ready;
+#endif
+	nand->chip_delay = 20;
+
+#ifdef CONFIG_ATMEL_NAND_HWECC
+#ifdef CONFIG_ATMEL_NAND_HW_PMECC
+	ret = atmel_pmecc_nand_init_params(nand, &mtd);
+#endif
+#endif
+
+	return ret;
+}
+
+void nand_init(void)
+{
+	mtd.writesize = CONFIG_SYS_NAND_PAGE_SIZE;
+	mtd.oobsize = CONFIG_SYS_NAND_OOBSIZE;
+	mtd.priv = &nand_chip;
+	nand_chip.IO_ADDR_R = (void __iomem *)CONFIG_SYS_NAND_BASE;
+	nand_chip.IO_ADDR_W = (void __iomem *)CONFIG_SYS_NAND_BASE;
+	board_nand_init(&nand_chip);
+
+#ifdef CONFIG_SPL_NAND_ECC
+	if (nand_chip.ecc.mode == NAND_ECC_SOFT) {
+		nand_chip.ecc.calculate = nand_calculate_ecc;
+		nand_chip.ecc.correct = nand_correct_data;
+	}
+#endif
+
+	if (nand_chip.select_chip)
+		nand_chip.select_chip(&mtd, 0);
+}
+
+void nand_deselect(void)
+{
+	if (nand_chip.select_chip)
+		nand_chip.select_chip(&mtd, -1);
+}
+
+#else
+
 #ifndef CONFIG_SYS_NAND_BASE_LIST
 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
 #endif
@@ -1178,7 +1391,11 @@ int atmel_nand_chip_init(int devnum, ulong base_addr)
 	mtd->priv = nand;
 	nand->IO_ADDR_R = nand->IO_ADDR_W = (void  __iomem *)base_addr;
 
+#ifdef CONFIG_NAND_ECC_BCH
+	nand->ecc.mode = NAND_ECC_SOFT_BCH;
+#else
 	nand->ecc.mode = NAND_ECC_SOFT;
+#endif
 #ifdef CONFIG_SYS_NAND_DBW_16
 	nand->options = NAND_BUSWIDTH_16;
 #endif
@@ -1186,7 +1403,7 @@ int atmel_nand_chip_init(int devnum, ulong base_addr)
 #ifdef CONFIG_SYS_NAND_READY_PIN
 	nand->dev_ready = at91_nand_ready;
 #endif
-	nand->chip_delay = 20;
+	nand->chip_delay = 75;
 
 	ret = nand_scan_ident(mtd, CONFIG_SYS_NAND_MAX_CHIPS, NULL);
 	if (ret)
@@ -1214,6 +1431,7 @@ void board_nand_init(void)
 	int i;
 	for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
 		if (atmel_nand_chip_init(i, base_addr[i]))
-			printk(KERN_ERR "atmel_nand: Fail to initialize #%d chip",
+			dev_err(host->dev, "atmel_nand: Fail to initialize #%d chip",
 				i);
 }
+#endif /* CONFIG_SPL_BUILD */
diff --git a/drivers/mtd/nand/davinci_nand.c b/drivers/mtd/nand/davinci_nand.c
index d8bb5d3519..5b17d7be8b 100644
--- a/drivers/mtd/nand/davinci_nand.c
+++ b/drivers/mtd/nand/davinci_nand.c
@@ -266,6 +266,17 @@ static int nand_davinci_correct_data(struct mtd_info *mtd, u_char *dat,
 static struct nand_ecclayout nand_davinci_4bit_layout_oobfirst = {
 #if defined(CONFIG_SYS_NAND_PAGE_2K)
 	.eccbytes = 40,
+#ifdef CONFIG_NAND_6BYTES_OOB_FREE_10BYTES_ECC
+	.eccpos = {
+		6,   7,  8,  9, 10,	11, 12, 13, 14, 15,
+		22, 23, 24, 25, 26,	27, 28, 29, 30, 31,
+		38, 39, 40, 41, 42,	43, 44, 45, 46, 47,
+		54, 55, 56, 57, 58,	59, 60, 61, 62, 63,
+	},
+	.oobfree = {
+		{2, 4}, {16, 6}, {32, 6}, {48, 6},
+	},
+#else
 	.eccpos = {
 		24, 25, 26, 27, 28,
 		29, 30, 31, 32, 33, 34, 35, 36, 37, 38,
@@ -276,6 +287,7 @@ static struct nand_ecclayout nand_davinci_4bit_layout_oobfirst = {
 	.oobfree = {
 		{.offset = 2, .length = 22, },
 	},
+#endif	/* #ifdef CONFIG_NAND_6BYTES_OOB_FREE_10BYTES_ECC */
 #elif defined(CONFIG_SYS_NAND_PAGE_4K)
 	.eccbytes = 80,
 	.eccpos = {
diff --git a/drivers/mtd/nand/fsl_elbc_nand.c b/drivers/mtd/nand/fsl_elbc_nand.c
index 795209788b..2f31fc96ad 100644
--- a/drivers/mtd/nand/fsl_elbc_nand.c
+++ b/drivers/mtd/nand/fsl_elbc_nand.c
@@ -759,8 +759,12 @@ static int fsl_elbc_chip_init(int devnum, u8 *addr)
 		nand->ecc.steps = 1;
 		nand->ecc.strength = 1;
 	} else {
-		/* otherwise fall back to default software ECC */
+		/* otherwise fall back to software ECC */
+#if defined(CONFIG_NAND_ECC_BCH)
+		nand->ecc.mode = NAND_ECC_SOFT_BCH;
+#else
 		nand->ecc.mode = NAND_ECC_SOFT;
+#endif
 	}
 
 	ret = nand_scan_ident(mtd, 1, NULL);
diff --git a/drivers/mtd/nand/fsl_ifc_nand.c b/drivers/mtd/nand/fsl_ifc_nand.c
index 98a09c0641..be5a16a1ba 100644
--- a/drivers/mtd/nand/fsl_ifc_nand.c
+++ b/drivers/mtd/nand/fsl_ifc_nand.c
@@ -17,7 +17,7 @@
 
 #include <asm/io.h>
 #include <asm/errno.h>
-#include <asm/fsl_ifc.h>
+#include <fsl_ifc.h>
 
 #define FSL_IFC_V1_1_0	0x01010000
 #define MAX_BANKS	4
@@ -125,6 +125,69 @@ static struct nand_ecclayout oob_4096_ecc8 = {
 	.oobfree = { {2, 6}, {136, 82} },
 };
 
+/* 8192-byte page size with 4-bit ECC */
+static struct nand_ecclayout oob_8192_ecc4 = {
+	.eccbytes = 128,
+	.eccpos = {
+		8, 9, 10, 11, 12, 13, 14, 15,
+		16, 17, 18, 19, 20, 21, 22, 23,
+		24, 25, 26, 27, 28, 29, 30, 31,
+		32, 33, 34, 35, 36, 37, 38, 39,
+		40, 41, 42, 43, 44, 45, 46, 47,
+		48, 49, 50, 51, 52, 53, 54, 55,
+		56, 57, 58, 59, 60, 61, 62, 63,
+		64, 65, 66, 67, 68, 69, 70, 71,
+		72, 73, 74, 75, 76, 77, 78, 79,
+		80, 81, 82, 83, 84, 85, 86, 87,
+		88, 89, 90, 91, 92, 93, 94, 95,
+		96, 97, 98, 99, 100, 101, 102, 103,
+		104, 105, 106, 107, 108, 109, 110, 111,
+		112, 113, 114, 115, 116, 117, 118, 119,
+		120, 121, 122, 123, 124, 125, 126, 127,
+		128, 129, 130, 131, 132, 133, 134, 135,
+	},
+	.oobfree = { {2, 6}, {136, 208} },
+};
+
+/* 8192-byte page size with 8-bit ECC -- requires 218-byte OOB */
+static struct nand_ecclayout oob_8192_ecc8 = {
+	.eccbytes = 256,
+	.eccpos = {
+		8, 9, 10, 11, 12, 13, 14, 15,
+		16, 17, 18, 19, 20, 21, 22, 23,
+		24, 25, 26, 27, 28, 29, 30, 31,
+		32, 33, 34, 35, 36, 37, 38, 39,
+		40, 41, 42, 43, 44, 45, 46, 47,
+		48, 49, 50, 51, 52, 53, 54, 55,
+		56, 57, 58, 59, 60, 61, 62, 63,
+		64, 65, 66, 67, 68, 69, 70, 71,
+		72, 73, 74, 75, 76, 77, 78, 79,
+		80, 81, 82, 83, 84, 85, 86, 87,
+		88, 89, 90, 91, 92, 93, 94, 95,
+		96, 97, 98, 99, 100, 101, 102, 103,
+		104, 105, 106, 107, 108, 109, 110, 111,
+		112, 113, 114, 115, 116, 117, 118, 119,
+		120, 121, 122, 123, 124, 125, 126, 127,
+		128, 129, 130, 131, 132, 133, 134, 135,
+		136, 137, 138, 139, 140, 141, 142, 143,
+		144, 145, 146, 147, 148, 149, 150, 151,
+		152, 153, 154, 155, 156, 157, 158, 159,
+		160, 161, 162, 163, 164, 165, 166, 167,
+		168, 169, 170, 171, 172, 173, 174, 175,
+		176, 177, 178, 179, 180, 181, 182, 183,
+		184, 185, 186, 187, 188, 189, 190, 191,
+		192, 193, 194, 195, 196, 197, 198, 199,
+		200, 201, 202, 203, 204, 205, 206, 207,
+		208, 209, 210, 211, 212, 213, 214, 215,
+		216, 217, 218, 219, 220, 221, 222, 223,
+		224, 225, 226, 227, 228, 229, 230, 231,
+		232, 233, 234, 235, 236, 237, 238, 239,
+		240, 241, 242, 243, 244, 245, 246, 247,
+		248, 249, 250, 251, 252, 253, 254, 255,
+		256, 257, 258, 259, 260, 261, 262, 263,
+	},
+	.oobfree = { {2, 6}, {264, 80} },
+};
 
 /*
  * Generic flash bbt descriptors
@@ -167,8 +230,8 @@ static void set_addr(struct mtd_info *mtd, int column, int page_addr, int oob)
 	ctrl->page = page_addr;
 
 	/* Program ROW0/COL0 */
-	out_be32(&ifc->ifc_nand.row0, page_addr);
-	out_be32(&ifc->ifc_nand.col0, (oob ? IFC_NAND_COL_MS : 0) | column);
+	ifc_out32(&ifc->ifc_nand.row0, page_addr);
+	ifc_out32(&ifc->ifc_nand.col0, (oob ? IFC_NAND_COL_MS : 0) | column);
 
 	buf_num = page_addr & priv->bufnum_mask;
 
@@ -231,23 +294,23 @@ static int fsl_ifc_run_command(struct mtd_info *mtd)
 	int i;
 
 	/* set the chip select for NAND Transaction */
-	out_be32(&ifc->ifc_nand.nand_csel, ifc_ctrl->cs_nand);
+	ifc_out32(&ifc->ifc_nand.nand_csel, ifc_ctrl->cs_nand);
 
 	/* start read/write seq */
-	out_be32(&ifc->ifc_nand.nandseq_strt,
-		 IFC_NAND_SEQ_STRT_FIR_STRT);
+	ifc_out32(&ifc->ifc_nand.nandseq_strt,
+		  IFC_NAND_SEQ_STRT_FIR_STRT);
 
 	/* wait for NAND Machine complete flag or timeout */
 	end_tick = usec2ticks(IFC_TIMEOUT_MSECS * 1000) + get_ticks();
 
 	while (end_tick > get_ticks()) {
-		ctrl->status = in_be32(&ifc->ifc_nand.nand_evter_stat);
+		ctrl->status = ifc_in32(&ifc->ifc_nand.nand_evter_stat);
 
 		if (ctrl->status & IFC_NAND_EVTER_STAT_OPC)
 			break;
 	}
 
-	out_be32(&ifc->ifc_nand.nand_evter_stat, ctrl->status);
+	ifc_out32(&ifc->ifc_nand.nand_evter_stat, ctrl->status);
 
 	if (ctrl->status & IFC_NAND_EVTER_STAT_FTOER)
 		printf("%s: Flash Time Out Error\n", __func__);
@@ -261,7 +324,7 @@ static int fsl_ifc_run_command(struct mtd_info *mtd)
 		int sector_end = sector + chip->ecc.steps - 1;
 
 		for (i = sector / 4; i <= sector_end / 4; i++)
-			eccstat[i] = in_be32(&ifc->ifc_nand.nand_eccstat[i]);
+			eccstat[i] = ifc_in32(&ifc->ifc_nand.nand_eccstat[i]);
 
 		for (i = sector; i <= sector_end; i++) {
 			errors = check_read_ecc(mtd, ctrl, eccstat, i);
@@ -301,30 +364,30 @@ static void fsl_ifc_do_read(struct nand_chip *chip,
 
 	/* Program FIR/IFC_NAND_FCR0 for Small/Large page */
 	if (mtd->writesize > 512) {
-		out_be32(&ifc->ifc_nand.nand_fir0,
-			 (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
-			 (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) |
-			 (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP2_SHIFT) |
-			 (IFC_FIR_OP_CMD1 << IFC_NAND_FIR0_OP3_SHIFT) |
-			 (IFC_FIR_OP_RBCD << IFC_NAND_FIR0_OP4_SHIFT));
-		out_be32(&ifc->ifc_nand.nand_fir1, 0x0);
-
-		out_be32(&ifc->ifc_nand.nand_fcr0,
-			(NAND_CMD_READ0 << IFC_NAND_FCR0_CMD0_SHIFT) |
-			(NAND_CMD_READSTART << IFC_NAND_FCR0_CMD1_SHIFT));
+		ifc_out32(&ifc->ifc_nand.nand_fir0,
+			  (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
+			  (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) |
+			  (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP2_SHIFT) |
+			  (IFC_FIR_OP_CMD1 << IFC_NAND_FIR0_OP3_SHIFT) |
+			  (IFC_FIR_OP_RBCD << IFC_NAND_FIR0_OP4_SHIFT));
+		ifc_out32(&ifc->ifc_nand.nand_fir1, 0x0);
+
+		ifc_out32(&ifc->ifc_nand.nand_fcr0,
+			  (NAND_CMD_READ0 << IFC_NAND_FCR0_CMD0_SHIFT) |
+			  (NAND_CMD_READSTART << IFC_NAND_FCR0_CMD1_SHIFT));
 	} else {
-		out_be32(&ifc->ifc_nand.nand_fir0,
-			 (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
-			 (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) |
-			 (IFC_FIR_OP_RA0  << IFC_NAND_FIR0_OP2_SHIFT) |
-			 (IFC_FIR_OP_RBCD << IFC_NAND_FIR0_OP3_SHIFT));
+		ifc_out32(&ifc->ifc_nand.nand_fir0,
+			  (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
+			  (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) |
+			  (IFC_FIR_OP_RA0  << IFC_NAND_FIR0_OP2_SHIFT) |
+			  (IFC_FIR_OP_RBCD << IFC_NAND_FIR0_OP3_SHIFT));
 
 		if (oob)
-			out_be32(&ifc->ifc_nand.nand_fcr0,
-				 NAND_CMD_READOOB << IFC_NAND_FCR0_CMD0_SHIFT);
+			ifc_out32(&ifc->ifc_nand.nand_fcr0,
+				  NAND_CMD_READOOB << IFC_NAND_FCR0_CMD0_SHIFT);
 		else
-			out_be32(&ifc->ifc_nand.nand_fcr0,
-				NAND_CMD_READ0 << IFC_NAND_FCR0_CMD0_SHIFT);
+			ifc_out32(&ifc->ifc_nand.nand_fcr0,
+				  NAND_CMD_READ0 << IFC_NAND_FCR0_CMD0_SHIFT);
 	}
 }
 
@@ -345,7 +408,7 @@ static void fsl_ifc_cmdfunc(struct mtd_info *mtd, unsigned int command,
 	switch (command) {
 	/* READ0 read the entire buffer to use hardware ECC. */
 	case NAND_CMD_READ0: {
-		out_be32(&ifc->ifc_nand.nand_fbcr, 0);
+		ifc_out32(&ifc->ifc_nand.nand_fbcr, 0);
 		set_addr(mtd, 0, page_addr, 0);
 
 		ctrl->read_bytes = mtd->writesize + mtd->oobsize;
@@ -361,7 +424,7 @@ static void fsl_ifc_cmdfunc(struct mtd_info *mtd, unsigned int command,
 
 	/* READOOB reads only the OOB because no ECC is performed. */
 	case NAND_CMD_READOOB:
-		out_be32(&ifc->ifc_nand.nand_fbcr, mtd->oobsize - column);
+		ifc_out32(&ifc->ifc_nand.nand_fbcr, mtd->oobsize - column);
 		set_addr(mtd, column, page_addr, 1);
 
 		ctrl->read_bytes = mtd->writesize + mtd->oobsize;
@@ -378,19 +441,19 @@ static void fsl_ifc_cmdfunc(struct mtd_info *mtd, unsigned int command,
 		if (command == NAND_CMD_PARAM)
 			timing = IFC_FIR_OP_RBCD;
 
-		out_be32(&ifc->ifc_nand.nand_fir0,
-				(IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
-				(IFC_FIR_OP_UA  << IFC_NAND_FIR0_OP1_SHIFT) |
-				(timing << IFC_NAND_FIR0_OP2_SHIFT));
-		out_be32(&ifc->ifc_nand.nand_fcr0,
-				command << IFC_NAND_FCR0_CMD0_SHIFT);
-		out_be32(&ifc->ifc_nand.row3, column);
+		ifc_out32(&ifc->ifc_nand.nand_fir0,
+			  (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
+			  (IFC_FIR_OP_UA  << IFC_NAND_FIR0_OP1_SHIFT) |
+			  (timing << IFC_NAND_FIR0_OP2_SHIFT));
+		ifc_out32(&ifc->ifc_nand.nand_fcr0,
+			  command << IFC_NAND_FCR0_CMD0_SHIFT);
+		ifc_out32(&ifc->ifc_nand.row3, column);
 
 		/*
 		 * although currently it's 8 bytes for READID, we always read
 		 * the maximum 256 bytes(for PARAM)
 		 */
-		out_be32(&ifc->ifc_nand.nand_fbcr, 256);
+		ifc_out32(&ifc->ifc_nand.nand_fbcr, 256);
 		ctrl->read_bytes = 256;
 
 		set_addr(mtd, 0, 0, 0);
@@ -405,16 +468,16 @@ static void fsl_ifc_cmdfunc(struct mtd_info *mtd, unsigned int command,
 
 	/* ERASE2 uses the block and page address from ERASE1 */
 	case NAND_CMD_ERASE2:
-		out_be32(&ifc->ifc_nand.nand_fir0,
-			 (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
-			 (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP1_SHIFT) |
-			 (IFC_FIR_OP_CMD1 << IFC_NAND_FIR0_OP2_SHIFT));
+		ifc_out32(&ifc->ifc_nand.nand_fir0,
+			  (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
+			  (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP1_SHIFT) |
+			  (IFC_FIR_OP_CMD1 << IFC_NAND_FIR0_OP2_SHIFT));
 
-		out_be32(&ifc->ifc_nand.nand_fcr0,
-			 (NAND_CMD_ERASE1 << IFC_NAND_FCR0_CMD0_SHIFT) |
-			 (NAND_CMD_ERASE2 << IFC_NAND_FCR0_CMD1_SHIFT));
+		ifc_out32(&ifc->ifc_nand.nand_fcr0,
+			  (NAND_CMD_ERASE1 << IFC_NAND_FCR0_CMD0_SHIFT) |
+			  (NAND_CMD_ERASE2 << IFC_NAND_FCR0_CMD1_SHIFT));
 
-		out_be32(&ifc->ifc_nand.nand_fbcr, 0);
+		ifc_out32(&ifc->ifc_nand.nand_fbcr, 0);
 		ctrl->read_bytes = 0;
 		fsl_ifc_run_command(mtd);
 		return;
@@ -428,29 +491,41 @@ static void fsl_ifc_cmdfunc(struct mtd_info *mtd, unsigned int command,
 		if (mtd->writesize > 512) {
 			nand_fcr0 =
 				(NAND_CMD_SEQIN << IFC_NAND_FCR0_CMD0_SHIFT) |
-				(NAND_CMD_PAGEPROG << IFC_NAND_FCR0_CMD1_SHIFT);
-
-			out_be32(&ifc->ifc_nand.nand_fir0,
-				 (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
-				 (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) |
-				 (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP2_SHIFT) |
-				 (IFC_FIR_OP_WBCD  << IFC_NAND_FIR0_OP3_SHIFT) |
-				 (IFC_FIR_OP_CW1 << IFC_NAND_FIR0_OP4_SHIFT));
-			out_be32(&ifc->ifc_nand.nand_fir1, 0);
+				(NAND_CMD_STATUS << IFC_NAND_FCR0_CMD1_SHIFT) |
+				(NAND_CMD_PAGEPROG << IFC_NAND_FCR0_CMD2_SHIFT);
+
+			ifc_out32(&ifc->ifc_nand.nand_fir0,
+				  (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
+				  (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) |
+				  (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP2_SHIFT) |
+				  (IFC_FIR_OP_WBCD  <<
+						IFC_NAND_FIR0_OP3_SHIFT) |
+				  (IFC_FIR_OP_CMD2 << IFC_NAND_FIR0_OP4_SHIFT));
+			ifc_out32(&ifc->ifc_nand.nand_fir1,
+				  (IFC_FIR_OP_CW1 << IFC_NAND_FIR1_OP5_SHIFT) |
+				  (IFC_FIR_OP_RDSTAT <<
+					IFC_NAND_FIR1_OP6_SHIFT) |
+				  (IFC_FIR_OP_NOP << IFC_NAND_FIR1_OP7_SHIFT));
 		} else {
 			nand_fcr0 = ((NAND_CMD_PAGEPROG <<
 					IFC_NAND_FCR0_CMD1_SHIFT) |
 				    (NAND_CMD_SEQIN <<
-					IFC_NAND_FCR0_CMD2_SHIFT));
-
-			out_be32(&ifc->ifc_nand.nand_fir0,
-				 (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
-				 (IFC_FIR_OP_CMD2 << IFC_NAND_FIR0_OP1_SHIFT) |
-				 (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP2_SHIFT) |
-				 (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP3_SHIFT) |
-				 (IFC_FIR_OP_WBCD << IFC_NAND_FIR0_OP4_SHIFT));
-			out_be32(&ifc->ifc_nand.nand_fir1,
-				 (IFC_FIR_OP_CW1 << IFC_NAND_FIR1_OP5_SHIFT));
+					IFC_NAND_FCR0_CMD2_SHIFT) |
+				    (NAND_CMD_STATUS <<
+					IFC_NAND_FCR0_CMD3_SHIFT));
+
+			ifc_out32(&ifc->ifc_nand.nand_fir0,
+				  (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
+				  (IFC_FIR_OP_CMD2 << IFC_NAND_FIR0_OP1_SHIFT) |
+				  (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP2_SHIFT) |
+				  (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP3_SHIFT) |
+				  (IFC_FIR_OP_WBCD << IFC_NAND_FIR0_OP4_SHIFT));
+			ifc_out32(&ifc->ifc_nand.nand_fir1,
+				  (IFC_FIR_OP_CMD1 << IFC_NAND_FIR1_OP5_SHIFT) |
+				  (IFC_FIR_OP_CW3 << IFC_NAND_FIR1_OP6_SHIFT) |
+				  (IFC_FIR_OP_RDSTAT <<
+					IFC_NAND_FIR1_OP7_SHIFT) |
+				  (IFC_FIR_OP_NOP << IFC_NAND_FIR1_OP8_SHIFT));
 
 			if (column >= mtd->writesize)
 				nand_fcr0 |=
@@ -465,7 +540,7 @@ static void fsl_ifc_cmdfunc(struct mtd_info *mtd, unsigned int command,
 			column -= mtd->writesize;
 			ctrl->oob = 1;
 		}
-		out_be32(&ifc->ifc_nand.nand_fcr0, nand_fcr0);
+		ifc_out32(&ifc->ifc_nand.nand_fcr0, nand_fcr0);
 		set_addr(mtd, column, page_addr, ctrl->oob);
 		return;
 	}
@@ -473,21 +548,21 @@ static void fsl_ifc_cmdfunc(struct mtd_info *mtd, unsigned int command,
 	/* PAGEPROG reuses all of the setup from SEQIN and adds the length */
 	case NAND_CMD_PAGEPROG:
 		if (ctrl->oob)
-			out_be32(&ifc->ifc_nand.nand_fbcr,
-					ctrl->index - ctrl->column);
+			ifc_out32(&ifc->ifc_nand.nand_fbcr,
+				  ctrl->index - ctrl->column);
 		else
-			out_be32(&ifc->ifc_nand.nand_fbcr, 0);
+			ifc_out32(&ifc->ifc_nand.nand_fbcr, 0);
 
 		fsl_ifc_run_command(mtd);
 		return;
 
 	case NAND_CMD_STATUS:
-		out_be32(&ifc->ifc_nand.nand_fir0,
-				(IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
-				(IFC_FIR_OP_RB << IFC_NAND_FIR0_OP1_SHIFT));
-		out_be32(&ifc->ifc_nand.nand_fcr0,
-				NAND_CMD_STATUS << IFC_NAND_FCR0_CMD0_SHIFT);
-		out_be32(&ifc->ifc_nand.nand_fbcr, 1);
+		ifc_out32(&ifc->ifc_nand.nand_fir0,
+			  (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
+			  (IFC_FIR_OP_RB << IFC_NAND_FIR0_OP1_SHIFT));
+		ifc_out32(&ifc->ifc_nand.nand_fcr0,
+			  NAND_CMD_STATUS << IFC_NAND_FCR0_CMD0_SHIFT);
+		ifc_out32(&ifc->ifc_nand.nand_fbcr, 1);
 		set_addr(mtd, 0, 0, 0);
 		ctrl->read_bytes = 1;
 
@@ -498,10 +573,10 @@ static void fsl_ifc_cmdfunc(struct mtd_info *mtd, unsigned int command,
 		return;
 
 	case NAND_CMD_RESET:
-		out_be32(&ifc->ifc_nand.nand_fir0,
-				IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT);
-		out_be32(&ifc->ifc_nand.nand_fcr0,
-				NAND_CMD_RESET << IFC_NAND_FCR0_CMD0_SHIFT);
+		ifc_out32(&ifc->ifc_nand.nand_fir0,
+			  IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT);
+		ifc_out32(&ifc->ifc_nand.nand_fcr0,
+			  NAND_CMD_RESET << IFC_NAND_FCR0_CMD0_SHIFT);
 		fsl_ifc_run_command(mtd);
 		return;
 
@@ -573,8 +648,8 @@ static uint8_t fsl_ifc_read_byte16(struct mtd_info *mtd)
 	 * next byte.
 	 */
 	if (ctrl->index < ctrl->read_bytes) {
-		data = in_be16((uint16_t *)&ctrl->
-					addr[ctrl->index]);
+		data = ifc_in16((uint16_t *)&ctrl->
+				 addr[ctrl->index]);
 		ctrl->index += 2;
 		return (uint8_t)data;
 	}
@@ -653,12 +728,12 @@ static int fsl_ifc_wait(struct mtd_info *mtd, struct nand_chip *chip)
 		return NAND_STATUS_FAIL;
 
 	/* Use READ_STATUS command, but wait for the device to be ready */
-	out_be32(&ifc->ifc_nand.nand_fir0,
-		 (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
-		 (IFC_FIR_OP_RDSTAT << IFC_NAND_FIR0_OP1_SHIFT));
-	out_be32(&ifc->ifc_nand.nand_fcr0, NAND_CMD_STATUS <<
-			IFC_NAND_FCR0_CMD0_SHIFT);
-	out_be32(&ifc->ifc_nand.nand_fbcr, 1);
+	ifc_out32(&ifc->ifc_nand.nand_fir0,
+		  (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
+		  (IFC_FIR_OP_RDSTAT << IFC_NAND_FIR0_OP1_SHIFT));
+	ifc_out32(&ifc->ifc_nand.nand_fcr0, NAND_CMD_STATUS <<
+		  IFC_NAND_FCR0_CMD0_SHIFT);
+	ifc_out32(&ifc->ifc_nand.nand_fbcr, 1);
 	set_addr(mtd, 0, 0, 0);
 	ctrl->read_bytes = 1;
 
@@ -667,7 +742,7 @@ static int fsl_ifc_wait(struct mtd_info *mtd, struct nand_chip *chip)
 	if (ctrl->status != IFC_NAND_EVTER_STAT_OPC)
 		return NAND_STATUS_FAIL;
 
-	nand_fsr = in_be32(&ifc->ifc_nand.nand_fsr);
+	nand_fsr = ifc_in32(&ifc->ifc_nand.nand_fsr);
 
 	/* Chip sometimes reporting write protect even when it's not */
 	nand_fsr = nand_fsr | NAND_STATUS_WP;
@@ -710,17 +785,17 @@ static void fsl_ifc_ctrl_init(void)
 	ifc_ctrl->regs = IFC_BASE_ADDR;
 
 	/* clear event registers */
-	out_be32(&ifc_ctrl->regs->ifc_nand.nand_evter_stat, ~0U);
-	out_be32(&ifc_ctrl->regs->ifc_nand.pgrdcmpl_evt_stat, ~0U);
+	ifc_out32(&ifc_ctrl->regs->ifc_nand.nand_evter_stat, ~0U);
+	ifc_out32(&ifc_ctrl->regs->ifc_nand.pgrdcmpl_evt_stat, ~0U);
 
 	/* Enable error and event for any detected errors */
-	out_be32(&ifc_ctrl->regs->ifc_nand.nand_evter_en,
-			IFC_NAND_EVTER_EN_OPC_EN |
-			IFC_NAND_EVTER_EN_PGRDCMPL_EN |
-			IFC_NAND_EVTER_EN_FTOER_EN |
-			IFC_NAND_EVTER_EN_WPER_EN);
+	ifc_out32(&ifc_ctrl->regs->ifc_nand.nand_evter_en,
+		  IFC_NAND_EVTER_EN_OPC_EN |
+		  IFC_NAND_EVTER_EN_PGRDCMPL_EN |
+		  IFC_NAND_EVTER_EN_FTOER_EN |
+		  IFC_NAND_EVTER_EN_WPER_EN);
 
-	out_be32(&ifc_ctrl->regs->ifc_nand.ncfgr, 0x0);
+	ifc_out32(&ifc_ctrl->regs->ifc_nand.ncfgr, 0x0);
 }
 
 static void fsl_ifc_select_chip(struct mtd_info *mtd, int chip)
@@ -736,50 +811,50 @@ static void fsl_ifc_sram_init(void)
 	cs = ifc_ctrl->cs_nand >> IFC_NAND_CSEL_SHIFT;
 
 	/* Save CSOR and CSOR_ext */
-	csor = in_be32(&ifc_ctrl->regs->csor_cs[cs].csor);
-	csor_ext = in_be32(&ifc_ctrl->regs->csor_cs[cs].csor_ext);
+	csor = ifc_in32(&ifc_ctrl->regs->csor_cs[cs].csor);
+	csor_ext = ifc_in32(&ifc_ctrl->regs->csor_cs[cs].csor_ext);
 
 	/* chage PageSize 8K and SpareSize 1K*/
 	csor_8k = (csor & ~(CSOR_NAND_PGS_MASK)) | 0x0018C000;
-	out_be32(&ifc_ctrl->regs->csor_cs[cs].csor, csor_8k);
-	out_be32(&ifc_ctrl->regs->csor_cs[cs].csor_ext, 0x0000400);
+	ifc_out32(&ifc_ctrl->regs->csor_cs[cs].csor, csor_8k);
+	ifc_out32(&ifc_ctrl->regs->csor_cs[cs].csor_ext, 0x0000400);
 
 	/* READID */
-	out_be32(&ifc->ifc_nand.nand_fir0,
-			(IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
-			(IFC_FIR_OP_UA  << IFC_NAND_FIR0_OP1_SHIFT) |
-			(IFC_FIR_OP_RB << IFC_NAND_FIR0_OP2_SHIFT));
-	out_be32(&ifc->ifc_nand.nand_fcr0,
-			NAND_CMD_READID << IFC_NAND_FCR0_CMD0_SHIFT);
-	out_be32(&ifc->ifc_nand.row3, 0x0);
+	ifc_out32(&ifc->ifc_nand.nand_fir0,
+		  (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
+		  (IFC_FIR_OP_UA  << IFC_NAND_FIR0_OP1_SHIFT) |
+		  (IFC_FIR_OP_RB << IFC_NAND_FIR0_OP2_SHIFT));
+	ifc_out32(&ifc->ifc_nand.nand_fcr0,
+		  NAND_CMD_READID << IFC_NAND_FCR0_CMD0_SHIFT);
+	ifc_out32(&ifc->ifc_nand.row3, 0x0);
 
-	out_be32(&ifc->ifc_nand.nand_fbcr, 0x0);
+	ifc_out32(&ifc->ifc_nand.nand_fbcr, 0x0);
 
 	/* Program ROW0/COL0 */
-	out_be32(&ifc->ifc_nand.row0, 0x0);
-	out_be32(&ifc->ifc_nand.col0, 0x0);
+	ifc_out32(&ifc->ifc_nand.row0, 0x0);
+	ifc_out32(&ifc->ifc_nand.col0, 0x0);
 
 	/* set the chip select for NAND Transaction */
-	out_be32(&ifc->ifc_nand.nand_csel, ifc_ctrl->cs_nand);
+	ifc_out32(&ifc->ifc_nand.nand_csel, ifc_ctrl->cs_nand);
 
 	/* start read seq */
-	out_be32(&ifc->ifc_nand.nandseq_strt, IFC_NAND_SEQ_STRT_FIR_STRT);
+	ifc_out32(&ifc->ifc_nand.nandseq_strt, IFC_NAND_SEQ_STRT_FIR_STRT);
 
 	/* wait for NAND Machine complete flag or timeout */
 	end_tick = usec2ticks(IFC_TIMEOUT_MSECS * 1000) + get_ticks();
 
 	while (end_tick > get_ticks()) {
-		ifc_ctrl->status = in_be32(&ifc->ifc_nand.nand_evter_stat);
+		ifc_ctrl->status = ifc_in32(&ifc->ifc_nand.nand_evter_stat);
 
 		if (ifc_ctrl->status & IFC_NAND_EVTER_STAT_OPC)
 			break;
 	}
 
-	out_be32(&ifc->ifc_nand.nand_evter_stat, ifc_ctrl->status);
+	ifc_out32(&ifc->ifc_nand.nand_evter_stat, ifc_ctrl->status);
 
 	/* Restore CSOR and CSOR_ext */
-	out_be32(&ifc_ctrl->regs->csor_cs[cs].csor, csor);
-	out_be32(&ifc_ctrl->regs->csor_cs[cs].csor_ext, csor_ext);
+	ifc_out32(&ifc_ctrl->regs->csor_cs[cs].csor, csor);
+	ifc_out32(&ifc_ctrl->regs->csor_cs[cs].csor_ext, csor_ext);
 }
 
 static int fsl_ifc_chip_init(int devnum, u8 *addr)
@@ -809,8 +884,8 @@ static int fsl_ifc_chip_init(int devnum, u8 *addr)
 	for (priv->bank = 0; priv->bank < MAX_BANKS; priv->bank++) {
 		phys_addr_t phys_addr = virt_to_phys(addr);
 
-		cspr = in_be32(&ifc_ctrl->regs->cspr_cs[priv->bank].cspr);
-		csor = in_be32(&ifc_ctrl->regs->csor_cs[priv->bank].csor);
+		cspr = ifc_in32(&ifc_ctrl->regs->cspr_cs[priv->bank].cspr);
+		csor = ifc_in32(&ifc_ctrl->regs->csor_cs[priv->bank].csor);
 
 		if ((cspr & CSPR_V) && (cspr & CSPR_MSEL) == CSPR_MSEL_NAND &&
 		    (cspr & CSPR_BA) == CSPR_PHYS_ADDR(phys_addr)) {
@@ -902,6 +977,21 @@ static int fsl_ifc_chip_init(int devnum, u8 *addr)
 		priv->bufnum_mask = 1;
 		break;
 
+	case CSOR_NAND_PGS_8K:
+		if ((csor & CSOR_NAND_ECC_MODE_MASK) ==
+		    CSOR_NAND_ECC_MODE_4) {
+			layout = &oob_8192_ecc4;
+			nand->ecc.strength = 4;
+		} else {
+			layout = &oob_8192_ecc8;
+			nand->ecc.strength = 8;
+			nand->ecc.bytes = 16;
+		}
+
+		priv->bufnum_mask = 0;
+		break;
+
+
 	default:
 		printf("ifc nand: bad csor %#x: bad page size\n", csor);
 		return -ENODEV;
@@ -915,7 +1005,7 @@ static int fsl_ifc_chip_init(int devnum, u8 *addr)
 		nand->ecc.mode = NAND_ECC_SOFT;
 	}
 
-	ver = in_be32(&ifc_ctrl->regs->ifc_rev);
+	ver = ifc_in32(&ifc_ctrl->regs->ifc_rev);
 	if (ver == FSL_IFC_V1_1_0)
 		fsl_ifc_sram_init();
 
diff --git a/drivers/mtd/nand/fsl_ifc_spl.c b/drivers/mtd/nand/fsl_ifc_spl.c
index d4622653fa..2f82f7c5c6 100644
--- a/drivers/mtd/nand/fsl_ifc_spl.c
+++ b/drivers/mtd/nand/fsl_ifc_spl.c
@@ -9,7 +9,7 @@
 
 #include <common.h>
 #include <asm/io.h>
-#include <asm/fsl_ifc.h>
+#include <fsl_ifc.h>
 #include <linux/mtd/nand.h>
 
 static inline int is_blank(uchar *addr, int page_size)
@@ -60,7 +60,7 @@ static inline void nand_wait(uchar *buf, int bufnum, int page_size)
 	bufnum_end = bufnum + bufperpage - 1;
 
 	do {
-		status = in_be32(&ifc->ifc_nand.nand_evter_stat);
+		status = ifc_in32(&ifc->ifc_nand.nand_evter_stat);
 	} while (!(status & IFC_NAND_EVTER_STAT_OPC));
 
 	if (status & IFC_NAND_EVTER_STAT_FTOER) {
@@ -70,14 +70,14 @@ static inline void nand_wait(uchar *buf, int bufnum, int page_size)
 	}
 
 	for (i = bufnum / 4; i <= bufnum_end / 4; i++)
-		eccstat[i] = in_be32(&ifc->ifc_nand.nand_eccstat[i]);
+		eccstat[i] = ifc_in32(&ifc->ifc_nand.nand_eccstat[i]);
 
 	for (i = bufnum; i <= bufnum_end; i++) {
 		if (check_read_ecc(buf, eccstat, i, page_size))
 			break;
 	}
 
-	out_be32(&ifc->ifc_nand.nand_evter_stat, status);
+	ifc_out32(&ifc->ifc_nand.nand_evter_stat, status);
 }
 
 static inline int bad_block(uchar *marker, int port_size)
@@ -88,7 +88,11 @@ static inline int bad_block(uchar *marker, int port_size)
 		return __raw_readw((u16 *)marker) != 0xffff;
 }
 
-static void nand_load(unsigned int offs, int uboot_size, uchar *dst)
+#ifdef CONFIG_TPL_BUILD
+int nand_spl_load_image(uint32_t offs, unsigned int uboot_size, void *vdst)
+#else
+static int nand_load(uint32_t offs, unsigned int uboot_size, void *vdst)
+#endif
 {
 	struct fsl_ifc *ifc = IFC_BASE_ADDR;
 	uchar *buf = (uchar *)CONFIG_SYS_NAND_BASE;
@@ -105,6 +109,7 @@ static void nand_load(unsigned int offs, int uboot_size, uchar *dst)
 
 	int sram_addr;
 	int pg_no;
+	uchar *dst = vdst;
 
 	/* Get NAND Flash configuration */
 	csor = CONFIG_SYS_NAND_CSOR;
@@ -112,10 +117,13 @@ static void nand_load(unsigned int offs, int uboot_size, uchar *dst)
 
 	port_size = (cspr & CSPR_PORT_SIZE_16) ? 16 : 8;
 
-	if (csor & CSOR_NAND_PGS_4K) {
+	if ((csor & CSOR_NAND_PGS_MASK) == CSOR_NAND_PGS_8K) {
+		page_size = 8192;
+		bufnum_mask = 0x0;
+	} else if ((csor & CSOR_NAND_PGS_MASK) == CSOR_NAND_PGS_4K) {
 		page_size = 4096;
 		bufnum_mask = 0x1;
-	} else if (csor & CSOR_NAND_PGS_2K) {
+	} else if ((csor & CSOR_NAND_PGS_MASK) == CSOR_NAND_PGS_2K) {
 		page_size = 2048;
 		bufnum_mask = 0x3;
 	} else {
@@ -132,38 +140,38 @@ static void nand_load(unsigned int offs, int uboot_size, uchar *dst)
 	blk_size = pages_per_blk * page_size;
 
 	/* Open Full SRAM mapping for spare are access */
-	out_be32(&ifc->ifc_nand.ncfgr, 0x0);
+	ifc_out32(&ifc->ifc_nand.ncfgr, 0x0);
 
 	/* Clear Boot events */
-	out_be32(&ifc->ifc_nand.nand_evter_stat, 0xffffffff);
+	ifc_out32(&ifc->ifc_nand.nand_evter_stat, 0xffffffff);
 
 	/* Program FIR/FCR for Large/Small page */
 	if (page_size > 512) {
-		out_be32(&ifc->ifc_nand.nand_fir0,
-			 (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
-			 (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) |
-			 (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP2_SHIFT) |
-			 (IFC_FIR_OP_CMD1 << IFC_NAND_FIR0_OP3_SHIFT) |
-			 (IFC_FIR_OP_BTRD << IFC_NAND_FIR0_OP4_SHIFT));
-		out_be32(&ifc->ifc_nand.nand_fir1, 0x0);
-
-		out_be32(&ifc->ifc_nand.nand_fcr0,
-			 (NAND_CMD_READ0 << IFC_NAND_FCR0_CMD0_SHIFT) |
-			 (NAND_CMD_READSTART << IFC_NAND_FCR0_CMD1_SHIFT));
+		ifc_out32(&ifc->ifc_nand.nand_fir0,
+			  (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
+			  (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) |
+			  (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP2_SHIFT) |
+			  (IFC_FIR_OP_CMD1 << IFC_NAND_FIR0_OP3_SHIFT) |
+			  (IFC_FIR_OP_BTRD << IFC_NAND_FIR0_OP4_SHIFT));
+		ifc_out32(&ifc->ifc_nand.nand_fir1, 0x0);
+
+		ifc_out32(&ifc->ifc_nand.nand_fcr0,
+			  (NAND_CMD_READ0 << IFC_NAND_FCR0_CMD0_SHIFT) |
+			  (NAND_CMD_READSTART << IFC_NAND_FCR0_CMD1_SHIFT));
 	} else {
-		out_be32(&ifc->ifc_nand.nand_fir0,
-			 (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
-			 (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) |
-			 (IFC_FIR_OP_RA0  << IFC_NAND_FIR0_OP2_SHIFT) |
-			 (IFC_FIR_OP_BTRD << IFC_NAND_FIR0_OP3_SHIFT));
-		out_be32(&ifc->ifc_nand.nand_fir1, 0x0);
-
-		out_be32(&ifc->ifc_nand.nand_fcr0,
-			 NAND_CMD_READ0 << IFC_NAND_FCR0_CMD0_SHIFT);
+		ifc_out32(&ifc->ifc_nand.nand_fir0,
+			  (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
+			  (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) |
+			  (IFC_FIR_OP_RA0  << IFC_NAND_FIR0_OP2_SHIFT) |
+			  (IFC_FIR_OP_BTRD << IFC_NAND_FIR0_OP3_SHIFT));
+		ifc_out32(&ifc->ifc_nand.nand_fir1, 0x0);
+
+		ifc_out32(&ifc->ifc_nand.nand_fcr0,
+			  NAND_CMD_READ0 << IFC_NAND_FCR0_CMD0_SHIFT);
 	}
 
 	/* Program FBCR = 0 for full page read */
-	out_be32(&ifc->ifc_nand.nand_fbcr, 0);
+	ifc_out32(&ifc->ifc_nand.nand_fbcr, 0);
 
 	/* Read and copy u-boot on SDRAM from NAND device, In parallel
 	 * check for Bad block if found skip it and read continue to
@@ -176,11 +184,11 @@ static void nand_load(unsigned int offs, int uboot_size, uchar *dst)
 			bufnum = pg_no & bufnum_mask;
 			sram_addr = bufnum * page_size * 2;
 
-			out_be32(&ifc->ifc_nand.row0, pg_no);
-			out_be32(&ifc->ifc_nand.col0, 0);
+			ifc_out32(&ifc->ifc_nand.row0, pg_no);
+			ifc_out32(&ifc->ifc_nand.col0, 0);
 			/* start read */
-			out_be32(&ifc->ifc_nand.nandseq_strt,
-				 IFC_NAND_SEQ_STRT_FIR_STRT);
+			ifc_out32(&ifc->ifc_nand.nandseq_strt,
+				  IFC_NAND_SEQ_STRT_FIR_STRT);
 
 			/* wait for read to complete */
 			nand_wait(&buf[sram_addr], bufnum, page_size);
@@ -205,9 +213,20 @@ static void nand_load(unsigned int offs, int uboot_size, uchar *dst)
 			offs += page_size;
 		} while ((offs & (blk_size - 1)) && (pos < uboot_size));
 	}
+
+	return 0;
 }
 
 /*
+ * Defines a static function nand_load_image() here, because non-static makes
+ * the code too large for certain SPLs(minimal SPL, maximum size <= 4Kbytes)
+ */
+#ifndef CONFIG_TPL_BUILD
+#define nand_spl_load_image(offs, uboot_size, vdst) \
+	nand_load(offs, uboot_size, vdst)
+#endif
+
+/*
  * Main entrypoint for NAND Boot. It's necessary that SDRAM is already
  * configured and available since this code loads the main U-boot image
  * from NAND into SDRAM and starts from there.
@@ -218,16 +237,17 @@ void nand_boot(void)
 	/*
 	 * Load U-Boot image from NAND into RAM
 	 */
-	nand_load(CONFIG_SYS_NAND_U_BOOT_OFFS, CONFIG_SYS_NAND_U_BOOT_SIZE,
-		  (uchar *)CONFIG_SYS_NAND_U_BOOT_DST);
+	nand_spl_load_image(CONFIG_SYS_NAND_U_BOOT_OFFS,
+			    CONFIG_SYS_NAND_U_BOOT_SIZE,
+			    (uchar *)CONFIG_SYS_NAND_U_BOOT_DST);
 
 #ifdef CONFIG_NAND_ENV_DST
-	nand_load(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
-		  (uchar *)CONFIG_NAND_ENV_DST);
+	nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
+			    (uchar *)CONFIG_NAND_ENV_DST);
 
 #ifdef CONFIG_ENV_OFFSET_REDUND
-	nand_load(CONFIG_ENV_OFFSET_REDUND, CONFIG_ENV_SIZE,
-		  (uchar *)CONFIG_NAND_ENV_DST + CONFIG_ENV_SIZE);
+	nand_spl_load_image(CONFIG_ENV_OFFSET_REDUND, CONFIG_ENV_SIZE,
+			    (uchar *)CONFIG_NAND_ENV_DST + CONFIG_ENV_SIZE);
 #endif
 #endif
 	/*
diff --git a/drivers/mtd/nand/fsl_nfc.c b/drivers/mtd/nand/fsl_nfc.c
new file mode 100644
index 0000000000..6a257e696b
--- /dev/null
+++ b/drivers/mtd/nand/fsl_nfc.c
@@ -0,0 +1,670 @@
+/*
+ * Copyright 2009-2014 Freescale Semiconductor, Inc. and others
+ *
+ * Description: MPC5125, VF610, MCF54418 and Kinetis K70 Nand driver.
+ * Ported to U-Boot by Stefan Agner
+ * Based on RFC driver posted on Kernel Mailing list by Bill Pringlemeir
+ * Jason ported to M54418TWR and MVFA5.
+ * Authors: Stefan Agner <stefan.agner@toradex.com>
+ *          Bill Pringlemeir <bpringlemeir@nbsps.com>
+ *          Shaohui Xie <b21989@freescale.com>
+ *          Jason Jin <Jason.jin@freescale.com>
+ *
+ * Based on original driver mpc5121_nfc.c.
+ *
+ * This is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * Limitations:
+ * - Untested on MPC5125 and M54418.
+ * - DMA not used.
+ * - 2K pages or less.
+ * - Only 2K page w. 64+OOB and hardware ECC.
+ */
+
+#include <common.h>
+#include <malloc.h>
+
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/nand.h>
+#include <linux/mtd/partitions.h>
+
+#include <nand.h>
+#include <errno.h>
+#include <asm/io.h>
+#include <asm/processor.h>
+
+#define	DRV_NAME		"fsl_nfc"
+
+/* Register Offsets */
+#define NFC_FLASH_CMD1			0x3F00
+#define NFC_FLASH_CMD2			0x3F04
+#define NFC_COL_ADDR			0x3F08
+#define NFC_ROW_ADDR			0x3F0c
+#define NFC_ROW_ADDR_INC		0x3F14
+#define NFC_FLASH_STATUS1		0x3F18
+#define NFC_FLASH_STATUS2		0x3F1c
+#define NFC_CACHE_SWAP			0x3F28
+#define NFC_SECTOR_SIZE			0x3F2c
+#define NFC_FLASH_CONFIG		0x3F30
+#define NFC_IRQ_STATUS			0x3F38
+
+/* Addresses for NFC MAIN RAM BUFFER areas */
+#define NFC_MAIN_AREA(n)		((n) *  0x1000)
+
+#define PAGE_2K				0x0800
+#define OOB_64				0x0040
+
+/* NFC_CMD2[CODE] values. See section:
+    - 31.4.7 Flash Command Code Description, Vybrid manual
+    - 23.8.6 Flash Command Sequencer, MPC5125 manual
+
+    Briefly these are bitmasks of controller cycles.
+*/
+#define READ_PAGE_CMD_CODE		0x7EE0
+#define PROGRAM_PAGE_CMD_CODE	0x7FC0
+#define ERASE_CMD_CODE			0x4EC0
+#define READ_ID_CMD_CODE		0x4804
+#define RESET_CMD_CODE			0x4040
+#define STATUS_READ_CMD_CODE	0x4068
+
+/* NFC ECC mode define */
+#define ECC_BYPASS			0
+#define ECC_45_BYTE			6
+
+/*** Register Mask and bit definitions */
+
+/* NFC_FLASH_CMD1 Field */
+#define CMD_BYTE2_MASK				0xFF000000
+#define CMD_BYTE2_SHIFT				24
+
+/* NFC_FLASH_CM2 Field */
+#define CMD_BYTE1_MASK				0xFF000000
+#define CMD_BYTE1_SHIFT				24
+#define CMD_CODE_MASK				0x00FFFF00
+#define CMD_CODE_SHIFT				8
+#define BUFNO_MASK				0x00000006
+#define BUFNO_SHIFT				1
+#define START_BIT				(1<<0)
+
+/* NFC_COL_ADDR Field */
+#define COL_ADDR_MASK				0x0000FFFF
+#define COL_ADDR_SHIFT				0
+
+/* NFC_ROW_ADDR Field */
+#define ROW_ADDR_MASK				0x00FFFFFF
+#define ROW_ADDR_SHIFT				0
+#define ROW_ADDR_CHIP_SEL_RB_MASK		0xF0000000
+#define ROW_ADDR_CHIP_SEL_RB_SHIFT		28
+#define ROW_ADDR_CHIP_SEL_MASK			0x0F000000
+#define ROW_ADDR_CHIP_SEL_SHIFT			24
+
+/* NFC_FLASH_STATUS2 Field */
+#define STATUS_BYTE1_MASK			0x000000FF
+
+/* NFC_FLASH_CONFIG Field */
+#define CONFIG_ECC_SRAM_ADDR_MASK		0x7FC00000
+#define CONFIG_ECC_SRAM_ADDR_SHIFT		22
+#define CONFIG_ECC_SRAM_REQ_BIT			(1<<21)
+#define CONFIG_DMA_REQ_BIT			(1<<20)
+#define CONFIG_ECC_MODE_MASK			0x000E0000
+#define CONFIG_ECC_MODE_SHIFT			17
+#define CONFIG_FAST_FLASH_BIT			(1<<16)
+#define CONFIG_16BIT				(1<<7)
+#define CONFIG_BOOT_MODE_BIT			(1<<6)
+#define CONFIG_ADDR_AUTO_INCR_BIT		(1<<5)
+#define CONFIG_BUFNO_AUTO_INCR_BIT		(1<<4)
+#define CONFIG_PAGE_CNT_MASK			0xF
+#define CONFIG_PAGE_CNT_SHIFT			0
+
+/* NFC_IRQ_STATUS Field */
+#define IDLE_IRQ_BIT				(1<<29)
+#define IDLE_EN_BIT				(1<<20)
+#define CMD_DONE_CLEAR_BIT			(1<<18)
+#define IDLE_CLEAR_BIT				(1<<17)
+
+#define NFC_TIMEOUT		(1000)
+
+/* ECC status placed at end of buffers. */
+#define ECC_SRAM_ADDR	((PAGE_2K+256-8) >> 3)
+#define ECC_STATUS_MASK	0x80
+#define ECC_ERR_COUNT	0x3F
+
+struct fsl_nfc {
+	struct mtd_info	  *mtd;
+	struct nand_chip   chip;
+	struct device	  *dev;
+	void __iomem	  *regs;
+	//wait_queue_head_t  irq_waitq;
+	uint               column;
+	int                spareonly;
+	int                page;
+	/* Status and ID are in alternate locations. */
+	int                alt_buf;
+#define ALT_BUF_ID   1
+#define ALT_BUF_STAT 2
+	struct clk        *clk;
+};
+//#define mtd_to_nfc(_mtd) container_of(_mtd, struct fsl_nfc, mtd)
+#define mtd_to_nfc(_mtd) (struct fsl_nfc *)((struct nand_chip *)_mtd->priv)->priv;
+
+static u8 bbt_pattern[] = {'B', 'b', 't', '0' };
+static u8 mirror_pattern[] = {'1', 't', 'b', 'B' };
+
+static struct nand_bbt_descr bbt_main_descr = {
+	.options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE |
+		   NAND_BBT_2BIT | NAND_BBT_VERSION,
+	.offs =	11,
+	.len = 4,
+	.veroffs = 15,
+	.maxblocks = 4,
+	.pattern = bbt_pattern,
+};
+
+static struct nand_bbt_descr bbt_mirror_descr = {
+	.options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE |
+		   NAND_BBT_2BIT | NAND_BBT_VERSION,
+	.offs =	11,
+	.len = 4,
+	.veroffs = 15,
+	.maxblocks = 4,
+	.pattern = mirror_pattern,
+};
+
+static struct nand_ecclayout nfc_ecc45 = {
+	.eccbytes = 45,
+	.eccpos = {19, 20, 21, 22, 23,
+		   24, 25, 26, 27, 28, 29, 30, 31,
+		   32, 33, 34, 35, 36, 37, 38, 39,
+		   40, 41, 42, 43, 44, 45, 46, 47,
+		   48, 49, 50, 51, 52, 53, 54, 55,
+		   56, 57, 58, 59, 60, 61, 62, 63},
+	.oobfree = {
+		{.offset = 8,
+		 .length = 11} }
+};
+
+static u32 nfc_read(struct mtd_info *mtd, uint reg)
+{
+	struct fsl_nfc *nfc = mtd_to_nfc(mtd);
+
+	if (reg == NFC_FLASH_STATUS1 ||
+	    reg == NFC_FLASH_STATUS2 ||
+	    reg == NFC_IRQ_STATUS)
+		return __raw_readl(nfc->regs + reg);
+	/* Gang read/writes together for most registers. */
+	else
+		return *(u32 *)(nfc->regs + reg);
+}
+
+static void nfc_write(struct mtd_info *mtd, uint reg, u32 val)
+{
+	struct fsl_nfc *nfc = mtd_to_nfc(mtd);
+
+	if (reg == NFC_FLASH_STATUS1 ||
+	    reg == NFC_FLASH_STATUS2 ||
+	    reg == NFC_IRQ_STATUS)
+		__raw_writel(val, nfc->regs + reg);
+	/* Gang read/writes together for most registers. */
+	else
+		*(u32 *)(nfc->regs + reg) = val;
+}
+
+static void nfc_set(struct mtd_info *mtd, uint reg, u32 bits)
+{
+	nfc_write(mtd, reg, nfc_read(mtd, reg) | bits);
+}
+
+static void nfc_clear(struct mtd_info *mtd, uint reg, u32 bits)
+{
+	nfc_write(mtd, reg, nfc_read(mtd, reg) & ~bits);
+}
+
+static void nfc_set_field(struct mtd_info *mtd, u32 reg,
+			  u32 mask, u32 shift, u32 val)
+{
+	nfc_write(mtd, reg, (nfc_read(mtd, reg) & (~mask)) | val << shift);
+}
+
+/* Clear flags for upcoming command */
+static void nfc_clear_status(struct mtd_info *mtd)
+{
+	nfc_set(mtd, NFC_IRQ_STATUS, CMD_DONE_CLEAR_BIT);
+	nfc_set(mtd, NFC_IRQ_STATUS, IDLE_CLEAR_BIT);
+}
+
+/* Wait for complete operation */
+static void nfc_done(struct mtd_info *mtd)
+{
+	uint start;
+
+	nfc_set(mtd, NFC_FLASH_CMD2, START_BIT);
+	barrier();
+
+	start = get_timer(0);
+
+	while (!(nfc_read(mtd, NFC_IRQ_STATUS) & IDLE_IRQ_BIT)) {
+		if (get_timer(start) > NFC_TIMEOUT)
+			printf("Timeout while waiting for BUSY.\n");
+	}
+	nfc_clear_status(mtd);
+}
+
+static u8 nfc_get_id(struct mtd_info *mtd, int col)
+{
+	u32 flash_id;
+
+	if (col < 4) {
+		flash_id = nfc_read(mtd, NFC_FLASH_STATUS1);
+		return (flash_id >> (3-col)*8) & 0xff;
+	} else {
+		flash_id = nfc_read(mtd, NFC_FLASH_STATUS2);
+		return flash_id >> 24;
+	}
+}
+
+static u8 nfc_get_status(struct mtd_info *mtd)
+{
+	return nfc_read(mtd, NFC_FLASH_STATUS2) & STATUS_BYTE1_MASK;
+}
+
+/* Single command */
+static void nfc_send_command(struct mtd_info *mtd, u32 cmd_byte1,
+			     u32 cmd_code)
+{
+	nfc_clear_status(mtd);
+
+	nfc_set_field(mtd, NFC_FLASH_CMD2, CMD_BYTE1_MASK,
+			CMD_BYTE1_SHIFT, cmd_byte1);
+
+	nfc_clear(mtd, NFC_FLASH_CMD2, BUFNO_MASK);
+
+	nfc_set_field(mtd, NFC_FLASH_CMD2, CMD_CODE_MASK,
+			CMD_CODE_SHIFT, cmd_code);
+}
+
+/* Two commands */
+static void nfc_send_commands(struct mtd_info *mtd, u32 cmd_byte1,
+			      u32 cmd_byte2, u32 cmd_code)
+{
+	nfc_send_command(mtd, cmd_byte1, cmd_code);
+
+	nfc_set_field(mtd, NFC_FLASH_CMD1, CMD_BYTE2_MASK,
+			CMD_BYTE2_SHIFT, cmd_byte2);
+}
+
+static void nfc_addr_cycle(struct mtd_info *mtd, int column, int page)
+{
+	if (column != -1) {
+		struct fsl_nfc *nfc = mtd_to_nfc(mtd);
+		if (nfc->chip.options | NAND_BUSWIDTH_16)
+			column = column/2;
+		nfc_set_field(mtd, NFC_COL_ADDR, COL_ADDR_MASK,
+			      COL_ADDR_SHIFT, column);
+	}
+	if (page != -1)
+		nfc_set_field(mtd, NFC_ROW_ADDR, ROW_ADDR_MASK,
+				ROW_ADDR_SHIFT, page);
+}
+
+/* Send command to NAND chip */
+static void nfc_command(struct mtd_info *mtd, unsigned command,
+			int column, int page)
+{
+	struct fsl_nfc *nfc = mtd_to_nfc(mtd);
+
+	nfc->column     = max(column, 0);
+	nfc->spareonly	= 0;
+	nfc->alt_buf	= 0;
+
+	switch (command) {
+	case NAND_CMD_PAGEPROG:
+		nfc->page = -1;
+		nfc_send_commands(mtd, NAND_CMD_SEQIN,
+			     command, PROGRAM_PAGE_CMD_CODE);
+		nfc_addr_cycle(mtd, column, page);
+		break;
+
+	case NAND_CMD_RESET:
+		nfc_send_command(mtd, command, RESET_CMD_CODE);
+		break;
+	/*
+	 * NFC does not support sub-page reads and writes,
+	 * so emulate them using full page transfers.
+	 */
+	case NAND_CMD_READOOB:
+		nfc->spareonly = 1;
+	case NAND_CMD_SEQIN: /* Pre-read for partial writes. */
+	case NAND_CMD_READ0:
+		column = 0;
+		/* Already read? */
+		if (nfc->page == page)
+			return;
+		nfc->page = page;
+		nfc_send_commands(mtd, NAND_CMD_READ0,
+				  NAND_CMD_READSTART, READ_PAGE_CMD_CODE);
+		nfc_addr_cycle(mtd, column, page);
+		break;
+
+	case NAND_CMD_ERASE1:
+		if (nfc->page == page)
+			nfc->page = -1;
+		nfc_send_commands(mtd, command,
+				  NAND_CMD_ERASE2, ERASE_CMD_CODE);
+		nfc_addr_cycle(mtd, column, page);
+		break;
+
+	case NAND_CMD_READID:
+		nfc->alt_buf = ALT_BUF_ID;
+		nfc_send_command(mtd, command, READ_ID_CMD_CODE);
+		break;
+
+	case NAND_CMD_STATUS:
+		nfc->alt_buf = ALT_BUF_STAT;
+		nfc_send_command(mtd, command, STATUS_READ_CMD_CODE);
+		break;
+	default:
+		return;
+	}
+
+	nfc_done(mtd);
+}
+
+static void nfc_read_spare(struct mtd_info *mtd, void *buf, int len)
+{
+	struct fsl_nfc *nfc = mtd_to_nfc(mtd);
+
+	len = min(mtd->oobsize, (uint)len);
+	if (len > 0)
+		memcpy(buf, nfc->regs + mtd->writesize, len);
+}
+
+/* Read data from NFC buffers */
+static void nfc_read_buf(struct mtd_info *mtd, u_char *buf, int len)
+{
+	struct fsl_nfc *nfc = mtd_to_nfc(mtd);
+	uint c = nfc->column;
+	uint l;
+
+	/* Handle main area */
+	if (!nfc->spareonly) {
+
+		l = min((uint)len, mtd->writesize - c);
+		nfc->column += l;
+
+		if (!nfc->alt_buf)
+			memcpy(buf, nfc->regs + NFC_MAIN_AREA(0) + c, l);
+		else
+			if (nfc->alt_buf & ALT_BUF_ID)
+				*buf = nfc_get_id(mtd, c);
+			else
+				*buf = nfc_get_status(mtd);
+		buf += l;
+		len -= l;
+	}
+
+	/* Handle spare area access */
+	if (len) {
+		nfc->column += len;
+		nfc_read_spare(mtd, buf, len);
+	}
+}
+
+/* Write data to NFC buffers */
+static void nfc_write_buf(struct mtd_info *mtd, const u_char *buf, int len)
+{
+	struct fsl_nfc *nfc = mtd_to_nfc(mtd);
+	uint c = nfc->column;
+	uint l;
+
+	l = min((uint)len, mtd->writesize + mtd->oobsize - c);
+	nfc->column += l;
+	memcpy(nfc->regs + NFC_MAIN_AREA(0) + c, buf, l);
+}
+
+/* Read byte from NFC buffers */
+static u8 nfc_read_byte(struct mtd_info *mtd)
+{
+	u8 tmp;
+	nfc_read_buf(mtd, &tmp, sizeof(tmp));
+	return tmp;
+}
+
+/* Read word from NFC buffers */
+static u16 nfc_read_word(struct mtd_info *mtd)
+{
+	u16 tmp;
+	nfc_read_buf(mtd, (u_char *)&tmp, sizeof(tmp));
+	return tmp;
+}
+
+/* If not provided, upper layers apply a fixed delay. */
+static int nfc_dev_ready(struct mtd_info *mtd)
+{
+	/* NFC handles R/B internally; always ready.  */
+	return 1;
+}
+
+/* Vybrid only.  MPC5125 has full RB and four CS. Assume boot loader
+ * has set this register for now.
+ */
+static void
+nfc_select_chip(struct mtd_info *mtd, int chip)
+{
+#ifdef CONFIG_VF610
+	nfc_set_field(mtd, NFC_ROW_ADDR, ROW_ADDR_CHIP_SEL_RB_MASK,
+		      ROW_ADDR_CHIP_SEL_RB_SHIFT, 1);
+
+	if (chip == 0)
+		nfc_set_field(mtd, NFC_ROW_ADDR, ROW_ADDR_CHIP_SEL_MASK,
+			      ROW_ADDR_CHIP_SEL_SHIFT, 1);
+	else if (chip == 1)
+		nfc_set_field(mtd, NFC_ROW_ADDR, ROW_ADDR_CHIP_SEL_MASK,
+			      ROW_ADDR_CHIP_SEL_SHIFT, 2);
+	else
+		nfc_clear(mtd, NFC_ROW_ADDR, ROW_ADDR_CHIP_SEL_MASK);
+#endif
+}
+
+/* Count the number of 0's in buff upto max_bits */
+static int count_written_bits(uint8_t *buff, int size, int max_bits)
+{
+	int k, written_bits = 0;
+
+	for (k = 0; k < size; k++) {
+		written_bits += hweight8(~buff[k]);
+		if (written_bits > max_bits)
+			break;
+	}
+
+	return written_bits;
+}
+
+static int nfc_correct_data(struct mtd_info *mtd, u_char *dat,
+				 u_char *read_ecc, u_char *calc_ecc)
+{
+	struct fsl_nfc *nfc = mtd_to_nfc(mtd);
+	u32 ecc_status;
+	u8 ecc_count;
+	int flip;
+
+	/* 
+	 * Errata: ECC status is stored at NFC_CFG[ECCADD] +4 for
+	 * little-endian and +7 for big-endian SOC.  Access as 32 bits
+	 * and use low byte.
+	 */
+	ecc_status = __raw_readl(nfc->regs + ECC_SRAM_ADDR * 8 + 4);
+	ecc_count = ecc_status & ECC_ERR_COUNT;
+	if (!(ecc_status & ECC_STATUS_MASK))
+		return ecc_count;
+
+	/* If 'ecc_count' zero or less then buffer is all 0xff or erased. */
+	flip = count_written_bits(dat, nfc->chip.ecc.size, ecc_count);
+
+	/* ECC failed. */
+	if (flip > ecc_count)
+		return -1;
+
+	/* Erased page. */
+	memset(dat, 0xff, nfc->chip.ecc.size);
+	return 0;
+}
+
+static int nfc_calculate_ecc(struct mtd_info *mtd, const u_char *dat,
+				  u_char *ecc_code)
+{
+	return 0;
+}
+
+static void nfc_enable_hwecc(struct mtd_info *mtd, int mode)
+{
+}
+
+struct nfc_config {
+	int hardware_ecc;
+	int width;
+	int flash_bbt;
+};
+
+//static int nfc_probe(struct platform_device *pdev)
+int board_nand_init(struct nand_chip *chip)
+{
+	struct fsl_nfc *nfc;
+	struct mtd_info *mtd;
+	uint chips_no = 0;
+	int err = 0;
+	int page_sz;
+	struct nfc_config cfg = {
+		.hardware_ecc = 1,
+		.width = 8,
+		.flash_bbt = 1,
+	};
+
+	if (chip->IO_ADDR_R == NULL)
+		return -1;
+
+	nfc = malloc(sizeof(*nfc));
+	if (!nfc) {
+		printf(KERN_ERR DRV_NAME ": Memory exhausted!\n");
+		return -ENOMEM;
+	}
+
+	nfc->regs = (void __iomem *)chip->IO_ADDR_R; //CONFIG_SYS_NAND_BASE;
+
+	mtd = &nand_info[chips_no++];
+	mtd->priv = chip;
+	chip->priv = nfc;
+
+	if (cfg.width == 16) {
+		chip->options |= NAND_BUSWIDTH_16;
+		nfc_set(mtd, NFC_FLASH_CONFIG, CONFIG_16BIT);
+	} else {
+		chip->options &= ~NAND_BUSWIDTH_16;
+		nfc_clear(mtd, NFC_FLASH_CONFIG, CONFIG_16BIT);
+	}
+
+	chip->dev_ready = nfc_dev_ready;
+	chip->cmdfunc = nfc_command;
+	chip->read_byte = nfc_read_byte;
+	chip->read_word = nfc_read_word;
+	chip->read_buf = nfc_read_buf;
+	chip->write_buf = nfc_write_buf;
+	chip->select_chip = nfc_select_chip;
+
+	/* Bad block options. */
+	if (cfg.flash_bbt)
+		chip->bbt_options = NAND_BBT_USE_FLASH | NAND_BBT_CREATE;
+
+	/* Default to software ECC until flash ID. */
+	nfc_set_field(mtd, NFC_FLASH_CONFIG,
+		      CONFIG_ECC_MODE_MASK,
+		      CONFIG_ECC_MODE_SHIFT, ECC_BYPASS);
+
+	chip->bbt_td = &bbt_main_descr;
+	chip->bbt_md = &bbt_mirror_descr;
+
+	page_sz = PAGE_2K + OOB_64;
+	page_sz += cfg.width == 16 ? 1 : 0;
+	nfc_write(mtd, NFC_SECTOR_SIZE, page_sz);
+
+	/* Set configuration register. */
+	nfc_clear(mtd, NFC_FLASH_CONFIG, CONFIG_ADDR_AUTO_INCR_BIT);
+	nfc_clear(mtd, NFC_FLASH_CONFIG, CONFIG_BUFNO_AUTO_INCR_BIT);
+	nfc_clear(mtd, NFC_FLASH_CONFIG, CONFIG_BOOT_MODE_BIT);
+	nfc_clear(mtd, NFC_FLASH_CONFIG, CONFIG_DMA_REQ_BIT);
+	nfc_set(mtd, NFC_FLASH_CONFIG, CONFIG_FAST_FLASH_BIT);
+
+	/* Enable Idle IRQ */
+	nfc_set(mtd, NFC_IRQ_STATUS, IDLE_EN_BIT);
+
+	/* PAGE_CNT = 1 */
+	nfc_set_field(mtd, NFC_FLASH_CONFIG, CONFIG_PAGE_CNT_MASK,
+			CONFIG_PAGE_CNT_SHIFT, 1);
+
+	/* Set ECC_STATUS offset */
+	nfc_set_field(mtd, NFC_FLASH_CONFIG,
+		      CONFIG_ECC_SRAM_ADDR_MASK,
+		      CONFIG_ECC_SRAM_ADDR_SHIFT, ECC_SRAM_ADDR);
+
+	/* first scan to find the device and get the page size */
+	if (nand_scan_ident(mtd, CONFIG_SYS_MAX_NAND_DEVICE, NULL)) {
+		err = -ENXIO;
+		goto error;
+	}
+
+	chip->ecc.mode = NAND_ECC_SOFT; /* default */
+
+	page_sz = mtd->writesize + mtd->oobsize;
+
+	/* Single buffer only, max 256 OOB minus ECC status */
+	if (page_sz > PAGE_2K + 256 - 8) {
+		dev_err(nfc->dev, "Unsupported flash size\n");
+		err = -ENXIO;
+		goto error;
+	}
+	page_sz += cfg.width == 16 ? 1 : 0;
+	nfc_write(mtd, NFC_SECTOR_SIZE, page_sz);
+
+	if (cfg.hardware_ecc) {
+		if (mtd->writesize != PAGE_2K && mtd->oobsize < 64) {
+			dev_err(nfc->dev, "Unsupported flash with hwecc\n");
+			err = -ENXIO;
+			goto error;
+		}
+
+		chip->ecc.layout = &nfc_ecc45;
+
+		/* propagate ecc.layout to mtd_info */
+		mtd->ecclayout = chip->ecc.layout;
+		chip->ecc.calculate = nfc_calculate_ecc;
+		chip->ecc.hwctl = nfc_enable_hwecc;
+		chip->ecc.correct = nfc_correct_data;
+		chip->ecc.mode = NAND_ECC_HW;
+
+		chip->ecc.bytes = 45;
+		chip->ecc.size = PAGE_2K;
+		chip->ecc.strength = 24;
+
+		/* set ECC mode to 45 bytes OOB with 24 bits correction */
+		nfc_set_field(mtd, NFC_FLASH_CONFIG,
+				CONFIG_ECC_MODE_MASK,
+				CONFIG_ECC_MODE_SHIFT, ECC_45_BYTE);
+
+		/* Enable ECC_STATUS */
+		nfc_set(mtd, NFC_FLASH_CONFIG, CONFIG_ECC_SRAM_REQ_BIT);
+
+	}
+
+	/* second phase scan */
+	if (nand_scan_tail(mtd)) {
+		err = -ENXIO;
+		goto error;
+	}
+
+	return 0;
+
+error:
+	return err;
+}
diff --git a/drivers/mtd/nand/nand_util.c b/drivers/mtd/nand/nand_util.c
index 5246bbf1ac..b292826034 100644
--- a/drivers/mtd/nand/nand_util.c
+++ b/drivers/mtd/nand/nand_util.c
@@ -14,7 +14,9 @@
  * Copyright (C) 2008 Nokia Corporation: drop_ffs() function by
  * Artem Bityutskiy <dedekind1@gmail.com> from mtd-utils
  *
- * SPDX-License-Identifier:	GPL-2.0+
+ * Copyright 2010 Freescale Semiconductor
+ *
+ * SPDX-License-Identifier:	GPL-2.0
  */
 
 #include <common.h>
@@ -313,7 +315,7 @@ int nand_unlock(struct mtd_info *mtd, loff_t start, size_t length,
 	int page;
 	struct nand_chip *chip = mtd->priv;
 
-	debug("nand_unlock%s: start: %08llx, length: %d!\n",
+	debug("nand_unlock%s: start: %08llx, length: %zd!\n",
 		allexcept ? " (allexcept)" : "", start, length);
 
 	/* select the NAND device */
diff --git a/drivers/mtd/nand/ndfc.c b/drivers/mtd/nand/ndfc.c
index 34688e9bef..5510b13c01 100644
--- a/drivers/mtd/nand/ndfc.c
+++ b/drivers/mtd/nand/ndfc.c
@@ -104,7 +104,6 @@ static void ndfc_read_buf(struct mtd_info *mtdinfo, uint8_t *buf, int len)
 		*p++ = in_be32((u32 *)(base + NDFC_DATA));
 }
 
-#ifndef CONFIG_NAND_SPL
 /*
  * Don't use these speedup functions in NAND boot image, since the image
  * has to fit into 4kByte.
@@ -148,8 +147,6 @@ static uint8_t ndfc_read_byte(struct mtd_info *mtd)
 
 }
 
-#endif /* #ifndef CONFIG_NAND_SPL */
-
 void board_nand_select_device(struct nand_chip *nand, int chip)
 {
 	/*
@@ -207,21 +204,11 @@ int board_nand_init(struct nand_chip *nand)
 	nand->options |= NAND_BUSWIDTH_16;
 #endif
 
-#ifndef CONFIG_NAND_SPL
 	nand->write_buf  = ndfc_write_buf;
 	nand->verify_buf = ndfc_verify_buf;
 	nand->read_byte = ndfc_read_byte;
 
 	chip++;
-#else
-	/*
-	 * Setup EBC (CS0 only right now)
-	 */
-	mtebc(EBC0_CFG, CONFIG_SYS_NDFC_EBC0_CFG);
-
-	mtebc(PB0CR, CONFIG_SYS_EBC_PB0CR);
-	mtebc(PB0AP, CONFIG_SYS_EBC_PB0AP);
-#endif
 
 	return 0;
 }
diff --git a/drivers/mtd/nand/omap_elm.c b/drivers/mtd/nand/omap_elm.c
new file mode 100644
index 0000000000..47b1f1bfe2
--- /dev/null
+++ b/drivers/mtd/nand/omap_elm.c
@@ -0,0 +1,196 @@
+/*
+ * (C) Copyright 2010-2011 Texas Instruments, <www.ti.com>
+ * Mansoor Ahamed <mansoor.ahamed@ti.com>
+ *
+ * BCH Error Location Module (ELM) support.
+ *
+ * NOTE:
+ * 1. Supports only continuous mode. Dont see need for page mode in uboot
+ * 2. Supports only syndrome polynomial 0. i.e. poly local variable is
+ *    always set to ELM_DEFAULT_POLY. Dont see need for other polynomial
+ *    sets in uboot
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/errno.h>
+#include <linux/mtd/omap_gpmc.h>
+#include <linux/mtd/omap_elm.h>
+#include <asm/arch/hardware.h>
+
+#define ELM_DEFAULT_POLY (0)
+
+struct elm *elm_cfg;
+
+/**
+ * elm_load_syndromes - Load BCH syndromes based on nibble selection
+ * @syndrome: BCH syndrome
+ * @nibbles:
+ * @poly: Syndrome Polynomial set to use
+ *
+ * Load BCH syndromes based on nibble selection
+ */
+static void elm_load_syndromes(u8 *syndrome, u32 nibbles, u8 poly)
+{
+	u32 *ptr;
+	u32 val;
+
+	/* reg 0 */
+	ptr = &elm_cfg->syndrome_fragments[poly].syndrome_fragment_x[0];
+	val = syndrome[0] | (syndrome[1] << 8) | (syndrome[2] << 16) |
+				(syndrome[3] << 24);
+	writel(val, ptr);
+	/* reg 1 */
+	ptr = &elm_cfg->syndrome_fragments[poly].syndrome_fragment_x[1];
+	val = syndrome[4] | (syndrome[5] << 8) | (syndrome[6] << 16) |
+				(syndrome[7] << 24);
+	writel(val, ptr);
+
+	/* BCH 8-bit with 26 nibbles (4*8=32) */
+	if (nibbles > 13) {
+		/* reg 2 */
+		ptr = &elm_cfg->syndrome_fragments[poly].syndrome_fragment_x[2];
+		val = syndrome[8] | (syndrome[9] << 8) | (syndrome[10] << 16) |
+				(syndrome[11] << 24);
+		writel(val, ptr);
+		/* reg 3 */
+		ptr = &elm_cfg->syndrome_fragments[poly].syndrome_fragment_x[3];
+		val = syndrome[12] | (syndrome[13] << 8) |
+			(syndrome[14] << 16) | (syndrome[15] << 24);
+		writel(val, ptr);
+	}
+
+	/* BCH 16-bit with 52 nibbles (7*8=56) */
+	if (nibbles > 26) {
+		/* reg 4 */
+		ptr = &elm_cfg->syndrome_fragments[poly].syndrome_fragment_x[4];
+		val = syndrome[16] | (syndrome[17] << 8) |
+			(syndrome[18] << 16) | (syndrome[19] << 24);
+		writel(val, ptr);
+
+		/* reg 5 */
+		ptr = &elm_cfg->syndrome_fragments[poly].syndrome_fragment_x[5];
+		val = syndrome[20] | (syndrome[21] << 8) |
+			(syndrome[22] << 16) | (syndrome[23] << 24);
+		writel(val, ptr);
+
+		/* reg 6 */
+		ptr = &elm_cfg->syndrome_fragments[poly].syndrome_fragment_x[6];
+		val = syndrome[24] | (syndrome[25] << 8) |
+			(syndrome[26] << 16) | (syndrome[27] << 24);
+		writel(val, ptr);
+	}
+}
+
+/**
+ * elm_check_errors - Check for BCH errors and return error locations
+ * @syndrome: BCH syndrome
+ * @nibbles:
+ * @error_count: Returns number of errrors in the syndrome
+ * @error_locations: Returns error locations (in decimal) in this array
+ *
+ * Check the provided syndrome for BCH errors and return error count
+ * and locations in the array passed. Returns -1 if error is not correctable,
+ * else returns 0
+ */
+int elm_check_error(u8 *syndrome, u32 nibbles, u32 *error_count,
+		u32 *error_locations)
+{
+	u8 poly = ELM_DEFAULT_POLY;
+	s8 i;
+	u32 location_status;
+
+	elm_load_syndromes(syndrome, nibbles, poly);
+
+	/* start processing */
+	writel((readl(&elm_cfg->syndrome_fragments[poly].syndrome_fragment_x[6])
+				| ELM_SYNDROME_FRAGMENT_6_SYNDROME_VALID),
+		&elm_cfg->syndrome_fragments[poly].syndrome_fragment_x[6]);
+
+	/* wait for processing to complete */
+	while ((readl(&elm_cfg->irqstatus) & (0x1 << poly)) != 0x1)
+		;
+	/* clear status */
+	writel((readl(&elm_cfg->irqstatus) | (0x1 << poly)),
+			&elm_cfg->irqstatus);
+
+	/* check if correctable */
+	location_status = readl(&elm_cfg->error_location[poly].location_status);
+	if (!(location_status & ELM_LOCATION_STATUS_ECC_CORRECTABLE_MASK))
+		return -1;
+
+	/* get error count */
+	*error_count = readl(&elm_cfg->error_location[poly].location_status) &
+					ELM_LOCATION_STATUS_ECC_NB_ERRORS_MASK;
+
+	for (i = 0; i < *error_count; i++) {
+		error_locations[i] =
+		     readl(&elm_cfg->error_location[poly].error_location_x[i]);
+	}
+
+	return 0;
+}
+
+
+/**
+ * elm_config - Configure ELM module
+ * @level: 4 / 8 / 16 bit BCH
+ *
+ * Configure ELM module based on BCH level.
+ * Set mode as continuous mode.
+ * Currently we are using only syndrome 0 and syndromes 1 to 6 are not used.
+ * Also, the mode is set only for syndrome 0
+ */
+int elm_config(enum bch_level level)
+{
+	u32 val;
+	u8 poly = ELM_DEFAULT_POLY;
+	u32 buffer_size = 0x7FF;
+
+	/* config size and level */
+	val = (u32)(level) & ELM_LOCATION_CONFIG_ECC_BCH_LEVEL_MASK;
+	val |= ((buffer_size << ELM_LOCATION_CONFIG_ECC_SIZE_POS) &
+				ELM_LOCATION_CONFIG_ECC_SIZE_MASK);
+	writel(val, &elm_cfg->location_config);
+
+	/* config continous mode */
+	/* enable interrupt generation for syndrome polynomial set */
+	writel((readl(&elm_cfg->irqenable) | (0x1 << poly)),
+			&elm_cfg->irqenable);
+	/* set continuous mode for the syndrome polynomial set */
+	writel((readl(&elm_cfg->page_ctrl) & ~(0x1 << poly)),
+			&elm_cfg->page_ctrl);
+
+	return 0;
+}
+
+/**
+ * elm_reset - Do a soft reset of ELM
+ *
+ * Perform a soft reset of ELM and return after reset is done.
+ */
+void elm_reset(void)
+{
+	/* initiate reset */
+	writel((readl(&elm_cfg->sysconfig) | ELM_SYSCONFIG_SOFTRESET),
+			&elm_cfg->sysconfig);
+
+	/* wait for reset complete and normal operation */
+	while ((readl(&elm_cfg->sysstatus) & ELM_SYSSTATUS_RESETDONE) !=
+		ELM_SYSSTATUS_RESETDONE)
+		;
+}
+
+/**
+ * elm_init - Initialize ELM module
+ *
+ * Initialize ELM support. Currently it does only base address init
+ * and ELM reset.
+ */
+void elm_init(void)
+{
+	elm_cfg = (struct elm *)ELM_BASE;
+	elm_reset();
+}
diff --git a/drivers/mtd/nand/omap_gpmc.c b/drivers/mtd/nand/omap_gpmc.c
index ec1787f224..881a63618c 100644
--- a/drivers/mtd/nand/omap_gpmc.c
+++ b/drivers/mtd/nand/omap_gpmc.c
@@ -9,21 +9,26 @@
 #include <asm/io.h>
 #include <asm/errno.h>
 #include <asm/arch/mem.h>
-#include <asm/arch/cpu.h>
-#include <asm/omap_gpmc.h>
+#include <linux/mtd/omap_gpmc.h>
 #include <linux/mtd/nand_ecc.h>
 #include <linux/bch.h>
 #include <linux/compiler.h>
 #include <nand.h>
-#ifdef CONFIG_AM33XX
-#include <asm/arch/elm.h>
+#include <linux/mtd/omap_elm.h>
+
+#define BADBLOCK_MARKER_LENGTH	2
+#define SECTOR_BYTES		512
+#define ECCCLEAR		(0x1 << 8)
+#define ECCRESULTREG1		(0x1 << 0)
+/* 4 bit padding to make byte aligned, 56 = 52 + 4 */
+#define BCH4_BIT_PAD		4
+
+#ifdef CONFIG_BCH
+static u8  bch8_polynomial[] = {0xef, 0x51, 0x2e, 0x09, 0xed, 0x93, 0x9a, 0xc2,
+				0x97, 0x79, 0xe5, 0x24, 0xb5};
 #endif
-
 static uint8_t cs;
-static __maybe_unused struct nand_ecclayout hw_nand_oob =
-	GPMC_NAND_HW_ECC_LAYOUT;
-static __maybe_unused struct nand_ecclayout hw_bch8_nand_oob =
-	GPMC_NAND_HW_BCH8_ECC_LAYOUT;
+static __maybe_unused struct nand_ecclayout omap_ecclayout;
 
 /*
  * omap_nand_hwcontrol - Set the address pointers corretly for the
@@ -62,21 +67,6 @@ int omap_spl_dev_ready(struct mtd_info *mtd)
 }
 #endif
 
-/*
- * omap_hwecc_init - Initialize the Hardware ECC for NAND flash in
- *                   GPMC controller
- * @mtd:        MTD device structure
- *
- */
-static void __maybe_unused omap_hwecc_init(struct nand_chip *chip)
-{
-	/*
-	 * Init ECC Control Register
-	 * Clear all ECC | Enable Reg1
-	 */
-	writel(ECCCLEAR | ECCRESULTREG1, &gpmc_cfg->ecc_control);
-	writel(ECCSIZE1 | ECCSIZE0 | ECCSIZE0SEL, &gpmc_cfg->ecc_size_config);
-}
 
 /*
  * gen_true_ecc - This function will generate true ECC value, which
@@ -158,74 +148,6 @@ static int __maybe_unused omap_correct_data(struct mtd_info *mtd, uint8_t *dat,
 }
 
 /*
- *  omap_calculate_ecc - Generate non-inverted ECC bytes.
- *
- *  Using noninverted ECC can be considered ugly since writing a blank
- *  page ie. padding will clear the ECC bytes. This is no problem as
- *  long nobody is trying to write data on the seemingly unused page.
- *  Reading an erased page will produce an ECC mismatch between
- *  generated and read ECC bytes that has to be dealt with separately.
- *  E.g. if page is 0xFF (fresh erased), and if HW ECC engine within GPMC
- *  is used, the result of read will be 0x0 while the ECC offsets of the
- *  spare area will be 0xFF which will result in an ECC mismatch.
- *  @mtd:	MTD structure
- *  @dat:	unused
- *  @ecc_code:	ecc_code buffer
- */
-static int __maybe_unused omap_calculate_ecc(struct mtd_info *mtd,
-		const uint8_t *dat, uint8_t *ecc_code)
-{
-	u_int32_t val;
-
-	/* Start Reading from HW ECC1_Result = 0x200 */
-	val = readl(&gpmc_cfg->ecc1_result);
-
-	ecc_code[0] = val & 0xFF;
-	ecc_code[1] = (val >> 16) & 0xFF;
-	ecc_code[2] = ((val >> 8) & 0x0F) | ((val >> 20) & 0xF0);
-
-	/*
-	 * Stop reading anymore ECC vals and clear old results
-	 * enable will be called if more reads are required
-	 */
-	writel(0x000, &gpmc_cfg->ecc_config);
-
-	return 0;
-}
-
-/*
- * omap_enable_ecc - This function enables the hardware ecc functionality
- * @mtd:        MTD device structure
- * @mode:       Read/Write mode
- */
-static void __maybe_unused omap_enable_hwecc(struct mtd_info *mtd, int32_t mode)
-{
-	struct nand_chip *chip = mtd->priv;
-	uint32_t val, dev_width = (chip->options & NAND_BUSWIDTH_16) >> 1;
-
-	switch (mode) {
-	case NAND_ECC_READ:
-	case NAND_ECC_WRITE:
-		/* Clear the ecc result registers, select ecc reg as 1 */
-		writel(ECCCLEAR | ECCRESULTREG1, &gpmc_cfg->ecc_control);
-
-		/*
-		 * Size 0 = 0xFF, Size1 is 0xFF - both are 512 bytes
-		 * tell all regs to generate size0 sized regs
-		 * we just have a single ECC engine for all CS
-		 */
-		writel(ECCSIZE1 | ECCSIZE0 | ECCSIZE0SEL,
-			&gpmc_cfg->ecc_size_config);
-		val = (dev_width << 7) | (cs << 1) | (0x1);
-		writel(val, &gpmc_cfg->ecc_config);
-		break;
-	default:
-		printf("Error: Unrecognized Mode[%d]!\n", mode);
-		break;
-	}
-}
-
-/*
  * Generic BCH interface
  */
 struct nand_bch_priv {
@@ -233,6 +155,7 @@ struct nand_bch_priv {
 	uint8_t type;
 	uint8_t nibbles;
 	struct bch_control *control;
+	enum omap_ecc ecc_scheme;
 };
 
 /* bch types */
@@ -240,12 +163,7 @@ struct nand_bch_priv {
 #define ECC_BCH8	1
 #define ECC_BCH16	2
 
-/* GPMC ecc engine settings */
-#define BCH_WRAPMODE_1		1	/* BCH wrap mode 1 */
-#define BCH_WRAPMODE_6		6	/* BCH wrap mode 6 */
-
 /* BCH nibbles for diff bch levels */
-#define NAND_ECC_HW_BCH ((uint8_t)(NAND_ECC_HW_OOB_FIRST) + 1)
 #define ECC_BCH4_NIBBLES	13
 #define ECC_BCH8_NIBBLES	26
 #define ECC_BCH16_NIBBLES	52
@@ -257,266 +175,161 @@ struct nand_bch_priv {
  * When some users with other BCH strength will exists this have to change!
  */
 static __maybe_unused struct nand_bch_priv bch_priv = {
-	.mode = NAND_ECC_HW_BCH,
 	.type = ECC_BCH8,
 	.nibbles = ECC_BCH8_NIBBLES,
 	.control = NULL
 };
 
 /*
- * omap_hwecc_init_bch - Initialize the BCH Hardware ECC for NAND flash in
- *				GPMC controller
- * @mtd:	MTD device structure
- * @mode:	Read/Write mode
- */
-__maybe_unused
-static void omap_hwecc_init_bch(struct nand_chip *chip, int32_t mode)
+ * omap_reverse_list - re-orders list elements in reverse order [internal]
+ * @list:	pointer to start of list
+ * @length:	length of list
+*/
+void omap_reverse_list(u8 *list, unsigned int length)
 {
-	uint32_t val;
-	uint32_t dev_width = (chip->options & NAND_BUSWIDTH_16) >> 1;
-#ifdef CONFIG_AM33XX
-	uint32_t unused_length = 0;
-#endif
-	uint32_t wr_mode = BCH_WRAPMODE_6;
-	struct nand_bch_priv *bch = chip->priv;
-
-	/* Clear the ecc result registers, select ecc reg as 1 */
-	writel(ECCCLEAR | ECCRESULTREG1, &gpmc_cfg->ecc_control);
-
-#ifdef CONFIG_AM33XX
-	wr_mode = BCH_WRAPMODE_1;
-
-	switch (bch->nibbles) {
-	case ECC_BCH4_NIBBLES:
-		unused_length = 3;
-		break;
-	case ECC_BCH8_NIBBLES:
-		unused_length = 2;
-		break;
-	case ECC_BCH16_NIBBLES:
-		unused_length = 0;
-		break;
-	}
-
-	/*
-	 * This is ecc_size_config for ELM mode.
-	 * Here we are using different settings for read and write access and
-	 * also depending on BCH strength.
-	 */
-	switch (mode) {
-	case NAND_ECC_WRITE:
-		/* write access only setup eccsize1 config */
-		val = ((unused_length + bch->nibbles) << 22);
-		break;
-
-	case NAND_ECC_READ:
-	default:
-		/*
-		 * by default eccsize0 selected for ecc1resultsize
-		 * eccsize0 config.
-		 */
-		val  = (bch->nibbles << 12);
-		/* eccsize1 config */
-		val |= (unused_length << 22);
-		break;
+	unsigned int i, j;
+	unsigned int half_length = length / 2;
+	u8 tmp;
+	for (i = 0, j = length - 1; i < half_length; i++, j--) {
+		tmp = list[i];
+		list[i] = list[j];
+		list[j] = tmp;
 	}
-#else
-	/*
-	 * This ecc_size_config setting is for BCH sw library.
-	 *
-	 * Note: we only support BCH8 currently with BCH sw library!
-	 * Should be really easy to adobt to BCH4, however some omap3 have
-	 * flaws with BCH4.
-	 *
-	 * Here we are using wrapping mode 6 both for reading and writing, with:
-	 *  size0 = 0  (no additional protected byte in spare area)
-	 *  size1 = 32 (skip 32 nibbles = 16 bytes per sector in spare area)
-	 */
-	val = (32 << 22) | (0 << 12);
-#endif
-	/* ecc size configuration */
-	writel(val, &gpmc_cfg->ecc_size_config);
-
-	/*
-	 * Configure the ecc engine in gpmc
-	 * We assume 512 Byte sector pages for access to NAND.
-	 */
-	val  = (1 << 16);		/* enable BCH mode */
-	val |= (bch->type << 12);	/* setup BCH type */
-	val |= (wr_mode << 8);		/* setup wrapping mode */
-	val |= (dev_width << 7);	/* setup device width (16 or 8 bit) */
-	val |= (cs << 1);		/* setup chip select to work on */
-	debug("set ECC_CONFIG=0x%08x\n", val);
-	writel(val, &gpmc_cfg->ecc_config);
 }
 
 /*
- * omap_enable_ecc_bch - This function enables the bch h/w ecc functionality
+ * omap_enable_hwecc - configures GPMC as per ECC scheme before read/write
  * @mtd:	MTD device structure
  * @mode:	Read/Write mode
  */
 __maybe_unused
-static void omap_enable_ecc_bch(struct mtd_info *mtd, int32_t mode)
+static void omap_enable_hwecc(struct mtd_info *mtd, int32_t mode)
 {
-	struct nand_chip *chip = mtd->priv;
-
-	omap_hwecc_init_bch(chip, mode);
-	/* enable ecc */
-	writel((readl(&gpmc_cfg->ecc_config) | 0x1), &gpmc_cfg->ecc_config);
-}
-
-/*
- * omap_ecc_disable - Disable H/W ECC calculation
- *
- * @mtd:	MTD device structure
- */
-static void __maybe_unused omap_ecc_disable(struct mtd_info *mtd)
-{
-	writel((readl(&gpmc_cfg->ecc_config) & ~0x1), &gpmc_cfg->ecc_config);
+	struct nand_chip	*nand	= mtd->priv;
+	struct nand_bch_priv	*bch	= nand->priv;
+	unsigned int dev_width = (nand->options & NAND_BUSWIDTH_16) ? 1 : 0;
+	unsigned int ecc_algo = 0;
+	unsigned int bch_type = 0;
+	unsigned int eccsize1 = 0x00, eccsize0 = 0x00, bch_wrapmode = 0x00;
+	u32 ecc_size_config_val = 0;
+	u32 ecc_config_val = 0;
+
+	/* configure GPMC for specific ecc-scheme */
+	switch (bch->ecc_scheme) {
+	case OMAP_ECC_HAM1_CODE_SW:
+		return;
+	case OMAP_ECC_HAM1_CODE_HW:
+		ecc_algo = 0x0;
+		bch_type = 0x0;
+		bch_wrapmode = 0x00;
+		eccsize0 = 0xFF;
+		eccsize1 = 0xFF;
+		break;
+	case OMAP_ECC_BCH8_CODE_HW_DETECTION_SW:
+	case OMAP_ECC_BCH8_CODE_HW:
+		ecc_algo = 0x1;
+		bch_type = 0x1;
+		if (mode == NAND_ECC_WRITE) {
+			bch_wrapmode = 0x01;
+			eccsize0 = 0;  /* extra bits in nibbles per sector */
+			eccsize1 = 28; /* OOB bits in nibbles per sector */
+		} else {
+			bch_wrapmode = 0x01;
+			eccsize0 = 26; /* ECC bits in nibbles per sector */
+			eccsize1 = 2;  /* non-ECC bits in nibbles per sector */
+		}
+		break;
+	default:
+		return;
+	}
+	/* Clear ecc and enable bits */
+	writel(ECCCLEAR | ECCRESULTREG1, &gpmc_cfg->ecc_control);
+	/* Configure ecc size for BCH */
+	ecc_size_config_val = (eccsize1 << 22) | (eccsize0 << 12);
+	writel(ecc_size_config_val, &gpmc_cfg->ecc_size_config);
+
+	/* Configure device details for BCH engine */
+	ecc_config_val = ((ecc_algo << 16)	| /* HAM1 | BCHx */
+			(bch_type << 12)	| /* BCH4/BCH8/BCH16 */
+			(bch_wrapmode << 8)	| /* wrap mode */
+			(dev_width << 7)	| /* bus width */
+			(0x0 << 4)		| /* number of sectors */
+			(cs <<  1)		| /* ECC CS */
+			(0x1));			  /* enable ECC */
+	writel(ecc_config_val, &gpmc_cfg->ecc_config);
 }
 
 /*
- * BCH8 support (needs ELM and thus AM33xx-only)
- */
-#ifdef CONFIG_AM33XX
-/*
- * omap_read_bch8_result - Read BCH result for BCH8 level
- *
- * @mtd:	MTD device structure
- * @big_endian:	When set read register 3 first
- * @ecc_code:	Read syndrome from BCH result registers
+ *  omap_calculate_ecc - Read ECC result
+ *  @mtd:	MTD structure
+ *  @dat:	unused
+ *  @ecc_code:	ecc_code buffer
+ *  Using noninverted ECC can be considered ugly since writing a blank
+ *  page ie. padding will clear the ECC bytes. This is no problem as
+ *  long nobody is trying to write data on the seemingly unused page.
+ *  Reading an erased page will produce an ECC mismatch between
+ *  generated and read ECC bytes that has to be dealt with separately.
+ *  E.g. if page is 0xFF (fresh erased), and if HW ECC engine within GPMC
+ *  is used, the result of read will be 0x0 while the ECC offsets of the
+ *  spare area will be 0xFF which will result in an ECC mismatch.
  */
-static void omap_read_bch8_result(struct mtd_info *mtd, uint8_t big_endian,
+static int omap_calculate_ecc(struct mtd_info *mtd, const uint8_t *dat,
 				uint8_t *ecc_code)
 {
-	uint32_t *ptr;
+	struct nand_chip *chip = mtd->priv;
+	struct nand_bch_priv *bch = chip->priv;
+	uint32_t *ptr, val = 0;
 	int8_t i = 0, j;
 
-	if (big_endian) {
+	switch (bch->ecc_scheme) {
+	case OMAP_ECC_HAM1_CODE_HW:
+		val = readl(&gpmc_cfg->ecc1_result);
+		ecc_code[0] = val & 0xFF;
+		ecc_code[1] = (val >> 16) & 0xFF;
+		ecc_code[2] = ((val >> 8) & 0x0F) | ((val >> 20) & 0xF0);
+		break;
+#ifdef CONFIG_BCH
+	case OMAP_ECC_BCH8_CODE_HW_DETECTION_SW:
+#endif
+	case OMAP_ECC_BCH8_CODE_HW:
 		ptr = &gpmc_cfg->bch_result_0_3[0].bch_result_x[3];
-		ecc_code[i++] = readl(ptr) & 0xFF;
+		val = readl(ptr);
+		ecc_code[i++] = (val >>  0) & 0xFF;
 		ptr--;
 		for (j = 0; j < 3; j++) {
-			ecc_code[i++] = (readl(ptr) >> 24) & 0xFF;
-			ecc_code[i++] = (readl(ptr) >> 16) & 0xFF;
-			ecc_code[i++] = (readl(ptr) >>  8) & 0xFF;
-			ecc_code[i++] = readl(ptr) & 0xFF;
+			val = readl(ptr);
+			ecc_code[i++] = (val >> 24) & 0xFF;
+			ecc_code[i++] = (val >> 16) & 0xFF;
+			ecc_code[i++] = (val >>  8) & 0xFF;
+			ecc_code[i++] = (val >>  0) & 0xFF;
 			ptr--;
 		}
-	} else {
-		ptr = &gpmc_cfg->bch_result_0_3[0].bch_result_x[0];
-		for (j = 0; j < 3; j++) {
-			ecc_code[i++] = readl(ptr) & 0xFF;
-			ecc_code[i++] = (readl(ptr) >>  8) & 0xFF;
-			ecc_code[i++] = (readl(ptr) >> 16) & 0xFF;
-			ecc_code[i++] = (readl(ptr) >> 24) & 0xFF;
-			ptr++;
-		}
-		ecc_code[i++] = readl(ptr) & 0xFF;
-		ecc_code[i++] = 0;	/* 14th byte is always zero */
+		break;
+	default:
+		return -EINVAL;
 	}
-}
-
-/*
- * omap_rotate_ecc_bch - Rotate the syndrome bytes
- *
- * @mtd:	MTD device structure
- * @calc_ecc:	ECC read from ECC registers
- * @syndrome:	Rotated syndrome will be retuned in this array
- *
- */
-static void omap_rotate_ecc_bch(struct mtd_info *mtd, uint8_t *calc_ecc,
-		uint8_t *syndrome)
-{
-	struct nand_chip *chip = mtd->priv;
-	struct nand_bch_priv *bch = chip->priv;
-	uint8_t n_bytes = 0;
-	int8_t i, j;
-
-	switch (bch->type) {
-	case ECC_BCH4:
-		n_bytes = 8;
+	/* ECC scheme specific syndrome customizations */
+	switch (bch->ecc_scheme) {
+	case OMAP_ECC_HAM1_CODE_HW:
 		break;
+#ifdef CONFIG_BCH
+	case OMAP_ECC_BCH8_CODE_HW_DETECTION_SW:
 
-	case ECC_BCH16:
-		n_bytes = 28;
+		for (i = 0; i < chip->ecc.bytes; i++)
+			*(ecc_code + i) = *(ecc_code + i) ^
+						bch8_polynomial[i];
 		break;
-
-	case ECC_BCH8:
-	default:
-		n_bytes = 13;
+#endif
+	case OMAP_ECC_BCH8_CODE_HW:
+		ecc_code[chip->ecc.bytes - 1] = 0x00;
 		break;
+	default:
+		return -EINVAL;
 	}
-
-	for (i = 0, j = (n_bytes-1); i < n_bytes; i++, j--)
-		syndrome[i] =  calc_ecc[j];
-}
-
-/*
- *  omap_calculate_ecc_bch - Read BCH ECC result
- *
- *  @mtd:	MTD structure
- *  @dat:	unused
- *  @ecc_code:	ecc_code buffer
- */
-static int omap_calculate_ecc_bch(struct mtd_info *mtd, const uint8_t *dat,
-				uint8_t *ecc_code)
-{
-	struct nand_chip *chip = mtd->priv;
-	struct nand_bch_priv *bch = chip->priv;
-	uint8_t big_endian = 1;
-	int8_t ret = 0;
-
-	if (bch->type == ECC_BCH8)
-		omap_read_bch8_result(mtd, big_endian, ecc_code);
-	else /* BCH4 and BCH16 currently not supported */
-		ret = -1;
-
-	/*
-	 * Stop reading anymore ECC vals and clear old results
-	 * enable will be called if more reads are required
-	 */
-	omap_ecc_disable(mtd);
-
-	return ret;
-}
-
-/*
- * omap_fix_errors_bch - Correct bch error in the data
- *
- * @mtd:	MTD device structure
- * @data:	Data read from flash
- * @error_count:Number of errors in data
- * @error_loc:	Locations of errors in the data
- *
- */
-static void omap_fix_errors_bch(struct mtd_info *mtd, uint8_t *data,
-		uint32_t error_count, uint32_t *error_loc)
-{
-	struct nand_chip *chip = mtd->priv;
-	struct nand_bch_priv *bch = chip->priv;
-	uint8_t count = 0;
-	uint32_t error_byte_pos;
-	uint32_t error_bit_mask;
-	uint32_t last_bit = (bch->nibbles * 4) - 1;
-
-	/* Flip all bits as specified by the error location array. */
-	/* FOR( each found error location flip the bit ) */
-	for (count = 0; count < error_count; count++) {
-		if (error_loc[count] > last_bit) {
-			/* Remove the ECC spare bits from correction. */
-			error_loc[count] -= (last_bit + 1);
-			/* Offset bit in data region */
-			error_byte_pos = ((512 * 8) -
-					(error_loc[count]) - 1) / 8;
-			/* Error Bit mask */
-			error_bit_mask = 0x1 << (error_loc[count] % 8);
-			/* Toggle the error bit to make the correction. */
-			data[error_byte_pos] ^= error_bit_mask;
-		}
-	}
+	return 0;
 }
 
+#ifdef CONFIG_NAND_OMAP_ELM
 /*
  * omap_correct_data_bch - Compares the ecc read from nand spare area
  * with ECC registers values and corrects one bit error if it has occured
@@ -533,40 +346,72 @@ static int omap_correct_data_bch(struct mtd_info *mtd, uint8_t *dat,
 {
 	struct nand_chip *chip = mtd->priv;
 	struct nand_bch_priv *bch = chip->priv;
-	uint8_t syndrome[28];
-	uint32_t error_count = 0;
+	uint32_t eccbytes = chip->ecc.bytes;
+	uint32_t error_count = 0, error_max;
 	uint32_t error_loc[8];
-	uint32_t i, ecc_flag;
+	uint32_t i, ecc_flag = 0;
+	uint8_t count, err = 0;
+	uint32_t byte_pos, bit_pos;
+
+	/* check calculated ecc */
+	for (i = 0; i < chip->ecc.bytes && !ecc_flag; i++) {
+		if (calc_ecc[i] != 0x00)
+			ecc_flag = 1;
+	}
+	if (!ecc_flag)
+		return 0;
 
+	/* check for whether its a erased-page */
 	ecc_flag = 0;
-	for (i = 0; i < chip->ecc.bytes; i++)
+	for (i = 0; i < chip->ecc.bytes && !ecc_flag; i++) {
 		if (read_ecc[i] != 0xff)
 			ecc_flag = 1;
-
+	}
 	if (!ecc_flag)
 		return 0;
 
-	elm_reset();
-	elm_config((enum bch_level)(bch->type));
-
 	/*
 	 * while reading ECC result we read it in big endian.
 	 * Hence while loading to ELM we have rotate to get the right endian.
 	 */
-	omap_rotate_ecc_bch(mtd, calc_ecc, syndrome);
-
+	switch (bch->ecc_scheme) {
+	case OMAP_ECC_BCH8_CODE_HW:
+		omap_reverse_list(calc_ecc, eccbytes - 1);
+		break;
+	default:
+		return -EINVAL;
+	}
 	/* use elm module to check for errors */
-	if (elm_check_error(syndrome, bch->nibbles, &error_count,
-				error_loc) != 0) {
-		printf("ECC: uncorrectable.\n");
-		return -1;
+	elm_config((enum bch_level)(bch->type));
+	if (elm_check_error(calc_ecc, bch->nibbles, &error_count, error_loc)) {
+		printf("nand: error: uncorrectable ECC errors\n");
+		return -EINVAL;
 	}
-
 	/* correct bch error */
-	if (error_count > 0)
-		omap_fix_errors_bch(mtd, dat, error_count, error_loc);
-
-	return 0;
+	for (count = 0; count < error_count; count++) {
+		switch (bch->type) {
+		case ECC_BCH8:
+			/* 14th byte in ECC is reserved to match ROM layout */
+			error_max = SECTOR_BYTES + (eccbytes - 1);
+			break;
+		default:
+			return -EINVAL;
+		}
+		byte_pos = error_max - (error_loc[count] / 8) - 1;
+		bit_pos  = error_loc[count] % 8;
+		if (byte_pos < SECTOR_BYTES) {
+			dat[byte_pos] ^= 1 << bit_pos;
+			printf("nand: bit-flip corrected @data=%d\n", byte_pos);
+		} else if (byte_pos < error_max) {
+			read_ecc[byte_pos - SECTOR_BYTES] = 1 << bit_pos;
+			printf("nand: bit-flip corrected @oob=%d\n", byte_pos -
+								SECTOR_BYTES);
+		} else {
+			err = -EBADMSG;
+			printf("nand: error: invalid bit-flip location\n");
+		}
+	}
+	return (err) ? err : error_count;
 }
 
 /**
@@ -631,71 +476,20 @@ static int omap_read_page_bch(struct mtd_info *mtd, struct nand_chip *chip,
 	}
 	return 0;
 }
-#endif /* CONFIG_AM33XX */
+#endif /* CONFIG_NAND_OMAP_ELM */
 
 /*
  * OMAP3 BCH8 support (with BCH library)
  */
-#ifdef CONFIG_NAND_OMAP_BCH8
-/*
- *  omap_calculate_ecc_bch - Read BCH ECC result
- *
- *  @mtd:	MTD device structure
- *  @dat:	The pointer to data on which ecc is computed (unused here)
- *  @ecc:	The ECC output buffer
- */
-static int omap_calculate_ecc_bch(struct mtd_info *mtd, const uint8_t *dat,
-				uint8_t *ecc)
-{
-	int ret = 0;
-	size_t i;
-	unsigned long nsectors, val1, val2, val3, val4;
-
-	nsectors = ((readl(&gpmc_cfg->ecc_config) >> 4) & 0x7) + 1;
-
-	for (i = 0; i < nsectors; i++) {
-		/* Read hw-computed remainder */
-		val1 = readl(&gpmc_cfg->bch_result_0_3[i].bch_result_x[0]);
-		val2 = readl(&gpmc_cfg->bch_result_0_3[i].bch_result_x[1]);
-		val3 = readl(&gpmc_cfg->bch_result_0_3[i].bch_result_x[2]);
-		val4 = readl(&gpmc_cfg->bch_result_0_3[i].bch_result_x[3]);
-
-		/*
-		 * Add constant polynomial to remainder, in order to get an ecc
-		 * sequence of 0xFFs for a buffer filled with 0xFFs.
-		 */
-		*ecc++ = 0xef ^ (val4 & 0xFF);
-		*ecc++ = 0x51 ^ ((val3 >> 24) & 0xFF);
-		*ecc++ = 0x2e ^ ((val3 >> 16) & 0xFF);
-		*ecc++ = 0x09 ^ ((val3 >> 8) & 0xFF);
-		*ecc++ = 0xed ^ (val3 & 0xFF);
-		*ecc++ = 0x93 ^ ((val2 >> 24) & 0xFF);
-		*ecc++ = 0x9a ^ ((val2 >> 16) & 0xFF);
-		*ecc++ = 0xc2 ^ ((val2 >> 8) & 0xFF);
-		*ecc++ = 0x97 ^ (val2 & 0xFF);
-		*ecc++ = 0x79 ^ ((val1 >> 24) & 0xFF);
-		*ecc++ = 0xe5 ^ ((val1 >> 16) & 0xFF);
-		*ecc++ = 0x24 ^ ((val1 >> 8) & 0xFF);
-		*ecc++ = 0xb5 ^ (val1 & 0xFF);
-	}
-
-	/*
-	 * Stop reading anymore ECC vals and clear old results
-	 * enable will be called if more reads are required
-	 */
-	omap_ecc_disable(mtd);
-
-	return ret;
-}
-
+#ifdef CONFIG_BCH
 /**
- * omap_correct_data_bch - Decode received data and correct errors
+ * omap_correct_data_bch_sw - Decode received data and correct errors
  * @mtd: MTD device structure
  * @data: page data
  * @read_ecc: ecc read from nand flash
  * @calc_ecc: ecc read from HW ECC registers
  */
-static int omap_correct_data_bch(struct mtd_info *mtd, u_char *data,
+static int omap_correct_data_bch_sw(struct mtd_info *mtd, u_char *data,
 				 u_char *read_ecc, u_char *calc_ecc)
 {
 	int i, count;
@@ -752,7 +546,161 @@ static void __maybe_unused omap_free_bch(struct mtd_info *mtd)
 		chip_priv->control = NULL;
 	}
 }
-#endif /* CONFIG_NAND_OMAP_BCH8 */
+#endif /* CONFIG_BCH */
+
+/**
+ * omap_select_ecc_scheme - configures driver for particular ecc-scheme
+ * @nand: NAND chip device structure
+ * @ecc_scheme: ecc scheme to configure
+ * @pagesize: number of main-area bytes per page of NAND device
+ * @oobsize: number of OOB/spare bytes per page of NAND device
+ */
+static int omap_select_ecc_scheme(struct nand_chip *nand,
+	enum omap_ecc ecc_scheme, unsigned int pagesize, unsigned int oobsize) {
+	struct nand_bch_priv	*bch		= nand->priv;
+	struct nand_ecclayout	*ecclayout	= &omap_ecclayout;
+	int eccsteps = pagesize / SECTOR_BYTES;
+	int i;
+
+	switch (ecc_scheme) {
+	case OMAP_ECC_HAM1_CODE_SW:
+		debug("nand: selected OMAP_ECC_HAM1_CODE_SW\n");
+		/* For this ecc-scheme, ecc.bytes, ecc.layout, ... are
+		 * initialized in nand_scan_tail(), so just set ecc.mode */
+		bch_priv.control	= NULL;
+		bch_priv.type		= 0;
+		nand->ecc.mode		= NAND_ECC_SOFT;
+		nand->ecc.layout	= NULL;
+		nand->ecc.size		= 0;
+		bch->ecc_scheme		= OMAP_ECC_HAM1_CODE_SW;
+		break;
+
+	case OMAP_ECC_HAM1_CODE_HW:
+		debug("nand: selected OMAP_ECC_HAM1_CODE_HW\n");
+		/* check ecc-scheme requirements before updating ecc info */
+		if ((3 * eccsteps) + BADBLOCK_MARKER_LENGTH > oobsize) {
+			printf("nand: error: insufficient OOB: require=%d\n", (
+				(3 * eccsteps) + BADBLOCK_MARKER_LENGTH));
+			return -EINVAL;
+		}
+		bch_priv.control	= NULL;
+		bch_priv.type		= 0;
+		/* populate ecc specific fields */
+		memset(&nand->ecc, 0, sizeof(struct nand_ecc_ctrl));
+		nand->ecc.mode		= NAND_ECC_HW;
+		nand->ecc.strength	= 1;
+		nand->ecc.size		= SECTOR_BYTES;
+		nand->ecc.bytes		= 3;
+		nand->ecc.hwctl		= omap_enable_hwecc;
+		nand->ecc.correct	= omap_correct_data;
+		nand->ecc.calculate	= omap_calculate_ecc;
+		/* define ecc-layout */
+		ecclayout->eccbytes	= nand->ecc.bytes * eccsteps;
+		for (i = 0; i < ecclayout->eccbytes; i++) {
+			if (nand->options & NAND_BUSWIDTH_16)
+				ecclayout->eccpos[i] = i + 2;
+			else
+				ecclayout->eccpos[i] = i + 1;
+		}
+		ecclayout->oobfree[0].offset = i + BADBLOCK_MARKER_LENGTH;
+		ecclayout->oobfree[0].length = oobsize - ecclayout->eccbytes -
+						BADBLOCK_MARKER_LENGTH;
+		bch->ecc_scheme		= OMAP_ECC_HAM1_CODE_HW;
+		break;
+
+	case OMAP_ECC_BCH8_CODE_HW_DETECTION_SW:
+#ifdef CONFIG_BCH
+		debug("nand: selected OMAP_ECC_BCH8_CODE_HW_DETECTION_SW\n");
+		/* check ecc-scheme requirements before updating ecc info */
+		if ((13 * eccsteps) + BADBLOCK_MARKER_LENGTH > oobsize) {
+			printf("nand: error: insufficient OOB: require=%d\n", (
+				(13 * eccsteps) + BADBLOCK_MARKER_LENGTH));
+			return -EINVAL;
+		}
+		/* check if BCH S/W library can be used for error detection */
+		bch_priv.control = init_bch(13, 8, 0x201b);
+		if (!bch_priv.control) {
+			printf("nand: error: could not init_bch()\n");
+			return -ENODEV;
+		}
+		bch_priv.type = ECC_BCH8;
+		/* populate ecc specific fields */
+		memset(&nand->ecc, 0, sizeof(struct nand_ecc_ctrl));
+		nand->ecc.mode		= NAND_ECC_HW;
+		nand->ecc.strength	= 8;
+		nand->ecc.size		= SECTOR_BYTES;
+		nand->ecc.bytes		= 13;
+		nand->ecc.hwctl		= omap_enable_hwecc;
+		nand->ecc.correct	= omap_correct_data_bch_sw;
+		nand->ecc.calculate	= omap_calculate_ecc;
+		/* define ecc-layout */
+		ecclayout->eccbytes	= nand->ecc.bytes * eccsteps;
+		ecclayout->eccpos[0]	= BADBLOCK_MARKER_LENGTH;
+		for (i = 1; i < ecclayout->eccbytes; i++) {
+			if (i % nand->ecc.bytes)
+				ecclayout->eccpos[i] =
+						ecclayout->eccpos[i - 1] + 1;
+			else
+				ecclayout->eccpos[i] =
+						ecclayout->eccpos[i - 1] + 2;
+		}
+		ecclayout->oobfree[0].offset = i + BADBLOCK_MARKER_LENGTH;
+		ecclayout->oobfree[0].length = oobsize - ecclayout->eccbytes -
+						BADBLOCK_MARKER_LENGTH;
+		bch->ecc_scheme		= OMAP_ECC_BCH8_CODE_HW_DETECTION_SW;
+		break;
+#else
+		printf("nand: error: CONFIG_BCH required for ECC\n");
+		return -EINVAL;
+#endif
+
+	case OMAP_ECC_BCH8_CODE_HW:
+#ifdef CONFIG_NAND_OMAP_ELM
+		debug("nand: selected OMAP_ECC_BCH8_CODE_HW\n");
+		/* check ecc-scheme requirements before updating ecc info */
+		if ((14 * eccsteps) + BADBLOCK_MARKER_LENGTH > oobsize) {
+			printf("nand: error: insufficient OOB: require=%d\n", (
+				(14 * eccsteps) + BADBLOCK_MARKER_LENGTH));
+			return -EINVAL;
+		}
+		/* intialize ELM for ECC error detection */
+		elm_init();
+		bch_priv.type		= ECC_BCH8;
+		/* populate ecc specific fields */
+		memset(&nand->ecc, 0, sizeof(struct nand_ecc_ctrl));
+		nand->ecc.mode		= NAND_ECC_HW;
+		nand->ecc.strength	= 8;
+		nand->ecc.size		= SECTOR_BYTES;
+		nand->ecc.bytes		= 14;
+		nand->ecc.hwctl		= omap_enable_hwecc;
+		nand->ecc.correct	= omap_correct_data_bch;
+		nand->ecc.calculate	= omap_calculate_ecc;
+		nand->ecc.read_page	= omap_read_page_bch;
+		/* define ecc-layout */
+		ecclayout->eccbytes	= nand->ecc.bytes * eccsteps;
+		for (i = 0; i < ecclayout->eccbytes; i++)
+			ecclayout->eccpos[i] = i + BADBLOCK_MARKER_LENGTH;
+		ecclayout->oobfree[0].offset = i + BADBLOCK_MARKER_LENGTH;
+		ecclayout->oobfree[0].length = oobsize - ecclayout->eccbytes -
+						BADBLOCK_MARKER_LENGTH;
+		bch->ecc_scheme		= OMAP_ECC_BCH8_CODE_HW;
+		break;
+#else
+		printf("nand: error: CONFIG_NAND_OMAP_ELM required for ECC\n");
+		return -EINVAL;
+#endif
+
+	default:
+		debug("nand: error: ecc scheme not enabled or supported\n");
+		return -EINVAL;
+	}
+
+	/* nand_scan_tail() sets ham1 sw ecc; hw ecc layout is set by driver */
+	if (ecc_scheme != OMAP_ECC_HAM1_CODE_SW)
+		nand->ecc.layout = ecclayout;
+
+	return 0;
+}
 
 #ifndef CONFIG_SPL_BUILD
 /*
@@ -763,77 +711,46 @@ static void __maybe_unused omap_free_bch(struct mtd_info *mtd)
  * @eccstrength		- the number of bits that could be corrected
  *			  (1 - hamming, 4 - BCH4, 8 - BCH8, 16 - BCH16)
  */
-void omap_nand_switch_ecc(uint32_t hardware, uint32_t eccstrength)
+int __maybe_unused omap_nand_switch_ecc(uint32_t hardware, uint32_t eccstrength)
 {
 	struct nand_chip *nand;
 	struct mtd_info *mtd;
+	int err = 0;
 
 	if (nand_curr_device < 0 ||
 	    nand_curr_device >= CONFIG_SYS_MAX_NAND_DEVICE ||
 	    !nand_info[nand_curr_device].name) {
-		printf("Error: Can't switch ecc, no devices available\n");
-		return;
+		printf("nand: error: no NAND devices found\n");
+		return -ENODEV;
 	}
 
 	mtd = &nand_info[nand_curr_device];
 	nand = mtd->priv;
-
 	nand->options |= NAND_OWN_BUFFERS;
-
-	/* Reset ecc interface */
-	nand->ecc.mode = NAND_ECC_NONE;
-	nand->ecc.read_page = NULL;
-	nand->ecc.write_page = NULL;
-	nand->ecc.read_oob = NULL;
-	nand->ecc.write_oob = NULL;
-	nand->ecc.hwctl = NULL;
-	nand->ecc.correct = NULL;
-	nand->ecc.calculate = NULL;
-	nand->ecc.strength = eccstrength;
-
+	nand->options &= ~NAND_SUBPAGE_READ;
 	/* Setup the ecc configurations again */
 	if (hardware) {
 		if (eccstrength == 1) {
-			nand->ecc.mode = NAND_ECC_HW;
-			nand->ecc.layout = &hw_nand_oob;
-			nand->ecc.size = 512;
-			nand->ecc.bytes = 3;
-			nand->ecc.hwctl = omap_enable_hwecc;
-			nand->ecc.correct = omap_correct_data;
-			nand->ecc.calculate = omap_calculate_ecc;
-			omap_hwecc_init(nand);
-			printf("1-bit hamming HW ECC selected\n");
-		}
-#if defined(CONFIG_AM33XX) || defined(CONFIG_NAND_OMAP_BCH8)
-		else if (eccstrength == 8) {
-			nand->ecc.mode = NAND_ECC_HW;
-			nand->ecc.layout = &hw_bch8_nand_oob;
-			nand->ecc.size = 512;
-#ifdef CONFIG_AM33XX
-			nand->ecc.bytes = 14;
-			nand->ecc.read_page = omap_read_page_bch;
-#else
-			nand->ecc.bytes = 13;
-#endif
-			nand->ecc.hwctl = omap_enable_ecc_bch;
-			nand->ecc.correct = omap_correct_data_bch;
-			nand->ecc.calculate = omap_calculate_ecc_bch;
-			omap_hwecc_init_bch(nand, NAND_ECC_READ);
-			printf("8-bit BCH HW ECC selected\n");
+			err = omap_select_ecc_scheme(nand,
+					OMAP_ECC_HAM1_CODE_HW,
+					mtd->writesize, mtd->oobsize);
+		} else if (eccstrength == 8) {
+			err = omap_select_ecc_scheme(nand,
+					OMAP_ECC_BCH8_CODE_HW,
+					mtd->writesize, mtd->oobsize);
+		} else {
+			printf("nand: error: unsupported ECC scheme\n");
+			return -EINVAL;
 		}
-#endif
 	} else {
-		nand->ecc.mode = NAND_ECC_SOFT;
-		/* Use mtd default settings */
-		nand->ecc.layout = NULL;
-		nand->ecc.size = 0;
-		printf("SW ECC selected\n");
+		err = omap_select_ecc_scheme(nand, OMAP_ECC_HAM1_CODE_SW,
+					mtd->writesize, mtd->oobsize);
 	}
 
 	/* Update NAND handling after ECC mode switch */
-	nand_scan_tail(mtd);
-
-	nand->options &= ~NAND_OWN_BUFFERS;
+	if (!err)
+		err = nand_scan_tail(mtd);
+	return err;
 }
 #endif /* CONFIG_SPL_BUILD */
 
@@ -856,7 +773,7 @@ int board_nand_init(struct nand_chip *nand)
 {
 	int32_t gpmc_config = 0;
 	cs = 0;
-
+	int err = 0;
 	/*
 	 * xloader/Uboot's gpmc configuration would have configured GPMC for
 	 * nand type of memory. The following logic scans and latches on to the
@@ -873,7 +790,7 @@ int board_nand_init(struct nand_chip *nand)
 		cs++;
 	}
 	if (cs >= GPMC_MAX_CS) {
-		printf("NAND: Unable to find NAND settings in "
+		printf("nand: error: Unable to find NAND settings in "
 			"GPMC Configuration - quitting\n");
 		return -ENODEV;
 	}
@@ -885,64 +802,27 @@ int board_nand_init(struct nand_chip *nand)
 
 	nand->IO_ADDR_R = (void __iomem *)&gpmc_cfg->cs[cs].nand_dat;
 	nand->IO_ADDR_W = (void __iomem *)&gpmc_cfg->cs[cs].nand_cmd;
-
-	nand->cmd_ctrl = omap_nand_hwcontrol;
-	nand->options = NAND_NO_PADDING | NAND_CACHEPRG;
+	nand->priv	= &bch_priv;
+	nand->cmd_ctrl	= omap_nand_hwcontrol;
+	nand->options	|= NAND_NO_PADDING | NAND_CACHEPRG;
 	/* If we are 16 bit dev, our gpmc config tells us that */
 	if ((readl(&gpmc_cfg->cs[cs].config1) & 0x3000) == 0x1000)
 		nand->options |= NAND_BUSWIDTH_16;
 
 	nand->chip_delay = 100;
+	nand->ecc.layout = &omap_ecclayout;
 
-#if defined(CONFIG_AM33XX) || defined(CONFIG_NAND_OMAP_BCH8)
-#ifdef CONFIG_AM33XX
-	/* AM33xx uses the ELM */
-	/* required in case of BCH */
-	elm_init();
+	/* select ECC scheme */
+#if defined(CONFIG_NAND_OMAP_ECCSCHEME)
+	err = omap_select_ecc_scheme(nand, CONFIG_NAND_OMAP_ECCSCHEME,
+			CONFIG_SYS_NAND_PAGE_SIZE, CONFIG_SYS_NAND_OOBSIZE);
 #else
-	/*
-	 * Whereas other OMAP based SoC do not have the ELM, they use the BCH
-	 * SW library.
-	 */
-	bch_priv.control = init_bch(13, 8, 0x201b /* hw polynominal */);
-	if (!bch_priv.control) {
-		puts("Could not init_bch()\n");
-		return -ENODEV;
-	}
-#endif
-	/* BCH info that will be correct for SPL or overridden otherwise. */
-	nand->priv = &bch_priv;
-#endif
-
-	/* Default ECC mode */
-#if defined(CONFIG_AM33XX) || defined(CONFIG_NAND_OMAP_BCH8)
-	nand->ecc.mode = NAND_ECC_HW;
-	nand->ecc.layout = &hw_bch8_nand_oob;
-	nand->ecc.size = CONFIG_SYS_NAND_ECCSIZE;
-	nand->ecc.bytes = CONFIG_SYS_NAND_ECCBYTES;
-	nand->ecc.strength = 8;
-	nand->ecc.hwctl = omap_enable_ecc_bch;
-	nand->ecc.correct = omap_correct_data_bch;
-	nand->ecc.calculate = omap_calculate_ecc_bch;
-#ifdef CONFIG_AM33XX
-	nand->ecc.read_page = omap_read_page_bch;
-#endif
-	omap_hwecc_init_bch(nand, NAND_ECC_READ);
-#else
-#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_NAND_SOFTECC)
-	nand->ecc.mode = NAND_ECC_SOFT;
-#else
-	nand->ecc.mode = NAND_ECC_HW;
-	nand->ecc.layout = &hw_nand_oob;
-	nand->ecc.size = CONFIG_SYS_NAND_ECCSIZE;
-	nand->ecc.bytes = CONFIG_SYS_NAND_ECCBYTES;
-	nand->ecc.hwctl = omap_enable_hwecc;
-	nand->ecc.correct = omap_correct_data;
-	nand->ecc.calculate = omap_calculate_ecc;
-	nand->ecc.strength = 1;
-	omap_hwecc_init(nand);
-#endif
+	/* pagesize and oobsize are not required to configure sw ecc-scheme */
+	err = omap_select_ecc_scheme(nand, OMAP_ECC_HAM1_CODE_SW,
+			0, 0);
 #endif
+	if (err)
+		return err;
 
 #ifdef CONFIG_SPL_BUILD
 	if (nand->options & NAND_BUSWIDTH_16)
diff --git a/drivers/mtd/onenand/Makefile b/drivers/mtd/onenand/Makefile
index 993d317476..b249348814 100644
--- a/drivers/mtd/onenand/Makefile
+++ b/drivers/mtd/onenand/Makefile
@@ -5,30 +5,9 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	:= $(obj)libonenand.o
-
 ifndef	CONFIG_SPL_BUILD
-COBJS-$(CONFIG_CMD_ONENAND)	:= onenand_uboot.o onenand_base.o onenand_bbt.o
-COBJS-$(CONFIG_SAMSUNG_ONENAND)	+= samsung.o
+obj-$(CONFIG_CMD_ONENAND)	:= onenand_uboot.o onenand_base.o onenand_bbt.o
+obj-$(CONFIG_SAMSUNG_ONENAND)	+= samsung.o
 else
-COBJS-y				:= onenand_spl.o
+obj-y				:= onenand_spl.o
 endif
-
-COBJS	:= $(COBJS-y)
-SRCS	:= $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-
-all:	$(LIB)
-
-$(LIB): $(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
diff --git a/drivers/mtd/onenand/onenand_base.c b/drivers/mtd/onenand/onenand_base.c
index 067f8ef184..e33e8d38e7 100644
--- a/drivers/mtd/onenand/onenand_base.c
+++ b/drivers/mtd/onenand/onenand_base.c
@@ -91,7 +91,13 @@ static struct nand_ecclayout onenand_oob_32 = {
 	.oobfree	= { {2, 3}, {14, 2}, {18, 3}, {30, 2} }
 };
 
-static const unsigned char ffchars[] = {
+/*
+ * Warning! This array is used with the memcpy_16() function, thus
+ * it must be aligned to 2 bytes. GCC can make this array unaligned
+ * as the array is made of unsigned char, which memcpy16() doesn't
+ * like and will cause unaligned access.
+ */
+static const unsigned char __aligned(2) ffchars[] = {
 	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
 	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,	/* 16 */
 	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
@@ -761,7 +767,8 @@ static int onenand_transfer_auto_oob(struct mtd_info *mtd, uint8_t *buf,
 	uint8_t *oob_buf = this->oob_buf;
 
 	free = this->ecclayout->oobfree;
-	for (i = 0; i < MTD_MAX_OOBFREE_ENTRIES && free->length; i++, free++) {
+	for (i = 0; i < MTD_MAX_OOBFREE_ENTRIES_LARGE && free->length;
+	     i++, free++) {
 		if (readcol >= lastgap)
 			readcol += free->offset - lastgap;
 		if (readend >= lastgap)
@@ -770,7 +777,8 @@ static int onenand_transfer_auto_oob(struct mtd_info *mtd, uint8_t *buf,
 	}
 	this->read_bufferram(mtd, 0, ONENAND_SPARERAM, oob_buf, 0, mtd->oobsize);
 	free = this->ecclayout->oobfree;
-	for (i = 0; i < MTD_MAX_OOBFREE_ENTRIES && free->length; i++, free++) {
+	for (i = 0; i < MTD_MAX_OOBFREE_ENTRIES_LARGE && free->length;
+	     i++, free++) {
 		int free_end = free->offset + free->length;
 		if (free->offset < readend && free_end > readcol) {
 			int st = max_t(int,free->offset,readcol);
@@ -1356,7 +1364,8 @@ static int onenand_fill_auto_oob(struct mtd_info *mtd, u_char *oob_buf,
 	unsigned int i;
 
 	free = this->ecclayout->oobfree;
-	for (i = 0; i < MTD_MAX_OOBFREE_ENTRIES && free->length; i++, free++) {
+	for (i = 0; i < MTD_MAX_OOBFREE_ENTRIES_LARGE && free->length;
+	     i++, free++) {
 		if (writecol >= lastgap)
 			writecol += free->offset - lastgap;
 		if (writeend >= lastgap)
@@ -1364,7 +1373,8 @@ static int onenand_fill_auto_oob(struct mtd_info *mtd, u_char *oob_buf,
 		lastgap = free->offset + free->length;
 	}
 	free = this->ecclayout->oobfree;
-	for (i = 0; i < MTD_MAX_OOBFREE_ENTRIES && free->length; i++, free++) {
+	for (i = 0; i < MTD_MAX_OOBFREE_ENTRIES_LARGE && free->length;
+	     i++, free++) {
 		int free_end = free->offset + free->length;
 		if (free->offset < writeend && free_end > writecol) {
 			int st = max_t(int,free->offset,writecol);
@@ -2750,7 +2760,8 @@ int onenand_scan(struct mtd_info *mtd, int maxchips)
 	 * the out of band area
 	 */
 	this->ecclayout->oobavail = 0;
-	for (i = 0; i < MTD_MAX_OOBFREE_ENTRIES &&
+
+	for (i = 0; i < MTD_MAX_OOBFREE_ENTRIES_LARGE &&
 	    this->ecclayout->oobfree[i].length; i++)
 		this->ecclayout->oobavail +=
 			this->ecclayout->oobfree[i].length;
diff --git a/drivers/mtd/spi/Makefile b/drivers/mtd/spi/Makefile
index 86ffc59d03..9e18fb41de 100644
--- a/drivers/mtd/spi/Makefile
+++ b/drivers/mtd/spi/Makefile
@@ -5,36 +5,13 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	:= $(obj)libspi_flash.o
-
 ifdef CONFIG_SPL_BUILD
-COBJS-$(CONFIG_SPL_SPI_LOAD)	+= spi_spl_load.o
-COBJS-$(CONFIG_SPL_SPI_BOOT)	+= fsl_espi_spl.o
+obj-$(CONFIG_SPL_SPI_LOAD)	+= spi_spl_load.o
+obj-$(CONFIG_SPL_SPI_BOOT)	+= fsl_espi_spl.o
 endif
 
-ifdef CONFIG_CMD_SF
-COBJS-y        += sf.o
-endif
-COBJS-$(CONFIG_SPI_FLASH) += sf_probe.o sf_ops.o
-COBJS-$(CONFIG_SPI_FRAM_RAMTRON) += ramtron.o
-COBJS-$(CONFIG_SPI_M95XXX) += eeprom_m95xxx.o
-
-COBJS	:= $(COBJS-y)
-SRCS	:= $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-
-all:	$(LIB)
-
-$(LIB): $(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-$(CONFIG_CMD_SF) += sf.o
+obj-$(CONFIG_SPI_FLASH) += sf_params.o sf_probe.o sf_ops.o
+obj-$(CONFIG_SPI_FRAM_RAMTRON) += ramtron.o
+obj-$(CONFIG_SPI_FLASH_SANDBOX) += sandbox.o
+obj-$(CONFIG_SPI_M95XXX) += eeprom_m95xxx.o
diff --git a/drivers/mtd/spi/fsl_espi_spl.c b/drivers/mtd/spi/fsl_espi_spl.c
index 6263d8c221..e5ac79b952 100644
--- a/drivers/mtd/spi/fsl_espi_spl.c
+++ b/drivers/mtd/spi/fsl_espi_spl.c
@@ -31,6 +31,10 @@ void spi_boot(void)
 		hang();
 	}
 
+#ifdef CONFIG_FSL_CORENET
+	offset = CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS;
+	code_len = CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE;
+#else
 	/*
 	* Load U-Boot image from SPI flash into RAM
 	*/
@@ -50,6 +54,7 @@ void spi_boot(void)
 	code_len = *(u32 *)(buf + ESPI_BOOT_IMAGE_SIZE);
 	/* Skip spl code */
 	code_len = code_len - CONFIG_SPL_MAX_SIZE;
+#endif
 	/* copy code to DDR */
 	spi_flash_read(flash, offset, code_len,
 		       (void *)CONFIG_SYS_SPI_FLASH_U_BOOT_DST);
diff --git a/drivers/mtd/spi/sandbox.c b/drivers/mtd/spi/sandbox.c
new file mode 100644
index 0000000000..a62ef4cbbd
--- /dev/null
+++ b/drivers/mtd/spi/sandbox.c
@@ -0,0 +1,483 @@
+/*
+ * Simulate a SPI flash
+ *
+ * Copyright (c) 2011-2013 The Chromium OS Authors.
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+#include <common.h>
+#include <malloc.h>
+#include <spi.h>
+#include <os.h>
+
+#include <spi_flash.h>
+#include "sf_internal.h"
+
+#include <asm/getopt.h>
+#include <asm/spi.h>
+#include <asm/state.h>
+
+/*
+ * The different states that our SPI flash transitions between.
+ * We need to keep track of this across multiple xfer calls since
+ * the SPI bus could possibly call down into us multiple times.
+ */
+enum sandbox_sf_state {
+	SF_CMD,   /* default state -- we're awaiting a command */
+	SF_ID,    /* read the flash's (jedec) ID code */
+	SF_ADDR,  /* processing the offset in the flash to read/etc... */
+	SF_READ,  /* reading data from the flash */
+	SF_WRITE, /* writing data to the flash, i.e. page programming */
+	SF_ERASE, /* erase the flash */
+	SF_READ_STATUS, /* read the flash's status register */
+	SF_READ_STATUS1, /* read the flash's status register upper 8 bits*/
+};
+
+static const char *sandbox_sf_state_name(enum sandbox_sf_state state)
+{
+	static const char * const states[] = {
+		"CMD", "ID", "ADDR", "READ", "WRITE", "ERASE", "READ_STATUS",
+	};
+	return states[state];
+}
+
+/* Bits for the status register */
+#define STAT_WIP	(1 << 0)
+#define STAT_WEL	(1 << 1)
+
+/* Assume all SPI flashes have 3 byte addresses since they do atm */
+#define SF_ADDR_LEN	3
+
+struct sandbox_spi_flash_erase_commands {
+	u8 cmd;
+	u32 size;
+};
+#define IDCODE_LEN 5
+#define MAX_ERASE_CMDS 3
+struct sandbox_spi_flash_data {
+	const char *name;
+	u8 idcode[IDCODE_LEN];
+	u32 size;
+	const struct sandbox_spi_flash_erase_commands
+						erase_cmds[MAX_ERASE_CMDS];
+};
+
+/* Structure describing all the flashes we know how to emulate */
+static const struct sandbox_spi_flash_data sandbox_sf_flashes[] = {
+	{
+		"M25P16", { 0x20, 0x20, 0x15 }, (2 << 20),
+		{	/* erase commands */
+			{ 0xd8, (64 << 10), }, /* sector */
+			{ 0xc7, (2 << 20), }, /* bulk */
+		},
+	},
+	{
+		"W25Q32", { 0xef, 0x40, 0x16 }, (4 << 20),
+		{	/* erase commands */
+			{ 0x20, (4 << 10), }, /* 4KB */
+			{ 0xd8, (64 << 10), }, /* sector */
+			{ 0xc7, (4 << 20), }, /* bulk */
+		},
+	},
+	{
+		"W25Q128", { 0xef, 0x40, 0x18 }, (16 << 20),
+		{	/* erase commands */
+			{ 0x20, (4 << 10), }, /* 4KB */
+			{ 0xd8, (64 << 10), }, /* sector */
+			{ 0xc7, (16 << 20), }, /* bulk */
+		},
+	},
+};
+
+/* Used to quickly bulk erase backing store */
+static u8 sandbox_sf_0xff[0x1000];
+
+/* Internal state data for each SPI flash */
+struct sandbox_spi_flash {
+	/*
+	 * As we receive data over the SPI bus, our flash transitions
+	 * between states.  For example, we start off in the SF_CMD
+	 * state where the first byte tells us what operation to perform
+	 * (such as read or write the flash).  But the operation itself
+	 * can go through a few states such as first reading in the
+	 * offset in the flash to perform the requested operation.
+	 * Thus "state" stores the exact state that our machine is in
+	 * while "cmd" stores the overall command we're processing.
+	 */
+	enum sandbox_sf_state state;
+	uint cmd;
+	const void *cmd_data;
+	/* Current position in the flash; used when reading/writing/etc... */
+	uint off;
+	/* How many address bytes we've consumed */
+	uint addr_bytes, pad_addr_bytes;
+	/* The current flash status (see STAT_XXX defines above) */
+	u16 status;
+	/* Data describing the flash we're emulating */
+	const struct sandbox_spi_flash_data *data;
+	/* The file on disk to serv up data from */
+	int fd;
+};
+
+static int sandbox_sf_setup(void **priv, const char *spec)
+{
+	/* spec = idcode:file */
+	struct sandbox_spi_flash *sbsf;
+	const char *file;
+	size_t i, len, idname_len;
+	const struct sandbox_spi_flash_data *data;
+
+	file = strchr(spec, ':');
+	if (!file) {
+		printf("sandbox_sf: unable to parse file\n");
+		goto error;
+	}
+	idname_len = file - spec;
+	++file;
+
+	for (i = 0; i < ARRAY_SIZE(sandbox_sf_flashes); ++i) {
+		data = &sandbox_sf_flashes[i];
+		len = strlen(data->name);
+		if (idname_len != len)
+			continue;
+		if (!memcmp(spec, data->name, len))
+			break;
+	}
+	if (i == ARRAY_SIZE(sandbox_sf_flashes)) {
+		printf("sandbox_sf: unknown flash '%*s'\n", (int)idname_len,
+		       spec);
+		goto error;
+	}
+
+	if (sandbox_sf_0xff[0] == 0x00)
+		memset(sandbox_sf_0xff, 0xff, sizeof(sandbox_sf_0xff));
+
+	sbsf = calloc(sizeof(*sbsf), 1);
+	if (!sbsf) {
+		printf("sandbox_sf: out of memory\n");
+		goto error;
+	}
+
+	sbsf->fd = os_open(file, 02);
+	if (sbsf->fd == -1) {
+		free(sbsf);
+		printf("sandbox_sf: unable to open file '%s'\n", file);
+		goto error;
+	}
+
+	sbsf->data = data;
+
+	*priv = sbsf;
+	return 0;
+
+ error:
+	return 1;
+}
+
+static void sandbox_sf_free(void *priv)
+{
+	struct sandbox_spi_flash *sbsf = priv;
+
+	os_close(sbsf->fd);
+	free(sbsf);
+}
+
+static void sandbox_sf_cs_activate(void *priv)
+{
+	struct sandbox_spi_flash *sbsf = priv;
+
+	debug("sandbox_sf: CS activated; state is fresh!\n");
+
+	/* CS is asserted, so reset state */
+	sbsf->off = 0;
+	sbsf->addr_bytes = 0;
+	sbsf->pad_addr_bytes = 0;
+	sbsf->state = SF_CMD;
+	sbsf->cmd = SF_CMD;
+}
+
+static void sandbox_sf_cs_deactivate(void *priv)
+{
+	debug("sandbox_sf: CS deactivated; cmd done processing!\n");
+}
+
+/* Figure out what command this stream is telling us to do */
+static int sandbox_sf_process_cmd(struct sandbox_spi_flash *sbsf, const u8 *rx,
+				  u8 *tx)
+{
+	enum sandbox_sf_state oldstate = sbsf->state;
+
+	/* We need to output a byte for the cmd byte we just ate */
+	sandbox_spi_tristate(tx, 1);
+
+	sbsf->cmd = rx[0];
+	switch (sbsf->cmd) {
+	case CMD_READ_ID:
+		sbsf->state = SF_ID;
+		sbsf->cmd = SF_ID;
+		break;
+	case CMD_READ_ARRAY_FAST:
+		sbsf->pad_addr_bytes = 1;
+	case CMD_READ_ARRAY_SLOW:
+	case CMD_PAGE_PROGRAM:
+ state_addr:
+		sbsf->state = SF_ADDR;
+		break;
+	case CMD_WRITE_DISABLE:
+		debug(" write disabled\n");
+		sbsf->status &= ~STAT_WEL;
+		break;
+	case CMD_READ_STATUS:
+		sbsf->state = SF_READ_STATUS;
+		break;
+	case CMD_READ_STATUS1:
+		sbsf->state = SF_READ_STATUS1;
+		break;
+	case CMD_WRITE_ENABLE:
+		debug(" write enabled\n");
+		sbsf->status |= STAT_WEL;
+		break;
+	default: {
+		size_t i;
+
+		/* handle erase commands first */
+		for (i = 0; i < MAX_ERASE_CMDS; ++i) {
+			const struct sandbox_spi_flash_erase_commands *
+				erase_cmd = &sbsf->data->erase_cmds[i];
+
+			if (erase_cmd->cmd == 0x00)
+				continue;
+			if (sbsf->cmd != erase_cmd->cmd)
+				continue;
+
+			sbsf->cmd_data = erase_cmd;
+			goto state_addr;
+		}
+
+		debug(" cmd unknown: %#x\n", sbsf->cmd);
+		return 1;
+	}
+	}
+
+	if (oldstate != sbsf->state)
+		debug(" cmd: transition to %s state\n",
+		      sandbox_sf_state_name(sbsf->state));
+
+	return 0;
+}
+
+int sandbox_erase_part(struct sandbox_spi_flash *sbsf, int size)
+{
+	int todo;
+	int ret;
+
+	while (size > 0) {
+		todo = min(size, sizeof(sandbox_sf_0xff));
+		ret = os_write(sbsf->fd, sandbox_sf_0xff, todo);
+		if (ret != todo)
+			return ret;
+		size -= todo;
+	}
+
+	return 0;
+}
+
+static int sandbox_sf_xfer(void *priv, const u8 *rx, u8 *tx,
+		uint bytes)
+{
+	struct sandbox_spi_flash *sbsf = priv;
+	uint cnt, pos = 0;
+	int ret;
+
+	debug("sandbox_sf: state:%x(%s) bytes:%u\n", sbsf->state,
+	      sandbox_sf_state_name(sbsf->state), bytes);
+
+	if (sbsf->state == SF_CMD) {
+		/* Figure out the initial state */
+		if (sandbox_sf_process_cmd(sbsf, rx, tx))
+			return 1;
+		++pos;
+	}
+
+	/* Process the remaining data */
+	while (pos < bytes) {
+		switch (sbsf->state) {
+		case SF_ID: {
+			u8 id;
+
+			debug(" id: off:%u tx:", sbsf->off);
+			if (sbsf->off < IDCODE_LEN)
+				id = sbsf->data->idcode[sbsf->off];
+			else
+				id = 0;
+			debug("%02x\n", id);
+			tx[pos++] = id;
+			++sbsf->off;
+			break;
+		}
+		case SF_ADDR:
+			debug(" addr: bytes:%u rx:%02x ", sbsf->addr_bytes,
+			      rx[pos]);
+
+			if (sbsf->addr_bytes++ < SF_ADDR_LEN)
+				sbsf->off = (sbsf->off << 8) | rx[pos];
+			debug("addr:%06x\n", sbsf->off);
+
+			sandbox_spi_tristate(&tx[pos++], 1);
+
+			/* See if we're done processing */
+			if (sbsf->addr_bytes <
+					SF_ADDR_LEN + sbsf->pad_addr_bytes)
+				break;
+
+			/* Next state! */
+			if (os_lseek(sbsf->fd, sbsf->off, OS_SEEK_SET) < 0) {
+				puts("sandbox_sf: os_lseek() failed");
+				return 1;
+			}
+			switch (sbsf->cmd) {
+			case CMD_READ_ARRAY_FAST:
+			case CMD_READ_ARRAY_SLOW:
+				sbsf->state = SF_READ;
+				break;
+			case CMD_PAGE_PROGRAM:
+				sbsf->state = SF_WRITE;
+				break;
+			default:
+				/* assume erase state ... */
+				sbsf->state = SF_ERASE;
+				goto case_sf_erase;
+			}
+			debug(" cmd: transition to %s state\n",
+			      sandbox_sf_state_name(sbsf->state));
+			break;
+		case SF_READ:
+			/*
+			 * XXX: need to handle exotic behavior:
+			 *      - reading past end of device
+			 */
+
+			cnt = bytes - pos;
+			debug(" tx: read(%u)\n", cnt);
+			ret = os_read(sbsf->fd, tx + pos, cnt);
+			if (ret < 0) {
+				puts("sandbox_spi: os_read() failed\n");
+				return 1;
+			}
+			pos += ret;
+			break;
+		case SF_READ_STATUS:
+			debug(" read status: %#x\n", sbsf->status);
+			cnt = bytes - pos;
+			memset(tx + pos, sbsf->status, cnt);
+			pos += cnt;
+			break;
+		case SF_READ_STATUS1:
+			debug(" read status: %#x\n", sbsf->status);
+			cnt = bytes - pos;
+			memset(tx + pos, sbsf->status >> 8, cnt);
+			pos += cnt;
+			break;
+		case SF_WRITE:
+			/*
+			 * XXX: need to handle exotic behavior:
+			 *      - unaligned addresses
+			 *      - more than a page (256) worth of data
+			 *      - reading past end of device
+			 */
+			if (!(sbsf->status & STAT_WEL)) {
+				puts("sandbox_sf: write enable not set before write\n");
+				goto done;
+			}
+
+			cnt = bytes - pos;
+			debug(" rx: write(%u)\n", cnt);
+			sandbox_spi_tristate(&tx[pos], cnt);
+			ret = os_write(sbsf->fd, rx + pos, cnt);
+			if (ret < 0) {
+				puts("sandbox_spi: os_write() failed\n");
+				return 1;
+			}
+			pos += ret;
+			sbsf->status &= ~STAT_WEL;
+			break;
+		case SF_ERASE:
+ case_sf_erase: {
+			const struct sandbox_spi_flash_erase_commands *
+						erase_cmd = sbsf->cmd_data;
+
+			if (!(sbsf->status & STAT_WEL)) {
+				puts("sandbox_sf: write enable not set before erase\n");
+				goto done;
+			}
+
+			/* verify address is aligned */
+			if (sbsf->off & (erase_cmd->size - 1)) {
+				debug(" sector erase: cmd:%#x needs align:%#x, but we got %#x\n",
+				      erase_cmd->cmd, erase_cmd->size,
+				      sbsf->off);
+				sbsf->status &= ~STAT_WEL;
+				goto done;
+			}
+
+			debug(" sector erase addr: %u\n", sbsf->off);
+
+			cnt = bytes - pos;
+			sandbox_spi_tristate(&tx[pos], cnt);
+			pos += cnt;
+
+			/*
+			 * TODO(vapier@gentoo.org): latch WIP in status, and
+			 * delay before clearing it ?
+			 */
+			ret = sandbox_erase_part(sbsf, erase_cmd->size);
+			sbsf->status &= ~STAT_WEL;
+			if (ret) {
+				debug("sandbox_sf: Erase failed\n");
+				goto done;
+			}
+			goto done;
+		}
+		default:
+			debug(" ??? no idea what to do ???\n");
+			goto done;
+		}
+	}
+
+ done:
+	return pos == bytes ? 0 : 1;
+}
+
+static const struct sandbox_spi_emu_ops sandbox_sf_ops = {
+	.setup         = sandbox_sf_setup,
+	.free          = sandbox_sf_free,
+	.cs_activate   = sandbox_sf_cs_activate,
+	.cs_deactivate = sandbox_sf_cs_deactivate,
+	.xfer          = sandbox_sf_xfer,
+};
+
+static int sandbox_cmdline_cb_spi_sf(struct sandbox_state *state,
+				     const char *arg)
+{
+	unsigned long bus, cs;
+	const char *spec = sandbox_spi_parse_spec(arg, &bus, &cs);
+
+	if (!spec)
+		return 1;
+
+	/*
+	 * It is safe to not make a copy of 'spec' because it comes from the
+	 * command line.
+	 *
+	 * TODO(sjg@chromium.org): It would be nice if we could parse the
+	 * spec here, but the problem is that no U-Boot init has been done
+	 * yet. Perhaps we can figure something out.
+	 */
+	state->spi[bus][cs].ops = &sandbox_sf_ops;
+	state->spi[bus][cs].spec = spec;
+	return 0;
+}
+SANDBOX_CMDLINE_OPT(spi_sf, 1, "connect a SPI flash: <bus>:<cs>:<id>:<file>");
diff --git a/drivers/mtd/spi/sf.c b/drivers/mtd/spi/sf.c
index d5e175ca00..664e86082b 100644
--- a/drivers/mtd/spi/sf.c
+++ b/drivers/mtd/spi/sf.c
@@ -18,6 +18,10 @@ static int spi_flash_read_write(struct spi_slave *spi,
 	unsigned long flags = SPI_XFER_BEGIN;
 	int ret;
 
+#ifdef CONFIG_SF_DUAL_FLASH
+	if (spi->flags & SPI_XFER_U_PAGE)
+		flags |= SPI_XFER_U_PAGE;
+#endif
 	if (data_len == 0)
 		flags |= SPI_XFER_END;
 
diff --git a/drivers/mtd/spi/sf_internal.h b/drivers/mtd/spi/sf_internal.h
index 732ddf836d..6bcd522040 100644
--- a/drivers/mtd/spi/sf_internal.h
+++ b/drivers/mtd/spi/sf_internal.h
@@ -10,12 +10,15 @@
 #ifndef _SF_INTERNAL_H_
 #define _SF_INTERNAL_H_
 
+#define SPI_FLASH_3B_ADDR_LEN		3
+#define SPI_FLASH_CMD_LEN		(1 + SPI_FLASH_3B_ADDR_LEN)
 #define SPI_FLASH_16MB_BOUN		0x1000000
 
-/* SECT flags */
-#define SECT_4K				(1 << 1)
-#define SECT_32K			(1 << 2)
-#define E_FSR				(1 << 3)
+/* CFI Manufacture ID's */
+#define SPI_FLASH_CFI_MFR_SPANSION	0x01
+#define SPI_FLASH_CFI_MFR_STMICRO	0x20
+#define SPI_FLASH_CFI_MFR_MACRONIX	0xc2
+#define SPI_FLASH_CFI_MFR_WINBOND	0xef
 
 /* Erase commands */
 #define CMD_ERASE_4K			0x20
@@ -28,6 +31,8 @@
 #define CMD_PAGE_PROGRAM		0x02
 #define CMD_WRITE_DISABLE		0x04
 #define CMD_READ_STATUS			0x05
+#define CMD_QUAD_PAGE_PROGRAM		0x32
+#define CMD_READ_STATUS1		0x35
 #define CMD_WRITE_ENABLE		0x06
 #define CMD_READ_CONFIG			0x35
 #define CMD_FLAG_STATUS			0x70
@@ -35,6 +40,10 @@
 /* Read commands */
 #define CMD_READ_ARRAY_SLOW		0x03
 #define CMD_READ_ARRAY_FAST		0x0b
+#define CMD_READ_DUAL_OUTPUT_FAST	0x3b
+#define CMD_READ_DUAL_IO_FAST		0xbb
+#define CMD_READ_QUAD_OUTPUT_FAST	0x6b
+#define CMD_READ_QUAD_IO_FAST		0xeb
 #define CMD_READ_ID			0x9f
 
 /* Bank addr access commands */
@@ -46,8 +55,10 @@
 #endif
 
 /* Common status */
-#define STATUS_WIP			0x01
-#define STATUS_PEC			0x80
+#define STATUS_WIP			(1 << 0)
+#define STATUS_QEB_WINSPAN		(1 << 1)
+#define STATUS_QEB_MXIC			(1 << 6)
+#define STATUS_PEC			(1 << 7)
 
 /* Flash timeout values */
 #define SPI_FLASH_PROG_TIMEOUT		(2 * CONFIG_SYS_HZ)
@@ -85,11 +96,17 @@ int spi_flash_cmd_write(struct spi_slave *spi, const u8 *cmd, size_t cmd_len,
 /* Flash erase(sectors) operation, support all possible erase commands */
 int spi_flash_cmd_erase_ops(struct spi_flash *flash, u32 offset, size_t len);
 
+/* Read the status register */
+int spi_flash_cmd_read_status(struct spi_flash *flash, u8 *rs);
+
 /* Program the status register */
-int spi_flash_cmd_write_status(struct spi_flash *flash, u8 sr);
+int spi_flash_cmd_write_status(struct spi_flash *flash, u8 ws);
+
+/* Read the config register */
+int spi_flash_cmd_read_config(struct spi_flash *flash, u8 *rc);
 
-/* Set quad enbale bit */
-int spi_flash_set_qeb(struct spi_flash *flash);
+/* Program the config register */
+int spi_flash_cmd_write_config(struct spi_flash *flash, u8 wc);
 
 /* Enable writing on the SPI flash */
 static inline int spi_flash_cmd_write_enable(struct spi_flash *flash)
diff --git a/drivers/mtd/spi/sf_ops.c b/drivers/mtd/spi/sf_ops.c
index 108665f441..ef91b924d7 100644
--- a/drivers/mtd/spi/sf_ops.c
+++ b/drivers/mtd/spi/sf_ops.c
@@ -9,6 +9,8 @@
  */
 
 #include <common.h>
+#include <errno.h>
+#include <malloc.h>
 #include <spi.h>
 #include <spi_flash.h>
 #include <watchdog.h>
@@ -23,13 +25,28 @@ static void spi_flash_addr(u32 addr, u8 *cmd)
 	cmd[3] = addr >> 0;
 }
 
-int spi_flash_cmd_write_status(struct spi_flash *flash, u8 sr)
+int spi_flash_cmd_read_status(struct spi_flash *flash, u8 *rs)
+{
+	int ret;
+	u8 cmd;
+
+	cmd = CMD_READ_STATUS;
+	ret = spi_flash_read_common(flash, &cmd, 1, rs, 1);
+	if (ret < 0) {
+		debug("SF: fail to read status register\n");
+		return ret;
+	}
+
+	return 0;
+}
+
+int spi_flash_cmd_write_status(struct spi_flash *flash, u8 ws)
 {
 	u8 cmd;
 	int ret;
 
 	cmd = CMD_WRITE_STATUS;
-	ret = spi_flash_write_common(flash, &cmd, 1, &sr, 1);
+	ret = spi_flash_write_common(flash, &cmd, 1, &ws, 1);
 	if (ret < 0) {
 		debug("SF: fail to write status register\n");
 		return ret;
@@ -38,6 +55,44 @@ int spi_flash_cmd_write_status(struct spi_flash *flash, u8 sr)
 	return 0;
 }
 
+#if defined(CONFIG_SPI_FLASH_SPANSION) || defined(CONFIG_SPI_FLASH_WINBOND)
+int spi_flash_cmd_read_config(struct spi_flash *flash, u8 *rc)
+{
+	int ret;
+	u8 cmd;
+
+	cmd = CMD_READ_CONFIG;
+	ret = spi_flash_read_common(flash, &cmd, 1, rc, 1);
+	if (ret < 0) {
+		debug("SF: fail to read config register\n");
+		return ret;
+	}
+
+	return 0;
+}
+
+int spi_flash_cmd_write_config(struct spi_flash *flash, u8 wc)
+{
+	u8 data[2];
+	u8 cmd;
+	int ret;
+
+	ret = spi_flash_cmd_read_status(flash, &data[0]);
+	if (ret < 0)
+		return ret;
+
+	cmd = CMD_WRITE_STATUS;
+	data[1] = wc;
+	ret = spi_flash_write_common(flash, &cmd, 1, &data, 2);
+	if (ret) {
+		debug("SF: fail to write config register\n");
+		return ret;
+	}
+
+	return 0;
+}
+#endif
+
 #ifdef CONFIG_SPI_FLASH_BAR
 static int spi_flash_cmd_bankaddr_write(struct spi_flash *flash, u8 bank_sel)
 {
@@ -65,7 +120,7 @@ static int spi_flash_bank(struct spi_flash *flash, u32 offset)
 	u8 bank_sel;
 	int ret;
 
-	bank_sel = offset / SPI_FLASH_16MB_BOUN;
+	bank_sel = offset / (SPI_FLASH_16MB_BOUN << flash->shift);
 
 	ret = spi_flash_cmd_bankaddr_write(flash, bank_sel);
 	if (ret) {
@@ -73,7 +128,29 @@ static int spi_flash_bank(struct spi_flash *flash, u32 offset)
 		return ret;
 	}
 
-	return 0;
+	return bank_sel;
+}
+#endif
+
+#ifdef CONFIG_SF_DUAL_FLASH
+static void spi_flash_dual_flash(struct spi_flash *flash, u32 *addr)
+{
+	switch (flash->dual_flash) {
+	case SF_DUAL_STACKED_FLASH:
+		if (*addr >= (flash->size >> 1)) {
+			*addr -= flash->size >> 1;
+			flash->spi->flags |= SPI_XFER_U_PAGE;
+		} else {
+			flash->spi->flags &= ~SPI_XFER_U_PAGE;
+		}
+		break;
+	case SF_DUAL_PARALLEL_FLASH:
+		*addr >>= flash->shift;
+		break;
+	default:
+		debug("SF: Unsupported dual_flash=%d\n", flash->dual_flash);
+		break;
+	}
 }
 #endif
 
@@ -81,6 +158,7 @@ int spi_flash_cmd_wait_ready(struct spi_flash *flash, unsigned long timeout)
 {
 	struct spi_slave *spi = flash->spi;
 	unsigned long timebase;
+	unsigned long flags = SPI_XFER_BEGIN;
 	int ret;
 	u8 status;
 	u8 check_status = 0x0;
@@ -92,7 +170,11 @@ int spi_flash_cmd_wait_ready(struct spi_flash *flash, unsigned long timeout)
 		check_status = poll_bit;
 	}
 
-	ret = spi_xfer(spi, 8, &cmd, NULL, SPI_XFER_BEGIN);
+#ifdef CONFIG_SF_DUAL_FLASH
+	if (spi->flags & SPI_XFER_U_PAGE)
+		flags |= SPI_XFER_U_PAGE;
+#endif
+	ret = spi_xfer(spi, 8, &cmd, NULL, flags);
 	if (ret) {
 		debug("SF: fail to read %s status register\n",
 		      cmd == CMD_READ_STATUS ? "read" : "flag");
@@ -165,8 +247,8 @@ int spi_flash_write_common(struct spi_flash *flash, const u8 *cmd,
 
 int spi_flash_cmd_erase_ops(struct spi_flash *flash, u32 offset, size_t len)
 {
-	u32 erase_size;
-	u8 cmd[4];
+	u32 erase_size, erase_addr;
+	u8 cmd[SPI_FLASH_CMD_LEN];
 	int ret = -1;
 
 	erase_size = flash->erase_size;
@@ -177,15 +259,21 @@ int spi_flash_cmd_erase_ops(struct spi_flash *flash, u32 offset, size_t len)
 
 	cmd[0] = flash->erase_cmd;
 	while (len) {
+		erase_addr = offset;
+
+#ifdef CONFIG_SF_DUAL_FLASH
+		if (flash->dual_flash > SF_SINGLE_FLASH)
+			spi_flash_dual_flash(flash, &erase_addr);
+#endif
 #ifdef CONFIG_SPI_FLASH_BAR
-		ret = spi_flash_bank(flash, offset);
+		ret = spi_flash_bank(flash, erase_addr);
 		if (ret < 0)
 			return ret;
 #endif
-		spi_flash_addr(offset, cmd);
+		spi_flash_addr(erase_addr, cmd);
 
 		debug("SF: erase %2x %2x %2x %2x (%x)\n", cmd[0], cmd[1],
-		      cmd[2], cmd[3], offset);
+		      cmd[2], cmd[3], erase_addr);
 
 		ret = spi_flash_write_common(flash, cmd, sizeof(cmd), NULL, 0);
 		if (ret < 0) {
@@ -204,16 +292,23 @@ int spi_flash_cmd_write_ops(struct spi_flash *flash, u32 offset,
 		size_t len, const void *buf)
 {
 	unsigned long byte_addr, page_size;
+	u32 write_addr;
 	size_t chunk_len, actual;
-	u8 cmd[4];
+	u8 cmd[SPI_FLASH_CMD_LEN];
 	int ret = -1;
 
 	page_size = flash->page_size;
 
-	cmd[0] = CMD_PAGE_PROGRAM;
+	cmd[0] = flash->write_cmd;
 	for (actual = 0; actual < len; actual += chunk_len) {
+		write_addr = offset;
+
+#ifdef CONFIG_SF_DUAL_FLASH
+		if (flash->dual_flash > SF_SINGLE_FLASH)
+			spi_flash_dual_flash(flash, &write_addr);
+#endif
 #ifdef CONFIG_SPI_FLASH_BAR
-		ret = spi_flash_bank(flash, offset);
+		ret = spi_flash_bank(flash, write_addr);
 		if (ret < 0)
 			return ret;
 #endif
@@ -223,9 +318,9 @@ int spi_flash_cmd_write_ops(struct spi_flash *flash, u32 offset,
 		if (flash->spi->max_write_size)
 			chunk_len = min(chunk_len, flash->spi->max_write_size);
 
-		spi_flash_addr(offset, cmd);
+		spi_flash_addr(write_addr, cmd);
 
-		debug("PP: 0x%p => cmd = { 0x%02x 0x%02x%02x%02x } chunk_len = %zu\n",
+		debug("SF: 0x%p => cmd = { 0x%02x 0x%02x%02x%02x } chunk_len = %zu\n",
 		      buf + actual, cmd[0], cmd[1], cmd[2], cmd[3], chunk_len);
 
 		ret = spi_flash_write_common(flash, cmd, sizeof(cmd),
@@ -267,41 +362,55 @@ int spi_flash_read_common(struct spi_flash *flash, const u8 *cmd,
 int spi_flash_cmd_read_ops(struct spi_flash *flash, u32 offset,
 		size_t len, void *data)
 {
-	u8 cmd[5], bank_sel = 0;
-	u32 remain_len, read_len;
+	u8 *cmd, cmdsz;
+	u32 remain_len, read_len, read_addr;
+	int bank_sel = 0;
 	int ret = -1;
 
 	/* Handle memory-mapped SPI */
 	if (flash->memory_map) {
+		ret = spi_claim_bus(flash->spi);
+		if (ret) {
+			debug("SF: unable to claim SPI bus\n");
+			return ret;
+		}
 		spi_xfer(flash->spi, 0, NULL, NULL, SPI_XFER_MMAP);
 		memcpy(data, flash->memory_map + offset, len);
 		spi_xfer(flash->spi, 0, NULL, NULL, SPI_XFER_MMAP_END);
+		spi_release_bus(flash->spi);
 		return 0;
 	}
 
-	cmd[0] = CMD_READ_ARRAY_FAST;
-	cmd[4] = 0x00;
+	cmdsz = SPI_FLASH_CMD_LEN + flash->dummy_byte;
+	cmd = calloc(1, cmdsz);
+	if (!cmd) {
+		debug("SF: Failed to allocate cmd\n");
+		return -ENOMEM;
+	}
 
+	cmd[0] = flash->read_cmd;
 	while (len) {
-#ifdef CONFIG_SPI_FLASH_BAR
-		bank_sel = offset / SPI_FLASH_16MB_BOUN;
+		read_addr = offset;
 
-		ret = spi_flash_cmd_bankaddr_write(flash, bank_sel);
-		if (ret) {
-			debug("SF: fail to set bank%d\n", bank_sel);
+#ifdef CONFIG_SF_DUAL_FLASH
+		if (flash->dual_flash > SF_SINGLE_FLASH)
+			spi_flash_dual_flash(flash, &read_addr);
+#endif
+#ifdef CONFIG_SPI_FLASH_BAR
+		bank_sel = spi_flash_bank(flash, read_addr);
+		if (bank_sel < 0)
 			return ret;
-		}
 #endif
-		remain_len = (SPI_FLASH_16MB_BOUN * (bank_sel + 1)) - offset;
+		remain_len = ((SPI_FLASH_16MB_BOUN << flash->shift) *
+				(bank_sel + 1)) - offset;
 		if (len < remain_len)
 			read_len = len;
 		else
 			read_len = remain_len;
 
-		spi_flash_addr(offset, cmd);
+		spi_flash_addr(read_addr, cmd);
 
-		ret = spi_flash_read_common(flash, cmd, sizeof(cmd),
-							data, read_len);
+		ret = spi_flash_read_common(flash, cmd, cmdsz, data, read_len);
 		if (ret < 0) {
 			debug("SF: read failed\n");
 			break;
diff --git a/drivers/mtd/spi/sf_params.c b/drivers/mtd/spi/sf_params.c
new file mode 100644
index 0000000000..eb372b7575
--- /dev/null
+++ b/drivers/mtd/spi/sf_params.c
@@ -0,0 +1,131 @@
+/*
+ * SPI flash Params table
+ *
+ * Copyright (C) 2013 Jagannadha Sutradharudu Teki, Xilinx Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <spi_flash.h>
+
+#include "sf_internal.h"
+
+/* SPI/QSPI flash device params structure */
+const struct spi_flash_params spi_flash_params_table[] = {
+#ifdef CONFIG_SPI_FLASH_ATMEL		/* ATMEL */
+	{"AT45DB011D",	   0x1f2200, 0x0,	64 * 1024,     4,	0,		    SECT_4K},
+	{"AT45DB021D",	   0x1f2300, 0x0,	64 * 1024,     8,	0,		    SECT_4K},
+	{"AT45DB041D",	   0x1f2400, 0x0,	64 * 1024,     8,	0,		    SECT_4K},
+	{"AT45DB081D",	   0x1f2500, 0x0,	64 * 1024,    16,	0,		    SECT_4K},
+	{"AT45DB161D",	   0x1f2600, 0x0,	64 * 1024,    32,	0,		    SECT_4K},
+	{"AT45DB321D",	   0x1f2700, 0x0,	64 * 1024,    64,	0,		    SECT_4K},
+	{"AT45DB641D",	   0x1f2800, 0x0,	64 * 1024,   128,	0,		    SECT_4K},
+	{"AT25DF321",      0x1f4701, 0x0,	64 * 1024,    64,	0,		    SECT_4K},
+#endif
+#ifdef CONFIG_SPI_FLASH_EON		/* EON */
+	{"EN25Q32B",	   0x1c3016, 0x0,	64 * 1024,    64,	0,			  0},
+	{"EN25Q64",	   0x1c3017, 0x0,	64 * 1024,   128,	0,		    SECT_4K},
+	{"EN25Q128B",	   0x1c3018, 0x0,       64 * 1024,   256,	0,			  0},
+	{"EN25S64",	   0x1c3817, 0x0,	64 * 1024,   128,	0,			  0},
+#endif
+#ifdef CONFIG_SPI_FLASH_GIGADEVICE	/* GIGADEVICE */
+	{"GD25Q64B",	   0xc84017, 0x0,	64 * 1024,   128,	0,		    SECT_4K},
+	{"GD25LQ32",	   0xc86016, 0x0,	64 * 1024,    64,	0,		    SECT_4K},
+#endif
+#ifdef CONFIG_SPI_FLASH_MACRONIX	/* MACRONIX */
+	{"MX25L2006E",	   0xc22012, 0x0,	64 * 1024,     4,	0,			  0},
+	{"MX25L4005",	   0xc22013, 0x0,	64 * 1024,     8,	0,			  0},
+	{"MX25L8005",	   0xc22014, 0x0,	64 * 1024,    16,	0,			  0},
+	{"MX25L1605D",	   0xc22015, 0x0,	64 * 1024,    32,	0,			  0},
+	{"MX25L3205D",	   0xc22016, 0x0,	64 * 1024,    64,	0,			  0},
+	{"MX25L6405D",	   0xc22017, 0x0,	64 * 1024,   128,	0,			  0},
+	{"MX25L12805",	   0xc22018, 0x0,	64 * 1024,   256, RD_FULL,		     WR_QPP},
+	{"MX25L25635F",	   0xc22019, 0x0,	64 * 1024,   512, RD_FULL,		     WR_QPP},
+	{"MX25L51235F",	   0xc2201a, 0x0,	64 * 1024,  1024, RD_FULL,		     WR_QPP},
+	{"MX25L12855E",	   0xc22618, 0x0,	64 * 1024,   256, RD_FULL,		     WR_QPP},
+#endif
+#ifdef CONFIG_SPI_FLASH_SPANSION	/* SPANSION */
+	{"S25FL008A",	   0x010213, 0x0,	64 * 1024,    16,	0,			  0},
+	{"S25FL016A",	   0x010214, 0x0,	64 * 1024,    32,	0,			  0},
+	{"S25FL032A",	   0x010215, 0x0,	64 * 1024,    64,	0,			  0},
+	{"S25FL064A",	   0x010216, 0x0,	64 * 1024,   128,	0,			  0},
+	{"S25FL128P_256K", 0x012018, 0x0300,   256 * 1024,    64, RD_FULL,		     WR_QPP},
+	{"S25FL128P_64K",  0x012018, 0x0301,    64 * 1024,   256, RD_FULL,		     WR_QPP},
+	{"S25FL032P",	   0x010215, 0x4d00,    64 * 1024,    64, RD_FULL,		     WR_QPP},
+	{"S25FL064P",	   0x010216, 0x4d00,    64 * 1024,   128, RD_FULL,		     WR_QPP},
+	{"S25FL128S_256K", 0x012018, 0x4d00,   256 * 1024,    64, RD_FULL,		     WR_QPP},
+	{"S25FL128S_64K",  0x012018, 0x4d01,    64 * 1024,   256, RD_FULL,		     WR_QPP},
+	{"S25FL256S_256K", 0x010219, 0x4d00,   256 * 1024,   128, RD_FULL,		     WR_QPP},
+	{"S25FL256S_64K",  0x010219, 0x4d01,	64 * 1024,   512, RD_FULL,		     WR_QPP},
+	{"S25FL512S_256K", 0x010220, 0x4d00,   256 * 1024,   256, RD_FULL,		     WR_QPP},
+	{"S25FL512S_64K",  0x010220, 0x4d01,    64 * 1024,  1024, RD_FULL,		     WR_QPP},
+#endif
+#ifdef CONFIG_SPI_FLASH_STMICRO		/* STMICRO */
+	{"M25P10",	   0x202011, 0x0,	32 * 1024,     4,	0,			  0},
+	{"M25P20",	   0x202012, 0x0,       64 * 1024,     4,	0,			  0},
+	{"M25P40",	   0x202013, 0x0,       64 * 1024,     8,	0,			  0},
+	{"M25P80",	   0x202014, 0x0,       64 * 1024,    16,	0,			  0},
+	{"M25P16",	   0x202015, 0x0,       64 * 1024,    32,	0,			  0},
+	{"M25P32",	   0x202016, 0x0,       64 * 1024,    64,	0,			  0},
+	{"M25P64",	   0x202017, 0x0,       64 * 1024,   128,	0,			  0},
+	{"M25P128",	   0x202018, 0x0,      256 * 1024,    64,	0,			  0},
+	{"N25Q32",	   0x20ba16, 0x0,       64 * 1024,    64, RD_FULL,	   WR_QPP | SECT_4K},
+	{"N25Q32A",	   0x20bb16, 0x0,       64 * 1024,    64, RD_FULL,	   WR_QPP | SECT_4K},
+	{"N25Q64",	   0x20ba17, 0x0,       64 * 1024,   128, RD_FULL,	   WR_QPP | SECT_4K},
+	{"N25Q64A",	   0x20bb17, 0x0,       64 * 1024,   128, RD_FULL,	   WR_QPP | SECT_4K},
+	{"N25Q128",	   0x20ba18, 0x0,       64 * 1024,   256, RD_FULL,		     WR_QPP},
+	{"N25Q128A",	   0x20bb18, 0x0,       64 * 1024,   256, RD_FULL,		     WR_QPP},
+	{"N25Q256",	   0x20ba19, 0x0,       64 * 1024,   512, RD_FULL,	   WR_QPP | SECT_4K},
+	{"N25Q256A",	   0x20bb19, 0x0,       64 * 1024,   512, RD_FULL,	   WR_QPP | SECT_4K},
+	{"N25Q512",	   0x20ba20, 0x0,       64 * 1024,  1024, RD_FULL, WR_QPP | E_FSR | SECT_4K},
+	{"N25Q512A",	   0x20bb20, 0x0,       64 * 1024,  1024, RD_FULL, WR_QPP | E_FSR | SECT_4K},
+	{"N25Q1024",	   0x20ba21, 0x0,       64 * 1024,  2048, RD_FULL, WR_QPP | E_FSR | SECT_4K},
+	{"N25Q1024A",	   0x20bb21, 0x0,       64 * 1024,  2048, RD_FULL, WR_QPP | E_FSR | SECT_4K},
+#endif
+#ifdef CONFIG_SPI_FLASH_SST		/* SST */
+	{"SST25VF040B",	   0xbf258d, 0x0,	64 * 1024,     8,	0,          SECT_4K | SST_WP},
+	{"SST25VF080B",	   0xbf258e, 0x0,	64 * 1024,    16,	0,	    SECT_4K | SST_WP},
+	{"SST25VF016B",	   0xbf2541, 0x0,	64 * 1024,    32,	0,	    SECT_4K | SST_WP},
+	{"SST25VF032B",	   0xbf254a, 0x0,	64 * 1024,    64,	0,	    SECT_4K | SST_WP},
+	{"SST25VF064C",	   0xbf254b, 0x0,	64 * 1024,   128,	0,		     SECT_4K},
+	{"SST25WF512",	   0xbf2501, 0x0,	64 * 1024,     1,	0,	    SECT_4K | SST_WP},
+	{"SST25WF010",	   0xbf2502, 0x0,	64 * 1024,     2,       0,          SECT_4K | SST_WP},
+	{"SST25WF020",	   0xbf2503, 0x0,	64 * 1024,     4,       0,	    SECT_4K | SST_WP},
+	{"SST25WF040",	   0xbf2504, 0x0,	64 * 1024,     8,       0,	    SECT_4K | SST_WP},
+	{"SST25WF080",	   0xbf2505, 0x0,	64 * 1024,    16,       0,	    SECT_4K | SST_WP},
+#endif
+#ifdef CONFIG_SPI_FLASH_WINBOND		/* WINBOND */
+	{"W25P80",	   0xef2014, 0x0,	64 * 1024,    16,	0,		           0},
+	{"W25P16",	   0xef2015, 0x0,	64 * 1024,    32,	0,		           0},
+	{"W25P32",	   0xef2016, 0x0,	64 * 1024,    64,	0,		           0},
+	{"W25X40",	   0xef3013, 0x0,	64 * 1024,     8,	0,		     SECT_4K},
+	{"W25X16",	   0xef3015, 0x0,	64 * 1024,    32,	0,		     SECT_4K},
+	{"W25X32",	   0xef3016, 0x0,	64 * 1024,    64,	0,		     SECT_4K},
+	{"W25X64",	   0xef3017, 0x0,	64 * 1024,   128,	0,		     SECT_4K},
+	{"W25Q80BL",	   0xef4014, 0x0,	64 * 1024,    16, RD_FULL,	    WR_QPP | SECT_4K},
+	{"W25Q16CL",	   0xef4015, 0x0,	64 * 1024,    32, RD_FULL,	    WR_QPP | SECT_4K},
+	{"W25Q32BV",	   0xef4016, 0x0,	64 * 1024,    64, RD_FULL,	    WR_QPP | SECT_4K},
+	{"W25Q64CV",	   0xef4017, 0x0,	64 * 1024,   128, RD_FULL,	    WR_QPP | SECT_4K},
+	{"W25Q128BV",	   0xef4018, 0x0,	64 * 1024,   256, RD_FULL,	    WR_QPP | SECT_4K},
+	{"W25Q256",	   0xef4019, 0x0,	64 * 1024,   512, RD_FULL,	    WR_QPP | SECT_4K},
+	{"W25Q80BW",	   0xef5014, 0x0,	64 * 1024,    16, RD_FULL,	    WR_QPP | SECT_4K},
+	{"W25Q16DW",	   0xef6015, 0x0,	64 * 1024,    32, RD_FULL,	    WR_QPP | SECT_4K},
+	{"W25Q32DW",	   0xef6016, 0x0,	64 * 1024,    64, RD_FULL,	    WR_QPP | SECT_4K},
+	{"W25Q64DW",	   0xef6017, 0x0,	64 * 1024,   128, RD_FULL,	    WR_QPP | SECT_4K},
+	{"W25Q128FW",	   0xef6018, 0x0,	64 * 1024,   256, RD_FULL,	    WR_QPP | SECT_4K},
+#endif
+	/*
+	 * Note:
+	 * Below paired flash devices has similar spi_flash params.
+	 * (S25FL129P_64K, S25FL128S_64K)
+	 * (W25Q80BL, W25Q80BV)
+	 * (W25Q16CL, W25Q16DV)
+	 * (W25Q32BV, W25Q32FV_SPI)
+	 * (W25Q64CV, W25Q64FV_SPI)
+	 * (W25Q128BV, W25Q128FV_SPI)
+	 * (W25Q32DW, W25Q32FV_QPI)
+	 * (W25Q64DW, W25Q64FV_QPI)
+	 * (W25Q128FW, W25Q128FV_QPI)
+	 */
+};
diff --git a/drivers/mtd/spi/sf_probe.c b/drivers/mtd/spi/sf_probe.c
index 5eb8ffe843..0a46fe38da 100644
--- a/drivers/mtd/spi/sf_probe.c
+++ b/drivers/mtd/spi/sf_probe.c
@@ -13,158 +13,99 @@
 #include <malloc.h>
 #include <spi.h>
 #include <spi_flash.h>
+#include <asm/io.h>
 
 #include "sf_internal.h"
 
 DECLARE_GLOBAL_DATA_PTR;
 
-/**
- * struct spi_flash_params - SPI/QSPI flash device params structure
- *
- * @name:		Device name ([MANUFLETTER][DEVTYPE][DENSITY][EXTRAINFO])
- * @jedec:		Device jedec ID (0x[1byte_manuf_id][2byte_dev_id])
- * @ext_jedec:		Device ext_jedec ID
- * @sector_size:	Sector size of this device
- * @nr_sectors:		No.of sectors on this device
- * @flags:		Importent param, for flash specific behaviour
- */
-struct spi_flash_params {
-	const char *name;
-	u32 jedec;
-	u16 ext_jedec;
-	u32 sector_size;
-	u32 nr_sectors;
-	u16 flags;
+/* Read commands array */
+static u8 spi_read_cmds_array[] = {
+	CMD_READ_ARRAY_SLOW,
+	CMD_READ_DUAL_OUTPUT_FAST,
+	CMD_READ_DUAL_IO_FAST,
+	CMD_READ_QUAD_OUTPUT_FAST,
+	CMD_READ_QUAD_IO_FAST,
 };
 
-static const struct spi_flash_params spi_flash_params_table[] = {
-#ifdef CONFIG_SPI_FLASH_ATMEL		/* ATMEL */
-	{"AT45DB011D",	   0x1f2200, 0x0,	64 * 1024,     4,	       SECT_4K},
-	{"AT45DB021D",	   0x1f2300, 0x0,	64 * 1024,     8,	       SECT_4K},
-	{"AT45DB041D",	   0x1f2400, 0x0,	64 * 1024,     8,	       SECT_4K},
-	{"AT45DB081D",	   0x1f2500, 0x0,	64 * 1024,    16,	       SECT_4K},
-	{"AT45DB161D",	   0x1f2600, 0x0,	64 * 1024,    32,	       SECT_4K},
-	{"AT45DB321D",	   0x1f2700, 0x0,	64 * 1024,    64,	       SECT_4K},
-	{"AT45DB641D",	   0x1f2800, 0x0,	64 * 1024,   128,	       SECT_4K},
-	{"AT25DF321",      0x1f4701, 0x0,	64 * 1024,    64,	       SECT_4K},
-#endif
-#ifdef CONFIG_SPI_FLASH_EON		/* EON */
-	{"EN25Q32B",	   0x1c3016, 0x0,	64 * 1024,    64,	             0},
-	{"EN25Q64",	   0x1c3017, 0x0,	64 * 1024,   128,	       SECT_4K},
-	{"EN25Q128B",	   0x1c3018, 0x0,       64 * 1024,   256,	             0},
-	{"EN25S64",	   0x1c3817, 0x0,	64 * 1024,   128,		     0},
-#endif
-#ifdef CONFIG_SPI_FLASH_GIGADEVICE	/* GIGADEVICE */
-	{"GD25Q64B",	   0xc84017, 0x0,	64 * 1024,   128,	       SECT_4K},
-	{"GD25LQ32",	   0xc86016, 0x0,	64 * 1024,    64,	       SECT_4K},
-#endif
-#ifdef CONFIG_SPI_FLASH_MACRONIX	/* MACRONIX */
-	{"MX25L4005",	   0xc22013, 0x0,	64 * 1024,     8,	             0},
-	{"MX25L8005",	   0xc22014, 0x0,	64 * 1024,    16,	             0},
-	{"MX25L1605D",	   0xc22015, 0x0,	64 * 1024,    32,	             0},
-	{"MX25L3205D",	   0xc22016, 0x0,	64 * 1024,    64,	             0},
-	{"MX25L6405D",	   0xc22017, 0x0,	64 * 1024,   128,	             0},
-	{"MX25L12805",	   0xc22018, 0x0,	64 * 1024,   256,	             0},
-	{"MX25L25635F",	   0xc22019, 0x0,	64 * 1024,   512,	             0},
-	{"MX25L51235F",	   0xc2201A, 0x0,	64 * 1024,  1024,	             0},
-	{"MX25L12855E",	   0xc22618, 0x0,	64 * 1024,   256,	             0},
+#ifdef CONFIG_SPI_FLASH_MACRONIX
+static int spi_flash_set_qeb_mxic(struct spi_flash *flash)
+{
+	u8 qeb_status;
+	int ret;
+
+	ret = spi_flash_cmd_read_status(flash, &qeb_status);
+	if (ret < 0)
+		return ret;
+
+	if (qeb_status & STATUS_QEB_MXIC) {
+		debug("SF: mxic: QEB is already set\n");
+	} else {
+		ret = spi_flash_cmd_write_status(flash, STATUS_QEB_MXIC);
+		if (ret < 0)
+			return ret;
+	}
+
+	return ret;
+}
 #endif
-#ifdef CONFIG_SPI_FLASH_SPANSION	/* SPANSION */
-	{"S25FL008A",	   0x010213, 0x0,	64 * 1024,    16,	             0},
-	{"S25FL016A",	   0x010214, 0x0,	64 * 1024,    32,	             0},
-	{"S25FL032A",	   0x010215, 0x0,	64 * 1024,    64,	             0},
-	{"S25FL064A",	   0x010216, 0x0,	64 * 1024,   128,	             0},
-	{"S25FL128P_256K", 0x012018, 0x0300,   256 * 1024,    64,	             0},
-	{"S25FL128P_64K",  0x012018, 0x0301,    64 * 1024,   256,	             0},
-	{"S25FL032P",	   0x010215, 0x4d00,    64 * 1024,    64,	             0},
-	{"S25FL064P",	   0x010216, 0x4d00,    64 * 1024,   128,	             0},
-	{"S25FL128S_64K",  0x012018, 0x4d01,    64 * 1024,   256,		     0},
-	{"S25FL256S_256K", 0x010219, 0x4d00,    64 * 1024,   512,	             0},
-	{"S25FL256S_64K",  0x010219, 0x4d01,    64 * 1024,   512,	             0},
-	{"S25FL512S_256K", 0x010220, 0x4d00,    64 * 1024,  1024,	             0},
-	{"S25FL512S_64K",  0x010220, 0x4d01,    64 * 1024,  1024,	             0},
+
+#if defined(CONFIG_SPI_FLASH_SPANSION) || defined(CONFIG_SPI_FLASH_WINBOND)
+static int spi_flash_set_qeb_winspan(struct spi_flash *flash)
+{
+	u8 qeb_status;
+	int ret;
+
+	ret = spi_flash_cmd_read_config(flash, &qeb_status);
+	if (ret < 0)
+		return ret;
+
+	if (qeb_status & STATUS_QEB_WINSPAN) {
+		debug("SF: winspan: QEB is already set\n");
+	} else {
+		ret = spi_flash_cmd_write_config(flash, STATUS_QEB_WINSPAN);
+		if (ret < 0)
+			return ret;
+	}
+
+	return ret;
+}
 #endif
-#ifdef CONFIG_SPI_FLASH_STMICRO		/* STMICRO */
-	{"M25P10",	   0x202011, 0x0,       32 * 1024,     4,	             0},
-	{"M25P20",	   0x202012, 0x0,       64 * 1024,     4,	             0},
-	{"M25P40",	   0x202013, 0x0,       64 * 1024,     8,	             0},
-	{"M25P80",	   0x202014, 0x0,       64 * 1024,    16,	             0},
-	{"M25P16",	   0x202015, 0x0,       64 * 1024,    32,	             0},
-	{"M25P32",	   0x202016, 0x0,       64 * 1024,    64,	             0},
-	{"M25P64",	   0x202017, 0x0,       64 * 1024,   128,	             0},
-	{"M25P128",	   0x202018, 0x0,      256 * 1024,    64,	             0},
-	{"N25Q32",	   0x20ba16, 0x0,       64 * 1024,    64,	       SECT_4K},
-	{"N25Q32A",	   0x20bb16, 0x0,       64 * 1024,    64,	       SECT_4K},
-	{"N25Q64",	   0x20ba17, 0x0,       64 * 1024,   128,	       SECT_4K},
-	{"N25Q64A",	   0x20bb17, 0x0,       64 * 1024,   128,	       SECT_4K},
-	{"N25Q128",	   0x20ba18, 0x0,       64 * 1024,   256,	       SECT_4K},
-	{"N25Q128A",	   0x20bb18, 0x0,       64 * 1024,   256,	       SECT_4K},
-	{"N25Q256",	   0x20ba19, 0x0,       64 * 1024,   512,	       SECT_4K},
-	{"N25Q256A",	   0x20bb19, 0x0,       64 * 1024,   512,	       SECT_4K},
-	{"N25Q512",	   0x20ba20, 0x0,       64 * 1024,  1024,      E_FSR | SECT_4K},
-	{"N25Q512A",	   0x20bb20, 0x0,       64 * 1024,  1024,      E_FSR | SECT_4K},
-	{"N25Q1024",	   0x20ba21, 0x0,       64 * 1024,  2048,      E_FSR | SECT_4K},
-	{"N25Q1024A",	   0x20bb21, 0x0,       64 * 1024,  2048,      E_FSR | SECT_4K},
+
+static int spi_flash_set_qeb(struct spi_flash *flash, u8 idcode0)
+{
+	switch (idcode0) {
+#ifdef CONFIG_SPI_FLASH_MACRONIX
+	case SPI_FLASH_CFI_MFR_MACRONIX:
+		return spi_flash_set_qeb_mxic(flash);
 #endif
-#ifdef CONFIG_SPI_FLASH_SST		/* SST */
-	{"SST25VF040B",	   0xbf258d, 0x0,	64 * 1024,     8,     SECT_4K | SST_WP},
-	{"SST25VF080B",	   0xbf258e, 0x0,	64 * 1024,    16,     SECT_4K | SST_WP},
-	{"SST25VF016B",	   0xbf2541, 0x0,	64 * 1024,    32,     SECT_4K | SST_WP},
-	{"SST25VF032B",	   0xbf254a, 0x0,	64 * 1024,    64,     SECT_4K | SST_WP},
-	{"SST25VF064C",	   0xbf254b, 0x0,	64 * 1024,   128,	       SECT_4K},
-	{"SST25WF512",	   0xbf2501, 0x0,	64 * 1024,     1,     SECT_4K | SST_WP},
-	{"SST25WF010",	   0xbf2502, 0x0,	64 * 1024,     2,     SECT_4K | SST_WP},
-	{"SST25WF020",	   0xbf2503, 0x0,	64 * 1024,     4,     SECT_4K | SST_WP},
-	{"SST25WF040",	   0xbf2504, 0x0,	64 * 1024,     8,     SECT_4K | SST_WP},
-	{"SST25WF080",	   0xbf2505, 0x0,	64 * 1024,    16,     SECT_4K | SST_WP},
+#if defined(CONFIG_SPI_FLASH_SPANSION) || defined(CONFIG_SPI_FLASH_WINBOND)
+	case SPI_FLASH_CFI_MFR_SPANSION:
+	case SPI_FLASH_CFI_MFR_WINBOND:
+		return spi_flash_set_qeb_winspan(flash);
 #endif
-#ifdef CONFIG_SPI_FLASH_WINBOND		/* WINBOND */
-	{"W25P80",	   0xef2014, 0x0,	64 * 1024,    16,		    0},
-	{"W25P16",	   0xef2015, 0x0,	64 * 1024,    32,		    0},
-	{"W25P32",	   0xef2016, 0x0,	64 * 1024,    64,		    0},
-	{"W25X40",	   0xef3013, 0x0,	64 * 1024,     8,	      SECT_4K},
-	{"W25X16",	   0xef3015, 0x0,	64 * 1024,    32,	      SECT_4K},
-	{"W25X32",	   0xef3016, 0x0,	64 * 1024,    64,	      SECT_4K},
-	{"W25X64",	   0xef3017, 0x0,	64 * 1024,   128,	      SECT_4K},
-	{"W25Q80BL",	   0xef4014, 0x0,	64 * 1024,    16,	      SECT_4K},
-	{"W25Q16CL",	   0xef4015, 0x0,	64 * 1024,    32,	      SECT_4K},
-	{"W25Q32BV",	   0xef4016, 0x0,	64 * 1024,    64,	      SECT_4K},
-	{"W25Q64CV",	   0xef4017, 0x0,	64 * 1024,   128,	      SECT_4K},
-	{"W25Q128BV",	   0xef4018, 0x0,	64 * 1024,   256,	      SECT_4K},
-	{"W25Q256",	   0xef4019, 0x0,	64 * 1024,   512,	      SECT_4K},
-	{"W25Q80BW",	   0xef5014, 0x0,	64 * 1024,    16,	      SECT_4K},
-	{"W25Q16DW",	   0xef6015, 0x0,	64 * 1024,    32,	      SECT_4K},
-	{"W25Q32DW",	   0xef6016, 0x0,	64 * 1024,    64,	      SECT_4K},
-	{"W25Q64DW",	   0xef6017, 0x0,	64 * 1024,   128,	      SECT_4K},
-	{"W25Q128FW",	   0xef6018, 0x0,	64 * 1024,   256,	      SECT_4K},
+#ifdef CONFIG_SPI_FLASH_STMICRO
+	case SPI_FLASH_CFI_MFR_STMICRO:
+		debug("SF: QEB is volatile for %02x flash\n", idcode0);
+		return 0;
 #endif
-	/*
-	 * Note:
-	 * Below paired flash devices has similar spi_flash params.
-	 * (S25FL129P_64K, S25FL128S_64K)
-	 * (W25Q80BL, W25Q80BV)
-	 * (W25Q16CL, W25Q16DV)
-	 * (W25Q32BV, W25Q32FV_SPI)
-	 * (W25Q64CV, W25Q64FV_SPI)
-	 * (W25Q128BV, W25Q128FV_SPI)
-	 * (W25Q32DW, W25Q32FV_QPI)
-	 * (W25Q64DW, W25Q64FV_QPI)
-	 * (W25Q128FW, W25Q128FV_QPI)
-	 */
-};
+	default:
+		printf("SF: Need set QEB func for %02x flash\n", idcode0);
+		return -1;
+	}
+}
 
 static struct spi_flash *spi_flash_validate_params(struct spi_slave *spi,
 		u8 *idcode)
 {
 	const struct spi_flash_params *params;
 	struct spi_flash *flash;
-	int i;
+	u8 cmd;
 	u16 jedec = idcode[1] << 8 | idcode[2];
 	u16 ext_jedec = idcode[3] << 8 | idcode[4];
 
-	/* Get the flash id (jedec = manuf_id + dev_id, ext_jedec) */
-	for (i = 0; i < ARRAY_SIZE(spi_flash_params_table); i++) {
-		params = &spi_flash_params_table[i];
+	params = spi_flash_params_table;
+	for (; params->name != NULL; params++) {
 		if ((params->jedec >> 16) == idcode[0]) {
 			if ((params->jedec & 0xFFFF) == jedec) {
 				if (params->ext_jedec == 0)
@@ -175,24 +116,24 @@ static struct spi_flash *spi_flash_validate_params(struct spi_slave *spi,
 		}
 	}
 
-	if (i == ARRAY_SIZE(spi_flash_params_table)) {
+	if (!params->name) {
 		printf("SF: Unsupported flash IDs: ");
 		printf("manuf %02x, jedec %04x, ext_jedec %04x\n",
 		       idcode[0], jedec, ext_jedec);
 		return NULL;
 	}
 
-	flash = malloc(sizeof(*flash));
+	flash = calloc(1, sizeof(*flash));
 	if (!flash) {
 		debug("SF: Failed to allocate spi_flash\n");
 		return NULL;
 	}
-	memset(flash, '\0', sizeof(*flash));
 
 	/* Assign spi data */
 	flash->spi = spi;
 	flash->name = params->name;
 	flash->memory_map = spi->memory_map;
+	flash->dual_flash = flash->spi->option;
 
 	/* Assign spi_flash ops */
 	flash->write = spi_flash_cmd_write_ops;
@@ -204,23 +145,88 @@ static struct spi_flash *spi_flash_validate_params(struct spi_slave *spi,
 	flash->read = spi_flash_cmd_read_ops;
 
 	/* Compute the flash size */
-	flash->page_size = (ext_jedec == 0x4d00) ? 512 : 256;
-	flash->sector_size = params->sector_size;
-	flash->size = flash->sector_size * params->nr_sectors;
+	flash->shift = (flash->dual_flash & SF_DUAL_PARALLEL_FLASH) ? 1 : 0;
+	/*
+	 * The Spansion S25FL032P and S25FL064P have 256b pages, yet use the
+	 * 0x4d00 Extended JEDEC code. The rest of the Spansion flashes with
+	 * the 0x4d00 Extended JEDEC code have 512b pages. All of the others
+	 * have 256b pages.
+	 */
+	if (ext_jedec == 0x4d00) {
+		if ((jedec == 0x0215) || (jedec == 0x216))
+			flash->page_size = 256;
+		else
+			flash->page_size = 512;
+	} else {
+		flash->page_size = 256;
+	}
+	flash->page_size <<= flash->shift;
+	flash->sector_size = params->sector_size << flash->shift;
+	flash->size = flash->sector_size * params->nr_sectors << flash->shift;
+#ifdef CONFIG_SF_DUAL_FLASH
+	if (flash->dual_flash & SF_DUAL_STACKED_FLASH)
+		flash->size <<= 1;
+#endif
 
 	/* Compute erase sector and command */
 	if (params->flags & SECT_4K) {
 		flash->erase_cmd = CMD_ERASE_4K;
-		flash->erase_size = 4096;
+		flash->erase_size = 4096 << flash->shift;
 	} else if (params->flags & SECT_32K) {
 		flash->erase_cmd = CMD_ERASE_32K;
-		flash->erase_size = 32768;
+		flash->erase_size = 32768 << flash->shift;
 	} else {
 		flash->erase_cmd = CMD_ERASE_64K;
 		flash->erase_size = flash->sector_size;
 	}
 
-	/* Poll cmd seclection */
+	/* Look for the fastest read cmd */
+	cmd = fls(params->e_rd_cmd & flash->spi->op_mode_rx);
+	if (cmd) {
+		cmd = spi_read_cmds_array[cmd - 1];
+		flash->read_cmd = cmd;
+	} else {
+		/* Go for default supported read cmd */
+		flash->read_cmd = CMD_READ_ARRAY_FAST;
+	}
+
+	/* Not require to look for fastest only two write cmds yet */
+	if (params->flags & WR_QPP && flash->spi->op_mode_tx & SPI_OPM_TX_QPP)
+		flash->write_cmd = CMD_QUAD_PAGE_PROGRAM;
+	else
+		/* Go for default supported write cmd */
+		flash->write_cmd = CMD_PAGE_PROGRAM;
+
+	/* Set the quad enable bit - only for quad commands */
+	if ((flash->read_cmd == CMD_READ_QUAD_OUTPUT_FAST) ||
+	    (flash->read_cmd == CMD_READ_QUAD_IO_FAST) ||
+	    (flash->write_cmd == CMD_QUAD_PAGE_PROGRAM)) {
+		if (spi_flash_set_qeb(flash, idcode[0])) {
+			debug("SF: Fail to set QEB for %02x\n", idcode[0]);
+			return NULL;
+		}
+	}
+
+	/* Read dummy_byte: dummy byte is determined based on the
+	 * dummy cycles of a particular command.
+	 * Fast commands - dummy_byte = dummy_cycles/8
+	 * I/O commands- dummy_byte = (dummy_cycles * no.of lines)/8
+	 * For I/O commands except cmd[0] everything goes on no.of lines
+	 * based on particular command but incase of fast commands except
+	 * data all go on single line irrespective of command.
+	 */
+	switch (flash->read_cmd) {
+	case CMD_READ_QUAD_IO_FAST:
+		flash->dummy_byte = 2;
+		break;
+	case CMD_READ_ARRAY_SLOW:
+		flash->dummy_byte = 0;
+		break;
+	default:
+		flash->dummy_byte = 1;
+	}
+
+	/* Poll cmd selection */
 	flash->poll_cmd = CMD_READ_STATUS;
 #ifdef CONFIG_SPI_FLASH_STMICRO
 	if (params->flags & E_FSR)
@@ -279,22 +285,19 @@ int spi_flash_decode_fdt(const void *blob, struct spi_flash *flash)
 		debug("%s: Memory map must cover entire device\n", __func__);
 		return -1;
 	}
-	flash->memory_map = (void *)addr;
+	flash->memory_map = map_sysmem(addr, size);
 
 	return 0;
 }
 #endif /* CONFIG_OF_CONTROL */
 
-struct spi_flash *spi_flash_probe(unsigned int bus, unsigned int cs,
-		unsigned int max_hz, unsigned int spi_mode)
+static struct spi_flash *spi_flash_probe_slave(struct spi_slave *spi)
 {
-	struct spi_slave *spi;
 	struct spi_flash *flash = NULL;
 	u8 idcode[5];
 	int ret;
 
 	/* Setup spi_slave */
-	spi = spi_setup_slave(bus, cs, max_hz, spi_mode);
 	if (!spi) {
 		printf("SF: Failed to set up slave\n");
 		return NULL;
@@ -340,7 +343,10 @@ struct spi_flash *spi_flash_probe(unsigned int bus, unsigned int cs,
 	puts("\n");
 #endif
 #ifndef CONFIG_SPI_FLASH_BAR
-	if (flash->size > SPI_FLASH_16MB_BOUN) {
+	if (((flash->dual_flash == SF_SINGLE_FLASH) &&
+	     (flash->size > SPI_FLASH_16MB_BOUN)) ||
+	     ((flash->dual_flash > SF_SINGLE_FLASH) &&
+	     (flash->size > SPI_FLASH_16MB_BOUN << 1))) {
 		puts("SF: Warning - Only lower 16MiB accessible,");
 		puts(" Full access #define CONFIG_SPI_FLASH_BAR\n");
 	}
@@ -358,6 +364,26 @@ err_claim_bus:
 	return NULL;
 }
 
+struct spi_flash *spi_flash_probe(unsigned int bus, unsigned int cs,
+		unsigned int max_hz, unsigned int spi_mode)
+{
+	struct spi_slave *spi;
+
+	spi = spi_setup_slave(bus, cs, max_hz, spi_mode);
+	return spi_flash_probe_slave(spi);
+}
+
+#ifdef CONFIG_OF_SPI_FLASH
+struct spi_flash *spi_flash_probe_fdt(const void *blob, int slave_node,
+				      int spi_node)
+{
+	struct spi_slave *spi;
+
+	spi = spi_setup_slave_fdt(blob, slave_node, spi_node);
+	return spi_flash_probe_slave(spi);
+}
+#endif
+
 void spi_flash_free(struct spi_flash *flash)
 {
 	spi_free_slave(flash->spi);
diff --git a/drivers/mtd/ubi/Makefile b/drivers/mtd/ubi/Makefile
index 1a88e9499d..56c2823477 100644
--- a/drivers/mtd/ubi/Makefile
+++ b/drivers/mtd/ubi/Makefile
@@ -5,31 +5,6 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB 	:= $(obj)libubi.o
-
-ifdef CONFIG_CMD_UBI
-COBJS-y += build.o vtbl.o vmt.o upd.o kapi.o eba.o io.o wl.o scan.o crc32.o
-
-COBJS-y += misc.o
-COBJS-y += debug.o
-endif
-
-COBJS	:= $(COBJS-y)
-SRCS 	:= $(COBJS:.o=.c)
-OBJS 	:= $(addprefix $(obj),$(COBJS))
-
-all:	$(LIB)
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y += build.o vtbl.o vmt.o upd.o kapi.o eba.o io.o wl.o scan.o crc32.o
+obj-y += misc.o
+obj-y += debug.o
diff --git a/drivers/net/Makefile b/drivers/net/Makefile
index 18fd54fc66..7f9ce90a6d 100644
--- a/drivers/net/Makefile
+++ b/drivers/net/Makefile
@@ -5,83 +5,61 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	:= $(obj)libnet.o
-
-COBJS-$(CONFIG_PPC4xx_EMAC) += 4xx_enet.o
-COBJS-$(CONFIG_ALTERA_TSE) += altera_tse.o
-COBJS-$(CONFIG_ARMADA100_FEC) += armada100_fec.o
-COBJS-$(CONFIG_DRIVER_AT91EMAC) += at91_emac.o
-COBJS-$(CONFIG_DRIVER_AX88180) += ax88180.o
-COBJS-$(CONFIG_BFIN_MAC) += bfin_mac.o
-COBJS-$(CONFIG_CALXEDA_XGMAC) += calxedaxgmac.o
-COBJS-$(CONFIG_CS8900) += cs8900.o
-COBJS-$(CONFIG_TULIP) += dc2114x.o
-COBJS-$(CONFIG_DESIGNWARE_ETH) += designware.o
-COBJS-$(CONFIG_DRIVER_DM9000) += dm9000x.o
-COBJS-$(CONFIG_DNET) += dnet.o
-COBJS-$(CONFIG_E1000) += e1000.o
-COBJS-$(CONFIG_E1000_SPI) += e1000_spi.o
-COBJS-$(CONFIG_EEPRO100) += eepro100.o
-COBJS-$(CONFIG_ENC28J60) += enc28j60.o
-COBJS-$(CONFIG_EP93XX) += ep93xx_eth.o
-COBJS-$(CONFIG_ETHOC) += ethoc.o
-COBJS-$(CONFIG_FEC_MXC) += fec_mxc.o
-COBJS-$(CONFIG_FSLDMAFEC) += fsl_mcdmafec.o mcfmii.o
-COBJS-$(CONFIG_FTGMAC100) += ftgmac100.o
-COBJS-$(CONFIG_FTMAC110) += ftmac110.o
-COBJS-$(CONFIG_FTMAC100) += ftmac100.o
-COBJS-$(CONFIG_GRETH) += greth.o
-COBJS-$(CONFIG_INCA_IP_SWITCH) += inca-ip_sw.o
-COBJS-$(CONFIG_DRIVER_KS8695ETH) += ks8695eth.o
-COBJS-$(CONFIG_KS8851_MLL) += ks8851_mll.o
-COBJS-$(CONFIG_LAN91C96) += lan91c96.o
-COBJS-$(CONFIG_MACB) += macb.o
-COBJS-$(CONFIG_MCFFEC) += mcffec.o mcfmii.o
-COBJS-$(CONFIG_MPC5xxx_FEC) += mpc5xxx_fec.o
-COBJS-$(CONFIG_MPC512x_FEC) += mpc512x_fec.o
-COBJS-$(CONFIG_MVGBE) += mvgbe.o
-COBJS-$(CONFIG_NATSEMI) += natsemi.o
-COBJS-$(CONFIG_DRIVER_NE2000) += ne2000.o ne2000_base.o
-COBJS-$(CONFIG_DRIVER_AX88796L) += ax88796.o ne2000_base.o
-COBJS-$(CONFIG_NETCONSOLE) += netconsole.o
-COBJS-$(CONFIG_NS8382X) += ns8382x.o
-COBJS-$(CONFIG_PCNET) += pcnet.o
-COBJS-$(CONFIG_PLB2800_ETHER) += plb2800_eth.o
-COBJS-$(CONFIG_RTL8139) += rtl8139.o
-COBJS-$(CONFIG_RTL8169) += rtl8169.o
-COBJS-$(CONFIG_SH_ETHER) += sh_eth.o
-COBJS-$(CONFIG_SMC91111) += smc91111.o
-COBJS-$(CONFIG_SMC911X) += smc911x.o
-COBJS-$(CONFIG_SUNXI_WEMAC) += sunxi_wemac.o
-COBJS-$(CONFIG_DRIVER_TI_EMAC) += davinci_emac.o
-COBJS-$(CONFIG_TSEC_ENET) += tsec.o fsl_mdio.o
-COBJS-$(CONFIG_DRIVER_TI_CPSW) += cpsw.o
-COBJS-$(CONFIG_FMAN_ENET) += fsl_mdio.o
-COBJS-$(CONFIG_TSI108_ETH) += tsi108_eth.o
-COBJS-$(CONFIG_ULI526X) += uli526x.o
-COBJS-$(CONFIG_VSC7385_ENET) += vsc7385.o
-COBJS-$(CONFIG_XILINX_AXIEMAC) += xilinx_axi_emac.o
-COBJS-$(CONFIG_XILINX_EMACLITE) += xilinx_emaclite.o
-COBJS-$(CONFIG_XILINX_LL_TEMAC) += xilinx_ll_temac.o xilinx_ll_temac_mdio.o \
+obj-$(CONFIG_PPC4xx_EMAC) += 4xx_enet.o
+obj-$(CONFIG_ALTERA_TSE) += altera_tse.o
+obj-$(CONFIG_ARMADA100_FEC) += armada100_fec.o
+obj-$(CONFIG_DRIVER_AT91EMAC) += at91_emac.o
+obj-$(CONFIG_DRIVER_AX88180) += ax88180.o
+obj-$(CONFIG_BFIN_MAC) += bfin_mac.o
+obj-$(CONFIG_CALXEDA_XGMAC) += calxedaxgmac.o
+obj-$(CONFIG_CS8900) += cs8900.o
+obj-$(CONFIG_TULIP) += dc2114x.o
+obj-$(CONFIG_DESIGNWARE_ETH) += designware.o
+obj-$(CONFIG_DRIVER_DM9000) += dm9000x.o
+obj-$(CONFIG_DNET) += dnet.o
+obj-$(CONFIG_E1000) += e1000.o
+obj-$(CONFIG_E1000_SPI) += e1000_spi.o
+obj-$(CONFIG_EEPRO100) += eepro100.o
+obj-$(CONFIG_ENC28J60) += enc28j60.o
+obj-$(CONFIG_EP93XX) += ep93xx_eth.o
+obj-$(CONFIG_ETHOC) += ethoc.o
+obj-$(CONFIG_FEC_MXC) += fec_mxc.o
+obj-$(CONFIG_FSLDMAFEC) += fsl_mcdmafec.o mcfmii.o
+obj-$(CONFIG_FTGMAC100) += ftgmac100.o
+obj-$(CONFIG_FTMAC110) += ftmac110.o
+obj-$(CONFIG_FTMAC100) += ftmac100.o
+obj-$(CONFIG_GRETH) += greth.o
+obj-$(CONFIG_INCA_IP_SWITCH) += inca-ip_sw.o
+obj-$(CONFIG_DRIVER_KS8695ETH) += ks8695eth.o
+obj-$(CONFIG_KS8851_MLL) += ks8851_mll.o
+obj-$(CONFIG_LAN91C96) += lan91c96.o
+obj-$(CONFIG_MACB) += macb.o
+obj-$(CONFIG_MCFFEC) += mcffec.o mcfmii.o
+obj-$(CONFIG_MPC5xxx_FEC) += mpc5xxx_fec.o
+obj-$(CONFIG_MPC512x_FEC) += mpc512x_fec.o
+obj-$(CONFIG_MVGBE) += mvgbe.o
+obj-$(CONFIG_NATSEMI) += natsemi.o
+obj-$(CONFIG_DRIVER_NE2000) += ne2000.o ne2000_base.o
+obj-$(CONFIG_DRIVER_AX88796L) += ax88796.o ne2000_base.o
+obj-$(CONFIG_NETCONSOLE) += netconsole.o
+obj-$(CONFIG_NS8382X) += ns8382x.o
+obj-$(CONFIG_PCNET) += pcnet.o
+obj-$(CONFIG_PLB2800_ETHER) += plb2800_eth.o
+obj-$(CONFIG_RTL8139) += rtl8139.o
+obj-$(CONFIG_RTL8169) += rtl8169.o
+obj-$(CONFIG_SH_ETHER) += sh_eth.o
+obj-$(CONFIG_SMC91111) += smc91111.o
+obj-$(CONFIG_SMC911X) += smc911x.o
+obj-$(CONFIG_SUNXI_WEMAC) += sunxi_wemac.o
+obj-$(CONFIG_DRIVER_TI_EMAC) += davinci_emac.o
+obj-$(CONFIG_TSEC_ENET) += tsec.o fsl_mdio.o
+obj-$(CONFIG_DRIVER_TI_CPSW) += cpsw.o
+obj-$(CONFIG_FMAN_ENET) += fsl_mdio.o
+obj-$(CONFIG_TSI108_ETH) += tsi108_eth.o
+obj-$(CONFIG_ULI526X) += uli526x.o
+obj-$(CONFIG_VSC7385_ENET) += vsc7385.o
+obj-$(CONFIG_XILINX_AXIEMAC) += xilinx_axi_emac.o
+obj-$(CONFIG_XILINX_EMACLITE) += xilinx_emaclite.o
+obj-$(CONFIG_XILINX_LL_TEMAC) += xilinx_ll_temac.o xilinx_ll_temac_mdio.o \
 		xilinx_ll_temac_fifo.o xilinx_ll_temac_sdma.o
-COBJS-$(CONFIG_ZYNQ_GEM) += zynq_gem.o
-
-COBJS	:= $(sort $(COBJS-y))
-SRCS	:= $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-
-all:	$(LIB)
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-$(CONFIG_ZYNQ_GEM) += zynq_gem.o
diff --git a/drivers/net/at91_emac.c b/drivers/net/at91_emac.c
index 73612ea069..64d4c56ac5 100644
--- a/drivers/net/at91_emac.c
+++ b/drivers/net/at91_emac.c
@@ -10,19 +10,10 @@
 
 #include <common.h>
 #include <asm/io.h>
-#ifndef CONFIG_AT91_LEGACY
 #include <asm/arch/hardware.h>
 #include <asm/arch/at91_emac.h>
 #include <asm/arch/at91_pmc.h>
 #include <asm/arch/at91_pio.h>
-#else
-/* remove next 5 lines, if all RM9200 boards convert to at91 arch */
-#include <asm/arch-at91/at91rm9200.h>
-#include <asm/arch-at91/hardware.h>
-#include <asm/arch-at91/at91_emac.h>
-#include <asm/arch-at91/at91_pmc.h>
-#include <asm/arch-at91/at91_pio.h>
-#endif
 #include <net.h>
 #include <netdev.h>
 #include <malloc.h>
diff --git a/drivers/net/bfin_mac.c b/drivers/net/bfin_mac.c
index 0ffd59d497..0c2d2ef1a9 100644
--- a/drivers/net/bfin_mac.c
+++ b/drivers/net/bfin_mac.c
@@ -16,6 +16,7 @@
 #include <linux/mii.h>
 
 #include <asm/blackfin.h>
+#include <asm/clock.h>
 #include <asm/portmux.h>
 #include <asm/mach-common/bits/dma.h>
 #include <asm/mach-common/bits/emac.h>
@@ -259,6 +260,8 @@ static int bfin_miiphy_init(struct eth_device *dev, int *opmode)
 		*opmode = 0;
 
 	bfin_write_EMAC_MMC_CTL(RSTC | CROLL);
+	bfin_write_EMAC_VLAN1(EMAC_VLANX_DEF_VAL);
+	bfin_write_EMAC_VLAN2(EMAC_VLANX_DEF_VAL);
 
 	/* Initialize the TX DMA channel registers */
 	bfin_write_DMA2_X_COUNT(0);
diff --git a/drivers/net/cpsw.c b/drivers/net/cpsw.c
index 39240d9662..bd5fba21ce 100644
--- a/drivers/net/cpsw.c
+++ b/drivers/net/cpsw.c
@@ -656,7 +656,7 @@ static void cpsw_slave_init(struct cpsw_slave *slave, struct cpsw_priv *priv)
 
 	cpsw_ale_add_mcast(priv, NetBcastAddr, 1 << slave_port);
 
-	priv->phy_mask |= 1 << slave->data->phy_id;
+	priv->phy_mask |= 1 << slave->data->phy_addr;
 }
 
 static struct cpdma_desc *cpdma_desc_alloc(struct cpsw_priv *priv)
@@ -914,7 +914,7 @@ static int cpsw_recv(struct eth_device *dev)
 	void *buffer;
 	int len;
 
-	cpsw_update_link(priv);
+	cpsw_check_link(priv);
 
 	while (cpdma_process(priv, &priv->rx_chan, &buffer, &len) >= 0) {
 		invalidate_dcache_range((unsigned long)buffer,
@@ -941,14 +941,10 @@ static int cpsw_phy_init(struct eth_device *dev, struct cpsw_slave *slave)
 {
 	struct cpsw_priv *priv = (struct cpsw_priv *)dev->priv;
 	struct phy_device *phydev;
-	u32 supported = (SUPPORTED_10baseT_Half |
-			SUPPORTED_10baseT_Full |
-			SUPPORTED_100baseT_Half |
-			SUPPORTED_100baseT_Full |
-			SUPPORTED_1000baseT_Full);
+	u32 supported = PHY_GBIT_FEATURES;
 
 	phydev = phy_connect(priv->bus,
-			CONFIG_PHY_ADDR,
+			slave->data->phy_addr,
 			dev,
 			slave->data->phy_if);
 
diff --git a/drivers/net/designware.c b/drivers/net/designware.c
index 8413d57767..c45593bcc0 100644
--- a/drivers/net/designware.c
+++ b/drivers/net/designware.c
@@ -17,7 +17,75 @@
 #include <asm/io.h>
 #include "designware.h"
 
-static int configure_phy(struct eth_device *dev);
+#if !defined(CONFIG_PHYLIB)
+# error "DesignWare Ether MAC requires PHYLIB - missing CONFIG_PHYLIB"
+#endif
+
+static int dw_mdio_read(struct mii_dev *bus, int addr, int devad, int reg)
+{
+	struct eth_mac_regs *mac_p = bus->priv;
+	ulong start;
+	u16 miiaddr;
+	int timeout = CONFIG_MDIO_TIMEOUT;
+
+	miiaddr = ((addr << MIIADDRSHIFT) & MII_ADDRMSK) |
+		  ((reg << MIIREGSHIFT) & MII_REGMSK);
+
+	writel(miiaddr | MII_CLKRANGE_150_250M | MII_BUSY, &mac_p->miiaddr);
+
+	start = get_timer(0);
+	while (get_timer(start) < timeout) {
+		if (!(readl(&mac_p->miiaddr) & MII_BUSY))
+			return readl(&mac_p->miidata);
+		udelay(10);
+	};
+
+	return -1;
+}
+
+static int dw_mdio_write(struct mii_dev *bus, int addr, int devad, int reg,
+			u16 val)
+{
+	struct eth_mac_regs *mac_p = bus->priv;
+	ulong start;
+	u16 miiaddr;
+	int ret = -1, timeout = CONFIG_MDIO_TIMEOUT;
+
+	writel(val, &mac_p->miidata);
+	miiaddr = ((addr << MIIADDRSHIFT) & MII_ADDRMSK) |
+		  ((reg << MIIREGSHIFT) & MII_REGMSK) | MII_WRITE;
+
+	writel(miiaddr | MII_CLKRANGE_150_250M | MII_BUSY, &mac_p->miiaddr);
+
+	start = get_timer(0);
+	while (get_timer(start) < timeout) {
+		if (!(readl(&mac_p->miiaddr) & MII_BUSY)) {
+			ret = 0;
+			break;
+		}
+		udelay(10);
+	};
+
+	return ret;
+}
+
+static int dw_mdio_init(char *name, struct eth_mac_regs *mac_regs_p)
+{
+	struct mii_dev *bus = mdio_alloc();
+
+	if (!bus) {
+		printf("Failed to allocate MDIO bus\n");
+		return -1;
+	}
+
+	bus->read = dw_mdio_read;
+	bus->write = dw_mdio_write;
+	sprintf(bus->name, name);
+
+	bus->priv = (void *)mac_regs_p;
+
+	return mdio_register(bus);
+}
 
 static void tx_descs_init(struct eth_device *dev)
 {
@@ -51,7 +119,13 @@ static void tx_descs_init(struct eth_device *dev)
 	/* Correcting the last pointer of the chain */
 	desc_p->dmamac_next = &desc_table_p[0];
 
+	/* Flush all Tx buffer descriptors at once */
+	flush_dcache_range((unsigned int)priv->tx_mac_descrtable,
+			   (unsigned int)priv->tx_mac_descrtable +
+			   sizeof(priv->tx_mac_descrtable));
+
 	writel((ulong)&desc_table_p[0], &dma_p->txdesclistaddr);
+	priv->tx_currdescnum = 0;
 }
 
 static void rx_descs_init(struct eth_device *dev)
@@ -63,6 +137,15 @@ static void rx_descs_init(struct eth_device *dev)
 	struct dmamacdescr *desc_p;
 	u32 idx;
 
+	/* Before passing buffers to GMAC we need to make sure zeros
+	 * written there right after "priv" structure allocation were
+	 * flushed into RAM.
+	 * Otherwise there's a chance to get some of them flushed in RAM when
+	 * GMAC is already pushing data to RAM via DMA. This way incoming from
+	 * GMAC data will be corrupted. */
+	flush_dcache_range((unsigned int)rxbuffs, (unsigned int)rxbuffs +
+			   RX_TOTAL_BUFSIZE);
+
 	for (idx = 0; idx < CONFIG_RX_DESCR_NUM; idx++) {
 		desc_p = &desc_table_p[idx];
 		desc_p->dmamac_addr = &rxbuffs[idx * CONFIG_ETH_BUFSIZE];
@@ -78,56 +161,68 @@ static void rx_descs_init(struct eth_device *dev)
 	/* Correcting the last pointer of the chain */
 	desc_p->dmamac_next = &desc_table_p[0];
 
+	/* Flush all Rx buffer descriptors at once */
+	flush_dcache_range((unsigned int)priv->rx_mac_descrtable,
+			   (unsigned int)priv->rx_mac_descrtable +
+			   sizeof(priv->rx_mac_descrtable));
+
 	writel((ulong)&desc_table_p[0], &dma_p->rxdesclistaddr);
+	priv->rx_currdescnum = 0;
 }
 
-static void descs_init(struct eth_device *dev)
+static int dw_write_hwaddr(struct eth_device *dev)
 {
-	tx_descs_init(dev);
-	rx_descs_init(dev);
+	struct dw_eth_dev *priv = dev->priv;
+	struct eth_mac_regs *mac_p = priv->mac_regs_p;
+	u32 macid_lo, macid_hi;
+	u8 *mac_id = &dev->enetaddr[0];
+
+	macid_lo = mac_id[0] + (mac_id[1] << 8) + (mac_id[2] << 16) +
+		   (mac_id[3] << 24);
+	macid_hi = mac_id[4] + (mac_id[5] << 8);
+
+	writel(macid_hi, &mac_p->macaddr0hi);
+	writel(macid_lo, &mac_p->macaddr0lo);
+
+	return 0;
 }
 
-static int mac_reset(struct eth_device *dev)
+static void dw_adjust_link(struct eth_mac_regs *mac_p,
+			   struct phy_device *phydev)
 {
-	struct dw_eth_dev *priv = dev->priv;
-	struct eth_mac_regs *mac_p = priv->mac_regs_p;
-	struct eth_dma_regs *dma_p = priv->dma_regs_p;
+	u32 conf = readl(&mac_p->conf) | FRAMEBURSTENABLE | DISABLERXOWN;
 
-	ulong start;
-	int timeout = CONFIG_MACRESET_TIMEOUT;
+	if (!phydev->link) {
+		printf("%s: No link.\n", phydev->dev->name);
+		return;
+	}
 
-	writel(DMAMAC_SRST, &dma_p->busmode);
+	if (phydev->speed != 1000)
+		conf |= MII_PORTSELECT;
 
-	if (priv->interface != PHY_INTERFACE_MODE_RGMII)
-		writel(MII_PORTSELECT, &mac_p->conf);
+	if (phydev->speed == 100)
+		conf |= FES_100;
 
-	start = get_timer(0);
-	while (get_timer(start) < timeout) {
-		if (!(readl(&dma_p->busmode) & DMAMAC_SRST))
-			return 0;
+	if (phydev->duplex)
+		conf |= FULLDPLXMODE;
 
-		/* Try again after 10usec */
-		udelay(10);
-	};
+	writel(conf, &mac_p->conf);
 
-	return -1;
+	printf("Speed: %d, %s duplex%s\n", phydev->speed,
+	       (phydev->duplex) ? "full" : "half",
+	       (phydev->port == PORT_FIBRE) ? ", fiber mode" : "");
 }
 
-static int dw_write_hwaddr(struct eth_device *dev)
+static void dw_eth_halt(struct eth_device *dev)
 {
 	struct dw_eth_dev *priv = dev->priv;
 	struct eth_mac_regs *mac_p = priv->mac_regs_p;
-	u32 macid_lo, macid_hi;
-	u8 *mac_id = &dev->enetaddr[0];
-
-	macid_lo = mac_id[0] + (mac_id[1] << 8) + \
-		   (mac_id[2] << 16) + (mac_id[3] << 24);
-	macid_hi = mac_id[4] + (mac_id[5] << 8);
+	struct eth_dma_regs *dma_p = priv->dma_regs_p;
 
-	writel(macid_hi, &mac_p->macaddr0hi);
-	writel(macid_lo, &mac_p->macaddr0lo);
+	writel(readl(&mac_p->conf) & ~(RXENABLE | TXENABLE), &mac_p->conf);
+	writel(readl(&dma_p->opmode) & ~(RXSTART | TXSTART), &dma_p->opmode);
 
-	return 0;
+	phy_shutdown(priv->phydev);
 }
 
 static int dw_eth_init(struct eth_device *dev, bd_t *bis)
@@ -135,55 +230,43 @@ static int dw_eth_init(struct eth_device *dev, bd_t *bis)
 	struct dw_eth_dev *priv = dev->priv;
 	struct eth_mac_regs *mac_p = priv->mac_regs_p;
 	struct eth_dma_regs *dma_p = priv->dma_regs_p;
-	u32 conf;
+	unsigned int start;
 
-	if (priv->phy_configured != 1)
-		configure_phy(dev);
+	writel(readl(&dma_p->busmode) | DMAMAC_SRST, &dma_p->busmode);
 
-	/* Print link status only once */
-	if (!priv->link_printed) {
-		printf("ENET Speed is %d Mbps - %s duplex connection\n",
-		       priv->speed, (priv->duplex == HALF) ? "HALF" : "FULL");
-		priv->link_printed = 1;
-	}
+	start = get_timer(0);
+	while (readl(&dma_p->busmode) & DMAMAC_SRST) {
+		if (get_timer(start) >= CONFIG_MACRESET_TIMEOUT)
+			return -1;
 
-	/* Reset ethernet hardware */
-	if (mac_reset(dev) < 0)
-		return -1;
+		mdelay(100);
+	};
 
-	/* Resore the HW MAC address as it has been lost during MAC reset */
+	/* Soft reset above clears HW address registers.
+	 * So we have to set it here once again */
 	dw_write_hwaddr(dev);
 
-	writel(FIXEDBURST | PRIORXTX_41 | BURST_16,
-			&dma_p->busmode);
-
-	writel(readl(&dma_p->opmode) | FLUSHTXFIFO | STOREFORWARD |
-		TXSECONDFRAME, &dma_p->opmode);
+	rx_descs_init(dev);
+	tx_descs_init(dev);
 
-	conf = FRAMEBURSTENABLE | DISABLERXOWN;
+	writel(FIXEDBURST | PRIORXTX_41 | BURST_16, &dma_p->busmode);
 
-	if (priv->speed != 1000)
-		conf |= MII_PORTSELECT;
+	writel(readl(&dma_p->opmode) | FLUSHTXFIFO | STOREFORWARD,
+	       &dma_p->opmode);
 
-	if ((priv->interface != PHY_INTERFACE_MODE_MII) &&
-		(priv->interface != PHY_INTERFACE_MODE_GMII)) {
+	writel(readl(&dma_p->opmode) | RXSTART | TXSTART, &dma_p->opmode);
 
-		if (priv->speed == 100)
-			conf |= FES_100;
+	/* Start up the PHY */
+	if (phy_startup(priv->phydev)) {
+		printf("Could not initialize PHY %s\n",
+		       priv->phydev->dev->name);
+		return -1;
 	}
 
-	if (priv->duplex == FULL)
-		conf |= FULLDPLXMODE;
-
-	writel(conf, &mac_p->conf);
-
-	descs_init(dev);
+	dw_adjust_link(mac_p, priv->phydev);
 
-	/*
-	 * Start/Enable xfer at dma as well as mac level
-	 */
-	writel(readl(&dma_p->opmode) | RXSTART, &dma_p->opmode);
-	writel(readl(&dma_p->opmode) | TXSTART, &dma_p->opmode);
+	if (!priv->phydev->link)
+		return -1;
 
 	writel(readl(&mac_p->conf) | RXENABLE | TXENABLE, &mac_p->conf);
 
@@ -197,6 +280,11 @@ static int dw_eth_send(struct eth_device *dev, void *packet, int length)
 	u32 desc_num = priv->tx_currdescnum;
 	struct dmamacdescr *desc_p = &priv->tx_mac_descrtable[desc_num];
 
+	/* Invalidate only "status" field for the following check */
+	invalidate_dcache_range((unsigned long)&desc_p->txrx_status,
+				(unsigned long)&desc_p->txrx_status +
+				sizeof(desc_p->txrx_status));
+
 	/* Check if the descriptor is owned by CPU */
 	if (desc_p->txrx_status & DESC_TXSTS_OWNBYDMA) {
 		printf("CPU not owner of tx frame\n");
@@ -205,6 +293,10 @@ static int dw_eth_send(struct eth_device *dev, void *packet, int length)
 
 	memcpy((void *)desc_p->dmamac_addr, packet, length);
 
+	/* Flush data to be sent */
+	flush_dcache_range((unsigned long)desc_p->dmamac_addr,
+			   (unsigned long)desc_p->dmamac_addr + length);
+
 #if defined(CONFIG_DW_ALTDESCRIPTOR)
 	desc_p->txrx_status |= DESC_TXSTS_TXFIRST | DESC_TXSTS_TXLAST;
 	desc_p->dmamac_cntl |= (length << DESC_TXCTRL_SIZE1SHFT) & \
@@ -220,6 +312,10 @@ static int dw_eth_send(struct eth_device *dev, void *packet, int length)
 	desc_p->txrx_status = DESC_TXSTS_OWNBYDMA;
 #endif
 
+	/* Flush modified buffer descriptor */
+	flush_dcache_range((unsigned long)desc_p,
+			   (unsigned long)desc_p + sizeof(struct dmamacdescr));
+
 	/* Test the wrap-around condition. */
 	if (++desc_num >= CONFIG_TX_DESCR_NUM)
 		desc_num = 0;
@@ -235,18 +331,28 @@ static int dw_eth_send(struct eth_device *dev, void *packet, int length)
 static int dw_eth_recv(struct eth_device *dev)
 {
 	struct dw_eth_dev *priv = dev->priv;
-	u32 desc_num = priv->rx_currdescnum;
+	u32 status, desc_num = priv->rx_currdescnum;
 	struct dmamacdescr *desc_p = &priv->rx_mac_descrtable[desc_num];
-
-	u32 status = desc_p->txrx_status;
 	int length = 0;
 
+	/* Invalidate entire buffer descriptor */
+	invalidate_dcache_range((unsigned long)desc_p,
+				(unsigned long)desc_p +
+				sizeof(struct dmamacdescr));
+
+	status = desc_p->txrx_status;
+
 	/* Check  if the owner is the CPU */
 	if (!(status & DESC_RXSTS_OWNBYDMA)) {
 
 		length = (status & DESC_RXSTS_FRMLENMSK) >> \
 			 DESC_RXSTS_FRMLENSHFT;
 
+		/* Invalidate received data */
+		invalidate_dcache_range((unsigned long)desc_p->dmamac_addr,
+					(unsigned long)desc_p->dmamac_addr +
+					length);
+
 		NetReceive(desc_p->dmamac_addr, length);
 
 		/*
@@ -255,6 +361,11 @@ static int dw_eth_recv(struct eth_device *dev)
 		 */
 		desc_p->txrx_status |= DESC_RXSTS_OWNBYDMA;
 
+		/* Flush only status field - others weren't changed */
+		flush_dcache_range((unsigned long)&desc_p->txrx_status,
+				   (unsigned long)&desc_p->txrx_status +
+				   sizeof(desc_p->txrx_status));
+
 		/* Test the wrap-around condition. */
 		if (++desc_num >= CONFIG_RX_DESCR_NUM)
 			desc_num = 0;
@@ -265,251 +376,30 @@ static int dw_eth_recv(struct eth_device *dev)
 	return length;
 }
 
-static void dw_eth_halt(struct eth_device *dev)
-{
-	struct dw_eth_dev *priv = dev->priv;
-
-	mac_reset(dev);
-	priv->tx_currdescnum = priv->rx_currdescnum = 0;
-}
-
-static int eth_mdio_read(struct eth_device *dev, u8 addr, u8 reg, u16 *val)
-{
-	struct dw_eth_dev *priv = dev->priv;
-	struct eth_mac_regs *mac_p = priv->mac_regs_p;
-	ulong start;
-	u32 miiaddr;
-	int timeout = CONFIG_MDIO_TIMEOUT;
-
-	miiaddr = ((addr << MIIADDRSHIFT) & MII_ADDRMSK) | \
-		  ((reg << MIIREGSHIFT) & MII_REGMSK);
-
-	writel(miiaddr | MII_CLKRANGE_150_250M | MII_BUSY, &mac_p->miiaddr);
-
-	start = get_timer(0);
-	while (get_timer(start) < timeout) {
-		if (!(readl(&mac_p->miiaddr) & MII_BUSY)) {
-			*val = readl(&mac_p->miidata);
-			return 0;
-		}
-
-		/* Try again after 10usec */
-		udelay(10);
-	};
-
-	return -1;
-}
-
-static int eth_mdio_write(struct eth_device *dev, u8 addr, u8 reg, u16 val)
-{
-	struct dw_eth_dev *priv = dev->priv;
-	struct eth_mac_regs *mac_p = priv->mac_regs_p;
-	ulong start;
-	u32 miiaddr;
-	int ret = -1, timeout = CONFIG_MDIO_TIMEOUT;
-	u16 value;
-
-	writel(val, &mac_p->miidata);
-	miiaddr = ((addr << MIIADDRSHIFT) & MII_ADDRMSK) | \
-		  ((reg << MIIREGSHIFT) & MII_REGMSK) | MII_WRITE;
-
-	writel(miiaddr | MII_CLKRANGE_150_250M | MII_BUSY, &mac_p->miiaddr);
-
-	start = get_timer(0);
-	while (get_timer(start) < timeout) {
-		if (!(readl(&mac_p->miiaddr) & MII_BUSY)) {
-			ret = 0;
-			break;
-		}
-
-		/* Try again after 10usec */
-		udelay(10);
-	};
-
-	/* Needed as a fix for ST-Phy */
-	eth_mdio_read(dev, addr, reg, &value);
-
-	return ret;
-}
-
-#if defined(CONFIG_DW_SEARCH_PHY)
-static int find_phy(struct eth_device *dev)
-{
-	int phy_addr = 0;
-	u16 ctrl, oldctrl;
-
-	do {
-		eth_mdio_read(dev, phy_addr, MII_BMCR, &ctrl);
-		oldctrl = ctrl & BMCR_ANENABLE;
-
-		ctrl ^= BMCR_ANENABLE;
-		eth_mdio_write(dev, phy_addr, MII_BMCR, ctrl);
-		eth_mdio_read(dev, phy_addr, MII_BMCR, &ctrl);
-		ctrl &= BMCR_ANENABLE;
-
-		if (ctrl == oldctrl) {
-			phy_addr++;
-		} else {
-			ctrl ^= BMCR_ANENABLE;
-			eth_mdio_write(dev, phy_addr, MII_BMCR, ctrl);
-
-			return phy_addr;
-		}
-	} while (phy_addr < 32);
-
-	return -1;
-}
-#endif
-
-static int dw_reset_phy(struct eth_device *dev)
-{
-	struct dw_eth_dev *priv = dev->priv;
-	u16 ctrl;
-	ulong start;
-	int timeout = CONFIG_PHYRESET_TIMEOUT;
-	u32 phy_addr = priv->address;
-
-	eth_mdio_write(dev, phy_addr, MII_BMCR, BMCR_RESET);
-
-	start = get_timer(0);
-	while (get_timer(start) < timeout) {
-		eth_mdio_read(dev, phy_addr, MII_BMCR, &ctrl);
-		if (!(ctrl & BMCR_RESET))
-			break;
-
-		/* Try again after 10usec */
-		udelay(10);
-	};
-
-	if (get_timer(start) >= CONFIG_PHYRESET_TIMEOUT)
-		return -1;
-
-#ifdef CONFIG_PHY_RESET_DELAY
-	udelay(CONFIG_PHY_RESET_DELAY);
-#endif
-	return 0;
-}
-
-/*
- * Add weak default function for board specific PHY configuration
- */
-int __weak designware_board_phy_init(struct eth_device *dev, int phy_addr,
-		int (*mii_write)(struct eth_device *, u8, u8, u16),
-		int dw_reset_phy(struct eth_device *))
-{
-	return 0;
-}
-
-static int configure_phy(struct eth_device *dev)
+static int dw_phy_init(struct eth_device *dev)
 {
 	struct dw_eth_dev *priv = dev->priv;
-	int phy_addr;
-	u16 bmcr;
-#if defined(CONFIG_DW_AUTONEG)
-	u16 bmsr;
-	u32 timeout;
-	ulong start;
-#endif
+	struct phy_device *phydev;
+	int mask = 0xffffffff;
 
-#if defined(CONFIG_DW_SEARCH_PHY)
-	phy_addr = find_phy(dev);
-	if (phy_addr >= 0)
-		priv->address = phy_addr;
-	else
-		return -1;
-#else
-	phy_addr = priv->address;
+#ifdef CONFIG_PHY_ADDR
+	mask = 1 << CONFIG_PHY_ADDR;
 #endif
 
-	/*
-	 * Some boards need board specific PHY initialization. This is
-	 * after the main driver init code but before the auto negotiation
-	 * is run.
-	 */
-	if (designware_board_phy_init(dev, phy_addr,
-				      eth_mdio_write, dw_reset_phy) < 0)
-		return -1;
-
-	if (dw_reset_phy(dev) < 0)
+	phydev = phy_find_by_mask(priv->bus, mask, priv->interface);
+	if (!phydev)
 		return -1;
 
-#if defined(CONFIG_DW_AUTONEG)
-	/* Set Auto-Neg Advertisement capabilities to 10/100 half/full */
-	eth_mdio_write(dev, phy_addr, MII_ADVERTISE, 0x1E1);
-
-	bmcr = BMCR_ANENABLE | BMCR_ANRESTART;
-#else
-	bmcr = BMCR_SPEED100 | BMCR_FULLDPLX;
-
-#if defined(CONFIG_DW_SPEED10M)
-	bmcr &= ~BMCR_SPEED100;
-#endif
-#if defined(CONFIG_DW_DUPLEXHALF)
-	bmcr &= ~BMCR_FULLDPLX;
-#endif
-#endif
-	if (eth_mdio_write(dev, phy_addr, MII_BMCR, bmcr) < 0)
-		return -1;
-
-	/* Read the phy status register and populate priv structure */
-#if defined(CONFIG_DW_AUTONEG)
-	timeout = CONFIG_AUTONEG_TIMEOUT;
-	start = get_timer(0);
-	puts("Waiting for PHY auto negotiation to complete");
-	while (get_timer(start) < timeout) {
-		eth_mdio_read(dev, phy_addr, MII_BMSR, &bmsr);
-		if (bmsr & BMSR_ANEGCOMPLETE) {
-			priv->phy_configured = 1;
-			break;
-		}
-
-		/* Print dot all 1s to show progress */
-		if ((get_timer(start) % 1000) == 0)
-			putc('.');
-
-		/* Try again after 1msec */
-		udelay(1000);
-	};
-
-	if (!(bmsr & BMSR_ANEGCOMPLETE))
-		puts(" TIMEOUT!\n");
-	else
-		puts(" done\n");
-#else
-	priv->phy_configured = 1;
-#endif
-
-	priv->speed = miiphy_speed(dev->name, phy_addr);
-	priv->duplex = miiphy_duplex(dev->name, phy_addr);
+	phydev->supported &= PHY_GBIT_FEATURES;
+	phydev->advertising = phydev->supported;
 
-	return 0;
-}
-
-#if defined(CONFIG_MII)
-static int dw_mii_read(const char *devname, u8 addr, u8 reg, u16 *val)
-{
-	struct eth_device *dev;
-
-	dev = eth_get_dev_by_name(devname);
-	if (dev)
-		eth_mdio_read(dev, addr, reg, val);
+	priv->phydev = phydev;
+	phy_config(phydev);
 
-	return 0;
-}
-
-static int dw_mii_write(const char *devname, u8 addr, u8 reg, u16 val)
-{
-	struct eth_device *dev;
-
-	dev = eth_get_dev_by_name(devname);
-	if (dev)
-		eth_mdio_write(dev, addr, reg, val);
-
-	return 0;
+	return 1;
 }
-#endif
 
-int designware_initialize(u32 id, ulong base_addr, u32 phy_addr, u32 interface)
+int designware_initialize(ulong base_addr, u32 interface)
 {
 	struct eth_device *dev;
 	struct dw_eth_dev *priv;
@@ -531,19 +421,14 @@ int designware_initialize(u32 id, ulong base_addr, u32 phy_addr, u32 interface)
 	memset(dev, 0, sizeof(struct eth_device));
 	memset(priv, 0, sizeof(struct dw_eth_dev));
 
-	sprintf(dev->name, "mii%d", id);
+	sprintf(dev->name, "dwmac.%lx", base_addr);
 	dev->iobase = (int)base_addr;
 	dev->priv = priv;
 
-	eth_getenv_enetaddr_by_index("eth", id, &dev->enetaddr[0]);
-
 	priv->dev = dev;
 	priv->mac_regs_p = (struct eth_mac_regs *)base_addr;
 	priv->dma_regs_p = (struct eth_dma_regs *)(base_addr +
 			DW_DMA_BASE_OFFSET);
-	priv->address = phy_addr;
-	priv->phy_configured = 0;
-	priv->interface = interface;
 
 	dev->init = dw_eth_init;
 	dev->send = dw_eth_send;
@@ -553,8 +438,10 @@ int designware_initialize(u32 id, ulong base_addr, u32 phy_addr, u32 interface)
 
 	eth_register(dev);
 
-#if defined(CONFIG_MII)
-	miiphy_register(dev->name, dw_mii_read, dw_mii_write);
-#endif
-	return 1;
+	priv->interface = interface;
+
+	dw_mdio_init(dev->name, priv->mac_regs_p);
+	priv->bus = miiphy_get_dev_by_name(dev->name);
+
+	return dw_phy_init(dev);
 }
diff --git a/drivers/net/designware.h b/drivers/net/designware.h
index e80002a0e4..382b0c7f0a 100644
--- a/drivers/net/designware.h
+++ b/drivers/net/designware.h
@@ -16,8 +16,6 @@
 
 #define CONFIG_MACRESET_TIMEOUT	(3 * CONFIG_SYS_HZ)
 #define CONFIG_MDIO_TIMEOUT	(3 * CONFIG_SYS_HZ)
-#define CONFIG_PHYRESET_TIMEOUT	(3 * CONFIG_SYS_HZ)
-#define CONFIG_AUTONEG_TIMEOUT	(5 * CONFIG_SYS_HZ)
 
 struct eth_mac_regs {
 	u32 conf;		/* 0x00 */
@@ -112,7 +110,7 @@ struct dmamacdescr {
 	u32 dmamac_cntl;
 	void *dmamac_addr;
 	struct dmamacdescr *dmamac_next;
-};
+} __aligned(ARCH_DMA_MINALIGN);
 
 /*
  * txrx_status definitions
@@ -217,15 +215,9 @@ struct dmamacdescr {
 #endif
 
 struct dw_eth_dev {
-	u32 address;
 	u32 interface;
-	u32 speed;
-	u32 duplex;
 	u32 tx_currdescnum;
 	u32 rx_currdescnum;
-	u32 phy_configured;
-	int link_printed;
-	u32 padding;
 
 	struct dmamacdescr tx_mac_descrtable[CONFIG_TX_DESCR_NUM];
 	struct dmamacdescr rx_mac_descrtable[CONFIG_RX_DESCR_NUM];
@@ -237,15 +229,8 @@ struct dw_eth_dev {
 	struct eth_dma_regs *dma_regs_p;
 
 	struct eth_device *dev;
-} __attribute__ ((aligned(8)));
-
-/* Speed specific definitions */
-#define SPEED_10M		1
-#define SPEED_100M		2
-#define SPEED_1000M		3
-
-/* Duplex mode specific definitions */
-#define HALF_DUPLEX		1
-#define FULL_DUPLEX		2
+	struct phy_device *phydev;
+	struct mii_dev *bus;
+};
 
 #endif
diff --git a/drivers/net/dm9000x.c b/drivers/net/dm9000x.c
index f7170e0554..b68d808c74 100644
--- a/drivers/net/dm9000x.c
+++ b/drivers/net/dm9000x.c
@@ -342,6 +342,15 @@ static int dm9000_init(struct eth_device *dev, bd_t *bd)
 	DM9000_iow(DM9000_ISR, ISR_ROOS | ISR_ROS | ISR_PTS | ISR_PRS);
 
 	printf("MAC: %pM\n", dev->enetaddr);
+	if (!is_valid_ether_addr(dev->enetaddr)) {
+#ifdef CONFIG_RANDOM_MACADDR
+		printf("Bad MAC address (uninitialized EEPROM?), randomizing\n");
+		eth_random_enetaddr(dev->enetaddr);
+		printf("MAC: %pM\n", dev->enetaddr);
+#else
+		printf("WARNING: Bad MAC address (uninitialized EEPROM?)\n");
+#endif
+	}
 
 	/* fill device MAC address registers */
 	for (i = 0, oft = DM9000_PAR; i < 6; i++, oft++)
diff --git a/drivers/net/e1000.c b/drivers/net/e1000.c
index 57aa53dbae..9a66e68ae0 100644
--- a/drivers/net/e1000.c
+++ b/drivers/net/e1000.c
@@ -114,12 +114,13 @@ static int e1000_write_phy_reg(struct e1000_hw *hw, uint32_t reg_addr,
 static int32_t e1000_phy_hw_reset(struct e1000_hw *hw);
 static int e1000_phy_reset(struct e1000_hw *hw);
 static int e1000_detect_gig_phy(struct e1000_hw *hw);
-static void e1000_put_hw_eeprom_semaphore(struct e1000_hw *hw);
 static void e1000_set_media_type(struct e1000_hw *hw);
 
 static int32_t e1000_swfw_sync_acquire(struct e1000_hw *hw, uint16_t mask);
 static int32_t e1000_check_phy_reset_block(struct e1000_hw *hw);
 
+#ifndef CONFIG_E1000_NO_NVM
+static void e1000_put_hw_eeprom_semaphore(struct e1000_hw *hw);
 static int32_t e1000_read_eeprom(struct e1000_hw *hw, uint16_t offset,
 		uint16_t words,
 		uint16_t *data);
@@ -885,6 +886,7 @@ static int e1000_validate_eeprom_checksum(struct e1000_hw *hw)
 
 	return -E1000_ERR_EEPROM;
 }
+#endif /* CONFIG_E1000_NO_NVM */
 
 /*****************************************************************************
  * Set PHY to class A mode
@@ -897,6 +899,7 @@ static int e1000_validate_eeprom_checksum(struct e1000_hw *hw)
 static int32_t
 e1000_set_phy_mode(struct e1000_hw *hw)
 {
+#ifndef CONFIG_E1000_NO_NVM
 	int32_t ret_val;
 	uint16_t eeprom_data;
 
@@ -923,10 +926,11 @@ e1000_set_phy_mode(struct e1000_hw *hw)
 			hw->phy_reset_disable = false;
 		}
 	}
-
+#endif
 	return E1000_SUCCESS;
 }
 
+#ifndef CONFIG_E1000_NO_NVM
 /***************************************************************************
  *
  * Obtaining software semaphore bit (SMBI) before resetting PHY.
@@ -965,6 +969,7 @@ e1000_get_software_semaphore(struct e1000_hw *hw)
 
 	return E1000_SUCCESS;
 }
+#endif
 
 /***************************************************************************
  * This function clears HW semaphore bits.
@@ -977,6 +982,7 @@ e1000_get_software_semaphore(struct e1000_hw *hw)
 static void
 e1000_put_hw_eeprom_semaphore(struct e1000_hw *hw)
 {
+#ifndef CONFIG_E1000_NO_NVM
 	 uint32_t swsm;
 
 	DEBUGFUNC();
@@ -991,6 +997,7 @@ e1000_put_hw_eeprom_semaphore(struct e1000_hw *hw)
 	} else
 		swsm &= ~(E1000_SWSM_SWESMBI);
 	E1000_WRITE_REG(hw, SWSM, swsm);
+#endif
 }
 
 /***************************************************************************
@@ -1007,6 +1014,7 @@ e1000_put_hw_eeprom_semaphore(struct e1000_hw *hw)
 static int32_t
 e1000_get_hw_eeprom_semaphore(struct e1000_hw *hw)
 {
+#ifndef CONFIG_E1000_NO_NVM
 	int32_t timeout;
 	uint32_t swsm;
 
@@ -1043,7 +1051,7 @@ e1000_get_hw_eeprom_semaphore(struct e1000_hw *hw)
 				"SWESMBI bit is set.\n");
 		return -E1000_ERR_EEPROM;
 	}
-
+#endif
 	return E1000_SUCCESS;
 }
 
@@ -1097,6 +1105,7 @@ static bool e1000_is_second_port(struct e1000_hw *hw)
 	}
 }
 
+#ifndef CONFIG_E1000_NO_NVM
 /******************************************************************************
  * Reads the adapter's MAC address from the EEPROM and inverts the LSB for the
  * second function of dual function devices
@@ -1136,6 +1145,7 @@ e1000_read_mac_addr(struct eth_device *nic)
 #endif
 	return 0;
 }
+#endif
 
 /******************************************************************************
  * Initializes receive address filters.
@@ -1764,9 +1774,11 @@ static int
 e1000_setup_link(struct eth_device *nic)
 {
 	struct e1000_hw *hw = nic->priv;
-	uint32_t ctrl_ext;
 	int32_t ret_val;
+#ifndef CONFIG_E1000_NO_NVM
+	uint32_t ctrl_ext;
 	uint16_t eeprom_data;
+#endif
 
 	DEBUGFUNC();
 
@@ -1775,6 +1787,7 @@ e1000_setup_link(struct eth_device *nic)
 	if (e1000_check_phy_reset_block(hw))
 		return E1000_SUCCESS;
 
+#ifndef CONFIG_E1000_NO_NVM
 	/* Read and store word 0x0F of the EEPROM. This word contains bits
 	 * that determine the hardware's default PAUSE (flow control) mode,
 	 * a bit that determines whether the HW defaults to enabling or
@@ -1788,7 +1801,7 @@ e1000_setup_link(struct eth_device *nic)
 		DEBUGOUT("EEPROM Read Error\n");
 		return -E1000_ERR_EEPROM;
 	}
-
+#endif
 	if (hw->fc == e1000_fc_default) {
 		switch (hw->mac_type) {
 		case e1000_ich8lan:
@@ -1797,6 +1810,7 @@ e1000_setup_link(struct eth_device *nic)
 			hw->fc = e1000_fc_full;
 			break;
 		default:
+#ifndef CONFIG_E1000_NO_NVM
 			ret_val = e1000_read_eeprom(hw,
 				EEPROM_INIT_CONTROL2_REG, 1, &eeprom_data);
 			if (ret_val) {
@@ -1809,6 +1823,7 @@ e1000_setup_link(struct eth_device *nic)
 				    EEPROM_WORD0F_ASM_DIR)
 				hw->fc = e1000_fc_tx_pause;
 			else
+#endif
 				hw->fc = e1000_fc_full;
 			break;
 		}
@@ -1828,6 +1843,7 @@ e1000_setup_link(struct eth_device *nic)
 
 	DEBUGOUT("After fix-ups FlowControl is now = %x\n", hw->fc);
 
+#ifndef CONFIG_E1000_NO_NVM
 	/* Take the 4 bits from EEPROM word 0x0F that determine the initial
 	 * polarity value for the SW controlled pins, and setup the
 	 * Extended Device Control reg with that info.
@@ -1840,6 +1856,7 @@ e1000_setup_link(struct eth_device *nic)
 			    SWDPIO__EXT_SHIFT);
 		E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
 	}
+#endif
 
 	/* Call the necessary subroutine to configure the link. */
 	ret_val = (hw->media_type == e1000_media_type_fiber) ?
@@ -5196,6 +5213,7 @@ e1000_initialize(bd_t * bis)
 		e1000_reset_hw(hw);
 		list_add_tail(&hw->list_node, &e1000_hw_list);
 
+#ifndef CONFIG_E1000_NO_NVM
 		/* Validate the EEPROM and get chipset information */
 #if !defined(CONFIG_MVBC_1G)
 		if (e1000_init_eeprom_params(hw)) {
@@ -5206,11 +5224,17 @@ e1000_initialize(bd_t * bis)
 			continue;
 #endif
 		e1000_read_mac_addr(nic);
+#endif
 		e1000_get_bus_type(hw);
 
+#ifndef CONFIG_E1000_NO_NVM
 		printf("e1000: %02x:%02x:%02x:%02x:%02x:%02x\n       ",
 		       nic->enetaddr[0], nic->enetaddr[1], nic->enetaddr[2],
 		       nic->enetaddr[3], nic->enetaddr[4], nic->enetaddr[5]);
+#else
+		memset(nic->enetaddr, 0, 6);
+		printf("e1000: no NVM\n");
+#endif
 
 		/* Set up the function pointers and register the device */
 		nic->init = e1000_init;
diff --git a/drivers/net/e1000.h b/drivers/net/e1000.h
index 25884f5bc5..ff87af2ef8 100644
--- a/drivers/net/e1000.h
+++ b/drivers/net/e1000.h
@@ -63,11 +63,14 @@ struct e1000_hw_stats;
 
 /* Internal E1000 helper functions */
 struct e1000_hw *e1000_find_card(unsigned int cardnum);
+
+#ifndef CONFIG_E1000_NO_NVM
 int32_t e1000_acquire_eeprom(struct e1000_hw *hw);
 void e1000_standby_eeprom(struct e1000_hw *hw);
 void e1000_release_eeprom(struct e1000_hw *hw);
 void e1000_raise_ee_clk(struct e1000_hw *hw, uint32_t *eecd);
 void e1000_lower_ee_clk(struct e1000_hw *hw, uint32_t *eecd);
+#endif
 
 #ifdef CONFIG_E1000_SPI
 int do_e1000_spi(cmd_tbl_t *cmdtp, struct e1000_hw *hw,
@@ -1019,6 +1022,7 @@ struct e1000_hw_stats {
 	uint64_t tsctfc;
 };
 
+#ifndef CONFIG_E1000_NO_NVM
 struct e1000_eeprom_info {
 e1000_eeprom_type type;
 	uint16_t word_size;
@@ -1029,6 +1033,7 @@ e1000_eeprom_type type;
 	bool use_eerd;
 	bool use_eewr;
 };
+#endif
 
 typedef enum {
     e1000_smart_speed_default = 0,
@@ -1081,10 +1086,14 @@ struct e1000_hw {
 	uint32_t io_base;
 #endif
 	uint32_t		asf_firmware_present;
+#ifndef CONFIG_E1000_NO_NVM
 	uint32_t		eeprom_semaphore_present;
+#endif
 	uint32_t		swfw_sync_present;
 	uint32_t		swfwhw_semaphore_present;
+#ifndef CONFIG_E1000_NO_NVM
 	struct e1000_eeprom_info eeprom;
+#endif
 	e1000_ms_type		master_slave;
 	e1000_ms_type		original_master_slave;
 	e1000_ffe_config	ffe_config_state;
diff --git a/drivers/net/fec_mxc.c b/drivers/net/fec_mxc.c
index 107cd6ecc5..4cefda48e4 100644
--- a/drivers/net/fec_mxc.c
+++ b/drivers/net/fec_mxc.c
@@ -128,8 +128,12 @@ static void fec_mii_setspeed(struct ethernet_regs *eth)
 	 * Set MII_SPEED = (1/(mii_speed * 2)) * System Clock
 	 * and do not drop the Preamble.
 	 */
-	writel((((imx_get_fecclk() / 1000000) + 2) / 5) << 1,
-			&eth->mii_speed);
+	register u32 speed = DIV_ROUND_UP(imx_get_fecclk(), 5000000);
+#ifdef FEC_QUIRK_ENET_MAC
+	speed--;
+#endif
+	speed <<= 1;
+	writel(speed, &eth->mii_speed);
 	debug("%s: mii_speed %08x\n", __func__, readl(&eth->mii_speed));
 }
 
@@ -270,49 +274,34 @@ static int fec_tx_task_disable(struct fec_priv *fec)
  * @param[in] dsize desired size of each receive buffer
  * @return 0 on success
  *
- * For this task we need additional memory for the data buffers. And each
- * data buffer requires some alignment. Thy must be aligned to a specific
- * boundary each.
+ * Init all RX descriptors to default values.
  */
-static int fec_rbd_init(struct fec_priv *fec, int count, int dsize)
+static void fec_rbd_init(struct fec_priv *fec, int count, int dsize)
 {
 	uint32_t size;
+	uint8_t *data;
 	int i;
 
 	/*
-	 * Allocate memory for the buffers. This allocation respects the
-	 * alignment
+	 * Reload the RX descriptors with default values and wipe
+	 * the RX buffers.
 	 */
 	size = roundup(dsize, ARCH_DMA_MINALIGN);
 	for (i = 0; i < count; i++) {
-		uint32_t data_ptr = readl(&fec->rbd_base[i].data_pointer);
-		if (data_ptr == 0) {
-			uint8_t *data = memalign(ARCH_DMA_MINALIGN,
-						 size);
-			if (!data) {
-				printf("%s: error allocating rxbuf %d\n",
-				       __func__, i);
-				goto err;
-			}
-			writel((uint32_t)data, &fec->rbd_base[i].data_pointer);
-		} /* needs allocation */
-		writew(FEC_RBD_EMPTY, &fec->rbd_base[i].status);
-		writew(0, &fec->rbd_base[i].data_length);
+		data = (uint8_t *)fec->rbd_base[i].data_pointer;
+		memset(data, 0, dsize);
+		flush_dcache_range((uint32_t)data, (uint32_t)data + size);
+
+		fec->rbd_base[i].status = FEC_RBD_EMPTY;
+		fec->rbd_base[i].data_length = 0;
 	}
 
 	/* Mark the last RBD to close the ring. */
-	writew(FEC_RBD_WRAP | FEC_RBD_EMPTY, &fec->rbd_base[i - 1].status);
+	fec->rbd_base[i - 1].status = FEC_RBD_WRAP | FEC_RBD_EMPTY;
 	fec->rbd_index = 0;
 
-	return 0;
-
-err:
-	for (; i >= 0; i--) {
-		uint32_t data_ptr = readl(&fec->rbd_base[i].data_pointer);
-		free((void *)data_ptr);
-	}
-
-	return -ENOMEM;
+	flush_dcache_range((unsigned)fec->rbd_base,
+			   (unsigned)fec->rbd_base + size);
 }
 
 /**
@@ -332,10 +321,12 @@ static void fec_tbd_init(struct fec_priv *fec)
 	unsigned addr = (unsigned)fec->tbd_base;
 	unsigned size = roundup(2 * sizeof(struct fec_bd),
 				ARCH_DMA_MINALIGN);
-	writew(0x0000, &fec->tbd_base[0].status);
-	writew(FEC_TBD_WRAP, &fec->tbd_base[1].status);
+
+	memset(fec->tbd_base, 0, size);
+	fec->tbd_base[0].status = 0;
+	fec->tbd_base[1].status = FEC_TBD_WRAP;
 	fec->tbd_index = 0;
-	flush_dcache_range(addr, addr+size);
+	flush_dcache_range(addr, addr + size);
 }
 
 /**
@@ -527,51 +518,18 @@ static int fec_init(struct eth_device *dev, bd_t* bd)
 {
 	struct fec_priv *fec = (struct fec_priv *)dev->priv;
 	uint32_t mib_ptr = (uint32_t)&fec->eth->rmon_t_drop;
-	uint32_t size;
-	int i, ret;
+	int i;
 
 	/* Initialize MAC address */
 	fec_set_hwaddr(dev);
 
 	/*
-	 * Allocate transmit descriptors, there are two in total. This
-	 * allocation respects cache alignment.
+	 * Setup transmit descriptors, there are two in total.
 	 */
-	if (!fec->tbd_base) {
-		size = roundup(2 * sizeof(struct fec_bd),
-				ARCH_DMA_MINALIGN);
-		fec->tbd_base = memalign(ARCH_DMA_MINALIGN, size);
-		if (!fec->tbd_base) {
-			ret = -ENOMEM;
-			goto err1;
-		}
-		memset(fec->tbd_base, 0, size);
-		fec_tbd_init(fec);
-	}
+	fec_tbd_init(fec);
 
-	/*
-	 * Allocate receive descriptors. This allocation respects cache
-	 * alignment.
-	 */
-	if (!fec->rbd_base) {
-		size = roundup(FEC_RBD_NUM * sizeof(struct fec_bd),
-				ARCH_DMA_MINALIGN);
-		fec->rbd_base = memalign(ARCH_DMA_MINALIGN, size);
-		if (!fec->rbd_base) {
-			ret = -ENOMEM;
-			goto err2;
-		}
-		memset(fec->rbd_base, 0, size);
-		/*
-		 * Initialize RxBD ring
-		 */
-		if (fec_rbd_init(fec, FEC_RBD_NUM, FEC_MAX_PKT_SIZE) < 0) {
-			ret = -ENOMEM;
-			goto err3;
-		}
-		flush_dcache_range((unsigned)fec->rbd_base,
-				   (unsigned)fec->rbd_base + size);
-	}
+	/* Setup receive descriptors. */
+	fec_rbd_init(fec, FEC_RBD_NUM, FEC_MAX_PKT_SIZE);
 
 	fec_reg_setup(fec);
 
@@ -608,13 +566,6 @@ static int fec_init(struct eth_device *dev, bd_t* bd)
 #endif
 	fec_open(dev);
 	return 0;
-
-err3:
-	free(fec->rbd_base);
-err2:
-	free(fec->tbd_base);
-err1:
-	return ret;
 }
 
 /**
@@ -907,6 +858,74 @@ static void fec_set_dev_name(char *dest, int dev_id)
 	sprintf(dest, (dev_id == -1) ? "FEC" : "FEC%i", dev_id);
 }
 
+static int fec_alloc_descs(struct fec_priv *fec)
+{
+	unsigned int size;
+	int i;
+	uint8_t *data;
+
+	/* Allocate TX descriptors. */
+	size = roundup(2 * sizeof(struct fec_bd), ARCH_DMA_MINALIGN);
+	fec->tbd_base = memalign(ARCH_DMA_MINALIGN, size);
+	if (!fec->tbd_base)
+		goto err_tx;
+
+	/* Allocate RX descriptors. */
+	size = roundup(FEC_RBD_NUM * sizeof(struct fec_bd), ARCH_DMA_MINALIGN);
+	fec->rbd_base = memalign(ARCH_DMA_MINALIGN, size);
+	if (!fec->rbd_base)
+		goto err_rx;
+
+	memset(fec->rbd_base, 0, size);
+
+	/* Allocate RX buffers. */
+
+	/* Maximum RX buffer size. */
+	size = roundup(FEC_MAX_PKT_SIZE, ARCH_DMA_MINALIGN);
+	for (i = 0; i < FEC_RBD_NUM; i++) {
+		data = memalign(ARCH_DMA_MINALIGN, size);
+		if (!data) {
+			printf("%s: error allocating rxbuf %d\n", __func__, i);
+			goto err_ring;
+		}
+
+		memset(data, 0, size);
+
+		fec->rbd_base[i].data_pointer = (uint32_t)data;
+		fec->rbd_base[i].status = FEC_RBD_EMPTY;
+		fec->rbd_base[i].data_length = 0;
+		/* Flush the buffer to memory. */
+		flush_dcache_range((uint32_t)data, (uint32_t)data + size);
+	}
+
+	/* Mark the last RBD to close the ring. */
+	fec->rbd_base[i - 1].status = FEC_RBD_WRAP | FEC_RBD_EMPTY;
+
+	fec->rbd_index = 0;
+	fec->tbd_index = 0;
+
+	return 0;
+
+err_ring:
+	for (; i >= 0; i--)
+		free((void *)fec->rbd_base[i].data_pointer);
+	free(fec->rbd_base);
+err_rx:
+	free(fec->tbd_base);
+err_tx:
+	return -ENOMEM;
+}
+
+static void fec_free_descs(struct fec_priv *fec)
+{
+	int i;
+
+	for (i = 0; i < FEC_RBD_NUM; i++)
+		free((void *)fec->rbd_base[i].data_pointer);
+	free(fec->rbd_base);
+	free(fec->tbd_base);
+}
+
 #ifdef CONFIG_PHYLIB
 int fec_probe(bd_t *bd, int dev_id, uint32_t base_addr,
 		struct mii_dev *bus, struct phy_device *phydev)
@@ -939,6 +958,10 @@ static int fec_probe(bd_t *bd, int dev_id, uint32_t base_addr,
 	memset(edev, 0, sizeof(*edev));
 	memset(fec, 0, sizeof(*fec));
 
+	ret = fec_alloc_descs(fec);
+	if (ret)
+		goto err3;
+
 	edev->priv = fec;
 	edev->init = fec_init;
 	edev->send = fec_send;
@@ -957,7 +980,7 @@ static int fec_probe(bd_t *bd, int dev_id, uint32_t base_addr,
 	while (readl(&fec->eth->ecntrl) & FEC_ECNTRL_RESET) {
 		if (get_timer(start) > (CONFIG_SYS_HZ * 5)) {
 			printf("FEC MXC: Timeout reseting chip\n");
-			goto err3;
+			goto err4;
 		}
 		udelay(10);
 	}
@@ -984,6 +1007,8 @@ static int fec_probe(bd_t *bd, int dev_id, uint32_t base_addr,
 			eth_setenv_enetaddr("ethaddr", ethaddr);
 	}
 	return ret;
+err4:
+	fec_free_descs(fec);
 err3:
 	free(fec);
 err2:
diff --git a/drivers/net/fm/Makefile b/drivers/net/fm/Makefile
index 4edd849268..ee5d768937 100644
--- a/drivers/net/fm/Makefile
+++ b/drivers/net/fm/Makefile
@@ -4,50 +4,33 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	:= $(obj)libfm.o
-
-ifdef CONFIG_FMAN_ENET
-COBJS-y += dtsec.o
-COBJS-y += eth.o
-COBJS-y += fm.o
-COBJS-y += init.o
-COBJS-y += tgec.o
-COBJS-y += tgec_phy.o
+obj-y += dtsec.o
+obj-y += eth.o
+obj-y += fm.o
+obj-y += init.o
+obj-y += tgec.o
+obj-y += tgec_phy.o
 
 # Soc have FMAN v3 with mEMAC
-COBJS-$(CONFIG_SYS_FMAN_V3) += memac_phy.o
-COBJS-$(CONFIG_SYS_FMAN_V3) += memac.o
+obj-$(CONFIG_SYS_FMAN_V3) += memac_phy.o
+obj-$(CONFIG_SYS_FMAN_V3) += memac.o
 
 # SoC specific SERDES support
-COBJS-$(CONFIG_P1017)	+= p1023.o
-COBJS-$(CONFIG_P1023)	+= p1023.o
+obj-$(CONFIG_P1017)	+= p1023.o
+obj-$(CONFIG_P1023)	+= p1023.o
 # The P204x, P304x, and P5020 are the same
-COBJS-$(CONFIG_PPC_P2041) += p5020.o
-COBJS-$(CONFIG_PPC_P3041) += p5020.o
-COBJS-$(CONFIG_PPC_P4080) += p4080.o
-COBJS-$(CONFIG_PPC_P5020) += p5020.o
-COBJS-$(CONFIG_PPC_P5040) += p5040.o
-COBJS-$(CONFIG_PPC_T4240) += t4240.o
-COBJS-$(CONFIG_PPC_T4160) += t4240.o
-COBJS-$(CONFIG_PPC_B4420) += b4860.o
-COBJS-$(CONFIG_PPC_B4860) += b4860.o
-endif
-
-COBJS	:= $(COBJS-y)
-SRCS	:= $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-
-all:	$(LIB)
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-$(CONFIG_PPC_P2041) += p5020.o
+obj-$(CONFIG_PPC_P3041) += p5020.o
+obj-$(CONFIG_PPC_P4080) += p4080.o
+obj-$(CONFIG_PPC_P5020) += p5020.o
+obj-$(CONFIG_PPC_P5040) += p5040.o
+obj-$(CONFIG_PPC_T1040) += t1040.o
+obj-$(CONFIG_PPC_T1042)	+= t1040.o
+obj-$(CONFIG_PPC_T1020)	+= t1040.o
+obj-$(CONFIG_PPC_T1022)	+= t1040.o
+obj-$(CONFIG_PPC_T2080) += t2080.o
+obj-$(CONFIG_PPC_T2081) += t2080.o
+obj-$(CONFIG_PPC_T4240) += t4240.o
+obj-$(CONFIG_PPC_T4160) += t4240.o
+obj-$(CONFIG_PPC_B4420) += b4860.o
+obj-$(CONFIG_PPC_B4860) += b4860.o
diff --git a/drivers/net/fm/b4860.c b/drivers/net/fm/b4860.c
index 9b3d5324e0..373cc4f424 100644
--- a/drivers/net/fm/b4860.c
+++ b/drivers/net/fm/b4860.c
@@ -37,6 +37,13 @@ void fman_disable_port(enum fm_port port)
 	setbits_be32(&gur->devdisr2, port_to_devdisr[port]);
 }
 
+void fman_enable_port(enum fm_port port)
+{
+	ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+
+	clrbits_be32(&gur->devdisr2, port_to_devdisr[port]);
+}
+
 phy_interface_t fman_port_enet_if(enum fm_port port)
 {
 	if (is_device_disabled(port))
diff --git a/drivers/net/fm/eth.c b/drivers/net/fm/eth.c
index cb099cd849..218a5ed175 100644
--- a/drivers/net/fm/eth.c
+++ b/drivers/net/fm/eth.c
@@ -557,8 +557,16 @@ static int fm_eth_init_mac(struct fm_eth *fm_eth, struct ccsr_fman *reg)
 	num = fm_eth->num;
 
 #ifdef CONFIG_SYS_FMAN_V3
-	if (fm_eth->type == FM_ETH_10G_E)
-		num += 8;
+	if (fm_eth->type == FM_ETH_10G_E) {
+		/* 10GEC1/10GEC2 use mEMAC9/mEMAC10
+		 * 10GEC3/10GEC4 use mEMAC1/mEMAC2
+		 * so it needs to change the num.
+		 */
+		if (fm_eth->num >= 2)
+			num -= 2;
+		else
+			num += 8;
+	}
 	base = &reg->memac[num].fm_memac;
 	phyregs = &reg->memac[num].fm_memac_mdio;
 #else
diff --git a/drivers/net/fm/fm.h b/drivers/net/fm/fm.h
index 38fdbcdc42..43de114b52 100644
--- a/drivers/net/fm/fm.h
+++ b/drivers/net/fm/fm.h
@@ -18,9 +18,12 @@
 #define RX_PORT_1G_BASE		0x08
 #define MAX_NUM_RX_PORT_1G	CONFIG_SYS_NUM_FM1_DTSEC
 #define RX_PORT_10G_BASE	0x10
+#define RX_PORT_10G_BASE2	0x08
 #define TX_PORT_1G_BASE		0x28
 #define MAX_NUM_TX_PORT_1G	CONFIG_SYS_NUM_FM1_DTSEC
 #define TX_PORT_10G_BASE	0x30
+#define TX_PORT_10G_BASE2	0x28
+#define MIIM_TIMEOUT    0xFFFF
 
 struct fm_muram {
 	u32 base;
@@ -98,6 +101,7 @@ int fm_init_common(int index, struct ccsr_fman *reg);
 int fm_eth_initialize(struct ccsr_fman *reg, struct fm_eth_info *info);
 phy_interface_t fman_port_enet_if(enum fm_port port);
 void fman_disable_port(enum fm_port port);
+void fman_enable_port(enum fm_port port);
 
 struct fsl_enet_mac {
 	void *base; /* MAC controller registers base address */
diff --git a/drivers/net/fm/init.c b/drivers/net/fm/init.c
index 14fa2ce59c..cd787f4eed 100644
--- a/drivers/net/fm/init.c
+++ b/drivers/net/fm/init.c
@@ -64,6 +64,12 @@ struct fm_eth_info fm_info[] = {
 #if (CONFIG_SYS_NUM_FM1_10GEC >= 2)
 	FM_TGEC_INFO_INITIALIZER(1, 2),
 #endif
+#if (CONFIG_SYS_NUM_FM1_10GEC >= 3)
+	FM_TGEC_INFO_INITIALIZER2(1, 3),
+#endif
+#if (CONFIG_SYS_NUM_FM1_10GEC >= 4)
+	FM_TGEC_INFO_INITIALIZER2(1, 4),
+#endif
 #if (CONFIG_SYS_NUM_FM2_10GEC >= 1)
 	FM_TGEC_INFO_INITIALIZER(2, 1),
 #endif
@@ -145,6 +151,14 @@ void fm_disable_port(enum fm_port port)
 	fman_disable_port(port);
 }
 
+void fm_enable_port(enum fm_port port)
+{
+	int i = fm_port_to_index(port);
+
+	fm_info[i].enabled = 1;
+	fman_enable_port(port);
+}
+
 void fm_info_set_mdio(enum fm_port port, struct mii_dev *bus)
 {
 	int i = fm_port_to_index(port);
@@ -231,10 +245,14 @@ static void ft_fixup_port(void *blob, struct fm_eth_info *info, char *prop)
 	 * FM1_10GEC1 is enabled and  FM1_DTSEC9 is disabled, ensure that the
 	 * dual-role MAC is not disabled, ditto for other dual-role MACs.
 	 */
-	if (((info->port == FM1_DTSEC9) && (PORT_IS_ENABLED(FM1_10GEC1)))	||
-	    ((info->port == FM1_DTSEC10) && (PORT_IS_ENABLED(FM1_10GEC2)))	||
-	    ((info->port == FM1_10GEC1) && (PORT_IS_ENABLED(FM1_DTSEC9)))	||
-	    ((info->port == FM1_10GEC2) && (PORT_IS_ENABLED(FM1_DTSEC10)))
+	if (((info->port == FM1_DTSEC9) && (PORT_IS_ENABLED(FM1_10GEC1)))  ||
+	    ((info->port == FM1_DTSEC10) && (PORT_IS_ENABLED(FM1_10GEC2))) ||
+	    ((info->port == FM1_DTSEC1) && (PORT_IS_ENABLED(FM1_10GEC3)))  ||
+	    ((info->port == FM1_DTSEC2) && (PORT_IS_ENABLED(FM1_10GEC4)))  ||
+	    ((info->port == FM1_10GEC1) && (PORT_IS_ENABLED(FM1_DTSEC9)))  ||
+	    ((info->port == FM1_10GEC2) && (PORT_IS_ENABLED(FM1_DTSEC10))) ||
+	    ((info->port == FM1_10GEC3) && (PORT_IS_ENABLED(FM1_DTSEC1)))  ||
+	    ((info->port == FM1_10GEC4) && (PORT_IS_ENABLED(FM1_DTSEC2)))
 #if (CONFIG_SYS_NUM_FMAN == 2)
 										||
 	    ((info->port == FM2_DTSEC9) && (PORT_IS_ENABLED(FM2_10GEC1)))	||
@@ -274,3 +292,47 @@ void fdt_fixup_fman_ethernet(void *blob)
 	}
 #endif
 }
+
+/*QSGMII Riser Card can work in SGMII mode, but the PHY address is different.
+ *This function scans which Riser Card being used(QSGMII or SGMII Riser Card),
+ *then set the correct PHY address
+ */
+void set_sgmii_phy(struct mii_dev *bus, enum fm_port base_port,
+		unsigned int port_num, int phy_base_addr)
+{
+	unsigned int regnum = 0;
+	int qsgmii;
+	int i;
+	int phy_real_addr;
+
+	qsgmii = is_qsgmii_riser_card(bus, phy_base_addr, port_num, regnum);
+
+	if (!qsgmii)
+		return;
+
+	for (i = base_port; i < base_port + port_num; i++) {
+		if (fm_info_get_enet_if(i) == PHY_INTERFACE_MODE_SGMII) {
+			phy_real_addr = phy_base_addr + i - base_port;
+			fm_info_set_phy_address(i, phy_real_addr);
+		}
+	}
+}
+
+/*to check whether qsgmii riser card is used*/
+int is_qsgmii_riser_card(struct mii_dev *bus, int phy_base_addr,
+		unsigned int port_num, unsigned regnum)
+{
+	int i;
+	int val;
+
+	if (!bus)
+		return 0;
+
+	for (i = phy_base_addr; i < phy_base_addr + port_num; i++) {
+		val = bus->read(bus, i, MDIO_DEVAD_NONE, regnum);
+		if (val != MIIM_TIMEOUT)
+			return 1;
+	}
+
+	return 0;
+}
diff --git a/drivers/net/fm/p1023.c b/drivers/net/fm/p1023.c
index 0eaad0f45d..b25d10ae0f 100644
--- a/drivers/net/fm/p1023.c
+++ b/drivers/net/fm/p1023.c
@@ -34,6 +34,13 @@ void fman_disable_port(enum fm_port port)
 	setbits_be32(&gur->devdisr, port_to_devdisr[port]);
 }
 
+void fman_enable_port(enum fm_port port)
+{
+	ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+
+	clrbits_be32(&gur->devdisr, port_to_devdisr[port]);
+}
+
 phy_interface_t fman_port_enet_if(enum fm_port port)
 {
 	ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
diff --git a/drivers/net/fm/p4080.c b/drivers/net/fm/p4080.c
index febfdd4e87..de71911355 100644
--- a/drivers/net/fm/p4080.c
+++ b/drivers/net/fm/p4080.c
@@ -42,6 +42,13 @@ void fman_disable_port(enum fm_port port)
 	setbits_be32(&gur->devdisr2, port_to_devdisr[port]);
 }
 
+void fman_enable_port(enum fm_port port)
+{
+	ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+
+	clrbits_be32(&gur->devdisr2, port_to_devdisr[port]);
+}
+
 phy_interface_t fman_port_enet_if(enum fm_port port)
 {
 	ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
diff --git a/drivers/net/fm/p5020.c b/drivers/net/fm/p5020.c
index 8d49c7bc1f..5c158cd5df 100644
--- a/drivers/net/fm/p5020.c
+++ b/drivers/net/fm/p5020.c
@@ -38,6 +38,13 @@ void fman_disable_port(enum fm_port port)
 	setbits_be32(&gur->devdisr2, port_to_devdisr[port]);
 }
 
+void fman_enable_port(enum fm_port port)
+{
+	ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+
+	clrbits_be32(&gur->devdisr2, port_to_devdisr[port]);
+}
+
 phy_interface_t fman_port_enet_if(enum fm_port port)
 {
 	ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
diff --git a/drivers/net/fm/p5040.c b/drivers/net/fm/p5040.c
index 546ebce567..403d7d7948 100644
--- a/drivers/net/fm/p5040.c
+++ b/drivers/net/fm/p5040.c
@@ -44,6 +44,13 @@ void fman_disable_port(enum fm_port port)
 	setbits_be32(&gur->devdisr2, port_to_devdisr[port]);
 }
 
+void fman_enable_port(enum fm_port port)
+{
+	ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+
+	clrbits_be32(&gur->devdisr2, port_to_devdisr[port]);
+}
+
 phy_interface_t fman_port_enet_if(enum fm_port port)
 {
 	ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
diff --git a/drivers/net/fm/t1040.c b/drivers/net/fm/t1040.c
new file mode 100644
index 0000000000..bcc871d842
--- /dev/null
+++ b/drivers/net/fm/t1040.c
@@ -0,0 +1,72 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+#include <common.h>
+#include <phy.h>
+#include <fm_eth.h>
+#include <asm/io.h>
+#include <asm/immap_85xx.h>
+#include <asm/fsl_serdes.h>
+
+phy_interface_t fman_port_enet_if(enum fm_port port)
+{
+	ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+	u32 rcwsr13 = in_be32(&gur->rcwsr[13]);
+
+	/* handle RGMII first */
+	if ((port == FM1_DTSEC2) &&
+	    ((rcwsr13 & FSL_CORENET_RCWSR13_MAC2_GMII_SEL) ==
+			FSL_CORENET_RCWSR13_MAC2_GMII_SEL_ENET_PORT)) {
+		if ((rcwsr13 & FSL_CORENET_RCWSR13_EC1) ==
+				FSL_CORENET_RCWSR13_EC1_FM1_DTSEC4_RGMII)
+			return PHY_INTERFACE_MODE_RGMII;
+		else if ((rcwsr13 & FSL_CORENET_RCWSR13_EC1) ==
+				FSL_CORENET_RCWSR13_EC1_FM1_DTSEC4_MII)
+			return PHY_INTERFACE_MODE_MII;
+		else
+			return PHY_INTERFACE_MODE_NONE;
+	}
+
+	if ((port == FM1_DTSEC4) &&
+	    ((rcwsr13 & FSL_CORENET_RCWSR13_MAC2_GMII_SEL) ==
+			FSL_CORENET_RCWSR13_MAC2_GMII_SEL_L2_SWITCH)) {
+		if ((rcwsr13 & FSL_CORENET_RCWSR13_EC1) ==
+				FSL_CORENET_RCWSR13_EC1_FM1_DTSEC4_RGMII)
+			return PHY_INTERFACE_MODE_RGMII;
+		else if ((rcwsr13 & FSL_CORENET_RCWSR13_EC1) ==
+				FSL_CORENET_RCWSR13_EC1_FM1_DTSEC4_MII)
+			return PHY_INTERFACE_MODE_MII;
+		else
+			return PHY_INTERFACE_MODE_NONE;
+	}
+
+	if (port == FM1_DTSEC5) {
+		if ((rcwsr13 & FSL_CORENET_RCWSR13_EC2) ==
+				FSL_CORENET_RCWSR13_EC2_FM1_DTSEC5_RGMII)
+			return PHY_INTERFACE_MODE_RGMII;
+		else if ((rcwsr13 & FSL_CORENET_RCWSR13_EC2) ==
+				FSL_CORENET_RCWSR13_EC2_FM1_DTSEC5_MII)
+			return PHY_INTERFACE_MODE_MII;
+		else
+			return PHY_INTERFACE_MODE_NONE;
+	}
+
+	switch (port) {
+	case FM1_DTSEC1:
+	case FM1_DTSEC2:
+		if (is_serdes_configured(QSGMII_SW1_A + port - FM1_DTSEC1))
+			return PHY_INTERFACE_MODE_QSGMII;
+	case FM1_DTSEC3:
+	case FM1_DTSEC4:
+	case FM1_DTSEC5:
+		if (is_serdes_configured(SGMII_FM1_DTSEC1 + port - FM1_DTSEC1))
+			return PHY_INTERFACE_MODE_SGMII;
+		break;
+	default:
+		return PHY_INTERFACE_MODE_NONE;
+	}
+
+	return PHY_INTERFACE_MODE_NONE;
+}
diff --git a/drivers/net/fm/t2080.c b/drivers/net/fm/t2080.c
new file mode 100644
index 0000000000..3b6212f858
--- /dev/null
+++ b/drivers/net/fm/t2080.c
@@ -0,0 +1,93 @@
+/*
+ * Copyright 2012 Freescale Semiconductor, Inc.
+ *
+ * Shengzhou Liu <Shengzhou.Liu@freescale.com>
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#include <common.h>
+#include <phy.h>
+#include <fm_eth.h>
+#include <asm/immap_85xx.h>
+#include <asm/fsl_serdes.h>
+
+u32 port_to_devdisr[] = {
+	[FM1_DTSEC1] = FSL_CORENET_DEVDISR2_DTSEC1_1,
+	[FM1_DTSEC2] = FSL_CORENET_DEVDISR2_DTSEC1_2,
+	[FM1_DTSEC3] = FSL_CORENET_DEVDISR2_DTSEC1_3,
+	[FM1_DTSEC4] = FSL_CORENET_DEVDISR2_DTSEC1_4,
+	[FM1_DTSEC5] = FSL_CORENET_DEVDISR2_DTSEC1_5,
+	[FM1_DTSEC6] = FSL_CORENET_DEVDISR2_DTSEC1_6,
+	[FM1_DTSEC9] = FSL_CORENET_DEVDISR2_DTSEC1_9,
+	[FM1_DTSEC10] = FSL_CORENET_DEVDISR2_DTSEC1_10,
+	[FM1_10GEC1] = FSL_CORENET_DEVDISR2_10GEC1_1,
+	[FM1_10GEC2] = FSL_CORENET_DEVDISR2_10GEC1_2,
+	[FM1_10GEC3] = FSL_CORENET_DEVDISR2_10GEC1_3,
+	[FM1_10GEC4] = FSL_CORENET_DEVDISR2_10GEC1_4,
+};
+
+static int is_device_disabled(enum fm_port port)
+{
+	ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+	u32 devdisr2 = in_be32(&gur->devdisr2);
+
+	return port_to_devdisr[port] & devdisr2;
+}
+
+void fman_disable_port(enum fm_port port)
+{
+	ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+
+	setbits_be32(&gur->devdisr2, port_to_devdisr[port]);
+}
+
+phy_interface_t fman_port_enet_if(enum fm_port port)
+{
+	ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+	u32 rcwsr13 = in_be32(&gur->rcwsr[13]);
+
+	if (is_device_disabled(port))
+		return PHY_INTERFACE_MODE_NONE;
+
+	if ((port == FM1_10GEC1 || port == FM1_10GEC2) &&
+	    ((is_serdes_configured(XAUI_FM1_MAC9))	||
+	     (is_serdes_configured(XFI_FM1_MAC9))	||
+	     (is_serdes_configured(XFI_FM1_MAC10))))
+		return PHY_INTERFACE_MODE_XGMII;
+
+	if ((port == FM1_10GEC3 || port == FM1_10GEC4) &&
+	    ((is_serdes_configured(XFI_FM1_MAC1))	||
+	     (is_serdes_configured(XFI_FM1_MAC2))))
+		return PHY_INTERFACE_MODE_XGMII;
+
+	if ((port == FM1_DTSEC3) && ((rcwsr13 & FSL_CORENET_RCWSR13_EC1) ==
+		FSL_CORENET_RCWSR13_EC1_DTSEC3_RGMII))
+		return PHY_INTERFACE_MODE_RGMII;
+
+	if ((port == FM1_DTSEC4) && ((rcwsr13 & FSL_CORENET_RCWSR13_EC2) ==
+		FSL_CORENET_RCWSR13_EC2_DTSEC4_RGMII))
+		return PHY_INTERFACE_MODE_RGMII;
+
+	if ((port == FM1_DTSEC10) && ((rcwsr13 & FSL_CORENET_RCWSR13_EC2) ==
+		FSL_CORENET_RCWSR13_EC2_DTSEC10_RGMII))
+		return PHY_INTERFACE_MODE_RGMII;
+
+	switch (port) {
+	case FM1_DTSEC1:
+	case FM1_DTSEC2:
+	case FM1_DTSEC3:
+	case FM1_DTSEC4:
+	case FM1_DTSEC5:
+	case FM1_DTSEC6:
+	case FM1_DTSEC9:
+	case FM1_DTSEC10:
+		if (is_serdes_configured(SGMII_FM1_DTSEC1 + port - FM1_DTSEC1))
+			return PHY_INTERFACE_MODE_SGMII;
+		break;
+	default:
+		return PHY_INTERFACE_MODE_NONE;
+	}
+
+	return PHY_INTERFACE_MODE_NONE;
+}
diff --git a/drivers/net/fm/t4240.c b/drivers/net/fm/t4240.c
index 6253f22f75..1eacb22841 100644
--- a/drivers/net/fm/t4240.c
+++ b/drivers/net/fm/t4240.c
@@ -49,6 +49,13 @@ void fman_disable_port(enum fm_port port)
 	setbits_be32(&gur->devdisr2, port_to_devdisr[port]);
 }
 
+void fman_enable_port(enum fm_port port)
+{
+	ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+
+	clrbits_be32(&gur->devdisr2, port_to_devdisr[port]);
+}
+
 phy_interface_t fman_port_enet_if(enum fm_port port)
 {
 	ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
diff --git a/drivers/net/fsl_mdio.c b/drivers/net/fsl_mdio.c
index ce36bd7a34..1d88e6504b 100644
--- a/drivers/net/fsl_mdio.c
+++ b/drivers/net/fsl_mdio.c
@@ -1,5 +1,5 @@
 /*
- * Copyright 2009-2010 Freescale Semiconductor, Inc.
+ * Copyright 2009-2010, 2013 Freescale Semiconductor, Inc.
  *	Jun-jie Zhang <b18070@freescale.com>
  *	Mingkai Hu <Mingkai.hu@freescale.com>
  *
@@ -13,7 +13,7 @@
 #include <asm/errno.h>
 #include <asm/fsl_enet.h>
 
-void tsec_local_mdio_write(struct tsec_mii_mng *phyregs, int port_addr,
+void tsec_local_mdio_write(struct tsec_mii_mng __iomem *phyregs, int port_addr,
 		int dev_addr, int regnum, int value)
 {
 	int timeout = 1000000;
@@ -26,7 +26,7 @@ void tsec_local_mdio_write(struct tsec_mii_mng *phyregs, int port_addr,
 		;
 }
 
-int tsec_local_mdio_read(struct tsec_mii_mng *phyregs, int port_addr,
+int tsec_local_mdio_read(struct tsec_mii_mng __iomem *phyregs, int port_addr,
 		int dev_addr, int regnum)
 {
 	int value;
@@ -57,7 +57,8 @@ int tsec_local_mdio_read(struct tsec_mii_mng *phyregs, int port_addr,
 
 static int fsl_pq_mdio_reset(struct mii_dev *bus)
 {
-	struct tsec_mii_mng *regs = bus->priv;
+	struct tsec_mii_mng __iomem *regs =
+		(struct tsec_mii_mng __iomem *)bus->priv;
 
 	/* Reset MII (due to new addresses) */
 	out_be32(&regs->miimcfg, MIIMCFG_RESET_MGMT);
@@ -72,7 +73,8 @@ static int fsl_pq_mdio_reset(struct mii_dev *bus)
 
 int tsec_phy_read(struct mii_dev *bus, int addr, int dev_addr, int regnum)
 {
-	struct tsec_mii_mng *phyregs = bus->priv;
+	struct tsec_mii_mng __iomem *phyregs =
+		(struct tsec_mii_mng __iomem *)bus->priv;
 
 	return tsec_local_mdio_read(phyregs, addr, dev_addr, regnum);
 }
@@ -80,7 +82,8 @@ int tsec_phy_read(struct mii_dev *bus, int addr, int dev_addr, int regnum)
 int tsec_phy_write(struct mii_dev *bus, int addr, int dev_addr, int regnum,
 			u16 value)
 {
-	struct tsec_mii_mng *phyregs = bus->priv;
+	struct tsec_mii_mng __iomem *phyregs =
+		(struct tsec_mii_mng __iomem *)bus->priv;
 
 	tsec_local_mdio_write(phyregs, addr, dev_addr, regnum, value);
 
@@ -101,7 +104,7 @@ int fsl_pq_mdio_init(bd_t *bis, struct fsl_pq_mdio_info *info)
 	bus->reset = fsl_pq_mdio_reset;
 	sprintf(bus->name, info->name);
 
-	bus->priv = info->regs;
+	bus->priv = (void *)info->regs;
 
 	return mdio_register(bus);
 }
diff --git a/drivers/net/macb.c b/drivers/net/macb.c
index bf3983a00c..781a272cff 100644
--- a/drivers/net/macb.c
+++ b/drivers/net/macb.c
@@ -621,6 +621,24 @@ static u32 gem_mdc_clk_div(int id, struct macb_device *macb)
 	return config;
 }
 
+/*
+ * Get the DMA bus width field of the network configuration register that we
+ * should program. We find the width from decoding the design configuration
+ * register to find the maximum supported data bus width.
+ */
+static u32 macb_dbw(struct macb_device *macb)
+{
+	switch (GEM_BFEXT(DBWDEF, gem_readl(macb, DCFG1))) {
+	case 4:
+		return GEM_BF(DBW, GEM_DBW128);
+	case 2:
+		return GEM_BF(DBW, GEM_DBW64);
+	case 1:
+	default:
+		return GEM_BF(DBW, GEM_DBW32);
+	}
+}
+
 int macb_eth_initialize(int id, void *regs, unsigned int phy_addr)
 {
 	struct macb_device *macb;
@@ -665,7 +683,7 @@ int macb_eth_initialize(int id, void *regs, unsigned int phy_addr)
 	 */
 	if (macb_is_gem(macb)) {
 		ncfgr = gem_mdc_clk_div(id, macb);
-		ncfgr |= GEM_BF(DBW, 1);
+		ncfgr |= macb_dbw(macb);
 	} else {
 		ncfgr = macb_mdc_clk_div(id, macb);
 	}
diff --git a/drivers/net/macb.h b/drivers/net/macb.h
index de5214fe6e..06f7c66dfd 100644
--- a/drivers/net/macb.h
+++ b/drivers/net/macb.h
@@ -58,6 +58,9 @@
 #define MACB_WOL				0x00c4
 #define MACB_MID				0x00fc
 
+/* GEM specific register offsets */
+#define GEM_DCFG1				0x0280
+
 /* Bitfields in NCR */
 #define MACB_LB_OFFSET				0
 #define MACB_LB_SIZE				1
@@ -242,6 +245,14 @@
 #define MACB_IDNUM_SIZE				16
 
 /* Bitfields in DCFG1 */
+#define GEM_DBWDEF_OFFSET			25
+#define GEM_DBWDEF_SIZE				3
+
+/* constants for data bus width */
+#define GEM_DBW32				0
+#define GEM_DBW64				1
+#define GEM_DBW128				2
+
 /* Constants for CLK */
 #define MACB_CLK_DIV8				0
 #define MACB_CLK_DIV16				1
diff --git a/drivers/net/mvgbe.c b/drivers/net/mvgbe.c
index 6c901d1eaa..0cd06b6a69 100644
--- a/drivers/net/mvgbe.c
+++ b/drivers/net/mvgbe.c
@@ -420,8 +420,9 @@ static int mvgbe_init(struct eth_device *dev)
 {
 	struct mvgbe_device *dmvgbe = to_mvgbe(dev);
 	struct mvgbe_registers *regs = dmvgbe->regs;
-#if (defined (CONFIG_MII) || defined (CONFIG_CMD_MII)) \
-	 && defined (CONFIG_SYS_FAULT_ECHO_LINK_DOWN)
+#if (defined(CONFIG_MII) || defined(CONFIG_CMD_MII)) &&  \
+	!defined(CONFIG_PHYLIB) &&			 \
+	defined(CONFIG_SYS_FAULT_ECHO_LINK_DOWN)
 	int i;
 #endif
 	/* setup RX rings */
diff --git a/drivers/net/netconsole.c b/drivers/net/netconsole.c
index df8ab07b94..65c747e14b 100644
--- a/drivers/net/netconsole.c
+++ b/drivers/net/netconsole.c
@@ -184,7 +184,9 @@ static void nc_send_packet(const char *buf, int len)
 			return;	/* inside net loop */
 		output_packet = buf;
 		output_packet_len = len;
+		input_recursion = 1;
 		NetLoop(NETCONS); /* wait for arp reply and send packet */
+		input_recursion = 0;
 		output_packet_len = 0;
 		return;
 	}
diff --git a/drivers/net/nicext.h b/drivers/net/nicext.h
deleted file mode 100644
index ff422e7737..0000000000
--- a/drivers/net/nicext.h
+++ /dev/null
@@ -1,109 +0,0 @@
-/****************************************************************************
- * Copyright(c) 2000-2001 Broadcom Corporation. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation.
- *
- * Name:        nicext.h
- *
- * Description: Broadcom Network Interface Card Extension (NICE) is an
- *              extension to Linux NET device kernel mode drivers.
- *              NICE is designed to provide additional functionalities,
- *              such as receive packet intercept. To support Broadcom NICE,
- *              the network device driver can be modified by adding an
- *              device ioctl handler and by indicating receiving packets
- *              to the NICE receive handler. Broadcom NICE will only be
- *              enabled by a NICE-aware intermediate driver, such as
- *              Broadcom Advanced Server Program Driver (BASP). When NICE
- *              is not enabled, the modified network device drivers
- *              functions exactly as other non-NICE aware drivers.
- *
- * Author:      Frankie Fan
- *
- * Created:     September 17, 2000
- *
- ****************************************************************************/
-#ifndef _nicext_h_
-#define _nicext_h_
-
-/*
- * ioctl for NICE
- */
-#define SIOCNICE	SIOCDEVPRIVATE+7
-
-/*
- * SIOCNICE:
- *
- * The following structure needs to be less than IFNAMSIZ (16 bytes) because
- * we're overloading ifreq.ifr_ifru.
- *
- * If 16 bytes is not enough, we should consider relaxing this because
- * this is no field after ifr_ifru in the ifreq structure. But we may
- * run into future compatiability problem in case of changing struct ifreq.
- */
-struct nice_req
-{
-    __u32 cmd;
-
-    union
-    {
-#ifdef __KERNEL__
-	/* cmd = NICE_CMD_SET_RX or NICE_CMD_GET_RX */
-	struct
-	{
-	    void (*nrqus1_rx)( struct sk_buff*, void* );
-	    void* nrqus1_ctx;
-	} nrqu_nrqus1;
-
-	/* cmd = NICE_CMD_QUERY_SUPPORT */
-	struct
-	{
-	    __u32 nrqus2_magic;
-	    __u32 nrqus2_support_rx:1;
-	    __u32 nrqus2_support_vlan:1;
-	    __u32 nrqus2_support_get_speed:1;
-	} nrqu_nrqus2;
-#endif
-
-	/* cmd = NICE_CMD_GET_SPEED */
-	struct
-	{
-	    unsigned int nrqus3_speed; /* 0 if link is down, */
-				       /* otherwise speed in Mbps */
-	} nrqu_nrqus3;
-
-	/* cmd = NICE_CMD_BLINK_LED */
-	struct
-	{
-	    unsigned int nrqus4_blink_time; /* blink duration in seconds */
-	} nrqu_nrqus4;
-
-    } nrq_nrqu;
-};
-
-#define nrq_rx           nrq_nrqu.nrqu_nrqus1.nrqus1_rx
-#define nrq_ctx          nrq_nrqu.nrqu_nrqus1.nrqus1_ctx
-#define nrq_support_rx   nrq_nrqu.nrqu_nrqus2.nrqus2_support_rx
-#define nrq_magic        nrq_nrqu.nrqu_nrqus2.nrqus2_magic
-#define nrq_support_vlan nrq_nrqu.nrqu_nrqus2.nrqus2_support_vlan
-#define nrq_support_get_speed nrq_nrqu.nrqu_nrqus2.nrqus2_support_get_speed
-#define nrq_speed        nrq_nrqu.nrqu_nrqus3.nrqus3_speed
-#define nrq_blink_time   nrq_nrqu.nrqu_nrqus4.nrqus4_blink_time
-
-/*
- * magic constants
- */
-#define NICE_REQUESTOR_MAGIC            0x4543494E /* NICE in ascii */
-#define NICE_DEVICE_MAGIC               0x4E494345 /* ECIN in ascii */
-
-/*
- * command field
- */
-#define NICE_CMD_QUERY_SUPPORT          0x00000001
-#define NICE_CMD_SET_RX                 0x00000002
-#define NICE_CMD_GET_RX                 0x00000003
-#define NICE_CMD_GET_SPEED              0x00000004
-#define NICE_CMD_BLINK_LED              0x00000005
-
-#endif  /* _nicext_h_ */
diff --git a/drivers/net/npe/IxEthAcc.c b/drivers/net/npe/IxEthAcc.c
deleted file mode 100644
index 05a9e053ff..0000000000
--- a/drivers/net/npe/IxEthAcc.c
+++ /dev/null
@@ -1,237 +0,0 @@
-/**
- * @file IxEthAcc.c
- *
- * @author Intel Corporation
- * @date 20-Feb-2001
- *
- * @brief This file contains the implementation of the IXP425 Ethernet Access Component
- *
- * Design Notes:
- *
- * @par
- * IXP400 SW Release version 2.0
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * SPDX-License-Identifier:	BSD-3-Clause
- * @par
- * -- End of Copyright Notice --
- */
-
-
-
-#include "IxEthAcc.h"
-#ifdef CONFIG_IXP425_COMPONENT_ETHDB
-#include "IxEthDB.h"
-#endif
-#include "IxFeatureCtrl.h"
-
-#include "IxEthAcc_p.h"
-#include "IxEthAccMac_p.h"
-#include "IxEthAccMii_p.h"
-
-/**
- * @addtogroup IxEthAcc
- *@{
- */
-
-
-/**
- * @brief System-wide information data strucure.
- *
- * @ingroup IxEthAccPri
- *
- */
-
-IxEthAccInfo ixEthAccDataInfo;
-extern PUBLIC IxEthAccMacState ixEthAccMacState[];
-extern PUBLIC IxOsalMutex ixEthAccControlInterfaceMutex;
-
-/**
- * @brief System-wide information
- *
- * @ingroup IxEthAccPri
- *
- */
-BOOL ixEthAccServiceInit = false;
-
-/* global filtering bit mask */
-PUBLIC UINT32 ixEthAccNewSrcMask;
-
-/**
- * @brief Per port information data strucure.
- *
- * @ingroup IxEthAccPri
- *
- */
-
-IxEthAccPortDataInfo ixEthAccPortData[IX_ETH_ACC_NUMBER_OF_PORTS];
-
-PUBLIC IxEthAccStatus ixEthAccInit()
-{
-#ifdef CONFIG_IXP425_COMPONENT_ETHDB
-  /*
-   * Initialize Control plane
-   */
-  if (ixEthDBInit() != IX_ETH_DB_SUCCESS)
-  {
-      IX_ETH_ACC_WARNING_LOG("ixEthAccInit: EthDB init failed\n", 0, 0, 0, 0, 0, 0);
-
-      return IX_ETH_ACC_FAIL;
-  }
-#endif
-
-  if (IX_FEATURE_CTRL_SWCONFIG_ENABLED == ixFeatureCtrlSwConfigurationCheck (IX_FEATURECTRL_ETH_LEARNING))
-  {
-      ixEthAccNewSrcMask = (~0); /* want all the bits */
-  }
-  else
-  {
-      ixEthAccNewSrcMask = (~IX_ETHACC_NE_NEWSRCMASK); /* want all but the NewSrc bit */
-  }
-
-  /*
-   * Initialize Data plane
-   */
-   if ( ixEthAccInitDataPlane()  != IX_ETH_ACC_SUCCESS )
-   {
-      IX_ETH_ACC_WARNING_LOG("ixEthAccInit: data plane init failed\n", 0, 0, 0, 0, 0, 0);
-
-       return IX_ETH_ACC_FAIL;
-   }
-
-
-   if ( ixEthAccQMgrQueuesConfig() != IX_ETH_ACC_SUCCESS )
-   {
-      IX_ETH_ACC_WARNING_LOG("ixEthAccInit: queue config failed\n", 0, 0, 0, 0, 0, 0);
-
-       return IX_ETH_ACC_FAIL;
-   }
-
-   /*
-    * Initialize MII
-    */
-   if ( ixEthAccMiiInit() != IX_ETH_ACC_SUCCESS )
-   {
-      IX_ETH_ACC_WARNING_LOG("ixEthAccInit: Mii init failed\n", 0, 0, 0, 0, 0, 0);
-
-       return IX_ETH_ACC_FAIL;
-   }
-
-   /*
-    * Initialize MAC I/O memory
-    */
-   if (ixEthAccMacMemInit() != IX_ETH_ACC_SUCCESS)
-   {
-      IX_ETH_ACC_WARNING_LOG("ixEthAccInit: Mac init failed\n", 0, 0, 0, 0, 0, 0);
-
-     return IX_ETH_ACC_FAIL;
-   }
-
-   /*
-    * Initialize control plane interface lock
-    */
-   if (ixOsalMutexInit(&ixEthAccControlInterfaceMutex) != IX_SUCCESS)
-   {
-       IX_ETH_ACC_WARNING_LOG("ixEthAccInit: Control plane interface lock initialization failed\n", 0, 0, 0, 0, 0, 0);
-
-       return IX_ETH_ACC_FAIL;
-   }
-
-   /* initialiasation is complete */
-   ixEthAccServiceInit = true;
-
-   return IX_ETH_ACC_SUCCESS;
-
-}
-
-PUBLIC void ixEthAccUnload(void)
-{
-    IxEthAccPortId portId;
-
-    if ( IX_ETH_ACC_IS_SERVICE_INITIALIZED() )
-    {
-       /* check none of the port is still active */
-       for (portId = 0; portId < IX_ETH_ACC_NUMBER_OF_PORTS; portId++)
-       {
-	   if ( IX_ETH_IS_PORT_INITIALIZED(portId) )
-	   {
-	       if (ixEthAccMacState[portId].portDisableState == ACTIVE)
-	       {
-		   IX_ETH_ACC_WARNING_LOG("ixEthAccUnload: port %u still active, bail out\n", portId, 0, 0, 0, 0, 0);
-		   return;
-	       }
-	   }
-       }
-
-       /* unmap the memory areas */
-       ixEthAccMiiUnload();
-       ixEthAccMacUnload();
-
-       /* set all ports as uninitialized */
-       for (portId = 0; portId < IX_ETH_ACC_NUMBER_OF_PORTS; portId++)
-       {
-	       ixEthAccPortData[portId].portInitialized = false;
-       }
-
-       /* uninitialize the service */
-       ixEthAccServiceInit = false;
-   }
-}
-
-PUBLIC IxEthAccStatus ixEthAccPortInit( IxEthAccPortId portId)
-{
-
-  IxEthAccStatus ret=IX_ETH_ACC_SUCCESS;
-
-   if ( ! IX_ETH_ACC_IS_SERVICE_INITIALIZED() )
-   {
-	return(IX_ETH_ACC_FAIL);
-   }
-
-   /*
-    * Check for valid port
-    */
-
-   if ( ! IX_ETH_ACC_IS_PORT_VALID(portId) )
-   {
-       return (IX_ETH_ACC_INVALID_PORT);
-   }
-
-   if (IX_ETH_ACC_SUCCESS != ixEthAccSingleEthNpeCheck(portId))
-   {
-       IX_ETH_ACC_WARNING_LOG("EthAcc: Unavailable Eth %d: Cannot initialize Eth port.\n",(INT32) portId,0,0,0,0,0);
-       return IX_ETH_ACC_SUCCESS ;
-   }
-
-   if ( IX_ETH_IS_PORT_INITIALIZED(portId) )
-   {
-	/* Already initialized */
-	return(IX_ETH_ACC_FAIL);
-   }
-
-   if(ixEthAccMacInit(portId)!=IX_ETH_ACC_SUCCESS)
-   {
-       return IX_ETH_ACC_FAIL;
-   }
-
-   /*
-     * Set the port init flag.
-     */
-
-    ixEthAccPortData[portId].portInitialized = true;
-
-#ifdef CONFIG_IXP425_COMPONENT_ETHDB
-    /* init learning/filtering database structures for this port */
-    ixEthDBPortInit(portId);
-#endif
-
-    return(ret);
-}
-
-
diff --git a/drivers/net/npe/IxEthAccCommon.c b/drivers/net/npe/IxEthAccCommon.c
deleted file mode 100644
index 8249737b0c..0000000000
--- a/drivers/net/npe/IxEthAccCommon.c
+++ /dev/null
@@ -1,1025 +0,0 @@
-/**
- * @file IxEthAccCommon.c
- *
- * @author Intel Corporation
- * @date 12-Feb-2002
- *
- * @brief This file contains the implementation common support routines for the component
- *
- * Design Notes:
- *
- * @par
- * IXP400 SW Release version 2.0
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * SPDX-License-Identifier:	BSD-3-Clause
- * @par
- * -- End of Copyright Notice --
- */
-
-/*
- * Component header files
- */
-
-#include "IxOsal.h"
-#include "IxEthAcc.h"
-#include "IxEthDB.h"
-#include "IxNpeMh.h"
-#include "IxEthDBPortDefs.h"
-#include "IxFeatureCtrl.h"
-#include "IxEthAcc_p.h"
-#include "IxEthAccQueueAssign_p.h"
-
-#include "IxEthAccDataPlane_p.h"
-#include "IxEthAccMii_p.h"
-
-/**
- * @addtogroup IxEthAccPri
- *@{
- */
-
-extern IxEthAccInfo   ixEthAccDataInfo;
-
-/**
- *
- * @brief Maximum number of RX queues set to be the maximum number
- * of traffic calsses.
- *
- */
-#define IX_ETHACC_MAX_RX_QUEUES \
-      (IX_ETH_DB_QOS_TRAFFIC_CLASS_7_RX_QUEUE_PROPERTY \
-      - IX_ETH_DB_QOS_TRAFFIC_CLASS_0_RX_QUEUE_PROPERTY \
-      + 1)
-
-/**
- *
- * @brief Maximum number of 128 entry RX queues
- *
- */
-#define IX_ETHACC_MAX_LARGE_RX_QUEUES 4
-
-/**
- *
- * @brief Data structure template for Default RX Queues
- *
- */
-IX_ETH_ACC_PRIVATE
-IxEthAccQregInfo ixEthAccQmgrRxDefaultTemplate =
-  {
-    IX_ETH_ACC_RX_FRAME_ETH_Q,	     /**< Queue ID */
-    "Eth Rx Q",
-    ixEthRxFrameQMCallback,          /**< Functional callback */
-    (IxQMgrCallbackId) 0,	     /**< Callback tag	      */
-    IX_QMGR_Q_SIZE128,		     /**< Allocate Max Size Q */
-    IX_QMGR_Q_ENTRY_SIZE1,	     /**< Queue Entry Sizes - all Q entries are single word entries   */
-    true,			     /**< Enable Q notification at startup */
-    IX_ETH_ACC_RX_FRAME_ETH_Q_SOURCE,/**< Q Condition to drive callback   */
-    IX_QMGR_Q_WM_LEVEL0,	     /**< Q Low water mark */
-    IX_QMGR_Q_WM_LEVEL1,	     /**< Q High water mark - needed by NPE */
-  };
-
-/**
- *
- * @brief Data structure template for Small RX Queues
- *
- */
-IX_ETH_ACC_PRIVATE
-IxEthAccQregInfo ixEthAccQmgrRxSmallTemplate =
-  {
-    IX_ETH_ACC_RX_FRAME_ETH_Q,	     /**< Queue ID */
-    "Eth Rx Q",
-    ixEthRxFrameQMCallback,          /**< Functional callback */
-    (IxQMgrCallbackId) 0,	     /**< Callback tag	      */
-    IX_QMGR_Q_SIZE64,		     /**< Allocate Smaller Q */
-    IX_QMGR_Q_ENTRY_SIZE1,	     /**< Queue Entry Sizes - all Q entries are single word entries   */
-    true,			     /**< Enable Q notification at startup */
-    IX_ETH_ACC_RX_FRAME_ETH_Q_SOURCE,/**< Q Condition to drive callback   */
-    IX_QMGR_Q_WM_LEVEL0,	     /**< Q Low water mark */
-    IX_QMGR_Q_WM_LEVEL1,	     /**< Q High water mark - needed by NPE */
-  };
-
-
-/**
- *
- * @brief Data structure used to register & initialize the Queues
- *
- */
-IX_ETH_ACC_PRIVATE
-IxEthAccQregInfo ixEthAccQmgrStaticInfo[]=
-{
-  {
-    IX_ETH_ACC_RX_FREE_BUFF_ENET0_Q,
-    "Eth Rx Fr Q 1",
-    ixEthRxFreeQMCallback,
-    (IxQMgrCallbackId) IX_ETH_PORT_1,
-    IX_QMGR_Q_SIZE128,		     /**< Allocate Max Size Q */
-    IX_QMGR_Q_ENTRY_SIZE1,	     /**< Queue Entry Sizes - all Q entries are single word entries   */
-    false,			     /**< Disable Q notification at startup */
-    IX_ETH_ACC_RX_FREE_BUFF_ENET0_Q_SOURCE, /**< Q Condition to drive callback  */
-    IX_QMGR_Q_WM_LEVEL0,	     /***< Q Low water mark */
-    IX_QMGR_Q_WM_LEVEL64,	     /**< Q High water mark */
-  },
-
-  {
-    IX_ETH_ACC_RX_FREE_BUFF_ENET1_Q,
-    "Eth Rx Fr Q 2",
-    ixEthRxFreeQMCallback,
-    (IxQMgrCallbackId) IX_ETH_PORT_2,
-    IX_QMGR_Q_SIZE128,		     /**< Allocate Max Size Q */
-    IX_QMGR_Q_ENTRY_SIZE1,	     /**< Queue Entry Sizes - all Q entries are single word entries   */
-    false,			     /**< Disable Q notification at startup */
-    IX_ETH_ACC_RX_FREE_BUFF_ENET1_Q_SOURCE,  /**< Q Condition to drive callback  */
-    IX_QMGR_Q_WM_LEVEL0,	     /**< Q Low water mark */
-    IX_QMGR_Q_WM_LEVEL64,	     /**< Q High water mark */
-  },
-#ifdef __ixp46X
-  {
-    IX_ETH_ACC_RX_FREE_BUFF_ENET2_Q,
-    "Eth Rx Fr Q 3",
-    ixEthRxFreeQMCallback,
-    (IxQMgrCallbackId) IX_ETH_PORT_3,
-    IX_QMGR_Q_SIZE128,		     /**< Allocate Max Size Q */
-    IX_QMGR_Q_ENTRY_SIZE1,	     /**< Queue Entry Sizes - all Q entries are single word entries   */
-    false,			     /**< Disable Q notification at startup */
-    IX_ETH_ACC_RX_FREE_BUFF_ENET2_Q_SOURCE,  /**< Q Condition to drive callback  */
-    IX_QMGR_Q_WM_LEVEL0,	     /**< Q Low water mark */
-    IX_QMGR_Q_WM_LEVEL64,	     /**< Q High water mark */
-  },
-#endif
-  {
-     IX_ETH_ACC_TX_FRAME_ENET0_Q,
-    "Eth Tx Q 1",
-     ixEthTxFrameQMCallback,
-     (IxQMgrCallbackId) IX_ETH_PORT_1,
-    IX_QMGR_Q_SIZE128,		     /**< Allocate Max Size Q */
-    IX_QMGR_Q_ENTRY_SIZE1,	     /**< Queue Entry Sizes - all Q entries are single word entries   */
-    false,			     /**< Disable Q notification at startup */
-    IX_ETH_ACC_TX_FRAME_ENET0_Q_SOURCE,	 /**< Q Condition to drive callback  */
-    IX_QMGR_Q_WM_LEVEL0,	     /**< Q Low water mark */
-    IX_QMGR_Q_WM_LEVEL64,	     /**< Q High water mark */
-  },
-
-  {
-     IX_ETH_ACC_TX_FRAME_ENET1_Q,
-    "Eth Tx Q 2",
-     ixEthTxFrameQMCallback,
-     (IxQMgrCallbackId) IX_ETH_PORT_2,
-    IX_QMGR_Q_SIZE128,		     /**< Allocate Max Size Q */
-    IX_QMGR_Q_ENTRY_SIZE1,	     /**< Queue Entry Sizes - all Q entries are single word entries   */
-    false,			     /**< Disable Q notification at startup */
-    IX_ETH_ACC_TX_FRAME_ENET1_Q_SOURCE,	     /**< Q Condition to drive callback  */
-    IX_QMGR_Q_WM_LEVEL0,	     /**< Q Low water mark */
-    IX_QMGR_Q_WM_LEVEL64,	     /**< Q High water mark */
-  },
-#ifdef __ixp46X
-  {
-     IX_ETH_ACC_TX_FRAME_ENET2_Q,
-    "Eth Tx Q 3",
-     ixEthTxFrameQMCallback,
-     (IxQMgrCallbackId) IX_ETH_PORT_3,
-    IX_QMGR_Q_SIZE128,		     /**< Allocate Max Size Q */
-    IX_QMGR_Q_ENTRY_SIZE1,	     /** Queue Entry Sizes - all Q entries are single ord entries   */
-    false,			     /** Disable Q notification at startup */
-    IX_ETH_ACC_TX_FRAME_ENET2_Q_SOURCE,	     /** Q Condition to drive callback  */
-    IX_QMGR_Q_WM_LEVEL0,	     /* No queues use almost empty */
-    IX_QMGR_Q_WM_LEVEL64,	      /** Q High water mark - needed used  */
-  },
-#endif
-  {
-     IX_ETH_ACC_TX_FRAME_DONE_ETH_Q,
-    "Eth Tx Done Q",
-     ixEthTxFrameDoneQMCallback,
-     (IxQMgrCallbackId) 0,
-    IX_QMGR_Q_SIZE128,		     /**< Allocate Max Size Q */
-    IX_QMGR_Q_ENTRY_SIZE1,	     /**< Queue Entry Sizes - all Q entries are single word entries   */
-    true,			     /**< Enable Q notification at startup */
-    IX_ETH_ACC_TX_FRAME_DONE_ETH_Q_SOURCE, /**< Q Condition to drive callback  */
-    IX_QMGR_Q_WM_LEVEL0,	     /**< Q Low water mark */
-    IX_QMGR_Q_WM_LEVEL2,	     /**< Q High water mark - needed by NPE */
-  },
-
-  {  /* Null Termination entry
-      */
-     (IxQMgrQId)0,
-     (char *) NULL,
-     (IxQMgrCallback) NULL,
-     (IxQMgrCallbackId) 0,
-     0,
-     0,
-     0,
-     0,
-     0,
-     0
-  }
-
-};
-
-/**
- *
- * @brief Data structure used to register & initialize the Queues
- *
- * The structure will be filled at run time depending on the NPE
- * image already loaded and the QoS configured in ethDB.
- *
- */
-IX_ETH_ACC_PRIVATE
-IxEthAccQregInfo ixEthAccQmgrRxQueuesInfo[IX_ETHACC_MAX_RX_QUEUES+1]=
-{
-  {  /* PlaceHolder for rx queues
-      * depending on the QoS configured
-      */
-     (IxQMgrQId)0,
-     (char *) NULL,
-     (IxQMgrCallback) NULL,
-     (IxQMgrCallbackId) 0,
-     0,
-     0,
-     0,
-     0,
-     0,
-     0
-  },
-
-  {  /* PlaceHolder for rx queues
-      * depending on the QoS configured
-      */
-     (IxQMgrQId)0,
-     (char *) NULL,
-     (IxQMgrCallback) NULL,
-     (IxQMgrCallbackId) 0,
-     0,
-     0,
-     0,
-     0,
-     0,
-     0
-  },
-
-  {  /* PlaceHolder for rx queues
-      * depending on the QoS configured
-      */
-     (IxQMgrQId)0,
-     (char *) NULL,
-     (IxQMgrCallback) NULL,
-     (IxQMgrCallbackId) 0,
-     0,
-     0,
-     0,
-     0,
-     0,
-     0
-  },
-
-  {  /* PlaceHolder for rx queues
-      * depending on the QoS configured
-      */
-     (IxQMgrQId)0,
-     (char *) NULL,
-     (IxQMgrCallback) NULL,
-     (IxQMgrCallbackId) 0,
-     0,
-     0,
-     0,
-     0,
-     0,
-     0
-  },
-
-  {  /* PlaceHolder for rx queues
-      * depending on the QoS configured
-      */
-     (IxQMgrQId)0,
-     (char *) NULL,
-     (IxQMgrCallback) NULL,
-     (IxQMgrCallbackId) 0,
-     0,
-     0,
-     0,
-     0,
-     0,
-     0
-  },
-
-  {  /* PlaceHolder for rx queues
-      * depending on the QoS configured
-      */
-      (IxQMgrQId)0,
-     (char *) NULL,
-     (IxQMgrCallback) NULL,
-     (IxQMgrCallbackId) 0,
-     0,
-     0,
-     0,
-     0,
-     0,
-     0
-  },
-
-  {  /* PlaceHolder for rx queues
-      * depending on the QoS configured
-      */
-     (IxQMgrQId)0,
-     (char *) NULL,
-     (IxQMgrCallback) NULL,
-     (IxQMgrCallbackId) 0,
-     0,
-     0,
-     0,
-     0,
-     0,
-     0
-  },
-
-  {  /* PlaceHolder for rx queues
-      * depending on the QoS configured
-      */
-     (IxQMgrQId)0,
-     (char *) NULL,
-     (IxQMgrCallback) NULL,
-     (IxQMgrCallbackId) 0,
-     0,
-     0,
-     0,
-     0,
-     0,
-     0
-  },
-
-  {  /* Null Termination entry
-      */
-     (IxQMgrQId)0,
-     (char *) NULL,
-     (IxQMgrCallback) NULL,
-     (IxQMgrCallbackId) 0,
-     0,
-     0,
-     0,
-     0,
-     0,
-     0
-  }
-
-};
-
-/* forward declarations */
-IX_ETH_ACC_PRIVATE IxEthAccStatus
-ixEthAccQMgrQueueSetup(IxEthAccQregInfo *qInfoDes);
-
-/**
- * @fn ixEthAccQMgrQueueSetup(void)
- *
- * @brief Setup one queue and its event, and register the callback required
- * by this component to the QMgr
- *
- * @internal
- */
-IX_ETH_ACC_PRIVATE IxEthAccStatus
-ixEthAccQMgrQueueSetup(IxEthAccQregInfo *qInfoDes)
-{
-    /*
-     * Configure each Q.
-     */
-    if ( ixQMgrQConfig( qInfoDes->qName,
-			qInfoDes->qId,
-			qInfoDes->qSize,
-			qInfoDes->qWords) != IX_SUCCESS)
-    {
-	return IX_ETH_ACC_FAIL;
-    }
-
-    if ( ixQMgrWatermarkSet( qInfoDes->qId,
-			     qInfoDes->AlmostEmptyThreshold,
-			     qInfoDes->AlmostFullThreshold
-			     ) != IX_SUCCESS)
-    {
-	return IX_ETH_ACC_FAIL;
-    }
-
-    /*
-     * Set dispatcher priority.
-     */
-    if ( ixQMgrDispatcherPrioritySet( qInfoDes->qId,
-				      IX_ETH_ACC_QM_QUEUE_DISPATCH_PRIORITY)
-	 != IX_SUCCESS)
-    {
-	return IX_ETH_ACC_FAIL;
-    }
-
-    /*
-     * Register callbacks for each Q.
-     */
-    if ( ixQMgrNotificationCallbackSet(qInfoDes->qId,
-				       qInfoDes->qCallback,
-				       qInfoDes->callbackTag)
-	 != IX_SUCCESS )
-    {
-	return IX_ETH_ACC_FAIL;
-    }
-
-    /*
-     * Set notification condition for Q
-     */
-    if (qInfoDes->qNotificationEnableAtStartup == true)
-    {
-	if (   ixQMgrNotificationEnable(qInfoDes->qId,
-					qInfoDes->qConditionSource)
-	       != IX_SUCCESS )
-	{
-	    return IX_ETH_ACC_FAIL;
-	}
-    }
-
-    return(IX_ETH_ACC_SUCCESS);
-}
-
-/**
- * @fn ixEthAccQMgrQueuesConfig(void)
- *
- * @brief Setup all the queues and register all callbacks required
- * by this component to the QMgr
- *
- * The RxFree queues, tx queues, rx queues are configured statically
- *
- * Rx queues configuration is driven by QoS setup.
- * Many Rx queues may be required when QoS is enabled (this depends
- * on IxEthDB setup and the images being downloaded). The configuration
- * of the rxQueues is done in many steps as follows:
- *
- * @li select all Rx queues as configured by ethDB for all ports
- * @li sort the queues by traffic class
- * @li build the priority dependency for all queues
- * @li fill the configuration for all rx queues
- * @li configure all statically configured queues
- * @li configure all dynamically configured queues
- *
- * @param none
- *
- * @return IxEthAccStatus
- *
- * @internal
- */
-IX_ETH_ACC_PUBLIC
-IxEthAccStatus ixEthAccQMgrQueuesConfig(void)
-{
-    struct
-    {
-	int npeCount;
-	UINT32 npeId;
-	IxQMgrQId qId;
-	IxEthDBProperty trafficClass;
-    } rxQueues[IX_ETHACC_MAX_RX_QUEUES];
-
-    UINT32 rxQueue = 0;
-    UINT32 rxQueueCount = 0;
-    IxQMgrQId ixQId =IX_QMGR_MAX_NUM_QUEUES;
-    IxEthDBStatus ixEthDBStatus = IX_ETH_DB_SUCCESS;
-    IxEthDBPortId ixEthDbPortId = 0;
-    IxEthAccPortId ixEthAccPortId = 0;
-    UINT32 ixNpeId = 0;
-    UINT32 ixHighestNpeId = 0;
-    UINT32 sortIterations = 0;
-    IxEthAccStatus ret = IX_ETH_ACC_SUCCESS;
-    IxEthAccQregInfo *qInfoDes = NULL;
-    IxEthDBProperty ixEthDBTrafficClass = IX_ETH_DB_QOS_TRAFFIC_CLASS_0_RX_QUEUE_PROPERTY;
-    IxEthDBPropertyType ixEthDBPropertyType = IX_ETH_DB_INTEGER_PROPERTY;
-    UINT32 ixEthDBParameter = 0;
-    BOOL completelySorted = false;
-
-    /* Fill the corspondance between ports and queues
-     * This defines the mapping from port to queue Ids.
-     */
-
-    ixEthAccPortData[IX_ETH_PORT_1].ixEthAccRxData.rxFreeQueue
-	= IX_ETH_ACC_RX_FREE_BUFF_ENET0_Q;
-    ixEthAccPortData[IX_ETH_PORT_2].ixEthAccRxData.rxFreeQueue
-	= IX_ETH_ACC_RX_FREE_BUFF_ENET1_Q;
-#ifdef __ixp46X
-    ixEthAccPortData[IX_ETH_PORT_3].ixEthAccRxData.rxFreeQueue
-	= IX_ETH_ACC_RX_FREE_BUFF_ENET2_Q;
-#endif
-    ixEthAccPortData[IX_ETH_PORT_1].ixEthAccTxData.txQueue
-	= IX_ETH_ACC_TX_FRAME_ENET0_Q;
-    ixEthAccPortData[IX_ETH_PORT_2].ixEthAccTxData.txQueue
-	= IX_ETH_ACC_TX_FRAME_ENET1_Q;
-#ifdef __ixp46X
-    ixEthAccPortData[IX_ETH_PORT_3].ixEthAccTxData.txQueue
-	= IX_ETH_ACC_TX_FRAME_ENET2_Q;
-#endif
-    /* Fill the corspondance between ports and NPEs
-     * This defines the mapping from port to npeIds.
-     */
-
-    ixEthAccPortData[IX_ETH_PORT_1].npeId = IX_NPEMH_NPEID_NPEB;
-    ixEthAccPortData[IX_ETH_PORT_2].npeId = IX_NPEMH_NPEID_NPEC;
-#ifdef __ixp46X
-    ixEthAccPortData[IX_ETH_PORT_3].npeId = IX_NPEMH_NPEID_NPEA;
-#endif
-    /* set the default rx scheduling discipline */
-    ixEthAccDataInfo.schDiscipline = FIFO_NO_PRIORITY;
-
-    /*
-     * Queue Selection step:
-     *
-     * The following code selects all the queues and build
-     * a temporary array which contains for each queue
-     * - the queue Id,
-     * - the highest traffic class (in case of many
-     * priorities configured for the same queue on different
-     * ports)
-     * - the number of different Npes which are
-     * configured to write to this queue.
-     *
-     * The output of this loop is a temporary array of RX queues
-     * in any order.
-     *
-     */
-#ifdef CONFIG_IXP425_COMPONENT_ETHDB
-    for (ixEthAccPortId = 0;
-	 (ixEthAccPortId < IX_ETH_ACC_NUMBER_OF_PORTS)
-	     && (ret == IX_ETH_ACC_SUCCESS);
-	 ixEthAccPortId++)
-    {
-	/* map between ethDb and ethAcc port Ids */
-	ixEthDbPortId = (IxEthDBPortId)ixEthAccPortId;
-
-	/* map between npeId and ethAcc port Ids */
-	ixNpeId = IX_ETH_ACC_PORT_TO_NPE_ID(ixEthAccPortId);
-
-	/* Iterate thru the different priorities */
-	for (ixEthDBTrafficClass = IX_ETH_DB_QOS_TRAFFIC_CLASS_0_RX_QUEUE_PROPERTY;
-	     ixEthDBTrafficClass <= IX_ETH_DB_QOS_TRAFFIC_CLASS_7_RX_QUEUE_PROPERTY;
-	     ixEthDBTrafficClass++)
-	{
-	    ixEthDBStatus = ixEthDBFeaturePropertyGet(
-	      ixEthDbPortId,
-	      IX_ETH_DB_VLAN_QOS,
-	      ixEthDBTrafficClass,
-	      &ixEthDBPropertyType,
-	      (void *)&ixEthDBParameter);
-
-	    if (ixEthDBStatus == IX_ETH_DB_SUCCESS)
-	    {
-		/* This port and QoS class are mapped to
-		 * a RX queue.
-		 */
-		if (ixEthDBPropertyType == IX_ETH_DB_INTEGER_PROPERTY)
-		{
-		    /* remember the highest npe Id supporting ethernet */
-		    if (ixNpeId > ixHighestNpeId)
-		    {
-			ixHighestNpeId = ixNpeId;
-		    }
-
-		    /* search the queue in the list of queues
-		     * already used by an other port or QoS
-		     */
-		    for (rxQueue = 0;
-			 rxQueue < rxQueueCount;
-			 rxQueue++)
-		    {
-			if (rxQueues[rxQueue].qId == (IxQMgrQId)ixEthDBParameter)
-			{
-			    /* found an existing setup, update the number of ports
-			     * for this queue if the port maps to
-			     * a different NPE.
-			     */
-			    if (rxQueues[rxQueue].npeId != ixNpeId)
-			    {
-				rxQueues[rxQueue].npeCount++;
-				rxQueues[rxQueue].npeId = ixNpeId;
-			    }
-			    /* get the highest traffic class for this queue */
-			    if (rxQueues[rxQueue].trafficClass > ixEthDBTrafficClass)
-			    {
-				rxQueues[rxQueue].trafficClass = ixEthDBTrafficClass;
-			    }
-			    break;
-			}
-		    }
-		    if (rxQueue == rxQueueCount)
-		    {
-			/* new queue not found in the current list,
-			 * add a new entry.
-			 */
-			IX_OSAL_ASSERT(rxQueueCount < IX_ETHACC_MAX_RX_QUEUES);
-			rxQueues[rxQueueCount].qId = ixEthDBParameter;
-			rxQueues[rxQueueCount].npeCount = 1;
-			rxQueues[rxQueueCount].npeId = ixNpeId;
-			rxQueues[rxQueueCount].trafficClass = ixEthDBTrafficClass;
-			rxQueueCount++;
-		    }
-		}
-		else
-		{
-		    /* unexpected property type (not Integer) */
-		    ret = IX_ETH_ACC_FAIL;
-
-                    IX_ETH_ACC_WARNING_LOG("ixEthAccQMgrQueuesConfig: unexpected property type returned by EthDB\n", 0, 0, 0, 0, 0, 0);
-
-		    /* no point to continue to iterate */
-		    break;
-		}
-	    }
-	    else
-	    {
-		/* No Rx queue configured for this port
-		 * and this traffic class. Do nothing.
-		 */
-	    }
-	}
-
-        /* notify EthDB that queue initialization is complete and traffic class allocation is frozen */
-        ixEthDBFeaturePropertySet(ixEthDbPortId,
-            IX_ETH_DB_VLAN_QOS,
-            IX_ETH_DB_QOS_QUEUE_CONFIGURATION_COMPLETE,
-            NULL /* ignored */);
-    }
-
-#else
-
-    ixNpeId = IX_ETH_ACC_PORT_TO_NPE_ID(ixEthAccPortId);
-    rxQueues[0].qId = 4;
-    rxQueues[0].npeCount = 1;
-    rxQueues[0].npeId = ixNpeId;
-    rxQueues[0].trafficClass = IX_ETH_DB_QOS_TRAFFIC_CLASS_0_RX_QUEUE_PROPERTY;
-    rxQueueCount++;
-
-#endif
-
-    /* check there is at least 1 rx queue : there is no point
-     * to continue if there is no rx queue configured
-     */
-    if ((rxQueueCount == 0) || (ret == IX_ETH_ACC_FAIL))
-    {
-        IX_ETH_ACC_WARNING_LOG("ixEthAccQMgrQueuesConfig: no queues configured, bailing out\n", 0, 0, 0, 0, 0, 0);
-	return (IX_ETH_ACC_FAIL);
-    }
-
-    /* Queue sort step:
-     *
-     * Re-order the array of queues by decreasing traffic class
-     * using a bubble sort. (trafficClass 0 is the lowest
-     * priority traffic, trafficClass 7 is the highest priority traffic)
-     *
-     * Primary sort order is traffic class
-     * Secondary sort order is npeId
-     *
-     * Note that a bubble sort algorithm is not very efficient when
-     * the number of queues grows . However, this is not a very bad choice
-     * considering the very small number of entries to sort. Also, bubble
-     * sort is extremely fast when the list is already sorted.
-     *
-     * The output of this loop is a sorted array of queues.
-     *
-     */
-    sortIterations = 0;
-    do
-    {
-	sortIterations++;
-	completelySorted = true;
-	for (rxQueue = 0;
-	     rxQueue < rxQueueCount - sortIterations;
-	     rxQueue++)
-	{
-	    /* compare adjacent elements */
-	    if ((rxQueues[rxQueue].trafficClass <
-		rxQueues[rxQueue+1].trafficClass)
-		|| ((rxQueues[rxQueue].trafficClass ==
-		     rxQueues[rxQueue+1].trafficClass)
-		    &&(rxQueues[rxQueue].npeId <
-		       rxQueues[rxQueue+1].npeId)))
-	    {
-		/* swap adjacent elements */
-		int npeCount = rxQueues[rxQueue].npeCount;
-		UINT32 npeId = rxQueues[rxQueue].npeId;
-		IxQMgrQId qId = rxQueues[rxQueue].qId;
-		IxEthDBProperty trafficClass = rxQueues[rxQueue].trafficClass;
-		rxQueues[rxQueue].npeCount = rxQueues[rxQueue+1].npeCount;
-		rxQueues[rxQueue].npeId = rxQueues[rxQueue+1].npeId;
-		rxQueues[rxQueue].qId = rxQueues[rxQueue+1].qId;
-		rxQueues[rxQueue].trafficClass = rxQueues[rxQueue+1].trafficClass;
-		rxQueues[rxQueue+1].npeCount = npeCount;
-		rxQueues[rxQueue+1].npeId = npeId;
-		rxQueues[rxQueue+1].qId = qId;
-		rxQueues[rxQueue+1].trafficClass = trafficClass;
-		completelySorted = false;
-	    }
-	}
-    }
-    while (!completelySorted);
-
-    /* Queue traffic class list:
-     *
-     * Fill an array of rx queues linked by ascending traffic classes.
-     *
-     * If the queues are configured as follows
-     *   qId 6 -> traffic class 0 (lowest)
-     *   qId 7 -> traffic class 0
-     *   qId 8 -> traffic class 6
-     *   qId 12 -> traffic class 7 (highest)
-     *
-     * Then the output of this loop will be
-     *
-     * higherPriorityQueue[6] = 8
-     * higherPriorityQueue[7] = 8
-     * higherPriorityQueue[8] = 12
-     * higherPriorityQueue[12] = Invalid queueId
-     * higherPriorityQueue[...] = Invalid queueId
-     *
-     * Note that this queue ordering does not handle all possibilities
-     * that could result from different rules associated with different
-     * ports, and inconsistencies in the rules. In all cases, the
-     * output of this  algorithm is a simple linked list of queues,
-     * without closed circuit.
-
-     * This list is implemented as an array with invalid values initialized
-     * with an "invalid" queue id which is the maximum number of queues.
-     *
-     */
-
-    /*
-     * Initialise the rx queue list.
-     */
-    for (rxQueue = 0; rxQueue < IX_QMGR_MAX_NUM_QUEUES; rxQueue++)
-    {
-	ixEthAccDataInfo.higherPriorityQueue[rxQueue] = IX_QMGR_MAX_NUM_QUEUES;
-    }
-
-    /* build the linked list for this NPE.
-     */
-    for (ixNpeId = 0;
-	 ixNpeId <= ixHighestNpeId;
-	 ixNpeId++)
-    {
-	/* iterate thru the sorted list of queues
-	 */
-	ixQId = IX_QMGR_MAX_NUM_QUEUES;
-	for (rxQueue = 0;
-	     rxQueue < rxQueueCount;
-	     rxQueue++)
-	{
-	    if (rxQueues[rxQueue].npeId == ixNpeId)
-	    {
-		ixEthAccDataInfo.higherPriorityQueue[rxQueues[rxQueue].qId] = ixQId;
-		/* iterate thru queues with the same traffic class
-		 * than the current queue. (queues are ordered by descending
-		 * traffic classes and npeIds).
-		 */
-		while ((rxQueue < rxQueueCount - 1)
-		       && (rxQueues[rxQueue].trafficClass
-			   == rxQueues[rxQueue+1].trafficClass)
-		       && (ixNpeId == rxQueues[rxQueue].npeId))
-		{
-		    rxQueue++;
-		    ixEthAccDataInfo.higherPriorityQueue[rxQueues[rxQueue].qId] = ixQId;
-		}
-		ixQId = rxQueues[rxQueue].qId;
-	    }
-	}
-    }
-
-    /* point on the first dynamic queue description */
-    qInfoDes = ixEthAccQmgrRxQueuesInfo;
-
-    /* update the list of queues with the rx queues */
-    for (rxQueue = 0;
-	 (rxQueue < rxQueueCount) && (ret == IX_ETH_ACC_SUCCESS);
-	 rxQueue++)
-    {
-	/* Don't utilize more than IX_ETHACC_MAX_LARGE_RX_QUEUES queues
-	 * with the full 128 entries.  For the lower priority queues, use
-	 * a smaller number of entries.  This ensures queue resources
-	 * remain available for other components.
-	 */
-	if( (rxQueueCount > IX_ETHACC_MAX_LARGE_RX_QUEUES) &&
-	    (rxQueue < rxQueueCount - IX_ETHACC_MAX_LARGE_RX_QUEUES) )
-	{
-	    /* add the small RX Queue setup template to the list of queues */
-	    memcpy(qInfoDes, &ixEthAccQmgrRxSmallTemplate, sizeof(*qInfoDes));
-	} else {
-	    /* add the default RX Queue setup template to the list of queues */
-	    memcpy(qInfoDes, &ixEthAccQmgrRxDefaultTemplate, sizeof(*qInfoDes));
-	}
-
-	/* setup the RxQueue ID */
-	qInfoDes->qId = rxQueues[rxQueue].qId;
-
-	/* setup the RxQueue watermark level
-	 *
-	 * Each queue can be filled by many NPEs. To avoid the
-	 * NPEs to write to a full queue, need to set the
-	 * high watermark level for nearly full condition.
-	 * (the high watermark level are a power of 2
-	 * starting from the top of the queue)
-	 *
-	 * Number of     watermark
-         *   ports        level
-         *    1             0
-	 *    2             1
-	 *    3             2
-	 *    4             4
-	 *    5             4
-	 *    6             8
-	 *    n          approx. 2**ceil(log2(n))
-	 */
-	if (rxQueues[rxQueue].npeCount == 1)
-	{
-	    qInfoDes->AlmostFullThreshold = IX_QMGR_Q_WM_LEVEL0;
-	}
-	else if (rxQueues[rxQueue].npeCount == 2)
-	{
-	    qInfoDes->AlmostFullThreshold = IX_QMGR_Q_WM_LEVEL1;
-	}
-	else if (rxQueues[rxQueue].npeCount == 3)
-	{
-	    qInfoDes->AlmostFullThreshold = IX_QMGR_Q_WM_LEVEL2;
-	}
-	else
-	{
-	    /* reach the maximum number for CSR 2.0 */
-            IX_ETH_ACC_WARNING_LOG("ixEthAccQMgrQueuesConfig: maximum number of NPEs per queue reached, bailing out\n", 0, 0, 0, 0, 0, 0);
-	    ret = IX_ETH_ACC_FAIL;
-	    break;
-	}
-
-	/* move to next queue entry */
-	++qInfoDes;
-    }
-
-    /* configure the static list (RxFree, Tx and TxDone queues) */
-    for (qInfoDes = ixEthAccQmgrStaticInfo;
-	 (qInfoDes->qCallback != (IxQMgrCallback) NULL )
-	     && (ret == IX_ETH_ACC_SUCCESS);
-	 ++qInfoDes)
-    {
-	ret = ixEthAccQMgrQueueSetup(qInfoDes);
-    }
-
-    /* configure the dynamic list (Rx queues) */
-    for (qInfoDes = ixEthAccQmgrRxQueuesInfo;
-	 (qInfoDes->qCallback != (IxQMgrCallback) NULL )
-	     && (ret == IX_ETH_ACC_SUCCESS);
-	 ++qInfoDes)
-    {
-	ret = ixEthAccQMgrQueueSetup(qInfoDes);
-    }
-
-    return(ret);
-}
-
-/**
- * @fn ixEthAccQMgrRxQEntryGet(UINT32 *rxQueueEntries)
- *
- * @brief Add and return the total number of entries in all Rx queues
- *
- * @param UINT32 rxQueueEntries[in] number of entries in all queues
- *
- * @return void
- *
- * @note Rx queues configuration is driven by Qos Setup. There is a
- * variable number of rx queues which are set at initialisation.
- *
- * @internal
- */
-IX_ETH_ACC_PUBLIC
-void ixEthAccQMgrRxQEntryGet(UINT32 *numRxQueueEntries)
-{
-    UINT32 rxQueueLevel;
-    IxEthAccQregInfo *qInfoDes;;
-
-    *numRxQueueEntries = 0;
-
-    /* iterate thru rx queues */
-    for (qInfoDes = ixEthAccQmgrRxQueuesInfo;
-	 qInfoDes->qCallback != (IxQMgrCallback)NULL;
-	 ++qInfoDes)
-    {
-	/* retrieve the rx queue level */
-	rxQueueLevel = 0;
-	ixQMgrQNumEntriesGet(qInfoDes->qId, &rxQueueLevel);
-	(*numRxQueueEntries) += rxQueueLevel;
-    }
-}
-
-/**
- * @fn ixEthAccQMgrRxCallbacksRegister(IxQMgrCallback ixQMgrCallback)
- *
- * @brief Change the callback registered to all rx queues.
- *
- * @param IxQMgrCallback ixQMgrCallback[in] QMgr callback to register
- *
- * @return IxEthAccStatus
- *
- * @note The user may decide to use different Rx mechanisms
- * (e.g. receive many frames at the same time , or receive
- *  one frame at a time, depending on the overall application
- *  performances). A different QMgr callback is registered. This
- *  way, there is no excessive pointer checks in the datapath.
- *
- * @internal
- */
-IX_ETH_ACC_PUBLIC
-IxEthAccStatus ixEthAccQMgrRxCallbacksRegister(IxQMgrCallback ixQMgrCallback)
-{
-    IxEthAccQregInfo *qInfoDes;
-    IxEthAccStatus ret = IX_ETH_ACC_SUCCESS;
-
-    /* parameter check */
-    if (NULL == ixQMgrCallback)
-    {
-	ret = IX_ETH_ACC_FAIL;
-    }
-
-    /* iterate thru rx queues */
-    for (qInfoDes = ixEthAccQmgrRxQueuesInfo;
-	 (qInfoDes->qCallback != (IxQMgrCallback) NULL )
-	     && (ret == IX_ETH_ACC_SUCCESS);
-	 ++qInfoDes)
-    {
-	/* register the rx callback for all queues */
-	if (ixQMgrNotificationCallbackSet(qInfoDes->qId,
-					     ixQMgrCallback,
-					     qInfoDes->callbackTag
-					     ) != IX_SUCCESS)
-	{
-	    ret = IX_ETH_ACC_FAIL;
-	}
-    }
-    return(ret);
-}
-
-/**
- * @fn ixEthAccSingleEthNpeCheck(IxEthAccPortId portId)
- *
- * @brief Check the npe exists for this port
- *
- * @param IxEthAccPortId portId[in] port
- *
- * @return IxEthAccStatus
- *
- * @internal
- */
-IX_ETH_ACC_PUBLIC
-IxEthAccStatus ixEthAccSingleEthNpeCheck(IxEthAccPortId portId)
-{
-
-    /* If not IXP42X A0 stepping, proceed to check for existence of coprocessors */
-    if ((IX_FEATURE_CTRL_SILICON_TYPE_A0 !=
-        (ixFeatureCtrlProductIdRead() & IX_FEATURE_CTRL_SILICON_STEPPING_MASK))
-        || (IX_FEATURE_CTRL_DEVICE_TYPE_IXP42X != ixFeatureCtrlDeviceRead ()))
-      {
-            if ((IX_ETH_PORT_1 == portId) &&
-                (ixFeatureCtrlComponentCheck(IX_FEATURECTRL_ETH0) ==
-                 IX_FEATURE_CTRL_COMPONENT_ENABLED))
-            {
-                return IX_ETH_ACC_SUCCESS;
-            }
-
-            if ((IX_ETH_PORT_2 == portId) &&
-                (ixFeatureCtrlComponentCheck(IX_FEATURECTRL_ETH1) ==
-                 IX_FEATURE_CTRL_COMPONENT_ENABLED))
-            {
-                return IX_ETH_ACC_SUCCESS;
-            }
-
-            if ((IX_ETH_PORT_3 == portId) &&
-                (ixFeatureCtrlComponentCheck(IX_FEATURECTRL_NPEA_ETH) ==
-                 IX_FEATURE_CTRL_COMPONENT_ENABLED))
-            {
-                return IX_ETH_ACC_SUCCESS;
-            }
-
-            return IX_ETH_ACC_FAIL;
-      }
-
-    return IX_ETH_ACC_SUCCESS;
-}
-
-/**
- * @fn ixEthAccStatsShow(void)
- *
- * @brief Displays all EthAcc stats
- *
- * @return void
- *
- */
-void ixEthAccStatsShow(IxEthAccPortId portId)
-{
-    ixEthAccMdioShow();
-
-    printf("\nPort %u\nUnicast MAC : ", portId);
-    ixEthAccPortUnicastAddressShow(portId);
-    ixEthAccPortMulticastAddressShow(portId);
-    printf("\n");
-
-    ixEthAccDataPlaneShow();
-}
-
-
-
diff --git a/drivers/net/npe/IxEthAccControlInterface.c b/drivers/net/npe/IxEthAccControlInterface.c
deleted file mode 100644
index dbe32e133c..0000000000
--- a/drivers/net/npe/IxEthAccControlInterface.c
+++ /dev/null
@@ -1,509 +0,0 @@
-/**
- * @file IxEthAccControlInterface.c
- *
- * @author Intel Corporation
- * @date 
- *
- * @brief IX_ETH_ACC_PUBLIC wrappers for control plane functions
- *
- * Design Notes:
- *
- * @par
- * IXP400 SW Release version 2.0
- * 
- * -- Copyright Notice --
- * 
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- * 
- * @par
- * SPDX-License-Identifier:	BSD-3-Clause
- * @par
- * -- End of Copyright Notice --
- */
-
-#include "IxOsal.h"
-#include "IxEthAcc.h"
-#include "IxEthAcc_p.h"
-
-PUBLIC IxOsalMutex ixEthAccControlInterfaceMutex;
-
-IX_ETH_ACC_PUBLIC IxEthAccStatus
-ixEthAccPortEnable(IxEthAccPortId portId)
-{
-    IxEthAccStatus result;
-
-    if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED())
-    {
-        printf("EthAcc: (Mac) cannot enable port %d, service not initialized\n", portId);
-	return (IX_ETH_ACC_FAIL);
-    }
-
-    ixOsalMutexLock(&ixEthAccControlInterfaceMutex, IX_OSAL_WAIT_FOREVER);
-    result = ixEthAccPortEnablePriv(portId);
-    ixOsalMutexUnlock(&ixEthAccControlInterfaceMutex);
-    return result;
-}
-
-IX_ETH_ACC_PUBLIC IxEthAccStatus 
-ixEthAccPortDisable(IxEthAccPortId portId)
-{
-    IxEthAccStatus result;
-
-    /* check the context is iinitialized */
-    if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED())
-    {
-	return (IX_ETH_ACC_FAIL);
-    }
-
-    ixOsalMutexLock(&ixEthAccControlInterfaceMutex, IX_OSAL_WAIT_FOREVER);
-    result = ixEthAccPortDisablePriv(portId);
-    ixOsalMutexUnlock(&ixEthAccControlInterfaceMutex);
-    return result;
-}
-
-IX_ETH_ACC_PUBLIC IxEthAccStatus
-ixEthAccPortEnabledQuery(IxEthAccPortId portId, BOOL *enabled)
-{
-    IxEthAccStatus result;
-
-    if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED())
-    {
-	return (IX_ETH_ACC_FAIL);
-    }
-
-    ixOsalMutexLock(&ixEthAccControlInterfaceMutex, IX_OSAL_WAIT_FOREVER);
-    result = ixEthAccPortEnabledQueryPriv(portId, enabled);
-    ixOsalMutexUnlock(&ixEthAccControlInterfaceMutex);
-    return result;
-}
-
-IX_ETH_ACC_PUBLIC IxEthAccStatus 
-ixEthAccPortPromiscuousModeClear(IxEthAccPortId portId)
-{
-    IxEthAccStatus result;
-
-    if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED())
-    {
-	return (IX_ETH_ACC_FAIL);
-    }
-
-    ixOsalMutexLock(&ixEthAccControlInterfaceMutex, IX_OSAL_WAIT_FOREVER);
-    result = ixEthAccPortPromiscuousModeClearPriv(portId);
-    ixOsalMutexUnlock(&ixEthAccControlInterfaceMutex);
-    return result;
-}
-
-IX_ETH_ACC_PUBLIC IxEthAccStatus 
-ixEthAccPortPromiscuousModeSet(IxEthAccPortId portId)
-{
-    IxEthAccStatus result;
-
-    if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED())
-    {
-	return (IX_ETH_ACC_FAIL);
-    }
-
-    ixOsalMutexLock(&ixEthAccControlInterfaceMutex, IX_OSAL_WAIT_FOREVER);
-    result = ixEthAccPortPromiscuousModeSetPriv(portId);
-    ixOsalMutexUnlock(&ixEthAccControlInterfaceMutex);
-    return result;
-}
-
-IX_ETH_ACC_PUBLIC IxEthAccStatus 
-ixEthAccPortUnicastMacAddressSet(IxEthAccPortId portId, IxEthAccMacAddr *macAddr)
-{
-    IxEthAccStatus result;
-
-    if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED())
-    {
-	return (IX_ETH_ACC_FAIL);
-    }
-
-    ixOsalMutexLock(&ixEthAccControlInterfaceMutex, IX_OSAL_WAIT_FOREVER);
-    result = ixEthAccPortUnicastMacAddressSetPriv(portId, macAddr);
-    ixOsalMutexUnlock(&ixEthAccControlInterfaceMutex);
-    return result;
-}
-
-IX_ETH_ACC_PUBLIC IxEthAccStatus
-ixEthAccPortUnicastMacAddressGet(IxEthAccPortId portId, IxEthAccMacAddr *macAddr)
-{
-    IxEthAccStatus result;
-
-    if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED())
-    {
-	return (IX_ETH_ACC_FAIL);
-    }
-
-    ixOsalMutexLock(&ixEthAccControlInterfaceMutex, IX_OSAL_WAIT_FOREVER);
-    result = ixEthAccPortUnicastMacAddressGetPriv(portId, macAddr);
-    ixOsalMutexUnlock(&ixEthAccControlInterfaceMutex);
-    return result;
-}
-
-IX_ETH_ACC_PUBLIC IxEthAccStatus
-ixEthAccPortMulticastAddressJoin(IxEthAccPortId portId, IxEthAccMacAddr *macAddr)
-{
-    IxEthAccStatus result;
-
-    if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED())
-    {
-	return (IX_ETH_ACC_FAIL);
-    }
-
-    ixOsalMutexLock(&ixEthAccControlInterfaceMutex, IX_OSAL_WAIT_FOREVER);
-    result = ixEthAccPortMulticastAddressJoinPriv(portId, macAddr);
-    ixOsalMutexUnlock(&ixEthAccControlInterfaceMutex);
-    return result;
-}
-
-IX_ETH_ACC_PUBLIC IxEthAccStatus
-ixEthAccPortMulticastAddressJoinAll(IxEthAccPortId portId)
-{
-    IxEthAccStatus result;
-
-    if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED())
-    {
-	return (IX_ETH_ACC_FAIL);
-    }
-
-    ixOsalMutexLock(&ixEthAccControlInterfaceMutex, IX_OSAL_WAIT_FOREVER);
-    result = ixEthAccPortMulticastAddressJoinAllPriv(portId);
-    ixOsalMutexUnlock(&ixEthAccControlInterfaceMutex);
-    return result;
-}
-
-IX_ETH_ACC_PUBLIC IxEthAccStatus
-ixEthAccPortMulticastAddressLeave(IxEthAccPortId portId, IxEthAccMacAddr *macAddr)
-{
-    IxEthAccStatus result;
-
-    if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED())
-    {
-	return (IX_ETH_ACC_FAIL);
-    }
-
-    ixOsalMutexLock(&ixEthAccControlInterfaceMutex, IX_OSAL_WAIT_FOREVER);
-    result = ixEthAccPortMulticastAddressLeavePriv(portId, macAddr);
-    ixOsalMutexUnlock(&ixEthAccControlInterfaceMutex);
-    return result;
-}
-
-IX_ETH_ACC_PUBLIC IxEthAccStatus
-ixEthAccPortMulticastAddressLeaveAll(IxEthAccPortId portId)
-{
-    IxEthAccStatus result;
-
-    if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED())
-    {
-	return (IX_ETH_ACC_FAIL);
-    }
-
-    ixOsalMutexLock(&ixEthAccControlInterfaceMutex, IX_OSAL_WAIT_FOREVER);
-    result = ixEthAccPortMulticastAddressLeaveAllPriv(portId);
-    ixOsalMutexUnlock(&ixEthAccControlInterfaceMutex);
-    return result;
-}
-
-IX_ETH_ACC_PUBLIC IxEthAccStatus 
-ixEthAccPortUnicastAddressShow(IxEthAccPortId portId)
-{
-    IxEthAccStatus result;
- 
-    if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED())
-    {
-	return (IX_ETH_ACC_FAIL);
-    }
-
-    ixOsalMutexLock(&ixEthAccControlInterfaceMutex, IX_OSAL_WAIT_FOREVER);
-    result = ixEthAccPortUnicastAddressShowPriv(portId);
-    ixOsalMutexUnlock(&ixEthAccControlInterfaceMutex);
-    return result;
-}
-
-IX_ETH_ACC_PUBLIC void 
-ixEthAccPortMulticastAddressShow(IxEthAccPortId portId)
-{
-    if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED())
-    {
-	return;
-    }
-
-    ixOsalMutexLock(&ixEthAccControlInterfaceMutex, IX_OSAL_WAIT_FOREVER);
-    ixEthAccPortMulticastAddressShowPriv(portId);
-    ixOsalMutexUnlock(&ixEthAccControlInterfaceMutex);
-}
-
-IX_ETH_ACC_PUBLIC IxEthAccStatus 
-ixEthAccPortDuplexModeSet(IxEthAccPortId portId, IxEthAccDuplexMode mode)
-{
-    IxEthAccStatus result;
-
-    if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED())
-    {
-	return (IX_ETH_ACC_FAIL);
-    }
-
-    ixOsalMutexLock(&ixEthAccControlInterfaceMutex, IX_OSAL_WAIT_FOREVER);
-    result = ixEthAccPortDuplexModeSetPriv(portId, mode);
-    ixOsalMutexUnlock(&ixEthAccControlInterfaceMutex);
-    return result;
-}
-
-IX_ETH_ACC_PUBLIC IxEthAccStatus 
-ixEthAccPortDuplexModeGet(IxEthAccPortId portId, IxEthAccDuplexMode *mode)
-{
-    IxEthAccStatus result;
-
-    if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED())
-    {
-	return (IX_ETH_ACC_FAIL);
-    }
-
-    ixOsalMutexLock(&ixEthAccControlInterfaceMutex, IX_OSAL_WAIT_FOREVER);
-    result = ixEthAccPortDuplexModeGetPriv(portId, mode);
-    ixOsalMutexUnlock(&ixEthAccControlInterfaceMutex);
-    return result;
-}
-
-IX_ETH_ACC_PUBLIC IxEthAccStatus
-ixEthAccPortTxFrameAppendPaddingEnable(IxEthAccPortId portId)
-{
-    IxEthAccStatus result;
-     
-    if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED())
-    {
-	return (IX_ETH_ACC_FAIL);
-    }
-
-    ixOsalMutexLock(&ixEthAccControlInterfaceMutex, IX_OSAL_WAIT_FOREVER);
-    result = ixEthAccPortTxFrameAppendPaddingEnablePriv(portId);
-    ixOsalMutexUnlock(&ixEthAccControlInterfaceMutex);
-    return result;
-}
-
-IX_ETH_ACC_PUBLIC IxEthAccStatus
-ixEthAccPortTxFrameAppendPaddingDisable(IxEthAccPortId portId)
-{
-    IxEthAccStatus result;
-
-    if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED())
-    {
-	return (IX_ETH_ACC_FAIL);
-    }
-
-    ixOsalMutexLock(&ixEthAccControlInterfaceMutex, IX_OSAL_WAIT_FOREVER);
-    result = ixEthAccPortTxFrameAppendPaddingDisablePriv(portId);
-    ixOsalMutexUnlock(&ixEthAccControlInterfaceMutex);
-    return result;
-}
-
-IX_ETH_ACC_PUBLIC IxEthAccStatus
-ixEthAccPortTxFrameAppendFCSEnable(IxEthAccPortId portId)
-{
-    IxEthAccStatus result;
-
-    if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED())
-    {
-	return (IX_ETH_ACC_FAIL);
-    }
-
-    ixOsalMutexLock(&ixEthAccControlInterfaceMutex, IX_OSAL_WAIT_FOREVER);
-    result = ixEthAccPortTxFrameAppendFCSEnablePriv(portId);
-    ixOsalMutexUnlock(&ixEthAccControlInterfaceMutex);
-    return result;
-}
-
-IX_ETH_ACC_PUBLIC IxEthAccStatus
-ixEthAccPortTxFrameAppendFCSDisable(IxEthAccPortId portId)
-{
-    IxEthAccStatus result;
-
-    if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED())
-    {
-	return (IX_ETH_ACC_FAIL);
-    }
-
-    ixOsalMutexLock(&ixEthAccControlInterfaceMutex, IX_OSAL_WAIT_FOREVER);
-    result = ixEthAccPortTxFrameAppendFCSDisablePriv(portId);
-    ixOsalMutexUnlock(&ixEthAccControlInterfaceMutex);
-    return result;
-}
-
-IX_ETH_ACC_PUBLIC IxEthAccStatus
-ixEthAccPortRxFrameAppendFCSEnable(IxEthAccPortId portId)
-{
-    IxEthAccStatus result;
-
-    if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED())
-    {
-	return (IX_ETH_ACC_FAIL);
-    }
-
-    ixOsalMutexLock(&ixEthAccControlInterfaceMutex, IX_OSAL_WAIT_FOREVER);
-    result = ixEthAccPortRxFrameAppendFCSEnablePriv(portId);
-    ixOsalMutexUnlock(&ixEthAccControlInterfaceMutex);
-    return result;
-}
-
-IX_ETH_ACC_PUBLIC IxEthAccStatus
-ixEthAccPortRxFrameAppendFCSDisable(IxEthAccPortId portId)
-{
-    IxEthAccStatus result;
-
-    if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED())
-    {
-	return (IX_ETH_ACC_FAIL);
-    }
-
-    ixOsalMutexLock(&ixEthAccControlInterfaceMutex, IX_OSAL_WAIT_FOREVER);
-    result = ixEthAccPortRxFrameAppendFCSDisablePriv(portId);
-    ixOsalMutexUnlock(&ixEthAccControlInterfaceMutex);
-    return result;
-}
-
-IX_ETH_ACC_PUBLIC IxEthAccStatus
-ixEthAccTxSchedulingDisciplineSet(IxEthAccPortId portId, IxEthAccSchedulerDiscipline sched)
-{
-    IxEthAccStatus result;
-
-    if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED())
-    {
-	return (IX_ETH_ACC_FAIL);
-    }
-
-    ixOsalMutexLock(&ixEthAccControlInterfaceMutex, IX_OSAL_WAIT_FOREVER);
-    result = ixEthAccTxSchedulingDisciplineSetPriv(portId, sched);
-    ixOsalMutexUnlock(&ixEthAccControlInterfaceMutex);
-    return result;
-}
-
-IX_ETH_ACC_PUBLIC IxEthAccStatus
-ixEthAccRxSchedulingDisciplineSet(IxEthAccSchedulerDiscipline sched)
-{
-    IxEthAccStatus result;
-
-    if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED())
-    {
-	return (IX_ETH_ACC_FAIL);
-    }
-
-    ixOsalMutexLock(&ixEthAccControlInterfaceMutex, IX_OSAL_WAIT_FOREVER);
-    result = ixEthAccRxSchedulingDisciplineSetPriv(sched);
-    ixOsalMutexUnlock(&ixEthAccControlInterfaceMutex);
-    return result;
-}
-
-IX_ETH_ACC_PUBLIC IxEthAccStatus 
-ixEthAccPortNpeLoopbackEnable(IxEthAccPortId portId)
-{
-    IxEthAccStatus result;
-
-    if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED())
-    {
-	return (IX_ETH_ACC_FAIL);
-    }
-
-    ixOsalMutexLock(&ixEthAccControlInterfaceMutex, IX_OSAL_WAIT_FOREVER);
-    result = ixEthAccNpeLoopbackEnablePriv(portId);
-    ixOsalMutexUnlock(&ixEthAccControlInterfaceMutex);
-    return result;
-}
-
-IX_ETH_ACC_PUBLIC IxEthAccStatus 
-ixEthAccPortTxEnable(IxEthAccPortId portId)
-{
-    IxEthAccStatus result;
-
-    if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED())
-    {
-	return (IX_ETH_ACC_FAIL);
-    }
-
-    ixOsalMutexLock(&ixEthAccControlInterfaceMutex, IX_OSAL_WAIT_FOREVER);
-    result = ixEthAccPortTxEnablePriv(portId);
-    ixOsalMutexUnlock(&ixEthAccControlInterfaceMutex);
-    return result;
-}
-
-IX_ETH_ACC_PUBLIC IxEthAccStatus 
-ixEthAccPortRxEnable(IxEthAccPortId portId)
-{
-    IxEthAccStatus result;
-
-    if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED())
-    {
-	return (IX_ETH_ACC_FAIL);
-    }
-
-    ixOsalMutexLock(&ixEthAccControlInterfaceMutex, IX_OSAL_WAIT_FOREVER);
-    result = ixEthAccPortRxEnablePriv(portId);
-    ixOsalMutexUnlock(&ixEthAccControlInterfaceMutex);
-    return result;
-}
-
-IX_ETH_ACC_PUBLIC IxEthAccStatus 
-ixEthAccPortNpeLoopbackDisable(IxEthAccPortId portId)
-{
-    IxEthAccStatus result;
-
-    if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED())
-    {
-	return (IX_ETH_ACC_FAIL);
-    }
-
-    ixOsalMutexLock(&ixEthAccControlInterfaceMutex, IX_OSAL_WAIT_FOREVER);
-    result = ixEthAccNpeLoopbackDisablePriv(portId);
-    ixOsalMutexUnlock(&ixEthAccControlInterfaceMutex);
-    return result;
-}
-
-IX_ETH_ACC_PUBLIC IxEthAccStatus 
-ixEthAccPortTxDisable(IxEthAccPortId portId)
-{
-    IxEthAccStatus result;
-
-    if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED())
-    {
-	return (IX_ETH_ACC_FAIL);
-    }
-
-    ixOsalMutexLock(&ixEthAccControlInterfaceMutex, IX_OSAL_WAIT_FOREVER);
-    result = ixEthAccPortTxDisablePriv(portId);
-    ixOsalMutexUnlock(&ixEthAccControlInterfaceMutex);
-    return result;
-}
-
-IX_ETH_ACC_PUBLIC IxEthAccStatus 
-ixEthAccPortRxDisable(IxEthAccPortId portId)
-{
-    IxEthAccStatus result;
-
-    if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED())
-    {
-	return (IX_ETH_ACC_FAIL);
-    }
-
-    ixOsalMutexLock(&ixEthAccControlInterfaceMutex, IX_OSAL_WAIT_FOREVER);
-    result = ixEthAccPortRxDisablePriv(portId);
-    ixOsalMutexUnlock(&ixEthAccControlInterfaceMutex);
-    return result;
-}
-
-IX_ETH_ACC_PUBLIC IxEthAccStatus 
-ixEthAccPortMacReset(IxEthAccPortId portId)
-{
-    IxEthAccStatus result;
-
-    if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED())
-    {
-	return (IX_ETH_ACC_FAIL);
-    }
-
-    ixOsalMutexLock(&ixEthAccControlInterfaceMutex, IX_OSAL_WAIT_FOREVER);
-    result = ixEthAccPortMacResetPriv(portId);
-    ixOsalMutexUnlock(&ixEthAccControlInterfaceMutex);
-    return result;
-}
diff --git a/drivers/net/npe/IxEthAccDataPlane.c b/drivers/net/npe/IxEthAccDataPlane.c
deleted file mode 100644
index c0b82d99b7..0000000000
--- a/drivers/net/npe/IxEthAccDataPlane.c
+++ /dev/null
@@ -1,2459 +0,0 @@
-/**
- * @file IxEthDataPlane.c
- *
- * @author Intel Corporation
- * @date 12-Feb-2002
- *
- * @brief This file contains the implementation of the IXPxxx
- * Ethernet Access Data plane component
- *
- * Design Notes:
- *
- * @par
- * IXP400 SW Release version 2.0
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * SPDX-License-Identifier:	BSD-3-Clause
- * @par
- * -- End of Copyright Notice --
- */
-
-#include "IxNpeMh.h"
-#include "IxEthAcc.h"
-#include "IxEthDB.h"
-#include "IxOsal.h"
-#include "IxEthDBPortDefs.h"
-#include "IxFeatureCtrl.h"
-#include "IxEthAcc_p.h"
-#include "IxEthAccQueueAssign_p.h"
-
-extern PUBLIC IxEthAccMacState ixEthAccMacState[];
-extern PUBLIC UINT32 ixEthAccNewSrcMask;
-
-/**
- * private functions prototype
- */
-PRIVATE IX_OSAL_MBUF *
-ixEthAccEntryFromQConvert(UINT32 qEntry, UINT32 mask);
-
-PRIVATE UINT32
-ixEthAccMbufRxQPrepare(IX_OSAL_MBUF *mbuf);
-
-PRIVATE UINT32
-ixEthAccMbufTxQPrepare(IX_OSAL_MBUF *mbuf);
-
-PRIVATE IxEthAccStatus
-ixEthAccTxSwQHighestPriorityGet(IxEthAccPortId portId,
-				IxEthAccTxPriority *priorityPtr);
-
-PRIVATE IxEthAccStatus
-ixEthAccTxFromSwQ(IxEthAccPortId portId,
-		  IxEthAccTxPriority priority);
-
-PRIVATE IxEthAccStatus
-ixEthAccRxFreeFromSwQ(IxEthAccPortId portId);
-
-PRIVATE void
-ixEthAccMbufFromTxQ(IX_OSAL_MBUF *mbuf);
-
-PRIVATE void
-ixEthAccMbufFromRxQ(IX_OSAL_MBUF *mbuf);
-
-PRIVATE IX_STATUS
-ixEthAccQmgrLockTxWrite(IxEthAccPortId portId,
-			UINT32 qBuffer);
-
-PRIVATE IX_STATUS
-ixEthAccQmgrLockRxWrite(IxEthAccPortId portId,
-			UINT32 qBuffer);
-
-PRIVATE IX_STATUS
-ixEthAccQmgrTxWrite(IxEthAccPortId portId,
-		    UINT32 qBuffer,
-		    UINT32 priority);
-
-/**
- * @addtogroup IxEthAccPri
- *@{
- */
-
-/* increment a counter only when stats are enabled */
-#define TX_STATS_INC(port,field) \
-        IX_ETH_ACC_STATS_INC(ixEthAccPortData[port].ixEthAccTxData.stats.field)
-#define RX_STATS_INC(port,field) \
-        IX_ETH_ACC_STATS_INC(ixEthAccPortData[port].ixEthAccRxData.stats.field)
-
-/* always increment the counter (mainly used for unexpected errors) */
-#define TX_INC(port,field) \
-        ixEthAccPortData[port].ixEthAccTxData.stats.field++
-#define RX_INC(port,field) \
-        ixEthAccPortData[port].ixEthAccRxData.stats.field++
-
-PRIVATE IxEthAccDataPlaneStats     ixEthAccDataStats;
-
-extern IxEthAccPortDataInfo   ixEthAccPortData[];
-extern IxEthAccInfo   ixEthAccDataInfo;
-
-PRIVATE IxOsalFastMutex txWriteMutex[IX_ETH_ACC_NUMBER_OF_PORTS];
-PRIVATE IxOsalFastMutex rxWriteMutex[IX_ETH_ACC_NUMBER_OF_PORTS];
-
-/**
- *
- * @brief Mbuf header conversion macros : they implement the
- *  different conversions using a temporary value. They also double-check
- *  that the parameters can be converted to/from NPE format.
- *
- */
-#if defined(__wince) && !defined(IN_KERNEL)
-#define PTR_VIRT2NPE(ptrSrc,dst) \
-  do { UINT32 temp; \
-      IX_OSAL_ENSURE(sizeof(ptrSrc) == sizeof(UINT32), "Wrong parameter type"); \
-      IX_OSAL_ENSURE(sizeof(dst) == sizeof(UINT32), "Wrong parameter type"); \
-      temp = (UINT32)IX_OSAL_MBUF_MBUF_VIRTUAL_TO_PHYSICAL_TRANSLATION((IX_OSAL_MBUF*)ptrSrc); \
-      (dst) = IX_OSAL_SWAP_BE_SHARED_LONG(temp); } \
-  while(0)
-
-#define PTR_NPE2VIRT(type,src,ptrDst) \
-  do { void *temp; \
-      IX_OSAL_ENSURE(sizeof(type) == sizeof(UINT32), "Wrong parameter type"); \
-      IX_OSAL_ENSURE(sizeof(src) == sizeof(UINT32), "Wrong parameter type"); \
-      IX_OSAL_ENSURE(sizeof(ptrDst) == sizeof(UINT32), "Wrong parameter type"); \
-      temp = (void *)IX_OSAL_SWAP_BE_SHARED_LONG(src); \
-      (ptrDst) = (type)IX_OSAL_MBUF_MBUF_PHYSICAL_TO_VIRTUAL_TRANSLATION(temp); } \
-  while(0)
-#else
-#define PTR_VIRT2NPE(ptrSrc,dst) \
-  do { UINT32 temp; \
-      IX_OSAL_ENSURE(sizeof(ptrSrc) == sizeof(UINT32), "Wrong parameter type"); \
-      IX_OSAL_ENSURE(sizeof(dst) == sizeof(UINT32), "Wrong parameter type"); \
-      temp = (UINT32)IX_OSAL_MMU_VIRT_TO_PHYS(ptrSrc); \
-      (dst) = IX_OSAL_SWAP_BE_SHARED_LONG(temp); } \
-  while(0)
-
-#define PTR_NPE2VIRT(type,src,ptrDst) \
-  do { void *temp; \
-      IX_OSAL_ENSURE(sizeof(type) == sizeof(UINT32), "Wrong parameter type"); \
-      IX_OSAL_ENSURE(sizeof(src) == sizeof(UINT32), "Wrong parameter type"); \
-      IX_OSAL_ENSURE(sizeof(ptrDst) == sizeof(UINT32), "Wrong parameter type"); \
-      temp = (void *)IX_OSAL_SWAP_BE_SHARED_LONG(src); \
-      (ptrDst) = (type)IX_OSAL_MMU_PHYS_TO_VIRT(temp); } \
-  while(0)
-#endif
-
-/**
- *
- * @brief Mbuf payload pointer conversion macros : Wince has its own
- *  method to convert the buffer pointers
- */
-#if defined(__wince) && !defined(IN_KERNEL)
-#define DATAPTR_VIRT2NPE(ptrSrc,dst) \
-  do { UINT32 temp; \
-      temp = (UINT32)IX_OSAL_MBUF_DATA_VIRTUAL_TO_PHYSICAL_TRANSLATION(ptrSrc); \
-      (dst) = IX_OSAL_SWAP_BE_SHARED_LONG(temp); } \
-  while(0)
-
-#else
-#define DATAPTR_VIRT2NPE(ptrSrc,dst) PTR_VIRT2NPE(IX_OSAL_MBUF_MDATA(ptrSrc),dst)
-#endif
-
-
-/* Flush the shared part of the mbuf header */
-#define IX_ETHACC_NE_CACHE_FLUSH(mbufPtr) \
-  do { \
-      IX_OSAL_CACHE_FLUSH(IX_ETHACC_NE_SHARED(mbufPtr), \
-			      sizeof(IxEthAccNe)); \
-    } \
-  while(0)
-
-/* Invalidate the shared part of the mbuf header */
-#define IX_ETHACC_NE_CACHE_INVALIDATE(mbufPtr) \
-  do { \
-      IX_OSAL_CACHE_INVALIDATE(IX_ETHACC_NE_SHARED(mbufPtr), \
-				   sizeof(IxEthAccNe)); \
-    } \
-  while(0)
-
-/* Preload one cache line (shared mbuf headers are aligned
- * and their size is 1 cache line)
- *
- * IX_OSAL_CACHED  is defined when the mbuf headers are
- * allocated from cached memory.
- *
- * Other processor on emulation environment may not implement
- * preload function
- */
-#ifdef IX_OSAL_CACHED
-	#if (CPU!=SIMSPARCSOLARIS) && !defined (__wince)
-		#define IX_ACC_DATA_CACHE_PRELOAD(ptr) \
-		do { /* preload a cache line (Xscale Processor) */ \
-			__asm__ (" pld [%0]\n": : "r" (ptr)); \
-		} \
-		while(0)
-	#else
-		/* preload not implemented on different processor */
-		#define IX_ACC_DATA_CACHE_PRELOAD(mbufPtr) \
-		do { /* nothing */ } while (0)
-	#endif
-#else
-	/* preload not needed if cache is not enabled */
-	#define IX_ACC_DATA_CACHE_PRELOAD(mbufPtr) \
-	do { /* nothing */ } while (0)
-#endif
-
-/**
- *
- * @brief function to retrieve the correct pointer from
- * a queue entry posted by the NPE
- *
- * @param qEntry : entry from qmgr queue
- *        mask : applicable mask for this queue
- *        (4 most significant bits are used for additional informations)
- *
- * @return IX_OSAL_MBUF * pointer to mbuf header
- *
- * @internal
- */
-PRIVATE IX_OSAL_MBUF *
-ixEthAccEntryFromQConvert(UINT32 qEntry, UINT32 mask)
-{
-    IX_OSAL_MBUF *mbufPtr;
-
-    if (qEntry != 0)
-    {
-        /* mask NPE bits (e.g. priority, port ...) */
-        qEntry &= mask;
-
-#if IX_ACC_DRAM_PHYS_OFFSET != 0
-        /* restore the original address pointer (if PHYS_OFFSET is not 0) */
-        qEntry |= (IX_ACC_DRAM_PHYS_OFFSET & ~IX_ETHNPE_QM_Q_RXENET_ADDR_MASK);
-#endif
-        /* get the mbuf pointer address from the npe-shared address */
-        qEntry -= offsetof(IX_OSAL_MBUF,ix_ne);
-
-        /* phys2virt mbuf */
-        mbufPtr = (IX_OSAL_MBUF *)IX_OSAL_MMU_PHYS_TO_VIRT(qEntry);
-
-        /* preload the cacheline shared with NPE */
-        IX_ACC_DATA_CACHE_PRELOAD(IX_ETHACC_NE_SHARED(mbufPtr));
-
-        /* preload the cacheline used by xscale */
-        IX_ACC_DATA_CACHE_PRELOAD(mbufPtr);
-    }
-    else
-    {
-	mbufPtr = NULL;
-    }
-
-    return mbufPtr;
-}
-
-/* Convert the mbuf header for NPE transmission */
-PRIVATE UINT32
-ixEthAccMbufTxQPrepare(IX_OSAL_MBUF *mbuf)
-{
-    UINT32 qbuf;
-    UINT32 len;
-
-    /* endianess swap for tci and flags
-       note: this is done only once, even for chained buffers */
-    IX_ETHACC_NE_FLAGS(mbuf)   = IX_OSAL_SWAP_BE_SHARED_SHORT(IX_ETHACC_NE_FLAGS(mbuf));
-    IX_ETHACC_NE_VLANTCI(mbuf) = IX_OSAL_SWAP_BE_SHARED_SHORT(IX_ETHACC_NE_VLANTCI(mbuf));
-
-    /* test for unchained mbufs */
-    if (IX_OSAL_MBUF_NEXT_BUFFER_IN_PKT_PTR(mbuf) == NULL)
-    {
-	/* "best case" scenario : unchained mbufs */
-	IX_ETH_ACC_STATS_INC(ixEthAccDataStats.unchainedTxMBufs);
-
-	/* payload pointer conversion */
-	DATAPTR_VIRT2NPE(mbuf, IX_ETHACC_NE_DATA(mbuf));
-
-	/* unchained mbufs : the frame length is the mbuf length
-	 * and the 2 identical lengths are stored in the same
-	 * word.
-	 */
-	len = IX_OSAL_MBUF_MLEN(mbuf);
-
-	/* set the length in both length and pktLen 16-bits fields */
-	len |= (len << IX_ETHNPE_ACC_LENGTH_OFFSET);
-	IX_ETHACC_NE_LEN(mbuf) = IX_OSAL_SWAP_BE_SHARED_LONG(len);
-
-	/* unchained mbufs : next contains 0 */
-	IX_ETHACC_NE_NEXT(mbuf) = 0;
-
-	/* flush shared header after all address conversions */
-	IX_ETHACC_NE_CACHE_FLUSH(mbuf);
-    }
-    else
-    {
-	/* chained mbufs */
-	IX_OSAL_MBUF *ptr = mbuf;
-	IX_OSAL_MBUF *nextPtr;
-	UINT32 frmLen;
-
-	/* get the frame length from the header of the first buffer */
-	frmLen = IX_OSAL_MBUF_PKT_LEN(mbuf);
-
-	do
-	{
-	    IX_ETH_ACC_STATS_INC(ixEthAccDataStats.chainedTxMBufs);
-
-	    /* payload pointer */
-	    DATAPTR_VIRT2NPE(ptr,IX_ETHACC_NE_DATA(ptr));
-	    /* Buffer length and frame length are stored in the same word */
-	    len = IX_OSAL_MBUF_MLEN(ptr);
-	    len = frmLen | (len << IX_ETHNPE_ACC_LENGTH_OFFSET);
-	    IX_ETHACC_NE_LEN(ptr) = IX_OSAL_SWAP_BE_SHARED_LONG(len);
-
-	    /* get the virtual next chain pointer */
-	    nextPtr = IX_OSAL_MBUF_NEXT_BUFFER_IN_PKT_PTR(ptr);
-	    if (nextPtr != NULL)
-	    {
-		/* shared pointer of the next buffer is chained */
-		PTR_VIRT2NPE(IX_ETHACC_NE_SHARED(nextPtr),
-			     IX_ETHACC_NE_NEXT(ptr));
-	    }
-	    else
-	    {
-		IX_ETHACC_NE_NEXT(ptr) = 0;
-	    }
-
-	    /* flush shared header after all address conversions */
-	    IX_ETHACC_NE_CACHE_FLUSH(ptr);
-
-	    /* move to next buffer */
-	    ptr = nextPtr;
-
-	    /* the frame length field is set only in the first buffer
-	     * and is zeroed in the next buffers
-	     */
-	    frmLen = 0;
-	}
-	while(ptr != NULL);
-
-    }
-
-    /* virt2phys mbuf itself */
-    qbuf = (UINT32)IX_OSAL_MMU_VIRT_TO_PHYS(
-		  IX_ETHACC_NE_SHARED(mbuf));
-
-    /* Ensure the bits which are reserved to exchange information with
-     * the NPE are cleared
-     *
-     * If the mbuf address is not correctly aligned, or from an
-     * incompatible memory range, there is no point to continue
-     */
-    IX_OSAL_ENSURE(((qbuf & ~IX_ETHNPE_QM_Q_TXENET_ADDR_MASK) == 0),
-	      "Invalid address range");
-
-    return qbuf;
-}
-
-/* Convert the mbuf header for NPE reception */
-PRIVATE UINT32
-ixEthAccMbufRxQPrepare(IX_OSAL_MBUF *mbuf)
-{
-    UINT32 len;
-    UINT32 qbuf;
-
-    if (IX_OSAL_MBUF_NEXT_BUFFER_IN_PKT_PTR(mbuf) == NULL)
-    {
-	/* "best case" scenario : unchained mbufs */
-	IX_ETH_ACC_STATS_INC(ixEthAccDataStats.unchainedRxFreeMBufs);
-
-	/* unchained mbufs : payload pointer */
-	DATAPTR_VIRT2NPE(mbuf, IX_ETHACC_NE_DATA(mbuf));
-
-	/* unchained mbufs : set the buffer length
-	* and the frame length field is zeroed
-	*/
-	len = (IX_OSAL_MBUF_MLEN(mbuf) << IX_ETHNPE_ACC_LENGTH_OFFSET);
-	IX_ETHACC_NE_LEN(mbuf) = IX_OSAL_SWAP_BE_SHARED_LONG(len);
-
-	/* unchained mbufs : next pointer is null */
-	IX_ETHACC_NE_NEXT(mbuf) = 0;
-
-	/* flush shared header after all address conversions */
-	IX_ETHACC_NE_CACHE_FLUSH(mbuf);
-
-	/* remove shared header cache line */
-	IX_ETHACC_NE_CACHE_INVALIDATE(mbuf);
-    }
-    else
-    {
-	/* chained mbufs */
-	IX_OSAL_MBUF *ptr = mbuf;
-	IX_OSAL_MBUF *nextPtr;
-
-	do
-	{
-	    /* chained mbufs */
-	    IX_ETH_ACC_STATS_INC(ixEthAccDataStats.chainedRxFreeMBufs);
-
-	    /* we must save virtual next chain pointer */
-	    nextPtr = IX_OSAL_MBUF_NEXT_BUFFER_IN_PKT_PTR(ptr);
-
-	    if (nextPtr != NULL)
-	    {
-		/* chaining pointer for NPE */
-		PTR_VIRT2NPE(IX_ETHACC_NE_SHARED(nextPtr),
-			     IX_ETHACC_NE_NEXT(ptr));
-	    }
-	    else
-	    {
-		IX_ETHACC_NE_NEXT(ptr) = 0;
-	    }
-
-	    /* payload pointer */
-	    DATAPTR_VIRT2NPE(ptr,IX_ETHACC_NE_DATA(ptr));
-
-	    /* buffer length */
-	    len = (IX_OSAL_MBUF_MLEN(ptr) << IX_ETHNPE_ACC_LENGTH_OFFSET);
-	    IX_ETHACC_NE_LEN(ptr) = IX_OSAL_SWAP_BE_SHARED_LONG(len);
-
-	    /* flush shared header after all address conversions */
-	    IX_ETHACC_NE_CACHE_FLUSH(ptr);
-
-	    /* remove shared header cache line */
-	    IX_ETHACC_NE_CACHE_INVALIDATE(ptr);
-
-	    /* next mbuf in the chain */
-	    ptr = nextPtr;
-	}
-	while(ptr != NULL);
-    }
-
-    /* virt2phys mbuf itself */
-    qbuf = (UINT32)IX_OSAL_MMU_VIRT_TO_PHYS(
-		  IX_ETHACC_NE_SHARED(mbuf));
-
-    /* Ensure the bits which are reserved to exchange information with
-     * the NPE are cleared
-     *
-     * If the mbuf address is not correctly aligned, or from an
-     * incompatible memory range, there is no point to continue
-     */
-    IX_OSAL_ENSURE(((qbuf & ~IX_ETHNPE_QM_Q_RXENET_ADDR_MASK) == 0),
-	      "Invalid address range");
-
-    return qbuf;
-}
-
-/* Convert the mbuf header after NPE transmission
- * Since there is nothing changed by the NPE, there is no need
- * to process anything but the update of internal stats
- * when they are enabled
-*/
-PRIVATE void
-ixEthAccMbufFromTxQ(IX_OSAL_MBUF *mbuf)
-{
-#ifndef NDEBUG
-    /* test for unchained mbufs */
-    if (IX_ETHACC_NE_NEXT(mbuf) == 0)
-    {
-	/* unchained mbufs : update the stats */
-	IX_ETH_ACC_STATS_INC(ixEthAccDataStats.unchainedTxDoneMBufs);
-    }
-    else
-    {
-	/* chained mbufs : walk the chain and update the stats */
-	IX_OSAL_MBUF *ptr = mbuf;
-
-	do
-	{
-	    IX_ETH_ACC_STATS_INC(ixEthAccDataStats.chainedTxDoneMBufs);
-	    ptr = IX_OSAL_MBUF_NEXT_BUFFER_IN_PKT_PTR(ptr);
-	}
-	while (ptr != NULL);
-    }
-#endif
-}
-
-/* Convert the mbuf header after NPE reception */
-PRIVATE void
-ixEthAccMbufFromRxQ(IX_OSAL_MBUF *mbuf)
-{
-    UINT32 len;
-
-    /* endianess swap for tci and flags
-       note: this is done only once, even for chained buffers */
-    IX_ETHACC_NE_FLAGS(mbuf)   = IX_OSAL_SWAP_BE_SHARED_SHORT(IX_ETHACC_NE_FLAGS(mbuf));
-    IX_ETHACC_NE_VLANTCI(mbuf) = IX_OSAL_SWAP_BE_SHARED_SHORT(IX_ETHACC_NE_VLANTCI(mbuf));
-
-    /* test for unchained mbufs */
-    if (IX_ETHACC_NE_NEXT(mbuf) == 0)
-    {
-	/* unchained mbufs */
-	IX_ETH_ACC_STATS_INC(ixEthAccDataStats.unchainedRxMBufs);
-
-	/* get the frame length. it is the same than the buffer length */
-	len = IX_OSAL_SWAP_BE_SHARED_LONG(IX_ETHACC_NE_LEN(mbuf));
-	len &= IX_ETHNPE_ACC_PKTLENGTH_MASK;
-	IX_OSAL_MBUF_PKT_LEN(mbuf) = IX_OSAL_MBUF_MLEN(mbuf) = len;
-
-        /* clears the next packet field */
-	IX_OSAL_MBUF_NEXT_BUFFER_IN_PKT_PTR(mbuf) = NULL;
-    }
-    else
-    {
-	IX_OSAL_MBUF *ptr = mbuf;
-	IX_OSAL_MBUF *nextPtr;
-	UINT32 frmLen;
-
-	/* convert the frame length */
-	frmLen = IX_OSAL_SWAP_BE_SHARED_LONG(IX_ETHACC_NE_LEN(mbuf));
-	IX_OSAL_MBUF_PKT_LEN(mbuf) = (frmLen & IX_ETHNPE_ACC_PKTLENGTH_MASK);
-
-        /* chained mbufs */
-	do
-	{
-	    IX_ETH_ACC_STATS_INC(ixEthAccDataStats.chainedRxMBufs);
-
-	    /* convert the length */
-	    len = IX_OSAL_SWAP_BE_SHARED_LONG(IX_ETHACC_NE_LEN(ptr));
-	    IX_OSAL_MBUF_MLEN(ptr) = (len >> IX_ETHNPE_ACC_LENGTH_OFFSET);
-
-            /* get the next pointer */
-	    PTR_NPE2VIRT(IX_OSAL_MBUF *,IX_ETHACC_NE_NEXT(ptr), nextPtr);
-	    if (nextPtr != NULL)
-	    {
-		nextPtr = (IX_OSAL_MBUF *)((UINT8 *)nextPtr - offsetof(IX_OSAL_MBUF,ix_ne));
-	    }
-	    /* set the next pointer */
-	    IX_OSAL_MBUF_NEXT_BUFFER_IN_PKT_PTR(ptr) = nextPtr;
-
-	    /* move to the next buffer */
-	    ptr = nextPtr;
-	}
-	while (ptr != NULL);
-    }
-}
-
-/* write to qmgr if possible and report an overflow if not possible
- * Use a fast lock to protect the queue write.
- * This way, the tx feature is reentrant.
- */
-PRIVATE IX_STATUS
-ixEthAccQmgrLockTxWrite(IxEthAccPortId portId, UINT32 qBuffer)
-{
-    IX_STATUS qStatus;
-    if (ixOsalFastMutexTryLock(&txWriteMutex[portId]) == IX_SUCCESS)
-    {
-	qStatus = ixQMgrQWrite(
-	       IX_ETH_ACC_PORT_TO_TX_Q_ID(portId),
-	       &qBuffer);
-#ifndef NDEBUG
-	if (qStatus != IX_SUCCESS)
-	{
-	    TX_STATS_INC(portId, txOverflow);
-	}
-#endif
-	ixOsalFastMutexUnlock(&txWriteMutex[portId]);
-    }
-    else
-    {
-	TX_STATS_INC(portId, txLock);
-	qStatus = IX_QMGR_Q_OVERFLOW;
-    }
-    return qStatus;
-}
-
-/* write to qmgr if possible and report an overflow if not possible
- * Use a fast lock to protect the queue write.
- * This way, the Rx feature is reentrant.
- */
-PRIVATE IX_STATUS
-ixEthAccQmgrLockRxWrite(IxEthAccPortId portId, UINT32 qBuffer)
-{
-    IX_STATUS qStatus;
-    if (ixOsalFastMutexTryLock(&rxWriteMutex[portId]) == IX_SUCCESS)
-    {
-	qStatus = ixQMgrQWrite(
-	       IX_ETH_ACC_PORT_TO_RX_FREE_Q_ID(portId),
-	       &qBuffer);
-#ifndef NDEBUG
-	if (qStatus != IX_SUCCESS)
-	{
-	    RX_STATS_INC(portId, rxFreeOverflow);
-	}
-#endif
-	ixOsalFastMutexUnlock(&rxWriteMutex[portId]);
-    }
-    else
-    {
-	RX_STATS_INC(portId, rxFreeLock);
-	qStatus = IX_QMGR_Q_OVERFLOW;
-    }
-    return qStatus;
-}
-
-/*
- * Set the priority and write to a qmgr queue.
- */
-PRIVATE IX_STATUS
-ixEthAccQmgrTxWrite(IxEthAccPortId portId, UINT32 qBuffer, UINT32 priority)
-{
-    /* fill the priority field */
-    qBuffer |= (priority << IX_ETHNPE_QM_Q_FIELD_PRIOR_R);
-
-    return ixEthAccQmgrLockTxWrite(portId, qBuffer);
-}
-
-/**
- *
- * @brief This function will discover the highest priority S/W Tx Q that
- *        has entries in it
- *
- * @param portId - (in) the id of the port whose S/W Tx queues are to be searched
- *        priorityPtr - (out) the priority of the highest priority occupied q will be written
- *                      here
- *
- * @return IX_ETH_ACC_SUCCESS if an occupied Q is found
- *         IX_ETH_ACC_FAIL if no Q has entries
- *
- * @internal
- */
-PRIVATE IxEthAccStatus
-ixEthAccTxSwQHighestPriorityGet(IxEthAccPortId portId,
-				IxEthAccTxPriority *priorityPtr)
-{
-    if (ixEthAccPortData[portId].ixEthAccTxData.schDiscipline
-	== FIFO_NO_PRIORITY)
-    {
-	if(IX_ETH_ACC_DATAPLANE_IS_Q_EMPTY(ixEthAccPortData[portId].
-	       ixEthAccTxData.txQ[IX_ETH_ACC_TX_DEFAULT_PRIORITY]))
-	{
-	    return IX_ETH_ACC_FAIL;
-	}
-	else
-	{
-	    *priorityPtr = IX_ETH_ACC_TX_DEFAULT_PRIORITY;
-	    TX_STATS_INC(portId,txPriority[*priorityPtr]);
-	    return IX_ETH_ACC_SUCCESS;
-	}
-    }
-    else
-    {
-	IxEthAccTxPriority highestPriority = IX_ETH_ACC_TX_PRIORITY_7;
-	while(1)
-	{
-	    if(!IX_ETH_ACC_DATAPLANE_IS_Q_EMPTY(ixEthAccPortData[portId].
-	       ixEthAccTxData.txQ[highestPriority]))
-	    {
-
-		*priorityPtr = highestPriority;
-		TX_STATS_INC(portId,txPriority[highestPriority]);
-		return IX_ETH_ACC_SUCCESS;
-
-	    }
-	    if (highestPriority == IX_ETH_ACC_TX_PRIORITY_0)
-	    {
-		return IX_ETH_ACC_FAIL;
-	    }
-	    highestPriority--;
-	}
-    }
-}
-
-/**
- *
- * @brief This function will take a buffer from a TX S/W Q and attempt
- *        to add it to the relevant TX H/W Q
- *
- * @param portId - the port whose TX queue is to be written to
- *        priority - identifies the queue from which the entry is to be read
- *
- * @internal
- */
-PRIVATE IxEthAccStatus
-ixEthAccTxFromSwQ(IxEthAccPortId portId,
-		  IxEthAccTxPriority priority)
-{
-    IX_OSAL_MBUF        *mbuf;
-    IX_STATUS	   qStatus;
-
-    IX_OSAL_ENSURE((UINT32)priority <= (UINT32)7, "Invalid priority");
-
-    IX_ETH_ACC_DATAPLANE_REMOVE_MBUF_FROM_Q_HEAD(
-	ixEthAccPortData[portId].ixEthAccTxData.txQ[priority],
-	mbuf);
-
-    if (mbuf != NULL)
-    {
-	/*
-	 * Add the Tx buffer to the H/W Tx Q
-	 * We do not need to flush here as it is already done
-	 * in TxFrameSubmit().
-	 */
-	qStatus = ixEthAccQmgrTxWrite(
-	      portId,
-	      IX_OSAL_MMU_VIRT_TO_PHYS((UINT32)IX_ETHACC_NE_SHARED(mbuf)),
-	      priority);
-
-	if (qStatus == IX_SUCCESS)
-	{
-	    TX_STATS_INC(portId,txFromSwQOK);
-	    return IX_SUCCESS;
-	}
-	else if (qStatus == IX_QMGR_Q_OVERFLOW)
-	{
-	    /*
-	     * H/W Q overflow, need to save the buffer
-	     * back on the s/w Q.
-	     * we must put it back on the head of the q to avoid
-	     * reordering packet tx
-	     */
-	    TX_STATS_INC(portId,txFromSwQDelayed);
-	    IX_ETH_ACC_DATAPLANE_ADD_MBUF_TO_Q_HEAD(
-		ixEthAccPortData[portId].ixEthAccTxData.txQ[priority],
-		mbuf);
-
-	    /*enable Q notification*/
-	    qStatus = ixQMgrNotificationEnable(
-		IX_ETH_ACC_PORT_TO_TX_Q_ID(portId),
-		IX_ETH_ACC_PORT_TO_TX_Q_SOURCE(portId));
-
-            if (qStatus != IX_SUCCESS && qStatus != IX_QMGR_WARNING)
-            {
-		TX_INC(portId,txUnexpectedError);
-		IX_ETH_ACC_FATAL_LOG(
-	            "ixEthAccTxFromSwQ:Unexpected Error: %u\n",
-	            qStatus, 0, 0, 0, 0, 0);
-            }
-	}
-	else
-	{
-	    TX_INC(portId,txUnexpectedError);
-
-	    /* recovery attempt */
-	    IX_ETH_ACC_DATAPLANE_ADD_MBUF_TO_Q_HEAD(
-		ixEthAccPortData[portId].ixEthAccTxData.txQ[priority],
-		mbuf);
-
-	    IX_ETH_ACC_FATAL_LOG(
-		"ixEthAccTxFromSwQ:Error: unexpected QM status 0x%08X\n",
-		qStatus, 0, 0, 0, 0, 0);
-	}
-    }
-    else
-    {
-	/* sw queue is empty */
-    }
-    return IX_ETH_ACC_FAIL;
-}
-
-/**
- *
- * @brief This function will take a buffer from a RXfree S/W Q and attempt
- *        to add it to the relevant RxFree H/W Q
- *
- * @param portId - the port whose RXFree queue is to be written to
- *
- * @internal
- */
-PRIVATE IxEthAccStatus
-ixEthAccRxFreeFromSwQ(IxEthAccPortId portId)
-{
-    IX_OSAL_MBUF        *mbuf;
-    IX_STATUS	   qStatus = IX_SUCCESS;
-
-    IX_ETH_ACC_DATAPLANE_REMOVE_MBUF_FROM_Q_HEAD(
-	  ixEthAccPortData[portId].ixEthAccRxData.freeBufferList,
-	  mbuf);
-    if (mbuf != NULL)
-    {
-	/*
-	 * Add The Rx Buffer to the H/W Free buffer Q if possible
-	 */
-	qStatus = ixEthAccQmgrLockRxWrite(portId,
-		  IX_OSAL_MMU_VIRT_TO_PHYS(
-			 (UINT32)IX_ETHACC_NE_SHARED(mbuf)));
-
-	if (qStatus == IX_SUCCESS)
-	{
-	    RX_STATS_INC(portId,rxFreeRepFromSwQOK);
-	    /*
-	     * Buffer added to h/w Q.
-	     */
-	    return IX_SUCCESS;
-	}
-	else if (qStatus == IX_QMGR_Q_OVERFLOW)
-	{
-	    /*
-	     * H/W Q overflow, need to save the buffer back on the s/w Q.
-	     */
-	    RX_STATS_INC(portId,rxFreeRepFromSwQDelayed);
-
-	    IX_ETH_ACC_DATAPLANE_ADD_MBUF_TO_Q_HEAD(
-		   ixEthAccPortData[portId].ixEthAccRxData.freeBufferList,
-		   mbuf);
-	}
-	else
-	{
-	    /* unexpected qmgr error */
-	    RX_INC(portId,rxUnexpectedError);
-
-	    IX_ETH_ACC_DATAPLANE_ADD_MBUF_TO_Q_HEAD(
-		    ixEthAccPortData[portId].ixEthAccRxData.freeBufferList,
-		    mbuf);
-
-	    IX_ETH_ACC_FATAL_LOG("IxEthAccRxFreeFromSwQ:Error: unexpected QM status 0x%08X\n",
-				 qStatus, 0, 0, 0, 0, 0);
-	}
-    }
-    else
-    {
-	/* sw queue is empty */
-    }
-    return IX_ETH_ACC_FAIL;
-}
-
-
-IX_ETH_ACC_PUBLIC
-IxEthAccStatus ixEthAccInitDataPlane()
-{
-    UINT32 portId;
-
-    /*
-     * Initialize the service and register callback to other services.
-     */
-
-    IX_ETH_ACC_MEMSET(&ixEthAccDataStats,
-		      0,
-		      sizeof(ixEthAccDataStats));
-
-    for(portId=0; portId < IX_ETH_ACC_NUMBER_OF_PORTS; portId++)
-    {
-	ixOsalFastMutexInit(&txWriteMutex[portId]);
-	ixOsalFastMutexInit(&rxWriteMutex[portId]);
-
-	IX_ETH_ACC_MEMSET(&ixEthAccPortData[portId],
-			  0,
-			  sizeof(ixEthAccPortData[portId]));
-
-	ixEthAccPortData[portId].ixEthAccTxData.schDiscipline = FIFO_NO_PRIORITY;
-    }
-
-    return (IX_ETH_ACC_SUCCESS);
-}
-
-
-IX_ETH_ACC_PUBLIC
-IxEthAccStatus ixEthAccPortTxDoneCallbackRegister(IxEthAccPortId portId,
-						  IxEthAccPortTxDoneCallback
-						  txCallbackFn,
-						  UINT32 callbackTag)
-{
-    if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED())
-    {
-	return (IX_ETH_ACC_FAIL);
-    }
-    if (!IX_ETH_ACC_IS_PORT_VALID(portId))
-    {
-	return (IX_ETH_ACC_INVALID_PORT);
-    }
-
-/* HACK: removing this code to enable NPE-A preliminary testing
- *    if (IX_ETH_ACC_SUCCESS != ixEthAccSingleEthNpeCheck(portId))
- *    {
- *        IX_ETH_ACC_WARNING_LOG("ixEthAccPortTxDoneCallbackRegister: Unavailable Eth %d: Cannot register TxDone Callback.\n",(INT32)portId,0,0,0,0,0);
- *        return IX_ETH_ACC_SUCCESS ;
- *    }
- */
-
-    if (!IX_ETH_IS_PORT_INITIALIZED(portId))
-    {
-	return (IX_ETH_ACC_PORT_UNINITIALIZED);
-    }
-    if (txCallbackFn == 0)
-	/* Check for null function pointer here. */
-    {
-	return (IX_ETH_ACC_INVALID_ARG);
-    }
-    ixEthAccPortData[portId].ixEthAccTxData.txBufferDoneCallbackFn = txCallbackFn;
-    ixEthAccPortData[portId].ixEthAccTxData.txCallbackTag = callbackTag;
-    return (IX_ETH_ACC_SUCCESS);
-}
-
-
-IX_ETH_ACC_PUBLIC
-IxEthAccStatus ixEthAccPortRxCallbackRegister(IxEthAccPortId portId,
-					      IxEthAccPortRxCallback
-					      rxCallbackFn,
-					      UINT32 callbackTag)
-{
-    IxEthAccPortId port;
-
-    if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED())
-    {
-	return (IX_ETH_ACC_FAIL);
-    }
-    if (!IX_ETH_ACC_IS_PORT_VALID(portId))
-    {
-	return (IX_ETH_ACC_INVALID_PORT);
-    }
-
-    if (IX_ETH_ACC_SUCCESS != ixEthAccSingleEthNpeCheck(portId))
-    {
-        IX_ETH_ACC_WARNING_LOG("ixEthAccPortRxCallbackRegister: Unavailable Eth %d: Cannot register Rx Callback.\n",(INT32)portId,0,0,0,0,0);
-        return IX_ETH_ACC_SUCCESS ;
-    }
-
-    if (!IX_ETH_IS_PORT_INITIALIZED(portId))
-    {
-	return (IX_ETH_ACC_PORT_UNINITIALIZED);
-    }
-
-    /* Check for null function pointer here. */
-    if (rxCallbackFn == NULL)
-    {
-	return (IX_ETH_ACC_INVALID_ARG);
-    }
-
-    /* Check the user is not changing the callback type
-     * when the port is enabled.
-    */
-    if (ixEthAccMacState[portId].portDisableState == ACTIVE)
-    {
-	for (port = 0; port < IX_ETH_ACC_NUMBER_OF_PORTS; port++)
-	{
-	    if ((ixEthAccMacState[port].portDisableState == ACTIVE)
-		&& (ixEthAccPortData[port].ixEthAccRxData.rxMultiBufferCallbackInUse == true))
-	    {
-		/* one of the active ports has a different rx callback type.
-		 * Changing the callback type when the port is enabled
-		 * is not safe
-		 */
-		return (IX_ETH_ACC_INVALID_ARG);
-	    }
-	}
-    }
-
-    /* update the callback pointer : this is done before
-     * registering the new qmgr callback
-     */
-    ixEthAccPortData[portId].ixEthAccRxData.rxCallbackFn = rxCallbackFn;
-    ixEthAccPortData[portId].ixEthAccRxData.rxCallbackTag = callbackTag;
-
-    /* update the qmgr callback for rx queues */
-    if (ixEthAccQMgrRxCallbacksRegister(ixEthRxFrameQMCallback)
-	!= IX_ETH_ACC_SUCCESS)
-    {
-	/* unexpected qmgr error */
-        IX_ETH_ACC_FATAL_LOG("ixEthAccPortRxCallbackRegister: unexpected QMgr error, " \
-            "could not register Rx single-buffer callback\n", 0, 0, 0, 0, 0, 0);
-
-	RX_INC(portId,rxUnexpectedError);
-	return (IX_ETH_ACC_INVALID_ARG);
-    }
-
-    ixEthAccPortData[portId].ixEthAccRxData.rxMultiBufferCallbackInUse = false;
-
-    return (IX_ETH_ACC_SUCCESS);
-}
-
-IX_ETH_ACC_PUBLIC
-IxEthAccStatus ixEthAccPortMultiBufferRxCallbackRegister(
-			 IxEthAccPortId portId,
-			 IxEthAccPortMultiBufferRxCallback
-			 rxCallbackFn,
-			 UINT32 callbackTag)
-{
-    IxEthAccPortId port;
-
-    if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED())
-    {
-	return (IX_ETH_ACC_FAIL);
-    }
-    if (!IX_ETH_ACC_IS_PORT_VALID(portId))
-    {
-	return (IX_ETH_ACC_INVALID_PORT);
-    }
-
-    if (IX_ETH_ACC_SUCCESS != ixEthAccSingleEthNpeCheck(portId))
-    {
-        IX_ETH_ACC_WARNING_LOG("ixEthAccPortMultiBufferRxCallbackRegister: Unavailable Eth %d: Cannot register Rx Callback.\n",(INT32)portId,0,0,0,0,0);
-        return IX_ETH_ACC_SUCCESS ;
-    }
-
-    if (!IX_ETH_IS_PORT_INITIALIZED(portId))
-    {
-	return (IX_ETH_ACC_PORT_UNINITIALIZED);
-    }
-
-    /* Check for null function pointer here. */
-    if (rxCallbackFn == NULL)
-    {
-	return (IX_ETH_ACC_INVALID_ARG);
-    }
-
-    /* Check the user is not changing the callback type
-     * when the port is enabled.
-    */
-    if (ixEthAccMacState[portId].portDisableState == ACTIVE)
-    {
-	for (port = 0; port < IX_ETH_ACC_NUMBER_OF_PORTS; port++)
-	{
-	    if ((ixEthAccMacState[port].portDisableState == ACTIVE)
-		&& (ixEthAccPortData[port].ixEthAccRxData.rxMultiBufferCallbackInUse == false))
-	    {
-		/* one of the active ports has a different rx callback type.
-		 * Changing the callback type when the port is enabled
-		 * is not safe
-		 */
-		return (IX_ETH_ACC_INVALID_ARG);
-	    }
-	}
-    }
-
-    /* update the callback pointer : this is done before
-     * registering the new qmgr callback
-     */
-    ixEthAccPortData[portId].ixEthAccRxData.rxMultiBufferCallbackFn = rxCallbackFn;
-    ixEthAccPortData[portId].ixEthAccRxData.rxMultiBufferCallbackTag = callbackTag;
-
-    /* update the qmgr callback for rx queues */
-    if (ixEthAccQMgrRxCallbacksRegister(ixEthRxMultiBufferQMCallback)
-	!= IX_ETH_ACC_SUCCESS)
-    {
-	/* unexpected qmgr error */
-	RX_INC(portId,rxUnexpectedError);
-
-        IX_ETH_ACC_FATAL_LOG("ixEthAccPortMultiBufferRxCallbackRegister: unexpected QMgr error, " \
-            "could not register Rx multi-buffer callback\n", 0, 0, 0, 0, 0, 0);
-
-	return (IX_ETH_ACC_INVALID_ARG);
-    }
-
-    ixEthAccPortData[portId].ixEthAccRxData.rxMultiBufferCallbackInUse = true;
-
-    return (IX_ETH_ACC_SUCCESS);
-}
-
-IX_ETH_ACC_PUBLIC
-IxEthAccStatus ixEthAccPortTxFrameSubmit(IxEthAccPortId portId,
-					 IX_OSAL_MBUF *buffer,
-					 IxEthAccTxPriority priority)
-{
-    IX_STATUS	qStatus = IX_SUCCESS;
-    UINT32      qBuffer;
-    IxEthAccTxPriority highestPriority;
-    IxQMgrQStatus txQStatus;
-
-#ifndef NDEBUG
-    if (buffer == NULL)
-    {
-	return (IX_ETH_ACC_FAIL);
-    }
-    if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED())
-    {
-	return (IX_ETH_ACC_FAIL);
-    }
-    if (!IX_ETH_ACC_IS_PORT_VALID(portId))
-    {
-	return (IX_ETH_ACC_INVALID_PORT);
-    }
-
-    if (IX_ETH_ACC_SUCCESS != ixEthAccSingleEthNpeCheck(portId))
-    {
-        IX_ETH_ACC_FATAL_LOG("ixEthAccPortTxFrameSubmit: Unavailable Eth %d: Cannot submit Tx Frame.\n",
-			     (INT32)portId,0,0,0,0,0);
-        return IX_ETH_ACC_PORT_UNINITIALIZED ;
-    }
-
-    if (!IX_ETH_IS_PORT_INITIALIZED(portId))
-    {
-	return (IX_ETH_ACC_PORT_UNINITIALIZED);
-    }
-    if ((UINT32)priority > (UINT32)IX_ETH_ACC_TX_PRIORITY_7)
-    {
-	return (IX_ETH_ACC_INVALID_ARG);
-    }
-#endif
-
-    /*
-     * Need to Flush the MBUF and its contents (data) as it may be
-     * read from the NPE. Convert virtual addresses to physical addresses also.
-     */
-    qBuffer = ixEthAccMbufTxQPrepare(buffer);
-
-    /*
-     * If no fifo priority set on Xscale ...
-     */
-    if (ixEthAccPortData[portId].ixEthAccTxData.schDiscipline ==
-	FIFO_NO_PRIORITY)
-    {
-	/*
-	 * Add The Tx Buffer to the H/W Tx Q if possible
-	 * (the priority is passed to the NPE, because
-	 * the NPE is able to reorder the frames
-	 * before transmission to the underlying hardware)
-	 */
-	qStatus = ixEthAccQmgrTxWrite(portId,
-				      qBuffer,
-				      IX_ETH_ACC_TX_DEFAULT_PRIORITY);
-
-	if (qStatus == IX_SUCCESS)
-	{
-	    TX_STATS_INC(portId,txQOK);
-
-	    /*
-	     * "best case" scenario : Buffer added to h/w Q.
-	     */
-	    return (IX_SUCCESS);
-	}
-	else if (qStatus == IX_QMGR_Q_OVERFLOW)
-	{
-	    /*
-	     * We were unable to write the buffer to the
-	     * appropriate H/W Q,  Save it in the sw Q.
-	     * (use the default priority queue regardless of
-	     * input parameter)
-	     */
-	    priority = IX_ETH_ACC_TX_DEFAULT_PRIORITY;
-	}
-	else
-	{
-	    /* unexpected qmgr error */
-	    TX_INC(portId,txUnexpectedError);
-	    IX_ETH_ACC_FATAL_LOG(
-		"ixEthAccPortTxFrameSubmit:Error: qStatus = %u\n",
-		(UINT32)qStatus, 0, 0, 0, 0, 0);
-	    return (IX_ETH_ACC_FAIL);
-	}
-    }
-    else if (ixEthAccPortData[portId].ixEthAccTxData.schDiscipline ==
-	     FIFO_PRIORITY)
-    {
-
-	/*
-	 * For priority transmission, put the frame directly on the H/W queue
-	 * if the H/W queue is empty, otherwise, put it in a S/W Q
-	 */
-	ixQMgrQStatusGet(IX_ETH_ACC_PORT_TO_TX_Q_ID(portId), &txQStatus);
-	if((txQStatus & IX_QMGR_Q_STATUS_E_BIT_MASK) != 0)
-	{
-	    /*The tx queue is empty, check whether there are buffers on the s/w queues*/
-	    if(ixEthAccTxSwQHighestPriorityGet(portId,  &highestPriority)
-	       !=IX_ETH_ACC_FAIL)
-	    {
-		/*there are buffers on the s/w queues, submit them*/
-		ixEthAccTxFromSwQ(portId, highestPriority);
-
-		/* the queue was empty, 1 buffer is already supplied
-		 * but is likely to be immediately transmitted and the
-		 * hw queue is likely to be empty again, so submit
-		 * more from the sw queues
-		 */
-		if(ixEthAccTxSwQHighestPriorityGet(portId,  &highestPriority)
-		   !=IX_ETH_ACC_FAIL)
-		{
-		    ixEthAccTxFromSwQ(portId, highestPriority);
-		    /*
-		     * and force the buffer supplied to be placed
-		     * on a priority queue
-		     */
-		    qStatus = IX_QMGR_Q_OVERFLOW;
-		}
-		else
-		{
-		    /*there are no buffers in the s/w queues, submit directly*/
-		    qStatus = ixEthAccQmgrTxWrite(portId, qBuffer, priority);
-		}
-	    }
-	    else
-	    {
-		/*there are no buffers in the s/w queues, submit directly*/
-		qStatus = ixEthAccQmgrTxWrite(portId, qBuffer, priority);
-	    }
-	}
-	else
-	{
-	    qStatus = IX_QMGR_Q_OVERFLOW;
-	}
-    }
-    else
-    {
-	TX_INC(portId,txUnexpectedError);
-	IX_ETH_ACC_FATAL_LOG(
-	    "ixEthAccPortTxFrameSubmit:Error: wrong schedule discipline setup\n",
-	    0, 0, 0, 0, 0, 0);
-	return (IX_ETH_ACC_FAIL);
-    }
-
-    if(qStatus == IX_SUCCESS )
-    {
-	TX_STATS_INC(portId,txQOK);
-	return IX_ETH_ACC_SUCCESS;
-    }
-    else if(qStatus == IX_QMGR_Q_OVERFLOW)
-    {
-	TX_STATS_INC(portId,txQDelayed);
-	/*
-	 * We were unable to write the buffer to the
-	 * appropriate H/W Q,  Save it in a s/w Q.
-	 */
-	IX_ETH_ACC_DATAPLANE_ADD_MBUF_TO_Q_TAIL(
-		ixEthAccPortData[portId].
-		ixEthAccTxData.txQ[priority],
-		buffer);
-
-	qStatus = ixQMgrNotificationEnable(
-		IX_ETH_ACC_PORT_TO_TX_Q_ID(portId),
-		IX_ETH_ACC_PORT_TO_TX_Q_SOURCE(portId));
-
-        if (qStatus != IX_SUCCESS)
-	{
-	    if (qStatus == IX_QMGR_WARNING)
-	    {
-		/* notification is enabled for a queue
-		 * which is already empty (the condition is already met)
-		 * and there will be no more queue event to drain the sw queue
-		 */
-		TX_STATS_INC(portId,txLateNotificationEnabled);
-
-		/* pull a buffer from the sw queue */
-		if(ixEthAccTxSwQHighestPriorityGet(portId,  &highestPriority)
-		   !=IX_ETH_ACC_FAIL)
-		{
-		    /*there are buffers on the s/w queues, submit from them*/
-		    ixEthAccTxFromSwQ(portId, highestPriority);
-		}
-	    }
-	    else
-	    {
-		TX_INC(portId,txUnexpectedError);
-		IX_ETH_ACC_FATAL_LOG(
-		     "ixEthAccPortTxFrameSubmit: unexpected Error: %u\n",
-		     qStatus, 0, 0, 0, 0, 0);
-	    }
-        }
-    }
-    else
-    {
-	TX_INC(portId,txUnexpectedError);
-	IX_ETH_ACC_FATAL_LOG(
-	     "ixEthAccPortTxFrameSubmit: unexpected Error: %u\n",
-	     qStatus, 0, 0, 0, 0, 0);
-	return (IX_ETH_ACC_FAIL);
-    }
-
-    return (IX_ETH_ACC_SUCCESS);
-}
-
-
-/**
- *
- * @brief replenish: convert a chain of mbufs to the format
- *        expected by the NPE
- *
-  */
-
-IX_ETH_ACC_PUBLIC
-IxEthAccStatus ixEthAccPortRxFreeReplenish(IxEthAccPortId portId,
-					   IX_OSAL_MBUF *buffer)
-{
-    IX_STATUS	qStatus = IX_SUCCESS;
-    UINT32      qBuffer;
-
-    /*
-     * Check buffer is valid.
-     */
-
-#ifndef NDEBUG
-    /* check parameter value */
-    if (buffer == 0)
-    {
-	return (IX_ETH_ACC_FAIL);
-    }
-    if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED())
-    {
-	return (IX_ETH_ACC_FAIL);
-    }
-    if (!IX_ETH_ACC_IS_PORT_VALID(portId))
-    {
-	return (IX_ETH_ACC_INVALID_PORT);
-    }
-
-    /* check initialisation is done */
-    if (IX_ETH_ACC_SUCCESS != ixEthAccSingleEthNpeCheck(portId))
-    {
-        IX_ETH_ACC_FATAL_LOG(" ixEthAccPortRxFreeReplenish: Unavailable Eth %d: Cannot replenish Rx Free Q.\n",(INT32)portId,0,0,0,0,0);
-        return IX_ETH_ACC_PORT_UNINITIALIZED ;
-    }
-
-    if (!IX_ETH_IS_PORT_INITIALIZED(portId))
-    {
-	return (IX_ETH_ACC_PORT_UNINITIALIZED);
-    }
-    /* check boundaries and constraints */
-    if (IX_OSAL_MBUF_MLEN(buffer) < IX_ETHNPE_ACC_RXFREE_BUFFER_LENGTH_MIN)
-    {
-	return (IX_ETH_ACC_FAIL);
-    }
-#endif
-
-    qBuffer = ixEthAccMbufRxQPrepare(buffer);
-
-    /*
-     * Add The Rx Buffer to the H/W Free buffer Q if possible
-     */
-    qStatus = ixEthAccQmgrLockRxWrite(portId, qBuffer);
-
-    if (qStatus == IX_SUCCESS)
-    {
-	RX_STATS_INC(portId,rxFreeRepOK);
-	/*
-	 * Buffer added to h/w Q.
-	 */
-	return (IX_SUCCESS);
-    }
-    else if (qStatus == IX_QMGR_Q_OVERFLOW)
-    {
-	RX_STATS_INC(portId,rxFreeRepDelayed);
-	/*
-	 * We were unable to write the buffer to the approprate H/W Q,
-	 * Save it in a s/w Q.
-	 */
-	IX_ETH_ACC_DATAPLANE_ADD_MBUF_TO_Q_TAIL(
-	    ixEthAccPortData[portId].ixEthAccRxData.freeBufferList,
-	    buffer);
-
-	qStatus = ixQMgrNotificationEnable(
-	    IX_ETH_ACC_PORT_TO_RX_FREE_Q_ID(portId),
-	    IX_ETH_ACC_PORT_TO_RX_FREE_Q_SOURCE(portId));
-
-        if (qStatus != IX_SUCCESS)
-	{
-	    if (qStatus == IX_QMGR_WARNING)
-	    {
-		/* notification is enabled for a queue
-		 * which is already empty (the condition is already met)
-		 * and there will be no more queue event to drain the sw queue
-		 * move an entry from the sw queue to the hw queue */
-		RX_STATS_INC(portId,rxFreeLateNotificationEnabled);
-		ixEthAccRxFreeFromSwQ(portId);
-	    }
-	    else
-	    {
-		RX_INC(portId,rxUnexpectedError);
-		IX_ETH_ACC_FATAL_LOG(
-		     "ixEthAccRxPortFreeReplenish:Error: %u\n",
-		     qStatus, 0, 0, 0, 0, 0);
-	    }
-        }
-    }
-    else
-    {
-	RX_INC(portId,rxUnexpectedError);
-	IX_ETH_ACC_FATAL_LOG(
-	    "ixEthAccRxPortFreeReplenish:Error: qStatus = %u\n",
-	    (UINT32)qStatus, 0, 0, 0, 0, 0);
-        return(IX_ETH_ACC_FAIL);
-    }
-    return (IX_ETH_ACC_SUCCESS);
-}
-
-
-IX_ETH_ACC_PUBLIC
-IxEthAccStatus ixEthAccTxSchedulingDisciplineSetPriv(IxEthAccPortId portId,
-						 IxEthAccSchedulerDiscipline
-						 sched)
-{
-    if (!IX_ETH_ACC_IS_PORT_VALID(portId))
-    {
-	return (IX_ETH_ACC_INVALID_PORT);
-    }
-
-    if (IX_ETH_ACC_SUCCESS != ixEthAccSingleEthNpeCheck(portId))
-    {
-        IX_ETH_ACC_WARNING_LOG("ixEthAccTxSchedulingDisciplineSet: Unavailable Eth %d: Cannot set Tx Scheduling Discipline.\n",(INT32)portId,0,0,0,0,0);
-        return IX_ETH_ACC_SUCCESS ;
-    }
-
-    if (!IX_ETH_IS_PORT_INITIALIZED(portId))
-    {
-	return (IX_ETH_ACC_PORT_UNINITIALIZED);
-    }
-
-    if (sched != FIFO_PRIORITY && sched != FIFO_NO_PRIORITY)
-    {
-	return (IX_ETH_ACC_INVALID_ARG);
-    }
-
-    ixEthAccPortData[portId].ixEthAccTxData.schDiscipline = sched;
-    return (IX_ETH_ACC_SUCCESS);
-}
-
-IX_ETH_ACC_PUBLIC
-IxEthAccStatus ixEthAccRxSchedulingDisciplineSetPriv(IxEthAccSchedulerDiscipline
-						 sched)
-{
-    if (sched != FIFO_PRIORITY && sched != FIFO_NO_PRIORITY)
-    {
-	return (IX_ETH_ACC_INVALID_ARG);
-    }
-
-    ixEthAccDataInfo.schDiscipline = sched;
-
-    return (IX_ETH_ACC_SUCCESS);
-}
-
-
-/**
- * @fn ixEthRxFrameProcess(IxEthAccPortId portId, IX_OSAL_MBUF *mbufPtr)
- *
- * @brief process incoming frame :
- *
- * @param @ref IxQMgrCallback IxQMgrMultiBufferCallback
- *
- * @return none
- *
- * @internal
- *
- */
-IX_ETH_ACC_PRIVATE BOOL
-ixEthRxFrameProcess(IxEthAccPortId portId, IX_OSAL_MBUF *mbufPtr)
-{
-    UINT32 flags;
-    IxEthDBStatus result;
-
-#ifndef NDEBUG
-    /* Prudent to at least check the port is within range */
-    if (portId >= IX_ETH_ACC_NUMBER_OF_PORTS)
-    {
-	ixEthAccDataStats.unexpectedError++;
-	IX_ETH_ACC_FATAL_LOG(
-	     "ixEthRxFrameProcess: Illegal port: %u\n",
-	     (UINT32)portId, 0, 0, 0, 0, 0);
-	return false;
-    }
-#endif
-
-    /* convert fields from mbuf header */
-    ixEthAccMbufFromRxQ(mbufPtr);
-
-    /* check about any special processing for this frame */
-    flags = IX_ETHACC_NE_FLAGS(mbufPtr);
-    if ((flags & (IX_ETHACC_NE_FILTERMASK | IX_ETHACC_NE_NEWSRCMASK)) == 0)
-    {
-	/* "best case" scenario : nothing special to do for this frame */
-	return true;
-    }
-
-#ifdef CONFIG_IXP425_COMPONENT_ETHDB
-    /* if a new source MAC address is detected by the NPE,
-     * update IxEthDB with the portId and the MAC address.
-     */
-    if ((flags & IX_ETHACC_NE_NEWSRCMASK & ixEthAccNewSrcMask) != 0)
-    {
-        result = ixEthDBFilteringDynamicEntryProvision(portId,
-			  (IxEthDBMacAddr *) IX_ETHACC_NE_SOURCEMAC(mbufPtr));
-
-	if (result != IX_ETH_DB_SUCCESS && result != IX_ETH_DB_FEATURE_UNAVAILABLE)
-	{
-            if ((ixEthAccMacState[portId].portDisableState == ACTIVE) && (result != IX_ETH_DB_BUSY))
-            {
-	        RX_STATS_INC(portId, rxUnexpectedError);
-                IX_ETH_ACC_FATAL_LOG("ixEthRxFrameProcess: Failed to add source MAC \
-                                    to the Learning/Filtering database\n", 0, 0, 0, 0, 0, 0);
-            }
-            else
-            {
-                /* we expect this to fail during PortDisable, as EthDB is disabled for
-                 * that port and will refuse to learn new addresses
-		 */
-            }
-	}
-	else
-	{
-	    RX_STATS_INC(portId, rxUnlearnedMacAddress);
-	}
-    }
-#endif
-
-    /* check if this frame should have been filtered
-     * by the NPE and take the appropriate action
-     */
-    if (((flags & IX_ETHACC_NE_FILTERMASK) != 0)
-        && (ixEthAccMacState[portId].portDisableState == ACTIVE))
-    {
-        /* If the mbuf was allocated with a small data size, or the current data pointer is not
-         * within the allocated data area, then the buffer is non-standard and has to be
-         * replenished with the minimum size only
-         */
-        if( (IX_OSAL_MBUF_ALLOCATED_BUFF_LEN(mbufPtr) < IX_ETHNPE_ACC_RXFREE_BUFFER_LENGTH_MIN)
-           || ((UINT8 *)IX_OSAL_MBUF_ALLOCATED_BUFF_DATA(mbufPtr) > IX_OSAL_MBUF_MDATA(mbufPtr))
-           || ((UINT8 *)(IX_OSAL_MBUF_ALLOCATED_BUFF_DATA(mbufPtr) +
-              IX_OSAL_MBUF_ALLOCATED_BUFF_LEN(mbufPtr))
-               < IX_OSAL_MBUF_MDATA(mbufPtr)) )
-        {
-            /* set to minimum length */
-            IX_OSAL_MBUF_MLEN(mbufPtr) = IX_OSAL_MBUF_PKT_LEN(mbufPtr) =
-                IX_ETHNPE_ACC_RXFREE_BUFFER_LENGTH_MIN;
-        }
-        else
-        {
-            /* restore original length */
-            IX_OSAL_MBUF_MLEN(mbufPtr) = IX_OSAL_MBUF_PKT_LEN(mbufPtr) =
-                ( IX_OSAL_MBUF_ALLOCATED_BUFF_LEN(mbufPtr) -
-                 (IX_OSAL_MBUF_MDATA(mbufPtr) - (UINT8 *)IX_OSAL_MBUF_ALLOCATED_BUFF_DATA(mbufPtr)) );
-        }
-
-        /* replenish from here */
-        if (ixEthAccPortRxFreeReplenish(portId, mbufPtr) != IX_ETH_ACC_SUCCESS)
-        {
-                IX_ETH_ACC_FATAL_LOG("ixEthRxFrameProcess: Failed to replenish with filtered frame\
-                                      on port %d\n", portId, 0, 0, 0, 0, 0);
-        }
-
-        RX_STATS_INC(portId, rxFiltered);
-
-        /* indicate that frame should not be subjected to further processing */
-        return false;
-    }
-
-    return true;
-}
-
-
-/**
- * @fn ixEthRxFrameQMCallback
- *
- * @brief receive callback for Frame receive Q from NPE
- *
- * Frames are passed one-at-a-time to the user
- *
- * @param @ref IxQMgrCallback
- *
- * @return none
- *
- * @internal
- *
- * Design note : while processing the entry X, entry X+1 is preloaded
- * into memory to reduce the number of stall cycles
- *
- */
-void ixEthRxFrameQMCallback(IxQMgrQId qId, IxQMgrCallbackId callbackId)
-{
-    IX_OSAL_MBUF    *mbufPtr;
-    IX_OSAL_MBUF    *nextMbufPtr;
-    UINT32     qEntry;
-    UINT32     nextQEntry;
-    UINT32     *qEntryPtr;
-    UINT32     portId;
-    UINT32     destPortId;
-    UINT32     npeId;
-    UINT32     rxQReadStatus;
-
-    /*
-     * Design note : entries are read in a buffer, This buffer contains
-     * an extra zeroed entry so the loop will
-     * always terminate on a null entry, whatever the result of Burst read is.
-     */
-    UINT32 rxQEntry[IX_ETH_ACC_MAX_RX_FRAME_CONSUME_PER_CALLBACK + 1];
-
-    /*
-     * Indication of the number of times the callback is used.
-     */
-    IX_ETH_ACC_STATS_INC(ixEthAccDataStats.rxCallbackCounter);
-
-    do
-    {
-	/*
-	 * Indication of the number of times the queue is drained
-	 */
-	IX_ETH_ACC_STATS_INC(ixEthAccDataStats.rxCallbackBurstRead);
-
-	/* ensure the last entry of the array contains a zeroed value */
-	qEntryPtr = rxQEntry;
-	qEntryPtr[IX_ETH_ACC_MAX_RX_FRAME_CONSUME_PER_CALLBACK] = 0;
-
-	rxQReadStatus = ixQMgrQBurstRead(qId,
-		 IX_ETH_ACC_MAX_RX_FRAME_CONSUME_PER_CALLBACK,
-		 qEntryPtr);
-
-#ifndef NDEBUG
-	if ((rxQReadStatus != IX_QMGR_Q_UNDERFLOW)
-	    && (rxQReadStatus != IX_SUCCESS))
-	{
-	    ixEthAccDataStats.unexpectedError++;
-	    /*major error*/
-	    IX_ETH_ACC_FATAL_LOG(
-		"ixEthRxFrameQMCallback:Error: %u\n",
-		(UINT32)rxQReadStatus, 0, 0, 0, 0, 0);
-	    return;
-	}
-#endif
-
-	/* convert and preload the next entry
-	 * (the conversion function takes care about null pointers which
-	 * are used to mark the end of the loop)
-	 */
-	nextQEntry = *qEntryPtr;
-	nextMbufPtr = ixEthAccEntryFromQConvert(nextQEntry,
-			  IX_ETHNPE_QM_Q_RXENET_ADDR_MASK);
-
-	while(nextQEntry != 0)
-	{
-	    /* get the next entry */
-	    qEntry = nextQEntry;
-	    mbufPtr = nextMbufPtr;
-
-#ifndef NDEBUG
-	    if (mbufPtr == NULL)
-	    {
-		ixEthAccDataStats.unexpectedError++;
-		IX_ETH_ACC_FATAL_LOG(
-		    "ixEthRxFrameQMCallback: Null Mbuf Ptr\n",
-		    0, 0, 0, 0, 0, 0);
-		return;
-	    }
-#endif
-
-	    /* convert the next entry
-	     * (the conversion function takes care about null pointers which
-	     * are used to mark the end of the loop)
-	     */
-	    nextQEntry = *(++qEntryPtr);
-	    nextMbufPtr = ixEthAccEntryFromQConvert(nextQEntry,
-			      IX_ETHNPE_QM_Q_RXENET_ADDR_MASK);
-
-	    /*
-	     * Get Port and Npe ID from message.
-	     */
-	    npeId = ((IX_ETHNPE_QM_Q_RXENET_NPEID_MASK &
-		      qEntry) >> IX_ETHNPE_QM_Q_FIELD_NPEID_R);
-	    portId = IX_ETH_ACC_NPE_TO_PORT_ID(npeId);
-
-	    /* process frame, check the return code and skip the remaining of
-	     * the loop if the frame is to be filtered out
-	     */
-            if (ixEthRxFrameProcess(portId, mbufPtr))
-            {
-	        /* destination portId for this packet */
-	        destPortId = IX_ETHACC_NE_DESTPORTID(mbufPtr);
-
-                if (destPortId != IX_ETH_DB_UNKNOWN_PORT)
-                {
-                    destPortId = IX_ETH_DB_NPE_LOGICAL_ID_TO_PORT_ID(destPortId);
-                }
-
-	        /* test if QoS is enabled in ethAcc
-	        */
-	        if (ixEthAccDataInfo.schDiscipline == FIFO_PRIORITY)
-	        {
-		    /* check if there is a higher priority queue
-		    * which may require processing and then process it.
-		    */
-		    if (ixEthAccDataInfo.higherPriorityQueue[qId] < IX_QMGR_MAX_NUM_QUEUES)
-		    {
-		        ixEthRxFrameQMCallback(ixEthAccDataInfo.higherPriorityQueue[qId],
-					    callbackId);
-		    }
-	        }
-
-	        /*
-	        * increment priority stats
-	        */
-	        RX_STATS_INC(portId,rxPriority[IX_ETHACC_NE_QOS(mbufPtr)]);
-
-	        /*
-	        * increment callback count stats
-	        */
-	        RX_STATS_INC(portId,rxFrameClientCallback);
-
-	        /*
-	        * Call user level callback.
-	        */
-	        ixEthAccPortData[portId].ixEthAccRxData.rxCallbackFn(
-		    ixEthAccPortData[portId].ixEthAccRxData.rxCallbackTag,
-		    mbufPtr,
-		    destPortId);
-            }
-	}
-    } while (rxQReadStatus == IX_SUCCESS);
-}
-
-/**
- * @fn ixEthRxMultiBufferQMCallback
- *
- * @brief receive callback for Frame receive Q from NPE
- *
- * Frames are passed as an array to the user
- *
- * @param @ref IxQMgrCallback
- *
- * @return none
- *
- * @internal
- *
- * Design note : while processing the entry X, entry X+1 is preloaded
- * into memory to reduce the number of stall cycles
- *
- */
-void ixEthRxMultiBufferQMCallback(IxQMgrQId qId, IxQMgrCallbackId callbackId)
-{
-    IX_OSAL_MBUF    *mbufPtr;
-    IX_OSAL_MBUF    *nextMbufPtr;
-    UINT32     qEntry;
-    UINT32     nextQEntry;
-    UINT32     *qEntryPtr;
-    UINT32     portId;
-    UINT32     npeId;
-    UINT32     rxQReadStatus;
-    /*
-     * Design note : entries are read in a static buffer, This buffer contains
-     * an extra zeroed entry so the loop will
-     * always terminate on a null entry, whatever the result of Burst read is.
-     */
-    static UINT32 rxQEntry[IX_ETH_ACC_MAX_RX_FRAME_CONSUME_PER_CALLBACK + 1];
-    static IX_OSAL_MBUF *rxMbufPortArray[IX_ETH_ACC_NUMBER_OF_PORTS][IX_ETH_ACC_MAX_RX_FRAME_CONSUME_PER_CALLBACK + 1];
-    IX_OSAL_MBUF **rxMbufPtr[IX_ETH_ACC_NUMBER_OF_PORTS];
-
-    for (portId = 0; portId < IX_ETH_ACC_NUMBER_OF_PORTS; portId++)
-    {
-	rxMbufPtr[portId] = rxMbufPortArray[portId];
-    }
-
-    /*
-     * Indication of the number of times the callback is used.
-     */
-    IX_ETH_ACC_STATS_INC(ixEthAccDataStats.rxCallbackCounter);
-
-    do
-    {
-	/*
-	 * Indication of the number of times the queue is drained
-	 */
-	IX_ETH_ACC_STATS_INC(ixEthAccDataStats.rxCallbackBurstRead);
-
-	/* ensure the last entry of the array contains a zeroed value */
-	qEntryPtr = rxQEntry;
-	qEntryPtr[IX_ETH_ACC_MAX_RX_FRAME_CONSUME_PER_CALLBACK] = 0;
-
-	rxQReadStatus = ixQMgrQBurstRead(qId,
-		 IX_ETH_ACC_MAX_RX_FRAME_CONSUME_PER_CALLBACK,
-		 qEntryPtr);
-
-#ifndef NDEBUG
-	if ((rxQReadStatus != IX_QMGR_Q_UNDERFLOW)
-	    && (rxQReadStatus != IX_SUCCESS))
-	{
-	    ixEthAccDataStats.unexpectedError++;
-	    /*major error*/
-	    IX_ETH_ACC_FATAL_LOG(
-		"ixEthRxFrameMultiBufferQMCallback:Error: %u\n",
-		(UINT32)rxQReadStatus, 0, 0, 0, 0, 0);
-	    return;
-	}
-#endif
-
-	/* convert and preload the next entry
-	 * (the conversion function takes care about null pointers which
-	 * are used to mark the end of the loop)
-	 */
-	nextQEntry = *qEntryPtr;
-	nextMbufPtr = ixEthAccEntryFromQConvert(nextQEntry,
-			  IX_ETHNPE_QM_Q_RXENET_ADDR_MASK);
-
-	while(nextQEntry != 0)
-	{
-	    /* get the next entry */
-	    qEntry = nextQEntry;
-	    mbufPtr = nextMbufPtr;
-
-#ifndef NDEBUG
-	    if (mbufPtr == NULL)
-	    {
-		ixEthAccDataStats.unexpectedError++;
-		IX_ETH_ACC_FATAL_LOG(
-		    "ixEthRxFrameMultiBufferQMCallback:Error: Null Mbuf Ptr\n",
-		    0, 0, 0, 0, 0, 0);
-		return;
-	    }
-#endif
-
-	    /* convert the next entry
-	     * (the conversion function takes care about null pointers which
-	     * are used to mark the end of the loop)
-	     */
-	    nextQEntry = *(++qEntryPtr);
-	    nextMbufPtr = ixEthAccEntryFromQConvert(nextQEntry,
-			      IX_ETHNPE_QM_Q_RXENET_ADDR_MASK);
-
-	    /*
-	     * Get Port and Npe ID from message.
-	     */
-	    npeId = ((IX_ETHNPE_QM_Q_RXENET_NPEID_MASK &
-		      qEntry) >>
-		     IX_ETHNPE_QM_Q_FIELD_NPEID_R);
-	    portId = IX_ETH_ACC_NPE_TO_PORT_ID(npeId);
-
-	    /* skip the remaining of the loop if the frame is
-	     * to be filtered out
-	     */
-	    if (ixEthRxFrameProcess(portId, mbufPtr))
-	    {
-		/* store a mbuf pointer in an array */
-		*rxMbufPtr[portId]++ = mbufPtr;
-
-		/*
-		 * increment priority stats
-		 */
-		RX_STATS_INC(portId,rxPriority[IX_ETHACC_NE_QOS(mbufPtr)]);
-	    }
-
-	    /* test for QoS enabled in ethAcc */
-	    if (ixEthAccDataInfo.schDiscipline == FIFO_PRIORITY)
-	    {
-		/* check if there is a higher priority queue
-		 * which may require processing and then process it.
-		 */
-		if (ixEthAccDataInfo.higherPriorityQueue[qId] < IX_QMGR_MAX_NUM_QUEUES)
-		{
-		    ixEthRxMultiBufferQMCallback(ixEthAccDataInfo.higherPriorityQueue[qId],
-						 callbackId);
-		}
-	    }
-	}
-
-	/* check if any of the the arrays contains any entry */
-	for (portId = 0; portId < IX_ETH_ACC_NUMBER_OF_PORTS; portId++)
-	{
-	    if (rxMbufPtr[portId] != rxMbufPortArray[portId])
-	    {
-		/* add a last NULL pointer at the end of the
-		 * array of mbuf pointers
-		 */
-		*rxMbufPtr[portId] = NULL;
-
-		/*
-		 * increment callback count stats
-		 */
-		RX_STATS_INC(portId,rxFrameClientCallback);
-
-		/*
-		 * Call user level callback with an array of
-		 * buffers (NULL terminated)
-		 */
-		ixEthAccPortData[portId].ixEthAccRxData.
-		    rxMultiBufferCallbackFn(
-			    ixEthAccPortData[portId].ixEthAccRxData.
-			           rxMultiBufferCallbackTag,
-			    rxMbufPortArray[portId]);
-
-		/* reset the buffer pointer to the beginning of
-		 * the array
-		 */
-		rxMbufPtr[portId] = rxMbufPortArray[portId];
-	    }
-	}
-
-    } while (rxQReadStatus == IX_SUCCESS);
-}
-
-
-/**
- * @brief  rxFree low event handler
- *
- */
-void ixEthRxFreeQMCallback(IxQMgrQId qId, IxQMgrCallbackId callbackId)
-{
-    IxEthAccPortId	portId = (IxEthAccPortId) callbackId;
-    int		        lockVal;
-    UINT32		maxQWritesToPerform = IX_ETH_ACC_MAX_RX_FREE_BUFFERS_LOAD;
-    IX_STATUS	        qStatus = IX_SUCCESS;
-
-    /*
-     * We have reached a low threshold on one of the Rx Free Qs
-     */
-
-    /*note that due to the fact that we are working off an Empty threshold, this callback
-      need only write a single entry to the Rx Free queue in order to re-arm the notification
-    */
-
-    RX_STATS_INC(portId,rxFreeLowCallback);
-
-    /*
-     * Get buffers from approprite S/W Rx freeBufferList Q.
-     */
-
-#ifndef NDEBUG
-    if (!IX_ETH_ACC_IS_PORT_VALID(portId))
-    {
-	ixEthAccDataStats.unexpectedError++;
-	IX_ETH_ACC_FATAL_LOG(
-	    "ixEthRxFreeQMCallback:Error: Invalid Port 0x%08X\n",
-	    portId, 0, 0, 0, 0, 0);
-	return;
-    }
-#endif
-    IX_ETH_ACC_DATA_PLANE_LOCK(lockVal);
-    if (IX_ETH_ACC_DATAPLANE_IS_Q_EMPTY(ixEthAccPortData[portId].
-					ixEthAccRxData.freeBufferList))
-    {
-	/*
-	 * Turn off Q callback notification for Q in Question.
-	 */
-	qStatus = ixQMgrNotificationDisable(
-	    IX_ETH_ACC_PORT_TO_RX_FREE_Q_ID(portId));
-
-
-	IX_ETH_ACC_DATA_PLANE_UNLOCK(lockVal);
-
-	if (qStatus != IX_SUCCESS)
-	{
-	    RX_INC(portId,rxUnexpectedError);
-	    IX_ETH_ACC_FATAL_LOG(
-		"ixEthRxFreeQMCallback:Error: unexpected QM status 0x%08X\n",
-		qStatus, 0, 0, 0, 0, 0);
-	    return;
-	}
-    }
-    else
-    {
-	IX_ETH_ACC_DATA_PLANE_UNLOCK(lockVal);
-	/*
-	 * Load the H/W Q with buffers from the s/w Q.
-	 */
-
-	do
-	{
-	    /*
-	     * Consume Q entries. - Note Q contains Physical addresss,
-	     * and have already been flushed to memory,
-	     * And endianess converted if required.
-	     */
-	    if (ixEthAccRxFreeFromSwQ(portId) != IX_SUCCESS)
-	    {
-		/*
-		 * No more entries in s/w Q.
-		 * Turn off Q callback indication
-		 */
-
-		IX_ETH_ACC_DATA_PLANE_LOCK(lockVal);
-		if (IX_ETH_ACC_DATAPLANE_IS_Q_EMPTY(ixEthAccPortData[portId].
-		    ixEthAccRxData.freeBufferList))
-		{
-		    qStatus = ixQMgrNotificationDisable(
-			IX_ETH_ACC_PORT_TO_RX_FREE_Q_ID(portId));
-		}
-		IX_ETH_ACC_DATA_PLANE_UNLOCK(lockVal);
-		break;
-	    }
-	}
-	while (--maxQWritesToPerform);
-    }
-}
-/**
- * @fn Tx queue low event handler
- *
- */
-void
-ixEthTxFrameQMCallback(IxQMgrQId qId, IxQMgrCallbackId callbackId)
-{
-    IxEthAccPortId portId = (IxEthAccPortId) callbackId;
-    int		   lockVal;
-    UINT32	   maxQWritesToPerform = IX_ETH_ACC_MAX_TX_FRAME_TX_CONSUME_PER_CALLBACK;
-    IX_STATUS	   qStatus = IX_SUCCESS;
-    IxEthAccTxPriority highestPriority;
-
-
-    /*
-     * We have reached a low threshold on the Tx Q, and are being asked to
-     * supply a buffer for transmission from our S/W TX queues
-     */
-    TX_STATS_INC(portId,txLowThreshCallback);
-
-    /*
-     * Get buffers from approprite Q.
-     */
-
-#ifndef NDEBUG
-    if (!IX_ETH_ACC_IS_PORT_VALID(portId))
-    {
-	ixEthAccDataStats.unexpectedError++;
-	IX_ETH_ACC_FATAL_LOG(
-	    "ixEthTxFrameQMCallback:Error: Invalid Port 0x%08X\n",
-	    portId, 0, 0, 0, 0, 0);
-	return;
-    }
-#endif
-
-    do
-    {
-	/*
-	 * Consume Q entries. - Note Q contains Physical addresss,
-	 * and have already been flushed to memory,
-	 * and endianess already sone if required.
-	 */
-
-	IX_ETH_ACC_DATA_PLANE_LOCK(lockVal);
-
-	if(ixEthAccTxSwQHighestPriorityGet(portId, &highestPriority) ==
-	   IX_ETH_ACC_FAIL)
-	{
-	    /*
-	     * No more entries in s/w Q.
-	     * Turn off Q callback indication
-	     */
-	    qStatus = ixQMgrNotificationDisable(
-		IX_ETH_ACC_PORT_TO_TX_Q_ID(portId));
-
-	    IX_ETH_ACC_DATA_PLANE_UNLOCK(lockVal);
-
-	    if (qStatus != IX_SUCCESS)
-	    {
-		ixEthAccDataStats.unexpectedError++;
-		IX_ETH_ACC_FATAL_LOG(
-		    "ixEthTxFrameQMCallback:Error: unexpected QM status 0x%08X\n",
-		    qStatus, 0, 0, 0, 0, 0);
-	    }
-
-	    return;
-	}
-	else
-	{
-	    IX_ETH_ACC_DATA_PLANE_UNLOCK(lockVal);
-	    if (ixEthAccTxFromSwQ(portId,highestPriority)!=IX_SUCCESS)
-	    {
-                /* nothing left in the sw queue or the hw queues are
-                * full. There is no point to continue to drain the
-                * sw queues
-                */
-		return;
-	    }
-	}
-    }
-    while (--maxQWritesToPerform);
-}
-
-/**
- * @brief TxDone event handler
- *
- * Design note : while processing the entry X, entry X+1 is preloaded
- * into memory to reduce the number of stall cycles
- *
- */
-
-void
-ixEthTxFrameDoneQMCallback(IxQMgrQId qId, IxQMgrCallbackId callbackId)
-{
-    IX_OSAL_MBUF    *mbufPtr;
-    UINT32     qEntry;
-    UINT32     *qEntryPtr;
-    UINT32     txDoneQReadStatus;
-    UINT32     portId;
-    UINT32     npeId;
-
-    /*
-     * Design note : entries are read in a static buffer, This buffer contains
-     * an extra entyry (which is zeroed by the compiler), so the loop will
-     * always terminate on a null entry, whatever the result of Burst read is.
-     */
-    static UINT32 txDoneQEntry[IX_ETH_ACC_MAX_TX_FRAME_DONE_CONSUME_PER_CALLBACK + 1];
-
-    /*
-     * Indication that Tx frames have been transmitted from the NPE.
-     */
-
-    IX_ETH_ACC_STATS_INC(ixEthAccDataStats.txDoneCallbackCounter);
-
-    do{
-	qEntryPtr = txDoneQEntry;
-	txDoneQReadStatus = ixQMgrQBurstRead(IX_ETH_ACC_TX_FRAME_DONE_ETH_Q,
-		     IX_ETH_ACC_MAX_TX_FRAME_DONE_CONSUME_PER_CALLBACK,
-		     qEntryPtr);
-
-#ifndef NDEBUG
-	if (txDoneQReadStatus != IX_QMGR_Q_UNDERFLOW
-	    && (txDoneQReadStatus != IX_SUCCESS))
-	{
-	    /*major error*/
-	    ixEthAccDataStats.unexpectedError++;
-	    IX_ETH_ACC_FATAL_LOG(
-		"ixEthTxFrameDoneQMCallback:Error: %u\n",
-		(UINT32)txDoneQReadStatus, 0, 0, 0, 0, 0);
-	    return;
-	}
-#endif
-
-	qEntry = *qEntryPtr;
-
-	while(qEntry != 0)
-	{
-	    mbufPtr = ixEthAccEntryFromQConvert(qEntry,
-		      IX_ETHNPE_QM_Q_TXENET_ADDR_MASK);
-
-#ifndef NDEBUG
-	    if (mbufPtr == NULL)
-	    {
-		ixEthAccDataStats.unexpectedError++;
-		IX_ETH_ACC_FATAL_LOG(
-		    "ixEthTxFrameDoneQMCallback:Error: Null Mbuf Ptr\n",
-		    0, 0, 0, 0, 0, 0);
-		return;
-	    }
-#endif
-
-	    /* endianness conversions and stats updates */
-	    ixEthAccMbufFromTxQ(mbufPtr);
-
-	    /*
-	     * Get NPE id from message, then convert to portId.
-	     */
-	    npeId = ((IX_ETHNPE_QM_Q_TXENETDONE_NPEID_MASK &
-		       qEntry) >>
-		      IX_ETHNPE_QM_Q_FIELD_NPEID_R);
-	    portId = IX_ETH_ACC_NPE_TO_PORT_ID(npeId);
-
-#ifndef NDEBUG
-	    /* Prudent to at least check the port is within range */
-	    if (portId >= IX_ETH_ACC_NUMBER_OF_PORTS)
-	    {
-		ixEthAccDataStats.unexpectedError++;
-		IX_ETH_ACC_FATAL_LOG(
-		    "ixEthTxFrameDoneQMCallback: Illegal port: %u\n",
-		    (UINT32)portId, 0, 0, 0, 0, 0);
-		return;
-	    }
-#endif
-
-	    TX_STATS_INC(portId,txDoneClientCallback);
-
-	    /*
-	     * Call user level callback.
-	     */
-	    ixEthAccPortData[portId].ixEthAccTxData.txBufferDoneCallbackFn(
-		ixEthAccPortData[portId].ixEthAccTxData.txCallbackTag,
-		mbufPtr);
-
-	    /* move to next queue entry */
-	    qEntry = *(++qEntryPtr);
-
-	}
-    } while( txDoneQReadStatus == IX_SUCCESS );
-}
-
-IX_ETH_ACC_PUBLIC
-void ixEthAccDataPlaneShow(void)
-{
-    UINT32 numTx0Entries;
-    UINT32 numTx1Entries;
-    UINT32 numTxDoneEntries;
-    UINT32 numRxEntries;
-    UINT32 numRxFree0Entries;
-    UINT32 numRxFree1Entries;
-    UINT32 portId;
-#ifdef __ixp46X
-    UINT32 numTx2Entries;
-    UINT32 numRxFree2Entries;
-#endif
-#ifndef NDEBUG
-    UINT32 priority;
-    UINT32 numBuffersInRx=0;
-    UINT32 numBuffersInTx=0;
-    UINT32 numBuffersInSwQ=0;
-    UINT32 totalBuffers=0;
-    UINT32 rxFreeCallbackCounter = 0;
-    UINT32 txCallbackCounter = 0;
-#endif
-    UINT32 key;
-
-    /* snapshot of stats */
-    IxEthAccTxDataStats tx[IX_ETH_ACC_NUMBER_OF_PORTS];
-    IxEthAccRxDataStats rx[IX_ETH_ACC_NUMBER_OF_PORTS];
-    IxEthAccDataPlaneStats stats;
-
-    if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED())
-    {
-	return;
-    }
-
-    /* get a reliable snapshot */
-    key = ixOsalIrqLock();
-
-    numTx0Entries = 0;
-    ixQMgrQNumEntriesGet(IX_ETH_ACC_TX_FRAME_ENET0_Q, &numTx0Entries);
-    numTx1Entries = 0;
-    ixQMgrQNumEntriesGet(IX_ETH_ACC_TX_FRAME_ENET1_Q, &numTx1Entries);
-    numTxDoneEntries = 0;
-    ixQMgrQNumEntriesGet( IX_ETH_ACC_TX_FRAME_DONE_ETH_Q, &numTxDoneEntries);
-    numRxEntries = 0;
-    ixEthAccQMgrRxQEntryGet(&numRxEntries);
-    numRxFree0Entries = 0;
-    ixQMgrQNumEntriesGet(IX_ETH_ACC_RX_FREE_BUFF_ENET0_Q, &numRxFree0Entries);
-    numRxFree1Entries = 0;
-    ixQMgrQNumEntriesGet(IX_ETH_ACC_RX_FREE_BUFF_ENET1_Q, &numRxFree1Entries);
-
-#ifdef __ixp46X
-    numTx2Entries = 0;
-    ixQMgrQNumEntriesGet(IX_ETH_ACC_TX_FRAME_ENET2_Q, &numTx2Entries);
-    numRxFree2Entries = 0;
-    ixQMgrQNumEntriesGet(IX_ETH_ACC_RX_FREE_BUFF_ENET2_Q, &numRxFree2Entries);
-#endif
-
-    for(portId=IX_ETH_PORT_1; portId < IX_ETH_ACC_NUMBER_OF_PORTS; portId++)
-    {
-	memcpy(&tx[portId],
-	       &ixEthAccPortData[portId].ixEthAccTxData.stats,
-	       sizeof(tx[portId]));
-	memcpy(&rx[portId],
-	       &ixEthAccPortData[portId].ixEthAccRxData.stats,
-	       sizeof(rx[portId]));
-    }
-    memcpy(&stats, &ixEthAccDataStats, sizeof(stats));
-
-    ixOsalIrqUnlock(key);
-
-#ifdef NDEBUG
-    printf("Detailed statistics collection not supported in this load\n");
-#endif
-
-    /* print snapshot */
-    for(portId=0; portId < IX_ETH_ACC_NUMBER_OF_PORTS; portId++)
-    {
-        /* If not IXP42X A0 stepping, proceed to check for existence of coprocessors */
-        if ((IX_FEATURE_CTRL_SILICON_TYPE_A0 !=
-	     (ixFeatureCtrlProductIdRead() & IX_FEATURE_CTRL_SILICON_STEPPING_MASK))
-	    || (IX_FEATURE_CTRL_DEVICE_TYPE_IXP42X != ixFeatureCtrlDeviceRead ()))
-        {
-                if ((IX_ETH_PORT_1 == portId) &&
-                    (ixFeatureCtrlComponentCheck(IX_FEATURECTRL_ETH0) ==
-                     IX_FEATURE_CTRL_COMPONENT_DISABLED))
-                {
-                   continue ;
-                }
-                if ((IX_ETH_PORT_2 == portId) &&
-                    (ixFeatureCtrlComponentCheck(IX_FEATURECTRL_ETH1) ==
-                     IX_FEATURE_CTRL_COMPONENT_DISABLED))
-                {
-                    continue ;
-                }
-                if ((IX_ETH_PORT_3 == portId) &&
-                    (ixFeatureCtrlComponentCheck(IX_FEATURECTRL_NPEA_ETH) ==
-                     IX_FEATURE_CTRL_COMPONENT_DISABLED))
-                {
-                    continue ;
-                }
-        }
-
-	printf("PORT %u --------------------------------\n",
-	       portId);
-#ifndef NDEBUG
-	printf("Tx Done Frames                : %u\n",
-	       tx[portId].txDoneClientCallback +
-	       tx[portId].txDoneSwQDuringDisable +
-	       tx[portId].txDoneDuringDisable);
-	printf("Tx Frames                     : %u\n",
-	       tx[portId].txQOK + tx[portId].txQDelayed);
-	printf("Tx H/W Q Added OK             : %u\n",
-	       tx[portId].txQOK);
-	printf("Tx H/W Q Delayed              : %u\n",
-	       tx[portId].txQDelayed);
-	printf("Tx From S/W Q Added OK        : %u\n",
-	       tx[portId].txFromSwQOK);
-	printf("Tx From S/W Q Delayed         : %u\n",
-	       tx[portId].txFromSwQDelayed);
-	printf("Tx Overflow                   : %u\n",
-	       tx[portId].txOverflow);
-	printf("Tx Mutual Lock                : %u\n",
-	       tx[portId].txLock);
-	printf("Tx Late Ntf Enabled           : %u\n",
-	       tx[portId].txLateNotificationEnabled);
-	printf("Tx Low Thresh CB              : %u\n",
-	       tx[portId].txLowThreshCallback);
-	printf("Tx Done from H/W Q (Disable)  : %u\n",
-	       tx[portId].txDoneDuringDisable);
-	printf("Tx Done from S/W Q (Disable)  : %u\n",
-	       tx[portId].txDoneSwQDuringDisable);
-	for (priority = IX_ETH_ACC_TX_PRIORITY_0;
-	     priority <= IX_ETH_ACC_TX_PRIORITY_7;
-	     priority++)
-	{
-	    if (tx[portId].txPriority[priority])
-	    {
-		printf("Tx Priority %u                 : %u\n",
-		       priority,
-		       tx[portId].txPriority[priority]);
-	    }
-	}
-#endif
-	printf("Tx unexpected errors          : %u (should be 0)\n",
-	       tx[portId].txUnexpectedError);
-
-#ifndef NDEBUG
-	printf("Rx Frames                     : %u\n",
-	       rx[portId].rxFrameClientCallback +
-	       rx[portId].rxSwQDuringDisable+
-	       rx[portId].rxDuringDisable);
-	printf("Rx Free Replenish             : %u\n",
-	       rx[portId].rxFreeRepOK + rx[portId].rxFreeRepDelayed);
-	printf("Rx Free H/W Q Added OK        : %u\n",
-	       rx[portId].rxFreeRepOK);
-	printf("Rx Free H/W Q Delayed         : %u\n",
-	       rx[portId].rxFreeRepDelayed);
-	printf("Rx Free From S/W Q Added OK   : %u\n",
-	       rx[portId].rxFreeRepFromSwQOK);
-	printf("Rx Free From S/W Q Delayed    : %u\n",
-	       rx[portId].rxFreeRepFromSwQDelayed);
-	printf("Rx Free Overflow              : %u\n",
-	       rx[portId].rxFreeOverflow);
-	printf("Rx Free Mutual Lock           : %u\n",
-	       rx[portId].rxFreeLock);
-	printf("Rx Free Late Ntf Enabled      : %u\n",
-	       rx[portId].rxFreeLateNotificationEnabled);
-	printf("Rx Free Low CB                : %u\n",
-	       rx[portId].rxFreeLowCallback);
-	printf("Rx From H/W Q (Disable)       : %u\n",
-	       rx[portId].rxDuringDisable);
-	printf("Rx From S/W Q (Disable)       : %u\n",
-	       rx[portId].rxSwQDuringDisable);
-	printf("Rx unlearned Mac Address      : %u\n",
-	       rx[portId].rxUnlearnedMacAddress);
-        printf("Rx Filtered (Rx => RxFree)    : %u\n",
-            rx[portId].rxFiltered);
-
-	for (priority = IX_ETH_ACC_TX_PRIORITY_0;
-	     priority <= IX_ETH_ACC_TX_PRIORITY_7;
-	     priority++)
-	{
-	    if (rx[portId].rxPriority[priority])
-	    {
-		printf("Rx Priority %u                 : %u\n",
-		       priority,
-		       rx[portId].rxPriority[priority]);
-	    }
-	}
-#endif
-	printf("Rx unexpected errors          : %u (should be 0)\n",
-	       rx[portId].rxUnexpectedError);
-
-#ifndef NDEBUG
-	numBuffersInTx = tx[portId].txQOK +
-	    tx[portId].txQDelayed -
-	    tx[portId].txDoneClientCallback -
-	    tx[portId].txDoneSwQDuringDisable -
-	    tx[portId].txDoneDuringDisable;
-
-	printf("# Tx Buffers currently for transmission : %u\n",
-	       numBuffersInTx);
-
-	numBuffersInRx = rx[portId].rxFreeRepOK +
-	    rx[portId].rxFreeRepDelayed -
-	    rx[portId].rxFrameClientCallback -
-	    rx[portId].rxSwQDuringDisable -
-	    rx[portId].rxDuringDisable;
-
-	printf("# Rx Buffers currently for reception    : %u\n",
-	       numBuffersInRx);
-
-	totalBuffers += numBuffersInRx + numBuffersInTx;
-#endif
-    }
-
-    printf("---------------------------------------\n");
-
-#ifndef NDEBUG
-    printf("\n");
-    printf("Mbufs :\n");
-    printf("Tx Unchained mbufs            : %u\n",
-	   stats.unchainedTxMBufs);
-    printf("Tx Chained bufs               : %u\n",
-	   stats.chainedTxMBufs);
-    printf("TxDone Unchained mbufs        : %u\n",
-	   stats.unchainedTxDoneMBufs);
-    printf("TxDone Chained bufs           : %u\n",
-	   stats.chainedTxDoneMBufs);
-    printf("RxFree Unchained mbufs        : %u\n",
-	   stats.unchainedRxFreeMBufs);
-    printf("RxFree Chained bufs           : %u\n",
-	   stats.chainedRxFreeMBufs);
-    printf("Rx Unchained mbufs            : %u\n",
-	   stats.unchainedRxMBufs);
-    printf("Rx Chained bufs               : %u\n",
-	   stats.chainedRxMBufs);
-
-    printf("\n");
-    printf("Software queue usage :\n");
-    printf("Buffers added to S/W Q        : %u\n",
-	   stats.addToSwQ);
-    printf("Buffers removed from S/W Q    : %u\n",
-	   stats.removeFromSwQ);
-
-    printf("\n");
-    printf("Hardware queues callbacks :\n");
-
-    for(portId=0; portId < IX_ETH_ACC_NUMBER_OF_PORTS; portId++)
-    {
-	rxFreeCallbackCounter += rx[portId].rxFreeLowCallback;
-	txCallbackCounter += tx[portId].txLowThreshCallback;
-    }
-    printf("Tx Done QM Callback invoked   : %u\n",
-	   stats.txDoneCallbackCounter);
-    printf("Tx QM Callback invoked        : %u\n",
-	   txCallbackCounter);
-    printf("Rx QM Callback invoked        : %u\n",
-	   stats.rxCallbackCounter);
-    printf("Rx QM Callback burst read     : %u\n",
-	   stats.rxCallbackBurstRead);
-    printf("Rx Free QM Callback invoked   : %u\n",
-	   rxFreeCallbackCounter);
-#endif
-    printf("Unexpected errors in CB       : %u (should be 0)\n",
-	   stats.unexpectedError);
-    printf("\n");
-
-    printf("Hardware queues levels :\n");
-    printf("Transmit Port 1 Q             : %u \n",numTx0Entries);
-    printf("Transmit Port 2 Q             : %u \n",numTx1Entries);
-#ifdef __ixp46X
-    printf("Transmit Port 3 Q             : %u \n",numTx2Entries);
-#endif
-    printf("Transmit Done Q               : %u \n",numTxDoneEntries);
-    printf("Receive Q                     : %u \n",numRxEntries);
-    printf("Receive Free Port 1 Q         : %u \n",numRxFree0Entries);
-    printf("Receive Free Port 2 Q         : %u \n",numRxFree1Entries);
-#ifdef __ixp46X
-    printf("Receive Free Port 3 Q         : %u \n",numRxFree2Entries);
-#endif
-
-#ifndef NDEBUG
-    printf("\n");
-    printf("# Total Buffers accounted for : %u\n",
-	   totalBuffers);
-
-    numBuffersInSwQ = ixEthAccDataStats.addToSwQ -
-	ixEthAccDataStats.removeFromSwQ;
-
-    printf("    Buffers in S/W Qs         : %u\n",
-	   numBuffersInSwQ);
-    printf("    Buffers in H/W Qs or NPEs : %u\n",
-	   totalBuffers - numBuffersInSwQ);
-#endif
-
-    printf("Rx QoS Discipline             : %s\n",
-	   (ixEthAccDataInfo.schDiscipline ==
-	    FIFO_PRIORITY ) ? "Enabled" : "Disabled");
-
-    for(portId=0; portId < IX_ETH_ACC_NUMBER_OF_PORTS; portId++)
-    {
-	printf("Tx QoS Discipline port %u      : %s\n",
-	       portId,
-	       (ixEthAccPortData[portId].ixEthAccTxData.schDiscipline ==
-		FIFO_PRIORITY ) ? "Enabled" : "Disabled");
-    }
-    printf("\n");
-}
-
-
-
-
-
diff --git a/drivers/net/npe/IxEthAccMac.c b/drivers/net/npe/IxEthAccMac.c
deleted file mode 100644
index 65113448d2..0000000000
--- a/drivers/net/npe/IxEthAccMac.c
+++ /dev/null
@@ -1,2617 +0,0 @@
-/**
- * @file IxEthAccMac.c
- *
- * @author Intel Corporation
- * @date
- *
- * @brief  MAC control functions
- *
- * Design Notes:
- *
- * @par
- * IXP400 SW Release version 2.0
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * SPDX-License-Identifier:	BSD-3-Clause
- * @par
- * -- End of Copyright Notice --
- */
-
-#include "IxOsal.h"
-#include "IxNpeMh.h"
-#ifdef CONFIG_IXP425_COMPONENT_ETHDB
-#include "IxEthDB.h"
-#endif
-#include "IxEthDBPortDefs.h"
-#include "IxEthNpe.h"
-#include "IxEthAcc.h"
-#include "IxEthAccDataPlane_p.h"
-#include "IxEthAcc_p.h"
-#include "IxEthAccMac_p.h"
-
-/* Maximum number of retries during ixEthAccPortDisable, which
- * is approximately 10 seconds
-*/
-#define IX_ETH_ACC_MAX_RETRY 500
-
-/* Maximum number of retries during ixEthAccPortDisable when expecting
- * timeout
- */
-#define IX_ETH_ACC_MAX_RETRY_TIMEOUT 5
-
-#define IX_ETH_ACC_VALIDATE_PORT_ID(portId) \
-    do                                                           \
-    {                                                            \
-        if(!IX_ETH_ACC_IS_PORT_VALID(portId))   \
-        {                                                        \
-	    return IX_ETH_ACC_INVALID_PORT;                      \
-        }                                                        \
-    } while(0)
-
-PUBLIC IxEthAccMacState ixEthAccMacState[IX_ETH_ACC_NUMBER_OF_PORTS];
-
-PRIVATE UINT32 ixEthAccMacBase[IX_ETH_ACC_NUMBER_OF_PORTS];
-
-/*Forward function declarations*/
-PRIVATE void
-ixEthAccPortDisableRx (IxEthAccPortId portId,
-		       IX_OSAL_MBUF * mBufPtr,
-		       BOOL useMultiBufferCallback);
-
-PRIVATE void
-ixEthAccPortDisableRxAndReplenish (IxEthAccPortId portId,
-				   IX_OSAL_MBUF * mBufPtr,
-				   BOOL useMultiBufferCallback);
-
-PRIVATE void
-ixEthAccPortDisableTxDone (UINT32 cbTag,
-			   IX_OSAL_MBUF *mbuf);
-
-PRIVATE void
-ixEthAccPortDisableTxDoneAndSubmit (UINT32 cbTag,
-				    IX_OSAL_MBUF *mbuf);
-
-PRIVATE void
-ixEthAccPortDisableRxCallback (UINT32 cbTag,
-			       IX_OSAL_MBUF * mBufPtr,
-			       UINT32 learnedPortId);
-
-PRIVATE void
-ixEthAccPortDisableMultiBufferRxCallback (UINT32 cbTag,
-					  IX_OSAL_MBUF **mBufPtr);
-
-PRIVATE IxEthAccStatus
-ixEthAccPortDisableTryTransmit(UINT32 portId);
-
-PRIVATE IxEthAccStatus
-ixEthAccPortDisableTryReplenish(UINT32 portId);
-
-PRIVATE IxEthAccStatus
-ixEthAccPortMulticastMacAddressGet (IxEthAccPortId portId,
-				    IxEthAccMacAddr *macAddr);
-
-PRIVATE IxEthAccStatus
-ixEthAccPortMulticastMacFilterGet (IxEthAccPortId portId,
-				   IxEthAccMacAddr *macAddr);
-
-PRIVATE void
-ixEthAccMacNpeStatsMessageCallback (IxNpeMhNpeId npeId,
-				    IxNpeMhMessage msg);
-
-PRIVATE void
-ixEthAccMacNpeStatsResetMessageCallback (IxNpeMhNpeId npeId,
-					 IxNpeMhMessage msg);
-
-PRIVATE void
-ixEthAccNpeLoopbackMessageCallback (IxNpeMhNpeId npeId,
-				    IxNpeMhMessage msg);
-
-PRIVATE void
-ixEthAccMulticastAddressSet(IxEthAccPortId portId);
-
-PRIVATE BOOL
-ixEthAccMacEqual(IxEthAccMacAddr *macAddr1,
-		 IxEthAccMacAddr *macAddr2);
-
-PRIVATE void
-ixEthAccMacPrint(IxEthAccMacAddr *m);
-
-PRIVATE void
-ixEthAccMacStateUpdate(IxEthAccPortId portId);
-
-IxEthAccStatus
-ixEthAccMacMemInit(void)
-{
-    ixEthAccMacBase[IX_ETH_PORT_1] =
-	(UINT32) IX_OSAL_MEM_MAP(IX_ETH_ACC_MAC_0_BASE,
-				 IX_OSAL_IXP400_ETHA_MAP_SIZE);
-    ixEthAccMacBase[IX_ETH_PORT_2] =
-	(UINT32) IX_OSAL_MEM_MAP(IX_ETH_ACC_MAC_1_BASE,
-				 IX_OSAL_IXP400_ETHB_MAP_SIZE);
-#ifdef __ixp46X
-    ixEthAccMacBase[IX_ETH_PORT_3] =
-	(UINT32) IX_OSAL_MEM_MAP(IX_ETH_ACC_MAC_2_BASE,
-				 IX_OSAL_IXP400_ETH_NPEA_MAP_SIZE);
-    if (ixEthAccMacBase[IX_ETH_PORT_3] == 0)
-    {
-	ixOsalLog(IX_OSAL_LOG_LVL_FATAL,
-		  IX_OSAL_LOG_DEV_STDOUT,
-		  "EthAcc: Could not map MAC I/O memory\n",
-		  0, 0, 0, 0, 0 ,0);
-
-	return IX_ETH_ACC_FAIL;
-    }
-#endif
-
-    if (ixEthAccMacBase[IX_ETH_PORT_1] == 0
-	|| ixEthAccMacBase[IX_ETH_PORT_2] == 0)
-    {
-	ixOsalLog(IX_OSAL_LOG_LVL_FATAL,
-		  IX_OSAL_LOG_DEV_STDOUT,
-		  "EthAcc: Could not map MAC I/O memory\n",
-		  0, 0, 0, 0, 0 ,0);
-
-	return IX_ETH_ACC_FAIL;
-    }
-
-    return IX_ETH_ACC_SUCCESS;
-}
-
-void
-ixEthAccMacUnload(void)
-{
-    IX_OSAL_MEM_UNMAP(ixEthAccMacBase[IX_ETH_PORT_1]);
-    IX_OSAL_MEM_UNMAP(ixEthAccMacBase[IX_ETH_PORT_2]);
-#ifdef __ixp46X
-    IX_OSAL_MEM_UNMAP(ixEthAccMacBase[IX_ETH_PORT_3]);
-    ixEthAccMacBase[IX_ETH_PORT_3] = 0;
-#endif
-    ixEthAccMacBase[IX_ETH_PORT_2] = 0;
-    ixEthAccMacBase[IX_ETH_PORT_1] = 0;
-}
-
-IxEthAccStatus
-ixEthAccPortEnablePriv(IxEthAccPortId portId)
-{
-    IX_ETH_ACC_VALIDATE_PORT_ID(portId);
-
-    if (IX_ETH_ACC_SUCCESS != ixEthAccSingleEthNpeCheck(portId))
-    {
-        IX_ETH_ACC_WARNING_LOG("EthAcc: Unavailable Eth %d: Cannot enable port.\n",(INT32)portId,0,0,0,0,0);
-        return IX_ETH_ACC_SUCCESS ;
-    }
-
-    if (!IX_ETH_IS_PORT_INITIALIZED(portId))
-    {
-        printf("EthAcc: (Mac) cannot enable port %d, port not initialized\n", portId);
-	return (IX_ETH_ACC_PORT_UNINITIALIZED);
-    }
-
-    if (ixEthAccPortData[portId].ixEthAccTxData.txBufferDoneCallbackFn == NULL)
-    {
-        /* TxDone callback not registered */
-        printf("EthAcc: (Mac) cannot enable port %d, TxDone callback not registered\n", portId);
-	return (IX_ETH_ACC_PORT_UNINITIALIZED);
-    }
-
-    if ((ixEthAccPortData[portId].ixEthAccRxData.rxCallbackFn == NULL)
-	&& (ixEthAccPortData[portId].ixEthAccRxData.rxMultiBufferCallbackFn == NULL))
-    {
-        /* Receive callback not registered */
-        printf("EthAcc: (Mac) cannot enable port %d, Rx callback not registered\n", portId);
-	return (IX_ETH_ACC_PORT_UNINITIALIZED);
-    }
-
-    if(!ixEthAccMacState[portId].initDone)
-    {
-        printf("EthAcc: (Mac) cannot enable port %d, MAC address not set\n", portId);
-	return (IX_ETH_ACC_MAC_UNINITIALIZED);
-    }
-
-    /* if the state is being set to what it is already at, do nothing*/
-    if (ixEthAccMacState[portId].enabled)
-    {
-        return IX_ETH_ACC_SUCCESS;
-    }
-
-#ifdef CONFIG_IXP425_COMPONENT_ETHDB
-    /* enable ethernet database for this port */
-    if (ixEthDBPortEnable(portId) != IX_ETH_DB_SUCCESS)
-    {
-        printf("EthAcc: (Mac) cannot enable port %d, EthDB failure\n", portId);
-        return IX_ETH_ACC_FAIL;
-    }
-#endif
-
-    /* set the MAC core registers */
-    REG_WRITE(ixEthAccMacBase[portId],
-	      IX_ETH_ACC_MAC_TX_CNTRL2,
-	      IX_ETH_ACC_TX_CNTRL2_RETRIES_MASK);
-
-    REG_WRITE(ixEthAccMacBase[portId],
-	      IX_ETH_ACC_MAC_RANDOM_SEED,
-	      IX_ETH_ACC_RANDOM_SEED_DEFAULT);
-
-    REG_WRITE(ixEthAccMacBase[portId],
-	      IX_ETH_ACC_MAC_THRESH_P_EMPTY,
-	      IX_ETH_ACC_MAC_THRESH_P_EMPTY_DEFAULT);
-
-    REG_WRITE(ixEthAccMacBase[portId],
-	      IX_ETH_ACC_MAC_THRESH_P_FULL,
-	      IX_ETH_ACC_MAC_THRESH_P_FULL_DEFAULT);
-
-    REG_WRITE(ixEthAccMacBase[portId],
-	      IX_ETH_ACC_MAC_TX_DEFER,
-	      IX_ETH_ACC_MAC_TX_DEFER_DEFAULT);
-
-    REG_WRITE(ixEthAccMacBase[portId],
-	      IX_ETH_ACC_MAC_TX_TWO_DEFER_1,
-	      IX_ETH_ACC_MAC_TX_TWO_DEFER_1_DEFAULT);
-
-    REG_WRITE(ixEthAccMacBase[portId],
-	      IX_ETH_ACC_MAC_TX_TWO_DEFER_2,
-	      IX_ETH_ACC_MAC_TX_TWO_DEFER_2_DEFAULT);
-
-    REG_WRITE(ixEthAccMacBase[portId],
-	      IX_ETH_ACC_MAC_SLOT_TIME,
-	      IX_ETH_ACC_MAC_SLOT_TIME_DEFAULT);
-
-    REG_WRITE(ixEthAccMacBase[portId],
-	      IX_ETH_ACC_MAC_INT_CLK_THRESH,
-	      IX_ETH_ACC_MAC_INT_CLK_THRESH_DEFAULT);
-
-    REG_WRITE(ixEthAccMacBase[portId],
-	      IX_ETH_ACC_MAC_BUF_SIZE_TX,
-	      IX_ETH_ACC_MAC_BUF_SIZE_TX_DEFAULT);
-
-    REG_WRITE(ixEthAccMacBase[portId],
-	      IX_ETH_ACC_MAC_TX_CNTRL1,
-	      IX_ETH_ACC_TX_CNTRL1_DEFAULT);
-
-    REG_WRITE(ixEthAccMacBase[portId],
-	      IX_ETH_ACC_MAC_RX_CNTRL1,
-	      IX_ETH_ACC_RX_CNTRL1_DEFAULT);
-
-    /* set the global state */
-    ixEthAccMacState[portId].portDisableState = ACTIVE;
-    ixEthAccMacState[portId].enabled = true;
-
-    /* rewrite the setup (including mac filtering) depending
-     * on current options
-     */
-    ixEthAccMacStateUpdate(portId);
-
-    return IX_ETH_ACC_SUCCESS;
-}
-
-/*
- * PortDisable local variables. They contain the intermediate steps
- * while the port is being disabled and the buffers being drained out
- * of the NPE.
- */
-typedef void (*IxEthAccPortDisableRx)(IxEthAccPortId portId,
-				      IX_OSAL_MBUF * mBufPtr,
-				      BOOL useMultiBufferCallback);
-static IxEthAccPortRxCallback
-ixEthAccPortDisableFn[IX_ETH_ACC_NUMBER_OF_PORTS];
-static IxEthAccPortMultiBufferRxCallback
-ixEthAccPortDisableMultiBufferFn[IX_ETH_ACC_NUMBER_OF_PORTS];
-static IxEthAccPortDisableRx
-ixEthAccPortDisableRxTable[IX_ETH_ACC_NUMBER_OF_PORTS];
-static UINT32
-ixEthAccPortDisableCbTag[IX_ETH_ACC_NUMBER_OF_PORTS];
-static UINT32
-ixEthAccPortDisableMultiBufferCbTag[IX_ETH_ACC_NUMBER_OF_PORTS];
-
-static IxEthAccPortTxDoneCallback
-ixEthAccPortDisableTxDoneFn[IX_ETH_ACC_NUMBER_OF_PORTS];
-static UINT32
-ixEthAccPortDisableTxDoneCbTag[IX_ETH_ACC_NUMBER_OF_PORTS];
-
-static UINT32
-ixEthAccPortDisableUserBufferCount[IX_ETH_ACC_NUMBER_OF_PORTS];
-
-/*
- * PortDisable private callbacks functions. They handle the user
- * traffic, and the special buffers (one for tx, one for rx) used
- * in portDisable.
- */
-PRIVATE void
-ixEthAccPortDisableTxDone(UINT32 cbTag,
-			  IX_OSAL_MBUF *mbuf)
-{
-    IxEthAccPortId portId = (IxEthAccPortId)cbTag;
-    volatile IxEthAccPortDisableState *txState = &ixEthAccMacState[portId].txState;
-
-    /* check for the special mbuf used in portDisable */
-    if (mbuf == ixEthAccMacState[portId].portDisableTxMbufPtr)
-    {
-        *txState = TRANSMIT_DONE;
-    }
-    else
-    {
-	/* increment the count of user traffic during portDisable */
-	ixEthAccPortDisableUserBufferCount[portId]++;
-
-       /* call client TxDone function */
-        ixEthAccPortDisableTxDoneFn[portId](ixEthAccPortDisableTxDoneCbTag[portId], mbuf);
-    }
-}
-
-PRIVATE IxEthAccStatus
-ixEthAccPortDisableTryTransmit(UINT32 portId)
-{
-    int key;
-    IxEthAccStatus status = IX_ETH_ACC_SUCCESS;
-    volatile IxEthAccPortDisableState *txState = &ixEthAccMacState[portId].txState;
-    /* transmit the special buffer again if it is transmitted
-     * and update the txState
-     * This section is protected because the portDisable context
-     * run an identical code, so the system keeps transmitting at the
-     * maximum rate.
-     */
-    key = ixOsalIrqLock();
-    if (*txState == TRANSMIT_DONE)
-    {
-	IX_OSAL_MBUF *mbufTxPtr = ixEthAccMacState[portId].portDisableTxMbufPtr;
-	*txState = TRANSMIT;
-	status = ixEthAccPortTxFrameSubmit(portId,
-					   mbufTxPtr,
-					   IX_ETH_ACC_TX_DEFAULT_PRIORITY);
-    }
-    ixOsalIrqUnlock(key);
-
-    return status;
-}
-
-PRIVATE void
-ixEthAccPortDisableTxDoneAndSubmit(UINT32 cbTag,
-				   IX_OSAL_MBUF *mbuf)
-{
-    IxEthAccPortId portId = (IxEthAccPortId)cbTag;
-
-    /* call the callback which forwards the traffic to the client */
-    ixEthAccPortDisableTxDone(cbTag, mbuf);
-
-    /* try to transmit the buffer used in portDisable
-     * if seen in TxDone
-     */
-    ixEthAccPortDisableTryTransmit(portId);
-}
-
-PRIVATE void
-ixEthAccPortDisableRx (IxEthAccPortId portId,
-		       IX_OSAL_MBUF * mBufPtr,
-		       BOOL useMultiBufferCallback)
-{
-    volatile IxEthAccPortDisableState *rxState = &ixEthAccMacState[portId].rxState;
-    IX_OSAL_MBUF *mNextPtr;
-
-    while (mBufPtr)
-    {
-	mNextPtr = IX_OSAL_MBUF_NEXT_BUFFER_IN_PKT_PTR(mBufPtr);
-	IX_OSAL_MBUF_NEXT_BUFFER_IN_PKT_PTR(mBufPtr) = NULL;
-
-	/* check for the special mbuf used in portDisable */
-	if (mBufPtr == ixEthAccMacState[portId].portDisableRxMbufPtr)
-	{
-            *rxState = RECEIVE;
-	}
-	else
-	{
-	    /* increment the count of user traffic during portDisable */
-	    ixEthAccPortDisableUserBufferCount[portId]++;
-
-	    /* reset the received payload length during portDisable */
-	    IX_OSAL_MBUF_MLEN(mBufPtr)    = 0;
-	    IX_OSAL_MBUF_PKT_LEN(mBufPtr) = 0;
-
-	    if (useMultiBufferCallback)
-	    {
-		/* call the user callback with one unchained
-		 * buffer, without payload. A small array is built
-		 * to be used as a parameter (the user callback expects
-		 * to receive an array ended by a NULL pointer.
-		 */
-		IX_OSAL_MBUF *mBufPtrArray[2];
-
-		mBufPtrArray[0] = mBufPtr;
-		mBufPtrArray[1] = NULL;
-		ixEthAccPortDisableMultiBufferFn[portId](
-			 ixEthAccPortDisableMultiBufferCbTag[portId],
-			 mBufPtrArray);
-	    }
-	    else
-	    {
-		/* call the user callback with a unchained
-		 * buffer, without payload and the destination port is
-		 * unknown.
-		 */
-		ixEthAccPortDisableFn[portId](
-		      ixEthAccPortDisableCbTag[portId],
-		      mBufPtr,
-		      IX_ETH_DB_UNKNOWN_PORT /* port not found */);
-	    }
-        }
-
-        mBufPtr = mNextPtr;
-    }
-}
-
-PRIVATE IxEthAccStatus
-ixEthAccPortDisableTryReplenish(UINT32 portId)
-{
-    int key;
-    IxEthAccStatus status = IX_ETH_ACC_SUCCESS;
-    volatile IxEthAccPortDisableState *rxState = &ixEthAccMacState[portId].rxState;
-    /* replenish with the special buffer again if it is received
-     * and update the rxState
-     * This section is protected because the portDisable context
-     * run an identical code, so the system keeps replenishing at the
-     * maximum rate.
-     */
-    key = ixOsalIrqLock();
-    if (*rxState == RECEIVE)
-    {
-	IX_OSAL_MBUF *mbufRxPtr = ixEthAccMacState[portId].portDisableRxMbufPtr;
-	*rxState = REPLENISH;
-	IX_OSAL_MBUF_MLEN(mbufRxPtr) = IX_ETHACC_RX_MBUF_MIN_SIZE;
-	status = ixEthAccPortRxFreeReplenish(portId, mbufRxPtr);
-    }
-    ixOsalIrqUnlock(key);
-
-    return status;
-}
-
-PRIVATE void
-ixEthAccPortDisableRxAndReplenish (IxEthAccPortId portId,
-				   IX_OSAL_MBUF * mBufPtr,
-				   BOOL useMultiBufferCallback)
-{
-    /* call the callback which forwards the traffic to the client */
-    ixEthAccPortDisableRx(portId, mBufPtr, useMultiBufferCallback);
-
-    /* try to replenish with the buffer used in portDisable
-     * if seen in Rx
-     */
-    ixEthAccPortDisableTryReplenish(portId);
-}
-
-PRIVATE void
-ixEthAccPortDisableRxCallback (UINT32 cbTag,
-			       IX_OSAL_MBUF * mBufPtr,
-			       UINT32 learnedPortId)
-{
-    IxEthAccPortId portId = (IxEthAccPortId)cbTag;
-
-    /* call the portDisable receive callback */
-   (ixEthAccPortDisableRxTable[portId])(portId, mBufPtr, false);
-}
-
-PRIVATE void
-ixEthAccPortDisableMultiBufferRxCallback (UINT32 cbTag,
-					  IX_OSAL_MBUF **mBufPtr)
-{
-    IxEthAccPortId portId = (IxEthAccPortId)cbTag;
-
-    while (*mBufPtr)
-    {
-	/* call the portDisable receive callback with one buffer at a time */
-	(ixEthAccPortDisableRxTable[portId])(portId, *mBufPtr++, true);
-    }
-}
-
-IxEthAccStatus
-ixEthAccPortDisablePriv(IxEthAccPortId portId)
-{
-    IxEthAccStatus status = IX_ETH_ACC_SUCCESS;
-    int key;
-    int retry, retryTimeout;
-    volatile IxEthAccPortDisableState *state = &ixEthAccMacState[portId].portDisableState;
-    volatile IxEthAccPortDisableState *rxState = &ixEthAccMacState[portId].rxState;
-    volatile IxEthAccPortDisableState *txState = &ixEthAccMacState[portId].txState;
-
-    IX_ETH_ACC_VALIDATE_PORT_ID(portId);
-
-    if (IX_ETH_ACC_SUCCESS != ixEthAccSingleEthNpeCheck(portId))
-    {
-        IX_ETH_ACC_WARNING_LOG("EthAcc: Unavailable Eth %d: Cannot disable port.\n",(INT32)portId,0,0,0,0,0);
-        return IX_ETH_ACC_SUCCESS ;
-    }
-
-    if (!IX_ETH_IS_PORT_INITIALIZED(portId))
-    {
-	return (IX_ETH_ACC_PORT_UNINITIALIZED);
-    }
-
-    /* if the state is being set to what it is already at, do nothing */
-    if (!ixEthAccMacState[portId].enabled)
-    {
-        return IX_ETH_ACC_SUCCESS;
-    }
-
-    *state = DISABLED;
-
-    /* disable MAC receive first */
-    ixEthAccPortRxDisablePriv(portId);
-
-#ifdef CONFIG_IXP425_COMPONENT_ETHDB
-    /* disable ethernet database for this port - It is done now to avoid
-     * issuing ELT maintenance after requesting 'port disable' in an NPE
-     */
-    if (ixEthDBPortDisable(portId) != IX_ETH_DB_SUCCESS)
-    {
-	status = IX_ETH_ACC_FAIL;
-        IX_ETH_ACC_FATAL_LOG("ixEthAccPortDisable: failed to disable EthDB for this port\n", 0, 0, 0, 0, 0, 0);
-    }
-#endif
-
-    /* enter the critical section */
-    key = ixOsalIrqLock();
-
-    /* swap the Rx and TxDone callbacks */
-    ixEthAccPortDisableFn[portId]            = ixEthAccPortData[portId].ixEthAccRxData.rxCallbackFn;
-    ixEthAccPortDisableMultiBufferFn[portId] = ixEthAccPortData[portId].ixEthAccRxData.rxMultiBufferCallbackFn;
-    ixEthAccPortDisableCbTag[portId]         = ixEthAccPortData[portId].ixEthAccRxData.rxCallbackTag;
-    ixEthAccPortDisableMultiBufferCbTag[portId] = ixEthAccPortData[portId].ixEthAccRxData.rxMultiBufferCallbackTag;
-    ixEthAccPortDisableTxDoneFn[portId]      = ixEthAccPortData[portId].ixEthAccTxData.txBufferDoneCallbackFn;
-    ixEthAccPortDisableTxDoneCbTag[portId]   = ixEthAccPortData[portId].ixEthAccTxData.txCallbackTag;
-    ixEthAccPortDisableRxTable[portId]       =  ixEthAccPortDisableRx;
-
-    /* register temporary callbacks */
-    ixEthAccPortData[portId].ixEthAccRxData.rxCallbackFn            = ixEthAccPortDisableRxCallback;
-    ixEthAccPortData[portId].ixEthAccRxData.rxCallbackTag           = portId;
-
-    ixEthAccPortData[portId].ixEthAccRxData.rxMultiBufferCallbackFn = ixEthAccPortDisableMultiBufferRxCallback;
-    ixEthAccPortData[portId].ixEthAccRxData.rxMultiBufferCallbackTag = portId;
-
-    ixEthAccPortData[portId].ixEthAccTxData.txBufferDoneCallbackFn  = ixEthAccPortDisableTxDone;
-    ixEthAccPortData[portId].ixEthAccTxData.txCallbackTag           = portId;
-
-    /* initialise the Rx state and Tx states */
-    *txState = TRANSMIT_DONE;
-    *rxState = RECEIVE;
-
-    /* exit the critical section */
-    ixOsalIrqUnlock(key);
-
-    /* enable a NPE loopback */
-    if (ixEthAccNpeLoopbackEnablePriv(portId) != IX_ETH_ACC_SUCCESS)
-    {
-	status = IX_ETH_ACC_FAIL;
-    }
-
-    if (status == IX_ETH_ACC_SUCCESS)
-    {
-	retry = 0;
-
-	/* Step 1 : Drain Tx traffic and TxDone queues :
-	 *
-	 * Transmit and replenish at least once with the
-	 * special buffers until both of them are seen
-	 * in the callback hook
-	 *
-	 * (the receive callback keeps replenishing, so once we see
-	 * the special Tx buffer, we can be sure that Tx drain is complete)
-	 */
-	ixEthAccPortDisableRxTable[portId]
-	    =  ixEthAccPortDisableRxAndReplenish;
-	ixEthAccPortData[portId].ixEthAccTxData.txBufferDoneCallbackFn
-	    = ixEthAccPortDisableTxDone;
-
-	do
-	{
-	    /* keep replenishing */
-	    status = ixEthAccPortDisableTryReplenish(portId);
-	    if (status == IX_ETH_ACC_SUCCESS)
-	    {
-		/* keep transmitting */
-		status = ixEthAccPortDisableTryTransmit(portId);
-	    }
-	    if (status == IX_ETH_ACC_SUCCESS)
-	    {
-		/* wait for some traffic being processed */
-		ixOsalSleep(IX_ETH_ACC_PORT_DISABLE_DELAY_MSECS);
-	    }
-	}
-	while ((status == IX_ETH_ACC_SUCCESS)
-	       && (retry++ < IX_ETH_ACC_MAX_RETRY)
-	       && (*txState == TRANSMIT));
-
-	/* Step 2 : Drain Rx traffic, RxFree and Rx queues :
-	 *
-	 * Transmit and replenish at least once with the
-	 * special buffers until both of them are seen
-	 * in the callback hook
-	 * (the transmit callback keeps transmitting, and when we see
-	 * the special Rx buffer, we can be sure that rxFree drain
-	 * is complete)
-	 *
-	 * The nested loop helps to retry if the user was keeping
-	 * replenishing or transmitting during portDisable.
-	 *
-	 * The 2 nested loops ensure more retries if user traffic is
-	 * seen during portDisable : the user should not replenish
-	 * or transmit while portDisable is running. However, because of
-	 * the queueing possibilities in ethAcc dataplane, it is possible
-	 * that a lot of traffic is left in the queues (e.g. when
-	 * transmitting over a low speed link) and therefore, more
-	 * retries are allowed to help flushing the buffers out.
-	 */
-	ixEthAccPortDisableRxTable[portId]
-	    =  ixEthAccPortDisableRx;
-	ixEthAccPortData[portId].ixEthAccTxData.txBufferDoneCallbackFn
-	    = ixEthAccPortDisableTxDoneAndSubmit;
-
-	do
-	{
-	    do
-	    {
-		ixEthAccPortDisableUserBufferCount[portId] = 0;
-
-		/* keep replenishing */
-		status = ixEthAccPortDisableTryReplenish(portId);
-		if (status == IX_ETH_ACC_SUCCESS)
-		{
-		    /* keep transmitting */
-		    status = ixEthAccPortDisableTryTransmit(portId);
-		}
-		if (status == IX_ETH_ACC_SUCCESS)
-		{
-		    /* wait for some traffic being processed */
-		    ixOsalSleep(IX_ETH_ACC_PORT_DISABLE_DELAY_MSECS);
-		}
-	    }
-	    while ((status == IX_ETH_ACC_SUCCESS)
-		   && (retry++ < IX_ETH_ACC_MAX_RETRY)
-		   && ((ixEthAccPortDisableUserBufferCount[portId] != 0)
-		       || (*rxState == REPLENISH)));
-
-	    /* After the first iteration, change the receive callbacks,
-	     * to process only 1 buffer at a time
-	     */
-	    ixEthAccPortDisableRxTable[portId]
-		= ixEthAccPortDisableRx;
-	    ixEthAccPortData[portId].ixEthAccTxData.txBufferDoneCallbackFn
-		= ixEthAccPortDisableTxDone;
-
-	    /* repeat the whole process while user traffic is seen in TxDone
-	     *
-	     * The conditions to stop the loop are
-	     * - Xscale has both Rx and Tx special buffers
-	     *   (txState = transmit, rxState = receive)
-	     * - any error in txSubmit or rxReplenish
-	     * - no user traffic seen
-	     * - an excessive amount of retries
-	     */
-	}
-	while ((status == IX_ETH_ACC_SUCCESS)
-	       && (retry < IX_ETH_ACC_MAX_RETRY)
-	       && (*txState == TRANSMIT));
-
-	/* check the loop exit conditions. The NPE should not hold
-	 * the special buffers.
-	 */
-	if ((*rxState == REPLENISH) || (*txState == TRANSMIT))
-	{
-	    status = IX_ETH_ACC_FAIL;
-	}
-
-	if (status == IX_ETH_ACC_SUCCESS)
-	{
-	    /* Step 3 : Replenish without transmitting until a timeout
-	     * occurs, in order to drain the internal NPE fifos
-	     *
-	     * we can expect a few frames srill held
-	     * in the NPE.
-	     *
-	     * The 2 nested loops take care about the NPE dropping traffic
-	     * (including loopback traffic) when the Rx queue is full.
-	     *
-	     * The timeout value is very conservative
-	     * since the loopback used keeps replenishhing.
-	     *
-	     */
-	    do
-	    {
-		ixEthAccPortDisableRxTable[portId] = ixEthAccPortDisableRxAndReplenish;
-		ixEthAccPortDisableUserBufferCount[portId] = 0;
-		retryTimeout = 0;
-		do
-		{
-		    /* keep replenishing */
-		    status = ixEthAccPortDisableTryReplenish(portId);
-		    if (status == IX_ETH_ACC_SUCCESS)
-		    {
-			/* wait for some traffic being processed */
-			ixOsalSleep(IX_ETH_ACC_PORT_DISABLE_DELAY_MSECS);
-		    }
-		}
-		while ((status == IX_ETH_ACC_SUCCESS)
-		       && (retryTimeout++ < IX_ETH_ACC_MAX_RETRY_TIMEOUT));
-
-		/* Step 4 : Transmit once. Stop replenish
-		 *
-		 * After the Rx timeout, we are sure that the NPE does not
-		 * hold any frame in its internal NPE fifos.
-		 *
-		 * At this point, the NPE still holds the last rxFree buffer.
-		 * By transmitting a single frame, this should unblock the
-		 * last rxFree buffer. This code just transmit once and
-		 * wait for both frames seen in TxDone and in rxFree.
-		 *
-		 */
-		ixEthAccPortDisableRxTable[portId] =  ixEthAccPortDisableRx;
-		status = ixEthAccPortDisableTryTransmit(portId);
-
-		/* the NPE should immediatelyt release
-		 * the last Rx buffer and the last transmitted buffer
-		 * unless the last Tx frame was dropped (rx queue full)
-		 */
-		if (status == IX_ETH_ACC_SUCCESS)
-		{
-		    retryTimeout = 0;
-		    do
-		    {
-			ixOsalSleep(IX_ETH_ACC_PORT_DISABLE_DELAY_MSECS);
-		    }
-		    while ((*rxState == REPLENISH)
-			   && (retryTimeout++ < IX_ETH_ACC_MAX_RETRY_TIMEOUT));
-		}
-
-		/* the NPE may have dropped the traffic because of Rx
-		 * queue being full. This code ensures that the last
-		 * Tx and Rx frames are both received.
-		 */
-	    }
-	    while ((status == IX_ETH_ACC_SUCCESS)
-		   && (retry++ < IX_ETH_ACC_MAX_RETRY)
-		   && ((*txState == TRANSMIT)
-		       || (*rxState == REPLENISH)
-		       || (ixEthAccPortDisableUserBufferCount[portId] != 0)));
-
-	    /* Step 5 : check the final states : the NPE has
-	     * no buffer left, nor in Tx , nor in Rx directions.
-	     */
-	    if ((*rxState == REPLENISH) || (*txState == TRANSMIT))
-	    {
-		status = IX_ETH_ACC_FAIL;
-	    }
-	}
-
-        /* now all the buffers are drained, disable NPE loopback
-	 * This is done regardless of the logic to drain the queues and
-	 * the internal buffers held by the NPE.
-	 */
-	if (ixEthAccNpeLoopbackDisablePriv(portId) != IX_ETH_ACC_SUCCESS)
-	{
-	    status = IX_ETH_ACC_FAIL;
-	}
-    }
-
-    /* disable MAC Tx and Rx services */
-    ixEthAccMacState[portId].enabled = false;
-    ixEthAccMacStateUpdate(portId);
-
-    /* restore the Rx and TxDone callbacks (within a critical section) */
-    key = ixOsalIrqLock();
-
-    ixEthAccPortData[portId].ixEthAccRxData.rxCallbackFn            = ixEthAccPortDisableFn[portId];
-    ixEthAccPortData[portId].ixEthAccRxData.rxCallbackTag           = ixEthAccPortDisableCbTag[portId];
-    ixEthAccPortData[portId].ixEthAccRxData.rxMultiBufferCallbackFn = ixEthAccPortDisableMultiBufferFn[portId];
-    ixEthAccPortData[portId].ixEthAccRxData.rxMultiBufferCallbackTag = ixEthAccPortDisableMultiBufferCbTag[portId];
-    ixEthAccPortData[portId].ixEthAccTxData.txBufferDoneCallbackFn  = ixEthAccPortDisableTxDoneFn[portId];
-    ixEthAccPortData[portId].ixEthAccTxData.txCallbackTag           = ixEthAccPortDisableTxDoneCbTag[portId];
-
-    ixOsalIrqUnlock(key);
-
-    /* the MAC core rx/tx disable may left the MAC hardware in an
-     * unpredictable state. A hw reset is executed before resetting
-     * all the MAC parameters to a known value.
-     */
-    REG_WRITE(ixEthAccMacBase[portId],
-	      IX_ETH_ACC_MAC_CORE_CNTRL,
-	      IX_ETH_ACC_CORE_RESET);
-
-    ixOsalSleep(IX_ETH_ACC_MAC_RESET_DELAY);
-
-    /* rewrite all parameters to their current value */
-    ixEthAccMacStateUpdate(portId);
-
-    REG_WRITE(ixEthAccMacBase[portId],
-	      IX_ETH_ACC_MAC_INT_CLK_THRESH,
-	      IX_ETH_ACC_MAC_INT_CLK_THRESH_DEFAULT);
-
-    REG_WRITE(ixEthAccMacBase[portId],
-	      IX_ETH_ACC_MAC_CORE_CNTRL,
-	      IX_ETH_ACC_CORE_MDC_EN);
-
-    return status;
-}
-
-IxEthAccStatus
-ixEthAccPortEnabledQueryPriv(IxEthAccPortId portId, BOOL *enabled)
-{
-    IX_ETH_ACC_VALIDATE_PORT_ID(portId);
-
-    if (IX_ETH_ACC_SUCCESS != ixEthAccSingleEthNpeCheck(portId))
-    {
-        IX_ETH_ACC_WARNING_LOG("EthAcc: Unavailable Eth %d: Cannot enable port.\n",(INT32)portId,0,0,0,0,0);
-
-        /* Since Eth NPE is not available, port must be disabled */
-        *enabled = false ;
-        return IX_ETH_ACC_SUCCESS ;
-    }
-
-    if (!IX_ETH_IS_PORT_INITIALIZED(portId))
-    {
-        /* Since Eth NPE is not available, port must be disabled */
-        *enabled = false ;
-	return (IX_ETH_ACC_PORT_UNINITIALIZED);
-    }
-
-    *enabled = ixEthAccMacState[portId].enabled;
-
-    return IX_ETH_ACC_SUCCESS;
-}
-
-IxEthAccStatus
-ixEthAccPortMacResetPriv(IxEthAccPortId portId)
-{
-    IX_ETH_ACC_VALIDATE_PORT_ID(portId);
-
-    if (IX_ETH_ACC_SUCCESS != ixEthAccSingleEthNpeCheck(portId))
-    {
-        IX_ETH_ACC_WARNING_LOG("EthAcc: Eth %d: Cannot reset Ethernet coprocessor.\n",(INT32)portId,0,0,0,0,0);
-        return IX_ETH_ACC_SUCCESS ;
-    }
-
-    if (!IX_ETH_IS_PORT_INITIALIZED(portId))
-    {
-	return (IX_ETH_ACC_PORT_UNINITIALIZED);
-    }
-
-    REG_WRITE(ixEthAccMacBase[portId],
-	      IX_ETH_ACC_MAC_CORE_CNTRL,
-	      IX_ETH_ACC_CORE_RESET);
-
-    ixOsalSleep(IX_ETH_ACC_MAC_RESET_DELAY);
-
-    /* rewrite all parameters to their current value */
-    ixEthAccMacStateUpdate(portId);
-
-    REG_WRITE(ixEthAccMacBase[portId],
-	      IX_ETH_ACC_MAC_INT_CLK_THRESH,
-	      IX_ETH_ACC_MAC_INT_CLK_THRESH_DEFAULT);
-
-    REG_WRITE(ixEthAccMacBase[portId],
-	      IX_ETH_ACC_MAC_CORE_CNTRL,
-	      IX_ETH_ACC_CORE_MDC_EN);
-
-    return IX_ETH_ACC_SUCCESS;
-}
-
-IxEthAccStatus
-ixEthAccPortLoopbackEnable(IxEthAccPortId portId)
-{
-    UINT32 regval;
-
-    /* Turn off promiscuous mode */
-    IX_ETH_ACC_VALIDATE_PORT_ID(portId);
-
-    if (IX_ETH_ACC_SUCCESS != ixEthAccSingleEthNpeCheck(portId))
-    {
-        IX_ETH_ACC_WARNING_LOG("EthAcc: Eth %d: Cannot enable loopback.\n",(INT32)portId,0,0,0,0,0);
-        return IX_ETH_ACC_SUCCESS ;
-    }
-
-    if (!IX_ETH_IS_PORT_INITIALIZED(portId))
-    {
-	return (IX_ETH_ACC_PORT_UNINITIALIZED);
-    }
-
-    /* read register */
-    REG_READ(ixEthAccMacBase[portId],
-	     IX_ETH_ACC_MAC_RX_CNTRL1,
-	     regval);
-
-    /* update register */
-    REG_WRITE(ixEthAccMacBase[portId],
-	      IX_ETH_ACC_MAC_RX_CNTRL1,
-	      regval | IX_ETH_ACC_RX_CNTRL1_LOOP_EN);
-
-    return IX_ETH_ACC_SUCCESS;
-}
-
-PRIVATE void
-ixEthAccNpeLoopbackMessageCallback (IxNpeMhNpeId npeId,
-				    IxNpeMhMessage msg)
-{
-    IxEthAccPortId portId = IX_ETH_ACC_NPE_TO_PORT_ID(npeId);
-
-#ifndef NDEBUG
-    /* Prudent to at least check the port is within range */
-    if (portId >= IX_ETH_ACC_NUMBER_OF_PORTS)
-    {
-	IX_ETH_ACC_FATAL_LOG("IXETHACC:ixEthAccPortDisableMessageCallback: Illegal port: %u\n",
-            (UINT32) portId, 0, 0, 0, 0, 0);
-
-	return;
-    }
-#endif
-
-    /* unlock message reception mutex */
-    ixOsalMutexUnlock(&ixEthAccMacState[portId].npeLoopbackMessageLock);
-}
-
-IxEthAccStatus
-ixEthAccNpeLoopbackEnablePriv(IxEthAccPortId portId)
-{
-    IX_STATUS npeMhStatus;
-    IxNpeMhMessage message;
-    IxEthAccStatus status = IX_ETH_ACC_SUCCESS;
-
-    /* Turn off promiscuous mode */
-    IX_ETH_ACC_VALIDATE_PORT_ID(portId);
-
-    if (IX_ETH_ACC_SUCCESS != ixEthAccSingleEthNpeCheck(portId))
-    {
-        IX_ETH_ACC_WARNING_LOG("EthAcc: Eth %d: Cannot enable NPE loopback.\n",(INT32)portId,0,0,0,0,0);
-        return IX_ETH_ACC_SUCCESS ;
-    }
-
-    if (!IX_ETH_IS_PORT_INITIALIZED(portId))
-    {
-	return (IX_ETH_ACC_PORT_UNINITIALIZED);
-    }
-
-    /* enable NPE loopback (lsb of the message contains the value 1) */
-    message.data[0] = (IX_ETHNPE_SETLOOPBACK_MODE << IX_ETH_ACC_MAC_MSGID_SHL)
-	| 0x01;
-    message.data[1] = 0;
-
-    npeMhStatus = ixNpeMhMessageWithResponseSend(IX_ETH_ACC_PORT_TO_NPE_ID(portId),
-		message,
-		IX_ETHNPE_SETLOOPBACK_MODE_ACK,
-		ixEthAccNpeLoopbackMessageCallback,
-		IX_NPEMH_SEND_RETRIES_DEFAULT);
-
-    if (npeMhStatus != IX_SUCCESS)
-    {
-        status = IX_ETH_ACC_FAIL;
-    }
-    else
-    {
-	/* wait for NPE loopbackEnable response */
-        if (ixOsalMutexLock(&ixEthAccMacState[portId]. npeLoopbackMessageLock,
-			    IX_ETH_ACC_PORT_DISABLE_DELAY_MSECS)
-	    != IX_SUCCESS)
-        {
-            status = IX_ETH_ACC_FAIL;
-        }
-    }
-
-    return status;
-}
-
-IxEthAccStatus
-ixEthAccPortTxEnablePriv(IxEthAccPortId portId)
-{
-    UINT32 regval;
-
-    /* Turn off promiscuous mode */
-    IX_ETH_ACC_VALIDATE_PORT_ID(portId);
-
-    if (IX_ETH_ACC_SUCCESS != ixEthAccSingleEthNpeCheck(portId))
-    {
-        IX_ETH_ACC_WARNING_LOG("EthAcc: Eth %d: Cannot enable TX.\n",(INT32)portId,0,0,0,0,0);
-        return IX_ETH_ACC_SUCCESS ;
-    }
-
-    if (!IX_ETH_IS_PORT_INITIALIZED(portId))
-    {
-	return (IX_ETH_ACC_PORT_UNINITIALIZED);
-    }
-
-    /* read register */
-    REG_READ(ixEthAccMacBase[portId],
-	     IX_ETH_ACC_MAC_TX_CNTRL1,
-	     regval);
-
-    /* update register */
-    REG_WRITE(ixEthAccMacBase[portId],
-	      IX_ETH_ACC_MAC_TX_CNTRL1,
-	      regval | IX_ETH_ACC_TX_CNTRL1_TX_EN);
-
-    return IX_ETH_ACC_SUCCESS;
-}
-
-IxEthAccStatus
-ixEthAccPortRxEnablePriv(IxEthAccPortId portId)
-{
-    UINT32 regval;
-
-    /* Turn off promiscuous mode */
-    IX_ETH_ACC_VALIDATE_PORT_ID(portId);
-
-    if (IX_ETH_ACC_SUCCESS != ixEthAccSingleEthNpeCheck(portId))
-    {
-        IX_ETH_ACC_WARNING_LOG("EthAcc: Eth %d: Cannot enable RX.\n",(INT32)portId,0,0,0,0,0);
-        return IX_ETH_ACC_SUCCESS ;
-    }
-
-    if (!IX_ETH_IS_PORT_INITIALIZED(portId))
-    {
-	return (IX_ETH_ACC_PORT_UNINITIALIZED);
-    }
-
-    /* read register */
-    REG_READ(ixEthAccMacBase[portId],
-	     IX_ETH_ACC_MAC_RX_CNTRL1,
-	     regval);
-
-    /* update register */
-    REG_WRITE(ixEthAccMacBase[portId],
-	      IX_ETH_ACC_MAC_RX_CNTRL1,
-	      regval | IX_ETH_ACC_RX_CNTRL1_RX_EN);
-
-    return IX_ETH_ACC_SUCCESS;
-}
-
-IxEthAccStatus
-ixEthAccPortLoopbackDisable(IxEthAccPortId portId)
-{
-    UINT32 regval;
-
-    IX_ETH_ACC_VALIDATE_PORT_ID(portId);
-
-    if (IX_ETH_ACC_SUCCESS != ixEthAccSingleEthNpeCheck(portId))
-    {
-        IX_ETH_ACC_WARNING_LOG("EthAcc: Eth %d: Cannot disable loopback.\n",(INT32)portId,0,0,0,0,0);
-        return IX_ETH_ACC_SUCCESS ;
-    }
-
-    if (!IX_ETH_IS_PORT_INITIALIZED(portId))
-    {
-	return (IX_ETH_ACC_PORT_UNINITIALIZED);
-    }
-
-    /*disable MAC loopabck */
-    REG_READ(ixEthAccMacBase[portId],
-	     IX_ETH_ACC_MAC_RX_CNTRL1,
-	     regval);
-
-    REG_WRITE(ixEthAccMacBase[portId],
-	      IX_ETH_ACC_MAC_RX_CNTRL1,
-	      (regval & ~IX_ETH_ACC_RX_CNTRL1_LOOP_EN));
-
-    return IX_ETH_ACC_SUCCESS;
-}
-
-IxEthAccStatus
-ixEthAccNpeLoopbackDisablePriv(IxEthAccPortId portId)
-{
-    IX_STATUS npeMhStatus;
-    IxNpeMhMessage message;
-    IxEthAccStatus status = IX_ETH_ACC_SUCCESS;
-
-    /* Turn off promiscuous mode */
-    IX_ETH_ACC_VALIDATE_PORT_ID(portId);
-
-    if (IX_ETH_ACC_SUCCESS != ixEthAccSingleEthNpeCheck(portId))
-    {
-        IX_ETH_ACC_WARNING_LOG("EthAcc: Eth %d: Cannot enable NPE loopback.\n",(INT32)portId,0,0,0,0,0);
-        return IX_ETH_ACC_SUCCESS ;
-    }
-
-    if (!IX_ETH_IS_PORT_INITIALIZED(portId))
-    {
-	return (IX_ETH_ACC_PORT_UNINITIALIZED);
-    }
-
-    /* disable NPE loopback (lsb of the message contains the value 0) */
-    message.data[0] = (IX_ETHNPE_SETLOOPBACK_MODE << IX_ETH_ACC_MAC_MSGID_SHL);
-    message.data[1] = 0;
-
-    npeMhStatus = ixNpeMhMessageWithResponseSend(IX_ETH_ACC_PORT_TO_NPE_ID(portId),
-		message,
-		IX_ETHNPE_SETLOOPBACK_MODE_ACK,
-		ixEthAccNpeLoopbackMessageCallback,
-		IX_NPEMH_SEND_RETRIES_DEFAULT);
-
-    if (npeMhStatus != IX_SUCCESS)
-    {
-        status = IX_ETH_ACC_FAIL;
-    }
-    else
-    {
-	/* wait for NPE loopbackEnable response */
-        if (ixOsalMutexLock(&ixEthAccMacState[portId].npeLoopbackMessageLock,
-			    IX_ETH_ACC_PORT_DISABLE_DELAY_MSECS)
-	    != IX_SUCCESS)
-        {
-            status = IX_ETH_ACC_FAIL;
-        }
-    }
-
-    return status;
-}
-
-IxEthAccStatus
-ixEthAccPortTxDisablePriv(IxEthAccPortId portId)
-{
-    UINT32 regval;
-
-    /* Turn off promiscuous mode */
-    IX_ETH_ACC_VALIDATE_PORT_ID(portId);
-
-    if (IX_ETH_ACC_SUCCESS != ixEthAccSingleEthNpeCheck(portId))
-    {
-        IX_ETH_ACC_WARNING_LOG("EthAcc: Eth %d: Cannot disable TX.\n", (INT32)portId,0,0,0,0,0);
-        return IX_ETH_ACC_SUCCESS ;
-    }
-
-    if (!IX_ETH_IS_PORT_INITIALIZED(portId))
-    {
-	return (IX_ETH_ACC_PORT_UNINITIALIZED);
-    }
-
-    /* read register */
-    REG_READ(ixEthAccMacBase[portId],
-	     IX_ETH_ACC_MAC_TX_CNTRL1,
-	     regval);
-
-    /* update register */
-    REG_WRITE(ixEthAccMacBase[portId],
-	      IX_ETH_ACC_MAC_TX_CNTRL1,
-	      (regval & ~IX_ETH_ACC_TX_CNTRL1_TX_EN));
-
-    return IX_ETH_ACC_SUCCESS;
-}
-
-IxEthAccStatus
-ixEthAccPortRxDisablePriv(IxEthAccPortId portId)
-{
-    UINT32 regval;
-
-    /* Turn off promiscuous mode */
-    IX_ETH_ACC_VALIDATE_PORT_ID(portId);
-
-    if (IX_ETH_ACC_SUCCESS != ixEthAccSingleEthNpeCheck(portId))
-    {
-        IX_ETH_ACC_WARNING_LOG("EthAcc: Eth %d: Cannot disable RX.\n", (INT32)portId,0,0,0,0,0);
-        return IX_ETH_ACC_SUCCESS ;
-    }
-
-    if (!IX_ETH_IS_PORT_INITIALIZED(portId))
-    {
-	return (IX_ETH_ACC_PORT_UNINITIALIZED);
-    }
-
-    /* read register */
-    REG_READ(ixEthAccMacBase[portId],
-	     IX_ETH_ACC_MAC_RX_CNTRL1,
-	     regval);
-
-    /* update register */
-    REG_WRITE(ixEthAccMacBase[portId],
-	      IX_ETH_ACC_MAC_RX_CNTRL1,
-	      (regval & ~IX_ETH_ACC_RX_CNTRL1_RX_EN));
-
-    return IX_ETH_ACC_SUCCESS;
-}
-
-IxEthAccStatus
-ixEthAccPortPromiscuousModeClearPriv(IxEthAccPortId portId)
-{
-    UINT32 regval;
-
-    /* Turn off promiscuous mode */
-    IX_ETH_ACC_VALIDATE_PORT_ID(portId);
-
-    if (IX_ETH_ACC_SUCCESS != ixEthAccSingleEthNpeCheck(portId))
-    {
-        IX_ETH_ACC_WARNING_LOG("EthAcc: Unavailable Eth %d: Cannot clear promiscuous mode.\n",(INT32)portId,0,0,0,0,0);
-        return IX_ETH_ACC_SUCCESS ;
-    }
-
-    if (!IX_ETH_IS_PORT_INITIALIZED(portId))
-    {
-	return (IX_ETH_ACC_PORT_UNINITIALIZED);
-    }
-
-    /*set bit 5 of Rx control 1 - enable address filtering*/
-    REG_READ(ixEthAccMacBase[portId],
-	     IX_ETH_ACC_MAC_RX_CNTRL1,
-	     regval);
-
-    REG_WRITE(ixEthAccMacBase[portId],
-	      IX_ETH_ACC_MAC_RX_CNTRL1,
-	      regval | IX_ETH_ACC_RX_CNTRL1_ADDR_FLTR_EN);
-
-    ixEthAccMacState[portId].promiscuous = false;
-
-    ixEthAccMulticastAddressSet(portId);
-
-    return IX_ETH_ACC_SUCCESS;
-}
-
-IxEthAccStatus
-ixEthAccPortPromiscuousModeSetPriv(IxEthAccPortId portId)
-{
-    UINT32 regval;
-
-    IX_ETH_ACC_VALIDATE_PORT_ID(portId);
-
-    if (IX_ETH_ACC_SUCCESS != ixEthAccSingleEthNpeCheck(portId))
-    {
-        IX_ETH_ACC_WARNING_LOG("EthAcc: Unavailable Eth %d: Cannot set promiscuous mode.\n",(INT32)portId,0,0,0,0,0);
-        return IX_ETH_ACC_SUCCESS ;
-    }
-
-    if (!IX_ETH_IS_PORT_INITIALIZED(portId))
-    {
-	return (IX_ETH_ACC_PORT_UNINITIALIZED);
-    }
-
-    /*
-     * Set bit 5 of Rx control 1 - We enable address filtering even in
-     * promiscuous mode because we want the MAC to set the appropriate
-     * bits in m_flags which doesn't happen if we turn off filtering.
-     */
-    REG_READ(ixEthAccMacBase[portId],
-	     IX_ETH_ACC_MAC_RX_CNTRL1,
-	     regval);
-
-    REG_WRITE(ixEthAccMacBase[portId],
-	      IX_ETH_ACC_MAC_RX_CNTRL1,
-	      regval | IX_ETH_ACC_RX_CNTRL1_ADDR_FLTR_EN);
-
-    ixEthAccMacState[portId].promiscuous = true;
-
-    ixEthAccMulticastAddressSet(portId);
-
-    return IX_ETH_ACC_SUCCESS;
-}
-
-IxEthAccStatus
-ixEthAccPortUnicastMacAddressSetPriv (IxEthAccPortId portId,
-				  IxEthAccMacAddr *macAddr)
-{
-    UINT32 i;
-
-    IX_ETH_ACC_VALIDATE_PORT_ID(portId);
-
-    if (IX_ETH_ACC_SUCCESS != ixEthAccSingleEthNpeCheck(portId))
-    {
-        IX_ETH_ACC_WARNING_LOG("EthAcc: Unavailable Eth %d: Cannot set Unicast Mac Address.\n",(INT32)portId,0,0,0,0,0);
-        return IX_ETH_ACC_SUCCESS ;
-    }
-
-    if (!IX_ETH_IS_PORT_INITIALIZED(portId))
-    {
-	return (IX_ETH_ACC_PORT_UNINITIALIZED);
-    }
-
-
-    if (macAddr == NULL)
-    {
-	return IX_ETH_ACC_FAIL;
-    }
-
-    if ( macAddr->macAddress[0] & IX_ETH_ACC_ETH_MAC_BCAST_MCAST_BIT )
-    {
-	/* This is a multicast/broadcast address cant set it ! */
-	return IX_ETH_ACC_FAIL;
-    }
-
-    if ( macAddr->macAddress[0] == 0 &&
-	 macAddr->macAddress[1] == 0 &&
-	 macAddr->macAddress[2] == 0 &&
-	 macAddr->macAddress[3] == 0 &&
-	 macAddr->macAddress[4] == 0 &&
-	 macAddr->macAddress[5] == 0  )
-    {
-	/* This is an invalid mac address cant set it ! */
-	return IX_ETH_ACC_FAIL;
-    }
-
-#ifdef CONFIG_IXP425_COMPONENT_ETHDB
-    /* update the MAC address in the ethernet database */
-    if (ixEthDBPortAddressSet(portId, (IxEthDBMacAddr *) macAddr) != IX_ETH_DB_SUCCESS)
-    {
-        return IX_ETH_ACC_FAIL;
-    }
-#endif
-
-    /*Set the Unicast MAC to the specified value*/
-    for(i=0;i<IX_IEEE803_MAC_ADDRESS_SIZE;i++)
-    {
-	REG_WRITE(ixEthAccMacBase[portId],
-		  IX_ETH_ACC_MAC_UNI_ADDR_1 + i*sizeof(UINT32),
-		  macAddr->macAddress[i]);
-    }
-    ixEthAccMacState[portId].initDone = true;
-
-    return IX_ETH_ACC_SUCCESS;
-}
-
-IxEthAccStatus
-ixEthAccPortUnicastMacAddressGetPriv (IxEthAccPortId portId,
-				  IxEthAccMacAddr *macAddr)
-{
-    /*Return the current value of the Unicast MAC from h/w
-      for the specified port*/
-    UINT32 i;
-
-    IX_ETH_ACC_VALIDATE_PORT_ID(portId);
-
-    if (IX_ETH_ACC_SUCCESS != ixEthAccSingleEthNpeCheck(portId))
-    {
-        IX_ETH_ACC_WARNING_LOG("EthAcc: Unavailable Eth %d: Cannot get Unicast Mac Address.\n",(INT32)portId,0,0,0,0,0);
-        /* Since Eth Npe is unavailable, return invalid MAC Address = 00:00:00:00:00:00 */
-        for(i=0;i<IX_IEEE803_MAC_ADDRESS_SIZE;i++)
-        {
-	    macAddr->macAddress[i] = 0;
-        }
-        return IX_ETH_ACC_SUCCESS ;
-    }
-
-    if(!ixEthAccMacState[portId].initDone)
-    {
-	return (IX_ETH_ACC_MAC_UNINITIALIZED);
-    }
-
-    if (macAddr == NULL)
-    {
-	return IX_ETH_ACC_FAIL;
-    }
-
-
-    for(i=0;i<IX_IEEE803_MAC_ADDRESS_SIZE;i++)
-    {
-	REG_READ(ixEthAccMacBase[portId],
-		 IX_ETH_ACC_MAC_UNI_ADDR_1 + i*sizeof(UINT32),
-		 macAddr->macAddress[i]);
-    }
-    return IX_ETH_ACC_SUCCESS;
-}
-
-PRIVATE IxEthAccStatus
-ixEthAccPortMulticastMacAddressGet (IxEthAccPortId portId,
-				    IxEthAccMacAddr *macAddr)
-{
-    /*Return the current value of the Multicast MAC from h/w
-      for the specified port*/
-    UINT32 i;
-
-    for(i=0;i<IX_IEEE803_MAC_ADDRESS_SIZE;i++)
-    {
-
-	REG_READ(ixEthAccMacBase[portId],
-		 IX_ETH_ACC_MAC_ADDR_1 + i*sizeof(UINT32),
-		 macAddr->macAddress[i]);
-    }
-
-    return IX_ETH_ACC_SUCCESS;
-}
-
-PRIVATE IxEthAccStatus
-ixEthAccPortMulticastMacFilterGet (IxEthAccPortId portId,
-				   IxEthAccMacAddr *macAddr)
-{
-    /*Return the current value of the Multicast MAC from h/w
-      for the specified port*/
-    UINT32 i;
-
-    for(i=0;i<IX_IEEE803_MAC_ADDRESS_SIZE;i++)
-    {
-
-	REG_READ(ixEthAccMacBase[portId],
-		 IX_ETH_ACC_MAC_ADDR_MASK_1 + i*sizeof(UINT32),
-		 macAddr->macAddress[i]);
-    }
-    return IX_ETH_ACC_SUCCESS;
-}
-
-IxEthAccStatus
-ixEthAccPortMulticastAddressJoinPriv (IxEthAccPortId portId,
-				  IxEthAccMacAddr *macAddr)
-{
-    UINT32 i;
-    IxEthAccMacAddr broadcastAddr = {{0xff,0xff,0xff,0xff,0xff,0xff}};
-
-    /*Check that the port parameter is valid*/
-    IX_ETH_ACC_VALIDATE_PORT_ID(portId);
-
-    if (IX_ETH_ACC_SUCCESS != ixEthAccSingleEthNpeCheck(portId))
-    {
-        IX_ETH_ACC_WARNING_LOG("EthAcc: Unavailable Eth %d: Cannot join Multicast Mac Address.\n",(INT32)portId,0,0,0,0,0);
-        return IX_ETH_ACC_SUCCESS ;
-    }
-
-    if (!IX_ETH_IS_PORT_INITIALIZED(portId))
-    {
-	return (IX_ETH_ACC_PORT_UNINITIALIZED);
-    }
-
-    /*Check that the mac address is valid*/
-    if(macAddr == NULL)
-    {
-	return IX_ETH_ACC_FAIL;
-    }
-
-    /* Check that this is a multicast address */
-    if (!(macAddr->macAddress[0] & IX_ETH_ACC_ETH_MAC_BCAST_MCAST_BIT))
-    {
-	return IX_ETH_ACC_FAIL;
-    }
-
-    /* We don't add the Broadcast address */
-    if(ixEthAccMacEqual(&broadcastAddr, macAddr))
-    {
-	return IX_ETH_ACC_FAIL;
-    }
-
-    for (i = 0;
-	 i<ixEthAccMacState[portId].mcastAddrIndex;
-	 i++)
-    {
-	/*Check if the current entry already match an existing matches*/
-	if(ixEthAccMacEqual(&ixEthAccMacState[portId].mcastAddrsTable[i], macAddr))
-	{
-	    /* Address found in the list and already configured,
-	     * return a success status
-	     */
-	    return IX_ETH_ACC_SUCCESS;
-	}
-    }
-
-    /* check for availability at the end of the current table */
-    if(ixEthAccMacState[portId].mcastAddrIndex >= IX_ETH_ACC_MAX_MULTICAST_ADDRESSES)
-    {
-	return IX_ETH_ACC_FAIL;
-    }
-
-    /*First add the address to the multicast table for the
-      specified port*/
-    i=ixEthAccMacState[portId].mcastAddrIndex;
-
-    memcpy(&ixEthAccMacState[portId].mcastAddrsTable[i],
-	   &macAddr->macAddress,
-	   IX_IEEE803_MAC_ADDRESS_SIZE);
-
-    /*Increment the index into the table, this must be done here
-     as MulticastAddressSet below needs to know about the latest
-     entry.
-    */
-    ixEthAccMacState[portId].mcastAddrIndex++;
-
-    /*Then calculate the new value to be written to the address and
-      address mask registers*/
-    ixEthAccMulticastAddressSet(portId);
-
-    return IX_ETH_ACC_SUCCESS;
-}
-
-
-IxEthAccStatus
-ixEthAccPortMulticastAddressJoinAllPriv (IxEthAccPortId portId)
-{
-    IxEthAccMacAddr mcastMacAddr = {{0x1,0x0,0x0,0x0,0x0,0x0}};
-
-    /*Check that the port parameter is valid*/
-    IX_ETH_ACC_VALIDATE_PORT_ID(portId);
-
-    if (IX_ETH_ACC_SUCCESS != ixEthAccSingleEthNpeCheck(portId))
-    {
-        IX_ETH_ACC_WARNING_LOG("EthAcc: Unavailable Eth %d: Cannot join all Multicast Address.\n",(INT32)portId,0,0,0,0,0);
-        return IX_ETH_ACC_SUCCESS ;
-    }
-
-    if (!IX_ETH_IS_PORT_INITIALIZED(portId))
-    {
-	return (IX_ETH_ACC_PORT_UNINITIALIZED);
-    }
-
-    /* remove all entries from the database and
-    *  insert a multicast entry
-    */
-    memcpy(&ixEthAccMacState[portId].mcastAddrsTable[0],
-	   &mcastMacAddr.macAddress,
-	   IX_IEEE803_MAC_ADDRESS_SIZE);
-
-    ixEthAccMacState[portId].mcastAddrIndex = 1;
-    ixEthAccMacState[portId].joinAll = true;
-
-    ixEthAccMulticastAddressSet(portId);
-
-    return IX_ETH_ACC_SUCCESS;
-}
-
-IxEthAccStatus
-ixEthAccPortMulticastAddressLeavePriv (IxEthAccPortId portId,
-				   IxEthAccMacAddr *macAddr)
-{
-    UINT32 i;
-    IxEthAccMacAddr mcastMacAddr = {{0x1,0x0,0x0,0x0,0x0,0x0}};
-
-    /*Check that the port parameter is valid*/
-    IX_ETH_ACC_VALIDATE_PORT_ID(portId);
-
-    if (IX_ETH_ACC_SUCCESS != ixEthAccSingleEthNpeCheck(portId))
-    {
-        IX_ETH_ACC_WARNING_LOG("EthAcc: Unavailable Eth %d: Cannot leave Multicast Address.\n",(INT32)portId,0,0,0,0,0);
-        return IX_ETH_ACC_SUCCESS ;
-    }
-
-    if (!IX_ETH_IS_PORT_INITIALIZED(portId))
-    {
-	return (IX_ETH_ACC_PORT_UNINITIALIZED);
-    }
-
-    /*Check that the mac address is valid*/
-    if(macAddr == NULL)
-    {
-	return IX_ETH_ACC_FAIL;
-    }
-    /* Remove this mac address from the mask for the specified port
-     * we copy down all entries above the blanked entry, and
-     * decrement the index
-     */
-    i=0;
-
-    while(i<ixEthAccMacState[portId].mcastAddrIndex)
-    {
-	/*Check if the current entry matches*/
-	if(ixEthAccMacEqual(&ixEthAccMacState[portId].mcastAddrsTable[i],
-			    macAddr))
-	{
-	    if(ixEthAccMacEqual(macAddr, &mcastMacAddr))
-	    {
-		ixEthAccMacState[portId].joinAll = false;
-	    }
-	    /*Decrement the index into the multicast address table
-	      for the current port*/
-	    ixEthAccMacState[portId].mcastAddrIndex--;
-
-	    /*Copy down all entries above the current entry*/
-	    while(i<ixEthAccMacState[portId].mcastAddrIndex)
-	    {
-		memcpy(&ixEthAccMacState[portId].mcastAddrsTable[i],
-		       &ixEthAccMacState[portId].mcastAddrsTable[i+1],
-		       IX_IEEE803_MAC_ADDRESS_SIZE);
-                i++;
-	    }
-	    /*recalculate the mask and write it to the MAC*/
-	    ixEthAccMulticastAddressSet(portId);
-
-	    return IX_ETH_ACC_SUCCESS;
-	}
-	/* search the next entry */
-	i++;
-    }
-    /* no matching entry found */
-    return IX_ETH_ACC_NO_SUCH_ADDR;
-}
-
-IxEthAccStatus
-ixEthAccPortMulticastAddressLeaveAllPriv (IxEthAccPortId portId)
-{
-    /*Check that the port parameter is valid*/
-    IX_ETH_ACC_VALIDATE_PORT_ID(portId);
-
-    if (IX_ETH_ACC_SUCCESS != ixEthAccSingleEthNpeCheck(portId))
-    {
-        IX_ETH_ACC_WARNING_LOG("EthAcc: Unavailable Eth %d: Cannot leave all Multicast Address.\n",(INT32)portId,0,0,0,0,0);
-        return IX_ETH_ACC_SUCCESS ;
-    }
-
-    if (!IX_ETH_IS_PORT_INITIALIZED(portId))
-    {
-	return (IX_ETH_ACC_PORT_UNINITIALIZED);
-    }
-
-    ixEthAccMacState[portId].mcastAddrIndex = 0;
-    ixEthAccMacState[portId].joinAll = false;
-
-    ixEthAccMulticastAddressSet(portId);
-
-    return IX_ETH_ACC_SUCCESS;
-}
-
-
-IxEthAccStatus
-ixEthAccPortUnicastAddressShowPriv (IxEthAccPortId portId)
-{
-    IxEthAccMacAddr macAddr;
-
-    IX_ETH_ACC_VALIDATE_PORT_ID(portId);
-
-    if (IX_ETH_ACC_SUCCESS != ixEthAccSingleEthNpeCheck(portId))
-    {
-        IX_ETH_ACC_WARNING_LOG("EthAcc: Unavailable Eth %d: Cannot show Unicast Address.\n",(INT32)portId,0,0,0,0,0);
-        return IX_ETH_ACC_SUCCESS ;
-    }
-
-    if (!IX_ETH_IS_PORT_INITIALIZED(portId))
-    {
-	return (IX_ETH_ACC_PORT_UNINITIALIZED);
-    }
-
-    /*Get the MAC (UINICAST) address from hardware*/
-    if(ixEthAccPortUnicastMacAddressGetPriv(portId, &macAddr) != IX_ETH_ACC_SUCCESS)
-    {
-        IX_ETH_ACC_WARNING_LOG("EthAcc: MAC address uninitialised port %u\n",
-			       (INT32)portId,0,0,0,0,0);
-	return IX_ETH_ACC_MAC_UNINITIALIZED;
-    }
-
-    /*print it out*/
-    ixEthAccMacPrint(&macAddr);
-    printf("\n");
-    return IX_ETH_ACC_SUCCESS;
-}
-
-
-
-void
-ixEthAccPortMulticastAddressShowPriv(IxEthAccPortId portId)
-{
-    IxEthAccMacAddr macAddr;
-    UINT32 i;
-
-    if(!IX_ETH_ACC_IS_PORT_VALID(portId))
-    {
-        return;
-    }
-
-    if (IX_ETH_ACC_SUCCESS != ixEthAccSingleEthNpeCheck(portId))
-    {
-        IX_ETH_ACC_WARNING_LOG("EthAcc: Unavailable Eth %d: Cannot show Multicast Address.\n",(INT32)portId,0,0,0,0,0);
-        return ;
-    }
-
-    if (!IX_ETH_IS_PORT_INITIALIZED(portId))
-    {
-	return;
-    }
-
-    printf("Multicast MAC: ");
-    /*Get the MAC (MULTICAST) address from hardware*/
-    ixEthAccPortMulticastMacAddressGet(portId, &macAddr);
-    /*print it out*/
-    ixEthAccMacPrint(&macAddr);
-    /*Get the MAC (MULTICAST) filter from hardware*/
-    ixEthAccPortMulticastMacFilterGet(portId, &macAddr);
-    /*print it out*/
-    printf(" ( ");
-    ixEthAccMacPrint(&macAddr);
-    printf(" )\n");
-    printf("Constituent Addresses:\n");
-    for(i=0;i<ixEthAccMacState[portId].mcastAddrIndex;i++)
-    {
-	ixEthAccMacPrint(&ixEthAccMacState[portId].mcastAddrsTable[i]);
-	printf("\n");
-    }
-    return;
-}
-
-/*Set the duplex mode*/
-IxEthAccStatus
-ixEthAccPortDuplexModeSetPriv (IxEthAccPortId portId,
-			   IxEthAccDuplexMode mode)
-{
-    UINT32 txregval;
-    UINT32 rxregval;
-
-    /*This is bit 1 of the transmit control reg, set to 1 for half
-      duplex, 0 for full duplex*/
-    IX_ETH_ACC_VALIDATE_PORT_ID(portId);
-
-    if (IX_ETH_ACC_SUCCESS != ixEthAccSingleEthNpeCheck(portId))
-    {
-        IX_ETH_ACC_WARNING_LOG("EthAcc: Unavailable Eth %d: Cannot set Duplex Mode.\n",(INT32)portId,0,0,0,0,0);
-        return IX_ETH_ACC_SUCCESS ;
-    }
-
-    if (!IX_ETH_IS_PORT_INITIALIZED(portId))
-    {
-	return (IX_ETH_ACC_PORT_UNINITIALIZED);
-    }
-
-    REG_READ(ixEthAccMacBase[portId],
-	     IX_ETH_ACC_MAC_TX_CNTRL1,
-	     txregval);
-
-    REG_READ(ixEthAccMacBase[portId],
-	     IX_ETH_ACC_MAC_RX_CNTRL1,
-	     rxregval);
-
-    if (mode ==  IX_ETH_ACC_FULL_DUPLEX)
-    {
-	/*Clear half duplex bit in TX*/
-	REG_WRITE(ixEthAccMacBase[portId],
-		  IX_ETH_ACC_MAC_TX_CNTRL1,
-		  txregval & ~IX_ETH_ACC_TX_CNTRL1_DUPLEX);
-
-	/*We must set the pause enable in the receive logic when in
-	  full duplex mode*/
-	REG_WRITE(ixEthAccMacBase[portId],
-		  IX_ETH_ACC_MAC_RX_CNTRL1,
-		  rxregval | IX_ETH_ACC_RX_CNTRL1_PAUSE_EN);
-	ixEthAccMacState[portId].fullDuplex = true;
-
-    }
-    else if (mode ==  IX_ETH_ACC_HALF_DUPLEX)
-    {
-	/*Set half duplex bit in TX*/
-	REG_WRITE(ixEthAccMacBase[portId],
-		  IX_ETH_ACC_MAC_TX_CNTRL1,
-		  txregval | IX_ETH_ACC_TX_CNTRL1_DUPLEX);
-
-	/*We must clear pause enable in the receive logic when in
-	  half duplex mode*/
-	REG_WRITE(ixEthAccMacBase[portId],
-		  IX_ETH_ACC_MAC_RX_CNTRL1,
-		  rxregval & ~IX_ETH_ACC_RX_CNTRL1_PAUSE_EN);
-
-	ixEthAccMacState[portId].fullDuplex = false;
-    }
-    else
-    {
-	return IX_ETH_ACC_FAIL;
-    }
-
-
-    return IX_ETH_ACC_SUCCESS;
-
-}
-
-
-
-IxEthAccStatus
-ixEthAccPortDuplexModeGetPriv (IxEthAccPortId portId,
-			   IxEthAccDuplexMode *mode)
-{
-    /*Return the duplex mode for the specified port*/
-    UINT32 regval;
-
-    /*This is bit 1 of the transmit control reg, set to 1 for half
-      duplex, 0 for full duplex*/
-    IX_ETH_ACC_VALIDATE_PORT_ID(portId);
-
-    if (IX_ETH_ACC_SUCCESS != ixEthAccSingleEthNpeCheck(portId))
-    {
-        IX_ETH_ACC_WARNING_LOG("EthAcc: Unavailable Eth %d: Cannot get Duplex Mode.\n",(INT32)portId,0,0,0,0,0);
-        /* return hald duplex */
-        *mode = IX_ETH_ACC_HALF_DUPLEX ;
-        return IX_ETH_ACC_SUCCESS ;
-    }
-
-    if (!IX_ETH_IS_PORT_INITIALIZED(portId))
-    {
-	return (IX_ETH_ACC_PORT_UNINITIALIZED);
-    }
-
-    if (mode == NULL)
-    {
-	return (IX_ETH_ACC_FAIL);
-    }
-
-    REG_READ(ixEthAccMacBase[portId],
-	     IX_ETH_ACC_MAC_TX_CNTRL1,
-	     regval);
-
-    if( regval & IX_ETH_ACC_TX_CNTRL1_DUPLEX)
-    {
-	*mode = IX_ETH_ACC_HALF_DUPLEX;
-    }
-    else
-    {
-	*mode = IX_ETH_ACC_FULL_DUPLEX;
-    }
-
-    return IX_ETH_ACC_SUCCESS;
-}
-
-
-
-IxEthAccStatus
-ixEthAccPortTxFrameAppendPaddingEnablePriv (IxEthAccPortId portId)
-{
-    UINT32 regval;
-    /*Enable FCS computation by the MAC and appending to the
-      frame*/
-
-    IX_ETH_ACC_VALIDATE_PORT_ID(portId);
-
-    if (IX_ETH_ACC_SUCCESS != ixEthAccSingleEthNpeCheck(portId))
-    {
-        IX_ETH_ACC_WARNING_LOG("EthAcc: Unavailable Eth %d: Cannot enable Tx Frame Append Padding.\n",(INT32)portId,0,0,0,0,0);
-        return IX_ETH_ACC_SUCCESS ;
-    }
-
-    if (!IX_ETH_IS_PORT_INITIALIZED(portId))
-    {
-	return (IX_ETH_ACC_PORT_UNINITIALIZED);
-    }
-
-    REG_READ(ixEthAccMacBase[portId],
-	     IX_ETH_ACC_MAC_TX_CNTRL1,
-	     regval);
-
-    REG_WRITE(ixEthAccMacBase[portId],
-	      IX_ETH_ACC_MAC_TX_CNTRL1,
-	      regval |
-	      IX_ETH_ACC_TX_CNTRL1_PAD_EN);
-
-    ixEthAccMacState[portId].txPADAppend = true;
-    return IX_ETH_ACC_SUCCESS;
-}
-
-IxEthAccStatus
-ixEthAccPortTxFrameAppendPaddingDisablePriv (IxEthAccPortId portId)
-{
-    UINT32 regval;
-
-    /*disable FCS computation and appending*/
-    /*Set bit 4 of Tx control register one to zero*/
-    IX_ETH_ACC_VALIDATE_PORT_ID(portId);
-
-    if (IX_ETH_ACC_SUCCESS != ixEthAccSingleEthNpeCheck(portId))
-    {
-        IX_ETH_ACC_WARNING_LOG("EthAcc: Unavailable Eth %d: Cannot disble Tx Frame Append Padding.\n",(INT32)portId,0,0,0,0,0);
-        return IX_ETH_ACC_SUCCESS ;
-    }
-
-    if (!IX_ETH_IS_PORT_INITIALIZED(portId))
-    {
-	return (IX_ETH_ACC_PORT_UNINITIALIZED);
-    }
-
-    REG_READ(ixEthAccMacBase[portId],
-	     IX_ETH_ACC_MAC_TX_CNTRL1,
-	     regval);
-
-    REG_WRITE(ixEthAccMacBase[portId],
-	      IX_ETH_ACC_MAC_TX_CNTRL1,
-	      regval & ~IX_ETH_ACC_TX_CNTRL1_PAD_EN);
-
-    ixEthAccMacState[portId].txPADAppend = false;
-    return IX_ETH_ACC_SUCCESS;
-}
-
-IxEthAccStatus
-ixEthAccPortTxFrameAppendFCSEnablePriv (IxEthAccPortId portId)
-{
-    UINT32 regval;
-
-    /*Enable FCS computation by the MAC and appending to the
-      frame*/
-
-    IX_ETH_ACC_VALIDATE_PORT_ID(portId);
-
-    if (IX_ETH_ACC_SUCCESS != ixEthAccSingleEthNpeCheck(portId))
-    {
-        IX_ETH_ACC_WARNING_LOG("EthAcc: Unavailable Eth %d: Cannot enable Tx Frame Append FCS.\n",(INT32)portId,0,0,0,0,0);
-        return IX_ETH_ACC_SUCCESS ;
-    }
-
-    if (!IX_ETH_IS_PORT_INITIALIZED(portId))
-    {
-	return (IX_ETH_ACC_PORT_UNINITIALIZED);
-    }
-
-    REG_READ(ixEthAccMacBase[portId],
-	     IX_ETH_ACC_MAC_TX_CNTRL1,
-	     regval);
-
-    REG_WRITE(ixEthAccMacBase[portId],
-	      IX_ETH_ACC_MAC_TX_CNTRL1,
-	      regval | IX_ETH_ACC_TX_CNTRL1_FCS_EN);
-
-    ixEthAccMacState[portId].txFCSAppend = true;
-    return IX_ETH_ACC_SUCCESS;
-}
-
-IxEthAccStatus
-ixEthAccPortTxFrameAppendFCSDisablePriv (IxEthAccPortId portId)
-{
-    UINT32 regval;
-
-    /*disable FCS computation and appending*/
-    /*Set bit 4 of Tx control register one to zero*/
-    IX_ETH_ACC_VALIDATE_PORT_ID(portId);
-
-    if (IX_ETH_ACC_SUCCESS != ixEthAccSingleEthNpeCheck(portId))
-    {
-        IX_ETH_ACC_WARNING_LOG("EthAcc: Unavailable Eth %d: Cannot disable Tx Frame Append FCS.\n",(INT32)portId,0,0,0,0,0);
-        return IX_ETH_ACC_SUCCESS ;
-    }
-
-    if (!IX_ETH_IS_PORT_INITIALIZED(portId))
-    {
-	return (IX_ETH_ACC_PORT_UNINITIALIZED);
-    }
-
-    REG_READ(ixEthAccMacBase[portId],
-	     IX_ETH_ACC_MAC_TX_CNTRL1,
-	     regval);
-
-    REG_WRITE(ixEthAccMacBase[portId],
-	      IX_ETH_ACC_MAC_TX_CNTRL1,
-	      regval & ~IX_ETH_ACC_TX_CNTRL1_FCS_EN);
-
-    ixEthAccMacState[portId].txFCSAppend = false;
-    return IX_ETH_ACC_SUCCESS;
-}
-
-IxEthAccStatus
-ixEthAccPortRxFrameAppendFCSEnablePriv (IxEthAccPortId portId)
-{
-    /*Set bit 2 of Rx control 1*/
-    UINT32 regval;
-
-    IX_ETH_ACC_VALIDATE_PORT_ID(portId);
-
-    if (IX_ETH_ACC_SUCCESS != ixEthAccSingleEthNpeCheck(portId))
-    {
-        IX_ETH_ACC_WARNING_LOG("EthAcc: Unavailable Eth %d: Cannot enable Rx Frame Append FCS.\n",(INT32)portId,0,0,0,0,0);
-        return IX_ETH_ACC_SUCCESS ;
-    }
-
-    if (!IX_ETH_IS_PORT_INITIALIZED(portId))
-    {
-	return (IX_ETH_ACC_PORT_UNINITIALIZED);
-    }
-
-    REG_READ(ixEthAccMacBase[portId],
-	     IX_ETH_ACC_MAC_RX_CNTRL1,
-	     regval);
-
-    REG_WRITE(ixEthAccMacBase[portId],
-	      IX_ETH_ACC_MAC_RX_CNTRL1,
-	      regval | IX_ETH_ACC_RX_CNTRL1_CRC_EN);
-
-    ixEthAccMacState[portId].rxFCSAppend = true;
-    return IX_ETH_ACC_SUCCESS;
-}
-
-IxEthAccStatus
-ixEthAccPortRxFrameAppendFCSDisablePriv (IxEthAccPortId portId)
-{
-    UINT32 regval;
-
-    /*Clear bit 2 of Rx control 1*/
-    IX_ETH_ACC_VALIDATE_PORT_ID(portId);
-
-    if (IX_ETH_ACC_SUCCESS != ixEthAccSingleEthNpeCheck(portId))
-    {
-        IX_ETH_ACC_WARNING_LOG("EthAcc: Unavailable Eth %d: Cannot disable Rx Frame Append FCS.\n",(INT32)portId,0,0,0,0,0);
-        return IX_ETH_ACC_SUCCESS ;
-    }
-
-    if (!IX_ETH_IS_PORT_INITIALIZED(portId))
-    {
-	return (IX_ETH_ACC_PORT_UNINITIALIZED);
-    }
-
-    REG_READ(ixEthAccMacBase[portId],
-	     IX_ETH_ACC_MAC_RX_CNTRL1,
-	     regval);
-
-    REG_WRITE(ixEthAccMacBase[portId],
-	      IX_ETH_ACC_MAC_RX_CNTRL1,
-	      regval & ~IX_ETH_ACC_RX_CNTRL1_CRC_EN);
-
-    ixEthAccMacState[portId].rxFCSAppend = false;
-    return IX_ETH_ACC_SUCCESS;
-}
-
-
-
-PRIVATE void
-ixEthAccMacNpeStatsMessageCallback (IxNpeMhNpeId npeId,
-				    IxNpeMhMessage msg)
-{
-    IxEthAccPortId portId = IX_ETH_ACC_NPE_TO_PORT_ID(npeId);
-
-#ifndef NDEBUG
-    /* Prudent to at least check the port is within range */
-    if (portId >= IX_ETH_ACC_NUMBER_OF_PORTS)
-    {
-	IX_ETH_ACC_FATAL_LOG(
-     "IXETHACC:ixEthAccMacNpeStatsMessageCallback: Illegal port: %u\n",
-     (UINT32)portId, 0, 0, 0, 0, 0);
-	return;
-    }
-#endif
-
-    /*Unblock Stats Get call*/
-    ixOsalMutexUnlock(&ixEthAccMacState[portId].ackMIBStatsLock);
-
-}
-
-PRIVATE void
-ixEthAccMibIIStatsEndianConvert (IxEthEthObjStats *retStats)
-{
-    /* endianness conversion */
-
-    /* Rx stats */
-    retStats->dot3StatsAlignmentErrors =
-	IX_OSAL_SWAP_BE_SHARED_LONG(retStats->dot3StatsAlignmentErrors);
-    retStats->dot3StatsFCSErrors =
-	IX_OSAL_SWAP_BE_SHARED_LONG(retStats->dot3StatsFCSErrors);
-    retStats->dot3StatsInternalMacReceiveErrors =
-	IX_OSAL_SWAP_BE_SHARED_LONG(retStats->dot3StatsInternalMacReceiveErrors);
-    retStats->RxOverrunDiscards =
-	IX_OSAL_SWAP_BE_SHARED_LONG(retStats->RxOverrunDiscards);
-    retStats->RxLearnedEntryDiscards =
-	IX_OSAL_SWAP_BE_SHARED_LONG(retStats->RxLearnedEntryDiscards);
-    retStats->RxLargeFramesDiscards =
-	IX_OSAL_SWAP_BE_SHARED_LONG(retStats->RxLargeFramesDiscards);
-    retStats->RxSTPBlockedDiscards =
-	IX_OSAL_SWAP_BE_SHARED_LONG(retStats->RxSTPBlockedDiscards);
-    retStats->RxVLANTypeFilterDiscards =
-	IX_OSAL_SWAP_BE_SHARED_LONG(retStats->RxVLANTypeFilterDiscards);
-    retStats->RxVLANIdFilterDiscards =
-	IX_OSAL_SWAP_BE_SHARED_LONG(retStats->RxVLANIdFilterDiscards);
-    retStats->RxInvalidSourceDiscards =
-	IX_OSAL_SWAP_BE_SHARED_LONG(retStats->RxInvalidSourceDiscards);
-    retStats->RxBlackListDiscards =
-	IX_OSAL_SWAP_BE_SHARED_LONG(retStats->RxBlackListDiscards);
-    retStats->RxWhiteListDiscards =
-	IX_OSAL_SWAP_BE_SHARED_LONG(retStats->RxWhiteListDiscards);
-    retStats->RxUnderflowEntryDiscards =
-	IX_OSAL_SWAP_BE_SHARED_LONG(retStats->RxUnderflowEntryDiscards);
-
-    /* Tx stats */
-    retStats->dot3StatsSingleCollisionFrames =
-	IX_OSAL_SWAP_BE_SHARED_LONG(retStats->dot3StatsSingleCollisionFrames);
-    retStats->dot3StatsMultipleCollisionFrames =
-	IX_OSAL_SWAP_BE_SHARED_LONG(retStats->dot3StatsMultipleCollisionFrames);
-    retStats->dot3StatsDeferredTransmissions =
-	IX_OSAL_SWAP_BE_SHARED_LONG(retStats->dot3StatsDeferredTransmissions);
-    retStats->dot3StatsLateCollisions =
-	IX_OSAL_SWAP_BE_SHARED_LONG(retStats->dot3StatsLateCollisions);
-    retStats->dot3StatsExcessiveCollsions =
-	IX_OSAL_SWAP_BE_SHARED_LONG(retStats->dot3StatsExcessiveCollsions);
-    retStats->dot3StatsInternalMacTransmitErrors =
-	IX_OSAL_SWAP_BE_SHARED_LONG(retStats->dot3StatsInternalMacTransmitErrors);
-    retStats->dot3StatsCarrierSenseErrors =
-	IX_OSAL_SWAP_BE_SHARED_LONG(retStats->dot3StatsCarrierSenseErrors);
-    retStats->TxLargeFrameDiscards =
-	IX_OSAL_SWAP_BE_SHARED_LONG(retStats->TxLargeFrameDiscards);
-    retStats->TxVLANIdFilterDiscards =
-	IX_OSAL_SWAP_BE_SHARED_LONG(retStats->TxVLANIdFilterDiscards);
-}
-
-IxEthAccStatus
-ixEthAccMibIIStatsGet (IxEthAccPortId portId,
-		       IxEthEthObjStats *retStats )
-{
-    IxNpeMhMessage message;
-
-    if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED())
-    {
-        printf("EthAcc: ixEthAccMibIIStatsGet (Mac) EthAcc service is not initialized\n");
-	return (IX_ETH_ACC_FAIL);
-    }
-
-    IX_ETH_ACC_VALIDATE_PORT_ID(portId);
-
-    if (retStats == NULL)
-    {
-        printf("EthAcc: ixEthAccMibIIStatsGet (Mac) NULL argument\n");
-	return (IX_ETH_ACC_FAIL);
-    }
-
-    if (IX_ETH_ACC_SUCCESS != ixEthAccSingleEthNpeCheck(portId))
-    {
-        printf("EthAcc: ixEthAccMibIIStatsGet (Mac) NPE for port %d is not available\n", portId);
-
-        IX_ETH_ACC_WARNING_LOG("EthAcc: Unavailable Eth %d: Cannot get MIB II Stats.\n",(INT32)portId,0,0,0,0,0);
-
-        /* Return all zero stats */
-        IX_ETH_ACC_MEMSET(retStats, 0, sizeof(IxEthEthObjStats));
-
-        return IX_ETH_ACC_SUCCESS ;
-    }
-
-    if (!IX_ETH_IS_PORT_INITIALIZED(portId))
-    {
-        printf("EthAcc: ixEthAccMibIIStatsGet (Mac) port %d is not initialized\n", portId);
-	return (IX_ETH_ACC_PORT_UNINITIALIZED);
-    }
-
-    IX_OSAL_CACHE_INVALIDATE(retStats, sizeof(IxEthEthObjStats));
-
-    message.data[0] = IX_ETHNPE_GETSTATS << IX_ETH_ACC_MAC_MSGID_SHL;
-    message.data[1] = (UINT32) IX_OSAL_MMU_VIRT_TO_PHYS(retStats);
-
-    /* Permit only one task to request MIB statistics Get operation
-       at a time */
-    ixOsalMutexLock(&ixEthAccMacState[portId].MIBStatsGetAccessLock, IX_OSAL_WAIT_FOREVER);
-
-    if(ixNpeMhMessageWithResponseSend(IX_ETH_ACC_PORT_TO_NPE_ID(portId),
-				      message,
-				      IX_ETHNPE_GETSTATS,
-				      ixEthAccMacNpeStatsMessageCallback,
-				      IX_NPEMH_SEND_RETRIES_DEFAULT)
-       != IX_SUCCESS)
-    {
-	ixOsalMutexUnlock(&ixEthAccMacState[portId].MIBStatsGetAccessLock);
-
-        printf("EthAcc: (Mac) StatsGet failed to send NPE message\n");
-
-	return IX_ETH_ACC_FAIL;
-    }
-
-    /* Wait for callback invocation indicating response to
-       this request - we need this mutex in order to ensure
-       that the return from this function is synchronous */
-    ixOsalMutexLock(&ixEthAccMacState[portId].ackMIBStatsLock, IX_ETH_ACC_MIB_STATS_DELAY_MSECS);
-
-    /* Permit other tasks to perform MIB statistics Get operation */
-    ixOsalMutexUnlock(&ixEthAccMacState[portId].MIBStatsGetAccessLock);
-
-    ixEthAccMibIIStatsEndianConvert (retStats);
-
-    return IX_ETH_ACC_SUCCESS;
-}
-
-
-PRIVATE void
-ixEthAccMacNpeStatsResetMessageCallback (IxNpeMhNpeId npeId,
-					 IxNpeMhMessage msg)
-{
-    IxEthAccPortId portId = IX_ETH_ACC_NPE_TO_PORT_ID(npeId);
-
-#ifndef NDEBUG
-    /* Prudent to at least check the port is within range */
-    if (portId >= IX_ETH_ACC_NUMBER_OF_PORTS)
-    {
-	IX_ETH_ACC_FATAL_LOG(
-     "IXETHACC:ixEthAccMacNpeStatsResetMessageCallback: Illegal port: %u\n",
-     (UINT32)portId, 0, 0, 0, 0, 0);
-	return;
-    }
-#endif
-
-    /*Unblock Stats Get & reset call*/
-    ixOsalMutexUnlock(&ixEthAccMacState[portId].ackMIBStatsResetLock);
-
-}
-
-
-
-IxEthAccStatus
-ixEthAccMibIIStatsGetClear (IxEthAccPortId portId,
-			    IxEthEthObjStats *retStats)
-{
-    IxNpeMhMessage message;
-
-    if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED())
-    {
-        printf("EthAcc: ixEthAccMibIIStatsGetClear (Mac) EthAcc service is not initialized\n");
-	return (IX_ETH_ACC_FAIL);
-    }
-
-    IX_ETH_ACC_VALIDATE_PORT_ID(portId);
-
-    if (retStats == NULL)
-    {
-        printf("EthAcc: ixEthAccMibIIStatsGetClear (Mac) NULL argument\n");
-	return (IX_ETH_ACC_FAIL);
-    }
-
-    if (IX_ETH_ACC_SUCCESS != ixEthAccSingleEthNpeCheck(portId))
-    {
-        printf("EthAcc: ixEthAccMibIIStatsGetClear (Mac) NPE for port %d is not available\n", portId);
-
-        IX_ETH_ACC_WARNING_LOG("EthAcc: Unavailable Eth %d: Cannot get and clear MIB II Stats.\n", (INT32)portId, 0, 0, 0, 0, 0);
-
-        /* Return all zero stats */
-        IX_ETH_ACC_MEMSET(retStats, 0, sizeof(IxEthEthObjStats));
-
-        return IX_ETH_ACC_SUCCESS ;
-    }
-
-    if (!IX_ETH_IS_PORT_INITIALIZED(portId))
-    {
-        printf("EthAcc: ixEthAccMibIIStatsGetClear (Mac) port %d is not initialized\n", portId);
-	return (IX_ETH_ACC_PORT_UNINITIALIZED);
-    }
-
-    IX_OSAL_CACHE_INVALIDATE(retStats, sizeof(IxEthEthObjStats));
-
-    message.data[0] = IX_ETHNPE_RESETSTATS << IX_ETH_ACC_MAC_MSGID_SHL;
-    message.data[1] = (UINT32) IX_OSAL_MMU_VIRT_TO_PHYS(retStats);
-
-    /* Permit only one task to request MIB statistics Get-Reset operation at a time */
-    ixOsalMutexLock(&ixEthAccMacState[portId].MIBStatsGetResetAccessLock, IX_OSAL_WAIT_FOREVER);
-
-    if(ixNpeMhMessageWithResponseSend(IX_ETH_ACC_PORT_TO_NPE_ID(portId),
-				      message,
-				      IX_ETHNPE_RESETSTATS,
-				      ixEthAccMacNpeStatsResetMessageCallback,
-				      IX_NPEMH_SEND_RETRIES_DEFAULT)
-       != IX_SUCCESS)
-    {
-	ixOsalMutexUnlock(&ixEthAccMacState[portId].MIBStatsGetResetAccessLock);
-
-        printf("EthAcc: (Mac) ixEthAccMibIIStatsGetClear failed to send NPE message\n");
-
-	return IX_ETH_ACC_FAIL;
-    }
-
-    /* Wait for callback invocation indicating response to this request */
-    ixOsalMutexLock(&ixEthAccMacState[portId].ackMIBStatsResetLock, IX_ETH_ACC_MIB_STATS_DELAY_MSECS);
-
-    /* permit other tasks to get and reset MIB stats*/
-    ixOsalMutexUnlock(&ixEthAccMacState[portId].MIBStatsGetResetAccessLock);
-
-    ixEthAccMibIIStatsEndianConvert(retStats);
-
-    return IX_ETH_ACC_SUCCESS;
-}
-
-IxEthAccStatus
-ixEthAccMibIIStatsClear (IxEthAccPortId portId)
-{
-    static IxEthEthObjStats retStats;
-    IxEthAccStatus status;
-
-    if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED())
-    {
-	return (IX_ETH_ACC_FAIL);
-    }
-
-    IX_ETH_ACC_VALIDATE_PORT_ID(portId);
-
-    if (IX_ETH_ACC_SUCCESS != ixEthAccSingleEthNpeCheck(portId))
-    {
-        IX_ETH_ACC_WARNING_LOG("EthAcc: Unavailable Eth %d: Cannot clear MIB II Stats.\n",(INT32)portId,0,0,0,0,0);
-        return IX_ETH_ACC_SUCCESS ;
-    }
-
-    /* there is no reset operation without a corresponding Get */
-    status = ixEthAccMibIIStatsGetClear(portId, &retStats);
-
-    return status;
-}
-
-/* Initialize the ethernet MAC settings */
-IxEthAccStatus
-ixEthAccMacInit(IxEthAccPortId portId)
-{
-    IX_OSAL_MBUF_POOL* portDisablePool;
-    UINT8 *data;
-
-    IX_ETH_ACC_VALIDATE_PORT_ID(portId);
-
-    if (IX_ETH_ACC_SUCCESS != ixEthAccSingleEthNpeCheck(portId))
-    {
-        IX_ETH_ACC_WARNING_LOG("EthAcc: Unavailable Eth %d: Cannot initialize Mac.\n",(INT32)portId,0,0,0,0,0);
-        return IX_ETH_ACC_SUCCESS ;
-    }
-
-    if(ixEthAccMacState[portId].macInitialised == false)
-    {
-	ixEthAccMacState[portId].fullDuplex  = true;
-	ixEthAccMacState[portId].rxFCSAppend = true;
-	ixEthAccMacState[portId].txFCSAppend = true;
-	ixEthAccMacState[portId].txPADAppend = true;
-	ixEthAccMacState[portId].enabled     = false;
-	ixEthAccMacState[portId].promiscuous = true;
-	ixEthAccMacState[portId].joinAll     = false;
-	ixEthAccMacState[portId].initDone    = false;
-	ixEthAccMacState[portId].macInitialised = true;
-
-        /* initialize MIB stats mutexes */
-        ixOsalMutexInit(&ixEthAccMacState[portId].ackMIBStatsLock);
-        ixOsalMutexLock(&ixEthAccMacState[portId].ackMIBStatsLock, IX_OSAL_WAIT_FOREVER);
-
-        ixOsalMutexInit(&ixEthAccMacState[portId].ackMIBStatsResetLock);
-        ixOsalMutexLock(&ixEthAccMacState[portId].ackMIBStatsResetLock, IX_OSAL_WAIT_FOREVER);
-
-        ixOsalMutexInit(&ixEthAccMacState[portId].MIBStatsGetAccessLock);
-
-        ixOsalMutexInit(&ixEthAccMacState[portId].MIBStatsGetResetAccessLock);
-
-        ixOsalMutexInit(&ixEthAccMacState[portId].npeLoopbackMessageLock);
-
-	ixEthAccMacState[portId].portDisableRxMbufPtr = NULL;
-        ixEthAccMacState[portId].portDisableTxMbufPtr = NULL;
-
-	portDisablePool = IX_OSAL_MBUF_POOL_INIT(2,
-			  IX_ETHACC_RX_MBUF_MIN_SIZE,
-			  "portDisable Pool");
-
-        IX_OSAL_ENSURE(portDisablePool != NULL, "Failed to initialize PortDisable pool");
-
-	ixEthAccMacState[portId].portDisableRxMbufPtr = IX_OSAL_MBUF_POOL_GET(portDisablePool);
-        ixEthAccMacState[portId].portDisableTxMbufPtr = IX_OSAL_MBUF_POOL_GET(portDisablePool);
-
-	IX_OSAL_ENSURE(ixEthAccMacState[portId].portDisableRxMbufPtr != NULL,
-		  "Pool allocation failed");
-        IX_OSAL_ENSURE(ixEthAccMacState[portId].portDisableTxMbufPtr != NULL,
-		  "Pool allocation failed");
-	/* fill the payload of the Rx mbuf used in portDisable */
-        IX_OSAL_MBUF_MLEN(ixEthAccMacState[portId].portDisableRxMbufPtr) = IX_ETHACC_RX_MBUF_MIN_SIZE;
-
-        memset(IX_OSAL_MBUF_MDATA(ixEthAccMacState[portId].portDisableRxMbufPtr),
-	       0xAA,
-	       IX_ETHACC_RX_MBUF_MIN_SIZE);
-
-	/* fill the payload of the Tx mbuf used in portDisable (64 bytes) */
-        IX_OSAL_MBUF_MLEN(ixEthAccMacState[portId].portDisableTxMbufPtr) = 64;
-        IX_OSAL_MBUF_PKT_LEN(ixEthAccMacState[portId].portDisableTxMbufPtr) = 64;
-
-        data = (UINT8 *) IX_OSAL_MBUF_MDATA(ixEthAccMacState[portId].portDisableTxMbufPtr);
-        memset(data, 0xBB, 64);
-        data[0] = 0x00; /* unicast destination MAC address */
-        data[6] = 0x00; /* unicast source MAC address */
-        data[12] = 0x08; /* typelength : IP frame */
-        data[13] = 0x00; /* typelength : IP frame */
-
-	IX_OSAL_CACHE_FLUSH(data, 64);
-    }
-
-    IX_OSAL_ASSERT (ixEthAccMacBase[portId] != 0);
-
-    REG_WRITE(ixEthAccMacBase[portId],
-	      IX_ETH_ACC_MAC_CORE_CNTRL,
-	      IX_ETH_ACC_CORE_RESET);
-
-    ixOsalSleep(IX_ETH_ACC_MAC_RESET_DELAY);
-
-    REG_WRITE(ixEthAccMacBase[portId],
-	      IX_ETH_ACC_MAC_CORE_CNTRL,
-	      IX_ETH_ACC_CORE_MDC_EN);
-
-    REG_WRITE(ixEthAccMacBase[portId],
-	      IX_ETH_ACC_MAC_INT_CLK_THRESH,
-	      IX_ETH_ACC_MAC_INT_CLK_THRESH_DEFAULT);
-
-    ixEthAccMacStateUpdate(portId);
-
-    return IX_ETH_ACC_SUCCESS;
-}
-
-/* PRIVATE Functions*/
-
-PRIVATE void
-ixEthAccMacStateUpdate(IxEthAccPortId portId)
-{
-    UINT32 regval;
-
-    if ( ixEthAccMacState[portId].enabled == false )
-    {
-	/*  Just disable both the transmitter and reciver in the MAC.  */
-        REG_READ(ixEthAccMacBase[portId],
-		 IX_ETH_ACC_MAC_RX_CNTRL1,
-		 regval);
-	REG_WRITE(ixEthAccMacBase[portId],
-		  IX_ETH_ACC_MAC_RX_CNTRL1,
-		  regval & ~IX_ETH_ACC_RX_CNTRL1_RX_EN);
-
-        REG_READ(ixEthAccMacBase[portId],
-		 IX_ETH_ACC_MAC_TX_CNTRL1,
-		 regval);
-	REG_WRITE(ixEthAccMacBase[portId],
-		  IX_ETH_ACC_MAC_TX_CNTRL1,
-		  regval & ~IX_ETH_ACC_TX_CNTRL1_TX_EN);
-    }
-
-    if(ixEthAccMacState[portId].fullDuplex)
-    {
-	ixEthAccPortDuplexModeSetPriv (portId, IX_ETH_ACC_FULL_DUPLEX);
-    }
-    else
-    {
-	ixEthAccPortDuplexModeSetPriv (portId, IX_ETH_ACC_HALF_DUPLEX);
-    }
-
-    if(ixEthAccMacState[portId].rxFCSAppend)
-    {
-	ixEthAccPortRxFrameAppendFCSEnablePriv (portId);
-    }
-    else
-    {
-	ixEthAccPortRxFrameAppendFCSDisablePriv (portId);
-    }
-
-    if(ixEthAccMacState[portId].txFCSAppend)
-    {
-	ixEthAccPortTxFrameAppendFCSEnablePriv (portId);
-    }
-    else
-    {
-	ixEthAccPortTxFrameAppendFCSDisablePriv (portId);
-    }
-
-    if(ixEthAccMacState[portId].txPADAppend)
-    {
-	ixEthAccPortTxFrameAppendPaddingEnablePriv (portId);
-    }
-    else
-    {
-	ixEthAccPortTxFrameAppendPaddingDisablePriv (portId);
-    }
-
-    if(ixEthAccMacState[portId].promiscuous)
-    {
-	ixEthAccPortPromiscuousModeSetPriv(portId);
-    }
-    else
-    {
-	ixEthAccPortPromiscuousModeClearPriv(portId);
-    }
-
-    if ( ixEthAccMacState[portId].enabled == true )
-    {
-        /*   Enable both the transmitter and reciver in the MAC.  */
-        REG_READ(ixEthAccMacBase[portId],
-		 IX_ETH_ACC_MAC_RX_CNTRL1,
-		 regval);
-        REG_WRITE(ixEthAccMacBase[portId],
-		  IX_ETH_ACC_MAC_RX_CNTRL1,
-		  regval | IX_ETH_ACC_RX_CNTRL1_RX_EN);
-
-        REG_READ(ixEthAccMacBase[portId],
-		 IX_ETH_ACC_MAC_TX_CNTRL1,
-		 regval);
-	REG_WRITE(ixEthAccMacBase[portId],
-		  IX_ETH_ACC_MAC_TX_CNTRL1,
-		  regval | IX_ETH_ACC_TX_CNTRL1_TX_EN);
-    }
-}
-
-
-PRIVATE BOOL
-ixEthAccMacEqual(IxEthAccMacAddr *macAddr1,
-		 IxEthAccMacAddr *macAddr2)
-{
-    UINT32 i;
-    for(i=0;i<IX_IEEE803_MAC_ADDRESS_SIZE; i++)
-    {
-	if(macAddr1->macAddress[i] != macAddr2->macAddress[i])
-	{
-	    return false;
-	}
-    }
-    return true;
-}
-
-PRIVATE void
-ixEthAccMacPrint(IxEthAccMacAddr *m)
-{
-    printf("%2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x",
-	   m->macAddress[0], m->macAddress[1],
-	   m->macAddress[2], m->macAddress[3],
-	   m->macAddress[4], m->macAddress[5]);
-}
-
-/* Set the multicast address and address mask registers
- *
- * A bit in the address mask register must be set if
- * all multicast addresses always have that bit set, or if
- * all multicast addresses always have that bit cleared.
- *
- * A bit in the address register must be set if all multicast
- * addresses have that bit set, otherwise, it should be cleared
- */
-
-PRIVATE void
-ixEthAccMulticastAddressSet(IxEthAccPortId portId)
-{
-    UINT32 i;
-    UINT32 j;
-    IxEthAccMacAddr addressMask;
-    IxEthAccMacAddr address;
-    IxEthAccMacAddr alwaysClearBits;
-    IxEthAccMacAddr alwaysSetBits;
-
-    /* calculate alwaysClearBits and alwaysSetBits:
-     * alwaysClearBits is calculated by ORing all
-     * multicast addresses, those bits that are always
-     * clear are clear in the result
-     *
-     * alwaysSetBits is calculated by ANDing all
-     * multicast addresses, those bits that are always set
-     * are set in the result
-     */
-
-    if (ixEthAccMacState[portId].promiscuous == true)
-    {
-	/* Promiscuous Mode is set, and filtering
-	 * allow all packets, and enable the mcast and
-	 * bcast detection.
-	 */
-	memset(&addressMask.macAddress,
-	       0,
-	       IX_IEEE803_MAC_ADDRESS_SIZE);
-	memset(&address.macAddress,
-	       0,
-	       IX_IEEE803_MAC_ADDRESS_SIZE);
-    }
-    else
-    {
-	if(ixEthAccMacState[portId].joinAll == true)
-	{
-	    /* Join all is set. The mask and address are
-	     * the multicast settings.
-	     */
-	    IxEthAccMacAddr macAddr = {{0x1,0x0,0x0,0x0,0x0,0x0}};
-
-	    memcpy(addressMask.macAddress,
-		   macAddr.macAddress,
-		   IX_IEEE803_MAC_ADDRESS_SIZE);
-	    memcpy(address.macAddress,
-		   macAddr.macAddress,
-		   IX_IEEE803_MAC_ADDRESS_SIZE);
-	}
-	else if(ixEthAccMacState[portId].mcastAddrIndex == 0)
-	{
-	    /* No entry in the filtering database,
-	     * Promiscuous Mode is cleared, Broadcast filtering
-	     * is configured.
-	     */
-	    memset(addressMask.macAddress,
-		   IX_ETH_ACC_MAC_ALL_BITS_SET,
-		   IX_IEEE803_MAC_ADDRESS_SIZE);
-	    memset(address.macAddress,
-		   IX_ETH_ACC_MAC_ALL_BITS_SET,
-		   IX_IEEE803_MAC_ADDRESS_SIZE);
-	}
-	else
-	{
-	    /* build a mask and an address which mix all entreis
-	     * from the list of multicast addresses
-	     */
-	    memset(alwaysClearBits.macAddress,
-		   0,
-		   IX_IEEE803_MAC_ADDRESS_SIZE);
-	    memset(alwaysSetBits.macAddress,
-		   IX_ETH_ACC_MAC_ALL_BITS_SET,
-		   IX_IEEE803_MAC_ADDRESS_SIZE);
-
-	    for(i=0;i<ixEthAccMacState[portId].mcastAddrIndex;i++)
-	    {
-		for(j=0;j<IX_IEEE803_MAC_ADDRESS_SIZE;j++)
-		{
-		    alwaysClearBits.macAddress[j] |=
-			ixEthAccMacState[portId].mcastAddrsTable[i].macAddress[j];
-		    alwaysSetBits.macAddress[j] &=
-			ixEthAccMacState[portId].mcastAddrsTable[i].macAddress[j];
-		}
-	    }
-
-	    for(i=0;i<IX_IEEE803_MAC_ADDRESS_SIZE;i++)
-	    {
-		addressMask.macAddress[i] = alwaysSetBits.macAddress[i]
-		    | ~alwaysClearBits.macAddress[i];
-		address.macAddress[i] = alwaysSetBits.macAddress[i];
-	    }
-	}
-    }
-
-    /*write the new addr filtering to h/w*/
-    for(i=0;i<IX_IEEE803_MAC_ADDRESS_SIZE;i++)
-    {
-	REG_WRITE(ixEthAccMacBase[portId],
-		  IX_ETH_ACC_MAC_ADDR_MASK_1+i*sizeof(UINT32),
-		  addressMask.macAddress[i]);
-	REG_WRITE(ixEthAccMacBase[portId],
-		  IX_ETH_ACC_MAC_ADDR_1+i*sizeof(UINT32),
-		  address.macAddress[i]);
-    }
-}
diff --git a/drivers/net/npe/IxEthAccMii.c b/drivers/net/npe/IxEthAccMii.c
deleted file mode 100644
index bfe606f507..0000000000
--- a/drivers/net/npe/IxEthAccMii.c
+++ /dev/null
@@ -1,386 +0,0 @@
-/**
- * @file IxEthAccMii.c
- *
- * @author Intel Corporation
- * @date 
- *
- * @brief  MII control functions
- *
- * Design Notes:
- *
- * IXP400 SW Release version 2.0
- * 
- * -- Copyright Notice --
- * 
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- * 
- * @par
- * SPDX-License-Identifier:	BSD-3-Clause
- * @par
- * -- End of Copyright Notice --
- */
-
-#include "IxOsal.h"
-#include "IxEthAcc.h"
-#include "IxEthAcc_p.h"
-#include "IxEthAccMac_p.h"
-#include "IxEthAccMii_p.h"
-
-
-PRIVATE UINT32 miiBaseAddressVirt;
-PRIVATE IxOsalMutex miiAccessLock;
-
-PUBLIC UINT32 ixEthAccMiiRetryCount    = IX_ETH_ACC_MII_TIMEOUT_10TH_SECS;
-PUBLIC UINT32 ixEthAccMiiAccessTimeout = IX_ETH_ACC_MII_10TH_SEC_IN_MILLIS;
-
-/* -----------------------------------
- * private function prototypes
- */
-PRIVATE void
-ixEthAccMdioCmdWrite(UINT32 mdioCommand);
-
-PRIVATE void
-ixEthAccMdioCmdRead(UINT32 *data);
-
-PRIVATE void
-ixEthAccMdioStatusRead(UINT32 *data);
-
-
-PRIVATE void
-ixEthAccMdioCmdWrite(UINT32 mdioCommand)
-{
-    REG_WRITE(miiBaseAddressVirt,
-	      IX_ETH_ACC_MAC_MDIO_CMD_1,
-	      mdioCommand & 0xff);
-
-    REG_WRITE(miiBaseAddressVirt,
-	      IX_ETH_ACC_MAC_MDIO_CMD_2,
-	      (mdioCommand >> 8) & 0xff);
-
-    REG_WRITE(miiBaseAddressVirt,
-	      IX_ETH_ACC_MAC_MDIO_CMD_3,
-	      (mdioCommand >> 16) & 0xff);
-
-    REG_WRITE(miiBaseAddressVirt,
-	      IX_ETH_ACC_MAC_MDIO_CMD_4,
-	      (mdioCommand >> 24) & 0xff);
-}
-
-PRIVATE void
-ixEthAccMdioCmdRead(UINT32 *data)
-{
-    UINT32 regval;
-
-    REG_READ(miiBaseAddressVirt,
-	     IX_ETH_ACC_MAC_MDIO_CMD_1,
-	     regval);
-
-    *data = regval & 0xff;
-
-    REG_READ(miiBaseAddressVirt,
-	     IX_ETH_ACC_MAC_MDIO_CMD_2,
-	     regval);
-
-    *data |= (regval & 0xff) << 8;
-
-    REG_READ(miiBaseAddressVirt,
-	     IX_ETH_ACC_MAC_MDIO_CMD_3,
-	     regval);
-
-    *data |= (regval & 0xff) << 16;
-
-    REG_READ(miiBaseAddressVirt,
-	     IX_ETH_ACC_MAC_MDIO_CMD_4,
-	     regval);
-
-    *data |= (regval & 0xff) << 24;
-
-}
-
-PRIVATE void
-ixEthAccMdioStatusRead(UINT32 *data)
-{
-    UINT32 regval;
-
-    REG_READ(miiBaseAddressVirt,
-	     IX_ETH_ACC_MAC_MDIO_STS_1,
-	     regval);
-
-    *data = regval & 0xff;
-
-    REG_READ(miiBaseAddressVirt,
-	     IX_ETH_ACC_MAC_MDIO_STS_2,
-	     regval);
-
-    *data |= (regval & 0xff) << 8;
-
-    REG_READ(miiBaseAddressVirt,
-	     IX_ETH_ACC_MAC_MDIO_STS_3,
-	     regval);
-
-    *data |= (regval & 0xff) << 16;
-
-    REG_READ(miiBaseAddressVirt,
-	     IX_ETH_ACC_MAC_MDIO_STS_4,
-	     regval);
-    
-    *data |= (regval & 0xff) << 24;
-    
-}
-
-
-/********************************************************************
- * ixEthAccMiiInit
- */
-IxEthAccStatus
-ixEthAccMiiInit()
-{
-    if(ixOsalMutexInit(&miiAccessLock)!= IX_SUCCESS)
-    {
-	return IX_ETH_ACC_FAIL;
-    }
-
-    miiBaseAddressVirt = (UINT32) IX_OSAL_MEM_MAP(IX_ETH_ACC_MAC_0_BASE, IX_OSAL_IXP400_ETHA_MAP_SIZE);
-    
-    if (miiBaseAddressVirt == 0)
-    {
-      ixOsalLog(IX_OSAL_LOG_LVL_FATAL, 
-		IX_OSAL_LOG_DEV_STDOUT, 
-		"EthAcc: Could not map MII I/O mapped memory\n", 
-		0, 0, 0, 0, 0, 0);
-      
-      return IX_ETH_ACC_FAIL;
-    }
-    
-    return IX_ETH_ACC_SUCCESS;
-}
-
-void
-ixEthAccMiiUnload(void)
-{
-    IX_OSAL_MEM_UNMAP(miiBaseAddressVirt);
-  
-    miiBaseAddressVirt = 0;
-}
-
-PUBLIC IxEthAccStatus
-ixEthAccMiiAccessTimeoutSet(UINT32 timeout, UINT32 retryCount)
-{
-    if (retryCount < 1) return IX_ETH_ACC_FAIL;
-
-    ixEthAccMiiRetryCount    = retryCount;
-    ixEthAccMiiAccessTimeout = timeout;
-
-    return IX_ETH_ACC_SUCCESS;
-}
-
-/*********************************************************************
- * ixEthAccMiiReadRtn - read a 16 bit value from a PHY
- */
-IxEthAccStatus      
-ixEthAccMiiReadRtn (UINT8 phyAddr, 
-		    UINT8 phyReg, 
-		    UINT16 *value)
-{
-    UINT32 mdioCommand;
-    UINT32 regval;
-    UINT32 miiTimeout;
-
-    if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED())
-    {
-	return (IX_ETH_ACC_FAIL);
-    }
-
-    if ((phyAddr >= IXP425_ETH_ACC_MII_MAX_ADDR) 
-	|| (phyReg >= IXP425_ETH_ACC_MII_MAX_REG))
-    {
-	return (IX_ETH_ACC_FAIL);
-    }
-
-    if (value == NULL)
-    {
-	return (IX_ETH_ACC_FAIL);
-    }
-
-    ixOsalMutexLock(&miiAccessLock, IX_OSAL_WAIT_FOREVER);
-    mdioCommand = phyReg <<  IX_ETH_ACC_MII_REG_SHL 
-	| phyAddr << IX_ETH_ACC_MII_ADDR_SHL;
-    mdioCommand |= IX_ETH_ACC_MII_GO;
-
-    ixEthAccMdioCmdWrite(mdioCommand);
-    
-    miiTimeout = ixEthAccMiiRetryCount;
-
-    while(miiTimeout)
-    {
-	
-	ixEthAccMdioCmdRead(&regval);
-     
-	if((regval & IX_ETH_ACC_MII_GO) == 0x0)
-	{	    
-	    break;
-	}
-	/* Sleep for a while */
-	ixOsalSleep(ixEthAccMiiAccessTimeout);
-	miiTimeout--;
-    }
-    
-
-    
-    if(miiTimeout == 0)
-    {	
-	ixOsalMutexUnlock(&miiAccessLock);
-	*value = 0xffff;
-	return IX_ETH_ACC_FAIL;
-    }
-    
-    
-    ixEthAccMdioStatusRead(&regval);
-    if(regval & IX_ETH_ACC_MII_READ_FAIL)
-    {
-	ixOsalMutexUnlock(&miiAccessLock);
-	*value = 0xffff;
-	return IX_ETH_ACC_FAIL;
-    }
-
-    *value = regval & 0xffff;
-    ixOsalMutexUnlock(&miiAccessLock);
-    return IX_ETH_ACC_SUCCESS;
-    
-}
-
-
-/*********************************************************************
- * ixEthAccMiiWriteRtn - write a 16 bit value to a PHY
- */
-IxEthAccStatus
-ixEthAccMiiWriteRtn (UINT8 phyAddr, 
-		     UINT8 phyReg, 
-		     UINT16 value)
-{
-    UINT32 mdioCommand;
-    UINT32 regval;
-    UINT16 readVal;
-    UINT32 miiTimeout;
-
-    if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED())
-    {
-	return (IX_ETH_ACC_FAIL);
-    }
-
-    if ((phyAddr >= IXP425_ETH_ACC_MII_MAX_ADDR) 
-	|| (phyReg >= IXP425_ETH_ACC_MII_MAX_REG))
-    {
-	return (IX_ETH_ACC_FAIL);
-    }
-   
-    /* ensure that a PHY is present at this address */
-    if(ixEthAccMiiReadRtn(phyAddr,
-                          IX_ETH_ACC_MII_CTRL_REG,
-                          &readVal) != IX_ETH_ACC_SUCCESS)
-    {
-        return (IX_ETH_ACC_FAIL);
-    }
-
-    ixOsalMutexLock(&miiAccessLock, IX_OSAL_WAIT_FOREVER);
-    mdioCommand = phyReg << IX_ETH_ACC_MII_REG_SHL
-	| phyAddr << IX_ETH_ACC_MII_ADDR_SHL ;
-    mdioCommand |= IX_ETH_ACC_MII_GO | IX_ETH_ACC_MII_WRITE | value;
-
-    ixEthAccMdioCmdWrite(mdioCommand);
-    
-    miiTimeout = ixEthAccMiiRetryCount;
-
-    while(miiTimeout)
-    {
-	
-	ixEthAccMdioCmdRead(&regval);
-
-	/*The "GO" bit is reset to 0 when the write completes*/
-	if((regval & IX_ETH_ACC_MII_GO) == 0x0)
-	{		    
-	    break;
-	}
-	/* Sleep for a while */
-	ixOsalSleep(ixEthAccMiiAccessTimeout);
-        miiTimeout--;
-    }
-    
-    ixOsalMutexUnlock(&miiAccessLock);
-    if(miiTimeout == 0)
-    {
-	return IX_ETH_ACC_FAIL;
-    }
-    return IX_ETH_ACC_SUCCESS;
-}
-
-
-/*****************************************************************
- *
- *  Phy query functions
- *
- */
-IxEthAccStatus
-ixEthAccMiiStatsShow (UINT32 phyAddr)
-{
-    UINT16 regval;
-    printf("Regisers on PHY at address 0x%x\n", phyAddr);
-    ixEthAccMiiReadRtn(phyAddr, IX_ETH_ACC_MII_CTRL_REG, &regval);
-    printf("    Control Register                  :      0x%4.4x\n", regval);
-    ixEthAccMiiReadRtn(phyAddr,  IX_ETH_ACC_MII_STAT_REG, &regval);
-    printf("    Status Register                   :      0x%4.4x\n", regval);
-    ixEthAccMiiReadRtn(phyAddr,  IX_ETH_ACC_MII_PHY_ID1_REG, &regval);
-    printf("    PHY ID1 Register                  :      0x%4.4x\n", regval);
-    ixEthAccMiiReadRtn(phyAddr,  IX_ETH_ACC_MII_PHY_ID2_REG, &regval);
-    printf("    PHY ID2 Register                  :      0x%4.4x\n", regval);
-    ixEthAccMiiReadRtn(phyAddr,  IX_ETH_ACC_MII_AN_ADS_REG, &regval);
-    printf("    Auto Neg ADS Register             :      0x%4.4x\n", regval);
-    ixEthAccMiiReadRtn(phyAddr,  IX_ETH_ACC_MII_AN_PRTN_REG, &regval);
-    printf("    Auto Neg Partner Ability Register :      0x%4.4x\n", regval);
-    ixEthAccMiiReadRtn(phyAddr,  IX_ETH_ACC_MII_AN_EXP_REG, &regval);
-    printf("    Auto Neg Expansion Register       :      0x%4.4x\n", regval);
-    ixEthAccMiiReadRtn(phyAddr,  IX_ETH_ACC_MII_AN_NEXT_REG, &regval);
-    printf("    Auto Neg Next Register            :      0x%4.4x\n", regval);
-
-    return IX_ETH_ACC_SUCCESS;
-}
-
-
-/*****************************************************************
- *
- *  Interface query functions
- *
- */
-IxEthAccStatus
-ixEthAccMdioShow (void)
-{
-    UINT32 regval;
-
-    if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED())
-    {
-	return (IX_ETH_ACC_FAIL);
-    }
-
-    ixOsalMutexLock(&miiAccessLock, IX_OSAL_WAIT_FOREVER);
-    ixEthAccMdioCmdRead(&regval);
-    ixOsalMutexUnlock(&miiAccessLock);
-    
-    printf("MDIO command register\n");
-    printf("    Go bit      : 0x%x\n", (regval & BIT(31)) >> 31);
-    printf("    MDIO Write  : 0x%x\n", (regval & BIT(26)) >> 26);
-    printf("    PHY address : 0x%x\n", (regval >> 21) & 0x1f);
-    printf("    Reg address : 0x%x\n", (regval >> 16) & 0x1f);
-	
-    ixOsalMutexLock(&miiAccessLock, IX_OSAL_WAIT_FOREVER);
-    ixEthAccMdioStatusRead(&regval);
-    ixOsalMutexUnlock(&miiAccessLock);
-
-    printf("MDIO status register\n");
-    printf("    Read OK     : 0x%x\n", (regval & BIT(31)) >> 31);
-    printf("    Read Data   : 0x%x\n", (regval >> 16) & 0xff);
-
-    return IX_ETH_ACC_SUCCESS;   
-}
-
diff --git a/drivers/net/npe/IxEthDBAPI.c b/drivers/net/npe/IxEthDBAPI.c
deleted file mode 100644
index 023cf50248..0000000000
--- a/drivers/net/npe/IxEthDBAPI.c
+++ /dev/null
@@ -1,424 +0,0 @@
-/**
- * @file IxEthDBAPI.c
- *
- * @brief Implementation of the public API
- * 
- * @par
- * IXP400 SW Release version 2.0
- * 
- * -- Copyright Notice --
- * 
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- * 
- * @par
- * SPDX-License-Identifier:	BSD-3-Clause
- * @par
- * -- End of Copyright Notice --
- */
-
-#include "IxEthDB_p.h"
-#include "IxFeatureCtrl.h"
-
-extern HashTable dbHashtable;
-extern IxEthDBPortMap overflowUpdatePortList;
-extern BOOL ixEthDBPortUpdateRequired[IX_ETH_DB_MAX_RECORD_TYPE_INDEX + 1];
-
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBFilteringStaticEntryProvision(IxEthDBPortId portID, IxEthDBMacAddr *macAddr)
-{
-    IX_ETH_DB_CHECK_PORT(portID);
-    
-    IX_ETH_DB_CHECK_SINGLE_NPE(portID);
-    
-    IX_ETH_DB_CHECK_REFERENCE(macAddr);
-    
-    IX_ETH_DB_CHECK_FEATURE(portID, IX_ETH_DB_LEARNING);
-
-    return ixEthDBTriggerAddPortUpdate(macAddr, portID, true);
-}
-    
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBFilteringDynamicEntryProvision(IxEthDBPortId portID, IxEthDBMacAddr *macAddr)
-{
-    IX_ETH_DB_CHECK_PORT(portID);
-    
-    IX_ETH_DB_CHECK_SINGLE_NPE(portID);
-        
-    IX_ETH_DB_CHECK_REFERENCE(macAddr);
-
-    IX_ETH_DB_CHECK_FEATURE(portID, IX_ETH_DB_LEARNING);
-
-    return ixEthDBTriggerAddPortUpdate(macAddr, portID, false);
-}
-
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBFilteringEntryDelete(IxEthDBMacAddr *macAddr)
-{
-    HashNode *searchResult;
-
-    IX_ETH_DB_CHECK_REFERENCE(macAddr);
-
-    searchResult = ixEthDBSearch(macAddr, IX_ETH_DB_ALL_FILTERING_RECORDS);
-
-    if (searchResult == NULL)
-    {
-        return IX_ETH_DB_NO_SUCH_ADDR; /* not found */
-    }
-    
-    ixEthDBReleaseHashNode(searchResult);
-    
-    /* build a remove event and place it on the event queue */
-    return ixEthDBTriggerRemovePortUpdate(macAddr, ((MacDescriptor *) searchResult->data)->portID);
-}
-       
-IX_ETH_DB_PUBLIC
-void ixEthDBDatabaseMaintenance()
-{
-    HashIterator iterator;
-    UINT32 portIndex;
-    BOOL agingRequired = false;
-
-    /* ports who will have deleted records and therefore will need updating */
-    IxEthDBPortMap triggerPorts;
-
-    if (IX_FEATURE_CTRL_SWCONFIG_ENABLED !=
-        ixFeatureCtrlSwConfigurationCheck (IX_FEATURECTRL_ETH_LEARNING))
-    {
-        return;
-    }
-
-    SET_EMPTY_DEPENDENCY_MAP(triggerPorts);
-
-    /* check if there's at least a port that needs aging */
-    for (portIndex = 0 ; portIndex < IX_ETH_DB_NUMBER_OF_PORTS ; portIndex++)
-    {
-        if (ixEthDBPortInfo[portIndex].agingEnabled && ixEthDBPortInfo[portIndex].enabled)
-        {
-            agingRequired = true;
-        }
-    }
-
-    if (agingRequired)
-    {
-        /* ask each NPE port to write back the database for aging inspection */
-        for (portIndex = 0 ; portIndex < IX_ETH_DB_NUMBER_OF_PORTS ; portIndex++)
-        {
-            if (ixEthDBPortDefinitions[portIndex].type == IX_ETH_NPE
-                && ixEthDBPortInfo[portIndex].agingEnabled
-                && ixEthDBPortInfo[portIndex].enabled)
-            {
-                IxNpeMhMessage message;
-                IX_STATUS result;
-                
-                /* send EDB_GetMACAddressDatabase message */
-                FILL_GETMACADDRESSDATABASE(message, 
-                    0 /* unused */, 
-                    IX_OSAL_MMU_VIRT_TO_PHYS(ixEthDBPortInfo[portIndex].updateMethod.npeUpdateZone));
-
-                IX_ETHDB_SEND_NPE_MSG(IX_ETH_DB_PORT_ID_TO_NPE(portIndex), message, result);
-
-                if (result == IX_SUCCESS)
-                {
-                    /* analyze NPE copy */
-                    ixEthDBNPESyncScan(portIndex, ixEthDBPortInfo[portIndex].updateMethod.npeUpdateZone, FULL_ELT_BYTE_SIZE);
-
-                    IX_ETH_DB_SUPPORT_TRACE("DB: (API) Finished scanning NPE tree on port %d\n", portIndex);
-                }
-                else
-                {
-                    ixEthDBPortInfo[portIndex].agingEnabled                = false;
-                    ixEthDBPortInfo[portIndex].updateMethod.updateEnabled  = false;
-                    ixEthDBPortInfo[portIndex].updateMethod.userControlled = true;
-
-                    ixOsalLog(IX_OSAL_LOG_LVL_FATAL,
-                        IX_OSAL_LOG_DEV_STDOUT, 
-                        "EthDB: (Maintenance) warning, disabling aging and updates for port %d (assumed dead)\n",
-                        portIndex, 0, 0, 0, 0, 0);
-
-                    ixEthDBDatabaseClear(portIndex, IX_ETH_DB_ALL_RECORD_TYPES);
-                }
-            }
-        }
-
-        /* browse database and age entries */
-        BUSY_RETRY(ixEthDBInitHashIterator(&dbHashtable, &iterator));
-
-        while (IS_ITERATOR_VALID(&iterator))
-        {
-            MacDescriptor *descriptor = (MacDescriptor *) iterator.node->data;
-            UINT32 *age               = NULL;
-            BOOL staticEntry          = true;
-
-            if (descriptor->type == IX_ETH_DB_FILTERING_RECORD)
-            {
-                age         = &descriptor->recordData.filteringData.age;
-                staticEntry = descriptor->recordData.filteringData.staticEntry;
-            }
-            else if (descriptor->type == IX_ETH_DB_FILTERING_VLAN_RECORD)
-            {
-                age         = &descriptor->recordData.filteringVlanData.age;
-                staticEntry = descriptor->recordData.filteringVlanData.staticEntry;
-            }
-            else
-            {
-                staticEntry = true;
-            }
-
-            if (ixEthDBPortInfo[descriptor->portID].agingEnabled && (staticEntry == false))
-            {
-                /* manually increment the age if the port has no such capability */
-                if ((ixEthDBPortDefinitions[descriptor->portID].capabilities & IX_ETH_ENTRY_AGING) == 0)
-                {
-                    *age += (IX_ETH_DB_MAINTENANCE_TIME / 60);
-                }
-
-                /* age entry if it exceeded the maximum time to live */
-                if (*age >= (IX_ETH_DB_LEARNING_ENTRY_AGE_TIME / 60))
-                {
-                    /* add port to the set of update trigger ports */
-                    JOIN_PORT_TO_MAP(triggerPorts, descriptor->portID);
-
-                    /* delete entry */
-                    BUSY_RETRY(ixEthDBRemoveEntryAtHashIterator(&dbHashtable, &iterator));
-                }
-                else
-                {
-                    /* move to the next record */
-                    BUSY_RETRY(ixEthDBIncrementHashIterator(&dbHashtable, &iterator));
-                }
-            }
-            else
-            {
-                /* move to the next record */
-                BUSY_RETRY(ixEthDBIncrementHashIterator(&dbHashtable, &iterator));
-            }
-        }
-
-        /* update ports which lost records */
-        ixEthDBUpdatePortLearningTrees(triggerPorts);
-    }
-}
-
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBDatabaseClear(IxEthDBPortId portID, IxEthDBRecordType recordType)
-{
-    IxEthDBPortMap triggerPorts;
-    HashIterator iterator;
-
-    if (portID >= IX_ETH_DB_NUMBER_OF_PORTS && portID != IX_ETH_DB_ALL_PORTS)
-    {
-        return IX_ETH_DB_INVALID_PORT;
-    }
-
-    /* check if the user passes some extra bits */
-    if ((recordType | IX_ETH_DB_ALL_RECORD_TYPES) != IX_ETH_DB_ALL_RECORD_TYPES)
-    {
-        return IX_ETH_DB_INVALID_ARG;
-    }
-
-    SET_EMPTY_DEPENDENCY_MAP(triggerPorts);
-    
-    /* browse database and age entries */
-    BUSY_RETRY(ixEthDBInitHashIterator(&dbHashtable, &iterator));
-
-    while (IS_ITERATOR_VALID(&iterator))
-    {
-        MacDescriptor *descriptor = (MacDescriptor *) iterator.node->data;
-
-        if (((descriptor->portID == portID) || (portID == IX_ETH_DB_ALL_PORTS))
-            && ((descriptor->type & recordType) != 0))
-        {
-            /* add to trigger if automatic updates are required */
-            if (ixEthDBPortUpdateRequired[descriptor->type])
-            {
-                /* add port to the set of update trigger ports */
-                JOIN_PORT_TO_MAP(triggerPorts, descriptor->portID);
-            }
-
-            /* delete entry */
-            BUSY_RETRY(ixEthDBRemoveEntryAtHashIterator(&dbHashtable, &iterator));
-        }
-        else
-        {
-            /* move to the next record */
-            BUSY_RETRY(ixEthDBIncrementHashIterator(&dbHashtable, &iterator));
-        }
-    }
-
-    /* update ports which lost records */
-    ixEthDBUpdatePortLearningTrees(triggerPorts);
-    
-    return IX_ETH_DB_SUCCESS;
-}
-
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBFilteringPortSearch(IxEthDBPortId portID, IxEthDBMacAddr *macAddr)
-{
-    HashNode *searchResult;
-    IxEthDBStatus result = IX_ETH_DB_NO_SUCH_ADDR;
-
-    IX_ETH_DB_CHECK_PORT(portID);
-    
-    IX_ETH_DB_CHECK_SINGLE_NPE(portID);
-    
-    IX_ETH_DB_CHECK_REFERENCE(macAddr);
-
-    IX_ETH_DB_CHECK_FEATURE(portID, IX_ETH_DB_LEARNING);
-
-    searchResult = ixEthDBSearch(macAddr, IX_ETH_DB_ALL_FILTERING_RECORDS);
-
-    if (searchResult == NULL)
-    {
-        return IX_ETH_DB_NO_SUCH_ADDR; /* not found */
-    }
-
-    if (((MacDescriptor *) (searchResult->data))->portID == portID)
-    {
-        result = IX_ETH_DB_SUCCESS; /* address and port match */
-    }
-
-    ixEthDBReleaseHashNode(searchResult);
-
-    return result;
-}
-
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBFilteringDatabaseSearch(IxEthDBPortId *portID, IxEthDBMacAddr *macAddr)
-{
-    HashNode *searchResult;
-
-    IX_ETH_DB_CHECK_REFERENCE(portID);
-    
-    IX_ETH_DB_CHECK_REFERENCE(macAddr);
-
-    searchResult = ixEthDBSearch(macAddr, IX_ETH_DB_ALL_FILTERING_RECORDS);
-
-    if (searchResult == NULL)
-    {
-        return IX_ETH_DB_NO_SUCH_ADDR; /* not found */
-    }
-
-    /* return the port ID */
-    *portID = ((MacDescriptor *) searchResult->data)->portID;
-
-    ixEthDBReleaseHashNode(searchResult);
-
-    return IX_ETH_DB_SUCCESS;
-}
-
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBPortAgingDisable(IxEthDBPortId portID)
-{
-    IX_ETH_DB_CHECK_PORT(portID);
-
-    IX_ETH_DB_CHECK_SINGLE_NPE(portID);
-
-    IX_ETH_DB_CHECK_FEATURE(portID, IX_ETH_DB_LEARNING);
-
-    ixEthDBPortInfo[portID].agingEnabled = false;
-
-    return IX_ETH_DB_SUCCESS;
-}
-
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBPortAgingEnable(IxEthDBPortId portID)
-{
-    IX_ETH_DB_CHECK_PORT(portID);
-
-    IX_ETH_DB_CHECK_SINGLE_NPE(portID);
-
-    IX_ETH_DB_CHECK_FEATURE(portID, IX_ETH_DB_LEARNING);
-
-    ixEthDBPortInfo[portID].agingEnabled = true;
-
-    return IX_ETH_DB_SUCCESS;
-}
-
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBFilteringPortUpdatingSearch(IxEthDBPortId *portID, IxEthDBMacAddr *macAddr)
-{
-    HashNode *searchResult;
-    MacDescriptor *descriptor;
-
-    IX_ETH_DB_CHECK_REFERENCE(portID);
-    
-    IX_ETH_DB_CHECK_REFERENCE(macAddr);
-
-    searchResult = ixEthDBSearch(macAddr, IX_ETH_DB_ALL_FILTERING_RECORDS);
-
-    if (searchResult == NULL)
-    {
-        return IX_ETH_DB_NO_SUCH_ADDR; /* not found */
-    }
-    
-    descriptor = (MacDescriptor *) searchResult->data;
-
-    /* return the port ID */
-    *portID = descriptor->portID;
-
-    /* reset entry age */
-    if (descriptor->type == IX_ETH_DB_FILTERING_RECORD)
-    {
-        descriptor->recordData.filteringData.age = 0;
-    }
-    else
-    {
-        descriptor->recordData.filteringVlanData.age = 0;
-    }
-
-    ixEthDBReleaseHashNode(searchResult);
-
-    return IX_ETH_DB_SUCCESS;
-}
-
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBPortDependencyMapSet(IxEthDBPortId portID, IxEthDBPortMap dependencyPortMap)
-{
-    IX_ETH_DB_CHECK_PORT(portID);
-    
-    IX_ETH_DB_CHECK_SINGLE_NPE(portID);
-    
-    IX_ETH_DB_CHECK_REFERENCE(dependencyPortMap);
-    
-    IX_ETH_DB_CHECK_FEATURE(portID, IX_ETH_DB_FILTERING);
-
-    /* force bit at offset 255 to 0 (reserved) */
-    dependencyPortMap[31] &= 0xFE;
-
-    COPY_DEPENDENCY_MAP(ixEthDBPortInfo[portID].dependencyPortMap, dependencyPortMap);
-
-    return IX_ETH_DB_SUCCESS;
-}
-
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBPortDependencyMapGet(IxEthDBPortId portID, IxEthDBPortMap dependencyPortMap)
-{
-    IX_ETH_DB_CHECK_PORT(portID);
-    
-    IX_ETH_DB_CHECK_SINGLE_NPE(portID);
-    
-    IX_ETH_DB_CHECK_REFERENCE(dependencyPortMap);
-    
-    IX_ETH_DB_CHECK_FEATURE(portID, IX_ETH_DB_FILTERING);
-
-    COPY_DEPENDENCY_MAP(dependencyPortMap, ixEthDBPortInfo[portID].dependencyPortMap);
-
-    return IX_ETH_DB_SUCCESS;
-}
-
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBPortUpdateEnableSet(IxEthDBPortId portID, BOOL enableUpdate)
-{
-    IX_ETH_DB_CHECK_PORT(portID);
-
-    IX_ETH_DB_CHECK_SINGLE_NPE(portID);    
-
-    IX_ETH_DB_CHECK_FEATURE(portID, IX_ETH_DB_FILTERING);
-
-    ixEthDBPortInfo[portID].updateMethod.updateEnabled  = enableUpdate;
-    ixEthDBPortInfo[portID].updateMethod.userControlled = true;
-
-    return IX_ETH_DB_SUCCESS;
-}
diff --git a/drivers/net/npe/IxEthDBAPISupport.c b/drivers/net/npe/IxEthDBAPISupport.c
deleted file mode 100644
index c265d942e0..0000000000
--- a/drivers/net/npe/IxEthDBAPISupport.c
+++ /dev/null
@@ -1,651 +0,0 @@
-/**
- * @file IxEthDBAPISupport.c
- *
- * @brief Public API support functions
- *
- * @par
- * IXP400 SW Release version 2.0
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * SPDX-License-Identifier:	BSD-3-Clause
- * @par
- * -- End of Copyright Notice --
- */
-
-#include <IxEthDB.h>
-#include <IxNpeMh.h>
-#include <IxFeatureCtrl.h>
-
-#include "IxEthDB_p.h"
-#include "IxEthDBMessages_p.h"
-#include "IxEthDB_p.h"
-#include "IxEthDBLog_p.h"
-
-#ifdef IX_UNIT_TEST
-
-int dbAccessCounter = 0;
-int overflowEvent   = 0;
-
-#endif
-
-/*
- * External declaration
- */
-extern HashTable dbHashtable;
-
-/*
- * Internal declaration
- */
-IX_ETH_DB_PUBLIC
-PortInfo ixEthDBPortInfo[IX_ETH_DB_NUMBER_OF_PORTS];
-
-IX_ETH_DB_PRIVATE
-struct
-{
-    BOOL saved;
-    IxEthDBPriorityTable priorityTable;
-    IxEthDBVlanSet vlanMembership;
-    IxEthDBVlanSet transmitTaggingInfo;
-    IxEthDBFrameFilter frameFilter;
-    IxEthDBTaggingAction taggingAction;
-    IxEthDBFirewallMode firewallMode;
-    BOOL stpBlocked;
-    BOOL srcAddressFilterEnabled;
-    UINT32 maxRxFrameSize;
-    UINT32 maxTxFrameSize;
-} ixEthDBPortState[IX_ETH_DB_NUMBER_OF_PORTS];
-
-#define IX_ETH_DB_DEFAULT_FRAME_SIZE (1518)
-
-/**
- * @brief initializes a port
- *
- * @param portID ID of the port to be initialized
- *
- * Note that redundant initializations are silently
- * dealt with and do not constitute an error
- *
- * This function is fully documented in the main
- * header file, IxEthDB.h
- */
-IX_ETH_DB_PUBLIC
-void ixEthDBPortInit(IxEthDBPortId portID)
-{
-    PortInfo *portInfo;
-
-    if (portID >= IX_ETH_DB_NUMBER_OF_PORTS)
-    {
-        return;
-    }
-
-    portInfo = &ixEthDBPortInfo[portID];
-
-    if (ixEthDBSingleEthNpeCheck(portID) != IX_ETH_DB_SUCCESS)
-    {
-        WARNING_LOG("EthDB: Unavailable Eth %d: Cannot initialize EthDB Port.\n", (UINT32) portID);
-
-        return;
-    }
-
-    if (portInfo->initialized)
-    {
-        /* redundant */
-        return;
-    }
-
-    /* initialize core fields */
-    portInfo->portID = portID;
-    SET_DEPENDENCY_MAP(portInfo->dependencyPortMap, portID);
-
-    /* default values */
-    portInfo->agingEnabled       = false;
-    portInfo->enabled            = false;
-    portInfo->macAddressUploaded = false;
-    portInfo->maxRxFrameSize     = IX_ETHDB_DEFAULT_FRAME_SIZE;
-    portInfo->maxTxFrameSize     = IX_ETHDB_DEFAULT_FRAME_SIZE;
-
-    /* default update control values */
-    portInfo->updateMethod.searchTree              = NULL;
-    portInfo->updateMethod.searchTreePendingWrite  = false;
-    portInfo->updateMethod.treeInitialized         = false;
-    portInfo->updateMethod.updateEnabled           = false;
-    portInfo->updateMethod.userControlled          = false;
-
-    /* default WiFi parameters */
-    memset(portInfo->bbsid, 0, sizeof (portInfo->bbsid));
-    portInfo->frameControlDurationID = 0;
-
-    /* Ethernet NPE-specific initializations */
-    if (ixEthDBPortDefinitions[portID].type == IX_ETH_NPE)
-    {
-        /* update handler */
-        portInfo->updateMethod.updateHandler = ixEthDBNPEUpdateHandler;
-    }
-
-    /* initialize state save */
-    ixEthDBPortState[portID].saved = false;
-
-    portInfo->initialized = true;
-}
-
-/**
- * @brief enables a port
- *
- * @param portID ID of the port to enable
- *
- * This function is fully documented in the main
- * header file, IxEthDB.h
- *
- * @return IX_ETH_DB_SUCCESS if enabling was
- * accomplished, or a meaningful error message otherwise
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBPortEnable(IxEthDBPortId portID)
-{
-    IxEthDBPortMap triggerPorts;
-    PortInfo *portInfo;
-
-    IX_ETH_DB_CHECK_PORT_EXISTS(portID);
-
-    IX_ETH_DB_CHECK_SINGLE_NPE(portID);
-
-    portInfo = &ixEthDBPortInfo[portID];
-
-    if (portInfo->enabled)
-    {
-        /* redundant */
-        return IX_ETH_DB_SUCCESS;
-    }
-
-    SET_DEPENDENCY_MAP(triggerPorts, portID);
-
-    /* mark as enabled */
-    portInfo->enabled = true;
-
-    /* Operation stops here when Ethernet Learning is not enabled */
-    if(IX_FEATURE_CTRL_SWCONFIG_DISABLED ==
-       ixFeatureCtrlSwConfigurationCheck(IX_FEATURECTRL_ETH_LEARNING))
-    {
-        return IX_ETH_DB_SUCCESS;
-    }
-
-    if (ixEthDBPortDefinitions[portID].type == IX_ETH_NPE && !portInfo->macAddressUploaded)
-    {
-        IX_ETH_DB_SUPPORT_TRACE("DB: (Support) MAC address not set on port %d, enable failed\n", portID);
-
-        /* must use UnicastAddressSet() before enabling an NPE port */
-        return IX_ETH_DB_MAC_UNINITIALIZED;
-    }
-
-    if (ixEthDBPortDefinitions[portID].type == IX_ETH_NPE)
-    {
-        IX_ETH_DB_SUPPORT_TRACE("DB: (Support) Attempting to enable the NPE callback for port %d...\n", portID);
-
-        if (!portInfo->updateMethod.userControlled
-                && ((portInfo->featureCapability & IX_ETH_DB_FILTERING) != 0))
-        {
-            portInfo->updateMethod.updateEnabled = true;
-        }
-
-        /* if this is first time initialization then we already have
-           write access to the tree and can AccessRelease directly */
-        if (!portInfo->updateMethod.treeInitialized)
-        {
-            IX_ETH_DB_SUPPORT_TRACE("DB: (Support) Initializing tree for port %d\n", portID);
-
-            /* create an initial tree and release access into it */
-            ixEthDBUpdatePortLearningTrees(triggerPorts);
-
-            /* mark tree as being initialized */
-            portInfo->updateMethod.treeInitialized = true;
-        }
-    }
-
-    if (ixEthDBPortState[portID].saved)
-    {
-        /* previous configuration data stored, restore state */
-        if ((portInfo->featureCapability & IX_ETH_DB_FIREWALL) != 0)
-        {
-            ixEthDBFirewallModeSet(portID, ixEthDBPortState[portID].firewallMode);
-            ixEthDBFirewallInvalidAddressFilterEnable(portID, ixEthDBPortState[portID].srcAddressFilterEnabled);
-        }
-
-#if 0 /* test-only */
-        if ((portInfo->featureCapability & IX_ETH_DB_VLAN_QOS) != 0)
-        {
-            ixEthDBAcceptableFrameTypeSet(portID, ixEthDBPortState[portID].frameFilter);
-            ixEthDBIngressVlanTaggingEnabledSet(portID, ixEthDBPortState[portID].taggingAction);
-
-            ixEthDBEgressVlanTaggingEnabledSet(portID, ixEthDBPortState[portID].transmitTaggingInfo);
-            ixEthDBPortVlanMembershipSet(portID, ixEthDBPortState[portID].vlanMembership);
-
-            ixEthDBPriorityMappingTableSet(portID, ixEthDBPortState[portID].priorityTable);
-        }
-#endif
-
-        if ((portInfo->featureCapability & IX_ETH_DB_SPANNING_TREE_PROTOCOL) != 0)
-        {
-            ixEthDBSpanningTreeBlockingStateSet(portID, ixEthDBPortState[portID].stpBlocked);
-        }
-
-        ixEthDBFilteringPortMaximumRxFrameSizeSet(portID, ixEthDBPortState[portID].maxRxFrameSize);
-        ixEthDBFilteringPortMaximumTxFrameSizeSet(portID, ixEthDBPortState[portID].maxTxFrameSize);
-
-        /* discard previous save */
-        ixEthDBPortState[portID].saved = false;
-    }
-
-    IX_ETH_DB_SUPPORT_TRACE("DB: (Support) Enabling succeeded for port %d\n", portID);
-
-    return IX_ETH_DB_SUCCESS;
-}
-
-/**
- * @brief disables a port
- *
- * @param portID ID of the port to disable
- *
- * This function is fully documented in the
- * main header file, IxEthDB.h
- *
- * @return IX_ETH_DB_SUCCESS if disabling was
- * successful or an appropriate error message
- * otherwise
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBPortDisable(IxEthDBPortId portID)
-{
-    HashIterator iterator;
-    IxEthDBPortMap triggerPorts; /* ports who will have deleted records and therefore will need updating */
-    BOOL result;
-    PortInfo *portInfo;
-    IxEthDBFeature learningEnabled;
-#if 0 /* test-only */
-    IxEthDBPriorityTable classZeroTable;
-#endif
-
-    IX_ETH_DB_CHECK_PORT_EXISTS(portID);
-
-    IX_ETH_DB_CHECK_SINGLE_NPE(portID);
-
-    portInfo = &ixEthDBPortInfo[portID];
-
-    if (!portInfo->enabled)
-    {
-        /* redundant */
-        return IX_ETH_DB_SUCCESS;
-    }
-
-    if (ixEthDBPortDefinitions[portID].type == IX_ETH_NPE)
-    {
-        /* save filtering state */
-        ixEthDBPortState[portID].firewallMode            = portInfo->firewallMode;
-        ixEthDBPortState[portID].frameFilter             = portInfo->frameFilter;
-        ixEthDBPortState[portID].taggingAction           = portInfo->taggingAction;
-        ixEthDBPortState[portID].stpBlocked              = portInfo->stpBlocked;
-        ixEthDBPortState[portID].srcAddressFilterEnabled = portInfo->srcAddressFilterEnabled;
-        ixEthDBPortState[portID].maxRxFrameSize          = portInfo->maxRxFrameSize;
-        ixEthDBPortState[portID].maxTxFrameSize          = portInfo->maxTxFrameSize;
-
-        memcpy(ixEthDBPortState[portID].vlanMembership, portInfo->vlanMembership, sizeof (IxEthDBVlanSet));
-        memcpy(ixEthDBPortState[portID].transmitTaggingInfo, portInfo->transmitTaggingInfo, sizeof (IxEthDBVlanSet));
-        memcpy(ixEthDBPortState[portID].priorityTable, portInfo->priorityTable, sizeof (IxEthDBPriorityTable));
-
-        ixEthDBPortState[portID].saved = true;
-
-        /* now turn off all EthDB filtering features on the port */
-
-#if 0 /* test-only */
-        /* VLAN & QoS */
-        if ((portInfo->featureCapability & IX_ETH_DB_VLAN_QOS) != 0)
-        {
-            ixEthDBPortVlanMembershipRangeAdd((IxEthDBPortId) portID, 0, IX_ETH_DB_802_1Q_MAX_VLAN_ID);
-            ixEthDBEgressVlanRangeTaggingEnabledSet((IxEthDBPortId) portID, 0, IX_ETH_DB_802_1Q_MAX_VLAN_ID, false);
-            ixEthDBAcceptableFrameTypeSet((IxEthDBPortId) portID, IX_ETH_DB_ACCEPT_ALL_FRAMES);
-            ixEthDBIngressVlanTaggingEnabledSet((IxEthDBPortId) portID, IX_ETH_DB_PASS_THROUGH);
-
-            memset(classZeroTable, 0, sizeof (classZeroTable));
-            ixEthDBPriorityMappingTableSet((IxEthDBPortId) portID, classZeroTable);
-        }
-#endif
-
-        /* STP */
-        if ((portInfo->featureCapability & IX_ETH_DB_SPANNING_TREE_PROTOCOL) != 0)
-        {
-            ixEthDBSpanningTreeBlockingStateSet((IxEthDBPortId) portID, false);
-        }
-
-        /* Firewall */
-        if ((portInfo->featureCapability & IX_ETH_DB_FIREWALL) != 0)
-        {
-            ixEthDBFirewallModeSet((IxEthDBPortId) portID, IX_ETH_DB_FIREWALL_BLACK_LIST);
-            ixEthDBFirewallTableDownload((IxEthDBPortId) portID);
-            ixEthDBFirewallInvalidAddressFilterEnable((IxEthDBPortId) portID, false);
-        }
-
-        /* Frame size filter */
-        ixEthDBFilteringPortMaximumFrameSizeSet((IxEthDBPortId) portID, IX_ETH_DB_DEFAULT_FRAME_SIZE);
-
-        /* WiFi */
-        if ((portInfo->featureCapability & IX_ETH_DB_WIFI_HEADER_CONVERSION) != 0)
-        {
-            ixEthDBWiFiConversionTableDownload((IxEthDBPortId) portID);
-        }
-
-        /* save and disable the learning feature bit */
-        learningEnabled          = portInfo->featureStatus & IX_ETH_DB_LEARNING;
-        portInfo->featureStatus &= ~IX_ETH_DB_LEARNING;
-    }
-    else
-    {
-        /* save the learning feature bit */
-        learningEnabled          = portInfo->featureStatus & IX_ETH_DB_LEARNING;
-    }
-
-    SET_EMPTY_DEPENDENCY_MAP(triggerPorts);
-
-    ixEthDBUpdateLock();
-
-    /* wipe out current entries for this port */
-    BUSY_RETRY(ixEthDBInitHashIterator(&dbHashtable, &iterator));
-
-    while (IS_ITERATOR_VALID(&iterator))
-    {
-        MacDescriptor *descriptor =  (MacDescriptor *) iterator.node->data;
-
-        /* check if the port match. If so, remove the entry  */
-        if (descriptor->portID == portID
-                && (descriptor->type == IX_ETH_DB_FILTERING_RECORD || descriptor->type == IX_ETH_DB_FILTERING_VLAN_RECORD)
-                && !descriptor->recordData.filteringData.staticEntry)
-        {
-            /* delete entry */
-            BUSY_RETRY(ixEthDBRemoveEntryAtHashIterator(&dbHashtable, &iterator));
-
-            /* add port to the set of update trigger ports */
-            JOIN_PORT_TO_MAP(triggerPorts, portID);
-        }
-        else
-        {
-            /* move to the next record */
-            BUSY_RETRY(ixEthDBIncrementHashIterator(&dbHashtable, &iterator));
-        }
-    }
-
-    if (ixEthDBPortDefinitions[portID].type == IX_ETH_NPE)
-    {
-        if (portInfo->updateMethod.searchTree != NULL)
-        {
-            ixEthDBFreeMacTreeNode(portInfo->updateMethod.searchTree);
-            portInfo->updateMethod.searchTree = NULL;
-        }
-
-        ixEthDBNPEUpdateHandler(portID, IX_ETH_DB_FILTERING_RECORD);
-    }
-
-    /* mark as disabled */
-    portInfo->enabled = false;
-
-    /* disable updates unless the user has specifically altered the default behavior */
-    if (ixEthDBPortDefinitions[portID].type == IX_ETH_NPE)
-    {
-        if (!portInfo->updateMethod.userControlled)
-        {
-            portInfo->updateMethod.updateEnabled = false;
-        }
-
-        /* make sure we re-initialize the NPE learning tree when the port is re-enabled */
-        portInfo->updateMethod.treeInitialized = false;
-    }
-
-    ixEthDBUpdateUnlock();
-
-    /* restore learning feature bit */
-    portInfo->featureStatus |= learningEnabled;
-
-    /* if we've removed any records or lost any events make sure to force an update */
-    IS_EMPTY_DEPENDENCY_MAP(result, triggerPorts);
-
-    if (!result)
-    {
-        ixEthDBUpdatePortLearningTrees(triggerPorts);
-    }
-
-    return IX_ETH_DB_SUCCESS;
-}
-
-/**
- * @brief sends the updated maximum Tx/Rx frame lengths to the NPE
- *
- * @param portID ID of the port to update
- *
- * @return IX_ETH_DB_SUCCESS if the update completed
- * successfully or an appropriate error message otherwise
- *
- * @internal
- */
-IX_ETH_DB_PRIVATE
-IxEthDBStatus ixEthDBPortFrameLengthsUpdate(IxEthDBPortId portID)
-{
-    IxNpeMhMessage message;
-    PortInfo *portInfo = &ixEthDBPortInfo[portID];
-    IX_STATUS result;
-
-    FILL_SETMAXFRAMELENGTHS_MSG(message, portID, portInfo->maxRxFrameSize, portInfo->maxTxFrameSize);
-
-    IX_ETHDB_SEND_NPE_MSG(IX_ETH_DB_PORT_ID_TO_NPE(portID), message, result);
-
-    return result;
-}
-
-/**
- * @brief sets the port maximum Rx frame size
- *
- * @param portID ID of the port to set the frame size on
- * @param maximumRxFrameSize maximum Rx frame size
- *
- * This function updates the internal data structures and
- * calls ixEthDBPortFrameLengthsUpdate() for NPE update.
- *
- * This function is fully documented in the main header
- * file, IxEthDB.h.
- *
- * @return IX_ETH_DB_SUCCESS if the operation was
- * successfull or an appropriate error message otherwise
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBFilteringPortMaximumRxFrameSizeSet(IxEthDBPortId portID, UINT32 maximumRxFrameSize)
-{
-    IX_ETH_DB_CHECK_PORT_EXISTS(portID);
-
-    IX_ETH_DB_CHECK_SINGLE_NPE(portID);
-
-	if (!ixEthDBPortInfo[portID].initialized)
-	{
-		return IX_ETH_DB_PORT_UNINITIALIZED;
-	}
-
-    if (ixEthDBPortDefinitions[portID].type == IX_ETH_NPE)
-    {
-	if ((maximumRxFrameSize < IX_ETHDB_MIN_NPE_FRAME_SIZE) ||
-	    (maximumRxFrameSize > IX_ETHDB_MAX_NPE_FRAME_SIZE))
-	{
-	    return IX_ETH_DB_INVALID_ARG;
-	}
-    }
-    else
-    {
-        return IX_ETH_DB_NO_PERMISSION;
-    }
-
-    /* update internal structure */
-    ixEthDBPortInfo[portID].maxRxFrameSize = maximumRxFrameSize;
-
-    /* update the maximum frame size in the NPE */
-    return ixEthDBPortFrameLengthsUpdate(portID);
-}
-
-/**
- * @brief sets the port maximum Tx frame size
- *
- * @param portID ID of the port to set the frame size on
- * @param maximumTxFrameSize maximum Tx frame size
- *
- * This function updates the internal data structures and
- * calls ixEthDBPortFrameLengthsUpdate() for NPE update.
- *
- * This function is fully documented in the main header
- * file, IxEthDB.h.
- *
- * @return IX_ETH_DB_SUCCESS if the operation was
- * successfull or an appropriate error message otherwise
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBFilteringPortMaximumTxFrameSizeSet(IxEthDBPortId portID, UINT32 maximumTxFrameSize)
-{
-    IX_ETH_DB_CHECK_PORT_EXISTS(portID);
-
-    IX_ETH_DB_CHECK_SINGLE_NPE(portID);
-
-	if (!ixEthDBPortInfo[portID].initialized)
-	{
-		return IX_ETH_DB_PORT_UNINITIALIZED;
-	}
-
-    if (ixEthDBPortDefinitions[portID].type == IX_ETH_NPE)
-    {
-	if ((maximumTxFrameSize < IX_ETHDB_MIN_NPE_FRAME_SIZE) ||
-	    (maximumTxFrameSize > IX_ETHDB_MAX_NPE_FRAME_SIZE))
-	{
-	    return IX_ETH_DB_INVALID_ARG;
-	}
-    }
-    else
-    {
-        return IX_ETH_DB_NO_PERMISSION;
-    }
-
-    /* update internal structure */
-    ixEthDBPortInfo[portID].maxTxFrameSize = maximumTxFrameSize;
-
-    /* update the maximum frame size in the NPE */
-    return ixEthDBPortFrameLengthsUpdate(portID);
-}
-
-/**
- * @brief sets the port maximum Tx and Rx frame sizes
- *
- * @param portID ID of the port to set the frame size on
- * @param maximumFrameSize maximum Tx and Rx frame sizes
- *
- * This function updates the internal data structures and
- * calls ixEthDBPortFrameLengthsUpdate() for NPE update.
- *
- * Note that both the maximum Tx and Rx frame size are set
- * to the same value. This function is kept for compatibility
- * reasons.
- *
- * This function is fully documented in the main header
- * file, IxEthDB.h.
- *
- * @return IX_ETH_DB_SUCCESS if the operation was
- * successfull or an appropriate error message otherwise
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBFilteringPortMaximumFrameSizeSet(IxEthDBPortId portID, UINT32 maximumFrameSize)
-{
-    IX_ETH_DB_CHECK_PORT_EXISTS(portID);
-
-    IX_ETH_DB_CHECK_SINGLE_NPE(portID);
-
-    if (!ixEthDBPortInfo[portID].initialized)
-    {
-        return IX_ETH_DB_PORT_UNINITIALIZED;
-    }
-
-    if (ixEthDBPortDefinitions[portID].type == IX_ETH_NPE)
-    {
-	if ((maximumFrameSize < IX_ETHDB_MIN_NPE_FRAME_SIZE) ||
-	    (maximumFrameSize > IX_ETHDB_MAX_NPE_FRAME_SIZE))
-	{
-	    return IX_ETH_DB_INVALID_ARG;
-	}
-    }
-    else
-    {
-        return IX_ETH_DB_NO_PERMISSION;
-    }
-
-    /* update internal structure */
-    ixEthDBPortInfo[portID].maxRxFrameSize = maximumFrameSize;
-    ixEthDBPortInfo[portID].maxTxFrameSize = maximumFrameSize;
-
-    /* update the maximum frame size in the NPE */
-    return ixEthDBPortFrameLengthsUpdate(portID);
-}
-
-/**
- * @brief sets the MAC address of an NPE port
- *
- * @param portID port ID to set the MAC address on
- * @param macAddr pointer to the 6-byte MAC address
- *
- * This function is called by the EthAcc
- * ixEthAccUnicastMacAddressSet() and should not be
- * manually invoked unless required by special circumstances.
- *
- * @return IX_ETH_DB_SUCCESS if the operation succeeded
- * or an appropriate error message otherwise
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBPortAddressSet(IxEthDBPortId portID, IxEthDBMacAddr *macAddr)
-{
-    IxNpeMhMessage message;
-    IX_STATUS result;
-
-    /* use this macro instead CHECK_PORT
-       as the port doesn't need to be enabled */
-    IX_ETH_DB_CHECK_PORT_EXISTS(portID);
-
-    IX_ETH_DB_CHECK_REFERENCE(macAddr);
-
-    if (!ixEthDBPortInfo[portID].initialized)
-    {
-        return IX_ETH_DB_PORT_UNINITIALIZED;
-    }
-
-    /* Operation stops here when Ethernet Learning is not enabled */
-    if(IX_FEATURE_CTRL_SWCONFIG_DISABLED ==
-       ixFeatureCtrlSwConfigurationCheck(IX_FEATURECTRL_ETH_LEARNING))
-    {
-        return IX_ETH_DB_SUCCESS;
-    }
-
-    IX_ETH_DB_CHECK_SINGLE_NPE(portID);
-
-    /* exit if the port is not an Ethernet NPE */
-    if (ixEthDBPortDefinitions[portID].type != IX_ETH_NPE)
-    {
-        return IX_ETH_DB_INVALID_PORT;
-    }
-
-    /* populate message */
-    FILL_SETPORTADDRESS_MSG(message, portID, macAddr->macAddress);
-
-    IX_ETH_DB_SUPPORT_TRACE("DB: (Support) Sending SetPortAddress on port %d...\n", portID);
-
-    /* send a SetPortAddress message */
-    IX_ETHDB_SEND_NPE_MSG(IX_ETH_DB_PORT_ID_TO_NPE(portID), message, result);
-
-    if (result == IX_SUCCESS)
-    {
-        ixEthDBPortInfo[portID].macAddressUploaded = true;
-    }
-
-    return result;
-}
diff --git a/drivers/net/npe/IxEthDBCore.c b/drivers/net/npe/IxEthDBCore.c
deleted file mode 100644
index 3d3050d5ce..0000000000
--- a/drivers/net/npe/IxEthDBCore.c
+++ /dev/null
@@ -1,439 +0,0 @@
-/**
- * @file IxEthDBDBCore.c
- *
- * @brief Database support functions
- *
- * @par
- * IXP400 SW Release version 2.0
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * SPDX-License-Identifier:	BSD-3-Clause
- * @par
- * -- End of Copyright Notice --
- */
-
-#include "IxEthDB_p.h"
-
-/* list of database hashtables */
-IX_ETH_DB_PUBLIC HashTable dbHashtable;
-IX_ETH_DB_PUBLIC MatchFunction matchFunctions[IX_ETH_DB_MAX_KEY_INDEX + 1];
-IX_ETH_DB_PUBLIC BOOL ixEthDBPortUpdateRequired[IX_ETH_DB_MAX_RECORD_TYPE_INDEX + 1];
-IX_ETH_DB_PUBLIC UINT32 ixEthDBKeyType[IX_ETH_DB_MAX_RECORD_TYPE_INDEX + 1];
-
-/* private initialization flag */
-IX_ETH_DB_PRIVATE BOOL ethDBInitializationComplete = false;
-
-/**
- * @brief initializes EthDB
- *
- * This function must be called to initialize the component.
- *
- * It does the following things:
- * - checks the port definition structure
- * - scans the capabilities of the NPE images and sets the
- *   capabilities of the ports accordingly
- * - initializes the memory pools internally used in EthDB
- *   for storing database records and handling data
- * - registers automatic update handlers for add and remove
- *   operations
- * - registers hashing match functions, depending on key sets
- * - initializes the main database hashtable
- * - allocates contiguous memory zones to be used for NPE
- *   updates
- * - registers the serialize methods used to convert data
- *   into NPE-readable format
- * - starts the event processor
- *
- * Note that this function is documented in the public
- * component header file, IxEthDB.h.
- *
- * @return IX_ETH_DB_SUCCESS or an appropriate error if the
- * component failed to initialize correctly
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBInit(void)
-{
-    IxEthDBStatus result;
-
-    if (ethDBInitializationComplete)
-    {
-        /* redundant */
-        return IX_ETH_DB_SUCCESS;
-    }
-
-    /* trap an invalid port definition structure */
-    IX_ETH_DB_PORTS_ASSERTION;
-
-    /* memory management */
-    ixEthDBInitMemoryPools();
-
-    /* register hashing search methods */
-    ixEthDBMatchMethodsRegister(matchFunctions);
-
-    /* register type-based automatic port updates */
-    ixEthDBUpdateTypeRegister(ixEthDBPortUpdateRequired);
-
-    /* register record to key type mappings */
-    ixEthDBKeyTypeRegister(ixEthDBKeyType);
-
-    /* hash table */
-    ixEthDBInitHash(&dbHashtable, NUM_BUCKETS, ixEthDBEntryXORHash, matchFunctions, (FreeFunction) ixEthDBFreeMacDescriptor);
-
-    /* NPE update zones */
-    ixEthDBNPEUpdateAreasInit();
-
-    /* register record serialization methods */
-    ixEthDBRecordSerializeMethodsRegister();
-
-    /* start the event processor */
-    result = ixEthDBEventProcessorInit();
-
-    /* scan NPE features */
-    if (result == IX_ETH_DB_SUCCESS)
-    {
-        ixEthDBFeatureCapabilityScan();
-    }
-
-    ethDBInitializationComplete = true;
-
-    return result;
-}
-
-/**
- * @brief prepares EthDB for unloading
- *
- * This function must be called before removing the
- * EthDB component from memory (e.g. doing rmmod in
- * Linux) if the component is to be re-initialized again
- * without rebooting the platform.
- *
- * All the EthDB ports must be disabled before this
- * function is to be called. Failure to disable all
- * the ports will return the IX_ETH_DB_BUSY error.
- *
- * This function will destroy mutexes, deallocate
- * memory and stop the event processor.
- *
- * Note that this function is fully documented in the
- * main component header file, IxEthDB.h.
- *
- * @return IX_ETH_DB_SUCCESS if de-initialization
- * completed successfully or an appropriate error
- * message otherwise
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBUnload(void)
-{
-    IxEthDBPortId portIndex;
-
-    if (!ethDBInitializationComplete)
-    {
-        /* redundant */
-        return IX_ETH_DB_SUCCESS;
-    }
-
-    /* check if any ports are enabled */
-    for (portIndex = 0 ; portIndex < IX_ETH_DB_NUMBER_OF_PORTS ; portIndex++)
-    {
-        if (ixEthDBPortInfo[portIndex].enabled)
-        {
-            return IX_ETH_DB_BUSY;
-        }
-    }
-
-    /* free port resources */
-    for (portIndex = 0 ; portIndex < IX_ETH_DB_NUMBER_OF_PORTS ; portIndex++)
-    {
-        if (ixEthDBPortDefinitions[portIndex].type == IX_ETH_NPE)
-        {
-            ixOsalMutexDestroy(&ixEthDBPortInfo[portIndex].npeAckLock);
-        }
-
-        ixEthDBPortInfo[portIndex].initialized = false;
-    }
-
-    /* shutdown event processor */
-    ixEthDBStopLearningFunction();
-
-    /* deallocate NPE update zones */
-    ixEthDBNPEUpdateAreasUnload();
-
-    ethDBInitializationComplete = false;
-
-    return IX_ETH_DB_SUCCESS;
-}
-
-/**
- * @brief adds a new entry to the Ethernet database
- *
- * @param newRecordTemplate address of the record template to use
- * @param updateTrigger port map containing the update triggers
- * resulting from this update operation
- *
- * Creates a new database entry, populates it with the data
- * copied from the given template and adds the record to the
- * database hash table.
- * It also checks whether the new record type is registered to trigger
- * automatic updates; if it is, the update trigger will contain the
- * port on which the record insertion was performed, as well as the
- * old port in case the addition was a record migration (from one port
- * to the other). The caller can use the updateTrigger to trigger
- * automatic updates on the ports changed as a result of this addition.
- *
- * @retval IX_ETH_DB_SUCCESS addition successful
- * @retval IX_ETH_DB_NOMEM insertion failed, no memory left in the mac descriptor memory pool
- * @retval IX_ETH_DB_BUSY database busy, cannot insert due to locking
- *
- * @internal
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBAdd(MacDescriptor *newRecordTemplate, IxEthDBPortMap updateTrigger)
-{
-    IxEthDBStatus result;
-    MacDescriptor *newDescriptor;
-    IxEthDBPortId originalPortID;
-    HashNode *node = NULL;
-
-    BUSY_RETRY(ixEthDBSearchHashEntry(&dbHashtable, ixEthDBKeyType[newRecordTemplate->type], newRecordTemplate, &node));
-
-    TEST_FIXTURE_INCREMENT_DB_CORE_ACCESS_COUNTER;
-
-    if (node == NULL)
-    {
-        /* not found, create a new one */
-        newDescriptor = ixEthDBAllocMacDescriptor();
-
-        if (newDescriptor == NULL)
-        {
-            return IX_ETH_DB_NOMEM; /* no memory */
-        }
-
-        /* old port does not exist, avoid unnecessary updates */
-        originalPortID = newRecordTemplate->portID;
-    }
-    else
-    {
-        /* a node with the same key exists, will update node */
-        newDescriptor = (MacDescriptor *) node->data;
-
-        /* save original port id */
-        originalPortID = newDescriptor->portID;
-    }
-
-    /* copy/update fields into new record */
-    memcpy(newDescriptor->macAddress, newRecordTemplate->macAddress, sizeof (IxEthDBMacAddr));
-    memcpy(&newDescriptor->recordData, &newRecordTemplate->recordData, sizeof (IxEthDBRecordData));
-
-    newDescriptor->type   = newRecordTemplate->type;
-    newDescriptor->portID = newRecordTemplate->portID;
-    newDescriptor->user   = newRecordTemplate->user;
-
-    if (node == NULL)
-    {
-        /* new record, insert into hashtable */
-        BUSY_RETRY_WITH_RESULT(ixEthDBAddHashEntry(&dbHashtable, newDescriptor), result);
-
-        if (result != IX_ETH_DB_SUCCESS)
-        {
-            ixEthDBFreeMacDescriptor(newDescriptor);
-
-            return result; /* insertion failed */
-        }
-    }
-
-    if (node != NULL)
-    {
-        /* release access */
-        ixEthDBReleaseHashNode(node);
-    }
-
-    /* trigger add/remove update if required by type */
-    if (updateTrigger != NULL &&
-        ixEthDBPortUpdateRequired[newRecordTemplate->type])
-    {
-        /* add new port to update list */
-        JOIN_PORT_TO_MAP(updateTrigger, newRecordTemplate->portID);
-
-        /* check if record has moved, we'll need to update the old port as well */
-        if (originalPortID != newDescriptor->portID)
-        {
-            JOIN_PORT_TO_MAP(updateTrigger, originalPortID);
-        }
-    }
-
-    return IX_ETH_DB_SUCCESS;
-}
-
-/**
- * @brief remove a record from the Ethernet database
- *
- * @param templateRecord template record used to determine
- * what record is to be removed
- * @param updateTrigger port map containing the update triggers
- * resulting from this update operation
- *
- * This function will examine the template record it receives
- * and attempts to delete a record of the same type and containing
- * the same keys as the template record. If deletion is successful
- * and the record type is registered for automatic port updates the
- * port will also be set in the updateTrigger port map, so that the
- * client can perform an update of the port.
- *
- * @retval IX_ETH_DB_SUCCESS removal was successful
- * @retval IX_ETH_DB_NO_SUCH_ADDR the record with the given MAC address was not found
- * @retval IX_ETH_DB_BUSY database busy, cannot remove due to locking
- *
- * @internal
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBRemove(MacDescriptor *templateRecord, IxEthDBPortMap updateTrigger)
-{
-    IxEthDBStatus result;
-
-    TEST_FIXTURE_INCREMENT_DB_CORE_ACCESS_COUNTER;
-
-    BUSY_RETRY_WITH_RESULT(ixEthDBRemoveHashEntry(&dbHashtable, ixEthDBKeyType[templateRecord->type], templateRecord), result);
-
-    if (result != IX_ETH_DB_SUCCESS)
-    {
-        return IX_ETH_DB_NO_SUCH_ADDR; /* not found */
-    }
-
-    /* trigger add/remove update if required by type */
-    if (updateTrigger != NULL
-        &&ixEthDBPortUpdateRequired[templateRecord->type])
-    {
-        /* add new port to update list */
-        JOIN_PORT_TO_MAP(updateTrigger, templateRecord->portID);
-    }
-
-    return IX_ETH_DB_SUCCESS;
-}
-
-/**
- * @brief register record key types
- *
- * This function registers the appropriate key types,
- * depending on record types.
- *
- * All filtering records use the MAC address as the key.
- * WiFi and Firewall records use a compound key consisting
- * in both the MAC address and the port ID.
- *
- * @return the number of registered record types
- */
-IX_ETH_DB_PUBLIC
-UINT32 ixEthDBKeyTypeRegister(UINT32 *keyType)
-{
-    /* safety */
-    memset(keyType, 0, sizeof (keyType));
-
-    /* register all known record types */
-    keyType[IX_ETH_DB_FILTERING_RECORD]      = IX_ETH_DB_MAC_KEY;
-    keyType[IX_ETH_DB_FILTERING_VLAN_RECORD] = IX_ETH_DB_MAC_KEY;
-    keyType[IX_ETH_DB_ALL_FILTERING_RECORDS] = IX_ETH_DB_MAC_KEY;
-    keyType[IX_ETH_DB_WIFI_RECORD]           = IX_ETH_DB_MAC_PORT_KEY;
-    keyType[IX_ETH_DB_FIREWALL_RECORD]       = IX_ETH_DB_MAC_PORT_KEY;
-
-    return 5;
-}
-
-/**
- * @brief Sets a user-defined field into a database record
- *
- * Note that this function is fully documented in the main component
- * header file.
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBUserFieldSet(IxEthDBRecordType recordType, IxEthDBMacAddr *macAddr, IxEthDBPortId portID, IxEthDBVlanId vlanID, void *field)
-{
-    HashNode *result = NULL;
-
-    if (macAddr == NULL)
-    {
-        return IX_ETH_DB_INVALID_ARG;
-    }
-
-    if (recordType == IX_ETH_DB_FILTERING_RECORD)
-    {
-        result = ixEthDBSearch(macAddr, recordType);
-    }
-    else if (recordType == IX_ETH_DB_FILTERING_VLAN_RECORD)
-    {
-        result = ixEthDBVlanSearch(macAddr, vlanID, recordType);
-    }
-    else if (recordType == IX_ETH_DB_WIFI_RECORD || recordType == IX_ETH_DB_FIREWALL_RECORD)
-    {
-        IX_ETH_DB_CHECK_PORT_EXISTS(portID);
-
-        result = ixEthDBPortSearch(macAddr, portID, recordType);
-    }
-    else
-    {
-        return IX_ETH_DB_INVALID_ARG;
-    }
-
-    if (result == NULL)
-    {
-        return IX_ETH_DB_NO_SUCH_ADDR;
-    }
-
-    ((MacDescriptor *) result->data)->user = field;
-
-    ixEthDBReleaseHashNode(result);
-
-    return IX_ETH_DB_SUCCESS;
-}
-
-/**
- * @brief Retrieves a user-defined field from a database record
- *
- * Note that this function is fully documented in the main component
- * header file.
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBUserFieldGet(IxEthDBRecordType recordType, IxEthDBMacAddr *macAddr, IxEthDBPortId portID, IxEthDBVlanId vlanID, void **field)
-{
-    HashNode *result = NULL;
-
-    if (macAddr == NULL || field == NULL)
-    {
-        return IX_ETH_DB_INVALID_ARG;
-    }
-
-    if (recordType == IX_ETH_DB_FILTERING_RECORD)
-    {
-        result = ixEthDBSearch(macAddr, recordType);
-    }
-    else if (recordType == IX_ETH_DB_FILTERING_VLAN_RECORD)
-    {
-        result = ixEthDBVlanSearch(macAddr, vlanID, recordType);
-    }
-    else if (recordType == IX_ETH_DB_WIFI_RECORD || recordType == IX_ETH_DB_FIREWALL_RECORD)
-    {
-        IX_ETH_DB_CHECK_PORT_EXISTS(portID);
-
-        result = ixEthDBPortSearch(macAddr, portID, recordType);
-    }
-    else
-    {
-        return IX_ETH_DB_INVALID_ARG;
-    }
-
-    if (result == NULL)
-    {
-        return IX_ETH_DB_NO_SUCH_ADDR;
-    }
-
-    *field = ((MacDescriptor *) result->data)->user;
-
-    ixEthDBReleaseHashNode(result);
-
-    return IX_ETH_DB_SUCCESS;
-}
diff --git a/drivers/net/npe/IxEthDBEvents.c b/drivers/net/npe/IxEthDBEvents.c
deleted file mode 100644
index 5b3be0b6c1..0000000000
--- a/drivers/net/npe/IxEthDBEvents.c
+++ /dev/null
@@ -1,496 +0,0 @@
-/**
- * @file IxEthDBEvents.c
- *
- * @brief Implementation of the event processor component
- * 
- * @par
- * IXP400 SW Release version 2.0
- * 
- * -- Copyright Notice --
- * 
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- * 
- * @par
- * SPDX-License-Identifier:	BSD-3-Clause
- * @par
- * -- End of Copyright Notice --
- */
-
-#include <IxNpeMh.h>
-#include <IxFeatureCtrl.h>
-
-#include "IxEthDB_p.h"
-
-/* forward prototype declarations */
-IX_ETH_DB_PUBLIC void ixEthDBEventProcessorLoop(void *); 
-IX_ETH_DB_PUBLIC void ixEthDBNPEEventCallback(IxNpeMhNpeId npeID, IxNpeMhMessage msg);
-IX_ETH_DB_PRIVATE void ixEthDBProcessEvent(PortEvent *local_event, IxEthDBPortMap triggerPorts);
-IX_ETH_DB_PRIVATE IxEthDBStatus ixEthDBTriggerPortUpdate(UINT32 eventType, IxEthDBMacAddr *macAddr, IxEthDBPortId portID, BOOL staticEntry);
-IX_ETH_DB_PUBLIC IxEthDBStatus ixEthDBStartLearningFunction(void);
-IX_ETH_DB_PUBLIC IxEthDBStatus ixEthDBStopLearningFunction(void);
-
-/* data */
-IX_ETH_DB_PRIVATE IxOsalSemaphore eventQueueSemaphore;
-IX_ETH_DB_PRIVATE PortEventQueue eventQueue;
-IX_ETH_DB_PRIVATE IxOsalMutex eventQueueLock;
-IX_ETH_DB_PRIVATE IxOsalMutex portUpdateLock;
-
-IX_ETH_DB_PRIVATE BOOL ixEthDBLearningShutdown      = false;
-IX_ETH_DB_PRIVATE BOOL ixEthDBEventProcessorRunning = false;
-
-/* imported data */
-extern HashTable dbHashtable;
-
-/**
- * @brief initializes the event processor
- *
- * Initializes the event processor queue and processing thread.
- * Called from ixEthDBInit() DB-subcomponent master init function.
- *
- * @warning do not call directly
- *
- * @retval IX_ETH_DB_SUCCESS initialization was successful
- * @retval IX_ETH_DB_FAIL initialization failed (OSAL or mutex init failure)
- *
- * @internal
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBEventProcessorInit(void)
-{
-    if (ixOsalMutexInit(&portUpdateLock) != IX_SUCCESS)
-    {
-        return IX_ETH_DB_FAIL;
-    }
-
-    if (ixOsalMutexInit(&eventQueueLock) != IX_SUCCESS)
-    {
-        return IX_ETH_DB_FAIL;
-    }
-
-    if (IX_FEATURE_CTRL_SWCONFIG_ENABLED ==
-        ixFeatureCtrlSwConfigurationCheck (IX_FEATURECTRL_ETH_LEARNING))
-    {
-
-        /* start processor loop thread */
-        if (ixEthDBStartLearningFunction() != IX_ETH_DB_SUCCESS)
-        {
-            return IX_ETH_DB_FAIL;
-        }
-    }
-
-    return IX_ETH_DB_SUCCESS;
-}
-
-/**
- * @brief initializes the event queue and the event processor
- *
- * This function is called by the component initialization
- * function, ixEthDBInit().
- *
- * @warning do not call directly
- *
- * @return IX_ETH_DB_SUCCESS if the operation completed
- * successfully or IX_ETH_DB_FAIL otherwise
- *
- * @internal
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBStartLearningFunction(void)
-{
-    IxOsalThread eventProcessorThread;
-    IxOsalThreadAttr threadAttr;
-
-    threadAttr.name      = "EthDB event thread";
-    threadAttr.stackSize = 32 * 1024; /* 32kbytes */
-    threadAttr.priority  = 128;
-
-    /* reset event queue */
-    ixOsalMutexLock(&eventQueueLock, IX_OSAL_WAIT_FOREVER);
-
-    RESET_QUEUE(&eventQueue);
-
-    ixOsalMutexUnlock(&eventQueueLock);
-
-    /* init event queue semaphore */
-    if (ixOsalSemaphoreInit(&eventQueueSemaphore, 0) != IX_SUCCESS)
-    {
-        return IX_ETH_DB_FAIL;
-    }
-
-    ixEthDBLearningShutdown = false;
-
-    /* create processor loop thread */
-    if (ixOsalThreadCreate(&eventProcessorThread, &threadAttr, ixEthDBEventProcessorLoop, NULL) != IX_SUCCESS)
-    {
-        return IX_ETH_DB_FAIL;
-    }
-
-    /* start event processor */
-    ixOsalThreadStart(&eventProcessorThread);
-
-    return IX_ETH_DB_SUCCESS;
-}
-
-/**
- * @brief stops the event processor
- *
- * Stops the event processor and frees the event queue semaphore
- * Called by the component de-initialization function, ixEthDBUnload()
- *
- * @warning do not call directly
- *
- * @return IX_ETH_DB_SUCCESS if the operation completed 
- * successfully or IX_ETH_DB_FAIL otherwise;
- *
- * @internal
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBStopLearningFunction(void)
-{
-    ixEthDBLearningShutdown = true;
-
-    /* wake up event processing loop to actually process the shutdown event */
-    ixOsalSemaphorePost(&eventQueueSemaphore);
-
-    if (ixOsalSemaphoreDestroy(&eventQueueSemaphore) != IX_SUCCESS)
-    {
-        return IX_ETH_DB_FAIL;
-    }
-
-    return IX_ETH_DB_SUCCESS;
-}
-
-/**
- * @brief default NPE event processing callback
- *
- * @param npeID ID of the NPE that generated the event
- * @param msg NPE message (encapsulated event)
- *
- * Creates an event object on the Ethernet event processor queue
- * and signals the new event by incrementing the event queue semaphore.
- * Events are processed by @ref ixEthDBEventProcessorLoop() which runs
- * at user level.
- *
- * @see ixEthDBEventProcessorLoop()
- *
- * @warning do not call directly
- *
- * @internal
- */
-IX_ETH_DB_PUBLIC
-void ixEthDBNPEEventCallback(IxNpeMhNpeId npeID, IxNpeMhMessage msg)
-{
-    PortEvent *local_event;
-
-    IX_ETH_DB_IRQ_EVENTS_TRACE("DB: (Events) new event received by processor callback from port %d, id 0x%X\n", IX_ETH_DB_NPE_TO_PORT_ID(npeID), NPE_MSG_ID(msg), 0, 0, 0, 0);
-
-    if (CAN_ENQUEUE(&eventQueue))
-    {
-        TEST_FIXTURE_LOCK_EVENT_QUEUE;
-
-        local_event = QUEUE_HEAD(&eventQueue);
-
-        /* create event structure on queue */
-        local_event->eventType = NPE_MSG_ID(msg);
-        local_event->portID    = IX_ETH_DB_NPE_TO_PORT_ID(npeID);
-        
-        /* update queue */
-        PUSH_UPDATE_QUEUE(&eventQueue);
-
-        TEST_FIXTURE_UNLOCK_EVENT_QUEUE;
-
-        IX_ETH_DB_IRQ_EVENTS_TRACE("DB: (Events) Waking up main processor loop...\n", 0, 0, 0, 0, 0, 0);
-
-        /* increment event queue semaphore */
-        ixOsalSemaphorePost(&eventQueueSemaphore);
-    }
-    else
-    {
-        IX_ETH_DB_IRQ_EVENTS_TRACE("DB: (Events) Warning: could not enqueue event (overflow)\n", 0, 0, 0, 0, 0, 0);
-    }
-}
-
-/**
- * @brief Ethernet event processor loop
- *
- * Extracts at most EVENT_PROCESSING_LIMIT batches of events and
- * sends them for processing to @ref ixEthDBProcessEvent().
- * Triggers port updates which normally follow learning events.
- *
- * @warning do not call directly, executes in separate thread
- *
- * @internal
- */
-IX_ETH_DB_PUBLIC
-void ixEthDBEventProcessorLoop(void *unused1)
-{
-    IxEthDBPortMap triggerPorts;
-    IxEthDBPortId portIndex;
-
-    ixEthDBEventProcessorRunning = true;
-
-    IX_ETH_DB_EVENTS_TRACE("DB: (Events) Event processor loop was started\n");
-
-    while (!ixEthDBLearningShutdown)
-    {
-        BOOL keepProcessing    = true;
-        UINT32 processedEvents = 0;
-
-        IX_ETH_DB_EVENTS_VERBOSE_TRACE("DB: (Events) Waiting for new learning event...\n");
-
-        ixOsalSemaphoreWait(&eventQueueSemaphore, IX_OSAL_WAIT_FOREVER);
-
-        IX_ETH_DB_EVENTS_VERBOSE_TRACE("DB: (Events) Received new event\n");
-
-        if (!ixEthDBLearningShutdown)
-        {
-            /* port update handling */
-            SET_EMPTY_DEPENDENCY_MAP(triggerPorts);
-
-            while (keepProcessing)
-            {
-                PortEvent local_event;
-                UINT32 intLockKey;
-
-                /* lock queue */
-                ixOsalMutexLock(&eventQueueLock, IX_OSAL_WAIT_FOREVER);
-
-                /* lock NPE interrupts */
-                intLockKey = ixOsalIrqLock();
-
-                /* extract event */
-                local_event = *(QUEUE_TAIL(&eventQueue));
-
-                SHIFT_UPDATE_QUEUE(&eventQueue);
-
-                ixOsalIrqUnlock(intLockKey);
-
-                ixOsalMutexUnlock(&eventQueueLock);
-
-                IX_ETH_DB_EVENTS_TRACE("DB: (Events) Processing event with ID 0x%X\n", local_event.eventType);
-
-                ixEthDBProcessEvent(&local_event, triggerPorts);
-
-                processedEvents++;
-
-                if (processedEvents > EVENT_PROCESSING_LIMIT /* maximum burst reached? */
-                    || ixOsalSemaphoreTryWait(&eventQueueSemaphore) != IX_SUCCESS) /* or empty queue? */
-                {
-                    keepProcessing = false;
-                }
-            }
-
-            ixEthDBUpdatePortLearningTrees(triggerPorts);
-        }
-    }
-
-    /* turn off automatic updates */
-    for (portIndex = 0 ; portIndex < IX_ETH_DB_NUMBER_OF_PORTS ; portIndex++)
-    {
-        ixEthDBPortInfo[portIndex].updateMethod.updateEnabled = false;
-    }
-
-    ixEthDBEventProcessorRunning = false;
-}
-
-/**
- * @brief event processor routine
- *
- * @param event event to be processed
- * @param triggerPorts port map accumulating ports to be updated
- *
- * Processes learning events by synchronizing the database with
- * newly learnt data. Called only by @ref ixEthDBEventProcessorLoop().
- *
- * @warning do not call directly
- *
- * @internal
- */
-IX_ETH_DB_PRIVATE
-void ixEthDBProcessEvent(PortEvent *local_event, IxEthDBPortMap triggerPorts)
-{
-    MacDescriptor recordTemplate;
-
-    switch (local_event->eventType)
-    {
-        case IX_ETH_DB_ADD_FILTERING_RECORD:
-            /* add record */
-            memset(&recordTemplate, 0, sizeof (recordTemplate));
-            memcpy(recordTemplate.macAddress, local_event->macAddr.macAddress, sizeof (IxEthDBMacAddr));
-            
-            recordTemplate.type   = IX_ETH_DB_FILTERING_RECORD;
-            recordTemplate.portID = local_event->portID;
-            recordTemplate.recordData.filteringData.staticEntry = local_event->staticEntry;
-            
-            ixEthDBAdd(&recordTemplate, triggerPorts);
-
-            IX_ETH_DB_EVENTS_TRACE("DB: (Events) Added record on port %d\n", local_event->portID);
-
-            break;
-
-        case IX_ETH_DB_REMOVE_FILTERING_RECORD:
-            /* remove record */
-            memset(&recordTemplate, 0, sizeof (recordTemplate));
-            memcpy(recordTemplate.macAddress, local_event->macAddr.macAddress, sizeof (IxEthDBMacAddr));
-            
-            recordTemplate.type = IX_ETH_DB_FILTERING_RECORD | IX_ETH_DB_FILTERING_VLAN_RECORD;
-            
-            ixEthDBRemove(&recordTemplate, triggerPorts);
-            
-            IX_ETH_DB_EVENTS_TRACE("DB: (Events) Removed record on port %d\n", local_event->portID);
-
-            break;
-
-        default:
-            /* can't handle/not interested in this event type */
-            ERROR_LOG("DB: (Events) Event processor received an unknown event type (0x%X)\n", local_event->eventType);
-
-            return;
-    }
-}
-
-/**
- * @brief asynchronously adds a filtering record
- * by posting an ADD_FILTERING_RECORD event to the event queue
- *
- * @param macAddr MAC address of the new record
- * @param portID port ID of the new record
- * @param staticEntry true if record is static, false if dynamic
- *
- * @return IX_ETH_DB_SUCCESS if the event creation was
- * successfull or IX_ETH_DB_BUSY if the event queue is full
- *
- * @internal
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBTriggerAddPortUpdate(IxEthDBMacAddr *macAddr, IxEthDBPortId portID, BOOL staticEntry)
-{
-    MacDescriptor reference;
-    
-    TEST_FIXTURE_INCREMENT_DB_CORE_ACCESS_COUNTER;
-
-    /* fill search fields */
-    memcpy(reference.macAddress, macAddr, sizeof (IxEthDBMacAddr));
-    reference.portID = portID;
-    
-    /* set acceptable record types */
-    reference.type = IX_ETH_DB_ALL_FILTERING_RECORDS;
-
-    if (ixEthDBPeekHashEntry(&dbHashtable, IX_ETH_DB_MAC_PORT_KEY, &reference) == IX_ETH_DB_SUCCESS)
-    {
-        /* already have an identical record */
-        return IX_ETH_DB_SUCCESS;
-    }
-    else
-    {
-        return ixEthDBTriggerPortUpdate(IX_ETH_DB_ADD_FILTERING_RECORD, macAddr, portID, staticEntry);
-    }
-}
-
-/**
- * @brief asynchronously removes a filtering record
- * by posting a REMOVE_FILTERING_RECORD event to the event queue
- *
- * @param macAddr MAC address of the record to remove
- * @param portID port ID of the record to remove
- *
- * @return IX_ETH_DB_SUCCESS if the event creation was
- * successfull or IX_ETH_DB_BUSY if the event queue is full
- *
- * @internal
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBTriggerRemovePortUpdate(IxEthDBMacAddr *macAddr, IxEthDBPortId portID)
-{
-    if (ixEthDBPeek(macAddr, IX_ETH_DB_ALL_FILTERING_RECORDS) != IX_ETH_DB_NO_SUCH_ADDR)
-    {
-        return ixEthDBTriggerPortUpdate(IX_ETH_DB_REMOVE_FILTERING_RECORD, macAddr, portID, false);
-    }
-    else
-    {
-        return IX_ETH_DB_NO_SUCH_ADDR;
-    }
-}
-
-/**
- * @brief adds an ADD or REMOVE event to the main event queue
- *
- * @param eventType event type - IX_ETH_DB_ADD_FILTERING_RECORD 
- * to add and IX_ETH_DB_REMOVE_FILTERING_RECORD to remove a
- * record.
- *
- * @return IX_ETH_DB_SUCCESS if the event was successfully
- * sent or IX_ETH_DB_BUSY if the event queue is full
- *
- * @internal
- */
-IX_ETH_DB_PRIVATE
-IxEthDBStatus ixEthDBTriggerPortUpdate(UINT32 eventType, IxEthDBMacAddr *macAddr, IxEthDBPortId portID, BOOL staticEntry)
-{
-    UINT32 intLockKey;
-
-    /* lock interrupts to protect queue */
-    intLockKey = ixOsalIrqLock();
-
-    if (CAN_ENQUEUE(&eventQueue))
-    {
-        PortEvent *queueEvent = QUEUE_HEAD(&eventQueue);
-
-        /* update fields on the queue */
-        memcpy(queueEvent->macAddr.macAddress, macAddr->macAddress, sizeof (IxEthDBMacAddr));
-        
-        queueEvent->eventType     = eventType;
-        queueEvent->portID        = portID;
-        queueEvent->staticEntry   = staticEntry;
-
-        PUSH_UPDATE_QUEUE(&eventQueue);
-
-        /* imcrement event queue semaphore */
-        ixOsalSemaphorePost(&eventQueueSemaphore);
-        
-        /* unlock interrupts */
-        ixOsalIrqUnlock(intLockKey);
-
-        return IX_ETH_DB_SUCCESS;
-    }
-    else /* event queue full */
-    {
-        /* unlock interrupts */
-        ixOsalIrqUnlock(intLockKey);
-
-        return IX_ETH_DB_BUSY;
-    }
-}
-
-/**
- * @brief Locks learning tree updates and port disable
- *
- *
- * This function locks portUpdateLock single mutex. It is primarily used
- * to avoid executing 'port disable' during ELT maintenance.
- *
- * @internal
- */
-IX_ETH_DB_PUBLIC
-void ixEthDBUpdateLock(void)
-{
-    ixOsalMutexLock(&portUpdateLock, IX_OSAL_WAIT_FOREVER);
-}
-
-/**
- * @brief Unlocks learning tree updates and port disable
- *
- *
- * This function unlocks a portUpdateLock mutex. It is primarily used
- * to avoid executing 'port disable' during ELT maintenance.
- *
- * @internal
- */
-IX_ETH_DB_PUBLIC
-void ixEthDBUpdateUnlock(void)
-{
-    ixOsalMutexUnlock(&portUpdateLock);
-}
-
diff --git a/drivers/net/npe/IxEthDBFeatures.c b/drivers/net/npe/IxEthDBFeatures.c
deleted file mode 100644
index 1f7624016a..0000000000
--- a/drivers/net/npe/IxEthDBFeatures.c
+++ /dev/null
@@ -1,638 +0,0 @@
-/**
- * @file IxEthDBFeatures.c
- *
- * @brief Implementation of the EthDB feature control API
- *
- * @par
- * IXP400 SW Release version 2.0
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * SPDX-License-Identifier:	BSD-3-Clause
- * @par
- * -- End of Copyright Notice --
- */
-
-#include "IxNpeDl.h"
-#include "IxEthDBQoS.h"
-#include "IxEthDB_p.h"
-
-/**
- * @brief scans the capabilities of the loaded NPE images
- *
- * This function MUST be called by the ixEthDBInit() function.
- * No EthDB features (including learning and filtering) are enabled
- * before this function is called.
- *
- * @return none
- *
- * @internal
- */
-IX_ETH_DB_PUBLIC
-void ixEthDBFeatureCapabilityScan(void)
-{
-    IxNpeDlImageId imageId, npeAImageId;
-    IxEthDBPortId portIndex;
-    PortInfo *portInfo;
-    IxEthDBPriorityTable defaultPriorityTable;
-    IX_STATUS result;
-    UINT32 queueIndex;
-    UINT32 queueStructureIndex;
-    UINT32 trafficClassDefinitionIndex;
-
-    /* read version of NPE A - required to set the AQM queues for B and C */
-    npeAImageId.functionalityId = 0;
-    ixNpeDlLoadedImageGet(IX_NPEDL_NPEID_NPEA, &npeAImageId);
-
-    for (portIndex = 0 ; portIndex < IX_ETH_DB_NUMBER_OF_PORTS ; portIndex++)
-    {
-        IxNpeMhMessage msg;
-
-        portInfo = &ixEthDBPortInfo[portIndex];
-
-        /* check and bypass if NPE B or C is fused out */
-        if (ixEthDBSingleEthNpeCheck(portIndex) != IX_ETH_DB_SUCCESS) continue;
-
-        /* all ports are capable of LEARNING by default */
-        portInfo->featureCapability |= IX_ETH_DB_LEARNING;
-        portInfo->featureStatus     |= IX_ETH_DB_LEARNING;
-
-        if (ixEthDBPortDefinitions[portIndex].type == IX_ETH_NPE)
-        {
-
-            if (ixNpeDlLoadedImageGet(IX_ETH_DB_PORT_ID_TO_NPE(portIndex), &imageId) != IX_SUCCESS)
-            {
-                WARNING_LOG("DB: (FeatureScan) NpeDl did not provide the image ID for NPE port %d\n", portIndex);
-            }
-            else
-            {
-                /* initialize and empty NPE response mutex */
-                ixOsalMutexInit(&portInfo->npeAckLock);
-                ixOsalMutexLock(&portInfo->npeAckLock, IX_OSAL_WAIT_FOREVER);
-
-                /* check NPE response to GetStatus */
-                msg.data[0] = IX_ETHNPE_NPE_GETSTATUS << 24;
-                msg.data[1] = 0;
-                IX_ETHDB_SEND_NPE_MSG(IX_ETH_DB_PORT_ID_TO_NPE(portIndex), msg, result);
-                if (result != IX_SUCCESS)
-                {
-                    WARNING_LOG("DB: (FeatureScan) warning, could not send message to the NPE\n");
-                    continue;
-                }
-
-
-                if (imageId.functionalityId == 0x00
-                    || imageId.functionalityId == 0x03
-                    || imageId.functionalityId == 0x04
-                    || imageId.functionalityId == 0x80)
-                {
-                    portInfo->featureCapability |= IX_ETH_DB_FILTERING;
-                    portInfo->featureCapability |= IX_ETH_DB_FIREWALL;
-                    portInfo->featureCapability |= IX_ETH_DB_SPANNING_TREE_PROTOCOL;
-                }
-                else if (imageId.functionalityId == 0x01
-                         || imageId.functionalityId == 0x81)
-                {
-                    portInfo->featureCapability |= IX_ETH_DB_FILTERING;
-                    portInfo->featureCapability |= IX_ETH_DB_FIREWALL;
-                    portInfo->featureCapability |= IX_ETH_DB_SPANNING_TREE_PROTOCOL;
-                    portInfo->featureCapability |= IX_ETH_DB_VLAN_QOS;
-                }
-                else if (imageId.functionalityId == 0x02
-                         || imageId.functionalityId == 0x82)
-                {
-                    portInfo->featureCapability |= IX_ETH_DB_WIFI_HEADER_CONVERSION;
-                    portInfo->featureCapability |= IX_ETH_DB_FIREWALL;
-                    portInfo->featureCapability |= IX_ETH_DB_SPANNING_TREE_PROTOCOL;
-                    portInfo->featureCapability |= IX_ETH_DB_VLAN_QOS;
-                }
-
-                /* reset AQM queues */
-                memset(portInfo->ixEthDBTrafficClassAQMAssignments, 0, sizeof (portInfo->ixEthDBTrafficClassAQMAssignments));
-
-                /* ensure there's at least one traffic class record in the definition table, otherwise we have no default case, hence no queues */
-                IX_ENSURE(sizeof (ixEthDBTrafficClassDefinitions) != 0, "DB: no traffic class definitions found, check IxEthDBQoS.h");
-
-                /* find the traffic class definition index compatible with the current NPE A functionality ID */
-                for (trafficClassDefinitionIndex = 0 ;
-                    trafficClassDefinitionIndex < ARRAY_SIZE(ixEthDBTrafficClassDefinitions);
-                    trafficClassDefinitionIndex++)
-                {
-                    if (ixEthDBTrafficClassDefinitions[trafficClassDefinitionIndex][IX_ETH_DB_NPE_A_FUNCTIONALITY_ID_INDEX] == npeAImageId.functionalityId)
-                    {
-                        /* found it */
-                        break;
-                    }
-                }
-
-                /* select the default case if we went over the array boundary */
-                if (trafficClassDefinitionIndex == ARRAY_SIZE(ixEthDBTrafficClassDefinitions))
-                {
-                    trafficClassDefinitionIndex = 0; /* the first record is the default case */
-                }
-
-                /* select queue assignment structure based on the traffic class configuration index */
-                queueStructureIndex = ixEthDBTrafficClassDefinitions[trafficClassDefinitionIndex][IX_ETH_DB_QUEUE_ASSIGNMENT_INDEX];
-
-                /* only traffic class 0 is active at initialization time */
-                portInfo->ixEthDBTrafficClassCount = 1;
-
-                /* enable port, VLAN and Firewall feature bits to initialize QoS/VLAN/Firewall configuration */
-                portInfo->featureStatus |= IX_ETH_DB_VLAN_QOS;
-                portInfo->featureStatus |= IX_ETH_DB_FIREWALL;
-                portInfo->enabled        = true;
-
-#define CONFIG_WITH_VLAN  /* test-only: VLAN support not included to save space!!! */
-#ifdef CONFIG_WITH_VLAN /* test-only: VLAN support not included to save space!!! */
-                /* set VLAN initial configuration (permissive) */
-                if ((portInfo->featureCapability & IX_ETH_DB_VLAN_QOS) != 0) /* QoS-enabled image */
-                {
-                    /* QoS capable */
-                    portInfo->ixEthDBTrafficClassAvailable = ixEthDBTrafficClassDefinitions[trafficClassDefinitionIndex][IX_ETH_DB_TRAFFIC_CLASS_COUNT_INDEX];
-
-                    /* set AQM queues */
-                    for (queueIndex = 0 ; queueIndex < IX_IEEE802_1Q_QOS_PRIORITY_COUNT ; queueIndex++)
-                    {
-                        portInfo->ixEthDBTrafficClassAQMAssignments[queueIndex] = ixEthDBQueueAssignments[queueStructureIndex][queueIndex];
-                    }
-
-                    /* set default PVID (0) and default traffic class 0 */
-                    ixEthDBPortVlanTagSet(portIndex, 0);
-
-                    /* enable reception of all frames */
-                    ixEthDBAcceptableFrameTypeSet(portIndex, IX_ETH_DB_ACCEPT_ALL_FRAMES);
-
-                    /* clear full VLAN membership */
-                    ixEthDBPortVlanMembershipRangeRemove(portIndex, 0, IX_ETH_DB_802_1Q_MAX_VLAN_ID);
-
-                    /* clear TTI table - no VLAN tagged frames will be transmitted */
-                    ixEthDBEgressVlanRangeTaggingEnabledSet(portIndex, 0, 4094, false);
-
-                    /* set membership on 0, otherwise no Tx or Rx is working */
-                    ixEthDBPortVlanMembershipAdd(portIndex, 0);
-                }
-                else /* QoS not available in this image */
-#endif /* test-only */
-                {
-                    /* initialize traffic class availability (only class 0 is available) */
-                    portInfo->ixEthDBTrafficClassAvailable = 1;
-
-                    /* point all AQM queues to traffic class 0 */
-                    for (queueIndex = 0 ; queueIndex < IX_IEEE802_1Q_QOS_PRIORITY_COUNT ; queueIndex++)
-                    {
-                        portInfo->ixEthDBTrafficClassAQMAssignments[queueIndex] =
-                            ixEthDBQueueAssignments[queueStructureIndex][0];
-                    }
-                }
-
-#ifdef CONFIG_WITH_VLAN /* test-only: VLAN support not included to save space!!! */
-                /* download priority mapping table and Rx queue configuration */
-                memset (defaultPriorityTable, 0, sizeof (defaultPriorityTable));
-                ixEthDBPriorityMappingTableSet(portIndex, defaultPriorityTable);
-#endif
-
-                /* by default we turn off invalid source MAC address filtering */
-                ixEthDBFirewallInvalidAddressFilterEnable(portIndex, false);
-
-                /* disable port, VLAN, Firewall feature bits */
-                portInfo->featureStatus &= ~IX_ETH_DB_VLAN_QOS;
-                portInfo->featureStatus &= ~IX_ETH_DB_FIREWALL;
-                portInfo->enabled        = false;
-
-                /* enable filtering by default if present */
-                if ((portInfo->featureCapability & IX_ETH_DB_FILTERING) != 0)
-                {
-                    portInfo->featureStatus |= IX_ETH_DB_FILTERING;
-                }
-            }
-        }
-    }
-}
-
-/**
- * @brief returns the capability of a port
- *
- * @param portID ID of the port
- * @param featureSet location to store the port capability in
- *
- * This function will save the capability set of the given port
- * into the given location. Capabilities are bit-ORed, each representing
- * a bit of the feature set.
- *
- * Note that this function is documented in the main component
- * public header file, IxEthDB.h.
- *
- * @return IX_ETH_DB_SUCCESS if the operation completed successfully
- * or IX_ETH_DB_INVALID_PORT if the given port is invalid
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBFeatureCapabilityGet(IxEthDBPortId portID, IxEthDBFeature *featureSet)
-{
-    IX_ETH_DB_CHECK_PORT_INITIALIZED(portID);
-
-    IX_ETH_DB_CHECK_REFERENCE(featureSet);
-
-    *featureSet = ixEthDBPortInfo[portID].featureCapability;
-
-    return IX_ETH_DB_SUCCESS;
-}
-
-/**
- * @brief enables or disables a port capability
- *
- * @param portID ID of the port
- * @param feature feature to enable or disable
- * @param enabled true to enable the selected feature or false to disable it
- *
- * Note that this function is documented in the main component
- * header file, IxEthDB.h.
- *
- * @return IX_ETH_DB_SUCCESS if the operation completed
- * successfully or an appropriate error message otherwise
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBFeatureEnable(IxEthDBPortId portID, IxEthDBFeature feature, BOOL enable)
-{
-    PortInfo *portInfo;
-    IxEthDBPriorityTable defaultPriorityTable;
-    IxEthDBVlanSet vlanSet;
-    IxEthDBStatus status = IX_ETH_DB_SUCCESS;
-    BOOL portEnabled;
-
-    IX_ETH_DB_CHECK_PORT_INITIALIZED(portID);
-
-    portInfo    = &ixEthDBPortInfo[portID];
-    portEnabled = portInfo->enabled;
-
-    /* check that only one feature is selected */
-    if (!ixEthDBCheckSingleBitValue(feature))
-    {
-        return IX_ETH_DB_FEATURE_UNAVAILABLE;
-    }
-
-    /* port capable of this feature? */
-    if ((portInfo->featureCapability & feature) == 0)
-    {
-        return IX_ETH_DB_FEATURE_UNAVAILABLE;
-    }
-
-    /* mutual exclusion between learning and WiFi header conversion */
-    if (enable && ((feature | portInfo->featureStatus) & (IX_ETH_DB_FILTERING | IX_ETH_DB_WIFI_HEADER_CONVERSION))
-            == (IX_ETH_DB_FILTERING | IX_ETH_DB_WIFI_HEADER_CONVERSION))
-    {
-        return IX_ETH_DB_NO_PERMISSION;
-    }
-
-    /* learning must be enabled before filtering */
-    if (enable && (feature == IX_ETH_DB_FILTERING) && ((portInfo->featureStatus & IX_ETH_DB_LEARNING) == 0))
-    {
-        return IX_ETH_DB_NO_PERMISSION;
-    }
-
-    /* filtering must be disabled before learning */
-    if (!enable && (feature == IX_ETH_DB_LEARNING) && ((portInfo->featureStatus & IX_ETH_DB_FILTERING) != 0))
-    {
-        return IX_ETH_DB_NO_PERMISSION;
-    }
-
-    /* redundant enabling or disabling */
-    if ((!enable && ((portInfo->featureStatus & feature) == 0))
-        || (enable && ((portInfo->featureStatus & feature) != 0)))
-    {
-        /* do nothing */
-        return IX_ETH_DB_SUCCESS;
-    }
-
-    /* force port enabled */
-    portInfo->enabled = true;
-
-    if (enable)
-    {
-        /* turn on enable bit */
-        portInfo->featureStatus |= feature;
-
-#ifdef CONFIG_WITH_VLAN /* test-only: VLAN support not included to save space!!! */
-        /* if this is VLAN/QoS set the default priority table */
-        if (feature == IX_ETH_DB_VLAN_QOS)
-        {
-            /* turn on VLAN/QoS (most permissive mode):
-                - set default 802.1Q priority mapping table, in accordance to the
-                  availability of traffic classes
-                - set the acceptable frame filter to accept all
-                - set the Ingress tagging mode to pass-through
-                - set full VLAN membership list
-                - set full TTI table
-                - set the default 802.1Q tag to 0 (VLAN ID 0, Pri 0, CFI 0)
-                - enable TPID port extraction
-            */
-
-            portInfo->ixEthDBTrafficClassCount = portInfo->ixEthDBTrafficClassAvailable;
-
-            /* set default 802.1Q priority mapping table - note that C indexing starts from 0, so we substract 1 here */
-            memcpy (defaultPriorityTable,
-                (const void *) ixEthIEEE802_1QUserPriorityToTrafficClassMapping[portInfo->ixEthDBTrafficClassCount - 1],
-                sizeof (defaultPriorityTable));
-
-            /* update priority mapping and AQM queue assignments */
-            status = ixEthDBPriorityMappingTableSet(portID, defaultPriorityTable);
-
-            if (status == IX_ETH_DB_SUCCESS)
-            {
-                status = ixEthDBAcceptableFrameTypeSet(portID, IX_ETH_DB_ACCEPT_ALL_FRAMES);
-            }
-
-            if (status == IX_ETH_DB_SUCCESS)
-            {
-                status = ixEthDBIngressVlanTaggingEnabledSet(portID, IX_ETH_DB_PASS_THROUGH);
-            }
-
-            /* set membership and TTI tables */
-            memset (vlanSet, 0xFF, sizeof (vlanSet));
-
-            if (status == IX_ETH_DB_SUCCESS)
-            {
-                /* use the internal function to bypass PVID check */
-                status = ixEthDBPortVlanTableSet(portID, portInfo->vlanMembership, vlanSet);
-            }
-
-            if (status == IX_ETH_DB_SUCCESS)
-            {
-                /* use the internal function to bypass PVID check */
-                status = ixEthDBPortVlanTableSet(portID, portInfo->transmitTaggingInfo, vlanSet);
-            }
-
-            /* reset the PVID */
-            if (status == IX_ETH_DB_SUCCESS)
-            {
-                status = ixEthDBPortVlanTagSet(portID, 0);
-            }
-
-            /* enable TPID port extraction */
-            if (status == IX_ETH_DB_SUCCESS)
-            {
-                status = ixEthDBVlanPortExtractionEnable(portID, true);
-            }
-        }
-        else if (feature == IX_ETH_DB_FIREWALL)
-#endif
-        {
-            /* firewall starts in black-list mode unless otherwise configured before *
-             * note that invalid source MAC address filtering is disabled by default */
-            if (portInfo->firewallMode != IX_ETH_DB_FIREWALL_BLACK_LIST
-                && portInfo->firewallMode != IX_ETH_DB_FIREWALL_WHITE_LIST)
-            {
-                status = ixEthDBFirewallModeSet(portID, IX_ETH_DB_FIREWALL_BLACK_LIST);
-
-                if (status == IX_ETH_DB_SUCCESS)
-                {
-                    status = ixEthDBFirewallInvalidAddressFilterEnable(portID, false);
-                }
-            }
-        }
-
-        if (status != IX_ETH_DB_SUCCESS)
-        {
-            /* checks failed, disable */
-            portInfo->featureStatus &= ~feature;
-        }
-    }
-    else
-    {
-        /* turn off features */
-        if (feature == IX_ETH_DB_FIREWALL)
-        {
-            /* turning off the firewall is equivalent to:
-                - set to black-list mode
-                - clear all the entries and download the new table
-                - turn off the invalid source address checking
-            */
-
-            status = ixEthDBDatabaseClear(portID, IX_ETH_DB_FIREWALL_RECORD);
-
-            if (status == IX_ETH_DB_SUCCESS)
-            {
-                status = ixEthDBFirewallModeSet(portID, IX_ETH_DB_FIREWALL_BLACK_LIST);
-            }
-
-            if (status == IX_ETH_DB_SUCCESS)
-            {
-                status = ixEthDBFirewallInvalidAddressFilterEnable(portID, false);
-            }
-
-            if (status == IX_ETH_DB_SUCCESS)
-            {
-                status = ixEthDBFirewallTableDownload(portID);
-            }
-        }
-        else if (feature == IX_ETH_DB_WIFI_HEADER_CONVERSION)
-        {
-            /* turn off header conversion */
-            status = ixEthDBDatabaseClear(portID, IX_ETH_DB_WIFI_RECORD);
-
-            if (status == IX_ETH_DB_SUCCESS)
-            {
-                status = ixEthDBWiFiConversionTableDownload(portID);
-            }
-        }
-#ifdef CONFIG_WITH_VLAN /* test-only: VLAN support not included to save space!!! */
-        else if (feature == IX_ETH_DB_VLAN_QOS)
-        {
-            /* turn off VLAN/QoS:
-                - set a priority mapping table with one traffic class
-                - set the acceptable frame filter to accept all
-                - set the Ingress tagging mode to pass-through
-                - clear the VLAN membership list
-                - clear the TTI table
-                - set the default 802.1Q tag to 0 (VLAN ID 0, Pri 0, CFI 0)
-                - disable TPID port extraction
-            */
-
-            /* initialize all => traffic class 0 priority mapping table */
-            memset (defaultPriorityTable, 0, sizeof (defaultPriorityTable));
-            portInfo->ixEthDBTrafficClassCount = 1;
-            status = ixEthDBPriorityMappingTableSet(portID, defaultPriorityTable);
-
-            if (status == IX_ETH_DB_SUCCESS)
-            {
-                status = ixEthDBAcceptableFrameTypeSet(portID, IX_ETH_DB_ACCEPT_ALL_FRAMES);
-            }
-
-            if (status == IX_ETH_DB_SUCCESS)
-            {
-                status = ixEthDBIngressVlanTaggingEnabledSet(portID, IX_ETH_DB_PASS_THROUGH);
-            }
-
-            /* clear membership and TTI tables */
-            memset (vlanSet, 0, sizeof (vlanSet));
-
-            if (status == IX_ETH_DB_SUCCESS)
-            {
-                /* use the internal function to bypass PVID check */
-                status = ixEthDBPortVlanTableSet(portID, portInfo->vlanMembership, vlanSet);
-            }
-
-            if (status == IX_ETH_DB_SUCCESS)
-            {
-                /* use the internal function to bypass PVID check */
-                status = ixEthDBPortVlanTableSet(portID, portInfo->transmitTaggingInfo, vlanSet);
-            }
-
-            /* reset the PVID */
-            if (status == IX_ETH_DB_SUCCESS)
-            {
-                status = ixEthDBPortVlanTagSet(portID, 0);
-            }
-
-            /* disable TPID port extraction */
-            if (status == IX_ETH_DB_SUCCESS)
-            {
-                status = ixEthDBVlanPortExtractionEnable(portID, false);
-            }
-        }
-#endif
-
-        if (status == IX_ETH_DB_SUCCESS)
-        {
-            /* checks passed, disable */
-            portInfo->featureStatus &= ~feature;
-        }
-    }
-
-    /* restore port enabled state */
-    portInfo->enabled = portEnabled;
-
-    return status;
-}
-
-/**
- * @brief returns the status of a feature
- *
- * @param portID port ID
- * @param present location to store a boolean value indicating
- * if the feature is present (true) or not (false)
- * @param enabled location to store a booleam value indicating
- * if the feature is present (true) or not (false)
- *
- * Note that this function is documented in the main component
- * header file, IxEthDB.h.
- *
- * @return IX_ETH_DB_SUCCESS if the operation completed
- * successfully or an appropriate error message otherwise
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBFeatureStatusGet(IxEthDBPortId portID, IxEthDBFeature feature, BOOL *present, BOOL *enabled)
-{
-    PortInfo *portInfo;
-
-    IX_ETH_DB_CHECK_PORT(portID);
-
-    IX_ETH_DB_CHECK_REFERENCE(present);
-
-    IX_ETH_DB_CHECK_REFERENCE(enabled);
-
-    portInfo = &ixEthDBPortInfo[portID];
-
-    *present = (portInfo->featureCapability & feature) != 0;
-    *enabled = (portInfo->featureStatus & feature) != 0;
-
-    return IX_ETH_DB_SUCCESS;
-}
-
-/**
- * @brief returns the value of an EthDB property
- *
- * @param portID ID of the port
- * @param feature feature owning the property
- * @param property ID of the property
- * @param type location to store the property type into
- * @param value location to store the property value into
- *
- * Note that this function is documented in the main component
- * header file, IxEthDB.h.
- *
- * @return IX_ETH_DB_SUCCESS if the operation completed
- * successfully or an appropriate error message otherwise
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBFeaturePropertyGet(IxEthDBPortId portID, IxEthDBFeature feature, IxEthDBProperty property, IxEthDBPropertyType *type, void *value)
-{
-    IX_ETH_DB_CHECK_PORT_EXISTS(portID);
-
-    IX_ETH_DB_CHECK_REFERENCE(type);
-
-    IX_ETH_DB_CHECK_REFERENCE(value);
-
-    if (feature == IX_ETH_DB_VLAN_QOS)
-    {
-        if (property == IX_ETH_DB_QOS_TRAFFIC_CLASS_COUNT_PROPERTY)
-        {
-            * (UINT32 *) value = ixEthDBPortInfo[portID].ixEthDBTrafficClassCount;
-            *type              = IX_ETH_DB_INTEGER_PROPERTY;
-
-            return IX_ETH_DB_SUCCESS;
-        }
-        else if (property >= IX_ETH_DB_QOS_TRAFFIC_CLASS_0_RX_QUEUE_PROPERTY
-            && property <= IX_ETH_DB_QOS_TRAFFIC_CLASS_7_RX_QUEUE_PROPERTY)
-        {
-            UINT32 classDelta = property - IX_ETH_DB_QOS_TRAFFIC_CLASS_0_RX_QUEUE_PROPERTY;
-
-            if (classDelta >= ixEthDBPortInfo[portID].ixEthDBTrafficClassCount)
-            {
-                return IX_ETH_DB_FAIL;
-            }
-
-            * (UINT32 *) value = ixEthDBPortInfo[portID].ixEthDBTrafficClassAQMAssignments[classDelta];
-            *type              = IX_ETH_DB_INTEGER_PROPERTY;
-
-            return IX_ETH_DB_SUCCESS;
-        }
-    }
-
-    return IX_ETH_DB_INVALID_ARG;
-}
-
-/**
- * @brief sets the value of an EthDB property
- *
- * @param portID ID of the port
- * @param feature feature owning the property
- * @param property ID of the property
- * @param value location containing the property value
- *
- * This function implements a private property intended
- * only for EthAcc usage. Upon setting the IX_ETH_DB_QOS_QUEUE_CONFIGURATION_COMPLETE
- * property (the value is ignored), the availability of traffic classes is
- * frozen to whatever traffic class structure is currently in use.
- * This means that if VLAN_QOS has been enabled before EthAcc
- * initialization then all the defined traffic classes will be available;
- * otherwise only one traffic class (0) will be available.
- *
- * Note that this function is documented in the main component
- * header file, IxEthDB.h as not accepting any parameters. The
- * current implementation is only intended for the private use of EthAcc.
- *
- * Also note that once this function is called the effect is irreversible,
- * unless EthDB is complete unloaded and re-initialized.
- *
- * @return IX_ETH_DB_INVALID_ARG (no read-write properties are
- * supported in this release)
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBFeaturePropertySet(IxEthDBPortId portID, IxEthDBFeature feature, IxEthDBProperty property, void *value)
-{
-    IX_ETH_DB_CHECK_PORT_EXISTS(portID);
-
-    if ((feature == IX_ETH_DB_VLAN_QOS) && (property == IX_ETH_DB_QOS_QUEUE_CONFIGURATION_COMPLETE))
-    {
-        ixEthDBPortInfo[portID].ixEthDBTrafficClassAvailable = ixEthDBPortInfo[portID].ixEthDBTrafficClassCount;
-
-        return IX_ETH_DB_SUCCESS;
-    }
-
-    return IX_ETH_DB_INVALID_ARG;
-}
diff --git a/drivers/net/npe/IxEthDBFirewall.c b/drivers/net/npe/IxEthDBFirewall.c
deleted file mode 100644
index c0ae5624ff..0000000000
--- a/drivers/net/npe/IxEthDBFirewall.c
+++ /dev/null
@@ -1,242 +0,0 @@
-/**
- * @file IxEthDBFirewall.c
- *
- * @brief Implementation of the firewall API
- * 
- * @par
- * IXP400 SW Release version 2.0
- * 
- * -- Copyright Notice --
- * 
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- * 
- * @par
- * SPDX-License-Identifier:	BSD-3-Clause
- * @par
- * -- End of Copyright Notice --
- */
-
-
-#include "IxEthDB_p.h"
-
-/**
- * @brief updates the NPE firewall operating mode and 
- * firewall address table
- *
- * @param portID ID of the port
- * @param epDelta initial entry point for binary searches (NPE optimization)
- * @param address address of the firewall MAC address table
- *
- * This function will send a message to the NPE configuring the
- * firewall mode (white list or black list), invalid source 
- * address filtering and downloading a new MAC address database 
- * to be used for firewall matching.
- *
- * @return IX_ETH_DB_SUCCESS if the operation completed 
- * successfully or IX_ETH_DB_FAIL otherwise
- *
- * @internal
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBFirewallUpdate(IxEthDBPortId portID, void *address, UINT32 epDelta)
-{
-    IxNpeMhMessage message;
-    IX_STATUS result;
-    
-    UINT32 mode        = 0;    
-    PortInfo *portInfo = &ixEthDBPortInfo[portID];
-
-    mode = (portInfo->srcAddressFilterEnabled != false) << 1 | (portInfo->firewallMode == IX_ETH_DB_FIREWALL_WHITE_LIST);
-
-    FILL_SETFIREWALLMODE_MSG(message, 
-        IX_ETH_DB_PORT_ID_TO_NPE_LOGICAL_ID(portID), 
-        epDelta, 
-        mode, 
-        IX_OSAL_MMU_VIRT_TO_PHYS(address));
-
-    IX_ETHDB_SEND_NPE_MSG(IX_ETH_DB_PORT_ID_TO_NPE(portID), message, result);
-    
-    return result;
-}
-
-/**
- * @brief configures the firewall white list/black list
- * access mode
- *
- * @param portID ID of the port
- * @param mode firewall filtering mode (IX_ETH_DB_FIREWALL_WHITE_LIST
- * or IX_ETH_DB_FIREWALL_BLACK_LIST)
- *
- * Note that this function is documented in the main component
- * header file, IxEthDB.h.
- *
- * @return IX_ETH_DB_SUCCESS if the operation completed
- * successfully or an appropriate error message otherwise
- */
-IX_ETH_DB_PUBLIC 
-IxEthDBStatus ixEthDBFirewallModeSet(IxEthDBPortId portID, IxEthDBFirewallMode mode)
-{
-    IX_ETH_DB_CHECK_PORT(portID);
-    
-    IX_ETH_DB_CHECK_SINGLE_NPE(portID);
-     
-    IX_ETH_DB_CHECK_FEATURE(portID, IX_ETH_DB_FIREWALL);
-    
-    if (mode != IX_ETH_DB_FIREWALL_WHITE_LIST
-        && mode != IX_ETH_DB_FIREWALL_BLACK_LIST)
-    {
-        return IX_ETH_DB_INVALID_ARG;
-    }    
-    
-    ixEthDBPortInfo[portID].firewallMode = mode;
-    
-    return ixEthDBFirewallTableDownload(portID);
-}
-
-/**
- * @brief enables or disables the invalid source MAC address filter
- *
- * @param portID ID of the port
- * @param enable true to enable invalid source MAC address filtering
- * or false to disable it
- *
- * The invalid source MAC address filter will discard, when enabled,
- * frames whose source MAC address is a multicast or the broadcast MAC
- * address.
- *
- * Note that this function is documented in the main component
- * header file, IxEthDB.h.
- *
- * @return IX_ETH_DB_SUCCESS if the operation completed 
- * successfully or an appropriate error message otherwise
- */
-IX_ETH_DB_PUBLIC 
-IxEthDBStatus ixEthDBFirewallInvalidAddressFilterEnable(IxEthDBPortId portID, BOOL enable)
-{
-    IX_ETH_DB_CHECK_PORT(portID);
-    
-    IX_ETH_DB_CHECK_SINGLE_NPE(portID);
-    
-    IX_ETH_DB_CHECK_FEATURE(portID, IX_ETH_DB_FIREWALL);
-
-    ixEthDBPortInfo[portID].srcAddressFilterEnabled = enable;
-    
-    return ixEthDBFirewallTableDownload(portID);
-}
-
-/**
- * @brief adds a firewall record
- *
- * @param portID ID of the port
- * @param macAddr MAC address of the new record
- *
- * This function will add a new firewall record
- * on the specified port, using the specified 
- * MAC address. If the record already exists this
- * function will silently return IX_ETH_DB_SUCCESS,
- * although no duplicate records are added.
- *
- * Note that this function is documented in the main
- * component header file, IxEthDB.h.
- *
- * @return IX_ETH_DB_SUCCESS if the operation completed
- * successfully or an appropriate error message otherwise
- */
-IX_ETH_DB_PUBLIC 
-IxEthDBStatus ixEthDBFirewallEntryAdd(IxEthDBPortId portID, IxEthDBMacAddr *macAddr)
-{
-    MacDescriptor recordTemplate;
-
-    IX_ETH_DB_CHECK_PORT(portID);
-
-    IX_ETH_DB_CHECK_SINGLE_NPE(portID);
-
-    IX_ETH_DB_CHECK_REFERENCE(macAddr);
-
-    IX_ETH_DB_CHECK_FEATURE(portID, IX_ETH_DB_FIREWALL);
-    
-    memcpy(recordTemplate.macAddress, macAddr, sizeof (IxEthDBMacAddr));
-    
-    recordTemplate.type   = IX_ETH_DB_FIREWALL_RECORD;
-    recordTemplate.portID = portID;
-    
-    return ixEthDBAdd(&recordTemplate, NULL);
-}
-
-/**
- * @brief removes a firewall record
- *
- * @param portID ID of the port
- * @param macAddr MAC address of the record to remove
- *
- * This function will attempt to remove a firewall
- * record from the given port, using the specified
- * MAC address.
- *
- * Note that this function is documented in the main
- * component header file, IxEthDB.h.
- *
- * @return IX_ETH_DB_SUCCESS if the operation completed
- * successfully of an appropriate error message otherwise
- */
-IX_ETH_DB_PUBLIC 
-IxEthDBStatus ixEthDBFirewallEntryRemove(IxEthDBPortId portID, IxEthDBMacAddr *macAddr)
-{
-    MacDescriptor recordTemplate;
-    
-    IX_ETH_DB_CHECK_PORT(portID);
-
-    IX_ETH_DB_CHECK_SINGLE_NPE(portID);
-
-    IX_ETH_DB_CHECK_REFERENCE(macAddr);
-
-    IX_ETH_DB_CHECK_FEATURE(portID, IX_ETH_DB_FIREWALL);
-    
-    memcpy(recordTemplate.macAddress, macAddr, sizeof (IxEthDBMacAddr));
-    
-    recordTemplate.type   = IX_ETH_DB_FIREWALL_RECORD;
-    recordTemplate.portID = portID;
-    
-    return ixEthDBRemove(&recordTemplate, NULL);
-}
-
-/**
- * @brief downloads the firewall address table to an NPE
- *
- * @param portID ID of the port
- *
- * This function will download the firewall address table to
- * an NPE port.
- *
- * Note that this function is documented in the main 
- * component header file, IxEthDB.h.
- *
- * @return IX_ETH_DB_SUCCESS if the operation completed
- * successfully or IX_ETH_DB_FAIL otherwise
- */
-IX_ETH_DB_PUBLIC 
-IxEthDBStatus ixEthDBFirewallTableDownload(IxEthDBPortId portID)
-{
-    IxEthDBPortMap query;
-    IxEthDBStatus result;
-    
-    IX_ETH_DB_CHECK_PORT(portID);
-
-    IX_ETH_DB_CHECK_SINGLE_NPE(portID);
-
-    IX_ETH_DB_CHECK_FEATURE(portID, IX_ETH_DB_FIREWALL);
-    
-    SET_DEPENDENCY_MAP(query, portID);
-
-    ixEthDBUpdateLock();
-    
-    ixEthDBPortInfo[portID].updateMethod.searchTree = ixEthDBQuery(NULL, query, IX_ETH_DB_FIREWALL_RECORD, MAX_FW_SIZE);
-    
-    result = ixEthDBNPEUpdateHandler(portID, IX_ETH_DB_FIREWALL_RECORD);
-
-    ixEthDBUpdateUnlock();
-
-    return result;
-}
diff --git a/drivers/net/npe/IxEthDBHashtable.c b/drivers/net/npe/IxEthDBHashtable.c
deleted file mode 100644
index 9493a5b48b..0000000000
--- a/drivers/net/npe/IxEthDBHashtable.c
+++ /dev/null
@@ -1,618 +0,0 @@
-/**
- * @file ethHash.c
- *
- * @brief Hashtable implementation
- * 
- * @par
- * IXP400 SW Release version 2.0
- * 
- * -- Copyright Notice --
- * 
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- * 
- * @par
- * SPDX-License-Identifier:	BSD-3-Clause
- * @par
- * -- End of Copyright Notice --
- */
-
-
-#include "IxEthDB_p.h"
-#include "IxEthDBLocks_p.h"
-
-/**
- * @addtogroup EthDB
- *
- * @{
- */
-
-/**
- * @brief initializes a hash table object
- *
- * @param hashTable uninitialized hash table structure
- * @param numBuckets number of buckets to use
- * @param entryHashFunction hash function used 
- * to hash entire hash node data block (for adding)
- * @param matchFunctions array of match functions, indexed on type,
- * used to differentiate records with the same hash value
- * @param freeFunction function used to free node data blocks
- *
- * Initializes the given hash table object.
- *
- * @internal
- */
-void ixEthDBInitHash(HashTable *hashTable, 
-                     UINT32 numBuckets, 
-                     HashFunction entryHashFunction, 
-                     MatchFunction *matchFunctions, 
-                     FreeFunction freeFunction)
-{
-    UINT32 bucketIndex;
-    UINT32 hashSize = numBuckets * sizeof(HashNode *);
-
-    /* entry hashing, matching and freeing methods */
-    hashTable->entryHashFunction  = entryHashFunction;
-    hashTable->matchFunctions     = matchFunctions;
-    hashTable->freeFunction       = freeFunction;
-
-    /* buckets */
-    hashTable->numBuckets = numBuckets;
-
-    /* set to 0 all buckets */
-    memset(hashTable->hashBuckets, 0, hashSize);
-
-    /* init bucket locks - note that initially all mutexes are unlocked after MutexInit()*/
-    for (bucketIndex = 0 ; bucketIndex < numBuckets ; bucketIndex++)
-    {
-        ixOsalFastMutexInit(&hashTable->bucketLocks[bucketIndex]);
-    }
-}
-
-/**
- * @brief adds an entry to the hash table
- *
- * @param hashTable hash table to add the entry to
- * @param entry entry to add
- *
- * The entry will be hashed using the entry hashing function and added to the
- * hash table, unless a locking blockage occurs, in which case the caller
- * should retry.
- *
- * @retval IX_ETH_DB_SUCCESS if adding <i>entry</i> has succeeded
- * @retval IX_ETH_DB_NOMEM if there's no memory left in the hash node pool
- * @retval IX_ETH_DB_BUSY if there's a locking failure on the insertion path
- *
- * @internal
- */
-IX_ETH_DB_PUBLIC IxEthDBStatus ixEthDBAddHashEntry(HashTable *hashTable, void *entry)
-{
-    UINT32 hashValue   = hashTable->entryHashFunction(entry);
-    UINT32 bucketIndex = hashValue % hashTable->numBuckets;
-    HashNode *bucket   = hashTable->hashBuckets[bucketIndex];
-    HashNode *newNode;
-
-    LockStack locks;
-
-    INIT_STACK(&locks);
-
-    /* lock bucket */
-    PUSH_LOCK(&locks, &hashTable->bucketLocks[bucketIndex]);
-
-    /* lock insertion element (first in chain), if any */
-    if (bucket != NULL)
-    {
-        PUSH_LOCK(&locks, &bucket->lock);
-    }
-
-    /* get new node */
-    newNode = ixEthDBAllocHashNode();
-
-    if (newNode == NULL)
-    {
-        /* unlock everything */
-        UNROLL_STACK(&locks);
-
-        return IX_ETH_DB_NOMEM;
-    }
-
-    /* init lock - note that mutexes are unlocked after MutexInit */
-    ixOsalFastMutexInit(&newNode->lock);
-
-    /* populate new link */
-    newNode->data = entry;
-
-    /* add to bucket */
-    newNode->next                       = bucket;
-    hashTable->hashBuckets[bucketIndex] = newNode;
-
-    /* unlock bucket and insertion point */
-    UNROLL_STACK(&locks);
-
-    return IX_ETH_DB_SUCCESS;
-}
-
-/**
- * @brief removes an entry from the hashtable
- *
- * @param hashTable hash table to remove entry from
- * @param keyType type of record key used for matching
- * @param reference reference key used to identify the entry
- *
- * The reference key will be hashed using the key hashing function,
- * the entry is searched using the hashed value and then examined
- * against the reference entry using the match function. A positive
- * match will trigger the deletion of the entry.
- * Locking failures are reported and the caller should retry.
- *
- * @retval IX_ETH_DB_SUCCESS if the removal was successful
- * @retval IX_ETH_DB_NO_SUCH_ADDR if the entry was not found
- * @retval IX_ETH_DB_BUSY if a locking failure occured during the process
- *
- * @internal
- */
-IxEthDBStatus ixEthDBRemoveHashEntry(HashTable *hashTable, int keyType, void *reference)
-{
-    UINT32 hashValue       = hashTable->entryHashFunction(reference);
-    UINT32 bucketIndex     = hashValue % hashTable->numBuckets;
-    HashNode *node         = hashTable->hashBuckets[bucketIndex];
-    HashNode *previousNode = NULL;
-    
-    LockStack locks;
-
-    INIT_STACK(&locks);
-
-    while (node != NULL)
-    {
-        /* try to lock node */
-        PUSH_LOCK(&locks, &node->lock);
-
-        if (hashTable->matchFunctions[keyType](reference, node->data))
-        {
-            /* found entry */
-            if (node->next != NULL)
-            {
-                PUSH_LOCK(&locks, &node->next->lock);
-            }
-
-            if (previousNode == NULL)
-            {
-                /* node is head of chain */
-                PUSH_LOCK(&locks, &hashTable->bucketLocks[bucketIndex]);
-
-                hashTable->hashBuckets[bucketIndex] = node->next;
-
-                POP_LOCK(&locks);
-            }
-            else
-            {
-                /* relink */
-                previousNode->next = node->next;
-            }
-
-            UNROLL_STACK(&locks);
-
-            /* free node */
-            hashTable->freeFunction(node->data);
-            ixEthDBFreeHashNode(node);
-
-            return IX_ETH_DB_SUCCESS;
-        }
-        else
-        {
-            if (previousNode != NULL)
-            {
-                /* unlock previous node */
-                SHIFT_STACK(&locks);
-            }
-
-            /* advance to next element in chain */
-            previousNode = node;
-            node         = node->next;
-        }
-    }
-
-    UNROLL_STACK(&locks);
-
-    /* not found */
-    return IX_ETH_DB_NO_SUCH_ADDR;
-}
-
-/**
- * @brief retrieves an entry from the hash table
- *
- * @param hashTable hash table to perform the search into
- * @param reference search key (a MAC address)
- * @param keyType type of record key used for matching
- * @param searchResult pointer where a reference to the located hash node 
- * is placed
- *
- * Searches the entry with the same key as <i>reference</i> and places the
- * pointer to the resulting node in <i>searchResult</i>.
- * An implicit write access lock is granted after a search, which gives the 
- * caller the opportunity to modify the entry.
- * Access should be released as soon as possible using @ref ixEthDBReleaseHashNode().
- *
- * @see ixEthDBReleaseHashNode()
- *
- * @retval IX_ETH_DB_SUCCESS if the search was completed successfully
- * @retval IX_ETH_DB_NO_SUCH_ADDRESS if no entry with the given key was found
- * @retval IX_ETH_DB_BUSY if a locking failure has occured, in which case
- * the caller should retry
- *
- * @warning unless the return value is <b>IX_ETH_DB_SUCCESS</b> the searchResult
- * location is NOT modified and therefore using a NULL comparison test when the
- * value was not properly initialized would be an error
- *
- * @internal
- */
-IxEthDBStatus ixEthDBSearchHashEntry(HashTable *hashTable, int keyType, void *reference, HashNode **searchResult)
-{
-    UINT32 hashValue;
-    HashNode *node;
-
-    hashValue = hashTable->entryHashFunction(reference);
-    node      = hashTable->hashBuckets[hashValue % hashTable->numBuckets];
-
-    while (node != NULL)
-    {
-        TRY_LOCK(&node->lock);
-
-        if (hashTable->matchFunctions[keyType](reference, node->data))
-        {
-            *searchResult = node;
-
-            return IX_ETH_DB_SUCCESS;
-        }
-        else
-        {
-            UNLOCK(&node->lock);
-
-            node = node->next;
-        }
-    }
-
-    /* not found */
-    return IX_ETH_DB_NO_SUCH_ADDR;
-}
-
-/**
- * @brief reports the existence of an entry in the hash table
- *
- * @param hashTable hash table to perform the search into
- * @param reference search key (a MAC address)
- * @param keyType type of record key used for matching
- *
- * Searches the entry with the same key as <i>reference</i>.
- * No implicit write access lock is granted after a search, hence the 
- * caller cannot access or modify the entry. The result is only temporary.
- *
- * @see ixEthDBReleaseHashNode()
- *
- * @retval IX_ETH_DB_SUCCESS if the search was completed successfully
- * @retval IX_ETH_DB_NO_SUCH_ADDRESS if no entry with the given key was found
- * @retval IX_ETH_DB_BUSY if a locking failure has occured, in which case
- * the caller should retry
- *
- * @internal
- */
-IxEthDBStatus ixEthDBPeekHashEntry(HashTable *hashTable, int keyType, void *reference)
-{
-    UINT32 hashValue;
-    HashNode *node;
-
-    hashValue = hashTable->entryHashFunction(reference);
-    node      = hashTable->hashBuckets[hashValue % hashTable->numBuckets];
-
-    while (node != NULL)
-    {
-        TRY_LOCK(&node->lock);
-
-        if (hashTable->matchFunctions[keyType](reference, node->data))
-        {
-            UNLOCK(&node->lock);
-
-            return IX_ETH_DB_SUCCESS;
-        }
-        else
-        {
-            UNLOCK(&node->lock);
-
-            node = node->next;
-        }
-    }
-
-    /* not found */
-    return IX_ETH_DB_NO_SUCH_ADDR;
-}
-
-/**
- * @brief releases the write access lock
- *
- * @pre the node should have been obtained via @ref ixEthDBSearchHashEntry()
- *
- * @see ixEthDBSearchHashEntry()
- *
- * @internal
- */
-void ixEthDBReleaseHashNode(HashNode *node)
-{
-    UNLOCK(&node->lock);
-}
-
-/**
- * @brief initializes a hash iterator
- *
- * @param hashTable hash table to be iterated
- * @param iterator iterator object
- *
- * If the initialization is successful the iterator will point to the
- * first hash table record (if any).
- * Testing if the iterator has not passed the end of the table should be
- * done using the IS_ITERATOR_VALID(iteratorPtr) macro.
- * An implicit write access lock is granted on the entry pointed by the iterator.
- * The access is automatically revoked when the iterator is incremented.
- * If the caller decides to terminate the iteration before the end of the table is
- * passed then the manual access release method, @ref ixEthDBReleaseHashIterator,
- * must be called.
- *
- * @see ixEthDBReleaseHashIterator()
- *
- * @retval IX_ETH_DB_SUCCESS if initialization was successful and the iterator points
- * to the first valid table node
- * @retval IX_ETH_DB_FAIL if the table is empty
- * @retval IX_ETH_DB_BUSY if a locking failure has occured, in which case the caller
- * should retry
- *
- * @warning do not use ixEthDBReleaseHashNode() on entries pointed by the iterator, as this
- * might place the database in a permanent invalid lock state
- *
- * @internal
- */
-IxEthDBStatus ixEthDBInitHashIterator(HashTable *hashTable, HashIterator *iterator)
-{
-    iterator->bucketIndex  = 0;
-    iterator->node         = NULL;
-    iterator->previousNode = NULL;
-
-    return ixEthDBIncrementHashIterator(hashTable, iterator);
-}
-
-/**
- * @brief releases the write access locks of the iterator nodes
- *
- * @warning use of this function is required only when the caller terminates an iteration
- * before reaching the end of the table
- *
- * @see ixEthDBInitHashIterator()
- * @see ixEthDBIncrementHashIterator()
- *
- * @param iterator iterator whose node(s) should be unlocked
- *
- * @internal
- */
-void ixEthDBReleaseHashIterator(HashIterator *iterator)
-{
-    if (iterator->previousNode != NULL)
-    {
-        UNLOCK(&iterator->previousNode->lock);
-    }
-
-    if (iterator->node != NULL)
-    {
-        UNLOCK(&iterator->node->lock);
-    }
-}
-
-/**
- * @brief incremenents an iterator so that it points to the next valid entry of the table
- * (if any)
- *
- * @param hashTable hash table to iterate
- * @param iterator iterator object
- *
- * @pre the iterator object must be initialized using @ref ixEthDBInitHashIterator()
- *
- * If the increment operation is successful the iterator will point to the
- * next hash table record (if any).
- * Testing if the iterator has not passed the end of the table should be
- * done using the IS_ITERATOR_VALID(iteratorPtr) macro.
- * An implicit write access lock is granted on the entry pointed by the iterator.
- * The access is automatically revoked when the iterator is re-incremented.
- * If the caller decides to terminate the iteration before the end of the table is
- * passed then the manual access release method, @ref ixEthDBReleaseHashIterator,
- * must be called.
- * Is is guaranteed that no other thread can remove or change the iterated entry until
- * the iterator is incremented successfully.
- *
- * @see ixEthDBReleaseHashIterator()
- *
- * @retval IX_ETH_DB_SUCCESS if the operation was successful and the iterator points
- * to the next valid table node
- * @retval IX_ETH_DB_FAIL if the iterator has passed the end of the table
- * @retval IX_ETH_DB_BUSY if a locking failure has occured, in which case the caller
- * should retry
- *
- * @warning do not use ixEthDBReleaseHashNode() on entries pointed by the iterator, as this
- * might place the database in a permanent invalid lock state
- *
- * @internal
- */
-IxEthDBStatus ixEthDBIncrementHashIterator(HashTable *hashTable, HashIterator *iterator)
-{
-    /* unless iterator is just initialized... */
-    if (iterator->node != NULL)
-    {
-        /* try next in chain */
-        if (iterator->node->next != NULL)
-        {
-            TRY_LOCK(&iterator->node->next->lock);
-
-            if (iterator->previousNode != NULL)
-            {
-                UNLOCK(&iterator->previousNode->lock);
-            }
-
-            iterator->previousNode = iterator->node;
-            iterator->node         = iterator->node->next;
-
-            return IX_ETH_DB_SUCCESS;
-        }
-        else
-        {
-            /* last in chain, prepare for next bucket */
-            iterator->bucketIndex++;
-        }
-    }
-
-   /* try next used bucket */
-    for (; iterator->bucketIndex < hashTable->numBuckets ; iterator->bucketIndex++)
-    {
-        HashNode **nodePtr = &(hashTable->hashBuckets[iterator->bucketIndex]);
-        HashNode *node = *nodePtr;
-#if (CPU!=SIMSPARCSOLARIS) && !defined (__wince)
-        if (((iterator->bucketIndex & IX_ETHDB_BUCKET_INDEX_MASK) == 0) &&
-            (iterator->bucketIndex < (hashTable->numBuckets - IX_ETHDB_BUCKETPTR_AHEAD)))
-        {
-            /* preload next cache line (2 cache line ahead) */
-            nodePtr += IX_ETHDB_BUCKETPTR_AHEAD;
-            __asm__ ("pld [%0];\n": : "r" (nodePtr));
-        }
-#endif
-        if (node != NULL)
-        {
-            TRY_LOCK(&node->lock);
-
-            /* unlock last one or two nodes in the previous chain */
-            if (iterator->node != NULL)
-            {
-                UNLOCK(&iterator->node->lock);
-
-                if (iterator->previousNode != NULL)
-                {
-                    UNLOCK(&iterator->previousNode->lock);
-                }
-            }
-            
-            /* redirect iterator */
-            iterator->previousNode = NULL;
-            iterator->node         = node;
-
-            return IX_ETH_DB_SUCCESS;
-        }
-    }
-
-    /* could not advance iterator */
-    if (iterator->node != NULL)
-    {
-        UNLOCK(&iterator->node->lock);
-
-        if (iterator->previousNode != NULL)
-        {
-            UNLOCK(&iterator->previousNode->lock);
-        }
-
-        iterator->node = NULL;
-    }
-
-    return IX_ETH_DB_END;
-}
-
-/**
- * @brief removes an entry pointed by an iterator
- *
- * @param hashTable iterated hash table
- * @param iterator iterator object
- *
- * Removes the entry currently pointed by the iterator and repositions the iterator
- * on the next valid entry (if any). Handles locking issues automatically and
- * implicitely grants write access lock to the new pointed entry.
- * Failures due to concurrent threads having write access locks in the same region
- * preserve the state of the database and the iterator object, leaving the caller
- * free to retry without loss of access. It is guaranteed that only the thread owning
- * the iterator can remove the object pointed by the iterator.
- *
- * @retval IX_ETH_DB_SUCCESS if removal has succeeded
- * @retval IX_ETH_DB_BUSY if a locking failure has occured, in which case the caller
- * should retry
- *
- * @internal
- */
-IxEthDBStatus ixEthDBRemoveEntryAtHashIterator(HashTable *hashTable, HashIterator *iterator)
-{
-    HashIterator nextIteratorPos;
-    LockStack locks;
-
-    INIT_STACK(&locks);
-
-    /* set initial bucket index for next position */
-    nextIteratorPos.bucketIndex = iterator->bucketIndex;
-
-    /* compute iterator position before removing anything and lock ahead */
-    if (iterator->node->next != NULL)
-    {
-        PUSH_LOCK(&locks, &iterator->node->next->lock);
-
-        /* reposition on the next node in the chain */
-        nextIteratorPos.node         = iterator->node->next;
-        nextIteratorPos.previousNode = iterator->previousNode;
-    }
-    else
-    {
-        /* try next chain - don't know yet if we'll find anything */
-        nextIteratorPos.node = NULL;
-
-        /* if we find something it's a chain head */
-        nextIteratorPos.previousNode = NULL;
-
-        /* browse up in the buckets to find a non-null chain */
-        while (++nextIteratorPos.bucketIndex < hashTable->numBuckets)
-        {
-            nextIteratorPos.node = hashTable->hashBuckets[nextIteratorPos.bucketIndex];
-
-            if (nextIteratorPos.node != NULL)
-            {
-                /* found a non-empty chain, try to lock head */
-                PUSH_LOCK(&locks, &nextIteratorPos.node->lock);
-
-                break;
-            }
-        }
-    }
-
-    /* restore links over the to-be-deleted item */
-    if (iterator->previousNode == NULL)
-    {
-        /* first in chain, lock bucket */
-        PUSH_LOCK(&locks, &hashTable->bucketLocks[iterator->bucketIndex]);
-
-        hashTable->hashBuckets[iterator->bucketIndex] = iterator->node->next;
-
-        POP_LOCK(&locks);
-    }
-    else
-    {
-        /* relink */
-        iterator->previousNode->next = iterator->node->next;
-
-        /* unlock last remaining node in current chain when moving between chains */
-        if (iterator->node->next == NULL)
-        {
-            UNLOCK(&iterator->previousNode->lock);
-        }
-    }
-
-    /* delete entry */
-    hashTable->freeFunction(iterator->node->data);
-    ixEthDBFreeHashNode(iterator->node);
-
-    /* reposition iterator */
-    *iterator = nextIteratorPos;
-
-    return IX_ETH_DB_SUCCESS;
-}
-
-/**
- * @}
- */
diff --git a/drivers/net/npe/IxEthDBLearning.c b/drivers/net/npe/IxEthDBLearning.c
deleted file mode 100644
index 1080d112de..0000000000
--- a/drivers/net/npe/IxEthDBLearning.c
+++ /dev/null
@@ -1,125 +0,0 @@
-/**
- * @file IxEthDBLearning.c
- * 
- * @par
- * IXP400 SW Release version 2.0
- * 
- * -- Copyright Notice --
- * 
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- * 
- * @par
- * SPDX-License-Identifier:	BSD-3-Clause
- * @par
- * -- End of Copyright Notice --
- */
-
-#include "IxEthDB_p.h"
-
-/**
- * @brief hashes the mac address in a mac descriptor with a XOR function
- *
- * @param entry pointer to a mac descriptor to be hashed
- * 
- * This function only extracts the mac address and employs ixEthDBKeyXORHash()
- * to do the actual hashing.
- * Used only to add a whole entry to a hash table, as opposed to searching which
- * takes only a key and uses the key hashing directly.
- *
- * @see ixEthDBKeyXORHash()
- *
- * @return the hash value
- *
- * @internal
- */
-UINT32 ixEthDBEntryXORHash(void *entry)
-{
-    MacDescriptor *descriptor = (MacDescriptor *) entry;
-
-    return ixEthDBKeyXORHash(descriptor->macAddress);
-}
-
-/**
- * @brief hashes a mac address
- *
- * @param key pointer to a 6 byte structure (typically an IxEthDBMacAddr pointer)
- * to be hashed
- *
- * Given a 6 bytes MAC address, the hash used is:
- *
- * hash(MAC[0:5]) = MAC[0:1] ^ MAC[2:3] ^ MAC[4:5]
- *
- * Used by the hash table to search and remove entries based
- * solely on their keys (mac addresses).
- *
- * @return the hash value
- *
- * @internal
- */
-UINT32 ixEthDBKeyXORHash(void *key)
-{
-    UINT32 hashValue;
-    UINT8 *value = (UINT8 *) key;
-    
-    hashValue  = (value[5] << 8) | value[4];
-    hashValue ^= (value[3] << 8) | value[2];
-    hashValue ^= (value[1] << 8) | value[0];
-
-    return hashValue;
-}
-
-/**
- * @brief mac descriptor match function
- *
- * @param reference mac address (typically an IxEthDBMacAddr pointer) structure
- * @param entry pointer to a mac descriptor whose key (mac address) is to be 
- * matched against the reference key
- *
- * Used by the hash table to retrieve entries. Hashing entries can produce
- * collisions, i.e. descriptors with different mac addresses and the same
- * hash value, where this function is used to differentiate entries.
- *
- * @retval true if the entry matches the reference key (equal addresses)
- * @retval false if the entry does not match the reference key
- *
- * @internal
- */
-BOOL ixEthDBAddressMatch(void *reference, void *entry)
-{
-    return (ixEthDBAddressCompare(reference, ((MacDescriptor *) entry)->macAddress) == 0);
-}
-
-/**
- * @brief compares two mac addresses
- *
- * @param mac1 first mac address to compare
- * @param mac2 second mac address to compare
- * 
- * This comparison works in a similar way to strcmp, producing similar results.
- * Used to insert values keyed on mac addresses into binary search trees.
- *
- * @retval -1 if mac1 < mac2
- * @retval 0 if ma1 == mac2
- * @retval 1 if mac1 > mac2
- */
-UINT32 ixEthDBAddressCompare(UINT8 *mac1, UINT8 *mac2)
-{
-    UINT32 local_index;
-
-    for (local_index = 0 ; local_index < IX_IEEE803_MAC_ADDRESS_SIZE ; local_index++)
-    {
-        if (mac1[local_index] > mac2[local_index])
-        {
-            return 1;
-        }
-        else if (mac1[local_index] < mac2[local_index])
-        {
-            return -1;
-        }
-    }
-
-    return 0;
-}
-
diff --git a/drivers/net/npe/IxEthDBMem.c b/drivers/net/npe/IxEthDBMem.c
deleted file mode 100644
index 78fce4bd92..0000000000
--- a/drivers/net/npe/IxEthDBMem.c
+++ /dev/null
@@ -1,625 +0,0 @@
-/**
- * @file IxEthDBDBMem.c
- *
- * @brief Memory handling routines for the MAC address database
- * 
- * @par
- * IXP400 SW Release version 2.0
- * 
- * -- Copyright Notice --
- * 
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- * 
- * @par
- * SPDX-License-Identifier:	BSD-3-Clause
- * @par
- * -- End of Copyright Notice --
- */
-
-
-#include "IxEthDB_p.h"
-
-IX_ETH_DB_PRIVATE HashNode *nodePool     = NULL;
-IX_ETH_DB_PRIVATE MacDescriptor *macPool = NULL;
-IX_ETH_DB_PRIVATE MacTreeNode *treePool  = NULL;
-
-IX_ETH_DB_PRIVATE HashNode nodePoolArea[NODE_POOL_SIZE];
-IX_ETH_DB_PRIVATE MacDescriptor macPoolArea[MAC_POOL_SIZE];
-IX_ETH_DB_PRIVATE MacTreeNode treePoolArea[TREE_POOL_SIZE];
-
-IX_ETH_DB_PRIVATE IxOsalMutex nodePoolLock;
-IX_ETH_DB_PRIVATE IxOsalMutex macPoolLock;
-IX_ETH_DB_PRIVATE IxOsalMutex treePoolLock;
-
-#define LOCK_NODE_POOL   { ixOsalMutexLock(&nodePoolLock, IX_OSAL_WAIT_FOREVER); }
-#define UNLOCK_NODE_POOL { ixOsalMutexUnlock(&nodePoolLock); }
-
-#define LOCK_MAC_POOL    { ixOsalMutexLock(&macPoolLock, IX_OSAL_WAIT_FOREVER); }
-#define UNLOCK_MAC_POOL  { ixOsalMutexUnlock(&macPoolLock); }
-
-#define LOCK_TREE_POOL   { ixOsalMutexLock(&treePoolLock, IX_OSAL_WAIT_FOREVER); }
-#define UNLOCK_TREE_POOL { ixOsalMutexUnlock(&treePoolLock); }
-
-/* private function prototypes */
-IX_ETH_DB_PRIVATE MacDescriptor* ixEthDBPoolAllocMacDescriptor(void);
-IX_ETH_DB_PRIVATE void ixEthDBPoolFreeMacDescriptor(MacDescriptor *macDescriptor);
-
-/**
- * @addtogroup EthMemoryManagement
- *
- * @{
- */
-
-/**
- * @brief initializes the memory pools used by the ethernet database component
- *
- * Initializes the hash table node, mac descriptor and mac tree node pools.
- * Called at initialization time by @ref ixEthDBInit().
- *
- * @internal
- */
-IX_ETH_DB_PUBLIC
-void ixEthDBInitMemoryPools(void)
-{
-    int local_index;
-
-    /* HashNode pool */
-    ixOsalMutexInit(&nodePoolLock);
-
-    for (local_index = 0 ; local_index < NODE_POOL_SIZE ; local_index++)
-    {
-        HashNode *freeNode = &nodePoolArea[local_index];
-
-        freeNode->nextFree = nodePool;
-        nodePool           = freeNode;
-    }
-
-    /* MacDescriptor pool */
-    ixOsalMutexInit(&macPoolLock);
-
-    for (local_index = 0 ; local_index < MAC_POOL_SIZE ; local_index++)
-    {
-        MacDescriptor *freeDescriptor = &macPoolArea[local_index];
-
-        freeDescriptor->nextFree = macPool;
-        macPool                  = freeDescriptor;
-    }
-
-    /* MacTreeNode pool */
-    ixOsalMutexInit(&treePoolLock);
-
-    for (local_index = 0 ; local_index < TREE_POOL_SIZE ; local_index++)
-    {
-        MacTreeNode *freeNode = &treePoolArea[local_index];
-
-        freeNode->nextFree = treePool;
-        treePool           = freeNode;
-    }
-}
-
-/**
- * @brief allocates a hash node from the pool
- *
- * Allocates a hash node and resets its value.
- *
- * @return the allocated hash node or NULL if the pool is empty
- *
- * @internal
- */
-IX_ETH_DB_PUBLIC
-HashNode* ixEthDBAllocHashNode(void)
-{
-    HashNode *allocatedNode = NULL;
-
-    if (nodePool != NULL)
-    {
-        LOCK_NODE_POOL;
-
-        allocatedNode = nodePool;
-        nodePool      = nodePool->nextFree;
-
-        UNLOCK_NODE_POOL;
-
-        memset(allocatedNode, 0, sizeof(HashNode));
-    }
-
-    return allocatedNode;
-}
-
-/**
- * @brief frees a hash node into the pool
- *
- * @param hashNode node to be freed
- *
- * @internal
- */
-IX_ETH_DB_PUBLIC
-void ixEthDBFreeHashNode(HashNode *hashNode)
-{
-    if (hashNode != NULL)
-    {
-        LOCK_NODE_POOL;
-
-        hashNode->nextFree = nodePool;
-        nodePool           = hashNode;
-
-        UNLOCK_NODE_POOL;
-    }
-}
-
-/**
- * @brief allocates a mac descriptor from the pool
- *
- * Allocates a mac descriptor and resets its value.
- * This function is not used directly, instead @ref ixEthDBAllocMacDescriptor()
- * is used, which keeps track of the pointer reference count.
- *
- * @see ixEthDBAllocMacDescriptor()
- * 
- * @warning this function is not used directly by any other function
- * apart from ixEthDBAllocMacDescriptor()
- *
- * @return the allocated mac descriptor or NULL if the pool is empty
- *
- * @internal
- */
-IX_ETH_DB_PRIVATE
-MacDescriptor* ixEthDBPoolAllocMacDescriptor(void)
-{
-    MacDescriptor *allocatedDescriptor = NULL;
-
-    if (macPool != NULL)
-    {
-        LOCK_MAC_POOL;
-
-        allocatedDescriptor = macPool;
-        macPool             = macPool->nextFree;
-
-        UNLOCK_MAC_POOL;
-
-        memset(allocatedDescriptor, 0, sizeof(MacDescriptor));
-    }
-
-    return allocatedDescriptor;
-}
-
-/**
- * @brief allocates and initializes a mac descriptor smart pointer
- *
- * Uses @ref ixEthDBPoolAllocMacDescriptor() to allocate a mac descriptor
- * from the pool and initializes its reference count.
- *
- * @see ixEthDBPoolAllocMacDescriptor()
- *
- * @return the allocated mac descriptor or NULL if the pool is empty
- *
- * @internal
- */
-IX_ETH_DB_PUBLIC
-MacDescriptor* ixEthDBAllocMacDescriptor(void)
-{
-    MacDescriptor *allocatedDescriptor = ixEthDBPoolAllocMacDescriptor();
-
-    if (allocatedDescriptor != NULL)
-    {
-        LOCK_MAC_POOL;
-
-        allocatedDescriptor->refCount++;
-
-        UNLOCK_MAC_POOL;
-    }
-
-    return allocatedDescriptor;
-}
-
-/**
- * @brief frees a mac descriptor back into the pool
- *
- * @param macDescriptor mac descriptor to be freed
- *
- * @warning this function is not to be called by anyone but
- * ixEthDBFreeMacDescriptor()
- *
- * @see ixEthDBFreeMacDescriptor()
- *
- * @internal
- */
-IX_ETH_DB_PRIVATE
-void ixEthDBPoolFreeMacDescriptor(MacDescriptor *macDescriptor)
-{
-    LOCK_MAC_POOL;
-
-    macDescriptor->nextFree = macPool;
-    macPool                 = macDescriptor;
-
-    UNLOCK_MAC_POOL;
-}
-
-/**
- * @brief frees or reduces the usage count of a mac descriptor smart pointer
- *
- * If the reference count reaches 0 (structure is no longer used anywhere)
- * then the descriptor is freed back into the pool using ixEthDBPoolFreeMacDescriptor().
- *
- * @see ixEthDBPoolFreeMacDescriptor()
- *
- * @internal
- */
-IX_ETH_DB_PUBLIC
-void ixEthDBFreeMacDescriptor(MacDescriptor *macDescriptor)
-{
-    if (macDescriptor != NULL)
-    {
-        LOCK_MAC_POOL;
-
-        if (macDescriptor->refCount > 0)
-        {
-            macDescriptor->refCount--;
-
-            if (macDescriptor->refCount == 0)
-            {
-                UNLOCK_MAC_POOL;
-
-                ixEthDBPoolFreeMacDescriptor(macDescriptor);
-            }
-            else
-            {
-                UNLOCK_MAC_POOL;
-            }
-        }
-        else
-        {
-            UNLOCK_MAC_POOL;
-        }
-    }
-}
-
-/**
- * @brief clones a mac descriptor smart pointer
- *
- * @param macDescriptor mac descriptor to clone
- *
- * Increments the usage count of the smart pointer
- *
- * @returns the cloned smart pointer
- *
- * @internal
- */
-IX_ETH_DB_PUBLIC
-MacDescriptor* ixEthDBCloneMacDescriptor(MacDescriptor *macDescriptor)
-{
-    LOCK_MAC_POOL;
-
-    if (macDescriptor->refCount == 0)
-    {
-        UNLOCK_MAC_POOL;
-
-        return NULL;
-    }
-
-    macDescriptor->refCount++;
-
-    UNLOCK_MAC_POOL;
-
-    return macDescriptor;
-}
-
-/**
- * @brief allocates a mac tree node from the pool
- *
- * Allocates and initializes a mac tree node from the pool.
- *
- * @return the allocated mac tree node or NULL if the pool is empty
- *
- * @internal
- */
-IX_ETH_DB_PUBLIC
-MacTreeNode* ixEthDBAllocMacTreeNode(void)
-{
-    MacTreeNode *allocatedNode = NULL;
-
-    if (treePool != NULL)
-    {
-        LOCK_TREE_POOL;
-
-        allocatedNode = treePool;
-        treePool      = treePool->nextFree;
-
-        UNLOCK_TREE_POOL;
-
-        memset(allocatedNode, 0, sizeof(MacTreeNode));
-    }
-
-    return allocatedNode;
-}
-
-/**
- * @brief frees a mac tree node back into the pool
- *
- * @param macNode mac tree node to be freed
- *
- * @warning not to be used except from ixEthDBFreeMacTreeNode().
- *
- * @see ixEthDBFreeMacTreeNode()
- *
- * @internal
- */
-void ixEthDBPoolFreeMacTreeNode(MacTreeNode *macNode)
-{
-    if (macNode != NULL)
-    {
-        LOCK_TREE_POOL;
-
-        macNode->nextFree = treePool;
-        treePool          = macNode;
-
-        UNLOCK_TREE_POOL;
-    }
-}
-
-/**
- * @brief frees or reduces the usage count of a mac tree node smart pointer
- *
- * @param macNode mac tree node to free
- *
- * Reduces the usage count of the given mac node. If the usage count
- * reaches 0 the node is freed back into the pool using ixEthDBPoolFreeMacTreeNode()
- *
- * @internal
- */
-IX_ETH_DB_PUBLIC
-void ixEthDBFreeMacTreeNode(MacTreeNode *macNode)
-{
-    if (macNode->descriptor != NULL)
-    {
-        ixEthDBFreeMacDescriptor(macNode->descriptor);
-    }
-
-    if (macNode->left != NULL)
-    {
-        ixEthDBFreeMacTreeNode(macNode->left);
-    }
-
-    if (macNode->right != NULL)
-    {
-        ixEthDBFreeMacTreeNode(macNode->right);
-    }
-
-    ixEthDBPoolFreeMacTreeNode(macNode);
-}
-
-/**
- * @brief clones a mac tree node
- *
- * @param macNode mac tree node to be cloned
- *
- * Increments the usage count of the node, <i>its associated descriptor 
- * and <b>recursively</b> of all its child nodes</i>.
- *
- * @warning this function is recursive and clones whole trees/subtrees, use only for
- * root nodes
- *
- * @internal
- */
-IX_ETH_DB_PUBLIC
-MacTreeNode* ixEthDBCloneMacTreeNode(MacTreeNode *macNode)
-{
-    if (macNode != NULL)
-    {
-        MacTreeNode *clonedMacNode = ixEthDBAllocMacTreeNode();
-
-        if (clonedMacNode != NULL)
-        {
-            if (macNode->right != NULL)
-            {
-                clonedMacNode->right = ixEthDBCloneMacTreeNode(macNode->right);
-            }
-
-            if (macNode->left != NULL)
-            {
-                clonedMacNode->left = ixEthDBCloneMacTreeNode(macNode->left);
-            }
-
-            if (macNode->descriptor != NULL)
-            {
-                clonedMacNode->descriptor = ixEthDBCloneMacDescriptor(macNode->descriptor);
-            }
-        }
-
-        return clonedMacNode;
-    }
-    else
-    {
-        return NULL;
-    }
-}
-
-#ifndef NDEBUG
-/* Debug statistical functions for memory usage */
-
-extern HashTable dbHashtable;
-int ixEthDBNumHashElements(void);
-
-int ixEthDBNumHashElements(void)
-{   
-    UINT32 bucketIndex;
-    int numElements = 0;
-    HashTable *hashTable = &dbHashtable;
-
-    for (bucketIndex = 0 ; bucketIndex < hashTable->numBuckets ; bucketIndex++)
-    {
-        if (hashTable->hashBuckets[bucketIndex] != NULL)
-        {
-            HashNode *node = hashTable->hashBuckets[bucketIndex];
-
-            while (node != NULL)
-            {
-                numElements++;
-
-                node = node->next;
-            }
-        }
-    }
-
-    return numElements;
-}
-
-UINT32 ixEthDBSearchTreeUsageGet(MacTreeNode *tree)
-{
-    if (tree == NULL)
-    {
-        return 0;
-    }
-    else
-    {
-        return 1 /* this node */ + ixEthDBSearchTreeUsageGet(tree->left) + ixEthDBSearchTreeUsageGet(tree->right);
-    }
-}
-
-int ixEthDBShowMemoryStatus(void)
-{
-    MacDescriptor *mac;
-    MacTreeNode *tree;
-    HashNode *node;
-
-    int macCounter  = 0;
-    int treeCounter = 0;
-    int nodeCounter = 0;
-
-    int totalTreeUsage            = 0;
-    int totalDescriptorUsage      = 0;
-    int totalCloneDescriptorUsage = 0;
-    int totalNodeUsage            = 0;
-
-    UINT32 portIndex;
-
-    LOCK_NODE_POOL;
-    LOCK_MAC_POOL;
-    LOCK_TREE_POOL;
-
-    mac  = macPool;
-    tree = treePool;
-    node = nodePool;
-
-    while (mac != NULL)
-    {
-        macCounter++;
-
-        mac = mac->nextFree;
-
-        if (macCounter > MAC_POOL_SIZE)
-        {
-            break;
-        }
-    }
-
-    while (tree != NULL)
-    {
-        treeCounter++;
-
-        tree = tree->nextFree;
-
-        if (treeCounter > TREE_POOL_SIZE)
-        {
-            break;
-        }
-    }
-
-    while (node != NULL)
-    {
-        nodeCounter++;
-
-        node = node->nextFree;
-
-        if (nodeCounter > NODE_POOL_SIZE)
-        {
-            break;
-        }
-    }
-
-    for (portIndex = 0 ; portIndex < IX_ETH_DB_NUMBER_OF_PORTS ; portIndex++)
-    {
-        int treeUsage = ixEthDBSearchTreeUsageGet(ixEthDBPortInfo[portIndex].updateMethod.searchTree);
-
-        totalTreeUsage            += treeUsage;
-        totalCloneDescriptorUsage += treeUsage; /* each tree node contains a descriptor */
-    }
-
-    totalNodeUsage        = ixEthDBNumHashElements();
-    totalDescriptorUsage += totalNodeUsage; /* each hash table entry contains a descriptor */
-
-    UNLOCK_NODE_POOL;
-    UNLOCK_MAC_POOL;
-    UNLOCK_TREE_POOL;
-
-    printf("Ethernet database memory usage stats:\n\n");
-
-    if (macCounter <= MAC_POOL_SIZE)
-    {
-        printf("\tMAC descriptor pool  : %d free out of %d entries (%d%%)\n", macCounter, MAC_POOL_SIZE, macCounter * 100 / MAC_POOL_SIZE);
-    }
-    else
-    {
-        printf("\tMAC descriptor pool  : invalid state (ring within the pool), normally %d entries\n", MAC_POOL_SIZE);
-    }
-
-    if (treeCounter <= TREE_POOL_SIZE)
-    {
-	printf("\tTree node pool       : %d free out of %d entries (%d%%)\n", treeCounter, TREE_POOL_SIZE, treeCounter * 100 / TREE_POOL_SIZE);
-    }
-    else
-    {
-        printf("\tTREE descriptor pool  : invalid state (ring within the pool), normally %d entries\n", TREE_POOL_SIZE);
-    }
-
-    if (nodeCounter <= NODE_POOL_SIZE)
-    {
-	printf("\tHash node pool       : %d free out of %d entries (%d%%)\n", nodeCounter, NODE_POOL_SIZE, nodeCounter * 100 / NODE_POOL_SIZE);
-    }
-    else
-    {
-        printf("\tNODE descriptor pool  : invalid state (ring within the pool), normally %d entries\n", NODE_POOL_SIZE);
-    }
-
-    printf("\n");
-    printf("\tMAC descriptor usage : %d entries, %d cloned\n", totalDescriptorUsage, totalCloneDescriptorUsage);
-    printf("\tTree node usage      : %d entries\n", totalTreeUsage);
-    printf("\tHash node usage      : %d entries\n", totalNodeUsage);
-    printf("\n");
-
-    /* search for duplicate nodes in the mac pool */
-    {
-        MacDescriptor *reference = macPool;
-
-        while (reference != NULL)
-        {
-            MacDescriptor *comparison = reference->nextFree;
-
-            while (comparison != NULL)
-            {
-                if (reference == comparison)
-                {
-                    printf("Warning: reached a duplicate (%p), invalid MAC pool state\n", reference);
-
-                    return 1;
-                }
-
-                comparison = comparison->nextFree;
-            }
-
-            reference = reference->nextFree;
-        }
-    }
-
-    printf("No duplicates found in the MAC pool (sanity check ok)\n");
-
-    return 0;
-}
-
-#endif /* NDEBUG */
-
-/**
- * @} EthMemoryManagement
- */
diff --git a/drivers/net/npe/IxEthDBNPEAdaptor.c b/drivers/net/npe/IxEthDBNPEAdaptor.c
deleted file mode 100644
index 30e1f61ab9..0000000000
--- a/drivers/net/npe/IxEthDBNPEAdaptor.c
+++ /dev/null
@@ -1,695 +0,0 @@
-/**
- * @file IxEthDBDBNPEAdaptor.c
- *
- * @brief Routines that read and write learning/search trees in NPE-specific format
- * 
- * @par
- * IXP400 SW Release version 2.0
- * 
- * -- Copyright Notice --
- * 
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- * 
- * @par
- * SPDX-License-Identifier:	BSD-3-Clause
- * @par
- * -- End of Copyright Notice --
- */
-
-#include "IxEthDB_p.h"
-#include "IxEthDBLog_p.h"
-
-/* forward prototype declarations */
-IX_ETH_DB_PUBLIC void ixEthDBELTShow(IxEthDBPortId portID);
-IX_ETH_DB_PUBLIC void ixEthDBShowNpeMsgHistory(void);
-
-/* data */
-UINT8* ixEthDBNPEUpdateArea[IX_ETH_DB_NUMBER_OF_PORTS];
-UINT32 dumpEltSize;
-
-/* private data */
-IX_ETH_DB_PRIVATE IxEthDBNoteWriteFn ixEthDBNPENodeWrite[IX_ETH_DB_MAX_RECORD_TYPE_INDEX + 1];
-
-#define IX_ETH_DB_MAX_DELTA_ZONES (6) /* at most 6 EP Delta zones, according to NPE FS */
-IX_ETH_DB_PRIVATE UINT32 ixEthDBEPDeltaOffset[IX_ETH_DB_MAX_RECORD_TYPE_INDEX + 1][IX_ETH_DB_MAX_DELTA_ZONES]; 
-IX_ETH_DB_PRIVATE UINT32 ixEthDBEPDelta[IX_ETH_DB_MAX_RECORD_TYPE_INDEX + 1][IX_ETH_DB_MAX_DELTA_ZONES];
-
-/**
- * @brief allocates non-cached or contiguous NPE tree update areas for all the ports
- *
- * This function is called only once at initialization time from
- * @ref ixEthDBInit().
- *
- * @warning do not call manually
- *
- * @see ixEthDBInit()
- *
- * @internal
- */
-IX_ETH_DB_PUBLIC
-void ixEthDBNPEUpdateAreasInit(void)
-{
-    UINT32 portIndex;
-    PortUpdateMethod *update;
-
-    for (portIndex = 0 ; portIndex < IX_ETH_DB_NUMBER_OF_PORTS ; portIndex++)
-    {
-        update = &ixEthDBPortInfo[portIndex].updateMethod;
-
-        if (ixEthDBPortDefinitions[portIndex].type == IX_ETH_NPE)
-        {
-            update->npeUpdateZone   = IX_OSAL_CACHE_DMA_MALLOC(FULL_ELT_BYTE_SIZE);
-            update->npeGwUpdateZone = IX_OSAL_CACHE_DMA_MALLOC(FULL_GW_BYTE_SIZE);
-            update->vlanUpdateZone  = IX_OSAL_CACHE_DMA_MALLOC(FULL_VLAN_BYTE_SIZE);
-
-            if (update->npeUpdateZone == NULL
-                || update->npeGwUpdateZone == NULL
-                || update->vlanUpdateZone == NULL)
-            {
-                ERROR_LOG("Fatal error: IX_ACC_DRV_DMA_MALLOC() returned NULL, no NPE update zones available\n");
-            }
-            else
-            {
-                memset(update->npeUpdateZone, 0, FULL_ELT_BYTE_SIZE);
-                memset(update->npeGwUpdateZone, 0, FULL_GW_BYTE_SIZE);
-                memset(update->vlanUpdateZone, 0, FULL_VLAN_BYTE_SIZE);
-            }
-        }
-        else
-        {
-            /* unused */
-            update->npeUpdateZone   = NULL;
-            update->npeGwUpdateZone = NULL;
-            update->vlanUpdateZone  = NULL;
-        }
-    }
-}
-
-/**
- * @brief deallocates the NPE update areas for all the ports
- *
- * This function is called at component de-initialization time
- * by @ref ixEthDBUnload().
- *
- * @warning do not call manually
- *
- * @internal
- */
-IX_ETH_DB_PUBLIC
-void ixEthDBNPEUpdateAreasUnload(void)
-{
-    UINT32 portIndex;
-
-    for (portIndex = 0 ; portIndex < IX_ETH_DB_NUMBER_OF_PORTS ; portIndex++)
-    {
-        if (ixEthDBPortDefinitions[portIndex].type == IX_ETH_NPE)
-        {
-            IX_OSAL_CACHE_DMA_FREE(ixEthDBPortInfo[portIndex].updateMethod.npeUpdateZone);
-            IX_OSAL_CACHE_DMA_FREE(ixEthDBPortInfo[portIndex].updateMethod.npeGwUpdateZone);
-            IX_OSAL_CACHE_DMA_FREE(ixEthDBPortInfo[portIndex].updateMethod.vlanUpdateZone);
-        }
-    }
-}
-
-/**
- * @brief general-purpose NPE callback function
- *
- * @param npeID NPE ID
- * @param msg NPE message
- *
- * This function will unblock the caller by unlocking
- * the npeAckLock mutex defined for each NPE port
- *
- * @internal
- */
-IX_ETH_DB_PUBLIC
-void ixEthDBNpeMsgAck(IxNpeMhNpeId npeID, IxNpeMhMessage msg)
-{
-    IxEthDBPortId portID = IX_ETH_DB_NPE_TO_PORT_ID(npeID);
-    PortInfo *portInfo;
-
-    if (portID >= IX_ETH_DB_NUMBER_OF_PORTS)
-    {
-        /* invalid port */
-        return;
-    }
-
-    if (ixEthDBPortDefinitions[portID].type != IX_ETH_NPE)
-    {
-        /* not an NPE */
-        return;
-    }
-
-    portInfo = &ixEthDBPortInfo[portID];
-    
-    ixOsalMutexUnlock(&portInfo->npeAckLock);
-}
-
-/**
- * @brief synchronizes the database with tree
- *
- * @param portID port ID of the NPE whose tree is to be scanned
- * @param eltBaseAddress memory base address of the NPE serialized tree
- * @param eltSize size in bytes of the NPE serialized tree
- *
- * Scans the NPE learning tree and resets the age of active database records.
- *
- * @internal
- */
-IX_ETH_DB_PUBLIC
-void ixEthDBNPESyncScan(IxEthDBPortId portID, void *eltBaseAddress, UINT32 eltSize)
-{
-    UINT32 eltEntryOffset;
-    UINT32 entryPortID;
-
-    /* invalidate cache */
-    IX_OSAL_CACHE_INVALIDATE(eltBaseAddress, eltSize);
-
-    for (eltEntryOffset = ELT_ROOT_OFFSET ; eltEntryOffset < eltSize ; eltEntryOffset += ELT_ENTRY_SIZE)
-    {
-        /* (eltBaseAddress + eltEntryOffset) points to a valid NPE tree node
-         *
-         * the format of the node is MAC[6 bytes]:PortID[1 byte]:Reserved[6 bits]:Active[1 bit]:Valid[1 bit]
-         * therefore we can just use the pointer for database searches as only the first 6 bytes are checked
-         */
-        void *eltNodeAddress       = (void *) ((UINT32) eltBaseAddress + eltEntryOffset);
-
-        /* debug */
-        IX_ETH_DB_NPE_VERBOSE_TRACE("DB: (NPEAdaptor) checking node at offset %d...\n", eltEntryOffset / ELT_ENTRY_SIZE);
-
-        if (IX_EDB_NPE_NODE_VALID(eltNodeAddress) != true)
-        {
-            IX_ETH_DB_NPE_VERBOSE_TRACE("\t... node is empty\n");
-        }
-        else if (eltEntryOffset == ELT_ROOT_OFFSET)
-        {
-            IX_ETH_DB_NPE_VERBOSE_TRACE("\t... node is root\n");
-        }
-
-        if (IX_EDB_NPE_NODE_VALID(eltNodeAddress))
-        {
-            entryPortID = IX_ETH_DB_NPE_LOGICAL_ID_TO_PORT_ID(IX_EDB_NPE_NODE_PORT_ID(eltNodeAddress));
-
-            /* check only active entries belonging to this port */
-            if (ixEthDBPortInfo[portID].agingEnabled && IX_EDB_NPE_NODE_ACTIVE(eltNodeAddress) && (portID == entryPortID)
-                && ((ixEthDBPortDefinitions[portID].capabilities & IX_ETH_ENTRY_AGING) == 0))
-            {
-                /* search record */
-                HashNode *node = ixEthDBSearch((IxEthDBMacAddr *) eltNodeAddress, IX_ETH_DB_ALL_FILTERING_RECORDS);
-
-                /* safety check, maybe user deleted record right before sync? */
-                if (node != NULL)
-                {
-                    /* found record */
-                    MacDescriptor *descriptor = (MacDescriptor *) node->data;
-
-                    IX_ETH_DB_NPE_VERBOSE_TRACE("DB: (NPEAdaptor) synced entry [%s] already in the database, updating fields\n", mac2string(eltNodeAddress));
-
-                    /* reset age - set to -1 so that maintenance will restore it to 0 (or more) when incrementing */
-                    if (!descriptor->recordData.filteringData.staticEntry)
-                    {
-                        if (descriptor->type == IX_ETH_DB_FILTERING_RECORD)
-                        {
-                            descriptor->recordData.filteringData.age = AGE_RESET;
-                        }
-                        else if (descriptor->type == IX_ETH_DB_FILTERING_VLAN_RECORD)
-                        {
-                            descriptor->recordData.filteringVlanData.age = AGE_RESET;
-                        }
-                    }
-
-                    /* end transaction */
-                    ixEthDBReleaseHashNode(node);
-                }
-            }
-            else
-            {
-                IX_ETH_DB_NPE_VERBOSE_TRACE("\t... found portID %d, we check only port %d\n", entryPortID, portID);
-            }
-        }
-    }
-}
-
-/**
- * @brief writes a search tree in NPE format
- *
- * @param type type of records to be written into the NPE update zone
- * @param totalSize maximum size of the linearized tree
- * @param baseAddress memory base address where to write the NPE tree into
- * @param tree search tree to write in NPE format
- * @param blocks number of written 64-byte blocks
- * @param startIndex optimal binary search start index
- *
- * Serializes the given tree in NPE linear format
- *
- * @return none
- *
- * @internal
- */
-IX_ETH_DB_PUBLIC
-void ixEthDBNPETreeWrite(IxEthDBRecordType type, UINT32 totalSize, void *baseAddress, MacTreeNode *tree, UINT32 *epDelta, UINT32 *blocks)
-{
-    MacTreeNodeStack *stack;
-    UINT32 maxOffset = 0;
-    UINT32 emptyOffset;
-
-    stack = ixOsalCacheDmaMalloc(sizeof (MacTreeNodeStack));
-    
-    if (stack == NULL)
-    {
-        ERROR_LOG("DB: (NPEAdaptor) failed to allocate the node stack for learning tree linearization, out of memory?\n");
-        return;
-    }
-
-    /* zero out empty root */
-    memset(baseAddress, 0, ELT_ENTRY_SIZE);
-
-    NODE_STACK_INIT(stack);
-
-    if (tree != NULL)
-    {
-        /* push tree root at offset 1 */
-        NODE_STACK_PUSH(stack, tree, 1);
-
-        maxOffset = 1;
-    }
-
-    while (NODE_STACK_NONEMPTY(stack))
-    {
-        MacTreeNode *node;
-        UINT32 offset;
-
-        NODE_STACK_POP(stack, node, offset);
-
-        /* update maximum offset */
-        if (offset > maxOffset)
-        {
-            maxOffset = offset;
-        }
-
-        IX_ETH_DB_NPE_VERBOSE_TRACE("DB: (NPEAdaptor) writing MAC [%s] at offset %d\n", mac2string(node->descriptor->macAddress), offset);
-
-        /* add node to NPE ELT at position indicated by offset */
-        if (offset < MAX_ELT_SIZE)
-        {
-            ixEthDBNPENodeWrite[type]((void *) (((UINT32) baseAddress) + offset * ELT_ENTRY_SIZE), node);
-        }
-
-        if (node->left != NULL)
-        {
-            NODE_STACK_PUSH(stack, node->left, LEFT_CHILD_OFFSET(offset));
-        }
-        else
-        {
-            /* ensure this entry is zeroed */
-            memset((void *) ((UINT32) baseAddress + LEFT_CHILD_OFFSET(offset) * ELT_ENTRY_SIZE), 0, ELT_ENTRY_SIZE);
-        }
-
-        if (node->right != NULL)
-        {
-            NODE_STACK_PUSH(stack, node->right, RIGHT_CHILD_OFFSET(offset));
-        }
-        else
-        {
-            /* ensure this entry is zeroed */
-            memset((void *) ((UINT32) baseAddress + RIGHT_CHILD_OFFSET(offset) * ELT_ENTRY_SIZE), 0, ELT_ENTRY_SIZE);
-        }
-    }
-    
-    emptyOffset = maxOffset + 1;
-
-    /* zero out rest of the tree */
-    IX_ETH_DB_NPE_TRACE("DB: (NPEAdaptor) Emptying tree from offset %d, address 0x%08X, %d bytes\n", 
-        emptyOffset, ((UINT32) baseAddress) + emptyOffset * ELT_ENTRY_SIZE, totalSize - (emptyOffset * ELT_ENTRY_SIZE));
-
-    if (emptyOffset < MAX_ELT_SIZE - 1)
-    {
-        memset((void *) (((UINT32) baseAddress) + (emptyOffset * ELT_ENTRY_SIZE)), 0, totalSize - (emptyOffset * ELT_ENTRY_SIZE));
-    }
-
-    /* flush cache */
-    IX_OSAL_CACHE_FLUSH(baseAddress, totalSize);
-
-    /* debug */
-    IX_ETH_DB_NPE_TRACE("DB: (NPEAdaptor) Ethernet learning/filtering tree XScale wrote at address 0x%08X (max %d bytes):\n\n",
-        (UINT32) baseAddress, FULL_ELT_BYTE_SIZE);
-
-    IX_ETH_DB_NPE_DUMP_ELT(baseAddress, FULL_ELT_BYTE_SIZE);
-    
-    /* compute number of 64-byte blocks */
-    if (blocks != NULL)
-    {
-        *blocks = maxOffset != 0 ? 1 + maxOffset / 8 : 0;
-
-        IX_ETH_DB_NPE_TRACE("DB: (NPEAdaptor) Wrote %d 64-byte blocks\n", *blocks);
-    }
-    
-    /* compute epDelta - start index for binary search */
-    if (epDelta != NULL)
-    {
-        UINT32 deltaIndex = 0;
-
-        *epDelta = 0;
-        
-        for (; deltaIndex < IX_ETH_DB_MAX_DELTA_ZONES ; deltaIndex ++)
-        {
-            if (ixEthDBEPDeltaOffset[type][deltaIndex] >= maxOffset)
-            {
-                *epDelta = ixEthDBEPDelta[type][deltaIndex];
-                break;
-            }
-        }
-
-        IX_ETH_DB_NPE_TRACE("DB: (NPEAdaptor) Computed epDelta %d (based on maxOffset %d)\n", *epDelta, maxOffset);
-    }
-
-    ixOsalCacheDmaFree(stack);
-}
-
-/**
- * @brief implements a dummy node serialization function
- *
- * @param address address of where the node is to be serialized (unused)
- * @param node tree node to be serialized (unused)
- *
- * This function is registered for safety reasons and should
- * never be called. It will display an error message if this
- * function is called.
- *
- * @return none
- *
- * @internal
- */
-IX_ETH_DB_PRIVATE
-void ixEthDBNullSerialize(void *address, MacTreeNode *node)
-{
-    IX_ETH_DB_NPE_TRACE("DB: (NPEAdaptor) Warning, the NullSerialize function was called, wrong record type?\n");
-}
-
-/**
- * @brief writes a filtering entry in NPE linear format
- *
- * @param address memory address to write node to
- * @param node node to be written
- *
- * Used by @ref ixEthDBNPETreeWrite to liniarize a search tree
- * in NPE-readable format.
- *
- * @internal
- */
-IX_ETH_DB_PRIVATE
-void ixEthDBNPELearningNodeWrite(void *address, MacTreeNode *node)
-{
-    /* copy mac address */
-    memcpy(address, node->descriptor->macAddress, IX_IEEE803_MAC_ADDRESS_SIZE);
-
-    /* copy port ID */
-    NPE_NODE_BYTE(address, IX_EDB_NPE_NODE_ELT_PORT_ID_OFFSET) = IX_ETH_DB_PORT_ID_TO_NPE_LOGICAL_ID(node->descriptor->portID);
-
-    /* copy flags (valid and not active, as the NPE sets it to active) and clear reserved section (bits 2-7) */
-    NPE_NODE_BYTE(address, IX_EDB_NPE_NODE_ELT_FLAGS_OFFSET) = (UINT8) IX_EDB_FLAGS_INACTIVE_VALID;
-
-    IX_ETH_DB_NPE_VERBOSE_TRACE("DB: (NPEAdaptor) writing ELT node 0x%08x:0x%08x\n", * (UINT32 *) address, * (((UINT32 *) (address)) + 1));
-}
-
-/**
- * @brief writes a WiFi header conversion record in
- * NPE linear format
- *
- * @param address memory address to write node to
- * @param node node to be written
- *
- * Used by @ref ixEthDBNPETreeWrite to liniarize a search tree
- * in NPE-readable format.
- *
- * @internal
- */
-IX_ETH_DB_PRIVATE
-void ixEthDBNPEWiFiNodeWrite(void *address, MacTreeNode *node)
-{
-    /* copy mac address */
-    memcpy(address, node->descriptor->macAddress, IX_IEEE803_MAC_ADDRESS_SIZE);
-
-    /* copy index */
-    NPE_NODE_BYTE(address, IX_EDB_NPE_NODE_WIFI_INDEX_OFFSET) = node->descriptor->recordData.wifiData.gwAddressIndex;
-
-    /* copy flags (type and valid) */
-    NPE_NODE_BYTE(address, IX_EDB_NPE_NODE_WIFI_FLAGS_OFFSET) = node->descriptor->recordData.wifiData.type << 1 | IX_EDB_FLAGS_VALID;
-}
-
-/**
- * @brief writes a WiFi gateway header conversion record in
- * NPE linear format
- *
- * @param address memory address to write node to
- * @param node node to be written
- *
- * Used by @ref ixEthDBNPETreeWrite to liniarize a search tree
- * in NPE-readable format.
- *
- * @internal
- */
-IX_ETH_DB_PUBLIC
-void ixEthDBNPEGatewayNodeWrite(void *address, MacTreeNode *node)
-{
-    /* copy mac address */
-    memcpy(address, node->descriptor->recordData.wifiData.gwMacAddress, IX_IEEE803_MAC_ADDRESS_SIZE);
-
-    /* set reserved field, two bytes */
-    NPE_NODE_BYTE(address, IX_EDB_NPE_NODE_FW_RESERVED_OFFSET)     = 0;
-    NPE_NODE_BYTE(address, IX_EDB_NPE_NODE_FW_RESERVED_OFFSET + 1) = 0;
-}
-
-/**
- * @brief writes a firewall record in
- * NPE linear format
- *
- * @param address memory address to write node to
- * @param node node to be written
- *
- * Used by @ref ixEthDBNPETreeWrite to liniarize a search tree
- * in NPE-readable format.
- *
- * @internal
- */
-IX_ETH_DB_PRIVATE
-void ixEthDBNPEFirewallNodeWrite(void *address, MacTreeNode *node)
-{
-    /* set reserved field */
-    NPE_NODE_BYTE(address, IX_EDB_NPE_NODE_FW_RESERVED_OFFSET) = 0;
-
-    /* set flags */
-    NPE_NODE_BYTE(address, IX_EDB_NPE_NODE_FW_FLAGS_OFFSET) = IX_EDB_FLAGS_VALID;
-
-    /* copy mac address */
-    memcpy((void *) ((UINT32) address + IX_EDB_NPE_NODE_FW_ADDR_OFFSET), node->descriptor->macAddress, IX_IEEE803_MAC_ADDRESS_SIZE);
-}
-
-/**
- * @brief registers the NPE serialization methods
- *
- * This functions registers NPE serialization methods
- * for writing the following types of records in NPE
- * readable linear format:
- * - filtering records
- * - WiFi header conversion records
- * - WiFi gateway header conversion records
- * - firewall records
- *
- * Note that this function should be called by the
- * component initialization function.
- *
- * @return number of registered record types
- *
- * @internal
- */
-IX_ETH_DB_PUBLIC
-UINT32 ixEthDBRecordSerializeMethodsRegister()
-{
-    int i;
-    
-    /* safety - register a blank method for everybody first */
-    for ( i = 0 ; i < IX_ETH_DB_MAX_RECORD_TYPE_INDEX + 1 ; i++)
-    {
-        ixEthDBNPENodeWrite[i] = ixEthDBNullSerialize;
-    }
-    
-    /* register real methods */
-    ixEthDBNPENodeWrite[IX_ETH_DB_FILTERING_RECORD]      = ixEthDBNPELearningNodeWrite;
-    ixEthDBNPENodeWrite[IX_ETH_DB_FILTERING_VLAN_RECORD] = ixEthDBNPELearningNodeWrite;
-    ixEthDBNPENodeWrite[IX_ETH_DB_WIFI_RECORD]           = ixEthDBNPEWiFiNodeWrite;
-    ixEthDBNPENodeWrite[IX_ETH_DB_FIREWALL_RECORD]       = ixEthDBNPEFirewallNodeWrite;
-    ixEthDBNPENodeWrite[IX_ETH_DB_GATEWAY_RECORD]        = ixEthDBNPEGatewayNodeWrite;
-    
-    /* EP Delta arrays */
-    memset(ixEthDBEPDeltaOffset, 0, sizeof (ixEthDBEPDeltaOffset));
-    memset(ixEthDBEPDelta, 0, sizeof (ixEthDBEPDelta));
-    
-    /* filtering records */
-    ixEthDBEPDeltaOffset[IX_ETH_DB_FILTERING_RECORD][0] = 1;
-    ixEthDBEPDelta[IX_ETH_DB_FILTERING_RECORD][0]       = 0;
-    
-    ixEthDBEPDeltaOffset[IX_ETH_DB_FILTERING_RECORD][1] = 3;
-    ixEthDBEPDelta[IX_ETH_DB_FILTERING_RECORD][1]       = 7;
-    
-    ixEthDBEPDeltaOffset[IX_ETH_DB_FILTERING_RECORD][2] = 511;
-    ixEthDBEPDelta[IX_ETH_DB_FILTERING_RECORD][2]       = 14;
-    
-    /* wifi records */
-    ixEthDBEPDeltaOffset[IX_ETH_DB_WIFI_RECORD][0] = 1;
-    ixEthDBEPDelta[IX_ETH_DB_WIFI_RECORD][0]       = 0;
-    
-    ixEthDBEPDeltaOffset[IX_ETH_DB_WIFI_RECORD][1] = 3;
-    ixEthDBEPDelta[IX_ETH_DB_WIFI_RECORD][1]       = 7;
-    
-    ixEthDBEPDeltaOffset[IX_ETH_DB_WIFI_RECORD][2] = 511;
-    ixEthDBEPDelta[IX_ETH_DB_WIFI_RECORD][2]       = 14;
-
-    /* firewall records */
-    ixEthDBEPDeltaOffset[IX_ETH_DB_FIREWALL_RECORD][0] = 0;
-    ixEthDBEPDelta[IX_ETH_DB_FIREWALL_RECORD][0]       = 0;
-    
-    ixEthDBEPDeltaOffset[IX_ETH_DB_FIREWALL_RECORD][1] = 1;
-    ixEthDBEPDelta[IX_ETH_DB_FIREWALL_RECORD][1]       = 5;
-    
-    ixEthDBEPDeltaOffset[IX_ETH_DB_FIREWALL_RECORD][2] = 3;
-    ixEthDBEPDelta[IX_ETH_DB_FIREWALL_RECORD][2]       = 13;
-    
-    ixEthDBEPDeltaOffset[IX_ETH_DB_FIREWALL_RECORD][3] = 7;
-    ixEthDBEPDelta[IX_ETH_DB_FIREWALL_RECORD][3]       = 21;
-    
-    ixEthDBEPDeltaOffset[IX_ETH_DB_FIREWALL_RECORD][4] = 15;
-    ixEthDBEPDelta[IX_ETH_DB_FIREWALL_RECORD][4]       = 29;
-    
-    ixEthDBEPDeltaOffset[IX_ETH_DB_FIREWALL_RECORD][5] = 31;
-    ixEthDBEPDelta[IX_ETH_DB_FIREWALL_RECORD][5]       = 37;
-    
-    return 5; /* 5 methods registered */
-}
-
-#ifndef IX_NDEBUG
-
-IX_ETH_DB_PUBLIC UINT32 npeMsgHistory[IX_ETH_DB_NPE_MSG_HISTORY_DEPTH][2];
-IX_ETH_DB_PUBLIC UINT32 npeMsgHistoryLen = 0;
-
-/**
- * When compiled in DEBUG mode, this function can be used to display
- * the history of messages sent to the NPEs (up to 100).
- */
-IX_ETH_DB_PUBLIC
-void ixEthDBShowNpeMsgHistory()
-{
-    UINT32 i = 0;
-    UINT32 base, len;
-
-    if (npeMsgHistoryLen <= IX_ETH_DB_NPE_MSG_HISTORY_DEPTH)
-    {
-        base = 0;
-        len  = npeMsgHistoryLen;
-    }
-    else
-    {
-        base = npeMsgHistoryLen % IX_ETH_DB_NPE_MSG_HISTORY_DEPTH;
-        len  = IX_ETH_DB_NPE_MSG_HISTORY_DEPTH;
-    }
-
-    printf("NPE message history [last %d messages, from least to most recent]:\n", len);
-
-    for (; i < len ; i++)
-    {
-        UINT32 pos = (base + i) % IX_ETH_DB_NPE_MSG_HISTORY_DEPTH;
-        printf("msg[%d]: 0x%08x:0x%08x\n", i, npeMsgHistory[pos][0], npeMsgHistory[pos][1]);
-    }
-}
-
-IX_ETH_DB_PUBLIC
-void ixEthDBELTShow(IxEthDBPortId portID)
-{
-    IxNpeMhMessage message;
-    IX_STATUS result;
-    
-    /* send EDB_GetMACAddressDatabase message */
-    FILL_GETMACADDRESSDATABASE(message, 
-        0 /* reserved */, 
-        IX_OSAL_MMU_VIRT_TO_PHYS(ixEthDBPortInfo[portID].updateMethod.npeUpdateZone));
-
-    IX_ETHDB_SEND_NPE_MSG(IX_ETH_DB_PORT_ID_TO_NPE(portID), message, result);
-
-    if (result == IX_SUCCESS)
-    {
-        /* analyze NPE copy */
-        UINT32 eltEntryOffset;
-        UINT32 entryPortID;
-
-        UINT32 eltBaseAddress = (UINT32) ixEthDBPortInfo[portID].updateMethod.npeUpdateZone;
-        UINT32 eltSize        = FULL_ELT_BYTE_SIZE;
-
-        /* invalidate cache */
-        IX_OSAL_CACHE_INVALIDATE((void *) eltBaseAddress, eltSize);
-
-        printf("Listing records in main learning tree for port %d\n", portID);
-
-        for (eltEntryOffset = ELT_ROOT_OFFSET ; eltEntryOffset < eltSize ; eltEntryOffset += ELT_ENTRY_SIZE)
-        {
-            /* (eltBaseAddress + eltEntryOffset) points to a valid NPE tree node
-            *
-            * the format of the node is MAC[6 bytes]:PortID[1 byte]:Reserved[6 bits]:Active[1 bit]:Valid[1 bit]
-            * therefore we can just use the pointer for database searches as only the first 6 bytes are checked
-            */
-            void *eltNodeAddress = (void *) ((UINT32) eltBaseAddress + eltEntryOffset);
-
-            if (IX_EDB_NPE_NODE_VALID(eltNodeAddress))
-            {
-                HashNode *node;
-
-                entryPortID = IX_ETH_DB_NPE_LOGICAL_ID_TO_PORT_ID(IX_EDB_NPE_NODE_PORT_ID(eltNodeAddress));
-
-                /* search record */
-                node = ixEthDBSearch((IxEthDBMacAddr *) eltNodeAddress, IX_ETH_DB_ALL_RECORD_TYPES);
-
-                printf("%s - port %d - %s ", mac2string((unsigned char *) eltNodeAddress), entryPortID, 
-                    IX_EDB_NPE_NODE_ACTIVE(eltNodeAddress) ? "active" : "inactive");
-
-                /* safety check, maybe user deleted record right before sync? */
-                if (node != NULL)
-                {
-                    /* found record */
-                    MacDescriptor *descriptor = (MacDescriptor *) node->data;
-
-                    printf("- %s ",
-                        descriptor->type == IX_ETH_DB_FILTERING_RECORD ? "filtering" :
-                        descriptor->type == IX_ETH_DB_FILTERING_VLAN_RECORD ? "vlan" :
-                        descriptor->type == IX_ETH_DB_WIFI_RECORD ? "wifi" : "other (check main DB)");
-
-                    if (descriptor->type == IX_ETH_DB_FILTERING_RECORD) printf("- age %d - %s ", 
-                        descriptor->recordData.filteringData.age,
-                        descriptor->recordData.filteringData.staticEntry ? "static" : "dynamic");
-
-                    if (descriptor->type == IX_ETH_DB_FILTERING_VLAN_RECORD) printf("- age %d - %s - tci %d ",
-                        descriptor->recordData.filteringVlanData.age,
-                        descriptor->recordData.filteringVlanData.staticEntry ? "static" : "dynamic",
-                        descriptor->recordData.filteringVlanData.ieee802_1qTag);
-
-                    /* end transaction */
-                    ixEthDBReleaseHashNode(node);
-                }
-                else
-                {
-                    printf("- not synced");
-                }
-
-                printf("\n");
-            }
-        }
-    }
-    else
-    {
-        ixOsalLog(IX_OSAL_LOG_LVL_FATAL, IX_OSAL_LOG_DEV_STDOUT, 
-            "EthDB: (ShowELT) Could not complete action (communication failure)\n",
-            portID, 0, 0, 0, 0, 0);
-    }
-}
-
-#endif
diff --git a/drivers/net/npe/IxEthDBPortUpdate.c b/drivers/net/npe/IxEthDBPortUpdate.c
deleted file mode 100644
index 92af331a54..0000000000
--- a/drivers/net/npe/IxEthDBPortUpdate.c
+++ /dev/null
@@ -1,716 +0,0 @@
-/**
- * @file IxEthDBDBPortUpdate.c
- *
- * @brief Implementation of dependency and port update handling
- * 
- * @par
- * IXP400 SW Release version 2.0
- * 
- * -- Copyright Notice --
- * 
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- * 
- * @par
- * SPDX-License-Identifier:	BSD-3-Clause
- * @par
- * -- End of Copyright Notice --
- */
-
-#include "IxEthDB_p.h"
-
-/* forward prototype declarations */
-IX_ETH_DB_PRIVATE MacTreeNode* ixEthDBTreeInsert(MacTreeNode *searchTree, MacDescriptor *descriptor);
-IX_ETH_DB_PRIVATE void ixEthDBCreateTrees(IxEthDBPortMap updatePorts);
-IX_ETH_DB_PRIVATE MacTreeNode* ixEthDBTreeRebalance(MacTreeNode *searchTree);
-IX_ETH_DB_PRIVATE void ixEthDBRebalanceTreeToVine(MacTreeNode *root, UINT32 *size);
-IX_ETH_DB_PRIVATE void ixEthDBRebalanceVineToTree(MacTreeNode *root, UINT32 size);
-IX_ETH_DB_PRIVATE void ixEthDBRebalanceCompression(MacTreeNode *root, UINT32 count);
-IX_ETH_DB_PRIVATE UINT32 ixEthDBRebalanceLog2Floor(UINT32 x);
-
-extern HashTable dbHashtable;
-
-/**
- * @brief register types requiring automatic updates
- *
- * @param typeArray array indexed on record types, each
- * element indicating whether the record type requires an
- * automatic update (true) or not (false)
- * 
- * Automatic updates are done for registered record types
- * upon adding, updating (that is, updating the record portID) 
- * and removing records. Whenever an automatic update is triggered
- * the appropriate ports will be provided with new database
- * information.
- *
- * It is assumed that the typeArray parameter is allocated large
- * enough to hold all the user defined types. Also, the type
- * array should be initialized to false as this function only
- * caters for types which do require automatic updates.
- *
- * Note that this function should be called by the component
- * initialization function.
- *
- * @return number of record types registered for automatic
- * updates
- *
- * @internal
- */
-IX_ETH_DB_PUBLIC
-UINT32 ixEthDBUpdateTypeRegister(BOOL *typeArray)
-{
-    typeArray[IX_ETH_DB_FILTERING_RECORD]      = true;
-    typeArray[IX_ETH_DB_FILTERING_VLAN_RECORD] = true;
-
-    return 2;
-}
-
-/**
- * @brief computes dependencies and triggers port learning tree updates
- *
- * @param triggerPorts port map consisting in the ports which triggered the update
- *
- * This function browses through all the ports and determines how to waterfall the update
- * event from the trigger ports to all other ports depending on them.
- *
- * Once the list of ports to be updated is determined this function 
- * calls @ref ixEthDBCreateTrees.
- *
- * @internal
- */
-IX_ETH_DB_PUBLIC
-void ixEthDBUpdatePortLearningTrees(IxEthDBPortMap triggerPorts)
-{
-    IxEthDBPortMap updatePorts;
-    UINT32 portIndex;
-    
-    ixEthDBUpdateLock();
-    
-    SET_EMPTY_DEPENDENCY_MAP(updatePorts);
-    
-    for (portIndex = 0 ; portIndex < IX_ETH_DB_NUMBER_OF_PORTS ; portIndex++)
-    {
-        PortInfo *port   = &ixEthDBPortInfo[portIndex];
-        BOOL mapsCollide;
-        
-        MAPS_COLLIDE(mapsCollide, triggerPorts, port->dependencyPortMap);
-
-        if (mapsCollide                                   /* do triggers influence this port? */
-            && !IS_PORT_INCLUDED(portIndex, updatePorts)  /* and it's not already in the update list */
-            && port->updateMethod.updateEnabled)          /* and we're allowed to update it */
-        {
-            IX_ETH_DB_UPDATE_TRACE("DB: (Update) Adding port %d to update set\n", portIndex);
-
-            JOIN_PORT_TO_MAP(updatePorts, portIndex);
-        }
-        else
-        {
-            IX_ETH_DB_UPDATE_TRACE("DB: (Update) Didn't add port %d to update set, reasons follow:\n", portIndex);
-
-            if (!mapsCollide)
-            {
-                IX_ETH_DB_UPDATE_TRACE("\tMaps don't collide on port %d\n", portIndex);
-            }
-
-            if (IS_PORT_INCLUDED(portIndex, updatePorts))
-            {
-                IX_ETH_DB_UPDATE_TRACE("\tPort %d is already in the update set\n", portIndex);
-            }
-
-            if (!port->updateMethod.updateEnabled)
-            {
-                IX_ETH_DB_UPDATE_TRACE("\tPort %d doesn't have updateEnabled set\n", portIndex);
-            }
-        }
-    }
-    
-    IX_ETH_DB_UPDATE_TRACE("DB: (Update) Updating port set\n");
-
-    ixEthDBCreateTrees(updatePorts);
-        
-    ixEthDBUpdateUnlock();
-}
-
-/**
- * @brief creates learning trees and calls the port update handlers
- *
- * @param updatePorts set of ports in need of learning trees
- *
- * This function determines the optimal method of creating learning
- * trees using a minimal number of database queries, keeping in mind
- * that different ports can either use the same learning trees or they
- * can partially share them. The actual tree building routine is
- * @ref ixEthDBQuery.
- *
- * @internal
- */
-IX_ETH_DB_PRIVATE
-void ixEthDBCreateTrees(IxEthDBPortMap updatePorts)
-{
-    UINT32 portIndex;
-    BOOL result;
-    BOOL portsLeft = true;
-
-    while (portsLeft)
-    {
-        /* get port with minimal dependency map and NULL search tree */
-        UINT32 minPortIndex = MAX_PORT_SIZE;
-        UINT32 minimalSize  = MAX_PORT_SIZE;
-
-        for (portIndex = 0 ; portIndex < IX_ETH_DB_NUMBER_OF_PORTS ; portIndex++)
-        {
-            UINT32 size;
-            PortInfo *port = &ixEthDBPortInfo[portIndex];
-
-            /* generate trees only for ports that need them */
-            if (!port->updateMethod.searchTreePendingWrite && IS_PORT_INCLUDED(portIndex, updatePorts))
-            {
-                GET_MAP_SIZE(port->dependencyPortMap, size);
-                
-                IX_ETH_DB_UPDATE_TRACE("DB: (Update) Dependency map for port %d: size %d\n",
-                    portIndex, size);
-
-                if (size < minimalSize)
-                {
-                    minPortIndex = portIndex;
-                    minimalSize  = size;
-                }
-            }
-            else
-            {
-                IX_ETH_DB_UPDATE_TRACE("DB: (Update) Skipped port %d from tree diff (%s)\n", portIndex,
-                    port->updateMethod.searchTreePendingWrite ? "pending write access" : "ignored by query");
-            }            
-        }
-
-        /* if a port was found than minimalSize is not MAX_PORT_SIZE */
-        if (minimalSize != MAX_PORT_SIZE)
-        {
-            /* minPortIndex is the port we seek */
-            PortInfo *port = &ixEthDBPortInfo[minPortIndex];
-
-            IxEthDBPortMap query;
-            MacTreeNode *baseTree;
-
-            /* now try to find a port with minimal map difference */
-            PortInfo *minimalDiffPort = NULL;
-            UINT32 minimalDiff        = MAX_PORT_SIZE;
-            
-            IX_ETH_DB_UPDATE_TRACE("DB: (Update) Minimal size port is %d\n", minPortIndex);
-
-            for (portIndex = 0 ; portIndex < IX_ETH_DB_NUMBER_OF_PORTS ; portIndex++)
-            {   
-                PortInfo *diffPort = &ixEthDBPortInfo[portIndex];
-                BOOL mapIsSubset;
-                
-                IS_MAP_SUBSET(mapIsSubset, diffPort->dependencyPortMap, port->dependencyPortMap);
-                
-
-                if (portIndex != minPortIndex
-                    && diffPort->updateMethod.searchTree != NULL
-                    && mapIsSubset)
-                {
-                    /* compute size and pick only minimal size difference */
-                    UINT32 diffPortSize;
-                    UINT32 sizeDifference;
-
-                    GET_MAP_SIZE(diffPort->dependencyPortMap, diffPortSize);
-                     
-                    IX_ETH_DB_UPDATE_TRACE("DB: (Update) Checking port %d for differences...\n", portIndex);
-
-                    sizeDifference = minimalSize - diffPortSize;
-
-                    if (sizeDifference < minimalDiff)
-                    {
-                        minimalDiffPort = diffPort;
-                        minimalDiff     = sizeDifference;
-                        
-                        IX_ETH_DB_UPDATE_TRACE("DB: (Update) Minimal difference 0x%x was found on port %d\n",
-                            minimalDiff, portIndex);
-                    }
-                }
-            }
-
-            /* check if filtering is enabled on this port */
-            if ((port->featureStatus & IX_ETH_DB_FILTERING) != 0)
-            {
-                /* if minimalDiff is not MAX_PORT_SIZE minimalDiffPort points to the most similar port */
-                if (minimalDiff != MAX_PORT_SIZE)
-                {
-                    baseTree = ixEthDBCloneMacTreeNode(minimalDiffPort->updateMethod.searchTree);
-                    DIFF_MAPS(query, port->dependencyPortMap , minimalDiffPort->dependencyPortMap);
-                    
-                    IX_ETH_DB_UPDATE_TRACE("DB: (Update) Found minimal diff, extending tree %d on query\n",
-                        minimalDiffPort->portID);
-                }
-                else /* .. otherwise no similar port was found, build tree from scratch */
-                {
-                    baseTree = NULL;
-                    
-                    COPY_DEPENDENCY_MAP(query, port->dependencyPortMap);
-                    
-                    IX_ETH_DB_UPDATE_TRACE("DB: (Update) No similar diff, creating tree from query\n");
-                }
-
-                IS_EMPTY_DEPENDENCY_MAP(result, query);
-                
-                if (!result) /* otherwise we don't need anything more on top of the cloned tree */
-                {
-                    IX_ETH_DB_UPDATE_TRACE("DB: (Update) Adding query tree to port %d\n", minPortIndex);
-                        
-                    /* build learning tree */
-                    port->updateMethod.searchTree = ixEthDBQuery(baseTree, query, IX_ETH_DB_ALL_FILTERING_RECORDS, MAX_ELT_SIZE);
-                }
-                else
-                {
-                    IX_ETH_DB_UPDATE_TRACE("DB: (Update) Query is empty, assuming identical nearest tree\n");
-                      
-                    port->updateMethod.searchTree = baseTree;
-                }
-            }
-            else
-            {
-                /* filtering is not enabled, will download an empty tree */
-                if (port->updateMethod.searchTree != NULL)
-                {
-                    ixEthDBFreeMacTreeNode(port->updateMethod.searchTree);
-                }
-
-                port->updateMethod.searchTree = NULL;
-            }
-
-            /* mark tree as valid */
-            port->updateMethod.searchTreePendingWrite = true;
-        }
-        else
-        {
-            portsLeft = false;
-
-            IX_ETH_DB_UPDATE_TRACE("DB: (Update) No trees to create this round\n");            
-        }
-    }
-    
-    for (portIndex = 0 ; portIndex < IX_ETH_DB_NUMBER_OF_PORTS ; portIndex++)
-    {
-        PortInfo *updatePort = &ixEthDBPortInfo[portIndex];
-
-        if (updatePort->updateMethod.searchTreePendingWrite)
-        {
-            IX_ETH_DB_UPDATE_TRACE("DB: (PortUpdate) Starting procedure to upload new search tree (%snull) into NPE %d\n", 
-                updatePort->updateMethod.searchTree != NULL ? "not " : "",
-                portIndex);
-
-            updatePort->updateMethod.updateHandler(portIndex, IX_ETH_DB_FILTERING_RECORD);
-        }
-    }
-}
-
-/**
- * @brief standard NPE update handler
- *
- * @param portID id of the port to be updated
- * @param type record type to be pushed during this update
- *
- * The NPE update handler manages updating the NPE databases
- * given a certain record type.
- *
- * @internal
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBNPEUpdateHandler(IxEthDBPortId portID, IxEthDBRecordType type)
-{
-    UINT32 epDelta, blockCount;
-    IxNpeMhMessage message;
-    UINT32 treeSize = 0;
-    PortInfo *port = &ixEthDBPortInfo[portID];
-
-    /* size selection and type check */
-    if (type == IX_ETH_DB_FILTERING_RECORD || type == IX_ETH_DB_WIFI_RECORD)
-    {
-        treeSize = FULL_ELT_BYTE_SIZE;
-    }
-    else if (type == IX_ETH_DB_FIREWALL_RECORD)
-    {
-        treeSize = FULL_FW_BYTE_SIZE;
-    }
-    else
-    {
-        return IX_ETH_DB_INVALID_ARG;
-    }
-    
-    /* serialize tree into memory */
-    ixEthDBNPETreeWrite(type, treeSize, port->updateMethod.npeUpdateZone, port->updateMethod.searchTree, &epDelta, &blockCount);
-
-    /* free internal copy */
-    if (port->updateMethod.searchTree != NULL)
-    {
-        ixEthDBFreeMacTreeNode(port->updateMethod.searchTree);
-    }
-
-    /* forget last used search tree */
-    port->updateMethod.searchTree             = NULL;
-    port->updateMethod.searchTreePendingWrite = false;
-
-    /* dependending on the update type we do different things */
-    if (type == IX_ETH_DB_FILTERING_RECORD || type == IX_ETH_DB_WIFI_RECORD)
-    {
-        IX_STATUS result;
-
-        FILL_SETMACADDRESSDATABASE_MSG(message, IX_ETH_DB_PORT_ID_TO_NPE_LOGICAL_ID(portID), 
-            epDelta, blockCount, 
-            IX_OSAL_MMU_VIRT_TO_PHYS(port->updateMethod.npeUpdateZone));
-
-        IX_ETHDB_SEND_NPE_MSG(IX_ETH_DB_PORT_ID_TO_NPE(portID), message, result);
-
-        if (result == IX_SUCCESS)
-	{
-            IX_ETH_DB_UPDATE_TRACE("DB: (PortUpdate) Finished downloading NPE tree on port %d\n", portID);
-        }
-        else
-        {
-            ixEthDBPortInfo[portID].agingEnabled                = false;
-            ixEthDBPortInfo[portID].updateMethod.updateEnabled  = false;
-            ixEthDBPortInfo[portID].updateMethod.userControlled = true;
-
-            ERROR_LOG("EthDB: (PortUpdate) disabling aging and updates on port %d (assumed dead)\n", portID);
-
-            ixEthDBDatabaseClear(portID, IX_ETH_DB_ALL_RECORD_TYPES);
-
-            return IX_ETH_DB_FAIL;
-        }
-
-	return IX_ETH_DB_SUCCESS;
-    }
-    else if (type == IX_ETH_DB_FIREWALL_RECORD)
-    {
-        return ixEthDBFirewallUpdate(portID, port->updateMethod.npeUpdateZone, epDelta);
-    }
-    
-    return IX_ETH_DB_INVALID_ARG;
-}
-
-/**
- * @brief queries the database for a set of records to be inserted into a given tree
- *
- * @param searchTree pointer to a tree where insertions will be performed; can be NULL
- * @param query set of ports that a database record must match to be inserted into the tree
- *
- * The query method browses through the database, extracts all the descriptors matching
- * the given query parameter and inserts them into the given learning tree.
- * Note that this is an append procedure, the given tree needs not to be empty.
- * A "descriptor matching the query" is a descriptor whose port id is in the query map.
- * If the given tree is empty (NULL) a new tree is created and returned.
- * 
- * @return the tree root
- *
- * @internal
- */
-IX_ETH_DB_PUBLIC
-MacTreeNode* ixEthDBQuery(MacTreeNode *searchTree, IxEthDBPortMap query, IxEthDBRecordType recordFilter, UINT32 maxEntries)
-{
-    HashIterator iterator;
-    UINT32 entryCount = 0;
-
-    /* browse database */
-    BUSY_RETRY(ixEthDBInitHashIterator(&dbHashtable, &iterator));
-
-    while (IS_ITERATOR_VALID(&iterator))
-    {
-        MacDescriptor *descriptor = (MacDescriptor *) iterator.node->data;
-
-        IX_ETH_DB_UPDATE_TRACE("DB: (PortUpdate) querying [%s]:%d on port map ... ", 
-            mac2string(descriptor->macAddress), 
-            descriptor->portID);
-
-	if ((descriptor->type & recordFilter) != 0 
-            && IS_PORT_INCLUDED(descriptor->portID, query))
-	{
-            MacDescriptor *descriptorClone = ixEthDBCloneMacDescriptor(descriptor);
-
-            IX_ETH_DB_UPDATE_TRACE("match\n");
-
-            if (descriptorClone != NULL)
-            {
-                /* add descriptor to tree */
-                searchTree = ixEthDBTreeInsert(searchTree, descriptorClone);
-
-                entryCount++;
-            }
-        }
-        else
-        {
-            IX_ETH_DB_UPDATE_TRACE("no match\n");
-        }
-
-        if (entryCount < maxEntries)
-        {
-            /* advance to the next record */
-	        BUSY_RETRY(ixEthDBIncrementHashIterator(&dbHashtable, &iterator));
-        }
-        else
-        {
-            /* the NPE won't accept more entries so we can stop now */
-            ixEthDBReleaseHashIterator(&iterator);
-
-            IX_ETH_DB_UPDATE_TRACE("DB: (PortUpdate) number of elements reached maximum supported by port\n");
-
-            break;
-        }
-    }
-
-    IX_ETH_DB_UPDATE_TRACE("DB: (PortUpdate) query inserted %d records in the search tree\n", entryCount);
-
-    return ixEthDBTreeRebalance(searchTree);
-}
-
-/**
- * @brief inserts a mac descriptor into an tree
- *
- * @param searchTree tree where the insertion is to be performed (may be NULL)
- * @param descriptor descriptor to insert into tree
- *
- * @return the tree root
- *
- * @internal
- */
-IX_ETH_DB_PRIVATE
-MacTreeNode* ixEthDBTreeInsert(MacTreeNode *searchTree, MacDescriptor *descriptor)
-{
-    MacTreeNode *currentNode    = searchTree;
-    MacTreeNode *insertLocation = NULL;
-    MacTreeNode *newNode;
-    INT32 insertPosition = RIGHT;
-
-    if (descriptor == NULL)
-    {
-        return searchTree;
-    }
-
-    /* create a new node */
-    newNode = ixEthDBAllocMacTreeNode();
-
-    if (newNode == NULL)
-    {
-        /* out of memory */
-        ERROR_LOG("Warning: ixEthDBAllocMacTreeNode returned NULL in file %s:%d (out of memory?)\n", __FILE__, __LINE__);
-
-        ixEthDBFreeMacDescriptor(descriptor);
-
-        return NULL;
-    }
-
-    /* populate node */
-    newNode->descriptor = descriptor;
-
-    /* an empty initial tree is a special case */
-    if (searchTree == NULL)
-    {
-        return newNode;
-    }
-
-    /* get insertion location */
-    while (insertLocation == NULL)
-    {
-        MacTreeNode *nextNode;
-
-        /* compare given key with current node key */
-        insertPosition = ixEthDBAddressCompare(descriptor->macAddress, currentNode->descriptor->macAddress);
-
-        /* navigate down */
-        if (insertPosition == RIGHT)
-        {
-            nextNode = currentNode->right;
-        }
-        else if (insertPosition == LEFT)
-        {
-            nextNode = currentNode->left;
-        }
-        else
-        {
-            /* error, duplicate key */
-            ERROR_LOG("Warning: trapped insertion of a duplicate MAC address in an NPE search tree\n");
-
-            /* this will free the MAC descriptor as well */
-            ixEthDBFreeMacTreeNode(newNode);
-
-            return searchTree;
-        }
-
-        /* when we can no longer dive through the tree we found the insertion place */
-        if (nextNode != NULL)
-        {
-            currentNode = nextNode;
-        }
-        else
-        {
-            insertLocation = currentNode;
-        }
-    }
-
-    /* insert node */
-    if (insertPosition == RIGHT)
-    {
-        insertLocation->right = newNode;
-    }
-    else
-    {
-        insertLocation->left = newNode;
-    }
-
-    return searchTree;
-}
-
-/**
- * @brief balance a tree
- *
- * @param searchTree tree to balance
- *
- * Converts a tree into a balanced tree and returns the root of
- * the balanced tree. The resulting tree is <i>route balanced</i>
- * not <i>perfectly balanced</i>. This makes no difference to the
- * average tree search time which is the same in both cases, O(log2(n)).
- *
- * @return root of the balanced tree or NULL if there's no memory left
- *
- * @internal
- */
-IX_ETH_DB_PRIVATE
-MacTreeNode* ixEthDBTreeRebalance(MacTreeNode *searchTree)
-{
-    MacTreeNode *pseudoRoot = ixEthDBAllocMacTreeNode();
-    UINT32 size;
-
-    if (pseudoRoot == NULL)
-    {
-        /* out of memory */
-        return NULL;
-    }
-
-    pseudoRoot->right = searchTree;
-
-    ixEthDBRebalanceTreeToVine(pseudoRoot, &size);
-    ixEthDBRebalanceVineToTree(pseudoRoot, size);
-
-    searchTree = pseudoRoot->right;
-
-    /* remove pseudoRoot right branch, otherwise it will free the entire tree */
-    pseudoRoot->right = NULL;
-
-    ixEthDBFreeMacTreeNode(pseudoRoot);
-
-    return searchTree;
-}
-
-/**
- * @brief converts a tree into a vine
- *
- * @param root root of tree to convert
- * @param size depth of vine (equal to the number of nodes in the tree)
- *
- * @internal
- */
-IX_ETH_DB_PRIVATE
-void ixEthDBRebalanceTreeToVine(MacTreeNode *root, UINT32 *size)
-{
-    MacTreeNode *vineTail  = root;
-    MacTreeNode *remainder = vineTail->right;
-    MacTreeNode *tempPtr;
-
-    *size = 0;
-
-    while (remainder != NULL)
-    {
-        if (remainder->left == NULL)
-        {
-            /* move tail down one */
-            vineTail  = remainder;
-            remainder = remainder->right;
-            (*size)++;
-        }
-        else
-        {
-            /* rotate around remainder */
-            tempPtr         = remainder->left;
-            remainder->left = tempPtr->right;
-            tempPtr->right  = remainder;
-            remainder       = tempPtr;
-            vineTail->right = tempPtr;
-        }
-    }
-}
-
-/**
- * @brief converts a vine into a balanced tree
- *
- * @param root vine to convert
- * @param size depth of vine
- *
- * @internal
- */
-IX_ETH_DB_PRIVATE
-void ixEthDBRebalanceVineToTree(MacTreeNode *root, UINT32 size)
-{
-    UINT32 leafCount = size + 1 - (1 << ixEthDBRebalanceLog2Floor(size + 1));
-
-    ixEthDBRebalanceCompression(root, leafCount);
-
-    size = size - leafCount;
-
-    while (size > 1)
-    {
-        ixEthDBRebalanceCompression(root, size / 2);
-
-        size /= 2;
-    }
-}
-
-/**
- * @brief compresses a vine/tree stage into a more balanced vine/tree
- *
- * @param root root of the tree to compress
- * @param count number of "spine" nodes
- *
- * @internal
- */
-IX_ETH_DB_PRIVATE
-void ixEthDBRebalanceCompression(MacTreeNode *root, UINT32 count)
-{
-    MacTreeNode *scanner = root;
-    MacTreeNode *child;
-    UINT32 local_index;
-
-    for (local_index = 0 ; local_index < count ; local_index++)
-    {
-        child          = scanner->right;
-        scanner->right = child->right;
-        scanner        = scanner->right;
-        child->right   = scanner->left;
-        scanner->left  = child;
-    }
-}
-
-/**
- * @brief computes |_log2(x)_| (a.k.a. floor(log2(x)))
- *
- * @param x number to compute |_log2(x)_| for
- *
- * @return |_log2(x)_|
- *
- * @internal
- */
-IX_ETH_DB_PRIVATE
-UINT32 ixEthDBRebalanceLog2Floor(UINT32 x)
-{
-    UINT32 log = 0;
-    UINT32 val = 1;
-
-    while (val < x)
-    {
-        log++;
-        val <<= 1;
-    }
-
-    return val == x ? log : log - 1;
-}
-
diff --git a/drivers/net/npe/IxEthDBReports.c b/drivers/net/npe/IxEthDBReports.c
deleted file mode 100644
index d74f1215fd..0000000000
--- a/drivers/net/npe/IxEthDBReports.c
+++ /dev/null
@@ -1,628 +0,0 @@
-/**
- * @file IxEthDBAPI.c
- *
- * @brief Implementation of the public API
- * 
- * @par
- * IXP400 SW Release version 2.0
- * 
- * -- Copyright Notice --
- * 
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- * 
- * @par
- * SPDX-License-Identifier:	BSD-3-Clause
- * @par
- * -- End of Copyright Notice --
- */
-
-#include "IxEthDB_p.h"
-
-extern HashTable dbHashtable;
-IX_ETH_DB_PRIVATE void ixEthDBPortInfoShow(IxEthDBPortId portID, IxEthDBRecordType recordFilter);
-IX_ETH_DB_PRIVATE IxEthDBStatus ixEthDBHeaderShow(IxEthDBRecordType recordFilter);
-IX_ETH_DB_PUBLIC IxEthDBStatus ixEthDBDependencyPortMapShow(IxEthDBPortId portID, IxEthDBPortMap map);
-
-/**
- * @brief displays a port dependency map
- *
- * @param portID ID of the port
- * @param map port map to display
- *
- * @return IX_ETH_DB_SUCCESS if the operation completed
- * successfully
- */ 
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBDependencyPortMapShow(IxEthDBPortId portID, IxEthDBPortMap map)
-{
-    UINT32 portIndex;
-    BOOL mapSelf = true, mapNone = true, firstPort = true;
-    
-    /* dependency port maps */
-    printf("Dependency port map: ");
-    
-    /* browse the port map */
-    for (portIndex = 0 ; portIndex < IX_ETH_DB_NUMBER_OF_PORTS ; portIndex++)
-    {
-        if (IS_PORT_INCLUDED(portIndex, map))
-        {
-            mapNone   = false;
-            
-            if (portIndex != portID)
-            {
-                mapSelf = false;
-            }
-            
-            printf("%s%d", firstPort ? "{" : ", ", portIndex);
-            
-            firstPort = false;
-        }
-    }
-    
-    if (mapNone)
-    {
-        mapSelf = false;
-    }
-    
-    printf("%s (%s)\n", firstPort ? "" : "}", mapSelf ? "self" : mapNone ? "none" : "group");
-    
-    return IX_ETH_DB_SUCCESS;
-}
-
-/**
- * @brief displays all the filtering records belonging to a port
- *
- * @param portID ID of the port to display
- *
- * Note that this function is documented in the main component
- * header file, IxEthDB.h.
- *
- * @warning deprecated, use @ref ixEthDBFilteringDatabaseShowRecords() 
- * instead. Calling this function is equivalent to calling
- * ixEthDBFilteringDatabaseShowRecords(portID, IX_ETH_DB_FILTERING_RECORD)
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBFilteringDatabaseShow(IxEthDBPortId portID)
-{
-    IxEthDBStatus local_result;
-    HashIterator iterator;
-    PortInfo *portInfo;
-    UINT32 recordCount = 0;
-
-    IX_ETH_DB_CHECK_PORT(portID);
-
-    IX_ETH_DB_CHECK_SINGLE_NPE(portID);
-
-    portInfo = &ixEthDBPortInfo[portID];
-
-    /* display table header */
-    printf("Ethernet database records for port ID [%d]\n", portID);
-    
-    ixEthDBDependencyPortMapShow(portID, portInfo->dependencyPortMap);
-    
-    if (ixEthDBPortDefinitions[portID].type == IX_ETH_NPE)
-    {
-        printf("NPE updates are %s\n\n", portInfo->updateMethod.updateEnabled ? "enabled" : "disabled");
-    }
-    else
-    {
-        printf("updates disabled (not an NPE)\n\n");
-    }
-
-    printf("    MAC address    |   Age  | Type \n");
-    printf("___________________________________\n");
-
-    /* browse database */
-    BUSY_RETRY(ixEthDBInitHashIterator(&dbHashtable, &iterator));
-
-    while (IS_ITERATOR_VALID(&iterator))
-    {
-      MacDescriptor *descriptor = (MacDescriptor *) iterator.node->data;
-
-      if (descriptor->portID == portID && descriptor->type == IX_ETH_DB_FILTERING_RECORD)
-      {
-          recordCount++;
-
-          /* display entry */
-          printf(" %02X:%02X:%02X:%02X:%02X:%02X | %5d  | %s\n",
-              descriptor->macAddress[0],
-              descriptor->macAddress[1],
-              descriptor->macAddress[2],
-              descriptor->macAddress[3],
-              descriptor->macAddress[4],
-              descriptor->macAddress[5],
-              descriptor->recordData.filteringData.age,
-              descriptor->recordData.filteringData.staticEntry ? "static" : "dynamic");
-      }
-
-      /* move to the next record */
-      BUSY_RETRY_WITH_RESULT(ixEthDBIncrementHashIterator(&dbHashtable, &iterator), local_result);
-
-      /* debug */
-      if (local_result == IX_ETH_DB_BUSY)
-      {
-          return IX_ETH_DB_FAIL;
-      }
-    }
-
-    /* display number of records */
-    printf("\nFound %d records\n", recordCount);
-
-    return IX_ETH_DB_SUCCESS;
-}
-
-/**
- * @brief displays all the filtering records belonging to all the ports
- *
- * Note that this function is documented in the main component
- * header file, IxEthDB.h.
- *
- * @warning deprecated, use @ref ixEthDBFilteringDatabaseShowRecords() 
- * instead. Calling this function is equivalent to calling
- * ixEthDBFilteringDatabaseShowRecords(IX_ETH_DB_ALL_PORTS, IX_ETH_DB_FILTERING_RECORD)
- */
-IX_ETH_DB_PUBLIC
-void ixEthDBFilteringDatabaseShowAll()
-{
-    IxEthDBPortId portIndex;
-
-    printf("\nEthernet learning/filtering database: listing %d ports\n\n", (UINT32) IX_ETH_DB_NUMBER_OF_PORTS);
-
-    for (portIndex = 0 ; portIndex < IX_ETH_DB_NUMBER_OF_PORTS ; portIndex++)
-    {
-        ixEthDBFilteringDatabaseShow(portIndex);
-
-        if (portIndex < IX_ETH_DB_NUMBER_OF_PORTS - 1)
-        {
-            printf("\n");
-        }
-    }
-}
-
-/**
- * @brief displays one record in a format depending on the record filter
- *
- * @param descriptor pointer to the record
- * @param recordFilter format filter
- *
- * This function will display the fields in a record depending on the
- * selected record filter.
- *
- * @internal
- */
-IX_ETH_DB_PRIVATE
-void ixEthDBRecordShow(MacDescriptor *descriptor, IxEthDBRecordType recordFilter)
-{
-    if (recordFilter == IX_ETH_DB_FILTERING_VLAN_RECORD
-        || recordFilter == (IX_ETH_DB_FILTERING_RECORD | IX_ETH_DB_FILTERING_VLAN_RECORD))
-    {
-        /* display VLAN record header - leave this commented code in place, its purpose is to align the print format with the header
-        printf("    MAC address    |   Age  |   Type   | VLAN ID | CFI | QoS class \n");
-        printf("___________________________________________________________________\n"); */
-
-        if (descriptor->type == IX_ETH_DB_FILTERING_VLAN_RECORD)
-        {
-            printf("%02X:%02X:%02X:%02X:%02X:%02X | %3d | %s | %d | %d | %d\n",
-                descriptor->macAddress[0],
-                descriptor->macAddress[1],
-                descriptor->macAddress[2],
-                descriptor->macAddress[3],
-                descriptor->macAddress[4],
-                descriptor->macAddress[5],
-                descriptor->recordData.filteringVlanData.age,
-                descriptor->recordData.filteringVlanData.staticEntry ? "static" : "dynamic",
-                IX_ETH_DB_GET_VLAN_ID(descriptor->recordData.filteringVlanData.ieee802_1qTag),
-                (descriptor->recordData.filteringVlanData.ieee802_1qTag & 0x1000) >> 12,
-                IX_ETH_DB_GET_QOS_PRIORITY(descriptor->recordData.filteringVlanData.ieee802_1qTag));
-         }
-         else if (descriptor->type == IX_ETH_DB_FILTERING_RECORD)
-         {
-            printf("%02X:%02X:%02X:%02X:%02X:%02X | %3d | %s | - | - | -\n",
-                descriptor->macAddress[0],
-                descriptor->macAddress[1],
-                descriptor->macAddress[2],
-                descriptor->macAddress[3],
-                descriptor->macAddress[4],
-                descriptor->macAddress[5],
-                descriptor->recordData.filteringData.age,
-                descriptor->recordData.filteringData.staticEntry ? "static" : "dynamic");
-         }
-    }
-    else if (recordFilter == IX_ETH_DB_FILTERING_RECORD)
-    {
-        /* display filtering record header - leave this commented code in place, its purpose is to align the print format with the header
-        printf("    MAC address    |   Age  |   Type   \n");
-        printf("_______________________________________\n");  */
-
-        if (descriptor->type == IX_ETH_DB_FILTERING_RECORD)
-        {
-         printf("%02X:%02X:%02X:%02X:%02X:%02X | %3d | %s \n",
-             descriptor->macAddress[0],
-             descriptor->macAddress[1],
-             descriptor->macAddress[2],
-             descriptor->macAddress[3],
-             descriptor->macAddress[4],
-             descriptor->macAddress[5],
-             descriptor->recordData.filteringData.age,
-             descriptor->recordData.filteringData.staticEntry ? "static" : "dynamic");
-        }
-    }
-    else if (recordFilter == IX_ETH_DB_WIFI_RECORD)
-    {
-        /* display WiFi record header - leave this commented code in place, its purpose is to align the print format with the header 
-        printf("    MAC address    |   GW MAC address  \n");
-        printf("_______________________________________\n"); */
-
-        if (descriptor->type == IX_ETH_DB_WIFI_RECORD)
-        {
-            if (descriptor->recordData.wifiData.type == IX_ETH_DB_WIFI_AP_TO_AP)
-            {
-                /* gateway address present */
-                printf("%02X:%02X:%02X:%02X:%02X:%02X | %02X:%02X:%02X:%02X:%02X:%02X \n",
-                    descriptor->macAddress[0],
-                    descriptor->macAddress[1],
-                    descriptor->macAddress[2],
-                    descriptor->macAddress[3],
-                    descriptor->macAddress[4],
-                    descriptor->macAddress[5],
-                    descriptor->recordData.wifiData.gwMacAddress[0],
-                    descriptor->recordData.wifiData.gwMacAddress[1],
-                    descriptor->recordData.wifiData.gwMacAddress[2],
-                    descriptor->recordData.wifiData.gwMacAddress[3],
-                    descriptor->recordData.wifiData.gwMacAddress[4],
-                    descriptor->recordData.wifiData.gwMacAddress[5]);
-            }
-            else
-            {
-                /* no gateway */
-                printf("%02X:%02X:%02X:%02X:%02X:%02X | ----no gateway----- \n",
-                    descriptor->macAddress[0],
-                    descriptor->macAddress[1],
-                    descriptor->macAddress[2],
-                    descriptor->macAddress[3],
-                    descriptor->macAddress[4],
-                    descriptor->macAddress[5]);
-            }
-        }
-    }
-    else if (recordFilter == IX_ETH_DB_FIREWALL_RECORD)
-    {
-        /* display Firewall record header - leave this commented code in place, its purpose is to align the print format with the header 
-        printf("    MAC address   \n");
-        printf("__________________\n"); */
-
-        if (descriptor->type == IX_ETH_DB_FIREWALL_RECORD)
-        {
-            printf("%02X:%02X:%02X:%02X:%02X:%02X \n",
-                descriptor->macAddress[0],
-                descriptor->macAddress[1],
-                descriptor->macAddress[2],
-                descriptor->macAddress[3],
-                descriptor->macAddress[4],
-                descriptor->macAddress[5]);
-        }
-    }
-    else if (recordFilter == IX_ETH_DB_ALL_RECORD_TYPES)
-    {
-        /* display composite record header - leave this commented code in place, its purpose is to align the print format with the header 
-        printf("    MAC address   | Record | Age|  Type   | VLAN |CFI| QoS |  GW MAC address   \n");
-        printf("_______________________________________________________________________________\n"); */
-
-        if (descriptor->type == IX_ETH_DB_FILTERING_VLAN_RECORD)
-        {
-            printf("%02X:%02X:%02X:%02X:%02X:%02X |  VLAN  | %2d | %s | %4d | %1d |  %1d  | -----------------\n",
-                descriptor->macAddress[0],
-                descriptor->macAddress[1],
-                descriptor->macAddress[2],
-                descriptor->macAddress[3],
-                descriptor->macAddress[4],
-                descriptor->macAddress[5],
-                descriptor->recordData.filteringVlanData.age,
-                descriptor->recordData.filteringVlanData.staticEntry ? "static " : "dynamic",
-                IX_ETH_DB_GET_VLAN_ID(descriptor->recordData.filteringVlanData.ieee802_1qTag),
-                (descriptor->recordData.filteringVlanData.ieee802_1qTag & 0x1000) >> 12,
-                IX_ETH_DB_GET_QOS_PRIORITY(descriptor->recordData.filteringVlanData.ieee802_1qTag));
-         }
-         else if (descriptor->type == IX_ETH_DB_FILTERING_RECORD)
-         {
-            printf("%02X:%02X:%02X:%02X:%02X:%02X | Filter | %2d | %s | ---- | - | --- | -----------------\n",
-                descriptor->macAddress[0],
-                descriptor->macAddress[1],
-                descriptor->macAddress[2],
-                descriptor->macAddress[3],
-                descriptor->macAddress[4],
-                descriptor->macAddress[5],
-                descriptor->recordData.filteringData.age,
-                descriptor->recordData.filteringData.staticEntry ? "static " : "dynamic");
-         }
-        else if (descriptor->type == IX_ETH_DB_WIFI_RECORD)
-        {
-            if (descriptor->recordData.wifiData.type == IX_ETH_DB_WIFI_AP_TO_AP)
-            {
-                /* gateway address present */
-                printf("%02X:%02X:%02X:%02X:%02X:%02X |  WiFi  | -- | AP=>AP  | ---- | - | --- | %02X:%02X:%02X:%02X:%02X:%02X\n",
-                    descriptor->macAddress[0],
-                    descriptor->macAddress[1],
-                    descriptor->macAddress[2],
-                    descriptor->macAddress[3],
-                    descriptor->macAddress[4],
-                    descriptor->macAddress[5],
-                    descriptor->recordData.wifiData.gwMacAddress[0],
-                    descriptor->recordData.wifiData.gwMacAddress[1],
-                    descriptor->recordData.wifiData.gwMacAddress[2],
-                    descriptor->recordData.wifiData.gwMacAddress[3],
-                    descriptor->recordData.wifiData.gwMacAddress[4],
-                    descriptor->recordData.wifiData.gwMacAddress[5]);
-            }
-            else
-            {
-                /* no gateway */
-                printf("%02X:%02X:%02X:%02X:%02X:%02X |  WiFi  | -- | AP=>ST  | ---- | - | --- | -- no gateway -- \n",
-                    descriptor->macAddress[0],
-                    descriptor->macAddress[1],
-                    descriptor->macAddress[2],
-                    descriptor->macAddress[3],
-                    descriptor->macAddress[4],
-                    descriptor->macAddress[5]);
-            }
-        }
-        else if (descriptor->type == IX_ETH_DB_FIREWALL_RECORD)
-        {
-            printf("%02X:%02X:%02X:%02X:%02X:%02X |   FW   | -- | ------- | ---- | - | --- | -----------------\n",
-                descriptor->macAddress[0],
-                descriptor->macAddress[1],
-                descriptor->macAddress[2],
-                descriptor->macAddress[3],
-                descriptor->macAddress[4],
-                descriptor->macAddress[5]);
-        }
-    }
-    else
-    {
-        printf("invalid record filter\n");
-    }
-}
-
-/**
- * @brief displays the status, records and configuration information of a port
- *
- * @param portID ID of the port
- * @param recordFilter record filter to display
- *
- * @internal
- */
-IX_ETH_DB_PRIVATE
-void ixEthDBPortInfoShow(IxEthDBPortId portID, IxEthDBRecordType recordFilter)
-{
-    PortInfo *portInfo = &ixEthDBPortInfo[portID];
-    UINT32 recordCount = 0;
-    HashIterator iterator;
-    IxEthDBStatus local_result;
-
-    /* display port status */
-    printf("== Port ID %d ==\n", portID);
-
-    /* display capabilities */
-    printf("- Capabilities: ");
-
-    if ((portInfo->featureCapability & IX_ETH_DB_LEARNING) != 0)
-    {
-        printf("Learning (%s) ", ((portInfo->featureStatus & IX_ETH_DB_LEARNING) != 0) ? "on" : "off");
-    }
-
-    if ((portInfo->featureCapability & IX_ETH_DB_VLAN_QOS) != 0)
-    {
-        printf("VLAN/QoS (%s) ", ((portInfo->featureStatus & IX_ETH_DB_VLAN_QOS) != 0) ? "on" : "off");
-    }
-
-    if ((portInfo->featureCapability & IX_ETH_DB_FIREWALL) != 0)
-    {
-        printf("Firewall (%s) ", ((portInfo->featureStatus & IX_ETH_DB_FIREWALL) != 0) ? "on" : "off");
-    }
-
-    if ((portInfo->featureCapability & IX_ETH_DB_WIFI_HEADER_CONVERSION) != 0)
-    {
-        printf("WiFi (%s) ", ((portInfo->featureStatus & IX_ETH_DB_WIFI_HEADER_CONVERSION) != 0) ? "on" : "off");
-    }
-
-    if ((portInfo->featureCapability & IX_ETH_DB_SPANNING_TREE_PROTOCOL) != 0)
-    {
-        printf("STP (%s) ", ((portInfo->featureStatus & IX_ETH_DB_SPANNING_TREE_PROTOCOL) != 0) ? "on" : "off");
-    }
-
-    printf("\n");
-
-    /* dependency map */
-    ixEthDBDependencyPortMapShow(portID, portInfo->dependencyPortMap);
-
-    /* NPE dynamic updates */
-    if (ixEthDBPortDefinitions[portID].type == IX_ETH_NPE) 
-    {
-        printf(" - NPE dynamic update is %s\n", portInfo->updateMethod.updateEnabled ? "enabled" : "disabled");
-    }
-    else
-    {
-        printf(" - dynamic update disabled (not an NPE)\n");
-    }
-
-    if ((portInfo->featureCapability & IX_ETH_DB_WIFI_HEADER_CONVERSION) != 0)
-    {
-        if ((portInfo->featureStatus & IX_ETH_DB_WIFI_HEADER_CONVERSION) != 0)
-        {
-            /* WiFi header conversion */
-            if ((portInfo->frameControlDurationID 
-                + portInfo->bbsid[0] 
-                + portInfo->bbsid[1] 
-                + portInfo->bbsid[2] 
-                + portInfo->bbsid[3] 
-                + portInfo->bbsid[4] 
-                + portInfo->bbsid[5]) == 0)
-            {
-                printf(" - WiFi header conversion not configured\n");
-            }
-            else
-            {  
-                printf(" - WiFi header conversion: BBSID [%02X:%02X:%02X:%02X:%02X:%02X], Frame Control 0x%X, Duration/ID 0x%X\n", 
-                    portInfo->bbsid[0],
-                    portInfo->bbsid[1],
-                    portInfo->bbsid[2],
-                    portInfo->bbsid[3],
-                    portInfo->bbsid[4],
-                    portInfo->bbsid[5],
-                    portInfo->frameControlDurationID >> 16,
-                    portInfo->frameControlDurationID & 0xFFFF);
-            }
-        }
-        else
-        {
-            printf(" - WiFi header conversion not enabled\n");
-        }
-    }
-
-    /* Firewall */
-    if ((portInfo->featureCapability & IX_ETH_DB_FIREWALL) != 0)
-    {
-        if ((portInfo->featureStatus & IX_ETH_DB_FIREWALL) != 0)
-        {
-            printf(" - Firewall is in %s-list mode\n", portInfo->firewallMode == IX_ETH_DB_FIREWALL_BLACK_LIST ? "black" : "white");
-            printf(" - Invalid source MAC address filtering is %s\n", portInfo->srcAddressFilterEnabled ? "enabled" : "disabled");
-        }
-        else
-        {
-            printf(" - Firewall not enabled\n");
-        }
-    }
-  
-    /* browse database if asked to display records */
-    if (recordFilter != IX_ETH_DB_NO_RECORD_TYPE)
-    {
-        printf("\n");
-        ixEthDBHeaderShow(recordFilter);
-
-        BUSY_RETRY(ixEthDBInitHashIterator(&dbHashtable, &iterator));
-
-        while (IS_ITERATOR_VALID(&iterator))
-        {
-            MacDescriptor *descriptor = (MacDescriptor *) iterator.node->data;
-
-            if (descriptor->portID == portID && (descriptor->type & recordFilter) != 0)
-            {
-                recordCount++;
-
-                /* display entry */
-                ixEthDBRecordShow(descriptor, recordFilter);
-            }
-
-            /* move to the next record */
-            BUSY_RETRY_WITH_RESULT(ixEthDBIncrementHashIterator(&dbHashtable, &iterator), local_result);
-
-            /* debug */
-            if (local_result == IX_ETH_DB_BUSY)
-            {
-                printf("EthDB (API): Error, database browser failed (no access), giving up\n");
-            }
-        }
-        
-        printf("\nFound %d records\n\n", recordCount);
-    }
-}
-
-/**
- * @brief displays a record header
- *
- * @param recordFilter record type filter
- *
- * This function displays a record header, depending on
- * the given record type filter. It is useful when used
- * in conjunction with ixEthDBRecordShow which will display
- * record fields formatted for the header, provided the same
- * record filter is used.
- *
- * @return IX_ETH_DB_SUCCESS if the operation completed
- * successfully or IX_ETH_DB_INVALID_ARG if the recordFilter
- * parameter is invalid or not supported
- *
- * @internal
- */
-IX_ETH_DB_PRIVATE
-IxEthDBStatus ixEthDBHeaderShow(IxEthDBRecordType recordFilter)
-{
-  if (recordFilter == IX_ETH_DB_FILTERING_VLAN_RECORD
-      || recordFilter == (IX_ETH_DB_FILTERING_RECORD | IX_ETH_DB_FILTERING_VLAN_RECORD))
-  {
-    /* display VLAN record header */
-    printf("    MAC address    |   Age  |   Type   | VLAN ID | CFI | QoS class \n");
-    printf("___________________________________________________________________\n");
-  }
-  else if (recordFilter == IX_ETH_DB_FILTERING_RECORD)
-  {
-    /* display filtering record header */
-    printf("    MAC address    |   Age  |   Type   \n");
-    printf("_______________________________________\n");
-  }
-  else if (recordFilter == IX_ETH_DB_WIFI_RECORD)
-  {
-    /* display WiFi record header */
-    printf("    MAC address    |   GW MAC address  \n");
-    printf("_______________________________________\n");
-  }
-  else if (recordFilter == IX_ETH_DB_FIREWALL_RECORD)
-  {
-    /* display Firewall record header */
-    printf("    MAC address   \n");
-    printf("__________________\n");
-  }
-  else if (recordFilter == IX_ETH_DB_ALL_RECORD_TYPES)
-  {
-    /* display composite record header */
-    printf("    MAC address   | Record | Age|  Type   | VLAN |CFI| QoS |  GW MAC address   \n");
-    printf("_______________________________________________________________________________\n");
-  }
-  else
-  {
-    return IX_ETH_DB_INVALID_ARG;
-  }
-  
-  return IX_ETH_DB_SUCCESS;
-}
-
-/**
- * @brief displays database information (records and port information)
- *
- * @param portID ID of the port to display (or IX_ETH_DB_ALL_PORTS for all the ports)
- * @param recordFilter record filter (use IX_ETH_DB_NO_RECORD_TYPE to display only
- * port information)
- * 
- * Note that this function is documented in the main component header
- * file, IxEthDB.h.
- *
- * @return IX_ETH_DB_SUCCESS if the operation completed successfully or
- * an appropriate error code otherwise
- * 
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBFilteringDatabaseShowRecords(IxEthDBPortId portID, IxEthDBRecordType recordFilter)
-{
-  IxEthDBPortId currentPort;
-  BOOL showAllPorts = (portID == IX_ETH_DB_ALL_PORTS);
-  
-  IX_ETH_DB_CHECK_PORT_ALL(portID);
-
-  printf("\nEthernet learning/filtering database: listing %d port(s)\n\n", showAllPorts ? (UINT32) IX_ETH_DB_NUMBER_OF_PORTS : 1);
-  
-  currentPort = showAllPorts ? 0 : portID;
-  
-  while (currentPort != IX_ETH_DB_NUMBER_OF_PORTS)
-  {
-    /* display port info */
-    ixEthDBPortInfoShow(currentPort, recordFilter);
-    
-    /* next port */
-    currentPort = showAllPorts ? currentPort + 1 : IX_ETH_DB_NUMBER_OF_PORTS;
-  }
-  
-  return IX_ETH_DB_SUCCESS;
-}
-
diff --git a/drivers/net/npe/IxEthDBSearch.c b/drivers/net/npe/IxEthDBSearch.c
deleted file mode 100644
index 4fd28da080..0000000000
--- a/drivers/net/npe/IxEthDBSearch.c
+++ /dev/null
@@ -1,303 +0,0 @@
-/**
- * @file IxEthDBSearch.c
- * 
- * @par
- * IXP400 SW Release version 2.0
- * 
- * -- Copyright Notice --
- * 
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- * 
- * @par
- * SPDX-License-Identifier:	BSD-3-Clause
- * @par
- * -- End of Copyright Notice --
- */
-
-#include "IxEthDB_p.h"
-
-extern HashTable dbHashtable;
-
-/**
- * @brief matches two database records based on their MAC addresses
- *
- * @param untypedReference record to match against
- * @param untypedEntry record to match
- *
- * @return true if the match is successful or false otherwise
- *
- * @internal
- */
-IX_ETH_DB_PUBLIC
-BOOL ixEthDBAddressRecordMatch(void *untypedReference, void *untypedEntry)
-{
-    MacDescriptor *entry     = (MacDescriptor *) untypedEntry;
-    MacDescriptor *reference = (MacDescriptor *) untypedReference;
-    
-    /* check accepted record types */
-    if ((entry->type & reference->type) == 0) return false;
-       
-    return (ixEthDBAddressCompare((UINT8 *) entry->macAddress, (UINT8 *) reference->macAddress) == 0);
-}
-
-/**
- * @brief matches two database records based on their MAC addresses
- * and VLAN IDs
- *
- * @param untypedReference record to match against
- * @param untypedEntry record to match
- *
- * @return true if the match is successful or false otherwise
- *
- * @internal
- */
-IX_ETH_DB_PUBLIC
-BOOL ixEthDBVlanRecordMatch(void *untypedReference, void *untypedEntry)
-{
-    MacDescriptor *entry     = (MacDescriptor *) untypedEntry;
-    MacDescriptor *reference = (MacDescriptor *) untypedReference;
-    
-    /* check accepted record types */
-    if ((entry->type & reference->type) == 0) return false;
-    
-    return (IX_ETH_DB_GET_VLAN_ID(entry->recordData.filteringVlanData.ieee802_1qTag) ==
-        IX_ETH_DB_GET_VLAN_ID(reference->recordData.filteringVlanData.ieee802_1qTag)) &&
-        (ixEthDBAddressCompare(entry->macAddress, reference->macAddress) == 0);
-}
-
-/**
- * @brief matches two database records based on their MAC addresses
- * and port IDs
- *
- * @param untypedReference record to match against
- * @param untypedEntry record to match
- *
- * @return true if the match is successful or false otherwise
- *
- * @internal
- */
-IX_ETH_DB_PUBLIC
-BOOL ixEthDBPortRecordMatch(void *untypedReference, void *untypedEntry)
-{
-    MacDescriptor *entry     = (MacDescriptor *) untypedEntry;
-    MacDescriptor *reference = (MacDescriptor *) untypedReference;
-    
-    /* check accepted record types */
-    if ((entry->type & reference->type) == 0) return false;
-    
-    return (entry->portID == reference->portID) &&
-        (ixEthDBAddressCompare(entry->macAddress, reference->macAddress) == 0);
-}
-
-/**
- * @brief dummy matching function, registered for safety
- *
- * @param reference record to match against (unused)
- * @param entry record to match (unused)
- *
- * This function is registered in the matching functions
- * array on invalid types. Calling it will display an 
- * error message, indicating an error in the component logic.
- *
- * @return false
- *
- * @internal
- */
-IX_ETH_DB_PUBLIC
-BOOL ixEthDBNullMatch(void *reference, void *entry)
-{
-    /* display an error message */
-
-    ixOsalLog(IX_OSAL_LOG_LVL_WARNING, IX_OSAL_LOG_DEV_STDOUT, "DB: (Search) The NullMatch function was called, wrong key type?\n", 0, 0, 0, 0, 0, 0);
-
-
-    return false;
-}
-
-/**
- * @brief registers hash matching methods
- *
- * @param matchFunctions table of match functions to be populated
- *
- * This function registers the available record matching functions
- * by indexing them on record types into the given function array.
- * 
- * Note that it is compulsory to call this in ixEthDBInit(), 
- * otherwise hashtable searching and removal will not work
- *
- * @return number of registered functions
- *
- * @internal
- */
-IX_ETH_DB_PUBLIC
-UINT32 ixEthDBMatchMethodsRegister(MatchFunction *matchFunctions)
-{
-    UINT32 i;
-    
-    /* safety first */
-    for ( i = 0 ; i < IX_ETH_DB_MAX_KEY_INDEX + 1 ; i++)
-    {
-        matchFunctions[i] = ixEthDBNullMatch;
-    }
-    
-    /* register MAC search method */
-    matchFunctions[IX_ETH_DB_MAC_KEY] = ixEthDBAddressRecordMatch;
-    
-    /* register MAC/PortID search method */
-    matchFunctions[IX_ETH_DB_MAC_PORT_KEY] = ixEthDBPortRecordMatch;
-    
-    /* register MAC/VLAN ID search method */
-    matchFunctions[IX_ETH_DB_MAC_VLAN_KEY] = ixEthDBVlanRecordMatch;
-    
-    return 3; /* three methods */
-}
-
-/**
- * @brief search a record in the Ethernet datbase
- *
- * @param macAddress MAC address to perform the search on
- * @param typeFilter type of records to consider for matching
- *
- * @warning if searching is successful an implicit write lock
- * to the search result is granted, therefore unlock the 
- * entry using @ref ixEthDBReleaseHashNode() as soon as possible.
- *
- * @see ixEthDBReleaseHashNode()
- *
- * @return the search result, or NULL if a record with the given
- * MAC address was not found
- *
- * @internal
- */
-IX_ETH_DB_PUBLIC
-HashNode* ixEthDBSearch(IxEthDBMacAddr *macAddress, IxEthDBRecordType typeFilter)
-{
-    HashNode *searchResult = NULL;
-    MacDescriptor reference;
-    
-    TEST_FIXTURE_INCREMENT_DB_CORE_ACCESS_COUNTER;
-
-    if (macAddress == NULL)
-    {
-        return NULL;
-    }
-
-    /* fill search fields */
-    memcpy(reference.macAddress, macAddress, sizeof (IxEthDBMacAddr));
-    
-    /* set acceptable record types */
-    reference.type = typeFilter;
-    
-    BUSY_RETRY(ixEthDBSearchHashEntry(&dbHashtable, IX_ETH_DB_MAC_KEY, &reference, &searchResult));
-
-    return searchResult;
-}
-
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBPeek(IxEthDBMacAddr *macAddress, IxEthDBRecordType typeFilter)
-{
-    MacDescriptor reference;
-    IxEthDBStatus result;
-    
-    TEST_FIXTURE_INCREMENT_DB_CORE_ACCESS_COUNTER;
-
-    if (macAddress == NULL)
-    {
-        return IX_ETH_DB_INVALID_ARG;
-    }
-
-    /* fill search fields */
-    memcpy(reference.macAddress, macAddress, sizeof (IxEthDBMacAddr));
-    
-    /* set acceptable record types */
-    reference.type = typeFilter;
-    
-    result = ixEthDBPeekHashEntry(&dbHashtable, IX_ETH_DB_MAC_KEY, &reference);
-
-    return result;
-}
-
-/**
- * @brief search a record in the Ethernet datbase
- *
- * @param macAddress MAC address to perform the search on
- * @param portID port ID to perform the search on
- * @param typeFilter type of records to consider for matching
- *
- * @warning if searching is successful an implicit write lock
- * to the search result is granted, therefore unlock the 
- * entry using @ref ixEthDBReleaseHashNode() as soon as possible.
- *
- * @see ixEthDBReleaseHashNode()
- *
- * @return the search result, or NULL if a record with the given
- * MAC address/port ID combination was not found
- *
- * @internal
- */
-IX_ETH_DB_PUBLIC
-HashNode* ixEthDBPortSearch(IxEthDBMacAddr *macAddress, IxEthDBPortId portID, IxEthDBRecordType typeFilter)
-{
-    HashNode *searchResult = NULL;
-    MacDescriptor reference;
-    
-    if (macAddress == NULL)
-    {
-        return NULL;
-    }
-    
-    /* fill search fields */
-    memcpy(reference.macAddress, macAddress, sizeof (IxEthDBMacAddr));
-    reference.portID = portID;
-    
-    /* set acceptable record types */
-    reference.type = typeFilter;
-
-    BUSY_RETRY(ixEthDBSearchHashEntry(&dbHashtable, IX_ETH_DB_MAC_PORT_KEY, &reference, &searchResult));
-
-    return searchResult;
-}
-
-/**
- * @brief search a record in the Ethernet datbase
- *
- * @param macAddress MAC address to perform the search on
- * @param vlanID VLAN ID to perform the search on
- * @param typeFilter type of records to consider for matching
- *
- * @warning if searching is successful an implicit write lock
- * to the search result is granted, therefore unlock the 
- * entry using @ref ixEthDBReleaseHashNode() as soon as possible.
- *
- * @see ixEthDBReleaseHashNode()
- *
- * @return the search result, or NULL if a record with the given
- * MAC address/VLAN ID combination was not found
- *
- * @internal
- */
-IX_ETH_DB_PUBLIC
-HashNode* ixEthDBVlanSearch(IxEthDBMacAddr *macAddress, IxEthDBVlanId vlanID, IxEthDBRecordType typeFilter)
-{
-    HashNode *searchResult = NULL;
-    MacDescriptor reference;
-    
-    if (macAddress == NULL)
-    {
-        return NULL;
-    }
-    
-    /* fill search fields */
-    memcpy(reference.macAddress, macAddress, sizeof (IxEthDBMacAddr));
-    reference.recordData.filteringVlanData.ieee802_1qTag = 
-            IX_ETH_DB_SET_VLAN_ID(reference.recordData.filteringVlanData.ieee802_1qTag, vlanID);
-    
-    /* set acceptable record types */
-    reference.type = typeFilter;
-
-    BUSY_RETRY(ixEthDBSearchHashEntry(&dbHashtable, IX_ETH_DB_MAC_VLAN_KEY, &reference, &searchResult));
-
-    return searchResult;
-}
diff --git a/drivers/net/npe/IxEthDBSpanningTree.c b/drivers/net/npe/IxEthDBSpanningTree.c
deleted file mode 100644
index e12be0d884..0000000000
--- a/drivers/net/npe/IxEthDBSpanningTree.c
+++ /dev/null
@@ -1,83 +0,0 @@
-/**
- * @file IxEthDBSpanningTree.c
- *
- * @brief Implementation of the STP API
- * 
- * @par
- * IXP400 SW Release version 2.0
- * 
- * -- Copyright Notice --
- * 
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- * 
- * @par
- * SPDX-License-Identifier:	BSD-3-Clause
- * @par
- * -- End of Copyright Notice --
- */
-
-
-#include "IxEthDB_p.h"
-
-/**
- * @brief sets the STP blocking state of a port
- *
- * @param portID ID of the port
- * @param blocked true to block the port or false to unblock it
- * 
- * Note that this function is documented in the main component
- * header file, IxEthDB.h.
- *
- * @return IX_ETH_DB_SUCCESS if the operation completed successfully
- * or an appropriate error message otherwise
- */
-IX_ETH_DB_PUBLIC 
-IxEthDBStatus ixEthDBSpanningTreeBlockingStateSet(IxEthDBPortId portID, BOOL blocked)
-{
-    IxNpeMhMessage message;
-    IX_STATUS result;
-    
-    IX_ETH_DB_CHECK_PORT(portID);
-    
-    IX_ETH_DB_CHECK_SINGLE_NPE(portID);
- 
-    IX_ETH_DB_CHECK_FEATURE(portID, IX_ETH_DB_SPANNING_TREE_PROTOCOL);
-    
-    ixEthDBPortInfo[portID].stpBlocked = blocked;
-
-    FILL_SETBLOCKINGSTATE_MSG(message, portID, blocked);
-    
-    IX_ETHDB_SEND_NPE_MSG(IX_ETH_DB_PORT_ID_TO_NPE(portID), message, result);
-    
-    return result;
-}
-
-/**
- * @brief retrieves the STP blocking state of a port
- *
- * @param portID ID of the port
- * @param blocked address to write the blocked status into
- *
- * Note that this function is documented in the main component
- * header file, IxEthDB.h.
- *
- * @return IX_ETH_DB_SUCCESS if the operation completed successfully
- * or an appropriate error message otherwise
- */
-IX_ETH_DB_PUBLIC 
-IxEthDBStatus ixEthDBSpanningTreeBlockingStateGet(IxEthDBPortId portID, BOOL *blocked)
-{
-    IX_ETH_DB_CHECK_PORT(portID);
-    
-    IX_ETH_DB_CHECK_SINGLE_NPE(portID);
- 
-    IX_ETH_DB_CHECK_FEATURE(portID, IX_ETH_DB_SPANNING_TREE_PROTOCOL);
-    
-    IX_ETH_DB_CHECK_REFERENCE(blocked);
-    
-    *blocked = ixEthDBPortInfo[portID].stpBlocked;
-    
-    return IX_ETH_DB_SUCCESS;
-}
diff --git a/drivers/net/npe/IxEthDBUtil.c b/drivers/net/npe/IxEthDBUtil.c
deleted file mode 100644
index 40d4470bef..0000000000
--- a/drivers/net/npe/IxEthDBUtil.c
+++ /dev/null
@@ -1,96 +0,0 @@
-/**
- * @file ethUtil.c
- *
- * @brief Utility functions
- * 
- * @par
- * IXP400 SW Release version 2.0
- * 
- * -- Copyright Notice --
- * 
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- * 
- * @par
- * SPDX-License-Identifier:	BSD-3-Clause
- * @par
- * -- End of Copyright Notice --
- */
-
-
-#include "IxFeatureCtrl.h"
-#include "IxEthDB_p.h"
-
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBSingleEthNpeCheck(IxEthDBPortId portID)
-{
-    /* If not IXP42X A0 stepping, proceed to check for existence of coprocessors */ 
-    if ((IX_FEATURE_CTRL_SILICON_TYPE_A0 != 
-        (ixFeatureCtrlProductIdRead() & IX_FEATURE_CTRL_SILICON_STEPPING_MASK))
-        || (IX_FEATURE_CTRL_DEVICE_TYPE_IXP42X != ixFeatureCtrlDeviceRead ()))
-    {  
-        if ((portID == 0) && 
-            (ixFeatureCtrlComponentCheck(IX_FEATURECTRL_ETH0) ==
-             IX_FEATURE_CTRL_COMPONENT_DISABLED))
-        {
-	    return IX_ETH_DB_FAIL;
-        }
-
-        if ((portID == 1) &&
-            (ixFeatureCtrlComponentCheck(IX_FEATURECTRL_ETH1) ==
-             IX_FEATURE_CTRL_COMPONENT_DISABLED))
-        {
-	    return IX_ETH_DB_FAIL;	    
-        }
-
-        if ((portID == 2) &&
-            (ixFeatureCtrlComponentCheck(IX_FEATURECTRL_NPEA_ETH) ==
-             IX_FEATURE_CTRL_COMPONENT_DISABLED))
-        {
-	    return IX_ETH_DB_FAIL;	    
-        }
-    }
-    
-    return IX_ETH_DB_SUCCESS;
-}
-
-IX_ETH_DB_PUBLIC
-BOOL ixEthDBCheckSingleBitValue(UINT32 value)
-{
-#if (CPU != SIMSPARCSOLARIS) && !defined (__wince)
-    UINT32 shift;
-    
-    /* use the count-leading-zeros XScale instruction */
-    __asm__ ("clz %0, %1\n" : "=r" (shift) : "r" (value));
-    
-    return ((value << shift) == 0x80000000UL);
-    
-#else
-	
-    while (value != 0)
-    {
-        if (value == 1) return true;
-        else if ((value & 1) == 1) return false;
-
-        value >>= 1;
-    }
-    
-    return false;
-
-#endif
-}
-
-const char *mac2string(const unsigned char *mac)
-{
-  static char str[19];
-  
-  if (mac == NULL)
-  {
-    return NULL;
-  }  
-
-  sprintf(str, "%02X:%02X:%02X:%02X:%02X:%02X", mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
-
-  return str;
-}
diff --git a/drivers/net/npe/IxEthDBVlan.c b/drivers/net/npe/IxEthDBVlan.c
deleted file mode 100644
index 483e348934..0000000000
--- a/drivers/net/npe/IxEthDBVlan.c
+++ /dev/null
@@ -1,1155 +0,0 @@
-/**
- * @file IxEthDBVlan.c
- *
- * @brief Implementation of the VLAN API
- * 
- * @par
- * IXP400 SW Release version 2.0
- * 
- * -- Copyright Notice --
- * 
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- * 
- * @par
- * SPDX-License-Identifier:	BSD-3-Clause
- * @par
- * -- End of Copyright Notice --
- */
-
-#include "IxEthDB.h"
-#include "IxEthDB_p.h"
-
-/* forward prototypes */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBUpdateTrafficClass(IxEthDBPortId portID, UINT32 classIndex);
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBVlanTableGet(IxEthDBPortId portID, IxEthDBVlanSet portVlanTable, IxEthDBVlanSet vlanSet);
-
-/* contants used by various functions as "action" parameter */
-#define ADD_VLAN    (0x1)
-#define REMOVE_VLAN (0x2)
-
-/**
- * @brief adds or removes a VLAN from a VLAN set
- *
- * @param vlanID VLAN ID to add or remove
- * @param table VLAN set to add into or remove from
- * @param action ADD_VLAN or REMOVE_VLAN
- * 
- * @internal
- */
-IX_ETH_DB_PRIVATE
-void ixEthDBLocalVlanMembershipChange(UINT32 vlanID, IxEthDBVlanSet table, UINT32 action)
-{
-    UINT32 setOffset;
-    
-    /* add/remove VID to membership table */
-    setOffset = VLAN_SET_OFFSET(vlanID); /* we need 9 bits to index the 512 byte membership array */
-
-    if (action == ADD_VLAN)
-    {
-        table[setOffset] |= 1 << VLAN_SET_MASK(vlanID);
-    }
-    else if (action == REMOVE_VLAN)
-    {
-        table[setOffset] &= ~(1 << VLAN_SET_MASK(vlanID));
-    }
-}
-
-/**
- * @brief updates a set of 8 VLANs in an NPE
- *
- * @param portID ID of the port
- * @param setOffset offset of the 8 VLANs
- *
- * This function updates the VLAN membership table
- * and Transmit Tagging Info table for 8 consecutive
- * VLAN IDs indexed by setOffset.
- *
- * For example, a setOffset of 0 indexes VLAN IDs 0
- * through 7, 1 indexes VLAN IDs 8 through 9 etc.
- *
- * @return IX_ETH_DB_SUCCESS if the operation completed
- * successfully or an appropriate error message otherwise
- *
- * @internal
- */
-IX_ETH_DB_PRIVATE
-IxEthDBStatus ixEthDBVlanTableEntryUpdate(IxEthDBPortId portID, UINT32 setOffset)
-{
-    PortInfo *portInfo = &ixEthDBPortInfo[portID];
-    IxNpeMhMessage message;
-    IX_STATUS result;
-        
-    FILL_SETPORTVLANTABLEENTRY_MSG(message, IX_ETH_DB_PORT_ID_TO_NPE_LOGICAL_ID(portID), 
-        2 * setOffset, 
-        portInfo->vlanMembership[setOffset], 
-        portInfo->transmitTaggingInfo[setOffset]);
-    
-    IX_ETHDB_SEND_NPE_MSG(IX_ETH_DB_PORT_ID_TO_NPE(portID), message, result);
-    
-    return result;
-}
-
-/**
- * @brief updates a VLAN range in an NPE
- *
- * @param portID ID of the port
- *
- * This function is similar to @ref ixEthDBVlanTableEntryUpdate
- * except that it can update more than one VLAN set (up to
- * the entire VLAN membership and TTI tables if the offset is 0
- * and length is sizeof (IxEthDBVlanSet) (512 bytes).
- *
- * Updating the NPE via this method is slower as it requires
- * a memory copy from SDRAM, hence it is recommended that the
- * ixEthDBVlanTableEntryUpdate function is used where possible.
- *
- * @return IX_ETH_DB_SUCCESS if the operation completed
- * successfully or an appropriate error message otherwise
- *
- * @internal
- */
-IX_ETH_DB_PRIVATE
-IxEthDBStatus ixEthDBVlanTableRangeUpdate(IxEthDBPortId portID)
-{
-    PortInfo *portInfo    = &ixEthDBPortInfo[portID];
-    UINT8 *vlanUpdateZone = (UINT8 *) portInfo->updateMethod.vlanUpdateZone;
-    IxNpeMhMessage message;
-    UINT32 setIndex;
-    IX_STATUS result;
-
-    /* copy membership info and transmit tagging into into exchange area */
-    for (setIndex = 0 ; setIndex < sizeof (portInfo->vlanMembership) ; setIndex++)
-    {
-        /* membership and TTI data are interleaved */
-        vlanUpdateZone[setIndex * 2]     = portInfo->vlanMembership[setIndex];
-        vlanUpdateZone[setIndex * 2 + 1] = portInfo->transmitTaggingInfo[setIndex];
-    }
-
-    IX_OSAL_CACHE_FLUSH(vlanUpdateZone, FULL_VLAN_BYTE_SIZE);
-    
-    /* build NPE message */
-    FILL_SETPORTVLANTABLERANGE_MSG(message, IX_ETH_DB_PORT_ID_TO_NPE_LOGICAL_ID(portID), 0, 0, 
-        IX_OSAL_MMU_VIRT_TO_PHYS(vlanUpdateZone));
-
-    /* send message */    
-    IX_ETHDB_SEND_NPE_MSG(IX_ETH_DB_PORT_ID_TO_NPE(portID), message, result);
-
-    return result;
-}
-
-/**
- * @brief adds or removes a VLAN from a port's VLAN membership table
- * or Transmit Tagging Information table
- *
- * @param portID ID of the port
- * @param vlanID VLAN ID to add or remove
- * @param table to add or remove from
- * @param action ADD_VLAN or REMOVE_VLAN
- *
- * @return IX_ETH_DB_SUCCESS if the operation completed
- * successfully or an appropriate error message otherwise
- *
- * @internal
- */
-IX_ETH_DB_PRIVATE
-IxEthDBStatus ixEthDBPortVlanMembershipChange(IxEthDBPortId portID, IxEthDBVlanId vlanID, IxEthDBVlanSet table, UINT32 action)
-{
-    /* change VLAN in local membership table */
-    ixEthDBLocalVlanMembershipChange(vlanID, table, action);
-    
-    /* send updated entry to NPE */
-    return ixEthDBVlanTableEntryUpdate(portID, VLAN_SET_OFFSET(vlanID));
-}
-
-/**
- * @brief sets the default port VLAN tag (the lower 3 bytes are the PVID)
- *
- * @param portID ID of the port
- * @param vlanTag port VLAN tag (802.1Q tag)
- * 
- * Note that this function is documented in the main component
- * header file, IxEthDB.h.
- *
- * @return IX_ETH_DB_SUCCESS if the operation completed successfully
- * or an appropriate error message otherwise
- */
-IX_ETH_DB_PUBLIC 
-IxEthDBStatus ixEthDBPortVlanTagSet(IxEthDBPortId portID, IxEthDBVlanTag vlanTag)
-{
-    IxNpeMhMessage message;
-    IX_STATUS result;
-    
-    IX_ETH_DB_CHECK_PORT(portID);
-    
-    IX_ETH_DB_CHECK_SINGLE_NPE(portID);
- 
-    IX_ETH_DB_CHECK_VLAN_TAG(vlanTag);
-    
-    IX_ETH_DB_CHECK_FEATURE(portID, IX_ETH_DB_VLAN_QOS);
-        
-    /* add VLAN ID to local membership table */
-    ixEthDBPortVlanMembershipChange(portID, 
-        vlanTag & IX_ETH_DB_802_1Q_VLAN_MASK, 
-        ixEthDBPortInfo[portID].vlanMembership, 
-        ADD_VLAN);
-        
-    /* set tag in portInfo */
-    ixEthDBPortInfo[portID].vlanTag = vlanTag;
-    
-    /* build VLAN_SetDefaultRxVID message */
-    FILL_SETDEFAULTRXVID_MSG(message, 
-        IX_ETH_DB_PORT_ID_TO_NPE_LOGICAL_ID(portID), 
-        IX_IEEE802_1Q_VLAN_TPID, 
-        vlanTag);
-    
-    IX_ETHDB_SEND_NPE_MSG(IX_ETH_DB_PORT_ID_TO_NPE(portID), message, result);
-    
-    return result;
-}
-
-/**
- * @brief retrieves the default port VLAN tag (the lower 3 bytes are the PVID)
- *
- * @param portID ID of the port
- * @param vlanTag address to write the port VLAN tag (802.1Q tag) into
- * 
- * Note that this function is documented in the main component
- * header file, IxEthDB.h.
- *
- * @return IX_ETH_DB_SUCCESS if the operation completed successfully
- * or an appropriate error message otherwise
- */
-IX_ETH_DB_PUBLIC 
-IxEthDBStatus ixEthDBPortVlanTagGet(IxEthDBPortId portID, IxEthDBVlanTag *vlanTag)
-{
-    IX_ETH_DB_CHECK_PORT(portID);
-    
-    IX_ETH_DB_CHECK_SINGLE_NPE(portID);
-    
-    IX_ETH_DB_CHECK_FEATURE(portID, IX_ETH_DB_VLAN_QOS);
-    
-    IX_ETH_DB_CHECK_REFERENCE(vlanTag);
-    
-    *vlanTag = ixEthDBPortInfo[portID].vlanTag;
-    
-    return IX_ETH_DB_SUCCESS;
-}
-
-/**
- * @brief sets the VLAN tag (the lower 3 bytes are the PVID) of a 
- * database filtering record
- *
- * @param portID ID of the port
- * @param vlanTag VLAN tag (802.1Q tag)
- * 
- * Important: filtering records are automatically converted to 
- * IX_ETH_DB_FILTERING_VLAN record when added a VLAN tag.
- *
- * Note that this function is documented in the main component
- * header file, IxEthDB.h.
- *
- * @return IX_ETH_DB_SUCCESS if the operation completed successfully
- * or an appropriate error message otherwise
- */
-IX_ETH_DB_PUBLIC 
-IxEthDBStatus ixEthDBVlanTagSet(IxEthDBMacAddr *macAddr, IxEthDBVlanTag vlanTag)
-{
-    HashNode *searchResult;
-    MacDescriptor *descriptor;
-    
-    IX_ETH_DB_CHECK_REFERENCE(macAddr);
-    
-    IX_ETH_DB_CHECK_VLAN_TAG(vlanTag);
-    
-    searchResult = ixEthDBSearch(macAddr, IX_ETH_DB_ALL_FILTERING_RECORDS);
-    
-    if (searchResult == NULL)
-    {
-        return IX_ETH_DB_NO_SUCH_ADDR;
-    }
-    
-    descriptor = (MacDescriptor *) searchResult->data;
-    
-    /* set record type to VLAN if not already set */
-    descriptor->type = IX_ETH_DB_FILTERING_VLAN_RECORD;
-    
-    /* add vlan tag */
-    descriptor->recordData.filteringVlanData.ieee802_1qTag = vlanTag;
-    
-    /* transaction completed */
-    ixEthDBReleaseHashNode(searchResult);
-    
-    return IX_ETH_DB_SUCCESS;
-}
-
-/**
- * @brief retrieves the VLAN tag (the lower 3 bytes are the PVID) from a 
- * database VLAN filtering record
- *
- * @param portID ID of the port
- * @param vlanTag address to write the VLAN tag (802.1Q tag) into
- * 
- * Note that this function is documented in the main component
- * header file, IxEthDB.h.
- *
- * @return IX_ETH_DB_SUCCESS if the operation completed successfully
- * or an appropriate error message otherwise
- */
-IX_ETH_DB_PUBLIC 
-IxEthDBStatus ixEthDBVlanTagGet(IxEthDBMacAddr *macAddr, IxEthDBVlanTag *vlanTag)
-{
-    HashNode *searchResult;
-    MacDescriptor *descriptor;
-    
-    IX_ETH_DB_CHECK_REFERENCE(macAddr);
-    
-    IX_ETH_DB_CHECK_REFERENCE(vlanTag);
-    
-    searchResult = ixEthDBSearch(macAddr, IX_ETH_DB_FILTERING_VLAN_RECORD);
-    
-    if (searchResult == NULL)
-    {
-        return IX_ETH_DB_NO_SUCH_ADDR;
-    }
-    
-    descriptor = (MacDescriptor *) searchResult->data;
-        
-    /* get vlan tag */
-    *vlanTag = descriptor->recordData.filteringVlanData.ieee802_1qTag;
-    
-    /* transaction completed */
-    ixEthDBReleaseHashNode(searchResult);
-    
-    return IX_ETH_DB_SUCCESS;
-}
-
-/**
- * @brief adds a VLAN to a port's VLAN membership table
- *
- * @param portID ID of the port
- * @param vlanID VLAN ID to add
- * 
- * Note that this function is documented in the main component
- * header file, IxEthDB.h.
- *
- * @return IX_ETH_DB_SUCCESS if the operation completed successfully
- * or an appropriate error message otherwise
- */
-IX_ETH_DB_PUBLIC 
-IxEthDBStatus ixEthDBPortVlanMembershipAdd(IxEthDBPortId portID, IxEthDBVlanId vlanID)
-{
-    IX_ETH_DB_CHECK_PORT(portID);
-
-    IX_ETH_DB_CHECK_SINGLE_NPE(portID);
-
-    IX_ETH_DB_CHECK_VLAN_ID(vlanID);
-
-    IX_ETH_DB_CHECK_FEATURE(portID, IX_ETH_DB_VLAN_QOS);
-
-    return ixEthDBPortVlanMembershipChange(portID, vlanID, ixEthDBPortInfo[portID].vlanMembership, ADD_VLAN);
-}
-
-/**
- * @brief removes a VLAN from a port's VLAN membership table
- *
- * @param portID ID of the port
- * @param vlanID VLAN ID to remove
- *
- * Note that this function is documented in the main component
- * header file, IxEthDB.h.
- *
- * @return IX_ETH_DB_SUCCESS if the operation completed successfully
- * or an appropriate error message otherwise
- */
-IX_ETH_DB_PUBLIC 
-IxEthDBStatus ixEthDBPortVlanMembershipRemove(IxEthDBPortId portID, IxEthDBVlanId vlanID)
-{
-    IX_ETH_DB_CHECK_PORT(portID);
-
-    IX_ETH_DB_CHECK_SINGLE_NPE(portID);
-
-    IX_ETH_DB_CHECK_FEATURE(portID, IX_ETH_DB_VLAN_QOS);
-
-    IX_ETH_DB_CHECK_VLAN_ID(vlanID);
-
-    /* for safety isolate only the VLAN ID in the tag (the lower 12 bits) */
-    vlanID = vlanID & IX_ETH_DB_802_1Q_VLAN_MASK;
-    
-    /* check we're not asked to remove the default port VID */
-    if (vlanID == IX_ETH_DB_GET_VLAN_ID(ixEthDBPortInfo[portID].vlanTag))
-    {
-        return IX_ETH_DB_NO_PERMISSION;
-    }
-    
-    return ixEthDBPortVlanMembershipChange(portID, vlanID, ixEthDBPortInfo[portID].vlanMembership, REMOVE_VLAN);
-}
-
-/**
- * @brief adds or removes a VLAN range from a port's 
- * VLAN membership table or TTI table
- *
- * @param portID ID of the port
- * @param vlanIDMin start of the VLAN range
- * @param vlanIDMax end of the VLAN range
- * @param table VLAN set to add or remove from
- * @param action ADD_VLAN or REMOVE_VLAN
- *
- * @return IX_ETH_DB_SUCCESS if the operation completed successfully
- * or an appropriate error message otherwise
- *
- * @internal
- */
-IX_ETH_DB_PRIVATE
-IxEthDBStatus ixEthDBPortVlanMembershipRangeChange(IxEthDBPortId portID, IxEthDBVlanId vlanIDMin, IxEthDBVlanId vlanIDMax, IxEthDBVlanSet table, UINT32 action)
-{
-    UINT32 setOffsetMin, setOffsetMax;
-    
-    IX_ETH_DB_CHECK_PORT(portID);
-    
-    IX_ETH_DB_CHECK_SINGLE_NPE(portID);
-    
-    IX_ETH_DB_CHECK_FEATURE(portID, IX_ETH_DB_VLAN_QOS);
-    
-    IX_ETH_DB_CHECK_VLAN_ID(vlanIDMin);
-    
-    IX_ETH_DB_CHECK_VLAN_ID(vlanIDMax);
-    
-    /* for safety isolate only the VLAN ID in the tags (the lower 12 bits) */
-    vlanIDMin = vlanIDMin & IX_ETH_DB_802_1Q_VLAN_MASK;
-    vlanIDMax = vlanIDMax & IX_ETH_DB_802_1Q_VLAN_MASK;
-    
-    /* is this a range? */
-    if (vlanIDMax < vlanIDMin)
-    {
-        return IX_ETH_DB_INVALID_VLAN;
-    }
-    
-    /* check that we're not specifically asked to remove the default port VID */
-    if (action == REMOVE_VLAN && vlanIDMax == vlanIDMin && IX_ETH_DB_GET_VLAN_ID(ixEthDBPortInfo[portID].vlanTag) == vlanIDMin)
-    {
-        return IX_ETH_DB_NO_PERMISSION;
-    }
-    
-    /* compute set offsets */
-    setOffsetMin = VLAN_SET_OFFSET(vlanIDMin);
-    setOffsetMax = VLAN_SET_OFFSET(vlanIDMax);
-
-    /* change VLAN range */
-    for (; vlanIDMin <= vlanIDMax ; vlanIDMin++)
-    {
-        /* change vlan in local membership table */
-        ixEthDBLocalVlanMembershipChange(vlanIDMin, table, action);
-    }
-
-    /* if the range is within one set (max 8 VLANs in one table byte) we can just update that entry in the NPE */
-    if (setOffsetMin == setOffsetMax)
-    {
-        /* send updated entry to NPE */
-        return ixEthDBVlanTableEntryUpdate(portID, setOffsetMin);
-    }
-    else
-    {
-        /* update a zone of the membership/transmit tag info table */
-        return ixEthDBVlanTableRangeUpdate(portID);
-    }
-}
-
-/**
- * @brief adds a VLAN range to a port's VLAN membership table
- *
- * @param portID ID of the port
- * @param vlanIDMin start of the VLAN range
- * @param vlanIDMax end of the VLAN range
- * 
- * Note that this function is documented in the main component
- * header file, IxEthDB.h.
- *
- * @return IX_ETH_DB_SUCCESS if the operation completed successfully
- * or an appropriate error message otherwise
- */
-IX_ETH_DB_PUBLIC 
-IxEthDBStatus ixEthDBPortVlanMembershipRangeAdd(IxEthDBPortId portID, IxEthDBVlanId vlanIDMin, IxEthDBVlanId vlanIDMax)
-{
-    IX_ETH_DB_CHECK_PORT(portID);
-
-    IX_ETH_DB_CHECK_SINGLE_NPE(portID);
-
-    return ixEthDBPortVlanMembershipRangeChange(portID, vlanIDMin, vlanIDMax, ixEthDBPortInfo[portID].vlanMembership, ADD_VLAN);
-}
-
-/**
- * @brief removes a VLAN range from a port's VLAN membership table
- *
- * @param portID ID of the port
- * @param vlanIDMin start of the VLAN range
- * @param vlanIDMax end of the VLAN range
- *
- * Note that this function is documented in the main component
- * header file, IxEthDB.h.
- *
- * @return IX_ETH_DB_SUCCESS if the operation completed successfully
- * or an appropriate error message otherwise
- */
-IX_ETH_DB_PUBLIC 
-IxEthDBStatus ixEthDBPortVlanMembershipRangeRemove(IxEthDBPortId portID, IxEthDBVlanId vlanIDMin, IxEthDBVlanId vlanIDMax)
-{
-    IX_ETH_DB_CHECK_PORT(portID);
-
-    IX_ETH_DB_CHECK_SINGLE_NPE(portID);
-
-    return ixEthDBPortVlanMembershipRangeChange(portID, vlanIDMin, vlanIDMax, ixEthDBPortInfo[portID].vlanMembership, REMOVE_VLAN);
-}
-
-/**
- * @brief sets a port's VLAN membership table or TTI table and
- * updates the NPE VLAN configuration
- *
- * @param portID ID of the port
- * @param portVlanTable port VLAN table to set
- * @param vlanSet new set contents
- *
- * @return IX_ETH_DB_SUCCESS if the operation completed successfully
- * or an appropriate error message otherwise
- *
- * @internal
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBPortVlanTableSet(IxEthDBPortId portID, IxEthDBVlanSet portVlanTable, IxEthDBVlanSet vlanSet)
-{
-    IX_ETH_DB_CHECK_PORT(portID);
-    
-    IX_ETH_DB_CHECK_SINGLE_NPE(portID);
-    
-    IX_ETH_DB_CHECK_FEATURE(portID, IX_ETH_DB_VLAN_QOS);
-    
-    IX_ETH_DB_CHECK_REFERENCE(vlanSet);
-
-    memcpy(portVlanTable, vlanSet, sizeof (IxEthDBVlanSet));
-    
-    return ixEthDBVlanTableRangeUpdate(portID);
-}
-
-/**
- * @brief retireves a port's VLAN membership table or TTI table
- *
- * @param portID ID of the port
- * @param portVlanTable port VLAN table to retrieve
- * @param vlanSet address to 
- *
- * @return IX_ETH_DB_SUCCESS if the operation completed successfully
- * or an appropriate error message otherwise
- *
- * @internal
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBVlanTableGet(IxEthDBPortId portID, IxEthDBVlanSet portVlanTable, IxEthDBVlanSet vlanSet)
-{
-    IX_ETH_DB_CHECK_PORT(portID);
-    
-    IX_ETH_DB_CHECK_SINGLE_NPE(portID);
-    
-    IX_ETH_DB_CHECK_FEATURE(portID, IX_ETH_DB_VLAN_QOS);
-    
-    IX_ETH_DB_CHECK_REFERENCE(vlanSet);
-    
-    memcpy(vlanSet, portVlanTable, sizeof (IxEthDBVlanSet));
-    
-    return IX_ETH_DB_SUCCESS;
-}
-
-/**
- * @brief sets a port's VLAN membership table
- *
- * @param portID ID of the port
- * @param vlanSet new VLAN membership table
- *
- * Note that this function is documented in the main component
- * header file, IxEthDB.h.
- *
- * @return IX_ETH_DB_SUCCESS if the operation completed successfully
- * or an appropriate error message otherwise
- */
-IX_ETH_DB_PUBLIC 
-IxEthDBStatus ixEthDBPortVlanMembershipSet(IxEthDBPortId portID, IxEthDBVlanSet vlanSet)
-{
-    IxEthDBVlanId vlanID;
-
-    IX_ETH_DB_CHECK_PORT(portID);
-    
-    IX_ETH_DB_CHECK_SINGLE_NPE(portID);
-
-    IX_ETH_DB_CHECK_REFERENCE(vlanSet);
-
-    /* set the bit corresponding to the PVID just in case */
-    vlanID = IX_ETH_DB_GET_VLAN_ID(ixEthDBPortInfo[portID].vlanTag);
-    vlanSet[VLAN_SET_OFFSET(vlanID)] |= 1 << VLAN_SET_MASK(vlanID);
-    
-    return ixEthDBPortVlanTableSet(portID, ixEthDBPortInfo[portID].vlanMembership, vlanSet);
-}
-
-/**
- * @brief retrieves a port's VLAN membership table
- *
- * @param portID ID of the port
- * @param vlanSet location to store the port's VLAN membership table
- *
- * Note that this function is documented in the main component
- * header file, IxEthDB.h.
- *
- * @return IX_ETH_DB_SUCCESS if the operation completed successfully
- * or an appropriate error message otherwise
- */
-IX_ETH_DB_PUBLIC 
-IxEthDBStatus ixEthDBPortVlanMembershipGet(IxEthDBPortId portID, IxEthDBVlanSet vlanSet)
-{
-    IX_ETH_DB_CHECK_PORT(portID);
-    
-    IX_ETH_DB_CHECK_SINGLE_NPE(portID);
-    
-    return ixEthDBVlanTableGet(portID, ixEthDBPortInfo[portID].vlanMembership, vlanSet);
-}
-
-/**
- * @brief enables or disables Egress tagging for one VLAN ID
- *
- * @param portID ID of the port
- * @param vlanID VLAN ID to enable or disable Egress tagging on
- * @param enabled true to enable and false to disable tagging
- *
- * Note that this function is documented in the main component
- * header file, IxEthDB.h.
- *
- * @return IX_ETH_DB_SUCCESS if the operation completed successfully
- * or an appropriate error message otherwise
- */
-IX_ETH_DB_PUBLIC 
-IxEthDBStatus ixEthDBEgressVlanEntryTaggingEnabledSet(IxEthDBPortId portID, IxEthDBVlanId vlanID, BOOL enabled)
-{
-    IX_ETH_DB_CHECK_PORT(portID);
-    
-    IX_ETH_DB_CHECK_SINGLE_NPE(portID);
-
-    IX_ETH_DB_CHECK_VLAN_ID(vlanID);
-
-    IX_ETH_DB_CHECK_FEATURE(portID, IX_ETH_DB_VLAN_QOS);
-
-    return ixEthDBPortVlanMembershipChange(portID, vlanID, ixEthDBPortInfo[portID].transmitTaggingInfo, enabled? ADD_VLAN : REMOVE_VLAN);
-}
-
-/**
- * @brief retrieves the Egress tagging status for one VLAN ID
- *
- * @param portID ID of the port
- * @param vlanID VLAN ID to retrieve the tagging status for
- * @param enabled location to store the tagging status
- * (true - tagging enabled, false - tagging disabled)
- *
- * Note that this function is documented in the main component
- * header file, IxEthDB.h.
- *
- * @return IX_ETH_DB_SUCCESS if the operation completed successfully
- * or an appropriate error message otherwise
- */
-IX_ETH_DB_PUBLIC 
-IxEthDBStatus ixEthDBEgressVlanEntryTaggingEnabledGet(IxEthDBPortId portID, IxEthDBVlanId vlanID, BOOL *enabled)
-{
-    IX_ETH_DB_CHECK_PORT(portID);
-    
-    IX_ETH_DB_CHECK_SINGLE_NPE(portID);
-    
-    IX_ETH_DB_CHECK_FEATURE(portID, IX_ETH_DB_VLAN_QOS);
-    
-    IX_ETH_DB_CHECK_REFERENCE(enabled);
-
-    IX_ETH_DB_CHECK_VLAN_ID(vlanID);
-    
-    *enabled = ((ixEthDBPortInfo[portID].transmitTaggingInfo[VLAN_SET_OFFSET(vlanID)] & (1 << VLAN_SET_MASK(vlanID))) != 0);
-    
-    return IX_ETH_DB_SUCCESS;
-}
-
-/**
- * @brief enables or disables Egress VLAN tagging for a VLAN range
- *
- * @param portID ID of the port
- * @param vlanIDMin start of VLAN range
- * @param vlanIDMax end of VLAN range
- * @param enabled true to enable or false to disable VLAN tagging
- *
- * Note that this function is documented in the main component
- * header file, IxEthDB.h.
- *
- * @return IX_ETH_DB_SUCCESS if the operation completed successfully
- * or an appropriate error message otherwise
- */
-IX_ETH_DB_PUBLIC 
-IxEthDBStatus ixEthDBEgressVlanRangeTaggingEnabledSet(IxEthDBPortId portID, IxEthDBVlanId vlanIDMin, IxEthDBVlanId vlanIDMax, BOOL enabled)
-{
-    IX_ETH_DB_CHECK_PORT(portID);
-    
-    IX_ETH_DB_CHECK_SINGLE_NPE(portID);
-    
-    return ixEthDBPortVlanMembershipRangeChange(portID, vlanIDMin, vlanIDMax, ixEthDBPortInfo[portID].transmitTaggingInfo, enabled? ADD_VLAN : REMOVE_VLAN);
-}
-
-/**
- * @brief sets the Egress VLAN tagging table (the Transmit Tagging
- * Information table)
- *
- * @param portID ID of the port
- * @param vlanSet new TTI table
- *
- * Note that this function is documented in the main component
- * header file, IxEthDB.h.
- *
- * @return IX_ETH_DB_SUCCESS if the operation completed successfully
- * or an appropriate error message otherwise
- */
-IX_ETH_DB_PUBLIC 
-IxEthDBStatus ixEthDBEgressVlanTaggingEnabledSet(IxEthDBPortId portID, IxEthDBVlanSet vlanSet)
-{
-    IxEthDBVlanId vlanID;
-
-    IX_ETH_DB_CHECK_PORT(portID);
-    
-    IX_ETH_DB_CHECK_SINGLE_NPE(portID);
-
-    IX_ETH_DB_CHECK_REFERENCE(vlanSet);
-
-    /* set the PVID bit just in case */
-    vlanID = IX_ETH_DB_GET_VLAN_ID(ixEthDBPortInfo[portID].vlanTag);
-    vlanSet[VLAN_SET_OFFSET(vlanID)] |= 1 << VLAN_SET_MASK(vlanID);
-    
-    return ixEthDBPortVlanTableSet(portID, ixEthDBPortInfo[portID].transmitTaggingInfo, vlanSet);
-}
-
-/**
- * @brief retrieves the Egress VLAN tagging table (the Transmit 
- * Tagging Information table)
- *
- * @param portID ID of the port
- * @param vlanSet location to store the port's TTI table
- *
- * Note that this function is documented in the main component
- * header file, IxEthDB.h.
- *
- * @return IX_ETH_DB_SUCCESS if the operation completed successfully
- * or an appropriate error message otherwise
- */
-IX_ETH_DB_PUBLIC 
-IxEthDBStatus ixEthDBEgressVlanTaggingEnabledGet(IxEthDBPortId portID, IxEthDBVlanSet vlanSet)
-{
-    IX_ETH_DB_CHECK_PORT(portID);
-    
-    IX_ETH_DB_CHECK_SINGLE_NPE(portID);
-    
-    return ixEthDBVlanTableGet(portID, ixEthDBPortInfo[portID].transmitTaggingInfo, vlanSet);
-}
-
-/**
- * @brief sends the NPE the updated frame filter and default
- * Ingress tagging
- *
- * @param portID ID of the port
- * 
- * @return IX_ETH_DB_SUCCESS if the operation completed successfully
- * or an appropriate error message otherwise
- *
- * @internal
- */
-IX_ETH_DB_PRIVATE
-IxEthDBStatus ixEthDBIngressVlanModeUpdate(IxEthDBPortId portID)
-{
-    PortInfo *portInfo = &ixEthDBPortInfo[portID];
-    IxNpeMhMessage message;
-    IX_STATUS result;
-
-    FILL_SETRXTAGMODE_MSG(message, portID, portInfo->npeFrameFilter, portInfo->npeTaggingAction);
-    IX_ETHDB_SEND_NPE_MSG(IX_ETH_DB_PORT_ID_TO_NPE(portID), message, result);
-
-    return result;
-}
-
-/**
- * @brief sets the default Ingress tagging behavior
- *
- * @param portID ID of the port
- * @param taggingAction default tagging behavior
- *
- * Note that this function is documented in the main component
- * header file, IxEthDB.h.
- *
- * @return IX_ETH_DB_SUCCESS if the operation completed successfully
- * or an appropriate error message otherwise
- */
-IX_ETH_DB_PUBLIC 
-IxEthDBStatus ixEthDBIngressVlanTaggingEnabledSet(IxEthDBPortId portID, IxEthDBTaggingAction taggingAction)
-{
-    PortInfo *portInfo;
-    
-    IX_ETH_DB_CHECK_PORT(portID);
-    
-    IX_ETH_DB_CHECK_SINGLE_NPE(portID);
-    
-    IX_ETH_DB_CHECK_FEATURE(portID, IX_ETH_DB_VLAN_QOS);
-    
-    portInfo = &ixEthDBPortInfo[portID];
-    
-    if (taggingAction == IX_ETH_DB_PASS_THROUGH)
-    {
-        portInfo->npeTaggingAction = 0x00;
-    }
-    else if (taggingAction == IX_ETH_DB_ADD_TAG)
-    {
-        portInfo->npeTaggingAction = 0x02;
-    }
-    else if (taggingAction == IX_ETH_DB_REMOVE_TAG)
-    {
-        portInfo->npeTaggingAction = 0x01;
-    }
-    else
-    {
-        return IX_ETH_DB_INVALID_ARG;
-    }
-    
-    portInfo->taggingAction = taggingAction;
-    
-    return ixEthDBIngressVlanModeUpdate(portID);
-}
-
-/**
- * @brief retrieves the default Ingress tagging behavior of a port
- *
- * @param portID ID of the port
- * @param taggingAction location to save the default tagging behavior
- * 
- * Note that this function is documented in the main component
- * header file, IxEthDB.h.
- *
- * @return IX_ETH_DB_SUCCESS if the operation completed successfully
- * or an appropriate error message otherwise
- */
-IX_ETH_DB_PUBLIC 
-IxEthDBStatus ixEthDBIngressVlanTaggingEnabledGet(IxEthDBPortId portID, IxEthDBTaggingAction *taggingAction)
-{
-    IX_ETH_DB_CHECK_PORT(portID);
-    
-    IX_ETH_DB_CHECK_SINGLE_NPE(portID);
-    
-    IX_ETH_DB_CHECK_FEATURE(portID, IX_ETH_DB_VLAN_QOS);
-
-    IX_ETH_DB_CHECK_REFERENCE(taggingAction);
-    
-    *taggingAction = ixEthDBPortInfo[portID].taggingAction;
-    
-    return IX_ETH_DB_SUCCESS;
-}
-
-/**
- * @brief sets the Ingress acceptable frame type filter
- *
- * @param portID ID of the port
- * @param frameFilter acceptable frame type filter
- * 
- * Note that this function is documented in the main component
- * header file, IxEthDB.h.
- *
- * @return IX_ETH_DB_SUCCESS if the operation completed successfully
- * or an appropriate error message otherwise
- */
-IX_ETH_DB_PUBLIC 
-IxEthDBStatus ixEthDBAcceptableFrameTypeSet(IxEthDBPortId portID, IxEthDBFrameFilter frameFilter)
-{
-    PortInfo *portInfo;
-    IxEthDBStatus result = IX_ETH_DB_SUCCESS;
-        
-    IX_ETH_DB_CHECK_PORT(portID);
-    
-    IX_ETH_DB_CHECK_SINGLE_NPE(portID);
-    
-    IX_ETH_DB_CHECK_FEATURE(portID, IX_ETH_DB_VLAN_QOS);
-    
-    /* check parameter range 
-       the ORed value of the valid values is 0x7
-       a value having extra bits is invalid */
-    if ((frameFilter | 0x7) != 0x7 || frameFilter == 0)
-    {
-        return IX_ETH_DB_INVALID_ARG;
-    }
-    
-    portInfo = &ixEthDBPortInfo[portID];
-    
-    portInfo->frameFilter    = frameFilter;
-    portInfo->npeFrameFilter = 0; /* allow all by default */
-    
-    /* if accepting priority tagged but not all VLAN tagged
-       set the membership table to contain only VLAN ID 0 
-       hence remove vlans 1-4094 and add VLAN ID 0 */
-    if (((frameFilter & IX_ETH_DB_PRIORITY_TAGGED_FRAMES) != 0)
-        && ((frameFilter & IX_ETH_DB_VLAN_TAGGED_FRAMES) == 0))
-    {
-        result = ixEthDBPortVlanMembershipRangeChange(portID, 
-            1, IX_ETH_DB_802_1Q_MAX_VLAN_ID, portInfo->vlanMembership, REMOVE_VLAN);
-
-        if (result == IX_ETH_DB_SUCCESS)
-        {
-            ixEthDBLocalVlanMembershipChange(0, portInfo->vlanMembership, ADD_VLAN);
-            result = ixEthDBVlanTableRangeUpdate(portID);
-        }
-    }
-    
-    /* untagged only? */
-    if (frameFilter == IX_ETH_DB_UNTAGGED_FRAMES)
-    {
-        portInfo->npeFrameFilter = 0x01;
-    }
-    
-    /* tagged only? */
-    if ((frameFilter & IX_ETH_DB_UNTAGGED_FRAMES) == 0)
-    {
-        portInfo->npeFrameFilter = 0x02;
-    }
-
-    if (result == IX_ETH_DB_SUCCESS)
-    {
-        result = ixEthDBIngressVlanModeUpdate(portID);
-    }
-
-    return result;
-}
-
-/**
- * @brief retrieves the acceptable frame type filter for a port
- *
- * @param portID ID of the port
- * @param frameFilter location to store the frame filter
- *
- * Note that this function is documented in the main component
- * header file, IxEthDB.h.
- *
- * @return IX_ETH_DB_SUCCESS if the operation completed successfully
- * or an appropriate error message otherwise
- */
-IX_ETH_DB_PUBLIC 
-IxEthDBStatus ixEthDBAcceptableFrameTypeGet(IxEthDBPortId portID, IxEthDBFrameFilter *frameFilter)
-{
-    IX_ETH_DB_CHECK_PORT(portID);
-    
-    IX_ETH_DB_CHECK_SINGLE_NPE(portID);
-    
-    IX_ETH_DB_CHECK_FEATURE(portID, IX_ETH_DB_VLAN_QOS);
-    
-    IX_ETH_DB_CHECK_REFERENCE(frameFilter);
-    
-    *frameFilter = ixEthDBPortInfo[portID].frameFilter;
-    
-    return IX_ETH_DB_SUCCESS;
-}
-
-/**
- * @brief sends an NPE the updated configuration related
- * to one QoS priority (associated traffic class and AQM mapping)
- *
- * @param portID ID of the port
- * @param classIndex QoS priority (traffic class index)
- *
- * @return IX_ETH_DB_SUCCESS if the operation completed successfully
- * or an appropriate error message otherwise
- *
- * @internal
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBUpdateTrafficClass(IxEthDBPortId portID, UINT32 classIndex)
-{
-    IxNpeMhMessage message;
-    IX_STATUS result;
-
-    UINT32 trafficClass = ixEthDBPortInfo[portID].priorityTable[classIndex];
-    UINT32 aqmQueue     = ixEthDBPortInfo[portID].ixEthDBTrafficClassAQMAssignments[trafficClass];
-    
-    FILL_SETRXQOSENTRY(message, IX_ETH_DB_PORT_ID_TO_NPE_LOGICAL_ID(portID), classIndex, trafficClass, aqmQueue);
-    
-    IX_ETHDB_SEND_NPE_MSG(IX_ETH_DB_PORT_ID_TO_NPE(portID), message, result);
-    
-    return result;
-}
-
-/**
- * @brief sets the priority mapping table
- *
- * @param portID ID of the port
- * @param priorityTable new priority mapping table
- *
- * Note that this function is documented in the main component
- * header file, IxEthDB.h.
- *
- * @return IX_ETH_DB_SUCCESS if the operation completed successfully
- * or an appropriate error message otherwise
- */
-IX_ETH_DB_PUBLIC 
-IxEthDBStatus ixEthDBPriorityMappingTableSet(IxEthDBPortId portID, IxEthDBPriorityTable priorityTable)
-{
-    UINT32 classIndex;
-    
-    IX_ETH_DB_CHECK_PORT(portID);
-    
-    IX_ETH_DB_CHECK_SINGLE_NPE(portID);
-    
-    IX_ETH_DB_CHECK_FEATURE(portID, IX_ETH_DB_VLAN_QOS);
-    
-    IX_ETH_DB_CHECK_REFERENCE(priorityTable);
-           
-    for (classIndex = 0 ; classIndex < IX_IEEE802_1Q_QOS_PRIORITY_COUNT ; classIndex++)
-    {
-        /* check range */
-        if (priorityTable[classIndex] >= ixEthDBPortInfo[portID].ixEthDBTrafficClassCount)
-        {
-            return IX_ETH_DB_INVALID_PRIORITY;
-        }
-    }
-    
-    /* set new traffic classes */
-    for (classIndex = 0 ; classIndex < IX_IEEE802_1Q_QOS_PRIORITY_COUNT ; classIndex++)
-    {
-        ixEthDBPortInfo[portID].priorityTable[classIndex] = priorityTable[classIndex];
-        
-        if (ixEthDBUpdateTrafficClass(portID, classIndex) != IX_ETH_DB_SUCCESS)
-        {
-            return IX_ETH_DB_FAIL;
-        }
-    }
-    
-    return IX_ETH_DB_SUCCESS;
- }
-
-/**
- * @brief retrieves a port's priority mapping table
- *
- * @param portID ID of the port
- * @param priorityTable location to store the priority table
- *
- * Note that this function is documented in the main component
- * header file, IxEthDB.h.
- *
- * @return IX_ETH_DB_SUCCESS if the operation completed successfully
- * or an appropriate error message otherwise
- */
-IX_ETH_DB_PUBLIC 
-IxEthDBStatus ixEthDBPriorityMappingTableGet(IxEthDBPortId portID, IxEthDBPriorityTable priorityTable)
-{
-    IX_ETH_DB_CHECK_PORT(portID);
-    
-    IX_ETH_DB_CHECK_SINGLE_NPE(portID);
-    
-    IX_ETH_DB_CHECK_FEATURE(portID, IX_ETH_DB_VLAN_QOS);
-    
-    IX_ETH_DB_CHECK_REFERENCE(priorityTable);
-    
-    memcpy(priorityTable, ixEthDBPortInfo[portID].priorityTable, sizeof (IxEthDBPriorityTable));
-    
-    return IX_ETH_DB_SUCCESS;
-}
-
-/**
- * @brief sets one QoS priority => traffic class mapping
- *
- * @param portID ID of the port
- * @param userPriority QoS (user) priority
- * @param trafficClass associated traffic class
- *
- * Note that this function is documented in the main component
- * header file, IxEthDB.h.
- *
- * @return IX_ETH_DB_SUCCESS if the operation completed successfully
- * or an appropriate error message otherwise
- */
-IX_ETH_DB_PUBLIC 
-IxEthDBStatus ixEthDBPriorityMappingClassSet(IxEthDBPortId portID, IxEthDBPriority userPriority, IxEthDBPriority trafficClass)
-{
-    IX_ETH_DB_CHECK_PORT(portID);
-    
-    IX_ETH_DB_CHECK_SINGLE_NPE(portID);
-    
-    IX_ETH_DB_CHECK_FEATURE(portID, IX_ETH_DB_VLAN_QOS);
-
-    /* check ranges for userPriority and trafficClass */
-    if (userPriority >= IX_IEEE802_1Q_QOS_PRIORITY_COUNT || trafficClass >= ixEthDBPortInfo[portID].ixEthDBTrafficClassCount)
-    {
-        return IX_ETH_DB_INVALID_PRIORITY;
-    }
-    
-    ixEthDBPortInfo[portID].priorityTable[userPriority] = trafficClass;
-    
-    return ixEthDBUpdateTrafficClass(portID, userPriority);
-}
-
-/**
- * @brief retrieves one QoS priority => traffic class mapping
- *
- * @param portID ID of the port
- * @param userPriority QoS (user) priority
- * @param trafficClass location to store the associated traffic class
- * 
- * Note that this function is documented in the main component
- * header file, IxEthDB.h.
- *
- * @return IX_ETH_DB_SUCCESS if the operation completed successfully
- * or an appropriate error message otherwise
- */
-IX_ETH_DB_PUBLIC 
-IxEthDBStatus ixEthDBPriorityMappingClassGet(IxEthDBPortId portID, IxEthDBPriority userPriority, IxEthDBPriority *trafficClass)
-{
-    IX_ETH_DB_CHECK_PORT(portID);
-    
-    IX_ETH_DB_CHECK_SINGLE_NPE(portID);
-    
-    IX_ETH_DB_CHECK_FEATURE(portID, IX_ETH_DB_VLAN_QOS);
-    
-    IX_ETH_DB_CHECK_REFERENCE(trafficClass);
-    
-    /* check userPriority range */
-    if (userPriority >= IX_IEEE802_1Q_QOS_PRIORITY_COUNT)
-    {
-        return IX_ETH_DB_INVALID_PRIORITY;
-    }
-    
-    *trafficClass = ixEthDBPortInfo[portID].priorityTable[userPriority];
-    
-    return IX_ETH_DB_SUCCESS;
-}
-
-/**
- * @brief enables or disables the source port extraction
- * from the VLAN TPID field
- *
- * @param portID ID of the port
- * @param enable true to enable or false to disable
- *
- * Note that this function is documented in the main component
- * header file, IxEthDB.h.
- *
- * @return IX_ETH_DB_SUCCESS if the operation completed successfully
- * or an appropriate error message otherwise
- */
-IX_ETH_DB_PUBLIC 
-IxEthDBStatus ixEthDBVlanPortExtractionEnable(IxEthDBPortId portID, BOOL enable)
-{
-    IxNpeMhMessage message;
-    IX_STATUS result;
-
-    IX_ETH_DB_CHECK_PORT(portID);
-    
-    IX_ETH_DB_CHECK_SINGLE_NPE(portID);
-    
-    IX_ETH_DB_CHECK_FEATURE(portID, IX_ETH_DB_VLAN_QOS);
-
-    FILL_SETPORTIDEXTRACTIONMODE(message, portID, enable);
-
-    IX_ETHDB_SEND_NPE_MSG(IX_ETH_DB_PORT_ID_TO_NPE(portID), message, result);
-    
-    return result;
-}
diff --git a/drivers/net/npe/IxEthDBWiFi.c b/drivers/net/npe/IxEthDBWiFi.c
deleted file mode 100644
index 44edd47f2f..0000000000
--- a/drivers/net/npe/IxEthDBWiFi.c
+++ /dev/null
@@ -1,456 +0,0 @@
-/**
- * @file IxEthDBAPI.c
- *
- * @brief Implementation of the public API
- * 
- * @par
- * IXP400 SW Release version 2.0
- * 
- * -- Copyright Notice --
- * 
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- * 
- * @par
- * SPDX-License-Identifier:	BSD-3-Clause
- * @par
- * -- End of Copyright Notice --
- */
-
-#include "IxEthDB_p.h"
-
-/* forward prototypes */
-IX_ETH_DB_PUBLIC
-MacTreeNode *ixEthDBGatewaySelect(MacTreeNode *stations);
-
-/**
- * @brief sets the BBSID value for the WiFi header conversion feature
- *
- * @param portID ID of the port
- * @param bbsid pointer to the 6-byte BBSID value
- *
- * Note that this function is documented in the main component
- * header file, IxEthDB.h.
- *
- * @return IX_ETH_DB_SUCCESS if the operation completed successfully
- * or an appropriate error message otherwise
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBWiFiBBSIDSet(IxEthDBPortId portID, IxEthDBMacAddr *bbsid)
-{
-    IxNpeMhMessage message;
-    IX_STATUS result;
-    
-    IX_ETH_DB_CHECK_PORT(portID);
-    
-    IX_ETH_DB_CHECK_SINGLE_NPE(portID);
-    
-    IX_ETH_DB_CHECK_FEATURE(portID, IX_ETH_DB_WIFI_HEADER_CONVERSION);
- 
-    IX_ETH_DB_CHECK_REFERENCE(bbsid);
-    
-    memcpy(ixEthDBPortInfo[portID].bbsid, bbsid, sizeof (IxEthDBMacAddr));
-
-    FILL_SETBBSID_MSG(message, portID, bbsid);
-
-    IX_ETHDB_SEND_NPE_MSG(IX_ETH_DB_PORT_ID_TO_NPE(portID), message, result);
-    
-    return result;
-}
-
-/**
- * @brief updates the Frame Control and Duration/ID WiFi header
- * conversion parameters in an NPE
- *
- * @param portID ID of the port
- *
- * This function will send a message to the NPE updating the 
- * frame conversion parameters for 802.3 => 802.11 header conversion.
- *
- * @return IX_ETH_DB_SUCCESS if the operation completed successfully
- * or IX_ETH_DB_FAIL otherwise
- *
- * @internal
- */
-IX_ETH_DB_PRIVATE
-IxEthDBStatus ixEthDBWiFiFrameControlDurationIDUpdate(IxEthDBPortId portID)
-{
-    IxNpeMhMessage message;
-    IX_STATUS result;
-
-    FILL_SETFRAMECONTROLDURATIONID(message, portID, ixEthDBPortInfo[portID].frameControlDurationID);
-    
-    IX_ETHDB_SEND_NPE_MSG(IX_ETH_DB_PORT_ID_TO_NPE(portID), message, result);
-    
-    return result;
-}
-
-/**
- * @brief sets the Duration/ID WiFi frame header conversion parameter
- *
- * @param portID ID of the port
- * @param durationID 16-bit value containing the new Duration/ID parameter
- *
- * Note that this function is documented in the main component
- * header file, IxEthDB.h.
- *
- * @return IX_ETH_DB_SUCCESS if the operation completed successfully
- * or an appropriate error message otherwise
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBWiFiDurationIDSet(IxEthDBPortId portID, UINT16 durationID)
-{
-    IX_ETH_DB_CHECK_PORT(portID);
-    
-    IX_ETH_DB_CHECK_SINGLE_NPE(portID);
-    
-    IX_ETH_DB_CHECK_FEATURE(portID, IX_ETH_DB_WIFI_HEADER_CONVERSION);
-
-    ixEthDBPortInfo[portID].frameControlDurationID = (ixEthDBPortInfo[portID].frameControlDurationID & 0xFFFF0000) | durationID;
-    
-    return ixEthDBWiFiFrameControlDurationIDUpdate(portID);
-}
-
-/**
- * @brief sets the Frame Control WiFi frame header conversion parameter
- *
- * @param portID ID of the port
- * @param durationID 16-bit value containing the new Frame Control parameter
- *
- * Note that this function is documented in the main component
- * header file, IxEthDB.h.
- *
- * @return IX_ETH_DB_SUCCESS if the operation completed successfully
- * or an appropriate error message otherwise
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBWiFiFrameControlSet(IxEthDBPortId portID, UINT16 frameControl)
-{
-    IX_ETH_DB_CHECK_PORT(portID);
-    
-    IX_ETH_DB_CHECK_SINGLE_NPE(portID);
-    
-    IX_ETH_DB_CHECK_FEATURE(portID, IX_ETH_DB_WIFI_HEADER_CONVERSION);
-
-    ixEthDBPortInfo[portID].frameControlDurationID = (ixEthDBPortInfo[portID].frameControlDurationID & 0xFFFF) | (frameControl << 16); 
-    
-    return ixEthDBWiFiFrameControlDurationIDUpdate(portID);
-}
-
-/**
- * @brief removes a WiFi header conversion record
- *
- * @param portID ID of the port
- * @param macAddr MAC address of the record to remove
- *
- * Note that this function is documented in the main
- * component header file, IxEthDB.h.
- *
- * @return IX_ETH_DB_SUCCESS if the operation completed
- * successfully or an appropriate error message otherwise
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBWiFiEntryRemove(IxEthDBPortId portID, IxEthDBMacAddr *macAddr)
-{
-    MacDescriptor recordTemplate;
-    
-    IX_ETH_DB_CHECK_PORT(portID);
-    
-    IX_ETH_DB_CHECK_SINGLE_NPE(portID);
-    
-    IX_ETH_DB_CHECK_REFERENCE(macAddr);
-    
-    IX_ETH_DB_CHECK_FEATURE(portID, IX_ETH_DB_WIFI_HEADER_CONVERSION);
-    
-    memcpy(recordTemplate.macAddress, macAddr, sizeof (IxEthDBMacAddr));
-    
-    recordTemplate.type   = IX_ETH_DB_WIFI_RECORD;
-    recordTemplate.portID = portID;
-    
-    return ixEthDBRemove(&recordTemplate, NULL);
-}
-
-/**
- * @brief adds a WiFi header conversion record
- *
- * @param portID ID of the port
- * @param macAddr MAC address of the record to add
- * @param gatewayMacAddr address of the gateway (or
- * NULL if this is a station record)
- *
- * This function adds a record of type AP_TO_AP (gateway is not NULL)
- * or AP_TO_STA (gateway is NULL) in the main database as a 
- * WiFi header conversion record.
- *
- * @return IX_ETH_DB_SUCCESS if the operation completed
- * successfully or an appropriate error message otherwise
- *
- * @internal
- */
-IX_ETH_DB_PRIVATE
-IxEthDBStatus ixEthDBWiFiEntryAdd(IxEthDBPortId portID, IxEthDBMacAddr *macAddr, IxEthDBMacAddr *gatewayMacAddr)
-{
-    MacDescriptor recordTemplate;
-
-    IX_ETH_DB_CHECK_PORT(portID);
-
-    IX_ETH_DB_CHECK_SINGLE_NPE(portID);
-
-    IX_ETH_DB_CHECK_REFERENCE(macAddr);
-    
-    IX_ETH_DB_CHECK_FEATURE(portID, IX_ETH_DB_WIFI_HEADER_CONVERSION);
-
-    memcpy(recordTemplate.macAddress, macAddr, sizeof (IxEthDBMacAddr));
-    
-    recordTemplate.type   = IX_ETH_DB_WIFI_RECORD;
-    recordTemplate.portID = portID;
-    
-    if (gatewayMacAddr != NULL)
-    {
-        memcpy(recordTemplate.recordData.wifiData.gwMacAddress, gatewayMacAddr, sizeof (IxEthDBMacAddr));
-        
-        recordTemplate.recordData.wifiData.type = IX_ETH_DB_WIFI_AP_TO_AP;
-    }
-    else
-    {
-        memset(recordTemplate.recordData.wifiData.gwMacAddress, 0, sizeof (IxEthDBMacAddr));
-
-        recordTemplate.recordData.wifiData.type = IX_ETH_DB_WIFI_AP_TO_STA;
-    }
-    
-    return ixEthDBAdd(&recordTemplate, NULL);
-}
-
-/**
- * @brief adds a WiFi header conversion record
- *
- * @param portID ID of the port
- * @param macAddr MAC address of the record to add
- * @param gatewayMacAddr address of the gateway 
- *
- * This function adds a record of type AP_TO_AP
- * in the main database as a WiFi header conversion record.
- *
- * This is simply a wrapper over @ref ixEthDBWiFiEntryAdd().
- *
- * Note that this function is documented in the main
- * component header file, IxEthDB.h.
- *
- * @return IX_ETH_DB_SUCCESS if the operation completed
- * successfully or an appropriate error message otherwise
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBWiFiAccessPointEntryAdd(IxEthDBPortId portID, IxEthDBMacAddr *macAddr, IxEthDBMacAddr *gatewayMacAddr)
-{
-    IX_ETH_DB_CHECK_REFERENCE(gatewayMacAddr);
-
-    return ixEthDBWiFiEntryAdd(portID, macAddr, gatewayMacAddr);
-}
-
-/**
- * @brief adds a WiFi header conversion record
- *
- * @param portID ID of the port
- * @param macAddr MAC address of the record to add
- *
- * This function adds a record of type AP_TO_STA
- * in the main database as a WiFi header conversion record.
- *
- * This is simply a wrapper over @ref ixEthDBWiFiEntryAdd().
- *
- * Note that this function is documented in the main
- * component header file, IxEthDB.h.
- *
- * @return IX_ETH_DB_SUCCESS if the operation completed
- * successfully or an appropriate error message otherwise
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBWiFiStationEntryAdd(IxEthDBPortId portID, IxEthDBMacAddr *macAddr)
-{
-    return ixEthDBWiFiEntryAdd(portID, macAddr, NULL);
-}
-
-/**
- * @brief selects a set of gateways from a tree of 
- * WiFi header conversion records
- *
- * @param stations binary tree containing pointers to WiFi header
- * conversion records
- *
- * This function browses through the input binary tree, identifies
- * records of type AP_TO_AP, clones these records and appends them
- * to a vine (a single right-branch binary tree) which is returned
- * as result. A maximum of MAX_GW_SIZE entries containing gateways
- * will be cloned from the original tree.
- *
- * @return vine (linear binary tree) containing record
- * clones of AP_TO_AP type, which have a gateway field
- *
- * @internal
- */
-IX_ETH_DB_PUBLIC
-MacTreeNode *ixEthDBGatewaySelect(MacTreeNode *stations)
-{
-    MacTreeNodeStack *stack;
-    MacTreeNode *gateways, *insertionPlace;
-    UINT32 gwIndex = 1; /* skip the empty root */
-    
-    if (stations == NULL)
-    {
-        return NULL;
-    }
-
-    stack = ixOsalCacheDmaMalloc(sizeof (MacTreeNodeStack));
-
-    if (stack == NULL)
-    {
-        ERROR_LOG("DB: (WiFi) failed to allocate the node stack for gateway tree linearization, out of memory?\n");
-        return NULL;
-    }
-    
-    /* initialize root node */
-    gateways = insertionPlace = NULL;
-        
-    /* start browsing the station tree */
-    NODE_STACK_INIT(stack);
-    
-    /* initialize stack by pushing the tree root at offset 0 */
-    NODE_STACK_PUSH(stack, stations, 0);
-    
-    while (NODE_STACK_NONEMPTY(stack))
-    {
-        MacTreeNode *node;
-        UINT32 offset;
-       
-        NODE_STACK_POP(stack, node, offset);
-
-        /* we can store maximum 31 (32 total, 1 empty root) entries in the gateway tree */
-        if (offset > (MAX_GW_SIZE - 1)) break;
-        
-        /* check if this record has a gateway address */
-        if (node->descriptor != NULL && node->descriptor->recordData.wifiData.type == IX_ETH_DB_WIFI_AP_TO_AP)
-        {
-            /* found a record, create an insertion place */
-            if (insertionPlace != NULL)
-            {
-                insertionPlace->right = ixEthDBAllocMacTreeNode();
-                insertionPlace        = insertionPlace->right;
-            }
-            else
-            {
-                gateways       = ixEthDBAllocMacTreeNode();
-                insertionPlace = gateways;
-            }
-
-            if (insertionPlace == NULL)
-            {
-                /* no nodes left, bail out with what we have */
-                ixOsalCacheDmaFree(stack);
-                return gateways;
-            }
-            
-            /* clone the original record for the gateway tree */
-            insertionPlace->descriptor = ixEthDBCloneMacDescriptor(node->descriptor);
-            
-            /* insert and update the offset in the original record */
-            node->descriptor->recordData.wifiData.gwAddressIndex = gwIndex++;
-        }
-        
-        /* browse the tree */
-        if (node->left != NULL)
-        {
-            NODE_STACK_PUSH(stack, node->left, LEFT_CHILD_OFFSET(offset));
-        }
-
-        if (node->right != NULL)
-        {
-            NODE_STACK_PUSH(stack, node->right, RIGHT_CHILD_OFFSET(offset));
-        }
-    }
-    
-    ixOsalCacheDmaFree(stack);
-    return gateways;    
-}
-
-/**
- * @brief downloads the WiFi header conversion table to an NPE
- *
- * @param portID ID of the port
- *
- * This function prepares the WiFi header conversion tables and
- * downloads them to the specified NPE port.
- *
- * The header conversion tables consist in the main table of
- * addresses and the secondary table of gateways. AP_TO_AP records
- * from the first table contain index fields into the second table
- * for gateway selection.
- *
- * Note that this function is documented in the main component
- * header file, IxEthDB.h.
- *
- * @return IX_ETH_DB_SUCCESS if the operation completed successfully
- * or an appropriate error message otherwise
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBWiFiConversionTableDownload(IxEthDBPortId portID)
-{
-    IxEthDBPortMap query;
-    MacTreeNode *stations = NULL, *gateways = NULL, *gateway = NULL;
-    IxNpeMhMessage message;
-    PortInfo *portInfo;
-    IX_STATUS result;
-
-    IX_ETH_DB_CHECK_PORT(portID);
-
-    IX_ETH_DB_CHECK_SINGLE_NPE(portID);
-    
-    IX_ETH_DB_CHECK_FEATURE(portID, IX_ETH_DB_WIFI_HEADER_CONVERSION);
-
-    portInfo = &ixEthDBPortInfo[portID];
-   
-    SET_DEPENDENCY_MAP(query, portID);
-    
-    ixEthDBUpdateLock();
-
-    stations = ixEthDBQuery(NULL, query, IX_ETH_DB_WIFI_RECORD, MAX_ELT_SIZE);
-    gateways = ixEthDBGatewaySelect(stations);
-    
-    /* clean up gw area */
-    memset((void *) portInfo->updateMethod.npeGwUpdateZone, FULL_GW_BYTE_SIZE, 0);
-
-    /* write all gateways */
-    gateway = gateways;
-
-    while (gateway != NULL)
-    {
-        ixEthDBNPEGatewayNodeWrite((void *) (((UINT32) portInfo->updateMethod.npeGwUpdateZone) 
-            + gateway->descriptor->recordData.wifiData.gwAddressIndex * ELT_ENTRY_SIZE), 
-            gateway);
-
-        gateway = gateway->right;
-    }
-
-    /* free the gateway tree */
-    if (gateways != NULL)
-    {
-        ixEthDBFreeMacTreeNode(gateways);
-    }
-
-    FILL_SETAPMACTABLE_MSG(message, 
-        IX_OSAL_MMU_VIRT_TO_PHYS(portInfo->updateMethod.npeGwUpdateZone));
-
-    IX_ETHDB_SEND_NPE_MSG(IX_ETH_DB_PORT_ID_TO_NPE(portID), message, result);
-
-    if (result == IX_SUCCESS)
-    {
-        /* update the main tree (the stations tree) */
-        portInfo->updateMethod.searchTree = stations;
-        
-        result = ixEthDBNPEUpdateHandler(portID, IX_ETH_DB_WIFI_RECORD);
-    }
-
-    ixEthDBUpdateUnlock();
-
-    return result;
-}
diff --git a/drivers/net/npe/IxEthMii.c b/drivers/net/npe/IxEthMii.c
deleted file mode 100644
index 27f3548ce0..0000000000
--- a/drivers/net/npe/IxEthMii.c
+++ /dev/null
@@ -1,473 +0,0 @@
-/**
- * @file IxEthMii.c
- *
- * @author Intel Corporation
- * @date
- *
- * @brief  MII control functions
- *
- * Design Notes:
- *
- * 
- * @par
- * IXP400 SW Release version 2.0
- * 
- * -- Copyright Notice --
- * 
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- * 
- * @par
- * SPDX-License-Identifier:	BSD-3-Clause
- * @par
- * -- End of Copyright Notice --
- */
-
-#include "IxOsal.h"
-
-#include "IxEthAcc.h"
-#include "IxEthMii_p.h"
-
-#ifdef __wince
-#include "IxOsPrintf.h"
-#endif
-
-/* Array to store the phy IDs of the discovered phys */
-PRIVATE UINT32 ixEthMiiPhyId[IXP425_ETH_ACC_MII_MAX_ADDR];
-
-/*********************************************************
- *
- * Scan for PHYs on the MII bus. This function returns
- * an array of booleans, one for each PHY address.
- * If a PHY is found at a particular address, the
- * corresponding entry in the array is set to true.
- *
- */
-
-PUBLIC IX_STATUS
-ixEthMiiPhyScan(BOOL phyPresent[], UINT32 maxPhyCount)
-{
-    UINT32 i;
-    UINT16 regval, regvalId1, regvalId2;
-
-    /*Search for PHYs on the MII*/
-    /*Search for existant phys on the MDIO bus*/
-
-    if ((phyPresent == NULL) || 
-	(maxPhyCount > IXP425_ETH_ACC_MII_MAX_ADDR))
-    {
-	return IX_FAIL;
-    }
-
-    /* fill the array */
-    for(i=0;
-        i<IXP425_ETH_ACC_MII_MAX_ADDR;
-	i++)
-    {
-	phyPresent[i] = false;
-    }
-
-    /* iterate through the PHY addresses */
-    for(i=0;
-	maxPhyCount > 0 && i<IXP425_ETH_ACC_MII_MAX_ADDR;
-	i++)
-    {
-	ixEthMiiPhyId[i] = IX_ETH_MII_INVALID_PHY_ID;
-	if(ixEthAccMiiReadRtn(i,
-			      IX_ETH_MII_CTRL_REG,
-			      &regval) == IX_ETH_ACC_SUCCESS)
-	{
-	    if((regval & 0xffff) != 0xffff)
-	    {
-		maxPhyCount--;
-		/*Need to read the register twice here to flush PHY*/
-		ixEthAccMiiReadRtn(i,  IX_ETH_MII_PHY_ID1_REG, &regvalId1);
-		ixEthAccMiiReadRtn(i,  IX_ETH_MII_PHY_ID1_REG, &regvalId1);
-		ixEthAccMiiReadRtn(i,  IX_ETH_MII_PHY_ID2_REG, &regvalId2);
-		ixEthMiiPhyId[i] = (regvalId1 << IX_ETH_MII_REG_SHL) | regvalId2;
-		if ((ixEthMiiPhyId[i] == IX_ETH_MII_KS8995_PHY_ID)
-		    || (ixEthMiiPhyId[i] == IX_ETH_MII_LXT971_PHY_ID)
-		    || (ixEthMiiPhyId[i] == IX_ETH_MII_LXT972_PHY_ID)
-		    || (ixEthMiiPhyId[i] == IX_ETH_MII_LXT973_PHY_ID)
-		    || (ixEthMiiPhyId[i] == IX_ETH_MII_LXT973A3_PHY_ID)
-		    || (ixEthMiiPhyId[i] == IX_ETH_MII_LXT9785_PHY_ID)
-		    )
-		{
-		    /* supported phy */
-		    phyPresent[i] = true;
-		} /* end of if(ixEthMiiPhyId) */
-		else
-		{
-		    if (ixEthMiiPhyId[i] != IX_ETH_MII_INVALID_PHY_ID)
-		    {
-			/* unsupported phy */
-                        ixOsalLog (IX_OSAL_LOG_LVL_ERROR,
-                                   IX_OSAL_LOG_DEV_STDOUT,
-				    "ixEthMiiPhyScan : unexpected Mii PHY ID %8.8x\n", 
-				    ixEthMiiPhyId[i], 2, 3, 4, 5, 6);
-			ixEthMiiPhyId[i] = IX_ETH_MII_UNKNOWN_PHY_ID;
-			phyPresent[i] = true;
-		    }
-		} 
-	    }
-	}
-    }
-    return IX_SUCCESS;
-}
-
-/************************************************************
- *
- * Configure the PHY at the specified address
- *
- */
-PUBLIC IX_STATUS
-ixEthMiiPhyConfig(UINT32 phyAddr,
-		  BOOL speed100,
-		  BOOL fullDuplex,
-		  BOOL autonegotiate)
-{
-    UINT16 regval=0;
-
-    /* parameter check */
-    if ((phyAddr < IXP425_ETH_ACC_MII_MAX_ADDR) &&
-	(ixEthMiiPhyId[phyAddr] != IX_ETH_MII_INVALID_PHY_ID))
-    {
-    /*
-     * set the control register
-     */
-	if(autonegotiate)
-	{
-	    regval |= IX_ETH_MII_CR_AUTO_EN | IX_ETH_MII_CR_RESTART;
-	}
-	else
-	{
-	    if(speed100)
-	    {
-		regval |= IX_ETH_MII_CR_100;
-	    }
-	    if(fullDuplex)
-	    {
-		regval |= IX_ETH_MII_CR_FDX;
-	    }
-	} /* end of if-else() */
-	if (ixEthAccMiiWriteRtn(phyAddr, 
-				IX_ETH_MII_CTRL_REG, 
-				regval) == IX_ETH_ACC_SUCCESS)
-	{
-	    return IX_SUCCESS;
-	}
-    } /* end of if(phyAddr) */
-    return IX_FAIL;
-}
-
-/******************************************************************
- *
- *  Enable the PHY Loopback at the specified address
- */
-PUBLIC IX_STATUS
-ixEthMiiPhyLoopbackEnable (UINT32 phyAddr)
-{
-  UINT16 regval ;  
-
-  if ((phyAddr < IXP425_ETH_ACC_MII_MAX_ADDR) && 
-      (IX_ETH_MII_INVALID_PHY_ID != ixEthMiiPhyId[phyAddr]))
-  {
-      /* read/write the control register */
-      if(ixEthAccMiiReadRtn (phyAddr,
-			     IX_ETH_MII_CTRL_REG, 
-			     &regval) 
-	 == IX_ETH_ACC_SUCCESS)
-      {
-	  if(ixEthAccMiiWriteRtn (phyAddr, 
-				  IX_ETH_MII_CTRL_REG, 
-				  regval | IX_ETH_MII_CR_LOOPBACK)
-	     == IX_ETH_ACC_SUCCESS)
-	  {
-	      return IX_SUCCESS;
-	  }
-      }
-  }
-  return IX_FAIL;
-}
-
-/******************************************************************
- *
- *  Disable the PHY Loopback at the specified address
- */
-PUBLIC IX_STATUS
-ixEthMiiPhyLoopbackDisable (UINT32 phyAddr)
-{
-  UINT16 regval ;  
-
-  if ((phyAddr < IXP425_ETH_ACC_MII_MAX_ADDR) && 
-      (IX_ETH_MII_INVALID_PHY_ID != ixEthMiiPhyId[phyAddr]))
-  {
-      /* read/write the control register */
-      if(ixEthAccMiiReadRtn (phyAddr,
-			     IX_ETH_MII_CTRL_REG, 
-			     &regval) 
-	 == IX_ETH_ACC_SUCCESS)
-      {
-	  if(ixEthAccMiiWriteRtn (phyAddr, 
-				  IX_ETH_MII_CTRL_REG, 
-				  regval & (~IX_ETH_MII_CR_LOOPBACK))
-	     == IX_ETH_ACC_SUCCESS)
-	  {
-	      return IX_SUCCESS;
-	  }
-      }
-  }
-  return IX_FAIL;
-}
-
-/******************************************************************
- *
- *  Reset the PHY at the specified address
- */
-PUBLIC IX_STATUS
-ixEthMiiPhyReset(UINT32 phyAddr)
-{
-    UINT32 timeout;
-    UINT16 regval;
-
-    if ((phyAddr < IXP425_ETH_ACC_MII_MAX_ADDR) &&
-	(ixEthMiiPhyId[phyAddr] != IX_ETH_MII_INVALID_PHY_ID))
-    {
-	if ((ixEthMiiPhyId[phyAddr] == IX_ETH_MII_LXT971_PHY_ID)	||
-	    (ixEthMiiPhyId[phyAddr] == IX_ETH_MII_LXT972_PHY_ID)	||
-	    (ixEthMiiPhyId[phyAddr] == IX_ETH_MII_LXT973_PHY_ID)	||
-	    (ixEthMiiPhyId[phyAddr] == IX_ETH_MII_LXT973A3_PHY_ID)	||
-		(ixEthMiiPhyId[phyAddr] == IX_ETH_MII_LXT9785_PHY_ID)
-	    )
-	{
-	    /* use the control register to reset the phy */
-	    ixEthAccMiiWriteRtn(phyAddr, 
-				IX_ETH_MII_CTRL_REG,
-				IX_ETH_MII_CR_RESET);
-	 
-	    /* poll until the reset bit is cleared */
-	    timeout = 0;
-	    do
-	    {
-		ixOsalSleep (IX_ETH_MII_RESET_POLL_MS);
-
-		/* read the control register and check for timeout */
-		ixEthAccMiiReadRtn(phyAddr, 
-				   IX_ETH_MII_CTRL_REG,
-				   &regval);
-		if ((regval & IX_ETH_MII_CR_RESET) == 0)
-		{
-		    /* timeout bit is self-cleared */
-		    break;
-		}
-		timeout += IX_ETH_MII_RESET_POLL_MS;
-	    }
-	    while (timeout < IX_ETH_MII_RESET_DELAY_MS);
-
-	    /* check for timeout */
-	    if (timeout >= IX_ETH_MII_RESET_DELAY_MS)
-	    {
-		ixEthAccMiiWriteRtn(phyAddr, IX_ETH_MII_CTRL_REG,
-				    IX_ETH_MII_CR_NORM_EN);
-		return IX_FAIL;
-	    }
-
-	    return IX_SUCCESS;
-	} /* end of if(ixEthMiiPhyId) */
-	else if (ixEthMiiPhyId[phyAddr] == IX_ETH_MII_KS8995_PHY_ID)
-	{
-	    /* reset bit is reserved, just reset the control register */
-	    ixEthAccMiiWriteRtn(phyAddr, IX_ETH_MII_CTRL_REG,
-				IX_ETH_MII_CR_NORM_EN);
-	    return IX_SUCCESS;
-	}
-	else
-	{
-	    /* unknown PHY, set the control register reset bit,
-	     * wait 2 s. and clear the control register.
-	     */
-	    ixEthAccMiiWriteRtn(phyAddr, IX_ETH_MII_CTRL_REG,
-				IX_ETH_MII_CR_RESET);
-	    
-	    ixOsalSleep (IX_ETH_MII_RESET_DELAY_MS);
-	    
-	    ixEthAccMiiWriteRtn(phyAddr, IX_ETH_MII_CTRL_REG,
-				IX_ETH_MII_CR_NORM_EN);
-	    return IX_SUCCESS;
-	} /* end of if-else(ixEthMiiPhyId) */
-    } /* end of if(phyAddr) */
-    return IX_FAIL;
-}
-
-/*****************************************************************
- *
- *  Link state query functions
- */
-
-PUBLIC IX_STATUS
-ixEthMiiLinkStatus(UINT32 phyAddr,
-           BOOL *linkUp,
-           BOOL *speed100,
-           BOOL *fullDuplex,
-           BOOL *autoneg)
-{
-    UINT16 ctrlRegval, statRegval, regval, regval4, regval5;
-
-    /* check the parameters */
-    if ((linkUp == NULL) || 
-	(speed100 == NULL) || 
-	(fullDuplex == NULL) ||
-	(autoneg == NULL))
-    {
-	return IX_FAIL;
-    }
-
-    *linkUp = false;
-    *speed100 = false;
-    *fullDuplex = false;
-    *autoneg = false;
-
-    if ((phyAddr < IXP425_ETH_ACC_MII_MAX_ADDR) &&
-	(ixEthMiiPhyId[phyAddr] != IX_ETH_MII_INVALID_PHY_ID))
-    {
-	if ((ixEthMiiPhyId[phyAddr] == IX_ETH_MII_LXT971_PHY_ID)	||
-	    (ixEthMiiPhyId[phyAddr] == IX_ETH_MII_LXT972_PHY_ID)	||
-	    (ixEthMiiPhyId[phyAddr] == IX_ETH_MII_LXT9785_PHY_ID)
-		)
-	{
-	    /* --------------------------------------------------*/
-	    /* Retrieve information from PHY specific register   */
-	    /* --------------------------------------------------*/
-	    if (ixEthAccMiiReadRtn(phyAddr, 
-				   IX_ETH_MII_STAT2_REG, 
-				   &regval) != IX_ETH_ACC_SUCCESS)
-	    {
-		return IX_FAIL;
-	    }
-	    *linkUp = ((regval & IX_ETH_MII_SR2_LINK) != 0);
-	    *speed100 = ((regval & IX_ETH_MII_SR2_100) != 0);
-	    *fullDuplex = ((regval & IX_ETH_MII_SR2_FD) != 0);
-	    *autoneg = ((regval & IX_ETH_MII_SR2_AUTO) != 0);
-	    return IX_SUCCESS;
-	} /* end of if(ixEthMiiPhyId) */
-	else
-	{    
-	    /* ----------------------------------------------------*/
-	    /* Retrieve information from status and ctrl registers */
-	    /* ----------------------------------------------------*/
-	    if (ixEthAccMiiReadRtn(phyAddr,  
-				   IX_ETH_MII_CTRL_REG, 
-				   &ctrlRegval) != IX_ETH_ACC_SUCCESS)
-	    {
-		return IX_FAIL;
-	    }
-	    ixEthAccMiiReadRtn(phyAddr,  IX_ETH_MII_STAT_REG, &statRegval);
-	    
-	    *linkUp = ((statRegval & IX_ETH_MII_SR_LINK_STATUS) != 0);
-	    if (*linkUp)
-	    {
-		*autoneg = ((ctrlRegval & IX_ETH_MII_CR_AUTO_EN) != 0) &&
-		    ((statRegval &  IX_ETH_MII_SR_AUTO_SEL) != 0) &&
-		    ((statRegval & IX_ETH_MII_SR_AUTO_NEG) != 0);
-		
-		if (*autoneg)
-		{
-		    /* mask the current stat values with the capabilities */
-		    ixEthAccMiiReadRtn(phyAddr, IX_ETH_MII_AN_ADS_REG, &regval4);
-		    ixEthAccMiiReadRtn(phyAddr, IX_ETH_MII_AN_PRTN_REG, &regval5);
-		    /* merge the flags from the 3 registers */
-		    regval = (statRegval & ((regval4 & regval5) << 6));
-		    /* initialise from status register values */
-		    if ((regval & IX_ETH_MII_SR_TX_FULL_DPX) != 0)
-		    {
-			/* 100 Base X full dplx */
-			*speed100 = true;
-			*fullDuplex = true;
-			return IX_SUCCESS;
-		    }
-		    if ((regval & IX_ETH_MII_SR_TX_HALF_DPX) != 0)
-		    {
-			/* 100 Base X half dplx */
-			*speed100 = true;
-			return IX_SUCCESS;
-		    }
-		    if ((regval & IX_ETH_MII_SR_10T_FULL_DPX) != 0)
-		    {
-			/* 10 mb full dplx */
-			*fullDuplex = true;
-			return IX_SUCCESS;
-		    }
-		    if ((regval & IX_ETH_MII_SR_10T_HALF_DPX) != 0)
-		    {
-			/* 10 mb half dplx */
-			return IX_SUCCESS;
-		    }
-		} /* end of if(autoneg) */
-		else
-		{
-		    /* autonegotiate not complete, return setup parameters */
-		    *speed100 = ((ctrlRegval & IX_ETH_MII_CR_100) != 0);
-		    *fullDuplex = ((ctrlRegval & IX_ETH_MII_CR_FDX) != 0);
-		}
-	    } /* end of if(linkUp) */
-	} /* end of if-else(ixEthMiiPhyId) */
-    } /* end of if(phyAddr) */
-    else
-    {
-	return IX_FAIL;
-    } /* end of if-else(phyAddr) */
-    return IX_SUCCESS;
-}
-
-/*****************************************************************
- *
- *  Link state display functions
- */
-
-PUBLIC IX_STATUS
-ixEthMiiPhyShow (UINT32 phyAddr)
-{
-    BOOL linkUp, speed100, fullDuplex, autoneg;
-    UINT16 cregval;
-    UINT16 sregval;
-    
-
-    ixEthAccMiiReadRtn(phyAddr,  IX_ETH_MII_STAT_REG, &sregval);
-    ixEthAccMiiReadRtn(phyAddr,  IX_ETH_MII_CTRL_REG, &cregval);
-
-    /* get link information */
-    if (ixEthMiiLinkStatus(phyAddr,
-			   &linkUp,
-			   &speed100,
-			   &fullDuplex,
-			   &autoneg) != IX_ETH_ACC_SUCCESS)
-    {
-	printf("PHY Status unknown\n");
-	return IX_FAIL;
-    }
-
-    printf("PHY ID [phyAddr]: %8.8x\n",ixEthMiiPhyId[phyAddr]);
-    printf( " Status reg:  %4.4x\n",sregval);
-    printf( " control reg: %4.4x\n",cregval);
-    /* display link information */
-    printf("PHY Status:\n");
-    printf("    Link is %s\n",
-	   (linkUp ? "Up" : "Down"));
-    if((sregval & IX_ETH_MII_SR_REMOTE_FAULT) != 0)
-    {
-	printf("    Remote fault detected\n");
-    }
-    printf("    Auto Negotiation %s\n",
-	   (autoneg ? "Completed" : "Not Completed"));
-
-    printf("PHY Configuration:\n");
-    printf("    Speed %sMb/s\n",
-	   (speed100 ? "100" : "10"));
-    printf("    %s Duplex\n",
-	   (fullDuplex ? "Full" : "Half"));
-    printf("    Auto Negotiation %s\n",
-	   (autoneg ? "Enabled" : "Disabled"));
-    return IX_SUCCESS;
-}
-
diff --git a/drivers/net/npe/IxFeatureCtrl.c b/drivers/net/npe/IxFeatureCtrl.c
deleted file mode 100644
index 0b6807d9d7..0000000000
--- a/drivers/net/npe/IxFeatureCtrl.c
+++ /dev/null
@@ -1,398 +0,0 @@
-/**
- * @file IxFeatureCtrl.c
- *
- * @author Intel Corporation
- * @date 29-Jan-2003
- *
- * @brief Feature Control Public API Implementation
- *
- * 
- * @par
- * IXP400 SW Release version 2.0
- * 
- * -- Copyright Notice --
- * 
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- * 
- * @par
- * SPDX-License-Identifier:	BSD-3-Clause
- * @par
- * -- End of Copyright Notice --
-*/
-
-#include "IxOsal.h"
-#include "IxVersionId.h"
-#include "IxFeatureCtrl.h"
-
-/* Macro to read from the Feature Control Register */
-#define IX_FEATURE_CTRL_READ(result) \
-do { \
-ixFeatureCtrlExpMap(); \
-(result) = IX_OSAL_READ_LONG(ixFeatureCtrlRegister); \
-} while (0)
-
-/* Macro to write to the Feature Control Register */
-#define IX_FEATURE_CTRL_WRITE(value) \
-do { \
-ixFeatureCtrlExpMap(); \
-IX_OSAL_WRITE_LONG(ixFeatureCtrlRegister, (value)); \
-} while (0)
-
-/*
- * This is the offset of the feature register relative to the base of the
- * Expansion Bus Controller MMR.
- */
-#define IX_FEATURE_CTRL_REG_OFFSET (0x00000028)
-
-
-/* Boolean to mark the fact that the EXP_CONFIG address space was mapped */
-PRIVATE BOOL ixFeatureCtrlExpCfgRegionMapped = false;
-
-/* Pointer holding the virtual address of the Feature Control Register */
-PRIVATE VUINT32 *ixFeatureCtrlRegister = NULL;
-
-/* Place holder to store the software configuration */
-PRIVATE BOOL swConfiguration[IX_FEATURECTRL_SWCONFIG_MAX];
-
-/* Flag to control swConfiguration[] is initialized once */
-PRIVATE BOOL swConfigurationFlag = false ;
-
-/* Array containing component mask values */
-#ifdef __ixp42X
-UINT32 componentMask[IX_FEATURECTRL_MAX_COMPONENTS] = {
-    (0x1<<IX_FEATURECTRL_RCOMP),
-    (0x1<<IX_FEATURECTRL_USB),
-    (0x1<<IX_FEATURECTRL_HASH),
-    (0x1<<IX_FEATURECTRL_AES),
-    (0x1<<IX_FEATURECTRL_DES),
-    (0x1<<IX_FEATURECTRL_HDLC),
-    (0x1<<IX_FEATURECTRL_AAL),
-    (0x1<<IX_FEATURECTRL_HSS),
-    (0x1<<IX_FEATURECTRL_UTOPIA),
-    (0x1<<IX_FEATURECTRL_ETH0),
-    (0x1<<IX_FEATURECTRL_ETH1),
-    (0x1<<IX_FEATURECTRL_NPEA),
-    (0x1<<IX_FEATURECTRL_NPEB),
-    (0x1<<IX_FEATURECTRL_NPEC),
-    (0x1<<IX_FEATURECTRL_PCI),
-    IX_FEATURECTRL_COMPONENT_NOT_AVAILABLE,
-    (0x3<<IX_FEATURECTRL_UTOPIA_PHY_LIMIT),
-    (0x1<<IX_FEATURECTRL_UTOPIA_PHY_LIMIT_BIT2),
-    IX_FEATURECTRL_COMPONENT_NOT_AVAILABLE,
-    IX_FEATURECTRL_COMPONENT_NOT_AVAILABLE,
-    IX_FEATURECTRL_COMPONENT_NOT_AVAILABLE,
-    IX_FEATURECTRL_COMPONENT_NOT_AVAILABLE,
-    IX_FEATURECTRL_COMPONENT_NOT_AVAILABLE
-};
-#elif defined (__ixp46X)
-UINT32 componentMask[IX_FEATURECTRL_MAX_COMPONENTS] = {
-    (0x1<<IX_FEATURECTRL_RCOMP),
-    (0x1<<IX_FEATURECTRL_USB),
-    (0x1<<IX_FEATURECTRL_HASH),
-    (0x1<<IX_FEATURECTRL_AES),
-    (0x1<<IX_FEATURECTRL_DES),
-    (0x1<<IX_FEATURECTRL_HDLC),
-    IX_FEATURECTRL_COMPONENT_ALWAYS_AVAILABLE,  /* AAL component is always on */
-    (0x1<<IX_FEATURECTRL_HSS),
-    (0x1<<IX_FEATURECTRL_UTOPIA),
-    (0x1<<IX_FEATURECTRL_ETH0),
-    (0x1<<IX_FEATURECTRL_ETH1),
-    (0x1<<IX_FEATURECTRL_NPEA),
-    (0x1<<IX_FEATURECTRL_NPEB),
-    (0x1<<IX_FEATURECTRL_NPEC),
-    (0x1<<IX_FEATURECTRL_PCI),
-    (0x1<<IX_FEATURECTRL_ECC_TIMESYNC),
-    (0x3<<IX_FEATURECTRL_UTOPIA_PHY_LIMIT),
-    (0x1<<IX_FEATURECTRL_UTOPIA_PHY_LIMIT_BIT2), /* NOT TO BE USED */
-    (0x1<<IX_FEATURECTRL_USB_HOST_CONTROLLER),
-    (0x1<<IX_FEATURECTRL_NPEA_ETH),
-    (0x1<<IX_FEATURECTRL_NPEB_ETH),
-    (0x1<<IX_FEATURECTRL_RSA),
-    (0x3<<IX_FEATURECTRL_XSCALE_MAX_FREQ),
-    (0x1<<IX_FEATURECTRL_XSCALE_MAX_FREQ_BIT2)
-};
-#endif /* __ixp42X */
-
-/**
- * Forward declaration
- */
-PRIVATE
-void ixFeatureCtrlExpMap(void);
-
-PRIVATE 
-void ixFeatureCtrlSwConfigurationInit(void);
-
-/**
- * Function to map EXP_CONFIG space
- */
-PRIVATE
-void ixFeatureCtrlExpMap(void)
-{
-    UINT32 expCfgBaseAddress = 0;
-
-    /* If the EXP Configuration space has already been mapped then
-     * return */
-    if (ixFeatureCtrlExpCfgRegionMapped == true)
-    {
-	return;
-    }
-
-    /* Map (get virtual address) for the EXP_CONFIG space */
-    expCfgBaseAddress = (UINT32)
-	(IX_OSAL_MEM_MAP(IX_OSAL_IXP400_EXP_BUS_REGS_PHYS_BASE,
-			   IX_OSAL_IXP400_EXP_REG_MAP_SIZE));
-
-    /* Assert that the mapping operation succeeded */
-    IX_OSAL_ASSERT(expCfgBaseAddress);
-
-    /* Set the address of the Feature register */
-    ixFeatureCtrlRegister =
-	(VUINT32 *) (expCfgBaseAddress + IX_FEATURE_CTRL_REG_OFFSET);
-
-    /* Mark the fact that the EXP_CONFIG space has already been mapped */
-    ixFeatureCtrlExpCfgRegionMapped = true;
-}
-
-/**
- * Function definition: ixFeatureCtrlSwConfigurationInit
- * This function will only initialize software configuration once.
- */
-PRIVATE void ixFeatureCtrlSwConfigurationInit(void)
-{
-  UINT32 i;
-  if (false == swConfigurationFlag)
-  {
-    for (i=0; i<IX_FEATURECTRL_SWCONFIG_MAX ; i++)
-    {
-        /* By default, all software configuration are enabled */
-        swConfiguration[i]= true ;
-    }
-    /*Make sure this function only initializes swConfiguration[] once*/
-    swConfigurationFlag = true ;
-  }  
-}
-
-/**
- * Function definition: ixFeatureCtrlRead
- */
-IxFeatureCtrlReg 
-ixFeatureCtrlRead (void)
-{
-    IxFeatureCtrlReg result;
-
-#if CPU!=SIMSPARCSOLARIS
-    /* Read the feature control register */
-    IX_FEATURE_CTRL_READ(result);
-    return result;
-#else
-    /* Return an invalid value for VxWorks simulation */
-    result = 0xFFFFFFFF;
-    return result;
-#endif
-}
-
-/**
- * Function definition: ixFeatureCtrlWrite
- */
-void
-ixFeatureCtrlWrite (IxFeatureCtrlReg expUnitReg)
-{
-#if CPU!=SIMSPARCSOLARIS
-    /* Write value to feature control register */
-    IX_FEATURE_CTRL_WRITE(expUnitReg);
-#endif
-}
-
-
-/**
- * Function definition: ixFeatureCtrlHwCapabilityRead
- */
-IxFeatureCtrlReg
-ixFeatureCtrlHwCapabilityRead (void)
-{ 
-  IxFeatureCtrlReg currentReg, hwCapability;
-  
-  /* Capture a copy of feature control register */
-  currentReg = ixFeatureCtrlRead(); 
-
-  /* Try to enable all hardware components. 
-   * Only software disable hardware can be enabled again */
-  ixFeatureCtrlWrite(0);
-  
-  /* Read feature control register to know the hardware capability. */ 
-  hwCapability = ixFeatureCtrlRead();
-     
-  /* Restore initial feature control value */
-  ixFeatureCtrlWrite(currentReg);
-
-  /* return Hardware Capability */
-  return hwCapability;  
-}
-
-
-/**
- * Function definition: ixFeatureCtrlComponentCheck
- */
-IX_STATUS 
-ixFeatureCtrlComponentCheck (IxFeatureCtrlComponentType componentType)
-{
-  IxFeatureCtrlReg expUnitReg; 
-  UINT32 mask = 0;
-
-  /* Lookup mask of component */
-  mask=componentMask[componentType];
-
-  /* Check if mask is available or not */
-  if(IX_FEATURECTRL_COMPONENT_NOT_AVAILABLE == mask)
-  {
-      return IX_FEATURE_CTRL_COMPONENT_DISABLED;
-  }
-
-  if(IX_FEATURECTRL_COMPONENT_ALWAYS_AVAILABLE == mask)
-  {
-      return IX_FEATURE_CTRL_COMPONENT_ENABLED;
-  }
-
-  /* Read feature control register to know current hardware capability. */ 
-  expUnitReg = ixFeatureCtrlRead();
-
-  /* For example: To check for Hashing Coprocessor (bit-2) 
-   *                   expUniteg    = 0x0010
-   *                  ~expUnitReg   = 0x1101 
-   *                  componentType = 0x0100
-   *    ~expUnitReg & componentType = 0x0100 (Not zero)                      
-   */
- 
-  /* 
-   * Inverse the bit value because available component is 0 in value 
-   */
-  expUnitReg = ~expUnitReg ;
-
-  if (expUnitReg & mask)
-  {
-     return (IX_FEATURE_CTRL_COMPONENT_ENABLED);
-  }   
-  else
-  {  
-     return (IX_FEATURE_CTRL_COMPONENT_DISABLED);
-  } 
-}
-
-
-/**
- * Function definition: ixFeatureCtrlProductIdRead
- */
-IxFeatureCtrlProductId
-ixFeatureCtrlProductIdRead ()
-{
-#if CPU!=SIMSPARCSOLARIS
-  IxFeatureCtrlProductId  pdId = 0 ;
-   
-  /* Use ARM instruction to move register0 from coprocessor to ARM register */ 
-    
-#ifndef __wince
-    __asm__("mrc p15, 0, %0, cr0, cr0, 0;" : "=r"(pdId) :);
-#else
-      
-#ifndef IN_KERNEL
-        BOOL  mode;
-#endif
-    extern  IxFeatureCtrlProductId AsmixFeatureCtrlProductIdRead();
-    
-#ifndef IN_KERNEL
-    mode = SetKMode(true);
-#endif
-    pdId = AsmixFeatureCtrlProductIdRead();
-#ifndef IN_KERNEL
-    SetKMode(mode);
-#endif
-
-#endif
-  return (pdId);
-#else
-  /* Return an invalid value for VxWorks simulation */
-  return 0xffffffff;
-#endif
-}
-
-/**
- * Function definition: ixFeatureCtrlDeviceRead
- */
-IxFeatureCtrlDeviceId
-ixFeatureCtrlDeviceRead ()
-{
-  return ((ixFeatureCtrlProductIdRead() >> IX_FEATURE_CTRL_DEVICE_TYPE_OFFSET) 
-             & IX_FEATURE_CTRL_DEVICE_TYPE_MASK);
-} /* End function ixFeatureCtrlDeviceRead */
-
-
-/**
- * Function definition: ixFeatureCtrlSwConfigurationCheck
- */
-IX_STATUS
-ixFeatureCtrlSwConfigurationCheck (IxFeatureCtrlSwConfig swConfigType)
-{
-  if (swConfigType >= IX_FEATURECTRL_SWCONFIG_MAX)  
-  {
-     ixOsalLog(IX_OSAL_LOG_LVL_WARNING, 
-               IX_OSAL_LOG_DEV_STDOUT,
-               "FeatureCtrl: Invalid software configuraiton input.\n",
-               0, 0, 0, 0, 0, 0);  
-
-     return IX_FEATURE_CTRL_SWCONFIG_DISABLED;
-  }
-
-  /* The function will only initialize once. */
-  ixFeatureCtrlSwConfigurationInit();
-  
-  /* Check and return software configuration */
-  return  ((swConfiguration[(UINT32)swConfigType] == true) ? IX_FEATURE_CTRL_SWCONFIG_ENABLED: IX_FEATURE_CTRL_SWCONFIG_DISABLED);
-}
-
-/**
- * Function definition: ixFeatureCtrlSwConfigurationWrite
- */
-void
-ixFeatureCtrlSwConfigurationWrite (IxFeatureCtrlSwConfig swConfigType, BOOL enabled)
-{
-  if (swConfigType >= IX_FEATURECTRL_SWCONFIG_MAX)  
-  {
-     ixOsalLog(IX_OSAL_LOG_LVL_WARNING, 
-               IX_OSAL_LOG_DEV_STDOUT,
-               "FeatureCtrl: Invalid software configuraiton input.\n",
-               0, 0, 0, 0, 0, 0);  
-
-     return;
-  }
-
-  /* The function will only initialize once. */
-  ixFeatureCtrlSwConfigurationInit();
-  
-  /* Write software configuration */
-  swConfiguration[(UINT32)swConfigType]=enabled ;
-}
-
-/**
- * Function definition: ixFeatureCtrlIxp400SwVersionShow
- */
-void
-ixFeatureCtrlIxp400SwVersionShow (void)
-{
-    printf ("\nIXP400 Software Release %s %s\n\n", IX_VERSION_ID, IX_VERSION_INTERNAL_ID);
-
-}
-
-/**
- * Function definition: ixFeatureCtrlSoftwareBuildGet
- */
-IxFeatureCtrlBuildDevice
-ixFeatureCtrlSoftwareBuildGet (void)
-{
-    #ifdef __ixp42X
-    return IX_FEATURE_CTRL_SW_BUILD_IXP42X;
-    #else
-    return IX_FEATURE_CTRL_SW_BUILD_IXP46X;
-    #endif
-}
diff --git a/drivers/net/npe/IxNpeDl.c b/drivers/net/npe/IxNpeDl.c
deleted file mode 100644
index 0e5c428323..0000000000
--- a/drivers/net/npe/IxNpeDl.c
+++ /dev/null
@@ -1,916 +0,0 @@
-/**
- * @file IxNpeDl.c
- *
- * @author Intel Corporation
- * @date 08 January 2002
- *
- * @brief This file contains the implementation of the public API for the
- *        IXP425 NPE Downloader component
- *
- *
- * @par
- * IXP400 SW Release version 2.0
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * SPDX-License-Identifier:	BSD-3-Clause
- * @par
- * -- End of Copyright Notice --
-*/
-
-/*
- * Put the system defined include files required
- */
-
-/*
- * Put the user defined include files required
- */
-#include "IxNpeDl.h"
-#include "IxNpeDlImageMgr_p.h"
-#include "IxNpeDlNpeMgr_p.h"
-#include "IxNpeDlMacros_p.h"
-#include "IxFeatureCtrl.h"
-#include "IxOsal.h"
-/*
- * #defines used in this file
- */
- #define IMAGEID_MAJOR_NUMBER_DEFAULT 0
- #define IMAGEID_MINOR_NUMBER_DEFAULT 0
-
-/*
- * Typedefs whose scope is limited to this file.
- */
-typedef struct
-{
-    BOOL validImage;
-    IxNpeDlImageId imageId;
-} IxNpeDlNpeState;
-
-/* module statistics counters */
-typedef struct
-{
-    UINT32 attemptedDownloads;
-    UINT32 successfulDownloads;
-    UINT32 criticalFailDownloads;
-} IxNpeDlStats;
-
-/*
- * Variable declarations global to this file only.  Externs are followed
- * by static variables.
- */
-static IxNpeDlNpeState ixNpeDlNpeState[IX_NPEDL_NPEID_MAX] =
-{
-    {false, {IX_NPEDL_NPEID_MAX, 0, 0, 0}},
-    {false, {IX_NPEDL_NPEID_MAX, 0, 0, 0}},
-    {false, {IX_NPEDL_NPEID_MAX, 0, 0, 0}}
-};
-
-static IxNpeDlStats ixNpeDlStats;
-
-/*
- * Software guard to prevent NPE from being started multiple times.
- */
-static BOOL ixNpeDlNpeStarted[IX_NPEDL_NPEID_MAX] ={false, false, false} ;
-
-
-/*
- * static function prototypes.
- */
-PRIVATE IX_STATUS
-ixNpeDlNpeInitAndStartInternal (UINT32 *imageLibrary, UINT32 imageId);
-
-/*
- * Function definition: ixNpeDlImageDownload
- */
-PUBLIC IX_STATUS
-ixNpeDlImageDownload (IxNpeDlImageId *imageIdPtr,
-                      BOOL verify)
-{
-    UINT32        imageSize;
-    UINT32       *imageCodePtr  = NULL;
-    IX_STATUS     status;
-    IxNpeDlNpeId  npeId           = imageIdPtr->npeId;
-
-    IX_NPEDL_TRACE0 (IX_NPEDL_FN_ENTRY_EXIT,
-                     "Entering ixNpeDlImageDownload\n");
-
-    ixNpeDlStats.attemptedDownloads++;
-
-    /* Check input parameters */
-    if ((npeId >= IX_NPEDL_NPEID_MAX) || (npeId < 0))
-    {
-        status = IX_NPEDL_PARAM_ERR;
-        IX_NPEDL_ERROR_REPORT ("ixNpeDlImageDownload - invalid parameter\n");
-    }
-    else
-    {
-        /* Ensure initialisation has been completed */
-        ixNpeDlNpeMgrInit();
-
-	/* If not IXP42X A0 stepping, proceed to check for existence of npe's */
-	if ((IX_FEATURE_CTRL_SILICON_TYPE_A0 !=
-	     (ixFeatureCtrlProductIdRead() & IX_FEATURE_CTRL_SILICON_STEPPING_MASK))
-	    || (IX_FEATURE_CTRL_DEVICE_TYPE_IXP42X != ixFeatureCtrlDeviceRead ()))
-	{
-            if (npeId == IX_NPEDL_NPEID_NPEA)
-            {
-                if (ixFeatureCtrlComponentCheck(IX_FEATURECTRL_NPEA) ==
-                    IX_FEATURE_CTRL_COMPONENT_DISABLED)
-                {
-                    IX_NPEDL_WARNING_REPORT("Warning: the NPE A component you specified does"
-                                            " not exist\n");
-                    return IX_SUCCESS;
-                }
-            } /* end of if(npeId) */
-            else if (npeId == IX_NPEDL_NPEID_NPEB)
-            {
-                if (ixFeatureCtrlComponentCheck(IX_FEATURECTRL_NPEB)==
-                    IX_FEATURE_CTRL_COMPONENT_DISABLED)
-                {
-                    IX_NPEDL_WARNING_REPORT("Warning: the NPE B component you specified"
-                                            " does not exist\n");
-                    return IX_SUCCESS;
-                }
-            } /* end of elseif(npeId) */
-            else if (npeId == IX_NPEDL_NPEID_NPEC)
-            {
-                if (ixFeatureCtrlComponentCheck(IX_FEATURECTRL_NPEC)==
-                    IX_FEATURE_CTRL_COMPONENT_DISABLED)
-                {
-                    IX_NPEDL_WARNING_REPORT("Warning: the NPE C component you specified"
-                                            " does not exist\n");
-                    return IX_SUCCESS;
-                }
-            } /* end of elseif(npeId) */
-        } /* end of if(IX_FEATURE_CTRL_SILICON_TYPE_B0) */ /*End of Silicon Type Check*/
-
-        /* stop and reset the NPE */
-        if (IX_SUCCESS != ixNpeDlNpeStopAndReset (npeId))
-        {
-            IX_NPEDL_ERROR_REPORT ("Failed to stop and reset NPE\n");
-            return IX_FAIL;
-        }
-
-        /* Locate image */
-        status = ixNpeDlImageMgrImageLocate (imageIdPtr, &imageCodePtr,
-                                             &imageSize);
-        if (IX_SUCCESS == status)
-        {
-            /*
-             * If download was successful, store image Id in list of
-             * currently loaded images. If a critical error occured
-             * during download, record that the NPE has an invalid image
-             */
-            status = ixNpeDlNpeMgrImageLoad (npeId, imageCodePtr,
-                                             verify);
-            if (IX_SUCCESS == status)
-            {
-                ixNpeDlNpeState[npeId].imageId = *imageIdPtr;
-                ixNpeDlNpeState[npeId].validImage = true;
-                ixNpeDlStats.successfulDownloads++;
-
-                status =  ixNpeDlNpeExecutionStart (npeId);
-            }
-            else if ((status == IX_NPEDL_CRITICAL_NPE_ERR) ||
-                     (status == IX_NPEDL_CRITICAL_MICROCODE_ERR))
-            {
-                ixNpeDlNpeState[npeId].imageId = *imageIdPtr;
-                ixNpeDlNpeState[npeId].validImage = false;
-                ixNpeDlStats.criticalFailDownloads++;
-            }
-        } /* end of if(IX_SUCCESS) */ /* condition: image located successfully in microcode image */
-    } /* end of if-else(npeId) */ /* condition: parameter checks ok */
-
-    IX_NPEDL_TRACE1 (IX_NPEDL_FN_ENTRY_EXIT,
-                     "Exiting ixNpeDlImageDownload : status = %d\n", status);
-    return status;
-}
-
-/*
- * Function definition: ixNpeDlAvailableImagesCountGet
- */
-PUBLIC IX_STATUS
-ixNpeDlAvailableImagesCountGet (UINT32 *numImagesPtr)
-{
-    IX_STATUS status;
-
-    IX_NPEDL_TRACE0 (IX_NPEDL_FN_ENTRY_EXIT,
-                     "Entering ixNpeDlAvailableImagesCountGet\n");
-
-    /* Check input parameters */
-    if (numImagesPtr == NULL)
-    {
-        status = IX_NPEDL_PARAM_ERR;
-        IX_NPEDL_ERROR_REPORT ("ixNpeDlAvailableImagesCountGet - "
-                               "invalid parameter\n");
-    }
-    else
-    {
-        /*
-         * Use ImageMgr module to get no. of images listed in Image Library Header.
-         * If NULL is passed as imageListPtr parameter to following function,
-         * it will only fill number of images into numImagesPtr
-         */
-        status = ixNpeDlImageMgrImageListExtract (NULL, numImagesPtr);
-    } /* end of if-else(numImagesPtr) */
-
-    IX_NPEDL_TRACE1 (IX_NPEDL_FN_ENTRY_EXIT,
-                     "Exiting ixNpeDlAvailableImagesCountGet : "
-                     "status = %d\n", status);
-    return status;
-}
-
-/*
- * Function definition: ixNpeDlAvailableImagesListGet
- */
-PUBLIC IX_STATUS
-ixNpeDlAvailableImagesListGet (IxNpeDlImageId *imageIdListPtr,
-                               UINT32 *listSizePtr)
-{
-    IX_STATUS status;
-
-    IX_NPEDL_TRACE0 (IX_NPEDL_FN_ENTRY_EXIT,
-                     "Entering ixNpeDlAvailableImagesListGet\n");
-
-    /* Check input parameters */
-    if ((imageIdListPtr == NULL) || (listSizePtr == NULL))
-    {
-        status = IX_NPEDL_PARAM_ERR;
-        IX_NPEDL_ERROR_REPORT ("ixNpeDlAvailableImagesListGet - "
-                               "invalid parameter\n");
-    }
-    else
-    {
-        /* Call ImageMgr to get list of images listed in Image Library Header */
-        status = ixNpeDlImageMgrImageListExtract (imageIdListPtr,
-                                                  listSizePtr);
-    } /* end of if-else(imageIdListPtr) */
-
-    IX_NPEDL_TRACE1 (IX_NPEDL_FN_ENTRY_EXIT,
-                     "Exiting ixNpeDlAvailableImagesListGet : status = %d\n",
-                     status);
-    return status;
-}
-
-/*
- * Function definition: ixNpeDlLoadedImageGet
- */
-PUBLIC IX_STATUS
-ixNpeDlLoadedImageGet (IxNpeDlNpeId npeId,
-                       IxNpeDlImageId *imageIdPtr)
-{
-    IX_STATUS status = IX_SUCCESS;
-
-    IX_NPEDL_TRACE0 (IX_NPEDL_FN_ENTRY_EXIT,
-                     "Entering ixNpeDlLoadedImageGet\n");
-
-    /* Check input parameters */
-    if ((npeId >= IX_NPEDL_NPEID_MAX) || (npeId < 0) || (imageIdPtr == NULL))
-    {
-        status = IX_NPEDL_PARAM_ERR;
-        IX_NPEDL_ERROR_REPORT ("ixNpeDlLoadedImageGet - invalid parameter\n");
-    }
-    else
-    {
-
-         /* If not IXP42X A0 stepping, proceed to check for existence of npe's */
-         if ((IX_FEATURE_CTRL_SILICON_TYPE_A0 !=
-	      (ixFeatureCtrlProductIdRead() & IX_FEATURE_CTRL_SILICON_STEPPING_MASK))
-	     || (IX_FEATURE_CTRL_DEVICE_TYPE_IXP42X != ixFeatureCtrlDeviceRead ()))
-        {
-            if (npeId == IX_NPEDL_NPEID_NPEA &&
-                (ixFeatureCtrlComponentCheck(IX_FEATURECTRL_NPEA) ==
-                 IX_FEATURE_CTRL_COMPONENT_DISABLED))
-            {
-                IX_NPEDL_WARNING_REPORT("Warning: the NPE A component you specified does"
-                                        " not exist\n");
-                return IX_SUCCESS;
-            } /* end of if(npeId) */
-
-            if (npeId == IX_NPEDL_NPEID_NPEB &&
-                (ixFeatureCtrlComponentCheck(IX_FEATURECTRL_NPEB) ==
-                 IX_FEATURE_CTRL_COMPONENT_DISABLED))
-            {
-                IX_NPEDL_WARNING_REPORT("Warning: the NPE B component you specified does"
-                                        " not exist\n");
-                return IX_SUCCESS;
-            } /* end of if(npeId) */
-
-            if (npeId == IX_NPEDL_NPEID_NPEC &&
-                (ixFeatureCtrlComponentCheck(IX_FEATURECTRL_NPEC) ==
-                 IX_FEATURE_CTRL_COMPONENT_DISABLED))
-            {
-                IX_NPEDL_WARNING_REPORT("Warning: the NPE C component you specified does"
-                                        " not exist\n");
-                return IX_SUCCESS;
-            } /* end of if(npeId) */
-        } /* end of if not IXP42x-A0 silicon */
-
-        if (ixNpeDlNpeState[npeId].validImage)
-        {
-            /* use npeId to get imageId from list of currently loaded
-               images */
-            *imageIdPtr = ixNpeDlNpeState[npeId].imageId;
-        }
-        else
-        {
-            status = IX_FAIL;
-        } /* end of if-else(ixNpeDlNpeState) */
-    } /* end of if-else(npeId) */
-
-    IX_NPEDL_TRACE1 (IX_NPEDL_FN_ENTRY_EXIT,
-                     "Exiting ixNpeDlLoadedImageGet : status = %d\n",
-                     status);
-    return status;
-}
-
-/*
- * Function definition: ixNpeDlLatestImageGet
- */
-PUBLIC IX_STATUS
-ixNpeDlLatestImageGet (
-    IxNpeDlNpeId npeId,
-    IxNpeDlFunctionalityId functionalityId,
-    IxNpeDlImageId *imageIdPtr)
-{
-    IX_STATUS status;
-
-    IX_NPEDL_TRACE0 (IX_NPEDL_FN_ENTRY_EXIT,
-                     "Entering ixNpeDlLatestImageGet\n");
-
-    /* Check input parameters */
-    if ((npeId >= IX_NPEDL_NPEID_MAX) ||
-        (npeId < 0) ||
-        (imageIdPtr == NULL))
-    {
-        status = IX_NPEDL_PARAM_ERR;
-        IX_NPEDL_ERROR_REPORT ("ixNpeDlLatestImageGet - "
-                               "invalid parameter\n");
-    } /* end of if(npeId) */
-    else
-    {
-
-	/* If not IXP42X A0 stepping, proceed to check for existence of npe's */
-	if ((IX_FEATURE_CTRL_SILICON_TYPE_A0 !=
-	     (ixFeatureCtrlProductIdRead() & IX_FEATURE_CTRL_SILICON_STEPPING_MASK))
-	    || (IX_FEATURE_CTRL_DEVICE_TYPE_IXP42X != ixFeatureCtrlDeviceRead ()))
-        {
-            if (npeId == IX_NPEDL_NPEID_NPEA &&
-                (ixFeatureCtrlComponentCheck(IX_FEATURECTRL_NPEA) ==
-                 IX_FEATURE_CTRL_COMPONENT_DISABLED))
-            {
-                IX_NPEDL_WARNING_REPORT("Warning: the NPE A component you specified does"
-                                        " not exist\n");
-                return IX_SUCCESS;
-            } /* end of if(npeId) */
-
-            if (npeId == IX_NPEDL_NPEID_NPEB &&
-                (ixFeatureCtrlComponentCheck(IX_FEATURECTRL_NPEB) ==
-                 IX_FEATURE_CTRL_COMPONENT_DISABLED))
-            {
-                IX_NPEDL_WARNING_REPORT("Warning: the NPE B component you specified does"
-                                        " not exist\n");
-                return IX_SUCCESS;
-            } /* end of if(npeId) */
-
-            if (npeId == IX_NPEDL_NPEID_NPEC &&
-                (ixFeatureCtrlComponentCheck(IX_FEATURECTRL_NPEC) ==
-                 IX_FEATURE_CTRL_COMPONENT_DISABLED))
-            {
-                IX_NPEDL_WARNING_REPORT("Warning: the NPE C component you specified does"
-                                        " not exist\n");
-                return IX_SUCCESS;
-            } /* end of if(npeId) */
-        } /* end of if not IXP42x-A0 silicon */
-
-        imageIdPtr->npeId = npeId;
-        imageIdPtr->functionalityId = functionalityId;
-        imageIdPtr->major = IMAGEID_MAJOR_NUMBER_DEFAULT;
-        imageIdPtr->minor = IMAGEID_MINOR_NUMBER_DEFAULT;
-        /* Call ImageMgr to get list of images listed in Image Library Header */
-        status = ixNpeDlImageMgrLatestImageExtract(imageIdPtr);
-    } /* end of if-else(npeId) */
-
-    IX_NPEDL_TRACE1 (IX_NPEDL_FN_ENTRY_EXIT,
-                     "Exiting ixNpeDlLatestImageGet : status = %d\n",
-                     status);
-
-    return status;
-}
-
-/*
- * Function definition: ixNpeDlNpeStopAndReset
- */
-PUBLIC IX_STATUS
-ixNpeDlNpeStopAndReset (IxNpeDlNpeId npeId)
-{
-    IX_STATUS status = IX_SUCCESS;
-
-    IX_NPEDL_TRACE0 (IX_NPEDL_FN_ENTRY_EXIT,
-                     "Entering ixNpeDlNpeStopAndReset\n");
-
-    /* Ensure initialisation has been completed */
-    ixNpeDlNpeMgrInit();
-
-    /* If not IXP42X A0 stepping, proceed to check for existence of npe's */
-    if ((IX_FEATURE_CTRL_SILICON_TYPE_A0 !=
-	 (ixFeatureCtrlProductIdRead() & IX_FEATURE_CTRL_SILICON_STEPPING_MASK))
-	|| (IX_FEATURE_CTRL_DEVICE_TYPE_IXP42X != ixFeatureCtrlDeviceRead ()))
-    {
-        /*
-         * Check whether NPE is present
-         */
-        if (IX_NPEDL_NPEID_NPEA == npeId)
-        {
-            /* Check whether NPE A is present */
-            if (ixFeatureCtrlComponentCheck(IX_FEATURECTRL_NPEA)==
-                IX_FEATURE_CTRL_COMPONENT_DISABLED)
-            {
-                /* NPE A does not present */
-                IX_NPEDL_WARNING_REPORT ("ixNpeDlNpeStopAndReset - Warning:NPEA does not present.\n");
-                return IX_SUCCESS;
-            }
-        } /* end of if(IX_NPEDL_NPEID_NPEA) */
-        else if (IX_NPEDL_NPEID_NPEB == npeId)
-        {
-            /* Check whether NPE B is present */
-            if (ixFeatureCtrlComponentCheck(IX_FEATURECTRL_NPEB)==
-                IX_FEATURE_CTRL_COMPONENT_DISABLED)
-            {
-                /* NPE B does not present */
-                IX_NPEDL_WARNING_REPORT ("ixNpeDlNpeStopAndReset - Warning:NPEB does not present.\n");
-                return IX_SUCCESS;
-            }
-        } /* end of elseif(IX_NPEDL_NPEID_NPEB) */
-        else if (IX_NPEDL_NPEID_NPEC == npeId)
-        {
-            /* Check whether NPE C is present */
-            if (ixFeatureCtrlComponentCheck(IX_FEATURECTRL_NPEC)==
-                IX_FEATURE_CTRL_COMPONENT_DISABLED)
-            {
-                /* NPE C does not present */
-                IX_NPEDL_WARNING_REPORT ("ixNpeDlNpeStopAndReset - Warning:NPEC does not present.\n");
-                return IX_SUCCESS;
-            }
-        } /* end of elseif(IX_NPEDL_NPEID_NPEC) */
-        else
-        {
-            /* Invalid NPE ID */
-            IX_NPEDL_ERROR_REPORT ("ixNpeDlNpeStopAndReset - invalid Npe ID\n");
-            status = IX_NPEDL_PARAM_ERR;
-        } /* end of if-else(IX_NPEDL_NPEID_NPEC) */
-    } /* end of if not IXP42x-A0 Silicon */
-
-    if (status == IX_SUCCESS)
-    {
-        /* call NpeMgr function to stop the NPE */
-        status = ixNpeDlNpeMgrNpeStop (npeId);
-        if (status == IX_SUCCESS)
-        {
-            /* call NpeMgr function to reset the NPE */
-            status = ixNpeDlNpeMgrNpeReset (npeId);
-        }
-    } /* end of if(status) */
-
-    IX_NPEDL_TRACE1 (IX_NPEDL_FN_ENTRY_EXIT,
-                     "Exiting ixNpeDlNpeStopAndReset : status = %d\n", status);
-
-    if (IX_SUCCESS == status)
-    {
-        /* Indicate NPE has been stopped */
-        ixNpeDlNpeStarted[npeId] = false ;
-    }
-
-    return status;
-}
-
-/*
- * Function definition: ixNpeDlNpeExecutionStart
- */
-PUBLIC IX_STATUS
-ixNpeDlNpeExecutionStart (IxNpeDlNpeId npeId)
-{
-    IX_STATUS status = IX_SUCCESS;
-
-    IX_NPEDL_TRACE0 (IX_NPEDL_FN_ENTRY_EXIT,
-                     "Entering ixNpeDlNpeExecutionStart\n");
-
-    /* If not IXP42X A0 stepping, proceed to check for existence of npe's */
-    if ((IX_FEATURE_CTRL_SILICON_TYPE_A0 !=
-	 (ixFeatureCtrlProductIdRead() & IX_FEATURE_CTRL_SILICON_STEPPING_MASK))
-	|| (IX_FEATURE_CTRL_DEVICE_TYPE_IXP42X != ixFeatureCtrlDeviceRead ()))
-    {
-        /*
-         * Check whether NPE is present
-         */
-        if (IX_NPEDL_NPEID_NPEA == npeId)
-        {
-            /* Check whether NPE A is present */
-            if (ixFeatureCtrlComponentCheck(IX_FEATURECTRL_NPEA)==
-                IX_FEATURE_CTRL_COMPONENT_DISABLED)
-            {
-                /* NPE A does not present */
-                IX_NPEDL_WARNING_REPORT ("ixNpeDlNpeExecutionStart - Warning:NPEA does not present.\n");
-                return IX_SUCCESS;
-            }
-        } /* end of if(IX_NPEDL_NPEID_NPEA) */
-        else if (IX_NPEDL_NPEID_NPEB == npeId)
-        {
-            /* Check whether NPE B is present */
-            if (ixFeatureCtrlComponentCheck(IX_FEATURECTRL_NPEB)==
-                IX_FEATURE_CTRL_COMPONENT_DISABLED)
-            {
-                /* NPE B does not present */
-                IX_NPEDL_WARNING_REPORT ("ixNpeDlNpeExecutionStart - Warning:NPEB does not present.\n");
-                return IX_SUCCESS;
-            }
-        } /* end of elseif(IX_NPEDL_NPEID_NPEB) */
-        else if (IX_NPEDL_NPEID_NPEC ==  npeId)
-        {
-            /* Check whether NPE C is present */
-            if (ixFeatureCtrlComponentCheck(IX_FEATURECTRL_NPEC)==
-                IX_FEATURE_CTRL_COMPONENT_DISABLED)
-            {
-                /* NPE C does not present */
-                IX_NPEDL_WARNING_REPORT ("ixNpeDlNpeExecutionStart - Warning:NPEC does not present.\n");
-                return IX_SUCCESS;
-            }
-        } /* end of elseif(IX_NPEDL_NPEID_NPEC) */
-        else
-        {
-            /* Invalid NPE ID */
-            IX_NPEDL_ERROR_REPORT ("ixNpeDlNpeExecutionStart - invalid Npe ID\n");
-            return IX_NPEDL_PARAM_ERR;
-        } /* end of if-else(IX_NPEDL_NPEID_NPEC) */
-    } /* end of if not IXP42x-A0 Silicon */
-
-    if (true == ixNpeDlNpeStarted[npeId])
-    {
-        /* NPE has been started. */
-        return IX_SUCCESS ;
-    }
-
-    /* Ensure initialisation has been completed */
-    ixNpeDlNpeMgrInit();
-
-    /* call NpeMgr function to start the NPE */
-    status = ixNpeDlNpeMgrNpeStart (npeId);
-
-    if (IX_SUCCESS == status)
-    {
-        /* Indicate NPE has started */
-        ixNpeDlNpeStarted[npeId] = true ;
-    }
-
-    IX_NPEDL_TRACE1 (IX_NPEDL_FN_ENTRY_EXIT,
-                     "Exiting ixNpeDlNpeExecutionStart : status = %d\n",
-                     status);
-
-    return status;
-}
-
-/*
- * Function definition: ixNpeDlNpeExecutionStop
- */
-PUBLIC IX_STATUS
-ixNpeDlNpeExecutionStop (IxNpeDlNpeId npeId)
-{
-    IX_STATUS status = IX_SUCCESS;
-
-    IX_NPEDL_TRACE0 (IX_NPEDL_FN_ENTRY_EXIT,
-                     "Entering ixNpeDlNpeExecutionStop\n");
-
-    /* Ensure initialisation has been completed */
-    ixNpeDlNpeMgrInit();
-
-    /* If not IXP42X A0 stepping, proceed to check for existence of npe's */
-    if ((IX_FEATURE_CTRL_SILICON_TYPE_A0 !=
-	 (ixFeatureCtrlProductIdRead() & IX_FEATURE_CTRL_SILICON_STEPPING_MASK))
-	|| (IX_FEATURE_CTRL_DEVICE_TYPE_IXP42X != ixFeatureCtrlDeviceRead ()))
-    {
-        /*
-         * Check whether NPE is present
-         */
-        if (IX_NPEDL_NPEID_NPEA == npeId)
-        {
-            /* Check whether NPE A is present */
-            if (ixFeatureCtrlComponentCheck(IX_FEATURECTRL_NPEA)==
-                IX_FEATURE_CTRL_COMPONENT_DISABLED)
-            {
-                /* NPE A does not present */
-                IX_NPEDL_WARNING_REPORT ("ixNpeDlNpeExecutionStop - Warning:NPEA does not present.\n");
-                return IX_SUCCESS;
-            }
-        } /* end of if(IX_NPEDL_NPEID_NPEA) */
-        else if (IX_NPEDL_NPEID_NPEB == npeId)
-        {
-            /* Check whether NPE B is present */
-            if (ixFeatureCtrlComponentCheck(IX_FEATURECTRL_NPEB)==
-                IX_FEATURE_CTRL_COMPONENT_DISABLED)
-            {
-                /* NPE B does not present */
-                IX_NPEDL_WARNING_REPORT ("ixNpeDlNpeExecutionStop - Warning:NPEB does not present.\n");
-                return IX_SUCCESS;
-            }
-        } /* end of elseif(IX_NPEDL_NPEID_NPEB) */
-        else if (IX_NPEDL_NPEID_NPEC == npeId)
-        {
-            /* Check whether NPE C is present */
-            if (ixFeatureCtrlComponentCheck(IX_FEATURECTRL_NPEC)==
-                IX_FEATURE_CTRL_COMPONENT_DISABLED)
-            {
-                /* NPE C does not present */
-                IX_NPEDL_WARNING_REPORT ("ixNpeDlNpeExecutionStop - Warning:NPEC does not present.\n");
-                return IX_SUCCESS;
-            }
-        } /* end of elseif(IX_NPEDL_NPEID_NPEC) */
-        else
-        {
-            /* Invalid NPE ID */
-            IX_NPEDL_ERROR_REPORT ("ixNpeDlNpeExecutionStop - invalid Npe ID\n");
-            status = IX_NPEDL_PARAM_ERR;
-        } /* end of if-else(IX_NPEDL_NPEID_NPEC) */
-    } /* end of if not IXP42X-AO Silicon */
-
-    if (status == IX_SUCCESS)
-    {
-        /* call NpeMgr function to stop the NPE */
-        status = ixNpeDlNpeMgrNpeStop (npeId);
-    }
-
-    IX_NPEDL_TRACE1 (IX_NPEDL_FN_ENTRY_EXIT,
-                     "Exiting ixNpeDlNpeExecutionStop : status = %d\n",
-                     status);
-
-    if (IX_SUCCESS == status)
-    {
-        /* Indicate NPE has been stopped */
-        ixNpeDlNpeStarted[npeId] = false ;
-    }
-
-    return status;
-}
-
-/*
- * Function definition: ixNpeDlUnload
- */
-PUBLIC IX_STATUS
-ixNpeDlUnload (void)
-{
-    IX_STATUS status;
-
-    IX_NPEDL_TRACE0 (IX_NPEDL_FN_ENTRY_EXIT,
-                     "Entering ixNpeDlUnload\n");
-
-    status = ixNpeDlNpeMgrUninit();
-
-    IX_NPEDL_TRACE1 (IX_NPEDL_FN_ENTRY_EXIT,
-                     "Exiting ixNpeDlUnload : status = %d\n",
-                     status);
-    return status;
-}
-
-/*
- * Function definition: ixNpeDlStatsShow
- */
-PUBLIC void
-ixNpeDlStatsShow (void)
-{
-    ixOsalLog (IX_OSAL_LOG_LVL_USER,
-               IX_OSAL_LOG_DEV_STDOUT,
-               "\nixNpeDlStatsShow:\n"
-               "\tDownloads Attempted by user: %u\n"
-               "\tSuccessful Downloads: %u\n"
-               "\tFailed Downloads (due to Critical Error): %u\n\n",
-               ixNpeDlStats.attemptedDownloads,
-               ixNpeDlStats.successfulDownloads,
-               ixNpeDlStats.criticalFailDownloads,
-               0,0,0);
-
-    ixNpeDlImageMgrStatsShow ();
-    ixNpeDlNpeMgrStatsShow ();
-}
-
-/*
- * Function definition: ixNpeDlStatsReset
- */
-PUBLIC void
-ixNpeDlStatsReset (void)
-{
-    ixNpeDlStats.attemptedDownloads = 0;
-    ixNpeDlStats.successfulDownloads = 0;
-    ixNpeDlStats.criticalFailDownloads = 0;
-
-    ixNpeDlImageMgrStatsReset ();
-    ixNpeDlNpeMgrStatsReset ();
-}
-
-/*
- * Function definition: ixNpeDlNpeInitAndStartInternal
- */
-PRIVATE IX_STATUS
-ixNpeDlNpeInitAndStartInternal (UINT32 *imageLibrary,
-                                UINT32 imageId)
-{
-    UINT32        imageSize;
-    UINT32       *imageCodePtr  = NULL;
-    IX_STATUS     status;
-    IxNpeDlNpeId  npeId = IX_NPEDL_NPEID_FROM_IMAGEID_GET(imageId);
-    IxFeatureCtrlDeviceId deviceId = IX_NPEDL_DEVICEID_FROM_IMAGEID_GET(imageId);
-
-    IX_NPEDL_TRACE0 (IX_NPEDL_FN_ENTRY_EXIT,
-                     "Entering ixNpeDlNpeInitAndStartInternal\n");
-
-    ixNpeDlStats.attemptedDownloads++;
-
-    /* Check input parameter device correctness */
-    if ((deviceId >= IX_FEATURE_CTRL_DEVICE_TYPE_MAX) ||
-        (deviceId < IX_FEATURE_CTRL_DEVICE_TYPE_IXP42X))
-    {
-        status = IX_NPEDL_PARAM_ERR;
-        IX_NPEDL_ERROR_REPORT ("ixNpeDlNpeInitAndStartInternal - "
-                               "invalid parameter\n");
-    } /* End valid device id checking */
-
-    /* Check input parameters */
-    else if ((npeId >= IX_NPEDL_NPEID_MAX) || (npeId < 0))
-    {
-        status = IX_NPEDL_PARAM_ERR;
-        IX_NPEDL_ERROR_REPORT ("ixNpeDlNpeInitAndStartInternal - "
-                               "invalid parameter\n");
-    }
-
-    else
-    {
-        /* Ensure initialisation has been completed */
-        ixNpeDlNpeMgrInit();
-
-        /* Checking if image being loaded is meant for device that is running.
-         * Image is forward compatible. i.e Image built for IXP42X should run
-         * on IXP46X but not vice versa.*/
-        if (deviceId > (ixFeatureCtrlDeviceRead() & IX_FEATURE_CTRL_DEVICE_TYPE_MASK))
-        {
-            IX_NPEDL_ERROR_REPORT ("ixNpeDlNpeInitAndStartInternal - "
-                                   "Device type mismatch. NPE Image not "
-                                   "meant for device in use \n");
-            return IX_NPEDL_DEVICE_ERR;
-        }/* if statement - matching image device and current device */
-
-	/* If not IXP42X A0 stepping, proceed to check for existence of npe's */
-	if ((IX_FEATURE_CTRL_SILICON_TYPE_A0 !=
-	     (ixFeatureCtrlProductIdRead() & IX_FEATURE_CTRL_SILICON_STEPPING_MASK))
-	    || (IX_FEATURE_CTRL_DEVICE_TYPE_IXP42X != ixFeatureCtrlDeviceRead ()))
-        {
-            if (npeId == IX_NPEDL_NPEID_NPEA)
-            {
-                if (ixFeatureCtrlComponentCheck(IX_FEATURECTRL_NPEA) ==
-                    IX_FEATURE_CTRL_COMPONENT_DISABLED)
-                {
-                    IX_NPEDL_WARNING_REPORT("Warning: the NPE A component you specified does"
-                                            " not exist\n");
-                    return IX_SUCCESS;
-                }
-            } /* end of if(npeId) */
-            else if (npeId == IX_NPEDL_NPEID_NPEB)
-            {
-                if (ixFeatureCtrlComponentCheck(IX_FEATURECTRL_NPEB)==
-                    IX_FEATURE_CTRL_COMPONENT_DISABLED)
-                {
-                    IX_NPEDL_WARNING_REPORT("Warning: the NPE B component you specified"
-                                            " does not exist\n");
-                    return IX_SUCCESS;
-                }
-            } /* end of elseif(npeId) */
-            else if (npeId == IX_NPEDL_NPEID_NPEC)
-            {
-                if (ixFeatureCtrlComponentCheck(IX_FEATURECTRL_NPEC)==
-                    IX_FEATURE_CTRL_COMPONENT_DISABLED)
-                {
-                    IX_NPEDL_WARNING_REPORT("Warning: the NPE C component you specified"
-                                            " does not exist\n");
-                    return IX_SUCCESS;
-                }
-            } /* end of elseif(npeId) */
-        } /* end of if not IXP42X-A0 Silicon */
-
-        /* stop and reset the NPE */
-        status = ixNpeDlNpeStopAndReset (npeId);
-        if (IX_SUCCESS != status)
-        {
-            IX_NPEDL_ERROR_REPORT ("Failed to stop and reset NPE\n");
-            return status;
-        }
-
-        /* Locate image */
-        status = ixNpeDlImageMgrImageFind (imageLibrary, imageId,
-                                           &imageCodePtr, &imageSize);
-        if (IX_SUCCESS == status)
-        {
-            /*
-             * If download was successful, store image Id in list of
-             * currently loaded images. If a critical error occured
-             * during download, record that the NPE has an invalid image
-             */
-            status = ixNpeDlNpeMgrImageLoad (npeId, imageCodePtr, true);
-            if (IX_SUCCESS == status)
-            {
-                ixNpeDlNpeState[npeId].validImage = true;
-                ixNpeDlStats.successfulDownloads++;
-
-                status = ixNpeDlNpeExecutionStart (npeId);
-            }
-            else if ((status == IX_NPEDL_CRITICAL_NPE_ERR) ||
-                     (status == IX_NPEDL_CRITICAL_MICROCODE_ERR))
-            {
-                ixNpeDlNpeState[npeId].validImage = false;
-                ixNpeDlStats.criticalFailDownloads++;
-            }
-
-            /* NOTE - The following section of code is here to support
-             * a deprecated function ixNpeDlLoadedImageGet().  When that
-             * function is removed from the API, this code should be revised.
-             */
-            ixNpeDlNpeState[npeId].imageId.npeId = npeId;
-            ixNpeDlNpeState[npeId].imageId.functionalityId =
-                IX_NPEDL_FUNCTIONID_FROM_IMAGEID_GET(imageId);
-            ixNpeDlNpeState[npeId].imageId.major =
-                IX_NPEDL_MAJOR_FROM_IMAGEID_GET(imageId);
-            ixNpeDlNpeState[npeId].imageId.minor =
-                IX_NPEDL_MINOR_FROM_IMAGEID_GET(imageId);
-        } /* end of if(IX_SUCCESS) */ /* condition: image located successfully in microcode image */
-    } /* end of if-else(npeId-deviceId) */ /* condition: parameter checks ok */
-
-    IX_NPEDL_TRACE1 (IX_NPEDL_FN_ENTRY_EXIT,
-                     "Exiting ixNpeDlNpeInitAndStartInternal : "
-                     "status = %d\n", status);
-    return status;
-}
-
-/*
- * Function definition: ixNpeDlCustomImageNpeInitAndStart
- */
-PUBLIC IX_STATUS
-ixNpeDlCustomImageNpeInitAndStart (UINT32 *imageLibrary,
-                                   UINT32 imageId)
-{
-    IX_STATUS status;
-
-    if (imageLibrary == NULL)
-    {
-        status = IX_NPEDL_PARAM_ERR;
-        IX_NPEDL_ERROR_REPORT ("ixNpeDlCustomImageNpeInitAndStart "
-                               "- invalid parameter\n");
-    }
-    else
-    {
-        status = ixNpeDlNpeInitAndStartInternal (imageLibrary, imageId);
-    } /* end of if-else(imageLibrary) */
-
-    return status;
-}
-
-/*
- * Function definition: ixNpeDlNpeInitAndStart
- */
-PUBLIC IX_STATUS
-ixNpeDlNpeInitAndStart (UINT32 imageId)
-{
-    return ixNpeDlNpeInitAndStartInternal (NULL, imageId);
-}
-
-/*
- * Function definition: ixNpeDlLoadedImageFunctionalityGet
- */
-PUBLIC IX_STATUS
-ixNpeDlLoadedImageFunctionalityGet (IxNpeDlNpeId npeId,
-                                    UINT8 *functionalityId)
-{
-    /* Check input parameters */
-    if ((npeId >= IX_NPEDL_NPEID_MAX) || (npeId < 0))
-    {
-        IX_NPEDL_ERROR_REPORT ("ixNpeDlLoadedImageFunctionalityGet "
-                               "- invalid parameter\n");
-        return IX_NPEDL_PARAM_ERR;
-    }
-    if (functionalityId == NULL)
-    {
-        IX_NPEDL_ERROR_REPORT ("ixNpeDlLoadedImageFunctionalityGet "
-                               "- invalid parameter\n");
-        return IX_NPEDL_PARAM_ERR;
-    }
-
-    if (ixNpeDlNpeState[npeId].validImage)
-    {
-        *functionalityId = ixNpeDlNpeState[npeId].imageId.functionalityId;
-        return IX_SUCCESS;
-    }
-    else
-    {
-        return IX_FAIL;
-    }
-}
diff --git a/drivers/net/npe/IxNpeDlImageMgr.c b/drivers/net/npe/IxNpeDlImageMgr.c
deleted file mode 100644
index 52f73d7ad8..0000000000
--- a/drivers/net/npe/IxNpeDlImageMgr.c
+++ /dev/null
@@ -1,663 +0,0 @@
-/**
- * @file IxNpeDlImageMgr.c
- *
- * @author Intel Corporation
- * @date 09 January 2002
- *
- * @brief This file contains the implementation of the private API for the 
- *        IXP425 NPE Downloader ImageMgr module
- *
- * 
- * @par
- * IXP400 SW Release version 2.0
- * 
- * -- Copyright Notice --
- * 
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- * 
- * @par
- * SPDX-License-Identifier:	BSD-3-Clause
- * @par
- * -- End of Copyright Notice --
-*/
-
-
-/*
- * Put the system defined include files required.
- */
-#include "IxOsal.h"
-
-/*
- * Put the user defined include files required.
- */
-#include "IxNpeDlImageMgr_p.h"
-#include "IxNpeDlMacros_p.h"
-
-/*
- * define the flag which toggles the firmare inclusion
- */
-#define IX_NPE_MICROCODE_FIRMWARE_INCLUDED 1
-#include "IxNpeMicrocode.h"
-
-/*
- * Indicates the start of an NPE Image, in new NPE Image Library format.
- * 2 consecutive occurances indicates the end of the NPE Image Library
- */
-#define NPE_IMAGE_MARKER 0xfeedf00d
-
-/*
- * Typedefs whose scope is limited to this file.
- */
-
-/*
- * FOR BACKWARD-COMPATIBILITY WITH OLD NPE IMAGE LIBRARY FORMAT
- * TO BE DEPRECATED IN A FUTURE RELEASE
- */
-typedef struct
-{
-    UINT32 size;
-    UINT32 offset;
-    UINT32 id;
-} IxNpeDlImageMgrImageEntry;
-
-/*
- * FOR BACKWARD-COMPATIBILITY WITH OLD NPE IMAGE LIBRARY FORMAT
- * TO BE DEPRECATED IN A FUTURE RELEASE
- */
-typedef union
-{
-    IxNpeDlImageMgrImageEntry image;
-    UINT32 eohMarker;
-} IxNpeDlImageMgrHeaderEntry;
-
-/*
- * FOR BACKWARD-COMPATIBILITY WITH OLD NPE IMAGE LIBRARY FORMAT
- * TO BE DEPRECATED IN A FUTURE RELEASE
- */
-typedef struct
-{
-    UINT32 signature;
-    /* 1st entry in the header (there may be more than one) */
-    IxNpeDlImageMgrHeaderEntry entry[1];
-} IxNpeDlImageMgrImageLibraryHeader;
-
-
-/*
- * NPE Image Header definition, used in new NPE Image Library format
- */
-typedef struct
-{
-    UINT32 marker;
-    UINT32 id;
-    UINT32 size;
-} IxNpeDlImageMgrImageHeader;
-
-/* module statistics counters */
-typedef struct
-{
-    UINT32 invalidSignature;
-    UINT32 imageIdListOverflow;
-    UINT32 imageIdNotFound;
-} IxNpeDlImageMgrStats;
-
-
-/*
- * Variable declarations global to this file only.  Externs are followed by
- * static variables.
- */
-static IxNpeDlImageMgrStats ixNpeDlImageMgrStats;
-
-static UINT32* getIxNpeMicroCodeImageLibrary(void)
-{
-	char *s;
-
-	if ((s = getenv("npe_ucode")) != NULL)
-		return (UINT32*) simple_strtoul(s, NULL, 16);
-	else
-		return NULL;
-}
-
-/*
- * static function prototypes.
- */
-PRIVATE BOOL
-ixNpeDlImageMgrSignatureCheck (UINT32 *microCodeImageLibrary);
-
-PRIVATE void  
-ixNpeDlImageMgrImageIdFormat (UINT32 rawImageId, IxNpeDlImageId *imageId);
-
-PRIVATE BOOL
-ixNpeDlImageMgrImageIdCompare (IxNpeDlImageId *imageIdA, 
-				 IxNpeDlImageId *imageIdB);
-				 
-PRIVATE BOOL
-ixNpeDlImageMgrNpeFunctionIdCompare (IxNpeDlImageId *imageIdA,
-				       IxNpeDlImageId *imageIdB);
-
-#if 0
-PRIVATE IX_STATUS
-ixNpeDlImageMgrImageFind_legacy (UINT32 *imageLibrary,
-                                 UINT32 imageId,
-                                 UINT32 **imagePtr,
-                                 UINT32 *imageSize);
-
-/*
- * Function definition: ixNpeDlImageMgrMicrocodeImageLibraryOverride
- *
- * FOR BACKWARD-COMPATIBILITY WITH OLD NPE IMAGE LIBRARY FORMAT
- * AND/OR LEGACY API FUNCTIONS. TO BE DEPRECATED IN A FUTURE RELEASE
- */
-IX_STATUS
-ixNpeDlImageMgrMicrocodeImageLibraryOverride (
-    UINT32 *clientImageLibrary)
-{
-    IX_STATUS status = IX_SUCCESS;
-
-    IX_NPEDL_TRACE0 (IX_NPEDL_FN_ENTRY_EXIT, 
-		     "Entering ixNpeDlImageMgrMicrocodeImageLibraryOverride\n");
-
-    if (ixNpeDlImageMgrSignatureCheck (clientImageLibrary))
-    {
-	IxNpeMicroCodeImageLibrary = clientImageLibrary;
-    }
-    else
-    {
-	IX_NPEDL_ERROR_REPORT ("ixNpeDlImageMgrMicrocodeImageLibraryOverride: "
-			       "Client-supplied image has invalid signature\n");
-	status = IX_FAIL;
-    }
-
-    IX_NPEDL_TRACE1 (IX_NPEDL_FN_ENTRY_EXIT, 
-		     "Exiting ixNpeDlImageMgrMicrocodeImageLibraryOverride: status = %d\n",
-		     status);
-    return status;
-}
-#endif
-
-/*
- * Function definition: ixNpeDlImageMgrImageListExtract
- *
- * FOR BACKWARD-COMPATIBILITY WITH OLD NPE IMAGE LIBRARY FORMAT
- * AND/OR LEGACY API FUNCTIONS. TO BE DEPRECATED IN A FUTURE RELEASE
- */
-IX_STATUS
-ixNpeDlImageMgrImageListExtract (
-    IxNpeDlImageId *imageListPtr,
-    UINT32 *numImages)
-{
-    UINT32 rawImageId;
-    IxNpeDlImageId formattedImageId;
-    IX_STATUS status = IX_SUCCESS;
-    UINT32 imageCount = 0;
-    IxNpeDlImageMgrImageLibraryHeader *header;
-
-    IX_NPEDL_TRACE0 (IX_NPEDL_FN_ENTRY_EXIT, 
-		     "Entering ixNpeDlImageMgrImageListExtract\n");
-
-    header = (IxNpeDlImageMgrImageLibraryHeader *) getIxNpeMicroCodeImageLibrary();
-
-    if (ixNpeDlImageMgrSignatureCheck (getIxNpeMicroCodeImageLibrary()))
-    {
-	/* for each image entry in the image header ... */
-	while (header->entry[imageCount].eohMarker !=
-	       IX_NPEDL_IMAGEMGR_END_OF_HEADER)
-	{
-	    /*
-	     * if the image list container from calling function has capacity,
-	     * add the image id to the list 
-	     */
-	    if ((imageListPtr != NULL) && (imageCount < *numImages))
-	    {
-		rawImageId = header->entry[imageCount].image.id;
-	        ixNpeDlImageMgrImageIdFormat (rawImageId, &formattedImageId);
-		imageListPtr[imageCount] = formattedImageId;
-	    }
-	    /* imageCount reflects no. of image entries in image library header */
-	    imageCount++;  
-	}
-	
-	/*
-	 * if image list container from calling function was too small to
-	 * contain all image ids in the header, set return status to FAIL
-	 */
-	if ((imageListPtr != NULL) && (imageCount > *numImages))
-	{
-	    status = IX_FAIL;
-	    IX_NPEDL_ERROR_REPORT ("ixNpeDlImageMgrImageListExtract: "
-				   "number of Ids found exceeds list capacity\n");
-	    ixNpeDlImageMgrStats.imageIdListOverflow++;
-	}
-	/* return number of image ids found in image library header */
-	*numImages = imageCount;  
-    }
-    else
-    {
-	status = IX_FAIL;
-	IX_NPEDL_ERROR_REPORT ("ixNpeDlImageMgrImageListExtract: "
-			       "invalid signature in image\n");
-    }
-    
-    IX_NPEDL_TRACE1 (IX_NPEDL_FN_ENTRY_EXIT, 
-		     "Exiting ixNpeDlImageMgrImageListExtract: status = %d\n",
-		     status);
-    return status;
-}
-
-
-/*
- * Function definition: ixNpeDlImageMgrImageLocate
- *
- * FOR BACKWARD-COMPATIBILITY WITH OLD NPE IMAGE LIBRARY FORMAT
- * AND/OR LEGACY API FUNCTIONS. TO BE DEPRECATED IN A FUTURE RELEASE
- */
-IX_STATUS
-ixNpeDlImageMgrImageLocate (
-    IxNpeDlImageId *imageId,
-    UINT32 **imagePtr,
-    UINT32 *imageSize)
-{
-    UINT32 imageOffset;
-    UINT32 rawImageId;
-    IxNpeDlImageId formattedImageId;
-    /* used to index image entries in image library header */
-    UINT32 imageCount = 0;   
-    IX_STATUS status = IX_FAIL;
-    IxNpeDlImageMgrImageLibraryHeader *header;
-
-    IX_NPEDL_TRACE0 (IX_NPEDL_FN_ENTRY_EXIT,
-		     "Entering ixNpeDlImageMgrImageLocate\n");
-
-    header = (IxNpeDlImageMgrImageLibraryHeader *) getIxNpeMicroCodeImageLibrary();
-
-    if (ixNpeDlImageMgrSignatureCheck (getIxNpeMicroCodeImageLibrary()))
-    {
-	/* for each image entry in the image library header ... */
-	while (header->entry[imageCount].eohMarker !=
-	       IX_NPEDL_IMAGEMGR_END_OF_HEADER)
-	{
-	    rawImageId = header->entry[imageCount].image.id;
-	    ixNpeDlImageMgrImageIdFormat (rawImageId, &formattedImageId);
-	    /* if a match for imageId is found in the image library header... */
-	    if (ixNpeDlImageMgrImageIdCompare (imageId, &formattedImageId))
-	    {
-		/*
-		 * get pointer to the image in the image library using offset from
-		 * 1st word in image library
-		 */
-		UINT32 *tmp=getIxNpeMicroCodeImageLibrary();
-		imageOffset = header->entry[imageCount].image.offset;
-		*imagePtr = &tmp[imageOffset];
-		/* get the image size */
-		*imageSize = header->entry[imageCount].image.size;
-		status = IX_SUCCESS;
-		break;
-	    }
-	    imageCount++;
-	}
-	if (status != IX_SUCCESS)
-	{
-	    IX_NPEDL_ERROR_REPORT ("ixNpeDlImageMgrImageLocate: "
-				   "imageId not found in image library header\n");
-	    ixNpeDlImageMgrStats.imageIdNotFound++;
-	}
-    }
-    else
-    {
-	IX_NPEDL_ERROR_REPORT ("ixNpeDlImageMgrImageLocate: "
-			       "invalid signature in image library\n");
-    }
-
-    IX_NPEDL_TRACE1 (IX_NPEDL_FN_ENTRY_EXIT,
-		     "Exiting ixNpeDlImageMgrImageLocate: status = %d\n", status);
-    return status;
-}
-
-/*
- * Function definition: ixNpeDlImageMgrLatestImageExtract
- *
- * FOR BACKWARD-COMPATIBILITY WITH OLD NPE IMAGE LIBRARY FORMAT
- * AND/OR LEGACY API FUNCTIONS. TO BE DEPRECATED IN A FUTURE RELEASE
- */
-IX_STATUS
-ixNpeDlImageMgrLatestImageExtract (IxNpeDlImageId *imageId)
-{
-    UINT32 imageCount = 0; 
-    UINT32 rawImageId;
-    IxNpeDlImageId formattedImageId;
-    IX_STATUS status = IX_FAIL;
-    IxNpeDlImageMgrImageLibraryHeader *header;
-    
-    
-    IX_NPEDL_TRACE0 (IX_NPEDL_FN_ENTRY_EXIT,
-		     "Entering ixNpeDlImageMgrLatestImageExtract\n");
-		     
-    header = (IxNpeDlImageMgrImageLibraryHeader *) getIxNpeMicroCodeImageLibrary();
-    
-    if (ixNpeDlImageMgrSignatureCheck (getIxNpeMicroCodeImageLibrary()))
-    {
-	/* for each image entry in the image library header ... */
-	while (header->entry[imageCount].eohMarker !=
-	       IX_NPEDL_IMAGEMGR_END_OF_HEADER)
-	{
-	    rawImageId = header->entry[imageCount].image.id;
-	    ixNpeDlImageMgrImageIdFormat (rawImageId, &formattedImageId);
-	    /* 
-	     * if a match for the npe Id and functionality Id of the imageId is
-	     *  found in the image library header... 
-	     */
-            if(ixNpeDlImageMgrNpeFunctionIdCompare(imageId, &formattedImageId))
-            {
-                if(imageId->major <= formattedImageId.major)
-                {
-                    if(imageId->minor < formattedImageId.minor)
-                    {
-                        imageId->minor = formattedImageId.minor;
-                    }
-                    imageId->major = formattedImageId.major;
-                }
-                status = IX_SUCCESS;
-            }
-            imageCount++;
-	}
-	if (status != IX_SUCCESS)
-	{
-	    IX_NPEDL_ERROR_REPORT ("ixNpeDlImageMgrLatestImageExtract: "
-				   "imageId not found in image library header\n");
-	    ixNpeDlImageMgrStats.imageIdNotFound++;
-	}
-    }
-    else
-    {
-	IX_NPEDL_ERROR_REPORT ("ixNpeDlImageMgrLatestImageGet: "
-			       "invalid signature in image library\n");
-    }
-
-    IX_NPEDL_TRACE1 (IX_NPEDL_FN_ENTRY_EXIT,
-		     "Exiting ixNpeDlImageMgrLatestImageGet: status = %d\n", status);
-    return status;
-}
-
-/*
- * Function definition: ixNpeDlImageMgrSignatureCheck
- *
- * FOR BACKWARD-COMPATIBILITY WITH OLD NPE IMAGE LIBRARY FORMAT
- * AND/OR LEGACY API FUNCTIONS. TO BE DEPRECATED IN A FUTURE RELEASE
- */
-PRIVATE BOOL
-ixNpeDlImageMgrSignatureCheck (UINT32 *microCodeImageLibrary)
-{
-    IxNpeDlImageMgrImageLibraryHeader *header =
-	(IxNpeDlImageMgrImageLibraryHeader *) microCodeImageLibrary;
-    BOOL result = true;
-
-    if (!header || header->signature != IX_NPEDL_IMAGEMGR_SIGNATURE)
-    {
-	result = false;
-	ixNpeDlImageMgrStats.invalidSignature++;
-    }
-
-    return result;
-}
-
-
-/*
- * Function definition: ixNpeDlImageMgrImageIdFormat
- *
- * FOR BACKWARD-COMPATIBILITY WITH OLD NPE IMAGE LIBRARY FORMAT
- * AND/OR LEGACY API FUNCTIONS. TO BE DEPRECATED IN A FUTURE RELEASE
- */
-PRIVATE void
-ixNpeDlImageMgrImageIdFormat (
-    UINT32 rawImageId, 
-    IxNpeDlImageId *imageId)
-{  
-    imageId->npeId = (rawImageId >>
-				IX_NPEDL_IMAGEID_NPEID_OFFSET) &
-	IX_NPEDL_NPEIMAGE_FIELD_MASK;
-    imageId->functionalityId = (rawImageId >> 
-				  IX_NPEDL_IMAGEID_FUNCTIONID_OFFSET) &
-	IX_NPEDL_NPEIMAGE_FIELD_MASK;
-    imageId->major = (rawImageId >>
-				IX_NPEDL_IMAGEID_MAJOR_OFFSET) &
-	IX_NPEDL_NPEIMAGE_FIELD_MASK;
-    imageId->minor = (rawImageId >>
-				IX_NPEDL_IMAGEID_MINOR_OFFSET) &
-	IX_NPEDL_NPEIMAGE_FIELD_MASK;
-
-}
-
-
-/*
- * Function definition: ixNpeDlImageMgrImageIdCompare
- *
- * FOR BACKWARD-COMPATIBILITY WITH OLD NPE IMAGE LIBRARY FORMAT
- * AND/OR LEGACY API FUNCTIONS. TO BE DEPRECATED IN A FUTURE RELEASE
- */
-PRIVATE BOOL
-ixNpeDlImageMgrImageIdCompare (
-    IxNpeDlImageId *imageIdA,
-    IxNpeDlImageId *imageIdB)
-{
-    if ((imageIdA->npeId   == imageIdB->npeId)   &&
-	(imageIdA->functionalityId == imageIdB->functionalityId) &&
-	(imageIdA->major   == imageIdB->major)   &&
-	(imageIdA->minor   == imageIdB->minor))
-    {
-	return true;
-    }
-    else
-    {
-	return false;
-    }
-}
-
-/*
- * Function definition: ixNpeDlImageMgrNpeFunctionIdCompare
- *
- * FOR BACKWARD-COMPATIBILITY WITH OLD NPE IMAGE LIBRARY FORMAT
- * AND/OR LEGACY API FUNCTIONS. TO BE DEPRECATED IN A FUTURE RELEASE
- */
-PRIVATE BOOL
-ixNpeDlImageMgrNpeFunctionIdCompare (
-    IxNpeDlImageId *imageIdA,
-    IxNpeDlImageId *imageIdB)
-{
-    if ((imageIdA->npeId   == imageIdB->npeId)   &&
-	(imageIdA->functionalityId == imageIdB->functionalityId))
-    {
-	return true;
-    }
-    else
-    {
-	return false;
-    }
-}
-
-
-/*
- * Function definition: ixNpeDlImageMgrStatsShow
- */
-void
-ixNpeDlImageMgrStatsShow (void)
-{
-    ixOsalLog (IX_OSAL_LOG_LVL_USER,
-               IX_OSAL_LOG_DEV_STDOUT,
-               "\nixNpeDlImageMgrStatsShow:\n"
-               "\tInvalid Image Signatures: %u\n"
-               "\tImage Id List capacity too small: %u\n"
-               "\tImage Id not found: %u\n\n",
-               ixNpeDlImageMgrStats.invalidSignature,
-               ixNpeDlImageMgrStats.imageIdListOverflow,
-               ixNpeDlImageMgrStats.imageIdNotFound,
-               0,0,0);
-}
-
-
-/*
- * Function definition: ixNpeDlImageMgrStatsReset
- */
-void
-ixNpeDlImageMgrStatsReset (void)
-{
-    ixNpeDlImageMgrStats.invalidSignature = 0;
-    ixNpeDlImageMgrStats.imageIdListOverflow = 0;
-    ixNpeDlImageMgrStats.imageIdNotFound = 0;
-}
-
-
-#if 0
-/*
- * Function definition: ixNpeDlImageMgrImageFind_legacy
- *
- * FOR BACKWARD-COMPATIBILITY WITH OLD NPE IMAGE LIBRARY FORMAT
- * AND/OR LEGACY API FUNCTIONS. TO BE DEPRECATED IN A FUTURE RELEASE
- */
-PRIVATE IX_STATUS
-ixNpeDlImageMgrImageFind_legacy (
-    UINT32 *imageLibrary,
-    UINT32 imageId,
-    UINT32 **imagePtr,
-    UINT32 *imageSize)
-{
-    UINT32 imageOffset;
-    /* used to index image entries in image library header */
-    UINT32 imageCount = 0;   
-    IX_STATUS status = IX_FAIL;
-    IxNpeDlImageMgrImageLibraryHeader *header;
-    BOOL imageFound = false;
-
-    IX_NPEDL_TRACE0 (IX_NPEDL_FN_ENTRY_EXIT,
-		     "Entering ixNpeDlImageMgrImageFind\n");
-
-
-    /* If user didn't specify a library to use, use the default
-     * one from IxNpeMicrocode.h
-     */
-    if (imageLibrary == NULL)
-    {
-	imageLibrary = IxNpeMicroCodeImageLibrary;
-    }
-    
-    if (ixNpeDlImageMgrSignatureCheck (imageLibrary))
-    {
-	header = (IxNpeDlImageMgrImageLibraryHeader *) imageLibrary;
-    
-	/* for each image entry in the image library header ... */
-	while ((header->entry[imageCount].eohMarker !=
-               IX_NPEDL_IMAGEMGR_END_OF_HEADER) && !(imageFound))
-	{
-	    /* if a match for imageId is found in the image library header... */
-	    if (imageId == header->entry[imageCount].image.id)
-	    {
-		/*
-		 * get pointer to the image in the image library using offset from
-		 * 1st word in image library
-		 */
-		imageOffset = header->entry[imageCount].image.offset;
-		*imagePtr = &imageLibrary[imageOffset];
-		/* get the image size */
-		*imageSize = header->entry[imageCount].image.size;
-		status = IX_SUCCESS;
-		imageFound = true;
-	    }
-	    imageCount++;
-	}
-	if (status != IX_SUCCESS)
-	{
-	    IX_NPEDL_ERROR_REPORT ("ixNpeDlImageMgrImageFind: "
-				   "imageId not found in image library header\n");
-	    ixNpeDlImageMgrStats.imageIdNotFound++;
-	}
-    }
-    else
-    {
-	IX_NPEDL_ERROR_REPORT ("ixNpeDlImageMgrImageFind: "
-			       "invalid signature in image library\n");
-    }
-
-    IX_NPEDL_TRACE1 (IX_NPEDL_FN_ENTRY_EXIT,
-		     "Exiting ixNpeDlImageMgrImageFind: status = %d\n", status);
-    return status;
-}
-#endif
-
-/*
- * Function definition: ixNpeDlImageMgrImageFind
- */
-IX_STATUS
-ixNpeDlImageMgrImageFind (
-    UINT32 *imageLibrary,
-    UINT32 imageId,
-    UINT32 **imagePtr,
-    UINT32 *imageSize)
-{
-    IxNpeDlImageMgrImageHeader *image;
-    UINT32 offset = 0;
-
-    /* If user didn't specify a library to use, use the default
-     * one from IxNpeMicrocode.h
-     */
-    if (imageLibrary == NULL)
-    {
-#ifdef IX_NPEDL_READ_MICROCODE_FROM_FILE
-	if (ixNpeMicrocode_binaryArray == NULL)
-        {
-	    printk (KERN_ERR "ixp400.o:  ERROR, no Microcode found in memory\n");
-	    return IX_FAIL;
-	}
-	else
-	{
-	    imageLibrary = ixNpeMicrocode_binaryArray;
-	}
-#else
-	imageLibrary = getIxNpeMicroCodeImageLibrary();
-	if (imageLibrary == NULL)
-        {
-	    printf ("npe:  ERROR, no Microcode found in memory\n");
-	    return IX_FAIL;
-	}
-#endif /* IX_NPEDL_READ_MICROCODE_FROM_FILE */
-    }
-
-#if 0
-    /* For backward's compatibility with previous image format */
-    if (ixNpeDlImageMgrSignatureCheck(imageLibrary))
-    {
-        return ixNpeDlImageMgrImageFind_legacy(imageLibrary,
-                                               imageId,
-                                               imagePtr,
-                                               imageSize);
-    }
-#endif
-
-    while (*(imageLibrary+offset) == NPE_IMAGE_MARKER)
-    {
-        image = (IxNpeDlImageMgrImageHeader *)(imageLibrary+offset);
-        offset += sizeof(IxNpeDlImageMgrImageHeader)/sizeof(UINT32);
-        
-        if (image->id == imageId)
-        {
-            *imagePtr = imageLibrary + offset;
-            *imageSize = image->size;
-            return IX_SUCCESS;
-        }
-        /* 2 consecutive NPE_IMAGE_MARKER's indicates end of library */
-        else if (image->id == NPE_IMAGE_MARKER)
-        {
-	    IX_NPEDL_ERROR_REPORT ("ixNpeDlImageMgrImageFind: "
-				   "imageId not found in image library header\n");
-	    ixNpeDlImageMgrStats.imageIdNotFound++;
-            /* reached end of library, image not found */
-            return IX_FAIL;
-        }
-        offset += image->size;
-    }
-
-    /* If we get here, our image library may be corrupted */
-    IX_NPEDL_ERROR_REPORT ("ixNpeDlImageMgrImageFind: "
-                           "image library format may be invalid or corrupted\n");
-    return IX_FAIL;
-}
-
diff --git a/drivers/net/npe/IxNpeDlNpeMgr.c b/drivers/net/npe/IxNpeDlNpeMgr.c
deleted file mode 100644
index 8d94dfac3d..0000000000
--- a/drivers/net/npe/IxNpeDlNpeMgr.c
+++ /dev/null
@@ -1,907 +0,0 @@
-/**
- * @file IxNpeDlNpeMgr.c
- *
- * @author Intel Corporation
- * @date 09 January 2002
- *
- * @brief This file contains the implementation of the private API for the
- *        IXP425 NPE Downloader NpeMgr module
- *
- * 
- * @par
- * IXP400 SW Release version 2.0
- * 
- * -- Copyright Notice --
- * 
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- * 
- * @par
- * SPDX-License-Identifier:	BSD-3-Clause
- * @par
- * -- End of Copyright Notice --
-*/
-
-
-/*
- * Put the user defined include files required.
- */
-#include "IxOsal.h"
-#include "IxNpeDl.h"
-#include "IxNpeDlNpeMgr_p.h"
-#include "IxNpeDlNpeMgrUtils_p.h"
-#include "IxNpeDlNpeMgrEcRegisters_p.h"
-#include "IxNpeDlMacros_p.h"
-#include "IxFeatureCtrl.h"
-
-/*
- * #defines and macros used in this file.
- */
-#define IX_NPEDL_BYTES_PER_WORD                   4
-
-/* used to read download map from version in microcode image */
-#define IX_NPEDL_BLOCK_TYPE_INSTRUCTION           0x00000000
-#define IX_NPEDL_BLOCK_TYPE_DATA                  0x00000001
-#define IX_NPEDL_BLOCK_TYPE_STATE                 0x00000002
-#define IX_NPEDL_END_OF_DOWNLOAD_MAP              0x0000000F
-
-/*
- * masks used to extract address info from State information context
- * register addresses as read from microcode image 
- */
-#define IX_NPEDL_MASK_STATE_ADDR_CTXT_REG         0x0000000F
-#define IX_NPEDL_MASK_STATE_ADDR_CTXT_NUM         0x000000F0
-
-/* LSB offset of Context Number field in State-Info Context Address */
-#define IX_NPEDL_OFFSET_STATE_ADDR_CTXT_NUM       4
-
-/* size (in words) of single State Information entry (ctxt reg address|data) */
-#define IX_NPEDL_STATE_INFO_ENTRY_SIZE            2
-
-
- #define IX_NPEDL_RESET_NPE_PARITY  0x0800
- #define IX_NPEDL_PARITY_BIT_MASK   0x3F00FFFF
- #define IX_NPEDL_CONFIG_CTRL_REG_MASK  0x3F3FFFFF
-
-
-/*
- * Typedefs whose scope is limited to this file.
- */
-
-typedef struct
-{
-    UINT32 type;
-    UINT32 offset;
-} IxNpeDlNpeMgrDownloadMapBlockEntry;
-
-typedef union
-{
-    IxNpeDlNpeMgrDownloadMapBlockEntry block;
-    UINT32 eodmMarker;
-} IxNpeDlNpeMgrDownloadMapEntry;
-
-typedef struct
-{
-    /* 1st entry in the download map (there may be more than one) */
-    IxNpeDlNpeMgrDownloadMapEntry entry[1];
-} IxNpeDlNpeMgrDownloadMap;
-
-
-/* used to access an instruction or data block in a microcode image */
-typedef struct
-{
-    UINT32 npeMemAddress;
-    UINT32 size;
-    UINT32 data[1];
-} IxNpeDlNpeMgrCodeBlock;
-
-/* used to access each Context Reg entry state-information block */
-typedef struct
-{
-    UINT32 addressInfo;
-    UINT32 value;
-} IxNpeDlNpeMgrStateInfoCtxtRegEntry;
-
-/* used to access a state-information block in a microcode image */
-typedef struct
-{
-    UINT32 size;
-    IxNpeDlNpeMgrStateInfoCtxtRegEntry ctxtRegEntry[1];
-} IxNpeDlNpeMgrStateInfoBlock;
- 
-/* used to store some useful NPE information for easy access */
-typedef struct
-{
-    UINT32 baseAddress;
-    UINT32 insMemSize;
-    UINT32 dataMemSize;
-} IxNpeDlNpeInfo;
-
-/* used to distinguish instruction and data memory operations */
-typedef enum 
-{
-  IX_NPEDL_MEM_TYPE_INSTRUCTION = 0,
-  IX_NPEDL_MEM_TYPE_DATA
-} IxNpeDlNpeMemType;
-
-/* used to hold a reset value for a particular ECS register */
-typedef struct
-{
-    UINT32 regAddr;
-    UINT32 regResetVal;
-} IxNpeDlEcsRegResetValue;
-
-/* prototype of function to write either Instruction or Data memory */
-typedef IX_STATUS (*IxNpeDlNpeMgrMemWrite) (UINT32 npeBaseAddress,
-					    UINT32 npeMemAddress,
-					    UINT32 npeMemData,
-					    BOOL verify);
-
-/* module statistics counters */
-typedef struct
-{
-    UINT32 instructionBlocksLoaded;
-    UINT32 dataBlocksLoaded;
-    UINT32 stateInfoBlocksLoaded;
-    UINT32 criticalNpeErrors;
-    UINT32 criticalMicrocodeErrors;
-    UINT32 npeStarts;
-    UINT32 npeStops;
-    UINT32 npeResets;
-} IxNpeDlNpeMgrStats;
-
-
-/*
- * Variable declarations global to this file only.  Externs are followed by
- * static variables.
- */
-static IxNpeDlNpeInfo ixNpeDlNpeInfo[] =
-{
-    {
-	0,
-	IX_NPEDL_INS_MEMSIZE_WORDS_NPEA,
-	IX_NPEDL_DATA_MEMSIZE_WORDS_NPEA
-    },
-    {
-	0,
-	IX_NPEDL_INS_MEMSIZE_WORDS_NPEB,
-	IX_NPEDL_DATA_MEMSIZE_WORDS_NPEB
-    },
-    {
-	0,
-	IX_NPEDL_INS_MEMSIZE_WORDS_NPEC,
-	IX_NPEDL_DATA_MEMSIZE_WORDS_NPEC
-    }
-};
-
-/* contains Reset values for Context Store Registers  */
-static UINT32 ixNpeDlCtxtRegResetValues[] =
-{
-    IX_NPEDL_CTXT_REG_RESET_STEVT,
-    IX_NPEDL_CTXT_REG_RESET_STARTPC,
-    IX_NPEDL_CTXT_REG_RESET_REGMAP,
-    IX_NPEDL_CTXT_REG_RESET_CINDEX,
-};
-
-/* contains Reset values for Context Store Registers  */
-static IxNpeDlEcsRegResetValue ixNpeDlEcsRegResetValues[] =
-{
-    {IX_NPEDL_ECS_BG_CTXT_REG_0,    IX_NPEDL_ECS_BG_CTXT_REG_0_RESET},
-    {IX_NPEDL_ECS_BG_CTXT_REG_1,    IX_NPEDL_ECS_BG_CTXT_REG_1_RESET},
-    {IX_NPEDL_ECS_BG_CTXT_REG_2,    IX_NPEDL_ECS_BG_CTXT_REG_2_RESET},
-    {IX_NPEDL_ECS_PRI_1_CTXT_REG_0, IX_NPEDL_ECS_PRI_1_CTXT_REG_0_RESET},
-    {IX_NPEDL_ECS_PRI_1_CTXT_REG_1, IX_NPEDL_ECS_PRI_1_CTXT_REG_1_RESET},
-    {IX_NPEDL_ECS_PRI_1_CTXT_REG_2, IX_NPEDL_ECS_PRI_1_CTXT_REG_2_RESET},
-    {IX_NPEDL_ECS_PRI_2_CTXT_REG_0, IX_NPEDL_ECS_PRI_2_CTXT_REG_0_RESET},
-    {IX_NPEDL_ECS_PRI_2_CTXT_REG_1, IX_NPEDL_ECS_PRI_2_CTXT_REG_1_RESET},
-    {IX_NPEDL_ECS_PRI_2_CTXT_REG_2, IX_NPEDL_ECS_PRI_2_CTXT_REG_2_RESET},
-    {IX_NPEDL_ECS_DBG_CTXT_REG_0,   IX_NPEDL_ECS_DBG_CTXT_REG_0_RESET},
-    {IX_NPEDL_ECS_DBG_CTXT_REG_1,   IX_NPEDL_ECS_DBG_CTXT_REG_1_RESET},
-    {IX_NPEDL_ECS_DBG_CTXT_REG_2,   IX_NPEDL_ECS_DBG_CTXT_REG_2_RESET},
-    {IX_NPEDL_ECS_INSTRUCT_REG,     IX_NPEDL_ECS_INSTRUCT_REG_RESET}
-};
-
-static IxNpeDlNpeMgrStats ixNpeDlNpeMgrStats;
-
-/* Set when NPE register memory has been mapped */
-static BOOL ixNpeDlMemInitialised = false;
-
-
-/*
- * static function prototypes.
- */
-PRIVATE IX_STATUS
-ixNpeDlNpeMgrMemLoad (IxNpeDlNpeId npeId, UINT32 npeBaseAddress,
-		      IxNpeDlNpeMgrCodeBlock *codeBlockPtr,
-		      BOOL verify, IxNpeDlNpeMemType npeMemType);
-PRIVATE IX_STATUS
-ixNpeDlNpeMgrStateInfoLoad (UINT32 npeBaseAddress,
-			    IxNpeDlNpeMgrStateInfoBlock *codeBlockPtr,
-			    BOOL verify);
-PRIVATE BOOL
-ixNpeDlNpeMgrBitsSetCheck (UINT32 npeBaseAddress, UINT32 regOffset,
-			   UINT32 expectedBitsSet);
-
-PRIVATE UINT32
-ixNpeDlNpeMgrBaseAddressGet (IxNpeDlNpeId npeId);
-
-/*
- * Function definition: ixNpeDlNpeMgrBaseAddressGet
- */
-PRIVATE UINT32
-ixNpeDlNpeMgrBaseAddressGet (IxNpeDlNpeId npeId)
-{
-    IX_OSAL_ASSERT (ixNpeDlMemInitialised);
-    return ixNpeDlNpeInfo[npeId].baseAddress;
-}
-
-
-/*
- * Function definition: ixNpeDlNpeMgrInit
- */
-void
-ixNpeDlNpeMgrInit (void)
-{
-    /* Only map the memory once */
-    if (!ixNpeDlMemInitialised)
-    {
-	UINT32 virtAddr;
-
-	/* map the register memory for NPE-A */
-	virtAddr = (UINT32) IX_OSAL_MEM_MAP (IX_NPEDL_NPEBASEADDRESS_NPEA,
-					    IX_OSAL_IXP400_NPEA_MAP_SIZE); 
-	IX_OSAL_ASSERT(virtAddr);
-	ixNpeDlNpeInfo[IX_NPEDL_NPEID_NPEA].baseAddress = virtAddr;
-
-	/* map the register memory for NPE-B */
-	virtAddr = (UINT32) IX_OSAL_MEM_MAP (IX_NPEDL_NPEBASEADDRESS_NPEB,
-					    IX_OSAL_IXP400_NPEB_MAP_SIZE); 
-	IX_OSAL_ASSERT(virtAddr);
-	ixNpeDlNpeInfo[IX_NPEDL_NPEID_NPEB].baseAddress = virtAddr;
-
-	/* map the register memory for NPE-C */
-	virtAddr = (UINT32) IX_OSAL_MEM_MAP (IX_NPEDL_NPEBASEADDRESS_NPEC,
-					    IX_OSAL_IXP400_NPEC_MAP_SIZE); 
-	IX_OSAL_ASSERT(virtAddr);
-	ixNpeDlNpeInfo[IX_NPEDL_NPEID_NPEC].baseAddress = virtAddr;
-
-	ixNpeDlMemInitialised = true;
-    }
-}
-
-
-/*
- * Function definition: ixNpeDlNpeMgrUninit
- */
-IX_STATUS
-ixNpeDlNpeMgrUninit (void)
-{
-    if (!ixNpeDlMemInitialised)
-    {
-	return IX_FAIL;
-    }
-
-    IX_OSAL_MEM_UNMAP (ixNpeDlNpeInfo[IX_NPEDL_NPEID_NPEA].baseAddress);
-    IX_OSAL_MEM_UNMAP (ixNpeDlNpeInfo[IX_NPEDL_NPEID_NPEB].baseAddress);
-    IX_OSAL_MEM_UNMAP (ixNpeDlNpeInfo[IX_NPEDL_NPEID_NPEC].baseAddress);
-
-    ixNpeDlNpeInfo[IX_NPEDL_NPEID_NPEA].baseAddress = 0;
-    ixNpeDlNpeInfo[IX_NPEDL_NPEID_NPEB].baseAddress = 0;
-    ixNpeDlNpeInfo[IX_NPEDL_NPEID_NPEC].baseAddress = 0;
-
-    ixNpeDlMemInitialised = false;
-
-    return IX_SUCCESS;
-}
-
-/*
- * Function definition: ixNpeDlNpeMgrImageLoad
- */
-IX_STATUS
-ixNpeDlNpeMgrImageLoad (
-    IxNpeDlNpeId npeId,
-    UINT32 *imageCodePtr,
-    BOOL verify)
-{
-    UINT32 npeBaseAddress;
-    IxNpeDlNpeMgrDownloadMap *downloadMap;
-    UINT32 *blockPtr;
-    UINT32 mapIndex = 0;
-    IX_STATUS status = IX_SUCCESS;
-    
-    IX_NPEDL_TRACE0 (IX_NPEDL_FN_ENTRY_EXIT,
-		     "Entering ixNpeDlNpeMgrImageLoad\n");
-
-    /* get base memory address of NPE from npeId */
-    npeBaseAddress = ixNpeDlNpeMgrBaseAddressGet (npeId);
-
-    /* check execution status of NPE to verify NPE Stop was successful */
-    if (!ixNpeDlNpeMgrBitsSetCheck (npeBaseAddress, IX_NPEDL_REG_OFFSET_EXCTL,
-				    IX_NPEDL_EXCTL_STATUS_STOP))
-    {
-	IX_NPEDL_ERROR_REPORT ("ixNpeDlNpeMgrImageDownload - "
-			       "NPE was not stopped before download\n");
-	status = IX_FAIL;
-    }
-    else
-    {
-	/*
-	 * Read Download Map, checking each block type and calling
-	 * appropriate function to perform download 
-	 */
-	downloadMap = (IxNpeDlNpeMgrDownloadMap *) imageCodePtr;
-	while ((downloadMap->entry[mapIndex].eodmMarker != 
-		IX_NPEDL_END_OF_DOWNLOAD_MAP)
-	       && (status == IX_SUCCESS))
-	{
-	    /* calculate pointer to block to be downloaded */
-	    blockPtr = imageCodePtr +
-		downloadMap->entry[mapIndex].block.offset;
-
-	    switch (downloadMap->entry[mapIndex].block.type)
-	    {
-	    case IX_NPEDL_BLOCK_TYPE_INSTRUCTION:
-		status = ixNpeDlNpeMgrMemLoad (npeId, npeBaseAddress, 
-					     (IxNpeDlNpeMgrCodeBlock *)blockPtr,
-					       verify,
-					       IX_NPEDL_MEM_TYPE_INSTRUCTION);
-		break;
-	    case IX_NPEDL_BLOCK_TYPE_DATA:
-		status = ixNpeDlNpeMgrMemLoad (npeId, npeBaseAddress,
-                                             (IxNpeDlNpeMgrCodeBlock *)blockPtr,
-					       verify, IX_NPEDL_MEM_TYPE_DATA);
-		break;
-	    case IX_NPEDL_BLOCK_TYPE_STATE:
-		status = ixNpeDlNpeMgrStateInfoLoad (npeBaseAddress,
-				       (IxNpeDlNpeMgrStateInfoBlock *) blockPtr,
-						     verify);
-		break;
-	    default:
-		IX_NPEDL_ERROR_REPORT ("ixNpeDlNpeMgrImageLoad: "
-				       "unknown block type in download map\n");
-		status = IX_NPEDL_CRITICAL_MICROCODE_ERR;
-		ixNpeDlNpeMgrStats.criticalMicrocodeErrors++;
-		break;
-	    }
-	    mapIndex++;
-	}/* loop: for each entry in download map, while status == SUCCESS */
-    }/* condition: NPE stopped before attempting download */
-    
-    IX_NPEDL_TRACE1 (IX_NPEDL_FN_ENTRY_EXIT, 
-		     "Exiting ixNpeDlNpeMgrImageLoad : status = %d\n",
-		     status);
-    return status;
-}
-
-
-/*
- * Function definition: ixNpeDlNpeMgrMemLoad
- */
-PRIVATE IX_STATUS
-ixNpeDlNpeMgrMemLoad (
-    IxNpeDlNpeId npeId,
-    UINT32 npeBaseAddress,
-    IxNpeDlNpeMgrCodeBlock *blockPtr,
-    BOOL verify,
-    IxNpeDlNpeMemType npeMemType)
-{
-    UINT32 npeMemAddress;
-    UINT32 blockSize;
-    UINT32 memSize = 0;
-    IxNpeDlNpeMgrMemWrite memWriteFunc = NULL;
-    UINT32 localIndex = 0;
-    IX_STATUS status = IX_SUCCESS;
-
-    IX_NPEDL_TRACE0 (IX_NPEDL_FN_ENTRY_EXIT,
-		     "Entering ixNpeDlNpeMgrMemLoad\n");
-    
-    /*
-     * select NPE EXCTL reg read/write commands depending on memory
-     * type (instruction/data) to be accessed
-     */
-    if (npeMemType == IX_NPEDL_MEM_TYPE_INSTRUCTION)
-    {
-	memSize = ixNpeDlNpeInfo[npeId].insMemSize;
-	memWriteFunc = (IxNpeDlNpeMgrMemWrite) ixNpeDlNpeMgrInsMemWrite;
-    }
-    else if (npeMemType == IX_NPEDL_MEM_TYPE_DATA)
-    {
-	memSize = ixNpeDlNpeInfo[npeId].dataMemSize;
-	memWriteFunc = (IxNpeDlNpeMgrMemWrite) ixNpeDlNpeMgrDataMemWrite;
-    }
-
-    /*
-     * NPE memory is loaded contiguously from each block, so only address
-     * of 1st word in block is needed
-     */
-    npeMemAddress = blockPtr->npeMemAddress;
-    /* number of words of instruction/data microcode in block to download */
-    blockSize = blockPtr->size;
-    if ((npeMemAddress + blockSize) > memSize)
-    {
-	IX_NPEDL_ERROR_REPORT ("ixNpeDlNpeMgrMemLoad: "
-			       "Block size too big for NPE memory\n");
-	status = IX_NPEDL_CRITICAL_MICROCODE_ERR;
-	ixNpeDlNpeMgrStats.criticalMicrocodeErrors++;
-    }
-    else
-    {
-	for (localIndex = 0; localIndex < blockSize; localIndex++)
-	{
-	    status = memWriteFunc (npeBaseAddress, npeMemAddress,
-				   blockPtr->data[localIndex], verify);
-
-	    if (status != IX_SUCCESS)
-	    {
-		IX_NPEDL_ERROR_REPORT ("ixNpeDlNpeMgrMemLoad: "
-				       "write to NPE memory failed\n");
-		status = IX_NPEDL_CRITICAL_NPE_ERR;
-		ixNpeDlNpeMgrStats.criticalNpeErrors++;
-		break;   /* abort download */
-	    }
-	    /* increment target (word)address in NPE memory */
-	    npeMemAddress++;   
-	}
-    }/* condition: block size will fit in NPE memory */
-
-    if (status == IX_SUCCESS)
-    {
-	if (npeMemType == IX_NPEDL_MEM_TYPE_INSTRUCTION)
-	{
-	    ixNpeDlNpeMgrStats.instructionBlocksLoaded++;
-	}
-	else if (npeMemType == IX_NPEDL_MEM_TYPE_DATA)
-	{
-	    ixNpeDlNpeMgrStats.dataBlocksLoaded++;
-	}
-    }
-
-    IX_NPEDL_TRACE1 (IX_NPEDL_FN_ENTRY_EXIT,
-		     "Exiting ixNpeDlNpeMgrMemLoad : status = %d\n", status);
-    return status;
-}
-
-
-/*
- * Function definition: ixNpeDlNpeMgrStateInfoLoad
- */
-PRIVATE IX_STATUS
-ixNpeDlNpeMgrStateInfoLoad (
-    UINT32 npeBaseAddress,
-    IxNpeDlNpeMgrStateInfoBlock *blockPtr,
-    BOOL verify)
-{
-    UINT32 blockSize;
-    UINT32 ctxtRegAddrInfo; 
-    UINT32 ctxtRegVal;
-    IxNpeDlCtxtRegNum ctxtReg; /* identifies Context Store reg (0-3) */
-    UINT32 ctxtNum;            /* identifies Context number (0-16)   */
-    UINT32 i;
-    IX_STATUS status = IX_SUCCESS;
-
-    IX_NPEDL_TRACE0 (IX_NPEDL_FN_ENTRY_EXIT,
-		     "Entering ixNpeDlNpeMgrStateInfoLoad\n");
-
-    /* block size contains number of words of state-info in block */
-    blockSize = blockPtr->size;
-    
-    ixNpeDlNpeMgrDebugInstructionPreExec (npeBaseAddress);
-
-    /* for each state-info context register entry in block */
-    for (i = 0; i < (blockSize/IX_NPEDL_STATE_INFO_ENTRY_SIZE); i++)
-    {
-	/* each state-info entry is 2 words (address, value) in length */
-	ctxtRegAddrInfo = (blockPtr->ctxtRegEntry[i]).addressInfo;
-	ctxtRegVal      = (blockPtr->ctxtRegEntry[i]).value;
-	
-	ctxtReg = (ctxtRegAddrInfo & IX_NPEDL_MASK_STATE_ADDR_CTXT_REG);
-	ctxtNum = (ctxtRegAddrInfo & IX_NPEDL_MASK_STATE_ADDR_CTXT_NUM) >> 
-	    IX_NPEDL_OFFSET_STATE_ADDR_CTXT_NUM;
-	
-	/* error-check Context Register No. and Context Number values  */
-	/* NOTE that there is no STEVT register for Context 0 */
-	if ((ctxtReg < 0) ||
-	    (ctxtReg >= IX_NPEDL_CTXT_REG_MAX) ||
-	    (ctxtNum > IX_NPEDL_CTXT_NUM_MAX) ||
-	    ((ctxtNum == 0) && (ctxtReg == IX_NPEDL_CTXT_REG_STEVT)))
-	{
-	    IX_NPEDL_ERROR_REPORT ("ixNpeDlNpeMgrStateInfoLoad: "
-				   "invalid Context Register Address\n");
-	    status = IX_NPEDL_CRITICAL_MICROCODE_ERR;
-	    ixNpeDlNpeMgrStats.criticalMicrocodeErrors++;
-	    break;   /* abort download */
-	}    
-	
-	status = ixNpeDlNpeMgrCtxtRegWrite (npeBaseAddress, ctxtNum, ctxtReg,
-					    ctxtRegVal, verify);
-	if (status != IX_SUCCESS)
-	{
-	    IX_NPEDL_ERROR_REPORT ("ixNpeDlNpeMgrStateInfoLoad: "
-				   "write of state-info to NPE failed\n");
-	    status = IX_NPEDL_CRITICAL_NPE_ERR;
-	    ixNpeDlNpeMgrStats.criticalNpeErrors++;
-	    break;   /* abort download */
-	}
-    }/* loop: for each context reg entry in State Info block */
-    
-    ixNpeDlNpeMgrDebugInstructionPostExec (npeBaseAddress);
-
-    if (status == IX_SUCCESS)
-    {
-	ixNpeDlNpeMgrStats.stateInfoBlocksLoaded++;
-    }
-
-    IX_NPEDL_TRACE1 (IX_NPEDL_FN_ENTRY_EXIT,
-		     "Exiting ixNpeDlNpeMgrStateInfoLoad : status = %d\n",
-		     status);
-    return status;
-}
-
-
-/*
- * Function definition: ixNpeDlNpeMgrNpeReset
- */
-IX_STATUS
-ixNpeDlNpeMgrNpeReset (
-    IxNpeDlNpeId npeId)
-{
-    UINT32 npeBaseAddress;
-    IxNpeDlCtxtRegNum ctxtReg; /* identifies Context Store reg (0-3) */
-    UINT32 ctxtNum;            /* identifies Context number (0-16)   */
-    UINT32 regAddr;
-    UINT32 regVal;
-    UINT32 localIndex;
-    UINT32 indexMax;
-    IX_STATUS status = IX_SUCCESS;
-    IxFeatureCtrlReg unitFuseReg;
-    UINT32 ixNpeConfigCtrlRegVal;
-    
-    IX_NPEDL_TRACE0 (IX_NPEDL_FN_ENTRY_EXIT, 
-		     "Entering ixNpeDlNpeMgrNpeReset\n");
-    
-    /* get base memory address of NPE from npeId */
-    npeBaseAddress = ixNpeDlNpeMgrBaseAddressGet (npeId);
-
-    /* pre-store the NPE Config Control Register Value */
-    IX_NPEDL_REG_READ (npeBaseAddress, IX_NPEDL_REG_OFFSET_CTL, &ixNpeConfigCtrlRegVal);
-    
-    ixNpeConfigCtrlRegVal |= 0x3F000000;
-    
-    /* disable the parity interrupt */
-    IX_NPEDL_REG_WRITE (npeBaseAddress, IX_NPEDL_REG_OFFSET_CTL, (ixNpeConfigCtrlRegVal & IX_NPEDL_PARITY_BIT_MASK));
-    
-    ixNpeDlNpeMgrDebugInstructionPreExec (npeBaseAddress);
-
-    /*
-     * clear the FIFOs
-     */
-    while (ixNpeDlNpeMgrBitsSetCheck (npeBaseAddress,
-				      IX_NPEDL_REG_OFFSET_WFIFO,
-				      IX_NPEDL_MASK_WFIFO_VALID))
-    {
-	/* read from the Watch-point FIFO until empty */
-	IX_NPEDL_REG_READ (npeBaseAddress, IX_NPEDL_REG_OFFSET_WFIFO,
-			   &regVal);
-    }
-    
-    while (ixNpeDlNpeMgrBitsSetCheck (npeBaseAddress,
-					  IX_NPEDL_REG_OFFSET_STAT,
-				      IX_NPEDL_MASK_STAT_OFNE))
-    {
-	/* read from the outFIFO until empty */
-	IX_NPEDL_REG_READ (npeBaseAddress, IX_NPEDL_REG_OFFSET_FIFO,
-			   &regVal);
-    }
-    
-    while (ixNpeDlNpeMgrBitsSetCheck (npeBaseAddress,
-				      IX_NPEDL_REG_OFFSET_STAT,
-				      IX_NPEDL_MASK_STAT_IFNE))
-    {
-	/*
-	 * step execution of the NPE intruction to read inFIFO using
-	 * the Debug Executing Context stack
-	 */
-	status = ixNpeDlNpeMgrDebugInstructionExec (npeBaseAddress,
-					   IX_NPEDL_INSTR_RD_FIFO, 0, 0);
-
-    if (IX_SUCCESS != status)
-    {
-        return status;   
-    }
-    
-    }
-    
-    /*
-     * Reset the mailbox reg
-     */
-    /* ...from XScale side */
-    IX_NPEDL_REG_WRITE (npeBaseAddress, IX_NPEDL_REG_OFFSET_MBST,
-			IX_NPEDL_REG_RESET_MBST);
-    /* ...from NPE side */
-    status = ixNpeDlNpeMgrDebugInstructionExec (npeBaseAddress,
-				       IX_NPEDL_INSTR_RESET_MBOX, 0, 0);
-
-    if (IX_SUCCESS != status)
-    {
-        return status;   
-    }
-
-    /* 
-     *   Reset the physical registers in the NPE register file:
-     *   Note: no need to save/restore REGMAP for Context 0 here
-     *   since all Context Store regs are reset in subsequent code
-     */
-    for (regAddr = 0;
-	 (regAddr < IX_NPEDL_TOTAL_NUM_PHYS_REG) && (status != IX_FAIL);
-	 regAddr++)
-    {
-	/* for each physical register in the NPE reg file, write 0 : */
-	status = ixNpeDlNpeMgrPhysicalRegWrite (npeBaseAddress, regAddr,
-						0, true);
-	if (status != IX_SUCCESS)
-	{
-	    return status;  /* abort reset */
-	}
-    }
-    
-
-    /*
-     * Reset the context store:
-     */
-    for (ctxtNum = IX_NPEDL_CTXT_NUM_MIN;
-	 ctxtNum <= IX_NPEDL_CTXT_NUM_MAX; ctxtNum++)
-    {	
-	/* set each context's Context Store registers to reset values: */
-	for (ctxtReg = 0; ctxtReg < IX_NPEDL_CTXT_REG_MAX; ctxtReg++)
-	{
-	    /* NOTE that there is no STEVT register for Context 0 */
-	    if (!((ctxtNum == 0) && (ctxtReg == IX_NPEDL_CTXT_REG_STEVT)))
-	    { 
-		regVal = ixNpeDlCtxtRegResetValues[ctxtReg];
-		status = ixNpeDlNpeMgrCtxtRegWrite (npeBaseAddress, ctxtNum,
-						    ctxtReg, regVal, true);
-		if (status != IX_SUCCESS)
-		{
-		    return status;  /* abort reset */
-		}
-	    }
-	}
-    }
-
-    ixNpeDlNpeMgrDebugInstructionPostExec (npeBaseAddress);
-
-    /* write Reset values to Execution Context Stack registers */
-    indexMax = sizeof (ixNpeDlEcsRegResetValues) /
-	sizeof (IxNpeDlEcsRegResetValue);
-    for (localIndex = 0; localIndex < indexMax; localIndex++)
-    {
-	regAddr = ixNpeDlEcsRegResetValues[localIndex].regAddr;
-	regVal = ixNpeDlEcsRegResetValues[localIndex].regResetVal;
-	ixNpeDlNpeMgrExecAccRegWrite (npeBaseAddress, regAddr, regVal);
-    }
-    
-    /* clear the profile counter */
-    ixNpeDlNpeMgrCommandIssue (npeBaseAddress, 
-			       IX_NPEDL_EXCTL_CMD_CLR_PROFILE_CNT);
-    
-    /* clear registers EXCT, AP0, AP1, AP2 and AP3 */
-    for (regAddr = IX_NPEDL_REG_OFFSET_EXCT;
-	     regAddr <= IX_NPEDL_REG_OFFSET_AP3;
-	 regAddr += IX_NPEDL_BYTES_PER_WORD)
-    {
-	IX_NPEDL_REG_WRITE (npeBaseAddress, regAddr, 0);
-    }
-    
-    /* Reset the Watch-count register */
-    IX_NPEDL_REG_WRITE (npeBaseAddress, IX_NPEDL_REG_OFFSET_WC, 0);
-    
-    /*
-     * WR IXA00055043 - Remove IMEM Parity Introduced by NPE Reset Operation
-     */
-
-    /*
-     * Call the feature control API to fused out and reset the NPE and its
-     * coprocessor - to reset internal states and remove parity error
-     */
-    unitFuseReg = ixFeatureCtrlRead ();
-    unitFuseReg |= (IX_NPEDL_RESET_NPE_PARITY << npeId);
-    ixFeatureCtrlWrite (unitFuseReg);
-
-    /* call the feature control API to un-fused and un-reset the NPE & COP */
-    unitFuseReg &= (~(IX_NPEDL_RESET_NPE_PARITY << npeId));
-    ixFeatureCtrlWrite (unitFuseReg);
-
-    /*
-     * Call NpeMgr function to stop the NPE again after the Feature Control
-     * has unfused and Un-Reset the NPE and its associated Coprocessors
-     */
-    status = ixNpeDlNpeMgrNpeStop (npeId);
-
-    /* restore NPE configuration bus Control Register - Parity Settings  */
-    IX_NPEDL_REG_WRITE (npeBaseAddress, IX_NPEDL_REG_OFFSET_CTL, 
-        (ixNpeConfigCtrlRegVal & IX_NPEDL_CONFIG_CTRL_REG_MASK));
-
-    ixNpeDlNpeMgrStats.npeResets++;
-
-    IX_NPEDL_TRACE1 (IX_NPEDL_FN_ENTRY_EXIT,
-		     "Exiting ixNpeDlNpeMgrNpeReset : status = %d\n", status);
-    return status;
-}
-
-
-/*
- * Function definition: ixNpeDlNpeMgrNpeStart
- */
-IX_STATUS
-ixNpeDlNpeMgrNpeStart (
-    IxNpeDlNpeId npeId)
-{
-    UINT32    npeBaseAddress;
-    UINT32    ecsRegVal;
-    BOOL      npeRunning;
-    IX_STATUS status = IX_SUCCESS;
-
-    IX_NPEDL_TRACE0 (IX_NPEDL_FN_ENTRY_EXIT, 
-		     "Entering ixNpeDlNpeMgrNpeStart\n");
-
-    /* get base memory address of NPE from npeId */
-    npeBaseAddress = ixNpeDlNpeMgrBaseAddressGet (npeId);
-
-    /*
-     * ensure only Background Context Stack Level is Active by turning off
-     * the Active bit in each of the other Executing Context Stack levels
-     */
-    ecsRegVal = ixNpeDlNpeMgrExecAccRegRead (npeBaseAddress,
-					     IX_NPEDL_ECS_PRI_1_CTXT_REG_0);
-    ecsRegVal &= ~IX_NPEDL_MASK_ECS_REG_0_ACTIVE;
-    ixNpeDlNpeMgrExecAccRegWrite (npeBaseAddress, IX_NPEDL_ECS_PRI_1_CTXT_REG_0,
-				  ecsRegVal);
-
-    ecsRegVal = ixNpeDlNpeMgrExecAccRegRead (npeBaseAddress,
-					     IX_NPEDL_ECS_PRI_2_CTXT_REG_0);
-    ecsRegVal &= ~IX_NPEDL_MASK_ECS_REG_0_ACTIVE;
-    ixNpeDlNpeMgrExecAccRegWrite (npeBaseAddress, IX_NPEDL_ECS_PRI_2_CTXT_REG_0,
-				  ecsRegVal);
-
-    ecsRegVal = ixNpeDlNpeMgrExecAccRegRead (npeBaseAddress,
-					     IX_NPEDL_ECS_DBG_CTXT_REG_0);
-    ecsRegVal &= ~IX_NPEDL_MASK_ECS_REG_0_ACTIVE;
-    ixNpeDlNpeMgrExecAccRegWrite (npeBaseAddress, IX_NPEDL_ECS_DBG_CTXT_REG_0,
-				  ecsRegVal);
-    
-    /* clear the pipeline */
-    ixNpeDlNpeMgrCommandIssue (npeBaseAddress, IX_NPEDL_EXCTL_CMD_NPE_CLR_PIPE);
-    
-    /* start NPE execution by issuing command through EXCTL register on NPE */
-    ixNpeDlNpeMgrCommandIssue (npeBaseAddress, IX_NPEDL_EXCTL_CMD_NPE_START);
-
-    /*
-     * check execution status of NPE to verify NPE Start operation was
-     * successful
-     */
-    npeRunning = ixNpeDlNpeMgrBitsSetCheck (npeBaseAddress,
-					    IX_NPEDL_REG_OFFSET_EXCTL,
-					    IX_NPEDL_EXCTL_STATUS_RUN);
-    if (npeRunning)
-    {
-	ixNpeDlNpeMgrStats.npeStarts++;
-    }
-    else
-    {
-	IX_NPEDL_ERROR_REPORT ("ixNpeDlNpeMgrNpeStart: "
-			       "failed to start NPE execution\n");
-	status = IX_FAIL;
-    }
-
-    
-    IX_NPEDL_TRACE1 (IX_NPEDL_FN_ENTRY_EXIT,
-		     "Exiting ixNpeDlNpeMgrNpeStart : status = %d\n", status);
-    return status;
-}
-
-
-/*
- * Function definition: ixNpeDlNpeMgrNpeStop
- */
-IX_STATUS
-ixNpeDlNpeMgrNpeStop (
-    IxNpeDlNpeId npeId)
-{
-    UINT32    npeBaseAddress;
-    IX_STATUS status = IX_SUCCESS;
-    
-    IX_NPEDL_TRACE0 (IX_NPEDL_FN_ENTRY_EXIT,
-		     "Entering ixNpeDlNpeMgrNpeStop\n");
-    
-    /* get base memory address of NPE from npeId */
-    npeBaseAddress = ixNpeDlNpeMgrBaseAddressGet (npeId);
-
-    /* stop NPE execution by issuing command through EXCTL register on NPE */
-    ixNpeDlNpeMgrCommandIssue (npeBaseAddress, IX_NPEDL_EXCTL_CMD_NPE_STOP);
-
-    /* verify that NPE Stop was successful */
-    if (! ixNpeDlNpeMgrBitsSetCheck (npeBaseAddress, IX_NPEDL_REG_OFFSET_EXCTL,
-				     IX_NPEDL_EXCTL_STATUS_STOP))
-    {
-	IX_NPEDL_ERROR_REPORT ("ixNpeDlNpeMgrNpeStop: "
-			       "failed to stop NPE execution\n");
-	status = IX_FAIL;
-    }
-
-    ixNpeDlNpeMgrStats.npeStops++;
-    
-    IX_NPEDL_TRACE1 (IX_NPEDL_FN_ENTRY_EXIT,
-		     "Exiting ixNpeDlNpeMgrNpeStop : status = %d\n", status);
-    return status;
-}
-
-
-/*
- * Function definition: ixNpeDlNpeMgrBitsSetCheck
- */
-PRIVATE BOOL
-ixNpeDlNpeMgrBitsSetCheck (
-    UINT32 npeBaseAddress,
-    UINT32 regOffset,
-    UINT32 expectedBitsSet)
-{
-    UINT32 regVal;
-    IX_NPEDL_REG_READ (npeBaseAddress, regOffset, &regVal);
-
-    return expectedBitsSet == (expectedBitsSet & regVal);
-}
-
-
-/*
- * Function definition: ixNpeDlNpeMgrStatsShow
- */
-void
-ixNpeDlNpeMgrStatsShow (void)
-{
-    ixOsalLog (IX_OSAL_LOG_LVL_USER,
-               IX_OSAL_LOG_DEV_STDOUT,
-               "\nixNpeDlNpeMgrStatsShow:\n"
-               "\tInstruction Blocks loaded: %u\n"
-               "\tData Blocks loaded: %u\n"
-               "\tState Information Blocks loaded: %u\n"
-               "\tCritical NPE errors: %u\n"
-               "\tCritical Microcode errors: %u\n",
-               ixNpeDlNpeMgrStats.instructionBlocksLoaded,
-               ixNpeDlNpeMgrStats.dataBlocksLoaded,
-               ixNpeDlNpeMgrStats.stateInfoBlocksLoaded,
-               ixNpeDlNpeMgrStats.criticalNpeErrors,
-               ixNpeDlNpeMgrStats.criticalMicrocodeErrors,
-               0);
-
-    ixOsalLog (IX_OSAL_LOG_LVL_USER,
-               IX_OSAL_LOG_DEV_STDOUT,
-               "\tSuccessful NPE Starts: %u\n"
-               "\tSuccessful NPE Stops: %u\n"
-               "\tSuccessful NPE Resets: %u\n\n",
-               ixNpeDlNpeMgrStats.npeStarts,
-               ixNpeDlNpeMgrStats.npeStops,
-               ixNpeDlNpeMgrStats.npeResets,
-               0,0,0);
-
-    ixNpeDlNpeMgrUtilsStatsShow ();
-}
-
-
-/*
- * Function definition: ixNpeDlNpeMgrStatsReset
- */
-void
-ixNpeDlNpeMgrStatsReset (void)
-{
-    ixNpeDlNpeMgrStats.instructionBlocksLoaded = 0;
-    ixNpeDlNpeMgrStats.dataBlocksLoaded = 0;
-    ixNpeDlNpeMgrStats.stateInfoBlocksLoaded = 0;
-    ixNpeDlNpeMgrStats.criticalNpeErrors = 0;
-    ixNpeDlNpeMgrStats.criticalMicrocodeErrors = 0;
-    ixNpeDlNpeMgrStats.npeStarts = 0;
-    ixNpeDlNpeMgrStats.npeStops = 0;
-    ixNpeDlNpeMgrStats.npeResets = 0;
-
-    ixNpeDlNpeMgrUtilsStatsReset ();
-}
diff --git a/drivers/net/npe/IxNpeDlNpeMgrUtils.c b/drivers/net/npe/IxNpeDlNpeMgrUtils.c
deleted file mode 100644
index db50d22d1b..0000000000
--- a/drivers/net/npe/IxNpeDlNpeMgrUtils.c
+++ /dev/null
@@ -1,782 +0,0 @@
-/**
- * @file IxNpeDlNpeMgrUtils.c
- *
- * @author Intel Corporation
- * @date 18 February 2002
- *
- * @brief This file contains the implementation of the private API for the 
- *        IXP425 NPE Downloader NpeMgr Utils module
- *
- * 
- * @par
- * IXP400 SW Release version 2.0
- * 
- * -- Copyright Notice --
- * 
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- * 
- * @par
- * SPDX-License-Identifier:	BSD-3-Clause
- * @par
- * -- End of Copyright Notice --
-*/
-
-
-/*
- * Put the system defined include files required.
- */
-#define IX_NPE_DL_MAX_NUM_OF_RETRIES 1000000 /**< Maximum number of
-                                              * retries before
-                                              * timeout
-					                          */  
-
-/*
- * Put the user defined include files required.
- */
-#include "IxOsal.h"
-#include "IxNpeDl.h"
-#include "IxNpeDlNpeMgrUtils_p.h"
-#include "IxNpeDlNpeMgrEcRegisters_p.h"
-#include "IxNpeDlMacros_p.h"
-
-/*
- * #defines and macros used in this file.
- */
-
-/* used to bit-mask a number of bytes */
-#define IX_NPEDL_MASK_LOWER_BYTE_OF_WORD  0x000000FF
-#define IX_NPEDL_MASK_LOWER_SHORT_OF_WORD 0x0000FFFF
-#define IX_NPEDL_MASK_FULL_WORD           0xFFFFFFFF
-
-#define IX_NPEDL_BYTES_PER_WORD           4
-#define IX_NPEDL_BYTES_PER_SHORT          2
-
-#define IX_NPEDL_REG_SIZE_BYTE            8
-#define IX_NPEDL_REG_SIZE_SHORT           16
-#define IX_NPEDL_REG_SIZE_WORD            32
-
-/*
- * Introduce extra read cycles after issuing read command to NPE
- * so that we read the register after the NPE has updated it
- * This is to overcome race condition between XScale and NPE
- */
-#define IX_NPEDL_DELAY_READ_CYCLES        2
-/*
- * To mask top three MSBs of 32bit word to download into NPE IMEM
- */
-#define IX_NPEDL_MASK_UNUSED_IMEM_BITS    0x1FFFFFFF;
-
-
-/*
- * typedefs
- */
-typedef struct
-{
-    UINT32 regAddress;
-    UINT32 regSize;
-} IxNpeDlCtxtRegAccessInfo;
-
-/* module statistics counters */
-typedef struct
-{
-    UINT32 insMemWrites;
-    UINT32 insMemWriteFails;
-    UINT32 dataMemWrites;
-    UINT32 dataMemWriteFails;
-    UINT32 ecsRegWrites;
-    UINT32 ecsRegReads;
-    UINT32 dbgInstructionExecs;
-    UINT32 contextRegWrites;
-    UINT32 physicalRegWrites;
-    UINT32 nextPcWrites;
-} IxNpeDlNpeMgrUtilsStats;
-
-
-/*
- * Variable declarations global to this file only.  Externs are followed by
- * static variables.
- */
-
-/* 
- * contains useful address and function pointers to read/write Context Regs, 
- * eliminating some switch or if-else statements in places
- */
-static IxNpeDlCtxtRegAccessInfo ixNpeDlCtxtRegAccInfo[IX_NPEDL_CTXT_REG_MAX] =
-{
-    {
-	IX_NPEDL_CTXT_REG_ADDR_STEVT,
-	IX_NPEDL_REG_SIZE_BYTE
-    },
-    {
-	IX_NPEDL_CTXT_REG_ADDR_STARTPC,
-	IX_NPEDL_REG_SIZE_SHORT
-    },
-    {
-	IX_NPEDL_CTXT_REG_ADDR_REGMAP,
-	IX_NPEDL_REG_SIZE_SHORT
-    },
-    {
-	IX_NPEDL_CTXT_REG_ADDR_CINDEX,
-	IX_NPEDL_REG_SIZE_BYTE
-    }
-};
-
-static UINT32 ixNpeDlSavedExecCount = 0;
-static UINT32 ixNpeDlSavedEcsDbgCtxtReg2 = 0;
-
-static IxNpeDlNpeMgrUtilsStats ixNpeDlNpeMgrUtilsStats;
-
-
-/*
- * static function prototypes.
- */
-PRIVATE __inline__ void
-ixNpeDlNpeMgrWriteCommandIssue (UINT32 npeBaseAddress, UINT32 cmd,
-				UINT32 addr, UINT32 data);
-
-PRIVATE __inline__ UINT32
-ixNpeDlNpeMgrReadCommandIssue (UINT32 npeBaseAddress, UINT32 cmd, UINT32 addr);
-
-PRIVATE IX_STATUS
-ixNpeDlNpeMgrLogicalRegRead (UINT32 npeBaseAddress, UINT32 regAddr,
-			     UINT32 regSize, UINT32 ctxtNum, UINT32 *regVal);
-
-PRIVATE IX_STATUS
-ixNpeDlNpeMgrLogicalRegWrite (UINT32 npeBaseAddress, UINT32 regAddr,
-			      UINT32 regVal, UINT32 regSize,
-			      UINT32 ctxtNum, BOOL verify);
-
-/*
- * Function definition: ixNpeDlNpeMgrWriteCommandIssue
- */
-PRIVATE __inline__ void
-ixNpeDlNpeMgrWriteCommandIssue (
-    UINT32 npeBaseAddress,
-    UINT32 cmd,
-    UINT32 addr,
-    UINT32 data)
-{
-    IX_NPEDL_REG_WRITE (npeBaseAddress, IX_NPEDL_REG_OFFSET_EXDATA, data);
-    IX_NPEDL_REG_WRITE (npeBaseAddress, IX_NPEDL_REG_OFFSET_EXAD, addr);
-    IX_NPEDL_REG_WRITE (npeBaseAddress, IX_NPEDL_REG_OFFSET_EXCTL, cmd);
-}
-
-
-/*
- * Function definition: ixNpeDlNpeMgrReadCommandIssue
- */
-PRIVATE __inline__ UINT32
-ixNpeDlNpeMgrReadCommandIssue (
-    UINT32 npeBaseAddress,
-    UINT32 cmd,
-    UINT32 addr)
-{
-    UINT32 data = 0;
-    int i;
-
-    IX_NPEDL_REG_WRITE (npeBaseAddress, IX_NPEDL_REG_OFFSET_EXAD, addr);
-    IX_NPEDL_REG_WRITE (npeBaseAddress, IX_NPEDL_REG_OFFSET_EXCTL, cmd);
-    for (i = 0; i <= IX_NPEDL_DELAY_READ_CYCLES; i++)
-    {
-	IX_NPEDL_REG_READ (npeBaseAddress, IX_NPEDL_REG_OFFSET_EXDATA, &data);
-    }
-
-    return data;
-}
-
-/*
- * Function definition: ixNpeDlNpeMgrInsMemWrite
- */
-IX_STATUS
-ixNpeDlNpeMgrInsMemWrite (
-    UINT32 npeBaseAddress,
-    UINT32 insMemAddress,
-    UINT32 insMemData,
-    BOOL verify)
-{
-    UINT32 insMemDataRtn;
-
-    ixNpeDlNpeMgrWriteCommandIssue (npeBaseAddress,
-				    IX_NPEDL_EXCTL_CMD_WR_INS_MEM,
-				    insMemAddress, insMemData);
-    if (verify)
-    {
-        /* write invalid data to this reg, so we can see if we're reading 
-	   the EXDATA register too early */
-	IX_NPEDL_REG_WRITE (npeBaseAddress, IX_NPEDL_REG_OFFSET_EXDATA,
-			    ~insMemData);
-
-        /*Disabled since top 3 MSB are not used for Azusa hardware Refer WR:IXA00053900*/
-        insMemData&=IX_NPEDL_MASK_UNUSED_IMEM_BITS;
-
-        insMemDataRtn=ixNpeDlNpeMgrReadCommandIssue (npeBaseAddress,
-                                           IX_NPEDL_EXCTL_CMD_RD_INS_MEM,
-                                           insMemAddress);
-
-        insMemDataRtn&=IX_NPEDL_MASK_UNUSED_IMEM_BITS;
-
-	if (insMemData != insMemDataRtn)
-	{
-	    ixNpeDlNpeMgrUtilsStats.insMemWriteFails++;
-	    return IX_FAIL;
-	}
-    }
-
-    ixNpeDlNpeMgrUtilsStats.insMemWrites++;
-    return IX_SUCCESS;
-}
-
-
-/*
- * Function definition: ixNpeDlNpeMgrDataMemWrite
- */
-IX_STATUS
-ixNpeDlNpeMgrDataMemWrite (
-    UINT32 npeBaseAddress,
-    UINT32 dataMemAddress,
-    UINT32 dataMemData,
-    BOOL verify)
-{
-    ixNpeDlNpeMgrWriteCommandIssue (npeBaseAddress,
-				    IX_NPEDL_EXCTL_CMD_WR_DATA_MEM,
-				    dataMemAddress, dataMemData);
-    if (verify)
-    {
-        /* write invalid data to this reg, so we can see if we're reading 
-	   the EXDATA register too early */
-	IX_NPEDL_REG_WRITE (npeBaseAddress, IX_NPEDL_REG_OFFSET_EXDATA, ~dataMemData);
-
-	if (dataMemData !=
-	    ixNpeDlNpeMgrReadCommandIssue (npeBaseAddress,
-					   IX_NPEDL_EXCTL_CMD_RD_DATA_MEM,
-					   dataMemAddress))
-	{
-	    ixNpeDlNpeMgrUtilsStats.dataMemWriteFails++;
-	    return IX_FAIL;
-	}
-    }
-
-    ixNpeDlNpeMgrUtilsStats.dataMemWrites++;
-    return IX_SUCCESS;
-}
-
-
-/*
- * Function definition: ixNpeDlNpeMgrExecAccRegWrite
- */
-void
-ixNpeDlNpeMgrExecAccRegWrite (
-    UINT32 npeBaseAddress,
-    UINT32 regAddress,
-    UINT32 regData)
-{
-    ixNpeDlNpeMgrWriteCommandIssue (npeBaseAddress,
-				    IX_NPEDL_EXCTL_CMD_WR_ECS_REG,
-				    regAddress, regData);
-    ixNpeDlNpeMgrUtilsStats.ecsRegWrites++;
-}
-
-
-/*
- * Function definition: ixNpeDlNpeMgrExecAccRegRead
- */
-UINT32
-ixNpeDlNpeMgrExecAccRegRead (
-    UINT32 npeBaseAddress,
-    UINT32 regAddress)
-{
-    ixNpeDlNpeMgrUtilsStats.ecsRegReads++;
-    return ixNpeDlNpeMgrReadCommandIssue (npeBaseAddress,
-					  IX_NPEDL_EXCTL_CMD_RD_ECS_REG,
-					  regAddress);
-}
-
-
-/*
- * Function definition: ixNpeDlNpeMgrCommandIssue
- */
-void
-ixNpeDlNpeMgrCommandIssue (
-    UINT32 npeBaseAddress,
-    UINT32 command)     
-{
-    IX_NPEDL_TRACE0 (IX_NPEDL_FN_ENTRY_EXIT,
-		     "Entering ixNpeDlNpeMgrCommandIssue\n");
-
-    IX_NPEDL_REG_WRITE (npeBaseAddress, IX_NPEDL_REG_OFFSET_EXCTL, command);
-
-    IX_NPEDL_TRACE0 (IX_NPEDL_FN_ENTRY_EXIT,
-		     "Exiting ixNpeDlNpeMgrCommandIssue\n");
-}
-
-
-/*
- * Function definition: ixNpeDlNpeMgrDebugInstructionPreExec
- */
-void
-ixNpeDlNpeMgrDebugInstructionPreExec(
-    UINT32 npeBaseAddress)
-{
-    /* turn off the halt bit by clearing Execution Count register. */
-    /* save reg contents 1st and restore later */
-    IX_NPEDL_REG_READ (npeBaseAddress, IX_NPEDL_REG_OFFSET_EXCT,
-		       &ixNpeDlSavedExecCount);
-    IX_NPEDL_REG_WRITE (npeBaseAddress, IX_NPEDL_REG_OFFSET_EXCT, 0);
-
-    /* ensure that IF and IE are on (temporarily), so that we don't end up
-     * stepping forever */
-    ixNpeDlSavedEcsDbgCtxtReg2 = ixNpeDlNpeMgrExecAccRegRead (npeBaseAddress,
-				                   IX_NPEDL_ECS_DBG_CTXT_REG_2);
-
-    ixNpeDlNpeMgrExecAccRegWrite (npeBaseAddress, IX_NPEDL_ECS_DBG_CTXT_REG_2,
-				  (ixNpeDlSavedEcsDbgCtxtReg2 |
-				   IX_NPEDL_MASK_ECS_DBG_REG_2_IF |
-				   IX_NPEDL_MASK_ECS_DBG_REG_2_IE));
-}
-
-
-/*
- * Function definition: ixNpeDlNpeMgrDebugInstructionExec
- */
-IX_STATUS
-ixNpeDlNpeMgrDebugInstructionExec(
-    UINT32 npeBaseAddress,
-    UINT32 npeInstruction,
-    UINT32 ctxtNum,
-    UINT32 ldur)
-{
-    UINT32 ecsDbgRegVal;
-    UINT32 oldWatchcount, newWatchcount;
-    UINT32 retriesCount = 0;
-    IX_STATUS status = IX_SUCCESS;
-
-    IX_NPEDL_TRACE0 (IX_NPEDL_FN_ENTRY_EXIT,
-		     "Entering ixNpeDlNpeMgrDebugInstructionExec\n");
-
-    /* set the Active bit, and the LDUR, in the debug level */
-    ecsDbgRegVal = IX_NPEDL_MASK_ECS_REG_0_ACTIVE |
-	(ldur << IX_NPEDL_OFFSET_ECS_REG_0_LDUR);
-
-    ixNpeDlNpeMgrExecAccRegWrite (npeBaseAddress, IX_NPEDL_ECS_DBG_CTXT_REG_0,
-				  ecsDbgRegVal);
-
-    /*
-     * set CCTXT at ECS DEBUG L3 to specify in which context to execute the
-     * instruction, and set SELCTXT at ECS DEBUG Level to specify which context
-     * store to access.
-     * Debug ECS Level Reg 1 has form  0x000n000n, where n = context number
-     */
-    ecsDbgRegVal = (ctxtNum << IX_NPEDL_OFFSET_ECS_REG_1_CCTXT) |
-	(ctxtNum << IX_NPEDL_OFFSET_ECS_REG_1_SELCTXT);
-
-    ixNpeDlNpeMgrExecAccRegWrite (npeBaseAddress, IX_NPEDL_ECS_DBG_CTXT_REG_1,
-				  ecsDbgRegVal);
-
-    /* clear the pipeline */
-    ixNpeDlNpeMgrCommandIssue (npeBaseAddress, IX_NPEDL_EXCTL_CMD_NPE_CLR_PIPE);
-
-    /* load NPE instruction into the instruction register */
-    ixNpeDlNpeMgrExecAccRegWrite (npeBaseAddress, IX_NPEDL_ECS_INSTRUCT_REG,
-				  npeInstruction);
-
-    /* we need this value later to wait for completion of NPE execution step */
-    IX_NPEDL_REG_READ (npeBaseAddress, IX_NPEDL_REG_OFFSET_WC, &oldWatchcount);
-
-    /* issue a Step One command via the Execution Control register */
-    ixNpeDlNpeMgrCommandIssue (npeBaseAddress, IX_NPEDL_EXCTL_CMD_NPE_STEP);
-
-	/* Watch Count register increments when NPE completes an instruction */
-	IX_NPEDL_REG_READ (npeBaseAddress, IX_NPEDL_REG_OFFSET_WC,
-        &newWatchcount);
-        
-    /*
-     * force the XScale to wait until the NPE has finished execution step
-     * NOTE that this delay will be very small, just long enough to allow a
-     * single NPE instruction to complete execution; if instruction execution
-     * is not completed before timeout retries, exit the while loop
-     */
-    while ((IX_NPE_DL_MAX_NUM_OF_RETRIES > retriesCount) 
-        && (newWatchcount == oldWatchcount))
-    {
-	    /* Watch Count register increments when NPE completes an instruction */
-	    IX_NPEDL_REG_READ (npeBaseAddress, IX_NPEDL_REG_OFFSET_WC,
-		    &newWatchcount);
-			   
-        retriesCount++;
-    }    
-
-    if (IX_NPE_DL_MAX_NUM_OF_RETRIES > retriesCount)
-    {
-        ixNpeDlNpeMgrUtilsStats.dbgInstructionExecs++;
-    }
-    else
-    {
-        /* Return timeout status as the instruction has not been executed
-         * after maximum retries */
-        status = IX_NPEDL_CRITICAL_NPE_ERR;
-    }
-    
-    IX_NPEDL_TRACE0 (IX_NPEDL_FN_ENTRY_EXIT,
-		     "Exiting ixNpeDlNpeMgrDebugInstructionExec\n");
-		     
-    return status;
-}    
-
-
-/*
- * Function definition: ixNpeDlNpeMgrDebugInstructionPostExec
- */
-void
-ixNpeDlNpeMgrDebugInstructionPostExec(
-    UINT32 npeBaseAddress)
-{
-    /* clear active bit in debug level */
-    ixNpeDlNpeMgrExecAccRegWrite (npeBaseAddress, IX_NPEDL_ECS_DBG_CTXT_REG_0,
-				  0);
-
-    /* clear the pipeline */
-    ixNpeDlNpeMgrCommandIssue (npeBaseAddress, IX_NPEDL_EXCTL_CMD_NPE_CLR_PIPE);
-    
-    /* restore Execution Count register contents. */
-    IX_NPEDL_REG_WRITE (npeBaseAddress, IX_NPEDL_REG_OFFSET_EXCT,
-			ixNpeDlSavedExecCount);
-
-    /* restore IF and IE bits to original values */
-    ixNpeDlNpeMgrExecAccRegWrite (npeBaseAddress, IX_NPEDL_ECS_DBG_CTXT_REG_2,
-				  ixNpeDlSavedEcsDbgCtxtReg2);
-}
-
-
-/*
- * Function definition: ixNpeDlNpeMgrLogicalRegRead
- */
-PRIVATE IX_STATUS
-ixNpeDlNpeMgrLogicalRegRead (
-    UINT32 npeBaseAddress, 
-    UINT32 regAddr,
-    UINT32 regSize,
-    UINT32 ctxtNum,
-    UINT32 *regVal)
-{
-    IX_STATUS status = IX_SUCCESS;
-    UINT32 npeInstruction = 0;
-    UINT32 mask = 0;
-
-    IX_NPEDL_TRACE0 (IX_NPEDL_FN_ENTRY_EXIT,
-		     "Entering ixNpeDlNpeMgrLogicalRegRead\n");
-
-    switch (regSize)
-    {
-    case IX_NPEDL_REG_SIZE_BYTE:
-      npeInstruction = IX_NPEDL_INSTR_RD_REG_BYTE;
-      mask = IX_NPEDL_MASK_LOWER_BYTE_OF_WORD;  break;
-    case IX_NPEDL_REG_SIZE_SHORT:
-      npeInstruction = IX_NPEDL_INSTR_RD_REG_SHORT;
-      mask = IX_NPEDL_MASK_LOWER_SHORT_OF_WORD;  break;
-    case IX_NPEDL_REG_SIZE_WORD:
-      npeInstruction = IX_NPEDL_INSTR_RD_REG_WORD;
-      mask = IX_NPEDL_MASK_FULL_WORD;  break;
-    }
-
-    /* make regAddr be the SRC and DEST operands (e.g. movX d0, d0) */
-    npeInstruction |= (regAddr << IX_NPEDL_OFFSET_INSTR_SRC) |
-	(regAddr << IX_NPEDL_OFFSET_INSTR_DEST);
-
-    /* step execution of NPE intruction using Debug Executing Context stack */
-    status = ixNpeDlNpeMgrDebugInstructionExec (npeBaseAddress, npeInstruction,
-				       ctxtNum, IX_NPEDL_RD_INSTR_LDUR);
-
-    if (IX_SUCCESS != status)
-    {
-        return status;
-    }
-    
-    /* read value of register from Execution Data register */
-    IX_NPEDL_REG_READ (npeBaseAddress,	IX_NPEDL_REG_OFFSET_EXDATA, regVal);
-
-   /* align value from left to right */
-    *regVal = (*regVal >> (IX_NPEDL_REG_SIZE_WORD - regSize)) & mask;
-
-    IX_NPEDL_TRACE0 (IX_NPEDL_FN_ENTRY_EXIT,
-		     "Exiting ixNpeDlNpeMgrLogicalRegRead\n");
-    
-    return IX_SUCCESS;
-}
-
-
-/*
- * Function definition: ixNpeDlNpeMgrLogicalRegWrite
- */
-PRIVATE IX_STATUS
-ixNpeDlNpeMgrLogicalRegWrite (
-    UINT32 npeBaseAddress, 
-    UINT32 regAddr,
-    UINT32 regVal,
-    UINT32 regSize,
-    UINT32 ctxtNum,
-    BOOL verify)
-{
-    UINT32 npeInstruction = 0;
-    UINT32 mask = 0;
-    IX_STATUS status = IX_SUCCESS;
-    UINT32 retRegVal;
-
-    IX_NPEDL_TRACE0 (IX_NPEDL_FN_ENTRY_EXIT,
-		     "Entering ixNpeDlNpeMgrLogicalRegWrite\n");
-
-    if (regSize == IX_NPEDL_REG_SIZE_WORD)
-    {
-	/* NPE register addressing is left-to-right: e.g. |d0|d1|d2|d3| */
-	/* Write upper half-word (short) to |d0|d1| */
-	status = ixNpeDlNpeMgrLogicalRegWrite (npeBaseAddress, regAddr,
-				      regVal >> IX_NPEDL_REG_SIZE_SHORT,
-				      IX_NPEDL_REG_SIZE_SHORT,
-				      ctxtNum, verify);
-				      
-	if (IX_SUCCESS != status)
-	{
-	    return status;
-	}
-	
-	/* Write lower half-word (short) to |d2|d3| */
-	status = ixNpeDlNpeMgrLogicalRegWrite (npeBaseAddress,
-				      regAddr + IX_NPEDL_BYTES_PER_SHORT,
-                                    regVal & IX_NPEDL_MASK_LOWER_SHORT_OF_WORD,
-				      IX_NPEDL_REG_SIZE_SHORT,
-				      ctxtNum, verify);
-    
-    if (IX_SUCCESS != status)
-	{
-	    return status;
-	}
-	}
-    else
-    {
-        switch (regSize)
-	{ 
-	case IX_NPEDL_REG_SIZE_BYTE:
-	    npeInstruction = IX_NPEDL_INSTR_WR_REG_BYTE;
-	    mask = IX_NPEDL_MASK_LOWER_BYTE_OF_WORD;  break;
-	case IX_NPEDL_REG_SIZE_SHORT:
-            npeInstruction = IX_NPEDL_INSTR_WR_REG_SHORT;
-	    mask = IX_NPEDL_MASK_LOWER_SHORT_OF_WORD;  break;
-	}
-	/* mask out any redundant bits, so verify will work later */
-	regVal &= mask;
-
-	/* fill dest operand field of  instruction with destination reg addr */
-	npeInstruction |= (regAddr << IX_NPEDL_OFFSET_INSTR_DEST);
-
-	/* fill src operand field of instruction with least-sig 5 bits of val*/
-	npeInstruction |= ((regVal & IX_NPEDL_MASK_IMMED_INSTR_SRC_DATA) <<
-			   IX_NPEDL_OFFSET_INSTR_SRC);
-
-	/* fill coprocessor field of instruction with most-sig 11 bits of val*/
-	npeInstruction |= ((regVal & IX_NPEDL_MASK_IMMED_INSTR_COPROC_DATA) <<
-			   IX_NPEDL_DISPLACE_IMMED_INSTR_COPROC_DATA);
-
-	/* step execution of NPE intruction using Debug ECS */
-	status = ixNpeDlNpeMgrDebugInstructionExec(npeBaseAddress, npeInstruction,
-					  ctxtNum, IX_NPEDL_WR_INSTR_LDUR);
-					  
-	if (IX_SUCCESS != status)
-	{
-	    return status;  
-	} 
-    }/* condition: if reg to be written is 8-bit or 16-bit (not 32-bit) */
-
-    if (verify)
-    {
-	status = ixNpeDlNpeMgrLogicalRegRead (npeBaseAddress, regAddr,
-						   regSize, ctxtNum, &retRegVal);
-						   
-        if (IX_SUCCESS == status)
-        {
-            if (regVal != retRegVal)
-            {
-                status = IX_FAIL;
-            }
-        }        
-    }
-
-    IX_NPEDL_TRACE1 (IX_NPEDL_FN_ENTRY_EXIT,
-		     "Exiting ixNpeDlNpeMgrLogicalRegWrite : status = %d\n",
-		     status);
-    
-    return status;
-}
-
-
-/*
- * Function definition: ixNpeDlNpeMgrPhysicalRegWrite
- */
-IX_STATUS
-ixNpeDlNpeMgrPhysicalRegWrite (
-    UINT32 npeBaseAddress,
-    UINT32 regAddr,
-    UINT32 regValue,
-    BOOL verify)
-{
-    IX_STATUS status;
-
-    IX_NPEDL_TRACE0 (IX_NPEDL_FN_ENTRY_EXIT,
-		     "Entering ixNpeDlNpeMgrPhysicalRegWrite\n");
-
-/*
- * There are 32 physical registers used in an NPE.  These are
- * treated as 16 pairs of 32-bit registers.  To write one of the pair,
- * write the pair number (0-16) to the REGMAP for Context 0.  Then write
- * the value to register  0 or 4 in the regfile, depending on which
- * register of the pair is to be written
- */
-
-    /*
-     * set REGMAP for context 0 to (regAddr >> 1) to choose which pair (0-16)
-     * of physical registers to write 
-     */
-    status = ixNpeDlNpeMgrLogicalRegWrite (npeBaseAddress,
-					   IX_NPEDL_CTXT_REG_ADDR_REGMAP,
-					   (regAddr >>
-					  IX_NPEDL_OFFSET_PHYS_REG_ADDR_REGMAP),
-					   IX_NPEDL_REG_SIZE_SHORT, 0, verify);
-    if (status == IX_SUCCESS)
-    {
-	/* regAddr = 0 or 4  */
-	regAddr = (regAddr & IX_NPEDL_MASK_PHYS_REG_ADDR_LOGICAL_ADDR) *
-	    IX_NPEDL_BYTES_PER_WORD;
-    
-    status = ixNpeDlNpeMgrLogicalRegWrite (npeBaseAddress, regAddr, regValue, 
-					   IX_NPEDL_REG_SIZE_WORD, 0, verify);
-    }
-    
-    if (status != IX_SUCCESS)
-    {
-	IX_NPEDL_ERROR_REPORT ("ixNpeDlNpeMgrPhysicalRegWrite: "
-			       "error writing to physical register\n");
-    }
-
-    ixNpeDlNpeMgrUtilsStats.physicalRegWrites++;
-
-    IX_NPEDL_TRACE1 (IX_NPEDL_FN_ENTRY_EXIT,
-		     "Exiting ixNpeDlNpeMgrPhysicalRegWrite : status = %d\n",
-		     status);
-    return status;
-}
-
-
-/*
- * Function definition: ixNpeDlNpeMgrCtxtRegWrite
- */
-IX_STATUS
-ixNpeDlNpeMgrCtxtRegWrite (
-    UINT32 npeBaseAddress,
-    UINT32 ctxtNum,
-    IxNpeDlCtxtRegNum ctxtReg,
-    UINT32 ctxtRegVal,
-    BOOL verify)
-{
-    UINT32 tempRegVal;
-    UINT32 ctxtRegAddr;
-    UINT32 ctxtRegSize;
-    IX_STATUS status = IX_SUCCESS;
-
-    IX_NPEDL_TRACE0 (IX_NPEDL_FN_ENTRY_EXIT, 
-		     "Entering ixNpeDlNpeMgrCtxtRegWrite\n");
-
-    /*
-     * Context 0 has no STARTPC. Instead, this value is used to set
-     * NextPC for Background ECS, to set where NPE starts executing code
-     */
-    if ((ctxtNum == 0) && (ctxtReg == IX_NPEDL_CTXT_REG_STARTPC))
-    {
-	/* read BG_CTXT_REG_0, update NEXTPC bits, and write back to reg */
-	tempRegVal = ixNpeDlNpeMgrExecAccRegRead (npeBaseAddress,
-						  IX_NPEDL_ECS_BG_CTXT_REG_0);
-	tempRegVal &= ~IX_NPEDL_MASK_ECS_REG_0_NEXTPC;
-	tempRegVal |= (ctxtRegVal << IX_NPEDL_OFFSET_ECS_REG_0_NEXTPC) &
-	    IX_NPEDL_MASK_ECS_REG_0_NEXTPC;
-	
-	ixNpeDlNpeMgrExecAccRegWrite (npeBaseAddress,
-				      IX_NPEDL_ECS_BG_CTXT_REG_0, tempRegVal);
-
-	ixNpeDlNpeMgrUtilsStats.nextPcWrites++;
-    }
-    else
-    {
-	ctxtRegAddr = ixNpeDlCtxtRegAccInfo[ctxtReg].regAddress;
-	ctxtRegSize = ixNpeDlCtxtRegAccInfo[ctxtReg].regSize;
-	status = ixNpeDlNpeMgrLogicalRegWrite (npeBaseAddress, ctxtRegAddr,
-					       ctxtRegVal, ctxtRegSize,
-					       ctxtNum, verify);
-	if (status != IX_SUCCESS)
-	{
-	    IX_NPEDL_ERROR_REPORT ("ixNpeDlNpeMgrCtxtRegWrite: "
-				   "error writing to context store register\n");
-	}
-	
-	ixNpeDlNpeMgrUtilsStats.contextRegWrites++;
-    }
-
-    IX_NPEDL_TRACE1 (IX_NPEDL_FN_ENTRY_EXIT, 
-		     "Exiting ixNpeDlNpeMgrCtxtRegWrite : status = %d\n",
-		     status);
-
-    return status;
-}
-
-
-/*
- * Function definition: ixNpeDlNpeMgrUtilsStatsShow
- */
-void
-ixNpeDlNpeMgrUtilsStatsShow (void)
-{
-    ixOsalLog (IX_OSAL_LOG_LVL_USER,
-               IX_OSAL_LOG_DEV_STDOUT,
-               "\nixNpeDlNpeMgrUtilsStatsShow:\n"
-               "\tInstruction Memory writes: %u\n"
-               "\tInstruction Memory writes failed: %u\n"
-               "\tData Memory writes: %u\n"
-               "\tData Memory writes failed: %u\n",
-               ixNpeDlNpeMgrUtilsStats.insMemWrites,
-               ixNpeDlNpeMgrUtilsStats.insMemWriteFails,
-               ixNpeDlNpeMgrUtilsStats.dataMemWrites,
-               ixNpeDlNpeMgrUtilsStats.dataMemWriteFails,
-               0,0);
-
-    ixOsalLog (IX_OSAL_LOG_LVL_USER,
-               IX_OSAL_LOG_DEV_STDOUT,
-               "\tExecuting Context Stack Register writes: %u\n"
-               "\tExecuting Context Stack Register reads: %u\n"
-               "\tPhysical Register writes: %u\n"
-               "\tContext Store Register writes: %u\n"
-               "\tExecution Backgound Context NextPC writes: %u\n"
-               "\tDebug Instructions Executed: %u\n\n",
-               ixNpeDlNpeMgrUtilsStats.ecsRegWrites,
-               ixNpeDlNpeMgrUtilsStats.ecsRegReads,
-               ixNpeDlNpeMgrUtilsStats.physicalRegWrites,
-               ixNpeDlNpeMgrUtilsStats.contextRegWrites,
-               ixNpeDlNpeMgrUtilsStats.nextPcWrites,
-               ixNpeDlNpeMgrUtilsStats.dbgInstructionExecs);
-}
-
-
-/*
- * Function definition: ixNpeDlNpeMgrUtilsStatsReset
- */
-void
-ixNpeDlNpeMgrUtilsStatsReset (void)
-{
-    ixNpeDlNpeMgrUtilsStats.insMemWrites = 0;
-    ixNpeDlNpeMgrUtilsStats.insMemWriteFails = 0;
-    ixNpeDlNpeMgrUtilsStats.dataMemWrites = 0;
-    ixNpeDlNpeMgrUtilsStats.dataMemWriteFails = 0;
-    ixNpeDlNpeMgrUtilsStats.ecsRegWrites = 0;
-    ixNpeDlNpeMgrUtilsStats.ecsRegReads = 0;
-    ixNpeDlNpeMgrUtilsStats.physicalRegWrites = 0;
-    ixNpeDlNpeMgrUtilsStats.contextRegWrites = 0;
-    ixNpeDlNpeMgrUtilsStats.nextPcWrites = 0;
-    ixNpeDlNpeMgrUtilsStats.dbgInstructionExecs = 0;
-}
diff --git a/drivers/net/npe/IxNpeMh.c b/drivers/net/npe/IxNpeMh.c
deleted file mode 100644
index 5adabd82fc..0000000000
--- a/drivers/net/npe/IxNpeMh.c
+++ /dev/null
@@ -1,558 +0,0 @@
-/**
- * @file IxNpeMh.c
- *
- * @author Intel Corporation
- * @date 18 Jan 2002
- *
- * @brief This file contains the implementation of the public API for the
- * IXP425 NPE Message Handler component.
- *
- *
- * @par
- * IXP400 SW Release version 2.0
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * SPDX-License-Identifier:	BSD-3-Clause
- * @par
- * -- End of Copyright Notice --
-*/
-
-/*
- * Put the system defined include files required.
- */
-
-/*
- * Put the user defined include files required.
- */
-
-#include "IxOsal.h"
-#include "IxNpeMhMacros_p.h"
-
-#include "IxNpeMh.h"
-
-#include "IxNpeMhConfig_p.h"
-#include "IxNpeMhReceive_p.h"
-#include "IxNpeMhSend_p.h"
-#include "IxNpeMhSolicitedCbMgr_p.h"
-#include "IxNpeMhUnsolicitedCbMgr_p.h"
-
-/*
- * #defines and macros used in this file.
- */
-
-/*
- * Typedefs whose scope is limited to this file.
- */
-
-/*
- * Variable declarations global to this file only.  Externs are followed by
- * static variables.
- */
-
-PRIVATE BOOL ixNpeMhInitialized = false;
-
-/*
- * Extern function prototypes.
- */
-
-/*
- * Static function prototypes.
- */
-
-/*
- * Function definition: ixNpeMhInitialize
- */
-
-PUBLIC IX_STATUS ixNpeMhInitialize (
-    IxNpeMhNpeInterrupts npeInterrupts)
-{
-    IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Entering "
-                     "ixNpeMhInitialize\n");
-
-    /* check the npeInterrupts parameter */
-    if ((npeInterrupts != IX_NPEMH_NPEINTERRUPTS_NO) &&
-        (npeInterrupts != IX_NPEMH_NPEINTERRUPTS_YES))
-    {
-        IX_NPEMH_ERROR_REPORT ("Illegal npeInterrupts parameter value\n");
-        return IX_FAIL;
-    }
-
-    /* parameters are ok ... */
-
-    /* initialize the Receive module */
-    ixNpeMhReceiveInitialize ();
-
-    /* initialize the Solicited Callback Manager module */
-    ixNpeMhSolicitedCbMgrInitialize ();
-
-    /* initialize the Unsolicited Callback Manager module */
-    ixNpeMhUnsolicitedCbMgrInitialize ();
-
-    /* initialize the Configuration module
-     *
-     * NOTE: This module was originally configured before the
-     * others, but the sequence was changed so that interrupts
-     * would only be enabled after the handler functions were
-     * set up.  The above modules need to be initialised to
-     * handle the NPE interrupts.  See SCR #2231.
-     */
-    ixNpeMhConfigInitialize (npeInterrupts);
-
-    ixNpeMhInitialized = true;
-
-    IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Exiting "
-                     "ixNpeMhInitialize\n");
-
-    return IX_SUCCESS;
-}
-
-/*
- * Function definition: ixNpeMhUnload
- */
-
-PUBLIC IX_STATUS ixNpeMhUnload (void)
-{
-    IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Entering "
-                     "ixNpeMhUnload\n");
-
-    if (!ixNpeMhInitialized)
-    {
-	return IX_FAIL;
-    }
-
-    /* Uninitialize the Configuration module */
-    ixNpeMhConfigUninit ();
-
-    ixNpeMhInitialized = false;
-
-    IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Exiting "
-                     "ixNpeMhUnload\n");
-
-    return IX_SUCCESS;
-}
-
-
-/*
- * Function definition: ixNpeMhUnsolicitedCallbackRegister
- */
-
-PUBLIC IX_STATUS ixNpeMhUnsolicitedCallbackRegister (
-    IxNpeMhNpeId npeId,
-    IxNpeMhMessageId messageId,
-    IxNpeMhCallback unsolicitedCallback)
-{
-    IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Entering "
-                     "ixNpeMhUnsolicitedCallbackRegister\n");
-
-    /* check that we are initialized */
-    if (!ixNpeMhInitialized)
-    {
-        IX_NPEMH_ERROR_REPORT ("IxNpeMh component is not initialized\n");
-        return IX_FAIL;
-    }
-
-    /* check the npeId parameter */
-    if (!ixNpeMhConfigNpeIdIsValid (npeId))
-    {
-        IX_NPEMH_ERROR_REPORT ("NPE ID invalid\n");
-        return IX_FAIL;
-    }
-
-    /* check the messageId parameter */
-    if ((messageId < IX_NPEMH_MIN_MESSAGE_ID)
-        || (messageId > IX_NPEMH_MAX_MESSAGE_ID))
-    {
-        IX_NPEMH_ERROR_REPORT ("Message ID is out of range\n");
-        return IX_FAIL;
-    }
-
-    /* the unsolicitedCallback parameter is allowed to be NULL */
-
-    /* parameters are ok ... */
-
-    /* get the lock to prevent other clients from entering */
-    ixNpeMhConfigLockGet (npeId);
-
-    /* save the unsolicited callback for the message ID */
-    ixNpeMhUnsolicitedCbMgrCallbackSave (
-        npeId, messageId, unsolicitedCallback);
-
-    /* release the lock to allow other clients back in */
-    ixNpeMhConfigLockRelease (npeId);
-
-    IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Exiting "
-                     "ixNpeMhUnsolicitedCallbackRegister\n");
-
-    return IX_SUCCESS;
-}
-
-/*
- * Function definition: ixNpeMhUnsolicitedCallbackForRangeRegister
- */
-
-PUBLIC IX_STATUS ixNpeMhUnsolicitedCallbackForRangeRegister (
-    IxNpeMhNpeId npeId,
-    IxNpeMhMessageId minMessageId,
-    IxNpeMhMessageId maxMessageId,
-    IxNpeMhCallback unsolicitedCallback)
-{
-    IxNpeMhMessageId messageId;
-
-    IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Entering "
-                     "ixNpeMhUnsolicitedCallbackForRangeRegister\n");
-
-    /* check that we are initialized */
-    if (!ixNpeMhInitialized)
-    {
-        IX_NPEMH_ERROR_REPORT ("IxNpeMh component is not initialized\n");
-        return IX_FAIL;
-    }
-
-    /* check the npeId parameter */
-    if (!ixNpeMhConfigNpeIdIsValid (npeId))
-    {
-        IX_NPEMH_ERROR_REPORT ("NPE ID invalid\n");
-        return IX_FAIL;
-    }
-
-    /* check the minMessageId parameter */
-    if ((minMessageId < IX_NPEMH_MIN_MESSAGE_ID)
-        || (minMessageId > IX_NPEMH_MAX_MESSAGE_ID))
-    {
-        IX_NPEMH_ERROR_REPORT ("Min message ID is out of range\n");
-        return IX_FAIL;
-    }
-
-    /* check the maxMessageId parameter */
-    if ((maxMessageId < IX_NPEMH_MIN_MESSAGE_ID)
-        || (maxMessageId > IX_NPEMH_MAX_MESSAGE_ID))
-    {
-        IX_NPEMH_ERROR_REPORT ("Max message ID is out of range\n");
-        return IX_FAIL;
-    }
-
-    /* check the semantics of the message range parameters */
-    if (minMessageId > maxMessageId)
-    {
-        IX_NPEMH_ERROR_REPORT ("Min message ID greater than max message "
-                               "ID\n");
-        return IX_FAIL;
-    }
-
-    /* the unsolicitedCallback parameter is allowed to be NULL */
-
-    /* parameters are ok ... */
-
-    /* get the lock to prevent other clients from entering */
-    ixNpeMhConfigLockGet (npeId);
-
-    /* for each message ID in the range ... */
-    for (messageId = minMessageId; messageId <= maxMessageId; messageId++)
-    {
-        /* save the unsolicited callback for the message ID */
-        ixNpeMhUnsolicitedCbMgrCallbackSave (
-            npeId, messageId, unsolicitedCallback);
-    }
-
-    /* release the lock to allow other clients back in */
-    ixNpeMhConfigLockRelease (npeId);
-
-    IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Exiting "
-                     "ixNpeMhUnsolicitedCallbackForRangeRegister\n");
-
-    return IX_SUCCESS;
-}
-
-/*
- * Function definition: ixNpeMhMessageSend
- */
-
-PUBLIC IX_STATUS ixNpeMhMessageSend (
-    IxNpeMhNpeId npeId,
-    IxNpeMhMessage message,
-    UINT32 maxSendRetries)
-{
-    IX_STATUS status = IX_SUCCESS;
-
-    IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Entering "
-                     "ixNpeMhMessageSend\n");
-
-    /* check that we are initialized */
-    if (!ixNpeMhInitialized)
-    {
-        IX_NPEMH_ERROR_REPORT ("IxNpeMh component is not initialized\n");
-        return IX_FAIL;
-    }
-
-    /* check the npeId parameter */
-    if (!ixNpeMhConfigNpeIdIsValid (npeId))
-    {
-        IX_NPEMH_ERROR_REPORT ("NPE ID invalid\n");
-        return IX_FAIL;
-    }
-
-    /* parameters are ok ... */
-
-    /* get the lock to prevent other clients from entering */
-    ixNpeMhConfigLockGet (npeId);
-
-    /* send the message */
-    status = ixNpeMhSendMessageSend (npeId, message, maxSendRetries);
-    if (status != IX_SUCCESS)
-    {
-        IX_NPEMH_ERROR_REPORT ("Failed to send message\n");
-    }
-
-    /* release the lock to allow other clients back in */
-    ixNpeMhConfigLockRelease (npeId);
-
-    IX_NPEMH_TRACE1 (IX_NPEMH_FN_ENTRY_EXIT, "Exiting "
-                     "ixNpeMhMessageSend"
-                     " : status = %d\n", status);
-
-    return status;
-}
-
-/*
- * Function definition: ixNpeMhMessageWithResponseSend
- */
-
-PUBLIC IX_STATUS ixNpeMhMessageWithResponseSend (
-    IxNpeMhNpeId npeId,
-    IxNpeMhMessage message,
-    IxNpeMhMessageId solicitedMessageId,
-    IxNpeMhCallback solicitedCallback,
-    UINT32 maxSendRetries)
-{
-    IX_STATUS status = IX_SUCCESS;
-    IxNpeMhCallback unsolicitedCallback = NULL;
-
-    IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Entering "
-                     "ixNpeMhMessageWithResponseSend\n");
-
-    /* check that we are initialized */
-    if (!ixNpeMhInitialized)
-    {
-        IX_NPEMH_ERROR_REPORT ("IxNpeMh component is not initialized\n");
-        return IX_FAIL;
-    }
-
-    /* the solicitecCallback parameter is allowed to be NULL.  this */
-    /* signifies the client is not interested in the response message */
-
-    /* check the npeId parameter */
-    if (!ixNpeMhConfigNpeIdIsValid (npeId))
-    {
-        IX_NPEMH_ERROR_REPORT ("NPE ID invalid\n");
-        return IX_FAIL;
-    }
-
-    /* check the solicitedMessageId parameter */
-    if ((solicitedMessageId < IX_NPEMH_MIN_MESSAGE_ID)
-        || (solicitedMessageId > IX_NPEMH_MAX_MESSAGE_ID))
-    {
-        IX_NPEMH_ERROR_REPORT ("Solicited message ID is out of range\n");
-        return IX_FAIL;
-    }
-
-    /* check the solicitedMessageId parameter.  if an unsolicited */
-    /* callback has been registered for the specified message ID then */
-    /* report an error and return failure */
-    ixNpeMhUnsolicitedCbMgrCallbackRetrieve (
-        npeId, solicitedMessageId, &unsolicitedCallback);
-    if (unsolicitedCallback != NULL)
-    {
-        IX_NPEMH_ERROR_REPORT ("Solicited message ID conflicts with "
-                               "unsolicited message ID\n");
-        return IX_FAIL;
-    }
-
-    /* parameters are ok ... */
-
-    /* get the lock to prevent other clients from entering */
-    ixNpeMhConfigLockGet (npeId);
-
-    /* send the message */
-    status = ixNpeMhSendMessageWithResponseSend (
-        npeId, message, solicitedMessageId, solicitedCallback,
-        maxSendRetries);
-    if (status != IX_SUCCESS)
-    {
-        IX_NPEMH_ERROR_REPORT ("Failed to send message\n");
-    }
-
-    /* release the lock to allow other clients back in */
-    ixNpeMhConfigLockRelease (npeId);
-
-    IX_NPEMH_TRACE1 (IX_NPEMH_FN_ENTRY_EXIT, "Exiting "
-                     "ixNpeMhMessageWithResponseSend"
-                     " : status = %d\n", status);
-
-    return status;
-}
-
-/*
- * Function definition: ixNpeMhMessagesReceive
- */
-
-PUBLIC IX_STATUS ixNpeMhMessagesReceive (
-    IxNpeMhNpeId npeId)
-{
-    IX_STATUS status = IX_SUCCESS;
-
-    IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Entering "
-                     "ixNpeMhMessagesReceive\n");
-
-    /* check that we are initialized */
-    if (!ixNpeMhInitialized)
-    {
-        IX_NPEMH_ERROR_REPORT ("IxNpeMh component is not initialized\n");
-        return IX_FAIL;
-    }
-
-    /* check the npeId parameter */
-    if (!ixNpeMhConfigNpeIdIsValid (npeId))
-    {
-        IX_NPEMH_ERROR_REPORT ("NPE ID invalid\n");
-        return IX_FAIL;
-    }
-
-    /* parameters are ok ... */
-
-    /* get the lock to prevent other clients from entering */
-    ixNpeMhConfigLockGet (npeId);
-
-    /* receive messages from the NPE */
-    status = ixNpeMhReceiveMessagesReceive (npeId);
-
-    if (status != IX_SUCCESS)
-    {
-        IX_NPEMH_ERROR_REPORT ("Failed to receive message\n");
-    }
-
-    /* release the lock to allow other clients back in */
-    ixNpeMhConfigLockRelease (npeId);
-
-    IX_NPEMH_TRACE1 (IX_NPEMH_FN_ENTRY_EXIT, "Exiting "
-                     "ixNpeMhMessagesReceive"
-                     " : status = %d\n", status);
-
-    return status;
-}
-
-/*
- * Function definition: ixNpeMhShow
- */
-
-PUBLIC IX_STATUS ixNpeMhShow (
-    IxNpeMhNpeId npeId)
-{
-    IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Entering "
-                     "ixNpeMhShow\n");
-
-    /* check that we are initialized */
-    if (!ixNpeMhInitialized)
-    {
-        IX_NPEMH_ERROR_REPORT ("IxNpeMh component is not initialized\n");
-        return IX_FAIL;
-    }
-
-    /* check the npeId parameter */
-    if (!ixNpeMhConfigNpeIdIsValid (npeId))
-    {
-        IX_NPEMH_ERROR_REPORT ("NPE ID invalid\n");
-        return IX_FAIL;
-    }
-
-    /* parameters are ok ... */
-
-    /* note we don't get the lock here as printing the statistics */
-    /* to a console may take some time and we don't want to impact */
-    /* system performance.  this means that the statistics displayed */
-    /* may be in a state of flux and make not represent a consistent */
-    /* snapshot. */
-
-    /* display a header */
-    ixOsalLog (IX_OSAL_LOG_LVL_USER, IX_OSAL_LOG_DEV_STDOUT,
-	       "Current state of NPE ID %d:\n\n", npeId, 0, 0, 0, 0, 0);
-
-    /* show the current state of each module */
-
-    /* show the current state of the Configuration module */
-    ixNpeMhConfigShow (npeId);
-
-    /* show the current state of the Receive module */
-    ixNpeMhReceiveShow (npeId);
-
-    /* show the current state of the Send module */
-    ixNpeMhSendShow (npeId);
-
-    /* show the current state of the Solicited Callback Manager module */
-    ixNpeMhSolicitedCbMgrShow (npeId);
-
-    /* show the current state of the Unsolicited Callback Manager module */
-    ixNpeMhUnsolicitedCbMgrShow (npeId);
-
-    IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Exiting "
-                     "ixNpeMhShow\n");
-
-    return IX_SUCCESS;
-}
-
-/*
- * Function definition: ixNpeMhShowReset
- */
-
-PUBLIC IX_STATUS ixNpeMhShowReset (
-    IxNpeMhNpeId npeId)
-{
-    IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Entering "
-                     "ixNpeMhShowReset\n");
-
-    /* check that we are initialized */
-    if (!ixNpeMhInitialized)
-    {
-        IX_NPEMH_ERROR_REPORT ("IxNpeMh component is not initialized\n");
-        return IX_FAIL;
-    }
-
-    /* check the npeId parameter */
-    if (!ixNpeMhConfigNpeIdIsValid (npeId))
-    {
-        IX_NPEMH_ERROR_REPORT ("NPE ID invalid\n");
-        return IX_FAIL;
-    }
-
-    /* parameters are ok ... */
-
-    /* note we don't get the lock here as resetting the statistics */
-    /* shouldn't impact system performance. */
-
-    /* reset the current state of each module */
-
-    /* reset the current state of the Configuration module */
-    ixNpeMhConfigShowReset (npeId);
-
-    /* reset the current state of the Receive module */
-    ixNpeMhReceiveShowReset (npeId);
-
-    /* reset the current state of the Send module */
-    ixNpeMhSendShowReset (npeId);
-
-    /* reset the current state of the Solicited Callback Manager module */
-    ixNpeMhSolicitedCbMgrShowReset (npeId);
-
-    /* reset the current state of the Unsolicited Callback Manager module */
-    ixNpeMhUnsolicitedCbMgrShowReset (npeId);
-
-    IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Exiting "
-                     "ixNpeMhShowReset\n");
-
-    return IX_SUCCESS;
-}
diff --git a/drivers/net/npe/IxNpeMhConfig.c b/drivers/net/npe/IxNpeMhConfig.c
deleted file mode 100644
index eaa9a21ad7..0000000000
--- a/drivers/net/npe/IxNpeMhConfig.c
+++ /dev/null
@@ -1,584 +0,0 @@
-/**
- * @file IxNpeMhConfig.c
- *
- * @author Intel Corporation
- * @date 18 Jan 2002
- *
- * @brief This file contains the implementation of the private API for the
- * Configuration module.
- *
- * 
- * @par
- * IXP400 SW Release version 2.0
- * 
- * -- Copyright Notice --
- * 
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- * 
- * @par
- * SPDX-License-Identifier:	BSD-3-Clause
- * @par
- * -- End of Copyright Notice --
-*/
-
-/*
- * Put the system defined include files required.
- */
-
-
-/*
- * Put the user defined include files required.
- */
-
-#include "IxOsal.h"
-
-#include "IxNpeMhMacros_p.h"
-
-#include "IxNpeMhConfig_p.h"
-
-/*
- * #defines and macros used in this file.
- */
-#define IX_NPE_MH_MAX_NUM_OF_RETRIES 1000000 /**< Maximum number of
-                                              * retries before
-                                              * timeout
-					                          */  
-
-/*
- * Typedefs whose scope is limited to this file.
- */
-
-/**
- * @struct IxNpeMhConfigStats
- *
- * @brief This structure is used to maintain statistics for the
- * Configuration module.
- */
-
-typedef struct
-{
-    UINT32 outFifoReads;        /**< outFifo reads */
-    UINT32 inFifoWrites;        /**< inFifo writes */
-    UINT32 maxInFifoFullRetries;   /**< max retries if inFIFO full   */
-    UINT32 maxOutFifoEmptyRetries; /**< max retries if outFIFO empty */
-} IxNpeMhConfigStats;
-
-/*
- * Variable declarations global to this file only.  Externs are followed by
- * static variables.
- */
-
-IxNpeMhConfigNpeInfo ixNpeMhConfigNpeInfo[IX_NPEMH_NUM_NPES] =
-{
-    {
-        0,
-        IX_NPEMH_NPEA_INT,
-	0,
-        0,
-        0,
-        0,
-        0,
-        NULL,
-        false
-    },
-    {
-        0,
-        IX_NPEMH_NPEB_INT,
-	0,
-	0,
-        0,
-        0,
-        0,
-        NULL,
-        false
-    },
-    {
-        0,
-        IX_NPEMH_NPEC_INT,
-        0,
-        0,
-        0,
-        0,
-        0,
-        NULL,
-        false
-    }
-};
-
-PRIVATE IxNpeMhConfigStats ixNpeMhConfigStats[IX_NPEMH_NUM_NPES];
-
-/*
- * Extern function prototypes.
- */
-
-/*
- * Static function prototypes.
- */
-PRIVATE
-void ixNpeMhConfigIsr (void *parameter);
-
-/*
- * Function definition: ixNpeMhConfigIsr
- */
-
-PRIVATE
-void ixNpeMhConfigIsr (void *parameter)
-{
-    IxNpeMhNpeId npeId = (IxNpeMhNpeId)parameter;
-    UINT32 ofint;
-    volatile UINT32 *statusReg =
-        (UINT32 *)ixNpeMhConfigNpeInfo[npeId].statusRegister;
-
-    IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Entering "
-                     "ixNpeMhConfigIsr\n");
-
-    /* get the OFINT (OutFifo interrupt) bit of the status register */
-    IX_NPEMH_REGISTER_READ_BITS (statusReg, &ofint, IX_NPEMH_NPE_STAT_OFINT);
-
-    /* if the OFINT status bit is set */
-    if (ofint)
-    {
-        /* if there is an ISR registered for this NPE */
-        if (ixNpeMhConfigNpeInfo[npeId].isr != NULL)
-        {
-            /* invoke the ISR routine */
-            ixNpeMhConfigNpeInfo[npeId].isr (npeId);
-        }
-        else
-        {
-            /* if we don't service the interrupt the NPE will continue */
-            /* to trigger the interrupt indefinitely */
-            IX_NPEMH_ERROR_REPORT ("No ISR registered to service "
-                                   "interrupt\n");
-        }
-    }
-
-    IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Exiting "
-                     "ixNpeMhConfigIsr\n");
-}
-
-/*
- * Function definition: ixNpeMhConfigInitialize
- */
-
-void ixNpeMhConfigInitialize (
-    IxNpeMhNpeInterrupts npeInterrupts)
-{
-    IxNpeMhNpeId npeId;
-    UINT32 virtualAddr[IX_NPEMH_NUM_NPES];
-
-    IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Entering "
-                     "ixNpeMhConfigInitialize\n");
-
-    /* Request a mapping for the NPE-A config register address space */
-    virtualAddr[IX_NPEMH_NPEID_NPEA] =
-	(UINT32) IX_OSAL_MEM_MAP (IX_NPEMH_NPEA_BASE,
-				     IX_OSAL_IXP400_NPEA_MAP_SIZE);
-    IX_OSAL_ASSERT (virtualAddr[IX_NPEMH_NPEID_NPEA]);
-
-    /* Request a mapping for the NPE-B config register address space */
-    virtualAddr[IX_NPEMH_NPEID_NPEB] =
-	(UINT32) IX_OSAL_MEM_MAP (IX_NPEMH_NPEB_BASE,
-				     IX_OSAL_IXP400_NPEB_MAP_SIZE);
-    IX_OSAL_ASSERT (virtualAddr[IX_NPEMH_NPEID_NPEB]);
-    
-    /* Request a mapping for the NPE-C config register address space */
-    virtualAddr[IX_NPEMH_NPEID_NPEC] =
-	(UINT32) IX_OSAL_MEM_MAP (IX_NPEMH_NPEC_BASE,
-				     IX_OSAL_IXP400_NPEC_MAP_SIZE);
-    IX_OSAL_ASSERT (virtualAddr[IX_NPEMH_NPEID_NPEC]);
-
-    /* for each NPE ... */
-    for (npeId = 0; npeId < IX_NPEMH_NUM_NPES; npeId++)
-    {
-        /* declare a convenience pointer */
-        IxNpeMhConfigNpeInfo *npeInfo = &ixNpeMhConfigNpeInfo[npeId];
-	
-	/* store the virtual addresses of the NPE registers for later use */
-	npeInfo->virtualRegisterBase  = virtualAddr[npeId];
-	npeInfo->statusRegister  = virtualAddr[npeId] + IX_NPEMH_NPESTAT_OFFSET;
-	npeInfo->controlRegister = virtualAddr[npeId] + IX_NPEMH_NPECTL_OFFSET;
-	npeInfo->inFifoRegister  = virtualAddr[npeId] + IX_NPEMH_NPEFIFO_OFFSET;
-	npeInfo->outFifoRegister = virtualAddr[npeId] + IX_NPEMH_NPEFIFO_OFFSET;
-
-        /* for test purposes - to verify the register addresses */
-        IX_NPEMH_TRACE2 (IX_NPEMH_DEBUG, "NPE %d status register  = "
-                         "0x%08X\n", npeId, npeInfo->statusRegister);
-        IX_NPEMH_TRACE2 (IX_NPEMH_DEBUG, "NPE %d control register = "
-                         "0x%08X\n", npeId, npeInfo->controlRegister);
-        IX_NPEMH_TRACE2 (IX_NPEMH_DEBUG, "NPE %d inFifo register  = "
-                         "0x%08X\n", npeId, npeInfo->inFifoRegister);
-        IX_NPEMH_TRACE2 (IX_NPEMH_DEBUG, "NPE %d outFifo register = "
-                         "0x%08X\n", npeId, npeInfo->outFifoRegister);
-
-        /* connect our ISR to the NPE interrupt */
-        (void) ixOsalIrqBind (
-            npeInfo->interruptId, ixNpeMhConfigIsr, (void *)npeId);
-
-        /* initialise a mutex for this NPE */
-        (void) ixOsalMutexInit (&npeInfo->mutex);
-
-        /* if we should service the NPE's "outFIFO not empty" interrupt */
-        if (npeInterrupts == IX_NPEMH_NPEINTERRUPTS_YES)
-        {
-            /* enable the NPE's "outFIFO not empty" interrupt */
-            ixNpeMhConfigNpeInterruptEnable (npeId);
-        }
-        else
-        {
-            /* disable the NPE's "outFIFO not empty" interrupt */
-            ixNpeMhConfigNpeInterruptDisable (npeId);
-        }
-    }
-
-    IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Exiting "
-                     "ixNpeMhConfigInitialize\n");
-}
-
-/*
- * Function definition: ixNpeMhConfigUninit
- */
-
-void ixNpeMhConfigUninit (void)
-{
-    IxNpeMhNpeId npeId;
-
-    IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Entering "
-                     "ixNpeMhConfigUninit\n");
-
-    /* for each NPE ... */
-    for (npeId = 0; npeId < IX_NPEMH_NUM_NPES; npeId++)
-    {
-        /* declare a convenience pointer */
-        IxNpeMhConfigNpeInfo *npeInfo = &ixNpeMhConfigNpeInfo[npeId];
-        
-        /* disconnect ISR */
-        ixOsalIrqUnbind(npeInfo->interruptId);
-
-        /* destroy mutex associated with this NPE */
-        ixOsalMutexDestroy(&npeInfo->mutex);
-	
-	IX_OSAL_MEM_UNMAP (npeInfo->virtualRegisterBase);
-
-	npeInfo->virtualRegisterBase  = 0;
-	npeInfo->statusRegister  = 0;
-	npeInfo->controlRegister = 0;
-	npeInfo->inFifoRegister  = 0;
-	npeInfo->outFifoRegister = 0;
-    }
-
-    IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Exiting "
-                     "ixNpeMhConfigUninit\n");
-}
-
-/*
- * Function definition: ixNpeMhConfigIsrRegister
- */
-
-void ixNpeMhConfigIsrRegister (
-    IxNpeMhNpeId npeId,
-    IxNpeMhConfigIsr isr)
-{
-    IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Entering "
-                     "ixNpeMhConfigIsrRegister\n");
-
-    /* check if there is already an ISR registered for this NPE */
-    if (ixNpeMhConfigNpeInfo[npeId].isr != NULL)
-    {
-        IX_NPEMH_TRACE0 (IX_NPEMH_DEBUG, "Over-writing registered NPE ISR\n");
-    }
-
-    /* save the ISR routine with the NPE info */
-    ixNpeMhConfigNpeInfo[npeId].isr = isr;
-
-    IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Exiting "
-                     "ixNpeMhConfigIsrRegister\n");
-}
-
-/*
- * Function definition: ixNpeMhConfigNpeInterruptEnable
- */
-
-BOOL ixNpeMhConfigNpeInterruptEnable (
-    IxNpeMhNpeId npeId)
-{
-    UINT32 ofe;
-    volatile UINT32 *controlReg =
-        (UINT32 *)ixNpeMhConfigNpeInfo[npeId].controlRegister;
-
-    /* get the OFE (OutFifoEnable) bit of the control register */
-    IX_NPEMH_REGISTER_READ_BITS (controlReg, &ofe, IX_NPEMH_NPE_CTL_OFE);
-
-    /* if the interrupt is disabled then we must enable it */
-    if (!ofe)
-    {
-        /* set the OFE (OutFifoEnable) bit of the control register */
-        /* we must set the OFEWE (OutFifoEnableWriteEnable) at the same */
-        /* time for the write to have effect */
-        IX_NPEMH_REGISTER_WRITE_BITS (controlReg,
-                                      (IX_NPEMH_NPE_CTL_OFE |
-                                       IX_NPEMH_NPE_CTL_OFEWE),
-                                      (IX_NPEMH_NPE_CTL_OFE |
-                                       IX_NPEMH_NPE_CTL_OFEWE));
-    }
-
-    /* return the previous state of the interrupt */
-    return (ofe != 0);
-}
-
-/*
- * Function definition: ixNpeMhConfigNpeInterruptDisable
- */
-
-BOOL ixNpeMhConfigNpeInterruptDisable (
-    IxNpeMhNpeId npeId)
-{
-    UINT32 ofe;
-    volatile UINT32 *controlReg =
-        (UINT32 *)ixNpeMhConfigNpeInfo[npeId].controlRegister;
-
-    /* get the OFE (OutFifoEnable) bit of the control register */
-    IX_NPEMH_REGISTER_READ_BITS (controlReg, &ofe, IX_NPEMH_NPE_CTL_OFE);
-
-    /* if the interrupt is enabled then we must disable it */
-    if (ofe)
-    {
-        /* unset the OFE (OutFifoEnable) bit of the control register */
-        /* we must set the OFEWE (OutFifoEnableWriteEnable) at the same */
-        /* time for the write to have effect */
-        IX_NPEMH_REGISTER_WRITE_BITS (controlReg,
-                                      (0                    |
-                                       IX_NPEMH_NPE_CTL_OFEWE),
-                                      (IX_NPEMH_NPE_CTL_OFE |
-                                       IX_NPEMH_NPE_CTL_OFEWE));
-    }
-
-    /* return the previous state of the interrupt */
-    return (ofe != 0);
-}
-
-/*
- * Function definition: ixNpeMhConfigMessageIdGet
- */
-
-IxNpeMhMessageId ixNpeMhConfigMessageIdGet (
-    IxNpeMhMessage message)
-{
-    /* return the most-significant byte of the first word of the */
-    /* message */
-    return ((IxNpeMhMessageId) ((message.data[0] >> 24) & 0xFF));
-}
-
-/*
- * Function definition: ixNpeMhConfigNpeIdIsValid
- */
-
-BOOL ixNpeMhConfigNpeIdIsValid (
-    IxNpeMhNpeId npeId)
-{
-    /* check that the npeId parameter is within the range of valid IDs */
-    return (npeId >= 0 && npeId < IX_NPEMH_NUM_NPES);
-}
-
-/*
- * Function definition: ixNpeMhConfigLockGet
- */
-
-void ixNpeMhConfigLockGet (
-    IxNpeMhNpeId npeId)
-{
-    IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Entering "
-                     "ixNpeMhConfigLockGet\n");
-
-    /* lock the mutex for this NPE */
-    (void) ixOsalMutexLock (&ixNpeMhConfigNpeInfo[npeId].mutex, 
-			    IX_OSAL_WAIT_FOREVER);
-
-    /* disable the NPE's "outFIFO not empty" interrupt */
-    ixNpeMhConfigNpeInfo[npeId].oldInterruptState =
-        ixNpeMhConfigNpeInterruptDisable (npeId);
-
-    IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Exiting "
-                     "ixNpeMhConfigLockGet\n");
-}
-
-/*
- * Function definition: ixNpeMhConfigLockRelease
- */
-
-void ixNpeMhConfigLockRelease (
-    IxNpeMhNpeId npeId)
-{
-    IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Entering "
-                     "ixNpeMhConfigLockRelease\n");
-
-    /* if the interrupt was previously enabled */
-    if (ixNpeMhConfigNpeInfo[npeId].oldInterruptState)
-    {
-        /* enable the NPE's "outFIFO not empty" interrupt */
-        ixNpeMhConfigNpeInfo[npeId].oldInterruptState =
-            ixNpeMhConfigNpeInterruptEnable (npeId);
-    }
-
-    /* unlock the mutex for this NPE */
-    (void) ixOsalMutexUnlock (&ixNpeMhConfigNpeInfo[npeId].mutex);
-
-    IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Exiting "
-                     "ixNpeMhConfigLockRelease\n");
-}
-
-/*
- * Function definition: ixNpeMhConfigInFifoWrite
- */
-
-IX_STATUS ixNpeMhConfigInFifoWrite (
-    IxNpeMhNpeId npeId,
-    IxNpeMhMessage message)
-{
-    volatile UINT32 *npeInFifo =
-        (UINT32 *)ixNpeMhConfigNpeInfo[npeId].inFifoRegister;
-    UINT32 retriesCount = 0;
-
-    /* write the first word of the message to the NPE's inFIFO */
-    IX_NPEMH_REGISTER_WRITE (npeInFifo, message.data[0]);
-
-    /* need to wait for room to write second word - see SCR #493,
-       poll for maximum number of retries, if exceed maximum
-       retries, exit from while loop */
-    while ((IX_NPE_MH_MAX_NUM_OF_RETRIES > retriesCount)
-        && ixNpeMhConfigInFifoIsFull (npeId))
-    {
-        retriesCount++;
-    }
-
-    /* Return TIMEOUT status to caller, indicate that NPE Hang / Halt */
-    if (IX_NPE_MH_MAX_NUM_OF_RETRIES == retriesCount)
-    {
-        return IX_NPEMH_CRITICAL_NPE_ERR;   
-    }    
-    
-    /* write the second word of the message to the NPE's inFIFO */
-    IX_NPEMH_REGISTER_WRITE (npeInFifo, message.data[1]);
-
-    /* record in the stats the maximum number of retries needed */
-    if (ixNpeMhConfigStats[npeId].maxInFifoFullRetries < retriesCount)
-    {
-	ixNpeMhConfigStats[npeId].maxInFifoFullRetries = retriesCount;
-    }
-
-    /* update statistical info */
-    ixNpeMhConfigStats[npeId].inFifoWrites++;
-    
-    return IX_SUCCESS;
-}
-
-/*
- * Function definition: ixNpeMhConfigOutFifoRead
- */
-
-IX_STATUS ixNpeMhConfigOutFifoRead (
-    IxNpeMhNpeId npeId,
-    IxNpeMhMessage *message)
-{
-    volatile UINT32 *npeOutFifo =
-        (UINT32 *)ixNpeMhConfigNpeInfo[npeId].outFifoRegister;
-    UINT32 retriesCount = 0;
-
-    /* read the first word of the message from the NPE's outFIFO */
-    IX_NPEMH_REGISTER_READ (npeOutFifo, &message->data[0]);
-
-    /* need to wait for NPE to write second word - see SCR #493 
-       poll for maximum number of retries, if exceed maximum
-       retries, exit from while loop */
-    while ((IX_NPE_MH_MAX_NUM_OF_RETRIES > retriesCount)
-        && ixNpeMhConfigOutFifoIsEmpty (npeId))
-    {
-        retriesCount++;
-    }
-
-    /* Return TIMEOUT status to caller, indicate that NPE Hang / Halt */
-    if (IX_NPE_MH_MAX_NUM_OF_RETRIES == retriesCount)
-    {
-        return IX_NPEMH_CRITICAL_NPE_ERR;   
-    } 
-    
-    /* read the second word of the message from the NPE's outFIFO */
-    IX_NPEMH_REGISTER_READ (npeOutFifo, &message->data[1]);
-
-    /* record in the stats the maximum number of retries needed */
-    if (ixNpeMhConfigStats[npeId].maxOutFifoEmptyRetries < retriesCount)
-    {
-	ixNpeMhConfigStats[npeId].maxOutFifoEmptyRetries = retriesCount;
-    }
-
-    /* update statistical info */
-    ixNpeMhConfigStats[npeId].outFifoReads++;
-    
-    return IX_SUCCESS;
-}
-
-/*
- * Function definition: ixNpeMhConfigShow
- */
-
-void ixNpeMhConfigShow (
-    IxNpeMhNpeId npeId)
-{
-    /* show the message fifo read counter */
-    IX_NPEMH_SHOW ("Message FIFO reads",
-                   ixNpeMhConfigStats[npeId].outFifoReads);
-
-    /* show the message fifo write counter */
-    IX_NPEMH_SHOW ("Message FIFO writes",
-                   ixNpeMhConfigStats[npeId].inFifoWrites);
-
-    /* show the max retries performed when inFIFO full */
-    IX_NPEMH_SHOW ("Max inFIFO Full retries",
-		   ixNpeMhConfigStats[npeId].maxInFifoFullRetries);
-
-    /* show the max retries performed when outFIFO empty */
-    IX_NPEMH_SHOW ("Max outFIFO Empty retries",
-		   ixNpeMhConfigStats[npeId].maxOutFifoEmptyRetries);
-
-    /* show the current status of the inFifo */
-    ixOsalLog (IX_OSAL_LOG_LVL_USER, IX_OSAL_LOG_DEV_STDOUT,
-	       "InFifo is %s and %s\n",
-	       (ixNpeMhConfigInFifoIsEmpty (npeId) ? 
-		(int) "EMPTY" : (int) "NOT EMPTY"),
-	       (ixNpeMhConfigInFifoIsFull (npeId) ? 
-		(int) "FULL" : (int) "NOT FULL"),
-	       0, 0, 0, 0);
-
-    /* show the current status of the outFifo */
-    ixOsalLog (IX_OSAL_LOG_LVL_USER, IX_OSAL_LOG_DEV_STDOUT,
-	       "OutFifo is %s and %s\n",
-	       (ixNpeMhConfigOutFifoIsEmpty (npeId) ? 
-		(int) "EMPTY" : (int) "NOT EMPTY"),
-	       (ixNpeMhConfigOutFifoIsFull (npeId) ? 
-		(int) "FULL" : (int) "NOT FULL"),
-	       0, 0, 0, 0);
-}
-
-/*
- * Function definition: ixNpeMhConfigShowReset
- */
-
-void ixNpeMhConfigShowReset (
-    IxNpeMhNpeId npeId)
-{
-    /* reset the message fifo read counter */
-    ixNpeMhConfigStats[npeId].outFifoReads = 0;
-
-    /* reset the message fifo write counter */
-    ixNpeMhConfigStats[npeId].inFifoWrites = 0;
-
-    /* reset the max inFIFO Full retries counter */
-    ixNpeMhConfigStats[npeId].maxInFifoFullRetries = 0;
-
-    /* reset the max outFIFO empty retries counter */
-    ixNpeMhConfigStats[npeId].maxOutFifoEmptyRetries = 0;
-}
-
-
diff --git a/drivers/net/npe/IxNpeMhReceive.c b/drivers/net/npe/IxNpeMhReceive.c
deleted file mode 100644
index 273c3733f3..0000000000
--- a/drivers/net/npe/IxNpeMhReceive.c
+++ /dev/null
@@ -1,296 +0,0 @@
-/**
- * @file IxNpeMhReceive.c
- *
- * @author Intel Corporation
- * @date 18 Jan 2002
- *
- * @brief This file contains the implementation of the private API for the
- * Receive module.
- *
- * 
- * @par
- * IXP400 SW Release version 2.0
- * 
- * -- Copyright Notice --
- * 
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * SPDX-License-Identifier:	BSD-3-Clause
- * @par
- * -- End of Copyright Notice --
-*/
-
-/*
- * Put the system defined include files required.
- */
-
-
-/*
- * Put the user defined include files required.
- */
-#include "IxOsal.h"
-#include "IxNpeMhMacros_p.h"
-#include "IxNpeMhConfig_p.h"
-#include "IxNpeMhReceive_p.h"
-#include "IxNpeMhSolicitedCbMgr_p.h"
-#include "IxNpeMhUnsolicitedCbMgr_p.h"
-
-/*
- * #defines and macros used in this file.
- */
-
-/*
- * Typedefs whose scope is limited to this file.
- */
-
-/**
- * @struct IxNpeMhReceiveStats
- *
- * @brief This structure is used to maintain statistics for the Receive
- * module.
- */
-
-typedef struct
-{
-    UINT32 isrs;        /**< receive ISR invocations */
-    UINT32 receives;    /**< receive messages invocations */
-    UINT32 messages;    /**< messages received */
-    UINT32 solicited;   /**< solicited messages received */
-    UINT32 unsolicited; /**< unsolicited messages received */
-    UINT32 callbacks;   /**< callbacks invoked */
-} IxNpeMhReceiveStats;
-
-/*
- * Variable declarations global to this file only.  Externs are followed by
- * static variables.
- */
-
-PRIVATE IxNpeMhReceiveStats ixNpeMhReceiveStats[IX_NPEMH_NUM_NPES];
-
-/*
- * Extern function prototypes.
- */
-
-/*
- * Static function prototypes.
- */
-PRIVATE
-void ixNpeMhReceiveIsr (int npeId);
-
-PRIVATE
-void ixNpeMhReceiveIsr (int npeId)
-{
-    int lockKey;
-
-    IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Entering "
-                     "ixNpeMhReceiveIsr\n");
-
-    lockKey = ixOsalIrqLock ();
-
-    /* invoke the message receive routine to get messages from the NPE */
-    ixNpeMhReceiveMessagesReceive (npeId);
-
-    /* update statistical info */
-    ixNpeMhReceiveStats[npeId].isrs++;
-
-    ixOsalIrqUnlock (lockKey);
-
-    IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Exiting "
-                     "ixNpeMhReceiveIsr\n");
-}
-
-/*
- * Function definition: ixNpeMhReceiveInitialize
- */
-
-void ixNpeMhReceiveInitialize (void)
-{
-    IxNpeMhNpeId npeId = 0;
-
-    IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Entering "
-                     "ixNpeMhReceiveInitialize\n");
-
-    /* for each NPE ... */
-    for (npeId = 0; npeId < IX_NPEMH_NUM_NPES; npeId++)
-    {
-        /* register our internal ISR for the NPE to handle "outFIFO not */
-        /* empty" interrupts */
-        ixNpeMhConfigIsrRegister (npeId, ixNpeMhReceiveIsr);
-    }
-
-    IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Exiting "
-                     "ixNpeMhReceiveInitialize\n");
-}
-
-/*
- * Function definition: ixNpeMhReceiveMessagesReceive
- */
-
-IX_STATUS ixNpeMhReceiveMessagesReceive (
-    IxNpeMhNpeId npeId)
-{
-    IxNpeMhMessage message = { { 0, 0 } };
-    IxNpeMhMessageId messageId = 0;
-    IxNpeMhCallback callback = NULL;
-    IX_STATUS status;
-
-    IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Entering "
-                     "ixNpeMhReceiveMessagesReceive\n");
-
-    /* update statistical info */
-    ixNpeMhReceiveStats[npeId].receives++;
-
-    /* while the NPE has messages in its outFIFO */
-    while (!ixNpeMhConfigOutFifoIsEmpty (npeId))
-    {
-        /* read a message from the NPE's outFIFO */
-        status = ixNpeMhConfigOutFifoRead (npeId, &message);
-
-        if (IX_SUCCESS != status)
-        {
-            return status;
-        }
-        
-        /* get the ID of the message */
-        messageId = ixNpeMhConfigMessageIdGet (message);
-
-	    IX_NPEMH_TRACE2 (IX_NPEMH_DEBUG,
-			 "Received message from NPE %d with ID 0x%02X\n",
-			 npeId, messageId);
-
-        /* update statistical info */
-        ixNpeMhReceiveStats[npeId].messages++;
-
-        /* try to find a matching unsolicited callback for this message. */
-
-        /* we assume the message is unsolicited.  only if there is no */
-        /* unsolicited callback for this message type do we assume the */
-        /* message is solicited.  it is much faster to check for an */
-        /* unsolicited callback, so doing this check first should result */
-        /* in better performance. */
-
-        ixNpeMhUnsolicitedCbMgrCallbackRetrieve (
-            npeId, messageId, &callback);
-
-        if (callback != NULL)
-        {
-	    IX_NPEMH_TRACE0 (IX_NPEMH_DEBUG,
-			     "Found matching unsolicited callback\n");
-
-            /* update statistical info */
-            ixNpeMhReceiveStats[npeId].unsolicited++;
-        }
-
-        /* if no unsolicited callback was found try to find a matching */
-        /* solicited callback for this message */
-        if (callback == NULL)
-        {
-            ixNpeMhSolicitedCbMgrCallbackRetrieve (
-                npeId, messageId, &callback);
-
-            if (callback != NULL)
-            {
-		IX_NPEMH_TRACE0 (IX_NPEMH_DEBUG,
-				 "Found matching solicited callback\n");
-
-                /* update statistical info */
-                ixNpeMhReceiveStats[npeId].solicited++;
-            }
-        }
-
-        /* if a callback (either unsolicited or solicited) was found */
-        if (callback != NULL)
-        {
-            /* invoke the callback to pass the message back to the client */
-            callback (npeId, message);
-
-            /* update statistical info */
-            ixNpeMhReceiveStats[npeId].callbacks++;
-        }
-        else /* no callback (neither unsolicited nor solicited) was found */
-        {
-	    IX_NPEMH_TRACE2 (IX_NPEMH_WARNING,
-			     "No matching callback for NPE %d"
-			     " and ID 0x%02X, discarding message\n",
-			     npeId, messageId);
-
-            /* the message will be discarded.  this is normal behaviour */
-            /* if the client passes a NULL solicited callback when */
-            /* sending a message.  this indicates that the client is not */
-            /* interested in receiving the response.  alternatively a */
-            /* NULL callback here may signify an unsolicited message */
-            /* with no appropriate registered callback. */
-        }
-    }
-
-    IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Exiting "
-                     "ixNpeMhReceiveMessagesReceive\n");
-    
-    return IX_SUCCESS;
-}
-
-/*
- * Function definition: ixNpeMhReceiveShow
- */
-
-void ixNpeMhReceiveShow (
-    IxNpeMhNpeId npeId)
-{
-    /* show the ISR invocation counter */
-    IX_NPEMH_SHOW ("Receive ISR invocations",
-                   ixNpeMhReceiveStats[npeId].isrs);
-
-    /* show the receive message invocation counter */
-    IX_NPEMH_SHOW ("Receive messages invocations",
-                   ixNpeMhReceiveStats[npeId].receives);
-
-    /* show the message received counter */
-    IX_NPEMH_SHOW ("Messages received",
-                   ixNpeMhReceiveStats[npeId].messages);
-
-    /* show the solicited message counter */
-    IX_NPEMH_SHOW ("Solicited messages received",
-                   ixNpeMhReceiveStats[npeId].solicited);
-
-    /* show the unsolicited message counter */
-    IX_NPEMH_SHOW ("Unsolicited messages received",
-                   ixNpeMhReceiveStats[npeId].unsolicited);
-
-    /* show the callback invoked counter */
-    IX_NPEMH_SHOW ("Callbacks invoked",
-                   ixNpeMhReceiveStats[npeId].callbacks);
-
-    /* show the message discarded counter */
-    IX_NPEMH_SHOW ("Received messages discarded",
-                   (ixNpeMhReceiveStats[npeId].messages -
-                    ixNpeMhReceiveStats[npeId].callbacks));
-}
-
-/*
- * Function definition: ixNpeMhReceiveShowReset
- */
-
-void ixNpeMhReceiveShowReset (
-    IxNpeMhNpeId npeId)
-{
-    /* reset the ISR invocation counter */
-    ixNpeMhReceiveStats[npeId].isrs = 0;
-
-    /* reset the receive message invocation counter */
-    ixNpeMhReceiveStats[npeId].receives = 0;
-
-    /* reset the message received counter */
-    ixNpeMhReceiveStats[npeId].messages = 0;
-
-    /* reset the solicited message counter */
-    ixNpeMhReceiveStats[npeId].solicited = 0;
-
-    /* reset the unsolicited message counter */
-    ixNpeMhReceiveStats[npeId].unsolicited = 0;
-
-    /* reset the callback invoked counter */
-    ixNpeMhReceiveStats[npeId].callbacks = 0;
-}
diff --git a/drivers/net/npe/IxNpeMhSend.c b/drivers/net/npe/IxNpeMhSend.c
deleted file mode 100644
index 8b7038870a..0000000000
--- a/drivers/net/npe/IxNpeMhSend.c
+++ /dev/null
@@ -1,283 +0,0 @@
-/**
- * @file IxNpeMhSend.c
- *
- * @author Intel Corporation
- * @date 18 Jan 2002
- *
- * @brief This file contains the implementation of the private API for the
- * Send module.
- *
- *
- * @par
- * IXP400 SW Release version 2.0
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * SPDX-License-Identifier:	BSD-3-Clause
- * @par
- * -- End of Copyright Notice --
-*/
-
-/*
- * Put the system defined include files required.
- */
-
-
-/*
- * Put the user defined include files required.
- */
-
-#include "IxNpeMhMacros_p.h"
-
-#include "IxNpeMhConfig_p.h"
-#include "IxNpeMhSend_p.h"
-#include "IxNpeMhSolicitedCbMgr_p.h"
-
-/*
- * #defines and macros used in this file.
- */
-
-/**
- * @def IX_NPEMH_INFIFO_RETRY_DELAY_US
- *
- * @brief Amount of time (uSecs) to delay between retries
- * while inFIFO is Full when attempting to send a message
- */
-#define IX_NPEMH_INFIFO_RETRY_DELAY_US (1)
-
-
-/*
- * Typedefs whose scope is limited to this file.
- */
-
-/**
- * @struct IxNpeMhSendStats
- *
- * @brief This structure is used to maintain statistics for the Send
- * module.
- */
-
-typedef struct
-{
-    UINT32 sends;             /**< send invocations */
-    UINT32 sendWithResponses; /**< send with response invocations */
-    UINT32 queueFulls;        /**< fifo queue full occurrences */
-    UINT32 queueFullRetries;  /**< fifo queue full retry occurrences */
-    UINT32 maxQueueFullRetries; /**< max fifo queue full retries */
-    UINT32 callbackFulls;     /**< callback list full occurrences */
-} IxNpeMhSendStats;
-
-/*
- * Variable declarations global to this file only.  Externs are followed by
- * static variables.
- */
-
-PRIVATE IxNpeMhSendStats ixNpeMhSendStats[IX_NPEMH_NUM_NPES];
-
-/*
- * Extern function prototypes.
- */
-
-/*
- * Static function prototypes.
- */
-PRIVATE
-BOOL ixNpeMhSendInFifoIsFull(
-    IxNpeMhNpeId npeId,
-    UINT32 maxSendRetries);
-
-/*
- * Function definition: ixNpeMhSendInFifoIsFull
- */
-
-PRIVATE
-BOOL ixNpeMhSendInFifoIsFull(
-    IxNpeMhNpeId npeId,
-    UINT32 maxSendRetries)
-{
-    BOOL isFull = false;
-    UINT32 numRetries = 0;
-
-    /* check the NPE's inFIFO */
-    isFull = ixNpeMhConfigInFifoIsFull (npeId);
-
-    /* we retry a few times, just to give the NPE a chance to read from */
-    /* the FIFO if the FIFO is currently full */
-    while (isFull && (numRetries++ < maxSendRetries))
-    {
-	if (numRetries >= IX_NPEMH_SEND_RETRIES_DEFAULT)
-	{
-	    /* Delay here for as short a time as possible (1 us). */
-	    /* Adding a delay here should ensure we are not hogging */
-	    /* the AHB bus while we are retrying                    */
-	    ixOsalBusySleep (IX_NPEMH_INFIFO_RETRY_DELAY_US);
-	}
-
-        /* re-check the NPE's inFIFO */
-        isFull = ixNpeMhConfigInFifoIsFull (npeId);
-
-        /* update statistical info */
-        ixNpeMhSendStats[npeId].queueFullRetries++;
-    }
-
-    /* record the highest number of retries that occurred */
-    if (ixNpeMhSendStats[npeId].maxQueueFullRetries < numRetries)
-    {
-	ixNpeMhSendStats[npeId].maxQueueFullRetries = numRetries;
-    }
-
-    if (isFull)
-    {
-        /* update statistical info */
-        ixNpeMhSendStats[npeId].queueFulls++;
-    }
-
-    return isFull;
-}
-
-/*
- * Function definition: ixNpeMhSendMessageSend
- */
-
-IX_STATUS ixNpeMhSendMessageSend (
-    IxNpeMhNpeId npeId,
-    IxNpeMhMessage message,
-    UINT32 maxSendRetries)
-{
-    IX_STATUS status;
-
-    IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Entering "
-                     "ixNpeMhSendMessageSend\n");
-
-    /* update statistical info */
-    ixNpeMhSendStats[npeId].sends++;
-
-    /* check if the NPE's inFIFO is full - if so return an error */
-    if (ixNpeMhSendInFifoIsFull (npeId, maxSendRetries))
-    {
-        IX_NPEMH_TRACE0 (IX_NPEMH_WARNING, "NPE's inFIFO is full\n");
-        return IX_FAIL;
-    }
-
-    /* write the message to the NPE's inFIFO */
-    status = ixNpeMhConfigInFifoWrite (npeId, message);
-
-    IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Exiting "
-                     "ixNpeMhSendMessageSend\n");
-
-    return status;
-}
-
-/*
- * Function definition: ixNpeMhSendMessageWithResponseSend
- */
-
-IX_STATUS ixNpeMhSendMessageWithResponseSend (
-    IxNpeMhNpeId npeId,
-    IxNpeMhMessage message,
-    IxNpeMhMessageId solicitedMessageId,
-    IxNpeMhCallback solicitedCallback,
-    UINT32 maxSendRetries)
-{
-    IX_STATUS status = IX_SUCCESS;
-
-    IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Entering "
-                     "ixNpeMhSendMessageWithResponseSend\n");
-
-    /* update statistical info */
-    ixNpeMhSendStats[npeId].sendWithResponses++;
-
-    /* sr: this sleep will call the receive routine (no interrupts used!!!) */
-    ixOsalSleep (IX_NPEMH_INFIFO_RETRY_DELAY_US);
-
-    /* check if the NPE's inFIFO is full - if so return an error */
-    if (ixNpeMhSendInFifoIsFull (npeId, maxSendRetries))
-    {
-        IX_NPEMH_TRACE0 (IX_NPEMH_WARNING, "NPE's inFIFO is full\n");
-        return IX_FAIL;
-    }
-
-    /* save the solicited callback */
-    status = ixNpeMhSolicitedCbMgrCallbackSave (
-        npeId, solicitedMessageId, solicitedCallback);
-    if (status != IX_SUCCESS)
-    {
-        IX_NPEMH_ERROR_REPORT ("Failed to save solicited callback\n");
-
-        /* update statistical info */
-        ixNpeMhSendStats[npeId].callbackFulls++;
-
-        return status;
-    }
-
-    /* write the message to the NPE's inFIFO */
-    status = ixNpeMhConfigInFifoWrite (npeId, message);
-
-    IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Exiting "
-                     "ixNpeMhSendMessageWithResponseSend\n");
-
-    return status;
-}
-
-/*
- * Function definition: ixNpeMhSendShow
- */
-
-void ixNpeMhSendShow (
-    IxNpeMhNpeId npeId)
-{
-    /* show the message send invocation counter */
-    IX_NPEMH_SHOW ("Send invocations",
-                   ixNpeMhSendStats[npeId].sends);
-
-    /* show the message send with response invocation counter */
-    IX_NPEMH_SHOW ("Send with response invocations",
-                   ixNpeMhSendStats[npeId].sendWithResponses);
-
-    /* show the fifo queue full occurrence counter */
-    IX_NPEMH_SHOW ("Fifo queue full occurrences",
-                   ixNpeMhSendStats[npeId].queueFulls);
-
-    /* show the fifo queue full retry occurrence counter */
-    IX_NPEMH_SHOW ("Fifo queue full retry occurrences",
-                   ixNpeMhSendStats[npeId].queueFullRetries);
-
-    /* show the fifo queue full maximum retries counter */
-    IX_NPEMH_SHOW ("Maximum fifo queue full retries",
-                   ixNpeMhSendStats[npeId].maxQueueFullRetries);
-
-    /* show the callback list full occurrence counter */
-    IX_NPEMH_SHOW ("Solicited callback list full occurrences",
-                   ixNpeMhSendStats[npeId].callbackFulls);
-}
-
-/*
- * Function definition: ixNpeMhSendShowReset
- */
-
-void ixNpeMhSendShowReset (
-    IxNpeMhNpeId npeId)
-{
-    /* reset the message send invocation counter */
-    ixNpeMhSendStats[npeId].sends = 0;
-
-    /* reset the message send with response invocation counter */
-    ixNpeMhSendStats[npeId].sendWithResponses = 0;
-
-    /* reset the fifo queue full occurrence counter */
-    ixNpeMhSendStats[npeId].queueFulls = 0;
-
-    /* reset the fifo queue full retry occurrence counter */
-    ixNpeMhSendStats[npeId].queueFullRetries = 0;
-
-    /* reset the max fifo queue full retries counter */
-    ixNpeMhSendStats[npeId].maxQueueFullRetries = 0;
-
-    /* reset the callback list full occurrence counter */
-    ixNpeMhSendStats[npeId].callbackFulls = 0;
-}
diff --git a/drivers/net/npe/IxNpeMhSolicitedCbMgr.c b/drivers/net/npe/IxNpeMhSolicitedCbMgr.c
deleted file mode 100644
index c539d09071..0000000000
--- a/drivers/net/npe/IxNpeMhSolicitedCbMgr.c
+++ /dev/null
@@ -1,334 +0,0 @@
-/**
- * @file IxNpeMhSolicitedCbMgr.c
- *
- * @author Intel Corporation
- * @date 18 Jan 2002
- *
- * @brief This file contains the implementation of the private API for the
- * Solicited Callback Manager module.
- *
- * 
- * @par
- * IXP400 SW Release version 2.0
- * 
- * -- Copyright Notice --
- * 
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- * 
- * @par
- * SPDX-License-Identifier:	BSD-3-Clause
- * @par
- * -- End of Copyright Notice --
-*/
-#ifndef IXNPEMHCONFIG_P_H
-#	define IXNPEMHSOLICITEDCBMGR_C
-#else
-#	error "Error, IxNpeMhConfig_p.h should not be included before this definition."
-#endif
-
-/*
- * Put the system defined include files required.
- */
-
-
-/*
- * Put the user defined include files required.
- */
-
-#include "IxOsal.h"
-
-#include "IxNpeMhMacros_p.h"
-#include "IxNpeMhSolicitedCbMgr_p.h"
-#include "IxNpeMhConfig_p.h"
-/*
- * #defines and macros used in this file.
- */
-
-/*
- * Typedefs whose scope is limited to this file.
- */
-
-/**
- * @struct IxNpeMhSolicitedCallbackListEntry
- *
- * @brief This structure is used to store the information associated with
- * an entry in the callback list.  This consists of the ID of the send
- * message (which indicates the ID of the corresponding response message)
- * and the callback function pointer itself.
- *
- */
-
-typedef struct IxNpeMhSolicitedCallbackListEntry
-{
-    /** message ID */
-    IxNpeMhMessageId messageId;
-
-    /** callback function pointer */
-    IxNpeMhCallback callback;
-
-    /** pointer to next entry in the list */
-    struct IxNpeMhSolicitedCallbackListEntry *next;
-} IxNpeMhSolicitedCallbackListEntry;
-
-/**
- * @struct IxNpeMhSolicitedCallbackList
- *
- * @brief This structure is used to maintain the list of response
- * callbacks.  The number of entries in this list will be variable, and
- * they will be stored in a linked list fashion for ease of addition and
- * removal.  The entries themselves are statically allocated, and are
- * organised into a "free" list and a "callback" list.  Adding an entry
- * means taking an entry from the "free" list and adding it to the
- * "callback" list.  Removing an entry means removing it from the
- * "callback" list and returning it to the "free" list.
- */
-
-typedef struct
-{
-    /** pointer to the head of the free list */
-    IxNpeMhSolicitedCallbackListEntry *freeHead;
-
-    /** pointer to the head of the callback list */
-    IxNpeMhSolicitedCallbackListEntry *callbackHead;
-
-    /** pointer to the tail of the callback list */
-    IxNpeMhSolicitedCallbackListEntry *callbackTail;
-
-    /** array of entries - the first entry is used as a dummy entry to */
-    /* avoid the scenario of having an empty list, hence '+ 1' */
-    IxNpeMhSolicitedCallbackListEntry entries[IX_NPEMH_MAX_CALLBACKS + 1];
-} IxNpeMhSolicitedCallbackList;
-
-/**
- * @struct IxNpeMhSolicitedCbMgrStats
- *
- * @brief This structure is used to maintain statistics for the Solicited
- * Callback Manager module.
- */
-
-typedef struct
-{
-    UINT32 saves;     /**< callback list saves */
-    UINT32 retrieves; /**< callback list retrieves */
-} IxNpeMhSolicitedCbMgrStats;
-
-/*
- * Variable declarations global to this file only.  Externs are followed by
- * static variables.
- */
-
-PRIVATE IxNpeMhSolicitedCallbackList
-ixNpeMhSolicitedCbMgrCallbackLists[IX_NPEMH_NUM_NPES];
-
-PRIVATE IxNpeMhSolicitedCbMgrStats
-ixNpeMhSolicitedCbMgrStats[IX_NPEMH_NUM_NPES];
-
-/*
- * Extern function prototypes.
- */
-
-/*
- * Static function prototypes.
- */
-
-/*
- * Function definition: ixNpeMhSolicitedCbMgrInitialize
- */
-
-void ixNpeMhSolicitedCbMgrInitialize (void)
-{
-    IxNpeMhNpeId npeId;
-    UINT32 localIndex;
-    IxNpeMhSolicitedCallbackList *list = NULL;
-
-    IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Entering "
-                     "ixNpeMhSolicitedCbMgrInitialize\n");
-
-    /* for each NPE ... */
-    for (npeId = 0; npeId < IX_NPEMH_NUM_NPES; npeId++)
-    {
-        /* initialise a pointer to the list for convenience */
-        list = &ixNpeMhSolicitedCbMgrCallbackLists[npeId];
-
-        /* for each entry in the list, after the dummy entry ... */
-        for (localIndex = 1; localIndex <= IX_NPEMH_MAX_CALLBACKS; localIndex++)
-        {
-            /* initialise the entry */
-            list->entries[localIndex].messageId = 0x00;
-            list->entries[localIndex].callback = NULL;
-
-            /* if this entry is before the last entry */
-            if (localIndex < IX_NPEMH_MAX_CALLBACKS)
-            {
-                /* chain this entry to the following entry */
-                list->entries[localIndex].next = &(list->entries[localIndex + 1]);
-            }
-            else /* this entry is the last entry */
-            {
-                /* the last entry isn't chained to anything */
-                list->entries[localIndex].next = NULL;
-            }
-        }
-
-        /* set the free list pointer to point to the first real entry */
-        /* (all real entries begin chained together on the free list) */
-        list->freeHead = &(list->entries[1]);
-
-        /* set the callback list pointers to point to the dummy entry */
-        /* (the callback list is initially empty) */
-        list->callbackHead = &(list->entries[0]);
-        list->callbackTail = &(list->entries[0]);
-    }
-
-    IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Exiting "
-                     "ixNpeMhSolicitedCbMgrInitialize\n");
-}
-
-/*
- * Function definition: ixNpeMhSolicitedCbMgrCallbackSave
- */
-
-IX_STATUS ixNpeMhSolicitedCbMgrCallbackSave (
-    IxNpeMhNpeId npeId,
-    IxNpeMhMessageId solicitedMessageId,
-    IxNpeMhCallback solicitedCallback)
-{
-    IxNpeMhSolicitedCallbackList *list = NULL;
-    IxNpeMhSolicitedCallbackListEntry *callbackEntry = NULL;
-
-    IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Entering "
-                     "ixNpeMhSolicitedCbMgrCallbackSave\n");
-
-    /* initialise a pointer to the list for convenience */
-    list = &ixNpeMhSolicitedCbMgrCallbackLists[npeId];
-
-    /* check to see if there are any entries in the free list */
-    if (list->freeHead == NULL)
-    {
-        IX_NPEMH_ERROR_REPORT ("Solicited callback list is full\n");
-        return IX_FAIL;
-    }
-
-    /* there is an entry in the free list we can use */
-
-    /* update statistical info */
-    ixNpeMhSolicitedCbMgrStats[npeId].saves++;
-
-    /* remove a callback entry from the start of the free list */
-    callbackEntry = list->freeHead;
-    list->freeHead = callbackEntry->next;
-
-    /* fill in the callback entry with the new data */
-    callbackEntry->messageId = solicitedMessageId;
-    callbackEntry->callback = solicitedCallback;
-
-    /* the new callback entry will be added to the tail of the callback */
-    /* list, so it isn't chained to anything */
-    callbackEntry->next = NULL;
-
-    /* chain new callback entry to the last entry of the callback list */
-    list->callbackTail->next = callbackEntry;
-    list->callbackTail = callbackEntry;
-
-    IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Exiting "
-                     "ixNpeMhSolicitedCbMgrCallbackSave\n");
-
-    return IX_SUCCESS;
-}
-
-/*
- * Function definition: ixNpeMhSolicitedCbMgrCallbackRetrieve
- */
-
-void ixNpeMhSolicitedCbMgrCallbackRetrieve (
-    IxNpeMhNpeId npeId,
-    IxNpeMhMessageId solicitedMessageId,
-    IxNpeMhCallback *solicitedCallback)
-{
-    IxNpeMhSolicitedCallbackList *list = NULL;
-    IxNpeMhSolicitedCallbackListEntry *callbackEntry = NULL;
-    IxNpeMhSolicitedCallbackListEntry *previousEntry = NULL;
-
-    /* initialise a pointer to the list for convenience */
-    list = &ixNpeMhSolicitedCbMgrCallbackLists[npeId];
-
-    /* initialise the callback entry to the first entry of the callback */
-    /* list - we must skip over the dummy entry, which is the previous */
-    callbackEntry = list->callbackHead->next;
-    previousEntry = list->callbackHead;
-
-    /* traverse the callback list looking for an entry with a matching */
-    /* message ID.  note we also save the previous entry's pointer to */
-    /* allow us to unchain the matching entry from the callback list */
-    while ((callbackEntry != NULL) &&
-           (callbackEntry->messageId != solicitedMessageId))
-    {
-        previousEntry = callbackEntry;
-        callbackEntry = callbackEntry->next;
-    }
-
-    /* if we didn't find a matching callback entry */
-    if (callbackEntry == NULL)
-    {
-        /* return a NULL callback in the outgoing parameter */
-        *solicitedCallback = NULL;
-    }
-    else /* we found a matching callback entry */
-    {
-        /* update statistical info */
-        ixNpeMhSolicitedCbMgrStats[npeId].retrieves++;
-
-        /* return the callback in the outgoing parameter */
-        *solicitedCallback = callbackEntry->callback;
-
-        /* unchain callback entry by chaining previous entry to next */
-        previousEntry->next = callbackEntry->next;
-
-        /* if the callback entry is at the tail of the list */
-        if (list->callbackTail == callbackEntry)
-        {
-            /* update the tail of the callback list */
-            list->callbackTail = previousEntry;
-        }
-
-        /* re-initialise the callback entry */
-        callbackEntry->messageId = 0x00;
-        callbackEntry->callback = NULL;
-
-        /* add the callback entry to the start of the free list */
-        callbackEntry->next = list->freeHead;
-        list->freeHead = callbackEntry;
-    }
-}
-
-/*
- * Function definition: ixNpeMhSolicitedCbMgrShow
- */
-
-void ixNpeMhSolicitedCbMgrShow (
-    IxNpeMhNpeId npeId)
-{
-    /* show the solicited callback list save counter */
-    IX_NPEMH_SHOW ("Solicited callback list saves",
-                   ixNpeMhSolicitedCbMgrStats[npeId].saves);
-
-    /* show the solicited callback list retrieve counter */
-    IX_NPEMH_SHOW ("Solicited callback list retrieves",
-                   ixNpeMhSolicitedCbMgrStats[npeId].retrieves);
-}
-
-/*
- * Function definition: ixNpeMhSolicitedCbMgrShowReset
- */
-
-void ixNpeMhSolicitedCbMgrShowReset (
-    IxNpeMhNpeId npeId)
-{
-    /* reset the solicited callback list save counter */
-    ixNpeMhSolicitedCbMgrStats[npeId].saves = 0;
-
-    /* reset the solicited callback list retrieve counter */
-    ixNpeMhSolicitedCbMgrStats[npeId].retrieves = 0;
-}
diff --git a/drivers/net/npe/IxNpeMhUnsolicitedCbMgr.c b/drivers/net/npe/IxNpeMhUnsolicitedCbMgr.c
deleted file mode 100644
index 082f677e62..0000000000
--- a/drivers/net/npe/IxNpeMhUnsolicitedCbMgr.c
+++ /dev/null
@@ -1,222 +0,0 @@
-/**
- * @file IxNpeMhUnsolicitedCbMgr.c
- *
- * @author Intel Corporation
- * @date 18 Jan 2002
- *
- * @brief This file contains the implementation of the private API for
- * the Unsolicited Callback Manager module.
- *
- * 
- * @par
- * IXP400 SW Release version 2.0
- * 
- * -- Copyright Notice --
- * 
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- * 
- * @par
- * SPDX-License-Identifier:	BSD-3-Clause
- * @par
- * -- End of Copyright Notice --
-*/
-
-/*
- * Put the system defined include files required.
- */
-
-
-/*
- * Put the user defined include files required.
- */
-#include "IxOsal.h"
-
-#include "IxNpeMhMacros_p.h"
-
-#include "IxNpeMhUnsolicitedCbMgr_p.h"
-
-
-/*
- * #defines and macros used in this file.
- */
-
-/*
- * Typedefs whose scope is limited to this file.
- */
-
-/**
- * @struct IxNpeMhUnsolicitedCallbackTable
- *
- * @brief This structure is used to maintain the list of registered
- * callbacks.  One entry exists for each message ID, and a NULL entry will
- * signify that no callback has been registered for that ID.
- */
-
-typedef struct
-{
-    /** array of entries */
-    IxNpeMhCallback entries[IX_NPEMH_MAX_MESSAGE_ID + 1];
-} IxNpeMhUnsolicitedCallbackTable;
-
-/**
- * @struct IxNpeMhUnsolicitedCbMgrStats
- *
- * @brief This structure is used to maintain statistics for the Unsolicited
- * Callback Manager module.
- */
-
-typedef struct
-{
-    UINT32 saves;      /**< callback table saves */
-    UINT32 overwrites; /**< callback table overwrites */
-} IxNpeMhUnsolicitedCbMgrStats;
-
-/*
- * Variable declarations global to this file only.  Externs are followed by
- * static variables.
- */
-
-PRIVATE IxNpeMhUnsolicitedCallbackTable
-ixNpeMhUnsolicitedCallbackTables[IX_NPEMH_NUM_NPES];
-
-PRIVATE IxNpeMhUnsolicitedCbMgrStats
-ixNpeMhUnsolicitedCbMgrStats[IX_NPEMH_NUM_NPES];
-
-/*
- * Extern function prototypes.
- */
-
-/*
- * Static function prototypes.
- */
-
-/*
- * Function definition: ixNpeMhUnsolicitedCbMgrInitialize
- */
-
-void ixNpeMhUnsolicitedCbMgrInitialize (void)
-{
-    IxNpeMhNpeId npeId = 0;
-    IxNpeMhUnsolicitedCallbackTable *table = NULL;
-    IxNpeMhMessageId messageId = 0;
-
-    IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Entering "
-                     "ixNpeMhUnsolicitedCbMgrInitialize\n");
-
-    /* for each NPE ... */
-    for (npeId = 0; npeId < IX_NPEMH_NUM_NPES; npeId++)
-    {
-        /* initialise a pointer to the table for convenience */
-        table = &ixNpeMhUnsolicitedCallbackTables[npeId];
-
-        /* for each message ID ... */
-        for (messageId = IX_NPEMH_MIN_MESSAGE_ID;
-             messageId <= IX_NPEMH_MAX_MESSAGE_ID; messageId++)
-        {
-            /* initialise the callback for this message ID to NULL */
-            table->entries[messageId] = NULL;
-        }
-    }
-
-    IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Exiting "
-                     "ixNpeMhUnsolicitedCbMgrInitialize\n");
-}
-
-/*
- * Function definition: ixNpeMhUnsolicitedCbMgrCallbackSave
- */
-
-void ixNpeMhUnsolicitedCbMgrCallbackSave (
-    IxNpeMhNpeId npeId,
-    IxNpeMhMessageId unsolicitedMessageId,
-    IxNpeMhCallback unsolicitedCallback)
-{
-    IxNpeMhUnsolicitedCallbackTable *table = NULL;
-
-    /* initialise a pointer to the table for convenience */
-    table = &ixNpeMhUnsolicitedCallbackTables[npeId];
-
-    IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Entering "
-                     "ixNpeMhUnsolicitedCbMgrCallbackSave\n");
-
-    /* update statistical info */
-    ixNpeMhUnsolicitedCbMgrStats[npeId].saves++;
-
-    /* check if there is a callback already registered for this NPE and */
-    /* message ID */
-    if (table->entries[unsolicitedMessageId] != NULL)
-    {
-	/* if we are overwriting an existing callback */
-	if (unsolicitedCallback != NULL)
-	{
-	    IX_NPEMH_TRACE2 (IX_NPEMH_DEBUG, "Unsolicited callback "
-			     "overwriting existing callback for NPE ID %d "
-			     "message ID 0x%02X\n", npeId, unsolicitedMessageId);
-	}
-	else /* if we are clearing an existing callback */
-	{
-	    IX_NPEMH_TRACE2 (IX_NPEMH_DEBUG, "NULL unsolicited callback "
-			     "clearing existing callback for NPE ID %d "
-			     "message ID 0x%02X\n", npeId, unsolicitedMessageId);
-	}
-
-        /* update statistical info */
-        ixNpeMhUnsolicitedCbMgrStats[npeId].overwrites++;
-    }
-
-    /* save the callback into the table */
-    table->entries[unsolicitedMessageId] = unsolicitedCallback;
-
-    IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Exiting "
-                     "ixNpeMhUnsolicitedCbMgrCallbackSave\n");
-}
-
-/*
- * Function definition: ixNpeMhUnsolicitedCbMgrCallbackRetrieve
- */
-
-void ixNpeMhUnsolicitedCbMgrCallbackRetrieve (
-    IxNpeMhNpeId npeId,
-    IxNpeMhMessageId unsolicitedMessageId,
-    IxNpeMhCallback *unsolicitedCallback)
-{
-    IxNpeMhUnsolicitedCallbackTable *table = NULL;
-
-    /* initialise a pointer to the table for convenience */
-    table = &ixNpeMhUnsolicitedCallbackTables[npeId];
-
-    /* retrieve the callback from the table */
-    *unsolicitedCallback = table->entries[unsolicitedMessageId];
-}
-
-/*
- * Function definition: ixNpeMhUnsolicitedCbMgrShow
- */
-
-void ixNpeMhUnsolicitedCbMgrShow (
-    IxNpeMhNpeId npeId)
-{
-    /* show the unsolicited callback table save counter */
-    IX_NPEMH_SHOW ("Unsolicited callback table saves",
-                   ixNpeMhUnsolicitedCbMgrStats[npeId].saves);
-
-    /* show the unsolicited callback table overwrite counter */
-    IX_NPEMH_SHOW ("Unsolicited callback table overwrites",
-                   ixNpeMhUnsolicitedCbMgrStats[npeId].overwrites);
-}
-
-/*
- * Function definition: ixNpeMhUnsolicitedCbMgrShowReset
- */
-
-void ixNpeMhUnsolicitedCbMgrShowReset (
-    IxNpeMhNpeId npeId)
-{
-    /* reset the unsolicited callback table save counter */
-    ixNpeMhUnsolicitedCbMgrStats[npeId].saves = 0;
-
-    /* reset the unsolicited callback table overwrite counter */
-    ixNpeMhUnsolicitedCbMgrStats[npeId].overwrites = 0;
-}
diff --git a/drivers/net/npe/IxOsalBufferMgt.c b/drivers/net/npe/IxOsalBufferMgt.c
deleted file mode 100644
index f70ba05d9e..0000000000
--- a/drivers/net/npe/IxOsalBufferMgt.c
+++ /dev/null
@@ -1,776 +0,0 @@
-/**
- * @file IxOsalBufferMgt.c
- *
- * @brief Default buffer pool management and buffer management
- *        Implementation.
- *
- * Design Notes:
- *
- * @par
- * IXP400 SW Release version 2.0
- * 
- * -- Copyright Notice --
- * 
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- * 
- * @par
- * SPDX-License-Identifier:	BSD-3-Clause
- * @par
- * -- End of Copyright Notice --
- */
-
-/*
- * OS may choose to use default bufferMgt by defining
- * IX_OSAL_USE_DEFAULT_BUFFER_MGT in IxOsalOsBufferMgt.h  
- */
-
-#include "IxOsal.h"
-
-#define IX_OSAL_BUFFER_FREE_PROTECTION  /* Define this to enable Illegal MBuf Freed Protection*/
-
-/*
- * The implementation is only used when the following
- * is defined.
- */
-#ifdef IX_OSAL_USE_DEFAULT_BUFFER_MGT
-
-
-#define IX_OSAL_MBUF_SYS_SIGNATURE				(0x8BADF00D)
-#define IX_OSAL_MBUF_SYS_SIGNATURE_MASK				(0xEFFFFFFF)
-#define IX_OSAL_MBUF_USED_FLAG					(0x10000000)
-#define IX_OSAL_MBUF_SYS_SIGNATURE_INIT(bufPtr)        		IX_OSAL_MBUF_SIGNATURE (bufPtr) = (UINT32)IX_OSAL_MBUF_SYS_SIGNATURE
-
-/* 
-*  This implementation is protect, the buffer pool management's  ixOsalMBufFree 
-*  against an invalid MBUF pointer argument that already has been freed earlier 
-*  or in other words resides in the free pool of MBUFs. This added feature, 
-*  checks the MBUF "USED" FLAG. The Flag tells if the MBUF is still not freed 
-*  back to the Buffer Pool.
-*  Disable this feature for performance reasons by undef 
-*  IX_OSAL_BUFFER_FREE_PROTECTION macro.
-*/
-#ifdef IX_OSAL_BUFFER_FREE_PROTECTION  /*IX_OSAL_BUFFER_FREE_PROTECTION With Buffer Free protection*/
-
-#define IX_OSAL_MBUF_GET_SYS_SIGNATURE(bufPtr)		(IX_OSAL_MBUF_SIGNATURE (bufPtr)&(IX_OSAL_MBUF_SYS_SIGNATURE_MASK) )
-#define IX_OSAL_MBUF_SET_SYS_SIGNATURE(bufPtr)    do {																											\
-																									IX_OSAL_MBUF_SIGNATURE (bufPtr)&(~IX_OSAL_MBUF_SYS_SIGNATURE_MASK);\
-														    									IX_OSAL_MBUF_SIGNATURE (bufPtr)|=IX_OSAL_MBUF_SYS_SIGNATURE;			\
-																									}while(0)
-
-#define IX_OSAL_MBUF_SET_USED_FLAG(bufPtr)   IX_OSAL_MBUF_SIGNATURE (bufPtr)|=IX_OSAL_MBUF_USED_FLAG
-#define IX_OSAL_MBUF_CLEAR_USED_FLAG(bufPtr) IX_OSAL_MBUF_SIGNATURE (bufPtr)&=~IX_OSAL_MBUF_USED_FLAG
-#define IX_OSAL_MBUF_ISSET_USED_FLAG(bufPtr) (IX_OSAL_MBUF_SIGNATURE (bufPtr)&IX_OSAL_MBUF_USED_FLAG)
-
-#else
-
-#define IX_OSAL_MBUF_GET_SYS_SIGNATURE(bufPtr)	 IX_OSAL_MBUF_SIGNATURE (bufPtr)
-#define IX_OSAL_MBUF_SET_SYS_SIGNATURE(bufPtr)   IX_OSAL_MBUF_SIGNATURE (bufPtr) = IX_OSAL_MBUF_SYS_SIGNATURE
-
-#endif /*IX_OSAL_BUFFER_FREE_PROTECTION With Buffer Free protection*/
-/*
- * Variable declarations global to this file only.  Externs are followed by
- * static variables.
- */
-
-/* 
- * A unit of 32, used to provide bit-shift for pool
- * management. Needs some work if users want more than 32 pools.
- */
-#define IX_OSAL_BUFF_FREE_BITS 32
-
-PRIVATE UINT32 ixOsalBuffFreePools[IX_OSAL_MBUF_MAX_POOLS /
-    IX_OSAL_BUFF_FREE_BITS];
-
-PUBLIC IX_OSAL_MBUF_POOL ixOsalBuffPools[IX_OSAL_MBUF_MAX_POOLS];
-
-static int ixOsalBuffPoolsInUse = 0;
-
-#ifdef IX_OSAL_BUFFER_ALLOC_SEPARATELY
-PRIVATE IX_OSAL_MBUF *
-ixOsalBuffPoolMbufInit (UINT32 mbufSizeAligned,
-                      UINT32 dataSizeAligned,
-                      IX_OSAL_MBUF_POOL *poolPtr);
-#endif
-
-PRIVATE IX_OSAL_MBUF_POOL * ixOsalPoolAlloc (void);                      
-
-/*
- * Function definition: ixOsalPoolAlloc
- */
-
-/****************************/
-
-PRIVATE IX_OSAL_MBUF_POOL *
-ixOsalPoolAlloc (void)
-{
-    register unsigned int i = 0;
-
-    /*
-     * Scan for the first free buffer. Free buffers are indicated by 0
-     * on the corrsponding bit in ixOsalBuffFreePools. 
-     */
-    if (ixOsalBuffPoolsInUse >= IX_OSAL_MBUF_MAX_POOLS)
-    {
-        /*
-         * Fail to grab a ptr this time 
-         */
-        return NULL;
-    }
-
-    while (ixOsalBuffFreePools[i / IX_OSAL_BUFF_FREE_BITS] &
-        (1 << (i % IX_OSAL_BUFF_FREE_BITS)))
-        i++;
-    /*
-     * Free buffer found. Mark it as busy and initialize. 
-     */
-    ixOsalBuffFreePools[i / IX_OSAL_BUFF_FREE_BITS] |=
-        (1 << (i % IX_OSAL_BUFF_FREE_BITS));
-
-    memset (&ixOsalBuffPools[i], 0, sizeof (IX_OSAL_MBUF_POOL));
-
-    ixOsalBuffPools[i].poolIdx = i;
-    ixOsalBuffPoolsInUse++;
-
-    return &ixOsalBuffPools[i];
-}
-
-
-#ifdef IX_OSAL_BUFFER_ALLOC_SEPARATELY
-PRIVATE IX_OSAL_MBUF *
-ixOsalBuffPoolMbufInit (UINT32 mbufSizeAligned,
-                      UINT32 dataSizeAligned,
-                      IX_OSAL_MBUF_POOL *poolPtr)
-{
-    UINT8 *dataPtr;
-    IX_OSAL_MBUF *realMbufPtr;
-    /* Allocate cache-aligned memory for mbuf header */
-    realMbufPtr = (IX_OSAL_MBUF *) IX_OSAL_CACHE_DMA_MALLOC (mbufSizeAligned);
-    IX_OSAL_ASSERT (realMbufPtr != NULL);
-    memset (realMbufPtr, 0, mbufSizeAligned);
-
-    /* Allocate cache-aligned memory for mbuf data */
-    dataPtr = (UINT8 *) IX_OSAL_CACHE_DMA_MALLOC (dataSizeAligned);
-    IX_OSAL_ASSERT (dataPtr != NULL);
-    memset (dataPtr, 0, dataSizeAligned);
-
-    /* Fill in mbuf header fields */
-    IX_OSAL_MBUF_MDATA (realMbufPtr) = dataPtr;
-    IX_OSAL_MBUF_ALLOCATED_BUFF_DATA (realMbufPtr) = (UINT32)dataPtr;
-
-    IX_OSAL_MBUF_MLEN (realMbufPtr) = dataSizeAligned;
-    IX_OSAL_MBUF_ALLOCATED_BUFF_LEN (realMbufPtr) = dataSizeAligned;
-
-    IX_OSAL_MBUF_NET_POOL (realMbufPtr) = (IX_OSAL_MBUF_POOL *) poolPtr;
-
-    IX_OSAL_MBUF_SYS_SIGNATURE_INIT(realMbufPtr);
-
-    /* update some statistical information */
-    poolPtr->mbufMemSize += mbufSizeAligned;
-    poolPtr->dataMemSize += dataSizeAligned;
-
-    return realMbufPtr;
-}
-#endif /* #ifdef IX_OSAL_BUFFER_ALLOC_SEPARATELY */
-
-/*
- * Function definition: ixOsalBuffPoolInit
- */
-
-PUBLIC IX_OSAL_MBUF_POOL *
-ixOsalPoolInit (UINT32 count, UINT32 size, const char *name)
-{
-
-    /* These variables are only used if UX_OSAL_BUFFER_ALLOC_SEPERATELY
-     * is defined .
-     */
-#ifdef IX_OSAL_BUFFER_ALLOC_SEPARATELY
-    UINT32 i, mbufSizeAligned, dataSizeAligned;
-    IX_OSAL_MBUF *currentMbufPtr = NULL;
-#else
-    void *poolBufPtr;
-    void *poolDataPtr;
-    int mbufMemSize;
-    int dataMemSize;
-#endif
-
-    IX_OSAL_MBUF_POOL *poolPtr = NULL;
-    
-    if (count <= 0)
-    {
-        ixOsalLog (IX_OSAL_LOG_LVL_ERROR,
-            IX_OSAL_LOG_DEV_STDOUT,
-            "ixOsalPoolInit(): " "count = 0 \n", 0, 0, 0, 0, 0, 0);
-        return NULL;        
-    }
-
-    if (name == NULL)
-    {
-        ixOsalLog (IX_OSAL_LOG_LVL_ERROR,
-            IX_OSAL_LOG_DEV_STDOUT,
-            "ixOsalPoolInit(): " "NULL name \n", 0, 0, 0, 0, 0, 0);
-        return NULL;        
-    }
-    
-    if (strlen (name) > IX_OSAL_MBUF_POOL_NAME_LEN)
-    {
-        ixOsalLog (IX_OSAL_LOG_LVL_ERROR,
-            IX_OSAL_LOG_DEV_STDOUT,
-            "ixOsalPoolInit(): "
-            "ERROR - name length should be no greater than %d  \n",
-            IX_OSAL_MBUF_POOL_NAME_LEN, 0, 0, 0, 0, 0);
-        return NULL;
-    }
-
-/* OS can choose whether to allocate all buffers all together (if it 
- * can handle a huge single alloc request), or to allocate buffers 
- * separately by the defining IX_OSAL_BUFFER_ALLOC_SEPARATELY.
- */
-#ifdef IX_OSAL_BUFFER_ALLOC_SEPARATELY
-    /* Get a pool Ptr */
-    poolPtr = ixOsalPoolAlloc ();
-
-    if (poolPtr == NULL)
-    {
-        ixOsalLog (IX_OSAL_LOG_LVL_ERROR,
-            IX_OSAL_LOG_DEV_STDOUT,
-            "ixOsalPoolInit(): " "Fail to Get PoolPtr \n", 0, 0, 0, 0, 0, 0);    
-        return NULL;
-    }
-
-    mbufSizeAligned = IX_OSAL_MBUF_POOL_SIZE_ALIGN (sizeof (IX_OSAL_MBUF));
-    dataSizeAligned = IX_OSAL_MBUF_POOL_SIZE_ALIGN(size);
-
-    poolPtr->nextFreeBuf = NULL;    
-    poolPtr->mbufMemPtr = NULL;    
-    poolPtr->dataMemPtr = NULL;
-    poolPtr->bufDataSize = dataSizeAligned;
-    poolPtr->totalBufsInPool = count;
-    poolPtr->poolAllocType = IX_OSAL_MBUF_POOL_TYPE_SYS_ALLOC;
-    strcpy (poolPtr->name, name);
-
-
-    for (i = 0; i < count; i++)
-    {
-	    /* create an mbuf */
-	    currentMbufPtr = ixOsalBuffPoolMbufInit (mbufSizeAligned,
-					         dataSizeAligned,
-					         poolPtr);
-
-#ifdef IX_OSAL_BUFFER_FREE_PROTECTION 		
-/* Set the Buffer USED Flag. If not, ixOsalMBufFree will fail.
-   ixOsalMbufFree used here is in a special case whereby, it's 
-   used to add MBUF to the Pool. By specification, ixOsalMbufFree 
-   deallocates an allocated MBUF from Pool.
-*/ 			         
-      IX_OSAL_MBUF_SET_USED_FLAG(currentMbufPtr);
-#endif                             
-	    /* Add it to the pool */
-	    ixOsalMbufFree (currentMbufPtr);
-
-	    /* flush the pool information to RAM */
-	    IX_OSAL_CACHE_FLUSH (currentMbufPtr, mbufSizeAligned);
-    }
-    
-    /*
-     * update the number of free buffers in the pool 
-     */
-    poolPtr->freeBufsInPool = count;
-
-#else 
-/* Otherwise allocate buffers in a continuous block fashion */    
-    poolBufPtr = IX_OSAL_MBUF_POOL_MBUF_AREA_ALLOC (count, mbufMemSize);
-    IX_OSAL_ASSERT (poolBufPtr != NULL);
-    poolDataPtr =
-        IX_OSAL_MBUF_POOL_DATA_AREA_ALLOC (count, size, dataMemSize);
-    IX_OSAL_ASSERT (poolDataPtr != NULL);
-
-    poolPtr = ixOsalNoAllocPoolInit (poolBufPtr, poolDataPtr,
-        count, size, name);
-    if (poolPtr == NULL)
-    {
-        ixOsalLog (IX_OSAL_LOG_LVL_ERROR,
-            IX_OSAL_LOG_DEV_STDOUT,
-            "ixOsalPoolInit(): " "Fail to get pool ptr \n", 0, 0, 0, 0, 0, 0);
-        return NULL;
-    }
-
-    poolPtr->poolAllocType = IX_OSAL_MBUF_POOL_TYPE_SYS_ALLOC;
-
-#endif /* IX_OSAL_BUFFER_ALLOC_SEPARATELY */
-    return poolPtr;
-}
-
-PUBLIC IX_OSAL_MBUF_POOL *
-ixOsalNoAllocPoolInit (void *poolBufPtr,
-    void *poolDataPtr, UINT32 count, UINT32 size, const char *name)
-{
-    UINT32 i,  mbufSizeAligned, sizeAligned;
-    IX_OSAL_MBUF *currentMbufPtr = NULL;
-    IX_OSAL_MBUF *nextMbufPtr = NULL;
-    IX_OSAL_MBUF_POOL *poolPtr = NULL;
-
-    /*
-     * check parameters 
-     */
-    if (poolBufPtr == NULL)
-    {
-        ixOsalLog (IX_OSAL_LOG_LVL_ERROR,
-            IX_OSAL_LOG_DEV_STDOUT,
-            "ixOsalNoAllocPoolInit(): "
-            "ERROR - NULL poolBufPtr \n", 0, 0, 0, 0, 0, 0);
-        return NULL;
-    }
-
-    if (count <= 0)
-    {
-        ixOsalLog (IX_OSAL_LOG_LVL_ERROR,
-            IX_OSAL_LOG_DEV_STDOUT,
-            "ixOsalNoAllocPoolInit(): "
-            "ERROR - count must > 0   \n", 0, 0, 0, 0, 0, 0);
-        return NULL;
-    }
-
-    if (name == NULL)
-    {
-        ixOsalLog (IX_OSAL_LOG_LVL_ERROR,
-            IX_OSAL_LOG_DEV_STDOUT,
-            "ixOsalNoAllocPoolInit(): "
-            "ERROR - NULL name ptr  \n", 0, 0, 0, 0, 0, 0);
-        return NULL;
-    }
-
-    if (strlen (name) > IX_OSAL_MBUF_POOL_NAME_LEN)
-    {
-        ixOsalLog (IX_OSAL_LOG_LVL_ERROR,
-            IX_OSAL_LOG_DEV_STDOUT,
-            "ixOsalNoAllocPoolInit(): "
-            "ERROR - name length should be no greater than %d  \n",
-            IX_OSAL_MBUF_POOL_NAME_LEN, 0, 0, 0, 0, 0);
-        return NULL;
-    }
-
-    poolPtr = ixOsalPoolAlloc ();
-
-    if (poolPtr == NULL)
-    {
-        return NULL;
-    }
-
-    /*
-     * Adjust sizes to ensure alignment on cache line boundaries 
-     */
-    mbufSizeAligned =
-        IX_OSAL_MBUF_POOL_SIZE_ALIGN (sizeof (IX_OSAL_MBUF));
-    /*
-     * clear the mbuf memory area 
-     */
-    memset (poolBufPtr, 0, mbufSizeAligned * count);
-
-    if (poolDataPtr != NULL)
-    {
-        /*
-         * Adjust sizes to ensure alignment on cache line boundaries 
-         */
-        sizeAligned = IX_OSAL_MBUF_POOL_SIZE_ALIGN (size);
-        /*
-         * clear the data memory area 
-         */
-        memset (poolDataPtr, 0, sizeAligned * count);
-    }
-    else
-    {
-        sizeAligned = 0;
-    }
-
-    /*
-     * initialise pool fields 
-     */
-    strcpy ((poolPtr)->name, name);
-
-    poolPtr->dataMemPtr = poolDataPtr;
-    poolPtr->mbufMemPtr = poolBufPtr;
-    poolPtr->bufDataSize = sizeAligned;
-    poolPtr->totalBufsInPool = count;
-    poolPtr->mbufMemSize = mbufSizeAligned * count;
-    poolPtr->dataMemSize = sizeAligned * count;
-
-    currentMbufPtr = (IX_OSAL_MBUF *) poolBufPtr;
-
-    poolPtr->nextFreeBuf = currentMbufPtr;
-
-    for (i = 0; i < count; i++)
-    {
-        if (i < (count - 1))
-        {
-            nextMbufPtr =
-                (IX_OSAL_MBUF *) ((unsigned) currentMbufPtr +
-                mbufSizeAligned);
-        }
-        else
-        {                       /* last mbuf in chain */
-            nextMbufPtr = NULL;
-        }
-        IX_OSAL_MBUF_NEXT_BUFFER_IN_PKT_PTR (currentMbufPtr) = nextMbufPtr;
-        IX_OSAL_MBUF_NET_POOL (currentMbufPtr) = poolPtr;
-
-        IX_OSAL_MBUF_SYS_SIGNATURE_INIT(currentMbufPtr);
-
-        if (poolDataPtr != NULL)
-        {
-            IX_OSAL_MBUF_MDATA (currentMbufPtr) = poolDataPtr;
-            IX_OSAL_MBUF_ALLOCATED_BUFF_DATA(currentMbufPtr) = (UINT32) poolDataPtr;
-
-            IX_OSAL_MBUF_MLEN (currentMbufPtr) = sizeAligned;
-            IX_OSAL_MBUF_ALLOCATED_BUFF_LEN(currentMbufPtr) = sizeAligned;
-
-            poolDataPtr = (void *) ((unsigned) poolDataPtr + sizeAligned);
-        }
-
-        currentMbufPtr = nextMbufPtr;
-    }
-
-    /*
-     * update the number of free buffers in the pool 
-     */
-    poolPtr->freeBufsInPool = count;
-
-    poolPtr->poolAllocType = IX_OSAL_MBUF_POOL_TYPE_USER_ALLOC;
-
-    return poolPtr;
-}
-
-/* 
- * Get a mbuf ptr from the pool
- */
-PUBLIC IX_OSAL_MBUF *
-ixOsalMbufAlloc (IX_OSAL_MBUF_POOL * poolPtr)
-{
-    int lock;
-    IX_OSAL_MBUF *newBufPtr = NULL;
-
-    /*
-     * check parameters 
-     */
-    if (poolPtr == NULL)
-    {
-        ixOsalLog (IX_OSAL_LOG_LVL_ERROR,
-            IX_OSAL_LOG_DEV_STDOUT,
-            "ixOsalMbufAlloc(): "
-            "ERROR - Invalid Parameter\n", 0, 0, 0, 0, 0, 0);
-        return NULL;
-    }
-
-    lock = ixOsalIrqLock ();
-
-    newBufPtr = poolPtr->nextFreeBuf;
-    if (newBufPtr)
-    {
-        poolPtr->nextFreeBuf =
-            IX_OSAL_MBUF_NEXT_BUFFER_IN_PKT_PTR (newBufPtr);
-        IX_OSAL_MBUF_NEXT_BUFFER_IN_PKT_PTR (newBufPtr) = NULL;
-
-        /*
-         * update the number of free buffers in the pool 
-         */
-        poolPtr->freeBufsInPool--;
-    }
-    else
-    {
-        /* Return NULL to indicate to caller that request is denied. */
-        ixOsalIrqUnlock (lock);
-
-        return NULL;
-    }
-
-#ifdef IX_OSAL_BUFFER_FREE_PROTECTION
-	/* Set Buffer Used Flag to indicate state.*/
-    IX_OSAL_MBUF_SET_USED_FLAG(newBufPtr);
-#endif
-
-    ixOsalIrqUnlock (lock);
-
-    return newBufPtr;
-}
-
-PUBLIC IX_OSAL_MBUF *
-ixOsalMbufFree (IX_OSAL_MBUF * bufPtr)
-{
-    int lock;
-    IX_OSAL_MBUF_POOL *poolPtr;
-
-    IX_OSAL_MBUF *nextBufPtr = NULL;
-
-    /*
-     * check parameters 
-     */
-    if (bufPtr == NULL)
-    {
-        ixOsalLog (IX_OSAL_LOG_LVL_ERROR,
-            IX_OSAL_LOG_DEV_STDOUT,
-            "ixOsalMbufFree(): "
-            "ERROR - Invalid Parameter\n", 0, 0, 0, 0, 0, 0);
-        return NULL;
-    }
-
-
-
-    lock = ixOsalIrqLock ();
-
-#ifdef IX_OSAL_BUFFER_FREE_PROTECTION
-	
-	/* Prevention for Buffer freed more than once*/
-    if(!IX_OSAL_MBUF_ISSET_USED_FLAG(bufPtr))
-    {
-   	return NULL;
-    }
-    IX_OSAL_MBUF_CLEAR_USED_FLAG(bufPtr);
-#endif
-	
-    poolPtr = IX_OSAL_MBUF_NET_POOL (bufPtr);
-
-    /*
-     * check the mbuf wrapper signature (if mbuf wrapper was used) 
-     */
-    if (poolPtr->poolAllocType == IX_OSAL_MBUF_POOL_TYPE_SYS_ALLOC)
-    {
-        IX_OSAL_ENSURE ( (IX_OSAL_MBUF_GET_SYS_SIGNATURE(bufPtr) == IX_OSAL_MBUF_SYS_SIGNATURE),
-            "ixOsalBuffPoolBufFree: ERROR - Invalid mbuf signature.");
-    }
-
-    nextBufPtr = IX_OSAL_MBUF_NEXT_BUFFER_IN_PKT_PTR (bufPtr);
-
-    IX_OSAL_MBUF_NEXT_BUFFER_IN_PKT_PTR (bufPtr) = poolPtr->nextFreeBuf;
-    poolPtr->nextFreeBuf = bufPtr;
-
-    /*
-     * update the number of free buffers in the pool 
-     */
-    poolPtr->freeBufsInPool++;
-
-    ixOsalIrqUnlock (lock);
-
-    return nextBufPtr;
-}
-
-PUBLIC void
-ixOsalMbufChainFree (IX_OSAL_MBUF * bufPtr)
-{
-    while ((bufPtr = ixOsalMbufFree (bufPtr)));
-}
-
-/*
- * Function definition: ixOsalBuffPoolShow
- */
-PUBLIC void
-ixOsalMbufPoolShow (IX_OSAL_MBUF_POOL * poolPtr)
-{
-    IX_OSAL_MBUF *nextBufPtr;
-    int count = 0;
-    int lock;
-
-    /*
-     * check parameters 
-     */
-    if (poolPtr == NULL)
-    {
-        ixOsalLog (IX_OSAL_LOG_LVL_ERROR,
-            IX_OSAL_LOG_DEV_STDOUT,
-            "ixOsalBuffPoolShow(): "
-            "ERROR - Invalid Parameter", 0, 0, 0, 0, 0, 0);
-        /*
-         * return IX_FAIL; 
-         */
-        return;
-    }
-
-    lock = ixOsalIrqLock ();
-    count = poolPtr->freeBufsInPool;
-    nextBufPtr = poolPtr->nextFreeBuf;
-    ixOsalIrqUnlock (lock);
-
-    ixOsalLog (IX_OSAL_LOG_LVL_MESSAGE,
-        IX_OSAL_LOG_DEV_STDOUT, "=== POOL INFORMATION ===\n", 0, 0, 0,
-        0, 0, 0);
-    ixOsalLog (IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT,
-        "Pool Name:                   %s\n",
-        (unsigned int) poolPtr->name, 0, 0, 0, 0, 0);
-    ixOsalLog (IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT,
-        "Pool Allocation Type:        %d\n",
-        (unsigned int) poolPtr->poolAllocType, 0, 0, 0, 0, 0);
-    ixOsalLog (IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT,
-        "Pool Mbuf Mem Usage (bytes): %d\n",
-        (unsigned int) poolPtr->mbufMemSize, 0, 0, 0, 0, 0);
-    ixOsalLog (IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT,
-        "Pool Data Mem Usage (bytes): %d\n",
-        (unsigned int) poolPtr->dataMemSize, 0, 0, 0, 0, 0);
-    ixOsalLog (IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT,
-        "Mbuf Data Capacity  (bytes): %d\n",
-        (unsigned int) poolPtr->bufDataSize, 0, 0, 0, 0, 0);
-    ixOsalLog (IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT,
-        "Total Mbufs in Pool:         %d\n",
-        (unsigned int) poolPtr->totalBufsInPool, 0, 0, 0, 0, 0);
-    ixOsalLog (IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT,
-        "Available Mbufs:             %d\n", (unsigned int) count, 0,
-        0, 0, 0, 0);
-    ixOsalLog (IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT,
-        "Next Available Mbuf:         %p\n", (unsigned int) nextBufPtr,
-        0, 0, 0, 0, 0);
-
-    if (poolPtr->poolAllocType == IX_OSAL_MBUF_POOL_TYPE_USER_ALLOC)
-    {
-        ixOsalLog (IX_OSAL_LOG_LVL_MESSAGE,
-            IX_OSAL_LOG_DEV_STDOUT,
-            "Mbuf Mem Area Start address: %p\n",
-            (unsigned int) poolPtr->mbufMemPtr, 0, 0, 0, 0, 0);
-        ixOsalLog (IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT,
-            "Data Mem Area Start address: %p\n",
-            (unsigned int) poolPtr->dataMemPtr, 0, 0, 0, 0, 0);
-    }
-}
-
-PUBLIC void
-ixOsalMbufDataPtrReset (IX_OSAL_MBUF * bufPtr)
-{
-    IX_OSAL_MBUF_POOL *poolPtr;
-    UINT8 *poolDataPtr;
-
-    if (bufPtr == NULL)
-    {
-        ixOsalLog (IX_OSAL_LOG_LVL_ERROR, IX_OSAL_LOG_DEV_STDOUT,
-            "ixOsalBuffPoolBufDataPtrReset"
-            ": ERROR - Invalid Parameter\n", 0, 0, 0, 0, 0, 0);
-        return;
-    }
-
-    poolPtr = (IX_OSAL_MBUF_POOL *) IX_OSAL_MBUF_NET_POOL (bufPtr);
-    poolDataPtr = poolPtr->dataMemPtr;
-
-    if (poolPtr->poolAllocType == IX_OSAL_MBUF_POOL_TYPE_SYS_ALLOC)
-    {
-        if (IX_OSAL_MBUF_GET_SYS_SIGNATURE(bufPtr) != IX_OSAL_MBUF_SYS_SIGNATURE)
-        {
-            ixOsalLog (IX_OSAL_LOG_LVL_ERROR, IX_OSAL_LOG_DEV_STDOUT,
-                "ixOsalBuffPoolBufDataPtrReset"
-                ": invalid mbuf, cannot reset mData pointer\n", 0, 0,
-                0, 0, 0, 0);
-            return;
-        }
-        IX_OSAL_MBUF_MDATA (bufPtr) = (UINT8*)IX_OSAL_MBUF_ALLOCATED_BUFF_DATA (bufPtr);
-    }
-    else
-    {
-        if (poolDataPtr)
-        {
-            unsigned int bufSize = poolPtr->bufDataSize;
-            unsigned int bufDataAddr =
-                (unsigned int) IX_OSAL_MBUF_MDATA (bufPtr);
-            unsigned int poolDataAddr = (unsigned int) poolDataPtr;
-
-            /*
-             * the pointer is still pointing somewhere in the mbuf payload.
-             * This operation moves the pointer to the beginning of the 
-             * mbuf payload
-             */
-            bufDataAddr = ((bufDataAddr - poolDataAddr) / bufSize) * bufSize;
-            IX_OSAL_MBUF_MDATA (bufPtr) = &poolDataPtr[bufDataAddr];
-        }
-        else
-        {
-            ixOsalLog (IX_OSAL_LOG_LVL_WARNING, IX_OSAL_LOG_DEV_STDOUT,
-                "ixOsalBuffPoolBufDataPtrReset"
-                ": cannot be used if user supplied NULL pointer for pool data area "
-                "when pool was created\n", 0, 0, 0, 0, 0, 0);
-            return;
-        }
-    }
-
-}
-
-/*
- * Function definition: ixOsalBuffPoolUninit
- */
-PUBLIC IX_STATUS
-ixOsalBuffPoolUninit (IX_OSAL_MBUF_POOL * pool)
-{
-    if (!pool)
-    {
-        ixOsalLog (IX_OSAL_LOG_LVL_ERROR, IX_OSAL_LOG_DEV_STDOUT,
-            "ixOsalBuffPoolUninit: NULL ptr \n", 0, 0, 0, 0, 0, 0);
-        return IX_FAIL;
-    }
-
-    if (pool->freeBufsInPool != pool->totalBufsInPool)
-    {
-        ixOsalLog (IX_OSAL_LOG_LVL_ERROR, IX_OSAL_LOG_DEV_STDOUT,
-            "ixOsalBuffPoolUninit: need to return all ptrs to the pool first! \n",
-            0, 0, 0, 0, 0, 0);
-        return IX_FAIL;
-    }
-
-    if (pool->poolAllocType == IX_OSAL_MBUF_POOL_TYPE_SYS_ALLOC)
-    {
-#ifdef IX_OSAL_BUFFER_ALLOC_SEPARATELY
-				UINT32 i;
-				IX_OSAL_MBUF* pBuf;
-				
-				pBuf = pool->nextFreeBuf;
-				/* Freed the Buffer one by one till all the Memory is freed*/
-				for (i= pool->freeBufsInPool; i >0 && pBuf!=NULL ;i--){
-						IX_OSAL_MBUF* pBufTemp;
-						pBufTemp = IX_OSAL_MBUF_NEXT_BUFFER_IN_PKT_PTR(pBuf);
-						/* Freed MBUF Data Memory area*/
-						IX_OSAL_CACHE_DMA_FREE( (void *) (IX_OSAL_MBUF_ALLOCATED_BUFF_DATA(pBuf)) );
-						/* Freed MBUF Struct Memory area*/
-						IX_OSAL_CACHE_DMA_FREE(pBuf);
-						pBuf = pBufTemp;
-				}
-				
-#else    	
-        IX_OSAL_CACHE_DMA_FREE (pool->mbufMemPtr);
-        IX_OSAL_CACHE_DMA_FREE (pool->dataMemPtr);
-#endif        
-    }
-
-    ixOsalBuffFreePools[pool->poolIdx / IX_OSAL_BUFF_FREE_BITS] &=
-        ~(1 << (pool->poolIdx % IX_OSAL_BUFF_FREE_BITS));
-    ixOsalBuffPoolsInUse--;
-    return IX_SUCCESS;
-}
-
-/*
- * Function definition: ixOsalBuffPoolDataAreaSizeGet
- */
-PUBLIC UINT32
-ixOsalBuffPoolDataAreaSizeGet (int count, int size)
-{
-    UINT32 memorySize;
-    memorySize = count * IX_OSAL_MBUF_POOL_SIZE_ALIGN (size);
-    return memorySize;
-}
-
-/*
- * Function definition: ixOsalBuffPoolMbufAreaSizeGet
- */
-PUBLIC UINT32
-ixOsalBuffPoolMbufAreaSizeGet (int count)
-{
-    UINT32 memorySize;
-    memorySize =
-        count * IX_OSAL_MBUF_POOL_SIZE_ALIGN (sizeof (IX_OSAL_MBUF));
-    return memorySize;
-}
-
-/*
- * Function definition: ixOsalBuffPoolFreeCountGet
- */
-PUBLIC UINT32 ixOsalBuffPoolFreeCountGet(IX_OSAL_MBUF_POOL * poolPtr)
-
-{
-
-   return poolPtr->freeBufsInPool;
-
-}
-
-#endif /* IX_OSAL_USE_DEFAULT_BUFFER_MGT */
diff --git a/drivers/net/npe/IxOsalIoMem.c b/drivers/net/npe/IxOsalIoMem.c
deleted file mode 100644
index bf3acdc10c..0000000000
--- a/drivers/net/npe/IxOsalIoMem.c
+++ /dev/null
@@ -1,307 +0,0 @@
-/**
- * @file IxOsalIoMem.c 
- *
- * @brief OS-independent IO/Mem implementation 
- * 
- * 
- * @par
- * IXP400 SW Release version 2.0
- * 
- * -- Copyright Notice --
- * 
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- * 
- * @par
- * SPDX-License-Identifier:	BSD-3-Clause
- * @par
- * -- End of Copyright Notice --
- */
-
-/* Access to the global mem map is only allowed in this file */
-#define IxOsalIoMem_C
-
-#include "IxOsal.h"
-
-#define SEARCH_PHYSICAL_ADDRESS (1)
-#define SEARCH_VIRTUAL_ADDRESS  (2)
-
-/*
- * Searches for map using one of the following criteria:
- * 
- * - enough room to include a zone starting with the physical "requestedAddress" of size "size" (for mapping)
- * - includes the virtual "requestedAddress" in its virtual address space (already mapped, for unmapping)
- * - correct coherency
- *
- * Returns a pointer to the map or NULL if a suitable map is not found.
- */
-PRIVATE IxOsalMemoryMap *
-ixOsalMemMapFind (UINT32 requestedAddress,
-    UINT32 size, UINT32 searchCriteria, UINT32 requestedEndianType)
-{
-    UINT32 mapIndex;
-
-    UINT32 numMapElements = ARRAY_SIZE(ixOsalGlobalMemoryMap);
-
-    for (mapIndex = 0; mapIndex < numMapElements; mapIndex++)
-    {
-        IxOsalMemoryMap *map = &ixOsalGlobalMemoryMap[mapIndex];
-
-        if (searchCriteria == SEARCH_PHYSICAL_ADDRESS
-            && requestedAddress >= map->physicalAddress
-            && (requestedAddress + size) <= (map->physicalAddress + map->size)
-            && (map->mapEndianType & requestedEndianType) != 0)
-        {
-            return map;
-        }
-        else if (searchCriteria == SEARCH_VIRTUAL_ADDRESS
-            && requestedAddress >= map->virtualAddress
-            && requestedAddress <= (map->virtualAddress + map->size)
-            && (map->mapEndianType & requestedEndianType) != 0)
-        {
-            return map;
-        }
-        else if (searchCriteria == SEARCH_PHYSICAL_ADDRESS)
-        {
-            ixOsalLog (IX_OSAL_LOG_LVL_DEBUG3,
-                IX_OSAL_LOG_DEV_STDOUT,
-                "Osal: Checking [phys addr 0x%x:size 0x%x:endianType %d]\n",
-                map->physicalAddress, map->size, map->mapEndianType, 0, 0, 0);
-        }
-    }
-
-    /*
-     * not found 
-     */
-    return NULL;
-}
-
-/*
- * This function maps an I/O mapped physical memory zone of the given size
- * into a virtual memory zone accessible by the caller and returns a cookie - 
- * the start address of the virtual memory zone. 
- * IX_OSAL_MMAP_PHYS_TO_VIRT should NOT therefore be used on the returned 
- * virtual address.
- * The memory zone is to be unmapped using ixOsalMemUnmap once the caller has
- * finished using this zone (e.g. on driver unload) using the cookie as 
- * parameter.
- * The IX_OSAL_READ/WRITE_LONG/SHORT macros should be used to read and write 
- * the mapped memory, adding the necessary offsets to the address cookie.
- *
- * Note: this function is not to be used directly. Use IX_OSAL_MEM_MAP 
- * instead.
- */
-PUBLIC void *
-ixOsalIoMemMap (UINT32 requestedAddress,
-    UINT32 size, IxOsalMapEndianessType requestedEndianType)
-{
-    IxOsalMemoryMap *map;
-
-    ixOsalLog (IX_OSAL_LOG_LVL_DEBUG3,
-        IX_OSAL_LOG_DEV_STDOUT,
-        "OSAL: Mapping [addr 0x%x:size 0x%x:endianType %d]\n",
-        requestedAddress, size, requestedEndianType, 0, 0, 0);
-
-    if (requestedEndianType == IX_OSAL_LE)
-    {
-        ixOsalLog (IX_OSAL_LOG_LVL_ERROR,
-            IX_OSAL_LOG_DEV_STDOUT,
-            "ixOsalIoMemMap: Please specify component coherency mode to use MEM functions \n",
-            0, 0, 0, 0, 0, 0);
-        return (NULL);
-    }
-    map = ixOsalMemMapFind (requestedAddress,
-        size, SEARCH_PHYSICAL_ADDRESS, requestedEndianType);
-    if (map != NULL)
-    {
-        UINT32 offset = requestedAddress - map->physicalAddress;
-
-        ixOsalLog (IX_OSAL_LOG_LVL_DEBUG3,
-            IX_OSAL_LOG_DEV_STDOUT, "OSAL: Found map [", 0, 0, 0, 0, 0, 0);
-        ixOsalLog (IX_OSAL_LOG_LVL_DEBUG3,
-            IX_OSAL_LOG_DEV_STDOUT, map->name, 0, 0, 0, 0, 0, 0);
-        ixOsalLog (IX_OSAL_LOG_LVL_DEBUG3,
-            IX_OSAL_LOG_DEV_STDOUT,
-            ":addr 0x%x: virt 0x%x:size 0x%x:ref %d:endianType %d]\n",
-            map->physicalAddress, map->virtualAddress,
-            map->size, map->refCount, map->mapEndianType, 0);
-
-        if (map->type == IX_OSAL_DYNAMIC_MAP && map->virtualAddress == 0)
-        {
-            if (map->mapFunction != NULL)
-            {
-                map->mapFunction (map);
-
-                if (map->virtualAddress == 0)
-                {
-                    /*
-                     * failed 
-                     */
-                    ixOsalLog (IX_OSAL_LOG_LVL_FATAL,
-                        IX_OSAL_LOG_DEV_STDERR,
-                        "OSAL: Remap failed - [addr 0x%x:size 0x%x:endianType %d]\n",
-                        requestedAddress, size, requestedEndianType, 0, 0, 0);
-                    return NULL;
-                }
-            }
-            else
-            {
-                /*
-                 * error, no map function for a dynamic map 
-                 */
-                ixOsalLog (IX_OSAL_LOG_LVL_FATAL,
-                    IX_OSAL_LOG_DEV_STDERR,
-                    "OSAL: No map function for a dynamic map - "
-                    "[addr 0x%x:size 0x%x:endianType %d]\n",
-                    requestedAddress, size, requestedEndianType, 0, 0, 0);
-
-                return NULL;
-            }
-        }
-
-        /*
-         * increment reference count 
-         */
-        map->refCount++;
-
-        return (void *) (map->virtualAddress + offset);
-    }
-
-    /*
-     * requested address is not described in the global memory map 
-     */
-    ixOsalLog (IX_OSAL_LOG_LVL_FATAL,
-        IX_OSAL_LOG_DEV_STDERR,
-        "OSAL: No mapping found - [addr 0x%x:size 0x%x:endianType %d]\n",
-        requestedAddress, size, requestedEndianType, 0, 0, 0);
-    return NULL;
-}
-
-/*
- * This function unmaps a previously mapped I/O memory zone using
- * the cookie obtained in the mapping operation. The memory zone in question
- * becomes unavailable to the caller once unmapped and the cookie should be
- * discarded.
- *
- * This function cannot fail if the given parameter is correct and does not
- * return a value.
- *
- * Note: this function is not to be used directly. Use IX_OSAL_MEM_UNMAP
- * instead.
- */
-PUBLIC void
-ixOsalIoMemUnmap (UINT32 requestedAddress, UINT32 endianType)
-{
-    IxOsalMemoryMap *map;
-
-    if (endianType == IX_OSAL_LE)
-    {
-        ixOsalLog (IX_OSAL_LOG_LVL_ERROR,
-            IX_OSAL_LOG_DEV_STDOUT,
-            "ixOsalIoMemUnmap: Please specify component coherency mode to use MEM functions \n",
-            0, 0, 0, 0, 0, 0);
-        return;
-    }
-
-    if (requestedAddress == 0)
-    {
-        /*
-         * invalid virtual address 
-         */
-        return;
-    }
-
-    map =
-        ixOsalMemMapFind (requestedAddress, 0, SEARCH_VIRTUAL_ADDRESS,
-        endianType);
-
-    if (map != NULL)
-    {
-        if (map->refCount > 0)
-        {
-            /*
-             * decrement reference count 
-             */
-            map->refCount--;
-
-            if (map->refCount == 0)
-            {
-                /*
-                 * no longer used, deallocate 
-                 */
-                if (map->type == IX_OSAL_DYNAMIC_MAP
-                    && map->unmapFunction != NULL)
-                {
-                    map->unmapFunction (map);
-                }
-            }
-        }
-    }
-    else
-    {
-        ixOsalLog (IX_OSAL_LOG_LVL_WARNING,
-            IX_OSAL_LOG_DEV_STDERR,
-            "OSAL: ixOsServMemUnmap didn't find the requested map "
-            "[virt addr 0x%x: endianType %d], ignoring call\n",
-            requestedAddress, endianType, 0, 0, 0, 0);
-    }
-}
-
-/* 
- * This function Converts a virtual address into a physical 
- * address, including the dynamically mapped memory.
- * 
- * Parameters	virtAddr - virtual address to convert
- * Return value: corresponding physical address, or NULL 
- *               if there is no physical address addressable 
- *               by the given virtual address
- * OS:	VxWorks, Linux, WinCE, QNX, eCos
- * Reentrant: Yes
- * IRQ safe: Yes
- */
-PUBLIC UINT32
-ixOsalIoMemVirtToPhys (UINT32 virtualAddress, UINT32 requestedCoherency)
-{
-    IxOsalMemoryMap *map =
-        ixOsalMemMapFind (virtualAddress, 0, SEARCH_VIRTUAL_ADDRESS,
-        requestedCoherency);
-
-    if (map != NULL)
-    {
-        return map->physicalAddress + virtualAddress - map->virtualAddress;
-    }
-    else
-    {
-        return (UINT32) IX_OSAL_MMU_VIRT_TO_PHYS (virtualAddress);
-    }
-}
-
-/* 
- * This function Converts a virtual address into a physical 
- * address, including the dynamically mapped memory.
- * 
- * Parameters	virtAddr - virtual address to convert
- * Return value: corresponding physical address, or NULL 
- *               if there is no physical address addressable 
- *               by the given virtual address
- * OS:	VxWorks, Linux, WinCE, QNX, eCos
- * Reentrant: Yes
- * IRQ safe: Yes
- */
-PUBLIC UINT32
-ixOsalIoMemPhysToVirt (UINT32 physicalAddress, UINT32 requestedCoherency)
-{
-    IxOsalMemoryMap *map =
-        ixOsalMemMapFind (physicalAddress, 0, SEARCH_PHYSICAL_ADDRESS,
-        requestedCoherency);
-
-    if (map != NULL)
-    {
-        return map->virtualAddress + physicalAddress - map->physicalAddress;
-    }
-    else
-    {
-        return (UINT32) IX_OSAL_MMU_PHYS_TO_VIRT (physicalAddress);
-    }
-}
diff --git a/drivers/net/npe/IxOsalOsCacheMMU.c b/drivers/net/npe/IxOsalOsCacheMMU.c
deleted file mode 100644
index 72d22e5882..0000000000
--- a/drivers/net/npe/IxOsalOsCacheMMU.c
+++ /dev/null
@@ -1,43 +0,0 @@
-/**
- * @file IxOsalOsCacheMMU.c (linux)
- *
- * @brief Cache MemAlloc and MemFree.
- *
- *
- * @par
- * IXP400 SW Release version 1.5
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * SPDX-License-Identifier:	BSD-3-Clause
- * @par
- * -- End of Copyright Notice --
- */
-
-#include "IxOsal.h"
-
-#include <malloc.h>
-
-/*
- * Allocate on a cache line boundary (null pointers are
- * not affected by this operation). This operation is NOT cache safe.
- */
-void *
-ixOsalCacheDmaMalloc (UINT32 n)
-{
-	return malloc(n);
-}
-
-/*
- *
- */
-void
-ixOsalCacheDmaFree (void *ptr)
-{
-	free(ptr);
-}
diff --git a/drivers/net/npe/IxOsalOsMsgQ.c b/drivers/net/npe/IxOsalOsMsgQ.c
deleted file mode 100644
index 5fe368bdaf..0000000000
--- a/drivers/net/npe/IxOsalOsMsgQ.c
+++ /dev/null
@@ -1,55 +0,0 @@
-/**
- * @file IxOsalOsMsgQ.c (eCos)
- *
- * @brief OS-specific Message Queue implementation.
- *
- *
- * @par
- * IXP400 SW Release version 1.5
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * SPDX-License-Identifier:	BSD-3-Clause
- * @par
- * -- End of Copyright Notice --
- */
-
-#include "IxOsal.h"
-
-/*******************************
- * Public functions
- *******************************/
-PUBLIC IX_STATUS
-ixOsalMessageQueueCreate (IxOsalMessageQueue * queue,
-    UINT32 msgCount, UINT32 msgLen)
-{
-    diag_printf("%s called\n", __FUNCTION__);
-    return IX_FAIL;
-}
-
-PUBLIC IX_STATUS
-ixOsalMessageQueueDelete (IxOsalMessageQueue * queue)
-{
-    diag_printf("%s called\n", __FUNCTION__);
-    return IX_FAIL;
-}
-
-PUBLIC IX_STATUS
-ixOsalMessageQueueSend (IxOsalMessageQueue * queue, UINT8 * message)
-{
-    diag_printf("%s called\n", __FUNCTION__);
-    return IX_FAIL;
-}
-
-PUBLIC IX_STATUS
-ixOsalMessageQueueReceive (IxOsalMessageQueue * queue, UINT8 * message)
-{
-    diag_printf("%s called\n", __FUNCTION__);
-    return IX_FAIL;
-}
-
diff --git a/drivers/net/npe/IxOsalOsSemaphore.c b/drivers/net/npe/IxOsalOsSemaphore.c
deleted file mode 100644
index 33de7f6e42..0000000000
--- a/drivers/net/npe/IxOsalOsSemaphore.c
+++ /dev/null
@@ -1,209 +0,0 @@
-/**
- * @file IxOsalOsSemaphore.c (eCos)
- *
- * @brief Implementation for semaphore and mutex.
- *
- *
- * @par
- * IXP400 SW Release version 1.5
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * SPDX-License-Identifier:	BSD-3-Clause
- * @par
- * -- End of Copyright Notice --
- */
-
-#include "IxOsal.h"
-#include "IxNpeMhReceive_p.h"
-
-/* Define a large number */
-#define IX_OSAL_MAX_LONG (0x7FFFFFFF)
-
-/* Max timeout in MS, used to guard against possible overflow */
-#define IX_OSAL_MAX_TIMEOUT_MS (IX_OSAL_MAX_LONG/HZ)
-
-
-PUBLIC IX_STATUS
-ixOsalSemaphoreInit (IxOsalSemaphore * sid, UINT32 start_value)
-{
-    diag_printf("%s called\n", __FUNCTION__);
-    return IX_SUCCESS;
-}
-
-/**
- * DESCRIPTION: If the semaphore is 'empty', the calling thread is blocked.
- *              If the semaphore is 'full', it is taken and control is returned
- *              to the caller. If the time indicated in 'timeout' is reached,
- *              the thread will unblock and return an error indication. If the
- *              timeout is set to 'IX_OSAL_WAIT_NONE', the thread will never block;
- *              if it is set to 'IX_OSAL_WAIT_FOREVER', the thread will block until
- *              the semaphore is available.
- *
- *
- */
-
-
-PUBLIC IX_STATUS
-ixOsalSemaphoreWait (IxOsalOsSemaphore * sid, INT32 timeout)
-{
-    diag_printf("%s called\n", __FUNCTION__);
-    return IX_SUCCESS;
-}
-
-/*
- * Attempt to get semaphore, return immediately,
- * no error info because users expect some failures
- * when using this API.
- */
-PUBLIC IX_STATUS
-ixOsalSemaphoreTryWait (IxOsalSemaphore * sid)
-{
-    diag_printf("%s called\n", __FUNCTION__);
-    return IX_FAIL;
-}
-
-/**
- *
- * DESCRIPTION: This function causes the next available thread in the pend queue
- *              to be unblocked. If no thread is pending on this semaphore, the
- *              semaphore becomes 'full'.
- */
-PUBLIC IX_STATUS
-ixOsalSemaphorePost (IxOsalSemaphore * sid)
-{
-    diag_printf("%s called\n", __FUNCTION__);
-    return IX_SUCCESS;
-}
-
-PUBLIC IX_STATUS
-ixOsalSemaphoreGetValue (IxOsalSemaphore * sid, UINT32 * value)
-{
-    diag_printf("%s called\n", __FUNCTION__);
-    return IX_FAIL;
-}
-
-PUBLIC IX_STATUS
-ixOsalSemaphoreDestroy (IxOsalSemaphore * sid)
-{
-    diag_printf("%s called\n", __FUNCTION__);
-    return IX_FAIL;
-}
-
-/****************************
- *    Mutex
- ****************************/
-
-static void drv_mutex_init(IxOsalMutex *mutex)
-{
-	*mutex = 0;
-}
-
-static void drv_mutex_destroy(IxOsalMutex *mutex)
-{
-	*mutex = -1;
-}
-
-static int drv_mutex_trylock(IxOsalMutex *mutex)
-{
-	int result = true;
-
-	if (*mutex == 1)
-		result = false;
-
-	return result;
-}
-
-static void drv_mutex_unlock(IxOsalMutex *mutex)
-{
-	if (*mutex == 1)
-		printf("Trying to unlock unlocked mutex!");
-
-	*mutex = 0;
-}
-
-PUBLIC IX_STATUS
-ixOsalMutexInit (IxOsalMutex * mutex)
-{
-    drv_mutex_init(mutex);
-    return IX_SUCCESS;
-}
-
-PUBLIC IX_STATUS
-ixOsalMutexLock (IxOsalMutex * mutex, INT32 timeout)
-{
-    int tries;
-
-    if (timeout == IX_OSAL_WAIT_NONE) {
-	if (drv_mutex_trylock(mutex))
-	    return IX_SUCCESS;
-	else
-	    return IX_FAIL;
-    }
-
-    tries = (timeout * 1000) / 50;
-    while (1) {
-	if (drv_mutex_trylock(mutex))
-	    return IX_SUCCESS;
-	if (timeout != IX_OSAL_WAIT_FOREVER && tries-- <= 0)
-	    break;
-	udelay(50);
-    }
-    return IX_FAIL;
-}
-
-PUBLIC IX_STATUS
-ixOsalMutexUnlock (IxOsalMutex * mutex)
-{
-    drv_mutex_unlock(mutex);
-    return IX_SUCCESS;
-}
-
-/*
- * Attempt to get mutex, return immediately,
- * no error info because users expect some failures
- * when using this API.
- */
-PUBLIC IX_STATUS
-ixOsalMutexTryLock (IxOsalMutex * mutex)
-{
-    if (drv_mutex_trylock(mutex))
-	return IX_SUCCESS;
-    return IX_FAIL;
-}
-
-PUBLIC IX_STATUS
-ixOsalMutexDestroy (IxOsalMutex * mutex)
-{
-    drv_mutex_destroy(mutex);
-    return IX_SUCCESS;
-}
-
-PUBLIC IX_STATUS
-ixOsalFastMutexInit (IxOsalFastMutex * mutex)
-{
-    return ixOsalMutexInit(mutex);
-}
-
-PUBLIC IX_STATUS ixOsalFastMutexTryLock(IxOsalFastMutex *mutex)
-{
-    return ixOsalMutexTryLock(mutex);
-}
-
-
-PUBLIC IX_STATUS
-ixOsalFastMutexUnlock (IxOsalFastMutex * mutex)
-{
-    return ixOsalMutexUnlock(mutex);
-}
-
-PUBLIC IX_STATUS
-ixOsalFastMutexDestroy (IxOsalFastMutex * mutex)
-{
-    return ixOsalMutexDestroy(mutex);
-}
diff --git a/drivers/net/npe/IxOsalOsServices.c b/drivers/net/npe/IxOsalOsServices.c
deleted file mode 100644
index a9aa36804b..0000000000
--- a/drivers/net/npe/IxOsalOsServices.c
+++ /dev/null
@@ -1,227 +0,0 @@
-/**
- * @file IxOsalOsServices.c (linux)
- *
- * @brief Implementation for Irq, Mem, sleep.
- *
- *
- * @par
- * IXP400 SW Release version 1.5
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * SPDX-License-Identifier:	BSD-3-Clause
- * @par
- * -- End of Copyright Notice --
- */
-
-#include <config.h>
-#include <common.h>
-#include "IxOsal.h"
-#include <IxEthAcc.h>
-#include <IxEthDB.h>
-#include <IxNpeDl.h>
-#include <IxQMgr.h>
-#include <IxNpeMh.h>
-
-static char *traceHeaders[] = {
-    "",
-    "[fatal] ",
-    "[error] ",
-    "[warning] ",
-    "[message] ",
-    "[debug1] ",
-    "[debug2] ",
-    "[debug3] ",
-    "[all]"
-};
-
-/* by default trace all but debug message */
-PRIVATE int ixOsalCurrLogLevel = IX_OSAL_LOG_LVL_MESSAGE;
-
-/**************************************
- * Irq services
- *************************************/
-
-PUBLIC IX_STATUS
-ixOsalIrqBind (UINT32 vector, IxOsalVoidFnVoidPtr routine, void *parameter)
-{
-    return IX_FAIL;
-}
-
-PUBLIC IX_STATUS
-ixOsalIrqUnbind (UINT32 vector)
-{
-    return IX_FAIL;
-}
-
-PUBLIC UINT32
-ixOsalIrqLock ()
-{
-    return 0;
-}
-
-/* Enable interrupts and task scheduling,
- * input parameter: irqEnable status returned
- * by ixOsalIrqLock().
- */
-PUBLIC void
-ixOsalIrqUnlock (UINT32 lockKey)
-{
-}
-
-PUBLIC UINT32
-ixOsalIrqLevelSet (UINT32 level)
-{
-    return IX_FAIL;
-}
-
-PUBLIC void
-ixOsalIrqEnable (UINT32 irqLevel)
-{
-}
-
-PUBLIC void
-ixOsalIrqDisable (UINT32 irqLevel)
-{
-}
-
-/*********************
- * Log function
- *********************/
-
-INT32
-ixOsalLog (IxOsalLogLevel level,
-    IxOsalLogDevice device,
-    char *format, int arg1, int arg2, int arg3, int arg4, int arg5, int arg6)
-{
-    /*
-     * Return -1 for custom display devices
-     */
-    if ((device != IX_OSAL_LOG_DEV_STDOUT)
-        && (device != IX_OSAL_LOG_DEV_STDERR))
-    {
-        debug("ixOsalLog: only IX_OSAL_LOG_DEV_STDOUT and IX_OSAL_LOG_DEV_STDERR are supported \n");
-        return (IX_OSAL_LOG_ERROR);
-    }
-
-    if (level <= ixOsalCurrLogLevel && level != IX_OSAL_LOG_LVL_NONE)
-    {
-#if 0 /* sr: U-Boots printf or debug doesn't return a length */
-        int headerByteCount = (level == IX_OSAL_LOG_LVL_USER) ? 0 : diag_printf(traceHeaders[level - 1]);
-
-        return headerByteCount + diag_printf (format, arg1, arg2, arg3, arg4, arg5, arg6);
-#else
-        int headerByteCount = (level == IX_OSAL_LOG_LVL_USER) ? 0 : strlen(traceHeaders[level - 1]);
-
-        return headerByteCount + strlen(format);
-#endif
-    }
-    else
-    {
-        /*
-         * Return error
-         */
-        return (IX_OSAL_LOG_ERROR);
-    }
-}
-
-PUBLIC UINT32
-ixOsalLogLevelSet (UINT32 level)
-{
-    UINT32 oldLevel;
-
-    /*
-     * Check value first
-     */
-    if ((level < IX_OSAL_LOG_LVL_NONE) || (level > IX_OSAL_LOG_LVL_ALL))
-    {
-        ixOsalLog (IX_OSAL_LOG_LVL_MESSAGE,
-            IX_OSAL_LOG_DEV_STDOUT,
-            "ixOsalLogLevelSet: Log Level is between %d and%d \n",
-            IX_OSAL_LOG_LVL_NONE, IX_OSAL_LOG_LVL_ALL, 0, 0, 0, 0);
-        return IX_OSAL_LOG_LVL_NONE;
-    }
-    oldLevel = ixOsalCurrLogLevel;
-
-    ixOsalCurrLogLevel = level;
-
-    return oldLevel;
-}
-
-/**************************************
- * Task services
- *************************************/
-
-PUBLIC void
-ixOsalBusySleep (UINT32 microseconds)
-{
-	udelay(microseconds);
-}
-
-PUBLIC void
-ixOsalSleep (UINT32 milliseconds)
-{
-    if (milliseconds != 0) {
-#if 1
-	/*
-	 * sr: We poll while we wait because interrupts are off in U-Boot
-	 * and CSR expects messages, etc to be dispatched while sleeping.
-	 */
-	int i;
-	IxQMgrDispatcherFuncPtr qDispatcherFunc;
-
-	ixQMgrDispatcherLoopGet(&qDispatcherFunc);
-
-	while (milliseconds--) {
-		for (i = 1; i <= 2; i++)
-			ixNpeMhMessagesReceive(i);
-		(*qDispatcherFunc)(IX_QMGR_QUELOW_GROUP);
-
-		udelay(1000);
-	}
-#endif
-    }
-}
-
-/**************************************
- * Memory functions
- *************************************/
-
-void *
-ixOsalMemAlloc (UINT32 size)
-{
-    return (void *)0;
-}
-
-void
-ixOsalMemFree (void *ptr)
-{
-}
-
-/*
- * Copy count bytes from src to dest ,
- * returns pointer to the dest mem zone.
- */
-void *
-ixOsalMemCopy (void *dest, void *src, UINT32 count)
-{
-    IX_OSAL_ASSERT (dest != NULL);
-    IX_OSAL_ASSERT (src != NULL);
-    return (memcpy (dest, src, count));
-}
-
-/*
- * Fills a memory zone with a given constant byte,
- * returns pointer to the memory zone.
- */
-void *
-ixOsalMemSet (void *ptr, UINT8 filler, UINT32 count)
-{
-    IX_OSAL_ASSERT (ptr != NULL);
-    return (memset (ptr, filler, count));
-}
diff --git a/drivers/net/npe/IxOsalOsThread.c b/drivers/net/npe/IxOsalOsThread.c
deleted file mode 100644
index b3caae19b1..0000000000
--- a/drivers/net/npe/IxOsalOsThread.c
+++ /dev/null
@@ -1,74 +0,0 @@
-/**
- * @file IxOsalOsThread.c (eCos)
- *
- * @brief OS-specific thread implementation.
- *
- *
- * @par
- * IXP400 SW Release version 1.5
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * SPDX-License-Identifier:	BSD-3-Clause
- * @par
- * -- End of Copyright Notice --
- */
-
-#include "IxOsal.h"
-
-/* Thread attribute is ignored */
-PUBLIC IX_STATUS
-ixOsalThreadCreate (IxOsalThread * ptrTid,
-    IxOsalThreadAttr * threadAttr, IxOsalVoidFnVoidPtr entryPoint, void *arg)
-{
-    return IX_SUCCESS;
-}
-
-/*
- * Start thread after given its thread handle
- */
-PUBLIC IX_STATUS
-ixOsalThreadStart (IxOsalThread * tId)
-{
-    /* Thread already started upon creation */
-    return IX_SUCCESS;
-}
-
-/*
- * In Linux threadKill does not actually destroy the thread,
- * it will stop the signal handling.
- */
-PUBLIC IX_STATUS
-ixOsalThreadKill (IxOsalThread * tid)
-{
-    return IX_SUCCESS;
-}
-
-PUBLIC void
-ixOsalThreadExit (void)
-{
-}
-
-PUBLIC IX_STATUS
-ixOsalThreadPrioritySet (IxOsalOsThread * tid, UINT32 priority)
-{
-    return IX_SUCCESS;
-}
-
-PUBLIC IX_STATUS
-ixOsalThreadSuspend (IxOsalThread * tId)
-{
-    return IX_SUCCESS;
-
-}
-
-PUBLIC IX_STATUS
-ixOsalThreadResume (IxOsalThread * tId)
-{
-    return IX_SUCCESS;
-}
diff --git a/drivers/net/npe/IxQMgrAqmIf.c b/drivers/net/npe/IxQMgrAqmIf.c
deleted file mode 100644
index 69138ccded..0000000000
--- a/drivers/net/npe/IxQMgrAqmIf.c
+++ /dev/null
@@ -1,939 +0,0 @@
-/* 
- * @file:    IxQMgrAqmIf.c
- *
- * @author Intel Corporation
- * @date     30-Oct-2001
- *
- * @brief    This component provides a set of functions for
- * perfoming I/O on the AQM hardware.
- * 
- * Design Notes: 
- *              These functions are intended to be as fast as possible
- * and as a result perform NO PARAMETER CHECKING.
- *
- * 
- * @par
- * IXP400 SW Release version 2.0
- * 
- * -- Copyright Notice --
- * 
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * SPDX-License-Identifier:	BSD-3-Clause
- * @par
- * -- End of Copyright Notice --
-*/
-
-/*
- * Inlines are compiled as function when this is defined.
- * N.B. Must be placed before #include of "IxQMgrAqmIf_p.h
- */
-#ifndef IXQMGRAQMIF_P_H
-#    define IXQMGRAQMIF_C
-#else
-#    error
-#endif
-
-/*
- * User defined include files.
- */
-#include "IxOsal.h"
-#include "IxQMgr.h"
-#include "IxQMgrAqmIf_p.h"
-#include "IxQMgrLog_p.h"
-
-
-/*
- * #defines and macros used in this file.
- */
-
-/* These defines are the bit offsets of the various fields of
- * the queue configuration register
- */
-#define IX_QMGR_Q_CONFIG_WRPTR_OFFSET       0x00
-#define IX_QMGR_Q_CONFIG_RDPTR_OFFSET       0x07
-#define IX_QMGR_Q_CONFIG_BADDR_OFFSET       0x0E
-#define IX_QMGR_Q_CONFIG_ESIZE_OFFSET       0x16
-#define IX_QMGR_Q_CONFIG_BSIZE_OFFSET       0x18
-#define IX_QMGR_Q_CONFIG_NE_OFFSET          0x1A
-#define IX_QMGR_Q_CONFIG_NF_OFFSET          0x1D
-
-#define IX_QMGR_BASE_ADDR_16_WORD_ALIGN     0x40
-#define IX_QMGR_BASE_ADDR_16_WORD_SHIFT     0x6
-
-#define IX_QMGR_NE_NF_CLEAR_MASK            0x03FFFFFF
-#define IX_QMGR_NE_MASK                     0x7
-#define IX_QMGR_NF_MASK                     0x7
-#define IX_QMGR_SIZE_MASK                   0x3
-#define IX_QMGR_ENTRY_SIZE_MASK             0x3
-#define IX_QMGR_BADDR_MASK                  0x003FC000
-#define IX_QMGR_RDPTR_MASK                  0x7F
-#define IX_QMGR_WRPTR_MASK                  0x7F
-#define IX_QMGR_RDWRPTR_MASK                0x00003FFF
-
-#define IX_QMGR_AQM_ADDRESS_SPACE_SIZE_IN_WORDS 0x1000
-
-/* Base address of AQM SRAM */
-#define IX_QMGR_AQM_SRAM_BASE_ADDRESS_OFFSET \
-((IX_QMGR_QUECONFIG_BASE_OFFSET) + (IX_QMGR_QUECONFIG_SIZE))
-
-/* Min buffer size used for generating buffer size in QUECONFIG */
-#define IX_QMGR_MIN_BUFFER_SIZE 16
-
-/* Reset values of QMgr hardware registers */
-#define IX_QMGR_QUELOWSTAT_RESET_VALUE    0x33333333
-#define IX_QMGR_QUEUOSTAT_RESET_VALUE     0x00000000
-#define IX_QMGR_QUEUPPSTAT0_RESET_VALUE   0xFFFFFFFF
-#define IX_QMGR_QUEUPPSTAT1_RESET_VALUE   0x00000000
-#define IX_QMGR_INT0SRCSELREG_RESET_VALUE 0x00000000
-#define IX_QMGR_QUEIEREG_RESET_VALUE      0x00000000
-#define IX_QMGR_QINTREG_RESET_VALUE       0xFFFFFFFF
-#define IX_QMGR_QUECONFIG_RESET_VALUE     0x00000000
-
-#define IX_QMGR_PHYSICAL_AQM_BASE_ADDRESS IX_OSAL_IXP400_QMGR_PHYS_BASE
-
-#define IX_QMGR_QUELOWSTAT_BITS_PER_Q (BITS_PER_WORD/IX_QMGR_QUELOWSTAT_NUM_QUE_PER_WORD)
-
-#define IX_QMGR_QUELOWSTAT_QID_MASK 0x7
-#define IX_QMGR_Q_CONFIG_ADDR_GET(qId)\
-        (((qId) * IX_QMGR_NUM_BYTES_PER_WORD) +\
-                  IX_QMGR_QUECONFIG_BASE_OFFSET)
-
-#define IX_QMGR_ENTRY1_OFFSET 0
-#define IX_QMGR_ENTRY2_OFFSET 1
-#define IX_QMGR_ENTRY4_OFFSET 3
-
-/*
- * Variable declarations global to this file. Externs are followed by
- * statics.
- */
-UINT32 aqmBaseAddress = 0;
-/* Store addresses and bit-masks for certain queue access and status registers.
- * This is to facilitate inlining of QRead, QWrite and QStatusGet functions
- * in IxQMgr,h
- */
-extern IxQMgrQInlinedReadWriteInfo ixQMgrQInlinedReadWriteInfo[];
-UINT32 * ixQMgrAqmIfQueAccRegAddr[IX_QMGR_MAX_NUM_QUEUES];
-UINT32 ixQMgrAqmIfQueLowStatRegAddr[IX_QMGR_MIN_QUEUPP_QID];
-UINT32 ixQMgrAqmIfQueLowStatBitsOffset[IX_QMGR_MIN_QUEUPP_QID];
-UINT32 ixQMgrAqmIfQueLowStatBitsMask;
-UINT32 ixQMgrAqmIfQueUppStat0RegAddr;
-UINT32 ixQMgrAqmIfQueUppStat1RegAddr;
-UINT32 ixQMgrAqmIfQueUppStat0BitMask[IX_QMGR_MIN_QUEUPP_QID];
-UINT32 ixQMgrAqmIfQueUppStat1BitMask[IX_QMGR_MIN_QUEUPP_QID];
-
-/* 
- * Fast mutexes, one for each queue, used to protect peek & poke functions
- */
-IxOsalFastMutex ixQMgrAqmIfPeekPokeFastMutex[IX_QMGR_MAX_NUM_QUEUES];
-
-/*
- * Function prototypes
- */
-PRIVATE unsigned
-watermarkToAqmWatermark (IxQMgrWMLevel watermark );
-
-PRIVATE unsigned
-entrySizeToAqmEntrySize (IxQMgrQEntrySizeInWords entrySize);
-
-PRIVATE unsigned
-bufferSizeToAqmBufferSize (unsigned bufferSizeInWords);
-
-PRIVATE void
-ixQMgrAqmIfRegistersReset (void);
-
-PRIVATE void
-ixQMgrAqmIfEntryAddressGet (unsigned int entryIndex,
-			    UINT32 configRegWord,
-			    unsigned int qEntrySizeInwords,
-			    unsigned int qSizeInWords,
-			    UINT32 **address);
-/*
- * Function definitions
- */
-void
-ixQMgrAqmIfInit (void)
-{
-    UINT32 aqmVirtualAddr;
-    int i;
-
-    /* The value of aqmBaseAddress depends on the logical address
-     * assigned by the MMU.
-     */
-    aqmVirtualAddr =
-	(UINT32) IX_OSAL_MEM_MAP(IX_QMGR_PHYSICAL_AQM_BASE_ADDRESS,
-				    IX_OSAL_IXP400_QMGR_MAP_SIZE);
-    IX_OSAL_ASSERT (aqmVirtualAddr);
-    
-    ixQMgrAqmIfBaseAddressSet (aqmVirtualAddr);
-
-    ixQMgrAqmIfRegistersReset ();
-
-    for (i = 0; i< IX_QMGR_MAX_NUM_QUEUES; i++)
-    {
-	ixOsalFastMutexInit(&ixQMgrAqmIfPeekPokeFastMutex[i]);
-
-	/********************************************************************
-	 * Register addresses and bit masks are calculated and stored here to
-	 * facilitate inlining of QRead, QWrite and QStatusGet functions in
-	 * IxQMgr.h.
-	 * These calculations are normally performed dynamically in inlined
-	 * functions in IxQMgrAqmIf_p.h, and their semantics are reused here.
-	 */
-
-	/* AQM Queue access reg addresses, per queue */
-	ixQMgrAqmIfQueAccRegAddr[i] = 
-	    (UINT32 *)(aqmBaseAddress + IX_QMGR_Q_ACCESS_ADDR_GET(i));
-	ixQMgrQInlinedReadWriteInfo[i].qAccRegAddr = 
-	    (volatile UINT32 *)(aqmBaseAddress + IX_QMGR_Q_ACCESS_ADDR_GET(i));
-
-
-	ixQMgrQInlinedReadWriteInfo[i].qConfigRegAddr = 
-	    (volatile UINT32 *)(aqmBaseAddress + IX_QMGR_Q_CONFIG_ADDR_GET(i));
-
-	/* AQM Queue lower-group (0-31), only */
-	if (i < IX_QMGR_MIN_QUEUPP_QID)
-	{
-	    /* AQM Q underflow/overflow status register addresses, per queue */
-	    ixQMgrQInlinedReadWriteInfo[i].qUOStatRegAddr = 
-		(volatile UINT32 *)(aqmBaseAddress +
-		IX_QMGR_QUEUOSTAT0_OFFSET +
-		((i / IX_QMGR_QUEUOSTAT_NUM_QUE_PER_WORD) *
-		 IX_QMGR_NUM_BYTES_PER_WORD));
-
-	    /* AQM Q underflow status bit masks for status register per queue */
-	    ixQMgrQInlinedReadWriteInfo[i].qUflowStatBitMask = 
-		(IX_QMGR_UNDERFLOW_BIT_OFFSET + 1) <<
-		((i & (IX_QMGR_QUEUOSTAT_NUM_QUE_PER_WORD - 1)) *
-		 (BITS_PER_WORD / IX_QMGR_QUEUOSTAT_NUM_QUE_PER_WORD));
-
-	    /* AQM Q overflow status bit masks for status register, per queue */
-	    ixQMgrQInlinedReadWriteInfo[i].qOflowStatBitMask = 
-		(IX_QMGR_OVERFLOW_BIT_OFFSET + 1) <<
-		((i & (IX_QMGR_QUEUOSTAT_NUM_QUE_PER_WORD - 1)) *
-		 (BITS_PER_WORD / IX_QMGR_QUEUOSTAT_NUM_QUE_PER_WORD));
-
-	    /* AQM Q lower-group (0-31) status register addresses, per queue */
-	    ixQMgrAqmIfQueLowStatRegAddr[i] = aqmBaseAddress +
-		IX_QMGR_QUELOWSTAT0_OFFSET +
-		((i / IX_QMGR_QUELOWSTAT_NUM_QUE_PER_WORD) *
-		 IX_QMGR_NUM_BYTES_PER_WORD);
-
-	    /* AQM Q lower-group (0-31) status register bit offset */
-	    ixQMgrAqmIfQueLowStatBitsOffset[i] =
-		(i & (IX_QMGR_QUELOWSTAT_NUM_QUE_PER_WORD - 1)) * 
-		(BITS_PER_WORD / IX_QMGR_QUELOWSTAT_NUM_QUE_PER_WORD);
-	}
-	else /* AQM Q upper-group (32-63), only */
-	{
-	    /* AQM Q upper-group (32-63) Nearly Empty status reg bit masks */
-	    ixQMgrAqmIfQueUppStat0BitMask[i - IX_QMGR_MIN_QUEUPP_QID] =
-		(1 << (i - IX_QMGR_MIN_QUEUPP_QID));
-
-	    /* AQM Q upper-group (32-63) Full status register bit masks */
-	    ixQMgrAqmIfQueUppStat1BitMask[i - IX_QMGR_MIN_QUEUPP_QID] =
-		(1 << (i - IX_QMGR_MIN_QUEUPP_QID));
-	}
-    }
-
-    /* AQM Q lower-group (0-31) status register bit mask */
-    ixQMgrAqmIfQueLowStatBitsMask = (1 <<
-				    (BITS_PER_WORD /
-				     IX_QMGR_QUELOWSTAT_NUM_QUE_PER_WORD)) - 1;
-
-    /* AQM Q upper-group (32-63) Nearly Empty status register address */
-    ixQMgrAqmIfQueUppStat0RegAddr = aqmBaseAddress + IX_QMGR_QUEUPPSTAT0_OFFSET;
-    
-    /* AQM Q upper-group (32-63) Full status register address */
-    ixQMgrAqmIfQueUppStat1RegAddr = aqmBaseAddress + IX_QMGR_QUEUPPSTAT1_OFFSET;
-}
-
-/*
- * Uninitialise the AqmIf module by unmapping memory, etc
- */
-void
-ixQMgrAqmIfUninit (void)
-{
-    UINT32 virtAddr;
-
-    ixQMgrAqmIfBaseAddressGet (&virtAddr);
-    IX_OSAL_MEM_UNMAP (virtAddr);
-    ixQMgrAqmIfBaseAddressSet (0);
-}
-
-/*
- * Set the the logical base address of AQM
- */
-void
-ixQMgrAqmIfBaseAddressSet (UINT32 address)
-{
-    aqmBaseAddress = address;
-}
-
-/*
- * Get the logical base address of AQM
- */
-void
-ixQMgrAqmIfBaseAddressGet (UINT32 *address)
-{
-    *address = aqmBaseAddress;
-}
-
-/*
- * Get the logical base address of AQM SRAM
- */
-void
-ixQMgrAqmIfSramBaseAddressGet (UINT32 *address)
-{
-    *address = aqmBaseAddress                +
-	IX_QMGR_AQM_SRAM_BASE_ADDRESS_OFFSET;
-}
-
-/*
- * This function will write the status bits of a queue
- * specified by qId.
- */
-void
-ixQMgrAqmIfQRegisterBitsWrite (IxQMgrQId qId, 
-			       UINT32 registerBaseAddrOffset,
-			       unsigned queuesPerRegWord,
-			       UINT32 value)
-{
-    volatile UINT32 *registerAddress;
-    UINT32 registerWord;
-    UINT32 statusBitsMask;
-    UINT32 bitsPerQueue;
-
-    bitsPerQueue = BITS_PER_WORD / queuesPerRegWord;
-
-    /*
-     * Calculate the registerAddress
-     * multiple queues split accross registers
-     */
-    registerAddress = (UINT32*)(aqmBaseAddress +
-				registerBaseAddrOffset +
-				((qId / queuesPerRegWord) *
-				 IX_QMGR_NUM_BYTES_PER_WORD));    
-
-    /* Read the current data */
-    ixQMgrAqmIfWordRead (registerAddress, &registerWord);
-
-
-    if( (registerBaseAddrOffset == IX_QMGR_INT0SRCSELREG0_OFFSET) &&
-        (qId == IX_QMGR_QUEUE_0) )
-    {
-      statusBitsMask = 0x7 ;   
-
-      /* Queue 0 at INT0SRCSELREG should not corrupt the value bit-3  */
-      value &=  0x7 ;        
-    }
-    else
-    {     
-      /* Calculate the mask for the status bits for this queue. */
-      statusBitsMask = ((1 << bitsPerQueue) - 1);
-      statusBitsMask <<= ((qId & (queuesPerRegWord - 1)) * bitsPerQueue);
-
-      /* Mask out bits in value that would overwrite other q data */
-      value <<= ((qId & (queuesPerRegWord - 1)) * bitsPerQueue);
-      value &= statusBitsMask;
-    }
-
-    /* Mask out bits to write to */
-    registerWord &= ~statusBitsMask;
-    
-
-    /* Set the write bits */
-    registerWord |= value;
-
-    /*
-     * Write the data
-     */
-    ixQMgrAqmIfWordWrite (registerAddress, registerWord);
-}
-
-/*
- * This function generates the parameters that can be used to
- * check if a Qs status matches the specified source select.
- * It calculates which status word to check (statusWordOffset),
- * the value to check the status against (checkValue) and the
- * mask (mask) to mask out all but the bits to check in the status word.
- */
-void
-ixQMgrAqmIfQStatusCheckValsCalc (IxQMgrQId qId,
-				 IxQMgrSourceId srcSel,
-				 unsigned int *statusWordOffset,
-				 UINT32 *checkValue,
-				 UINT32 *mask)
-{
-    UINT32 shiftVal;
-   
-    if (qId < IX_QMGR_MIN_QUEUPP_QID)
-    {
-	switch (srcSel)
-	{
-	    case IX_QMGR_Q_SOURCE_ID_E:
-		*checkValue = IX_QMGR_Q_STATUS_E_BIT_MASK;
-		*mask = IX_QMGR_Q_STATUS_E_BIT_MASK;
-		break;
-	    case IX_QMGR_Q_SOURCE_ID_NE:
-		*checkValue = IX_QMGR_Q_STATUS_NE_BIT_MASK;
-		*mask = IX_QMGR_Q_STATUS_NE_BIT_MASK;
-		break;
-	    case IX_QMGR_Q_SOURCE_ID_NF:
-		*checkValue = IX_QMGR_Q_STATUS_NF_BIT_MASK;
-		*mask = IX_QMGR_Q_STATUS_NF_BIT_MASK;
-		break;
-	    case IX_QMGR_Q_SOURCE_ID_F:
-		*checkValue = IX_QMGR_Q_STATUS_F_BIT_MASK;
-		*mask = IX_QMGR_Q_STATUS_F_BIT_MASK;
-		break;
-	    case IX_QMGR_Q_SOURCE_ID_NOT_E:
-		*checkValue = 0;
-		*mask = IX_QMGR_Q_STATUS_E_BIT_MASK;
-		break;
-	    case IX_QMGR_Q_SOURCE_ID_NOT_NE:
-		*checkValue = 0;
-		*mask = IX_QMGR_Q_STATUS_NE_BIT_MASK;
-		break;
-	    case IX_QMGR_Q_SOURCE_ID_NOT_NF:
-		*checkValue = 0;
-		*mask = IX_QMGR_Q_STATUS_NF_BIT_MASK;
-		break;
-	    case IX_QMGR_Q_SOURCE_ID_NOT_F:
-		*checkValue = 0;
-		*mask = IX_QMGR_Q_STATUS_F_BIT_MASK;
-		break;
-	    default:
-		/* Should never hit */
-		IX_OSAL_ASSERT(0);
-		break;
-	}
-
-	/* One nibble of status per queue so need to shift the
-	 * check value and mask out to the correct position.
-	 */
-	shiftVal = (qId % IX_QMGR_QUELOWSTAT_NUM_QUE_PER_WORD) * 
-	    IX_QMGR_QUELOWSTAT_BITS_PER_Q;
-
-	/* Calculate the which status word to check from the qId,
-	 * 8 Qs status per word
-	 */
-	*statusWordOffset = qId / IX_QMGR_QUELOWSTAT_NUM_QUE_PER_WORD;
-
-	*checkValue <<= shiftVal;
-	*mask <<= shiftVal;
-    }
-    else
-    {
-	/* One status word */
-	*statusWordOffset = 0;
-	/* Single bits per queue and int source bit hardwired  NE,
-	 * Qs start at 32.
-	 */
-	*mask = 1 << (qId - IX_QMGR_MIN_QUEUPP_QID);
-	*checkValue = *mask;
-    }
-}
-
-void
-ixQMgrAqmIfQInterruptEnable (IxQMgrQId qId)
-{
-    volatile UINT32 *registerAddress;
-    UINT32 registerWord;
-    UINT32 actualBitOffset;
-    
-    if (qId < IX_QMGR_MIN_QUEUPP_QID)
-    {    
-	registerAddress = (UINT32*)(aqmBaseAddress + IX_QMGR_QUEIEREG0_OFFSET);
-    }
-    else
-    {
-	registerAddress = (UINT32*)(aqmBaseAddress + IX_QMGR_QUEIEREG1_OFFSET);
-    }
-
-    actualBitOffset = 1 << (qId % IX_QMGR_MIN_QUEUPP_QID);
-
-    ixQMgrAqmIfWordRead (registerAddress, &registerWord);
-    ixQMgrAqmIfWordWrite (registerAddress, (registerWord | actualBitOffset));
-}
-
-void
-ixQMgrAqmIfQInterruptDisable (IxQMgrQId qId)
-{
-    volatile UINT32 *registerAddress;
-    UINT32 registerWord;
-    UINT32 actualBitOffset;
-
-    if (qId < IX_QMGR_MIN_QUEUPP_QID)
-    {    
-	registerAddress = (UINT32*)(aqmBaseAddress + IX_QMGR_QUEIEREG0_OFFSET);
-    }
-    else
-    {
-	registerAddress = (UINT32*)(aqmBaseAddress + IX_QMGR_QUEIEREG1_OFFSET);
-    }
-
-    actualBitOffset = 1 << (qId % IX_QMGR_MIN_QUEUPP_QID);
-
-    ixQMgrAqmIfWordRead (registerAddress, &registerWord);
-    ixQMgrAqmIfWordWrite (registerAddress, registerWord & (~actualBitOffset));
-}
-
-void
-ixQMgrAqmIfQueCfgWrite (IxQMgrQId qId,
-		       IxQMgrQSizeInWords qSizeInWords,
-		       IxQMgrQEntrySizeInWords entrySizeInWords,
-		       UINT32 freeSRAMAddress)
-{
-    volatile UINT32 *cfgAddress = NULL;
-    UINT32 qCfg = 0;
-    UINT32 baseAddress = 0;
-    unsigned aqmEntrySize = 0;
-    unsigned aqmBufferSize = 0;
-
-    /* Build config register */
-    aqmEntrySize = entrySizeToAqmEntrySize (entrySizeInWords);
-    qCfg |= (aqmEntrySize&IX_QMGR_ENTRY_SIZE_MASK) <<
-	IX_QMGR_Q_CONFIG_ESIZE_OFFSET;
-
-    aqmBufferSize = bufferSizeToAqmBufferSize (qSizeInWords);
-    qCfg |= (aqmBufferSize&IX_QMGR_SIZE_MASK) << IX_QMGR_Q_CONFIG_BSIZE_OFFSET;
-
-    /* baseAddress, calculated relative to aqmBaseAddress and start address  */
-    baseAddress = freeSRAMAddress -
-	(aqmBaseAddress + IX_QMGR_QUECONFIG_BASE_OFFSET);
-		   
-    /* Verify base address aligned to a 16 word boundary */
-    if ((baseAddress % IX_QMGR_BASE_ADDR_16_WORD_ALIGN) != 0)
-    {
-	IX_QMGR_LOG_ERROR0("ixQMgrAqmIfQueCfgWrite () address is not on 16 word boundary\n");
-    }
-    /* Now convert it to a 16 word pointer as required by QUECONFIG register */
-    baseAddress >>= IX_QMGR_BASE_ADDR_16_WORD_SHIFT;
-    
-    
-    qCfg |= (baseAddress << IX_QMGR_Q_CONFIG_BADDR_OFFSET);
-
-
-    cfgAddress = (UINT32*)(aqmBaseAddress +
-			IX_QMGR_Q_CONFIG_ADDR_GET(qId));
-
-
-    /* NOTE: High and Low watermarks are set to zero */
-    ixQMgrAqmIfWordWrite (cfgAddress, qCfg);
-}
-
-void
-ixQMgrAqmIfQueCfgRead (IxQMgrQId qId,
-		       unsigned int numEntries,
-		       UINT32 *baseAddress,
-		       unsigned int *ne,
-		       unsigned int *nf,
-		       UINT32 *readPtr,
-		       UINT32 *writePtr)
-{
-    UINT32 qcfg;
-    UINT32 *cfgAddress = (UINT32*)(aqmBaseAddress + IX_QMGR_Q_CONFIG_ADDR_GET(qId));
-    unsigned int qEntrySizeInwords;
-    unsigned int qSizeInWords;
-    UINT32 *readPtr_ = NULL;
-	
-    /* Read the queue configuration register */
-    ixQMgrAqmIfWordRead (cfgAddress, &qcfg);
-    
-    /* Extract the base address */
-    *baseAddress = (UINT32)((qcfg & IX_QMGR_BADDR_MASK) >>
-			    (IX_QMGR_Q_CONFIG_BADDR_OFFSET));
-
-    /* Base address is a 16 word pointer from the start of AQM SRAM.
-     * Convert to absolute word address.
-     */
-    *baseAddress <<= IX_QMGR_BASE_ADDR_16_WORD_SHIFT;
-    *baseAddress += (UINT32)IX_QMGR_QUECONFIG_BASE_OFFSET;
-
-    /*
-     * Extract the watermarks. 0->0 entries, 1->1 entries, 2->2 entries, 3->4 entries......
-     * If ne > 0 ==> neInEntries = 2^(ne - 1)
-     * If ne == 0 ==> neInEntries = 0
-     * The same applies.
-     */
-    *ne = ((qcfg) >> (IX_QMGR_Q_CONFIG_NE_OFFSET)) & IX_QMGR_NE_MASK;
-    *nf = ((qcfg) >> (IX_QMGR_Q_CONFIG_NF_OFFSET)) & IX_QMGR_NF_MASK;
-
-    if (0 != *ne)
-    {
-	*ne = 1 << (*ne - 1);	
-    }
-    if (0 != *nf)
-    {
-	*nf = 1 << (*nf - 1);
-    }
-
-    /* Get the queue entry size in words */
-    qEntrySizeInwords = ixQMgrQEntrySizeInWordsGet (qId);
-
-    /* Get the queue size in words */
-    qSizeInWords = ixQMgrQSizeInWordsGet (qId);
-
-    ixQMgrAqmIfEntryAddressGet (0/* Entry 0. i.e the readPtr*/,
-				qcfg,
-				qEntrySizeInwords,
-				qSizeInWords,
-				&readPtr_);
-    *readPtr = (UINT32)readPtr_;
-    *readPtr -= (UINT32)aqmBaseAddress;/* Offset, not absolute address */
-
-    *writePtr = (qcfg >> IX_QMGR_Q_CONFIG_WRPTR_OFFSET) & IX_QMGR_WRPTR_MASK;
-    *writePtr = *baseAddress + (*writePtr * (IX_QMGR_NUM_BYTES_PER_WORD));
-    return;
-}
-
-unsigned
-ixQMgrAqmIfLog2 (unsigned number)
-{
-    unsigned count = 0;
-
-    /*
-     * N.B. this function will return 0
-     * for ixQMgrAqmIfLog2 (0)
-     */
-    while (number/2)
-    {
-	number /=2;
-	count++;	
-    }
-
-    return count;
-}
-
-void ixQMgrAqmIfIntSrcSelReg0Bit3Set (void)
-{
-
-    volatile UINT32 *registerAddress;
-    UINT32 registerWord; 
-
-    /*
-     * Calculate the registerAddress
-     * multiple queues split accross registers
-     */
-    registerAddress = (UINT32*)(aqmBaseAddress +
-				IX_QMGR_INT0SRCSELREG0_OFFSET);    
-
-    /* Read the current data */
-    ixQMgrAqmIfWordRead (registerAddress, &registerWord);
-
-    /* Set the write bits */
-    registerWord |= (1<<IX_QMGR_INT0SRCSELREG0_BIT3) ;
-
-    /*
-     * Write the data
-     */
-    ixQMgrAqmIfWordWrite (registerAddress, registerWord);
-}  
-
-
-void
-ixQMgrAqmIfIntSrcSelWrite (IxQMgrQId qId,
-			  IxQMgrSourceId sourceId)
-{
-    ixQMgrAqmIfQRegisterBitsWrite (qId,
-				   IX_QMGR_INT0SRCSELREG0_OFFSET,
-				   IX_QMGR_INTSRC_NUM_QUE_PER_WORD,
-				   sourceId);
-}
-
-
-
-void
-ixQMgrAqmIfWatermarkSet (IxQMgrQId qId,
-			unsigned ne,
-			unsigned nf)
-{
-    volatile UINT32 *address = 0;
-    UINT32 value = 0;
-    unsigned aqmNeWatermark = 0;
-    unsigned aqmNfWatermark = 0;
-
-    address = (UINT32*)(aqmBaseAddress +
-		     IX_QMGR_Q_CONFIG_ADDR_GET(qId));
-
-    aqmNeWatermark = watermarkToAqmWatermark (ne);
-    aqmNfWatermark = watermarkToAqmWatermark (nf);
-
-    /* Read the current watermarks */
-    ixQMgrAqmIfWordRead (address, &value);
-
-    /* Clear out the old watermarks */
-    value &=  IX_QMGR_NE_NF_CLEAR_MASK;
-    
-    /* Generate the value to write */
-    value |= (aqmNeWatermark << IX_QMGR_Q_CONFIG_NE_OFFSET) |
-	(aqmNfWatermark << IX_QMGR_Q_CONFIG_NF_OFFSET); 
-
-    ixQMgrAqmIfWordWrite (address, value);
-
-}
-
-PRIVATE void
-ixQMgrAqmIfEntryAddressGet (unsigned int entryIndex,
-			    UINT32 configRegWord,
-			    unsigned int qEntrySizeInwords,
-			    unsigned int qSizeInWords,
-			    UINT32 **address)
-{
-    UINT32 readPtr;
-    UINT32 baseAddress;
-    UINT32 *topOfAqmSram;
-
-    topOfAqmSram = ((UINT32 *)aqmBaseAddress + IX_QMGR_AQM_ADDRESS_SPACE_SIZE_IN_WORDS);
-
-    /* Extract the base address */
-    baseAddress = (UINT32)((configRegWord & IX_QMGR_BADDR_MASK) >>
-			   (IX_QMGR_Q_CONFIG_BADDR_OFFSET));
-
-    /* Base address is a 16 word pointer from the start of AQM SRAM.
-     * Convert to absolute word address.
-     */
-    baseAddress <<= IX_QMGR_BASE_ADDR_16_WORD_SHIFT;
-    baseAddress += ((UINT32)aqmBaseAddress + (UINT32)IX_QMGR_QUECONFIG_BASE_OFFSET);
-
-    /* Extract the read pointer. Read pointer is a word pointer */
-    readPtr = (UINT32)((configRegWord >>
-			IX_QMGR_Q_CONFIG_RDPTR_OFFSET)&IX_QMGR_RDPTR_MASK);
-
-    /* Read/Write pointers(word pointers)  are offsets from the queue buffer space base address.
-     * Calculate the absolute read pointer address. NOTE: Queues are circular buffers.
-     */
-    readPtr  = (readPtr + (entryIndex * qEntrySizeInwords)) & (qSizeInWords - 1); /* Mask by queue size */
-    *address = (UINT32 *)(baseAddress + (readPtr * (IX_QMGR_NUM_BYTES_PER_WORD)));
-
-    switch (qEntrySizeInwords)
-    {
-	case IX_QMGR_Q_ENTRY_SIZE1:
-	    IX_OSAL_ASSERT((*address + IX_QMGR_ENTRY1_OFFSET) < topOfAqmSram);	    
-	    break;
-	case IX_QMGR_Q_ENTRY_SIZE2:
-	    IX_OSAL_ASSERT((*address + IX_QMGR_ENTRY2_OFFSET) < topOfAqmSram);
-	    break;
-	case IX_QMGR_Q_ENTRY_SIZE4:
-	    IX_OSAL_ASSERT((*address + IX_QMGR_ENTRY4_OFFSET) < topOfAqmSram);
-	    break;
-	default:
-	    IX_QMGR_LOG_ERROR0("Invalid Q Entry size passed to ixQMgrAqmIfEntryAddressGet");
-	    break;
-    }
-    
-}
-
-IX_STATUS
-ixQMgrAqmIfQPeek (IxQMgrQId qId,
-		  unsigned int entryIndex,
-		  unsigned int *entry)
-{
-    UINT32 *cfgRegAddress = (UINT32*)(aqmBaseAddress + IX_QMGR_Q_CONFIG_ADDR_GET(qId));
-    UINT32 *entryAddress = NULL;
-    UINT32 configRegWordOnEntry;
-    UINT32 configRegWordOnExit;
-    unsigned int qEntrySizeInwords;
-    unsigned int qSizeInWords;
-
-    /* Get the queue entry size in words */
-    qEntrySizeInwords = ixQMgrQEntrySizeInWordsGet (qId);
-
-    /* Get the queue size in words */
-    qSizeInWords = ixQMgrQSizeInWordsGet (qId);
-
-    /* Read the config register */
-    ixQMgrAqmIfWordRead (cfgRegAddress, &configRegWordOnEntry);
-
-    /* Get the entry address */
-    ixQMgrAqmIfEntryAddressGet (entryIndex,
-				configRegWordOnEntry,
-				qEntrySizeInwords,
-				qSizeInWords,
-				&entryAddress);
-
-    /* Get the lock or return busy */
-    if (IX_SUCCESS != ixOsalFastMutexTryLock(&ixQMgrAqmIfPeekPokeFastMutex[qId]))
-    {
-	return IX_FAIL;
-    }
-
-    while(qEntrySizeInwords--)
-    {
-	ixQMgrAqmIfWordRead (entryAddress++, entry++);
-    }
-
-    /* Release the lock */
-    ixOsalFastMutexUnlock(&ixQMgrAqmIfPeekPokeFastMutex[qId]);
-
-    /* Read the config register */
-    ixQMgrAqmIfWordRead (cfgRegAddress, &configRegWordOnExit);
-
-    /* Check that the read and write pointers have not changed */
-    if (configRegWordOnEntry != configRegWordOnExit)
-    {
-	return IX_FAIL;
-    }
-
-    return IX_SUCCESS;
-}
-
-IX_STATUS
-ixQMgrAqmIfQPoke (IxQMgrQId qId,
-		  unsigned entryIndex,
-		  unsigned int *entry)
-{
-    UINT32 *cfgRegAddress = (UINT32*)(aqmBaseAddress + IX_QMGR_Q_CONFIG_ADDR_GET(qId));
-    UINT32 *entryAddress = NULL;
-    UINT32 configRegWordOnEntry;
-    UINT32 configRegWordOnExit;
-    unsigned int qEntrySizeInwords;
-    unsigned int qSizeInWords;
-    
-    /* Get the queue entry size in words */
-    qEntrySizeInwords = ixQMgrQEntrySizeInWordsGet (qId);
-
-    /* Get the queue size in words */
-    qSizeInWords = ixQMgrQSizeInWordsGet (qId);
-
-    /* Read the config register */
-    ixQMgrAqmIfWordRead (cfgRegAddress, &configRegWordOnEntry);
-
-    /* Get the entry address */
-    ixQMgrAqmIfEntryAddressGet (entryIndex,
-				configRegWordOnEntry,
-				qEntrySizeInwords,
-				qSizeInWords,
-				&entryAddress);
-
-    /* Get the lock or return busy */
-    if (IX_SUCCESS != ixOsalFastMutexTryLock(&ixQMgrAqmIfPeekPokeFastMutex[qId]))
-    {
-	return IX_FAIL;
-    }
-
-    /* Else read the entry directly from SRAM. This will not move the read pointer */
-    while(qEntrySizeInwords--)
-    {
-	ixQMgrAqmIfWordWrite (entryAddress++, *entry++);
-    }
-
-    /* Release the lock */
-    ixOsalFastMutexUnlock(&ixQMgrAqmIfPeekPokeFastMutex[qId]);
-
-    /* Read the config register */
-    ixQMgrAqmIfWordRead (cfgRegAddress, &configRegWordOnExit);
-
-    /* Check that the read and write pointers have not changed */
-    if (configRegWordOnEntry != configRegWordOnExit)
-    {
-	return IX_FAIL;
-    }
-
-    return IX_SUCCESS;
-}
-
-PRIVATE unsigned
-watermarkToAqmWatermark (IxQMgrWMLevel watermark )
-{
-    unsigned aqmWatermark = 0;
-
-    /*
-     * Watermarks 0("000"),1("001"),2("010"),4("011"),
-     * 8("100"),16("101"),32("110"),64("111")
-     */
-    aqmWatermark = ixQMgrAqmIfLog2 (watermark * 2);
-    
-    return aqmWatermark;
-}
-
-PRIVATE unsigned
-entrySizeToAqmEntrySize (IxQMgrQEntrySizeInWords entrySize)
-{
-    /* entrySize  1("00"),2("01"),4("10") */
-    return (ixQMgrAqmIfLog2 (entrySize));
-}
-
-PRIVATE unsigned
-bufferSizeToAqmBufferSize (unsigned bufferSizeInWords)
-{
-    /* bufferSize 16("00"),32("01),64("10"),128("11") */
-    return (ixQMgrAqmIfLog2 (bufferSizeInWords / IX_QMGR_MIN_BUFFER_SIZE));
-}
-
-/*
- * Reset AQM registers to default values.
- */
-PRIVATE void
-ixQMgrAqmIfRegistersReset (void)
-{
-    volatile UINT32 *qConfigWordAddress = NULL;
-    unsigned int i;
-
-    /*
-     * Need to initialize AQM hardware registers to an initial
-     * value as init may have been called as a result of a soft
-     * reset. i.e. soft reset does not reset hardware registers.
-     */
-
-    /* Reset queues 0..31 status registers 0..3 */
-    ixQMgrAqmIfWordWrite((UINT32 *)(aqmBaseAddress + IX_QMGR_QUELOWSTAT0_OFFSET), 
-			 IX_QMGR_QUELOWSTAT_RESET_VALUE);
-    ixQMgrAqmIfWordWrite((UINT32 *)(aqmBaseAddress + IX_QMGR_QUELOWSTAT1_OFFSET), 
-			 IX_QMGR_QUELOWSTAT_RESET_VALUE);
-    ixQMgrAqmIfWordWrite((UINT32 *)(aqmBaseAddress + IX_QMGR_QUELOWSTAT2_OFFSET), 
-			 IX_QMGR_QUELOWSTAT_RESET_VALUE);
-    ixQMgrAqmIfWordWrite((UINT32 *)(aqmBaseAddress + IX_QMGR_QUELOWSTAT3_OFFSET), 
-			 IX_QMGR_QUELOWSTAT_RESET_VALUE);
-
-    /* Reset underflow/overflow status registers 0..1 */
-    ixQMgrAqmIfWordWrite((UINT32 *)(aqmBaseAddress + IX_QMGR_QUEUOSTAT0_OFFSET), 
-			 IX_QMGR_QUEUOSTAT_RESET_VALUE);
-    ixQMgrAqmIfWordWrite((UINT32 *)(aqmBaseAddress + IX_QMGR_QUEUOSTAT1_OFFSET), 
-			 IX_QMGR_QUEUOSTAT_RESET_VALUE);
-    
-    /* Reset queues 32..63 nearly empty status registers */
-    ixQMgrAqmIfWordWrite((UINT32 *)(aqmBaseAddress + IX_QMGR_QUEUPPSTAT0_OFFSET),
-			 IX_QMGR_QUEUPPSTAT0_RESET_VALUE);
-
-    /* Reset queues 32..63 full status registers */
-    ixQMgrAqmIfWordWrite((UINT32 *)(aqmBaseAddress + IX_QMGR_QUEUPPSTAT1_OFFSET),
-			 IX_QMGR_QUEUPPSTAT1_RESET_VALUE);
-
-    /* Reset int0 status flag source select registers 0..3 */
-    ixQMgrAqmIfWordWrite((UINT32 *)(aqmBaseAddress + IX_QMGR_INT0SRCSELREG0_OFFSET),
-			 IX_QMGR_INT0SRCSELREG_RESET_VALUE);
-    ixQMgrAqmIfWordWrite((UINT32 *)(aqmBaseAddress + IX_QMGR_INT0SRCSELREG1_OFFSET),
-			 IX_QMGR_INT0SRCSELREG_RESET_VALUE);
-    ixQMgrAqmIfWordWrite((UINT32 *)(aqmBaseAddress + IX_QMGR_INT0SRCSELREG2_OFFSET),
-			 IX_QMGR_INT0SRCSELREG_RESET_VALUE);
-    ixQMgrAqmIfWordWrite((UINT32 *)(aqmBaseAddress + IX_QMGR_INT0SRCSELREG3_OFFSET),
-			 IX_QMGR_INT0SRCSELREG_RESET_VALUE);
-	 
-    /* Reset queue interrupt enable register 0..1 */
-    ixQMgrAqmIfWordWrite((UINT32 *)(aqmBaseAddress + IX_QMGR_QUEIEREG0_OFFSET),
-			 IX_QMGR_QUEIEREG_RESET_VALUE);
-    ixQMgrAqmIfWordWrite((UINT32 *)(aqmBaseAddress + IX_QMGR_QUEIEREG1_OFFSET),
-			 IX_QMGR_QUEIEREG_RESET_VALUE);
-
-    /* Reset queue interrupt register 0..1 */
-    ixQMgrAqmIfWordWrite((UINT32 *)(aqmBaseAddress + IX_QMGR_QINTREG0_OFFSET),
-			 IX_QMGR_QINTREG_RESET_VALUE);
-    ixQMgrAqmIfWordWrite((UINT32 *)(aqmBaseAddress + IX_QMGR_QINTREG1_OFFSET),
-			 IX_QMGR_QINTREG_RESET_VALUE);
-
-    /* Reset queue configuration words 0..63 */
-    qConfigWordAddress = (UINT32 *)(aqmBaseAddress + IX_QMGR_QUECONFIG_BASE_OFFSET);
-    for (i = 0; i < (IX_QMGR_QUECONFIG_SIZE / sizeof(UINT32)); i++)
-    {
-	ixQMgrAqmIfWordWrite(qConfigWordAddress,
-			     IX_QMGR_QUECONFIG_RESET_VALUE);
-	/* Next word */
-	qConfigWordAddress++;
-    }
-}
-
diff --git a/drivers/net/npe/IxQMgrDispatcher.c b/drivers/net/npe/IxQMgrDispatcher.c
deleted file mode 100644
index 2baeaafeb1..0000000000
--- a/drivers/net/npe/IxQMgrDispatcher.c
+++ /dev/null
@@ -1,1320 +0,0 @@
-/**
- * @file    IxQMgrDispatcher.c
- *
- * @author Intel Corporation
- * @date    20-Dec-2001
- *    
- * @brief   This file contains the implementation of the Dispatcher sub component
- *
- * 
- * @par
- * IXP400 SW Release version 2.0
- * 
- * -- Copyright Notice --
- * 
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- * 
- * @par
- * SPDX-License-Identifier:	BSD-3-Clause
- * @par
- * -- End of Copyright Notice --
-*/
-
-/*
- * User defined include files.
- */
-#include "IxQMgr.h"
-#include "IxQMgrAqmIf_p.h"
-#include "IxQMgrQCfg_p.h"
-#include "IxQMgrDispatcher_p.h"
-#include "IxQMgrLog_p.h"
-#include "IxQMgrDefines_p.h"
-#include "IxFeatureCtrl.h"
-#include "IxOsal.h"
-
-
-
-/*
- * #defines and macros used in this file.
- */
-
-
-/*
- * This constant is used to indicate the number of priority levels supported
- */
-#define IX_QMGR_NUM_PRIORITY_LEVELS 3
-
-/* 
- * This constant is used to set the size of the array of status words
- */
-#define MAX_Q_STATUS_WORDS      4
-
-/*
- * This macro is used to check if a given priority is valid
- */
-#define IX_QMGR_DISPATCHER_PRIORITY_CHECK(priority) \
-(((priority) >= IX_QMGR_Q_PRIORITY_0) && ((priority) <= IX_QMGR_Q_PRIORITY_2))
-
-/*
- * This macto is used to check that a given interrupt source is valid
- */
-#define IX_QMGR_DISPATCHER_SOURCE_ID_CHECK(srcSel) \
-(((srcSel) >= IX_QMGR_Q_SOURCE_ID_E) && ((srcSel) <= IX_QMGR_Q_SOURCE_ID_NOT_F))
-
-/*
- * Number of times a dummy callback is called before logging a trace
- * message
- */
-#define LOG_THROTTLE_COUNT 1000000
-
-/* Priority tables limits */
-#define IX_QMGR_MIN_LOW_QUE_PRIORITY_TABLE_INDEX (0)
-#define IX_QMGR_MID_LOW_QUE_PRIORITY_TABLE_INDEX (16)
-#define IX_QMGR_MAX_LOW_QUE_PRIORITY_TABLE_INDEX (31)
-#define IX_QMGR_MIN_UPP_QUE_PRIORITY_TABLE_INDEX (32)
-#define IX_QMGR_MID_UPP_QUE_PRIORITY_TABLE_INDEX (48)
-#define IX_QMGR_MAX_UPP_QUE_PRIORITY_TABLE_INDEX (63)
- 
-/*
- * This macro is used to check if a given callback type is valid
- */
-#define IX_QMGR_DISPATCHER_CALLBACK_TYPE_CHECK(type) \
-            (((type) >= IX_QMGR_TYPE_REALTIME_OTHER) && \
-            ((type) <= IX_QMGR_TYPE_REALTIME_SPORADIC))
-
-/* 
- * define max index in lower queue to use in loops 
- */
-#define IX_QMGR_MAX_LOW_QUE_TABLE_INDEX (31)
-
-/*
- * Typedefs whose scope is limited to this file.
- */
-
-/*
- * Information on a queue needed by the Dispatcher
- */
-typedef struct 
-{
-    IxQMgrCallback callback;       /* Notification callback                  */
-    IxQMgrCallbackId callbackId;   /* Notification callback identifier       */
-    unsigned dummyCallbackCount;   /* Number of times runs of dummy callback */
-    IxQMgrPriority priority;       /* Dispatch priority                      */
-    unsigned int statusWordOffset; /* Offset to the status word to check     */
-    UINT32 statusMask;             /* Status mask                            */    
-    UINT32 statusCheckValue;       /* Status check value                     */
-    UINT32 intRegCheckMask;	   /* Interrupt register check mask          */
-} IxQMgrQInfo;
-
-/*
- * Variable declarations global to this file. Externs are followed by
- * statics.
- */
-
-/* 
- * Flag to keep record of what dispatcher set in featureCtrl when ixQMgrInit()
- * is called. This is needed because it is possible that a client might
- * change whether the live lock prevention dispatcher is used between
- * calls to ixQMgrInit() and ixQMgrDispatcherLoopGet(). 
- */
-PRIVATE IX_STATUS ixQMgrOrigB0Dispatcher = IX_FEATURE_CTRL_COMPONENT_ENABLED;
-
-/* 
- * keep record of Q types - not in IxQMgrQInfo for performance as
- * it is only used with ixQMgrDispatcherLoopRunB0LLP()
- */
-PRIVATE IxQMgrType ixQMgrQTypes[IX_QMGR_MAX_NUM_QUEUES];
-
-/*
- * This array contains a list of queue identifiers ordered by priority. The table
- * is split logically between queue identifiers 0-31 and 32-63.
- */
-static IxQMgrQId priorityTable[IX_QMGR_MAX_NUM_QUEUES];
-
-/*
- * This flag indicates to the dispatcher that the priority table needs to be rebuilt.
- */
-static BOOL rebuildTable = false;
-
-/* Dispatcher statistics */
-static IxQMgrDispatcherStats dispatcherStats;
-
-/* Table of queue information */
-static IxQMgrQInfo dispatchQInfo[IX_QMGR_MAX_NUM_QUEUES];
-
-/* Masks use to identify the first queues in the priority tables 
-*  when comparing with the interrupt register
-*/
-static unsigned int lowPriorityTableFirstHalfMask;
-static unsigned int uppPriorityTableFirstHalfMask;
-
-/*
- * Static function prototypes
- */
-
-/*
- * This function is the default callback for all queues
- */
-PRIVATE void
-dummyCallback (IxQMgrQId qId,	      
-	       IxQMgrCallbackId cbId);
-
-PRIVATE void
-ixQMgrDispatcherReBuildPriorityTable (void);
-
-/*
- * Function definitions.
- */
-void
-ixQMgrDispatcherInit (void)
-{
-    int i;
-    IxFeatureCtrlProductId productId = 0;
-    IxFeatureCtrlDeviceId deviceId = 0;
-    BOOL stickyIntSilicon = true;
-
-    /* Set default priorities */
-    for (i=0; i< IX_QMGR_MAX_NUM_QUEUES; i++)
-    {
-	dispatchQInfo[i].callback = dummyCallback;
-	dispatchQInfo[i].callbackId = 0;
-	dispatchQInfo[i].dummyCallbackCount = 0;
-	dispatchQInfo[i].priority = IX_QMGR_Q_PRIORITY_2;
-	dispatchQInfo[i].statusWordOffset = 0;
-	dispatchQInfo[i].statusCheckValue = 0;
-	dispatchQInfo[i].statusMask = 0;  
-        /* 
-	 * There are two interrupt registers, 32 bits each. One for the lower
-	 * queues(0-31) and one for the upper queues(32-63). Therefore need to
-	 * mod by 32 i.e the min upper queue identifier.
-	 */
-	dispatchQInfo[i].intRegCheckMask = (1<<(i%(IX_QMGR_MIN_QUEUPP_QID)));
-
-        /* 
-         * Set the Q types - will only be used with livelock 
-         */
-        ixQMgrQTypes[i] = IX_QMGR_TYPE_REALTIME_OTHER;
-
-	/* Reset queue statistics */
-	dispatcherStats.queueStats[i].callbackCnt = 0;
-	dispatcherStats.queueStats[i].priorityChangeCnt = 0;
-	dispatcherStats.queueStats[i].intNoCallbackCnt = 0;
-	dispatcherStats.queueStats[i].intLostCallbackCnt = 0;
-        dispatcherStats.queueStats[i].notificationEnabled = false;
-        dispatcherStats.queueStats[i].srcSel = 0;
-
-    }
-
-    /* Priority table. Order the table from queue 0 to 63 */
-    ixQMgrDispatcherReBuildPriorityTable();
-
-    /* Reset statistics */
-    dispatcherStats.loopRunCnt = 0;
-
-    /* Get the device ID for the underlying silicon */
-    deviceId = ixFeatureCtrlDeviceRead();
-    
-    /* Get the product ID for the underlying silicon */
-    productId = ixFeatureCtrlProductIdRead();
-
-    /* 
-     * Check featureCtrl to see if Livelock prevention is required 
-     */
-    ixQMgrOrigB0Dispatcher = ixFeatureCtrlSwConfigurationCheck( 
-                                 IX_FEATURECTRL_ORIGB0_DISPATCHER);
-
-    /*
-     * Check if the silicon supports the sticky interrupt feature.
-     * IF (IXP42X AND A0) -> No sticky interrupt feature supported 
-     */
-    if ((IX_FEATURE_CTRL_DEVICE_TYPE_IXP42X == 
-        (IX_FEATURE_CTRL_DEVICE_TYPE_MASK & deviceId)) &&
-        (IX_FEATURE_CTRL_SILICON_TYPE_A0 == 
-        (IX_FEATURE_CTRL_SILICON_STEPPING_MASK & productId))) 
-    {
-       stickyIntSilicon = false;
-    }
-
-    /*
-     * IF user wants livelock prev option AND silicon supports sticky interrupt 
-     * feature -> enable the sticky interrupt bit
-     */
-    if ((IX_FEATURE_CTRL_SWCONFIG_DISABLED == ixQMgrOrigB0Dispatcher) &&
-         stickyIntSilicon)  
-    {
-        ixQMgrStickyInterruptRegEnable();
-    }
-}
-
-IX_STATUS
-ixQMgrDispatcherPrioritySet (IxQMgrQId qId,
-			     IxQMgrPriority priority)
-{   
-    int ixQMgrLockKey;
-
-    if (!ixQMgrQIsConfigured(qId))
-    {
-	return IX_QMGR_Q_NOT_CONFIGURED;
-    }
-    
-    if (!IX_QMGR_DISPATCHER_PRIORITY_CHECK(priority))
-    {
-	return IX_QMGR_Q_INVALID_PRIORITY;
-    }
-
-    ixQMgrLockKey = ixOsalIrqLock();
-    
-    /* Change priority */
-    dispatchQInfo[qId].priority = priority;
-    /* Set flag */
-    rebuildTable = true;
-
-    ixOsalIrqUnlock(ixQMgrLockKey);
-
-#ifndef NDEBUG
-    /* Update statistics */
-    dispatcherStats.queueStats[qId].priorityChangeCnt++;
-#endif
-
-    return IX_SUCCESS;
-}
-
-IX_STATUS
-ixQMgrNotificationCallbackSet (IxQMgrQId qId,
-			       IxQMgrCallback callback,
-			       IxQMgrCallbackId callbackId)
-{
-    if (!ixQMgrQIsConfigured(qId))
-    {
-	return IX_QMGR_Q_NOT_CONFIGURED;
-    }
-
-    if (NULL == callback)
-    {
-	/* Reset to dummy callback */
-	dispatchQInfo[qId].callback = dummyCallback;
-	dispatchQInfo[qId].dummyCallbackCount = 0;
-	dispatchQInfo[qId].callbackId = 0;
-    }
-    else 
-    {
-	dispatchQInfo[qId].callback = callback;
-	dispatchQInfo[qId].callbackId = callbackId;
-    }
-
-    return IX_SUCCESS;
-}
-
-IX_STATUS
-ixQMgrNotificationEnable (IxQMgrQId qId, 
-			  IxQMgrSourceId srcSel)
-{
-    IxQMgrQStatus qStatusOnEntry;/* The queue status on entry/exit */
-    IxQMgrQStatus qStatusOnExit; /* to this function               */
-    int ixQMgrLockKey;
-
-#ifndef NDEBUG
-    if (!ixQMgrQIsConfigured (qId))
-    {
-	return IX_QMGR_Q_NOT_CONFIGURED;
-    }
-
-    if ((qId < IX_QMGR_MIN_QUEUPP_QID) &&
-       !IX_QMGR_DISPATCHER_SOURCE_ID_CHECK(srcSel))
-    {
-	/* QId 0-31 source id invalid */
-	return IX_QMGR_INVALID_INT_SOURCE_ID;
-    }
-
-    if ((IX_QMGR_Q_SOURCE_ID_NE != srcSel) &&
-	(qId >= IX_QMGR_MIN_QUEUPP_QID))
-    {
-	/*
-	 * For queues 32-63 the interrupt source is fixed to the Nearly
-	 * Empty status flag and therefore should have a srcSel of NE.
-	 */
-	return IX_QMGR_INVALID_INT_SOURCE_ID;
-    }
-#endif
-
-#ifndef NDEBUG
-    dispatcherStats.queueStats[qId].notificationEnabled = true;
-    dispatcherStats.queueStats[qId].srcSel = srcSel;
-#endif
-
-    /* Get the current queue status */
-    ixQMgrAqmIfQueStatRead (qId, &qStatusOnEntry);
-  
-    /* 
-     * Enabling interrupts results in Read-Modify-Write
-     * so need critical section
-     */
-
-    ixQMgrLockKey = ixOsalIrqLock();
-
-    /* Calculate the checkMask and checkValue for this q */
-    ixQMgrAqmIfQStatusCheckValsCalc (qId,
-				     srcSel,
-				     &dispatchQInfo[qId].statusWordOffset,
-				     &dispatchQInfo[qId].statusCheckValue,
-				     &dispatchQInfo[qId].statusMask);
-
-
-    /* Set the interrupt source is this queue is in the range 0-31 */
-    if (qId < IX_QMGR_MIN_QUEUPP_QID)
-    {
-	ixQMgrAqmIfIntSrcSelWrite (qId, srcSel);
-    }
-
-    /* Enable the interrupt */
-    ixQMgrAqmIfQInterruptEnable (qId);
-
-    ixOsalIrqUnlock(ixQMgrLockKey);
-    
-    /* Get the current queue status */
-    ixQMgrAqmIfQueStatRead (qId, &qStatusOnExit);
-  
-    /* If the status has changed return a warning */
-    if (qStatusOnEntry != qStatusOnExit)
-    {
-	return IX_QMGR_WARNING;
-    }
-    
-    return IX_SUCCESS;
-}
-
-
-IX_STATUS
-ixQMgrNotificationDisable (IxQMgrQId qId)
-{
-    int ixQMgrLockKey;
-
-#ifndef NDEBUG
-    /* Validate parameters */
-    if (!ixQMgrQIsConfigured (qId))
-    {
-	return IX_QMGR_Q_NOT_CONFIGURED;
-    }
-#endif
-  
-    /* 
-     * Enabling interrupts results in Read-Modify-Write
-     * so need critical section
-     */
-#ifndef NDEBUG
-    dispatcherStats.queueStats[qId].notificationEnabled = false;
-#endif
-
-    ixQMgrLockKey = ixOsalIrqLock();
-
-    ixQMgrAqmIfQInterruptDisable (qId);
-    
-    ixOsalIrqUnlock(ixQMgrLockKey);
-
-    return IX_SUCCESS;    
-}
-
-void 
-ixQMgrStickyInterruptRegEnable(void)
-{
- /* Use Aqm If function to set Interrupt Register0 Bit-3 */ 
- ixQMgrAqmIfIntSrcSelReg0Bit3Set ();   
-}
-
-#if !defined __XSCALE__ || defined __linux
-
-/* Count the number of leading zero bits in a word,
- * and return the same value than the CLZ instruction.
- *
- * word (in)    return value (out)
- * 0x80000000   0
- * 0x40000000   1
- * ,,,          ,,,
- * 0x00000002   30
- * 0x00000001   31
- * 0x00000000   32
- *
- * The C version of this function is used as a replacement 
- * for system not providing the equivalent of the CLZ 
- * assembly language instruction.
- *
- * Note that this version is big-endian
- */
-unsigned int
-ixQMgrCountLeadingZeros(UINT32 word)
-{
-  unsigned int leadingZerosCount = 0;
-
-  if (word == 0)
-  {
-      return 32;
-  }
-  /* search the first bit set by testing the MSB and shifting the input word */
-  while ((word & 0x80000000) == 0)
-  {
-      word <<= 1;
-      leadingZerosCount++;
-  }
-  return leadingZerosCount;
-}
-#endif /* not  __XSCALE__ or __linux */
-
-void
-ixQMgrDispatcherLoopGet (IxQMgrDispatcherFuncPtr *qDispatcherFuncPtr)
-{
-  IxFeatureCtrlProductId productId = 0;
-  IxFeatureCtrlDeviceId deviceId = 0;
-  
-  /* Get the device ID for the underlying silicon */
-  deviceId = ixFeatureCtrlDeviceRead();
-
-  /* Get the product ID for the underlying silicon */
-  productId = ixFeatureCtrlProductIdRead ();
-
-  /* IF (IXP42X AND A0 silicon) -> use ixQMgrDispatcherLoopRunA0 */
-  if ((IX_FEATURE_CTRL_DEVICE_TYPE_IXP42X ==
-      (IX_FEATURE_CTRL_DEVICE_TYPE_MASK & deviceId)) &&
-      (IX_FEATURE_CTRL_SILICON_TYPE_A0 ==  
-      (IX_FEATURE_CTRL_SILICON_STEPPING_MASK & productId)))  
-  {
-    /*For IXP42X A0 silicon */
-    *qDispatcherFuncPtr = &ixQMgrDispatcherLoopRunA0 ;
-  } 
-  else /*For IXP42X B0 or IXP46X silicon*/ 
-  { 
-    if (IX_FEATURE_CTRL_SWCONFIG_ENABLED == ixQMgrOrigB0Dispatcher)
-    {
-        /* Default for IXP42X B0 and IXP46X silicon */
-        *qDispatcherFuncPtr = &ixQMgrDispatcherLoopRunB0;
-    }
-    else 
-    {
-        /* FeatureCtrl indicated that livelock dispatcher be used */
-        *qDispatcherFuncPtr = &ixQMgrDispatcherLoopRunB0LLP;
-    }
-  }
-}
-
-void
-ixQMgrDispatcherLoopRunA0 (IxQMgrDispatchGroup group)
-{
-    UINT32 intRegVal;                /* Interrupt reg val */
-    UINT32 intRegValAfterWrite;      /* Interrupt reg val after writing back */
-    UINT32 intRegCheckMask;          /* Mask for checking interrupt bits */
-    UINT32 qStatusWordsB4Write[MAX_Q_STATUS_WORDS];  /* Status b4 interrupt write */
-    UINT32 qStatusWordsAfterWrite[MAX_Q_STATUS_WORDS]; /* Status after interrupt write */
-    IxQMgrQInfo *currDispatchQInfo;
-    BOOL statusChangeFlag;
-
-    int priorityTableIndex;/* Priority table index */
-    int qIndex;            /* Current queue being processed */
-    int endIndex;          /* Index of last queue to process */
-
-#ifndef NDEBUG
-    IX_OSAL_ASSERT((group == IX_QMGR_QUEUPP_GROUP) || 
-	      (group == IX_QMGR_QUELOW_GROUP));
-#endif
-
-    /* Read Q status registers before interrupt status read/write */
-    ixQMgrAqmIfQStatusRegsRead (group, qStatusWordsB4Write);
-
-    /* Read the interrupt register */
-    ixQMgrAqmIfQInterruptRegRead (group, &intRegVal);
-
-    /* No bit set : nothing to process (the reaminder of the algorithm is
-    * based on the fact that the interrupt register value contains at
-    * least one bit set
-    */
-    if (intRegVal == 0) 
-    {
-#ifndef NDEBUG
-	/* Update statistics */
-	dispatcherStats.loopRunCnt++;
-#endif
-
-	/* Rebuild the priority table if needed */
-	if (rebuildTable)
-	{
-	    ixQMgrDispatcherReBuildPriorityTable ();
-	}
-
-	return;
-    }
-   
-    /* Write it back to clear the interrupt */
-    ixQMgrAqmIfQInterruptRegWrite (group, intRegVal);
-
-    /* Read Q status registers after interrupt status read/write */
-    ixQMgrAqmIfQStatusRegsRead (group, qStatusWordsAfterWrite);
- 
-    /* get the first queue Id from the interrupt register value */
-    qIndex = (BITS_PER_WORD - 1) - ixQMgrCountLeadingZeros(intRegVal);
-
-    /* check if any change occured during hw register modifications */ 
-    if (IX_QMGR_QUELOW_GROUP == group)
-    {
-	statusChangeFlag = 
-	    (qStatusWordsB4Write[0] != qStatusWordsAfterWrite[0]) ||
-	    (qStatusWordsB4Write[1] != qStatusWordsAfterWrite[1]) ||
-	    (qStatusWordsB4Write[2] != qStatusWordsAfterWrite[2]) ||
-	    (qStatusWordsB4Write[3] != qStatusWordsAfterWrite[3]);
-    }
-    else
-    {
-	statusChangeFlag = 
-	    (qStatusWordsB4Write[0] != qStatusWordsAfterWrite[0]);
-	/* Set the queue range based on the queue group to proccess */
-	qIndex += IX_QMGR_MIN_QUEUPP_QID;
-    }
-
-    if (statusChangeFlag == false)
-    {
-	/* check if the interrupt register contains 
-	 * only 1 bit set (happy day scenario)
-	 */
-	currDispatchQInfo = &dispatchQInfo[qIndex];
-	if (intRegVal == currDispatchQInfo->intRegCheckMask)
-	{
-	    /* only 1 queue event triggered a notification *
-	     * Call the callback function for this queue 
-	     */
-	    currDispatchQInfo->callback (qIndex,
-					 currDispatchQInfo->callbackId);  
-#ifndef NDEBUG
-	    /* Update statistics */
-	    dispatcherStats.queueStats[qIndex].callbackCnt++;
-#endif
-	}
-	else 
-	{
-	    /* the event is triggered by more than 1 queue, 
-	     * the queue search will be starting from the beginning
-	     * or the middle of the priority table
-	     *
-	     * the serach will end when all the bits of the interrupt
-	     * register are cleared. There is no need to maintain
-	     * a seperate value and test it at each iteration.
-	     */
-	    if (IX_QMGR_QUELOW_GROUP == group)
-	    {
-		/* check if any bit related to queues in the first
-		 * half of the priority table is set
-		 */
-		if (intRegVal & lowPriorityTableFirstHalfMask)
-		{
-		    priorityTableIndex = IX_QMGR_MIN_LOW_QUE_PRIORITY_TABLE_INDEX;
-		}
-		else
-		{
-		    priorityTableIndex = IX_QMGR_MID_LOW_QUE_PRIORITY_TABLE_INDEX;
-		}
-	    }
-	    else 
-	    {
-		/* check if any bit related to queues in the first
-		 * half of the priority table is set
-		 */
-		if (intRegVal & uppPriorityTableFirstHalfMask)
-		{
-		    priorityTableIndex = IX_QMGR_MIN_UPP_QUE_PRIORITY_TABLE_INDEX;
-		}
-		else
-		{
-		    priorityTableIndex = IX_QMGR_MID_UPP_QUE_PRIORITY_TABLE_INDEX;
-		}
-	    }
-	    
-	    /* iterate following the priority table until all the bits 
-	     * of the interrupt register are cleared.
-	     */
-	    do
-	    {
-		qIndex = priorityTable[priorityTableIndex++];
-		currDispatchQInfo = &dispatchQInfo[qIndex];
-		intRegCheckMask = currDispatchQInfo->intRegCheckMask;
-		
-		/* If this queue caused this interrupt to be raised */
-		if (intRegVal & intRegCheckMask)
-		{
-		    /* Call the callback function for this queue */
-		    currDispatchQInfo->callback (qIndex,
-						 currDispatchQInfo->callbackId);
-#ifndef NDEBUG
-		    /* Update statistics */
-		    dispatcherStats.queueStats[qIndex].callbackCnt++;
-#endif
-		    
-		    /* Clear the interrupt register bit */
-		    intRegVal &= ~intRegCheckMask;
-		}
-	    }
-	    while(intRegVal);
-	}
-    }
-    else
-    {
-    /* A change in queue status occured during the hw interrupt
-     * register update. To maintain the interrupt consistency, it
-     * is necessary to iterate through all queues of the queue group.
-     */
-
-    /* Read interrupt status again */
-    ixQMgrAqmIfQInterruptRegRead (group, &intRegValAfterWrite);
-
-    if (IX_QMGR_QUELOW_GROUP == group)
-    {
-	priorityTableIndex = IX_QMGR_MIN_LOW_QUE_PRIORITY_TABLE_INDEX;
-	endIndex = IX_QMGR_MAX_LOW_QUE_PRIORITY_TABLE_INDEX;
-    }
-    else
-    {
-	priorityTableIndex = IX_QMGR_MIN_UPP_QUE_PRIORITY_TABLE_INDEX;
-	endIndex = IX_QMGR_MAX_UPP_QUE_PRIORITY_TABLE_INDEX;
-    }
-
-    for ( ; priorityTableIndex<=endIndex; priorityTableIndex++)
-    {
-	qIndex = priorityTable[priorityTableIndex];
-	currDispatchQInfo = &dispatchQInfo[qIndex];
-	intRegCheckMask = currDispatchQInfo->intRegCheckMask;
-
-	/* If this queue caused this interrupt to be raised */
-	if (intRegVal & intRegCheckMask)
-	{  
-	    /* Call the callback function for this queue */
-	    currDispatchQInfo->callback (qIndex,
-					 currDispatchQInfo->callbackId);
-#ifndef NDEBUG
-	    /* Update statistics */
-	    dispatcherStats.queueStats[qIndex].callbackCnt++;
-#endif
-	    
-	} /* if (intRegVal .. */
-
-	/* 
-	 * If interrupt bit is set in intRegValAfterWrite don't
-	 * proceed as this will be caught in next interrupt
-	 */
-	else if ((intRegValAfterWrite & intRegCheckMask) == 0)
-	{
-	    /* Check if an interrupt was lost for this Q */
-	    if (ixQMgrAqmIfQStatusCheck(qStatusWordsB4Write,
-					qStatusWordsAfterWrite,
-					currDispatchQInfo->statusWordOffset,
-					currDispatchQInfo->statusCheckValue,
-					currDispatchQInfo->statusMask))
-	    {
-		/* Call the callback function for this queue */
-		currDispatchQInfo->callback (qIndex, 
-					     dispatchQInfo[qIndex].callbackId);                 
-#ifndef NDEBUG
-		/* Update statistics */
-		dispatcherStats.queueStats[qIndex].callbackCnt++;
-		dispatcherStats.queueStats[qIndex].intLostCallbackCnt++;
-#endif
-	    } /* if ixQMgrAqmIfQStatusCheck(.. */
-	} /* else if ((intRegValAfterWrite ... */
-    } /* for (priorityTableIndex=0 ... */
-    }
-
-    /* Rebuild the priority table if needed */
-    if (rebuildTable)
-    {
-	ixQMgrDispatcherReBuildPriorityTable ();
-    }
-
-#ifndef NDEBUG
-    /* Update statistics */
-    dispatcherStats.loopRunCnt++;
-#endif
-}
-
-
-
-void
-ixQMgrDispatcherLoopRunB0 (IxQMgrDispatchGroup group)
-{
-    UINT32 intRegVal;                /* Interrupt reg val */
-    UINT32 intRegCheckMask;          /* Mask for checking interrupt bits */
-    IxQMgrQInfo *currDispatchQInfo;
-
-
-    int priorityTableIndex; /* Priority table index */
-    int qIndex;             /* Current queue being processed */
-
-#ifndef NDEBUG
-    IX_OSAL_ASSERT((group == IX_QMGR_QUEUPP_GROUP) ||
-              (group == IX_QMGR_QUELOW_GROUP));
-    IX_OSAL_ASSERT((group == IX_QMGR_QUEUPP_GROUP) || 
-	      (group == IX_QMGR_QUELOW_GROUP));
-#endif
-
-    /* Read the interrupt register */
-    ixQMgrAqmIfQInterruptRegRead (group, &intRegVal);
-
-
-    /* No queue has interrupt register set */
-    if (intRegVal != 0)
-    {
-
-            /* Write it back to clear the interrupt */
-            ixQMgrAqmIfQInterruptRegWrite (group, intRegVal);
-
-            /* get the first queue Id from the interrupt register value */
-            qIndex = (BITS_PER_WORD - 1) - ixQMgrCountLeadingZeros(intRegVal);
-
-            if (IX_QMGR_QUEUPP_GROUP == group)
-            {
-                /* Set the queue range based on the queue group to proccess */
-                qIndex += IX_QMGR_MIN_QUEUPP_QID;
-            }
-
-            /* check if the interrupt register contains
-             * only 1 bit set
-             * For example:
-             *                                        intRegVal = 0x0010
-             *               currDispatchQInfo->intRegCheckMask = 0x0010
-             *    intRegVal == currDispatchQInfo->intRegCheckMask is true.
-             */
-             currDispatchQInfo = &dispatchQInfo[qIndex];
-             if (intRegVal == currDispatchQInfo->intRegCheckMask)
-             {
-                /* only 1 queue event triggered a notification *
-                 * Call the callback function for this queue
-                 */
-                currDispatchQInfo->callback (qIndex,
-                                     currDispatchQInfo->callbackId);
-#ifndef NDEBUG
-                /* Update statistics */
-                dispatcherStats.queueStats[qIndex].callbackCnt++;
-#endif
-             }
-             else
-             {
-                 /* the event is triggered by more than 1 queue,
-                  * the queue search will be starting from the beginning
-                  * or the middle of the priority table
-                  *
-                  * the serach will end when all the bits of the interrupt
-                  * register are cleared. There is no need to maintain
-                  * a seperate value and test it at each iteration.
-                  */
-                 if (IX_QMGR_QUELOW_GROUP == group)
-                 {
-                     /* check if any bit related to queues in the first
-                      * half of the priority table is set
-                      */
-                     if (intRegVal & lowPriorityTableFirstHalfMask)
-                     {
-                         priorityTableIndex = IX_QMGR_MIN_LOW_QUE_PRIORITY_TABLE_INDEX;
-                     }
-                     else
-                     {
-                         priorityTableIndex = IX_QMGR_MID_LOW_QUE_PRIORITY_TABLE_INDEX;
-                     }
-                 }
-                else
-                 {
-                     /* check if any bit related to queues in the first
-                      * half of the priority table is set
-                      */
-                     if (intRegVal & uppPriorityTableFirstHalfMask)
-                     {
-                         priorityTableIndex = IX_QMGR_MIN_UPP_QUE_PRIORITY_TABLE_INDEX;
-                     }
-                     else
-                     {
-                         priorityTableIndex = IX_QMGR_MID_UPP_QUE_PRIORITY_TABLE_INDEX;
-                     }
-                 }
-
-                 /* iterate following the priority table until all the bits
-                  * of the interrupt register are cleared.
-                  */
-                 do
-                 {
-                     qIndex = priorityTable[priorityTableIndex++];
-                     currDispatchQInfo = &dispatchQInfo[qIndex];
-                     intRegCheckMask = currDispatchQInfo->intRegCheckMask;
-
-                     /* If this queue caused this interrupt to be raised */
-                     if (intRegVal & intRegCheckMask)
-                     {
-                         /* Call the callback function for this queue */
-                         currDispatchQInfo->callback (qIndex,
-                                              currDispatchQInfo->callbackId);
-#ifndef NDEBUG
-                         /* Update statistics */
-                         dispatcherStats.queueStats[qIndex].callbackCnt++;
-#endif
-
-                         /* Clear the interrupt register bit */
-                         intRegVal &= ~intRegCheckMask;
-                     }
-                  }
-                  while(intRegVal);
-             } /*End of intRegVal == currDispatchQInfo->intRegCheckMask */
-     } /* End of intRegVal != 0 */
-
-#ifndef NDEBUG
-    /* Update statistics */
-    dispatcherStats.loopRunCnt++;
-#endif
-
-    /* Rebuild the priority table if needed */
-    if (rebuildTable)
-    {
-        ixQMgrDispatcherReBuildPriorityTable ();
-    }
-}
-
-void
-ixQMgrDispatcherLoopRunB0LLP (IxQMgrDispatchGroup group)
-{
-    UINT32 intRegVal =0;                /* Interrupt reg val */
-    UINT32 intRegCheckMask;          /* Mask for checking interrupt bits */
-    IxQMgrQInfo *currDispatchQInfo;
-
-    int priorityTableIndex; /* Priority table index */
-    int qIndex;             /* Current queue being processed */
-
-    UINT32 intRegValCopy = 0;
-    UINT32 intEnableRegVal = 0;
-    UINT8 i = 0;
-
-#ifndef NDEBUG
-    IX_OSAL_ASSERT((group == IX_QMGR_QUEUPP_GROUP) ||
-              (group == IX_QMGR_QUELOW_GROUP));
-#endif
-
-    /* Read the interrupt register */
-    ixQMgrAqmIfQInterruptRegRead (group, &intRegVal);
-
-    /* 
-     * mask any interrupts that are not enabled 
-     */
-    ixQMgrAqmIfQInterruptEnableRegRead (group, &intEnableRegVal);
-    intRegVal &= intEnableRegVal;
-
-    /* No queue has interrupt register set */
-    if (intRegVal != 0)
-    {
-        if (IX_QMGR_QUELOW_GROUP == group)
-        {
-            /*
-             * As the sticky bit is set, the interrupt register will 
-             * not clear if write back at this point because the condition
-             * has not been cleared. Take a copy and write back later after
-             * the condition has been cleared
-             */
-            intRegValCopy = intRegVal;
-        }
-        else
-        {
-            /* no sticky for upper Q's, so write back now */
-            ixQMgrAqmIfQInterruptRegWrite (group, intRegVal);
-        }
-
-        /* get the first queue Id from the interrupt register value */
-        qIndex = (BITS_PER_WORD - 1) - ixQMgrCountLeadingZeros(intRegVal);
-
-        if (IX_QMGR_QUEUPP_GROUP == group)
-        {
-            /* Set the queue range based on the queue group to proccess */
-            qIndex += IX_QMGR_MIN_QUEUPP_QID;
-        }
-
-        /* check if the interrupt register contains
-        * only 1 bit set
-        * For example:
-        *                                        intRegVal = 0x0010
-        *               currDispatchQInfo->intRegCheckMask = 0x0010
-        *    intRegVal == currDispatchQInfo->intRegCheckMask is true.
-        */
-        currDispatchQInfo = &dispatchQInfo[qIndex];
-        if (intRegVal == currDispatchQInfo->intRegCheckMask)
-        {
-
-            /* 
-             * check if Q type periodic -  only lower queues can
-             * have there type set to periodic 
-             */
-            if (IX_QMGR_TYPE_REALTIME_PERIODIC == ixQMgrQTypes[qIndex])
-            {
-                /* 
-                 * Disable the notifications on any sporadics 
-                 */
-                for (i=0; i <= IX_QMGR_MAX_LOW_QUE_TABLE_INDEX; i++)
-                {
-                    if (IX_QMGR_TYPE_REALTIME_SPORADIC == ixQMgrQTypes[i])
-                    {
-                        ixQMgrNotificationDisable(i);
-#ifndef NDEBUG
-                        /* Update statistics */
-                        dispatcherStats.queueStats[i].disableCount++;
-#endif
-                    }
-                }
-            }
-
-            currDispatchQInfo->callback (qIndex,
-                                         currDispatchQInfo->callbackId);
-#ifndef NDEBUG
-            /* Update statistics */
-            dispatcherStats.queueStats[qIndex].callbackCnt++;
-#endif
-        }
-        else
-        {
-            /* the event is triggered by more than 1 queue,
-            * the queue search will be starting from the beginning
-            * or the middle of the priority table
-            *
-            * the serach will end when all the bits of the interrupt
-            * register are cleared. There is no need to maintain
-            * a seperate value and test it at each iteration.
-            */
-            if (IX_QMGR_QUELOW_GROUP == group)
-            {
-                /* check if any bit related to queues in the first
-                 * half of the priority table is set
-                 */
-                if (intRegVal & lowPriorityTableFirstHalfMask)
-                {
-                    priorityTableIndex =
-                                       IX_QMGR_MIN_LOW_QUE_PRIORITY_TABLE_INDEX;
-                }
-                else
-                {
-                    priorityTableIndex =
-                                       IX_QMGR_MID_LOW_QUE_PRIORITY_TABLE_INDEX;
-                }
-            }
-            else
-            {
-                /* check if any bit related to queues in the first
-                 * half of the priority table is set
-                 */
-                if (intRegVal & uppPriorityTableFirstHalfMask)
-                {
-                    priorityTableIndex =
-                                       IX_QMGR_MIN_UPP_QUE_PRIORITY_TABLE_INDEX;
-                }
-                else
-                {
-                    priorityTableIndex =
-                                       IX_QMGR_MID_UPP_QUE_PRIORITY_TABLE_INDEX;
-                }
-            }
-
-            /* iterate following the priority table until all the bits
-             * of the interrupt register are cleared.
-             */
-            do
-            {
-                qIndex = priorityTable[priorityTableIndex++];
-                currDispatchQInfo = &dispatchQInfo[qIndex];
-                intRegCheckMask = currDispatchQInfo->intRegCheckMask;
-
-                /* If this queue caused this interrupt to be raised */
-                if (intRegVal & intRegCheckMask)
-                {
-                    /* 
-                     * check if Q type periodic - only lower queues can
-                     * have there type set to periodic. There can only be one
-                     * periodic queue, so the sporadics are only disabled once.
-                     */
-                    if (IX_QMGR_TYPE_REALTIME_PERIODIC == ixQMgrQTypes[qIndex])
-                    {
-                        /* 
-                         * Disable the notifications on any sporadics 
-                         */
-                        for (i=0; i <= IX_QMGR_MAX_LOW_QUE_TABLE_INDEX; i++)
-                        {
-                            if (IX_QMGR_TYPE_REALTIME_SPORADIC == 
-                                    ixQMgrQTypes[i])
-                            {
-                                ixQMgrNotificationDisable(i);
-                                /* 
-                                 * remove from intRegVal as we don't want 
-                                 * to service any sporadics now
-                                 */
-                                intRegVal &= ~dispatchQInfo[i].intRegCheckMask;
-#ifndef NDEBUG
-                                /* Update statistics */
-                                dispatcherStats.queueStats[i].disableCount++;
-#endif
-                            }
-                        }
-                    }
-
-                    currDispatchQInfo->callback (qIndex,
-                                                 currDispatchQInfo->callbackId);
-#ifndef NDEBUG
-                    /* Update statistics */
-                    dispatcherStats.queueStats[qIndex].callbackCnt++;
-#endif
-                    /* Clear the interrupt register bit */
-                    intRegVal &= ~intRegCheckMask;
-                }
-            }
-            while(intRegVal);
-        } /*End of intRegVal == currDispatchQInfo->intRegCheckMask */
-    } /* End of intRegVal != 0 */
-
-#ifndef NDEBUG
-    /* Update statistics */
-    dispatcherStats.loopRunCnt++;
-#endif
-
-    if ((intRegValCopy != 0) && (IX_QMGR_QUELOW_GROUP == group))
-    {
-        /* 
-         * lower groups (therefore sticky) AND at least one enabled interrupt
-         * Write back to clear the interrupt 
-         */
-        ixQMgrAqmIfQInterruptRegWrite (IX_QMGR_QUELOW_GROUP, intRegValCopy);
-    }
-
-    /* Rebuild the priority table if needed */
-    if (rebuildTable)
-    {
-        ixQMgrDispatcherReBuildPriorityTable ();
-    }
-}
-
-PRIVATE void
-ixQMgrDispatcherReBuildPriorityTable (void)
-{
-    UINT32 qIndex;
-    UINT32 priority;
-    int lowQuePriorityTableIndex = IX_QMGR_MIN_LOW_QUE_PRIORITY_TABLE_INDEX;
-    int uppQuePriorityTableIndex = IX_QMGR_MIN_UPP_QUE_PRIORITY_TABLE_INDEX;
-
-    /* Reset the rebuild flag */
-    rebuildTable = false;
-
-    /* initialize the mak used to identify the queues in the first half
-     * of the priority table
-     */
-    lowPriorityTableFirstHalfMask = 0;
-    uppPriorityTableFirstHalfMask = 0;
-    
-    /* For each priority level */
-    for(priority=0; priority<IX_QMGR_NUM_PRIORITY_LEVELS; priority++)
-    {
-	/* Foreach low queue in this priority */
-	for(qIndex=0; qIndex<IX_QMGR_MIN_QUEUPP_QID; qIndex++)
-	{
-	    if (dispatchQInfo[qIndex].priority == priority)
-	    { 
-		/* build the priority table bitmask which match the
-		 * queues of the first half of the priority table 
-		 */
-		if (lowQuePriorityTableIndex < IX_QMGR_MID_LOW_QUE_PRIORITY_TABLE_INDEX) 
-		{
-		    lowPriorityTableFirstHalfMask |= dispatchQInfo[qIndex].intRegCheckMask;
-		}
-		/* build the priority table */
-		priorityTable[lowQuePriorityTableIndex++] = qIndex;
-	    }
-	}
-	/* Foreach upp queue */
-	for(qIndex=IX_QMGR_MIN_QUEUPP_QID; qIndex<=IX_QMGR_MAX_QID; qIndex++)
-	{
-	    if (dispatchQInfo[qIndex].priority == priority)
-	    {
-		/* build the priority table bitmask which match the
-		 * queues of the first half of the priority table 
-		 */
-		if (uppQuePriorityTableIndex < IX_QMGR_MID_UPP_QUE_PRIORITY_TABLE_INDEX) 
-		{
-		    uppPriorityTableFirstHalfMask |= dispatchQInfo[qIndex].intRegCheckMask;
-		}
-		/* build the priority table */
-		priorityTable[uppQuePriorityTableIndex++] = qIndex;
-	    }
-	}
-    }
-}
-
-IxQMgrDispatcherStats*
-ixQMgrDispatcherStatsGet (void)
-{
-    return &dispatcherStats;
-}
-
-PRIVATE void
-dummyCallback (IxQMgrQId qId,
-	       IxQMgrCallbackId cbId)
-{
-    /* Throttle the trace message */
-    if ((dispatchQInfo[qId].dummyCallbackCount % LOG_THROTTLE_COUNT) == 0)
-    {
-	IX_QMGR_LOG_WARNING2("--> dummyCallback: qId (%d), callbackId (%d)\n",qId,cbId);
-    }
-    dispatchQInfo[qId].dummyCallbackCount++;
-
-#ifndef NDEBUG
-    /* Update statistcs */
-    dispatcherStats.queueStats[qId].intNoCallbackCnt++;
-#endif
-}
-void
-ixQMgrLLPShow (int resetStats)
-{
-#ifndef NDEBUG
-    UINT8 i = 0;
-    UINT32 intEnableRegVal = 0;
-
-    printf ("Livelock statistics are printed on the fly.\n");
-    printf ("qId Type     EnableCnt DisableCnt IntEnableState Callbacks\n");
-    printf ("=== ======== ========= ========== ============== =========\n");
-
-    for (i=0; i<= IX_QMGR_MAX_LOW_QUE_TABLE_INDEX; i++)
-    {
-        if (ixQMgrQTypes[i] != IX_QMGR_TYPE_REALTIME_OTHER)
-        {
-            printf (" %2d ", i);
-
-            if (ixQMgrQTypes[i] == IX_QMGR_TYPE_REALTIME_SPORADIC)
-            {
-                printf ("Sporadic");
-            }
-            else
-            {
-                printf ("Periodic");
-            }
-
-           
-            ixQMgrAqmIfQInterruptEnableRegRead (IX_QMGR_QUELOW_GROUP, 
-                                                    &intEnableRegVal);
-            	
-
-	    intEnableRegVal &= dispatchQInfo[i].intRegCheckMask;
-            intEnableRegVal = intEnableRegVal >> i;
-
-            printf (" %10d %10d %10d %10d\n",
-                    dispatcherStats.queueStats[i].enableCount,
-                    dispatcherStats.queueStats[i].disableCount,
-                    intEnableRegVal,
-                    dispatcherStats.queueStats[i].callbackCnt);
-
-            if (resetStats)
-            {
-                dispatcherStats.queueStats[i].enableCount =
-                dispatcherStats.queueStats[i].disableCount = 
-                dispatcherStats.queueStats[i].callbackCnt = 0;
-            }
-        }
-    }
-#else
-    IX_QMGR_LOG0("Livelock Prevention statistics are only collected in debug mode\n");
-#endif
-}
-
-void
-ixQMgrPeriodicDone (void)
-{
-    UINT32 i = 0;
-    UINT32 ixQMgrLockKey = 0;
-
-    /* 
-     * for the lower queues
-     */
-    for (i=0; i <= IX_QMGR_MAX_LOW_QUE_TABLE_INDEX; i++)
-    {
-        /*
-         * check for sporadics 
-         */
-        if (IX_QMGR_TYPE_REALTIME_SPORADIC == ixQMgrQTypes[i])
-        {
-             /* 
-              * enable any sporadics 
-              */
-             ixQMgrLockKey = ixOsalIrqLock();
-             ixQMgrAqmIfQInterruptEnable(i);
-             ixOsalIrqUnlock(ixQMgrLockKey);
-#ifndef NDEBUG
-             /* 
-              * Update statistics 
-              */
-             dispatcherStats.queueStats[i].enableCount++;
-             dispatcherStats.queueStats[i].notificationEnabled = true;
-#endif
-        }
-    }
-}
-IX_STATUS
-ixQMgrCallbackTypeSet (IxQMgrQId qId, 
-                       IxQMgrType type)
-{
-    UINT32 ixQMgrLockKey = 0;
-    IxQMgrType ixQMgrOldType =0;
-
-#ifndef NDEBUG
-    if (!ixQMgrQIsConfigured(qId))
-    {
-        return IX_QMGR_Q_NOT_CONFIGURED;
-    }
-    if (qId >= IX_QMGR_MIN_QUEUPP_QID)
-    {
-        return IX_QMGR_PARAMETER_ERROR;
-    }
-    if(!IX_QMGR_DISPATCHER_CALLBACK_TYPE_CHECK(type))
-    {
-        return IX_QMGR_PARAMETER_ERROR;
-    }
-#endif
-
-    ixQMgrOldType = ixQMgrQTypes[qId];
-    ixQMgrQTypes[qId] = type;
-
-    /*
-     * check if Q has been changed from type SPORADIC
-     */
-    if (IX_QMGR_TYPE_REALTIME_SPORADIC == ixQMgrOldType)
-    {
-       /* 
-        * previously Q was a SPORADIC, this means that LLP
-        * might have had it disabled. enable it now.
-        */
-       ixQMgrLockKey = ixOsalIrqLock();
-       ixQMgrAqmIfQInterruptEnable(qId);
-       ixOsalIrqUnlock(ixQMgrLockKey);
-
-#ifndef NDEBUG
-       /* 
-        * Update statistics 
-        */
-       dispatcherStats.queueStats[qId].enableCount++;
-#endif
-    }
-
-    return IX_SUCCESS;
-}
-
-IX_STATUS
-ixQMgrCallbackTypeGet (IxQMgrQId qId, 
-                       IxQMgrType *type)
-{
-#ifndef NDEBUG
-    if (!ixQMgrQIsConfigured(qId))
-    {
-        return IX_QMGR_Q_NOT_CONFIGURED;
-    }
-    if (qId >= IX_QMGR_MIN_QUEUPP_QID)
-    {
-        return IX_QMGR_PARAMETER_ERROR;
-    }
-    if(type == NULL)
-    {
-         return IX_QMGR_PARAMETER_ERROR;
-    }
-#endif
-
-    *type = ixQMgrQTypes[qId];
-    return IX_SUCCESS;
-}
diff --git a/drivers/net/npe/IxQMgrInit.c b/drivers/net/npe/IxQMgrInit.c
deleted file mode 100644
index 14687e61af..0000000000
--- a/drivers/net/npe/IxQMgrInit.c
+++ /dev/null
@@ -1,209 +0,0 @@
-/**
- * @file    IxQMgrInit.c
- *
- * @author Intel Corporation
- * @date    30-Oct-2001
- *
- * @brief:  Provided initialization of the QMgr component and its subcomponents.
- *
- * 
- * @par
- * IXP400 SW Release version 2.0
- * 
- * -- Copyright Notice --
- * 
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- * 
- * @par
- * SPDX-License-Identifier:	BSD-3-Clause
- * @par
- * -- End of Copyright Notice --
-*/
-
-/*
- * System defined include files.
- */
-
-/*
- * User defined include files.
- */
-#include "IxOsal.h"
-#include "IxQMgr.h"
-#include "IxQMgrQCfg_p.h"
-#include "IxQMgrDispatcher_p.h"
-#include "IxQMgrLog_p.h"
-#include "IxQMgrQAccess_p.h"
-#include "IxQMgrDefines_p.h"
-#include "IxQMgrAqmIf_p.h"
-
-/*
- * Set to true if initialized
- * N.B. global so integration/unit tests can reinitialize
- */
-BOOL qMgrIsInitialized = false;
-
-/*
- * Function definitions.
- */
-IX_STATUS
-ixQMgrInit (void)
-{
-    if (qMgrIsInitialized)
-    {
-	IX_QMGR_LOG0("ixQMgrInit: IxQMgr already initialised\n");
-	return IX_FAIL;
-    }
-
-    /* Initialise the QCfg component */
-    ixQMgrQCfgInit ();
-
-    /* Initialise the Dispatcher component */
-    ixQMgrDispatcherInit ();
-
-    /* Initialise the Access component */
-    ixQMgrQAccessInit ();
-
-    /* Initialization complete */
-    qMgrIsInitialized = true;
-
-    return IX_SUCCESS;
-}
-
-IX_STATUS
-ixQMgrUnload (void)
-{
-    if (!qMgrIsInitialized)
-    {
-	return IX_FAIL;
-    }
-
-    /* Uninitialise the QCfg component */
-    ixQMgrQCfgUninit ();
-
-    /* Uninitialization complete */
-    qMgrIsInitialized = false;
-
-    return IX_SUCCESS;
-}
-
-void
-ixQMgrShow (void)
-{
-    IxQMgrQCfgStats *qCfgStats = NULL;
-    IxQMgrDispatcherStats *dispatcherStats = NULL;
-    int i;
-    UINT32 lowIntRegRead, upIntRegRead;
-
-    qCfgStats = ixQMgrQCfgStatsGet ();
-    dispatcherStats = ixQMgrDispatcherStatsGet ();
-    ixQMgrAqmIfQInterruptRegRead (IX_QMGR_QUELOW_GROUP, &lowIntRegRead);
-    ixQMgrAqmIfQInterruptRegRead (IX_QMGR_QUEUPP_GROUP, &upIntRegRead);
-    printf("Generic Stats........\n");
-    printf("=====================\n");
-    printf("Loop Run Count..........%u\n",dispatcherStats->loopRunCnt);
-    printf("Watermark set count.....%d\n", qCfgStats->wmSetCnt);
-    printf("===========================================\n");
-    printf("On the fly Interrupt Register Stats........\n");
-    printf("===========================================\n");
-    printf("Lower Interrupt Register............0x%08x\n",lowIntRegRead);
-    printf("Upper Interrupt Register............0x%08x\n",upIntRegRead);
-    printf("==============================================\n");
-    printf("Queue Specific Stats........\n");
-    printf("============================\n");
-
-    for (i=0; i<IX_QMGR_MAX_NUM_QUEUES; i++)
-    {
-	if (ixQMgrQIsConfigured(i))
-	{
-	    ixQMgrQShow(i);
-	}
-    }
-
-    printf("============================\n");
-}
-
-IX_STATUS
-ixQMgrQShow (IxQMgrQId qId)
-{
-    IxQMgrQCfgStats *qCfgStats = NULL;
-    IxQMgrDispatcherStats *dispatcherStats = NULL; 
-
-    if (!ixQMgrQIsConfigured(qId))
-    {
-	return IX_QMGR_Q_NOT_CONFIGURED;
-    }
-    
-    dispatcherStats = ixQMgrDispatcherStatsGet ();
-    qCfgStats = ixQMgrQCfgQStatsGet (qId);
-
-    printf("QId %d\n", qId);
-    printf("======\n");
-    printf("  IxQMgrQCfg Stats\n");
-    printf("    Name..................... \"%s\"\n", qCfgStats->qStats[qId].qName);
-    printf("    Size in words............ %u\n", qCfgStats->qStats[qId].qSizeInWords);
-    printf("    Entry size in words...... %u\n", qCfgStats->qStats[qId].qEntrySizeInWords);
-    printf("    Nearly empty watermark... %u\n", qCfgStats->qStats[qId].ne);
-    printf("    Nearly full watermark.... %u\n", qCfgStats->qStats[qId].nf);
-    printf("    Number of full entries... %u\n", qCfgStats->qStats[qId].numEntries);
-    printf("    Sram base address........ 0x%X\n", qCfgStats->qStats[qId].baseAddress);
-    printf("    Read pointer............. 0x%X\n", qCfgStats->qStats[qId].readPtr);
-    printf("    Write pointer............ 0x%X\n", qCfgStats->qStats[qId].writePtr);
-
-#ifndef NDEBUG
-    if (dispatcherStats->queueStats[qId].notificationEnabled)
-    {
-        char *localEvent = "none ????";
-        switch (dispatcherStats->queueStats[qId].srcSel)
-        {
-            case IX_QMGR_Q_SOURCE_ID_E:
-                localEvent = "Empty";
-                break;
-            case IX_QMGR_Q_SOURCE_ID_NE:
-                localEvent = "Nearly Empty";
-                break;
-            case IX_QMGR_Q_SOURCE_ID_NF:
-                localEvent = "Nearly Full";
-                break;
-            case IX_QMGR_Q_SOURCE_ID_F:
-                localEvent = "Full";
-                break;
-            case IX_QMGR_Q_SOURCE_ID_NOT_E:
-                localEvent = "Not Empty";
-                break;
-            case IX_QMGR_Q_SOURCE_ID_NOT_NE:
-                localEvent = "Not Nearly Empty";
-                break;
-            case IX_QMGR_Q_SOURCE_ID_NOT_NF:
-                localEvent = "Not Nearly Full";
-                break;
-            case IX_QMGR_Q_SOURCE_ID_NOT_F:
-                localEvent = "Not Full";
-                break;
-            default :
-                break;
-        }
-        printf("    Notifications localEvent...... %s\n", localEvent);
-    }
-    else
-    {
-        printf("    Notifications............ not enabled\n");
-    }
-    printf("  IxQMgrDispatcher Stats\n");
-    printf("    Callback count................%d\n",
-	  dispatcherStats->queueStats[qId].callbackCnt);
-    printf("    Priority change count.........%d\n",
-	  dispatcherStats->queueStats[qId].priorityChangeCnt);
-    printf("    Interrupt no callback count...%d\n",
-	  dispatcherStats->queueStats[qId].intNoCallbackCnt);
-    printf("    Interrupt lost callback count...%d\n",
-	  dispatcherStats->queueStats[qId].intLostCallbackCnt);
-#endif
-
-    return IX_SUCCESS;
-}
-
-
-
-
diff --git a/drivers/net/npe/IxQMgrQAccess.c b/drivers/net/npe/IxQMgrQAccess.c
deleted file mode 100644
index 13ee0f4f11..0000000000
--- a/drivers/net/npe/IxQMgrQAccess.c
+++ /dev/null
@@ -1,772 +0,0 @@
-/**
- * @file    IxQMgrQAccess.c
- *
- * @author Intel Corporation
- * @date    30-Oct-2001
- *
- * @brief   This file contains functions for putting entries on a queue and
- * removing entries from a queue.
- *
- * 
- * @par
- * IXP400 SW Release version 2.0
- * 
- * -- Copyright Notice --
- * 
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- * 
- * @par
- * SPDX-License-Identifier:	BSD-3-Clause
- * @par
- * -- End of Copyright Notice --
-*/
-
-/*
- * Inlines are compiled as function when this is defined.
- * N.B. Must be placed before #include of "IxQMgr.h"
- */
-#ifndef IXQMGR_H
-#    define IXQMGRQACCESS_C
-#else
-#    error
-#endif
-
-/*
- * System defined include files.
- */
-
-/*
- * User defined include files.
- */
-#include "IxQMgr.h"
-#include "IxQMgrAqmIf_p.h"
-#include "IxQMgrQAccess_p.h"
-#include "IxQMgrQCfg_p.h"
-#include "IxQMgrDefines_p.h"
-
-/*
- * Global variables and extern definitions
- */
-extern IxQMgrQInlinedReadWriteInfo ixQMgrQInlinedReadWriteInfo[];
-
-/*
- * Function definitions.
- */
-void
-ixQMgrQAccessInit (void)
-{   
-}
-
-IX_STATUS
-ixQMgrQReadWithChecks (IxQMgrQId qId,
-                       UINT32 *entry)
-{
-    IxQMgrQEntrySizeInWords entrySizeInWords;
-    IxQMgrQInlinedReadWriteInfo *infoPtr;
-
-    if (NULL == entry)
-    {
-	return IX_QMGR_PARAMETER_ERROR;
-    }
-
-    /* Check QId */
-    if (!ixQMgrQIsConfigured(qId))
-    {
-	return IX_QMGR_Q_NOT_CONFIGURED;
-    }
-
-    /* Get the q entry size in words */
-    entrySizeInWords = ixQMgrQEntrySizeInWordsGet (qId);
-
-    ixQMgrAqmIfQPop (qId, entrySizeInWords, entry);	    
-
-    /* reset the current read count if the counter wrapped around 
-    * (unsigned arithmetic)
-    */
-    infoPtr = &ixQMgrQInlinedReadWriteInfo[qId];
-    if (infoPtr->qReadCount-- > infoPtr->qSizeInEntries)
-    {
-	infoPtr->qReadCount = 0;
-    }
-
-    /* Check if underflow occurred on the read */
-    if (ixQMgrAqmIfUnderflowCheck (qId))
-    {
-	return IX_QMGR_Q_UNDERFLOW;
-    }
-    
-    return IX_SUCCESS;
-}
-
-/* this function reads the remaining of the q entry
- * for queues configured with many words.
- * (the first word of the entry is already read 
- * in the inlined function and the entry pointer already
- * incremented
- */
-IX_STATUS
-ixQMgrQReadMWordsMinus1 (IxQMgrQId qId,
-			 UINT32 *entry)
-{
-    IxQMgrQInlinedReadWriteInfo *infoPtr = &ixQMgrQInlinedReadWriteInfo[qId];
-    UINT32 entrySize = infoPtr->qEntrySizeInWords;
-    volatile UINT32 *qAccRegAddr = infoPtr->qAccRegAddr;
-    
-    while (--entrySize)
-    {
-	/* read the entry and accumulate the result */
-	*(++entry) = IX_OSAL_READ_LONG(++qAccRegAddr);
-    }
-    /* underflow is available for lower queues only */
-    if (qId < IX_QMGR_MIN_QUEUPP_QID)
-    {
-	/* get the queue status */
-	UINT32 status = IX_OSAL_READ_LONG(infoPtr->qUOStatRegAddr);
-	
-	/* check the underflow status */
-	if (status & infoPtr->qUflowStatBitMask)
-	{
-	    /* the queue is empty 
-	     *  clear the underflow status bit if it was set 
-	     */
-	    IX_OSAL_WRITE_LONG(infoPtr->qUOStatRegAddr,
-				 status & ~infoPtr->qUflowStatBitMask);
-	    return IX_QMGR_Q_UNDERFLOW;
-	}
-    }
-    return IX_SUCCESS;
-}
-
-IX_STATUS
-ixQMgrQWriteWithChecks (IxQMgrQId qId,
-                        UINT32 *entry)
-{
-    IxQMgrQEntrySizeInWords entrySizeInWords;
-    IxQMgrQInlinedReadWriteInfo *infoPtr;
-
-    if (NULL == entry)
-    {
-	return IX_QMGR_PARAMETER_ERROR;
-    }
-
-    /* Check QId */
-    if (!ixQMgrQIsConfigured(qId))
-    {
-	return IX_QMGR_Q_NOT_CONFIGURED;
-    }
-
-    /* Get the q entry size in words */
-    entrySizeInWords = ixQMgrQEntrySizeInWordsGet (qId);
-    
-    ixQMgrAqmIfQPush (qId, entrySizeInWords, entry);
-
-    /* reset the current read count if the counter wrapped around 
-    * (unsigned arithmetic)
-    */
-    infoPtr = &ixQMgrQInlinedReadWriteInfo[qId];
-    if (infoPtr->qWriteCount++ >= infoPtr->qSizeInEntries)
-    {
-	infoPtr->qWriteCount = infoPtr->qSizeInEntries;
-    }
-
-    /* Check if overflow occurred on the write*/
-    if (ixQMgrAqmIfOverflowCheck (qId))
-    {
-	return IX_QMGR_Q_OVERFLOW;
-    }
-         
-    return IX_SUCCESS;
-}
-
-IX_STATUS
-ixQMgrQPeek (IxQMgrQId qId,
-	     unsigned int entryIndex,
-	     UINT32 *entry)
-{
-    unsigned int numEntries;
-
-#ifndef NDEBUG
-    if ((NULL == entry) || (entryIndex >= IX_QMGR_Q_SIZE_INVALID))
-    {
-	return IX_QMGR_PARAMETER_ERROR;
-    }
-
-    if (!ixQMgrQIsConfigured(qId))
-    {
-	return IX_QMGR_Q_NOT_CONFIGURED;
-    }
-#endif
-    
-    if (IX_SUCCESS != ixQMgrQNumEntriesGet (qId, &numEntries))
-    {
-	return IX_FAIL;
-    }
-
-    if (entryIndex >= numEntries) /* entryIndex starts at 0 */
-    {
-	return IX_QMGR_ENTRY_INDEX_OUT_OF_BOUNDS;
-    }
-
-    return ixQMgrAqmIfQPeek (qId, entryIndex, entry);
-}
-
-IX_STATUS
-ixQMgrQPoke (IxQMgrQId qId,
-	     unsigned entryIndex,
-	     UINT32 *entry)
-{
-    unsigned int numEntries;
-
-#ifndef NDEBUG
-    if ((NULL == entry) || (entryIndex > 128))
-    {
-	return IX_QMGR_PARAMETER_ERROR;
-    }
-
-    if (!ixQMgrQIsConfigured(qId))
-    {
-	return IX_QMGR_Q_NOT_CONFIGURED;
-    }
-#endif
-        
-    if (IX_SUCCESS != ixQMgrQNumEntriesGet (qId, &numEntries))
-    {
-	return IX_FAIL;
-    }
-
-    if (numEntries < (entryIndex + 1)) /* entryIndex starts at 0 */
-    {
-	return IX_QMGR_ENTRY_INDEX_OUT_OF_BOUNDS;
-    }
-
-    return ixQMgrAqmIfQPoke (qId, entryIndex, entry);
-}
-
-IX_STATUS
-ixQMgrQStatusGetWithChecks (IxQMgrQId qId,
-                            IxQMgrQStatus *qStatus)
-{
-    if (NULL == qStatus)
-    {
-	return IX_QMGR_PARAMETER_ERROR;
-    }
-   
-    if (!ixQMgrQIsConfigured (qId)) 
-    {
-        return IX_QMGR_Q_NOT_CONFIGURED;
-    }
-
-    ixQMgrAqmIfQueStatRead (qId, qStatus);
-
-    return IX_SUCCESS;
-}
-
-IX_STATUS
-ixQMgrQNumEntriesGet (IxQMgrQId qId,
-		      unsigned *numEntriesPtr)
-{
-    UINT32 qPtrs;
-    UINT32 qStatus;
-    unsigned numEntries;
-    IxQMgrQInlinedReadWriteInfo *infoPtr;
-
-
-#ifndef NDEBUG
-    if (NULL == numEntriesPtr)
-    {
-	return IX_QMGR_PARAMETER_ERROR;
-    }
-
-    /* Check QId */
-    if (!ixQMgrQIsConfigured(qId))
-    {
-	return IX_QMGR_Q_NOT_CONFIGURED;
-    }
-#endif
-
-    /* get fast access data */
-    infoPtr = &ixQMgrQInlinedReadWriteInfo[qId];
-
-    /* get snapshot */
-    qPtrs = IX_OSAL_READ_LONG(infoPtr->qConfigRegAddr);
-
-    /* Mod subtraction of pointers to get number of words in Q. */
-    numEntries = (qPtrs - (qPtrs >> 7)) & 0x7f;
-  
-    if (numEntries == 0)
-    {
-	/* 
-	 * Could mean either full or empty queue
-	 * so look at status
-	 */
-	ixQMgrAqmIfQueStatRead (qId, &qStatus);
-
-	if (qId < IX_QMGR_MIN_QUEUPP_QID)
-	{
-	    if (qStatus & IX_QMGR_Q_STATUS_E_BIT_MASK)
-	    {
-		/* Empty */
-		*numEntriesPtr = 0;
-	    }
-	    else if (qStatus & IX_QMGR_Q_STATUS_F_BIT_MASK)
-	    {
-		/* Full */
-		*numEntriesPtr = infoPtr->qSizeInEntries;
-	    }
-	    else
-	    {	    
-		/* 
-		 * Queue status and read/write pointers are volatile.
-		 * The queue state has changed since we took the
-		 * snapshot of the read and write pointers.
-		 * Client can retry if they wish
-		 */
-		*numEntriesPtr = 0;
-		return IX_QMGR_WARNING;
-	    }
-	}
-	else /* It is an upper queue which does not have an empty status bit maintained */
-	{
-	    if (qStatus & IX_QMGR_Q_STATUS_F_BIT_MASK)
-	    {
-		/* The queue is Full at the time of snapshot. */
-		*numEntriesPtr = infoPtr->qSizeInEntries;
-	    }
-	    else
-	    {
-	       /* The queue is either empty, either moving,
-	        * Client can retry if they wish
-	        */
-		*numEntriesPtr = 0;
-	        return IX_QMGR_WARNING;
-	    }
-	}
-    }
-    else
-    {
-	*numEntriesPtr = (numEntries / infoPtr->qEntrySizeInWords) & (infoPtr->qSizeInEntries - 1);
-    }
-    
-    return IX_SUCCESS;
-}
-
-#if defined(__wince) && defined(NO_INLINE_APIS)
-
-PUBLIC IX_STATUS
-ixQMgrQRead (IxQMgrQId qId,
-      UINT32 *entryPtr)
-{
-    extern IxQMgrQInlinedReadWriteInfo ixQMgrQInlinedReadWriteInfo[];
-    IxQMgrQInlinedReadWriteInfo *infoPtr = &ixQMgrQInlinedReadWriteInfo[qId];
-    UINT32 entry, entrySize;
-
-    /* get a new entry */
-    entrySize = infoPtr->qEntrySizeInWords;
-    entry = IX_OSAL_READ_LONG(infoPtr->qAccRegAddr);
-
-    if (entrySize != IX_QMGR_Q_ENTRY_SIZE1)
-    { 
-    *entryPtr = entry;
-  /* process the remaining part of the entry */
-   return ixQMgrQReadMWordsMinus1(qId, entryPtr);
-    }
-
-    /* underflow is available for lower queues only */
-    if (qId < IX_QMGR_MIN_QUEUPP_QID)
-    {
- /* the counter of queue entries is decremented. In happy 
-    * day scenario there are many entries in the queue
-  * and the counter does not reach zero.
-  */
-     if (infoPtr->qReadCount-- == 0)
- {
-       /* There is maybe no entry in the queue
-      * qReadCount is now negative, but will be corrected before
-      * the function returns.
-         */
-     UINT32 qPtrs; /* queue internal pointers */
-
-     /* when a queue is empty, the hw guarantees to return 
-       * a null value. If the value is not null, the queue is
-      * not empty.
-        */
-     if (entry == 0)
-     {
-       /* get the queue status */
-      UINT32 status = IX_OSAL_READ_LONG(infoPtr->qUOStatRegAddr);
-   
-        /* check the underflow status */
-        if (status & infoPtr->qUflowStatBitMask)
-        {
-           /* the queue is empty 
-          *  clear the underflow status bit if it was set 
-            */
-          IX_OSAL_WRITE_LONG(infoPtr->qUOStatRegAddr,
-                    status & ~infoPtr->qUflowStatBitMask);
-         *entryPtr = 0;
-          infoPtr->qReadCount = 0;
-            return IX_QMGR_Q_UNDERFLOW;
-     }
-       }
-       /* store the result */
-      *entryPtr = entry;
-
-      /* No underflow occured : someone is filling the queue
-       * or the queue contains null entries.
-       * The current counter needs to be
-       * updated from the current number of entries in the queue
-       */
-
-     /* get snapshot of queue pointers */
-        qPtrs = IX_OSAL_READ_LONG(infoPtr->qConfigRegAddr);
-
-       /* Mod subtraction of pointers to get number of words in Q. */
-      qPtrs = (qPtrs - (qPtrs >> 7)) & 0x7f; 
-  
-       if (qPtrs == 0)
-     {
-       /* no entry in the queue */
-     infoPtr->qReadCount = 0;
-        }
-       else
-        {
-       /* convert the number of words inside the queue
-      * to a number of entries 
-       */
-     infoPtr->qReadCount = qPtrs & (infoPtr->qSizeInEntries - 1);
-        }
-       return IX_SUCCESS;
-  }
-    }
-    *entryPtr = entry;
-    return IX_SUCCESS;
-}
-
-PUBLIC IX_STATUS
-ixQMgrQBurstRead (IxQMgrQId qId,
-          UINT32 numEntries,
-          UINT32 *entries)
-{
-    extern IxQMgrQInlinedReadWriteInfo ixQMgrQInlinedReadWriteInfo[];
-    IxQMgrQInlinedReadWriteInfo *infoPtr = &ixQMgrQInlinedReadWriteInfo[qId];
-    UINT32 nullCheckEntry;
-
-    if (infoPtr->qEntrySizeInWords == IX_QMGR_Q_ENTRY_SIZE1)
-    {
-    volatile UINT32 *qAccRegAddr = infoPtr->qAccRegAddr;
-
-    /* the code is optimized to take care of data dependencies:
-  * Durig a read, there are a few cycles needed to get the 
-   * read complete. During these cycles, it is poossible to
-    * do some CPU, e.g. increment pointers and decrement 
-   * counters.
-     */
-
- /* fetch a queue entry */
-   nullCheckEntry = IX_OSAL_READ_LONG(infoPtr->qAccRegAddr);
-
- /* iterate the specified number of queue entries */ 
-    while (--numEntries)
-    {
-       /* check the result of the previous read */
-     if (nullCheckEntry == 0)
-        {
-       /* if we read a NULL entry, stop. We have underflowed */
-        break;
-      }
-       else
-        {
-       /* write the entry */
-       *entries = nullCheckEntry;
-      /* fetch next entry */
-      nullCheckEntry = IX_OSAL_READ_LONG(qAccRegAddr);
-      /* increment the write address */
-       entries++;
-      }
-   }
-   /* write the pre-fetched entry */
-   *entries = nullCheckEntry;
-    }
-    else
-    {
-    IxQMgrQEntrySizeInWords entrySizeInWords = infoPtr->qEntrySizeInWords;
-  /* read the specified number of queue entries */
-    nullCheckEntry = 0;
- while (numEntries--)
-    {
-       int i;
-
-      for (i = 0; i < entrySizeInWords; i++)
-      {
-       *entries = IX_OSAL_READ_LONG(infoPtr->qAccRegAddr + i);
-       nullCheckEntry |= *entries++;
-       }
-
-       /* if we read a NULL entry, stop. We have underflowed */
-        if (nullCheckEntry == 0)
-        {
-       break;
-      }
-       nullCheckEntry = 0;
- }
-    }
-
-    /* reset the current read count : next access to the read function 
-     * will force a underflow status check 
-     */
-    infoPtr->qWriteCount = 0;
-
-    /* Check if underflow occurred on the read */
-    if (nullCheckEntry == 0 && qId < IX_QMGR_MIN_QUEUPP_QID)
-    {
-  /* get the queue status */
-  UINT32 status = IX_OSAL_READ_LONG(infoPtr->qUOStatRegAddr);
-
-   if (status & infoPtr->qUflowStatBitMask)
-    {
-       /* clear the underflow status bit if it was set */
-      IX_OSAL_WRITE_LONG(infoPtr->qUOStatRegAddr,
-                status & ~infoPtr->qUflowStatBitMask);
-     return IX_QMGR_Q_UNDERFLOW;
- }
-    }
-
-    return IX_SUCCESS;
-}
-
-PUBLIC IX_STATUS
-ixQMgrQWrite (IxQMgrQId qId,
-         UINT32 *entry)
-{
-    extern IxQMgrQInlinedReadWriteInfo ixQMgrQInlinedReadWriteInfo[];
-    IxQMgrQInlinedReadWriteInfo *infoPtr = &ixQMgrQInlinedReadWriteInfo[qId];
-    UINT32 entrySize;
-
-    /* write the entry */
-    IX_OSAL_WRITE_LONG(infoPtr->qAccRegAddr, *entry);
-    entrySize = infoPtr->qEntrySizeInWords;
-
-    if (entrySize != IX_QMGR_Q_ENTRY_SIZE1)
-    {   
-    /* process the remaining part of the entry */
-   volatile UINT32 *qAccRegAddr = infoPtr->qAccRegAddr;
-    while (--entrySize)
- {
-       ++entry;
-        IX_OSAL_WRITE_LONG(++qAccRegAddr, *entry);
-    }
-   entrySize = infoPtr->qEntrySizeInWords;
-    }
-
-    /* overflow is available for lower queues only */
-    if (qId < IX_QMGR_MIN_QUEUPP_QID)
-    {   
-  UINT32 qSize = infoPtr->qSizeInEntries;
- /* increment the current number of entries in the queue
-  * and check for overflow 
-   */
- if (infoPtr->qWriteCount++ == qSize)
-    {
-       /* the queue may have overflow */
-       UINT32 qPtrs; /* queue internal pointers */
-  
-       /* get the queue status */
-      UINT32 status = IX_OSAL_READ_LONG(infoPtr->qUOStatRegAddr);
-
-       /* read the status twice because the status may 
-         * not be immediately ready after the write operation
-        */
-     if ((status & infoPtr->qOflowStatBitMask) ||
-        ((status = IX_OSAL_READ_LONG(infoPtr->qUOStatRegAddr))
-         & infoPtr->qOflowStatBitMask))
-     {
-       /* the queue is full, clear the overflow status
-      *  bit if it was set 
-       */
-     IX_OSAL_WRITE_LONG(infoPtr->qUOStatRegAddr,
-                    status & ~infoPtr->qOflowStatBitMask);
-     infoPtr->qWriteCount = infoPtr->qSizeInEntries;
-     return IX_QMGR_Q_OVERFLOW;
-      }
-       /* No overflow occured : someone is draining the queue
-       * and the current counter needs to be
-       * updated from the current number of entries in the queue
-       */
-
-     /* get q pointer snapshot */
-        qPtrs = IX_OSAL_READ_LONG(infoPtr->qConfigRegAddr);
-
-       /* Mod subtraction of pointers to get number of words in Q. */
-      qPtrs = (qPtrs - (qPtrs >> 7)) & 0x7f; 
-
-     if (qPtrs == 0)
-     {
-       /* the queue may be full at the time of the 
-         * snapshot. Next access will check 
-         * the overflow status again.
-        */
-     infoPtr->qWriteCount = qSize;
-       }
-       else 
-       {
-       /* convert the number of words to a number of entries */
-        if (entrySize == IX_QMGR_Q_ENTRY_SIZE1)
-     {
-           infoPtr->qWriteCount = qPtrs & (qSize - 1);
-     }
-       else
-        {
-           infoPtr->qWriteCount = (qPtrs / entrySize) & (qSize - 1);
-       }
-       }
-   }
-    }
-    return IX_SUCCESS;
-}
-
-PUBLIC IX_STATUS
-ixQMgrQBurstWrite (IxQMgrQId qId,
-          unsigned numEntries,
-        UINT32 *entries)
-{
-    extern IxQMgrQInlinedReadWriteInfo ixQMgrQInlinedReadWriteInfo[];
-    IxQMgrQInlinedReadWriteInfo *infoPtr = &ixQMgrQInlinedReadWriteInfo[qId];
-    UINT32 status;
-
-    /* update the current write count */
-    infoPtr->qWriteCount += numEntries;
-
-    if (infoPtr->qEntrySizeInWords == IX_QMGR_Q_ENTRY_SIZE1)
-    {
-    volatile UINT32 *qAccRegAddr = infoPtr->qAccRegAddr;
-    while (numEntries--)
-    {
-       IX_OSAL_WRITE_LONG(qAccRegAddr, *entries);
-        entries++;
-  }
-    }
-    else
-    {
- IxQMgrQEntrySizeInWords entrySizeInWords = infoPtr->qEntrySizeInWords;
-  int i;
-
-  /* write each queue entry */
-    while (numEntries--)
-    {
-       /* write the queueEntrySize number of words for each entry */
-       for (i = 0; i < entrySizeInWords; i++)
-      {
-       IX_OSAL_WRITE_LONG((infoPtr->qAccRegAddr + i), *entries);
-     entries++;
-      }
-   }
-    }
-
-    /* check if the write count overflows */
-    if (infoPtr->qWriteCount > infoPtr->qSizeInEntries)
-    {
-  /* reset the current write count */
- infoPtr->qWriteCount = infoPtr->qSizeInEntries;
-    }
-
-    /* Check if overflow occurred on the write operation */
-    if (qId < IX_QMGR_MIN_QUEUPP_QID)
-    {
-   /* get the queue status */
-  status = IX_OSAL_READ_LONG(infoPtr->qUOStatRegAddr);
-
-  /* read the status twice because the status may 
-     * not be ready at the time of the write
-     */
- if ((status & infoPtr->qOflowStatBitMask) ||
-        ((status = IX_OSAL_READ_LONG(infoPtr->qUOStatRegAddr))
-         & infoPtr->qOflowStatBitMask))
- {
-       /* clear the underflow status bit if it was set */
-      IX_OSAL_WRITE_LONG(infoPtr->qUOStatRegAddr,
-                status & ~infoPtr->qOflowStatBitMask);
-     return IX_QMGR_Q_OVERFLOW;
-  }
-    }
-
-    return IX_SUCCESS;
-}
-
-PUBLIC IX_STATUS
-ixQMgrQStatusGet (IxQMgrQId qId,
-          IxQMgrQStatus *qStatus)
-{
-    /* read the status of a queue in the range 0-31 */
-    if (qId < IX_QMGR_MIN_QUEUPP_QID)
-    {
-  extern UINT32 ixQMgrAqmIfQueLowStatRegAddr[];
-   extern UINT32 ixQMgrAqmIfQueLowStatBitsOffset[];
-    extern UINT32 ixQMgrAqmIfQueLowStatBitsMask;
-    extern IxQMgrQInlinedReadWriteInfo ixQMgrQInlinedReadWriteInfo[];
-    IxQMgrQInlinedReadWriteInfo *infoPtr = &ixQMgrQInlinedReadWriteInfo[qId];
-   volatile UINT32 *lowStatRegAddr = (UINT32*)ixQMgrAqmIfQueLowStatRegAddr[qId];
-   volatile UINT32 *qUOStatRegAddr = infoPtr->qUOStatRegAddr;
-
-  UINT32 lowStatBitsOffset = ixQMgrAqmIfQueLowStatBitsOffset[qId];
-    UINT32 lowStatBitsMask   = ixQMgrAqmIfQueLowStatBitsMask;
-   UINT32 underflowBitMask  = infoPtr->qUflowStatBitMask;
-  UINT32 overflowBitMask   = infoPtr->qOflowStatBitMask;
-
-  /* read the status register for this queue */
-   *qStatus = IX_OSAL_READ_LONG(lowStatRegAddr);
- /* mask out the status bits relevant only to this queue */
-  *qStatus = (*qStatus >> lowStatBitsOffset) & lowStatBitsMask;
-
-   /* Check if the queue has overflowed */
- if (IX_OSAL_READ_LONG(qUOStatRegAddr) & overflowBitMask)
-  {
-       /* clear the overflow status bit if it was set */
-       IX_OSAL_WRITE_LONG(qUOStatRegAddr,
-                 (IX_OSAL_READ_LONG(qUOStatRegAddr) &
-               ~overflowBitMask));
-       *qStatus |= IX_QMGR_Q_STATUS_OF_BIT_MASK;
-   }
-
-   /* Check if the queue has underflowed */
-        if (IX_OSAL_READ_LONG(qUOStatRegAddr) & underflowBitMask)
- {
-       /* clear the underflow status bit if it was set */
-      IX_OSAL_WRITE_LONG(qUOStatRegAddr,
-                 (IX_OSAL_READ_LONG(qUOStatRegAddr) &
-               ~underflowBitMask));
-      *qStatus |= IX_QMGR_Q_STATUS_UF_BIT_MASK;
-   }
-    }
-    else /* read status of a queue in the range 32-63 */
-    {
- extern UINT32 ixQMgrAqmIfQueUppStat0RegAddr;
-    extern UINT32 ixQMgrAqmIfQueUppStat1RegAddr;
-    extern UINT32 ixQMgrAqmIfQueUppStat0BitMask[];
-  extern UINT32 ixQMgrAqmIfQueUppStat1BitMask[];
-
-  volatile UINT32 *qNearEmptyStatRegAddr = (UINT32*)ixQMgrAqmIfQueUppStat0RegAddr;
-    volatile UINT32 *qFullStatRegAddr      = (UINT32*)ixQMgrAqmIfQueUppStat1RegAddr;
-    int maskIndex = qId - IX_QMGR_MIN_QUEUPP_QID;
-   UINT32 qNearEmptyStatBitMask = ixQMgrAqmIfQueUppStat0BitMask[maskIndex];
-    UINT32 qFullStatBitMask      = ixQMgrAqmIfQueUppStat1BitMask[maskIndex];
-
-    /* Reset the status bits */
- *qStatus = 0;
-
-   /* Check if the queue is nearly empty */
-    if (IX_OSAL_READ_LONG(qNearEmptyStatRegAddr) & qNearEmptyStatBitMask)
- {
-       *qStatus |= IX_QMGR_Q_STATUS_NE_BIT_MASK;
-   }
-
-   /* Check if the queue is full */
-    if (IX_OSAL_READ_LONG(qFullStatRegAddr) & qFullStatBitMask)
-   {
-       *qStatus |= IX_QMGR_Q_STATUS_F_BIT_MASK;
-    }
-    }
-    return IX_SUCCESS;
-}
-#endif /* def NO_INLINE_APIS */
diff --git a/drivers/net/npe/IxQMgrQCfg.c b/drivers/net/npe/IxQMgrQCfg.c
deleted file mode 100644
index b64bb2dd90..0000000000
--- a/drivers/net/npe/IxQMgrQCfg.c
+++ /dev/null
@@ -1,519 +0,0 @@
-/**
- * @file    QMgrQCfg.c
- *
- * @author Intel Corporation
- * @date    30-Oct-2001
- * 
- * @brief   This modules provides an interface for setting up the static
- * configuration of AQM queues.This file contains the following
- * functions:
- *
- * 
- * 
- * @par
- * IXP400 SW Release version 2.0
- * 
- * -- Copyright Notice --
- * 
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- * 
- * @par
- * SPDX-License-Identifier:	BSD-3-Clause
- * @par
- * -- End of Copyright Notice --
-*/
-
-/*
- * System defined include files.
- */
-
-/*
- * User defined include files.
- */
-#include "IxOsal.h"
-#include "IxQMgr.h"
-#include "IxQMgrAqmIf_p.h"
-#include "IxQMgrQCfg_p.h"
-#include "IxQMgrDefines_p.h"
-
-/*
- * #defines and macros used in this file.
- */
-
-#define IX_QMGR_MIN_ENTRY_SIZE_IN_WORDS 16
-
-/* Total size of SRAM */
-#define IX_QMGR_AQM_SRAM_SIZE_IN_BYTES 0x4000
-
-/*
- * Check that qId is a valid queue identifier. This is provided to
- * make the code easier to read.
- */
-#define IX_QMGR_QID_IS_VALID(qId) \
-(((qId) >= (IX_QMGR_MIN_QID)) && ((qId) <= (IX_QMGR_MAX_QID)))
-
-/*
- * Typedefs whose scope is limited to this file.
- */
-
-/*
- * This struct describes an AQM queue.
- * N.b. bufferSizeInWords and qEntrySizeInWords are stored in the queue
- * as these are requested by Access in the data path. sizeInEntries is
- * not required by the data path so it can be calculated dynamically.
- * 
- */
-typedef struct
-{
-    char qName[IX_QMGR_MAX_QNAME_LEN+1];       /* Textual description of a queue*/
-    IxQMgrQSizeInWords qSizeInWords;           /* The number of words in the queue */
-    IxQMgrQEntrySizeInWords qEntrySizeInWords; /* Number of words per queue entry*/
-    BOOL isConfigured;                         /* This flag is true if the queue has
-                                                *   been configured
-                                                */
-} IxQMgrCfgQ;
-
-/*
- * Variable declarations global to this file. Externs are followed by
- * statics.
- */
-
-extern UINT32 * ixQMgrAqmIfQueAccRegAddr[]; 
-
-/* Store data required to inline read and write access
- */
-IxQMgrQInlinedReadWriteInfo ixQMgrQInlinedReadWriteInfo[IX_QMGR_MAX_NUM_QUEUES];
-
-static IxQMgrCfgQ cfgQueueInfo[IX_QMGR_MAX_NUM_QUEUES];
-
-/* This pointer holds the starting address of AQM SRAM not used by
- * the AQM queues.
- */
-static UINT32 freeSramAddress=0;
-
-/* 4 words of zeroed memory for inline access */
-static UINT32 zeroedPlaceHolder[4] = { 0, 0, 0, 0 };
-
-static BOOL cfgInitialized = false;
-
-static IxOsalMutex ixQMgrQCfgMutex;
-
-/*
- * Statistics
- */
-static IxQMgrQCfgStats stats;
-
-/*
- * Function declarations
- */
-PRIVATE BOOL
-watermarkLevelIsOk (IxQMgrQId qId, IxQMgrWMLevel level);
-
-PRIVATE BOOL
-qSizeInWordsIsOk (IxQMgrQSizeInWords qSize);
-
-PRIVATE BOOL
-qEntrySizeInWordsIsOk (IxQMgrQEntrySizeInWords entrySize);
-
-/*
- * Function definitions.
- */
-void
-ixQMgrQCfgInit (void)
-{
-    int loopIndex;
-    
-    for (loopIndex=0; loopIndex < IX_QMGR_MAX_NUM_QUEUES;loopIndex++)
-    {
-	/* info for code inlining */
-	ixQMgrAqmIfQueAccRegAddr[loopIndex] = zeroedPlaceHolder;
-
-	/* info for code inlining */
-	ixQMgrQInlinedReadWriteInfo[loopIndex].qReadCount = 0;
-	ixQMgrQInlinedReadWriteInfo[loopIndex].qWriteCount = 0;
-	ixQMgrQInlinedReadWriteInfo[loopIndex].qAccRegAddr = zeroedPlaceHolder;
-	ixQMgrQInlinedReadWriteInfo[loopIndex].qUOStatRegAddr = zeroedPlaceHolder;
-	ixQMgrQInlinedReadWriteInfo[loopIndex].qUflowStatBitMask = 0;
-	ixQMgrQInlinedReadWriteInfo[loopIndex].qOflowStatBitMask = 0;
-	ixQMgrQInlinedReadWriteInfo[loopIndex].qEntrySizeInWords = 0;
-	ixQMgrQInlinedReadWriteInfo[loopIndex].qSizeInEntries = 0;
-	ixQMgrQInlinedReadWriteInfo[loopIndex].qConfigRegAddr = zeroedPlaceHolder;
-   }
-
-    /* Initialise the AqmIf component */
-    ixQMgrAqmIfInit ();
-   
-    /* Reset all queues to have queue name = NULL, entry size = 0 and
-     * isConfigured = false
-     */
-    for (loopIndex=0; loopIndex < IX_QMGR_MAX_NUM_QUEUES;loopIndex++)
-    {
-	strcpy (cfgQueueInfo[loopIndex].qName, "");
-	cfgQueueInfo[loopIndex].qSizeInWords = 0;
-	cfgQueueInfo[loopIndex].qEntrySizeInWords = 0;
-	cfgQueueInfo[loopIndex].isConfigured = false;
-
-	/* Statistics */
-	stats.qStats[loopIndex].isConfigured = false;
-	stats.qStats[loopIndex].qName = cfgQueueInfo[loopIndex].qName;
-    }
-
-    /* Statistics */
-    stats.wmSetCnt = 0;
-
-    ixQMgrAqmIfSramBaseAddressGet (&freeSramAddress);
-    
-    ixOsalMutexInit(&ixQMgrQCfgMutex);
-
-    cfgInitialized = true;
-}
-
-void
-ixQMgrQCfgUninit (void)
-{
-    cfgInitialized = false;
-
-    /* Uninitialise the AqmIf component */
-    ixQMgrAqmIfUninit ();
-}
-
-IX_STATUS
-ixQMgrQConfig (char *qName,
-	      IxQMgrQId qId,
-	      IxQMgrQSizeInWords qSizeInWords,
-	      IxQMgrQEntrySizeInWords qEntrySizeInWords)
-{
-    UINT32 aqmLocalBaseAddress;
-
-    if (!cfgInitialized)
-    {
-        return IX_FAIL;
-    }
-    
-    if (!IX_QMGR_QID_IS_VALID(qId))
-    {
-	return IX_QMGR_INVALID_Q_ID;
-    }
-    
-    else if (NULL == qName)
-    {
-	return IX_QMGR_PARAMETER_ERROR;
-    }
-    
-    else if (strlen (qName) > IX_QMGR_MAX_QNAME_LEN)
-    {
-	return IX_QMGR_PARAMETER_ERROR;
-    }
-
-    else if (!qSizeInWordsIsOk (qSizeInWords))
-    {
-	return IX_QMGR_INVALID_QSIZE;
-    }
-
-    else if (!qEntrySizeInWordsIsOk (qEntrySizeInWords))
-    {
-	return IX_QMGR_INVALID_Q_ENTRY_SIZE;
-    }
-    
-    else if (cfgQueueInfo[qId].isConfigured)
-    {
-	return IX_QMGR_Q_ALREADY_CONFIGURED;
-    }
-   
-    ixOsalMutexLock(&ixQMgrQCfgMutex, IX_OSAL_WAIT_FOREVER);
-
-    /* Write the config register */
-    ixQMgrAqmIfQueCfgWrite (qId,
-			   qSizeInWords,
-			   qEntrySizeInWords,
-			   freeSramAddress);
-
-
-    strcpy (cfgQueueInfo[qId].qName, qName);
-    cfgQueueInfo[qId].qSizeInWords = qSizeInWords;
-    cfgQueueInfo[qId].qEntrySizeInWords = qEntrySizeInWords;
-
-    /* store pre-computed information in the same cache line
-     * to facilitate inlining of QRead and QWrite functions 
-     * in IxQMgr.h
-     */
-    ixQMgrQInlinedReadWriteInfo[qId].qReadCount = 0;
-    ixQMgrQInlinedReadWriteInfo[qId].qWriteCount = 0;
-    ixQMgrQInlinedReadWriteInfo[qId].qEntrySizeInWords = qEntrySizeInWords;
-    ixQMgrQInlinedReadWriteInfo[qId].qSizeInEntries = 
-		(UINT32)qSizeInWords / (UINT32)qEntrySizeInWords;
-
-    /* Calculate the new freeSramAddress from the size of the queue
-     * currently being configured.
-     */
-    freeSramAddress += (qSizeInWords * IX_QMGR_NUM_BYTES_PER_WORD);
-
-    /* Get the virtual SRAM address */
-    ixQMgrAqmIfBaseAddressGet (&aqmLocalBaseAddress);
-
-    IX_OSAL_ASSERT((freeSramAddress - (aqmLocalBaseAddress + (IX_QMGR_QUEBUFFER_SPACE_OFFSET))) <=
-	      IX_QMGR_QUE_BUFFER_SPACE_SIZE);
-
-    /* The queue is now configured */
-    cfgQueueInfo[qId].isConfigured = true;
-
-    ixOsalMutexUnlock(&ixQMgrQCfgMutex);
-
-#ifndef NDEBUG
-    /* Update statistics */
-    stats.qStats[qId].isConfigured = true;
-    stats.qStats[qId].qName = cfgQueueInfo[qId].qName;
-#endif
-    return IX_SUCCESS;
-}
-
-IxQMgrQSizeInWords
-ixQMgrQSizeInWordsGet (IxQMgrQId qId)
-{
-    /* No parameter checking as this is used on the data path */
-    return (cfgQueueInfo[qId].qSizeInWords);
-}
-
-IX_STATUS
-ixQMgrQSizeInEntriesGet (IxQMgrQId qId,
-			 unsigned *qSizeInEntries)
-{
-    if (!ixQMgrQIsConfigured(qId))
-    {
-        return IX_QMGR_Q_NOT_CONFIGURED;
-    }
-
-    if(NULL == qSizeInEntries)
-    {
-        return IX_QMGR_PARAMETER_ERROR;
-    }
-
-    *qSizeInEntries = (UINT32)(cfgQueueInfo[qId].qSizeInWords) /
-        (UINT32)cfgQueueInfo[qId].qEntrySizeInWords;
-
-    return IX_SUCCESS;
-}
-
-IxQMgrQEntrySizeInWords
-ixQMgrQEntrySizeInWordsGet (IxQMgrQId qId)
-{
-    /* No parameter checking as this is used on the data path */
-    return (cfgQueueInfo[qId].qEntrySizeInWords);
-}
-
-IX_STATUS
-ixQMgrWatermarkSet (IxQMgrQId qId,
-		    IxQMgrWMLevel ne,
-		    IxQMgrWMLevel nf)
-{    
-    IxQMgrQStatus qStatusOnEntry;/* The queue status on entry/exit */
-    IxQMgrQStatus qStatusOnExit; /* to this function               */
-
-    if (!ixQMgrQIsConfigured(qId))
-    {
-        return IX_QMGR_Q_NOT_CONFIGURED;
-    }
-
-    if (!watermarkLevelIsOk (qId, ne))
-    {
-	return IX_QMGR_INVALID_Q_WM;
-    }
-
-    if (!watermarkLevelIsOk (qId, nf))
-    {
-	return IX_QMGR_INVALID_Q_WM;
-    }
-
-    /* Get the current queue status */
-    ixQMgrAqmIfQueStatRead (qId, &qStatusOnEntry);
-
-#ifndef NDEBUG
-    /* Update statistics */
-    stats.wmSetCnt++;
-#endif
-
-    ixQMgrAqmIfWatermarkSet (qId,
-			    ne,
-			    nf);
-
-    /* Get the current queue status */
-    ixQMgrAqmIfQueStatRead (qId, &qStatusOnExit);
-  
-    /* If the status has changed return a warning */
-    if (qStatusOnEntry != qStatusOnExit)
-    {
-	return IX_QMGR_WARNING;
-    }
-
-    return IX_SUCCESS;
-}
-
-IX_STATUS
-ixQMgrAvailableSramAddressGet (UINT32 *address,
-			      unsigned *sizeOfFreeRam)
-{
-    UINT32 aqmLocalBaseAddress;
-
-    if ((NULL == address)||(NULL == sizeOfFreeRam)) 
-    {
-	return IX_QMGR_PARAMETER_ERROR;
-    }
-    if (!cfgInitialized)
-    {
-	return IX_FAIL;
-    }
-
-    *address = freeSramAddress;
-
-    /* Get the virtual SRAM address */
-    ixQMgrAqmIfBaseAddressGet (&aqmLocalBaseAddress);
-
-    /* 
-     * Calculate the size in bytes of free sram 
-     * i.e. current free SRAM virtual pointer from
-     *      (base + total size)
-     */
-    *sizeOfFreeRam = 
-	(aqmLocalBaseAddress +
-	IX_QMGR_AQM_SRAM_SIZE_IN_BYTES) -
-	freeSramAddress;
-
-    if (0 == *sizeOfFreeRam)
-    {
-	return IX_QMGR_NO_AVAILABLE_SRAM;
-    }
-
-    return IX_SUCCESS;
-}
-
-BOOL
-ixQMgrQIsConfigured (IxQMgrQId qId)
-{
-    if (!IX_QMGR_QID_IS_VALID(qId))
-    {
-	return false;
-    }
-
-    return cfgQueueInfo[qId].isConfigured;
-}
-
-IxQMgrQCfgStats*
-ixQMgrQCfgStatsGet (void)
-{
-    return &stats;
-}
-
-IxQMgrQCfgStats*
-ixQMgrQCfgQStatsGet (IxQMgrQId qId)
-{
-    unsigned int ne;
-    unsigned int nf;
-    UINT32 baseAddress;
-    UINT32 readPtr;
-    UINT32 writePtr;
-
-    stats.qStats[qId].qSizeInWords = cfgQueueInfo[qId].qSizeInWords;
-    stats.qStats[qId].qEntrySizeInWords = cfgQueueInfo[qId].qEntrySizeInWords;
-    
-    if (IX_SUCCESS != ixQMgrQNumEntriesGet (qId, &stats.qStats[qId].numEntries))
-    {
-        if (IX_QMGR_WARNING != ixQMgrQNumEntriesGet (qId, &stats.qStats[qId].numEntries))
-        {
-	   IX_QMGR_LOG_WARNING1("Failed to get the number of entries in queue.... %d\n", qId);
-        }
-    }
-
-    ixQMgrAqmIfQueCfgRead (qId,
-			   stats.qStats[qId].numEntries,
-			   &baseAddress,
-			   &ne,
-			   &nf,
-			   &readPtr,
-			   &writePtr);
-        
-    stats.qStats[qId].baseAddress = baseAddress;
-    stats.qStats[qId].ne = ne;
-    stats.qStats[qId].nf = nf;
-    stats.qStats[qId].readPtr = readPtr;
-    stats.qStats[qId].writePtr = writePtr;
-
-    return &stats;
-}
-
-/* 
- * Static function definitions
- */
-
-PRIVATE BOOL
-watermarkLevelIsOk (IxQMgrQId qId, IxQMgrWMLevel level)
-{
-    unsigned qSizeInEntries;
-
-    switch (level)
-    {
-	case IX_QMGR_Q_WM_LEVEL0: 
-	case IX_QMGR_Q_WM_LEVEL1: 
-	case IX_QMGR_Q_WM_LEVEL2: 
-	case IX_QMGR_Q_WM_LEVEL4: 
-	case IX_QMGR_Q_WM_LEVEL8: 
-	case IX_QMGR_Q_WM_LEVEL16:
-	case IX_QMGR_Q_WM_LEVEL32:
-	case IX_QMGR_Q_WM_LEVEL64:
-	    break;
-	default:
-	    return false;
-    }
-
-    /* Check watermark is not bigger than the qSizeInEntries */
-    ixQMgrQSizeInEntriesGet(qId, &qSizeInEntries);
-
-    if ((unsigned)level > qSizeInEntries)
-    {
-	return false;
-    }
-
-    return true;
-}
-
-PRIVATE BOOL
-qSizeInWordsIsOk (IxQMgrQSizeInWords qSize)
-{
-    BOOL status;
-
-    switch (qSize)
-    {	
-	case IX_QMGR_Q_SIZE16:
-	case IX_QMGR_Q_SIZE32:
-	case IX_QMGR_Q_SIZE64:
-	case IX_QMGR_Q_SIZE128:
-	    status = true;
-	    break;
-	default:
-	    status = false;
-	    break;
-    }
-
-    return status;
-}
-
-PRIVATE BOOL
-qEntrySizeInWordsIsOk (IxQMgrQEntrySizeInWords entrySize)
-{
-    BOOL status;
-
-    switch (entrySize)
-    {
-	case IX_QMGR_Q_ENTRY_SIZE1:
-	case IX_QMGR_Q_ENTRY_SIZE2:
-	case IX_QMGR_Q_ENTRY_SIZE4:
-	    status = true;
-	    break;
-	default:
-	    status = false;
-	    break;
-    }
-
-    return status;
-}
diff --git a/drivers/net/npe/Makefile b/drivers/net/npe/Makefile
deleted file mode 100644
index a982678d89..0000000000
--- a/drivers/net/npe/Makefile
+++ /dev/null
@@ -1,83 +0,0 @@
-#
-# (C) Copyright 2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-include $(TOPDIR)/config.mk
-
-LIB := $(obj)libnpe.o
-
-LOCAL_CFLAGS  += -I$(TOPDIR)/drivers/net/npe/include -DCONFIG_IXP425_COMPONENT_ETHDB -D__linux
-CFLAGS  += $(LOCAL_CFLAGS)
-CPPFLAGS  += $(LOCAL_CFLAGS) # needed for depend
-HOSTCFLAGS  += $(LOCAL_CFLAGS)
-
-COBJS-$(CONFIG_IXP4XX_NPE) := npe.o \
-	miiphy.o \
-	IxOsalBufferMgt.o \
-	IxOsalIoMem.o \
-	IxOsalOsCacheMMU.o \
-	IxOsalOsMsgQ.o \
-	IxOsalOsSemaphore.o \
-	IxOsalOsServices.o \
-	IxOsalOsThread.o \
-	IxEthAcc.o \
-	IxEthAccCommon.o \
-	IxEthAccControlInterface.o \
-	IxEthAccDataPlane.o \
-	IxEthAccMac.o \
-	IxEthAccMii.o \
-	IxEthDBAPI.o \
-	IxEthDBAPISupport.o \
-	IxEthDBCore.o \
-	IxEthDBEvents.o \
-	IxEthDBFeatures.o \
-	IxEthDBFirewall.o \
-	IxEthDBHashtable.o \
-	IxEthDBLearning.o \
-	IxEthDBMem.o \
-	IxEthDBNPEAdaptor.o \
-	IxEthDBPortUpdate.o \
-	IxEthDBReports.o \
-	IxEthDBSearch.o \
-	IxEthDBSpanningTree.o \
-	IxEthDBUtil.o \
-	IxEthDBVlan.o \
-	IxEthDBWiFi.o \
-	IxEthMii.o \
-	IxQMgrAqmIf.o \
-	IxQMgrDispatcher.o \
-	IxQMgrInit.o \
-	IxQMgrQAccess.o \
-	IxQMgrQCfg.o \
-	IxFeatureCtrl.o \
-	IxNpeDl.o \
-	IxNpeDlImageMgr.o \
-	IxNpeDlNpeMgr.o \
-	IxNpeDlNpeMgrUtils.o \
-	IxNpeMh.o \
-	IxNpeMhConfig.o \
-	IxNpeMhReceive.o \
-	IxNpeMhSend.o \
-	IxNpeMhSolicitedCbMgr.o \
-	IxNpeMhUnsolicitedCbMgr.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS-y))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-all:	$(LIB)
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
diff --git a/drivers/net/npe/include/IxAssert.h b/drivers/net/npe/include/IxAssert.h
deleted file mode 100644
index 8be0cafc44..0000000000
--- a/drivers/net/npe/include/IxAssert.h
+++ /dev/null
@@ -1,47 +0,0 @@
-/**
- * @file IxAssert.h
- *
- * @date 21-MAR-2002 (replaced by OSAL)
- *
- * @brief This file contains assert and ensure macros used by the IXP400 software
- *
- * 
- * @par
- * IXP400 SW Release version 2.0
- * 
- * -- Copyright Notice --
- * 
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- * 
- * @par
- * SPDX-License-Identifier:	BSD-3-Clause
- * @par
- * -- End of Copyright Notice --
- */
-
-/**
- * @defgroup IxAssert IXP400 Assertion Macros (IxAssert) API
- *
- * @brief Assertion support
- *
- * @{
- */
-
-#ifndef IXASSERT_H
-
-#ifndef __doxygen_HIDE
-#define IXASSERT_H
-#endif /* __doxygen_HIDE */
-
-#include "IxOsalBackward.h"
-
-#endif /* IXASSERT_H */
-
-/**
- * @} addtogroup IxAssert
- */
-
-
-
diff --git a/drivers/net/npe/include/IxAtmSch.h b/drivers/net/npe/include/IxAtmSch.h
deleted file mode 100644
index 7d74771c28..0000000000
--- a/drivers/net/npe/include/IxAtmSch.h
+++ /dev/null
@@ -1,480 +0,0 @@
-/**
- * @file    IxAtmSch.h
- *
- * @date    23-NOV-2001
- *
- * @brief   Header file for the IXP400 ATM Traffic Shaper
- *
- * This component demonstrates an ATM Traffic Shaper implementation. It
- * will perform shaping on upto 12 ports and total of 44 VCs accross all ports,
- * 32 are intended for AAL0/5 and 12 for OAM (1 per port).
- * The supported traffic types are;1 rt-VBR VC where PCR = SCR.
- * (Effectively CBR) and Up-to 44 VBR VCs.
- *
- * This component models the ATM ports and VCs and is capable of producing
- * a schedule of ATM cells per port which can be supplied to IxAtmdAcc
- * for execution on the data path.
- * 
- * @par
- * IXP400 SW Release version 2.0
- * 
- * -- Copyright Notice --
- * 
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- * 
- * @par
- * SPDX-License-Identifier:	BSD-3-Clause
- * @par
- * -- End of Copyright Notice --
- *
- * @sa IxAtmm.h
- *
- */
-
-/**
- * @defgroup IxAtmSch IXP400 ATM Transmit Scheduler (IxAtmSch) API
- *
- * @brief IXP400 ATM scheduler component Public API
- *
- * @{
- */
-
-#ifndef IXATMSCH_H
-#define IXATMSCH_H
-
-#include "IxOsalTypes.h"
-#include "IxAtmTypes.h"
-
-/*
- * #defines and macros used in this file.
- */
-
-/* Return codes */
-
-/** 
- * @ingroup IxAtmSch
- *
- * @def IX_ATMSCH_RET_NOT_ADMITTED
- * @brief Indicates that CAC function has rejected VC registration due
- *         to insufficient line capacity.
-*/
-#define IX_ATMSCH_RET_NOT_ADMITTED 2
-
-/**  
- * @ingroup IxAtmSch
- *
- * @def IX_ATMSCH_RET_QUEUE_FULL
- *  @brief Indicates that the VC queue is full, no more demand can be
- *         queued at this time.
- */
-#define IX_ATMSCH_RET_QUEUE_FULL 3
-
-/**  
- * @ingroup IxAtmSch
- *
- *  @def IX_ATMSCH_RET_QUEUE_EMPTY
- *  @brief Indicates that all VC queues on this port are empty and
- *         therefore there are no cells to be scheduled at this time.
- */
-#define IX_ATMSCH_RET_QUEUE_EMPTY 4
-
-/*
- * Function declarations
- */
-
-/**  
- * @ingroup IxAtmSch
- *
- * @fn ixAtmSchInit(void)
- *
- *  @brief This function is used to initialize the ixAtmSch component. It
- *         should be called before any other IxAtmSch API function.
- *
- * @param None
- *
- * @return
- * - <b>IX_SUCCESS :</b> indicates that
- *          -# The ATM scheduler component has been successfully initialized.
- *          -# The scheduler is ready to accept Port modelling requests.
- * - <b>IX_FAIL :</b> Some internal error has prevented the scheduler component
- *          from initialising.
- */
-PUBLIC IX_STATUS
-ixAtmSchInit(void);
-
-/**  
- * @ingroup IxAtmSch
- *
- * @fn ixAtmSchPortModelInitialize( IxAtmLogicalPort port,
-                                       unsigned int portRate,
-                                       unsigned int minCellsToSchedule)
- *
- * @brief This function shall be called first to initialize an ATM port before
- *         any other ixAtmSch API calls may be made for that port.
- *
- * @param port @ref IxAtmLogicalPort [in] - The specific port to initialize.  Valid
- *          values range from 0 to IX_UTOPIA_MAX_PORTS - 1, representing a 
- *          maximum of IX_UTOPIA_MAX_PORTS possible ports.
- *
- * @param portRate unsigned int [in] - Value indicating the upstream capacity
- *          of the indicated port.  The value should be supplied in
- *          units of ATM (53 bytes) cells per second.
- *          A port rate of 800Kbits/s is the equivalent 
- *          of 1886 cells per second
- *
- * @param minCellsToSchedule unsigned int [in] - This parameter specifies the minimum
- *          number of cells which the scheduler will put in a schedule
- *          table for this port. This value sets the worst case CDVT for VCs
- *          on this port i.e. CDVT = 1*minCellsToSchedule/portRate.
- * @return
- *    - <b>IX_SUCCESS :</b> indicates that
- *          -# The ATM scheduler has been successfully initialized.
- *          -# The requested port model has been established.
- *          -# The scheduler is ready to accept VC modelling requests
- *            on the ATM port.
- *    - <b>IX_FAIL :</b> indicates the requested port could not be
- * initialized.  */
-PUBLIC IX_STATUS
-ixAtmSchPortModelInitialize( IxAtmLogicalPort port,
-                                       unsigned int portRate,
-                                       unsigned int minCellsToSchedule);
-
-/**  
- * @ingroup IxAtmSch
- *
- * @fn ixAtmSchPortRateModify( IxAtmLogicalPort port,
-                        unsigned int portRate)
- *
- *  @brief This function is called to modify the portRate on a
- *         previously initialized port, typically in the event that
- *         the line condition of the port changes.
- *
- * @param port @ref IxAtmLogicalPort [in] - Specifies the ATM port which is to be
- *          modified.
- *
- * @param portRate unsigned int [in] - Value indicating the new upstream
- *          capacity for this port in cells/second.
- *          A port rate of 800Kbits/s is the equivalent 
- *          of 1886 cells per second
- *
- * @return
- * - <b>IX_SUCCESS :</b> The port rate has been successfully modified.<br>
- * - <b>IX_FAIL :</b> The port rate could not be modified, either
- *      because the input data was invalid, or the new port rate is
- *      insufficient to support established ATM VC contracts on this
- *      port.
- *
- * @warning The IxAtmSch component will validate the supplied port
- *          rate is sufficient to support all established VC
- *          contracts on the port.  If the new port rate is
- *          insufficient to support all established contracts then
- *          the request to modify the port rate will be rejected.
- *          In this event, the user is expected to remove
- *          established contracts using the ixAtmSchVcModelRemove
- *          interface and then retry this interface.
- *
- * @sa ixAtmSchVcModelRemove() */
-PUBLIC IX_STATUS
-ixAtmSchPortRateModify( IxAtmLogicalPort port,
-                        unsigned int portRate);
-
-
-/**  
- * @ingroup IxAtmSch
- *
- * @fn ixAtmSchVcModelSetup( IxAtmLogicalPort port,
-                      IxAtmTrafficDescriptor *trafficDesc,
-                      IxAtmSchedulerVcId *vcId)
- *
- *  @brief A client calls this interface to set up an upstream
- *         (transmitting) virtual connection model (VC) on the
- *         specified ATM port.  This function also provides the
- *         virtual * connection admission control (CAC) service to the
- *         client.
- *
- * @param port @ref IxAtmLogicalPort [in] - Specifies the ATM port on which the upstream
- *          VC is to be established.
- *
- * @param *trafficDesc @ref IxAtmTrafficDescriptor [in] - Pointer to a structure
- *          describing the requested traffic contract of the VC to be
- *          established.  This structure contains the typical ATM
- *          traffic descriptor values (e.g. PCR, SCR, MBS, CDVT, etc.)
- *          defined by the ATM standard.
- *
- * @param *vcId @ref IxAtmSchedulerVcId [out] - This value will be filled with the
- *              port-unique identifier for this virtual connection.  A
- *              valid identification is a non-negative number.
- *
- * @return
- * - <b>IX_SUCCESS :</b> The VC has been successfully established on
- *      this port.  The client may begin to submit demand on this VC.
- * - <b>IX_ATMSCH_RET_NOT_ADMITTED :</b> The VC cannot be established
- *      on this port because there is insufficient upstream capacity
- *      available to support the requested traffic contract descriptor
- * - <b>IX_FAIL :</b>Input data are invalid.  VC has not been
- *      established.
- */
-PUBLIC IX_STATUS
-ixAtmSchVcModelSetup( IxAtmLogicalPort port,
-                      IxAtmTrafficDescriptor *trafficDesc,
-                      IxAtmSchedulerVcId *vcId);
-
-/**  
- * @ingroup IxAtmSch
- *
- * @fn ixAtmSchVcConnIdSet( IxAtmLogicalPort port,
-                     IxAtmSchedulerVcId vcId,
-                     IxAtmConnId vcUserConnId)
- *
- *  @brief A client calls this interface to set the vcUserConnId for a VC on
- *         the specified ATM port. This vcUserConnId will default to
- *         IX_ATM_IDLE_CELLS_CONNID if this function is not called for a VC.
- *         Hence if the client does not call this function for a VC then only idle
- *         cells will be scheduled for this VC.
- *
- * @param port @ref IxAtmLogicalPort [in] - Specifies the ATM port on which the upstream
- *        VC is has been established.
- *
- * @param vcId @ref IxAtmSchedulerVcId [in] - This is the unique identifier for this virtual
- *        connection. A valid identification is a non-negative number and is
- *        all ports.
- *
- * @param vcUserConnId @ref IxAtmConnId [in] - The connId is used to refer to a VC in schedule
- *        table entries. It is treated as the Id by which the scheduler client
- *        knows the VC. It is used in any communicatations from the Scheduler
- *        to the scheduler user e.g. schedule table entries.
- *
- * @return
- * - <b>IX_SUCCESS :</b> The id has successfully been set.
- * - <b>IX_FAIL :</b>Input data are invalid. connId id is not established.
- */
-PUBLIC IX_STATUS
-ixAtmSchVcConnIdSet( IxAtmLogicalPort port,
-                     IxAtmSchedulerVcId vcId,
-                     IxAtmConnId vcUserConnId);
-
-/**  
- * @ingroup IxAtmSch
- *
- * @fn ixAtmSchVcModelRemove( IxAtmLogicalPort port,
-                       IxAtmSchedulerVcId vcId)
- *
- *  @brief Interface called by the client to remove a previously
- *         established VC on a particular port.
- *
- * @param port @ref IxAtmLogicalPort [in] - Specifies the ATM port on which the VC to be
- *          removed is established.
- *
- * @param vcId @ref IxAtmSchedulerVcId [in] - Identifies the VC to be removed.  This is the
- *          value returned by the @ref ixAtmSchVcModelSetup call which
- *          established the relevant VC.
- *
- * @return
- * - <b>IX_SUCCESS :</b> The VC has been successfully removed from
- *      this port. It is no longer modelled on this port.
- * - <b>IX_FAIL :</b>Input data are invalid. The VC is still being modeled
- *      by the traffic shaper.
- *
- * @sa ixAtmSchVcModelSetup() 
- */
-PUBLIC IX_STATUS
-ixAtmSchVcModelRemove( IxAtmLogicalPort port,
-                       IxAtmSchedulerVcId vcId);
-
-/**  
- * @ingroup IxAtmSch
- *
- * @fn ixAtmSchVcQueueUpdate( IxAtmLogicalPort port,
-                       IxAtmSchedulerVcId vcId,
-                       unsigned int numberOfCells)
- *
- *  @brief The client calls this function to notify IxAtmSch that the
- *         user of a VC has submitted cells for transmission.
- *
- *  This information is stored, aggregated from a number of calls to
- *  ixAtmSchVcQueueUpdate and eventually used in the call to
- *  ixAtmSchTableUpdate.
- *
- *  Normally IxAtmSch will update the VC queue by adding the number of
- *  cells to the current queue length.  However, if IxAtmSch
- *  determines that the user has over-submitted for the VC and
- *  exceeded its transmission quota the queue request can be rejected.
- *  The user should resubmit the request later when the queue has been
- *  depleted.
- *
- *  This implementation of ixAtmSchVcQueueUpdate uses no operating
- *  system or external facilities, either directly or indirectly.
- *  This allows clients to call this function form within an interrupt handler.
- *
- *  This interface is structurally compatible with the
- *  IxAtmdAccSchQueueUpdate callback type definition required for
- *  IXP400 ATM scheduler interoperability.
- *
- * @param port @ref IxAtmLogicalPort [in] - Specifies the ATM port on which the VC to be
- *          updated is established.
- *
- * @param vcId @ref IxAtmSchedulerVcId [in] - Identifies the VC to be updated.  This is the
- *          value returned by the @ref ixAtmSchVcModelSetup call which
- *          established the relevant VC.
- *
- * @param numberOfCells unsigned int [in] - Indicates how many ATM cells should
- *          be added to the queue for this VC.
- *
- * @return
- *  - <b>IX_SUCCESS :</b> The VC queue has been successfully updated.
- *  - <b>IX_ATMSCH_RET_QUEUE_FULL :</b> The VC queue has reached a
- *       preset limit.  This indicates the client has over-submitted
- *       and exceeded its transmission quota.  The request is
- *       rejected.  The VC queue is not updated.  The VC user is
- *       advised to resubmit the request later.
- *  - <b>IX_FAIL :</b> The input are invalid.  No VC queue is updated.
- *
- * @warning IxAtmSch assumes that the calling software ensures that
- *          calls to ixAtmSchVcQueueUpdate, ixAtmSchVcQueueClear and
- *          ixAtmSchTableUpdate are both self and mutually exclusive
- *          for the same port.
- *
- * @sa ixAtmSchVcQueueUpdate(), ixAtmSchVcQueueClear(), ixAtmSchTableUpdate().  */
-PUBLIC IX_STATUS
-ixAtmSchVcQueueUpdate( IxAtmLogicalPort port,
-                       IxAtmSchedulerVcId vcId,
-                       unsigned int numberOfCells);
-
-/**  
- * @ingroup IxAtmSch
- *
- * @fn ixAtmSchVcQueueClear( IxAtmLogicalPort port,
-                      IxAtmSchedulerVcId vcId)
- *
- *  @brief The client calls this function to remove all currently
- *         queued cells from a registered VC.  The pending cell count
- *         for the specified VC is reset to zero.
- *
- *  This interface is structurally compatible with the
- *  IxAtmdAccSchQueueClear callback type definition required for
- *  IXP400 ATM scheduler interoperability.
- *
- * @param port @ref IxAtmLogicalPort [in] - Specifies the ATM port on which the VC to be
- *          cleared is established.
- *
- * @param vcId @ref IxAtmSchedulerVcId [in] - Identifies the VC to be cleared.  This is the
- *          value returned by the @ref ixAtmSchVcModelSetup call which
- *          established the relevant VC.
- *
- * @return
- *  - <b>IX_SUCCESS :</b> The VC queue has been successfully cleared.
- *  - <b>IX_FAIL :</b> The input are invalid.  No VC queue is modified.
- *
- * @warning IxAtmSch assumes that the calling software ensures that
- *          calls to ixAtmSchVcQueueUpdate, ixAtmSchVcQueueClear and
- *          ixAtmSchTableUpdate are both self and mutually exclusive
- *          for the same port.
- *
- * @sa ixAtmSchVcQueueUpdate(), ixAtmSchVcQueueClear(), ixAtmSchTableUpdate().  */
-PUBLIC IX_STATUS
-ixAtmSchVcQueueClear( IxAtmLogicalPort port,
-                      IxAtmSchedulerVcId vcId);
-
-/**  
- * @ingroup IxAtmSch
- *
- * @fn ixAtmSchTableUpdate( IxAtmLogicalPort port,
-                     unsigned int maxCells,
-                     IxAtmScheduleTable **rettable)
- *
- *  @brief The client calls this function to request an update of the
- *         schedule table for a particular ATM port.
- *
- *  This is called when the client decides it needs a new sequence of
- *  cells to send (probably because the transmit queue is near to
- *  empty for this ATM port).  The scheduler will use its stored
- *  information on the cells submitted for transmit (i.e. data
- *  supplied via @ref ixAtmSchVcQueueUpdate function) with the traffic
- *  descriptor information of all established VCs on the ATM port to
- *  decide the sequence of cells to be sent and fill the schedule
- *  table for a period of time into the future.
- *
- *  IxAtmSch will guarantee a minimum of minCellsToSchedule if there
- *  is at least one cell ready to send. If there are no cells then
- *  IX_ATMSCH_RET_QUEUE_EMPTY is returned.
- *
- *  This implementation of ixAtmSchTableUpdate uses no operating
- *  system or external facilities, either directly or indirectly.
- *  This allows clients to call this function form within an FIQ
- *  interrupt handler.
- *
- * @param port @ref IxAtmLogicalPort [in] - Specifies the ATM port for which requested
- *          schedule table is to be generated.
- *
- * @param maxCells unsigned [in] - Specifies the maximum number of cells
- *          that must be scheduled in the supplied table during any
- *          call to the interface.
- *
- * @param **table @ref IxAtmScheduleTable [out] - A pointer to an area of
- *              storage is returned which contains the generated
- *              schedule table.  The client should not modify the
- *              contents of this table.
- *
- * @return
- *  - <b>IX_SUCCESS :</b> The schedule table has been published.
- *       Currently there is at least one VC queue that is nonempty.
- *  - <b>IX_ATMSCH_RET_QUEUE_EMPTY :</b> Currently all VC queues on
- *       this port are empty.  The schedule table returned is set to
- *       NULL.  The client is not expected to invoke this function
- *       again until more cells have been submitted on this port
- *       through the @ref ixAtmSchVcQueueUpdate function.
- *  - <b>IX_FAIL :</b> The input are invalid.  No action is taken.
- *
- * @warning IxAtmSch assumes that the calling software ensures that
- *          calls to ixAtmSchVcQueueUpdate, ixAtmSchVcQueueClear and
- *          ixAtmSchTableUpdate are both self and mutually exclusive
- *          for the same port.
- *
- * @warning Subsequent calls to this function for the same port will
- *          overwrite the contents of previously supplied schedule
- *          tables.  The client must be completely finished with the
- *          previously supplied schedule table before calling this
- *          function again for the same port.
- *
- * @sa ixAtmSchVcQueueUpdate(), ixAtmSchVcQueueClear(), ixAtmSchTableUpdate().  */
-PUBLIC IX_STATUS
-ixAtmSchTableUpdate( IxAtmLogicalPort port,
-                     unsigned int maxCells,
-                     IxAtmScheduleTable **rettable);
-
-/**  
- * @ingroup IxAtmSch
- *
- * @fn ixAtmSchShow(void)
- *
- *  @brief Utility function which will print statistics on the current
- *         and accumulated state of VCs and traffic in the ATM
- *         scheduler component.  Output is sent to the default output
- *         device.
- *
- * @param none
- * @return none
- */
-PUBLIC void
-ixAtmSchShow(void);
-
-/**  
- * @ingroup IxAtmSch
- *
- * @fn ixAtmSchStatsClear(void)
- *
- *  @brief Utility function which will reset all counter statistics in
- *         the ATM scheduler to zero.
- *
- * @param none
- * @return none
- */
-PUBLIC void
-ixAtmSchStatsClear(void);
-
-#endif
-/* IXATMSCH_H */
-
-/** @} */
diff --git a/drivers/net/npe/include/IxAtmTypes.h b/drivers/net/npe/include/IxAtmTypes.h
deleted file mode 100644
index 6c8d12f394..0000000000
--- a/drivers/net/npe/include/IxAtmTypes.h
+++ /dev/null
@@ -1,385 +0,0 @@
-/**
- * @file IxAtmTypes.h
- *
- * @date 24-MAR-2002
- *
- * @brief This file contains Atm types common to a number of Atm components.
- * 
- * @par
- * IXP400 SW Release version 2.0
- * 
- * -- Copyright Notice --
- * 
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- * 
- * @par
- * SPDX-License-Identifier:	BSD-3-Clause
- * @par
- * -- End of Copyright Notice --
- */
-
-/* ------------------------------------------------------
-   Doxygen group definitions
-   ------------------------------------------------------ */
-/**
- * @defgroup IxAtmTypes IXP400 ATM Types (IxAtmTypes)
- *
- * @brief The common set of types used in many Atm components
- *
- * @{ */
-
-#ifndef IXATMTYPES_H
-#define IXATMTYPES_H
-
-#include "IxNpeA.h"
-
-/**
- * @enum IxAtmLogicalPort
- *
- * @brief Logical Port Definitions  :
- *
- * Only 1 port is available in SPHY configuration
- * 12 ports are enabled in MPHY configuration
- *
- */
-typedef enum
-{
-    IX_UTOPIA_PORT_0 = 0,  /**< Port 0 */
-#ifdef IX_NPE_MPHYMULTIPORT
-    IX_UTOPIA_PORT_1,      /**< Port 1 */
-    IX_UTOPIA_PORT_2,      /**< Port 2 */
-    IX_UTOPIA_PORT_3,      /**< Port 3 */
-    IX_UTOPIA_PORT_4,      /**< Port 4 */
-    IX_UTOPIA_PORT_5,      /**< Port 5 */
-    IX_UTOPIA_PORT_6,      /**< Port 6 */
-    IX_UTOPIA_PORT_7,      /**< Port 7 */
-    IX_UTOPIA_PORT_8,      /**< Port 8 */
-    IX_UTOPIA_PORT_9,      /**< Port 9 */
-    IX_UTOPIA_PORT_10,     /**< Port 10 */
-    IX_UTOPIA_PORT_11,     /**< Port 11 */
-#endif /* IX_NPE_MPHY */
-    IX_UTOPIA_MAX_PORTS    /**< Not a port - just a definition for the
-                           * maximum possible ports
-                           */
-} IxAtmLogicalPort;
-
-/**
- * @def IX_ATM_CELL_PAYLOAD_SIZE
- * @brief Size of a ATM cell payload
- */
-#define IX_ATM_CELL_PAYLOAD_SIZE             (48)
-
-/**
- * @def IX_ATM_CELL_SIZE
- * @brief Size of a ATM cell, including header
- */
-#define IX_ATM_CELL_SIZE                     (53)
-
-/**
- * @def IX_ATM_CELL_SIZE_NO_HEC
- * @brief Size of a ATM cell, excluding HEC byte
- */
-#define IX_ATM_CELL_SIZE_NO_HEC              (IX_ATM_CELL_SIZE - 1)
-
-/**
- * @def IX_ATM_OAM_CELL_SIZE_NO_HEC
- * @brief Size of a OAM cell, excluding HEC byte
- */
-#define IX_ATM_OAM_CELL_SIZE_NO_HEC          IX_ATM_CELL_SIZE_NO_HEC
-
-/**
- * @def IX_ATM_AAL0_48_CELL_PAYLOAD_SIZE
- * @brief Size of a AAL0 48 Cell payload
- */
-#define IX_ATM_AAL0_48_CELL_PAYLOAD_SIZE     IX_ATM_CELL_PAYLOAD_SIZE
-
-/**
- * @def IX_ATM_AAL5_CELL_PAYLOAD_SIZE
- * @brief Size of a AAL5 Cell payload
- */
-#define IX_ATM_AAL5_CELL_PAYLOAD_SIZE        IX_ATM_CELL_PAYLOAD_SIZE
-
-/**
- * @def IX_ATM_AAL0_52_CELL_SIZE_NO_HEC
- * @brief Size of a AAL0 52 Cell, excluding HEC byte
- */
-#define IX_ATM_AAL0_52_CELL_SIZE_NO_HEC      IX_ATM_CELL_SIZE_NO_HEC
-
-
-/**
- * @def IX_ATM_MAX_VPI
- * @brief Maximum value of an ATM VPI
- */
-#define IX_ATM_MAX_VPI 255
-
-/**
- * @def IX_ATM_MAX_VCI
- * @brief Maximum value of an ATM VCI
- */
-#define IX_ATM_MAX_VCI 65535
-
- /**
- * @def IX_ATM_MAX_NUM_AAL_VCS
- * @brief Maximum number of active AAL5/AAL0 VCs in the system
- */
-#define IX_ATM_MAX_NUM_AAL_VCS 32
-
-/**
- * @def IX_ATM_MAX_NUM_VC
- * @brief Maximum number of active AAL5/AAL0 VCs in the system
- * The use of this macro is depreciated, it is retained for
- * backward compatiblity. For current software release
- * and beyond the define IX_ATM_MAX_NUM_AAL_VC should be used.
- */
-#define IX_ATM_MAX_NUM_VC IX_ATM_MAX_NUM_AAL_VCS
-
-
-
-/**
- * @def IX_ATM_MAX_NUM_OAM_TX_VCS
- * @brief Maximum number of active OAM Tx VCs in the system, 
- *        1 OAM VC per port
- */
-#define IX_ATM_MAX_NUM_OAM_TX_VCS IX_UTOPIA_MAX_PORTS
-
-/**
- * @def IX_ATM_MAX_NUM_OAM_RX_VCS
- * @brief Maximum number of active OAM Rx VCs in the system, 
- *        1 OAM VC shared accross all ports
- */
-#define IX_ATM_MAX_NUM_OAM_RX_VCS 1
-
-/**
- * @def IX_ATM_MAX_NUM_AAL_OAM_TX_VCS
- * @brief Maximum number of active AAL5/AAL0/OAM Tx VCs in the system
- */
-#define IX_ATM_MAX_NUM_AAL_OAM_TX_VCS (IX_ATM_MAX_NUM_AAL_VCS + IX_ATM_MAX_NUM_OAM_TX_VCS)
-
-/**
- * @def IX_ATM_MAX_NUM_AAL_OAM_RX_VCS
- * @brief Maximum number of active AAL5/AAL0/OAM Rx VCs in the system
- */
-#define IX_ATM_MAX_NUM_AAL_OAM_RX_VCS (IX_ATM_MAX_NUM_AAL_VCS + IX_ATM_MAX_NUM_OAM_RX_VCS)
-
-/**
- *  @def IX_ATM_IDLE_CELLS_CONNID
- *  @brief VC Id used to indicate idle cells in the returned schedule table.
- */
-#define IX_ATM_IDLE_CELLS_CONNID 0
-
-
-/**
- *  @def IX_ATM_CELL_HEADER_VCI_GET
- *  @brief get the VCI field from a cell header
- */
-#define IX_ATM_CELL_HEADER_VCI_GET(cellHeader) \
-    (((cellHeader) >> 4) & IX_OAM_VCI_BITS_MASK);
-
-/**
- *  @def IX_ATM_CELL_HEADER_VPI_GET
- *  @brief get the VPI field from a cell header
- */
-#define IX_ATM_CELL_HEADER_VPI_GET(cellHeader) \
-    (((cellHeader) >> 20) & IX_OAM_VPI_BITS_MASK);
-
-/**
- *  @def IX_ATM_CELL_HEADER_PTI_GET
- *  @brief get the PTI field from a cell header
- */
-#define IX_ATM_CELL_HEADER_PTI_GET(cellHeader) \
-    ((cellHeader) >> 1) & IX_OAM_PTI_BITS_MASK;
-
-/**
- * @typedef IxAtmCellHeader
- *
- * @brief ATM Cell Header, does not contain 4 byte HEC, added by NPE-A 
- */
-typedef unsigned int IxAtmCellHeader;
-
-
-/**
- * @enum IxAtmServiceCategory
- *
- * @brief Enumerated type representing available ATM service categories.
- *   For more informatoin on these categories, see "Traffic Management
- *   Specification" v4.1, published by the ATM Forum -
- *   http://www.atmforum.com
- */
-typedef enum
-{
-    IX_ATM_CBR,    /**< Constant Bit Rate */
-    IX_ATM_RTVBR,  /**< Real Time Variable Bit Rate */
-    IX_ATM_VBR,    /**< Variable Bit Rate */
-    IX_ATM_UBR,    /**< Unspecified Bit Rate */
-    IX_ATM_ABR     /**< Available Bit Rate (not supported) */
-
-} IxAtmServiceCategory;
-
-/**
- *
- * @enum IxAtmRxQueueId
- *
- * @brief Rx Queue Type for RX traffic
- *
- * IxAtmRxQueueId defines the queues involved for receiving data.
- *
- * There are two queues to facilitate prioritisation handling
- * and processing the 2 queues with different algorithms and
- * constraints
- *
- * e.g. : one queue can carry voice (or time-critical traffic), the
- * other queue can carry non-voice traffic
- *
- */
-typedef enum
-{
-    IX_ATM_RX_A = 0,      /**< RX queue A */
-    IX_ATM_RX_B,          /**< RX queue B */
-    IX_ATM_MAX_RX_STREAMS /**< Maximum number of RX streams */
-} IxAtmRxQueueId;
-
-/**
- * @brief Structure describing an ATM traffic contract for a Virtual
- *         Connection (VC).
- *
- * Structure is used to specify the requested traffic contract for a
- * VC to the IxAtmSch component using the @ref ixAtmSchVcModelSetup
- * interface.
- *
- * These parameters are defined by the ATM forum working group
- * (http://www.atmforum.com).
- *
- * @note Typical values for a voice channel 64 Kbit/s
- * - atmService @a IX_ATM_RTVBR
- * - pcr   400  (include IP overhead, and AAL5 trailer)
- * - cdvt  5000000 (5 ms)
- * - scr = pcr
- *
- * @note Typical values for a data channel 800 Kbit/s
- * - atmService @a IX_ATM_UBR
- * - pcr   1962  (include IP overhead, and AAL5 trailer)
- * - cdvt  5000000 (5 ms)
- *
- */
-typedef struct
-{
-    IxAtmServiceCategory atmService; /**< ATM service category */
-    unsigned pcr;   /**< Peak Cell Rate - cells per second */
-    unsigned cdvt;  /**< Cell Delay Variation Tolerance - in nanoseconds */
-    unsigned scr;   /**< Sustained Cell Rate - cells per second */
-    unsigned mbs;   /**< Max Burst Size - cells */
-    unsigned mcr;   /**< Minimum Cell Rate - cells per second */
-    unsigned mfs;   /**< Max Frame Size - cells */
-} IxAtmTrafficDescriptor;
-
-/**
- * @typedef IxAtmConnId
- *
- * @brief ATM VC data connection identifier.
- *
- * This is is generated by IxAtmdAcc when a successful connection is
- * made on a VC. The is the ID by which IxAtmdAcc knows an active
- * VC and should be used in IxAtmdAcc API calls to reference a
- * specific VC.
- */
-typedef unsigned int IxAtmConnId;
-
-/**
- * @typedef IxAtmSchedulerVcId
- *
- * @brief ATM VC scheduling connection identifier.
- *
- * This id is generated and used by ATM Tx controller, generally
- * the traffic shaper (e.g. IxAtmSch). The IxAtmdAcc component
- * will request one of these Ids whenever a data connection on
- * a Tx VC is requested. This ID will be used in callbacks to
- * the ATM Transmission Ctrl s/w (e.g. IxAtmm) to reference a
- * particular VC.
- */
-typedef int IxAtmSchedulerVcId;
-
-/**
- * @typedef IxAtmNpeRxVcId
- *
- * @brief ATM Rx VC identifier used by the ATM Npe.
- *
- * This Id is generated by IxAtmdAcc when a successful data connection
- * is made on a rx VC.
- */
-typedef unsigned int IxAtmNpeRxVcId;
-
-/**
- * @brief ATM Schedule Table entry
- *
- * This IxAtmScheduleTableEntry is used by an ATM scheduler to inform
- * IxAtmdAcc about the data to transmit (in term of cells per VC)
- *
- * This structure defines
- * @li the number of cells to be transmitted (numberOfCells)
- * @li the VC connection to be used for transmission (connId).
- *
- * @note - When the connection Id value is IX_ATM_IDLE_CELLS_CONNID, the
- * corresponding number of idle cells will be transmitted to the hardware.
- *
- */
-typedef struct
-{
-    IxAtmConnId connId; /**< connection Id
-                 *
-                 * Identifier of VC from which cells are to be transmitted.
-                 * When this valus is IX_ATM_IDLE_CELLS_CONNID, this indicates
-                 * that the system should transmit the specified number
-                 * of idle cells. Unknown connIds result in the transmission
-                 * idle cells.
-                 */
-    unsigned int numberOfCells; /**< number of cells to transmit
-                 *
-                 * The number of contiguous cells to schedule from this VC
-                 * at this point. The valid range is from 1 to
-                 * @a IX_ATM_SCHEDULETABLE_MAXCELLS_PER_ENTRY. This
-                 * number can swap over mbufs and pdus. OverSchduling results
-                 * in the transmission of idle cells.
-                 */
-} IxAtmScheduleTableEntry;
-
-/**
- * @brief This structure defines a schedule table which gives details
- *         on which data (from which VCs) should be transmitted for a
- *         forthcoming period of time for a particular port and the
- *         order in which that data should be transmitted.
- *
- *  The schedule table consists of a series of entries each of which
- *  will schedule one or more cells from a particular registered VC.
- *  The total number of cells scheduled and the total number of
- *  entries in the table are also indicated.
- *
- */
-typedef struct
-{
-    unsigned tableSize;      /**< Number of entries
-                              *
-                              * Indicates the total number of
-                              *   entries in the table.
-                              */
-    unsigned totalCellSlots; /**< Number of cells
-                              *
-                              * Indicates the total number of ATM
-                              *   cells which are scheduled by all the
-                              *   entries in the table.
-                              */
-    IxAtmScheduleTableEntry *table; /**< Pointer to schedule entries
-                                     *
-                                     * Pointer to an array
-                                     *   containing tableSize entries
-                                     */
-} IxAtmScheduleTable;
-
-#endif /* IXATMTYPES_H */
-
-/**
- * @} defgroup IxAtmTypes
- */
-
-
diff --git a/drivers/net/npe/include/IxAtmdAcc.h b/drivers/net/npe/include/IxAtmdAcc.h
deleted file mode 100644
index 291b662151..0000000000
--- a/drivers/net/npe/include/IxAtmdAcc.h
+++ /dev/null
@@ -1,1170 +0,0 @@
-
-/**
- * @file    IxAtmdAcc.h
- *
- * @date    07-Nov-2001
- *
- * @brief IxAtmdAcc Public API
- *
- * This file contains the public API of IxAtmdAcc, related to the
- * data functions of the component
- *
- * 
- * @par
- * IXP400 SW Release version 2.0
- * 
- * -- Copyright Notice --
- * 
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- * 
- * @par
- * SPDX-License-Identifier:	BSD-3-Clause
- * @par
- * -- End of Copyright Notice --
- */
-
-/* ------------------------------------------------------
-   Doxygen group definitions
-   ------------------------------------------------------ */
-
-/**
- *
- * @defgroup IxAtmdAccAPI IXP400 ATM Driver Access (IxAtmdAcc) API
- *
- * @brief The public API for the IXP400 Atm Driver Data component
- *
- * IxAtmdAcc is the low level interface by which AAL0/AAL5 and
- * OAM data gets transmitted to,and received from the Utopia bus.
- *
- * For AAL0/AAL5 services transmit and receive connections may
- * be established independantly for unique combinations of
- * port,VPI,and VCI.
- *
- * Two AAL0 services supporting 48 or 52 byte cell data are provided.
- * Submitted AAL0 PDUs must be a multiple of the cell data size (48/52).
- * AAL0_52 is a raw cell service the client must format
- * the PDU with an ATM cell header (excluding HEC) at the start of
- * each cell, note that AtmdAcc does not validate the cell headers in
- * a submitted PDU.
- *
- * OAM cells cannot be received over the AAL0 service but instead
- * are received over a dedicated OAM service.
- *
- * For the OAM service an "OAM Tx channel" may be enabled for a port
- * by establishing a single dedicated OAM Tx connection on that port.
- * A single "OAM Rx channel" for all ports may be  enabled by
- * establishing a dedicated OAM Rx connection.
- *
- * The OAM service allows buffers containing 52 byte OAM F4/F5 cells
- * to be transmitted and received over the dedicated OAM channels.
- * HEC is appended/removed, and CRC-10 performed by the NPE. The OAM
- * service offered by AtmdAcc is a raw cell transport service.
- * It is assumed that ITU I.610 procedures that make use of this
- * service are implemented above AtmdAcc.
- *
- * Note that the dedicated OAM connections are established on
- * reserved VPI,VCI, and (in the case of Rx) port values defined below.
- * These values are used purely to descriminate the dedicated OAM channels
- * and do not identify a particular OAM F4/F5 flow. F4/F5 flows may be
- * realised for particluar VPI/VCIs by manipulating the VPI,VCI
- * fields of the ATM cell headers of cells in the buffers passed
- * to AtmdAcc. Note that AtmdAcc does not validate the cell headers
- * in a submitted OAM PDU.
- *
- *
- *
- * This part is related to the User datapath processing
- *
- * @{
- */
-
-#ifndef IXATMDACC_H
-#define IXATMDACC_H
-
-#include "IxAtmTypes.h"
-
-/* ------------------------------------------------------
-   AtmdAcc Data Types definition
-   ------------------------------------------------------ */
-
-/**
- *
- * @ingroup IxAtmdAccAPI
- *
- * @def IX_ATMDACC_WARNING
- *
- * @brief Warning return code
- *
- * This constant is used to tell IxAtmDAcc user about a special case.
- *
- */
-#define IX_ATMDACC_WARNING 2
-
-/**
- *
- * @ingroup IxAtmdAccAPI
- *
- * @def IX_ATMDACC_BUSY
- *
- * @brief Busy return code
- *
- * This constant is used to tell IxAtmDAcc user that the request
- * is correct, but cannot be processed because the IxAtmAcc resources
- * are already used. The user has to retry its request later
- *
- */
-#define IX_ATMDACC_BUSY 3
-
-/**
- *
- * @ingroup IxAtmdAccAPI
- *
- * @def IX_ATMDACC_RESOURCES_STILL_ALLOCATED
- *
- * @brief Disconnect return code
- *
- * This constant is used to tell IxAtmDAcc user that the disconnect
- * functions are not complete because the resources used by the driver
- * are not yet released. The user has to retry the disconnect call
- * later.
- *
- */
-#define IX_ATMDACC_RESOURCES_STILL_ALLOCATED 4
-
-/**
- *
- * @ingroup IxAtmdAccAPI
- *
- * @def IX_ATMDACC_DEFAULT_REPLENISH_COUNT
- *
- * @brief Default resources usage for RxVcFree replenish mechanism
- *
- * This constant is used to tell IxAtmDAcc to allocate and use
- * the minimum of resources for rx free replenish.
- *
- * @sa ixAtmdAccRxVcConnect
- */
-#define IX_ATMDACC_DEFAULT_REPLENISH_COUNT 0
-
-
-/**
- * @ingroup IxAtmdAccAPI
- *
- * @def IX_ATMDACC_OAM_TX_VPI
- *
- * @brief The reserved value used for the dedicated OAM
- * Tx connection. This "well known" value is used by atmdAcc and
- * its clients to dsicriminate the OAM channel, and should be chosen so
- * that it does not coencide with the VPI value used in an AAL0/AAL5 connection.
- * Any attempt to connect a service type other than OAM on this VPI will fail.
- *
- *
- */
-#define IX_ATMDACC_OAM_TX_VPI 0
-
-/**
- * @ingroup IxAtmdAccAPI
- *
- * @def IX_ATMDACC_OAM_TX_VCI
- *
- * @brief The reserved value used for the dedicated OAM
- * Tx connection. This "well known" value is used by atmdAcc and
- * its clients to dsicriminate the OAM channel, and should be chosen so
- * that it does not coencide with the VCI value used in an AAL0/AAL5 connection.
- * Any attempt to connect a service type other than OAM on this VCI will fail.
- */
-#define IX_ATMDACC_OAM_TX_VCI 0
-
-
- /**
- * @ingroup IxAtmdAccAPI
- *
- * @def IX_ATMDACC_OAM_RX_PORT
- *
- * @brief The reserved dummy PORT used for all dedicated OAM
- * Rx connections. Note that this is not a real port but must
- * have a value that lies within the valid range of port values.
- */
-#define IX_ATMDACC_OAM_RX_PORT IX_UTOPIA_PORT_0
-
- /**
- * @ingroup IxAtmdAccAPI
- *
- * @def IX_ATMDACC_OAM_RX_VPI
- *
- * @brief The reserved value value used for the dedicated OAM
- * Rx connection. This value should be chosen so that it does not
- * coencide with the VPI value used in an AAL0/AAL5 connection.
- * Any attempt to connect a service type other than OAM on this VPI will fail.
- */
-#define IX_ATMDACC_OAM_RX_VPI 0
-
-/**
- * @ingroup IxAtmdAccAPI
- *
- * @def IX_ATMDACC_OAM_RX_VCI
- *
- * @brief The reserved value value used for the dedicated OAM
- * Rx connection. This value should be chosen so that it does not
- * coencide with the VCI value used in an AAL0/AAL5 connection.
- * Any attempt to connect a service type other than OAM on this VCI will fail.
- */
-#define IX_ATMDACC_OAM_RX_VCI 0
-
-
-/**
- * @enum IxAtmdAccPduStatus
- *
- * @ingroup IxAtmdAccAPI
- *
- * @brief IxAtmdAcc Pdu status :
- *
- * IxAtmdAccPduStatus is used during a RX operation to indicate
- * the status of the received PDU
- *
- */
-
-typedef enum
-{
-    IX_ATMDACC_AAL0_VALID = 0,    /**< aal0 pdu */
-    IX_ATMDACC_OAM_VALID,         /**< OAM pdu */
-    IX_ATMDACC_AAL2_VALID,        /**< aal2 pdu @b reserved for future use */
-    IX_ATMDACC_AAL5_VALID,        /**< aal5 pdu complete and trailer is valid */
-    IX_ATMDACC_AAL5_PARTIAL,      /**< aal5 pdu not complete, trailer is missing */
-    IX_ATMDACC_AAL5_CRC_ERROR,    /**< aal5 pdu not complete, crc error/length error */
-    IX_ATMDACC_MBUF_RETURN        /**< empty buffer returned to the user */
-} IxAtmdAccPduStatus;
-
-
-/**
- *
- * @enum IxAtmdAccAalType
- *
- * @ingroup IxAtmdAccAPI
- *
- * @brief IxAtmdAcc AAL Service Type :
- *
- * IxAtmdAccAalType defines the type of traffic to run on this VC
- *
- */
-typedef enum
-{
-    IX_ATMDACC_AAL5,                /**< ITU-T AAL5 */
-    IX_ATMDACC_AAL2,                /**< ITU-T AAL2 @b reserved for future use */
-    IX_ATMDACC_AAL0_48,             /**< AAL0 48 byte payloads (cell header is added by NPE)*/
-    IX_ATMDACC_AAL0_52,             /**< AAL0 52 byte cell data (HEC is added by NPE) */
-    IX_ATMDACC_OAM,                 /**< OAM cell transport service (HEC is added by NPE)*/
-    IX_ATMDACC_MAX_SERVICE_TYPE     /**< not a service, used for parameter validation */
-} IxAtmdAccAalType;
-
-/**
- *
- * @enum IxAtmdAccClpStatus
- *
- * @ingroup IxAtmdAccAPI
- *
- * @brief IxAtmdAcc CLP indication
- *
- * IxAtmdAccClpStatus defines the CLP status of the current PDU
- *
- */
-typedef enum
-{
-    IX_ATMDACC_CLP_NOT_SET = 0,     /**< CLP indication is not set */
-    IX_ATMDACC_CLP_SET = 1     /**< CLP indication is set */
-} IxAtmdAccClpStatus;
-
-/**
- * @typedef IxAtmdAccUserId
- *
- * @ingroup IxAtmdAccAPI
- *
- * @brief User-supplied Id
- *
- * IxAtmdAccUserId is passed through callbacks and allows the
- * IxAtmdAcc user to identify the source of a call back. The range of
- * this user-owned Id is [0...2^32-1)].
- *
- * The user provides this own Ids on a per-channel basis as a parameter
- * in a call to @a ixAtmdAccRxVcConnect() or @a ixAtmdAccRxVcConnect()
- *
- * @sa ixAtmdAccRxVcConnect
- * @sa ixAtmdAccTxVcConnect
- *
- */
-typedef unsigned int IxAtmdAccUserId;
-
-/* ------------------------------------------------------
-   Part of the IxAtmdAcc interface related to RX traffic
-   ------------------------------------------------------ */
-
-/**
- *
- * @ingroup IxAtmdAccAPI
- *
- * @brief  Rx callback prototype
- *
- * IxAtmdAccRxVcRxCallback is the prototype of the Rx callback user
- * function called once per PDU to pass a receive Pdu to a user on a
- * partilcular connection. The callback is likely to push the mbufs
- * to a protocol layer, and recycle the mbufs for a further use.
- *
- * @note -This function is called ONLY in the context of
- *        the @a ixAtmdAccRxDispatch() function
- *
- * @sa ixAtmdAccRxDispatch
- * @sa ixAtmdAccRxVcConnect
- *
- * @param port @ref IxAtmLogicalPort [in] - the port on which this PDU was received
- *        a logical PHY port [@a IX_UTOPIA_PORT_0 .. @a IX_UTOPIA_MAX_PORTS - 1]
- * @param userId @ref IxAtmdAccUserId [in] - user Id provided in the call
- *        to @a ixAtmdAccRxVcConnect()
- * @param status @ref IxAtmdAccPduStatus [in] - an indication about the PDU validity.
- *        In the case of AAL0 the only possibile value is
- *        AAL0_VALID, in this case the client may optionally determine
- *        that an rx timeout occured by checking if the mbuf is
- *        compleletly or only partially filled, the later case
- *        indicating a timeout.
- *        In the case of OAM the only possible value is OAM valid.
- *        The status is set to @a IX_ATMDACC_MBUF_RETURN when
- *        the mbuf is released during a disconnect process.
- * @param clp @ref IxAtmdAccClpStatus [in] - clp indication for this PDU.
- *        For AAL5/AAL0_48 this information
- *        is set if the clp bit of any rx cell is set
- *        For AAL0-52/OAM the client may inspect the CLP in individual
- *        cell headers in the PDU, and this parameter is set to 0.
- * @param *mbufPtr @ref IX_OSAL_MBUF [in] - depending on the servive type a pointer to
- *        an mbuf (AAL5/AAL0/OAM) or mbuf chain (AAL5 only),
- *        that comprises the complete PDU data.
- *
- *        This parameter is guaranteed not to be a null pointer.
- *
- */
-typedef void (*IxAtmdAccRxVcRxCallback) (IxAtmLogicalPort port,
-                       IxAtmdAccUserId userId,
-                       IxAtmdAccPduStatus status,
-                       IxAtmdAccClpStatus clp,
-                       IX_OSAL_MBUF * mbufPtr);
-
-/**
- *
- * @ingroup IxAtmdAccAPI
- *
- * @brief Callback prototype for free buffer level is low.
- *
- * IxAtmdAccRxVcFreeLowCallback is the prototype of the user function
- * which get called on a per-VC basis, when more  mbufs are needed to
- * continue the ATM data reception. This function is likely to supply
- * more available mbufs by one or many calls to the replenish function
- * @a ixAtmdAccRxVcFreeReplenish()
- *
- * This function is called when the number of available buffers for
- * reception is going under the threshold level as defined
- * in @a ixAtmdAccRxVcFreeLowCallbackRegister()
- *
- * This function is called inside an Qmgr dispatch context. No system
- * resource or interrupt-unsafe feature should be used inside this
- * callback.
- *
- * @sa ixAtmdAccRxVcFreeLowCallbackRegister
- * @sa IxAtmdAccRxVcFreeLowCallback
- * @sa ixAtmdAccRxVcFreeReplenish
- * @sa ixAtmdAccRxVcFreeEntriesQuery
- * @sa ixAtmdAccRxVcConnect
- *
- * @param userId @ref IxAtmdAccUserId [in] - user Id provided in the call
- * to @a ixAtmdAccRxVcConnect()
- *
- * @return None
- *
- */
-typedef void (*IxAtmdAccRxVcFreeLowCallback) (IxAtmdAccUserId userId);
-
-/* ------------------------------------------------------
-   Part of the IxAtmdAcc interface related to TX traffic
-   ------------------------------------------------------ */
-
-/**
- *
- * @ingroup IxAtmdAccAPI
- *
- * @brief  Buffer callback prototype.
- *
- * This function is called to relinguish ownership of a transmitted
- * buffer chain to the user.
- *
- * @note -In the case of a chained mbuf the AmtdAcc component can
- * chain many user buffers together and pass ownership to the user in
- * one function call.
- *
- * @param userId @ref IxAtmdAccUserId [in] - user If provided at registration of this
- *        callback.
- * @param mbufPtr @ref IX_OSAL_MBUF [in] - a pointer to mbufs or chain of mbufs and is
- *        guaranteed not to be a null pointer.
- *
- */
-typedef void (*IxAtmdAccTxVcBufferReturnCallback) (IxAtmdAccUserId userId,
-                        IX_OSAL_MBUF * mbufPtr);
-
-/* ------------------------------------------------------
-   Part of the IxAtmdAcc interface related to Initialisation
-   ------------------------------------------------------ */
-
-/**
- *
- * @ingroup IxAtmdAccAPI
- *
- * @fn ixAtmdAccInit (void)
- *
- * @brief Initialise the IxAtmdAcc Component
- *
- * This function initialise the IxAtmdAcc component. This function shall
- * be called before any other function of the API. Its role is to
- * initialise all internal resources of the IxAtmdAcc component.
- *
- * The ixQmgr component needs to be initialized prior the use of
- * @a ixAtmdAccInit()
- *
- * @param none
- *
- * Failing to initilialize the IxAtmdAcc API before any use of it will
- * result in a failed status.
- * If the specified component is not present, a success status will still be 
- * returned, however, a warning indicating the NPE to download to is not
- * present will be issued.
- *
- * @return @li IX_SUCCESS initialisation is complete (in case of component not
- *             being present, a warning is clearly indicated)
- * @return @li IX_FAIL unable to process this request either
- *             because this IxAtmdAcc is already initialised
- *             or some unspecified error has occrred.
- */
-PUBLIC IX_STATUS ixAtmdAccInit (void);
-
-/**
- *
- * @ingroup IxAtmdAccAPI
- *
- * @fn ixAtmdAccShow (void)
- *
- * @brief Show IxAtmdAcc configuration on a per port basis
- *
- * @param none
- *
- * @return none
- *
- * @note - Display use printf() and are redirected to stdout
- */
-PUBLIC void
-ixAtmdAccShow (void);
-
-/**
- *
- * @ingroup IxAtmdAccAPI
- * 
- * @fn ixAtmdAccStatsShow (void)
- *
- * @brief Show all IxAtmdAcc stats
- *
- * @param none
- *
- * @return none
- *
- * @note - Stats display use printf() and are redirected to stdout
- */
-PUBLIC void
-ixAtmdAccStatsShow (void);
-
-/**
- *
- * @ingroup IxAtmdAccAPI
- *
- * @fn ixAtmdAccStatsReset (void)
- *
- * @brief Reset all IxAtmdAcc stats
- *
- * @param none
- *
- * @return none
- *
- */
-PUBLIC void
-ixAtmdAccStatsReset (void);
-
-/* ------------------------------------------------------
-   Part of the IxAtmdAcc interface related to RX traffic
-   ------------------------------------------------------ */
-
-/**
- *
- * @ingroup IxAtmdAccAPI
- *
- * @fn ixAtmdAccRxVcConnect (IxAtmLogicalPort port,
-                      unsigned int vpi,
-                      unsigned int vci,
-                      IxAtmdAccAalType aalServiceType,
-                      IxAtmRxQueueId rxQueueId,
-                      IxAtmdAccUserId userCallbackId,
-                      IxAtmdAccRxVcRxCallback rxCallback,
-                      unsigned int minimumReplenishCount,
-                      IxAtmConnId * connIdPtr,
-                      IxAtmNpeRxVcId * npeVcIdPtr )
- *
- * @brief Connect to a Aal Pdu receive service for a particular
- *        port/vpi/vci, and service type.
- *
- * This function allows a user to connect to an Aal5/Aal0/OAM Pdu receive service
- * for a particular port/vpi/vci. It registers the callback and allocates
- * internal resources and a Connection Id to be used in further API calls
- * related to this VCC.
- *
- * The function will setup VC receive service on the specified rx queue.
- *
- * This function is blocking and makes use internal locks, and hence
- * should not be called from an interrupt context.
- *
- * On return from @a ixAtmdAccRxVcConnect() with a failure status, the
- * connection Id parameter is unspecified. Its value cannot be used.
- * A connId is the reference by which IxAtmdAcc refers to a
- * connected VC. This identifier is the result of a succesful call
- * to a connect function. This identifier is invalid after a
- * sucessful call to a disconnect function.
- *
- * Calling this function for the same combination of Vpi, Vci and more
- * than once without calling @a ixAtmdAccRxVcTryDisconnect() will result in a
- * failure status.
- *
- * If this function returns success the user should supply receive
- * buffers by calling @a ixAtmdAccRxVcFreeReplenish() and then call
- * @a ixAtmdAccRxVcEnable() to begin receiving pdus.
- *
- * There is a choice of two receive Qs on which the VC pdus could be
- * receive. The user must associate the VC with one of these. Essentially
- * having two qs allows more flexible system configuration such as have
- * high prioriy traffic on one q (e.g. voice) and low priority traffic on
- * the other (e.g. data). The high priority Q could be serviced in
- * preference to the low priority Q. One queue may be configured to be
- * serviced as soon as there is traffic, the other queue may be configured
- * to be serviced by a polling mechanism running at idle time.
- *
- * Two AAL0 services supporting 48 or 52 byte cell data are provided.
- * Received AAL0 PDUs will be be a multiple of the cell data size (48/52).
- * AAL0_52 is a raw cell service and includes an ATM cell header
- * (excluding HEC) at the start of each cell.
- *
- * A single "OAM Rx channel" for all ports may be  enabled by
- * establishing a dedicated OAM Rx connection.
- *
- * The OAM service allows buffers containing 52 byte OAM F4/F5 cells
- * to be transmitted and received over the dedicated OAM channels.
- * HEC is appended/removed, and CRC-10 performed by the NPE. The OAM
- * service offered by AtmdAcc is a raw cell transport service.
- * It is assumed that ITU I.610 procedures that make use of this
- * service are implemented above AtmdAcc.
- *
- * Note that the dedicated OAM connections are established on
- * reserved VPI,VCI, and (in the case of Rx) port values.
- * These values are used purely to descriminate the dedicated OAM channels
- * and do not identify a particular OAM F4/F5 flow. F4/F5 flows may be
- * realised for particluar VPI/VCIs by manipulating the VPI,VCI
- * fields of the ATM cell headers of cells in the buffers passed
- * to AtmdAcc.
- *
- * Calling this function prior to enable the port will fail.
- *
- * @sa ixAtmdAccRxDispatch
- * @sa ixAtmdAccRxVcEnable
- * @sa ixAtmdAccRxVcDisable
- * @sa ixAtmdAccRxVcTryDisconnect
- * @sa ixAtmdAccPortEnable
- *
- * @param port @ref IxAtmLogicalPort [in] - VC identification : logical PHY port
- *                  [@a IX_UTOPIA_PORT_0 .. @a IX_UTOPIA_MAX_PORTS - 1]
- * @param vpi unsigned int [in] - VC identification : ATM Vpi [0..255] or IX_ATMDACC_OAM_VPI
- * @param vci unsigned int [in] - VC identification : ATM Vci [0..65535] or IX_ATMDACC_OAM_VCI
- * @param aalServiceType @ref IxAtmdAccAalType [in] - type of service: AAL5, AAL0_48, AAL0_52, or OAM
- * @param rxQueueId @ref IxAtmRxQueueId [in] - this identifieds which of two Qs the VC
- *     should use.when icoming traffic is processed
- * @param userCallbackId @ref IxAtmdAccUserId [in] - user Id used later as a parameter to
- *     the supplied rxCallback.
- * @param rxCallback [in] @ref IxAtmdAccRxVxRxCallback - function called when mbufs are received.
- *     This parameter cannot be a null pointer.
- * @param bufferFreeCallback [in] - function to be called to return
- *     ownership of buffers to IxAtmdAcc user.
- * @param minimumReplenishCount unsigned int [in] -  For AAL5/AAL0 the number of free mbufs
- *     to be used with this channel. Use a high number when the expected traffic
- *     rate on this channel is high, or when the user's mbufs are small, or when
- *     the RxVcFreeLow Notification has to be invoked less often. When this
- *     value is IX_ATMDACC_DEFAULT_REPLENISH_COUNT, the minimum of
- *     resources  will be used. Depending on traffic rate, pdu
- *     size and mbuf size, rxfree queue size, polling/interrupt rate, this value may
- *     require to be replaced by a different value in the range 1-128
- *     For OAM the rxFree queue size is fixed by atmdAcc and this parameter is ignored.
- * @param connIdPtr @ref IxAtmConnId [out] - pointer to a connection Id
- *     This parameter cannot be a null pointer.
- * @param npeVcIdPtr @ref IxAtmNpeRxVcId [out] - pointer to an npe Vc Id
- *     This parameter cannot be a null pointer.
- *
- * @return @li IX_SUCCESS successful call to IxAtmdAccRxVcConnect
- * @return @li IX_ATMDACC_BUSY cannot process this request :
- *         no VC is available
- * @return @li IX_FAIL
- *             parameter error,
- *             VC already in use,
- *             attempt to connect AAL service on reserved OAM VPI/VCI,
- *             attempt to connect OAM service on VPI/VCI other than the reserved OAM VPI/VCI,
- *             port is not initialised,
- *             or some other error occurs during processing.
- *
- */
-PUBLIC IX_STATUS ixAtmdAccRxVcConnect (IxAtmLogicalPort port,
-                      unsigned int vpi,
-                      unsigned int vci,
-                      IxAtmdAccAalType aalServiceType,
-                      IxAtmRxQueueId rxQueueId,
-                      IxAtmdAccUserId userCallbackId,
-                      IxAtmdAccRxVcRxCallback rxCallback,
-                      unsigned int minimumReplenishCount,
-                      IxAtmConnId * connIdPtr,
-                      IxAtmNpeRxVcId * npeVcIdPtr );
-
-/**
- *
- * @ingroup IxAtmdAccAPI
- * 
- * @fn ixAtmdAccRxVcFreeReplenish (IxAtmConnId connId,
-                        IX_OSAL_MBUF * mbufPtr)
- *
- * @brief Provide free mbufs for data reception on a connection.
- *
- * This function provides mbufs for data reception by the hardware. This
- * function needs to be called by the user on a regular basis to ensure
- * no packet loss. Providing free buffers is a connection-based feature;
- * each connection can have different requirements in terms of buffer size
- * number of buffers, recycling rate. This function could be invoked from
- * within the context of a @a IxAtmdAccRxVcFreeLowCallback() callback
- * for a particular VC
- *
- * Mbufs provided through this function call can be chained. They will be
- * unchained internally. A call to this function with chained mbufs or
- * multiple calls with unchained mbufs are equivalent, but calls with
- * unchained mbufs are more efficients.
- *
- * Mbufs provided to this interface need to be able to hold at least one
- * full cell payload (48/52 bytes, depending on service type).
- * Chained buffers with a size less than the size supported by the hardware
- * will be returned through the rx callback provided during the connect step.
- *
- * Failing to invoke this function prior to enabling the RX traffic
- * can result in packet loss.
- *
- * This function is not reentrant for the same connId.
- *
- * This function does not use system resources and can be
- * invoked from an interrupt context.
- *
- * @note - Over replenish is detected, and extra mbufs are returned through
- *         the rx callback provided during the connect step.
- *
- * @note - Mbuf provided to the replenish function should have a length greater or
- *         equal to 48/52 bytes according to service type.
- *
- * @note - The memory cache of mMbuf payload should be invalidated prior to Mbuf
- *         submission. Flushing the Mbuf headers is handled by IxAtmdAcc.
- *
- * @note - When a chained mbuf is provided, this function process the mbufs
- *         up to the hardware limit and invokes the user-supplied callback
- *         to release extra buffers.
- *
- * @sa ixAtmdAccRxVcFreeLowCallbackRegister
- * @sa IxAtmdAccRxVcFreeLowCallback
- * @sa ixAtmdAccRxVcConnect
- *
- * @param connId @ref IxAtmConnId [in] - connection Id as returned from a succesfull call to
- *        @a IxAtmdAccRxVcConnect()
- * @param mbufPtr @ref IX_OSAL_MBUF [in] - pointer to a mbuf structure to be used for data
- *        reception. The mbuf pointed to by this parameter can be chained
- *        to an other mbuf.
- *
- * @return @li IX_SUCCESS successful call to @a ixAtmdAccRxVcFreeReplenish()
- *          and the mbuf is now ready to use for incoming traffic.
- * @return @li IX_ATMDACC_BUSY cannot process this request because
- *         the max number of outstanding free buffers has been reached
- *         or the internal resources have exhausted for this VC.
- *         The user is responsible for retrying this request later.
- * @return @li IX_FAIL cannot process this request because of parameter
- *         errors or some unspecified internal error has occurred.
- *
- * @note - It is not always guaranteed the replenish step to be as fast as the
- *   hardware is consuming Rx Free mbufs. There is nothing in IxAtmdAcc to
- *   guarantee that replenish reaches the rxFree threshold level. If the
- *   threshold level is not reached, the next rxFree low notification for
- *   this channel will not be triggered.
- *   The preferred ways to replenish can be as follows (depending on
- *   applications and implementations) :
- *   @li Replenish in a rxFree low notification until the function
- *       ixAtmdAccRxVcFreeReplenish() returns IX_ATMDACC_BUSY
- *   @li Query the queue level using @sa ixAtmdAccRxVcFreeEntriesQuery, then
- *     , replenish using @a ixAtmdAccRxVcFreeReplenish(), then query the queue
- *       level again, and replenish if the threshold is still not reached.
- *   @li Trigger replenish from an other event source and use rxFree starvation
- *       to throttle the Rx traffic.
- *
- */
-PUBLIC IX_STATUS ixAtmdAccRxVcFreeReplenish (IxAtmConnId connId,
-                        IX_OSAL_MBUF * mbufPtr);
-
-/**
- *
- * @ingroup IxAtmdAccAPI
- * 
- * @fn ixAtmdAccRxVcFreeLowCallbackRegister (IxAtmConnId connId,
-                                    unsigned int numberOfMbufs,
-                                    IxAtmdAccRxVcFreeLowCallback callback)
- *
- * @brief Configure the RX Free threshold value and register a callback
- * to handle threshold notifications.
- *
- * The function ixAtmdAccRxVcFreeLowCallbackRegister sets the threshold value for
- * a particular RX VC. When the number of buffers reaches this threshold
- * the callback is invoked.
- *
- * This function should be called once per VC before RX traffic is
- * enabled.This function will fail if the curent level of the free buffers
- * is equal or less than the threshold value.
- *
- * @sa ixAtmdAccRxVcFreeLowCallbackRegister
- * @sa IxAtmdAccRxVcFreeLowCallback
- * @sa ixAtmdAccRxVcFreeReplenish
- * @sa ixAtmdAccRxVcFreeEntriesQuery
- * @sa ixAtmdAccRxVcConnect
- *
- * @param connId @ref IxAtmConnId [in] - connection Id as resulted from a succesfull call
- *        to @a IxAtmdAccRxVcConnect()
- * @param numberOfMbufs unsigned int [in] - threshold number of buffers. This number
- *        has to be a power of 2, one of the values 0,1,2,4,8,16,32....
- *        The maximum value cannot be more than half of the rxFree queue
- *        size (which can be retrieved using @a ixAtmdAccRxVcFreeEntriesQuery()
- *        before any use of the @a ixAtmdAccRxVcFreeReplenish() function)
- * @param callback @ref IxAtmdAccRxVcFreeLowCallback [in] - function telling the user that the number of
- *        free buffers has reduced to the threshold value.
- *
- * @return @li IX_SUCCESS Threshold set successfully.
- * @return @li IX_FAIL parameter error or the current number of free buffers
- *              is less than or equal to the threshold supplied or some
- *              unspecified error has occrred.
- *
- * @note - the callback will be called when the threshold level will drop from
- *        exactly (numberOfMbufs + 1) to (numberOfMbufs).
- *
- */
-PUBLIC IX_STATUS ixAtmdAccRxVcFreeLowCallbackRegister (IxAtmConnId connId,
-    unsigned int numberOfMbufs,
-    IxAtmdAccRxVcFreeLowCallback callback);
-
-/**
- *
- * @ingroup IxAtmdAccAPI
- *
- * @fn ixAtmdAccRxVcFreeEntriesQuery (IxAtmConnId connId,
-                         unsigned int *numberOfMbufsPtr)
- *
- * @brief Get the number of rx mbufs the system can accept to replenish the
- *       the rx reception mechanism on a particular channel
- *
- * The ixAtmdAccRxVcFreeEntriesQuery function is used to retrieve the current
- * number of available mbuf entries for reception, on a per-VC basis. This
- * function can be used to know the number of mbufs which can be provided
- * using @a ixAtmdAccRxVcFreeReplenish().
- *
- * This function can be used from a timer context, or can be associated
- * with a threshold event, or can be used inside an active polling
- * mechanism which is under user control.
- *
- * This function is reentrant and does not use system resources and can
- * be invoked from an interrupt context.
- *
- * @param connId @ref IxAtmConnId [in] - connection Id as resulted from a succesfull call
- *        to @a IxAtmdAccRxVcConnect()
- * @param numberOfMbufsPtr unsigned int [out] - Pointer to the number of available entries.
- *      . This parameter cannot be a null pointer.
- *
- * @return @li IX_SUCCESS the current number of mbufs not yet used for incoming traffic
- * @return @li IX_FAIL invalid parameter
- *
- * @sa ixAtmdAccRxVcFreeReplenish
- *
- */
-PUBLIC IX_STATUS ixAtmdAccRxVcFreeEntriesQuery (IxAtmConnId connId,
-                         unsigned int *numberOfMbufsPtr);
-
-/**
- *
- * @ingroup IxAtmdAccAPI
- *
- * @fn ixAtmdAccRxVcEnable (IxAtmConnId connId)
- *
- * @brief Start the RX service on a VC.
- *
- * This functions kicks-off the traffic reception for a particular VC.
- * Once invoked, incoming PDUs will be made available by the hardware
- * and are eventually directed to the @a IxAtmdAccRxVcRxCallback() callback
- * registered for the connection.
- *
- * If the traffic is already running, this function returns IX_SUCCESS.
- * This function can be invoked many times.
- *
- * IxAtmdAccRxVcFreeLowCallback event will occur only after
- * @a ixAtmdAccRxVcEnable() function is invoked.
- *
- * Before using this function, the @a ixAtmdAccRxVcFreeReplenish() function
- * has to be used to replenish the RX Free queue. If not, incoming traffic
- * may be discarded.and in the case of interrupt driven reception the
- * @a IxAtmdAccRxVcFreeLowCallback() callback may be invoked as a side effect
- * during a replenish action.
- *
- * This function is not reentrant and should not be used inside an
- * interrupt context.
- *
- * For an VC connection this function can be called after a call to
- * @a ixAtmdAccRxVcDisable() and should not be called after
- * @a ixAtmdAccRxVcTryDisconnect()
- *
- * @sa ixAtmdAccRxVcDisable
- * @sa ixAtmdAccRxVcConnect
- * @sa ixAtmdAccRxVcFreeReplenish
- *
- * @param connId @ref IxAtmConnId [in] - connection Id as resulted from a succesfull call
- * to @a IxAtmdAccRxVcConnect()
- *
- * @return @li IX_SUCCESS successful call to ixAtmdAccRxVcEnable
- * @return @li IX_ATMDACC_WARNING the channel is already enabled
- * @return @li IX_FAIL invalid parameters or some unspecified internal
- *         error occured.
- *
- */
-PUBLIC IX_STATUS ixAtmdAccRxVcEnable (IxAtmConnId connId);
-
-/**
- *
- * @ingroup IxAtmdAccAPI
- * 
- * @fn ixAtmdAccRxVcDisable (IxAtmConnId connId)
- *
- * @brief Stop the RX service on a VC.
- *
- * This functions stops the traffic reception for a particular VC connection.
- *
- * Once invoked, incoming Pdus are discarded by the hardware. Any Pdus
- * pending will be freed to the user
- *
- * Hence once this function returns no more receive callbacks will be
- * called for that VC. However, buffer free callbacks will be invoked
- * until such time as all buffers supplied by the user have been freed
- * back to the user
- *
- * Calling this function doe not invalidate the connId.
- * @a ixAtmdAccRxVcEnable() can be invoked to enable Pdu reception again.
- *
- * If the traffic is already stopped, this function returns IX_SUCCESS.
- *
- * This function is not reentrant and should not be used inside an
- * interrupt context.
- *
- * @sa ixAtmdAccRxVcConnect
- * @sa ixAtmdAccRxVcEnable
- * @sa ixAtmdAccRxVcDisable
- *
- * @param connId @ref IxAtmConnId [in] - connection Id as resulted from a succesfull call to @a
- *     IxAtmdAccRxVcConnect()
- *
- * @return @li IX_SUCCESS successful call to @a ixAtmdAccRxVcDisable().
- * @return @li IX_ATMDACC_WARNING the channel is already disabled
- * @return @li IX_FAIL invalid parameters or some unspecified internal error occured
- *
- */
-PUBLIC IX_STATUS ixAtmdAccRxVcDisable (IxAtmConnId connId);
-
-/**
- *
- * @ingroup IxAtmdAccAPI
- * 
- * @fn ixAtmdAccRxVcTryDisconnect (IxAtmConnId connId)
- *
- * @brief Disconnect a VC from the RX service.
- *
- * This function deregisters the VC and guarantees that all resources
- * associated with this VC are free. After its execution, the connection
- * Id is not available.
- *
- * This function will fail until such time as all resources allocated to
- * the VC connection have been freed. The user is responsible to delay and
- * call again this function many times until a success status is returned.
- *
- * This function needs internal locks and should not be called from an
- * interrupt context
- *
- * @param connId @ref IxAtmConnId [in] - connection Id as resulted from a succesfull call to
- * @a IxAtmdAccRxVcConnect()
- *
- * @return @li IX_SUCCESS successful call to ixAtmdAccRxVcDisable
- * @return @li IX_ATMDACC_RESOURCES_STILL_ALLOCATED not all resources
- *         associated with the connection have been freed.
- * @return @li IX_FAIL cannot process this request because of a parameter
- *         error
- *
- */
-PUBLIC IX_STATUS ixAtmdAccRxVcTryDisconnect (IxAtmConnId connId);
-
-/* ------------------------------------------------------
-   Part of the IxAtmdAcc interface related to TX traffic
-   ------------------------------------------------------ */
-
-/**
- *
- * @ingroup IxAtmdAccAPI
- * 
- * @fn ixAtmdAccTxVcConnect (IxAtmLogicalPort port,
-                      unsigned int vpi,
-                      unsigned int vci,
-                      IxAtmdAccAalType aalServiceType,
-                      IxAtmdAccUserId userId,
-                      IxAtmdAccTxVcBufferReturnCallback bufferFreeCallback,
-                      IxAtmConnId * connIdPtr)
- *
- * @brief Connect to a Aal Pdu transmit service for a particular
- *        port/vpi/vci and service type.
- *
- * This function allows a user to connect to an Aal5/Aal0/OAM Pdu transmit service
- * for a particular port/vpi/vci. It registers the callback and allocates
- * internal resources and a Connection Id to be used in further API calls
- * related to this VC.
- *
- * The function will setup VC transmit service on the specified on the
- * specified port. A connId is the reference by which IxAtmdAcc refers to a
- * connected VC. This identifier is the result of a succesful call
- * to a connect function. This identifier is invalid after a
- * sucessful call to a disconnect function.
- *
- * This function needs internal locks, and hence  should not be called
- * from an interrupt context.
- *
- * On return from @a ixAtmdAccTxVcConnect() with a failure status, the
- * connection Id parameter is unspecified. Its value cannot be used.
- *
- * Calling this function for the same combination of port, Vpi, Vci and
- * more than once without calling @a ixAtmdAccTxVcTryDisconnect() will result
- * in a failure status.
- *
- * Two AAL0 services supporting 48 or 52 byte cell data are provided.
- * Submitted AAL0 PDUs must be a multiple of the cell data size (48/52).
- * AAL0_52 is a raw cell service the client must format
- * the PDU with an ATM cell header (excluding HEC) at the start of
- * each cell, note that AtmdAcc does not validate the cell headers in
- * a submitted PDU.
- *
- * For the OAM service an "OAM Tx channel" may be enabled for a port
- * by establishing a single dedicated OAM Tx connection on that port.
- *
- * The OAM service allows buffers containing 52 byte OAM F4/F5 cells
- * to be transmitted and received over the dedicated OAM channels.
- * HEC is appended/removed, and CRC-10 performed by the NPE. The OAM
- * service offered by AtmdAcc is a raw cell transport service.
- * It is assumed that ITU I.610 procedures that make use of this
- * service are implemented above AtmdAcc.
- *
- * Note that the dedicated OAM connections are established on
- * reserved VPI,VCI, and (in the case of Rx) port values.
- * These values are used purely to descriminate the dedicated OAM channels
- * and do not identify a particular OAM F4/F5 flow. F4/F5 flows may be
- * realised for particluar VPI/VCIs by manipulating the VPI,VCI
- * fields of the ATM cell headers of cells in the buffers passed
- * to AtmdAcc.
- *
- * Calling this function before enabling the port will fail.
- *
- * @sa ixAtmdAccTxVcTryDisconnect
- * @sa ixAtmdAccPortTxScheduledModeEnable
- * @sa ixAtmdAccPortEnable
- *
- * @param port @ref IxAtmLogicalPort [in] - VC identification : logical PHY port
- *                  [@a IX_UTOPIA_PORT_0 .. @a IX_UTOPIA_MAX_PORTS - 1]
- * @param vpi unsigned int  [in] - VC identification : ATM Vpi [0..255] or IX_ATMDACC_OAM_VPI
- * @param vci unsigned int [in] - VC identification : ATM Vci [0..65535] or IX_ATMDACC_OAM_VCI
- * @param aalServiceType @ref IxAtmdAccAalType [in] - type of service AAL5, AAL0_48, AAL0_52, or OAM
- * @param userId @ref IxAtmdAccUserId [in] - user id to be used later during callbacks related
- *        to this channel
- * @param bufferFreeCallback @ref IxAtmdAccTxVcBufferReturnCallback [in] - function called when mbufs
- *        transmission is complete. This parameter cannot be a null
- *        pointer.
- * @param connIdPtr @ref IxAtmConnId [out] - Pointer to a connection Id.
- *        This parameter cannot be a null pointer.
- *
- * @return @li IX_SUCCESS successful call to @a IxAtmdAccRxVcConnect().
- * @return @li IX_ATMDACC_BUSY cannot process this request
- *         because no VC is available
- * @return @li IX_FAIL
- *             parameter error,
- *             VC already in use,
- *             attempt to connect AAL service on reserved OAM VPI/VCI,
- *             attempt to connect OAM service on VPI/VCI other than the reserved OAM VPI/VCI,
- *             port is not initialised,
- *             or some other error occurs during processing.
- *
- * @note - Unscheduled mode is not supported in ixp425 1.0. Therefore, the
- *       function @a ixAtmdAccPortTxScheduledModeEnable() need to be called
- *       for this port before any establishing a Tx Connection
- */
-PUBLIC IX_STATUS ixAtmdAccTxVcConnect (IxAtmLogicalPort port,
-                      unsigned int vpi,
-                      unsigned int vci,
-                      IxAtmdAccAalType aalServiceType,
-                      IxAtmdAccUserId userId,
-                      IxAtmdAccTxVcBufferReturnCallback bufferFreeCallback,
-                      IxAtmConnId * connIdPtr);
-
-/**
- *
- * @ingroup IxAtmdAccAPI
- *
- * @fn ixAtmdAccTxVcPduSubmit (IxAtmConnId connId,
-                    IX_OSAL_MBUF * mbufPtr,
-                    IxAtmdAccClpStatus clp,
-                    unsigned int numberOfCells)
- *
- * @brief Submit a Pdu for transmission on connection.
- *
- * A data user calls this function to submit an mbufs containing a Pdu
- * to be transmitted. The buffer supplied can be chained and the Pdu it
- * contains must be complete.
- *
- * The transmission behavior of this call depends on the operational mode
- * of the port on which the connection is made.
- *
- * In unscheduled mode the mbuf will be submitted to the hardware
- * immediately if sufficent resource is available. Otherwise the function
- * will return failure.
- *
- * In scheduled mode the buffer is queued internally in IxAtmdAcc. The cell
- * demand is made known to the traffic shaping entity. Cells from the
- * buffers are MUXed onto the port some time later as dictated by the
- * traffic shaping entity. The traffic shaping entity does this by sending
- * transmit schedules to IxAtmdAcc via @a ixAtmdAccPortTxProcess() function call.
- *
- * Note that the dedicated OAM channel is scheduled just like any
- * other channel. This means that any OAM traffic relating to an
- * active AAL0/AAL5 connection will be scheduled independantly of the
- * AAL0/AAL5 traffic for that connection.
- *
- * When transmission is complete, the TX Done mechanism will give the
- * owmnership of these buffers back to the customer. The tx done mechanism
- * must be in operation before transmission is attempted.
- *
- * For AAL0/OAM submitted AAL0 PDUs must be a multiple of the cell data
- * size (48/52). AAL0_52 and OAM are raw cell services, and the client
- * must format the PDU with an ATM cell header (excluding HEC) at the
- * start of each cell, note that AtmdAcc does not validate the cell headers in
- * a submitted PDU.
- *
- *
- * @sa IxAtmdAccTxVcBufferReturnCallback
- * @sa ixAtmdAccTxDoneDispatch
- *
- * @param connId @ref IxAtmConnId [in] - connection Id as resulted from a succesfull call to
- *        @a ixAtmdAccTxVcConnect()
- * @param mbufPtr @ref IX_OSAL_MBUF [in] - pointer to a chained structure of mbufs to transmit.
- *       This parameter cannot be a null pointer.
- * @param clp @ref IxAtmdAccClpStatus [in] - clp indication for this PDU. All cells of this pdu
- *       will be sent with the clp bit set
- * @param numberOfCells unsigned int [in] - number of cells in the PDU.
- *
- * @return @li IX_SUCCESS successful call to @a ixAtmdAccTxVcPduSubmit()
- *             The pdu pointed by the mbufPtr parameter will be
- *             transmitted
- * @return @li IX_ATMDACC_BUSY unable to process this request because
- *             internal resources are all used. The caller is responsible
- *             for retrying this request later.
- * @return @li IX_FAIL unable to process this request because of error
- *             in the parameters (wrong connId supplied,
- *             or wrong mbuf pointer supplied), the total length of all buffers
- *             in the chain should be a multiple of the cell size
- *             ( 48/52 depending on the service type ),
- *             or unspecified error during processing
- *
- * @note - This function in not re-entrant for the same VC (e.g. : two
- *         thread cannot send PDUs for the same VC). But two threads can
- *         safely call this function with a different connection Id
- *
- * @note - In unscheduled mode, this function is not re-entrant on a per
- *         port basis. The size of pdus is limited to 8Kb.
- *
- * @note - 0-length mbufs should be removed from the chain before submission.
- *         The total length of the pdu (sdu + padding +trailer) has to be
- *         updated in the header of the first mbuf of a chain of mbufs.
- *
- * @note - Aal5 trailer information (UUI, CPI, SDU length) has to be supplied
- *         before submission.
- *
- * @note - The payload memory cache should be flushed, if needed, prior to
- *         transmission. Mbuf headers are flushed by IxAtmdAcc
- *
- * @note - This function does not use system resources and can be used
- *         inside an interrupt context
- */
-PUBLIC IX_STATUS ixAtmdAccTxVcPduSubmit (IxAtmConnId connId,
-                    IX_OSAL_MBUF * mbufPtr,
-                    IxAtmdAccClpStatus clp,
-                    unsigned int numberOfCells);
-
-/**
- *
- * @ingroup IxAtmdAccAPI
- *
- * @fn ixAtmdAccTxVcTryDisconnect (IxAtmConnId connId)
- *
- * @brief Disconnect from a Aal Pdu transmit service for a particular
- *        port/vpi/vci.
- *
- * This function deregisters the VC and guarantees that all resources
- * associated with this VC are free. After its execution, the connection
- * Id is not available.
- *
- * This function will fail until such time as all resources allocated to
- * the VC connection have been freed. The user is responsible to delay
- * and call again this function many times until a success status is
- * returned.
- *
- * After its execution, the connection Id is not available.
- *
- * @param connId @ref IxAtmConnId [in] - connection Id as resulted from a succesfull call to
- *        @a ixAtmdAccTxVcConnect()
- *
- * @return @li IX_SUCCESS successful call to @a ixAtmdAccTxVcTryDisconnect()
- * @return @li IX_ATMDACC_RESOURCES_STILL_ALLOCATED not all resources
- *     associated with the connection have been freed. This condition will
- *     disappear after Tx and TxDone is complete for this channel.
- * @return @li IX_FAIL unable to process this request because of errors
- *                     in the parameters (wrong connId supplied)
- *
- * @note - This function needs internal locks and should not be called
- *         from an interrupt context
- *
- * @note - If the @a IX_ATMDACC_RESOURCES_STILL_ALLOCATED error does not
- *     clear after a while, this may be linked to a previous problem
- *     of cell overscheduling. Diabling the port and retry a disconnect
- *     will free the resources associated with this channel.
- *
- * @sa ixAtmdAccPortTxProcess
- *
- */
-PUBLIC IX_STATUS ixAtmdAccTxVcTryDisconnect (IxAtmConnId connId);
-
-#endif /* IXATMDACC_H */
-
-/**
- * @} defgroup IxAtmdAccAPI
- */
-
-
diff --git a/drivers/net/npe/include/IxAtmdAccCtrl.h b/drivers/net/npe/include/IxAtmdAccCtrl.h
deleted file mode 100644
index 1a696b0e66..0000000000
--- a/drivers/net/npe/include/IxAtmdAccCtrl.h
+++ /dev/null
@@ -1,1934 +0,0 @@
-
-/**
- * @file    IxAtmdAccCtrl.h
- *
- * @date    20-Mar-2002
- *
- * @brief IxAtmdAcc Public API
- *
- * This file contains the public API of IxAtmdAcc, related to the
- * control functions of the component.
- *
- * 
- * @par
- * IXP400 SW Release version 2.0
- * 
- * -- Copyright Notice --
- * 
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- * 
- * @par
- * SPDX-License-Identifier:	BSD-3-Clause
- * @par
- * -- End of Copyright Notice --
- */
-
-/* ------------------------------------------------------
-   Doxygen group definitions
-   ------------------------------------------------------ */
-
-/**
- *
- * @defgroup IxAtmdAccCtrlAPI IXP400 ATM Driver Access (IxAtmdAcc) Control API
- *
- * @brief The public API for the IXP400 Atm Driver Control component
- *
- * IxAtmdAcc is the low level interface by which AAL PDU get transmitted
- * to,and received from the Utopia bus
- *
- * This part is related to the Control configuration
- *
- * @{
- */
-
-#ifndef IXATMDACCCTRL_H
-#define IXATMDACCCTRL_H
-
-#include "IxAtmdAcc.h"
-
-/* ------------------------------------------------------
-   AtmdAccCtrl Data Types definition
-   ------------------------------------------------------ */
-
-/**
-*
-* @ingroup IxAtmdAccCtrlAPI
-*
-* @def IX_ATMDACC_PORT_DISABLE_IN_PROGRESS
-*
-* @brief Port enable return code
-*
-* This constant is used to tell IxAtmDAcc user that the port disable
-* functions are not complete. The user can call ixAtmdAccPortDisableComplete()
-* to find out when the disable has finished. The port enable can then proceed.
-*
-*/
-#define IX_ATMDACC_PORT_DISABLE_IN_PROGRESS 5
-
-/**
-*
-* @ingroup IxAtmdAccCtrlAPI
-*
-* @def IX_ATMDACC_ALLPDUS
-*
-* @brief All PDUs
-*
-* This constant is used to tell IxAtmDAcc to process all PDUs from
-* the RX queue or the TX Done
-*
-* @sa IxAtmdAccRxDispatcher
-* @sa IxAtmdAccTxDoneDispatcher
-*
-*/
-#define IX_ATMDACC_ALLPDUS 0xffffffff
-
-/* ------------------------------------------------------
-   Part of the IxAtmdAcc interface related to RX traffic
-   ------------------------------------------------------ */
-
-/**
- *
- * @ingroup IxAtmdAccCtrlAPI
- *
- * @brief Callback prototype for notification of available PDUs for
- * an Rx Q.
- *
- * This a protoype for a function which is called when there is at
- * least one Pdu available for processing on a particular Rx Q.
- *
- * This function should call @a ixAtmdAccRxDispatch() with
- * the aprropriate number of parameters to read and process the Rx Q.
- *
- * @sa ixAtmdAccRxDispatch
- * @sa ixAtmdAccRxVcConnect
- * @sa ixAtmdAccRxDispatcherRegister
- *
- * @param rxQueueId @ref IxAtmRxQueueId [in] indicates which RX queue to has Pdus to process.
- * @param numberOfPdusToProcess unsigned int [in] indicates the minimum number of
- *        PDUs available to process all PDUs from the queue.
- * @param reservedPtr unsigned int* [out] pointer to a int location which can
- *        be written to, but does not retain written values. This is
- *        provided to make this prototype compatible
- *        with @a ixAtmdAccRxDispatch()
- *
- * @return @li int - ignored.
- *
- */
-typedef IX_STATUS (*IxAtmdAccRxDispatcher) (IxAtmRxQueueId rxQueueId,
-                         unsigned int numberOfPdusToProcess,
-                         unsigned int *reservedPtr);
-
-/* ------------------------------------------------------
-   Part of the IxAtmdAcc interface related to TX traffic
-   ------------------------------------------------------ */
-
-/**
- *
- * @ingroup IxAtmdAccCtrlAPI
- *
- * @brief Callback prototype for transmitted mbuf when threshold level is
- *        crossed.
- *
- * IxAtmdAccTxDoneDispatcher is the prototype of the user function
- * which get called when pdus are completely transmitted. This function
- * is likely to call the @a ixAtmdAccTxDoneDispatch() function.
- *
- * This function is called when the number of available pdus for
- * reception is crossing the threshold level as defined
- * in @a ixAtmdAccTxDoneDispatcherRegister()
- *
- * This function is called inside an Qmgr dispatch context. No system
- * resource or interrupt-unsafe feature should be used inside this
- * callback.
- *
- * Transmitted buffers recycling implementation is a sytem-wide mechanism
- * and needs to be set before any traffic is started. If this threshold
- * mechanism is not used, the user is responsible for polling the
- * transmitted buffers with @a ixAtmdAccTxDoneDispatch()
- * and @a ixAtmdAccTxDoneLevelQuery() functions.
- *
- * @sa ixAtmdAccTxDoneDispatcherRegister
- * @sa ixAtmdAccTxDoneDispatch
- * @sa ixAtmdAccTxDoneLevelQuery
- *
- * @param numberOfPdusToProcess unsigned int [in] - The current number of pdus currently
- *        available for recycling
- * @param *reservedPtr unsigned int [out] - pointer to a int location which can be
- *        written to but does not retain written values. This is provided
- *        to make this prototype compatible
- *        with @a ixAtmdAccTxDoneDispatch()
- *
- * @return @li IX_SUCCESS This is provided to make
- *    this prototype compatible with @a ixAtmdAccTxDoneDispatch()
- * @return @li IX_FAIL invalid parameters or some unspecified internal
- *    error occured. This is provided to make
- *    this prototype compatible with @a ixAtmdAccTxDoneDispatch()
- *
- */
-typedef IX_STATUS (*IxAtmdAccTxDoneDispatcher) (unsigned int numberOfPdusToProcess,
-                                                unsigned int *reservedPtr);
-
-/**
-*
-* @ingroup IxAtmdAccCtrlAPI
-*
-* @brief Notification that the threshold number of scheduled cells
-* remains in a port's transmit Q.
-*
-* The is the prototype for of the user notification function which
-* gets called on a per-port basis, when the number of remaining
-* scheduled cells to be transmitted decreases to the threshold level.
-* The number of cells passed as a parameter can be used for scheduling
-* purposes as the maximum number of cells that can be passed in a
-* schedule table to the @a ixAtmdAccPortTxProcess() function.
-*
-* @sa ixAtmdAccPortTxCallbackRegister
-* @sa ixAtmdAccPortTxProcess
-* @sa ixAtmdAccPortTxFreeEntriesQuery
-*
-* @param port @ref IxAtmLogicalPort [in] - logical PHY port [@a IX_UTOPIA_PORT_0 .. @a IX_UTOPIA_MAX_PORTS - 1]
-* @param numberOfAvailableCells unsigned int [in] - number of available
-*        cell entries.for the port
-*
-* @note - This functions shall not use system resources when used
-*         inside an interrupt context.
-*
-*/
-typedef void (*IxAtmdAccPortTxLowCallback) (IxAtmLogicalPort port,
-                           unsigned int numberOfAvailableCells);
-
-/**
-*
-* @ingroup IxAtmdAccCtrlAPI
-*
-* @brief  Prototype to submit cells for transmission
-*
-* IxAtmdAccTxVcDemandUpdateCallback is the prototype of the callback
-* function used by AtmD to notify an ATM Scheduler that the user of
-* a VC has submitted cells for transmission.
-*
-* @sa IxAtmdAccTxVcDemandUpdateCallback
-* @sa IxAtmdAccTxVcDemandClearCallback
-* @sa IxAtmdAccTxSchVcIdGetCallback
-* @sa ixAtmdAccPortTxScheduledModeEnable
-*
-* @param port @ref IxAtmLogicalPort [in] - Specifies the ATM port on which the VC to be updated
-*        is established
-* @param vcId int [in] - Identifies the VC to be updated. This is the value
-*        returned by the @a IxAtmdAccTxSchVcIdGetCallback() call .
-* @param numberOfCells unsigned int [in] - Indicates how many ATM cells should be added
-*        to the queue for this VC.
-*
-* @return @li IX_SUCCESS the function is registering the cell demand for
-*        this VC.
-* @return @li IX_FAIL the function cannot register cell for this VC : the
-*         scheduler maybe overloaded or misconfigured
-*
-*/
-typedef IX_STATUS (*IxAtmdAccTxVcDemandUpdateCallback) (IxAtmLogicalPort port,
-                        int vcId,
-                        unsigned int numberOfCells);
-
-/**
-*
-* @ingroup IxAtmdAccCtrlAPI
-*
-* @brief  prototype to  remove all currently queued cells from a
-* registered VC
-*
-* IxAtmdAccTxVcDemandClearCallback is the prototype of the function
-* to remove all currently queued cells from a registered VC. The
-* pending cell count for the specified VC is reset to zero. After the
-* use of this callback, the scheduler shall not schedule more cells
-* for this VC.
-*
-* This callback function is called during a VC disconnection
-* @a ixAtmdAccTxVcTryDisconnect()
-*
-* @sa IxAtmdAccTxVcDemandUpdateCallback
-* @sa IxAtmdAccTxVcDemandClearCallback
-* @sa IxAtmdAccTxSchVcIdGetCallback
-* @sa ixAtmdAccPortTxScheduledModeEnable
-* @sa ixAtmdAccTxVcTryDisconnect
-*
-* @param port @ref IxAtmLogicalPort [in] - Specifies the ATM port on which the VC to be cleared
-*        is established
-* @param vcId int [in] - Identifies the VC to be cleared. This is the value
-*        returned by the @a IxAtmdAccTxSchVcIdGetCallback() call .
-*
-* @return none
-*
-*/
-typedef void (*IxAtmdAccTxVcDemandClearCallback) (IxAtmLogicalPort port,
-                             int vcId);
-
-/**
-*
-* @ingroup IxAtmdAccCtrlAPI
-*
-* @brief  prototype to get a scheduler vc id
-*
-* IxAtmdAccTxSchVcIdGetCallback is the prototype of the function to get
-* a scheduler vcId
-*
-* @sa IxAtmdAccTxVcDemandUpdateCallback
-* @sa IxAtmdAccTxVcDemandClearCallback
-* @sa IxAtmdAccTxSchVcIdGetCallback
-* @sa ixAtmdAccPortTxScheduledModeEnable
-*
-* @param port @ref IxAtmLogicalPort [in] - Specifies the ATM logical port on which the VC is
-*        established
-* @param vpi unsigned int [in] - For AAL0/AAL5 specifies the ATM vpi on which the 
-*                 VC is established.
-*                 For OAM specifies the dedicated "OAM Tx channel" VPI.
-* @param vci unsigned int [in] - For AAL0/AAL5 specifies the ATM vci on which the 
-*                 VC is established.
-*                 For OAM specifies the dedicated "OAM Tx channel" VCI.
-* @param connId @ref IxAtmConnId [in] - specifies the IxAtmdAcc connection Id already
-*        associated with this VC
-* @param vcId int* [out] - pointer to a vcId
-*
-* @return @li IX_SUCCESS the function is returning a Scheduler vcId for this
-*         VC
-* @return @li IX_FAIL the function cannot process scheduling for this VC.
-*                 the contents of vcId is unspecified
-*
-*/
-typedef IX_STATUS (*IxAtmdAccTxSchVcIdGetCallback) (IxAtmLogicalPort port,
-                               unsigned int vpi,
-                               unsigned int vci,
-                               IxAtmConnId connId,
-                               int *vcId);
-
-/* ------------------------------------------------------
-   Part of the IxAtmdAcc interface related to RX traffic
-   ------------------------------------------------------ */
-
-/**
- *
- * @ingroup IxAtmdAccCtrlAPI
- *
- * @fn ixAtmdAccRxDispatcherRegister (
-                          IxAtmRxQueueId queueId,
-                          IxAtmdAccRxDispatcher callback)
- *
- * @brief Register a notification callback to be invoked when there is
- * at least one entry on a particular Rx queue.
- *
- * This function registers a callback to be invoked when there is at
- * least one entry in a particular queue. The registered callback is
- * called every time when the hardware adds one or more pdus to the
- * specified Rx queue.
- *
- * This function cannot be used when a Rx Vc using this queue is
- * already existing.
- *
- * @note -The callback function can be the API function
- *       @a ixAtmdAccRxDispatch() : every time the threhold level
- *       of the queue is reached, the ixAtmdAccRxDispatch() is
- *       invoked to remove all entries from the queue.
- *
- * @sa ixAtmdAccRxDispatch
- * @sa IxAtmdAccRxDispatcher
- *
- * @param queueId @ref IxAtmRxQueueId [in] RX queue identification
- * @param callback @ref IxAtmdAccRxDispatcher [in] function triggering the delivery of incoming
- *        traffic. This parameter cannot be a null pointer.
- *
- * @return @li IX_SUCCESS Successful call to @a ixAtmdAccRxDispatcherRegister()
- * @return @li IX_FAIL error in the parameters, or there is an
- *             already active RX VC for this queue or some unspecified
- *             internal error occurred.
- *
- */
-PUBLIC IX_STATUS ixAtmdAccRxDispatcherRegister (
-                          IxAtmRxQueueId queueId,
-                          IxAtmdAccRxDispatcher callback);
-
-/**
- *
- * @ingroup IxAtmdAccCtrlAPI
- *
- * @fn ixAtmdAccRxDispatch (IxAtmRxQueueId rxQueueId,
-    unsigned int numberOfPdusToProcess,
-    unsigned int *numberOfPdusProcessedPtr)
- *
- *
- * @brief Control function which executes Rx processing for a particular
- * Rx stream.
- *
- * The @a IxAtmdAccRxDispatch() function is used to process received Pdus
- * available from one of the two incoming RX streams. When this function
- * is invoked, the incoming traffic (up to the number of PDUs passed as
- * a parameter) will be transferred to the IxAtmdAcc users through the
- * callback @a IxAtmdAccRxVcRxCallback(), as registered during the
- * @a ixAtmdAccRxVcConnect() call.
- *
- * The user receive callbacks will be executed in the context of this
- * function.
- *
- * Failing to use this function on a regular basis when there is traffic
- * will block incoming traffic and can result in Pdus being dropped by
- * the hardware.
- *
- * This should be used to control when received pdus are handed off from
- * the hardware to Aal users from a particluar stream. The function can
- * be used from a timer context, or can be registered as a callback in
- * response to an rx stream threshold event, or can be used inside an
- * active polling mechanism which is under user control.
- *
- * @note - The signature of this function is directly compatible with the
- * callback prototype which can be register with @a ixAtmdAccRxDispatcherRegister().
- *
- * @sa ixAtmdAccRxDispatcherRegister
- * @sa IxAtmdAccRxVcRxCallback
- * @sa ixAtmdAccRxVcFreeEntriesQuery
- *
- * @param rxQueueId @ref IxAtmRxQueueId [in] - indicates which RX queue to process.
- * @param numberOfPdusToProcess unsigned int [in] - indicates the maxiumum number of PDU to
- *     remove from the RX queue. A value of IX_ATMDACC_ALLPDUS indicates
- *     to process all PDUs from the queue. This includes at least the PDUs
- *     in the queue when the fuction is invoked. Because of real-time
- *     constraints, there is no guarantee thatthe queue will be empty
- *     when the function exits. If this parameter is greater than the
- *     number of entries of the queues, the function will succeed
- *     and the parameter numberOfPdusProcessedPtr will reflect the exact
- *     number of PDUs processed.
- * @param *numberOfPdusProcessedPtr unsigned int [out] - indicates the actual number of PDU
- *     processed during this call. This parameter cannot be a null
- *     pointer.
- *
- * @return @li IX_SUCCESS the number of PDUs as indicated in
- *     numberOfPdusProcessedPtr are removed from the RX queue and the VC callback
- *     are called.
- * @return @li IX_FAIL invalid parameters or some unspecified internal
- *     error occured.
- *
- */
-PUBLIC IX_STATUS ixAtmdAccRxDispatch (IxAtmRxQueueId rxQueueId,
-    unsigned int numberOfPdusToProcess,
-    unsigned int *numberOfPdusProcessedPtr);
-
-/**
- *
- * @ingroup IxAtmdAccCtrlAPI
- * 
- * @fn ixAtmdAccRxLevelQuery (IxAtmRxQueueId rxQueueId,
-                     unsigned int *numberOfPdusPtr)
- *
- * @brief Query the number of entries in a particular RX queue.
- *
- * This function is used to retrieve the number of pdus received by
- * the hardware and ready for distribution to users.
- *
- * @param rxQueueId @ref IxAtmRxQueueId [in] - indicates which of two RX queues to query.
- * @param numberOfPdusPtr unsigned int* [out] - Pointer to store the number of available
- *        PDUs in the RX queue. This parameter cannot be a null pointer.
- *
- * @return @li IX_SUCCESS the value in numberOfPdusPtr specifies the
- *         number of incoming pdus waiting in this queue
- * @return @li IX_FAIL an error occurs during processing.
- *         The value in numberOfPdusPtr is unspecified.
- *
- * @note - This function is reentrant, doesn't use system resources
- *         and can be used from an interrupt context.
- *
- */
-PUBLIC IX_STATUS ixAtmdAccRxLevelQuery (IxAtmRxQueueId rxQueueId,
-                     unsigned int *numberOfPdusPtr);
-
-/**
- *
- * @ingroup IxAtmdAccCtrlAPI
- *
- * @fn ixAtmdAccRxQueueSizeQuery (IxAtmRxQueueId rxQueueId,
-                     unsigned int *numberOfPdusPtr)
- *
- * @brief Query the size of a particular RX queue.
- *
- * This function is used to retrieve the number of pdus the system is
- * able to queue when reception is complete.
- *
- * @param rxQueueId @ref IxAtmRxQueueId [in] - indicates which of two RX queues to query.
- * @param numberOfPdusPtr unsigned int* [out] - Pointer to store the number of pdus
- *         the system is able to queue in the RX queue. This parameter
- *         cannot be a null pointer.
- *
- * @return @li IX_SUCCESS the value in numberOfPdusPtr specifies the
- *         number of pdus the system is able to queue.
- * @return @li IX_FAIL an error occurs during processing.
- *         The value in numberOfPdusPtr is unspecified.
- *
- * @note - This function is reentrant, doesn't use system resources
- *         and can be used from an interrupt context.
- *
- */
-PUBLIC IX_STATUS ixAtmdAccRxQueueSizeQuery (IxAtmRxQueueId rxQueueId,
-                     unsigned int *numberOfPdusPtr);
-
-/* ------------------------------------------------------
-   Part of the IxAtmdAcc interface related to TX traffic
-   ------------------------------------------------------ */
-
-/**
- *
- * @ingroup IxAtmdAccCtrlAPI
- *
- * @fn ixAtmdAccPortTxFreeEntriesQuery (IxAtmLogicalPort port,
-                         unsigned int *numberOfCellsPtr)
- *
- * @brief Get the number of available cells the system can accept for
- *       transmission.
- *
- * The function is used to retrieve the number of cells that can be
- * queued for transmission to the hardware.
- *
- * This number is based on the worst schedule table where one cell
- * is stored in one schedule table entry, depending on the pdus size
- * and mbuf size and fragmentation.
- *
- * This function doesn't use system resources and can be used from a
- * timer context, or can be associated with a threshold event, or can
- * be used inside an active polling mechanism
- *
- * @param port @ref IxAtmLogicalPort [in] - logical PHY port [@a IX_UTOPIA_PORT_0 .. @a IX_UTOPIA_MAX_PORTS - 1]
- * @param numberOfCellsPtr unsigned int* [out] - number of available cells.
- *                   This parameter cannot be a null pointer.
- *
- * @sa ixAtmdAccPortTxProcess
- *
- * @return @li IX_SUCCESS numberOfCellsPtr contains the number of cells that can be scheduled
- *         for this port.
- * @return @li IX_FAIL error in the parameters, or some processing error
- *         occured.
- *
- */
-PUBLIC IX_STATUS ixAtmdAccPortTxFreeEntriesQuery (IxAtmLogicalPort port,
-                         unsigned int *numberOfCellsPtr);
-
-/**
- *
- * @ingroup IxAtmdAccCtrlAPI
- * 
- * @fn ixAtmdAccPortTxCallbackRegister (IxAtmLogicalPort port,
-                       unsigned int numberOfCells,
-                       IxAtmdAccPortTxLowCallback callback)
- *
- * @brief Configure the Tx port threshold value and register a callback to handle
- * threshold notifications.
- *
- * This function sets the threshold in cells
- *
- * @sa ixAtmdAccPortTxCallbackRegister
- * @sa ixAtmdAccPortTxProcess
- * @sa ixAtmdAccPortTxFreeEntriesQuery
- *
- * @param port @ref IxAtmLogicalPort [in] - logical PHY port [@a IX_UTOPIA_PORT_0 .. @a IX_UTOPIA_MAX_PORTS - 1]
- * @param numberOfCells unsigned int [in] - threshold value which triggers the callback
- *        invocation, This number has to be one of the
- *        values 0,1,2,4,8,16,32 ....
- *        The maximum value cannot be more than half of the txVc queue
- *        size (which can be retrieved using @a ixAtmdAccPortTxFreeEntriesQuery()
- *        before any Tx traffic is sent for this port)
- * @param callback @ref IxAtmdAccPortTxLowCallback [in] - callback function to invoke when the threshold
- *                 level is reached.
- *                 This parameter cannot be a null pointer.
- *
- * @return @li IX_SUCCESS Successful call to @a ixAtmdAccPortTxCallbackRegister()
- * @return @li IX_FAIL error in the parameters, Tx channel already set for this port
- *             threshold level is not correct or within the range regarding the
- *             queue size:or unspecified error during processing:
- *
- * @note - This callback function get called when the threshold level drops from
- *         (numberOfCells+1) cells to (numberOfCells) cells
- *
- * @note - This function should be called during system initialisation,
- *         outside an interrupt context
- *
- */
-PUBLIC IX_STATUS ixAtmdAccPortTxCallbackRegister (IxAtmLogicalPort port,
-                       unsigned int numberOfCells,
-                       IxAtmdAccPortTxLowCallback callback);
-
-/**
- *
- * @ingroup IxAtmdAccCtrlAPI
- *
- * @fn ixAtmdAccPortTxScheduledModeEnable (IxAtmLogicalPort port,
-    IxAtmdAccTxVcDemandUpdateCallback vcDemandUpdateCallback,
-    IxAtmdAccTxVcDemandClearCallback vcDemandClearCallback,
-    IxAtmdAccTxSchVcIdGetCallback vcIdGetCallback)
- *
- * @brief Put the port into Scheduled Mode
- *
- * This function puts the specified port into scheduled mode of
- * transmission which means an external s/w entity controls the
- * transmission of cells on this port. This faciltates traffic shaping on
- * the port.
- *
- * Any buffers submitted on a VC for this port will be queued in IxAtmdAcc.
- * The transmission of these buffers to and by the hardware will be driven
- * by a transmit schedule submitted regulary in calls to
- * @a ixAtmdAccPortTxProcess() by traffic shaping entity.
- *
- * The transmit schedule is expected to be dynamic in nature based on
- * the demand in cells for each VC on the port. Hence the callback
- * parameters provided to this function allow IxAtmdAcc to inform the
- * shaping entity of demand changes for each VC on the port.
- *
- * By default a port is in Unscheduled Mode so if this function is not
- * called, transmission of data is done without sheduling rules, on a
- * first-come, first-out basis.
- *
- * Once a port is put in scheduled mode it cannot be reverted to
- * un-scheduled mode. Note that unscheduled mode is not supported
- * in ixp425 1.0
- *
- * @note - This function should be called before any VCs have be
- * connected on a port. Otherwise this function call will return failure.
- *
- * @note - This function uses internal locks and should not be called from
- * an interrupt context
- *
- * @sa IxAtmdAccTxVcDemandUpdateCallback
- * @sa IxAtmdAccTxVcDemandClearCallback
- * @sa IxAtmdAccTxSchVcIdGetCallback
- * @sa ixAtmdAccPortTxProcess
- *
- * @param port @ref IxAtmLogicalPort [in] - logical PHY port [@a IX_UTOPIA_PORT_0 .. @a IX_UTOPIA_MAX_PORTS - 1]
- * @param vcDemandUpdateCallback @ref IxAtmdAccTxVcDemandUpdateCallback [in] - callback function used to update
- *     the number of outstanding cells for transmission. This parameter
- *     cannot be a null pointer.
- * @param vcDemandClearCallback @ref IxAtmdAccTxVcDemandClearCallback [in] - callback function used to remove all
- *     clear the number of outstanding cells for a VC. This parameter
- *     cannot be a null pointer.
- * @param vcIdGetCallback @ref IxAtmdAccTxSchVcIdGetCallback [in] - callback function used to exchange vc
- *     Identifiers between IxAtmdAcc and the entity supplying the
- *     transmit schedule. This parameter cannot be a null pointer.
- *
- * @return @li IX_SUCCESS scheduler registration is complete and the port
- *         is now in scheduled mode.
- * @return @li IX_FAIL failed (wrong parameters, or traffic is already
- *         enabled on this port, possibly without ATM shaping)
- *
- */
-PUBLIC IX_STATUS ixAtmdAccPortTxScheduledModeEnable (IxAtmLogicalPort port,
-    IxAtmdAccTxVcDemandUpdateCallback vcDemandUpdateCallback,
-    IxAtmdAccTxVcDemandClearCallback vcDemandClearCallback,
-    IxAtmdAccTxSchVcIdGetCallback vcIdGetCallback);
-
-/**
- *
- * @ingroup IxAtmdAccCtrlAPI
- *
- * @fn ixAtmdAccPortTxProcess (IxAtmLogicalPort port,
-    IxAtmScheduleTable* scheduleTablePtr)
- *
- * @brief Transmit queue cells to the H/W based on the supplied schedule
- *        table.
- *
- * This function @a ixAtmdAccPortTxProcess() process the schedule
- * table provided as a parameter to the function. As a result cells are
- * sent to the underlaying hardware for transmission.
- *
- * The schedule table is executed in its entirety or not at all. So the
- * onus is on the caller not to submit a table containing more cells than
- * can be transmitted at that point. The maximum numbers that can be
- * transmitted is guaranteed to be the number of cells as returned by the
- * function @a ixAtmdAccPortTxFreeEntriesQuery().
- *
- * When the scheduler is invoked on a threshold level, IxAtmdAcc gives the
- * minimum number of cells (to ensure the callback will fire again later)
- * and the maximum number of cells that @a ixAtmdAccPortTxProcess()
- * will be able to process (assuming the ATM scheduler is able
- * to produce the worst-case schedule table, i.e. one entry per cell).
- *
- * When invoked ouside a threshold level, the overall number of cells of
- * the schedule table should be less than the number of cells returned
- * by the @a ixAtmdAccPortTxFreeEntriesQuery() function.
- *
- * After invoking the @a ixAtmdAccPortTxProcess() function, it is the
- * user choice to query again the queue level with the function
- * @a ixAtmdAccPortTxFreeEntriesQuery() and, depending on a new cell
- * number, submit an other schedule table.
- *
- * IxAtmdAcc will check that the number of cells in the schedule table
- * is compatible with the current transmit level. If the
- *
- * Obsolete or invalid connection Id will be silently discarded.
- *
- * This function is not reentrant for the same port.
- *
- * This functions doesn't use system resources and can be used inside an
- * interrupt context.
- *
- * This function is used as a response to the hardware requesting more
- * cells to transmit.
- *
- * @sa ixAtmdAccPortTxScheduledModeEnable
- * @sa ixAtmdAccPortTxFreeEntriesQuery
- * @sa ixAtmdAccPortTxCallbackRegister
- * @sa ixAtmdAccPortEnable
- *
- * @param port @ref IxAtmLogicalPort [in] - logical PHY port [@a IX_UTOPIA_PORT_0 .. @a IX_UTOPIA_MAX_PORTS - 1]
- * @param scheduleTablePtr @ref IxAtmScheduleTable* [in] - pointer to a scheduler update table. The
- *     content of this table is not modified by this function. This
- *     parameter cannot be a null pointer.
- *
- * @return @li IX_SUCCESS the schedule table process is complete
- *             and cells are transmitted to the hardware
- * @return @li IX_ATMDACC_WARNING : Traffic will be dropped: the schedule table exceed
- *     the hardware capacity  If this error is ignored, further traffic
- *     and schedule will work correctly.
- *     Overscheduling does not occur when the schedule table does
- *     not contain more entries that the number of free entries returned
- *     by @a ixAtmdAccPortTxFreeEntriesQuery().
- *     However, Disconnect attempts just after this error will fail permanently
- *     with the error code @a IX_ATMDACC_RESOURCES_STILL_ALLOCATED, and it is
- *     necessary to disable the port to make @a ixAtmdAccTxVcTryDisconnect()
- *     successful.
- * @return @li IX_FAIL a wrong parameter is supplied, or the format of
- *     the schedule table is invalid, or the port is not Enabled, or
- *     an internal severe error occured. No cells is transmitted to the hardware
- *
- * @note - If the failure is linked to an overschedule of data cells
- *     the result is an inconsistency in the output traffic (one or many
- *     cells may be missing and the traffic contract is not respected).
- *
- */
-PUBLIC IX_STATUS ixAtmdAccPortTxProcess (IxAtmLogicalPort port,
-    IxAtmScheduleTable* scheduleTablePtr);
-
-/**
- *
- * @ingroup IxAtmdAccCtrlAPI
- *
- * @fn ixAtmdAccTxDoneDispatch (unsigned int numberOfPdusToProcess,
-                unsigned int *numberOfPdusProcessedPtr)
- *
- * @brief Process a number of pending transmit done pdus from the hardware.
- *
- * As a by-product of Atm transmit operation buffers which transmission
- * is complete need to be recycled to users. This function is invoked
- * to service the oustanding list of transmitted buffers and pass them
- * to VC users.
- *
- * Users are handed back pdus by invoking the free callback registered
- * during the @a ixAtmdAccTxVcConnect() call.
- *
- * There is a single Tx done stream servicing all active Atm Tx ports
- * which can contain a maximum of 64 entries. If this stream fills port
- * transmission will stop so this function must be call sufficently
- * frequently to ensure no disruption to the transmit operation.
- *
- * This function can be used from a timer context, or can be associated
- * with a TxDone level threshold event (see @a ixAtmdAccTxDoneDispatcherRegister() ),
- * or can be used inside an active polling mechanism under user control.
- *
- * For ease of use the signature of this function is compatible with the
- * TxDone threshold event callback prototype.
- *
- * This functions can be used inside an interrupt context.
- *
- * @sa ixAtmdAccTxDoneDispatcherRegister
- * @sa IxAtmdAccTxVcBufferReturnCallback
- * @sa ixAtmdAccTxDoneLevelQuery
- *
- * @param numberOfPdusToProcess unsigned int [in] - maxiumum number of pdus to remove
- *     from the TX Done queue
- * @param *numberOfPdusProcessedPtr unsigned int [out] - number of pdus removed from
- *     the TX Done queue. This parameter cannot be a null pointer.
- *
- * @return @li IX_SUCCESS the number of pdus as indicated in
- *     numberOfPdusToProcess are removed from the TX Done hardware
- *     and passed to the user through the Tx Done callback registered
- *     during a call to @a ixAtmdAccTxVcConnect()
- * @return @li IX_FAIL invalid parameters or numberOfPdusProcessedPtr is
- *     a null pointer or some unspecified internal error occured.
- *
- */
-PUBLIC IX_STATUS
-ixAtmdAccTxDoneDispatch (unsigned int numberOfPdusToProcess,
-                unsigned int *numberOfPdusProcessedPtr);
-
-/**
- *
- * @ingroup IxAtmdAccCtrlAPI
- * 
- * @fn ixAtmdAccTxDoneLevelQuery (unsigned int *numberOfPdusPtr)
- *
- * @brief Query the current number of transmit pdus ready for
- *        recycling.
- *
- * This function is used to get the number of transmitted pdus which
- * the hardware is ready to hand back to user.
- *
- * This function can be used from a timer context, or can be associated
- * with a threshold event, on can be used inside an active polling
- * mechanism
- *
- * @sa ixAtmdAccTxDoneDispatch
- *
- * @param *numberOfPdusPtr unsigned int [out] - Pointer to the number of pdus transmitted
- *        at the time of this function call, and ready for recycling
- *        This parameter cannot be a null pointer.
- *
- * @return @li IX_SUCCESS numberOfPdusPtr contains the number of pdus
- *        ready for recycling at the time of this function call
- *
- * @return @li IX_FAIL wrong parameter (null pointer as parameter).or
- *         unspecified rocessing error occurs..The value in numberOfPdusPtr
- *         is unspecified.
- *
- */
-PUBLIC IX_STATUS
-ixAtmdAccTxDoneLevelQuery (unsigned int *numberOfPdusPtr);
-
-/**
- *
- * @ingroup IxAtmdAccCtrlAPI
- *
- * @fn ixAtmdAccTxDoneQueueSizeQuery (unsigned int *numberOfPdusPtr)
- *
- * @brief Query the TxDone queue size.
- *
- * This function is used to get the number of pdus which
- * the hardware is able to store after transmission is complete
- *
- * The returned value can be used to set a threshold and enable
- * a callback to be notified when the number of pdus is going over
- * the threshold.
- *
- * @sa ixAtmdAccTxDoneDispatcherRegister
- *
- * @param *numberOfPdusPtr unsigned int [out] - Pointer to the number of pdus the system
- *        is able to queue after transmission
- *
- * @return @li IX_SUCCESS numberOfPdusPtr contains the the number of
- *        pdus the system is able to queue after transmission
- * @return @li IX_FAIL wrong parameter (null pointer as parameter).or
- *         unspecified rocessing error occurs..The value in numberOfPdusPtr
- *         is unspecified.
- *
- * @note - This function is reentrant, doesn't use system resources
- *         and can be used from an interrupt context.
- */
-PUBLIC IX_STATUS
-ixAtmdAccTxDoneQueueSizeQuery (unsigned int *numberOfPdusPtr);
-
-/**
- *
- * @ingroup IxAtmdAccCtrlAPI
- * 
- * @fn ixAtmdAccTxDoneDispatcherRegister (unsigned int numberOfPdus,
-   IxAtmdAccTxDoneDispatcher notificationCallback)
- *
- * @brief Configure the Tx Done stream threshold value and register a
- * callback to handle threshold notifications.
- *
- * This function sets the threshold level in term of number of pdus at
- * which the supplied notification function should be called.
- *
- * The higher the threshold value is, the less events will be necessary
- * to process transmitted buffers.
- *
- * Transmitted buffers recycling implementation is a sytem-wide mechanism
- * and needs to be set prior any traffic is started. If this threshold
- * mechanism is not used, the user is responsible for polling the
- * transmitted buffers thanks to @a ixAtmdAccTxDoneDispatch() and
- * @a ixAtmdAccTxDoneLevelQuery() functions.
- *
- * This function should be called during system initialisation outside
- * an interrupt context
- *
- * @sa ixAtmdAccTxDoneDispatcherRegister
- * @sa ixAtmdAccTxDoneDispatch
- * @sa ixAtmdAccTxDoneLevelQuery
- *
- * @param numberOfPdus unsigned int [in] - The number of TxDone pdus which triggers the
- *        callback invocation This number has to be a power of 2, one of the
- *        values 0,1,2,4,8,16,32 ...
- *        The maximum value cannot be more than half of the txDone queue
- *        size (which can be retrieved using @a ixAtmdAccTxDoneQueueSizeQuery())
- * @param notificationCallback @ref IxAtmdAccTxDoneDispatcher [in] - The function to invoke. (This
- *        parameter can be @a ixAtmdAccTxDoneDispatch()).This
- *        parameter ust not be a null pointer.
- *
- * @return @li IX_SUCCESS Successful call to ixAtmdAccTxDoneDispatcherRegister
- * @return @li IX_FAIL error in the parameters:
- *
- * @note - The notificationCallback will be called exactly when the threshold level
- *         will increase from (numberOfPdus) to (numberOfPdus+1)
- *
- * @note - If there is no Tx traffic, there is no guarantee that TxDone Pdus will
- *       be released to the user (when txDone level is permanently under the threshold
- *       level. One of the preffered way to return resources to the user is to use
- *       a mix of txDone notifications, used together with a slow
- *       rate timer and an exclusion mechanism protecting from re-entrancy
- *
- * @note - The TxDone threshold will only hand back buffers when the threshold level is
- *      crossed. Setting this threshold to a great number reduce the interrupt rate
- *      and the cpu load, but also increase the number of outstanding mbufs and has
- *      a system wide impact when these mbufs are needed by other components.
- *
- */
-PUBLIC IX_STATUS ixAtmdAccTxDoneDispatcherRegister (unsigned int numberOfPdus,
-   IxAtmdAccTxDoneDispatcher notificationCallback);
-
-/* ------------------------------------------------------
-   Part of the IxAtmdAcc interface related to Utopia config
-   ------------------------------------------------------ */
-
-/**
- *
- * @ingroup IxAtmdAccCtrlAPI
- *
- * @defgroup IxAtmdAccUtopiaCtrlAPI IXP400 ATM Driver Access (IxAtmdAcc) Utopia Control API
- *
- * @brief The public API for the IXP400 Atm Driver Control component
- *
- * IxAtmdAcc is the low level interface by which AAL PDU get
- * transmitted to,and received from the Utopia bus
- *
- * This part is related to the UTOPIA configuration.
- *
- * @{
- */
-
-/**
- *
- * @brief Utopia configuration
- *
- * This structure is used to set the Utopia parameters
- * @li contains the values of Utopia registers, to be set during initialisation
- * @li contains debug commands for NPE, to be used during development steps
- *
- * @note - the exact description of all parameters is done in the Utopia reference
- *   documents.
- *
- */
-typedef struct
-{
-    /**
-    * @ingroup IxAtmdAccUtopiaCtrlAPI
-    * @struct UtTxConfig_
-    * @brief Utopia Tx Config Register
-    */
-    struct UtTxConfig_
-    {
-
-    unsigned int reserved_1:1;  /**< [31] These bits are always 0.*/
-    unsigned int txInterface:1;     /**< [30] Utopia Transmit Interface. The following encoding
-                                   * is used to set the Utopia Transmit interface as ATM master
-                                   * or PHY slave:
-                                   * @li 1 - PHY
-                                   * @li 0 - ATM
-                                   */
-    unsigned int txMode:1;      /**< [29] Utopia Transmit Mode. The following encoding is used
-    *  to set the Utopia Transmit mode to SPHY or MPHY:
-    *  @li 1 - SPHY
-    *  @li 0 - MPHY
-    */
-    unsigned int txOctet:1;  /**< [28] Utopia Transmit cell transfer protocol. Used to set
-    * the Utopia cell transfer protocol to Octet-level handshaking.
-    * Note this is only applicable in SPHY mode.
-    * @li 1 - Octet-handshaking enabled
-    * @li 0 - Cell-handshaking enabled
-    */
-    unsigned int txParity:1;    /**< [27] Utopia Transmit parity enabled when set. TxEvenParity
-    * defines the parity format odd/even.
-    * @li 1 - Enable Parity generation.
-    * @li 0 - ut_op_prty held low.
-    */
-    unsigned int txEvenParity:1; /**< [26] Utopia Transmit Parity Mode
-    * @li 1 - Even Parity Generated.
-    * @li 0 - Odd Parity Generated.
-    */
-    unsigned int txHEC:1; /**< [25] Header Error Check Insertion Mode. Specifies if the transmit
-    * cell header check byte is calculated and inserted when set.
-    * @li 1 - Generate HEC.
-    * @li 0 - Disable HEC generation.
-    */
-    unsigned int txCOSET:1;    /**< [24] If enabled the HEC is Exclusive-OR'ed with the value 0x55 before
-  * being presented on the Utopia bus.
-  * @li 1 - Enable HEC ExOR with value 0x55
-  * @li 0 - Use generated HEC value.
-  */
-
-    unsigned int reserved_2:1;    /**< [23] These bits are always 0
-    */
-    unsigned int txCellSize:7;    /**< [22:16] Transmit expected cell size. Configures the cell size
-    * for the transmit module: Values between 52-64 are valid.
-    */
-    unsigned int reserved_3:3;  /**< [15:13] These bits are always 0 */
-    unsigned int txAddrRange:5;       /**< [12:8] When configured as an ATM master in MPHY mode this
-    * register specifies the upper limit of the PHY polling logical
-    * range. The number of active PHYs are TxAddrRange + 1.
-    */
-    unsigned int reserved_4:3;      /**< [7:5] These bits are always 0 */
-    unsigned int txPHYAddr:5;     /**< [4:0] When configured as a slave in an MPHY system this register
-    * specifies the physical address of the PHY.
-    */
-    }
-
-    utTxConfig;       /**< Tx config Utopia register */
-
-   /**
-    * @ingroup IxAtmdAccUtopiaCtrlAPI
-   * @struct UtTxStatsConfig_
-   * @brief Utopia Tx stats Register
-    */
-    struct UtTxStatsConfig_
-    {
-
-    unsigned int vpi:12;  /**< [31:20] ATM VPI [11:0] OR GFC [3:0] and VPI [7:0]
-    @li Note: if VCStatsTxGFC is set to 0 the GFC field is ignored in test. */
-
-    unsigned int vci:16;  /**< [19:4] ATM VCI [15:0] or PHY Address[4] */
-
-    unsigned int pti:3;  /**< [3:1] ATM PTI [2:0] or PHY Address[3:1]
-  @li Note: if VCStatsTxPTI is set to 0 the PTI field is ignored in test.
-  @li Note: if VCStatsTxEnb is set to 0 only the transmit PHY port
-  address as defined by this register is used for ATM statistics [4:0]. */
-
-    unsigned int clp:1;  /**< [0] ATM CLP or PHY Address [0]
-  @li Note: if VCStatsTxCLP is set to 0 the CLP field is ignored in test.
-  @li Note: if VCStatsTxEnb is set to 0 only the transmit PHY port
-  address as defined by this register is used for ATM statistics [4:0]. */
-    }
-
-    utTxStatsConfig;       /**< Tx stats config Utopia register */
-
-       /**
-    * @ingroup IxAtmdAccUtopiaCtrlAPI
-       * @struct UtTxDefineIdle_
-       * @brief Utopia Tx idle cells Register
-    */
-    struct UtTxDefineIdle_
-    {
-
-    unsigned int vpi:12;  /**< [31:20] ATM VPI [11:0] OR GFC [3:0] and VPI [7:0]
-    @li Note: if VCIdleTxGFC is set to 0 the GFC field is ignored in test. */
-
-    unsigned int vci:16;  /**< [19:4] ATM VCI [15:0] */
-
-    unsigned int pti:3;  /**< [3:1] ATM PTI PTI [2:0]
-  @li Note: if VCIdleTxPTI is set to 0 the PTI field is ignored in test.*/
-
-    unsigned int clp:1;  /**< [0] ATM CLP [0]
-  @li Note: if VCIdleTxCLP is set to 0 the CLP field is ignored in test.*/
-    }
-
-    utTxDefineIdle;      /**< Tx idle cell config Utopia register */
-
-      /**
-    * @ingroup IxAtmdAccUtopiaCtrlAPI
-      * @struct UtTxEnableFields_
-      * @brief Utopia Tx ienable fields Register
-    */
-    struct UtTxEnableFields_
-    {
-
-    unsigned int defineTxIdleGFC:1;    /**< [31] This register is used to include or exclude the GFC
-    field of the ATM header when testing for Idle cells.
-    @li 1 - GFC field is valid.
-    @li 0 - GFC field ignored.*/
-
-    unsigned int defineTxIdlePTI:1;    /**< [30] This register is used to include or exclude the PTI
-    field of the ATM header when testing for Idle cells.
-    @li 1 - PTI field is valid
-    @li    0 - PTI field ignored.*/
-
-    unsigned int defineTxIdleCLP:1;    /**< [29] This register is used to include or
-    exclude the CLP field of the ATM header when testing for Idle cells.
-    @li 1 - CLP field is valid.
-    @li 0 - CLP field ignored. */
-
-    unsigned int phyStatsTxEnb:1;    /**< [28] This register is used to enable or disable ATM
-  statistics gathering based on the specified PHY address as defined
-  in TxStatsConfig register.
-  @li 1 - Enable statistics for specified transmit PHY address.
-    @li 0 - Disable statistics for specified transmit PHY address. */
-
-    unsigned int vcStatsTxEnb:1;  /**< [27] This register is used to change the ATM
-      statistics-gathering mode from the specified logical PHY address
-      to a specific VPI/VCI address.
-      @li 1 - Enable statistics for specified VPI/VCI address.
-      @li 0 - Disable statistics for specified VPI/VCI address */
-
-    unsigned int vcStatsTxGFC:1;  /**< [26] This register is used to include or exclude the GFC
-      field of the ATM header when ATM VPI/VCI statistics are enabled.
-      GFC is only available at the UNI and uses the first 4-bits of
-      the VPI field.
-      @li 1 - GFC field is valid
-      @li 0 - GFC field ignored.*/
-
-    unsigned int vcStatsTxPTI:1;  /**< [25] This register is used to include or exclude the PTI
-      field of the ATM header when ATM VPI/VCI statistics are enabled.
-      @li 1 - PTI field is valid
-      @li 0 - PTI field ignored.*/
-
-    unsigned int vcStatsTxCLP:1;  /**< [24] This register is used to include or exclude the CLP
-      field of the ATM header when ATM VPI/VCI statistics are enabled.
-      @li 1 - CLP field is valid
-      @li 0 - CLP field ignored. */
-
-    unsigned int reserved_1:3;  /**< [23-21] These bits are always 0 */
-
-    unsigned int txPollStsInt:1;    /**< [20] Enable the assertion of the ucp_tx_poll_sts condition
-  where there is a change in polling status.
-  @li 1 - ucp_tx_poll_sts asserted whenever there is a change in status
-  @li    0 - ucp_tx_poll_sts asserted if ANY transmit PHY is available
-  */
-    unsigned int txCellOvrInt:1;    /**< [19] Enable TxCellCount overflow CBI Transmit Status condition
-      assertion.
-      @li 1 - If TxCellCountOvr is set assert the Transmit Status Condition.
-      @li 0 - No CBI Transmit Status condition assertion */
-
-    unsigned int txIdleCellOvrInt:1;  /**< [18] Enable TxIdleCellCount overflow Transmit Status Condition
-    @li 1 - If TxIdleCellCountOvr is set assert the Transmit Status Condition
-      @li 0 - No CBI Transmit Status condition assertion..*/
-
-    unsigned int enbIdleCellCnt:1;    /**< [17] Enable Transmit Idle Cell Count.
-    @li 1 - Enable count of Idle cells transmitted.
-      @li 0 - No count is maintained. */
-
-    unsigned int enbTxCellCnt:1;    /**< [16] Enable Transmit Valid Cell Count of non-idle/non-error cells
-      @li 1 - Enable count of valid cells transmitted- non-idle/non-error
-      @li 0 - No count is maintained.*/
-
-    unsigned int reserved_2:16;   /**< [15:0] These bits are always 0 */
-    } utTxEnableFields;  /**< Tx enable Utopia register */
-
-    /**
-    * @ingroup IxAtmdAccUtopiaCtrlAPI
-    * @struct UtTxTransTable0_
-    * @brief Utopia Tx translation table Register
-    */
-    struct UtTxTransTable0_
-    {
-
-    unsigned int phy0:5;  /**< [31-27] Tx Mapping value of logical phy 0 */
-
-    unsigned int phy1:5;  /**< [26-22] Tx Mapping value of logical phy 1 */
-
-    unsigned int phy2:5;  /**< [21-17] Tx Mapping value of logical phy 2 */
-
-    unsigned int reserved_1:1;  /**< [16] These bits are always 0.*/
-
-    unsigned int phy3:5;  /**< [15-11] Tx Mapping value of logical phy 3 */
-
-    unsigned int phy4:5;  /**< [10-6] Tx Mapping value of logical phy 4 */
-
-    unsigned int phy5:5;  /**< [5-1] Tx Mapping value of logical phy 5 */
-
-    unsigned int reserved_2:1;  /**< [0] These bits are always 0 */
-    } utTxTransTable0;  /**< Tx translation table */
-
-  /**
-    * @ingroup IxAtmdAccUtopiaCtrlAPI
-  * @struct UtTxTransTable1_
-  * @brief Utopia Tx translation table Register
-    */
-    struct UtTxTransTable1_
-    {
-
-    unsigned int phy6:5;  /**< [31-27] Tx Mapping value of logical phy 6 */
-
-    unsigned int phy7:5;  /**< [26-22] Tx Mapping value of logical phy 7 */
-
-    unsigned int phy8:5;  /**< [21-17] Tx Mapping value of logical phy 8 */
-
-    unsigned int reserved_1:1; /**< [16-0] These bits are always 0 */
-
-    unsigned int phy9:5;  /**< [15-11] Tx Mapping value of logical phy 3 */
-
-    unsigned int phy10:5;   /**< [10-6] Tx Mapping value of logical phy 4 */
-
-    unsigned int phy11:5;   /**< [5-1] Tx Mapping value of logical phy 5 */
-
-    unsigned int reserved_2:1;  /**< [0] These bits are always 0 */
-    } utTxTransTable1;  /**< Tx translation table */
-
-    /**
-    * @ingroup IxAtmdAccUtopiaCtrlAPI
-    * @struct UtTxTransTable2_
-    * @brief Utopia Tx translation table Register
-    */
-    struct UtTxTransTable2_
-    {
-
-    unsigned int phy12:5;   /**< [31-27] Tx Mapping value of logical phy 6 */
-
-    unsigned int phy13:5;   /**< [26-22] Tx Mapping value of logical phy 7 */
-
-    unsigned int phy14:5;   /**< [21-17] Tx Mapping value of logical phy 8 */
-
-    unsigned int reserved_1:1; /**< [16-0] These bits are always 0 */
-
-    unsigned int phy15:5;   /**< [15-11] Tx Mapping value of logical phy 3 */
-
-    unsigned int phy16:5;   /**< [10-6] Tx Mapping value of logical phy 4 */
-
-    unsigned int phy17:5;   /**< [5-1] Tx Mapping value of logical phy 5 */
-
-    unsigned int reserved_2:1;  /**< [0] These bits are always 0 */
-    } utTxTransTable2;    /**< Tx translation table */
-
-    /**
-    * @ingroup IxAtmdAccUtopiaCtrlAPI
-    * @struct UtTxTransTable3_
-    * @brief Utopia Tx translation table Register
-    */
-    struct UtTxTransTable3_
-    {
-
-    unsigned int phy18:5;   /**< [31-27] Tx Mapping value of logical phy 6 */
-
-    unsigned int phy19:5;   /**< [26-22] Tx Mapping value of logical phy 7 */
-
-    unsigned int phy20:5;   /**< [21-17] Tx Mapping value of logical phy 8 */
-
-    unsigned int reserved_1:1; /**< [16-0] These bits are always 0 */
-
-    unsigned int phy21:5;   /**< [15-11] Tx Mapping value of logical phy 3 */
-
-    unsigned int phy22:5;   /**< [10-6] Tx Mapping value of logical phy 4 */
-
-    unsigned int phy23:5;   /**< [5-1] Tx Mapping value of logical phy 5 */
-
-    unsigned int reserved_2:1;  /**< [0] These bits are always 0 */
-    } utTxTransTable3;  /**< Tx translation table */
-
-    /**
-    * @ingroup IxAtmdAccUtopiaCtrlAPI
-    * @struct UtTxTransTable4_
-    * @brief Utopia Tx translation table Register
-    */
-    struct UtTxTransTable4_
-    {
-
-    unsigned int phy24:5;   /**< [31-27] Tx Mapping value of logical phy 6 */
-
-    unsigned int phy25:5;   /**< [26-22] Tx Mapping value of logical phy 7 */
-
-    unsigned int phy26:5;   /**< [21-17] Tx Mapping value of logical phy 8 */
-
-    unsigned int reserved_1:1; /**< [16-0] These bits are always 0 */
-
-    unsigned int phy27:5;   /**< [15-11] Tx Mapping value of logical phy 3 */
-
-    unsigned int phy28:5;   /**< [10-6] Tx Mapping value of logical phy 4 */
-
-    unsigned int phy29:5;   /**< [5-1] Tx Mapping value of logical phy 5 */
-
-    unsigned int reserved_2:1;  /**< [0] These bits are always 0 */
-    } utTxTransTable4;  /**< Tx translation table */
-
-    /**
-    * @ingroup IxAtmdAccUtopiaCtrlAPI
-    * @struct UtTxTransTable5_
-    * @brief Utopia Tx translation table Register
-    */
-    struct UtTxTransTable5_
-    {
-
-    unsigned int phy30:5;   /**< [31-27] Tx Mapping value of logical phy 6 */
-
-    unsigned int reserved_1:27;     /**< [26-0] These bits are always 0 */
-
-    } utTxTransTable5;  /**< Tx translation table */
-
-    /**
-    * @ingroup IxAtmdAccUtopiaCtrlAPI
-    * @struct UtRxConfig_
-    * @brief Utopia Rx config Register
-    */
-    struct UtRxConfig_
-    {
-
-    unsigned int rxInterface:1;    /**< [31] Utopia Receive Interface. The following encoding is used
- to set the Utopia Receive interface as ATM master or PHY slave:
- @li 1 - PHY
-    @li 0 - ATM */
-
-    unsigned int rxMode:1;      /**< [30] Utopia Receive Mode. The following encoding is used to set
-      the Utopia Receive mode to SPHY or MPHY:
-      @li 1 - SPHY
-    @li 0 - MPHY */
-
-    unsigned int rxOctet:1;  /**< [29] Utopia Receive cell transfer protocol. Used to set the Utopia
-  cell transfer protocol to Octet-level handshaking. Note this is only
-  applicable in SPHY mode.
-  @li 1 - Octet-handshaking enabled
-    @li 0 - Cell-handshaking enabled */
-
-    unsigned int rxParity:1;    /**< [28] Utopia Receive Parity Checking enable.
-    @li 1 - Parity checking enabled
-    @li 0 - Parity checking disabled */
-
-    unsigned int rxEvenParity:1;/**< [27] Utopia Receive Parity Mode
-    @li 1 - Check for Even Parity
-    @li 0 - Check for Odd Parity.*/
-
-    unsigned int rxHEC:1;    /**< [26] RxHEC    Header Error Check Mode. Enables/disables cell header
-    error checking on the received cell header.
-    @li 1 - HEC checking enabled
-    @li 0 - HEC checking disabled */
-
-    unsigned int rxCOSET:1;  /**< [25] If enabled the HEC is Exclusive-OR'ed with the value 0x55
-  before being tested with the received HEC.
-  @li 1 - Enable HEC ExOR with value 0x55.
-    @li 0 - Use generated HEC value.*/
-
-    unsigned int rxHECpass:1;    /**< [24] Specifies if the incoming cell HEC byte should be transferred
-     after optional processing to the NPE2 Coprocessor Bus Interface or
-     if it should be discarded.
-     @li 1 - HEC maintained 53-byte/UDC cell sent to NPE2.
-    @li 0 - HEC discarded 52-byte/UDC cell sent to NPE2 coprocessor.*/
-
-    unsigned int reserved_1:1;    /**< [23] These bits are always 0 */
-
-    unsigned int rxCellSize:7;    /**< [22:16] Receive cell size. Configures the receive cell size.
-      Values between 52-64 are valid */
-
-    unsigned int rxHashEnbGFC:1;      /**< [15] Specifies if the VPI field [11:8]/GFC field should be
-      included in the Hash data input or if the bits should be padded
-      with 1'b0.
-      @li 1 - VPI [11:8]/GFC field valid and used in Hash residue calculation.
-      @li 0 - VPI [11:8]/GFC field padded with 1'b0 */
-
-    unsigned int rxPreHash:1; /**< [14] Enable Pre-hash value generation. Specifies if the
- incoming cell data should be pre-hashed to allow VPI/VCI header look-up
- in a hash table.
- @li 1 - Pre-hashing enabled
-      @li 0 - Pre-hashing disabled */
-
-    unsigned int reserved_2:1;    /**< [13] These bits are always 0 */
-
-    unsigned int rxAddrRange:5;     /**< [12:8] In ATM master, MPHY mode,
-     * this register specifies the upper
-     * limit of the PHY polling logical range. The number of active PHYs are
-     * RxAddrRange + 1.
-     */
-    unsigned int reserved_3:3;    /**< [7-5] These bits are always 0 .*/
-    unsigned int rxPHYAddr:5;     /**< [4:0] When configured as a slave in an MPHY system this register
-      * specifies the physical address of the PHY.
-      */
-    } utRxConfig;  /**< Rx config Utopia register */
-
-      /**
-    * @ingroup IxAtmdAccUtopiaCtrlAPI
-      * @struct UtRxStatsConfig_
-      * @brief Utopia Rx stats config Register
-    */
-    struct UtRxStatsConfig_
-    {
-
-    unsigned int vpi:12;  /**< [31:20] ATM VPI    VPI [11:0] OR GFC [3:0] and VPI [7:0]
-    @li Note: if VCStatsRxGFC is set to 0 the GFC field is ignored in test. */
-
-    unsigned int vci:16;  /**< [19:4] VCI [15:0] or PHY Address [4] */
-
-    unsigned int pti:3;  /**< [3:1] PTI [2:0] or or PHY Address [3:1]
-  @li Note: if VCStatsRxPTI is set to 0 the PTI field is ignored in test.
-  @li Note: if VCStatsRxEnb is set to 0 only the PHY port address is used
-  for statistics gathering.. */
-
-    unsigned int clp:1;  /**< [0] CLP [0] or PHY Address [0]
-  @li Note: if VCStatsRxCLP is set to 0 the CLP field is ignored in test.
-  @li Note: if VCStatsRxEnb is set to 0 only the PHY port address is used
-  for statistics gathering.. */
-    } utRxStatsConfig;  /**< Rx stats config Utopia register */
-
-  /**
-    * @ingroup IxAtmdAccUtopiaCtrlAPI
-  * @struct UtRxDefineIdle_
-  * @brief Utopia Rx idle cells config Register
-    */
-    struct UtRxDefineIdle_
-    {
-
-    unsigned int vpi:12;  /**< [31:20] ATM VPI [11:0] OR GFC [3:0] and VPI [7:0]
-    @li Note: if VCIdleRxGFC is set to 0 the GFC field is ignored in test. */
-
-    unsigned int vci:16;  /**< [19:4] ATM VCI [15:0] */
-
-    unsigned int pti:3;  /**< [3:1] ATM PTI PTI [2:0]
-  @li Note: if VCIdleRxPTI is set to 0 the PTI field is ignored in test.*/
-
-    unsigned int clp:1;  /**< [0] ATM CLP [0]
-  @li Note: if VCIdleRxCLP is set to 0 the CLP field is ignored in test.*/
-    } utRxDefineIdle;      /**< Rx idle cell config Utopia register */
-
-      /**
-    * @ingroup IxAtmdAccUtopiaCtrlAPI
-      * @struct UtRxEnableFields_
-      * @brief Utopia Rx enable Register
-    */
-    struct UtRxEnableFields_
-    {
-
-    unsigned int defineRxIdleGFC:1;/**< [31] This register is used to include or exclude the GFC
- field of the ATM header when testing for Idle cells.
- @li 1 - GFC field is valid.
-    @li 0 - GFC field ignored.*/
-
-    unsigned int defineRxIdlePTI:1;/**< [30] This register is used to include or exclude the PTI
- field of the ATM header when testing for Idle cells.
- @li 1 - PTI field is valid.
-    @li 0 - PTI field ignored.*/
-
-    unsigned int defineRxIdleCLP:1;/**< [29] This register is used to include or exclude the CLP
- field of the ATM header when testing for Idle cells.
- @li 1 - CLP field is valid.
-    @li    0 - CLP field ignored.*/
-
-    unsigned int phyStatsRxEnb:1;/**< [28] This register is used to enable or disable ATM statistics
-     gathering based on the specified PHY address as defined in RxStatsConfig
-     register.
-     @li 1 - Enable statistics for specified receive PHY address.
-    @li 0 - Disable statistics for specified receive PHY address.*/
-
-    unsigned int vcStatsRxEnb:1;/**< [27] This register is used to enable or disable ATM statistics
-    gathering based on a specific VPI/VCI address.
-    @li 1 - Enable statistics for specified VPI/VCI address.
-    @li 0 - Disable statistics for specified VPI/VCI address.*/
-
-    unsigned int vcStatsRxGFC:1;/**< [26] This register is used to include or exclude the GFC field
-    of the ATM header when ATM VPI/VCI statistics are enabled. GFC is only
-    available at the UNI and uses the first 4-bits of the VPI field.
-    @li 1 - GFC field is valid.
-    @li 0 - GFC field ignored. */
-
-    unsigned int vcStatsRxPTI:1;/**< [25] This register is used to include or exclude the PTI field
-    of the ATM header when ATM VPI/VCI statistics are enabled.
-    @li 1 - PTI field is valid.
-    @li 0 - PTI field ignored.*/
-
-    unsigned int vcStatsRxCLP:1;/**< [24] This register is used to include or exclude the CLP field
-    of the ATM header when ATM VPI/VCI statistics are enabled.
-    @li 1 - CLP field is valid.
-    @li 0 - CLP field ignored. */
-
-    unsigned int discardHecErr:1;/**< [23] Discard cells with an invalid HEC.
-     @li 1 - Discard cells with HEC errors
-    @li 0 - Cells with HEC errors are passed */
-
-    unsigned int discardParErr:1;/**< [22] Discard cells containing parity errors.
-     @li 1 - Discard cells with parity errors
-    @li 0 - Cells with parity errors are passed */
-
-    unsigned int discardIdle:1;    /**< [21] Discard Idle Cells based on DefineIdle register values
- @li    1 - Discard IDLE cells
-    @li 0 - IDLE cells passed */
-
-    unsigned int enbHecErrCnt:1;/**< [20] Enable Receive HEC Error Count.
-    @li 1 - Enable count of received cells containing HEC errors
-    @li 0 - No count is maintained. */
-
-    unsigned int enbParErrCnt:1;/**< [19] Enable Parity Error Count
-    @li    1 - Enable count of received cells containing Parity errors
-    @li 0 - No count is maintained. */
-
-    unsigned int enbIdleCellCnt:1;/**< [18] Enable Receive Idle Cell Count.
-      @li 1 - Enable count of Idle cells received.
-    @li 0 - No count is maintained.*/
-
-    unsigned int enbSizeErrCnt:1;/**< [17] Enable Receive Size Error Count.
-     @li 1 - Enable count of received cells of incorrect size
-    @li    0 - No count is maintained. */
-
-    unsigned int enbRxCellCnt:1;/**< [16] Enable Receive Valid Cell Count of non-idle/non-error cells.
-    @li    1 - Enable count of valid cells received - non-idle/non-error
-    @li 0 - No count is maintained. */
-
-    unsigned int reserved_1:3;    /**< [15:13] These bits are always 0 */
-
-    unsigned int rxCellOvrInt:1;      /**< [12] Enable CBI Utopia Receive Status Condition if the RxCellCount
-      register overflows.
-      @li 1 - CBI Receive Status asserted.
-      @li    0 - No CBI Receive Status asserted.*/
-
-    unsigned int invalidHecOvrInt:1;  /**< [11] Enable CBI Receive Status Condition if the InvalidHecCount
-    register overflows.
-    @li    1 - CBI Receive Condition asserted.
-      @li 0 - No CBI Receive Condition asserted */
-
-    unsigned int invalidParOvrInt:1;  /**< [10] Enable CBI Receive Status Condition if the InvalidParCount
-    register overflows
-    @li    1 - CBI Receive Condition asserted.
-      @li 0 - No CBI Receive Condition asserted */
-
-    unsigned int invalidSizeOvrInt:1;   /**< [9] Enable CBI Receive Status Condition if the InvalidSizeCount
-     register overflows.
-     @li 1 - CBI Receive Status Condition asserted.
-     @li 0 - No CBI Receive Status asserted */
-
-    unsigned int rxIdleOvrInt:1;      /**< [8] Enable CBI Receive Status Condition if the RxIdleCount overflows.
-      @li 1 - CBI Receive Condition asserted.
-      @li 0 - No CBI Receive Condition asserted */
-
-    unsigned int reserved_2:3;    /**< [7:5] These bits are always 0 */
-
-    unsigned int rxAddrMask:5;    /**< [4:0] This register is used as a mask to allow the user to increase
-    the PHY receive address range. The register should be programmed with
-    the address-range limit, i.e. if set to 0x3 the address range increases
-  to a maximum of 4 addresses. */
-    } utRxEnableFields;      /**< Rx enable Utopia register */
-
-      /**
-    * @ingroup IxAtmdAccUtopiaCtrlAPI
-      * @struct UtRxTransTable0_
-      * @brief Utopia Rx translation table Register
-    */
-    struct UtRxTransTable0_
-    {
-
-    unsigned int phy0:5;  /**< [31-27] Rx Mapping value of logical phy 0 */
-
-    unsigned int phy1:5;  /**< [26-22] Rx Mapping value of logical phy 1 */
-
-    unsigned int phy2:5;  /**< [21-17] Rx Mapping value of logical phy 2 */
-
-    unsigned int reserved_1:1;  /**< [16] These bits are always 0 */
-
-    unsigned int phy3:5;  /**< [15-11] Rx Mapping value of logical phy 3 */
-
-    unsigned int phy4:5;  /**< [10-6] Rx Mapping value of logical phy 4 */
-
-    unsigned int phy5:5;  /**< [5-1] Rx Mapping value of logical phy 5 */
-
-    unsigned int reserved_2:1;  /**< [0] These bits are always 0 */
-    }
-
-    utRxTransTable0;  /**< Rx translation table */
-
-  /**
-    * @ingroup IxAtmdAccUtopiaCtrlAPI
-  * @struct UtRxTransTable1_
-  * @brief Utopia Rx translation table Register
-    */
-    struct UtRxTransTable1_
-    {
-
-    unsigned int phy6:5;  /**< [31-27] Rx Mapping value of logical phy 6 */
-
-    unsigned int phy7:5;  /**< [26-22] Rx Mapping value of logical phy 7 */
-
-    unsigned int phy8:5;  /**< [21-17] Rx Mapping value of logical phy 8 */
-
-    unsigned int reserved_1:1; /**< [16-0] These bits are always 0 */
-
-    unsigned int phy9:5;  /**< [15-11] Rx Mapping value of logical phy 3 */
-
-    unsigned int phy10:5;   /**< [10-6] Rx Mapping value of logical phy 4 */
-
-    unsigned int phy11:5;   /**< [5-1] Rx Mapping value of logical phy 5 */
-
-    unsigned int reserved_2:1;  /**< [0] These bits are always 0 */
-    }
-
-    utRxTransTable1;  /**< Rx translation table */
-
-    /**
-    * @ingroup IxAtmdAccUtopiaCtrlAPI
-    * @struct UtRxTransTable2_
-    * @brief Utopia Rx translation table Register
-    */
-    struct UtRxTransTable2_
-    {
-
-    unsigned int phy12:5;   /**< [31-27] Rx Mapping value of logical phy 6 */
-
-    unsigned int phy13:5;   /**< [26-22] Rx Mapping value of logical phy 7 */
-
-    unsigned int phy14:5;   /**< [21-17] Rx Mapping value of logical phy 8 */
-
-    unsigned int reserved_1:1; /**< [16-0] These bits are always 0 */
-
-    unsigned int phy15:5;   /**< [15-11] Rx Mapping value of logical phy 3 */
-
-    unsigned int phy16:5;   /**< [10-6] Rx Mapping value of logical phy 4 */
-
-    unsigned int phy17:5;   /**< [5-1] Rx Mapping value of logical phy 5 */
-
-    unsigned int reserved_2:1;  /**< [0] These bits are always 0 */
-    } utRxTransTable2;    /**< Rx translation table */
-
-    /**
-    * @ingroup IxAtmdAccUtopiaCtrlAPI
-    * @struct UtRxTransTable3_
-    * @brief Utopia Rx translation table Register
-    */
-    struct UtRxTransTable3_
-    {
-
-    unsigned int phy18:5;   /**< [31-27] Rx Mapping value of logical phy 6 */
-
-    unsigned int phy19:5;   /**< [26-22] Rx Mapping value of logical phy 7 */
-
-    unsigned int phy20:5;   /**< [21-17] Rx Mapping value of logical phy 8 */
-
-    unsigned int reserved_1:1; /**< [16-0] These bits are always 0 */
-
-    unsigned int phy21:5;   /**< [15-11] Rx Mapping value of logical phy 3 */
-
-    unsigned int phy22:5;   /**< [10-6] Rx Mapping value of logical phy 4 */
-
-    unsigned int phy23:5;   /**< [5-1] Rx Mapping value of logical phy 5 */
-
-    unsigned int reserved_2:1;  /**< [0] These bits are always 0 */
-    } utRxTransTable3;  /**< Rx translation table */
-
-    /**
-    * @ingroup IxAtmdAccUtopiaCtrlAPI
-    * @struct UtRxTransTable4_
-    * @brief Utopia Rx translation table Register
-    */
-    struct UtRxTransTable4_
-    {
-
-    unsigned int phy24:5;   /**< [31-27] Rx Mapping value of logical phy 6 */
-
-    unsigned int phy25:5;   /**< [26-22] Rx Mapping value of logical phy 7 */
-
-    unsigned int phy26:5;   /**< [21-17] Rx Mapping value of logical phy 8 */
-
-    unsigned int reserved_1:1; /**< [16-0] These bits are always 0 */
-
-    unsigned int phy27:5;   /**< [15-11] Rx Mapping value of logical phy 3 */
-
-    unsigned int phy28:5;   /**< [10-6] Rx Mapping value of logical phy 4 */
-
-    unsigned int phy29:5;   /**< [5-1] Rx Mapping value of logical phy 5 */
-
-    unsigned int reserved_2:1;  /**< [0] These bits are always 0 */
-    } utRxTransTable4;  /**< Rx translation table */
-
-    /**
-    * @ingroup IxAtmdAccUtopiaCtrlAPI
-    * @struct UtRxTransTable5_
-    * @brief Utopia Rx translation table Register
-    */
-    struct UtRxTransTable5_
-    {
-
-    unsigned int phy30:5;   /**< [31-27] Rx Mapping value of logical phy 6 */
-
-    unsigned int reserved_1:27;     /**< [26-0] These bits are always 0 */
-
-    } utRxTransTable5;  /**< Rx translation table */
-
-    /**
-    * @ingroup IxAtmdAccUtopiaCtrlAPI
-    * @struct UtSysConfig_
-    * @brief NPE setup Register
-    */
-    struct UtSysConfig_
-    {
-
-    unsigned int reserved_1:2;     /**< [31-30] These bits are always 0 */
-    unsigned int txEnbFSM:1;    /**< [29] Enables the operation ofthe Utopia Transmit FSM
-   * @li 1 - FSM enabled
-   * @li 0 - FSM inactive
-   */
-    unsigned int rxEnbFSM:1;    /**< [28] Enables the operation ofthe Utopia Revieve FSM
-   * @li 1 - FSM enabled
-   * @li 0 - FSM inactive
-   */
-    unsigned int disablePins:1;    /**< [27] Disable Utopia interface I/O pins forcing the signals to an
-   * inactive state.  Note that this bit is set on reset and must be
-   * de-asserted
-   * @li 0 - Normal data transfer
-   * @li    1 - Utopia interface pins are forced inactive
-    */
-    unsigned int tstLoop:1;    /**< [26] Test Loop Back Enable.
-    * @li Note: For loop back to function RxMode and Tx Mode must both be set
-    * to single PHY mode.
-    * @li 0 - Loop back
-    * @li 1 - Normal operating mode
-    */
-
-    unsigned int txReset:1;   /**< [25] Resets the Utopia Coprocessor transmit module to a known state.
-    * @li Note: All transmit configuration and status registers will be reset
-    * to their reset values.
-    * @li 0 - Normal operating mode
-    * @li 1 - Reset transmit modules
-    */
-
-    unsigned int rxReset:1;   /**< [24] Resets the Utopia Coprocessor receive module to a known state.
-    * @li Note: All receive configuration and status registers will be reset
-    * to their reset values.
-    * @li    0 - Normal operating mode
-    * @li 1 - Reset receive modules
-    */
-
-    unsigned int reserved_2:24;     /**< [23-0] These bits are always 0 */
-    } utSysConfig;  /**< NPE debug config */
-
-}
-IxAtmdAccUtopiaConfig;
-
-/**
-*
-* @brief Utopia status
-*
-* This structure is used to set/get the Utopia status parameters
-* @li contains debug cell counters, to be accessed during a read operation
-*
-* @note - the exact description of all parameters is done in the Utopia reference
-*   documents.
-*
-*/
-typedef struct
-{
-
-    unsigned int utTxCellCount;  /**< count of cells transmitted */
-
-    unsigned int utTxIdleCellCount;    /**< count of idle cells transmitted */
-
-    /**
-    * @ingroup IxAtmdAccUtopiaCtrlAPI
-    * @struct UtTxCellConditionStatus_
-    * @brief Utopia Tx Status Register
-    */
-    struct UtTxCellConditionStatus_
-    {
-
-    unsigned int reserved_1:2;   /**< [31:30] These bits are always 0 */
-    unsigned int txFIFO2Underflow:1; /**< [29] This bit is set if 64-byte
-                                     * Transmit FIFO2 indicates a FIFO underflow
-                                     * error condition.
-                                     */
-    unsigned int txFIFO1Underflow:1; /**< [28] This bit is set if
-                                     * 64-byte Transmit FIFO1 indicates a FIFO
-                                     * underflow error condition.
-                                     */
-    unsigned int txFIFO2Overflow:1;  /**< [27] This bit is set if 64-byte
-                                     * Transmit FIFO2 indicates a FIFO overflow
-                                     * error condition.
-                                     */
-    unsigned int txFIFO1Overflow:1; /**< [26] This bit is set if 64-byte
-                                    * Transmit FIFO1 indicates a FIFO overflow
-                                    * error condition.
-                                    */
-    unsigned int txIdleCellCountOvr:1; /**< [25] This bit is set if the
-                                       * TxIdleCellCount register overflows.
-                                       */
-    unsigned int txCellCountOvr:1; /**< [24] This bit is set if the
-                                   * TxCellCount register overflows
-                                   */
-    unsigned int reserved_2:24;    /**< [23:0] These bits are always 0 */
-    } utTxCellConditionStatus;    /**< Tx cells condition status */
-
-    unsigned int utRxCellCount; /**< count of cell received */
-    unsigned int utRxIdleCellCount;    /**< count of idle cell received */
-    unsigned int utRxInvalidHECount;     /**< count of invalid cell
-                                        * received because of HEC errors
-                                        */
-    unsigned int utRxInvalidParCount;  /**< count of invalid cell received
-                                        * because of parity errors
-                                        */
-    unsigned int utRxInvalidSizeCount;  /**< count of invalid cell
-                                        * received because of cell
-                                        * size errors
-                                        */
-
-    /**
-    * @ingroup IxAtmdAccUtopiaCtrlAPI
-    * @struct UtRxCellConditionStatus_
-    * @brief Utopia Rx Status Register
-    */
-    struct UtRxCellConditionStatus_
-    {
-
-    unsigned int reserved_1:3;  /**< [31:29] These bits are always 0.*/
-    unsigned int rxCellCountOvr:1;      /**< [28] This bit is set if the RxCellCount register overflows. */
-    unsigned int invalidHecCountOvr:1;    /**< [27] This bit is set if the InvalidHecCount register overflows.*/
-    unsigned int invalidParCountOvr:1;    /**< [26] This bit is set if the InvalidParCount register overflows.*/
-    unsigned int invalidSizeCountOvr:1;    /**< [25] This bit is set if the InvalidSizeCount register overflows.*/
-    unsigned int rxIdleCountOvr:1;      /**< [24] This bit is set if the RxIdleCount register overflows.*/
-    unsigned int reserved_2:4;  /**< [23:20] These bits are always 0 */
-    unsigned int rxFIFO2Underflow:1;  /**< [19] This bit is set if 64-byte Receive FIFO2
-                                      * indicates a FIFO underflow error condition.
-                                      */
-    unsigned int rxFIFO1Underflow:1;  /**< [18] This bit is set if 64-byte Receive
-                                      * FIFO1 indicates a FIFO underflow error condition
-                                    . */
-    unsigned int rxFIFO2Overflow:1;    /**< [17] This bit is set if 64-byte Receive FIFO2
-                                       * indicates a FIFO overflow error condition.
-                                        */
-    unsigned int rxFIFO1Overflow:1;    /**< [16] This bit is set if 64-byte Receive FIFO1
-                                    * indicates a FIFO overflow error condition.
-                                    */
-    unsigned int reserved_3:16;      /**< [15:0] These bits are always 0. */
-    } utRxCellConditionStatus;    /**< Rx cells condition status */
-
-} IxAtmdAccUtopiaStatus;
-
-/**
- * @} defgroup IxAtmdAccUtopiaCtrlAPI
- */
-
- /**
- *
- * @ingroup IxAtmdAccCtrlAPI
- *
- * @fn ixAtmdAccUtopiaConfigSet (const IxAtmdAccUtopiaConfig *
-                        ixAtmdAccUtopiaConfigPtr)
- *
- * @brief Send the configuration structure to the Utopia interface
- *
- * This function downloads the @a IxAtmdAccUtopiaConfig structure to
- * the Utopia and has the following effects
- *  @li setup the Utopia interface
- *  @li initialise the NPE
- *  @li reset the Utopia cell counters and status registers to known values
- *
- * This action has to be done once at initialisation. A lock is preventing
- * the concurrent use of @a ixAtmdAccUtopiaStatusGet() and
- * @A ixAtmdAccUtopiaConfigSet()
- *
- * @param *ixAtmdAccNPEConfigPtr @ref IxAtmdAccUtopiaConfig [in] - pointer to a structure to download to
- *  Utopia. This parameter cannot be a null pointer.
- *
- * @return @li IX_SUCCESS successful download
- * @return @li IX_FAIL error in the parameters, or configuration is not
- *         complete or failed
- *
- * @sa ixAtmdAccUtopiaStatusGet
- *
- */
-PUBLIC IX_STATUS ixAtmdAccUtopiaConfigSet (const IxAtmdAccUtopiaConfig *
-                        ixAtmdAccUtopiaConfigPtr);
-
-/**
- *
- * @ingroup IxAtmdAccCtrlAPI
- *
- * @fn ixAtmdAccUtopiaStatusGet (IxAtmdAccUtopiaStatus *
-                        ixAtmdAccUtopiaStatus)
- *
- * @brief Get the Utopia interface configuration.
- *
- * This function reads the Utopia registers and the Cell counts
- * and fills the @a IxAtmdAccUtopiaStatus structure
- *
- * A lock is preventing the concurrent
- * use of @a ixAtmdAccUtopiaStatusGet() and @A ixAtmdAccUtopiaConfigSet()
- *
- * @param ixAtmdAccUtopiaStatus @ref IxAtmdAccUtopiaStatus [out] - pointer to structure to be updated from internal
- *        hardware counters. This parameter cannot be a NULL pointer.
- *
- * @return @li IX_SUCCESS successful read
- * @return @li IX_FAIL error in the parameters null pointer, or
- *          configuration read is not complete or failed
- *
- * @sa ixAtmdAccUtopiaConfigSet
- *
- */
-PUBLIC IX_STATUS ixAtmdAccUtopiaStatusGet (IxAtmdAccUtopiaStatus *
-                        ixAtmdAccUtopiaStatus);
-
-/**
- *
- * @ingroup IxAtmdAcc
- *
- * @fn ixAtmdAccPortEnable (IxAtmLogicalPort port)
- *
- * @brief enable a PHY logical port
- *
- * This function enables the transmission over one port. It should be
- * called before accessing any resource from this port and before the
- * establishment of a VC.
- *
- * When a port is enabled, the cell transmission to the Utopia interface
- * is started. If there is no traffic already running, idle cells are
- * sent over the interface.
- *
- * This function can be called multiple times.
- *
- * @param port @ref IxAtmLogicalPort [in] - logical PHY port [@a IX_UTOPIA_PORT_0 .. @a IX_UTOPIA_MAX_PORTS - 1]
- *
- * @return @li IX_SUCCESS enable is complete
- * @return @li IX_ATMDACC_WARNING port already enabled
- * @return @li IX_FAIL enable failed, wrong parameter, or cannot
- *         initialise this port (the port is maybe already in use,
- *         or there is a hardware issue)
- *
- * @note - This function needs internal locks and should not be
- *         called from an interrupt context
- *
- * @sa ixAtmdAccPortDisable
- *
- */
-PUBLIC IX_STATUS ixAtmdAccPortEnable (IxAtmLogicalPort port);
-
-/**
- *
- * @ingroup IxAtmdAccCtrlAPI
- *
- * @fn ixAtmdAccPortDisable (IxAtmLogicalPort port)
- *
- * @brief disable a PHY logical port
- *
- * This function disable the transmission over one port.
- *
- * When a port is disabled, the cell transmission to the Utopia interface
- * is stopped.
- *
- * @param port @ref IxAtmLogicalPort [in] - logical PHY port [@a IX_UTOPIA_PORT_0 .. @a IX_UTOPIA_MAX_PORTS - 1]
- *
- * @return @li IX_SUCCESS disable is complete
- * @return @li IX_ATMDACC_WARNING port already disabled
- * @return @li IX_FAIL disable failed, wrong parameter .
- *
- * @note - This function needs internal locks and should not be called
- *         from an interrupt context
- *
- * @note - The response from hardware is done through the txDone mechanism
- *         to ensure the synchrnisation with tx resources. Therefore, the
- *         txDone mechanism needs to be serviced to make a PortDisable complete.
- *
- * @sa ixAtmdAccPortEnable
- * @sa ixAtmdAccPortDisableComplete
- * @sa ixAtmdAccTxDoneDispatch
- *
- */
-PUBLIC IX_STATUS ixAtmdAccPortDisable (IxAtmLogicalPort port);
-
-/**
-*
-* @ingroup IxAtmdAccCtrlAPI
-*
-* @fn ixAtmdAccPortDisableComplete (IxAtmLogicalPort port)
-*
-* @brief disable a PHY logical port
-*
-* This function indicates if the port disable for a port has completed. This
-* function will return true if the port has never been enabled.
-*
-* @param port @ref IxAtmLogicalPort [in] - logical PHY port [@a IX_UTOPIA_PORT_0 .. @a IX_UTOPIA_MAX_PORTS - 1]
-*
-* @return @li true disable is complete
-* @return @li false disable failed, wrong parameter .
-*
-* @note - This function needs internal locks and should not be called
-*         from an interrupt context
-*
-* @sa ixAtmdAccPortEnable
-* @sa ixAtmdAccPortDisable
-*
-*/
-PUBLIC BOOL ixAtmdAccPortDisableComplete (IxAtmLogicalPort port);
-
-#endif /* IXATMDACCCTRL_H */
-
-/**
- * @} defgroup IxAtmdAccCtrlAPI
- */
-
-
diff --git a/drivers/net/npe/include/IxAtmm.h b/drivers/net/npe/include/IxAtmm.h
deleted file mode 100644
index 805b8c9bd6..0000000000
--- a/drivers/net/npe/include/IxAtmm.h
+++ /dev/null
@@ -1,771 +0,0 @@
-/**
- * @file    IxAtmm.h
- *
- * @date    3-DEC-2001
- *
- * @brief   Header file for the IXP400 ATM Manager component (IxAtmm)
- *
- * 
- * @par
- * IXP400 SW Release version 2.0
- * 
- * -- Copyright Notice --
- * 
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- * 
- * @par
- * SPDX-License-Identifier:	BSD-3-Clause
- * @par
- * -- End of Copyright Notice --
- */
-
-
-/**
- * @defgroup IxAtmm IXP400 ATM Manager (IxAtmm) API
- *
- * @brief IXP400 ATM Manager component Public API
- *
- * @{
- */
-
-#ifndef IXATMM_H
-#define IXATMM_H
-
-/*
- * Put the user defined include files required
- */
-#include "IxAtmSch.h"
-#include "IxOsalTypes.h"
-
-/*
- * #defines and macros used in this file.
- */
-
-/** 
- * @def IX_ATMM_RET_ALREADY_INITIALIZED
- * 
- * @brief Component has already been initialized 
- */
-#define IX_ATMM_RET_ALREADY_INITIALIZED 2
-
-/** 
- * @def IX_ATMM_RET_INVALID_PORT
- * 
- * @brief Specified port does not exist or is out of range */
-#define IX_ATMM_RET_INVALID_PORT 3
-
-/** 
- * @def IX_ATMM_RET_INVALID_VC_DESCRIPTOR
- * 
- * @brief The VC description does not adhere to ATM standards */
-#define IX_ATMM_RET_INVALID_VC_DESCRIPTOR 4
-
-/** 
- * @def IX_ATMM_RET_VC_CONFLICT
- * 
- * @brief The VPI/VCI values supplied are either reserved, or they
- *         conflict with a previously registered VC on this port */
-#define IX_ATMM_RET_VC_CONFLICT 5
-
-/** 
- * @def IX_ATMM_RET_PORT_CAPACITY_IS_FULL
- * 
- * @brief The virtual connection cannot be established on the port
- *         because the remaining port capacity is not sufficient to
- *         support it */
-#define IX_ATMM_RET_PORT_CAPACITY_IS_FULL 6
-
-/** 
- * @def IX_ATMM_RET_NO_SUCH_VC
- * 
- * @brief No registered VC, as described by the supplied VCI/VPI or
- *         VC identifier values, exists on this port */
-#define IX_ATMM_RET_NO_SUCH_VC 7
-
-/** 
- * @def IX_ATMM_RET_INVALID_VC_ID
- * 
- * @brief The specified VC identifier is out of range. */
-#define IX_ATMM_RET_INVALID_VC_ID 8
-
-/** 
- * @def IX_ATMM_RET_INVALID_PARAM_PTR
- * 
- * @brief A pointer parameter was NULL. */
-#define IX_ATMM_RET_INVALID_PARAM_PTR 9
-
-/** 
- * @def IX_ATMM_UTOPIA_SPHY_ADDR  
- * 
- * @brief The phy address when in SPHY mode */
-#define IX_ATMM_UTOPIA_SPHY_ADDR 31
-
-/**
- * @def IX_ATMM_THREAD_PRI_HIGH
- *
- * @brief The value of high priority thread */
-#define IX_ATMM_THREAD_PRI_HIGH 90
-
-/*
- * Typedefs whose scope is limited to this file.
- */
-
-/** @brief Definition for use in the @ref IxAtmmVc structure.
- *         Indicates the direction of a VC */
-typedef enum
-{
-    IX_ATMM_VC_DIRECTION_TX=0, /**< Atmm Vc direction transmit*/
-    IX_ATMM_VC_DIRECTION_RX, /**< Atmm Vc direction receive*/
-    IX_ATMM_VC_DIRECTION_INVALID /**< Atmm Vc direction invalid*/
-} IxAtmmVcDirection;
-
-/** @brief Definition for use with @ref IxAtmmVcChangeCallback
- *         callback.  Indicates that the event type represented by the
- *         callback for this VC. */
-typedef enum
-{
-    IX_ATMM_VC_CHANGE_EVENT_REGISTER=0, /**< Atmm Vc event register*/
-    IX_ATMM_VC_CHANGE_EVENT_DEREGISTER, /**< Atmm Vc event de-register*/
-    IX_ATMM_VC_CHANGE_EVENT_INVALID /**< Atmm Vc event invalid*/
-} IxAtmmVcChangeEvent;
-
-/** @brief Definitions for use with @ref ixAtmmUTOPIAInit interface to
- *         indicate that UTOPIA loopback should be enabled or disabled
- *         on initialisation. */
-typedef enum
-{
-    IX_ATMM_UTOPIA_LOOPBACK_DISABLED=0, /**< Atmm Utopia loopback mode disabled*/
-    IX_ATMM_UTOPIA_LOOPBACK_ENABLED, /**< Atmm Utopia loopback mode enabled*/
-    IX_ATMM_UTOPIA_LOOPBACK_INVALID /**< Atmm Utopia loopback mode invalid*/
-} IxAtmmUtopiaLoopbackMode;
-
-/** @brief This structure describes the required attributes of a
- *         virtual connection.
-*/
-typedef struct {
-    unsigned vpi;  /**< VPI value of this virtual connection */
-    unsigned vci;  /**< VCI value of this virtual connection. */
-    IxAtmmVcDirection direction; /**< VC direction */
-
-    /** Traffic descriptor of this virtual connection.  This structure
-     *  is defined by the @ref IxAtmSch component.  */
-    IxAtmTrafficDescriptor trafficDesc;
-} IxAtmmVc;
-
-
-/** @brief Definitions for use with @ref ixAtmmUtopiaInit interface to
- *         indicate that UTOPIA multi-phy/single-phy mode is used.
- */
-typedef enum
-{
-    IX_ATMM_MPHY_MODE = 0, /**< Atmm phy mode mphy*/
-    IX_ATMM_SPHY_MODE, /**< Atmm phy mode sphy*/
-    IX_ATMM_PHY_MODE_INVALID /**< Atmm phy mode invalid*/
-} IxAtmmPhyMode;
-
-
-/** @brief Structure contains port-specific information required to
- *         initialize IxAtmm, and specifically, the IXP400 UTOPIA
- *         Level-2 device. */
-typedef struct {
-    unsigned reserved_1:11;     /**< [31:21] Should be zero */
-    unsigned UtopiaTxPhyAddr:5; /**< [20:16] Address of the
-     *   transmit (Tx) PHY for this
-     *   port on the 5-bit UTOPIA
-     *   Level-2 address bus */
-    unsigned reserved_2:11;     /**< [15:5] Should be zero */
-    unsigned UtopiaRxPhyAddr:5; /**< [4:0] Address of the receive
-     *   (Rx) PHY for this port on the
-     *   5-bit UTOPIA  Level-2
-     *   address bus */
-} IxAtmmPortCfg;
-
-/** @brief Callback type used with @ref ixAtmmVcChangeCallbackRegister interface
- *         Defines a callback type  which will be used to notify registered
- *         users of registration/deregistration events on a particular port
- *
- * @param eventType @ref IxAtmmVcChangeEvent [in] - Event indicating
- *                        whether the VC supplied has been added or
- *                        removed
- *
- * @param port @ref IxAtmLogicalPort [in] - Specifies the port on which the event has
- *                        occurred
- *
- * @param vcChanged @ref IxAtmmVc* [in] - Pointer to a structure which gives
- *                              details of the VC which has been added
- *                              or removed on the port
- */
-typedef void (*IxAtmmVcChangeCallback) (IxAtmmVcChangeEvent eventType,
-					IxAtmLogicalPort port,
-					const IxAtmmVc* vcChanged);
-
-/*
- * Variable declarations global to this file only. Externs are followed by
- * static variables.
- */
-
-/*
- * Extern function prototypes
- */
-
-/*
- * Function declarations
- */
-
-
-/** 
- * @ingroup IxAtmm
- *
- * @fn ixAtmmInit (void)
- *
- * @brief Interface to initialize the IxAtmm software component.  Can
- *         be called once only.
- *
- *  Must be called before any other IxAtmm API is called.
- *
- * @param "none"
- *
- *  @return @li  IX_SUCCESS : IxAtmm has been successfully initialized.
- *      Calls to other IxAtmm interfaces may now be performed.
- *  @return @li  IX_FAIL : IxAtmm has already been initialized.
- */
-PUBLIC IX_STATUS
-ixAtmmInit (void);
-
-/**  
- * @ingroup IxAtmm
- * 
- * @fn ixAtmmUtopiaInit (unsigned numPorts,
-		  IxAtmmPhyMode phyMode,
-		  IxAtmmPortCfg portCfgs[],
-		  IxAtmmUtopiaLoopbackMode loopbackMode)
- *
- * @brief Interface to initialize the UTOPIA Level-2 ATM coprocessor
- *         for the specified number of physical ports.  The function
- *         must be called before the ixAtmmPortInitialize interface
- *         can operate successfully.
- *
- * @param numPorts unsigned [in] - Indicates the total number of logical
- *          ports that are active on the device.  Up to 12 ports are
- *          supported.
- *
- * @param phyMode @ref IxAtmmPhyMode [in] - Put the Utopia coprocessor in SPHY
- *        or MPHY mode.
- *
- * @param portCfgs[] @ref IxAtmmPortCfg [in] - Pointer to an array of elements
- *          detailing the UTOPIA specific port characteristics.  The
- *          length of the array must be equal to the number of ports
- *          activated.  ATM ports are referred to by the relevant
- *          offset in this array in all subsequent IxAtmm interface
- *          calls.
- *
- * @param loopbackMode @ref IxAtmmUtopiaLoopbackMode [in] - Value must be one of
- *          @ref IX_ATMM_UTOPIA_LOOPBACK_ENABLED or @ref
- *          IX_ATMM_UTOPIA_LOOPBACK_DISABLED indicating whether
- *          loopback should be enabled on the device.  Loopback can
- *          only be supported on a single PHY, therefore the numPorts
- *          parameter must be 1 if loopback is enabled.
- *
- * @return @li IX_SUCCESS : Indicates that the  UTOPIA device has been
- *      successfully initialized for the supplied ports.
- * @return @li IX_ATMM_RET_ALREADY_INITIALIZED : The UTOPIA device has
- *      already been initialized.
- * @return @li IX_FAIL : The supplied parameters are invalid or have been
- *     rejected by the UTOPIA-NPE device.
- *
- * @warning
- * This interface may only be called once.
- * Port identifiers are assumed to range from 0 to (numPorts - 1) in all 
- * instances.
- * In all subsequent calls to interfaces supplied by IxAtmm, the specified
- * port value is expected to represent the offset in the portCfgs array
- * specified in this interface.  i.e. The first port in this array will
- * subsequently be represented as port 0, the second port as port 1,
- * and so on.*/
-PUBLIC IX_STATUS
-ixAtmmUtopiaInit (unsigned numPorts,
-		  IxAtmmPhyMode phyMode,
-		  IxAtmmPortCfg portCfgs[],
-		  IxAtmmUtopiaLoopbackMode loopbackMode);
-
-
-/**   
- * @ingroup IxAtmm
- * 
- * @fn ixAtmmPortInitialize (IxAtmLogicalPort port,
-		      unsigned txPortRate,
-		      unsigned rxPortRate)
- *
- * @brief The interface is called following @ref ixAtmmUtopiaInit ()
- *         and before calls to any other IxAtmm interface.  It serves
- *         to activate the registered ATM port with IxAtmm.
- *
- *  The transmit and receive port rates are specified in bits per
- *  second.  This translates to ATM cells per second according to the
- *  following formula: CellsPerSecond = portRate / (53*8)  The
- *  IXP400 device supports only 53 byte cells. The client shall make
- *  sure that the off-chip physical layer device has already been
- *  initialized.
- *
- *  IxAtmm will configure IxAtmdAcc and IxAtmSch to enable scheduling
- *  on the port.
- *
- *  This interface must be called once for each active port in the
- *  system.  The first time the interface is invoked, it will configure
- *  the mechanism by which the handling of transmit, transmit-done and
- *  receive are driven with the IxAtmdAcc component.
- *
- *  This function is reentrant.
- *
- *  @note The minimum tx rate that will be accepted is 424 bit/s which equates
- *        to 1 cell (53 bytes) per second.
- *
- * @param port @ref IxAtmLogicalPort [in] - Identifies the port which is to be
- *          initialized.
- *
- * @param txPortRate unsigned [in] - Value specifies the
- *          transmit port rate for this port in
- *          bits/second.  This value is used by the ATM Scheduler
- *          component is evaluating VC access requests for the port.
- *
- * @param rxPortRate unsigned [in] - Value specifies the
- *          receive port rate for this port in bits/second.
- *
- * @return @li IX_SUCCESS : The specificed ATM port has been successfully
- *       initialized. IxAtmm is ready to accept VC registrations on
- *       this port.
- *
- * @return @li IX_ATMM_RET_ALREADY_INITIALIZED : ixAtmmPortInitialize has
- *       already been called successfully on this port.  The current
- *       call is rejected.
- *
- * @return @li IX_ATMM_RET_INVALID_PORT : The port value indicated in the
- *       input is not valid.  The request is rejected.
- *
- * @return @li IX_FAIL : IxAtmm could not initialize the port because the
- * inputs are not understood.
- *
- * @sa ixAtmmPortEnable, ixAtmmPortDisable
- *
- */
-PUBLIC IX_STATUS
-ixAtmmPortInitialize (IxAtmLogicalPort port,
-		      unsigned txPortRate,
-		      unsigned rxPortRate);
-
-/**    
- * @ingroup IxAtmm
- * 
- * @fn ixAtmmPortModify (IxAtmLogicalPort port,
-		  unsigned txPortRate,
-		  unsigned rxPortRate)
- *
- * @brief A client may call this interface to change the existing
- *         port rate (expressed in bits/second) on an established ATM
- *         port.
- *
- * @param port @ref IxAtmLogicalPort [in] - Identifies the port which is to be
- *          initialized.
- *
- * @param txPortRate unsigned [in] -  Value specifies the``
- *          transmit port rate for this port in
- *          bits/second.  This value is used by the ATM Scheduler
- *          component is evaluating VC access requests for the port.
- *
- * @param rxPortRate unsigned [in] - Value specifies the
- *          receive port rate for this port in
- *          bits/second.
- *
- * @return @li IX_SUCCESS : The indicated ATM port rates have been
- *      successfully modified.
- *
- * @return @li IX_ATMM_RET_INVALID_PORT : The port value indicated in the
- *       input is not valid.  The request is rejected.
- *
- * @return @li IX_FAIL : IxAtmm could not update the port because the
- *       inputs are not understood, or the interface was called before
- * the port was initialized.  */
-PUBLIC IX_STATUS
-ixAtmmPortModify (IxAtmLogicalPort port,
-		  unsigned txPortRate,
-		  unsigned rxPortRate);
-
-/**    
- * @ingroup IxAtmm
- * 
- * @fn ixAtmmPortQuery (IxAtmLogicalPort port,
-		 unsigned *txPortRate,
-		 unsigned *rxPortRate);
-
- *
- * @brief The client may call this interface to request details on
- *          currently registered transmit and receive rates for an ATM
- *          port.
- *
- * @param port @ref IxAtmLogicalPort [in] - Value identifies the port from which the
- *          rate details are requested.
- *
- * @param *txPortRate unsigned [out] - Pointer to a value
- *          which will be filled with the value of the transmit port
- *          rate specified in bits/second.
- *
- * @param *rxPortRate unsigned [out] - Pointer to a value
- *          which will be filled with the value of the receive port
- *          rate specified in bits/second.
- *
- * @return @li IX_SUCCESS : The information requested on the specified
- *       port has been successfully supplied in the output.
- *
- * @return @li IX_ATMM_RET_INVALID_PORT : The port value indicated in the
- *       input is not valid.  The request is rejected.
- *
- * @return @li IX_ATMM_RET_INVALID_PARAM_PTR : A pointer parameter was
- *       NULL.
- *
- * @return @li IX_FAIL : IxAtmm could not update the port because the
- *       inputs are not understood, or the interface was called before
- *       the port was initialized.  */
-PUBLIC IX_STATUS
-ixAtmmPortQuery (IxAtmLogicalPort port,
-		 unsigned *txPortRate,
-		 unsigned *rxPortRate);
-
-/**    
- * @ingroup IxAtmm
- * 
- * @fn ixAtmmPortEnable(IxAtmLogicalPort port)
- *
- * @brief The client call this interface to enable transmit for an ATM
- *          port. At initialisation, all the ports are disabled.
- *
- * @param port @ref IxAtmLogicalPort [in] - Value identifies the port
- *
- * @return @li IX_SUCCESS : Transmission over this port is started.
- *
- * @return @li IX_FAIL : The port parameter is not valid, or the
- *       port is already enabled
- *
- * @note - When a port is disabled, Rx and Tx VC Connect requests will fail
- *
- * @note - This function uses system resources and should not be used
- *        inside an interrupt context.
- *
- * @sa ixAtmmPortDisable  */
-PUBLIC IX_STATUS
-ixAtmmPortEnable(IxAtmLogicalPort port);
-
-/**    
- * @ingroup IxAtmm
- * 
- * @fn ixAtmmPortDisable(IxAtmLogicalPort port)
- *
- * @brief The client call this interface to disable transmit for an ATM
- *          port. At initialisation, all the ports are disabled.
- *
- * @param port @ref IxAtmLogicalPort [in] - Value identifies the port
- *
- * @return @li IX_SUCCESS : Transmission over this port is stopped.
- *
- * @return @li IX_FAIL : The port parameter is not valid, or the
- *       port is already disabled
- *
- * @note - When a port is disabled, Rx and Tx VC Connect requests will fail
- *
- * @note - This function call does not stop RX traffic. It is supposed
- *        that this function is invoked when a serious problem
- *        is detected (e.g. physical layer broken). Then, the RX traffic
- *        is not passing.
- *
- * @note - This function is blocking until the hw acknowledge that the
- *        transmission is stopped.
- *
- * @note - This function uses system resources and should not be used
- *        inside an interrupt context.
- *
- * @sa ixAtmmPortEnable  */
-PUBLIC IX_STATUS
-ixAtmmPortDisable(IxAtmLogicalPort port);
-
-/**    
- * @ingroup IxAtmm
- * 
- * @fn ixAtmmVcRegister (IxAtmLogicalPort port,
-		  IxAtmmVc *vcToAdd,
-		  IxAtmSchedulerVcId *vcId)
- *
- * @brief This interface is used to register an ATM Virtual
- *         Connection on the specified ATM port.
- *
- *  Each call to this interface registers a unidirectional virtual
- *  connection with the parameters specified.  If a bi-directional VC
- *  is needed, the function should be called twice (once for each
- *  direction, Tx & Rx) where the VPI and VCI and port parameters in
- *  each call are identical.
- *
- *  With the addition of each new VC to a port, a series of
- *  callback functions are invoked by the IxAtmm component to notify
- *  possible external components of the change.  The callback functions
- *  are registered using the @ref ixAtmmVcChangeCallbackRegister interface.
- *
- *  The IxAtmSch component is notified of the registration of transmit
- *  VCs.
- *
- * @param port @ref IxAtmLogicalPort [in] - Identifies port on which the specified VC is
- *          to be registered.
- *
- * @param *vcToAdd @ref IxAtmmVc [in] -  Pointer to an @ref IxAtmmVc structure
- *          containing a description of the VC to be registered. The
- *          client shall fill the vpi, vci and direction and relevant
- *          trafficDesc members of this structure before calling this
- *          function.
- *
- * @param *vcId @ref IxAtmSchedulerVcId [out] - Pointer to an integer value which is filled
- *              with the per-port unique identifier value for this VC.
- *              This identifier will be required when a request is
- *              made to deregister or change this VC.  VC identifiers
- *              for transmit VCs will have a value between 0-43,
- *              i.e. 32 data Tx VCs + 12 OAM Tx Port VCs.
- *              Receive VCs will have a value between 44-66,
- *              i.e. 32 data Rx VCs + 1 OAM Rx VC.
- *
- * @return @li IX_SUCCESS : The VC has been successfully registered on
- *       this port. The VC is ready for a client to configure IxAtmdAcc
- *       for receive and transmit operations on the VC.
- * @return @li IX_ATMM_RET_INVALID_PORT : The port value indicated in the
- *       input is not valid or has not been initialized.  The request
- *       is rejected.
- * @return @li IX_ATMM_RET_INVALID_VC_DESCRIPTOR : The descriptor
- *       pointed to by vcToAdd is invalid.  The registration request
- *       is rejected.
- * @return @li IX_ATMM_RET_VC_CONFLICT : The VC requested conflicts with
- *      reserved VPI and/or VCI values or with another VC already activated
- *      on this port.
- * @return @li IX_ATMM_RET_PORT_CAPACITY_IS_FULL : The VC cannot be
- *       registered in the port becuase the port capacity is
- *       insufficient to support the requested ATM traffic contract.
- *       The registration request is rejected.
- * @return @li IX_ATMM_RET_INVALID_PARAM_PTR : A pointer parameter was
- *       NULL.
- *
- * @warning IxAtmm has no capability of signaling or negotiating a virtual
- *          connection. Negotiation of the admission of the VC to the network
- *          is beyond the scope of this function.  This is assumed to be
- *          performed by the calling client, if appropriate,
- *          before or after this function is called.
- */
-PUBLIC IX_STATUS
-ixAtmmVcRegister (IxAtmLogicalPort port,
-		  IxAtmmVc *vcToAdd,
-		  IxAtmSchedulerVcId *vcId);
-
-/**    
- * @ingroup IxAtmm
- * 
- * @fn ixAtmmVcDeregister (IxAtmLogicalPort port, IxAtmSchedulerVcId vcId)
- *
- * @brief Function called by a client to deregister a VC from the
- *         system.
- *
- *  With the removal of each new VC from a port, a series of
- *  registered callback functions are invoked by the IxAtmm component
- *  to notify possible external components of the change.  The callback
- *  functions are registered using the @ref ixAtmmVcChangeCallbackRegister.
- *
- *  The IxAtmSch component is notified of the removal of transmit VCs.
- *
- * @param port @ref IxAtmLogicalPort [in] - Identifies port on which the VC to be
- *          removed is currently registered.
- *
- * @param vcId @ref IxAtmSchedulerVcId [in] - VC identifier value of the VC to
- *          be deregistered.  This value was supplied to the client when
-            the VC was originally registered.  This value can also be
-	    queried from the IxAtmm component through the @ref ixAtmmVcQuery
- *          interface.
- *
- * @return @li IX_SUCCESS : The specified VC has been successfully
- *       removed from this port.
- * @return @li IX_ATMM_RET_INVALID_PORT : The port value indicated in the
- *       input is not valid or has not been initialized.  The request
- *       is rejected.
- * @return @li IX_FAIL : There is no registered VC associated with the
- *       supplied identifier registered on this port. */
-PUBLIC IX_STATUS
-ixAtmmVcDeregister (IxAtmLogicalPort port, IxAtmSchedulerVcId vcId);
-
-/**    
- * @ingroup IxAtmm
- * 
- * @fn ixAtmmVcQuery (IxAtmLogicalPort port,
-	       unsigned vpi,
-	       unsigned vci,
-	       IxAtmmVcDirection direction,
-	       IxAtmSchedulerVcId *vcId,
-	       IxAtmmVc *vcDesc)
- *
- * @brief This interface supplies information about an active VC on a
- *         particular port when supplied with the VPI, VCI and
- *         direction of that VC.
- *
- * @param port @ref IxAtmLogicalPort [in] - Identifies port on which the VC to be
- *          queried is currently registered.
- *
- * @param vpi unsigned [in] - ATM VPI value of the requested VC.
- *
- * @param vci unsigned [in] - ATM VCI value of the requested VC.
- *
- * @param direction @ref IxAtmmVcDirection [in] - One of @ref
- *          IX_ATMM_VC_DIRECTION_TX or @ref IX_ATMM_VC_DIRECTION_RX
- *          indicating the direction (Tx or Rx) of the requested VC.
- *
- * @param *vcId @ref IxAtmSchedulerVcId [out] - Pointer to an integer value which will be
- *              filled with the VC identifier value for the requested
- *              VC (as returned by @ref ixAtmmVcRegister), if it
- *              exists on this port.
- *
- * @param *vcDesc @ref IxAtmmVc [out] - Pointer to an @ref IxAtmmVc structure
- *              which will be filled with the specific details of the
- *              requested VC, if it exists on this port.
- *
- * @return @li IX_SUCCESS : The specified VC has been found on this port
- *       and the requested details have been returned.
- * @return @li IX_ATMM_RET_INVALID_PORT : The port value indicated in the
- *       input is not valid or has not been initialized.  The request
- *       is rejected.
- * @return @li IX_ATMM_RET_NO_SUCH_VC : No VC exists on the specified
- *       port which matches the search criteria (VPI, VCI, direction)
- *       given.  No data is returned.
- * @return @li IX_ATMM_RET_INVALID_PARAM_PTR : A pointer parameter was
- *       NULL.
- *
- */
-PUBLIC IX_STATUS
-ixAtmmVcQuery (IxAtmLogicalPort port,
-	       unsigned vpi,
-	       unsigned vci,
-	       IxAtmmVcDirection direction,
-	       IxAtmSchedulerVcId *vcId,
-	       IxAtmmVc *vcDesc);
-
-
-/**    
- * @ingroup IxAtmm
- * 
- * @fn ixAtmmVcIdQuery (IxAtmLogicalPort port, IxAtmSchedulerVcId vcId, IxAtmmVc *vcDesc)
- *
- * @brief This interface supplies information about an active VC on a
- *         particular port when supplied with a vcId for that VC.
- *
- * @param port @ref IxAtmLogicalPort [in] - Identifies port on which the VC to be
- *          queried is currently registered.
- *
- * @param vcId @ref IxAtmSchedulerVcId [in] - Value returned by @ref ixAtmmVcRegister which
- *          uniquely identifies the requested VC on this port.
- *
- * @param *vcDesc @ref IxAtmmVc [out] - Pointer to an @ref IxAtmmVc structure
- *              which will be filled with the specific details of the
- *              requested VC, if it exists on this port.
- *
- * @return @li IX_SUCCESS : The specified VC has been found on this port
- *       and the requested details have been returned.
- * @return @li IX_ATMM_RET_INVALID_PORT : The port value indicated in the
- *       input is not valid or has not been initialized.  The request
- *       is rejected.
- * @return @li IX_ATMM_RET_NO_SUCH_VC : No VC exists on the specified
- *       port which matches the supplied identifier.  No data is
- *       returned.
- * @return @li IX_ATMM_RET_INVALID_PARAM_PTR : A pointer parameter was
- *       NULL.
- */
-PUBLIC IX_STATUS
-ixAtmmVcIdQuery (IxAtmLogicalPort port, IxAtmSchedulerVcId vcId, IxAtmmVc *vcDesc);
-
-/**    
- * @ingroup IxAtmm
- * 
- * @fn ixAtmmVcChangeCallbackRegister (IxAtmmVcChangeCallback callback)
- *
- * @brief This interface is invoked to supply a function to IxAtmm
- *         which will be called to notify the client if a new VC is
- *         registered with IxAtmm or an existing VC is removed.
- *
- * The callback, when invoked, will run within the context of the call
- * to @ref ixAtmmVcRegister or @ref ixAtmmVcDeregister which caused
- * the change of state.
- *
- * A maximum of 32 calbacks may be registered in with IxAtmm.
- *
- * @param callback @ref IxAtmmVcChangeCallback [in] - Callback which complies
- *          with the @ref IxAtmmVcChangeCallback definition.  This
- *          function will be invoked by IxAtmm with the appropiate
- *          parameters for the relevant VC when any VC has been
- *          registered or deregistered with IxAtmm.
- *
- * @return @li IX_SUCCESS : The specified callback has been registered
- *      successfully with IxAtmm and will be invoked when appropriate.
- * @return @li IX_FAIL : Either the supplied callback is invalid, or
- *      IxAtmm has already registered 32 and connot accommodate
- *      any further registrations of this type.  The request is
- *      rejected.
- *
- * @warning The client must not call either the @ref
- *          ixAtmmVcRegister or @ref ixAtmmVcDeregister interfaces
- *          from within the supplied callback function.  */
-PUBLIC IX_STATUS ixAtmmVcChangeCallbackRegister (IxAtmmVcChangeCallback callback);
-
-
-/**    
- * @ingroup IxAtmm
- * 
- * @fn ixAtmmVcChangeCallbackDeregister (IxAtmmVcChangeCallback callback)
- *
- * @brief This interface is invoked to deregister a previously supplied
- *         callback function.
- *
- * @param callback @ref IxAtmmVcChangeCallback [in] - Callback which complies
- *          with the @ref IxAtmmVcChangeCallback definition.  This
- *          function will removed from the table of callbacks.
- *
- * @return @li IX_SUCCESS : The specified callback has been deregistered
- *      successfully from IxAtmm.
- * @return @li IX_FAIL : Either the supplied callback is invalid, or
- *      is not currently registered with IxAtmm.
- */
-PUBLIC IX_STATUS
-ixAtmmVcChangeCallbackDeregister (IxAtmmVcChangeCallback callback);
-
-/**    
- * @ingroup IxAtmm
- * 
- * @fn ixAtmmUtopiaStatusShow (void)
- * 
- *  @brief Display utopia status counters
- *
- * @param "none"
- *
- * @return @li IX_SUCCESS : Show function was successful
- * @return @li IX_FAIL : Internal failure
- */
-PUBLIC IX_STATUS
-ixAtmmUtopiaStatusShow (void);
-
-/**     
- * @ingroup IxAtmm
- * 
- * @fn ixAtmmUtopiaCfgShow (void)
- *
- * @brief Display utopia information(config registers and status registers)
- *
- * @param "none"
- *
- * @return @li IX_SUCCESS : Show function was successful
- * @return @li IX_FAIL : Internal failure
- */
-PUBLIC IX_STATUS
-ixAtmmUtopiaCfgShow (void);
-
-#endif
-/* IXATMM_H */
-
-/** @} */
diff --git a/drivers/net/npe/include/IxDmaAcc.h b/drivers/net/npe/include/IxDmaAcc.h
deleted file mode 100644
index a62e72cc1b..0000000000
--- a/drivers/net/npe/include/IxDmaAcc.h
+++ /dev/null
@@ -1,236 +0,0 @@
-/**
- * @file IxDmaAcc.h
- *
- * @date	15 October 2002 
- *
- * @brief   API of the IXP400 DMA Access Driver Component (IxDma)
- *
- *
- * @par
- * IXP400 SW Release version 2.0
- * 
- * -- Copyright Notice --
- * 
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- * 
- * @par
- * SPDX-License-Identifier:	BSD-3-Clause
- * @par
- * -- End of Copyright Notice --
- */
-
-/*---------------------------------------------------------------------
-   Doxygen group definitions
-  ---------------------------------------------------------------------*/
-
-#ifndef IXDMAACC_H
-#define IXDMAACC_H
-
-#include "IxOsal.h"
-#include "IxNpeDl.h"
-/**
- * @defgroup IxDmaTypes IXP400 DMA Types (IxDmaTypes)
- * @brief The common set of types used in the DMA component
- * @{
- */
-
-/** 
- * @ingroup IxDmaTypes
- * @enum IxDmaReturnStatus
- * @brief Dma return status definitions
- */
-typedef enum
-{
-    IX_DMA_SUCCESS = IX_SUCCESS,  /**< DMA Transfer Success */
-    IX_DMA_FAIL = IX_FAIL,        /**< DMA Transfer Fail */
-    IX_DMA_INVALID_TRANSFER_WIDTH, /**< Invalid transfer width */
-    IX_DMA_INVALID_TRANSFER_LENGTH, /**< Invalid transfer length */
-    IX_DMA_INVALID_TRANSFER_MODE, /**< Invalid transfer mode */
-    IX_DMA_INVALID_ADDRESS_MODE, /**< Invalid address mode */
-    IX_DMA_REQUEST_FIFO_FULL  /**< DMA request queue is full */
-} IxDmaReturnStatus;
-
-/** 
- * @ingroup IxDmaTypes
- * @enum IxDmaTransferMode
- * @brief Dma transfer mode definitions
- * @note Copy and byte swap, and copy and reverse modes only support multiples of word data length.
- */
-typedef enum
-{
-    IX_DMA_COPY_CLEAR = 0,      /**< copy and clear source*/
-    IX_DMA_COPY,                /**< copy */
-    IX_DMA_COPY_BYTE_SWAP,      /**< copy and byte swap (endian) */
-    IX_DMA_COPY_REVERSE,        /**< copy and reverse */
-    IX_DMA_TRANSFER_MODE_INVALID /**< Invalid transfer mode */
-} IxDmaTransferMode;
-
-/** 
- * @ingroup IxDmaTypes
- * @enum IxDmaAddressingMode
- * @brief Dma addressing mode definitions
- * @note Fixed source address to fixed destination address addressing mode is not supported.
- */
-typedef enum
-{
-    IX_DMA_INC_SRC_INC_DST = 0, /**< Incremental source address to incremental destination address */
-    IX_DMA_INC_SRC_FIX_DST,     /**< Incremental source address to incremental destination address */
-    IX_DMA_FIX_SRC_INC_DST,     /**< Incremental source address to incremental destination address */
-    IX_DMA_FIX_SRC_FIX_DST,     /**< Incremental source address to incremental destination address */
-    IX_DMA_ADDRESSING_MODE_INVALID /**< Invalid Addressing Mode */
-} IxDmaAddressingMode;
-
-/** 
- * @ingroup IxDmaTypes
- * @enum IxDmaTransferWidth
- * @brief Dma transfer width definitions
- * @Note Fixed addresses (either source or destination) do not support burst transfer width.
- */
-typedef enum
-{
-    IX_DMA_32_SRC_32_DST = 0,  /**< 32-bit src to 32-bit dst */
-    IX_DMA_32_SRC_16_DST,      /**< 32-bit src to 16-bit dst */
-    IX_DMA_32_SRC_8_DST,       /**< 32-bit src to 8-bit dst */
-    IX_DMA_16_SRC_32_DST,      /**< 16-bit src to 32-bit dst */
-    IX_DMA_16_SRC_16_DST,      /**< 16-bit src to 16-bit dst */
-    IX_DMA_16_SRC_8_DST,       /**< 16-bit src to 8-bit dst */
-    IX_DMA_8_SRC_32_DST,       /**< 8-bit src to 32-bit dst */
-    IX_DMA_8_SRC_16_DST,       /**< 8-bit src to 16-bit dst */
-    IX_DMA_8_SRC_8_DST,        /**< 8-bit src to 8-bit dst */
-    IX_DMA_8_SRC_BURST_DST,    /**< 8-bit src to burst dst - Not supported for fixed destination address */
-    IX_DMA_16_SRC_BURST_DST,   /**< 16-bit src to burst dst - Not supported for fixed destination address */
-    IX_DMA_32_SRC_BURST_DST,   /**< 32-bit src to burst dst - Not supported for fixed destination address */
-    IX_DMA_BURST_SRC_8_DST,    /**< burst src to 8-bit dst  - Not supported for fixed source address */
-    IX_DMA_BURST_SRC_16_DST,   /**< burst src to 16-bit dst - Not supported for fixed source address */
-    IX_DMA_BURST_SRC_32_DST,   /**< burst src to 32-bit dst - Not supported for fixed source address*/
-    IX_DMA_BURST_SRC_BURST_DST, /**< burst src to burst dst  - Not supported for fixed source and destination address
-*/
-    IX_DMA_TRANSFER_WIDTH_INVALID /**< Invalid transfer width */
-} IxDmaTransferWidth;
-
-/** 
- * @ingroup IxDmaTypes
- * @enum IxDmaNpeId
- * @brief NpeId numbers to identify NPE A, B or C
- */
-typedef enum
-{
-    IX_DMA_NPEID_NPEA = 0, /**< Identifies NPE A */
-    IX_DMA_NPEID_NPEB,     /**< Identifies NPE B */
-    IX_DMA_NPEID_NPEC,     /**< Identifies NPE C */
-    IX_DMA_NPEID_MAX       /**< Total Number of NPEs */
-} IxDmaNpeId;
-/* @} */
-/**
- * @defgroup IxDmaAcc IXP400 DMA Access Driver (IxDmaAcc) API
- *
- * @brief The public API for the IXP400 IxDmaAcc component
- *
- * @{
- */
-
-/**
- * @ingroup IxDmaAcc
- * @brief DMA Request Id type
- */
-typedef UINT32 IxDmaAccRequestId;
-
-/**
- * @ingroup IxDmaAcc
- * @def IX_DMA_REQUEST_FULL
- * @brief DMA request queue is full
- * This constant is a return value used to tell the user that the IxDmaAcc
- * queue is full.
- *
- */
-#define IX_DMA_REQUEST_FULL 16
-
-/**
- * @ingroup	IxDmaAcc
- * @brief       DMA completion notification
- * This function is called to notify a client that the DMA has been completed
- * @param status @ref IxDmaReturnStatus [out] - reporting to client
- *
- */
-typedef void (*IxDmaAccDmaCompleteCallback) (IxDmaReturnStatus status);
-
-/**
- * @ingroup	IxDmaAcc
- * 
- * @fn ixDmaAccInit(IxNpeDlNpeId npeId)
- * 
- * @brief	Initialise the DMA Access component
- * This function will initialise the DMA Access component internals
- * @param npeId @ref IxNpeDlNpeId [in] - NPE to use for Dma Transfer
- * @return @li IX_SUCCESS succesfully initialised the component
- * @return @li IX_FAIL Initialisation failed for some unspecified
- * internal reason.
- */
-PUBLIC IX_STATUS
-ixDmaAccInit(IxNpeDlNpeId npeId);
-
-/**
- * @ingroup	IxDmaAcc
- * 
- * @fn ixDmaAccDmaTransfer(
-    IxDmaAccDmaCompleteCallback callback,
-    UINT32 SourceAddr,
-    UINT32 DestinationAddr,
-    UINT16 TransferLength,
-    IxDmaTransferMode TransferMode,
-    IxDmaAddressingMode AddressingMode,
-    IxDmaTransferWidth TransferWidth)
- *
- * @brief       Perform DMA transfer
- * This function will perform DMA transfer between devices within the
- * IXP400 memory map.
- * @note The following are restrictions for IxDmaAccDmaTransfer:
- *      @li The function is non re-entrant.
- *      @li The function assumes host devices are operating in big-endian mode.
- *      @li Fixed address does not suport burst transfer width
- *      @li Fixed source address to fixed destinatiom address mode is not suported
- *      @li The incrementing source address for expansion bus will not support a burst transfer width and copy and clear mode
- *
- * @param callback @ref IxDmaAccDmaCompleteCallback [in] - function pointer to be stored and called when the DMA transfer is completed. This cannot be NULL.
- * @param SourceAddr UINT32 [in] -	Starting address of DMA source. Must be a valid IXP400 memory map address.
- * @param DestinationAddr UINT32 [in] - Starting address of DMA destination. Must be a valid IXP400 memory map address.
- * @param TransferLength UINT16 [in] - The size of DMA data transfer. The range must be from 1-64Kbyte
- * @param TransferMode @ref IxDmaTransferMode [in] - The DMA transfer mode
- * @param AddressingMode @ref IxDmaAddressingMode [in] - The DMA addressing mode
- * @param TransferWidth	@ref IxDmaTransferWidth [in] - The DMA transfer width
- *
- * @return @li IX_DMA_SUCCESS	Notification that the DMA request is succesful
- * @return @li IX_DMA_FAIL	IxDmaAcc not yet initialised or some internal error has occured
- * @return @li IX_DMA_INVALID_TRANSFER_WIDTH Transfer width is nit valid
- * @return @li IX_DMA_INVALID_TRANSFER_LENGTH Transfer length outside of valid range
- * @return @li IX_DMA_INVALID_TRANSFER_MODE Transfer Mode not valid
- * @return @li IX_DMA_REQUEST_FIFO_FULL IxDmaAcc request queue is full
- */
-PUBLIC IxDmaReturnStatus
-ixDmaAccDmaTransfer(
-    IxDmaAccDmaCompleteCallback callback,
-    UINT32 SourceAddr,
-    UINT32 DestinationAddr,
-    UINT16 TransferLength,
-    IxDmaTransferMode TransferMode,
-    IxDmaAddressingMode AddressingMode,
-    IxDmaTransferWidth TransferWidth);
-/**
- * @ingroup IxDmaAcc
- *
- * @fn ixDmaAccShow(void)
- *
- * @brief Display some component information for debug purposes
- * Show some internal operation information relating to the DMA service.
- * At a minimum the following will show.
- * - the number of the DMA pend (in queue)
- * @param None
- * @return @li None
- */
-PUBLIC IX_STATUS
-ixDmaAccShow(void);
-
-#endif /* IXDMAACC_H */
-
diff --git a/drivers/net/npe/include/IxEthAcc.h b/drivers/net/npe/include/IxEthAcc.h
deleted file mode 100644
index cc7e010667..0000000000
--- a/drivers/net/npe/include/IxEthAcc.h
+++ /dev/null
@@ -1,2488 +0,0 @@
-/** @file    IxEthAcc.h
- *
- * @brief this file contains the public API of @ref IxEthAcc component
- *
- * Design notes:
- * The IX_OSAL_MBUF address is to be specified on bits [31-5] and must 
- * be cache aligned (bits[4-0] cleared)
- *
- * 
- * @par
- * IXP400 SW Release version 2.0
- * 
- * -- Copyright Notice --
- * 
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- * 
- * @par
- * SPDX-License-Identifier:	BSD-3-Clause
- * @par
- * -- End of Copyright Notice --
- *
- */
-
-#ifndef IxEthAcc_H
-#define IxEthAcc_H
-
-#include <IxOsBuffMgt.h>
-#include <IxTypes.h>
-
-/**
- * @defgroup IxEthAcc IXP400 Ethernet Access (IxEthAcc) API
- *
- * @brief ethAcc is a library that does provides access to the internal IXP400 10/100Bt Ethernet MACs.
- *
- *@{
- */
-
-/**
- * @ingroup IxEthAcc
- * @brief Definition of the Ethernet Access status
- */
-typedef enum /* IxEthAccStatus */
-{
-    IX_ETH_ACC_SUCCESS = IX_SUCCESS, /**< return success*/
-    IX_ETH_ACC_FAIL = IX_FAIL, /**< return fail*/
-    IX_ETH_ACC_INVALID_PORT, /**< return invalid port*/
-    IX_ETH_ACC_PORT_UNINITIALIZED, /**< return uninitialized*/
-    IX_ETH_ACC_MAC_UNINITIALIZED, /**< return MAC uninitialized*/
-    IX_ETH_ACC_INVALID_ARG, /**< return invalid arg*/
-    IX_ETH_TX_Q_FULL, /**< return tx queue is full*/
-    IX_ETH_ACC_NO_SUCH_ADDR /**< return no such address*/
-} IxEthAccStatus;
-
-/**
- * @ingroup IxEthAcc
- * @enum IxEthAccPortId
- * @brief Definition of the IXP400 Mac Ethernet device.
- */
-typedef enum  
-{
-	IX_ETH_PORT_1 = 0, /**< Ethernet Port 1 */
-	IX_ETH_PORT_2 = 1  /**< Ethernet port 2 */
-	,IX_ETH_PORT_3 = 2 /**< Ethernet port 3 */
-} IxEthAccPortId;
-
-/**
- * @ingroup IxEthAcc
- *
- * @def IX_ETH_ACC_NUMBER_OF_PORTS
- *
- * @brief  Definition of the number of ports
- *
- */
-#ifdef __ixp46X
-#define IX_ETH_ACC_NUMBER_OF_PORTS (3)
-#else
-#define IX_ETH_ACC_NUMBER_OF_PORTS (2)
-#endif
-
-/**
- * @ingroup IxEthAcc
- *
- * @def IX_IEEE803_MAC_ADDRESS_SIZE
- *
- * @brief  Definition of the size of the MAC address
- *
- */
-#define IX_IEEE803_MAC_ADDRESS_SIZE (6)
-
-
-/**
- *
- * @brief Definition of the IEEE 802.3 Ethernet MAC address structure.
- *
- * The data should be packed with bytes xx:xx:xx:xx:xx:xx 
- * @note
- * The data must be packed in network byte order.
- */
-typedef struct  
-{
-    UINT8 macAddress[IX_IEEE803_MAC_ADDRESS_SIZE]; /**< MAC address */
-} IxEthAccMacAddr;
-
-/**
- * @ingroup IxEthAcc
- * @def IX_ETH_ACC_NUM_TX_PRIORITIES
- * @brief Definition of the number of transmit priorities
- * 
- */
-#define IX_ETH_ACC_NUM_TX_PRIORITIES (8)
-
-/**
- * @ingroup IxEthAcc
- * @enum IxEthAccTxPriority
- * @brief Definition of the relative priority used to transmit a frame
- * 
- */
-typedef enum  
-{
-	IX_ETH_ACC_TX_PRIORITY_0 = 0, /**<Lowest Priority submission */
-	IX_ETH_ACC_TX_PRIORITY_1 = 1, /**<submission prority of 1 (0 is lowest)*/
-	IX_ETH_ACC_TX_PRIORITY_2 = 2, /**<submission prority of 2 (0 is lowest)*/
-	IX_ETH_ACC_TX_PRIORITY_3 = 3, /**<submission prority of 3 (0 is lowest)*/
-	IX_ETH_ACC_TX_PRIORITY_4 = 4, /**<submission prority of 4 (0 is lowest)*/
-	IX_ETH_ACC_TX_PRIORITY_5 = 5, /**<submission prority of 5 (0 is lowest)*/
-	IX_ETH_ACC_TX_PRIORITY_6 = 6, /**<submission prority of 6 (0 is lowest)*/
-	IX_ETH_ACC_TX_PRIORITY_7 = 7, /**<Highest priority submission */
-
-	IX_ETH_ACC_TX_DEFAULT_PRIORITY = IX_ETH_ACC_TX_PRIORITY_0 /**< By default send all 
-								 packets with lowest priority */
-} IxEthAccTxPriority;
-
-/**
- * @ingroup IxEthAcc
- * @enum IxEthAccRxFrameType
- * @brief Identify the type of a frame.
- * 
- * @sa IX_ETHACC_NE_FLAGS
- * @sa IX_ETHACC_NE_LINKMASK
- */
-typedef enum  
-{
-	IX_ETHACC_RX_LLCTYPE = 0x00, /**< 802.3 - 8802, with LLC/SNAP */
-	IX_ETHACC_RX_ETHTYPE = 0x10, /**< 802.3 (Ethernet) without LLC/SNAP */
-	IX_ETHACC_RX_STATYPE = 0x20, /**< 802.11, AP <=> STA */
-	IX_ETHACC_RX_APTYPE  = 0x30  /**< 802.11, AP <=> AP */
-} IxEthAccRxFrameType;
-
-/**
- * @ingroup IxEthAcc
- * @enum IxEthAccDuplexMode
- * @brief Definition to provision the duplex mode of the MAC. 
- * 
- */
-typedef enum
-{
-    IX_ETH_ACC_FULL_DUPLEX, /**< Full duplex operation of the MAC */
-    IX_ETH_ACC_HALF_DUPLEX  /**< Half duplex operation of the MAC */
-} IxEthAccDuplexMode;
-
-
-/**
- * @ingroup IxEthAcc
- * @struct IxEthAccNe
- * @brief Definition of service-specific informations.
- * 
- * This structure defines the Ethernet service-specific informations
- * and enable QoS and VLAN features.
- */
-typedef struct
-{
-    UINT32 ixReserved_next;    /**< reserved for chaining */
-    UINT32 ixReserved_lengths; /**< reserved for buffer lengths */
-    UINT32 ixReserved_data;    /**< reserved for buffer pointer */
-    UINT8  ixDestinationPortId; /**< Destination portId for this packet, if known by NPE */
-    UINT8  ixSourcePortId; /**< Source portId for this packet */
-    UINT16 ixFlags;        /**< BitField of option for this frame */
-    UINT8  ixQoS;          /**< QoS class of the frame */
-    UINT8  ixReserved;     /**< reserved */
-    UINT16 ixVlanTCI;      /**< Vlan TCI */
-    UINT8  ixDestMac[IX_IEEE803_MAC_ADDRESS_SIZE]; /**< Destination MAC address */
-    UINT8  ixSourceMac[IX_IEEE803_MAC_ADDRESS_SIZE]; /**< Source MAC address */
-} IxEthAccNe;
-
-/**
- * @ingroup IxEthAcc
- *
- * @def IX_ETHACC_NE_PORT_UNKNOWN
- *
- * @brief  Contents of the field @a IX_ETHACC_NE_DESTPORTID when no
- * destination port can be found by the NPE for this frame.
- *
- */
-#define IX_ETHACC_NE_PORT_UNKNOWN   (0xff)
-
-/**
- * @ingroup IxEthAcc
- *
- * @def IX_ETHACC_NE_DESTMAC
- *
- * @brief The location of the destination MAC address in the Mbuf header.
- *
- */
-#define IX_ETHACC_NE_DESTMAC(mBufPtr) ((IxEthAccNe *)&((mBufPtr)->ix_ne))->ixDestMac
-
-/**
- * @ingroup IxEthAcc
- *
- * @def IX_ETHACC_NE_SOURCEMAC
- *
- * @brief The location of the source MAC address in the Mbuf header.
- *
- */
-#define IX_ETHACC_NE_SOURCEMAC(mBufPtr) ((IxEthAccNe *)&((mBufPtr)->ix_ne))->ixSourceMac
-
-/**
- * @ingroup IxEthAcc
- *
- * @def IX_ETHACC_NE_VLANTCI
- *
- * @brief The VLAN Tag Control Information associated with this frame
- * 
- * The VLAN Tag Control Information associated with this frame. On Rx
- * path, this field is extracted from the packet header.
- * On Tx path, the value of this field is inserted in the frame when
- * the port is configured to insert or replace vlan tags in the 
- * egress frames.
- *
- * @sa IX_ETHACC_NE_FLAGS
- */
-#define IX_ETHACC_NE_VLANTCI(mBufPtr) ((IxEthAccNe *)&((mBufPtr)->ix_ne))->ixVlanTCI
-
-/**
- * @ingroup IxEthAcc
- *
- * @def IX_ETHACC_NE_SOURCEPORTID
- *
- * @brief The port where this frame came from.
- *
- * The port where this frame came from. This field is set on receive
- * with the port information. This field is ignored on Transmit path.
- */
-#define IX_ETHACC_NE_SOURCEPORTID(mBufPtr) ((IxEthAccNe *)&((mBufPtr)->ix_ne))->ixSourcePortId
-
-/**
- * @ingroup IxEthAcc
- *
- * @def IX_ETHACC_NE_DESTPORTID
- *
- * @brief The destination port where this frame should be sent.
- *
- * The destination port where this frame should be sent.
- *
- * @li In the transmit direction, this field contains the destination port
- * and is ignored unless @a IX_ETHACC_NE_FLAG_DST is set.
- * 
- * @li In the receive direction, this field contains the port where the
- * destination MAC addresses has been learned. If the destination
- * MAC address is unknown, then this value is set to the reserved value
- * @a IX_ETHACC_NE_PORT_UNKNOWN
- *
- */
-#define IX_ETHACC_NE_DESTPORTID(mBufPtr) ((IxEthAccNe *)&((mBufPtr)->ix_ne))->ixDestinationPortId
-
-/**
- * @ingroup IxEthAcc
- *
- * @def IX_ETHACC_NE_QOS
- *
- * @brief QualityOfService class (QoS) for this received frame.
- *
- */
-#define IX_ETHACC_NE_QOS(mBufPtr) ((IxEthAccNe *)&((mBufPtr)->ix_ne))->ixQoS
-
-/**
- * @ingroup IxEthAcc
- *
- * @def IX_ETHACC_NE_FLAGS
- *
- * @brief Bit Mask of the different flags associated with a frame
- * 
- * The flags are the bit-oring combination 
- * of the following different fields :
- *
- *      @li IP flag (Rx @a IX_ETHACC_NE_IPMASK)
- *      @li Spanning Tree flag (Rx @a IX_ETHACC_NE_STMASK)
- *      @li Link layer type (Rx and Tx @a IX_ETHACC_NE_LINKMASK)
- *      @li VLAN Tagged Frame (Rx @a IX_ETHACC_NE_VLANMASK)
- *      @li New source MAC address (Rx @a IX_ETHACC_NE_NEWSRCMASK)
- *      @li Multicast flag (Rx @a IX_ETHACC_NE_MCASTMASK)
- *      @li Broadcast flag (Rx @a IX_ETHACC_NE_BCASTMASK)
- *      @li Destination port flag (Tx @a IX_ETHACC_NE_PORTMASK)
- *      @li Tag/Untag Tx frame (Tx @a IX_ETHACC_NE_TAGMODEMASK)
- *      @li Overwrite destination port (Tx @a IX_ETHACC_NE_PORTOVERMASK)
- *      @li Filtered frame (Rx @a IX_ETHACC_NE_STMASK)
- *      @li VLAN Enabled (Rx and Tx @a IX_ETHACC_NE_VLANENABLEMASK)
- */
-#define IX_ETHACC_NE_FLAGS(mBufPtr) ((IxEthAccNe *)&((mBufPtr)->ix_ne))->ixFlags
-
-/**
- * @ingroup IxEthAcc
- *
- * @def IX_ETHACC_NE_BCASTMASK
- *
- * @brief This mask defines if a received frame is a broadcast frame.
- *
- * This mask defines if a received frame is a broadcast frame.
- * The BCAST flag is set when the destination MAC address of 
- * a frame is broadcast.
- *
- * @sa IX_ETHACC_NE_FLAGS 
- *
- */
-#define IX_ETHACC_NE_BCASTMASK      (0x1)
-
-/**
- * @ingroup IxEthAcc
- *
- * @def IX_ETHACC_NE_MCASTMASK
- *
- * @brief This mask defines if a received frame is a multicast frame.
- *
- * This mask defines if a received frame is a multicast frame.
- * The MCAST flag is set when the destination MAC address of 
- * a frame is multicast.
- *
- * @sa IX_ETHACC_NE_FLAGS 
- *
- */
-#define IX_ETHACC_NE_MCASTMASK      (0x1 << 1)
-
-/**
- * @ingroup IxEthAcc
- *
- * @def IX_ETHACC_NE_IPMASK
- *
- * @brief This mask defines if a received frame is a IP frame.
- *
- * This mask applies to @a IX_ETHACC_NE_FLAGS and defines if a received 
- * frame is a IP frame. The IP flag is set on Rx direction, depending on 
- * the frame contents. The flag is set when the length/type field of a 
- * received frame is 0x8000.
- *
- * @sa IX_ETHACC_NE_FLAGS
- *
- */
-#define IX_ETHACC_NE_IPMASK         (0x1 << 2)
-
-/**
- * @ingroup IxEthAcc
- *
- * @def IX_ETHACC_NE_VLANMASK
- *
- * @brief This mask defines if a received frame is VLAN tagged.
- *
- * This mask defines if a received frame is VLAN tagged.
- * When set, the Rx frame is VLAN-tagged and the tag value 
- * is available thru @a IX_ETHACC_NE_VLANID.
- * Note that when sending frames which are already tagged
- * this flag should be set, to avoid inserting another VLAN tag.
- *
- * @sa IX_ETHACC_NE_FLAGS 
- * @sa IX_ETHACC_NE_VLANID
- *
- */
-#define IX_ETHACC_NE_VLANMASK       (0x1 << 3)
-
-/**
- * @ingroup IxEthAcc
- *
- * @def IX_ETHACC_NE_LINKMASK
- *
- * @brief This mask is the link layer protocol indicator
- *
- * This mask applies to @a IX_ETHACC_NE_FLAGS.
- * It reflects the state of a frame as it exits an NPE on the Rx path
- * or enters an NPE on the Tx path. Its values are as follows:
- *      @li 0x00 - IEEE802.3 - 8802 (Rx) / IEEE802.3 - 8802 (Tx)
- *      @li 0x01 - IEEE802.3 - Ethernet (Rx) / IEEE802.3 - Ethernet (Tx)
- *      @li 0x02 - IEEE802.11 AP -> STA (Rx) / IEEE802.11 STA -> AP (Tx)
- *      @li 0x03 - IEEE802.11 AP -> AP (Rx) / IEEE802.11 AP->AP (Tx)
- *
- * @sa IX_ETHACC_NE_FLAGS
- *
- */
-#define IX_ETHACC_NE_LINKMASK       (0x3 << 4)
-
-/**
- * @ingroup IxEthAcc
- *
- * @def IX_ETHACC_NE_STMASK
- *
- * @brief This mask defines if a received frame is a Spanning Tree frame.
- *
- * This mask applies to @a IX_ETHACC_NE_FLAGS.
- * On rx direction, it defines if a received if frame is a Spanning Tree frame.
- * Setting this fkag on transmit direction overrides the port settings 
- * regarding the VLAN options and 
- *
- * @sa IX_ETHACC_NE_FLAGS
- *
- */
-#define IX_ETHACC_NE_STMASK         (0x1 << 6)
-
-/**
- * @ingroup IxEthAcc
- *
- * @def IX_ETHACC_NE_FILTERMASK
- *
- * @brief This bit indicates whether a frame has been filtered by the Rx service.
- *
- * This mask applies to @a IX_ETHACC_NE_FLAGS.
- * Certain frames, which should normally be fully filtered by the NPE to due
- * the destination MAC address being on the same segment as the Rx port are
- * still forwarded to the XScale (although the payload is invalid) in order
- * to learn the MAC address of the transmitting station, if this is unknown.
- * Normally EthAcc will filter and recycle these framess internally and no
- * frames with the FILTER bit set will be received by the client.
- *
- * @sa IX_ETHACC_NE_FLAGS
- *
- */
-#define IX_ETHACC_NE_FILTERMASK     (0x1 << 7)
-
-/**
- * @ingroup IxEthAcc
- *
- * @def IX_ETHACC_NE_PORTMASK
- *
- * @brief This mask defines the rule to transmit a frame
- *
- * This mask defines the rule to transmit a frame. When set, a frame
- * is transmitted to the destination port as set by the macro
- * @a IX_ETHACC_NE_DESTPORTID. If not set, the destination port 
- * is searched using the destination MAC address.
- *
- * @note This flag is meaningful only for multiport Network Engines.
- * 
- * @sa IX_ETHACC_NE_FLAGS 
- * @sa IX_ETHACC_NE_DESTPORTID
- *
- */
-#define IX_ETHACC_NE_PORTOVERMASK   (0x1 << 8)
-
-/**
- * @ingroup IxEthAcc
- *
- * @def IX_ETHACC_NE_TAGMODEMASK
- *
- * @brief This mask defines the tagging rules to apply to a transmit frame.
- *
- * This mask defines the tagging rules to apply to a transmit frame
- * regardless of the default setting for a port. When used together 
- * with @a IX_ETHACC_NE_TAGOVERMASK and when set, the 
- * frame will be tagged prior to transmission. When not set,
- * the frame will be untagged prior to transmission. This is accomplished
- * irrespective of the Egress tagging rules, constituting a per-frame override.
- *
- * @sa IX_ETHACC_NE_FLAGS
- * @sa IX_ETHACC_NE_TAGOVERMASK 
- *
- */
-#define IX_ETHACC_NE_TAGMODEMASK    (0x1 << 9)
-
-/**
- * @ingroup IxEthAcc
- *
- * @def IX_ETHACC_NE_TAGOVERMASK
- *
- * @brief This mask defines the rule to transmit a frame
- *
- * This mask defines the rule to transmit a frame. When set, the
- * default transmit rules of a port are overriden.
- * When not set, the default rules as set by @ref IxEthDB should apply.
- *
- * @sa IX_ETHACC_NE_FLAGS
- * @sa IX_ETHACC_NE_TAGMODEMASK
- *
- */
-#define IX_ETHACC_NE_TAGOVERMASK    (0x1 << 10)
-
-/**
- * @ingroup IxEthAcc
- *
- * @def IX_ETHACC_NE_VLANENABLEMASK
- *
- * @brief This mask defines if a frame is a VLAN frame or not
- *
- * When set, frames undergo normal VLAN processing on the Tx path
- * (membership filtering, tagging, tag removal etc). If this flag is
- * not set, the frame is considered to be a regular non-VLAN frame
- * and no VLAN processing will be performed.
- *
- * Note that VLAN-enabled NPE images will always set this flag in all
- * Rx frames, and images which are not VLAN enabled will clear this
- * flag for all received frames.
- *
- * @sa IX_ETHACC_NE_FLAGS
- *
- */
-#define IX_ETHACC_NE_VLANENABLEMASK (0x1 << 14)
-
-/**
- * @ingroup IxEthAcc
- *
- * @def IX_ETHACC_NE_NEWSRCMASK
- *
- * @brief This mask defines if a received frame has been learned.
- *
- * This mask defines if the source MAC address of a frame is 
- * already known. If the bit is set, the source MAC address was
- * unknown to the NPE at the time the frame was received.
- *
- * @sa IX_ETHACC_NE_FLAGS 
- *
- */
-#define IX_ETHACC_NE_NEWSRCMASK     (0x1 << 15)
-
-/**
- * @ingroup IxEthAcc
- *
- * @brief This defines the recommanded minimum size of MBUF's submitted
- * to the frame receive service.
- *
- */
-#define IX_ETHACC_RX_MBUF_MIN_SIZE (2048)
-
-/**
- * @ingroup IxEthAcc
- *
- * @brief This defines the highest MII address of any attached PHYs 
- * 
- * The maximum number for PHY address is 31, add on for range checking.
- *
- */
-#define IXP425_ETH_ACC_MII_MAX_ADDR   32
-
-/**
- * @ingroup IxEthAcc
- *
- * @fn ixEthAccInit(void)
- * 
- * @brief Initializes the IXP400 Ethernet Access Service.
- * 
- * @li Reentrant    - no
- * @li ISR Callable - no
- * 
- * This should be called once per module initialization.
- * @pre
- *   The NPE must first be downloaded with the required microcode which supports all
- *   required features.
- *
- * @return IxEthAccStatus
- * @li @a IX_ETH_ACC_SUCCESS
- * @li @a IX_ETH_ACC_FAIL	:  Service has failed to initialize.
- *
- * <hr>
- */
-PUBLIC IxEthAccStatus ixEthAccInit(void);
-
-
-/**
- * @ingroup IxEthAcc
- *
- * @fn ixEthAccUnload(void)
- * 
- * @brief Unload the Ethernet Access Service.
- * 
- * @li Reentrant    - no
- * @li ISR Callable - no
- *
- * @return void 
- *
- * <hr>
- */
-PUBLIC void ixEthAccUnload(void);
-
-/**
- * @ingroup IxEthAcc
- *
- * @fn ixEthAccPortInit( IxEthAccPortId portId)
- *
- * @brief Initializes an NPE/Ethernet MAC Port.
- *
- * The NPE/Ethernet port initialisation includes the following steps
- * @li Initialize the NPE/Ethernet MAC hardware.
- * @li Verify NPE downloaded and operational.
- * @li The NPE shall be available for usage once this API returns.
- * @li Verify that the Ethernet port is present before initializing
- *
- * @li Reentrant    - no
- * @li ISR Callable - no
- *
- * This should be called once per mac device.
- * The NPE/MAC shall be in disabled state after init.
- *
- * @pre
- *   The component must be initialized via @a ixEthAccInit
- *   The NPE must first be downloaded with the required microcode which supports all
- *   required features.
- *
- * Dependant on Services: (Must be initialized before using this service may be initialized)
- *	ixNPEmh - NPE Message handling service.
- *	ixQmgr	- Queue Manager component.
- *
- * @param portId  @ref IxEthAccPortId [in]
- *
- * @return IxEthAccStatus
- * @li @a IX_ETH_ACC_SUCCESS: if the ethernet port is not present, a warning is issued.
- * @li @a IX_ETH_ACC_FAIL : The NPE processor has failed to initialize.
- * @li @a IX_ETH_ACC_INVALID_PORT : portId is invalid.
- *
- * <hr>
- */
-PUBLIC IxEthAccStatus ixEthAccPortInit(IxEthAccPortId portId);
-
-
-/*************************************************************************
-
- #####     ##     #####    ##            #####     ##     #####  #    #
- #    #   #  #      #     #  #           #    #   #  #      #    #    #
- #    #  #    #     #    #    #          #    #  #    #     #    ######
- #    #  ######     #    ######          #####   ######     #    #    #
- #    #  #    #     #    #    #          #       #    #     #    #    #
- #####   #    #     #    #    #          #       #    #     #    #    #
-
-*************************************************************************/
-
-
-/**
- * @ingroup IxEthAcc
- *
- * @fn ixEthAccPortTxFrameSubmit( 
-    IxEthAccPortId portId,
-    IX_OSAL_MBUF *buffer, 
-    IxEthAccTxPriority priority)
- * 
- * @brief This function shall be used to submit MBUFs buffers for transmission on a particular MAC device. 
- *
- * When the frame is transmitted, the buffer shall be returned thru the 
- * callback @a IxEthAccPortTxDoneCallback.
- *
- * In case of over-submitting, the order of the frames on the 
- * network may be modified.
- *
- * Buffers shall be not queued for transmission if the port is disabled.
- * The port can be enabled using @a ixEthAccPortEnable
- *
- * 
- * @li Reentrant    - yes
- * @li ISR Callable - yes
- *
- *
- * @pre 
- *  @a ixEthAccPortTxDoneCallbackRegister must be called to register a function to allow this service to
- *   return the buffer to the calling service. 
- * 
- * @note 
- *  If the buffer submit fails for any reason the user has retained ownership of the buffer.
- *
- * @param portId @ref IxEthAccPortId [in] - MAC port ID to transmit Ethernet frame on.
- * @param buffer @ref IX_OSAL_MBUF [in] - pointer to an MBUF formatted buffer. Chained buffers are supported for transmission.
- *             Chained packets are not supported and the field IX_OSAL_MBUF_NEXT_PKT_IN_CHAIN_PTR is ignored. 
- * @param priority @ref IxEthAccTxPriority [in]
- *
- * @return IxEthAccStatus
- * @li @a IX_ETH_ACC_SUCCESS
- * @li @a IX_ETH_ACC_FAIL  : Failed to queue frame for transmission. 
- * @li @a IX_ETH_ACC_INVALID_PORT : portId is invalid.
- * @li @a IX_ETH_ACC_PORT_UNINITIALIZED : portId is un-initialized
- *
- * <hr>
- */
-
-PUBLIC IxEthAccStatus ixEthAccPortTxFrameSubmit( 
-    IxEthAccPortId portId,
-    IX_OSAL_MBUF *buffer, 
-    IxEthAccTxPriority priority);
-
-/**
- * @ingroup IxEthAcc
- *
- * @brief Function prototype for Ethernet Tx Buffer Done callback. Registered 
- *  via @a ixEthAccTxBufferDoneCallbackRegister 
- * 
- * This function is called once the previously submitted buffer is no longer required by this service.
- * It may be returned upon successful transmission of the frame or during the shutdown of 
- * the port prior to the transmission of a queued frame.
- * The calling of this registered function is not a guarantee of successful transmission of the buffer.
- *
- *  
- * @li Reentrant    - yes , The user provided function should be reentrant.
- * @li ISR Callable - yes , The user provided function must be callable from an ISR.
- *
- *
- * <b>Calling Context </b>: 
- * @par
- *   This callback is called in the context of the queue manager dispatch loop @a ixQmgrgrDispatcherLoopRun
- *   within the @ref IxQMgrAPI component. The calling context may be from interrupt or high priority thread. 
- *   The decision is system specific.
- *
- * @param callbackTag UINT32 [in] - This tag is that provided when the callback was registered for a particular MAC 
- * via @a ixEthAccPortTxDoneCallbackRegister. It allows the same callback to be used for multiple MACs.
- * @param mbuf @ref IX_OSAL_MBUF [in] - Pointer to the Tx mbuf descriptor. 
- * 
- * @return void
- *
- * @note
- * The field IX_OSAL_MBUF_NEXT_PKT_IN_CHAIN_PTR is modified by the access layer and reset to NULL.
- *
- * <hr>
- */
-typedef void (*IxEthAccPortTxDoneCallback) ( UINT32 callbackTag, IX_OSAL_MBUF *buffer );
-
-
-
-/**
- * @ingroup IxEthAcc
- *
- * @fn ixEthAccPortTxDoneCallbackRegister( IxEthAccPortId portId, 
-					   IxEthAccPortTxDoneCallback txCallbackFn, 
-					   UINT32 callbackTag)
- *
- * @brief Register a callback function to allow 
- * the transmitted buffers to return to the user.
- * 
- * This function registers the transmit buffer done function callback for a particular port.
- *
- * The registered callback function is called once the previously submitted buffer is no longer required by this service.
- * It may be returned upon successful transmission of the frame or  shutdown of port prior to submission.
- * The calling of this registered function is not a guarantee of successful transmission of the buffer.
- *
- * If called several times the latest callback shall be registered for a particular port.
- *
- * @li Reentrant    - yes
- * @li ISR Callable - yes
- *
- * @pre
- *	The port must be initialized via @a ixEthAccPortInit
- *
- *
- * @param portId @ref IxEthAccPortId [in] - Register callback for a particular MAC device.
- * @param txCallbackFn @ref IxEthAccPortTxDoneCallback [in] - Function to be called to return transmit buffers to the user.
- * @param callbackTag UINT32 [in] -  This tag shall be provided to the callback function.
- *
- * @return IxEthAccStatus
- * @li @a IX_ETH_ACC_SUCCESS 
- * @li @a IX_ETH_ACC_INVALID_PORT : portId is invalid.
- * @li @a IX_ETH_ACC_PORT_UNINITIALIZED : portId is un-initialized
- * @li @a IX_ETH_ACC_INVALID_ARG : An argument other than portId is invalid.
- *
- * <hr>
- */
-PUBLIC IxEthAccStatus
-ixEthAccPortTxDoneCallbackRegister(IxEthAccPortId portId,
-								   IxEthAccPortTxDoneCallback txCallbackFn,
-								   UINT32 callbackTag);
-
-
-
-/**
- * @ingroup IxEthAcc
- *
- * @brief Function prototype for Ethernet Frame Rx callback. Registered via @a ixEthAccPortRxCallbackRegister 
- * 
- * It is the responsibility of the user function to free any MBUF's which it receives.
- *  
- * @li Reentrant    - yes , The user provided function should be reentrant.
- * @li ISR Callable - yes , The user provided function must be callable from an ISR.
- * @par
- *
- * This function dispatches frames to the user level
- * via the provided function. The invocation shall be made for each
- * frame dequeued from the Ethernet QM queue. The user is required to free any MBUF's 
- * supplied via this callback. In addition the registered callback must free up MBUF's
- * from the receive free queue when the port is disabled 
- * 
- * If called several times the latest callback shall be registered for a particular port.
- *
- * <b>Calling Context </b>: 
- * @par
- *   This callback is called in the context of the queue manager dispatch loop @a ixQmgrgrDispatcherLoopRun
- *   within the @ref IxQMgrAPI component. The calling context may be from interrupt or high priority thread. 
- *   The decision is system specific.
- *
- *
- * @param callbackTag UINT32 [in] - This tag is that provided when the callback was registered for a particular MAC 
- * via @a ixEthAccPortRxCallbackRegister. It allows the same callback to be used for multiple MACs.
- * @param mbuf @ref IX_OSAL_MBUF [in] - Pointer to the Rx mbuf header. Mbufs may be chained if 
- *               the frame length is greater than the supplied mbuf length.
- * @param reserved [in] - deprecated parameter The information is passed 
- *      thru the IxEthAccNe header destination port ID field 
- *      (@sa IX_ETHACC_NE_DESTPORTID). For backward 
- *      compatibility,the value is equal to IX_ETH_DB_UNKNOWN_PORT (0xff). 
- * 
- * @return void
- *
- * @note
- * Buffers may not be filled up to the length supplied in 
- * @a ixEthAccPortRxFreeReplenish(). The firmware fills
- * them to the previous 64 bytes boundary. The user has to be aware 
- * that the length of the received mbufs may be smaller than the length
- * of the supplied mbufs. 
- * The mbuf header contains the following modified field
- * @li @a IX_OSAL_MBUF_PKT_LEN is set in the header of the first mbuf and indicates
- *  the total frame size
- * @li @a IX_OSAL_MBUF_MLEN is set each mbuf header and indicates the payload length
- * @li @a IX_OSAL_MBUF_NEXT_BUFFER_IN_PKT_PTR contains a pointer to the next 
- *     mbuf, or NULL at the end of a chain.
- * @li @a IX_OSAL_MBUF_NEXT_PKT_IN_CHAIN_PTR is modified. Its value is reset to NULL
- * @li @a IX_OSAL_MBUF_FLAGS contains the bit 4 set for a broadcast packet and the bit 5
- *     set for a multicast packet. Other bits are unmodified.
- *
- * <hr>
- */
-typedef void (*IxEthAccPortRxCallback) (UINT32 callbackTag, IX_OSAL_MBUF *buffer, UINT32 reserved);
-
-/**
- * @ingroup IxEthAcc
- *
- * @brief Function prototype for Ethernet Frame Rx callback. Registered via @a ixEthAccPortMultiBufferRxCallbackRegister 
- * 
- * It is the responsibility of the user function to free any MBUF's which it receives.
- *  
- * @li Reentrant    - yes , The user provided function should be reentrant.
- * @li ISR Callable - yes , The user provided function must be callable from an ISR.
- * @par
- *
- * This function dispatches many frames to the user level
- * via the provided function. The invocation shall be made for multiple frames
- * dequeued from the Ethernet QM queue. The user is required to free any MBUF's 
- * supplied via this callback. In addition the registered callback must free up MBUF's
- * from the receive free queue when the port is disabled 
- * 
- * If called several times the latest callback shall be registered for a particular port.
- *
- * <b>Calling Context </b>: 
- * @par
- *   This callback is called in the context of the queue manager dispatch loop @a ixQmgrDispatcherLoopRun
- *   within the @ref IxQMgrAPI component. The calling context may be from interrupt or high priority thread. 
- *   The decision is system specific.
- *
- *
- * @param callbackTag - This tag is that provided when the callback was registered for a particular MAC 
- * via @a ixEthAccPortMultiBufferRxCallbackRegister. It allows the same callback to be used for multiple MACs.
- * @param mbuf - Pointer to an array of Rx mbuf headers. Mbufs 
- *               may be chained if 
- *               the frame length is greater than the supplied mbuf length.
- *               The end of the array contains a zeroed entry (NULL pointer).
- *
- * @return void
- *
- * @note The mbufs passed to this callback have the same structure than the
- *  buffers passed to @a IxEthAccPortRxCallback interfac. 
- *
- * @note The usage of this callback is exclusive with the usage of
- *  @a ixEthAccPortRxCallbackRegister and @a IxEthAccPortRxCallback 
- *
- * @sa ixEthAccPortMultiBufferRxCallbackRegister
- * @sa IxEthAccPortMultiBufferRxCallback
- * @sa ixEthAccPortRxCallbackRegister
- * @sa IxEthAccPortRxCallback
- * <hr>
- */
-
-typedef void (*IxEthAccPortMultiBufferRxCallback) (UINT32 callbackTag, IX_OSAL_MBUF **buffer);
-
-
-
-
-/**
- * @ingroup IxEthAcc
- *
- * @fn ixEthAccPortRxCallbackRegister( IxEthAccPortId portId, IxEthAccPortRxCallback rxCallbackFn, UINT32 callbackTag)
- *
- * @brief Register a callback function to allow 
- * the reception of frames.
- *
- * The registered callback function is called once a frame is received  by this service.
- *
- * If called several times the latest callback shall be registered for a particular port.
- *
- *
- * @li Reentrant    - yes
- * @li ISR Callable - yes
- *
- *
- * @param portId @ref IxEthAccPortId [in] - Register callback for a particular MAC device.
- * @param rxCallbackFn @ref IxEthAccPortRxCallback [in] - Function to be called when Ethernet frames are availble.
- * @param callbackTag UINT32 [in] -  This tag shall be provided to the callback function.
- *
- * @return IxEthAccStatus
- * @li @a IX_ETH_ACC_SUCCESS 
- * @li @a IX_ETH_ACC_INVALID_PORT : portId is invalid.
- * @li @a IX_ETH_ACC_PORT_UNINITIALIZED : portId is un-initialized
- * @li @a IX_ETH_ACC_INVALID_ARG : An argument other than portId is invalid.
- *
- * <hr>
- */
-PUBLIC IxEthAccStatus
-ixEthAccPortRxCallbackRegister(IxEthAccPortId portId,
-							   IxEthAccPortRxCallback rxCallbackFn,
-							   UINT32 callbackTag);
-
-
-/**
- * @ingroup IxEthAcc
- *
- * @fn ixEthAccPortMultiBufferRxCallbackRegister( IxEthAccPortId portId, IxEthAccPortMultiBufferRxCallback rxCallbackFn, UINT32 callbackTag)
- *
- * @brief Register a callback function to allow 
- * the reception of frames.
- * 
- * The registered callback function is called once a frame is 
- * received  by this service. If many frames are already received, 
- * the function is called once.
- *
- * If called several times the latest callback shall be registered for a particular port.
- *
- * @li Reentrant    - yes
- * @li ISR Callable - yes
- *
- *
- * @param portId - Register callback for a particular MAC device.
- * @param rxCallbackFn - @a IxEthAccMultiBufferRxCallbackFn - Function to be called when Ethernet frames are availble.
- * @param callbackTag -  This tag shall be provided to the callback function.
- *
- * @return IxEthAccStatus
- * @li @a IX_ETH_ACC_SUCCESS 
- * @li @a IX_ETH_ACC_INVALID_PORT : portId is invalid.
- * @li @a IX_ETH_ACC_PORT_UNINITIALIZED : portId is un-initialized
- * @li @a IX_ETH_ACC_INVALID_ARG : An argument other than portId is invalid.
- *
- * @sa ixEthAccPortMultiBufferRxCallbackRegister
- * @sa IxEthAccPortMultiBufferRxCallback
- * @sa ixEthAccPortRxCallbackRegister
- * @sa IxEthAccPortRxCallback
- * <hr>
- */
-PUBLIC IxEthAccStatus
-ixEthAccPortMultiBufferRxCallbackRegister(IxEthAccPortId portId,
-										  IxEthAccPortMultiBufferRxCallback rxCallbackFn,
-										  UINT32 callbackTag);
-
-/**
- * @ingroup IxEthAcc
- *
- * @fn ixEthAccPortRxFreeReplenish( IxEthAccPortId portId, IX_OSAL_MBUF *buffer)
- *
- * @brief This function provides buffers for the Ethernet receive path. 
- *
- * This component does not have a buffer management mechanisms built in. All Rx buffers must be supplied to it
- * via this interface. 
- *
- * @li Reentrant    - yes
- * @li ISR Callable - yes
- *
- * @param portId @ref IxEthAccPortId [in] - Provide buffers only to specific Rx MAC. 
- * @param buffer @ref IX_OSAL_MBUF [in] - Provide an MBUF to the Ethernet receive mechanism. 
- *                 Buffers size smaller than IX_ETHACC_RX_MBUF_MIN_SIZE may result in poor
- *                 performances and excessive buffer chaining. Buffers
- *                 larger than this size may be suitable for jumbo frames.
- *                 Chained packets are not supported and the field IX_OSAL_MBUF_NEXT_PKT_IN_CHAIN_PTR must be NULL. 
- *
- * @return IxEthAccStatus
- * @li @a IX_ETH_ACC_SUCCESS
- * @li @a IX_ETH_ACC_FAIL : Buffer has was not able to queue the 
- *                     buffer in the receive service.
- * @li @a IX_ETH_ACC_FAIL : Buffer size is less than IX_ETHACC_RX_MBUF_MIN_SIZE
- * @li @a IX_ETH_ACC_INVALID_PORT : portId is invalid.
- * @li @a IX_ETH_ACC_PORT_UNINITIALIZED : portId is un-initialized
- *
- * @note
- * If the buffer replenish operation fails it is the responsibility 
- * of the user to free the buffer.
- *
- * @note
- * Sufficient buffers must be supplied to the component to maintain
- * receive throughput and avoid rx buffer underflow conditions.
- * To meet this goal, It is expected that the user preload the 
- * component with a sufficent number of buffers prior to enabling the
- * NPE Ethernet receive path. The recommended minimum number of 
- * buffers is 8.
- *
- * @note
- * For maximum performances, the mbuf size should be greater 
- * than the maximum frame size (Ethernet header, payload and FCS) + 64. 
- * Supplying smaller mbufs to the service results in mbuf
- * chaining and degraded performances. The recommended size
- * is @a IX_ETHACC_RX_MBUF_MIN_SIZE, which is
- * enough to take care of 802.3 frames and "baby jumbo" frames without
- * chaining, and "jumbo" frame within chaining.
- *
- * @note
- * Buffers may not be filled up to their length. The firware fills
- * them up to the previous 64 bytes boundary. The user has to be aware 
- * that the length of the received mbufs may be smaller than the length
- * of the supplied mbufs.
- *
- * @warning This function checks the parameters if the NDEBUG 
- * flag is not defined. Turning on the argument checking (disabled by 
- * default) results in a lower EthAcc performance as this function
- * is part of the data path.
- *
- * <hr>
- */
-PUBLIC IxEthAccStatus
-ixEthAccPortRxFreeReplenish( IxEthAccPortId portId, IX_OSAL_MBUF *buffer);
-
-
-
-/***************************************************************
-
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-  ####    ####   #    #     #    #    #   ####   ######
-
-
-         #####   #         ##    #    #  ######
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-         #    #  #       #    #  # #  #  #####
-         #####   #       ######  #  # #  #
-         #       #       #    #  #   ##  #
-         #       ######  #    #  #    #  ######
-
-***************************************************************/
-
-/**
- * @ingroup IxEthAcc
- *
- * @fn ixEthAccPortEnable(IxEthAccPortId portId)
- *
- * @brief This enables an Ethernet port for both Tx and Rx. 
- *
- * @li Reentrant    - yes
- * @li ISR Callable - no
- *
- * @pre The port must first be initialized via @a ixEthAccPortInit and the MAC address 
- * must be set using @a ixEthAccUnicastMacAddressSet before enabling it
- * The rx and Tx Done callbacks registration via @a
- * ixEthAccPortTxDoneCallbackRegister amd @a  ixEthAccPortRxCallbackRegister
- * has to be done before enabling the traffic.
- * 
- * @param  portId @ref IxEthAccPortId [in] - Port id to act upon.
- * 
- * @return IxEthAccStatus
- * @li @a IX_ETH_ACC_SUCCESS 
- * @li @a IX_ETH_ACC_INVALID_PORT : portId is invalid.
- * @li @a IX_ETH_ACC_PORT_UNINITIALIZED : portId is not initialized
- * @li @a IX_ETH_ACC_MAC_UNINITIALIZED : port MAC address is not initialized
- *
- * <hr>
- */
-PUBLIC IxEthAccStatus ixEthAccPortEnable(IxEthAccPortId portId);
-
-/**
- * @ingroup IxEthAcc
- *
- * @fn ixEthAccPortDisable(IxEthAccPortId portId)
- *
- * @brief This disables an Ethernet port for both Tx and Rx. 
- *
- * Free MBufs are returned to the user via the registered callback when the port is disabled 
- *
- * @li Reentrant    - yes
- * @li ISR Callable - no
- *
- * @pre The port must be enabled with @a ixEthAccPortEnable, otherwise this
- * function has no effect
- *
- * @param  portId @ref IxEthAccPortId [in] - Port id to act upon.
- * 
- * @return IxEthAccStatus
- * @li @a IX_ETH_ACC_SUCCESS 
- * @li @a IX_ETH_ACC_INVALID_PORT : portId is invalid.
- * @li @a IX_ETH_ACC_PORT_UNINITIALIZED : portId is not initialized
- * @li @a IX_ETH_ACC_MAC_UNINITIALIZED : port MAC address is not initialized
- *
- * <hr>
- */
-PUBLIC IxEthAccStatus ixEthAccPortDisable(IxEthAccPortId portId);
-
-/**
- * @ingroup IxEthAcc
- *
- * @fn ixEthAccPortEnabledQuery(IxEthAccPortId portId, BOOL *enabled)
- *
- * @brief Get the enabled state of a port.
- *
- * @li Reentrant    - yes
- * @li ISR Callable - yes
- *
- * @pre The port must first be initialized via @a ixEthAccPortInit
- *
- * @param  portId @ref IxEthAccPortId [in] - Port id to act upon.
- * @param  enabled BOOL [out] - location to store the state of the port
- *
- * @return IxEthAccStatus
- * @li @a IX_ETH_ACC_SUCCESS
- * @li @a IX_ETH_ACC_INVALID_PORT : portId is invalid
- *
- * <hr>
- */
-PUBLIC IxEthAccStatus
-ixEthAccPortEnabledQuery(IxEthAccPortId portId, BOOL *enabled);
-
-/**
- * @ingroup IxEthAcc
- *
- * @fn ixEthAccPortPromiscuousModeClear(IxEthAccPortId portId)
- *
- * @brief Put the Ethernet MAC device in non-promiscuous mode.
- * 
- * In non-promiscuous mode the MAC filters all frames other than 
- * destination MAC address which matches the following criteria:
- * @li Unicast address provisioned via @a ixEthAccUnicastMacAddressSet
- * @li All broadcast frames.
- * @li Multicast addresses provisioned via @a ixEthAccMulticastAddressJoin
- *
- * Other functions modify the MAC filtering
- *
- * @li @a ixEthAccPortMulticastAddressJoinAll() - all multicast
- *     frames are forwarded to the application
- * @li @a ixEthAccPortMulticastAddressLeaveAll() - rollback the
- *     effects of @a ixEthAccPortMulticastAddressJoinAll()
- * @li @a ixEthAccPortMulticastAddressLeave() - unprovision a new 
- *     filtering address
- * @li @a ixEthAccPortMulticastAddressJoin() - provision a new 
- *     filtering address
- * @li @a ixEthAccPortPromiscuousModeSet() - all frames are 
- *     forwarded to the application regardless of the multicast 
- *     address provisioned
- * @li @a ixEthAccPortPromiscuousModeClear() - frames are forwarded 
- *     to the application following the multicast address provisioned
- *
- * In all cases, unicast and broadcast addresses are forwarded to 
- * the application.
- *
- * @li Reentrant    - yes
- * @li ISR Callable - no
- * 
- * @sa ixEthAccPortPromiscuousModeSet
- * 
- * @param portId @ref IxEthAccPortId [in] - Ethernet port id.
- * 
- * @return IxEthAccStatus 
- * @li @a IX_ETH_ACC_SUCCESS
- * @li @a IX_ETH_ACC_INVALID_PORT : portId is invalid.
- * @li @a IX_ETH_ACC_PORT_UNINITIALIZED : portId is un-initialized
- *
- * <hr>
- */
-PUBLIC IxEthAccStatus ixEthAccPortPromiscuousModeClear(IxEthAccPortId portId);
-
-
-/**
- * @ingroup IxEthAcc
- *
- * @fn  ixEthAccPortPromiscuousModeSet(IxEthAccPortId portId)
- *
- * @brief Put the MAC device in promiscuous mode.
- * 
- * If the device is in promiscuous mode then all all received frames shall be forwared
- * to the NPE for processing.
- *
- * Other functions modify the MAC filtering
- *
- * @li @a ixEthAccPortMulticastAddressJoinAll() - all multicast
- *     frames are forwarded to the application
- * @li @a ixEthAccPortMulticastAddressLeaveAll() - rollback the
- *     effects of @a ixEthAccPortMulticastAddressJoinAll()
- * @li @a ixEthAccPortMulticastAddressLeave() - unprovision a new 
- *     filtering address
- * @li @a ixEthAccPortMulticastAddressJoin() - provision a new 
- *     filtering address
- * @li @a ixEthAccPortPromiscuousModeSet() - all frames are 
- *     forwarded to the application regardless of the multicast 
- *     address provisioned
- * @li @a ixEthAccPortPromiscuousModeClear() - frames are forwarded 
- *     to the application following the multicast address provisioned
- *
- * In all cases, unicast and broadcast addresses are forwarded to 
- * the application.
- *
- * @li Reentrant    - yes
- * @li ISR Callable - no
- * 
- * @sa ixEthAccPortPromiscuousModeClear
- *
- * @param portId @ref IxEthAccPortId [in] - Ethernet port id.
- * 
- * @return IxEthAccStatus 
- * @li @a IX_ETH_ACC_SUCCESS
- * @li @a IX_ETH_ACC_INVALID_PORT : portId is invalid.
- * @li @a IX_ETH_ACC_PORT_UNINITIALIZED : portId is un-initialized
- *
- * <hr>
- */
-PUBLIC IxEthAccStatus ixEthAccPortPromiscuousModeSet(IxEthAccPortId portId);
-
-/**
- * @ingroup IxEthAcc
- *
- * @fn ixEthAccPortUnicastMacAddressSet(      IxEthAccPortId portId,
-                                                  IxEthAccMacAddr *macAddr)
- *
- * @brief Configure unicast MAC address for a particular port
- *
- *
- * @li Reentrant    - yes
- * @li ISR Callable - no
- *
- * @param portId @ref IxEthAccPortId [in] - Ethernet port id.
- * @param *macAddr @ref IxEthAccMacAddr [in] - Ethernet Mac address.
- *
- * @return IxEthAccStatus 
- * @li @a IX_ETH_ACC_SUCCESS
- * @li @a IX_ETH_ACC_INVALID_PORT : portId is invalid.
- * @li @a IX_ETH_ACC_PORT_UNINITIALIZED : portId is un-initialized
- *
- * <hr>
- */
-PUBLIC IxEthAccStatus ixEthAccPortUnicastMacAddressSet(IxEthAccPortId portId,
-													   IxEthAccMacAddr *macAddr);
-
-/**
- * @ingroup IxEthAcc
- *
- * @fn ixEthAccPortUnicastMacAddressGet(	IxEthAccPortId portId, 
-					IxEthAccMacAddr *macAddr)
- *
- * @brief Get unicast MAC address for a particular MAC port 
- *
- * @pre
- * The MAC address must first be set via @a ixEthAccMacPromiscuousModeSet
- * If the MAC address has not been set, the function returns a 
- * IX_ETH_ACC_MAC_UNINITIALIZED status
- *
- * @li Reentrant    - yes
- * @li ISR Callable - no
- *
- * @param portId @ref IxEthAccPortId [in] - Ethernet port id.
- * @param *macAddr @ref IxEthAccMacAddr [out] - Ethernet MAC address.
- *
- * @return  IxEthAccStatus
- * @li @a IX_ETH_ACC_SUCCESS
- * @li @a IX_ETH_ACC_INVALID_PORT : portId is invalid.
- * @li @a IX_ETH_ACC_MAC_UNINITIALIZED : port MAC address is not initialized.
- * @li @a IX_ETH_ACC_FAIL : macAddr is invalid.
- *
- * <hr>
- */
-PUBLIC IxEthAccStatus
-ixEthAccPortUnicastMacAddressGet(IxEthAccPortId portId,
-								 IxEthAccMacAddr *macAddr);
-
-
-
-
-/**
- * @ingroup IxEthAcc
- *
- * @fn ixEthAccPortMulticastAddressJoin(      IxEthAccPortId portId,
-                                             IxEthAccMacAddr *macAddr)
- *
- * @brief Add a multicast address to the MAC address table.
- *
- *  @note
- *  Due to the operation of the Ethernet MAC multicast filtering mechanism, frames which do not 
- *  have a multicast destination address which were provisioned via this API may be forwarded 
- *  to the NPE's. This is a result of the hardware comparison  algorithm used in the destination mac address logic
- *  within the Ethernet MAC. 
- *
- *  See Also: IXP425 hardware development manual.
- * 
- * Other functions modify the MAC filtering
- *
- * @li @a ixEthAccPortMulticastAddressJoinAll() - all multicast
- *     frames are forwarded to the application
- * @li @a ixEthAccPortMulticastAddressLeaveAll() - rollback the
- *     effects of @a ixEthAccPortMulticastAddressJoinAll()
- * @li @a ixEthAccPortMulticastAddressLeave() - unprovision a new 
- *     filtering address
- * @li @a ixEthAccPortMulticastAddressJoin() - provision a new 
- *     filtering address
- * @li @a ixEthAccPortPromiscuousModeSet() - all frames are 
- *     forwarded to the application regardless of the multicast 
- *     address provisioned
- * @li @a ixEthAccPortPromiscuousModeClear() - frames are forwarded 
- *     to the application following the multicast address provisioned
- *
- * In all cases, unicast and broadcast addresses are forwarded to 
- * the application.
- *
- * @li Reentrant    - yes
- * @li ISR Callable - no
- *
- * @param portId @ref IxEthAccPortId [in] - Ethernet port id.
- * @param *macAddr @ref IxEthAccMacAddr [in] - Ethernet Mac address.
- *
- * @return IxEthAccStatus 
- * @li @a IX_ETH_ACC_SUCCESS
- * @li @a IX_ETH_ACC_FAIL : Error writing to the MAC registers
- * @li @a IX_ETH_ACC_INVALID_PORT : portId is invalid.
- * @li @a IX_ETH_ACC_PORT_UNINITIALIZED : portId is un-initialized
- *
- * <hr>
- */
-PUBLIC IxEthAccStatus
-ixEthAccPortMulticastAddressJoin(IxEthAccPortId portId,
-								 IxEthAccMacAddr *macAddr);
-
-/**
- * @ingroup IxEthAcc
- *
- * @fn ixEthAccPortMulticastAddressJoinAll(  IxEthAccPortId portId)
- *
- * @brief Filter all frames with multicast dest.
- *
- * This function clears the MAC address table, and then sets
- * the MAC to forward ALL multicast frames to the NPE.
- * Specifically, it forwards all frames whose destination address
- * has the LSB of the highest byte set  (01:00:00:00:00:00).  This
- * bit is commonly referred to as the "multicast bit".
- * Broadcast frames will still be forwarded. 
- *
- * Other functions modify the MAC filtering
- *
- * @li @a ixEthAccPortMulticastAddressJoinAll() - all multicast
- *     frames are forwarded to the application
- * @li @a ixEthAccPortMulticastAddressLeaveAll() - rollback the
- *     effects of @a ixEthAccPortMulticastAddressJoinAll()
- * @li @a ixEthAccPortMulticastAddressLeave() - unprovision a new 
- *     filtering address
- * @li @a ixEthAccPortMulticastAddressJoin() - provision a new 
- *     filtering address
- * @li @a ixEthAccPortPromiscuousModeSet() - all frames are 
- *     forwarded to the application regardless of the multicast 
- *     address provisioned
- * @li @a ixEthAccPortPromiscuousModeClear() - frames are forwarded 
- *     to the application following the multicast address provisioned
- *
- * In all cases, unicast and broadcast addresses are forwarded to 
- * the application.
- *
- * @li Reentrant    - yes
- * @li ISR Callable - no
- *
- * @param portId @ref IxEthAccPortId [in] - Ethernet port id.
- *
- * @return IxEthAccStatus 
- * @li @a IX_ETH_ACC_SUCCESS
- * @li @a IX_ETH_ACC_INVALID_PORT : portId is invalid.
- * @li @a IX_ETH_ACC_PORT_UNINITIALIZED : portId is un-initialized
- *
- * <hr>
- */
-PUBLIC IxEthAccStatus
-ixEthAccPortMulticastAddressJoinAll(IxEthAccPortId portId);
-
-/**
- * @ingroup IxEthAcc
- *
- * @fn ixEthAccPortMulticastAddressLeave( IxEthAccPortId portId,
-                                         IxEthAccMacAddr *macAddr)
- *
- * @brief Remove a multicast address from the MAC address table.
- *
- * Other functions modify the MAC filtering
- *
- * @li @a ixEthAccPortMulticastAddressJoinAll() - all multicast
- *     frames are forwarded to the application
- * @li @a ixEthAccPortMulticastAddressLeaveAll() - rollback the
- *     effects of @a ixEthAccPortMulticastAddressJoinAll()
- * @li @a ixEthAccPortMulticastAddressLeave() - unprovision a new 
- *     filtering address
- * @li @a ixEthAccPortMulticastAddressJoin() - provision a new 
- *     filtering address
- * @li @a ixEthAccPortPromiscuousModeSet() - all frames are 
- *     forwarded to the application regardless of the multicast 
- *     address provisioned
- * @li @a ixEthAccPortPromiscuousModeClear() - frames are forwarded 
- *     to the application following the multicast address provisioned
- *
- * In all cases, unicast and broadcast addresses are forwarded to 
- * the application.
- *
- * @li Reentrant    - yes
- * @li ISR Callable - no
- *
- * @param portId @ref IxEthAccPortId [in] - Ethernet port id.
- * @param *macAddr @ref IxEthAccMacAddr [in] - Ethernet Mac address.
- *
- * @return IxEthAccStatus
- * @li @a IX_ETH_ACC_SUCCESS
- * @li @a IX_ETH_ACC_NO_SUCH_ADDR :  Failed if MAC address was not in the table.
- * @li @a IX_ETH_ACC_INVALID_PORT : portId is invalid.
- * @li @a IX_ETH_ACC_PORT_UNINITIALIZED : portId is un-initialized
- *
- * <hr>
- */
-PUBLIC IxEthAccStatus
-ixEthAccPortMulticastAddressLeave(IxEthAccPortId portId,
-								  IxEthAccMacAddr *macAddr);
-
-/**
- * @ingroup IxEthAcc
- *
- * @fn ixEthAccPortMulticastAddressLeaveAll( IxEthAccPortId portId)
- *
- * @brief This function unconfigures the multicast filtering settings
- *
- * This function first clears the MAC address table, and then sets
- * the MAC as configured by the promiscuous mode current settings.
- *
- * Other functions modify the MAC filtering
- *
- * @li @a ixEthAccPortMulticastAddressJoinAll() - all multicast
- *     frames are forwarded to the application
- * @li @a ixEthAccPortMulticastAddressLeaveAll() - rollback the
- *     effects of @a ixEthAccPortMulticastAddressJoinAll()
- * @li @a ixEthAccPortMulticastAddressLeave() - unprovision a new 
- *     filtering address
- * @li @a ixEthAccPortMulticastAddressJoin() - provision a new 
- *     filtering address
- * @li @a ixEthAccPortPromiscuousModeSet() - all frames are 
- *     forwarded to the application regardless of the multicast 
- *     address provisioned
- * @li @a ixEthAccPortPromiscuousModeClear() - frames are forwarded 
- *     to the application following the multicast address provisioned
- *
- * In all cases, unicast and broadcast addresses are forwarded to 
- * the application.
- *
- * @li Reentrant    - yes
- * @li ISR Callable - no
- *
- * @param portId @ref IxEthAccPortId [in] - Ethernet port id.
- *
- * @return IxEthAccStatus
- * @li @a IX_ETH_ACC_SUCCESS
- * @li @a IX_ETH_ACC_INVALID_PORT : portId is invalid.
- * @li @a IX_ETH_ACC_PORT_UNINITIALIZED : portId is un-initialized
- *
- * <hr>
- */
-PUBLIC IxEthAccStatus
-ixEthAccPortMulticastAddressLeaveAll(IxEthAccPortId portId);
-
-/**
- * @ingroup IxEthAcc
- *
- * @fn ixEthAccPortUnicastAddressShow(IxEthAccPortId portId)
- *
- * @brief Displays unicast MAC address
- *
- * Displays unicast address which is configured using 
- * @a ixEthAccUnicastMacAddressSet. This function also displays the MAC filter used
- * to filter multicast frames.
- *
- * Other functions modify the MAC filtering
- *
- * @li @a ixEthAccPortMulticastAddressJoinAll() - all multicast
- *     frames are forwarded to the application
- * @li @a ixEthAccPortMulticastAddressLeaveAll() - rollback the
- *     effects of @a ixEthAccPortMulticastAddressJoinAll()
- * @li @a ixEthAccPortMulticastAddressLeave() - unprovision a new 
- *     filtering address
- * @li @a ixEthAccPortMulticastAddressJoin() - provision a new 
- *     filtering address
- * @li @a ixEthAccPortPromiscuousModeSet() - all frames are 
- *     forwarded to the application regardless of the multicast 
- *     address provisioned
- * @li @a ixEthAccPortPromiscuousModeClear() - frames are forwarded 
- *     to the application following the multicast address provisioned
- *
- * In all cases, unicast and broadcast addresses are forwarded to 
- * the application.
- *
- * @li Reentrant    - yes
- * @li ISR Callable - no
- *
- * @param portId @ref IxEthAccPortId [in] - Ethernet port id.
- *
- * @return void
- *
- * <hr>
- */
-PUBLIC IxEthAccStatus ixEthAccPortUnicastAddressShow(IxEthAccPortId portId);
-
-
-/**
- * @ingroup IxEthAcc
- *
- * @fn ixEthAccPortMulticastAddressShow( IxEthAccPortId portId)
- *
- * @brief Displays multicast MAC address
- *
- * Displays multicast address which have been configured using @a ixEthAccMulticastAddressJoin
- * 
- * @li Reentrant    - yes
- * @li ISR Callable - no
- * 
- * @param portId @ref IxEthAccPortId [in] - Ethernet port id.
- *
- * @return void
- *
- * <hr>
- */
-PUBLIC void ixEthAccPortMulticastAddressShow( IxEthAccPortId portId);
-
-/**
- * @ingroup IxEthAcc
- *
- * @fn ixEthAccPortDuplexModeSet( IxEthAccPortId portId, IxEthAccDuplexMode mode )
- *
- * @brief  Set the duplex mode for the MAC.
- *
- * Configure the IXP400 MAC to either full or half duplex. 
- *
- * @note 
- * The configuration should match that provisioned on the PHY.
- *
- * @li Reentrant    - yes
- * @li ISR Callable - no
- *
- * @param portId @ref IxEthAccPortId [in]
- * @param mode @ref IxEthAccDuplexMode [in]
- *
- * @return IxEthAccStatus 
- * @li @a IX_ETH_ACC_SUCCESS 
- * @li @a IX_ETH_ACC_INVALID_PORT : portId is invalid.
- * @li @a IX_ETH_ACC_PORT_UNINITIALIZED : portId is un-initialized
- *
- * <hr>
- */
-PUBLIC IxEthAccStatus 
-ixEthAccPortDuplexModeSet(IxEthAccPortId portId,IxEthAccDuplexMode mode);
-
-/**
- * @ingroup IxEthAcc
- *
- * @fn ixEthAccPortDuplexModeGet( IxEthAccPortId portId, IxEthAccDuplexMode *mode )
- *
- * @brief  Get the duplex mode for the MAC.
- *
- * return the duplex configuration of the IXP400 MAC.
- *
- * @note
- * The configuration should match that provisioned on the PHY.
- * See @a ixEthAccDuplexModeSet
- *
- * @li Reentrant    - yes
- * @li ISR Callable - no
- *
- * @param portId @ref IxEthAccPortId [in]
- * @param *mode @ref IxEthAccDuplexMode [out]
- *
- * @return IxEthAccStatus
- * @li @a IX_ETH_ACC_SUCCESS 
- * @li @a IX_ETH_ACC_INVALID_PORT : portId is invalid.
- * @li @a IX_ETH_ACC_PORT_UNINITIALIZED : portId is un-initialized
- *
- * <hr>
- *
- */
-PUBLIC IxEthAccStatus 
-ixEthAccPortDuplexModeGet(IxEthAccPortId portId,IxEthAccDuplexMode *mode );
-
-/**
- * @ingroup IxEthAcc
- *
- * @fn ixEthAccPortTxFrameAppendPaddingEnable( IxEthAccPortId portId)
- *
- * @brief  Enable padding bytes to be appended to runt frames submitted to
- * this port
- * 
- * Enable up to 60 null-bytes padding bytes to be appended to runt frames 
- * submitted to this port. This is the default behavior of the access 
- * component.
- *
- * @warning Do not change this behaviour while the port is enabled.
- *
- * @note When Tx padding is enabled, Tx FCS generation is turned on
- *
- * @li Reentrant    - yes
- * @li ISR Callable - no
- *
- * @sa ixEthAccPortTxFrameAppendFCSDusable
- *
- * @param portId @ref IxEthAccPortId [in]
- *
- * @return IxEthAccStatus
- * @li @a IX_ETH_ACC_SUCCESS 
- * @li @a IX_ETH_ACC_INVALID_PORT : portId is invalid.
- * @li @a IX_ETH_ACC_PORT_UNINITIALIZED : portId is un-initialized
- *
- * <hr>
- */
-PUBLIC IxEthAccStatus
-ixEthAccPortTxFrameAppendPaddingEnable(IxEthAccPortId portId);
-
-/**
- * @ingroup IxEthAcc
- *
- * @fn ixEthAccPortTxFrameAppendPaddingDisable( IxEthAccPortId portId)
- *
- * @brief  Disable padding bytes to be appended to runt frames submitted to
- * this port
- * 
- * Disable padding bytes to be appended to runt frames 
- * submitted to this port. This is not the default behavior of the access 
- * component.
- *
- * @warning Do not change this behaviour while the port is enabled.
- *
- * @li Reentrant    - yes
- * @li ISR Callable - no
- *
- * @param portId @ref IxEthAccPortId [in] 
- *
- * @return IxEthAccStatus
- * @li @a IX_ETH_ACC_SUCCESS 
- * @li @a IX_ETH_ACC_INVALID_PORT : portId is invalid.
- * @li @a IX_ETH_ACC_PORT_UNINITIALIZED : portId is un-initialized
- *
- * <hr>
- */
-PUBLIC IxEthAccStatus
-ixEthAccPortTxFrameAppendPaddingDisable(IxEthAccPortId portId);
-
-/**
- * @ingroup IxEthAcc
- *
- * @fn ixEthAccPortTxFrameAppendFCSEnable( IxEthAccPortId portId)
- *
- * @brief  Enable the appending of Ethernet FCS to all frames submitted to this port
- * 
- * When enabled, the FCS is added to the submitted frames. This is the default 
- * behavior of the access component.
- * Do not change this behaviour while the port is enabled.
- *
- * @li Reentrant    - yes
- * @li ISR Callable - no
- *
- * @param portId @ref IxEthAccPortId [in] 
- *
- * @return IxEthAccStatus
- * @li @a IX_ETH_ACC_SUCCESS 
- * @li @a IX_ETH_ACC_INVALID_PORT : portId is invalid.
- * @li @a IX_ETH_ACC_PORT_UNINITIALIZED : portId is un-initialized
- *
- * <hr>
- */
-PUBLIC IxEthAccStatus
-ixEthAccPortTxFrameAppendFCSEnable(IxEthAccPortId portId);
-
-/**
- * @ingroup IxEthAcc
- *
- * @fn ixEthAccPortTxFrameAppendFCSDisable( IxEthAccPortId portId)
- *
- * @brief  Disable the appending of Ethernet FCS to all frames submitted to this port.
- * 
- * When disabled, the Ethernet FCS is not added to the submitted frames. 
- * This is not the default
- * behavior of the access component.
- *
- * @note Since the FCS is not appended to the frame it is expected that the frame submitted to the 
- * component includes a valid FCS at the end of the data, although this will not be validated.
- *
- * The component shall forward the frame to the Ethernet MAC WITHOUT modification.
- *
- * Do not change this behaviour while the port is enabled.
- *
- * @note Tx FCS append is not disabled while Tx padding is enabled.
- *
- * @li Reentrant    - yes
- * @li ISR Callable - no
- *
- * @sa ixEthAccPortTxFrameAppendPaddingEnable
- *
- * @param portId @ref IxEthAccPortId [in] 
- *
- * @return IxEthAccStatus
- * @li @a IX_ETH_ACC_SUCCESS 
- * @li @a IX_ETH_ACC_INVALID_PORT : portId is invalid.
- * @li @a IX_ETH_ACC_PORT_UNINITIALIZED : portId is un-initialized
- *
- * <hr>
- */
-PUBLIC IxEthAccStatus
-ixEthAccPortTxFrameAppendFCSDisable(IxEthAccPortId portId);
-
-/**
- * @ingroup IxEthAcc
- *
- * @fn ixEthAccPortRxFrameAppendFCSEnable( IxEthAccPortId portId)
- *
- * @brief Forward frames with FCS included in the receive buffer.
- *
- * The FCS is not striped from the receive buffer. 
- * The received frame length includes the FCS size (4 bytes). ie. 
- * A minimum sized ethernet frame shall have a length of 64bytes.
- *
- * Frame FCS validity checks are still carried out on all received frames.
- *
- * This is not the default
- * behavior of the access component.
- *
- * @li Reentrant    - yes
- * @li ISR Callable - no
- *
- * @param portId @ref IxEthAccPortId [in]
- *
- * @return IxEthAccStatus
- * @li @a IX_ETH_ACC_SUCCESS 
- * @li @a IX_ETH_ACC_INVALID_PORT : portId is invalid.
- * @li @a IX_ETH_ACC_PORT_UNINITIALIZED : portId is un-initialized
- *
- * <hr>
- */
-PUBLIC IxEthAccStatus
-ixEthAccPortRxFrameAppendFCSEnable(IxEthAccPortId portId);
-
-/**
- * @ingroup IxEthAcc
- *
- * @fn ixEthAccPortRxFrameAppendFCSDisable( IxEthAccPortId portId)
- *
- * @brief  Do not forward the FCS portion of the received Ethernet frame to the user. 
- * The FCS is striped from the receive buffer. 
- * The received frame length does not include the FCS size (4 bytes).
- * Frame FCS validity checks are still carried out on all received frames.
- *
- * This is the default behavior of the component.
- * Do not change this behaviour while the port is enabled.
- *
- * @li Reentrant    - yes
- * @li ISR Callable - no
- *
- * @param portId @ref IxEthAccPortId [in]
- *
- * @return IxEthAccStatus
- * @li @a IX_ETH_ACC_SUCCESS 
- * @li @a IX_ETH_ACC_INVALID_PORT : portId is invalid.
- * @li @a IX_ETH_ACC_PORT_UNINITIALIZED : portId is un-initialized
- *
- * <hr>
- */
-PUBLIC IxEthAccStatus
-ixEthAccPortRxFrameAppendFCSDisable(IxEthAccPortId portId);
-
-
-
-
-/**
- * @ingroup IxEthAcc
- *
- * @enum IxEthAccSchedulerDiscipline
- *
- * @brief  Definition for the port scheduling discipline
- *
- * Select the port scheduling discipline on receive and transmit path
- * @li FIFO : No Priority : In this configuration all frames are processed
- *                       in the access component in the strict order in which 
- *                        the component received them.
- * @li FIFO : Priority : This shall be a very simple priority mechanism. 
- *                     Higher prior-ity frames shall be forwarded 
- *                     before lower priority frames. There shall be no 
- *                     fairness mechanisms applied across different 
- *                     priorities. Higher priority frames could starve 
- *                     lower priority frames indefinitely.
- */
-typedef  enum 
-{
-    FIFO_NO_PRIORITY, /**<frames submitted with no priority*/
-    FIFO_PRIORITY /**<higher prority frames submitted before lower priority*/
-}IxEthAccSchedulerDiscipline;
-
-/**
- * @ingroup IxEthAcc
- *
- * @def IxEthAccTxSchedulerDiscipline
- *
- * @brief  Deprecated definition for the port transmit scheduling discipline
- */ 
-#define IxEthAccTxSchedulerDiscipline IxEthAccSchedulerDiscipline
-
-
-
-/**
- * @ingroup IxEthAcc
- *
- * @fn ixEthAccTxSchedulingDisciplineSet( IxEthAccPortId portId, IxEthAccSchedulerDiscipline sched)
- *
- * @brief Set the port scheduling to one of @a IxEthAccSchedulerDiscipline
- *
- * The default behavior of the component is @a FIFO_NO_PRIORITY.
- *
- * @li Reentrant    - yes
- * @li ISR Callable - no
- *
- * @pre
- *
- *
- * @param portId @ref IxEthAccPortId [in] 
- * @param sched @ref IxEthAccSchedulerDiscipline [in] 
- *
- * @return IxEthAccStatus
- * @li @a IX_ETH_ACC_SUCCESS : Set appropriate discipline.
- * @li @a IX_ETH_ACC_FAIL :  Invalid/unsupported discipline.
- * @li @a IX_ETH_ACC_INVALID_PORT : portId is invalid.
- * @li @a IX_ETH_ACC_PORT_UNINITIALIZED : portId is un-initialized
- *
- * <hr>
- */
-PUBLIC IxEthAccStatus
-ixEthAccTxSchedulingDisciplineSet(IxEthAccPortId portId, 
-								  IxEthAccSchedulerDiscipline sched);
-
-
-/**
- * @ingroup IxEthAcc
- *
- * @fn ixEthAccRxSchedulingDisciplineSet(IxEthAccSchedulerDiscipline sched)
- *
- * @brief Set the Rx scheduling to one of @a IxEthAccSchedulerDiscipline
- *
- * The default behavior of the component is @a FIFO_NO_PRIORITY.
- *
- * @li Reentrant    - yes
- * @li ISR Callable - no
- *
- * @pre
- *
- * @param sched : @a IxEthAccSchedulerDiscipline 
- *
- * @return IxEthAccStatus
- * @li @a IX_ETH_ACC_SUCCESS : Set appropriate discipline.
- * @li @a IX_ETH_ACC_FAIL :  Invalid/unsupported discipline.
- *
- * <hr>
- */
-PUBLIC IxEthAccStatus
-ixEthAccRxSchedulingDisciplineSet(IxEthAccSchedulerDiscipline sched);
-
-/**
- * @ingroup IxEthAcc
- *
- * @fn IxEthAccStatus ixEthAccNpeLoopbackEnable(IxEthAccPortId portId)
- *
- * @brief Enable NPE loopback
- *
- * When this loopback mode is enabled all the transmitted frames are
- * received on the same port, without payload.
- *
- * This function is recommended for power-up diagnostic checks and
- * should never be used under normal Ethernet traffic operations.
- *
- * @li Reentrant    - yes
- * @li ISR Callable - no
- *
- * @pre
- *
- * @param portId : ID of the port 
- *
- * @note Calling ixEthAccPortDisable followed by ixEthAccPortEnable is
- * guaranteed to restore correct Ethernet Tx/Rx operation.
- *
- * @return IxEthAccStatus
- * @li @a IX_ETH_ACC_SUCCESS : NPE loopback mode enabled
- * @li @a IX_ETH_ACC_FAIL : Invalid port or Ethernet service not initialized
- *
- * <hr>
- */
-PUBLIC IxEthAccStatus 
-ixEthAccPortNpeLoopbackEnable(IxEthAccPortId portId);
-
-/**
- * @ingroup IxEthAcc
- *
- * @fn IxEthAccStatus ixEthAccPortNpeLoopbackDisable(IxEthAccPortId portId)
- *
- * @brief Disable NPE loopback
- *
- * This function is used to disable the NPE loopback if previously
- * enabled using ixEthAccNpeLoopbackEnable.
- *
- * This function is recommended for power-up diagnostic checks and
- * should never be used under normal Ethernet traffic operations.
- *
- * @li Reentrant    - yes
- * @li ISR Callable - no
- *
- * @pre
- *
- * @note Calling ixEthAccPortDisable followed by ixEthAccPortEnable is
- * guaranteed to restore correct Ethernet Tx/Rx operation.
- *
- * @param portId : ID of the port 
- *
- * @return IxEthAccStatus
- * @li @a IX_ETH_ACC_SUCCESS : NPE loopback successfully disabled
- * @li @a IX_ETH_ACC_FAIL : Invalid port or Ethernet service not initialized
- *
- * <hr>
- */
-PUBLIC IxEthAccStatus 
-ixEthAccPortNpeLoopbackDisable(IxEthAccPortId portId);
-
-/**
- * @ingroup IxEthAcc
- *
- * @fn IxEthAccStatus ixEthAccPortTxEnable(IxEthAccPortId portId)
- *
- * @brief Enable Tx on the port
- *
- * This function is the complement of ixEthAccPortTxDisable and should
- * be used only after Tx was disabled. A MAC core reset is required before
- * this function is called (see @a ixEthAccPortMacReset).
- *
- * This function is the recommended usage scenario for emergency security
- * shutdown and hardware failure recovery and should never be used for throttling 
- * traffic.
- *
- * @li Reentrant    - yes
- * @li ISR Callable - no
- *
- * @pre
- *
- * @note Calling ixEthAccPortDisable followed by ixEthAccPortEnable is
- * guaranteed to restore correct Ethernet Tx/Rx operation.
- *
- * @param portId : ID of the port 
- *
- * @return IxEthAccStatus
- * @li @a IX_ETH_ACC_SUCCESS : Tx successfully enabled
- * @li @a IX_ETH_ACC_FAIL : Invalid port or Ethernet service not initialized
- *
- * <hr>
- */
-PUBLIC IxEthAccStatus 
-ixEthAccPortTxEnable(IxEthAccPortId portId);
-
-/**
- * @ingroup IxEthAcc
- *
- * @fn IxEthAccStatus ixEthAccPortTxDisable(IxEthAccPortId portId)
- *
- * @brief Disable Tx on the port
- *
- * This function can be used to disable Tx in the MAC core.
- * Tx can be re-enabled, although this is not guaranteed, by performing
- * a MAC core reset (@a ixEthAccPortMacReset) and calling ixEthAccPortTxEnable.
- * Note that using this function is not recommended, except for shutting
- * down Tx for emergency reasons. For proper port shutdown and re-enabling
- * see ixEthAccPortEnable and ixEthAccPortDisable.
- *
- * This function is the recommended usage scenario for emergency security
- * shutdown and hardware failure recovery and should never be used for throttling 
- * traffic.
- *
- * @li Reentrant    - yes
- * @li ISR Callable - no
- *
- * @note Calling ixEthAccPortDisable followed by ixEthAccPortEnable is
- * guaranteed to restore correct Ethernet Tx/Rx operation.
- *
- * @pre
- *
- * @param portId : ID of the port 
- *
- * @return IxEthAccStatus
- * @li @a IX_ETH_ACC_SUCCESS : Tx successfully disabled
- * @li @a IX_ETH_ACC_FAIL : Invalid port or Ethernet service not initialized
- *
- * <hr>
- */
-PUBLIC IxEthAccStatus 
-ixEthAccPortTxDisable(IxEthAccPortId portId);
-
-/**
- * @ingroup IxEthAcc
- *
- * @fn IxEthAccStatus ixEthAccPortRxEnable(IxEthAccPortId portId)
- *
- * @brief Enable Rx on the port
- *
- * This function is the complement of ixEthAccPortRxDisable and should
- * be used only after Rx was disabled.
- *
- * This function is the recommended usage scenario for emergency security
- * shutdown and hardware failure recovery and should never be used for throttling 
- * traffic.
- *
- * @li Reentrant    - yes
- * @li ISR Callable - no
- *
- * @note Calling ixEthAccPortDisable followed by ixEthAccPortEnable is
- * guaranteed to restore correct Ethernet Tx/Rx operation.
- *
- * @pre
- *
- * @param portId : ID of the port 
- *
- * @return IxEthAccStatus
- * @li @a IX_ETH_ACC_SUCCESS : Rx successfully enabled
- * @li @a IX_ETH_ACC_FAIL : Invalid port or Ethernet service not initialized
- *
- * <hr>
- */
-PUBLIC IxEthAccStatus 
-ixEthAccPortRxEnable(IxEthAccPortId portId);
-
-/**
- * @ingroup IxEthAcc
- *
- * @fn IxEthAccStatus ixEthAccPortRxDisable(IxEthAccPortId portId)
- *
- * @brief Disable Rx on the port
- *
- * This function can be used to disable Rx in the MAC core.
- * Rx can be re-enabled, although this is not guaranteed, by performing
- * a MAC core reset (@a ixEthAccPortMacReset) and calling ixEthAccPortRxEnable.
- * Note that using this function is not recommended, except for shutting
- * down Rx for emergency reasons. For proper port shutdown and re-enabling
- * see ixEthAccPortEnable and ixEthAccPortDisable.
- *
- * This function is the recommended usage scenario for emergency security
- * shutdown and hardware failure recovery and should never be used for throttling 
- * traffic.
- *
- * @li Reentrant    - yes
- * @li ISR Callable - no
- *
- * @pre
- *
- * @note Calling ixEthAccPortDisable followed by ixEthAccPortEnable is
- * guaranteed to restore correct Ethernet Tx/Rx operation.
- *
- * @param portId : ID of the port 
- *
- * @return IxEthAccStatus
- * @li @a IX_ETH_ACC_SUCCESS : Rx successfully disabled
- * @li @a IX_ETH_ACC_FAIL : Invalid port or Ethernet service not initialized
- *
- * <hr>
- */
-PUBLIC IxEthAccStatus 
-ixEthAccPortRxDisable(IxEthAccPortId portId);
-
-/**
- * @ingroup IxEthAcc
- *
- * @fn IxEthAccStatus ixEthAccPortMacReset(IxEthAccPortId portId)
- *
- * @brief Reset MAC core on the port
- *
- * This function will perform a MAC core reset (NPE Ethernet coprocessor).
- * This function is inherently unsafe and the NPE recovery is not guaranteed
- * after this function is called. The proper manner of performing port disable
- * and enable (which will reset the MAC as well) is ixEthAccPortEnable/ixEthAccPortDisable.
- *
- * This function is the recommended usage scenario for hardware failure recovery
- * and should never be used for throttling traffic.
- *
- * @li Reentrant    - yes
- * @li ISR Callable - no
- *
- * @pre
- *
- * @note Calling ixEthAccPortDisable followed by ixEthAccPortEnable is
- * guaranteed to restore correct Ethernet Tx/Rx operation.
- *
- * @param portId : ID of the port 
- *
- * @return IxEthAccStatus
- * @li @a IX_ETH_ACC_SUCCESS : MAC core reset
- * @li @a IX_ETH_ACC_FAIL : Invalid port or Ethernet service not initialized
- *
- * <hr>
- */
-PUBLIC IxEthAccStatus 
-ixEthAccPortMacReset(IxEthAccPortId portId);
-
-/*********************************************************************************
-  ####    #####    ##     #####     #     ####    #####     #     ####    ####
- #          #     #  #      #       #    #          #       #    #    #  #
-  ####      #    #    #     #       #     ####      #       #    #        ####
-      #     #    ######     #       #         #     #       #    #            #
- #    #     #    #    #     #       #    #    #     #       #    #    #  #    #
-  ####      #    #    #     #       #     ####      #       #     ####    ####
-**********************************************************************************/
-
-
-/**
- *
- * @brief This struct defines the statistics returned by this component.
- *
- * The component returns MIB2 EthObj variables which are obtained from the 
- * hardware or maintained by this component. 
- *
- *
- */
-typedef struct   
-{
-    UINT32 dot3StatsAlignmentErrors;            /**< link error count (rx) */
-    UINT32 dot3StatsFCSErrors;                  /**< link error count (rx) */
-    UINT32 dot3StatsInternalMacReceiveErrors;   /**< link error count (rx) */
-    UINT32 RxOverrunDiscards;                   /**< NPE: discarded frames count (rx) */
-    UINT32 RxLearnedEntryDiscards;                /**< NPE: discarded frames count(rx)  */
-    UINT32 RxLargeFramesDiscards;                 /**< NPE: discarded frames count(rx)  */
-    UINT32 RxSTPBlockedDiscards;                  /**< NPE: discarded frames count(rx)  */
-    UINT32 RxVLANTypeFilterDiscards;              /**< NPE: discarded frames count (rx) */
-    UINT32 RxVLANIdFilterDiscards;                /**< NPE: discarded frames count (rx) */
-    UINT32 RxInvalidSourceDiscards;               /**< NPE: discarded frames count (rx) */
-    UINT32 RxBlackListDiscards;                   /**< NPE: discarded frames count (rx) */
-    UINT32 RxWhiteListDiscards;                   /**< NPE: discarded frames count (rx) */
-    UINT32 RxUnderflowEntryDiscards;              /**< NPE: discarded frames count (rx) */
-    UINT32 dot3StatsSingleCollisionFrames;      /**< link error count (tx) */
-    UINT32 dot3StatsMultipleCollisionFrames;    /**< link error count (tx) */
-    UINT32 dot3StatsDeferredTransmissions;      /**< link error count (tx) */
-    UINT32 dot3StatsLateCollisions;             /**< link error count (tx) */
-    UINT32 dot3StatsExcessiveCollsions;         /**< link error count (tx) */
-    UINT32 dot3StatsInternalMacTransmitErrors;  /**< link error count (tx) */
-    UINT32 dot3StatsCarrierSenseErrors;         /**< link error count (tx) */
-    UINT32 TxLargeFrameDiscards;                /**< NPE: discarded frames count (tx) */
-    UINT32 TxVLANIdFilterDiscards;              /**< NPE: discarded frames count (tx) */
-
-}IxEthEthObjStats;
-
-/**
- * @ingroup IxEthAcc
- *
- * @fn ixEthAccMibIIStatsGet(IxEthAccPortId portId ,IxEthEthObjStats *retStats )
- *
- * @brief  Returns the statistics maintained for a port.
- *
- * @li Reentrant    - yes
- * @li ISR Callable - no
- *
- * @pre
- *
- *
- * @param portId @ref IxEthAccPortId [in] 
- * @param retStats @ref IxEthEthObjStats [out]
- * @note Please note the user is responsible for cache coheriency of the retStat
- * buffer. The data is actually populated via the NPE's. As such cache safe
- * memory should be used in the retStats argument.
- *
- * @return IxEthAccStatus
- * @li @a IX_ETH_ACC_SUCCESS
- * @li @a IX_ETH_ACC_FAIL : Invalid arguments.
- * @li @a IX_ETH_ACC_INVALID_PORT : portId is invalid.
- * @li @a IX_ETH_ACC_PORT_UNINITIALIZED : portId is un-initialized
- *
- * <hr>
- */
-PUBLIC IxEthAccStatus
-ixEthAccMibIIStatsGet(IxEthAccPortId portId, IxEthEthObjStats *retStats );
-
-/**
- * @ingroup IxEthAcc
- *
- * @fn ixEthAccMibIIStatsGetClear(IxEthAccPortId portId, IxEthEthObjStats *retStats)
- * 
- * @brief  Returns and clears the statistics maintained for a port. 
- *
- * @li Reentrant    - yes
- * @li ISR Callable - yes
- *
- * @pre
- *
- * @param portId @ref IxEthAccPortId [in] 
- * @param retStats @ref IxEthEthObjStats [out]
- * @note Please note the user is responsible for cache coheriency of the retStats
- * buffer. The data is actually populated via the NPE's. As such cache safe
- * memory should be used in the retStats argument.
- *
- * @return IxEthAccStatus
- * @li @a IX_ETH_ACC_SUCCESS
- * @li @a IX_ETH_ACC_FAIL : invalid arguments.
- * @li @a IX_ETH_ACC_INVALID_PORT : portId is invalid.
- * @li @a IX_ETH_ACC_PORT_UNINITIALIZED : portId is un-initialized
- *
- * <hr>
- */
-PUBLIC IxEthAccStatus
-ixEthAccMibIIStatsGetClear(IxEthAccPortId portId, IxEthEthObjStats *retStats);
-
-/**
- * @ingroup IxEthAcc
- *
- * @fn ixEthAccMibIIStatsClear(IxEthAccPortId portId)
- *
- * @brief   Clears the statistics maintained for a port.
- *
- * @li Reentrant    - yes
- * @li ISR Callable - no
- *
- * @pre
- *
- * @param portId @ref IxEthAccPortId [in]
- *
- * @return IxEthAccStatus
- * @li @a IX_ETH_ACC_SUCCESS
- * @li @a IX_ETH_ACC_FAIL : Invalid arguments.
- * @li @a IX_ETH_ACC_INVALID_PORT : portId is invalid.
- * @li @a IX_ETH_ACC_PORT_UNINITIALIZED : portId is un-initialized
- *
- * <hr>
- */
-PUBLIC IxEthAccStatus ixEthAccMibIIStatsClear(IxEthAccPortId portId);
-
-/**
- * @ingroup IxEthAcc
- *
- * @fn ixEthAccMacInit(IxEthAccPortId portId)
- * 
- * @brief Initializes the ethernet MAC settings 
- * 
- * @li Reentrant    - no
- * @li ISR Callable - no
- *
- * @param portId @ref IxEthAccPortId [in]
- *
- * @return IxEthAccStatus
- * @li @a IX_ETH_ACC_SUCCESS
- * @li @a IX_ETH_ACC_INVALID_PORT	:  portId is invalid.
- *
- * <hr>
- */
-PUBLIC IxEthAccStatus ixEthAccMacInit(IxEthAccPortId portId);
-
-/**
- * @ingroup IxEthAcc
- *
- * @fn ixEthAccStatsShow(IxEthAccPortId portId)
- *
- *
- * @brief Displays a ports statistics on the standard io console using printf.
- *
- * @li Reentrant    - no
- * @li ISR Callable - no
- *
- * @pre
- *
- * @param portId @ref IxEthAccPortId [in]
- *
- * @return void
- *
- * <hr>
- */
-PUBLIC void ixEthAccStatsShow(IxEthAccPortId portId);
-
-/*************************************************************************
-
- #    #     #       #            #    #  #####      #     ####
- ##  ##     #       #            ##  ##  #    #     #    #    #
- # ## #     #       #            # ## #  #    #     #    #    #
- #    #     #       #            #    #  #    #     #    #    #
- #    #     #       #            #    #  #    #     #    #    #
- #    #     #       #            #    #  #####      #     ####
-
-*************************************************************************/
-
-
-/**
- * @ingroup IxEthAcc
- *
- * @fn ixEthAccMiiReadRtn (UINT8 phyAddr, 
-                           UINT8 phyReg, 
-	                   UINT16 *value)
- *
- *
- * @brief Reads a 16 bit value from a PHY
- *
- * Reads a 16-bit word from a register of a MII-compliant PHY. Reading
- * is performed through the MII management interface.  This function returns
- * when the read operation has successfully completed, or when a timeout has elapsed.
- *
- * @li Reentrant    - no
- * @li ISR Callable - no
- *
- * @pre The MAC on Ethernet Port 2 (NPE C) must be initialised, and generating the MDIO clock.
- *   
- * @param phyAddr UINT8 [in] - the address of the Ethernet PHY (0-31)
- * @param phyReg UINT8 [in] -  the number of the MII register to read (0-31)
- * @param value UINT16 [in] -  the value read from the register
- *
- * @return IxEthAccStatus
- * @li @a IX_ETH_ACC_SUCCESS
- * @li @a IX_ETH_ACC_FAIL : failed to read the register.
- *
- * <hr>
- */
-PUBLIC IxEthAccStatus
-ixEthAccMiiReadRtn (UINT8 phyAddr, UINT8 phyReg, UINT16 *value);
-
-/**
- * @ingroup IxEthAcc
- *
- * @fn ixEthAccMiiWriteRtn (UINT8 phyAddr, 
-                            UINT8 phyReg, 
-	                    UINT16 value)
- *
- *
- * @brief Writes a 16 bit value to a PHY
- *
- * Writes a 16-bit word from a register of a MII-compliant PHY. Writing
- * is performed through the MII management interface.  This function returns
- * when the write operation has successfully completed, or when a timeout has elapsed.
- *
- * @li Reentrant    - no
- * @li ISR Callable - no
- *
- * @pre The MAC on Ethernet Port 2 (NPE C) must be initialised, and generating the MDIO clock.
- *   
- * @param phyAddr UINT8 [in] - the address of the Ethernet PHY (0-31)
- * @param phyReg UINT8 [in] -  the number of the MII register to write (0-31)
- * @param value UINT16 [out] -  the value to write to the register
- *
- * @return IxEthAccStatus
- * @li @a IX_ETH_ACC_SUCCESS
- * @li @a IX_ETH_ACC_FAIL : failed to write register.
- *
- * <hr>
- */
-PUBLIC IxEthAccStatus
-ixEthAccMiiWriteRtn (UINT8 phyAddr, UINT8 phyReg, UINT16 value);
-
-/**
- * @ingroup IxEthAcc
- *
- * @fn ixEthAccMiiAccessTimeoutSet(UINT32 timeout)
- *
- * @brief Overrides the default timeout value and retry count when reading or 
- * writing MII registers using ixEthAccMiiWriteRtn or ixEthAccMiiReadRtn
- *
- * The default behavior of the component is to use a IX_ETH_ACC_MII_10TH_SEC_IN_MILLIS ms
- * timeout (declared as 100 in IxEthAccMii_p.h) and a retry count of IX_ETH_ACC_MII_TIMEOUT_10TH_SECS
- * (declared as 5 in IxEthAccMii_p.h).
- *
- * The MII read and write functions will attempt to read the status of the register up
- * to the retry count times, delaying between each attempt with the timeout value.
- *
- * @li Reentrant    - no
- * @li ISR Callable - no
- *
- * @pre
- *
- * @param timeout UINT32 [in] - new timeout value, in milliseconds
- * @param timeout UINT32 [in] - new retry count (a minimum value of 1 must be used)
- *
- * @return IxEthAccStatus
- * @li @a IX_ETH_ACC_SUCCESS
- * @li @a IX_ETH_ACC_FAIL : invalid parameter(s)
- *
- * <hr>
- */
-PUBLIC IxEthAccStatus
-ixEthAccMiiAccessTimeoutSet(UINT32 timeout, UINT32 retryCount);
-
-/**
- * @ingroup IxEthAcc
- *
- * @fn ixEthAccMiiStatsShow (UINT32 phyAddr)
- *
- *
- * @brief Displays detailed information on a specified PHY
- *
- * Displays the current values of the first eigth MII registers for a PHY, 
- *
- * @li Reentrant    - no
- * @li ISR Callable - no
- *
- * @pre The MAC on Ethernet Port 2 (NPE C) must be initialised, and 
- *      generating the MDIO clock.
- *   
- * @param phyAddr UINT32 [in] - the address of the Ethernet PHY (0-31)
- *
- * @return IxEthAccStatus
- * @li @a IX_ETH_ACC_SUCCESS
- * @li @a IX_ETH_ACC_FAIL : invalid arguments.
- *
- * <hr>
- */
-PUBLIC IxEthAccStatus ixEthAccMiiStatsShow (UINT32 phyAddr);
-
-
-
-/******* BOARD SPECIFIC DEPRECATED API *********/
-
-/* The following functions are high level functions which rely
- * on the properties and interface of some Ethernet PHYs. The
- * implementation is hardware specific and has been moved to 
- * the hardware-specific component IxEthMii.
- */
-
- #include "IxEthMii.h"
-
-/**
- * @ingroup IxEthAcc
- *
- * @def  ixEthAccMiiPhyScan
- *
- * @brief : deprecated API entry point. This definition 
- * ensures backward compatibility
- *
- * See @ref ixEthMiiPhyScan
- *
- * @note this feature is board specific
- *
- */
-#define ixEthAccMiiPhyScan(phyPresent) ixEthMiiPhyScan(phyPresent,IXP425_ETH_ACC_MII_MAX_ADDR)
-
-/**
- * @ingroup IxEthAcc
- *
- * @def ixEthAccMiiPhyConfig
- *
- * @brief : deprecated API entry point. This definition 
- * ensures backward compatibility
- *
- * See @ref ixEthMiiPhyConfig
- *
- * @note this feature is board specific
- */
-#define ixEthAccMiiPhyConfig(phyAddr,speed100,fullDuplex,autonegotiate) \
-           ixEthMiiPhyConfig(phyAddr,speed100,fullDuplex,autonegotiate)
-
-/**
- * @ingroup IxEthAcc
- *
- * @def ixEthAccMiiPhyReset
- *
- * @brief : deprecated API entry point. This definition 
- * ensures backward compatibility
- *
- * See @ref ixEthMiiPhyReset
- *
- * @note this feature is board specific
- */
-#define ixEthAccMiiPhyReset(phyAddr) \
-           ixEthMiiPhyReset(phyAddr)
-
-/**
- * @ingroup IxEthAcc
- *
- * @def ixEthAccMiiLinkStatus
- *
- * @brief : deprecated API entry point. This definition 
- * ensures backward compatibility
- *
- * See @ref ixEthMiiLinkStatus
- *
- * @note this feature is board specific
- */
-#define ixEthAccMiiLinkStatus(phyAddr,linkUp,speed100,fullDuplex,autoneg) \
-           ixEthMiiLinkStatus(phyAddr,linkUp,speed100,fullDuplex,autoneg)
-
-
-
-/**
- * @ingroup IxEthAcc
- *
- * @def ixEthAccMiiShow  
- *
- * @brief : deprecated API entry point. This definition 
- * ensures backward compatibility
- *
- * See @ref ixEthMiiPhyShow
- *
- * @note this feature is board specific
- */
-#define ixEthAccMiiShow(phyAddr) \
-        ixEthMiiPhyShow(phyAddr)
-
-#endif /* ndef IxEthAcc_H */
-/**
- *@}
- */
diff --git a/drivers/net/npe/include/IxEthAccDataPlane_p.h b/drivers/net/npe/include/IxEthAccDataPlane_p.h
deleted file mode 100644
index dce43d9a19..0000000000
--- a/drivers/net/npe/include/IxEthAccDataPlane_p.h
+++ /dev/null
@@ -1,221 +0,0 @@
-/**
- * @file IxEthAccDataPlane_p.h
- *
- * @author Intel Corporation
- * @date 12-Feb-2002
- *
- * @brief  Internal Header file for IXP425 Ethernet Access component.
- *
- * Design Notes:
- *
- * 
- * @par
- * IXP400 SW Release version 2.0
- * 
- * -- Copyright Notice --
- * 
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- * 
- * @par
- * SPDX-License-Identifier:	BSD-3-Clause
- * @par
- * -- End of Copyright Notice --
- */
-
-
-
-#ifndef IxEthAccDataPlane_p_H
-#define IxEthAccDataPlane_p_H
-
-#include <IxOsal.h>
-#include <IxQMgr.h>
-
-/**
- * @addtogroup IxEthAccPri
- *@{
- */
-
-/* typedefs global to this file*/
-
-typedef struct
-{
-    IX_OSAL_MBUF *pHead;
-    IX_OSAL_MBUF *pTail;
-}IxEthAccDataPlaneQList;
-
-
-/**
- * @struct  IxEthAccDataPlaneStats
- * @brief   Statistics data structure associated with the data plane
- *
- */
-typedef struct
-{
-    UINT32 addToSwQ;
-    UINT32 removeFromSwQ;
-    UINT32 unchainedTxMBufs;
-    UINT32 chainedTxMBufs;
-    UINT32 unchainedTxDoneMBufs;
-    UINT32 chainedTxDoneMBufs;
-    UINT32 unchainedRxMBufs;
-    UINT32 chainedRxMBufs;
-    UINT32 unchainedRxFreeMBufs;
-    UINT32 chainedRxFreeMBufs;
-    UINT32 rxCallbackCounter;
-    UINT32 rxCallbackBurstRead;
-    UINT32 txDoneCallbackCounter;
-    UINT32 unexpectedError;
-} IxEthAccDataPlaneStats;
-
-/**
- * @fn ixEthAccMbufFromSwQ
- * @brief  used during disable steps to convert mbufs from 
- *  swq format, ready to be pushed into hw queues for NPE, 
- *  back into XScale format 
- */
-IX_OSAL_MBUF *ixEthAccMbufFromSwQ(IX_OSAL_MBUF *mbuf);
-
-/**
- * @fn ixEthAccDataPlaneShow
- * @brief  Show function (for data plane statistics
- */
-void ixEthAccDataPlaneShow(void);
-
-/*
- * lock dataplane when atomic operation is required
- */
-#define IX_ETH_ACC_DATA_PLANE_LOCK(arg) arg = ixOsalIrqLock();
-#define IX_ETH_ACC_DATA_PLANE_UNLOCK(arg) ixOsalIrqUnlock(arg);
-
-/*
- * Use MBUF fields
- */
-#define IX_ETHACC_NE_SHARED(mBufPtr) \
- ((IxEthAccNe *)&((mBufPtr)->ix_ne))
-
-#if 1
-
-#define IX_ETHACC_NE_NEXT(mBufPtr) (mBufPtr)->ix_ne.reserved[0]
-
-/* tm - wrong!! len and pkt_len are in the second word - #define IX_ETHACC_NE_LEN(mBufPtr) (mBufPtr)->ix_ne.reserved[3] */
-#define IX_ETHACC_NE_LEN(mBufPtr) (mBufPtr)->ix_ne.reserved[1]
-
-#define IX_ETHACC_NE_DATA(mBufPtr)(mBufPtr)->ix_ne.reserved[2]
-
-#else
-
-#define IX_ETHACC_NE_NEXT(mBufPtr) \
-  IX_ETHACC_NE_SHARED(mBufPtr)->ixReserved_next
-
-#define IX_ETHACC_NE_LEN(mBufPtr) \
-  IX_ETHACC_NE_SHARED(mBufPtr)->ixReserved_lengths
-
-#define IX_ETHACC_NE_DATA(mBufPtr) \
-  IX_ETHACC_NE_SHARED(mBufPtr)->ixReserved_data
-#endif
-
-/*
- * Use MBUF  next pointer field to chain data.
- */
-#define IX_ETH_ACC_MBUF_NEXT_PKT_CHAIN_MEMBER(mbuf) (mbuf)->ix_ctrl.ix_chain
-
-
-
-#define IX_ETH_ACC_DATAPLANE_IS_Q_EMPTY(mbuf_list) ((mbuf_list.pHead) == NULL)
-    
-
-#define IX_ETH_ACC_DATAPLANE_ADD_MBUF_TO_Q_HEAD(mbuf_list,mbuf_to_add) 		\
-  do {										\
-    int lockVal;								\
-    IX_ETH_ACC_DATA_PLANE_LOCK(lockVal);                                    	\
-    IX_ETH_ACC_STATS_INC(ixEthAccDataStats.addToSwQ);                           \
-    if ( (mbuf_list.pHead) != NULL ) 						\
-    {										\
-      (IX_ETH_ACC_MBUF_NEXT_PKT_CHAIN_MEMBER((mbuf_to_add))) = (mbuf_list.pHead);\
-      (mbuf_list.pHead) = (mbuf_to_add);					\
-    } 										\
-    else {									\
-      (mbuf_list.pTail) = (mbuf_list.pHead) = (mbuf_to_add);			\
-      IX_ETH_ACC_MBUF_NEXT_PKT_CHAIN_MEMBER((mbuf_to_add)) = NULL;		\
-    } 										\
-    IX_ETH_ACC_DATA_PLANE_UNLOCK(lockVal);					\
-  } while(0)
-
-
-#define IX_ETH_ACC_DATAPLANE_ADD_MBUF_TO_Q_TAIL(mbuf_list,mbuf_to_add)   	\
-  do {										\
-    int lockVal;								\
-    IX_ETH_ACC_DATA_PLANE_LOCK(lockVal);                                    	\
-    IX_ETH_ACC_STATS_INC(ixEthAccDataStats.addToSwQ);                           \
-    if ( (mbuf_list.pHead) == NULL ) 						\
-    {										\
-      (mbuf_list.pHead) = mbuf_to_add;						\
-      IX_ETH_ACC_MBUF_NEXT_PKT_CHAIN_MEMBER((mbuf_to_add)) = NULL;		\
-    } 										\
-    else {									\
-      IX_ETH_ACC_MBUF_NEXT_PKT_CHAIN_MEMBER((mbuf_list.pTail)) = (mbuf_to_add);	\
-      IX_ETH_ACC_MBUF_NEXT_PKT_CHAIN_MEMBER((mbuf_to_add)) = NULL;		\
-    } 										\
-    (mbuf_list.pTail) = mbuf_to_add;						\
-    IX_ETH_ACC_DATA_PLANE_UNLOCK(lockVal);					\
-  } while (0)
-
-
-#define IX_ETH_ACC_DATAPLANE_REMOVE_MBUF_FROM_Q_HEAD(mbuf_list,mbuf_to_rem)   	\
-  do {										\
-    int lockVal;								\
-    IX_ETH_ACC_DATA_PLANE_LOCK(lockVal);                                    	\
-    if ( (mbuf_list.pHead) != NULL ) 						\
-    {										\
-      IX_ETH_ACC_STATS_INC(ixEthAccDataStats.removeFromSwQ);                    \
-      (mbuf_to_rem) = (mbuf_list.pHead) ;					\
-      (mbuf_list.pHead) = (IX_ETH_ACC_MBUF_NEXT_PKT_CHAIN_MEMBER((mbuf_to_rem)));\
-    } 										\
-    else {									\
-      (mbuf_to_rem) = NULL;							\
-    } 										\
-    IX_ETH_ACC_DATA_PLANE_UNLOCK(lockVal);					\
-  } while (0)
-
-
-/**
- * @brief message handler QManager entries for NPE id => port ID conversion (NPE_B => 0, NPE_C => 1)
- */
-#define IX_ETH_ACC_PORT_TO_NPE_ID(port) \
-   ixEthAccPortData[(port)].npeId
-
-#define IX_ETH_ACC_NPE_TO_PORT_ID(npe) ((npe == 0 ? 2 : (npe == 1 ? 0 : ( npe == 2 ? 1 : -1 ))))
-
-#define IX_ETH_ACC_PORT_TO_TX_Q_ID(port)  \
-   ixEthAccPortData[(port)].ixEthAccTxData.txQueue
-
-#define IX_ETH_ACC_PORT_TO_RX_FREE_Q_ID(port) \
-   ixEthAccPortData[(port)].ixEthAccRxData.rxFreeQueue
-
-#define IX_ETH_ACC_PORT_TO_TX_Q_SOURCE(port)    (port == IX_ETH_PORT_1 ? IX_ETH_ACC_TX_FRAME_ENET0_Q_SOURCE : (port == IX_ETH_PORT_2 ? IX_ETH_ACC_TX_FRAME_ENET1_Q_SOURCE : IX_ETH_ACC_TX_FRAME_ENET2_Q_SOURCE))
-
-#define IX_ETH_ACC_PORT_TO_RX_FREE_Q_SOURCE(port) (port == IX_ETH_PORT_1 ? IX_ETH_ACC_RX_FREE_BUFF_ENET0_Q_SOURCE : (port == IX_ETH_PORT_2 ? IX_ETH_ACC_RX_FREE_BUFF_ENET1_Q_SOURCE : IX_ETH_ACC_RX_FREE_BUFF_ENET2_Q_SOURCE ))
-
-/* Flush the mbufs chain and all data pointed to by the mbuf */
-
-#ifndef NDEBUG
-#define IX_ETH_ACC_STATS_INC(x) (x++)
-#else
-#define IX_ETH_ACC_STATS_INC(x)
-#endif
-
-#define IX_ETH_ACC_MAX_TX_FRAMES_TO_SUBMIT 128
-
-void ixEthRxFrameQMCallback(IxQMgrQId qId, IxQMgrCallbackId callbackId);
-void ixEthRxMultiBufferQMCallback(IxQMgrQId qId, IxQMgrCallbackId callbackId);
-void ixEthTxFrameDoneQMCallback(IxQMgrQId qId, IxQMgrCallbackId callbackId);
-
-#endif /* IxEthAccDataPlane_p_H */
-
-
-/**
- *@}
- */
-
diff --git a/drivers/net/npe/include/IxEthAccMac_p.h b/drivers/net/npe/include/IxEthAccMac_p.h
deleted file mode 100644
index 4eafab2585..0000000000
--- a/drivers/net/npe/include/IxEthAccMac_p.h
+++ /dev/null
@@ -1,224 +0,0 @@
-/*
- * 
- * @par
- * IXP400 SW Release version 2.0
- * 
- * -- Copyright Notice --
- * 
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- * 
- * @par
- * SPDX-License-Identifier:	BSD-3-Clause
- * @par
- * -- End of Copyright Notice --
-*/
-
-
-#ifndef IxEthAccMac_p_H
-#define IxEthAccMac_p_H
-
-#include "IxOsal.h"
-
-#define IX_ETH_ACC_MAX_MULTICAST_ADDRESSES 256
-#define IX_ETH_ACC_NUM_PORTS 3
-#define IX_ETH_ACC_MAX_FRAME_SIZE_DEFAULT 1536
-#define IX_ETH_ACC_MAX_FRAME_SIZE_UPPER_RANGE (65536-64)
-#define IX_ETH_ACC_MAX_FRAME_SIZE_LOWER_RANGE 64
-
-/*
- * 
- * MAC register definitions
- *
- */
-#define IX_ETH_ACC_MAC_0_BASE IX_OSAL_IXP400_ETHA_PHYS_BASE
-#define IX_ETH_ACC_MAC_1_BASE IX_OSAL_IXP400_ETHB_PHYS_BASE
-#define IX_ETH_ACC_MAC_2_BASE IX_OSAL_IXP400_ETH_NPEA_PHYS_BASE
-
-#define IX_ETH_ACC_MAC_TX_CNTRL1       0x000
-#define IX_ETH_ACC_MAC_TX_CNTRL2       0x004
-#define IX_ETH_ACC_MAC_RX_CNTRL1       0x010
-#define IX_ETH_ACC_MAC_RX_CNTRL2       0x014
-#define IX_ETH_ACC_MAC_RANDOM_SEED     0x020
-#define IX_ETH_ACC_MAC_THRESH_P_EMPTY  0x030
-#define IX_ETH_ACC_MAC_THRESH_P_FULL   0x038
-#define IX_ETH_ACC_MAC_BUF_SIZE_TX     0x040
-#define IX_ETH_ACC_MAC_TX_DEFER        0x050
-#define IX_ETH_ACC_MAC_RX_DEFER        0x054
-#define IX_ETH_ACC_MAC_TX_TWO_DEFER_1  0x060
-#define IX_ETH_ACC_MAC_TX_TWO_DEFER_2  0x064
-#define IX_ETH_ACC_MAC_SLOT_TIME       0x070
-#define IX_ETH_ACC_MAC_MDIO_CMD_1      0x080
-#define IX_ETH_ACC_MAC_MDIO_CMD_2      0x084
-#define IX_ETH_ACC_MAC_MDIO_CMD_3      0x088
-#define IX_ETH_ACC_MAC_MDIO_CMD_4      0x08c
-#define IX_ETH_ACC_MAC_MDIO_STS_1      0x090
-#define IX_ETH_ACC_MAC_MDIO_STS_2      0x094
-#define IX_ETH_ACC_MAC_MDIO_STS_3      0x098
-#define IX_ETH_ACC_MAC_MDIO_STS_4      0x09c
-#define IX_ETH_ACC_MAC_ADDR_MASK_1     0x0A0
-#define IX_ETH_ACC_MAC_ADDR_MASK_2     0x0A4
-#define IX_ETH_ACC_MAC_ADDR_MASK_3     0x0A8
-#define IX_ETH_ACC_MAC_ADDR_MASK_4     0x0AC
-#define IX_ETH_ACC_MAC_ADDR_MASK_5     0x0B0
-#define IX_ETH_ACC_MAC_ADDR_MASK_6     0x0B4
-#define IX_ETH_ACC_MAC_ADDR_1          0x0C0
-#define IX_ETH_ACC_MAC_ADDR_2          0x0C4
-#define IX_ETH_ACC_MAC_ADDR_3          0x0C8
-#define IX_ETH_ACC_MAC_ADDR_4          0x0CC
-#define IX_ETH_ACC_MAC_ADDR_5          0x0D0
-#define IX_ETH_ACC_MAC_ADDR_6          0x0D4
-#define IX_ETH_ACC_MAC_INT_CLK_THRESH  0x0E0
-#define IX_ETH_ACC_MAC_UNI_ADDR_1      0x0F0
-#define IX_ETH_ACC_MAC_UNI_ADDR_2      0x0F4
-#define IX_ETH_ACC_MAC_UNI_ADDR_3      0x0F8
-#define IX_ETH_ACC_MAC_UNI_ADDR_4      0x0FC
-#define IX_ETH_ACC_MAC_UNI_ADDR_5      0x100
-#define IX_ETH_ACC_MAC_UNI_ADDR_6      0x104
-#define IX_ETH_ACC_MAC_CORE_CNTRL      0x1FC
-
-
-/*
- *
- *Bit definitions
- *
- */
-
-/* TX Control Register 1*/
-
-#define IX_ETH_ACC_TX_CNTRL1_TX_EN         BIT(0)
-#define IX_ETH_ACC_TX_CNTRL1_DUPLEX        BIT(1)
-#define IX_ETH_ACC_TX_CNTRL1_RETRY         BIT(2)
-#define IX_ETH_ACC_TX_CNTRL1_PAD_EN        BIT(3)
-#define IX_ETH_ACC_TX_CNTRL1_FCS_EN        BIT(4)
-#define IX_ETH_ACC_TX_CNTRL1_2DEFER        BIT(5)
-#define IX_ETH_ACC_TX_CNTRL1_RMII          BIT(6)
-
-/* TX Control Register 2 */
-#define IX_ETH_ACC_TX_CNTRL2_RETRIES_MASK  0xf
-
-/* RX Control Register 1 */
-#define IX_ETH_ACC_RX_CNTRL1_RX_EN         BIT(0)
-#define IX_ETH_ACC_RX_CNTRL1_PADSTRIP_EN   BIT(1)
-#define IX_ETH_ACC_RX_CNTRL1_CRC_EN        BIT(2)
-#define IX_ETH_ACC_RX_CNTRL1_PAUSE_EN      BIT(3)
-#define IX_ETH_ACC_RX_CNTRL1_LOOP_EN       BIT(4)
-#define IX_ETH_ACC_RX_CNTRL1_ADDR_FLTR_EN  BIT(5)
-#define IX_ETH_ACC_RX_CNTRL1_RX_RUNT_EN    BIT(6)
-#define IX_ETH_ACC_RX_CNTRL1_BCAST_DIS     BIT(7)
-
-/* RX Control Register 2 */
-#define IX_ETH_ACC_RX_CNTRL2_DEFER_EN      BIT(0)
-
-
-
-/* Core Control Register */
-#define IX_ETH_ACC_CORE_RESET              BIT(0)
-#define IX_ETH_ACC_CORE_RX_FIFO_FLUSH      BIT(1)
-#define IX_ETH_ACC_CORE_TX_FIFO_FLUSH      BIT(2)
-#define IX_ETH_ACC_CORE_SEND_JAM           BIT(3)
-#define IX_ETH_ACC_CORE_MDC_EN             BIT(4)
-
-/* 1st bit of 1st MAC octet */
-#define IX_ETH_ACC_ETH_MAC_BCAST_MCAST_BIT ( 1) 
-
-
-/*
- *
- * Default values
- *
- */
-
-
-#define IX_ETH_ACC_TX_CNTRL1_DEFAULT  (IX_ETH_ACC_TX_CNTRL1_TX_EN | \
- IX_ETH_ACC_TX_CNTRL1_RETRY  | \
- IX_ETH_ACC_TX_CNTRL1_FCS_EN | \
- IX_ETH_ACC_TX_CNTRL1_2DEFER | \
- IX_ETH_ACC_TX_CNTRL1_PAD_EN)
-
-#define IX_ETH_ACC_TX_MAX_RETRIES_DEFAULT      0x0f 
-
-#define IX_ETH_ACC_RX_CNTRL1_DEFAULT    (IX_ETH_ACC_RX_CNTRL1_CRC_EN    \
-					 | IX_ETH_ACC_RX_CNTRL1_RX_EN)
-
-#define IX_ETH_ACC_RX_CNTRL2_DEFAULT           0x0
-
-/* Thresholds determined by NPE firmware FS */
-#define IX_ETH_ACC_MAC_THRESH_P_EMPTY_DEFAULT  0x12
-#define IX_ETH_ACC_MAC_THRESH_P_FULL_DEFAULT   0x30
-
-/* Number of bytes that must be in the tx fifo before
-   transmission commences*/
-#define IX_ETH_ACC_MAC_BUF_SIZE_TX_DEFAULT     0x8
-
-/* One-part deferral values */
-#define IX_ETH_ACC_MAC_TX_DEFER_DEFAULT        0x15
-#define IX_ETH_ACC_MAC_RX_DEFER_DEFAULT        0x16
-
-/* Two-part deferral values... */
-#define IX_ETH_ACC_MAC_TX_TWO_DEFER_1_DEFAULT  0x08
-#define IX_ETH_ACC_MAC_TX_TWO_DEFER_2_DEFAULT  0x07
-
-/* This value applies to MII */
-#define IX_ETH_ACC_MAC_SLOT_TIME_DEFAULT       0x80
-
-/* This value applies to RMII */
-#define IX_ETH_ACC_MAC_SLOT_TIME_RMII_DEFAULT  0xFF
-
-#define IX_ETH_ACC_MAC_ADDR_MASK_DEFAULT       0xFF
-
-#define IX_ETH_ACC_MAC_INT_CLK_THRESH_DEFAULT  0x1
-/*The following is a value chosen at random*/
-#define IX_ETH_ACC_RANDOM_SEED_DEFAULT         0x8
-
-/*By default we must configure the MAC to generate the 
-  MDC clock*/
-#define IX_ETH_ACC_CORE_DEFAULT                (IX_ETH_ACC_CORE_MDC_EN)
-
-#define IXP425_ETH_ACC_MAX_PHY 2
-#define IXP425_ETH_ACC_MAX_AN_ENTRIES 20
-#define IX_ETH_ACC_MAC_RESET_DELAY    1
-
-#define IX_ETH_ACC_MAC_ALL_BITS_SET   0xFF
-
-#define IX_ETH_ACC_MAC_MSGID_SHL      24
-
-#define IX_ETH_ACC_PORT_DISABLE_DELAY_MSECS 20
-#define IX_ETH_ACC_PORT_DISABLE_DELAY_COUNT 200  /* 4 seconds timeout */
-#define IX_ETH_ACC_PORT_DISABLE_RETRY_COUNT 3
-#define IX_ETH_ACC_MIB_STATS_DELAY_MSECS 2000 /* 2 seconds delay for ethernet stats */ 
-
-/*Register access macros*/
-#if  (CPU == SIMSPARCSOLARIS)
-extern void registerWriteStub (UINT32 base, UINT32 offset, UINT32 val);
-extern UINT32 registerReadStub (UINT32 base, UINT32 offset);
-
-#define REG_WRITE(b,o,v) registerWriteStub(b, o, v)
-#define REG_READ(b,o,v)  do { v = registerReadStub(b, o); } while (0)
-#else
-#define REG_WRITE(b,o,v) IX_OSAL_WRITE_LONG((volatile UINT32 *)(b + o), v)
-#define REG_READ(b,o,v)  (v = IX_OSAL_READ_LONG((volatile UINT32 *)(b + o)))
-
-#endif
-
-void ixEthAccMacUnload(void);
-IxEthAccStatus ixEthAccMacMemInit(void);
-
-/* MAC core loopback */
-IxEthAccStatus ixEthAccPortLoopbackEnable(IxEthAccPortId portId);
-IxEthAccStatus ixEthAccPortLoopbackDisable(IxEthAccPortId portId);
-
-/* MAC core traffic control */
-IxEthAccStatus ixEthAccPortTxEnablePriv(IxEthAccPortId portId);
-IxEthAccStatus ixEthAccPortTxDisablePriv(IxEthAccPortId portId);
-IxEthAccStatus ixEthAccPortRxEnablePriv(IxEthAccPortId portId);
-IxEthAccStatus ixEthAccPortRxDisablePriv(IxEthAccPortId portId);
-IxEthAccStatus ixEthAccPortMacResetPriv(IxEthAccPortId portId);
-
-/* NPE software loopback */
-IxEthAccStatus ixEthAccNpeLoopbackDisablePriv(IxEthAccPortId portId);
-IxEthAccStatus ixEthAccNpeLoopbackEnablePriv(IxEthAccPortId portId);
-
-#endif /*IxEthAccMac_p_H*/
-
diff --git a/drivers/net/npe/include/IxEthAccMii_p.h b/drivers/net/npe/include/IxEthAccMii_p.h
deleted file mode 100644
index aff30f00af..0000000000
--- a/drivers/net/npe/include/IxEthAccMii_p.h
+++ /dev/null
@@ -1,73 +0,0 @@
-/**
- * @file IxEthAccMii_p.h
- *
- * @author Intel Corporation
- * @date 
- *
- * @brief  MII Header file
- *
- * Design Notes:
- *
- * 
- * @par
- * IXP400 SW Release version 2.0
- * 
- * -- Copyright Notice --
- * 
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- * 
- * @par
- * SPDX-License-Identifier:	BSD-3-Clause
- * @par
- * -- End of Copyright Notice --
- */
-
-#ifndef IxEthAccMii_p_H
-#define IxEthAccMii_p_H
-
-/* MII definitions - these have been verified against the LXT971 and LXT972 PHYs*/
-
-#define IXP425_ETH_ACC_MII_MAX_REG      32      /* max register per phy */
-
-#define IX_ETH_ACC_MII_REG_SHL    16
-#define IX_ETH_ACC_MII_ADDR_SHL   21
-
-/* Definitions for MII access routines*/
- 
-#define IX_ETH_ACC_MII_GO                  BIT(31)
-#define IX_ETH_ACC_MII_WRITE               BIT(26)
-#define IX_ETH_ACC_MII_TIMEOUT_10TH_SECS        5    
-#define IX_ETH_ACC_MII_10TH_SEC_IN_MILLIS     100
-#define IX_ETH_ACC_MII_READ_FAIL           BIT(31)
- 
-#define IX_ETH_ACC_MII_PHY_DEF_DELAY   300  /* max delay before link up, etc. */
-#define IX_ETH_ACC_MII_PHY_NO_DELAY    0x0  /* do not delay */
-#define IX_ETH_ACC_MII_PHY_NULL        0xff /* PHY is not present */
-#define IX_ETH_ACC_MII_PHY_DEF_ADDR    0x0  /* default PHY's logical address */
-
-#ifndef IX_ETH_ACC_MII_MONITOR_DELAY
-#   define IX_ETH_ACC_MII_MONITOR_DELAY   0x5    /* in seconds */
-#endif
-
-/* Register definition */  
-
-#define IX_ETH_ACC_MII_CTRL_REG	    0x0	/* Control Register */
-#define IX_ETH_ACC_MII_STAT_REG	    0x1	/* Status Register */
-#define IX_ETH_ACC_MII_PHY_ID1_REG  0x2	/* PHY identifier 1 Register */
-#define IX_ETH_ACC_MII_PHY_ID2_REG  0x3	/* PHY identifier 2 Register */
-#define IX_ETH_ACC_MII_AN_ADS_REG   0x4	/* Auto-Negotiation	  */
-					/* Advertisement Register */
-#define IX_ETH_ACC_MII_AN_PRTN_REG  0x5	/* Auto-Negotiation	    */
-					/* partner ability Register */
-#define IX_ETH_ACC_MII_AN_EXP_REG   0x6	/* Auto-Negotiation   */
-					/* Expansion Register */
-#define IX_ETH_ACC_MII_AN_NEXT_REG  0x7	/* Auto-Negotiation	       */
-					/* next-page transmit Register */
-
-IxEthAccStatus ixEthAccMdioShow (void);
-IxEthAccStatus ixEthAccMiiInit(void);
-void ixEthAccMiiUnload(void);
-
-#endif  /*IxEthAccMii_p_H*/
diff --git a/drivers/net/npe/include/IxEthAccQueueAssign_p.h b/drivers/net/npe/include/IxEthAccQueueAssign_p.h
deleted file mode 100644
index 65661a0dd5..0000000000
--- a/drivers/net/npe/include/IxEthAccQueueAssign_p.h
+++ /dev/null
@@ -1,113 +0,0 @@
-/**
- * @file IxEthAccQueueAssign_p.h
- *
- * @author Intel Corporation
- * @date 06-Mar-2002
- *
- * @brief   Mapping from QMgr Q's to internal assignment
- *
- * Design Notes:
- *
- * 
- * @par
- * IXP400 SW Release version 2.0
- * 
- * -- Copyright Notice --
- * 
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- * 
- * @par
- * SPDX-License-Identifier:	BSD-3-Clause
- * @par
- * -- End of Copyright Notice --
- */
-
-/**
- * @addtogroup IxEthAccPri
- *@{
- */
-
-/*
- * Os/System dependancies.
- */
-#include "IxOsal.h"
-
-/*
- * Intermodule dependancies
- */
-#include "IxQMgr.h"
-#include "IxQueueAssignments.h"
-
-/* Check range of Q's assigned to this component. */
-#if IX_ETH_ACC_RX_FRAME_ETH_Q >= (IX_QMGR_MIN_QUEUPP_QID ) |    	\
- IX_ETH_ACC_RX_FREE_BUFF_ENET0_Q  >=  (IX_QMGR_MIN_QUEUPP_QID) | 	\
- IX_ETH_ACC_RX_FREE_BUFF_ENET1_Q  >=  (IX_QMGR_MIN_QUEUPP_QID) | 	\
- IX_ETH_ACC_TX_FRAME_ENET0_Q >=   (IX_QMGR_MIN_QUEUPP_QID) |  		\
- IX_ETH_ACC_TX_FRAME_ENET1_Q >=   (IX_QMGR_MIN_QUEUPP_QID) | 		\
- IX_ETH_ACC_TX_FRAME_DONE_ETH_Q  >=  (IX_QMGR_MIN_QUEUPP_QID)  
-#error "Not all Ethernet Access Queues are betweem 1-31, requires full functionalty Q's unless otherwise validated "
-#endif
-
-/**
-*
-* @typedef  IxEthAccQregInfo
-*
-* @brief 
-*
-*/
-typedef struct 
-{
-   IxQMgrQId qId;
-   char *qName;
-   IxQMgrCallback qCallback;
-   IxQMgrCallbackId callbackTag;
-   IxQMgrQSizeInWords qSize;
-   IxQMgrQEntrySizeInWords qWords; 
-   BOOL           qNotificationEnableAtStartup;
-   IxQMgrSourceId qConditionSource; 
-   IxQMgrWMLevel  AlmostEmptyThreshold;
-   IxQMgrWMLevel  AlmostFullThreshold;
-
-} IxEthAccQregInfo;
-
-/*
- * Prototypes for all QM callbacks.
- */
-
-/* 
- * Rx Callbacks 
- */
-IX_ETH_ACC_PUBLIC
-void  ixEthRxFrameQMCallback(IxQMgrQId, IxQMgrCallbackId);
-
-IX_ETH_ACC_PUBLIC
-void  ixEthRxMultiBufferQMCallback(IxQMgrQId, IxQMgrCallbackId);
-
-IX_ETH_ACC_PUBLIC
-void  ixEthRxFreeQMCallback(IxQMgrQId, IxQMgrCallbackId);
-
-/* 
- * Tx Callback.
- */
-IX_ETH_ACC_PUBLIC
-void  ixEthTxFrameQMCallback(IxQMgrQId, IxQMgrCallbackId);
-
-IX_ETH_ACC_PUBLIC
-void  ixEthTxFrameDoneQMCallback(IxQMgrQId, IxQMgrCallbackId );
-
-
-#define IX_ETH_ACC_QM_QUEUE_DISPATCH_PRIORITY (IX_QMGR_Q_PRIORITY_0) /* Highest priority */
-
-/*
- * Queue watermarks
- */
-#define IX_ETH_ACC_RX_FRAME_ETH_Q_SOURCE 		(IX_QMGR_Q_SOURCE_ID_NOT_E   )
-#define IX_ETH_ACC_RX_FREE_BUFF_ENET0_Q_SOURCE 		(IX_QMGR_Q_SOURCE_ID_E   )   
-#define IX_ETH_ACC_RX_FREE_BUFF_ENET1_Q_SOURCE 		(IX_QMGR_Q_SOURCE_ID_E   )
-#define IX_ETH_ACC_RX_FREE_BUFF_ENET2_Q_SOURCE 		(IX_QMGR_Q_SOURCE_ID_E   )
-#define IX_ETH_ACC_TX_FRAME_ENET0_Q_SOURCE 		(IX_QMGR_Q_SOURCE_ID_E   ) 
-#define IX_ETH_ACC_TX_FRAME_ENET1_Q_SOURCE 		(IX_QMGR_Q_SOURCE_ID_E   )
-#define IX_ETH_ACC_TX_FRAME_ENET2_Q_SOURCE 		(IX_QMGR_Q_SOURCE_ID_E   )
-#define IX_ETH_ACC_TX_FRAME_DONE_ETH_Q_SOURCE 		(IX_QMGR_Q_SOURCE_ID_NOT_E   )
diff --git a/drivers/net/npe/include/IxEthAcc_p.h b/drivers/net/npe/include/IxEthAcc_p.h
deleted file mode 100644
index 1348f4e3c8..0000000000
--- a/drivers/net/npe/include/IxEthAcc_p.h
+++ /dev/null
@@ -1,301 +0,0 @@
-/**
- * @file IxEthAcc_p.h
- *
- * @author Intel Corporation
- * @date 12-Feb-2002
- *
- * @brief  Internal Header file for IXP425 Ethernet Access component.
- *
- * Design Notes:
- *
- * 
- * @par
- * IXP400 SW Release version 2.0
- * 
- * -- Copyright Notice --
- * 
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- * 
- * @par
- * SPDX-License-Identifier:	BSD-3-Clause
- * @par
- * -- End of Copyright Notice --
- */
-
-/**
- * @addtogroup IxEthAccPri
- *@{
- */
-
-#ifndef IxEthAcc_p_H
-#define IxEthAcc_p_H
-
-/*
- * Os/System dependancies.
- */
-#include "IxOsal.h"
-
-/*
- * Intermodule dependancies
- */
-#include "IxNpeDl.h"
-#include "IxQMgr.h"
-
-#include "IxEthNpe.h"
-
-/* 
- * Intra module dependancies
- */
-
-#include "IxEthAccDataPlane_p.h"
-#include "IxEthAccMac_p.h"
-
-
-#define INLINE __inline__
-
-#ifdef NDEBUG
-
-#define IX_ETH_ACC_PRIVATE static
-
-#else
-
-#define IX_ETH_ACC_PRIVATE
-
-#endif /* ndef NDEBUG */
-
-#define IX_ETH_ACC_PUBLIC
-
-
-#define IX_ETH_ACC_IS_PORT_VALID(port) ((port) <  IX_ETH_ACC_NUMBER_OF_PORTS  ? true : false )
-
-
-
-#ifndef NDEBUG
-#define IX_ETH_ACC_FATAL_LOG(a,b,c,d,e,f,g)   { ixOsalLog ( IX_OSAL_LOG_LVL_FATAL,IX_OSAL_LOG_DEV_STDOUT,a,b,c,d,e,f,g);}
-#define IX_ETH_ACC_WARNING_LOG(a,b,c,d,e,f,g) { ixOsalLog ( IX_OSAL_LOG_LVL_WARNING,IX_OSAL_LOG_DEV_STDOUT,a,b,c,d,e,f,g);}
-#define IX_ETH_ACC_DEBUG_LOG(a,b,c,d,e,f,g)   { ixOsalLog ( IX_OSAL_LOG_LVL_FATAL,IX_OSAL_LOG_DEV_STDOUT,a,b,c,d,e,f,g);}
-#else
-#define IX_ETH_ACC_FATAL_LOG(a,b,c,d,e,f,g)   { ixOsalLog ( IX_OSAL_LOG_LVL_FATAL,IX_OSAL_LOG_DEV_STDOUT,a,b,c,d,e,f,g);}
-#define IX_ETH_ACC_WARNING_LOG(a,b,c,d,e,f,g) { ixOsalLog ( IX_OSAL_LOG_LVL_WARNING,IX_OSAL_LOG_DEV_STDOUT,a,b,c,d,e,f,g);}
-#define IX_ETH_ACC_DEBUG_LOG(a,b,c,d,e,f,g)   {}
-#endif
-
-IX_ETH_ACC_PUBLIC IxEthAccStatus ixEthAccInitDataPlane(void);
-IX_ETH_ACC_PUBLIC IxEthAccStatus ixEthAccQMgrQueuesConfig(void);
-IX_ETH_ACC_PUBLIC IxEthAccStatus ixEthAccQMgrRxCallbacksRegister(IxQMgrCallback ixQMgrCallback);
-IX_ETH_ACC_PUBLIC IxEthAccStatus ixEthAccSingleEthNpeCheck(IxEthAccPortId portId);
-IX_ETH_ACC_PUBLIC void ixEthAccQMgrRxQEntryGet(UINT32 *numRxQueueEntries);
-
-/* prototypes for the private control plane functions (used by the control interface wrapper) */
-IX_ETH_ACC_PUBLIC IxEthAccStatus ixEthAccPortEnablePriv(IxEthAccPortId portId);
-IX_ETH_ACC_PUBLIC IxEthAccStatus ixEthAccPortDisablePriv(IxEthAccPortId portId);
-IX_ETH_ACC_PUBLIC IxEthAccStatus ixEthAccPortEnabledQueryPriv(IxEthAccPortId portId, BOOL *enabled);
-IX_ETH_ACC_PUBLIC IxEthAccStatus ixEthAccPortPromiscuousModeClearPriv(IxEthAccPortId portId);
-IX_ETH_ACC_PUBLIC IxEthAccStatus ixEthAccPortPromiscuousModeSetPriv(IxEthAccPortId portId);
-IX_ETH_ACC_PUBLIC IxEthAccStatus ixEthAccPortUnicastMacAddressSetPriv(IxEthAccPortId portId, IxEthAccMacAddr *macAddr);
-IX_ETH_ACC_PUBLIC IxEthAccStatus ixEthAccPortUnicastMacAddressGetPriv(IxEthAccPortId portId, IxEthAccMacAddr *macAddr);
-IX_ETH_ACC_PUBLIC IxEthAccStatus ixEthAccPortMulticastAddressJoinPriv(IxEthAccPortId portId, IxEthAccMacAddr *macAddr);
-IX_ETH_ACC_PUBLIC IxEthAccStatus ixEthAccPortMulticastAddressJoinAllPriv(IxEthAccPortId portId);
-IX_ETH_ACC_PUBLIC IxEthAccStatus ixEthAccPortMulticastAddressLeavePriv(IxEthAccPortId portId, IxEthAccMacAddr *macAddr);
-IX_ETH_ACC_PUBLIC IxEthAccStatus ixEthAccPortMulticastAddressLeaveAllPriv(IxEthAccPortId portId);
-IX_ETH_ACC_PUBLIC IxEthAccStatus ixEthAccPortUnicastAddressShowPriv(IxEthAccPortId portId);
-IX_ETH_ACC_PUBLIC void ixEthAccPortMulticastAddressShowPriv(IxEthAccPortId portId);
-IX_ETH_ACC_PUBLIC IxEthAccStatus ixEthAccPortDuplexModeSetPriv(IxEthAccPortId portId, IxEthAccDuplexMode mode);
-IX_ETH_ACC_PUBLIC IxEthAccStatus ixEthAccPortDuplexModeGetPriv(IxEthAccPortId portId, IxEthAccDuplexMode *mode);
-IX_ETH_ACC_PUBLIC IxEthAccStatus ixEthAccPortTxFrameAppendPaddingEnablePriv(IxEthAccPortId portId);
-IX_ETH_ACC_PUBLIC IxEthAccStatus ixEthAccPortTxFrameAppendPaddingDisablePriv(IxEthAccPortId portId);
-IX_ETH_ACC_PUBLIC IxEthAccStatus ixEthAccPortTxFrameAppendFCSEnablePriv(IxEthAccPortId portId);
-IX_ETH_ACC_PUBLIC IxEthAccStatus ixEthAccPortTxFrameAppendFCSDisablePriv(IxEthAccPortId portId);
-IX_ETH_ACC_PUBLIC IxEthAccStatus ixEthAccPortRxFrameAppendFCSEnablePriv(IxEthAccPortId portId);
-IX_ETH_ACC_PUBLIC IxEthAccStatus ixEthAccPortRxFrameAppendFCSDisablePriv(IxEthAccPortId portId);
-IX_ETH_ACC_PUBLIC IxEthAccStatus ixEthAccTxSchedulingDisciplineSetPriv(IxEthAccPortId portId, IxEthAccSchedulerDiscipline sched);
-IX_ETH_ACC_PUBLIC IxEthAccStatus ixEthAccRxSchedulingDisciplineSetPriv(IxEthAccSchedulerDiscipline sched);
-
-/**
- * @struct  ixEthAccRxDataStats
- * @brief   Stats data structures for data path. - Not obtained from h/w
- *
- */
-typedef struct
-{ 
-    UINT32 rxFrameClientCallback;
-    UINT32 rxFreeRepOK;
-    UINT32 rxFreeRepDelayed;
-    UINT32 rxFreeRepFromSwQOK;
-    UINT32 rxFreeRepFromSwQDelayed;
-    UINT32 rxFreeLateNotificationEnabled;
-    UINT32 rxFreeLowCallback;
-    UINT32 rxFreeOverflow;
-    UINT32 rxFreeLock;
-    UINT32 rxDuringDisable;
-    UINT32 rxSwQDuringDisable;
-    UINT32 rxUnlearnedMacAddress;
-    UINT32 rxPriority[IX_ETH_ACC_TX_PRIORITY_7 + 1];
-    UINT32 rxUnexpectedError;
-    UINT32 rxFiltered;
-} IxEthAccRxDataStats;
-
-/**
- * @struct  IxEthAccTxDataStats
- * @brief   Stats data structures for data path. - Not obtained from h/w
- *
- */
-typedef struct
-{   
-    UINT32 txQOK;
-    UINT32 txQDelayed;
-    UINT32 txFromSwQOK;
-    UINT32 txFromSwQDelayed;
-    UINT32 txLowThreshCallback;
-    UINT32 txDoneClientCallback;
-    UINT32 txDoneClientCallbackDisable;
-    UINT32 txOverflow;
-    UINT32 txLock;
-    UINT32 txPriority[IX_ETH_ACC_TX_PRIORITY_7 + 1];
-    UINT32 txLateNotificationEnabled;
-    UINT32 txDoneDuringDisable;
-    UINT32 txDoneSwQDuringDisable;
-    UINT32 txUnexpectedError;
-} IxEthAccTxDataStats;
-
-/* port Disable state machine : list of states */
-typedef enum
-{
-    /* general port states */
-    DISABLED = 0,
-    ACTIVE,
-
-    /* particular Tx/Rx states */
-    REPLENISH,
-    RECEIVE,
-    TRANSMIT,
-    TRANSMIT_DONE
-} IxEthAccPortDisableState;
-
-typedef struct
-{
-    BOOL fullDuplex;
-    BOOL rxFCSAppend;
-    BOOL txFCSAppend;
-    BOOL txPADAppend;
-    BOOL enabled;
-    BOOL promiscuous;
-    BOOL joinAll;
-    IxOsalMutex ackMIBStatsLock;
-    IxOsalMutex ackMIBStatsResetLock;
-    IxOsalMutex MIBStatsGetAccessLock;
-    IxOsalMutex MIBStatsGetResetAccessLock;
-    IxOsalMutex npeLoopbackMessageLock;
-    IxEthAccMacAddr mcastAddrsTable[IX_ETH_ACC_MAX_MULTICAST_ADDRESSES];
-    UINT32 mcastAddrIndex;
-    IX_OSAL_MBUF *portDisableTxMbufPtr;
-    IX_OSAL_MBUF *portDisableRxMbufPtr;
-
-    volatile IxEthAccPortDisableState portDisableState;
-    volatile IxEthAccPortDisableState rxState;
-    volatile IxEthAccPortDisableState txState;
-
-    BOOL initDone;
-    BOOL macInitialised;
-} IxEthAccMacState;
-
-/**
- * @struct  IxEthAccRxInfo
- * @brief   System-wide data structures associated with the data plane.
- *
- */
-typedef struct
-{
-  IxQMgrQId higherPriorityQueue[IX_QMGR_MAX_NUM_QUEUES]; /**< higher priority queue list */
-  IxEthAccSchedulerDiscipline schDiscipline; /**< Receive Xscale QoS type */
-} IxEthAccInfo; 
-
-/**
- * @struct  IxEthAccRxDataInfo
- * @brief   Per Port data structures associated with the receive data plane.
- *
- */
-typedef struct
-{
-  IxQMgrQId rxFreeQueue; /**< rxFree Queue for this port */
-  IxEthAccPortRxCallback rxCallbackFn;
-  UINT32  rxCallbackTag;
-  IxEthAccDataPlaneQList freeBufferList;
-  IxEthAccPortMultiBufferRxCallback rxMultiBufferCallbackFn;
-  UINT32  rxMultiBufferCallbackTag;
-  BOOL rxMultiBufferCallbackInUse;
-  IxEthAccRxDataStats stats; /**< Receive s/w stats */
-} IxEthAccRxDataInfo; 
-
-/**
- * @struct  IxEthAccTxDataInfo
- * @brief   Per Port data structures associated with the transmit data plane.
- *
- */
-typedef struct
-{
-  IxEthAccPortTxDoneCallback  txBufferDoneCallbackFn;
-  UINT32  txCallbackTag;
-  IxEthAccDataPlaneQList	txQ[IX_ETH_ACC_NUM_TX_PRIORITIES]; /**< Transmit Q */
-  IxEthAccSchedulerDiscipline schDiscipline; /**< Transmit Xscale QoS */
-  IxQMgrQId txQueue; /**< txQueue for this port */
-  IxEthAccTxDataStats stats; /**< Transmit s/w stats */
-} IxEthAccTxDataInfo; 
-
-
-/**
- * @struct  IxEthAccPortDataInfo
- * @brief   Per Port data structures associated with the port data plane.
- *
- */
-typedef struct
-{
-    BOOL               portInitialized;
-    UINT32 npeId; /**< NpeId for this port */
-    IxEthAccTxDataInfo ixEthAccTxData; /**< Transmit data control structures */
-    IxEthAccRxDataInfo ixEthAccRxData; /**< Receive data control structures */
-} IxEthAccPortDataInfo; 
-
-extern IxEthAccPortDataInfo  ixEthAccPortData[];
-#define IX_ETH_IS_PORT_INITIALIZED(port) (ixEthAccPortData[port].portInitialized)
-
-extern BOOL ixEthAccServiceInit;
-#define IX_ETH_ACC_IS_SERVICE_INITIALIZED() (ixEthAccServiceInit == true )
-
-/* 
- * Maximum number of frames to consume from the Rx Frame Q.
- */
-
-#define IX_ETH_ACC_MAX_RX_FRAME_CONSUME_PER_CALLBACK (128)
-
-/*
- * Max number of times to load the Rx Free Q from callback.  
- */
-#define IX_ETH_ACC_MAX_RX_FREE_BUFFERS_LOAD (256)  /* Set greater than depth of h/w Q + drain time at line rate */
-
-/*
- *  Max number of times to read from the Tx Done Q in one sitting.
- */
-
-#define IX_ETH_ACC_MAX_TX_FRAME_DONE_CONSUME_PER_CALLBACK (256)
-
-/*
- *  Max number of times to take buffers from S/w queues and write them to the H/w Tx
- *  queues on receipt of a Tx low threshold callback 
- */
-
-#define IX_ETH_ACC_MAX_TX_FRAME_TX_CONSUME_PER_CALLBACK (16)
-
-
-#define IX_ETH_ACC_FLUSH_CACHE(addr,size)  IX_OSAL_CACHE_FLUSH((addr),(size))
-#define IX_ETH_ACC_INVALIDATE_CACHE(addr,size)  IX_OSAL_CACHE_INVALIDATE((addr),(size))
-
-
-#define IX_ETH_ACC_MEMSET(start,value,size) memset(start,value,size)
-
-#endif /* ndef IxEthAcc_p_H */
-
-
-
diff --git a/drivers/net/npe/include/IxEthDB.h b/drivers/net/npe/include/IxEthDB.h
deleted file mode 100644
index 9c4a6a4ec4..0000000000
--- a/drivers/net/npe/include/IxEthDB.h
+++ /dev/null
@@ -1,2349 +0,0 @@
-/** @file IxEthDB.h
- *
- * @brief this file contains the public API of @ref IxEthDB component
- *
- * 
- * @par
- * IXP400 SW Release version 2.0
- * 
- * -- Copyright Notice --
- * 
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- * 
- * @par
- * SPDX-License-Identifier:	BSD-3-Clause
- * @par
- * -- End of Copyright Notice --
- *
- */
- 
-#ifndef IxEthDB_H
-#define IxEthDB_H
-
-#include <IxOsBuffMgt.h>
-#include <IxTypes.h>
-
-/**
- * @defgroup IxEthDB IXP400 Ethernet Database (IxEthDB) API
- *
- * @brief ethDB is a library that does provides a MAC address database learning/filtering capability
- *
- *@{
- */
-
-#define INLINE __inline__
-
-#define IX_ETH_DB_PRIVATE PRIVATE /* imported from IxTypes.h */
-
-#define IX_ETH_DB_PUBLIC PUBLIC
-
-/**
- * @brief port ID => message handler NPE id conversion (0 => NPE_B, 1 => NPE_C)
- */
-#define IX_ETH_DB_PORT_ID_TO_NPE(id) (id == 0 ? 1 : (id == 1 ? 2 : (id == 2 ? 0 : -1)))
-
-/**
- * @def IX_ETH_DB_NPE_TO_PORT_ID(npe)
- * @brief message handler NPE id => port ID conversion (NPE_B => 0, NPE_C => 1)
- */
-#define IX_ETH_DB_NPE_TO_PORT_ID(npe) (npe == 0 ? 2 : (npe == 1 ? 0 : (npe == 2 ? 1 : -1)))
-
-/* temporary define - won't work for Azusa */
-#define IX_ETH_DB_PORT_ID_TO_NPE_LOGICAL_ID(id) (IX_ETH_DB_PORT_ID_TO_NPE(id) << 4)
-#define IX_ETH_DB_NPE_LOGICAL_ID_TO_PORT_ID(id) (IX_ETH_DB_NPE_TO_PORT_ID(id >> 4))
-
-/**
- * @def IX_IEEE803_MAC_ADDRESS_SIZE
- * @brief The size of the MAC address
- */
-#define IX_IEEE803_MAC_ADDRESS_SIZE (6)
-
-/**
- * @def IX_IEEE802_1Q_QOS_PRIORITY_COUNT
- * @brief Number of QoS priorities defined by IEEE802.1Q
- */
-#define IX_IEEE802_1Q_QOS_PRIORITY_COUNT (8)
-
-/**
- * @enum IxEthDBStatus
- * @brief Ethernet Database API return values
- */
-typedef enum /* IxEthDBStatus */
-{
-  IX_ETH_DB_SUCCESS = IX_SUCCESS,   /**< Success */
-  IX_ETH_DB_FAIL = IX_FAIL,         /**< Failure */
-  IX_ETH_DB_INVALID_PORT,           /**< Invalid port */
-  IX_ETH_DB_PORT_UNINITIALIZED,     /**< Port not initialized */
-  IX_ETH_DB_MAC_UNINITIALIZED,      /**< MAC not initialized */
-  IX_ETH_DB_INVALID_ARG,            /**< Invalid argument */
-  IX_ETH_DB_NO_SUCH_ADDR,           /**< Address not found for search or delete operations */
-  IX_ETH_DB_NOMEM,                  /**< Learning database memory full */
-  IX_ETH_DB_BUSY,                   /**< Learning database cannot complete operation, access temporarily blocked */
-  IX_ETH_DB_END,                    /**< Database browser passed the end of the record set */
-  IX_ETH_DB_INVALID_VLAN,           /**< Invalid VLAN ID (valid range is 0..4094, 0 signifies no VLAN membership, used for priority tagged frames) */
-  IX_ETH_DB_INVALID_PRIORITY,       /**< Invalid QoS priority/traffic class (valid range for QoS priority is 0..7, valid range for traffic class depends on run-time configuration) */
-  IX_ETH_DB_NO_PERMISSION,          /**< No permission for attempted operation */
-  IX_ETH_DB_FEATURE_UNAVAILABLE,    /**< Feature not available (or not enabled) */
-  IX_ETH_DB_INVALID_KEY,            /**< Invalid search key */
-  IX_ETH_DB_INVALID_RECORD_TYPE     /**< Invalid record type */
-} IxEthDBStatus;
-    
-/** @brief VLAN ID type, valid range is 0..4094, 0 signifying no VLAN membership */
-typedef UINT32 IxEthDBVlanId;
-
-/** @brief 802.1Q VLAN tag, contains 3 bits user priority, 1 bit CFI, 12 bits VLAN ID */
-typedef UINT32 IxEthDBVlanTag;
-
-/** @brief QoS priority/traffic class type, valid range is 0..7, 0 being the lowest */
-typedef UINT32 IxEthDBPriority;
-
-/** @brief Priority mapping table; 0..7 QoS priorities used to index, table contains traffic classes */
-typedef UINT8 IxEthDBPriorityTable[8];
-
-/** @brief A 4096 bit array used to map the complete VLAN ID range */
-typedef UINT8 IxEthDBVlanSet[512];
-
-#define IX_ETH_DB_802_1Q_VLAN_MASK (0xFFF)
-#define IX_ETH_DB_802_1Q_QOS_MASK  (0x7)
-
-#define IX_ETH_DB_802_1Q_MAX_VLAN_ID (0xFFE)
-
-/**
- * @def IX_ETH_DB_SET_VLAN_ID
- * @brief returns the given 802.1Q tag with the VLAN ID field substituted with the given VLAN ID
- *
- * This macro is used to change the VLAN ID in a 802.1Q tag.
- *
- * Example: 
- * 
- *  tag = IX_ETH_DB_SET_VLAN_ID(tag, 32)
- *
- * inserts the VLAN ID "32" in the given tag.
- */
-#define IX_ETH_DB_SET_VLAN_ID(vlanTag, vlanID) (((vlanTag) & 0xF000) | ((vlanID) & IX_ETH_DB_802_1Q_VLAN_MASK))
-
-/**
-* @def IX_ETH_DB_GET_VLAN_ID
-* @brief returns the VLAN ID from the given 802.1Q tag
-*/
-#define IX_ETH_DB_GET_VLAN_ID(vlanTag) ((vlanTag) & IX_ETH_DB_802_1Q_VLAN_MASK)
-
-#define IX_ETH_DB_GET_QOS_PRIORITY(vlanTag) (((vlanTag) >> 13) & IX_ETH_DB_802_1Q_QOS_MASK)
-
-#define IX_ETH_DB_SET_QOS_PRIORITY(vlanTag, priority) (((vlanTag) & 0x1FFF) | (((priority) & IX_ETH_DB_802_1Q_QOS_MASK) << 13))
-
-#define IX_ETH_DB_CHECK_VLAN_TAG(vlanTag) { if(((vlanTag & 0xFFFF0000) != 0) || (IX_ETH_DB_GET_VLAN_ID(vlanTag) > 4094)) return IX_ETH_DB_INVALID_VLAN; }
-
-#define IX_ETH_DB_CHECK_VLAN_ID(vlanId) { if (vlanId > IX_ETH_DB_802_1Q_MAX_VLAN_ID) return IX_ETH_DB_INVALID_VLAN; }
-
-#define IX_IEEE802_1Q_VLAN_TPID (0x8100)
-    
-typedef enum
-{
-  IX_ETH_DB_UNTAGGED_FRAMES        = 0x1, /**< Accepts untagged frames */
-  IX_ETH_DB_VLAN_TAGGED_FRAMES     = 0x2, /**< Accepts tagged frames */
-  IX_ETH_DB_PRIORITY_TAGGED_FRAMES = 0x4, /**< Accepts tagged frames with VLAN ID set to 0 (no VLAN membership) */
-  IX_ETH_DB_ACCEPT_ALL_FRAMES      = 
-      IX_ETH_DB_UNTAGGED_FRAMES | IX_ETH_DB_VLAN_TAGGED_FRAMES /**< Accepts all the frames */
-} IxEthDBFrameFilter;
-
-typedef enum
-{
-  IX_ETH_DB_PASS_THROUGH = 0x1, /**< Leave frame as-is */
-  IX_ETH_DB_ADD_TAG      = 0x2, /**< Add default port VLAN tag */
-  IX_ETH_DB_REMOVE_TAG   = 0x3  /**< Remove VLAN tag from frame */
-} IxEthDBTaggingAction;
-
-typedef enum
-{
-  IX_ETH_DB_FIREWALL_WHITE_LIST = 0x1,  /**< Firewall operates in white-list mode (MAC address based admission) */
-  IX_ETH_DB_FIREWALL_BLACK_LIST = 0x2   /**< Firewall operates in black-list mode (MAC address based blocking) */
-} IxEthDBFirewallMode;
-  
-typedef enum
-{
-  IX_ETH_DB_FILTERING_RECORD        = 0x01, /**< <table><caption> Filtering record </caption> 
-                                             *      <tr><td> MAC address <td> static/dynamic type <td> age 
-                                             *   </table> 
-                                             */
-  IX_ETH_DB_FILTERING_VLAN_RECORD   = 0x02, /**< <table><caption> VLAN-enabled filtering record </caption>
-                                             *      <tr><td> MAC address <td> static/dynamic type <td> age <td> 802.1Q tag 
-                                             *   </table> 
-                                             */
-  IX_ETH_DB_WIFI_RECORD             = 0x04, /**< <table><caption> WiFi header conversion record </caption>
-                                             *      <tr><td> MAC address <td> optional gateway MAC address <td> 
-                                             *   </table>
-                                             */
-  IX_ETH_DB_FIREWALL_RECORD         = 0x08, /**< <table><caption> Firewall record </caption>
-                                             *      <tr><td> MAC address 
-                                             *   </table>
-                                             */
-  IX_ETH_DB_GATEWAY_RECORD          = 0x10, /**< <i>For internal use only</i> */
-  IX_ETH_DB_MAX_RECORD_TYPE_INDEX   = 0x10, /**< <i>For internal use only</i> */
-  IX_ETH_DB_NO_RECORD_TYPE          = 0,    /**< None of the registered record types */
-  IX_ETH_DB_ALL_FILTERING_RECORDS   = IX_ETH_DB_FILTERING_RECORD | IX_ETH_DB_FILTERING_VLAN_RECORD, /**< All the filtering records */
-  IX_ETH_DB_ALL_RECORD_TYPES        = IX_ETH_DB_FILTERING_RECORD | IX_ETH_DB_FILTERING_VLAN_RECORD |
-      IX_ETH_DB_WIFI_RECORD | IX_ETH_DB_FIREWALL_RECORD /**< All the record types registered within EthDB */    
-} IxEthDBRecordType;
-  
-typedef enum
-{
-  IX_ETH_DB_LEARNING                = 0x01, /**< Learning feature; enables EthDB to learn MAC address (filtering) records, including 802.1Q enabled records */
-  IX_ETH_DB_FILTERING               = 0x02, /**< Filtering feature; enables EthDB to communicate with the NPEs for downloading filtering information in the NPEs; depends on the learning feature */
-  IX_ETH_DB_VLAN_QOS                = 0x04, /**< VLAN/QoS feature; enables EthDB to configure NPEs to operate in VLAN/QoS aware modes */
-  IX_ETH_DB_FIREWALL                = 0x08, /**< Firewall feature; enables EthDB to configure NPEs to operate in firewall mode, using white/black address lists */
-  IX_ETH_DB_SPANNING_TREE_PROTOCOL  = 0x10, /**< Spanning tree protocol feature; enables EthDB to configure the NPEs as STP nodes */
-  IX_ETH_DB_WIFI_HEADER_CONVERSION  = 0x20  /**< WiFi 802.3 to 802.11 header conversion feature; enables EthDB to handle WiFi conversion data */
-} IxEthDBFeature;
-  
-typedef UINT32 IxEthDBProperty;  /**< Property ID type */
-
-typedef enum
-{
-  IX_ETH_DB_INTEGER_PROPERTY  = 0x1, /**< 4 byte unsigned integer type */
-  IX_ETH_DB_STRING_PROPERTY   = 0x2, /**< NULL-terminated string type of maximum 255 characters (including the terminator) */
-  IX_ETH_DB_MAC_ADDR_PROPERTY = 0x3, /**< 6 byte MAC address type */
-  IX_ETH_DB_BOOL_PROPERTY     = 0x4  /**< 4 byte boolean type; can contain only true and false values */
-} IxEthDBPropertyType;
-
-/* list of supported properties for the IX_ETH_DB_VLAN_QOS feature */
-#define IX_ETH_DB_QOS_TRAFFIC_CLASS_COUNT_PROPERTY   (0x01)     /**< Property identifying number the supported number of traffic classes */
-#define IX_ETH_DB_QOS_TRAFFIC_CLASS_0_RX_QUEUE_PROPERTY (0x10)  /**< Rx queue assigned to traffic class 0 */
-#define IX_ETH_DB_QOS_TRAFFIC_CLASS_1_RX_QUEUE_PROPERTY (0x11)  /**< Rx queue assigned to traffic class 1 */
-#define IX_ETH_DB_QOS_TRAFFIC_CLASS_2_RX_QUEUE_PROPERTY (0x12)  /**< Rx queue assigned to traffic class 2 */
-#define IX_ETH_DB_QOS_TRAFFIC_CLASS_3_RX_QUEUE_PROPERTY (0x13)  /**< Rx queue assigned to traffic class 3 */
-#define IX_ETH_DB_QOS_TRAFFIC_CLASS_4_RX_QUEUE_PROPERTY (0x14)  /**< Rx queue assigned to traffic class 4 */
-#define IX_ETH_DB_QOS_TRAFFIC_CLASS_5_RX_QUEUE_PROPERTY (0x15)  /**< Rx queue assigned to traffic class 5 */
-#define IX_ETH_DB_QOS_TRAFFIC_CLASS_6_RX_QUEUE_PROPERTY (0x16)  /**< Rx queue assigned to traffic class 6 */
-#define IX_ETH_DB_QOS_TRAFFIC_CLASS_7_RX_QUEUE_PROPERTY (0x17)  /**< Rx queue assigned to traffic class 7 */
-
-/* private property used by EthAcc to indicate queue configuration complete */
-#define IX_ETH_DB_QOS_QUEUE_CONFIGURATION_COMPLETE (0x18)
-      
-/**
- *
- * @brief The IEEE 802.3 Ethernet MAC address structure.
- * 
- * The data should be packed with bytes xx:xx:xx:xx:xx:xx 
- *
- * @note The data must be packed in network byte order.
- */
-typedef struct  
-{
-   UINT8 macAddress[IX_IEEE803_MAC_ADDRESS_SIZE];
-} IxEthDBMacAddr;
-
-/**
- * @ingroup IxEthDB
- *
- * @brief Definition of an IXP400 port.
- */
-typedef UINT32 IxEthDBPortId;
-
-/**
- * @ingroup IxEthDB
- *
- * @brief Port dependency map definition
- */
-typedef UINT8 IxEthDBPortMap[32];
-    
-/**
- * @ingroup IxEthDB
- *
- * @fn IxEthDBStatus ixEthDBInit(void)
- *
- * @brief Initializes the Ethernet learning/filtering database
- *
- * @note calling this function multiple times does not constitute an error;
- * redundant calls will be ignored, returning IX_ETH_DB_SUCCESS
- *
- * @retval IX_ETH_DB_SUCCESS initialization was successful
- * @retval IX_ETH_DB_FAIL initialization failed (OS error)
- */
-IX_ETH_DB_PUBLIC 
-IxEthDBStatus ixEthDBInit(void);
- 
-/**
- * @ingroup IxEthDB
- *
- * @fn IxEthDBStatus ixEthDBUnload(void)
- *
- * @brief Stops and prepares the EthDB component for unloading.
- *
- * @retval IX_ETH_DB_SUCCESS de-initialization was successful
- * @retval IX_ETH_DB_BUSY de-initialization failed, ports must be disabled first
- * @retval IX_ETH_DB_FAIL de-initialization failed (OS error)
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBUnload(void);
-
-/**
- * @ingroup IxEthDB
- *
- * @fn void ixEthDBPortInit(IxEthDBPortId portID)
- *
- * @brief Initializes a port
- *
- * This function is called automatically by the Ethernet Access
- * ixEthAccPortInit() routine for Ethernet NPE ports and should be manually
- * called for any user-defined port (any port that is not one of
- * the two Ethernet NPEs). 
- *
- * @param portID @ref IxEthDBPortId [in] - ID of the port to be initialized
- *
- * @see IxEthDBPortDefs.h for port definitions
- *
- * @note calling this function multiple times does not constitute an error;
- * redundant calls will be ignored
- */
-IX_ETH_DB_PUBLIC 
-void ixEthDBPortInit(IxEthDBPortId portID);
-
-/**
- * @ingroup IxEthDB
- *
- * @fn IxEthDBStatus ixEthDBPortEnable(IxEthDBPortId portID)
- *
- * @brief Enables a port
- *
- * This function is called automatically from the Ethernet Access component
- * ixEthAccPortEnable() routine for Ethernet NPE ports and should be manually
- * called for any user-defined port (any port that is not one of
- * the Ethernet NPEs). 
- *
- * @param portID @ref IxEthDBPortId [in] - ID of the port to enable processing on
- *
- * @retval IX_ETH_DB_SUCCESS if enabling is successful
- * @retval IX_ETH_DB_FAIL if the enabling was not successful due to
- * a message handler error
- * @retval IX_ETH_DB_MAC_UNINITIALIZED the MAC address of this port was
- * not initialized (only for Ethernet NPEs)
- * @retval IX_ETH_DB_INVALID_PORT if portID is invalid
- *
- * @pre ixEthDBPortAddressSet needs to be called prior to enabling the port events
- * for Ethernet NPEs
- *
- * @see ixEthDBPortAddressSet
- *
- * @see IxEthDBPortDefs.h for port definitions
- *
- * @note calling this function multiple times does not constitute an error;
- * redundant calls will be ignored
- */
-IX_ETH_DB_PUBLIC 
-IxEthDBStatus ixEthDBPortEnable(IxEthDBPortId portID);
-
-/**
- * @ingroup IxEthDB
- *
- * @fn IxEthDBStatus ixEthDBPortDisable(IxEthDBPortId portID)
- *
- * @brief Disables processing on a port
- *
- * This function is called automatically from the Ethernet Access component
- * ixEthAccPortDisable() routine for Ethernet NPE ports and should be manually
- * called for any user-defined port (any port that is not one of
- * the Ethernet NPEs).
- *
- * @note Calling ixEthAccPortDisable() will disable the respective Ethernet NPE.
- * After Ethernet NPEs are disabled they are stopped therefore
- * when re-enabled they need to be reset, downloaded with microcode and started.
- * For learning to restart working the user needs to call again 
- * ixEthAccPortUnicastMacAddressSet or ixEthDBUnicastAddressSet
- * with the respective port MAC address.
- * Residual MAC addresses learnt before the port was disabled are deleted as soon
- * as the port is disabled. This only applies to dynamic (learnt) entries, static
- * entries do not dissapear when the port is disabled.
- *
- * @param portID @ref IxEthDBPortId [in] - ID of the port to disable processing on
- *
- * @retval IX_ETH_DB_SUCCESS if disabling is successful
- * @retval IX_ETH_DB_FAIL if the disabling was not successful due to
- * a message handler error
- * @retval IX_ETH_DB_INVALID_PORT if portID is invalid
- *
- * @note calling this function multiple times after the first time completed successfully
- * does not constitute an error; redundant calls will be ignored and return IX_ETH_DB_SUCCESS
-*/
-IX_ETH_DB_PUBLIC 
-IxEthDBStatus ixEthDBPortDisable(IxEthDBPortId portID);
-
-/**
- * @ingroup IxEthDB
- *
- * @fn IxEthDBStatus ixEthDBPortAddressSet(IxEthDBPortId portID, IxEthDBMacAddr *macAddr)
- *
- * @brief Sets the port MAC address
- *
- * This function is to be called from the Ethernet Access component top-level
- * ixEthDBUnicastAddressSet(). Event processing cannot be enabled for a port
- * until its MAC address has been set.
- *
- * @param portID @ref IxEthDBPortId [in] - ID of the port whose MAC address is set
- * @param macAddr @ref IxEthDBMacAddr [in] - port MAC address
- *
- * @retval IX_ETH_DB_SUCCESS MAC address was set successfully
- * @retval IX_ETH_DB_FAIL MAC address was not set due to a message handler failure
- * @retval IX_ETH_DB_INVALID_PORT if the port is not an Ethernet NPE
- *
- * @see IxEthDBPortDefs.h for port definitions
- */
-IX_ETH_DB_PUBLIC 
-IxEthDBStatus ixEthDBPortAddressSet(IxEthDBPortId portID, IxEthDBMacAddr *macAddr);
-
-/**
- * @ingroup IxEthDB
- *
- * @fn IxEthDBStatus ixEthDBFilteringPortMaximumFrameSizeSet(IxEthDBPortId portID, UINT32 maximumFrameSize)
- *
- * @brief Set the maximum frame size supported on the given port ID
- *
- * This functions set the maximum frame size supported on a specific port ID 
- * 
- * - Reentrant    - yes
- * - ISR Callable - no
- *
- * @param portID @ref IxEthDBPortId [in] - port ID to configure
- * @param maximumFrameSize UINT32 [in] - maximum frame size to configure
- *
- * @retval IX_ETH_DB_SUCCESS the port is configured
- * @retval IX_ETH_DB_PORT_UNINITIALIZED the port has not been initialized
- * @retval IX_ETH_DB_INVALID_PORT portID is invalid
- * @retval IX_ETH_DB_INVALID_ARG size parameter is out of range
- * @retval IX_ETH_DB_NO_PERMISSION selected port is not an Ethernet NPE
- * @retval IX_FAIL unknown OS or NPE communication error
- *
- * @note
- * This maximum frame size is used to filter the frames based on their
- * destination addresses and the capabilities of the destination port.
- * The mximum value that can be set for a NPE port is 16320.
- * (IX_ETHNPE_ACC_FRAME_LENGTH_MAX)
- */
-IX_ETH_DB_PUBLIC 
-IxEthDBStatus ixEthDBFilteringPortMaximumFrameSizeSet(IxEthDBPortId portID, UINT32 maximumFrameSize);
-
-/**
- * @ingroup IxEthDB
- *
- * @fn IxEthDBStatus ixEthDBFilteringStaticEntryProvision(IxEthDBPortId portID, IxEthDBMacAddr *macAddr)
- *
- * @brief Populate the Ethernet learning/filtering database with a static MAC address
- *
- * Populates the Ethernet learning/filtering database with a static MAC address. The entry will not be subject to aging.
- * If there is an entry (static or dynamic) with the corresponding MAC address on any port this entry will take precedence.
- * Any other entry with the same MAC address will be removed.
- *
- * - Reentrant    - yes
- * - ISR Callable - yes
- * 
- * @param portID @ref IxEthDBPortId [in] - port ID to add the static address to
- * @param macAddr @ref IxEthDBMacAddr [in] - static MAC address to add
- * 
- * @retval IX_ETH_DB_SUCCESS the add was successful
- * @retval IX_ETH_DB_FAIL failed to populate the database entry
- * @retval IX_ETH_DB_BUSY failed due to a temporary busy condition (i.e. lack of CPU cycles), try again later
- * @retval IX_ETH_DB_INVALID_PORT portID is invalid
- * @retval IX_ETH_DB_PORT_UNINITIALIZED port is not initialized
- * @retval IX_ETH_DB_INVALID_ARG invalid <i>macAddr</i> pointer argument
- * @retval IX_ETH_DB_FEATURE_UNAVAILABLE learning feature is disabled
- */
-IX_ETH_DB_PUBLIC 
-IxEthDBStatus ixEthDBFilteringStaticEntryProvision(IxEthDBPortId portID, IxEthDBMacAddr *macAddr);
-
-/**
- * @ingroup IxEthDB
- *
- * @fn IxEthDBStatus ixEthDBFilteringDynamicEntryProvision(IxEthDBPortId portID, IxEthDBMacAddr *macAddr)
- *
- * @brief Populate the Ethernet learning/filtering database with a dynamic MAC address
- *
- * Populates the Ethernet learning/filtering database with a dynamic MAC address. This entry will be subject to normal 
- * aging function, if aging is enabled on its port.
- * If there is an entry (static or dynamic) with the same MAC address on any port this entry will take precedence.
- * Any other entry with the same MAC address will be removed.
- *
- * - Reentrant    - yes
- * - ISR Callable - yes
- *
- * @param portID @ref IxEthDBPortId [in] - port ID to add the dynamic address to
- * @param macAddr @ref IxEthDBMacAddr [in] - static MAC address to add
- *
- * @retval IX_ETH_DB_SUCCESS the add was successful
- * @retval IX_ETH_DB_FAIL failed to populate the database entry
- * @retval IX_ETH_DB_BUSY failed due to a temporary busy condition (i.e. lack of CPU cycles), try again later
- * @retval IX_ETH_DB_INVALID_PORT portID is invalid
- * @retval IX_ETH_DB_PORT_UNINITIALIZED port is not initialized
- * @retval IX_ETH_DB_INVALID_ARG invalid <i>macAddr</i> pointer argument
- * @retval IX_ETH_DB_FEATURE_UNAVAILABLE learning feature is disabled
- */
-IX_ETH_DB_PUBLIC 
-IxEthDBStatus ixEthDBFilteringDynamicEntryProvision(IxEthDBPortId portID, IxEthDBMacAddr *macAddr);
-
-/**
- * @ingroup IxEthDB
- *
- * @fn IxEthDBStatus ixEthDBFilteringEntryDelete(IxEthDBMacAddr *macAddr)
- *
- * @brief Removes a MAC address entry from the Ethernet learning/filtering database
- *
- * @param macAddr IxEthDBMacAddr [in] - MAC address to remove
- *
- * - Reentrant    - yes
- * - ISR Callable - no
- *
- * @retval IX_ETH_DB_SUCCESS the removal was successful
- * @retval IX_ETH_DB_NO_SUCH_ADDR failed to remove the address (not in the database)
- * @retval IX_ETH_DB_INVALID_ARG invalid <i>macAddr</i> pointer argument
- * @retval IX_ETH_DB_BUSY failed due to a temporary busy condition (i.e. lack of CPU cycles), try again later
- */
-IX_ETH_DB_PUBLIC 
-IxEthDBStatus ixEthDBFilteringEntryDelete(IxEthDBMacAddr *macAddr);
-
-/**
- * @ingroup IxEthDB
- *
- * @fn IxEthDBStatus ixEthDBFilteringPortSearch(IxEthDBPortId portID, IxEthDBMacAddr *macAddr)
- *
- * @brief Search the Ethernet learning/filtering database for the given MAC address and port ID
- *
- * This functions searches the database for a specific port ID and MAC address. Both the port ID
- * and the MAC address have to match in order for the record to be reported as found.
- *
- * - Reentrant    - yes
- * - ISR Callable - no
- *
- * @param portID @ref IxEthDBPortId [in] - port ID to search for
- * @param macAddr @ref IxEthDBMacAddr [in] - MAC address to search for
- *
- * @retval IX_ETH_DB_SUCCESS the record exists in the database
- * @retval IX_ETH_DB_INVALID_ARG invalid macAddr pointer argument
- * @retval IX_ETH_DB_NO_SUCH_ADDR the record was not found in the database
- * @retval IX_ETH_DB_INVALID_PORT portID is invalid
- * @retval IX_ETH_DB_PORT_UNINITIALIZED port ID is not initialized
- * @retval IX_ETH_DB_FEATURE_UNAVAILABLE learning feature is disabled
- */
-IX_ETH_DB_PUBLIC 
-IxEthDBStatus ixEthDBFilteringPortSearch(IxEthDBPortId portID, IxEthDBMacAddr *macAddr);
-
-/**
- * @ingroup IxEthDB
- *
- * @fn IxEthDBStatus ixEthDBFilteringDatabaseSearch(IxEthDBPortId *portID, IxEthDBMacAddr *macAddr)
- *
- * @brief Search the Ethernet learning/filtering database for a MAC address and return the port ID
- *
- * Searches the database for a MAC address. The function returns the portID for the 
- * MAC address record, if found. If no match is found the function returns IX_ETH_DB_NO_SUCH_ADDR. 
- * The portID is only valid if the function finds a match.
- *
- * - Reentrant    - yes
- * - ISR Callable - no
- *
- * @param portID @ref IxEthDBPortId [in] - port ID the address belongs to (populated only on a successful search)
- * @param macAddr @ref IxEthDBMacAddr [in] - MAC address to search for
- *
- * @retval IX_ETH_DB_SUCCESS the record exists in the database
- * @retval IX_ETH_DB_NO_SUCH_ADDR the record was not found in the database
- * @retval IX_ETH_DB_INVALID_ARG invalid macAddr or portID pointer argument(s)
- */
-IX_ETH_DB_PUBLIC 
-IxEthDBStatus ixEthDBFilteringDatabaseSearch(IxEthDBPortId *portID, IxEthDBMacAddr *macAddr);
-
-/**
- * @ingroup IxEthDB
- *
- * @fn IxEthDBStatus ixEthDBFilteringPortUpdatingSearch(IxEthDBPortId *portID, IxEthDBMacAddr *macAddr)
- *
- * @brief Search the filtering database for a MAC address, return the port ID and reset the record age
- *
- * Searches the database for a MAC address. The function returns the portID for the 
- * MAC address record and resets the entry age to 0, if found. 
- * If no match is found the function returns IX_ETH_DB_NO_SUCH_ADDR. 
- * The portID is only valid if the function finds a match.
- *
- * - Reentrant      - yes
- * - ISR Callable   - no
- *
- * @retval IX_ETH_DB_SUCCESS the MAC address was found
- * @retval IX_ETH_DB_NO_SUCH_ADDR the MAC address was not found
- * @retval IX_ETH_DB_INVALID_ARG invalid macAddr or portID pointer argument(s)
- */
-IX_ETH_DB_PUBLIC 
-IxEthDBStatus ixEthDBFilteringPortUpdatingSearch(IxEthDBPortId *portID, IxEthDBMacAddr *macAddr);
-
-/**
- * @ingroup IxEthDB
- *
- * @def IX_ETH_DB_MAINTENANCE_TIME
- *
- * @brief The @ref ixEthDBDatabaseMaintenance must be called by the user at a frequency of 
- * IX_ETH_DB_MAINTENANCE_TIME
- *
- */
-#define IX_ETH_DB_MAINTENANCE_TIME (1 * 60) /* 1 Minute */
-
-/**
- * @ingroup IxEthDB
- *
- * @def IX_ETH_DB_LEARNING_ENTRY_AGE_TIME
- *
- * @brief The define specifies the filtering database age entry time. Static entries older than
- * IX_ETH_DB_LEARNING_ENTRY_AGE_TIME +/- IX_ETH_DB_MAINTENANCE_TIME shall be removed.
- *
- */
-#define IX_ETH_DB_LEARNING_ENTRY_AGE_TIME (15 * 60 ) /* 15 Mins */
-
-/**
- * @ingroup IxEthDB
- *
- * @fn IxEthDBStatus ixEthDBPortAgingDisable(IxEthDBPortId portID)
- *
- * @brief Disable the aging function for a specific port
- *
- * @param portID @ref IxEthDBPortId [in] - port ID to disable aging on
- *
- * - Reentrant    - yes
- * - ISR Callable - no
- *
- * @retval IX_ETH_DB_SUCCESS aging disabled successfully
- * @retval IX_ETH_DB_INVALID_PORT portID is invalid
- * @retval IX_ETH_DB_PORT_UNINITIALIZED port ID is not initialized
- * @retval IX_ETH_DB_FEATURE_UNAVAILABLE learning feature is disabled
- */
-IX_ETH_DB_PUBLIC 
-IxEthDBStatus ixEthDBPortAgingDisable(IxEthDBPortId portID);
-
-/**
- * @ingroup IxEthDB
- *
- * @fn IxEthDBStatus ixEthDBPortAgingEnable(IxEthDBPortId portID)
- *
- * @brief Enable the aging function for a specific port
- * 
- * Enables the aging of dynamic MAC address entries stored in the learning/filtering database
- * 
- * @note The aging function relies on the @ref ixEthDBDatabaseMaintenance being called with a period of 
- * @ref IX_ETH_DB_MAINTENANCE_TIME seconds.
- *
- * - Reentrant    - yes
- * - ISR Callable - no
- *
- * @param portID @ref IxEthDBPortId [in] - port ID to enable aging on
- *
- * @retval IX_ETH_DB_SUCCESS aging enabled successfully
- * @retval IX_ETH_DB_INVALID_PORT portID is invalid
- * @retval IX_ETH_DB_PORT_UNINITIALIZED port ID is not initialized
- * @retval IX_ETH_DB_FEATURE_UNAVAILABLE learning feature is disabled
- */
-IX_ETH_DB_PUBLIC 
-IxEthDBStatus ixEthDBPortAgingEnable(IxEthDBPortId portID);
-
-/**
- * @ingroup IxEthDB
- *
- * @fn void ixEthDBDatabaseMaintenance(void)
- *
- * @brief Performs a maintenance operation on the Ethernet learning/filtering database
- * 
- * In order to perform a database maintenance this function must be called every
- * @ref IX_ETH_DB_MAINTENANCE_TIME seconds. It should be called regardless of whether learning is
- * enabled or not.
- *
- * - Reentrant    - no
- * - ISR Callable - no
- * 
- * @note this function call will be ignored if the learning feature is disabled
- */
-IX_ETH_DB_PUBLIC 
-void ixEthDBDatabaseMaintenance(void);
-
-/**
- * @ingroup IxEthDB
- *
- * @fn IxEthDBStatus ixEthDBFilteringDatabaseShow(IxEthDBPortId  portID)
- *
- * @brief This function displays the Mac Ethernet MAC address filtering tables.
- *
- * It displays the MAC address, port ID, entry type (dynamic/static),and age for 
- * the given port ID.
- *
- * - Reentrant    - no
- * - ISR Callable - no
- *
- * @param portID @ref IxEthDBPortId [in] - port ID to display the MAC address entries
- *
- * @retval IX_ETH_DB_SUCCESS operation completed successfully
- * @retval IX_ETH_DB_INVALID_PORT portID is invalid
- * @retval IX_ETH_DB_PORT_UNINITIALIZED port ID is not initialized
- * @retval IX_ETH_DB_FAIL record browser failed due to an internal busy or lock condition
- *
- * @note this function is deprecated and kept for compatibility reasons; use @ref ixEthDBFilteringDatabaseShowRecords instead
- * 
- * @see ixEthDBFilteringDatabaseShowRecords
- */
-IX_ETH_DB_PUBLIC 
-IxEthDBStatus ixEthDBFilteringDatabaseShow(IxEthDBPortId portID);
-
-/** 
- * @ingroup IxEthDB
- *
- * @fn void ixEthDBFilteringDatabaseShowAll(void)
- *
- * @brief Displays the MAC address recorded in the filtering database for all registered
- * ports (see IxEthDBPortDefs.h), grouped by port ID.
- *
- * - Reentrant    - no
- * - ISR Callable - no
- *
- * @retval void
- *
- * @note this function is deprecated and kept for compatibility reasons; use @ref ixEthDBFilteringDatabaseShowRecords instead
- * 
- * @see ixEthDBFilteringDatabaseShowRecords
- */
-IX_ETH_DB_PUBLIC 
-void ixEthDBFilteringDatabaseShowAll(void);
-
-/**
- * @ingroup IxEthDB
- *
- * @fn IxEthDBStatus ixEthDBFilteringDatabaseShowRecords(IxEthDBPortId portID, IxEthDBRecordType recordFilter)
- *
- * @brief This function displays per port database records, given a record type filter
- *
- * The supported record type filters are:
- * 
- * - IX_ETH_DB_FILTERING_RECORD - displays the non-VLAN filtering records (MAC address, age, static/dynamic)
- * - IX_ETH_DB_FILTERING_VLAN_RECORD - displays the VLAN filtering records (MAC address, age, static/dynamic, VLAN ID, CFI, QoS class)
- * - IX_ETH_DB_FILTERING_RECORD | IX_ETH_DB_FILTERING_VLAN_RECORD - displays the previous two types of records
- * - IX_ETH_DB_WIFI_RECORD - displays the WiFi header conversion records (MAC address, optional gateway MAC address) and WiFi header conversion parameters (BBSID, Duration/ID)
- * - IX_ETH_DB_FIREWALL_RECORD - displays the firewall MAC address table and firewall operating mode (white list/black list)
- * - IX_ETH_DB_ALL_RECORD_TYPES - displays all the record types
- * - IX_ETH_DB_NO_RECORD_TYPE - displays only the port status (no records are displayed)
- * 
- * Additionally, the status of each port will be displayed, containg the following information: type, capabilities, enabled status, 
- * aging enabled status, group membership and maximum frame size.
- *
- * The port ID can either be an actual port or IX_ETH_DB_ALL_PORTS, in which case the requested information
- * will be displayed for all the ports (grouped by port)
- *
- * - Reentrant    - no
- * - ISR Callable - no
- *
- * @param portID ID of the port to display information on (use IX_ETH_DB_ALL_PORTS for all the ports)
- * @param recordFilter record type filter
- *
- * @retval IX_ETH_DB_SUCCESS operation completed successfully
- * @retval IX_ETH_DB_INVALID_PORT portID is invalid
- * @retval IX_ETH_DB_PORT_UNINITIALIZED port ID is not initialized
- */
-IX_ETH_DB_PUBLIC 
-IxEthDBStatus ixEthDBFilteringDatabaseShowRecords(IxEthDBPortId portID, IxEthDBRecordType recordFilter);
-
-/**
- * @ingroup IxEthDB
- *
- * @fn IxEthDBStatus ixEthDBPortDependencyMapSet(IxEthDBPortId portID, IxEthDBPortMap dependencyPortMap)
- *
- * @brief Sets the dependency port map for a port
- *
- * @param portID ID of the port to set the dependency map to
- * @param dependencyPortMap new dependency map (as bitmap, each bit set indicates a port being included)
- *
- * This function is used to share filtering information between ports.
- * By adding a port into another port's dependency map the target port
- * filtering data will import the filtering data from the port it depends on.
- * Any changes to filtering data for a port - such as adding, updating or removing records -
- * will trigger updates in the filtering information for all the ports depending on
- * on the updated port.
- *
- * For example, if ports 2 and 3 are set in the port 0 dependency map the filtering
- * information for port 0 will also include the filtering information from ports 2 and 3.
- * Adding a record to port 2 will also trigger an update not only on port 2 but also on
- * port 0.
- *
- * The dependency map is a 256 bit array where each bit corresponds to a port corresponding to the
- * bit offset (bit 0 - port 0, bit 1 - port 1 etc). Setting a bit to 1 indicates that the corresponding
- * port is the port map. For example, a dependency port map of 0x14 consists in the ports with IDs 2 and 4.
- * Note that the last bit (offset 255) is reserved and should never be set (it will be automatically
- * cleared by the function).
- *
- * By default, each port has a dependency port map consisting only of itself, i.e. 
- *
- * @verbatim
-    IxEthDBPortMap portMap;
-    
-    // clear all ports from port map
-    memset(portMap, 0, sizeof (portMap)); 
-    
-    // include portID in port map 
-    portMap[portID / 8] = 1 << (portID % 8);
-   @endverbatim
- *
- * - Reentrant    - no
- * - ISR Callable - no
- *
- * @note Setting dependency maps is useful for NPE ports, which benefit from automatic updates
- * of filtering information. Setting dependency maps for user-defined ports is not an error
- * but will have no actual effect.
- * 
- * @note Including a port in its own dependency map is not compulsory, however note that
- * in this case updating the port will not trigger an update on the port itself, which 
- * might not be the intended behavior
- *
- * @retval IX_ETH_DB_SUCCESS operation completed successfully
- * @retval IX_ETH_DB_INVALID_PORT portID is not a valid port identifier
- * @retval IX_ETH_DB_PORT_UNINITIALIZED port is not initialized
- * @retval IX_ETH_DB_INVALID_ARG invalid <i>dependencyPortMap</i> pointer
- * @retval IX_ETH_DB_FEATURE_UNAVAILABLE Filtering is not available or not enabled for the port
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBPortDependencyMapSet(IxEthDBPortId portID, IxEthDBPortMap dependencyPortMap);
-
-/**
- * @ingroup IxEthDB
- *
- * @fn IxEthDBStatus ixEthDBPortDependencyMapGet(IxEthDBPortId portID, IxEthDBPortMap dependencyPortMap)
- *
- * @brief Retrieves the dependency port map for a port
- *
- * @param portID ID of the port to set the dependency map to
- * @param dependencyPortMap location where the port dependency map is to be copied
- *
- * This function will copy the port dependency map to a user specified location.
- *
- * - Reentrant    - no
- * - ISR Callable - no
- *
- * @retval IX_ETH_DB_SUCCESS operation completed successfully
- * @retval IX_ETH_DB_INVALID_PORT portID is not a valid port identifier
- * @retval IX_ETH_DB_PORT_UNINITIALIZED port is not initialized
- * @retval IX_ETH_DB_INVALID_ARG invalid <i>dependencyPortMap</i> pointer
- * @retval IX_ETH_DB_FEATURE_UNAVAILABLE Filtering is not available or not enabled for the port
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBPortDependencyMapGet(IxEthDBPortId portID, IxEthDBPortMap dependencyPortMap);
-
-/**
- * @ingroup IxEthDB
- *
- * @fn IxEthDBStatus ixEthDBPortVlanTagSet(IxEthDBPortId portID, IxEthDBVlanTag vlanTag)
- *
- * @brief Sets the default 802.1Q VLAN tag for a given port
- *
- * @param portID @ref IxEthDBPortId [in] - ID of the port to set the default VLAN tag to
- * @param vlanTag @ref IxEthDBVlanTag [in] - default 802.1Q VLAN tag
- *
- * The tag format has 16 bits and it is defined in the IEEE802.1Q specification.
- * This tag will be used for tagging untagged frames (if enabled) and classifying
- * unexpedited traffic into an internal traffic class (using the user priority field).
- *
- * <table border="1"> <caption> 802.1Q tag format </caption>
- *    <tr> <td>  <b> 3 bits   <td> <b> 1 bit <td> <b> 12 bits </b>
- *    <tr> <td> user priority <td>  CFI  <td>   VID
- * </table>
- *
- * User Priority : Defines user priority, giving eight (2^3) priority levels. IEEE 802.1P defines 
- * the operation for these 3 user priority bits
- * 
- * CFI : Canonical Format Indicator is always set to zero for Ethernet switches. CFI is used for 
- * compatibility reason between Ethernet type network and Token Ring type network. If a frame received 
- * at an Ethernet port has a CFI set to 1, then that frame should not be forwarded as it is to an untagged port. 
- *
- * VID : VLAN ID is the identification of the VLAN, which is basically used by the standard 802.1Q. 
- * It has 12 bits and allow the id entification of 4096 (2^12) VLANs. Of the 4096 possible VIDs, a VID of 0 
- * is used to identify priority frames and value 4095 (FFF) is reserved, so the maximum possible VLAN 
- * configurations are 4,094.
- * 
- * - Reentrant    - no
- * - ISR Callable - no
- *
- * @retval IX_ETH_DB_SUCCESS operation completed successfully
- * @retval IX_ETH_DB_INVALID_PORT portID is not a valid port identifier
- * @retval IX_ETH_DB_PORT_UNINITIALIZED port is not initialized
- * @retval IX_ETH_DB_FEATURE_UNAVAILABLE VLAN/QoS feature is not available or not enabled for the port
- * @retval IX_ETH_DB_INVALID_VLAN <i>vlanTag</i> argument does not parse to a valid 802.1Q VLAN tag
- *
- * @note a VLAN ID value of 0 indicates that the port is not part of any VLAN
- * @note the value of the cannonical frame indicator (CFI) field is ignored, the 
- * field being used only in frame tagging operations
- */
-IX_ETH_DB_PUBLIC 
-IxEthDBStatus ixEthDBPortVlanTagSet(IxEthDBPortId portID, IxEthDBVlanTag vlanTag);
-
-/**
- * @ingroup IxEthDB
- *
- * @fn IxEthDBStatus ixEthDBPortVlanTagGet(IxEthDBPortId portID, IxEthDBVlanTag *vlanTag)
- *
- * @brief Retrieves the default 802.1Q port VLAN tag for a given port (see also @ref ixEthDBPortVlanTagSet)
- *
- * @param portID @ref IxEthDBPortId [in] - ID of the port to retrieve the default VLAN tag from
- * @param vlanTag @ref IxEthDBVlanTag [out] - location to write the default port 802.1Q VLAN tag to
- *
- * - Reentrant    - no
- * - ISR Callable - no
- *
- * @retval IX_ETH_DB_SUCCESS operation completed successfully
- * @retval IX_ETH_DB_INVALID_PORT portID is not a valid port identifier
- * @retval IX_ETH_DB_PORT_UNINITIALIZED port is not initialized
- * @retval IX_ETH_DB_INVALID_ARG invalid vlanTag pointer
- * @retval IX_ETH_DB_FEATURE_UNAVAILABLE VLAN/QoS feature is not available or not enabled for the port
- */
-IX_ETH_DB_PUBLIC 
-IxEthDBStatus ixEthDBPortVlanTagGet(IxEthDBPortId portID, IxEthDBVlanTag *vlanTag);
-
-/**
- * @ingroup IxEthDB
- *
- * @fn IxEthDBStatus ixEthDBVlanTagSet(IxEthDBMacAddr *macAddr, IxEthDBVlanTag vlanTag)
- *
- * @brief Sets the 802.1Q VLAN tag for a database record
- *
- * @param macAddr MAC address
- * @param vlanTag 802.1Q VLAN tag
- *
- * This function is used together with @ref ixEthDBVlanTagGet to provide MAC-based VLAN classification support.
- * Please note that the bridging application must contain specific code to make use of this feature (see below).
- * 
- * VLAN tags can be set only in IX_ETH_DB_FILTERING_RECORD or IX_ETH_DB_FILTERING_VLAN_RECORD type records.
- * If to an IX_ETH_DB_FILTERING_RECORD type record is added a VLAN tag the record type is automatically
- * changed to IX_ETH_DB_FILTERING_VLAN_RECORD. Once this has occurred the record type will never
- * revert to a non-VLAN type (unless deleted and re-added).
- *
- * Record types used for different purposes (such as IX_ETH_DB_WIFI_RECORD) will be ignored by
- * this function.
- *
- * After using this function to associate a VLAN ID with a MAC address the VLAN ID can be extracted knowing the
- * MAC address using @ref ixEthDBVlanTagGet. This mechanism can be used to implement MAC-based VLAN classification
- * if a bridging application searches for the VLAN tag when receiving a frame based on the source MAC address 
- * (contained in the <i>ixp_ne_src_mac</i> field of the buffer header).
- * If found in the database, the application can instruct the NPE to tag the frame by writing the VLAN tag
- * in the <i>ixp_ne_vlan_tci</i> field of the buffer header. This way the NPE will inspect the Egress tagging
- * rule associated with the given VLAN ID on the Tx port and tag the frame if Egress tagging on the VLAN is
- * allowed. Additionally, Egress tagging can be forced by setting the <i>ixp_ne_tx_flags.tag_over</i> and 
- * <i>ixp_ne_tx_flags.tag_mode</i> flags in the buffer header.
- *
- * - Reentrant    - no
- * - ISR Callable - no
- *
- * @note this function will <b>not</b> add a filtering record, it can only be used to update an existing one
- * 
- * @retval IX_ETH_DB_SUCCESS operation completed successfully
- * @retval IX_ETH_DB_INVALID_ARG invalid <i>macAddr</i> pointer
- * @retval IX_ETH_DB_NO_SUCH_ADDR a filtering record with the specified MAC address was not found
- * @retval IX_ETH_DB_INVALID_VLAN <i>vlanTag</i> argument does not parse to a valid 802.1Q VLAN tag
- */
-IX_ETH_DB_PUBLIC 
-IxEthDBStatus ixEthDBVlanTagSet(IxEthDBMacAddr *macAddr, IxEthDBVlanTag vlanTag);
-
-/**
- * @ingroup IxEthDB
- *
- * @fn ixEthDBVlanTagGet(IxEthDBMacAddr *macAddr, IxEthDBVlanTag *vlanTag)
- *
- * @brief Retrieves the 802.1Q VLAN tag from a database record given the record MAC address
- *
- * @param macAddr MAC address
- * @param vlanTag location to write the record 802.1Q VLAN tag to
- *
- * @note VLAN tags can be retrieved only from IX_ETH_DB_FILTERING_VLAN_RECORD type records
- * 
- * This function is used together with ixEthDBVlanTagSet to provide MAC-based VLAN classification support.
- * Please note that the bridging application must contain specific code to make use of this feature (see @ref ixEthDBVlanTagSet).
- *
- * - Reentrant    - no
- * - ISR Callable - no
- *
- * @retval IX_ETH_DB_SUCCESS operation completed successfully
- * @retval IX_ETH_DB_INVALID_ARG invalid <i>macAddr</i> or <i>vlanTag</i> pointer
- * @retval IX_ETH_DB_NO_SUCH_ADDR a filtering record with the specified MAC address was not found
- */
-IX_ETH_DB_PUBLIC 
-IxEthDBStatus ixEthDBVlanTagGet(IxEthDBMacAddr *macAddr, IxEthDBVlanTag *vlanTag);
-
-/**
- * @ingroup IxEthDB
- *
- * @fn IxEthDBStatus ixEthDBPortVlanMembershipAdd(IxEthDBPortId portID, IxEthDBVlanId vlanID)
- *
- * @brief Adds a VLAN ID to a port's VLAN membership table
- *
- * Adding a VLAN ID to a port's VLAN membership table will cause frames tagged with the specified 
- * VLAN ID to be accepted by the frame filter, if Ingress VLAN membership filtering is enabled.
- * 
- * - Reentrant    - no
- * - ISR Callable - no
- *
- * @param portID @ref IxEthDBPortId [in] - ID of the port to add the VLAN ID membership to
- * @param vlanID @ref IxEthDBVlanId [in] - VLAN ID to be added to the port membership table
- *
- * @retval IX_ETH_DB_SUCCESS operation completed successfully
- * @retval IX_ETH_DB_INVALID_PORT portID is not a valid port identifier
- * @retval IX_ETH_DB_PORT_UNINITIALIZED port is not initialized
- * @retval IX_ETH_DB_INVALID_VLAN vlanID is not a valid VLAN ID
- * @retval IX_ETH_DB_FEATURE_UNAVAILABLE VLAN/QoS feature is not available or not enabled for the port
- * @retval IX_FAIL unknown OS or NPE communication error
- *
- * @note A port's default VLAN ID is always in its own membership table, hence there
- * is no need to explicitly add it using this function (although it is not an error
- * to do so)
- */
-IX_ETH_DB_PUBLIC 
-IxEthDBStatus ixEthDBPortVlanMembershipAdd(IxEthDBPortId portID, IxEthDBVlanId vlanID);
-
-/**
- * @ingroup IxEthDB
- *
- * @fn IxEthDBStatus ixEthDBPortVlanMembershipRangeAdd(IxEthDBPortId portID, IxEthDBVlanId vlanIDMin, IxEthDBVlanId vlanIDMax)
- *
- * @brief Adds a VLAN ID range to a port's VLAN membership table
- *
- * All the VLAN IDs in the specified range will be added to the port VLAN
- * membership table, including the range start and end VLAN IDs. Tagged frames with
- * VLAN IDs in the specified range will be accepted by the frame filter, if Ingress VLAN
- * membership filtering is enabled.
- *
- * - Reentrant    - no
- * - ISR Callable - no
- *
- * @param portID @ref IxEthDBPortId [in] - port ID to add the VLAN membership range into
- * @param vlanIDMin @ref IxEthDBVlanId [in] - start of the VLAN ID range
- * @param vlanIDMax @ref IxEthDBVlanId [in] - end of the VLAN ID range
- *
- * @retval IX_ETH_DB_SUCCESS operation completed successfully
- * @retval IX_ETH_DB_INVALID_PORT portID is not a valid port identifier
- * @retval IX_ETH_DB_PORT_UNINITIALIZED port is not initialized
- * @retval IX_ETH_DB_INVALID_VLAN the specified VLAN IDs are invalid or do not constitute a range
- * @retval IX_ETH_DB_FEATURE_UNAVAILABLE VLAN/QoS feature is not available or not enabled for the port
- * @retval IX_FAIL unknown OS or NPE communication error
- *
- * @note Is is valid to use the same VLAN ID for both vlanIDMin and vlanIDMax, in which case this
- * function will behave as @ref ixEthDBPortVlanMembershipAdd
- *
- * @note A port's default VLAN ID is always in its own membership table, hence there is no need
- * to explicitly add it using this function (although it is not an error to do so)
- */
-IX_ETH_DB_PUBLIC 
-IxEthDBStatus ixEthDBPortVlanMembershipRangeAdd(IxEthDBPortId portID, IxEthDBVlanId vlanIDMin, IxEthDBVlanId vlanIDMax);
-
-/**
- * @ingroup IxEthDB
- *
- * @fn IxEthDBStatus ixEthDBPortVlanMembershipRemove(IxEthDBPortId portID, IxEthDBVlanId vlanID)
- *
- * @brief Removes a VLAN ID from a port's VLAN membership table
- *
- * Frames tagged with a VLAN ID which is not in a port's VLAN membership table
- * will be discarded by the frame filter, if Ingress membership filtering is enabled.
- *
- * - Reentrant    - no
- * - ISR Callable - no
- *
- * @param portID @ref IxEthDBPortId [in] - ID of the port to remove the VLAN ID membership from
- * @param vlanID @ref IxEthDBVlanId [in] - VLAN ID to be removed from the port membership table
- *
- * @retval IX_ETH_DB_SUCCESS operation completed successfully
- * @retval IX_ETH_DB_INVALID_PORT portID is not a valid port identifier
- * @retval IX_ETH_DB_INVALID_VLAN vlanID is not a valid VLAN ID
- * @retval IX_ETH_DB_NO_PERMISSION attempted to remove the default VLAN ID
- * from the port membership table (vlanID was set to the default port VLAN ID)
- * @retval IX_ETH_DB_FEATURE_UNAVAILABLE VLAN/QoS feature is not available or not enabled for the port
- * @retval IX_FAIL unknown OS or NPE communication error
- *
- * @note A port's default VLAN ID cannot be removed from the port's membership
- * table; attempting it will return IX_ETH_DB_NO_PERMISSION
- */
-IX_ETH_DB_PUBLIC 
-IxEthDBStatus ixEthDBPortVlanMembershipRemove(IxEthDBPortId portID, IxEthDBVlanId vlanID);
-
-/**
- * @ingroup IxEthDB
- *
- * @fn IxEthDBStatus ixEthDBPortVlanMembershipRangeRemove(IxEthDBPortId portID, IxEthDBVlanId vlanIDMin, IxEthDBVlanId vlanIDMax)
- *
- * @brief Removes a VLAN ID range from a port's VLAN membership table
- *
- * All the VLAN IDs in the specified range will be removed from the port VLAN
- * membership table, including the range start and end VLAN IDs. Tagged frames
- * with VLAN IDs in the range will be discarded by the frame filter, if Ingress
- * membership filtering is enabled.
- *
- * - Reentrant    - no
- * - ISR Callable - no
- *
- * @param portID @ref IxEthDBPortId [in] - ID of the port to remove the VLAN membership range from
- * @param vlanIDMin @ref IxEthDBVlanId [in] - start of the VLAN ID range
- * @param vlanIDMax @ref IxEthDBVlanId [in] - end of the VLAN ID range
- *
- * @retval IX_ETH_DB_SUCCESS operation completed successfully
- * @retval IX_ETH_DB_INVALID_PORT portID is not a valid port identifier
- * @retval IX_ETH_DB_PORT_UNINITIALIZED port is not initialized
- * @retval IX_ETH_DB_INVALID_VLAN the specified VLAN IDs are invalid or do not constitute a range
- * @retval IX_ETH_DB_NO_PERMISSION attempted to remove the default VLAN ID
- * from the port membership table (both vlanIDMin and vlanIDMax were set to the default port VLAN ID)
- * @retval IX_ETH_DB_FEATURE_UNAVAILABLE VLAN/QoS feature is not available or not enabled for the port
- * @retval IX_FAIL unknown OS or NPE communication error
- *
- * @note Is is valid to use the same VLAN ID for both vlanIDMin and vlanIDMax, in which case
- * function will behave as @ref ixEthDBPortVlanMembershipRemove
- *
- * @note If the given range overlaps the default port VLAN ID this function
- * will remove all the VLAN IDs in the range except for the port VLAN ID from its 
- * own membership table. This situation will be silently dealt with (no error message
- * will be returned) as long as the range contains more than one value (i.e. at least 
- * one other value, apart from the default port VLAN ID). If the function is called 
- * with the vlanIDMin and vlanIDMax parameters both set to the port default VLAN ID, the 
- * function will infer that an attempt was specifically made to remove the default port 
- * VLAN ID from the port membership table, in which case the return value will be 
- * IX_ETH_DB_NO_PERMISSION.
- */
-IX_ETH_DB_PUBLIC 
-IxEthDBStatus ixEthDBPortVlanMembershipRangeRemove(IxEthDBPortId portID, IxEthDBVlanId vlanIDMin, IxEthDBVlanId vlanIDMax);
-
-/**
- * @ingroup IxEthDB
- *
- * @fn IxEthDBStatus ixEthDBPortVlanMembershipSet(IxEthDBPortId portID, IxEthDBVlanSet vlanSet)
- *
- * @brief Sets a port's VLAN membership table
- *
- * Sets a port's VLAN membership table from a complete VLAN table containing all the possible
- * 4096 VLAN IDs. The table format is an array containing 4096 bits (512 bytes), where each bit
- * indicates whether the VLAN at that bit index is in the port's membership list (if set) or
- * not (unset).
- *
- * The bit at index 0, indicating VLAN ID 0, indicates no VLAN membership and therefore no
- * other bit must be set if bit 0 is set.
- *
- * The bit at index 4095 is reserved and should never be set (it will be ignored if set).
- *
- * The bit referencing the same VLAN ID as the default port VLAN ID should always be set, as 
- * the membership list must contain at least the default port VLAN ID.
- *
- * - Reentrant    - no
- * - ISR Callable - no
- *
- * @param portID @ref IxEthDBPortId [in] - port ID to set the VLAN membership table to
- * @param vlanSet @ref IxEthDBVlanSet [in] - pointer to the VLAN membership table
- * 
- * @retval IX_ETH_DB_SUCCESS operation completed successfully
- * @retval IX_ETH_DB_INVALID_PORT portID is not a valid port identifier
- * @retval IX_ETH_DB_PORT_UNINITIALIZED port is not initialized
- * @retval IX_ETH_DB_INVALID_ARG invalid <i>vlanSet</i> pointer
- * @retval IX_ETH_DB_FEATURE_UNAVAILABLE VLAN/QoS feature is not available or not enabled for the port
- * @retval IX_FAIL unknown OS or NPE communication error
- */
-IX_ETH_DB_PUBLIC 
-IxEthDBStatus ixEthDBPortVlanMembershipSet(IxEthDBPortId portID, IxEthDBVlanSet vlanSet);
-
-/**
- * @ingroup IxEthDB
- *
- * @fn IxEthDBStatus ixEthDBPortVlanMembershipGet(IxEthDBPortId portID, IxEthDBVlanSet vlanSet)
- *
- * @brief Retrieves a port's VLAN membership table
- *
- * Retrieves the complete VLAN membership table from a port, containing all the possible
- * 4096 VLAN IDs. The table format is an array containing 4096 bits (512 bytes), where each bit
- * indicates whether the VLAN at that bit index is in the port's membership list (if set) or
- * not (unset).
- *
- * The bit at index 0, indicating VLAN ID 0, indicates no VLAN membership and therefore no
- * other bit will be set if bit 0 is set.
- *
- * The bit at index 4095 is reserved and will not be set (it will be ignored if set).
- *
- * The bit referencing the same VLAN ID as the default port VLAN ID will always be set, as 
- * the membership list must contain at least the default port VLAN ID.
- *
- * - Reentrant    - no
- * - ISR Callable - no
- *
- * @param portID @ref IxEthDBPortId [in] - port ID to retrieve the VLAN membership table from
- * @param vlanSet @ref IxEthDBVlanSet [out] - pointer a location where the VLAN membership table will be
- *                written to 
- * 
- * @retval IX_ETH_DB_SUCCESS operation completed successfully
- * @retval IX_ETH_DB_INVALID_PORT portID is not a valid port identifier
- * @retval IX_ETH_DB_PORT_UNINITIALIZED port is not initialized
- * @retval IX_ETH_DB_INVALID_ARG invalid <i>vlanSet</i> pointer
- * @retval IX_ETH_DB_FEATURE_UNAVAILABLE VLAN/QoS feature is not available or not enabled for the port
- */
-IX_ETH_DB_PUBLIC 
-IxEthDBStatus ixEthDBPortVlanMembershipGet(IxEthDBPortId portID, IxEthDBVlanSet vlanSet);
-
-/**
- * @ingroup IxEthDB
- *
- * @fn IxEthDBStatus ixEthDBAcceptableFrameTypeSet(IxEthDBPortId portID, IxEthDBFrameFilter frameFilter)
- *
- * @brief Sets a port's acceptable frame type filter
- *
- * The acceptable frame type is one (or a combination) of the following values:
- *    - IX_ETH_DB_ACCEPT_ALL_FRAMES       - accepts all the frames
- *    - IX_ETH_DB_UNTAGGED_FRAMES         - accepts untagged frames
- *    - IX_ETH_DB_VLAN_TAGGED_FRAMES      - accepts tagged frames
- *    - IX_ETH_DB_PRIORITY_TAGGED_FRAMES  - accepts tagged frames with VLAN ID set to 0 (no VLAN membership)
- *
- * Except for using the exact values given above only the following combinations are valid:
- *    - IX_ETH_DB_UNTAGGED_FRAMES | IX_ETH_DB_VLAN_TAGGED_FRAMES
- *    - IX_ETH_DB_UNTAGGED_FRAMES | IX_ETH_DB_PRIORITY_TAGGED_FRAMES
- *
- * Please note that IX_ETH_DB_UNTAGGED_FRAMES | IX_ETH_DB_VLAN_TAGGED_FRAMES is equivalent
- * to IX_ETH_DB_ACCEPT_ALL_FRAMES.
- *
- * - Reentrant    - no
- * - ISR Callable - no
- *
- * @note by default the acceptable frame type filter is set to IX_ETH_DB_ACCEPT_ALL_FRAMES
- *
- * @note setting the acceptable frame type to PRIORITY_TAGGED_FRAMES is internally
- * accomplished by changing the frame filter to VLAN_TAGGED_FRAMES and setting the
- * VLAN membership list to include only VLAN ID 0; the membership list will need
- * to be restored manually to an appropriate value if the acceptable frame type
- * filter is changed back to ACCEPT_ALL_FRAMES or VLAN_TAGGED_FRAMES; failure to do so
- * will filter all VLAN traffic bar frames tagged with VLAN ID 0
- *
- * @param portID @ref IxEthDBPortId [in] - port ID to set the acceptable frame type filter to
- * @param frameFilter @ref IxEthDBFrameFilter [in] - acceptable frame type filter
- * 
- * @retval IX_ETH_DB_SUCCESS operation completed successfully
- * @retval IX_ETH_DB_INVALID_PORT portID is not a valid port identifier
- * @retval IX_ETH_DB_PORT_UNINITIALIZED port is not initialized
- * @retval IX_ETH_DB_INVALID_ARG invalid frame type filter
- * @retval IX_ETH_DB_FEATURE_UNAVAILABLE VLAN/QoS feature is not available or not enabled for the port
- * @retval IX_FAIL unknown OS or NPE communication error
- */
-IX_ETH_DB_PUBLIC 
-IxEthDBStatus ixEthDBAcceptableFrameTypeSet(IxEthDBPortId portID, IxEthDBFrameFilter frameFilter);
-
-/**
- * @ingroup IxEthDB
- *
- * @fn IxEthDBStatus ixEthDBAcceptableFrameTypeGet(IxEthDBPortId portID, IxEthDBFrameFilter *frameFilter)
- *
- * @brief Retrieves a port's acceptable frame type filter 
- *
- * For a description of the acceptable frame types see @ref ixEthDBAcceptableFrameTypeSet
- *
- * - Reentrant    - no
- * - ISR Callable - no
- *
- * @param portID @ref IxEthDBPortId [in] - port ID to retrieve the acceptable frame type filter from
- * @param frameFilter @ref IxEthDBFrameFilter [out] - location to store the acceptable frame type filter
- * 
- * @retval IX_ETH_DB_SUCCESS operation completed successfully
- * @retval IX_ETH_DB_INVALID_PORT portID is not a valid port identifier
- * @retval IX_ETH_DB_PORT_UNINITIALIZED port is not initialized
- * @retval IX_ETH_DB_INVALID_ARG invalid <i>frameFilter</i> pointer argument
- * @retval IX_ETH_DB_FEATURE_UNAVAILABLE VLAN/QoS feature is not available or not enabled for the port
- */
-IX_ETH_DB_PUBLIC 
-IxEthDBStatus ixEthDBAcceptableFrameTypeGet(IxEthDBPortId portID, IxEthDBFrameFilter *frameFilter);
-
-/**
- * @ingroup IxEthDB
- *
- * @fn IxEthDBStatus ixEthDBPriorityMappingTableSet(IxEthDBPortId portID, IxEthDBPriorityTable priorityTable)
- *
- * @brief Sets a port's priority mapping table
- *
- * The priority mapping table is an 8x2 table mapping a QoS (user) priority into an internal
- * traffic class. There are 8 valid QoS priorities (0..7, 0 being the lowest) which can be
- * mapped into one of the 4 available traffic classes (0..3, 0 being the lowest).
- * If a custom priority mapping table is not specified using this function the following
- * default priority table will be used (as per IEEE 802.1Q and IEEE 802.1D):
- * 
- * <table border="1"> <caption> QoS traffic classes  </caption>
- *    <tr> <td> <b> QoS priority <td> <b> Default traffic class <td> <b> Traffic type </b>
- *    <tr> <td>      0       <td>           1           <td> Best effort, default class for unexpedited traffic
- *    <tr> <td>      1       <td>           0           <td> Background traffic
- *    <tr> <td>      2       <td>           0           <td> Spare bandwidth
- *    <tr> <td>      3       <td>           1           <td> Excellent effort
- *    <tr> <td>      4       <td>           2           <td> Controlled load
- *    <tr> <td>      5       <td>           2           <td> Video traffic
- *    <tr> <td>      6       <td>           3           <td> Voice traffic
- *    <tr> <td>      7       <td>           3           <td> Network control
- * </table>
- *
- * - Reentrant    - no
- * - ISR Callable - no
- *
- * @param portID @ref IxEthDBPortId [in] - port ID of the port to set the priority mapping table to
- * @param priorityTable @ref IxEthDBPriorityTable [in] - location of the user priority table
- *
- * @note The provided table will be copied into internal data structures in EthDB and 
- * can be deallocated by the called after this function has completed its execution, if
- * so desired
- *
- * @warning The number of available traffic classes differs depending on the NPE images
- * and queue configuration. Check IxEthDBQoS.h for up-to-date information on the availability of
- * traffic classes. Note that specifiying a traffic class in the priority map which exceeds
- * the system availability will produce an IX_ETH_DB_INVALID_PRIORITY return error code and no
- * priority will be remapped.
- * 
- * @retval IX_ETH_DB_SUCCESS operation completed successfully
- * @retval IX_ETH_DB_INVALID_PORT portID is not a valid port identifier
- * @retval IX_ETH_DB_PORT_UNINITIALIZED port is not initialized
- * @retval IX_ETH_DB_INVALID_ARG invalid <i>priorityTable</i> pointer
- * @retval IX_ETH_DB_INVALID_PRIORITY at least one priority value exceeds
- * the current number of available traffic classes
- * @retval IX_ETH_DB_FEATURE_UNAVAILABLE VLAN/QoS feature is not available or not enabled for the port
- * @retval IX_FAIL unknown OS or NPE communication error
- */
-IX_ETH_DB_PUBLIC 
-IxEthDBStatus ixEthDBPriorityMappingTableSet(IxEthDBPortId portID, IxEthDBPriorityTable priorityTable);
-
-/**
- * @ingroup IxEthDB
- *
- * @fn IxEthDBStatus ixEthDBPriorityMappingTableGet(IxEthDBPortId portID, IxEthDBPriorityTable priorityTable)
- *
- * @brief Retrieves a port's priority mapping table
- *
- * The priority mapping table for the given port will be copied in the location
- * specified by the caller using "priorityTable"
- *
- * - Reentrant    - no
- * - ISR Callable - no
- *
- * @param portID ID @ref IxEthDBPortId [in] - of the port to retrieve the priority mapping table from
- * @param priorityTable @ref IxEthDBPriorityTable [out] - pointer to a user specified location where the table will be copied to
- *
- * @retval IX_ETH_DB_SUCCESS operation completed successfully
- * @retval IX_ETH_DB_INVALID_PORT portID is not a valid port identifier
- * @retval IX_ETH_DB_PORT_UNINITIALIZED port is not initialized
- * @retval IX_ETH_DB_INVALID_ARG invalid priorityTable pointer
- * @retval IX_ETH_DB_FEATURE_UNAVAILABLE VLAN/QoS feature is not available or not enabled for the port
- */
-IX_ETH_DB_PUBLIC 
-IxEthDBStatus ixEthDBPriorityMappingTableGet(IxEthDBPortId portID, IxEthDBPriorityTable priorityTable);
-
-/**
- * @ingroup IxEthDB
- *
- * @fn IxEthDBStatus ixEthDBPriorityMappingClassSet(IxEthDBPortId portID, IxEthDBPriority userPriority, IxEthDBPriority trafficClass)
- *
- * @brief Sets one QoS/user priority => traffic class mapping in a port's priority mapping table
- *
- * This function establishes a mapping between a user (QoS) priority and an internal traffic class.
- * The mapping will be saved in the port's priority mapping table. Use this function when not all
- * the QoS priorities need remapping (see also @ref ixEthDBPriorityMappingTableSet)
- *
- * - Reentrant    - no
- * - ISR Callable - no
- *
- * @param portID @ref IxEthDBPortId [in] - ID of the port to set the mapping to
- * @param userPriority @ref IxEthDBPriority [in] - user (QoS) priority, between 0 and 7 (0 being the lowest)
- * @param trafficClass @ref IxEthDBPriority [in] - internal traffic class, between 0 and 3 (0 being the lowest)
- *
- * @retval IX_ETH_DB_SUCCESS operation completed successfully
- * @retval IX_ETH_DB_INVALID_PORT portID is not a valid port identifier
- * @retval IX_ETH_DB_PORT_UNINITIALIZED port is not initialized
- * @retval IX_ETH_DB_INVALID_PRIORITY <i>userPriority</i> out of range or
- * <i>trafficClass</i> is beyond the number of currently available traffic classes
- * @retval IX_ETH_DB_FEATURE_UNAVAILABLE VLAN/QoS feature is not available or not enabled for the port
- * @retval IX_FAIL unknown OS or NPE communication error
- */
-IX_ETH_DB_PUBLIC 
-IxEthDBStatus ixEthDBPriorityMappingClassSet(IxEthDBPortId portID, IxEthDBPriority userPriority, IxEthDBPriority trafficClass);
-
-/**
- * @ingroup IxEthDB
- *
- * @fn IxEthDBStatus ixEthDBPriorityMappingClassGet(IxEthDBPortId portID, IxEthDBPriority userPriority, IxEthDBPriority *trafficClass)
- *
- * @brief Retrieves one QoS/user priority => traffic class mapping in a port's priority mapping table
- *
- * This function retrieves the internal traffic class associated with a QoS (user) priority from a given
- * port's priority mapping table. Use this function when not all the QoS priority mappings are 
- * required (see also @ref ixEthDBPriorityMappingTableGet)
- *
- * - Reentrant    - no
- * - ISR Callable - no
- *
- * @param portID @ref IxEthDBPortId [in] - ID of the port to set the mapping to
- * @param userPriority @ref IxEthDBPriority [in] - user (QoS) priority, between 0 and 7 (0 being the lowest)
- * @param trafficClass @ref IxEthDBPriority [out] - location to write the corresponding internal traffic class to
- *
- * @retval IX_ETH_DB_SUCCESS operation completed successfully
- * @retval IX_ETH_DB_INVALID_PORT portID is not a valid port identifier
- * @retval IX_ETH_DB_PORT_UNINITIALIZED port is not initialized
- * @retval IX_ETH_DB_INVALID_PRIORITY invalid userPriority value (out of range)
- * @retval IX_ETH_DB_FEATURE_UNAVAILABLE VLAN/QoS feature is not available or not enabled for the port
- * @retval IX_ETH_DB_INVALID_ARG invalid <i>trafficClass</i> pointer argument
- */
-IX_ETH_DB_PUBLIC 
-IxEthDBStatus ixEthDBPriorityMappingClassGet(IxEthDBPortId portID, IxEthDBPriority userPriority, IxEthDBPriority *trafficClass);
-
-/**
- * @ingroup IxEthDB
- *
- * @fn IxEthDBStatus ixEthDBEgressVlanEntryTaggingEnabledSet(IxEthDBPortId portID, IxEthDBVlanId vlanID, BOOL enabled)
- *
- * @brief Enables or disables Egress VLAN tagging for a port and a given VLAN
- *
- * This function enables or disables Egress VLAN tagging for the given port and VLAN ID.
- * If the VLAN tagging for a certain VLAN ID is enabled then all the frames to be
- * transmitted on the given port tagged with the same VLAN ID will be transmitted in a tagged format.
- * If tagging is not enabled for the given VLAN ID, the VLAN tag from the frames matching
- * this VLAN ID will be removed (the frames will be untagged).
- *
- * VLAN ID 4095 is reserved and should never be used with this function.
- * VLAN ID 0 has the special meaning of "No VLAN membership" and it is used in this
- * context to allow the port to send priority-tagged frames or not.
- *
- * By default, no Egress VLAN tagging is enabled on any port.
- *
- * - Reentrant    - no
- * - ISR Callable - no
- *
- * @param portID @ref IxEthDBPortId [in] - ID of the port to enable or disable the VLAN ID Egress tagging on
- * @param vlanID @ref IxEthDBVlanId [in] - VLAN ID to be matched against outgoing frames
- * @param enabled BOOL [in] - true to enable Egress VLAN tagging on the port and given VLAN, and
- *                false to disable Egress VLAN tagging
- *
- * @retval IX_ETH_DB_SUCCESS operation completed successfully
- * @retval IX_ETH_DB_INVALID_PORT portID is not a valid port identifier
- * @retval IX_ETH_DB_PORT_UNINITIALIZED port is not initialized
- * @retval IX_ETH_DB_INVALID_VLAN invalid VLAN ID (out of range)
- * @retval IX_ETH_DB_FEATURE_UNAVAILABLE VLAN/QoS feature is not available or not enabled for the port
- * @retval IX_FAIL unknown OS or NPE communication error
- */
-IX_ETH_DB_PUBLIC 
-IxEthDBStatus ixEthDBEgressVlanEntryTaggingEnabledSet(IxEthDBPortId portID, IxEthDBVlanId vlanID, BOOL enabled);
-
-/**
- * @ingroup IxEthDB
- *
- * @fn IxEthDBStatus ixEthDBEgressVlanEntryTaggingEnabledGet(IxEthDBPortId portID, IxEthDBVlanId vlanID, BOOL *enabled)
- *
- * @brief Retrieves the Egress VLAN tagging enabling status for a port and VLAN ID
- *
- * @param portID [in] - ID of the port to extract the Egress VLAN ID tagging status from
- * @param vlanID VLAN [in] - ID whose tagging status is to be extracted
- * @param enabled [in] - user-specifed location where the status is copied to; following
- * the successfull execution of this function the value will be true if Egress VLAN
- * tagging is enabled for the given port and VLAN ID, and false otherwise
- *
- * - Reentrant    - no
- * - ISR Callable - no
- *
- * @see ixEthDBEgressVlanEntryTaggingEnabledGet
- *
- * @retval IX_ETH_DB_SUCCESS operation completed successfully
- * @retval IX_ETH_DB_INVALID_PORT portID is not a valid port identifier
- * @retval IX_ETH_DB_PORT_UNINITIALIZED port is not initialized
- * @retval IX_ETH_DB_INVALID_VLAN invalid VLAN ID (out of range)
- * @retval IX_ETH_DB_INVALID_ARG invalid <i>enabled</i> argument pointer
- * @retval IX_ETH_DB_FEATURE_UNAVAILABLE VLAN/QoS feature is not available or not enabled for the port
- */
-IX_ETH_DB_PUBLIC 
-IxEthDBStatus ixEthDBEgressVlanEntryTaggingEnabledGet(IxEthDBPortId portID, IxEthDBVlanId vlanID, BOOL *enabled);
-
-/**
- * @ingroup IxEthDB
- *
- * @fn IxEthDBStatus ixEthDBEgressVlanRangeTaggingEnabledSet(IxEthDBPortId portID, IxEthDBVlanId vlanIDMin, IxEthDBVlanId vlanIDMax, BOOL enabled)
- *
- * @brief Enables or disables Egress VLAN tagging for a port and given VLAN range
- *
- * This function is very similar to @ref ixEthDBEgressVlanEntryTaggingEnabledSet with the
- * difference that it can manipulate the Egress tagging status on multiple VLAN IDs,
- * defined by a contiguous range. Note that both limits in the range are explicitly 
- * included in the execution of this function.
- *
- * - Reentrant    - no
- * - ISR Callable - no
- *
- * @param portID @ref IxEthDBPortId [in] - ID of the port to enable or disable the VLAN ID Egress tagging on
- * @param vlanIDMin @ref IxEthDBVlanId [in] - start of the VLAN range to be matched against outgoing frames
- * @param vlanIDMax @ref IxEthDBVlanId [in] - end of the VLAN range to be matched against outgoing frames
- * @param enabled BOOL [in] - true to enable Egress VLAN tagging on the port and given VLAN range,
- *                and false to disable Egress VLAN tagging
- * 
- * @retval IX_ETH_DB_SUCCESS operation completed successfully
- * @retval IX_ETH_DB_INVALID_PORT portID is not a valid port identifier
- * @retval IX_ETH_DB_PORT_UNINITIALIZED port is not initialized
- * @retval IX_ETH_DB_INVALID_VLAN invalid VLAN ID (out of range), or do not constitute a range
- * @retval IX_ETH_DB_FEATURE_UNAVAILABLE VLAN/QoS feature is not available or not enabled for the port
- * @retval IX_ETH_DB_NO_PERMISSION attempted to explicitly remove the default port VLAN ID from the tagging table
- * @retval IX_FAIL unknown OS or NPE communication error
- *
- * @note Specifically removing the default port VLAN ID from the Egress tagging table by setting both vlanIDMin and vlanIDMax
- * to the VLAN ID portion of the PVID is not allowed by this function and will return IX_ETH_DB_NO_PERMISSION.
- * However, this can be circumvented, should the user specifically desire this, by either using a 
- * larger range (vlanIDMin < vlanIDMax) or by using ixEthDBEgressVlanEntryTaggingEnabledSet.
- */
-IX_ETH_DB_PUBLIC 
-IxEthDBStatus ixEthDBEgressVlanRangeTaggingEnabledSet(IxEthDBPortId portID, IxEthDBVlanId vlanIDMin, IxEthDBVlanId vlanIDMax, BOOL enabled);
-
-/**
- * @ingroup IxEthDB
- *
- * @fn IxEthDBStatus ixEthDBEgressVlanTaggingEnabledSet(IxEthDBPortId portID, IxEthDBVlanSet vlanSet)
- *
- * @brief Sets the complete Egress VLAN tagging table for a port
- *
- * This function is used to set the VLAN tagging/untagging per VLAN ID for a given port
- * covering the entire VLAN ID range (0..4094). The <i>vlanSet</i> parameter is a 4096
- * bit array, each bit indicating the Egress behavior for the corresponding VLAN ID.
- * If a bit is set then outgoing frames with the corresponding VLAN ID will be transmitted
- * with the VLAN tag, otherwise the frame will be transmitted without the VLAN tag.
- *
- * Bit 0 has a special significance, indicating tagging or tag removal for priority-tagged
- * frames.
- *
- * Bit 4095 is reserved and should never be set (it will be ignored if set).
- *
- * - Reentrant    - no
- * - ISR Callable - no
- *
- * @param portID @ref IxEthDBPortId [in] - ID of the port whose Egress VLAN tagging behavior is set
- * @param vlanSet @ref IxEthDBVlanSet [in] - 4096 bit array controlling per-VLAN tagging and untagging 
- *
- * @retval IX_ETH_DB_SUCCESS operation completed successfully
- * @retval IX_ETH_DB_INVALID_PORT portID is not a valid port identifier
- * @retval IX_ETH_DB_PORT_UNINITIALIZED port is not initialized
- * @retval IX_ETH_DB_INVALID_ARG invalid <i>vlanSet</i> pointer
- * @retval IX_ETH_DB_FEATURE_UNAVAILABLE VLAN/QoS feature is not available or not enabled for the port
- * @retval IX_FAIL unknown OS or NPE communication error
- *
- * @warning This function will automatically add the default port VLAN ID to the Egress tagging table
- * every time it is called. The user should manually call ixEthDBEgressVlanEntryTaggingEnabledSet to
- * prevent tagging on the default port VLAN ID if the default behavior is not intended.
- */
-IX_ETH_DB_PUBLIC 
-IxEthDBStatus ixEthDBEgressVlanTaggingEnabledSet(IxEthDBPortId portID, IxEthDBVlanSet vlanSet);
-
-/**
- * @ingroup IxEthDB
- *
- * @fn IxEthDBStatus ixEthDBEgressVlanTaggingEnabledGet(IxEthDBPortId portID, IxEthDBVlanSet vlanSet)
- *
- * @brief Retrieves the complete Egress VLAN tagging table from a port
- *
- * This function copies the 4096 bit table controlling the Egress VLAN tagging into a user specified
- * area. Each bit in the array indicates whether tagging for the corresponding VLAN (the bit position
- * in the array) is enabled (the bit is set) or not (the bit is unset). 
- *
- * Bit 4095 is reserved and should not be set (it will be ignored if set).
- *
- * @see ixEthDBEgressVlanTaggingEnabledSet
- *
- * @param portID @ref IxEthDBPortId [in] - ID of the port whose Egress VLAN tagging behavior is retrieved
- * @param vlanSet @ref IxEthDBVlanSet [out] - user location to copy the Egress tagging table into; should have
- * room to store 4096 bits (512 bytes)
- * 
- * @retval IX_ETH_DB_SUCCESS operation completed successfully
- * @retval IX_ETH_DB_INVALID_PORT portID is not a valid port identifier
- * @retval IX_ETH_DB_PORT_UNINITIALIZED port is not initialized
- * @retval IX_ETH_DB_INVALID_ARG invalid <i>vlanSet</i> pointer
- * @retval IX_ETH_DB_FEATURE_UNAVAILABLE VLAN/QoS feature is not available or not enabled for the port
- */
-IX_ETH_DB_PUBLIC 
-IxEthDBStatus ixEthDBEgressVlanTaggingEnabledGet(IxEthDBPortId portID, IxEthDBVlanSet vlanSet);
-
-/**
- * @ingroup IxEthDB
- *
- * @fn IxEthDBStatus ixEthDBIngressVlanTaggingEnabledSet(IxEthDBPortId portID, IxEthDBTaggingAction taggingAction)
- *
- * @brief Sets the Ingress VLAN tagging behavior for a port
- *
- * A port's Ingress tagging behavior is controlled by the taggingAction parameter,
- * which can take one of the following values:
- * 
- * - IX_ETH_DB_PASS_THROUGH - leaves the frame unchanged (does not add or remove the VLAN tag)
- * - IX_ETH_DB_ADD_TAG - adds the VLAN tag if not present, using the default port VID
- * - IX_ETH_DB_REMOVE_TAG - removes the VLAN tag if present
- * 
- * @param portID @ref IxEthDBPortId [in] - ID of the port whose Ingress VLAN tagging behavior is set
- * @param taggingAction @ref IxEthDBTaggingAction [in] - tagging behavior for the port
- * 
- * @retval IX_ETH_DB_SUCCESS operation completed successfully
- * @retval IX_ETH_DB_INVALID_PORT portID is not a valid port identifier
- * @retval IX_ETH_DB_PORT_UNINITIALIZED port is not initialized
- * @retval IX_ETH_DB_INVALID_ARG invalid <i>taggingAction</i> argument
- * @retval IX_ETH_DB_FEATURE_UNAVAILABLE VLAN/QoS feature is not available or not enabled for the port
- * @retval IX_FAIL unknown OS or NPE communication error
- */
-IX_ETH_DB_PUBLIC 
-IxEthDBStatus ixEthDBIngressVlanTaggingEnabledSet(IxEthDBPortId portID, IxEthDBTaggingAction taggingAction);
-
-/**
- * @ingroup IxEthDB
- *
- * @fn IxEthDBStatus ixEthDBIngressVlanTaggingEnabledGet(IxEthDBPortId portID, IxEthDBTaggingAction *taggingAction)
- *
- * @brief Retrieves the Ingress VLAN tagging behavior from a port (see @ref ixEthDBIngressVlanTaggingEnabledSet)
- *
- * @param portID @ref IxEthDBPortId [in] - ID of the port whose Ingress VLAN tagging behavior is set
- * @param taggingAction @ref IxEthDBTaggingAction [out] - location where the tagging behavior for the port is written to
- * 
- * @retval IX_ETH_DB_SUCCESS operation completed successfully
- * @retval IX_ETH_DB_INVALID_PORT portID is not a valid port identifier
- * @retval IX_ETH_DB_PORT_UNINITIALIZED port is not initialized
- * @retval IX_ETH_DB_INVALID_ARG invalid <i>taggingAction</i> pointer argument
- * @retval IX_ETH_DB_FEATURE_UNAVAILABLE VLAN/QoS feature is not available or not enabled for the port
- */
-IX_ETH_DB_PUBLIC 
-IxEthDBStatus ixEthDBIngressVlanTaggingEnabledGet(IxEthDBPortId portID, IxEthDBTaggingAction *taggingAction);
-
-/**
- * @ingroup IxEthDB
- *
- * @fn IxEthDBStatus ixEthDBVlanPortExtractionEnable(IxEthDBPortId portID, BOOL enable)
- *
- * @brief Enables or disables port ID extraction
- *
- * This feature can be used in the situation when a multi-port device (e.g. a switch) 
- * is connected to an IXP4xx port and the device can provide incoming frame port 
- * identification by tagging the TPID field in the Ethernet frame. Enabling
- * port extraction will instruct the NPE to copy the TPID field from the frame and 
- * place it in the <i>ixp_ne_src_port</i> of the <i>ixp_buf</i> header. In addition,
- * the NPE restores the TPID field to 0.
- *
- * If the frame is not tagged the NPE will fill the <i>ixp_ne_src_port</i> with the 
- * port ID of the MII interface the frame was received from.
- *
- * The TPID field is the least significant byte of the type/length field, which is 
- * normally set to 0x8100 for 802.1Q-tagged frames.
- *
- * This feature is disabled by default.
- *
- * @param portID ID of the port to configure port ID extraction on
- * @param enable true to enable port ID extraction and false to disable it
- * 
- * @retval IX_ETH_DB_SUCCESS operation completed successfully
- * @retval IX_ETH_DB_INVALID_PORT portID is not a valid port identifier
- * @retval IX_ETH_DB_PORT_UNINITIALIZED port is not initialized
- * @retval IX_ETH_DB_FEATURE_UNAVAILABLE VLAN/QoS feature is not available or not enabled for the port
- * @retval IX_FAIL unknown OS or NPE communication error
- */
-IX_ETH_DB_PUBLIC 
-IxEthDBStatus ixEthDBVlanPortExtractionEnable(IxEthDBPortId portID, BOOL enable);
-
-/**
- * @ingroup IxEthDB
- *
- * @fn IxEthDBStatus ixEthDBFeatureCapabilityGet(IxEthDBPortId portID, IxEthDBFeature *featureSet)
- *
- * @brief Retrieves the feature capability set for a port
- *
- * This function retrieves the feature capability set for a port or the common capabilities shared between all 
- * the ports, writing the feature capability set in a user specified location.
- *
- * The feature capability set will consist of a set formed by OR-ing one or more of the following values:
- * - IX_ETH_DB_LEARNING - Learning feature; enables EthDB to learn MAC address (filtering) records, including 802.1Q enabled records
- * - IX_ETH_DB_FILTERING - Filtering feature; enables EthDB to communicate with the NPEs for downloading filtering information in the NPEs; depends on the learning feature
- * - IX_ETH_DB_VLAN_QOS - VLAN/QoS feature; enables EthDB to configure NPEs to operate in VLAN/QoS aware modes
- * - IX_ETH_DB_FIREWALL - Firewall feature; enables EthDB to configure NPEs to operate in firewall mode, using white/black address lists
- * - IX_ETH_DB_SPANNING_TREE_PROTOCOL - Spanning tree protocol feature; enables EthDB to configure the NPEs as STP nodes
- * - IX_ETH_DB_WIFI_HEADER_CONVERSION - WiFi 802.3 to 802.11 header conversion feature; enables EthDB to handle WiFi conversion data
- *
- * Note that EthDB provides only the LEARNING feature for non-NPE ports.
- * 
- * @param portID @ref IxEthDBPortId [in] - ID of the port to retrieve the capability set for 
- * (use IX_ETH_DB_ALL_PORTS to retrieve the common capabilities shared between all the ports)
- * @param featureSet @ref IxEthDBFeature [out] - location where the capability set will be written to
- * 
- * @retval IX_ETH_DB_SUCCESS operation completed successfully
- * @retval IX_ETH_DB_INVALID_PORT portID is not a valid port identifier
- * @retval IX_ETH_DB_PORT_UNINITIALIZED port is not initialized
- * @retval IX_ETH_DB_INVALID_ARG invalid <i>featureSet</i> pointer
- */
-IX_ETH_DB_PUBLIC 
-IxEthDBStatus ixEthDBFeatureCapabilityGet(IxEthDBPortId portID, IxEthDBFeature *featureSet);
-
-/**
- * @ingroup IxEthDB
- *
- * @fn IxEthDBStatus ixEthDBFeatureEnable(IxEthDBPortId portID, IxEthDBFeature feature, BOOL enabled)
- *
- * @brief Enables or disables one or more EthDB features
- *
- * Selects one or more features (see @ref ixEthDBFeatureCapabilityGet for a description of the supported
- * features) to be enabled or disabled on the selected port (or all the ports).
- *
- * Note that some features are mutually incompatible:
- * - IX_ETH_DB_FILTERING is incompatible with IX_ETH_DB_WIFI_HEADER_CONVERSION
- *
- * Also note that some features require other features to be enabled: 
- * - IX_ETH_DB_FILTERING requires IX_ETH_DB_LEARNING
- *
- * This function will either enable the entire selected feature set for the selected port (or all the ports),
- * in which case it will return IX_ETH_DB_SUCCESS, or in case of error it will not enable any feature at all
- * and return an appropriate error message.
- *
- * The following features are enabled by default (for ports with the respective capability), 
- * for compatibility reasons with previous versions of CSR:
- * - IX_ETH_DB_LEARNING
- * - IX_ETH_DB_FILTERING
- *
- * All other features are disabled by default and require manual enabling using ixEthDBFeatureEnable.
- *
- * <b>Default settings for VLAN, QoS, Firewall and WiFi header conversion features:</b>
- *
- * <i>VLAN</i>
- *
- * When the VLAN/QoS feature is enabled for a port for the first time the default VLAN behavior 
- * of the port is set to be as <b>permissive</b> (it will accept all the frames) and 
- * <b>non-interferential</b> (it will not change any frames) as possible:
- * - the port VLAN ID (VID) is set to 0
- * - the Ingress acceptable frame filter is set to accept all frames
- * - the VLAN port membership is set to the complete VLAN range (0 - 4094)
- * - the Ingress tagging mode is set to pass-through (will not change frames)
- * - the Egress tagging mode is to send tagged frames in the entire VLAN range (0 - 4094)
- *
- * Note that further disabling and re-enabling the VLAN feature for a given port will not reset the port VLAN behavior
- * to the settings listed above. Any VLAN settings made by the user are kept.
- *
- * <i>QoS</i>
- *
- * The following default priority mapping table will be used (as per IEEE 802.1Q and IEEE 802.1D):
- * 
- * <table border="1"> <caption> QoS traffic classes  </caption>
- *    <tr> <td> <b> QoS priority <td> <b> Default traffic class <td> <b> Traffic type </b>
- *    <tr> <td>      0       <td>           1           <td> Best effort, default class for unexpedited traffic
- *    <tr> <td>      1       <td>           0           <td> Background traffic
- *    <tr> <td>      2       <td>           0           <td> Spare bandwidth
- *    <tr> <td>      3       <td>           1           <td> Excellent effort
- *    <tr> <td>      4       <td>           2           <td> Controlled load
- *    <tr> <td>      5       <td>           2           <td> Video traffic
- *    <tr> <td>      6       <td>           3           <td> Voice traffic
- *    <tr> <td>      7       <td>           3           <td> Network control
- * </table>
- *
- * <i> Firewall </i>
- *  
- * The port firewall is configured by default in <b>black-list mode</b>, and the firewall address table is empty.
- * This means the firewall will not filter any frames until the feature is configured and the firewall table is
- * downloaded to the NPE.
- *
- * <i> Spanning Tree </i>
- *
- * The port is set to <b>STP unblocked mode</b>, therefore it will accept all frames until re-configured.
- *
- * <i> WiFi header conversion </i>
- *
- * The WiFi header conversion database is empty, therefore no actual header conversion will take place until this
- * feature is configured and the conversion table downloaded to the NPE.
- *
- * @param portID @ref IxEthDBPortId [in] - ID of the port to enable or disable the features on (use IX_ETH_DB_ALL_PORTS for all the ports)
- * @param feature @ref IxEthDBFeature [in] - feature or feature set to enable or disable
- * @param enabled BOOL [in] - true to enable the feature and false to disable it
- * 
- * @note Certain features, from a functional point of view, cannot be disabled as such at NPE level;
- * when such features are set to <i>disabled</i> using the EthDB API they will be configured in such
- * a way to determine a behavior equivalent to the feature being disabled. As well as this, disabled
- * features cannot be configured or accessed via the EthDB API (except for getting their status).
- *
- * @retval IX_ETH_DB_SUCCESS operation completed successfully
- * @retval IX_ETH_DB_INVALID_PORT portID is not a valid port identifier
- * @retval IX_ETH_DB_PORT_UNINITIALIZED port is not initialized
- * @retval IX_ETH_DB_NO_PERMISSION attempted to enable mutually exclusive features, 
- * or a feature that depends on another feature which is not present or enabled
- * @retval IX_ETH_DB_FEATURE_UNAVAILABLE at least one of the features selected is unavailable
- * @retval IX_FAIL unknown OS or NPE communication error
- */
-IX_ETH_DB_PUBLIC 
-IxEthDBStatus ixEthDBFeatureEnable(IxEthDBPortId portID, IxEthDBFeature feature, BOOL enabled);
-
-/**
- * @ingroup IxEthDB
- *
- * @fn IxEthDBStatus ixEthDBFeatureStatusGet(IxEthDBPortId portID, IxEthDBFeature feature, BOOL *present, BOOL *enabled)
- *
- * @brief Retrieves the availability and status of a feature set
- *
- * This function returns the availability and status for a feature set.
- * Note that if more than one feature is selected (e.g. IX_ETH_DB_LEARNING | IX_ETH_DB_FILTERING)
- * the "present" and "enabled" return values will be set to true only if all the features in the
- * feature set are present and enabled (not only some). 
- * 
- * @param portID @ref IxEthDBPortId [in] - ID of the port 
- * @param feature @ref IxEthDBFeature [in] - identifier of the feature to retrieve the status for
- * @param present BOOL [out] - location where a boolean flag indicating whether this feature is present will be written to
- * @param enabled BOOL [out] - location where a boolean flag indicating whether this feature is enabled will be written to
- * 
- * @retval IX_ETH_DB_SUCCESS operation completed successfully
- * @retval IX_ETH_DB_INVALID_PORT portID is not a valid port identifier
- * @retval IX_ETH_DB_PORT_UNINITIALIZED port is not initialized
- * @retval IX_ETH_DB_INVALID_ARG either <i>present</i> or <i>enabled</i> pointer argument is invalid
- */
-IX_ETH_DB_PUBLIC 
-IxEthDBStatus ixEthDBFeatureStatusGet(IxEthDBPortId portID, IxEthDBFeature feature, BOOL *present, BOOL *enabled);
-
-/**
- * @ingroup IxEthDB
- *
- * @fn IxEthDBStatus ixEthDBFeaturePropertyGet(IxEthDBPortId portID, IxEthDBFeature feature, IxEthDBProperty property, IxEthDBPropertyType *type, void *value)
- *
- * @brief Retrieves the value of a feature property
- *
- * The EthDB features usually contain feature-specific properties describing or
- * controlling how the feature operates. While essential properties (e.g. the
- * firewall operating mode) have their own API, secondary properties can be 
- * retrieved using this function.
- *
- * Properties can be read-only or read-write. ixEthDBFeaturePropertyGet operates with
- * both types of features.
- *
- * Properties have types associated with them. A descriptor indicating the property
- * type is returned in the <i>type</i> argument for convenience.
- *
- * The currently supported properties and their corresponding features are as follows:
- *
- * <table border="1"> <caption> Properties for IX_ETH_DB_VLAN_QOS </caption>
- *    <tr> <td> <b>        Property identifier                  <td> <b> Property type          <td> <b> Property value                   <td> <b> Read-Only </b>
- *    <tr> <td> IX_ETH_DB_QOS_TRAFFIC_CLASS_COUNT_PROPERTY      <td> IX_ETH_DB_INTEGER_PROPERTY <td> number of internal traffic classes   <td> Yes
- *    <tr> <td> IX_ETH_DB_QOS_TRAFFIC_CLASS_0_RX_QUEUE_PROPERTY <td> IX_ETH_DB_INTEGER_PROPERTY <td> queue assignment for traffic class 0 <td> Yes
- *    <tr> <td> IX_ETH_DB_QOS_TRAFFIC_CLASS_1_RX_QUEUE_PROPERTY <td> IX_ETH_DB_INTEGER_PROPERTY <td> queue assignment for traffic class 1 <td> Yes
- *    <tr> <td> IX_ETH_DB_QOS_TRAFFIC_CLASS_2_RX_QUEUE_PROPERTY <td> IX_ETH_DB_INTEGER_PROPERTY <td> queue assignment for traffic class 2 <td> Yes
- *    <tr> <td> IX_ETH_DB_QOS_TRAFFIC_CLASS_3_RX_QUEUE_PROPERTY <td> IX_ETH_DB_INTEGER_PROPERTY <td> queue assignment for traffic class 3 <td> Yes
- *    <tr> <td> IX_ETH_DB_QOS_TRAFFIC_CLASS_4_RX_QUEUE_PROPERTY <td> IX_ETH_DB_INTEGER_PROPERTY <td> queue assignment for traffic class 4 <td> Yes
- *    <tr> <td> IX_ETH_DB_QOS_TRAFFIC_CLASS_5_RX_QUEUE_PROPERTY <td> IX_ETH_DB_INTEGER_PROPERTY <td> queue assignment for traffic class 5 <td> Yes
- *    <tr> <td> IX_ETH_DB_QOS_TRAFFIC_CLASS_6_RX_QUEUE_PROPERTY <td> IX_ETH_DB_INTEGER_PROPERTY <td> queue assignment for traffic class 6 <td> Yes
- *    <tr> <td> IX_ETH_DB_QOS_TRAFFIC_CLASS_7_RX_QUEUE_PROPERTY <td> IX_ETH_DB_INTEGER_PROPERTY <td> queue assignment for traffic class 7 <td> Yes
- * </table>
- * 
- * @see ixEthDBFeaturePropertySet
- *
- * @param portID @ref IxEthDBPortId [in] - ID of the port 
- * @param feature @ref IxEthDBFeature [in] - EthDB feature for which the property is retrieved
- * @param property @ref IxEthDBProperty [in] - property identifier
- * @param type @ref IxEthDBPropertyType [out] - location where the property type will be stored
- * @param value void [out] - location where the property value will be stored
- * 
- * @retval IX_ETH_DB_SUCCESS operation completed successfully
- * @retval IX_ETH_DB_INVALID_PORT portID is not a valid port identifier
- * @retval IX_ETH_DB_INVALID_ARG invalid property identifier, <i>type</i> or <i>value</i> pointer arguments
- * @retval IX_ETH_DB_FAIL incorrect property value or unknown error
- */
-IX_ETH_DB_PUBLIC 
-IxEthDBStatus ixEthDBFeaturePropertyGet(IxEthDBPortId portID, IxEthDBFeature feature, IxEthDBProperty property, IxEthDBPropertyType *type, void *value);
-
-/**
- * @ingroup IxEthDB
- *
- * @fn IxEthDBStatus ixEthDBFeaturePropertySet(IxEthDBPortId portID, IxEthDBFeature feature, IxEthDBProperty property, void *value)
- *
- * @brief Sets the value of a feature property
- *
- * Unlike @ref ixEthDBFeaturePropertyGet, this function operates only with read-write properties
- *
- * The currently supported properties and their corresponding features are as follows:
- *
- *   - IX_ETH_DB_QOS_QUEUE_CONFIGURATION_COMPLETE (for IX_ETH_DB_VLAN_QOS): freezes the availability of traffic classes
- *     to the number of traffic classes currently in use
- *
- * Note that this function creates deep copies of the property values; once the function is invoked the client 
- * can free or reuse the memory area containing the original property value.
- *
- * Copy behavior for different property types is defined as follows:
- *
- *   - IX_ETH_DB_INTEGER_PROPERTY   - 4 bytes are copied from the source location
- *   - IX_ETH_DB_STRING_PROPERTY    - the source string will be copied up to the NULL '\0' string terminator, maximum of 255 characters
- *   - IX_ETH_DB_MAC_ADDR_PROPERTY  - 6 bytes are copied from the source location
- *   - IX_ETH_DB_BOOL_PROPERTY      - 4 bytes are copied from the source location; the only allowed values are true (1L) and false (0L)
- *
- * @see ixEthDBFeaturePropertySet
- *
- * @warning IX_ETH_DB_QOS_QUEUE_CONFIGURATION_COMPLETE is provided for EthAcc internal use; 
- * do not attempt to set this property directly
- *
- * @param portID @ref IxEthDBPortId [in] - ID of the port 
- * @param feature @ref IxEthDBFeature [in] - EthDB feature for which the property is set
- * @param property @ref IxEthDBProperty [in] - property identifier
- * @param value void [in] - location where the property value is to be copied from
- * 
- * @retval IX_ETH_DB_SUCCESS operation completed successfully
- * @retval IX_ETH_DB_INVALID_PORT portID is not a valid port identifier
- * @retval IX_ETH_DB_INVALID_ARG invalid property identifier, <i>value</i> pointer, or invalid property value
- */
-IX_ETH_DB_PUBLIC 
-IxEthDBStatus ixEthDBFeaturePropertySet(IxEthDBPortId portID, IxEthDBFeature feature, IxEthDBProperty property, void *value);
-
-/**
- * @ingroup IxEthDB
- *
- * @fn IxEthDBStatus ixEthDBDatabaseClear(IxEthDBPortId portID, IxEthDBRecordType recordType)
- *
- * @brief Deletes a set of record types from the Ethernet Database
- *
- * This function deletes all the records of certain types (specified in the recordType filter)
- * associated with a port. Additionally, the IX_ETH_DB_ALL_PORTS value can be used as port ID
- * to indicate that the specified record types should be deleted for all the ports.
- *
- * The record type filter can be an ORed combination of the following types:
- *
- * <caption> Record types </caption>
- *    - IX_ETH_DB_FILTERING_RECORD      <table><caption> Filtering record </caption>
- *                                               <tr><td> MAC address <td> static/dynamic type <td> age </tr>
- *                                             </table> 
- *
- *    - IX_ETH_DB_FILTERING_VLAN_RECORD <table><caption> VLAN-enabled filtering record </caption>
- *                                               <tr><td> MAC address <td> static/dynamic type <td> age <td> 802.1Q tag </tr>
- *                                             </table> 
- *
- *    - IX_ETH_DB_WIFI_RECORD           <table><caption> WiFi header conversion record </caption>
- *                                                <tr><td> MAC address <td> optional gateway MAC address <td> </tr>
- *                                             </table>
- *
- *    - IX_ETH_DB_FIREWALL_RECORD       <table><caption> Firewall record </caption>
- *                                                <tr><td> MAC address </tr>
- *                                             </table>
- *    - IX_ETH_DB_ALL_RECORD_TYPES
- * 
- * Any combination of the above types is valid e.g. 
- *
- *    (IX_ETH_DB_FILTERING_RECORD | IX_ETH_DB_FILTERING_VLAN_RECORD | IX_ETH_DB_FIREWALL_RECORD), 
- *
- * although some might be redundant (it is not an error to do so) e.g.
- *
- *    (IX_ETH_DB_FILTERING_RECORD | IX_ETH_DB_ALL_RECORD_TYPES)
- *
- * @param portID @ref IxEthDBPortId [in] - ID of the port
- * @param recordType @ref IxEthDBRecordType [in] - record type filter
- * 
- * @retval IX_ETH_DB_SUCCESS operation completed successfully
- * @retval IX_ETH_DB_INVALID_PORT portID is not a valid port identifier
- * @retval IX_ETH_DB_INVALID_ARG invalid <i>recordType</i> filter
- *
- * @note If the record type filter contains any unrecognized value (hence the 
- * IX_ETH_DB_INVALID_ARG error value is returned) no actual records will be deleted.
- */
-IX_ETH_DB_PUBLIC 
-IxEthDBStatus ixEthDBDatabaseClear(IxEthDBPortId portID, IxEthDBRecordType recordType);
-
-/**
- * @ingroup IxEthDB
- *
- * @fn IxEthDBStatus ixEthDBWiFiStationEntryAdd(IxEthDBPortId portID, IxEthDBMacAddr *macAddr)
- *
- * @brief Adds an "Access Point to Station" record to the database, for 802.3 => 802.11 frame 
- * header conversion
- *
- * Frame header conversion is controlled by the set of MAC addresses
- * added using @ref ixEthDBWiFiStationEntryAdd and @ref ixEthDBWiFiAccessPointEntryAdd.
- * Conversion arguments are added using @ref ixEthDBWiFiFrameControlSet, 
- * @ref ixEthDBWiFiDurationIDSet and @ref ixEthDBWiFiBBSIDSet.
- *
- * Note that adding the same MAC address twice will not return an error
- * (but will not accomplish anything either), while re-adding a record previously added
- * as an "Access Point to Access Point" will migrate the record to the "Access Point
- * to Station" type.
- *
- * @param portID @ref IxEthDBPortId [in] - ID of the port 
- * @param macAddr @ref IxEthDBMacAddr [in] - MAC address to add
- * 
- * @retval IX_ETH_DB_SUCCESS operation completed successfully
- * @retval IX_ETH_DB_INVALID_PORT portID is not a valid port identifier
- * @retval IX_ETH_DB_INVALID_ARG macAddr is an invalid pointer
- * @retval IX_ETH_DB_FEATURE_UNAVAILABLE WiFi feature not enabled 
- * @retval IX_ETH_DB_INVALID_ARG invalid <i>macAddr</i> pointer argument
- * @retval IX_ETH_DB_NOMEM maximum number of records reached
- * @retval IX_ETH_DB_BUSY lock condition or transaction in progress, try again later
- */
-IX_ETH_DB_PUBLIC 
-IxEthDBStatus ixEthDBWiFiStationEntryAdd(IxEthDBPortId portID, IxEthDBMacAddr *macAddr);
-
-/**
- * @ingroup IxEthDB
- *
- * @fn IxEthDBStatus ixEthDBWiFiAccessPointEntryAdd(IxEthDBPortId portID, IxEthDBMacAddr *macAddr, IxEthDBMacAddr *gatewayMacAddr)
- *
- * @brief Adds an "Access Point to Access Point" record to the database
- *
- * @see ixEthDBWiFiStationEntryAdd
- *
- * Note that adding the same MAC address twice will simply overwrite the previously
- * defined gateway MAC address value in the same record, if the record was previously of the
- * "Access Point to Access Point" type.
- *
- * Re-adding a MAC address as "Access Point to Access Point", which was previously added as 
- * "Access Point to Station" will migrate the record type to "Access Point to Access Point" and
- * record the gateway MAC address.
- *
- * @param portID @ref IxEthDBPortId [in] - ID of the port 
- * @param macAddr @ref IxEthDBMacAddr [in] - MAC address to add
- * @param gatewayMacAddr @ref IxEthDBMacAddr [in] - MAC address of the gateway Access Point
- * 
- * @retval IX_ETH_DB_SUCCESS operation completed successfully
- * @retval IX_ETH_DB_INVALID_PORT portID is not a valid port identifier
- * @retval IX_ETH_DB_PORT_UNINITIALIZED port is not initialized
- * @retval IX_ETH_DB_INVALID_ARG macAddr is an invalid pointer
- * @retval IX_ETH_DB_FEATURE_UNAVAILABLE WiFi feature not enabled 
- * @retval IX_ETH_DB_INVALID_ARG invalid <i>macAddr</i> or <i>gatewayMacAddr</i> pointer argument
- * @retval IX_ETH_DB_NOMEM maximum number of records reached
- * @retval IX_ETH_DB_BUSY lock condition or transaction in progress, try again later
- */
-IX_ETH_DB_PUBLIC 
-IxEthDBStatus ixEthDBWiFiAccessPointEntryAdd(IxEthDBPortId portID, IxEthDBMacAddr *macAddr, IxEthDBMacAddr *gatewayMacAddr);
-
-/**
- * @ingroup IxEthDB
- *
- * @fn IxEthDBStatus ixEthDBWiFiEntryRemove(IxEthDBPortId portID, IxEthDBMacAddr *macAddr)
- *
- * @brief Removes a WiFi station record
- *
- * This function removes both types of WiFi records ("Access Point to Station" and
- * "Access Point to Access Point").
- * 
- * @param portID @ref IxEthDBPortId [in] - ID of the port 
- * @param macAddr @ref IxEthDBMacAddr [in] - MAC address to remove
- * 
- * @retval IX_ETH_DB_SUCCESS operation completed successfully
- * @retval IX_ETH_DB_INVALID_PORT portID is not a valid port identifier
- * @retval IX_ETH_DB_PORT_UNINITIALIZED port is not initialized
- * @retval IX_ETH_DB_INVALID_ARG invalid <i>macAddr</i> pointer argument
- * @retval IX_ETH_DB_NO_SUCH_ADDR specified address was not found in the database
- * @retval IX_ETH_DB_FEATURE_UNAVAILABLE WiFi feature not enabled 
- * @retval IX_ETH_DB_BUSY lock condition or transaction in progress, try again later
- */
-IX_ETH_DB_PUBLIC 
-IxEthDBStatus ixEthDBWiFiEntryRemove(IxEthDBPortId portID, IxEthDBMacAddr *macAddr);
-
-/**
- * @ingroup IxEthDB
- *
- * @fn IxEthDBStatus ixEthDBWiFiConversionTableDownload(IxEthDBPortId portID)
- *
- * @brief Downloads the MAC address table for 802.3 => 802.11 frame header
- * conversion to the NPE
- *
- * Note that the frame conversion MAC address table must be individually downloaded
- * to each NPE for which the frame header conversion feature is enabled (i.e. it
- * is not possible to specify IX_ETH_DB_ALL_PORTS).
- *
- * @param portID @ref IxEthDBPortId [in] - ID of the port 
- * 
- * @retval IX_ETH_DB_SUCCESS operation completed successfully
- * @retval IX_ETH_DB_PORT_UNINITIALIZED port not initialized
- * @retval IX_ETH_DB_INVALID_PORT portID is not a valid port identifier
- * @retval IX_ETH_DB_FEATURE_UNAVAILABLE WiFi feature not enabled
- * @retval IX_ETH_DB_FAIL unknown OS or NPE communication error
- */
-IX_ETH_DB_PUBLIC 
-IxEthDBStatus ixEthDBWiFiConversionTableDownload(IxEthDBPortId portID);
-
-/**
- * @ingroup IxEthDB
- *
- * @fn IxEthDBStatus ixEthDBWiFiFrameControlSet(IxEthDBPortId portID, UINT16 frameControl)
- *
- * @brief Sets the GlobalFrameControl field
- *
- * The GlobalFrameControl field is a 2-byte value inserted in the <i>Frame Control</i>
- * field for all 802.3 to 802.11 frame header conversions
- * 
- * @param portID @ref IxEthDBPortId [in] - ID of the port
- * @param frameControl UINT16 [in] - GlobalFrameControl value
- * 
- * @retval IX_ETH_DB_SUCCESS operation completed successfully
- * @retval IX_ETH_DB_INVALID_PORT portID is not a valid port identifier
- * @retval IX_ETH_DB_PORT_UNINITIALIZED port not initialized
- * @retval IX_ETH_DB_FEATURE_UNAVAILABLE WiFi feature not enabled
- * @retval IX_ETH_DB_FAIL unknown OS or NPE communication error
- */
-IX_ETH_DB_PUBLIC 
-IxEthDBStatus ixEthDBWiFiFrameControlSet(IxEthDBPortId portID, UINT16 frameControl);
-
-/**
- * @ingroup IxEthDB
- *
- * @fn IxEthDBStatus ixEthDBWiFiDurationIDSet(IxEthDBPortId portID, UINT16 durationID)
- *
- * @brief Sets the GlobalDurationID field
- *
- * The GlobalDurationID field is a 2-byte value inserted in the <i>Duration/ID</i>
- * field for all 802.3 to 802.11 frame header conversions
- *
- * @param portID @ref IxEthDBPortId [in] - ID of the port 
- * @param durationID UINT16 [in] - GlobalDurationID field
- * 
- * @retval IX_ETH_DB_SUCCESS operation completed successfully
- * @retval IX_ETH_DB_INVALID_PORT portID is not a valid port identifier
- * @retval IX_ETH_DB_PORT_UNINITIALIZED port not initialized
- * @retval IX_ETH_DB_FEATURE_UNAVAILABLE WiFi feature not enabled
- * @retval IX_ETH_DB_FAIL unknown OS or NPE communication error
- */
-IX_ETH_DB_PUBLIC 
-IxEthDBStatus ixEthDBWiFiDurationIDSet(IxEthDBPortId portID, UINT16 durationID);
-
-/**
- * @ingroup IxEthDB
- *
- * @fn IxEthDBStatus ixEthDBWiFiBBSIDSet(IxEthDBPortId portID, IxEthDBMacAddr *bbsid)
- *
- * @brief Sets the BBSID field
- *
- * The BBSID field is a 6-byte value which
- * identifies the infrastructure of the service set managed 
- * by the Access Point having the IXP400 as its processor. The value
- * is written in the <i>BBSID</i> field of the 802.11 frame header.
- * The BBSID value is the MAC address of the Access Point.
- *
- * @param portID @ref IxEthDBPortId [in] - ID of the port 
- * @param bbsid @ref IxEthDBMacAddr [in] - pointer to 6 bytes containing the BSSID
- * 
- * @retval IX_ETH_DB_SUCCESS operation completed successfully
- * @retval IX_ETH_DB_INVALID_PORT portID is not a valid port identifier
- * @retval IX_ETH_DB_PORT_UNINITIALIZED port not initialized
- * @retval IX_ETH_DB_INVALID_ARG invalid <i>bbsid</i> pointer argument
- * @retval IX_ETH_DB_FEATURE_UNAVAILABLE WiFi feature not enabled
- * @retval IX_ETH_DB_FAIL unknown OS or NPE communication error
- */
-IX_ETH_DB_PUBLIC 
-IxEthDBStatus ixEthDBWiFiBBSIDSet(IxEthDBPortId portID, IxEthDBMacAddr *bbsid);
-
-/**
- * @ingroup IxEthDB
- *
- * @fn IxEthDBStatus ixEthDBSpanningTreeBlockingStateSet(IxEthDBPortId portID, BOOL blocked)
- *
- * @brief Sets the STP blocked/unblocked state for a port
- *
- * @param portID @ref IxEthDBPortId [in] - ID of the port 
- * @param blocked BOOL [in] - true to set the port as STP blocked, false to set it as unblocked
- * 
- * @retval IX_ETH_DB_SUCCESS operation completed successfully
- * @retval IX_ETH_DB_INVALID_PORT portID is not a valid port identifier
- * @retval IX_ETH_DB_PORT_UNINITIALIZED port not initialized
- * @retval IX_ETH_DB_FEATURE_UNAVAILABLE Spanning Tree Protocol feature not enabled
- * @retval IX_ETH_DB_FAIL unknown OS or NPE communication error
- */
-IX_ETH_DB_PUBLIC 
-IxEthDBStatus ixEthDBSpanningTreeBlockingStateSet(IxEthDBPortId portID, BOOL blocked);
-
-/**
- * @ingroup IxEthDB
- *
- * @fn IxEthDBStatus ixEthDBSpanningTreeBlockingStateGet(IxEthDBPortId portID, BOOL *blocked)
- *
- * @brief Retrieves the STP blocked/unblocked state for a port
- *
- * @param portID @ref IxEthDBPortId [in] - ID of the port 
- * @param blocked BOOL * [in] - set to true if the port is STP blocked, false otherwise
- * 
- * @retval IX_ETH_DB_SUCCESS operation completed successfully
- * @retval IX_ETH_DB_INVALID_PORT portID is not a valid port identifier
- * @retval IX_ETH_DB_PORT_UNINITIALIZED port not initialized
- * @retval IX_ETH_DB_INVALID_ARG invalid <i>blocked</i> pointer argument
- * @retval IX_ETH_DB_FEATURE_UNAVAILABLE Spanning Tree Protocol feature not enabled
- */
-IX_ETH_DB_PUBLIC 
-IxEthDBStatus ixEthDBSpanningTreeBlockingStateGet(IxEthDBPortId portID, BOOL *blocked);
-
-/**
- * @ingroup IxEthDB
- *
- * @fn IxEthDBStatus ixEthDBFirewallModeSet(IxEthDBPortId portID, IxEthDBFirewallMode mode)
- *
- * @brief Sets the firewall mode to use white or black listing
- *
- * When enabled, the NPE MAC address based firewall support operates in two modes:
- *
- * - white-list mode (MAC address based admission) 
- *    - <i>mode</i> set to IX_ETH_DB_FIREWALL_WHITE_LIST
- *    - only packets originating from MAC addresses contained in the firewall address list
- *      are allowed on the Rx path
- * - black-list mode (MAC address based blocking)  
- *    - <i>mode</i> set to IX_ETH_DB_FIREWALL_BLACK_LIST
- *    - packets originating from MAC addresses contained in the firewall address list
- *      are discarded
- *
- * @param portID @ref IxEthDBPortId [in] - ID of the port 
- * @param mode @ref IxEthDBFirewallMode [in] - firewall mode (IX_ETH_DB_FIREWALL_WHITE_LIST or IX_ETH_DB_FIREWALL_BLACK_LIST)
- *
- * @note by default the firewall operates in black-list mode with an empty address
- * list, hence it doesn't filter any packets
- * 
- * @retval IX_ETH_DB_SUCCESS operation completed successfully
- * @retval IX_ETH_DB_INVALID_PORT portID is not a valid port identifier
- * @retval IX_ETH_DB_PORT_UNINITIALIZED port not initialized
- * @retval IX_ETH_DB_FEATURE_UNAVAILABLE Firewall feature not enabled 
- * @retval IX_ETH_DB_INVALID_ARGUMENT <i>mode</i> argument is not a valid firewall configuration mode
- * @retval IX_ETH_DB_FAIL unknown OS or NPE communication error
-*/
-IX_ETH_DB_PUBLIC 
-IxEthDBStatus ixEthDBFirewallModeSet(IxEthDBPortId portID, IxEthDBFirewallMode mode);
-
-/**
- * @ingroup IxEthDB
- *
- * @fn ixEthDBFirewallInvalidAddressFilterEnable(IxEthDBPortId portID, BOOL enable)
- *
- * @brief Enables or disables invalid MAC address filtering
- *
- * According to IEEE802 it is illegal for a source address to be a multicast
- * or broadcast address. If this feature is enabled the NPE inspects the source
- * MAC addresses of incoming frames and discards them if invalid addresses are
- * detected.
- *
- * By default this service is enabled, if the firewall feature is supported by the
- * NPE image.
- *
- * @param portID ID of the port 
- * @param enable true to enable invalid MAC address filtering and false to disable it
- * 
- * @retval IX_ETH_DB_SUCCESS operation completed successfully
- * @retval IX_ETH_DB_INVALID_PORT portID is not a valid port identifier
- * @retval IX_ETH_DB_PORT_UNINITIALIZED port not initialized
- * @retval IX_ETH_DB_FEATURE_UNAVAILABLE Firewall feature not enabled 
- * @retval IX_ETH_DB_FAIL unknown OS or NPE communication error
- */
-IX_ETH_DB_PUBLIC 
-IxEthDBStatus ixEthDBFirewallInvalidAddressFilterEnable(IxEthDBPortId portID, BOOL enable);
-
-/**
- * @ingroup IxEthDB
- *
- * @fn IxEthDBStatus ixEthDBFirewallEntryAdd(IxEthDBPortId portID, IxEthDBMacAddr *macAddr)
- *
- * @brief Adds a MAC address to the firewall address list
- *
- * Note that adding the same MAC address twice will not return an error
- * but will not actually accomplish anything.
- *
- * The firewall MAC address list has a limited number of entries; once
- * the maximum number of entries has been reached this function will failed
- * to add more addresses, returning IX_ETH_DB_NOMEM.
- *
- * @param portID @ref IxEthDBPortId [in] - ID of the port 
- * @param macAddr @ref IxEthDBMacAddr [in] - MAC address to be added
- * 
- * @retval IX_ETH_DB_SUCCESS operation completed successfully
- * @retval IX_ETH_DB_INVALID_PORT portID is not a valid port identifier
- * @retval IX_ETH_DB_PORT_UNINITIALIZED port not initialized
- * @retval IX_ETH_DB_INVALID_ARG invalid <i>macAddr</i> pointer argument
- * @retval IX_ETH_DB_NOMEM maximum number of records reached
- * @retval IX_ETH_DB_BUSY lock condition or transaction in progress, try again later
- * @retval IX_ETH_DB_FEATURE_UNAVAILABLE Firewall feature not enabled 
- */
-IX_ETH_DB_PUBLIC 
-IxEthDBStatus ixEthDBFirewallEntryAdd(IxEthDBPortId portID, IxEthDBMacAddr *macAddr);
-
-/**
- * @ingroup IxEthDB
- *
- * @fn IxEthDBStatus ixEthDBFirewallEntryRemove(IxEthDBPortId portID, IxEthDBMacAddr *macAddr)
- *
- * @brief Removes a MAC address from the firewall address list
- *
- * @param portID @ref IxEthDBPortId [in] - ID of the port 
- * @param macAddr @ref IxEthDBMacAddr [in] - MAC address to be removed
- * 
- * @retval IX_ETH_DB_SUCCESS operation completed successfully
- * @retval IX_ETH_DB_INVALID_PORT portID is not a valid port identifier
- * @retval IX_ETH_DB_PORT_UNINITIALIZED port not initialized
- * @retval IX_ETH_DB_INVALID_ARG invalid <i>macAddr</i> pointer argument
- * @retval IX_ETH_DB_NO_SUCH_ADDR address not found
- * @retval IX_ETH_DB_FEATURE_UNAVAILABLE Firewall feature not enabled 
- */
-IX_ETH_DB_PUBLIC 
-IxEthDBStatus ixEthDBFirewallEntryRemove(IxEthDBPortId portID, IxEthDBMacAddr *macAddr);
-
-/**
- * @ingroup IxEthDB
- *
- * @fn IxEthDBStatus ixEthDBFirewallTableDownload(IxEthDBPortId portID)
- *
- * @brief Downloads the MAC firewall table to a port
- *
- * @param portID ID of the port 
- * 
- * @retval IX_ETH_DB_SUCCESS operation completed successfully
- * @retval IX_ETH_DB_INVALID_PORT portID is not a valid port identifier
- * @retval IX_ETH_DB_PORT_UNINITIALIZED port not initialized
- * @retval IX_ETH_DB_FEATURE_UNAVAILABLE Firewall feature not enabled 
- * @retval IX_ETH_DB_FAIL unknown OS or NPE communication error
- */
-IX_ETH_DB_PUBLIC 
-IxEthDBStatus ixEthDBFirewallTableDownload(IxEthDBPortId portID);
-
-/**
- * @ingroup IxEthDB
- *
- * @fn IxEthDBStatus ixEthDBUserFieldSet(IxEthDBRecordType recordType, IxEthDBMacAddr *macAddr, IxEthDBPortId portID, IxEthDBVlanId vlanID, void *field)
- *
- * @brief Adds a user-defined field to a database record
- *
- * This function associates a user-defined field to a database record.
- * The user-defined field is passed as a <i>(void *)</i> parameter, hence it can be used
- * for any purpose (such as identifying a structure). Retrieving the user-defined field from
- * a record is done using @ref ixEthDBUserFieldGet. Note that EthDB never uses the user-defined
- * field for any internal operation and it is not aware of the significance of its contents. The
- * field is only stored as a pointer.
- *
- * The database record is identified using a combination of the given parameters, depending on the record type.
- * All the record types require the record MAC address.
- *
- * - IX_ETH_DB_FILTERING_RECORD requires only the MAC address
- * - IX_ETH_DB_VLAN_FILTERING_RECORD requires the MAC address and the VLAN ID
- * - IX_ETH_DB_WIFI_RECORD requires the MAC address and the portID
- * - IX_ETH_DB_FIREWALL_RECORD requires the MAC address and the portID
- *
- * Please note that if a parameter is not required it is completely ignored (it does not undergo parameter checking).
- * The user-defined field can be cleared using a <b>NULL</b> <i>field</i> parameter.
- *
- * @param recordType @ref IxEthDBRecordType [in] - type of record (can be IX_ETH_DB_FILTERING_RECORD, 
- * IX_ETH_DB_FILTERING_VLAN_RECORD, IX_ETH_DB_WIFI_RECORD or IX_ETH_DB_FIREWALL_RECORD)
- * @param portID @ref IxEthDBPortId [in] - ID of the port (required only for WIFI and FIREWALL records) 
- * @param macAddr @ref IxEthDBMacAddr * [in] - MAC address of the record
- * @param vlanID @ref IxEthDBVlanId [in] - VLAN ID of the record (required only for FILTERING_VLAN records)
- * @param field void * [in] - user defined field
- * 
- * @retval IX_ETH_DB_SUCCESS operation completed successfully
- * @retval IX_ETH_DB_INVALID_PORT portID was required but it is not a valid port identifier
- * @retval IX_ETH_DB_INVALID_ARG invalid <i>macAddr</i> pointer argument
- * @retval IX_ETH_DB_NO_SUCH_ADDR record not found
- */
-IX_ETH_DB_PUBLIC 
-IxEthDBStatus ixEthDBUserFieldSet(IxEthDBRecordType recordType, IxEthDBMacAddr *macAddr, IxEthDBPortId portID, IxEthDBVlanId vlanID, void *field);
-
-/**
- * @ingroup IxEthDB
- *
- * @fn IxEthDBStatus ixEthDBUserFieldGet(IxEthDBRecordType recordType, IxEthDBMacAddr *macAddr, IxEthDBPortId portID, IxEthDBVlanId vlanID, void **field)
- *
- * @brief Retrieves a user-defined field from a database record
- *
- * The database record is identified using a combination of the given parameters, depending on the record type.
- * All the record types require the record MAC address.
- *
- * - IX_ETH_DB_FILTERING_RECORD requires only the MAC address
- * - IX_ETH_DB_VLAN_FILTERING_RECORD requires the MAC address and the VLAN ID
- * - IX_ETH_DB_WIFI_RECORD requires the MAC address and the portID
- * - IX_ETH_DB_FIREWALL_RECORD requires the MAC address and the portID
- *
- * Please note that if a parameter is not required it is completely ignored (it does not undergo parameter checking).
- *
- * If no user-defined field was registered with the specified record then <b>NULL</b> will be written
- * at the location specified by <i>field</i>.
- *
- * @param recordType type of record (can be IX_ETH_DB_FILTERING_RECORD, IX_ETH_DB_FILTERING_VLAN_RECORD, IX_ETH_DB_WIFI_RECORD 
- * or IX_ETH_DB_FIREWALL_RECORD)
- * @param portID ID of the port (required only for WIFI and FIREWALL records) 
- * @param macAddr MAC address of the record
- * @param vlanID VLAN ID of the record (required only for FILTERING_VLAN records)
- * @param field location to write the user defined field into
- * 
- * @retval IX_ETH_DB_SUCCESS operation completed successfully
- * @retval IX_ETH_DB_INVALID_PORT portID was required but it is not a valid port identifier
- * @retval IX_ETH_DB_INVALID_ARG invalid <i>macAddr</i> or <i>field</i> pointer arguments
- * @retval IX_ETH_DB_NO_SUCH_ADDR record not found
- */
-IX_ETH_DB_PUBLIC 
-IxEthDBStatus ixEthDBUserFieldGet(IxEthDBRecordType recordType, IxEthDBMacAddr *macAddr, IxEthDBPortId portId, IxEthDBVlanId vlanID, void **field);
-
-/**
- * @}
- */
-
-#endif /* IxEthDB_H */
diff --git a/drivers/net/npe/include/IxEthDBLocks_p.h b/drivers/net/npe/include/IxEthDBLocks_p.h
deleted file mode 100644
index 91ab441b26..0000000000
--- a/drivers/net/npe/include/IxEthDBLocks_p.h
+++ /dev/null
@@ -1,98 +0,0 @@
-/**
- * @file IxEthAccDBLocks_p.h
- *
- * @brief Definition of transaction lock stacks and lock utility macros
- * 
- * @par
- * IXP400 SW Release version 2.0
- * 
- * -- Copyright Notice --
- * 
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- * 
- * @par
- * SPDX-License-Identifier:	BSD-3-Clause
- * @par
- * -- End of Copyright Notice --
- */
-
-#ifndef IxEthAccDBLocks_p_H
-#define IxEthAccDBLocks_p_H
-
-#include "IxOsPrintf.h"
-
-/* Lock and lock stacks */
-typedef struct
-{
-    IxOsalFastMutex* locks[MAX_LOCKS];
-    UINT32 stackPointer, basePointer;
-} LockStack;
-
-#define TRY_LOCK(mutex) \
-    { \
-        if (ixOsalFastMutexTryLock(mutex) != IX_SUCCESS) \
-        { \
-            return IX_ETH_DB_BUSY; \
-        } \
-    }
-
-
-#define UNLOCK(mutex) { ixOsalFastMutexUnlock(mutex); }
-
-#define INIT_STACK(stack) \
-    { \
-        (stack)->basePointer  = 0; \
-        (stack)->stackPointer = 0; \
-    }
-
-#define PUSH_LOCK(stack, lock) \
-    { \
-        if ((stack)->stackPointer == MAX_LOCKS) \
-        { \
-            ERROR_LOG("Ethernet DB: maximum number of elements in a lock stack has been exceeded on push, heavy chaining?\n"); \
-            UNROLL_STACK(stack); \
-            \
-            return IX_ETH_DB_NOMEM; \
-        } \
-        \
-        if (ixOsalFastMutexTryLock(lock) == IX_SUCCESS) \
-        { \
-            (stack)->locks[(stack)->stackPointer++] = (lock); \
-        } \
-        else \
-        { \
-            UNROLL_STACK(stack); \
-            \
-            return IX_ETH_DB_BUSY; \
-        } \
-    }
-
-#define POP_LOCK(stack) \
-    { \
-        ixOsalFastMutexUnlock((stack)->locks[--(stack)->stackPointer]); \
-    }
-
-#define UNROLL_STACK(stack) \
-    { \
-        while ((stack)->stackPointer > (stack)->basePointer) \
-        { \
-            POP_LOCK(stack); \
-        } \
-    }
-
-#define SHIFT_STACK(stack) \
-    { \
-        if ((stack)->basePointer == MAX_LOCKS - 1) \
-        { \
-            ERROR_LOG("Ethernet DB: maximum number of elements in a lock stack has been exceeded on shift, heavy chaining?\n"); \
-            UNROLL_STACK(stack); \
-            \
-            return IX_ETH_DB_BUSY; \
-        } \
-        \
-        ixOsalFastMutexUnlock((stack)->locks[(stack)->basePointer++]); \
-    }
-
-#endif /* IxEthAccDBLocks_p_H */
diff --git a/drivers/net/npe/include/IxEthDBLog_p.h b/drivers/net/npe/include/IxEthDBLog_p.h
deleted file mode 100644
index b3576236ff..0000000000
--- a/drivers/net/npe/include/IxEthDBLog_p.h
+++ /dev/null
@@ -1,203 +0,0 @@
-/**
- * @file IxEthDBLog_p.h
- *
- * @brief definitions of log macros and log configuration
- * 
- * @par
- * IXP400 SW Release version 2.0
- * 
- * -- Copyright Notice --
- * 
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- * 
- * @par
- * SPDX-License-Identifier:	BSD-3-Clause
- * @par
- * -- End of Copyright Notice --
- */
-
-#include <IxOsal.h>
-
-#ifdef IX_UNIT_TEST
-#define NULL_PRINT_ROUTINE(format, arg...) /* nothing */
-#else
-#define NULL_PRINT_ROUTINE if(0) printf
-#endif
-
-/***************************************************
- *                 Globals                         *
- ***************************************************/
-/* safe to permanently leave these on */
-#define HAS_ERROR_LOG
-#define HAS_ERROR_IRQ_LOG
-#define HAS_WARNING_LOG
-
-/***************************************************
- *              Log Configuration                  *
- ***************************************************/
-
-/* debug output can be turned on unless specifically
-   declared as a non-debug build */
-#ifndef NDEBUG
-
-#undef HAS_EVENTS_TRACE
-#undef HAS_EVENTS_VERBOSE_TRACE
-
-#undef HAS_SUPPORT_TRACE
-#undef HAS_SUPPORT_VERBOSE_TRACE
-
-#undef HAS_NPE_TRACE
-#undef HAS_NPE_VERBOSE_TRACE
-#undef HAS_DUMP_NPE_TREE
-
-#undef HAS_UPDATE_TRACE
-#undef HAS_UPDATE_VERBOSE_TRACE
-
-#endif /* NDEBUG */
-
-
-/***************************************************
- *              Log Macros                         *
- ***************************************************/
-
-/************** Globals ******************/
-
-#ifdef HAS_ERROR_LOG
-
-    #define ERROR_LOG printf
-
-#else
-
-    #define ERROR_LOG NULL_PRINT_ROUTINE
-
-#endif
-
-#ifdef HAS_ERROR_IRQ_LOG
-
-    #define ERROR_IRQ_LOG(format, arg1, arg2, arg3, arg4, arg5, arg6) ixOsalLog(IX_OSAL_LOG_LVL_ERROR, IX_OSAL_LOG_DEV_STDOUT, format, arg1, arg2, arg3, arg4, arg5, arg6)
-
-#else
-
-    #define ERROR_IRQ_LOG(format, arg1, arg2, arg3, arg4, arg5, arg6) /* nothing */
-
-#endif
-
-#ifdef HAS_WARNING_LOG
-
-    #define WARNING_LOG printf
-
-#else
-
-    #define WARNING_LOG NULL_PRINT_ROUTINE
-
-#endif
-
-/************** Events *******************/
-
-#ifdef HAS_EVENTS_TRACE
-
-    #define IX_ETH_DB_EVENTS_TRACE     printf
-    #define IX_ETH_DB_IRQ_EVENTS_TRACE(format, arg1, arg2, arg3, arg4, arg5, arg6) ixOsalLog(IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT, format, arg1, arg2, arg3, arg4, arg5, arg6)
-
-    #ifdef HAS_EVENTS_VERBOSE_TRACE
-
-        #define IX_ETH_DB_EVENTS_VERBOSE_TRACE printf
-    
-    #else
-
-        #define IX_ETH_DB_EVENTS_VERBOSE_TRACE NULL_PRINT_ROUTINE
-
-    #endif /* HAS_EVENTS_VERBOSE_TRACE */
-
-#else
-
-    #define IX_ETH_DB_EVENTS_TRACE         NULL_PRINT_ROUTINE
-    #define IX_ETH_DB_EVENTS_VERBOSE_TRACE NULL_PRINT_ROUTINE
-    #define IX_ETH_DB_IRQ_EVENTS_TRACE(format, arg1, arg2, arg3, arg4, arg5, arg6) /* nothing */
-
-#endif /* HAS_EVENTS_TRACE */
-
-/************** Support *******************/
-
-#ifdef HAS_SUPPORT_TRACE
-
-    #define IX_ETH_DB_SUPPORT_TRACE     printf
-    #define IX_ETH_DB_SUPPORT_IRQ_TRACE(format, arg1, arg2, arg3, arg4, arg5, arg6) ixOsalLog(IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT, format, arg1, arg2, arg3, arg4, arg5, arg6)
-
-    #ifdef HAS_SUPPORT_VERBOSE_TRACE
-
-        #define IX_ETH_DB_SUPPORT_VERBOSE_TRACE printf
-
-    #else
-
-        #define IX_ETH_DB_SUPPORT_VERBOSE_TRACE NULL_PRINT_ROUTINE
-
-    #endif /* HAS_SUPPORT_VERBOSE_TRACE */
-
-#else
-
-    #define IX_ETH_DB_SUPPORT_TRACE         NULL_PRINT_ROUTINE
-    #define IX_ETH_DB_SUPPORT_VERBOSE_TRACE NULL_PRINT_ROUTINE
-    #define IX_ETH_DB_SUPPORT_IRQ_TRACE(format, arg1, arg2, arg3, arg4, arg5, arg6) /* nothing */
-
-#endif /* HAS_SUPPORT_TRACE */
-
-/************** NPE Adaptor *******************/
-
-#ifdef HAS_NPE_TRACE
-
-    #define IX_ETH_DB_NPE_TRACE     printf
-    #define IX_ETH_DB_NPE_IRQ_TRACE(format, arg1, arg2, arg3, arg4, arg5, arg6) ixOsalLog(IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT, format, arg1, arg2, arg3, arg4, arg5, arg6)
-
-    #ifdef HAS_NPE_VERBOSE_TRACE
-
-        #define IX_ETH_DB_NPE_VERBOSE_TRACE printf
-
-    #else
-
-        #define IX_ETH_DB_NPE_VERBOSE_TRACE NULL_PRINT_ROUTINE
-
-    #endif /* HAS_NPE_VERBOSE_TRACE */
-
-#else
-
-    #define IX_ETH_DB_NPE_TRACE         NULL_PRINT_ROUTINE
-    #define IX_ETH_DB_NPE_VERBOSE_TRACE NULL_PRINT_ROUTINE
-    #define IX_ETH_DB_NPE_IRQ_TRACE(format, arg1, arg2, arg3, arg4, arg5, arg6) /* nothing */
-
-#endif /* HAS_NPE_TRACE */
-
-#ifdef HAS_DUMP_NPE_TREE
-
-#define IX_ETH_DB_NPE_DUMP_ELT(eltBaseAddress, eltSize) ixEthELTDumpTree(eltBaseAddress, eltSize)
-
-#else
-
-#define IX_ETH_DB_NPE_DUMP_ELT(eltBaseAddress, eltSize) /* nothing */
-
-#endif /* HAS_DUMP_NPE_TREE */
-
-/************** Port Update *******************/
-
-#ifdef HAS_UPDATE_TRACE
-
-    #define IX_ETH_DB_UPDATE_TRACE printf
-
-    #ifdef HAS_UPDATE_VERBOSE_TRACE
-
-        #define IX_ETH_DB_UPDATE_VERBOSE_TRACE printf
-
-    #else
-
-        #define IX_ETH_DB_UPDATE_VERBOSE_TRACE NULL_PRINT_ROUTINE
-
-    #endif
-
-#else /* HAS_UPDATE_VERBOSE_TRACE */
-
-    #define IX_ETH_DB_UPDATE_TRACE         NULL_PRINT_ROUTINE
-    #define IX_ETH_DB_UPDATE_VERBOSE_TRACE NULL_PRINT_ROUTINE
-
-#endif /* HAS_UPDATE_TRACE */
diff --git a/drivers/net/npe/include/IxEthDBMessages_p.h b/drivers/net/npe/include/IxEthDBMessages_p.h
deleted file mode 100644
index 5907fd59e2..0000000000
--- a/drivers/net/npe/include/IxEthDBMessages_p.h
+++ /dev/null
@@ -1,234 +0,0 @@
-/**
- * @file IxEthDBMessages_p.h
- *
- * @brief Definitions of NPE messages
- *
- * @par
- * IXP400 SW Release version 2.0
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * SPDX-License-Identifier:	BSD-3-Clause
- * @par
- * -- End of Copyright Notice --
- */
-
-#ifndef IxEthDBMessages_p_H
-#define IxEthDBMessages_p_H
-
-#include <IxEthNpe.h>
-#include <IxOsCacheMMU.h>
-#include "IxEthDB_p.h"
-
-/* events watched by the Eth event processor */
-#define IX_ETH_DB_MIN_EVENT_ID        (IX_ETHNPE_EDB_GETMACADDRESSDATABASE)
-#define IX_ETH_DB_MAX_EVENT_ID        (IX_ETHNPE_PC_SETAPMACTABLE)
-
-/* macros to fill and extract data from NPE messages - place any endian conversions here */
-#define RESET_ELT_MESSAGE(message) { memset((void *) &(message), 0, sizeof((message))); }
-#define NPE_MSG_ID(msg) ((msg).data[0] >> 24)
-
-#define FILL_SETPORTVLANTABLEENTRY_MSG(message, portID, setOffset, vlanMembershipSet, ttiSet) \
-    do { \
-        message.data[0] = (IX_ETHNPE_VLAN_SETPORTVLANTABLEENTRY << 24) | (portID << 16) | (setOffset * 2); \
-        message.data[1] = (vlanMembershipSet << 8) | ttiSet; \
-    } while (0);
-
-#define FILL_SETPORTVLANTABLERANGE_MSG(message, portID, offset, length, zone) \
-    do { \
-        message.data[0] = IX_ETHNPE_VLAN_SETPORTVLANTABLERANGE << 24 | portID << 16 | offset << 9 | length << 1; \
-        message.data[1] = (UINT32) zone; \
-    } while (0);
-
-#define FILL_SETDEFAULTRXVID_MSG(message, portID, tpid, vlanTag) \
-    do { \
-        message.data[0] = (IX_ETHNPE_VLAN_SETDEFAULTRXVID << 24) \
-            | (portID << 16); \
-        \
-        message.data[1] = (tpid << 16) | vlanTag; \
-    } while (0);
-
-#define FILL_SETRXTAGMODE_MSG(message, portID, filterMode, tagMode) \
-    do { \
-        message.data[0] = IX_ETHNPE_VLAN_SETRXTAGMODE << 24 \
-            | portID << 16 \
-            | filterMode << 2 \
-            | tagMode; \
-        \
-        message.data[1] = 0; \
-    } while (0);
-
-#define FILL_SETRXQOSENTRY(message, portID, classIndex, trafficClass, aqmQueue) \
-    do { \
-        message.data[0] = IX_ETHNPE_VLAN_SETRXQOSENTRY << 24 \
-            | portID << 16 \
-            | classIndex; \
-        \
-        message.data[1] = trafficClass << 24 \
-            | 0x1 << 23 \
-            | aqmQueue << 16 \
-            | aqmQueue << 4; \
-    } while (0);
-
-#define FILL_SETPORTIDEXTRACTIONMODE(message, portID, enable) \
-    do { \
-        message.data[0] = IX_ETHNPE_VLAN_SETPORTIDEXTRACTIONMODE << 24 \
-            | portID << 16 \
-            | (enable ? 0x1 : 0x0); \
-        \
-        message.data[1] = 0; \
-    } while (0);
-
-
-#define FILL_SETBLOCKINGSTATE_MSG(message, portID, blocked) \
-    do { \
-        message.data[0] = IX_ETHNPE_STP_SETBLOCKINGSTATE << 24 \
-            | portID << 16 \
-            | (blocked ? 0x1 : 0x0); \
-        \
-        message.data[1] = 0; \
-    } while (0);
-
-#define FILL_SETBBSID_MSG(message, portID, bbsid) \
-    do { \
-        message.data[0] = IX_ETHNPE_PC_SETBBSID << 24 \
-            | portID << 16 \
-            | bbsid->macAddress[0] << 8 \
-            | bbsid->macAddress[1]; \
-        \
-        message.data[1] = bbsid->macAddress[2] << 24 \
-            | bbsid->macAddress[3] << 16 \
-            | bbsid->macAddress[4] << 8 \
-            | bbsid->macAddress[5]; \
-    } while (0);
-
-#define FILL_SETFRAMECONTROLDURATIONID(message, portID, frameControlDurationID) \
-    do { \
-        message.data[0] = (IX_ETHNPE_PC_SETFRAMECONTROLDURATIONID << 24) | (portID << 16); \
-        message.data[1] = frameControlDurationID; \
-    } while (0);
-
-#define FILL_SETAPMACTABLE_MSG(message, zone) \
-    do { \
-        message.data[0] = IX_ETHNPE_PC_SETAPMACTABLE << 24 \
-            | 0 << 8      /* always use index 0 */ \
-            | 64;         /* 32 entries, 8 bytes each, 4 bytes in a word */ \
-        message.data[1] = (UINT32) zone; \
-    } while (0);
-
-#define FILL_SETFIREWALLMODE_MSG(message, portID, epDelta, mode, address) \
-    do { \
-        message.data[0] = IX_ETHNPE_FW_SETFIREWALLMODE << 24 \
-            | portID << 16 \
-            | (epDelta & 0xFF) << 8 \
-            | mode; \
-        \
-        message.data[1] = (UINT32) address; \
-    } while (0);
-
-#define FILL_SETMACADDRESSDATABASE_MSG(message, portID, epDelta, blockCount, address) \
-    do { \
-        message.data[0] = IX_ETHNPE_EDB_SETMACADDRESSSDATABASE << 24 \
-                | (epDelta & 0xFF) << 8 \
-                | (blockCount & 0xFF); \
-        \
-        message.data[1] = (UINT32) address; \
-    } while (0);
-
-#define FILL_GETMACADDRESSDATABASE(message, npeId, zone) \
-    do { \
-        message.data[0] = IX_ETHNPE_EDB_GETMACADDRESSDATABASE << 24; \
-        message.data[1] = (UINT32) zone; \
-    } while (0);
-
-#define FILL_SETMAXFRAMELENGTHS_MSG(message, portID, maxRxFrameSize, maxTxFrameSize) \
-    do { \
-        message.data[0] = IX_ETHNPE_SETMAXFRAMELENGTHS << 24 \
-            | portID << 16 \
-            | ((maxRxFrameSize + 63) / 64) << 8  /* max Rx 64-byte blocks */ \
-            | (maxTxFrameSize + 63) / 64; /* max Tx 64-byte blocks */ \
-        \
-        message.data[1] = maxRxFrameSize << 16 | maxTxFrameSize; \
-    } while (0);
-
-#define FILL_SETPORTADDRESS_MSG(message, portID, macAddress) \
-    do { \
-        message.data[0] = IX_ETHNPE_EDB_SETPORTADDRESS << 24 \
-            | portID << 16 \
-            | macAddress[0] << 8 \
-            | macAddress[1]; \
-        \
-        message.data[1] = macAddress[2] << 24 \
-            | macAddress[3] << 16 \
-            | macAddress[4] << 8 \
-            | macAddress[5]; \
-    } while (0);
-
-/* access to a MAC node in the NPE tree */
-#define NPE_NODE_BYTE(eltNodeAddr, offset)      (((UINT8 *) (eltNodeAddr))[offset])
-
-/* browsing of the implicit linear binary tree structure of the NPE tree */
-#define LEFT_CHILD_OFFSET(offset)   ((offset) << 1)
-#define RIGHT_CHILD_OFFSET(offset)  (((offset) << 1) + 1)
-
-#define IX_EDB_FLAGS_ACTIVE         (0x2)
-#define IX_EDB_FLAGS_VALID          (0x1)
-#define IX_EDB_FLAGS_RESERVED       (0xfc)
-#define IX_EDB_FLAGS_INACTIVE_VALID (0x1)
-
-#define IX_EDB_NPE_NODE_ELT_PORT_ID_OFFSET (6)
-#define IX_EDB_NPE_NODE_ELT_FLAGS_OFFSET   (7)
-#define IX_EDB_NPE_NODE_WIFI_INDEX_OFFSET  (6)
-#define IX_EDB_NPE_NODE_WIFI_FLAGS_OFFSET  (7)
-#define IX_EDB_NPE_NODE_FW_FLAGS_OFFSET    (1)
-#define IX_EDB_NPE_NODE_FW_RESERVED_OFFSET (6)
-#define IX_EDB_NPE_NODE_FW_ADDR_OFFSET     (2)
-
-#define IX_EDB_NPE_NODE_VALID(address)     ((NPE_NODE_BYTE(address, IX_EDB_NPE_NODE_ELT_FLAGS_OFFSET) & IX_EDB_FLAGS_VALID) != 0)
-#define IX_EDB_NPE_NODE_ACTIVE(address)    ((NPE_NODE_BYTE(address, IX_EDB_NPE_NODE_ELT_FLAGS_OFFSET) & IX_EDB_FLAGS_ACTIVE) != 0)
-#define IX_EDB_NPE_NODE_PORT_ID(address)   (NPE_NODE_BYTE(address, IX_EDB_NPE_NODE_ELT_PORT_ID_OFFSET))
-
-/* macros to send messages to the NPEs */
-#define IX_ETHDB_ASYNC_SEND_NPE_MSG(npeId, msg, result) \
-    do { \
-        result = ixNpeMhMessageSend(npeId, msg, IX_NPEMH_SEND_RETRIES_DEFAULT); \
-        \
-        if (result != IX_SUCCESS) \
-        { \
-            ERROR_LOG("DB: Failed to send NPE message\n"); \
-        } \
-    } while (0);
-
-#define IX_ETHDB_SYNC_SEND_NPE_MSG(npeId, msg, result) \
-    do { \
-        result = ixNpeMhMessageWithResponseSend(npeId, msg, msg.data[0] >> 24, ixEthDBNpeMsgAck, IX_NPEMH_SEND_RETRIES_DEFAULT); \
-        \
-        if (result == IX_SUCCESS) \
-        { \
-            result = ixOsalMutexLock(&ixEthDBPortInfo[IX_ETH_DB_NPE_TO_PORT_ID(npeId)].npeAckLock, IX_ETH_DB_NPE_TIMEOUT); \
-            \
-            if (result != IX_SUCCESS) \
-            { \
-                ERROR_LOG("DB: NPE failed to respond within %dms\n", IX_ETH_DB_NPE_TIMEOUT); \
-            } \
-        } \
-        else \
-        { \
-            ERROR_LOG("DB: Failed to send NPE message\n"); \
-        } \
-    } while (0);
-
-#ifndef IX_NDEBUG
-#define IX_ETH_DB_NPE_MSG_HISTORY_DEPTH (100)
-extern IX_ETH_DB_PUBLIC UINT32 npeMsgHistory[IX_ETH_DB_NPE_MSG_HISTORY_DEPTH][2];
-extern IX_ETH_DB_PUBLIC UINT32 npeMsgHistoryLen;
-#endif
-
-#define IX_ETHDB_SEND_NPE_MSG(npeId, msg, result) { LOG_NPE_MSG(msg); IX_ETHDB_SYNC_SEND_NPE_MSG(npeId, msg, result); }
-
-#endif /* IxEthDBMessages_p_H */
diff --git a/drivers/net/npe/include/IxEthDBPortDefs.h b/drivers/net/npe/include/IxEthDBPortDefs.h
deleted file mode 100644
index 9f5e467832..0000000000
--- a/drivers/net/npe/include/IxEthDBPortDefs.h
+++ /dev/null
@@ -1,139 +0,0 @@
-/**
- * @file IxEthDBPortDefs.h
- *
- * @brief Public definition of the ports and port capabilities
- * 
- * @par
- * IXP400 SW Release version 2.0
- * 
- * -- Copyright Notice --
- * 
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- * 
- * @par
- * SPDX-License-Identifier:	BSD-3-Clause
- * @par
- * -- End of Copyright Notice --
- */
-
-/**
- * @defgroup IxEthDBPortDefs IXP400 Ethernet Database Port Definitions (IxEthDBPortDefs)
- *
- * @brief IXP400 Public definition of the ports and port capabilities
- *
- * @{
- */
-
-#ifndef IxEthDBPortDefs_H
-#define IxEthDBPortDefs_H
-
-/** 
- * @brief Port types - currently only Ethernet NPEs are recognized as specific types 
- * All other (user-defined) ports must be specified as IX_ETH_GENERIC
- */
-typedef enum
-{
-    IX_ETH_GENERIC = 0, /**< generic ethernet port */
-    IX_ETH_NPE          /**< specific Ethernet NPE */
-} IxEthDBPortType;
-
-/** 
- * @brief Port capabilities - used by ixEthAccDatabaseMaintenance to decide whether it
- * should manually age entries or not depending on the port capabilities.
- *
- * Ethernet NPEs have aging capabilities, meaning that they will age the entries
- * automatically (by themselves).*/
-typedef enum
-{
-    IX_ETH_NO_CAPABILITIES = 0,   /**< no aging capabilities */
-    IX_ETH_ENTRY_AGING     = 0x1  /**< aging capabilities present */
-} IxEthDBPortCapability;
-
-/** 
- * @brief Port Definition - a structure contains the Port type and capabilities 
- */
-typedef struct
-{
-    IxEthDBPortType type;
-    IxEthDBPortCapability capabilities;
-} IxEthDBPortDefinition;
-
-/** 
- * @brief Port definitions structure, indexed on the port ID
- * @warning Ports 0 and 1 are used by the Ethernet access component therefore
- * it is essential to be left untouched. Port 2 here (WAN) is given as 
- * an example port. The NPE firmware also assumes the NPE B to be
- * the port 0 and NPE C to be the port 1.
- *
- * @note that only 32 ports (0..31) are supported by EthDB
- */
-static const IxEthDBPortDefinition ixEthDBPortDefinitions[] = 
-{
-    /*    id       type              capabilities */
-    {   /* 0 */    IX_ETH_NPE,       IX_ETH_NO_CAPABILITIES },    /* Ethernet NPE B */
-    {   /* 1 */    IX_ETH_NPE,       IX_ETH_NO_CAPABILITIES },    /* Ethernet NPE C */
-    {   /* 2 */    IX_ETH_NPE,       IX_ETH_NO_CAPABILITIES },    /* Ethernet NPE A */
-    {   /* 3 */    IX_ETH_GENERIC,   IX_ETH_NO_CAPABILITIES },    /* WAN port */
-};
-
-/** 
- * @def IX_ETH_DB_NUMBER_OF_PORTS
- * @brief number of supported ports 
- */
-#define IX_ETH_DB_NUMBER_OF_PORTS ARRAY_SIZE(ixEthDBPortDefinitions)
-
-/**
- * @def IX_ETH_DB_UNKNOWN_PORT
- * @brief definition of an unknown port
- */
-#define IX_ETH_DB_UNKNOWN_PORT (0xff)
-
-/** 
- * @def IX_ETH_DB_ALL_PORTS
- * @brief Special port ID indicating all the ports
- * @note This port ID can be used only by a subset of the EthDB API; each
- * function specifically mentions whether this is a valid parameter as the port ID
- */
-#define IX_ETH_DB_ALL_PORTS (IX_ETH_DB_NUMBER_OF_PORTS + 1)
-
-/**
- * @def IX_ETH_DB_PORTS_ASSERTION
- * @brief catch invalid port definitions (<2) with a 
- * compile-time assertion resulting in a duplicate case error. 
- */
-#define IX_ETH_DB_PORTS_ASSERTION { switch(0) { case 0 : ; case 1 : ; case IX_ETH_DB_NUMBER_OF_PORTS : ; }}
-
-/** 
- * @def IX_ETH_DB_CHECK_PORT(portID)
- * @brief safety checks to verify whether the port is invalid or uninitialized
- */
-#define IX_ETH_DB_CHECK_PORT(portID) \
-{ \
-  if ((portID) >= IX_ETH_DB_NUMBER_OF_PORTS) \
-  { \
-      return IX_ETH_DB_INVALID_PORT; \
-  } \
-  \
-  if (!ixEthDBPortInfo[(portID)].enabled) \
-  { \
-      return IX_ETH_DB_PORT_UNINITIALIZED; \
-  } \
-}
-
-/**
- * @def IX_ETH_DB_CHECK_PORT_ALL(portID)
- * @brief safety checks to verify whether the port is invalid or uninitialized; 
- * tolerates the use of IX_ETH_DB_ALL_PORTS
- */
-#define IX_ETH_DB_CHECK_PORT_ALL(portID) \
-{ \
-  if ((portID) != IX_ETH_DB_ALL_PORTS) \
-    IX_ETH_DB_CHECK_PORT(portID) \
-}
-
-#endif /* IxEthDBPortDefs_H */
-/**
- *@}
- */
diff --git a/drivers/net/npe/include/IxEthDBQoS.h b/drivers/net/npe/include/IxEthDBQoS.h
deleted file mode 100644
index 6276930dc7..0000000000
--- a/drivers/net/npe/include/IxEthDBQoS.h
+++ /dev/null
@@ -1,130 +0,0 @@
-/**
- * @file IxEthDBQoS.h
- *
- * @brief Public definitions for QoS traffic classes
- * 
- * @par
- * IXP400 SW Release version 2.0
- * 
- * -- Copyright Notice --
- * 
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- * 
- * @par
- * SPDX-License-Identifier:	BSD-3-Clause
- * @par
- * -- End of Copyright Notice --
- */
-
-/**
- * @defgroup IxEthDBPortDefs IXP400 Ethernet QoS definitions
- *
- * @brief IXP00 Public definitions for QoS traffic classes
- *
- * @{
- */
-
-#ifndef IxEthDBQoS_H
-#define IxEthDBQoS_H
-
-/**
- * @def IX_ETH_DB_QUEUE_UNAVAILABLE
- * @brief alias to indicate a queue (traffic class) is not available
- */
-#define IX_ETH_DB_QUEUE_UNAVAILABLE  (0)
-
-#ifndef IX_IEEE802_1Q_QOS_PRIORITY_COUNT
-/**
- * @def IX_IEEE802_1Q_QOS_PRIORITY_COUNT
- * @brief number of QoS priorities, according to IEEE 802.1Q
- */
-#define IX_IEEE802_1Q_QOS_PRIORITY_COUNT (8)
-#endif
-
-/**
- * @brief array containing all the supported traffic class configurations
- */
-static const
-UINT8 ixEthDBQueueAssignments[][IX_IEEE802_1Q_QOS_PRIORITY_COUNT] = 
-{
-    { 4, 5, 6, 7, IX_ETH_DB_QUEUE_UNAVAILABLE, IX_ETH_DB_QUEUE_UNAVAILABLE, IX_ETH_DB_QUEUE_UNAVAILABLE, IX_ETH_DB_QUEUE_UNAVAILABLE },
-    { 15, 16, 17, 18, IX_ETH_DB_QUEUE_UNAVAILABLE, IX_ETH_DB_QUEUE_UNAVAILABLE, IX_ETH_DB_QUEUE_UNAVAILABLE, IX_ETH_DB_QUEUE_UNAVAILABLE },
-    { 11, 23, 26, IX_ETH_DB_QUEUE_UNAVAILABLE, IX_ETH_DB_QUEUE_UNAVAILABLE, IX_ETH_DB_QUEUE_UNAVAILABLE, IX_ETH_DB_QUEUE_UNAVAILABLE,  IX_ETH_DB_QUEUE_UNAVAILABLE },
-    { 4, 5, 6, 7, 8, 9, 10, 11 }
-    /* add here all other cases of queue configuration structures and update ixEthDBTrafficClassDefinitions to use them */
-};
-
-/**
- * @brief value used to index the NPE A functionality ID in the traffic class definition table
- */
-#define IX_ETH_DB_NPE_A_FUNCTIONALITY_ID_INDEX    (0)
-
-/**
- * @brief value used to index the traffic class count in the traffic class definition table
- */
-#define IX_ETH_DB_TRAFFIC_CLASS_COUNT_INDEX       (1)
-
-/**
- * @brief value used to index the queue assignment index in the traffic class definition table
- */
-#define IX_ETH_DB_QUEUE_ASSIGNMENT_INDEX          (2)
-
-/**
- * @brief traffic class definitions
- *
- * This array contains the default traffic class definition configuration,
- * as well as any special cases dictated by the functionality ID of NPE A.
- *
- * The default case should not be removed (otherwise the Ethernet
- * components will assert a fatal failure on initialization).
- */
-static const
-UINT8 ixEthDBTrafficClassDefinitions[][3] = 
-{
-    /* NPE A functionality ID | traffic class count | queue assignment index (points to the queue enumeration in ixEthDBQueueAssignments) */
-    {            0x00,                      4,                    0 }, /* default case - DO NOT REMOVE */
-    {            0x04,                      4,                    1 }, /* NPE A image ID 0.4.0.0 */
-    {            0x09,                      3,                    2 }, /* NPE A image ID 0.9.0.0 */
-    {            0x80,                      8,                    3 }, /* NPE A image ID 10.80.02.0 */
-    {            0x81,                      8,                    3 }, /* NPE A image ID 10.81.02.0 */
-    {            0x82,                      8,                    3 }  /* NPE A image ID 10.82.02.0 */
-};
-
-/**
- * @brief IEEE 802.1Q recommended QoS Priority => traffic class maps
- *
- * @verbatim
-                    Number of available traffic classes
-                    1 2 3 4 5 6 7 8
-    QoS Priority
-        0           0 0 0 1 1 1 1 2
-        1           0 0 0 0 0 0 0 0
-        2           0 0 0 0 0 0 0 1
-        3           0 0 0 1 1 2 2 3
-        4           0 1 1 2 2 3 3 4
-        5           0 1 1 2 3 4 4 5
-        6           0 1 2 3 4 5 5 6
-        7           0 1 2 3 4 5 6 7
-
-    @endverbatim
- */
-static const
-UINT8 ixEthIEEE802_1QUserPriorityToTrafficClassMapping[IX_IEEE802_1Q_QOS_PRIORITY_COUNT][IX_IEEE802_1Q_QOS_PRIORITY_COUNT] = 
- {
-     { 0, 0, 0, 0, 0, 0, 0, 0 }, /* 1 traffic class available */
-     { 0, 0, 0, 0, 1, 1, 1, 1 }, /* 2 traffic classes available */
-     { 0, 0, 0, 0, 1, 1, 2, 2 }, /* 3 traffic classes available */
-     { 1, 0, 0, 1, 2, 2, 3, 3 }, /* 4 traffic classes available */
-     { 1, 0, 0, 1, 2, 3, 4, 4 }, /* 5 traffic classes available */
-     { 1, 0, 0, 2, 3, 4, 5, 5 }, /* 6 traffic classes available */
-     { 1, 0, 0, 2, 3, 4, 5, 6 }, /* 7 traffic classes available */
-     { 2, 0, 1, 3, 4, 5, 6, 7 }  /* 8 traffic classes available */
- };
-
-#endif /* IxEthDBQoS_H */
-
-/**
- *@}
- */
diff --git a/drivers/net/npe/include/IxEthDB_p.h b/drivers/net/npe/include/IxEthDB_p.h
deleted file mode 100644
index ddc10a5789..0000000000
--- a/drivers/net/npe/include/IxEthDB_p.h
+++ /dev/null
@@ -1,686 +0,0 @@
-/**
- * @file IxEthDB_p.h
- *
- * @brief Private MAC learning API
- *
- * @par
- * IXP400 SW Release version 2.0
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * SPDX-License-Identifier:	BSD-3-Clause
- * @par
- * -- End of Copyright Notice --
- */
-
-#ifndef IxEthDB_p_H
-#define IxEthDB_p_H
-
-#include <IxTypes.h>
-#include <IxOsal.h>
-#include <IxEthDB.h>
-#include <IxNpeMh.h>
-#include <IxEthDBPortDefs.h>
-
-#include "IxEthDBMessages_p.h"
-#include "IxEthDBLog_p.h"
-
-#if (CPU==SIMSPARCSOLARIS)
-
-/* when running unit tests intLock() won't protect the event queue so we lock it manually */
-#define TEST_FIXTURE_LOCK_EVENT_QUEUE   { ixOsalMutexLock(&eventQueueLock, IX_OSAL_WAIT_FOREVER); }
-#define TEST_FIXTURE_UNLOCK_EVENT_QUEUE { ixOsalMutexUnlock(&eventQueueLock); }
-
-#else
-
-#define TEST_FIXTURE_LOCK_EVENT_QUEUE   /* nothing */
-#define TEST_FIXTURE_UNLOCK_EVENT_QUEUE /* nothing */
-
-#endif /* #if(CPU==SIMSPARCSOLARIS) */
-
-#ifndef IX_UNIT_TEST
-
-#define TEST_FIXTURE_INCREMENT_DB_CORE_ACCESS_COUNTER /* nothing */
-#define TEST_FIXTURE_MARK_OVERFLOW_EVENT              /* nothing */
-
-#else
-
-extern int dbAccessCounter;
-extern int overflowEvent;
-
-#define TEST_FIXTURE_INCREMENT_DB_CORE_ACCESS_COUNTER { dbAccessCounter++; }
-#define TEST_FIXTURE_MARK_OVERFLOW_EVENT              { overflowEvent = 1; }
-
-#endif
-
-/* code readability markers */
-#define __mempool__      /* memory pool marker */
-#define __lock__         /* hash write locking marker */
-#define __smartpointer__ /* smart pointer marker - warning: use only clone() when duplicating! */
-#define __alignment__    /* marker for data used only as alignment zones */
-
-/* constants */
-#define IX_ETH_DB_NPE_TIMEOUT (100) /* NPE response timeout, in ms */
-
-/**
- * number of hash table buckets
- * it should be at least 8x the predicted number of entries for performance
- * each bucket needs 8 bytes
- */
-#define NUM_BUCKETS (8192)
-
-/**
- * number of hash table buckets to preload when incrementing bucket iterator
- * = two cache lines
- */
-#define IX_ETHDB_CACHE_LINE_AHEAD (2)
-
-#define IX_ETHDB_BUCKETPTR_AHEAD  ((IX_ETHDB_CACHE_LINE_AHEAD * IX_OSAL_CACHE_LINE_SIZE)/sizeof(void *))
-
-#define IX_ETHDB_BUCKET_INDEX_MASK   (((IX_OSAL_CACHE_LINE_SIZE)/sizeof(void *)) - 1)
-
-/* locks */
-#define MAX_LOCKS (20) /**< maximum number of locks used simultaneously, do not tamper with */
-
-/* learning tree constants */
-#define INITIAL_ELT_SIZE    (8)                              /**< initial byte size of tree (empty unused root size) */
-#define MAX_ELT_SIZE        (512)                            /**< maximum number of entries (includes unused root) */
-#define MAX_GW_SIZE         (32)                             /**< maximum number of gateway entries (including unused root) */
-#define MAX_FW_SIZE         (32)                             /**< maximum number of firewall entries (including unused root) */
-#define ELT_ENTRY_SIZE      (8)                              /**< entry size, in bytes */
-#define ELT_ROOT_OFFSET     (ELT_ENTRY_SIZE)                 /**< tree root offset, in bytes - node preceeding root is unused */
-#define FULL_ELT_BYTE_SIZE  (MAX_ELT_SIZE * ELT_ENTRY_SIZE)  /**< full size of tree, in bytes, including unused root */
-#define FULL_GW_BYTE_SIZE   (MAX_GW_SIZE * ELT_ENTRY_SIZE)   /**< full size of gateway list, in bytes, including unused root */
-#define FULL_FW_BYTE_SIZE   (MAX_FW_SIZE * ELT_ENTRY_SIZE)   /**< full size of firewall table, in bytes, including unused root */
-
-/* maximum size of the VLAN table:
- * 4096 bits (one per VLAN)
- * 8 bits in one byte
- * interleaved VLAN membership and VLAN TTI (*2) */
-#define FULL_VLAN_BYTE_SIZE (4096 / 8 * 2)
-
-/* upper 9 bits used as set index, lower 3 bits as byte index */
-#define VLAN_SET_OFFSET(vlanID) ((vlanID) >> 3)
-#define VLAN_SET_MASK(vlanID)   (0x7 - ((vlanID) & 0x7))
-
-/* Update zone definitions */
-#define NPE_TREE_MEM_SIZE (4096) /* ((511 entries + 1 unused root) * 8 bytes/entry) */
-
-/* check the above value, we rely on 4k */
-#if NPE_TREE_MEM_SIZE != 4096
-    #error NPE_TREE_MEM_SIZE is not defined to 4096 bytes!
-#endif
-
-/* Size Filtering limits (Jumbo frame filtering) */
-#define IX_ETHDB_MAX_FRAME_SIZE     65535 /* other ports than NPE ports */
-#define IX_ETHDB_MIN_FRAME_SIZE         1 /* other ports than NPE ports */
-#define IX_ETHDB_MAX_NPE_FRAME_SIZE 16320 /* NPE ports firmware limit */
-#define IX_ETHDB_MIN_NPE_FRAME_SIZE     1 /* NPE ports firmware limit */
-#define IX_ETHDB_DEFAULT_FRAME_SIZE  1522
-
-/* memory management pool sizes  */
-
-/*
- * Note:
- *
- * NODE_POOL_SIZE controls the maximum number of elements in the database at any one time.
- * It should be large enough to cover all the search trees of all the ports simultaneously.
- *
- * MAC_POOL_SIZE should be higher than NODE_POOL_SIZE by at least the total number of MAC addresses
- * possible to be held at any time in all the ports.
- *
- * TREE_POOL_SIZE should follow the same guideline as for MAC_POOL_SIZE.
- *
- * The database structure described here (2000/4000/4000) is enough for two NPEs holding at most 511
- * entries each plus one PCI NIC holding at most 900 entries.
- */
-
-#define NODE_POOL_SIZE (2000) /**< number of HashNode objects - also master number of elements in the database; each entry has 16 bytes */
-#define MAC_POOL_SIZE  (4000) /**< number of MacDescriptor objects; each entry has 28 bytes */
-#define TREE_POOL_SIZE (4000) /**< number of MacTreeNode objects; each entry has 16 bytes */
-
-/* retry policies */
-#define BUSY_RETRY_ENABLED (true)  /**< if set to true the API will retry automatically calls returning BUSY */
-#define FOREVER_RETRY      (true)  /**< if set to true the API will retry forever BUSY calls */
-#define MAX_RETRIES        (400)   /**< upper retry limit - used only when FOREVER_RETRY is false */
-#define BUSY_RETRY_YIELD   (5)     /**< ticks to yield for every failed retry */
-
-/* event management */
-#define EVENT_QUEUE_SIZE       (500) /**< size of the sink collecting events from the Message Handler FIFO */
-#define EVENT_PROCESSING_LIMIT (100)  /**< batch processing control size (how many events are extracted from the queue at once) */
-
-/* MAC descriptors */
-#define STATIC_ENTRY  (true)
-#define DYNAMIC_ENTRY (false)
-
-/* age reset on next maintenance - incrementing by 1 will reset to 0 */
-#define AGE_RESET (0xFFFFFFFF)
-
-/* dependency maps */
-#define EMPTY_DEPENDENCY_MAP (0)
-
-/* trees */
-#define RIGHT (1)
-#define LEFT  (-1)
-
-/* macros */
-#define IX_ETH_DB_CHECK_PORT_EXISTS(portID) \
-{ \
-    if ((portID) >= IX_ETH_DB_NUMBER_OF_PORTS) \
-    { \
-        return IX_ETH_DB_INVALID_PORT; \
-    } \
-}
-
-#define IX_ETH_DB_CHECK_PORT_INITIALIZED(portID) \
-{ \
-    if ((portID) >= IX_ETH_DB_NUMBER_OF_PORTS) \
-    { \
-        return IX_ETH_DB_INVALID_PORT; \
-    } \
-    else \
-    { \
-        if (!ixEthDBPortInfo[portID].initialized) \
-        { \
-            return IX_ETH_DB_PORT_UNINITIALIZED; \
-        } \
-    } \
-}
-
-/* single NPE check */
-#define IX_ETH_DB_CHECK_SINGLE_NPE(portID) \
-    if (ixEthDBSingleEthNpeCheck(portID) != IX_ETH_DB_SUCCESS) \
-    { \
-        WARNING_LOG("EthDB: port ID %d is unavailable\n",(UINT32) portID); \
-        \
-        return IX_ETH_DB_INVALID_PORT; \
-    }
-
-/* feature check */
-#define IX_ETH_DB_CHECK_FEATURE(portID, feature) \
-    if ((ixEthDBPortInfo[portID].featureStatus & feature) == 0) \
-    { \
-        return IX_ETH_DB_FEATURE_UNAVAILABLE; \
-    }
-
-/* busy retrying */
-#define BUSY_RETRY(functionCall) \
-    { \
-        UINT32 retries = 0; \
-        IxEthDBStatus br_result; \
-        \
-        while ((br_result = functionCall) == IX_ETH_DB_BUSY \
-            && BUSY_RETRY_ENABLED && (FOREVER_RETRY || ++retries < MAX_RETRIES)) { ixOsalSleep(BUSY_RETRY_YIELD); }; \
-        \
-        if ((!FOREVER_RETRY && retries == MAX_RETRIES) || (br_result == IX_ETH_DB_FAIL)) \
-        {\
-            ERROR_LOG("Ethernet Learning Database Error: BUSY_RETRY failed at %s:%d\n", __FILE__, __LINE__); \
-        }\
-    }
-
-#define BUSY_RETRY_WITH_RESULT(functionCall, brwr_result) \
-    { \
-        UINT32 retries = 0; \
-        \
-        while ((brwr_result = functionCall) == IX_ETH_DB_BUSY \
-            && BUSY_RETRY_ENABLED && (FOREVER_RETRY || ++retries < MAX_RETRIES)) { ixOsalSleep(BUSY_RETRY_YIELD); }; \
-        \
-        if ((!FOREVER_RETRY && retries == MAX_RETRIES) || (brwr_result == IX_ETH_DB_FAIL)) \
-        {\
-            ERROR_LOG("Ethernet Learning Database Error: BUSY_RETRY_WITH_RESULT failed at %s:%d\n", __FILE__, __LINE__); \
-        }\
-    }
-
-/* iterators */
-#define IS_ITERATOR_VALID(iteratorPtr) ((iteratorPtr)->node != NULL)
-
-/* dependency port maps */
-
-/* Warning: if port indexing starts from 1 replace (portID) with (portID - 1) in DEPENDENCY_MAP (and make sure IX_ETH_DB_NUMBER_OF_PORTS is big enough) */
-
-/* gives an empty dependency map */
-#define SET_EMPTY_DEPENDENCY_MAP(map)      { int i = 0; for (; i < 32 ; i++) map[i] = 0; }
-
-#define IS_EMPTY_DEPENDENCY_MAP(result, map)       { int i = 0 ; result = true; for (; i < 32 ; i++) if (map[i] != 0) { result = false; break; }}
-
-/**
- * gives a map consisting only of 'portID'
- */
-#define SET_DEPENDENCY_MAP(map, portID)    {SET_EMPTY_DEPENDENCY_MAP(map); map[portID >> 3] = 1 << (portID & 0x7);}
-
-/**
- * gives a map resulting from joining map1 and map2
- */
-#define JOIN_MAPS(map, map1, map2)         { int i = 0; for (; i < 32 ; i++) map[i] = map1[i] | map2[i]; }
-
-/**
- * gives the map resulting from joining portID and map
- */
-#define JOIN_PORT_TO_MAP(map, portID)      { map[portID >> 3] |= 1 << (portID & 0x7); }
-
-/**
- * gives the map resulting from excluding portID from map
- */
-#define EXCLUDE_PORT_FROM_MAP(map, portID) { map[portID >> 3] &= ~(1 << (portID & 0x7); }
-
-/**
- * returns true if map1 is a subset of map2 and false otherwise
- */
-#define IS_MAP_SUBSET(result, map1, map2)  { int i = 0; result = true; for (; i < 32 ; i++) if ((map1[i] | map2[i]) != map2[i]) result = false; }
-
-/**
- * returns true is portID is part of map and false otherwise
- */
-#define IS_PORT_INCLUDED(portID, map)      ((map[portID >> 3] & (1 << (portID & 0x7))) != 0)
-
-/**
- * returns the difference between map1 and map2 (ports included in map1 and not included in map2)
- */
-#define DIFF_MAPS(map, map1, map2)         { int i = 0; for (; i < 32 ; i++) map[i] = map1[i] ^ (map1[i] & map2[i]); }
-
-/**
- * returns true if the maps collide (have at least one port in common) and false otherwise
- */
-#define MAPS_COLLIDE(result, map1, map2)   { int i = 0; result = false; for (; i < 32 ; i++) if ((map1[i] & map2[i]) != 0) result = true; }
-
-/* size (number of ports) of a dependency map */
-#define GET_MAP_SIZE(map, size)            { int i = 0, b = 0; size = 0; for (; i < 32 ; i++) { char y = map[i]; for (; b < 8 && (y >>= 1); b++) size += (y & 1); }}
-
-/* copy map2 into map1 */
-#define COPY_DEPENDENCY_MAP(map1, map2)    { memcpy (map1, map2, sizeof (map1)); }
-
-/* definition of a port map size/port number which cannot be reached (we support at most 32 ports) */
-#define MAX_PORT_SIZE   (0xFF)
-#define MAX_PORT_NUMBER (0xFF)
-
-#define IX_ETH_DB_CHECK_REFERENCE(ptr)   { if ((ptr) == NULL) { return IX_ETH_DB_INVALID_ARG; } }
-#define IX_ETH_DB_CHECK_MAP(portID, map) { if (!IS_PORT_INCLUDED(portID, map)) { return IX_ETH_DB_INVALID_ARG; } }
-
-/* event queue macros */
-#define EVENT_QUEUE_WRAP(offset)            ((offset) >= EVENT_QUEUE_SIZE ? (offset) - EVENT_QUEUE_SIZE : (offset))
-
-#define CAN_ENQUEUE(eventQueuePtr)          ((eventQueuePtr)->length < EVENT_QUEUE_SIZE)
-
-#define QUEUE_HEAD(eventQueuePtr)           (&(eventQueuePtr)->queue[EVENT_QUEUE_WRAP((eventQueuePtr)->base + (eventQueuePtr)->length)])
-
-#define QUEUE_TAIL(eventQueuePtr)           (&(eventQueuePtr)->queue[(eventQueuePtr)->base])
-
-#define PUSH_UPDATE_QUEUE(eventQueuePtr)    { (eventQueuePtr)->length++; }
-
-#define SHIFT_UPDATE_QUEUE(eventQueuePtr) \
-        { \
-            (eventQueuePtr)->base = EVENT_QUEUE_WRAP((eventQueuePtr)->base + 1); \
-            (eventQueuePtr)->length--; \
-        }
-
-#define RESET_QUEUE(eventQueuePtr) \
-    { \
-        (eventQueuePtr)->base   = 0; \
-        (eventQueuePtr)->length = 0; \
-    }
-
-/* node stack macros - used to browse a tree without using a recursive function */
-#define NODE_STACK_INIT(stack)               { (stack)->nodeCount = 0; }
-#define NODE_STACK_PUSH(stack, node, offset) { (stack)->nodes[(stack)->nodeCount] = (node); (stack)->offsets[(stack)->nodeCount++] = (offset); }
-#define NODE_STACK_POP(stack, node, offset)  { (node) = (stack)->nodes[--(stack)->nodeCount]; offset = (stack)->offsets[(stack)->nodeCount]; }
-#define NODE_STACK_NONEMPTY(stack)           ((stack)->nodeCount != 0)
-
-#ifndef IX_NDEBUG
-#define IX_ETH_DB_NPE_MSG_HISTORY_DEPTH (100)
-#define LOG_NPE_MSG(msg) \
-    do { \
-        UINT32 npeMsgHistoryIndex = (npeMsgHistoryLen++) % IX_ETH_DB_NPE_MSG_HISTORY_DEPTH; \
-        npeMsgHistory[npeMsgHistoryIndex][0] = msg.data[0]; \
-        npeMsgHistory[npeMsgHistoryIndex][1] = msg.data[1]; \
-    } while (0);
-#else
-#define LOG_NPE_MSG() /* nothing */
-#endif
-
-/* ----------- Data -------------- */
-
-/* typedefs */
-
-typedef UINT32 (*HashFunction)(void *entity);
-typedef BOOL (*MatchFunction)(void *reference, void *entry);
-typedef void (*FreeFunction)(void *entry);
-
-/**
- * basic component of a hash table
- */
-typedef struct HashNode_t
-{
-    void *data;                                 /**< specific data */
-    struct HashNode_t *next;                    /**< used for bucket chaining */
-
-    __mempool__ struct HashNode_t *nextFree;    /**< memory pool management */
-
-    __lock__ IxOsalFastMutex lock;              /**< node lock */
-} HashNode;
-
-/**
- * @brief hash table iterator definition
- *
- * an iterator is an object which can be used
- * to browse a hash table
- */
-typedef struct
-{
-    UINT32 bucketIndex;     /**< index of the currently iterated bucket */
-    HashNode *previousNode; /**< reference to the previously iterated node within the current bucket */
-    HashNode *node;         /**< reference to the currently iterated node */
-} HashIterator;
-
-/**
- * definition of a MAC descriptor (a database record)
- */
-
-typedef enum
-{
-    IX_ETH_DB_WIFI_AP_TO_STA = 0x0,
-    IX_ETH_DB_WIFI_AP_TO_AP  = 0x1
-} IxEthDBWiFiRecordType;
-
-typedef union
-{
-    struct
-    {
-        UINT32 age;
-        BOOL staticEntry; /**< true if this address is static (doesn't age) */
-    } filteringData;
-
-    struct
-    {
-        UINT32 age;
-        BOOL staticEntry;
-        UINT32 ieee802_1qTag;
-      } filteringVlanData;
-
-    struct
-    {
-        IxEthDBWiFiRecordType type;  /**< AP_TO_AP (0x1) or AP_TO_STA (0x0) */
-        UINT32 gwAddressIndex; /**< used only when linearizing the entries for NPE usage */
-        UINT8 gwMacAddress[IX_IEEE803_MAC_ADDRESS_SIZE];
-
-        __alignment__ UINT8 reserved2[2];
-    } wifiData;
-} IxEthDBRecordData;
-
-typedef struct MacDescriptor_t
-{
-    UINT8 macAddress[IX_IEEE803_MAC_ADDRESS_SIZE];
-
-    __alignment__ UINT8 reserved1[2];
-
-    UINT32 portID;
-    IxEthDBRecordType type;
-    IxEthDBRecordData recordData;
-
-    /* used for internal operations, such as NPE linearization */
-    void *internal;
-
-    /* custom user data */
-    void *user;
-
-    __mempool__ struct MacDescriptor_t *nextFree;   /**< memory pool management */
-    __smartpointer__ UINT32 refCount;               /**< smart pointer reference counter */
-} MacDescriptor;
-
-/**
- * hash table definition
- */
-typedef struct
-{
-    HashNode *hashBuckets[NUM_BUCKETS];
-    UINT32 numBuckets;
-
-    __lock__ IxOsalFastMutex bucketLocks[NUM_BUCKETS];
-
-    HashFunction entryHashFunction;
-    MatchFunction *matchFunctions;
-    FreeFunction freeFunction;
-} HashTable;
-
-typedef enum
-{
-    IX_ETH_DB_MAC_KEY       = 1,
-    IX_ETH_DB_MAC_PORT_KEY  = 2,
-    IX_ETH_DB_MAC_VLAN_KEY  = 3,
-    IX_ETH_DB_MAX_KEY_INDEX = 3
-} IxEthDBSearchKeyType;
-
-typedef struct MacTreeNode_t
-{
-    __smartpointer__  MacDescriptor *descriptor;
-    struct MacTreeNode_t *left, *right;
-
-    __mempool__ struct MacTreeNode_t *nextFree;
-} MacTreeNode;
-
-typedef IxEthDBStatus (*IxEthDBPortUpdateHandler)(IxEthDBPortId portID, IxEthDBRecordType type);
-
-typedef void (*IxEthDBNoteWriteFn)(void *address, MacTreeNode *node);
-
-typedef struct
-{
-    BOOL updateEnabled;                         /**< true if updates are enabled for port */
-    BOOL userControlled;                        /**< true if the user has manually used ixEthDBPortUpdateEnableSet */
-    BOOL treeInitialized;                       /**< true if the NPE has received an initial tree */
-    IxEthDBPortUpdateHandler updateHandler;     /**< port update handler routine */
-    void *npeUpdateZone;                        /**< port update memory zone */
-    void *npeGwUpdateZone;                      /**< port update memory zone for gateways */
-    void *vlanUpdateZone;                       /**< port update memory zone for VLAN tables */
-    MacTreeNode *searchTree;                    /**< internal search tree, in MacTreeNode representation */
-    BOOL searchTreePendingWrite;                /**< true if searchTree holds a tree pending write to the port */
-} PortUpdateMethod;
-
-typedef struct
-{
-    IxEthDBPortId portID;                   /**< port ID */
-    BOOL enabled;                           /**< true if the port is enabled */
-    BOOL agingEnabled;                      /**< true if aging on this port is enabled */
-    BOOL initialized;
-    IxEthDBPortMap dependencyPortMap;       /**< dependency port map for this port */
-    PortUpdateMethod updateMethod;          /**< update method structure */
-    BOOL macAddressUploaded;                /**< true if the MAC address was uploaded into the port */
-    UINT32 maxRxFrameSize;                  /**< maximum Rx frame size for this port */
-    UINT32 maxTxFrameSize;                  /**< maximum Rx frame size for this port */
-
-    UINT8 bbsid[6];
-    __alignment__ UINT8 reserved[2];
-    UINT32 frameControlDurationID;          /**< Frame Control - Duration/ID WiFi control */
-
-    IxEthDBVlanTag vlanTag;                  /**< default VLAN tag for port */
-    IxEthDBPriorityTable priorityTable;     /**< QoS <=> internal priority mapping */
-    IxEthDBVlanSet vlanMembership;
-    IxEthDBVlanSet transmitTaggingInfo;
-    IxEthDBFrameFilter frameFilter;
-    IxEthDBTaggingAction taggingAction;
-
-    UINT32 npeFrameFilter;
-    UINT32 npeTaggingAction;
-
-    IxEthDBFirewallMode firewallMode;
-    BOOL srcAddressFilterEnabled;
-
-    BOOL stpBlocked;
-
-    IxEthDBFeature featureCapability;
-    IxEthDBFeature featureStatus;
-
-    UINT32 ixEthDBTrafficClassAQMAssignments[IX_IEEE802_1Q_QOS_PRIORITY_COUNT];
-
-    UINT32 ixEthDBTrafficClassCount;
-
-    UINT32 ixEthDBTrafficClassAvailable;
-
-
-
-    __lock__ IxOsalMutex npeAckLock;
-} PortInfo;
-
-/* list of port information structures indexed on port Ids */
-extern IX_ETH_DB_PUBLIC PortInfo ixEthDBPortInfo[IX_ETH_DB_NUMBER_OF_PORTS];
-
-typedef enum
-{
-    IX_ETH_DB_ADD_FILTERING_RECORD    = 0xFF0001,
-    IX_ETH_DB_REMOVE_FILTERING_RECORD = 0xFF0002
-} PortEventType;
-
-typedef struct
-{
-    UINT32 eventType;
-    IxEthDBPortId portID;
-    IxEthDBMacAddr macAddr;
-    BOOL staticEntry;
-} PortEvent;
-
-typedef struct
-{
-    PortEvent queue[EVENT_QUEUE_SIZE];
-    UINT32 base;
-    UINT32 length;
-} PortEventQueue;
-
-typedef struct
-{
-    IxEthDBPortId portID; /**< originating port */
-    MacDescriptor *macDescriptors[MAX_ELT_SIZE]; /**< addresses to be synced into db */
-    UINT32 addressCount; /**< number of addresses */
-} TreeSyncInfo;
-
-typedef struct
-{
-    MacTreeNode *nodes[MAX_ELT_SIZE];
-    UINT32 offsets[MAX_ELT_SIZE];
-    UINT32 nodeCount;
-} MacTreeNodeStack;
-
-/* Prototypes */
-
-/* ----------- Memory management -------------- */
-
-IX_ETH_DB_PUBLIC void ixEthDBInitMemoryPools(void);
-
-IX_ETH_DB_PUBLIC HashNode* ixEthDBAllocHashNode(void);
-IX_ETH_DB_PUBLIC void ixEthDBFreeHashNode(HashNode *);
-
-IX_ETH_DB_PUBLIC __smartpointer__ MacDescriptor* ixEthDBAllocMacDescriptor(void);
-IX_ETH_DB_PUBLIC __smartpointer__ MacDescriptor* ixEthDBCloneMacDescriptor(MacDescriptor *macDescriptor);
-IX_ETH_DB_PUBLIC __smartpointer__ void ixEthDBFreeMacDescriptor(MacDescriptor *);
-
-IX_ETH_DB_PUBLIC __smartpointer__ MacTreeNode* ixEthDBAllocMacTreeNode(void);
-IX_ETH_DB_PUBLIC __smartpointer__ MacTreeNode* ixEthDBCloneMacTreeNode(MacTreeNode *);
-IX_ETH_DB_PUBLIC __smartpointer__ void ixEthDBFreeMacTreeNode(MacTreeNode *);
-
-IX_ETH_DB_PUBLIC void ixEthDBPoolFreeMacTreeNode(MacTreeNode *);
-IX_ETH_DB_PUBLIC UINT32 ixEthDBSearchTreeUsageGet(MacTreeNode *tree);
-IX_ETH_DB_PUBLIC int ixEthDBShowMemoryStatus(void);
-
-/* Hash Table */
-IX_ETH_DB_PUBLIC void ixEthDBInitHash(HashTable *hashTable, UINT32 numBuckets, HashFunction entryHashFunction, MatchFunction *matchFunctions, FreeFunction freeFunction);
-
-IX_ETH_DB_PUBLIC IxEthDBStatus ixEthDBAddHashEntry(HashTable *hashTable, void *entry);
-IX_ETH_DB_PUBLIC IxEthDBStatus ixEthDBRemoveHashEntry(HashTable *hashTable, int keyType, void *reference);
-IX_ETH_DB_PUBLIC IxEthDBStatus ixEthDBSearchHashEntry(HashTable *hashTable, int keyType, void *reference, HashNode **searchResult);
-IX_ETH_DB_PUBLIC IxEthDBStatus ixEthDBPeekHashEntry(HashTable *hashTable, int keyType, void *reference);
-IX_ETH_DB_PUBLIC void ixEthDBReleaseHashNode(HashNode *node);
-
-IX_ETH_DB_PUBLIC IxEthDBStatus ixEthDBInitHashIterator(HashTable *hashTable, HashIterator *iterator);
-IX_ETH_DB_PUBLIC IxEthDBStatus ixEthDBIncrementHashIterator(HashTable *hashTable, HashIterator *iterator);
-IX_ETH_DB_PUBLIC IxEthDBStatus ixEthDBRemoveEntryAtHashIterator(HashTable *hashTable, HashIterator *iterator);
-IX_ETH_DB_PUBLIC void ixEthDBReleaseHashIterator(HashIterator *iterator);
-
-/* API Support */
-IX_ETH_DB_PUBLIC IxEthDBStatus ixEthDBPortAddressSet(IxEthDBPortId portID, IxEthDBMacAddr *macAddr);
-IX_ETH_DB_PUBLIC void ixEthDBMaximumFrameSizeAckCallback(IxNpeMhNpeId npeID, IxNpeMhMessage msg);
-
-/* DB Core functions */
-IX_ETH_DB_PUBLIC IxEthDBStatus ixEthDBInit(void);
-IX_ETH_DB_PUBLIC IxEthDBStatus ixEthDBAdd(MacDescriptor *newRecordTemplate, IxEthDBPortMap updateTrigger);
-IX_ETH_DB_PUBLIC IxEthDBStatus ixEthDBRemove(MacDescriptor *templateRecord, IxEthDBPortMap updateTrigger);
-IX_ETH_DB_PUBLIC HashNode* ixEthDBSearch(IxEthDBMacAddr *macAddress, IxEthDBRecordType typeFilter);
-IX_ETH_DB_PUBLIC IxEthDBStatus ixEthDBPeek(IxEthDBMacAddr *macAddress, IxEthDBRecordType typeFilter);
-
-/* Learning support */
-IX_ETH_DB_PUBLIC UINT32 ixEthDBAddressCompare(UINT8 *mac1, UINT8 *mac2);
-IX_ETH_DB_PUBLIC BOOL ixEthDBAddressMatch(void *reference, void *entry);
-IX_ETH_DB_PUBLIC UINT32 ixEthDBEntryXORHash(void *macDescriptor);
-IX_ETH_DB_PUBLIC UINT32 ixEthDBKeyXORHash(void *macAddress);
-
-/* Port updates */
-IX_ETH_DB_PUBLIC IxEthDBStatus ixEthDBNPEUpdateHandler(IxEthDBPortId portID, IxEthDBRecordType type);
-IX_ETH_DB_PUBLIC void ixEthDBUpdatePortLearningTrees(IxEthDBPortMap triggerPorts);
-IX_ETH_DB_PUBLIC void ixEthDBNPEAccessRequest(IxEthDBPortId portID);
-IX_ETH_DB_PUBLIC void ixEthDBUpdateLock(void);
-IX_ETH_DB_PUBLIC void ixEthDBUpdateUnlock(void);
-IX_ETH_DB_PUBLIC MacTreeNode* ixEthDBQuery(MacTreeNode *searchTree, IxEthDBPortMap query, IxEthDBRecordType recordFilter, UINT32 maximumEntries);
-IX_ETH_DB_PUBLIC IxEthDBStatus ixEthDBFirewallUpdate(IxEthDBPortId portID, void *address, UINT32 epDelta);
-
-/* Init/unload */
-IX_ETH_DB_PUBLIC void ixEthDBPortSetAckCallback(IxNpeMhNpeId npeID, IxNpeMhMessage msg);
-IX_ETH_DB_PUBLIC IxEthDBStatus ixEthDBEventProcessorInit(void);
-IX_ETH_DB_PUBLIC void ixEthDBPortInit(IxEthDBPortId portID);
-IX_ETH_DB_PUBLIC IxEthDBStatus ixEthDBPortEnable(IxEthDBPortId portID);
-IX_ETH_DB_PUBLIC IxEthDBStatus ixEthDBPortDisable(IxEthDBPortId portID);
-IX_ETH_DB_PUBLIC void ixEthDBNPEUpdateAreasInit(void);
-IX_ETH_DB_PUBLIC UINT32 ixEthDBMatchMethodsRegister(MatchFunction *matchFunctions);
-IX_ETH_DB_PUBLIC UINT32 ixEthDBRecordSerializeMethodsRegister(void);
-IX_ETH_DB_PUBLIC UINT32 ixEthDBUpdateTypeRegister(BOOL *typeArray);
-IX_ETH_DB_PUBLIC void ixEthDBNPEUpdateAreasUnload(void);
-IX_ETH_DB_PUBLIC void ixEthDBFeatureCapabilityScan(void);
-IX_ETH_DB_PUBLIC UINT32 ixEthDBKeyTypeRegister(UINT32 *keyType);
-
-/* Event processing */
-IX_ETH_DB_PUBLIC IxEthDBStatus ixEthDBDefaultEventCallbackEnable(IxEthDBPortId portID, BOOL enable);
-IX_ETH_DB_PUBLIC IxEthDBStatus ixEthDBTriggerAddPortUpdate(IxEthDBMacAddr *macAddr, IxEthDBPortId portID, BOOL staticEntry);
-IX_ETH_DB_PUBLIC IxEthDBStatus ixEthDBTriggerRemovePortUpdate(IxEthDBMacAddr *macAddr, IxEthDBPortId portID);
-IX_ETH_DB_PUBLIC void ixEthDBNPEEventCallback(IxNpeMhNpeId npeID, IxNpeMhMessage msg);
-
-/* NPE adaptor */
-IX_ETH_DB_PUBLIC void ixEthDBGetMacDatabaseCbk(IxNpeMhNpeId npeID, IxNpeMhMessage msg);
-IX_ETH_DB_PUBLIC void ixEthDBNpeMsgAck(IxNpeMhNpeId npeID, IxNpeMhMessage msg);
-IX_ETH_DB_PUBLIC void ixEthDBNPESyncScan(IxEthDBPortId portID, void *eltBaseAddress, UINT32 eltSize);
-IX_ETH_DB_PUBLIC void ixEthDBNPETreeWrite(IxEthDBRecordType type, UINT32 totalSize, void *baseAddress, MacTreeNode *tree, UINT32 *blocks, UINT32 *startIndex);
-IX_ETH_DB_PUBLIC void ixEthDBNPEGatewayNodeWrite(void *address, MacTreeNode *node);
-
-/* Other public API functions */
-IX_ETH_DB_PUBLIC IxEthDBStatus ixEthDBStartLearningFunction(void);
-IX_ETH_DB_PUBLIC IxEthDBStatus ixEthDBStopLearningFunction(void);
-IX_ETH_DB_PUBLIC IxEthDBStatus ixEthDBPortUpdateEnableSet(IxEthDBPortId portID, BOOL enableUpdate);
-
-/* Maximum Tx/Rx public functions */
-IX_ETH_DB_PUBLIC IxEthDBStatus ixEthDBFilteringPortMaximumRxFrameSizeSet(IxEthDBPortId portID, UINT32 maximumRxFrameSize);
-IX_ETH_DB_PUBLIC IxEthDBStatus ixEthDBFilteringPortMaximumTxFrameSizeSet(IxEthDBPortId portID, UINT32 maximumTxFrameSize);
-
-/* VLAN-related */
-IX_ETH_DB_PUBLIC IxEthDBStatus ixEthDBPortVlanTableSet(IxEthDBPortId portID, IxEthDBVlanSet portVlanTable, IxEthDBVlanSet vlanSet);
-
-/* Record search */
-IX_ETH_DB_PUBLIC BOOL ixEthDBAddressRecordMatch(void *untypedReference, void *untypedEntry);
-IX_ETH_DB_PUBLIC BOOL ixEthDBVlanRecordMatch(void *untypedReference, void *untypedEntry);
-IX_ETH_DB_PUBLIC BOOL ixEthDBPortRecordMatch(void *untypedReference, void *untypedEntry);
-IX_ETH_DB_PUBLIC BOOL ixEthDBNullMatch(void *reference, void *entry);
-IX_ETH_DB_PUBLIC HashNode* ixEthDBPortSearch(IxEthDBMacAddr *macAddress, IxEthDBPortId portID, IxEthDBRecordType typeFilter);
-IX_ETH_DB_PUBLIC HashNode* ixEthDBVlanSearch(IxEthDBMacAddr *macAddress, IxEthDBVlanId vlanID, IxEthDBRecordType typeFilter);
-
-/* Utilities */
-IX_ETH_DB_PUBLIC const char* mac2string(const unsigned char *mac);
-IX_ETH_DB_PUBLIC void showHashInfo(void);
-IX_ETH_DB_PUBLIC int ixEthDBAnalyzeHash(void);
-IX_ETH_DB_PUBLIC const char* errorString(IxEthDBStatus error);
-IX_ETH_DB_PUBLIC int numHashElements(void);
-IX_ETH_DB_PUBLIC void zapHashtable(void);
-IX_ETH_DB_PUBLIC BOOL ixEthDBCheckSingleBitValue(UINT32 value);
-
-/* Single Eth NPE Check */
-IX_ETH_DB_PUBLIC IxEthDBStatus ixEthDBSingleEthNpeCheck(IxEthDBPortId portId);
-
-#endif /* IxEthDB_p_H */
-
diff --git a/drivers/net/npe/include/IxEthMii.h b/drivers/net/npe/include/IxEthMii.h
deleted file mode 100644
index 8d7de3d4ce..0000000000
--- a/drivers/net/npe/include/IxEthMii.h
+++ /dev/null
@@ -1,246 +0,0 @@
-/**
- * @file    IxEthMii.h
- *
- * @brief this file contains the public API of @ref IxEthMii component
- *
- * Design notes :  
- * The main intent of this API is to inplement MII high level fonctionalitoes
- * to support the codelets provided with the IXP400 software releases. It 
- * superceedes previous interfaces provided with @ref IxEThAcc component.
- * 
- * This API has been tested with the PHYs provided with the
- * IXP400 development platforms. It may not work for specific Ethernet PHYs
- * used on specific boards.
- *
- * This source code detects and interface the LXT972, LXT973 and KS6995
- * Ethernet PHYs.
- *
- * This source code should be considered as an example which may need
- * to be adapted for different hardware implementations.
- *
- * It is strongly recommended to use public domain and GPL utilities
- * like libmii, mii-diag for MII interface support.
- * 
- *
- * 
- * @par
- * IXP400 SW Release version 2.0
- * 
- * -- Copyright Notice --
- * 
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- * 
- * @par
- * SPDX-License-Identifier:	BSD-3-Clause
- * @par
- * -- End of Copyright Notice --
- */
-
-#ifndef IxEthMii_H
-#define IxEthMii_H
-
-#include <IxTypes.h>
-
-/**
- * @defgroup IxEthMii IXP400 Ethernet Phy Access (IxEthMii) API
- *
- * @brief ethMii is a library that does provides access to the 
- * Ethernet PHYs
- *
- *@{
- */
-
-/**
- * @ingroup IxEthMii
- *
- * @fn  ixEthMiiPhyScan(BOOL phyPresent[], UINT32 maxPhyCount)
- *
- * @brief Scan the MDIO bus for PHYs
- *  This function scans PHY addresses 0 through 31, and sets phyPresent[n] to 
- *  true if a phy is discovered at address n.
- *
- * - Reentrant    - no
- * - ISR Callable - no
- *
- * @pre The MAC on Ethernet Port 2 (NPE C) must be initialised, and generating the MDIO clock.
- *
- * @param phyPresent BOOL [in] - boolean array of IXP425_ETH_ACC_MII_MAX_ADDR entries
- * @param maxPhyCount UINT32 [in] - number of PHYs to search for (the scan will stop when
- *         the indicated number of PHYs is found).
- *
- * @return IX_STATUS
- * - IX_ETH_ACC_SUCCESS
- * - IX_ETH_ACC_FAIL : invalid arguments.
- *
- * <hr>
- */
-PUBLIC IX_STATUS ixEthMiiPhyScan(BOOL phyPresent[], UINT32 maxPhyCount);
-
-/**
- * @ingroup IxEthMii
- *
- * @fn ixEthMiiPhyConfig(UINT32 phyAddr,
-		         BOOL speed100, 
-			 BOOL fullDuplex, 
-			 BOOL autonegotiate)
- *
- *
- * @brief Configure a PHY
- *   Configure a PHY's speed, duplex and autonegotiation status
- *
- * - Reentrant    - no
- * - ISR Callable - no
- *
- * @pre The MAC on Ethernet Port 2 (NPE C) must be initialised, and generating the MDIO clock.
- *   
- * @param phyAddr UINT32 [in] 
- * @param speed100 BOOL [in] - set to true for 100Mbit/s operation, false for 10Mbit/s
- * @param fullDuplex BOOL [in] - set to true for Full Duplex, false for Half Duplex
- * @param autonegotiate BOOL [in] - set to true to enable autonegotiation
- *
- * @return IX_STATUS
- * - IX_SUCCESS
- * - IX_FAIL : invalid arguments.
- *
- * <hr>
- */
-PUBLIC IX_STATUS ixEthMiiPhyConfig(UINT32 phyAddr,
-				    BOOL speed100, 
-				    BOOL fullDuplex, 
-				    BOOL autonegotiate);
-
-/**
- * @ingroup IxEthMii
- *
- * @fn ixEthMiiPhyLoopbackEnable(UINT32 phyAddr)
- *
- *
- * @brief Enable PHY Loopback in a specific Eth MII port
- *
- * @note When PHY Loopback is enabled, frames sent out to the PHY from the
- * IXP400 will be looped back to the IXP400. They will not be transmitted out
- * on the wire.
- *
- * - Reentrant    - no
- * - ISR Callable - no
- *
- * @param phyAddr UINT32 [in] - the address of the Ethernet PHY (0-31)
- *
- * @return IX_STATUS
- * - IX_SUCCESS
- * - IX_FAIL : invalid arguments.
- * <hr>
- */
-PUBLIC IX_STATUS
-ixEthMiiPhyLoopbackEnable (UINT32 phyAddr);
-
-/**
- * @ingroup IxEthMii
- *
- * @fn ixEthMiiPhyLoopbackDisable(UINT32 phyAddr)
- *
- *
- * @brief Disable PHY Loopback in a specific Eth MII port
- *
- * - Reentrant    - no
- * - ISR Callable - no
- *   
- * @param phyAddr UINT32 [in] - the address of the Ethernet PHY (0-31)
- *
- * @return IX_STATUS
- * - IX_SUCCESS
- * - IX_FAIL : invalid arguments.
- * <hr>
- */
-PUBLIC IX_STATUS
-ixEthMiiPhyLoopbackDisable (UINT32 phyAddr);
-
-/**
- * @ingroup IxEthMii
- *
- * @fn ixEthMiiPhyReset(UINT32 phyAddr)
- *
- * @brief Reset a PHY
- *   Reset a PHY
- *
- * - Reentrant    - no
- * - ISR Callable - no
- *
- * @pre The MAC on Ethernet Port 2 (NPE C) must be initialised, and generating the MDIO clock.
- *   
- * @param phyAddr UINT32 [in] - the address of the Ethernet PHY (0-31)
- *
- * @return IX_STATUS
- * - IX_SUCCESS
- * - IX_FAIL : invalid arguments.
- *
- * <hr>
- */
-PUBLIC IX_STATUS ixEthMiiPhyReset(UINT32 phyAddr);
-
-
-/**
- * @ingroup IxEthMii
- *
- * @fn ixEthMiiLinkStatus(UINT32 phyAddr, 
-			  BOOL *linkUp,
-			  BOOL *speed100, 
-			  BOOL *fullDuplex,
-		          BOOL *autoneg)
- *
- * @brief Retrieve the current status of a PHY
- *   Retrieve the link, speed, duplex and autonegotiation status of a PHY
- *
- * - Reentrant    - no
- * - ISR Callable - no
- *
- * @pre The MAC on Ethernet Port 2 (NPE C) must be initialised, and generating the MDIO clock.
- *   
- * @param phyAddr UINT32 [in] - the address of the Ethernet PHY (0-31)
- * @param linkUp BOOL [out] - set to true if the link is up
- * @param speed100 BOOL [out] - set to true indicates 100Mbit/s, false indicates 10Mbit/s
- * @param fullDuplex BOOL [out] - set to true indicates Full Duplex, false indicates Half Duplex
- * @param autoneg BOOL [out] - set to true indicates autonegotiation is enabled, false indicates autonegotiation is disabled
- *
- * @return IX_STATUS
- * - IX_SUCCESS
- * - IX_FAIL : invalid arguments.
- *
- * <hr>
- */
-PUBLIC IX_STATUS ixEthMiiLinkStatus(UINT32 phyAddr, 
-				     BOOL *linkUp,
-				     BOOL *speed100, 
-				     BOOL *fullDuplex,
-				     BOOL *autoneg);
-
-/**
- * @ingroup IxEthMii
- *
- * @fn ixEthMiiPhyShow (UINT32 phyAddr)
- *
- *
- * @brief Display information on a specified PHY
- *   Display link status, speed, duplex and Auto Negotiation status
- *
- * - Reentrant    - no
- * - ISR Callable - no
- *
- * @pre The MAC on Ethernet Port 2 (NPE C) must be initialised, and generating the MDIO clock.
- *   
- * @param phyAddr UINT32 [in] - the address of the Ethernet PHY (0-31)
- *
- * @return IX_STATUS
- * - IX_SUCCESS
- * - IX_FAIL : invalid arguments.
- *
- * <hr>
- */
-PUBLIC IX_STATUS ixEthMiiPhyShow (UINT32 phyAddr);
-
-#endif /* ndef IxEthMii_H */
-/**
- *@}
- */
diff --git a/drivers/net/npe/include/IxEthMii_p.h b/drivers/net/npe/include/IxEthMii_p.h
deleted file mode 100644
index 0c48a6971a..0000000000
--- a/drivers/net/npe/include/IxEthMii_p.h
+++ /dev/null
@@ -1,161 +0,0 @@
-/**
- * @file IxEthMii_p.h
- *
- * @author Intel Corporation
- * @date 
- *
- * @brief  MII Header file
- *
- * Design Notes:
- *
- * 
- * @par
- * IXP400 SW Release version 2.0
- * 
- * -- Copyright Notice --
- * 
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- * 
- * @par
- * SPDX-License-Identifier:	BSD-3-Clause
- * @par
- * -- End of Copyright Notice --
- */
-
-#ifndef IxEthMii_p_H
-#define IxEthMii_p_H
-
-
-/* MII definitions - these have been verified against the LXT971 and
- LXT972 PHYs*/
-
-#define IX_ETH_MII_MAX_REG_NUM  0x20  /* max number of registers */
-
-#define IX_ETH_MII_CTRL_REG     0x0	/* Control Register */
-#define IX_ETH_MII_STAT_REG	0x1	/* Status Register */
-#define IX_ETH_MII_PHY_ID1_REG  0x2	/* PHY identifier 1 Register */
-#define IX_ETH_MII_PHY_ID2_REG  0x3	/* PHY identifier 2 Register */
-#define IX_ETH_MII_AN_ADS_REG   0x4	/* Auto-Negotiation 	  */
-					/* Advertisement Register */
-#define IX_ETH_MII_AN_PRTN_REG  0x5	/* Auto-Negotiation 	    */
-					/* partner ability Register */
-#define IX_ETH_MII_AN_EXP_REG   0x6	/* Auto-Negotiation   */
-					/* Expansion Register */
-#define IX_ETH_MII_AN_NEXT_REG  0x7	/* Auto-Negotiation 	       */
-					/* next-page transmit Register */
-
-#define IX_ETH_MII_STAT2_REG    0x11    /* Status Register 2*/
-
-
-/* MII control register bit  */
-
-#define IX_ETH_MII_CR_COLL_TEST  0x0080  /* collision test */
-#define IX_ETH_MII_CR_FDX	 0x0100  /* FDX =1, half duplex =0 */
-#define IX_ETH_MII_CR_RESTART    0x0200  /* restart auto negotiation */
-#define IX_ETH_MII_CR_ISOLATE    0x0400  /* isolate PHY from MII */
-#define IX_ETH_MII_CR_POWER_DOWN 0x0800  /* power down */
-#define IX_ETH_MII_CR_AUTO_EN    0x1000  /* auto-negotiation enable */
-#define IX_ETH_MII_CR_100	 0x2000  /* 0 = 10mb, 1 = 100mb */
-#define IX_ETH_MII_CR_LOOPBACK   0x4000  /* 0 = normal, 1 = loopback */
-#define IX_ETH_MII_CR_RESET	 0x8000  /* 0 = normal, 1 = PHY reset */
-#define IX_ETH_MII_CR_NORM_EN    0x0000  /* just enable the PHY */
-#define IX_ETH_MII_CR_DEF_0_MASK 0xca7f  /* they must return zero */
-#define IX_ETH_MII_CR_RES_MASK   0x007f  /* reserved bits, return zero */
-
-/* MII Status register bit definitions */
-
-#define IX_ETH_MII_SR_LINK_STATUS   0x0004 /* link Status -- 1 = link */
-#define IX_ETH_MII_SR_AUTO_SEL      0x0008 /* auto speed select capable */
-#define IX_ETH_MII_SR_REMOTE_FAULT  0x0010 /* Remote fault detect */
-#define IX_ETH_MII_SR_AUTO_NEG      0x0020 /* auto negotiation complete */
-#define IX_ETH_MII_SR_10T_HALF_DPX  0x0800 /* 10BaseT HD capable */
-#define IX_ETH_MII_SR_10T_FULL_DPX  0x1000 /* 10BaseT FD capable */
-#define IX_ETH_MII_SR_TX_HALF_DPX   0x2000 /* TX HD capable */
-#define IX_ETH_MII_SR_TX_FULL_DPX   0x4000 /* TX FD capable */
-#define IX_ETH_MII_SR_T4            0x8000 /* T4 capable */
-#define IX_ETH_MII_SR_ABIL_MASK     0xff80 /* abilities mask */
-#define IX_ETH_MII_SR_EXT_CAP       0x0001 /* extended capabilities */
-
-
-/* LXT971/2 Status 2 register bit definitions */
-#define IX_ETH_MII_SR2_100          0x4000
-#define IX_ETH_MII_SR2_TX           0x2000
-#define IX_ETH_MII_SR2_RX           0x1000
-#define IX_ETH_MII_SR2_COL          0x0800
-#define IX_ETH_MII_SR2_LINK         0x0400
-#define IX_ETH_MII_SR2_FD           0x0200
-#define IX_ETH_MII_SR2_AUTO         0x0100
-#define IX_ETH_MII_SR2_AUTO_CMPLT   0x0080
-#define IX_ETH_MII_SR2_POLARITY     0x0020
-#define IX_ETH_MII_SR2_PAUSE        0x0010
-#define IX_ETH_MII_SR2_ERROR        0x0008
-
-/* MII Link Code word  bit definitions */
-
-#define IX_ETH_MII_BP_FAULT	0x2000       	/* remote fault */
-#define IX_ETH_MII_BP_ACK	0x4000       	/* acknowledge */
-#define IX_ETH_MII_BP_NP	0x8000       	/* nexp page is supported */
-
-/* MII Next Page bit definitions */
-
-#define IX_ETH_MII_NP_TOGGLE 0x0800       	/* toggle bit */
-#define IX_ETH_MII_NP_ACK2	 0x1000       	/* acknowledge two */
-#define IX_ETH_MII_NP_MSG	 0x2000       	/* message page */
-#define IX_ETH_MII_NP_ACK1	 0x4000       	/* acknowledge one */
-#define IX_ETH_MII_NP_NP	 0x8000       	/* nexp page will follow */
-
-/* MII Expansion Register bit definitions */
-
-#define IX_ETH_MII_EXP_FAULT    0x0010  /* parallel detection fault */
-#define IX_ETH_MII_EXP_PRTN_NP  0x0008  /* link partner next-page able */
-#define IX_ETH_MII_EXP_LOC_NP   0x0004  /* local PHY next-page able */
-#define IX_ETH_MII_EXP_PR	    0x0002  /* full page received */
-#define IX_ETH_MII_EXP_PRT_AN   0x0001  /* link partner auto neg able */
-
-/* technology ability field bit definitions */
-
-#define IX_ETH_MII_TECH_10BASE_T	  0x0020  /* 10Base-T */
-#define IX_ETH_MII_TECH_10BASE_FD	  0x0040  /* 10Base-T Full Duplex */
-#define IX_ETH_MII_TECH_100BASE_TX	  0x0080  /* 100Base-TX */
-#define IX_ETH_MII_TECH_100BASE_TX_FD 0x0100  /* 100Base-TX Full Duplex */
-
-#define IX_ETH_MII_TECH_100BASE_T4	0x0200	/* 100Base-T4 */
-#define IX_ETH_MII_ADS_TECH_MASK	0x1fe0	/* technology abilities mask */
-#define IX_ETH_MII_TECH_MASK	IX_ETH_MII_ADS_TECH_MASK
-#define IX_ETH_MII_ADS_SEL_MASK	0x001f	/* selector field mask */
-
-#define IX_ETH_MII_AN_FAIL     0x10    /* auto-negotiation fail */
-#define IX_ETH_MII_STAT_FAIL   0x20    /* errors in the status register */
-#define IX_ETH_MII_PHY_NO_ABLE 0x40    /* the PHY lacks some abilities */
-
-/* Definitions for MII access routines*/
-
-#define IX_ETH_MII_GO                  BIT(31)
-#define IX_ETH_MII_WRITE               BIT(26)
-#define IX_ETH_MII_TIMEOUT_10TH_SECS       (5)    
-#define IX_ETH_MII_10TH_SEC_IN_MILLIS    (100)              
-#define IX_ETH_MII_READ_FAIL           BIT(31)
-
-/* When we reset the PHY we delay for 2 seconds to allow the reset to 
-   complete*/
-#define IX_ETH_MII_RESET_DELAY_MS  (2000)     
-#define IX_ETH_MII_RESET_POLL_MS     (50)
-
-#define IX_ETH_MII_REG_SHL    16
-#define IX_ETH_MII_ADDR_SHL   21
-
-/* supported PHYs */
-#define IX_ETH_MII_LXT971_PHY_ID	0x001378E0
-#define IX_ETH_MII_LXT972_PHY_ID	0x001378E2
-#define IX_ETH_MII_LXT973_PHY_ID	0x00137A10
-#define IX_ETH_MII_LXT973A3_PHY_ID	0x00137A11
-#define IX_ETH_MII_KS8995_PHY_ID	0x00221450
-#define IX_ETH_MII_LXT9785_PHY_ID	0x001378FF	
-
-
-#define IX_ETH_MII_INVALID_PHY_ID 0x00000000
-#define IX_ETH_MII_UNKNOWN_PHY_ID 0xffffffff
-
-#endif  /*IxEthAccMii_p_H*/
diff --git a/drivers/net/npe/include/IxEthNpe.h b/drivers/net/npe/include/IxEthNpe.h
deleted file mode 100644
index 20bfa76c36..0000000000
--- a/drivers/net/npe/include/IxEthNpe.h
+++ /dev/null
@@ -1,671 +0,0 @@
-#ifndef __doxygen_HIDE  /* This file is not part of the API */
-
-/**
- * @file IxEthNpe.h
- * 
- * @par
- * IXP400 SW Release version 2.0
- * 
- * -- Copyright Notice --
- * 
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- * 
- * @par
- * SPDX-License-Identifier:	BSD-3-Clause
- * @par
- * -- End of Copyright Notice --
-*/
-
-/**
- * @defgroup IxEthNpe IXP400 Ethernet NPE (IxEthNpe) API
- *
- * @brief Contains the API for Ethernet NPE.
- * 
- * All messages given to NPE, get back an acknowledgment. The acknowledgment 
- * is identical to the message sent to the NPE (except for NPE_GETSTATUS message).
- *
- * @{
- */
-
-
-/*--------------------------------------------------------------------------
- * APB Message IDs - XScale->NPE
- *------------------------------------------------------------------------*/
-
-/**
- * @def IX_ETHNPE_NPE_GETSTATUS
- *
- * @brief Request from the XScale client for the NPE to return the firmware
- * version of the currently executing image.
- *
- * Acknowledgment message id is same as the request message id. 
- * NPE returns the firmware version ID to XScale.
- */
-#define IX_ETHNPE_NPE_GETSTATUS                 0x00
-
-/**
- * @def IX_ETHNPE_EDB_SETPORTADDRESS
- *
- * @brief Request from the XScale client for the NPE to set the Ethernet 
- * port's port ID and MAC address. 
- */
-#define IX_ETHNPE_EDB_SETPORTADDRESS            0x01
-
-/**
- * @def IX_ETHNPE_EDB_GETMACADDRESSDATABASE
- *
- * @brief Request from XScale client to the NPE requesting upload of 
- * Ethernet Filtering Database or Header Conversion Database from NPE's 
- * data memory to XScale accessible SDRAM.
- */
-#define IX_ETHNPE_EDB_GETMACADDRESSDATABASE     0x02
-
-/**
- * @def IX_ETHNPE_EDB_SETMACADDRESSSDATABASE
- *
- * @brief Request from XScale client to the NPE requesting download of 
- * Ethernet Filtering Database or Header Conversion Database from SDRAM
- * to the NPE's datamemory.
- */
-#define IX_ETHNPE_EDB_SETMACADDRESSSDATABASE    0x03
-
-/**
- * @def IX_ETHNPE_GETSTATS
- *
- * @brief Request from the XScale client for the current MAC port statistics 
- * data to be written to the (empty) statistics structure and the specified
- * location in externa memory.
- */
-#define IX_ETHNPE_GETSTATS                      0x04
-
-/**
- * @def IX_ETHNPE_RESETSTATS
- *
- * @brief Request from the XScale client to the NPE to reset all of its internal 
- * MAC port statistics state variables. 
- *
- * As a side effect, this message entails an implicit request that the NPE
- *  write the current MAC port statistics into the MAC statistics structure 
- * at the specified location in external memory.
- */
-#define IX_ETHNPE_RESETSTATS                    0x05
-
-/**
- * @def IX_ETHNPE_SETMAXFRAMELENGTHS
- *
- * @brief Request from the XScale client to the NPE to configure maximum framelengths
- * and block sizes in receive and transmit direction.
- */
-#define IX_ETHNPE_SETMAXFRAMELENGTHS            0x06
-
-/**
- * @def IX_ETHNPE_VLAN_SETRXTAGMODE
- *
- * @brief Request from the XScale client to the NPE to configure VLAN frame type
- * filtering and VLAN the tagging mode for the receiver.
- */
-#define IX_ETHNPE_VLAN_SETRXTAGMODE             0x07
-
-/**
- * @def IX_ETHNPE_VLAN_SETDEFAULTRXVID
- *
- * @brief Request from the XScale client to the NPE to set receiver's default 
- * VLAN tag (PVID)and internal traffic class.
- */
-#define IX_ETHNPE_VLAN_SETDEFAULTRXVID          0x08
-
-/**
- * @def IX_ETHNPE_VLAN_SETPORTVLANTABLEENTRY
- *
- * @brief Request from the XScale client to the NPE to configure VLAN Port 
- * membership and Tx tagging for 8 consecutive VLANID's.
- */
-#define IX_ETHNPE_VLAN_SETPORTVLANTABLEENTRY    0x09
-
-/**
- * @def IX_ETHNPE_VLAN_SETPORTVLANTABLERANGE
- *
- * @brief Request from the XScale client to the NPE to configure VLAN Port
- * membership and Tx tagging for a range of VLANID's.
- */
-#define IX_ETHNPE_VLAN_SETPORTVLANTABLERANGE    0x0A
-
-/**
- * @def IX_ETHNPE_VLAN_SETRXQOSENTRY
- *
- * @brief Request from the XScale client to the NPE to map a user priority
- * to QoS class and an AQM queue number.
- */
-#define IX_ETHNPE_VLAN_SETRXQOSENTRY            0x0B
-
-/**
- * @def IX_ETHNPE_VLAN_SETPORTIDEXTRACTIONMODE
- *
- * @brief Request from the XScale client to the NPE to enable or disable
- * portID extraction from VLAN-tagged frames for the specified port.
- */
-#define IX_ETHNPE_VLAN_SETPORTIDEXTRACTIONMODE  0x0C
-
-/**
- * @def IX_ETHNPE_STP_SETBLOCKINGSTATE
- *
- * @brief Request from the XScale client to the NPE to block or unblock
- * forwarding for spanning tree BPDUs.
- */
-#define IX_ETHNPE_STP_SETBLOCKINGSTATE          0x0D
-
-/**
- * @def IX_ETHNPE_FW_SETFIREWALLMODE
- *
- * @brief Request from the XScale client to the NPE to configure firewall
- * services modes of operation and/or download Ethernet Firewall Database from
- * SDRAM to NPE.
- */
-#define IX_ETHNPE_FW_SETFIREWALLMODE            0x0E
-
-/**
- * @def IX_ETHNPE_PC_SETFRAMECONTROLDURATIONID 
- *
- * @brief Request from the XScale client to the NPE to set global frame control
- * and duration/ID field for the 802.3 to 802.11 protocol header conversion
- * service.
- */
-#define IX_ETHNPE_PC_SETFRAMECONTROLDURATIONID  0x0F
-
-/**
- * @def IX_ETHNPE_PC_SETBBSID
- *
- * @brief Request from the XScale client to the NPE to set global BBSID field
- * value for the 802.3 to 802.11 protocol header conversion service. 
- */
-#define IX_ETHNPE_PC_SETBBSID                   0x10
-
-/**
- * @def IX_ETHNPE_PC_SETAPMACTABLE
- *
- * @brief Request from the XScale client to the NPE to update a block/section/
- * range of the AP MAC Address Table.
- */
-#define IX_ETHNPE_PC_SETAPMACTABLE              0x11
-
-/**
- * @def IX_ETHNPE_SETLOOPBACK_MODE
- *
- * @brief Turn on or off the NPE frame loopback.
- */
-#define IX_ETHNPE_SETLOOPBACK_MODE              (0x12)
-
-/*--------------------------------------------------------------------------
- * APB Message IDs - NPE->XScale
- *------------------------------------------------------------------------*/
-
-/**
- * @def IX_ETHNPE_NPE_GETSTATUS_ACK
- *
- * @brief Acknowledgment to IX_ETHNPE_NPE_GETSTATUS message. NPE firmware version 
- * id is returned in the message.
- */
-#define IX_ETHNPE_NPE_GETSTATUS_ACK                 0x00
-
-/**
- * @def IX_ETHNPE_EDB_SETPORTADDRESS_ACK
- *
- * @brief Acknowledgment to IX_ETHNPE_EDB_SETPORTADDRESS message.
- */
-#define IX_ETHNPE_EDB_SETPORTADDRESS_ACK            0x01
-
-/**
- * @def IX_ETHNPE_EDB_GETMACADDRESSDATABASE_ACK
- *
- * @brief Acknowledgment to IX_ETHNPE_EDB_GETMACADDRESSDATABASE message
- */
-#define IX_ETHNPE_EDB_GETMACADDRESSDATABASE_ACK     0x02
-
-/**
- * @def IX_ETHNPE_EDB_SETMACADDRESSSDATABASE_ACK
- *
- * @brief Acknowledgment to IX_ETHNPE_EDB_SETMACADDRESSSDATABASE message.
- */
-#define IX_ETHNPE_EDB_SETMACADDRESSSDATABASE_ACK    0x03
-
-/**
- * @def IX_ETHNPE_GETSTATS_ACK
- *
- * @brief Acknowledgment to IX_ETHNPE_GETSTATS message.
- */
-#define IX_ETHNPE_GETSTATS_ACK                      0x04
-
-/**
- * @def IX_ETHNPE_RESETSTATS_ACK
- *
- * @brief Acknowledgment to IX_ETHNPE_RESETSTATS message.
- */
-#define IX_ETHNPE_RESETSTATS_ACK                    0x05
-
-/**
- * @def IX_ETHNPE_SETMAXFRAMELENGTHS_ACK
- *
- * @brief Acknowledgment to IX_ETHNPE_SETMAXFRAMELENGTHS message.
- */
-#define IX_ETHNPE_SETMAXFRAMELENGTHS_ACK            0x06
-
-/**
- * @def IX_ETHNPE_VLAN_SETRXTAGMODE_ACK
- *
- * @brief Acknowledgment to IX_ETHNPE_VLAN_SETRXTAGMODE message.
- */
-#define IX_ETHNPE_VLAN_SETRXTAGMODE_ACK             0x07
-
-/**
- * @def IX_ETHNPE_VLAN_SETDEFAULTRXVID_ACK
- *
- * @brief Acknowledgment to IX_ETHNPE_VLAN_SETDEFAULTRXVID  message.
- */
-#define IX_ETHNPE_VLAN_SETDEFAULTRXVID_ACK          0x08
-
-/**
- * @def IX_ETHNPE_VLAN_SETPORTVLANTABLEENTRY_ACK
- *
- * @brief Acknowledgment to IX_ETHNPE_VLAN_SETPORTVLANTABLEENTRY message.
- */
-#define IX_ETHNPE_VLAN_SETPORTVLANTABLEENTRY_ACK    0x09
-
-/**
- * @def IX_ETHNPE_VLAN_SETPORTVLANTABLERANGE_ACK
- *
- * @brief Acknowledgment to IX_ETHNPE_VLAN_SETPORTVLANTABLERANGE message.
- */
-#define IX_ETHNPE_VLAN_SETPORTVLANTABLERANGE_ACK    0x0A
-
-/**
- * @def IX_ETHNPE_VLAN_SETRXQOSENTRY_ACK
- *
- * @brief Acknowledgment to IX_ETHNPE_VLAN_SETRXQOSENTRY message.
- */
-#define IX_ETHNPE_VLAN_SETRXQOSENTRY_ACK            0x0B
-
-/**
- * @def IX_ETHNPE_VLAN_SETPORTIDEXTRACTIONMODE_ACK
- *
- * @brief Acknowledgment to IX_ETHNPE_VLAN_SETPORTIDEXTRACTIONMODE message.
- */
-#define IX_ETHNPE_VLAN_SETPORTIDEXTRACTIONMODE_ACK  0x0C
-
-/**
- * @def IX_ETHNPE_STP_SETBLOCKINGSTATE_ACK
- *
- * @brief Acknowledgment to IX_ETHNPE_STP_SETBLOCKINGSTATE message.
- */
-#define IX_ETHNPE_STP_SETBLOCKINGSTATE_ACK          0x0D
-
-/**
- * @def IX_ETHNPE_FW_SETFIREWALLMODE_ACK
- *
- * @brief Acknowledgment to IX_ETHNPE_FW_SETFIREWALLMODE message. 
- */
-#define IX_ETHNPE_FW_SETFIREWALLMODE_ACK            0x0E
-
-/**
- * @def IX_ETHNPE_PC_SETFRAMECONTROLDURATIONID_ACK
- *
- * @brief Acknowledgment to IX_ETHNPE_PC_SETFRAMECONTROLDURATIONID message.
- */
-#define IX_ETHNPE_PC_SETFRAMECONTROLDURATIONID_ACK  0x0F
-
-/**
- * @def IX_ETHNPE_PC_SETBBSID_ACK
- *
- * @brief Acknowledgment to IX_ETHNPE_PC_SETBBSID message.
- */
-#define IX_ETHNPE_PC_SETBBSID_ACK                   0x10
-
-/**
- * @def IX_ETHNPE_PC_SETAPMACTABLE_ACK
- *
- * @brief Acknowledgment to IX_ETHNPE_PC_SETAPMACTABLE message.
- */
-#define IX_ETHNPE_PC_SETAPMACTABLE_ACK              0x11
-
-/**
- * @def IX_ETHNPE_SETLOOPBACK_MODE_ACK
- *
- * @brief Acknowledgment to IX_ETHNPE_SETLOOPBACK_MODE message.
- */
-#define IX_ETHNPE_SETLOOPBACK_MODE_ACK              (0x12)
-
-/*--------------------------------------------------------------------------
- * Queue Manager Queue entry bit field boundary definitions
- *------------------------------------------------------------------------*/
-
-/**
- * @def MASK(hi,lo)
- *
- * @brief Macro for mask
- */
-#define MASK(hi,lo)                    (((1 << (1 + ((hi) - (lo)))) - 1) << (lo))
-
-/**
- * @def BITS(x,hi,lo)
- *
- * @brief Macro for bits
- */
-#define BITS(x,hi,lo)                  (((x) & MASK(hi,lo)) >> (lo))
-
-/**
- * @def IX_ETHNPE_QM_Q_RXENET_LENGTH_MASK
- *
- * @brief QMgr Queue LENGTH field mask
- */
-#define IX_ETHNPE_QM_Q_RXENET_LENGTH_MASK   0x3fff
-
-/**
- * @def IX_ETHNPE_QM_Q_FIELD_FLAG_R
- *
- * @brief QMgr Queue FLAG field right boundary
- */
-#define IX_ETHNPE_QM_Q_FIELD_FLAG_R             20
-
-/**
- * @def IX_ETHNPE_QM_Q_FIELD_FLAG_MASK
- *
- * @brief QMgr Queue FLAG field mask
- *
- * Multicast bit : BIT(4)
- * Broadcast bit : BIT(5)
- * IP bit        : BIT(6) (linux only)
- *
- */
-#ifdef __vxworks
-#define IX_ETHNPE_QM_Q_FIELD_FLAG_MASK           0x30
-#else
-#define IX_ETHNPE_QM_Q_FIELD_FLAG_MASK           0x70
-#endif
-
-
-/**
- * @def IX_ETHNPE_QM_Q_FIELD_NPEID_L
- *
- * @brief QMgr Queue NPE ID field left boundary
- */
-#define IX_ETHNPE_QM_Q_FIELD_NPEID_L            1
-
-/**
- * @def IX_ETHNPE_QM_Q_FIELD_NPEID_R
- *
- * @brief QMgr Queue NPE ID field right boundary
- */
-#define IX_ETHNPE_QM_Q_FIELD_NPEID_R            0
-
-/**
- * @def IX_ETHNPE_QM_Q_FIELD_PRIOR_L
- *
- * @brief QMgr Queue Priority field left boundary
- */
-#define IX_ETHNPE_QM_Q_FIELD_PRIOR_L            2
-
-/**
- * @def IX_ETHNPE_QM_Q_FIELD_PRIOR_R
- *
- * @brief QMgr Queue Priority field right boundary
- */
-#define IX_ETHNPE_QM_Q_FIELD_PRIOR_R            0
-
-/**
- * @def IX_ETHNPE_QM_Q_FIELD_ADDR_L 
- *
- * @brief QMgr Queue Address field left boundary
- */
-#define IX_ETHNPE_QM_Q_FIELD_ADDR_L             31
-
-/**
- * @def IX_ETHNPE_QM_Q_FIELD_ADDR_R
- *
- * @brief QMgr Queue Address field right boundary
- */
-#define IX_ETHNPE_QM_Q_FIELD_ADDR_R              5
-
-/*--------------------------------------------------------------------------
- * Queue Manager Queue entry bit field masks
- *------------------------------------------------------------------------*/
-
-/**
- * @def IX_ETHNPE_QM_Q_FREEENET_ADDR_MASK 
- *
- * @brief Macro to mask the Address field of the FreeEnet Queue Manager Entry
- */
-#define IX_ETHNPE_QM_Q_FREEENET_ADDR_MASK \
-            MASK (IX_ETHNPE_QM_Q_FIELD_ADDR_L, \
-                  IX_ETHNPE_QM_Q_FIELD_ADDR_R)
-
-/**
- * @def IX_ETHNPE_QM_Q_RXENET_NPEID_MASK  
- *
- * @brief Macro to mask the NPE ID field of the RxEnet Queue Manager Entry
- */
-#define IX_ETHNPE_QM_Q_RXENET_NPEID_MASK \
-            MASK (IX_ETHNPE_QM_Q_FIELD_NPEID_L, \
-                  IX_ETHNPE_QM_Q_FIELD_NPEID_R)
-
-/**
- * @def IX_ETHNPE_QM_Q_RXENET_ADDR_MASK 
- *
- * @brief Macro to mask the Mbuf Address field of the RxEnet Queue Manager Entry
- */
-#define IX_ETHNPE_QM_Q_RXENET_ADDR_MASK \
-            MASK (IX_ETHNPE_QM_Q_FIELD_ADDR_L, \
-                  IX_ETHNPE_QM_Q_FIELD_ADDR_R)
-
-/**
- * @def IX_ETHNPE_QM_Q_TXENET_PRIOR_MASK
- *
- * @brief Macro to mask the Priority field of the TxEnet Queue Manager Entry
- */
-#define IX_ETHNPE_QM_Q_TXENET_PRIOR_MASK \
-            MASK (IX_ETHNPE_QM_Q_FIELD_PRIOR_L, \
-                  IX_ETHNPE_QM_Q_FIELD_PRIOR_R)
-
-/**
- * @def IX_ETHNPE_QM_Q_TXENET_ADDR_MASK 
- *
- * @brief Macro to mask the Mbuf Address field of the TxEnet Queue Manager Entry
- */
-#define IX_ETHNPE_QM_Q_TXENET_ADDR_MASK \
-            MASK (IX_ETHNPE_QM_Q_FIELD_ADDR_L, \
-                  IX_ETHNPE_QM_Q_FIELD_ADDR_R)
-
-/**
- * @def IX_ETHNPE_QM_Q_TXENETDONE_NPEID_MASK 
- *
- * @brief Macro to mask the NPE ID field of the TxEnetDone Queue Manager Entry
- */
-#define IX_ETHNPE_QM_Q_TXENETDONE_NPEID_MASK \
-            MASK (IX_ETHNPE_QM_Q_FIELD_NPEID_L, \
-                  IX_ETHNPE_QM_Q_FIELD_NPEID_R)
-
-/**
- * @def IX_ETHNPE_QM_Q_TXENETDONE_ADDR_MASK 
- * 
- * @brief Macro to mask the Mbuf Address field of the TxEnetDone Queue Manager 
- * Entry
- */
-#define IX_ETHNPE_QM_Q_TXENETDONE_ADDR_MASK \
-            MASK (IX_ETHNPE_QM_Q_FIELD_ADDR_L, \
-                  IX_ETHNPE_QM_Q_FIELD_ADDR_R)
-
-/*--------------------------------------------------------------------------
- * Queue Manager Queue entry bit field value extraction macros
- *------------------------------------------------------------------------*/
-
-/**
- * @def IX_ETHNPE_QM_Q_FREEENET_ADDR_VAL(x)
- *
- * @brief Extraction macro for Address field of FreeNet Queue Manager Entry 
- *
- * Pointer to an mbuf buffer descriptor
- */
-#define IX_ETHNPE_QM_Q_FREEENET_ADDR_VAL(x) \
-            ((x) & IX_ETHNPE_QM_Q_FREEENET_ADDR_MASK)
-
-/**
- * @def IX_ETHNPE_QM_Q_RXENET_NPEID_VAL(x)
- *
- * @brief Extraction macro for NPE ID field of RxEnet Queue Manager Entry 
- *
- * Set to 0 for entries originating from the Eth0 NPE; 
- * Set to 1 for entries originating from the Eth1 NPE.
- */
-#define IX_ETHNPE_QM_Q_RXENET_NPEID_VAL(x) \
-            BITS (x, IX_ETHNPE_QM_Q_FIELD_NPEID_L, \
-                     IX_ETHNPE_QM_Q_FIELD_NPEID_R)
-
-/**
- * @def IX_ETHNPE_QM_Q_RXENET_PORTID_VAL(x)
- *
- * @brief Extraction macro for Port ID field of RxEnet Queue Manager Entry 
- *
- * 0-5: Assignable (by the XScale client) to any of the physical ports.
- * 6: It is reserved
- * 7: Indication that the NPE did not find the associated frame's destination MAC address within 
- * its internal filtering database.
- */
-#define IX_ETHNPE_QM_Q_RXENET_PORTID_VAL(x) \
-            BITS (x, IX_ETHNPE_QM_Q_FIELD_PORTID_L, \
-                     IX_ETHNPE_QM_Q_Field_PortID_R)
-
-/**
- * @def IX_ETHNPE_QM_Q_RXENET_ADDR_VAL(x)
- *
- * @brief Extraction macro for Address field of RxEnet Queue Manager Entry
- *
- * Pointer to an mbuf buffer descriptor
- */
-#define IX_ETHNPE_QM_Q_RXENET_ADDR_VAL(x) \
-            ((x) & IX_ETHNPE_QM_Q_RXENET_ADDR_MASK)
-
-/**
- * @def IX_ETHNPE_QM_Q_TXENET_PRIOR_VAL(x)
- *
- * @brief Extraction macro for Priority field of TxEnet Queue Manager Entry
- *
- * Priority of the packet (as described in IEEE 802.1D). This field is
- * cleared upon return from the Ethernet NPE to the TxEnetDone queue.
- */
-#define IX_ETHNPE_QM_Q_TXENET_PRIOR_VAL(x) \
-            BITS (x, IX_ETHNPE_QM_Q_FIELD_PRIOR_L, \
-                     IX_ETHNPE_QM_Q_FIELD_PRIOR_R)
-
-/**
- * @def IX_ETHNPE_QM_Q_TXENET_ADDR_VAL(x)
- *
- * @brief Extraction macro for Address field of Queue Manager TxEnet Queue 
- * Manager Entry
- *
- * Pointer to an mbuf buffer descriptor
- */
-#define IX_ETHNPE_QM_Q_TXENET_ADDR_VAL(x) \
-            ((x) & IX_ETHNPE_QM_Q_TXENET_ADDR_MASK)
-
-/**
- * @def IX_ETHNPE_QM_Q_TXENETDONE_NPEID_VAL(x)
- *
- * @brief Extraction macro for NPE ID field of TxEnetDone Queue Manager Entry
- *
- * Set to 0 for entries originating from the Eth0 NPE; set to 1 for en-tries 
- * originating from the Eth1 NPE.
- */
-#define IX_ETHNPE_QM_Q_TXENETDONE_NPEID_VAL(x) \
-            BITS (x, IX_ETHNPE_QM_Q_FIELD_NPEID_L, \
-                     IX_ETHNPE_QM_Q_FIELD_NPEID_R)
-
-/**
- * @def IX_ETHNPE_QM_Q_TXENETDONE_ADDR_VAL(x)
- *
- * @brief Extraction macro for Address field of TxEnetDone Queue Manager Entry
- *
- * Pointer to an mbuf buffer descriptor
- */
-#define IX_ETHNPE_QM_Q_TXENETDONE_ADDR_VAL(x) \
-            ((x) & IX_ETHNPE_QM_Q_TXENETDONE_ADDR_MASK)
-
-
-/*--------------------------------------------------------------------------
- * NPE limits
- *------------------------------------------------------------------------*/
-
-/**
- * @def IX_ETHNPE_ACC_RXFREE_BUFFER_LENGTH_MIN
- * 
- * @brief Macro to check the minimum length of a rx free buffer
- */
-#define IX_ETHNPE_ACC_RXFREE_BUFFER_LENGTH_MIN (64)
-
-/**
- * @def IX_ETHNPE_ACC_RXFREE_BUFFER_LENGTH_MASK
- * 
- * @brief Mask to apply to the mbuf length before submitting it to the NPE
- * (the NPE handles only rx free mbufs which are multiple of 64)
- * 
- * @sa IX_ETHNPE_ACC_RXFREE_BUFFER_LENGTH_MASK
- */
-#define IX_ETHNPE_ACC_RXFREE_BUFFER_LENGTH_MASK (~63)
-
-/**
- * @def IX_ETHNPE_ACC_RXFREE_BUFFER_ROUND_UP(size)
- * 
- * @brief  Round up to get the size necessary to receive without chaining
- * the frames which are (size) bytes (the NPE operates by multiple of 64)
- * e.g. To receive 1514 bytes frames, the size of the buffers in replenish
- * has to be at least (1514+63)&(~63) = 1536 bytes.
- *
- */
-#define IX_ETHNPE_ACC_RXFREE_BUFFER_ROUND_UP(size) (((size) + 63) & ~63)
-
-/**
- * @def IX_ETHNPE_ACC_RXFREE_BUFFER_ROUND_DOWN(size)
- *
- * @brief Round down to apply to the mbuf length before submitting
- * it to the NPE. (the NPE operates by multiple of 64)
- *
- */
-#define IX_ETHNPE_ACC_RXFREE_BUFFER_ROUND_DOWN(size) ((size) & ~63)
-
-/**
- * @def IX_ETHNPE_ACC_FRAME_LENGTH_MAX
- * 
- * @brief maximum mbuf length supported by the NPE
- * 
- * @sa IX_ETHNPE_ACC_FRAME_LENGTH_MAX
- */
-#define IX_ETHNPE_ACC_FRAME_LENGTH_MAX (16320)
-
-/**
- * @def IX_ETHNPE_ACC_FRAME_LENGTH_DEFAULT
- * 
- * @brief default mbuf length supported by the NPE
- * 
- * @sa IX_ETHNPE_ACC_FRAME_LENGTH_DEFAULT
- */
-#define IX_ETHNPE_ACC_FRAME_LENGTH_DEFAULT (1522)
-
-/**
- * @def IX_ETHNPE_ACC_LENGTH_OFFSET
- *
- * @brief Offset of the cluster length field in the word shared with the NPEs
- */
-#define IX_ETHNPE_ACC_LENGTH_OFFSET 16
-
-/**
- * @def IX_ETHNPE_ACC_PKTLENGTH_MASK
- *
- * @brief Mask of the cluster length field in the word shared with the NPEs
- */
-#define IX_ETHNPE_ACC_PKTLENGTH_MASK 0x3fff
-
-
-/**
- *@}
- */
-
-#endif /* __doxygen_HIDE */
diff --git a/drivers/net/npe/include/IxFeatureCtrl.h b/drivers/net/npe/include/IxFeatureCtrl.h
deleted file mode 100644
index 987b00b562..0000000000
--- a/drivers/net/npe/include/IxFeatureCtrl.h
+++ /dev/null
@@ -1,718 +0,0 @@
-/**
- * @file IxFeatureCtrl.h
- *
- * @date 30-Jan-2003
-
- * @brief This file contains the public API of the IXP400 Feature Control
- *        component.
- *
- * 
- * @par
- * IXP400 SW Release version 2.0
- * 
- * -- Copyright Notice --
- * 
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- * 
- * @par
- * SPDX-License-Identifier:	BSD-3-Clause
- * @par
- * -- End of Copyright Notice --
-*/
-/* ------------------------------------------------------
-   Doxygen group definitions
-   ------------------------------------------------------ */
-/**
- * @defgroup IxFeatureCtrlAPI IXP400 Feature Control (IxFeatureCtrl) API
- *
- * @brief The Public API for the IXP400 Feature Control.
- * 
- * @{
- */
-
-#ifndef IXFEATURECTRL_H
-#define IXFEATURECTRL_H
-
-/*
- * User defined include files
- */
-#include "IxOsal.h"
-
-/*
- * #defines and macros
- */
-
-/*************************************************************
- * The following are IxFeatureCtrlComponentCheck return values.
- ************************************************************/
-
-/**
- * @ingroup IxFeatureCtrlAPI 
- *
- * @def  IX_FEATURE_CTRL_COMPONENT_DISABLED
- *
- * @brief Hardware Component is disabled/unavailable.
- *        Return status by ixFeatureCtrlComponentCheck()  
- */
-#define  IX_FEATURE_CTRL_COMPONENT_DISABLED 0
-
-/**
- * @ingroup IxFeatureCtrlAPI 
- *
- * @def  IX_FEATURE_CTRL_COMPONENT_ENABLED
- *
- * @brief Hardware Component is available. 
- *        Return status by ixFeatureCtrlComponentCheck()  
- */
-#define  IX_FEATURE_CTRL_COMPONENT_ENABLED  1
-
-/***********************************************************************************
- * Product ID in XScale CP15 - Register 0
- *  - It contains information on the maximum XScale Core Frequency and
- *    Silicon Stepping.  
- *  - XScale Core Frequency Id indicates only the maximum XScale frequency
- *    achievable and not the running XScale frequency (maybe stepped down).    
- *  - The register is read by using ixFeatureCtrlProductIdRead.
- *  - Usage example: 
- *          productId = ixFeatureCtrlProductIdRead();
- *          if( (productId & IX_FEATURE_CTRL_SILICON_STEPPING_MASK) == 
- *              IX_FEATURE_CTRL_SILICON_TYPE_A0 )
- *          if( (productId & IX_FEATURE_CTRL_XSCALE_FREQ_MASK) == 
- *              IX_FEATURE_CTRL_XSCALE_FREQ_533 )    
- * 
- *  31 28 27 24 23 20 19 16 15 12 11        9 8                   4 3              0  
- *  -------------------------------------------------------------------------------- 
- * | 0x6 | 0x9 | 0x0 | 0x5 | 0x4 | Device ID | XScale Core Freq Id | Si Stepping Id |    
- *  --------------------------------------------------------------------------------
- *
- *   Maximum Achievable XScale Core Frequency Id :  533MHz  - 0x1C 
- *                                                  400MHz  - 0x1D 
- *                                                  266MHz  - 0x1F
- *
- *   <b>THE CORE FREQUENCY ID IS NOT APPLICABLE TO IXP46X <\b>
- *  
- *   The above is applicable to IXP42X only. CP15 in IXP46X does not contain any
- *   Frequency ID. 
- * 
- *  Si Stepping Id            :  A       - 0x0    
- *                               B       - 0x1 
- *  
- *  XScale Core freq Id - Device ID [11:9] : IXP42X - 0x0
- *                                           IXP46X - 0x1
- *************************************************************************************/
-
-/**
- * @ingroup IxFeatureCtrlAPI 
- *
- * @def IX_FEATURE_CTRL_SILICON_TYPE_A0
- *
- * @brief This is the value of A0 Silicon in product ID. 
- */
-#define IX_FEATURE_CTRL_SILICON_TYPE_A0   0
-
-/**
- * @ingroup IxFeatureCtrlAPI 
- *
- * @def IX_FEATURE_CTRL_SILICON_TYPE_B0
- *
- * @brief This is the value of B0 Silicon in product ID.
- */
-#define IX_FEATURE_CTRL_SILICON_TYPE_B0   1
-
-/**
- * @ingroup IxFeatureCtrlAPI 
- *
- * @def IX_FEATURE_CTRL_SILICON_STEPPING_MASK
- *
- * @brief This is the mask of silicon stepping in product ID. 
- */
-#define IX_FEATURE_CTRL_SILICON_STEPPING_MASK  0xF 
-
-/**
- * @ingroup IxFeatureCtrlAPI
- *
- * @def IX_FEATURE_CTRL_DEVICE_TYPE_MASK
- *
- * @brief This is the mask of silicon stepping in product ID.
- */
-#define IX_FEATURE_CTRL_DEVICE_TYPE_MASK  (0x7) 
-
-/**
- * @ingroup IxFeatureCtrlAPI
- *
- * @def IX_FEATURE_CTRL_DEVICE_TYPE_OFFSET
- *
- * @brief This is the mask of silicon stepping in product ID.
- */
-#define IX_FEATURE_CTRL_DEVICE_TYPE_OFFSET  9
-
-
-/**
- * @ingroup IxFeatureCtrlAPI 
- *
- * @def IX_FEATURE_CTRL_XSCALE_FREQ_533
- *
- * @brief This is the value of 533MHz XScale Core in product ID.
- */
-#define IX_FEATURE_CTRL_XSCALE_FREQ_533  ((0x1C)<<4)
-
-/**
- * @ingroup IxFeatureCtrlAPI 
- *
- * @def IX_FEATURE_CTRL_XSCALE_FREQ_400
- *
- * @brief This is the value of 400MHz XScale Core in product ID.
- */
-#define IX_FEATURE_CTRL_XSCALE_FREQ_400  ((0x1D)<<4)
-
-/**
- * @ingroup IxFeatureCtrlAPI 
- *
- * @def IX_FEATURE_CTRL_XSCALE_FREQ_266
- *
- * @brief This is the value of 266MHz XScale Core in product ID.
- */
-#define IX_FEATURE_CTRL_XSCALE_FREQ_266 ((0x1F)<<4)   
-
-/**
- * @ingroup IxFeatureCtrlAPI 
- *
- * @def IX_FEATURE_CTRL_XSCALE_FREQ_MASK
- *
- * @brief This is the mask of XScale Core in product ID.
- */
-#define IX_FEATURE_CTRL_XSCALE_FREQ_MASK ((0xFF)<<4)  
-
-/**
- * @ingroup IxFeatureCtrlAPI 
- *
- * @def IX_FEATURECTRL_REG_UTOPIA_32PHY
- *
- * @brief Maximum  UTOPIA PHY available is 32.  
- * 
- */
-#define IX_FEATURECTRL_REG_UTOPIA_32PHY  0x0
-
-/**
- * @ingroup IxFeatureCtrlAPI 
- *
- * @def IX_FEATURECTRL_REG_UTOPIA_16PHY
- *
- * @brief Maximum  UTOPIA PHY available is 16.  
- * 
- */
-#define IX_FEATURECTRL_REG_UTOPIA_16PHY  0x1
-
-/**
- * @ingroup IxFeatureCtrlAPI 
- *
- * @def IX_FEATURECTRL_REG_UTOPIA_8PHY
- *
- * @brief Maximum  UTOPIA PHY available to is 8.  
- * 
- */
-#define IX_FEATURECTRL_REG_UTOPIA_8PHY   0x2
-
-/**
- * @ingroup IxFeatureCtrlAPI 
- *
- * @def IX_FEATURECTRL_REG_UTOPIA_4PHY
- *
- * @brief Maximum  UTOPIA PHY available to is 4.  
- * 
- */
-#define IX_FEATURECTRL_REG_UTOPIA_4PHY   0x3
-
-#ifdef __ixp46X
-
-/**
- * @ingroup IxFeatureCtrlAPI
- *
- * @def IX_FEATURECTRL_REG_XSCALE_533FREQ
- *
- * @brief Maximum  frequency available to IXP46x is 533 MHz.
- *
- */
-#define IX_FEATURECTRL_REG_XSCALE_533FREQ   0x0
-
-/**
- * @ingroup IxFeatureCtrlAPI
- *
- * @def IX_FEATURECTRL_REG_XSCALE_667FREQ
- *
- * @brief Maximum  frequency available to IXP46x is 667 MHz.
- *
- */
-#define IX_FEATURECTRL_REG_XSCALE_667FREQ   0x1
-
-/**
- * @ingroup IxFeatureCtrlAPI
- *
- * @def IX_FEATURECTRL_REG_XSCALE_400FREQ
- *
- * @brief Maximum  frequency available to IXP46x is 400 MHz.
- *
- */
-#define IX_FEATURECTRL_REG_XSCALE_400FREQ   0x2
-
-/**
- * @ingroup IxFeatureCtrlAPI
- *
- * @def IX_FEATURECTRL_REG_XSCALE_266FREQ
- *
- * @brief Maximum  frequency available to IXP46x is 266 MHz.
- *
- */
-#define IX_FEATURECTRL_REG_XSCALE_266FREQ   0x3
-
-#endif /* __ixp46X */
-
-/**
- * @ingroup IxFeatureCtrlAPI
- *
- * @def IX_FEATURECTRL_COMPONENT_NOT_AVAILABLE
- *
- * @brief Component selected is not available for device
- *
- */
-#define IX_FEATURECTRL_COMPONENT_NOT_AVAILABLE  0x0000
-
-/**
- * @ingroup IxFeatureCtrlAPI
- *
- * @def IX_FEATURECTRL_COMPONENT_ALWAYS_AVAILABLE
- *
- * @brief Component selected is not available for device
- *
- */
-#define IX_FEATURECTRL_COMPONENT_ALWAYS_AVAILABLE  0xffff
-
-/**
- * @defgroup IxFeatureCtrlSwConfig Software Configuration for Access Component
- *
- * @ingroup IxFeatureCtrlAPI 
- *
- * @brief This section describes software configuration in access component. The
- *        configuration can be changed at run-time. ixFeatureCtrlSwConfigurationCheck( )
- *        will be used across applicable access component to check the configuration.
- *        ixFeatureCtrlSwConfigurationWrite( ) is used to write the software configuration.
- *
- * @note <b>All software configurations are default to be enabled.</b> 
- *
- * @{
- */
-/**
- * @ingroup IxFeatureCtrlSwConfig
- *
- * @def IX_FEATURE_CTRL_SWCONFIG_DISABLED
- *
- * @brief Software configuration is disabled. 
- * 
- */
-#define IX_FEATURE_CTRL_SWCONFIG_DISABLED 0  
-
-/**
- * @ingroup IxFeatureCtrlSwConfig
- *
- * @def IX_FEATURE_CTRL_SWCONFIG_ENABLED
- *
- * @brief Software configuration is enabled. 
- * 
- */
-#define IX_FEATURE_CTRL_SWCONFIG_ENABLED 1  
-
-/**
- * Section for enums
- **/
-
-/**
- * @ingroup IxFeatureCtrlBuildDevice
- *
- * @enum IxFeatureCtrlBuildDevice
- *
- * @brief Indicates software build type.
- *
- * Default build type is IXP42X
- *
- */
-typedef enum
-{
-    IX_FEATURE_CTRL_SW_BUILD_IXP42X = 0, /**<Build type is IXP42X */
-    IX_FEATURE_CTRL_SW_BUILD_IXP46X      /**<Build type is IXP46X */
-} IxFeatureCtrlBuildDevice;
-
-/**
- * @ingroup IxFeatureCtrlSwConfig
- *
- * @enum IxFeatureCtrlSwConfig
- *
- * @brief Enumeration for software configuration in access components.
- *
- * Entry for new run-time software configuration should be added here.
- */
-typedef enum
-{
-    IX_FEATURECTRL_ETH_LEARNING = 0,       /**< EthDB Learning Feature */
-    IX_FEATURECTRL_ORIGB0_DISPATCHER,  /**< IXP42X B0 and IXP46X dispatcher without 
-                                            livelock prevention functionality Feature */
-    IX_FEATURECTRL_SWCONFIG_MAX        /**< Maximum boudary for IxFeatureCtrlSwConfig  */
-} IxFeatureCtrlSwConfig;
-
-
-/************************************************************************
- * IXP400 Feature Control Register
- * - It contains the information (available/unavailable) of IXP425&IXP46X
- *   hardware components in their corresponding bit location.
- * - Bit value of 0 means the hardware component is available
- *   or not software disabled. Hardware component that is available
- *   can be software disabled.
- * - Bit value of 1 means the hardware is unavailable or software
- *   disabled.Hardware component that is unavailable cannot be software
- *   enabled.
- * - Use ixFeatureCtrlHwCapabilityRead() to read the hardware component's
- *   availability.
- * - Use ixFeatureCtrlRead() to get the current IXP425/IXP46X feature control
- *   register value.
- *
- *   Bit            Field Description (Hardware Component Availability)
- *   ---            ---------------------------------------------------
- *    0             RComp Circuitry
- *    1             USB Controller
- *    2             Hashing Coprocessor
- *    3             AES Coprocessor
- *    4             DES Coprocessor
- *    5             HDLC Coprocessor
- *    6             AAL Coprocessor         - Always available in IXP46X
- *    7             HSS Coprocesspr
- *    8             Utopia Coprocessor
- *    9             Ethernet 0 Coprocessor
- *   10             Ethernet 1 Coprocessor
- *   11             NPE A
- *   12             NPE B
- *   13             NPE C
- *   14             PCI Controller
- *   15             ECC/TimeSync Coprocessor -  Only applicable to IXP46X
- *  16-17           Utopia PHY Limit Status : 0x0 - 32 PHY
- *                                            0x1 - 16 PHY
- *                                            0x2 -  8 PHY
- *                                            0x3 -  4 PHY
- *
- *  Portions below are only applicable to IXP46X
- *   18             USB Host Coprocessor
- *   19             NPE A Ethernet - 0 for Enable if Utopia = 1
- *   20             NPE B Ethernet coprocessor 1-3.
- *   21             RSA Crypto Block coprocessor.
- *  22-23           Processor frequency : 0x0 - 533 MHz
- *                                        0x1 - 667 MHz
- *                                        0x2 - 400 MHz
- *                                        0x3 - 266 MHz
- *  24-31           Reserved
- *
- ************************************************************************/
-/*Section generic to both IXP42X and IXP46X*/
-
-/**
- * @ingroup IxFeatureCtrlAPI
- *
- * @enum IxFeatureCtrlComponentType
- *
- * @brief Enumeration for components availavble
- *
- */
-typedef enum
-{
-    IX_FEATURECTRL_RCOMP = 0, /**<bit location for RComp Circuitry*/
-    IX_FEATURECTRL_USB,       /**<bit location for USB Controller*/
-    IX_FEATURECTRL_HASH,      /**<bit location for Hashing Coprocessor*/
-    IX_FEATURECTRL_AES,       /**<bit location for AES Coprocessor*/
-    IX_FEATURECTRL_DES,       /**<bit location for DES Coprocessor*/
-    IX_FEATURECTRL_HDLC,      /**<bit location for HDLC Coprocessor*/
-    IX_FEATURECTRL_AAL,       /**<bit location for AAL Coprocessor*/
-    IX_FEATURECTRL_HSS,       /**<bit location for HSS Coprocessor*/
-    IX_FEATURECTRL_UTOPIA,    /**<bit location for UTOPIA Coprocessor*/
-    IX_FEATURECTRL_ETH0,      /**<bit location for Ethernet 0 Coprocessor*/
-    IX_FEATURECTRL_ETH1,      /**<bit location for Ethernet 1 Coprocessor*/
-    IX_FEATURECTRL_NPEA,      /**<bit location for NPE A*/
-    IX_FEATURECTRL_NPEB,      /**<bit location for NPE B*/
-    IX_FEATURECTRL_NPEC,      /**<bit location for NPE C*/
-    IX_FEATURECTRL_PCI,       /**<bit location for PCI Controller*/
-    IX_FEATURECTRL_ECC_TIMESYNC,     /**<bit location for TimeSync Coprocessor*/
-    IX_FEATURECTRL_UTOPIA_PHY_LIMIT, /**<bit location for Utopia PHY Limit Status*/
-    IX_FEATURECTRL_UTOPIA_PHY_LIMIT_BIT2, /**<2nd bit of PHY limit status*/
-    IX_FEATURECTRL_USB_HOST_CONTROLLER, /**<bit location for USB host controller*/
-    IX_FEATURECTRL_NPEA_ETH,  /**<bit location for NPE-A Ethernet Disable*/
-    IX_FEATURECTRL_NPEB_ETH,  /**<bit location for NPE-B Ethernet 1-3 Coprocessors Disable*/
-    IX_FEATURECTRL_RSA,       /**<bit location for RSA Crypto block Coprocessors Disable*/
-    IX_FEATURECTRL_XSCALE_MAX_FREQ, /**<bit location for XScale max frequency*/
-    IX_FEATURECTRL_XSCALE_MAX_FREQ_BIT2, /**<2nd xscale max freq bit NOT TO BE USED */
-    IX_FEATURECTRL_MAX_COMPONENTS
-} IxFeatureCtrlComponentType;
-
-/**
- * @ingroup IxFeatureCtrlDeviceId
- *
- * @enum IxFeatureCtrlDeviceId
- *
- * @brief Enumeration for device type.
- *
- * @warning This enum is closely related to the npe image. Its format should comply
- *          with formats used in the npe image ImageID. This is indicated by the  
- *          first nibble of the image ID. This should also be in sync with the
- *          with what is defined in CP15.  Current available formats are
- *          - IXP42X - 0000
- *          - IXP46X - 0001
- *
- */
-typedef enum
-{
-    IX_FEATURE_CTRL_DEVICE_TYPE_IXP42X = 0, /**<Device type is IXP42X */
-    IX_FEATURE_CTRL_DEVICE_TYPE_IXP46X, /**<Device type is IXP46X */
-    IX_FEATURE_CTRL_DEVICE_TYPE_MAX /**<Max devices */
-} IxFeatureCtrlDeviceId;
-
-
-/**
- * @} addtogroup IxFeatureCtrlSwConfig
- */
-
-/*
- * Typedefs
- */
-
-/**
- * @ingroup IxFeatureCtrlAPI 
- * 
- * @typedef IxFeatureCtrlReg
- *
- * @brief Feature Control Register that contains hardware components'
- *        availability information.
- */
-typedef UINT32 IxFeatureCtrlReg;
-
-/**
- * @ingroup IxFeatureCtrlAPI 
- * 
- * @typedef IxFeatureCtrlProductId
- *
- * @brief Product ID of Silicon that contains Silicon Stepping and 
- *        Maximum XScale Core Frequency information.  
- */
-typedef UINT32 IxFeatureCtrlProductId;
-
-/*
- * Prototypes for interface functions
- */
-
-/**
- * @ingroup IxFeatureCtrlAPI 
- *
- * @fn IxFeatureCtrlReg ixFeatureCtrlRead (void)
- * 
- * @brief This function reads out the CURRENT value of Feature Control Register.
- *        The current value may not be the same as that of the hardware component 
- *        availability.    
- * 
- * The bit location of each hardware component is defined above. 
- * A value of '1' in bit means the hardware component is not available.  A value of '0'   
- * means the hardware component is available.
- *
- * @return 
- *      - IxFeatureCtrlReg - the current value of IXP400 Feature Control Register
- */ 
-PUBLIC IxFeatureCtrlReg
-ixFeatureCtrlRead (void);
-
-/**
- * @ingroup IxFeatureCtrlAPI
- *
- * @fn IxFeatureDeviceId ixFeatureCtrlDeviceRead (void)
- *
- * @brief This function gets the type of device that the software is currently running
- *        on
- *
- * This function reads the feature Ctrl register specifically to obtain the device id.
- * The definitions of the avilable IDs are as above.
- *
- * @return
- *      - IxFeatureCtrlDeviceId - the type of device currently running
- */
-IxFeatureCtrlDeviceId
-ixFeatureCtrlDeviceRead (void);
-
-/**
- * @ingroup IxFeatureCtrlAPI
- *
- * @fn IxFeatureCtrlBuildDevice ixFeatureCtrlSoftwareBuildGet (void)
- *
- * @brief This function refers to  the value set by the compiler flag to determine
- *        the type of device the software is built for.
- *
- * The function reads the compiler flag to determine the device the software is
- * built for. When the user executes build in the command line, 
- * a compile time flag (__ixp42X/__ixp46X is set. This API reads this 
- * flag and returns the software build type to the calling client.
- *
- * @return
- *      - IxFeatureCtrlBuildDevice - the type of device software is built for.
- */
-IxFeatureCtrlBuildDevice
-ixFeatureCtrlSoftwareBuildGet (void);
-
-/**
- * @ingroup IxFeatureCtrlAPI 
- *
- * @fn IxFeatureCtrlReg ixFeatureCtrlHwCapabilityRead (void)
- * 
- * @brief This function reads out the hardware capability of a silicon type as defined in 
- * feature control register.This value is different from that returned by 
- * ixFeatureCtrlRead() because this function returns the actual hardware component
- * availability.     
- *
- * The bit location of each hardware component is defined above. 
- * A value of '1' in bit means the hardware component is not available.  A value of '0'   
- * means the hardware component is available.
- *
- * @return 
- *      - IxFeatureCtrlReg - the hardware capability of IXP400. 
- *
- * @warning
- *      - This function must not be called when IXP400 is running as the result
- *        is undefined.    
- */ 
-PUBLIC IxFeatureCtrlReg
-ixFeatureCtrlHwCapabilityRead (void);
-
-/**
- * @ingroup IxFeatureCtrlAPI 
- *
- * @fn void ixFeatureCtrlWrite (IxFeatureCtrlReg expUnitReg)
- * 
- * @brief This function write the value stored in IxFeatureCtrlReg expUnitReg  
- *        to the Feature Control Register. 
- * 
- * The bit location of each hardware component is defined above.
- * The write is only effective on available hardware components. Writing '1' in a  
- * bit will software disable the respective hardware component. A '0' will mean that  
- * the hardware component will remain to be operable. 
- *
- * @param expUnitReg @ref IxFeatureCtrlReg [in] - The value to be written to feature control 
- *                                          register.
- *
- * @return none
- *
- */ 
-PUBLIC void
-ixFeatureCtrlWrite (IxFeatureCtrlReg expUnitReg);
-
-/**
- * @ingroup IxFeatureCtrlAPI 
- *
- * @fn IX_STATUS ixFeatureCtrlComponentCheck (IxFeatureCtrlComponentType componentType)
- * 
- * @brief This function will check the availability of hardware component specified
- *        as componentType value. 
- *
- *        Usage Example:<br> 
- *         -  if(IX_FEATURE_CTRL_COMPONENT_DISABLED != 
- *              ixFeatureCtrlComponentCheck(IX_FEATURECTRL_ETH0)) <br>
- *         -  if(IX_FEATURE_CTRL_COMPONENT_ENABLED == 
- *              ixFeatureCtrlComponentCheck(IX_FEATURECTRL_PCI)) <br>
- *
- * This function is typically called during component initialization time. 
- *
- * @param componentType @ref IxFeatureCtrlComponentType [in] - the type of a component as
- *        defined above as IX_FEATURECTRL_XXX (Exp: IX_FEATURECTRL_PCI, IX_FEATURECTRL_ETH0)           
-
- *        
- * @return 
- *      - IX_FEATURE_CTRL_COMPONENT_ENABLED if component is available 
- *      - IX_FEATURE_CTRL_COMPONENT_DISABLED if component is unavailable            
- */ 
-PUBLIC IX_STATUS
-ixFeatureCtrlComponentCheck (IxFeatureCtrlComponentType componentType);
-
-/**
- * @ingroup IxFeatureCtrlAPI 
- * 
- * @fn IxFeatureCtrlProductId ixFeatureCtrlProductIdRead (void)
- * 
- * @brief This function will return IXP400 product ID i.e. CP15,
- *        Register 0.
- *                                                
- * @return 
- *      - IxFeatureCtrlProductId - the value of product ID.
- *
- */ 
-PUBLIC IxFeatureCtrlProductId
-ixFeatureCtrlProductIdRead (void) ;
-
-/**
- * @ingroup IxFeatureCtrlAPI 
- *
- * @fn IX_STATUS ixFeatureCtrlSwConfigurationCheck (IxFeatureCtrlSwConfig swConfigType)
- * 
- * @brief This function checks whether the specified software configuration is
- *        enabled or disabled. 
- *
- *        Usage Example:<br> 
- *        - if(IX_FEATURE_CTRL_SWCONFIG_DISABLED != 
- *            ixFeatureCtrlSwConfigurationCheck(IX_FEATURECTRL_ETH_LEARNING)) <br>
- *        - if(IX_FEATURE_CTRL_SWCONFIG_ENABLED == 
- *            ixFeatureCtrlSwConfigurationCheck(IX_FEATURECTRL_ETH_LEARNING)) <br>
- *
- * This function is typically called during access component initialization time. 
- *
- * @param swConfigType @ref IxFeatureCtrlSwConfig [in] - the type of a software configuration
- *        defined in IxFeatureCtrlSwConfig enumeration.          
- *        
- * @return 
- *      - IX_FEATURE_CTRL_SWCONFIG_ENABLED if software configuration is enabled. 
- *      - IX_FEATURE_CTRL_SWCONFIG_DISABLED if software configuration is disabled.            
- */ 
-PUBLIC IX_STATUS
-ixFeatureCtrlSwConfigurationCheck (IxFeatureCtrlSwConfig swConfigType);
-
-/**
- * @ingroup IxFeatureCtrlAPI 
- *
- * @fn void ixFeatureCtrlSwConfigurationWrite (IxFeatureCtrlSwConfig swConfigType, BOOL enabled)
- * 
- * @brief This function enable/disable the specified software configuration.  
- *
- *        Usage Example:<br> 
- *        - ixFeatureCtrlSwConfigurationWrite(IX_FEATURECTRL_ETH_LEARNING, true) is used
- *          to enable Ethernet Learning Feature <br>
- *        - ixFeatureCtrlSwConfigurationWrite(IX_FEATURECTRL_ETH_LEARNING, false) is used
- *          to disable Ethernet Learning Feature <br> 
- *
- * @param swConfigType IxFeatureCtrlSwConfig [in] - the type of a software configuration
- *        defined in IxFeatureCtrlSwConfig enumeration. 
- * @param enabled BOOL [in] - To enable(true) / disable (false) the specified software
- *                           configuration.            
- *
- * @return none
- *          
- */ 
-PUBLIC void
-ixFeatureCtrlSwConfigurationWrite (IxFeatureCtrlSwConfig swConfigType, BOOL enabled);
-
-/**
- * @ingroup IxFeatureCtrlAPI 
- *
- * @fn void ixFeatureCtrlIxp400SwVersionShow (void)
- * 
- * @brief This function shows the current software release information for IXP400 
- *          
- * @return none
- *          
- */ 
-PUBLIC void
-ixFeatureCtrlIxp400SwVersionShow (void);
-
-#endif /* IXFEATURECTRL_H */
-
-/**
- * @} defgroup IxFeatureCtrlAPI
- */
diff --git a/drivers/net/npe/include/IxHssAcc.h b/drivers/net/npe/include/IxHssAcc.h
deleted file mode 100644
index da71c42023..0000000000
--- a/drivers/net/npe/include/IxHssAcc.h
+++ /dev/null
@@ -1,1292 +0,0 @@
-/**
- * @file IxHssAcc.h
- * 
- * @date 07-DEC-2001
- *
- * @brief This file contains the public API of the IXP400 HSS Access
- * component
- *
- * 
- * @par
- * IXP400 SW Release version 2.0
- * 
- * -- Copyright Notice --
- * 
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- * 
- * @par
- * SPDX-License-Identifier:	BSD-3-Clause
- * @par
- * -- End of Copyright Notice --
-*/
- 
-/* ------------------------------------------------------
-   Doxygen group definitions
-   ------------------------------------------------------ */
-/**
- * @defgroup IxHssAccAPI IXP400 HSS Access (IxHssAcc) API
- *
- * @brief The public API for the IXP400 HssAccess component
- *
- * IxHssAcc is the access layer to the HSS packetised and channelised
- * services
- * 
- * <b> Design Notes </b><br>
- * <UL>
- * <LI>When a packet-pipe is configured for 56Kbps RAW mode, byte alignment of 
- *     the transmitted data is not preserved. All raw data that is transmitted 
- *     will be received in proper order by the receiver, but the first bit of 
- *     the packet may be seen at any offset within a byte; all subsequent bytes 
- *     will have the same offset for the duration of the packet. The same offset 
- *     also applies to all subsequent packets received on the packet-pipe too. 
- *     (Similar results will occur for data received from remote end.) While 
- *     this behavior will also occur for 56Kbps HDLC mode, the HDLC 
- *     encoding/decoding will preserve the original byte alignment at the 
- *     receiver end.
- * </UL>
- *
- * <b> 56Kbps Packetised Service Bandwidth Limitation </b><br>
- * <UL>
- * <LI>IxHssAcc supports 56Kbps packetised service at a maximum aggregate rate
- *     for all HSS ports/HDLC channels of 12.288Mbps[1] in each direction, i.e.
- *     it supports 56Kbps packetised service on up to 8 T1 trunks. It does
- *     not support 56Kbps packetised service on 8 E1 trunks (i.e. 4 trunks per 
- *     HSS port) unless those trunks are running 'fractional E1' with maximum 
- *     aggregate rate of 12.288 Mbps in each direction.<br>
- *     [1] 12.288Mbps = 1.536Mbp * 8 T1
- * </UL>
- * @{ */
-
-#ifndef IXHSSACC_H
-#define IXHSSACC_H
-
-#include "IxOsal.h"
-
-/*
- * #defines for function return types, etc.
- */
-
-/**
- * @def IX_HSSACC_TSLOTS_PER_HSS_PORT
- *
- * @brief The max number of TDM timeslots supported per HSS port - 4E1's =
- *  32x4 = 128 
- */
-#define IX_HSSACC_TSLOTS_PER_HSS_PORT 128
-
-/* -----------------------------------------------------------
-   The following are HssAccess return values returned through 
-   service interfaces. The globally defined IX_SUCCESS (0) and
-   IX_FAIL (1) in IxOsalTypes.h are also used.
-   ----------------------------------------------------------- */
-/**
- * @def IX_HSSACC_PARAM_ERR
- *
- * @brief HssAccess function return value for a parameter error
- */
-#define IX_HSSACC_PARAM_ERR 2
-
-/**
- * @def IX_HSSACC_RESOURCE_ERR
- *
- * @brief HssAccess function return value for a resource error
- */
-#define IX_HSSACC_RESOURCE_ERR 3
-
-/**
- * @def IX_HSSACC_PKT_DISCONNECTING
- *
- * @brief Indicates that a disconnect call is progressing and will 
- * disconnect soon
- */
-#define IX_HSSACC_PKT_DISCONNECTING 4
-
-/**
- * @def IX_HSSACC_Q_WRITE_OVERFLOW
- *
- * @brief Indicates that an attempt to Tx or to replenish an 
- * RxFree Q failed due to Q overflow.  
- */
-#define IX_HSSACC_Q_WRITE_OVERFLOW 5
-
-/* -------------------------------------------------------------------
-   The following errors are HSS/NPE errors returned on error retrieval
-   ------------------------------------------------------------------- */
-/**
- * @def IX_HSSACC_NO_ERROR
- *
- * @brief HSS port no error present
- */
-#define IX_HSSACC_NO_ERROR 0
-
-/**
- * @def IX_HSSACC_TX_FRM_SYNC_ERR
- *
- * @brief HSS port TX Frame Sync error
- */
-#define IX_HSSACC_TX_FRM_SYNC_ERR 1
-
-/**
- * @def IX_HSSACC_TX_OVER_RUN_ERR
- *
- * @brief HSS port TX over-run error
- */
-#define IX_HSSACC_TX_OVER_RUN_ERR 2
-
-/**
- * @def IX_HSSACC_CHANNELISED_SW_TX_ERR
- *
- * @brief NPE software error in channelised TX
- */
-#define IX_HSSACC_CHANNELISED_SW_TX_ERR 3
-
-/**
- * @def IX_HSSACC_PACKETISED_SW_TX_ERR
- *
- * @brief NPE software error in packetised TX
- */
-#define IX_HSSACC_PACKETISED_SW_TX_ERR 4
-
-/**
- * @def IX_HSSACC_RX_FRM_SYNC_ERR
- *
- * @brief HSS port RX Frame Sync error
- */
-#define IX_HSSACC_RX_FRM_SYNC_ERR 5
-
-/**
- * @def IX_HSSACC_RX_OVER_RUN_ERR
- *
- * @brief HSS port RX over-run error
- */
-#define IX_HSSACC_RX_OVER_RUN_ERR 6
-
-/**
- * @def IX_HSSACC_CHANNELISED_SW_RX_ERR
- *
- * @brief NPE software error in channelised RX
- */
-#define IX_HSSACC_CHANNELISED_SW_RX_ERR 7
-
-/**
- * @def IX_HSSACC_PACKETISED_SW_RX_ERR
- *
- * @brief NPE software error in packetised TX
- */
-#define IX_HSSACC_PACKETISED_SW_RX_ERR 8
-
-/* -----------------------------------
-   Packetised service specific defines
-   ----------------------------------- */
-
-/**
- * @def IX_HSSACC_PKT_MIN_RX_MBUF_SIZE
- *
- * @brief Minimum size of the Rx mbuf in bytes which the client must supply 
- * to the component. 
- */
-#define IX_HSSACC_PKT_MIN_RX_MBUF_SIZE 64
-
-/* --------------------------------------------------------------------
-   Enumerated Types - these enumerated values may be used in setting up
-   the contents of hardware registers
-   -------------------------------------------------------------------- */
-/**
- * @enum IxHssAccHssPort
- * @brief The HSS port ID - There are two identical ports (0-1). 
- * 
- */
-typedef enum
-{
-    IX_HSSACC_HSS_PORT_0,   /**< HSS Port 0 */
-    IX_HSSACC_HSS_PORT_1,   /**< HSS Port 1 */
-    IX_HSSACC_HSS_PORT_MAX  /**< Delimiter for error checks */
-} IxHssAccHssPort;
-
-/**
- * @enum IxHssAccHdlcPort
- * @brief The HDLC port ID - There are four identical HDLC ports (0-3) per 
- * HSS port and they correspond to the 4 E1/T1 trunks.
- * 
- */
-typedef enum
-{
-   IX_HSSACC_HDLC_PORT_0,   /**< HDLC Port 0 */
-   IX_HSSACC_HDLC_PORT_1,   /**< HDLC Port 1 */
-   IX_HSSACC_HDLC_PORT_2,   /**< HDLC Port 2 */
-   IX_HSSACC_HDLC_PORT_3,   /**< HDLC Port 3 */
-   IX_HSSACC_HDLC_PORT_MAX  /**< Delimiter for error checks */
-} IxHssAccHdlcPort;
-
-/**
- * @enum IxHssAccTdmSlotUsage
- * @brief The HSS TDM stream timeslot assignment types
- *
- */
-typedef enum
-{
-    IX_HSSACC_TDMMAP_UNASSIGNED,    /**< Unassigned */
-    IX_HSSACC_TDMMAP_HDLC,          /**< HDLC - packetised */
-    IX_HSSACC_TDMMAP_VOICE56K,      /**< Voice56K - channelised */
-    IX_HSSACC_TDMMAP_VOICE64K,      /**< Voice64K - channelised */
-    IX_HSSACC_TDMMAP_MAX            /**< Delimiter for error checks */
-} IxHssAccTdmSlotUsage;
-
-/**
- * @enum IxHssAccFrmSyncType
- * @brief The HSS frame sync pulse type
- *
- */
-typedef enum
-{
-    IX_HSSACC_FRM_SYNC_ACTIVE_LOW,   /**< Frame sync is sampled low */
-    IX_HSSACC_FRM_SYNC_ACTIVE_HIGH,  /**< sampled high */
-    IX_HSSACC_FRM_SYNC_FALLINGEDGE,  /**< sampled on a falling edge */
-    IX_HSSACC_FRM_SYNC_RISINGEDGE,   /**< sampled on a rising edge */
-    IX_HSSACC_FRM_SYNC_TYPE_MAX      /**< Delimiter for error checks */
-} IxHssAccFrmSyncType;
-
-/**
- * @enum IxHssAccFrmSyncEnable
- * @brief The IxHssAccFrmSyncEnable determines how the frame sync pulse is
- * used
- * */
-typedef enum
-{
-    IX_HSSACC_FRM_SYNC_INPUT,          /**< Frame sync is sampled as an input */
-    IX_HSSACC_FRM_SYNC_INVALID_VALUE,  /**< 1 is not used */
-    IX_HSSACC_FRM_SYNC_OUTPUT_FALLING, /**< Frame sync is an output generated 
-					  off a falling clock edge */
-    IX_HSSACC_FRM_SYNC_OUTPUT_RISING,  /**< Frame sync is an output generated 
-					  off a rising clock edge */
-    IX_HSSACC_FRM_SYNC_ENABLE_MAX      /**< Delimiter for error checks */
-} IxHssAccFrmSyncEnable;
-
-/**
- * @enum IxHssAccClkEdge
- * @brief IxHssAccClkEdge is used to determine the clk edge to use for 
- * framing and data
- *
- */
-typedef enum
-{
-    IX_HSSACC_CLK_EDGE_FALLING,  /**< Clock sampled off a falling edge */
-    IX_HSSACC_CLK_EDGE_RISING,   /**< Clock sampled off a rising edge */
-    IX_HSSACC_CLK_EDGE_MAX       /**< Delimiter for error checks */
-} IxHssAccClkEdge;
-
-/**
- * @enum IxHssAccClkDir
- * @brief The HSS clock direction
- *
- */
-typedef enum
-{
-    IX_HSSACC_SYNC_CLK_DIR_INPUT,    /**< Clock is an input */
-    IX_HSSACC_SYNC_CLK_DIR_OUTPUT,   /**< Clock is an output */
-    IX_HSSACC_SYNC_CLK_DIR_MAX       /**< Delimiter for error checks */
-} IxHssAccClkDir;
-
-/**
- * @enum IxHssAccFrmPulseUsage
- * @brief The HSS frame pulse usage
- *
- */
-typedef enum
-{
-    IX_HSSACC_FRM_PULSE_ENABLED,     /**< Generate/Receive frame pulses */
-    IX_HSSACC_FRM_PULSE_DISABLED,    /**< Disregard frame pulses */
-    IX_HSSACC_FRM_PULSE_MAX          /**< Delimiter for error checks */
-} IxHssAccFrmPulseUsage;
-
-/**
- * @enum IxHssAccDataRate
- * @brief The HSS Data rate in relation to the clock
- *
- */
-typedef enum
-{
-    IX_HSSACC_CLK_RATE,      /**< Data rate is at the configured clk speed */
-    IX_HSSACC_HALF_CLK_RATE, /**< Data rate is half the configured clk speed */
-    IX_HSSACC_DATA_RATE_MAX  /**< Delimiter for error checks */
-} IxHssAccDataRate;
-
-/**
- * @enum IxHssAccDataPolarity
- * @brief The HSS data polarity type
- *
- */
-typedef enum
-{
-    IX_HSSACC_DATA_POLARITY_SAME,   /**< Don't invert data between NPE and 
-				       HSS FIFOs */
-    IX_HSSACC_DATA_POLARITY_INVERT, /**< Invert data between NPE and HSS 
-				       FIFOs */
-    IX_HSSACC_DATA_POLARITY_MAX     /**< Delimiter for error checks */
-} IxHssAccDataPolarity;
-
-/**
- * @enum IxHssAccBitEndian
- * @brief HSS Data endianness
- *
- */
-typedef enum
-{
-    IX_HSSACC_LSB_ENDIAN,    /**< TX/RX Least Significant Bit first */
-    IX_HSSACC_MSB_ENDIAN,    /**< TX/RX Most Significant Bit first */
-    IX_HSSACC_ENDIAN_MAX     /**< Delimiter for the purposes of error checks */
-} IxHssAccBitEndian;
-
-
-/**
- * @enum IxHssAccDrainMode
- * @brief Tx pin open drain mode
- *
- */
-typedef enum
-{
-    IX_HSSACC_TX_PINS_NORMAL,       /**< Normal mode */
-    IX_HSSACC_TX_PINS_OPEN_DRAIN,   /**< Open Drain mode */
-    IX_HSSACC_TX_PINS_MAX           /**< Delimiter for error checks */
-} IxHssAccDrainMode;
-
-/**
- * @enum IxHssAccSOFType
- * @brief HSS start of frame types
- *
- */
-typedef enum
-{
-    IX_HSSACC_SOF_FBIT,  /**< Framing bit transmitted and expected on rx */
-    IX_HSSACC_SOF_DATA,  /**< Framing bit not transmitted nor expected on rx */
-    IX_HSSACC_SOF_MAX    /**< Delimiter for error checks */
-} IxHssAccSOFType;
-
-/**
- * @enum IxHssAccDataEnable
- * @brief IxHssAccDataEnable is used to determine whether or not to drive 
- * the data pins
- *
- */
-typedef enum
-{
-    IX_HSSACC_DE_TRI_STATE,   /**< TRI-State the data pins */
-    IX_HSSACC_DE_DATA,        /**< Push data out the data pins */
-    IX_HSSACC_DE_MAX          /**< Delimiter for error checks */
-} IxHssAccDataEnable;
-
-/**
- * @enum IxHssAccTxSigType
- * @brief IxHssAccTxSigType is used to determine how to drive the data pins
- *
- */
-typedef enum
-{
-    IX_HSSACC_TXSIG_LOW,        /**< Drive the data pins low */
-    IX_HSSACC_TXSIG_HIGH,       /**< Drive the data pins high */
-    IX_HSSACC_TXSIG_HIGH_IMP,   /**< Drive the data pins with high impedance */
-    IX_HSSACC_TXSIG_MAX         /**< Delimiter for error checks */
-} IxHssAccTxSigType;
-
-/**
- * @enum IxHssAccFbType
- * @brief IxHssAccFbType determines how to drive the Fbit
- *
- * @warning This will only be used for T1 @ 1.544MHz
- *
- */
-typedef enum
-{
-    IX_HSSACC_FB_FIFO,        /**< Fbit is dictated in FIFO */
-    IX_HSSACC_FB_HIGH_IMP,    /**< Fbit is high impedance */
-    IX_HSSACC_FB_MAX          /**< Delimiter for error checks */
-} IxHssAccFbType;
-
-/**
- * @enum IxHssAcc56kEndianness
- * @brief 56k data endianness when using the 56k type
- *
- */
-typedef enum
-{
-    IX_HSSACC_56KE_BIT_7_UNUSED,  /**< High bit is unused */
-    IX_HSSACC_56KE_BIT_0_UNUSED,  /**< Low bit is unused */
-    IX_HSSACC_56KE_MAX            /**< Delimiter for error checks */
-} IxHssAcc56kEndianness;
-
-/**
- * @enum IxHssAcc56kSel
- * @brief 56k data transmission type when using the 56k type
- *
- */
-typedef enum
-{
-    IX_HSSACC_56KS_32_8_DATA,  /**< 32/8 bit data */
-    IX_HSSACC_56KS_56K_DATA,   /**< 56K data */
-    IX_HSSACC_56KS_MAX         /**< Delimiter for error checks */
-} IxHssAcc56kSel;
-
-
-/**
- * @enum IxHssAccClkSpeed
- * @brief IxHssAccClkSpeed represents the HSS clock speeds available
- *
- */
-typedef enum
-{
-    IX_HSSACC_CLK_SPEED_512KHZ,     /**< 512KHz */
-    IX_HSSACC_CLK_SPEED_1536KHZ,    /**< 1.536MHz */
-    IX_HSSACC_CLK_SPEED_1544KHZ,    /**< 1.544MHz */
-    IX_HSSACC_CLK_SPEED_2048KHZ,    /**< 2.048MHz */
-    IX_HSSACC_CLK_SPEED_4096KHZ,    /**< 4.096MHz */
-    IX_HSSACC_CLK_SPEED_8192KHZ,    /**< 8.192MHz */
-    IX_HSSACC_CLK_SPEED_MAX      /**< Delimiter for error checking */
-} IxHssAccClkSpeed;
-
-/**
- * @enum IxHssAccPktStatus
- * @brief Indicates the status of packets passed to the client
- *
- */
-typedef enum
-{
-    IX_HSSACC_PKT_OK,              /**< Error free.*/
-    IX_HSSACC_STOP_SHUTDOWN_ERROR, /**< Errored due to stop or shutdown 
-				      occurrance.*/
-    IX_HSSACC_HDLC_ALN_ERROR,      /**< HDLC alignment error */
-    IX_HSSACC_HDLC_FCS_ERROR,       /**< HDLC Frame Check Sum error.*/
-    IX_HSSACC_RXFREE_Q_EMPTY_ERROR,       /**< RxFree Q became empty 
-					     while receiving this packet.*/
-    IX_HSSACC_HDLC_MAX_FRAME_SIZE_EXCEEDED,      /**< HDLC frame size 
-						   received is greater than
-						   max specified at connect.*/
-    IX_HSSACC_HDLC_ABORT_ERROR,   /**< HDLC frame received is invalid due to an 
-				   abort sequence received.*/
-    IX_HSSACC_DISCONNECT_IN_PROGRESS     /**< Packet returned
-					    because a disconnect is in progress */
-} IxHssAccPktStatus;
-
-
-/**
- * @enum IxHssAccPktCrcType
- * @brief HDLC CRC type
- *
- */
-typedef enum
-{
-    IX_HSSACC_PKT_16_BIT_CRC = 16,  /**< 16 bit CRC is being used */
-    IX_HSSACC_PKT_32_BIT_CRC = 32   /**< 32 bit CRC is being used */
-} IxHssAccPktCrcType;
-
-/**
- * @enum IxHssAccPktHdlcIdleType
- * @brief HDLC idle transmission type
- *
- */
-typedef enum
-{
-    IX_HSSACC_HDLC_IDLE_ONES,    /**< idle tx/rx will be a succession of ones */
-    IX_HSSACC_HDLC_IDLE_FLAGS    /**< idle tx/rx will be repeated flags */
-} IxHssAccPktHdlcIdleType;
-
-/**
- * @brief Structure containing HSS port configuration parameters
- *
- * Note: All of these are used for TX. Only some are specific to RX.
- *
- */
-typedef struct
-{
-    IxHssAccFrmSyncType frmSyncType;     /**< frame sync pulse type (tx/rx) */
-    IxHssAccFrmSyncEnable frmSyncIO;     /**< how the frame sync pulse is 
-					    used (tx/rx) */
-    IxHssAccClkEdge frmSyncClkEdge;      /**< frame sync clock edge type 
-					    (tx/rx) */
-    IxHssAccClkEdge dataClkEdge;         /**< data clock edge type (tx/rx) */
-    IxHssAccClkDir clkDirection;         /**< clock direction (tx/rx) */
-    IxHssAccFrmPulseUsage frmPulseUsage; /**< whether to use the frame sync 
-					    pulse or not (tx/rx) */
-    IxHssAccDataRate dataRate;           /**< data rate in relation to the 
-					    clock (tx/rx) */
-    IxHssAccDataPolarity dataPolarity;   /**< data polarity type (tx/rx) */
-    IxHssAccBitEndian dataEndianness;    /**< data endianness (tx/rx) */
-    IxHssAccDrainMode drainMode;         /**< tx pin open drain mode (tx) */
-    IxHssAccSOFType fBitUsage;           /**< start of frame types (tx/rx) */
-    IxHssAccDataEnable dataEnable;       /**< whether or not to drive the data 
-					    pins (tx) */
-    IxHssAccTxSigType voice56kType;      /**< how to drive the data pins for 
-					    voice56k type (tx) */
-    IxHssAccTxSigType unassignedType;    /**< how to drive the data pins for 
-					    unassigned type (tx) */
-    IxHssAccFbType fBitType;             /**< how to drive the Fbit (tx) */
-    IxHssAcc56kEndianness voice56kEndian;/**< 56k data endianness when using 
-					    the 56k type (tx) */
-    IxHssAcc56kSel voice56kSel;          /**< 56k data transmission type when 
-					    using the 56k type (tx) */
-    unsigned frmOffset;                  /**< frame pulse offset in bits wrt 
-					    the first timeslot (0-1023) (tx/rx) */
-    unsigned maxFrmSize;                 /**< frame size in bits (1-1024) 
-					    (tx/rx) */
-} IxHssAccPortConfig;
-
-/**
- * @brief Structure containing HSS configuration parameters
- *
- */
-typedef struct
-{
-    IxHssAccPortConfig txPortConfig; /**< HSS tx port configuration */
-    IxHssAccPortConfig rxPortConfig; /**< HSS rx port configuration */
-    unsigned numChannelised;         /**< The number of channelised 
-					timeslots (0-32) */
-    unsigned hssPktChannelCount;     /**< The number of packetised 
-					clients (0 - 4) */
-    UINT8 channelisedIdlePattern;    /**< The byte to be transmitted on 
-					channelised service when there 
-					is no client data to tx */
-    BOOL loopback;                   /**< The HSS loopback state */
-    unsigned packetizedIdlePattern;  /**< The data to be transmitted on 
-					packetised service when there is 
-					no client data to tx */
-    IxHssAccClkSpeed clkSpeed;       /**< The HSS clock speed */
-} IxHssAccConfigParams;
-
-/**
- * @brief This structure contains 56Kbps, HDLC-mode configuration parameters
- *
- */
-typedef struct
-{
-    BOOL hdlc56kMode;                    /**< 56kbps(true)/64kbps(false) HDLC */
-    IxHssAcc56kEndianness hdlc56kEndian; /**< 56kbps data endianness 
-					    - ignored if hdlc56kMode is false*/
-    BOOL hdlc56kUnusedBitPolarity0;      /**< The polarity '0'(true)/'1'(false) of the unused
-					   bit while in 56kbps mode
-					   - ignored if hdlc56kMode is false*/
-} IxHssAccHdlcMode;
-
-/**
- * @brief This structure contains information required by the NPE to 
- * configure the HDLC co-processor
- *
- */
-typedef struct
-{
-    IxHssAccPktHdlcIdleType hdlcIdleType;   /**< What to transmit when a HDLC port is idle */
-    IxHssAccBitEndian dataEndian;           /**< The HDLC data endianness */
-    IxHssAccPktCrcType crcType;             /**< The CRC type to be used for this HDLC port */
-} IxHssAccPktHdlcFraming;
-
-/**
- * @typedef UINT32 IxHssAccPktUserId
- *
- * @brief The client supplied value which will be supplied as a parameter
- * with a given callback.
- *
- * This value will be passed into the ixHssAccPktPortConnect function once each
- * with given callbacks.  This value will then be passed back to the client
- * as one of the parameters to each of these callbacks, 
- * when these callbacks are called.
- */
-typedef UINT32 IxHssAccPktUserId;
-
-
-/**
- * @typedef IxHssAccLastErrorCallback
- * @brief Prototype of the clients function to accept notification of the 
- * last error
- *
- * This function is registered through the config. The client will initiate
- * the last error retrieval. The HssAccess component will send a message to
- * the NPE through the NPE Message Handler. When a response to the read is
- * received, the NPE Message Handler will callback the HssAccess component
- * which will execute this function in the same IxNpeMh context. The client
- * will be passed the last error and the related service port (packetised
- * 0-3, channelised 0)
- *
- * @param lastHssError unsigned [in] - The last Hss error registered that
- *                                      has been registered.
- * @param servicePort unsigned [in] - This is the service port number.  
- *                                     (packetised 0-3, channelised 0) 
- * 
- * @return void
- */
-typedef void (*IxHssAccLastErrorCallback) (unsigned lastHssError, 
-					   unsigned servicePort);
-
-/**
- * @typedef IxHssAccPktRxCallback
- * @brief  Prototype of the clients function to accept notification of 
- * packetised rx
- *
- * This function is registered through the ixHssAccPktPortConnect. hssPktAcc will pass
- * received data in the form of mbufs to the client.  The mbuf passed back
- * to the client could contain a chain of buffers, depending on the packet
- * size received. 
- * 
- * @param *buffer @ref IX_OSAL_MBUF [in] - This is the mbuf which contains the 
- * payload received.
- * @param numHssErrs unsigned [in] - This is the number of hssErrors 
- * the Npe has received
- * @param pktStatus @ref IxHssAccPktStatus [in] - This is the status of the 
- * mbuf that has been received.
- * @param rxUserId @ref IxHssAccPktUserId [in] - This is the client supplied value 
- * passed in at ixHssAccPktPortConnect time which is now returned to the client.			       
- * 
- * @return void
- */
-typedef void (*IxHssAccPktRxCallback) (IX_OSAL_MBUF *buffer, 
-				       unsigned numHssErrs, 
-				       IxHssAccPktStatus pktStatus, 
-				       IxHssAccPktUserId rxUserId);
-
-/**
- * @typedef IxHssAccPktRxFreeLowCallback
- * @brief Prototype of the clients function to accept notification of 
- * requirement of more Rx Free buffers
- *
- * The client can choose to register a callback of this type when
- * calling a connecting. This function is registered through the ixHssAccPktPortConnect. 
- * If defined, the access layer will provide the trigger for
- * this callback. The callback will be responsible for supplying mbufs to
- * the access layer for use on the receive path from the HSS using
- * ixHssPktAccFreeBufReplenish. 
- *
- * @return void
- */
-typedef void (*IxHssAccPktRxFreeLowCallback) (IxHssAccPktUserId rxFreeLowUserId);
-
-/**
- * @typedef IxHssAccPktTxDoneCallback
- * @brief  Prototype of the clients function to accept notification of 
- * completion with Tx buffers
- *
- * This function is registered through the ixHssAccPktPortConnect.  It enables
- * the hssPktAcc to pass buffers back to the client
- * when transmission is complete.
- *
- * @param *buffer @ref IX_OSAL_MBUF [in] - This is the mbuf which contained 
- * the payload that was for Tx.
- * @param numHssErrs unsigned [in] - This is the number of hssErrors 
- * the Npe has received
- * @param pktStatus @ref IxHssAccPktStatus [in] - This is the status of the 
- * mbuf that has been transmitted.
- * @param txDoneUserId @ref IxHssAccPktUserId [in] - This is the client supplied value 
- * passed in at ixHssAccPktPortConnect time which is now returned to the client.	 
- *
- * @return void
- */
-typedef void (*IxHssAccPktTxDoneCallback) (IX_OSAL_MBUF *buffer, 
-					   unsigned numHssErrs,
-					   IxHssAccPktStatus pktStatus, 
-					   IxHssAccPktUserId txDoneUserId);
-
-/**
- * @typedef IxHssAccChanRxCallback
- * @brief Prototype of the clients function to accept notification of 
- * channelised rx
- *
- * This callback, if defined by the client in the connect, will get called
- * in the context of an IRQ. The IRQ will be triggered when the hssSyncQMQ
- * is not empty. The queued entry will be dequeued and this function will
- * be executed.
- *
- * @param hssPortId @ref IxHssAccHssPort - The HSS port Id. There are two
- * identical ports (0-1).
- * @param txOffset unsigned [in] - an offset indicating from where within
- * the txPtrList the NPE is currently transmitting from.
- * @param rxOffset unsigned [in] - an offset indicating where within the
- * receive buffers the NPE has just written the received data to.
- * @param numHssErrs unsigned [in] - This is the number of hssErrors 
- * the Npe has received
- *
- * @return void
- */
-typedef void (*IxHssAccChanRxCallback) (IxHssAccHssPort hssPortId,
-					unsigned rxOffset, 
-					unsigned txOffset, 
-					unsigned numHssErrs);
-
-/*
- * Prototypes for interface functions.
- */
-
-/**
- *
- * @ingroup IxHssAccAPI
- *
- * @fn IX_STATUS ixHssAccPortInit (IxHssAccHssPort hssPortId, 
-               IxHssAccConfigParams *configParams, 
-               IxHssAccTdmSlotUsage *tdmMap, 
-               IxHssAccLastErrorCallback lastHssErrorCallback)
- *
- * @brief Initialise a HSS port. No channelised or packetised connections
- * should exist in the HssAccess layer while this interface is being called.
- *
- * @param hssPortId @ref IxHssAccHssPort [in] - The HSS port Id. There are two
- * identical ports (0-1). 
- * @param *configParams @ref IxHssAccConfigParams [in] - A pointer to the HSS 
- * configuration structure
- * @param *tdmMap @ref IxHssAccTdmSlotUsage [in] - A pointer to an array of size
- * IX_HSSACC_TSLOTS_PER_HSS_PORT, defining the slot usage over the HSS port
- * @param lastHssErrorCallback @ref IxHssAccLastErrorCallback [in] - Client 
- * callback to report last error
- *
- * @return 
- *         - IX_SUCCESS The function executed successfully
- *         - IX_FAIL The function did not execute successfully
- *         - IX_HSSACC_PARAM_ERR The function did not execute successfully due to a
- *                          parameter error
- */
-PUBLIC IX_STATUS 
-ixHssAccPortInit (IxHssAccHssPort hssPortId, 
-		  IxHssAccConfigParams *configParams, 
-		  IxHssAccTdmSlotUsage *tdmMap, 
-		  IxHssAccLastErrorCallback lastHssErrorCallback);
-
-/**
- *
- * @ingroup IxHssAccAPI
- *
- * @fn IX_STATUS ixHssAccLastErrorRetrievalInitiate (
-               IxHssAccHssPort hssPortId)
- *
- * @brief Initiate the retrieval of the last HSS error. The HSS port
- * should be configured before attempting to call this interface.
- *
- * @param hssPortId @ref IxHssAccHssPort [in] - the HSS port ID
- *
- * @return 
- *         - IX_SUCCESS The function executed successfully
- *         - IX_FAIL The function did not execute successfully
- *         - IX_HSSACC_PARAM_ERR The function did not execute successfully due to a
- *                          parameter error
- */
-PUBLIC IX_STATUS 
-ixHssAccLastErrorRetrievalInitiate (IxHssAccHssPort hssPortId);
-
-
-/**
- *
- * @ingroup IxHssAccAPI
- *
- * @fn IX_STATUS ixHssAccInit ()
- *
- * @brief This function is responsible for initialising resources for use
- * by the packetised and channelised clients. It should be called after 
- * HSS NPE image has been downloaded into NPE-A and before any other
- * HssAccess interface is called. 
- * No other HssAccPacketised interface should be called while this interface
- * is being processed.
- *
- * @return 
- *         - IX_SUCCESS The function executed successfully
- *         - IX_FAIL The function did not execute successfully
- *         - IX_HSSACC_RESOURCE_ERR The function did not execute successfully due
- *                          to a resource error 
- */
-PUBLIC IX_STATUS 
-ixHssAccInit (void);
-
-
-/**
- *
- * @ingroup IxHssAccAPI
- *
- * @fn ixHssAccPktPortConnect (IxHssAccHssPort hssPortId, 
-			IxHssAccHdlcPort hdlcPortId, 
-			BOOL hdlcFraming, 
-			IxHssAccHdlcMode hdlcMode,
-			BOOL hdlcBitInvert,
-			unsigned blockSizeInWords,
-			UINT32 rawIdleBlockPattern,
-			IxHssAccPktHdlcFraming hdlcTxFraming, 
-			IxHssAccPktHdlcFraming hdlcRxFraming, 
-			unsigned frmFlagStart, 
-			IxHssAccPktRxCallback rxCallback,
-			IxHssAccPktUserId rxUserId, 
-			IxHssAccPktRxFreeLowCallback rxFreeLowCallback, 
-			IxHssAccPktUserId rxFreeLowUserId,
-			IxHssAccPktTxDoneCallback txDoneCallback,
-			IxHssAccPktUserId txDoneUserId) 
- *
- * @brief This function is responsible for connecting a client to one of 
- * the 4 available HDLC ports. The HSS port should be configured before 
- * attempting a connect. No other HssAccPacketised interface should be
- * called while this connect is being processed.
- *
- * @param hssPortId @ref IxHssAccHssPort [in] - The HSS port Id. There are two
- * identical ports (0-1). 
- * @param hdlcPortId @ref IxHssAccHdlcPort [in] - This is the number of the HDLC port and 
- * it corresponds to the physical E1/T1 trunk i.e. 0, 1, 2, 3 
- * @param hdlcFraming BOOL [in] - This value determines whether the service 
- * will use HDLC data or the debug, raw data type i.e. no HDLC processing
- * @param hdlcMode @ref IxHssAccHdlcMode [in] - This structure contains 56Kbps, HDLC-mode
- * configuration parameters
- * @param hdlcBitInvert BOOL [in] - This value determines whether bit inversion
- * will occur between HDLC and HSS co-processors i.e. post-HDLC processing for
- * transmit and pre-HDLC processing for receive, for the specified HDLC Termination
- * Point
- * @param blockSizeInWords unsigned [in] -  The max tx/rx block size 
- * @param rawIdleBlockPattern UINT32 [in] -  Tx idle pattern in raw mode 
- * @param hdlcTxFraming @ref IxHssAccPktHdlcFraming [in] - This structure contains 
- * the following information required by the NPE to configure the HDLC 
- * co-processor for TX
- * @param hdlcRxFraming @ref IxHssAccPktHdlcFraming [in] -  This structure contains 
- * the following information required by the NPE to configure the HDLC 
- * co-processor for RX
- * @param frmFlagStart unsigned - Number of flags to precede to 
- * transmitted flags (0-2).
- * @param rxCallback @ref IxHssAccPktRxCallback [in] - Pointer to 
- * the clients packet receive function.
- * @param rxUserId @ref IxHssAccPktUserId [in] - The client supplied rx value
- * to be passed back as an argument to the supplied rxCallback
- * @param rxFreeLowCallback @ref IxHssAccPktRxFreeLowCallback [in] - Pointer to 
- * the clients Rx free buffer request function.  If NULL, assume client will 
- * trigger independently.
- * @param rxFreeLowUserId @ref IxHssAccPktUserId [in] - The client supplied RxFreeLow value
- * to be passed back as an argument to the supplied rxFreeLowCallback
- * @param txDoneCallback @ref IxHssAccPktTxDoneCallback [in] - Pointer to the 
- * clients Tx done callback function
- * @param txDoneUserId @ref IxHssAccPktUserId [in] - The client supplied txDone value
- * to be passed back as an argument to the supplied txDoneCallback
- *
- * @return 
- *         - IX_SUCCESS The function executed successfully
- *         - IX_FAIL The function did not execute successfully
- *         - IX_HSSACC_PARAM_ERR The function did not execute successfully due to a
- *                          parameter error
- *         - IX_HSSACC_RESOURCE_ERR The function did not execute successfully due
- *                          to a resource error
- */
-PUBLIC IX_STATUS 
-ixHssAccPktPortConnect (IxHssAccHssPort hssPortId, 
-			IxHssAccHdlcPort hdlcPortId, 
-			BOOL hdlcFraming, 
-			IxHssAccHdlcMode hdlcMode,
-			BOOL hdlcBitInvert,
-			unsigned blockSizeInWords,
-			UINT32 rawIdleBlockPattern,
-			IxHssAccPktHdlcFraming hdlcTxFraming, 
-			IxHssAccPktHdlcFraming hdlcRxFraming, 
-			unsigned frmFlagStart, 
-			IxHssAccPktRxCallback rxCallback,
-			IxHssAccPktUserId rxUserId, 
-			IxHssAccPktRxFreeLowCallback rxFreeLowCallback, 
-			IxHssAccPktUserId rxFreeLowUserId,
-			IxHssAccPktTxDoneCallback txDoneCallback,
-			IxHssAccPktUserId txDoneUserId);
-
-/**
- *
- * @ingroup IxHssAccAPI
- *
- * @fn IX_STATUS ixHssAccPktPortEnable (IxHssAccHssPort hssPortId, 
-           IxHssAccHdlcPort hdlcPortId)
- *
- * @brief This function is responsible for enabling a packetised service
- * for the specified HSS/HDLC port combination. It enables the RX flow. The
- * client must have already connected to a packetised service and is responsible 
- * for ensuring an adequate amount of RX mbufs have been supplied to the access
- * component before enabling the packetised service. This function must be called
- * on a given port before any call to ixHssAccPktPortTx on the same port. 
- * No other HssAccPacketised interface should be called while this interface is 
- * being processed.
- *
- * @param hssPortId @ref IxHssAccHssPort [in] - The HSS port Id. There are two
- * identical ports (0-1).   
- * @param hdlcPortId @ref IxHssAccHdlcPort [in] - The port id (0,1,2,3) to enable the service
- * on.
- *
- * @return 
- *         - IX_SUCCESS The function executed successfully
- *         - IX_FAIL The function did not execute successfully
- *         - IX_HSSACC_PARAM_ERR The function did not execute successfully due to a
- *                          parameter error
- */
-PUBLIC IX_STATUS 
-ixHssAccPktPortEnable (IxHssAccHssPort hssPortId, 
-		       IxHssAccHdlcPort hdlcPortId);
-
-/**
- * @fn IX_STATUS ixHssAccPktPortDisable (IxHssAccHssPort hssPortId, 
-           IxHssAccHdlcPort hdlcPortId)
- *
- * @brief This function is responsible for disabling a packetised service
- * for the specified HSS/HDLC port combination. It disables the RX flow. 
- * The client must have already connected to and enabled a packetised service 
- * for the specified HDLC port. This disable interface can be called before a
- * disconnect, but is not required to.
- *
- * @param hssPortId @ref IxHssAccHssPort [in] - The HSS port Id. There are two
- * identical ports (0-1). 
- * @param hdlcPortId @ref IxHssAccHdlcPort [in] - The port id (0,1,2,3) to disable 
- * the service on.
- *
- * @return 
- *         - IX_SUCCESS The function executed successfully
- *         - IX_FAIL The function did not execute successfully
- *         - IX_HSSACC_PARAM_ERR The function did not execute successfully due to a
- *                          parameter error
- */
-PUBLIC IX_STATUS 
-ixHssAccPktPortDisable (IxHssAccHssPort hssPortId, 
-			IxHssAccHdlcPort hdlcPortId);
-
-/**
- *
- * @ingroup IxHssAccAPI
- *
- * @fn IX_STATUS ixHssAccPktPortDisconnect (IxHssAccHssPort hssPortId, 
-           IxHssAccHdlcPort hdlcPortId)
- *
- * @brief This function is responsible for disconnecting a client from one
- * of the 4 available HDLC ports. It is not required that the Rx Flow 
- * has been disabled before calling this function.  If the RX Flow has not been
- * disabled, the disconnect will disable it before proceeding with the
- * disconnect.  No other HssAccPacketised 
- * interface should be called while this interface is being processed.
- *
- * @param hssPortId @ref IxHssAccHssPort [in] - The HSS port Id. There are two
- * identical ports (0-1). 
- * @param hdlcPortId @ref IxHssAccHdlcPort [in] - This is the number of the HDLC port
- * to disconnect and it corresponds to the physical E1/T1 trunk i.e. 0, 1, 2, 3
- *
- * @return 
- *         - IX_SUCCESS The function executed successfully
- *         - IX_FAIL The function did not execute successfully 
- *         - IX_HSSACC_PKT_DISCONNECTING The function has initiated the disconnecting
- *                             procedure but it has not completed yet.
- */
-PUBLIC IX_STATUS 
-ixHssAccPktPortDisconnect (IxHssAccHssPort hssPortId, 
-			   IxHssAccHdlcPort hdlcPortId);
-
-/**
- *
- * @ingroup IxHssAccAPI
- *
- * @fn BOOL ixHssAccPktPortIsDisconnectComplete (IxHssAccHssPort hssPortId, 
-           IxHssAccHdlcPort hdlcPortId)
- *
- * @brief This function is called to check if a given HSS/HDLC port 
- * combination is in a connected state or not. This function may be called 
- * at any time to determine a ports state.  No other HssAccPacketised 
- * interface should be called while this interface is being processed.
- *
- * @param hssPortId @ref IxHssAccHssPort [in] - The HSS port Id. There are two
- * identical ports (0-1). 
- * @param hdlcPortId @ref IxHssAccHdlcPort [in] - This is the number of the HDLC port
- * to disconnect and it corresponds to the physical E1/T1 trunk i.e. 0, 1, 2, 3
- *
- * @return 
- *         - true The state of this HSS/HDLC port combination is disconnected,
- *                so if a disconnect was called, it is now completed.
- *         - false The state of this HSS/HDLC port combination is connected,
- *                so if a disconnect was called, it is not yet completed.
- */
-PUBLIC BOOL 
-ixHssAccPktPortIsDisconnectComplete (IxHssAccHssPort hssPortId, 
-				     IxHssAccHdlcPort hdlcPortId);
-
-
-/**
- *
- * @ingroup IxHssAccAPI
- *
- * @fn IX_STATUS ixHssAccPktPortRxFreeReplenish (IxHssAccHssPort hssPortId, 
-              IxHssAccHdlcPort hdlcPortId, 
-	      IX_OSAL_MBUF *buffer)
- *
- * @brief Function which the client calls at regular intervals to provide
- * mbufs to the access component for RX. A connection should exist for
- * the specified hssPortId/hdlcPortId combination before attempting to call this 
- * interface. Also, the connection should not be in a disconnecting state.
- *
- * @param hssPortId @ref IxHssAccHssPort [in] - The HSS port Id. There are two
- * identical ports (0-1). 
- * @param hdlcPortId @ref IxHssAccHdlcPort [in] - This is the number of the HDLC port
- * and it corresponds to the physical E1/T1 trunk i.e. 0, 1, 2, 3
- * @param *buffer @ref IX_OSAL_MBUF [in] - A pointer to a free mbuf to filled with payload.
- *
- * @return 
- *         - IX_SUCCESS The function executed successfully
- *         - IX_FAIL The function did not execute successfully
- *         - IX_HSSACC_PARAM_ERR The function did not execute successfully due to a
- *                          parameter error
- *         - IX_HSSACC_RESOURCE_ERR The function did not execute successfully due
- *                          to a resource error
- *         - IX_HSSACC_Q_WRITE_OVERFLOW The function did not succeed due to a Q
- *                                      overflow
- */
-PUBLIC IX_STATUS 
-ixHssAccPktPortRxFreeReplenish (IxHssAccHssPort hssPortId, 
-				IxHssAccHdlcPort hdlcPortId, 
-				IX_OSAL_MBUF *buffer);
-
-/**
- *
- * @ingroup IxHssAccAPI
- *
- * @fn IX_STATUS ixHssAccPktPortTx (IxHssAccHssPort hssPortId, 
-    IxHssAccHdlcPort hdlcPortId, 
-    IX_OSAL_MBUF *buffer)
- *
- * @brief Function which the client calls when it wants to transmit
- * packetised data. An enabled connection should exist on the specified
- * hssPortId/hdlcPortId combination before attempting to call this interface.
- * No other HssAccPacketised 
- * interface should be called while this interface is being processed.
- *
- * @param hssPortId @ref IxHssAccHssPort [in] - The HSS port Id. There are two
- * identical ports (0-1). 
- * @param hdlcPortId @ref IxHssAccHdlcPort [in] - This is the number of the HDLC port
- * and it corresponds to the physical E1/T1 trunk i.e. 0, 1, 2, 3
- * @param *buffer @ref IX_OSAL_MBUF [in] - A pointer to a chain of mbufs which the
- * client has filled with the payload
- *
- * @return 
- *         - IX_SUCCESS The function executed successfully
- *         - IX_FAIL The function did not execute successfully
- *         - IX_HSSACC_PARAM_ERR The function did not execute successfully due to a
- *                          parameter error
- *         - IX_HSSACC_RESOURCE_ERR The function did not execute successfully due
- *                          to a resource error. See note.
- *         - IX_HSSACC_Q_WRITE_OVERFLOW The function did not succeed due to a Q
- *                                      overflow
- *
- * @note IX_HSSACC_RESOURCE_ERR is returned when a free descriptor cannot be
- * obtained to send the chain of mbufs to the NPE.  This is a normal scenario.
- * HssAcc has a pool of descriptors and this error means that they are currently
- * all in use.
- * The recommended approach to this is to retry until a descriptor becomes free
- * and the packet is successfully transmitted.
- * Alternatively, the user could wait until the next IxHssAccPktTxDoneCallback
- * callback is triggered, and then retry, as it is this event that causes a
- * transmit descriptor to be freed. 
- */
-PUBLIC IX_STATUS 
-ixHssAccPktPortTx (IxHssAccHssPort hssPortId, 
-		   IxHssAccHdlcPort hdlcPortId, 
-		   IX_OSAL_MBUF *buffer);
-
-/**
- *
- * @ingroup IxHssAccAPI
- *
- * @fn IX_STATUS ixHssAccChanConnect (IxHssAccHssPort hssPortId, 
-           unsigned bytesPerTSTrigger, 
-	   UINT8 *rxCircular, 
-	   unsigned numRxBytesPerTS, 
-	   UINT32 *txPtrList, 
-	   unsigned numTxPtrLists, 
-	   unsigned numTxBytesPerBlk, 
-	   IxHssAccChanRxCallback rxCallback)
- *
- * @brief This function allows the client to connect to the Tx/Rx NPE
- * Channelised Service. There can only be one client per HSS port. The
- * client is responsible for ensuring that the HSS port is configured
- * appropriately before its connect request. No other HssAccChannelised 
- * interface should be called while this interface is being processed.
- *
- * @param hssPortId @ref IxHssAccHssPort [in] - The HSS port Id. There are two
- * identical ports (0-1). 
- * @param bytesPerTSTrigger unsigned [in] - The NPE will trigger the access
- * component after bytesPerTSTrigger have been received for all trunk
- * timeslots. This figure is a multiple of 8 e.g. 8 for 1ms trigger, 16 for
- * 2ms trigger.
- * @param *rxCircular UINT8 [in] - A pointer to memory allocated by the
- * client to be filled by data received. The buffer at this address is part
- * of a pool of buffers to be accessed in a circular fashion. This address
- * will be written to by the NPE. Therefore, it needs to be a physical address.
- * @param numRxBytesPerTS unsigned [in] - The number of bytes allocated per
- * timeslot within the receive memory. This figure will depend on the
- * latency of the system. It needs to be deep enough for data to be read by
- * the client before the NPE re-writes over that memory e.g. if the client
- * samples at a rate of 40bytes per timeslot, numRxBytesPerTS may need to
- * be 40bytes * 3. This would give the client 3 * 5ms of time before
- * received data is over-written.
- * @param *txPtrList UINT32 [in] - The address of an area of contiguous
- * memory allocated by the client to be populated with pointers to data for
- * transmission. Each pointer list contains a pointer per active channel.
- * The txPtrs will point to data to be transmitted by the NPE. Therefore,
- * they must point to physical addresses.
- * @param numTxPtrLists unsigned [in] - The number of pointer lists in
- * txPtrList. This figure is dependent on jitter.
- * @param numTxBytesPerBlk unsigned [in] - The size of the Tx data, in
- * bytes, that each pointer within the PtrList points to.
- * @param rxCallback @ref IxHssAccChanRxCallback [in] - A client function
- * pointer to be called back to handle the actual tx/rx of channelised
- * data. If this is not NULL, an ISR will call this function. If this
- * pointer is NULL, it implies that the client will use a polling mechanism
- * to detect when the tx and rx of channelised data is to occur. The client
- * will use hssChanAccStatus for this.
- *
- * @return
- *         - IX_SUCCESS The function executed successfully
- *         - IX_FAIL The function did not execute successfully
- *         - IX_HSSACC_PARAM_ERR The function did not execute successfully due to a
- *                          parameter error
- */
- 
-PUBLIC IX_STATUS 
-ixHssAccChanConnect (IxHssAccHssPort hssPortId, 
-		     unsigned bytesPerTSTrigger, 
-		     UINT8 *rxCircular, 
-		     unsigned numRxBytesPerTS, 
-		     UINT32 *txPtrList, 
-		     unsigned numTxPtrLists, 
-		     unsigned numTxBytesPerBlk, 
-		     IxHssAccChanRxCallback rxCallback);
-
-/**
- *
- * @ingroup IxHssAccAPI
- *
- * @fn IX_STATUS ixHssAccChanPortEnable (IxHssAccHssPort hssPortId)
- *
- * @brief This function is responsible for enabling a channelised service
- * for the specified HSS port. It enables the NPE RX flow. The client must
- * have already connected to a channelised service before enabling the
- * channelised service. No other HssAccChannelised 
- * interface should be called while this interface is being processed.
- *
- * @param hssPortId @ref IxHssAccHssPort [in] - The HSS port Id. There are two
- * identical ports (0-1). 
- *
- * @return
- *         - IX_SUCCESS The function executed successfully
- *         - IX_FAIL The function did not execute successfully
- *         - IX_HSSACC_PARAM_ERR The function did not execute successfully due to a
- *                          parameter error
- */
-PUBLIC IX_STATUS 
-ixHssAccChanPortEnable (IxHssAccHssPort hssPortId);
-
-/**
- *
- * @ingroup IxHssAccAPI
- *
- * @fn IX_STATUS ixHssAccChanPortDisable (IxHssAccHssPort hssPortId)
- *
- * @brief This function is responsible for disabling a channelised service
- * for the specified HSS port. It disables the NPE RX flow. The client must
- * have already connected to and enabled a channelised service for the
- * specified HSS port. This disable interface can be called before a
- * disconnect, but is not required to. No other HssAccChannelised 
- * interface should be called while this interface is being processed.
- *
- * @param hssPortId @ref IxHssAccHssPort [in] - The HSS port Id. There are two
- * identical ports (0-1). 
- *
- * @return 
- *         - IX_SUCCESS The function executed successfully
- *         - IX_FAIL The function did not execute successfully
- *         - IX_HSSACC_PARAM_ERR The function did not execute successfully due to a
- *                          parameter error
- */
-PUBLIC IX_STATUS 
-ixHssAccChanPortDisable (IxHssAccHssPort hssPortId);
-
-/**
- *
- * @ingroup IxHssAccAPI
- *
- * @fn IX_STATUS ixHssAccChanDisconnect (IxHssAccHssPort hssPortId)
- *
- * @brief This function allows the client to Disconnect from a channelised
- * service. If the NPE RX Flow has not been disabled, the disconnect will
- * disable it before proceeding with other disconnect functionality.
- * No other HssAccChannelised interface should be called while this 
- * interface is being processed.
- *
- * @param hssPortId @ref IxHssAccHssPort [in] - The HSS port Id. There are two
- * identical ports (0-1). 
- *
- * @return 
- *         - IX_SUCCESS The function executed successfully
- *         - IX_FAIL The function did not execute successfully
- *         - IX_HSSACC_PARAM_ERR The function did not execute successfully due to a
- *                          parameter error
- */
-PUBLIC IX_STATUS 
-ixHssAccChanDisconnect (IxHssAccHssPort hssPortId);
-
-/**
- *
- * @ingroup IxHssAccAPI
- *
- * @fn IX_STATUS ixHssAccChanStatusQuery (IxHssAccHssPort hssPortId, 
-           BOOL *dataRecvd, 
-	   unsigned *rxOffset, 
-	   unsigned *txOffset, 
-	   unsigned *numHssErrs)
- *
- * @brief This function is called by the client to query whether or not
- * channelised data has been received. If there is, hssChanAcc will return
- * the details in the output parameters. An enabled connection should
- * exist on the specified hssPortId before attempting to call this interface.  
- * No other HssAccChannelised interface should be called while this 
- * interface is being processed.
- *
- * @param hssPortId @ref IxHssAccHssPort [in] - The HSS port Id. There are two
- * identical ports (0-1). 
- * @param *dataRecvd BOOL [out] - This BOOL indicates to the client whether
- * or not the access component has read any data for the client. If
- * false, the other output parameters will not have been written to.
- * @param *rxOffset unsigned [out] - An offset to indicate to the client
- * where within the receive buffers the NPE has just written the received
- * data to.
- * @param *txOffset unsigned [out] - An offset to indicate to the client
- * from where within the txPtrList the NPE is currently transmitting from
- * @param *numHssErrs unsigned [out] - The total number of HSS port errors
- * since initial port configuration
- *
- *
- * @return 
- *         - IX_SUCCESS The function executed successfully
- *         - IX_FAIL The function did not execute successfully
- *         - IX_HSSACC_PARAM_ERR The function did not execute successfully due to a
- *                          parameter error
- */
-PUBLIC IX_STATUS 
-ixHssAccChanStatusQuery (IxHssAccHssPort hssPortId, 
-			 BOOL *dataRecvd, 
-			 unsigned *rxOffset, 
-			 unsigned *txOffset, 
-			 unsigned *numHssErrs);
-
-/**
- *
- * @ingroup IxHssAccAPI
- *
- * @fn void ixHssAccShow (void)
- *
- * @brief This function will display the current state of the IxHssAcc
- * component. The output is sent to stdout.
- *
- * @return void
- */
-PUBLIC void 
-ixHssAccShow (void);
-
-/**
- *
- * @ingroup IxHssAccAPI
- *
- * @fn void ixHssAccStatsInit (void)
- *
- * @brief This function will reset the IxHssAcc statistics.
- *
- * @return void
- */
-PUBLIC void 
-ixHssAccStatsInit (void);
-
-#endif /* IXHSSACC_H */
-
-/**
- * @} defgroup IxHssAcc
- */
diff --git a/drivers/net/npe/include/IxI2cDrv.h b/drivers/net/npe/include/IxI2cDrv.h
deleted file mode 100644
index 033154046f..0000000000
--- a/drivers/net/npe/include/IxI2cDrv.h
+++ /dev/null
@@ -1,843 +0,0 @@
-/**
- * @file IxI2cDrv.h
- *
- * @brief  Header file for the IXP400 I2C Driver (IxI2cDrv)
- *
- * @version $Revision: 0.1 $
- * 
- * @par
- * IXP400 SW Release version 2.0
- * 
- * -- Copyright Notice --
- * 
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- * 
- * @par
- * SPDX-License-Identifier:	BSD-3-Clause
- * @par
- * -- End of Copyright Notice --
- */
-
-/**
- * @defgroup IxI2cDrv IXP400 I2C Driver(IxI2cDrv) API 
- *
- * @brief IXP400 I2C Driver Public API
- *
- * @{
- */
-#ifndef IXI2CDRV_H
-#define IXI2CDRV_H
-
-#ifdef __ixp46X
-#include "IxOsal.h"
-
-/*
- * Section for #define
- */
-
-/**
- * @ingroup IxI2cDrv
- * @brief The interval of micro/mili seconds the IXP will wait before it polls for
- *			status from the ixI2cIntrXferStatus; Every 20us is 1 byte @
- *			400Kbps and 4 bytes	@ 100Kbps. This is dependent on delay type selected
- *          through the API ixI2cDrvDelayTypeSelect.
- */
-#define IX_I2C_US_POLL_FOR_XFER_STATUS	20
-
-/**
- * @ingroup IxI2cDrv
- * @brief The number of tries that will be attempted to call a callback
- *          function if the callback does not or is unable to resolve the
- *          issue it is called to resolve
- */
-#define IX_I2C_NUM_OF_TRIES_TO_CALL_CALLBACK_FUNC	10
-
-
-/**
- * @ingroup IxI2cDrv
- * @brief Number of tries slave will poll the IDBR Rx full bit before it
- *			gives up
- */
-#define IX_I2C_NUM_TO_POLL_IDBR_RX_FULL 0x100
-
-/**
- * @ingroup IxI2cDrv
- * @brief Number of tries slave will poll the IDBR Tx empty bit before it
- *			gives up
- */
-#define IX_I2C_NUM_TO_POLL_IDBR_TX_EMPTY 0x100
-
-/*
- * Section for enum
- */
-
-/**
- * @ingroup IxI2cDrv
- * 
- * @enum IxI2cMasterStatus
- *
- * @brief The master status - transfer complete, bus error or arbitration loss
- */
-typedef enum
-{
-    IX_I2C_MASTER_XFER_COMPLETE = IX_SUCCESS,
-	IX_I2C_MASTER_XFER_BUS_ERROR,
-	IX_I2C_MASTER_XFER_ARB_LOSS
-} IxI2cMasterStatus;
-
-
-/**
- * @ingroup IxI2cDrv
- * 
- * @enum IX_I2C_STATUS
- *
- * @brief The status that can be returned in a I2C driver initialization
- */
-typedef enum
-{
-	IX_I2C_SUCCESS = IX_SUCCESS, /**< Success status */
-	IX_I2C_FAIL, /**< Fail status */
-	IX_I2C_NOT_SUPPORTED, /**< hardware does not have dedicated I2C hardware */
-	IX_I2C_NULL_POINTER, /**< parameter passed in is NULL */
-	IX_I2C_INVALID_SPEED_MODE_ENUM_VALUE, /**< speed mode selected is invalid */
-	IX_I2C_INVALID_FLOW_MODE_ENUM_VALUE, /**< flow mode selected is invalid */
-	IX_I2C_SLAVE_ADDR_CB_MISSING, /**< slave callback is NULL */
-	IX_I2C_GEN_CALL_CB_MISSING, /**< general callback is NULL */
-	IX_I2C_INVALID_SLAVE_ADDR, /**< invalid slave address specified */
-	IX_I2C_INT_BIND_FAIL, /**< interrupt bind fail */
-	IX_I2C_INT_UNBIND_FAIL, /**< interrupt unbind fail */
-	IX_I2C_NOT_INIT, /**< I2C is not initialized yet */
-	IX_I2C_MASTER_BUS_BUSY, /**< master detected a I2C bus busy */
-	IX_I2C_MASTER_ARB_LOSS, /**< master experienced arbitration loss */
-	IX_I2C_MASTER_XFER_ERROR, /**< master experienced a transfer error */
-	IX_I2C_MASTER_BUS_ERROR, /**< master detected a I2C bus error */
-	IX_I2C_MASTER_NO_BUFFER, /**< no buffer provided for master transfer */
-	IX_I2C_MASTER_INVALID_XFER_MODE, /**< xfer mode selected is invalid */
-	IX_I2C_SLAVE_ADDR_NOT_DETECTED, /**< polled slave addr not detected */
-	IX_I2C_GEN_CALL_ADDR_DETECTED, /**< polling detected general call */
-	IX_I2C_SLAVE_READ_DETECTED, /**< polling detected slave read request */
-	IX_I2C_SLAVE_WRITE_DETECTED, /**< polling detected slave write request */
-	IX_I2C_SLAVE_NO_BUFFER, /**< no buffer provided for slave transfers */
-	IX_I2C_DATA_SIZE_ZERO, /**< data size transfer is zero - invalid */
-	IX_I2C_SLAVE_WRITE_BUFFER_EMPTY, /**< slave buffer is used till empty */
-	IX_I2C_SLAVE_WRITE_ERROR, /**< slave write experienced an error */
-	IX_I2C_SLAVE_OR_GEN_READ_BUFFER_FULL, /**< slave buffer is filled up */
-	IX_I2C_SLAVE_OR_GEN_READ_ERROR /**< slave read experienced an error */
-} IX_I2C_STATUS;
-
-/**
- * @ingroup IxI2cDrv
- * 
- * @enum IxI2cSpeedMode
- *
- * @brief Type of speed modes supported by the I2C hardware.
- */
-typedef enum
-{
-    IX_I2C_NORMAL_MODE = 0x0,
-    IX_I2C_FAST_MODE
-} IxI2cSpeedMode;
-
-/**
- * @ingroup IxI2cDrv
- * 
- * @enum IxI2cXferMode
- *
- * @brief Used for indicating it is a repeated start or normal transfer
- */
-typedef enum
-{
-    IX_I2C_NORMAL = 0x0,
-    IX_I2C_REPEATED_START
-} IxI2cXferMode;
-
-/**
- * @ingroup IxI2cDrv
- * 
- * @enum IxI2cFlowMode
- *
- * @brief Used for indicating it is a poll or interrupt mode
- */
-typedef enum
-{
-    IX_I2C_POLL_MODE = 0x0,
-    IX_I2C_INTERRUPT_MODE
-} IxI2cFlowMode;
-
-/**
- * @ingroup IxI2cDrv
- * 
- * @enum IxI2cDelayMode
- *
- * @brief Used for selecting looping delay or OS scheduler delay
- */
-typedef enum
-{
-    IX_I2C_LOOP_DELAY = 1,  /**< delay in microseconds */
-    IX_I2C_SCHED_DELAY      /**< delay in miliseconds */
-} IxI2cDelayMode;
-
-/**
- * @ingroup IxI2cDrv
- * 
- * @brief The pointer to the function that will be called when the master
- *			has completed its receive. The parameter that is passed will
- *			provide the status of the read (success, arb loss, or bus
- *			error), the transfer mode (normal or repeated start, the
- *			buffer pointer and number of bytes transferred.
- */
-typedef void (*IxI2cMasterReadCallbackP)(IxI2cMasterStatus, IxI2cXferMode, char*, UINT32);
-
-/**
- * @ingroup IxI2cDrv
- * 
- * @brief The pointer to the function that will	be called when the master
- *			has completed its transmit. The parameter that is passed will
- *			provide the status of the write (success, arb loss, or buss
- *			error), the transfer mode (normal or repeated start), the
- *			buffer pointer and number of bytes transferred.
- */
-typedef void (*IxI2cMasterWriteCallbackP)(IxI2cMasterStatus, IxI2cXferMode, char*, UINT32);
-
-/**
- * @ingroup IxI2cDrv
- * 
- * @brief The pointer to the function that will be called when a slave
- *			address detected in interrupt mode for a read. The parameters
- *			that is passed will provide the read status, buffer pointer,
- *			buffer size, and the bytes received. When a start of a read
- *			is initiated there will be no buffer allocated and this callback
- *			will be called to request for a buffer. While receiving, if the
- *			buffer gets filled, this callback will be called to request for
- *			a new buffer while sending the filled buffer's pointer and size,
- *			and data size received. When the receive is complete, this
- *			callback will be called to process the data and free the memory
- *			by passing the buffer's pointer and size, and data size received.
- */
-typedef void (*IxI2cSlaveReadCallbackP)(IX_I2C_STATUS, char*, UINT32, UINT32);
-
-/**
- * @ingroup IxI2cDrv
- * 
- * @brief The pointer to the function that will be called when a slave
- *			address detected in interrupt mode for a write. The parameters
- *			that is passed will provide the write status, buffer pointer,
- *			buffer size, and the bytes received. When a start of a write is
- *			initiated there will be no buffer allocated and this callback
- *			will be called to request for a buffer and to fill it with data.
- *			While transmitting, if the data in the buffer empties, this
- *			callback will be called to request for more data to be filled in
- *			the same or new buffer. When the transmit is complete, this
- *			callback will be called to free the memory or other actions to
- *			be taken.
- */
-typedef void (*IxI2cSlaveWriteCallbackP)(IX_I2C_STATUS, char*, UINT32, UINT32);
-
-/**
- * @ingroup IxI2cDrv
- * 
- * @brief The pointer to the function that will be called when a general
- *			call detected in interrupt mode for a read. The parameters that
- *			is passed will provide the read status, buffer pointer, buffer
- *			size, and the bytes received. When a start of a read is
- *			initiated there will be no buffer allocated and this callback
- *			will be called to request for a buffer. While receiving, if the
- *			buffer gets filled, this callback will be called to request for
- *			a new buffer while sending the filled buffer's pointer and size,
- *			and data size received. When the receive is complete, this
- *			callback will be called to process the data and free the memory
- *			by passing the buffer's pointer and size, and data size received.
- */
-typedef void (*IxI2cGenCallCallbackP)(IX_I2C_STATUS, char*, UINT32, UINT32);
-
-/*
- * Section for struct
- */
-
-/**
- * @brief contains all the variables required to initialize the I2C unit
- * 
- * Structure to be filled and used for calling initialization
- */
-typedef struct
-{
-	IxI2cSpeedMode I2cSpeedSelect;	/**<Select either normal (100kbps)
-									or fast mode (400kbps)*/
-	IxI2cFlowMode I2cFlowSelect;	/**<Select interrupt or poll mode*/	
-	IxI2cMasterReadCallbackP MasterReadCBP;
-									/**<The master read callback pointer */
-	IxI2cMasterWriteCallbackP MasterWriteCBP;
-									/**<The master write callback pointer */
-	IxI2cSlaveReadCallbackP SlaveReadCBP;
-									/**<The slave read callback pointer */
-	IxI2cSlaveWriteCallbackP SlaveWriteCBP;
-									/**<The slave write callback pointer */
-	IxI2cGenCallCallbackP GenCallCBP;
-									/**<The general call callback pointer */
-	BOOL I2cGenCallResponseEnable;	/**<Enable/disable the unit to
-									respond to generall calls.*/
-	BOOL I2cSlaveAddrResponseEnable;/**<Enable/disable the unit to
-									respond to the slave address set in
-									ISAR*/
-	BOOL SCLEnable;					/**<Enable/disable the unit from
-									driving the SCL line during master
-									mode operation*/
-	UINT8 I2cHWAddr;				/**<The address the unit will
-									response to as a slave device*/
-} IxI2cInitVars;
-
-/**
- * @brief contains results of counters and their overflow
- * 
- * Structure contains all values of counters and associated overflows.
- */
-typedef struct
-{
-	UINT32 ixI2cMasterXmitCounter;			/**<Total bytes transmitted as
-											master.*/
-	UINT32 ixI2cMasterFailedXmitCounter;	/**<Total bytes failed for
-											transmission as master.*/
-	UINT32 ixI2cMasterRcvCounter;			/**<Total bytes received as
-											master.*/
-	UINT32 ixI2cMasterFailedRcvCounter;		/**<Total bytes failed for
-											receival as master.*/
-	UINT32 ixI2cSlaveXmitCounter;			/**<Total bytes transmitted as
-											slave.*/
-	UINT32 ixI2cSlaveFailedXmitCounter;		/**<Total bytes failed for
-											transmission as slave.*/
-	UINT32 ixI2cSlaveRcvCounter;			/**<Total bytes received as
-											slave.*/
-	UINT32 ixI2cSlaveFailedRcvCounter;		/**<Total bytes failed for
-											receival as slave.*/
-	UINT32 ixI2cGenAddrCallSucceedCounter;	/**<Total bytes successfully
-											transmitted for general address.*/
-	UINT32 ixI2cGenAddrCallFailedCounter;	/**<Total bytes failed transmission
-											for general address.*/
-	UINT32 ixI2cArbLossCounter;				/**<Total instances of arbitration
-											loss has occured.*/
-} IxI2cStatsCounters;
-
-
-/*
- * Section for prototypes interface functions
- */
-
-/**
- * @ingroup IxI2cDrv
- * 
- * @fn ixI2cDrvInit(
-	IxI2cInitVars *InitVarsSelected)
- *
- * @brief Initializes the I2C Driver.
- *
- * @param "IxI2cInitVars [in] *InitVarsSelected" - struct containing required
- *			variables for initialization 
- *
- * Global Data	:
- *		- None.
- *
- * This API will check if the hardware supports this I2C driver and the validity
- * of the parameters passed in. It will continue to process the parameters
- * passed in by setting the speed of the I2C unit (100kbps or 400kbps), setting
- * the flow to either interrupt or poll mode, setting the address of the I2C unit,
- * enabling/disabling the respond to General Calls, enabling/disabling the respond
- * to Slave Address and SCL line driving. If it is interrupt mode, then it will
- * register the callback routines for master, slavetransfer and general call receive.
- *
- * @return 
- *      - IX_I2C_SUCCESS - Successfully initialize and enable the I2C
- *							hardware.
- *		- IX_I2C_NOT_SUPPORTED - The hardware does not support or have a
- *                              dedicated I2C unit to support this driver
- *		- IX_I2C_NULL_POINTER - The parameter passed in is a NULL pointed
- *		- IX_I2C_INVALID_SPEED_MODE_ENUM_VALUE - The speed mode selected in the
- *												InitVarsSelected is invalid
- *		- IX_I2C_INVALID_FLOW_MODE_ENUM_VALUE - The flow mode selected in the
- *												InitVarsSelected is invalid
- *		- IX_I2C_INVALID_SLAVE_ADDR - The address 0x0 is reserved for
- *										general call.
- *		- IX_I2C_SLAVE_ADDR_CB_MISSING - interrupt mode is selected but
- *										slave address callback pointer is NULL
- *		- IX_I2C_GEN_CALL_CB_MISSING - interrupt mode is selected but
- *										general call callback pointer is NULL
- *		- IX_I2C_INT_BIND_FAIL - The ISR for the I2C failed to bind
- *		- IX_I2C_INT_UNBIND_FAIL - The ISR for the I2C failed to unbind
- *
- * @li   Reentrant    : yes
- * @li   ISR Callable : yes
- *
- */
-PUBLIC IX_I2C_STATUS
-ixI2cDrvInit(IxI2cInitVars *InitVarsSelected);
-
-/**
- * @ingroup IxI2cDrv
- * 
- * @fn ixI2cDrvUninit(
-	void)
- *
- * @brief Disables the I2C hardware
- *
- * @param - None
- *
- * Global Data	:
- *		- None.
- *                        
- * This API will disable the I2C hardware, unbind interrupt, and unmap memory.
- *
- * @return 
- *      - IX_I2C_SUCCESS - successfully un-initialized I2C
- *		- IX_I2C_INT_UNBIND_FAIL - failed to unbind the I2C interrupt
- *		- IX_I2C_NOT_INIT - I2C not init yet.
- *              
- * @li   Reentrant    : yes
- * @li   ISR Callable : yes
- *
- */
-PUBLIC IX_I2C_STATUS
-ixI2cDrvUninit(void);
-
-/**
- * @ingroup IxI2cDrv
- * 
- * @fn ixI2cDrvSlaveAddrSet(
-	UINT8 SlaveAddrSet)
- *
- * @brief Sets the I2C Slave Address
- *
- * @param "UINT8 [in] SlaveAddrSet" - Slave Address to be inserted into ISAR
- *
- * Global Data	:
- *		- None.
- *                        
- * This API will insert the SlaveAddrSet into the ISAR.
- *
- * @return 
- *      - IX_I2C_SUCCESS - successfuly set the slave addr
- *		- IX_I2C_INVALID_SLAVE_ADDR - invalid slave address (zero) specified
- *		- IX_I2C_NOT_INIT - I2C not init yet.
- *              
- * @li   Reentrant    : yes
- * @li   ISR Callable : yes
- *
- */
-PUBLIC IX_I2C_STATUS
-ixI2cDrvSlaveAddrSet(UINT8 SlaveAddrSet);
-
-/**
- * @ingroup IxI2cDrv
- * 
- * @fn ixI2cDrvBusScan(
-	void)
- *
- * @brief scans the I2C bus for slave devices
- *
- * @param - None
- *
- * Global Data	:
- *		- None.
- *                        
- * This API will prompt all slave addresses for a reply except its own
- *
- * @return 
- *      - IX_I2C_SUCCESS - found at least one slave device
- *		- IX_I2C_FAIL - Fail to find even one slave device
- *		- IX_I2C_BUS_BUSY - The I2C bus is busy (held by another I2C master)
- *		- IX_I2C_ARB_LOSS - The I2C bus was loss to another I2C master
- *		- IX_I2C_NOT_INIT - I2C not init yet.
- *              
- * @li   Reentrant    : yes
- * @li   ISR Callable : yes
- *
- */
-PUBLIC IX_I2C_STATUS
-ixI2cDrvBusScan(void);
-
-/**
- * @ingroup IxI2cDrv
- * 
- * @fn ixI2cDrvWriteTransfer(
-	UINT8 SlaveAddr,
-	char *bufP,
-	UINT32 dataSize,
-	IxI2cXferMode XferModeSelect)
- *
- * @param "UINT8 [in] SlaveAddr" - The slave address to request data from.
- * @param "char [in] *bufP" - The pointer to the data to be transmitted.
- * @param "UINT32 [in] dataSize" - The number of bytes requested.
- * @param "IxI2cXferMode [in] XferModeSelect" - the transfer mode selected,
- *			either repeated start (ends w/o stop) or normal (start and stop)
- *
- * Global Data	:
- *		- None.
- *                        
- * This API will try to obtain master control of the I2C bus and transmit the
- * number of bytes, specified by dataSize, to the user specified slave
- * address from the buffer pointer. It will use either interrupt or poll mode
- * depending on the method selected. 
- *
- * If in interrupt mode and IxI2cMasterWriteCallbackP is not NULL, the driver
- * will initiate the transfer and return immediately. The function pointed to
- * by IxI2cMasterWriteCallbackP will be called in the interrupt service
- * handlers when the operation is complete.
- *
- * If in interrupt mode and IxI2cMasterWriteCallbackP is NULL, then the driver
- * will wait for the operation to complete, and then return.
- *
- * And if the repeated start transfer mode is selected, then it will not send a
- * stop signal at the end of all the transfers.
- * *NOTE*: If repeated start transfer mode is selected, it has to end with a
- *			normal mode transfer mode else the bus will continue to be held
- *			by the IXP.
- *
- * @return 
- *      - IX_I2C_SUCCESS - Successfuuly wrote data to slave.
- *		- IX_I2C_MASTER_BUS_BUSY - The I2C bus is busy (held by another I2C master)
- *		- IX_I2C_MASTER_ARB_LOSS - The I2C bus was loss to another I2C master
- *		- IX_I2C_MASTER_XFER_ERROR - There was a transfer error
- *      - IX_I2C_MASTER_BUS_ERROR - There was a bus error during transfer
- *		- IX_I2C_MASTER_NO_BUFFER - buffer pointer is NULL
- *      - IX_I2C_MASTER_INVALID_XFER_MODE - Xfer mode selected is invalid
- *      - IX_I2C_DATA_SIZE_ZERO - dataSize passed in is zero, which is invalid
- *		- IX_I2C_NOT_INIT - I2C not init yet.
- *              
- * @li   Reentrant    : no
- * @li   ISR Callable : no
- *
- */
-PUBLIC IX_I2C_STATUS
-ixI2cDrvWriteTransfer(
-	UINT8 SlaveAddr,
-	char *bufP,
-	UINT32 dataSize,
-	IxI2cXferMode XferModeSelect);
-
-/**
- * @ingroup IxI2cDrv
- * 
- * @fn ixI2cDrvReadTransfer(
-	UINT8 SlaveAddr,
-	char *bufP,
-	UINT32 dataSize,
-	IxI2cXferMode XferModeSelect)
- *
- * @brief Initiates a transfer to receive bytes of data from a slave
- *			device through the I2C bus.
- *
- * @param "UINT8 [in] SlaveAddr" - The slave address to request data from.
- * @param "char [out] *bufP" - The pointer to the buffer to store the
- *			requested data.
- * @param "UINT32 [in] dataSize" - The number of bytes requested.
- * @param "IxI2cXferMode [in] XferModeSelect" - the transfer mode selected,
- *			either repeated start (ends w/o stop) or normal (start and stop)
- *
- * Global Data	:
- *		- None.
- *                        
- * This API will try to obtain master control of the I2C bus and receive the
- * number of bytes, specified by dataSize, from the user specified address
- * into the receive buffer. It will use either interrupt or poll mode depending
- * on the mode selected.
- *
- * If in interrupt mode and IxI2cMasterReadCallbackP is not NULL, the driver
- * will initiate the transfer and return immediately. The function pointed to
- * by IxI2cMasterReadCallbackP will be called in the interrupt service
- * handlers when the operation is complete.
- *
- * If in interrupt mode and IxI2cMasterReadCallbackP is NULL, then the driver will
- * wait for the operation to complete, and then return.
- *
- * And if the repeated start transfer mode is selected, then it will not send a
- * stop signal at the end of all the transfers.
- * *NOTE*: If repeated start transfer mode is selected, it has to end with a
- *			normal mode transfer mode else the bus will continue to be held
- *			by the IXP.
- *
- * @return 
- *      - IX_I2C_SUCCESS - Successfuuly read slave data
- *		- IX_I2C_MASTER_BUS_BUSY - The I2C bus is busy (held by another I2C master)
- *		- IX_I2C_MASTER_ARB_LOSS - The I2C bus was loss to another I2C master
- *		- IX_I2C_MASTER_XFER_ERROR - There was a bus error during transfer
- *      - IX_I2C_MASTER_BUS_ERROR - There was a bus error during transfer
- *		- IX_I2C_MASTER_NO_BUFFER - buffer pointer is NULL
- *      - IX_I2C_MASTER_INVALID_XFER_MODE - Xfer mode selected is invalid
- *      - IX_I2C_INVALID_SLAVE_ADDR - invalid slave address (zero) specified
- *      - IX_I2C_DATA_SIZE_ZERO - dataSize passed in is zero, which is invalid
- *		- IX_I2C_NOT_INIT - I2C not init yet.
- *              
- * @li   Reentrant    : no
- * @li   ISR Callable : no
- *
- */
-PUBLIC IX_I2C_STATUS
-ixI2cDrvReadTransfer(
-	UINT8 SlaveAddr,
-	char *bufP,
-	UINT32 dataSize,
-	IxI2cXferMode XferModeSelect);
-
-/**
- * @ingroup IxI2cDrv
- * 
- * @fn ixI2cDrvSlaveAddrAndGenCallDetectedCheck(
-	void)
- *
- * @brief Checks the I2C Status Register to determine if a slave address is
- *			detected
- *
- * @param - None
- *
- * Global Data	:
- *		- None.
- *                        
- * This API is used in polled mode to determine if the I2C unit is requested
- * for a slave or general call transfer. If it is requested for a slave
- * transfer then it will determine if it is a general call (read only), read,
- * or write transfer requested.
- *
- * @return 
- *      - IX_I2C_SLAVE_ADDR_NOT_DETECTED - The I2C unit is not requested for slave
- *										transfer
- *		- IX_I2C_GEN_CALL_ADDR_DETECTED - The I2C unit is not requested for slave
- *									transfer but for general call
- *      - IX_I2C_SLAVE_READ_DETECTED - The I2C unit is requested for a read
- *      - IX_I2C_SLAVE_WRITE_DETECTED - The I2C unit is requested for a write
- *		- IX_I2C_NOT_INIT - I2C not init yet.
- *              
- * @li   Reentrant    : no
- * @li   ISR Callable : no
- *
- */
-PUBLIC IX_I2C_STATUS
-ixI2cDrvSlaveAddrAndGenCallDetectedCheck(void);
-
-/**
- * @ingroup IxI2cDrv
- * 
- * @fn ixI2cDrvSlaveOrGenDataReceive(
-	char *bufP,
-	UINT32 bufSize,
-	UINT32 *dataSizeRcvd)
- *
- * @brief Performs the slave receive or general call receive data transfer
- *
- * @param	"char [in] *bufP" - the pointer to the buffer to store data
- *			"UINT32 [in] bufSize" - the buffer size allocated
- *			"UINT32 [in] *dataSizeRcvd" - the length of data received in bytes
- *
- * Global Data	:
- *		- None.
- *                        
- * This API is only used in polled mode to perform the slave read or general call
- * receive data. It will continuously store the data received into bufP until
- * complete or until bufP is full in which it will return
- * IX_I2C_SLAVE_OR_GEN_READ_BUFFER_FULL. If in interrupt mode, the callback will be
- * used.
- *
- * @return 
- *      - IX_I2C_SUCCESS - The I2C driver transferred the data successfully.
- *		- IX_I2C_SLAVE_OR_GEN_READ_BUFFER_FULL - The I2C driver has ran out of
- *			space to store the received data.
- *		- IX_I2C_SLAVE_OR_GEN_READ_ERROR - The I2C driver didn't manage to
- *			detect the IDBR Rx Full bit
- *      - IX_I2C_DATA_SIZE_ZERO - bufSize passed in is zero, which is invalid
- *		- IX_I2C_SLAVE_NO_BUFFER - buffer pointer is NULL
- *      - IX_I2C_NULL_POINTER - dataSizeRcvd is NULL
- *		- IX_I2C_NOT_INIT - I2C not init yet.
- *              
- * @li   Reentrant    : no
- * @li   ISR Callable : no
- *
- */
-PUBLIC IX_I2C_STATUS
-ixI2cDrvSlaveOrGenDataReceive(
-	char *bufP,
-	UINT32 bufSize,
-	UINT32 *dataSizeRcvd);
-
-/**
- * @ingroup IxI2cDrv
- * 
- * @fn ixI2cDrvSlaveDataTransmit(
-	char *bufP,
-	UINT32 dataSize,
-	UINT32 *dataSizeXmtd)
- *
- * @brief Performs the slave write data transfer
- *
- * @param	"char [in] *bufP" - the pointer to the buffer for data to be
- *				transmitted
- *			"UINT32 [in] bufSize" - the buffer size allocated
- *			"UINT32 [in] *dataSizeRcvd" - the length of data trasnmitted in
- *				bytes
- *
- * Global Data	:
- *		- None.
- *                        
- * This API is only used in polled mode to perform the slave transmit data. It
- * will continuously transmit the data from bufP until complete or until bufP
- * is empty in which it will return IX_I2C_SLAVE_WRITE_BUFFER_EMPTY. If in
- * interrupt mode, the callback will be used.
- *
- * @return 
- *      - IX_I2C_SUCCESS - The I2C driver transferred the data successfully.
- *      - IX_I2C_SLAVE_WRITE_BUFFER_EMPTY - The I2C driver needs more data to
- *			transmit.
- *      - IX_I2C_SLAVE_WRITE_ERROR -The I2C driver didn't manage to detect the
- *          IDBR Tx empty bit or the slave stop bit.
- *      - IX_I2C_DATA_SIZE_ZERO - dataSize passed in is zero, which is invalid
- *		- IX_I2C_SLAVE_NO_BUFFER - buffer pointer is NULL
- *      - IX_I2C_NULL_POINTER - dataSizeXmtd is NULL
- *		- IX_I2C_NOT_INIT - I2C not init yet.
- *              
- * @li   Reentrant    : no
- * @li   ISR Callable : no
- *
- */
-PUBLIC IX_I2C_STATUS
-ixI2cDrvSlaveDataTransmit(
-	char *bufP,
-	UINT32 dataSize,
-	UINT32 *dataSizeXmtd);
-
-/**
- * @ingroup IxI2cDrv
- * 
- * @fn ixI2cDrvSlaveOrGenCallBufReplenish(
-	char *bufP,
-	UINT32 bufSize)
- *
- * @brief Replenishes the buffer which stores buffer info for both slave and
- *			general call
- *
- * @param	"char [in] *bufP" - pointer to the buffer allocated
- *			"UINT32 [in] bufSize" - size of the buffer
- *
- * Global Data	:
- *		- None.
- *                        
- * This API is only used in interrupt mode for replenishing the same buffer
- * that is used by both slave and generall call by updating the buffer info
- * with new info and clearing previous offsets set by previous transfers.
- *
- * @return 
- *      - None
- *              
- * @li   Reentrant    : no
- * @li   ISR Callable : no
- *
- */
-PUBLIC void
-ixI2cDrvSlaveOrGenCallBufReplenish(
-	char *bufP,
-	UINT32 bufSize);
-
-/**
- * @ingroup IxI2cDrv
- * 
- * @fn ixI2cDrvStatsGet(IxI2cStatsCounters *I2cStats)
- *
- * @brief Returns the I2C Statistics through the pointer passed in
- *
- * @param - "IxI2cStatsCounters [out] *I2cStats" - I2C statistics counter will
- *			be read and written to the location pointed by this pointer.
- *
- * Global Data	:
- *		- None.
- *                        
- * This API will return the statistics counters of the I2C driver.
- *
- * @return 
- *      - IX_I2C_NULL_POINTER - pointer passed in is NULL
- *		- IX_I2C_SUCCESS - successfully obtained I2C statistics
- *              
- * @li   Reentrant    : yes
- * @li   ISR Callable : no
- *
- */
-PUBLIC IX_I2C_STATUS
-ixI2cDrvStatsGet(IxI2cStatsCounters *I2cStats);
-
-/**
- * @ingroup IxI2cDrv
- * 
- * @fn ixI2cDrvStatsReset(void)
- *
- * @brief Reset I2C statistics counters.
- *
- * @param - None
- *
- * Global Data	:
- *		- None.
- *                        
- * This API will reset the statistics counters of the I2C driver.
- *
- * @return 
- *      - None
- *              
- * @li   Reentrant    : yes
- * @li   ISR Callable : no
- *
- */
-PUBLIC void
-ixI2cDrvStatsReset(void);
-
-/**
- * @ingroup IxI2cDrv
- * 
- * @fn ixI2cDrvShow(void)
- *
- * @brief Displays the I2C status register and the statistics counter.
- *
- * @param - None
- *
- * Global Data	:
- *		- None.
- *                        
- * This API will display the I2C Status register and is useful if any error
- * occurs. It displays the detection of bus error, slave address, general call,
- * address, IDBR receive full, IDBR transmit empty, arbitration loss, slave
- * STOP signal, I2C bus busy, unit busy, ack/nack, and read/write mode. It will
- * also call the ixI2cDrvGetStats and then display the statistics counter.
- *
- * @return 
- *		- IX_I2C_SUCCESS - successfully displayed statistics and status register
- *		- IX_I2C_NOT_INIT - I2C not init yet.
- *              
- * @li   Reentrant    : yes
- * @li   ISR Callable : no
- *
- */
-PUBLIC IX_I2C_STATUS
-ixI2cDrvShow(void);
-
-/**
- * @ingroup IxI2cDrv
- * 
- * @fn ixI2cDrvDelayTypeSelect (IxI2cDelayMode delayMechanismSelect)
- *
- * @brief Sets the delay type of either looping delay or OS scheduler delay
- *          according to the argument provided.
- *
- * @param - "IxI2cDelayMode [in] delayTypeSelect" - the I2C delay type selected
- *
- * Global Data	:
- *		- None.
- *                        
- * This API will set the delay type used by the I2C Driver to either looping
- * delay or OS scheduler delay.
- *
- * @return 
- *		- None
- *              
- * @li   Reentrant    : yes
- * @li   ISR Callable : no
- *
- */
-PUBLIC void
-ixI2cDrvDelayTypeSelect (IxI2cDelayMode delayTypeSelect);
-
-#endif /* __ixp46X */
-#endif /* IXI2CDRV_H */
diff --git a/drivers/net/npe/include/IxNpeA.h b/drivers/net/npe/include/IxNpeA.h
deleted file mode 100644
index e145b4365f..0000000000
--- a/drivers/net/npe/include/IxNpeA.h
+++ /dev/null
@@ -1,758 +0,0 @@
-#ifndef __doxygen_HIDE  /* This file is not part of the API */
-
-/**
- * @file    IxNpeA.h
- *
- * @date    22-Mar-2002
- *
- * @brief   Header file for the IXP400 ATM NPE API
- *
- * 
- * @par
- * IXP400 SW Release version 2.0
- * 
- * -- Copyright Notice --
- * 
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- * 
- * @par
- * SPDX-License-Identifier:	BSD-3-Clause
- * @par
- * -- End of Copyright Notice --
- */
-
-/**
- * @defgroup IxNpeA IXP400 NPE-A (IxNpeA) API
- *
- * @brief The Public API for the IXP400 NPE-A
- *
- * @{
- */
-
-#ifndef IX_NPE_A_H
-#define IX_NPE_A_H
-
-#include "IxQMgr.h"
-#include "IxOsal.h"
-#include "IxQueueAssignments.h"
-
-/* General Message Ids */
-
-/* ATM Message Ids */
-
-/**
- * @def IX_NPE_A_MSSG_ATM_UTOPIA_CONFIG_WRITE
- *
- * @brief ATM Message ID command to write the data to the offset in the
- * Utopia Configuration Table
- */
-#define IX_NPE_A_MSSG_ATM_UTOPIA_CONFIG_WRITE       0x20
-
-/**
- * @def IX_NPE_A_MSSG_ATM_UTOPIA_CONFIG_LOAD
- *
- * @brief ATM Message ID command triggers the NPE to copy the Utopia
- * Configuration Table to the Utopia coprocessor
- */
-#define IX_NPE_A_MSSG_ATM_UTOPIA_CONFIG_LOAD        0x21
-
-/**
- * @def IX_NPE_A_MSSG_ATM_UTOPIA_STATUS_UPLOAD
- *
- * @brief ATM Message ID command triggers the NPE to read-back the Utopia
- * status registers and update the Utopia Status Table.
- */
-#define IX_NPE_A_MSSG_ATM_UTOPIA_STATUS_UPLOAD      0x22
-
-/**
- * @def IX_NPE_A_MSSG_ATM_UTOPIA_STATUS_READ
- *
- * @brief ATM Message ID command to read the Utopia Status Table at the
- * specified offset.
- */
-#define IX_NPE_A_MSSG_ATM_UTOPIA_STATUS_READ        0x23
-
-/**
- * @def IX_NPE_A_MSSG_ATM_TX_ENABLE
- *
- * @brief ATM Message ID command triggers the NPE to re-enable processing
- * of any entries on the TxVcQ for this port.
- *
- * This command will be ignored for a port already enabled
- */
-#define IX_NPE_A_MSSG_ATM_TX_ENABLE                 0x25
-
- /**
- * @def IX_NPE_A_MSSG_ATM_TX_DISABLE
- *
- * @brief ATM Message ID command triggers the NPE to disable processing on
- * this port
- *
- * This command will be ignored for a port already disabled
- */
-#define IX_NPE_A_MSSG_ATM_TX_DISABLE                0x26
-
-/**
- * @def IX_NPE_A_MSSG_ATM_RX_ENABLE
- *
- * @brief ATM Message ID command triggers the NPE to process any received
- * cells for this VC according to the VC Lookup Table.
- *
- * Re-issuing this command with different contents for a VC that is not
- * disabled will cause unpredictable behavior.
- */
-#define IX_NPE_A_MSSG_ATM_RX_ENABLE                 0x27
-
-/**
- * @def IX_NPE_A_MSSG_ATM_RX_DISABLE
- *
- * @brief ATM Message ID command triggers the NPE to disable processing for
- * this VC.
- *
- * This command will be ignored for a VC already disabled
- */
-#define IX_NPE_A_MSSG_ATM_RX_DISABLE                0x28
-
-/**
- * @def IX_NPE_A_MSSG_ATM_STATUS_READ
- *
- * @brief ATM Message ID command to read the ATM status. The data is returned via
- * a response message
- */
-#define IX_NPE_A_MSSG_ATM_STATUS_READ               0x29
-
-/*--------------------------------------------------------------------------
- * HSS Message IDs
- *--------------------------------------------------------------------------*/
-
-/**
- * @def IX_NPE_A_MSSG_HSS_PORT_CONFIG_WRITE
- *
- * @brief HSS Message ID command writes the ConfigWord value to the location
- * in the HSS_CONFIG_TABLE specified by offset for HSS port hPort.
- */
-#define IX_NPE_A_MSSG_HSS_PORT_CONFIG_WRITE         0x40
-
-/**
- * @def IX_NPE_A_MSSG_HSS_PORT_CONFIG_LOAD
- *
- * @brief HSS Message ID command triggers the NPE to copy the contents of the
- * HSS Configuration Table to the appropriate configuration registers in the
- * HSS coprocessor for the port specified by hPort.
- */
-#define IX_NPE_A_MSSG_HSS_PORT_CONFIG_LOAD          0x41
-
-/**
- * @def IX_NPE_A_MSSG_HSS_PORT_ERROR_READ
- *
- * @brief HSS Message ID command triggers the NPE to return an HssErrorReadResponse
- * message for HSS port hPort.
- */
-#define IX_NPE_A_MSSG_HSS_PORT_ERROR_READ           0x42
-
-/**
- * @def IX_NPE_A_MSSG_HSS_CHAN_FLOW_ENABLE
- *
- * @brief HSS Message ID command triggers the NPE to reset internal status and
- * enable the HssChannelized operation on the HSS port specified by hPort.
- */
-#define IX_NPE_A_MSSG_HSS_CHAN_FLOW_ENABLE          0x43
-
-/**
- * @def IX_NPE_A_MSSG_HSS_CHAN_FLOW_DISABLE
- *
- * @brief HSS Message ID command triggers the NPE to disable the HssChannelized
- * operation on the HSS port specified by hPort.
- */
-#define IX_NPE_A_MSSG_HSS_CHAN_FLOW_DISABLE         0x44
-
-/**
- * @def  IX_NPE_A_MSSG_HSS_CHAN_IDLE_PATTERN_WRITE
- *
- * @brief HSS Message ID command writes the HSSnC_IDLE_PATTERN value for HSS
- * port hPort. (n=hPort)
- */
-#define IX_NPE_A_MSSG_HSS_CHAN_IDLE_PATTERN_WRITE   0x45
-
-/**
- * @def IX_NPE_A_MSSG_HSS_CHAN_NUM_CHANS_WRITE
- *
- * @brief HSS Message ID command writes the HSSnC_NUM_CHANNELS value for HSS
- * port hPort. (n=hPort)
- */
-#define IX_NPE_A_MSSG_HSS_CHAN_NUM_CHANS_WRITE      0x46
-
-/**
- * @def IX_NPE_A_MSSG_HSS_CHAN_RX_BUF_ADDR_WRITE
- *
- * @brief HSS Message ID command writes the HSSnC_RX_BUF_ADDR value for HSS
- * port hPort. (n=hPort)
- */
-#define IX_NPE_A_MSSG_HSS_CHAN_RX_BUF_ADDR_WRITE    0x47
-
-/**
- * @def IX_NPE_A_MSSG_HSS_CHAN_RX_BUF_CFG_WRITE
- *
- * @brief HSS Message ID command  writes the HSSnC_RX_BUF_SIZEB and
- * HSSnC_RX_TRIG_PERIOD values for HSS port hPort.  (n=hPort)
- */
-#define IX_NPE_A_MSSG_HSS_CHAN_RX_BUF_CFG_WRITE     0x48
-
-/**
- * @def IX_NPE_A_MSSG_HSS_CHAN_TX_BLK_CFG_WRITE
- *
- * @brief HSS Message ID command writes the HSSnC_TX_BLK1_SIZEB,
- * HSSnC_TX_BLK1_SIZEW, HSSnC_TX_BLK2_SIZEB, and HSSnC_TX_BLK2_SIZEW  values
- * for HSS port hPort. (n=hPort)
- */
-#define IX_NPE_A_MSSG_HSS_CHAN_TX_BLK_CFG_WRITE     0x49
-
-/**
- * @def IX_NPE_A_MSSG_HSS_CHAN_TX_BUF_ADDR_WRITE
- * @brief HSS Message ID command writes the HSSnC_TX_BUF_ADDR value for HSS
- * port hPort. (n=hPort)
- */
-#define IX_NPE_A_MSSG_HSS_CHAN_TX_BUF_ADDR_WRITE    0x4A
-
-/**
- * @def IX_NPE_A_MSSG_HSS_CHAN_TX_BUF_SIZE_WRITE
- *
- * @brief HSS Message ID command writes the HSSnC_TX_BUF_SIZEN value for HSS
- * port hPort. (n=hPort)
- */
-#define IX_NPE_A_MSSG_HSS_CHAN_TX_BUF_SIZE_WRITE    0x4B
-
-/**
- * @def IX_NPE_A_MSSG_HSS_PKT_PIPE_FLOW_ENABLE
- *
- * @brief HSS Message ID command triggers the NPE to reset internal status and
- * enable the HssPacketized operation for the flow specified by pPipe on
- * the HSS port specified by hPort.
- */
-#define IX_NPE_A_MSSG_HSS_PKT_PIPE_FLOW_ENABLE      0x50
-
-/**
- * @def IX_NPE_A_MSSG_HSS_PKT_PIPE_FLOW_DISABLE
- * @brief HSS Message ID command triggers the NPE to disable the HssPacketized
- * operation for the flow specified by pPipe on the HSS port specified by hPort.
- */
-#define IX_NPE_A_MSSG_HSS_PKT_PIPE_FLOW_DISABLE     0x51
-
-/**
- * @def IX_NPE_A_MSSG_HSS_PKT_NUM_PIPES_WRITE
- * @brief HSS Message ID command writes the HSSnP_NUM_PIPES value for HSS
- * port hPort.(n=hPort)
- */
-#define IX_NPE_A_MSSG_HSS_PKT_NUM_PIPES_WRITE       0x52
-
-/**
- * @def IX_NPE_A_MSSG_HSS_PKT_PIPE_FIFO_SIZEW_WRITE
- *
- * @brief HSS Message ID command writes the HSSnP_PIPEp_FIFOSIZEW value for
- * packet-pipe pPipe on HSS port hPort.  (n=hPort, p=pPipe)
- */
-#define IX_NPE_A_MSSG_HSS_PKT_PIPE_FIFO_SIZEW_WRITE 0x53
-
-/**
- * @def IX_NPE_A_MSSG_HSS_PKT_PIPE_HDLC_CFG_WRITE
- *
- * @brief HSS Message ID command writes the HSSnP_PIPEp_HDLC_RXCFG and
- * HSSnP_PIPEp_HDLC_TXCFG values for packet-pipe pPipe on HSS port hPort.
- * (n=hPort, p=pPipe)
- */
-#define IX_NPE_A_MSSG_HSS_PKT_PIPE_HDLC_CFG_WRITE   0x54
-
-/**
- * @def IX_NPE_A_MSSG_HSS_PKT_PIPE_IDLE_PATTERN_WRITE
- *
- * @brief HSS Message ID command writes the HSSnP_PIPEp_IDLE_PATTERN value
- * for packet-pipe pPipe on HSS port hPort.  (n=hPort, p=pPipe)
- */
-#define IX_NPE_A_MSSG_HSS_PKT_PIPE_IDLE_PATTERN_WRITE 0x55
-
-/**
- * @def IX_NPE_A_MSSG_HSS_PKT_PIPE_RX_SIZE_WRITE
- *
- * @brief HSS Message ID command writes the HSSnP_PIPEp_RXSIZEB value for
- * packet-pipe pPipe on HSS port hPort.  (n=hPort, p=pPipe)
- */
-#define IX_NPE_A_MSSG_HSS_PKT_PIPE_RX_SIZE_WRITE    0x56
-
-/**
- * @def IX_NPE_A_MSSG_HSS_PKT_PIPE_MODE_WRITE
- *
- * @brief HSS Message ID command writes the HSSnP_PIPEp_MODE value for
- * packet-pipe pPipe on HSS port hPort.  (n=hPort, p=pPipe)
- */
-#define IX_NPE_A_MSSG_HSS_PKT_PIPE_MODE_WRITE       0x57
-
-
-
-/* Queue Entry Masks */
-
-/*--------------------------------------------------------------------------
- *  ATM Descriptor Structure offsets
- *--------------------------------------------------------------------------*/
-
-/**
- * @def IX_NPE_A_RXDESCRIPTOR_STATUS_OFFSET
- *
- * @brief ATM Descriptor structure offset for Receive Descriptor Status field
- *
- * It is used for descriptor error reporting.
- */
-#define IX_NPE_A_RXDESCRIPTOR_STATUS_OFFSET          0
-
-/**
- * @def IX_NPE_A_RXDESCRIPTOR_VCID_OFFSET
- *
- * @brief ATM Descriptor structure offset for Receive Descriptor VC ID field
- *
- * It is used to hold an identifier number for this VC
- */
-#define IX_NPE_A_RXDESCRIPTOR_VCID_OFFSET            1
-
-/**
- * @def IX_NPE_A_RXDESCRIPTOR_CURRMBUFSIZE_OFFSET
- *
- * @brief ATM Descriptor structure offset for Receive Descriptor Current Mbuf
- * Size field
- *
- * Number of bytes the current mbuf data buffer can hold
- */
-#define IX_NPE_A_RXDESCRIPTOR_CURRMBUFSIZE_OFFSET    2
-
-/**
- * @def IX_NPE_A_RXDESCRIPTOR_ATMHEADER_OFFSET
- *
- * @brief ATM Descriptor structure offset for Receive Descriptor ATM Header
- */
-#define IX_NPE_A_RXDESCRIPTOR_ATMHEADER_OFFSET       4
-
-/**
- * @def IX_NPE_A_RXDESCRIPTOR_CURRMBUFLEN_OFFSET
- *
- * @brief ATM Descriptor structure offset for Receive Descriptor Current MBuf length
- *
- *
- * RX - Initialized to zero.  The NPE updates this field as each cell is received and
- * zeroes it with every new mbuf for chaining. Will not be bigger than currBbufSize.
- */
-#define IX_NPE_A_RXDESCRIPTOR_CURRMBUFLEN_OFFSET    12
-
-/**
- * @def IX_NPE_A_RXDESCRIPTOR_TIMELIMIT__OFFSET
- *
- * @brief ATM Descriptor structure offset for Receive Descriptor Time Limit field
- *
- * Contains the Payload Reassembly Time Limit (used for aal0_xx only)
- */
-#define IX_NPE_A_RXDESCRIPTOR_TIMELIMIT_OFFSET        14
-
-/**
- * @def IX_NPE_A_RXDESCRIPTOR_PCURRMBUFF_OFFSET
- *
- * @brief ATM Descriptor structure offset for Receive Descriptor Current MBuf Pointer
- *
- * The current mbuf pointer of a chain of mbufs.
- */
-#define IX_NPE_A_RXDESCRIPTOR_PCURRMBUFF_OFFSET     20
-
-/**
- * @def IX_NPE_A_RXDESCRIPTOR_PCURRMBUFDATA_OFFSET
- *
- * @brief ATM Descriptor structure offset for Receive Descriptor Current MBuf Pointer
- *
- * Pointer to the next byte to be read or next free location to be written.
- */
-#define IX_NPE_A_RXDESCRIPTOR_PCURRMBUFDATA_OFFSET  24
-
-/**
- * @def IX_NPE_A_RXDESCRIPTOR_PNEXTMBUF_OFFSET
- *
- * @brief ATM Descriptor structure offset for Receive Descriptor Next MBuf Pointer
- *
- * Pointer to the next MBuf in a chain of MBufs.
- */
-#define IX_NPE_A_RXDESCRIPTOR_PNEXTMBUF_OFFSET      28
-
-/**
- * @def IX_NPE_A_RXDESCRIPTOR_TOTALLENGTH_OFFSET
- *
- * @brief ATM Descriptor structure offset for Receive Descriptor Total Length
- *
- * Total number of bytes written to the chain of MBufs by the NPE
- */
-#define IX_NPE_A_RXDESCRIPTOR_TOTALLENGTH_OFFSET    32
-
-/**
- * @def IX_NPE_A_RXDESCRIPTOR_AAL5CRCRESIDUE_OFFSET
- *
- * @brief ATM Descriptor structure offset for Receive Descriptor AAL5 CRC Residue
- *
- * Current CRC value for a PDU
- */
-#define IX_NPE_A_RXDESCRIPTOR_AAL5CRCRESIDUE_OFFSET 36
-
-/**
- * @def IX_NPE_A_RXDESCRIPTOR_SIZE
- *
- * @brief ATM Descriptor structure offset for Receive Descriptor Size
- *
- * The size of the Receive descriptor
- */
-#define IX_NPE_A_RXDESCRIPTOR_SIZE                  40
-
-/**
- * @def IX_NPE_A_TXDESCRIPTOR_PORT_OFFSET
- *
- * @brief ATM Descriptor structure offset for Transmit Descriptor Port
- *
- * Port identifier.
- */
-#define IX_NPE_A_TXDESCRIPTOR_PORT_OFFSET            0
-
-/**
- * @def IX_NPE_A_TXDESCRIPTOR_RSVD_OFFSET
- *
- * @brief ATM Descriptor structure offset for Transmit Descriptor RSVD
- */
-#define IX_NPE_A_TXDESCRIPTOR_RSVD_OFFSET            1
-
-/**
- * @def IX_NPE_A_TXDESCRIPTOR_CURRMBUFLEN_OFFSET
- *
- * @brief ATM Descriptor structure offset for Transmit Descriptor Current MBuf Length
- *
- * TX - Initialized by the XScale to the number of bytes in the current MBuf data buffer.
- * The NPE decrements this field for every transmitted cell.  Thus, when the NPE writes a
- * descriptor the TxDone queue, this field will equal zero.
- */
-#define IX_NPE_A_TXDESCRIPTOR_CURRMBUFLEN_OFFSET     2
-
-/**
- * @def IX_NPE_A_TXDESCRIPTOR_ATMHEADER_OFFSET
- * @brief ATM Descriptor structure offset for Transmit Descriptor ATM Header
- */
-#define IX_NPE_A_TXDESCRIPTOR_ATMHEADER_OFFSET       4
-
-/**
- * @def IX_NPE_A_TXDESCRIPTOR_PCURRMBUFF_OFFSET
- *
- * @brief ATM Descriptor structure offset for Transmit Descriptor Pointer to the current MBuf chain
- */
-#define IX_NPE_A_TXDESCRIPTOR_PCURRMBUFF_OFFSET      8
-
-/**
- * @def IX_NPE_A_TXDESCRIPTOR_PCURRMBUFDATA_OFFSET
- *
- * @brief ATM Descriptor structure offset for Transmit Descriptor Pointer to the current MBuf Data
- *
- * Pointer to the next byte to be read or next free location to be written.
- */
-#define IX_NPE_A_TXDESCRIPTOR_PCURRMBUFDATA_OFFSET  12
-
-/**
- * @def IX_NPE_A_TXDESCRIPTOR_PNEXTMBUF_OFFSET
- *
- * @brief ATM Descriptor structure offset for Transmit Descriptor Pointer to the Next MBuf chain
- */
-#define IX_NPE_A_TXDESCRIPTOR_PNEXTMBUF_OFFSET      16
-
-/**
- * @def IX_NPE_A_TXDESCRIPTOR_TOTALLENGTH_OFFSET
- *
- * @brief ATM Descriptor structure offset for Transmit Descriptor Total Length
- *
- * Total number of bytes written to the chain of MBufs by the NPE
- */
-#define IX_NPE_A_TXDESCRIPTOR_TOTALLENGTH_OFFSET    20
-
-/**
- * @def IX_NPE_A_TXDESCRIPTOR_AAL5CRCRESIDUE_OFFSET
- *
- * @brief ATM Descriptor structure offset for Transmit Descriptor AAL5 CRC Residue
- *
- * Current CRC value for a PDU
- */
-#define IX_NPE_A_TXDESCRIPTOR_AAL5CRCRESIDUE_OFFSET 24
-
-/**
- * @def IX_NPE_A_TXDESCRIPTOR_SIZE
- *
- * @brief ATM Descriptor structure offset for Transmit Descriptor Size
- */
-#define IX_NPE_A_TXDESCRIPTOR_SIZE                  28
-
-/**
- * @def IX_NPE_A_CHAIN_DESC_COUNT_MAX
- *
- * @brief Maximum number of chained MBufs that can be chained together
- */
-#define IX_NPE_A_CHAIN_DESC_COUNT_MAX            256
-
-/*
- *  Definition of the ATM cell header
- *
- * This would most conviently be defined as the bit field shown below.
- * Endian portability prevents this, therefore a set of macros
- * are defined to access the fields within the cell header assumed to
- * be passed as a UINT32.
- *
- * Changes to field sizes or orders must be reflected in the offset
- * definitions above.
- *
- *    typedef struct
- *    {
- *       unsigned int gfc:4;
- *       unsigned int vpi:8;
- *       unsigned int vci:16;
- *       unsigned int pti:3;
- *       unsigned int clp:1;
- *    } IxNpeA_AtmCellHeader;
- *
- */
-
-/** Mask to acess GFC */
-#define GFC_MASK        0xf0000000
-
-/** return GFC from ATM cell header */
-#define IX_NPE_A_ATMCELLHEADER_GFC_GET( header ) \
-(((header) & GFC_MASK) >> 28)
-
-/** set GFC into ATM cell header */
-#define IX_NPE_A_ATMCELLHEADER_GFC_SET( header,gfc ) \
-do { \
-    (header) &= ~GFC_MASK; \
-    (header) |= (((gfc) << 28) & GFC_MASK); \
-} while(0)
-
-/** Mask to acess VPI */
-#define VPI_MASK        0x0ff00000
-
-/** return VPI from ATM cell header */
-#define IX_NPE_A_ATMCELLHEADER_VPI_GET( header ) \
-(((header) & VPI_MASK) >> 20)
-
-/** set VPI into ATM cell header */
-#define IX_NPE_A_ATMCELLHEADER_VPI_SET( header, vpi ) \
-do { \
-    (header) &= ~VPI_MASK; \
-    (header) |= (((vpi) << 20) & VPI_MASK); \
-} while(0)
-
-/** Mask to acess VCI */
-#define VCI_MASK        0x000ffff0
-
-/** return VCI from ATM cell header */
-#define IX_NPE_A_ATMCELLHEADER_VCI_GET( header ) \
-(((header) & VCI_MASK) >> 4)
-
-/** set VCI into ATM cell header */
-#define IX_NPE_A_ATMCELLHEADER_VCI_SET( header, vci ) \
-do { \
-    (header) &= ~VCI_MASK; \
-    (header) |= (((vci) << 4) & VCI_MASK); \
-} while(0)
-
-/** Mask to acess PTI */
-#define PTI_MASK        0x0000000e
-
-/** return PTI from ATM cell header */
-#define IX_NPE_A_ATMCELLHEADER_PTI_GET( header ) \
-(((header) & PTI_MASK) >> 1)
-
-/** set PTI into ATM cell header */
-#define IX_NPE_A_ATMCELLHEADER_PTI_SET( header, pti ) \
-do { \
-    (header) &= ~PTI_MASK; \
-    (header) |= (((pti) << 1) & PTI_MASK); \
-} while(0)
-
-/** Mask to acess CLP */
-#define CLP_MASK        0x00000001
-
-/** return CLP from ATM cell header */
-#define IX_NPE_A_ATMCELLHEADER_CLP_GET( header ) \
-((header) & CLP_MASK)
-
-/** set CLP into ATM cell header */
-#define IX_NPE_A_ATMCELLHEADER_CLP_SET( header, clp ) \
-do { \
-    (header) &= ~CLP_MASK; \
-    (header) |= ((clp) & CLP_MASK); \
-} while(0)
-
-
-/*
-* Definition of the Rx bitfield
-*
-* This would most conviently be defined as the bit field shown below.
-* Endian portability prevents this, therefore a set of macros
-* are defined to access the fields within the rxBitfield assumed to
-* be passed as a UINT32.
-*
-* Changes to field sizes or orders must be reflected in the offset
-* definitions above.
-*
-* Rx bitfield
-*    struct
-*    {   IX_NPEA_RXBITFIELD(
-*        unsigned int status:1,
-*        unsigned int port:7,
-*        unsigned int vcId:8,
-*        unsigned int currMbufSize:16);
-*    } rxBitField;
-*
-*/
-
-/** Mask to acess the rxBitField status */
-#define STATUS_MASK     0x80000000
-
-/** return the rxBitField status */
-#define IX_NPE_A_RXBITFIELD_STATUS_GET( rxbitfield ) \
-(((rxbitfield) & STATUS_MASK) >> 31)
-
-/** set the rxBitField status */
-#define IX_NPE_A_RXBITFIELD_STATUS_SET( rxbitfield, status ) \
-do { \
-    (rxbitfield) &= ~STATUS_MASK; \
-    (rxbitfield) |= (((status) << 31) & STATUS_MASK); \
-} while(0)
-
-/** Mask to acess the rxBitField port */
-#define PORT_MASK       0x7f000000
-
-/** return the rxBitField port */
-#define IX_NPE_A_RXBITFIELD_PORT_GET( rxbitfield ) \
-(((rxbitfield) & PORT_MASK) >> 24)
-
-/** set the rxBitField port */
-#define IX_NPE_A_RXBITFIELD_PORT_SET( rxbitfield, port ) \
-do { \
-    (rxbitfield) &= ~PORT_MASK; \
-    (rxbitfield) |= (((port) << 24) & PORT_MASK); \
-} while(0)
-
-/** Mask to acess the rxBitField vcId */
-#define VCID_MASK       0x00ff0000
-
-/** return the rxBitField vcId */
-#define IX_NPE_A_RXBITFIELD_VCID_GET( rxbitfield ) \
-(((rxbitfield) & VCID_MASK) >> 16)
-
-/** set the rxBitField vcId */
-#define IX_NPE_A_RXBITFIELD_VCID_SET( rxbitfield, vcid ) \
-do { \
-    (rxbitfield) &= ~VCID_MASK; \
-    (rxbitfield) |= (((vcid) << 16) & VCID_MASK); \
-} while(0)
-
-/** Mask to acess the rxBitField mbuf size */
-#define CURRMBUFSIZE_MASK       0x0000ffff
-
-/** return the rxBitField mbuf size */
-#define IX_NPE_A_RXBITFIELD_CURRMBUFSIZE_GET( rxbitfield ) \
-((rxbitfield) & CURRMBUFSIZE_MASK)
-
-/** set the rxBitField mbuf size */
-#define IX_NPE_A_RXBITFIELD_CURRMBUFSIZE_SET( rxbitfield, currmbufsize ) \
-do { \
-    (rxbitfield) &= ~CURRMBUFSIZE_MASK; \
-    (rxbitfield) |= ((currmbufsize) & CURRMBUFSIZE_MASK); \
-} while(0)
-
-
-
-/**
- * @brief Tx Descriptor definition
- */
-typedef struct
-{
-    UINT8 port;				/**< Tx Port number */
-    UINT8 aalType; 			/**< AAL Type */
-    UINT16 currMbufLen;			/**< mbuf length */
-    UINT32 atmCellHeader;		/**< ATM cell header */
-    IX_OSAL_MBUF *pCurrMbuf;	        /**< pointer to mbuf */
-    unsigned char *pCurrMbufData;	/**< Pointer to mbuf->dat */
-    IX_OSAL_MBUF *pNextMbuf;		/**< Pointer to next mbuf */
-    UINT32  totalLen;			/**< Total Length */
-    UINT32  aal5CrcResidue;		/**< AAL5 CRC Residue */
-} IxNpeA_TxAtmVc;
-
-/* Changes to field sizes or orders must be reflected in the offset
- * definitions above. */
-
-
-
-
-/**
- * @brief Rx Descriptor definition
- */
-typedef struct
-{
-    UINT32  rxBitField;			/**< Received bit field */
-    UINT32  atmCellHeader;		/**< ATM Cell Header */
-    UINT32  rsvdWord0;                  /**< Reserved field */
-    UINT16  currMbufLen;		/**< Mbuf Length */
-    UINT8   timeLimit; 			/**< Payload Reassembly timeLimit (used for aal0_xx only) */
-    UINT8   rsvdByte0;                  /**< Reserved field */ 
-    UINT32  rsvdWord1;   		/**< Reserved field */
-    IX_OSAL_MBUF *pCurrMbuf;		/**< Pointer to current mbuf */
-    unsigned char *pCurrMbufData;	/**< Pointer to current mbuf->data */
-    IX_OSAL_MBUF *pNextMbuf;		/**< Pointer to next mbuf */
-    UINT32  totalLen;			/**< Total Length */
-    UINT32  aal5CrcResidue;		/**< AAL5 CRC Residue */
-} IxNpeA_RxAtmVc;
-
-
-/**
- * @brief NPE-A AAL Type
- */
-typedef enum
-{
-    IX_NPE_A_AAL_TYPE_INVALID = 0,	/**< Invalid AAL type */
-    IX_NPE_A_AAL_TYPE_0_48    = 0x1,	/**< AAL0 - 48 byte */
-    IX_NPE_A_AAL_TYPE_0_52    = 0x2,	/**< AAL0 - 52 byte */
-    IX_NPE_A_AAL_TYPE_5       = 0x5,	/**< AAL5 */
-    IX_NPE_A_AAL_TYPE_OAM     = 0xF	/**< OAM */
-} IxNpeA_AalType;
-
-/**
- * @brief NPE-A Payload format 52-bytes & 48-bytes
- */
-typedef enum
-{
-    IX_NPE_A_52_BYTE_PAYLOAD = 0,	/**< 52 byte payload */
-    IX_NPE_A_48_BYTE_PAYLOAD		/**< 48 byte payload */
-} IxNpeA_PayloadFormat;
-
-/**
- * @brief  HSS Packetized NpePacket Descriptor Structure
- */
-typedef struct
-{
-    UINT8   status;		/**< Status of the packet passed to the client */
-    UINT8   errorCount;		/**< Number of errors */
-    UINT8   chainCount;		/**< Mbuf chain count e.g. 0 - No mbuf chain */
-    UINT8   rsvdByte0;		/**< Reserved byte to make the descriptor word align */
-
-    UINT16  packetLength;	/**< Packet Length */
-    UINT16  rsvdShort0;		/**< Reserved short to make the descriptor a word align */
-
-    IX_OSAL_MBUF *pRootMbuf;	/**< Pointer to Root mbuf */
-    IX_OSAL_MBUF *pNextMbuf;	/**< Pointer to next mbuf */
-    UINT8   *pMbufData;		/**< Pointer to the current mbuf->data */
-    UINT32  mbufLength;		/**< Current mbuf length */
-
-} IxNpeA_NpePacketDescriptor;
-
-
-#endif
-/**
- *@}
- */
-
-#endif /* __doxygen_HIDE */
diff --git a/drivers/net/npe/include/IxNpeDl.h b/drivers/net/npe/include/IxNpeDl.h
deleted file mode 100644
index f87ee4b840..0000000000
--- a/drivers/net/npe/include/IxNpeDl.h
+++ /dev/null
@@ -1,956 +0,0 @@
-/**
- * @file IxNpeDl.h
- *
- * @date 14 December 2001
-
- * @brief This file contains the public API of the IXP400 NPE Downloader
- *        component.
- *
- * 
- * @par
- * IXP400 SW Release version 2.0
- * 
- * -- Copyright Notice --
- * 
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- * 
- * @par
- * SPDX-License-Identifier:	BSD-3-Clause
- * @par
- * -- End of Copyright Notice --
-*/
-
-/**
- * @defgroup IxNpeDl IXP400 NPE-Downloader (IxNpeDl) API
- *
- * @brief The Public API for the IXP400 NPE Downloader
- *
- * @{
- */
-
-#ifndef IXNPEDL_H
-#define IXNPEDL_H
-
-/*
- * Put the user defined include files required
- */
-#include "IxOsalTypes.h"
-#include "IxNpeMicrocode.h"
-
-/*
- * #defines for function return types, etc.
- */
-
-/**
- * @def IX_NPEDL_PARAM_ERR
- *
- * @brief NpeDl function return value for a parameter error
- */
-#define IX_NPEDL_PARAM_ERR               2
-
-/**
- * @def IX_NPEDL_RESOURCE_ERR
- *
- * @brief NpeDl function return value for a resource error
- */
-#define IX_NPEDL_RESOURCE_ERR            3
-
-/**
- * @def IX_NPEDL_CRITICAL_NPE_ERR
- *
- * @brief NpeDl function return value for a Critical NPE error occuring during
-          download. Assume NPE is left in unstable condition if this value is
-          returned or NPE is hang / halt.
- */
-#define IX_NPEDL_CRITICAL_NPE_ERR        4
-
-/**
- * @def IX_NPEDL_CRITICAL_MICROCODE_ERR
- *
- * @brief NpeDl function return value for a Critical Microcode error
- *        discovered during download. Assume NPE is left in unstable condition
- *        if this value is returned.
- */
-#define IX_NPEDL_CRITICAL_MICROCODE_ERR  5
-
-/**
- * @def IX_NPEDL_DEVICE_ERR
- *
- * @brief NpeDl function return value when image being downloaded
- *        is not meant for the device in use
- */
-#define IX_NPEDL_DEVICE_ERR 6 
-
-/**
- * @defgroup NPEImageID IXP400 NPE Image ID Definition
- *
- * @ingroup IxNpeDl
- *
- * @brief Definition of NPE Image ID to be passed to ixNpeDlNpeInitAndStart()
- *        as input of type UINT32 which has the following fields format:
- *
- *               Field [Bit Location] <BR>
- *               -------------------- <BR>
- *               Device ID [31 - 28] <BR>
- *               NPE ID [27 - 24] <BR>
- *               NPE Functionality ID [23 - 16] <BR>
- *               Major Release Number [15 -  8] <BR>
- *               Minor Release Number [7 - 0] <BR>
- *
- *
- * @{
- */
-
-/**
- * @def IX_NPEDL_NPEIMAGE_FIELD_MASK
- *
- * @brief Mask for NPE Image ID's Field
- *
- * @warning <b>THIS #define HAS BEEN DEPRECATED AND SHOULD NOT BE USED.</b>
- *       It will be removed in a future release.
- *       See @ref ixNpeDlNpeInitAndStart for more information.
- */
-#define IX_NPEDL_NPEIMAGE_FIELD_MASK  0xff
-
-/**
- * @def IX_NPEDL_NPEIMAGE_NPEID_MASK
- *
- * @brief Mask for NPE Image NPE ID's Field
- *
- */
-#define IX_NPEDL_NPEIMAGE_NPEID_MASK  0xf
-
-/**
- * @def IX_NPEDL_NPEIMAGE_DEVICEID_MASK
- *
- * @brief Mask for NPE Image Device ID's Field
- *
- */
-#define IX_NPEDL_NPEIMAGE_DEVICEID_MASK  0xf
-
-/**
- * @def IX_NPEDL_NPEIMAGE_BIT_LOC_NPEID
- *
- * @brief Location of NPE ID field in term of bit.
- *
- * @warning <b>THIS #define HAS BEEN DEPRECATED AND SHOULD NOT BE USED.</b>
- *       It will be removed in a future release.
- *       See @ref ixNpeDlNpeInitAndStart for more information.
- */
-#define IX_NPEDL_NPEIMAGE_BIT_LOC_NPEID  24
-
-/**
- * @def IX_NPEDL_NPEIMAGE_BIT_LOC_FUNCTIONALITYID
- *
- * @brief Location of Functionality ID field in term of bit.
- *
- * @warning <b>THIS #define HAS BEEN DEPRECATED AND SHOULD NOT BE USED.</b>
- *       It will be removed in a future release.
- *       See @ref ixNpeDlNpeInitAndStart for more information.
- */
-#define IX_NPEDL_NPEIMAGE_BIT_LOC_FUNCTIONALITYID  16
-
-/**
- * @def IX_NPEDL_NPEIMAGE_BIT_LOC_MAJOR
- *
- * @brief Location of Major Release Number field in term of bit.
- *
- * @warning <b>THIS #define HAS BEEN DEPRECATED AND SHOULD NOT BE USED.</b>
- *       It will be removed in a future release.
- *       See @ref ixNpeDlNpeInitAndStart for more information.
- */
-#define IX_NPEDL_NPEIMAGE_BIT_LOC_MAJOR  8
-
-/**
- * @def IX_NPEDL_NPEIMAGE_BIT_LOC_MINOR
- *
- * @brief Location of Minor Release Number field in term of bit.
- *
- * @warning <b>THIS #define HAS BEEN DEPRECATED AND SHOULD NOT BE USED.</b>
- *       It will be removed in a future release.
- *       See @ref ixNpeDlNpeInitAndStart for more information.
- */
-#define IX_NPEDL_NPEIMAGE_BIT_LOC_MINOR  0
-
-/**
- * @} addtogroup NPEImageID
- */
-
-/**
- * @def ixNpeDlMicrocodeImageOverride(x)
- *
- * @brief  Map old terminology that uses term "image" to new term
- *        "image library"
- *
- * @warning <b>THIS #define HAS BEEN DEPRECATED AND SHOULD NOT BE USED.</b>
- *       It will be removed in a future release.
- *       See @ref ixNpeDlNpeInitAndStart for more information.
- */
-#define ixNpeDlMicrocodeImageOverride(x) ixNpeDlMicrocodeImageLibraryOverride(x)
-
-/**
- * @def IxNpeDlVersionId
- *
- * @brief  Map old terminology that uses term "version" to new term
- *        "image"
- *
- * @warning <b>THIS #define HAS BEEN DEPRECATED AND SHOULD NOT BE USED.</b>
- *       It will be removed in a future release.
- *       See @ref ixNpeDlNpeInitAndStart for more information.
- */
-#define IxNpeDlVersionId IxNpeDlImageId
-
-/**
- * @def ixNpeDlVersionDownload
- *
- * @brief  Map old terminology that uses term "version" to new term
- *        "image"
- *
- * @warning <b>THIS #define HAS BEEN DEPRECATED AND SHOULD NOT BE USED.</b>
- *       It will be removed in a future release.
- *       See @ref ixNpeDlNpeInitAndStart for more information.
- */
-#define ixNpeDlVersionDownload(x,y) ixNpeDlImageDownload(x,y)
-
-/**
- * @def ixNpeDlAvailableVersionsCountGet
- *
- * @brief  Map old terminology that uses term "version" to new term
- *        "image"
- *
- * @warning <b>THIS #define HAS BEEN DEPRECATED AND SHOULD NOT BE USED.</b>
- *       It will be removed in a future release.
- *       See @ref ixNpeDlNpeInitAndStart for more information.
- */
-#define ixNpeDlAvailableVersionsCountGet(x) ixNpeDlAvailableImagesCountGet(x)
-
-/**
- * @def ixNpeDlAvailableVersionsListGet
- *
- * @brief  Map old terminology that uses term "version" to new term
- *        "image"
- *
- * @warning <b>THIS #define HAS BEEN DEPRECATED AND SHOULD NOT BE USED.</b>
- *       It will be removed in a future release.
- *       See @ref ixNpeDlNpeInitAndStart for more information.
- */
-#define ixNpeDlAvailableVersionsListGet(x,y) ixNpeDlAvailableImagesListGet(x,y)
-
- /**
- * @def ixNpeDlLoadedVersionGet
- *
- * @brief  Map old terminology that uses term "version" to new term
- *        "image"
- *
- * @warning <b>THIS #define HAS BEEN DEPRECATED AND SHOULD NOT BE USED.</b>
- *       It will be removed in a future release.
- *       See @ref ixNpeDlNpeInitAndStart for more information.
- */
-#define ixNpeDlLoadedVersionGet(x,y) ixNpeDlLoadedImageGet(x,y)
-
- /**
- * @def clientImage
- *
- * @brief  Map old terminology that uses term "image" to new term
- *        "image library"
- *
- * @warning <b>THIS #define HAS BEEN DEPRECATED AND SHOULD NOT BE USED.</b>
- *       It will be removed in a future release.
- *       See @ref ixNpeDlNpeInitAndStart for more information.
- */
-#define clientImage clientImageLibrary
-
- /**
- * @def versionIdPtr
- *
- * @brief  Map old terminology that uses term "version" to new term
- *        "image"
- *
- * @warning <b>THIS #define HAS BEEN DEPRECATED AND SHOULD NOT BE USED.</b>
- *       It will be removed in a future release.
- *       See @ref ixNpeDlNpeInitAndStart for more information.
- */
-#define versionIdPtr imageIdPtr
-
- /**
- * @def numVersionsPtr
- *
- * @brief  Map old terminology that uses term "version" to new term
- *        "image"
- *
- * @warning <b>THIS #define HAS BEEN DEPRECATED AND SHOULD NOT BE USED.</b>
- *       It will be removed in a future release.
- *       See @ref ixNpeDlNpeInitAndStart for more information.
- */
-#define numVersionsPtr numImagesPtr
-
-/**
- * @def versionIdListPtr
- *
- * @brief  Map old terminology that uses term "version" to new term
- *        "image"
- *
- * @warning <b>THIS #define HAS BEEN DEPRECATED AND SHOULD NOT BE USED.</b>
- *       It will be removed in a future release.
- *       See @ref ixNpeDlNpeInitAndStart for more information.
- */
-#define versionIdListPtr imageIdListPtr
-
-/**
- * @def IxNpeDlBuildId
- *
- * @brief  Map old terminology that uses term "buildId" to new term
- *        "functionalityId"
- *
- * @warning <b>THIS #define HAS BEEN DEPRECATED AND SHOULD NOT BE USED.</b>
- *       It will be removed in a future release.
- *       See @ref ixNpeDlNpeInitAndStart for more information.
- */
-#define IxNpeDlBuildId IxNpeDlFunctionalityId
-
-/**
- * @def buildId
- *
- * @brief  Map old terminology that uses term "buildId" to new term
- *        "functionalityId"
- *
- * @warning <b>THIS #define HAS BEEN DEPRECATED AND SHOULD NOT BE USED.</b>
- *       It will be removed in a future release.
- *       See @ref ixNpeDlNpeInitAndStart for more information.
- */
-#define buildId functionalityId
-
-/**
- * @def IX_NPEDL_MicrocodeImage
- *
- * @brief  Map old terminology that uses term "image" to new term
- *        "image library"
- *
- * @warning <b>THIS #define HAS BEEN DEPRECATED AND SHOULD NOT BE USED.</b>
- *       It will be removed in a future release.
- *       See @ref ixNpeDlNpeInitAndStart for more information.
- */
-#define IX_NPEDL_MicrocodeImage IX_NPEDL_MicrocodeImageLibrary
-
-/*
- * Typedefs
- */
-
-/**
- * @typedef IxNpeDlFunctionalityId
- * @brief Used to make up Functionality ID field of Image Id
- *
- * @warning <b>THIS typedef HAS BEEN DEPRECATED AND SHOULD NOT BE USED.</b>
- *       It will be removed in a future release.
- *       See @ref ixNpeDlNpeInitAndStart for more information.
- */
-typedef UINT8 IxNpeDlFunctionalityId;
-
-/**
- * @typedef IxNpeDlMajor
- * @brief Used to make up Major Release field of Image Id
- *
- * @warning <b>THIS typedef HAS BEEN DEPRECATED AND SHOULD NOT BE USED.</b>
- *       It will be removed in a future release.
- *       See @ref ixNpeDlNpeInitAndStart for more information.
- */
-typedef UINT8 IxNpeDlMajor;
-
-/**
- * @typedef IxNpeDlMinor
- * @brief Used to make up Minor Revision field of Image Id
- *
- * @warning <b>THIS typedef HAS BEEN DEPRECATED AND SHOULD NOT BE USED.</b>
- *       It will be removed in a future release.
- *       See @ref ixNpeDlNpeInitAndStart for more information.
- */
-typedef UINT8 IxNpeDlMinor;
-
-/*
- * Enums
- */
-
-/**
- * @brief NpeId numbers to identify NPE A, B or C
- * @note In this context, for IXP425 Silicon (B0):<br>
- *      - NPE-A has HDLC, HSS, AAL and UTOPIA Coprocessors.<br>
- *      - NPE-B has Ethernet Coprocessor.<br>
- *      - NPE-C has Ethernet, AES, DES and HASH Coprocessors.<br>
- *      - IXP400 Product Line have different combinations of coprocessors.
- */
-typedef enum
-{
-  IX_NPEDL_NPEID_NPEA = 0,    /**< Identifies NPE A */
-  IX_NPEDL_NPEID_NPEB,        /**< Identifies NPE B */
-  IX_NPEDL_NPEID_NPEC,        /**< Identifies NPE C */
-  IX_NPEDL_NPEID_MAX          /**< Total Number of NPEs */
-} IxNpeDlNpeId;
-
-/*
- * Structs
- */
-
-/**
- * @brief Image Id to identify each image contained in an image library
- *
- * @warning <b>THIS struct HAS BEEN DEPRECATED AND SHOULD NOT BE USED.</b>
- *       It will be removed in a future release.
- *       See @ref ixNpeDlNpeInitAndStart for more information.
- */
-typedef struct
-{
-    IxNpeDlNpeId   npeId;   /**< NPE ID */
-    IxNpeDlFunctionalityId functionalityId; /**< Build ID indicates functionality of image */
-    IxNpeDlMajor   major;   /**< Major Release Number */
-    IxNpeDlMinor   minor;   /**< Minor Revision Number */
-} IxNpeDlImageId;
-
-/*
- * Prototypes for interface functions
- */
-
-/**
- * @ingroup IxNpeDl
- *
- * @fn PUBLIC IX_STATUS ixNpeDlNpeInitAndStart (UINT32 imageId)
- *
- * @brief Stop, reset, download microcode (firmware) and finally start NPE.
- *
- * @param imageId UINT32 [in] - Id of the microcode image to download.
- *
- * This function locates the image specified by the <i>imageId</i> parameter
- * from the default microcode image library which is included internally by
- * this component.
- * It then stops and resets the NPE, loads the firmware image onto the NPE,
- * and then restarts the NPE.
- *
- * @note A list of valid image IDs is included in this header file.
- *       See #defines with prefix IX_NPEDL_NPEIMAGE_...
- *
- * @note This function, along with @ref ixNpeDlCustomImageNpeInitAndStart
- *       and @ref ixNpeDlLoadedImageFunctionalityGet, supercedes the following
- *       functions which are deprecated and will be removed completely in a
- *       future release:
- *       - @ref ixNpeDlImageDownload
- *       - @ref ixNpeDlAvailableImagesCountGet
- *       - @ref ixNpeDlAvailableImagesListGet
- *       - @ref ixNpeDlLatestImageGet
- *       - @ref ixNpeDlLoadedImageGet
- *       - @ref ixNpeDlMicrocodeImageLibraryOverride
- *       - @ref ixNpeDlNpeExecutionStop
- *       - @ref ixNpeDlNpeStopAndReset
- *       - @ref ixNpeDlNpeExecutionStart
- *
- * @pre
- *         - The Client is responsible for ensuring mutual access to the NPE.
- * @post
- *         - The NPE Instruction Pipeline will be cleared if State Information
- *           has been downloaded.
- *         - If the download fails with a critical error, the NPE may
- *           be left in an ususable state.
- * @return
- *         - IX_SUCCESS if the download was successful;
- *         - IX_NPEDL_PARAM_ERR if a parameter error occured
- *         - IX_NPEDL_CRITICAL_NPE_ERR if a critical NPE error occured during
- *           download
- *         - IX_NPEDL_CRITICAL_MICROCODE_ERR if a critical microcode error
- *           occured during download
- *         - IX_NPEDL_DEVICE_ERR if the image being loaded is not meant for 
- *           the device currently running.
- *         - IX_FAIL if NPE is not available or image is failed to be located.
- *           A warning is issued if the NPE is not present.
- */
-PUBLIC IX_STATUS
-ixNpeDlNpeInitAndStart (UINT32 npeImageId);
-
-/**
- * @ingroup IxNpeDl
- *
- * @fn PUBLIC IX_STATUS ixNpeDlCustomImageNpeInitAndStart (UINT32 *imageLibrary,
-                                                           UINT32 imageId)
- *
- * @brief Stop, reset, download microcode (firmware) and finally start NPE
- *
- * @param imageId UINT32 [in] - Id of the microcode image to download.
- *
- * This function locates the image specified by the <i>imageId</i> parameter
- * from the specified microcode image library which is pointed to by the
- * <i>imageLibrary</i> parameter.
- * It then stops and resets the NPE, loads the firmware image onto the NPE,
- * and then restarts the NPE.
- *
- * This is a facility for users who wish to use an image from an external
- * library of NPE firmware images.  To use a standard image from the
- * built-in library, see @ref ixNpeDlNpeInitAndStart instead.
- *
- * @note A list of valid image IDs is included in this header file.
- *       See #defines with prefix IX_NPEDL_NPEIMAGE_...
- *
- * @note This function, along with @ref ixNpeDlNpeInitAndStart
- *       and @ref ixNpeDlLoadedImageFunctionalityGet, supercedes the following
- *       functions which are deprecated and will be removed completely in a
- *       future release:
- *       - @ref ixNpeDlImageDownload
- *       - @ref ixNpeDlAvailableImagesCountGet
- *       - @ref ixNpeDlAvailableImagesListGet
- *       - @ref ixNpeDlLatestImageGet
- *       - @ref ixNpeDlLoadedImageGet
- *       - @ref ixNpeDlMicrocodeImageLibraryOverride
- *       - @ref ixNpeDlNpeExecutionStop
- *       - @ref ixNpeDlNpeStopAndReset
- *       - @ref ixNpeDlNpeExecutionStart
- *
- * @pre
- *         - The Client is responsible for ensuring mutual access to the NPE.
- *         - The image library supplied must be in the correct format for use
- *           by the NPE Downloader (IxNpeDl) component.  Details of the library
- *           format are contained in the Functional Specification document for
- *           IxNpeDl.
- * @post
- *         - The NPE Instruction Pipeline will be cleared if State Information
- *           has been downloaded.
- *         - If the download fails with a critical error, the NPE may
- *           be left in an ususable state.
- * @return
- *         - IX_SUCCESS if the download was successful;
- *         - IX_NPEDL_PARAM_ERR if a parameter error occured
- *         - IX_NPEDL_CRITICAL_NPE_ERR if a critical NPE error occured during
- *           download
- *         - IX_NPEDL_CRITICAL_MICROCODE_ERR if a critical microcode error
- *           occured during download
- *         - IX_NPEDL_DEVICE_ERR if the image being loaded is not meant for 
- *           the device currently running.
- *         - IX_FAIL if NPE is not available or image is failed to be located.
- *           A warning is issued if the NPE is not present.
- */
-PUBLIC IX_STATUS
-ixNpeDlCustomImageNpeInitAndStart (UINT32 *imageLibrary,
-                    UINT32 npeImageId);
-
-
-/**
- * @ingroup IxNpeDl
- *
- * @fn PUBLIC IX_STATUS ixNpeDlLoadedImageFunctionalityGet (IxNpeDlNpeId npeId,
-                                                        UINT8 *functionalityId)
- *
- * @brief Gets the functionality of the image last loaded on a particular NPE
- *
- * @param npeId  @ref IxNpeDlNpeId [in]      - Id of the target NPE.
- * @param functionalityId UINT8* [out] - the functionality ID of the image
- *                                       last loaded on the NPE.
- *
- * This function retrieves the functionality ID of the image most recently
- * downloaded successfully to the specified NPE.  If the NPE does not contain
- * a valid image, this function returns a FAIL status.
- *
- * @warning This function is not intended for general use, as a knowledge of
- * how to interpret the functionality ID is required.  As such, this function
- * should only be used by other Access Layer components of the IXP400 Software
- * Release.
- *
- * @pre
- *
- * @post
- *
- * @return
- *     -  IX_SUCCESS if the operation was successful
- *     -  IX_NPEDL_PARAM_ERR if a parameter error occured
- *     -  IX_FAIL if the NPE does not have a valid image loaded
- */
-PUBLIC IX_STATUS
-ixNpeDlLoadedImageFunctionalityGet (IxNpeDlNpeId npeId,
-                                    UINT8 *functionalityId);
-
-
-/**
- * @ingroup IxNpeDl
- *
- * @fn IX_STATUS ixNpeDlMicrocodeImageLibraryOverride (UINT32 *clientImageLibrary)
- *
- * @brief This instructs NPE Downloader to use client-supplied microcode image library.
- *
- * @param clientImageLibrary UINT32* [in]  - Pointer to the client-supplied
- *                                   NPE microcode image library
- *
- * This function sets NPE Downloader to use a client-supplied microcode image library
- * instead of the standard image library which is included by the NPE Downloader.
- * <b>This function is provided mainly for increased testability and should not
- * be used in normal circumstances.</b> When not used, NPE Downloader will use
- * a "built-in" image library, local to this component, which should always contain the
- * latest microcode for the NPEs.
- *
- * @warning <b>THIS FUNCTION HAS BEEN DEPRECATED AND SHOULD NOT BE USED.</b>
- *       It will be removed in a future release.
- *       See @ref ixNpeDlCustomImageNpeInitAndStart.
- *
- * @pre
- *      - <i>clientImageLibrary</i> should point to a microcode image library valid for use
- *        by the NPE Downloader component.
- *
- * @post
- *      - the client-supplied image library will be used for all subsequent operations
- *        performed by the NPE Downloader
- *
- * @return
- *      - IX_SUCCESS if the operation was successful
- *      - IX_NPEDL_PARAM_ERR if a parameter error occured
- *      - IX_FAIL if the client-supplied image library did not contain a valid signature
- */
-PUBLIC IX_STATUS
-ixNpeDlMicrocodeImageLibraryOverride (UINT32 *clientImageLibrary);
-
-/**
- * @ingroup IxNpeDl
- *
- * @fn PUBLIC IX_STATUS ixNpeDlImageDownload (IxNpeDlImageId *imageIdPtr,
-                                                BOOL verify)
- *
- * @brief Stop, reset, download microcode and finally start NPE.
- *
- * @param imageIdPtr @ref IxNpeDlImageId* [in] - Pointer to Id of the microcode
- *                                              image to download.
- * @param verify BOOL [in]     - ON/OFF option to verify the download. If ON
- *                               (verify == true), the Downloader will read back
- *                               each word written to the NPE registers to
- *                               ensure the download operation was successful.
- *
- * Using the <i>imageIdPtr</i>, this function locates a particular image of
- * microcode in the microcode image library in memory, and downloads the microcode
- * to a particular NPE.
- *
- * @warning <b>THIS FUNCTION HAS BEEN DEPRECATED AND SHOULD NOT BE USED.</b>
- *       It will be removed in a future release.
- *       See @ref ixNpeDlNpeInitAndStart and @ref ixNpeDlCustomImageNpeInitAndStart.
- *
- * @pre
- *         - The Client is responsible for ensuring mutual access to the NPE.
- *       - The Client should use ixNpeDlLatestImageGet() to obtain the latest
- *         version of the image before attempting download.
- * @post
- *         - The NPE Instruction Pipeline will be cleared if State Information
- *           has been downloaded.
- *         - If the download fails with a critical error, the NPE may
- *           be left in an ususable state.
- * @return
- *         - IX_SUCCESS if the download was successful;
- *         - IX_NPEDL_PARAM_ERR if a parameter error occured
- *         - IX_NPEDL_CRITICAL_NPE_ERR if a critical NPE error occured during
- *           download
- *         - IX_PARAM_CRITICAL_MICROCODE_ERR if a critical microcode error
- *           occured during download
- *         - IX_FAIL if NPE is not available or image is failed to be located.
- *           A warning is issued if the NPE is not present.
- */
-PUBLIC IX_STATUS
-ixNpeDlImageDownload (IxNpeDlImageId *imageIdPtr,
-            BOOL verify);
-
-/**
- * @ingroup IxNpeDl
- *
- * @fn PUBLIC IX_STATUS ixNpeDlAvailableImagesCountGet (UINT32 *numImagesPtr)
- *
- * @brief Get the number of Images available in a microcode image library
- *
- * @param numImagesPtr UINT32* [out] - A pointer to the number of images in
- *                                       the image library.
- *
- * Gets the number of images available in the microcode image library.
- * Then returns this in a variable pointed to by <i>numImagesPtr</i>.
- *
- * @warning <b>THIS FUNCTION HAS BEEN DEPRECATED AND SHOULD NOT BE USED.</b>
- *       It will be removed in a future release.
- *       See @ref ixNpeDlNpeInitAndStart and @ref ixNpeDlCustomImageNpeInitAndStart.
- *
- * @pre
- *     - The Client should declare the variable to which numImagesPtr points
- *
- * @post
- *
- * @return
- *     - IX_SUCCESS if the operation was successful
- *     - IX_NPEDL_PARAM_ERR if a parameter error occured
- *     - IX_FAIL otherwise
- */
-PUBLIC IX_STATUS
-ixNpeDlAvailableImagesCountGet (UINT32 *numImagesPtr);
-
-/**
- * @ingroup IxNpeDl
- *
- * @fn PUBLIC IX_STATUS ixNpeDlAvailableImagesListGet (IxNpeDlImageId *imageIdListPtr,
-                                                         UINT32 *listSizePtr)
- *
- * @brief Get a list of the images available in a microcode image library
- *
- * @param imageIdListPtr @ref IxNpeDlImageId* [out] - Array to contain list of
- *                                                   image Ids (memory
- *                                                   allocated by Client).
- * @param listSizePtr UINT32* [inout]  - As an input, this param should point
- *                                       to the max number of Ids the
- *                                       <i>imageIdListPtr</i> array can
- *                                       hold. NpeDl will replace the input
- *                                       value of this parameter with the
- *                                       number of image Ids actually filled
- *                                       into the array before returning.
- *
- * Finds list of images available in the microcode image library.
- * Fills these into the array pointed to by <i>imageIdListPtr</i>
- *
- * @warning <b>THIS FUNCTION HAS BEEN DEPRECATED AND SHOULD NOT BE USED.</b>
- *       It will be removed in a future release.
- *       See @ref ixNpeDlNpeInitAndStart and @ref ixNpeDlCustomImageNpeInitAndStart.
- *
- * @pre
- *     - The Client should declare the variable to which numImagesPtr points
- *     - The Client should create an array (<i>imageIdListPtr</i>) large
- *       enough to contain all the image Ids in the image library
- *
- * @post
- *
- * @return
- *     - IX_SUCCESS if the operation was successful
- *     - IX_NPEDL_PARAM_ERR if a parameter error occured
- *     - IX_FAIL otherwise
- */
-PUBLIC IX_STATUS
-ixNpeDlAvailableImagesListGet (IxNpeDlImageId *imageIdListPtr,
-                 UINT32 *listSizePtr);
-
-/**
- * @ingroup IxNpeDl
- *
- * @fn PUBLIC IX_STATUS ixNpeDlLoadedImageGet (IxNpeDlNpeId npeId,
-                                                IxNpeDlImageId *imageIdPtr)
- *
- * @brief Gets the Id of the image currently loaded on a particular NPE
- *
- * @param npeId @ref IxNpeDlNpeId [in]              - Id of the target NPE.
- * @param imageIdPtr @ref IxNpeDlImageId* [out]     - Pointer to the where the
- *                                               image id should be stored.
- *
- * If an image of microcode was previously downloaded successfully to the NPE
- * by NPE Downloader, this function returns in <i>imageIdPtr</i> the image
- * Id of that image loaded on the NPE.
- *
- * @pre
- *     - The Client has allocated memory to the <i>imageIdPtr</i> pointer.
- *
- * @post
- *
- * @return
- *     -  IX_SUCCESS if the operation was successful
- *     -  IX_NPEDL_PARAM_ERR if a parameter error occured
- *     -  IX_FAIL if the NPE doesn't currently have a image loaded
- */
-PUBLIC IX_STATUS
-ixNpeDlLoadedImageGet (IxNpeDlNpeId npeId,
-             IxNpeDlImageId *imageIdPtr);
-
-/**
- * @fn PUBLIC IX_STATUS ixNpeDlLatestImageGet (IxNpeDlNpeId npeId, IxNpeDlFunctionalityId
-                                        functionalityId, IxNpeDlImageId *imageIdPtr)
- *
- * @brief This instructs NPE Downloader to get Id of the latest version for an
- * image that is specified by the client.
- *
- * @param npeId @ref IxNpeDlNpeId [in]                    - Id of the target NPE.
- * @param functionalityId @ref IxNpeDlFunctionalityId [in]    - functionality of the image
- * @param imageIdPtr @ref IxNpeDlImageId* [out]               - Pointer to the where the
- *                                                         image id should be stored.
- *
- * This function sets NPE Downloader to return the id of the latest version for
- * image.  The user will select the image by providing a particular NPE
- * (specifying <i>npeId</i>) with particular functionality (specifying
- * <i>FunctionalityId</i>). The most recent version available as determined by the
- * highest Major and Minor revision numbers is returned in <i>imageIdPtr</i>.
- *
- * @warning <b>THIS FUNCTION HAS BEEN DEPRECATED AND SHOULD NOT BE USED.</b>
- *       It will be removed in a future release.
- *       See @ref ixNpeDlNpeInitAndStart and @ref ixNpeDlCustomImageNpeInitAndStart.
- *
- * @return
- *      - IX_SUCCESS if the operation was successful
- *      - IX_NPEDL_PARAM_ERR if a parameter error occured
- *      - IX_FAIL otherwise
- */
-PUBLIC IX_STATUS
-ixNpeDlLatestImageGet (IxNpeDlNpeId npeId,
-             IxNpeDlFunctionalityId functionalityId,
-                    IxNpeDlImageId *imageIdPtr);
-
-/**
- * @ingroup IxNpeDl
- *
- * @fn PUBLIC IX_STATUS ixNpeDlNpeStopAndReset (IxNpeDlNpeId npeId)
- *
- * @brief Stops and Resets an NPE
- *
- * @param npeId @ref IxNpeDlNpeId [in] - Id of the target NPE.
- *
- * This function performs a soft NPE reset by writing reset values to
- * particular NPE registers. Note that this does not reset NPE co-processors.
- * This implicitly stops NPE code execution before resetting the NPE.
- *
- * @note It is no longer necessary to call this function before downloading
- * a new image to the NPE.  It is left on the API only to allow greater control
- * of NPE execution if required.  Where appropriate, use @ref ixNpeDlNpeInitAndStart
- * or @ref ixNpeDlCustomImageNpeInitAndStart instead.
- *
- * @warning <b>THIS FUNCTION HAS BEEN DEPRECATED AND SHOULD NOT BE USED.</b>
- *       It will be removed in a future release.
- *       See @ref ixNpeDlNpeInitAndStart and @ref ixNpeDlCustomImageNpeInitAndStart.
- *
- * @pre
- *     - The Client is responsible for ensuring mutual access to the NPE.
- *
- * @post
- *
- * @return
- *      - IX_SUCCESS if the operation was successful
- *      - IX_NPEDL_PARAM_ERR if a parameter error occured
- *      - IX_FAIL otherwise
- *      - IX_NPEDL_CRITICAL_NPE_ERR failed to reset NPE due to timeout error. 
- *        Timeout error could happen if NPE hang
- */
-PUBLIC IX_STATUS
-ixNpeDlNpeStopAndReset (IxNpeDlNpeId npeId);
-
-/**
- * @ingroup IxNpeDl
- *
- * @fn PUBLIC IX_STATUS ixNpeDlNpeExecutionStart (IxNpeDlNpeId npeId)
- *
- * @brief Starts code execution on a NPE
- *
- * @param npeId @ref IxNpeDlNpeId [in] - Id of the target NPE
- *
- * Starts execution of code on a particular NPE.  A client would typically use
- * this after a download to NPE is performed, to start/restart code execution
- * on the NPE.
- *
- * @note It is no longer necessary to call this function after downloading
- * a new image to the NPE.  It is left on the API only to allow greater control
- * of NPE execution if required.  Where appropriate, use @ref ixNpeDlNpeInitAndStart
- * or @ref ixNpeDlCustomImageNpeInitAndStart instead.
- *
- * @warning <b>THIS FUNCTION HAS BEEN DEPRECATED AND SHOULD NOT BE USED.</b>
- *       It will be removed in a future release.
- *       See @ref ixNpeDlNpeInitAndStart and @ref ixNpeDlCustomImageNpeInitAndStart.
- *
- * @pre
- *     - The Client is responsible for ensuring mutual access to the NPE.
- *     - Note that this function does not set the NPE Next Program Counter
- *       (NextPC), so it should be set beforehand if required by downloading
- *       appropriate State Information (using ixNpeDlVersionDownload()).
- *
- * @post
- *
- * @return
- *      - IX_SUCCESS if the operation was successful
- *      - IX_NPEDL_PARAM_ERR if a parameter error occured
- *      - IX_FAIL otherwise
- */
-PUBLIC IX_STATUS
-ixNpeDlNpeExecutionStart (IxNpeDlNpeId npeId);
-
-/**
- * @ingroup IxNpeDl
- *
- * @fn PUBLIC IX_STATUS ixNpeDlNpeExecutionStop (IxNpeDlNpeId npeId)
- *
- * @brief Stops code execution on a NPE
- *
- * @param npeId @ref IxNpeDlNpeId [in] - Id of the target NPE
- *
- * Stops execution of code on a particular NPE.  This would typically be used
- * by a client before a download to NPE is performed, to stop code execution on
- * an NPE, unless ixNpeDlNpeStopAndReset() is used instead.  Unlike
- * ixNpeDlNpeStopAndReset(), this function only halts the NPE and leaves
- * all registers and settings intact. This is useful, for example, between
- * stages of a multi-stage download, to stop the NPE prior to downloading the
- * next image while leaving the current state of the NPE intact..
- *
- * @warning <b>THIS FUNCTION HAS BEEN DEPRECATED AND SHOULD NOT BE USED.</b>
- *       It will be removed in a future release.
- *       See @ref ixNpeDlNpeInitAndStart and @ref ixNpeDlCustomImageNpeInitAndStart.
- *
- * @pre
- *     - The Client is responsible for ensuring mutual access to the NPE.
- *
- * @post
- *
- * @return
- *      - IX_SUCCESS if the operation was successful
- *      - IX_NPEDL_PARAM_ERR if a parameter error occured
- *      - IX_FAIL otherwise
- */
-PUBLIC IX_STATUS
-ixNpeDlNpeExecutionStop (IxNpeDlNpeId npeId);
-
-/**
- * @ingroup IxNpeDl
- *
- * @fn PUBLIC IX_STATUS ixNpeDlUnload (void)
- *
- * @brief This function will uninitialise the IxNpeDl component.
- *
- * This function will uninitialise the IxNpeDl component.  It should only be
- * called once, and only if the IxNpeDl component has already been initialised by
- * calling any of the following functions:
- * - @ref ixNpeDlNpeInitAndStart
- * - @ref ixNpeDlCustomImageNpeInitAndStart
- * - @ref ixNpeDlImageDownload     (deprecated)
- * - @ref ixNpeDlNpeStopAndReset   (deprecated)
- * - @ref ixNpeDlNpeExecutionStop  (deprecated)
- * - @ref ixNpeDlNpeExecutionStart (deprecated)
- *
- * If possible, this function should be called before a soft reboot or unloading
- * a kernel module to perform any clean up operations required for IxNpeDl.
- *
- * The following actions will be performed by this function:
- * - Unmapping of any kernel memory mapped by IxNpeDl
- *
- * @return
- *      - IX_SUCCESS if the operation was successful
- *      - IX_FAIL otherwise
- */
-
-PUBLIC IX_STATUS 
-ixNpeDlUnload (void);
-
-/**
- * @ingroup IxNpeDl
- *
- * @fn PUBLIC void ixNpeDlStatsShow (void)
- *
- * @brief This function will display run-time statistics from the IxNpeDl
- *        component
- *
- * @return none
- */
-PUBLIC void
-ixNpeDlStatsShow (void);
-
-/**
- * @ingroup IxNpeDl
- *
- * @fn PUBLIC void ixNpeDlStatsReset (void)
- *
- * @brief This function will reset the statistics of the IxNpeDl component
- *
- * @return none
- */
-PUBLIC void
-ixNpeDlStatsReset (void);
-
-#endif /* IXNPEDL_H */
-
-/**
- * @} defgroup IxNpeDl
- */
-
-
diff --git a/drivers/net/npe/include/IxNpeDlImageMgr_p.h b/drivers/net/npe/include/IxNpeDlImageMgr_p.h
deleted file mode 100644
index 34dd3a441c..0000000000
--- a/drivers/net/npe/include/IxNpeDlImageMgr_p.h
+++ /dev/null
@@ -1,339 +0,0 @@
-/**
- * @file IxNpeDlImageMgr_p.h
- *
- * @author Intel Corporation
- * @date 14 December 2001
-
- * @brief This file contains the private API for the ImageMgr module
- *
- * 
- * @par
- * IXP400 SW Release version 2.0
- * 
- * -- Copyright Notice --
- * 
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- * 
- * @par
- * SPDX-License-Identifier:	BSD-3-Clause
- * @par
- * -- End of Copyright Notice --
-*/
-
-/**
- * @defgroup IxNpeDlImageMgr_p IxNpeDlImageMgr_p
- *
- * @brief The private API for the IxNpeDl ImageMgr module
- * 
- * @{
- */
-
-#ifndef IXNPEDLIMAGEMGR_P_H
-#define IXNPEDLIMAGEMGR_P_H
-
-
-/*
- * Put the user defined include files required.
- */
-#include "IxNpeDl.h"
-#include "IxOsalTypes.h"
-
-
-/*
- * #defines and macros
- */
-
-/**
- * @def IX_NPEDL_IMAGEMGR_SIGNATURE
- *
- * @brief Signature found as 1st word in a microcode image library
- */
-#define IX_NPEDL_IMAGEMGR_SIGNATURE      0xDEADBEEF
-
-/**
- * @def IX_NPEDL_IMAGEMGR_END_OF_HEADER
- *
- * @brief Marks end of header in a microcode image library
- */
-#define IX_NPEDL_IMAGEMGR_END_OF_HEADER  0xFFFFFFFF
-
-/**
- * @def IX_NPEDL_IMAGEID_NPEID_OFFSET
- *
- * @brief Offset from LSB of NPE ID field in Image ID
- */
-#define IX_NPEDL_IMAGEID_NPEID_OFFSET      24
-
-/**
- * @def IX_NPEDL_IMAGEID_DEVICEID_OFFSET
- *
- * @brief Offset from LSB of Device ID field in Image ID
- */
-#define IX_NPEDL_IMAGEID_DEVICEID_OFFSET   28
-
-/**
- * @def IX_NPEDL_IMAGEID_FUNCTIONID_OFFSET
- *
- * @brief Offset from LSB of Functionality ID field in Image ID
- */
-#define IX_NPEDL_IMAGEID_FUNCTIONID_OFFSET 16
-
-/**
- * @def IX_NPEDL_IMAGEID_MAJOR_OFFSET
- *
- * @brief Offset from LSB of Major revision field in Image ID
- */
-#define IX_NPEDL_IMAGEID_MAJOR_OFFSET      8
-
-/**
- * @def IX_NPEDL_IMAGEID_MINOR_OFFSET
- *
- * @brief Offset from LSB of Minor revision field in Image ID
- */
-#define IX_NPEDL_IMAGEID_MINOR_OFFSET      0
-
-
-/**
- * @def IX_NPEDL_NPEID_FROM_IMAGEID_GET
- *
- * @brief Macro to extract NPE ID field from Image ID
- */
-#define IX_NPEDL_NPEID_FROM_IMAGEID_GET(imageId) \
-    (((imageId) >> IX_NPEDL_IMAGEID_NPEID_OFFSET) & \
-     IX_NPEDL_NPEIMAGE_NPEID_MASK)
-
-/**
- * @def IX_NPEDL_DEVICEID_FROM_IMAGEID_GET
- *
- * @brief Macro to extract NPE ID field from Image ID
- */
-#define IX_NPEDL_DEVICEID_FROM_IMAGEID_GET(imageId) \
-    (((imageId) >> IX_NPEDL_IMAGEID_DEVICEID_OFFSET) & \
-     IX_NPEDL_NPEIMAGE_DEVICEID_MASK)
-
-/**
- * @def IX_NPEDL_FUNCTIONID_FROM_IMAGEID_GET
- *
- * @brief Macro to extract Functionality ID field from Image ID
- */
-#define IX_NPEDL_FUNCTIONID_FROM_IMAGEID_GET(imageId) \
-    (((imageId) >> IX_NPEDL_IMAGEID_FUNCTIONID_OFFSET) & \
-     IX_NPEDL_NPEIMAGE_FIELD_MASK)
-
-/**
- * @def IX_NPEDL_MAJOR_FROM_IMAGEID_GET
- *
- * @brief Macro to extract Major revision field from Image ID
- */
-#define IX_NPEDL_MAJOR_FROM_IMAGEID_GET(imageId) \
-    (((imageId) >> IX_NPEDL_IMAGEID_MAJOR_OFFSET) & \
-     IX_NPEDL_NPEIMAGE_FIELD_MASK)
-
-/**
- * @def IX_NPEDL_MINOR_FROM_IMAGEID_GET
- *
- * @brief Macro to extract Minor revision field from Image ID
- */
-#define IX_NPEDL_MINOR_FROM_IMAGEID_GET(imageId) \
-    (((imageId) >> IX_NPEDL_IMAGEID_MINOR_OFFSET) & \
-     IX_NPEDL_NPEIMAGE_FIELD_MASK)
-
-
-/*
- * Prototypes for interface functions
- */
-
-/**
- * @fn IX_STATUS ixNpeDlImageMgrMicrocodeImageLibraryOverride (UINT32 *clientImageLibrary)
- * 
- * @brief This instructs NPE Downloader to use client-supplied microcode image library.
- *
- * This function sets NPE Downloader to use a client-supplied microcode image library
- * instead of the standard image library which is included by the NPE Downloader.
- * 
- * @note THIS FUNCTION HAS BEEN DEPRECATED AND SHOULD NOT BE USED.
- *       It will be removed in a future release.
- *       See API header file IxNpeDl.h for more information.             
- *
- * @pre
- *    - <i>clientImageLibrary</i> should point to a microcode image library valid for use
- *      by the NPE Downloader component.
- *
- * @post
- *    - the client-supplied image uibrary will be used for all subsequent operations
- *      performed by the NPE Downloader
- *
- * @return
- *      - IX_SUCCESS if the operation was successful
- *      - IX_FAIL if the client-supplied image library did not contain a valid signature
- */ 
-IX_STATUS
-ixNpeDlImageMgrMicrocodeImageLibraryOverride (UINT32 *clientImageLibrary);
-
-
-/**
- * @fn IX_STATUS ixNpeDlImageMgrImageListExtract (IxNpeDlImageId *imageListPtr,
-                                                    UINT32 *numImages)
- * 
- * @brief Extracts a list of images available in the NPE microcode image library.
- *
- * @param IxNpeDlImageId* [out] imageListPtr - pointer to array to contain
- *                                                 a list of images. If NULL,
- *                                                 only the number of images 
- *                                                 is returned (in
- *                                                 <i>numImages</i>)
- * @param UINT32* [inout] numImages - As input, it points to a variable
- *                                      containing the number of images which
- *                                      can be stored in the
- *                                      <i>imageListPtr</i> array. Its value
- *                                      is ignored as input if
- *                                      <i>imageListPtr</i> is NULL. As an
- *                                      output, it will contain number of
- *                                      images in the image library.
- * 
- * This function reads the header of the microcode image library and extracts a list of the
- * images available in the image library.  It can also be used to find the number of
- * images in the image library.
- * 
- * @note THIS FUNCTION HAS BEEN DEPRECATED AND SHOULD NOT BE USED.
- *       It will be removed in a future release.
- *       See API header file IxNpeDl.h for more information.             
- *
- * @pre
- *    - if <i>imageListPtr</i> != NULL, <i>numImages</i> should reflect the
- *      number of image Id elements the <i>imageListPtr</i> can contain.
- *
- * @post
- *    - <i>numImages</i> will reflect the number of image Id's found in the
- *      microcode image library.
- *
- * @return
- *      - IX_SUCCESS if the operation was successful
- *      - IX_FAIL otherwise
- */ 
-IX_STATUS
-ixNpeDlImageMgrImageListExtract (IxNpeDlImageId *imageListPtr,
-				   UINT32 *numImages);
-
-
-/**
- * @fn IX_STATUS ixNpeDlImageMgrImageLocate (IxNpeDlImageId *imageId,
-                                               UINT32 **imagePtr,
-                                               UINT32 *imageSize)
- * 
- * @brief Finds a image block in the NPE microcode image library. 
- *
- * @param IxNpeDlImageId* [in] imageId - the id of the image to locate
- * @param UINT32** [out] imagePtr        - pointer to the image in memory
- * @param UINT32* [out] imageSize        - size (in 32-bit words) of image
- * 
- * This function examines the header of the microcode image library for the location
- * and size of the specified image.
- * 
- * @note THIS FUNCTION HAS BEEN DEPRECATED AND SHOULD NOT BE USED.
- *       It will be removed in a future release.
- *       See API header file IxNpeDl.h for more information.             
- *
- * @pre
- *
- * @post
- *
- * @return 
- *      - IX_SUCCESS if the operation was successful
- *      - IX_FAIL otherwise
- */ 
-IX_STATUS
-ixNpeDlImageMgrImageLocate (IxNpeDlImageId *imageId,
-			      UINT32 **imagePtr,
-			      UINT32 *imageSize);
-
-/**
- * @fn IX_STATUS ixNpeDlImageMgrLatestImageExtract (IxNpeDlImageId *imageId)
- * 
- * @brief Finds the most recent version of an image in the NPE image library. 
- *
- * @param IxNpeDlImageId* [inout] imageId - the id of the image 
- * 
- * This function determines the most recent version of a specified image by its 
- * higest major release and minor revision numbers
- * 
- * @note THIS FUNCTION HAS BEEN DEPRECATED AND SHOULD NOT BE USED.
- *       It will be removed in a future release.
- *       See API header file IxNpeDl.h for more information.             
- *
- * @pre
- *
- * @post
- *
- * @return 
- *      - IX_SUCCESS if the operation was successful
- *      - IX_FAIL otherwise
- */ 
-IX_STATUS
-ixNpeDlImageMgrLatestImageExtract (IxNpeDlImageId *imageId);
-
-/**
- * @fn void ixNpeDlImageMgrStatsShow (void)
- *
- * @brief This function will display the statistics of the IxNpeDl ImageMgr
- *        module
- *
- * @return none
- */
-void
-ixNpeDlImageMgrStatsShow (void);
-
-
-/**
- * @fn void ixNpeDlImageMgrStatsReset (void)
- *
- * @brief This function will reset the statistics of the IxNpeDl ImageMgr
- *        module
- *
- * @return none
- */
-void
-ixNpeDlImageMgrStatsReset (void);
-
-
-/**
- * @fn IX_STATUS ixNpeDlImageMgrImageGet (UINT32 *imageLibrary,
-                                          UINT32 imageId,
-                                          UINT32 **imagePtr,
-                                          UINT32 *imageSize)
- * 
- * @brief Finds a image block in the NPE microcode image library. 
- *
- * @param UINT32*  [in]  imageLibrary - the image library to use
- * @param UINT32   [in]  imageId      - the id of the image to locate
- * @param UINT32** [out] imagePtr     - pointer to the image in memory
- * @param UINT32*  [out] imageSize    - size (in 32-bit words) of image
- * 
- * This function examines the header of the specified microcode image library
- * for the location and size of the specified image.  It returns a pointer to
- * the image in the <i>imagePtr</i> parameter.
- * If no image library is specified (imageLibrary == NULL), then the default
- * built-in image library will be used.
- * 
- * @pre
- *
- * @post
- *
- * @return 
- *      - IX_SUCCESS if the operation was successful
- *      - IX_FAIL otherwise
- */ 
-IX_STATUS
-ixNpeDlImageMgrImageFind (UINT32 *imageLibrary,
-                          UINT32 imageId,
-			  UINT32 **imagePtr,
-			  UINT32 *imageSize);
-
-
-#endif /* IXNPEDLIMAGEMGR_P_H */
-
-/**
- * @} defgroup IxNpeDlImageMgr_p
- */
diff --git a/drivers/net/npe/include/IxNpeDlMacros_p.h b/drivers/net/npe/include/IxNpeDlMacros_p.h
deleted file mode 100644
index 771fe74203..0000000000
--- a/drivers/net/npe/include/IxNpeDlMacros_p.h
+++ /dev/null
@@ -1,390 +0,0 @@
-/**
- * @file IxNpeDlMacros_p.h
- *
- * @author Intel Corporation
- * @date 21 January 2002
- *
- * @brief This file contains the macros for the IxNpeDl component.
- *
- * 
- * @par
- * IXP400 SW Release version 2.0
- * 
- * -- Copyright Notice --
- * 
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- * 
- * @par
- * SPDX-License-Identifier:	BSD-3-Clause
- * @par
- * -- End of Copyright Notice --
-*/
-
-/**
- * @defgroup IxNpeDlMacros_p IxNpeDlMacros_p
- *
- * @brief Macros for the IxNpeDl component.
- * 
- * @{
- */
-
-#ifndef IXNPEDLMACROS_P_H
-#define IXNPEDLMACROS_P_H
-
-
-/*
- * Put the user defined include files required.
- */
-#if (CPU != XSCALE)
-/* To support IxNpeDl unit tests... */
-#include <stdio.h>
-#include "test/IxNpeDlTestReg.h"
-
-#else   
-#include "IxOsal.h"
-
-#endif
-
-
-/*
- * Typedefs
- */
-
-/**
- * @typedef IxNpeDlTraceTypes
- * @brief Enumeration defining IxNpeDl trace levels
- */
-typedef enum
-{
-    IX_NPEDL_TRACE_OFF,     /**< no trace */
-    IX_NPEDL_DEBUG,         /**< debug */
-    IX_NPEDL_FN_ENTRY_EXIT  /**< function entry/exit */
-} IxNpeDlTraceTypes;
-
-
-/*
- * #defines and macros.
- */
-
-/* Implementation of the following macros for use with IxNpeDl unit test code */
-#if (CPU != XSCALE)
-
-
-/**
- * @def IX_NPEDL_TRACE_LEVEL
- *
- * @brief IxNpeDl debug trace level
- */
-#define IX_NPEDL_TRACE_LEVEL IX_NPEDL_FN_ENTRY_EXIT
-
-/**
- * @def IX_NPEDL_ERROR_REPORT
- *
- * @brief Mechanism for reporting IxNpeDl software errors
- *
- * @param char* [in] STR - Error string to report
- *
- * This macro simply prints the error string passed.
- * Intended for use with IxNpeDl unit test code.
- *
- * @return none
- */
-#define IX_NPEDL_ERROR_REPORT(STR) printf ("IxNpeDl ERROR: %s\n", (STR));
-
-/**
- * @def IX_NPEDL_WARNING_REPORT
- *
- * @brief Mechanism for reporting IxNpeDl software errors
- *
- * @param char* [in] STR - Error string to report
- *
- * This macro simply prints the error string passed.
- * Intended for use with IxNpeDl unit test code.
- *
- * @return none
- */
-#define IX_NPEDL_WARNING_REPORT(STR) printf ("IxNpeDl WARNING: %s\n", (STR));
-
-/**
- * @def IX_NPEDL_TRACE0
- *
- * @brief Mechanism for tracing debug for the IxNpeDl component, for no arguments
- *
- * @param unsigned [in] LEVEL - one of IxNpeDlTraceTypes enumerated values
- * @param char* [in] STR - Trace string
- *
- * This macro simply prints the trace string passed, if the level is supported. 
- * Intended for use with IxNpeDl unit test code.
- *
- * @return none
- */
-#define IX_NPEDL_TRACE0(LEVEL, STR) \
-{ \
-    if (LEVEL <= IX_NPEDL_TRACE_LEVEL) \
-    { \
-        printf ("IxNpeDl TRACE: "); \
-        printf ((STR)); \
-        printf ("\n"); \
-    } \
-}
-
- /**
- * @def IX_NPEDL_TRACE1
- *
- * @brief Mechanism for tracing debug for the IxNpeDl component, with 1 argument
- *
- * @param unsigned [in] LEVEL - one of IxNpeDlTraceTypes enumerated values
- * @param char* [in] STR - Trace string
- * @param argType [in] ARG1 - Argument to trace
- *
- * This macro simply prints the trace string passed, if the level is supported.
- * Intended for use with IxNpeDl unit test code.
- *
- * @return none
- */
-#define IX_NPEDL_TRACE1(LEVEL, STR, ARG1) \
-{ \
-    if (LEVEL <= IX_NPEDL_TRACE_LEVEL) \
-    { \
-        printf ("IxNpeDl TRACE: "); \
-        printf (STR, ARG1); \
-        printf ("\n"); \
-    } \
-}
-
-/**
- * @def IX_NPEDL_TRACE2
- *
- * @brief Mechanism for tracing debug for the IxNpeDl component, with 2 arguments
- *
- * @param unsigned [in] LEVEL - one of IxNpeDlTraceTypes enumerated values
- * @param char* [in] STR - Trace string
- * @param argType [in] ARG1 - Argument to trace
- * @param argType [in] ARG2 - Argument to trace
- *
- * This macro simply prints the trace string passed, if the level is supported. 
- * Intended for use with IxNpeDl unit test code.
- *
- * @return none
- */
-#define IX_NPEDL_TRACE2(LEVEL, STR, ARG1, ARG2) \
-{ \
-    if (LEVEL <= IX_NPEDL_TRACE_LEVEL) \
-    { \
-        printf ("IxNpeDl TRACE: "); \
-        printf (STR, ARG1, ARG2); \
-        printf ("\n"); \
-    } \
-}
-
-
-/**
- * @def IX_NPEDL_REG_WRITE
- *
- * @brief Mechanism for writing to a memory-mapped register
- *
- * @param UINT32 [in] base   - Base memory address for this NPE's registers
- * @param UINT32 [in] offset - Offset from base memory address
- * @param UINT32 [in] value  - Value to write to register
- *
- * This macro calls a function from Unit Test code to write a register.  This
- * allows extra flexibility for unit testing of the IxNpeDl component.
- *
- * @return none
- */
-#define IX_NPEDL_REG_WRITE(base, offset, value) \
-{ \
-    ixNpeDlTestRegWrite (base, offset, value); \
-}
-
-
-/**
- * @def IX_NPEDL_REG_READ
- *
- * @brief Mechanism for reading from a memory-mapped register
- *
- * @param UINT32 [in] base     - Base memory address for this NPE's registers
- * @param UINT32 [in] offset   - Offset from base memory address
- * @param UINT32 *[out] value  - Value read from register
- *
- * This macro calls a function from Unit Test code to read a register.  This
- * allows extra flexibility for unit testing of the IxNpeDl component.
- *
- * @return none
- */
-#define IX_NPEDL_REG_READ(base, offset, value) \
-{ \
-    ixNpeDlTestRegRead (base, offset, value); \
-}
-
-
-/* Implementation of the following macros when integrated with IxOsal */
-#else  /* #if (CPU != XSCALE) */
-
-
-/**
- * @def IX_NPEDL_TRACE_LEVEL
- *
- * @brief IxNpeDl debug trace level
- */
-#define IX_NPEDL_TRACE_LEVEL IX_NPEDL_DEBUG
-
-
-/**
- * @def IX_NPEDL_ERROR_REPORT
- *
- * @brief Mechanism for reporting IxNpeDl software errors
- *
- * @param char* [in] STR - Error string to report
- *
- * This macro is used to report IxNpeDl software errors.
- *
- * @return none
- */
-#define IX_NPEDL_ERROR_REPORT(STR) \
-    ixOsalLog (IX_OSAL_LOG_LVL_ERROR, IX_OSAL_LOG_DEV_STDERR, STR, 0, 0, 0, 0, 0, 0);
-
-/**
- * @def IX_NPEDL_WARNING_REPORT
- *
- * @brief Mechanism for reporting IxNpeDl software warnings
- *
- * @param char* [in] STR - Warning string to report
- *
- * This macro is used to report IxNpeDl software warnings.
- *
- * @return none
- */
-#define IX_NPEDL_WARNING_REPORT(STR) \
-    ixOsalLog (IX_OSAL_LOG_LVL_WARNING, IX_OSAL_LOG_DEV_STDOUT, STR, 0, 0, 0, 0, 0, 0);
-
-
-/**
- * @def IX_NPEDL_TRACE0
- *
- * @brief Mechanism for tracing debug for the IxNpeDl component, for no arguments
- *
- * @param unsigned [in] LEVEL - one of IxNpeDlTraceTypes enumerated values
- * @param char* [in] STR - Trace string
- *
- * This macro simply prints the trace string passed, if the level is supported.
- *
- * @return none
- */
-#define IX_NPEDL_TRACE0(LEVEL, STR) \
-{ \
-    if (LEVEL <= IX_NPEDL_TRACE_LEVEL) \
-    { \
-        if (LEVEL == IX_NPEDL_FN_ENTRY_EXIT) \
-        { \
-            ixOsalLog (IX_OSAL_LOG_LVL_DEBUG3, IX_OSAL_LOG_DEV_STDOUT, STR, 0, 0, 0, 0, 0, 0); \
-        } \
-        else if (LEVEL == IX_NPEDL_DEBUG) \
-        { \
-            ixOsalLog (IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT, STR, 0, 0, 0, 0, 0, 0); \
-        } \
-    } \
-}
-
-/**
- * @def IX_NPEDL_TRACE1
- *
- * @brief Mechanism for tracing debug for the IxNpeDl component, with 1 argument
- *
- * @param unsigned [in] LEVEL - one of IxNpeDlTraceTypes enumerated values
- * @param char* [in] STR - Trace string
- * @param argType [in] ARG1 - Argument to trace
- *
- * This macro simply prints the trace string passed, if the level is supported. 
- *
- * @return none
- */
-#define IX_NPEDL_TRACE1(LEVEL, STR, ARG1) \
-{ \
-    if (LEVEL <= IX_NPEDL_TRACE_LEVEL) \
-    { \
-        if (LEVEL == IX_NPEDL_FN_ENTRY_EXIT) \
-        { \
-            ixOsalLog (IX_OSAL_LOG_LVL_DEBUG3, IX_OSAL_LOG_DEV_STDOUT, STR, ARG1, 0, 0, 0, 0, 0); \
-        } \
-        else if (LEVEL == IX_NPEDL_DEBUG) \
-        { \
-            ixOsalLog (IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT, STR, ARG1, 0, 0, 0, 0, 0); \
-        } \
-    } \
-}
-
-/**
- * @def IX_NPEDL_TRACE2
- *
- * @brief Mechanism for tracing debug for the IxNpeDl component, with 2 arguments
- *
- * @param unsigned [in] LEVEL - one of IxNpeDlTraceTypes enumerated values
- * @param char* [in] STR - Trace string
- * @param argType [in] ARG1 - Argument to trace
- * @param argType [in] ARG2 - Argument to trace
- *
- * This macro simply prints the trace string passed, if the level is supported. 
- *
- * @return none
- */
-#define IX_NPEDL_TRACE2(LEVEL, STR, ARG1, ARG2) \
-{ \
-    if (LEVEL <= IX_NPEDL_TRACE_LEVEL) \
-    { \
-        if (LEVEL == IX_NPEDL_FN_ENTRY_EXIT) \
-        { \
-            ixOsalLog (IX_OSAL_LOG_LVL_DEBUG3, IX_OSAL_LOG_DEV_STDOUT, STR, ARG1, ARG2, 0, 0, 0, 0); \
-        } \
-        else if (LEVEL == IX_NPEDL_DEBUG) \
-        { \
-            ixOsalLog (IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT, STR, ARG1, ARG2, 0, 0, 0, 0); \
-        } \
-    } \
-}
-
-/**
- * @def IX_NPEDL_REG_WRITE
- *
- * @brief Mechanism for writing to a memory-mapped register
- *
- * @param UINT32 [in] base   - Base memory address for this NPE's registers
- * @param UINT32 [in] offset - Offset from base memory address
- * @param UINT32 [in] value  - Value to write to register
- *
- * This macro forms the address of the register from base address + offset, and 
- * dereferences that address to write the contents of the register.
- *
- * @return none
- */
-#define IX_NPEDL_REG_WRITE(base, offset, value) \
-    IX_OSAL_WRITE_LONG(((base) + (offset)), (value))
-
-
-
-/**
- * @def IX_NPEDL_REG_READ
- *
- * @brief Mechanism for reading from a memory-mapped register
- *
- * @param UINT32 [in] base    - Base memory address for this NPE's registers
- * @param UINT32 [in] offset  - Offset from base memory address
- * @param UINT32 *[out] value  - Value read from register
- *
- * This macro forms the address of the register from base address + offset, and 
- * dereferences that address to read the register contents.
- *
- * @return none
- */
-#define IX_NPEDL_REG_READ(base, offset, value) \
-    *(value) = IX_OSAL_READ_LONG(((base) + (offset)))
-
-#endif  /* #if (CPU != XSCALE) */
-
-#endif /* IXNPEDLMACROS_P_H */
-
-/**
- * @} defgroup IxNpeDlMacros_p
- */
diff --git a/drivers/net/npe/include/IxNpeDlNpeMgrEcRegisters_p.h b/drivers/net/npe/include/IxNpeDlNpeMgrEcRegisters_p.h
deleted file mode 100644
index f6c2e46de3..0000000000
--- a/drivers/net/npe/include/IxNpeDlNpeMgrEcRegisters_p.h
+++ /dev/null
@@ -1,869 +0,0 @@
-/**
- * @file IxNpeDlNpeMgrEcRegisters_p.h
- *
- * @author Intel Corporation
- * @date 14 December 2001
-
- * 
- * @par
- * IXP400 SW Release version 2.0
- * 
- * -- Copyright Notice --
- * 
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- * 
- * @par
- * SPDX-License-Identifier:	BSD-3-Clause
- * @par
- * -- End of Copyright Notice --
-*/
-
-
-#ifndef IXNPEDLNPEMGRECREGISTERS_P_H
-#define IXNPEDLNPEMGRECREGISTERS_P_H
-
-#include "IxOsal.h"
-
-/*
- * Base Memory Addresses for accessing NPE registers
- */
-
-#define IX_NPEDL_NPE_BASE (IX_OSAL_IXP400_PERIPHERAL_PHYS_BASE)
-
-#define IX_NPEDL_NPEA_OFFSET (0x6000) /**< NPE-A register base offset */
-#define IX_NPEDL_NPEB_OFFSET (0x7000) /**< NPE-B register base offset */
-#define IX_NPEDL_NPEC_OFFSET (0x8000) /**< NPE-C register base offset */
-
-/**
- * @def IX_NPEDL_NPEBASEADDRESS_NPEA
- * @brief Base Memory Address of NPE-A Configuration Bus registers
- */
-#define IX_NPEDL_NPEBASEADDRESS_NPEA (IX_NPEDL_NPE_BASE + IX_NPEDL_NPEA_OFFSET)
-
-/**
- * @def IX_NPEDL_NPEBASEADDRESS_NPEB
- * @brief Base Memory Address of NPE-B Configuration Bus registers
- */
-#define IX_NPEDL_NPEBASEADDRESS_NPEB (IX_NPEDL_NPE_BASE + IX_NPEDL_NPEB_OFFSET)
-
-/**
- * @def IX_NPEDL_NPEBASEADDRESS_NPEC
- * @brief Base Memory Address of NPE-C Configuration Bus registers
- */
-#define IX_NPEDL_NPEBASEADDRESS_NPEC (IX_NPEDL_NPE_BASE + IX_NPEDL_NPEC_OFFSET)
-
-
-/*
- * Instruction Memory Size (in words) for each NPE 
- */
-
-/**
- * @def IX_NPEDL_INS_MEMSIZE_WORDS_NPEA
- * @brief Size (in words) of NPE-A Instruction Memory
- */
-#define IX_NPEDL_INS_MEMSIZE_WORDS_NPEA     4096
-
-/**
- * @def IX_NPEDL_INS_MEMSIZE_WORDS_NPEB
- * @brief Size (in words) of NPE-B Instruction Memory
- */
-#define IX_NPEDL_INS_MEMSIZE_WORDS_NPEB     2048
-
-/**
- * @def IX_NPEDL_INS_MEMSIZE_WORDS_NPEC
- * @brief Size (in words) of NPE-B Instruction Memory
- */
-#define IX_NPEDL_INS_MEMSIZE_WORDS_NPEC     2048
-
-
-/*
- * Data Memory Size (in words) for each NPE 
- */
-
-/**
- * @def IX_NPEDL_DATA_MEMSIZE_WORDS_NPEA
- * @brief Size (in words) of NPE-A Data Memory
- */
-#define IX_NPEDL_DATA_MEMSIZE_WORDS_NPEA    2048
-
-/**
- * @def IX_NPEDL_DATA_MEMSIZE_WORDS_NPEB
- * @brief Size (in words) of NPE-B Data Memory
- */
-#define IX_NPEDL_DATA_MEMSIZE_WORDS_NPEB    2048
-
-/**
- * @def IX_NPEDL_DATA_MEMSIZE_WORDS_NPEC
- * @brief Size (in words) of NPE-C Data Memory
- */
-#define IX_NPEDL_DATA_MEMSIZE_WORDS_NPEC    2048
-
-
-/*
- * Configuration Bus Register offsets (in bytes) from NPE Base Address
- */
-
-/**
- * @def IX_NPEDL_REG_OFFSET_EXAD
- * @brief Offset (in bytes) of EXAD (Execution Address) register from NPE Base
- *        Address
- */
-#define IX_NPEDL_REG_OFFSET_EXAD             0x00000000		
-
-/**
- * @def IX_NPEDL_REG_OFFSET_EXDATA
- * @brief Offset (in bytes) of EXDATA (Execution Data) register from NPE Base
- *        Address
- */
-#define IX_NPEDL_REG_OFFSET_EXDATA           0x00000004
-
-/**
- * @def IX_NPEDL_REG_OFFSET_EXCTL
- * @brief Offset (in bytes) of EXCTL (Execution Control) register from NPE Base
- *        Address
- */
-#define IX_NPEDL_REG_OFFSET_EXCTL            0x00000008		
-
-/**
- * @def IX_NPEDL_REG_OFFSET_EXCT
- * @brief Offset (in bytes) of EXCT (Execution Count) register from NPE Base
- *        Address
- */
-#define IX_NPEDL_REG_OFFSET_EXCT 	     0x0000000C		
-
-/**
- * @def IX_NPEDL_REG_OFFSET_AP0
- * @brief Offset (in bytes) of AP0 (Action Point 0) register from NPE Base
- *        Address
- */
-#define IX_NPEDL_REG_OFFSET_AP0	             0x00000010		
-
-/**
- * @def IX_NPEDL_REG_OFFSET_AP1
- * @brief Offset (in bytes) of AP1 (Action Point 1) register from NPE Base
- *        Address
- */
-#define IX_NPEDL_REG_OFFSET_AP1	             0x00000014		
-
-/**
- * @def IX_NPEDL_REG_OFFSET_AP2
- * @brief Offset (in bytes) of AP2 (Action Point 2) register from NPE Base
- *        Address
- */
-#define IX_NPEDL_REG_OFFSET_AP2	             0x00000018		
-
-/**
- * @def IX_NPEDL_REG_OFFSET_AP3
- * @brief Offset (in bytes) of AP3 (Action Point 3) register from NPE Base
- *        Address
- */
-#define IX_NPEDL_REG_OFFSET_AP3	             0x0000001C		
-
-/**
- * @def IX_NPEDL_REG_OFFSET_WFIFO
- * @brief Offset (in bytes) of WFIFO (Watchpoint FIFO) register from NPE Base
- *        Address
- */
-#define IX_NPEDL_REG_OFFSET_WFIFO            0x00000020
-
-/**
- * @def IX_NPEDL_REG_OFFSET_WC
- * @brief Offset (in bytes) of WC (Watch Count) register from NPE Base
- *        Address
- */
-#define IX_NPEDL_REG_OFFSET_WC	             0x00000024 		
-
-/**
- * @def IX_NPEDL_REG_OFFSET_PROFCT
- * @brief Offset (in bytes) of PROFCT (Profile Count) register from NPE Base
- *        Address
- */
-#define IX_NPEDL_REG_OFFSET_PROFCT           0x00000028		
-
-/**
- * @def IX_NPEDL_REG_OFFSET_STAT
- * @brief Offset (in bytes) of STAT (Messaging Status) register from NPE Base
- *        Address
- */
-#define IX_NPEDL_REG_OFFSET_STAT	     0x0000002C		
-
-/**
- * @def IX_NPEDL_REG_OFFSET_CTL
- * @brief Offset (in bytes) of CTL (Messaging Control) register from NPE Base
- *        Address
- */
-#define IX_NPEDL_REG_OFFSET_CTL	             0x00000030		
-
-/**
- * @def IX_NPEDL_REG_OFFSET_MBST
- * @brief Offset (in bytes) of MBST (Mailbox Status) register from NPE Base
- *        Address
- */
-#define IX_NPEDL_REG_OFFSET_MBST	     0x00000034		
-
-/**
- * @def IX_NPEDL_REG_OFFSET_FIFO
- * @brief Offset (in bytes) of FIFO (messaging in/out FIFO) register from NPE
- *        Base Address
- */
-#define IX_NPEDL_REG_OFFSET_FIFO	     0x00000038		
-
-
-/*
- * Non-zero reset values for the Configuration Bus registers
- */
-
-/**
- * @def IX_NPEDL_REG_RESET_FIFO
- * @brief Reset value for Mailbox (MBST) register
- *        NOTE that if used, it should be complemented with an NPE intruction
- *        to clear the Mailbox at the NPE side as well
- */
-#define IX_NPEDL_REG_RESET_MBST              0x0000F0F0
-
-
-/*
- * Bit-masks used to read/write particular bits in Configuration Bus registers
- */
-
-/**
- * @def IX_NPEDL_MASK_WFIFO_VALID
- * @brief Masks the VALID bit in the WFIFO register
- */
-#define IX_NPEDL_MASK_WFIFO_VALID            0x80000000
-
-/**
- * @def IX_NPEDL_MASK_STAT_OFNE
- * @brief Masks the OFNE bit in the STAT register
- */
-#define IX_NPEDL_MASK_STAT_OFNE              0x00010000
-
-/**
- * @def IX_NPEDL_MASK_STAT_IFNE
- * @brief Masks the IFNE bit in the STAT register
- */
-#define IX_NPEDL_MASK_STAT_IFNE              0x00080000
-
-
-/*
- * EXCTL (Execution Control) Register commands 
-*/
-
-/**
- * @def IX_NPEDL_EXCTL_CMD_NPE_STEP
- * @brief EXCTL Command to Step execution of an NPE Instruction
- */
-
-#define IX_NPEDL_EXCTL_CMD_NPE_STEP          0x01
-
-/**
- * @def IX_NPEDL_EXCTL_CMD_NPE_START
- * @brief EXCTL Command to Start NPE execution
- */
-#define IX_NPEDL_EXCTL_CMD_NPE_START         0x02
-
-/**
- * @def IX_NPEDL_EXCTL_CMD_NPE_STOP
- * @brief EXCTL Command to Stop NPE execution
- */
-#define IX_NPEDL_EXCTL_CMD_NPE_STOP          0x03
-
-/**
- * @def IX_NPEDL_EXCTL_CMD_NPE_CLR_PIPE
- * @brief EXCTL Command to Clear NPE instruction pipeline
- */
-#define IX_NPEDL_EXCTL_CMD_NPE_CLR_PIPE      0x04
-
-/**
- * @def IX_NPEDL_EXCTL_CMD_RD_INS_MEM
- * @brief EXCTL Command to read NPE instruction memory at address in EXAD
- *        register and return value in EXDATA register
- */
-#define IX_NPEDL_EXCTL_CMD_RD_INS_MEM        0x10
-
-/**
- * @def IX_NPEDL_EXCTL_CMD_WR_INS_MEM
- * @brief EXCTL Command to write NPE instruction memory at address in EXAD
- *        register with data in EXDATA register
- */
-#define IX_NPEDL_EXCTL_CMD_WR_INS_MEM        0x11
-
-/**
- * @def IX_NPEDL_EXCTL_CMD_RD_DATA_MEM
- * @brief EXCTL Command to read NPE data memory at address in EXAD
- *        register and return value in EXDATA register
- */
-#define IX_NPEDL_EXCTL_CMD_RD_DATA_MEM       0x12
-
-/**
- * @def IX_NPEDL_EXCTL_CMD_WR_DATA_MEM
- * @brief EXCTL Command to write NPE data memory at address in EXAD
- *        register with data in EXDATA register
- */
-#define IX_NPEDL_EXCTL_CMD_WR_DATA_MEM       0x13
-
-/**
- * @def IX_NPEDL_EXCTL_CMD_RD_ECS_REG
- * @brief EXCTL Command to read Execution Access register at address in EXAD
- *        register and return value in EXDATA register
- */
-#define IX_NPEDL_EXCTL_CMD_RD_ECS_REG        0x14
-
-/**
- * @def IX_NPEDL_EXCTL_CMD_WR_ECS_REG
- * @brief EXCTL Command to write Execution Access register at address in EXAD
- *        register with data in EXDATA register
- */
-#define IX_NPEDL_EXCTL_CMD_WR_ECS_REG        0x15
-
-/**
- * @def IX_NPEDL_EXCTL_CMD_CLR_PROFILE_CNT
- * @brief EXCTL Command to clear Profile Count register
- */
-#define IX_NPEDL_EXCTL_CMD_CLR_PROFILE_CNT   0x0C
-
-
-/*
- * EXCTL (Execution Control) Register status bit masks
- */
-
-/**
- * @def IX_NPEDL_EXCTL_STATUS_RUN
- * @brief Masks the RUN status bit in the EXCTL register
- */
-#define IX_NPEDL_EXCTL_STATUS_RUN            0x80000000
-
-/**
- * @def IX_NPEDL_EXCTL_STATUS_STOP
- * @brief Masks the STOP status bit in the EXCTL register
- */
-#define IX_NPEDL_EXCTL_STATUS_STOP           0x40000000
-
-/**
- * @def IX_NPEDL_EXCTL_STATUS_CLEAR
- * @brief Masks the CLEAR status bit in the EXCTL register
- */
-#define IX_NPEDL_EXCTL_STATUS_CLEAR          0x20000000
-
-/**
- * @def IX_NPEDL_EXCTL_STATUS_ECS_K
- * @brief Masks the K (pipeline Klean) status bit in the EXCTL register
- */
-#define IX_NPEDL_EXCTL_STATUS_ECS_K          0x00800000
-
-
-/*
- * Executing Context Stack (ECS) level registers 
- */
-
-/**
- * @def IX_NPEDL_ECS_BG_CTXT_REG_0
- * @brief Execution Access register address for register 0 at Backgound 
- *        Executing Context Stack level
- */
-#define IX_NPEDL_ECS_BG_CTXT_REG_0           0x00
-
-/**
- * @def IX_NPEDL_ECS_BG_CTXT_REG_1
- * @brief Execution Access register address for register 1 at Backgound 
- *        Executing Context Stack level
- */
-#define IX_NPEDL_ECS_BG_CTXT_REG_1           0x01
-
-/**
- * @def IX_NPEDL_ECS_BG_CTXT_REG_2
- * @brief Execution Access register address for register 2 at Backgound 
- *        Executing Context Stack level
- */
-#define IX_NPEDL_ECS_BG_CTXT_REG_2           0x02
-
-/**
- * @def IX_NPEDL_ECS_PRI_1_CTXT_REG_0
- * @brief Execution Access register address for register 0 at Priority 1
- *        Executing Context Stack level
- */
-#define IX_NPEDL_ECS_PRI_1_CTXT_REG_0        0x04
-
-/**
- * @def IX_NPEDL_ECS_PRI_1_CTXT_REG_1
- * @brief Execution Access register address for register 1 at Priority 1
- *        Executing Context Stack level
- */
-#define IX_NPEDL_ECS_PRI_1_CTXT_REG_1        0x05
-
-/**
- * @def IX_NPEDL_ECS_PRI_1_CTXT_REG_2
- * @brief Execution Access register address for register 2 at Priority 1
- *        Executing Context Stack level
- */
-#define IX_NPEDL_ECS_PRI_1_CTXT_REG_2        0x06
-
-/**
- * @def IX_NPEDL_ECS_PRI_2_CTXT_REG_0
- * @brief Execution Access register address for register 0 at Priority 2
- *        Executing Context Stack level
- */
-#define IX_NPEDL_ECS_PRI_2_CTXT_REG_0        0x08
-
-/**
- * @def IX_NPEDL_ECS_PRI_2_CTXT_REG_1
- * @brief Execution Access register address for register 1 at Priority 2
- *        Executing Context Stack level
- */
-#define IX_NPEDL_ECS_PRI_2_CTXT_REG_1        0x09
-
-/**
- * @def IX_NPEDL_ECS_PRI_2_CTXT_REG_2
- * @brief Execution Access register address for register 2 at Priority 2
- *        Executing Context Stack level
- */
-#define IX_NPEDL_ECS_PRI_2_CTXT_REG_2        0x0A
-
-/**
- * @def IX_NPEDL_ECS_DBG_CTXT_REG_0
- * @brief Execution Access register address for register 0 at Debug
- *        Executing Context Stack level
- */
-#define IX_NPEDL_ECS_DBG_CTXT_REG_0          0x0C
-
-/**
- * @def IX_NPEDL_ECS_DBG_CTXT_REG_1
- * @brief Execution Access register address for register 1 at Debug 
- *        Executing Context Stack level
- */
-#define IX_NPEDL_ECS_DBG_CTXT_REG_1          0x0D
-
-/**
- * @def IX_NPEDL_ECS_DBG_CTXT_REG_2
- * @brief Execution Access register address for register 2 at Debug 
- *        Executing Context Stack level
- */
-#define IX_NPEDL_ECS_DBG_CTXT_REG_2          0x0E
-
-/**
- * @def IX_NPEDL_ECS_INSTRUCT_REG
- * @brief Execution Access register address for NPE Instruction Register 
- */
-#define IX_NPEDL_ECS_INSTRUCT_REG            0x11
-
-
-/*
- * Execution Access register reset values
- */
-
-/**
- * @def IX_NPEDL_ECS_BG_CTXT_REG_0_RESET
- * @brief Reset value for Execution Access Background ECS level register 0
- */
-#define IX_NPEDL_ECS_BG_CTXT_REG_0_RESET     0xA0000000
-
-/**
- * @def IX_NPEDL_ECS_BG_CTXT_REG_1_RESET
- * @brief Reset value for Execution Access Background ECS level register 1
- */
-#define IX_NPEDL_ECS_BG_CTXT_REG_1_RESET     0x01000000
-
-/**
- * @def IX_NPEDL_ECS_BG_CTXT_REG_2_RESET
- * @brief Reset value for Execution Access Background ECS level register 2
- */
-#define IX_NPEDL_ECS_BG_CTXT_REG_2_RESET     0x00008000
-
-/**
- * @def IX_NPEDL_ECS_PRI_1_CTXT_REG_0_RESET
- * @brief Reset value for Execution Access Priority 1 ECS level register 0
- */
-#define IX_NPEDL_ECS_PRI_1_CTXT_REG_0_RESET  0x20000080
-
-/**
- * @def IX_NPEDL_ECS_PRI_1_CTXT_REG_1_RESET
- * @brief Reset value for Execution Access Priority 1 ECS level register 1
- */
-#define IX_NPEDL_ECS_PRI_1_CTXT_REG_1_RESET  0x01000000
-
-/**
- * @def IX_NPEDL_ECS_PRI_1_CTXT_REG_2_RESET
- * @brief Reset value for Execution Access Priority 1 ECS level register 2
- */
-#define IX_NPEDL_ECS_PRI_1_CTXT_REG_2_RESET  0x00008000
-
-/**
- * @def IX_NPEDL_ECS_PRI_2_CTXT_REG_0_RESET
- * @brief Reset value for Execution Access Priority 2 ECS level register 0
- */
-#define IX_NPEDL_ECS_PRI_2_CTXT_REG_0_RESET  0x20000080
-
-/**
- * @def IX_NPEDL_ECS_PRI_2_CTXT_REG_1_RESET
- * @brief Reset value for Execution Access Priority 2 ECS level register 1
- */
-#define IX_NPEDL_ECS_PRI_2_CTXT_REG_1_RESET  0x01000000
-
-/**
- * @def IX_NPEDL_ECS_PRI_2_CTXT_REG_2_RESET
- * @brief Reset value for Execution Access Priority 2 ECS level register 2
- */
-#define IX_NPEDL_ECS_PRI_2_CTXT_REG_2_RESET  0x00008000
-
-/**
- * @def IX_NPEDL_ECS_DBG_CTXT_REG_0_RESET
- * @brief Reset value for Execution Access Debug ECS level register 0
- */
-#define IX_NPEDL_ECS_DBG_CTXT_REG_0_RESET    0x20000000
-
-/**
- * @def IX_NPEDL_ECS_DBG_CTXT_REG_1_RESET
- * @brief Reset value for Execution Access Debug ECS level register 1
- */
-#define IX_NPEDL_ECS_DBG_CTXT_REG_1_RESET    0x00000000
-
-/**
- * @def IX_NPEDL_ECS_DBG_CTXT_REG_2_RESET
- * @brief Reset value for Execution Access Debug ECS level register 2
- */
-#define IX_NPEDL_ECS_DBG_CTXT_REG_2_RESET    0x001E0000
-
-/**
- * @def IX_NPEDL_ECS_INSTRUCT_REG_RESET
- * @brief Reset value for Execution Access NPE Instruction Register
- */
-#define IX_NPEDL_ECS_INSTRUCT_REG_RESET      0x1003C00F
-
-
-/*
- * masks used to read/write particular bits in Execution Access registers
- */
-
-/**
- * @def IX_NPEDL_MASK_ECS_REG_0_ACTIVE
- * @brief Mask the A (Active) bit in Execution Access Register 0 of all ECS
- *        levels
- */
-#define IX_NPEDL_MASK_ECS_REG_0_ACTIVE       0x80000000
-
-/**
- * @def IX_NPEDL_MASK_ECS_REG_0_NEXTPC
- * @brief Mask the NextPC bits in Execution Access Register 0 of all ECS
- *        levels (except Debug ECS level)
- */
-#define IX_NPEDL_MASK_ECS_REG_0_NEXTPC       0x1FFF0000
-
-/**
- * @def IX_NPEDL_MASK_ECS_REG_0_LDUR
- * @brief Mask the LDUR bits in Execution Access Register 0 of all ECS levels
- */
-#define IX_NPEDL_MASK_ECS_REG_0_LDUR         0x00000700
-
-/**
- * @def IX_NPEDL_MASK_ECS_REG_1_CCTXT
- * @brief Mask the NextPC bits in Execution Access Register 1 of all ECS levels
- */
-#define IX_NPEDL_MASK_ECS_REG_1_CCTXT        0x000F0000
-
-/**
- * @def IX_NPEDL_MASK_ECS_REG_1_SELCTXT
- * @brief Mask the NextPC bits in Execution Access Register 1 of all ECS levels
- */
-#define IX_NPEDL_MASK_ECS_REG_1_SELCTXT      0x0000000F
-
-/**
- * @def IX_NPEDL_MASK_ECS_DBG_REG_2_IF
- * @brief Mask the IF bit in Execution Access Register 2 of Debug ECS level
- */
-#define IX_NPEDL_MASK_ECS_DBG_REG_2_IF       0x00100000
-
-/**
- * @def IX_NPEDL_MASK_ECS_DBG_REG_2_IE
- * @brief Mask the IE bit in Execution Access Register 2 of Debug ECS level
- */
-#define IX_NPEDL_MASK_ECS_DBG_REG_2_IE       0x00080000
-
-
-/*
- * Bit-Offsets from LSB of particular bit-fields in Execution Access registers
- */
-
-/**
- * @def IX_NPEDL_OFFSET_ECS_REG_0_NEXTPC
- * @brief LSB-offset of NextPC field in Execution Access Register 0 of all ECS
- *        levels (except Debug ECS level)
- */
-#define IX_NPEDL_OFFSET_ECS_REG_0_NEXTPC     16 
-
-/**
- * @def IX_NPEDL_OFFSET_ECS_REG_0_LDUR
- * @brief LSB-offset of LDUR field in Execution Access Register 0 of all ECS
- *        levels
- */
-#define IX_NPEDL_OFFSET_ECS_REG_0_LDUR        8
-
-/**
- * @def IX_NPEDL_OFFSET_ECS_REG_1_CCTXT
- * @brief LSB-offset of CCTXT field in Execution Access Register 1 of all ECS
- *        levels
- */
-#define IX_NPEDL_OFFSET_ECS_REG_1_CCTXT      16
-
-/**
- * @def IX_NPEDL_OFFSET_ECS_REG_1_SELCTXT
- * @brief LSB-offset of SELCTXT field in Execution Access Register 1 of all ECS
- *        levels
- */
-#define IX_NPEDL_OFFSET_ECS_REG_1_SELCTXT     0
-
-
-/*
- * NPE core & co-processor instruction templates to load into NPE Instruction 
- * Register, for read/write of NPE register file registers
- */
-
-/**
- * @def IX_NPEDL_INSTR_RD_REG_BYTE
- * @brief NPE Instruction, used to read an 8-bit NPE internal logical register
- *        and return the value in the EXDATA register (aligned to MSB).
- *        NPE Assembler instruction:  "mov8 d0, d0  &&& DBG_WrExec"
- */
-#define IX_NPEDL_INSTR_RD_REG_BYTE    0x0FC00000
-
-/**
- * @def IX_NPEDL_INSTR_RD_REG_SHORT
- * @brief NPE Instruction, used to read a 16-bit NPE internal logical register
- *        and return the value in the EXDATA register (aligned to MSB).
- *        NPE Assembler instruction:  "mov16 d0, d0  &&& DBG_WrExec"
- */
-#define IX_NPEDL_INSTR_RD_REG_SHORT   0x0FC08010
-
-/**
- * @def IX_NPEDL_INSTR_RD_REG_WORD
- * @brief NPE Instruction, used to read a 16-bit NPE internal logical register
- *        and return the value in the EXDATA register.
- *        NPE Assembler instruction:  "mov32 d0, d0  &&& DBG_WrExec"
- */
-#define IX_NPEDL_INSTR_RD_REG_WORD    0x0FC08210
-
-/**
- * @def IX_NPEDL_INSTR_WR_REG_BYTE
- * @brief NPE Immediate-Mode Instruction, used to write an 8-bit NPE internal
- *        logical register.
- *        NPE Assembler instruction:  "mov8 d0, #0"
- */
-#define IX_NPEDL_INSTR_WR_REG_BYTE    0x00004000
-
-/**
- * @def IX_NPEDL_INSTR_WR_REG_SHORT
- * @brief NPE Immediate-Mode Instruction, used to write a 16-bit NPE internal
- *        logical register.
- *        NPE Assembler instruction:  "mov16 d0, #0"
- */
-#define IX_NPEDL_INSTR_WR_REG_SHORT   0x0000C000
-
-/**
- * @def IX_NPEDL_INSTR_RD_FIFO
- * @brief NPE Immediate-Mode Instruction, used to write a 16-bit NPE internal
- *        logical register.
- *        NPE Assembler instruction:  "cprd32 d0    &&& DBG_RdInFIFO"
- */
-#define IX_NPEDL_INSTR_RD_FIFO        0x0F888220    
-
-/**
- * @def IX_NPEDL_INSTR_RESET_MBOX
- * @brief NPE Instruction, used to reset Mailbox (MBST) register
- *        NPE Assembler instruction:  "mov32 d0, d0  &&& DBG_ClearM"
- */
-#define IX_NPEDL_INSTR_RESET_MBOX     0x0FAC8210
-
-
-/*
- * Bit-offsets from LSB, of particular bit-fields in an NPE instruction
- */
-
-/**
- * @def IX_NPEDL_OFFSET_INSTR_SRC
- * @brief LSB-offset to SRC (source operand) field of an NPE Instruction
- */
-#define IX_NPEDL_OFFSET_INSTR_SRC              4
-
-/**
- * @def IX_NPEDL_OFFSET_INSTR_DEST
- * @brief LSB-offset to DEST (destination operand) field of an NPE Instruction
- */
-#define IX_NPEDL_OFFSET_INSTR_DEST             9
-
-/**
- * @def IX_NPEDL_OFFSET_INSTR_COPROC
- * @brief LSB-offset to COPROC (coprocessor instruction) field of an NPE
- *        Instruction
- */
-#define IX_NPEDL_OFFSET_INSTR_COPROC          18
-
-
-/*
- * masks used to read/write particular bits of an NPE Instruction
- */
-
-/**
- * @def IX_NPEDL_MASK_IMMED_INSTR_SRC_DATA
- * @brief Mask the bits of 16-bit data value (least-sig 5 bits) to be used in
- *        SRC field of immediate-mode NPE instruction
- */
-#define IX_NPEDL_MASK_IMMED_INSTR_SRC_DATA         0x1F 
-
-/**
- * @def IX_NPEDL_MASK_IMMED_INSTR_COPROC_DATA
- * @brief Mask the bits of 16-bit data value (most-sig 11 bits) to be used in
- *        COPROC field of immediate-mode NPE instruction
- */
-#define IX_NPEDL_MASK_IMMED_INSTR_COPROC_DATA      0xFFE0
-
-/**
- * @def IX_NPEDL_OFFSET_IMMED_INSTR_COPROC_DATA
- * @brief LSB offset of the bit-field of 16-bit data value (most-sig 11 bits)
- *        to be used in COPROC field of immediate-mode NPE instruction
- */
-#define IX_NPEDL_OFFSET_IMMED_INSTR_COPROC_DATA    5
-
-/**
- * @def IX_NPEDL_DISPLACE_IMMED_INSTR_COPROC_DATA
- * @brief Number of left-shifts required to align most-sig 11 bits of 16-bit
- *        data value into COPROC field of immediate-mode NPE instruction
- */
-#define IX_NPEDL_DISPLACE_IMMED_INSTR_COPROC_DATA \
-     (IX_NPEDL_OFFSET_INSTR_COPROC - IX_NPEDL_OFFSET_IMMED_INSTR_COPROC_DATA)
-
-/**
- * @def IX_NPEDL_WR_INSTR_LDUR
- * @brief LDUR value used with immediate-mode NPE Instructions by the NpeDl
- *        for writing to NPE internal logical registers
- */
-#define IX_NPEDL_WR_INSTR_LDUR                     1
-
-/**
- * @def IX_NPEDL_RD_INSTR_LDUR
- * @brief LDUR value used with NON-immediate-mode NPE Instructions by the NpeDl
- *        for reading from NPE internal logical registers
- */
-#define IX_NPEDL_RD_INSTR_LDUR                     0
-
-
-/**
- * @enum IxNpeDlCtxtRegNum
- * @brief Numeric values to identify the NPE internal Context Store registers
- */
-typedef enum
-{
-    IX_NPEDL_CTXT_REG_STEVT = 0,  /**< identifies STEVT   */
-    IX_NPEDL_CTXT_REG_STARTPC,    /**< identifies STARTPC */
-    IX_NPEDL_CTXT_REG_REGMAP,     /**< identifies REGMAP  */
-    IX_NPEDL_CTXT_REG_CINDEX,     /**< identifies CINDEX  */
-    IX_NPEDL_CTXT_REG_MAX         /**< Total number of Context Store registers */
-} IxNpeDlCtxtRegNum;
-
-
-/*
- * NPE Context Store register logical addresses
- */
-
-/**
- * @def IX_NPEDL_CTXT_REG_ADDR_STEVT
- * @brief Logical address of STEVT NPE internal Context Store register
- */
-#define IX_NPEDL_CTXT_REG_ADDR_STEVT      0x0000001B
-
-/**
- * @def IX_NPEDL_CTXT_REG_ADDR_STARTPC
- * @brief Logical address of STARTPC NPE internal Context Store register
- */
-#define IX_NPEDL_CTXT_REG_ADDR_STARTPC    0x0000001C
-
-/**
- * @def IX_NPEDL_CTXT_REG_ADDR_REGMAP
- * @brief Logical address of REGMAP NPE internal Context Store register
- */
-#define IX_NPEDL_CTXT_REG_ADDR_REGMAP     0x0000001E
-
-/**
- * @def IX_NPEDL_CTXT_REG_ADDR_CINDEX
- * @brief Logical address of CINDEX NPE internal Context Store register
- */
-#define IX_NPEDL_CTXT_REG_ADDR_CINDEX     0x0000001F
-
-
-/*
- * NPE Context Store register reset values
- */
-
-/**
- * @def IX_NPEDL_CTXT_REG_RESET_STEVT
- * @brief Reset value of STEVT NPE internal Context Store register
- *        (STEVT = off, 0x80)
- */
-#define IX_NPEDL_CTXT_REG_RESET_STEVT     0x80
-
-/**
- * @def IX_NPEDL_CTXT_REG_RESET_STARTPC
- * @brief Reset value of STARTPC NPE internal Context Store register
- *        (STARTPC = 0x0000)
- */
-#define IX_NPEDL_CTXT_REG_RESET_STARTPC   0x0000
-
-/**
- * @def IX_NPEDL_CTXT_REG_RESET_REGMAP
- * @brief Reset value of REGMAP NPE internal Context Store register
- *        (REGMAP = d0->p0, d8->p2, d16->p4)
- */
-#define IX_NPEDL_CTXT_REG_RESET_REGMAP    0x0820
-
-/**
- * @def IX_NPEDL_CTXT_REG_RESET_CINDEX
- * @brief Reset value of CINDEX NPE internal Context Store register
- *        (CINDEX = 0)
- */
-#define IX_NPEDL_CTXT_REG_RESET_CINDEX    0x00
-
-
-/*
- * numeric range of context levels available on an NPE
- */
-
-/**
- * @def IX_NPEDL_CTXT_NUM_MIN
- * @brief Lowest NPE Context number in range
- */
-#define IX_NPEDL_CTXT_NUM_MIN             0
-
-/**
- * @def IX_NPEDL_CTXT_NUM_MAX
- * @brief Highest NPE Context number in range
- */
-#define IX_NPEDL_CTXT_NUM_MAX             15
-
-
-/*
- * Physical NPE internal registers
- */
-
-/**
- * @def IX_NPEDL_TOTAL_NUM_PHYS_REG
- * @brief Number of Physical registers currently supported
- *        Initial NPE implementations will have a 32-word register file.
- *        Later implementations may have a 64-word register file.
- */
-#define IX_NPEDL_TOTAL_NUM_PHYS_REG               32
-
-/**
- * @def IX_NPEDL_OFFSET_PHYS_REG_ADDR_REGMAP
- * @brief LSB-offset of Regmap number in Physical NPE register address, used
- *        for Physical To Logical register address mapping in the NPE
- */
-#define IX_NPEDL_OFFSET_PHYS_REG_ADDR_REGMAP      1
-
-/**
- * @def IX_NPEDL_MASK_PHYS_REG_ADDR_LOGICAL_ADDR
- * @brief Mask to extract a logical NPE register address from a physical
- *        register address, used for Physical To Logical address mapping
- */
-#define IX_NPEDL_MASK_PHYS_REG_ADDR_LOGICAL_ADDR   0x1
-
-#endif /* IXNPEDLNPEMGRECREGISTERS_P_H */
diff --git a/drivers/net/npe/include/IxNpeDlNpeMgrUtils_p.h b/drivers/net/npe/include/IxNpeDlNpeMgrUtils_p.h
deleted file mode 100644
index bb1f4abdf9..0000000000
--- a/drivers/net/npe/include/IxNpeDlNpeMgrUtils_p.h
+++ /dev/null
@@ -1,381 +0,0 @@
-/**
- * @file IxNpeDlNpeMgrUtils_p.h
- *
- * @author Intel Corporation
- * @date 18 February 2002
- * @brief This file contains the private API for the NpeMgr module.
- *
- * 
- * @par
- * IXP400 SW Release version 2.0
- * 
- * -- Copyright Notice --
- * 
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- * 
- * @par
- * SPDX-License-Identifier:	BSD-3-Clause
- * @par
- * -- End of Copyright Notice --
-*/
-
-
-/**
- * @defgroup IxNpeDlNpeMgrUtils_p IxNpeDlNpeMgrUtils_p
- *
- * @brief The private API for the IxNpeDl NpeMgr Utils module
- * 
- * @{
- */
-
-#ifndef IXNPEDLNPEMGRUTILS_P_H
-#define IXNPEDLNPEMGRUTILS_P_H
-
-
-/*
- * Put the user defined include files required.
- */
-#include "IxNpeDl.h"
-#include "IxOsalTypes.h"
-#include "IxNpeDlNpeMgrEcRegisters_p.h"
-
-
-/*
- * Function Prototypes
- */
-
-/**
- * @fn IX_STATUS ixNpeDlNpeMgrInsMemWrite (UINT32 npeBaseAddress,
-                                           UINT32 insMemAddress,
-			                   UINT32 insMemData,
-                                           BOOL verify)
- * 
- * @brief Writes a word to NPE Instruction memory
- *
- * @param UINT32 [in] npeBaseAddress - Base Address of NPE
- * @param UINT32 [in] insMemAddress  - NPE instruction memory address to write
- * @param UINT32 [in] insMemData     - data to write to instruction memory
- * @param BOOL   [in] verify         - if true, verify the memory location is
- *                                     written successfully.
- * 
- * This function is used to write a single word of data to a location in NPE 
- * instruction memory.  If the <i>verify</i> option is ON, NpeDl will read back
- * from the memory location to verify that it was written successfully
- * 
- * @pre
- *
- * @post
- *
- * @return
- *    - IX_FAIL if verify is true and the memory location was not written
- *      successfully
- *    - IX_SUCCESS otherwise
- */ 
-IX_STATUS
-ixNpeDlNpeMgrInsMemWrite (UINT32 npeBaseAddress, UINT32 insMemAddress,
-			  UINT32 insMemData, BOOL verify);
-
-
-/**
- * @fn IX_STATUS ixNpeDlNpeMgrDataMemWrite (UINT32 npeBaseAddress,
-                                            UINT32 dataMemAddress,
-	                                    UINT32 dataMemData,
-                                            BOOL verify)
- * 
- * @brief Writes a word to NPE Data memory
- *
- * @param UINT32 [in] npeBaseAddress - Base Address of NPE
- * @param UINT32 [in] dataMemAddress - NPE data memory address to write
- * @param UINT32 [in] dataMemData    - data to write to NPE data memory
- * @param BOOL   [in] verify         - if true, verify the memory location is
- *                                     written successfully.
- * 
- * This function is used to write a single word of data to a location in NPE 
- * data memory.  If the <i>verify</i> option is ON, NpeDl will read back from
- * the memory location to verify that it was written successfully
- * 
- * @pre
- *
- * @post
- *
- * @return
- *    - IX_FAIL if verify is true and the memory location was not written
- *      successfully
- *    - IX_SUCCESS otherwise
- */ 
-IX_STATUS
-ixNpeDlNpeMgrDataMemWrite (UINT32 npeBaseAddress, UINT32 dataMemAddress,
-			   UINT32 dataMemData, BOOL verify);
-
-
-/**
- * @fn void ixNpeDlNpeMgrExecAccRegWrite (UINT32 npeBaseAddress,
-                                          UINT32 regAddress,
-                                          UINT32 regData)
- * 
- * @brief Writes a word to an NPE Execution Access register
- *
- * @param UINT32 [in] npeBaseAddress - Base Address of NPE
- * @param UINT32 [in] regAddress     - NPE Execution Access register address
- * @param UINT32 [in] regData        - data to write to register
- * 
- * This function is used to write a single word of data to an NPE Execution
- * Access register.
- * 
- * @pre
- *
- * @post
- *
- * @return none
- */ 
-void
-ixNpeDlNpeMgrExecAccRegWrite (UINT32 npeBaseAddress, UINT32 regAddress,
-			      UINT32 regData);
-
-
-/**
- * @fn UINT32 ixNpeDlNpeMgrExecAccRegRead (UINT32 npeBaseAddress,
-                                           UINT32 regAddress)
- * 
- * @brief Reads the contents of an NPE Execution Access register
- *
- * @param UINT32 [in] npeBaseAddress - Base Address of NPE
- * @param UINT32 [in] regAddress     - NPE Execution Access register address
- * 
- * This function is used to read the contents of an NPE Execution
- * Access register.
- * 
- * @pre
- *
- * @post
- *
- * @return The value read from the Execution Access register
- */ 
-UINT32
-ixNpeDlNpeMgrExecAccRegRead (UINT32 npeBaseAddress, UINT32 regAddress);
-
-
-/**
- * @fn void ixNpeDlNpeMgrCommandIssue (UINT32 npeBaseAddress,
-                                       UINT32 command)
- * 
- * @brief Issues an NPE Execution Control command
- *
- * @param UINT32 [in] npeBaseAddress - Base Address of NPE
- * @param UINT32 [in] command        - Command to issue
- * 
- * This function is used to issue a stand-alone NPE Execution Control command
- * (e.g. command to Stop NPE execution)
- * 
- * @pre
- *
- * @post
- *
- * @return none
- */ 
-void
-ixNpeDlNpeMgrCommandIssue (UINT32 npeBaseAddress, UINT32 command);
-
-
-/**
- * @fn void ixNpeDlNpeMgrDebugInstructionPreExec (UINT32 npeBaseAddress)
- * 
- * @brief Prepare to executes one or more NPE instructions in the Debug
- *        Execution Stack level.
- *
- * @param UINT32 [in] npeBaseAddress - Base Address of NPE
- * 
- * This function should be called once before a sequence of calls to 
- * ixNpeDlNpeMgrDebugInstructionExec().
- * 
- * @pre
- *
- * @post
- *     - ixNpeDlNpeMgrDebugInstructionPostExec() should be called to restore
- *       registers values altered by this function
- *
- * @return none
- */ 
-void
-ixNpeDlNpeMgrDebugInstructionPreExec (UINT32 npeBaseAddress);
-
-
-/**
- * @fn IX_STATUS ixNpeDlNpeMgrDebugInstructionExec (UINT32 npeBaseAddress,
-                                               UINT32 npeInstruction,
-                                               UINT32 ctxtNum,
-                                               UINT32 ldur)
- * 
- * @brief Executes a single instruction on the NPE at the Debug Execution Stack
- *        level
- *
- * @param UINT32 [in] npeBaseAddress - Base Address of NPE
- * @param UINT32 [in] npeInstruction - Value to write to INSTR (Instruction)
- *                                     register
- * @param UINT32 [in] ctxtNum        - context the instruction will be executed
- *                                     in and which context store it may access
- * @param UINT32 [in] ldur           - Long Immediate Duration, set to non-zero
- *                                     to use long-immediate mode instruction
- * 
- * This function is used to execute a single instruction in the NPE pipeline at
- * the debug Execution Context Stack level. It won't disturb the state of other
- * executing contexts.  Its useful for performing NPE operations, such as
- * writing to NPE Context Store registers and physical registers, that cannot
- * be carried out directly using the Configuration Bus registers. This function
- * will return TIMEOUT status if NPE not responding due to NPS is hang / halt.
- * 
- * @pre 
- *     - The NPE should be stopped and in a clean state
- *     - ixNpeDlNpeMgrDebugInstructionPreExec() should be called once before
- *       a sequential of 1 or more calls to this function
- *
- * @post
- *     - ixNpeDlNpeMgrDebugInstructionPostExec() should be called after 
- *       a sequence of calls to this function
- *
- * @return 
- *    - IX_NPEDL_CRITICAL_NPE_ERR if execution of instruction failed / timeout
- *    - IX_SUCCESS otherwise 
- */ 
-IX_STATUS
-ixNpeDlNpeMgrDebugInstructionExec (UINT32 npeBaseAddress,
-				   UINT32 npeInstruction,
-				   UINT32 ctxtNum, UINT32 ldur);
-
-
-/**
- * @fn void ixNpeDlNpeMgrDebugInstructionPostExec (UINT32 npeBaseAddress)
- * 
- * @brief Clean up after executing one or more NPE instructions in the
- *        Debug Stack Level
- *
- * @param UINT32 [in] npeBaseAddress - Base Address of NPE
- * 
- * This function should be called once following a sequence of calls to 
- * ixNpeDlNpeMgrDebugInstructionExec().
- *
- * @pre 
- *    -  ixNpeDlNpeMgrDebugInstructionPreExec() was called earlier
- *
- * @post
- *    -  The Instruction Pipeline will cleared
- *
- * @return none
- */ 
-void
-ixNpeDlNpeMgrDebugInstructionPostExec (UINT32 npeBaseAddress);
-
-
-/**
- * @fn IX_STATUS ixNpeDlNpeMgrPhysicalRegWrite (UINT32 npeBaseAddress,
-                                                UINT32 regAddr,
-                                                UINT32 regValue,
-					        BOOL verify)
- * 
- * @brief Write one of the 32* 32-bit physical registers in the NPE data 
- *        register file
- *
- * @param UINT32 [in] npeBaseAddress - Base Address of NPE
- * @param UINT32 [in] regAddr        - number of the physical register (0-31)*
- * @param UINT32 [in] regValue       - value to write to the physical register
- * @param BOOL   [in] verify         - if true, verify the register is written
- *                                     successfully.
- * 
- * This function writes a physical register in the NPE data register file.
- * If the <i>verify</i> option is ON, NpeDl will read back the register to 
- * verify that it was written successfully
- * *Note that release 1.0 of this software supports 32 physical
- * registers, but 64 may be supported in future versions.
- * 
- * @pre
- *    - The NPE should be stopped and in a clean state
- *    - ixNpeDlNpeMgrDebugInstructionPreExec() should be called once before
- *      a sequential of 1 or more calls to this function
- *
- * @post
- *    - Contents of REGMAP Context Store register for Context 0 will be altered
- *    - ixNpeDlNpeMgrDebugInstructionPostExec() should be called after 
- *      a sequence of calls to this function
- *
- * @return
- *    - IX_FAIL if verify is true and the Context Register was not written
- *      successfully
- *    - IX_SUCCESS if Context Register was written successfully
- *    - IX_NPEDL_CRITICAL_NPE_ERR if Context Register was not written 
- *      successfully due to timeout error where NPE is not responding
- */
-IX_STATUS
-ixNpeDlNpeMgrPhysicalRegWrite (UINT32 npeBaseAddress, UINT32 regAddr,
-			       UINT32 regValue, BOOL verify);
-
-
-/**
- * @fn IX_STATUS ixNpeDlNpeMgrCtxtRegWrite (UINT32 npeBaseAddress,
-                                            UINT32 ctxtNum,
-                                            IxNpeDlCtxtRegNum ctxtReg,
-                                            UINT32 ctxtRegVal,
-                                            BOOL verify)
- * 
- * @brief Writes a value to a Context Store register on an NPE
- *
- * @param UINT32 [in] npeBaseAddress     - Base Address of NPE
- * @param UINT32 [in] ctxtNum            - context store to access
- * @param IxNpeDlCtxtRegNum [in] ctxtReg - which Context Store reg to write
- * @param UINT32 [in] ctxtRegVal         - value to write to the Context Store
- *                                         register
- * @param BOOL   [in] verify             - if true, verify the register is
- *                                         written successfully.
- * 
- * This function writes the contents of a Context Store register in the NPE 
- * register file. If the <i>verify</i> option is ON, NpeDl will read back the
- * register to verify that it was written successfully
- * 
- * @pre
- *    - The NPE should be stopped and in a clean state
- *    - ixNpeDlNpeMgrDebugInstructionPreExec() should be called once before
- *      a sequential of 1 or more calls to this function
- *
- * @post
- *    - ixNpeDlNpeMgrDebugInstructionPostExec() should be called after 
- *      a sequence of calls to this function
- *
- * @return
- *    - IX_FAIL if verify is true and the Context Register was not written
- *      successfully
- *    - IX_SUCCESS if Context Register was written successfully
- *    - IX_NPEDL_CRITICAL_NPE_ERR if Context Register was not written 
- *      successfully due to timeout error where NPE is not responding
- */
-IX_STATUS
-ixNpeDlNpeMgrCtxtRegWrite (UINT32 npeBaseAddress, UINT32 ctxtNum,
-			   IxNpeDlCtxtRegNum ctxtReg, UINT32 ctxtRegVal,
-			   BOOL verify);
-
-
-/**
- * @fn void ixNpeDlNpeMgrUtilsStatsShow (void)
- *
- * @brief This function will display the statistics of the IxNpeDl NpeMgrUtils
- *        module
- *
- * @return none
- */
-void
-ixNpeDlNpeMgrUtilsStatsShow (void);
-
-
-/**
- * @fn void ixNpeDlNpeMgrUtilsStatsReset (void)
- *
- * @brief This function will reset the statistics of the IxNpeDl NpeMgrUtils
- *        module
- *
- * @return none
- */
-void
-ixNpeDlNpeMgrUtilsStatsReset (void);
-
-
-#endif  /* IXNPEDLNPEMGRUTILS_P_H */
diff --git a/drivers/net/npe/include/IxNpeDlNpeMgr_p.h b/drivers/net/npe/include/IxNpeDlNpeMgr_p.h
deleted file mode 100644
index 989db2c57e..0000000000
--- a/drivers/net/npe/include/IxNpeDlNpeMgr_p.h
+++ /dev/null
@@ -1,236 +0,0 @@
-/**
- * @file IxNpeDlNpeMgr_p.h
- *
- * @author Intel Corporation
- * @date 14 December 2001
- * @brief This file contains the private API for the NpeMgr module.
- *
- * 
- * @par
- * IXP400 SW Release version 2.0
- * 
- * -- Copyright Notice --
- * 
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- * 
- * @par
- * SPDX-License-Identifier:	BSD-3-Clause
- * @par
- * -- End of Copyright Notice --
-*/
-
-
-/**
- * @defgroup IxNpeDlNpeMgr_p IxNpeDlNpeMgr_p
- *
- * @brief The private API for the IxNpeDl NpeMgr module
- * 
- * @{
- */
-
-#ifndef IXNPEDLNPEMGR_P_H
-#define IXNPEDLNPEMGR_P_H
-
-
-/*
- * Put the user defined include files required.
- */
-#include "IxNpeDl.h"
-#include "IxOsalTypes.h"
-
-
-/*
- * Function Prototypes
- */
-
-
-/**
- * @fn void ixNpeDlNpeMgrInit (void)
- * 
- * @brief Initialises the NpeMgr module
- *
- * @param none
- * 
- * This function initialises the NpeMgr module.
- * It should be called before any other function in this module is called.
- * It only needs to be called once, but can be called multiple times safely.
- * The code will ASSERT on failure.
- * 
- * @pre
- *     - It must be called before any other function in this module
- *
- * @post
- *     - NPE Configuration Register memory space will be mapped using
- *       IxOsal. This memory will not be unmapped by this module.
- *
- * @return none
- */ 
-void
-ixNpeDlNpeMgrInit (void);
-
-
-/**
- * @fn IX_STATUS ixNpeMhNpeMgrUninit (void)
- *
- * @brief This function will uninitialise the IxNpeDlNpeMgr sub-component.
- *
- * This function will uninitialise the IxNpeDlNpeMgr sub-component.
- * It should only be called once, and only if the IxNpeDlNpeMgr sub-component
- * has already been initialised by calling @ref ixNpeDlNpeMgrInit().
- * No other IxNpeDlNpeMgr sub-component API functions should be called
- * until @ref ixNpeDlNpeMgrInit() is called again.
- * If possible, this function should be called before a soft reboot or unloading
- * a kernel module to perform any clean up operations required for IxNpeMh.
- *
- * @return
- *      - IX_SUCCESS if the operation was successful
- *      - IX_FAIL otherwise
- */
-
-IX_STATUS ixNpeDlNpeMgrUninit (void);
-
-
-/**
- * @fn IX_STATUS ixNpeDlNpeMgrImageLoad (IxNpeDlNpeId npeId,
-                                           UINT32 *imageCodePtr,
-                                           BOOL verify)
- * 
- * @brief Loads a image of microcode onto an NPE
- *
- * @param IxNpeDlNpeId [in] npeId     - Id of target NPE
- * @param UINT32* [in] imageCodePtr - pointer to image code in image to be
- *                                      downloaded
- * @param BOOL [in] verify            - if true, verify each word written to
- *                                      NPE memory.
- * 
- * This function loads a image containing blocks of microcode onto a
- * particular NPE. If the <i>verify</i> option is ON, NpeDl will read back each
- * word written and verify that it was written successfully
- * 
- * @pre
- *     - The NPE should be stopped beforehand
- *
- * @post
- *     - The NPE Instruction Pipeline may be flushed clean
- *
- * @return
- *     - IX_SUCCESS if the download was successful
- *     - IX_FAIL if the download failed
- *     - IX_NPEDL_CRITICAL_NPE_ERR if the download failed due to timeout error 
- *       where NPE is not responding
- */ 
-IX_STATUS
-ixNpeDlNpeMgrImageLoad (IxNpeDlNpeId npeId, UINT32 *imageCodePtr,
-			  BOOL verify);
-
-
-/**
- * @fn IX_STATUS ixNpeDlNpeMgrNpeReset (IxNpeDlNpeId npeId)
- * 
- * @brief sets a NPE to RESET state
- *
- * @param IxNpeDlNpeId [in] npeId - id of target NPE
- * 
- * This function performs a soft NPE reset by writing reset values to the
- * Configuration Bus Execution Control registers, the Execution Context Stack
- * registers, the Physical Register file, and the Context Store registers for 
- * each context number. It also clears inFIFO, outFIFO and Watchpoint FIFO.
- * It does not reset NPE Co-processors.
- * 
- * @pre
- *     - The NPE should be stopped beforehand
- *
- * @post
- *     - NPE NextProgram Counter (NextPC) will be set to a fixed initial value,
- *       such as 0.  This should be explicitly set by downloading State
- *       Information before starting NPE Execution.
- *     - The NPE Instruction Pipeline will be in a clean state.
- *
- * @return
- *     - IX_SUCCESS if the operation was successful
- *     - IX_FAIL if the operation failed
- *     - IX_NPEDL_CRITICAL_NPE_ERR if the operation failed due to NPE hang
- */ 
-IX_STATUS
-ixNpeDlNpeMgrNpeReset (IxNpeDlNpeId npeId);
-
-
-/**
- * @fn IX_STATUS ixNpeDlNpeMgrNpeStart (IxNpeDlNpeId npeId)
- * 
- * @brief Starts NPE Execution
- *
- * @param IxNpeDlNpeId [in] npeId - Id of target NPE
- * 
- * Ensures only background Execution Stack Level is Active, clears instruction
- * pipeline, and starts Execution on a NPE by sending a Start NPE command to
- * the NPE. Checks the execution status of the NPE to verify that it is
- * running.
- * 
- * @pre
- *     - The NPE should be stopped beforehand.
- *     - Note that this function does not set the NPE Next Program Counter 
- *       (NextPC), so it should be set beforehand if required by downloading 
- *       appropriate State Information.
- *
- * @post
- *
- * @return
- *     - IX_SUCCESS if the operation was successful
- *     - IX_FAIL otherwise
- */ 
-IX_STATUS
-ixNpeDlNpeMgrNpeStart (IxNpeDlNpeId npeId);
-
-
-/**
- * @fn IX_STATUS ixNpeDlNpeMgrNpeStop (IxNpeDlNpeId npeId)
- * 
- * @brief Halts NPE Execution
- *
- * @param IxNpeDlNpeId [in] npeId - id of target NPE
- * 
- * Stops execution on an NPE by sending a Stop NPE command to the NPE.
- * Checks the execution status of the NPE to verify that it has stopped.
- *
- * @pre
- *
- * @post
- *
- * @return 
- *     - IX_SUCCESS if the operation was successful
- *     - IX_FAIL otherwise
- */ 
-IX_STATUS
-ixNpeDlNpeMgrNpeStop (IxNpeDlNpeId npeId);
-
-
-/**
- * @fn void ixNpeDlNpeMgrStatsShow (void)
- *
- * @brief This function will display statistics of the IxNpeDl NpeMgr module
- *
- * @return none
- */
-void
-ixNpeDlNpeMgrStatsShow (void);
-
-
-/**
- * @fn void ixNpeDlNpeMgrStatsReset (void)
- *
- * @brief This function will reset the statistics of the IxNpeDl NpeMgr module
- *
- * @return none
- */
-void
-ixNpeDlNpeMgrStatsReset (void);
-
-
-#endif /* IXNPEDLIMAGEMGR_P_H */
-
-/**
- * @} defgroup IxNpeDlNpeMgr_p
- */
diff --git a/drivers/net/npe/include/IxNpeMh.h b/drivers/net/npe/include/IxNpeMh.h
deleted file mode 100644
index 3a2bf9fa48..0000000000
--- a/drivers/net/npe/include/IxNpeMh.h
+++ /dev/null
@@ -1,473 +0,0 @@
-/**
- * @file IxNpeMh.h
- *
- * @date 14 Dec 2001
- *
- * @brief This file contains the public API for the IXP400 NPE Message
- * Handler component.
- *
- * 
- * @par
- * IXP400 SW Release version 2.0
- * 
- * -- Copyright Notice --
- * 
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- * 
- * @par
- * SPDX-License-Identifier:	BSD-3-Clause
- * @par
- * -- End of Copyright Notice --
-*/
-
-/**
- * @defgroup IxNpeMh IXP400 NPE Message Handler (IxNpeMh) API
- *
- * @brief The public API for the IXP400 NPE Message Handler component.
- * 
- * @{
- */
-
-#ifndef IXNPEMH_H
-#define IXNPEMH_H
-
-#include "IxOsalTypes.h"
-
-/*
- * #defines for function return types, etc.
- */
-
-#define IX_NPEMH_MIN_MESSAGE_ID (0x00) /**< minimum valid message ID */
-#define IX_NPEMH_MAX_MESSAGE_ID (0xFF) /**< maximum valid message ID */
-
-#define IX_NPEMH_SEND_RETRIES_DEFAULT (3) /**< default msg send retries */
-
-
-/**
- * @def IX_NPEMH_CRITICAL_NPE_ERR
- *
- * @brief NpeMH function return value for a Critical NPE error occuring during
-          sending/receiving message. Assume NPE hang / halt if this value is
-          returned.
- */
-#define IX_NPEMH_CRITICAL_NPE_ERR        2
-
-/**
- * @enum IxNpeMhNpeId
- *
- * @brief The ID of a particular NPE.
- * @note In this context, for IXP425 Silicon (B0):<br> 
- *      - NPE-A has HDLC, HSS, AAL and UTOPIA Coprocessors.<br> 
- *      - NPE-B has Ethernet Coprocessor.<br>
- *      - NPE-C has Ethernet, AES, DES and HASH Coprocessors.<br>
- *      - IXP400 Product Line have different combinations of coprocessors. 
- */
-
-typedef enum
-{
-    IX_NPEMH_NPEID_NPEA = 0, /**< ID for NPE-A */
-    IX_NPEMH_NPEID_NPEB,     /**< ID for NPE-B */
-    IX_NPEMH_NPEID_NPEC,     /**< ID for NPE-C */
-    IX_NPEMH_NUM_NPES        /**< Number of NPEs */
-} IxNpeMhNpeId;
-
-/**
- * @enum IxNpeMhNpeInterrupts
- *
- * @brief Indicator specifying whether or not NPE interrupts should drive
- * receiving of messages from the NPEs.
- */
-
-typedef enum
-{
-    IX_NPEMH_NPEINTERRUPTS_NO = 0, /**< Don't use NPE interrupts */
-    IX_NPEMH_NPEINTERRUPTS_YES     /**< Do use NPE interrupts */
-} IxNpeMhNpeInterrupts;
-
-/**
- * @brief The 2-word message structure to send to and receive from the
- * NPEs.
- */
-
-typedef struct
-{
-    UINT32 data[2]; /**< the actual data of the message */
-} IxNpeMhMessage;
-
-/** message ID */
-typedef UINT32 IxNpeMhMessageId;
-
-/**
- * @typedef IxNpeMhCallback
- *
- * @brief This prototype shows the format of a message callback function.
- *
- * This prototype shows the format of a message callback function.  The
- * message callback will be passed the message to be handled and will also
- * be told from which NPE the message was received.  The message callback
- * will either be registered by ixNpeMhUnsolicitedCallbackRegister() or
- * passed as a parameter to ixNpeMhMessageWithResponseSend().  It will be
- * called from within an ISR triggered by the NPE's "outFIFO not empty"
- * interrupt (see ixNpeMhInitialize()).  The parameters passed are the ID
- * of the NPE that the message was received from, and the message to be
- * handled.<P><B>Re-entrancy:</B> This function is only a prototype, and
- * will be implemented by the client.  It does not need to be re-entrant.
- */
-
-typedef void (*IxNpeMhCallback) (IxNpeMhNpeId, IxNpeMhMessage);
-
-/*
- * Prototypes for interface functions.
- */
-
-/**
- * @ingroup IxNpeMh
- *
- * @fn IX_STATUS ixNpeMhInitialize (
-           IxNpeMhNpeInterrupts npeInterrupts)
- *
- * @brief This function will initialise the IxNpeMh component.
- *
- * @param npeInterrupts @ref IxNpeMhNpeInterrupts [in] - This parameter
- * dictates whether or not the IxNpeMh component will service NPE "outFIFO
- * not empty" interrupts to trigger receiving and processing of messages
- * from the NPEs.  If not then the client must use ixNpeMhMessagesReceive()
- * to control message receiving and processing.
- *
- * This function will initialise the IxNpeMh component.  It should only be
- * called once, prior to using the IxNpeMh component.  The following
- * actions will be performed by this function:<OL><LI>Initialization of
- * internal data structures (e.g. solicited and unsolicited callback
- * tables).</LI><LI>Configuration of the interface with the NPEs (e.g.
- * enabling of NPE "outFIFO not empty" interrupts).</LI><LI>Registration of
- * ISRs that will receive and handle messages when the NPEs' "outFIFO not
- * empty" interrupts fire (if npeInterrupts equals
- * IX_NPEMH_NPEINTERRUPTS_YES).</LI></OL>
- *
- * @return The function returns a status indicating success or failure.
- */
-
-PUBLIC IX_STATUS ixNpeMhInitialize (
-    IxNpeMhNpeInterrupts npeInterrupts);
-
-/**
- * @ingroup IxNpeMh
- *
- * @fn IX_STATUS ixNpeMhUnload (void)
- *
- * @brief This function will uninitialise the IxNpeMh component.
- *
- * This function will uninitialise the IxNpeMh component.  It should only be
- * called once, and only if the IxNpeMh component has already been initialised.
- * No other IxNpeMh API functions should be called until @ref ixNpeMhInitialize
- * is called again.
- * If possible, this function should be called before a soft reboot or unloading
- * a kernel module to perform any clean up operations required for IxNpeMh.
- *
- * The following actions will be performed by this function:
- * <OL><LI>Unmapping of kernel memory mapped by the function
- * @ref ixNpeMhInitialize.</LI></OL>
- *
- * @return The function returns a status indicating success or failure.
- */
-
-PUBLIC IX_STATUS ixNpeMhUnload (void);
-
-/**
- * @ingroup IxNpeMh
- *
- * @fn IX_STATUS ixNpeMhUnsolicitedCallbackRegister (
-           IxNpeMhNpeId npeId,
-           IxNpeMhMessageId messageId,
-           IxNpeMhCallback unsolicitedCallback)
- *
- * @brief This function will register an unsolicited callback for a
- * particular NPE and message ID.
- *
- * @param npeId @ref IxNpeMhNpeId [in] - The ID of the NPE whose messages
- * the unsolicited callback will handle.
- * @param messageId @ref IxNpeMhMessageId [in] - The ID of the messages the
- * unsolicited callback will handle.
- * @param unsolicitedCallback @ref IxNpeMhCallback [in] - The unsolicited
- * callback function.  A value of NULL will deregister any previously
- * registered callback for this NPE and message ID.
- *
- * This function will register an unsolicited message callback for a
- * particular NPE and message ID.<P>If an unsolicited callback is already
- * registered for the specified NPE and message ID then the callback will
- * be overwritten.  Only one client will be responsible for handling a
- * particular message ID associated with a NPE.  Registering a NULL
- * unsolicited callback will deregister any previously registered
- * callback.<P>The callback function will be called from an ISR that will
- * be triggered by the NPE's "outFIFO not empty" interrupt (see
- * ixNpeMhInitialize()) to handle any unsolicited messages of the specific
- * message ID received from the NPE.  Unsolicited messages will be handled
- * in the order they are received.<P>If no unsolicited callback can be
- * found for a received message then it is assumed that the message is
- * solicited.<P>If more than one client may be interested in a particular
- * unsolicited message then the suggested strategy is to register a
- * callback for the message that can itself distribute the message to
- * multiple clients as necessary.<P>See also
- * ixNpeMhUnsolicitedCallbackForRangeRegister().<P><B>Re-entrancy:</B> This
- * function will be callable from any thread at any time.  IxOsal
- * will be used for any necessary resource protection.
- *
- * @return The function returns a status indicating success or failure.
- */
-
-PUBLIC IX_STATUS ixNpeMhUnsolicitedCallbackRegister (
-    IxNpeMhNpeId npeId,
-    IxNpeMhMessageId messageId,
-    IxNpeMhCallback unsolicitedCallback);
-
-/**
- * @ingroup IxNpeMh
- *
- * @fn IX_STATUS ixNpeMhUnsolicitedCallbackForRangeRegister (
-           IxNpeMhNpeId npeId,
-           IxNpeMhMessageId minMessageId,
-           IxNpeMhMessageId maxMessageId,
-           IxNpeMhCallback unsolicitedCallback)
- *
- * @brief This function will register an unsolicited callback for a
- * particular NPE and range of message IDs.
- *
- * @param npeId @ref IxNpeMhNpeId [in] - The ID of the NPE whose messages the
- * unsolicited callback will handle.
- * @param minMessageId @ref IxNpeMhMessageId [in] - The minimum message ID in
- * the range of message IDs the unsolicited callback will handle.
- * @param maxMessageId @ref IxNpeMhMessageId [in] - The maximum message ID in
- * the range of message IDs the unsolicited callback will handle.
- * @param unsolicitedCallback @ref IxNpeMhCallback [in] - The unsolicited
- * callback function.  A value of NULL will deregister any previously
- * registered callback(s) for this NPE and range of message IDs.
- *
- * This function will register an unsolicited callback for a particular NPE
- * and range of message IDs.  It is a convenience function that is
- * effectively the same as calling ixNpeMhUnsolicitedCallbackRegister() for
- * each ID in the specified range.  See
- * ixNpeMhUnsolicitedCallbackRegister() for more
- * information.<P><B>Re-entrancy:</B> This function will be callable from
- * any thread at any time.  IxOsal will be used for any necessary
- * resource protection.
- *
- * @return The function returns a status indicating success or failure.
- */
-
-PUBLIC IX_STATUS ixNpeMhUnsolicitedCallbackForRangeRegister (
-    IxNpeMhNpeId npeId,
-    IxNpeMhMessageId minMessageId,
-    IxNpeMhMessageId maxMessageId,
-    IxNpeMhCallback unsolicitedCallback);
-
-/**
- * @ingroup IxNpeMh
- *
- * @fn IX_STATUS ixNpeMhMessageSend (
-           IxNpeMhNpeId npeId,
-           IxNpeMhMessage message,
-           UINT32 maxSendRetries)
- *
- * @brief This function will send a message to a particular NPE.
- *
- * @param npeId @ref IxNpeMhNpeId [in] - The ID of the NPE to send the message
- * to.
- * @param message @ref IxNpeMhMessage [in] - The message to send.
- * @param maxSendRetries UINT32 [in] - Max num. of retries to perform
- * if the NPE's inFIFO is full.
- *
- * This function will send a message to a particular NPE.  It will be the
- * client's responsibility to ensure that the message is properly formed.
- * The return status will signify to the client if the message was
- * successfully sent or not.<P>If the message is sent to the NPE then this
- * function will return a status of success.  Note that this will only mean
- * the message has been placed in the NPE's inFIFO.  There will be no way
- * of knowing that the NPE has actually read the message, but once in the
- * incoming message queue it will be safe to assume that the NPE will
- * process it.
- * <P>The inFIFO may fill up sometimes if the Xscale is sending messages
- * faster than the NPE can handle them. This forces us to retry attempts 
- * to send the message until the NPE services the inFIFO. The client should
- * specify a ceiling value for the number of retries suitable to their
- * needs. IX_NPEMH_SEND_RETRIES_DEFAULT can be used as a default value for
- * the <i>maxSendRetries</i> parameter for this function. Each retry
- * exceeding this default number will incur a blocking delay of 1 microsecond,
- * to avoid consuming too much AHB bus bandwidth while performing retries.
- * <P>Note this function <B>must</B> only be used for messages.
- * that do not solicit responses. If the message being sent will solicit a
- * response then the ixNpeMhMessageWithResponseSend() function <B>must</B>
- * be used to ensure that the response is correctly
- * handled. <P> This function will return timeout status if NPE hang / halt 
- * while sending message. The timeout error is not related to the 
- * <i>maxSendRetries</i> as mentioned above. The timeout error will only occur 
- * if the first word of the message has been sent to NPE (not exceeding 
- * <i>maxSendRetries</i> when sending 1st message word), but the second word of
- * the message can't be written to NPE's inFIFO due to NPE hang / halt after 
- * maximum waiting time (IX_NPE_MH_MAX_NUM_OF_RETRIES). 
- * <P><B>Re-entrancy:</B> This function will be callable from any
- * thread at any time.  IxOsal will be used for any necessary
- * resource protection.
- *
- * @return The function returns a status indicating success, failure or timeout.
- */
-
-PUBLIC IX_STATUS ixNpeMhMessageSend (
-    IxNpeMhNpeId npeId,
-    IxNpeMhMessage message,
-    UINT32 maxSendRetries);
-
-/**
- * @ingroup IxNpeMh
- *
- * @fn IX_STATUS ixNpeMhMessageWithResponseSend (
-           IxNpeMhNpeId npeId,
-           IxNpeMhMessage message,
-           IxNpeMhMessageId solicitedMessageId,
-           IxNpeMhCallback solicitedCallback,
-           UINT32 maxSendRetries)
- *
- * @brief This function is equivalent to the ixNpeMhMessageSend() function,
- * but must be used when the message being sent will solicited a response.
- *
- * @param npeId @ref IxNpeMhNpeId [in] - The ID of the NPE to send the message
- * to.
- * @param message @ref IxNpeMhMessage [in] - The message to send.
- * @param solicitedMessageId @ref IxNpeMhMessageId [in] - The ID of the
- * solicited response message.
- * @param solicitedCallback @ref IxNpeMhCallback [in] - The function to use to
- * pass the response message back to the client.  A value of NULL will
- * cause the response message to be discarded.
- * @param maxSendRetries UINT32 [in] - Max num. of retries to perform
- * if the NPE's inFIFO is full.
- *
- * This function is equivalent to the ixNpeMhMessageSend() function, but
- * must be used when the message being sent will solicited a
- * response.<P>The client must specify the ID of the solicited response
- * message to allow the response to be recognised when it is received.  The
- * client must also specify a callback function to handle the received
- * response.  The IxNpeMh component will not offer the facility to send a
- * message to a NPE and receive a response within the same context.<P>Note
- * if the client is not interested in the response, specifying a NULL
- * callback will cause the response message to be discarded.<P>The
- * solicited callback will be stored and called some time later from an ISR
- * that will be triggered by the NPE's "outFIFO not empty" interrupt (see
- * ixNpeMhInitialize()) to handle the response message corresponding to the
- * message sent.  Response messages will be handled in the order they are
- * received.<P>
- * <P>The inFIFO may fill up sometimes if the Xscale is sending messages
- * faster than the NPE can handle them. This forces us to retry attempts 
- * to send the message until the NPE services the inFIFO. The client should
- * specify a ceiling value for the number of retries suitable to their
- * needs. IX_NPEMH_SEND_RETRIES_DEFAULT can be used as a default value for
- * the <i>maxSendRetries</i> parameter for this function. Each retry
- * exceeding this default number will incur a blocking delay of 1 microsecond,
- * to avoid consuming too much AHB bus bandwidth while performing retries.
- * <P> This function will return timeout status if NPE hang / halt 
- * while sending message. The timeout error is not related to the 
- * <i>maxSendRetries</i> as mentioned above. The timeout error will only occur 
- * if the first word of the message has been sent to NPE (not exceeding 
- * <i>maxSendRetries</i> when sending 1st message word), but the second word of
- * the message can't be written to NPE's inFIFO due to NPE hang / halt after 
- * maximum waiting time (IX_NPE_MH_MAX_NUM_OF_RETRIES). 
- * <P><B>Re-entrancy:</B> This function will be callable from any
- * thread at any time.  IxOsal will be used for any necessary
- * resource protection.
- *
- * @return The function returns a status indicating success or failure.
- */
-
-PUBLIC IX_STATUS ixNpeMhMessageWithResponseSend (
-    IxNpeMhNpeId npeId,
-    IxNpeMhMessage message,
-    IxNpeMhMessageId solicitedMessageId,
-    IxNpeMhCallback solicitedCallback,
-    UINT32 maxSendRetries);
-
-/**
- * @ingroup IxNpeMh
- *
- * @fn IX_STATUS ixNpeMhMessagesReceive (
-           IxNpeMhNpeId npeId)
- *
- * @brief This function will receive messages from a particular NPE and
- * pass each message to the client via a solicited callback (for solicited
- * messages) or an unsolicited callback (for unsolicited messages).
- *
- * @param npeId @ref IxNpeMhNpeId [in] - The ID of the NPE to receive and
- * process messages from.
- *
- * This function will receive messages from a particular NPE and pass each
- * message to the client via a solicited callback (for solicited messages)
- * or an unsolicited callback (for unsolicited messages).<P>If the IxNpeMh
- * component is initialised to service NPE "outFIFO not empty" interrupts
- * (see ixNpeMhInitialize()) then there is no need to call this function.
- * This function is only provided as an alternative mechanism to control
- * the receiving and processing of messages from the NPEs.<P> This function
- * will return timeout status if NPE hang / halt while receiving message. The
- * timeout error will only occur if this function has read the first word of
- * the message and can't read second word of the message from NPE's outFIFO
- * after maximum retries (IX_NPE_MH_MAX_NUM_OF_RETRIES). 
- * <P>Note this function cannot be called from within 
- * an ISR as it will use resource protection mechanisms.<P><B>Re-entrancy:</B> 
- * This function will be callable from any thread at any time.  IxOsal will be 
- * used for any necessary resource protection.
- *
- * @return The function returns a status indicating success, failure or timeout.
- */
-
-PUBLIC IX_STATUS ixNpeMhMessagesReceive (
-    IxNpeMhNpeId npeId);
-
-/**
- * @ingroup IxNpeMh
- *
- * @fn IX_STATUS ixNpeMhShow (
-           IxNpeMhNpeId npeId)
- *
- * @brief This function will display the current state of the IxNpeMh
- * component.
- *
- * <B>Re-entrancy:</B> This function will be callable from
- * any thread at any time.  However, no resource protection will be used
- * so as not to impact system performance.  As this function is only
- * reading statistical information then this is acceptable.
- *
- * @param npeId @ref IxNpeMhNpeId [in] - The ID of the NPE to display state
- * information for.
- *
- * @return The function returns a status indicating success or failure.
- */
-
-PUBLIC IX_STATUS ixNpeMhShow (
-    IxNpeMhNpeId npeId);
-
-/**
- * @ingroup IxNpeMh
- *
- * @fn IX_STATUS ixNpeMhShowReset (
-           IxNpeMhNpeId npeId)
- *
- * @brief This function will reset the current state of the IxNpeMh
- * component.
- *
- * <B>Re-entrancy:</B> This function will be callable from
- * any thread at any time.  However, no resource protection will be used
- * so as not to impact system performance.  As this function is only
- * writing statistical information then this is acceptable.
- *
- * @param npeId @ref IxNpeMhNpeId [in] - The ID of the NPE to reset state
- * information for.
- *
- * @return The function returns a status indicating success or failure.
- */
-
-PUBLIC IX_STATUS ixNpeMhShowReset (
-    IxNpeMhNpeId npeId);
-
-#endif /* IXNPEMH_H */
-
-/**
- * @} defgroup IxNpeMh
- */
diff --git a/drivers/net/npe/include/IxNpeMhConfig_p.h b/drivers/net/npe/include/IxNpeMhConfig_p.h
deleted file mode 100644
index ca47f7f108..0000000000
--- a/drivers/net/npe/include/IxNpeMhConfig_p.h
+++ /dev/null
@@ -1,531 +0,0 @@
-/**
- * @file IxNpeMhConfig_p.h
- *
- * @author Intel Corporation
- * @date 18 Jan 2002
- *
- * @brief This file contains the private API for the Configuration module.
- *
- * 
- * @par
- * IXP400 SW Release version 2.0
- * 
- * -- Copyright Notice --
- * 
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- * 
- * @par
- * SPDX-License-Identifier:	BSD-3-Clause
- * @par
- * -- End of Copyright Notice --
-*/
-
-/**
- * @defgroup IxNpeMhConfig_p IxNpeMhConfig_p
- *
- * @brief The private API for the Configuration module.
- * 
- * @{
- */
-
-#ifndef IXNPEMHCONFIG_P_H
-#define IXNPEMHCONFIG_P_H
-
-#include "IxOsal.h"
-
-#include "IxNpeMh.h"
-#include "IxNpeMhMacros_p.h"
-
-/*
- * inline definition
- */
-/* enable function inlining for performances */
-#ifdef IXNPEMHSOLICITEDCBMGR_C
-/* Non-inline functions will be defined in this translation unit. 
-	 Reason is that in GNU Compiler, if the Optimization is turn off, all extern inline
-	 functions will not be compiled.
-*/
-#		ifndef __wince
-#			ifndef IXNPEMHCONFIG_INLINE
-#				define IXNPEMHCONFIG_INLINE 
-#			endif
-#		else
-#			ifndef IXNPEMHCONFIG_INLINE
-#				define IXNPEMHCONFIG_INLINE IX_OSAL_INLINE_EXTERN
-#			endif
-#		endif /* __wince*/
-
-#else
-
-#		ifndef IXNPEMHCONFIG_INLINE
-#			define IXNPEMHCONFIG_INLINE IX_OSAL_INLINE_EXTERN
-#		endif /* IXNPEMHCONFIG_INLINE */
-#endif /* IXNPEMHSOLICITEDCBMGR_C */
-/*
- * Typedefs and #defines, etc.
- */
- 
-typedef void (*IxNpeMhConfigIsr) (int); /**< ISR function pointer */
-
-/**
- * @struct IxNpeMhConfigNpeInfo
- *
- * @brief This structure is used to maintain the configuration information
- * associated with an NPE.
- */
-
-typedef struct
-{
-    IxOsalMutex mutex;          /**< mutex */
-    UINT32 interruptId;     /**< interrupt ID */
-    UINT32 virtualRegisterBase; /**< register virtual base address */
-    UINT32 statusRegister;      /**< status register virtual address */
-    UINT32 controlRegister;     /**< control register virtual address */
-    UINT32 inFifoRegister;      /**< inFIFO register virutal address */
-    UINT32 outFifoRegister;     /**< outFIFO register virtual address */
-    IxNpeMhConfigIsr isr;   /**< isr routine for handling interrupt */
-    BOOL oldInterruptState; /**< old interrupt state (true => enabled) */
-} IxNpeMhConfigNpeInfo;
-
-
-/*
- * #defines for function return types, etc.
- */
-
-/**< NPE register base address */
-#define IX_NPEMH_NPE_BASE (IX_OSAL_IXP400_PERIPHERAL_PHYS_BASE)
-
-#define IX_NPEMH_NPEA_OFFSET (0x6000) /**< NPE-A register base offset */
-#define IX_NPEMH_NPEB_OFFSET (0x7000) /**< NPE-B register base offset */
-#define IX_NPEMH_NPEC_OFFSET (0x8000) /**< NPE-C register base offset */
-
-#define IX_NPEMH_NPESTAT_OFFSET (0x002C) /**< NPE status register offset */
-#define IX_NPEMH_NPECTL_OFFSET  (0x0030) /**< NPE control register offset */
-#define IX_NPEMH_NPEFIFO_OFFSET (0x0038) /**< NPE FIFO register offset */
-
-/** NPE-A register base address */
-#define IX_NPEMH_NPEA_BASE (IX_NPEMH_NPE_BASE + IX_NPEMH_NPEA_OFFSET)
-/** NPE-B register base address */
-#define IX_NPEMH_NPEB_BASE (IX_NPEMH_NPE_BASE + IX_NPEMH_NPEB_OFFSET)
-/** NPE-C register base address */
-#define IX_NPEMH_NPEC_BASE (IX_NPEMH_NPE_BASE + IX_NPEMH_NPEC_OFFSET)
-
-/* NPE-A configuration */
-
-/** NPE-A interrupt */
-#define IX_NPEMH_NPEA_INT  (IX_OSAL_IXP400_NPEA_IRQ_LVL)
-/** NPE-A FIFO register */
-#define IX_NPEMH_NPEA_FIFO (IX_NPEMH_NPEA_BASE + IX_NPEMH_NPEFIFO_OFFSET)
-/** NPE-A control register */
-#define IX_NPEMH_NPEA_CTL  (IX_NPEMH_NPEA_BASE + IX_NPEMH_NPECTL_OFFSET)
-/** NPE-A status register */
-#define IX_NPEMH_NPEA_STAT (IX_NPEMH_NPEA_BASE + IX_NPEMH_NPESTAT_OFFSET)
-
-/* NPE-B configuration */
-
-/** NPE-B interrupt */
-#define IX_NPEMH_NPEB_INT  (IX_OSAL_IXP400_NPEB_IRQ_LVL)
-/** NPE-B FIFO register */
-#define IX_NPEMH_NPEB_FIFO (IX_NPEMH_NPEB_BASE + IX_NPEMH_NPEFIFO_OFFSET)
-/** NPE-B control register */
-#define IX_NPEMH_NPEB_CTL  (IX_NPEMH_NPEB_BASE + IX_NPEMH_NPECTL_OFFSET)
-/** NPE-B status register */
-#define IX_NPEMH_NPEB_STAT (IX_NPEMH_NPEB_BASE + IX_NPEMH_NPESTAT_OFFSET)
-
-/* NPE-C configuration */
-
-/** NPE-C interrupt */
-#define IX_NPEMH_NPEC_INT  (IX_OSAL_IXP400_NPEC_IRQ_LVL)
-/** NPE-C FIFO register */
-#define IX_NPEMH_NPEC_FIFO (IX_NPEMH_NPEC_BASE + IX_NPEMH_NPEFIFO_OFFSET)
-/** NPE-C control register */
-#define IX_NPEMH_NPEC_CTL  (IX_NPEMH_NPEC_BASE + IX_NPEMH_NPECTL_OFFSET)
-/** NPE-C status register */
-#define IX_NPEMH_NPEC_STAT (IX_NPEMH_NPEC_BASE + IX_NPEMH_NPESTAT_OFFSET)
-
-/* NPE control register bit definitions */
-#define IX_NPEMH_NPE_CTL_OFE   (1 << 16) /**< OutFifoEnable */
-#define IX_NPEMH_NPE_CTL_IFE   (1 << 17) /**< InFifoEnable */
-#define IX_NPEMH_NPE_CTL_OFEWE (1 << 24) /**< OutFifoEnableWriteEnable */
-#define IX_NPEMH_NPE_CTL_IFEWE (1 << 25) /**< InFifoEnableWriteEnable */
-
-/* NPE status register bit definitions */
-#define IX_NPEMH_NPE_STAT_OFNE  (1 << 16) /**< OutFifoNotEmpty */
-#define IX_NPEMH_NPE_STAT_IFNF  (1 << 17) /**< InFifoNotFull */
-#define IX_NPEMH_NPE_STAT_OFNF  (1 << 18) /**< OutFifoNotFull */
-#define IX_NPEMH_NPE_STAT_IFNE  (1 << 19) /**< InFifoNotEmpty */
-#define IX_NPEMH_NPE_STAT_MBINT (1 << 20) /**< Mailbox interrupt */
-#define IX_NPEMH_NPE_STAT_IFINT (1 << 21) /**< InFifo interrupt */
-#define IX_NPEMH_NPE_STAT_OFINT (1 << 22) /**< OutFifo interrupt */
-#define IX_NPEMH_NPE_STAT_WFINT (1 << 23) /**< WatchFifo interrupt */
-
-
-/**
- * Variable declarations.  Externs are followed by static variables.
- */
-extern IxNpeMhConfigNpeInfo ixNpeMhConfigNpeInfo[IX_NPEMH_NUM_NPES];
-
-
-/*
- * Prototypes for interface functions.
- */
-
-/**
- * @fn void ixNpeMhConfigInitialize (
-           IxNpeMhNpeInterrupts npeInterrupts)
- *
- * @brief This function initialises the Configuration module.
- *
- * @param IxNpeMhNpeInterrupts npeInterrupts (in) - whether or not to
- * service the NPE "outFIFO not empty" interrupts.
- *
- * @return No return value.
- */
-
-void ixNpeMhConfigInitialize (
-    IxNpeMhNpeInterrupts npeInterrupts);
-
-/**
- * @fn void ixNpeMhConfigUninit (void)
- *
- * @brief This function uninitialises the Configuration module.
- *
- * @return No return value.
- */
-
-void ixNpeMhConfigUninit (void);
-
-/**
- * @fn void ixNpeMhConfigIsrRegister (
-           IxNpeMhNpeId npeId,
-           IxNpeMhConfigIsr isr)
- *
- * @brief This function registers an ISR to handle NPE "outFIFO not
- * empty" interrupts.
- *
- * @param IxNpeMhNpeId npeId (in) - the ID of the NPE whose interrupt will
- * be handled.
- * @param IxNpeMhConfigIsr isr (in) - the ISR function pointer that the
- * interrupt will trigger.
- *
- * @return No return value.
- */
-
-void ixNpeMhConfigIsrRegister (
-    IxNpeMhNpeId npeId,
-    IxNpeMhConfigIsr isr);
-
-/**
- * @fn BOOL ixNpeMhConfigNpeInterruptEnable (
-           IxNpeMhNpeId npeId)
- *
- * @brief This function enables a NPE's "outFIFO not empty" interrupt.
- *
- * @param IxNpeMhNpeId npeId (in) - the ID of the NPE whose interrupt will
- * be enabled.
- *
- * @return Returns the previous state of the interrupt (true => enabled).
- */
-
-BOOL ixNpeMhConfigNpeInterruptEnable (
-    IxNpeMhNpeId npeId);
-
-/**
- * @fn BOOL ixNpeMhConfigNpeInterruptDisable (
-           IxNpeMhNpeId npeId)
- *
- * @brief This function disables a NPE's "outFIFO not empty" interrupt
- *
- * @param IxNpeMhNpeId npeId (in) - the ID of the NPE whose interrupt will
- * be disabled.
- *
- * @return Returns the previous state of the interrupt (true => enabled).
- */
-
-BOOL ixNpeMhConfigNpeInterruptDisable (
-    IxNpeMhNpeId npeId);
-
-/**
- * @fn IxNpeMhMessageId ixNpeMhConfigMessageIdGet (
-           IxNpeMhMessage message)
- *
- * @brief This function gets the ID of a message.
- *
- * @param IxNpeMhMessage message (in) - the message to get the ID of.
- *
- * @return the ID of the message
- */
-
-IxNpeMhMessageId ixNpeMhConfigMessageIdGet (
-    IxNpeMhMessage message);
-
-/**
- * @fn BOOL ixNpeMhConfigNpeIdIsValid (
-           IxNpeMhNpeId npeId)
- *
- * @brief This function checks to see if a NPE ID is valid.
- *
- * @param IxNpeMhNpeId npeId (in) - the NPE ID to validate.
- *
- * @return true if the NPE ID is valid, otherwise false.
- */
-
-BOOL ixNpeMhConfigNpeIdIsValid (
-    IxNpeMhNpeId npeId);
-
-/**
- * @fn void ixNpeMhConfigLockGet (
-           IxNpeMhNpeId npeId)
- *
- * @brief This function gets a lock for exclusive NPE interaction, and
- * disables the NPE's "outFIFO not empty" interrupt.
- *
- * @param IxNpeMhNpeId npeId (in) - The ID of the NPE for which to get the
- * lock and disable its interrupt.
- *
- * @return No return value.
- */
-
-void ixNpeMhConfigLockGet (
-    IxNpeMhNpeId npeId);
-
-/**
- * @fn void ixNpeMhConfigLockRelease (
-           IxNpeMhNpeId npeId)
- *
- * @brief This function releases a lock for exclusive NPE interaction, and
- * enables the NPE's "outFIFO not empty" interrupt.
- *
- * @param IxNpeMhNpeId npeId (in) - The ID of the NPE for which to release
- * the lock and enable its interrupt.
- *
- * @return No return value.
- */
-
-void ixNpeMhConfigLockRelease (
-    IxNpeMhNpeId npeId);
-
-/**
- * @fn BOOL ixNpeMhConfigInFifoIsEmpty (
-           IxNpeMhNpeId npeId)
- *
- * @brief This inline function checks if a NPE's inFIFO is empty.
- *
- * @param IxNpeMhNpeId npeId (in) - The ID of the NPE for which the inFIFO
- * will be checked.
- *
- * @return true if the inFIFO is empty, otherwise false.
- */
-
-IXNPEMHCONFIG_INLINE BOOL ixNpeMhConfigInFifoIsEmpty (
-    IxNpeMhNpeId npeId);
-
-/**
- * @fn BOOL ixNpeMhConfigInFifoIsFull (
-           IxNpeMhNpeId npeId)
- *
- * @brief This inline function checks if a NPE's inFIFO is full.
- *
- * @param IxNpeMhNpeId npeId (in) - The ID of the NPE for which the inFIFO
- * will be checked.
- *
- * @return true if the inFIFO is full, otherwise false.
- */
-
-IXNPEMHCONFIG_INLINE BOOL ixNpeMhConfigInFifoIsFull (
-    IxNpeMhNpeId npeId);
-
-/**
- * @fn BOOL ixNpeMhConfigOutFifoIsEmpty (
-           IxNpeMhNpeId npeId)
- *
- * @brief This inline function checks if a NPE's outFIFO is empty.
- *
- * @param IxNpeMhNpeId npeId (in) - The ID of the NPE for which the outFIFO
- * will be checked.
- *
- * @return true if the outFIFO is empty, otherwise false.
- */
-
-IXNPEMHCONFIG_INLINE BOOL ixNpeMhConfigOutFifoIsEmpty (
-    IxNpeMhNpeId npeId);
-
-/**
- * @fn BOOL ixNpeMhConfigOutFifoIsFull (
-           IxNpeMhNpeId npeId)
- *
- * @brief This inline function checks if a NPE's outFIFO is full.
- *
- * @param IxNpeMhNpeId npeId (in) - The ID of the NPE for which the outFIFO
- * will be checked.
- *
- * @return true if the outFIFO is full, otherwise false.
- */
-
-IXNPEMHCONFIG_INLINE BOOL ixNpeMhConfigOutFifoIsFull (
-    IxNpeMhNpeId npeId);
-
-/**
- * @fn IX_STATUS ixNpeMhConfigInFifoWrite (
-           IxNpeMhNpeId npeId,
-           IxNpeMhMessage message)
- *
- * @brief This function writes a message to a NPE's inFIFO.  The caller
- * must first check that the NPE's inFifo is not full. After writing the first 
- * word of the message, this function will keep polling NPE's inFIFO is not
- * full to write the second word. If inFIFO is not available after maximum 
- * retries (IX_NPE_MH_MAX_NUM_OF_RETRIES), this function will return TIMEOUT 
- * status to indicate NPE hang / halt.
- *
- * @param IxNpeMhNpeId npeId (in) - The ID of the NPE for which the inFIFO
- * will be written to.
- * @param IxNpeMhMessage message (in) - The message to write.
- *
- * @return The function returns a status indicating success, failure or timeout.
- */
-
-IX_STATUS ixNpeMhConfigInFifoWrite (
-    IxNpeMhNpeId npeId,
-    IxNpeMhMessage message);
-
-/**
- * @fn IX_STATUS ixNpeMhConfigOutFifoRead (
-           IxNpeMhNpeId npeId,
-           IxNpeMhMessage *message)
- *
- * @brief This function reads a message from a NPE's outFIFO.  The caller
- * must first check that the NPE's outFifo is not empty. After reading the first 
- * word of the message, this function will keep polling NPE's outFIFO is not
- * empty to read the second word. If outFIFO is empty after maximum 
- * retries (IX_NPE_MH_MAX_NUM_OF_RETRIES), this function will return TIMEOUT 
- * status to indicate NPE hang / halt.
- *
- * @param IxNpeMhNpeId npeId (in) - The ID of the NPE for which the outFIFO
- * will be read from.
- * @param IxNpeMhMessage message (out) - The message read.
- *
- * @return The function returns a status indicating success, failure or timeout.
- */
-
-IX_STATUS ixNpeMhConfigOutFifoRead (
-    IxNpeMhNpeId npeId,
-    IxNpeMhMessage *message);
-
-/**
- * @fn void ixNpeMhConfigShow (
-           IxNpeMhNpeId npeId)
- *
- * @brief This function will display the current state of the Configuration
- * module.
- *
- * @param IxNpeMhNpeId npeId (in) - The ID of the NPE to display state
- * information for.
- *
- * @return No return value.
- */
-
-void ixNpeMhConfigShow (
-    IxNpeMhNpeId npeId);
-
-/**
- * @fn void ixNpeMhConfigShowReset (
-           IxNpeMhNpeId npeId)
- *
- * @brief This function will reset the current state of the Configuration
- * module.
- *
- * @param IxNpeMhNpeId npeId (in) - The ID of the NPE to reset state
- * information for.
- *
- * @return No return value.
- */
-
-void ixNpeMhConfigShowReset (
-    IxNpeMhNpeId npeId);
-
-/*
- * Inline functions
- */
- 
-/*
- * This inline function checks if a NPE's inFIFO is empty.
- */
-
-IXNPEMHCONFIG_INLINE
-BOOL ixNpeMhConfigInFifoIsEmpty (
-    IxNpeMhNpeId npeId)
-{
-    UINT32 ifne;
-    volatile UINT32 *statusReg =
-        (UINT32 *)ixNpeMhConfigNpeInfo[npeId].statusRegister;
-
-    /* get the IFNE (InFifoNotEmpty) bit of the status register */
-    IX_NPEMH_REGISTER_READ_BITS (statusReg, &ifne, IX_NPEMH_NPE_STAT_IFNE);
-
-    /* if the IFNE status bit is unset then the inFIFO is empty */
-    return (ifne == 0);
-}
-
-
-/*
- * This inline function checks if a NPE's inFIFO is full.
- */
-IXNPEMHCONFIG_INLINE
-BOOL ixNpeMhConfigInFifoIsFull (
-    IxNpeMhNpeId npeId)
-{
-    UINT32 ifnf;
-    volatile UINT32 *statusReg =
-        (UINT32 *)ixNpeMhConfigNpeInfo[npeId].statusRegister;
-
-    /* get the IFNF (InFifoNotFull) bit of the status register */
-    IX_NPEMH_REGISTER_READ_BITS (statusReg, &ifnf, IX_NPEMH_NPE_STAT_IFNF);
-
-    /* if the IFNF status bit is unset then the inFIFO is full */
-    return (ifnf == 0);
-}
-
-
-/*
- * This inline function checks if a NPE's outFIFO is empty.
- */
-IXNPEMHCONFIG_INLINE
-BOOL ixNpeMhConfigOutFifoIsEmpty (
-    IxNpeMhNpeId npeId)
-{
-    UINT32 ofne;
-    volatile UINT32 *statusReg =
-        (UINT32 *)ixNpeMhConfigNpeInfo[npeId].statusRegister;
-
-    /* get the OFNE (OutFifoNotEmpty) bit of the status register */
-    IX_NPEMH_REGISTER_READ_BITS (statusReg, &ofne, IX_NPEMH_NPE_STAT_OFNE);
-
-    /* if the OFNE status bit is unset then the outFIFO is empty */
-    return (ofne == 0);
-}
-
-/*
- * This inline function checks if a NPE's outFIFO is full.
- */
-IXNPEMHCONFIG_INLINE
-BOOL ixNpeMhConfigOutFifoIsFull (
-    IxNpeMhNpeId npeId)
-{
-    UINT32 ofnf;
-    volatile UINT32 *statusReg =
-        (UINT32 *)ixNpeMhConfigNpeInfo[npeId].statusRegister;
-
-    /* get the OFNF (OutFifoNotFull) bit of the status register */
-    IX_NPEMH_REGISTER_READ_BITS (statusReg, &ofnf, IX_NPEMH_NPE_STAT_OFNF);
-
-    /* if the OFNF status bit is unset then the outFIFO is full */
-    return (ofnf == 0);
-}
-
-#endif /* IXNPEMHCONFIG_P_H */
-
-/**
- * @} defgroup IxNpeMhConfig_p
- */
diff --git a/drivers/net/npe/include/IxNpeMhMacros_p.h b/drivers/net/npe/include/IxNpeMhMacros_p.h
deleted file mode 100644
index 51ee9e289b..0000000000
--- a/drivers/net/npe/include/IxNpeMhMacros_p.h
+++ /dev/null
@@ -1,272 +0,0 @@
-/**
- * @file IxNpeMhMacros_p.h
- *
- * @author Intel Corporation
- * @date 21 Jan 2002
- *
- * @brief This file contains the macros for the IxNpeMh component.
- *
- * 
- * @par
- * IXP400 SW Release version 2.0
- * 
- * -- Copyright Notice --
- * 
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- * 
- * @par
- * SPDX-License-Identifier:	BSD-3-Clause
- * @par
- * -- End of Copyright Notice --
-*/
-
-/**
- * @defgroup IxNpeMhMacros_p IxNpeMhMacros_p
- *
- * @brief Macros for the IxNpeMh component.
- * 
- * @{
- */
-
-#ifndef IXNPEMHMACROS_P_H
-#define IXNPEMHMACROS_P_H
-
-/* if we are running as a unit test */
-#ifdef IX_UNIT_TEST
-#undef NDEBUG
-#endif /* #ifdef IX_UNIT_TEST */
-
-#include "IxOsal.h"
-
-/*
- * #defines for function return types, etc.
- */
-
-#define IX_NPEMH_SHOW_TEXT_WIDTH (40) /**< text width for stats display */
-#define IX_NPEMH_SHOW_STAT_WIDTH (10) /**< stat width for stats display */
-
-/**
- * @def IX_NPEMH_SHOW
- *
- * @brief Macro for displaying a stat preceded by a textual description.
- */
-
-#define IX_NPEMH_SHOW(TEXT, STAT) \
-    ixOsalLog (IX_OSAL_LOG_LVL_USER, IX_OSAL_LOG_DEV_STDOUT, \
-               "%-40s: %10d\n", (int) TEXT, (int) STAT, 0, 0, 0, 0)
-
-/*
- * Prototypes for interface functions.
- */
-
-/**
- * @typedef IxNpeMhTraceTypes
- *
- * @brief Enumeration defining IxNpeMh trace levels
- */
-
-typedef enum
-{
-    IX_NPEMH_TRACE_OFF     = IX_OSAL_LOG_LVL_NONE,    /**< no trace */
-    IX_NPEMH_WARNING       = IX_OSAL_LOG_LVL_WARNING, /**< warning */
-    IX_NPEMH_DEBUG         = IX_OSAL_LOG_LVL_MESSAGE, /**< debug */
-    IX_NPEMH_FN_ENTRY_EXIT = IX_OSAL_LOG_LVL_DEBUG3   /**< function entry/exit */
-} IxNpeMhTraceTypes;
-
-#ifdef IX_UNIT_TEST
-#define IX_NPEMH_TRACE_LEVEL (IX_NPEMH_FN_ENTRY_EXIT) /**< trace level */
-#else
-#define IX_NPEMH_TRACE_LEVEL (IX_NPEMH_TRACE_OFF) /**< trace level */
-#endif
-
-/**
- * @def IX_NPEMH_TRACE0
- *
- * @brief Trace macro taking 0 arguments.
- */
-
-#define IX_NPEMH_TRACE0(LEVEL, STR) \
-    IX_NPEMH_TRACE6(LEVEL, STR, 0, 0, 0, 0, 0, 0)
-
-/**
- * @def IX_NPEMH_TRACE1
- *
- * @brief Trace macro taking 1 argument.
- */
-
-#define IX_NPEMH_TRACE1(LEVEL, STR, ARG1) \
-    IX_NPEMH_TRACE6(LEVEL, STR, ARG1, 0, 0, 0, 0, 0)
-
-/**
- * @def IX_NPEMH_TRACE2
- *
- * @brief Trace macro taking 2 arguments.
- */
-
-#define IX_NPEMH_TRACE2(LEVEL, STR, ARG1, ARG2) \
-    IX_NPEMH_TRACE6(LEVEL, STR, ARG1, ARG2, 0, 0, 0, 0)
-
-/**
- * @def IX_NPEMH_TRACE3
- *
- * @brief Trace macro taking 3 arguments.
- */
-
-#define IX_NPEMH_TRACE3(LEVEL, STR, ARG1, ARG2, ARG3) \
-    IX_NPEMH_TRACE6(LEVEL, STR, ARG1, ARG2, ARG3, 0, 0, 0)
-
-/**
- * @def IX_NPEMH_TRACE4
- *
- * @brief Trace macro taking 4 arguments.
- */
-
-#define IX_NPEMH_TRACE4(LEVEL, STR, ARG1, ARG2, ARG3, ARG4) \
-    IX_NPEMH_TRACE6(LEVEL, STR, ARG1, ARG2, ARG3, ARG4, 0, 0)
-
-/**
- * @def IX_NPEMH_TRACE5
- *
- * @brief Trace macro taking 5 arguments.
- */
-
-#define IX_NPEMH_TRACE5(LEVEL, STR, ARG1, ARG2, ARG3, ARG4, ARG5) \
-    IX_NPEMH_TRACE6(LEVEL, STR, ARG1, ARG2, ARG3, ARG4, ARG5, 0)
-
-/**
- * @def IX_NPEMH_TRACE6
- *
- * @brief Trace macro taking 6 arguments.
- */
-
-#define IX_NPEMH_TRACE6(LEVEL, STR, ARG1, ARG2, ARG3, ARG4, ARG5, ARG6) \
-{ \
-    if (LEVEL <= IX_NPEMH_TRACE_LEVEL) \
-    { \
-        (void) ixOsalLog (LEVEL, IX_OSAL_LOG_DEV_STDOUT, (STR), \
-                          (int)(ARG1), (int)(ARG2), (int)(ARG3), \
-                          (int)(ARG4), (int)(ARG5), (int)(ARG6)); \
-    } \
-}
-
-/**
- * @def IX_NPEMH_ERROR_REPORT
- *
- * @brief Error reporting facility.
- */
-
-#define IX_NPEMH_ERROR_REPORT(STR) \
-{ \
-    (void) ixOsalLog (IX_OSAL_LOG_LVL_ERROR, IX_OSAL_LOG_DEV_STDERR, \
-		      (STR), 0, 0, 0, 0, 0, 0); \
-}
-
-/* if we are running on XScale, i.e. real environment */
-#if CPU==XSCALE
-
-/**
- * @def IX_NPEMH_REGISTER_READ
- *
- * @brief This macro reads a memory-mapped register.
- */
-
-#define IX_NPEMH_REGISTER_READ(registerAddress, value) \
-{ \
-    *value = IX_OSAL_READ_LONG(registerAddress); \
-}
-
-/**
- * @def IX_NPEMH_REGISTER_READ_BITS
- *
- * @brief This macro partially reads a memory-mapped register.
- */
-
-#define IX_NPEMH_REGISTER_READ_BITS(registerAddress, value, mask) \
-{ \
-    *value = (IX_OSAL_READ_LONG(registerAddress) & mask); \
-}
-
-/**
- * @def IX_NPEMH_REGISTER_WRITE
- *
- * @brief This macro writes a memory-mapped register.
- */
-
-#define IX_NPEMH_REGISTER_WRITE(registerAddress, value) \
-{ \
-    IX_OSAL_WRITE_LONG(registerAddress, value); \
-}
-
-/**
- * @def IX_NPEMH_REGISTER_WRITE_BITS
- *
- * @brief This macro partially writes a memory-mapped register.
- */
-
-#define IX_NPEMH_REGISTER_WRITE_BITS(registerAddress, value, mask) \
-{ \
-    UINT32 orig = IX_OSAL_READ_LONG(registerAddress); \
-    orig &= (~mask); \
-    orig |= (value & mask); \
-    IX_OSAL_WRITE_LONG(registerAddress, orig); \
-}
-
-
-/* if we are running as a unit test */
-#else /* #if CPU==XSCALE */
-
-#include "IxNpeMhTestRegister.h"
-
-/**
- * @def IX_NPEMH_REGISTER_READ
- *
- * @brief This macro reads a memory-mapped register.
- */
-
-#define IX_NPEMH_REGISTER_READ(registerAddress, value) \
-{ \
-    ixNpeMhTestRegisterRead (registerAddress, value); \
-}
-
-/**
- * @def IX_NPEMH_REGISTER_READ_BITS
- *
- * @brief This macro partially reads a memory-mapped register.
- */
-
-#define IX_NPEMH_REGISTER_READ_BITS(registerAddress, value, mask) \
-{ \
-    ixNpeMhTestRegisterReadBits (registerAddress, value, mask); \
-}
-
-/**
- * @def IX_NPEMH_REGISTER_WRITE
- *
- * @brief This macro writes a memory-mapped register.
- */
-
-#define IX_NPEMH_REGISTER_WRITE(registerAddress, value) \
-{ \
-    ixNpeMhTestRegisterWrite (registerAddress, value); \
-}
-
-/**
- * @def IX_NPEMH_REGISTER_WRITE_BITS
- *
- * @brief This macro partially writes a memory-mapped register.
- */
-
-#define IX_NPEMH_REGISTER_WRITE_BITS(registerAddress, value, mask) \
-{ \
-    ixNpeMhTestRegisterWriteBits (registerAddress, value, mask); \
-}
-
-#endif /* #if CPU==XSCALE */
-
-#endif /* IXNPEMHMACROS_P_H */
-
-/**
- * @} defgroup IxNpeMhMacros_p
- */
diff --git a/drivers/net/npe/include/IxNpeMhReceive_p.h b/drivers/net/npe/include/IxNpeMhReceive_p.h
deleted file mode 100644
index 7b2afa0a3c..0000000000
--- a/drivers/net/npe/include/IxNpeMhReceive_p.h
+++ /dev/null
@@ -1,115 +0,0 @@
-/**
- * @file IxNpeMhReceive_p.h
- *
- * @author Intel Corporation
- * @date 18 Jan 2002
- *
- * @brief This file contains the private API for the Receive module.
- *
- * 
- * @par
- * IXP400 SW Release version 2.0
- * 
- * -- Copyright Notice --
- * 
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- * 
- * @par
- * SPDX-License-Identifier:	BSD-3-Clause
- * @par
- * -- End of Copyright Notice --
-*/
-
-/**
- * @defgroup IxNpeMhReceive_p IxNpeMhReceive_p
- *
- * @brief The private API for the Receive module.
- * 
- * @{
- */
-
-#ifndef IXNPEMHRECEIVE_P_H
-#define IXNPEMHRECEIVE_P_H
-
-#include "IxNpeMh.h"
-#include "IxOsalTypes.h"
-
-/*
- * #defines for function return types, etc.
- */
-
-/*
- * Prototypes for interface functions.
- */
-
-/**
- * @fn void ixNpeMhReceiveInitialize (void)
- *
- * @brief This function registers an internal ISR to handle the NPEs'
- * "outFIFO not empty" interrupts and receive messages from the NPEs when
- * they become available.
- *
- * @return No return value.
- */
-
-void ixNpeMhReceiveInitialize (void);
-
-/**
- * @fn IX_STATUS ixNpeMhReceiveMessagesReceive (
-           IxNpeMhNpeId npeId)
- *
- * @brief This function reads messages from a particular NPE's outFIFO
- * until the outFIFO is empty, and for each message looks first for an
- * unsolicited callback, then a solicited callback, to pass the message
- * back to the client.  If no callback can be found the message is
- * discarded and an error reported. This function will return TIMEOUT 
- * status if NPE hang / halt.
- *
- * @param IxNpeMhNpeId npeId (in) - The ID of the NPE to receive
- * messages from.
- *
- * @return The function returns a status indicating success, failure or timeout.
- */
-
-IX_STATUS ixNpeMhReceiveMessagesReceive (
-    IxNpeMhNpeId npeId);
-
-/**
- * @fn void ixNpeMhReceiveShow (
-           IxNpeMhNpeId npeId)
- *
- * @brief This function will display the current state of the Receive
- * module.
- *
- * @param IxNpeMhNpeId npeId (in) - The ID of the NPE to display state
- * information for.
- *
- * @return No return status.
- */
-
-void ixNpeMhReceiveShow (
-    IxNpeMhNpeId npeId);
-
-/**
- * @fn void ixNpeMhReceiveShowReset (
-           IxNpeMhNpeId npeId)
- *
- * @brief This function will reset the current state of the Receive
- * module.
- *
- * @param IxNpeMhNpeId npeId (in) - The ID of the NPE to reset state
- * information for.
- *
- * @return No return status.
- */
-
-void ixNpeMhReceiveShowReset (
-    IxNpeMhNpeId npeId);
-
-#endif /* IXNPEMHRECEIVE_P_H */
-
-/**
- * @} defgroup IxNpeMhReceive_p
- */
diff --git a/drivers/net/npe/include/IxNpeMhSend_p.h b/drivers/net/npe/include/IxNpeMhSend_p.h
deleted file mode 100644
index 0f060cc604..0000000000
--- a/drivers/net/npe/include/IxNpeMhSend_p.h
+++ /dev/null
@@ -1,139 +0,0 @@
-/**
- * @file IxNpeMhSend_p.h
- *
- * @author Intel Corporation
- * @date 18 Jan 2002
- *
- * @brief This file contains the private API for the Send module.
- *
- * 
- * @par
- * IXP400 SW Release version 2.0
- * 
- * -- Copyright Notice --
- * 
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- * 
- * @par
- * SPDX-License-Identifier:	BSD-3-Clause
- * @par
- * -- End of Copyright Notice --
-*/
-
-/**
- * @defgroup IxNpeMhSend_p IxNpeMhSend_p
- *
- * @brief The private API for the Send module.
- * 
- * @{
- */
-
-#ifndef IXNPEMHSEND_P_H
-#define IXNPEMHSEND_P_H
-
-#include "IxNpeMh.h"
-#include "IxOsalTypes.h"
-
-/*
- * #defines for function return types, etc.
- */
-
-/*
- * Prototypes for interface functions.
- */
-
-/**
- * @fn IX_STATUS ixNpeMhSendMessageSend (
-           IxNpeMhNpeId npeId,
-           IxNpeMhMessage message,
-           UINT32 maxSendRetries)
- *
- * @brief This function writes a message to the specified NPE's inFIFO,
- * and must be used when the message being sent does not solicit a response
- * from the NPE. This function will return TIMEOUT status if NPE hang / halt.
- *
- * @param IxNpeMhNpeId npeId (in) - The ID of the NPE to send the message
- * to.
- * @param IxNpeMhMessage message (in) - The message to send.
- * @param UINT32 maxSendRetries (in) - Max num. of retries to perform
- * if the NPE's inFIFO is full.
- *
- * @return The function returns a status indicating success, failure or timeout.
- */
-
-IX_STATUS ixNpeMhSendMessageSend (
-    IxNpeMhNpeId npeId,
-    IxNpeMhMessage message,
-    UINT32 maxSendRetries);
-
-/**
- * @fn IX_STATUS ixNpeMhSendMessageWithResponseSend (
-           IxNpeMhNpeId npeId,
-           IxNpeMhMessage message,
-           IxNpeMhMessageId solicitedMessageId,
-           IxNpeMhCallback solicitedCallback,
-           UINT32 maxSendRetries)
- *
- * @brief This function writes a message to the specified NPE's inFIFO,
- * and must be used when the message being sent solicits a response from
- * the NPE.  The ID of the solicited response must be specified so that it
- * can be recognised, and a callback provided to pass the response back to
- * the client. This function will return TIMEOUT status if NPE hang / halt.
- *
- * @param IxNpeMhNpeId npeId (in) - The ID of the NPE to send the message
- * to.
- * @param IxNpeMhMessage message (in) - The message to send.
- * @param IxNpeMhMessageId solicitedMessageId (in) - The ID of the
- * solicited response.
- * @param IxNpeMhCallback solicitedCallback (in) - The callback to pass the
- * solicited response back to the client.
- * @param UINT32 maxSendRetries (in) - Max num. of retries to perform
- * if the NPE's inFIFO is full.
- *
- * @return The function returns a status indicating success, failure or timeout.
- */
-
-IX_STATUS ixNpeMhSendMessageWithResponseSend (
-    IxNpeMhNpeId npeId,
-    IxNpeMhMessage message,
-    IxNpeMhMessageId solicitedMessageId,
-    IxNpeMhCallback solicitedCallback,
-    UINT32 maxSendRetries);
-
-/**
- * @fn void ixNpeMhSendShow (
-           IxNpeMhNpeId npeId)
- *
- * @brief This function will display the current state of the Send module.
- *
- * @param IxNpeMhNpeId npeId (in) - The ID of the NPE to display state
- * information for.
- *
- * @return No return value.
- */
-
-void ixNpeMhSendShow (
-    IxNpeMhNpeId npeId);
-
-/**
- * @fn void ixNpeMhSendShowReset (
-           IxNpeMhNpeId npeId)
- *
- * @brief This function will reset the current state of the Send module.
- *
- * @param IxNpeMhNpeId npeId (in) - The ID of the NPE to reset state
- * information for.
- *
- * @return No return value.
- */
-
-void ixNpeMhSendShowReset (
-    IxNpeMhNpeId npeId);
-
-#endif /* IXNPEMHSEND_P_H */
-
-/**
- * @} defgroup IxNpeMhSend_p
- */
diff --git a/drivers/net/npe/include/IxNpeMhSolicitedCbMgr_p.h b/drivers/net/npe/include/IxNpeMhSolicitedCbMgr_p.h
deleted file mode 100644
index b094fd99cb..0000000000
--- a/drivers/net/npe/include/IxNpeMhSolicitedCbMgr_p.h
+++ /dev/null
@@ -1,147 +0,0 @@
-/**
- * @file IxNpeMhSolicitedCbMgr_p.h
- *
- * @author Intel Corporation
- * @date 18 Jan 2002
- *
- * @brief This file contains the private API for the Solicited Callback
- * Manager module.
- *
- * 
- * @par
- * IXP400 SW Release version 2.0
- * 
- * -- Copyright Notice --
- * 
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- * 
- * @par
- * SPDX-License-Identifier:	BSD-3-Clause
- * @par
- * -- End of Copyright Notice --
-*/
-
-/**
- * @defgroup IxNpeMhSolicitedCbMgr_p IxNpeMhSolicitedCbMgr_p
- *
- * @brief The private API for the Solicited Callback Manager module.
- * 
- * @{
- */
-
-#ifndef IXNPEMHSOLICITEDCBMGR_P_H
-#define IXNPEMHSOLICITEDCBMGR_P_H
-
-#include "IxNpeMh.h"
-#include "IxOsalTypes.h"
-
-/*
- * #defines for function return types, etc.
- */
-
-/** Maximum number of solicited callbacks that can be stored in the list */
-#define IX_NPEMH_MAX_CALLBACKS (16)
-
-/*
- * Prototypes for interface functions.
- */
-
-/**
- * @fn void ixNpeMhSolicitedCbMgrInitialize (void)
- *
- * @brief This function initializes the Solicited Callback Manager module,
- * setting up a callback data structure for each NPE.
- *
- * @return No return value.
- */
-
-void ixNpeMhSolicitedCbMgrInitialize (void);
-
-/**
- * @fn IX_STATUS ixNpeMhSolicitedCbMgrCallbackSave (
-           IxNpeMhNpeId npeId,
-           IxNpeMhMessageId solicitedMessageId,
-           IxNpeMhCallback solicitedCallback)
- *
- * @brief This function saves a callback in the specified NPE's callback
- * list.  If the callback list is full the function will fail.
- *
- * @param IxNpeMhNpeId npeId (in) - The ID of the NPE in whose callback
- * list the callback will be saved.
- * @param IxNpeMhMessageId solicitedMessageId (in) - The ID of the message
- * that this callback is for.
- * @param IxNpeMhCallback solicitedCallback (in) - The callback function
- * pointer to save.
- *
- * @return The function returns a status indicating success or failure.
- */
-
-IX_STATUS ixNpeMhSolicitedCbMgrCallbackSave (
-    IxNpeMhNpeId npeId,
-    IxNpeMhMessageId solicitedMessageId,
-    IxNpeMhCallback solicitedCallback);
-
-/**
- * @fn void ixNpeMhSolicitedCbMgrCallbackRetrieve (
-           IxNpeMhNpeId npeId,
-           IxNpeMhMessageId solicitedMessageId,
-           IxNpeMhCallback *solicitedCallback)
- *
- * @brief This function retrieves the first ID-matching callback from the
- * specified NPE's callback list.  If no matching callback can be found the
- * function will fail.
- *
- * @param IxNpeMhNpeId npeId (in) - The ID of the NPE from whose callback
- * list the callback will be retrieved.
- * @param IxNpeMhMessageId solicitedMessageId (in) - The ID of the message
- * that the callback is for.
- * @param IxNpeMhCallback solicitedCallback (out) - The callback function
- * pointer retrieved.
- *
- * @return No return value.
- */
-
-void ixNpeMhSolicitedCbMgrCallbackRetrieve (
-    IxNpeMhNpeId npeId,
-    IxNpeMhMessageId solicitedMessageId,
-    IxNpeMhCallback *solicitedCallback);
-
-/**
- * @fn void ixNpeMhSolicitedCbMgrShow (
-           IxNpeMhNpeId npeId)
- *
- * @brief This function will display the current state of the Solicited
- * Callback Manager module.
- *
- * @param IxNpeMhNpeId npeId (in) - The ID of the NPE to display state
- * information for.
- *
- * @return No return value.
- */
-
-void ixNpeMhSolicitedCbMgrShow (
-    IxNpeMhNpeId npeId);
-
-/**
- * @fn void ixNpeMhSolicitedCbMgrShowReset (
-           IxNpeMhNpeId npeId)
- *
- * @brief This function will reset the current state of the Solicited
- * Callback Manager module.
- *
- * @param IxNpeMhNpeId npeId (in) - The ID of the NPE to reset state
- * information for.
- *
- * @return No return value.
- */
-
-void ixNpeMhSolicitedCbMgrShowReset (
-    IxNpeMhNpeId npeId);
-
-#endif /* IXNPEMHSOLICITEDCBMGR_P_H */
-
-/**
- * @} defgroup IxNpeMhSolicitedCbMgr_p
- */
diff --git a/drivers/net/npe/include/IxNpeMhUnsolicitedCbMgr_p.h b/drivers/net/npe/include/IxNpeMhUnsolicitedCbMgr_p.h
deleted file mode 100644
index faf6638380..0000000000
--- a/drivers/net/npe/include/IxNpeMhUnsolicitedCbMgr_p.h
+++ /dev/null
@@ -1,145 +0,0 @@
-/**
- * @file IxNpeMhUnsolicitedCbMgr_p.h
- *
- * @author Intel Corporation
- * @date 18 Jan 2002
- *
- * @brief This file contains the private API for the Unsolicited Callback
- * Manager module.
- *
- * 
- * @par
- * IXP400 SW Release version 2.0
- * 
- * -- Copyright Notice --
- * 
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- * 
- * @par
- * SPDX-License-Identifier:	BSD-3-Clause
- * @par
- * -- End of Copyright Notice --
- */
-
-/**
- * @defgroup IxNpeMhUnsolicitedCbMgr_p IxNpeMhUnsolicitedCbMgr_p
- *
- * @brief The private API for the Unsolicited Callback Manager module.
- * 
- * @{
- */
-
-#ifndef IXNPEMHUNSOLICITEDCBMGR_P_H
-#define IXNPEMHUNSOLICITEDCBMGR_P_H
-
-#include "IxNpeMh.h"
-#include "IxOsalTypes.h"
-
-/*
- * #defines for function return types, etc.
- */
-
-/*
- * Prototypes for interface functions.
- */
-
-/**
- * @fn void ixNpeMhUnsolicitedCbMgrInitialize (void)
- *
- * @brief This function initializes the Unsolicited Callback Manager
- * module, setting up a callback data structure for each NPE.
- *
- * @return No return value.
- */
-
-void ixNpeMhUnsolicitedCbMgrInitialize (void);
-
-/**
- * @fn void ixNpeMhUnsolicitedCbMgrCallbackSave (
-           IxNpeMhNpeId npeId,
-           IxNpeMhMessageId unsolicitedMessageId,
-           IxNpeMhCallback unsolicitedCallback)
- *
- * @brief This function saves a callback in the specified NPE's callback
- * table.  If a callback already exists for the specified ID then it will
- * be overwritten.
- *
- * @param IxNpeMhNpeId npeId (in) - The ID of the NPE in whose callback
- * table the callback will be saved.
- * @param IxNpeMhMessageId unsolicitedMessageId (in) - The ID of the
- * messages that this callback is for.
- * @param IxNpeMhCallback unsolicitedCallback (in) - The callback function
- * pointer to save.
- *
- * @return No return value.
- */
-
-void ixNpeMhUnsolicitedCbMgrCallbackSave (
-    IxNpeMhNpeId npeId,
-    IxNpeMhMessageId unsolicitedMessageId,
-    IxNpeMhCallback unsolicitedCallback);
-
-/**
- * @fn void ixNpeMhUnsolicitedCbMgrCallbackRetrieve (
-           IxNpeMhNpeId npeId,
-           IxNpeMhMessageId unsolicitedMessageId,
-           IxNpeMhCallback *unsolicitedCallback)
- *
- * @brief This function retrieves the callback for the specified ID from
- * the specified NPE's callback table.  If no callback is registered for
- * the specified ID and NPE then a callback value of NULL will be returned.
- *
- * @param IxNpeMhNpeId npeId (in) - The ID of the NPE from whose callback
- * table the callback will be retrieved.
- * @param IxNpeMhMessageId unsolicitedMessageId (in) - The ID of the
- * messages that the callback is for.
- * @param IxNpeMhCallback unsolicitedCallback (out) - The callback function
- * pointer retrieved.
- *
- * @return No return value.
- */
-
-void ixNpeMhUnsolicitedCbMgrCallbackRetrieve (
-    IxNpeMhNpeId npeId,
-    IxNpeMhMessageId unsolicitedMessageId,
-    IxNpeMhCallback *unsolicitedCallback);
-
-/**
- * @fn void ixNpeMhUnsolicitedCbMgrShow (
-           IxNpeMhNpeId npeId)
- *
- * @brief This function will display the current state of the Unsolicited
- * Callback Manager module.
- *
- * @param IxNpeMhNpeId npeId (in) - The ID of the NPE to display state
- * information for.
- *
- * @return No return value.
- */
-
-void ixNpeMhUnsolicitedCbMgrShow (
-    IxNpeMhNpeId npeId);
-
-/**
- * @fn void ixNpeMhUnsolicitedCbMgrShowReset (
-           IxNpeMhNpeId npeId)
- *
- * @brief This function will reset the current state of the Unsolicited
- * Callback Manager module.
- *
- * @param IxNpeMhNpeId npeId (in) - The ID of the NPE to reset state
- * information for.
- *
- * @return No return value.
- */
-
-void ixNpeMhUnsolicitedCbMgrShowReset (
-    IxNpeMhNpeId npeId);
-
-#endif /* IXNPEMHUNSOLICITEDCBMGR_P_H */
-
-/**
- * @} defgroup IxNpeMhUnsolicitedCbMgr_p
- */
diff --git a/drivers/net/npe/include/IxNpeMicrocode.h b/drivers/net/npe/include/IxNpeMicrocode.h
deleted file mode 100644
index 01dcd7ad4f..0000000000
--- a/drivers/net/npe/include/IxNpeMicrocode.h
+++ /dev/null
@@ -1,272 +0,0 @@
-/**
- * @date   April 18, 2005
- *
- * @brief  IXP400 NPE Microcode Image file
- *
- * This file was generated by the IxNpeDlImageGen tool.
- * It contains a NPE microcode image suitable for use
- * with the NPE Downloader (IxNpeDl) component in the
- * IXP400 Access Driver software library.
- *
- * @par
- * IXP400 SW Release version 2.0
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * SPDX-License-Identifier:	BSD-3-Clause
- * @par
- * -- End of Copyright Notice --
-*/
-
-/**
- * @defgroup IxNpeMicrocode IXP400 NPE Microcode Image Library
- *
- * @brief Library containing a set of NPE firmware images, for use
- * with NPE Downloader s/w component
- *
- * @{
- */
-
-/**
- * @def IX_NPE_IMAGE_INCLUDE
- *
- * @brief Wrap the following Image identifiers with "#if IX_NPE_IMAGE_INCLUDE ... #endif" to include the image in the library
- */
-#define IX_NPE_IMAGE_INCLUDE 1
-
-/**
- * @def IX_NPE_IMAGE_OMIT
- *
- * @brief Wrap the following Image identifiers with "#if IX_NPE_IMAGE_OMIT ... #endif" to OMIT the image from the library
- */
-#define IX_NPE_IMAGE_OMIT    0
-
-
-#if IX_NPE_IMAGE_INCLUDE
-/**
- * @def IX_NPEDL_NPEIMAGE_NPEA_HSS0
- *
- * @brief NPE Image Id for NPE-A with HSS-0 Only feature.  It supports 32 channelized and 4 packetized.
- */
-#define IX_NPEDL_NPEIMAGE_NPEA_HSS0 0x00010000
-#endif
-
-#if IX_NPE_IMAGE_INCLUDE
-/**
- * @def IX_NPEDL_NPEIMAGE_NPEA_HSS0_ATM_SPHY_1_PORT
- *
- * @brief NPE Image Id for NPE-A with HSS-0 and ATM feature. For HSS, it supports 16/32 channelized and 4/0 packetized. For ATM, it supports AAL5, AAL0 and OAM for UTOPIA SPHY, 1 logical port, 32 VCs. It also has Fast Path support.
- */
-#define IX_NPEDL_NPEIMAGE_NPEA_HSS0_ATM_SPHY_1_PORT 0x00020000
-#endif
-
-#if IX_NPE_IMAGE_INCLUDE
-/**
- * @def IX_NPEDL_NPEIMAGE_NPEA_HSS0_ATM_MPHY_1_PORT
- *
- * @brief NPE Image Id for NPE-A with HSS-0 and ATM feature. For HSS, it supports 16/32 channelized and 4/0 packetized. For ATM, it supports AAL5, AAL0 and OAM for UTOPIA MPHY, 1 logical port, 32 VCs. It also has Fast Path support.
- */
-#define IX_NPEDL_NPEIMAGE_NPEA_HSS0_ATM_MPHY_1_PORT 0x00030000
-#endif
-
-#if IX_NPE_IMAGE_INCLUDE
-/**
- * @def IX_NPEDL_NPEIMAGE_NPEA_ATM_MPHY_12_PORT
- *
- * @brief NPE Image Id for NPE-A with ATM-Only feature. It supports AAL5, AAL0 and OAM for UTOPIA MPHY, 12 logical ports, 32 VCs. It also has Fast Path support.
- */
-#define IX_NPEDL_NPEIMAGE_NPEA_ATM_MPHY_12_PORT 0x00040000
-#endif
-
-#if IX_NPE_IMAGE_INCLUDE
-/**
- * @def IX_NPEDL_NPEIMAGE_NPEA_DMA
- *
- * @brief NPE Image Id for NPE-A with DMA-Only feature.
- */
-#define IX_NPEDL_NPEIMAGE_NPEA_DMA 0x00150100
-#endif
-
-#if IX_NPE_IMAGE_INCLUDE
-/**
- * @def IX_NPEDL_NPEIMAGE_NPEA_HSS_2_PORT
- *
- * @brief NPE Image Id for NPE-A with HSS-0 and HSS-1 feature. Each HSS port supports 32 channelized and 4 packetized.
- */
-#define IX_NPEDL_NPEIMAGE_NPEA_HSS_2_PORT 0x00090000
-#endif
-
-#if IX_NPE_IMAGE_INCLUDE
-/**
- * @def IX_NPEDL_NPEIMAGE_NPEA_ETH
- *
- * @brief NPE Image Id for NPE-A with Basic Ethernet Rx/Tx which includes: MAC_FILTERING, MAC_LEARNING, SPANNING_TREE, FIREWALL
- */
-#define IX_NPEDL_NPEIMAGE_NPEA_ETH 0x10800200
-#endif
-
-#if IX_NPE_IMAGE_INCLUDE
-/**
- * @def IX_NPEDL_NPEIMAGE_NPEA_ETH_LEARN_FILTER_SPAN_FIREWALL
- *
- * @brief NPE Image Id for NPE-A with Basic Ethernet Rx/Tx which includes: MAC_FILTERING, MAC_LEARNING, SPANNING_TREE, FIREWALL
- */
-#define IX_NPEDL_NPEIMAGE_NPEA_ETH_LEARN_FILTER_SPAN_FIREWALL 0x10800200
-#endif
-
-#if IX_NPE_IMAGE_INCLUDE
-/**
- * @def IX_NPEDL_NPEIMAGE_NPEA_ETH_LEARN_FILTER_SPAN_FIREWALL_VLAN_QOS
- *
- * @brief NPE Image Id for NPE-A with Ethernet Rx/Tx which includes: MAC_FILTERING, MAC_LEARNING, SPANNING_TREE, FIREWALL, VLAN_QOS
- */
-#define IX_NPEDL_NPEIMAGE_NPEA_ETH_LEARN_FILTER_SPAN_FIREWALL_VLAN_QOS 0x10810200
-#endif
-
-#if IX_NPE_IMAGE_INCLUDE
-/**
- * @def IX_NPEDL_NPEIMAGE_NPEA_ETH_SPAN_FIREWALL_VLAN_QOS_HDR_CONV
- *
- * @brief NPE Image Id for NPE-A with Ethernet Rx/Tx which includes: SPANNING_TREE, FIREWALL, VLAN_QOS, HEADER_CONVERSION
- */
-#define IX_NPEDL_NPEIMAGE_NPEA_ETH_SPAN_FIREWALL_VLAN_QOS_HDR_CONV 0x10820200
-#endif
-
-#if IX_NPE_IMAGE_INCLUDE
-/**
- * @def IX_NPEDL_NPEIMAGE_NPEB_ETH
- *
- * @brief NPE Image Id for NPE-B with Basic Ethernet Rx/Tx which includes: MAC_FILTERING, MAC_LEARNING, SPANNING_TREE, FIREWALL
- */
-#define IX_NPEDL_NPEIMAGE_NPEB_ETH 0x01000200
-#endif
-
-#if IX_NPE_IMAGE_INCLUDE
-/**
- * @def IX_NPEDL_NPEIMAGE_NPEB_ETH_LEARN_FILTER_SPAN_FIREWALL
- *
- * @brief NPE Image Id for NPE-B with Basic Ethernet Rx/Tx which includes: MAC_FILTERING, MAC_LEARNING, SPANNING_TREE, FIREWALL
- */
-#define IX_NPEDL_NPEIMAGE_NPEB_ETH_LEARN_FILTER_SPAN_FIREWALL 0x01000200
-#endif
-
-#if IX_NPE_IMAGE_INCLUDE
-/**
- * @def IX_NPEDL_NPEIMAGE_NPEB_ETH_LEARN_FILTER_SPAN_FIREWALL_VLAN_QOS
- *
- * @brief NPE Image Id for NPE-B with Ethernet Rx/Tx which includes: MAC_FILTERING, MAC_LEARNING, SPANNING_TREE, FIREWALL, VLAN_QOS
- */
-#define IX_NPEDL_NPEIMAGE_NPEB_ETH_LEARN_FILTER_SPAN_FIREWALL_VLAN_QOS 0x01010200
-#endif
-
-#if IX_NPE_IMAGE_INCLUDE
-/**
- * @def IX_NPEDL_NPEIMAGE_NPEB_ETH_SPAN_FIREWALL_VLAN_QOS_HDR_CONV
- *
- * @brief NPE Image Id for NPE-B with Ethernet Rx/Tx which includes: SPANNING_TREE, FIREWALL, VLAN_QOS, HEADER_CONVERSION
- */
-#define IX_NPEDL_NPEIMAGE_NPEB_ETH_SPAN_FIREWALL_VLAN_QOS_HDR_CONV 0x01020200
-#endif
-
-#if IX_NPE_IMAGE_INCLUDE
-/**
- * @def IX_NPEDL_NPEIMAGE_NPEB_DMA
- *
- * @brief NPE Image Id for NPE-B with DMA-Only feature.
- */
-#define IX_NPEDL_NPEIMAGE_NPEB_DMA 0x01020100
-#endif
-
-#if IX_NPE_IMAGE_INCLUDE
-/**
- * @def IX_NPEDL_NPEIMAGE_NPEC_ETH
- *
- * @brief NPE Image Id for NPE-C with Basic Ethernet Rx/Tx which includes: MAC_FILTERING, MAC_LEARNING, SPANNING_TREE, FIREWALL
- */
-#define IX_NPEDL_NPEIMAGE_NPEC_ETH 0x02000200
-#endif
-
-#if IX_NPE_IMAGE_INCLUDE
-/**
- * @def IX_NPEDL_NPEIMAGE_NPEC_ETH_LEARN_FILTER_SPAN_FIREWALL
- *
- * @brief NPE Image Id for NPE-C with Basic Ethernet Rx/Tx which includes: MAC_FILTERING, MAC_LEARNING, SPANNING_TREE, FIREWALL
- */
-#define IX_NPEDL_NPEIMAGE_NPEC_ETH_LEARN_FILTER_SPAN_FIREWALL 0x02000200
-#endif
-
-#if IX_NPE_IMAGE_INCLUDE
-/**
- * @def IX_NPEDL_NPEIMAGE_NPEC_ETH_LEARN_FILTER_SPAN_FIREWALL_VLAN_QOS
- *
- * @brief NPE Image Id for NPE-C with Ethernet Rx/Tx which includes: MAC_FILTERING, MAC_LEARNING, SPANNING_TREE, FIREWALL, VLAN_QOS
- */
-#define IX_NPEDL_NPEIMAGE_NPEC_ETH_LEARN_FILTER_SPAN_FIREWALL_VLAN_QOS 0x02010200
-#endif
-
-#if IX_NPE_IMAGE_INCLUDE
-/**
- * @def IX_NPEDL_NPEIMAGE_NPEC_ETH_SPAN_FIREWALL_VLAN_QOS_HDR_CONV
- *
- * @brief NPE Image Id for NPE-C with Ethernet Rx/Tx which includes: SPANNING_TREE, FIREWALL, VLAN_QOS, HEADER_CONVERSION
- */
-#define IX_NPEDL_NPEIMAGE_NPEC_ETH_SPAN_FIREWALL_VLAN_QOS_HDR_CONV 0x02020200
-#endif
-
-#if IX_NPE_IMAGE_INCLUDE
-/**
- * @def IX_NPEDL_NPEIMAGE_NPEC_DMA
- *
- * @brief NPE Image Id for NPE-C with DMA-Only feature.
- */
-#define IX_NPEDL_NPEIMAGE_NPEC_DMA 0x02080100
-#endif
-
-/* Number of NPE firmware images in this library */
-#define IX_NPE_MICROCODE_AVAILABLE_VERSIONS_COUNT 17
-
-/* Location of Microcode Images */
-#ifdef IX_NPE_MICROCODE_FIRMWARE_INCLUDED
-#ifdef IX_NPEDL_READ_MICROCODE_FROM_FILE
-
-extern UINT32* ixNpeMicrocode_binaryArray;
-
-#else
-
-extern unsigned IxNpeMicrocode_array[];
-
-#endif
-#endif
-
-/*
- * sr: undef all but the bare minimum to reduce flash usage for U-Boot
- */
-#undef IX_NPEDL_NPEIMAGE_NPEA_HSS0
-#undef IX_NPEDL_NPEIMAGE_NPEA_HSS0_ATM_SPHY_1_PORT
-#undef IX_NPEDL_NPEIMAGE_NPEA_HSS0_ATM_MPHY_1_PORT
-#undef IX_NPEDL_NPEIMAGE_NPEA_ATM_MPHY_12_PORT
-#undef IX_NPEDL_NPEIMAGE_NPEA_DMA
-#undef IX_NPEDL_NPEIMAGE_NPEA_HSS_2_PORT
-#undef IX_NPEDL_NPEIMAGE_NPEA_ETH
-#undef IX_NPEDL_NPEIMAGE_NPEA_ETH_LEARN_FILTER_SPAN_FIREWALL
-#undef IX_NPEDL_NPEIMAGE_NPEA_ETH_LEARN_FILTER_SPAN_FIREWALL_VLAN_QOS
-#undef IX_NPEDL_NPEIMAGE_NPEA_ETH_SPAN_FIREWALL_VLAN_QOS_HDR_CONV
-#undef IX_NPEDL_NPEIMAGE_NPEB_ETH
-#undef IX_NPEDL_NPEIMAGE_NPEB_ETH_LEARN_FILTER_SPAN_FIREWALL
-/* #undef IX_NPEDL_NPEIMAGE_NPEB_ETH_LEARN_FILTER_SPAN_FIREWALL_VLAN_QOS */
-#undef IX_NPEDL_NPEIMAGE_NPEB_ETH_SPAN_FIREWALL_VLAN_QOS_HDR_CONV
-#undef IX_NPEDL_NPEIMAGE_NPEB_DMA
-#undef IX_NPEDL_NPEIMAGE_NPEC_ETH
-#undef IX_NPEDL_NPEIMAGE_NPEC_ETH_LEARN_FILTER_SPAN_FIREWALL
-/* #undef IX_NPEDL_NPEIMAGE_NPEC_ETH_LEARN_FILTER_SPAN_FIREWALL_VLAN_QOS */
-#undef IX_NPEDL_NPEIMAGE_NPEC_ETH_SPAN_FIREWALL_VLAN_QOS_HDR_CONV
-#undef IX_NPEDL_NPEIMAGE_NPEC_DMA
-
-/**
- * @} defgroup IxNpeMicrocode
- */
diff --git a/drivers/net/npe/include/IxOsBufLib.h b/drivers/net/npe/include/IxOsBufLib.h
deleted file mode 100644
index 68341dca2f..0000000000
--- a/drivers/net/npe/include/IxOsBufLib.h
+++ /dev/null
@@ -1,31 +0,0 @@
-/**
- * @file IxOsBufLib.h  (Replaced by OSAL)
- *
- * @date 9 Oct 2002
- *
- * @brief This file contains the mbuf pool initialisation entry point
- *
- * 
- * @par
- * IXP400 SW Release version 2.0
- * 
- * -- Copyright Notice --
- * 
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- * 
- * @par
- * SPDX-License-Identifier:	BSD-3-Clause
- * @par
- * -- End of Copyright Notice --
- *
- */
-
-#ifndef IXOSBUFLIB_H
-#define IXOSBUFLIB_H
-
-#include "IxOsalBackward.h"
-
-#endif /* IXOSBUFLIB_H */
-
diff --git a/drivers/net/npe/include/IxOsBuffMgt.h b/drivers/net/npe/include/IxOsBuffMgt.h
deleted file mode 100644
index 8b2ee964a2..0000000000
--- a/drivers/net/npe/include/IxOsBuffMgt.h
+++ /dev/null
@@ -1,28 +0,0 @@
-/**
- * @file (Replaced by OSAL)
- *
- * @brief This file includes the OS dependant MBUF header files.
- *
- * 
- * @par
- * IXP400 SW Release version 2.0
- * 
- * -- Copyright Notice --
- * 
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- * 
- * @par
- * SPDX-License-Identifier:	BSD-3-Clause
- * @par
- * -- End of Copyright Notice --
- */
-
-
-#ifndef IxOsBuffMgt_inc
-#define IxOsBuffMgt_inc
-
-#include "IxOsalBackward.h"
-
-#endif /* ndef IxOsBuffMgt_inc */
diff --git a/drivers/net/npe/include/IxOsBuffPoolMgt.h b/drivers/net/npe/include/IxOsBuffPoolMgt.h
deleted file mode 100644
index 1e39be2782..0000000000
--- a/drivers/net/npe/include/IxOsBuffPoolMgt.h
+++ /dev/null
@@ -1,50 +0,0 @@
-/**
- * @file IxOsBuffPoolMgt.h (Replaced by OSAL)
- *
- * @date 9 Oct 2002
- *
- * @brief This file contains the mbuf pool implementation API
- *
- * 
- * @par
- * IXP400 SW Release version 2.0
- * 
- * -- Copyright Notice --
- * 
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- * 
- * @par
- * SPDX-License-Identifier:	BSD-3-Clause
- * @par
- * -- End of Copyright Notice --
- * This module contains the implementation of the OS Services buffer pool
- * management service.  This module provides routines for creating pools
- * of buffers for exchange of network data, getting and returning buffers
- * from and to the pool, and some other utility functions. 
- * <P>
- * Currently, the pool has 2 underlying implementations - one for the vxWorks
- * OS, and another which attempts to be OS-agnostic so that it can be used on
- * other OS's such as Linux.  The API is largely the same for all OS's,
- * but there are some differences to be aware of.  These are documented
- * in the API descriptions below.
- * <P>
- * The most significant difference is this: when this module is used with
- * the WindRiver VxWorks OS, it will create a pool of vxWorks "MBufs".
- * These can be used directly with the vxWorks "netBufLib" OS Library.
- * For other OS's, it will create a pool of generic buffers.  These may need
- * to be converted into other buffer types (sk_buff's in Linux, for example)
- * before being used with any built-in OS routines available for
- * manipulating network data buffers.
- *
- * @sa IxOsBuffMgt.h
- */
-
-#ifndef IXOSBUFFPOOLMGT_H
-#define IXOSBUFFPOOLMGT_H
-
-#include "IxOsalBackward.h"
-
-#endif  /* IXOSBUFFPOOLMGT_H */
-
diff --git a/drivers/net/npe/include/IxOsCacheMMU.h b/drivers/net/npe/include/IxOsCacheMMU.h
deleted file mode 100644
index 2632cef751..0000000000
--- a/drivers/net/npe/include/IxOsCacheMMU.h
+++ /dev/null
@@ -1,36 +0,0 @@
-/**
- * @file IxOsCacheMMU.h
- *
- * @brief this file contains the API of the @ref IxCacheMMU component
- * 
- * <hr>
- * 
- * @par
- * IXP400 SW Release version 2.0
- * 
- * -- Copyright Notice --
- * 
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- * 
- * @par
- * SPDX-License-Identifier:	BSD-3-Clause
- * @par
- * -- End of Copyright Notice --
- */
-
-#ifndef IxOsCacheMMU_H
-
-#ifndef __doxygen_hide
-#define IxOsCacheMMU_H
-#endif /* __doxygen_hide */
-
-#ifdef __doxygen_HIDE
-#define IX_OS_CACHE_DOXYGEN
-#endif /* __doxygen_HIDE */
-
-#include "IxOsalBackward.h"
-
-#endif /* IxOsCacheMMU_H */
-
diff --git a/drivers/net/npe/include/IxOsPrintf.h b/drivers/net/npe/include/IxOsPrintf.h
deleted file mode 100644
index 7b573a4555..0000000000
--- a/drivers/net/npe/include/IxOsPrintf.h
+++ /dev/null
@@ -1,78 +0,0 @@
-/**
- * @file IxOsPrintf.h
- *
- * @brief this file contains the API of the @ref IxOsServices component
- * 
- * @par
- * IXP400 SW Release version 2.0
- * 
- * -- Copyright Notice --
- * 
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- * 
- * @par
- * SPDX-License-Identifier:	BSD-3-Clause
- * @par
- * -- End of Copyright Notice --
- */
-
-#include "IxTypes.h"
-
-#ifndef IxOsPrintf_H
-
-#ifndef __doxygen_hide
-#define IxOsPrintf_H
-#endif /* __doxygen_hide */
-
-#ifdef __wince
-
-#ifndef IX_USE_SERCONSOLE
-
-static int
-ixLogMsg(
-    char *pFormat, 
-    ...
-    )
-{    
-#ifndef IN_KERNEL
-    static WCHAR    pOutputString[256]; 
-	static char     pNarrowStr[256];
-    int             returnCnt = 0; 
-    va_list ap;
-    
-    pOutputString[0] = 0; 
-	pNarrowStr[0] = 0;	
-    
-    va_start(ap, pFormat);
-
-	returnCnt = _vsnprintf(pNarrowStr, 256, pFormat, ap);
-
-    MultiByteToWideChar(
-            CP_ACP, 
-            MB_PRECOMPOSED, 
-            pNarrowStr, 
-            -1, 
-            pOutputString, 
-            256
-            ); 
-
-    OutputDebugString(pOutputString);
-
-    return returnCnt; 
-#else
-    return 0; 
-#endif
-}
-#define printf ixLogMsg
-
-#endif /* IX_USE_SERCONSOLE */
-
-#endif /* __wince */
-
-/**
- * @} IxOsPrintf
- */
-
-#endif /* IxOsPrintf_H */
diff --git a/drivers/net/npe/include/IxOsServices.h b/drivers/net/npe/include/IxOsServices.h
deleted file mode 100644
index d3b88500e4..0000000000
--- a/drivers/net/npe/include/IxOsServices.h
+++ /dev/null
@@ -1,31 +0,0 @@
-/**
- * @file (Replaced by OSAL)
- *
- * @brief this file contains the API of the @ref IxOsServices component
- * 
- * 
- * @par
- * IXP400 SW Release version 2.0
- * 
- * -- Copyright Notice --
- * 
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- * 
- * @par
- * SPDX-License-Identifier:	BSD-3-Clause
- * @par
- * -- End of Copyright Notice --
- */
-#ifndef IxOsServices_H
-
-#ifndef __doxygen_hide
-#define IxOsServices_H
-#endif /* __doxygen_hide */
-
-#include "IxOsalBackward.h"
-
-#endif /* IxOsServices_H */
-
-
diff --git a/drivers/net/npe/include/IxOsServicesComponents.h b/drivers/net/npe/include/IxOsServicesComponents.h
deleted file mode 100644
index c5a6f68550..0000000000
--- a/drivers/net/npe/include/IxOsServicesComponents.h
+++ /dev/null
@@ -1,110 +0,0 @@
-/**
- * @file IxOsServicesComponents.h (Replaced by OSAL)
- *
- * @brief Header file for memory access
- *
- * @par
- * 
- * @par
- * IXP400 SW Release version 2.0
- * 
- * -- Copyright Notice --
- * 
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- * 
- * @par
- * SPDX-License-Identifier:	BSD-3-Clause
- * @par
- * -- End of Copyright Notice --
- */
-
-#ifndef IxOsServicesComponents_H
-#define IxOsServicesComponents_H
-
-#include "IxOsalBackward.h"
- * codelets_parityENAcc
- * timeSyncAcc
- * parityENAcc
- * sspAcc
- * i2c
- * integration_sspAcc
- * integration_i2c
-#define ix_timeSyncAcc         36
-#define ix_parityENAcc         37
-#define ix_codelets_parityENAcc     38
-#define ix_sspAcc              39
-#define ix_i2c                 40
-#define ix_integration_sspAcc  41
-#define ix_integration_i2c     42
-#define ix_osal		       43
-#define ix_integration_parityENAcc  44
-#define ix_integration_timeSyncAcc  45
-
-/***************************
- * timeSyncAcc
- ***************************/
-#if (IX_COMPONENT_NAME == ix_timeSyncAcc)
-
-#if defined (IX_OSSERV_VXWORKS_LE)
-
-#define CSR_LE_DATA_COHERENT_MAPPING
-
-#endif /* IX_OSSERV_VXWORKS_LE */
-
-#endif /* timeSyncAcc */
-
-/***************************
- * parityENAcc
- ***************************/
-#if (IX_COMPONENT_NAME == ix_parityENAcc)
-
-#if defined (IX_OSSERV_VXWORKS_LE)
-
-#define CSR_LE_DATA_COHERENT_MAPPING
-
-#endif /* IX_OSSERV_VXWORKS_LE */
-
-#endif /* parityENAcc */
-
-/***************************
- * codelets_parityENAcc
- ***************************/
-#if (IX_COMPONENT_NAME == ix_codelets_parityENAcc)
-
-#if defined (IX_OSSERV_VXWORKS_LE)
-
-#define CSR_LE_DATA_COHERENT_MAPPING
-
-#endif /* IX_OSSERV_VXWORKS_LE */
-
-#endif /* codelets_parityENAcc */
-
-#endif /* IxOsServicesComponents_H */
-
-/***************************
- * integration_timeSyncAcc
- ***************************/
-#if (IX_COMPONENT_NAME == ix_integration_timeSyncAcc)
-
-#if defined (IX_OSSERV_VXWORKS_LE)
-
-#define CSR_LE_DATA_COHERENT_MAPPING
-
-#endif /* IX_OSSERV_VXWORKS_LE */
-
-#endif /* integration_timeSyncAcc */
-
-/***************************
- * integration_parityENAcc
- ***************************/
-#if (IX_COMPONENT_NAME == ix_integration_parityENAcc)
-
-#if defined (IX_OSSERV_VXWORKS_LE)
-
-#define CSR_LE_DATA_COHERENT_MAPPING
-
-#endif /* IX_OSSERV_VXWORKS_LE */
-
-#endif /* integration_parityENAcc */
diff --git a/drivers/net/npe/include/IxOsServicesEndianess.h b/drivers/net/npe/include/IxOsServicesEndianess.h
deleted file mode 100644
index 383e30af56..0000000000
--- a/drivers/net/npe/include/IxOsServicesEndianess.h
+++ /dev/null
@@ -1,28 +0,0 @@
-/** 
- * @file IxOsServicesEndianess.h (Replaced by OSAL)
- * 
- * @brief Header file for determining system endianess and OS
- * 
- * @par
- * 
- * @par
- * IXP400 SW Release version 2.0
- * 
- * -- Copyright Notice --
- * 
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- * 
- * @par
- * SPDX-License-Identifier:	BSD-3-Clause
- * @par
- * -- End of Copyright Notice --
- */
- 
-#ifndef IxOsServicesEndianess_H
-#define IxOsServicesEndianess_H
-
-#include "IxOsalBackward.h"
-
-#endif /* IxOsServicesEndianess_H */
diff --git a/drivers/net/npe/include/IxOsServicesMemAccess.h b/drivers/net/npe/include/IxOsServicesMemAccess.h
deleted file mode 100644
index 896db14ac6..0000000000
--- a/drivers/net/npe/include/IxOsServicesMemAccess.h
+++ /dev/null
@@ -1,28 +0,0 @@
-/** 
- * @file IxOsServicesMemAccess.h (Replaced by OSAL)
- * 
- * @brief Header file for memory access
- * 
- * @par
- * 
- * @par
- * IXP400 SW Release version 2.0
- * 
- * -- Copyright Notice --
- * 
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- * 
- * @par
- * SPDX-License-Identifier:	BSD-3-Clause
- * @par
- * -- End of Copyright Notice --
- */
-
-#ifndef IxOsServicesMemAccess_H
-#define IxOsServicesMemAccess_H
-
-#include "IxOsalBackward.h"
-
-#endif /* IxOsServicesMemAccess_H */
diff --git a/drivers/net/npe/include/IxOsServicesMemMap.h b/drivers/net/npe/include/IxOsServicesMemMap.h
deleted file mode 100644
index 8af108126b..0000000000
--- a/drivers/net/npe/include/IxOsServicesMemMap.h
+++ /dev/null
@@ -1,30 +0,0 @@
-/**
- * @file IxOsServicesMemMap.h (Replaced by OSAL)
- * 
- * @brief Header file for memory access maps
- * 
- * @par
- * 
- * @par
- * IXP400 SW Release version 2.0
- * 
- * -- Copyright Notice --
- * 
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- * 
- * @par
- * SPDX-License-Identifier:	BSD-3-Clause
- * @par
- * -- End of Copyright Notice --
- */
-
-#ifndef IxOsServicesMemMap_H
-#define IxOsServicesMemMap_H
-
-#include "IxOsalBackward.h"
-#define IX_OSSERV_ETH_NPEA_MAP_SIZE           (0x1000)     /**< Eth for NPEA map size */
-#define IX_OSSERV_ETH_NPEA_PHYS_BASE           IXP425_Eth_NPEA_BASE_PHYS
-
-#endif /* IxOsServicesMemMap_H */
diff --git a/drivers/net/npe/include/IxOsal.h b/drivers/net/npe/include/IxOsal.h
deleted file mode 100644
index ac2631c9da..0000000000
--- a/drivers/net/npe/include/IxOsal.h
+++ /dev/null
@@ -1,1493 +0,0 @@
-/**
- * @file IxOsal.h
- *
- * @brief Top include file for OSAL 
- * 
- * 
- * @par
- * IXP400 SW Release version 2.0
- * 
- * -- Copyright Notice --
- * 
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- * 
- * @par
- * SPDX-License-Identifier:	BSD-3-Clause
- * @par
- * -- End of Copyright Notice --
- */
-
-#ifndef IxOsal_H
-#define IxOsal_H
-
-/* Basic types */
-#include "IxOsalTypes.h"
-
-/* Include assert */
-#include "IxOsalAssert.h"
-
-/* 
- * Config header gives users option to choose IO MEM 
- * and buffer management modules 
- */
-
-#include "IxOsalConfig.h"
-
-/*
- * Symbol file needed by some OS.
- */
-#include "IxOsalUtilitySymbols.h"
-
-/* OS-specific header */
-#include "IxOsalOs.h"
-
-
-/**
- * @defgroup IxOsal Operating System Abstraction Layer (IxOsal) API
- *
- * @brief This service provides a thin layer of OS dependency services. 
- *
- * This file contains the API to the functions which are some what OS dependant and would
- * require porting to a particular OS. 
- * A primary focus of the component development is to make them as OS independent as possible.
- * All other components should abstract their OS dependency to this module.
- * Services overview
- *	-# Data types, constants, defines
- *	-# Interrupts
- *              - bind interrupts to handlers
- *              - unbind interrupts from handlers
- *             	- disables all interrupts 
- *              - enables all interrupts 
- *              - selectively disables interrupts 
- *              - enables an interrupt level 
- *              - disables an interrupt level 
- *      -# Memory
- *              - allocates memory
- *              - frees memory 
- *              - copies memory zones 
- *              - fills a memory zone 
- *              - allocates cache-safe memory 
- *              - frees cache-safe memory 
- *              - physical to virtual address translation 
- *              - virtual to physical address translation 
- *              - cache to memory flush 
- *              - cache line invalidate 
- *      -# Threads
- *              - creates a new thread 
- *              - starts a newly created thread 
- *              - kills an existing thread 
- *              - exits a running thread 
- *              - sets the priority of an existing thread 
- *              - suspends thread execution 
- *              - resumes thread execution 
- *      -# IPC
- *              - creates a message queue 
- *              - deletes a message queue 
- *              - sends a message to a message queue 
- *              - receives a message from a message queue
- *      -# Thread Synchronisation
- *              - initializes a mutex 
- *              - locks a mutex 
- *              - unlocks a mutex 
- *              - non-blocking attempt to lock a mutex 
- *              - destroys a mutex object 
- *              - initializes a fast mutex 
- *              - non-blocking attempt to lock a fast mutex 
- *              - unlocks a fast mutex 
- *              - destroys a fast mutex object 
- *              - initializes a semaphore 
- *              - posts to (increments) a semaphore 
- *              - waits on (decrements) a semaphore 
- *              - non-blocking wait on semaphore 
- *              - gets semaphore value 
- *              - destroys a semaphore object 
- *              - yields execution of current thread 
- *      -# Time functions
- *              - yielding sleep for a number of milliseconds 
- *              - busy sleep for a number of microseconds 
- *              - value of the timestamp counter 
- *              - resolution of the timestamp counter 
- *              - system clock rate, in ticks 
- *              - current system time 
- *              - converts ixOsalTimeVal into ticks 
- *              - converts ticks into ixOsalTimeVal 
- *              - converts ixOsalTimeVal to milliseconds 
- *              - converts milliseconds to IxOsalTimeval 
- *              - "equal" comparison for IxOsalTimeval 
- *              - "less than" comparison for IxOsalTimeval 
- *              - "greater than" comparison for IxOsalTimeval 
- *              - "add" operator for IxOsalTimeval 
- *              - "subtract" operator for IxOsalTimeval 
- *      -# Logging
- *              - sets the current logging verbosity level 
- *              - interrupt-safe logging function 
- *      -# Timer services
- *              - schedules a repeating timer 
- *              - schedules a single-shot timer 
- *              - cancels a running timer 
- *              - displays all the running timers 
- *      -# Optional Modules
- *              - Buffer management module
- *              - I/O memory and endianess support module
- *
- * @{
- */
-
-
-/*
- * Prototypes
- */
-
-/* ==========================  Interrupts  ================================
- * 
- */
-
-/** 
- * @ingroup IxOsal
- *
- * @brief Binds an interrupt handler to an interrupt level
- *
- * @param irqLevel (in)   - interrupt level
- * @param irqHandler (in) - interrupt handler
- * @param parameter (in)  - custom parameter to be passed to the
- *                          interrupt handler
- *
- * Binds an interrupt handler to an interrupt level. The operation will
- * fail if the wrong level is selected, if the handler is NULL, or if the
- * interrupt is already bound. This functions binds the specified C
- * routine to an interrupt level. When called, the "parameter" value will
- * be passed to the routine.
- *
- * Reentrant: no
- * IRQ safe:  no
- *
- * @return IX_SUCCESS if the operation succeeded or IX_FAIL otherwise
- */
-PUBLIC IX_STATUS ixOsalIrqBind (UINT32 irqLevel,
-				IxOsalVoidFnVoidPtr irqHandler,
-				void *parameter);
-
-/** 
- * @ingroup IxOsal
- *
- * @brief Unbinds an interrupt handler from an interrupt level
- *
- * @param irqLevel (in)   - interrupt level
- *
- * Unbinds the selected interrupt level from any previously registered
- * handler 
- *
- * @li Reentrant: no
- * @li IRQ safe:  no
- *
- * @return IX_SUCCESS if the operation succeeded or IX_FAIL otherwise
- */
-PUBLIC IX_STATUS ixOsalIrqUnbind (UINT32 irqLevel);
-
-
-/** 
- * @ingroup IxOsal
- *
- * @brief Disables all interrupts
- *
- * @param - none
- *
- * Disables all the interrupts and prevents tasks scheduling 
- *
- * @li Reentrant: no
- * @li IRQ safe:  yes
- *
- * @return interrupt enable status prior to locking
- */
-PUBLIC UINT32 ixOsalIrqLock (void);
-
-/** 
- * @ingroup IxOsal
- *
- * @brief Enables all interrupts
- *
- * @param irqEnable (in) - interrupt enable status, prior to interrupt
- *                         locking 
- *
- * Enables the interrupts and task scheduling, cancelling the effect
- * of ixOsalIrqLock() 
- *
- * @li Reentrant: no
- * @li IRQ safe:  yes
- *
- * @return IX_SUCCESS if the operation succeeded or IX_FAIL otherwise
- */
-PUBLIC void ixOsalIrqUnlock (UINT32 irqEnable);
-
-/** 
- * @ingroup IxOsal
- *
- * @brief Selectively disables interrupts
- *
- * @param irqLevel - new interrupt level
- *
- * Disables the interrupts below the specified interrupt level 
- * 
- * @li Reentrant: no
- * @li IRQ safe:  yes
- *
- * @note Depending on the implementation this function can disable all
- *       the interrupts 
- *
- * @return previous interrupt level
- */
-PUBLIC UINT32 ixOsalIrqLevelSet (UINT32 irqLevel);
-
-/** 
- * @ingroup IxOsal
- *
- * @brief Enables an interrupt level
- *
- * @param irqLevel - interrupt level to enable
- *
- * Enables the specified interrupt level
- *
- * @li Reentrant: no
- * @li IRQ safe:  yes
- *
- * @return - none
- */
-PUBLIC void ixOsalIrqEnable (UINT32 irqLevel);
-
-/** 
- * @ingroup IxOsal
- *
- * @brief Disables an interrupt level
- *
- * @param irqLevel - interrupt level to disable
- *
- * Disables the specified interrupt level
- *
- * @li Reentrant: no
- * @li IRQ safe:  yes
- *
- * @return - none
- */
-PUBLIC void ixOsalIrqDisable (UINT32 irqLevel);
-
-
-/* =============================  Memory  =================================
- * 
- */
-
-/** 
- * @ingroup IxOsal
- *
- * @brief Allocates memory
- *
- * @param size - memory size to allocate, in bytes
- *
- * Allocates a memory zone of a given size
- *
- * @li Reentrant: no
- * @li IRQ safe:  no
- *
- * @return Pointer to the allocated zone or NULL if the allocation failed
- */
-PUBLIC void *ixOsalMemAlloc (UINT32 size);
-
-/** 
- * @ingroup IxOsal
- *
- * @brief Frees memory
- *
- * @param ptr - pointer to the memory zone
- *
- * Frees a previously allocated memory zone
- *
- * @li Reentrant: no
- * @li IRQ safe:  no
- *
- * @return - none
- */
-PUBLIC void ixOsalMemFree (void *ptr);
-
-/** 
- * @ingroup IxOsal
- *
- * @brief Copies memory zones
- *
- * @param dest  - destination memory zone
- * @param src   - source memory zone
- * @param count - number of bytes to copy
- *
- * Copies count bytes from the source memory zone pointed by src into the
- * memory zone pointed by dest.
- *
- * @li Reentrant: no
- * @li IRQ safe:  yes
- *
- * @return Pointer to the destination memory zone
- */
-PUBLIC void *ixOsalMemCopy (void *dest, void *src, UINT32 count);
-
-/** 
- * @ingroup IxOsal
- *
- * @brief Fills a memory zone
- *
- * @param ptr - pointer to the memory zone
- * @param filler - byte to fill the memory zone with
- * @param count - number of bytes to fill
- *
- * Fills a memory zone with a given constant byte
- *
- * @li Reentrant: no
- * @li IRQ safe:  yes
- *
- * @return Pointer to the memory zone
- */
-PUBLIC void *ixOsalMemSet (void *ptr, UINT8 filler, UINT32 count);
-
-/** 
- * @ingroup IxOsal
- *
- * @brief Allocates cache-safe memory
- *
- * @param size - size, in bytes, of the allocated zone
- *
- * Allocates a cache-safe memory zone of at least "size" bytes and returns
- * the pointer to the memory zone. This memory zone, depending on the
- * platform, is either uncached or aligned on a cache line boundary to make
- * the CACHE_FLUSH and CACHE_INVALIDATE macros safe to use. The memory
- * allocated with this function MUST be freed with ixOsalCacheDmaFree(),
- * otherwise memory corruption can occur.
- *
- * @li Reentrant: no
- * @li IRQ safe:  no
- *
- * @return Pointer to the memory zone or NULL if allocation failed
- *
- * @note It is important to note that cache coherence is maintained in
- * software by using the IX_OSAL_CACHE_FLUSH and IX_OSAL_CACHE_INVALIDATE
- * macros to maintain consistency between cache and external memory.
- */
-PUBLIC void *ixOsalCacheDmaMalloc (UINT32 size);
-
-/* Macros for ixOsalCacheDmaMalloc*/
-#define IX_OSAL_CACHE_DMA_MALLOC(size) ixOsalCacheDmaMalloc(size)
-
-/** 
- * @ingroup IxOsal
- *
- * @brief Frees cache-safe memory
- *
- * @param ptr   - pointer to the memory zone
- *
- * Frees a memory zone previously allocated with ixOsalCacheDmaMalloc()
- *
- * @li Reentrant: no
- * @li IRQ safe:  no
- *
- * @return - none
- */
-PUBLIC void ixOsalCacheDmaFree (void *ptr);
-
-#define IX_OSAL_CACHE_DMA_FREE(ptr)		ixOsalCacheDmaFree(ptr)
-
-/** 
- * @ingroup IxOsal
- *
- * @brief physical to virtual address translation
- *
- * @param physAddr - physical address
- *
- * Converts a physical address into its equivalent MMU-mapped virtual address
- *
- * @li Reentrant: no
- * @li IRQ safe:  yes
- *
- * @return Corresponding virtual address, as UINT32
- */
-#define IX_OSAL_MMU_PHYS_TO_VIRT(physAddr) \
-    IX_OSAL_OS_MMU_PHYS_TO_VIRT(physAddr)
-
-
-/** 
- * @ingroup IxOsal
- *
- * @brief virtual to physical address translation
- *
- * @param virtAddr - virtual address
- *
- * Converts a virtual address into its equivalent MMU-mapped physical address
- *
- * @li Reentrant: no
- * @li IRQ safe:  yes
- *
- * @return Corresponding physical address, as UINT32
- */
-#define IX_OSAL_MMU_VIRT_TO_PHYS(virtAddr)  \
-    IX_OSAL_OS_MMU_VIRT_TO_PHYS(virtAddr)
-
-
-
-/** 
- * @ingroup IxOsal
- *
- * @brief cache to memory flush
- *
- * @param addr - memory address to flush from cache
- * @param size - number of bytes to flush (rounded up to a cache line)
- *
- * Flushes the cached value of the memory zone pointed by "addr" into memory,
- * rounding up to a cache line. Use before the zone is to be read by a
- * processing unit which is not cache coherent with the main CPU.
- *
- * @li Reentrant: no
- * @li IRQ safe:  yes
- *
- * @return - none
- */
-#define IX_OSAL_CACHE_FLUSH(addr, size)  IX_OSAL_OS_CACHE_FLUSH(addr, size)
-
-
-
-/** 
- * @ingroup IxOsal
- *
- * @brief cache line invalidate
- *
- * @param addr - memory address to invalidate in cache
- * @param size - number of bytes to invalidate (rounded up to a cache line)
- *
- * Invalidates the cached value of the memory zone pointed by "addr",
- * rounding up to a cache line. Use before reading the zone from the main
- * CPU, if the zone has been updated by a processing unit which is not cache
- * coherent with the main CPU.
- *
- * @li Reentrant: no
- * @li IRQ safe:  yes
- *
- * @return - none
- */
-#define IX_OSAL_CACHE_INVALIDATE(addr, size)  IX_OSAL_OS_CACHE_INVALIDATE(addr, size)
-
-
-/* =============================  Threads  =================================
- * 
- */
-
-/** 
- * @ingroup IxOsal
- *
- * @brief Creates a new thread
- *
- * @param thread - handle of the thread to be created
- * @param threadAttr - pointer to a thread attribute object
- * @param startRoutine - thread entry point
- * @param arg - argument given to the thread
- *
- * Creates a thread given a thread handle and a thread attribute object. The
- * same thread attribute object can be used to create separate threads. "NULL"
- * can be specified as the attribute, in which case the default values will
- * be used. The thread needs to be explicitly started using ixOsalThreadStart().
- *
- * @li Reentrant: no
- * @li IRQ safe:  no
- *
- * @return - IX_SUCCESS/IX_FAIL
- */
-PUBLIC IX_STATUS ixOsalThreadCreate (IxOsalThread * thread,
-				     IxOsalThreadAttr * threadAttr,
-				     IxOsalVoidFnVoidPtr startRoutine,
-				     void *arg);
-
-/** 
- * @ingroup IxOsal
- *
- * @brief Starts a newly created thread
- *
- * @param thread - handle of the thread to be started
- *
- * Starts a thread given its thread handle. This function is to be called
- * only once, following the thread initialization.
- *
- * @li Reentrant: no
- * @li IRQ safe:  no
- *
- * @return - IX_SUCCESS/IX_FAIL
- */
-PUBLIC IX_STATUS ixOsalThreadStart (IxOsalThread * thread);
-
-/** 
- * @ingroup IxOsal
- *
- * @brief Kills an existing thread
- *
- * @param thread - handle of the thread to be killed
- *
- * Kills a thread given its thread handle.
- *
- * @li Reentrant: no
- * @li IRQ safe:  no
- *
- * @note It is not possible to kill threads in Linux kernel mode. This 
- * function will only send a SIGTERM signal, and it is the responsibility
- * of the thread to check for the presence of this signal with
- * signal_pending().
- *
- * @return -  IX_SUCCESS/IX_FAIL
- */
-PUBLIC IX_STATUS ixOsalThreadKill (IxOsalThread * thread);
-
-/** 
- * @ingroup IxOsal
- *
- * @brief Exits a running thread
- *
- * Terminates the calling thread
- *
- * @li Reentrant: no
- * @li IRQ safe:  no
- *
- * @return - This function never returns
- */
-PUBLIC void ixOsalThreadExit (void);
-
-/** 
- * @ingroup IxOsal
- *
- * @brief Sets the priority of an existing thread
- *
- * @param thread - handle of the thread
- * @param priority - new priority, between 0 and 255 (0 being the highest)
- *
- * Sets the thread priority
- *
- * @li Reentrant: no
- * @li IRQ safe:  no
- *
- * @return - IX_SUCCESS/IX_FAIL
- */
-PUBLIC IX_STATUS ixOsalThreadPrioritySet (IxOsalThread * thread,
-					  UINT32 priority);
-
-/** 
- * @ingroup IxOsal
- *
- * @brief Suspends thread execution
- *
- * @param thread - handle of the thread
- *
- * Suspends the thread execution
- *
- * @li Reentrant: no
- * @li IRQ safe:  no
- *
- * @return - IX_SUCCESS/IX_FAIL
- */
-PUBLIC IX_STATUS ixOsalThreadSuspend (IxOsalThread * thread);
-
-/** 
- * @ingroup IxOsal
- *
- * @brief Resumes thread execution
- *
- * @param thread - handle of the thread
- *
- * Resumes the thread execution
- *
- * @li Reentrant: no
- * @li IRQ safe:  no
- *
- * @return - IX_SUCCESS/IX_FAIL
- */
-PUBLIC IX_STATUS ixOsalThreadResume (IxOsalThread * thread);
-
-
-/* =======================  Message Queues (IPC) ==========================
- * 
- */
-
-/** 
- * @ingroup IxOsal
- *
- * @brief Creates a message queue
- *
- * @param queue - queue handle
- * @param msgCount - maximum number of messages to hold in the queue
- * @param msgLen - maximum length of each message, in bytes
- *
- * Creates a message queue of msgCount messages, each containing msgLen bytes
- *
- * @li Reentrant: no
- * @li IRQ safe:  no
- *
- * @return - IX_SUCCESS/IX_FAIL
- */
-PUBLIC IX_STATUS ixOsalMessageQueueCreate (IxOsalMessageQueue * queue,
-					   UINT32 msgCount, UINT32 msgLen);
-
-/** 
- * @ingroup IxOsal
- *
- * @brief Deletes a message queue
- *
- * @param queue - queue handle
- *
- * Deletes a message queue
- *
- * @li Reentrant: no
- * @li IRQ safe:  no
- *
- * @return - IX_SUCCESS/IX_FAIL
- */
-PUBLIC IX_STATUS ixOsalMessageQueueDelete (IxOsalMessageQueue * queue);
-
-/** 
- * @ingroup IxOsal
- *
- * @brief Sends a message to a message queue
- *
- * @param queue - queue handle
- * @param message - message to send
- *
- * Sends a message to the message queue. The message will be copied (at the
- * configured size of the message) into the queue.
- *
- * @li Reentrant: yes
- * @li IRQ safe:  yes
- *
- * @return - IX_SUCCESS/IX_FAIL
- */
-PUBLIC IX_STATUS ixOsalMessageQueueSend (IxOsalMessageQueue * queue,
-					 UINT8 * message);
-
-/** 
- * @ingroup IxOsal
- *
- * @brief Receives a message from a message queue
- *
- * @param queue - queue handle
- * @param message - pointer to where the message should be copied to
- *
- * Retrieves the first message from the message queue
- *
- * @li Reentrant: yes
- * @li IRQ safe:  yes
- *
- * @return - IX_SUCCESS/IX_FAIL
- */
-PUBLIC IX_STATUS ixOsalMessageQueueReceive (IxOsalMessageQueue * queue,
-					    UINT8 * message);
-
-
-/* =======================  Thread Synchronisation ========================
- * 
- */
-
-/** 
- * @ingroup IxOsal
- *
- * @brief initializes a mutex
- *
- * @param mutex - mutex handle
- *
- * Initializes a mutex object
- *
- * @li Reentrant: no
- * @li IRQ safe:  no
- *
- * @return - IX_SUCCESS/IX_FAIL
- */
-PUBLIC IX_STATUS ixOsalMutexInit (IxOsalMutex * mutex);
-
-/** 
- * @ingroup IxOsal
- *
- * @brief locks a mutex
- *
- * @param mutex - mutex handle
- * @param timeout - timeout in ms; IX_OSAL_WAIT_FOREVER (-1) to wait forever
- *                  or IX_OSAL_WAIT_NONE to return immediately
- *
- * Locks a mutex object
- *
- * @li Reentrant: yes
- * @li IRQ safe:  no
- *
- * @return - IX_SUCCESS/IX_FAIL
- */
-PUBLIC IX_STATUS ixOsalMutexLock (IxOsalMutex * mutex, INT32 timeout);
-
-/** 
- * @ingroup IxOsal
- *
- * @brief Unlocks a mutex
- *
- * @param mutex - mutex handle
- *
- * Unlocks a mutex object
- *
- * @li Reentrant: yes
- * @li IRQ safe:  yes
- *
- * @return - IX_SUCCESS/IX_FAIL
- */
-PUBLIC IX_STATUS ixOsalMutexUnlock (IxOsalMutex * mutex);
-
-/** 
- * @ingroup IxOsal
- *
- * @brief Non-blocking attempt to lock a mutex
- *
- * @param mutex - mutex handle
- *
- * Attempts to lock a mutex object, returning immediately with IX_SUCCESS if
- * the lock was successful or IX_FAIL if the lock failed
- *
- * @li Reentrant: yes
- * @li IRQ safe:  no
- *
- * @return - IX_SUCCESS/IX_FAIL
- */
-PUBLIC IX_STATUS ixOsalMutexTryLock (IxOsalMutex * mutex);
-
-/** 
- * @ingroup IxOsal
- *
- * @brief Destroys a mutex object
- *
- * @param mutex - mutex handle
- * @param
- *
- * Destroys a mutex object; the caller should ensure that no thread is
- * blocked on this mutex
- *
- * @li Reentrant: no
- * @li IRQ safe:  no
- *
- * @return - IX_SUCCESS/IX_FAIL
- */
-PUBLIC IX_STATUS ixOsalMutexDestroy (IxOsalMutex * mutex);
-
-/** 
- * @ingroup IxOsal
- *
- * @brief Initializes a fast mutex
- *
- * @param mutex - fast mutex handle
- *
- * Initializes a fast mutex object
- *
- * @li Reentrant: yes
- * @li IRQ safe:  yes
- *
- * @return - IX_SUCCESS/IX_FAIL
- */
-PUBLIC IX_STATUS ixOsalFastMutexInit (IxOsalFastMutex * mutex);
-
-/** 
- * @ingroup IxOsal
- *
- * @brief Non-blocking attempt to lock a fast mutex
- *
- * @param mutex - fast mutex handle
- *
- * Attempts to lock a fast mutex object, returning immediately with
- * IX_SUCCESS if the lock was successful or IX_FAIL if the lock failed
- *
- * @li Reentrant: yes
- * @li IRQ safe:  yes
- *
- * @return - IX_SUCCESS/IX_FAIL
- */
-PUBLIC IX_STATUS ixOsalFastMutexTryLock (IxOsalFastMutex * mutex);
-
-/** 
- * @ingroup IxOsal
- *
- * @brief Unlocks a fast mutex
- *
- * @param mutex - fast mutex handle
- *
- * Unlocks a fast mutex object
- *
- * @li Reentrant: yes
- * @li IRQ safe:  yes
- *
- * @return - IX_SUCCESS/IX_FAIL
- */
-PUBLIC IX_STATUS ixOsalFastMutexUnlock (IxOsalFastMutex * mutex);
-
-/** 
- * @ingroup IxOsal
- *
- * @brief Destroys a fast mutex object
- *
- * @param mutex - fast mutex handle
- *
- * Destroys a fast mutex object
- *
- * @li Reentrant: yes
- * @li IRQ safe:  yes
- *
- * @return - IX_SUCCESS/IX_FAIL
- */
-PUBLIC IX_STATUS ixOsalFastMutexDestroy (IxOsalFastMutex * mutex);
-
-/** 
- * @ingroup IxOsal
- *
- * @brief Initializes a semaphore
- *
- * @param semaphore - semaphore handle
- * @param value - initial semaphore value
- *
- * Initializes a semaphore object
- *
- * @li Reentrant: no
- * @li IRQ safe:  no
- *
- * @return - IX_SUCCESS/IX_FAIL
- */
-PUBLIC IX_STATUS ixOsalSemaphoreInit (IxOsalSemaphore * semaphore,
-				      UINT32 value);
-
-/** 
- * @ingroup IxOsal
- *
- * @brief Posts to (increments) a semaphore
- *
- * @param semaphore - semaphore handle
- *
- * Increments a semaphore object
- *
- * @li Reentrant: no
- * @li IRQ safe:  yes
- *
- * @return - IX_SUCCESS/IX_FAIL
- */
-PUBLIC IX_STATUS ixOsalSemaphorePost (IxOsalSemaphore * semaphore);
-
-/** 
- * @ingroup IxOsal
- *
- * @brief Waits on (decrements) a semaphore
- *
- * @param semaphore - semaphore handle
- * @param timeout - timeout, in ms; IX_OSAL_WAIT_FOREVER (-1) if the thread
- * is to block indefinitely or IX_OSAL_WAIT_NONE (0) if the thread is to
- * return immediately even if the call fails
- *
- * Decrements a semaphore, blocking if the semaphore is
- * unavailable (value is 0).
- *
- * @li Reentrant: no
- * @li IRQ safe:  no
- *
- * @return - IX_SUCCESS/IX_FAIL
- */
-PUBLIC IX_STATUS ixOsalSemaphoreWait (IxOsalSemaphore * semaphore,
-				      INT32 timeout);
-
-/** 
- * @ingroup IxOsal
- *
- * @brief Non-blocking wait on semaphore
- *
- * @param semaphore - semaphore handle
- *
- * Decrements a semaphore, not blocking the calling thread if the semaphore
- * is unavailable
- *
- * @li Reentrant: no
- * @li IRQ safe:  no
- *
- * @return - IX_SUCCESS/IX_FAIL
- */
-PUBLIC IX_STATUS ixOsalSemaphoreTryWait (IxOsalSemaphore * semaphore);
-
-/** 
- * @ingroup IxOsal
- *
- * @brief Gets semaphore value
- *
- * @param semaphore - semaphore handle
- * @param value - location to store the semaphore value
- *
- * Retrieves the current value of a semaphore object
- *
- * @li Reentrant: no
- * @li IRQ safe:  no
- *
- * @return - IX_SUCCESS/IX_FAIL
- */
-PUBLIC IX_STATUS ixOsalSemaphoreGetValue (IxOsalSemaphore * semaphore,
-					  UINT32 * value);
-
-/** 
- * @ingroup IxOsal
- *
- * @brief Destroys a semaphore object
- *
- * @param semaphore - semaphore handle
- *
- * Destroys a semaphore object; the caller should ensure that no thread is
- * blocked on this semaphore
- *
- * @li Reentrant: no
- * @li IRQ safe:  no
- *
- * @return - IX_SUCCESS/IX_FAIL
- */
-PUBLIC IX_STATUS ixOsalSemaphoreDestroy (IxOsalSemaphore * semaphore);
-
-/** 
- * @ingroup IxOsal
- *
- * @brief Yields execution of current thread
- *
- * Yields the execution of the current thread
- *
- * @li Reentrant: no
- * @li IRQ safe:  no
- *
- * @return - none
- */
-PUBLIC void ixOsalYield (void);
-
-
-/* ========================== Time functions  ===========================
- * 
- */
-
-/** 
- * @ingroup IxOsal
- *
- * @brief Yielding sleep for a number of milliseconds
- *
- * @param milliseconds - number of milliseconds to sleep
- *
- * The calling thread will sleep for the specified number of milliseconds.
- * This sleep is yielding, hence other tasks will be scheduled by the
- * operating system during the sleep period. Calling this function with an
- * argument of 0 will place the thread at the end of the current scheduling
- * loop.
- *
- * @li Reentrant: no
- * @li IRQ safe:  no
- *
- * @return - none
- */
-PUBLIC void ixOsalSleep (UINT32 milliseconds);
-
-/** 
- * @ingroup IxOsal
- *
- * @brief Busy sleep for a number of microseconds
- *
- * @param microseconds - number of microseconds to sleep
- *
- * Sleeps for the specified number of microseconds, without explicitly
- * yielding thread execution to the OS scheduler
- *
- * @li Reentrant: yes
- * @li IRQ safe:  yes
- *
- * @return - none
- */
-PUBLIC void ixOsalBusySleep (UINT32 microseconds);
-
-/** 
- * @ingroup IxOsal
- *
- * @brief XXX
- *
- * Retrieves the current timestamp
- *
- * @li Reentrant: yes
- * @li IRQ safe:  yes
- *
- * @return - The current timestamp
- *
- * @note The implementation of this function is platform-specific. Not
- * all the platforms provide a high-resolution timestamp counter.
- */
-PUBLIC UINT32 ixOsalTimestampGet (void);
-
-/** 
- * @ingroup IxOsal
- *
- * @brief Resolution of the timestamp counter
- *
- * Retrieves the resolution (frequency) of the timestamp counter.
- *
- * @li Reentrant: yes
- * @li IRQ safe:  yes
- *
- * @return - The resolution of the timestamp counter
- *
- * @note The implementation of this function is platform-specific. Not all
- * the platforms provide a high-resolution timestamp counter.
- */
-PUBLIC UINT32 ixOsalTimestampResolutionGet (void);
-
-/** 
- * @ingroup IxOsal
- *
- * @brief System clock rate, in ticks
- *
- * Retrieves the resolution (number of ticks per second) of the system clock
- *
- * @li Reentrant: no
- * @li IRQ safe:  no
- *
- * @return - The system clock rate
- *
- * @note The implementation of this function is platform and OS-specific.
- * The system clock rate is not always available - e.g. Linux does not
- * provide this information in user mode
- */
-PUBLIC UINT32 ixOsalSysClockRateGet (void);
-
-/** 
- * @ingroup IxOsal
- *
- * @brief Current system time
- *
- * @param tv - pointer to an IxOsalTimeval structure to store the current
- *             time in
- *
- * Retrieves the current system time (real-time)
- *
- * @li Reentrant: no
- * @li IRQ safe:  no
- *
- * @return - none
- *
- * @note The implementation of this function is platform-specific. Not all
- * platforms have a real-time clock.
- */
-PUBLIC void ixOsalTimeGet (IxOsalTimeval * tv);
-
-
-
-/* Internal function to convert timer val to ticks.
- * NOTE - This should not be called by the user.
- * Use the macro IX_OSAL_TIMEVAL_TO_TICKS 
- * OS-independent, implemented in framework.
- */
-PUBLIC UINT32 ixOsalTimevalToTicks (IxOsalTimeval tv);
-
-
-/** 
- * @ingroup IxOsal
- *
- * @brief Converts ixOsalTimeVal into ticks
- *
- * @param tv - an IxOsalTimeval structure
- *
- * Converts an IxOsalTimeval structure into OS ticks
- *
- * @li Reentrant: yes
- * @li IRQ safe:  yes
- *
- * @return - Corresponding number of ticks
- * 
- * Note: This function is OS-independent. Implemented by core.
- */
-#define IX_OSAL_TIMEVAL_TO_TICKS(tv)  ixOsalTimevalToTicks(tv)
-
-
-
-/* Internal function to convert ticks to timer val
- * NOTE - This should not be called by the user.
- * Use the macro IX_OSAL_TICKS_TO_TIMEVAL 
- */
-
-PUBLIC void ixOsalTicksToTimeval (UINT32 ticks, IxOsalTimeval * pTv);
-
-
-/** 
- * @ingroup IxOsal
- *
- * @brief Converts ticks into ixOsalTimeVal 
- *
- * @param ticks - number of ticks
- * @param pTv - pointer to the destination structure
- *
- * Converts the specified number of ticks into an IxOsalTimeval structure
- *
- * @li Reentrant: yes
- * @li IRQ safe:  yes
- *
- * @return - Corresponding IxOsalTimeval structure
- * Note: This function is OS-independent. Implemented by core.
- */
-#define IX_OSAL_TICKS_TO_TIMEVAL(ticks, pTv)  \
-    ixOsalTicksToTimeval(ticks, pTv)
-
-
-
-
-/** 
- * @ingroup IxOsal
- *
- * @brief Converts ixOsalTimeVal to milliseconds
- *
- * @param tv - IxOsalTimeval structure to convert
- *
- * Converts an IxOsalTimeval structure into milliseconds
- *
- * @li Reentrant: yes
- * @li IRQ safe:  yes
- *
- * @return - Corresponding number of milliseconds
- * Note: This function is OS-independent. Implemented by core.
- */
-#define IX_OSAL_TIMEVAL_TO_MS(tv)     ((tv.secs * 1000) + (tv.nsecs / 1000000))
-
-
-/** 
- * @ingroup IxOsal
- *
- * @brief Converts milliseconds to IxOsalTimeval
- *
- * @param milliseconds - number of milliseconds to convert
- * @param pTv - pointer to the destination structure
- *
- * Converts a millisecond value into an IxOsalTimeval structure
- *
- * @li Reentrant: yes
- * @li IRQ safe:  yes
- *
- * @return - Corresponding IxOsalTimeval structure
- * Note: This function is OS-independent. Implemented by core.
- */
-#define IX_OSAL_MS_TO_TIMEVAL(milliseconds, pTv)  \
-   	    ((IxOsalTimeval *) pTv)->secs = milliseconds / 1000;			  \
-        ((IxOsalTimeval *) pTv)->nsecs = (milliseconds % 1000) * 1000000
-
-
-/** 
- * @ingroup IxOsal
- *
- * @brief "equal" comparison for IxOsalTimeval
- *
- * @param tvA, tvB - IxOsalTimeval structures to compare
- *
- * Compares two IxOsalTimeval structures for equality
- *
- * @li Reentrant: yes
- * @li IRQ safe:  yes
- *
- * @return - true if the structures are equal
- *         - false otherwise
- * Note: This function is OS-independant
- */
-#define IX_OSAL_TIME_EQ(tvA, tvB)        \
-        ((tvA).secs == (tvB).secs && (tvA).nsecs == (tvB).nsecs)
-
-
-/** 
- * @ingroup IxOsal
- *
- * @brief "less than" comparison for IxOsalTimeval
- *
- * @param tvA, tvB - IxOsalTimeval structures to compare
- *
- * Compares two IxOsalTimeval structures to determine if the first one is
- * less than the second one
- *
- * @li Reentrant: yes
- * @li IRQ safe:  yes
- *
- * @return - true if tvA < tvB
- *         - false otherwise
- * Note: This function is OS-independent. Implemented by core.
- */
-#define IX_OSAL_TIME_LT(tvA,tvB) \
-        ((tvA).secs  < (tvB).secs ||	\
-        ((tvA).secs == (tvB).secs && (tvA).nsecs < (tvB).nsecs))
-
-
-/** 
- * @ingroup IxOsal
- *
- * @brief "greater than" comparison for IxOsalTimeval
- *
- * @param tvA, tvB - IxOsalTimeval structures to compare
- *
- * Compares two IxOsalTimeval structures to determine if the first one is
- * greater than the second one
- *
- * @li Reentrant: yes
- * @li IRQ safe:  yes
- *
- * @return - true if tvA > tvB
- *         - false  otherwise
- * Note: This function is OS-independent.
- */
-#define IX_OSAL_TIME_GT(tvA, tvB)  \
-        ((tvA).secs  > (tvB).secs ||	\
-        ((tvA).secs == (tvB).secs && (tvA).nsecs > (tvB).nsecs))
-
-
-/** 
- * @ingroup IxOsal
- *
- * @brief "add" operator for IxOsalTimeval
- *
- * @param tvA, tvB - IxOsalTimeval structures to add
- *
- * Adds the second IxOsalTimevalStruct to the first one (equivalent to
- * tvA += tvB)
- *
- * @li Reentrant: yes
- * @li IRQ safe:  yes
- *
- * @return - none
- * Note: This function is OS-independent.
- */
-#define IX_OSAL_TIME_ADD(tvA, tvB)  \
-        (tvA).secs += (tvB).secs;   \
-        (tvA).nsecs += (tvB).nsecs; \
-        if ((tvA).nsecs >= IX_OSAL_BILLION) \
-    	{ \
-        (tvA).secs++; \
-        (tvA).nsecs -= IX_OSAL_BILLION; }
-
-
-/** 
- * @ingroup IxOsal
- *
- * @brief "subtract" operator for IxOsalTimeval
- *
- * @param tvA, tvB - IxOsalTimeval structures to subtract
- *
- * Subtracts the second IxOsalTimevalStruct from the first one (equivalent
- * to tvA -= tvB)
- *
- * @li Reentrant: yes
- * @li IRQ safe:  yes
- *
- * @return - none
- * Note: This function is OS-independent. Implemented by core.
- */
-#define IX_OSAL_TIME_SUB(tvA, tvB)   \
-        if ((tvA).nsecs >= (tvB).nsecs) \
-        { \
-          (tvA).secs -= (tvB).secs; \
-          (tvA).nsecs -= (tvB).nsecs; \
-        } \
-        else \
-        { \
-          (tvA).secs -= ((tvB).secs + 1); \
-          (tvA).nsecs += IX_OSAL_BILLION - (tvB).nsecs; \
-        }
-
-
-/* ============================= Logging  ==============================
- * 
- */
-
-/** 
- * @ingroup IxOsal
- *
- * @brief Interrupt-safe logging function
- *
- * @param level - identifier prefix for the message
- * @param device - output device
- * @param format - message format, in a printf format
- * @param ... - up to 6 arguments to be printed
- *
- * IRQ-safe logging function, similar to printf. Accepts up to 6 arguments
- * to print (excluding the level, device and the format). This function will
- * actually display the message only if the level is lower than the current
- * verbosity level or if the IX_OSAL_LOG_USER level is used. An output device
- * must be specified (see IxOsalTypes.h).
- *
- * @li Reentrant: yes
- * @li IRQ safe:  yes
- *
- * @return - Beside the exceptions documented in the note below, the returned
- * value is the number of printed characters, or -1 if the parameters are
- * incorrect (NULL format, unknown output device)
- *
- * @note The exceptions to the return value are:
- * VxWorks: The return value is 32 if the specified level is 1 and 64
- * if the specified level is greater than 1 and less or equal than 9.
- * WinCE: If compiled for EBOOT then the return value is always 0.
- *
- * @note The given print format should take into account the specified 
- * output device. IX_OSAL_STDOUT supports all the usual print formats,
- * however a custom hex display specified by IX_OSAL_HEX would support
- * only a fixed number of hexadecimal digits.
- */
-PUBLIC INT32 ixOsalLog (IxOsalLogLevel level,
-			IxOsalLogDevice device,
-			char *format,
-			int arg1,
-			int arg2, int arg3, int arg4, int arg5, int arg6);
-
-/** 
- * @ingroup IxOsal
- *
- * @brief sets the current logging verbosity level
- *
- * @param level - new log verbosity level
- *
- * Sets the log verbosity level. The default value is IX_OSAL_LOG_ERROR.
- *
- * @li Reentrant: yes
- * @li IRQ safe:  yes
- *
- * @return - Old log verbosity level
- */
-PUBLIC UINT32 ixOsalLogLevelSet (UINT32 level);
-
-
-/* ============================= Logging  ==============================
- * 
- */
-
-/** 
- * @ingroup IxOsal
- *
- * @brief Schedules a repeating timer
- *
- * @param timer - handle of the timer object
- * @param period - timer trigger period, in milliseconds
- * @param priority - timer priority (0 being the highest)
- * @param callback - user callback to invoke when the timer triggers
- * @param param - custom parameter passed to the callback
- *
- * Schedules a timer to be called every period milliseconds. The timer
- * will invoke the specified callback function possibly in interrupt
- * context, passing the given parameter. If several timers trigger at the
- * same time contention issues are dealt according to the specified timer
- * priorities.
- *
- * @li Reentrant: no
- * @li IRQ safe:  no
- *
- * @return - IX_SUCCESS/IX_FAIL
- */
-PUBLIC IX_STATUS ixOsalRepeatingTimerSchedule (IxOsalTimer * timer,
-					       UINT32 period,
-					       UINT32 priority,
-					       IxOsalVoidFnVoidPtr callback,
-					       void *param);
-
-/** 
- * @ingroup IxOsal
- *
- * @brief Schedules a single-shot timer
- *
- * @param timer - handle of the timer object
- * @param period - timer trigger period, in milliseconds
- * @param priority - timer priority (0 being the highest)
- * @param callback - user callback to invoke when the timer triggers
- * @param param - custom parameter passed to the callback
- *
- * Schedules a timer to be called after period milliseconds. The timer
- * will cease to function past its first trigger. The timer will invoke
- * the specified callback function, possibly in interrupt context, passing
- * the given parameter. If several timers trigger at the same time contention
- * issues are dealt according to the specified timer priorities.
- *
- * @li Reentrant: no
- * @li IRQ safe:  no
- *
- * @return - IX_SUCCESS/IX_FAIL
- */
-PUBLIC IX_STATUS
-ixOsalSingleShotTimerSchedule (IxOsalTimer * timer,
-			       UINT32 period,
-			       UINT32 priority,
-			       IxOsalVoidFnVoidPtr callback, void *param);
-
-/** 
- * @ingroup IxOsal
- *
- * @brief Cancels a running timer
- *
- * @param timer - handle of the timer object
- *
- * Cancels a single-shot or repeating timer.
- *
- * @li Reentrant: no
- * @li IRQ safe:  yes
- *
- * @return - IX_SUCCESS/IX_FAIL
- */
-PUBLIC IX_STATUS ixOsalTimerCancel (IxOsalTimer * timer);
-
-/** 
- * @ingroup IxOsal
- *
- * @brief displays all the running timers
- *
- * Displays a list with all the running timers and their parameters (handle,
- * period, type, priority, callback and user parameter)
- *
- * @li Reentrant: no
- * @li IRQ safe:  no
- *
- * @return - none
- */
-PUBLIC void ixOsalTimersShow (void);
-
-
-/* ============================= Version  ==============================
- * 
- */
-
-/**
- * @ingroup IxOsal
- *
- * @brief provides the name of the Operating System running
- *
- * @param osName - Pointer to a NULL-terminated string of characters
- * that holds the name of the OS running.
- * This is both an input and an ouput parameter
- * @param maxSize - Input parameter that defines the maximum number of
- * bytes that can be stored in osName
- *
- * Returns a string of characters that describe the Operating System name
- *
- * @li Reentrant: yes
- * @li IRQ safe:  yes
- *
- * return - IX_SUCCESS for successful retrieval
- *        - IX_FAIL if (osType == NULL | maxSize =< 0)
- */
-PUBLIC IX_STATUS ixOsalOsNameGet (INT8* osName, INT32 maxSize);
-
-/**
- * @ingroup IxOsal
- *
- * @brief provides the version of the Operating System running
- *
- * @param osVersion - Pointer to a NULL terminated string of characters
- * that holds the version of the OS running.
- * This is both an input and an ouput parameter
- * @param maxSize - Input parameter that defines the maximum number of
- * bytes that can be stored in osVersion
- *
- * Returns a string of characters that describe the Operating System's version
- *
- * @li Reentrant: yes
- * @li IRQ safe:  yes
- *
- * return - IX_SUCCESS for successful retrieval
- *        - IX_FAIL if (osVersion == NULL | maxSize =< 0)
- */
-PUBLIC IX_STATUS ixOsalOsVersionGet(INT8* osVersion, INT32 maxSize);
-
-
-
-/**
- * @} IxOsal
- */
-
-#endif /* IxOsal_H */
diff --git a/drivers/net/npe/include/IxOsalAssert.h b/drivers/net/npe/include/IxOsalAssert.h
deleted file mode 100644
index ac26bb6bf5..0000000000
--- a/drivers/net/npe/include/IxOsalAssert.h
+++ /dev/null
@@ -1,57 +0,0 @@
-/*
- * @file        IxOsalAssert.h 
- * @author	Intel Corporation
- * @date        25-08-2004
- *
- * @brief       description goes here
- *
- * @par
- * IXP400 SW Release version 2.0
- * 
- * -- Copyright Notice --
- * 
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- * 
- * @par
- * SPDX-License-Identifier:	BSD-3-Clause
- * @par
- * -- End of Copyright Notice --
- */
-
-#ifndef IX_OSAL_ASSERT_H
-#define IX_OSAL_ASSERT_H
-
-/*
- * Put the system defined include files required
- * @par
- * <TAGGED>
- */
-
-#include "IxOsalOsAssert.h"
-
-/**
- * @brief Assert macro, assert the condition is true. This
- *        will not be compiled out.
- *        N.B. will result in a system crash if it is false.
- */
-#define IX_OSAL_ASSERT(c) IX_OSAL_OS_ASSERT(c)
-
-
-/**
- * @brief Ensure macro, ensure the condition is true.
- *        This will be conditionally compiled out and
- *        may be used for test purposes.
- */
-#ifdef IX_OSAL_ENSURE_ON
-#define IX_OSAL_ENSURE(c, str) do { \
-if (!(c)) ixOsalLog (IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT, str, \
-0, 0, 0, 0, 0, 0); } while (0)
-
-#else
-#define IX_OSAL_ENSURE(c, str)
-#endif
-
-
-#endif /* IX_OSAL_ASSERT_H */
diff --git a/drivers/net/npe/include/IxOsalBackward.h b/drivers/net/npe/include/IxOsalBackward.h
deleted file mode 100644
index 8e4a6fb511..0000000000
--- a/drivers/net/npe/include/IxOsalBackward.h
+++ /dev/null
@@ -1,41 +0,0 @@
-/** 
- * This file is intended to provide backward 
- * compatibility for main osService/OSSL 
- * APIs. 
- *
- * It shall be phased out gradually and users
- * are strongly recommended to use IX_OSAL API.
- *
- * @par
- * IXP400 SW Release version 2.0
- * 
- * -- Copyright Notice --
- * 
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- * 
- * @par
- * SPDX-License-Identifier:	BSD-3-Clause
- * @par
- * -- End of Copyright Notice --
- */
-
-#ifndef IX_OSAL_BACKWARD_H
-#define IX_OSAL_BACKWARD_H
-
-#include "IxOsal.h"
-
-#include "IxOsalBackwardCacheMMU.h"
-
-#include "IxOsalBackwardOsServices.h"
-
-#include "IxOsalBackwardMemMap.h"
-
-#include "IxOsalBackwardBufferMgt.h"
-
-#include "IxOsalBackwardOssl.h"
-
-#include "IxOsalBackwardAssert.h"
-
-#endif /* IX_OSAL_BACKWARD_H */
diff --git a/drivers/net/npe/include/IxOsalBackwardAssert.h b/drivers/net/npe/include/IxOsalBackwardAssert.h
deleted file mode 100644
index cf50a7a64b..0000000000
--- a/drivers/net/npe/include/IxOsalBackwardAssert.h
+++ /dev/null
@@ -1,30 +0,0 @@
-/** 
- * This file is intended to provide backward 
- * compatibility for main osService/OSSL 
- * APIs. 
- *
- * It shall be phased out gradually and users
- * are strongly recommended to use IX_OSAL API.
- *
- * @par
- * IXP400 SW Release version 2.0
- * 
- * -- Copyright Notice --
- * 
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- * 
- * @par
- * SPDX-License-Identifier:	BSD-3-Clause
- * @par
- * -- End of Copyright Notice --
- */
-
-#ifndef IX_OSAL_BACKWARD_ASSERT_H
-#define IX_OSAL_BACKWARD_ASSERT_H
-
-#define IX_ENSURE(c, str)	IX_OSAL_ENSURE(c, str)
-#define IX_ASSERT(c)		IX_OSAL_ASSERT(c)
-
-#endif /* IX_OSAL_BACKWARD_ASSERT_H */
diff --git a/drivers/net/npe/include/IxOsalBackwardBufferMgt.h b/drivers/net/npe/include/IxOsalBackwardBufferMgt.h
deleted file mode 100644
index 46df29d3d2..0000000000
--- a/drivers/net/npe/include/IxOsalBackwardBufferMgt.h
+++ /dev/null
@@ -1,135 +0,0 @@
-/** 
- * This file is intended to provide backward 
- * compatibility for main osService/OSSL 
- * APIs. 
- *
- * It shall be phased out gradually and users
- * are strongly recommended to use IX_OSAL API.
- *
- * @par
- * IXP400 SW Release version 2.0
- * 
- * -- Copyright Notice --
- * 
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- * 
- * @par
- * SPDX-License-Identifier:	BSD-3-Clause
- * @par
- * -- End of Copyright Notice --
- */
-
-#ifndef IX_OSAL_BACKWARD_BUFFER_MGT_H
-#define IX_OSAL_BACKWARD_BUFFER_MGT_H
-
-typedef IX_OSAL_MBUF IX_MBUF;
-
-typedef IX_OSAL_MBUF_POOL IX_MBUF_POOL;
-
-
-#define IX_MBUF_NEXT_BUFFER_IN_PKT_PTR(m_blk_ptr)  \
-		IX_OSAL_MBUF_NEXT_BUFFER_IN_PKT_PTR(m_blk_ptr)
-
-
-#define IX_MBUF_NEXT_PKT_IN_CHAIN_PTR(m_blk_ptr)  \
-		IX_OSAL_MBUF_NEXT_PKT_IN_CHAIN_PTR(m_blk_ptr)
-
-
-#define IX_MBUF_MDATA(m_blk_ptr)  \
-		IX_OSAL_MBUF_MDATA(m_blk_ptr)
-
-
-#define IX_MBUF_MLEN(m_blk_ptr) \
-		IX_OSAL_MBUF_MLEN(m_blk_ptr)
-
-
-#define IX_MBUF_TYPE(m_blk_ptr) \
-		IX_OSAL_MBUF_MTYPE(m_blk_ptr)
-
-/* Same as IX_MBUF_TYPE */
-#define IX_MBUF_MTYPE(m_blk_ptr) \
-                IX_OSAL_MBUF_MTYPE(m_blk_ptr)
-
-#define IX_MBUF_FLAGS(m_blk_ptr)	\
-		IX_OSAL_MBUF_FLAGS(m_blk_ptr)
-
-
-#define IX_MBUF_NET_POOL(m_blk_ptr)	\
-		IX_OSAL_MBUF_NET_POOL(m_blk_ptr)
-
-
-#define IX_MBUF_PKT_LEN(m_blk_ptr)	\
-		IX_OSAL_MBUF_PKT_LEN(m_blk_ptr)
-
-
-#define IX_MBUF_PRIV(m_blk_ptr)		\
-		IX_OSAL_MBUF_PRIV(m_blk_ptr)
-
-
-#define IX_MBUF_ALLOCATED_BUFF_LEN(m_blk_ptr)  \
-		IX_OSAL_MBUF_ALLOCATED_BUFF_LEN(m_blk_ptr)
-
-
-#define IX_MBUF_ALLOCATED_BUFF_DATA(m_blk_ptr)  \
-		IX_OSAL_MBUF_ALLOCATED_BUFF_DATA(m_blk_ptr)
-
-
-#define IX_MBUF_POOL_SIZE_ALIGN(size)   \
-		IX_OSAL_MBUF_POOL_SIZE_ALIGN(size)
-
-
-#define IX_MBUF_POOL_MBUF_AREA_SIZE_ALIGNED(count)	\
-		IX_OSAL_MBUF_POOL_MBUF_AREA_SIZE_ALIGNED(count)
-
-
-#define IX_MBUF_POOL_DATA_AREA_SIZE_ALIGNED(count, size) \
-		IX_OSAL_MBUF_POOL_DATA_AREA_SIZE_ALIGNED(count, size)
-
-
-#define IX_MBUF_POOL_MBUF_AREA_ALLOC(count, memAreaSize) \
-		IX_OSAL_MBUF_POOL_MBUF_AREA_ALLOC(count, memAreaSize)
-
-
-#define IX_MBUF_POOL_DATA_AREA_ALLOC(count, size, memAreaSize) \
-		IX_OSAL_MBUF_POOL_DATA_AREA_ALLOC(count, size, memAreaSize)
-
-IX_STATUS
-ixOsalOsIxp400BackwardPoolInit (IX_OSAL_MBUF_POOL ** poolPtrPtr,
-				UINT32 count, UINT32 size, const char *name);
-
-
-/* This one needs extra steps*/
-#define IX_MBUF_POOL_INIT(poolPtr, count, size, name) \
-		ixOsalOsIxp400BackwardPoolInit( poolPtr, count,  size, name)
-
-
-#define IX_MBUF_POOL_INIT_NO_ALLOC(poolPtrPtr, bufPtr, dataPtr, count, size, name) \
-		(*poolPtrPtr = IX_OSAL_MBUF_NO_ALLOC_POOL_INIT(bufPtr, dataPtr, count, size, name))
-
-
-IX_STATUS
-ixOsalOsIxp400BackwardMbufPoolGet (IX_OSAL_MBUF_POOL * poolPtr,
-				   IX_OSAL_MBUF ** newBufPtrPtr);
-
-#define IX_MBUF_POOL_GET(poolPtr, bufPtrPtr) \
-		ixOsalOsIxp400BackwardMbufPoolGet(poolPtr, bufPtrPtr)
-
-
-#define IX_MBUF_POOL_PUT(bufPtr) \
-		IX_OSAL_MBUF_POOL_PUT(bufPtr)
-
-
-#define IX_MBUF_POOL_PUT_CHAIN(bufPtr) \
-		IX_OSAL_MBUF_POOL_PUT_CHAIN(bufPtr)
-
-
-#define IX_MBUF_POOL_SHOW(poolPtr) \
-		IX_OSAL_MBUF_POOL_SHOW(poolPtr)
-
-
-#define IX_MBUF_POOL_MDATA_RESET(bufPtr) \
-		IX_OSAL_MBUF_POOL_MDATA_RESET(bufPtr)
-
-#endif /* IX_OSAL_BACKWARD_BUFFER_MGT_H */
diff --git a/drivers/net/npe/include/IxOsalBackwardCacheMMU.h b/drivers/net/npe/include/IxOsalBackwardCacheMMU.h
deleted file mode 100644
index d9e20c0a55..0000000000
--- a/drivers/net/npe/include/IxOsalBackwardCacheMMU.h
+++ /dev/null
@@ -1,45 +0,0 @@
-/** 
- * This file is intended to provide backward 
- * compatibility for main osService/OSSL 
- * APIs. 
- *
- * It shall be phased out gradually and users
- * are strongly recommended to use IX_OSAL API.
- *
- * @par
- * IXP400 SW Release version 2.0
- * 
- * -- Copyright Notice --
- * 
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- * 
- * @par
- * SPDX-License-Identifier:	BSD-3-Clause
- * @par
- * -- End of Copyright Notice --
- */
-
-#ifndef IX_OSAL_BACKWARD_CACHE_MMU_H
-#define IX_OSAL_BACKWARD_CACHE_MMU_H
-
-#ifdef IX_OSAL_CACHED
-#define IX_ACC_CACHE_ENABLED
-#endif
-
-#define IX_XSCALE_CACHE_LINE_SIZE IX_OSAL_CACHE_LINE_SIZE
-
-#define IX_ACC_DRV_DMA_MALLOC(size) IX_OSAL_CACHE_DMA_MALLOC(size)
-
-#define IX_ACC_DRV_DMA_FREE(ptr,size) IX_OSAL_CACHE_DMA_FREE(ptr)
-
-#define IX_MMU_VIRTUAL_TO_PHYSICAL_TRANSLATION(addr) IX_OSAL_MMU_VIRT_TO_PHYS(addr)
-
-#define IX_MMU_PHYSICAL_TO_VIRTUAL_TRANSLATION(addr) IX_OSAL_MMU_PHYS_TO_VIRT(addr)
-
-#define IX_ACC_DATA_CACHE_INVALIDATE(addr,size) IX_OSAL_CACHE_INVALIDATE(addr, size)
-
-#define IX_ACC_DATA_CACHE_FLUSH(addr,size) IX_OSAL_CACHE_FLUSH(addr,size)
-
-#endif /* IX_OSAL_BACKWARD_CACHE_MMU_H */
diff --git a/drivers/net/npe/include/IxOsalBackwardMemMap.h b/drivers/net/npe/include/IxOsalBackwardMemMap.h
deleted file mode 100644
index 9b6cc72d9f..0000000000
--- a/drivers/net/npe/include/IxOsalBackwardMemMap.h
+++ /dev/null
@@ -1,117 +0,0 @@
-/** 
- * This file is intended to provide backward 
- * compatibility for main osService/OSSL 
- * APIs. 
- *
- * It shall be phased out gradually and users
- * are strongly recommended to use IX_OSAL API.
- *
- * @par
- * IXP400 SW Release version 2.0
- * 
- * -- Copyright Notice --
- * 
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- * 
- * @par
- * SPDX-License-Identifier:	BSD-3-Clause
- * @par
- * -- End of Copyright Notice --
- */
-
-
-#ifndef IX_OSAL_BACKWARD_MEM_MAP_H
-#define IX_OSAL_BACKWARD_MEM_MAP_H
-
-#include "IxOsal.h"
-
-#define IX_OSSERV_SWAP_LONG(wData) IX_OSAL_SWAP_LONG(wData)
-#define IX_OSSERV_SWAP_SHORT(sData) IX_OSAL_SWAP_SHORT(sData)
-
-#define IX_OSSERV_SWAP_SHORT_ADDRESS(sAddr) IX_OSAL_SWAP_SHORT_ADDRESS(sAddr)
-#define IX_OSSERV_SWAP_BYTE_ADDRESS(bAddr) IX_OSAL_SWAP_BYTE_ADDRESS(bAddr)
-
-#define IX_OSSERV_BE_XSTOBUSL(wData)  IX_OSAL_BE_XSTOBUSL(wData)
-#define IX_OSSERV_BE_XSTOBUSS(sData)  IX_OSAL_BE_XSTOBUSS(sData)
-#define IX_OSSERV_BE_XSTOBUSB(bData)  IX_OSAL_BE_XSTOBUSB(bData)
-#define IX_OSSERV_BE_BUSTOXSL(wData)  IX_OSAL_BE_BUSTOXSL(wData)
-#define IX_OSSERV_BE_BUSTOXSS(sData)  IX_OSAL_BE_BUSTOXSS(sData)
-#define IX_OSSERV_BE_BUSTOXSB(bData)  IX_OSAL_BE_BUSTOXSB(bData)
-
-#define IX_OSSERV_LE_AC_XSTOBUSL(wAddr) IX_OSAL_LE_AC_XSTOBUSL(wAddr)
-#define IX_OSSERV_LE_AC_XSTOBUSS(sAddr) IX_OSAL_LE_AC_XSTOBUSS(sAddr)
-#define IX_OSSERV_LE_AC_XSTOBUSB(bAddr) IX_OSAL_LE_AC_XSTOBUSB(bAddr)
-#define IX_OSSERV_LE_AC_BUSTOXSL(wAddr) IX_OSAL_LE_AC_BUSTOXSL(wAddr)
-#define IX_OSSERV_LE_AC_BUSTOXSS(sAddr) IX_OSAL_LE_AC_BUSTOXSS(sAddr)
-#define IX_OSSERV_LE_AC_BUSTOXSB(bAddr) IX_OSAL_LE_AC_BUSTOXSB(bAddr)
-
-#define IX_OSSERV_LE_DC_XSTOBUSL(wData) IX_OSAL_LE_DC_XSTOBUSL(wData)
-#define IX_OSSERV_LE_DC_XSTOBUSS(sData) IX_OSAL_LE_DC_XSTOBUSS(sData)
-#define IX_OSSERV_LE_DC_XSTOBUSB(bData) IX_OSAL_LE_DC_XSTOBUSB(bData)
-#define IX_OSSERV_LE_DC_BUSTOXSL(wData) IX_OSAL_LE_DC_BUSTOXSL(wData)
-#define IX_OSSERV_LE_DC_BUSTOXSS(sData) IX_OSAL_LE_DC_BUSTOXSS(sData)
-#define IX_OSSERV_LE_DC_BUSTOXSB(bData) IX_OSAL_LE_DC_BUSTOXSB(bData)
-
-#define IX_OSSERV_READ_LONG(wAddr)          IX_OSAL_READ_LONG(wAddr)
-#define IX_OSSERV_READ_SHORT(sAddr)         IX_OSAL_READ_SHORT(sAddr)
-#define IX_OSSERV_READ_BYTE(bAddr)          IX_OSAL_READ_BYTE(bAddr)
-#define IX_OSSERV_WRITE_LONG(wAddr, wData)  IX_OSAL_WRITE_LONG(wAddr, wData)
-#define IX_OSSERV_WRITE_SHORT(sAddr, sData) IX_OSAL_WRITE_SHORT(sAddr, sData)
-#define IX_OSSERV_WRITE_BYTE(bAddr, bData)  IX_OSAL_WRITE_BYTE(bAddr, bData)
-
-
-#define IX_OSSERV_READ_NPE_SHARED_LONG(wAddr)            IX_OSAL_READ_BE_SHARED_LONG(wAddr)
-#define IX_OSSERV_READ_NPE_SHARED_SHORT(sAddr)           IX_OSAL_READ_BE_SHARED_SHORT(sAddr)
-#define IX_OSSERV_WRITE_NPE_SHARED_LONG(wAddr, wData)    IX_OSAL_WRITE_BE_SHARED_LONG(wAddr, wData)
-#define IX_OSSERV_WRITE_NPE_SHARED_SHORT(sAddr, sData)   IX_OSAL_WRITE_BE_SHARED_SHORT(sAddr, sData)
-
-#define IX_OSSERV_SWAP_NPE_SHARED_LONG(wData)            IX_OSAL_SWAP_BE_SHARED_LONG(wData)
-#define IX_OSSERV_SWAP_NPE_SHARED_SHORT(sData)           IX_OSAL_SWAP_BE_SHARED_SHORT(sData)
-
-
-/* Map osServ address/size */
-#define IX_OSSERV_QMGR_MAP_SIZE			IX_OSAL_IXP400_QMGR_MAP_SIZE
-#define IX_OSSERV_EXP_REG_MAP_SIZE		IX_OSAL_IXP400_EXP_REG_MAP_SIZE
-#define IX_OSSERV_UART1_MAP_SIZE		IX_OSAL_IXP400_UART1_MAP_SIZE
-#define IX_OSSERV_UART2_MAP_SIZE		IX_OSAL_IXP400_UART2_MAP_SIZE
-#define IX_OSSERV_PMU_MAP_SIZE			IX_OSAL_IXP400_PMU_MAP_SIZE
-#define IX_OSSERV_OSTS_MAP_SIZE			IX_OSAL_IXP400_OSTS_MAP_SIZE
-#define IX_OSSERV_NPEA_MAP_SIZE			IX_OSAL_IXP400_NPEA_MAP_SIZE
-#define IX_OSSERV_NPEB_MAP_SIZE			IX_OSAL_IXP400_NPEB_MAP_SIZE
-#define IX_OSSERV_NPEC_MAP_SIZE			IX_OSAL_IXP400_NPEC_MAP_SIZE
-#define IX_OSSERV_ETHA_MAP_SIZE			IX_OSAL_IXP400_ETHA_MAP_SIZE
-#define IX_OSSERV_ETHB_MAP_SIZE			IX_OSAL_IXP400_ETHB_MAP_SIZE
-#define IX_OSSERV_USB_MAP_SIZE			IX_OSAL_IXP400_USB_MAP_SIZE
-#define IX_OSSERV_GPIO_MAP_SIZE			IX_OSAL_IXP400_GPIO_MAP_SIZE
-#define IX_OSSERV_EXP_BUS_MAP_SIZE		IX_OSAL_IXP400_EXP_BUS_MAP_SIZE
-#define IX_OSSERV_EXP_BUS_CS0_MAP_SIZE	IX_OSAL_IXP400_EXP_BUS_CS0_MAP_SIZE
-#define IX_OSSERV_EXP_BUS_CS1_MAP_SIZE	IX_OSAL_IXP400_EXP_BUS_CS1_MAP_SIZE
-#define IX_OSSERV_EXP_BUS_CS4_MAP_SIZE	IX_OSAL_IXP400_EXP_BUS_CS4_MAP_SIZE
-
-
-#define IX_OSSERV_GPIO_PHYS_BASE			IX_OSAL_IXP400_GPIO_PHYS_BASE
-#define IX_OSSERV_UART1_PHYS_BASE			IX_OSAL_IXP400_UART1_PHYS_BASE
-#define IX_OSSERV_UART2_PHYS_BASE			IX_OSAL_IXP400_UART2_PHYS_BASE
-#define IX_OSSERV_ETHA_PHYS_BASE			IX_OSAL_IXP400_ETHA_PHYS_BASE
-#define IX_OSSERV_ETHB_PHYS_BASE			IX_OSAL_IXP400_ETHB_PHYS_BASE
-#define IX_OSSERV_NPEA_PHYS_BASE			IX_OSAL_IXP400_NPEA_PHYS_BASE
-#define IX_OSSERV_NPEB_PHYS_BASE			IX_OSAL_IXP400_NPEB_PHYS_BASE
-#define IX_OSSERV_NPEC_PHYS_BASE			IX_OSAL_IXP400_NPEC_PHYS_BASE
-#define IX_OSSERV_PERIPHERAL_PHYS_BASE		IX_OSAL_IXP400_PERIPHERAL_PHYS_BASE
-#define IX_OSSERV_QMGR_PHYS_BASE			IX_OSAL_IXP400_QMGR_PHYS_BASE
-#define IX_OSSERV_OSTS_PHYS_BASE			IX_OSAL_IXP400_OSTS_PHYS_BASE
-#define IX_OSSERV_USB_PHYS_BASE				IX_OSAL_IXP400_USB_PHYS_BASE
-#define IX_OSSERV_EXP_BUS_PHYS_BASE			IX_OSAL_IXP400_EXP_BUS_PHYS_BASE
-#define IX_OSSERV_EXP_BUS_BOOT_PHYS_BASE	IX_OSAL_IXP400_EXP_BUS_BOOT_PHYS_BASE
-#define IX_OSSERV_EXP_BUS_CS0_PHYS_BASE		IX_OSAL_IXP400_EXP_BUS_CS0_PHYS_BASE
-#define IX_OSSERV_EXP_BUS_CS1_PHYS_BASE		IX_OSAL_IXP400_EXP_BUS_CS1_PHYS_BASE
-#define IX_OSSERV_EXP_BUS_CS4_PHYS_BASE		IX_OSAL_IXP400_EXP_BUS_CS4_PHYS_BASE
-#define IX_OSSERV_EXP_BUS_REGS_PHYS_BASE	IX_OSAL_IXP400_EXP_BUS_REGS_PHYS_BASE
-
-#define IX_OSSERV_MEM_MAP(physAddr, size)		IX_OSAL_MEM_MAP(physAddr, size)
-
-#define IX_OSSERV_MEM_UNMAP(virtAddr)			IX_OSAL_MEM_UNMAP(virtAddr)
-
-#endif /* IX_OSAL_BACKWARD_MEM_MAP_H */
diff --git a/drivers/net/npe/include/IxOsalBackwardOsServices.h b/drivers/net/npe/include/IxOsalBackwardOsServices.h
deleted file mode 100644
index 761779d885..0000000000
--- a/drivers/net/npe/include/IxOsalBackwardOsServices.h
+++ /dev/null
@@ -1,101 +0,0 @@
-/** 
- * This file is intended to provide backward 
- * compatibility for main osService/OSSL 
- * APIs. 
- *
- * It shall be phased out gradually and users
- * are strongly recommended to use IX_OSAL API.
- *
- * @par
- * IXP400 SW Release version 2.0
- * 
- * -- Copyright Notice --
- * 
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- * 
- * @par
- * SPDX-License-Identifier:	BSD-3-Clause
- * @par
- * -- End of Copyright Notice --
- */
-
-#ifndef IX_OSAL_BACKWARD_OSSERVICES_H
-#define IX_OSAL_BACKWARD_OSSERVICES_H
-
-#ifndef __vxworks
-typedef UINT32 IX_IRQ_STATUS;
-#else
-typedef int IX_IRQ_STATUS;
-#endif
-
-typedef IxOsalMutex IxMutex;
-
-typedef IxOsalFastMutex IxFastMutex;
-
-typedef IxOsalVoidFnVoidPtr IxVoidFnVoidPtr;
-
-typedef IxOsalVoidFnPtr IxVoidFnPtr;
-
-
-#define LOG_NONE 	IX_OSAL_LOG_LVL_NONE
-#define LOG_USER 	IX_OSAL_LOG_LVL_USER
-#define LOG_FATAL 	IX_OSAL_LOG_LVL_FATAL
-#define LOG_ERROR  	IX_OSAL_LOG_LVL_ERROR
-#define LOG_WARNING	IX_OSAL_LOG_LVL_WARNING
-#define LOG_MESSAGE	IX_OSAL_LOG_LVL_MESSAGE
-#define LOG_DEBUG1  IX_OSAL_LOG_LVL_DEBUG1
-#define LOG_DEBUG2	IX_OSAL_LOG_LVL_DEBUG2
-#define LOG_DEBUG3 	IX_OSAL_LOG_LVL_DEBUG3
-#ifndef __vxworks
-#define LOG_ALL 	IX_OSAL_LOG_LVL_ALL
-#endif
-
-PUBLIC IX_STATUS
-ixOsServIntBind (int level, void (*routine) (void *), void *parameter);
-
-PUBLIC IX_STATUS ixOsServIntUnbind (int level);
-
-
-PUBLIC int ixOsServIntLock (void);
-
-PUBLIC void ixOsServIntUnlock (int lockKey);
-
-
-PUBLIC int ixOsServIntLevelSet (int level);
-
-PUBLIC IX_STATUS ixOsServMutexInit (IxMutex * mutex);
-
-PUBLIC IX_STATUS ixOsServMutexLock (IxMutex * mutex);
-
-PUBLIC IX_STATUS ixOsServMutexUnlock (IxMutex * mutex);
-
-PUBLIC IX_STATUS ixOsServMutexDestroy (IxMutex * mutex);
-
-PUBLIC IX_STATUS ixOsServFastMutexInit (IxFastMutex * mutex);
-
-PUBLIC IX_STATUS ixOsServFastMutexTryLock (IxFastMutex * mutex);
-
-PUBLIC IX_STATUS ixOsServFastMutexUnlock (IxFastMutex * mutex);
-
-PUBLIC int
-ixOsServLog (int level, char *format, int arg1, int arg2, int arg3, int arg4,
-	     int arg5, int arg6);
-
-
-PUBLIC int ixOsServLogLevelSet (int level);
-
-PUBLIC void ixOsServSleep (int microseconds);
-
-PUBLIC void ixOsServTaskSleep (int milliseconds);
-
-PUBLIC unsigned int ixOsServTimestampGet (void);
-
-
-PUBLIC void ixOsServUnload (void);
-
-PUBLIC void ixOsServYield (void);
-
-#endif
-/* IX_OSAL_BACKWARD_OSSERVICES_H */
diff --git a/drivers/net/npe/include/IxOsalBackwardOssl.h b/drivers/net/npe/include/IxOsalBackwardOssl.h
deleted file mode 100644
index c9deb544ce..0000000000
--- a/drivers/net/npe/include/IxOsalBackwardOssl.h
+++ /dev/null
@@ -1,248 +0,0 @@
-/** 
- * This file is intended to provide backward 
- * compatibility for main osService/OSSL 
- * APIs. 
- *
- * It shall be phased out gradually and users
- * are strongly recommended to use IX_OSAL API.
- *
- * @par
- * IXP400 SW Release version 2.0
- * 
- * -- Copyright Notice --
- * 
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- * 
- * @par
- * SPDX-License-Identifier:	BSD-3-Clause
- * @par
- * -- End of Copyright Notice --
- */
-
-#ifndef IX_OSAL_BACKWARD_OSSL_H
-#define IX_OSAL_BACKWARD_OSSL_H
-
-
-typedef IxOsalThread ix_ossl_thread_t;
-
-typedef IxOsalSemaphore ix_ossl_sem_t;
-
-typedef IxOsalMutex ix_ossl_mutex_t;
-
-typedef IxOsalTimeval ix_ossl_time_t;
-
-
-/* Map sub-fields for ix_ossl_time_t */
-#define tv_sec secs
-#define tv_nec nsecs
-
-
-typedef IX_STATUS ix_error;
-
-typedef UINT32 ix_ossl_thread_priority;
-
-typedef UINT32 ix_uint32;
-
-
-#define IX_OSSL_ERROR_SUCCESS IX_SUCCESS
-
-#define IX_ERROR_SUCCESS IX_SUCCESS
-
-
-typedef enum
-{
-    IX_OSSL_SEM_UNAVAILABLE = 0,
-    IX_OSSL_SEM_AVAILABLE
-} ix_ossl_sem_state;
-
-
-typedef enum
-{
-    IX_OSSL_MUTEX_UNLOCK = 0,
-    IX_OSSL_MUTEX_LOCK
-} ix_ossl_mutex_state;
-
-
-typedef IxOsalVoidFnVoidPtr ix_ossl_thread_entry_point_t;
-
-
-#define	IX_OSSL_THREAD_PRI_HIGH 	90
-#define IX_OSSL_THREAD_PRI_MEDIUM 	160
-#define IX_OSSL_THREAD_PRI_LOW 		240
-
-
-#define IX_OSSL_WAIT_FOREVER    IX_OSAL_WAIT_FOREVER
-
-#define IX_OSSL_WAIT_NONE       IX_OSAL_WAIT_NONE
-
-#define BILLION  IX_OSAL_BILLION
-
-#define IX_OSSL_TIME_EQ(a,b)  IX_OSAL_TIME_EQ(a,b)
-
-#define IX_OSSL_TIME_GT(a,b)  IX_OSAL_TIME_GT(a,b)
-
-#define IX_OSSL_TIME_LT(a,b)  IX_OSAL_TIME_LT(a,b)
-
-#define IX_OSSL_TIME_ADD(a,b)  IX_OSAL_TIME_ADD(a,b)
-
-#define IX_OSSL_TIME_SUB(a,b)  IX_OSAL_TIME_SUB(a,b)
-
-
-/* a is tick, b is timeval */
-#define IX_OSSL_TIME_CONVERT_TO_TICK(a,b)  \
-		 (a) = IX_OSAL_TIMEVAL_TO_TICKS(b)
-
-
-
-
-PUBLIC IX_STATUS
-ixOsalOsIxp400BackwardOsslThreadCreate (IxOsalVoidFnVoidPtr entryPoint,
-					void *arg, IxOsalThread * ptrThread);
-
-#define ix_ossl_thread_create(entryPoint, arg, ptrTid) \
-		ixOsalOsIxp400BackwardOsslThreadCreate(entryPoint, arg, ptrTid)
-
-
-/* void ix_ossl_thread_exit(ix_error retError, void* retObj) */
-#define ix_ossl_thread_exit(retError, retObj)   \
-		ixOsalThreadExit()
-
-
-PUBLIC IX_STATUS ixOsalOsIxp400BackwardOsslThreadKill (IxOsalThread tid);
-
-/* ix_error ix_ossl_thread_kill(tid) */
-#define ix_ossl_thread_kill(tid) \
-		ixOsalOsIxp400BackwardOsslThreadKill(tid)
-
-
-PUBLIC IX_STATUS
-ixOsalOsIxp400BackwardOsslThreadSetPriority (IxOsalThread tid,
-					     UINT32 priority);
-
-
-/* 
- * ix_error ix_ossl_thread_set_priority(ix_ossl_thread_t tid,
- *                             ix_ossl_thread_priority priority
- *                             ); 
- */
-
-#define ix_ossl_thread_set_priority(tid, priority) \
-		ixOsalOsIxp400BackwardOsslThreadSetPriority(tid, priority)
-
-
-PUBLIC IX_STATUS ixOsalOsIxp400BackwardOsslTickGet (int *pticks);
-
-#define ix_ossl_tick_get(pticks) \
-		ixOsalOsIxp400BackwardOsslTickGet(pticks)
-
-PUBLIC IX_STATUS ixOsalOsIxp400BackwardOsslThreadDelay (int ticks);
-
-#define ix_ossl_thread_delay(ticks) ixOsalOsIxp400BackwardOsslThreadDelay(ticks)
-
-
-
-/* ix_error ix_ossl_sem_init(int start_value, ix_ossl_sem_t* sid); */
-/* Note sid is a pointer to semaphore */
-#define ix_ossl_sem_init(value, sid) \
-		ixOsalSemaphoreInit(sid, value)
-
-
-PUBLIC IX_STATUS
-ixOsalOsIxp400BackwardOsslSemaphoreWait (IxOsalSemaphore semaphore,
-					 INT32 timeout);
-
-
-/*
-ix_error ix_ossl_sem_take(
-                          ix_ossl_sem_t sid,
-                          ix_uint32 timeout
-                         );
-*/
-
-#define ix_ossl_sem_take( sid, timeout) \
-		ixOsalOsIxp400BackwardOsslSemaphoreWait(sid, timeout)
-
-
-
-PUBLIC IX_STATUS
-ixOsalOsIxp400BackwardOsslSemaphorePost (IxOsalSemaphore sid);
-
-/*ix_error ix_ossl_sem_give(ix_ossl_sem_t sid); */
-#define ix_ossl_sem_give(sid) \
-		ixOsalOsIxp400BackwardOsslSemaphorePost(sid);
-
-
-PUBLIC IX_STATUS ixOsalOsIxp400BackwardSemaphoreDestroy (IxOsalSemaphore sid);
-
-#define ix_ossl_sem_fini(sid) \
-		ixOsalOsIxp400BackwardSemaphoreDestroy(sid)
-
-
-PUBLIC IX_STATUS
-ixOsalOsIxp400BackwardOsslMutexInit (ix_ossl_mutex_state start_state,
-				     IxOsalMutex * pMutex);
-
-
-/* ix_error ix_ossl_mutex_init(ix_ossl_mutex_state start_state, ix_ossl_mutex_t* mid); */
-#define ix_ossl_mutex_init(start_state, pMutex) \
-		ixOsalOsIxp400BackwardOsslMutexInit(start_state, pMutex)
-
-
-PUBLIC IX_STATUS
-ixOsalOsIxp400BackwardOsslMutexLock (IxOsalMutex mid, INT32 timeout);
-
-/*
-ix_error ix_ossl_mutex_lock(
-                            ix_ossl_mutex_t mid, 
-                            ix_uint32 timeout
-                           );
-*/
-#define ix_ossl_mutex_lock(mid, timeout) \
-		ixOsalOsIxp400BackwardOsslMutexLock(mid, timout)
-
-
-PUBLIC IX_STATUS ixOsalOsIxp400BackwardOsslMutexUnlock (IxOsalMutex mid);
-
-/* ix_error ix_ossl_mutex_unlock(ix_ossl_mutex_t mid); */
-#define ix_ossl_mutex_unlock(mid) \
-		ixOsalOsIxp400BackwardOsslMutexUnlock(mid)
-
-PUBLIC IX_STATUS ixOsalOsIxp400BackwardOsslMutexDestroy (IxOsalMutex mid);
-
-#define ix_ossl_mutex_fini(mid) \
-		ixOsalOsIxp400BackwardOsslMutexDestroy(mid);
-
-#define ix_ossl_sleep(sleeptime_ms) \
-		ixOsalSleep(sleeptime_ms)
-
-PUBLIC IX_STATUS ixOsalOsIxp400BackwardOsslSleepTick (UINT32 ticks);
-
-#define ix_ossl_sleep_tick(sleeptime_ticks) \
-		ixOsalOsIxp400BackwardOsslSleepTick(sleeptime_ticks)
-
-
-PUBLIC IX_STATUS ixOsalOsIxp400BackwardOsslTimeGet (IxOsalTimeval * pTv);
-
-#define ix_ossl_time_get(pTv)    \
-		ixOsalOsIxp400BackwardOsslTimeGet(pTv)
-
-
-typedef UINT32 ix_ossl_size_t;
-
-#define ix_ossl_malloc(arg_size) \
-		ixOsalMemAlloc(arg_size)
-
-#define ix_ossl_free(arg_pMemory) \
-		ixOsalMemFree(arg_pMemory)
-
-
-#define ix_ossl_memcpy(arg_pDest, arg_pSrc,arg_Count) \
-		ixOsalMemCopy(arg_pDest, arg_pSrc,arg_Count)
-
-#define ix_ossl_memset(arg_pDest, arg_pChar, arg_Count) \
-		ixOsalMemSet(arg_pDest, arg_pChar, arg_Count)
-
-
-#endif /* IX_OSAL_BACKWARD_OSSL_H */
diff --git a/drivers/net/npe/include/IxOsalBufferMgt.h b/drivers/net/npe/include/IxOsalBufferMgt.h
deleted file mode 100644
index 1f9e373cc7..0000000000
--- a/drivers/net/npe/include/IxOsalBufferMgt.h
+++ /dev/null
@@ -1,570 +0,0 @@
-/**
- * @file IxOsalBufferMgt.h
- *
- * @brief OSAL Buffer pool management and buffer management definitions.
- *
- * Design Notes:
- *
- * @par
- * IXP400 SW Release version 2.0
- * 
- * -- Copyright Notice --
- * 
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- * 
- * @par
- * SPDX-License-Identifier:	BSD-3-Clause
- * @par
- * -- End of Copyright Notice --
- */
-/* @par
- * -- Copyright Notice --
- *
- * @par
- * Copyright 1979, 1980, 1983, 1986, 1988, 1989, 1991, 1992, 1993, 1994 
- *      The Regents of the University of California. All rights reserved.
- * @par
- * -- End of Copyright Notice --
- */
-
-#ifndef IxOsalBufferMgt_H
-#define IxOsalBufferMgt_H
-
-#include "IxOsal.h"
-/**
- * @defgroup IxOsalBufferMgt OSAL Buffer Management Module.
- *
- * @brief Buffer management module for IxOsal
- *
- * @{ 
- */
-
-/**
- * @ingroup IxOsalBufferMgt
- *
- * @def IX_OSAL_MBUF_MAX_POOLS
- *
- * @brief The maximum number of pools that can be allocated, must be 
- *        a multiple of 32 as required by implementation logic.
- * @note  This can safely be increased if more pools are required.
- */
-#define IX_OSAL_MBUF_MAX_POOLS      32
-
-/**
- * @ingroup IxOsalBufferMgt
- *
- * @def IX_OSAL_MBUF_POOL_NAME_LEN
- *
- * @brief The maximum string length of the pool name
- */
-#define IX_OSAL_MBUF_POOL_NAME_LEN  64
-
-
-
-/**
- *  Define IX_OSAL_MBUF
- */
-
-
-/* forward declaration of internal structure */
-struct __IXP_BUF;
-
-/* 
- * OS can define it in IxOsalOs.h to skip the following
- * definition.
- */
-#ifndef IX_OSAL_ATTRIBUTE_ALIGN32
-#define IX_OSAL_ATTRIBUTE_ALIGN32 __attribute__ ((aligned(32)))
-#endif
-
-/* release v1.4 backward compatible definitions */
-struct __IX_MBUF
-{
-    struct __IXP_BUF *ix_next IX_OSAL_ATTRIBUTE_ALIGN32;
-    struct __IXP_BUF *ix_nextPacket;
-    UINT8 *ix_data;
-    UINT32 ix_len;  
-    unsigned char ix_type;
-    unsigned char ix_flags;
-    unsigned short ix_reserved;
-    UINT32 ix_rsvd;
-    UINT32 ix_PktLen; 
-    void *ix_priv;     
-};
-
-struct __IX_CTRL
-{
-    UINT32 ix_reserved[2];        /**< Reserved field */
-    UINT32 ix_signature;          /**< Field to indicate if buffers are allocated by the system */    
-    UINT32 ix_allocated_len;      /**< Allocated buffer length */  
-    UINT32 ix_allocated_data;     /**< Allocated buffer data pointer */  
-    void *ix_pool;                /**< pointer to the buffer pool */
-    struct __IXP_BUF *ix_chain;   /**< chaining */ 
-    void *ix_osbuf_ptr;           /**< Storage for OS-specific buffer pointer */
-};
-
-struct __IX_NE_SHARED
-{
-    UINT32 reserved[8] IX_OSAL_ATTRIBUTE_ALIGN32;   /**< Reserved area for NPE Service-specific usage */
-};
-
-
-/* 
- * IXP buffer structure 
- */
-typedef struct __IXP_BUF
-{
-    struct __IX_MBUF ix_mbuf IX_OSAL_ATTRIBUTE_ALIGN32; /**< buffer header */
-    struct __IX_CTRL ix_ctrl;                           /**< buffer management */
-    struct __IX_NE_SHARED ix_ne;                        /**< Reserved area for NPE Service-specific usage*/
-} IXP_BUF;
-
-
-
-/**
- * @ingroup IxOsalBufferMgt
- *
- * @def typedef IX_OSAL_MBUF
- *
- * @brief Generic IXP mbuf format.
- */
-typedef IXP_BUF IX_OSAL_MBUF;
-
-
-/**
- * @ingroup IxOsalBufferMgt
- *
- * @def IX_OSAL_IXP_NEXT_BUFFER_IN_PKT_PTR(m_blk_ptr)
- *
- * @brief Return pointer to the next mbuf in a single packet
- */
-#define IX_OSAL_MBUF_NEXT_BUFFER_IN_PKT_PTR(m_blk_ptr)  \
-        (m_blk_ptr)->ix_mbuf.ix_next
-
-
-/**
- * @ingroup IxOsalBufferMgt
- *
- * @def IX_OSAL_MBUF_NEXT_PKT_IN_CHAIN_PTR(m_blk_ptr)
- *
- * @brief Return pointer to the next packet in the chain
- */
-#define IX_OSAL_MBUF_NEXT_PKT_IN_CHAIN_PTR(m_blk_ptr)  \
-        (m_blk_ptr)->ix_mbuf.ix_nextPacket
-
-
-/**
- * @ingroup IxOsalBufferMgt
- *
- * @def IX_OSAL_MBUF_MDATA(m_blk_ptr)
- *
- * @brief Return pointer to the data in the mbuf
- */
-#define IX_OSAL_MBUF_MDATA(m_blk_ptr)       (m_blk_ptr)->ix_mbuf.ix_data
-
-/**
- * @ingroup IxOsalBufferMgt
- *
- * @def IX_OSAL_MBUF_MLEN(m_blk_ptr)
- *
- * @brief Return the data length
- */
-#define IX_OSAL_MBUF_MLEN(m_blk_ptr) \
-    (m_blk_ptr)->ix_mbuf.ix_len
-
-/**
- * @ingroup IxOsalBufferMgt
- *
- * @def IX_OSAL_MBUF_MTYPE(m_blk_ptr)
- *
- * @brief Return the data type in the mbuf
- */
-#define IX_OSAL_MBUF_MTYPE(m_blk_ptr) \
-    (m_blk_ptr)->ix_mbuf.ix_type
-
-
-/**
- * @ingroup IxOsalBufferMgt
- *
- * @def IX_OSAL_MBUF_FLAGS(m_blk_ptr)
- *
- * @brief Return the buffer flags
- */
-#define IX_OSAL_MBUF_FLAGS(m_blk_ptr)       \
-        (m_blk_ptr)->ix_mbuf.ix_flags
-
-
-/**
- * @ingroup IxOsalBufferMgt
- *
- * @def IX_OSAL_MBUF_NET_POOL(m_blk_ptr)
- *
- * @brief Return pointer to a network pool
- */
-#define IX_OSAL_MBUF_NET_POOL(m_blk_ptr)	\
-        (m_blk_ptr)->ix_ctrl.ix_pool
-
-
-
-/**
- * @ingroup IxOsalBufferMgt
- *
- * @def IX_OSAL_MBUF_PKT_LEN(m_blk_ptr)
- *
- * @brief Return the total length of all the data in
- * the mbuf chain for this packet
- */
-#define IX_OSAL_MBUF_PKT_LEN(m_blk_ptr) \
-        (m_blk_ptr)->ix_mbuf.ix_PktLen
-
-
-
-
-/**
- * @ingroup IxOsalBufferMgt
- *
- * @def IX_OSAL_MBUF_PRIV(m_blk_ptr)
- *
- * @brief Return the private field
- */
-#define IX_OSAL_MBUF_PRIV(m_blk_ptr)        \
-        (m_blk_ptr)->ix_mbuf.ix_priv
-
-
-
-/**
- * @ingroup IxOsalBufferMgt
- *
- * @def IX_OSAL_MBUF_SIGNATURE(m_blk_ptr)
- *
- * @brief Return the signature field of IX_OSAL_MBUF
- */
-#define IX_OSAL_MBUF_SIGNATURE(m_blk_ptr)  \
-        (m_blk_ptr)->ix_ctrl.ix_signature
-
-
-/**
- * @ingroup IxOsalBufferMgt
- *
- * @def IX_OSAL_MBUF_OSBUF_PTR(m_blk_ptr)
- *
- * @brief Return ix_osbuf_ptr field of IX_OSAL_MBUF, which is used to store OS-specific buffer pointer during a buffer conversion.
- */
-#define IX_OSAL_MBUF_OSBUF_PTR(m_blk_ptr)  \
-        (m_blk_ptr)->ix_ctrl.ix_osbuf_ptr
-
-
-/**
- * @ingroup IxOsalBufferMgt
- *
- * @def IX_OSAL_MBUF_ALLOCATED_BUFF_LEN(m_blk_ptr)
- *
- * @brief Return the allocated buffer size
- */
-#define IX_OSAL_MBUF_ALLOCATED_BUFF_LEN(m_blk_ptr)  \
-        (m_blk_ptr)->ix_ctrl.ix_allocated_len
-
-/**
- * @ingroup IxOsalBufferMgt
- *
- * @def IX_OSAL_MBUF_ALLOCATED_BUFF_DATA(m_blk_ptr)
- *
- * @brief Return the allocated buffer pointer
- */
-#define IX_OSAL_MBUF_ALLOCATED_BUFF_DATA(m_blk_ptr)  \
-        (m_blk_ptr)->ix_ctrl.ix_allocated_data
-
-
-
-/* Name length */
-#define IX_OSAL_MBUF_POOL_NAME_LEN  64
-
-
-/****************************************************
- * Macros for buffer pool management
- ****************************************************/
-
-/**
- * @ingroup IxOsalBufferMgt
- *
- * @def IX_OSAL_MBUF_POOL_FREE_COUNT(m_pool_ptr
- *
- * @brief Return the total number of freed buffers left in the pool.
- */
-#define IX_OSAL_MBUF_POOL_FREE_COUNT(m_pool_ptr) \
-                    ixOsalBuffPoolFreeCountGet(m_pool_ptr)
-
-/**
- * @ingroup IxOsalBufferMgt
- *
- * @def IX_OSAL_MBUF_POOL_SIZE_ALIGN
- *
- * @brief This macro takes an integer as an argument and
- * rounds it up to be a multiple of the memory cache-line 
- * size.
- *
- * @param int [in] size - the size integer to be rounded up
- *
- * @return int - the size, rounded up to a multiple of
- *               the cache-line size
- */
-#define IX_OSAL_MBUF_POOL_SIZE_ALIGN(size)                 \
-    ((((size) + (IX_OSAL_CACHE_LINE_SIZE - 1)) /      \
-        IX_OSAL_CACHE_LINE_SIZE) *                  \
-            IX_OSAL_CACHE_LINE_SIZE)
-
-/* Don't use this directly, use macro */
-PUBLIC UINT32 ixOsalBuffPoolMbufAreaSizeGet (int count);
-
-
-/**
- * @ingroup IxOsalBufferMgt
- *
- * @def IX_OSAL_MBUF_POOL_MBUF_AREA_SIZE_ALIGNED
- *
- * @brief This macro calculates, from the number of mbufs required, the 
- * size of the memory area required to contain the mbuf headers for the
- * buffers in the pool.  The size to be used for each mbuf header is 
- * rounded up to a multiple of the cache-line size, to ensure
- * each mbuf header aligns on a cache-line boundary.
- * This macro is used by IX_OSAL_MBUF_POOL_MBUF_AREA_ALLOC()
- *
- * @param int [in] count - the number of buffers the pool will contain
- *
- * @return int - the total size required for the pool mbuf area (aligned)
- */
-#define IX_OSAL_MBUF_POOL_MBUF_AREA_SIZE_ALIGNED(count) \
-        ixOsalBuffPoolMbufAreaSizeGet(count)
-
-
-/* Don't use this directly, use macro */
-PUBLIC UINT32 ixOsalBuffPoolDataAreaSizeGet (int count, int size);
-
-
-/**
- * @ingroup IxOsalBufferMgt
- *
- * @def IX_OSAL_MBUF_POOL_DATA_AREA_SIZE_ALIGNED
- *
- * @brief This macro calculates, from the number of mbufs required and the
- * size of the data portion for each mbuf, the size of the data memory area
- * required. The size is adjusted to ensure alignment on cache line boundaries.
- * This macro is used by IX_OSAL_MBUF_POOL_DATA_AREA_ALLOC()
- *
- *
- * @param int [in] count - The number of mbufs in the pool.
- * @param int [in] size  - The desired size for each mbuf data portion.
- *                         This size will be rounded up to a multiple of the
- *                         cache-line size to ensure alignment on cache-line
- *                         boundaries for each data block.
- *
- * @return int - the total size required for the pool data area (aligned)
- */
-#define IX_OSAL_MBUF_POOL_DATA_AREA_SIZE_ALIGNED(count, size) \
-        ixOsalBuffPoolDataAreaSizeGet((count), (size))
-
-
-/**
- * @ingroup IxOsalBufferMgt
- *
- * @def IX_OSAL_MBUF_POOL_MBUF_AREA_ALLOC
- *
- * @brief Allocates the memory area needed for the number of mbuf headers
- * specified by <i>count</i>.
- * This macro ensures the mbuf headers align on cache line boundaries.
- * This macro evaluates to a pointer to the memory allocated.
- *
- * @param int [in] count - the number of mbufs the pool will contain
- * @param int [out] memAreaSize - the total amount of memory allocated
- *
- * @return void * - a pointer to the allocated memory area
- */
-#define IX_OSAL_MBUF_POOL_MBUF_AREA_ALLOC(count, memAreaSize) \
-    IX_OSAL_CACHE_DMA_MALLOC((memAreaSize =                 \
-        IX_OSAL_MBUF_POOL_MBUF_AREA_SIZE_ALIGNED(count)))
-
-/**
- * @ingroup IxOsalBufferMgt
- *
- * @def IX_OSAL_MBUF_POOL_DATA_AREA_ALLOC
- *
- * @brief Allocates the memory pool for the data portion of the pool mbufs.
- * The number of mbufs is specified by <i>count</i>.  The size of the data
- * portion of each mbuf is specified by <i>size</i>.
- * This macro ensures the mbufs are aligned on cache line boundaries
- * This macro evaluates to a pointer to the memory allocated.
- *
- * @param int [in] count - the number of mbufs the pool will contain
- * @param int [in] size - the desired size (in bytes) required for the data
- *                        portion of each mbuf.  Note that this size may be
- *                        rounded up to ensure alignment on cache-line
- *                        boundaries.
- * @param int [out] memAreaSize - the total amount of memory allocated
- *
- * @return void * - a pointer to the allocated memory area
- */
-#define IX_OSAL_MBUF_POOL_DATA_AREA_ALLOC(count, size, memAreaSize) \
-    IX_OSAL_CACHE_DMA_MALLOC((memAreaSize =                     \
-        IX_OSAL_MBUF_POOL_DATA_AREA_SIZE_ALIGNED(count,size)))
-
-
-
-/**
- * @ingroup IxOsalBufferMgt
- *
- * @def IX_OSAL_MBUF_POOL_INIT
- *
- * @brief Wrapper macro for ixOsalPoolInit() 
- * See function description below for details.
- */
-#define IX_OSAL_MBUF_POOL_INIT(count, size, name) \
-    ixOsalPoolInit((count), (size), (name))
-
-/**
- * @ingroup IxOsalBufferMgt
- *
- * @def IX_OSAL_MBUF_NO_ALLOC_POOL_INIT
- *
- * @return Pointer to the new pool or NULL if the initialization failed.
- *
- * @brief Wrapper macro for ixOsalNoAllocPoolInit() 
- * See function description below for details.
- * 
- */
-#define IX_OSAL_MBUF_NO_ALLOC_POOL_INIT(bufPtr, dataPtr, count, size, name) \
-    ixOsalNoAllocPoolInit( (bufPtr), (dataPtr), (count), (size), (name))
-
-/**
- * @ingroup IxOsalBufferMgt
- *
- * @def IX_OSAL_MBUF_POOL_GET
- *
- * @brief Wrapper macro for ixOsalMbufAlloc() 
- * See function description below for details.
- */
-#define IX_OSAL_MBUF_POOL_GET(poolPtr) \
-        ixOsalMbufAlloc(poolPtr)
-
-/**
- * @ingroup IxOsalBufferMgt
- *
- * @def IX_OSAL_MBUF_POOL_PUT
- *
- * @brief Wrapper macro for ixOsalMbufFree() 
- * See function description below for details.
- */
-#define IX_OSAL_MBUF_POOL_PUT(bufPtr) \
-    ixOsalMbufFree(bufPtr)
-
-/**
- * @ingroup IxOsalBufferMgt
- *
- * @def IX_OSAL_MBUF_POOL_PUT_CHAIN
- *
- * @brief Wrapper macro for ixOsalMbufChainFree() 
- * See function description below for details.
- */
-#define IX_OSAL_MBUF_POOL_PUT_CHAIN(bufPtr) \
-    ixOsalMbufChainFree(bufPtr)
-
-/**
- * @ingroup IxOsalBufferMgt
- *
- * @def IX_OSAL_MBUF_POOL_SHOW
- *
- * @brief Wrapper macro for ixOsalMbufPoolShow() 
- * See function description below for details.
- */
-#define IX_OSAL_MBUF_POOL_SHOW(poolPtr) \
-    ixOsalMbufPoolShow(poolPtr)
-
-/**
- * @ingroup IxOsalBufferMgt
- *
- * @def IX_OSAL_MBUF_POOL_MDATA_RESET
- *
- * @brief Wrapper macro for ixOsalMbufDataPtrReset() 
- * See function description below for details.
- */
-#define IX_OSAL_MBUF_POOL_MDATA_RESET(bufPtr) \
-    ixOsalMbufDataPtrReset(bufPtr)
-
-/**
- * @ingroup IxOsalBufferMgt
- *
- * @def IX_OSAL_MBUF_POOL_UNINIT
- *
- * @brief Wrapper macro for ixOsalBuffPoolUninit() 
- * See function description below for details.
- */
-#define IX_OSAL_MBUF_POOL_UNINIT(m_pool_ptr)  \
-        ixOsalBuffPoolUninit(m_pool_ptr)
-
-/* 
- * Include OS-specific bufferMgt definitions 
- */
-#include "IxOsalOsBufferMgt.h"
-
-
-/**
- * @ingroup IxOsalBufferMgt
- *
- * @def IX_OSAL_CONVERT_OSBUF_TO_IXPBUF( osBufPtr, ixpBufPtr)
- *
- * @brief Convert pre-allocated os-specific buffer format to OSAL IXP_BUF (IX_OSAL_MBUF) format. 
- * It is users' responsibility to provide pre-allocated and valid buffer pointers.
- * @param osBufPtr (in) - a pre-allocated os-specific buffer pointer.
- * @param ixpBufPtr (in)- a pre-allocated OSAL IXP_BUF pointer
- * @return None
- */
-#define IX_OSAL_CONVERT_OSBUF_TO_IXPBUF( osBufPtr, ixpBufPtr) \
-        IX_OSAL_OS_CONVERT_OSBUF_TO_IXPBUF( osBufPtr, ixpBufPtr)        
-
-
-/**
- * @ingroup IxOsalBufferMgt
- *
- * @def IX_OSAL_CONVERT_IXPBUF_TO_OSBUF( ixpBufPtr, osBufPtr)
- *
- * @brief Convert pre-allocated OSAL IXP_BUF (IX_OSAL_MBUF) format to os-specific buffer pointers.
- * @param ixpBufPtr (in) - OSAL IXP_BUF pointer
- * @param osBufPtr (out) - os-specific buffer pointer.
- * @return None
- */
-
-#define IX_OSAL_CONVERT_IXPBUF_TO_OSBUF( ixpBufPtr, osBufPtr)  \
-        IX_OSAL_OS_CONVERT_IXPBUF_TO_OSBUF( ixpBufPtr, osBufPtr)
-
-
-PUBLIC IX_OSAL_MBUF_POOL *ixOsalPoolInit (UINT32 count,
-                      UINT32 size, const char *name);
-
-PUBLIC IX_OSAL_MBUF_POOL *ixOsalNoAllocPoolInit (void *poolBufPtr,
-                         void *poolDataPtr,
-						 UINT32 count,
-						 UINT32 size,
-						 const char *name);
-
-PUBLIC IX_OSAL_MBUF *ixOsalMbufAlloc (IX_OSAL_MBUF_POOL * pool);
-
-PUBLIC IX_OSAL_MBUF *ixOsalMbufFree (IX_OSAL_MBUF * mbuf);
-
-PUBLIC void ixOsalMbufChainFree (IX_OSAL_MBUF * mbuf);
-
-PUBLIC void ixOsalMbufDataPtrReset (IX_OSAL_MBUF * mbuf);
-
-PUBLIC void ixOsalMbufPoolShow (IX_OSAL_MBUF_POOL * pool);
-
-PUBLIC IX_STATUS ixOsalBuffPoolUninit (IX_OSAL_MBUF_POOL * pool);
-
-PUBLIC UINT32 ixOsalBuffPoolFreeCountGet(IX_OSAL_MBUF_POOL * pool);
-
-
-/**
- * @} IxOsalBufferMgt
- */
-
-
-#endif /* IxOsalBufferMgt_H */
diff --git a/drivers/net/npe/include/IxOsalBufferMgtDefault.h b/drivers/net/npe/include/IxOsalBufferMgtDefault.h
deleted file mode 100644
index 376c4980cf..0000000000
--- a/drivers/net/npe/include/IxOsalBufferMgtDefault.h
+++ /dev/null
@@ -1,64 +0,0 @@
-/**
- * @file IxOsalBufferMgtDefault.h
- *
- * @brief Default buffer pool management and buffer management
- *        definitions.
- *
- * Design Notes:
- *
- * @par
- * IXP400 SW Release version 2.0
- * 
- * -- Copyright Notice --
- * 
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- * 
- * @par
- * SPDX-License-Identifier:	BSD-3-Clause
- * @par
- * -- End of Copyright Notice --
- */
-
-#ifndef IX_OSAL_BUFFER_MGT_DEFAULT_H
-#define IX_OSAL_BUFFER_MGT_DEFAULT_H
-
-/**
- * @enum IxMbufPoolAllocationType
- * @brief Used to indicate how the pool memory was allocated
- */
-
-typedef enum
-{
-    IX_OSAL_MBUF_POOL_TYPE_SYS_ALLOC = 0, /**< mbuf pool allocated by the system */
-    IX_OSAL_MBUF_POOL_TYPE_USER_ALLOC	 /**< mbuf pool allocated by the user */
-} IxOsalMbufPoolAllocationType;
-
-
-/**
- * @brief Implementation of buffer pool structure for use with non-VxWorks OS
- */
-
-typedef struct
-{
-    IX_OSAL_MBUF *nextFreeBuf;	/**< Pointer to the next free mbuf              */
-    void *mbufMemPtr;	   /**< Pointer to the mbuf memory area            */
-    void *dataMemPtr;	   /**< Pointer to the data memory area            */
-    int bufDataSize;	   /**< The size of the data portion of each mbuf  */
-    int totalBufsInPool;   /**< Total number of mbufs in the pool          */
-    int freeBufsInPool;	   /**< Number of free mbufs currently in the pool */
-    int mbufMemSize;	   /**< The size of the pool mbuf memory area      */
-    int dataMemSize;	   /**< The size of the pool data memory area      */
-    char name[IX_OSAL_MBUF_POOL_NAME_LEN + 1];	 /**< Descriptive name for pool */
-    IxOsalMbufPoolAllocationType poolAllocType;
-    unsigned int poolIdx;  /**< Pool Index */ 
-} IxOsalMbufPool;
-
-typedef IxOsalMbufPool IX_OSAL_MBUF_POOL;
-
-
-PUBLIC IX_STATUS ixOsalBuffPoolUninit (IX_OSAL_MBUF_POOL * pool);
-
-
-#endif /* IX_OSAL_BUFFER_MGT_DEFAULT_H */
diff --git a/drivers/net/npe/include/IxOsalConfig.h b/drivers/net/npe/include/IxOsalConfig.h
deleted file mode 100644
index 81449f19b3..0000000000
--- a/drivers/net/npe/include/IxOsalConfig.h
+++ /dev/null
@@ -1,52 +0,0 @@
-/**
- * @file  IxOsalConfig.h
- *
- * @brief OSAL Configuration header file
- * 
- * 
- * @par
- * IXP400 SW Release version 2.0
- * 
- * -- Copyright Notice --
- * 
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- * 
- * @par
- * SPDX-License-Identifier:	BSD-3-Clause
- * @par
- * -- End of Copyright Notice --
- */
-
-/* 
- * This file contains user-editable fields for modules inclusion.
- */
-#ifndef IxOsalConfig_H
-#define IxOsalConfig_H
-
-
-/*
- * Note: in the future these config options may
- * become build time decision. 
- */
-
-/* Choose cache */
-#define IX_OSAL_CACHED
-/* #define IX_OSAL_UNCACHED */
-
-
-/*
- * Select the module headers to include
- */
-#include "IxOsalIoMem.h"	/* I/O Memory Management module API */
-#include "IxOsalBufferMgt.h"	/* Buffer Management module API */
-
-/*
- * Select main platform header file to use
- */
-#include "IxOsalOem.h"
-
-
-
-#endif /* IxOsalConfig_H */
diff --git a/drivers/net/npe/include/IxOsalEndianess.h b/drivers/net/npe/include/IxOsalEndianess.h
deleted file mode 100644
index 01de2c5e52..0000000000
--- a/drivers/net/npe/include/IxOsalEndianess.h
+++ /dev/null
@@ -1,110 +0,0 @@
-/** 
- * @file IxOsalEndianess.h (Obsolete file) 
- * 
- * @brief Header file for determining system endianess and OS
- * 
- * @par
- * @version $Revision: 1.1
- * 
- * @par
- * IXP400 SW Release version 2.0
- * 
- * -- Copyright Notice --
- * 
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- * 
- * @par
- * SPDX-License-Identifier:	BSD-3-Clause
- * @par
- * -- End of Copyright Notice --
- */
-
-
-#ifndef IxOsalEndianess_H
-#define IxOsalEndianess_H
-
-#if defined (__vxworks) || defined (__linux)
-
-/* get ntohl/ntohs/htohl/htons macros and CPU definitions for VxWorks */
-/* #include <netinet/in.h>  */
-
-#elif defined (__wince)
-
-/* get ntohl/ntohs/htohl/htons macros definitions for WinCE */
-#include <Winsock2.h>
-
-#else
-
-#error Unknown OS, please add a section with the include file for htonl/htons/ntohl/ntohs
-
-#endif /* vxworks or linux or wince */
-
-/* Compiler specific endianness selector - WARNING this works only with arm gcc, use appropriate defines with diab */
-
-#ifndef __wince
-
-#if defined (__ARMEL__)
-
-#ifndef __LITTLE_ENDIAN
-
-#define __LITTLE_ENDIAN
-
-#endif /* _LITTLE_ENDIAN */
-
-#elif defined (__ARMEB__) || CPU == SIMSPARCSOLARIS
-
-#ifndef __BIG_ENDIAN
-
-#define __BIG_ENDIAN
-
-#endif /* __BIG_ENDIAN */
-
-#else
-
-#error Error, could not identify target endianness
-
-#endif /* endianness selector no WinCE OSes */
-
-#else /* ndef __wince */
-
-#define __LITTLE_ENDIAN
-
-#endif /* def __wince */
-
-
-/* OS mode selector */
-#if defined (__vxworks) && defined (__LITTLE_ENDIAN)
-
-#define IX_OSAL_VXWORKS_LE
-
-#elif defined (__vxworks) && defined (__BIG_ENDIAN)
-
-#define IX_OSAL_VXWORKS_BE
-
-#elif defined (__linux) && defined (__BIG_ENDIAN)
-
-#define IX_OSAL_LINUX_BE
-
-#elif defined (__linux) && defined (__LITTLE_ENDIAN)
-
-#define IX_OSAL_LINUX_LE
-
-#elif defined (BOOTLOADER_BLD) && defined (__LITTLE_ENDIAN)
-
-#define IX_OSAL_EBOOT_LE
-
-#elif defined (__wince) && defined (__LITTLE_ENDIAN)
-
-#define IX_OSAL_WINCE_LE
-
-#else
-
-#error Unknown OS/Endianess combination - only vxWorks BE LE, Linux BE LE, WinCE BE LE are supported
-
-#endif /* mode selector */
-
-
-
-#endif /* IxOsalEndianess_H */
diff --git a/drivers/net/npe/include/IxOsalIoMem.h b/drivers/net/npe/include/IxOsalIoMem.h
deleted file mode 100644
index 7cb9c18c99..0000000000
--- a/drivers/net/npe/include/IxOsalIoMem.h
+++ /dev/null
@@ -1,298 +0,0 @@
-/*
- * @file        IxOsalIoMem.h
- * @author	Intel Corporation
- * @date        25-08-2004
- *
- * @brief       description goes here
- */
-
-/**
- * @par
- * IXP400 SW Release version 2.0
- * 
- * -- Copyright Notice --
- * 
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- * 
- * @par
- * SPDX-License-Identifier:	BSD-3-Clause
- * @par
- * -- End of Copyright Notice --
- */
-
-#ifndef IxOsalIoMem_H
-#define IxOsalIoMem_H
-
-
-/*
- * Decide OS and Endianess, such as IX_OSAL_VXWORKS_LE.
- */
-#include "IxOsalEndianess.h"
-
-/**
- * @defgroup IxOsalIoMem Osal IoMem module
- *
- * @brief I/O memory and endianess support.
- *
- * @{ 
- */
-
-/* Low-level conversion macros - DO NOT USE UNLESS ABSOLUTELY NEEDED */
-#ifndef __wince
-
-
-/* 
- * Private function to swap word
- */
-#ifdef __XSCALE__
-static __inline__ UINT32
-ixOsalCoreWordSwap (UINT32 wordIn)
-{
-    /*
-     * Storage for the swapped word 
-     */
-    UINT32 wordOut;
-
-    /*
-     * wordIn = A, B, C, D 
-     */
-    __asm__ (" eor r1, %1, %1, ror #16;"	/* R1 =      A^C, B^D, C^A, D^B */
-	     " bic r1, r1, #0x00ff0000;"	/* R1 =      A^C, 0  , C^A, D^B */
-	     " mov %0, %1, ror #8;"	/* wordOut = D,   A,   B,   C   */
-	     " eor %0, %0, r1, lsr #8;"	/* wordOut = D,   C,   B,   A   */
-  : "=r" (wordOut): "r" (wordIn):"r1");
-
-    return wordOut;
-}
-
-#define IX_OSAL_SWAP_LONG(wData)          (ixOsalCoreWordSwap(wData))
-#else
-#define IX_OSAL_SWAP_LONG(wData)          ((wData >> 24) | (((wData >> 16) & 0xFF) << 8) | (((wData >> 8) & 0xFF) << 16) | ((wData & 0xFF) << 24))
-#endif
-
-#else /* ndef __wince */
-#define IX_OSAL_SWAP_LONG(wData)        ((((UINT32)wData << 24) | ((UINT32)wData >> 24)) | (((wData << 8) & 0xff0000) | ((wData >> 8) & 0xff00)))
-#endif /* ndef __wince */
-
-#define IX_OSAL_SWAP_SHORT(sData)         ((sData >> 8) | ((sData & 0xFF) << 8))
-#define IX_OSAL_SWAP_SHORT_ADDRESS(sAddr) ((sAddr) ^ 0x2)
-#define IX_OSAL_SWAP_BYTE_ADDRESS(bAddr)  ((bAddr) ^ 0x3)
-
-#define IX_OSAL_BE_XSTOBUSL(wData)  (wData)
-#define IX_OSAL_BE_XSTOBUSS(sData)  (sData)
-#define IX_OSAL_BE_XSTOBUSB(bData)  (bData)
-#define IX_OSAL_BE_BUSTOXSL(wData)  (wData)
-#define IX_OSAL_BE_BUSTOXSS(sData)  (sData)
-#define IX_OSAL_BE_BUSTOXSB(bData)  (bData)
-
-#define IX_OSAL_LE_AC_XSTOBUSL(wAddr) (wAddr)
-#define IX_OSAL_LE_AC_XSTOBUSS(sAddr) IX_OSAL_SWAP_SHORT_ADDRESS(sAddr)
-#define IX_OSAL_LE_AC_XSTOBUSB(bAddr) IX_OSAL_SWAP_BYTE_ADDRESS(bAddr)
-#define IX_OSAL_LE_AC_BUSTOXSL(wAddr) (wAddr)
-#define IX_OSAL_LE_AC_BUSTOXSS(sAddr) IX_OSAL_SWAP_SHORT_ADDRESS(sAddr)
-#define IX_OSAL_LE_AC_BUSTOXSB(bAddr) IX_OSAL_SWAP_BYTE_ADDRESS(bAddr)
-
-#define IX_OSAL_LE_DC_XSTOBUSL(wData) IX_OSAL_SWAP_LONG(wData)
-#define IX_OSAL_LE_DC_XSTOBUSS(sData) IX_OSAL_SWAP_SHORT(sData)
-#define IX_OSAL_LE_DC_XSTOBUSB(bData) (bData)
-#define IX_OSAL_LE_DC_BUSTOXSL(wData) IX_OSAL_SWAP_LONG(wData)
-#define IX_OSAL_LE_DC_BUSTOXSS(sData) IX_OSAL_SWAP_SHORT(sData)
-#define IX_OSAL_LE_DC_BUSTOXSB(bData) (bData)
-
-
-/*
- * Decide SDRAM mapping, then implement read/write
- */
-#include "IxOsalMemAccess.h"
-
-
-/**
- * @ingroup IxOsalIoMem
- * @enum IxOsalMapEntryType
- * @brief This is an emum for OSAL I/O mem map type. 
- */
-typedef enum
-{
-    IX_OSAL_STATIC_MAP = 0,	 /**<Set map entry type to static map */
-    IX_OSAL_DYNAMIC_MAP	     /**<Set map entry type to dynamic map */
-} IxOsalMapEntryType;
-
-
-/**
- * @ingroup IxOsalIoMem
- * @enum IxOsalMapEndianessType
- * @brief This is an emum for OSAL I/O mem Endianess and Coherency mode.
- */
-typedef enum
-{
-    IX_OSAL_BE = 0x1,      /**<Set map endian mode to Big Endian */
-    IX_OSAL_LE_AC = 0x2,   /**<Set map endian mode to Little Endian, Address Coherent */
-    IX_OSAL_LE_DC = 0x4,   /**<Set map endian mode to Little Endian, Data Coherent */
-    IX_OSAL_LE = 0x8       /**<Set map endian mode to Little Endian without specifying coherency mode */
-} IxOsalMapEndianessType;
-
-
-/**
- * @struct IxOsalMemoryMap 
- * @brief IxOsalMemoryMap structure
- */
-typedef struct _IxOsalMemoryMap
-{
-    IxOsalMapEntryType type;   /**< map type - IX_OSAL_STATIC_MAP or IX_OSAL_DYNAMIC_MAP */
-
-    UINT32 physicalAddress;    /**< physical address of the memory mapped I/O zone */
-
-    UINT32 size;               /**< size of the map */
-
-    UINT32 virtualAddress;     /**< virtual address of the zone; must be predefined
-                                    in the global memory map for static maps and has
-                                    to be NULL for dynamic maps (populated on allocation)
-								*/
-    /*
-     * pointer to a map function called to map a dynamic map; 
-     * will populate the virtualAddress field 
-     */
-    void (*mapFunction) (struct _IxOsalMemoryMap * map);   /**< pointer to a map function called to map a dynamic map */
-
-    /*
-     * pointer to a map function called to unmap a dynamic map; 
-     * will reset the virtualAddress field to NULL 
-     */
-    void (*unmapFunction) (struct _IxOsalMemoryMap * map); /**< pointer to a map function called to unmap a dynamic map */
-
-    /*
-     * reference count describing how many components share this map; 
-     * actual allocation/deallocation for dynamic maps is done only 
-     * between 0 <=> 1 transitions of the counter 
-     */
-    UINT32 refCount;   /**< reference count describing how many components share this map */
-
-    /*
-     * memory endian type for the map; can be a combination of IX_OSAL_BE (Big 
-     * Endian) and IX_OSAL_LE or IX_OSAL_LE_AC or IX_OSAL_LE_DC
-     * (Little Endian, Address Coherent or Data Coherent). Any combination is
-     * allowed provided it contains at most one LE flag - e.g.
-     * (IX_OSAL_BE), (IX_OSAL_LE_AC), (IX_OSAL_BE | IX_OSAL_LE_DC) are valid
-     * combinations while (IX_OSAL_BE | IX_OSAL_LE_DC | IX_OSAL_LE_AC) is not. 
-     */
-    IxOsalMapEndianessType mapEndianType; /**< memory endian type for the map */
-
-    char *name;      /**< user-friendly name */
-} IxOsalMemoryMap;
-
-
-
-
-/* Internal function to map a memory zone
- * NOTE - This should not be called by the user.
- * Use the macro IX_OSAL_MEM_MAP instead
- */
-PUBLIC void *ixOsalIoMemMap (UINT32 requestedAddress,
-			     UINT32 size,
-			     IxOsalMapEndianessType requestedCoherency);
-
-
-/* Internal function to unmap a memory zone mapped with ixOsalIoMemMap
- * NOTE - This should not be called by the user.
- * Use the macro IX_OSAL_MEM_UNMAP instead
- */
-PUBLIC void ixOsalIoMemUnmap (UINT32 requestedAddress, UINT32 coherency);
-
-
-/* Internal function to convert virtual address to physical address 
- * NOTE - This should not be called by the user.
- * Use the macro IX_OSAL_MMAP_VIRT_TO_PHYS */
-PUBLIC UINT32 ixOsalIoMemVirtToPhys (UINT32 virtualAddress, UINT32 coherency);
-
-
-/* Internal function to convert physical address to virtual address 
- * NOTE - This should not be called by the user.
- * Use the macro IX_OSAL_MMAP_PHYS_TO_VIRT */
-PUBLIC UINT32
-ixOsalIoMemPhysToVirt (UINT32 physicalAddress, UINT32 coherency);
-
-/**
- * @ingroup IxOsalIoMem
- *
- * @def IX_OSAL_MEM_MAP(physAddr, size)
- *
- * @brief Map an I/O mapped physical memory zone to virtual zone and return virtual
- *        pointer.
- * @param  physAddr - the physical address
- * @param  size     - the size
- * @return start address of the virtual memory zone.
- *
- * @note  This function maps an I/O mapped physical memory zone of the given size
- * into a virtual memory zone accessible by the caller and returns a cookie - 
- * the start address of the virtual memory zone. 
- * IX_OSAL_MMAP_PHYS_TO_VIRT should NOT therefore be used on the returned 
- * virtual address.
- * The memory zone is to be unmapped using IX_OSAL_MEM_UNMAP once the caller has
- * finished using this zone (e.g. on driver unload) using the cookie as 
- * parameter.
- * The IX_OSAL_READ/WRITE_LONG/SHORT macros should be used to read and write 
- * the mapped memory, adding the necessary offsets to the address cookie.
- */
-#define IX_OSAL_MEM_MAP(physAddr, size) \
-    ixOsalIoMemMap((physAddr), (size), IX_OSAL_COMPONENT_MAPPING)
-
-
-/**
- * @ingroup IxOsalIoMem
- *
- * @def IX_OSAL_MEM_UNMAP(virtAddr)
- *
- * @brief Unmap a previously mapped I/O memory zone using virtual pointer obtained
- *        during the mapping operation.
- *        pointer.
- * @param  virtAddr - the virtual pointer to the zone to be unmapped.
- * @return none
- *
- * @note  This function unmaps a previously mapped I/O memory zone using
- * the cookie obtained in the mapping operation. The memory zone in question
- * becomes unavailable to the caller once unmapped and the cookie should be
- * discarded.
- *
- * This function cannot fail if the given parameter is correct and does not
- * return a value.
- */
-#define IX_OSAL_MEM_UNMAP(virtAddr) \
-    ixOsalIoMemUnmap ((virtAddr), IX_OSAL_COMPONENT_MAPPING)
-
-/**
- * @ingroup IxOsalIoMem
- *
- * @def IX_OSAL_MMAP_VIRT_TO_PHYS(virtAddr)
- *
- * @brief This function Converts a virtual address into a physical 
- * address, including the dynamically mapped memory.
- *
- * @param  virtAddr - virtual address to convert
- * Return value: corresponding physical address, or NULL
- */
-#define IX_OSAL_MMAP_VIRT_TO_PHYS(virtAddr) \
-    ixOsalIoMemVirtToPhys(virtAddr, IX_OSAL_COMPONENT_MAPPING)
-
-
-/**
- * @ingroup IxOsalIoMem
- *
- * @def IX_OSAL_MMAP_PHYS_TO_VIRT(physAddr)
- *
- * @brief  This function Converts a virtual address into a physical 
- * address, including the dynamically mapped memory.
- *
- * @param  physAddr - physical address to convert
- * Return value: corresponding virtual address, or NULL
- *
- */
-#define IX_OSAL_MMAP_PHYS_TO_VIRT(physAddr) \
-    ixOsalIoMemPhysToVirt(physAddr, IX_OSAL_COMPONENT_MAPPING)
-
-/**
- * @} IxOsalIoMem
- */
-
-#endif /* IxOsalIoMem_H */
diff --git a/drivers/net/npe/include/IxOsalMemAccess.h b/drivers/net/npe/include/IxOsalMemAccess.h
deleted file mode 100644
index be7472a2ea..0000000000
--- a/drivers/net/npe/include/IxOsalMemAccess.h
+++ /dev/null
@@ -1,470 +0,0 @@
-/** 
- * @file IxOsalMemAccess.h
- * 
- * @brief Header file for memory access
- * 
- * @par
- * @version $Revision: 1.0 $
- * 
- * @par
- * IXP400 SW Release version 2.0
- * 
- * -- Copyright Notice --
- * 
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- * 
- * @par
- * SPDX-License-Identifier:	BSD-3-Clause
- * @par
- * -- End of Copyright Notice --
- */
-
-#ifndef IxOsalMemAccess_H
-#define IxOsalMemAccess_H
-
-
-/* Global BE switch
- * 
- *  Should be set only in BE mode and only if the component uses I/O memory.
- */
-
-#if defined (__BIG_ENDIAN)
-
-#define IX_OSAL_BE_MAPPING
-
-#endif /* Global switch */
-
-
-/* By default only static memory maps in use;
-   define IX_OSAL_DYNAMIC_MEMORY_MAP per component if dynamic maps are
-   used instead in that component */
-#define IX_OSAL_STATIC_MEMORY_MAP
-
-
-/* 
- * SDRAM coherency mode
- * Must be defined to BE, LE_DATA_COHERENT or LE_ADDRESS_COHERENT.
- * The mode changes depending on OS 
- */
-#if defined (IX_OSAL_LINUX_BE) || defined (IX_OSAL_VXWORKS_BE)
-
-#define IX_SDRAM_BE
-
-#elif defined (IX_OSAL_VXWORKS_LE)
-
-#define IX_SDRAM_LE_DATA_COHERENT
-
-#elif defined (IX_OSAL_LINUX_LE)
-
-#define IX_SDRAM_LE_DATA_COHERENT
-
-#elif defined (IX_OSAL_WINCE_LE)
-
-#define IX_SDRAM_LE_DATA_COHERENT
-
-#elif defined (IX_OSAL_EBOOT_LE)
-
-#define IX_SDRAM_LE_ADDRESS_COHERENT
-
-#endif
-
-
-
-
-/**************************************
- * Retrieve current component mapping *
- **************************************/
-
-/*
- * Only use customized mapping for LE. 
- * 
- */
-#if defined (IX_OSAL_VXWORKS_LE) || defined (IX_OSAL_LINUX_LE) || defined (IX_OSAL_WINCE_LE) || defined (IX_OSAL_EBOOT_LE)
-
-#include "IxOsalOsIxp400CustomizedMapping.h"
-
-#endif
-
-
-/*******************************************************************
- * Turn off IX_STATIC_MEMORY map for components using dynamic maps *
- *******************************************************************/
-#ifdef IX_OSAL_DYNAMIC_MEMORY_MAP
-
-#undef IX_OSAL_STATIC_MEMORY_MAP
-
-#endif
-
-
-/************************************************************
- * Turn off BE access for components using LE or no mapping *
- ************************************************************/
-
-#if ( defined (IX_OSAL_LE_AC_MAPPING) || defined (IX_OSAL_LE_DC_MAPPING) || defined (IX_OSAL_NO_MAPPING) )
-
-#undef IX_OSAL_BE_MAPPING
-
-#endif
-
-
-/*****************
- * Safety checks *
- *****************/
-
-/* Default to no_mapping */
-#if !defined (IX_OSAL_BE_MAPPING) && !defined (IX_OSAL_LE_AC_MAPPING) && !defined (IX_OSAL_LE_DC_MAPPING) && !defined (IX_OSAL_NO_MAPPING)
-
-#define IX_OSAL_NO_MAPPING
-
-#endif /* check at least one mapping */
-
-/* No more than one mapping can be defined for a component */
-#if   (defined (IX_OSAL_BE_MAPPING)    && defined (IX_OSAL_LE_AC_MAPPING))  \
-    ||(defined (IX_OSAL_BE_MAPPING)    && defined (IX_OSAL_LE_DC_MAPPING))  \
-    ||(defined (IX_OSAL_BE_MAPPING)    && defined (IX_OSAL_NO_MAPPING))     \
-    ||(defined (IX_OSAL_LE_DC_MAPPING) && defined (IX_OSAL_NO_MAPPING))     \
-    ||(defined (IX_OSAL_LE_DC_MAPPING) && defined (IX_OSAL_LE_AC_MAPPING))	\
-    ||(defined (IX_OSAL_LE_AC_MAPPING) && defined (IX_OSAL_NO_MAPPING))
-
-
-#ifdef IX_OSAL_BE_MAPPING
-#warning IX_OSAL_BE_MAPPING is defined
-#endif
-
-#ifdef IX_OSAL_LE_AC_MAPPING
-#warning IX_OSAL_LE_AC_MAPPING is defined
-#endif
-
-#ifdef IX_OSAL_LE_DC_MAPPING
-#warning IX_OSAL_LE_DC_MAPPING is defined
-#endif
-
-#ifdef IX_OSAL_NO_MAPPING
-#warning IX_OSAL_NO_MAPPING is defined
-#endif
-
-#error More than one I/O mapping is defined, please check your component mapping
-
-#endif /* check at most one mapping */
-
-
-/* Now set IX_OSAL_COMPONENT_MAPPING */
-
-#ifdef IX_OSAL_BE_MAPPING
-#define IX_OSAL_COMPONENT_MAPPING IX_OSAL_BE
-#endif
-
-#ifdef IX_OSAL_LE_AC_MAPPING
-#define IX_OSAL_COMPONENT_MAPPING IX_OSAL_LE_AC
-#endif
-
-#ifdef IX_OSAL_LE_DC_MAPPING
-#define IX_OSAL_COMPONENT_MAPPING IX_OSAL_LE_DC
-#endif
-
-#ifdef IX_OSAL_NO_MAPPING
-#define IX_OSAL_COMPONENT_MAPPING IX_OSAL_LE
-#endif
-
-
-/* SDRAM coherency should be defined */
-#if !defined (IX_SDRAM_BE) && !defined (IX_SDRAM_LE_DATA_COHERENT) && !defined (IX_SDRAM_LE_ADDRESS_COHERENT)
-
-#error SDRAM coherency must be defined
-
-#endif /* SDRAM coherency must be defined */
-
-/* SDRAM coherency cannot be defined in several ways */
-#if (defined (IX_SDRAM_BE) && (defined (IX_SDRAM_LE_DATA_COHERENT) || defined (IX_SDRAM_LE_ADDRESS_COHERENT))) \
-    || (defined (IX_SDRAM_LE_DATA_COHERENT) && (defined (IX_SDRAM_BE) || defined (IX_SDRAM_LE_ADDRESS_COHERENT))) \
-    || (defined (IX_SDRAM_LE_ADDRESS_COHERENT) && (defined (IX_SDRAM_BE) || defined (IX_SDRAM_LE_DATA_COHERENT)))
-
-#error SDRAM coherency cannot be defined in more than one way
-
-#endif /* SDRAM coherency must be defined exactly once */
-
-
-/*********************
- * Read/write macros *
- *********************/
-
-/* WARNING - except for addition of special cookie read/write macros (see below)
-             these macros are NOT user serviceable. Please do not modify */
-
-#define IX_OSAL_READ_LONG_RAW(wAddr)          (*(wAddr))
-#define IX_OSAL_READ_SHORT_RAW(sAddr)         (*(sAddr))
-#define IX_OSAL_READ_BYTE_RAW(bAddr)          (*(bAddr))
-#define IX_OSAL_WRITE_LONG_RAW(wAddr, wData)  (*(wAddr) = (wData))
-#define IX_OSAL_WRITE_SHORT_RAW(sAddr,sData)  (*(sAddr) = (sData))
-#define IX_OSAL_WRITE_BYTE_RAW(bAddr, bData)  (*(bAddr) = (bData))
-
-#ifdef __linux
-
-/* Linux - specific cookie reads/writes. 
-  Redefine per OS if dynamic memory maps are used
-  and I/O memory is accessed via functions instead of raw pointer access. */
-
-#define IX_OSAL_READ_LONG_COOKIE(wCookie)           (readl((UINT32) (wCookie) ))
-#define IX_OSAL_READ_SHORT_COOKIE(sCookie)          (readw((UINT32) (sCookie) ))
-#define IX_OSAL_READ_BYTE_COOKIE(bCookie)           (readb((UINT32) (bCookie) ))
-#define IX_OSAL_WRITE_LONG_COOKIE(wCookie, wData)   (writel(wData, (UINT32) (wCookie) ))
-#define IX_OSAL_WRITE_SHORT_COOKIE(sCookie, sData)  (writew(sData, (UINT32) (sCookie) ))
-#define IX_OSAL_WRITE_BYTE_COOKIE(bCookie, bData)   (writeb(bData, (UINT32) (bCookie) ))
-
-#endif /* linux */
-
-#ifdef __wince
-
-/* WinCE - specific cookie reads/writes. */
-
-static __inline__ UINT32
-ixOsalWinCEReadLCookie (volatile UINT32 * lCookie)
-{
-    return *lCookie;
-}
-
-static __inline__ UINT16
-ixOsalWinCEReadWCookie (volatile UINT16 * wCookie)
-{
-#if 0
-    UINT32 auxVal = *((volatile UINT32 *) wCookie);
-    if ((unsigned) wCookie & 3)
-	return (UINT16) (auxVal >> 16);
-    else
-	return (UINT16) (auxVal & 0xffff);
-#else
-    return *wCookie;
-#endif
-}
-
-static __inline__ UINT8
-ixOsalWinCEReadBCookie (volatile UINT8 * bCookie)
-{
-#if 0
-    UINT32 auxVal = *((volatile UINT32 *) bCookie);
-    return (UINT8) ((auxVal >> (3 - (((unsigned) bCookie & 3) << 3)) & 0xff));
-#else
-    return *bCookie;
-#endif
-}
-
-static __inline__ void
-ixOsalWinCEWriteLCookie (volatile UINT32 * lCookie, UINT32 lVal)
-{
-    *lCookie = lVal;
-}
-
-static __inline__ void
-ixOsalWinCEWriteWCookie (volatile UINT16 * wCookie, UINT16 wVal)
-{
-#if 0
-    volatile UINT32 *auxCookie =
-	(volatile UINT32 *) ((unsigned) wCookie & ~3);
-    if ((unsigned) wCookie & 3)
-    {
-	*auxCookie &= 0xffff;
-	*auxCookie |= (UINT32) wVal << 16;
-    }
-    else
-    {
-	*auxCookie &= ~0xffff;
-	*auxCookie |= (UINT32) wVal & 0xffff;
-    }
-#else
-    *wCookie = wVal;
-#endif
-}
-
-static __inline__ void
-ixOsalWinCEWriteBCookie (volatile UINT8 * bCookie, UINT8 bVal)
-{
-#if 0
-    volatile UINT32 *auxCookie =
-	(volatile UINT32 *) ((unsigned) bCookie & ~3);
-    *auxCookie &= 0xff << (3 - (((unsigned) bCookie & 3) << 3));
-    *auxCookie |= (UINT32) bVal << (3 - (((unsigned) bCookie & 3) << 3));
-#else
-    *bCookie = bVal;
-#endif
-}
-
-
-#define IX_OSAL_READ_LONG_COOKIE(wCookie)           (ixOsalWinCEReadLCookie(wCookie))
-#define IX_OSAL_READ_SHORT_COOKIE(sCookie)          (ixOsalWinCEReadWCookie(sCookie))
-#define IX_OSAL_READ_BYTE_COOKIE(bCookie)           (ixOsalWinCEReadBCookie(bCookie))
-#define IX_OSAL_WRITE_LONG_COOKIE(wCookie, wData)   (ixOsalWinCEWriteLCookie(wCookie, wData))
-#define IX_OSAL_WRITE_SHORT_COOKIE(sCookie, sData)  (ixOsalWinCEWriteWCookie(sCookie, sData))
-#define IX_OSAL_WRITE_BYTE_COOKIE(bCookie, bData)   (ixOsalWinCEWriteBCookie(bCookie, bData))
-
-#endif /* wince */
-
-#if defined (__vxworks) || (defined (__linux) && defined (IX_OSAL_STATIC_MEMORY_MAP)) || \
-                           (defined (__wince) && defined (IX_OSAL_STATIC_MEMORY_MAP))
-
-#define IX_OSAL_READ_LONG_IO(wAddr)            IX_OSAL_READ_LONG_RAW(wAddr)
-#define IX_OSAL_READ_SHORT_IO(sAddr)           IX_OSAL_READ_SHORT_RAW(sAddr)
-#define IX_OSAL_READ_BYTE_IO(bAddr)            IX_OSAL_READ_BYTE_RAW(bAddr)
-#define IX_OSAL_WRITE_LONG_IO(wAddr, wData)    IX_OSAL_WRITE_LONG_RAW(wAddr, wData)
-#define IX_OSAL_WRITE_SHORT_IO(sAddr, sData)   IX_OSAL_WRITE_SHORT_RAW(sAddr, sData)
-#define IX_OSAL_WRITE_BYTE_IO(bAddr, bData)    IX_OSAL_WRITE_BYTE_RAW(bAddr, bData)
-
-#elif (defined (__linux) && !defined (IX_OSAL_STATIC_MEMORY_MAP)) || \
-      (defined (__wince) && !defined (IX_OSAL_STATIC_MEMORY_MAP))
-
-#ifndef __wince
-#include <asm/io.h>
-#endif /* ndef __wince */
-
-#define IX_OSAL_READ_LONG_IO(wAddr)            IX_OSAL_READ_LONG_COOKIE(wAddr)
-#define IX_OSAL_READ_SHORT_IO(sAddr)           IX_OSAL_READ_SHORT_COOKIE(sAddr)
-#define IX_OSAL_READ_BYTE_IO(bAddr)            IX_OSAL_READ_BYTE_COOKIE(bAddr)
-#define IX_OSAL_WRITE_LONG_IO(wAddr, wData)    IX_OSAL_WRITE_LONG_COOKIE(wAddr, wData)
-#define IX_OSAL_WRITE_SHORT_IO(sAddr, sData)   IX_OSAL_WRITE_SHORT_COOKIE(sAddr, sData)
-#define IX_OSAL_WRITE_BYTE_IO(bAddr, bData)    IX_OSAL_WRITE_BYTE_COOKIE(bAddr, bData)
-
-#endif
-
-/* Define BE macros */
-#define IX_OSAL_READ_LONG_BE(wAddr)          IX_OSAL_BE_BUSTOXSL(IX_OSAL_READ_LONG_IO((volatile UINT32 *) (wAddr) ))
-#define IX_OSAL_READ_SHORT_BE(sAddr)         IX_OSAL_BE_BUSTOXSS(IX_OSAL_READ_SHORT_IO((volatile UINT16 *) (sAddr) ))
-#define IX_OSAL_READ_BYTE_BE(bAddr)          IX_OSAL_BE_BUSTOXSB(IX_OSAL_READ_BYTE_IO((volatile UINT8 *) (bAddr) ))
-#define IX_OSAL_WRITE_LONG_BE(wAddr, wData)  IX_OSAL_WRITE_LONG_IO((volatile UINT32 *) (wAddr), IX_OSAL_BE_XSTOBUSL((UINT32) (wData) ))
-#define IX_OSAL_WRITE_SHORT_BE(sAddr, sData) IX_OSAL_WRITE_SHORT_IO((volatile UINT16 *) (sAddr), IX_OSAL_BE_XSTOBUSS((UINT16) (sData) ))
-#define IX_OSAL_WRITE_BYTE_BE(bAddr, bData)  IX_OSAL_WRITE_BYTE_IO((volatile UINT8 *) (bAddr), IX_OSAL_BE_XSTOBUSB((UINT8) (bData) ))
-
-/* Define LE AC macros */
-#define IX_OSAL_READ_LONG_LE_AC(wAddr)          IX_OSAL_READ_LONG_IO((volatile UINT32 *) IX_OSAL_LE_AC_BUSTOXSL((UINT32) (wAddr) ))
-#define IX_OSAL_READ_SHORT_LE_AC(sAddr)         IX_OSAL_READ_SHORT_IO((volatile UINT16 *) IX_OSAL_LE_AC_BUSTOXSS((UINT32) (sAddr) ))
-#define IX_OSAL_READ_BYTE_LE_AC(bAddr)          IX_OSAL_READ_BYTE_IO((volatile UINT8 *) IX_OSAL_LE_AC_BUSTOXSB((UINT32) (bAddr) ))
-#define IX_OSAL_WRITE_LONG_LE_AC(wAddr, wData)  IX_OSAL_WRITE_LONG_IO((volatile UINT32 *) IX_OSAL_LE_AC_XSTOBUSL((UINT32) (wAddr) ), (UINT32) (wData))
-#define IX_OSAL_WRITE_SHORT_LE_AC(sAddr, sData) IX_OSAL_WRITE_SHORT_IO((volatile UINT16 *) IX_OSAL_LE_AC_XSTOBUSS((UINT32) (sAddr) ), (UINT16) (sData))
-#define IX_OSAL_WRITE_BYTE_LE_AC(bAddr, bData)  IX_OSAL_WRITE_BYTE_IO((volatile UINT8 *) IX_OSAL_LE_AC_XSTOBUSB((UINT32) (bAddr) ), (UINT8) (bData))
-
-
-/* Inline functions are required here to avoid reading the same I/O location 2 or 4 times for the byte swap */
-static __inline__ UINT32
-ixOsalDataCoherentLongReadSwap (volatile UINT32 * wAddr)
-{
-    UINT32 wData = IX_OSAL_READ_LONG_IO (wAddr);
-    return IX_OSAL_LE_DC_BUSTOXSL (wData);
-}
-
-static __inline__ UINT16
-ixOsalDataCoherentShortReadSwap (volatile UINT16 * sAddr)
-{
-    UINT16 sData = IX_OSAL_READ_SHORT_IO (sAddr);
-    return IX_OSAL_LE_DC_BUSTOXSS (sData);
-}
-
-static __inline__ void
-ixOsalDataCoherentLongWriteSwap (volatile UINT32 * wAddr, UINT32 wData)
-{
-    wData = IX_OSAL_LE_DC_XSTOBUSL (wData);
-    IX_OSAL_WRITE_LONG_IO (wAddr, wData);
-}
-
-static __inline__ void
-ixOsalDataCoherentShortWriteSwap (volatile UINT16 * sAddr, UINT16 sData)
-{
-    sData = IX_OSAL_LE_DC_XSTOBUSS (sData);
-    IX_OSAL_WRITE_SHORT_IO (sAddr, sData);
-}
-
-/* Define LE DC macros */
-
-#define IX_OSAL_READ_LONG_LE_DC(wAddr)          ixOsalDataCoherentLongReadSwap((volatile UINT32 *) (wAddr) )
-#define IX_OSAL_READ_SHORT_LE_DC(sAddr)         ixOsalDataCoherentShortReadSwap((volatile UINT16 *) (sAddr) )
-#define IX_OSAL_READ_BYTE_LE_DC(bAddr)          IX_OSAL_LE_DC_BUSTOXSB(IX_OSAL_READ_BYTE_IO((volatile UINT8 *) (bAddr) ))
-#define IX_OSAL_WRITE_LONG_LE_DC(wAddr, wData)  ixOsalDataCoherentLongWriteSwap((volatile UINT32 *) (wAddr), (UINT32) (wData))
-#define IX_OSAL_WRITE_SHORT_LE_DC(sAddr, sData) ixOsalDataCoherentShortWriteSwap((volatile UINT16 *) (sAddr), (UINT16) (sData))
-#define IX_OSAL_WRITE_BYTE_LE_DC(bAddr, bData)  IX_OSAL_WRITE_BYTE_IO((volatile UINT8 *) (bAddr), IX_OSAL_LE_DC_XSTOBUSB((UINT8) (bData)))
-
-#if defined (IX_OSAL_BE_MAPPING)
-
-#define IX_OSAL_READ_LONG(wAddr)            IX_OSAL_READ_LONG_BE(wAddr) 
-#define IX_OSAL_READ_SHORT(sAddr)	        IX_OSAL_READ_SHORT_BE(sAddr) 
-#define IX_OSAL_READ_BYTE(bAddr)	        IX_OSAL_READ_BYTE_BE(bAddr) 
-#define IX_OSAL_WRITE_LONG(wAddr, wData)	IX_OSAL_WRITE_LONG_BE(wAddr, wData)
-#define IX_OSAL_WRITE_SHORT(sAddr, sData)	IX_OSAL_WRITE_SHORT_BE(sAddr, sData)
-#define IX_OSAL_WRITE_BYTE(bAddr, bData)	IX_OSAL_WRITE_BYTE_BE(bAddr, bData)
-
-#elif defined (IX_OSAL_LE_AC_MAPPING)
-
-#define IX_OSAL_READ_LONG(wAddr)            IX_OSAL_READ_LONG_LE_AC(wAddr) 
-#define IX_OSAL_READ_SHORT(sAddr)	        IX_OSAL_READ_SHORT_LE_AC(sAddr) 
-#define IX_OSAL_READ_BYTE(bAddr)	        IX_OSAL_READ_BYTE_LE_AC(bAddr) 
-#define IX_OSAL_WRITE_LONG(wAddr, wData)	IX_OSAL_WRITE_LONG_LE_AC(wAddr, wData)
-#define IX_OSAL_WRITE_SHORT(sAddr, sData)	IX_OSAL_WRITE_SHORT_LE_AC(sAddr, sData)
-#define IX_OSAL_WRITE_BYTE(bAddr, bData)	IX_OSAL_WRITE_BYTE_LE_AC(bAddr, bData)
-
-#elif defined (IX_OSAL_LE_DC_MAPPING)
-
-#define IX_OSAL_READ_LONG(wAddr)            IX_OSAL_READ_LONG_LE_DC(wAddr) 
-#define IX_OSAL_READ_SHORT(sAddr)	        IX_OSAL_READ_SHORT_LE_DC(sAddr) 
-#define IX_OSAL_READ_BYTE(bAddr)	        IX_OSAL_READ_BYTE_LE_DC(bAddr) 
-#define IX_OSAL_WRITE_LONG(wAddr, wData)	IX_OSAL_WRITE_LONG_LE_DC(wAddr, wData)
-#define IX_OSAL_WRITE_SHORT(sAddr, sData)	IX_OSAL_WRITE_SHORT_LE_DC(sAddr, sData)
-#define IX_OSAL_WRITE_BYTE(bAddr, bData)	IX_OSAL_WRITE_BYTE_LE_DC(bAddr, bData)
-
-#endif   /* End of BE and LE coherency mode switch */
-
-
-/* Reads/writes to and from memory shared with NPEs - depends on the SDRAM coherency */
-
-#if defined (IX_SDRAM_BE)
-
-#define IX_OSAL_READ_BE_SHARED_LONG(wAddr)            IX_OSAL_READ_LONG_RAW(wAddr)
-#define IX_OSAL_READ_BE_SHARED_SHORT(sAddr)           IX_OSAL_READ_SHORT_RAW(sAddr)
-#define IX_OSAL_READ_BE_SHARED_BYTE(bAddr)            IX_OSAL_READ_BYTE_RAW(bAddr)
-
-#define IX_OSAL_WRITE_BE_SHARED_LONG(wAddr, wData)    IX_OSAL_WRITE_LONG_RAW(wAddr, wData)
-#define IX_OSAL_WRITE_BE_SHARED_SHORT(sAddr, sData)   IX_OSAL_WRITE_SHORT_RAW(sAddr, sData)
-#define IX_OSAL_WRITE_BE_SHARED_BYTE(bAddr, bData)    IX_OSAL_WRITE_BYTE_RAW(bAddr, bData)
-
-#define IX_OSAL_SWAP_BE_SHARED_LONG(wData)            (wData)
-#define IX_OSAL_SWAP_BE_SHARED_SHORT(sData)           (sData)
-#define IX_OSAL_SWAP_BE_SHARED_BYTE(bData)            (bData)
-
-#elif defined (IX_SDRAM_LE_ADDRESS_COHERENT)
-
-#define IX_OSAL_READ_BE_SHARED_LONG(wAddr)            IX_OSAL_READ_LONG_RAW(wAddr)
-#define IX_OSAL_READ_BE_SHARED_SHORT(sAddr)           IX_OSAL_READ_SHORT_RAW(IX_OSAL_SWAP_SHORT_ADDRESS(sAddr))
-#define IX_OSAL_READ_BE_SHARED_BYTE(bAddr)            IX_OSAL_READ_BYTE_RAW(IX_OSAL_SWAP_BYTE_ADDRESS(bAddr))
-
-#define IX_OSAL_WRITE_BE_SHARED_LONG(wAddr, wData)    IX_OSAL_WRITE_LONG_RAW(wAddr, wData)
-#define IX_OSAL_WRITE_BE_SHARED_SHORT(sAddr, sData)   IX_OSAL_WRITE_SHORT_RAW(IX_OSAL_SWAP_SHORT_ADDRESS(sAddr), sData)
-#define IX_OSAL_WRITE_BE_SHARED_BYTE(bAddr, bData)    IX_OSAL_WRITE_BYTE_RAW(IX_OSAL_SWAP_BYTE_ADDRESS(bAddr), bData)
-
-#define IX_OSAL_SWAP_BE_SHARED_LONG(wData)            (wData)
-#define IX_OSAL_SWAP_BE_SHARED_SHORT(sData)           (sData)
-#define IX_OSAL_SWAP_BE_SHARED_BYTE(bData)            (bData)
-
-#elif defined (IX_SDRAM_LE_DATA_COHERENT)
-
-#define IX_OSAL_READ_BE_SHARED_LONG(wAddr)            IX_OSAL_SWAP_LONG(IX_OSAL_READ_LONG_RAW(wAddr))
-#define IX_OSAL_READ_BE_SHARED_SHORT(sAddr)           IX_OSAL_SWAP_SHORT(IX_OSAL_READ_SHORT_RAW(sAddr))
-#define IX_OSAL_READ_BE_SHARED_BYTE(bAddr)            IX_OSAL_READ_BYTE_RAW(bAddr)
-
-#define IX_OSAL_WRITE_BE_SHARED_LONG(wAddr, wData)    IX_OSAL_WRITE_LONG_RAW(wAddr, IX_OSAL_SWAP_LONG(wData))
-#define IX_OSAL_WRITE_BE_SHARED_SHORT(sAddr, sData)   IX_OSAL_WRITE_SHORT_RAW(sAddr, IX_OSAL_SWAP_SHORT(sData))
-#define IX_OSAL_WRITE_BE_SHARED_BYTE(bAddr, bData)    IX_OSAL_WRITE_BYTE_RAW(bAddr, bData)
-
-#define IX_OSAL_SWAP_BE_SHARED_LONG(wData)            IX_OSAL_SWAP_LONG(wData)
-#define IX_OSAL_SWAP_BE_SHARED_SHORT(sData)           IX_OSAL_SWAP_SHORT(sData)
-
-#endif
-
-
-#define IX_OSAL_COPY_BE_SHARED_LONG_ARRAY(wDestAddr, wSrcAddr, wCount) \
-  { \
-    UINT32 i; \
-    \
-    for ( i = 0 ; i < wCount ; i++ ) \
-    { \
-      * (((UINT32 *) wDestAddr) + i) = IX_OSAL_READ_BE_SHARED_LONG(((UINT32 *) wSrcAddr) + i); \
-    }; \
-  };
-
-#endif /* IxOsalMemAccess_H */
diff --git a/drivers/net/npe/include/IxOsalOem.h b/drivers/net/npe/include/IxOsalOem.h
deleted file mode 100644
index a1f4d21c1b..0000000000
--- a/drivers/net/npe/include/IxOsalOem.h
+++ /dev/null
@@ -1,73 +0,0 @@
-/**
- * @file IxOsalIxpOem.h
- *
- * @brief this file contains platform-specific defines.
- * 
- * 
- * @par
- * IXP400 SW Release version 2.0
- * 
- * -- Copyright Notice --
- * 
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- * 
- * @par
- * SPDX-License-Identifier:	BSD-3-Clause
- * @par
- * -- End of Copyright Notice --
- */
-
-#ifndef IxOsalOem_H
-#define IxOsalOem_H
-
-#include "IxOsalTypes.h"
-
-/* OS-specific header for Platform package */
-#include "IxOsalOsIxp400.h"
-
-/*
- * Platform Name
- */
-#define IX_OSAL_PLATFORM_NAME ixp400
-
-/*
- * Cache line size
- */
-#define IX_OSAL_CACHE_LINE_SIZE (32)
-
-
-/* Platform-specific fastmutex implementation */
-PUBLIC IX_STATUS ixOsalOemFastMutexTryLock (IxOsalFastMutex * mutex);
-
-/* Platform-specific init (MemMap) */
-PUBLIC IX_STATUS
-ixOsalOemInit (void);
-
-/* Platform-specific unload (MemMap) */
-PUBLIC void
-ixOsalOemUnload (void);
-
-/* Default implementations */
-
-PUBLIC UINT32
-ixOsalIxp400SharedTimestampGet (void);
-
-
-UINT32
-ixOsalIxp400SharedTimestampRateGet (void);
-
-UINT32
-ixOsalIxp400SharedSysClockRateGet (void);
-
-void
-ixOsalIxp400SharedTimeGet (IxOsalTimeval * tv);
-
-
-INT32
-ixOsalIxp400SharedLog (UINT32 level, UINT32 device, char *format, 
-                       int arg1, int arg2, int arg3, int arg4, 
-                       int arg5, int arg6);
-
-#endif /* IxOsal_Oem_H */
diff --git a/drivers/net/npe/include/IxOsalOs.h b/drivers/net/npe/include/IxOsalOs.h
deleted file mode 100644
index 6c66613415..0000000000
--- a/drivers/net/npe/include/IxOsalOs.h
+++ /dev/null
@@ -1,30 +0,0 @@
-#ifndef IxOsalOs_H
-#define IxOsalOs_H
-
-#ifndef IX_OSAL_CACHED
-#error "Uncached memory not supported in linux environment"
-#endif
-
-static inline unsigned long __v2p(unsigned long v)
-{
-	if (v < 0x40000000)
-		return (v & 0xfffffff);
-	else
-		return v;
-}
-
-#define IX_OSAL_OS_MMU_VIRT_TO_PHYS(addr)        __v2p((u32)addr)
-#define IX_OSAL_OS_MMU_PHYS_TO_VIRT(addr)        (addr)
-
-/*
- * Data cache not enabled (hopefully)
- */
-#define IX_OSAL_OS_CACHE_INVALIDATE(addr, size)
-#define IX_OSAL_OS_CACHE_FLUSH(addr, size)
-#define HAL_DCACHE_INVALIDATE(addr, size)
-#define HAL_DCACHE_FLUSH(addr, size)
-
-#define __ixp42X			/* sr: U-Boot needs this define */
-
-#endif /* IxOsalOs_H */
-
diff --git a/drivers/net/npe/include/IxOsalOsAssert.h b/drivers/net/npe/include/IxOsalOsAssert.h
deleted file mode 100644
index e4c3e1f614..0000000000
--- a/drivers/net/npe/include/IxOsalOsAssert.h
+++ /dev/null
@@ -1,10 +0,0 @@
-#ifndef IxOsalOsAssert_H
-#define IxOsalOsAssert_H
-
-#define IX_OSAL_OS_ASSERT(c)    if(!(c)) \
-                                { \
-                                    ixOsalLog (IX_OSAL_LOG_LVL_ERROR, IX_OSAL_LOG_DEV_STDOUT, "Assertion failure \n", 0, 0, 0, 0, 0, 0);\
-                                    while(1); \
-                                }
-
-#endif /* IxOsalOsAssert_H */
diff --git a/drivers/net/npe/include/IxOsalOsBufferMgt.h b/drivers/net/npe/include/IxOsalOsBufferMgt.h
deleted file mode 100644
index 53b961673f..0000000000
--- a/drivers/net/npe/include/IxOsalOsBufferMgt.h
+++ /dev/null
@@ -1,72 +0,0 @@
-/**
- * @file IxOsalOsBufferMgt.h
- *
- * @brief vxworks-specific buffer management module definitions.
- *
- * Design Notes:
- *
- * @par
- * IXP400 SW Release version 2.0
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * SPDX-License-Identifier:	BSD-3-Clause
- * @par
- * -- End of Copyright Notice --
- */
-
-
-#ifndef IX_OSAL_OS_BUFFER_MGT_H
-#define IX_OSAL_OS_BUFFER_MGT_H
-
-/*
- * use the defaul bufferMgt provided by OSAL framework.
- */
-#define IX_OSAL_USE_DEFAULT_BUFFER_MGT
-
-#include "IxOsalBufferMgtDefault.h"
-
-#if 0  /* FIXME */
-/* Define os-specific buffer macros for subfields */
-#define IX_OSAL_OSBUF_MDATA(osBufPtr) IX_OSAL_MBUF_MDATA(osBufPtr)
-             ( ((M_BLK *) osBufPtr)->m_data )
-
-#define IX_OSAL_OSBUF_MLEN(osBufPtr) \
-             ( ((M_BLK *) osBufPtr)->m_len )
-
-#define IX_OSAL_OSBUF_PKT_LEN(osBufPtr) \
-             ( ((M_BLK *) osBufPtr)->m_pkthdr.len )
-
-#define IX_OSAL_OS_CONVERT_OSBUF_TO_IXPBUF( osBufPtr, ixpBufPtr) \
-        { \
-            IX_OSAL_MBUF_OSBUF_PTR( (IX_OSAL_MBUF *) ixpBufPtr) = (void *) osBufPtr; \
-            IX_OSAL_MBUF_MDATA((IX_OSAL_MBUF *) ixpBufPtr) =  IX_OSAL_OSBUF_MDATA(osBufPtr); \
-            IX_OSAL_MBUF_PKT_LEN((IX_OSAL_MBUF *) ixpBufPtr) = IX_OSAL_OSBUF_PKT_LEN(osBufPtr); \
-            IX_OSAL_MBUF_MLEN((IX_OSAL_MBUF *) ixpBufPtr) = IX_OSAL_OSBUF_MLEN(osBufPtr); \
-        }
-
-#define IX_OSAL_OS_CONVERT_IXPBUF_TO_OSBUF( ixpBufPtr, osBufPtr) \
-        { \
-            if (ixpBufPtr == NULL) \
-            { /* Do nothing */ } \
-            else \
-            { \
-                (M_BLK *) osBufPtr = (M_BLK *) IX_OSAL_MBUF_OSBUF_PTR((IX_OSAL_MBUF *) ixpBufPtr); \
-                if (osBufPtr == NULL) \
-                { /* Do nothing */ } \
-                else \
-                { \
-                    IX_OSAL_OSBUF_MLEN(osBufPtr) =IX_OSAL_MBUF_MLEN((IX_OSAL_MBUF *) ixpBufPtr); \
-                    IX_OSAL_OSBUF_PKT_LEN(osBufPtr) =IX_OSAL_MBUF_PKT_LEN((IX_OSAL_MBUF *) ixpBufPtr); \
-                } \
-            } \
-        }
-
-#endif /* FIXME */
-
-#endif /* #define IX_OSAL_OS_BUFFER_MGT_H */
diff --git a/drivers/net/npe/include/IxOsalOsIxp400.h b/drivers/net/npe/include/IxOsalOsIxp400.h
deleted file mode 100644
index 104c733e3b..0000000000
--- a/drivers/net/npe/include/IxOsalOsIxp400.h
+++ /dev/null
@@ -1,292 +0,0 @@
-/**
- * @file IxOsalOsIxp400.h
- *
- * @brief OS and platform specific definitions
- *
- * Design Notes:
- *
- * @par
- * IXP400 SW Release version 2.0
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * SPDX-License-Identifier:	BSD-3-Clause
- * @par
- * -- End of Copyright Notice --
- */
-
-#ifndef IxOsalOsIxp400_H
-#define IxOsalOsIxp400_H
-
-#define BIT(x) (1<<(x))
-
-#define IXP425_EthA_BASE	0xc8009000
-#define IXP425_EthB_BASE	0xc800a000
-
-#define IXP425_PSMA_BASE	0xc8006000
-#define IXP425_PSMB_BASE	0xc8007000
-#define IXP425_PSMC_BASE	0xc8008000
-
-#define IXP425_PERIPHERAL_BASE	0xc8000000
-
-#define IXP425_QMGR_BASE	0x60000000
-#define IXP425_OSTS		0xC8005000
-
-#define IXP425_INT_LVL_NPEA	0
-#define IXP425_INT_LVL_NPEB	1
-#define IXP425_INT_LVL_NPEC	2
-
-#define IXP425_INT_LVL_QM1	3
-#define IXP425_INT_LVL_QM2	4
-
-#define IXP425_EXPANSION_BUS_BASE1	0x50000000
-#define IXP425_EXPANSION_BUS_BASE2	0x50000000
-#define IXP425_EXPANSION_BUS_CS1_BASE	0x51000000
-
-#define IXP425_EXP_CONFIG_BASE		0xC4000000
-
-/* physical addresses to be used when requesting memory with IX_OSAL_MEM_MAP */
-#define IX_OSAL_IXP400_INTC_PHYS_BASE          IXP425_INTC_BASE
-#define IX_OSAL_IXP400_GPIO_PHYS_BASE          IXP425_GPIO_BASE
-#define IX_OSAL_IXP400_UART1_PHYS_BASE         IXP425_UART1_BASE
-#define IX_OSAL_IXP400_UART2_PHYS_BASE         IXP425_UART2_BASE
-#define IX_OSAL_IXP400_ETHA_PHYS_BASE          IXP425_EthA_BASE
-#define IX_OSAL_IXP400_ETHB_PHYS_BASE          IXP425_EthB_BASE
-#define IX_OSAL_IXP400_NPEA_PHYS_BASE          IXP425_NPEA_BASE
-#define IX_OSAL_IXP400_NPEB_PHYS_BASE          IXP425_NPEB_BASE
-#define IX_OSAL_IXP400_NPEC_PHYS_BASE          IXP425_NPEC_BASE
-#define IX_OSAL_IXP400_PERIPHERAL_PHYS_BASE    IXP425_PERIPHERAL_BASE
-#define IX_OSAL_IXP400_QMGR_PHYS_BASE          IXP425_QMGR_BASE
-#define IX_OSAL_IXP400_OSTS_PHYS_BASE          IXP425_TIMER_BASE
-#define IX_OSAL_IXP400_USB_PHYS_BASE           IXP425_USB_BASE
-#define IX_OSAL_IXP400_EXP_CFG_PHYS_BASE       IXP425_EXP_CFG_BASE
-#define IX_OSAL_IXP400_EXP_BUS_PHYS_BASE       IXP425_EXP_BUS_BASE2
-#define IX_OSAL_IXP400_EXP_BUS_BOOT_PHYS_BASE  IXP425_EXP_BUS_BASE1
-#define IX_OSAL_IXP400_EXP_BUS_CS0_PHYS_BASE   IXP425_EXP_BUS_CS0_BASE
-#define IX_OSAL_IXP400_EXP_BUS_CS1_PHYS_BASE   IXP425_EXP_BUS_CS1_BASE
-#define IX_OSAL_IXP400_EXP_BUS_CS4_PHYS_BASE   IXP425_EXP_BUS_CS4_BASE
-#define IX_OSAL_IXP400_EXP_BUS_REGS_PHYS_BASE  IXP425_EXP_CFG_BASE
-#define IX_OSAL_IXP400_PCI_CFG_PHYS_BASE       IXP425_PCI_CFG_BASE
-
-/* map sizes to be used when requesting memory with IX_OSAL_MEM_MAP */
-#define IX_OSAL_IXP400_QMGR_MAP_SIZE        (0x4000)	 /**< Queue Manager map size */
-#define IX_OSAL_IXP400_PERIPHERAL_MAP_SIZE  (0xC000)	 /**< Peripheral space map size */
-#define IX_OSAL_IXP400_UART1_MAP_SIZE       (0x1000)	 /**< UART1 map size */
-#define IX_OSAL_IXP400_UART2_MAP_SIZE       (0x1000)	 /**< UART2 map size */
-#define IX_OSAL_IXP400_PMU_MAP_SIZE         (0x1000)	 /**< PMU map size */
-#define IX_OSAL_IXP400_OSTS_MAP_SIZE        (0x1000)	 /**< OS Timers map size */
-#define IX_OSAL_IXP400_NPEA_MAP_SIZE        (0x1000)	 /**< NPE A map size */
-#define IX_OSAL_IXP400_NPEB_MAP_SIZE        (0x1000)	 /**< NPE B map size */
-#define IX_OSAL_IXP400_NPEC_MAP_SIZE        (0x1000)	 /**< NPE C map size */
-#define IX_OSAL_IXP400_ETHA_MAP_SIZE        (0x1000)	 /**< Eth A map size */
-#define IX_OSAL_IXP400_ETHB_MAP_SIZE        (0x1000)	 /**< Eth B map size */
-#define IX_OSAL_IXP400_USB_MAP_SIZE         (0x1000)	 /**< USB map size */
-#define IX_OSAL_IXP400_GPIO_MAP_SIZE        (0x1000)	 /**< GPIO map size */
-#define IX_OSAL_IXP400_EXP_REG_MAP_SIZE     (0x1000)	 /**< Exp Bus Config Registers map size */
-#define IX_OSAL_IXP400_EXP_BUS_MAP_SIZE     (0x08000000) /**< Expansion bus map size */
-#define IX_OSAL_IXP400_EXP_BUS_CS0_MAP_SIZE (0x01000000) /**< CS0 map size */
-#define IX_OSAL_IXP400_EXP_BUS_CS1_MAP_SIZE (0x01000000) /**< CS1 map size */
-#define IX_OSAL_IXP400_EXP_BUS_CS4_MAP_SIZE (0x01000000) /**< CS4 map size */
-#define IX_OSAL_IXP400_PCI_CFG_MAP_SIZE     (0x1000)	 /**< PCI Bus Config Registers map size */
-
-#define IX_OSAL_IXP400_EXP_FUSE             (IXP425_EXP_CONFIG_BASE + 0x28)
-#define IX_OSAL_IXP400_ETH_NPEA_PHYS_BASE   0xC800C000
-#define IX_OSAL_IXP400_ETH_NPEA_MAP_SIZE    0x1000
-
-/*
- * Interrupt Levels
- */
-#define IX_OSAL_IXP400_NPEA_IRQ_LVL		(0)
-#define IX_OSAL_IXP400_NPEB_IRQ_LVL		(1)
-#define IX_OSAL_IXP400_NPEC_IRQ_LVL		(2)
-#define IX_OSAL_IXP400_QM1_IRQ_LVL		(3)
-#define IX_OSAL_IXP400_QM2_IRQ_LVL		(4)
-#define IX_OSAL_IXP400_TIMER1_IRQ_LVL		(5)
-#define IX_OSAL_IXP400_GPIO0_IRQ_LVL		(6)
-#define IX_OSAL_IXP400_GPIO1_IRQ_LVL		(7)
-#define IX_OSAL_IXP400_PCI_INT_IRQ_LVL		(8)
-#define IX_OSAL_IXP400_PCI_DMA1_IRQ_LVL		(9)
-#define IX_OSAL_IXP400_PCI_DMA2_IRQ_LVL		(10)
-#define IX_OSAL_IXP400_TIMER2_IRQ_LVL		(11)
-#define IX_OSAL_IXP400_USB_IRQ_LVL		(12)
-#define IX_OSAL_IXP400_UART2_IRQ_LVL		(13)
-#define IX_OSAL_IXP400_TIMESTAMP_IRQ_LVL	(14)
-#define IX_OSAL_IXP400_UART1_IRQ_LVL		(15)
-#define IX_OSAL_IXP400_WDOG_IRQ_LVL		(16)
-#define IX_OSAL_IXP400_AHB_PMU_IRQ_LVL		(17)
-#define IX_OSAL_IXP400_XSCALE_PMU_IRQ_LVL	(18)
-#define IX_OSAL_IXP400_GPIO2_IRQ_LVL		(19)
-#define IX_OSAL_IXP400_GPIO3_IRQ_LVL		(20)
-#define IX_OSAL_IXP400_GPIO4_IRQ_LVL		(21)
-#define IX_OSAL_IXP400_GPIO5_IRQ_LVL		(22)
-#define IX_OSAL_IXP400_GPIO6_IRQ_LVL		(23)
-#define IX_OSAL_IXP400_GPIO7_IRQ_LVL		(24)
-#define IX_OSAL_IXP400_GPIO8_IRQ_LVL		(25)
-#define IX_OSAL_IXP400_GPIO9_IRQ_LVL		(26)
-#define IX_OSAL_IXP400_GPIO10_IRQ_LVL		(27)
-#define IX_OSAL_IXP400_GPIO11_IRQ_LVL		(28)
-#define IX_OSAL_IXP400_GPIO12_IRQ_LVL		(29)
-#define IX_OSAL_IXP400_SW_INT1_IRQ_LVL		(30)
-#define IX_OSAL_IXP400_SW_INT2_IRQ_LVL		(31)
-
-/* USB interrupt level mask */
-#define IX_OSAL_IXP400_INT_LVL_USB             IRQ_IXP425_USB
-
-/* USB IRQ */
-#define IX_OSAL_IXP400_USB_IRQ                 IRQ_IXP425_USB
-
-/*
- * OS name retrieval
- */
-#define IX_OSAL_OEM_OS_NAME_GET(name, limit) \
-ixOsalOsIxp400NameGet((INT8*)(name), (INT32) (limit))
-
-/*
- * OS version retrieval
- */
-#define IX_OSAL_OEM_OS_VERSION_GET(version, limit) \
-ixOsalOsIxp400VersionGet((INT8*)(version), (INT32) (limit))
-
-/*
- * Function to retrieve the OS name
- */
-PUBLIC IX_STATUS ixOsalOsIxp400NameGet(INT8* osName, INT32 maxSize);
-
-/*
- * Function to retrieve the OS version
- */
-PUBLIC IX_STATUS ixOsalOsIxp400VersionGet(INT8* osVersion, INT32 maxSize);
-
-/*
- * TimestampGet
- */
-PUBLIC UINT32 ixOsalOsIxp400TimestampGet (void);
-
-/*
- * Timestamp
- */
-#define IX_OSAL_OEM_TIMESTAMP_GET ixOsalOsIxp400TimestampGet
-
-
-/*
- * Timestamp resolution
- */
-PUBLIC UINT32 ixOsalOsIxp400TimestampResolutionGet (void);
-
-#define IX_OSAL_OEM_TIMESTAMP_RESOLUTION_GET ixOsalOsIxp400TimestampResolutionGet
-
-/*
- * Retrieves the system clock rate
- */
-PUBLIC UINT32 ixOsalOsIxp400SysClockRateGet (void);
-
-#define IX_OSAL_OEM_SYS_CLOCK_RATE_GET ixOsalOsIxp400SysClockRateGet
-
-/*
- * required by FS but is not really platform-specific.
- */
-#define IX_OSAL_OEM_TIME_GET(pTv) ixOsalTimeGet(pTv)
-
-
-
-/* linux map/unmap functions */
-PUBLIC void ixOsalLinuxMemMap (IxOsalMemoryMap * map);
-
-PUBLIC void ixOsalLinuxMemUnmap (IxOsalMemoryMap * map);
-
-
-/*********************
- *	Memory map
- ********************/
-
-/* Global memmap only visible to IO MEM module */
-
-#ifdef IxOsalIoMem_C
-
-IxOsalMemoryMap ixOsalGlobalMemoryMap[] = {
-     {
-     /* Global BE and LE_AC map */
-     IX_OSAL_STATIC_MAP,	/* type            */
-     0x00000000,		/* physicalAddress */
-     0x30000000,		/* size            */
-     0x00000000,		/* virtualAddress  */
-     NULL,			/* mapFunction     */
-     NULL,			/* unmapFunction   */
-     0,				/* refCount        */
-     IX_OSAL_BE | IX_OSAL_LE_AC,/* endianType      */
-     "global_low"		/* name            */
-     },
-
-    /* SDRAM LE_DC alias */
-    {
-     IX_OSAL_STATIC_MAP,	/* type            */
-     0x00000000,		/* physicalAddress */
-     0x10000000,		/* size            */
-     0x30000000,		/* virtualAddress  */
-     NULL,			/* mapFunction     */
-     NULL,			/* unmapFunction   */
-     0,				/* refCount        */
-     IX_OSAL_LE_DC,		/* endianType      */
-     "sdram_dc"			/* name            */
-     },
-
-    /* QMGR LE_DC alias */
-    {
-     IX_OSAL_STATIC_MAP,	/* type            */
-     0x60000000,		/* physicalAddress */
-     0x00100000,		/* size            */
-     0x60000000,		/* virtualAddress  */
-     NULL,			/* mapFunction     */
-     NULL,			/* unmapFunction   */
-     0,				/* refCount        */
-     IX_OSAL_LE_DC,		/* endianType      */
-     "qmgr_dc"			/* name            */
-     },
-
-    /* QMGR BE alias */
-    {
-     IX_OSAL_STATIC_MAP,	/* type            */
-     0x60000000,		/* physicalAddress */
-     0x00100000,		/* size            */
-     0x60000000,		/* virtualAddress  */
-     NULL,			/* mapFunction     */
-     NULL,			/* unmapFunction   */
-     0,				/* refCount        */
-     IX_OSAL_BE | IX_OSAL_LE_AC,/* endianType      */
-     "qmgr_be"			/* name            */
-     },
-
-    /* Global BE and LE_AC map */
-    {
-     IX_OSAL_STATIC_MAP,	/* type            */
-     0x40000000,		/* physicalAddress */
-     0x20000000,		/* size            */
-     0x40000000,		/* virtualAddress  */
-     NULL,			/* mapFunction     */
-     NULL,			/* unmapFunction   */
-     0,				/* refCount        */
-     IX_OSAL_BE | IX_OSAL_LE_AC,/* endianType      */
-     "Misc Cfg"			/* name            */
-     },
-
-    /* Global BE and LE_AC map */
-    {
-     IX_OSAL_STATIC_MAP,	/* type            */
-     0x70000000,		/* physicalAddress */
-     0x8FFFFFFF,		/* size            */
-     0x70000000,		/* virtualAddress  */
-     NULL,			/* mapFunction     */
-     NULL,			/* unmapFunction   */
-     0,				/* refCount        */
-     IX_OSAL_BE | IX_OSAL_LE_AC,/* endianType      */
-     "Exp Cfg"			/* name            */
-     },
-};
-
-#endif /* IxOsalIoMem_C */
-#endif /* #define IxOsalOsIxp400_H */
diff --git a/drivers/net/npe/include/IxOsalOsIxp400CustomizedMapping.h b/drivers/net/npe/include/IxOsalOsIxp400CustomizedMapping.h
deleted file mode 100644
index e037823102..0000000000
--- a/drivers/net/npe/include/IxOsalOsIxp400CustomizedMapping.h
+++ /dev/null
@@ -1,380 +0,0 @@
-/**
- * @file IxOsalOsIxp400CustomizedMapping.h 
- *
- * @brief Set LE coherency modes for components. 
- *        The default setting is IX_OSAL_NO_MAPPING for LE.
- * 
- *
- *		  By default IX_OSAL_STATIC_MEMORY_MAP is defined for all the components.
- *		  If any component uses a dynamic memory map it must define
- *		  IX_OSAL_DYNAMIC_MEMORY_MAP in its corresponding section.
- *        
- *
- * @par
- * 
- * @par
- * IXP400 SW Release version 2.0
- * 
- * -- Copyright Notice --
- * 
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- * 
- * @par
- * SPDX-License-Identifier:	BSD-3-Clause
- * @par
- * -- End of Copyright Notice --
- */
-
-#ifndef IxOsalOsIxp400CustomizedMapping_H
-#define IxOsalOsIxp400CustomizedMapping_H
-
-/*
- * only include this file in Little Endian
- */
-
-#if defined (IX_OSAL_LINUX_BE)
-#error Only include IxOsalOsIxp400CustomizedMapping.h in Little Endian
-#endif
-
- /*
-  * Components don't have to be in this list if
-  * the default mapping is OK.
-  */
-#define ix_osal                1
-#define ix_dmaAcc              2
-#define ix_atmdAcc             3
-
-#define ix_atmsch              5
-#define ix_ethAcc              6
-#define ix_npeMh               7
-#define ix_qmgr                8
-#define ix_npeDl               9
-#define ix_atmm                10
-#define ix_hssAcc              11
-#define ix_ethDB               12
-#define ix_ethMii              13
-#define ix_timerCtrl           14
-#define ix_adsl                15
-#define ix_usb                 16
-#define ix_uartAcc             17
-#define ix_featureCtrl         18
-#define ix_cryptoAcc           19
-#define ix_unloadAcc           33
-#define ix_perfProfAcc         34
-#define ix_parityENAcc                 49
-#define ix_sspAcc                      51
-#define ix_timeSyncAcc                 52
-#define ix_i2c                         53
-
-#define ix_codelets_uartAcc    21
-#define ix_codelets_timers     22
-#define ix_codelets_atm        23
-#define ix_codelets_ethAal5App 24
-#define ix_codelets_demoUtils  26
-#define ix_codelets_usb        27
-#define ix_codelets_hssAcc     28
-#define ix_codelets_dmaAcc         40
-#define ix_codelets_cryptoAcc	   41
-#define ix_codelets_perfProfAcc    42
-#define ix_codelets_ethAcc         43
-#define ix_codelets_parityENAcc        54
-#define ix_codelets_timeSyncAcc        55
-
-
-#endif /* IxOsalOsIxp400CustomizedMapping_H */
-
-
-/***************************
- * osal
- ***************************/
-#if (IX_COMPONENT_NAME == ix_osal)
-
-#define IX_OSAL_LE_AC_MAPPING
-
-#endif /* osal */
-
-/***************************
- * dmaAcc
- ***************************/
-#if (IX_COMPONENT_NAME == ix_dmaAcc)
-
-#define IX_OSAL_LE_AC_MAPPING
-
-#endif /* dmaAcc */
-
-/***************************
- * atmdAcc
- ***************************/
-#if (IX_COMPONENT_NAME == ix_atmdAcc)
-
-#define IX_OSAL_LE_AC_MAPPING
-
-#endif /* atmdAcc */
-
-/***************************
- * atmsch
- ***************************/
-#if (IX_COMPONENT_NAME == ix_atmsch)
-
-#define IX_OSAL_LE_AC_MAPPING
-
-#endif /* atmsch */
-
-/***************************
- * ethAcc
- ***************************/
-#if (IX_COMPONENT_NAME == ix_ethAcc)
-
-#define IX_OSAL_LE_AC_MAPPING
-
-#endif /* ethAcc */
-
-/***************************
- * npeMh
- ***************************/
-#if (IX_COMPONENT_NAME == ix_npeMh)
-
-#define IX_OSAL_LE_AC_MAPPING
-
-#endif /* npeMh */
-
-/***************************
- * qmgr
- ***************************/
-#if (IX_COMPONENT_NAME == ix_qmgr)
-
-#define IX_OSAL_LE_DC_MAPPING
-
-#endif /* qmgr */
-
-/***************************
- * npeDl
- ***************************/
-#if (IX_COMPONENT_NAME == ix_npeDl)
-
-#define IX_OSAL_LE_AC_MAPPING
-
-#endif /* npeDl */
-
-/***************************
- * atmm
- ***************************/
-#if (IX_COMPONENT_NAME == ix_atmm)
-
-#define IX_OSAL_LE_AC_MAPPING
-
-#endif /* atmm */
-
-/***************************
- * ethMii
- ***************************/
-#if (IX_COMPONENT_NAME == ix_ethMii)
-
-#define IX_OSAL_LE_AC_MAPPING
-
-#endif /* ethMii */
-
-
-/***************************
- * adsl
- ***************************/
-#if (IX_COMPONENT_NAME == ix_adsl)
-
-#define IX_OSAL_LE_AC_MAPPING
-
-#endif /* adsl */
-
-/***************************
- * usb
- ***************************/
-#if (IX_COMPONENT_NAME == ix_usb)
-
-#define IX_OSAL_LE_AC_MAPPING
-
-#endif /* usb */
-
-/***************************
- * uartAcc
- ***************************/
-#if (IX_COMPONENT_NAME == ix_uartAcc)
-
-#define IX_OSAL_LE_AC_MAPPING
-
-#endif /* uartAcc */
-
-/***************************
- * featureCtrl
- ***************************/
-#if (IX_COMPONENT_NAME == ix_featureCtrl)
-
-#define IX_OSAL_LE_AC_MAPPING
-
-#endif /* featureCtrl */
-
-/***************************
- * cryptoAcc
- ***************************/
-#if (IX_COMPONENT_NAME == ix_cryptoAcc)
-
-#define IX_OSAL_LE_AC_MAPPING
-
-#endif /* cryptoAcc */
-
-/***************************
- * codelets_usb
- ***************************/
-#if (IX_COMPONENT_NAME == ix_codelets_usb)
-
-#define IX_OSAL_LE_AC_MAPPING
-
-#endif /* codelets_usb */
-
-
-/***************************
- * codelets_uartAcc
- ***************************/
-#if (IX_COMPONENT_NAME == ix_codelets_uartAcc)
-
-#define IX_OSAL_LE_AC_MAPPING
-
-#endif /* codelets_uartAcc */
-
-
-
-/***************************
- * codelets_timers
- ***************************/
-#if (IX_COMPONENT_NAME == ix_codelets_timers)
-
-#define IX_OSAL_LE_AC_MAPPING
-
-#endif /* codelets_timers */
-
-/***************************
- * codelets_atm
- ***************************/
-#if (IX_COMPONENT_NAME == ix_codelets_atm)
-
-#define IX_OSAL_LE_AC_MAPPING
-
-#endif /* codelets_atm */
-
-/***************************
- * codelets_ethAal5App
- ***************************/
-#if (IX_COMPONENT_NAME == ix_codelets_ethAal5App)
-
-#define IX_OSAL_LE_AC_MAPPING
-
-#endif /* codelets_ethAal5App */
-
-/***************************
- * codelets_ethAcc
- ***************************/
-#if (IX_COMPONENT_NAME == ix_codelets_ethAcc)
-
-#define IX_OSAL_LE_AC_MAPPING
-
-#endif /* codelets_ethAcc */
-
-
-/***************************
- * codelets_demoUtils
- ***************************/
-#if (IX_COMPONENT_NAME == ix_codelets_demoUtils)
-
-#define IX_OSAL_LE_AC_MAPPING
-
-#endif /* codelets_demoUtils */
-
-
-
-/***************************
- * perfProfAcc
- ***************************/
-#if (IX_COMPONENT_NAME == ix_perfProfAcc)
-
-#define IX_OSAL_LE_AC_MAPPING
-
-#endif /* perfProfAcc */
-
-
-/***************************
- * unloadAcc
- ***************************/
-#if (IX_COMPONENT_NAME == ix_unloadAcc)
-
-#define IX_OSAL_LE_AC_MAPPING
-
-#endif /* unloadAcc */
-
-
-
-
-
-/***************************
- * parityENAcc
- ***************************/
-#if (IX_COMPONENT_NAME == ix_parityENAcc)
-
-#define IX_OSAL_LE_AC_MAPPING
-
-#endif /* parityENAcc */
-
-/***************************
- * codelets_parityENAcc
- ***************************/
-#if (IX_COMPONENT_NAME == ix_codelets_parityENAcc)
-
-#define IX_OSAL_LE_AC_MAPPING
-
-#endif /* codelets_parityENAcc */
-
-
-
-
-/***************************
- * timeSyncAcc
- ***************************/
-#if (IX_COMPONENT_NAME == ix_timeSyncAcc)
-
-#define IX_OSAL_LE_AC_MAPPING
-
-#endif /* timeSyncAcc */
-
-
-/***************************
- * codelets_timeSyncAcc
- ***************************/
-#if (IX_COMPONENT_NAME == ix_codelets_timeSyncAcc)
-
-#define IX_OSAL_LE_AC_MAPPING
-
-#endif /* codelets_timeSyncAcc */
-
-
-
-
-/***************************
- * i2c
- ***************************/
-#if (IX_COMPONENT_NAME == ix_i2c)
-
-#define IX_OSAL_LE_AC_MAPPING
-
-#endif /* i2c */
-
-
-
-/***************************
- * sspAcc
- ***************************/
-#if (IX_COMPONENT_NAME == ix_sspAcc)
-
-#define IX_OSAL_LE_AC_MAPPING
-
-#endif /* sspAcc */
-
-
diff --git a/drivers/net/npe/include/IxOsalOsTypes.h b/drivers/net/npe/include/IxOsalOsTypes.h
deleted file mode 100644
index 272eef185e..0000000000
--- a/drivers/net/npe/include/IxOsalOsTypes.h
+++ /dev/null
@@ -1,60 +0,0 @@
-#ifndef IxOsalOsTypes_H
-#define IxOsalOsTypes_H
-
-#include <asm/types.h>
-
-typedef s64 INT64;
-typedef u64 UINT64;
-typedef s32 INT32;
-typedef u32 UINT32;
-typedef s16 INT16;
-typedef u16 UINT16;
-typedef s8 INT8;
-typedef u8 UINT8;
-
-typedef u32 ULONG;
-typedef u16 USHORT;
-typedef u8 UCHAR;
-typedef u32 BOOL;
-
-#if 0 /* FIXME */
-
-/* Default stack limit is 10 KB */
-#define IX_OSAL_OS_THREAD_DEFAULT_STACK_SIZE  (10240)
-
-/* Maximum stack limit is 32 MB */
-#define IX_OSAL_OS_THREAD_MAX_STACK_SIZE      (33554432)  /* 32 MBytes */
-
-/* Default thread priority */
-#define IX_OSAL_OS_DEFAULT_THREAD_PRIORITY    (90)
-
-/* Thread maximum priority (0 - 255). 0 - highest priority */
-#define IX_OSAL_OS_MAX_THREAD_PRIORITY	      (255)
-
-#endif /* FIXME */
-
-#define IX_OSAL_OS_WAIT_FOREVER (-1L)
-#define IX_OSAL_OS_WAIT_NONE	0
-
-
-/* Thread handle is eventually an int type */
-typedef int IxOsalOsThread;
-
-/* Semaphore handle FIXME */
-typedef int IxOsalOsSemaphore;
-
-/* Mutex handle */
-typedef int IxOsalOsMutex;
-
-/*
- * Fast mutex handle - fast mutex operations are implemented in
- * native assembler code using atomic test-and-set instructions
- */
-typedef int IxOsalOsFastMutex;
-
-typedef struct
-{
-} IxOsalOsMessageQueue;
-
-
-#endif /* IxOsalOsTypes_H */
diff --git a/drivers/net/npe/include/IxOsalOsUtilitySymbols.h b/drivers/net/npe/include/IxOsalOsUtilitySymbols.h
deleted file mode 100644
index beb45a0794..0000000000
--- a/drivers/net/npe/include/IxOsalOsUtilitySymbols.h
+++ /dev/null
@@ -1,4 +0,0 @@
-#ifndef IxOsalOsUtilitySymbols_H
-#define IxOsalOsUtilitySymbols_H
-
-#endif /* IxOsalOsUtilitySymbols_H */
diff --git a/drivers/net/npe/include/IxOsalTypes.h b/drivers/net/npe/include/IxOsalTypes.h
deleted file mode 100644
index aefa70f0b7..0000000000
--- a/drivers/net/npe/include/IxOsalTypes.h
+++ /dev/null
@@ -1,355 +0,0 @@
-/**
- * @file IxOsalTypes.h
- *
- * @brief Define OSAL basic data types.
- *
- * This file contains fundamental data types used by OSAL.
- *
- * @par
- * IXP400 SW Release version 2.0
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * SPDX-License-Identifier:	BSD-3-Clause
- * @par
- * -- End of Copyright Notice --
- */
-
-
-#ifndef IxOsalTypes_H
-#define IxOsalTypes_H
-
-#include <config.h>
-#include <common.h>
-
-#define __ixp42X			/* sr: U-Boot needs this define */
-#define IXP425_EXP_CFG_BASE	0xC4000000
-#define diag_printf		debug
-
-#undef SIMSPARCSOLARIS
-#define SIMSPARCSOLARIS		0xaffe	/* sr: U-Boot gets confused with this solaris define */
-
-/*
- * Include the OS-specific type definitions
- */
-#include "IxOsalOsTypes.h"
-/**
- * @defgroup IxOsalTypes Osal basic data types.
- *
- * @brief Basic data types for Osal
- *
- * @{
- */
-
-/**
- * @brief OSAL status
- *
- * @note Possible OSAL return status include IX_SUCCESS and IX_FAIL.
- */
-typedef UINT32 IX_STATUS;
-
-/**
- * @brief VUINT32
- *
- * @note volatile UINT32
- */
-typedef volatile UINT32 VUINT32;
-
-/**
- * @brief VINT32
- *
- * @note volatile INT32
- */
-typedef volatile INT32 VINT32;
-
-/**
- * @ingroup IxOsalTypes
- *
- * @def IX_OSAL_BILLION
- *
- * @brief  Alias for 1,000,000,000
- *
- */
-#define IX_OSAL_BILLION (1000000000)
-
-#ifndef NULL
-#define NULL       0L
-#endif
-
-/**
- * @ingroup IxOsalTypes
- *
- * @def IX_SUCCESS
- *
- * @brief Success status
- *
- */
-#ifndef IX_SUCCESS
-#define IX_SUCCESS 0L /**< #defined as 0L */
-#endif
-
-/**
- * @ingroup IxOsalTypes
- *
- * @def IX_FAIL
- *
- * @brief Failure status
- *
- */
-#ifndef IX_FAIL
-#define IX_FAIL    1L /**< #defined as 1L */
-#endif
-
-
-#ifndef PRIVATE
-#ifdef IX_PRIVATE_OFF
-#define PRIVATE			/* nothing */
-#else
-#define PRIVATE static	/**< #defined as static, except for debug builds */
-#endif /* IX_PRIVATE_OFF */
-#endif /* PRIVATE */
-
-
-/**
- * @ingroup IxOsalTypes
- *
- * @def IX_OSAL_INLINE
- *
- * @brief Alias for __inline
- *
- */
-#ifndef IX_OSAL_INLINE
-#define IX_OSAL_INLINE __inline
-#endif /* IX_OSAL_INLINE */
-
-
-#ifndef __inline__
-#define __inline__	IX_OSAL_INLINE
-#endif
-
-
-/* Each OS can define its own PUBLIC, otherwise it will be empty. */
-#ifndef PUBLIC
-#define PUBLIC
-#endif /* PUBLIC */
-
-
-/**
- * @ingroup IxOsalTypes
- *
- * @def IX_OSAL_INLINE_EXTERN
- *
- * @brief Alias for __inline extern
- *
- */
-#ifndef IX_OSAL_INLINE_EXTERN
-#define IX_OSAL_INLINE_EXTERN IX_OSAL_INLINE extern
-#endif
-
-/**
- * @ingroup IxOsalTypes
- * @enum IxOsalLogDevice
- * @brief This is an emum for OSAL log devices.
- */
-typedef enum
-{
-    IX_OSAL_LOG_DEV_STDOUT = 0,	       /**< standard output (implemented by default) */
-    IX_OSAL_LOG_DEV_STDERR = 1,	       /**< standard error (implemented */
-    IX_OSAL_LOG_DEV_HEX_DISPLAY = 2,   /**< hexadecimal display (not implemented) */
-    IX_OSAL_LOG_DEV_ASCII_DISPLAY = 3  /**< ASCII-capable display (not implemented) */
-} IxOsalLogDevice;
-
-
-/**
- * @ingroup IxOsalTypes
- *
- * @def IX_OSAL_LOG_ERROR
- *
- * @brief Alias for -1, used as log function error status
- *
- */
-#define IX_OSAL_LOG_ERROR (-1)
-
-/**
- * @ingroup IxOsalTypes
- * @enum IxOsalLogLevel
- * @brief This is an emum for OSAL log trace level.
- */
-typedef enum
-{
-    IX_OSAL_LOG_LVL_NONE = 0,	 /**<No trace level */
-    IX_OSAL_LOG_LVL_USER = 1,	 /**<Set trace level to user */
-    IX_OSAL_LOG_LVL_FATAL = 2,	 /**<Set trace level to fatal */
-    IX_OSAL_LOG_LVL_ERROR = 3,	 /**<Set trace level to error */
-    IX_OSAL_LOG_LVL_WARNING = 4, /**<Set trace level to warning */
-    IX_OSAL_LOG_LVL_MESSAGE = 5, /**<Set trace level to message */
-    IX_OSAL_LOG_LVL_DEBUG1 = 6,	 /**<Set trace level to debug1 */
-    IX_OSAL_LOG_LVL_DEBUG2 = 7,	 /**<Set trace level to debug2 */
-    IX_OSAL_LOG_LVL_DEBUG3 = 8,	 /**<Set trace level to debug3 */
-    IX_OSAL_LOG_LVL_ALL	/**<Set trace level to all */
-} IxOsalLogLevel;
-
-
-/**
- * @ingroup IxOsalTypes
- * @brief Void function pointer prototype
- *
- * @note accepts a void pointer parameter
- * and does not return a value.
- */
-typedef void (*IxOsalVoidFnVoidPtr) (void *);
-
-typedef void (*IxOsalVoidFnPtr) (void);
-
-
-/**
- * @brief Timeval structure
- *
- * @note Contain subfields of seconds and nanoseconds..
- */
-typedef struct
-{
-    UINT32 secs;		/**< seconds */
-    UINT32 nsecs;		/**< nanoseconds */
-} IxOsalTimeval;
-
-
-/**
- * @ingroup IxOsalTypes
- * @brief IxOsalTimer
- *
- * @note OSAL timer handle
- *
- */
-typedef UINT32 IxOsalTimer;
-
-
-/**
- * @ingroup IxOsalTypes
- *
- * @def IX_OSAL_WAIT_FOREVER
- *
- * @brief Definition for timeout forever, OS-specific.
- *
- */
-#define IX_OSAL_WAIT_FOREVER IX_OSAL_OS_WAIT_FOREVER
-
-/**
- * @ingroup IxOsalTypes
- *
- * @def IX_OSAL_WAIT_NONE
- *
- * @brief Definition for timeout 0, OS-specific.
- *
- */
-#define IX_OSAL_WAIT_NONE    IX_OSAL_OS_WAIT_NONE
-
-
-/**
- * @ingroup IxOsalTypes
- * @brief IxOsalMutex
- *
- * @note Mutex handle, OS-specific
- *
- */
-typedef IxOsalOsMutex IxOsalMutex;
-
-/**
- * @ingroup IxOsalTypes
- * @brief IxOsalFastMutex
- *
- * @note FastMutex handle, OS-specific
- *
- */
-typedef IxOsalOsFastMutex IxOsalFastMutex;
-
-/**
- * @ingroup IxOsalTypes
- * @brief IxOsalThread
- *
- * @note Thread handle, OS-specific
- *
- */
-typedef IxOsalOsThread IxOsalThread;
-
-/**
- * @ingroup IxOsalTypes
- * @brief IxOsalSemaphore
- *
- * @note Semaphore handle, OS-specific
- *
- */
-typedef IxOsalOsSemaphore IxOsalSemaphore;
-
-/**
- * @ingroup IxOsalTypes
- * @brief IxOsalMessageQueue
- *
- * @note Message Queue handle, OS-specific
- *
- */
-typedef IxOsalOsMessageQueue IxOsalMessageQueue;
-
-
-/**
- * @brief Thread Attribute
- * @note Default thread attribute
- */
-typedef struct
-{
-    char *name;        /**< name */
-    UINT32 stackSize;  /**< stack size */
-    UINT32 priority;   /**< priority */
-} IxOsalThreadAttr;
-
-/**
- * @ingroup IxOsalTypes
- *
- * @def IX_OSAL_THREAD_DEFAULT_STACK_SIZE
- *
- * @brief Default thread stack size, OS-specific.
- *
- */
-#define IX_OSAL_THREAD_DEFAULT_STACK_SIZE (IX_OSAL_OS_THREAD_DEFAULT_STACK_SIZE)
-
-/**
- * @ingroup IxOsalTypes
- *
- * @def IX_OSAL_THREAD_MAX_STACK_SIZE
- *
- * @brief Max stack size, OS-specific.
- *
- */
-#define IX_OSAL_THREAD_MAX_STACK_SIZE (IX_OSAL_OS_THREAD_MAX_STACK_SIZE)
-
-/**
- * @ingroup IxOsalTypes
- *
- * @def IX_OSAL_DEFAULT_THREAD_PRIORITY
- *
- * @brief Default thread priority, OS-specific.
- *
- */
-#define IX_OSAL_DEFAULT_THREAD_PRIORITY (IX_OSAL_OS_DEFAULT_THREAD_PRIORITY)
-
-/**
- * @ingroup IxOsalTypes
- *
- * @def IX_OSAL_MAX_THREAD_PRIORITY
- *
- * @brief Max thread priority, OS-specific.
- *
- */
-#define IX_OSAL_MAX_THREAD_PRIORITY (IX_OSAL_OS_MAX_THREAD_PRIORITY)
-
-/**
- * @} IxOsalTypes
- */
-
-
-#endif /* IxOsalTypes_H */
diff --git a/drivers/net/npe/include/IxOsalUtilitySymbols.h b/drivers/net/npe/include/IxOsalUtilitySymbols.h
deleted file mode 100644
index ec34df6f71..0000000000
--- a/drivers/net/npe/include/IxOsalUtilitySymbols.h
+++ /dev/null
@@ -1,27 +0,0 @@
-/**
- * @file
- *
- * @brief OSAL Configuration header file
- * 
- * 
- * @par
- * IXP400 SW Release version 2.0
- * 
- * -- Copyright Notice --
- * 
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- * 
- * @par
- * SPDX-License-Identifier:	BSD-3-Clause
- * @par
- * -- End of Copyright Notice --
- */
-
-#ifndef IxOsalUtilitySymbols_H
-#define IxOsalUtilitySymbols_H
-
-#include "IxOsalOsUtilitySymbols.h"	/* OS-specific utility symbol definitions */
-
-#endif /* IxOsalUtilitySymbols_H */
diff --git a/drivers/net/npe/include/IxParityENAcc.h b/drivers/net/npe/include/IxParityENAcc.h
deleted file mode 100644
index 4d44838cb1..0000000000
--- a/drivers/net/npe/include/IxParityENAcc.h
+++ /dev/null
@@ -1,761 +0,0 @@
-/**
- * @file IxParityENAcc.h
- *
- * @author Intel Corporation
- * @date 24 Mar 2004
- *
- * @brief This file contains the public API for the IXP400 Parity Error 
- * Notifier access component.
- *
- * @par
- * IXP400 SW Release version 2.0
- * 
- * -- Copyright Notice --
- * 
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- * 
- * @par
- * SPDX-License-Identifier:	BSD-3-Clause
- * @par
- * -- End of Copyright Notice --
- */
-
-/**
- * @defgroup IxParityENAcc IXP400 Parity Error Notifier (IxParityENAcc) API
- *
- * @brief The public API for the Parity Error Notifier 
- * 
- * @{
- */
-
-#ifndef IXPARITYENACC_H
-#define IXPARITYENACC_H
-
-#ifdef __ixp46X
-
-#include "IxOsal.h"
-
-/*
- * #defines for function return types, etc.
- */
-
-/**
- * @ingroup IxParityENAcc
- *
- * @enum IxParityENAccStatus
- *
- * @brief The status as returend from the API
- */
-typedef enum /**< IxParityENAccStatus */
-{
-  IX_PARITYENACC_SUCCESS = IX_SUCCESS, /**< The request is successful */
-  IX_PARITYENACC_INVALID_PARAMETERS,   /**< Invalid or NULL parameters passed */
-  IX_PARITYENACC_NOT_INITIALISED,      /**< Access layer has not been initialised before accessing the APIs */
-  IX_PARITYENACC_ALREADY_INITIALISED,  /**< Access layer has already been initialised */ 
-  IX_PARITYENACC_OPERATION_FAILED,     /**< Operation did not succeed due to hardware failure */
-  IX_PARITYENACC_NO_PARITY             /**< No parity condition exits or has already been cleared */
-} IxParityENAccStatus;
-
-/**
- * @ingroup IxParityENAcc
- *
- * @enum IxParityENAccParityType
- * 
- * @brief Odd or Even Parity Type
- */
-typedef enum  /**< IxParityENAccParityType */
-{
-  IX_PARITYENACC_EVEN_PARITY,    /**< Even Parity */
-  IX_PARITYENACC_ODD_PARITY      /**< Odd Parity */
-} IxParityENAccParityType;
-
-/**
- * @ingroup IxParityENAcc
- *
- * @enum IxParityENAccConfigOption
- *
- * @brief The parity error enable/disable configuration option
- */
-typedef enum /**< IxParityENAccConfigOption */
-{
-  IX_PARITYENACC_DISABLE,       /**< Disable parity error detection */
-  IX_PARITYENACC_ENABLE         /**< Enable parity error detection */
-} IxParityENAccConfigOption;
-
-/**
- * @ingroup IxParityENAcc
- *
- * @struct IxParityENAccNpeConfig
- *
- * @brief NPE parity detection is to be enabled/disabled
- */
-typedef struct /**< IxParityENAccNpeConfig */
-{
-  IxParityENAccConfigOption ideEnabled; /**< NPE IMem, DMem and External */
-  IxParityENAccParityType parityOddEven; /**< Parity - Odd or Even */
-} IxParityENAccNpeConfig ;
-
-
-/**
- * @ingroup IxParityENAcc
- *
- * @struct IxParityENAccMcuConfig
- *
- * @brief MCU pairty detection is to be enabled/disabled
- */
-typedef struct /**< IxParityENAccMcuConfig */ 
-{
-  IxParityENAccConfigOption singlebitDetectEnabled;      /**< Single-bit parity error detection */
-  IxParityENAccConfigOption singlebitCorrectionEnabled;  /**< Single-bit parity error correction */
-  IxParityENAccConfigOption multibitDetectionEnabled;    /**< Multi-bit  parity error detection */
-} IxParityENAccMcuConfig ;
-
-
-/**
- * @ingroup IxParityENAcc
- *
- * @struct IxParityENAccEbcConfig
- *
- * @brief Expansion Bus Controller parity detection is to be enabled or disabled 
- *
- * Note: All the Chip Select(s) and External Masters will have the same parity
- */
-typedef struct /**< IxParityENAccEbcConfig */
-{
-  IxParityENAccConfigOption ebcCs0Enabled;    /**< Expansion Bus Controller - Chip Select 0 */
-  IxParityENAccConfigOption ebcCs1Enabled;    /**< Expansion Bus Controller - Chip Select 1 */
-  IxParityENAccConfigOption ebcCs2Enabled;    /**< Expansion Bus Controller - Chip Select 2 */
-  IxParityENAccConfigOption ebcCs3Enabled;    /**< Expansion Bus Controller - Chip Select 3 */
-  IxParityENAccConfigOption ebcCs4Enabled;    /**< Expansion Bus Controller - Chip Select 4 */
-  IxParityENAccConfigOption ebcCs5Enabled;    /**< Expansion Bus Controller - Chip Select 5 */
-  IxParityENAccConfigOption ebcCs6Enabled;    /**< Expansion Bus Controller - Chip Select 6 */
-  IxParityENAccConfigOption ebcCs7Enabled;    /**< Expansion Bus Controller - Chip Select 7 */
-  IxParityENAccConfigOption ebcExtMstEnabled; /**< External Master on Expansion bus */
-  IxParityENAccParityType parityOddEven;      /**< Parity - Odd or Even */
-} IxParityENAccEbcConfig ;
-
-/**
- * @ingroup IxParityENAcc
- *
- * @struct IxParityENAccHWParityConfig
- *
- * @brief Parity error configuration of the Hardware Blocks
- */
-typedef struct /**< IxParityENAccHWParityConfig */
-{ 
-  IxParityENAccNpeConfig npeAConfig;     /**< NPE A parity detection is to be enabled/disabled */
-  IxParityENAccNpeConfig npeBConfig;     /**< NPE B parity detection is to be enabled/disabled */
-  IxParityENAccNpeConfig npeCConfig;     /**< NPE C parity detection is to be enabled/disabled */
-  IxParityENAccMcuConfig mcuConfig;      /**< MCU pairty detection is to be enabled/disabled */
-  IxParityENAccConfigOption swcpEnabled; /**< SWCP parity detection is to be enabled */
-  IxParityENAccConfigOption aqmEnabled;  /**< AQM parity detection is to be enabled */
-  IxParityENAccEbcConfig ebcConfig;      /**< Expansion Bus Controller parity detection is to be enabled/disabled */
-} IxParityENAccHWParityConfig;
-
-
-/**
- * @ingroup IxParityENAcc
- *
- * @struct IxParityENAccNpeParityErrorStats
- *
- * @brief NPE parity error statistics
- */
-typedef struct  /* IxParityENAccNpeParityErrorStats */
-{
-  UINT32 parityErrorsIMem;         /**< Parity errors in Instruction Memory */
-  UINT32 parityErrorsDMem;         /**< Parity errors in Data Memory */
-  UINT32 parityErrorsExternal;     /**< Parity errors in NPE External Entities */
-} IxParityENAccNpeParityErrorStats;
-
-/**
- * @ingroup IxParityENAcc
- *
- * @struct IxParityENAccMcuParityErrorStats
- *
- * @brief DDR Memory Control Unit parity error statistics
- * 
- * Note: There could be two outstanding parity errors at any given time whose address
- * details captured. If there is no room for the new interrupt then it would be treated
- * as overflow parity condition.
- */
-typedef struct  /* IxParityENAccMcuParityErrorStats */
-{
-  UINT32 parityErrorsSingleBit;    /**< Parity errors of the type Single-Bit */
-  UINT32 parityErrorsMultiBit;     /**< Parity errors of the type Multi-Bit */
-  UINT32 parityErrorsOverflow;     /**< Parity errors when more than two parity errors occured */
-} IxParityENAccMcuParityErrorStats;
-
-/**
- * @ingroup IxParityENAcc
- *
- * @struct IxParityENAccEbcParityErrorStats
- *
- * @brief Expansion Bus Controller parity error statistics
- */
-typedef struct  /* IxParityENAccEbcParityErrorStats */
-{
-  UINT32 parityErrorsInbound;      /**< Odd bit parity errors on inbound transfers */
-  UINT32 parityErrorsOutbound;     /**< Odd bit parity errors on outbound transfers */
-} IxParityENAccEbcParityErrorStats;
-
-
-/**
- * @ingroup IxParityENAcc
- *
- * @struct IxParityENAccParityErrorStats
- *
- * @brief Parity Error Statistics for the all the hardware blocks
- */
-typedef struct  /**< IxParityENAccParityErrorStats */
-{
-  IxParityENAccNpeParityErrorStats  npeStats;  /**< NPE parity error statistics */
-  IxParityENAccMcuParityErrorStats  mcuStats;  /**< MCU parity error statistics */
-  IxParityENAccEbcParityErrorStats  ebcStats;  /**< EBC parity error statistics */
-  UINT32                            swcpStats; /**< SWCP parity error statistics */
-  UINT32                            aqmStats;  /**< AQM parity error statistics */
-} IxParityENAccParityErrorStats;
-
-
-/**
- * @ingroup IxParityENAcc
- *
- * @enum IxParityENAccParityErrorSource
- *
- * @brief The source of the parity error notification 
- */
-typedef enum  /**< IxParityENAccParityErrorSource  */
-{
-  IX_PARITYENACC_NPE_A_IMEM,     /**< NPE A - Instruction memory */
-  IX_PARITYENACC_NPE_A_DMEM,     /**< NPE A - Data memory */
-  IX_PARITYENACC_NPE_A_EXT,      /**< NPE A - External Entity*/
-  IX_PARITYENACC_NPE_B_IMEM,     /**< NPE B - Instruction memory */
-  IX_PARITYENACC_NPE_B_DMEM,     /**< NPE B - Data memory */
-  IX_PARITYENACC_NPE_B_EXT,      /**< NPE B - External Entity*/
-  IX_PARITYENACC_NPE_C_IMEM,     /**< NPE C - Instruction memory */
-  IX_PARITYENACC_NPE_C_DMEM,     /**< NPE C - Data memory */
-  IX_PARITYENACC_NPE_C_EXT,      /**< NPE C - External Entity*/
-  IX_PARITYENACC_SWCP,           /**< SWCP */
-  IX_PARITYENACC_AQM,            /**< AQM */
-  IX_PARITYENACC_MCU_SBIT,       /**< DDR Memory Controller Unit - Single bit parity */
-  IX_PARITYENACC_MCU_MBIT,       /**< DDR Memory Controller Unit - Multi bit parity */
-  IX_PARITYENACC_MCU_OVERFLOW,   /**< DDR Memory Controller Unit - Parity errors in excess of two */
-  IX_PARITYENACC_EBC_CS,         /**< Expansion Bus Controller - Chip Select */
-  IX_PARITYENACC_EBC_EXTMST      /**< Expansion Bus Controller - External Master */
-} IxParityENAccParityErrorSource;
-
-/**
- * @ingroup IxParityENAcc
- *
- * @enum IxParityENAccParityErrorAccess
- *
- * @brief The type of access resulting in parity error
- */
-typedef enum  /**< IxParityENAccParityErrorAccess  */
-{
-  IX_PARITYENACC_READ,   /**< Read Access  */
-  IX_PARITYENACC_WRITE   /**< Write Access */
-} IxParityENAccParityErrorAccess;
-
-/**
- * @ingroup IxParityENAcc
- *
- * @typedef IxParityENAccParityErrorAddress
- *
- * @brief The memory location which has parity error
- */
-typedef UINT32 IxParityENAccParityErrorAddress;
-
-/**
- * @ingroup IxParityENAcc
- *
- * @typedef IxParityENAccParityErrorData
- *
- * @brief The data read from the memory location which has parity error
- */
-typedef UINT32 IxParityENAccParityErrorData;
-
-/**
- * @ingroup IxParityENAcc
- *
- * @enum IxParityENAccParityErrorRequester
- *
- * @brief The requester interface through which the SDRAM memory access 
- * resulted in the parity error.
- */
-typedef enum  /**< IxParityENAccParityErrorRequester  */
-{
-  IX_PARITYENACC_MPI,     /**< Direct Memory Port Interface  */
-  IX_PARITYENACC_AHB_BUS  /**< South or North AHB Bus */
-} IxParityENAccParityErrorRequester;
-
-/**
- * @ingroup IxParityENAcc
- *
- * @enum IxParityENAccAHBErrorMaster
- *
- * @brief The Master on the AHB bus interface whose transaction might have 
- * resulted in the parity error notification to XScale.
- */
-typedef enum  /**< IxParityENAccAHBErrorMaster */
-{
-  IX_PARITYENACC_AHBN_MST_NPE_A,       /**< NPE - A */
-  IX_PARITYENACC_AHBN_MST_NPE_B,       /**< NPE - B */
-  IX_PARITYENACC_AHBN_MST_NPE_C,       /**< NPE - C */
-  IX_PARITYENACC_AHBS_MST_XSCALE,      /**< XScale Bus Interface Unit */
-  IX_PARITYENACC_AHBS_MST_PBC,         /**< PCI Bus Controller */
-  IX_PARITYENACC_AHBS_MST_EBC,         /**< Expansion Bus Controller */
-  IX_PARITYENACC_AHBS_MST_AHB_BRIDGE,  /**< AHB Bridge */
-  IX_PARITYENACC_AHBS_MST_USBH         /**< USB Host Controller */
-} IxParityENAccAHBErrorMaster;
-
-/**
- * @ingroup IxParityENAcc
- *
- * @enum IxParityENAccAHBErrorSlave
- *
- * @brief The Slave on the AHB bus interface whose transaction might have 
- * resulted in the parity error notification to XScale.
- */
-typedef enum  /**< IxParityENAccAHBErrorSlave */
-{
-  IX_PARITYENACC_AHBN_SLV_MCU,         /**< Memory Control Unit */
-  IX_PARITYENACC_AHBN_SLV_AHB_BRIDGE,  /**< AHB Bridge */
-  IX_PARITYENACC_AHBS_SLV_MCU,         /**< XScale Bus Interface Unit */
-  IX_PARITYENACC_AHBS_SLV_APB_BRIDGE,  /**< APB Bridge */
-  IX_PARITYENACC_AHBS_SLV_AQM,         /**< AQM */
-  IX_PARITYENACC_AHBS_SLV_RSA,         /**< RSA (Crypto Bus) */
-  IX_PARITYENACC_AHBS_SLV_PBC,         /**< PCI Bus Controller */
-  IX_PARITYENACC_AHBS_SLV_EBC,         /**< Expansion Bus Controller */
-  IX_PARITYENACC_AHBS_SLV_USBH         /**< USB Host Controller */
-} IxParityENAccAHBErrorSlave;
-
-/**
- * @ingroup IxParityENAcc
- *
- * @struct IxParityENAccAHBErrorTransaction
- *
- * @brief The Master and Slave on the AHB bus interface whose transaction might
- * have resulted in the parity error notification to XScale.
- *
- * NOTE: This information may be used in the data abort exception handler
- * to differentiate between the XScale and non-XScale access to the SDRAM
- * memory.
- */
-typedef struct  /**< IxParityENAccAHBErrorTransaction  */
-{
-  IxParityENAccAHBErrorMaster  ahbErrorMaster; /**< Master on AHB bus */
-  IxParityENAccAHBErrorSlave   ahbErrorSlave;  /**< Slave  on AHB bus */
-} IxParityENAccAHBErrorTransaction;
-
-/**
- * @ingroup IxParityENAcc
- *
- * @struct IxParityENAccParityErrorContextMessage
- *
- * @brief Parity Error Context Message
- */
-typedef struct /**< IxParityENAccParityErrorContextMessage */
-{
-  IxParityENAccParityErrorSource     pecParitySource; /**< Source info of parity error */
-  IxParityENAccParityErrorAccess     pecAccessType;   /**< Read or Write Access
-                                                           Read  - NPE, SWCP, AQM, DDR MCU,
-                                                                   Exp Bus Ctrlr (Outbound)
-                                                           Write - DDR MCU,
-                                                                   Exp Bus Ctrlr (Inbound 
-                                                                   i.e., External Master) */
-  IxParityENAccParityErrorAddress    pecAddress;      /**< Address faulty location
-                                                           Valid only for AQM, DDR MCU, 
-                                                           Exp Bus Ctrlr */
-  IxParityENAccParityErrorData       pecData;         /**< Data read from the faulty location
-                                                           Valid only for AQM and DDR MCU
-                                                           For DDR MCU it is the bit location
-                                                           of the Single-bit parity */
-  IxParityENAccParityErrorRequester  pecRequester;    /**< Requester of SDRAM memory access
-                                                           Valid only for the DDR MCU */
-  IxParityENAccAHBErrorTransaction   ahbErrorTran;    /**< Master and Slave information on the
-                                                           last AHB Error Transaction */
-} IxParityENAccParityErrorContextMessage;
-
-/**
- * @ingroup IxParityENAcc
- *
- * @typedef IxParityENAccCallback
- *
- * @brief This prototype shows the format of a callback function.
- *
- * The callback will be used to notify the parity error to the client application.
- * The callback will be registered  by @ref ixParityENAccCallbackRegister.
- *
- * It will be called from an ISR when a parity error is detected and thus
- * needs to follow the interrupt callable function conventions.
- *
- */
-typedef void (*IxParityENAccCallback) (void);
-
-
-/*
- * Prototypes for interface functions.
- */
-
-/**
- * @ingroup IxParityENAcc
- *
- * @fn IxParityENAccStatus ixParityENAccInit(void)
- *
- * @brief This function will initialise the IxParityENAcc component.
- *
- * This function will initialise the IxParityENAcc component. It should only be
- * called once, prior to using the IxParityENAcc component.
- *
- * <OL><LI>It initialises the internal data structures, registers the ISR that 
- * will be triggered when a parity error occurs in IXP4xx silicon.</LI></OL>
- *
- * @li Re-entrant   : No
- * @li ISR Callable : No
- * 
- * @return @li IX_PARITYENACC_SUCCESS - Initialization is successful
- *         @li IX_PARITYENACC_ALREADY_INITIALISED - The access layer has already 
- *             been initialized
- *         @li IX_PARITYENACC_OPERATION_FAILED - The request failed because the 
- *             operation didn't succeed on the hardware. Refer to error trace/log
- *             for details.
- */
-
-PUBLIC IxParityENAccStatus ixParityENAccInit(void);
-
-/**
- * @ingroup IxParityENAcc
- *
- * @fn IxParityENAccStatus ixParityENAccCallbackRegister (
-           IxParityENAccCallback parityErrNfyCallBack)
- *
- * @brief This function will register a new callback with IxParityENAcc component. 
- * It can also reregister a new callback replacing the old callback.
- *
- * @param parityErrNfyCallBack [in] - This parameter will specify the call-back
- * function supplied by the client application.
- *
- * This interface registers the user application supplied call-back handler with
- * the parity error handling access component after the init.
- *
- * The callback function will be called from an ISR that will be triggered by the 
- * parity error in the IXP400 silicon.
- *
- * The following actions will be performed by this function:
- * <OL><LI>Check for the prior initialisation of the module before registering or
- * re-registering of the callback.
- * Check for parity error detection disabled before re-registration of the callback.
- * </LI></OL>
- *
- * @li   Re-entrant   : No
- * @li   ISR Callable : No
- *
- * @return @li IX_PARITYENACC_SUCCESS - The parameters check passed and the 
- *             registration is successful.
- *         @li IX_PARITYENACC_INVALID_PARAMETERS - Request failed due to NULL 
- *             parameter passed.
- *         @li IX_PARITYENACC_OPERATION_FAILED - The request failed because the 
- *             parity error detection not yet disabled.
- *         @li IX_PARITYENACC_NOT_INITIALISED - The operation requested prior to
- *             the initialisation of the access layer.
- */
-
-PUBLIC IxParityENAccStatus ixParityENAccCallbackRegister (
-           IxParityENAccCallback parityErrNfyCallBack);
-
-/**
- * @ingroup IxParityENAcc
- *
- * @fn IxParityENAccStatus ixParityENAccParityDetectionConfigure (
-           const IxParityENAccHWParityConfig *hwParityConfig)
- *
- * @brief This interface allows the client application to enable the parity 
- * error detection on the underlying hardware block.
- *
- * @param hwParityConfig [in] - Hardware blocks for which the parity error 
- * detection is to be enabled or disabled.
- *
- * The client application allocates and provides the reference to the buffer.
- *
- * It will also verify whether the specific hardware block is functional or not.
- *
- * NOTE: Failure in enabling or disabling of one or more components result in
- * trace message but still returns IX_PARITYENACC_SUCCESS. Refer to the function 
- * @ref ixParityENAccParityDetectionQuery on how to verify the failures while 
- * enabling/disabling paritys error detection.
- *
- * It shall be invoked after the Init and CallbackRegister functions but before
- * any other function of the IxParityENAcc layer.
- *
- * @li   Re-entrant   : No
- * @li   ISR Callable : No
- *
- * @return @li IX_PARITYENACC_SUCCESS - The parameters check passed and the 
- *             request to enable/disable is successful.
- *         @li IX_PARITYENACC_INVALID_PARAMETERS-The request failed due to  
- *             NULL parameter supplied.
- *         @li IX_PARITYENACC_OPERATION_FAILED - The request failed because the 
- *             operation didn't succeed on the hardware.
- *         @li IX_PARITYENACC_NOT_INITIALISED - The operation requested prior to
- *             the initialisation of the access layer.
- */
-
-PUBLIC IxParityENAccStatus ixParityENAccParityDetectionConfigure (
-           const IxParityENAccHWParityConfig *hwParityConfig);
-
-/**
- * @ingroup IxParityENAcc
- *
- * @fn IxParityENAccStatus ixParityENAccParityDetectionQuery (
-           IxParityENAccHWParityConfig * const hwParityConfig)
- *
- * @brief This interface allows the client application to determine the 
- * status of the parity error detection on the specified hardware blocks
- *
- * @param hwParityConfig [out] - Hardware blocks whose parity error detection 
- * has been enabled or disabled.
- *
- * The client application allocates and provides the reference to the buffer.
- *
- * This interface can be used immediately after the interface @ref
- * ixParityENAccParityDetectionConfigure to see on which of the hardware blocks
- * the parity error detection has either been enabled or disabled based on the
- * client application request.
- *
- * @li   Re-entrant   : No
- * @li   ISR Callable : No
- *
- * @return @li IX_PARITYENACC_SUCCESS - The parameters check passed and the 
- *             request to query on whether the hardware parity error detection
- *             is enabled or disabled is successful.
- *         @li IX_PARITYENACC_INVALID_PARAMETERS-The request failed due to  
- *             NULL parameter or invalid values supplied.
- *         @li IX_PARITYENACC_NOT_INITIALISED - The operation requested prior 
- *             to the initialisation of the access layer.
- */
-
-PUBLIC IxParityENAccStatus ixParityENAccParityDetectionQuery(
-           IxParityENAccHWParityConfig * const hwParityConfig);
-
-/**
- * @ingroup IxParityENAcc
- *
- * @fn IxParityENAccStatus ixParityENAccParityErrorContextGet( 
-           IxParityENAccParityErrorContextMessage * const pecMessage)
- *
- * @brief This interface allows the client application to determine the 
- * status of the parity error context on hardware block for which the
- * current parity error interrupt triggered.
- *
- * @param pecMessage [out] - The parity error context information of the
- * parity interrupt currently being process.
- *
- * The client application allocates and provides the reference to the buffer.
- *
- * Refer to the data structure @ref IxParityENAccParityErrorContextMessage
- * for details.
- *
- * The routine will will fetch the parity error context in the following
- * priority, if multiple parity errors observed.
- * 
- * <pre>
- * 0 - MCU (Multi-bit and single-bit in that order)
- * 1 - NPE-A
- * 2 - NPE-B
- * 3 - NPE-C
- * 4 - SWCP
- * 5 - QM
- * 6 - EXP
- *
- * NOTE: The information provided in the @ref IxParityENAccAHBErrorTransaction
- * may be of help for the client application to decide on the course of action 
- * to take. This info is taken from the Performance Monitoring Unit register
- * which records most recent error observed on the AHB bus. This information
- * might have been overwritten by some other error by the time it is retrieved.
- * </pre>
- *
- * @li   Re-entrant   : No
- * @li   ISR Callable : Yes
- *
- * @return @li IX_PARITYENACC_SUCCESS-The parameters check passed and the 
- *             request to get the parity error context information is successful.
- *         @li IX_PARITYENACC_INVALID_PARAMETERS-The request failed due to  
- *             NULL parameter is passed
- *         @li IX_PARITYENACC_OPERATION_FAILED - The request failed because 
- *             the operation didn't succeed on the hardware.
- *         @li IX_PARITYENACC_NOT_INITIALISED - The operation requested prior
- *             to the initialisation of the access layer.
- *         @li IX_PARITYENACC_NO_PARITY - No parity condition exits or has 
- *             already been cleared
- */
-
-PUBLIC IxParityENAccStatus ixParityENAccParityErrorContextGet( 
-           IxParityENAccParityErrorContextMessage * const pecMessage);
-
-/**
- * @ingroup IxParityENAcc
- *
- * @fn IxParityENAccStatus ixParityENAccParityErrorInterruptClear (
-          const IxParityENAccParityErrorContextMessage *pecMessage)
- *
- * @brief This interface helps the client application to clear off the
- * interrupt condition on the hardware block identified in the parity
- * error context message.  Please refer to the table below as the operation
- * varies depending on the interrupt source.
- * 
- * @param pecMessage [in] - The parity error context information of the
- * hardware block whose parity error interrupt condition is to disabled.
- *
- * The client application allocates and provides the reference to the buffer.
- *
- * <pre>
- * ****************************************************************************
- * Following actions will be taken during the interrupt clear for respective
- * hardware blocks.
- * 
- *  Parity Source     Actions taken during Interrupt clear 
- *  -------------     -------------------------------------------------------
- *  NPE-A             Interrupt will be masked off at the interrupt controller 
- *                    so that it will not trigger continuously.
- *                      Client application has to take appropriate action and 
- *                      re-configure the parity error detection subsequently. 
- *                      The client application will not be notified of further 
- *                      interrupts, until the re-configuration is done using
- *                      @ref ixParityENAccParityDetectionConfigure.
- *
- *  NPE-B             Interrupt will be masked off at the interrupt controller 
- *                    so that it will not trigger continuously.
- *                      Client application has to take appropriate action and 
- *                      re-configure the parity error detection subsequently. 
- *                      The client application will not be notified of further
- *                      interrupts, until the re-configuration is done using
- *                      @ref ixParityENAccParityDetectionConfigure.
- *
- *  NPE-C             Interrupt will be masked off at the interrupt controller 
- *                      Client application has to take appropriate action and 
- *                      re-configure the parity error detection subsequently. 
- *                      The client application will not be notified of further
- *                      interrupts, until the re-configuration is done using
- *                      @ref ixParityENAccParityDetectionConfigure.
- *
- *  SWCP              Interrupt will be masked off at the interrupt controller.
- *                      Client application has to take appropriate action and 
- *                      re-configure the parity error detection subsequently. 
- *                      The client application will not be notified of further
- *                      interrupts, until the re-configuration is done using
- *                      @ref ixParityENAccParityDetectionConfigure.
- *
- *  AQM               Interrupt will be masked off at the interrupt controller.
- *                         Client application has to take appropriate action and 
- *                         re-configure the parity error detection subsequently. 
- *                         The client application will not be notified of further
- *                         interrupts, until the re-configuration is done using
- *                         @ref ixParityENAccParityDetectionConfigure.
- *
- *  MCU               Parity interrupt condition is cleared at the SDRAM MCU for 
- *                    the following:
- *                    1. Single-bit
- *                    2. Multi-bit
- *                    3. Overflow condition i.e., more than two parity conditions 
- *                       occurred
- *                    Note that single-parity errors do not result in data abort
- *                    and not all data aborts caused by multi-bit parity error.
- *
- *  EXP               Parity interrupt condition is cleared at the expansion bus 
- *                    controller for the following:
- *                    1. External master initiated Inbound write
- *                    2. Internal master (IXP400) initiated Outbound read
- * ****************************************************************************
- * </pre>
- * @li   Re-entrant   : No
- * @li   ISR Callable : No
- *
- * @return @li IX_PARITYENACC_SUCCESS-The parameters check passed and the request
- *             to clear the parity error interrupt condition is successful.
- *         @li IX_PARITYENACC_INVALID_PARAMETERS-The request failed due to 
- *             NULL parameters have been passed or contents have been
- *             supplied with invalid values.
- *         @li IX_PARITYENACC_OPERATION_FAILED - The request failed because 
- *             the operation didn't succeed on the hardware.
- *         @li IX_PARITYENACC_NOT_INITIALISED - The operation requested prior
- *             to the initialisation of the access layer.
- */
-
-PUBLIC IxParityENAccStatus ixParityENAccParityErrorInterruptClear (
-          const IxParityENAccParityErrorContextMessage *pecMessage);
-
-/**
- * @ingroup IxParityENAcc
- *
- * @fn IxParityENAccStatus ixParityENAccStatsGet (
-            IxParityENAccParityErrorStats * const ixParityErrorStats)
- *
- * @brief This interface allows the client application to retrieve parity 
- * error statistics for all the hardware blocks 
- *
- * @param ixParityErrorStats - [out] The statistics for all the hardware blocks.
- *
- * The client application allocates and provides the reference to the buffer.
- *
- * @li   Re-entrant   : No
- * @li   ISR Callable : Yes
- *
- * @return @li IX_PARITYENACC_SUCCESS-The parameters check passed and the 
- *             request to retrieve parity error statistics for the hardware
- *             block is successful.
- *         @li IX_PARITYENACC_INVALID_PARAMETERS-The request failed due to a
- *             NULL parameter passed.
- *         @li IX_PARITYENACC_NOT_INITIALISED - The operation requested prior
- *             to the initialisation of the access layer.
- */
-
-PUBLIC IxParityENAccStatus ixParityENAccStatsGet (
-            IxParityENAccParityErrorStats * const ixParityErrorStats);
-
-/**
- * @ingroup IxParityENAcc
- *
- * @fn IxParityENAccStatus ixParityENAccStatsShow (void)
- *
- * @brief This interface allows the client application to print all the
- * parity error statistics.
- *
- * @li   Re-entrant   : No
- * @li   ISR Callable : No
- *
- * @return @li IX_PARITYENACC_SUCCESS - The request to show the pairty 
- *             error statistics is successful.
- *         @li IX_PARITYENACC_NOT_INITIALISED - The operation requested
- *             prior to the initialisation of the access layer.
- */
-
-PUBLIC IxParityENAccStatus ixParityENAccStatsShow (void);
-
-/**
- * @ingroup IxParityENAcc
- *
- * @fn IxParityENAccStatus ixParityENAccStatsReset (void)
- *
- * @brief This interface allows the client application to reset all the 
- * parity error statistics.
- *
- * @li   Re-entrant   : No
- * @li   ISR Callable : No
- *
- * @return @li IX_PARITYENACC_SUCCESS - The request to reset the parity 
- *             error statistics is successful.
- *         @li IX_PARITYENACC_NOT_INITIALISED - The operation requested 
- *             prior to the initialisation of the access layer.
- */
-
-PUBLIC IxParityENAccStatus ixParityENAccStatsReset (void);
-
-#endif /* IXPARITYENACC_H */
-#endif /* __ixp46X */
-
-/**
- * @} defgroup IxParityENAcc
- */
-
diff --git a/drivers/net/npe/include/IxPerfProfAcc.h b/drivers/net/npe/include/IxPerfProfAcc.h
deleted file mode 100644
index 2781ec851c..0000000000
--- a/drivers/net/npe/include/IxPerfProfAcc.h
+++ /dev/null
@@ -1,1334 +0,0 @@
-/**
- * @file IxPerfProfAcc.h
- *
- * @brief  Header file for the IXP400 Perf Prof component (IxPerfProfAcc)
- *
- * 
- * @par
- * IXP400 SW Release version 2.0
- * 
- * -- Copyright Notice --
- * 
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- * 
- * @par
- * SPDX-License-Identifier:	BSD-3-Clause
- * @par
- * -- End of Copyright Notice --
- */
-
-/**
- * @defgroup IxPerfProfAcc IXP400 Performance Profiling (IxPerfProfAcc) API 
- *
- * @brief IXP400 Performance Profiling Utility component Public API. 
- * @li NOTE: Xcycle measurement is not supported in Linux.
- *
- *
- * @{
- */
-#ifndef IXPERFPROFACC_H
-#define IXPERFPROFACC_H
-
-#include "IxOsal.h"
-
-#ifdef __linux
-#include <linux/proc_fs.h>
-#endif
-
-/*
- * Section for #define
- */
-/**
- * @ingroup IxPerfProfAcc
- *
- * @def IX_PERFPROF_ACC_XSCALE_PMU_MAX_PROFILE_SAMPLES
- *
- * @brief This is the maximum number of profiling samples allowed, which can be
- * modified according to the user's discretion
- */
-#define IX_PERFPROF_ACC_XSCALE_PMU_MAX_PROFILE_SAMPLES	0xFFFF
-
-/**
- * @ingroup IxPerfProfAcc
- *
- * @def IX_PERFPROF_ACC_BUS_PMU_MAX_PECS      
- *
- * @brief This is the maximum number of Programmable Event Counters available. 
- *        This is a hardware specific and fixed value. Do not change.
- *        
- */
-#define IX_PERFPROF_ACC_BUS_PMU_MAX_PECS        7
-
-/**  
- * @ingroup IxPerfProfAcc
- *
- * @def IX_PERFPROF_ACC_XCYCLE_MAX_NUM_OF_MEASUREMENTS
- *
- * @brief Max number of measurement allowed. This constant is used when 
- *        creating storage array for Xcycle. When run in continuous mode,  
- *        Xcycle will wrap around and re-use buffer. 
- */
-#define IX_PERFPROF_ACC_XCYCLE_MAX_NUM_OF_MEASUREMENTS 600
-
-#ifdef __linux
-/**
- * @ingroup IxPerfProfAcc
- *
- * @def IX_PERFPROF_ACC_XSCALE_PMU_SYMBOL_ACCURACY
- *
- * @brief Level of accuracy required for matching the PC Address to
- *        symbol address. This is used when the XScale PMU time/event
- *        sampling functions get the PC address and search for the 
- *        corresponding symbol address.
- */
-#define IX_PERFPROF_ACC_XSCALE_PMU_SYMBOL_ACCURACY 0xffff
-
-#endif /*__linux*/
-
-/**  
- * @ingroup IxPerfProfAcc
- *
- * @def IX_PERFPROF_ACC_LOG
- *
- * @brief Mechanism for logging a formatted message for the PerfProfAcc component
- *
- * @param level UINT32 [in] - trace level
- * @param device UINT32 [in] - output device
- * @param str char* [in] - format string, similar to printf().
- * @param a UINT32 [in] - first argument to display
- * @param b UINT32 [in] - second argument to display
- * @param c UINT32 [in] - third argument to display
- * @param d UINT32 [in] - fourth argument to display
- * @param e UINT32 [in] - fifth argument to display
- * @param f UINT32 [in] - sixth argument to display
- *
- * @return none
- */
-#ifndef NDEBUG
-#define IX_PERFPROF_ACC_LOG(level, device, str, a, b, c, d, e, f)\
-             (ixOsalLog (level, device, str, a, b, c, d, e, f))
-#else /*do nothing*/
-#define IX_PERFPROF_ACC_LOG(level, device, str, a, b, c, d, e, f) 
-#endif /*ifdef NDEBUG */
-
-/*
- * Section for struct
- */
-
-/**
- * @brief contains summary of samples taken 
- * 
- * Structure contains all details of each program counter value - frequency 
- * that PC occurs 
- */
-typedef struct
-{
-	UINT32 programCounter;  /**<the program counter value of the sample*/
-	UINT32 freq;		/**<the frequency of the occurence of the sample*/
-} IxPerfProfAccXscalePmuSamplePcProfile;
-
-/**
- * @brief contains results of a counter
- *
- * Structure contains the results of a counter, which are split into the lower 
- * and upper 32 bits of the final count
- */
-typedef struct
-{
-    UINT32 lower32BitsEventCount; /**<lower 32bits value of the event counter*/        
-    UINT32 upper32BitsEventCount; /**<upper 32bits value of the event counter*/
-}   IxPerfProfAccXscalePmuEvtCnt;
-
-/**
- * @brief contains results of counters and their overflow 
- * 
- * Structure contains all values of counters and associated overflows.  The 
- * specific event and clock counters are determined by the user
- */
-typedef struct
-{
-    UINT32 clk_value;           /**<current value of clock counter*/                 
-    UINT32 clk_samples;        /**<number of clock counter overflows*/
-    UINT32 event1_value;        /**<current value of event 1 counter*/    
-    UINT32 event1_samples;     /**<number of event 1 counter overflows*/
-    UINT32 event2_value;        /**<current value of event 2 counter*/
-    UINT32 event2_samples;     /**<number of event 2 counter overflows*/
-    UINT32 event3_value;        /**<current value of event 3 counter*/
-    UINT32 event3_samples;     /**<number of event 3 counter overflows*/
-    UINT32 event4_value;        /**<current value of event 4 counter*/
-    UINT32 event4_samples;     /**<number of event 4 counter overflows*/
-} IxPerfProfAccXscalePmuResults;
-
-/** 
- * 
- * @brief Results obtained from Xcycle run 
- */ 
-typedef struct 
-{
-    float maxIdlePercentage; 		/**<maximum percentage of Idle cycles*/
-    float minIdlePercentage; 		/**<minimum percentage of Idle cycles*/
-    float aveIdlePercentage;		/**<average percentage of Idle cycles*/
-    UINT32 totalMeasurements;		/**<total number of measurement made */
-} IxPerfProfAccXcycleResults; 
-
-/**
- *
- * @brief Results obtained from running the Bus Pmu component. The results
- *        are obtained when the get functions is called.
- *        
- */
-typedef struct
-{
-    UINT32 statsToGetLower27Bit[IX_PERFPROF_ACC_BUS_PMU_MAX_PECS]; /**<Lower 27 Bit of counter value */
-    UINT32 statsToGetUpper32Bit[IX_PERFPROF_ACC_BUS_PMU_MAX_PECS]; /**<Upper 32 Bit of counter value */
-} IxPerfProfAccBusPmuResults;
-
-/*
- * Section for enum
- */
-
-/**
- * @ingroup IxPerfProfAcc
- * 
- * @enum IxPerfProfAccBusPmuEventCounters1
- *
- * @brief Type of bus pmu events supported on PEC 1.
- *
- * Lists all bus pmu events.  
- */
-typedef enum
-{
-	IX_PERFPROF_ACC_BUS_PMU_PEC1_NORTH_NPEA_GRANT_SELECT = 1, /**< Select North NPEA grant on PEC1*/
-	IX_PERFPROF_ACC_BUS_PMU_PEC1_NORTH_NPEB_GRANT_SELECT, /**< Select North NPEB grant on PEC1*/
-	IX_PERFPROF_ACC_BUS_PMU_PEC1_NORTH_NPEC_GRANT_SELECT, /**< Select North NPEC grant on PEC1*/
-	IX_PERFPROF_ACC_BUS_PMU_PEC1_NORTH_BUS_IDLE_SELECT, /**< Select North bus idle on PEC1*/
-	IX_PERFPROF_ACC_BUS_PMU_PEC1_NORTH_NPEA_REQ_SELECT, /**< Select North NPEA req on PEC1*/
-	IX_PERFPROF_ACC_BUS_PMU_PEC1_NORTH_NPEB_REQ_SELECT, /**< Select North NPEB req on PEC1*/
-	IX_PERFPROF_ACC_BUS_PMU_PEC1_NORTH_NPEC_REQ_SELECT, /**< Select North NPEC req on PEC1*/
-
-	IX_PERFPROF_ACC_BUS_PMU_PEC1_SOUTH_GSKT_GRANT_SELECT, /**< Select south gasket grant on PEC1*/
-	IX_PERFPROF_ACC_BUS_PMU_PEC1_SOUTH_ABB_GRANT_SELECT, /**< Select south abb grant on PEC1*/
-	IX_PERFPROF_ACC_BUS_PMU_PEC1_SOUTH_PCI_GRANT_SELECT, /**< Select south pci grant on PEC1*/
-	IX_PERFPROF_ACC_BUS_PMU_PEC1_SOUTH_APB_GRANT_SELECT, /**< Select south apb grant on PEC1*/
-	IX_PERFPROF_ACC_BUS_PMU_PEC1_SOUTH_GSKT_REQ_SELECT, /**< Select south gasket request on PEC1*/
-	IX_PERFPROF_ACC_BUS_PMU_PEC1_SOUTH_ABB_REQ_SELECT, /**< Select south abb request on PEC1*/
-	IX_PERFPROF_ACC_BUS_PMU_PEC1_SOUTH_PCI_REQ_SELECT, /**< Select south pci request on PEC1*/
-	IX_PERFPROF_ACC_BUS_PMU_PEC1_SOUTH_APB_REQ_SELECT, /**< Select south apb request on PEC1*/
-
-	IX_PERFPROF_ACC_BUS_PMU_PEC1_SDR_0_HIT_SELECT, /**< Select sdram0 hit on PEC1*/
-	IX_PERFPROF_ACC_BUS_PMU_PEC1_SDR_1_HIT_SELECT, /**< Select sdram1 hit on PEC1*/
-	IX_PERFPROF_ACC_BUS_PMU_PEC1_SDR_2_HIT_SELECT, /**< Select sdram2 hit on PEC1*/
-	IX_PERFPROF_ACC_BUS_PMU_PEC1_SDR_3_HIT_SELECT, /**< Select sdram3 hit on PEC1*/
-	IX_PERFPROF_ACC_BUS_PMU_PEC1_SDR_4_MISS_SELECT, /**< Select sdram4 miss on PEC1*/
-	IX_PERFPROF_ACC_BUS_PMU_PEC1_SDR_5_MISS_SELECT, /**< Select sdram5 miss on PEC1*/
-	IX_PERFPROF_ACC_BUS_PMU_PEC1_SDR_6_MISS_SELECT, /**< Select sdram6 miss on PEC1*/
-	IX_PERFPROF_ACC_BUS_PMU_PEC1_SDR_7_MISS_SELECT /**< Select sdram7 miss on PEC1*/
-} IxPerfProfAccBusPmuEventCounters1;
-
-/**
- * @ingroup IxPerfProfAcc
- *
- * @enum IxPerfProfAccBusPmuEventCounters2
- *
- * @brief Type of bus pmu events supported on PEC 2.
- *
- * Lists all bus pmu events.
- */
-typedef enum
-{
-	IX_PERFPROF_ACC_BUS_PMU_PEC2_NORTH_NPEA_XFER_SELECT = 24, /**< Select North NPEA transfer on PEC2*/
-	IX_PERFPROF_ACC_BUS_PMU_PEC2_NORTH_NPEB_XFER_SELECT, /**< Select North NPEB transfer on PEC2*/
-	IX_PERFPROF_ACC_BUS_PMU_PEC2_NORTH_NPEC_XFER_SELECT, /**< Select North NPEC transfer on PEC2*/
-	IX_PERFPROF_ACC_BUS_PMU_PEC2_NORTH_BUS_WRITE_SELECT, /**< Select North bus write on PEC2*/
-	IX_PERFPROF_ACC_BUS_PMU_PEC2_NORTH_NPEA_OWN_SELECT, /**< Select North NPEA own on PEC2*/
-	IX_PERFPROF_ACC_BUS_PMU_PEC2_NORTH_NPEB_OWN_SELECT, /**< Select North NPEB own on PEC2*/
-	IX_PERFPROF_ACC_BUS_PMU_PEC2_NORTH_NPEC_OWN_SELECT, /**< Select North NPEC own on PEC2*/
-
-	IX_PERFPROF_ACC_BUS_PMU_PEC2_SOUTH_GSKT_XFER_SELECT, /**< Select South gasket transfer on PEC2*/
-	IX_PERFPROF_ACC_BUS_PMU_PEC2_SOUTH_ABB_XFER_SELECT, /**< Select South abb transfer on PEC2*/
-	IX_PERFPROF_ACC_BUS_PMU_PEC2_SOUTH_PCI_XFER_SELECT, /**< Select South pci transfer on PEC2*/
-	IX_PERFPROF_ACC_BUS_PMU_PEC2_SOUTH_APB_XFER_SELECT, /**< Select South apb transfer on PEC2*/
-	IX_PERFPROF_ACC_BUS_PMU_PEC2_SOUTH_GSKT_OWN_SELECT, /**< Select South gasket own on PEC2*/
-	IX_PERFPROF_ACC_BUS_PMU_PEC2_SOUTH_ABB_OWN_SELECT, /**< Select South abb own on PEC2*/
-	IX_PERFPROF_ACC_BUS_PMU_PEC2_SOUTH_PCI_OWN_SELECT, /**< Select South pci own on PEC2*/
-	IX_PERFPROF_ACC_BUS_PMU_PEC2_SOUTH_APB_OWN_SELECT, /**< Select South apb own transfer on PEC2*/
-
-	IX_PERFPROF_ACC_BUS_PMU_PEC2_SDR_1_HIT_SELECT, /**< Select sdram1 hit on PEC2*/
-	IX_PERFPROF_ACC_BUS_PMU_PEC2_SDR_2_HIT_SELECT, /**< Select sdram2 hit on PEC2*/
-	IX_PERFPROF_ACC_BUS_PMU_PEC2_SDR_3_HIT_SELECT, /**< Select sdram3 hit on PEC2*/
-	IX_PERFPROF_ACC_BUS_PMU_PEC2_SDR_4_HIT_SELECT, /**< Select sdram4 hit on PEC2*/
-	IX_PERFPROF_ACC_BUS_PMU_PEC2_SDR_5_MISS_SELECT, /**< Select sdram5 miss on PEC2*/
-	IX_PERFPROF_ACC_BUS_PMU_PEC2_SDR_6_MISS_SELECT, /**< Select sdram6 miss on PEC2*/
-	IX_PERFPROF_ACC_BUS_PMU_PEC2_SDR_7_MISS_SELECT, /**< Select sdram7 miss on PEC2*/
-	IX_PERFPROF_ACC_BUS_PMU_PEC2_SDR_0_MISS_SELECT /**< Select sdram0 miss on PEC2*/
-} IxPerfProfAccBusPmuEventCounters2;
-
-/**
- * @ingroup IxPerfProfAcc
- *
- * @enum IxPerfProfAccBusPmuEventCounters3
- *
- * @brief Type of bus pmu events supported on PEC 3.
- *
- * Lists all bus pmu events.
- */
-typedef enum
-{
-	IX_PERFPROF_ACC_BUS_PMU_PEC3_NORTH_NPEA_RETRY_SELECT = 47, /**< Select north NPEA retry on PEC3*/
-	IX_PERFPROF_ACC_BUS_PMU_PEC3_NORTH_NPEB_RETRY_SELECT, /**< Select north NPEB retry on PEC3*/
-	IX_PERFPROF_ACC_BUS_PMU_PEC3_NORTH_NPEC_RETRY_SELECT, /**< Select north NPEC retry on PEC3*/
-	IX_PERFPROF_ACC_BUS_PMU_PEC3_NORTH_BUS_READ_SELECT, /**< Select north bus read on PEC3*/
-	IX_PERFPROF_ACC_BUS_PMU_PEC3_NORTH_NPEA_WRITE_SELECT, /**< Select north NPEA write on PEC3*/
-	IX_PERFPROF_ACC_BUS_PMU_PEC3_NORTH_NPEB_WRITE_SELECT, /**< Select north NPEB write on PEC3*/
-	IX_PERFPROF_ACC_BUS_PMU_PEC3_NORTH_NPEC_WRITE_SELECT, /**< Select north NPEC wirte on PEC3*/
-
-	IX_PERFPROF_ACC_BUS_PMU_PEC3_SOUTH_GSKT_RETRY_SELECT, /**< Select south gasket retry on PEC3*/
-	IX_PERFPROF_ACC_BUS_PMU_PEC3_SOUTH_ABB_RETRY_SELECT, /**< Select south abb retry on PEC3*/
-	IX_PERFPROF_ACC_BUS_PMU_PEC3_SOUTH_PCI_RETRY_SELECT, /**< Select south pci retry on PEC3*/
-	IX_PERFPROF_ACC_BUS_PMU_PEC3_SOUTH_APB_RETRY_SELECT, /**< Select south apb retry on PEC3*/
- 	IX_PERFPROF_ACC_BUS_PMU_PEC3_SOUTH_GSKT_WRITE_SELECT, /**< Select south gasket write on PEC3*/
- 	IX_PERFPROF_ACC_BUS_PMU_PEC3_SOUTH_ABB_WRITE_SELECT, /**< Select south abb write on PEC3*/
- 	IX_PERFPROF_ACC_BUS_PMU_PEC3_SOUTH_PCI_WRITE_SELECT, /**< Select south pci write on PEC3*/
- 	IX_PERFPROF_ACC_BUS_PMU_PEC3_SOUTH_APB_WRITE_SELECT, /**< Select south apb write on PEC3*/
-
- 	IX_PERFPROF_ACC_BUS_PMU_PEC3_SDR_2_HIT_SELECT, /**< Select sdram2 hit on PEC3*/
- 	IX_PERFPROF_ACC_BUS_PMU_PEC3_SDR_3_HIT_SELECT, /**< Select sdram3 hit on PEC3*/
- 	IX_PERFPROF_ACC_BUS_PMU_PEC3_SDR_4_HIT_SELECT, /**< Select sdram4 hit on PEC3*/
- 	IX_PERFPROF_ACC_BUS_PMU_PEC3_SDR_5_HIT_SELECT, /**< Select sdram5 hit on PEC3*/
- 	IX_PERFPROF_ACC_BUS_PMU_PEC3_SDR_6_MISS_SELECT, /**< Select sdram6 miss on PEC3*/
- 	IX_PERFPROF_ACC_BUS_PMU_PEC3_SDR_7_MISS_SELECT, /**< Select sdram7 miss on PEC3*/
- 	IX_PERFPROF_ACC_BUS_PMU_PEC3_SDR_0_MISS_SELECT, /**< Select sdram0 miss on PEC3*/
- 	IX_PERFPROF_ACC_BUS_PMU_PEC3_SDR_1_MISS_SELECT /**< Select sdram1 miss on PEC3*/
-} IxPerfProfAccBusPmuEventCounters3;
-
-/**
- * @ingroup IxPerfProfAcc
- *
- * @enum IxPerfProfAccBusPmuEventCounters4
- *
- * @brief Type of bus pmu events supported on PEC 4.
- *
- * Lists all bus pmu events.
- */
-typedef enum
-{
- 	IX_PERFPROF_ACC_BUS_PMU_PEC4_SOUTH_PCI_SPLIT_SELECT = 70, /**< Select south pci split on PEC4*/
- 	IX_PERFPROF_ACC_BUS_PMU_PEC4_SOUTH_EXP_SPLIT_SELECT, /**< Select south expansion split on PEC4*/
- 	IX_PERFPROF_ACC_BUS_PMU_PEC4_SOUTH_APB_GRANT_SELECT, /**< Select south apb grant on PEC4*/
- 	IX_PERFPROF_ACC_BUS_PMU_PEC4_SOUTH_APB_XFER_SELECT, /**< Select south apb transfer on PEC4*/
- 	IX_PERFPROF_ACC_BUS_PMU_PEC4_SOUTH_GSKT_READ_SELECT, /**< Select south gasket read on PEC4*/
- 	IX_PERFPROF_ACC_BUS_PMU_PEC4_SOUTH_ABB_READ_SELECT, /**< Select south abb read on PEC4*/
- 	IX_PERFPROF_ACC_BUS_PMU_PEC4_SOUTH_PCI_READ_SELECT, /**< Select south pci read on PEC4*/
- 	IX_PERFPROF_ACC_BUS_PMU_PEC4_SOUTH_APB_READ_SELECT, /**< Select south apb read on PEC4*/
-
- 	IX_PERFPROF_ACC_BUS_PMU_PEC4_NORTH_ABB_SPLIT_SELECT, /**< Select north abb split on PEC4*/
- 	IX_PERFPROF_ACC_BUS_PMU_PEC4_NORTH_NPEA_REQ_SELECT, /**< Select north NPEA req on PEC4*/
- 	IX_PERFPROF_ACC_BUS_PMU_PEC4_NORTH_NPEA_READ_SELECT, /**< Select north NPEA read on PEC4*/
- 	IX_PERFPROF_ACC_BUS_PMU_PEC4_NORTH_NPEB_READ_SELECT, /**< Select north NPEB read on PEC4*/
- 	IX_PERFPROF_ACC_BUS_PMU_PEC4_NORTH_NPEC_READ_SELECT, /**< Select north NPEC read on PEC4*/
-
- 	IX_PERFPROF_ACC_BUS_PMU_PEC4_SDR_3_HIT_SELECT, /**< Select sdram3 hit on PEC4*/
- 	IX_PERFPROF_ACC_BUS_PMU_PEC4_SDR_4_HIT_SELECT, /**< Select sdram4 hit on PEC4*/
- 	IX_PERFPROF_ACC_BUS_PMU_PEC4_SDR_5_HIT_SELECT, /**< Select sdram5 hit on PEC4*/
- 	IX_PERFPROF_ACC_BUS_PMU_PEC4_SDR_6_HIT_SELECT, /**< Select sdram6 hit on PEC4*/
- 	IX_PERFPROF_ACC_BUS_PMU_PEC4_SDR_7_MISS_SELECT, /**< Select sdram7 miss on PEC4*/
- 	IX_PERFPROF_ACC_BUS_PMU_PEC4_SDR_0_MISS_SELECT, /**< Select sdram0 miss on PEC4*/
- 	IX_PERFPROF_ACC_BUS_PMU_PEC4_SDR_1_MISS_SELECT, /**< Select sdram1 miss on PEC4*/
- 	IX_PERFPROF_ACC_BUS_PMU_PEC4_SDR_2_MISS_SELECT /**< Select sdram2 miss on PEC4*/
-} IxPerfProfAccBusPmuEventCounters4;
-
-/**
- * @ingroup IxPerfProfAcc
- *
- * @enum IxPerfProfAccBusPmuEventCounters5
- *
- * @brief Type of bus pmu events supported on PEC 5.
- *
- * Lists all bus pmu events.
- */
-typedef enum
-{
- 	IX_PERFPROF_ACC_BUS_PMU_PEC5_SOUTH_ABB_GRANT_SELECT = 91, /**< Select south abb grant on PEC5*/
- 	IX_PERFPROF_ACC_BUS_PMU_PEC5_SOUTH_ABB_XFER_SELECT, /**< Select south abb transfer on PEC5*/
- 	IX_PERFPROF_ACC_BUS_PMU_PEC5_SOUTH_ABB_RETRY_SELECT, /**< Select south abb retry on PEC5*/
- 	IX_PERFPROF_ACC_BUS_PMU_PEC5_SOUTH_EXP_SPLIT_SELECT, /**< Select south expansion split on PEC5*/
- 	IX_PERFPROF_ACC_BUS_PMU_PEC5_SOUTH_ABB_REQ_SELECT, /**< Select south abb request on PEC5*/
- 	IX_PERFPROF_ACC_BUS_PMU_PEC5_SOUTH_ABB_OWN_SELECT, /**< Select south abb own on PEC5*/
- 	IX_PERFPROF_ACC_BUS_PMU_PEC5_SOUTH_BUS_IDLE_SELECT, /**< Select south bus idle on PEC5*/
-
- 	IX_PERFPROF_ACC_BUS_PMU_PEC5_NORTH_NPEB_GRANT_SELECT, /**< Select north NPEB grant on PEC5*/
- 	IX_PERFPROF_ACC_BUS_PMU_PEC5_NORTH_NPEB_XFER_SELECT, /**< Select north NPEB transfer on PEC5*/
- 	IX_PERFPROF_ACC_BUS_PMU_PEC5_NORTH_NPEB_RETRY_SELECT, /**< Select north NPEB retry on PEC5*/
- 	IX_PERFPROF_ACC_BUS_PMU_PEC5_NORTH_NPEB_REQ_SELECT, /**< Select north NPEB request on PEC5*/
- 	IX_PERFPROF_ACC_BUS_PMU_PEC5_NORTH_NPEB_OWN_SELECT, /**< Select north NPEB own on PEC5*/
- 	IX_PERFPROF_ACC_BUS_PMU_PEC5_NORTH_NPEB_WRITE_SELECT, /**< Select north NPEB write on PEC5*/
- 	IX_PERFPROF_ACC_BUS_PMU_PEC5_NORTH_NPEB_READ_SELECT, /**< Select north NPEB read on PEC5*/
-
- 	IX_PERFPROF_ACC_BUS_PMU_PEC5_SDR_4_HIT_SELECT, /**< Select north sdram4 hit on PEC5*/
- 	IX_PERFPROF_ACC_BUS_PMU_PEC5_SDR_5_HIT_SELECT, /**< Select north sdram5 hit on PEC5*/
- 	IX_PERFPROF_ACC_BUS_PMU_PEC5_SDR_6_HIT_SELECT, /**< Select north sdram6 hit on PEC5*/
- 	IX_PERFPROF_ACC_BUS_PMU_PEC5_SDR_7_HIT_SELECT, /**< Select north sdram7 hit on PEC5*/
- 	IX_PERFPROF_ACC_BUS_PMU_PEC5_SDR_0_MISS_SELECT, /**< Select north sdram0 miss on PEC5*/
- 	IX_PERFPROF_ACC_BUS_PMU_PEC5_SDR_1_MISS_SELECT, /**< Select north sdram1 miss on PEC5*/
- 	IX_PERFPROF_ACC_BUS_PMU_PEC5_SDR_2_MISS_SELECT, /**< Select north sdram2 miss on PEC5*/
- 	IX_PERFPROF_ACC_BUS_PMU_PEC5_SDR_3_MISS_SELECT /**< Select north sdram3 miss on PEC5*/
-} IxPerfProfAccBusPmuEventCounters5;
-
-/**
- * @ingroup IxPerfProfAcc
- *
- * @enum IxPerfProfAccBusPmuEventCounters6
- *
- * @brief Type of bus pmu events supported on PEC 6.
- *
- * Lists all bus pmu events.
- */
-typedef enum
-{
-	IX_PERFPROF_ACC_BUS_PMU_PEC6_SOUTH_PCI_GRANT_SELECT = 113, /**< Select south pci grant on PEC6*/
- 	IX_PERFPROF_ACC_BUS_PMU_PEC6_SOUTH_PCI_XFER_SELECT, /**< Select south pci transfer on PEC6*/
- 	IX_PERFPROF_ACC_BUS_PMU_PEC6_SOUTH_PCI_RETRY_SELECT, /**< Select south pci retry on PEC6*/
- 	IX_PERFPROF_ACC_BUS_PMU_PEC6_SOUTH_PCI_SPLIT_SELECT, /**< Select south pci split on PEC6*/
- 	IX_PERFPROF_ACC_BUS_PMU_PEC6_SOUTH_PCI_REQ_SELECT, /**< Select south pci request on PEC6*/
- 	IX_PERFPROF_ACC_BUS_PMU_PEC6_SOUTH_PCI_OWN_SELECT, /**< Select south pci own on PEC6*/
- 	IX_PERFPROF_ACC_BUS_PMU_PEC6_SOUTH_BUS_WRITE_SELECT, /**< Select south pci write on PEC6*/
-
- 	IX_PERFPROF_ACC_BUS_PMU_PEC6_NORTH_NPEC_GRANT_SELECT, /**< Select north NPEC grant on PEC6*/
- 	IX_PERFPROF_ACC_BUS_PMU_PEC6_NORTH_NPEC_XFER_SELECT, /**< Select north NPEC transfer on PEC6*/
- 	IX_PERFPROF_ACC_BUS_PMU_PEC6_NORTH_NPEC_RETRY_SELECT, /**< Select north NPEC retry on PEC6*/
- 	IX_PERFPROF_ACC_BUS_PMU_PEC6_NORTH_NPEC_REQ_SELECT, /**< Select north NPEC request on PEC6*/
- 	IX_PERFPROF_ACC_BUS_PMU_PEC6_NORTH_NPEC_OWN_SELECT, /**< Select north NPEC own on PEC6*/
- 	IX_PERFPROF_ACC_BUS_PMU_PEC6_NORTH_NPEB_WRITE_SELECT, /**< Select north NPEB write on PEC6*/
- 	IX_PERFPROF_ACC_BUS_PMU_PEC6_NORTH_NPEC_READ_SELECT, /**< Select north NPEC read on PEC6*/
-
- 	IX_PERFPROF_ACC_BUS_PMU_PEC6_SDR_5_HIT_SELECT, /**< Select sdram5 hit on PEC6*/
- 	IX_PERFPROF_ACC_BUS_PMU_PEC6_SDR_6_HIT_SELECT, /**< Select sdram6 hit on PEC6*/
- 	IX_PERFPROF_ACC_BUS_PMU_PEC6_SDR_7_HIT_SELECT, /**< Select sdram7 hit on PEC6*/
- 	IX_PERFPROF_ACC_BUS_PMU_PEC6_SDR_0_HIT_SELECT, /**< Select sdram0 hit on PEC6*/
- 	IX_PERFPROF_ACC_BUS_PMU_PEC6_SDR_1_MISS_SELECT, /**< Select sdram1 miss on PEC6*/
- 	IX_PERFPROF_ACC_BUS_PMU_PEC6_SDR_2_MISS_SELECT, /**< Select sdram2 miss on PEC6*/
- 	IX_PERFPROF_ACC_BUS_PMU_PEC6_SDR_3_MISS_SELECT, /**< Select sdram3 miss on PEC6*/
- 	IX_PERFPROF_ACC_BUS_PMU_PEC6_SDR_4_MISS_SELECT /**< Select sdram4 miss on PEC6*/
-} IxPerfProfAccBusPmuEventCounters6;
-
-/**
- * @ingroup IxPerfProfAcc
- *
- * @enum IxPerfProfAccBusPmuEventCounters7
- *
- * @brief Type of bus pmu events supported on PEC 7.
- *
- * Lists all bus pmu events.
- */
-typedef enum
-{
- 	IX_PERFPROF_ACC_BUS_PMU_PEC7_SOUTH_APB_RETRY_SELECT = 135, /**< Select south apb retry on PEC7*/
- 	IX_PERFPROF_ACC_BUS_PMU_PEC7_SOUTH_APB_REQ_SELECT, /**< Select south apb request on PEC7*/
- 	IX_PERFPROF_ACC_BUS_PMU_PEC7_SOUTH_APB_OWN_SELECT, /**< Select south apb own on PEC7*/
- 	IX_PERFPROF_ACC_BUS_PMU_PEC7_SOUTH_BUS_READ_SELECT, /**< Select south bus read on PEC7*/
- 	IX_PERFPROF_ACC_BUS_PMU_PEC7_CYCLE_COUNT_SELECT /**< Select cycle count on PEC7*/
-} IxPerfProfAccBusPmuEventCounters7;
-
-/** 
- * @ingroup IxPerfProfAcc 
- * 
- * @enum IxPerfProfAccXscalePmuEvent 
- * 
- * @brief Type of xscale pmu events supported 
- * 
- * Lists all xscale pmu events.  The maximum is a default value that the user 
- * should not exceed. 
- */ 
-typedef enum 
-{
-    IX_PERFPROF_ACC_XSCALE_PMU_EVENT_CACHE_MISS=0,      /**< cache miss*/ 
-    IX_PERFPROF_ACC_XSCALE_PMU_EVENT_CACHE_INSTRUCTION,/**< cache instruction*/ 
-    IX_PERFPROF_ACC_XSCALE_PMU_EVENT_STALL,     /**< event stall*/ 
-    IX_PERFPROF_ACC_XSCALE_PMU_EVENT_INST_TLB_MISS, /**< instruction tlb miss*/ 
-    IX_PERFPROF_ACC_XSCALE_PMU_EVENT_DATA_TLB_MISS, /**< data tlb miss*/ 
-    IX_PERFPROF_ACC_XSCALE_PMU_EVENT_BRANCH_EXEC,   /**< branch executed*/ 
-    IX_PERFPROF_ACC_XSCALE_PMU_EVENT_BRANCH_MISPREDICT, /**<branch mispredict*/ 
-    IX_PERFPROF_ACC_XSCALE_PMU_EVENT_INST_EXEC, /**< instruction executed*/ 
-    IX_PERFPROF_ACC_XSCALE_PMU_EVENT_FULL_EVERYCYCLE,   /**< 
-                                                         *Stall - data cache 
-                                                         *buffers are full. 
-							 							 *This event occurs 
-							 							 *every cycle where 
-							 							 *condition present 
-							 							 */ 
-    IX_PERFPROF_ACC_XSCALE_PMU_EVENT_ONCE,    /**< 
-                                               *Stall - data cache buffers are 
-					       					   *full.This event occurs once 
-					       					   *for each contiguous sequence 
-					       					   */ 
-    IX_PERFPROF_ACC_XSCALE_PMU_EVENT_DATA_CACHE_ACCESS, /**< data cache access*/ 
-    IX_PERFPROF_ACC_XSCALE_PMU_EVENT_DATA_CACHE_MISS,   /**< data cache miss*/ 
-    IX_PERFPROF_ACC_XSCALE_PMU_EVENT_DATA_CACHE_WRITEBACK,  /**<data cache 
-                                                             *writeback 
-						             						 */ 
-    IX_PERFPROF_ACC_XSCALE_PMU_EVENT_SW_CHANGE_PC,  /**< sw change pc*/ 
-    IX_PERFPROF_ACC_XSCALE_PMU_EVENT_MAX    /**< max value*/ 
-} IxPerfProfAccXscalePmuEvent;
-
-/**
- * @ingroup IxPerfProfAcc
- *
- * @enum IxPerfProfAccStatus
- *
- * @brief Invalid Status Definitions  
- *
- * These status will be used by the APIs to return to the user.
- */
-typedef enum
-{
-	IX_PERFPROF_ACC_STATUS_SUCCESS = IX_SUCCESS,    /**< success*/
-	IX_PERFPROF_ACC_STATUS_FAIL = IX_FAIL,          /**< fail*/
-	IX_PERFPROF_ACC_STATUS_ANOTHER_UTIL_IN_PROGRESS,/**<another utility in 
-													 *progress
-													 */ 
-	IX_PERFPROF_ACC_STATUS_XCYCLE_MEASUREMENT_IN_PROGRESS, /**<measurement in
-															*progress
-															*/
-	IX_PERFPROF_ACC_STATUS_XCYCLE_NO_BASELINE, /**<no baseline yet*/	 
-	IX_PERFPROF_ACC_STATUS_XCYCLE_MEASUREMENT_REQUEST_OUT_OF_RANGE, /**< 
-															* Measurement chosen 
-															* is out of range
-															*/
-	IX_PERFPROF_ACC_STATUS_XCYCLE_PRIORITY_SET_FAIL,  /**<
-	                                                     * Cannot set 
-														 * task priority
-	                                                     */
-	IX_PERFPROF_ACC_STATUS_XCYCLE_THREAD_CREATE_FAIL, /**< 
-	                                                     * Fail create thread
-	                                                     */
-	IX_PERFPROF_ACC_STATUS_XCYCLE_PRIORITY_RESTORE_FAIL,  /**<
-	                                                         *cannot restore
-	                                                         *priority
-	                                                         */
-	IX_PERFPROF_ACC_STATUS_XCYCLE_MEASUREMENT_NOT_RUNNING, /**< xcycle not running*/
-   	IX_PERFPROF_ACC_STATUS_XSCALE_PMU_NUM_INVALID, /**< invalid number 
-   	                                                *entered
-   	                                                */
-	IX_PERFPROF_ACC_STATUS_XSCALE_PMU_EVENT_INVALID, /**< invalid pmu event*/
-	IX_PERFPROF_ACC_STATUS_XSCALE_PMU_START_NOT_CALLED, /**<a start process
-							     						 *was not called 
-							     						 *before attempting
-							     						 *a stop or results
-							     						 *get
-							     						 */
-	IX_PERFPROF_ACC_STATUS_BUS_PMU_MODE_ERROR,  /**< invalid mode*/
-	IX_PERFPROF_ACC_STATUS_BUS_PMU_PEC1_ERROR,	/**< invalid pec1 entered*/
-	IX_PERFPROF_ACC_STATUS_BUS_PMU_PEC2_ERROR,	/**< invalid pec2 entered*/
-	IX_PERFPROF_ACC_STATUS_BUS_PMU_PEC3_ERROR,	/**< invalid pec3 entered*/
-	IX_PERFPROF_ACC_STATUS_BUS_PMU_PEC4_ERROR,	/**< invalid pec4 entered*/
-	IX_PERFPROF_ACC_STATUS_BUS_PMU_PEC5_ERROR,	/**< invalid pec5 entered*/
-	IX_PERFPROF_ACC_STATUS_BUS_PMU_PEC6_ERROR,	/**< invalid pec6 entered*/
-	IX_PERFPROF_ACC_STATUS_BUS_PMU_PEC7_ERROR,	/**< invalid pec7 entered*/
-	IX_PERFPROF_ACC_STATUS_BUS_PMU_START_NOT_CALLED, /**<a start process
-							     					 *was not called 
-							     					 *before attempting
-							     					 *a stop 
-													 */
-        IX_PERFPROF_ACC_STATUS_COMPONENT_NOT_SUPPORTED /**<Device or OS does not support component*/
-} IxPerfProfAccStatus;
-
-/**
- * @ingroup IxPerfProfAcc 
- * 
- * @enum IxPerfProfAccBusPmuMode
- *
- * @brief State selection of counters.
- *
- * These states will be used to determine the counters whose values are to be
- * read.
- */
-typedef enum
-{
-        IX_PERFPROF_ACC_BUS_PMU_MODE_HALT=0,   /**< halt state*/
-        IX_PERFPROF_ACC_BUS_PMU_MODE_SOUTH,    /**< south state*/
-        IX_PERFPROF_ACC_BUS_PMU_MODE_NORTH,    /**< north state*/
-        IX_PERFPROF_ACC_BUS_PMU_MODE_SDRAM    /**< SDRAM state*/
-} IxPerfProfAccBusPmuMode;
-
-/*
- * Section for prototypes interface functions
- */
-
-/**
- * @ingroup IxPerfProfAcc
- *
- * @fn ixPerfProfAccXscalePmuEventCountStart(
-   		BOOL clkCntDiv,
-   		UINT32 numEvents,
-  	 	IxPerfProfAccXscalePmuEvent pmuEvent1,
-   		IxPerfProfAccXscalePmuEvent pmuEvent2,
-   		IxPerfProfAccXscalePmuEvent pmuEvent3,
-   		IxPerfProfAccXscalePmuEvent pmuEvent4 )
- *
- * @brief This API will start the clock and event counting
- *
- * @param	clkCntDiv BOOL [in] - enables/disables the clock divider. When 
- *			true, the divider is enabled and the clock count will be incremented
- *          by one at each 64th processor clock cycle.  When false, the divider
- *			is disabled and the clock count will be incremented at every 
- *			processor clock cycle.
- * @param 	numEvents UINT32 [in] - the number of PMU events that are to be 
- *	  		monitored as specified by the user. For clock counting only, this
- *	  	 	is set to zero.
- * @param 	pmuEvent1 @ref IxPerfProfAccXscalePmuEvent [in] - the specific PMU 
- *    		event to be monitored by counter 1
- * @param 	pmuEvent2 @ref IxPerfProfAccXscalePmuEvent [in] - the specific PMU 
- *    		event to be monitored by counter 2 
- * @param	pmuEvent3 @ref IxPerfProfAccXscalePmuEvent [in] - the specific PMU 
- *    		event to be monitored by counter 3
- * @param 	pmuEvent4 @ref IxPerfProfAccXscalePmuEvent [in] - the specific PMU 
- *    		event to be monitored by counter 4
- *
- * This API will start the clock and xscale PMU event counting.  Up to 
- * 4 events can be monitored simultaneously. This API has to be called before
- * ixPerfProfAccXscalePmuEventCountStop can be called.
- *
- * @return 
- *	- IX_PERFPROF_ACC_STATUS_SUCCESS if clock and events counting are 
- *        started successfully
- *	- IX_PERFPROF_ACC_STATUS_FAIL if unable to start the counting
- *	- IX_PERFPROF_ACC_STATUS_XSCALE_PMU_NUM_INVALID if the number of events 
- *        specified is out of the valid range
- *	- IX_PERFPROF_ACC_STATUS_XSCALE_PMU_EVENT_INVALID if the value of the PMU 
- * 	  event specified does not exist
- * 	- IX_PERFPROF_ACC_STATUS_ANOTHER_UTIL_IN_PROGRESS - another utility is 
- * 	  running 
- *              
- * @li   Reentrant    : no
- * @li   ISR Callable : no
- *
- */
-PUBLIC IxPerfProfAccStatus
-ixPerfProfAccXscalePmuEventCountStart(
-	BOOL clkCntDiv,
-	UINT32 numEvents,
-	IxPerfProfAccXscalePmuEvent pmuEvent1,
-	IxPerfProfAccXscalePmuEvent pmuEvent2,
-	IxPerfProfAccXscalePmuEvent pmuEvent3,
-	IxPerfProfAccXscalePmuEvent pmuEvent4 );
-
-/**
- * @ingroup IxPerfProfAcc
- *
- * @fn ixPerfProfAccXscalePmuEventCountStop (
-   IxPerfProfAccXscalePmuResults *eventCountStopResults) 
- *
- * @brief This API will stop the clock and event counting
- *
- * @param *eventCountStopResults @ref IxPerfProfAccXscalePmuResults [out] - pointer 
- *		  to struct containing results of counters and their overflow. It is the 
- * 		  users's responsibility to allocate the memory for this pointer. 
- *
- * This API will stop the clock and xscale PMU events that are being counted.
- * The results of the clock and events count will be stored in the pointer 
- * allocated by the user. It can only be called once 
- * IxPerfProfAccEventCountStart has been called. 
- *
- * @return 
- *      - IX_PERFPROF_ACC_STATUS_SUCCESS if clock and events counting are 
- *        stopped successfully
- *      - IX_PERFPROF_ACC_STATUS_XSCALE_PMU_START_NOT_CALLED if
- *        ixPerfProfAccXscalePmuEventCountStart is not called first.
- *              
- * @li   Reentrant    : no
- * @li   ISR Callable : no
- *
- */
-
-PUBLIC IxPerfProfAccStatus 
-ixPerfProfAccXscalePmuEventCountStop(
-   IxPerfProfAccXscalePmuResults *eventCountStopResults); 
-
-/**
- * @ingroup IxPerfProfAcc
- *
- * @fn ixPerfProfAccXscalePmuTimeSampStart(
-   UINT32 samplingRate,
-   BOOL clkCntDiv) 
- *
- * @brief Starts the time based sampling
- *
- * @param	samplingRate UINT32 [in] - sampling rate is the number of
- *       	clock counts before a counter overflow interrupt is generated,
- *        	at which, a sample is taken; the rate specified cannot be greater
- *          than the counter size of 32bits or set to zero.
- * @param 	clkCntDiv BOOL [in] - enables/disables the clock divider. When 
- *		true, the divider is enabled and the clock count will be incremented
- *          by one at each 64th processor clock cycle.  When false, the divider
- *			is disabled and the clock count will be incremented at every 
- *			processor clock cycle. 
- *
- * This API starts the time based sampling to determine the frequency with 
- * which lines of code are being executed.  Sampling is done at the rate 
- * specified by the user.  At each sample,the value of the program counter
- * is determined.  Each of these occurrences are recorded to determine the 
- * frequency with which the Xscale code is being executed. This API has to be 
- * called before ixPerfProfAccXscalePmuTimeSampStop can be called.
- *
- * @return
- *	- IX_PERFPROF_ACC_STATUS_SUCCESS if time based sampling is started 
- *        successfully
- *	- IX_PERFPROF_ACC_STATUS_FAIL if unable to start the sampling
- * 	- IX_PERFPROF_ACC_STATUS_ANOTHER_UTIL_IN_PROGRESS - another utility is 
- *	  running 
- *              
- * @li   Reentrant    : no
- * @li   ISR Callable : no
- *
- */
-PUBLIC IxPerfProfAccStatus 
-ixPerfProfAccXscalePmuTimeSampStart(
-	UINT32 samplingRate, 
-	BOOL clkCntDiv);
-
-/**
- * @ingroup IxPerfProfAcc
- *
- * @fn ixPerfProfAccXscalePmuTimeSampStop(
-   IxPerfProfAccXscalePmuEvtCnt *clkCount,
-   IxPerfProfAccXscalePmuSamplePcProfile *timeProfile)
- *
- * @brief Stops the time based sampling
- *
- * @param	*clkCount @ref IxPerfProfAccXscalePmuEvtCnt [out]  - pointer to the 
- *			struct containing the final clock count and its overflow.  It is the
- *			user's responsibility to allocate the memory for this pointer.
- * @param 	*timeProfile @ref IxPerfProfAccXscalePmuSamplePcProfile [out] -
- *          pointer to the array of profiles for each program counter value;
- *          the user should set the size of the array to 
- *			IX_PERFPROF_ACC_XSCALE_PMU_MAX_PROFILE_SAMPLES.  It is the user's 
- * 			responsibility to allocate the memory for this pointer.
- *
- * This API stops the time based sampling.  The results are stored in the 
- * pointers allocated by the user.  It can only be called once
- * ixPerfProfAccXscalePmuTimeSampStart has been called.
- *
- * @return
- *	- IX_PERFPROF_ACC_STATUS_SUCCESS if time based sampling is stopped 
- *        successfully
- *	- IX_PERFPROF_ACC_STATUS_XSCALE_PMU_START_NOT_CALLED if
- *	  ixPerfProfAccXscalePmuTimeSampStart not called first
- *              
- * @li   Reentrant    : no
- * @li   ISR Callable : no
- *
- */
-PUBLIC IxPerfProfAccStatus
-ixPerfProfAccXscalePmuTimeSampStop(
-	IxPerfProfAccXscalePmuEvtCnt *clkCount,
-	IxPerfProfAccXscalePmuSamplePcProfile *timeProfile);
-
-/**
- * @ingroup IxPerfProfAcc
- *
- * @fn ixPerfProfAccXscalePmuEventSampStart(
-   UINT32 numEvents,
-   IxPerfProfAccXscalePmuEvent pmuEvent1,
-   UINT32 eventRate1,
-   IxPerfProfAccXscalePmuEvent pmuEvent2,
-   UINT32 eventRate2,
-   IxPerfProfAccXscalePmuEvent pmuEvent3,
-   UINT32 eventRate3,
-   IxPerfProfAccXscalePmuEvent pmuEvent4,
-   UINT32 eventRate4)
- *
- * @brief Starts the event based sampling
- *
- * @param	numEvents UINT32 [in] - the number of PMU events that are 
- *	  		to be monitored as specified by the user. The value should be
- *          between 1-4 events at a time.
- * @param 	pmuEvent1 @ref IxPerfProfAccXscalePmuEvent [in] - the specific PMU 
- *    		event to be monitored by counter 1
- * @param 	eventRate1 UINT32 [in] - sampling rate of counter 1. The rate is 
- *			the number of events before a sample taken.  If 0 is specified, the
- *			the full counter value (0xFFFFFFFF) is used. The rate must not be 
- *			greater than the full counter value.
- * @param 	pmuEvent2 @ref IxPerfProfAccXscalePmuEvent [in] - the specific PMU 
- *    		event to be monitored by counter 2 
- * @param 	eventRate2 UINT32 [in] -  sampling rate of counter 2. The rate is 
- *			the number of events before a sample taken. If 0 is specified, the 
- *			full counter value (0xFFFFFFFF) is used. The rate must not be 
- *          greater than the full counter value.
- * @param 	pmuEvent3 @ref IxPerfProfAccXscalePmuEvent [in] - the specific PMU 
- *    		event to be monitored by counter 3
- * @param 	eventRate3 UINT32 [in] -  sampling rate of counter 3. The rate is 
- *			the number of events before a sample taken.  If 0 is specified, the 
- *			full counter value (0xFFFFFFFF) is used.  The rate must not be 
- *          greater than the full counter value.
- * @param 	pmuEvent4 @ref IxPerfProfAccXscalePmuEvent [in] - the specific PMU 
- *    		event to be monitored by counter 4
- * @param 	eventRate4 UINT32 [in] -  sampling rate of counter 4. The rate is 
- *			the number of events before a sample taken.  If 0 is specified, the 
- *			full counter value (0xFFFFFFFF) is used. The rate must not be 
- *          greater than the full counter value.
- *
- * Starts the event based sampling to determine the frequency with 
- * which events are being executed.  The sampling rate is the number of events,
- * as specified by the user,  before a counter overflow interrupt is 
- * generated.  A sample is taken at each counter overflow interrupt.  At each
- * sample,the value of the program counter determines the corresponding 
- * location in the code.  Each of these occurrences are recorded to determine 
- * the frequency with which the Xscale code in each event is executed. This API
- * has to be called before ixPerfProfAccXscalePmuEventSampStop can be called.
- *
- * @return
- *	- IX_PERFPROF_ACC_STATUS_SUCCESS if event based sampling is started 
- *	  successfully
- *	- IX_PERFPROF_ACC_STATUS_FAIL if unable to start the sampling
- *	- IX_PERFPROF_ACC_STATUS_XSCALE_PMU_NUM_INVALID if the number of events 
- *        specified is out of the valid range
- *	- IX_PERFPROF_ACC_STATUS_XSCALE_PMU_EVENT_INVALID if the value of the
- *        PMU event specified does not exist
- *      - IX_PERFPROF_ACC_STATUS_ANOTHER_UTIL_IN_PROGRESS - another utility is
- *        running 
- *              
- * @li   Reentrant    : no
- * @li   ISR Callable : no
- *
- */
-PUBLIC IxPerfProfAccStatus
-ixPerfProfAccXscalePmuEventSampStart(
-	UINT32 numEvents,
-	IxPerfProfAccXscalePmuEvent pmuEvent1,
-	UINT32 eventRate1,
-    IxPerfProfAccXscalePmuEvent pmuEvent2,
-    UINT32 eventRate2,
-    IxPerfProfAccXscalePmuEvent pmuEvent3,
-    UINT32 eventRate3,
-    IxPerfProfAccXscalePmuEvent pmuEvent4,
-    UINT32 eventRate4);
-
-/**
- * @ingroup IxPerfProfAcc
- *
- * @fn ixPerfProfAccXscalePmuEventSampStop(
-   IxPerfProfAccXscalePmuSamplePcProfile *eventProfile1,
-   IxPerfProfAccXscalePmuSamplePcProfile *eventProfile2,
-   IxPerfProfAccXscalePmuSamplePcProfile *eventProfile3,
-   IxPerfProfAccXscalePmuSamplePcProfile *eventProfile4)
- *
- * @brief Stops the event based sampling
- *
- * @param       *eventProfile1 @ref IxPerfProfAccXscalePmuSamplePcProfile [out] - 
- *              pointer to the array of profiles for each program counter value;
- *              the user should set the size of the array to 
- *				IX_PERFPROF_ACC_XSCALE_PMU_MAX_PROFILE_SAMPLES. It is the 
- *				users's responsibility to allocate memory for this pointer.
- * @param       *eventProfile2 @ref IxPerfProfAccXscalePmuSamplePcProfile [out] - 
- *              pointer to the array of profiles for each program counter value;
- *              the user should set the size of the array to 
- *				IX_PERFPROF_ACC_XSCALE_PMU_MAX_PROFILE_SAMPLES.  It is the 
- *				users's responsibility to allocate memory for this pointer.
- * @param       *eventProfile3 @ref IxPerfProfAccXscalePmuSamplePcProfile [out] - 
- *              pointer to the array of profiles for each program counter value;
- *              the user should set the size of the array to 
- *				IX_PERFPROF_ACC_XSCALE_PMU_MAX_PROFILE_SAMPLES.  It is the 
- *				users's responsibility to allocate memory for this pointer.
- * @param       *eventProfile4 @ref IxPerfProfAccXscalePmuSamplePcProfile [out] - 
- *              pointer to the array of profiles for each program counter value;
- *              the user should set the size of the array to 
- *				IX_PERFPROF_ACC_XSCALE_PMU_MAX_PROFILE_SAMPLES.  It is the 
- *				users's responsibility to allocate memory for this pointer.
- *
- * This API stops the event based sampling.  The results are stored in the 
- * pointers allocated by the user.  It can only be called once 
- * ixPerfProfAccEventSampStart has been called.
- *
- * @return 
- *      - IX_PERFPROF_ACC_STATUS_SUCCESS if event based sampling is stopped 
- *         successfully
- *      - IX_PERFPROF_ACC_STATUS_XSCALE_PMU_START_NOT_CALLED if
- *          ixPerfProfAccEventSampStart not called first.
- *              
- * @li   Reentrant    : no
- * @li   ISR Callable : no
- *
- */
-PUBLIC IxPerfProfAccStatus 
-ixPerfProfAccXscalePmuEventSampStop(
-    IxPerfProfAccXscalePmuSamplePcProfile *eventProfile1,
-    IxPerfProfAccXscalePmuSamplePcProfile *eventProfile2,
-    IxPerfProfAccXscalePmuSamplePcProfile *eventProfile3,
-    IxPerfProfAccXscalePmuSamplePcProfile *eventProfile4);
-
-/**                                                                             
- * @ingroup IxPerfProfAcc                                                      
- *                                                                              
- * @fn ixPerfProfAccXscalePmuResultsGet(IxPerfProfAccXscalePmuResults *results)     
- *                                                                              
- * @brief Reads the current value of the counters and their overflow                                        
- *                                                                              
- * @param *results @ref IxPerfProfAccXscalePmuResults [out] - pointer to the 
-          results struct.  It is the user's responsibility to allocate memory
-          for this pointer
- *                                                                              
- * This API reads the value of all four event counters and the clock counter, 
- * and the associated overflows.  It does not give results associated with 
- * sampling, i.e. PC and their frequencies.  This API can be called at any time
- * once a process has been started. If it is called before a process has started
- * the user should be aware that the values it contains are default values and 
- * might be meaningless.  The values of the counters are stored in the pointer 
- * allocated by the client.
- *                                                                    
- * @return - none
- *              
- * @li   Reentrant    : no
- * @li   ISR Callable : no
- *
- */                                                                             
-PUBLIC void                                                     
-ixPerfProfAccXscalePmuResultsGet(IxPerfProfAccXscalePmuResults *results);    
-
-/**
- * @ingroup IxPerfProfAcc
- * 
- * @fn ixPerfProfAccBusPmuStart(
-        IxPerfProfAccBusPmuMode mode, 
-        IxPerfProfAccBusPmuEventCounters1 pecEvent1,
-        IxPerfProfAccBusPmuEventCounters2 pecEvent2, 
-        IxPerfProfAccBusPmuEventCounters3 pecEvent3, 
-        IxPerfProfAccBusPmuEventCounters4 pecEvent4,
-        IxPerfProfAccBusPmuEventCounters5 pecEvent5, 
-        IxPerfProfAccBusPmuEventCounters6 pecEvent6, 
-        IxPerfProfAccBusPmuEventCounters7 pecEvent7)
- * @brief Initializes all the counters and selects events to be monitored.
- *
- * Function initializes all the counters and assigns the events associated 
- * with the counters. Users send in the mode and events they want to count.
- * This API verifies if the combination chosen is appropriate 
- * and sets all the registers accordingly. Selecting HALT mode will result
- * in an error. User should use ixPerfProfAccBusPmuStop() to HALT. 
- * 
- * 
- * @param mode @ref IxPerfProfAccStateBusPmuMode [in] - Mode selection.
- * @param pecEvent1 @ref IxPerfProfAccBusPmuEventCounters1 [in] - Event for PEC1.
- * @param pecEvent2 @ref IxPerfProfAccBusPmuEventCounters2 [in] - Event for PEC2.
- * @param pecEvent3 @ref IxPerfProfAccBusPmuEventCounters3 [in] - Event for PEC3.
- * @param pecEvent4 @ref IxPerfProfAccBusPmuEventCounters4 [in] - Event for PEC4.
- * @param pecEvent5 @ref IxPerfProfAccBusPmuEventCounters5 [in] - Event for PEC5.
- * @param pecEvent6 @ref IxPerfProfAccBusPmuEventCounters6 [in] - Event for PEC6.
- * @param pecEvent7 @ref IxPerfProfAccBusPmuEventCounters7 [in] - Event for PEC7.
- *
- * @return 
- *      - IX_PERFPROF_ACC_STATUS_SUCCESS - Initialization executed 
- *        successfully.  
- *      - IX_PERFPROF_ACC_STATUS_BUS_PMU_MODE_ERROR - Error in selection of 
- * 		  mode. Only NORTH, SOUTH and SDRAM modes are allowed. 
- *      - IX_PERFPROF_ACC_STATUS_BUS_PMU_PEC1_ERROR - Error in selection of 
- *        event for PEC1
- *      - IX_PERFPROF_ACC_STATUS_BUS_PMU_PEC2_ERROR - Error in selection of 
- *        event for PEC2 
- *      - IX_PERFPROF_ACC_STATUS_BUS_PMU_PEC3_ERROR - Error in selection of 
- *        event for PEC3
- *      - IX_PERFPROF_ACC_STATUS_BUS_PMU_PEC4_ERROR - Error in selection of 
- *        event for PEC4
- *      - IX_PERFPROF_ACC_STATUS_BUS_PMU_PEC5_ERROR - Error in selection of 
- *        event for PEC5
- *      - IX_PERFPROF_ACC_STATUS_BUS_PMU_PEC6_ERROR - Error in selection of 
- *        event for PEC6
- *      - IX_PERFPROF_ACC_STATUS_BUS_PMU_PEC7_ERROR - Error in selection of 
- *        event for PEC7
- * 		- IX_PERFPROF_ACC_STATUS_ANOTHER_UTIL_IN_PROGRESS - another utility 
- * 		  is running
- * 		- IX_PERFPROF_ACC_STATUS_FAIL - Failed to start because interrupt 
- * 		  service routine fails to bind.  
- *              
- * @li   Reentrant    : no
- * @li   ISR Callable : no
- *
- **/
-PUBLIC 
-IxPerfProfAccStatus ixPerfProfAccBusPmuStart (
-        IxPerfProfAccBusPmuMode mode, 
-        IxPerfProfAccBusPmuEventCounters1 pecEvent1,
-        IxPerfProfAccBusPmuEventCounters2 pecEvent2, 
-        IxPerfProfAccBusPmuEventCounters3 pecEvent3, 
-        IxPerfProfAccBusPmuEventCounters4 pecEvent4,
-        IxPerfProfAccBusPmuEventCounters5 pecEvent5, 
-        IxPerfProfAccBusPmuEventCounters6 pecEvent6, 
-        IxPerfProfAccBusPmuEventCounters7 pecEvent7);
-
-/**
- * @ingroup IxPerfProfAcc
- * 
- * @fn ixPerfProfAccBusPmuStop(void)
- * @brief Stops all counters. 
- * 
- * This function stops all the PECs by setting the halt bit in the ESR.
- *
- *
- * @return 
- *      - IX_PERFPROF_ACC_STATUS_SUCCESS - Counters successfully halted.
- *      - IX_PERFPROF_ACC_STATUS_FAIL - Counters could'nt be halted. 
- *		- IX_PERFPROF_ACC_STATUS_BUS_PMU_START_NOT_CALLED - the 
- * 		  ixPerfProfAccBusPmuStart() function is not called.
- *              
- * @li   Reentrant    : no
- * @li   ISR Callable : no
- *
- **/
-PUBLIC IxPerfProfAccStatus 
-ixPerfProfAccBusPmuStop (void);
-
-/**
- * @ingroup IxPerfProfAcc
- * 
- * @fn ixPerfProfAccBusPmuResultsGet (
-		IxPerfProfAccBusPmuResults *busPmuResults)
- * @brief Gets values of all counters 
- * 
- * This function is responsible for getting all the counter values from the 
- * lower API and putting it into an array for the user.
- *
- * @param *busPmuResults @ref IxPerfProfAccBusPmuResults [out]
- *           - Pointer to a structure of arrays to store all counter values.
- *
- * @return  none
- *              
- * @li   Reentrant    : no
- * @li   ISR Callable : no
- *
- **/
-PUBLIC void
-ixPerfProfAccBusPmuResultsGet (IxPerfProfAccBusPmuResults *BusPmuResults);
-
-/**
- * @ingroup IxPerfProfAcc
- * 
- * @fn ixPerfProfAccBusPmuPMSRGet (
-	UINT32 *pmsrValue)
- * @brief Get values of PMSR  
- *
- * This API gets the Previous Master Slave Register
- * value and returns it to the calling function. This value indicates
- * which master or slave accessed the north, south bus or sdram last.
- * The value returned by this function is a 32 bit value and is read
- * from location of an offset 0x0024 of the base value.
- *
- * The PMSR value returned indicate the following:
- * <pre>
- *
- * *************************************************************************************
- * *  Bit    *  Name  *       Description                                              *
- * *                                                                                   * 
- * *************************************************************************************
- * * [31:18]  *Reserved*                                                               *
- * *************************************************************************************
- * * [17:12] *  PSS   * Indicates which of the slaves on                               *
- * *         *        *  ARBS was previously                                           *
- * *         *        * accessed by the AHBS.                                          * 
- * *         *        * [000001] Expansion Bus                                         *
- * *         *        * [000010] SDRAM Controller                                      *
- * *         *        * [000100] PCI                                                   *
- * *         *        * [001000] Queue Manager                                         * 
- * *         *        * [010000] AHB-APB Bridge                                        * 
- * *         *        * [100000] Reserved                                              *
- * *************************************************************************************
- * * [11:8]  *  PSN   * Indicates which of the Slaves on                               *
- * *         *        * ARBN was previously                                            *
- * *         *        * accessed the AHBN.                                             *
- * *         *        * [0001] SDRAM Controller                                        *
- * *         *        * [0010] AHB-AHB Bridge                                          *
- * *         *        * [0100] Reserved                                                *
- * *         *        * [1000] Reserved                                                *
- * *************************************************************************************
- * *  [7:4]  *  PMS   * Indicates which of the Masters on                              *
- * *         *        * ARBS was previously                                            *
- * *         *        * accessing the AHBS.                                            *
- * *         *        * [0001] Gasket                                                  *
- * *         *        * [0010] AHB-AHB Bridge                                          *
- * *         *        * [0100] PCI                                                     *
- * *         *        * [1000] APB                                                     *
- * *************************************************************************************
- * *  [3:0]  *  PMN   * Indicates which of the Masters on                              *
- * *         *        * ARBN was previously                                            *
- * *         *        * accessing the AHBN.                                            *
- * *         *        * [0001] NPEA                                                    *
- * *         *        * [0010] NPEB                                                    *
- * *         *        * [0100] NPEC                                                    *
- * *         *        * [1000] Reserved                                                *
- * *************************************************************************************
- * </pre>
- *
- * @param *pmsrValue UINT32 [out] - Pointer to return PMSR value. Users need to
- * 							  allocate storage for psmrValue.   
- *
- * @return none 
- *
- * @li   Reentrant    : no
- * @li   ISR Callable : no
- *
- **/
-PUBLIC void
-ixPerfProfAccBusPmuPMSRGet (
-UINT32 *pmsrValue);
-
-
-/** 
- * The APIs below are specifically used for Xcycle module. 
- **/
-
-/**
- * @ingroup IxPerfProfAcc
- * 
- * @fn ixPerfProfAccXcycleBaselineRun (
-		UINT32 *numBaselineCycle) 
- *
- * @brief Perform baseline for Xcycle 
- *
- * @param *numBaselineCycle UINT32 [out] - pointer to baseline value after
- * 					calibration. Calling function are responsible for 
- *					allocating memory space for this pointer. 
- *
- * Global Data  : 
- *                        - None.
- *                        
- * This function MUST be run before the Xcycle tool can be used. This 
- * function must be run immediately when the OS boots up with no other 
- * addition programs running. 
- * Addition note :     This API will measure the time needed to perform
- * a fix amount of CPU instructions (~ 1 second worth of loops) as a 
- * highest priority task and with interrupt disabled. The time measured
- * is known as the baseline - interpreted as the shortest time 
- * needed to complete the amount of CPU instructions. The baseline is 
- * returned as unit of time in 66Mhz clock tick.  
- *
- * @return 
- *      - IX_PERFPROF_ACC_STATUS_SUCCESS - successful run, result is returned
- *      - IX_PERFPROF_ACC_STATUS_XCYCLE_PRIORITY_SET_FAIL - failed to change
- *         task priority
- *      - IX_PERFPROF_ACC_STATUS_XCYCLE_PRIORITY_RESTORE_FAIL - failed to
- *         restore task priority
- *      - IX_PERFPROF_ACC_STATUS_ANOTHER_UTIL_IN_PROGRESS - another utility 
- *         is running 
- *      - IX_PERFPROF_ACC_STATUS_XCYCLE_MEASUREMENT_IN_PROGRESS  - Xcycle 
- *	  tool has already started
- *              
- * @li   Reentrant    : no
- * @li   ISR Callable : no
- *
- */
-PUBLIC IxPerfProfAccStatus
-ixPerfProfAccXcycleBaselineRun(
-	UINT32 *numBaselineCycle); 
-
-/**
- * @ingroup IxPerfProfAcc
- * 
- * @fn ixPerfProfAccXcycleStart(
-		UINT32 numMeasurementsRequested);
- *
- * @brief Start the measurement
- *
- * @param  numMeasurementsRequested UINT32 [in] - number of measurements 
- *							to perform. Value can be 0 to  
- *							IX_PERFPROF_ACC_XCYCLE_MAX_NUM_OF_MEASUREMENTS. 
- *							0 indicate continuous measurement. 
- *
- * Global Data  : 
- *                        - None.
- *                        
- * 
- * Start the measurements immediately. 
- * numMeasurementsRequested specifies number of measurements to run. 
- * If numMeasurementsRequested is set to 0, the measurement will
- * be performed continuously until IxPerfProfAccXcycleStop()
- * is called.  
- * It is estimated that 1 measurement takes approximately 1 second during 
- * low CPU utilization, therefore 128 measurement takes approximately 128 sec.
- * When CPU utilization is high, the measurement will take longer.
- * This function spawn a task the perform the measurement and returns. 
- * The measurement may continue even if this function returns. 
- *
- * IMPORTANT: Under heavy CPU utilization, the task spawn by this 
- * function may starve and fail to respond to stop command. User 
- * may need to kill the task manually in this case.  
- *
- * There are only IX_PERFPROF_ACC_XCYCLE_MAX_NUM_OF_MEASUREMENTS 
- * storage available so storing is wrapped around if measurements are  
- * more than IX_PERFPROF_ACC_XCYCLE_MAX_NUM_OF_MEASUREMENTS.
- *
- *
- * @return 
- *      - IX_PERFPROF_ACC_STATUS_SUCCESS - successful start, a thread is created 
- *	   in the background to perform measurement. 
- *      - IX_PERFPROF_ACC_STATUS_XCYCLE_PRIORITY_SET_FAIL - failed to set
- *         task priority
- *      - IX_PERFPROF_ACC_STATUS_XCYCLE_THREAD_CREATE_FAIL - failed to create
- *	   thread to perform measurement.
- *      - IX_PERFPROF_ACC_STATUS_XCYCLE_NO_BASELINE - baseline is not available 
- *      - IX_PERFPROF_ACC_STATUS_XCYCLE_MEASUREMENT_REQUEST_OUT_OF_RANGE -
- *	   value is larger than IX_PERFPROF_ACC_XCYCLE_MAX_NUM_OF_MEASUREMENTS
- *      - IX_PERFPROF_ACC_STATUS_XCYCLE_MEASUREMENT_IN_PROGRESS	- Xcycle tool 
- *	   has already started
- *      - IX_PERFPROF_ACC_STATUS_ANOTHER_UTIL_IN_PROGRESS - another utility is 
- *         running
- *              
- * @li   Reentrant    : no
- * @li   ISR Callable : no
- *
- */
-PUBLIC IxPerfProfAccStatus
-ixPerfProfAccXcycleStart (
-	UINT32 numMeasurementsRequested);  
-
-/**
- * @ingroup IxPerfProfAcc
- * 
- * @fn ixPerfProfAccXcycleStop(void); 
- *
- * @brief Stop the Xcycle measurement
- *
- * @param None
- *
- * Global Data  : 
- *                        - None.
- *                        
- * Stop Xcycle measurements immediately. If the measurements have stopped 
- * or not started, return IX_PERFPROF_STATUS_XCYCLE_MEASUREMENT_NOT_RUNNING. 
- * Note: This function does not stop measurement cold. The measurement thread 
- * may need a few seconds to complete the last measurement. User needs to use
- * ixPerfProfAccXcycleInProgress() to determine if measurement is indeed
- * completed. 
- *
- * @return 
- *      - IX_PERFPROF_ACC_STATUS_SUCCESS - successful measurement is stopped
- *      - IX_PERFPROF_STATUS_XCYCLE_MEASUREMENT_NOT_RUNNING - no measurement running
- *              
- * @li   Reentrant    : no
- * @li   ISR Callable : no
- *
- */
-PUBLIC IxPerfProfAccStatus
-ixPerfProfAccXcycleStop(void); 
-
-/**
- * @ingroup IxPerfProfAcc
- * 
- * @fn ixPerfProfAccXcycleResultsGet(
-	IxPerfProfAccXcycleResults *xcycleResult ) 
- *
- * @brief Get the results of Xcycle measurement
- *
- * @param *xcycleResult @ref IxPerfProfAccXcycleResults [out] - Pointer to 
- * 				results of last measurements. Calling function are 
- *				responsible for allocating memory space for this pointer.
- *
- * Global Data  : 
- *                        - None.
- *                        
- * Retrieve the results of last measurement. User should use 
- * ixPerfProfAccXcycleInProgress() to check if measurement is completed 
- * before getting the results.
- *
- * @return 
- *      - IX_PERFPROF_ACC_STATUS_SUCCESS - successful 
- *      - IX_PERFPROF_ACC_STATUS_FAIL - result is not complete. 
- *      - IX_PERFPROF_ACC_STATUS_XCYCLE_NO_BASELINE - baseline is performed
- *      - IX_PERFPROF_ACC_STATUS_XCYCLE_MEASUREMENT_IN_PROGRESS  - Xcycle 
- *         tool is still running
- *              
- * @li   Reentrant    : no
- * @li   ISR Callable : no
- *
- */
-PUBLIC IxPerfProfAccStatus
-ixPerfProfAccXcycleResultsGet (
-    IxPerfProfAccXcycleResults *xcycleResult);  
-
-/**
- * @ingroup IxPerfProfAcc
- * 
- * @fn ixPerfProfAccXcycleInProgress (void)
- *
- * @brief Check if Xcycle is running
- *
- * @param None
- * Global Data  : 
- *                        - None.
- *                        
- * Check if Xcycle measuring task is running. 
- *
- * @return 
- *      - true - Xcycle is running
- *      - false - Xcycle is not running
- *              
- * @li   Reentrant    : no
- * @li   ISR Callable : no
- *
- */
-PUBLIC BOOL
-ixPerfProfAccXcycleInProgress(void); 
-
-#ifdef __linux
-/**
- * @ingroup IxPerfProfAcc
- *
- * @fn ixPerfProfAccXscalePmuTimeSampCreateProcFile 
- *
- * @brief Enables proc file to call module function
- *
- * @param None
- *
- * Global Data  :
- *                        - None.
- *
- * This function is declared globally to enable /proc directory system to call
- * and execute the function when the registered file is called. This function is not meant to 
- * be called by the user.
- *
- * @return
- *      - Length of data written to file.
- *
- * @li   Reentrant    : no
- * @li   ISR Callable : no
- *
- */
-int
-ixPerfProfAccXscalePmuTimeSampCreateProcFile (char *buf, char **start, off_t offset,
-                                      int count, int *eof, void *data);
-
-/**
- * @ingroup IxPerfProfAcc
- *
- * @fn ixPerfProfAccXscalePmuEventSampCreateProcFile 
- *
- * @brief Enables proc file to call module function 
- *
- * @param None
- *
- * Global Data  :
- *                        - None.
- *
- * This function is declared globally to enable /proc directory system to call
- * and execute the function when the registered file is called. This function is not meant to 
- * be called by the user.
- *
- * @return
- *      - Length of data written to file.
- *
- * @li   Reentrant    : no
- * @li   ISR Callable : no
- *
- */
-int
-ixPerfProfAccXscalePmuEventSampCreateProcFile (char *buf, char **start, off_t offset,
-                                      int count, int *eof, void *data);
-
-
-#endif /* ifdef __linux */
-
-#endif /* ndef IXPERFPROFACC_H */
-
-/**
- *@} defgroup IxPerfProfAcc 
- */
-
-
diff --git a/drivers/net/npe/include/IxQMgr.h b/drivers/net/npe/include/IxQMgr.h
deleted file mode 100644
index 23a45413bc..0000000000
--- a/drivers/net/npe/include/IxQMgr.h
+++ /dev/null
@@ -1,2186 +0,0 @@
-/**
- * @file    IxQMgr.h
- *
- * @date    30-Oct-2001
- *
- * @brief This file contains the public API of IxQMgr component.
- *
- * Some functions contained in this module are inline to achieve better
- * data-path performance. For this to work, the function definitions are
- * contained in this header file. The "normal" use of inline functions
- * is to use the inline functions in the module in which they are
- * defined. In this case these inline functions are used in external
- * modules and therefore the use of "inline extern". What this means
- * is as follows: if a function foo is declared as "inline extern" this
- * definition is only used for inlining, in no case is the function
- * compiled on its own. If the compiler cannot inline the function it
- * becomes an external reference. Therefore in IxQMgrQAccess.c all
- * inline functions are defined without the "inline extern" specifier
- * and so define the external references. In all other source files
- * including this header file, these funtions are defined as "inline
- * extern".
- *
- * 
- * @par
- * IXP400 SW Release version 2.0
- * 
- * -- Copyright Notice --
- * 
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- * 
- * @par
- * SPDX-License-Identifier:	BSD-3-Clause
- * @par
- * -- End of Copyright Notice --
-*/
-
-/* ------------------------------------------------------
-   Doxygen group definitions
-   ------------------------------------------------------ */
-/**
- * @defgroup IxQMgrAPI IXP400 Queue Manager (IxQMgr) API
- *
- * @brief The public API for the IXP400 QMgr component.
- *
- * IxQMgr is a low level interface to the AHB Queue Manager
- *
- * @{
- */
-
-#ifndef IXQMGR_H
-#define IXQMGR_H
-
-/*
- * User defined include files
- */
-
-#include "IxOsal.h"
-
-/* 
- * Define QMgr's IoMem macros, in DC mode if in LE 
- * regular if in BE. (Note: For Linux LSP gold release
- * may need to adjust mode.
- */
-#if defined (__BIG_ENDIAN)
-
-#define IX_QMGR_INLINE_READ_LONG IX_OSAL_READ_LONG_BE
-#define IX_QMGR_INLINE_WRITE_LONG IX_OSAL_WRITE_LONG_BE
-
-#else
-
-#define IX_QMGR_INLINE_READ_LONG IX_OSAL_READ_LONG_LE_DC
-#define IX_QMGR_INLINE_WRITE_LONG IX_OSAL_WRITE_LONG_LE_DC
-
-#endif
-
-/*
- * #defines and macros
- */
-
-/**
-*
-* @ingroup IxQMgrAPI
-*
-* @def IX_QMGR_INLINE
-*
-* @brief Inline definition, for inlining of Queue Access functions on API
-*
-* Please read the header information in this file for more details on the
-* use of function inlining in this component.
-*
-*/
-
-#ifndef __wince
-
-#ifdef IXQMGRQACCESS_C
-/* If IXQMGRQACCESS_C is set then the IxQmgrQAccess.c is including this file
-   and must instantiate a concrete definition for each inlineable API function
-   whether or not that function actually gets inlined. */
-#    ifdef NO_INLINE_APIS
-#        undef NO_INLINE_APIS
-#    endif
-#    define IX_QMGR_INLINE  /* Empty Define */
-#else
-#    ifndef NO_INLINE_APIS
-#       define IX_QMGR_INLINE IX_OSAL_INLINE_EXTERN
-#    else
-#       define IX_QMGR_INLINE /* Empty Define */
-#    endif
-#endif
-
-#else /* ndef __wince */
-
-#    ifndef NO_INLINE_APIS
-#       define NO_INLINE_APIS
-#    endif
-#    define IX_QMGR_INLINE
-
-#endif
-
-
-/**
-*
-* @ingroup IxQMgrAPI
-*
-* @def IX_QMGR_MAX_NUM_QUEUES
-*
-* @brief Number of queues supported by the AQM.
-*
-* This constant is used to indicate the number of AQM queues
-*
-*/
-#define IX_QMGR_MAX_NUM_QUEUES  64
-
-/**
-*
-* @ingroup IxQMgrAPI
-*
-* @def IX_QMGR_MIN_QID
-*
-* @brief Minimum queue identifier.
-*
-* This constant is used to indicate the smallest queue identifier
-*
-*/
-#define IX_QMGR_MIN_QID IX_QMGR_QUEUE_0
-
-/**
-*
-* @ingroup IxQMgrAPI
-*
-* @def IX_QMGR_MAX_QID
-*
-* @brief Maximum queue identifier.
-*
-* This constant is used to indicate the largest queue identifier
-*
-*/
-#define IX_QMGR_MAX_QID IX_QMGR_QUEUE_63
-
-/**
-*
-* @ingroup IxQMgrAPI
-*
-* @def IX_QMGR_MIN_QUEUPP_QID
-*
-* @brief Minimum queue identifier for reduced functionality queues.
-*
-* This constant is used to indicate Minimum queue identifier for reduced
-* functionality queues
-*
-*/
-#define IX_QMGR_MIN_QUEUPP_QID 32
-
-/**
-*
-* @ingroup IxQMgrAPI
-*
-* @def IX_QMGR_MAX_QNAME_LEN
-*
-* @brief Maximum queue name length.
-*
-* This constant is used to indicate the maximum null terminated string length
-* (excluding '\0') for a queue name
-*
-*/
-#define IX_QMGR_MAX_QNAME_LEN 16
-
-/**
- *
- * @ingroup IxQMgrAPI
- *
- * @def IX_QMGR_WARNING
- *
- * @brief Warning return code.
- *
- * Execution complete, but there is a special case to handle
- *
- */
-#define IX_QMGR_WARNING 2
-
-/**
- *
- * @ingroup IxQMgrAPI
- *
- * @def IX_QMGR_PARAMETER_ERROR
- *
- * @brief Parameter error return code (NULL pointer etc..).
- *
- * parameter error out of range/invalid
- *
- */
-#define IX_QMGR_PARAMETER_ERROR 3
-
-/**
- *
- * @ingroup IxQMgrAPI
- *
- * @def IX_QMGR_INVALID_Q_ENTRY_SIZE
- *
- * @brief Invalid entry size return code.
- *
- * Invalid queue entry size for a queue read/write
- *
- */
-#define IX_QMGR_INVALID_Q_ENTRY_SIZE 4
-
-/**
- *
- * @ingroup IxQMgrAPI
- *
- * @def IX_QMGR_INVALID_Q_ID
- *
- * @brief Invalid queue identifier return code.
- *
- * Invalid queue id, not in range 0-63
- *
- */
-#define IX_QMGR_INVALID_Q_ID 5
-
-/**
- *
- * @ingroup IxQMgrAPI
- *
- * @def IX_QMGR_INVALID_CB_ID
- *
- * @brief Invalid callback identifier return code.
- *
- * Invalid callback id
- */
-#define IX_QMGR_INVALID_CB_ID 6
-
-/**
- *
- * @ingroup IxQMgrAPI
- *
- * @def IX_QMGR_CB_ALREADY_SET
- *
- * @brief Callback set error return code.
- *
- * The specified callback has already been for this queue
- *
- */
-#define IX_QMGR_CB_ALREADY_SET 7
-
-/**
- *
- * @ingroup IxQMgrAPI
- *
- * @def IX_QMGR_NO_AVAILABLE_SRAM
- *
- * @brief Sram consumed return code.
- *
- * All AQM Sram is consumed by queue configuration
- *
- */
-#define IX_QMGR_NO_AVAILABLE_SRAM 8
-
-/**
- *
- * @ingroup IxQMgrAPI
- *
- * @def IX_QMGR_INVALID_INT_SOURCE_ID
- *
- * @brief Invalid queue interrupt source identifier return code.
- *
- * Invalid queue interrupt source given for notification enable
- */
-#define IX_QMGR_INVALID_INT_SOURCE_ID 9
-
-/**
- *
- * @ingroup IxQMgrAPI
- *
- * @def IX_QMGR_INVALID_QSIZE
- *
- * @brief Invalid queue size error code.
- *
- * Invalid queue size not one of 16,32, 64, 128
- *
- *
- */
-#define IX_QMGR_INVALID_QSIZE 10
-
-/**
- *
- * @ingroup IxQMgrAPI
- *
- * @def IX_QMGR_INVALID_Q_WM
- *
- * @brief Invalid queue watermark return code.
- *
- * Invalid queue watermark given for watermark set
- */
-#define IX_QMGR_INVALID_Q_WM 11
-
-/**
- *
- * @ingroup IxQMgrAPI
- *
- * @def IX_QMGR_Q_NOT_CONFIGURED
- *
- * @brief Queue not configured return code.
- *
- * Returned to the client when a function has been called on an unconfigured
- * queue
- *
- */
-#define IX_QMGR_Q_NOT_CONFIGURED 12
-
-/**
- *
- * @ingroup IxQMgrAPI
- *
- * @def IX_QMGR_Q_ALREADY_CONFIGURED
- *
- * @brief Queue already configured return code.
- *
- * Returned to client to indicate that a queue has already been configured
- */
-#define IX_QMGR_Q_ALREADY_CONFIGURED 13
-
-/**
- *
- * @ingroup IxQMgrAPI
- *
- * @def IX_QMGR_Q_UNDERFLOW
- *
- * @brief Underflow return code.
- *
- * Underflow on a queue read has occurred
- *
- */
-#define IX_QMGR_Q_UNDERFLOW 14
-
-/**
- *
- * @ingroup IxQMgrAPI
- *
- * @def IX_QMGR_Q_OVERFLOW
- *
- * @brief Overflow return code.
- *
- * Overflow on a queue write has occurred
- *
- */
-#define IX_QMGR_Q_OVERFLOW 15
-
-/**
- *
- * @ingroup IxQMgrAPI
- *
- * @def IX_QMGR_Q_INVALID_PRIORITY
- *
- * @brief Invalid priority return code.
- *
- * Invalid priority, not one of 0,1,2
- */
-#define IX_QMGR_Q_INVALID_PRIORITY 16
-
-/**
- *
- * @ingroup IxQMgrAPI
- *
- * @def IX_QMGR_ENTRY_INDEX_OUT_OF_BOUNDS
- *
- * @brief  Entry index out of bounds return code.
- *
- * Entry index is greater than number of entries in queue.
- */
-#define IX_QMGR_ENTRY_INDEX_OUT_OF_BOUNDS 17
-
-/**
- *
- * @ingroup IxQMgrAPI
- *
- * @def ixQMgrDispatcherLoopRun
- *
- * @brief  Map old function name ixQMgrDispatcherLoopRun () 
- *         to @ref ixQMgrDispatcherLoopRunA0 ().
- *
- */
-#define ixQMgrDispatcherLoopRun ixQMgrDispatcherLoopRunA0
-
-
-/**
- *
- * @ingroup IxQMgrAPI
- *
- * @def IX_QMGR_QUEUE
- *
- * @brief  Definition of AQM queue numbers
- *
- */
-#define IX_QMGR_QUEUE_0 (0)      /**< Queue Number 0 */
-#define IX_QMGR_QUEUE_1 (1)      /**< Queue Number 1 */
-#define IX_QMGR_QUEUE_2 (2)      /**< Queue Number 2 */
-#define IX_QMGR_QUEUE_3 (3)      /**< Queue Number 3 */
-#define IX_QMGR_QUEUE_4 (4)      /**< Queue Number 4 */
-#define IX_QMGR_QUEUE_5 (5)      /**< Queue Number 5 */
-#define IX_QMGR_QUEUE_6 (6)      /**< Queue Number 6 */
-#define IX_QMGR_QUEUE_7 (7)      /**< Queue Number 7 */
-#define IX_QMGR_QUEUE_8 (8)      /**< Queue Number 8 */
-#define IX_QMGR_QUEUE_9 (9)      /**< Queue Number 9 */
-#define IX_QMGR_QUEUE_10 (10)    /**< Queue Number 10 */
-#define IX_QMGR_QUEUE_11 (11)    /**< Queue Number 11 */
-#define IX_QMGR_QUEUE_12 (12)    /**< Queue Number 12 */
-#define IX_QMGR_QUEUE_13 (13)    /**< Queue Number 13 */
-#define IX_QMGR_QUEUE_14 (14)    /**< Queue Number 14 */
-#define IX_QMGR_QUEUE_15 (15)    /**< Queue Number 15 */
-#define IX_QMGR_QUEUE_16 (16)    /**< Queue Number 16 */
-#define IX_QMGR_QUEUE_17 (17)    /**< Queue Number 17 */
-#define IX_QMGR_QUEUE_18 (18)    /**< Queue Number 18 */
-#define IX_QMGR_QUEUE_19 (19)    /**< Queue Number 19 */
-#define IX_QMGR_QUEUE_20 (20)    /**< Queue Number 20 */
-#define IX_QMGR_QUEUE_21 (21)    /**< Queue Number 21 */
-#define IX_QMGR_QUEUE_22 (22)    /**< Queue Number 22 */
-#define IX_QMGR_QUEUE_23 (23)    /**< Queue Number 23 */
-#define IX_QMGR_QUEUE_24 (24)    /**< Queue Number 24 */
-#define IX_QMGR_QUEUE_25 (25)    /**< Queue Number 25 */
-#define IX_QMGR_QUEUE_26 (26)    /**< Queue Number 26 */
-#define IX_QMGR_QUEUE_27 (27)    /**< Queue Number 27 */
-#define IX_QMGR_QUEUE_28 (28)    /**< Queue Number 28 */
-#define IX_QMGR_QUEUE_29 (29)    /**< Queue Number 29 */
-#define IX_QMGR_QUEUE_30 (30)    /**< Queue Number 30 */
-#define IX_QMGR_QUEUE_31 (31)    /**< Queue Number 31 */
-#define IX_QMGR_QUEUE_32 (32)    /**< Queue Number 32 */
-#define IX_QMGR_QUEUE_33 (33)    /**< Queue Number 33 */
-#define IX_QMGR_QUEUE_34 (34)    /**< Queue Number 34 */
-#define IX_QMGR_QUEUE_35 (35)    /**< Queue Number 35 */
-#define IX_QMGR_QUEUE_36 (36)    /**< Queue Number 36 */
-#define IX_QMGR_QUEUE_37 (37)    /**< Queue Number 37 */
-#define IX_QMGR_QUEUE_38 (38)    /**< Queue Number 38 */
-#define IX_QMGR_QUEUE_39 (39)    /**< Queue Number 39 */
-#define IX_QMGR_QUEUE_40 (40)    /**< Queue Number 40 */
-#define IX_QMGR_QUEUE_41 (41)    /**< Queue Number 41 */
-#define IX_QMGR_QUEUE_42 (42)    /**< Queue Number 42 */
-#define IX_QMGR_QUEUE_43 (43)    /**< Queue Number 43 */
-#define IX_QMGR_QUEUE_44 (44)    /**< Queue Number 44 */
-#define IX_QMGR_QUEUE_45 (45)    /**< Queue Number 45 */
-#define IX_QMGR_QUEUE_46 (46)    /**< Queue Number 46 */
-#define IX_QMGR_QUEUE_47 (47)    /**< Queue Number 47 */
-#define IX_QMGR_QUEUE_48 (48)    /**< Queue Number 48 */
-#define IX_QMGR_QUEUE_49 (49)    /**< Queue Number 49 */
-#define IX_QMGR_QUEUE_50 (50)    /**< Queue Number 50 */
-#define IX_QMGR_QUEUE_51 (51)    /**< Queue Number 51 */
-#define IX_QMGR_QUEUE_52 (52)    /**< Queue Number 52 */
-#define IX_QMGR_QUEUE_53 (53)    /**< Queue Number 53 */
-#define IX_QMGR_QUEUE_54 (54)    /**< Queue Number 54 */
-#define IX_QMGR_QUEUE_55 (55)    /**< Queue Number 55 */
-#define IX_QMGR_QUEUE_56 (56)    /**< Queue Number 56 */
-#define IX_QMGR_QUEUE_57 (57)    /**< Queue Number 57 */
-#define IX_QMGR_QUEUE_58 (58)    /**< Queue Number 58 */
-#define IX_QMGR_QUEUE_59 (59)    /**< Queue Number 59 */
-#define IX_QMGR_QUEUE_60 (60)    /**< Queue Number 60 */
-#define IX_QMGR_QUEUE_61 (61)    /**< Queue Number 61 */
-#define IX_QMGR_QUEUE_62 (62)    /**< Queue Number 62 */
-#define IX_QMGR_QUEUE_63 (63)    /**< Queue Number 63 */
-#define IX_QMGR_QUEUE_INVALID (64)     /**< AQM Queue Number Delimiter */
-
-
-/*
- * Typedefs
- */
-
-/**
- * @typedef IxQMgrQId
- *
- * @ingroup IxQMgrAPI
- *
- * @brief Used in the API to identify the AQM queues.
- *
- */
-typedef int IxQMgrQId;
-
-/**
- * @typedef IxQMgrQStatus
- *
- * @ingroup IxQMgrAPI
- *
- * @brief Queue status.
- *
- * A queues status is defined by its relative fullness or relative emptiness.
- * Each of the queues 0-31 have Nearly Empty, Nearly Full, Empty, Full,
- * Underflow and Overflow status flags. Queues 32-63 have just Nearly Empty and
- * Full status flags.
- * The flags bit positions are outlined below:
- *        
- *        OF - bit-5<br> 
- *        UF - bit-4<br> 
- *         F - bit-3<br> 
- *        NF - bit-2<br> 
- *        NE - bit-1<br>
- *         E - bit-0<br> 
- *
- */
-typedef UINT32 IxQMgrQStatus;
-
-/**
- * @enum IxQMgrQStatusMask
- *
- * @ingroup IxQMgrAPI
- *
- * @brief Queue status mask.
- *
- * Masks for extracting the individual status flags from the IxQMgrStatus
- * word.
- *
- */
-typedef enum
-{
-    IX_QMGR_Q_STATUS_E_BIT_MASK  = 0x1,
-    IX_QMGR_Q_STATUS_NE_BIT_MASK = 0x2,
-    IX_QMGR_Q_STATUS_NF_BIT_MASK = 0x4,
-    IX_QMGR_Q_STATUS_F_BIT_MASK  = 0x8,
-    IX_QMGR_Q_STATUS_UF_BIT_MASK = 0x10,
-    IX_QMGR_Q_STATUS_OF_BIT_MASK = 0x20
-} IxQMgrQStatusMask;
-
-/**
- * @enum IxQMgrSourceId
- *
- * @ingroup IxQMgrAPI
- *
- * @brief Queue interrupt source select.
- *
- * This enum defines the different source conditions on a queue that result in
- * an interrupt being fired by the AQM. Interrupt source is configurable for
- * queues 0-31 only. The interrupt source for queues 32-63 is hardwired to the
- * NE(Nearly Empty) status flag.
- *
- */
-typedef enum
-{
-    IX_QMGR_Q_SOURCE_ID_E = 0,  /**< Queue Empty due to last read             */
-    IX_QMGR_Q_SOURCE_ID_NE,     /**< Queue Nearly Empty due to last read      */
-    IX_QMGR_Q_SOURCE_ID_NF,     /**< Queue Nearly Full due to last write      */
-    IX_QMGR_Q_SOURCE_ID_F,      /**< Queue Full due to last write             */
-    IX_QMGR_Q_SOURCE_ID_NOT_E,  /**< Queue Not Empty due to last write        */
-    IX_QMGR_Q_SOURCE_ID_NOT_NE, /**< Queue Not Nearly Empty due to last write */
-    IX_QMGR_Q_SOURCE_ID_NOT_NF, /**< Queue Not Nearly Full due to last read   */
-    IX_QMGR_Q_SOURCE_ID_NOT_F   /**< Queue Not Full due to last read          */
-} IxQMgrSourceId;
-
-/**
- * @enum IxQMgrQEntrySizeInWords
- *
- * @ingroup IxQMgrAPI
- *
- * @brief QMgr queue entry sizes.
- *
- * The entry size of a queue specifies the size of a queues entry in words.
- *
- */
-typedef enum
-{
-    IX_QMGR_Q_ENTRY_SIZE1 = 1,   /**< 1 word entry       */
-    IX_QMGR_Q_ENTRY_SIZE2 = 2,   /**< 2 word entry       */
-    IX_QMGR_Q_ENTRY_SIZE4 = 4    /**< 4 word entry       */
-} IxQMgrQEntrySizeInWords;
-
-/**
- * @enum IxQMgrQSizeInWords
- *
- * @ingroup IxQMgrAPI
- *
- * @brief QMgr queue sizes.
- *
- * These values define the allowed queue sizes for AQM queue. The sizes are
- * specified in words.
- *
- */
-typedef enum
-{
-    IX_QMGR_Q_SIZE16 = 16,   /**< 16 word buffer     */
-    IX_QMGR_Q_SIZE32 = 32,   /**< 32 word buffer     */
-    IX_QMGR_Q_SIZE64 = 64,   /**< 64 word buffer     */
-    IX_QMGR_Q_SIZE128 = 128, /**< 128 word buffer    */
-    IX_QMGR_Q_SIZE_INVALID = 129  /**< Insure that this is greater than largest
-				    * queue size supported by the hardware
-				    */
-} IxQMgrQSizeInWords;
-
-/**
- * @enum IxQMgrWMLevel
- *
- * @ingroup IxQMgrAPI
- *
- * @brief QMgr watermark levels.
- *
- * These values define the valid watermark levels(in ENTRIES) for queues. Each
- * queue 0-63 have configurable Nearly full and Nearly empty watermarks. For
- * queues 32-63 the Nearly full watermark has NO EFFECT.
- * If the Nearly full watermark is set to IX_QMGR_Q_WM_LEVEL16 this means that
- * the nearly full flag will be set by the hardware when there are >= 16 empty
- * entries in the specified queue.
- * If the Nearly empty watermark is set to IX_QMGR_Q_WM_LEVEL16 this means that
- * the Nearly empty flag will be set by the hardware when there are <= 16 full
- * entries in the specified queue.
- */
-typedef enum
-{
-    IX_QMGR_Q_WM_LEVEL0 = 0,    /**< 0 entry watermark  */
-    IX_QMGR_Q_WM_LEVEL1 = 1,    /**< 1 entry watermark  */
-    IX_QMGR_Q_WM_LEVEL2 = 2,    /**< 2 entry watermark  */
-    IX_QMGR_Q_WM_LEVEL4 = 4,    /**< 4 entry watermark  */
-    IX_QMGR_Q_WM_LEVEL8 = 8,    /**< 8 entry watermark  */
-    IX_QMGR_Q_WM_LEVEL16 = 16,  /**< 16 entry watermark */
-    IX_QMGR_Q_WM_LEVEL32 = 32,  /**< 32 entry watermark */
-    IX_QMGR_Q_WM_LEVEL64 = 64   /**< 64 entry watermark */
-} IxQMgrWMLevel;
-
-/**
- * @ingroup IxQMgrAPI
- * 
- * @enum IxQMgrDispatchGroup
- *
- * @brief QMgr dispatch group select identifiers.
- *
- * This enum defines the groups over which the  dispatcher will process when
- * called. One of the enum values must be used as a input to
- * @a ixQMgrDispatcherLoopRunA0, @a ixQMgrDispatcherLoopRunB0 
- * or @a ixQMgrDispatcherLoopRunB0LLP.
- *
- */
-typedef enum
-{
-    IX_QMGR_QUELOW_GROUP = 0, /**< Queues 0-31  */
-    IX_QMGR_QUEUPP_GROUP      /**< Queues 32-63 */
-} IxQMgrDispatchGroup;
-
-/**
- * @ingroup IxQMgrAPI
- * 
- * @enum IxQMgrPriority
- *
- * @brief Dispatcher priority levels.
- *
- * This enum defines the different queue dispatch priority levels.
- * The lowest priority number (0) is the highest priority level.
- *
- */
-typedef enum
-{
-  IX_QMGR_Q_PRIORITY_0 = 0,  /**< Priority level 0 */
-  IX_QMGR_Q_PRIORITY_1,      /**< Priority level 1 */
-  IX_QMGR_Q_PRIORITY_2,      /**< Priority level 2 */
-  IX_QMGR_Q_PRIORITY_INVALID /**< Invalid Priority level */
-} IxQMgrPriority;
-
-/**
- * @ingroup IxQMgrAPI
- *
- * @enum IxQMgrType
- *
- * @brief Callback types as used with livelock prevention
- *
- * This enum defines the different callback types. 
- * These types are only used when Livelock prevention is enabled.
- * The default is IX_QMGR_TYPE_REALTIME_OTHER. 
- *
- */
-
-typedef enum
-{
-  IX_QMGR_TYPE_REALTIME_OTHER = 0, /**< Real time callbacks-always allowed run*/
-  IX_QMGR_TYPE_REALTIME_PERIODIC,  /**< Periodic callbacks-always allowed run */
-  IX_QMGR_TYPE_REALTIME_SPORADIC   /**< Sporadic callbacks-only run if no
-                                        periodic callbacks are in progress    */
-} IxQMgrType;
-
-
-/**
- * @ingroup IxQMgrAPI
- * 
- * @typedef IxQMgrCallbackId
- *
- * @brief Uniquely identifies a callback function.
- *
- * A unique callback identifier associated with each callback
- * registered by clients.
- *
- */
-typedef unsigned IxQMgrCallbackId;
-
-/**
- * @typedef IxQMgrCallback
- *
- * @brief QMgr notification callback type.
- *
- * This defines the interface to all client callback functions.
- *
- * @param qId @ref IxQMgrQId [in] - the queue identifier
- * @param cbId @ref IxQMgrCallbackId [in] - the callback identifier
- */
-typedef void (*IxQMgrCallback)(IxQMgrQId qId,
-                               IxQMgrCallbackId cbId);
-
-/**
- * @ingroup IxQMgrAPI
- *
- * @typedef IxQMgrDispatcherFuncPtr
- *
- * @brief QMgr Dispatcher Loop function pointer.
- *
- * This defines the interface for QMgr Dispather functions.
- *
- * @param group @ref IxQMgrDispatchGroup [in] - the group of the 
- *                  queue of which the dispatcher will run   
- */
-typedef void (*IxQMgrDispatcherFuncPtr)(IxQMgrDispatchGroup group);
-
-/*
- * Function Prototypes
- */
-
-/* ------------------------------------------------------------
-   Initialisation related functions
-   ---------------------------------------------------------- */
-
-/**
- *
- * @ingroup IxQMgrAPI
- *
- * @fn ixQMgrInit (void)
- *
- * @brief Initialise the QMgr.
- *
- * This function must be called before and other QMgr function. It
- * sets up internal data structures.
- *
- * @return @li IX_SUCCESS, the IxQMgr successfully initialised
- * @return @li IX_FAIL, failed to initialize the Qmgr
- *
- */
-PUBLIC IX_STATUS
-ixQMgrInit (void);
-
-/**
- *
- * @ingroup IxQMgrAPI
- *
- * @fn ixQMgrUnload (void)
- *
- * @brief Uninitialise the QMgr.
- *
- * This function will perform the tasks required to unload the QMgr component
- * cleanly.  This includes unmapping kernel memory.
- * This should be called before a soft reboot or unloading of a kernel module.
- *
- * @pre It should only be called if @ref ixQMgrInit has already been called.
- *
- * @post No QMgr functions should be called until ixQMgrInit is called again.
- *
- * @return @li IX_SUCCESS, the IxQMgr successfully uninitialised
- * @return @li IX_FAIL, failed to uninitialize the Qmgr
- *
- */
-PUBLIC IX_STATUS
-ixQMgrUnload (void);
-
-/**
- *
- * @ingroup IxQMgrAPI
- *
- * @fn ixQMgrShow (void)
- *
- * @brief Describe queue configuration and statistics for active queues.
- *
- * This function shows active queues, their configurations and statistics.
- *
- * @return @li void
- *
- */
-PUBLIC void
-ixQMgrShow (void);
-
-/**
- *
- * @ingroup IxQMgrAPI
- *
- * @fn ixQMgrQShow (IxQMgrQId qId)
- *
- * @brief Display aqueue configuration and statistics for a queue.
- *
- * This function shows queue configuration and statistics for a queue.
- *
- * @param qId @ref IxQMgrQId [in] - the queue identifier.
- *
- * @return @li IX_SUCCESS, success
- * @return @li IX_QMGR_Q_NOT_CONFIGURED, queue not configured for this QId
- *
- */
-PUBLIC IX_STATUS
-ixQMgrQShow (IxQMgrQId qId);
-
-
-/* ------------------------------------------------------------
-   Configuration related functions
-   ---------------------------------------------------------- */
-
-/**
- *
- * @ingroup IxQMgrAPI
- * 
- * @fn ixQMgrQConfig (char *qName,
-	       IxQMgrQId qId,
-	       IxQMgrQSizeInWords qSizeInWords,
-	       IxQMgrQEntrySizeInWords qEntrySizeInWords)
- *
- * @brief Configure an AQM queue.
- *
- * This function is called by a client to setup a queue. The size and entrySize
- * qId and qName(NULL pointer) are checked for valid values. This function must
- * be called for each queue, before any queue accesses are made and after
- * ixQMgrInit() has been called. qName is assumed to be a '\0' terminated array
- * of 16 charachters or less.
- *
- * @param *qName char [in] - is the name provided by the client and is associated
- *                          with a QId by the QMgr.
- * @param qId @ref IxQMgrQId [in]  - the qId of this queue
- * @param qSizeInWords @ref IxQMgrQSize [in] - the size of the queue can be one of 16,32
- *                                       64, 128 words.
- * @param qEntrySizeInWords @ref IxQMgrQEntrySizeInWords [in] - the size of a queue entry
- *                                                        can be one of 1,2,4 words.
- *
- * @return @li IX_SUCCESS, a specified queue has been successfully configured.
- * @return @li IX_FAIL, IxQMgr has not been initialised.
- * @return @li IX_QMGR_PARAMETER_ERROR, invalid parameter(s).
- * @return @li IX_QMGR_INVALID_QSIZE, invalid queue size
- * @return @li IX_QMGR_INVALID_Q_ID, invalid queue id
- * @return @li IX_QMGR_INVALID_Q_ENTRY_SIZE, invalid queue entry size
- * @return @li IX_QMGR_Q_ALREADY_CONFIGURED, queue already configured
- *
- */
-PUBLIC IX_STATUS
-ixQMgrQConfig (char *qName,
-	       IxQMgrQId qId,
-	       IxQMgrQSizeInWords qSizeInWords,
-	       IxQMgrQEntrySizeInWords qEntrySizeInWords);
-
-/**
- * @ingroup IxQMgrAPI
- * 
- * @fn ixQMgrQSizeInEntriesGet (IxQMgrQId qId,
-			 unsigned *qSizeInEntries)
- *
- * @brief Return the size of a queue in entries.
- *
- * This function returns the the size of the queue in entriese.
- *
- * @param qId @ref IxQMgrQId [in] - the queue identifier
- * @param *qSizeInEntries @ref IxQMgrQSize [out] - queue size in entries
- *
- * @return @li IX_SUCCESS, successfully retrieved the number of full entrie
- * @return @li IX_QMGR_Q_NOT_CONFIGURED, queue not configured for this QId
- * @return @li IX_QMGR_PARAMETER_ERROR, invalid parameter(s).
- *
- */
-PUBLIC IX_STATUS
-ixQMgrQSizeInEntriesGet (IxQMgrQId qId,
-			 unsigned *qSizeInEntries);
-
-/**
- *
- * @ingroup IxQMgrAPI
- * 
- * @fn ixQMgrWatermarkSet (IxQMgrQId qId,
-		    IxQMgrWMLevel ne,
-		    IxQMgrWMLevel nf)
- *
- * @brief Set the Nearly Empty and Nearly Full Watermarks fo a queue.
- *
- * This function is called by a client to set the watermarks NE and NF for the
- * queue specified by qId.
- * The queue must be empty at the time this function is called, it is the clients
- * responsibility to ensure that the queue is empty.
- * This function will read the status of the queue before the watermarks are set
- * and again after the watermarks are set. If the status register has changed,
- * due to a queue access by an NPE for example, a warning is returned.
- * Queues 32-63 only support the NE flag, therefore the value of nf will be ignored
- * for these queues.
- *
- * @param qId @ref IxQMgrQId [in] -  the QId of the queue.
- * @param ne @ref IxQMgrWMLevel [in]  - the NE(Nearly Empty) watermark for this
- *                                 queue. Valid values are 0,1,2,4,8,16,32 and
- *                                 64 entries.
- * @param nf @ref IxQMgrWMLevel [in] - the NF(Nearly Full) watermark for this queue.
- *                                 Valid values are 0,1,2,4,8,16,32 and 64
- *                                 entries.
- *
- * @return @li IX_SUCCESS, watermarks have been set for the queu
- * @return @li IX_QMGR_Q_NOT_CONFIGURED, queue not configured for this QId
- * @return @li IX_QMGR_INVALID_Q_WM, invalid watermark
- * @return @li IX_QMGR_WARNING, the status register may not be constistent
- *
- */
-PUBLIC IX_STATUS
-ixQMgrWatermarkSet (IxQMgrQId qId,
-		    IxQMgrWMLevel ne,
-		    IxQMgrWMLevel nf);
-
-/**
- * @ingroup IxQMgrAPI
- * 
- * @fn ixQMgrAvailableSramAddressGet (UINT32 *address,
-			       unsigned *sizeOfFreeSram)
- *
- * @brief Return the address of available AQM SRAM.
- *
- * This function returns the starting address in AQM SRAM not used by the
- * current queue configuration and should only be called after all queues
- * have been configured.
- * Calling this function before all queues have been configured will will return
- * the currently available SRAM. A call to configure another queue will use some
- * of the available SRAM.
- * The amount of SRAM available is specified in sizeOfFreeSram. The address is the
- * address of the bottom of available SRAM. Available SRAM extends from address
- * from address to address + sizeOfFreeSram.
- *
- * @param **address UINT32 [out] - the address of the available SRAM, NULL if
- *                                none available.
- * @param *sizeOfFreeSram unsigned [out]- the size in words of available SRAM
- *
- * @return @li IX_SUCCESS, there is available SRAM and is pointed to by address
- * @return @li IX_QMGR_PARAMETER_ERROR, invalid parameter(s)
- * @return @li IX_QMGR_NO_AVAILABLE_SRAM, all AQM SRAM is consumed by the queue
- *             configuration.
- *
- */
-PUBLIC IX_STATUS
-ixQMgrAvailableSramAddressGet (UINT32 *address,
-			       unsigned *sizeOfFreeSram);
-
-
-/* ------------------------------------------------------------
-   Queue access related functions
-   ---------------------------------------------------------- */
-
-/**
- *
- * @ingroup IxQMgrAPI
- * 
- * @fn ixQMgrQReadWithChecks (IxQMgrQId qId,
-                       UINT32 *entry)
- *
- * @brief Read an entry from a queue.
- *
- * This function reads an entire entry from a queue returning it in entry. The
- * queue configuration word is read to determine what entry size this queue is
- * configured for and then the number of words specified by the entry size is
- * read.  entry must be a pointer to a previously allocated array of sufficient
- * size to hold an entry.
- *
- * @note - IX_QMGR_Q_UNDERFLOW is only returned for queues 0-31 as queues 32-63
- * do not have an underflow status maintained.
- *
- * @param  qId @ref IxQMgrQId [in]   - the queue identifier.
- * @param  *entry UINT32 [out]  - pointer to the entry word(s).
- *
- * @return @li IX_SUCCESS, entry was successfully read.
- * @return @li IX_QMGR_PARAMETER_ERROR, invalid paramter(s).
- * @return @li IX_QMGR_Q_NOT_CONFIGURED, queue not configured for this QId
- * @return @li IX_QMGR_Q_UNDERFLOW, attempt to read from an empty queue
- *
- */
-PUBLIC IX_STATUS
-ixQMgrQReadWithChecks (IxQMgrQId qId,
-                       UINT32 *entry);
-
-
-
-/** 
- * @brief Internal structure to facilitate inlining functions in IxQMgr.h
- */
-typedef struct
-{
-    /* fields related to write functions */
-    UINT32 qOflowStatBitMask;         /**< overflow status mask */
-    UINT32 qWriteCount;               /**< queue write count */
-
-    /* fields related to read and write functions */
-    volatile UINT32 *qAccRegAddr;     /**< access register */
-    volatile UINT32 *qUOStatRegAddr;  /**< status register */
-    volatile UINT32 *qConfigRegAddr;  /**< config register */
-    UINT32 qEntrySizeInWords;         /**< queue entry size in words */
-    UINT32 qSizeInEntries;            /**< queue size in entries */
-
-    /* fields related to read functions */
-    UINT32 qUflowStatBitMask;         /**< underflow status mask */
-    UINT32 qReadCount;                /**< queue read count */
-} IxQMgrQInlinedReadWriteInfo;
-
-
-/**
- *
- * @ingroup IxQMgrAPI
- *
- * @fn ixQMgrQReadMWordsMinus1 (IxQMgrQId qId,
-			        UINT32 *entry)
- *
- * @brief This function reads the remaining of the q entry
- *        for queues configured with many words.
- *        (the first word of the entry is already read 
- *        in the inlined function and the entry pointer already
- *        incremented
- *
- * @param  qId @ref IxQMgrQId [in]  - the queue identifier.
- * @param  *entry UINT32 [out] - pointer to the entry word(s).
- *
- * @return @li IX_SUCCESS, entry was successfully read.
- * @return @li IX_QMGR_Q_UNDERFLOW, attempt to read from an empty queue
- *
- */
-PUBLIC IX_STATUS
-ixQMgrQReadMWordsMinus1 (IxQMgrQId qId,
-			 UINT32 *entry);
-
-
-
-/**
- *
- * @ingroup IxQMgrAPI
- * 
- * @fn ixQMgrQRead (IxQMgrQId qId,
-	     UINT32 *entry)
- *
- * @brief Fast read of an entry from a queue.
- *
- * This function is a heavily streamlined version of ixQMgrQReadWithChecks(),
- * but performs essentially the same task.  It reads an entire entry from a
- * queue, returning it in entry which must be a pointer to a previously
- * allocated array of sufficient size to hold an entry.
- *
- * @note - This function is inlined, to reduce unnecessary function call
- * overhead.  It does not perform any parameter checks, or update any statistics.
- * Also, it does not check that the queue specified by qId has been configured.
- * or is in range. It simply reads an entry from the queue, and checks for
- * underflow.
- *
- * @note - IX_QMGR_Q_UNDERFLOW is only returned for queues 0-31 as queues 32-63
- * do not have an underflow status maintained.
- *
- * @param  qId @ref IxQMgrQId [in] - the queue identifier.
- * @param  *entry UINT32 [out] - pointer to the entry word(s).
- *
- * @return @li IX_SUCCESS, entry was successfully read.
- * @return @li IX_QMGR_Q_UNDERFLOW, attempt to read from an empty queue
- *
- */
-#ifdef NO_INLINE_APIS
-PUBLIC IX_STATUS
-ixQMgrQRead (IxQMgrQId qId,
-             UINT32 *entryPtr);
-#else 
-extern IxQMgrQInlinedReadWriteInfo ixQMgrQInlinedReadWriteInfo[];
-extern IX_STATUS ixQMgrQReadMWordsMinus1 (IxQMgrQId qId, UINT32 *entryPtr);
-
-IX_QMGR_INLINE PUBLIC IX_STATUS
-ixQMgrQRead (IxQMgrQId qId,
-             UINT32 *entryPtr);
-#endif
-
-IX_QMGR_INLINE PUBLIC IX_STATUS
-ixQMgrQRead (IxQMgrQId qId,
-	     UINT32 *entryPtr)
-#ifdef NO_INLINE_APIS
-    ;
-#else
-{
-    IxQMgrQInlinedReadWriteInfo *infoPtr = &ixQMgrQInlinedReadWriteInfo[qId];
-    UINT32 entry, entrySize;
-
-    /* get a new entry */
-    entrySize = infoPtr->qEntrySizeInWords;
-    entry = IX_QMGR_INLINE_READ_LONG(infoPtr->qAccRegAddr);
-
-    if (entrySize != IX_QMGR_Q_ENTRY_SIZE1)
-    {	
-	*entryPtr = entry;
-	/* process the remaining part of the entry */
-	return ixQMgrQReadMWordsMinus1(qId, entryPtr);
-    }
-
-    /* underflow is available for lower queues only */
-    if (qId < IX_QMGR_MIN_QUEUPP_QID)
-    {
-	/* the counter of queue entries is decremented. In happy 
-	 * day scenario there are many entries in the queue
-	 * and the counter does not reach zero.
-	 */
-	if (infoPtr->qReadCount-- == 0)
-	{
-	    /* There is maybe no entry in the queue
-	     * qReadCount is now negative, but will be corrected before
-	     * the function returns.
-	     */
-	    UINT32 qPtrs; /* queue internal pointers */
-
-	    /* when a queue is empty, the hw guarantees to return 
-	     * a null value. If the value is not null, the queue is
-	     * not empty.
-	     */
-	    if (entry == 0)
-	    {
-		/* get the queue status */
-		UINT32 status = IX_QMGR_INLINE_READ_LONG(infoPtr->qUOStatRegAddr);
-	
-		/* check the underflow status */
-		if (status & infoPtr->qUflowStatBitMask)
-		{
-		    /* the queue is empty 
-		    *  clear the underflow status bit if it was set 
-		    */
-		    IX_QMGR_INLINE_WRITE_LONG(infoPtr->qUOStatRegAddr,
-					 status & ~infoPtr->qUflowStatBitMask);
-		    *entryPtr = 0;
-		    infoPtr->qReadCount = 0;
-		    return IX_QMGR_Q_UNDERFLOW;
-		}
-	    }
-	    /* store the result */
-	    *entryPtr = entry;
-
-	    /* No underflow occured : someone is filling the queue
-	     * or the queue contains null entries.
-	     * The current counter needs to be
-	     * updated from the current number of entries in the queue
-	     */
-
-	    /* get snapshot of queue pointers */
-	    qPtrs = IX_QMGR_INLINE_READ_LONG(infoPtr->qConfigRegAddr);
-
-	    /* Mod subtraction of pointers to get number of words in Q. */
-	    qPtrs = (qPtrs - (qPtrs >> 7)) & 0x7f; 
-  
-	    if (qPtrs == 0)
-	    {
-		/* no entry in the queue */
-		infoPtr->qReadCount = 0;
-	    }
-	    else
-	    {
-		/* convert the number of words inside the queue
-		 * to a number of entries 
-		 */
-		infoPtr->qReadCount = qPtrs & (infoPtr->qSizeInEntries - 1);
-	    }
-	    return IX_SUCCESS;
-	}
-    }
-    *entryPtr = entry;
-    return IX_SUCCESS;
-}
-#endif
-
-/**
- *
- * @ingroup IxQMgrAPI
- * 
- * @fn ixQMgrQBurstRead (IxQMgrQId qId,
-		  UINT32 numEntries,
-		  UINT32 *entries)
- *
- * @brief Read a number of entries from an AQM queue.
- *
- * This function will burst read a number of entries from the specified queue.
- * The entry size of queue is auto-detected. The function will attempt to
- * read as many entries as specified by the numEntries parameter and will
- * return an UNDERFLOW if any one of the individual entry reads fail.
- *
- * @warning
- * IX_QMGR_Q_UNDERFLOW is only returned for queues 0-31 as queues 32-63
- * do not have an underflow status maintained, hence there is a potential for
- * silent failure here. This function must be used with caution.
- *
- * @note
- * This function is intended for fast draining of queues, so to make it
- * as efficient as possible, it has the following features:
- * - This function is inlined, to reduce unnecessary function call overhead.
- * - It does not perform any parameter checks, or update any statistics.
- * - It does not check that the queue specified by qId has been configured.
- * - It does not check that the queue has the number of full entries that
- * have been specified to be read. It will read until it finds a NULL entry or
- * until the number of specified entries have been read.  It always checks for
- * underflow after all the reads have been performed.
- * Therefore, the client should ensure before calling this function that there
- * are enough entries in the queue to read.  ixQMgrQNumEntriesGet() will
- * provide the number of full entries in a queue.
- * ixQMgrQRead() or ixQMgrQReadWithChecks(), which only reads
- * a single queue entry per call, should be used instead if the user requires
- * checks for UNDERFLOW after each entry read.
- *
- * @param qId @ref IxQMgrQId [in]   - the queue identifier.
- * @param numEntries unsigned [in] - the number of entries to read. 
- *                     This number should be greater than 0
- * @param *entries UINT32 [out] - the word(s) read.
- *
- * @return @li IX_SUCCESS, entries were successfully read.
- * @return @li IX_QMGR_Q_UNDERFLOW, attempt to read from an empty queue 
- *
- */
-#ifdef NO_INLINE_APIS  
-PUBLIC IX_STATUS
-ixQMgrQBurstRead (IxQMgrQId qId,
-                  UINT32 numEntries,
-                  UINT32 *entries);
-#else
-IX_QMGR_INLINE PUBLIC IX_STATUS
-ixQMgrQBurstRead (IxQMgrQId qId,
-                  UINT32 numEntries,
-                  UINT32 *entries);
-#endif  /* endif NO_INLINE_APIS */
-
-IX_QMGR_INLINE PUBLIC IX_STATUS
-ixQMgrQBurstRead (IxQMgrQId qId,
-		  UINT32 numEntries,
-		  UINT32 *entries)
-#ifdef NO_INLINE_APIS
-;
-#else
-{
-    IxQMgrQInlinedReadWriteInfo *infoPtr = &ixQMgrQInlinedReadWriteInfo[qId];
-    UINT32 nullCheckEntry;
-
-    if (infoPtr->qEntrySizeInWords == IX_QMGR_Q_ENTRY_SIZE1)
-    {
-	volatile UINT32 *qAccRegAddr = infoPtr->qAccRegAddr;
-
-	/* the code is optimized to take care of data dependencies:
-	 * Durig a read, there are a few cycles needed to get the 
-	 * read complete. During these cycles, it is poossible to
-	 * do some CPU, e.g. increment pointers and decrement 
-	 * counters.
-	 */
-
-	/* fetch a queue entry */
-	nullCheckEntry = IX_QMGR_INLINE_READ_LONG(infoPtr->qAccRegAddr);
-
-	/* iterate the specified number of queue entries */ 
-	while (--numEntries)
-	{
-	    /* check the result of the previous read */
-	    if (nullCheckEntry == 0)
-	    {
-		/* if we read a NULL entry, stop. We have underflowed */
-		break;
-	    }
-	    else
-	    {
-		/* write the entry */
-		*entries = nullCheckEntry;
-		/* fetch next entry */
-		nullCheckEntry = IX_QMGR_INLINE_READ_LONG(qAccRegAddr);
-		/* increment the write address */
-		entries++;
-	    }
-	}
-	/* write the pre-fetched entry */
-	*entries = nullCheckEntry;
-    }
-    else
-    {
-	IxQMgrQEntrySizeInWords entrySizeInWords = infoPtr->qEntrySizeInWords;
-	/* read the specified number of queue entries */
-	nullCheckEntry = 0;
-	while (numEntries--)
-	{
-	    UINT32 i;
-
-	    for (i = 0; i < (UINT32)entrySizeInWords; i++)
-	    {
-		*entries = IX_QMGR_INLINE_READ_LONG(infoPtr->qAccRegAddr + i);
-		nullCheckEntry |= *entries++;
-	    }
-
-	    /* if we read a NULL entry, stop. We have underflowed */
-	    if (nullCheckEntry == 0)
-	    {
-		break;
-	    }
-	    nullCheckEntry = 0;
-	}
-    }
-
-    /* reset the current read count : next access to the read function 
-     * will force a underflow status check 
-     */
-    infoPtr->qReadCount = 0;
-
-    /* Check if underflow occurred on the read */
-    if (nullCheckEntry == 0 && qId < IX_QMGR_MIN_QUEUPP_QID)
-    {
-	/* get the queue status */
-	UINT32 status = IX_QMGR_INLINE_READ_LONG(infoPtr->qUOStatRegAddr);
-
-	if (status & infoPtr->qUflowStatBitMask)
-	{
-	    /* clear the underflow status bit if it was set */
-	    IX_QMGR_INLINE_WRITE_LONG(infoPtr->qUOStatRegAddr,
-				 status & ~infoPtr->qUflowStatBitMask);
-	    return IX_QMGR_Q_UNDERFLOW;
-	}
-    }
-
-    return IX_SUCCESS;
-}
-#endif
-
-/**
- * @ingroup IxQMgrAPI
- * 
- * @fn ixQMgrQPeek (IxQMgrQId qId,
-	     unsigned int entryIndex,
-	     UINT32 *entry)
- *
- * @brief Read an entry from a queue without moving the read pointer.
- *
- * This function inspects an entry in a queue. The entry is inspected directly
- * in AQM SRAM and is not read from queue access registers. The entry is NOT removed
- * from the queue and the read/write pointers are unchanged.
- * N.B: The queue should not be accessed when this function is called.
- *
- * @param  qId @ref IxQMgrQId [in]   - the queue identifier.
- * @param  entryIndex unsigned int [in] - index of entry in queue in the range
- *                          [0].......[current number of entries in queue].
- * @param  *entry UINT32 [out] - pointer to the entry word(s).
- *
- * @return @li IX_SUCCESS, entry was successfully inspected.
- * @return @li IX_QMGR_PARAMETER_ERROR, invalid paramter(s).
- * @return @li IX_QMGR_Q_NOT_CONFIGURED, queue not configured for this QId.
- * @return @li IX_QMGR_ENTRY_INDEX_OUT_OF_BOUNDS, an entry does not exist at
- *             specified index.
- * @return @li IX_FAIL, failed to inpected the queue entry.
- */
-PUBLIC IX_STATUS
-ixQMgrQPeek (IxQMgrQId qId,
-	     unsigned int entryIndex,
-	     UINT32 *entry);
-
-/**
- *
- * @ingroup IxQMgrAPI
- * 
- * @fn ixQMgrQWriteWithChecks (IxQMgrQId qId,
-                        UINT32 *entry)
- *
- * @brief Write an entry to an AQM queue.
- *
- * This function will write the entry size number of words pointed to by entry to
- * the queue specified by qId. The queue configuration word is read to
- * determine the entry size of queue and the corresponding number of words is
- * then written to the queue.
- *
- * @note - IX_QMGR_Q_OVERFLOW is only returned for queues 0-31 as queues 32-63
- * do not have an overflow status maintained.
- *
- * @param qId @ref IxQMgrQId [in] - the queue identifier.
- * @param *entry UINT32 [in] - the word(s) to write.
- *
- * @return @li IX_SUCCESS, value was successfully written.
- * @return @li IX_QMGR_PARAMETER_ERROR, invalid paramter(s).
- * @return @li IX_QMGR_Q_NOT_CONFIGURED, queue not configured for this QId
- * @return @li IX_QMGR_Q_OVERFLOW, attempt to write to a full queue
- *
- */
-PUBLIC IX_STATUS
-ixQMgrQWriteWithChecks (IxQMgrQId qId,
-                        UINT32 *entry);
-
-/**
- *
- * @ingroup IxQMgrAPI
- * 
- * @fn ixQMgrQWrite (IxQMgrQId qId,
-	      UINT32 *entry)
- *
- * @brief Fast write of an entry to a queue.
- *
- * This function is a heavily streamlined version of ixQMgrQWriteWithChecks(),
- * but performs essentially the same task.  It will write the entry size number
- * of words pointed to by entry to the queue specified by qId.
- *
- * @note - This function is inlined, to reduce unnecessary function call
- * overhead.  It does not perform any parameter checks, or update any
- * statistics. Also, it does not check that the queue specified by qId has
- * been configured. It simply writes an entry to the queue, and checks for
- * overflow.
- *
- * @note - IX_QMGR_Q_OVERFLOW is only returned for queues 0-31 as queues 32-63
- * do not have an overflow status maintained.
- *
- * @param  qId @ref IxQMgrQId [in]   - the queue identifier.
- * @param  *entry UINT32 [in] - pointer to the entry word(s).
- *
- * @return @li IX_SUCCESS, entry was successfully read.
- * @return @li IX_QMGR_Q_OVERFLOW, attempt to write to a full queue
- *
- */
-#ifdef NO_INLINE_APIS
-PUBLIC IX_STATUS
-ixQMgrQWrite (IxQMgrQId qId,
-	      UINT32 *entry);
-#else
-IX_QMGR_INLINE PUBLIC IX_STATUS
-ixQMgrQWrite (IxQMgrQId qId,
-	      UINT32 *entry);
-#endif /* NO_INLINE_APIS */
-
-IX_QMGR_INLINE PUBLIC IX_STATUS
-ixQMgrQWrite (IxQMgrQId qId,
-	      UINT32 *entry)
-#ifdef NO_INLINE_APIS
-    ;
-#else
-{
-    IxQMgrQInlinedReadWriteInfo *infoPtr = &ixQMgrQInlinedReadWriteInfo[qId];
-    UINT32 entrySize;
-
-    /* write the entry */
-    IX_QMGR_INLINE_WRITE_LONG(infoPtr->qAccRegAddr, *entry);
-    entrySize = infoPtr->qEntrySizeInWords;
-
-    if (entrySize != IX_QMGR_Q_ENTRY_SIZE1)
-    {	
-	/* process the remaining part of the entry */
-	volatile UINT32 *qAccRegAddr = infoPtr->qAccRegAddr;
-	while (--entrySize)
-	{
-	    ++entry;
-	    IX_QMGR_INLINE_WRITE_LONG(++qAccRegAddr, *entry);
-	}
-	entrySize = infoPtr->qEntrySizeInWords;
-    }
-
-    /* overflow is available for lower queues only */
-    if (qId < IX_QMGR_MIN_QUEUPP_QID)
-    {   
-	UINT32 qSize = infoPtr->qSizeInEntries;
-	/* increment the current number of entries in the queue
-	 * and check for overflow 
-	 */
-	if (infoPtr->qWriteCount++ == qSize)
-	{
-	    /* the queue may have overflow */
-	    UINT32 qPtrs; /* queue internal pointers */
-  
-	    /* get the queue status */
-	    UINT32 status = IX_QMGR_INLINE_READ_LONG(infoPtr->qUOStatRegAddr);
-
-	    /* read the status twice because the status may 
-	     * not be immediately ready after the write operation
-	     */
-	    if ((status & infoPtr->qOflowStatBitMask) ||
-		((status = IX_QMGR_INLINE_READ_LONG(infoPtr->qUOStatRegAddr))
-		 & infoPtr->qOflowStatBitMask))
-	    {
-		/* the queue is full, clear the overflow status
-		 *  bit if it was set 
-		 */
-		IX_QMGR_INLINE_WRITE_LONG(infoPtr->qUOStatRegAddr,
-				     status & ~infoPtr->qOflowStatBitMask);
-		infoPtr->qWriteCount = infoPtr->qSizeInEntries;
-		return IX_QMGR_Q_OVERFLOW;
-	    }
-	    /* No overflow occured : someone is draining the queue
-	     * and the current counter needs to be
-	     * updated from the current number of entries in the queue
-	     */
-
-	    /* get q pointer snapshot */
-	    qPtrs = IX_QMGR_INLINE_READ_LONG(infoPtr->qConfigRegAddr);
-
-	    /* Mod subtraction of pointers to get number of words in Q. */
-	    qPtrs = (qPtrs - (qPtrs >> 7)) & 0x7f; 
-
-	    if (qPtrs == 0)
-	    {
-		/* the queue may be full at the time of the 
-		 * snapshot. Next access will check 
-		 * the overflow status again.
-		 */
-		infoPtr->qWriteCount = qSize;
-	    }
-	    else 
-	    {
-		/* convert the number of words to a number of entries */
-		if (entrySize == IX_QMGR_Q_ENTRY_SIZE1)
-		{
-		    infoPtr->qWriteCount = qPtrs & (qSize - 1);
-		}
-		else
-		{
-		    infoPtr->qWriteCount = (qPtrs / entrySize) & (qSize - 1);
-		}
-	    }
-	}
-    }
-    return IX_SUCCESS;
-}
-#endif
-
-/**
- *
- * @ingroup IxQMgrAPI
- * 
- * @fn ixQMgrQBurstWrite (IxQMgrQId qId,
-		   unsigned numEntries,
-		   UINT32 *entries)
- *
- * @brief Write a number of entries to an AQM queue.
- *
- * This function will burst write a number of entries to the specified queue.
- * The entry size of queue is auto-detected. The function will attempt to
- * write as many entries as specified by the numEntries parameter and will
- * return an OVERFLOW if any one of the individual entry writes fail.
- *
- * @warning
- * IX_QMGR_Q_OVERFLOW is only returned for queues 0-31 as queues 32-63
- * do not have an overflow status maintained, hence there is a potential for
- * silent failure here. This function must be used with caution.
- *
- * @note
- * This function is intended for fast population of queues, so to make it
- * as efficient as possible, it has the following features:
- * - This function is inlined, to reduce unnecessary function call overhead.
- * - It does not perform any parameter checks, or update any statistics.
- * - It does not check that the queue specified by qId has been configured.
- * - It does not check that the queue has enough free space to hold the entries
- * before writing, and only checks for overflow after all writes have been
- * performed.  Therefore, the client should ensure before calling this function
- * that there is enough free space in the queue to hold the number of entries
- * to be written.  ixQMgrQWrite() or ixQMgrQWriteWithChecks(), which only writes
- * a single queue entry per call, should be used instead if the user requires
- * checks for OVERFLOW after each entry written.
- *
- * @param qId @ref IxQMgrQId [in]   - the queue identifier.
- * @param numEntries unsigned [in] - the number of entries to write.
- * @param *entries UINT32 [in]  - the word(s) to write.
- *
- * @return @li IX_SUCCESS, value was successfully written.
- * @return @li IX_QMGR_Q_OVERFLOW, attempt to write to a full queue
- *
- */
-#ifdef NO_INLINE_APIS
-PUBLIC IX_STATUS
-ixQMgrQBurstWrite (IxQMgrQId qId,
-		   unsigned numEntries,
-		   UINT32 *entries);
-#else
-IX_QMGR_INLINE PUBLIC IX_STATUS
-ixQMgrQBurstWrite (IxQMgrQId qId,
-		   unsigned numEntries,
-		   UINT32 *entries);
-#endif /* NO_INLINE_APIS */
-
-IX_QMGR_INLINE PUBLIC IX_STATUS
-ixQMgrQBurstWrite (IxQMgrQId qId,
-		   unsigned numEntries,
-		   UINT32 *entries)
-#ifdef NO_INLINE_APIS
-;
-#else
-{
-    IxQMgrQInlinedReadWriteInfo *infoPtr = &ixQMgrQInlinedReadWriteInfo[qId];
-    UINT32 status;
-
-    /* update the current write count */
-    infoPtr->qWriteCount += numEntries;
-
-    if (infoPtr->qEntrySizeInWords == IX_QMGR_Q_ENTRY_SIZE1)
-    {
-	volatile UINT32 *qAccRegAddr = infoPtr->qAccRegAddr;
-	while (numEntries--)
-	{
-	    IX_QMGR_INLINE_WRITE_LONG(qAccRegAddr, *entries);
-	    entries++;
-	}
-    }
-    else
-    {
-	IxQMgrQEntrySizeInWords entrySizeInWords = infoPtr->qEntrySizeInWords;
-	UINT32 i;
-
-	/* write each queue entry */
-	while (numEntries--)
-	{
-	    /* write the queueEntrySize number of words for each entry */
-	    for (i = 0; i < (UINT32)entrySizeInWords; i++)
-	    {
-		IX_QMGR_INLINE_WRITE_LONG((infoPtr->qAccRegAddr + i), *entries);
-		entries++;
-	    }
-	}
-    }
-
-    /* check if the write count overflows */
-    if (infoPtr->qWriteCount > infoPtr->qSizeInEntries)
-    {
-	/* reset the current write count */
-	infoPtr->qWriteCount = infoPtr->qSizeInEntries;
-    }
-
-    /* Check if overflow occurred on the write operation */
-    if (qId < IX_QMGR_MIN_QUEUPP_QID)
-    {
-	/* get the queue status */
-	status = IX_QMGR_INLINE_READ_LONG(infoPtr->qUOStatRegAddr);
-
-	/* read the status twice because the status may 
-	 * not be ready at the time of the write
-	 */
-	if ((status & infoPtr->qOflowStatBitMask) ||
-	    ((status = IX_QMGR_INLINE_READ_LONG(infoPtr->qUOStatRegAddr))
-	     & infoPtr->qOflowStatBitMask))
-	{
-	    /* clear the underflow status bit if it was set */
-	    IX_QMGR_INLINE_WRITE_LONG(infoPtr->qUOStatRegAddr,
-				 status & ~infoPtr->qOflowStatBitMask);
-	    return IX_QMGR_Q_OVERFLOW;
-	}
-    }
-
-    return IX_SUCCESS;
-}
-#endif
-
-/**
- * @ingroup IxQMgrAPI
- * 
- * @fn ixQMgrQPoke (IxQMgrQId qId,
-	     unsigned int entryIndex,
-	     UINT32 *entry)
- *
- * @brief Write an entry to a queue without moving the write pointer.
- *
- * This function modifies an entry in a queue. The entry is modified directly
- * in AQM SRAM and not using the queue access registers. The entry is NOT added to the
- * queue and the read/write pointers are unchanged.
- * N.B: The queue should not be accessed when this function is called.
- *
- * @param qId @ref IxQMgrQId [in]  - the queue identifier.
- * @param  entryIndex unsigned int [in] - index of entry in queue in the range
- *                          [0].......[current number of entries in queue].
- * @param  *entry UINT32 [in] - pointer to the entry word(s).
- *
- * @return @li IX_SUCCESS, entry was successfully modified.
- * @return @li IX_QMGR_PARAMETER_ERROR, invalid paramter(s).
- * @return @li IX_QMGR_Q_NOT_CONFIGURED, queue not configured for this QId.
- * @return @li IX_QMGR_ENTRY_INDEX_OUT_OF_BOUNDS, an entry does not exist at
- *             specified index.
- * @return @li IX_FAIL, failed to modify the queue entry.
- */
-PUBLIC IX_STATUS
-ixQMgrQPoke (IxQMgrQId qId,
-	     unsigned int entryIndex,
-	     UINT32 *entry);
-
-/**
- *
- * @ingroup IxQMgrAPI
- * 
- * @fn ixQMgrQNumEntriesGet (IxQMgrQId qId,
-		      unsigned *numEntries)
- *
- * @brief Get a snapshot of the number of entries in a queue.
- *
- * This function gets the number of entries in a queue.
- *
- * @param qId @ref IxQMgrQId [in] qId - the queue idenfifier
- * @param *numEntries unsigned [out] - the number of entries in a queue
- *
- * @return @li IX_SUCCESS, got the number of entries for the queue
- * @return @li IX_QMGR_PARAMETER_ERROR, invalid paramter(s).
- * @return @li IX_QMGR_Q_NOT_CONFIGURED, the specified qId has not been configured
- * @return @li IX_QMGR_WARNING, could not determine num entries at this time
- *
- */
-PUBLIC IX_STATUS
-ixQMgrQNumEntriesGet (IxQMgrQId qId,
-		      unsigned *numEntries);
-
-/**
- *
- * @ingroup IxQMgrAPI
- *
- * @fn ixQMgrQStatusGetWithChecks (IxQMgrQId qId,
-                            IxQMgrQStatus *qStatus)
- *
- * @brief Get a queues status.
- *
- * This function reads the specified queues status. A queues status is defined
- * by its status flags. For queues 0-31 these flags are E,NE,NF,F. For
- * queues 32-63 these flags are NE and F.
- *
- * @param qId @ref IxQMgrQId [in] - the queue identifier.
- * @param &qStatus @ref IxQMgrQStatus [out] - the status of the specified queue.
- *
- * @return @li IX_SUCCESS, queue status was successfully read.
- * @return @li IX_QMGR_Q_NOT_CONFIGURED, the specified qId has not been configured
- * @return @li IX_QMGR_PARAMETER_ERROR, invalid paramter.
- *
- */
-PUBLIC IX_STATUS
-ixQMgrQStatusGetWithChecks (IxQMgrQId qId,
-                            IxQMgrQStatus *qStatus);
-
-/**
- *
- * @ingroup IxQMgrAPI
- * 
- * @fn ixQMgrQStatusGet (IxQMgrQId qId,
-		  IxQMgrQStatus *qStatus)
- *
- * @brief Fast get of a queue's status.
- *
- * This function is a streamlined version of ixQMgrQStatusGetWithChecks(), but
- * performs essentially the same task.  It reads the specified queue's status.
- * A queues status is defined by its status flags. For queues 0-31 these flags
- * are E,NE,NF,F. For queues 32-63 these flags are NE and F.
- *
- * @note - This function is inlined, to reduce unnecessary function call
- * overhead.  It does not perform any parameter checks, or update any
- * statistics.  Also, it does not check that the queue specified by qId has
- * been configured.  It simply reads the specified queue's status.
- *
- * @param qId @ref IxQMgrQId [in] - the queue identifier.
- * @param *qStatus @ref IxQMgrQStatus [out] - the status of the specified queue.
- *
- * @return @li void.
- *
- */
-
-#ifdef NO_INLINE_APIS
-PUBLIC IX_STATUS
-ixQMgrQStatusGet (IxQMgrQId qId,
-		  IxQMgrQStatus *qStatus);
-#else  
-extern UINT32 ixQMgrAqmIfQueLowStatRegAddr[];
-extern UINT32 ixQMgrAqmIfQueLowStatBitsOffset[];
-extern UINT32 ixQMgrAqmIfQueLowStatBitsMask;
-extern UINT32 ixQMgrAqmIfQueUppStat0RegAddr;
-extern UINT32 ixQMgrAqmIfQueUppStat1RegAddr;
-extern UINT32 ixQMgrAqmIfQueUppStat0BitMask[];
-extern UINT32 ixQMgrAqmIfQueUppStat1BitMask[];
-
-IX_QMGR_INLINE PUBLIC IX_STATUS
-ixQMgrQStatusGet (IxQMgrQId qId,
-		  IxQMgrQStatus *qStatus);
-#endif  /* endif NO_INLINE_APIS */
-
-IX_QMGR_INLINE PUBLIC IX_STATUS
-ixQMgrQStatusGet (IxQMgrQId qId,
-		  IxQMgrQStatus *qStatus)
-#ifdef NO_INLINE_APIS
-    ;
-#else
-{
-    /* read the status of a queue in the range 0-31 */
-    if (qId < IX_QMGR_MIN_QUEUPP_QID)
-    {
-	volatile UINT32 *lowStatRegAddr = (UINT32*)ixQMgrAqmIfQueLowStatRegAddr[qId];
-
-	UINT32 lowStatBitsOffset = ixQMgrAqmIfQueLowStatBitsOffset[qId];
-	UINT32 lowStatBitsMask   = ixQMgrAqmIfQueLowStatBitsMask;
-
-	/* read the status register for this queue */
-	*qStatus = IX_QMGR_INLINE_READ_LONG(lowStatRegAddr);
-
-	/* mask out the status bits relevant only to this queue */
-	*qStatus = (*qStatus >> lowStatBitsOffset) & lowStatBitsMask;
-
-    }
-    else /* read status of a queue in the range 32-63 */
-    {
-
-	volatile UINT32 *qNearEmptyStatRegAddr = (UINT32*)ixQMgrAqmIfQueUppStat0RegAddr;
-	volatile UINT32 *qFullStatRegAddr      = (UINT32*)ixQMgrAqmIfQueUppStat1RegAddr;
-	int maskIndex = qId - IX_QMGR_MIN_QUEUPP_QID;
-	UINT32 qNearEmptyStatBitMask = ixQMgrAqmIfQueUppStat0BitMask[maskIndex];
-	UINT32 qFullStatBitMask      = ixQMgrAqmIfQueUppStat1BitMask[maskIndex];
-
-	/* Reset the status bits */
-	*qStatus = 0;
-
-	/* Check if the queue is nearly empty */
-	if (IX_QMGR_INLINE_READ_LONG(qNearEmptyStatRegAddr) & qNearEmptyStatBitMask)
-	{
-	    *qStatus |= IX_QMGR_Q_STATUS_NE_BIT_MASK;
-	}
-
-	/* Check if the queue is full */
-	if (IX_QMGR_INLINE_READ_LONG(qFullStatRegAddr) & qFullStatBitMask)
-	{
-	    *qStatus |= IX_QMGR_Q_STATUS_F_BIT_MASK;
-	}
-    }
-    return IX_SUCCESS;
-}
-#endif
-
-/* ------------------------------------------------------------
-   Queue dispatch related functions
-   ---------------------------------------------------------- */
-
-/**
- *
- * @ingroup IxQMgrAPI
- * 
- * @fn ixQMgrDispatcherPrioritySet (IxQMgrQId qId,
-			     IxQMgrPriority priority)
- *
- * @brief Set the dispatch priority of a queue.
- *
- * This function is called to set the dispatch priority of queue. The effect of
- * this function is to add a priority change request to a queue. This queue is
- * serviced by @a ixQMgrDispatcherLoopRunA0, @a ixQMgrDispatcherLoopRunB0 or 
- * @a ixQMgrDispatcherLoopRunB0LLP.
- *
- * This function is re-entrant. and can be used from an interrupt context
- *
- * @param qId @ref IxQMgrQId [in] - the queue identifier
- * @param priority @ref IxQMgrPriority [in] - the new queue dispatch priority
- *
- * @return @li IX_SUCCESS, priority change request is queued
- * @return @li IX_QMGR_Q_NOT_CONFIGURED, the specified qId has not been configured
- * @return @li IX_QMGR_Q_INVALID_PRIORITY, specified priority is invalid
- *
- */
-PUBLIC IX_STATUS
-ixQMgrDispatcherPrioritySet (IxQMgrQId qId,
-			     IxQMgrPriority priority);
-/**
- *
- * @ingroup IxQMgrAPI
- * 
- * @fn ixQMgrNotificationEnable (IxQMgrQId qId,
-			  IxQMgrSourceId sourceId)
- *
- * @brief Enable notification on a queue for a specified queue source flag.
- *
- * This function is called by a client of the QMgr to enable notifications on a
- * specified condition.
- * If the condition for the notification is set after the client has called this
- * function but before the function has enabled the interrupt source, then the
- * notification will not occur.
- * For queues 32-63 the notification source is fixed to the NE(Nearly Empty) flag
- * and cannot be changed so the sourceId parameter is ignored for these queues.
- * The status register is read before the notofication is enabled and is read again
- * after the notification has been enabled, if they differ then the warning status
- * is returned.
- *
- * This function is re-entrant. and can be used from an interrupt context
- *
- * @param qId @ref IxQMgrQId [in] - the queue identifier
- * @param sourceId @ref IxQMgrSourceId [in] - the interrupt src condition identifier
- *
- * @return @li IX_SUCCESS, the interrupt has been enabled for the specified source
- * @return @li IX_QMGR_Q_NOT_CONFIGURED, the specified qId has not been configured
- * @return @li IX_QMGR_INVALID_INT_SOURCE_ID, interrupt source invalid for this queue
- * @return @li IX_QMGR_WARNING, the status register may not be constistent
- *
- */
-PUBLIC IX_STATUS
-ixQMgrNotificationEnable (IxQMgrQId qId,
-			  IxQMgrSourceId sourceId);
-
-/**
- * @ingroup IxQMgrAPI
- * 
- * @fn ixQMgrNotificationDisable (IxQMgrQId qId)
- *
- * @brief Disable notifications on a queue.
- *
- * This function is called to disable notifications on a specified queue.
- *
- * This function is re-entrant. and can be used from an interrupt context
- *
- * @param qId @ref IxQMgrQId [in] - the queue identifier
- *
- * @return @li IX_SUCCESS, the interrupt has been disabled
- * @return @li IX_QMGR_Q_NOT_CONFIGURED, the specified qId has not been configured
- *
- */
-PUBLIC IX_STATUS
-ixQMgrNotificationDisable (IxQMgrQId qId);
-
-/**
- *
- * @ingroup IxQMgrAPI
- * 
- * @fn ixQMgrDispatcherLoopRunA0 (IxQMgrDispatchGroup group)
- *
- * @brief Run the callback dispatcher.
- *
- * This function runs the dispatcher for a group of queues.
- * Callbacks are made for interrupts that have occurred on queues within
- * the group that have registered callbacks. The order in which queues are
- * serviced depends on the queue priorities set by the client.
- * This function may be called from interrupt or task context.
- * For optimisations that were introduced in IXP42X B0 and supported IXP46X
- * the @a ixQMgrDispatcherLoopRunB0, or @a ixQMgrDispatcherLoopRunB0LLP 
- * should be used.
- *
- * This function is not re-entrant.
- *
- * @param group @ref IxQMgrDispatchGroup [in] - the group of queues over which the
- *                                        dispatcher will run
- *
- * @return @li void
- *
- * @note This function may be called from interrupt or task context.
- * However, for optimal performance the choice of context depends also on the
- * operating system used.
- *
- */
-PUBLIC void
-ixQMgrDispatcherLoopRunA0 (IxQMgrDispatchGroup group);
-
-/**
- *
- * @ingroup IxQMgrAPI
- * 
- * @fn ixQMgrDispatcherLoopRunB0 (IxQMgrDispatchGroup group)
- *
- * @brief Run the callback dispatcher.
- *
- * The enhanced version of @a ixQMgrDispatcherLoopRunA0 that is optimised for
- * features introduced in IXP42X B0 silicon and supported on IXP46X. 
- * This is the default dispatcher for IXP42X B0 and IXP46X silicon. 
- * The function runs the dispatcher for a group of queues.
- * Callbacks are made for interrupts that have occurred on queues within
- * the group that have registered callbacks. The order in which queues are
- * serviced depends on the queue priorities set by the client.
- * This  function may be called from interrupt or task context.
- *
- * This function is not re-entrant.
- *
- * @param group @ref IxQMgrDispatchGroup [in] - the group of queues over which the
- *                                        dispatcher will run
- *
- * @return @li void
- *
- *
- * @note This function may be called from interrupt or task context.
- * However, for optimal performance the choice of context depends also on the
- * operating system used.
- *
- */
-PUBLIC void
-ixQMgrDispatcherLoopRunB0 (IxQMgrDispatchGroup group);
-
-/**
- *
- * @ingroup IxQMgrAPI
- * 
- * @fn ixQMgrDispatcherLoopRunB0LLP (IxQMgrDispatchGroup group)
- *
- * @brief Run the callback dispatcher.
- *
- * This is a version of the optimised dispatcher for IXP42X B0 and IXP46X, 
- * @a ixQMgrDispatcherLoopRunB0, with added support for livelock prevention. 
- * This dispatcher will only be used for the IXP42X B0 or IXP46X silicon if 
- * feature control indicates that IX_FEATURECTRL_ORIGB0_DISPATCHER is set to   
- * IX_FEATURE_CTRL_SWCONFIG_DISABLED. Otherwise the @a ixQMgrDispatcherLoopRunB0 
- * dispatcher will be used (Default). 
- *
- * When this dispatcher notifies for a queue that is type
- * IX_QMGR_TYPE_REALTIME_PERIODIC, notifications for queues that are set
- * as type IX_QMGR_REALTIME_SPORADIC are not processed and disabled.
- * This helps prevent any tasks resulting from the notification of the 
- * IX_QMGR_TYPE_REALTIME_PERIODIC type queue to being subject to livelock.
- * The function runs the dispatcher for a group of queues.
- * Callbacks are made for interrupts that have occurred on queues within
- * the group that have registered callbacks. The order in which queues are
- * serviced depends on their type along with the  queue priorities set by the 
- * client. This function may be called from interrupt or task context.
- *
- * This function is not re-entrant.
- *
- * @param group @ref IxQMgrDispatchGroup [in] - the group of queues over which 
- *                                        the dispatcher will run
- *
- * @return @li void
- *
- * @note This function may be called from interrupt or task context.
- * However, for optimal performance the choice of context depends also on the
- * operating system used.
- *
- */
-PUBLIC void
-ixQMgrDispatcherLoopRunB0LLP (IxQMgrDispatchGroup group);
-
-/**
- *
- * @ingroup IxQMgrAPI
- * 
- * @fn ixQMgrNotificationCallbackSet (IxQMgrQId qId,
-			       IxQMgrCallback callback,
-			       IxQMgrCallbackId callbackId)
- *
- * @brief Set the notification callback for a queue.
- *
- * This function sets the callback for the specified queue. This callback will
- * be called by the dispatcher, and may be called in the context of a interrupt
- * If callback has a value of NULL the previously registered callback, if one
- * exists will be unregistered.
- *
- * @param qId @ref IxQMgrQId [in] - the queue idenfifier
- * @param callback @ref IxQMgrCallback  [in] - the callback registered for this queue
- * @param callbackId @ref IxQMgrCallbackId [in] - the callback identifier
- *
- * @return @li IX_SUCCESS, the callback for the specified queue has been set
- * @return @li IX_QMGR_Q_NOT_CONFIGURED, the specified qId has not been configured
- *
- */
-PUBLIC IX_STATUS
-ixQMgrNotificationCallbackSet (IxQMgrQId qId,
-			       IxQMgrCallback callback,
-			       IxQMgrCallbackId callbackId);
-
-/**
- *
- * @ingroup IxQMgrAPI
- *
- * @fn ixQMgrDispatcherLoopGet (IxQMgrDispatcherFuncPtr *qDispatcherFuncPtr)
- *
- * @brief Get QMgr DispatcherLoopRun for respective silicon device
- *
- * This function gets a function pointer to ixQMgrDispatcherLoopRunA0() for IXP42X A0
- * Silicon. If the IXP42X B0 or 46X Silicon, the default is the ixQMgrDispatcherLoopRunB0()
- * function, however if live lock prevention is enabled a function pointer to
- * ixQMgrDispatcherLoopRunB0LLP() is given.
- *
- * @param *qDispatchFuncPtr @ref IxQMgrDispatcherFuncPtr [out]  - 
- *              the function pointer of QMgr Dispatcher
- *
- */
-PUBLIC void
-ixQMgrDispatcherLoopGet (IxQMgrDispatcherFuncPtr *qDispatcherFuncPtr);
-
-/**
- *
- * @ingroup IxQMgrAPI
- *
- * @fn ixQMgrStickyInterruptRegEnable(void)
- *
- * @brief Enable AQM's sticky interrupt register behaviour only available
- *        on B0 Silicon. 
- * 
- * When AQM's sticky interrupt register is enabled, interrupt register bit will
- * only be cleared when a '1' is written to interrupt register bit and the
- * interrupting condition is satisfied, i.e.queue condition does not exist.
- * 
- * @note This function must be called before any queue is enabled.
- *       Calling this function after queue is enabled will cause
- *       undefined results. 
- *
- * @return none
- *
- */
-PUBLIC void
-ixQMgrStickyInterruptRegEnable(void);
-
-
-/**
- * @ingroup IxQMgrAPI
- *
- * @fn ixQMgrCallbackTypeSet(IxQMgrQId qId,
-                             IxQMgrType type)
- *
- * @brief Set the Callback Type of a queue.
- *
- * This function is only used for live lock prevention.
- * This function allows the callback type of a queue to be set. The default for
- * all queues is IX_QMGR_TYPE_REALTIME_OTHER. Setting the type to
- * IX_QMGR_TYPE_REALTIME_SPORADIC means that this queue will have it's 
- * notifications disabled while there is a task associated with a 
- * queue of type IX_QMGR_TYPE_REALTIME_PERIODIC running. As live lock
- * prevention operates on lower queues, this function should
- * be called for lower queues only.
- * This function is not re-entrant.  
- *
- * @param qId @ref IxQMgrQId [in] - the queue identifier
- * @param type @ref IxQMgrType [in] - the type of callback
- *
- * @return @li IX_SUCCESS, successfully set callback type for the queue entry
- * @return @li IX_QMGR_Q_NOT_CONFIGURED, queue not configured for this QId
- * @return @li IX_QMGR_PARAMETER_ERROR, invalid parameter(s).
- *
- */
-PUBLIC IX_STATUS
-ixQMgrCallbackTypeSet(IxQMgrQId qId,
-                      IxQMgrType type);
-
-/**
- * @ingroup IxQMgrAPI
- *
- * @fn ixQMgrCallbackTypeGet(IxQMgrQId qId,
-                             IxQMgrType *type)
- *
- * @brief Get the Callback Type of a queue.
- *
- * This function allows the callback type of a queue to be got. As live lock
- * prevention operates on lower queues, this function should
- * be called for lower queues only.
- * This function is re-entrant.
- *
- * @param qId @ref IxQMgrQId [in] - the queue identifier
- * @param *type @ref IxQMgrType [out] - the type of callback
- *
- * @return @li IX_SUCCESS, successfully set callback type for the queue entry
- * @return @li IX_QMGR_Q_NOT_CONFIGURED, queue not configured for this QId
- * @return @li IX_QMGR_PARAMETER_ERROR, invalid parameter(s)
- *
- */
-PUBLIC IX_STATUS
-ixQMgrCallbackTypeGet(IxQMgrQId qId,
-                      IxQMgrType *type);
-
-/**
- * @ingroup IxQMgrAPI
- *
- * @fn ixQMgrPeriodicDone(void)
- *
- * @brief Indicate that the Periodic task is completed for LLP
- *
- * This function is used as part of live lock prevention. 
- * A periodic task is a task that results from a queue that 
- * is set as type IX_QMGR_TYPE_REALTIME_PERIODIC. This function 
- * should be called to indicate to the dispatcher that the
- * the periodic task is completed. This ensures that the notifications
- * for queues set as type sporadic queues are re-enabled.
- * This function is re-entrant.
- *
- */
-PUBLIC void
-ixQMgrPeriodicDone(void);
-
-
-/**
- * @ingroup IxQMgrAPI
- *
- * @fn ixQMgrLLPShow(int resetStats)
- *
- * @brief Print out the live lock prevention statistics when in debug mode.
- *
- * This function prints out statistics related to the livelock. These
- * statistics are only collected in debug mode.
- * This function is not re-entrant.
- *
- * @param resetStats @ref int [in] - if set the the stats are reset.
- *
- */
-PUBLIC void
-ixQMgrLLPShow(int resetStats);
-
-
-#endif /* IXQMGR_H */
-
-/**
- * @} defgroup IxQMgrAPI
- */
-
-
diff --git a/drivers/net/npe/include/IxQMgrAqmIf_p.h b/drivers/net/npe/include/IxQMgrAqmIf_p.h
deleted file mode 100644
index 1b9cfd2e38..0000000000
--- a/drivers/net/npe/include/IxQMgrAqmIf_p.h
+++ /dev/null
@@ -1,903 +0,0 @@
-/**
- * @file    IxQMgrAqmIf_p.h
- *
- * @author Intel Corporation
- * @date    30-Oct-2001
- *
- * @brief   The IxQMgrAqmIf sub-component provides a number of inline
- * functions for performing I/O on the AQM. 
- *
- * Because  some functions contained in this module are inline and are
- * used in other modules (within the QMgr component) the definitions are
- * contained in this header file. The "normal" use of inline functions
- * is to use the inline functions in the module in which they are
- * defined. In this case these inline functions are used in external
- * modules and therefore the use of "inline extern". What this means
- * is as follows: if a function foo is declared as "inline extern"this
- * definition is only used for inlining, in no case is the function
- * compiled on its own. If the compiler cannot inline the function it
- * becomes an external reference. Therefore in IxQMgrAqmIf.c all
- * inline functions are defined without the "inline extern" specifier
- * and so define the external references. In all other modules these
- * funtions are defined as "inline extern".
- *
- * 
- * @par
- * IXP400 SW Release version 2.0
- * 
- * -- Copyright Notice --
- * 
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- * 
- * @par
- * SPDX-License-Identifier:	BSD-3-Clause
- * @par
- * -- End of Copyright Notice --
-*/
-
-#ifndef IXQMGRAQMIF_P_H
-#define IXQMGRAQMIF_P_H
-
-#include "IxOsalTypes.h"
-
-/*
- * inline definition
- */
- 
-#ifdef IX_OSAL_INLINE_ALL
-/* If IX_OSAL_INLINE_ALL is set then each inlineable API functions will be defined as
-   inline functions */
-#define IX_QMGR_AQMIF_INLINE IX_OSAL_INLINE_EXTERN
-#else   
-#ifdef IXQMGRAQMIF_C
-#ifndef IX_QMGR_AQMIF_INLINE
-#define IX_QMGR_AQMIF_INLINE
-#endif
-#else  
-#ifndef IX_QMGR_AQMIF_INLINE
-#define IX_QMGR_AQMIF_INLINE IX_OSAL_INLINE_EXTERN
-#endif
-#endif /* IXQMGRAQMIF_C */
-#endif /* IX_OSAL_INLINE */
-
-
-/*
- * User defined include files.
- */
-#include "IxQMgr.h"
-#include "IxQMgrLog_p.h"
-#include "IxQMgrQCfg_p.h"
-
-/* Because this file contains inline functions which will be compiled into
- * other components, we need to ensure that the IX_COMPONENT_NAME define
- * is set to ix_qmgr while this code is being compiled.  This will ensure
- * that the correct implementation is provided for the memory access macros
- * IX_OSAL_READ_LONG and IX_OSAL_WRITE_LONG which are used in this file.
- * This must be done before including "IxOsalMemAccess.h"
- */
-#define IX_QMGR_AQMIF_SAVED_COMPONENT_NAME IX_COMPONENT_NAME
-#undef  IX_COMPONENT_NAME
-#define IX_COMPONENT_NAME ix_qmgr
-#include "IxOsal.h" 
-
-/*
- * #defines and macros used in this file.
- */
-
-/* Number of bytes per word */
-#define IX_QMGR_NUM_BYTES_PER_WORD 4
-
-/* Underflow bit mask  */
-#define IX_QMGR_UNDERFLOW_BIT_OFFSET    0x0
-
-/* Overflow bit mask */
-#define IX_QMGR_OVERFLOW_BIT_OFFSET     0x1
-
-/* Queue access register, queue 0 */
-#define IX_QMGR_QUEACC0_OFFSET      0x0000
-
-/* Size of queue access register in words */
-#define IX_QMGR_QUEACC_SIZE         0x4/*words*/
-
-/* Queue status register, queues 0-7 */
-#define IX_QMGR_QUELOWSTAT0_OFFSET  (IX_QMGR_QUEACC0_OFFSET +\
-(IX_QMGR_MAX_NUM_QUEUES * IX_QMGR_QUEACC_SIZE * IX_QMGR_NUM_BYTES_PER_WORD))
-
-/* Queue status register, queues 8-15 */
-#define IX_QMGR_QUELOWSTAT1_OFFSET  (IX_QMGR_QUELOWSTAT0_OFFSET +\
-                                     IX_QMGR_NUM_BYTES_PER_WORD)
-
-/* Queue status register, queues 16-23 */
-#define IX_QMGR_QUELOWSTAT2_OFFSET  (IX_QMGR_QUELOWSTAT1_OFFSET +\
-                                     IX_QMGR_NUM_BYTES_PER_WORD)
-
-/* Queue status register, queues 24-31 */
-#define IX_QMGR_QUELOWSTAT3_OFFSET  (IX_QMGR_QUELOWSTAT2_OFFSET +\
-                                     IX_QMGR_NUM_BYTES_PER_WORD)
-
-/* Queue status register Q status bits mask */
-#define IX_QMGR_QUELOWSTAT_QUE_STS_BITS_MASK 0xF
-
-/* Size of queue 0-31 status register */
-#define IX_QMGR_QUELOWSTAT_SIZE     0x4 /*words*/
-
-/* The number of queues' status specified per word */
-#define IX_QMGR_QUELOWSTAT_NUM_QUE_PER_WORD 0x8
-
-/* Queue UF/OF status register queues 0-15  */
-#define IX_QMGR_QUEUOSTAT0_OFFSET   (IX_QMGR_QUELOWSTAT3_OFFSET +\
-                                     IX_QMGR_NUM_BYTES_PER_WORD)
-/* Queue UF/OF status register queues 16-31 */
-#define IX_QMGR_QUEUOSTAT1_OFFSET   (IX_QMGR_QUEUOSTAT0_OFFSET +\
-                                     IX_QMGR_NUM_BYTES_PER_WORD)
-
-/* The number of queues' underflow/overflow status specified per word */
-#define IX_QMGR_QUEUOSTAT_NUM_QUE_PER_WORD 0x10
-
-/* Queue NE status register, queues 32-63   */
-#define IX_QMGR_QUEUPPSTAT0_OFFSET  (IX_QMGR_QUEUOSTAT1_OFFSET +\
-                                     IX_QMGR_NUM_BYTES_PER_WORD)
-
-/* Queue F status register, queues 32-63    */
-#define IX_QMGR_QUEUPPSTAT1_OFFSET  (IX_QMGR_QUEUPPSTAT0_OFFSET +\
-                                     IX_QMGR_NUM_BYTES_PER_WORD)
-
-/* Size of queue 32-63 status register */
-#define IX_QMGR_QUEUPPSTAT_SIZE     0x2 /*words*/
-
-/* The number of queues' status specified per word */
-#define IX_QMGR_QUEUPPSTAT_NUM_QUE_PER_WORD 0x20
-
-/* Queue INT source select register, queues 0-7   */
-#define IX_QMGR_INT0SRCSELREG0_OFFSET (IX_QMGR_QUEUPPSTAT1_OFFSET   +\
-                                       IX_QMGR_NUM_BYTES_PER_WORD)
-
-/* Queue INT source select register, queues 8-15  */
-#define IX_QMGR_INT0SRCSELREG1_OFFSET (IX_QMGR_INT0SRCSELREG0_OFFSET+\
-                                       IX_QMGR_NUM_BYTES_PER_WORD)
-
-/* Queue INT source select register, queues 16-23 */
-#define IX_QMGR_INT0SRCSELREG2_OFFSET (IX_QMGR_INT0SRCSELREG1_OFFSET+\
-                                       IX_QMGR_NUM_BYTES_PER_WORD)
-
-/* Queue INT source select register, queues 24-31 */
-#define IX_QMGR_INT0SRCSELREG3_OFFSET (IX_QMGR_INT0SRCSELREG2_OFFSET+\
-                                       IX_QMGR_NUM_BYTES_PER_WORD)
-
-/* Size of interrupt source select reegister */
-#define IX_QMGR_INT0SRCSELREG_SIZE  0x4 /*words*/
-
-/* The number of queues' interrupt source select specified per word*/
-#define IX_QMGR_INTSRC_NUM_QUE_PER_WORD 0x8
-
-/* Queue INT enable register, queues 0-31  */
-#define IX_QMGR_QUEIEREG0_OFFSET    (IX_QMGR_INT0SRCSELREG3_OFFSET +\
-                                     IX_QMGR_NUM_BYTES_PER_WORD)
-
-/* Queue INT enable register, queues 32-63 */
-#define IX_QMGR_QUEIEREG1_OFFSET    (IX_QMGR_QUEIEREG0_OFFSET      +\
-                                     IX_QMGR_NUM_BYTES_PER_WORD)
-
-/* Queue INT register, queues 0-31  */
-#define IX_QMGR_QINTREG0_OFFSET     (IX_QMGR_QUEIEREG1_OFFSET +\
-                                     IX_QMGR_NUM_BYTES_PER_WORD)
-
-/* Queue INT register, queues 32-63 */
-#define IX_QMGR_QINTREG1_OFFSET     (IX_QMGR_QINTREG0_OFFSET  +\
-                                     IX_QMGR_NUM_BYTES_PER_WORD)
-
-/* Size of interrupt register */
-#define IX_QMGR_QINTREG_SIZE        0x2 /*words*/
-
-/* Number of queues' status specified per word */
-#define IX_QMGR_QINTREG_NUM_QUE_PER_WORD 0x20
-
-/* Number of bits per queue interrupt status */
-#define IX_QMGR_QINTREG_BITS_PER_QUEUE 0x1
-#define IX_QMGR_QINTREG_BIT_OFFSET 0x1
-
-/* Size of address space not used by AQM */
-#define IX_QMGR_AQM_UNUSED_ADDRESS_SPACE_SIZE_IN_BYTES  0x1bC0
-
-/* Queue config register, queue 0 */
-#define IX_QMGR_QUECONFIG_BASE_OFFSET (IX_QMGR_QINTREG1_OFFSET +\
-                             IX_QMGR_NUM_BYTES_PER_WORD +\
-                             IX_QMGR_AQM_UNUSED_ADDRESS_SPACE_SIZE_IN_BYTES)
-
-/* Total size of configuration words */
-#define IX_QMGR_QUECONFIG_SIZE      0x100
-
-/* Start of SRAM queue buffer space */
-#define IX_QMGR_QUEBUFFER_SPACE_OFFSET (IX_QMGR_QUECONFIG_BASE_OFFSET +\
-                                 IX_QMGR_MAX_NUM_QUEUES * IX_QMGR_NUM_BYTES_PER_WORD)
-
-/* Total bits in a word */
-#define BITS_PER_WORD 32
-
-/* Size of queue buffer space */
-#define IX_QMGR_QUE_BUFFER_SPACE_SIZE 0x1F00
-
-/*
- * This macro will return the address of the access register for the
- * queue  specified by qId
- */
-#define IX_QMGR_Q_ACCESS_ADDR_GET(qId)\
-        (((qId) * (IX_QMGR_QUEACC_SIZE * IX_QMGR_NUM_BYTES_PER_WORD))\
-	 + IX_QMGR_QUEACC0_OFFSET)
-
-/* 
- * Bit location of bit-3 of INT0SRCSELREG0 register to enabled
- * sticky interrupt register.
- */
-#define IX_QMGR_INT0SRCSELREG0_BIT3 3
-
-/*
- * Variable declerations global to this file. Externs are followed by
- * statics.
- */
-extern UINT32 aqmBaseAddress;
-
-/*
- * Function declarations.
- */
-void
-ixQMgrAqmIfInit (void);
-
-void
-ixQMgrAqmIfUninit (void);
-
-unsigned
-ixQMgrAqmIfLog2 (unsigned number);
-
-void
-ixQMgrAqmIfQRegisterBitsWrite (IxQMgrQId qId, 
-			       UINT32 registerBaseAddrOffset,
-			       unsigned queuesPerRegWord,
-			       UINT32 value);
-
-void
-ixQMgrAqmIfQStatusCheckValsCalc (IxQMgrQId qId,
-				 IxQMgrSourceId srcSel,
-				 unsigned int *statusWordOffset,
-				 UINT32 *checkValue,
-				 UINT32 *mask);
-/*
- * The Xscale software allways deals with logical addresses and so the
- * base address of the AQM memory space is not a hardcoded value. This
- * function must be called before any other function in this component.
- * NO CHECKING is performed to ensure that the base address has been
- * set.
- */
-void
-ixQMgrAqmIfBaseAddressSet (UINT32 address);
-
-/*
- * Get the base address of the AQM memory space.
- */
-void
-ixQMgrAqmIfBaseAddressGet (UINT32 *address);
-
-/*
- * Get the sram base address
- */
-void
-ixQMgrAqmIfSramBaseAddressGet (UINT32 *address);
-
-/*
- * Read a queue status
- */
-void
-ixQMgrAqmIfQueStatRead (IxQMgrQId qId,
-			IxQMgrQStatus* status);
-
-
-/*
- *   Set INT0SRCSELREG0 Bit3 
- */ 
-void ixQMgrAqmIfIntSrcSelReg0Bit3Set (void);
-
-
-/*
- * Set the interrupt source
- */
-void
-ixQMgrAqmIfIntSrcSelWrite (IxQMgrQId qId,
-			   IxQMgrSourceId sourceId);
-
-/*
- * Enable interruptson a queue
- */
-void
-ixQMgrAqmIfQInterruptEnable (IxQMgrQId qId);
-
-/*
- * Disable interrupt on a quee
- */
-void
-ixQMgrAqmIfQInterruptDisable (IxQMgrQId qId);
-
-/*
- * Write the config register of the specified queue
- */
-void
-ixQMgrAqmIfQueCfgWrite (IxQMgrQId qId,
-			IxQMgrQSizeInWords qSizeInWords,
-			IxQMgrQEntrySizeInWords entrySizeInWords,
-			UINT32 freeSRAMAddress);
-
-/*
- * read fields from the config of the specified queue.
- */
-void
-ixQMgrAqmIfQueCfgRead (IxQMgrQId qId,
-		       unsigned int numEntries,
-		       UINT32 *baseAddress,
-		       unsigned int *ne,
-		       unsigned int *nf,
-		       UINT32 *readPtr,
-		       UINT32 *writePtr);
-
-/*
- * Set the ne and nf watermark level on a queue.
- */
-void
-ixQMgrAqmIfWatermarkSet (IxQMgrQId qId,
-			 unsigned ne,
-			 unsigned nf);
-
-/* Inspect an entry without moving the read pointer */
-IX_STATUS
-ixQMgrAqmIfQPeek (IxQMgrQId qId,
-		  unsigned int entryIndex,
-		  unsigned int *entry);
-
-/* Modify an entry without moving the write pointer */
-IX_STATUS
-ixQMgrAqmIfQPoke (IxQMgrQId qId,
-		  unsigned int entryIndex,
-		  unsigned int *entry);
-
-/*
- * Function prototype for inline functions. For description refers to 
- * the functions defintion below.
- */
-IX_QMGR_AQMIF_INLINE void
-ixQMgrAqmIfWordWrite (VUINT32 *address,
-		      UINT32 word);
-
-IX_QMGR_AQMIF_INLINE void
-ixQMgrAqmIfWordRead (VUINT32 *address,
-		     UINT32 *word);
-
-IX_QMGR_AQMIF_INLINE void
-ixQMgrAqmIfQPop (IxQMgrQId qId,
-		 IxQMgrQEntrySizeInWords numWords,
-		 UINT32 *entry);
-
-IX_QMGR_AQMIF_INLINE void
-ixQMgrAqmIfQPush (IxQMgrQId qId,
-		  IxQMgrQEntrySizeInWords numWords,
-		  UINT32 *entry);
-
-IX_QMGR_AQMIF_INLINE void
-ixQMgrAqmIfQStatusRegsRead (IxQMgrDispatchGroup group, 
-			    UINT32 *qStatusWords);
-
-IX_QMGR_AQMIF_INLINE BOOL
-ixQMgrAqmIfQStatusCheck (UINT32 *oldQStatusWords,
-			 UINT32 *newQStatusWords,
-			 unsigned int statusWordOffset,			 
-			 UINT32 checkValue,
-			 UINT32 mask);
-
-IX_QMGR_AQMIF_INLINE BOOL
-ixQMgrAqmIfRegisterBitCheck (IxQMgrQId qId, 
-			     UINT32 registerBaseAddrOffset,
-			     unsigned queuesPerRegWord,
-			     unsigned relativeBitOffset,
-			     BOOL reset);
-
-IX_QMGR_AQMIF_INLINE BOOL
-ixQMgrAqmIfUnderflowCheck (IxQMgrQId qId);
-
-IX_QMGR_AQMIF_INLINE BOOL
-ixQMgrAqmIfOverflowCheck (IxQMgrQId qId);
-
-IX_QMGR_AQMIF_INLINE UINT32
-ixQMgrAqmIfQRegisterBitsRead (IxQMgrQId qId, 
-			      UINT32 registerBaseAddrOffset,
-			      unsigned queuesPerRegWord);
-IX_QMGR_AQMIF_INLINE void
-ixQMgrAqmIfQInterruptRegWrite (IxQMgrDispatchGroup group, 
-			       UINT32 reg);
-IX_QMGR_AQMIF_INLINE void
-ixQMgrAqmIfQInterruptRegRead (IxQMgrDispatchGroup group, 
-			      UINT32 *regVal);
-
-IX_QMGR_AQMIF_INLINE void
-ixQMgrAqmIfQueLowStatRead (IxQMgrQId qId,
-			   IxQMgrQStatus *status);
-
-IX_QMGR_AQMIF_INLINE void
-ixQMgrAqmIfQueUppStatRead (IxQMgrQId qId,
-			   IxQMgrQStatus *status);
-
-IX_QMGR_AQMIF_INLINE void
-ixQMgrAqmIfQueStatRead (IxQMgrQId qId, 
-			IxQMgrQStatus *qStatus);
-
-IX_QMGR_AQMIF_INLINE unsigned
-ixQMgrAqmIfPow2NumDivide (unsigned numerator, 
-			  unsigned denominator);
-
-IX_QMGR_AQMIF_INLINE void
-ixQMgrAqmIfQInterruptEnableRegRead (IxQMgrDispatchGroup group, 
-			            UINT32 *regVal);
-/*
- * Inline functions
- */
-
-/*
- * This inline function is used by other QMgr components to write one
- * word to the specified address.
- */
-IX_QMGR_AQMIF_INLINE void
-ixQMgrAqmIfWordWrite (VUINT32 *address,
-		      UINT32 word)
-{
-    IX_OSAL_WRITE_LONG(address, word);
-}
-
-/*
- * This inline function is used by other QMgr components to read a
- * word from the specified address.
- */
-IX_QMGR_AQMIF_INLINE void
-ixQMgrAqmIfWordRead (VUINT32 *address,
-		     UINT32 *word)
-{
-    *word = IX_OSAL_READ_LONG(address);
-}
-
-
-/*
- * This inline function is used by other QMgr components to pop an
- * entry off the specified queue.
- */
-IX_QMGR_AQMIF_INLINE void
-ixQMgrAqmIfQPop (IxQMgrQId qId,
-		 IxQMgrQEntrySizeInWords numWords,
-		 UINT32 *entry)
-{
-    volatile UINT32 *accRegAddr;
-
-    accRegAddr = (UINT32*)(aqmBaseAddress +
-			   IX_QMGR_Q_ACCESS_ADDR_GET(qId));
-
-    switch (numWords)
-    {
-	case IX_QMGR_Q_ENTRY_SIZE1:
-	    ixQMgrAqmIfWordRead (accRegAddr, entry);
-	    break;
-	case IX_QMGR_Q_ENTRY_SIZE2:
-	    ixQMgrAqmIfWordRead (accRegAddr++, entry++);
-	    ixQMgrAqmIfWordRead (accRegAddr, entry);
-	    break;
-	case IX_QMGR_Q_ENTRY_SIZE4:
-	    ixQMgrAqmIfWordRead (accRegAddr++, entry++);
-	    ixQMgrAqmIfWordRead (accRegAddr++, entry++);
-	    ixQMgrAqmIfWordRead (accRegAddr++, entry++);
-	    ixQMgrAqmIfWordRead (accRegAddr, entry);
-	    break;
-	default:
-	    IX_QMGR_LOG_ERROR0("Invalid Q Entry size passed to ixQMgrAqmIfQPop");
-	    break;
-    }
-}
-
-/*
- * This inline function is used by other QMgr components to push an
- * entry to the specified queue.
- */
-IX_QMGR_AQMIF_INLINE void
-ixQMgrAqmIfQPush (IxQMgrQId qId,
-		  IxQMgrQEntrySizeInWords numWords,
-		  UINT32 *entry)
-{
-    volatile UINT32 *accRegAddr;
-
-    accRegAddr = (UINT32*)(aqmBaseAddress +
-			   IX_QMGR_Q_ACCESS_ADDR_GET(qId));
-    
-    switch (numWords)
-    {
-	case IX_QMGR_Q_ENTRY_SIZE1:
-	    ixQMgrAqmIfWordWrite (accRegAddr, *entry);
-	    break;
-	case IX_QMGR_Q_ENTRY_SIZE2:
-	    ixQMgrAqmIfWordWrite (accRegAddr++, *entry++);
-	    ixQMgrAqmIfWordWrite (accRegAddr, *entry);
-	    break;
-	case IX_QMGR_Q_ENTRY_SIZE4:
-	    ixQMgrAqmIfWordWrite (accRegAddr++, *entry++);
-	    ixQMgrAqmIfWordWrite (accRegAddr++, *entry++);
-	    ixQMgrAqmIfWordWrite (accRegAddr++, *entry++);
-	    ixQMgrAqmIfWordWrite (accRegAddr, *entry);
-	    break;
-	default:
-	    IX_QMGR_LOG_ERROR0("Invalid Q Entry size passed to ixQMgrAqmIfQPush");
-	    break;
-    }
-}
-
-/*
- * The AQM interrupt registers contains a bit for each AQM queue
- * specifying the queue (s) that cause an interrupt to fire. This
- * function is called by IxQMGrDispatcher component.
- */
-IX_QMGR_AQMIF_INLINE void
-ixQMgrAqmIfQStatusRegsRead (IxQMgrDispatchGroup group, 
-			    UINT32 *qStatusWords)
-{
-    volatile UINT32 *regAddress = NULL;
-
-    if (group == IX_QMGR_QUELOW_GROUP)
-    {
-	regAddress = (UINT32*)(aqmBaseAddress +
-			       IX_QMGR_QUELOWSTAT0_OFFSET);
-
-	ixQMgrAqmIfWordRead (regAddress++, qStatusWords++);
-	ixQMgrAqmIfWordRead (regAddress++, qStatusWords++);
-	ixQMgrAqmIfWordRead (regAddress++, qStatusWords++);
-	ixQMgrAqmIfWordRead (regAddress, qStatusWords);
-    }
-    else /* We have the upper queues */
-    {
-       /* Only need to read the Nearly Empty status register for
-	* queues 32-63 as for therse queues the interrtupt source
-	* condition is fixed to Nearly Empty
-	*/
-	regAddress = (UINT32*)(aqmBaseAddress +
-			       IX_QMGR_QUEUPPSTAT0_OFFSET);
-	ixQMgrAqmIfWordRead (regAddress, qStatusWords);
-    }
-}
-
-
-/*
- * This function check if the status for a queue has changed between
- * 2 snapshots and if it has, that the status matches a particular
- * value after masking.
- */
-IX_QMGR_AQMIF_INLINE BOOL
-ixQMgrAqmIfQStatusCheck (UINT32 *oldQStatusWords,
-			 UINT32 *newQStatusWords,
-			 unsigned int statusWordOffset,			 
-			 UINT32 checkValue,
-			 UINT32 mask)
-{
-    if (((oldQStatusWords[statusWordOffset] & mask) != 
-	 (newQStatusWords[statusWordOffset] & mask)) &&
-	((newQStatusWords[statusWordOffset] & mask) == checkValue))
-    {
-	return true;
-    }
-
-    return false;
-}
-
-/*
- * The AQM interrupt register contains a bit for each AQM queue
- * specifying the queue (s) that cause an interrupt to fire. This
- * function is called by IxQMgrDispatcher component.
- */
-IX_QMGR_AQMIF_INLINE void
-ixQMgrAqmIfQInterruptRegRead (IxQMgrDispatchGroup group, 
-			      UINT32 *regVal)
-{
-    volatile UINT32 *regAddress;
-
-    if (group == IX_QMGR_QUELOW_GROUP)
-    {
-	regAddress = (UINT32*)(aqmBaseAddress +
-			       IX_QMGR_QINTREG0_OFFSET);
-    }
-    else
-    {
-	regAddress = (UINT32*)(aqmBaseAddress +
-			       IX_QMGR_QINTREG1_OFFSET);
-    }
-
-    ixQMgrAqmIfWordRead (regAddress, regVal);
-}
-
-/*
- * The AQM interrupt enable register contains a bit for each AQM queue.
- * This function reads the interrupt enable register. This
- * function is called by IxQMgrDispatcher component.
- */
-IX_QMGR_AQMIF_INLINE void
-ixQMgrAqmIfQInterruptEnableRegRead (IxQMgrDispatchGroup group, 
-			            UINT32 *regVal)
-{
-    volatile UINT32 *regAddress;
-
-    if (group == IX_QMGR_QUELOW_GROUP)
-    {
-	regAddress = (UINT32*)(aqmBaseAddress +
-			       IX_QMGR_QUEIEREG0_OFFSET);
-    }
-    else
-    {
-	regAddress = (UINT32*)(aqmBaseAddress +
-			       IX_QMGR_QUEIEREG1_OFFSET);
-    }
-
-    ixQMgrAqmIfWordRead (regAddress, regVal);
-}
-
-
-/*
- * This inline function will read the status bit of a queue
- * specified by qId. If reset is true the bit is cleared.
- */
-IX_QMGR_AQMIF_INLINE BOOL
-ixQMgrAqmIfRegisterBitCheck (IxQMgrQId qId, 
-			     UINT32 registerBaseAddrOffset,
-			     unsigned queuesPerRegWord,
-			     unsigned relativeBitOffset,
-			     BOOL reset)
-{
-    UINT32 actualBitOffset;
-    volatile UINT32 *registerAddress;
-    UINT32 registerWord;
-
-    /*
-     * Calculate the registerAddress
-     * multiple queues split accross registers
-     */
-    registerAddress = (UINT32*)(aqmBaseAddress +
-				registerBaseAddrOffset +
-				((qId / queuesPerRegWord) *
-				 IX_QMGR_NUM_BYTES_PER_WORD));
-
-    /*
-     * Get the status word
-     */
-    ixQMgrAqmIfWordRead (registerAddress, &registerWord);
-    
-    /*
-     * Calculate the actualBitOffset
-     * status for multiple queues stored in one register
-     */
-    actualBitOffset = (relativeBitOffset + 1) <<
-	((qId & (queuesPerRegWord - 1)) * (BITS_PER_WORD / queuesPerRegWord));
-
-    /* Check if the status bit is set */
-    if (registerWord & actualBitOffset)
-    {
-	/* Clear the bit if reset */
-	if (reset)
-	{
-	    ixQMgrAqmIfWordWrite (registerAddress, registerWord & (~actualBitOffset));
-	}
-	return true;
-    }
-
-    /* Bit not set */
-    return false;
-}
-
-
-/*
- * @ingroup IxQmgrAqmIfAPI
- *
- * @brief Read the underflow status of a queue 
- *
- * This inline function will read the underflow status of a queue
- * specified by qId.
- * 
- */
-IX_QMGR_AQMIF_INLINE BOOL
-ixQMgrAqmIfUnderflowCheck (IxQMgrQId qId)
-{
-    if (qId < IX_QMGR_MIN_QUEUPP_QID)
-    {
-	return (ixQMgrAqmIfRegisterBitCheck (qId,
-					     IX_QMGR_QUEUOSTAT0_OFFSET,
-					     IX_QMGR_QUEUOSTAT_NUM_QUE_PER_WORD,
-					     IX_QMGR_UNDERFLOW_BIT_OFFSET,
-					     true/*reset*/));
-    }
-    else
-    {
-	/* Qs 32-63 have no underflow status */
-	return false;
-    }
-}
-
-/*
- * This inline function will read the overflow status of a queue
- * specified by qId.
- */
-IX_QMGR_AQMIF_INLINE BOOL
-ixQMgrAqmIfOverflowCheck (IxQMgrQId qId)
-{
-    if (qId < IX_QMGR_MIN_QUEUPP_QID)
-    {
-	return (ixQMgrAqmIfRegisterBitCheck (qId,
-					     IX_QMGR_QUEUOSTAT0_OFFSET,
-					     IX_QMGR_QUEUOSTAT_NUM_QUE_PER_WORD,
-					     IX_QMGR_OVERFLOW_BIT_OFFSET,
-					     true/*reset*/));
-    }
-    else
-    {
-	/* Qs 32-63 have no overflow status */
-	return false;
-    }
-}
-
-/*
- * This inline function will read the status bits of a queue
- * specified by qId.
- */
-IX_QMGR_AQMIF_INLINE UINT32
-ixQMgrAqmIfQRegisterBitsRead (IxQMgrQId qId, 
-			      UINT32 registerBaseAddrOffset,
-			      unsigned queuesPerRegWord)
-{
-    volatile UINT32 *registerAddress;
-    UINT32 registerWord;
-    UINT32 statusBitsMask;
-    UINT32 bitsPerQueue;
-
-    bitsPerQueue = BITS_PER_WORD / queuesPerRegWord;
-
-    /*
-     * Calculate the registerAddress
-     * multiple queues split accross registers
-     */
-    registerAddress = (UINT32*)(aqmBaseAddress +
-				registerBaseAddrOffset +
-				((qId / queuesPerRegWord) *
-				 IX_QMGR_NUM_BYTES_PER_WORD));
-    /*
-     * Read the status word
-     */
-    ixQMgrAqmIfWordRead (registerAddress, &registerWord);
-    
-
-    /*
-     * Calculate the mask for the status bits for this queue.
-     */
-    statusBitsMask = ((1 << bitsPerQueue) - 1);
-
-    /*
-     * Shift the status word so it is right justified
-     */    
-    registerWord >>= ((qId & (queuesPerRegWord - 1)) * bitsPerQueue);
-
-    /*
-     * Mask out all bar the status bits for this queue
-     */
-    return (registerWord &= statusBitsMask);
-}
-
-/*
- * This function is called by IxQMgrDispatcher to set the contents of
- * the AQM interrupt register.
- */
-IX_QMGR_AQMIF_INLINE void
-ixQMgrAqmIfQInterruptRegWrite (IxQMgrDispatchGroup group, 
-			       UINT32 reg)
-{
-    volatile UINT32 *address;
-
-    if (group == IX_QMGR_QUELOW_GROUP)
-    {
-	address = (UINT32*)(aqmBaseAddress +
-			    IX_QMGR_QINTREG0_OFFSET);
-    }
-    else
-    {
-	address = (UINT32*)(aqmBaseAddress +
-			    IX_QMGR_QINTREG1_OFFSET);
-    }
-
-    ixQMgrAqmIfWordWrite (address, reg);
-}
-
-/*
- * Read the status of a queue in the range 0-31.
- *
- * This function is used by other QMgr components to read the
- * status of the queue specified by qId.
- */
-IX_QMGR_AQMIF_INLINE void
-ixQMgrAqmIfQueLowStatRead (IxQMgrQId qId,
-			   IxQMgrQStatus *status)
-{
-    /* Read the general status bits */
-    *status = ixQMgrAqmIfQRegisterBitsRead (qId,
-					    IX_QMGR_QUELOWSTAT0_OFFSET,
-					    IX_QMGR_QUELOWSTAT_NUM_QUE_PER_WORD);
-}
-
-/*
- * This function will read the status of the queue specified
- * by qId.
- */
-IX_QMGR_AQMIF_INLINE void
-ixQMgrAqmIfQueUppStatRead (IxQMgrQId qId,
-			   IxQMgrQStatus *status)
-{
-    /* Reset the status bits */
-    *status = 0;
-
-    /* 
-     * Check if the queue is nearly empty,
-     * N.b. QUPP stat register contains status for regs 32-63 at each
-     *      bit position so subtract 32 to get bit offset
-     */
-    if (ixQMgrAqmIfRegisterBitCheck ((qId - IX_QMGR_MIN_QUEUPP_QID),
-				     IX_QMGR_QUEUPPSTAT0_OFFSET,
-				     IX_QMGR_QUEUPPSTAT_NUM_QUE_PER_WORD,
-				     0/*relativeBitOffset*/,
-				     false/*!reset*/))
-    {
-	*status |= IX_QMGR_Q_STATUS_NE_BIT_MASK;
-    }
-
-    /* 
-     * Check if the queue is full,
-     * N.b. QUPP stat register contains status for regs 32-63 at each
-     *      bit position so subtract 32 to get bit offset
-     */
-    if (ixQMgrAqmIfRegisterBitCheck ((qId - IX_QMGR_MIN_QUEUPP_QID),
-				     IX_QMGR_QUEUPPSTAT1_OFFSET,
-				     IX_QMGR_QUEUPPSTAT_NUM_QUE_PER_WORD,
-				     0/*relativeBitOffset*/,
-				     false/*!reset*/))
-    {
-	*status |= IX_QMGR_Q_STATUS_F_BIT_MASK;
-    }
-}
-
-/*
- * This function is used by other QMgr components to read the
- * status of the queue specified by qId.
- */
-IX_QMGR_AQMIF_INLINE void
-ixQMgrAqmIfQueStatRead (IxQMgrQId qId, 
-			IxQMgrQStatus *qStatus)
-{
-    if (qId < IX_QMGR_MIN_QUEUPP_QID)
-    {
-	ixQMgrAqmIfQueLowStatRead (qId, qStatus);
-    }
-    else
-    {
-	ixQMgrAqmIfQueUppStatRead (qId, qStatus);
-    }
-}
-
-
-/*
- * This function performs a mod division
- */
-IX_QMGR_AQMIF_INLINE unsigned
-ixQMgrAqmIfPow2NumDivide (unsigned numerator, 
-			  unsigned denominator)
-{
-    /* Number is evenly divisable by 2 */
-    return (numerator >> ixQMgrAqmIfLog2 (denominator));
-}
-
-/* Restore IX_COMPONENT_NAME */
-#undef IX_COMPONENT_NAME
-#define IX_COMPONENT_NAME IX_QMGR_AQMIF_SAVED_COMPONENT_NAME
-
-#endif/*IXQMGRAQMIF_P_H*/
diff --git a/drivers/net/npe/include/IxQMgrDefines_p.h b/drivers/net/npe/include/IxQMgrDefines_p.h
deleted file mode 100644
index 1c5d674ffa..0000000000
--- a/drivers/net/npe/include/IxQMgrDefines_p.h
+++ /dev/null
@@ -1,31 +0,0 @@
-/**
- * @file    IxQMgrDefines_p.h
- *
- * @author Intel Corporation
- * @date    19-Jul-2002
- *
- * @brief   IxQMgr Defines and tuneable constants
- *
- * 
- * @par
- * IXP400 SW Release version 2.0
- * 
- * -- Copyright Notice --
- * 
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- * 
- * @par
- * SPDX-License-Identifier:	BSD-3-Clause
- * @par
- * -- End of Copyright Notice --
-*/
-
-#ifndef IXQMGRDEFINES_P_H
-#define IXQMGRDEFINES_P_H
-
-#define IX_QMGR_PARM_CHECKS_ENABLED   1
-#define IX_QMGR_STATS_UPDATE_ENABLED  1
-
-#endif /* IXQMGRDEFINES_P_H */
diff --git a/drivers/net/npe/include/IxQMgrDispatcher_p.h b/drivers/net/npe/include/IxQMgrDispatcher_p.h
deleted file mode 100644
index b68a3f1327..0000000000
--- a/drivers/net/npe/include/IxQMgrDispatcher_p.h
+++ /dev/null
@@ -1,82 +0,0 @@
-/**
- * @file    IxQMgrDispatcher_p.h
- *
- * @author Intel Corporation
- * @date    07-Feb-2002
- *
- * @brief   This file contains the internal functions for dispatcher
- *
- * 
- * @par
- * IXP400 SW Release version 2.0
- * 
- * -- Copyright Notice --
- * 
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- * 
- * @par
- * SPDX-License-Identifier:	BSD-3-Clause
- * @par
- * -- End of Copyright Notice --
-*/
-
-#ifndef IXQMGRDISPATCHER_P_H
-#define IXQMGRDISPATCHER_P_H
-
-/*
- * User defined include files
- */
-#include "IxQMgr.h"
-
-/*
- * This structure defines the statistic data for a queue
- */
-typedef struct
-{
-    unsigned callbackCnt;       /* Call count of callback                    */
-    unsigned priorityChangeCnt; /* Priority change count                     */
-    unsigned intNoCallbackCnt;  /* Interrupt fired but no callback set count */
-    unsigned intLostCallbackCnt;  /* Interrupt lost and detected ;  SCR541   */
-    BOOL notificationEnabled;    /* Interrupt enabled for this queue         */
-    IxQMgrSourceId srcSel;       /* interrupt source                         */
-    unsigned enableCount;        /* num times notif enabled by LLP           */
-    unsigned disableCount;       /* num of times notif disabled by LLP       */
-} IxQMgrDispatcherQStats;
-
-/*
- * This structure defines statistic data for the disatcher
- */
-typedef struct
- {
-    unsigned loopRunCnt;       /* ixQMgrDispatcherLoopRun count */
-
-    IxQMgrDispatcherQStats queueStats[IX_QMGR_MAX_NUM_QUEUES];
-
-} IxQMgrDispatcherStats;
-
-/*
- * Initialise the dispatcher component
- */
-void
-ixQMgrDispatcherInit (void);
-
-/*
- * Get the dispatcher statistics
- */
-IxQMgrDispatcherStats*
-ixQMgrDispatcherStatsGet (void);
-
-/**
- * Retrieve the number of leading zero bits starting from the MSB 
- * This function is implemented as an (extremely fast) asm routine 
- * for XSCALE processor (see clz instruction) and as a (slower) C 
- * function for other systems.
- */
-unsigned int
-ixQMgrCountLeadingZeros(unsigned int value);
-
-#endif/*IXQMGRDISPATCHER_P_H*/
-
-
diff --git a/drivers/net/npe/include/IxQMgrLog_p.h b/drivers/net/npe/include/IxQMgrLog_p.h
deleted file mode 100644
index 941236a38e..0000000000
--- a/drivers/net/npe/include/IxQMgrLog_p.h
+++ /dev/null
@@ -1,100 +0,0 @@
-/**
- * @file    IxQMgrLog_p.h
- *
- * @author Intel Corporation
- * @date    07-Feb-2002
- *
- * @brief   This file contains the internal functions for config
- *
- * 
- * @par
- * IXP400 SW Release version 2.0
- * 
- * -- Copyright Notice --
- * 
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- * 
- * @par
- * SPDX-License-Identifier:	BSD-3-Clause
- * @par
- * -- End of Copyright Notice --
-*/
-
-#ifndef IXQMGRLOG_P_H
-#define IXQMGRLOG_P_H
-
-/*
- * User defined header files
- */
-#include "IxOsal.h"
-
-/*
- * Macros
- */
-
-#define IX_QMGR_LOG0(string) do\
-{\
-    ixOsalLog(IX_OSAL_LOG_LVL_USER, IX_OSAL_LOG_DEV_STDOUT, string, 0, 0, 0, 0, 0, 0);\
-}while(0);
-
-#define IX_QMGR_LOG1(string, arg1) do\
-{\
-    ixOsalLog(IX_OSAL_LOG_LVL_USER, IX_OSAL_LOG_DEV_STDOUT, string, (int)arg1, 0, 0, 0, 0, 0);\
-}while(0);
-
-#define IX_QMGR_LOG2(string, arg1, arg2) do\
-{\
-    ixOsalLog(IX_OSAL_LOG_LVL_USER, IX_OSAL_LOG_DEV_STDOUT, string, (int)arg1, (int)arg2, 0, 0, 0, 0);\
-}while(0);
-
-#define IX_QMGR_LOG3(string, arg1, arg2, arg3) do\
-{\
-    ixOsalLog(IX_OSAL_LOG_LVL_USER, IX_OSAL_LOG_DEV_STDOUT, string, (int)arg1, (int)arg2, (int)arg3, 0, 0, 0);\
-}while(0);
-
-#define IX_QMGR_LOG6(string, arg1, arg2, arg3, arg4, arg5, arg6) do\
-{\
-    ixOsalLog(IX_OSAL_LOG_LVL_USER, IX_OSAL_LOG_DEV_STDOUT, string, (int)arg1, (int)arg2, (int)arg3, (int)arg4, (int)arg5, (int)arg6); \
-}while(0);
-
-#define IX_QMGR_LOG_WARNING0(string) do\
-{\
-    ixOsalLog(IX_OSAL_LOG_LVL_WARNING, IX_OSAL_LOG_DEV_STDOUT, string, 0, 0, 0, 0, 0, 0);\
-}while(0);
-
-#define IX_QMGR_LOG_WARNING1(string, arg1) do\
-{\
-    ixOsalLog(IX_OSAL_LOG_LVL_WARNING, IX_OSAL_LOG_DEV_STDOUT, string, (int)arg1, 0, 0, 0, 0, 0);\
-}while(0);
-
-#define IX_QMGR_LOG_WARNING2(string, arg1, arg2) do\
-{\
-    ixOsalLog(IX_OSAL_LOG_LVL_WARNING, IX_OSAL_LOG_DEV_STDOUT, string, (int)arg1, (int)arg2, 0, 0, 0, 0);\
-}while(0);
-
-#define IX_QMGR_LOG_ERROR0(string) do\
-{\
-    ixOsalLog(IX_OSAL_LOG_LVL_ERROR, IX_OSAL_LOG_DEV_STDERR, string, 0, 0, 0, 0, 0, 0);\
-}while(0);
-
-#define IX_QMGR_LOG_ERROR1(string, arg1) do\
-{\
-    ixOsalLog(IX_OSAL_LOG_LVL_ERROR, IX_OSAL_LOG_DEV_STDERR, string, (int)arg1, 0, 0, 0, 0, 0);\
-}while(0);
-
-#define IX_QMGR_LOG_ERROR2(string, arg1, arg2) do\
-{\
-    ixOsalLog(IX_OSAL_LOG_LVL_ERROR, IX_OSAL_LOG_DEV_STDERR, string, (int)arg1, (int)arg2, 0, 0, 0, 0);\
-}while(0);
-
-#define IX_QMGR_LOG_ERROR3(string, arg1, arg2, arg3) do\
-{\
-    ixOsalLog(IX_OSAL_LOG_LVL_ERROR, IX_OSAL_LOG_DEV_STDERR, string, (int)arg1, (int)arg2, (int)arg3, 0, 0, 0);\
-}while(0);
-#endif /* IX_QMGRLOG_P_H */
-
-
-
-
diff --git a/drivers/net/npe/include/IxQMgrQAccess_p.h b/drivers/net/npe/include/IxQMgrQAccess_p.h
deleted file mode 100644
index 363622fba6..0000000000
--- a/drivers/net/npe/include/IxQMgrQAccess_p.h
+++ /dev/null
@@ -1,72 +0,0 @@
-/**
- * @file    IxQMgrQAccess_p.h
- *
- * @author Intel Corporation
- * @date    30-Oct-2001
- *
- * @brief   QAccess private header file
- *
- * 
- * @par
- * IXP400 SW Release version 2.0
- * 
- * -- Copyright Notice --
- * 
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- * 
- * @par
- * SPDX-License-Identifier:	BSD-3-Clause
- * @par
- * -- End of Copyright Notice --
-*/
-
-#ifndef IXQMGRQACCESS_P_H
-#define IXQMGRQACCESS_P_H
-
-/*
- * User defined header files
- */
-#include "IxQMgr.h"
-
-/* 
- * Global variables declarations.
- */
-extern volatile UINT32 * ixQMgrAqmIfQueAccRegAddr[]; 
-
-/* 
- * Initialise the Queue Access component
- */
-void
-ixQMgrQAccessInit (void);
-
-/*
- * read the remainder of a multi-word queue entry 
- * (the first word is already read)
- */
-IX_STATUS
-ixQMgrQReadMWordsMinus1 (IxQMgrQId qId,
-                         UINT32 *entry);
-
-/*
- * Fast access : pop a q entry from a single word queue
- */
-extern __inline__ UINT32 ixQMgrQAccessPop(IxQMgrQId qId);
-
-extern __inline__ UINT32 ixQMgrQAccessPop(IxQMgrQId qId)
-{
-  return *(ixQMgrAqmIfQueAccRegAddr[qId]);
-}
-
-/*
- * Fast access : push a q entry in a single word queue
- */
-extern __inline__ void ixQMgrQAccessPush(IxQMgrQId qId, UINT32 entry);
-
-extern __inline__ void ixQMgrQAccessPush(IxQMgrQId qId, UINT32 entry)
-{
-  *(ixQMgrAqmIfQueAccRegAddr[qId]) = entry;
-}
-
-#endif/*IXQMGRQACCESS_P_H*/
diff --git a/drivers/net/npe/include/IxQMgrQCfg_p.h b/drivers/net/npe/include/IxQMgrQCfg_p.h
deleted file mode 100644
index 5480214e9f..0000000000
--- a/drivers/net/npe/include/IxQMgrQCfg_p.h
+++ /dev/null
@@ -1,98 +0,0 @@
-/**
- * @file    IxQMgrQCfg_p.h
- *
- * @author Intel Corporation
- * @date    07-Feb-2002
- *
- * @brief   This file contains the internal functions for config
- *
- * 
- * @par
- * IXP400 SW Release version 2.0
- * 
- * -- Copyright Notice --
- * 
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- * 
- * @par
- * SPDX-License-Identifier:	BSD-3-Clause
- * @par
- * -- End of Copyright Notice --
-*/
-
-#ifndef IXQMGRQCFG_P_H
-#define IXQMGRQCFG_P_H
-
-/*
- * User defined header files
- */
-#include "IxQMgr.h"
-
-/*
- * Typedefs
- */
-typedef struct
-{
-    unsigned wmSetCnt;    
-
-    struct
-    {
-	char *qName;
-	BOOL isConfigured;	
-	unsigned int qSizeInWords;
-	unsigned int qEntrySizeInWords;
-	unsigned int ne;
-	unsigned int nf;
-	unsigned int numEntries;
-	UINT32 baseAddress;
-	UINT32 readPtr;
-	UINT32 writePtr;
-    } qStats[IX_QMGR_MAX_NUM_QUEUES];
-
-} IxQMgrQCfgStats;
-
-/*
- * Initialize the QCfg subcomponent
- */ 
-void
-ixQMgrQCfgInit (void);
-
-/*
- * Uninitialize the QCfg subcomponent
- */ 
-void
-ixQMgrQCfgUninit (void);
-
-/*
- * Get the Q size in words
- */ 
-IxQMgrQSizeInWords
-ixQMgrQSizeInWordsGet (IxQMgrQId qId);
-
-/*
- * Get the Q entry size in words
- */ 
-IxQMgrQEntrySizeInWords
-ixQMgrQEntrySizeInWordsGet (IxQMgrQId qId);
-
-/*
- * Get the generic cfg stats
- */
-IxQMgrQCfgStats*
-ixQMgrQCfgStatsGet (void);
-
-/*
- * Get queue specific stats
- */
-IxQMgrQCfgStats*
-ixQMgrQCfgQStatsGet (IxQMgrQId qId);
-
-/*
- * Check is the queue configured
- */
-BOOL
-ixQMgrQIsConfigured(IxQMgrQId qId);
- 
-#endif /* IX_QMGRQCFG_P_H */
diff --git a/drivers/net/npe/include/IxQueueAssignments.h b/drivers/net/npe/include/IxQueueAssignments.h
deleted file mode 100644
index 28b924723f..0000000000
--- a/drivers/net/npe/include/IxQueueAssignments.h
+++ /dev/null
@@ -1,492 +0,0 @@
-/**
- * @file IxQueueAssignments.h
- *
- * @author Intel Corporation
- * @date 29-Oct-2004
- *
- * @brief Central definition for queue assignments
- *
- * Design Notes:
- * This file contains queue assignments used by Ethernet (EthAcc),
- * HSS (HssAcc), ATM (atmdAcc) and DMA (dmaAcc) access libraries.
- *
- * Note: Ethernet QoS traffic class definitions are managed separately
- * by EthDB in IxEthDBQoS.h.
- * 
- * @par
- * IXP400 SW Release version 2.0
- * 
- * -- Copyright Notice --
- * 
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- * 
- * @par
- * SPDX-License-Identifier:	BSD-3-Clause
- * @par
- * -- End of Copyright Notice --
- */
-
-#ifndef IxQueueAssignments_H
-#define IxQueueAssignments_H
-
-#include "IxQMgr.h"
-
-/***************************************************************************
- *  Queue assignments for ATM
- ***************************************************************************/
-
-/** 
- * @brief Global compiler switch to select between 3 possible NPE Modes
- * Define this macro to enable MPHY mode
- *
- * Default(No Switch) = MultiPHY Utopia2
- * IX_UTOPIAMODE = 1 for single Phy Utopia1
- * IX_MPHYSINGLEPORT = 1 for single Phy Utopia2 
- */
-#define IX_NPE_MPHYMULTIPORT 1
-#if IX_UTOPIAMODE == 1
-#undef  IX_NPE_MPHYMULTIPORT
-#endif
-#if IX_MPHYSINGLEPORT == 1
-#undef  IX_NPE_MPHYMULTIPORT
-#endif
-
-/**
- * @def IX_NPE_A_TXDONE_QUEUE_HIGHWATERMARK
- *
- * @brief The NPE reserves the High Watermark for its operation. But it must be set by the Xscale
- */
-#define IX_NPE_A_TXDONE_QUEUE_HIGHWATERMARK  2
-
-/**
- * @def IX_NPE_A_QMQ_ATM_TX_DONE
- *
- * @brief Queue ID for ATM Transmit Done queue
- */
-#define IX_NPE_A_QMQ_ATM_TX_DONE       IX_QMGR_QUEUE_1
-
-/**
- * @def IX_NPE_A_QMQ_ATM_TX0
- *
- * @brief Queue ID for ATM transmit Queue in a single phy configuration
- */
-#define IX_NPE_A_QMQ_ATM_TX0           IX_QMGR_QUEUE_2
-
-
-/**
- * @def IX_NPE_A_QMQ_ATM_TXID_MIN
- *
- * @brief Queue Manager Queue ID for ATM transmit Queue with minimum number of queue
- *
- */
-
-/**
- * @def IX_NPE_A_QMQ_ATM_TXID_MAX
- *
- * @brief Queue Manager Queue ID for ATM transmit Queue with maximum number of queue
- *
- */
-
-/**
- * @def IX_NPE_A_QMQ_ATM_RX_HI
- *
- * @brief Queue Manager Queue ID for ATM Receive high Queue
- *
- */
-
-/**
- * @def IX_NPE_A_QMQ_ATM_RX_LO
- *
- * @brief Queue Manager Queue ID for ATM Receive low Queue
- */
-
-#ifdef IX_NPE_MPHYMULTIPORT
-/**
- * @def IX_NPE_A_QMQ_ATM_TX1
- *
- * @brief Queue ID for ATM transmit Queue Multiphy from 1 to 11
- */
-#define IX_NPE_A_QMQ_ATM_TX1           IX_NPE_A_QMQ_ATM_TX0+1
-#define IX_NPE_A_QMQ_ATM_TX2           IX_NPE_A_QMQ_ATM_TX1+1
-#define IX_NPE_A_QMQ_ATM_TX3           IX_NPE_A_QMQ_ATM_TX2+1
-#define IX_NPE_A_QMQ_ATM_TX4           IX_NPE_A_QMQ_ATM_TX3+1
-#define IX_NPE_A_QMQ_ATM_TX5           IX_NPE_A_QMQ_ATM_TX4+1
-#define IX_NPE_A_QMQ_ATM_TX6           IX_NPE_A_QMQ_ATM_TX5+1
-#define IX_NPE_A_QMQ_ATM_TX7           IX_NPE_A_QMQ_ATM_TX6+1
-#define IX_NPE_A_QMQ_ATM_TX8           IX_NPE_A_QMQ_ATM_TX7+1
-#define IX_NPE_A_QMQ_ATM_TX9           IX_NPE_A_QMQ_ATM_TX8+1
-#define IX_NPE_A_QMQ_ATM_TX10          IX_NPE_A_QMQ_ATM_TX9+1
-#define IX_NPE_A_QMQ_ATM_TX11          IX_NPE_A_QMQ_ATM_TX10+1
-#define IX_NPE_A_QMQ_ATM_TXID_MIN      IX_NPE_A_QMQ_ATM_TX0
-#define IX_NPE_A_QMQ_ATM_TXID_MAX      IX_NPE_A_QMQ_ATM_TX11
-#define IX_NPE_A_QMQ_ATM_RX_HI         IX_QMGR_QUEUE_21
-#define IX_NPE_A_QMQ_ATM_RX_LO         IX_QMGR_QUEUE_22
-#else
-#define IX_NPE_A_QMQ_ATM_TXID_MIN      IX_NPE_A_QMQ_ATM_TX0
-#define IX_NPE_A_QMQ_ATM_TXID_MAX      IX_NPE_A_QMQ_ATM_TX0
-#define IX_NPE_A_QMQ_ATM_RX_HI         IX_QMGR_QUEUE_10
-#define IX_NPE_A_QMQ_ATM_RX_LO         IX_QMGR_QUEUE_11
-#endif /* MPHY */
-
-/**
- * @def IX_NPE_A_QMQ_ATM_FREE_VC0
- *
- * @brief Hardware QMgr Queue ID for ATM Free VC Queue.
- *
- * There are 32 Hardware QMgr Queue ID; from IX_NPE_A_QMQ_ATM_FREE_VC1 to
- * IX_NPE_A_QMQ_ATM_FREE_VC30
- */
-#define IX_NPE_A_QMQ_ATM_FREE_VC0      IX_QMGR_QUEUE_32
-#define IX_NPE_A_QMQ_ATM_FREE_VC1      IX_NPE_A_QMQ_ATM_FREE_VC0+1
-#define IX_NPE_A_QMQ_ATM_FREE_VC2      IX_NPE_A_QMQ_ATM_FREE_VC1+1
-#define IX_NPE_A_QMQ_ATM_FREE_VC3      IX_NPE_A_QMQ_ATM_FREE_VC2+1
-#define IX_NPE_A_QMQ_ATM_FREE_VC4      IX_NPE_A_QMQ_ATM_FREE_VC3+1
-#define IX_NPE_A_QMQ_ATM_FREE_VC5      IX_NPE_A_QMQ_ATM_FREE_VC4+1
-#define IX_NPE_A_QMQ_ATM_FREE_VC6      IX_NPE_A_QMQ_ATM_FREE_VC5+1
-#define IX_NPE_A_QMQ_ATM_FREE_VC7      IX_NPE_A_QMQ_ATM_FREE_VC6+1
-#define IX_NPE_A_QMQ_ATM_FREE_VC8      IX_NPE_A_QMQ_ATM_FREE_VC7+1
-#define IX_NPE_A_QMQ_ATM_FREE_VC9      IX_NPE_A_QMQ_ATM_FREE_VC8+1
-#define IX_NPE_A_QMQ_ATM_FREE_VC10     IX_NPE_A_QMQ_ATM_FREE_VC9+1
-#define IX_NPE_A_QMQ_ATM_FREE_VC11     IX_NPE_A_QMQ_ATM_FREE_VC10+1
-#define IX_NPE_A_QMQ_ATM_FREE_VC12     IX_NPE_A_QMQ_ATM_FREE_VC11+1
-#define IX_NPE_A_QMQ_ATM_FREE_VC13     IX_NPE_A_QMQ_ATM_FREE_VC12+1
-#define IX_NPE_A_QMQ_ATM_FREE_VC14     IX_NPE_A_QMQ_ATM_FREE_VC13+1
-#define IX_NPE_A_QMQ_ATM_FREE_VC15     IX_NPE_A_QMQ_ATM_FREE_VC14+1
-#define IX_NPE_A_QMQ_ATM_FREE_VC16     IX_NPE_A_QMQ_ATM_FREE_VC15+1
-#define IX_NPE_A_QMQ_ATM_FREE_VC17     IX_NPE_A_QMQ_ATM_FREE_VC16+1
-#define IX_NPE_A_QMQ_ATM_FREE_VC18     IX_NPE_A_QMQ_ATM_FREE_VC17+1
-#define IX_NPE_A_QMQ_ATM_FREE_VC19     IX_NPE_A_QMQ_ATM_FREE_VC18+1
-#define IX_NPE_A_QMQ_ATM_FREE_VC20     IX_NPE_A_QMQ_ATM_FREE_VC19+1
-#define IX_NPE_A_QMQ_ATM_FREE_VC21     IX_NPE_A_QMQ_ATM_FREE_VC20+1
-#define IX_NPE_A_QMQ_ATM_FREE_VC22     IX_NPE_A_QMQ_ATM_FREE_VC21+1
-#define IX_NPE_A_QMQ_ATM_FREE_VC23     IX_NPE_A_QMQ_ATM_FREE_VC22+1
-#define IX_NPE_A_QMQ_ATM_FREE_VC24     IX_NPE_A_QMQ_ATM_FREE_VC23+1
-#define IX_NPE_A_QMQ_ATM_FREE_VC25     IX_NPE_A_QMQ_ATM_FREE_VC24+1
-#define IX_NPE_A_QMQ_ATM_FREE_VC26     IX_NPE_A_QMQ_ATM_FREE_VC25+1
-#define IX_NPE_A_QMQ_ATM_FREE_VC27     IX_NPE_A_QMQ_ATM_FREE_VC26+1
-#define IX_NPE_A_QMQ_ATM_FREE_VC28     IX_NPE_A_QMQ_ATM_FREE_VC27+1
-#define IX_NPE_A_QMQ_ATM_FREE_VC29     IX_NPE_A_QMQ_ATM_FREE_VC28+1
-#define IX_NPE_A_QMQ_ATM_FREE_VC30     IX_NPE_A_QMQ_ATM_FREE_VC29+1
-#define IX_NPE_A_QMQ_ATM_FREE_VC31     IX_NPE_A_QMQ_ATM_FREE_VC30+1
-
-/**
- * @def IX_NPE_A_QMQ_ATM_RXFREE_MIN
- *
- * @brief The minimum queue ID for FreeVC queue
- */
-#define IX_NPE_A_QMQ_ATM_RXFREE_MIN  IX_NPE_A_QMQ_ATM_FREE_VC0
-
-/**
- * @def IX_NPE_A_QMQ_ATM_RXFREE_MAX
- *
- * @brief The maximum queue ID for FreeVC queue
- */
-#define IX_NPE_A_QMQ_ATM_RXFREE_MAX  IX_NPE_A_QMQ_ATM_FREE_VC31
-
-/**
- * @def IX_NPE_A_QMQ_OAM_FREE_VC
- * @brief OAM Rx Free queue ID
- */
-#ifdef IX_NPE_MPHYMULTIPORT
-#define IX_NPE_A_QMQ_OAM_FREE_VC       IX_QMGR_QUEUE_14
-#else
-#define IX_NPE_A_QMQ_OAM_FREE_VC       IX_QMGR_QUEUE_3
-#endif /* MPHY */
-
-/****************************************************************************
- * Queue assignments for HSS
- ****************************************************************************/
-
-/****  HSS Port 0 ****/
-
-/**
- * @def IX_NPE_A_QMQ_HSS0_CHL_RX_TRIG
- *
- * @brief Hardware QMgr Queue ID for HSS Port 0 Channelized Receive trigger
- */
-#define IX_NPE_A_QMQ_HSS0_CHL_RX_TRIG   IX_QMGR_QUEUE_12
-
-/**
- * @def IX_NPE_A_QMQ_HSS0_PKT_RX
- *
- * @brief Hardware QMgr Queue ID for HSS Port 0 Packetized Receive
- */
-#define IX_NPE_A_QMQ_HSS0_PKT_RX        IX_QMGR_QUEUE_13
-
-/**
- * @def IX_NPE_A_QMQ_HSS0_PKT_TX0
- *
- * @brief Hardware QMgr Queue ID for HSS Port 0 Packetized Transmit queue 0
- */
-#define IX_NPE_A_QMQ_HSS0_PKT_TX0       IX_QMGR_QUEUE_14
-
-/**
- * @def IX_NPE_A_QMQ_HSS0_PKT_TX1
- *
- * @brief Hardware QMgr Queue ID for HSS Port 0 Packetized Transmit queue 1
- */
-#define IX_NPE_A_QMQ_HSS0_PKT_TX1       IX_QMGR_QUEUE_15
-
-/**
- * @def IX_NPE_A_QMQ_HSS0_PKT_TX2
- *
- * @brief Hardware QMgr Queue ID for HSS Port 0 Packetized Transmit queue 2
- */
-#define IX_NPE_A_QMQ_HSS0_PKT_TX2       IX_QMGR_QUEUE_16
-
-/**
- * @def IX_NPE_A_QMQ_HSS0_PKT_TX3
- *
- * @brief Hardware QMgr Queue ID for HSS Port 0 Packetized Transmit queue 3
- */
-#define IX_NPE_A_QMQ_HSS0_PKT_TX3       IX_QMGR_QUEUE_17
-
-/**
- * @def IX_NPE_A_QMQ_HSS0_PKT_RX_FREE0
- *
- * @brief Hardware QMgr Queue ID for HSS Port 0 Packetized Receive Free queue 0
- */
-#define IX_NPE_A_QMQ_HSS0_PKT_RX_FREE0  IX_QMGR_QUEUE_18
-
-/**
- * @def IX_NPE_A_QMQ_HSS0_PKT_RX_FREE1
- *
- * @brief Hardware QMgr Queue ID for HSS Port 0 Packetized Receive Free queue 1
- */
-#define IX_NPE_A_QMQ_HSS0_PKT_RX_FREE1  IX_QMGR_QUEUE_19
-
-/**
- * @def IX_NPE_A_QMQ_HSS0_PKT_RX_FREE2
- *
- * @brief Hardware QMgr Queue ID for HSS Port 0 Packetized Receive Free queue 2
- */
-#define IX_NPE_A_QMQ_HSS0_PKT_RX_FREE2  IX_QMGR_QUEUE_20
-
-/**
- * @def IX_NPE_A_QMQ_HSS0_PKT_RX_FREE3
- *
- * @brief Hardware QMgr Queue ID for HSS Port 0 Packetized Receive Free queue 3
- */
-#define IX_NPE_A_QMQ_HSS0_PKT_RX_FREE3  IX_QMGR_QUEUE_21
-
-/**
- * @def IX_NPE_A_QMQ_HSS0_PKT_TX_DONE
- *
- * @brief Hardware QMgr Queue ID for HSS Port 0 Packetized Transmit Done queue
- */
-#define IX_NPE_A_QMQ_HSS0_PKT_TX_DONE   IX_QMGR_QUEUE_22
-
-/****  HSS Port 1 ****/
-
-/**
- * @def IX_NPE_A_QMQ_HSS1_CHL_RX_TRIG
- *
- * @brief Hardware QMgr Queue ID for HSS Port 1 Channelized Receive trigger
- */
-#define IX_NPE_A_QMQ_HSS1_CHL_RX_TRIG   IX_QMGR_QUEUE_10
-
-/**
- * @def IX_NPE_A_QMQ_HSS1_PKT_RX
- *
- * @brief Hardware QMgr Queue ID for HSS Port 1 Packetized Receive
- */
-#define IX_NPE_A_QMQ_HSS1_PKT_RX        IX_QMGR_QUEUE_0
-
-/**
- * @def IX_NPE_A_QMQ_HSS1_PKT_TX0
- *
- * @brief Hardware QMgr Queue ID for HSS Port 1 Packetized Transmit queue 0
- */
-#define IX_NPE_A_QMQ_HSS1_PKT_TX0       IX_QMGR_QUEUE_5
-
-/**
- * @def IX_NPE_A_QMQ_HSS1_PKT_TX1
- *
- * @brief Hardware QMgr Queue ID for HSS Port 1 Packetized Transmit queue 1
- */
-#define IX_NPE_A_QMQ_HSS1_PKT_TX1       IX_QMGR_QUEUE_6
-
-/**
- * @def IX_NPE_A_QMQ_HSS1_PKT_TX2
- *
- * @brief Hardware QMgr Queue ID for HSS Port 1 Packetized Transmit queue 2
- */
-#define IX_NPE_A_QMQ_HSS1_PKT_TX2       IX_QMGR_QUEUE_7
-
-/**
- * @def IX_NPE_A_QMQ_HSS1_PKT_TX3
- *
- * @brief Hardware QMgr Queue ID for HSS Port 1 Packetized Transmit queue 3
- */
-#define IX_NPE_A_QMQ_HSS1_PKT_TX3       IX_QMGR_QUEUE_8
-
-/**
- * @def IX_NPE_A_QMQ_HSS1_PKT_RX_FREE0
- *
- * @brief Hardware QMgr Queue ID for HSS Port 1 Packetized Receive Free queue 0
- */
-#define IX_NPE_A_QMQ_HSS1_PKT_RX_FREE0  IX_QMGR_QUEUE_1
-
-/**
- * @def IX_NPE_A_QMQ_HSS1_PKT_RX_FREE1
- *
- * @brief Hardware QMgr Queue ID for HSS Port 1 Packetized Receive Free queue 1
- */
-#define IX_NPE_A_QMQ_HSS1_PKT_RX_FREE1  IX_QMGR_QUEUE_2
-
-/**
- * @def IX_NPE_A_QMQ_HSS1_PKT_RX_FREE2
- *
- * @brief Hardware QMgr Queue ID for HSS Port 1 Packetized Receive Free queue 2
- */
-#define IX_NPE_A_QMQ_HSS1_PKT_RX_FREE2  IX_QMGR_QUEUE_3
-
-/**
- * @def IX_NPE_A_QMQ_HSS1_PKT_RX_FREE3
- *
- * @brief Hardware QMgr Queue ID for HSS Port 1 Packetized Receive Free queue 3
- */
-#define IX_NPE_A_QMQ_HSS1_PKT_RX_FREE3  IX_QMGR_QUEUE_4
-
-/**
- * @def IX_NPE_A_QMQ_HSS1_PKT_TX_DONE
- *
- * @brief Hardware QMgr Queue ID for HSS Port 1 Packetized Transmit Done queue
- */
-#define IX_NPE_A_QMQ_HSS1_PKT_TX_DONE   IX_QMGR_QUEUE_9
-
-/*****************************************************************************************
- * Queue assignments for DMA
- *****************************************************************************************/
-
-#define IX_DMA_NPE_A_REQUEST_QID IX_QMGR_QUEUE_19   /**< Queue Id for NPE A DMA Request */
-#define IX_DMA_NPE_A_DONE_QID    IX_QMGR_QUEUE_20   /**< Queue Id for NPE A DMA Done    */
-#define IX_DMA_NPE_B_REQUEST_QID IX_QMGR_QUEUE_24   /**< Queue Id for NPE B DMA Request */
-#define IX_DMA_NPE_B_DONE_QID    IX_QMGR_QUEUE_26   /**< Queue Id for NPE B DMA Done    */
-#define IX_DMA_NPE_C_REQUEST_QID IX_QMGR_QUEUE_25   /**< Queue Id for NPE C DMA Request */
-#define IX_DMA_NPE_C_DONE_QID    IX_QMGR_QUEUE_27   /**< Queue Id for NPE C DMA Done    */
-
-
-/*****************************************************************************************
- * Queue assignments for Ethernet
- *
- * Note: Rx queue definitions, which include QoS traffic class definitions
- * are managed by EthDB and declared in IxEthDBQoS.h
- *****************************************************************************************/
-
-/**
-*
-* @def IX_ETH_ACC_RX_FRAME_ETH_Q 
-*
-* @brief  Eth0/Eth1 NPE Frame Receive Q.
-*
-* @note THIS IS NOT USED - the Rx queues are read from EthDB QoS configuration
-* 
-*/
-#define IX_ETH_ACC_RX_FRAME_ETH_Q	(IX_QMGR_QUEUE_4)
-
-/**
-*
-* @def IX_ETH_ACC_RX_FREE_BUFF_ENET0_Q
-*
-* @brief Supply Rx Buffers Ethernet Q for NPEB - Eth 0 - Port 1
-*
-*/
-#define IX_ETH_ACC_RX_FREE_BUFF_ENET0_Q    (IX_QMGR_QUEUE_27)
-
-/**
-*
-* @def IX_ETH_ACC_RX_FREE_BUFF_ENET1_Q
-*
-* @brief Supply Rx Buffers Ethernet Q for NPEC - Eth 1 - Port 2
-*
-*/
-#define IX_ETH_ACC_RX_FREE_BUFF_ENET1_Q    (IX_QMGR_QUEUE_28)
-
-/**
-*
-* @def IX_ETH_ACC_RX_FREE_BUFF_ENET2_Q
-*
-* @brief Supply Rx Buffers Ethernet Q for NPEA - Eth 2 - Port 3
-*
-*/
-#define IX_ETH_ACC_RX_FREE_BUFF_ENET2_Q    (IX_QMGR_QUEUE_26)
-
-
-/**
-*
-* @def IX_ETH_ACC_TX_FRAME_ENET0_Q
-*
-* @brief Submit frame Q for NPEB Eth 0 - Port 1
-*
-*/
-#define IX_ETH_ACC_TX_FRAME_ENET0_Q    (IX_QMGR_QUEUE_24)
-
-
-/**
-*
-* @def IX_ETH_ACC_TX_FRAME_ENET1_Q
-*
-* @brief Submit frame Q for NPEC Eth 1 - Port 2
-*
-*/
-#define IX_ETH_ACC_TX_FRAME_ENET1_Q    (IX_QMGR_QUEUE_25)
-
-/**
-*
-* @def IX_ETH_ACC_TX_FRAME_ENET2_Q
-*
-* @brief Submit frame Q for NPEA Eth 2 - Port 3
-*
-*/
-#define IX_ETH_ACC_TX_FRAME_ENET2_Q    (IX_QMGR_QUEUE_23)
-
-/**
-*
-* @def IX_ETH_ACC_TX_FRAME_DONE_ETH_Q
-*
-* @brief Transmit complete Q for NPE Eth 0/1, Port 1&2
-*
-*/
-#define IX_ETH_ACC_TX_FRAME_DONE_ETH_Q    (IX_QMGR_QUEUE_31)
-
-/*****************************************************************************************
- * Queue assignments for Crypto
- *****************************************************************************************/
-
-/** Crypto Service Request Queue */
-#define IX_CRYPTO_ACC_CRYPTO_REQ_Q  (IX_QMGR_QUEUE_29)
-
-/** Crypto Service Done Queue */
-#define IX_CRYPTO_ACC_CRYPTO_DONE_Q (IX_QMGR_QUEUE_30)
-
-/** Crypto Req Q CB tag */
-#define IX_CRYPTO_ACC_CRYPTO_REQ_Q_CB_TAG   (0)
-
-/** Crypto Done Q CB tag */
-#define IX_CRYPTO_ACC_CRYPTO_DONE_Q_CB_TAG  (1)
-
-/** WEP Service Request Queue */
-#define IX_CRYPTO_ACC_WEP_REQ_Q  (IX_QMGR_QUEUE_21)
-
-/** WEP Service Done Queue */
-#define IX_CRYPTO_ACC_WEP_DONE_Q (IX_QMGR_QUEUE_22)
-
-/** WEP Req Q CB tag */
-#define IX_CRYPTO_ACC_WEP_REQ_Q_CB_TAG      (2)
-
-/** WEP Done Q CB tag */
-#define IX_CRYPTO_ACC_WEP_DONE_Q_CB_TAG     (3)
-
-/** Number of queues allocate to crypto hardware accelerator services */
-#define IX_CRYPTO_ACC_NUM_OF_CRYPTO_Q       (2)
-
-/** Number of queues allocate to WEP NPE services */
-#define IX_CRYPTO_ACC_NUM_OF_WEP_NPE_Q      (2)
-                                                      
-/** Number of queues allocate to CryptoAcc component */
-#define IX_CRYPTO_ACC_NUM_OF_Q (IX_CRYPTO_ACC_NUM_OF_CRYPTO_Q + IX_CRYPTO_ACC_NUM_OF_WEP_NPE_Q)   
-
-#endif /* IxQueueAssignments_H */
diff --git a/drivers/net/npe/include/IxSspAcc.h b/drivers/net/npe/include/IxSspAcc.h
deleted file mode 100644
index b4a9def274..0000000000
--- a/drivers/net/npe/include/IxSspAcc.h
+++ /dev/null
@@ -1,1247 +0,0 @@
-/**
- * @file IxSspAcc.h
- *
- * @brief  Header file for the IXP400 SSP Serial Port Access (IxSspAcc)
- *
- * @version $Revision: 0.1 $
- * 
- * @par
- * IXP400 SW Release version 2.0
- * 
- * -- Copyright Notice --
- * 
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- * 
- * @par
- * SPDX-License-Identifier:	BSD-3-Clause
- * @par
- * -- End of Copyright Notice --
- */
-
-/**
- * @defgroup IxSspAcc IXP400 SSP Serial Port Access (IxSspAcc) API 
- *
- * @brief IXP400 SSP Serial Port Access Public API
- *
- * @{
- */
-#ifndef IXSSPACC_H
-#define IXSSPACC_H
-
-#ifdef __ixp46X
-
-#include "IxOsal.h"
-
-/*
- * Section for enum
- */
-/**
- * @ingroup IxSspAcc
- * 
- * @enum IxSspAccDataSize
- *
- * @brief The data sizes in bits that are supported by the protocol
- */
-typedef enum
-{
-	DATA_SIZE_TOO_SMALL = 0x2,
-	DATA_SIZE_4 = 0x3,
-	DATA_SIZE_5,
-	DATA_SIZE_6,
-	DATA_SIZE_7,
-	DATA_SIZE_8,
-	DATA_SIZE_9,
-	DATA_SIZE_10,
-	DATA_SIZE_11,
-	DATA_SIZE_12,
-	DATA_SIZE_13,
-	DATA_SIZE_14,
-	DATA_SIZE_15,
-	DATA_SIZE_16,
-	DATA_SIZE_TOO_BIG
-} IxSspAccDataSize;
-
-/**
- * @ingroup IxSspAcc
- * 
- * @enum IxSspAccPortStatus
- *
- * @brief The status of the SSP port to be set to enable/disable
- */
-typedef enum
-{
-	SSP_PORT_DISABLE = 0x0,
-	SSP_PORT_ENABLE,
-	INVALID_SSP_PORT_STATUS
-} IxSspAccPortStatus;
-
-/**
- * @ingroup IxSspAcc
- * 
- * @enum IxSspAccFrameFormat
- *
- * @brief The frame format that is to be used - SPI, SSP, or Microwire
- */
-typedef enum
-{
-	SPI_FORMAT = 0x0,
-	SSP_FORMAT,
-	MICROWIRE_FORMAT,
-	INVALID_FORMAT
-} IxSspAccFrameFormat;
-
-/**
- * @ingroup IxSspAcc
- * 
- * @enum IxSspAccClkSource
- *
- * @brief The source to produce the SSP serial clock
- */
-typedef enum
-{
-	ON_CHIP_CLK = 0x0,
-	EXTERNAL_CLK,
-	INVALID_CLK_SOURCE
-} IxSspAccClkSource;
-
-/**
- * @ingroup IxSspAcc
- * 
- * @enum IxSspAccSpiSclkPhase
- *
- * @brief The SPI SCLK Phase: 
- * 0 - SCLK is inactive one cycle at the start of a frame and 1/2 cycle at the
- *		end of a frame.
- * 1 - SCLK is inactive 1/2 cycle at the start of a frame and one cycle at the
- *		end of a frame.
- */
-typedef enum
-{
-	START_ONE_END_HALF = 0x0,
-	START_HALF_END_ONE,
-	INVALID_SPI_PHASE
-} IxSspAccSpiSclkPhase;
-
-/**
- * @ingroup IxSspAcc
- * 
- * @enum IxSspAccSpiSclkPolarity
- *
- * @brief The SPI SCLK Polarity can be set to either low or high.
- */
-typedef enum
-{
-	SPI_POLARITY_LOW = 0x0,
-	SPI_POLARITY_HIGH,
-	INVALID_SPI_POLARITY
-} IxSspAccSpiSclkPolarity;
-
-/**
- * @ingroup IxSspAcc
- * 
- * @enum IxSspAccMicrowireCtlWord
- *
- * @brief The Microwire control word can be either 8 or 16 bit.
- */
-typedef enum
-{
-	MICROWIRE_8_BIT = 0x0,
-	MICROWIRE_16_BIT,
-	INVALID_MICROWIRE_CTL_WORD
-} IxSspAccMicrowireCtlWord;
-
-/**
- * @ingroup IxSspAcc
- * 
- * @enum IxSspAccFifoThreshold
- *
- * @brief The threshold in frames (each frame is defined by IxSspAccDataSize)
- *			that can be set for the FIFO to trigger a threshold exceed when
- *			checking with the ExceedThresholdCheck functions or an interrupt
- *			when it is enabled.
- */
-typedef enum
-{
-	FIFO_TSHLD_1 =	0x0,
-	FIFO_TSHLD_2,
-	FIFO_TSHLD_3,
-	FIFO_TSHLD_4,
-	FIFO_TSHLD_5,
-	FIFO_TSHLD_6,
-	FIFO_TSHLD_7,
-	FIFO_TSHLD_8,
-	FIFO_TSHLD_9,
-	FIFO_TSHLD_10,
-	FIFO_TSHLD_11,
-	FIFO_TSHLD_12,
-	FIFO_TSHLD_13,
-	FIFO_TSHLD_14,
-	FIFO_TSHLD_15,
-	FIFO_TSHLD_16,
-	INVALID_FIFO_TSHLD
-} IxSspAccFifoThreshold;
-
-/**
- * @ingroup IxSspAcc
- * 
- * @enum IX_SSP_STATUS
- *
- * @brief The statuses that can be returned in a SSP Serial Port Access
- */
-typedef enum
-{
-	IX_SSP_SUCCESS = IX_SUCCESS, /**< Success status */
-	IX_SSP_FAIL, /**< Fail status */
-	IX_SSP_RX_FIFO_OVERRUN_HANDLER_MISSING, /**<
-						Rx FIFO Overrun handler is NULL. */
-	IX_SSP_RX_FIFO_HANDLER_MISSING, /**<
-					Rx FIFO threshold hit or above handler is NULL
-					*/
-	IX_SSP_TX_FIFO_HANDLER_MISSING, /**<
-					Tx FIFO threshold hit or below handler is NULL
-					*/
-	IX_SSP_FIFO_NOT_EMPTY_FOR_SETTING_CTL_CMD, /**<
-					Tx FIFO not empty and therefore microwire
-					control command size setting is not allowed.	*/
-	IX_SSP_INVALID_FRAME_FORMAT_ENUM_VALUE, /**<
-					frame format selected is invalid. */
-	IX_SSP_INVALID_DATA_SIZE_ENUM_VALUE, /**<
-					data size selected is invalid. */
-	IX_SSP_INVALID_CLOCK_SOURCE_ENUM_VALUE, /**<
-					source clock selected is invalid. */
-	IX_SSP_INVALID_TX_FIFO_THRESHOLD_ENUM_VALUE, /**<
-					Tx FIFO threshold selected is invalid. */
-	IX_SSP_INVALID_RX_FIFO_THRESHOLD_ENUM_VALUE, /**<
-					Rx FIFO threshold selected is invalid. */
-	IX_SSP_INVALID_SPI_PHASE_ENUM_VALUE, /**<
-					SPI phase selected is invalid. */
-	IX_SSP_INVALID_SPI_POLARITY_ENUM_VALUE, /**<
-					SPI polarity selected is invalid. */
-	IX_SSP_INVALID_MICROWIRE_CTL_CMD_ENUM_VALUE, /**<
-					Microwire control command selected is invalid
-					*/
-	IX_SSP_INT_UNBIND_FAIL, /**< Interrupt unbind fail to unbind SSP
-	                interrupt */
-	IX_SSP_INT_BIND_FAIL, /**< Interrupt bind fail during init */
-	IX_SSP_RX_FIFO_NOT_EMPTY, /**<
-					Rx FIFO not empty while trying to change data
-					size. */
-	IX_SSP_TX_FIFO_NOT_EMPTY, /**<
-					Rx FIFO not empty while trying to change data
-					size or microwire control command size.	*/
-	IX_SSP_POLL_MODE_BLOCKING, /**<
-					poll mode selected blocks interrupt mode from
-					being selected.	*/
-	IX_SSP_TX_FIFO_HIT_BELOW_THRESHOLD, /**<
-					Tx FIFO level hit or below threshold. */
-	IX_SSP_TX_FIFO_EXCEED_THRESHOLD, /**<
-					Tx FIFO level exceeded threshold. */
-	IX_SSP_RX_FIFO_HIT_ABOVE_THRESHOLD, /**<
-					Rx FIFO level hit or exceeded threshold. */
-	IX_SSP_RX_FIFO_BELOW_THRESHOLD, /**<
-					Rx FIFO level below threshold. */
-	IX_SSP_BUSY, /**< SSP is busy. */
-	IX_SSP_IDLE, /**< SSP is idle. */
-	IX_SSP_OVERRUN_OCCURRED, /**<
-					SSP has experienced an overrun. */
-	IX_SSP_NO_OVERRUN, /**<
-					SSP did not experience an overrun. */
-	IX_SSP_NOT_SUPORTED, /**< hardware does not support SSP */
-	IX_SSP_NOT_INIT, /**< SSP Access not intialized */
-	IX_SSP_NULL_POINTER /**< parameter passed in is NULL */
-} IX_SSP_STATUS;
-
-/**
- * @ingroup IxSspAcc
- *
- * @brief SSP Rx FIFO Overrun handler
- *
- * This function is called for the client to handle Rx FIFO Overrun that occurs
- * in the SSP hardware
- */
-typedef void (*RxFIFOOverrunHandler)(void);
-
-/**
- * @ingroup IxSspAcc
- * 
- * @brief SSP Rx FIFO Threshold hit or above handler
- *
- * This function is called for the client to handle Rx FIFO threshold hit or
- * or above that occurs in the SSP hardware
- */
-typedef void (*RxFIFOThresholdHandler)(void);
-
-/**
- * @ingroup IxSspAcc
- * 
- * @brief SSP Tx FIFO Threshold hit or below handler
- *
- * This function is called for the client to handle Tx FIFO threshold hit or
- * or below that occurs in the SSP hardware
- */
-typedef void (*TxFIFOThresholdHandler)(void);
-
-
-/*
- * Section for struct
- */
-/**
- * @ingroup IxSspAcc
- *
- * @brief contains all the variables required to initialize the SSP serial port
- *		hardware.
- * 
- * Structure to be filled and used for calling initialization
- */
-typedef struct
-{
-	IxSspAccFrameFormat FrameFormatSelected;/**<Select between SPI, SSP and
-												Microwire. */
-	IxSspAccDataSize DataSizeSelected;		/**<Select between 4 and 16. */
-	IxSspAccClkSource ClkSourceSelected;	/**<Select clock source to be
-												on-chip or external. */
-	IxSspAccFifoThreshold TxFIFOThresholdSelected;
-											/**<Select Tx FIFO threshold
-												between 1 to 16. */
-	IxSspAccFifoThreshold RxFIFOThresholdSelected;
-											/**<Select Rx FIFO threshold
-												between 1 to 16. */
-	BOOL RxFIFOIntrEnable;					/**<Enable/disable Rx FIFO
-												threshold interrupt. Disabling
-												this interrupt will require
-												the use of the polling function
-												RxFIFOExceedThresholdCheck. */
-	BOOL TxFIFOIntrEnable;					/**<Enable/disable Tx FIFO
-												threshold interrupt. Disabling
-												this interrupt will require
-												the use of the polling function
-												TxFIFOExceedThresholdCheck. */
-	RxFIFOThresholdHandler RxFIFOThsldHdlr;	/**<Pointer to function to handle
-												a Rx FIFO interrupt. */
-	TxFIFOThresholdHandler TxFIFOThsldHdlr;	/**<Pointer to function to handle
-												a Tx FIFO interrupt. */
-	RxFIFOOverrunHandler RxFIFOOverrunHdlr;	/**<Pointer to function to handle
-												a Rx FIFO overrun interrupt. */
-	BOOL LoopbackEnable;					/**<Select operation mode to be
-												normal or loopback mode. */
-	IxSspAccSpiSclkPhase SpiSclkPhaseSelected;
-											/**<Select SPI SCLK phase to start
-												with one inactive cycle and end
-												with 1/2 inactive cycle or
-												start with 1/2 inactive cycle
-												and end with one inactive
-												cycle. (Only used in
-												SPI format). */
-	IxSspAccSpiSclkPolarity SpiSclkPolaritySelected;
-											/**<Select SPI SCLK idle state
-												to be low or high. (Only used in
-												SPI format). */
-	IxSspAccMicrowireCtlWord MicrowireCtlWordSelected;
-											/**<Select Microwire control
-												format to be 8 or 16-bit. (Only
-												used in Microwire format). */
-	UINT8 SerialClkRateSelected;			/**<Select between 0 (1.8432Mbps)
-												and 255 (7.2Kbps). The
-												formula used is	Bit rate = 
-												3.6864x10^6 / 
-												(2 x (SerialClkRateSelect + 1))
-												*/
-} IxSspInitVars;
-
-/**
- * @ingroup IxSspAcc
- *
- * @brief contains counters of the SSP statistics
- * 
- * Structure contains all values of counters and associated overflows.
- */
-typedef struct
-{
-	UINT32 ixSspRcvCounter;		/**<Total frames received. */
-	UINT32 ixSspXmitCounter;	/**<Total frames transmitted. */
-	UINT32 ixSspOverflowCounter;/**<Total occurrences of overflow. */
-} IxSspAccStatsCounters;
-
-
-/*
- * Section for prototypes interface functions
- */
-
-/**
- * @ingroup IxSspAcc
- * 
- * @fn ixSspAccInit (
-	IxSspInitVars *initVarsSelected);
- *
- * @brief Initializes the SSP Access module.
- *
- * @param "IxSspAccInitVars [in] *initVarsSelected" - struct containing required
- *			variables for initialization 
- *
- * Global Data	:
- *		- None.
- *                        
- * This API will initialize the SSP Serial Port hardware to the user specified
- * configuration. Then it will enable the SSP Serial Port.
- * *NOTE*: Once interrupt or polling mode is selected, the mode cannot be
- * changed via the interrupt enable/disable function but the init needs to be
- * called again to change it.
- *
- * @return 
- *      - IX_SSP_SUCCESS - Successfully initialize and enable the SSP
- *									serial port.
- *		- IX_SSP_RX_FIFO_HANDLER_MISSING - interrupt mode is selected but RX FIFO
- *									handler pointer is NULL
- *		- IX_SSP_TX_FIFO_HANDLER_MISSING - interrupt mode is selected but TX FIFO
- *									handler pointer is NULL
- *		- IX_SSP_RX_FIFO_OVERRUN_HANDLER_MISSING - interrupt mode is selected but
- *									RX FIFO Overrun handler pointer is NULL
- *		- IX_SSP_RX_FIFO_NOT_EMPTY - Rx FIFO not empty, data size change is not
- *			                        allowed.
- *		- IX_SSP_TX_FIFO_NOT_EMPTY - Tx FIFO not empty, data size change is not
- *			                        allowed.
- *		- IX_SSP_INVALID_FRAME_FORMAT_ENUM_VALUE - frame format selected is invalid
- *		- IX_SSP_INVALID_DATA_SIZE_ENUM_VALUE - data size selected is invalid
- *		- IX_SSP_INVALID_CLOCK_SOURCE_ENUM_VALUE - clock source selected is invalid
- *		- IX_SSP_INVALID_TX_FIFO_THRESHOLD_ENUM_VALUE - Tx FIFO threshold level
- *									selected is invalid
- *		- IX_SSP_INVALID_RX_FIFO_THRESHOLD_ENUM_VALUE - Rx FIFO threshold level
- *									selected is invalid
- *		- IX_SSP_INVALID_SPI_PHASE_ENUM_VALUE - SPI phase selected is invalid
- *		- IX_SSP_INVALID_SPI_POLARITY_ENUM_VALUE - SPI polarity selected is invalid
- *		- IX_SSP_INVALID_MICROWIRE_CTL_CMD_ENUM_VALUE - microwire control command
- *									size is invalid
- *      - IX_SSP_INT_UNBIND_FAIL - interrupt handler failed to unbind SSP interrupt
- *		- IX_SSP_INT_BIND_FAIL - interrupt handler failed to bind to SSP interrupt
- *									hardware trigger
- *      - IX_SSP_NOT_SUPORTED - hardware does not support SSP
- *      - IX_SSP_NULL_POINTER - parameter passed in is NULL
- *              
- * @li   Reentrant    : yes
- * @li   ISR Callable : yes
- *
- */
-PUBLIC IX_SSP_STATUS
-ixSspAccInit (IxSspInitVars *initVarsSelected);
-
-/**
- * @ingroup IxSspAcc
- * 
- * @fn ixSspAccUninit (
-	void)
- *
- * @brief Un-initializes the SSP Serial Port Access component
- *
- * @param - None
- *
- * Global Data	:
- *		- None.
- *                        
- * This API will disable the SSP Serial Port hardware. The client can call the
- * init function again if they wish to enable the SSP.
- *
- * @return 
- *      - IX_SSP_SUCCESS - successfully uninit SSP component
- *      - IX_SSP_INT_UNBIND_FAIL - interrupt handler failed to unbind SSP interrupt
- *              
- * @li   Reentrant    : yes
- * @li   ISR Callable : yes
- *
- */
-PUBLIC IX_SSP_STATUS
-ixSspAccUninit (void);
-
-/**
- * @ingroup IxSspAcc
- * 
- * @fn ixSspAccFIFODataSubmit (
-	UINT16 *data,
-	UINT32 amtOfData)
- *
- * @brief Inserts data into the SSP Serial Port's FIFO
- *
- * @param	"UINT16 [in] *data" - pointer to the location to transmit the data
- *				from
- *			"UINT32 [in] amtOfData" - number of data to be transmitted.
- *
- * Global Data	:
- *		- None.
- *                        
- * This API will insert the amount of data specified by "amtOfData" from buffer
- * pointed to by "data" into the FIFO to be transmitted by the hardware.
- *
- * @return 
- *      - IX_SSP_SUCCESS - Data inserted successfully into FIFO
- *		- IX_SSP_FAIL - FIFO insufficient space
- *		- IX_SSP_NULL_POINTER - data pointer passed by client is NULL
- *		- IX_SSP_NOT_INIT - SSP not initialized. SSP init needs to be called.
- *              
- * @li   Reentrant    : yes
- * @li   ISR Callable : yes
- *
- */
-PUBLIC IX_SSP_STATUS
-ixSspAccFIFODataSubmit (
-	UINT16* data,
-	UINT32 amtOfData);
-
-/**
- * @ingroup IxSspAcc
- * 
- * @fn ixSspAccFIFODataReceive (
-	UINT16 *data,
-	UINT32 amtOfData)
- *
- * @brief Extract data from the SSP Serial Port's FIFO
- *
- * @param	"UINT16 [in] *data" - pointer to the location to receive the data into
- *			"UINT32 [in] amtOfData" - number of data to be received.
- *
- * Global Data	:
- *		- None.
- *                        
- * This API will extract the amount of data specified by "amtOfData" from the
- * FIFO already received by the hardware into the buffer pointed to by "data".
- *
- * @return 
- *      - IX_SSP_SUCCESS - Data extracted successfully from FIFO
- *		- IX_SSP_FAIL - FIFO has no data
- *		- IX_SSP_NULL_POINTER - data pointer passed by client is NULL
- *		- IX_SSP_NOT_INIT - SSP not initialized. SSP init needs to be called.
- *              
- * @li   Reentrant    : yes
- * @li   ISR Callable : yes
- *
- */
-PUBLIC IX_SSP_STATUS
-ixSspAccFIFODataReceive (
-	UINT16* data,
-	UINT32 amtOfData);
-
-
-/**
- * Polling Functions
- */
-
-/**
- * @ingroup IxSspAcc
- * 
- * @fn ixSspAccTxFIFOHitOrBelowThresholdCheck (
-		void)
- *
- * @brief Check if the Tx FIFO threshold has been hit or fallen below.
- *
- * @param - None
- *
- * Global Data	:
- *		- None.
- *                        
- * This API will return whether the Tx FIFO threshold has been exceeded or not
- *
- * @return 
- *      - IX_SSP_TX_FIFO_HIT_BELOW_THRESHOLD - Tx FIFO level hit or below threshold .
- *		- IX_SSP_TX_FIFO_EXCEED_THRESHOLD - Tx FIFO level exceeded threshold.
- *		- IX_SSP_NOT_INIT - SSP not initialized. SSP init needs to be called.
- *              
- * @li   Reentrant    : yes
- * @li   ISR Callable : yes
- *
- */
-PUBLIC IX_SSP_STATUS
-ixSspAccTxFIFOHitOrBelowThresholdCheck (
-	void);
-
-/**
- * @ingroup IxSspAcc
- * 
- * @fn ixSspAccRxFIFOHitOrAboveThresholdCheck (
-		void)
- *
- * @brief Check if the Rx FIFO threshold has been hit or exceeded.
- *
- * @param - None
- *
- * Global Data	:
- *		- None.
- *                        
- * This API will return whether the Rx FIFO level is below threshold or not
- *
- * @return 
- *      - IX_SSP_RX_FIFO_HIT_ABOVE_THRESHOLD - Rx FIFO level hit or exceeded threshold
- *		- IX_SSP_RX_FIFO_BELOW_THRESHOLD - Rx FIFO level below threshold
- *		- IX_SSP_NOT_INIT - SSP not initialized. SSP init needs to be called.
- *              
- * @li   Reentrant    : yes
- * @li   ISR Callable : yes
- *
- */
-PUBLIC IX_SSP_STATUS
-ixSspAccRxFIFOHitOrAboveThresholdCheck (
-	void);
-
-
-/**
- * Configuration functions
- *
- * NOTE: These configurations are not required to be called once init is called
- * unless configurations need to be changed on the fly.
- */
-
-/**
- * @ingroup IxSspAcc
- * 
- * @fn ixSspAccSSPPortStatusSet (
-	IxSspAccPortStatus portStatusSelected)
- *
- * @brief Enables/disables the SSP Serial Port hardware.
- *
- * @param "IxSspAccPortStatus [in] portStatusSelected" - Set the SSP port to
- *			enable or disable
- *
- * Global Data	:
- *		- None.
- *                        
- * This API will enable/disable the SSP Serial Port hardware.
- * NOTE: This function is called by init to enable the SSP after setting up the
- * configurations and by uninit to disable the SSP.
- *
- * @return 
- *      - IX_SSP_SUCCESS - Port status set with valid enum value
- *		- IX_SSP_FAIL - invalid enum value
- *		- IX_SSP_NOT_INIT - SSP not initialized. SSP init needs to be called.
- *              
- * @li   Reentrant    : yes
- * @li   ISR Callable : yes
- *
- */
-PUBLIC IX_SSP_STATUS
-ixSspAccSSPPortStatusSet (
-	IxSspAccPortStatus portStatusSelected);
-
-/**
- * @ingroup IxSspAcc
- * 
- * @fn ixSspAccFrameFormatSelect (
-	IxSspAccFrameFormat frameFormatSelected)
- *
- * @brief Sets the frame format for the SSP Serial Port hardware
- *
- * @param "IxSspAccFrameFormat [in] frameFormatSelected" - The frame format of
- *			SPI, SSP or Microwire can be selected as the format
- *
- * Global Data	:
- *		- None.
- *                        
- * This API will set the format for the transfers via user input.
- * *NOTE*: The SSP hardware will be disabled to clear the FIFOs. Then its
- * previous state (enabled/disabled) restored after changing the format.
- *
- * @return 
- *      - IX_SSP_SUCCESS - frame format set with valid enum value
- *		- IX_SSP_INVALID_FRAME_FORMAT_ENUM_VALUE - invalid frame format value
- *		- IX_SSP_NOT_INIT - SSP not initialized. SSP init needs to be called.
- *              
- * @li   Reentrant    : yes
- * @li   ISR Callable : yes
- *
- */
-PUBLIC IX_SSP_STATUS
-ixSspAccFrameFormatSelect (
-	IxSspAccFrameFormat frameFormatSelected);
-
-/**
- * @ingroup IxSspAcc
- * 
- * @fn ixSspAccDataSizeSelect (
-	IxSspAccDataSize dataSizeSelected)
- *
- * @brief Sets the data size for transfers
- *
- * @param "IxSspAccDataSize [in] dataSizeSelected" - The data size between 4
- *			and 16 that can be selected for data transfers
- *
- * Global Data	:
- *		- None.
- *                        
- * This API will set the data size for the transfers via user input. It will
- * disallow the change of the data size if either of the Rx/Tx FIFO is not
- * empty to prevent data loss.
- * *NOTE*: The SSP port will be disabled if the FIFOs are found to be empty and
- *			if between the check and disabling of the SSP (which clears the
- *			FIFOs) data is received into the FIFO, it might be lost.
- * *NOTE*: The FIFOs can be cleared by disabling the SSP Port if necessary to
- *			force the data size change.
- *
- * @return 
- *      - IX_SSP_SUCCESS - data size set with valid enum value
- *		- IX_SSP_RX_FIFO_NOT_EMPTY - Rx FIFO not empty, data size change is not
- *							allowed.
- *		- IX_SSP_TX_FIFO_NOT_EMPTY - Tx FIFO not empty, data size change is not
- *							allowed.
- *		- IX_SSP_INVALID_DATA_SIZE_ENUM_VALUE - invalid enum value
- *		- IX_SSP_NOT_INIT - SSP not initialized. SSP init needs to be called.
- *              
- * @li   Reentrant    : yes
- * @li   ISR Callable : yes
- *
- */
-PUBLIC IX_SSP_STATUS
-ixSspAccDataSizeSelect (
-	IxSspAccDataSize dataSizeSelected);
-
-/**
- * @ingroup IxSspAcc
- * 
- * @fn ixSspAccClockSourceSelect(
-	IxSspAccClkSource clkSourceSelected)
- *
- * @brief Sets the clock source of the SSP Serial Port hardware
- *
- * @param "IxSspAccClkSource [in] clkSourceSelected" - The clock source from
- *			either external source on on-chip can be selected as the source
- *
- * Global Data	:
- *		- None.
- *                        
- * This API will set the clock source for the transfers via user input.
- *
- * @return 
- *      - IX_SSP_SUCCESS - clock source set with valid enum value
- *		- IX_SSP_INVALID_CLOCK_SOURCE_ENUM_VALUE - invalid enum value
- *		- IX_SSP_NOT_INIT - SSP not initialized. SSP init needs to be called.
- *              
- * @li   Reentrant    : yes
- * @li   ISR Callable : yes
- *
- */
-PUBLIC IX_SSP_STATUS
-ixSspAccClockSourceSelect (
-	IxSspAccClkSource clkSourceSelected);
-
-/**
- * @ingroup IxSspAcc
- * 
- * @fn ixSspAccSerialClockRateConfigure (
-	UINT8 serialClockRateSelected)
- *
- * @brief Sets the on-chip Serial Clock Rate of the SSP Serial Port hardware.
- *
- * @param "UINT8 [in] serialClockRateSelected" - The serial clock rate that can
- *			be set is between 7.2Kbps and 1.8432Mbps. The formula used is
- *			Bit rate = 3.6864x10^6 / (2 x (SerialClockRateSelected + 1))
- *
- * Global Data	:
- *		- None.
- *                        
- * This API will set the serial clock rate for the transfers via user input.
- *
- * @return 
- *      - IX_SSP_SUCCESS - Serial clock rate configured successfully
- *		- IX_SSP_NOT_INIT - SSP not initialized. SSP init needs to be called.
- *              
- * @li   Reentrant    : yes
- * @li   ISR Callable : yes
- *
- */
-PUBLIC IX_SSP_STATUS
-ixSspAccSerialClockRateConfigure (
-	UINT8 serialClockRateSelected);
-
-/**
- * @ingroup IxSspAcc
- * 
- * @fn ixSspAccRxFIFOIntEnable (
-	RxFIFOThresholdHandler rxFIFOIntrHandler)
- *
- * @brief Enables service request interrupt whenever the Rx FIFO hits its
- *		threshold
- *
- * @param "void [in] *rxFIFOIntrHandler(UINT32)" - function pointer to the
- *				interrupt handler for the Rx FIFO exceeded.
- *
- * Global Data	:
- *		- None.
- *                        
- * This API will enable the service request interrupt for the Rx FIFO
- *
- * @return 
- *      - IX_SSP_SUCCESS - Rx FIFO level interrupt enabled successfully
- *		- IX_SSP_RX_FIFO_HANDLER_MISSING - missing handler for Rx FIFO level interrupt
- *		- IX_SSP_POLL_MODE_BLOCKING - poll mode is selected at init, interrupt not
- *				allowed to be enabled. Use init to enable interrupt mode.
- *		- IX_SSP_NOT_INIT - SSP not initialized. SSP init needs to be called.
- *              
- * @li   Reentrant    : yes
- * @li   ISR Callable : yes
- *
- */
-PUBLIC IX_SSP_STATUS
-ixSspAccRxFIFOIntEnable (
-	RxFIFOThresholdHandler rxFIFOIntrHandler);
-
-/**
- * @ingroup IxSspAcc
- * 
- * @fn ixSspAccRxFIFOIntDisable (
-	void)
- *
- * @brief Disables service request interrupt of the Rx FIFO.
- *
- * @param - None
- *
- * Global Data	:
- *		- None.
- *                        
- * This API will disable the service request interrupt of the Rx FIFO.
- *
- * @return 
- *		- IX_SSP_SUCCESS - Rx FIFO Interrupt disabled successfully
- *		- IX_SSP_NOT_INIT - SSP not initialized. SSP init needs to be called.
- *              
- * @li   Reentrant    : yes
- * @li   ISR Callable : yes
- *
- */
-PUBLIC IX_SSP_STATUS
-ixSspAccRxFIFOIntDisable (
-	void);
-
-/**
- * @ingroup IxSspAcc
- * 
- * @fn ixSspAccTxFIFOIntEnable (
-	TxFIFOThresholdHandler txFIFOIntrHandler)
- *
- * @brief Enables service request interrupt of the Tx FIFO.
- *
- * @param "void [in] *txFIFOIntrHandler(UINT32)" - function pointer to the
- *				interrupt handler for the Tx FIFO exceeded.
- *
- * Global Data	:
- *		- None.
- *                        
- * This API will enable the service request interrupt of the Tx FIFO.
- *
- * @return 
- *      - IX_SSP_SUCCESS - Tx FIFO level interrupt enabled successfully
- *		- IX_SSP_TX_FIFO_HANDLER_MISSING - missing handler for Tx FIFO level interrupt
- *		- IX_SSP_POLL_MODE_BLOCKING - poll mode is selected at init, interrupt not
- *				allowed to be enabled. Use init to enable interrupt mode.
- *		- IX_SSP_NOT_INIT - SSP not initialized. SSP init needs to be called.
- *              
- * @li   Reentrant    : yes
- * @li   ISR Callable : yes
- *
- */
-PUBLIC IX_SSP_STATUS
-ixSspAccTxFIFOIntEnable (
-	TxFIFOThresholdHandler txFIFOIntrHandler);
-
-/**
- * @ingroup IxSspAcc
- * 
- * @fn ixSspAccTxFIFOIntDisable (
-	void)
- *
- * @brief Disables service request interrupt of the Tx FIFO
- *
- * @param - None
- *
- * Global Data	:
- *		- None.
- *                        
- * This API will disable the service request interrupt of the Tx FIFO
- *
- * @return 
- *		- IX_SSP_SUCCESS - Tx FIFO Interrupt disabled successfuly.
- *		- IX_SSP_NOT_INIT - SSP not initialized. SSP init needs to be called.
- *              
- * @li   Reentrant    : yes
- * @li   ISR Callable : yes
- *
- */
-PUBLIC IX_SSP_STATUS
-ixSspAccTxFIFOIntDisable (
-	void);
-
-/**
- * @ingroup IxSspAcc
- * 
- * @fn ixSspAccLoopbackEnable (
-	BOOL loopbackEnable)
- *
- * @brief Enables/disables the loopback mode
- *
- * @param "BOOL [in] loopbackEnable" - true to enable and false to disable.
- *
- * Global Data	:
- *		- None.
- *                        
- * This API will set the mode of operation to either loopback or normal mode
- * according to the user input.
- *
- * @return 
- *		- IX_SSP_SUCCESS - Loopback enabled successfully
- *		- IX_SSP_NOT_INIT - SSP not initialized. SSP init needs to be called.
- *              
- * @li   Reentrant    : yes
- * @li   ISR Callable : yes
- *
- */
-PUBLIC IX_SSP_STATUS
-ixSspAccLoopbackEnable (
-	BOOL loopbackEnable);
-
-/**
- * @ingroup IxSspAcc
- * 
- * @fn ixSspAccSpiSclkPolaritySet (
-	IxSspAccSpiSclkPolarity spiSclkPolaritySelected)
- *
- * @brief Sets the SPI SCLK Polarity to Low or High
- *
- * @param - "IxSspAccSpiSclkPolarity [in] spiSclkPolaritySelected" - SPI SCLK
- *				polarity that can be selected to either high or low
- *
- * Global Data	:
- *		- None.
- *                        
- * This API is only used for the SPI frame format and will set the SPI SCLK polarity
- * to either low or high
- *
- * @return 
- *      - IX_SSP_SUCCESS - SPI Sclk polarity set with valid enum value
- *		- IX_SSP_INVALID_SPI_POLARITY_ENUM_VALUE - invalid SPI polarity value
- *		- IX_SSP_NOT_INIT - SSP not initialized. SSP init needs to be called.
- *              
- * @li   Reentrant    : yes
- * @li   ISR Callable : yes
- *
- */
-PUBLIC IX_SSP_STATUS
-ixSspAccSpiSclkPolaritySet (
-	IxSspAccSpiSclkPolarity spiSclkPolaritySelected);
-
-/**
- * @ingroup IxSspAcc
- * 
- * @fn ixSspAccSpiSclkPhaseSet (
-	IxSspAccSpiSclkPhase spiSclkPhaseSelected)
- *
- * @brief Sets the SPI SCLK Phase
- *
- * @param "IxSspAccSpiSclkPhase [in] spiSclkPhaseSelected" - Phase of either
- *			the SCLK is inactive one cycle at the start of a frame and 1/2
- *			cycle at the end of a frame, OR
- *			the SCLK is inactive 1/2 cycle at the start of a frame and one
- *			cycle at the end of a frame.
- *
- * Global Data	:
- *		- IX_SSP_SUCCESS - SPI Sclk phase set with valid enum value
- *		- IX_SSP_INVALID_SPI_PHASE_ENUM_VALUE - invalid SPI phase value
- *		- IX_SSP_NOT_INIT - SSP not initialized. SSP init needs to be called.
- *                        
- * This API is only used for the SPI frame format and will set the SPI SCLK
- * phase according to user input.
- *
- * @return 
- *      - None
- *              
- * @li   Reentrant    : yes
- * @li   ISR Callable : yes
- *
- */
-PUBLIC IX_SSP_STATUS
-ixSspAccSpiSclkPhaseSet (
-	IxSspAccSpiSclkPhase spiSclkPhaseSelected);
-
-/**
- * @ingroup IxSspAcc
- * 
- * @fn ixSspAccMicrowireControlWordSet (
-	IxSspAccMicrowireCtlWord microwireCtlWordSelected)
- *
- * @brief Sets the Microwire control word to 8 or 16 bit format
- *
- * @param "IxSspAccMicrowireCtlWord [in] microwireCtlWordSelected" - Microwire
- *			control word format can be either 8 or 16 bit format
- *
- * Global Data	:
- *		- None.
- *                        
- * This API is only used for the Microwire frame format and will set the
- * control word to 8 or 16 bit format
- *
- * @return 
- *      - IX_SSP_SUCCESS - Microwire Control Word set with valid enum value
- *		- IX_SSP_TX_FIFO_NOT_EMPTY - Tx FIFO not empty, data size change is not
- *							allowed.
- *		- IX_SSP_INVALID_MICROWIRE_CTL_CMD_ENUM_VALUE - invalid enum value
- *		- IX_SSP_NOT_INIT - SSP not initialized. SSP init needs to be called.
- *              
- * @li   Reentrant    : yes
- * @li   ISR Callable : yes
- *
- */
-PUBLIC IX_SSP_STATUS
-ixSspAccMicrowireControlWordSet (
-	IxSspAccMicrowireCtlWord microwireCtlWordSelected);
-
-/**
- * @ingroup IxSspAcc
- * 
- * @fn ixSspAccTxFIFOThresholdSet (
-	IxSspAccFifoThreshold txFIFOThresholdSelected)
- *
- * @brief Sets the Tx FIFO Threshold.
- *
- * @param "IxSspAccFifoThreshold [in] txFIFOThresholdSelected" - Threshold that
- *		is set for a Tx FIFO service request to be triggered
- *
- * Global Data	:
- *		- None.
- *                        
- * This API will set the threshold for a Tx FIFO threshold to be triggered
- *
- * @return 
- *      - IX_SSP_SUCCESS - Tx FIFO Threshold set with valid enum value
- *		- IX_SSP_INVALID_TX_FIFO_THRESHOLD_ENUM_VALUE - invalid enum value
- *		- IX_SSP_NOT_INIT - SSP not initialized. SSP init needs to be called.
- *              
- * @li   Reentrant    : yes
- * @li   ISR Callable : yes
- *
- */
-PUBLIC IX_SSP_STATUS
-ixSspAccTxFIFOThresholdSet (
-	IxSspAccFifoThreshold txFIFOThresholdSelected);
-
-/**
- * @ingroup IxSspAcc
- * 
- * @fn ixSspAccRxFIFOThresholdSet (
-	IxSspAccFifoThreshold rxFIFOThresholdSelected)
- *
- * @brief Sets the Rx FIFO Threshold.
- *
- * @param "IxSspAccFifoThreshold [in] rxFIFOThresholdSelected" - Threshold that
- *		is set for a Tx FIFO service request to be triggered
- *
- * Global Data	:
- *		- None.
- *                        
- * This API will will set the threshold for a Rx FIFO threshold to be triggered
- *
- * @return 
- *      - IX_SSP_SUCCESS - Rx FIFO Threshold set with valid enum value
- *		- IX_SSP_INVALID_RX_FIFO_THRESHOLD_ENUM_VALUE - invalid enum value
- *		- IX_SSP_NOT_INIT - SSP not initialized. SSP init needs to be called.
- *              
- * @li   Reentrant    : yes
- * @li   ISR Callable : yes
- *
- */
-PUBLIC IX_SSP_STATUS
-ixSspAccRxFIFOThresholdSet (
-	IxSspAccFifoThreshold rxFIFOThresholdSelected);
-
-
-/**
- * Debug functions
- */
-
-/**
- * @ingroup IxSspAcc
- * 
- * @fn ixSspAccStatsGet (
-	IxSspAccStatsCounters *sspStats)
- *
- * @brief Returns the SSP Statistics through the pointer passed in
- *
- * @param "IxSspAccStatsCounters [in] *sspStats" - SSP statistics counter will
- *			be read and written to the location pointed by this pointer.
- *
- * Global Data	:
- *		- None.
- *                        
- * This API will return the statistics counters of the SSP transfers.
- *
- * @return 
- *      - IX_SSP_SUCCESS - Stats obtained into the pointer provided successfully
- *		- IX_SSP_FAIL - client provided pointer is NULL
- *              
- * @li   Reentrant    : yes
- * @li   ISR Callable : yes
- *
- */
-PUBLIC IX_SSP_STATUS
-ixSspAccStatsGet (
-	IxSspAccStatsCounters *sspStats);
-
-/**
- * @ingroup IxSspAcc
- * 
- * @fn ixSspAccStatsReset (
-	void)
- *
- * @brief Resets the SSP Statistics
- *
- * @param - None
- *
- * Global Data	:
- *		- None.
- *                        
- * This API will reset the SSP statistics counters.
- *
- * @return 
- *      - None
- *              
- * @li   Reentrant    : yes
- * @li   ISR Callable : yes
- *
- */
-PUBLIC void
-ixSspAccStatsReset (
-	void);
-
-/**
- * @ingroup IxSspAcc
- * 
- * @fn ixSspAccShow (
-		void)
- *
- * @brief Display SSP status registers and statistics counters.
- *
- * @param - None
- *
- * Global Data	:
- *		- None.
- *                        
- * This API will display the status registers of the SSP and the statistics
- * counters.
- *
- * @return 
- *		- IX_SSP_SUCCESS - SSP show called successfully.
- *		- IX_SSP_NOT_INIT - SSP not initialized. SSP init needs to be called.
- *              
- * @li   Reentrant    : yes
- * @li   ISR Callable : yes
- *
- */
-PUBLIC IX_SSP_STATUS
-ixSspAccShow (
-	void);
-
-/**
- * @ingroup IxSspAcc
- * 
- * @fn ixSspAccSSPBusyCheck (
-		void)
- *
- * @brief Determine the state of the SSP serial port hardware.
- *
- * @param - None
- *
- * Global Data	:
- *		- None.
- *                        
- * This API will return the state of the SSP serial port hardware - busy or
- * idle
- *
- * @return 
- *      - IX_SSP_BUSY - SSP is busy
- *		- IX_SSP_IDLE - SSP is idle.
- *		- IX_SSP_NOT_INIT - SSP not initialized. SSP init needs to be called.
- *              
- * @li   Reentrant    : yes
- * @li   ISR Callable : yes
- *
- */
-PUBLIC IX_SSP_STATUS
-ixSspAccSSPBusyCheck (
-	void);
-
-/**
- * @ingroup IxSspAcc
- * 
- * @fn ixSspAccTxFIFOLevelGet (
-		void)
- *
- * @brief Obtain the Tx FIFO's level
- *
- * @param - None
- *
- * Global Data	:
- *		- None.
- *                        
- * This API will return the level of the Tx FIFO
- *
- * @return 
- *      - 0..16; 0 can also mean SSP not initialized and will need to be init.
- *              
- * @li   Reentrant    : yes
- * @li   ISR Callable : yes
- *
- */
-PUBLIC UINT8
-ixSspAccTxFIFOLevelGet (
-	void);
-
-/**
- * @ingroup IxSspAcc
- * 
- * @fn ixSspAccRxFIFOLevelGet (
-		void)
- *
- * @brief Obtain the Rx FIFO's level
- *
- * @param - None
- *
- * Global Data	:
- *		- None.
- *                        
- * This API will return the level of the Rx FIFO
- *
- * @return 
- *      - 0..16; 0 can also mean SSP not initialized and will need to be init.
- *              
- * @li   Reentrant    : yes
- * @li   ISR Callable : yes
- *
- */
-PUBLIC UINT8
-ixSspAccRxFIFOLevelGet (
-	void);
-
-/**
- * @ingroup IxSspAcc
- * 
- * @fn ixSspAccRxFIFOOverrunCheck (
-		void)
- *
- * @brief Check if the Rx FIFO has overrun its FIFOs
- *
- * @param - None
- *
- * Global Data	:
- *		- None.
- *                        
- * This API will return whether the Rx FIFO has overrun its 16 FIFOs
- *
- * @return 
- *      - IX_SSP_OVERRUN_OCCURRED - Rx FIFO overrun occurred
- *		- IX_SSP_NO_OVERRUN - Rx FIFO did not overrun
- *		- IX_SSP_NOT_INIT - SSP not initialized. SSP init needs to be called.
- *
- * @li   Reentrant    : yes
- * @li   ISR Callable : yes
- *
- */
-PUBLIC IX_SSP_STATUS
-ixSspAccRxFIFOOverrunCheck (
-	void);
-
-#endif /* __ixp46X */
-#endif /* IXSSPACC_H */
diff --git a/drivers/net/npe/include/IxTimeSyncAcc.h b/drivers/net/npe/include/IxTimeSyncAcc.h
deleted file mode 100644
index f8bcffe8bd..0000000000
--- a/drivers/net/npe/include/IxTimeSyncAcc.h
+++ /dev/null
@@ -1,759 +0,0 @@
-/**
- * @file IxTimeSyncAcc.h
- *
- * @author Intel Corporation
- * @date 07 May 2004
- *
- * @brief  Header file for IXP400 Access Layer to IEEE 1588(TM) Precision
- * Clock Synchronisation Protocol Hardware Assist
- *
- * @version 1
- *
- * @par
- * IXP400 SW Release version 2.0
- * 
- * -- Copyright Notice --
- * 
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- * 
- * @par
- * SPDX-License-Identifier:	BSD-3-Clause
- * @par
- * -- End of Copyright Notice --
- */
-
-/**
- * @defgroup IxTimeSyncAcc IXP400 Time Sync Access Component API 
- *
- * @brief Public API for IxTimeSyncAcc
- *
- * @{
- */
-#ifndef IXTIMESYNCACC_H
-#define IXTIMESYNCACC_H
-
-#ifdef  __ixp46X
-
-#include "IxOsal.h"
-
-/**
- * Section for enum
- */
-
-/**
- * @ingroup IxTimeSyncAcc
- * 
- * @enum IxTimeSyncAccStatus
- *
- * @brief The status as returned from the API
- */
-typedef enum /**< IxTimeSyncAccStatus */
-{
-    IX_TIMESYNCACC_SUCCESS = IX_SUCCESS,    /**< Requested operation successful */
-    IX_TIMESYNCACC_INVALIDPARAM,            /**< An invalid parameter was passed */
-    IX_TIMESYNCACC_NOTIMESTAMP,             /**< While polling no time stamp available */
-    IX_TIMESYNCACC_INTERRUPTMODEINUSE,      /**< Polling not allowed while operating in interrupt mode */
-    IX_TIMESYNCACC_FAILED                   /**< Internal error occurred */
-}IxTimeSyncAccStatus;
-
-/**
- * @ingroup IxTimeSyncAcc
- * 
- * @enum IxTimeSyncAccAuxMode
- *
- * @brief Master or Slave Auxiliary Time Stamp (Snap Shot)
- */
-typedef enum /**< IxTimeSyncAccAuxMode */
-{
-    IX_TIMESYNCACC_AUXMODE_MASTER,          /**< Auxiliary Master Mode */
-    IX_TIMESYNCACC_AUXMODE_SLAVE,           /**< Auxiliary Slave Mode */
-    IX_TIMESYNCACC_AUXMODE_INVALID          /**< Invalid Auxiliary Mode */
-}IxTimeSyncAccAuxMode;
-
-/**
- * @ingroup IxTimeSyncAcc
- * 
- * @enum IxTimeSyncAcc1588PTPPort
- *
- * @brief IEEE 1588 PTP Communication Port(Channel)
- */
-typedef enum /**< IxTimeSyncAcc1588PTPPort */
-{
-    IX_TIMESYNCACC_NPE_A_1588PTP_PORT,      /**< PTP Communication Port on NPE-A */
-    IX_TIMESYNCACC_NPE_B_1588PTP_PORT,      /**< PTP Communication Port on NPE-B */
-    IX_TIMESYNCACC_NPE_C_1588PTP_PORT,      /**< PTP Communication Port on NPE-C */
-    IX_TIMESYNCACC_NPE_1588PORT_INVALID     /**< Invalid PTP Communication Port */
-} IxTimeSyncAcc1588PTPPort;
-
-/**
- * @ingroup IxTimeSyncAcc
- * 
- * @enum IxTimeSyncAcc1588PTPPortMode
- *
- * @brief Master or Slave mode for IEEE 1588 PTP Communication Port
- */
-typedef enum  /**< IxTimeSyncAcc1588PTPPortMode */
-{
-    IX_TIMESYNCACC_1588PTP_PORT_MASTER,       /**< PTP Communication Port in Master Mode */
-    IX_TIMESYNCACC_1588PTP_PORT_SLAVE,        /**< PTP Communication Port in Slave Mode */
-    IX_TIMESYNCACC_1588PTP_PORT_ANYMODE,      /**< PTP Communication Port in ANY Mode
-                                                  allows time stamping of all messages
-                                                  including non-1588 PTP */
-    IX_TIMESYNCACC_1588PTP_PORT_MODE_INVALID  /**< Invalid PTP Port Mode */
-}IxTimeSyncAcc1588PTPPortMode;
-
-/**
- * @ingroup IxTimeSyncAcc
- * 
- * @enum IxTimeSyncAcc1588PTPMsgType
- *
- * @brief 1588 PTP Messages types that can be detected on communication port
- *
- * Note that client code can determine this based on master/slave mode in which
- * it is already operating in and this information is made available for the sake
- * of convenience only.
- */
-typedef enum  /**< IxTimeSyncAcc1588PTPMsgType */
-{
-    IX_TIMESYNCACC_1588PTP_MSGTYPE_SYNC,     /**< PTP Sync message sent by Master or received by Slave */
-    IX_TIMESYNCACC_1588PTP_MSGTYPE_DELAYREQ, /**< PTP Delay_Req message sent by Slave or received by Master */
-    IX_TIMESYNCACC_1588PTP_MSGTYPE_UNKNOWN   /**< Other PTP and non-PTP message sent or received by both
-                                                Master and/or Slave */
-} IxTimeSyncAcc1588PTPMsgType;
-
-/**
- * Section for struct
- */
-
-/**
- * @ingroup IxTimeSyncAcc
- *
- * @struct IxTimeSyncAccTimeValue
- *
- * @brief Struct to hold 64 bit SystemTime and TimeStamp values
- */
-typedef struct  /**< IxTimeSyncAccTimeValue */
-{
-    UINT32 timeValueLowWord;               /**< Lower 32 bits of the time value */
-    UINT32 timeValueHighWord;              /**< Upper 32 bits of the time value */  
-} IxTimeSyncAccTimeValue;
-
-/**
- * @ingroup IxTimeSyncAcc
- *
- * @struct IxTimeSyncAccUuid
- *
- * @brief Struct to hold 48 bit UUID values captured in Sync or Delay_Req messages
- */
-typedef struct  /**< IxTimeSyncAccUuid */
-{
-    UINT32 uuidValueLowWord;               /**<The lower 32 bits of the UUID */
-    UINT16 uuidValueHighHalfword;          /**<The upper 16 bits of the UUID */  
-} IxTimeSyncAccUuid;
-
-/**
- * @ingroup IxTimeSyncAcc
- *
- * @struct IxTimeSyncAccPtpMsgData
- *
- * @brief Struct for data from the PTP message returned when TimeStamp available
- */
-typedef struct  /**< IxTimeSyncAccPtpMsgData */
-{
-    IxTimeSyncAcc1588PTPMsgType ptpMsgType; /**< PTP Messages type */
-    IxTimeSyncAccTimeValue ptpTimeStamp;    /**< 64 bit TimeStamp value from PTP Message */
-    IxTimeSyncAccUuid ptpUuid;              /**< 48 bit UUID value from the PTP Message */
-    UINT16 ptpSequenceNumber;               /**< 16 bit Sequence Number from PTP Message */
-} IxTimeSyncAccPtpMsgData;
-
-/**
- * @ingroup IxTimeSyncAcc
- *
- * @struct IxTimeSyncAccStats
- *
- * @brief Statistics for the PTP messages
- */
-typedef struct  /**< IxTimeSyncAccStats */
-{
-    UINT32 rxMsgs; /**< Count of timestamps for received PTP Messages */
-    UINT32 txMsgs; /**< Count of timestamps for transmitted PTP Messages */
-} IxTimeSyncAccStats;
-
-/**
- * @ingroup IxTimeSyncAcc
- *
- * @typedef IxTimeSyncAccTargetTimeCallback
- *
- * @brief Callback for use by target time stamp interrupt
- */
-typedef void (*IxTimeSyncAccTargetTimeCallback)(IxTimeSyncAccTimeValue targetTime);
-
-/**
- * @ingroup IxTimeSyncAcc
- *
- * @typedef IxTimeSyncAccAuxTimeCallback
- *
- * @brief Callback for use by auxiliary time interrupts
- */
-typedef void (*IxTimeSyncAccAuxTimeCallback)(IxTimeSyncAccAuxMode auxMode,
-             IxTimeSyncAccTimeValue auxTime);
-
-/*
- * Section for prototypes interface functions
- */
-
-/**
- * @ingroup IxTimeSyncAcc
- * 
- * @fn IxTimeSyncAccStatus ixTimeSyncAccPTPPortConfigSet(
-                               IxTimeSyncAcc1588PTPPort ptpPort,
-                               IxTimeSyncAcc1588PTPPortMode ptpPortMode)
- *
- * @brief Configures the IEEE 1588 message detect on particular PTP port.
- *
- * @param ptpPort [in] - PTP port to config
- * @param ptpPortMode [in]- Port to operate in Master or Slave mode
- *
- * This API will enable the time stamping on a particular PTP port.
- *          
- * @li Re-entrant   : No
- * @li ISR Callable : No
- * 
- * @return @li IX_TIMESYNCACC_SUCCESS - Operation is successful
- *         @li IX_TIMESYNCACC_INVALIDPARAM - Invalid parameters passed
- *         @li IX_TIMESYNCACC_FAILED - Internal error occurred
- */
-PUBLIC IxTimeSyncAccStatus
-ixTimeSyncAccPTPPortConfigSet(IxTimeSyncAcc1588PTPPort ptpPort,
-       IxTimeSyncAcc1588PTPPortMode ptpPortMode);
-
-/**
- * @ingroup IxTimeSyncAcc
- * 
- * @fn IxTimeSyncAccStatus ixTimeSyncAccPTPPortConfigGet(
-                               IxTimeSyncAcc1588PTPPort ptpPort,
-                               IxTimeSyncAcc1588PTPPortMode *ptpPortMode)
- *
- * @brief Retrieves IEEE 1588 PTP operation mode on particular PTP port.
- *
- * @param ptpPort [in] - PTP port
- * @param ptpPortMode [in]- Mode of operation of PTP port (Master or Slave)
- *
- * This API will identify the time stamping capability of a PTP port by means
- * of obtaining its mode of operation.
- *          
- * @li Re-entrant   : No
- * @li ISR Callable : No
- * 
- * @return @li IX_TIMESYNCACC_SUCCESS - Operation is successful
- *         @li IX_TIMESYNCACC_INVALIDPARAM - Invalid parameters passed
- *         @li IX_TIMESYNCACC_FAILED - Internal error occurred
- */
-PUBLIC IxTimeSyncAccStatus
-ixTimeSyncAccPTPPortConfigGet(IxTimeSyncAcc1588PTPPort ptpPort,
-    IxTimeSyncAcc1588PTPPortMode *ptpPortMode);
-
-/**
- * @ingroup IxTimeSyncAcc
- * 
- * @fn IxTimeSyncAccStatus ixTimeSyncAccPTPRxPoll(
-                               IxTimeSyncAcc1588PTPPort ptpPort,
-                               IxTimeSyncAccPtpMsgData  *ptpMsgData)
- *
- * @brief Polls the IEEE 1588 message/time stamp detect status on a particular 
- * PTP Port on the Receive side.
- *
- * @param ptpPort [in] - PTP port to poll
- * @param ptpMsgData [out] - Current TimeStamp and other Data
- *
- * This API will poll for the availability of a time stamp on the received Sync 
- * (Slave) or Delay_Req (Master) messages.
- * The client application will provide the buffer.
- *              
- * @li Re-entrant   : No
- * @li ISR Callable : No
- * 
- * @return @li IX_TIMESYNCACC_SUCCESS - Operation is successful
- *         @li IX_TIMESYNCACC_INVALIDPARAM - Invalid parameters passed
- *         @li IX_TIMESYNCACC_NOTIMESTAMP - No time stamp available
- *         @li IX_TIMESYNCACC_FAILED - Internal error occurred
- */
-PUBLIC IxTimeSyncAccStatus
-ixTimeSyncAccPTPRxPoll(IxTimeSyncAcc1588PTPPort ptpPort,
-    IxTimeSyncAccPtpMsgData  *ptpMsgData);
-
-/**
- * @ingroup IxTimeSyncAcc
- * 
- * @fn IxTimeSyncAccStatus ixTimeSyncAccPTPTxPoll(
-                               IxTimeSyncAcc1588PTPPort ptpPort,
-                               IxTimeSyncAccPtpMsgData  *ptpMsgData)
- *
- *
- * @brief Polls the IEEE 1588 message/time stamp detect status on a particular 
- * PTP Port on the Transmit side.
- *
- * @param ptpPort [in] - PTP port to poll
- * @param ptpMsgData [out] - Current TimeStamp and other Data
- *                        
- * This API will poll for the availability of a time stamp on the transmitted
- * Sync (Master) or Delay_Req (Slave) messages.
- * The client application will provide the buffer.
- *              
- * @li Re-entrant   : No
- * @li ISR Callable : No
- * 
- * @return @li IX_TIMESYNCACC_SUCCESS - Operation is successful
- *         @li IX_TIMESYNCACC_INVALIDPARAM - Invalid parameters passed
- *         @li IX_TIMESYNCACC_NOTIMESTAMP - No time stamp available
- *         @li IX_TIMESYNCACC_FAILED - Internal error occurred
- */
-PUBLIC IxTimeSyncAccStatus
-ixTimeSyncAccPTPTxPoll(IxTimeSyncAcc1588PTPPort ptpPort,
-    IxTimeSyncAccPtpMsgData  *ptpMsgData);
-
-/**
- * @ingroup IxTimeSyncAcc
- * 
- * @fn IxTimeSyncAccStatus ixTimeSyncAccSystemTimeSet(
-                               IxTimeSyncAccTimeValue systemTime)
- *
- * @brief Sets the System Time in the IEEE 1588 hardware assist block
- *
- * @param systemTime [in] - Value to set System Time
- *                        
- * This API will set the SystemTime to given value.
- *              
- * @li Re-entrant   : yes
- * @li ISR Callable : no
- * 
- * @return @li IX_TIMESYNCACC_SUCCESS - Operation is successful
- *         @li IX_TIMESYNCACC_FAILED - Internal error occurred
- */
-PUBLIC IxTimeSyncAccStatus
-ixTimeSyncAccSystemTimeSet(IxTimeSyncAccTimeValue systemTime);
-
-/**
- * @ingroup IxTimeSyncAcc
- * 
- * @fn IxTimeSyncAccStatus ixTimeSyncAccSystemTimeGet(
-                               IxTimeSyncAccTimeValue *systemTime)
- *
- * @brief Gets the System Time from the IEEE 1588 hardware assist block
- *
- * @param systemTime [out] - Copy the current System Time into the client 
- * application provided buffer
- *
- * This API will get the SystemTime from IEEE1588 block and return to client
- *      
- * @li Re-entrant   : no
- * @li ISR Callable : no
- * 
- * @return @li IX_TIMESYNCACC_SUCCESS - Operation is successful
- *         @li IX_TIMESYNCACC_INVALIDPARAM - Invalid parameters passed
- *         @li IX_TIMESYNCACC_FAILED - Internal error occurred
- */
-PUBLIC IxTimeSyncAccStatus
-ixTimeSyncAccSystemTimeGet(IxTimeSyncAccTimeValue *systemTime);
-
-/**
- * @ingroup IxTimeSyncAcc
- * 
- * @fn IxTimeSyncAccStatus ixTimeSyncAccTickRateSet(
-                               UINT32 tickRate)
- *
- * @brief Sets the Tick Rate (Frequency Scaling Value) in the IEEE 1588
- * hardware assist block
- *
- * @param tickRate [in] - Value to set Tick Rate
- *                        
- * This API will set the Tick Rate (Frequency Scaling Value) in the IEEE
- * 1588 block to the given value. The Accumulator register (not client 
- * visible) is incremented by this TickRate value every clock cycle. When 
- * the Accumulator overflows, the SystemTime is incremented by one. This
- * TickValue can therefore be used to adjust the system timer.
- *           
- * @li Re-entrant   : yes
- * @li ISR Callable : no
- *
- * @return @li IX_TIMESYNCACC_SUCCESS - Operation is successful
- *         @li IX_TIMESYNCACC_FAILED - Internal error occurred
- */
-PUBLIC IxTimeSyncAccStatus
-ixTimeSyncAccTickRateSet(UINT32 tickRate);
-
-/**
- * @ingroup IxTimeSyncAcc
- * 
- * @fn IxTimeSyncAccStatus ixTimeSyncAccTickRateGet(
-                               UINT32 *tickRate)
- *
- * @brief Gets the Tick Rate (Frequency Scaling Value) from the IEEE 1588
- * hardware assist block
- *
- * @param tickRate [out] - Current Tick Rate value in the IEEE 1588 block
- *
- * This API will get the TickRate on IEE15588 block. Refer to @ref 
- * ixTimeSyncAccTickRateSet for notes on usage of this value.
- *         
- * @li   Reentrant    : yes
- * @li   ISR Callable : no
- *
- * @return @li IX_TIMESYNCACC_SUCCESS - Operation is successful
- *         @li IX_TIMESYNCACC_INVALIDPARAM - Invalid parameters passed
- *         @li IX_TIMESYNCACC_FAILED - Internal error occurred
- */
-PUBLIC IxTimeSyncAccStatus
-ixTimeSyncAccTickRateGet(UINT32 *tickRate);
-
-/**
- * @ingroup IxTimeSyncAcc
- * 
- * @fn IxTimeSyncAccStatus ixTimeSyncAccTargetTimeInterruptEnable(
-                               IxTimeSyncAccTargetTimeCallback targetTimeCallback)
- *
- * @brief Enables the interrupt to verify the condition where the System Time 
- * greater or equal to the Target Time in the IEEE 1588 hardware assist block. 
- * If the condition is true an interrupt will be sent to XScale.
- *
- * @param targetTimeCallback [in] - Callback to be invoked when interrupt fires
- *
- * This API will enable the Target Time reached/hit condition interrupt.
- *
- * NOTE: The client application needs to ensure that the APIs 
- * @ref ixTimeSyncAccTargetTimeInterruptEnable, @ref ixTimeSyncAccTargetTimeSet and
- * @ref ixTimeSyncAccTargetTimeInterruptDisable are accessed in mutual exclusive 
- * manner with respect to each other.
- *
- * @li Re-entrant   : no
- * @li ISR Callable : yes
- *
- * @return @li IX_TIMESYNCACC_SUCCESS - Operation is successful
- *         @li IX_TIMESYNCACC_INVALIDPARAM - Null parameter passed for callback
- *         @li IX_TIMESYNCACC_FAILED - Internal error occurred
- */
-PUBLIC IxTimeSyncAccStatus
-ixTimeSyncAccTargetTimeInterruptEnable(IxTimeSyncAccTargetTimeCallback targetTimeCallback);
-
-/**
- * @ingroup IxTimeSyncAcc
- * 
- * @fn IxTimeSyncAccStatus ixTimeSyncAccTargetTimeInterruptDisable(
-                               void)
- *
- * @brief Disables the interrupt for the condition explained in the function
- * description of @ref ixTimeSyncAccTargetTimeInterruptEnable.
- *
- * This API will disable the Target Time interrupt.
- *
- * NOTE: The client application needs to ensure that the APIs 
- * @ref ixTimeSyncAccTargetTimeInterruptEnable, @ref ixTimeSyncAccTargetTimeSet and
- * @ref ixTimeSyncAccTargetTimeInterruptDisable are accessed in mutual exclusive 
- * manner with respect to each other.
- *              
- * @li Re-entrant   : no
- * @li ISR Callable : yes
- *
- * @return @li IX_TIMESYNCACC_SUCCESS - Operation is successful
- *         @li IX_TIMESYNCACC_FAILED - Internal error occurred
- */
-PUBLIC IxTimeSyncAccStatus
-ixTimeSyncAccTargetTimeInterruptDisable(void);
-
-/**
- * @ingroup IxTimeSyncAcc
- * 
- * @fn IxTimeSyncAccStatus ixTimeSyncAccTargetTimePoll(
-                               BOOL *ttmPollFlag,
-                               IxTimeSyncAccTimeValue *targetTime)
- *
- * @brief Poll to verify the condition where the System Time greater or equal to
- * the Target Time in the IEEE 1588 hardware assist block. If the condition is
- * true an event flag is set in the hardware.
- *
- * @param ttmPollFlag [out] - true  if the target time reached/hit condition event set
- *                            false if the target time reached/hit condition event is
-                                    not set
- * @param targetTime [out] - Capture current targetTime into client provided buffer
- *
- * Poll the target time reached/hit condition status. Return true and the current
- * target time value, if the condition is true else return false.
- *
- * NOTE: The client application will need to clear the event flag that will be set
- * as long as the condition that the System Time greater or equal to the Target Time is
- * valid, in one of the following ways:
- *     1) Invoke the API to change the target time
- *     2) Change the system timer value 
- *              
- * @li Re-entrant   : yes
- * @li ISR Callable : no
- *
- * @return @li IX_TIMESYNCACC_SUCCESS - Operation is successful
- *         @li IX_TIMESYNCACC_INVALIDPARAM - Null parameter passed
- *         @li IX_TIMESYNCACC_FAILED - Internal error occurred
- *         @li IX_TIMESYNCACC_INTERRUPTMODEINUSE - Interrupt mode in use
- */
-PUBLIC IxTimeSyncAccStatus
-ixTimeSyncAccTargetTimePoll(BOOL *ttmPollFlag,
-    IxTimeSyncAccTimeValue *targetTime);
-
-/**
- * @ingroup IxTimeSyncAcc
- * 
- * @fn IxTimeSyncAccStatus ixTimeSyncAccTargetTimeSet(
-                               IxTimeSyncAccTimeValue targetTime)
- *
- * @brief Sets the Target Time in the IEEE 1588 hardware assist block
- *
- * @param targetTime [in] - Value to set Target Time
- *                        
- * This API will set the Target Time to a given value.
- *
- * NOTE: The client application needs to ensure that the APIs 
- * @ref ixTimeSyncAccTargetTimeInterruptEnable, @ref ixTimeSyncAccTargetTimeSet and
- * @ref ixTimeSyncAccTargetTimeInterruptDisable are accessed in mutual exclusive 
- * manner with respect to each other.
- *              
- * @li   Reentrant    : no
- * @li   ISR Callable : yes
- *
- * @return @li IX_TIMESYNCACC_SUCCESS - Operation is successful
- *         @li IX_TIMESYNCACC_FAILED - Internal error occurred
- */
-PUBLIC IxTimeSyncAccStatus
-ixTimeSyncAccTargetTimeSet(IxTimeSyncAccTimeValue targetTime);
-
-/**
- * @ingroup IxTimeSyncAcc
- * 
- * @fn IxTimeSyncAccStatus ixTimeSyncAccTargetTimeGet(
-                               IxTimeSyncAccTimeValue *targetTime)
- *
- * @brief Gets the Target Time in the IEEE 1588 hardware assist block
- *
- * @param targetTime [out] - Copy current time to client provided buffer
- *                                                 
- * This API will get the Target Time from IEEE 1588 block and return to the 
- * client application
- *            
- * @li Re-entrant   : yes
- * @li ISR Callable : no
- *
- * @return @li IX_TIMESYNCACC_SUCCESS - Operation is successful
- *         @li IX_TIMESYNCACC_INVALIDPARAM - Null parameter passed
- *         @li IX_TIMESYNCACC_FAILED - Internal error occurred
- */
-PUBLIC IxTimeSyncAccStatus
-ixTimeSyncAccTargetTimeGet(IxTimeSyncAccTimeValue *targetTime);
-
-/**
- * @ingroup IxTimeSyncAcc
- * 
- * @fn IxTimeSyncAccStatus ixTimeSyncAccAuxTimeInterruptEnable(
-                               IxTimeSyncAccAuxMode auxMode, 
-                               IxTimeSyncAccAuxTimeCallback auxTimeCallback)
- *
- * @brief Enables the interrupt notification for the given mode of Auxiliary Time 
- * Stamp in the IEEE 1588 hardware assist block
- * 
- * @param auxMode [in] - Auxiliary time stamp register (slave or master) to use
- * @param auxTimeCallback [in] - Callback to be invoked when interrupt fires 
- *                                                              
- * This API will enable the Auxiliary Master/Slave Time stamp Interrupt.
- *
- * <pre>
- * NOTE: 1) An individual callback is to be registered for each Slave and Master 
- * Auxiliary Time Stamp registers. Thus to register for both Master and Slave time
- * stamp interrupts either the same callback or two separate callbacks the API has
- * to be invoked twice.
- *       2) On the IXDP465 Development Platform, the Auxiliary Timestamp signal for 
- * slave mode is tied to GPIO 8 pin. This signal is software routed by default to 
- * PCI for backwards compatibility with the IXDP425 Development Platform. This
- * routing must be disabled for the auxiliary slave time stamp register to work 
- * properly. The following commands may be used to accomplish this. However, refer
- * to the IXDP465 Development Platform Users Guide or the BSP/LSP documentation for
- * more specific information.
- *
- * For Linux (at the Redboot prompt i.e., before loading zImage):
- *     mfill -b 0x54100000 -1 -l 1 -p 8
- *     mfill -b 0x54100001 -1 -l 1 -p 0x7f
- * For vxWorks, at the prompt:
- *     intDisable(25)
- *     ixdp400FpgaIODetach(8)
- * </pre>
- *              
- * @li Re-entrant   : no
- * @li ISR Callable : no
- *
- * @return @li IX_TIMESYNCACC_SUCCESS - Operation is successful
- *         @li IX_TIMESYNCACC_INVALIDPARAM - Null parameter passed for callback or
-                                            invalid auxiliary snapshot mode
- *         @li IX_TIMESYNCACC_FAILED - Internal error occurred
- */
-PUBLIC IxTimeSyncAccStatus
-ixTimeSyncAccAuxTimeInterruptEnable(IxTimeSyncAccAuxMode auxMode,
-    IxTimeSyncAccAuxTimeCallback auxTimeCallback);
-
-/**
- * @ingroup IxTimeSyncAcc
- * 
- * @fn IxTimeSyncAccStatus ixTimeSyncAccAuxTimeInterruptDisable(
-                               IxTimeSyncAccAuxMode auxMode)
- *
- * @brief Disables the interrupt for the indicated mode of Auxiliary Time Stamp
- * in the IEEE 1588 hardware assist block
- *
- * @param auxMode [in] - Auxiliary time stamp mode (slave or master) using which
- * the interrupt will be disabled.
- *                        
- * This API will disable the Auxiliary Time Stamp Interrupt (Master or Slave)
- *              
- * @li Re-entrant   : yes
- * @li ISR Callable : no
- *
- * @return @li IX_TIMESYNCACC_SUCCESS - Operation is successful
- *         @li IX_TIMESYNCACC_INVALIDPARAM - Invalid parameters passed
- *         @li IX_TIMESYNCACC_FAILED - Internal error occurred
- */
-PUBLIC IxTimeSyncAccStatus
-ixTimeSyncAccAuxTimeInterruptDisable(IxTimeSyncAccAuxMode auxMode);
-
-/**
- * @ingroup IxTimeSyncAcc
- * 
- * @fn IxTimeSyncAccStatus ixTimeSyncAccAuxTimePoll(
-                               IxTimeSyncAccAuxMode auxMode,
-                               BOOL *auxPollFlag,
-                               IxTimeSyncAccTimeValue *auxTime)
- *
- * @brief Poll for the Auxiliary Time Stamp captured for the mode indicated 
- * (Master or Slave)
- *
- * @param auxMode [in] - Auxiliary Snapshot Register (Slave or Master) to be checked
- * @param auxPollFlag [out] - true if the time stamp captured in auxiliary
-                                   snapshot register
- *                            false if the time stamp not captured in
-                                   auxiliary snapshot register
- * @param auxTime [out] - Copy the current Auxiliary Snapshot Register value into the
- * client provided buffer
- *
- * Polls for the Time stamp in the appropriate Auxiliary Snapshot Registers based 
- * on the mode specified. Return true and the contents of the Auxiliary snapshot,
- * if it is available else return false.
- * 
- * Please refer to the note #2 of the API @ref ixTimeSyncAccAuxTimeInterruptEnable
- * for more information for Auxiliary Slave mode.
- *
- * @li Re-entrant   : yes
- * @li ISR Callable : no
- *
- * @return @li IX_TIMESYNCACC_SUCCESS - Operation is successful
- *         @li IX_TIMESYNCACC_INVALIDPARAM - Null parameter passed for auxPollFlag,
-                   callback or invalid auxiliary snapshot mode
- *         @li IX_TIMESYNCACC_FAILED - Internal error occurred
- *         @li IX_TIMESYNCACC_INTERRUPTMODEINUSE - Interrupt mode in use
- */
-PUBLIC IxTimeSyncAccStatus
-ixTimeSyncAccAuxTimePoll(IxTimeSyncAccAuxMode auxMode,
-    BOOL *auxPollFlag,
-    IxTimeSyncAccTimeValue *auxTime);
-
-/**
- * @ingroup IxTimeSyncAcc
- *
- * @fn IxTimeSyncAccStatus ixTimeSyncAccReset(void)
- *
- * @brief Resets the IEEE 1588 hardware assist block
- *
- * Sets the reset bit in the IEEE1588 silicon which fully resets the silicon block
- *            
- * @li Reentrant    : yes
- * @li ISR Callable : no
- *
- * @return @li IX_TIMESYNCACC_SUCCESS - Operation is successful
- *         @li IX_TIMESYNCACC_FAILED  - Internal error occurred
- */
-PUBLIC IxTimeSyncAccStatus
-ixTimeSyncAccReset(void);
-
-/**
- * @ingroup IxTimeSyncAcc
- *
- * @fn IxTimeSyncAccStatus ixTimeSyncAccStatsGet(IxTimeSyncAccStats
-                               *timeSyncStats)
- *
- * @brief Returns the IxTimeSyncAcc Statistics in the client supplied buffer
- *
- * @param timeSyncStats [out] - TimeSync statistics counter values
- *
- * This API will return the statistics of the received or transmitted messages.
- * 
- * NOTE: 1) These counters are updated only when the client polls for the time 
- * stamps or interrupt are enabled. This is because the IxTimeSyncAcc module 
- * does not either transmit or receive messages and does only run the code 
- * when explicit requests received by client application.
- *
- *       2) These statistics reflect the number of valid PTP messages exchanged
- * in Master and Slave modes but includes all the messages (including valid 
- * non-PTP messages) while operating in the Any mode.
- *              
- * @li Reentrant    : no
- * @li ISR Callable : no
- *
- * @return @li IX_TIMESYNCACC_SUCCESS - Operation is successful
- *         @li IX_TIMESYNCACC_INVALIDPARAM - NULL parameter passed
- *         @li IX_TIMESYNCACC_FAILED - Internal error occurred
- */
-PUBLIC IxTimeSyncAccStatus
-ixTimeSyncAccStatsGet(IxTimeSyncAccStats *timeSyncStats);
-
-/**
- * @ingroup IxTimeSyncAcc
- *
- * @fn void ixTimeSyncAccStatsReset(void)
- *
- * @brief Reset Time Sync statistics
- *
- * This API will reset the statistics counters of the TimeSync access layer.
- *             
- * @li Reentrant    : yes
- * @li ISR Callable:  no
- *
- * @return @li None
- */
-PUBLIC void
-ixTimeSyncAccStatsReset(void);
-
-/**
- * @ingroup IxTimeSyncAcc
- *
- * @fn IxTimeSyncAccStatus ixTimeSyncAccShow(void)
- *
- * @brief Displays the Time Sync current status
- *
- * This API will display status on the current configuration of the IEEE
- * 1588 hardware assist block, contents of the various time stamp registers,
- * outstanding interrupts and/or events.
- *
- * Note that this is intended for debug only, and in contrast to the other
- * functions, it does not clear the any of the status bits associated with
- * active timestamps and so is passive in its nature.
- *            
- * @li Reentrant    : yes
- * @li ISR Callable : no
- *
- * @return @li IX_TIMESYNCACC_SUCCESS - Operation is successful
- *         @li IX_TIMESYNCACC_FAILED - Internal error occurred
- */
-PUBLIC IxTimeSyncAccStatus
-ixTimeSyncAccShow(void);
-
-#endif /* __ixp46X */
-#endif /* IXTIMESYNCACC_H */
-
-/**
- * @} defgroup IxTimeSyncAcc
- */
-
diff --git a/drivers/net/npe/include/IxTimerCtrl.h b/drivers/net/npe/include/IxTimerCtrl.h
deleted file mode 100644
index a865b933a3..0000000000
--- a/drivers/net/npe/include/IxTimerCtrl.h
+++ /dev/null
@@ -1,239 +0,0 @@
-/** 
- * @file IxTimerCtrl.h
- * @brief 
- *    This is the header file for the Timer Control component.
- *
- *    The timer callback control component provides a mechanism by which different 
- *    client components can start a timer and have a supplied callback function
- *    invoked when the timer expires.
- *    The callbacks are all dispatched from one thread inside this component. 
- *    Any component that needs to be called periodically should use this facility 
- *    rather than create its own task with a sleep loop. 
- *
- * @par
- * 
- * @par
- * IXP400 SW Release version 2.0
- * 
- * -- Copyright Notice --
- * 
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- * 
- * @par
- * SPDX-License-Identifier:	BSD-3-Clause
- * @par
- * -- End of Copyright Notice --
-*/
-
-/**
- * @defgroup IxTimerCtrl IXP400 Timer Control (IxTimerCtrl) API
- *
- * @brief The public API for the IXP400 Timer Control Component.
- *
- * @{
- */
-
-#ifndef IxTimerCtrl_H
-#define IxTimerCtrl_H
-
-
-#include "IxTypes.h"
-/* #include "Ossl.h" */
-
-/*
- * #defines and macros used in this file.
- */
-
-/**
- * @ingroup IxTimerCtrl
- *
- * @def IX_TIMERCTRL_NO_FREE_TIMERS
- *
- * @brief Timer schedule return code.
- *
- * Indicates that the request to start a timer failed because
- * all available timer resources are used. 
- */
-#define IX_TIMERCTRL_NO_FREE_TIMERS 2
-
-
-/**
- * @ingroup IxTimerCtrl
- *
- * @def IX_TIMERCTRL_PARAM_ERROR
- *
- * @brief Timer schedule return code.
- *
- * Indicates that the request to start a timer failed because
- * the client has supplied invalid parameters.
- */
-#define IX_TIMERCTRL_PARAM_ERROR 3
-
- 
-/*
- * Typedefs whose scope is limited to this file.
- */
-
-/**
- * @ingroup IxTimerCtrl
- *
- * @brief A typedef for a pointer to a timer callback function. 
- * @para void * - This parameter is supplied by the client when the
- * timer is started and passed back to the client in the callback.
- * @note in general timer callback functions should not block or 
- * take longer than 100ms. This constraint is required to ensure that
- * higher priority callbacks are not held up. 
- * All callbacks are called from the same thread. 
- * This thread is a shared resource. 
- * The parameter passed is provided when the timer is scheduled.
- */
-typedef void (*IxTimerCtrlTimerCallback)(void *userParam);
-
-
-/**
- * @ingroup IxTimerCtrl
- *
- * @brief List used to identify the users of timers.
- * @note The order in this list indicates priority.  Components appearing 
- * higher in the list will be given priority over components lower in the
- * list.  When adding components, please insert at an appropriate position
- * for priority ( i.e values should be less than IxTimerCtrlMaxPurpose ) .
- */
-typedef enum 
-{
-    IxTimerCtrlAdslPurpose,
-   /* Insert new purposes above this line only
-    */
-   IxTimerCtrlMaxPurpose
-}
-IxTimerCtrlPurpose;
-
-
-/*
- * Function definition
- */
-
-/**
- * @ingroup IxTimerCtrl
- *
- * @fn ixTimerCtrlSchedule(IxTimerCtrlTimerCallback func, 
-                       void *userParam, 
-                       IxTimerCtrlPurpose purpose,
-	               UINT32 relativeTime,
-                       unsigned *timerId )
- * 
- * @brief Schedules a callback function to be called after a period of "time".
- * The callback function should not block or run for more than 100ms.
- * This function 
- *
- * @param func @ref IxTimerCtrlTimerCallback [in] - the callback function to be called.
- * @param userParam void [in] - a parameter to send to the callback function, can be NULL.
- * @param purpose @ref IxTimerCtrlPurpose [in] - the purpose of the callback, internally this component will 
- * decide the priority of callbacks with different purpose.
- * @param relativeTime UINT32 [in] - time relative to now in milliseconds after which the callback 
- * will be called. The time must be greater than the duration of one OS tick.
- * @param *timerId unsigned [out] -  An id for the callback scheduled. 
- * This id can be used to cancel the callback.
- * @return 
- * @li IX_SUCCESS - The timer was started successfully.
- * @li IX_TIMERCTRL_NO_FREE_TIMERS - The timer was not started because the maximum number
- * of running timers has been exceeded.
- * @li IX_TIMERCTRL_PARAM_ERROR - The timer was not started because the client has supplied 
- * a NULL callback func, or the requested timeout is less than one OS tick.
- * @note  This function is re-entrant. The function accesses a list of running timers
- * and may suspend the calling thread if this list is being accesed by another thread.
- */
-PUBLIC IX_STATUS 
-ixTimerCtrlSchedule(IxTimerCtrlTimerCallback func, 
-                       void *userParam, 
-                       IxTimerCtrlPurpose purpose,
-	               UINT32 relativeTime,
-                       unsigned *timerId );
-
-
-/**
- * @ingroup IxTimerCtrl
- *
- * @fn ixTimerCtrlScheduleRepeating(IxTimerCtrlTimerCallback func, 
-                                void *param, 
-                                IxTimerCtrlPurpose purpose,
-			        UINT32 interval,
-                                unsigned *timerId )
- * 
- * @brief Schedules a callback function to be called after a period of "time".
- * The callback function should not block or run for more than 100ms.
- *
- * @param func @ref IxTimerCtrlTimerCallback [in] - the callback function to be called.
- * @param userParam void [in] - a parameter to send to the callback function, can be NULL.
- * @param purpose @ref IxTimerCtrlPurpose [in] - the purpose of the callback, internally this component will 
- * decide the priority of callbacks with different purpose.
- * @param interval UINT32 [in] - the interval in milliseconds between calls to func. 
- * @param timerId unsigned [out] - An id for the callback scheduled. 
- * This id can be used to cancel the callback.
- * @return 
- * @li IX_SUCCESS - The timer was started successfully.
- * @li IX_TIMERCTRL_NO_FREE_TIMERS - The timer was not started because the maximum number
- * of running timers has been exceeded.
- * @li IX_TIMERCTRL_PARAM_ERROR - The timer was not started because the client has supplied 
- * a NULL callback func, or the requested timeout is less than one OS tick.
- * @note  This function is re-entrant. The function accesses a list of running timers
- * and may suspend the calling thread if this list is being accesed by another thread.
- */
-PUBLIC IX_STATUS 
-ixTimerCtrlScheduleRepeating(IxTimerCtrlTimerCallback func, 
-                                void *param, 
-                                IxTimerCtrlPurpose purpose,
-			        UINT32 interval,
-                                unsigned *timerId );
-
-/**
- * @ingroup IxTimerCtrl
- *
- * @fn ixTimerCtrlCancel (unsigned id)
- *
- * @brief Cancels a scheduled callback.
- *
- * @param id unsigned [in] - the id of the callback to be cancelled.
- * @return
- * @li IX_SUCCESS - The timer was successfully stopped.
- * @li IX_FAIL - The id parameter did not corrrespond to any running timer..
- * @note This function is re-entrant. The function accesses a list of running timers
- * and may suspend the calling thread if this list is being accesed by another thread.
- */
-PUBLIC IX_STATUS
-ixTimerCtrlCancel (unsigned id);
-
-/**
- * @ingroup IxTimerCtrl
- *
- * @fn ixTimerCtrlInit(void)
- *
- * @brief Initialise the Timer Control Component.
- * @return 
- * @li IX_SUCCESS - The timer control component initialized successfully.
- * @li IX_FAIL - The timer control component initialization failed,
- * or the component was already initialized.
- * @note This must be done before any other API function is called.
- * This function should be called once only and is not re-entrant.
- */
-PUBLIC IX_STATUS
-ixTimerCtrlInit(void);
-
-
-/**
- * @ingroup IxTimerCtrl
- *
- * @fn ixTimerCtrlShow( void )
- *
- * @brief Display the status of the Timer Control Component. 
- * @return void
- * @note Displays a list of running timers.
- * This function is not re-entrant. This function does not suspend the calling thread.
- */
-PUBLIC void
-ixTimerCtrlShow( void );
-
-#endif  /* IXTIMERCTRL_H */
-
diff --git a/drivers/net/npe/include/IxTypes.h b/drivers/net/npe/include/IxTypes.h
deleted file mode 100644
index f936a50bb3..0000000000
--- a/drivers/net/npe/include/IxTypes.h
+++ /dev/null
@@ -1,62 +0,0 @@
-/**
- * @file IxTypes.h (Replaced by OSAL)
- *
- * @date 28-NOV-2001
-
- * @brief This file contains basic types used by the IXP400 software
- *
- * Design Notes:
- *    This file shall only include fundamental types and definitions to be
- *    shared by all the IXP400 components.
- *    Please DO NOT add component-specific types here.
- *
- * 
- * @par
- * IXP400 SW Release version 2.0
- * 
- * -- Copyright Notice --
- * 
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- * 
- * @par
- * SPDX-License-Identifier:	BSD-3-Clause
- * @par
- * -- End of Copyright Notice --
- */
-
-/**
- * @defgroup IxTypes IXP400 Types (IxTypes) 
- *
- * @brief Basic data types used by the IXP400 project
- *
- * @{
- */
-
-#ifndef IxTypes_H
-
-#ifndef __doxygen_HIDE
-
-#define IxTypes_H
-
-#endif /* __doxygen_HIDE */
-
-
-/* WR51880: Undefined data types workaround for backward compatibility */
-#ifdef __linux
-#ifndef __INCvxTypesOldh
-typedef int (*FUNCPTR)(void);
-typedef int STATUS;
-#define OK (0)
-#define ERROR (-1)
-#endif
-#endif
-
-#include "IxOsalBackward.h"
-
-#endif /* IxTypes_H */
-
-/**
- * @} addtogroup IxTypes
- */
diff --git a/drivers/net/npe/include/IxUART.h b/drivers/net/npe/include/IxUART.h
deleted file mode 100644
index ff23b22fe7..0000000000
--- a/drivers/net/npe/include/IxUART.h
+++ /dev/null
@@ -1,434 +0,0 @@
-/** 
- * @file IxUART.h
- *
- * @date 12-OCT-01
- *
- * @brief Public header for the Intel IXP400 internal UART, generic driver.
- * 
- * Design Notes:
- * This driver allows you to perform the following functions: 
- *	Device Initialization,
- *	send/receive characters.
- *
- * Perform Uart IOCTL for the following:
- *	Set/Get the current baud rate,
- *	set parity,
- *	set the number of Stop bits,
- *	set the character Length (5,6,7,8),
- *	enable/disable Hardware flow control.
- *
- * Only Polled mode is supported for now.
- *    
- * 
- * @par
- * IXP400 SW Release version 2.0
- * 
- * -- Copyright Notice --
- * 
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- * 
- * @par
- * SPDX-License-Identifier:	BSD-3-Clause
- * @par
- * -- End of Copyright Notice --
-*/
-
-/**
- * @defgroup IxUARTAccAPI IXP400 UART Access (IxUARTAcc) API
- *
- * @brief IXP400 UARTAcc Driver Public API
- * 
- * @{
- */
-
-
-/* Defaults */
-
-/**
- * @defgroup DefaultDefines Defines for Default Values
- *
- * @brief Default values which can be used for UART configuration
- *
- * @sa ixUARTDev
- */
-
-/**
- * @def IX_UART_DEF_OPTS
- *
- * @brief The default hardware options to set the UART to -
- * no flow control, 8 bit word, 1 stop bit, no parity 
- *
- * @ingroup DefaultDefines
- */
-#define IX_UART_DEF_OPTS (CLOCAL | CS8)
-
-/**
- * @def IX_UART_DEF_XMIT
- *
- * @brief The default UART FIFO size - must be no bigger than 64
- *
- * @ingroup DefaultDefines
- */
-#define IX_UART_DEF_XMIT 64
-
-/**
- * @def IX_UART_DEF_BAUD
- *
- * @brief The default UART baud rate - 9600
- *
- * @ingroup DefaultDefines
- */
-#define IX_UART_DEF_BAUD 9600
-
-/**
- * @def IX_UART_MIN_BAUD
- *
- * @brief The minimum UART baud rate - 9600
- *
- * @ingroup DefaultDefines
- */
-#define IX_UART_MIN_BAUD 9600
-
-/**
- * @def IX_UART_MAX_BAUD
- *
- * @brief The maximum UART baud rate - 926100
- *
- * @ingroup DefaultDefines
- */
-#define IX_UART_MAX_BAUD 926100
-
-/**
- * @def IX_UART_XTAL
- *
- * @brief The UART clock speed
- *
- * @ingroup DefaultDefines
- */
-#define IX_UART_XTAL 14745600
-
-
-
-/* IOCTL commands (Request codes) */
-
-/**
- * @defgroup IoctlCommandDefines Defines for IOCTL Commands
- *
- * @brief IOCTL Commands (Request codes) which can be used
- *        with @ref ixUARTIoctl
- */
-
-
-/**
- * @ingroup IoctlCommandDefines
- *
- * @def IX_BAUD_SET
- *
- * @brief Set the baud rate
- */
-#define IX_BAUD_SET	0
-
-/**
- * @ingroup IoctlCommandDefines
- *
- * @def IX_BAUD_GET
- *
- * @brief Get the baud rate
- */
-#define IX_BAUD_GET	1
-
-/**
- * @ingroup IoctlCommandDefines
- * @def IX_MODE_SET
- * @brief Set the UART mode of operation
- */
-#define IX_MODE_SET	2
-
-/**
- * @ingroup IoctlCommandDefines
- *
- * @def IX_MODE_GET
- *
- * @brief Get the current UART mode of operation
- */
-#define IX_MODE_GET	3
-
-/**
- * @ingroup IoctlCommandDefines
- *
- * @def IX_OPTS_SET
- *
- * @brief Set the UART device options
- */
-#define IX_OPTS_SET	4
-
-/**
- * @ingroup IoctlCommandDefines
- *
- * @def IX_OPTS_GET
- *
- * @brief Get the UART device options
- */
-#define IX_OPTS_GET	5
-
-/**
- * @ingroup IoctlCommandDefines
- *
- * @def IX_STATS_GET
- *
- * @brief Get the UART statistics
- */
-#define IX_STATS_GET	6
-
-
-/* POSIX style ioctl arguments */
-
-/**
- * @defgroup IoctlArgDefines Defines for IOCTL Arguments
- *
- * @brief POSIX style IOCTL arguments which can be used
- *        with @ref ixUARTIoctl
- *
- * @sa ixUARTMode
- */
-
-
-/**
- * @ingroup IoctlArgDefines
- *
- * @def CLOCAL
- *
- * @brief Software flow control
- */
-#ifdef CLOCAL
-#undef CLOCAL
-#endif
-#define CLOCAL		0x1
-
-/**
- * @ingroup IoctlArgDefines
- *
- * @def CREAD
- *
- * @brief Enable interrupt receiver
- */
-#ifdef CREAD
-#undef CREAD
-#endif
-#define CREAD		0x2
-
-/**
- * @ingroup IoctlArgDefines
- *
- * @def CSIZE
- *
- * @brief Characters size
- */
-#ifdef CSIZE
-#undef CSIZE
-#endif
-#define CSIZE		0xc
-
-/**
- * @ingroup IoctlArgDefines
- *
- * @def CS5
- *
- * @brief 5 bits
- */
-#ifdef CS5
-#undef CS5
-#endif
-#define CS5		0x0
-
-/**
- * @ingroup IoctlArgDefines
- *
- * @def CS6
- *
- * @brief 6 bits
- */
-#ifdef CS6
-#undef CS6
-#endif
-#define CS6		0x4
-
-/**
- * @ingroup IoctlArgDefines
- *
- * @def CS7
- *
- * @brief 7 bits
- */
-#ifdef CS7
-#undef CS7
-#endif
-#define CS7		0x8
-
-/**
- * @ingroup IoctlArgDefines
- *
- * @def CS8
- *
- * @brief 8 bits
- */
-#ifdef CS8
-#undef CS8
-#endif
-#define CS8		0xc
-
-/**
- * @ingroup IoctlArgDefines
- *
- * @def STOPB
- *
- * @brief Send two stop bits (else one)
- */
-#define STOPB		0x20
-
-/**
- * @ingroup IoctlArgDefines
- *
- * @def PARENB
- *
- * @brief Parity detection enabled (else disabled)
- */
-#ifdef PARENB
-#undef PARENB
-#endif
-#define PARENB		0x40
-
-/**
- * @ingroup IoctlArgDefines
- *
- * @def PARODD
- *
- * @brief Odd parity  (else even)
- */
-#ifdef PARODD
-#undef PARODD
-#endif
-#define PARODD		0x80
-
-/**
- * @enum ixUARTMode
- * @brief The mode to set to UART to.
- */
-typedef enum
-{
-    INTERRUPT=0,	/**< Interrupt mode */
-    POLLED,		/**< Polled mode */
-    LOOPBACK		/**< Loopback mode */
-} ixUARTMode;
-
-/**
- * @struct ixUARTStats
- * @brief Statistics for the UART.
- */
-typedef struct
-{
-    UINT32  rxCount;
-    UINT32  txCount;	
-    UINT32  overrunErr;
-    UINT32  parityErr;
-    UINT32  framingErr;
-    UINT32  breakErr;
-} ixUARTStats;
-
-/**
- * @struct ixUARTDev
- * @brief Device descriptor for the UART.
- */
-typedef struct
-{
-    UINT8 *addr;	/**< device base address */
-    ixUARTMode mode;	/**< interrupt, polled or loopback */
-    int baudRate;	/**< baud rate */
-    int freq;		/**< UART clock frequency */     
-    int options;	/**< hardware options */
-    int fifoSize;	/**< FIFO xmit size */
-
-    ixUARTStats   stats;	/**< device statistics */
-} ixUARTDev;
-
-/**
- * @ingroup IxUARTAccAPI
- *
- * @fn IX_STATUS ixUARTInit(ixUARTDev* pUART)
- * 
- * @param pUART	@ref ixUARTDev [in] - pointer to UART structure describing our device.
- * 
- * @brief Initialise the UART. This puts the chip in a quiescent state.
- * 
- * @pre The base address for the UART must contain a valid value.
- *      Also the baud rate and hardware options must contain sensible values
- *      otherwise the defaults will be used as defined in ixUART.h
- *
- * @post UART is initialized and ready to send and receive data.
- *
- * @note This function should only be called once per device.
- *
- * @retval IX_SUCCESS - UART device successfully initialised.
- * @retval IX_FAIL - Critical error, device not initialised.
- ***************************************************************************/
-PUBLIC IX_STATUS ixUARTInit(ixUARTDev* pUART);
-
-/**
- * @ingroup IxUARTAccAPI
- *
- * @fn IX_STATUS ixUARTPollOutput(ixUARTDev* pUART, int outChar)
- *
- * @param pUART @ref ixUARTDev [out] - pointer to UART structure describing our device.
- * @param outChar int [out] - character to transmit.
- *
- * @brief Transmit a character in polled mode.
- *
- * @pre UART device must be initialised.
- *
- * @retval IX_SUCCESS - character was successfully transmitted.
- * @retval IX_FAIL - output buffer is full (try again).
- ***************************************************************************/
-PUBLIC IX_STATUS ixUARTPollOutput(ixUARTDev* pUART, int outChar);
-
-/**
- * @ingroup IxUARTAccAPI
- *
- * @fn IX_STATUS ixUARTPollInput(ixUARTDev* pUART, char *inChar)
- *
- * @param pUART	@ref ixUARTDev [in] - pointer to UART structure describing our device.
- * @param *inChar char [in] - character read from the device.
- *
- * @brief Receive a character in polled mode.
- *
- * @pre UART device must be initialised.
- *
- * @retval IX_SUCCESS - character was successfully read.
- * @retval IX_FAIL - input buffer empty (try again).
- ***************************************************************************/
-PUBLIC IX_STATUS ixUARTPollInput(ixUARTDev* pUART, char *inChar);
-
-/**
- * @ingroup IxUARTAccAPI
- *
- * @fn IX_STATUS ixUARTIoctl(ixUARTDev* pUART, int cmd, void* arg)
- *
- * @param pUART	@ref ixUARTDev [in] - pointer to UART structure describing our device.
- * @param cmd int [in] - an ioctl request code.
- * @param arg void* [in] - optional argument used to set the device mode,
- *	 baud rate, and hardware options.
- *
- * @brief Perform I/O control routines on the device.
- *
- * @retval IX_SUCCESS - requested feature was set/read successfully.
- * @retval IX_FAIL - error setting/reading the requested feature.
- *
- * @sa IoctlCommandDefines
- * @sa IoctlArgDefines
- ***************************************************************************/    
-PUBLIC IX_STATUS ixUARTIoctl(ixUARTDev* pUART, int cmd, void* arg);
-
-/**
- * @} defgroup IxUARTAcc
- */
diff --git a/drivers/net/npe/include/IxVersionId.h b/drivers/net/npe/include/IxVersionId.h
deleted file mode 100644
index 1769dcda45..0000000000
--- a/drivers/net/npe/include/IxVersionId.h
+++ /dev/null
@@ -1,131 +0,0 @@
-/**
- * @file IxVersionId.h
- *
- * @date 22-Aug-2002
- *
- * @brief This file contains the IXP400 Software version identifier
- *
- * 
- * @par
- * IXP400 SW Release version 2.0
- * 
- * -- Copyright Notice --
- * 
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- * 
- * @par
- * SPDX-License-Identifier:	BSD-3-Clause
- * @par
- * -- End of Copyright Notice --
- */
-
-/**
- * @defgroup IxVersionId IXP400 Version ID (IxVersionId)
- *
- * @brief Version Identifiers
- *
- * @{
- */
-
-#ifndef IXVERSIONID_H
-#define IXVERSIONID_H
-
-/**
- * @brief Version Identifier String
- *
- * This string will be updated with each customer release of the IXP400
- * Software.
- */
-#define IX_VERSION_ID "2_0"
-
-/**
- * This string will be updated with each customer release of the IXP400
- * ADSL driver package.
- */
-#define IX_VERSION_ADSL_ID "1_12"
-
-
-/**
- * This string will be updated with each customer release of the IXP400
- * USB Client driver package.
- */
-#define IX_VERSION_USBRNDIS_ID "1_9"
-
-/**
- * This string will be updated with each customer release of the IXP400
- * I2C Linux driver package.
- */
-#define IX_VERSION_I2C_LINUX_ID "1_0"
-
-/**
- * @brief Linux Ethernet Driver Patch Version Identifier String
- *
- * This string will be updated with each release of Linux Ethernet Patch
- */
-#define LINUX_ETHERNET_DRIVER_PATCH_ID "1_4"
-
-/**
- * @brief Linux Integration Patch Version Identifier String
- *
- * This String will be updated with each release of Linux Integration Patch
- */
-#define LINUX_INTEGRATION_PATCH_ID "1_3"
-
-/**
- * @brief Linux Ethernet Readme version Identifier String
- *
- * This string will be updated with each release of Linux Ethernet Readme
- */
-#define LINUX_ETHERNET_README_ID "1_3"
-
-/**
- * @brief Linux Integration Readme version Identifier String
- *
- * This string will be updated with each release of Linux Integration Readme
- */
-
-#define LINUX_INTEGRATION_README_ID "1_3"
-
-/**
- * @brief Linux I2C driver Readme version Identifier String
- *
- * This string will be updated with each release of Linux I2C Driver Readme
- */
-#define LINUX_I2C_DRIVER_README_ID "1_0"
-
-/**
- * @brief ixp425_eth_update_nf_bridge.patch version Identifier String
- *
- * This string will be updated with each release of ixp425_eth_update_nf_bridge.
-patch
- *
- */
-
-#define IXP425_ETH_UPDATE_NF_BRIDGE_ID "1_3"
-
-/**
- * @brief Internal Release Identifier String
- *
- * This string will be updated with each internal release (SQA drop)
- * of the IXP400 Software.
- */
-#define IX_VERSION_INTERNAL_ID "SQA3_5"
-
-/**
- * @brief Compatible Tornado Version Identifier
- */
-#define IX_VERSION_COMPATIBLE_TORNADO "Tornado2_2_1-PNE2_0"
-
-/**
- * @brief Compatible Linux Version Identifier
- */
-#define IX_VERSION_COMPATIBLE_LINUX "MVL3_1"
-
-
-#endif /* IXVERSIONID_H */
-
-/**
- * @} addtogroup IxVersionId
- */
diff --git a/drivers/net/npe/include/ix_error.h b/drivers/net/npe/include/ix_error.h
deleted file mode 100644
index 4c599996cf..0000000000
--- a/drivers/net/npe/include/ix_error.h
+++ /dev/null
@@ -1,42 +0,0 @@
-/**
- * ============================================================================
- * = COPYRIGHT
- * 
- * @par
- * IXP400 SW Release version 2.0
- * 
- * -- Copyright Notice --
- * 
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- * 
- * @par
- * SPDX-License-Identifier:	BSD-3-Clause
- * @par
- * -- End of Copyright Notice --
- * = PRODUCT
- *      Intel(r) IXP425 Software Release
- *
- * = FILENAME
- *      ix_error.h (Replaced by OSAL)
- *
- * = DESCRIPTION
- *      This file will describe the basic error type and support functions that
- *      will be used by the IXA SDK Framework API.
- *
- * = AUTHOR
- *      Intel Corporation
- *
- * = CHANGE HISTORY
- *      4/22/2002 4:19:03 PM - creation time 
- * ============================================================================
- */
-
-#if !defined(__IX_ERROR_H__)
-#define __IX_ERROR_H__
-
-#include "IxOsalBackward.h"
-
-#endif /* end !defined(__IX_ERROR_H__) */
-
diff --git a/drivers/net/npe/include/ix_macros.h b/drivers/net/npe/include/ix_macros.h
deleted file mode 100644
index b4cf7602ae..0000000000
--- a/drivers/net/npe/include/ix_macros.h
+++ /dev/null
@@ -1,242 +0,0 @@
-/**
- * ============================================================================
- * = COPYRIGHT
- * 
- * @par
- * IXP400 SW Release version 2.0
- * 
- * -- Copyright Notice --
- * 
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- * 
- * @par
- * SPDX-License-Identifier:	BSD-3-Clause
- * @par
- * -- End of Copyright Notice --
- * = PRODUCT
- *      Intel(r) IXP425 Software Release
- *
- * = FILENAME
- *      ix_macros.h
- *
- * = DESCRIPTION
- *      This file will define the basic preprocessor macros that are going to be used
- *      the IXA SDK Framework API.
- *
- * = AUTHOR
- *      Intel Corporation
- *
- * = CHANGE HISTORY
- *      4/22/2002 4:41:05 PM - creation time 
- * ============================================================================
- */
-
-#if !defined(__IX_MACROS_H__)
-#define __IX_MACROS_H__
-
-
-#if defined(__cplusplus)
-extern "C"
-{
-#endif /* end defined(__cplusplus) */
-
-
-/**
- * MACRO NAME: IX_BIT_FIELD_MASK16
- *
- * DESCRIPTION: Builds the mask required to extract the bit field from a 16 bit unsigned integer value.
- *
- * @Param:  - IN arg_FieldLSBBit an unsigned integer value representing the position of the least significant
- *          bit of the bit field.
- * @Param:  - IN arg_FieldMSBBit an unsigned integer value representing the position of the most significant
- *          bit of the bit field.
- *
- * @Return: Returns a 16 bit mask that will extract the bit field from a 16 bit unsigned integer value.
- */
-#define IX_BIT_FIELD_MASK16( \
-                             arg_FieldLSBBit, \
-                             arg_FieldMSBBit \
-                            ) \
-                            ((ix_bit_mask16)((((ix_uint16)1 << (arg_FieldMSBBit + 1 - arg_FieldLSBBit)) - \
-                            (ix_uint16)1) << arg_FieldLSBBit))
-
-
-
-/**
- * MACRO NAME: IX_GET_BIT_FIELD16
- *
- * DESCRIPTION: Extracts a bit field from 16 bit unsigned integer. The returned value is normalized in
- *          in the sense that will be right aligned.
- *
- * @Param:  - IN arg_PackedData16 a 16 bit unsigned integer that contains the bit field of interest.
- * @Param:  - IN arg_FieldLSBBit an unsigned integer value representing the position of the least significant
- *          bit of the bit field.
- * @Param:  - IN arg_FieldMSBBit an unsigned integer value representing the position of the most significant
- *          bit of the bit field.
- *
- * @Return: Returns the value of the bit field. The value can be from 0 to (1 << (arg_FieldMSBBit + 1 -
- *          arg_FieldLSBBit)) - 1.
- */
-#define IX_GET_BIT_FIELD16( \
-                            arg_PackedData16, \
-                            arg_FieldLSBBit, \
-                            arg_FieldMSBBit \
-                          ) \
-                          (((ix_uint16)(arg_PackedData16) & IX_BIT_FIELD_MASK16(arg_FieldLSBBit, arg_FieldMSBBit)) >> \
-                             arg_FieldLSBBit)
-
-
-/**
- * MACRO NAME: IX_MAKE_BIT_FIELD16
- *
- * DESCRIPTION: This macro will create a temporary 16 bit value with the bit field
- *          desired set to the desired value.
- *
- * @Param:  - IN arg_BitFieldValue is the new value of the bit field. The value can be from 0 to 
- *          (1 << (arg_FieldMSBBit + 1 - arg_FieldLSBBit)) - 1.
- * @Param:  - IN arg_FieldLSBBit an unsigned integer value representing the position of the least significant
- *          bit of the bit field.
- * @Param:  - IN arg_FieldMSBBit an unsigned integer value representing the position of the most significant
- *          bit of the bit field.
- * 
- * @Return: Returns a temporary ix_uint16 value that has the bit field set to the appropriate value.
- */
-#define IX_MAKE_BIT_FIELD16( \
-                             arg_BitFieldValue, \
-                             arg_FieldLSBBit, \
-                             arg_FieldMSBBit \
-                           ) \
-                           (((ix_uint16)(arg_BitFieldValue) << arg_FieldLSBBit) & \
-                           IX_BIT_FIELD_MASK16(arg_FieldLSBBit, arg_FieldMSBBit))
-                                 
-/**
- * MACRO NAME: IX_SET_BIT_FIELD16
- *
- * DESCRIPTION: Sets a new value for a bit field from a 16 bit unsigned integer.
- *
- * @Param:  - IN arg_PackedData16 a 16 bit unsigned integer that contains the bit field of interest.
- * @Param:  - IN arg_BitFieldValue is the new vale of the bit field. The value can be from 0 to 
- *          (1 << (arg_FieldMSBBit + 1 - arg_FieldLSBBit)) - 1.
- * @Param:  - IN arg_FieldLSBBit an unsigned integer value representing the position of the least significant
- *          bit of the bit field.
- * @Param:  - IN arg_FieldMSBBit an unsigned integer value representing the position of the most significant
- *          bit of the bit field.
- *
- * @Return: Returns the updated value of arg_PackedData16.
- */
-#define IX_SET_BIT_FIELD16( \
-                            arg_PackedData16, \
-                            arg_BitFieldValue, \
-                            arg_FieldLSBBit, \
-                            arg_FieldMSBBit \
-                          ) \
-                          (arg_PackedData16 = (((ix_uint16)(arg_PackedData16) & \
-                          ~(IX_BIT_FIELD_MASK16(arg_FieldLSBBit, arg_FieldMSBBit))) | \
-                          IX_MAKE_BIT_FIELD16(arg_BitFieldValue, arg_FieldLSBBit, arg_FieldMSBBit))) 
-
-
-/**
- * MACRO NAME: IX_BIT_FIELD_MASK32
- *
- * DESCRIPTION: Builds the mask required to extract the bit field from a 32 bit unsigned integer value.
- *
- * @Param:  - IN arg_FieldLSBBit an unsigned integer value representing the position of the least significant
- *          bit of the bit field.
- * @Param:  - IN arg_FieldMSBBit an unsigned integer value representing the position of the most significant
- *          bit of the bit field.
- *
- * @Return: Returns a 32 bit mask that will extract the bit field from a 32 bit unsigned integer value.
- */
-#define IX_BIT_FIELD_MASK32( \
-                             arg_FieldLSBBit, \
-                             arg_FieldMSBBit \
-                           ) \
-                           ((ix_bit_mask32)((((ix_uint32)1 << (arg_FieldMSBBit + 1 - arg_FieldLSBBit)) - \
-                           (ix_uint32)1) << arg_FieldLSBBit))
-
-
-
-/**
- * MACRO NAME: IX_GET_BIT_FIELD32
- *
- * DESCRIPTION: Extracts a bit field from 32 bit unsigned integer. The returned value is normalized in
- *          in the sense that will be right aligned.
- *
- * @Param:  - IN arg_PackedData32 a 32 bit unsigned integer that contains the bit field of interest.
- * @Param:  - IN arg_FieldLSBBit an unsigned integer value representing the position of the least significant
- *          bit of the bit field.
- * @Param:  - IN arg_FieldMSBBit an unsigned integer value representing the position of the most significant
- *          bit of the bit field.
- *
- * @Return: Returns the value of the bit field. The value can be from 0 to (1 << (arg_FieldMSBBit + 1 -
- *          arg_FieldLSBBit)) - 1.
- */
-#define IX_GET_BIT_FIELD32( \
-                            arg_PackedData32, \
-                            arg_FieldLSBBit, \
-                            arg_FieldMSBBit \
-                          ) \
-                          (((ix_uint32)(arg_PackedData32) & IX_BIT_FIELD_MASK32(arg_FieldLSBBit, arg_FieldMSBBit)) >> \
-                             arg_FieldLSBBit)
-
-
-
-
-/**
- * MACRO NAME: IX_MAKE_BIT_FIELD32
- *
- * DESCRIPTION: This macro will create a temporary 32 bit value with the bit field
- *          desired set to the desired value.
- *
- * @Param:  - IN arg_BitFieldValue is the new value of the bit field. The value can be from 0 to 
- *          (1 << (arg_FieldMSBBit + 1 - arg_FieldLSBBit)) - 1.
- * @Param:  - IN arg_FieldLSBBit an unsigned integer value representing the position of the least significant
- *          bit of the bit field.
- * @Param:  - IN arg_FieldMSBBit an unsigned integer value representing the position of the most significant
- *          bit of the bit field.
- * 
- * @Return: Returns a temporary ix_uint32 value that has the bit field set to the appropriate value.
- */
-#define IX_MAKE_BIT_FIELD32( \
-                             arg_BitFieldValue, \
-                             arg_FieldLSBBit, \
-                             arg_FieldMSBBit \
-                           ) \
-                           (((ix_uint32)(arg_BitFieldValue) << arg_FieldLSBBit) & \
-                           IX_BIT_FIELD_MASK32(arg_FieldLSBBit, arg_FieldMSBBit))
-                            
-                                
-/**
- * MACRO NAME: IX_SET_BIT_FIELD32
- *
- * DESCRIPTION: Sets a new value for a bit field from a 32 bit unsigned integer.
- *
- * @Param:  - IN arg_PackedData32 a 32 bit unsigned integer that contains the bit field of interest.
- * @Param:  - IN arg_BitFieldValue is the new value of the bit field. The value can be from 0 to 
- *          (1 << (arg_FieldMSBBit + 1 - arg_FieldLSBBit)) - 1.
- * @Param:  - IN arg_FieldLSBBit an unsigned integer value representing the position of the least significant
- *          bit of the bit field.
- * @Param:  - IN arg_FieldMSBBit an unsigned integer value representing the position of the most significant
- *          bit of the bit field.
- *
- * @Return: Returns the updated value of arg_PackedData32.
- */
-#define IX_SET_BIT_FIELD32( \
-                            arg_PackedData32, \
-                            arg_BitFieldValue, \
-                            arg_FieldLSBBit, \
-                            arg_FieldMSBBit \
-                          ) \
-                          (arg_PackedData32 = (((ix_uint32)(arg_PackedData32) & \
-                          ~(IX_BIT_FIELD_MASK32(arg_FieldLSBBit, arg_FieldMSBBit))) | \
-                          IX_MAKE_BIT_FIELD32(arg_BitFieldValue, arg_FieldLSBBit, arg_FieldMSBBit))) 
-
-
-
-#if defined(__cplusplus)
-}
-#endif /* end defined(__cplusplus) */
-
-#endif /* end !defined(__IX_MACROS_H__) */
diff --git a/drivers/net/npe/include/ix_os_type.h b/drivers/net/npe/include/ix_os_type.h
deleted file mode 100644
index e14d561c28..0000000000
--- a/drivers/net/npe/include/ix_os_type.h
+++ /dev/null
@@ -1,41 +0,0 @@
-/**
- * ============================================================================
- * = COPYRIGHT
- * 
- * @par
- * IXP400 SW Release version 2.0
- * 
- * -- Copyright Notice --
- * 
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- * 
- * @par
- * SPDX-License-Identifier:	BSD-3-Clause
- * @par
- * -- End of Copyright Notice --
- * = PRODUCT
- *      Intel(r) IXP425 Software Release
- *
- * = FILENAME
- *      ix_os_type.h (Replaced by OSAL)
- *
- * = DESCRIPTION
- *      This file provides protable symbol definitions for the current OS type.
- *
- * = AUTHOR
- *      Intel Corporation
- *
- * = CHANGE HISTORY
- *      4/22/2002 4:43:30 PM - creation time 
- * ============================================================================
- */
-
-#if !defined(__IX_OS_TYPE_H__)
-#define __IX_OS_TYPE_H__
-
-#include "IxOsalBackward.h"
-
-#endif /* end !defined(__IX_OS_TYPE_H__) */
-
diff --git a/drivers/net/npe/include/ix_ossl.h b/drivers/net/npe/include/ix_ossl.h
deleted file mode 100644
index eaa2629b8d..0000000000
--- a/drivers/net/npe/include/ix_ossl.h
+++ /dev/null
@@ -1,136 +0,0 @@
-/**
- * ============================================================================
- * = COPYRIGHT
- * 
- * @par
- * IXP400 SW Release version 2.0
- * 
- * -- Copyright Notice --
- * 
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- * 
- * @par
- * SPDX-License-Identifier:	BSD-3-Clause
- * @par
- * -- End of Copyright Notice --
- * = PRODUCT
- *      Intel(r) IXP425 Software Release
- *
- * = LIBRARY
- *      OSSL - Operating System Services  Library
- *
- * = MODULE
- *      OSSL  Abstraction layer header file
- *
- * = FILENAME
- *       ix_ossl.h (Replaced by OSAL)
- *
- * = DESCRIPTION
- *   This file contains the prototypes of OS-independent wrapper
- *   functions which allow the programmer not to be tied to a specific
- *   operating system. The OSSL functions can be divided into three classes:
- *
- *   1) synchronization-related wrapper functions around thread system calls
- *   2) thread-related wrapper functions around thread calls
- *   3) transactor/workbench osapi calls -- defined in osApi.h
- *
- *   Both 1 and 2 classes of functions provide Thread Management, Thread 
- *   Synchronization, Mutual Exclusion and  Timer primitives. Namely, 
- *   creation and deletion functions as well as the standard "wait" and
- *   "exit". Additionally, a couple of utility functions which enable to 
- *   pause the execution of a thread are also provided.
- *
- *   The 3rd class provides a  slew of other OSAPI functions to handle
- *   Transactor/WorkBench OS calls.
- *
- *
- *   OSSL Thread APIs:
- *             The OSSL thread functions that allow for thread creation,
- *             get thread id, thread deletion and set thread priroity.
- *
- *             ix_ossl_thread_create
- *             ix_ossl_thread_get_id
- *             ix_ossl_thread_exit
- *             ix_ossl_thread_kill
- *             ix_ossl_thread_set_priority
- *             ix_ossl_thread__delay
- * 
- *   OSSL Semaphore APIs:
- *             The OSSL semaphore functions that allow for initialization,
- *             posting, waiting and deletion of semaphores.
- *
- *             ix_ossl_sem_init
- *             ix_ossl_sem_fini
- *             ix_ossl_sem_take
- *             ix_ossl_sem_give
- *             ix_ossl_sem_flush
- *
- *   OSSL Mutex APIs:
- *             The OSSL wrapper functions that allow for initialization,
- *             posting, waiting and deletion of mutexes.
- *
- *             ix_ossl_mutex_init
- *             ix_ossl_mutex_fini
- *             ix_ossl_mutex_lock
- *             ix_ossl_mutex_unlock
- *
- *   OSSL Timer APIs:
- *     	       The timer APIs provide sleep and get time functions.
- *
- *             ix_ossl_sleep
- *             ix_ossl_sleep_tick
- *             ix_ossl_time_get
- * 
- *   OSAPIs for Transactor/WorkBench:
- *             These OSAPI functions are used for transator OS calls. 
- *             They are defined in osApi.h. 
- *
- *             Sem_Init 			
- *             Sem_Destroy 		
- *             Sem_Wait 			
- *             Sem_Wait			
- *             Thread_Create		
- *             Thread_Cancel 		
- *             Thread_SetPriority 		
- *             delayMs 			
- *             delayTick			
- *             
- *
- *
- **********************************************************************
- *      
- *
- * = AUTHOR
- *      Intel Corporation
- *
- * = ACKNOWLEDGEMENTS
- *      
- *
- * = CREATION TIME
- *      1/8/2002 1:53:42 PM
- *
- * = CHANGE HISTORY
- *   02/22/2002 : Renamed osapi.h os_api.h
- *                Moved OS header file includes from OSSL.h to os_api.h
- *                Moved OS specific datatypes to os_api.h 
- *                Modified data types, macros and functions as per
- *                'C' coding guidelines.
- *
- *
- * ============================================================================
- */
-
-#ifndef _IX_OSSL_H
-#ifndef __doxygen_hide
-#define _IX_OSSL_H
-#endif /* __doxygen_hide */
-
-#include "IxOsalBackward.h"
- 
-#endif /* _IX_OSSL_H */
-
-/**
- * @} defgroup IxOSSL
- */
diff --git a/drivers/net/npe/include/ix_symbols.h b/drivers/net/npe/include/ix_symbols.h
deleted file mode 100644
index 0006b227c6..0000000000
--- a/drivers/net/npe/include/ix_symbols.h
+++ /dev/null
@@ -1,82 +0,0 @@
-/**
- * ============================================================================
- * = COPYRIGHT
- * 
- * @par
- * IXP400 SW Release version 2.0
- * 
- * -- Copyright Notice --
- * 
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- * 
- * @par
- * SPDX-License-Identifier:	BSD-3-Clause
- * @par
- * -- End of Copyright Notice --
- * = PRODUCT
- *      Intel(r) IXP425 Software Release
- *
- * = FILENAME
- *      ix_symbols.h
- *
- * = DESCRIPTION
- *      This file declares all the global preprocessor symbols required by 
- *      the IXA SDK Framework API.
- *
- * = AUTHOR
- *      Intel Corporation
- *
- * = CHANGE HISTORY
- *      4/23/2002 10:41:13 AM - creation time 
- * ============================================================================
- */
-
-#if !defined(__IX_SYMBOLS_H__)
-#define __IX_SYMBOLS_H__
-
-
-#if defined(__cplusplus)
-extern "C"
-{
-#endif /* end defined(__cplusplus) */
-
-/**
- * The IX_EXPORT_FUNCTION symbol will be used for compilation on different platforms.
- * We are planning to provide a simulation version of the library that should work
- * with the Transactor rather than the hardware. This implementation will be done on
- * WIN32 in the form of a DLL that will need to export functions and symbols.
- */
-#if (_IX_OS_TYPE_ == _IX_OS_WIN32_)
-#    if defined(_IX_LIB_INTERFACE_IMPLEMENTATION_)
-#        define IX_EXPORT_FUNCTION __declspec( dllexport )
-#    elif defined(_IX_LIB_INTERFACE_IMPORT_DLL_)
-#        define IX_EXPORT_FUNCTION __declspec( dllimport )
-#    else
-#        define IX_EXPORT_FUNCTION extern 
-#    endif
-#elif (_IX_OS_TYPE_ == _IX_OS_WINCE_)
-#    define IX_EXPORT_FUNCTION __declspec(dllexport)
-#else
-#    define IX_EXPORT_FUNCTION  extern
-#endif
-
-
-/**
- * This symbols should be defined when we want to build for a multithreaded environment
- */
-#define _IX_MULTI_THREADED_     1
-    
-
-/**
- * This symbol should be defined in the case we to buils for a multithreaded environment
- * but we want that our modules to work as if they are used in a single threaded environment.
- */
-/* #define _IX_RM_EXPLICIT_SINGLE_THREADED_    1  */
-
-#if defined(__cplusplus)
-}
-#endif /* end defined(__cplusplus) */
-
-#endif /* end !defined(__IX_SYMBOLS_H__) */
diff --git a/drivers/net/npe/include/ix_types.h b/drivers/net/npe/include/ix_types.h
deleted file mode 100644
index 6945506049..0000000000
--- a/drivers/net/npe/include/ix_types.h
+++ /dev/null
@@ -1,184 +0,0 @@
-/**
- * ============================================================================
- * = COPYRIGHT
- * 
- * @par
- * IXP400 SW Release version 2.0
- * 
- * -- Copyright Notice --
- * 
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- * 
- * @par
- * SPDX-License-Identifier:	BSD-3-Clause
- * @par
- * -- End of Copyright Notice --
- * = PRODUCT
- *      Intel(r) IXP425 Software Release
- *
- * = FILENAME
- *      ix_types.h
- *
- * = DESCRIPTION
- *      This file will define generic types that will guarantee the protability
- *      between different architectures and compilers. It should be used the entire
- *      IXA SDK Framework API.
- *
- * = AUTHOR
- *      Intel Corporation
- *
- * = CHANGE HISTORY
- *      4/22/2002 4:44:17 PM - creation time 
- * ============================================================================
- */
-
-#if !defined(__IX_TYPES_H__)
-#define __IX_TYPES_H__
-
-
-#if defined(__cplusplus)
-extern "C"
-{
-#endif /* end defined(__cplusplus) */
-
-
-/**
- * Define generic integral data types that will guarantee the size.
- */
-
-/**
- * TYPENAME: ix_int8
- * 
- * DESCRIPTION: This type defines an 8 bit signed integer value.
- *
- */
-typedef signed char ix_int8;
-
-
-/**
- * TYPENAME: ix_uint8
- * 
- * DESCRIPTION: This type defines an 8 bit unsigned integer value.
- *
- */
-typedef unsigned char ix_uint8;
-
-
-/**
- * TYPENAME: ix_int16
- * 
- * DESCRIPTION: This type defines an 16 bit signed integer value.
- *
- */
-typedef signed short int ix_int16;
-
-
-/**
- * TYPENAME: ix_uint16
- * 
- * DESCRIPTION: This type defines an 16 bit unsigned integer value.
- *
- */
-typedef unsigned short int ix_uint16;
-
-
-/**
- * TYPENAME: ix_int32
- * 
- * DESCRIPTION: This type defines an 32 bit signed integer value.
- *
- */
-typedef signed int ix_int32;
-
-
-/**
- * TYPENAME: ix_uint32
- * 
- * DESCRIPTION: This type defines an 32 bit unsigned integer value.
- *
- */
-#ifndef __wince
-typedef unsigned int ix_uint32;
-#else
-typedef unsigned long ix_uint32;
-#endif
-
-/**
- * TYPENAME: ix_int64
- * 
- * DESCRIPTION: This type defines an 64 bit signed integer value.
- *
- */
-#ifndef __wince
-__extension__ typedef signed long long int ix_int64;
-#endif
-
-/**
- * TYPENAME: ix_uint64
- * 
- * DESCRIPTION: This type defines an 64 bit unsigned integer value.
- *
- */
-#ifndef __wince
-__extension__ typedef unsigned long long int ix_uint64;
-#endif
-
-
-/**
- * TYPENAME: ix_bit_mask8
- * 
- * DESCRIPTION: This is a generic type for a 8 bit mask. 
- */
-typedef ix_uint8 ix_bit_mask8;
-
-
-/**
- * TYPENAME: ix_bit_mask16
- * 
- * DESCRIPTION: This is a generic type for a 16 bit mask. 
- */
-typedef ix_uint16 ix_bit_mask16;
-
-
-/**
- * TYPENAME: ix_bit_mask32
- * 
- * DESCRIPTION: This is a generic type for a 32 bit mask. 
- */
-typedef ix_uint32 ix_bit_mask32;
-
-
-/**
- * TYPENAME: ix_bit_mask64
- * 
- * DESCRIPTION: This is a generic type for a 64 bit mask. 
- */
-#ifndef __wince
-typedef ix_uint64 ix_bit_mask64;
-#endif
-
-
-/**
- * TYPENAME: ix_handle
- * 
- * DESCRIPTION: This type defines a generic handle.
- *
- */
-typedef ix_uint32 ix_handle;
-
-
-
-/**
- * DESCRIPTION: This symbol defines a NULL handle
- *
- */
-#define IX_NULL_HANDLE   ((ix_handle)0) 
-
-
-#if defined(__cplusplus)
-}
-#endif /* end defined(__cplusplus) */
-
-#endif /* end !defined(__IX_TYPES_H__) */
diff --git a/drivers/net/npe/include/npe.h b/drivers/net/npe/include/npe.h
deleted file mode 100644
index 1c6ae26ddc..0000000000
--- a/drivers/net/npe/include/npe.h
+++ /dev/null
@@ -1,74 +0,0 @@
-/*
- * (C) Copyright 2005
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef NPE_H
-#define NPE_H
-
-/*
- * defines...
- */
-#define CONFIG_SYS_NPE_NUMS		1
-#ifdef CONFIG_HAS_ETH1
-#undef CONFIG_SYS_NPE_NUMS
-#define CONFIG_SYS_NPE_NUMS		2
-#endif
-
-#define NPE_NUM_PORTS		3
-#define ACTIVE_PORTS		1
-
-#define NPE_PKT_SIZE		1600
-
-#define CONFIG_DEVS_ETH_INTEL_NPE_MAX_RX_DESCRIPTORS	64
-#define CONFIG_DEVS_ETH_INTEL_NPE_MAX_TX_DESCRIPTORS	2
-
-#define NPE_MBUF_POOL_SIZE					\
-	((CONFIG_DEVS_ETH_INTEL_NPE_MAX_TX_DESCRIPTORS +	\
-	  CONFIG_DEVS_ETH_INTEL_NPE_MAX_RX_DESCRIPTORS) *	\
-	 sizeof(IX_OSAL_MBUF) * ACTIVE_PORTS)
-
-#define NPE_PKT_POOL_SIZE					\
-	((CONFIG_DEVS_ETH_INTEL_NPE_MAX_TX_DESCRIPTORS +	\
-	  CONFIG_DEVS_ETH_INTEL_NPE_MAX_RX_DESCRIPTORS) *	\
-	 NPE_PKT_SIZE * ACTIVE_PORTS)
-
-#define NPE_MEM_POOL_SIZE (NPE_MBUF_POOL_SIZE + NPE_PKT_POOL_SIZE)
-
-#define PHY_AUTONEGOTIATE_TIMEOUT 4000	/* 4000 ms autonegotiate timeout */
-
-/*
- * structs...
- */
-struct npe {
-	u8			active;           /* NPE active				*/
-	u8			eth_id;           /* IX_ETH_PORT_1 or IX_ETH_PORT_2	*/
-	u8			phy_no;           /* which PHY (0 - 31)			*/
-	u8			mac_address[6];
-
-	IX_OSAL_MBUF		*rxQHead;
-	IX_OSAL_MBUF		*txQHead;
-
-	u8			*tx_pkts;
-	u8			*rx_pkts;
-	IX_OSAL_MBUF		*rx_mbufs;
-	IX_OSAL_MBUF		*tx_mbufs;
-
-	int			print_speed;
-
-	int			rx_read;
-	int			rx_write;
-	int			rx_len[PKTBUFSRX];
-};
-
-/*
- * prototypes...
- */
-extern int npe_miiphy_read (const char *devname, unsigned char addr,
-			    unsigned char reg, unsigned short *value);
-extern int npe_miiphy_write (const char *devname, unsigned char addr,
-			     unsigned char reg, unsigned short value);
-
-#endif /* ifndef NPE_H */
diff --git a/drivers/net/npe/include/os_datatypes.h b/drivers/net/npe/include/os_datatypes.h
deleted file mode 100644
index def891b862..0000000000
--- a/drivers/net/npe/include/os_datatypes.h
+++ /dev/null
@@ -1,58 +0,0 @@
-/**
- * ============================================================================
- * = COPYRIGHT
- * 
- * @par
- * IXP400 SW Release version 2.0
- * 
- * -- Copyright Notice --
- * 
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- * 
- * @par
- * SPDX-License-Identifier:	BSD-3-Clause
- * @par
- * -- End of Copyright Notice --
- * = PRODUCT
- *      Intel(r) IXP425 Software Release
- *
- * = LIBRARY
- *      OSSL - Operating System Services  Library
- *
- * = MODULE
- *      OS Specific Data Types header file
- *
- * = FILENAME
- *       OSSL.h (Replaced by OSAL)
- *
- * = DESCRIPTION
- *   This file  contains definitions and encapsulations for OS specific data types. These
- *   encapsulated  data types are  used by OSSL header files and OS API functions.
- *
- *
- **********************************************************************
- *      
- *
- * = AUTHOR
- *      Intel Corporation
- *
- * = AKNOWLEDGEMENTS
- *      
- *
- * = CREATION TIME
- *      1/8/2002 1:53:42 PM
- *
- * = CHANGE HISTORY
- 
- * ============================================================================
- */
-
-#ifndef _OS_DATATYPES_H
-#define _OS_DATATYPES_H
-
-#include "IxOsalBackward.h"
-
-#endif /* _OS_DATATYPES_H */
-
diff --git a/drivers/net/npe/miiphy.c b/drivers/net/npe/miiphy.c
deleted file mode 100644
index 002fb8113b..0000000000
--- a/drivers/net/npe/miiphy.c
+++ /dev/null
@@ -1,101 +0,0 @@
-/*
- * SPDX-License-Identifier:	GPL-2.0	IBM-pibs
- */
-/*-----------------------------------------------------------------------------+
-  |
-  |  File Name:	 miiphy.c
-  |
-  |  Function:	 This module has utilities for accessing the MII PHY through
-  |	       the EMAC3 macro.
-  |
-  |  Author:	 Mark Wisner
-  |
-  |  Change Activity-
-  |
-  |  Date	 Description of Change					     BY
-  |  ---------	 ---------------------					     ---
-  |  05-May-99	 Created						     MKW
-  |  01-Jul-99	 Changed clock setting of sta_reg from 66MHz to 50MHz to
-  |		 better match OPB speed. Also modified delay times.	     JWB
-  |  29-Jul-99	 Added Full duplex support				     MKW
-  |  24-Aug-99	 Removed printf from dp83843_duplex()			     JWB
-  |  19-Jul-00	 Ported to esd cpci405					     sr
-  |  23-Dec-03	 Ported from miiphy.c to 440GX Travis Sawyer		     TBS
-  |		 <travis.sawyer@sandburst.com>
-  |
-  +-----------------------------------------------------------------------------*/
-
-#include <common.h>
-#include <miiphy.h>
-#include "IxOsal.h"
-#include "IxEthAcc.h"
-#include "IxEthAcc_p.h"
-#include "IxEthAccMac_p.h"
-#include "IxEthAccMii_p.h"
-
-/***********************************************************/
-/* Dump out to the screen PHY regs			   */
-/***********************************************************/
-
-void miiphy_dump (char *devname, unsigned char addr)
-{
-	unsigned long i;
-	unsigned short data;
-
-
-	for (i = 0; i < 0x1A; i++) {
-		if (miiphy_read (devname, addr, i, &data)) {
-			printf ("read error for reg %lx\n", i);
-			return;
-		}
-		printf ("Phy reg %lx ==> %4x\n", i, data);
-
-		/* jump to the next set of regs */
-		if (i == 0x07)
-			i = 0x0f;
-
-	}			/* end for loop */
-}				/* end dump */
-
-
-/***********************************************************/
-/* (Re)start autonegotiation				   */
-/***********************************************************/
-int phy_setup_aneg (char *devname, unsigned char addr)
-{
-	unsigned short ctl, adv;
-
-	/* Setup standard advertise */
-	miiphy_read (devname, addr, MII_ADVERTISE, &adv);
-	adv |= (LPA_LPACK | LPA_RFAULT | LPA_100BASE4 |
-		LPA_100FULL | LPA_100HALF | LPA_10FULL |
-		LPA_10HALF);
-	miiphy_write (devname, addr, MII_ADVERTISE, adv);
-
-	/* Start/Restart aneg */
-	miiphy_read (devname, addr, MII_BMCR, &ctl);
-	ctl |= (BMCR_ANENABLE | BMCR_ANRESTART);
-	miiphy_write (devname, addr, MII_BMCR, ctl);
-
-	return 0;
-}
-
-
-int npe_miiphy_read (const char *devname, unsigned char addr,
-		     unsigned char reg, unsigned short *value)
-{
-	u16 val;
-
-	ixEthAccMiiReadRtn(addr, reg, &val);
-	*value = val;
-
-	return 0;
-}				/* phy_read */
-
-
-int npe_miiphy_write (const char *devname, unsigned char addr,
-		      unsigned char reg, unsigned short value)
-{
-	ixEthAccMiiWriteRtn(addr, reg, value);
-	return 0;
-}				/* phy_write */
diff --git a/drivers/net/npe/npe.c b/drivers/net/npe/npe.c
deleted file mode 100644
index 00b381ec4a..0000000000
--- a/drivers/net/npe/npe.c
+++ /dev/null
@@ -1,680 +0,0 @@
-/*
- * (C) Copyright 2005-2006
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#if 0
-#define DEBUG		/* define for debug output */
-#endif
-
-#include <config.h>
-#include <common.h>
-#include <net.h>
-#include <miiphy.h>
-#include <malloc.h>
-#include <asm/processor.h>
-#include <asm/arch-ixp/ixp425.h>
-
-#include <IxOsal.h>
-#include <IxEthAcc.h>
-#include <IxEthDB.h>
-#include <IxNpeDl.h>
-#include <IxQMgr.h>
-#include <IxNpeMh.h>
-#include <ix_ossl.h>
-#include <IxFeatureCtrl.h>
-
-#include <npe.h>
-
-static IxQMgrDispatcherFuncPtr qDispatcherFunc = NULL;
-static int npe_exists[NPE_NUM_PORTS];
-static int npe_used[NPE_NUM_PORTS];
-
-/* A little extra so we can align to cacheline. */
-static u8 npe_alloc_pool[NPE_MEM_POOL_SIZE + CONFIG_SYS_CACHELINE_SIZE - 1];
-static u8 *npe_alloc_end;
-static u8 *npe_alloc_free;
-
-static void *npe_alloc(int size)
-{
-	static int count = 0;
-	void *p = NULL;
-
-	size = (size + (CONFIG_SYS_CACHELINE_SIZE-1)) & ~(CONFIG_SYS_CACHELINE_SIZE-1);
-	count++;
-
-	if ((npe_alloc_free + size) < npe_alloc_end) {
-		p = npe_alloc_free;
-		npe_alloc_free += size;
-	} else {
-		printf("npe_alloc: failed (count=%d, size=%d)!\n", count, size);
-	}
-	return p;
-}
-
-/* Not interrupt safe! */
-static void mbuf_enqueue(IX_OSAL_MBUF **q, IX_OSAL_MBUF *new)
-{
-	IX_OSAL_MBUF *m = *q;
-
-	IX_OSAL_MBUF_NEXT_PKT_IN_CHAIN_PTR(new) = NULL;
-
-	if (m) {
-		while(IX_OSAL_MBUF_NEXT_PKT_IN_CHAIN_PTR(m))
-			m = IX_OSAL_MBUF_NEXT_PKT_IN_CHAIN_PTR(m);
-		IX_OSAL_MBUF_NEXT_PKT_IN_CHAIN_PTR(m) = new;
-	} else
-		*q = new;
-}
-
-/* Not interrupt safe! */
-static IX_OSAL_MBUF *mbuf_dequeue(IX_OSAL_MBUF **q)
-{
-	IX_OSAL_MBUF *m = *q;
-	if (m)
-		*q = IX_OSAL_MBUF_NEXT_PKT_IN_CHAIN_PTR(m);
-	return m;
-}
-
-static void reset_tx_mbufs(struct npe* p_npe)
-{
-	IX_OSAL_MBUF *m;
-	int i;
-
-	p_npe->txQHead = NULL;
-
-	for (i = 0; i < CONFIG_DEVS_ETH_INTEL_NPE_MAX_TX_DESCRIPTORS; i++) {
-		m = &p_npe->tx_mbufs[i];
-
-		memset(m, 0, sizeof(*m));
-
-		IX_OSAL_MBUF_MDATA(m) = (void *)&p_npe->tx_pkts[i * NPE_PKT_SIZE];
-		IX_OSAL_MBUF_MLEN(m) = IX_OSAL_MBUF_PKT_LEN(m) = NPE_PKT_SIZE;
-		mbuf_enqueue(&p_npe->txQHead, m);
-	}
-}
-
-static void reset_rx_mbufs(struct npe* p_npe)
-{
-	IX_OSAL_MBUF *m;
-	int i;
-
-	p_npe->rxQHead = NULL;
-
-	HAL_DCACHE_INVALIDATE(p_npe->rx_pkts, NPE_PKT_SIZE *
-			      CONFIG_DEVS_ETH_INTEL_NPE_MAX_RX_DESCRIPTORS);
-
-	for (i = 0; i < CONFIG_DEVS_ETH_INTEL_NPE_MAX_RX_DESCRIPTORS; i++) {
-		m = &p_npe->rx_mbufs[i];
-
-		memset(m, 0, sizeof(*m));
-
-		IX_OSAL_MBUF_MDATA(m) = (void *)&p_npe->rx_pkts[i * NPE_PKT_SIZE];
-		IX_OSAL_MBUF_MLEN(m) = IX_OSAL_MBUF_PKT_LEN(m) = NPE_PKT_SIZE;
-
-		if(ixEthAccPortRxFreeReplenish(p_npe->eth_id, m) != IX_SUCCESS) {
-			printf("ixEthAccPortRxFreeReplenish failed for port %d\n", p_npe->eth_id);
-			break;
-		}
-	}
-}
-
-static void init_rx_mbufs(struct npe* p_npe)
-{
-	p_npe->rxQHead = NULL;
-
-	p_npe->rx_pkts = npe_alloc(NPE_PKT_SIZE *
-				   CONFIG_DEVS_ETH_INTEL_NPE_MAX_RX_DESCRIPTORS);
-	if (p_npe->rx_pkts == NULL) {
-		printf("alloc of packets failed.\n");
-		return;
-	}
-
-	p_npe->rx_mbufs = (IX_OSAL_MBUF *)
-		npe_alloc(sizeof(IX_OSAL_MBUF) *
-			  CONFIG_DEVS_ETH_INTEL_NPE_MAX_RX_DESCRIPTORS);
-	if (p_npe->rx_mbufs == NULL) {
-		printf("alloc of mbufs failed.\n");
-		return;
-	}
-
-	reset_rx_mbufs(p_npe);
-}
-
-static void init_tx_mbufs(struct npe* p_npe)
-{
-	p_npe->tx_pkts = npe_alloc(NPE_PKT_SIZE *
-				   CONFIG_DEVS_ETH_INTEL_NPE_MAX_TX_DESCRIPTORS);
-	if (p_npe->tx_pkts == NULL) {
-		printf("alloc of packets failed.\n");
-		return;
-	}
-
-	p_npe->tx_mbufs = (IX_OSAL_MBUF *)
-		npe_alloc(sizeof(IX_OSAL_MBUF) *
-			  CONFIG_DEVS_ETH_INTEL_NPE_MAX_TX_DESCRIPTORS);
-	if (p_npe->tx_mbufs == NULL) {
-		printf("alloc of mbufs failed.\n");
-		return;
-	}
-
-	reset_tx_mbufs(p_npe);
-}
-
-/* Convert IX_ETH_PORT_n to IX_NPEMH_NPEID_NPEx */
-static int __eth_to_npe(int eth_id)
-{
-	switch(eth_id) {
-	case IX_ETH_PORT_1:
-		return IX_NPEMH_NPEID_NPEB;
-
-	case IX_ETH_PORT_2:
-		return IX_NPEMH_NPEID_NPEC;
-
-	case IX_ETH_PORT_3:
-		return IX_NPEMH_NPEID_NPEA;
-	}
-	return 0;
-}
-
-/* Poll the CSR machinery. */
-static void npe_poll(int eth_id)
-{
-	if (qDispatcherFunc != NULL) {
-		ixNpeMhMessagesReceive(__eth_to_npe(eth_id));
-		(*qDispatcherFunc)(IX_QMGR_QUELOW_GROUP);
-	}
-}
-
-/* ethAcc RX callback */
-static void npe_rx_callback(u32 cbTag, IX_OSAL_MBUF *m, IxEthAccPortId portid)
-{
-	struct npe* p_npe = (struct npe *)cbTag;
-
-	if (IX_OSAL_MBUF_MLEN(m) > 0) {
-		mbuf_enqueue(&p_npe->rxQHead, m);
-
-		if (p_npe->rx_write == ((p_npe->rx_read-1) & (PKTBUFSRX-1))) {
-			debug("Rx overflow: rx_write=%d rx_read=%d\n",
-			      p_npe->rx_write, p_npe->rx_read);
-		} else {
-			debug("Received message #%d (len=%d)\n", p_npe->rx_write,
-			      IX_OSAL_MBUF_MLEN(m));
-			memcpy((void *)NetRxPackets[p_npe->rx_write], IX_OSAL_MBUF_MDATA(m),
-			       IX_OSAL_MBUF_MLEN(m));
-			p_npe->rx_len[p_npe->rx_write] = IX_OSAL_MBUF_MLEN(m);
-			p_npe->rx_write++;
-			if (p_npe->rx_write == PKTBUFSRX)
-				p_npe->rx_write = 0;
-
-#ifdef CONFIG_PRINT_RX_FRAMES
-			{
-				u8 *ptr = IX_OSAL_MBUF_MDATA(m);
-				int i;
-
-				for (i=0; i<60; i++) {
-					debug("%02x ", *ptr++);
-				}
-				debug("\n");
-			}
-#endif
-		}
-
-		m = mbuf_dequeue(&p_npe->rxQHead);
-	} else {
-		debug("Received frame with length 0!!!\n");
-		m = mbuf_dequeue(&p_npe->rxQHead);
-	}
-
-	/* Now return mbuf to NPE */
-	IX_OSAL_MBUF_MLEN(m) = IX_OSAL_MBUF_PKT_LEN(m) = NPE_PKT_SIZE;
-	IX_OSAL_MBUF_NEXT_BUFFER_IN_PKT_PTR(m) = NULL;
-	IX_OSAL_MBUF_FLAGS(m) = 0;
-
-	if(ixEthAccPortRxFreeReplenish(p_npe->eth_id, m) != IX_SUCCESS) {
-		debug("npe_rx_callback: Error returning mbuf.\n");
-	}
-}
-
-/* ethAcc TX callback */
-static void npe_tx_callback(u32 cbTag, IX_OSAL_MBUF *m)
-{
-	struct npe* p_npe = (struct npe *)cbTag;
-
-	debug("%s\n", __FUNCTION__);
-
-	IX_OSAL_MBUF_MLEN(m) = IX_OSAL_MBUF_PKT_LEN(m) = NPE_PKT_SIZE;
-	IX_OSAL_MBUF_NEXT_BUFFER_IN_PKT_PTR(m) = NULL;
-	IX_OSAL_MBUF_FLAGS(m) = 0;
-
-	mbuf_enqueue(&p_npe->txQHead, m);
-}
-
-
-static int npe_set_mac_address(struct eth_device *dev)
-{
-	struct npe *p_npe = (struct npe *)dev->priv;
-	IxEthAccMacAddr npeMac;
-
-	debug("%s\n", __FUNCTION__);
-
-	/* Set MAC address */
-	memcpy(npeMac.macAddress, dev->enetaddr, 6);
-
-	if (ixEthAccPortUnicastMacAddressSet(p_npe->eth_id, &npeMac) != IX_ETH_ACC_SUCCESS) {
-		printf("Error setting unicast address! %02x:%02x:%02x:%02x:%02x:%02x\n",
-		       npeMac.macAddress[0], npeMac.macAddress[1],
-		       npeMac.macAddress[2], npeMac.macAddress[3],
-		       npeMac.macAddress[4], npeMac.macAddress[5]);
-		return 0;
-	}
-
-	return 1;
-}
-
-/* Boot-time CSR library initialization. */
-static int npe_csr_load(void)
-{
-	int i;
-
-	if (ixQMgrInit() != IX_SUCCESS) {
-		debug("Error initialising queue manager!\n");
-		return 0;
-	}
-
-	ixQMgrDispatcherLoopGet(&qDispatcherFunc);
-
-	if(ixNpeMhInitialize(IX_NPEMH_NPEINTERRUPTS_YES) != IX_SUCCESS) {
-		printf("Error initialising NPE Message handler!\n");
-		return 0;
-	}
-
-	if (npe_used[IX_ETH_PORT_1] && npe_exists[IX_ETH_PORT_1] &&
-	    ixNpeDlNpeInitAndStart(IX_NPEDL_NPEIMAGE_NPEB_ETH_LEARN_FILTER_SPAN_FIREWALL_VLAN_QOS)
-	    != IX_SUCCESS) {
-		printf("Error downloading firmware to NPE-B!\n");
-		return 0;
-	}
-
-	if (npe_used[IX_ETH_PORT_2] && npe_exists[IX_ETH_PORT_2] &&
-	    ixNpeDlNpeInitAndStart(IX_NPEDL_NPEIMAGE_NPEC_ETH_LEARN_FILTER_SPAN_FIREWALL_VLAN_QOS)
-	    != IX_SUCCESS) {
-		printf("Error downloading firmware to NPE-C!\n");
-		return 0;
-	}
-
-	/* don't need this for U-Boot */
-	ixFeatureCtrlSwConfigurationWrite(IX_FEATURECTRL_ETH_LEARNING, false);
-
-	if (ixEthAccInit() != IX_ETH_ACC_SUCCESS) {
-		printf("Error initialising Ethernet access driver!\n");
-		return 0;
-	}
-
-	for (i = 0; i < IX_ETH_ACC_NUMBER_OF_PORTS; i++) {
-		if (!npe_used[i] || !npe_exists[i])
-			continue;
-		if (ixEthAccPortInit(i) != IX_ETH_ACC_SUCCESS) {
-			printf("Error initialising Ethernet port%d!\n", i);
-		}
-		if (ixEthAccTxSchedulingDisciplineSet(i, FIFO_NO_PRIORITY) != IX_ETH_ACC_SUCCESS) {
-			printf("Error setting scheduling discipline for port %d.\n", i);
-		}
-		if (ixEthAccPortRxFrameAppendFCSDisable(i) != IX_ETH_ACC_SUCCESS) {
-			printf("Error disabling RX FCS for port %d.\n", i);
-		}
-		if (ixEthAccPortTxFrameAppendFCSEnable(i) != IX_ETH_ACC_SUCCESS) {
-			printf("Error enabling TX FCS for port %d.\n", i);
-		}
-	}
-
-	return 1;
-}
-
-static int npe_init(struct eth_device *dev, bd_t * bis)
-{
-	struct npe *p_npe = (struct npe *)dev->priv;
-	int i;
-	u16 reg_short;
-	int speed;
-	int duplex;
-
-	debug("%s: 1\n", __FUNCTION__);
-
-#ifdef CONFIG_MII_NPE0_FIXEDLINK
-	if (0 == p_npe->eth_id) {
-		speed = CONFIG_MII_NPE0_SPEED;
-		duplex = CONFIG_MII_NPE0_FULLDUPLEX ? FULL : HALF;
-	} else
-#endif
-#ifdef CONFIG_MII_NPE1_FIXEDLINK
-	if (1 == p_npe->eth_id) {
-		speed = CONFIG_MII_NPE1_SPEED;
-		duplex = CONFIG_MII_NPE1_FULLDUPLEX ? FULL : HALF;
-	} else
-#endif
-	{
-		miiphy_read(dev->name, p_npe->phy_no, MII_BMSR, &reg_short);
-
-		/*
-		 * Wait if PHY is capable of autonegotiation and
-		 * autonegotiation is not complete
-		 */
-		if ((reg_short & BMSR_ANEGCAPABLE) &&
-		    !(reg_short & BMSR_ANEGCOMPLETE)) {
-			puts("Waiting for PHY auto negotiation to complete");
-			i = 0;
-			while (!(reg_short & BMSR_ANEGCOMPLETE)) {
-				/*
-				 * Timeout reached ?
-				 */
-				if (i > PHY_AUTONEGOTIATE_TIMEOUT) {
-					puts(" TIMEOUT !\n");
-					break;
-				}
-
-				if ((i++ % 1000) == 0) {
-					putc('.');
-					miiphy_read(dev->name, p_npe->phy_no,
-						     MII_BMSR, &reg_short);
-				}
-				udelay(1000);	/* 1 ms */
-			}
-			puts(" done\n");
-			/* another 500 ms (results in faster booting) */
-			udelay(500000);
-		}
-		speed = miiphy_speed(dev->name, p_npe->phy_no);
-		duplex = miiphy_duplex(dev->name, p_npe->phy_no);
-	}
-
-	if (p_npe->print_speed) {
-		p_npe->print_speed = 0;
-		printf ("ENET Speed is %d Mbps - %s duplex connection\n",
-			(int) speed, (duplex == HALF) ? "HALF" : "FULL");
-	}
-
-	npe_alloc_end = npe_alloc_pool + sizeof(npe_alloc_pool);
-	npe_alloc_free = (u8 *)(((unsigned)npe_alloc_pool +
-				 CONFIG_SYS_CACHELINE_SIZE - 1) & ~(CONFIG_SYS_CACHELINE_SIZE - 1));
-
-	/* initialize mbuf pool */
-	init_rx_mbufs(p_npe);
-	init_tx_mbufs(p_npe);
-
-	if (ixEthAccPortRxCallbackRegister(p_npe->eth_id, npe_rx_callback,
-					   (u32)p_npe) != IX_ETH_ACC_SUCCESS) {
-		printf("can't register RX callback!\n");
-		return -1;
-	}
-
-	if (ixEthAccPortTxDoneCallbackRegister(p_npe->eth_id, npe_tx_callback,
-					       (u32)p_npe) != IX_ETH_ACC_SUCCESS) {
-		printf("can't register TX callback!\n");
-		return -1;
-	}
-
-	npe_set_mac_address(dev);
-
-	if (ixEthAccPortEnable(p_npe->eth_id) != IX_ETH_ACC_SUCCESS) {
-		printf("can't enable port!\n");
-		return -1;
-	}
-
-	p_npe->active = 1;
-
-	return 0;
-}
-
-#if 0 /* test-only: probably have to deal with it when booting linux (for a clean state) */
-/* Uninitialize CSR library. */
-static void npe_csr_unload(void)
-{
-	ixEthAccUnload();
-	ixEthDBUnload();
-	ixNpeMhUnload();
-	ixQMgrUnload();
-}
-
-/* callback which is used by ethAcc to recover RX buffers when stopping */
-static void npe_rx_stop_callback(u32 cbTag, IX_OSAL_MBUF *m, IxEthAccPortId portid)
-{
-	debug("%s\n", __FUNCTION__);
-}
-
-/* callback which is used by ethAcc to recover TX buffers when stopping */
-static void npe_tx_stop_callback(u32 cbTag, IX_OSAL_MBUF *m)
-{
-	debug("%s\n", __FUNCTION__);
-}
-#endif
-
-static void npe_halt(struct eth_device *dev)
-{
-	struct npe *p_npe = (struct npe *)dev->priv;
-	int i;
-
-	debug("%s\n", __FUNCTION__);
-
-	/* Delay to give time for recovery of mbufs */
-	for (i = 0; i < 100; i++) {
-		npe_poll(p_npe->eth_id);
-		udelay(100);
-	}
-
-#if 0 /* test-only: probably have to deal with it when booting linux (for a clean state) */
-	if (ixEthAccPortRxCallbackRegister(p_npe->eth_id, npe_rx_stop_callback,
-					   (u32)p_npe) != IX_ETH_ACC_SUCCESS) {
-		debug("Error registering rx callback!\n");
-	}
-
-	if (ixEthAccPortTxDoneCallbackRegister(p_npe->eth_id, npe_tx_stop_callback,
-					       (u32)p_npe) != IX_ETH_ACC_SUCCESS) {
-		debug("Error registering tx callback!\n");
-	}
-
-	if (ixEthAccPortDisable(p_npe->eth_id) != IX_ETH_ACC_SUCCESS) {
-		debug("npe_stop: Error disabling NPEB!\n");
-	}
-
-	/* Delay to give time for recovery of mbufs */
-	for (i = 0; i < 100; i++) {
-		npe_poll(p_npe->eth_id);
-		udelay(10000);
-	}
-
-	/*
-	 * For U-Boot only, we are probably launching Linux or other OS that
-	 * needs a clean slate for its NPE library.
-	 */
-#if 0 /* test-only */
-	for (i = 0; i < IX_ETH_ACC_NUMBER_OF_PORTS; i++) {
-		if (npe_used[i] && npe_exists[i])
-			if (ixNpeDlNpeStopAndReset(__eth_to_npe(i)) != IX_SUCCESS)
-				printf("Failed to stop and reset NPE B.\n");
-	}
-#endif
-
-#endif
-	p_npe->active = 0;
-}
-
-
-static int npe_send(struct eth_device *dev, void *packet, int len)
-{
-	struct npe *p_npe = (struct npe *)dev->priv;
-	u8 *dest;
-	int err;
-	IX_OSAL_MBUF *m;
-
-	debug("%s\n", __FUNCTION__);
-	m = mbuf_dequeue(&p_npe->txQHead);
-	dest = IX_OSAL_MBUF_MDATA(m);
-	IX_OSAL_MBUF_PKT_LEN(m) = IX_OSAL_MBUF_MLEN(m) = len;
-	IX_OSAL_MBUF_NEXT_PKT_IN_CHAIN_PTR(m) = NULL;
-
-	memcpy(dest, (char *)packet, len);
-
-	if ((err = ixEthAccPortTxFrameSubmit(p_npe->eth_id, m, IX_ETH_ACC_TX_DEFAULT_PRIORITY))
-	    != IX_ETH_ACC_SUCCESS) {
-		printf("npe_send: Can't submit frame. err[%d]\n", err);
-		mbuf_enqueue(&p_npe->txQHead, m);
-		return 0;
-	}
-
-#ifdef DEBUG_PRINT_TX_FRAMES
-	{
-		u8 *ptr = IX_OSAL_MBUF_MDATA(m);
-		int i;
-
-		for (i=0; i<IX_OSAL_MBUF_MLEN(m); i++) {
-			printf("%02x ", *ptr++);
-		}
-		printf(" (tx-len=%d)\n", IX_OSAL_MBUF_MLEN(m));
-	}
-#endif
-
-	npe_poll(p_npe->eth_id);
-
-	return len;
-}
-
-static int npe_rx(struct eth_device *dev)
-{
-	struct npe *p_npe = (struct npe *)dev->priv;
-
-	debug("%s\n", __FUNCTION__);
-	npe_poll(p_npe->eth_id);
-
-	debug("%s: rx_write=%d rx_read=%d\n", __FUNCTION__, p_npe->rx_write, p_npe->rx_read);
-	while (p_npe->rx_write != p_npe->rx_read) {
-		debug("Reading message #%d\n", p_npe->rx_read);
-		NetReceive(NetRxPackets[p_npe->rx_read], p_npe->rx_len[p_npe->rx_read]);
-		p_npe->rx_read++;
-		if (p_npe->rx_read == PKTBUFSRX)
-			p_npe->rx_read = 0;
-	}
-
-	return 0;
-}
-
-int npe_initialize(bd_t * bis)
-{
-	static int virgin = 0;
-	struct eth_device *dev;
-	int eth_num = 0;
-	struct npe *p_npe = NULL;
-	uchar enetaddr[6];
-
-	for (eth_num = 0; eth_num < CONFIG_SYS_NPE_NUMS; eth_num++) {
-
-		/* See if we can actually bring up the interface, otherwise, skip it */
-#ifdef CONFIG_HAS_ETH1
-		if (eth_num == 1) {
-			if (!eth_getenv_enetaddr("eth1addr", enetaddr))
-				continue;
-		} else
-#endif
-			if (!eth_getenv_enetaddr("ethaddr", enetaddr))
-				continue;
-
-		/* Allocate device structure */
-		dev = (struct eth_device *)malloc(sizeof(*dev));
-		if (dev == NULL) {
-			printf ("%s: Cannot allocate eth_device %d\n", __FUNCTION__, eth_num);
-			return -1;
-		}
-		memset(dev, 0, sizeof(*dev));
-
-		/* Allocate our private use data */
-		p_npe = (struct npe *)malloc(sizeof(struct npe));
-		if (p_npe == NULL) {
-			printf("%s: Cannot allocate private hw data for eth_device %d",
-			       __FUNCTION__, eth_num);
-			free(dev);
-			return -1;
-		}
-		memset(p_npe, 0, sizeof(struct npe));
-
-		p_npe->eth_id = eth_num;
-		memcpy(dev->enetaddr, enetaddr, 6);
-#ifdef CONFIG_HAS_ETH1
-		if (eth_num == 1)
-			p_npe->phy_no = CONFIG_PHY1_ADDR;
-		else
-#endif
-			p_npe->phy_no = CONFIG_PHY_ADDR;
-
-		sprintf(dev->name, "NPE%d", eth_num);
-		dev->priv = (void *)p_npe;
-		dev->init = npe_init;
-		dev->halt = npe_halt;
-		dev->send = npe_send;
-		dev->recv = npe_rx;
-
-		p_npe->print_speed = 1;
-
-		if (0 == virgin) {
-			virgin = 1;
-
-			if (ixFeatureCtrlDeviceRead() == IX_FEATURE_CTRL_DEVICE_TYPE_IXP42X) {
-				switch (ixFeatureCtrlProductIdRead() & IX_FEATURE_CTRL_SILICON_STEPPING_MASK) {
-				case IX_FEATURE_CTRL_SILICON_TYPE_B0:
-				default: /* newer than B0 */
-					/*
-					 * If it is B0 or newer Silicon, we
-					 * only enable port when its
-					 * corresponding Eth Coprocessor is
-					 * available.
-					 */
-					if (ixFeatureCtrlComponentCheck(IX_FEATURECTRL_ETH0) ==
-					    IX_FEATURE_CTRL_COMPONENT_ENABLED)
-						npe_exists[IX_ETH_PORT_1] = true;
-
-					if (ixFeatureCtrlComponentCheck(IX_FEATURECTRL_ETH1) ==
-					    IX_FEATURE_CTRL_COMPONENT_ENABLED)
-						npe_exists[IX_ETH_PORT_2] = true;
-					break;
-				case IX_FEATURE_CTRL_SILICON_TYPE_A0:
-					/*
-					 * If it is A0 Silicon, we enable both as both Eth Coprocessors
-					 * are available.
-					 */
-					npe_exists[IX_ETH_PORT_1] = true;
-					npe_exists[IX_ETH_PORT_2] = true;
-					break;
-				}
-			} else if (ixFeatureCtrlDeviceRead() == IX_FEATURE_CTRL_DEVICE_TYPE_IXP46X) {
-				if (ixFeatureCtrlComponentCheck(IX_FEATURECTRL_ETH0) ==
-				    IX_FEATURE_CTRL_COMPONENT_ENABLED)
-					npe_exists[IX_ETH_PORT_1] = true;
-
-				if (ixFeatureCtrlComponentCheck(IX_FEATURECTRL_ETH1) ==
-				    IX_FEATURE_CTRL_COMPONENT_ENABLED)
-					npe_exists[IX_ETH_PORT_2] = true;
-			}
-
-			npe_used[IX_ETH_PORT_1] = 1;
-			npe_used[IX_ETH_PORT_2] = 1;
-
-			npe_alloc_end = npe_alloc_pool + sizeof(npe_alloc_pool);
-			npe_alloc_free = (u8 *)(((unsigned)npe_alloc_pool +
-						 CONFIG_SYS_CACHELINE_SIZE - 1)
-						& ~(CONFIG_SYS_CACHELINE_SIZE - 1));
-
-			if (!npe_csr_load())
-				return 0;
-		}
-
-		eth_register(dev);
-
-#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
-		miiphy_register(dev->name, npe_miiphy_read, npe_miiphy_write);
-#endif
-
-	}			/* end for each supported device */
-
-	return 1;
-}
diff --git a/drivers/net/pcnet.c b/drivers/net/pcnet.c
index 283cb48b4e..71a3110712 100644
--- a/drivers/net/pcnet.c
+++ b/drivers/net/pcnet.c
@@ -89,39 +89,39 @@ static pcnet_priv_t *lp;
 #define PCNET_RESET		0x14
 #define PCNET_BDP		0x16
 
-static u16 pcnet_read_csr (struct eth_device *dev, int index)
+static u16 pcnet_read_csr(struct eth_device *dev, int index)
 {
-	outw (index, dev->iobase + PCNET_RAP);
-	return inw (dev->iobase + PCNET_RDP);
+	outw(index, dev->iobase + PCNET_RAP);
+	return inw(dev->iobase + PCNET_RDP);
 }
 
-static void pcnet_write_csr (struct eth_device *dev, int index, u16 val)
+static void pcnet_write_csr(struct eth_device *dev, int index, u16 val)
 {
-	outw (index, dev->iobase + PCNET_RAP);
-	outw (val, dev->iobase + PCNET_RDP);
+	outw(index, dev->iobase + PCNET_RAP);
+	outw(val, dev->iobase + PCNET_RDP);
 }
 
-static u16 pcnet_read_bcr (struct eth_device *dev, int index)
+static u16 pcnet_read_bcr(struct eth_device *dev, int index)
 {
-	outw (index, dev->iobase + PCNET_RAP);
-	return inw (dev->iobase + PCNET_BDP);
+	outw(index, dev->iobase + PCNET_RAP);
+	return inw(dev->iobase + PCNET_BDP);
 }
 
-static void pcnet_write_bcr (struct eth_device *dev, int index, u16 val)
+static void pcnet_write_bcr(struct eth_device *dev, int index, u16 val)
 {
-	outw (index, dev->iobase + PCNET_RAP);
-	outw (val, dev->iobase + PCNET_BDP);
+	outw(index, dev->iobase + PCNET_RAP);
+	outw(val, dev->iobase + PCNET_BDP);
 }
 
-static void pcnet_reset (struct eth_device *dev)
+static void pcnet_reset(struct eth_device *dev)
 {
-	inw (dev->iobase + PCNET_RESET);
+	inw(dev->iobase + PCNET_RESET);
 }
 
-static int pcnet_check (struct eth_device *dev)
+static int pcnet_check(struct eth_device *dev)
 {
-	outw (88, dev->iobase + PCNET_RAP);
-	return (inw (dev->iobase + PCNET_RAP) == 88);
+	outw(88, dev->iobase + PCNET_RAP);
+	return inw(dev->iobase + PCNET_RAP) == 88;
 }
 
 static int pcnet_init (struct eth_device *dev, bd_t * bis);
@@ -139,63 +139,64 @@ static struct pci_device_id supported[] = {
 };
 
 
-int pcnet_initialize (bd_t * bis)
+int pcnet_initialize(bd_t *bis)
 {
 	pci_dev_t devbusfn;
 	struct eth_device *dev;
 	u16 command, status;
 	int dev_nr = 0;
 
-	PCNET_DEBUG1 ("\npcnet_initialize...\n");
+	PCNET_DEBUG1("\npcnet_initialize...\n");
 
 	for (dev_nr = 0;; dev_nr++) {
 
 		/*
 		 * Find the PCnet PCI device(s).
 		 */
-		if ((devbusfn = pci_find_devices (supported, dev_nr)) < 0) {
+		devbusfn = pci_find_devices(supported, dev_nr);
+		if (devbusfn < 0)
 			break;
-		}
 
 		/*
 		 * Allocate and pre-fill the device structure.
 		 */
-		dev = (struct eth_device *) malloc (sizeof *dev);
+		dev = (struct eth_device *)malloc(sizeof(*dev));
 		if (!dev) {
 			printf("pcnet: Can not allocate memory\n");
 			break;
 		}
 		memset(dev, 0, sizeof(*dev));
-		dev->priv = (void *) devbusfn;
-		sprintf (dev->name, "pcnet#%d", dev_nr);
+		dev->priv = (void *)devbusfn;
+		sprintf(dev->name, "pcnet#%d", dev_nr);
 
 		/*
 		 * Setup the PCI device.
 		 */
-		pci_read_config_dword (devbusfn, PCI_BASE_ADDRESS_0,
-				       (unsigned int *) &dev->iobase);
-		dev->iobase=pci_io_to_phys (devbusfn, dev->iobase);
+		pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_0,
+				      (unsigned int *)&dev->iobase);
+		dev->iobase = pci_io_to_phys(devbusfn, dev->iobase);
 		dev->iobase &= ~0xf;
 
-		PCNET_DEBUG1 ("%s: devbusfn=0x%x iobase=0x%x: ",
-			      dev->name, devbusfn, dev->iobase);
+		PCNET_DEBUG1("%s: devbusfn=0x%x iobase=0x%x: ",
+			     dev->name, devbusfn, dev->iobase);
 
 		command = PCI_COMMAND_IO | PCI_COMMAND_MASTER;
-		pci_write_config_word (devbusfn, PCI_COMMAND, command);
-		pci_read_config_word (devbusfn, PCI_COMMAND, &status);
+		pci_write_config_word(devbusfn, PCI_COMMAND, command);
+		pci_read_config_word(devbusfn, PCI_COMMAND, &status);
 		if ((status & command) != command) {
-			printf ("%s: Couldn't enable IO access or Bus Mastering\n", dev->name);
-			free (dev);
+			printf("%s: Couldn't enable IO access or Bus Mastering\n",
+			       dev->name);
+			free(dev);
 			continue;
 		}
 
-		pci_write_config_byte (devbusfn, PCI_LATENCY_TIMER, 0x40);
+		pci_write_config_byte(devbusfn, PCI_LATENCY_TIMER, 0x40);
 
 		/*
 		 * Probe the PCnet chip.
 		 */
-		if (pcnet_probe (dev, bis, dev_nr) < 0) {
-			free (dev);
+		if (pcnet_probe(dev, bis, dev_nr) < 0) {
+			free(dev);
 			continue;
 		}
 
@@ -207,15 +208,15 @@ int pcnet_initialize (bd_t * bis)
 		dev->send = pcnet_send;
 		dev->recv = pcnet_recv;
 
-		eth_register (dev);
+		eth_register(dev);
 	}
 
-	udelay (10 * 1000);
+	udelay(10 * 1000);
 
 	return dev_nr;
 }
 
-static int pcnet_probe (struct eth_device *dev, bd_t * bis, int dev_nr)
+static int pcnet_probe(struct eth_device *dev, bd_t *bis, int dev_nr)
 {
 	int chip_version;
 	char *chipname;
@@ -225,17 +226,17 @@ static int pcnet_probe (struct eth_device *dev, bd_t * bis, int dev_nr)
 #endif
 
 	/* Reset the PCnet controller */
-	pcnet_reset (dev);
+	pcnet_reset(dev);
 
 	/* Check if register access is working */
-	if (pcnet_read_csr (dev, 0) != 4 || !pcnet_check (dev)) {
-		printf ("%s: CSR register access check failed\n", dev->name);
+	if (pcnet_read_csr(dev, 0) != 4 || !pcnet_check(dev)) {
+		printf("%s: CSR register access check failed\n", dev->name);
 		return -1;
 	}
 
 	/* Identify the chip */
 	chip_version =
-		pcnet_read_csr (dev, 88) | (pcnet_read_csr (dev, 89) << 16);
+		pcnet_read_csr(dev, 88) | (pcnet_read_csr(dev, 89) << 16);
 	if ((chip_version & 0xfff) != 0x003)
 		return -1;
 	chip_version = (chip_version >> 12) & 0xffff;
@@ -254,12 +255,12 @@ static int pcnet_probe (struct eth_device *dev, bd_t * bis, int dev_nr)
 		break;
 #endif
 	default:
-		printf ("%s: PCnet version %#x not supported\n",
-			dev->name, chip_version);
+		printf("%s: PCnet version %#x not supported\n",
+		       dev->name, chip_version);
 		return -1;
 	}
 
-	PCNET_DEBUG1 ("AMD %s\n", chipname);
+	PCNET_DEBUG1("AMD %s\n", chipname);
 
 #ifdef PCNET_HAS_PROM
 	/*
@@ -270,7 +271,7 @@ static int pcnet_probe (struct eth_device *dev, bd_t * bis, int dev_nr)
 	for (i = 0; i < 3; i++) {
 		unsigned int val;
 
-		val = pcnet_read_csr (dev, i + 12) & 0x0ffff;
+		val = pcnet_read_csr(dev, i + 12) & 0x0ffff;
 		/* There may be endianness issues here. */
 		dev->enetaddr[2 * i] = val & 0x0ff;
 		dev->enetaddr[2 * i + 1] = (val >> 8) & 0x0ff;
@@ -280,35 +281,40 @@ static int pcnet_probe (struct eth_device *dev, bd_t * bis, int dev_nr)
 	return 0;
 }
 
-static int pcnet_init (struct eth_device *dev, bd_t * bis)
+static int pcnet_init(struct eth_device *dev, bd_t *bis)
 {
 	int i, val;
 	u32 addr;
 
-	PCNET_DEBUG1 ("%s: pcnet_init...\n", dev->name);
+	PCNET_DEBUG1("%s: pcnet_init...\n", dev->name);
 
 	/* Switch pcnet to 32bit mode */
-	pcnet_write_bcr (dev, 20, 2);
-
-#ifdef CONFIG_PN62
-	/* Setup LED registers */
-	val = pcnet_read_bcr (dev, 2) | 0x1000;
-	pcnet_write_bcr (dev, 2, val);	/* enable LEDPE */
-	pcnet_write_bcr (dev, 4, 0x5080);	/* 100MBit */
-	pcnet_write_bcr (dev, 5, 0x40c0);	/* LNKSE */
-	pcnet_write_bcr (dev, 6, 0x4090);	/* TX Activity */
-	pcnet_write_bcr (dev, 7, 0x4084);	/* RX Activity */
-#endif
+	pcnet_write_bcr(dev, 20, 2);
 
 	/* Set/reset autoselect bit */
-	val = pcnet_read_bcr (dev, 2) & ~2;
+	val = pcnet_read_bcr(dev, 2) & ~2;
 	val |= 2;
-	pcnet_write_bcr (dev, 2, val);
+	pcnet_write_bcr(dev, 2, val);
 
 	/* Enable auto negotiate, setup, disable fd */
-	val = pcnet_read_bcr (dev, 32) & ~0x98;
+	val = pcnet_read_bcr(dev, 32) & ~0x98;
 	val |= 0x20;
-	pcnet_write_bcr (dev, 32, val);
+	pcnet_write_bcr(dev, 32, val);
+
+	/*
+	 * Enable NOUFLO on supported controllers, with the transmit
+	 * start point set to the full packet. This will cause entire
+	 * packets to be buffered by the ethernet controller before
+	 * transmission, eliminating underflows which are common on
+	 * slower devices. Controllers which do not support NOUFLO will
+	 * simply be left with a larger transmit FIFO threshold.
+	 */
+	val = pcnet_read_bcr(dev, 18);
+	val |= 1 << 11;
+	pcnet_write_bcr(dev, 18, val);
+	val = pcnet_read_csr(dev, 80);
+	val |= 0x3 << 10;
+	pcnet_write_csr(dev, 80, val);
 
 	/*
 	 * We only maintain one structure because the drivers will never
@@ -316,12 +322,12 @@ static int pcnet_init (struct eth_device *dev, bd_t * bis)
 	 * must be aligned on 16-byte boundaries.
 	 */
 	if (lp == NULL) {
-		addr = (u32) malloc (sizeof (pcnet_priv_t) + 0x10);
+		addr = (u32)malloc(sizeof(pcnet_priv_t) + 0x10);
 		addr = (addr + 0xf) & ~0xf;
-		lp = (pcnet_priv_t *) addr;
+		lp = (pcnet_priv_t *)addr;
 	}
 
-	lp->init_block.mode = cpu_to_le16 (0x0000);
+	lp->init_block.mode = cpu_to_le16(0x0000);
 	lp->init_block.filter[0] = 0x00000000;
 	lp->init_block.filter[1] = 0x00000000;
 
@@ -330,9 +336,9 @@ static int pcnet_init (struct eth_device *dev, bd_t * bis)
 	 */
 	lp->cur_rx = 0;
 	for (i = 0; i < RX_RING_SIZE; i++) {
-		lp->rx_ring[i].base = PCI_TO_MEM_LE (dev, lp->rx_buf[i]);
-		lp->rx_ring[i].buf_length = cpu_to_le16 (-PKT_BUF_SZ);
-		lp->rx_ring[i].status = cpu_to_le16 (0x8000);
+		lp->rx_ring[i].base = PCI_TO_MEM_LE(dev, lp->rx_buf[i]);
+		lp->rx_ring[i].buf_length = cpu_to_le16(-PKT_BUF_SZ);
+		lp->rx_ring[i].status = cpu_to_le16(0x8000);
 		PCNET_DEBUG1
 			("Rx%d: base=0x%x buf_length=0x%hx status=0x%hx\n", i,
 			 lp->rx_ring[i].base, lp->rx_ring[i].buf_length,
@@ -352,48 +358,49 @@ static int pcnet_init (struct eth_device *dev, bd_t * bis)
 	/*
 	 * Setup Init Block.
 	 */
-	PCNET_DEBUG1 ("Init block at 0x%p: MAC", &lp->init_block);
+	PCNET_DEBUG1("Init block at 0x%p: MAC", &lp->init_block);
 
 	for (i = 0; i < 6; i++) {
 		lp->init_block.phys_addr[i] = dev->enetaddr[i];
-		PCNET_DEBUG1 (" %02x", lp->init_block.phys_addr[i]);
+		PCNET_DEBUG1(" %02x", lp->init_block.phys_addr[i]);
 	}
 
-	lp->init_block.tlen_rlen = cpu_to_le16 (TX_RING_LEN_BITS |
-						RX_RING_LEN_BITS);
-	lp->init_block.rx_ring = PCI_TO_MEM_LE (dev, lp->rx_ring);
-	lp->init_block.tx_ring = PCI_TO_MEM_LE (dev, lp->tx_ring);
+	lp->init_block.tlen_rlen = cpu_to_le16(TX_RING_LEN_BITS |
+					       RX_RING_LEN_BITS);
+	lp->init_block.rx_ring = PCI_TO_MEM_LE(dev, lp->rx_ring);
+	lp->init_block.tx_ring = PCI_TO_MEM_LE(dev, lp->tx_ring);
+	flush_dcache_range((unsigned long)lp, (unsigned long)&lp->rx_buf);
 
-	PCNET_DEBUG1 ("\ntlen_rlen=0x%x rx_ring=0x%x tx_ring=0x%x\n",
-		      lp->init_block.tlen_rlen,
-		      lp->init_block.rx_ring, lp->init_block.tx_ring);
+	PCNET_DEBUG1("\ntlen_rlen=0x%x rx_ring=0x%x tx_ring=0x%x\n",
+		     lp->init_block.tlen_rlen,
+		     lp->init_block.rx_ring, lp->init_block.tx_ring);
 
 	/*
 	 * Tell the controller where the Init Block is located.
 	 */
-	addr = PCI_TO_MEM (dev, &lp->init_block);
-	pcnet_write_csr (dev, 1, addr & 0xffff);
-	pcnet_write_csr (dev, 2, (addr >> 16) & 0xffff);
+	addr = PCI_TO_MEM(dev, &lp->init_block);
+	pcnet_write_csr(dev, 1, addr & 0xffff);
+	pcnet_write_csr(dev, 2, (addr >> 16) & 0xffff);
 
-	pcnet_write_csr (dev, 4, 0x0915);
-	pcnet_write_csr (dev, 0, 0x0001);	/* start */
+	pcnet_write_csr(dev, 4, 0x0915);
+	pcnet_write_csr(dev, 0, 0x0001);	/* start */
 
 	/* Wait for Init Done bit */
 	for (i = 10000; i > 0; i--) {
-		if (pcnet_read_csr (dev, 0) & 0x0100)
+		if (pcnet_read_csr(dev, 0) & 0x0100)
 			break;
-		udelay (10);
+		udelay(10);
 	}
 	if (i <= 0) {
-		printf ("%s: TIMEOUT: controller init failed\n", dev->name);
-		pcnet_reset (dev);
+		printf("%s: TIMEOUT: controller init failed\n", dev->name);
+		pcnet_reset(dev);
 		return -1;
 	}
 
 	/*
 	 * Finally start network controller operation.
 	 */
-	pcnet_write_csr (dev, 0, 0x0002);
+	pcnet_write_csr(dev, 0, 0x0002);
 
 	return 0;
 }
@@ -403,20 +410,25 @@ static int pcnet_send(struct eth_device *dev, void *packet, int pkt_len)
 	int i, status;
 	struct pcnet_tx_head *entry = &lp->tx_ring[lp->cur_tx];
 
-	PCNET_DEBUG2 ("Tx%d: %d bytes from 0x%p ", lp->cur_tx, pkt_len,
-		      packet);
+	PCNET_DEBUG2("Tx%d: %d bytes from 0x%p ", lp->cur_tx, pkt_len,
+		     packet);
+
+	flush_dcache_range((unsigned long)packet,
+			   (unsigned long)packet + pkt_len);
 
 	/* Wait for completion by testing the OWN bit */
 	for (i = 1000; i > 0; i--) {
-		status = le16_to_cpu (entry->status);
+		invalidate_dcache_range((unsigned long)entry,
+					(unsigned long)entry + sizeof(*entry));
+		status = le16_to_cpu(entry->status);
 		if ((status & 0x8000) == 0)
 			break;
-		udelay (100);
-		PCNET_DEBUG2 (".");
+		udelay(100);
+		PCNET_DEBUG2(".");
 	}
 	if (i <= 0) {
-		printf ("%s: TIMEOUT: Tx%d failed (status = 0x%x)\n",
-			dev->name, lp->cur_tx, status);
+		printf("%s: TIMEOUT: Tx%d failed (status = 0x%x)\n",
+		       dev->name, lp->cur_tx, status);
 		pkt_len = 0;
 		goto failure;
 	}
@@ -426,19 +438,21 @@ static int pcnet_send(struct eth_device *dev, void *packet, int pkt_len)
 	 * set the status with the "ownership" bits last.
 	 */
 	status = 0x8300;
-	entry->length = le16_to_cpu (-pkt_len);
+	entry->length = cpu_to_le16(-pkt_len);
 	entry->misc = 0x00000000;
-	entry->base = PCI_TO_MEM_LE (dev, packet);
-	entry->status = le16_to_cpu (status);
+	entry->base = PCI_TO_MEM_LE(dev, packet);
+	entry->status = cpu_to_le16(status);
+	flush_dcache_range((unsigned long)entry,
+			   (unsigned long)entry + sizeof(*entry));
 
 	/* Trigger an immediate send poll. */
-	pcnet_write_csr (dev, 0, 0x0008);
+	pcnet_write_csr(dev, 0, 0x0008);
 
       failure:
 	if (++lp->cur_tx >= TX_RING_SIZE)
 		lp->cur_tx = 0;
 
-	PCNET_DEBUG2 ("done\n");
+	PCNET_DEBUG2("done\n");
 	return pkt_len;
 }
 
@@ -450,43 +464,49 @@ static int pcnet_recv (struct eth_device *dev)
 
 	while (1) {
 		entry = &lp->rx_ring[lp->cur_rx];
+		invalidate_dcache_range((unsigned long)entry,
+					(unsigned long)entry + sizeof(*entry));
 		/*
 		 * If we own the next entry, it's a new packet. Send it up.
 		 */
-		if (((status = le16_to_cpu (entry->status)) & 0x8000) != 0) {
+		status = le16_to_cpu(entry->status);
+		if ((status & 0x8000) != 0)
 			break;
-		}
 		status >>= 8;
 
 		if (status != 0x03) {	/* There was an error. */
-
-			printf ("%s: Rx%d", dev->name, lp->cur_rx);
-			PCNET_DEBUG1 (" (status=0x%x)", status);
+			printf("%s: Rx%d", dev->name, lp->cur_rx);
+			PCNET_DEBUG1(" (status=0x%x)", status);
 			if (status & 0x20)
-				printf (" Frame");
+				printf(" Frame");
 			if (status & 0x10)
-				printf (" Overflow");
+				printf(" Overflow");
 			if (status & 0x08)
-				printf (" CRC");
+				printf(" CRC");
 			if (status & 0x04)
-				printf (" Fifo");
-			printf (" Error\n");
-			entry->status &= le16_to_cpu (0x03ff);
+				printf(" Fifo");
+			printf(" Error\n");
+			entry->status &= le16_to_cpu(0x03ff);
 
 		} else {
-
-			pkt_len =
-				(le32_to_cpu (entry->msg_length) & 0xfff) - 4;
+			pkt_len = (le32_to_cpu(entry->msg_length) & 0xfff) - 4;
 			if (pkt_len < 60) {
-				printf ("%s: Rx%d: invalid packet length %d\n", dev->name, lp->cur_rx, pkt_len);
+				printf("%s: Rx%d: invalid packet length %d\n",
+				       dev->name, lp->cur_rx, pkt_len);
 			} else {
-				NetReceive (lp->rx_buf[lp->cur_rx], pkt_len);
-				PCNET_DEBUG2 ("Rx%d: %d bytes from 0x%p\n",
-					      lp->cur_rx, pkt_len,
-					      lp->rx_buf[lp->cur_rx]);
+				invalidate_dcache_range(
+					(unsigned long)lp->rx_buf[lp->cur_rx],
+					(unsigned long)lp->rx_buf[lp->cur_rx] +
+					pkt_len);
+				NetReceive(lp->rx_buf[lp->cur_rx], pkt_len);
+				PCNET_DEBUG2("Rx%d: %d bytes from 0x%p\n",
+					     lp->cur_rx, pkt_len,
+					     lp->rx_buf[lp->cur_rx]);
 			}
 		}
-		entry->status |= cpu_to_le16 (0x8000);
+		entry->status |= cpu_to_le16(0x8000);
+		flush_dcache_range((unsigned long)entry,
+				   (unsigned long)entry + sizeof(*entry));
 
 		if (++lp->cur_rx >= RX_RING_SIZE)
 			lp->cur_rx = 0;
@@ -494,22 +514,21 @@ static int pcnet_recv (struct eth_device *dev)
 	return pkt_len;
 }
 
-static void pcnet_halt (struct eth_device *dev)
+static void pcnet_halt(struct eth_device *dev)
 {
 	int i;
 
-	PCNET_DEBUG1 ("%s: pcnet_halt...\n", dev->name);
+	PCNET_DEBUG1("%s: pcnet_halt...\n", dev->name);
 
 	/* Reset the PCnet controller */
-	pcnet_reset (dev);
+	pcnet_reset(dev);
 
 	/* Wait for Stop bit */
 	for (i = 1000; i > 0; i--) {
-		if (pcnet_read_csr (dev, 0) & 0x4)
+		if (pcnet_read_csr(dev, 0) & 0x4)
 			break;
-		udelay (10);
-	}
-	if (i <= 0) {
-		printf ("%s: TIMEOUT: controller reset failed\n", dev->name);
+		udelay(10);
 	}
+	if (i <= 0)
+		printf("%s: TIMEOUT: controller reset failed\n", dev->name);
 }
diff --git a/drivers/net/phy/Makefile b/drivers/net/phy/Makefile
index fe762e9de3..dbf7bf7058 100644
--- a/drivers/net/phy/Makefile
+++ b/drivers/net/phy/Makefile
@@ -5,44 +5,22 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	:= $(obj)libphy.o
-
-COBJS-$(CONFIG_BITBANGMII) += miiphybb.o
-COBJS-$(CONFIG_MV88E61XX_SWITCH) += mv88e61xx.o
-COBJS-$(CONFIG_MV88E6352_SWITCH) += mv88e6352.o
-
-COBJS-$(CONFIG_PHYLIB) += phy.o
-COBJS-$(CONFIG_PHYLIB_10G) += generic_10g.o
-COBJS-$(CONFIG_PHY_ATHEROS) += atheros.o
-COBJS-$(CONFIG_PHY_BROADCOM) += broadcom.o
-COBJS-$(CONFIG_PHY_DAVICOM) += davicom.o
-COBJS-$(CONFIG_PHY_ET1011C) += et1011c.o
-COBJS-$(CONFIG_PHY_ICPLUS) += icplus.o
-COBJS-$(CONFIG_PHY_LXT) += lxt.o
-COBJS-$(CONFIG_PHY_MARVELL) += marvell.o
-COBJS-$(CONFIG_PHY_MICREL) += micrel.o
-COBJS-$(CONFIG_PHY_NATSEMI) += natsemi.o
-COBJS-$(CONFIG_PHY_REALTEK) += realtek.o
-COBJS-$(CONFIG_PHY_SMSC) += smsc.o
-COBJS-$(CONFIG_PHY_TERANETICS) += teranetics.o
-COBJS-$(CONFIG_PHY_VITESSE) += vitesse.o
-
-COBJS	:= $(COBJS-y)
-SRCS	:= $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-
-all:	$(LIB)
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-$(CONFIG_BITBANGMII) += miiphybb.o
+obj-$(CONFIG_MV88E61XX_SWITCH) += mv88e61xx.o
+obj-$(CONFIG_MV88E6352_SWITCH) += mv88e6352.o
+
+obj-$(CONFIG_PHYLIB) += phy.o
+obj-$(CONFIG_PHYLIB_10G) += generic_10g.o
+obj-$(CONFIG_PHY_ATHEROS) += atheros.o
+obj-$(CONFIG_PHY_BROADCOM) += broadcom.o
+obj-$(CONFIG_PHY_DAVICOM) += davicom.o
+obj-$(CONFIG_PHY_ET1011C) += et1011c.o
+obj-$(CONFIG_PHY_ICPLUS) += icplus.o
+obj-$(CONFIG_PHY_LXT) += lxt.o
+obj-$(CONFIG_PHY_MARVELL) += marvell.o
+obj-$(CONFIG_PHY_MICREL) += micrel.o
+obj-$(CONFIG_PHY_NATSEMI) += natsemi.o
+obj-$(CONFIG_PHY_REALTEK) += realtek.o
+obj-$(CONFIG_PHY_SMSC) += smsc.o
+obj-$(CONFIG_PHY_TERANETICS) += teranetics.o
+obj-$(CONFIG_PHY_VITESSE) += vitesse.o
diff --git a/drivers/net/phy/atheros.c b/drivers/net/phy/atheros.c
index 0f2dfd6126..b80980d552 100644
--- a/drivers/net/phy/atheros.c
+++ b/drivers/net/phy/atheros.c
@@ -13,6 +13,7 @@ static int ar8021_config(struct phy_device *phydev)
 	phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05);
 	phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x3D47);
 
+	phydev->supported = phydev->drv->features;
 	return 0;
 }
 
@@ -40,7 +41,7 @@ static int ar8035_config(struct phy_device *phydev)
 static struct phy_driver AR8021_driver =  {
 	.name = "AR8021",
 	.uid = 0x4dd040,
-	.mask = 0xfffff0,
+	.mask = 0x4ffff0,
 	.features = PHY_GBIT_FEATURES,
 	.config = ar8021_config,
 	.startup = genphy_startup,
@@ -48,9 +49,9 @@ static struct phy_driver AR8021_driver =  {
 };
 
 static struct phy_driver AR8031_driver =  {
-	.name = "AR8031",
+	.name = "AR8031/AR8033",
 	.uid = 0x4dd074,
-	.mask = 0xfffff0,
+	.mask = 0xffffffef,
 	.features = PHY_GBIT_FEATURES,
 	.config = genphy_config,
 	.startup = genphy_startup,
@@ -60,7 +61,7 @@ static struct phy_driver AR8031_driver =  {
 static struct phy_driver AR8035_driver =  {
 	.name = "AR8035",
 	.uid = 0x4dd072,
-	.mask = 0x4fffff,
+	.mask = 0xffffffef,
 	.features = PHY_GBIT_FEATURES,
 	.config = ar8035_config,
 	.startup = genphy_startup,
diff --git a/drivers/net/phy/micrel.c b/drivers/net/phy/micrel.c
index a7450f8326..5d7e3be52e 100644
--- a/drivers/net/phy/micrel.c
+++ b/drivers/net/phy/micrel.c
@@ -100,6 +100,19 @@ int ksz9021_phy_extended_read(struct phy_device *phydev, int regnum)
 	return phy_read(phydev, MDIO_DEVAD_NONE, MII_KSZ9021_EXTENDED_DATAR);
 }
 
+
+static int ksz9021_phy_extread(struct phy_device *phydev, int addr, int devaddr,
+			      int regnum)
+{
+	return ksz9021_phy_extended_read(phydev, regnum);
+}
+
+static int ksz9021_phy_extwrite(struct phy_device *phydev, int addr,
+			       int devaddr, int regnum, u16 val)
+{
+	return ksz9021_phy_extended_write(phydev, regnum, val);
+}
+
 /* Micrel ksz9021 */
 static int ksz9021_config(struct phy_device *phydev)
 {
@@ -131,6 +144,8 @@ static struct phy_driver ksz9021_driver = {
 	.config = &ksz9021_config,
 	.startup = &ksz90xx_startup,
 	.shutdown = &genphy_shutdown,
+	.writeext = &ksz9021_phy_extwrite,
+	.readext = &ksz9021_phy_extread,
 };
 #endif
 
@@ -171,14 +186,31 @@ int ksz9031_phy_extended_read(struct phy_device *phydev, int devaddr,
 	return phy_read(phydev, MDIO_DEVAD_NONE, MII_KSZ9031_MMD_REG_DATA);
 }
 
+static int ksz9031_phy_extread(struct phy_device *phydev, int addr, int devaddr,
+			       int regnum)
+{
+	return ksz9031_phy_extended_read(phydev, devaddr, regnum,
+					 MII_KSZ9031_MOD_DATA_NO_POST_INC);
+};
+
+static int ksz9031_phy_extwrite(struct phy_device *phydev, int addr,
+				int devaddr, int regnum, u16 val)
+{
+	return ksz9031_phy_extended_write(phydev, devaddr, regnum,
+					 MII_KSZ9031_MOD_DATA_POST_INC_RW, val);
+};
+
+
 static struct phy_driver ksz9031_driver = {
 	.name = "Micrel ksz9031",
 	.uid  = 0x221620,
-	.mask = 0xfffffe,
+	.mask = 0xfffff0,
 	.features = PHY_GBIT_FEATURES,
 	.config   = &genphy_config,
 	.startup  = &ksz90xx_startup,
 	.shutdown = &genphy_shutdown,
+	.writeext = &ksz9031_phy_extwrite,
+	.readext = &ksz9031_phy_extread,
 };
 
 int phy_micrel_init(void)
diff --git a/drivers/net/phy/phy.c b/drivers/net/phy/phy.c
index 62925bb286..c691fbbbc6 100644
--- a/drivers/net/phy/phy.c
+++ b/drivers/net/phy/phy.c
@@ -275,13 +275,14 @@ int genphy_parse_link(struct phy_device *phydev)
 	int mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMSR);
 
 	/* We're using autonegotiation */
-	if (mii_reg & BMSR_ANEGCAPABLE) {
+	if (phydev->supported & SUPPORTED_Autoneg) {
 		u32 lpa = 0;
 		int gblpa = 0;
 		u32 estatus = 0;
 
 		/* Check for gigabit capability */
-		if (mii_reg & BMSR_ERCAP) {
+		if (phydev->supported & (SUPPORTED_1000baseT_Full |
+					SUPPORTED_1000baseT_Half)) {
 			/* We want a list of states supported by
 			 * both PHYs in the link
 			 */
diff --git a/drivers/net/phy/realtek.c b/drivers/net/phy/realtek.c
index ddbbc35e27..a3ace68526 100644
--- a/drivers/net/phy/realtek.c
+++ b/drivers/net/phy/realtek.c
@@ -102,7 +102,7 @@ static int rtl8211x_startup(struct phy_device *phydev)
 static struct phy_driver RTL8211B_driver = {
 	.name = "RealTek RTL8211B",
 	.uid = 0x1cc910,
-	.mask = 0xfffff0,
+	.mask = 0xffffff,
 	.features = PHY_GBIT_FEATURES,
 	.config = &rtl8211x_config,
 	.startup = &rtl8211x_startup,
@@ -113,7 +113,7 @@ static struct phy_driver RTL8211B_driver = {
 static struct phy_driver RTL8211E_driver = {
 	.name = "RealTek RTL8211E",
 	.uid = 0x1cc915,
-	.mask = 0xfffff0,
+	.mask = 0xffffff,
 	.features = PHY_GBIT_FEATURES,
 	.config = &rtl8211x_config,
 	.startup = &rtl8211x_startup,
@@ -124,7 +124,7 @@ static struct phy_driver RTL8211E_driver = {
 static struct phy_driver RTL8211DN_driver = {
 	.name = "RealTek RTL8211DN",
 	.uid = 0x1cc914,
-	.mask = 0xfffff0,
+	.mask = 0xffffff,
 	.features = PHY_GBIT_FEATURES,
 	.config = &rtl8211x_config,
 	.startup = &rtl8211x_startup,
diff --git a/drivers/net/phy/smsc.c b/drivers/net/phy/smsc.c
index 60ed92d203..bfd9815abf 100644
--- a/drivers/net/phy/smsc.c
+++ b/drivers/net/phy/smsc.c
@@ -12,6 +12,7 @@
  */
 #include <miiphy.h>
 
+/* This code does not check the partner abilities. */
 static int smsc_parse_status(struct phy_device *phydev)
 {
 	int mii_reg;
@@ -64,7 +65,7 @@ static struct phy_driver lan8710_driver = {
 	.mask = 0xffff0,
 	.features = PHY_BASIC_FEATURES,
 	.config = &genphy_config_aneg,
-	.startup = &smsc_startup,
+	.startup = &genphy_startup,
 	.shutdown = &genphy_shutdown,
 };
 
diff --git a/drivers/net/phy/vitesse.c b/drivers/net/phy/vitesse.c
index 5cf103e5a1..c555979661 100644
--- a/drivers/net/phy/vitesse.c
+++ b/drivers/net/phy/vitesse.c
@@ -49,6 +49,15 @@
 #define MIIM_VSC8574_18G_QSGMII		0x80e0
 #define MIIM_VSC8574_18G_CMDSTAT	0x8000
 
+/* Vitesse VSC8514 control register */
+#define MIIM_VSC8514_GENERAL18		0x12
+#define MIIM_VSC8514_GENERAL19		0x13
+#define MIIM_VSC8514_GENERAL23		0x17
+
+/* Vitesse VSC8514 gerenal purpose register 18 */
+#define MIIM_VSC8514_18G_QSGMII		0x80e0
+#define MIIM_VSC8514_18G_CMDSTAT	0x8000
+
 /* CIS8201 */
 static int vitesse_config(struct phy_device *phydev)
 {
@@ -148,7 +157,7 @@ static int vsc8601_config(struct phy_device *phydev)
 static int vsc8574_config(struct phy_device *phydev)
 {
 	u32 val;
-	/* configure regiser 19G for MAC */
+	/* configure register 19G for MAC */
 	phy_write(phydev, MDIO_DEVAD_NONE, PHY_EXT_PAGE_ACCESS,
 		  PHY_EXT_PAGE_ACCESS_GENERAL);
 
@@ -188,6 +197,53 @@ static int vsc8574_config(struct phy_device *phydev)
 	return 0;
 }
 
+static int vsc8514_config(struct phy_device *phydev)
+{
+	u32 val;
+	int timeout = 1000000;
+
+	/* configure register to access 19G */
+	phy_write(phydev, MDIO_DEVAD_NONE, PHY_EXT_PAGE_ACCESS,
+		  PHY_EXT_PAGE_ACCESS_GENERAL);
+
+	val = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_VSC8514_GENERAL19);
+	if (phydev->interface == PHY_INTERFACE_MODE_QSGMII) {
+		/* set bit 15:14 to '01' for QSGMII mode */
+		val = (val & 0x3fff) | (1 << 14);
+		phy_write(phydev, MDIO_DEVAD_NONE,
+			  MIIM_VSC8514_GENERAL19, val);
+		/* Enable 4 ports MAC QSGMII */
+		phy_write(phydev, MDIO_DEVAD_NONE, MIIM_VSC8514_GENERAL18,
+			  MIIM_VSC8514_18G_QSGMII);
+	} else {
+		/*TODO Add SGMII functionality once spec sheet
+		 * for VSC8514 defines complete functionality
+		 */
+	}
+
+	val = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_VSC8514_GENERAL18);
+	/* When bit 15 is cleared the command has completed */
+	while ((val & MIIM_VSC8514_18G_CMDSTAT) && timeout--)
+		val = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_VSC8514_GENERAL18);
+
+	if (0 == timeout) {
+		printf("PHY 8514 config failed\n");
+		return -1;
+	}
+
+	phy_write(phydev, MDIO_DEVAD_NONE, PHY_EXT_PAGE_ACCESS, 0);
+
+	/* configure register to access 23 */
+	val = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_VSC8514_GENERAL23);
+	/* set bits 10:8 to '000' */
+	val = (val & 0xf8ff);
+	phy_write(phydev, MDIO_DEVAD_NONE, MIIM_VSC8514_GENERAL23, val);
+
+	genphy_config_aneg(phydev);
+
+	return 0;
+}
+
 static struct phy_driver VSC8211_driver = {
 	.name	= "Vitesse VSC8211",
 	.uid	= 0xfc4b0,
@@ -238,6 +294,16 @@ static struct phy_driver VSC8574_driver = {
 	.shutdown = &genphy_shutdown,
 };
 
+static struct phy_driver VSC8514_driver = {
+	.name = "Vitesse VSC8514",
+	.uid = 0x70570,
+	.mask = 0xffff0,
+	.features = PHY_GBIT_FEATURES,
+	.config = &vsc8514_config,
+	.startup = &vitesse_startup,
+	.shutdown = &genphy_shutdown,
+};
+
 static struct phy_driver VSC8601_driver = {
 	.name = "Vitesse VSC8601",
 	.uid = 0x70420,
@@ -298,6 +364,7 @@ int phy_vitesse_init(void)
 	phy_register(&VSC8211_driver);
 	phy_register(&VSC8221_driver);
 	phy_register(&VSC8574_driver);
+	phy_register(&VSC8514_driver);
 	phy_register(&VSC8662_driver);
 	phy_register(&cis8201_driver);
 	phy_register(&cis8204_driver);
diff --git a/drivers/net/rtl8139.c b/drivers/net/rtl8139.c
index 4186699ff9..208ce5ccc4 100644
--- a/drivers/net/rtl8139.c
+++ b/drivers/net/rtl8139.c
@@ -188,7 +188,7 @@ static int rtl_transmit(struct eth_device *dev, void *packet, int length);
 static int rtl_poll(struct eth_device *dev);
 static void rtl_disable(struct eth_device *dev);
 #ifdef CONFIG_MCAST_TFTP/*  This driver already accepts all b/mcast */
-static int rtl_bcast_addr (struct eth_device *dev, u8 bcast_mac, u8 set)
+static int rtl_bcast_addr(struct eth_device *dev, const u8 *bcast_mac, u8 set)
 {
 	return (0);
 }
diff --git a/drivers/net/rtl8169.c b/drivers/net/rtl8169.c
index 13fa9c02fe..d040ab171b 100644
--- a/drivers/net/rtl8169.c
+++ b/drivers/net/rtl8169.c
@@ -246,6 +246,8 @@ static struct {
 	{"RTL-8169sc/8110sc",	0x18, 0xff7e1880,},
 	{"RTL-8168b/8111sb",	0x30, 0xff7e1880,},
 	{"RTL-8168b/8111sb",	0x38, 0xff7e1880,},
+	{"RTL-8168d/8111d",	0x28, 0xff7e1880,},
+	{"RTL-8168evl/8111evl",	0x2e, 0xff7e1880,},
 	{"RTL-8101e",		0x34, 0xff7e1880,},
 	{"RTL-8100e",		0x32, 0xff7e1880,},
 };
@@ -314,6 +316,7 @@ static const unsigned int rtl8169_rx_config =
 
 static struct pci_device_id supported[] = {
 	{PCI_VENDOR_ID_REALTEK, 0x8167},
+	{PCI_VENDOR_ID_REALTEK, 0x8168},
 	{PCI_VENDOR_ID_REALTEK, 0x8169},
 	{}
 };
@@ -394,6 +397,50 @@ match:
 	return 0;
 }
 
+/*
+ * Cache maintenance functions. These are simple wrappers around the more
+ * general purpose flush_cache() and invalidate_dcache_range() functions.
+ */
+
+static void rtl_inval_rx_desc(struct RxDesc *desc)
+{
+	unsigned long start = (unsigned long)desc & ~(ARCH_DMA_MINALIGN - 1);
+	unsigned long end = ALIGN(start + sizeof(*desc), ARCH_DMA_MINALIGN);
+
+	invalidate_dcache_range(start, end);
+}
+
+static void rtl_flush_rx_desc(struct RxDesc *desc)
+{
+	flush_cache((unsigned long)desc, sizeof(*desc));
+}
+
+static void rtl_inval_tx_desc(struct TxDesc *desc)
+{
+	unsigned long start = (unsigned long)desc & ~(ARCH_DMA_MINALIGN - 1);
+	unsigned long end = ALIGN(start + sizeof(*desc), ARCH_DMA_MINALIGN);
+
+	invalidate_dcache_range(start, end);
+}
+
+static void rtl_flush_tx_desc(struct TxDesc *desc)
+{
+	flush_cache((unsigned long)desc, sizeof(*desc));
+}
+
+static void rtl_inval_buffer(void *buf, size_t size)
+{
+	unsigned long start = (unsigned long)buf & ~(ARCH_DMA_MINALIGN - 1);
+	unsigned long end = ALIGN(start + size, ARCH_DMA_MINALIGN);
+
+	invalidate_dcache_range(start, end);
+}
+
+static void rtl_flush_buffer(void *buf, size_t size)
+{
+	flush_cache((unsigned long)buf, size);
+}
+
 /**************************************************************************
 RECV - Receive a frame
 ***************************************************************************/
@@ -411,14 +458,16 @@ static int rtl_recv(struct eth_device *dev)
 	ioaddr = dev->iobase;
 
 	cur_rx = tpc->cur_rx;
-	flush_cache((unsigned long)&tpc->RxDescArray[cur_rx],
-			sizeof(struct RxDesc));
+
+	rtl_inval_rx_desc(&tpc->RxDescArray[cur_rx]);
+
 	if ((le32_to_cpu(tpc->RxDescArray[cur_rx].status) & OWNbit) == 0) {
 		if (!(le32_to_cpu(tpc->RxDescArray[cur_rx].status) & RxRES)) {
 			unsigned char rxdata[RX_BUF_LEN];
 			length = (int) (le32_to_cpu(tpc->RxDescArray[cur_rx].
 						status) & 0x00001FFF) - 4;
 
+			rtl_inval_buffer(tpc->RxBufferRing[cur_rx], length);
 			memcpy(rxdata, tpc->RxBufferRing[cur_rx], length);
 			NetReceive(rxdata, length);
 
@@ -430,8 +479,7 @@ static int rtl_recv(struct eth_device *dev)
 					cpu_to_le32(OWNbit + RX_BUF_SIZE);
 			tpc->RxDescArray[cur_rx].buf_addr =
 				cpu_to_le32(bus_to_phys(tpc->RxBufferRing[cur_rx]));
-			flush_cache((unsigned long)tpc->RxBufferRing[cur_rx],
-					RX_BUF_SIZE);
+			rtl_flush_rx_desc(&tpc->RxDescArray[cur_rx]);
 		} else {
 			puts("Error Rx");
 		}
@@ -473,7 +521,7 @@ static int rtl_send(struct eth_device *dev, void *packet, int length)
 	/* point to the current txb incase multiple tx_rings are used */
 	ptxb = tpc->Tx_skbuff[entry * MAX_ETH_FRAME_SIZE];
 	memcpy(ptxb, (char *)packet, (int)length);
-	flush_cache((unsigned long)ptxb, length);
+	rtl_flush_buffer(ptxb, length);
 
 	while (len < ETH_ZLEN)
 		ptxb[len++] = '\0';
@@ -489,20 +537,20 @@ static int rtl_send(struct eth_device *dev, void *packet, int length)
 			cpu_to_le32((OWNbit | EORbit | FSbit | LSbit) |
 				    ((len > ETH_ZLEN) ? len : ETH_ZLEN));
 	}
+	rtl_flush_tx_desc(&tpc->TxDescArray[entry]);
 	RTL_W8(TxPoll, 0x40);	/* set polling bit */
 
 	tpc->cur_tx++;
 	to = currticks() + TX_TIMEOUT;
 	do {
-		flush_cache((unsigned long)&tpc->TxDescArray[entry],
-				sizeof(struct TxDesc));
+		rtl_inval_tx_desc(&tpc->TxDescArray[entry]);
 	} while ((le32_to_cpu(tpc->TxDescArray[entry].status) & OWNbit)
 				&& (currticks() < to));	/* wait */
 
 	if (currticks() >= to) {
 #ifdef DEBUG_RTL8169_TX
-		puts ("tx timeout/error\n");
-		printf ("%s elapsed time : %d\n", __FUNCTION__, currticks()-stime);
+		puts("tx timeout/error\n");
+		printf("%s elapsed time : %lu\n", __func__, currticks()-stime);
 #endif
 		ret = 0;
 	} else {
@@ -604,7 +652,7 @@ static void rtl8169_hw_start(struct eth_device *dev)
 	RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
 
 #ifdef DEBUG_RTL8169
-	printf ("%s elapsed time : %d\n", __FUNCTION__, currticks()-stime);
+	printf("%s elapsed time : %lu\n", __func__, currticks()-stime);
 #endif
 }
 
@@ -638,11 +686,11 @@ static void rtl8169_init_ring(struct eth_device *dev)
 		tpc->RxBufferRing[i] = &rxb[i * RX_BUF_SIZE];
 		tpc->RxDescArray[i].buf_addr =
 			cpu_to_le32(bus_to_phys(tpc->RxBufferRing[i]));
-		flush_cache((unsigned long)tpc->RxBufferRing[i], RX_BUF_SIZE);
+		rtl_flush_rx_desc(&tpc->RxDescArray[i]);
 	}
 
 #ifdef DEBUG_RTL8169
-	printf ("%s elapsed time : %d\n", __FUNCTION__, currticks()-stime);
+	printf("%s elapsed time : %lu\n", __func__, currticks()-stime);
 #endif
 }
 
@@ -683,7 +731,7 @@ static int rtl_reset(struct eth_device *dev, bd_t *bis)
 	txb[5] = dev->enetaddr[5];
 
 #ifdef DEBUG_RTL8169
-	printf ("%s elapsed time : %d\n", __FUNCTION__, currticks()-stime);
+	printf("%s elapsed time : %lu\n", __func__, currticks()-stime);
 #endif
 	return 0;
 }
@@ -869,11 +917,25 @@ int rtl8169_initialize(bd_t *bis)
 	int idx=0;
 
 	while(1){
+		unsigned int region;
+		u16 device;
+
 		/* Find RTL8169 */
 		if ((devno = pci_find_devices(supported, idx++)) < 0)
 			break;
 
-		pci_read_config_dword(devno, PCI_BASE_ADDRESS_1, &iobase);
+		pci_read_config_word(devno, PCI_DEVICE_ID, &device);
+		switch (device) {
+		case 0x8168:
+			region = 2;
+			break;
+
+		default:
+			region = 1;
+			break;
+		}
+
+		pci_read_config_dword(devno, PCI_BASE_ADDRESS_0 + (region * 4), &iobase);
 		iobase &= ~0xf;
 
 		debug ("rtl8169: REALTEK RTL8169 @0x%x\n", iobase);
diff --git a/drivers/net/sh_eth.c b/drivers/net/sh_eth.c
index d5a83e0bf5..5e132f2b53 100644
--- a/drivers/net/sh_eth.c
+++ b/drivers/net/sh_eth.c
@@ -4,6 +4,7 @@
  * Copyright (C) 2008, 2011 Renesas Solutions Corp.
  * Copyright (c) 2008, 2011 Nobuhiro Iwamatsu
  * Copyright (c) 2007 Carlos Munoz <carlos@kenati.com>
+ * Copyright (C) 2013  Renesas Electronics Corporation
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */
@@ -25,13 +26,31 @@
 #ifndef CONFIG_SH_ETHER_PHY_ADDR
 # error "Please define CONFIG_SH_ETHER_PHY_ADDR"
 #endif
-#ifdef CONFIG_SH_ETHER_CACHE_WRITEBACK
-#define flush_cache_wback(addr, len)	\
-			dcache_wback_range((u32)addr, (u32)(addr + len - 1))
+
+#if defined(CONFIG_SH_ETHER_CACHE_WRITEBACK) && !defined(CONFIG_SYS_DCACHE_OFF)
+#define flush_cache_wback(addr, len)    \
+		flush_dcache_range((u32)addr, (u32)(addr + len - 1))
 #else
 #define flush_cache_wback(...)
 #endif
 
+#if defined(CONFIG_SH_ETHER_CACHE_INVALIDATE) && defined(CONFIG_ARM)
+#define invalidate_cache(addr, len)		\
+	{	\
+		u32 line_size = CONFIG_SH_ETHER_ALIGNE_SIZE;	\
+		u32 start, end;	\
+		\
+		start = (u32)addr;	\
+		end = start + len;	\
+		start &= ~(line_size - 1);	\
+		end = ((end + line_size - 1) & ~(line_size - 1));	\
+		\
+		invalidate_dcache_range(start, end);	\
+	}
+#else
+#define invalidate_cache(...)
+#endif
+
 #define TIMEOUT_CNT 1000
 
 int sh_eth_send(struct eth_device *dev, void *packet, int len)
@@ -69,8 +88,11 @@ int sh_eth_send(struct eth_device *dev, void *packet, int len)
 
 	/* Wait until packet is transmitted */
 	timeout = TIMEOUT_CNT;
-	while (port_info->tx_desc_cur->td0 & TD_TACT && timeout--)
+	do {
+		invalidate_cache(port_info->tx_desc_cur,
+				 sizeof(struct tx_desc_s));
 		udelay(100);
+	} while (port_info->tx_desc_cur->td0 & TD_TACT && timeout--);
 
 	if (timeout < 0) {
 		printf(SHETHER_NAME ": transmit timeout\n");
@@ -94,12 +116,14 @@ int sh_eth_recv(struct eth_device *dev)
 	uchar *packet;
 
 	/* Check if the rx descriptor is ready */
+	invalidate_cache(port_info->rx_desc_cur, sizeof(struct rx_desc_s));
 	if (!(port_info->rx_desc_cur->rd0 & RD_RACT)) {
 		/* Check for errors */
 		if (!(port_info->rx_desc_cur->rd0 & RD_RFE)) {
 			len = port_info->rx_desc_cur->rd1 & 0xffff;
 			packet = (uchar *)
 				ADDR_TO_P2(port_info->rx_desc_cur->rd2);
+			invalidate_cache(packet, len);
 			NetReceive(packet, len);
 		}
 
@@ -108,7 +132,6 @@ int sh_eth_recv(struct eth_device *dev)
 			port_info->rx_desc_cur->rd0 = RD_RACT | RD_RDLE;
 		else
 			port_info->rx_desc_cur->rd0 = RD_RACT;
-
 		/* Point to the next descriptor */
 		port_info->rx_desc_cur++;
 		if (port_info->rx_desc_cur >=
@@ -237,15 +260,17 @@ static int sh_eth_rx_desc_init(struct sh_eth_dev *eth)
 	 * Allocate rx data buffers. They must be 32 bytes aligned  and in
 	 * P2 area
 	 */
-	port_info->rx_buf_malloc = malloc(NUM_RX_DESC * MAX_BUF_SIZE + 31);
+	port_info->rx_buf_malloc = malloc(
+		NUM_RX_DESC * MAX_BUF_SIZE + RX_BUF_ALIGNE_SIZE - 1);
 	if (!port_info->rx_buf_malloc) {
 		printf(SHETHER_NAME ": malloc failed\n");
 		ret = -ENOMEM;
 		goto err_buf_malloc;
 	}
 
-	tmp_addr = (u32)(((int)port_info->rx_buf_malloc + (32 - 1)) &
-			  ~(32 - 1));
+	tmp_addr = (u32)(((int)port_info->rx_buf_malloc
+			  + (RX_BUF_ALIGNE_SIZE - 1)) &
+			  ~(RX_BUF_ALIGNE_SIZE - 1));
 	port_info->rx_buf_base = (u8 *)ADDR_TO_P2(tmp_addr);
 
 	/* Initialize all descriptors */
@@ -351,8 +376,9 @@ static int sh_eth_config(struct sh_eth_dev *eth, bd_t *bd)
 	struct phy_device *phy;
 
 	/* Configure e-dmac registers */
-	sh_eth_write(eth, (sh_eth_read(eth, EDMR) & ~EMDR_DESC_R) | EDMR_EL,
-		     EDMR);
+	sh_eth_write(eth, (sh_eth_read(eth, EDMR) & ~EMDR_DESC_R) |
+			(EMDR_DESC | EDMR_EL), EDMR);
+
 	sh_eth_write(eth, 0, EESIPR);
 	sh_eth_write(eth, 0, TRSCER);
 	sh_eth_write(eth, 0, TFTR);
@@ -384,6 +410,8 @@ static int sh_eth_config(struct sh_eth_dev *eth, bd_t *bd)
 
 #if defined(CONFIG_CPU_SH7734) || defined(CONFIG_R8A7740)
 	sh_eth_write(eth, CONFIG_SH_ETHER_SH7734_MII, RMII_MII);
+#elif defined(CONFIG_R8A7790) || defined(CONFIG_R8A7791)
+	sh_eth_write(eth, sh_eth_read(eth, RMIIMR) | 0x1, RMIIMR);
 #endif
 	/* Configure phy */
 	ret = sh_eth_phy_config(eth);
@@ -407,7 +435,8 @@ static int sh_eth_config(struct sh_eth_dev *eth, bd_t *bd)
 		sh_eth_write(eth, GECMR_100B, GECMR);
 #elif defined(CONFIG_CPU_SH7757) || defined(CONFIG_CPU_SH7752)
 		sh_eth_write(eth, 1, RTRATE);
-#elif defined(CONFIG_CPU_SH7724)
+#elif defined(CONFIG_CPU_SH7724) || defined(CONFIG_R8A7790) || \
+		defined(CONFIG_R8A7791)
 		val = ECMR_RTM;
 #endif
 	} else if (phy->speed == 10) {
diff --git a/drivers/net/sh_eth.h b/drivers/net/sh_eth.h
index 9ad800e427..331c07cb59 100644
--- a/drivers/net/sh_eth.h
+++ b/drivers/net/sh_eth.h
@@ -31,6 +31,11 @@
 #define ADDR_TO_P2(addr)	(addr)
 #endif /* defined(CONFIG_SH) */
 
+/* base padding size is 16 */
+#ifndef CONFIG_SH_ETHER_ALIGNE_SIZE
+#define CONFIG_SH_ETHER_ALIGNE_SIZE 16
+#endif
+
 /* Number of supported ports */
 #define MAX_PORT_NUM	2
 
@@ -45,15 +50,16 @@
 
 /* The size of the tx descriptor is determined by how much padding is used.
    4, 20, or 52 bytes of padding can be used */
-#define TX_DESC_PADDING		4
-#define TX_DESC_SIZE		(12 + TX_DESC_PADDING)
+#define TX_DESC_PADDING	(CONFIG_SH_ETHER_ALIGNE_SIZE - 12)
+/* same as CONFIG_SH_ETHER_ALIGNE_SIZE */
+#define TX_DESC_SIZE	(12 + TX_DESC_PADDING)
 
 /* Tx descriptor. We always use 3 bytes of padding */
 struct tx_desc_s {
 	volatile u32 td0;
 	u32 td1;
 	u32 td2;		/* Buffer start */
-	u32 padding;
+	u8 padding[TX_DESC_PADDING];	/* aligned cache line size */
 };
 
 /* There is no limitation in the number of rx descriptors */
@@ -61,15 +67,18 @@ struct tx_desc_s {
 
 /* The size of the rx descriptor is determined by how much padding is used.
    4, 20, or 52 bytes of padding can be used */
-#define RX_DESC_PADDING		4
+#define RX_DESC_PADDING	(CONFIG_SH_ETHER_ALIGNE_SIZE - 12)
+/* same as CONFIG_SH_ETHER_ALIGNE_SIZE */
 #define RX_DESC_SIZE		(12 + RX_DESC_PADDING)
+/* aligned cache line size */
+#define RX_BUF_ALIGNE_SIZE	(CONFIG_SH_ETHER_ALIGNE_SIZE > 32 ? 64 : 32)
 
 /* Rx descriptor. We always use 4 bytes of padding */
 struct rx_desc_s {
 	volatile u32 rd0;
 	volatile u32 rd1;
 	u32 rd2;		/* Buffer start */
-	u32 padding;
+	u8 padding[TX_DESC_PADDING];	/* aligned cache line size */
 };
 
 struct sh_eth_info {
@@ -157,6 +166,7 @@ enum {
 	TLFRCR,
 	CERCR,
 	CEECR,
+	RMIIMR, /* R8A7790 */
 	MAFCR,
 	RTRATE,
 	CSMR,
@@ -263,6 +273,7 @@ static const u16 sh_eth_offset_fast_sh4[SH_ETH_MAX_REGISTER_OFFSET] = {
 	[RMCR]	= 0x0058,
 	[TFUCR]	= 0x0064,
 	[RFOCR]	= 0x0068,
+	[RMIIMR] = 0x006C,
 	[FCFTR]	= 0x0070,
 	[RPADIR]	= 0x0078,
 	[TRIMD]	= 0x007c,
@@ -276,7 +287,9 @@ static const u16 sh_eth_offset_fast_sh4[SH_ETH_MAX_REGISTER_OFFSET] = {
 #if defined(CONFIG_CPU_SH7763) || defined(CONFIG_CPU_SH7734)
 #define SH_ETH_TYPE_GETHER
 #define BASE_IO_ADDR	0xfee00000
-#elif defined(CONFIG_CPU_SH7757) || defined(CONFIG_CPU_SH7752)
+#elif defined(CONFIG_CPU_SH7757) || \
+	defined(CONFIG_CPU_SH7752) || \
+	defined(CONFIG_CPU_SH7753)
 #if defined(CONFIG_SH_ETHER_USE_GETHER)
 #define SH_ETH_TYPE_GETHER
 #define BASE_IO_ADDR	0xfee00000
@@ -290,6 +303,9 @@ static const u16 sh_eth_offset_fast_sh4[SH_ETH_MAX_REGISTER_OFFSET] = {
 #elif defined(CONFIG_R8A7740)
 #define SH_ETH_TYPE_GETHER
 #define BASE_IO_ADDR	0xE9A00000
+#elif defined(CONFIG_R8A7790) || defined(CONFIG_R8A7791)
+#define SH_ETH_TYPE_ETHER
+#define BASE_IO_ADDR	0xEE700200
 #endif
 
 /*
@@ -320,6 +336,14 @@ enum DMAC_M_BIT {
 #endif
 };
 
+#if CONFIG_SH_ETHER_ALIGNE_SIZE == 64
+# define EMDR_DESC EDMR_DL1
+#elif CONFIG_SH_ETHER_ALIGNE_SIZE == 32
+# define EMDR_DESC EDMR_DL0
+#elif CONFIG_SH_ETHER_ALIGNE_SIZE == 16 /* Default */
+# define EMDR_DESC 0
+#endif
+
 /* RFLR */
 #define RFLR_RFL_MIN	0x05EE	/* Recv Frame length 1518 byte */
 
@@ -334,7 +358,9 @@ enum DMAC_T_BIT {
 
 /* GECMR */
 enum GECMR_BIT {
-#if defined(CONFIG_CPU_SH7757) || defined(CONFIG_CPU_SH7752)
+#if defined(CONFIG_CPU_SH7757) || \
+	defined(CONFIG_CPU_SH7752) || \
+	defined(CONFIG_CPU_SH7753)
 	GECMR_1000B = 0x20, GECMR_100B = 0x01, GECMR_10B = 0x00,
 #else
 	GECMR_1000B = 0x01, GECMR_100B = 0x04, GECMR_10B = 0x00,
@@ -485,6 +511,8 @@ enum FELIC_MODE_BIT {
 	ECMR_PRM = 0x00000001,
 #ifdef CONFIG_CPU_SH7724
 	ECMR_RTM = 0x00000010,
+#elif defined(CONFIG_R8A7790) || defined(CONFIG_R8A7791)
+	ECMR_RTM = 0x00000004,
 #endif
 
 };
diff --git a/drivers/net/smc91111.h b/drivers/net/smc91111.h
index 9deee9bd2a..d9135cb57d 100644
--- a/drivers/net/smc91111.h
+++ b/drivers/net/smc91111.h
@@ -248,17 +248,26 @@ struct smc91111_priv{
 #define	SMC_inw(a,r)	(*((volatile word *)((a)->iobase+((r)<<1))))
 #elif CONFIG_BLACKFIN
 #define	SMC_inw(a,r)	({ word __v = (*((volatile word *)((a)->iobase+(r)))); SSYNC(); __v;})
+#elif CONFIG_ARM64
+#define	SMC_inw(a, r)	(*((volatile word*)((a)->iobase+((dword)(r)))))
 #else
-#define	SMC_inw(a,r)	(*((volatile word *)((a)->iobase+(r))))
+#define SMC_inw(a, r)	(*((volatile word*)((a)->iobase+(r))))
 #endif
 #define  SMC_inb(a,r)	(((r)&1) ? SMC_inw((a),(r)&~1)>>8 : SMC_inw((a),(r)&0xFF))
 
 #ifdef CONFIG_ADNPESC1
 #define	SMC_outw(a,d,r)	(*((volatile word *)((a)->iobase+((r)<<1))) = d)
 #elif CONFIG_BLACKFIN
-#define	SMC_outw(a,d,r)	{(*((volatile word *)((a)->iobase+(r))) = d); SSYNC();}
+#define	SMC_outw(a, d, r)	\
+			({	(*((volatile word*)((a)->iobase+((r)))) = d); \
+				SSYNC(); \
+			})
+#elif CONFIG_ARM64
+#define	SMC_outw(a, d, r)	\
+			(*((volatile word*)((a)->iobase+((dword)(r)))) = d)
 #else
-#define	SMC_outw(a,d,r)	(*((volatile word *)((a)->iobase+(r))) = d)
+#define	SMC_outw(a, d, r)	\
+			(*((volatile word*)((a)->iobase+(r))) = d)
 #endif
 #define	SMC_outb(a,d,r)	({	word __d = (byte)(d);  \
 				word __w = SMC_inw((a),(r)&~1);  \
diff --git a/drivers/net/tsec.c b/drivers/net/tsec.c
index f5e314b9ee..e9138f0338 100644
--- a/drivers/net/tsec.c
+++ b/drivers/net/tsec.c
@@ -5,7 +5,7 @@
  * terms of the GNU Public License, Version 2, incorporated
  * herein by reference.
  *
- * Copyright 2004-2011 Freescale Semiconductor, Inc.
+ * Copyright 2004-2011, 2013 Freescale Semiconductor, Inc.
  * (C) Copyright 2003, Motorola, Inc.
  * author Andy Fleming
  *
@@ -25,21 +25,13 @@ DECLARE_GLOBAL_DATA_PTR;
 
 #define TX_BUF_CNT		2
 
-static uint rxIdx;		/* index of the current RX buffer */
-static uint txIdx;		/* index of the current TX buffer */
-
-typedef volatile struct rtxbd {
-	txbd8_t txbd[TX_BUF_CNT];
-	rxbd8_t rxbd[PKTBUFSRX];
-} RTXBD;
-
-#define MAXCONTROLLERS	(8)
-
-static struct tsec_private *privlist[MAXCONTROLLERS];
-static int num_tsecs = 0;
+static uint rx_idx;		/* index of the current RX buffer */
+static uint tx_idx;		/* index of the current TX buffer */
 
 #ifdef __GNUC__
-static RTXBD rtx __attribute__ ((aligned(8)));
+static struct txbd8 __iomem txbd[TX_BUF_CNT] __aligned(8);
+static struct rxbd8 __iomem rxbd[PKTBUFSRX] __aligned(8);
+
 #else
 #error "rtx must be 64-bit aligned"
 #endif
@@ -57,7 +49,7 @@ static struct tsec_info_struct tsec_info[] = {
 #endif
 #ifdef CONFIG_MPC85XX_FEC
 	{
-		.regs = (tsec_t *)(TSEC_BASE_ADDR + 0x2000),
+		.regs = TSEC_GET_REGS(2, 0x2000),
 		.devname = CONFIG_MPC85XX_FEC_NAME,
 		.phyaddr = FEC_PHY_ADDR,
 		.flags = FEC_FLAGS,
@@ -113,32 +105,31 @@ static void tsec_configure_serdes(struct tsec_private *priv)
  * result.
  * 2) Use the 8 most significant bits as a hash into a 256-entry
  * table.  The table is controlled through 8 32-bit registers:
- * gaddr0-7.  gaddr0's MSB is entry 0, and gaddr7's LSB is
- * gaddr7.  This means that the 3 most significant bits in the
+ * gaddr0-7.  gaddr0's MSB is entry 0, and gaddr7's LSB is entry
+ * 255.  This means that the 3 most significant bits in the
  * hash index which gaddr register to use, and the 5 other bits
  * indicate which bit (assuming an IBM numbering scheme, which
- * for PowerPC (tm) is usually the case) in the tregister holds
+ * for PowerPC (tm) is usually the case) in the register holds
  * the entry. */
 static int
-tsec_mcast_addr (struct eth_device *dev, u8 mcast_mac, u8 set)
+tsec_mcast_addr(struct eth_device *dev, const u8 *mcast_mac, u8 set)
 {
-	struct tsec_private *priv = privlist[1];
-	volatile tsec_t *regs = priv->regs;
-	volatile u32  *reg_array, value;
-	u8 result, whichbit, whichreg;
-
-	result = (u8)((ether_crc(MAC_ADDR_LEN,mcast_mac) >> 24) & 0xff);
-	whichbit = result & 0x1f;	/* the 5 LSB = which bit to set */
-	whichreg = result >> 5;		/* the 3 MSB = which reg to set it in */
-	value = (1 << (31-whichbit));
-
-	reg_array = &(regs->hash.gaddr0);
-
-	if (set) {
-		reg_array[whichreg] |= value;
-	} else {
-		reg_array[whichreg] &= ~value;
-	}
+	struct tsec_private *priv = (struct tsec_private *)dev->priv;
+	struct tsec __iomem *regs = priv->regs;
+	u32 result, value;
+	u8 whichbit, whichreg;
+
+	result = ether_crc(MAC_ADDR_LEN, mcast_mac);
+	whichbit = (result >> 24) & 0x1f; /* the 5 LSB = which bit to set */
+	whichreg = result >> 29; /* the 3 MSB = which reg to set it in */
+
+	value = 1 << (31-whichbit);
+
+	if (set)
+		setbits_be32(&regs->hash.gaddr0 + whichreg, value);
+	else
+		clrbits_be32(&regs->hash.gaddr0 + whichreg, value);
+
 	return 0;
 }
 #endif /* Multicast TFTP ? */
@@ -147,7 +138,7 @@ tsec_mcast_addr (struct eth_device *dev, u8 mcast_mac, u8 set)
  * those we don't care about (unless zero is bad, in which case,
  * choose a more appropriate value)
  */
-static void init_registers(tsec_t *regs)
+static void init_registers(struct tsec __iomem *regs)
 {
 	/* Clear IEVENT */
 	out_be32(&regs->ievent, IEVENT_INIT_CLEAR);
@@ -175,7 +166,7 @@ static void init_registers(tsec_t *regs)
 	out_be32(&regs->rctrl, 0x00000000);
 
 	/* Init RMON mib registers */
-	memset((void *)&(regs->rmon), 0, sizeof(rmon_mib_t));
+	memset((void *)&regs->rmon, 0, sizeof(regs->rmon));
 
 	out_be32(&regs->rmon.cam1, 0xffffffff);
 	out_be32(&regs->rmon.cam2, 0xffffffff);
@@ -194,7 +185,7 @@ static void init_registers(tsec_t *regs)
  */
 static void adjust_link(struct tsec_private *priv, struct phy_device *phydev)
 {
-	tsec_t *regs = priv->regs;
+	struct tsec __iomem *regs = priv->regs;
 	u32 ecntrl, maccfg2;
 
 	if (!phydev->link) {
@@ -248,7 +239,7 @@ static void adjust_link(struct tsec_private *priv, struct phy_device *phydev)
 void redundant_init(struct eth_device *dev)
 {
 	struct tsec_private *priv = dev->priv;
-	tsec_t *regs = priv->regs;
+	struct tsec __iomem *regs = priv->regs;
 	uint t, count = 0;
 	int fail = 1;
 	static const u8 pkt[] = {
@@ -281,23 +272,26 @@ void redundant_init(struct eth_device *dev)
 	clrbits_be32(&regs->dmactrl, DMACTRL_GRS | DMACTRL_GTS);
 
 	do {
+		uint16_t status;
 		tsec_send(dev, (void *)pkt, sizeof(pkt));
 
 		/* Wait for buffer to be received */
-		for (t = 0; rtx.rxbd[rxIdx].status & RXBD_EMPTY; t++) {
+		for (t = 0; in_be16(&rxbd[rx_idx].status) & RXBD_EMPTY; t++) {
 			if (t >= 10 * TOUT_LOOP) {
 				printf("%s: tsec: rx error\n", dev->name);
 				break;
 			}
 		}
 
-		if (!memcmp(pkt, (void *)NetRxPackets[rxIdx], sizeof(pkt)))
+		if (!memcmp(pkt, (void *)NetRxPackets[rx_idx], sizeof(pkt)))
 			fail = 0;
 
-		rtx.rxbd[rxIdx].length = 0;
-		rtx.rxbd[rxIdx].status =
-		    RXBD_EMPTY | (((rxIdx + 1) == PKTBUFSRX) ? RXBD_WRAP : 0);
-		rxIdx = (rxIdx + 1) % PKTBUFSRX;
+		out_be16(&rxbd[rx_idx].length, 0);
+		status = RXBD_EMPTY;
+		if ((rx_idx + 1) == PKTBUFSRX)
+			status |= RXBD_WRAP;
+		out_be16(&rxbd[rx_idx].status, status);
+		rx_idx = (rx_idx + 1) % PKTBUFSRX;
 
 		if (in_be32(&regs->ievent) & IEVENT_BSY) {
 			out_be32(&regs->ievent, IEVENT_BSY);
@@ -325,36 +319,39 @@ void redundant_init(struct eth_device *dev)
  */
 static void startup_tsec(struct eth_device *dev)
 {
-	int i;
 	struct tsec_private *priv = (struct tsec_private *)dev->priv;
-	tsec_t *regs = priv->regs;
+	struct tsec __iomem *regs = priv->regs;
+	uint16_t status;
+	int i;
 
 	/* reset the indices to zero */
-	rxIdx = 0;
-	txIdx = 0;
+	rx_idx = 0;
+	tx_idx = 0;
 #ifdef CONFIG_SYS_FSL_ERRATUM_NMG_ETSEC129
 	uint svr;
 #endif
 
 	/* Point to the buffer descriptors */
-	out_be32(&regs->tbase, (unsigned int)(&rtx.txbd[txIdx]));
-	out_be32(&regs->rbase, (unsigned int)(&rtx.rxbd[rxIdx]));
+	out_be32(&regs->tbase, (u32)&txbd[0]);
+	out_be32(&regs->rbase, (u32)&rxbd[0]);
 
 	/* Initialize the Rx Buffer descriptors */
 	for (i = 0; i < PKTBUFSRX; i++) {
-		rtx.rxbd[i].status = RXBD_EMPTY;
-		rtx.rxbd[i].length = 0;
-		rtx.rxbd[i].bufPtr = (uint) NetRxPackets[i];
+		out_be16(&rxbd[i].status, RXBD_EMPTY);
+		out_be16(&rxbd[i].length, 0);
+		out_be32(&rxbd[i].bufptr, (u32)NetRxPackets[i]);
 	}
-	rtx.rxbd[PKTBUFSRX - 1].status |= RXBD_WRAP;
+	status = in_be16(&rxbd[PKTBUFSRX - 1].status);
+	out_be16(&rxbd[PKTBUFSRX - 1].status, status | RXBD_WRAP);
 
 	/* Initialize the TX Buffer Descriptors */
 	for (i = 0; i < TX_BUF_CNT; i++) {
-		rtx.txbd[i].status = 0;
-		rtx.txbd[i].length = 0;
-		rtx.txbd[i].bufPtr = 0;
+		out_be16(&txbd[i].status, 0);
+		out_be16(&txbd[i].length, 0);
+		out_be32(&txbd[i].bufptr, 0);
 	}
-	rtx.txbd[TX_BUF_CNT - 1].status |= TXBD_WRAP;
+	status = in_be16(&txbd[TX_BUF_CNT - 1].status);
+	out_be16(&txbd[TX_BUF_CNT - 1].status, status | TXBD_WRAP);
 
 #ifdef CONFIG_SYS_FSL_ERRATUM_NMG_ETSEC129
 	svr = get_svr();
@@ -378,66 +375,67 @@ static void startup_tsec(struct eth_device *dev)
  */
 static int tsec_send(struct eth_device *dev, void *packet, int length)
 {
-	int i;
-	int result = 0;
 	struct tsec_private *priv = (struct tsec_private *)dev->priv;
-	tsec_t *regs = priv->regs;
+	struct tsec __iomem *regs = priv->regs;
+	uint16_t status;
+	int result = 0;
+	int i;
 
 	/* Find an empty buffer descriptor */
-	for (i = 0; rtx.txbd[txIdx].status & TXBD_READY; i++) {
+	for (i = 0; in_be16(&txbd[tx_idx].status) & TXBD_READY; i++) {
 		if (i >= TOUT_LOOP) {
 			debug("%s: tsec: tx buffers full\n", dev->name);
 			return result;
 		}
 	}
 
-	rtx.txbd[txIdx].bufPtr = (uint) packet;
-	rtx.txbd[txIdx].length = length;
-	rtx.txbd[txIdx].status |=
-	    (TXBD_READY | TXBD_LAST | TXBD_CRC | TXBD_INTERRUPT);
+	out_be32(&txbd[tx_idx].bufptr, (u32)packet);
+	out_be16(&txbd[tx_idx].length, length);
+	status = in_be16(&txbd[tx_idx].status);
+	out_be16(&txbd[tx_idx].status, status |
+		(TXBD_READY | TXBD_LAST | TXBD_CRC | TXBD_INTERRUPT));
 
 	/* Tell the DMA to go */
 	out_be32(&regs->tstat, TSTAT_CLEAR_THALT);
 
 	/* Wait for buffer to be transmitted */
-	for (i = 0; rtx.txbd[txIdx].status & TXBD_READY; i++) {
+	for (i = 0; in_be16(&txbd[tx_idx].status) & TXBD_READY; i++) {
 		if (i >= TOUT_LOOP) {
 			debug("%s: tsec: tx error\n", dev->name);
 			return result;
 		}
 	}
 
-	txIdx = (txIdx + 1) % TX_BUF_CNT;
-	result = rtx.txbd[txIdx].status & TXBD_STATS;
+	tx_idx = (tx_idx + 1) % TX_BUF_CNT;
+	result = in_be16(&txbd[tx_idx].status) & TXBD_STATS;
 
 	return result;
 }
 
 static int tsec_recv(struct eth_device *dev)
 {
-	int length;
 	struct tsec_private *priv = (struct tsec_private *)dev->priv;
-	tsec_t *regs = priv->regs;
+	struct tsec __iomem *regs = priv->regs;
 
-	while (!(rtx.rxbd[rxIdx].status & RXBD_EMPTY)) {
-
-		length = rtx.rxbd[rxIdx].length;
+	while (!(in_be16(&rxbd[rx_idx].status) & RXBD_EMPTY)) {
+		int length = in_be16(&rxbd[rx_idx].length);
+		uint16_t status = in_be16(&rxbd[rx_idx].status);
 
 		/* Send the packet up if there were no errors */
-		if (!(rtx.rxbd[rxIdx].status & RXBD_STATS)) {
-			NetReceive(NetRxPackets[rxIdx], length - 4);
-		} else {
-			printf("Got error %x\n",
-			       (rtx.rxbd[rxIdx].status & RXBD_STATS));
-		}
+		if (!(status & RXBD_STATS))
+			NetReceive(NetRxPackets[rx_idx], length - 4);
+		else
+			printf("Got error %x\n", (status & RXBD_STATS));
 
-		rtx.rxbd[rxIdx].length = 0;
+		out_be16(&rxbd[rx_idx].length, 0);
 
+		status = RXBD_EMPTY;
 		/* Set the wrap bit if this is the last element in the list */
-		rtx.rxbd[rxIdx].status =
-		    RXBD_EMPTY | (((rxIdx + 1) == PKTBUFSRX) ? RXBD_WRAP : 0);
+		if ((rx_idx + 1) == PKTBUFSRX)
+			status |= RXBD_WRAP;
+		out_be16(&rxbd[rx_idx].status, status);
 
-		rxIdx = (rxIdx + 1) % PKTBUFSRX;
+		rx_idx = (rx_idx + 1) % PKTBUFSRX;
 	}
 
 	if (in_be32(&regs->ievent) & IEVENT_BSY) {
@@ -453,7 +451,7 @@ static int tsec_recv(struct eth_device *dev)
 static void tsec_halt(struct eth_device *dev)
 {
 	struct tsec_private *priv = (struct tsec_private *)dev->priv;
-	tsec_t *regs = priv->regs;
+	struct tsec __iomem *regs = priv->regs;
 
 	clrbits_be32(&regs->dmactrl, DMACTRL_GRS | DMACTRL_GTS);
 	setbits_be32(&regs->dmactrl, DMACTRL_GRS | DMACTRL_GTS);
@@ -475,11 +473,9 @@ static void tsec_halt(struct eth_device *dev)
  */
 static int tsec_init(struct eth_device *dev, bd_t * bd)
 {
-	uint tempval;
-	char tmpbuf[MAC_ADDR_LEN];
-	int i;
 	struct tsec_private *priv = (struct tsec_private *)dev->priv;
-	tsec_t *regs = priv->regs;
+	struct tsec __iomem *regs = priv->regs;
+	u32 tempval;
 	int ret;
 
 	/* Make sure the controller is stopped */
@@ -492,16 +488,16 @@ static int tsec_init(struct eth_device *dev, bd_t * bd)
 	out_be32(&regs->ecntrl, ECNTRL_INIT_SETTINGS);
 
 	/* Copy the station address into the address registers.
-	 * Backwards, because little endian MACS are dumb */
-	for (i = 0; i < MAC_ADDR_LEN; i++)
-		tmpbuf[MAC_ADDR_LEN - 1 - i] = dev->enetaddr[i];
-
-	tempval = (tmpbuf[0] << 24) | (tmpbuf[1] << 16) | (tmpbuf[2] << 8) |
-		  tmpbuf[3];
+	 * For a station address of 0x12345678ABCD in transmission
+	 * order (BE), MACnADDR1 is set to 0xCDAB7856 and
+	 * MACnADDR2 is set to 0x34120000.
+	 */
+	tempval = (dev->enetaddr[5] << 24) | (dev->enetaddr[4] << 16) |
+		  (dev->enetaddr[3] << 8)  |  dev->enetaddr[2];
 
 	out_be32(&regs->macstnaddr1, tempval);
 
-	tempval = *((uint *) (tmpbuf + 4));
+	tempval = (dev->enetaddr[1] << 24) | (dev->enetaddr[0] << 16);
 
 	out_be32(&regs->macstnaddr2, tempval);
 
@@ -527,7 +523,7 @@ static int tsec_init(struct eth_device *dev, bd_t * bd)
 
 static phy_interface_t tsec_get_interface(struct tsec_private *priv)
 {
-	tsec_t *regs = priv->regs;
+	struct tsec __iomem *regs = priv->regs;
 	u32 ecntrl;
 
 	ecntrl = in_be32(&regs->ecntrl);
@@ -576,7 +572,7 @@ static int init_phy(struct eth_device *dev)
 {
 	struct tsec_private *priv = (struct tsec_private *)dev->priv;
 	struct phy_device *phydev;
-	tsec_t *regs = priv->regs;
+	struct tsec __iomem *regs = priv->regs;
 	u32 supported = (SUPPORTED_10baseT_Half |
 			SUPPORTED_10baseT_Full |
 			SUPPORTED_100baseT_Half |
@@ -626,7 +622,6 @@ static int tsec_initialize(bd_t *bis, struct tsec_info_struct *tsec_info)
 	if (NULL == priv)
 		return 0;
 
-	privlist[num_tsecs++] = priv;
 	priv->regs = tsec_info->regs;
 	priv->phyregs_sgmii = tsec_info->miiregs_sgmii;
 
@@ -684,7 +679,7 @@ int tsec_standard_init(bd_t *bis)
 {
 	struct fsl_pq_mdio_info info;
 
-	info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR;
+	info.regs = TSEC_GET_MDIO_REGS_BASE(1);
 	info.name = DEFAULT_MII_NAME;
 
 	fsl_pq_mdio_init(bis, &info);
diff --git a/drivers/net/xilinx_axi_emac.c b/drivers/net/xilinx_axi_emac.c
index bb5044b31f..262b67b6cf 100644
--- a/drivers/net/xilinx_axi_emac.c
+++ b/drivers/net/xilinx_axi_emac.c
@@ -261,6 +261,10 @@ static int setup_phy(struct eth_device *dev)
 		       phydev->dev->name);
 		return 0;
 	}
+	if (!phydev->link) {
+		printf("%s: No link.\n", phydev->dev->name);
+		return 0;
+	}
 
 	switch (phydev->speed) {
 	case 1000:
diff --git a/drivers/net/xilinx_emaclite.c b/drivers/net/xilinx_emaclite.c
index 0a5209d2f8..2a5cc44553 100644
--- a/drivers/net/xilinx_emaclite.c
+++ b/drivers/net/xilinx_emaclite.c
@@ -14,8 +14,6 @@
 #include <asm/io.h>
 #include <fdtdec.h>
 
-DECLARE_GLOBAL_DATA_PTR;
-
 #undef DEBUG
 
 #define ENET_ADDR_LENGTH	6
@@ -364,24 +362,27 @@ int xilinx_emaclite_initialize(bd_t *bis, unsigned long base_addr,
 }
 
 #ifdef CONFIG_OF_CONTROL
-int xilinx_emaclite_init(bd_t *bis)
+int xilinx_emaclite_of_init(const void *blob)
 {
 	int offset = 0;
 	u32 ret = 0;
 	u32 reg;
 
 	do {
-		offset = fdt_node_offset_by_compatible(gd->fdt_blob, offset,
+		offset = fdt_node_offset_by_compatible(blob, offset,
 					"xlnx,xps-ethernetlite-1.00.a");
 		if (offset != -1) {
-			reg = fdtdec_get_addr(gd->fdt_blob, offset, "reg");
+			reg = fdtdec_get_addr(blob, offset, "reg");
 			if (reg != FDT_ADDR_T_NONE) {
-				u32 rxpp = fdtdec_get_int(gd->fdt_blob, offset,
+				u32 rxpp = fdtdec_get_int(blob, offset,
 							"xlnx,rx-ping-pong", 0);
-				u32 txpp = fdtdec_get_int(gd->fdt_blob, offset,
+				u32 txpp = fdtdec_get_int(blob, offset,
 							"xlnx,tx-ping-pong", 0);
-				ret |= xilinx_emaclite_initialize(bis, reg,
+				ret |= xilinx_emaclite_initialize(NULL, reg,
 								txpp, rxpp);
+			} else {
+				debug("EMACLITE: Can't get base address\n");
+				return -1;
 			}
 		}
 	} while (offset != -1);
diff --git a/drivers/net/zynq_gem.c b/drivers/net/zynq_gem.c
index 236a75311f..101489c994 100644
--- a/drivers/net/zynq_gem.c
+++ b/drivers/net/zynq_gem.c
@@ -12,6 +12,8 @@
 #include <common.h>
 #include <net.h>
 #include <config.h>
+#include <fdtdec.h>
+#include <libfdt.h>
 #include <malloc.h>
 #include <asm/io.h>
 #include <phy.h>
@@ -43,11 +45,6 @@
 #define ZYNQ_GEM_TXBUF_WRAP_MASK	0x40000000
 #define ZYNQ_GEM_TXBUF_LAST_MASK	0x00008000 /* Last buffer */
 
-#define ZYNQ_GEM_TXSR_HRESPNOK_MASK	0x00000100 /* Transmit hresp not OK */
-#define ZYNQ_GEM_TXSR_URUN_MASK		0x00000040 /* Transmit underrun */
-/* Transmit buffs exhausted mid frame */
-#define ZYNQ_GEM_TXSR_BUFEXH_MASK	0x00000010
-
 #define ZYNQ_GEM_NWCTRL_TXEN_MASK	0x00000008 /* Enable transmit */
 #define ZYNQ_GEM_NWCTRL_RXEN_MASK	0x00000004 /* Enable receive */
 #define ZYNQ_GEM_NWCTRL_MDEN_MASK	0x00000010 /* Enable MDIO port */
@@ -90,6 +87,16 @@
  */
 #define PHY_DETECT_MASK 0x1808
 
+/* TX BD status masks */
+#define ZYNQ_GEM_TXBUF_FRMLEN_MASK	0x000007ff
+#define ZYNQ_GEM_TXBUF_EXHAUSTED	0x08000000
+#define ZYNQ_GEM_TXBUF_UNDERRUN		0x10000000
+
+/* Clock frequencies for different speeds */
+#define ZYNQ_GEM_FREQUENCY_10	2500000UL
+#define ZYNQ_GEM_FREQUENCY_100	25000000UL
+#define ZYNQ_GEM_FREQUENCY_1000	125000000UL
+
 /* Device registers */
 struct zynq_gem_regs {
 	u32 nwctrl; /* Network Control reg */
@@ -123,12 +130,18 @@ struct emac_bd {
 };
 
 #define RX_BUF 3
+/* Page table entries are set to 1MB, or multiples of 1MB
+ * (not < 1MB). driver uses less bd's so use 1MB bdspace.
+ */
+#define BD_SPACE	0x100000
+/* BD separation space */
+#define BD_SEPRN_SPACE	64
 
 /* Initialized, rxbd_current, rx_first_buf must be 0 after init */
 struct zynq_gem_priv {
-	struct emac_bd tx_bd;
-	struct emac_bd rx_bd[RX_BUF];
-	char rxbuffers[RX_BUF * PKTSIZE_ALIGN];
+	struct emac_bd *tx_bd;
+	struct emac_bd *rx_bd;
+	char *rxbuffers;
 	u32 rxbd_current;
 	u32 rx_first_buf;
 	int phyaddr;
@@ -264,7 +277,8 @@ static int zynq_gem_setup_mac(struct eth_device *dev)
 
 static int zynq_gem_init(struct eth_device *dev, bd_t * bis)
 {
-	u32 i, rclk, clk = 0;
+	u32 i;
+	unsigned long clk_rate = 0;
 	struct phy_device *phydev;
 	const u32 stat_size = (sizeof(struct zynq_gem_regs) -
 				offsetof(struct zynq_gem_regs, stat)) / 4;
@@ -299,20 +313,18 @@ static int zynq_gem_init(struct eth_device *dev, bd_t * bis)
 			readl(&regs->stat[i]);
 
 		/* Setup RxBD space */
-		memset(&(priv->rx_bd), 0, sizeof(priv->rx_bd));
-		/* Create the RxBD ring */
-		memset(&(priv->rxbuffers), 0, sizeof(priv->rxbuffers));
+		memset(priv->rx_bd, 0, RX_BUF * sizeof(struct emac_bd));
 
 		for (i = 0; i < RX_BUF; i++) {
 			priv->rx_bd[i].status = 0xF0000000;
 			priv->rx_bd[i].addr =
-					(u32)((char *)&(priv->rxbuffers) +
+					((u32)(priv->rxbuffers) +
 							(i * PKTSIZE_ALIGN));
 		}
 		/* WRAP bit to last BD */
 		priv->rx_bd[--i].addr |= ZYNQ_GEM_RXBUF_WRAP_MASK;
 		/* Write RxBDs to IP */
-		writel((u32)&(priv->rx_bd), &regs->rxqbase);
+		writel((u32)priv->rx_bd, &regs->rxqbase);
 
 		/* Setup for DMA Configuration register */
 		writel(ZYNQ_GEM_DMACR_INIT, &regs->dmacr);
@@ -335,30 +347,31 @@ static int zynq_gem_init(struct eth_device *dev, bd_t * bis)
 	phy_config(phydev);
 	phy_startup(phydev);
 
+	if (!phydev->link) {
+		printf("%s: No link.\n", phydev->dev->name);
+		return -1;
+	}
+
 	switch (phydev->speed) {
 	case SPEED_1000:
 		writel(ZYNQ_GEM_NWCFG_INIT | ZYNQ_GEM_NWCFG_SPEED1000,
 		       &regs->nwcfg);
-		rclk = (0 << 4) | (1 << 0);
-		clk = (1 << 20) | (8 << 8) | (0 << 4) | (1 << 0);
+		clk_rate = ZYNQ_GEM_FREQUENCY_1000;
 		break;
 	case SPEED_100:
 		clrsetbits_le32(&regs->nwcfg, ZYNQ_GEM_NWCFG_SPEED1000,
 				ZYNQ_GEM_NWCFG_INIT | ZYNQ_GEM_NWCFG_SPEED100);
-		rclk = 1 << 0;
-		clk = (5 << 20) | (8 << 8) | (0 << 4) | (1 << 0);
+		clk_rate = ZYNQ_GEM_FREQUENCY_100;
 		break;
 	case SPEED_10:
-		rclk = 1 << 0;
-		/* FIXME untested */
-		clk = (5 << 20) | (8 << 8) | (0 << 4) | (1 << 0);
+		clk_rate = ZYNQ_GEM_FREQUENCY_10;
 		break;
 	}
 
 	/* Change the rclk and clk only not using EMIO interface */
 	if (!priv->emio)
 		zynq_slcr_gem_clk_setup(dev->iobase !=
-					ZYNQ_GEM_BASEADDR0, rclk, clk);
+					ZYNQ_GEM_BASEADDR0, clk_rate);
 
 	setbits_le32(&regs->nwctrl, ZYNQ_GEM_NWCTRL_RXEN_MASK |
 					ZYNQ_GEM_NWCTRL_TXEN_MASK);
@@ -368,32 +381,35 @@ static int zynq_gem_init(struct eth_device *dev, bd_t * bis)
 
 static int zynq_gem_send(struct eth_device *dev, void *ptr, int len)
 {
-	u32 status;
+	u32 addr, size;
 	struct zynq_gem_priv *priv = dev->priv;
 	struct zynq_gem_regs *regs = (struct zynq_gem_regs *)dev->iobase;
-	const u32 mask = ZYNQ_GEM_TXSR_HRESPNOK_MASK | \
-			ZYNQ_GEM_TXSR_URUN_MASK | ZYNQ_GEM_TXSR_BUFEXH_MASK;
 
 	/* setup BD */
-	writel((u32)&(priv->tx_bd), &regs->txqbase);
+	writel((u32)priv->tx_bd, &regs->txqbase);
 
 	/* Setup Tx BD */
-	memset((void *)&(priv->tx_bd), 0, sizeof(struct emac_bd));
+	memset(priv->tx_bd, 0, sizeof(struct emac_bd));
+
+	priv->tx_bd->addr = (u32)ptr;
+	priv->tx_bd->status = (len & ZYNQ_GEM_TXBUF_FRMLEN_MASK) |
+				ZYNQ_GEM_TXBUF_LAST_MASK;
 
-	priv->tx_bd.addr = (u32)ptr;
-	priv->tx_bd.status = len | ZYNQ_GEM_TXBUF_LAST_MASK;
+	addr = (u32) ptr;
+	addr &= ~(ARCH_DMA_MINALIGN - 1);
+	size = roundup(len, ARCH_DMA_MINALIGN);
+	flush_dcache_range(addr, addr + size);
+	barrier();
 
 	/* Start transmit */
 	setbits_le32(&regs->nwctrl, ZYNQ_GEM_NWCTRL_STARTTX_MASK);
 
-	/* Read the stat register to know if the packet has been transmitted */
-	status = readl(&regs->txsr);
-	if (status & mask)
-		printf("Something has gone wrong here!? Status is 0x%x.\n",
-		       status);
+	/* Read TX BD status */
+	if (priv->tx_bd->status & ZYNQ_GEM_TXBUF_UNDERRUN)
+		printf("TX underrun\n");
+	if (priv->tx_bd->status & ZYNQ_GEM_TXBUF_EXHAUSTED)
+		printf("TX buffers exhausted in mid frame\n");
 
-	/* Clear Tx status register before leaving . */
-	writel(status, &regs->txsr);
 	return 0;
 }
 
@@ -416,8 +432,12 @@ static int zynq_gem_recv(struct eth_device *dev)
 
 	frame_len = current_bd->status & ZYNQ_GEM_RXBUF_LEN_MASK;
 	if (frame_len) {
-		NetReceive((u8 *) (current_bd->addr &
-					ZYNQ_GEM_RXBUF_ADD_MASK), frame_len);
+		u32 addr = current_bd->addr & ZYNQ_GEM_RXBUF_ADD_MASK;
+		addr &= ~(ARCH_DMA_MINALIGN - 1);
+		u32 size = roundup(frame_len, ARCH_DMA_MINALIGN);
+		invalidate_dcache_range(addr, addr + size);
+
+		NetReceive((u8 *)addr, frame_len);
 
 		if (current_bd->status & ZYNQ_GEM_RXBUF_SOF_MASK)
 			priv->rx_first_buf = priv->rxbd_current;
@@ -471,6 +491,7 @@ int zynq_gem_initialize(bd_t *bis, int base_addr, int phy_addr, u32 emio)
 {
 	struct eth_device *dev;
 	struct zynq_gem_priv *priv;
+	void *bd_space;
 
 	dev = calloc(1, sizeof(*dev));
 	if (dev == NULL)
@@ -483,6 +504,18 @@ int zynq_gem_initialize(bd_t *bis, int base_addr, int phy_addr, u32 emio)
 	}
 	priv = dev->priv;
 
+	/* Align rxbuffers to ARCH_DMA_MINALIGN */
+	priv->rxbuffers = memalign(ARCH_DMA_MINALIGN, RX_BUF * PKTSIZE_ALIGN);
+	memset(priv->rxbuffers, 0, RX_BUF * PKTSIZE_ALIGN);
+
+	/* Align bd_space to 1MB */
+	bd_space = memalign(1 << MMU_SECTION_SHIFT, BD_SPACE);
+	mmu_set_region_dcache_behaviour((u32)bd_space, BD_SPACE, DCACHE_OFF);
+
+	/* Initialize the bd spaces for tx and rx bd's */
+	priv->tx_bd = (struct emac_bd *)bd_space;
+	priv->rx_bd = (struct emac_bd *)((u32)bd_space + BD_SEPRN_SPACE);
+
 	priv->phyaddr = phy_addr;
 	priv->emio = emio;
 
@@ -503,3 +536,43 @@ int zynq_gem_initialize(bd_t *bis, int base_addr, int phy_addr, u32 emio)
 
 	return 1;
 }
+
+#ifdef CONFIG_OF_CONTROL
+int zynq_gem_of_init(const void *blob)
+{
+	int offset = 0;
+	u32 ret = 0;
+	u32 reg, phy_reg;
+
+	debug("ZYNQ GEM: Initialization\n");
+
+	do {
+		offset = fdt_node_offset_by_compatible(blob, offset,
+					"xlnx,ps7-ethernet-1.00.a");
+		if (offset != -1) {
+			reg = fdtdec_get_addr(blob, offset, "reg");
+			if (reg != FDT_ADDR_T_NONE) {
+				offset = fdtdec_lookup_phandle(blob, offset,
+							       "phy-handle");
+				if (offset != -1)
+					phy_reg = fdtdec_get_addr(blob, offset,
+								  "reg");
+				else
+					phy_reg = 0;
+
+				debug("ZYNQ GEM: addr %x, phyaddr %x\n",
+				      reg, phy_reg);
+
+				ret |= zynq_gem_initialize(NULL, reg,
+							   phy_reg, 0);
+
+			} else {
+				debug("ZYNQ GEM: Can't get base address\n");
+				return -1;
+			}
+		}
+	} while (offset != -1);
+
+	return ret;
+}
+#endif
diff --git a/drivers/pci/Makefile b/drivers/pci/Makefile
index be26b60592..e73a498619 100644
--- a/drivers/pci/Makefile
+++ b/drivers/pci/Makefile
@@ -5,36 +5,15 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	:= $(obj)libpci.o
-
-COBJS-$(CONFIG_FSL_PCI_INIT) += fsl_pci_init.o
-COBJS-$(CONFIG_PCI) += pci.o pci_auto.o
-COBJS-$(CONFIG_PCI_INDIRECT_BRIDGE) += pci_indirect.o
-COBJS-$(CONFIG_PCI_GT64120) += pci_gt64120.o
-COBJS-$(CONFIG_FTPCI100) += pci_ftpci100.o
-COBJS-$(CONFIG_IXP_PCI) += pci_ixp.o
-COBJS-$(CONFIG_SH4_PCI) += pci_sh4.o
-COBJS-$(CONFIG_SH7751_PCI) +=pci_sh7751.o
-COBJS-$(CONFIG_SH7780_PCI) +=pci_sh7780.o
-COBJS-$(CONFIG_TSI108_PCI) += tsi108_pci.o
-COBJS-$(CONFIG_WINBOND_83C553) += w83c553f.o
-
-COBJS	:= $(COBJS-y)
-SRCS	:= $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-
-all:	$(LIB)
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-$(CONFIG_FSL_PCI_INIT) += fsl_pci_init.o
+obj-$(CONFIG_PCI) += pci.o pci_auto.o
+obj-$(CONFIG_PCI_INDIRECT_BRIDGE) += pci_indirect.o
+obj-$(CONFIG_PCI_GT64120) += pci_gt64120.o
+obj-$(CONFIG_PCI_MSC01) += pci_msc01.o
+obj-$(CONFIG_PCIE_IMX) += pcie_imx.o
+obj-$(CONFIG_FTPCI100) += pci_ftpci100.o
+obj-$(CONFIG_SH4_PCI) += pci_sh4.o
+obj-$(CONFIG_SH7751_PCI) +=pci_sh7751.o
+obj-$(CONFIG_SH7780_PCI) +=pci_sh7780.o
+obj-$(CONFIG_TSI108_PCI) += tsi108_pci.o
+obj-$(CONFIG_WINBOND_83C553) += w83c553f.o
diff --git a/drivers/pci/fsl_pci_init.c b/drivers/pci/fsl_pci_init.c
index d55db1a0b6..6317fb1324 100644
--- a/drivers/pci/fsl_pci_init.c
+++ b/drivers/pci/fsl_pci_init.c
@@ -295,6 +295,15 @@ void fsl_pci_init(struct pci_controller *hose, struct fsl_pci_info *pci_info)
 	int enabled, r, inbound = 0;
 	u16 ltssm;
 	u8 temp8, pcie_cap;
+	int pcie_cap_pos;
+	int pci_dcr;
+	int pci_dsr;
+	int pci_lsr;
+
+#if defined(CONFIG_FSL_PCIE_DISABLE_ASPM)
+	int pci_lcr;
+#endif
+
 	volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *)cfg_addr;
 	struct pci_region *reg = hose->regions + hose->region_count;
 	pci_dev_t dev = PCI_BDF(hose->first_busno, 0, 0);
@@ -367,7 +376,12 @@ void fsl_pci_init(struct pci_controller *hose, struct fsl_pci_info *pci_info)
 	hose->region_count++;
 
 	/* see if we are a PCIe or PCI controller */
-	pci_hose_read_config_byte(hose, dev, FSL_PCIE_CAP_ID, &pcie_cap);
+	pcie_cap_pos = pci_hose_find_capability(hose, dev, PCI_CAP_ID_EXP);
+	pci_dcr = pcie_cap_pos + 0x08;
+	pci_dsr = pcie_cap_pos + 0x0a;
+	pci_lsr = pcie_cap_pos + 0x12;
+
+	pci_hose_read_config_byte(hose, dev, pcie_cap_pos, &pcie_cap);
 
 #ifdef CONFIG_SRIO_PCIE_BOOT_MASTER
 	/* boot from PCIE --master */
@@ -406,15 +420,16 @@ void fsl_pci_init(struct pci_controller *hose, struct fsl_pci_info *pci_info)
 					 * - Master PERR (pci)
 					 * - ICCA (PCIe)
 					 */
-	pci_hose_read_config_dword(hose, dev, PCI_DCR, &temp32);
+	pci_hose_read_config_dword(hose, dev, pci_dcr, &temp32);
 	temp32 |= 0xf000e;		/* set URR, FER, NFER (but not CER) */
-	pci_hose_write_config_dword(hose, dev, PCI_DCR, temp32);
+	pci_hose_write_config_dword(hose, dev, pci_dcr, temp32);
 
 #if defined(CONFIG_FSL_PCIE_DISABLE_ASPM)
+	pci_lcr = pcie_cap_pos + 0x10;
 	temp32 = 0;
-	pci_hose_read_config_dword(hose, dev, PCI_LCR, &temp32);
+	pci_hose_read_config_dword(hose, dev, pci_lcr, &temp32);
 	temp32 &= ~0x03;		/* Disable ASPM  */
-	pci_hose_write_config_dword(hose, dev, PCI_LCR, temp32);
+	pci_hose_write_config_dword(hose, dev, pci_lcr, temp32);
 	udelay(1);
 #endif
 	if (pcie_cap == PCI_CAP_ID_EXP) {
@@ -494,9 +509,9 @@ void fsl_pci_init(struct pci_controller *hose, struct fsl_pci_info *pci_info)
 		out_be32(&pci->pme_msg_int_en, 0xffffffff);
 
 		/* Print the negotiated PCIe link width */
-		pci_hose_read_config_word(hose, dev, PCI_LSR, &temp16);
-		printf("x%d, regs @ 0x%lx\n", (temp16 & 0x3f0 ) >> 4,
-			pci_info->regs);
+		pci_hose_read_config_word(hose, dev, pci_lsr, &temp16);
+		printf("x%d gen%d, regs @ 0x%lx\n", (temp16 & 0x3f0) >> 4,
+		       (temp16 & 0xf), pci_info->regs);
 
 		hose->current_busno++; /* Start scan with secondary */
 		pciauto_prescan_setup_bridge(hose, dev, hose->current_busno);
@@ -541,9 +556,9 @@ void fsl_pci_init(struct pci_controller *hose, struct fsl_pci_info *pci_info)
 		out_be32(&pci->pme_msg_det, 0xffffffff);
 	out_be32(&pci->pedr, 0xffffffff);
 
-	pci_hose_read_config_word (hose, dev, PCI_DSR, &temp16);
+	pci_hose_read_config_word(hose, dev, pci_dsr, &temp16);
 	if (temp16) {
-		pci_hose_write_config_word(hose, dev, PCI_DSR, 0xffff);
+		pci_hose_write_config_word(hose, dev, pci_dsr, 0xffff);
 	}
 
 	pci_hose_read_config_word (hose, dev, PCI_SEC_STATUS, &temp16);
@@ -554,10 +569,12 @@ void fsl_pci_init(struct pci_controller *hose, struct fsl_pci_info *pci_info)
 
 int fsl_is_pci_agent(struct pci_controller *hose)
 {
+	int pcie_cap_pos;
 	u8 pcie_cap;
 	pci_dev_t dev = PCI_BDF(hose->first_busno, 0, 0);
 
-	pci_hose_read_config_byte(hose, dev, FSL_PCIE_CAP_ID, &pcie_cap);
+	pcie_cap_pos = pci_hose_find_capability(hose, dev, PCI_CAP_ID_EXP);
+	pci_hose_read_config_byte(hose, dev, pcie_cap_pos, &pcie_cap);
 	if (pcie_cap == PCI_CAP_ID_EXP) {
 		u8 header_type;
 
@@ -582,6 +599,7 @@ int fsl_pci_init_port(struct fsl_pci_info *pci_info,
 	volatile ccsr_fsl_pci_t *pci;
 	struct pci_region *r;
 	pci_dev_t dev = PCI_BDF(busno,0,0);
+	int pcie_cap_pos;
 	u8 pcie_cap;
 
 	pci = (ccsr_fsl_pci_t *) pci_info->regs;
@@ -631,11 +649,11 @@ int fsl_pci_init_port(struct fsl_pci_info *pci_info,
 #endif
 	}
 
-	pci_hose_read_config_byte(hose, dev, FSL_PCIE_CAP_ID, &pcie_cap);
+	pcie_cap_pos = pci_hose_find_capability(hose, dev, PCI_CAP_ID_EXP);
+	pci_hose_read_config_byte(hose, dev, pcie_cap_pos, &pcie_cap);
 	printf("PCI%s%x: Bus %02x - %02x\n", pcie_cap == PCI_CAP_ID_EXP ?
 		"e" : "", pci_info->pci_num,
 		hose->first_busno, hose->last_busno);
-
 	return(hose->last_busno + 1);
 }
 
@@ -643,13 +661,15 @@ int fsl_pci_init_port(struct fsl_pci_info *pci_info,
 void fsl_pci_config_unlock(struct pci_controller *hose)
 {
 	pci_dev_t dev = PCI_BDF(hose->first_busno,0,0);
+	int pcie_cap_pos;
 	u8 pcie_cap;
 	u16 pbfr;
 
 	if (!fsl_is_pci_agent(hose))
 		return;
 
-	pci_hose_read_config_byte(hose, dev, FSL_PCIE_CAP_ID, &pcie_cap);
+	pcie_cap_pos = pci_hose_find_capability(hose, dev, PCI_CAP_ID_EXP);
+	pci_hose_read_config_byte(hose, dev, pcie_cap_pos, &pcie_cap);
 	if (pcie_cap != 0x0) {
 		/* PCIe - set CFG_READY bit of Configuration Ready Register */
 		pci_hose_write_config_byte(hose, dev, FSL_PCIE_CFG_RDY, 0x1);
diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c
index 2c071589b4..ed113bf402 100644
--- a/drivers/pci/pci.c
+++ b/drivers/pci/pci.c
@@ -722,3 +722,68 @@ void pci_init(void)
 	/* now call board specific pci_init()... */
 	pci_init_board();
 }
+
+/* Returns the address of the requested capability structure within the
+ * device's PCI configuration space or 0 in case the device does not
+ * support it.
+ * */
+int pci_hose_find_capability(struct pci_controller *hose, pci_dev_t dev,
+			     int cap)
+{
+	int pos;
+	u8 hdr_type;
+
+	pci_hose_read_config_byte(hose, dev, PCI_HEADER_TYPE, &hdr_type);
+
+	pos = pci_hose_find_cap_start(hose, dev, hdr_type & 0x7F);
+
+	if (pos)
+		pos = pci_find_cap(hose, dev, pos, cap);
+
+	return pos;
+}
+
+/* Find the header pointer to the Capabilities*/
+int pci_hose_find_cap_start(struct pci_controller *hose, pci_dev_t dev,
+			    u8 hdr_type)
+{
+	u16 status;
+
+	pci_hose_read_config_word(hose, dev, PCI_STATUS, &status);
+
+	if (!(status & PCI_STATUS_CAP_LIST))
+		return 0;
+
+	switch (hdr_type) {
+	case PCI_HEADER_TYPE_NORMAL:
+	case PCI_HEADER_TYPE_BRIDGE:
+		return PCI_CAPABILITY_LIST;
+	case PCI_HEADER_TYPE_CARDBUS:
+		return PCI_CB_CAPABILITY_LIST;
+	default:
+		return 0;
+	}
+}
+
+int pci_find_cap(struct pci_controller *hose, pci_dev_t dev, int pos, int cap)
+{
+	int ttl = PCI_FIND_CAP_TTL;
+	u8 id;
+	u8 next_pos;
+
+	while (ttl--) {
+		pci_hose_read_config_byte(hose, dev, pos, &next_pos);
+		if (next_pos < CAP_START_POS)
+			break;
+		next_pos &= ~3;
+		pos = (int) next_pos;
+		pci_hose_read_config_byte(hose, dev,
+					  pos + PCI_CAP_LIST_ID, &id);
+		if (id == 0xff)
+			break;
+		if (id == cap)
+			return pos;
+		pos += PCI_CAP_LIST_NEXT;
+	}
+	return 0;
+}
diff --git a/drivers/pci/pci_ixp.c b/drivers/pci/pci_ixp.c
deleted file mode 100644
index d71fda2846..0000000000
--- a/drivers/pci/pci_ixp.c
+++ /dev/null
@@ -1,351 +0,0 @@
-/*
- * IXP PCI Init
- *
- * (C) Copyright 2011
- * Michael Schwingen, michael@schwingen.org
- * (C) Copyright 2004 eslab.whut.edu.cn
- * Yue Hu(huyue_whut@yahoo.com.cn), Ligong Xue(lgxue@hotmail.com)
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/processor.h>
-#include <asm/io.h>
-#include <pci.h>
-#include <asm/arch/ixp425.h>
-#include <asm/arch/ixp425pci.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-static void non_prefetch_read(unsigned int addr, unsigned int cmd,
-			      unsigned int *data);
-static void non_prefetch_write(unsigned int addr, unsigned int cmd,
-			       unsigned int data);
-
-/*define the sub vendor and subsystem to be used */
-#define IXP425_PCI_SUB_VENDOR_SYSTEM 0x00000000
-
-#define PCI_MEMORY_BUS		0x00000000
-#define PCI_MEMORY_PHY		0x00000000
-#define PCI_MEMORY_SIZE		0x04000000
-
-#define PCI_MEM_BUS		0x48000000
-#define PCI_MEM_PHY		0x00000000
-#define PCI_MEM_SIZE		0x04000000
-
-#define	PCI_IO_BUS		0x00000000
-#define PCI_IO_PHY		0x00000000
-#define PCI_IO_SIZE		0x00010000
-
-/* build address value for config sycle */
-static unsigned int pci_config_addr(pci_dev_t bdf, unsigned int reg)
-{
-	unsigned int bus = PCI_BUS(bdf);
-	unsigned int dev = PCI_DEV(bdf);
-	unsigned int func = PCI_FUNC(bdf);
-	unsigned int addr;
-
-	if (bus) { /* secondary bus, use type 1 config cycle */
-		addr = bdf | (reg & ~3) | 1;
-	} else {
-		/*
-		  primary bus, type 0 config cycle. address bits 31:28
-		  specify the device 10:8 specify the function
-		*/
-		addr = BIT((31 - dev)) | (func << 8) | (reg & ~3);
-	}
-
-	return addr;
-}
-
-static int pci_config_status(void)
-{
-	unsigned int regval;
-
-	regval = readl(PCI_CSR_BASE + PCI_ISR_OFFSET);
-	if ((regval & PCI_ISR_PFE) == 0)
-		return OK;
-
-	/* no device present, make sure that the master abort bit is reset */
-	writel(PCI_ISR_PFE, PCI_CSR_BASE + PCI_ISR_OFFSET);
-	return ERROR;
-}
-
-static int pci_ixp_hose_read_config_dword(struct pci_controller *hose,
-				   pci_dev_t bdf, int where, unsigned int *val)
-{
-	unsigned int retval;
-	unsigned int addr;
-	int stat;
-
-	debug("pci_ixp_hose_read_config_dword: bdf %x, reg %x", bdf, where);
-	/*Set the address to be read */
-	addr = pci_config_addr(bdf, where);
-	non_prefetch_read(addr, NP_CMD_CONFIGREAD, &retval);
-	*val = retval;
-
-	stat = pci_config_status();
-	if (stat < 0)
-		*val = -1;
-	debug("-> val %x, status %x\n", *val, stat);
-	return stat;
-}
-
-static int pci_ixp_hose_read_config_word(struct pci_controller *hose,
-				  pci_dev_t bdf, int where, unsigned short *val)
-{
-	unsigned int n;
-	unsigned int retval;
-	unsigned int addr;
-	unsigned int byteEnables;
-	int stat;
-
-	debug("pci_ixp_hose_read_config_word: bdf %x, reg %x", bdf, where);
-	n = where % 4;
-	/*byte enables are 4 bits active low, the position of each
-	   bit maps to the byte that it enables */
-	byteEnables =
-		(~(BIT(n) | BIT((n + 1)))) &
-		IXP425_PCI_BOTTOM_NIBBLE_OF_LONG_MASK;
-	byteEnables = byteEnables << PCI_NP_CBE_BESL;
-	/*Set the address to be read */
-	addr = pci_config_addr(bdf, where);
-	non_prefetch_read(addr, byteEnables | NP_CMD_CONFIGREAD, &retval);
-
-	/*Pick out the word we are interested in */
-	*val = retval >> (8 * n);
-
-	stat = pci_config_status();
-	if (stat < 0)
-		*val = -1;
-	debug("-> val %x, status %x\n", *val, stat);
-	return stat;
-}
-
-static int pci_ixp_hose_read_config_byte(struct pci_controller *hose,
-				  pci_dev_t bdf, int where, unsigned char *val)
-{
-	unsigned int retval;
-	unsigned int n;
-	unsigned int byteEnables;
-	unsigned int addr;
-	int stat;
-
-	debug("pci_ixp_hose_read_config_byte: bdf %x, reg %x", bdf, where);
-	n = where % 4;
-	/*byte enables are 4 bits, active low, the position of each
-	   bit maps to the byte that it enables */
-	byteEnables = (~BIT(n)) & IXP425_PCI_BOTTOM_NIBBLE_OF_LONG_MASK;
-	byteEnables = byteEnables << PCI_NP_CBE_BESL;
-
-	/*Set the address to be read */
-	addr = pci_config_addr(bdf, where);
-	non_prefetch_read(addr, byteEnables | NP_CMD_CONFIGREAD, &retval);
-	/*Pick out the byte we are interested in */
-	*val = retval >> (8 * n);
-
-	stat = pci_config_status();
-	if (stat < 0)
-		*val = -1;
-	debug("-> val %x, status %x\n", *val, stat);
-	return stat;
-}
-
-static int pci_ixp_hose_write_config_byte(struct pci_controller *hose,
-				   pci_dev_t bdf, int where, unsigned char val)
-{
-	unsigned int addr;
-	unsigned int byteEnables;
-	unsigned int n;
-	unsigned int ldata;
-	int stat;
-
-	debug("pci_ixp_hose_write_config_byte: bdf %x, reg %x, val %x",
-	      bdf, where, val);
-	n = where % 4;
-	/*byte enables are 4 bits active low, the position of each
-	   bit maps to the byte that it enables */
-	byteEnables = (~BIT(n)) & IXP425_PCI_BOTTOM_NIBBLE_OF_LONG_MASK;
-	byteEnables = byteEnables << PCI_NP_CBE_BESL;
-	ldata = val << (8 * n);
-	/*Set the address to be written */
-	addr = pci_config_addr(bdf, where);
-	non_prefetch_write(addr, byteEnables | NP_CMD_CONFIGWRITE, ldata);
-
-	stat = pci_config_status();
-	debug("-> status %x\n", stat);
-	return stat;
-}
-
-static int pci_ixp_hose_write_config_word(struct pci_controller *hose,
-				   pci_dev_t bdf, int where, unsigned short val)
-{
-	unsigned int addr;
-	unsigned int byteEnables;
-	unsigned int n;
-	unsigned int ldata;
-	int stat;
-
-	debug("pci_ixp_hose_write_config_word: bdf %x, reg %x, val %x",
-	      bdf, where, val);
-	n = where % 4;
-	/*byte enables are 4 bits active low, the position of each
-	   bit maps to the byte that it enables */
-	byteEnables =
-		(~(BIT(n) | BIT((n + 1)))) &
-		IXP425_PCI_BOTTOM_NIBBLE_OF_LONG_MASK;
-	byteEnables = byteEnables << PCI_NP_CBE_BESL;
-	ldata = val << (8 * n);
-	/*Set the address to be written */
-	addr = pci_config_addr(bdf, where);
-	non_prefetch_write(addr, byteEnables | NP_CMD_CONFIGWRITE, ldata);
-
-	stat = pci_config_status();
-	debug("-> status %x\n", stat);
-	return stat;
-}
-
-static int pci_ixp_hose_write_config_dword(struct pci_controller *hose,
-				    pci_dev_t bdf, int where, unsigned int val)
-{
-	unsigned int addr;
-	int stat;
-
-	debug("pci_ixp_hose_write_config_dword: bdf %x, reg %x, val %x",
-	      bdf, where, val);
-	/*Set the address to be written */
-	addr = pci_config_addr(bdf, where);
-	non_prefetch_write(addr, NP_CMD_CONFIGWRITE, val);
-
-	stat = pci_config_status();
-	debug("-> status %x\n", stat);
-	return stat;
-}
-
-static void non_prefetch_read(unsigned int addr,
-		       unsigned int cmd, unsigned int *data)
-{
-	writel(addr, PCI_CSR_BASE + PCI_NP_AD_OFFSET);
-
-	/*set up and execute the read */
-	writel(cmd, PCI_CSR_BASE + PCI_NP_CBE_OFFSET);
-
-	/*The result of the read is now in np_rdata */
-	*data = readl(PCI_CSR_BASE + PCI_NP_RDATA_OFFSET);
-
-	return;
-}
-
-static void non_prefetch_write(unsigned int addr,
-			unsigned int cmd, unsigned int data)
-{
-
-	writel(addr, PCI_CSR_BASE + PCI_NP_AD_OFFSET);
-	/*set up the write */
-	writel(cmd, PCI_CSR_BASE + PCI_NP_CBE_OFFSET);
-	/*Execute the write by writing to NP_WDATA */
-	writel(data, PCI_CSR_BASE + PCI_NP_WDATA_OFFSET);
-
-	return;
-}
-
-static void crp_write(unsigned int offset, unsigned int data)
-{
-	/*
-	 * The CRP address register bit 16 indicates that we want to do a
-	 * write
-	 */
-	writel(PCI_CRP_WRITE | offset, PCI_CSR_BASE + PCI_CRP_AD_CBE_OFFSET);
-	writel(data, PCI_CSR_BASE + PCI_CRP_WDATA_OFFSET);
-}
-
-void pci_ixp_init(struct pci_controller *hose)
-{
-	unsigned int csr;
-
-	/*
-	 * Specify that the AHB bus is operating in big endian mode. Set up
-	 * byte lane swapping between little-endian PCI and the big-endian
-	 * AHB bus
-	 */
-#ifdef __ARMEB__
-	csr =  PCI_CSR_ABE | PCI_CSR_PDS | PCI_CSR_ADS;
-#else
-	csr = PCI_CSR_ABE;
-#endif
-	writel(csr, PCI_CSR_BASE + PCI_CSR_OFFSET);
-
-	writel(0, PCI_CSR_BASE + PCI_INTEN_OFFSET);
-
-	/*
-	 * We configure the PCI inbound memory windows to be
-	 * 1:1 mapped to SDRAM
-	 */
-	crp_write(PCI_CFG_BASE_ADDRESS_0, 0x00000000);
-	crp_write(PCI_CFG_BASE_ADDRESS_1, 0x01000000);
-	crp_write(PCI_CFG_BASE_ADDRESS_2, 0x02000000);
-	crp_write(PCI_CFG_BASE_ADDRESS_3, 0x03000000);
-
-	/*
-	 * Enable CSR window at 64 MiB to allow PCI masters
-	 * to continue prefetching past 64 MiB boundary.
-	 */
-	crp_write(PCI_CFG_BASE_ADDRESS_4, 0x04000000);
-	/*
-	 * Enable the IO window to be way up high, at 0xfffffc00
-	 */
-	crp_write(PCI_CFG_BASE_ADDRESS_5, 0xfffffc01);
-
-	/*Setup PCI-AHB and AHB-PCI address mappings */
-	writel(0x00010203, PCI_CSR_BASE + PCI_AHBMEMBASE_OFFSET);
-
-	writel(0x00000000, PCI_CSR_BASE + PCI_AHBIOBASE_OFFSET);
-
-	writel(0x48494a4b, PCI_CSR_BASE + PCI_PCIMEMBASE_OFFSET);
-
-	crp_write(PCI_CFG_SUB_VENDOR_ID, IXP425_PCI_SUB_VENDOR_SYSTEM);
-
-	crp_write(PCI_CFG_COMMAND, PCI_CFG_CMD_MAE | PCI_CFG_CMD_BME);
-	udelay(1000);
-
-	/* clear error bits in status register */
-	writel(PCI_ISR_PSE | PCI_ISR_PFE | PCI_ISR_PPE | PCI_ISR_AHBE,
-	       PCI_CSR_BASE + PCI_ISR_OFFSET);
-
-	/*
-	 * Set Initialize Complete in PCI Control Register: allow IXP4XX to
-	 * respond to PCI configuration cycles.
-	 */
-	csr |= PCI_CSR_IC;
-	writel(csr, PCI_CSR_BASE + PCI_CSR_OFFSET);
-
-	hose->first_busno = 0;
-	hose->last_busno = 0;
-
-	/* System memory space */
-	pci_set_region(hose->regions + 0,
-		       PCI_MEMORY_BUS,
-		       PCI_MEMORY_PHY, PCI_MEMORY_SIZE, PCI_REGION_SYS_MEMORY);
-
-	/* PCI memory space */
-	pci_set_region(hose->regions + 1,
-		       PCI_MEM_BUS,
-		       PCI_MEM_PHY, PCI_MEM_SIZE, PCI_REGION_MEM);
-	/* PCI I/O space */
-	pci_set_region(hose->regions + 2,
-		       PCI_IO_BUS, PCI_IO_PHY, PCI_IO_SIZE, PCI_REGION_IO);
-
-	hose->region_count = 3;
-
-	pci_set_ops(hose,
-		    pci_ixp_hose_read_config_byte,
-		    pci_ixp_hose_read_config_word,
-		    pci_ixp_hose_read_config_dword,
-		    pci_ixp_hose_write_config_byte,
-		    pci_ixp_hose_write_config_word,
-		    pci_ixp_hose_write_config_dword);
-
-	pci_register_hose(hose);
-	hose->last_busno = pci_hose_scan(hose);
-}
diff --git a/drivers/pci/pci_msc01.c b/drivers/pci/pci_msc01.c
new file mode 100644
index 0000000000..284ffa09b6
--- /dev/null
+++ b/drivers/pci/pci_msc01.c
@@ -0,0 +1,125 @@
+/*
+ * Copyright (C) 2013 Imagination Technologies
+ * Author: Paul Burton <paul.burton@imgtec.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <msc01.h>
+#include <pci.h>
+#include <pci_msc01.h>
+#include <asm/io.h>
+
+#define PCI_ACCESS_READ  0
+#define PCI_ACCESS_WRITE 1
+
+struct msc01_pci_controller {
+	struct pci_controller hose;
+	void *base;
+};
+
+static inline struct msc01_pci_controller *
+hose_to_msc01(struct pci_controller *hose)
+{
+	return container_of(hose, struct msc01_pci_controller, hose);
+}
+
+static int msc01_config_access(struct msc01_pci_controller *msc01,
+			       unsigned char access_type, pci_dev_t bdf,
+			       int where, u32 *data)
+{
+	const u32 aborts = MSC01_PCI_INTSTAT_MA_MSK | MSC01_PCI_INTSTAT_TA_MSK;
+	void *intstat = msc01->base + MSC01_PCI_INTSTAT_OFS;
+	void *cfgdata = msc01->base + MSC01_PCI_CFGDATA_OFS;
+	unsigned int bus = PCI_BUS(bdf);
+	unsigned int dev = PCI_DEV(bdf);
+	unsigned int devfn = PCI_DEV(bdf) << 3 | PCI_FUNC(bdf);
+
+	/* clear abort status */
+	__raw_writel(aborts, intstat);
+
+	/* setup address */
+	__raw_writel((bus << MSC01_PCI_CFGADDR_BNUM_SHF) |
+		     (dev << MSC01_PCI_CFGADDR_DNUM_SHF) |
+		     (devfn << MSC01_PCI_CFGADDR_FNUM_SHF) |
+		     ((where / 4) << MSC01_PCI_CFGADDR_RNUM_SHF),
+		     msc01->base + MSC01_PCI_CFGADDR_OFS);
+
+	/* perform access */
+	if (access_type == PCI_ACCESS_WRITE)
+		__raw_writel(*data, cfgdata);
+	else
+		*data = __raw_readl(cfgdata);
+
+	/* check for aborts */
+	if (__raw_readl(intstat) & aborts) {
+		/* clear abort status */
+		__raw_writel(aborts, intstat);
+		return -1;
+	}
+
+	return 0;
+}
+
+static int msc01_read_config_dword(struct pci_controller *hose, pci_dev_t dev,
+				   int where, u32 *value)
+{
+	struct msc01_pci_controller *msc01 = hose_to_msc01(hose);
+
+	*value = 0xffffffff;
+	return msc01_config_access(msc01, PCI_ACCESS_READ, dev, where, value);
+}
+
+static int msc01_write_config_dword(struct pci_controller *hose, pci_dev_t dev,
+				    int where, u32 value)
+{
+	struct msc01_pci_controller *gt = hose_to_msc01(hose);
+	u32 data = value;
+
+	return msc01_config_access(gt, PCI_ACCESS_WRITE, dev, where, &data);
+}
+
+void msc01_pci_init(void *base, unsigned long sys_bus, unsigned long sys_phys,
+		    unsigned long sys_size, unsigned long mem_bus,
+		    unsigned long mem_phys, unsigned long mem_size,
+		    unsigned long io_bus, unsigned long io_phys,
+		    unsigned long io_size)
+{
+	static struct msc01_pci_controller global_msc01;
+	struct msc01_pci_controller *msc01;
+	struct pci_controller *hose;
+
+	msc01 = &global_msc01;
+	msc01->base = base;
+
+	hose = &msc01->hose;
+
+	hose->first_busno = 0;
+	hose->last_busno = 0;
+
+	/* System memory space */
+	pci_set_region(&hose->regions[0], sys_bus, sys_phys, sys_size,
+		       PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
+
+	/* PCI memory space */
+	pci_set_region(&hose->regions[1], mem_bus, mem_phys, mem_size,
+		       PCI_REGION_MEM);
+
+	/* PCI I/O space */
+	pci_set_region(&hose->regions[2], io_bus, io_phys, io_size,
+		       PCI_REGION_IO);
+
+	hose->region_count = 3;
+
+	pci_set_ops(hose,
+		    pci_hose_read_config_byte_via_dword,
+		    pci_hose_read_config_word_via_dword,
+		    msc01_read_config_dword,
+		    pci_hose_write_config_byte_via_dword,
+		    pci_hose_write_config_word_via_dword,
+		    msc01_write_config_dword);
+
+	pci_register_hose(hose);
+	hose->last_busno = pci_hose_scan(hose);
+}
diff --git a/drivers/pci/pcie_imx.c b/drivers/pci/pcie_imx.c
new file mode 100644
index 0000000000..c48737e6c9
--- /dev/null
+++ b/drivers/pci/pcie_imx.c
@@ -0,0 +1,617 @@
+/*
+ * Freescale i.MX6 PCI Express Root-Complex driver
+ *
+ * Copyright (C) 2013 Marek Vasut <marex@denx.de>
+ *
+ * Based on upstream Linux kernel driver:
+ * pci-imx6.c:		Sean Cross <xobs@kosagi.com>
+ * pcie-designware.c:	Jingoo Han <jg1.han@samsung.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0
+ */
+
+#include <common.h>
+#include <pci.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/iomux.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/gpio.h>
+#include <asm/io.h>
+#include <linux/sizes.h>
+#include <errno.h>
+
+#define PCI_ACCESS_READ  0
+#define PCI_ACCESS_WRITE 1
+
+#define MX6_DBI_ADDR	0x01ffc000
+#define MX6_DBI_SIZE	0x4000
+#define MX6_IO_ADDR	0x01000000
+#define MX6_IO_SIZE	0x100000
+#define MX6_MEM_ADDR	0x01100000
+#define MX6_MEM_SIZE	0xe00000
+#define MX6_ROOT_ADDR	0x01f00000
+#define MX6_ROOT_SIZE	0xfc000
+
+/* PCIe Port Logic registers (memory-mapped) */
+#define PL_OFFSET 0x700
+#define PCIE_PHY_DEBUG_R0 (PL_OFFSET + 0x28)
+#define PCIE_PHY_DEBUG_R1 (PL_OFFSET + 0x2c)
+#define PCIE_PHY_DEBUG_R1_LINK_UP		(1 << 4)
+#define PCIE_PHY_DEBUG_R1_LINK_IN_TRAINING	(1 << 29)
+
+#define PCIE_PHY_CTRL (PL_OFFSET + 0x114)
+#define PCIE_PHY_CTRL_DATA_LOC 0
+#define PCIE_PHY_CTRL_CAP_ADR_LOC 16
+#define PCIE_PHY_CTRL_CAP_DAT_LOC 17
+#define PCIE_PHY_CTRL_WR_LOC 18
+#define PCIE_PHY_CTRL_RD_LOC 19
+
+#define PCIE_PHY_STAT (PL_OFFSET + 0x110)
+#define PCIE_PHY_STAT_DATA_LOC 0
+#define PCIE_PHY_STAT_ACK_LOC 16
+
+/* PHY registers (not memory-mapped) */
+#define PCIE_PHY_RX_ASIC_OUT 0x100D
+
+#define PHY_RX_OVRD_IN_LO 0x1005
+#define PHY_RX_OVRD_IN_LO_RX_DATA_EN (1 << 5)
+#define PHY_RX_OVRD_IN_LO_RX_PLL_EN (1 << 3)
+
+/* iATU registers */
+#define PCIE_ATU_VIEWPORT		0x900
+#define PCIE_ATU_REGION_INBOUND		(0x1 << 31)
+#define PCIE_ATU_REGION_OUTBOUND	(0x0 << 31)
+#define PCIE_ATU_REGION_INDEX1		(0x1 << 0)
+#define PCIE_ATU_REGION_INDEX0		(0x0 << 0)
+#define PCIE_ATU_CR1			0x904
+#define PCIE_ATU_TYPE_MEM		(0x0 << 0)
+#define PCIE_ATU_TYPE_IO		(0x2 << 0)
+#define PCIE_ATU_TYPE_CFG0		(0x4 << 0)
+#define PCIE_ATU_TYPE_CFG1		(0x5 << 0)
+#define PCIE_ATU_CR2			0x908
+#define PCIE_ATU_ENABLE			(0x1 << 31)
+#define PCIE_ATU_BAR_MODE_ENABLE	(0x1 << 30)
+#define PCIE_ATU_LOWER_BASE		0x90C
+#define PCIE_ATU_UPPER_BASE		0x910
+#define PCIE_ATU_LIMIT			0x914
+#define PCIE_ATU_LOWER_TARGET		0x918
+#define PCIE_ATU_BUS(x)			(((x) & 0xff) << 24)
+#define PCIE_ATU_DEV(x)			(((x) & 0x1f) << 19)
+#define PCIE_ATU_FUNC(x)		(((x) & 0x7) << 16)
+#define PCIE_ATU_UPPER_TARGET		0x91C
+
+/*
+ * PHY access functions
+ */
+static int pcie_phy_poll_ack(void __iomem *dbi_base, int exp_val)
+{
+	u32 val;
+	u32 max_iterations = 10;
+	u32 wait_counter = 0;
+
+	do {
+		val = readl(dbi_base + PCIE_PHY_STAT);
+		val = (val >> PCIE_PHY_STAT_ACK_LOC) & 0x1;
+		wait_counter++;
+
+		if (val == exp_val)
+			return 0;
+
+		udelay(1);
+	} while (wait_counter < max_iterations);
+
+	return -ETIMEDOUT;
+}
+
+static int pcie_phy_wait_ack(void __iomem *dbi_base, int addr)
+{
+	u32 val;
+	int ret;
+
+	val = addr << PCIE_PHY_CTRL_DATA_LOC;
+	writel(val, dbi_base + PCIE_PHY_CTRL);
+
+	val |= (0x1 << PCIE_PHY_CTRL_CAP_ADR_LOC);
+	writel(val, dbi_base + PCIE_PHY_CTRL);
+
+	ret = pcie_phy_poll_ack(dbi_base, 1);
+	if (ret)
+		return ret;
+
+	val = addr << PCIE_PHY_CTRL_DATA_LOC;
+	writel(val, dbi_base + PCIE_PHY_CTRL);
+
+	ret = pcie_phy_poll_ack(dbi_base, 0);
+	if (ret)
+		return ret;
+
+	return 0;
+}
+
+/* Read from the 16-bit PCIe PHY control registers (not memory-mapped) */
+static int pcie_phy_read(void __iomem *dbi_base, int addr , int *data)
+{
+	u32 val, phy_ctl;
+	int ret;
+
+	ret = pcie_phy_wait_ack(dbi_base, addr);
+	if (ret)
+		return ret;
+
+	/* assert Read signal */
+	phy_ctl = 0x1 << PCIE_PHY_CTRL_RD_LOC;
+	writel(phy_ctl, dbi_base + PCIE_PHY_CTRL);
+
+	ret = pcie_phy_poll_ack(dbi_base, 1);
+	if (ret)
+		return ret;
+
+	val = readl(dbi_base + PCIE_PHY_STAT);
+	*data = val & 0xffff;
+
+	/* deassert Read signal */
+	writel(0x00, dbi_base + PCIE_PHY_CTRL);
+
+	ret = pcie_phy_poll_ack(dbi_base, 0);
+	if (ret)
+		return ret;
+
+	return 0;
+}
+
+static int pcie_phy_write(void __iomem *dbi_base, int addr, int data)
+{
+	u32 var;
+	int ret;
+
+	/* write addr */
+	/* cap addr */
+	ret = pcie_phy_wait_ack(dbi_base, addr);
+	if (ret)
+		return ret;
+
+	var = data << PCIE_PHY_CTRL_DATA_LOC;
+	writel(var, dbi_base + PCIE_PHY_CTRL);
+
+	/* capture data */
+	var |= (0x1 << PCIE_PHY_CTRL_CAP_DAT_LOC);
+	writel(var, dbi_base + PCIE_PHY_CTRL);
+
+	ret = pcie_phy_poll_ack(dbi_base, 1);
+	if (ret)
+		return ret;
+
+	/* deassert cap data */
+	var = data << PCIE_PHY_CTRL_DATA_LOC;
+	writel(var, dbi_base + PCIE_PHY_CTRL);
+
+	/* wait for ack de-assertion */
+	ret = pcie_phy_poll_ack(dbi_base, 0);
+	if (ret)
+		return ret;
+
+	/* assert wr signal */
+	var = 0x1 << PCIE_PHY_CTRL_WR_LOC;
+	writel(var, dbi_base + PCIE_PHY_CTRL);
+
+	/* wait for ack */
+	ret = pcie_phy_poll_ack(dbi_base, 1);
+	if (ret)
+		return ret;
+
+	/* deassert wr signal */
+	var = data << PCIE_PHY_CTRL_DATA_LOC;
+	writel(var, dbi_base + PCIE_PHY_CTRL);
+
+	/* wait for ack de-assertion */
+	ret = pcie_phy_poll_ack(dbi_base, 0);
+	if (ret)
+		return ret;
+
+	writel(0x0, dbi_base + PCIE_PHY_CTRL);
+
+	return 0;
+}
+
+static int imx6_pcie_link_up(void)
+{
+	u32 rc, ltssm;
+	int rx_valid, temp;
+
+	/* link is debug bit 36, debug register 1 starts at bit 32 */
+	rc = readl(MX6_DBI_ADDR + PCIE_PHY_DEBUG_R1);
+	if ((rc & PCIE_PHY_DEBUG_R1_LINK_UP) &&
+	    !(rc & PCIE_PHY_DEBUG_R1_LINK_IN_TRAINING))
+		return -EAGAIN;
+
+	/*
+	 * From L0, initiate MAC entry to gen2 if EP/RC supports gen2.
+	 * Wait 2ms (LTSSM timeout is 24ms, PHY lock is ~5us in gen2).
+	 * If (MAC/LTSSM.state == Recovery.RcvrLock)
+	 * && (PHY/rx_valid==0) then pulse PHY/rx_reset. Transition
+	 * to gen2 is stuck
+	 */
+	pcie_phy_read((void *)MX6_DBI_ADDR, PCIE_PHY_RX_ASIC_OUT, &rx_valid);
+	ltssm = readl(MX6_DBI_ADDR + PCIE_PHY_DEBUG_R0) & 0x3F;
+
+	if (rx_valid & 0x01)
+		return 0;
+
+	if (ltssm != 0x0d)
+		return 0;
+
+	printf("transition to gen2 is stuck, reset PHY!\n");
+
+	pcie_phy_read((void *)MX6_DBI_ADDR, PHY_RX_OVRD_IN_LO, &temp);
+	temp |= (PHY_RX_OVRD_IN_LO_RX_DATA_EN | PHY_RX_OVRD_IN_LO_RX_PLL_EN);
+	pcie_phy_write((void *)MX6_DBI_ADDR, PHY_RX_OVRD_IN_LO, temp);
+
+	udelay(3000);
+
+	pcie_phy_read((void *)MX6_DBI_ADDR, PHY_RX_OVRD_IN_LO, &temp);
+	temp &= ~(PHY_RX_OVRD_IN_LO_RX_DATA_EN | PHY_RX_OVRD_IN_LO_RX_PLL_EN);
+	pcie_phy_write((void *)MX6_DBI_ADDR, PHY_RX_OVRD_IN_LO, temp);
+
+	return 0;
+}
+
+/*
+ * iATU region setup
+ */
+static int imx_pcie_regions_setup(void)
+{
+	/*
+	 * i.MX6 defines 16MB in the AXI address map for PCIe.
+	 *
+	 * That address space excepted the pcie registers is
+	 * split and defined into different regions by iATU,
+	 * with sizes and offsets as follows:
+	 *
+	 * 0x0100_0000 --- 0x010F_FFFF 1MB IORESOURCE_IO
+	 * 0x0110_0000 --- 0x01EF_FFFF 14MB IORESOURCE_MEM
+	 * 0x01F0_0000 --- 0x01FF_FFFF 1MB Cfg + Registers
+	 */
+
+	/* CMD reg:I/O space, MEM space, and Bus Master Enable */
+	setbits_le32(MX6_DBI_ADDR | PCI_COMMAND,
+		     PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
+
+	/* Set the CLASS_REV of RC CFG header to PCI_CLASS_BRIDGE_PCI */
+	setbits_le32(MX6_DBI_ADDR + PCI_CLASS_REVISION,
+		     PCI_CLASS_BRIDGE_PCI << 16);
+
+	/* Region #0 is used for Outbound CFG space access. */
+	writel(0, MX6_DBI_ADDR + PCIE_ATU_VIEWPORT);
+
+	writel(MX6_ROOT_ADDR, MX6_DBI_ADDR + PCIE_ATU_LOWER_BASE);
+	writel(0, MX6_DBI_ADDR + PCIE_ATU_UPPER_BASE);
+	writel(MX6_ROOT_ADDR + MX6_ROOT_SIZE, MX6_DBI_ADDR + PCIE_ATU_LIMIT);
+
+	writel(0, MX6_DBI_ADDR + PCIE_ATU_LOWER_TARGET);
+	writel(0, MX6_DBI_ADDR + PCIE_ATU_UPPER_TARGET);
+	writel(PCIE_ATU_TYPE_CFG0, MX6_DBI_ADDR + PCIE_ATU_CR1);
+	writel(PCIE_ATU_ENABLE, MX6_DBI_ADDR + PCIE_ATU_CR2);
+
+	return 0;
+}
+
+/*
+ * PCI Express accessors
+ */
+static uint32_t get_bus_address(pci_dev_t d, int where)
+{
+	uint32_t va_address;
+
+	/* Reconfigure Region #0 */
+	writel(0, MX6_DBI_ADDR + PCIE_ATU_VIEWPORT);
+
+	if (PCI_BUS(d) < 2)
+		writel(PCIE_ATU_TYPE_CFG0, MX6_DBI_ADDR + PCIE_ATU_CR1);
+	else
+		writel(PCIE_ATU_TYPE_CFG1, MX6_DBI_ADDR + PCIE_ATU_CR1);
+
+	if (PCI_BUS(d) == 0) {
+		va_address = MX6_DBI_ADDR;
+	} else {
+		writel(d << 8, MX6_DBI_ADDR + PCIE_ATU_LOWER_TARGET);
+		va_address = MX6_IO_ADDR + SZ_16M - SZ_1M;
+	}
+
+	va_address += (where & ~0x3);
+
+	return va_address;
+}
+
+static int imx_pcie_addr_valid(pci_dev_t d)
+{
+	if ((PCI_BUS(d) == 0) && (PCI_DEV(d) > 1))
+		return -EINVAL;
+	if ((PCI_BUS(d) == 1) && (PCI_DEV(d) > 0))
+		return -EINVAL;
+	return 0;
+}
+
+/*
+ * Replace the original ARM DABT handler with a simple jump-back one.
+ *
+ * The problem here is that if we have a PCIe bridge attached to this PCIe
+ * controller, but no PCIe device is connected to the bridges' downstream
+ * port, the attempt to read/write from/to the config space will produce
+ * a DABT. This is a behavior of the controller and can not be disabled
+ * unfortuatelly.
+ *
+ * To work around the problem, we backup the current DABT handler address
+ * and replace it with our own DABT handler, which only bounces right back
+ * into the code.
+ */
+static void imx_pcie_fix_dabt_handler(bool set)
+{
+	extern uint32_t *_data_abort;
+	uint32_t *data_abort_addr = (uint32_t *)&_data_abort;
+
+	static const uint32_t data_abort_bounce_handler = 0xe25ef004;
+	uint32_t data_abort_bounce_addr = (uint32_t)&data_abort_bounce_handler;
+
+	static uint32_t data_abort_backup;
+
+	if (set) {
+		data_abort_backup = *data_abort_addr;
+		*data_abort_addr = data_abort_bounce_addr;
+	} else {
+		*data_abort_addr = data_abort_backup;
+	}
+}
+
+static int imx_pcie_read_config(struct pci_controller *hose, pci_dev_t d,
+				int where, u32 *val)
+{
+	uint32_t va_address;
+	int ret;
+
+	ret = imx_pcie_addr_valid(d);
+	if (ret) {
+		*val = 0xffffffff;
+		return ret;
+	}
+
+	va_address = get_bus_address(d, where);
+
+	/*
+	 * Read the PCIe config space. We must replace the DABT handler
+	 * here in case we got data abort from the PCIe controller, see
+	 * imx_pcie_fix_dabt_handler() description. Note that writing the
+	 * "val" with valid value is also imperative here as in case we
+	 * did got DABT, the val would contain random value.
+	 */
+	imx_pcie_fix_dabt_handler(true);
+	writel(0xffffffff, val);
+	*val = readl(va_address);
+	imx_pcie_fix_dabt_handler(false);
+
+	return 0;
+}
+
+static int imx_pcie_write_config(struct pci_controller *hose, pci_dev_t d,
+			int where, u32 val)
+{
+	uint32_t va_address = 0;
+	int ret;
+
+	ret = imx_pcie_addr_valid(d);
+	if (ret)
+		return ret;
+
+	va_address = get_bus_address(d, where);
+
+	/*
+	 * Write the PCIe config space. We must replace the DABT handler
+	 * here in case we got data abort from the PCIe controller, see
+	 * imx_pcie_fix_dabt_handler() description.
+	 */
+	imx_pcie_fix_dabt_handler(true);
+	writel(val, va_address);
+	imx_pcie_fix_dabt_handler(false);
+
+	return 0;
+}
+
+/*
+ * Initial bus setup
+ */
+static int imx6_pcie_assert_core_reset(void)
+{
+	struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
+
+	setbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_TEST_POWERDOWN);
+	clrbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_REF_SSP_EN);
+
+	return 0;
+}
+
+static int imx6_pcie_init_phy(void)
+{
+	struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
+
+	clrbits_le32(&iomuxc_regs->gpr[12], IOMUXC_GPR12_APPS_LTSSM_ENABLE);
+
+	clrsetbits_le32(&iomuxc_regs->gpr[12],
+			IOMUXC_GPR12_DEVICE_TYPE_MASK,
+			IOMUXC_GPR12_DEVICE_TYPE_RC);
+	clrsetbits_le32(&iomuxc_regs->gpr[12],
+			IOMUXC_GPR12_LOS_LEVEL_MASK,
+			IOMUXC_GPR12_LOS_LEVEL_9);
+
+	writel((0x0 << IOMUXC_GPR8_PCS_TX_DEEMPH_GEN1_OFFSET) |
+	       (0x0 << IOMUXC_GPR8_PCS_TX_DEEMPH_GEN2_3P5DB_OFFSET) |
+	       (20 << IOMUXC_GPR8_PCS_TX_DEEMPH_GEN2_6DB_OFFSET) |
+	       (127 << IOMUXC_GPR8_PCS_TX_SWING_FULL_OFFSET) |
+	       (127 << IOMUXC_GPR8_PCS_TX_SWING_LOW_OFFSET),
+	       &iomuxc_regs->gpr[8]);
+
+	return 0;
+}
+
+__weak int imx6_pcie_toggle_power(void)
+{
+#ifdef CONFIG_PCIE_IMX_POWER_GPIO
+	gpio_direction_output(CONFIG_PCIE_IMX_POWER_GPIO, 0);
+	mdelay(20);
+	gpio_set_value(CONFIG_PCIE_IMX_POWER_GPIO, 1);
+	mdelay(20);
+#endif
+	return 0;
+}
+
+__weak int imx6_pcie_toggle_reset(void)
+{
+	/*
+	 * See 'PCI EXPRESS BASE SPECIFICATION, REV 3.0, SECTION 6.6.1'
+	 * for detailed understanding of the PCIe CR reset logic.
+	 *
+	 * The PCIe #PERST reset line _MUST_ be connected, otherwise your
+	 * design does not conform to the specification. You must wait at
+	 * least 20 mS after de-asserting the #PERST so the EP device can
+	 * do self-initialisation.
+	 *
+	 * In case your #PERST pin is connected to a plain GPIO pin of the
+	 * CPU, you can define CONFIG_PCIE_IMX_PERST_GPIO in your board's
+	 * configuration file and the condition below will handle the rest
+	 * of the reset toggling.
+	 *
+	 * In case your #PERST toggling logic is more complex, for example
+	 * connected via CPLD or somesuch, you can override this function
+	 * in your board file and implement reset logic as needed. You must
+	 * not forget to wait at least 20 mS after de-asserting #PERST in
+	 * this case either though.
+	 *
+	 * In case your #PERST line of the PCIe EP device is not connected
+	 * at all, your design is broken and you should fix your design,
+	 * otherwise you will observe problems like for example the link
+	 * not coming up after rebooting the system back from running Linux
+	 * that uses the PCIe as well OR the PCIe link might not come up in
+	 * Linux at all in the first place since it's in some non-reset
+	 * state due to being previously used in U-Boot.
+	 */
+#ifdef CONFIG_PCIE_IMX_PERST_GPIO
+	gpio_direction_output(CONFIG_PCIE_IMX_PERST_GPIO, 0);
+	mdelay(20);
+	gpio_set_value(CONFIG_PCIE_IMX_PERST_GPIO, 1);
+	mdelay(20);
+#else
+	puts("WARNING: Make sure the PCIe #PERST line is connected!\n");
+#endif
+	return 0;
+}
+
+static int imx6_pcie_deassert_core_reset(void)
+{
+	struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
+
+	imx6_pcie_toggle_power();
+
+	/* Enable PCIe */
+	clrbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_TEST_POWERDOWN);
+	setbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_REF_SSP_EN);
+
+	enable_pcie_clock();
+
+	/*
+	 * Wait for the clock to settle a bit, when the clock are sourced
+	 * from the CPU, we need about 30mS to settle.
+	 */
+	mdelay(50);
+
+	imx6_pcie_toggle_reset();
+
+	return 0;
+}
+
+static int imx_pcie_link_up(void)
+{
+	struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
+	uint32_t tmp;
+	int count = 0;
+
+	imx6_pcie_assert_core_reset();
+	imx6_pcie_init_phy();
+	imx6_pcie_deassert_core_reset();
+
+	imx_pcie_regions_setup();
+
+	/*
+	 * FIXME: Force the PCIe RC to Gen1 operation
+	 * The RC must be forced into Gen1 mode before bringing the link
+	 * up, otherwise no downstream devices are detected. After the
+	 * link is up, a managed Gen1->Gen2 transition can be initiated.
+	 */
+	tmp = readl(MX6_DBI_ADDR + 0x7c);
+	tmp &= ~0xf;
+	tmp |= 0x1;
+	writel(tmp, MX6_DBI_ADDR + 0x7c);
+
+	/* LTSSM enable, starting link. */
+	setbits_le32(&iomuxc_regs->gpr[12], IOMUXC_GPR12_APPS_LTSSM_ENABLE);
+
+	while (!imx6_pcie_link_up()) {
+		udelay(10);
+		count++;
+		if (count >= 2000) {
+			debug("phy link never came up\n");
+			debug("DEBUG_R0: 0x%08x, DEBUG_R1: 0x%08x\n",
+			      readl(MX6_DBI_ADDR + PCIE_PHY_DEBUG_R0),
+			      readl(MX6_DBI_ADDR + PCIE_PHY_DEBUG_R1));
+			return -EINVAL;
+		}
+	}
+
+	return 0;
+}
+
+void imx_pcie_init(void)
+{
+	/* Static instance of the controller. */
+	static struct pci_controller	pcc;
+	struct pci_controller		*hose = &pcc;
+	int ret;
+
+	memset(&pcc, 0, sizeof(pcc));
+
+	/* PCI I/O space */
+	pci_set_region(&hose->regions[0],
+		       MX6_IO_ADDR, MX6_IO_ADDR,
+		       MX6_IO_SIZE, PCI_REGION_IO);
+
+	/* PCI memory space */
+	pci_set_region(&hose->regions[1],
+		       MX6_MEM_ADDR, MX6_MEM_ADDR,
+		       MX6_MEM_SIZE, PCI_REGION_MEM);
+
+	/* System memory space */
+	pci_set_region(&hose->regions[2],
+		       MMDC0_ARB_BASE_ADDR, MMDC0_ARB_BASE_ADDR,
+		       0xefffffff, PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
+
+	hose->region_count = 3;
+
+	pci_set_ops(hose,
+		    pci_hose_read_config_byte_via_dword,
+		    pci_hose_read_config_word_via_dword,
+		    imx_pcie_read_config,
+		    pci_hose_write_config_byte_via_dword,
+		    pci_hose_write_config_word_via_dword,
+		    imx_pcie_write_config);
+
+	/* Start the controller. */
+	ret = imx_pcie_link_up();
+
+	if (!ret) {
+		pci_register_hose(hose);
+		hose->last_busno = pci_hose_scan(hose);
+	}
+}
+
+/* Probe function. */
+void pci_init_board(void)
+{
+	imx_pcie_init();
+}
diff --git a/drivers/pcmcia/Makefile b/drivers/pcmcia/Makefile
index 80a132eb4b..ae3cafbea4 100644
--- a/drivers/pcmcia/Makefile
+++ b/drivers/pcmcia/Makefile
@@ -5,31 +5,9 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	:= $(obj)libpcmcia.o
-
-COBJS-$(CONFIG_I82365) += i82365.o
-COBJS-$(CONFIG_8xx) += mpc8xx_pcmcia.o
-COBJS-y += rpx_pcmcia.o
-COBJS-$(CONFIG_IDE_TI_CARDBUS) += ti_pci1410a.o
-COBJS-y += tqm8xx_pcmcia.o
-COBJS-$(CONFIG_MARUBUN_PCCARD) += marubun_pcmcia.o
-
-COBJS	:= $(COBJS-y)
-SRCS	:= $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-
-all:	$(LIB)
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-$(CONFIG_I82365) += i82365.o
+obj-$(CONFIG_8xx) += mpc8xx_pcmcia.o
+obj-y += rpx_pcmcia.o
+obj-$(CONFIG_IDE_TI_CARDBUS) += ti_pci1410a.o
+obj-y += tqm8xx_pcmcia.o
+obj-$(CONFIG_MARUBUN_PCCARD) += marubun_pcmcia.o
diff --git a/drivers/power/Makefile b/drivers/power/Makefile
index b2812dc65e..53ff97d745 100644
--- a/drivers/power/Makefile
+++ b/drivers/power/Makefile
@@ -5,38 +5,15 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	:= $(obj)libpower.o
-
-COBJS-$(CONFIG_EXYNOS_TMU)	+= exynos-tmu.o
-COBJS-$(CONFIG_FTPMU010_POWER)	+= ftpmu010.o
-COBJS-$(CONFIG_TPS6586X_POWER)	+= tps6586x.o
-COBJS-$(CONFIG_TWL4030_POWER)	+= twl4030.o
-COBJS-$(CONFIG_TWL6030_POWER)	+= twl6030.o
-COBJS-$(CONFIG_PALMAS_POWER)	+= palmas.o
-
-COBJS-$(CONFIG_POWER) += power_core.o
-COBJS-$(CONFIG_DIALOG_POWER) += power_dialog.o
-COBJS-$(CONFIG_POWER_FSL) += power_fsl.o
-COBJS-$(CONFIG_POWER_I2C) += power_i2c.o
-COBJS-$(CONFIG_POWER_SPI) += power_spi.o
-
-COBJS	:= $(COBJS-y)
-SRCS	:= $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-
-all:	$(LIB)
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-########################################################################
+obj-$(CONFIG_EXYNOS_TMU)	+= exynos-tmu.o
+obj-$(CONFIG_FTPMU010_POWER)	+= ftpmu010.o
+obj-$(CONFIG_TPS6586X_POWER)	+= tps6586x.o
+obj-$(CONFIG_TWL4030_POWER)	+= twl4030.o
+obj-$(CONFIG_TWL6030_POWER)	+= twl6030.o
+obj-$(CONFIG_PALMAS_POWER)	+= palmas.o
+
+obj-$(CONFIG_POWER) += power_core.o
+obj-$(CONFIG_DIALOG_POWER) += power_dialog.o
+obj-$(CONFIG_POWER_FSL) += power_fsl.o
+obj-$(CONFIG_POWER_I2C) += power_i2c.o
+obj-$(CONFIG_POWER_SPI) += power_spi.o
diff --git a/drivers/power/battery/Makefile b/drivers/power/battery/Makefile
index 4bf315da9b..f864f0439d 100644
--- a/drivers/power/battery/Makefile
+++ b/drivers/power/battery/Makefile
@@ -5,28 +5,5 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	:= $(obj)libbattery.o
-
-COBJS-$(CONFIG_POWER_BATTERY_TRATS) += bat_trats.o
-COBJS-$(CONFIG_POWER_BATTERY_TRATS2) += bat_trats2.o
-
-COBJS	:= $(COBJS-y)
-SRCS	:= $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-
-all:	$(LIB)
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-########################################################################
+obj-$(CONFIG_POWER_BATTERY_TRATS) += bat_trats.o
+obj-$(CONFIG_POWER_BATTERY_TRATS2) += bat_trats2.o
diff --git a/drivers/power/battery/bat_trats2.c b/drivers/power/battery/bat_trats2.c
index f2648329d4..94015aa41a 100644
--- a/drivers/power/battery/bat_trats2.c
+++ b/drivers/power/battery/bat_trats2.c
@@ -8,7 +8,7 @@
 #include <common.h>
 #include <power/pmic.h>
 #include <power/battery.h>
-#include <power/max8997_pmic.h>
+#include <power/max77693_pmic.h>
 #include <errno.h>
 
 static struct battery battery_trats;
diff --git a/drivers/power/fuel_gauge/Makefile b/drivers/power/fuel_gauge/Makefile
index 5166a30f62..3b349f939a 100644
--- a/drivers/power/fuel_gauge/Makefile
+++ b/drivers/power/fuel_gauge/Makefile
@@ -5,27 +5,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	:= $(obj)libfuel_gauge.o
-
-COBJS-$(CONFIG_POWER_FG_MAX17042) += fg_max17042.o
-
-COBJS	:= $(COBJS-y)
-SRCS	:= $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-
-all:	$(LIB)
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-########################################################################
+obj-$(CONFIG_POWER_FG_MAX17042) += fg_max17042.o
diff --git a/drivers/power/fuel_gauge/fg_max17042.c b/drivers/power/fuel_gauge/fg_max17042.c
index c285747f34..154ca6a695 100644
--- a/drivers/power/fuel_gauge/fg_max17042.c
+++ b/drivers/power/fuel_gauge/fg_max17042.c
@@ -20,21 +20,30 @@ static int fg_write_regs(struct pmic *p, u8 addr, u16 *data, int num)
 	int ret = 0;
 	int i;
 
-	for (i = 0; i < num; i++, addr++)
-		ret |= pmic_reg_write(p, addr, *(data + i));
+	for (i = 0; i < num; i++, addr++) {
+		ret = pmic_reg_write(p, addr, *(data + i));
+		if (ret)
+			return ret;
+	}
 
-	return ret;
+	return 0;
 }
 
 static int fg_read_regs(struct pmic *p, u8 addr, u16 *data, int num)
 {
+	unsigned int dat;
 	int ret = 0;
 	int i;
 
-	for (i = 0; i < num; i++, addr++)
-		ret |= pmic_reg_read(p, addr, (u32 *) (data + i));
+	for (i = 0; i < num; i++, addr++) {
+		ret = pmic_reg_read(p, addr, &dat);
+		if (ret)
+			return ret;
 
-	return ret;
+		*(data + i) = (u16)dat;
+	}
+
+	return 0;
 }
 
 static int fg_write_and_verify(struct pmic *p, u8 addr, u16 data)
@@ -57,9 +66,13 @@ static int fg_write_and_verify(struct pmic *p, u8 addr, u16 data)
 static void por_fuelgauge_init(struct pmic *p)
 {
 	u16 r_data0[16], r_data1[16], r_data2[16];
-	u32 rewrite_count = 5, i = 0;
-	unsigned int val;
-	int ret = 0;
+	u32 rewrite_count = 5;
+	u32 check_count;
+	u32 lock_count;
+	u32 i = 0;
+	u32 val;
+	s32 ret = 0;
+	char *status_msg;
 
 	/* Delay 500 ms */
 	mdelay(500);
@@ -67,29 +80,55 @@ static void por_fuelgauge_init(struct pmic *p)
 	pmic_reg_write(p, MAX17042_CONFIG, 0x2310);
 
 rewrite_model:
+	check_count = 5;
+	lock_count = 5;
+
+	if (!rewrite_count--) {
+		status_msg = "init failed!";
+		goto error;
+	}
+
 	/* Unlock Model Access */
 	pmic_reg_write(p, MAX17042_MLOCKReg1, MODEL_UNLOCK1);
 	pmic_reg_write(p, MAX17042_MLOCKReg2, MODEL_UNLOCK2);
 
 	/* Write/Read/Verify the Custom Model */
-	ret |= fg_write_regs(p, MAX17042_MODEL1, cell_character0,
+	ret = fg_write_regs(p, MAX17042_MODEL1, cell_character0,
 			     ARRAY_SIZE(cell_character0));
-	ret |= fg_write_regs(p, MAX17042_MODEL2, cell_character1,
+	if (ret)
+		goto rewrite_model;
+
+	ret = fg_write_regs(p, MAX17042_MODEL2, cell_character1,
 			     ARRAY_SIZE(cell_character1));
-	ret |= fg_write_regs(p, MAX17042_MODEL3, cell_character2,
+	if (ret)
+		goto rewrite_model;
+
+	ret = fg_write_regs(p, MAX17042_MODEL3, cell_character2,
 			     ARRAY_SIZE(cell_character2));
+	if (ret)
+		goto rewrite_model;
 
-	if (ret) {
-		printf("%s: Cell parameters write failed!\n", __func__);
-		return;
+check_model:
+	if (!check_count--) {
+		if (rewrite_count)
+			goto rewrite_model;
+		else
+			status_msg = "check failed!";
+
+		goto error;
 	}
 
-	ret |= fg_read_regs(p, MAX17042_MODEL1, r_data0, ARRAY_SIZE(r_data0));
-	ret |= fg_read_regs(p, MAX17042_MODEL2, r_data1, ARRAY_SIZE(r_data1));
-	ret |= fg_read_regs(p, MAX17042_MODEL3, r_data2, ARRAY_SIZE(r_data2));
+	ret = fg_read_regs(p, MAX17042_MODEL1, r_data0, ARRAY_SIZE(r_data0));
+	if (ret)
+		goto check_model;
+
+	ret = fg_read_regs(p, MAX17042_MODEL2, r_data1, ARRAY_SIZE(r_data1));
+	if (ret)
+		goto check_model;
 
+	ret = fg_read_regs(p, MAX17042_MODEL3, r_data2, ARRAY_SIZE(r_data2));
 	if (ret)
-		printf("%s: Cell parameters read failed!\n", __func__);
+		goto check_model;
 
 	for (i = 0; i < 16; i++) {
 		if ((cell_character0[i] != r_data0[i])
@@ -98,29 +137,37 @@ rewrite_model:
 			goto rewrite_model;
 		}
 
+lock_model:
+	if (!lock_count--) {
+		if (rewrite_count)
+			goto rewrite_model;
+		else
+			status_msg = "lock failed!";
+
+		goto error;
+	}
+
 	/* Lock model access */
 	pmic_reg_write(p, MAX17042_MLOCKReg1, MODEL_LOCK1);
 	pmic_reg_write(p, MAX17042_MLOCKReg2, MODEL_LOCK2);
 
 	/* Verify the model access is locked */
-	ret |= fg_read_regs(p, MAX17042_MODEL1, r_data0, ARRAY_SIZE(r_data0));
-	ret |= fg_read_regs(p, MAX17042_MODEL2, r_data1, ARRAY_SIZE(r_data1));
-	ret |= fg_read_regs(p, MAX17042_MODEL3, r_data2, ARRAY_SIZE(r_data2));
+	ret = fg_read_regs(p, MAX17042_MODEL1, r_data0, ARRAY_SIZE(r_data0));
+	if (ret)
+		goto lock_model;
 
-	if (ret) {
-		printf("%s: Cell parameters read failed!\n", __func__);
-		return;
-	}
+	ret = fg_read_regs(p, MAX17042_MODEL2, r_data1, ARRAY_SIZE(r_data1));
+	if (ret)
+		goto lock_model;
+
+	ret = fg_read_regs(p, MAX17042_MODEL3, r_data2, ARRAY_SIZE(r_data2));
+	if (ret)
+		goto lock_model;
 
 	for (i = 0; i < ARRAY_SIZE(r_data0); i++) {
 		/* Check if model locked */
-		if (r_data0[i] || r_data1[i] || r_data2[i]) {
-			/* Rewrite model data - prevent from endless loop */
-			if (rewrite_count--) {
-				puts("FG - Lock model access failed!\n");
-				goto rewrite_model;
-			}
-		}
+		if (r_data0[i] || r_data1[i] || r_data2[i])
+			goto lock_model;
 	}
 
 	/* Write Custom Parameters */
@@ -137,6 +184,11 @@ rewrite_model:
 
 	/* Delay at least 350 ms */
 	mdelay(350);
+
+	status_msg = "OK!";
+error:
+	debug("%s: model init status: %s\n", p->name, status_msg);
+	return;
 }
 
 static int power_update_battery(struct pmic *p, struct pmic *bat)
@@ -178,7 +230,7 @@ static int power_check_battery(struct pmic *p, struct pmic *bat)
 	ret |= pmic_reg_read(p, MAX17042_STATUS, &val);
 	debug("fg status: 0x%x\n", val);
 
-	if (val == MAX17042_POR)
+	if (val & MAX17042_POR)
 		por_fuelgauge_init(p);
 
 	ret |= pmic_reg_read(p, MAX17042_VERSION, &val);
diff --git a/drivers/power/mfd/Makefile b/drivers/power/mfd/Makefile
index 76a05daa67..43afe842ae 100644
--- a/drivers/power/mfd/Makefile
+++ b/drivers/power/mfd/Makefile
@@ -5,29 +5,6 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	:= $(obj)libmfd.o
-
-COBJS-$(CONFIG_POWER_PMIC_MAX77693) += pmic_max77693.o
-COBJS-$(CONFIG_POWER_MUIC_MAX77693) += muic_max77693.o
-COBJS-$(CONFIG_POWER_FG_MAX77693) += fg_max77693.o
-
-COBJS	:= $(COBJS-y)
-SRCS	:= $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-
-all:	$(LIB)
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-########################################################################
+obj-$(CONFIG_POWER_PMIC_MAX77693) += pmic_max77693.o
+obj-$(CONFIG_POWER_MUIC_MAX77693) += muic_max77693.o
+obj-$(CONFIG_POWER_FG_MAX77693) += fg_max77693.o
diff --git a/drivers/power/palmas.c b/drivers/power/palmas.c
index c7b0cbe8b5..cfbc9dc522 100644
--- a/drivers/power/palmas.c
+++ b/drivers/power/palmas.c
@@ -127,6 +127,21 @@ int twl603x_audio_power(u8 on)
 }
 #endif
 
+#ifdef CONFIG_PALMAS_USB_SS_PWR
+/**
+ * @brief palmas_enable_ss_ldo - Configure EVM board specific configurations
+ * for the USB Super speed SMPS10 regulator.
+ *
+ * @return 0
+ */
+int palmas_enable_ss_ldo(void)
+{
+	/* Enable smps10 regulator  */
+	return palmas_i2c_write_u8(TWL603X_CHIP_P1, SMPS10_CTRL,
+				SMPS10_MODE_ACTIVE_D);
+}
+#endif
+
 /*
  * Enable/disable back-up battery (or super cap) charging on TWL6035/37.
  * Please use defined BB_xxx values.
diff --git a/drivers/power/pmic/Makefile b/drivers/power/pmic/Makefile
index 11b3d030e4..4129bdabfb 100644
--- a/drivers/power/pmic/Makefile
+++ b/drivers/power/pmic/Makefile
@@ -5,32 +5,10 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	:= $(obj)libpmic.o
-
-COBJS-$(CONFIG_POWER_MAX8998) += pmic_max8998.o
-COBJS-$(CONFIG_POWER_MAX8997) += pmic_max8997.o
-COBJS-$(CONFIG_POWER_MUIC_MAX8997) += muic_max8997.o
-COBJS-$(CONFIG_POWER_MAX77686) += pmic_max77686.o
-COBJS-$(CONFIG_POWER_TPS65217) += pmic_tps65217.o
-COBJS-$(CONFIG_POWER_TPS65910) += pmic_tps65910.o
-
-COBJS	:= $(COBJS-y)
-SRCS	:= $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-
-all:	$(LIB)
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-########################################################################
+obj-$(CONFIG_POWER_MAX8998) += pmic_max8998.o
+obj-$(CONFIG_POWER_MAX8997) += pmic_max8997.o
+obj-$(CONFIG_POWER_MUIC_MAX8997) += muic_max8997.o
+obj-$(CONFIG_POWER_MAX77686) += pmic_max77686.o
+obj-$(CONFIG_POWER_PFUZE100) += pmic_pfuze100.o
+obj-$(CONFIG_POWER_TPS65217) += pmic_tps65217.o
+obj-$(CONFIG_POWER_TPS65910) += pmic_tps65910.o
diff --git a/drivers/power/pmic/pmic_pfuze100.c b/drivers/power/pmic/pmic_pfuze100.c
new file mode 100644
index 0000000000..22c1f15eeb
--- /dev/null
+++ b/drivers/power/pmic/pmic_pfuze100.c
@@ -0,0 +1,32 @@
+/*
+ * Copyright (C) 2014 Gateworks Corporation
+ * Tim Harvey <tharvey@gateworks.com>
+ *
+ * SPDX-License-Identifier:      GPL-2.0+
+ */
+
+#include <common.h>
+#include <errno.h>
+#include <i2c.h>
+#include <power/pmic.h>
+#include <power/pfuze100_pmic.h>
+
+int pmic_init(unsigned char bus)
+{
+	static const char name[] = "PFUZE100_PMIC";
+	struct pmic *p = pmic_alloc();
+
+	if (!p) {
+		printf("%s: POWER allocation error!\n", __func__);
+		return -ENOMEM;
+	}
+
+	p->name = name;
+	p->interface = PMIC_I2C;
+	p->number_of_regs = PMIC_NUM_OF_REGS;
+	p->hw.i2c.addr = CONFIG_POWER_PFUZE100_I2C_ADDR;
+	p->hw.i2c.tx_num = 1;
+	p->bus = bus;
+
+	return 0;
+}
diff --git a/drivers/power/power_core.c b/drivers/power/power_core.c
index 29ccc831af..fe1f316021 100644
--- a/drivers/power/power_core.c
+++ b/drivers/power/power_core.c
@@ -140,6 +140,9 @@ int do_pmic(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 		return CMD_RET_SUCCESS;
 	}
 
+	if (argc < 3)
+		return CMD_RET_USAGE;
+
 	name = argv[1];
 	cmd = argv[2];
 
diff --git a/drivers/power/power_fsl.c b/drivers/power/power_fsl.c
index ed778f333e..ac0b541d79 100644
--- a/drivers/power/power_fsl.c
+++ b/drivers/power/power_fsl.c
@@ -36,10 +36,10 @@ int pmic_init(unsigned char bus)
 
 	p->name = name;
 	p->number_of_regs = PMIC_NUM_OF_REGS;
+	p->bus = bus;
 
 #if defined(CONFIG_POWER_SPI)
 	p->interface = PMIC_SPI;
-	p->bus = CONFIG_FSL_PMIC_BUS;
 	p->hw.spi.cs = CONFIG_FSL_PMIC_CS;
 	p->hw.spi.clk = CONFIG_FSL_PMIC_CLK;
 	p->hw.spi.mode = CONFIG_FSL_PMIC_MODE;
@@ -50,7 +50,6 @@ int pmic_init(unsigned char bus)
 	p->interface = PMIC_I2C;
 	p->hw.i2c.addr = CONFIG_SYS_FSL_PMIC_I2C_ADDR;
 	p->hw.i2c.tx_num = FSL_PMIC_I2C_LENGTH;
-	p->bus = bus;
 #else
 #error "You must select CONFIG_POWER_SPI or CONFIG_PMIC_I2C"
 #endif
diff --git a/drivers/power/twl6030.c b/drivers/power/twl6030.c
index 0858b60e06..a1c6663a2e 100644
--- a/drivers/power/twl6030.c
+++ b/drivers/power/twl6030.c
@@ -9,6 +9,26 @@
 
 #include <twl6030.h>
 
+static struct twl6030_data *twl;
+
+static struct twl6030_data twl6030_info = {
+	.chip_type	= chip_TWL6030,
+	.adc_rbase	= GPCH0_LSB,
+	.adc_ctrl	= CTRL_P2,
+	.adc_enable	= CTRL_P2_SP2,
+	.vbat_mult	= TWL6030_VBAT_MULT,
+	.vbat_shift	= TWL6030_VBAT_SHIFT,
+};
+
+static struct twl6030_data twl6032_info = {
+	.chip_type	= chip_TWL6032,
+	.adc_rbase	= TWL6032_GPCH0_LSB,
+	.adc_ctrl	= TWL6032_CTRL_P1,
+	.adc_enable	= CTRL_P1_SP1,
+	.vbat_mult	= TWL6032_VBAT_MULT,
+	.vbat_shift	= TWL6032_VBAT_SHIFT,
+};
+
 static int twl6030_gpadc_read_channel(u8 channel_no)
 {
 	u8 lsb = 0;
@@ -16,12 +36,12 @@ static int twl6030_gpadc_read_channel(u8 channel_no)
 	int ret = 0;
 
 	ret = twl6030_i2c_read_u8(TWL6030_CHIP_ADC,
-				  GPCH0_LSB + channel_no * 2, &lsb);
+				  twl->adc_rbase + channel_no * 2, &lsb);
 	if (ret)
 		return ret;
 
 	ret = twl6030_i2c_read_u8(TWL6030_CHIP_ADC,
-				  GPCH0_MSB + channel_no * 2, &msb);
+				  twl->adc_rbase + 1 + channel_no * 2, &msb);
 	if (ret)
 		return ret;
 
@@ -33,7 +53,8 @@ static int twl6030_gpadc_sw2_trigger(void)
 	u8 val;
 	int ret = 0;
 
-	ret = twl6030_i2c_write_u8(TWL6030_CHIP_ADC, CTRL_P2, CTRL_P2_SP2);
+	ret = twl6030_i2c_write_u8(TWL6030_CHIP_ADC,
+				   twl->adc_ctrl, twl->adc_enable);
 	if (ret)
 		return ret;
 
@@ -41,7 +62,8 @@ static int twl6030_gpadc_sw2_trigger(void)
 	val =  CTRL_P2_BUSY;
 
 	while (!((val & CTRL_P2_EOCP2) && (!(val & CTRL_P2_BUSY)))) {
-		ret = twl6030_i2c_read_u8(TWL6030_CHIP_ADC, CTRL_P2, &val);
+		ret = twl6030_i2c_read_u8(TWL6030_CHIP_ADC,
+					  twl->adc_ctrl, &val);
 		if (ret)
 			return ret;
 		udelay(1000);
@@ -102,6 +124,18 @@ int twl6030_get_battery_voltage(void)
 {
 	int battery_volt = 0;
 	int ret = 0;
+	u8 vbatch;
+
+	if (twl->chip_type == chip_TWL6030) {
+		vbatch = TWL6030_GPADC_VBAT_CHNL;
+	} else {
+		ret = twl6030_i2c_write_u8(TWL6030_CHIP_ADC,
+					   TWL6032_GPSELECT_ISB,
+					   TWL6032_GPADC_VBAT_CHNL);
+		if (ret)
+			return ret;
+		vbatch = 0;
+	}
 
 	/* Start GPADC SW conversion */
 	ret = twl6030_gpadc_sw2_trigger();
@@ -111,12 +145,12 @@ int twl6030_get_battery_voltage(void)
 	}
 
 	/* measure Vbat voltage */
-	battery_volt = twl6030_gpadc_read_channel(7);
+	battery_volt = twl6030_gpadc_read_channel(vbatch);
 	if (battery_volt < 0) {
 		printf("Failed to read battery voltage\n");
 		return ret;
 	}
-	battery_volt = (battery_volt * 25 * 1000) >> (10 + 2);
+	battery_volt = (battery_volt * twl->vbat_mult) >> twl->vbat_shift;
 	printf("Battery Voltage: %d mV\n", battery_volt);
 
 	return battery_volt;
@@ -124,12 +158,35 @@ int twl6030_get_battery_voltage(void)
 
 void twl6030_init_battery_charging(void)
 {
-	u8 stat1 = 0;
+	u8 val = 0;
 	int battery_volt = 0;
 	int ret = 0;
 
+	ret = twl6030_i2c_read_u8(TWL6030_CHIP_USB, USB_PRODUCT_ID_LSB, &val);
+	if (ret) {
+		puts("twl6030_init_battery_charging(): could not determine chip!\n");
+		return;
+	}
+	if (val == 0x30) {
+		twl = &twl6030_info;
+	} else if (val == 0x32) {
+		twl = &twl6032_info;
+	} else {
+		puts("twl6030_init_battery_charging(): unsupported chip type\n");
+		return;
+	}
+
 	/* Enable VBAT measurement */
-	twl6030_i2c_write_u8(TWL6030_CHIP_PM, MISC1, VBAT_MEAS);
+	if (twl->chip_type == chip_TWL6030) {
+		twl6030_i2c_write_u8(TWL6030_CHIP_PM, MISC1, VBAT_MEAS);
+		twl6030_i2c_write_u8(TWL6030_CHIP_ADC,
+				     TWL6030_GPADC_CTRL,
+				     GPADC_CTRL_SCALER_DIV4);
+	} else {
+		twl6030_i2c_write_u8(TWL6030_CHIP_ADC,
+				     TWL6032_GPADC_CTRL2,
+				     GPADC_CTRL2_CH18_SCALER_EN);
+	}
 
 	/* Enable GPADC module */
 	ret = twl6030_i2c_write_u8(TWL6030_CHIP_CHARGER, TOGGLE1, FGS | GPADCS);
@@ -146,10 +203,10 @@ void twl6030_init_battery_charging(void)
 		printf("Main battery voltage too low!\n");
 
 	/* Check for the presence of USB charger */
-	twl6030_i2c_read_u8(TWL6030_CHIP_CHARGER, CONTROLLER_STAT1, &stat1);
+	twl6030_i2c_read_u8(TWL6030_CHIP_CHARGER, CONTROLLER_STAT1, &val);
 
 	/* check for battery presence indirectly via Fuel gauge */
-	if ((stat1 & VBUS_DET) && (battery_volt < 3300))
+	if ((val & VBUS_DET) && (battery_volt < 3300))
 		twl6030_start_usb_charging();
 
 	return;
diff --git a/drivers/qe/Makefile b/drivers/qe/Makefile
index 3aaf757934..7f1bd06922 100644
--- a/drivers/qe/Makefile
+++ b/drivers/qe/Makefile
@@ -4,26 +4,5 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	:= $(obj)libqe.o
-
-COBJS-$(and $(CONFIG_QE),$(CONFIG_OF_LIBFDT)) += fdt.o
-COBJS-$(CONFIG_QE) += qe.o uccf.o uec.o uec_phy.o
-
-COBJS	:= $(COBJS-y)
-SRCS	:= $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-
-all:	$(LIB)
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y := qe.o uccf.o uec.o uec_phy.o
+obj-$(CONFIG_OF_LIBFDT) += fdt.o
diff --git a/drivers/rtc/Makefile b/drivers/rtc/Makefile
index dcc0632ff2..003d322d23 100644
--- a/drivers/rtc/Makefile
+++ b/drivers/rtc/Makefile
@@ -5,70 +5,48 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-#CFLAGS += -DDEBUG
-
-LIB	= $(obj)librtc.o
-
-COBJS-$(CONFIG_RTC_AT91SAM9_RTT) += at91sam9_rtt.o
-COBJS-$(CONFIG_RTC_BFIN) += bfin_rtc.o
-COBJS-y += date.o
-COBJS-$(CONFIG_RTC_DAVINCI) += davinci.o
-COBJS-$(CONFIG_RTC_DS12887) += ds12887.o
-COBJS-$(CONFIG_RTC_DS1302) += ds1302.o
-COBJS-$(CONFIG_RTC_DS1306) += ds1306.o
-COBJS-$(CONFIG_RTC_DS1307) += ds1307.o
-COBJS-$(CONFIG_RTC_DS1338) += ds1307.o
-COBJS-$(CONFIG_RTC_DS1337) += ds1337.o
-COBJS-$(CONFIG_RTC_DS1374) += ds1374.o
-COBJS-$(CONFIG_RTC_DS1388) += ds1337.o
-COBJS-$(CONFIG_RTC_DS1556) += ds1556.o
-COBJS-$(CONFIG_RTC_DS164x) += ds164x.o
-COBJS-$(CONFIG_RTC_DS174x) += ds174x.o
-COBJS-$(CONFIG_RTC_DS3231) += ds3231.o
-COBJS-$(CONFIG_RTC_FTRTC010) += ftrtc010.o
-COBJS-$(CONFIG_RTC_IMXDI) += imxdi.o
-COBJS-$(CONFIG_RTC_ISL1208) += isl1208.o
-COBJS-$(CONFIG_RTC_M41T11) += m41t11.o
-COBJS-$(CONFIG_RTC_M41T60) += m41t60.o
-COBJS-$(CONFIG_RTC_M41T62) += m41t62.o
-COBJS-$(CONFIG_RTC_M41T94) += m41t94.o
-COBJS-$(CONFIG_RTC_M48T35A) += m48t35ax.o
-COBJS-$(CONFIG_RTC_MAX6900) += max6900.o
-COBJS-$(CONFIG_RTC_MC13XXX) += mc13xxx-rtc.o
-COBJS-$(CONFIG_RTC_MC146818) += mc146818.o
-COBJS-$(CONFIG_MCFRTC) += mcfrtc.o
-COBJS-$(CONFIG_RTC_MK48T59) += mk48t59.o
-COBJS-$(CONFIG_RTC_MPC5200) += mpc5xxx.o
-COBJS-$(CONFIG_RTC_MPC8xx) += mpc8xx.o
-COBJS-$(CONFIG_RTC_MV) += mvrtc.o
-COBJS-$(CONFIG_RTC_MX27) += mx27rtc.o
-COBJS-$(CONFIG_RTC_MXS) += mxsrtc.o
-COBJS-$(CONFIG_RTC_PCF8563) += pcf8563.o
-COBJS-$(CONFIG_RTC_PL031) += pl031.o
-COBJS-$(CONFIG_RTC_PT7C4338) += pt7c4338.o
-COBJS-$(CONFIG_RTC_RS5C372A) += rs5c372.o
-COBJS-$(CONFIG_RTC_RTC4543) += rtc4543.o
-COBJS-$(CONFIG_RTC_RV3029) += rv3029.o
-COBJS-$(CONFIG_RTC_RX8025) += rx8025.o
-COBJS-$(CONFIG_RTC_S3C24X0) += s3c24x0_rtc.o
-COBJS-$(CONFIG_RTC_X1205) += x1205.o
-
-COBJS	:= $(sort $(COBJS-y))
-SRCS	:= $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-
-all:	$(LIB)
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+#ccflags-y += -DDEBUG
+
+obj-$(CONFIG_RTC_AT91SAM9_RTT) += at91sam9_rtt.o
+obj-$(CONFIG_RTC_BFIN) += bfin_rtc.o
+obj-y += date.o
+obj-$(CONFIG_RTC_DAVINCI) += davinci.o
+obj-$(CONFIG_RTC_DS12887) += ds12887.o
+obj-$(CONFIG_RTC_DS1302) += ds1302.o
+obj-$(CONFIG_RTC_DS1306) += ds1306.o
+obj-$(CONFIG_RTC_DS1307) += ds1307.o
+obj-$(CONFIG_RTC_DS1338) += ds1307.o
+obj-$(CONFIG_RTC_DS1337) += ds1337.o
+obj-$(CONFIG_RTC_DS1374) += ds1374.o
+obj-$(CONFIG_RTC_DS1388) += ds1337.o
+obj-$(CONFIG_RTC_DS1556) += ds1556.o
+obj-$(CONFIG_RTC_DS164x) += ds164x.o
+obj-$(CONFIG_RTC_DS174x) += ds174x.o
+obj-$(CONFIG_RTC_DS3231) += ds3231.o
+obj-$(CONFIG_RTC_FTRTC010) += ftrtc010.o
+obj-$(CONFIG_RTC_IMXDI) += imxdi.o
+obj-$(CONFIG_RTC_ISL1208) += isl1208.o
+obj-$(CONFIG_RTC_M41T11) += m41t11.o
+obj-$(CONFIG_RTC_M41T60) += m41t60.o
+obj-$(CONFIG_RTC_M41T62) += m41t62.o
+obj-$(CONFIG_RTC_M41T94) += m41t94.o
+obj-$(CONFIG_RTC_M48T35A) += m48t35ax.o
+obj-$(CONFIG_RTC_MAX6900) += max6900.o
+obj-$(CONFIG_RTC_MC13XXX) += mc13xxx-rtc.o
+obj-$(CONFIG_RTC_MC146818) += mc146818.o
+obj-$(CONFIG_MCFRTC) += mcfrtc.o
+obj-$(CONFIG_RTC_MK48T59) += mk48t59.o
+obj-$(CONFIG_RTC_MPC5200) += mpc5xxx.o
+obj-$(CONFIG_RTC_MPC8xx) += mpc8xx.o
+obj-$(CONFIG_RTC_MV) += mvrtc.o
+obj-$(CONFIG_RTC_MX27) += mx27rtc.o
+obj-$(CONFIG_RTC_MXS) += mxsrtc.o
+obj-$(CONFIG_RTC_PCF8563) += pcf8563.o
+obj-$(CONFIG_RTC_PL031) += pl031.o
+obj-$(CONFIG_RTC_PT7C4338) += pt7c4338.o
+obj-$(CONFIG_RTC_RS5C372A) += rs5c372.o
+obj-$(CONFIG_RTC_RTC4543) += rtc4543.o
+obj-$(CONFIG_RTC_RV3029) += rv3029.o
+obj-$(CONFIG_RTC_RX8025) += rx8025.o
+obj-$(CONFIG_RTC_S3C24X0) += s3c24x0_rtc.o
+obj-$(CONFIG_RTC_X1205) += x1205.o
diff --git a/drivers/rtc/davinci.c b/drivers/rtc/davinci.c
index e60c0da64c..f862e2f951 100644
--- a/drivers/rtc/davinci.c
+++ b/drivers/rtc/davinci.c
@@ -8,12 +8,12 @@
 #include <command.h>
 #include <rtc.h>
 #include <asm/io.h>
-#include <asm/arch/hardware.h>
+#include <asm/davinci_rtc.h>
 
 #if defined(CONFIG_CMD_DATE)
 int rtc_get(struct rtc_time *tmp)
 {
-	struct davinci_rtc *rtc = davinci_rtc_base;
+	struct davinci_rtc *rtc = (struct davinci_rtc *)DAVINCI_RTC_BASE;
 	unsigned long sec, min, hour, mday, wday, mon_cent, year;
 	unsigned long status;
 
@@ -57,7 +57,7 @@ int rtc_get(struct rtc_time *tmp)
 
 int rtc_set(struct rtc_time *tmp)
 {
-	struct davinci_rtc *rtc = davinci_rtc_base;
+	struct davinci_rtc *rtc = (struct davinci_rtc *)DAVINCI_RTC_BASE;
 
 	debug("Set DATE: %4d-%02d-%02d (wday=%d)  TIME: %2d:%02d:%02d\n",
 		tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
@@ -75,7 +75,7 @@ int rtc_set(struct rtc_time *tmp)
 
 void rtc_reset(void)
 {
-	struct davinci_rtc *rtc = davinci_rtc_base;
+	struct davinci_rtc *rtc = (struct davinci_rtc *)DAVINCI_RTC_BASE;
 
 	/* run RTC counter */
 	writel(0x01, &rtc->ctrl);
diff --git a/drivers/rtc/mc146818.c b/drivers/rtc/mc146818.c
index 5f9d359590..f7cf1064f9 100644
--- a/drivers/rtc/mc146818.c
+++ b/drivers/rtc/mc146818.c
@@ -15,7 +15,7 @@
 #include <command.h>
 #include <rtc.h>
 
-#ifdef __I386__
+#if defined(__I386__) || defined(CONFIG_MALTA)
 #include <asm/io.h>
 #define in8(p) inb(p)
 #define out8(p, v) outb(v, p)
diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile
index e1fd7a5dc8..571c18fa93 100644
--- a/drivers/serial/Makefile
+++ b/drivers/serial/Makefile
@@ -5,58 +5,36 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	:= $(obj)libserial.o
-
-COBJS-y += serial.o
-
-COBJS-$(CONFIG_ALTERA_UART) += altera_uart.o
-COBJS-$(CONFIG_ALTERA_JTAG_UART) += altera_jtag_uart.o
-COBJS-$(CONFIG_ARM_DCC) += arm_dcc.o
-COBJS-$(CONFIG_ATMEL_USART) += atmel_usart.o
-COBJS-$(CONFIG_LPC32XX_HSUART) += lpc32xx_hsuart.o
-COBJS-$(CONFIG_MCFUART) += mcfuart.o
-COBJS-$(CONFIG_OPENCORES_YANU) += opencores_yanu.o
-COBJS-$(CONFIG_SYS_NS16550) += ns16550.o
-COBJS-$(CONFIG_S5P) += serial_s5p.o
-COBJS-$(CONFIG_SYS_NS16550_SERIAL) += serial_ns16550.o
-COBJS-$(CONFIG_IMX_SERIAL) += serial_imx.o
-COBJS-$(CONFIG_IXP_SERIAL) += serial_ixp.o
-COBJS-$(CONFIG_KS8695_SERIAL) += serial_ks8695.o
-COBJS-$(CONFIG_MAX3100_SERIAL) += serial_max3100.o
-COBJS-$(CONFIG_MXC_UART) += serial_mxc.o
-COBJS-$(CONFIG_PL010_SERIAL) += serial_pl01x.o
-COBJS-$(CONFIG_PL011_SERIAL) += serial_pl01x.o
-COBJS-$(CONFIG_PXA_SERIAL) += serial_pxa.o
-COBJS-$(CONFIG_SA1100_SERIAL) += serial_sa1100.o
-COBJS-$(CONFIG_S3C24X0_SERIAL) += serial_s3c24x0.o
-COBJS-$(CONFIG_XILINX_UARTLITE) += serial_xuartlite.o
-COBJS-$(CONFIG_SANDBOX_SERIAL) += sandbox.o
-COBJS-$(CONFIG_SCIF_CONSOLE) += serial_sh.o
-COBJS-$(CONFIG_ZYNQ_SERIAL) += serial_zynq.o
-COBJS-$(CONFIG_BFIN_SERIAL) += serial_bfin.o
-COBJS-$(CONFIG_FSL_LPUART) += serial_lpuart.o
-COBJS-$(CONFIG_MXS_AUART) += mxs_auart.o
+obj-y += serial.o
+
+obj-$(CONFIG_ALTERA_UART) += altera_uart.o
+obj-$(CONFIG_ALTERA_JTAG_UART) += altera_jtag_uart.o
+obj-$(CONFIG_ARM_DCC) += arm_dcc.o
+obj-$(CONFIG_ATMEL_USART) += atmel_usart.o
+obj-$(CONFIG_LPC32XX_HSUART) += lpc32xx_hsuart.o
+obj-$(CONFIG_MCFUART) += mcfuart.o
+obj-$(CONFIG_OPENCORES_YANU) += opencores_yanu.o
+obj-$(CONFIG_SYS_NS16550) += ns16550.o
+obj-$(CONFIG_S5P) += serial_s5p.o
+obj-$(CONFIG_SYS_NS16550_SERIAL) += serial_ns16550.o
+obj-$(CONFIG_IMX_SERIAL) += serial_imx.o
+obj-$(CONFIG_KS8695_SERIAL) += serial_ks8695.o
+obj-$(CONFIG_MAX3100_SERIAL) += serial_max3100.o
+obj-$(CONFIG_MXC_UART) += serial_mxc.o
+obj-$(CONFIG_PL010_SERIAL) += serial_pl01x.o
+obj-$(CONFIG_PL011_SERIAL) += serial_pl01x.o
+obj-$(CONFIG_PXA_SERIAL) += serial_pxa.o
+obj-$(CONFIG_SA1100_SERIAL) += serial_sa1100.o
+obj-$(CONFIG_S3C24X0_SERIAL) += serial_s3c24x0.o
+obj-$(CONFIG_XILINX_UARTLITE) += serial_xuartlite.o
+obj-$(CONFIG_SANDBOX_SERIAL) += sandbox.o
+obj-$(CONFIG_SCIF_CONSOLE) += serial_sh.o
+obj-$(CONFIG_ZYNQ_SERIAL) += serial_zynq.o
+obj-$(CONFIG_BFIN_SERIAL) += serial_bfin.o
+obj-$(CONFIG_FSL_LPUART) += serial_lpuart.o
+obj-$(CONFIG_MXS_AUART) += mxs_auart.o
+obj-$(CONFIG_ARC_SERIAL) += serial_arc.o
 
 ifndef CONFIG_SPL_BUILD
-COBJS-$(CONFIG_USB_TTY) += usbtty.o
+obj-$(CONFIG_USB_TTY) += usbtty.o
 endif
-
-COBJS	:= $(sort $(COBJS-y))
-SRCS	:= $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-
-all:	$(LIB)
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
diff --git a/drivers/serial/lpc32xx_hsuart.c b/drivers/serial/lpc32xx_hsuart.c
index 9c7c6213a5..c8926a8945 100644
--- a/drivers/serial/lpc32xx_hsuart.c
+++ b/drivers/serial/lpc32xx_hsuart.c
@@ -38,6 +38,9 @@ static int lpc32xx_serial_getc(void)
 
 static void lpc32xx_serial_putc(const char c)
 {
+	if (c == '\n')
+		serial_putc('\r');
+
 	writel(c, &hsuart->tx);
 
 	/* Wait for character to be sent */
diff --git a/drivers/serial/mxs_auart.c b/drivers/serial/mxs_auart.c
index 7cfe5bccf7..fc0fa96a0e 100644
--- a/drivers/serial/mxs_auart.c
+++ b/drivers/serial/mxs_auart.c
@@ -40,7 +40,7 @@ static struct mxs_uartapp_regs *get_uartapp_registers(void)
  * Sets the baud rate and settings.
  * The settings are: 8 data bits, no parit and 1 stop bit.
  */
-void mxs_auart_setbrg(void)
+static void mxs_auart_setbrg(void)
 {
 	u32 div;
 	u32 linectrl = 0;
@@ -77,7 +77,7 @@ void mxs_auart_setbrg(void)
 	writel(linectrl, &regs->hw_uartapp_linectrl);
 }
 
-int mxs_auart_init(void)
+static int mxs_auart_init(void)
 {
 	struct mxs_uartapp_regs *regs = get_uartapp_registers();
 	/* Reset everything */
@@ -99,7 +99,7 @@ int mxs_auart_init(void)
 	return 0;
 }
 
-void mxs_auart_putc(const char c)
+static void mxs_auart_putc(const char c)
 {
 	struct mxs_uartapp_regs *regs = get_uartapp_registers();
 	/* Wait in loop while the transmit FIFO is full */
@@ -112,14 +112,14 @@ void mxs_auart_putc(const char c)
 		mxs_auart_putc('\r');
 }
 
-int mxs_auart_tstc(void)
+static int mxs_auart_tstc(void)
 {
 	struct mxs_uartapp_regs *regs = get_uartapp_registers();
 	/* Checks if receive FIFO is empty */
 	return !(readl(&regs->hw_uartapp_stat) & UARTAPP_STAT_RXFE_MASK);
 }
 
-int mxs_auart_getc(void)
+static int mxs_auart_getc(void)
 {
 	struct mxs_uartapp_regs *regs = get_uartapp_registers();
 	/* Wait until a character is available to read */
diff --git a/drivers/serial/ns16550.c b/drivers/serial/ns16550.c
index 181c81815a..fbc37b27e8 100644
--- a/drivers/serial/ns16550.c
+++ b/drivers/serial/ns16550.c
@@ -56,9 +56,8 @@ void NS16550_init(NS16550_t com_port, int baud_divisor)
 		;
 
 	serial_out(CONFIG_SYS_NS16550_IER, &com_port->ier);
-#if (defined(CONFIG_OMAP) && !defined(CONFIG_OMAP3_ZOOM2)) || \
-			defined(CONFIG_AM33XX) || defined(CONFIG_TI81XX) || \
-			defined(CONFIG_AM43XX)
+#if defined(CONFIG_OMAP) || defined(CONFIG_AM33XX) || \
+			defined(CONFIG_TI81XX) || defined(CONFIG_AM43XX)
 	serial_out(0x7, &com_port->mdr1);	/* mode select reset TL16C750*/
 #endif
 	serial_out(UART_LCR_BKSE | UART_LCRVAL, &com_port->lcr);
diff --git a/drivers/serial/opencores_yanu.c b/drivers/serial/opencores_yanu.c
index 8de2eca2ac..d4ed60c303 100644
--- a/drivers/serial/opencores_yanu.c
+++ b/drivers/serial/opencores_yanu.c
@@ -8,6 +8,7 @@
 #include <watchdog.h>
 #include <asm/io.h>
 #include <nios2-yanu.h>
+#include <serial.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -17,62 +18,34 @@ DECLARE_GLOBAL_DATA_PTR;
 
 static yanu_uart_t *uart = (yanu_uart_t *)CONFIG_SYS_NIOS_CONSOLE;
 
-#if defined(CONFIG_SYS_NIOS_FIXEDBAUD)
-
-/* Everything's already setup for fixed-baud PTF assignment*/
-
 static void oc_serial_setbrg(void)
 {
 	int n, k;
 	const unsigned max_uns = 0xFFFFFFFF;
 	unsigned best_n, best_m, baud;
+	unsigned baudrate;
 
-	/* compute best N and M couple */
-	best_n = YANU_MAX_PRESCALER_N;
-	for (n = YANU_MAX_PRESCALER_N; n >= 0; n--) {
-		if ((unsigned)CONFIG_SYS_CLK_FREQ / (1 << (n + 4)) >=
-		    (unsigned)CONFIG_BAUDRATE) {
-			best_n = n;
-			break;
-		}
-	}
-	for (k = 0;; k++) {
-		if ((unsigned)CONFIG_BAUDRATE <= (max_uns >> (15+n-k)))
-			break;
-	}
-	best_m =
-	    ((unsigned)CONFIG_BAUDRATE * (1 << (15 + n - k))) /
-	    ((unsigned)CONFIG_SYS_CLK_FREQ >> k);
-
-	baud = best_m + best_n * YANU_BAUDE;
-	writel(baud, &uart->baud);
-
-	return;
-}
-
+#if defined(CONFIG_SYS_NIOS_FIXEDBAUD)
+	/* Everything's already setup for fixed-baud PTF assignment */
+	baudrate = CONFIG_BAUDRATE;
 #else
-
-static void oc_serial_setbrg(void)
-{
-	int n, k;
-	const unsigned max_uns = 0xFFFFFFFF;
-	unsigned best_n, best_m, baud;
-
+	baudrate = gd->baudrate;
+#endif
 	/* compute best N and M couple */
 	best_n = YANU_MAX_PRESCALER_N;
 	for (n = YANU_MAX_PRESCALER_N; n >= 0; n--) {
 		if ((unsigned)CONFIG_SYS_CLK_FREQ / (1 << (n + 4)) >=
-		    gd->baudrate) {
+		    baudrate) {
 			best_n = n;
 			break;
 		}
 	}
 	for (k = 0;; k++) {
-		if (gd->baudrate <= (max_uns >> (15+n-k)))
+		if (baudrate <= (max_uns >> (15+n-k)))
 			break;
 	}
 	best_m =
-	    (gd->baudrate * (1 << (15 + n - k))) /
+	    (baudrate * (1 << (15 + n - k))) /
 	    ((unsigned)CONFIG_SYS_CLK_FREQ >> k);
 
 	baud = best_m + best_n * YANU_BAUDE;
@@ -81,9 +54,6 @@ static void oc_serial_setbrg(void)
 	return;
 }
 
-
-#endif /* CONFIG_SYS_NIOS_FIXEDBAUD */
-
 static int oc_serial_init(void)
 {
 	unsigned action,control;
@@ -154,7 +124,7 @@ static int oc_serial_tstc(void)
 		 ((1 << YANU_RFIFO_CHARS_N) - 1)) > 0);
 }
 
-statoc int oc_serial_getc(void)
+static int oc_serial_getc(void)
 {
 	while (serial_tstc() == 0)
 		WATCHDOG_RESET ();
diff --git a/drivers/serial/sandbox.c b/drivers/serial/sandbox.c
index ffff5e1497..51fd871dff 100644
--- a/drivers/serial/sandbox.c
+++ b/drivers/serial/sandbox.c
@@ -11,9 +11,11 @@
  */
 
 #include <common.h>
+#include <lcd.h>
 #include <os.h>
 #include <serial.h>
 #include <linux/compiler.h>
+#include <asm/state.h>
 
 /*
  *
@@ -30,7 +32,10 @@ static unsigned int serial_buf_read;
 
 static int sandbox_serial_init(void)
 {
-	os_tty_raw(0);
+	struct sandbox_state *state = state_get_current();
+
+	if (state->term_raw != STATE_TERM_COOKED)
+		os_tty_raw(0, state->term_raw == STATE_TERM_RAW_WITH_SIGS);
 	return 0;
 }
 
@@ -60,6 +65,9 @@ static int sandbox_serial_tstc(void)
 	ssize_t count;
 
 	os_usleep(100);
+#ifdef CONFIG_LCD
+	lcd_sync();
+#endif
 	if (next_index == serial_buf_read)
 		return 1;	/* buffer full */
 
diff --git a/drivers/serial/serial.c b/drivers/serial/serial.c
index df2b84aaaf..df05bde461 100644
--- a/drivers/serial/serial.c
+++ b/drivers/serial/serial.c
@@ -150,7 +150,6 @@ serial_initfunc(oc_serial_initialize);
 serial_initfunc(sandbox_serial_initialize);
 serial_initfunc(clps7111_serial_initialize);
 serial_initfunc(imx_serial_initialize);
-serial_initfunc(ixp_serial_initialize);
 serial_initfunc(ks8695_serial_initialize);
 serial_initfunc(lh7a40x_serial_initialize);
 serial_initfunc(max3100_serial_initialize);
@@ -160,6 +159,7 @@ serial_initfunc(sa1100_serial_initialize);
 serial_initfunc(sh_serial_initialize);
 serial_initfunc(arm_dcc_initialize);
 serial_initfunc(mxs_auart_initialize);
+serial_initfunc(arc_serial_initialize);
 
 /**
  * serial_register() - Register serial driver with serial driver core
@@ -243,7 +243,6 @@ void serial_initialize(void)
 	sandbox_serial_initialize();
 	clps7111_serial_initialize();
 	imx_serial_initialize();
-	ixp_serial_initialize();
 	ks8695_serial_initialize();
 	lh7a40x_serial_initialize();
 	max3100_serial_initialize();
@@ -253,6 +252,7 @@ void serial_initialize(void)
 	sh_serial_initialize();
 	arm_dcc_initialize();
 	mxs_auart_initialize();
+	arc_serial_initialize();
 
 	serial_assign(default_serial_console()->name);
 }
diff --git a/drivers/serial/serial_arc.c b/drivers/serial/serial_arc.c
new file mode 100644
index 0000000000..2ddbf32a50
--- /dev/null
+++ b/drivers/serial/serial_arc.c
@@ -0,0 +1,115 @@
+/*
+ * Copyright (C) 2013 Synopsys, Inc. (www.synopsys.com)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#include <common.h>
+#include <serial.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct arc_serial_regs {
+	unsigned int id0;
+	unsigned int id1;
+	unsigned int id2;
+	unsigned int id3;
+	unsigned int data;
+	unsigned int status;
+	unsigned int baudl;
+	unsigned int baudh;
+};
+
+/* Bit definitions of STATUS register */
+#define UART_RXEMPTY		(1 << 5)
+#define UART_OVERFLOW_ERR	(1 << 1)
+#define UART_TXEMPTY		(1 << 7)
+
+struct arc_serial_regs *regs;
+
+static void arc_serial_setbrg(void)
+{
+	int arc_console_baud;
+
+	if (!gd->baudrate)
+		gd->baudrate = CONFIG_BAUDRATE;
+
+	arc_console_baud = gd->cpu_clk / (gd->baudrate * 4) - 1;
+	writeb(arc_console_baud & 0xff, &regs->baudl);
+
+#ifdef CONFIG_ARC
+	/*
+	 * UART ISS(Instruction Set simulator) emulation has a subtle bug:
+	 * A existing value of Baudh = 0 is used as a indication to startup
+	 * it's internal state machine.
+	 * Thus if baudh is set to 0, 2 times, it chokes.
+	 * This happens with BAUD=115200 and the formaula above
+	 * Until that is fixed, when running on ISS, we will set baudh to !0
+	 */
+	if (gd->arch.running_on_hw)
+		writeb((arc_console_baud & 0xff00) >> 8, &regs->baudh);
+	else
+		writeb(1, &regs->baudh);
+#else
+	writeb((arc_console_baud & 0xff00) >> 8, &regs->baudh);
+#endif
+}
+
+static int arc_serial_init(void)
+{
+	regs = (struct arc_serial_regs *)CONFIG_ARC_UART_BASE;
+	serial_setbrg();
+	return 0;
+}
+
+static void arc_serial_putc(const char c)
+{
+	if (c == '\n')
+		arc_serial_putc('\r');
+
+	while (!(readb(&regs->status) & UART_TXEMPTY))
+		;
+
+	writeb(c, &regs->data);
+}
+
+static int arc_serial_tstc(void)
+{
+	return !(readb(&regs->status) & UART_RXEMPTY);
+}
+
+static int arc_serial_getc(void)
+{
+	while (!arc_serial_tstc())
+		;
+
+	/* Check for overflow errors */
+	if (readb(&regs->status) & UART_OVERFLOW_ERR)
+		return 0;
+
+	return readb(&regs->data) & 0xFF;
+}
+
+static struct serial_device arc_serial_drv = {
+	.name	= "arc_serial",
+	.start	= arc_serial_init,
+	.stop	= NULL,
+	.setbrg	= arc_serial_setbrg,
+	.putc	= arc_serial_putc,
+	.puts	= default_serial_puts,
+	.getc	= arc_serial_getc,
+	.tstc	= arc_serial_tstc,
+};
+
+void arc_serial_initialize(void)
+{
+	serial_register(&arc_serial_drv);
+}
+
+__weak struct serial_device *default_serial_console(void)
+{
+	return &arc_serial_drv;
+}
diff --git a/drivers/serial/serial_ixp.c b/drivers/serial/serial_ixp.c
deleted file mode 100644
index b9d0f5bfa5..0000000000
--- a/drivers/serial/serial_ixp.c
+++ /dev/null
@@ -1,130 +0,0 @@
-/*
- * (C) Copyright 2002
- * Wolfgang Denk, DENX Software Engineering, <wd@denx.de>
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Alex Zuepke <azu@sysgo.de>
- *
- * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl)
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/arch/ixp425.h>
-#include <watchdog.h>
-#include <serial.h>
-#include <linux/compiler.h>
-
-/*
- *               14.7456 MHz
- * Baud Rate = --------------
- *              16 x Divisor
- */
-#define SERIAL_CLOCK 921600
-
-DECLARE_GLOBAL_DATA_PTR;
-
-static void ixp_serial_setbrg(void)
-{
-	unsigned int quot = 0;
-	int uart = CONFIG_SYS_IXP425_CONSOLE;
-
-	if ((gd->baudrate <= SERIAL_CLOCK) && (SERIAL_CLOCK % gd->baudrate == 0))
-		quot = SERIAL_CLOCK / gd->baudrate;
-	else
-		hang ();
-
-	IER(uart) = 0;					/* Disable for now */
-	FCR(uart) = 0;					/* No fifos enabled */
-
-	/* set baud rate */
-	LCR(uart) = LCR_WLS0 | LCR_WLS1 | LCR_DLAB;
-	DLL(uart) = quot & 0xff;
-	DLH(uart) = quot >> 8;
-	LCR(uart) = LCR_WLS0 | LCR_WLS1;
-#ifdef CONFIG_SERIAL_RTS_ACTIVE
-	MCR(uart) = MCR_RTS;				/* set RTS active */
-#else
-	MCR(uart) = 0;					/* set RTS inactive */
-#endif
-	IER(uart) = IER_UUE;
-}
-
-/*
- * Initialise the serial port with the given baudrate. The settings
- * are always 8 data bits, no parity, 1 stop bit, no start bits.
- *
- */
-static int ixp_serial_init(void)
-{
-	serial_setbrg ();
-
-	return (0);
-}
-
-
-/*
- * Output a single byte to the serial port.
- */
-static void ixp_serial_putc(const char c)
-{
-	/* wait for room in the tx FIFO on UART */
-	while ((LSR(CONFIG_SYS_IXP425_CONSOLE) & LSR_TEMT) == 0)
-		WATCHDOG_RESET();	/* Reset HW Watchdog, if needed */
-
-	THR(CONFIG_SYS_IXP425_CONSOLE) = c;
-
-	/* If \n, also do \r */
-	if (c == '\n')
-		serial_putc ('\r');
-}
-
-/*
- * Read a single byte from the serial port. Returns 1 on success, 0
- * otherwise. When the function is succesfull, the character read is
- * written into its argument c.
- */
-static int ixp_serial_tstc(void)
-{
-	return LSR(CONFIG_SYS_IXP425_CONSOLE) & LSR_DR;
-}
-
-/*
- * Read a single byte from the serial port. Returns 1 on success, 0
- * otherwise. When the function is succesfull, the character read is
- * written into its argument c.
- */
-static int ixp_serial_getc(void)
-{
-	while (!(LSR(CONFIG_SYS_IXP425_CONSOLE) & LSR_DR))
-		WATCHDOG_RESET();	/* Reset HW Watchdog, if needed */
-
-	return (char) RBR(CONFIG_SYS_IXP425_CONSOLE) & 0xff;
-}
-
-static struct serial_device ixp_serial_drv = {
-	.name	= "ixp_serial",
-	.start	= ixp_serial_init,
-	.stop	= NULL,
-	.setbrg	= ixp_serial_setbrg,
-	.putc	= ixp_serial_putc,
-	.puts	= default_serial_puts,
-	.getc	= ixp_serial_getc,
-	.tstc	= ixp_serial_tstc,
-};
-
-void ixp_serial_initialize(void)
-{
-	serial_register(&ixp_serial_drv);
-}
-
-__weak struct serial_device *default_serial_console(void)
-{
-	return &ixp_serial_drv;
-}
diff --git a/drivers/serial/serial_s5p.c b/drivers/serial/serial_s5p.c
index f98b422632..98c62b4c14 100644
--- a/drivers/serial/serial_s5p.c
+++ b/drivers/serial/serial_s5p.c
@@ -65,7 +65,7 @@ static const int udivslot[] = {
 	0xffdf,
 };
 
-void serial_setbrg_dev(const int dev_index)
+static void serial_setbrg_dev(const int dev_index)
 {
 	struct s5p_uart *const uart = s5p_get_base_uart(dev_index);
 	u32 uclk = get_uart_clk(dev_index);
@@ -96,12 +96,12 @@ void serial_setbrg_dev(const int dev_index)
  * Initialise the serial port with the given baudrate. The settings
  * are always 8 data bits, no parity, 1 stop bit, no start bits.
  */
-int serial_init_dev(const int dev_index)
+static int serial_init_dev(const int dev_index)
 {
 	struct s5p_uart *const uart = s5p_get_base_uart(dev_index);
 
-	/* enable FIFOs */
-	writel(0x1, &uart->ufcon);
+	/* enable FIFOs, auto clear Rx FIFO */
+	writel(0x3, &uart->ufcon);
 	writel(0, &uart->umcon);
 	/* 8N1 */
 	writel(0x3, &uart->ulcon);
@@ -138,7 +138,7 @@ static int serial_err_check(const int dev_index, int op)
  * otherwise. When the function is succesfull, the character read is
  * written into its argument c.
  */
-int serial_getc_dev(const int dev_index)
+static int serial_getc_dev(const int dev_index)
 {
 	struct s5p_uart *const uart = s5p_get_base_uart(dev_index);
 
@@ -158,7 +158,7 @@ int serial_getc_dev(const int dev_index)
 /*
  * Output a single byte to the serial port.
  */
-void serial_putc_dev(const char c, const int dev_index)
+static void serial_putc_dev(const char c, const int dev_index)
 {
 	struct s5p_uart *const uart = s5p_get_base_uart(dev_index);
 
@@ -181,7 +181,7 @@ void serial_putc_dev(const char c, const int dev_index)
 /*
  * Test whether a character is in the RX buffer
  */
-int serial_tstc_dev(const int dev_index)
+static int serial_tstc_dev(const int dev_index)
 {
 	struct s5p_uart *const uart = s5p_get_base_uart(dev_index);
 
@@ -191,7 +191,7 @@ int serial_tstc_dev(const int dev_index)
 	return (int)(readl(&uart->utrstat) & 0x1);
 }
 
-void serial_puts_dev(const char *s, const int dev_index)
+static void serial_puts_dev(const char *s, const int dev_index)
 {
 	while (*s)
 		serial_putc_dev(*s++, dev_index);
@@ -199,12 +199,12 @@ void serial_puts_dev(const char *s, const int dev_index)
 
 /* Multi serial device functions */
 #define DECLARE_S5P_SERIAL_FUNCTIONS(port) \
-int s5p_serial##port##_init(void) { return serial_init_dev(port); } \
-void s5p_serial##port##_setbrg(void) { serial_setbrg_dev(port); } \
-int s5p_serial##port##_getc(void) { return serial_getc_dev(port); } \
-int s5p_serial##port##_tstc(void) { return serial_tstc_dev(port); } \
-void s5p_serial##port##_putc(const char c) { serial_putc_dev(c, port); } \
-void s5p_serial##port##_puts(const char *s) { serial_puts_dev(s, port); }
+static int s5p_serial##port##_init(void) { return serial_init_dev(port); } \
+static void s5p_serial##port##_setbrg(void) { serial_setbrg_dev(port); } \
+static int s5p_serial##port##_getc(void) { return serial_getc_dev(port); } \
+static int s5p_serial##port##_tstc(void) { return serial_tstc_dev(port); } \
+static void s5p_serial##port##_putc(const char c) { serial_putc_dev(c, port); } \
+static void s5p_serial##port##_puts(const char *s) { serial_puts_dev(s, port); }
 
 #define INIT_S5P_SERIAL_STRUCTURE(port, __name) {	\
 	.name	= __name,				\
diff --git a/drivers/serial/serial_sh.c b/drivers/serial/serial_sh.c
index ff2cdc5847..0826d59ab2 100644
--- a/drivers/serial/serial_sh.c
+++ b/drivers/serial/serial_sh.c
@@ -1,5 +1,6 @@
 /*
  * SuperH SCIF device driver.
+ * Copyright (C) 2013  Renesas Electronics Corporation
  * Copyright (C) 2007,2008,2010 Nobuhiro Iwamatsu
  * Copyright (C) 2002 - 2008  Paul Mundt
  *
@@ -48,7 +49,9 @@ static struct uart_port sh_sci = {
 static void sh_serial_setbrg(void)
 {
 	DECLARE_GLOBAL_DATA_PTR;
-	sci_out(&sh_sci, SCBRR, SCBRR_VALUE(gd->baudrate, CONFIG_SYS_CLK_FREQ));
+
+	sci_out(&sh_sci, SCBRR,
+		SCBRR_VALUE(gd->baudrate, CONFIG_SH_SCIF_CLK_FREQ));
 }
 
 static int sh_serial_init(void)
diff --git a/drivers/serial/serial_sh.h b/drivers/serial/serial_sh.h
index 7e38a3fd53..f5e9854d13 100644
--- a/drivers/serial/serial_sh.h
+++ b/drivers/serial/serial_sh.h
@@ -143,7 +143,9 @@ struct uart_port {
 #elif defined(CONFIG_H8S2678)
 # define SCSCR_INIT(port)          0x30 /* TIE=0,RIE=0,TE=1,RE=1 */
 # define H8300_SCI_DR(ch) (*(volatile char *)(P1DR + h8300_sci_pins[ch].port))
-#elif defined(CONFIG_CPU_SH7757) || defined(CONFIG_CPU_SH7752)
+#elif defined(CONFIG_CPU_SH7757) || \
+	defined(CONFIG_CPU_SH7752) || \
+	defined(CONFIG_CPU_SH7753)
 # define SCSPTR0 0xfe4b0020
 # define SCSPTR1 0xfe4b0020
 # define SCSPTR2 0xfe4b0020
@@ -224,6 +226,9 @@ struct uart_port {
 # define SCSPTR3 0xffc60020		/* 16 bit SCIF */
 # define SCIF_ORER 0x0001		/* Overrun error bit */
 # define SCSCR_INIT(port)	0x38	/* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
+#elif defined(CONFIG_R8A7790) || defined(CONFIG_R8A7791)
+# define SCIF_ORER	0x0001
+# define SCSCR_INIT(port)	0x32	/* TIE=0,RIE=0,TE=1,RE=1,REIE=0, */
 #else
 # error CPU subtype not defined
 #endif
@@ -298,6 +303,9 @@ struct uart_port {
 /* SH7763 SCIF2 support */
 # define SCIF2_RFDC_MASK 0x001f
 # define SCIF2_TXROOM_MAX 16
+#elif defined(CONFIG_R8A7790) || defined(CONFIG_R8A7791)
+# define SCIF_ERRORS (SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK)
+# define SCIF_RFDC_MASK	0x003f
 #else
 # define SCIF_ERRORS (SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK)
 # define SCIF_RFDC_MASK 0x001f
@@ -579,6 +587,10 @@ SCIF_FNS(SCSPTR,                        0,  0, 0, 0)
 #else
 SCIF_FNS(SCSPTR,                        0,  0, 0x20, 16)
 #endif
+#if defined(CONFIG_R8A7790) || defined(CONFIG_R8A7791)
+SCIF_FNS(DL,				0,  0, 0x30, 16)
+SCIF_FNS(CKS,				0,  0, 0x34, 16)
+#endif
 SCIF_FNS(SCLSR,                         0,  0, 0x24, 16)
 #endif
 #endif
@@ -720,6 +732,9 @@ static inline int scbrr_calc(struct uart_port port, int bps, int clk)
 #define SCBRR_VALUE(bps, clk) scbrr_calc(sh_sci, bps, clk)
 #elif defined(__H8300H__) || defined(__H8300S__)
 #define SCBRR_VALUE(bps, clk) (((clk*1000/32)/bps)-1)
+#elif defined(CONFIG_R8A7790) || defined(CONFIG_R8A7791)
+#define SCBRR DL
+#define SCBRR_VALUE(bps, clk) (clk / bps / 16)
 #else /* Generic SH */
 #define SCBRR_VALUE(bps, clk) ((clk+16*bps)/(32*bps)-1)
 #endif
diff --git a/drivers/serial/serial_xuartlite.c b/drivers/serial/serial_xuartlite.c
index 9c1d025c40..988438e754 100644
--- a/drivers/serial/serial_xuartlite.c
+++ b/drivers/serial/serial_xuartlite.c
@@ -18,10 +18,14 @@
 #define SR_RX_FIFO_VALID_DATA	0x01 /* data in receive FIFO */
 #define SR_RX_FIFO_FULL		0x02 /* receive FIFO full */
 
+#define ULITE_CONTROL_RST_TX	0x01
+#define ULITE_CONTROL_RST_RX	0x02
+
 struct uartlite {
 	unsigned int rx_fifo;
 	unsigned int tx_fifo;
 	unsigned int status;
+	unsigned int control;
 };
 
 static struct uartlite *userial_ports[4] = {
@@ -39,7 +43,7 @@ static struct uartlite *userial_ports[4] = {
 #endif
 };
 
-void uartlite_serial_putc(const char c, const int port)
+static void uartlite_serial_putc(const char c, const int port)
 {
 	struct uartlite *regs = userial_ports[port];
 
@@ -51,13 +55,13 @@ void uartlite_serial_putc(const char c, const int port)
 	out_be32(&regs->tx_fifo, c & 0xff);
 }
 
-void uartlite_serial_puts(const char *s, const int port)
+static void uartlite_serial_puts(const char *s, const int port)
 {
 	while (*s)
 		uartlite_serial_putc(*s++, port);
 }
 
-int uartlite_serial_getc(const int port)
+static int uartlite_serial_getc(const int port)
 {
 	struct uartlite *regs = userial_ports[port];
 
@@ -66,7 +70,7 @@ int uartlite_serial_getc(const int port)
 	return in_be32(&regs->rx_fifo) & 0xff;
 }
 
-int uartlite_serial_tstc(const int port)
+static int uartlite_serial_tstc(const int port)
 {
 	struct uartlite *regs = userial_ports[port];
 
@@ -75,23 +79,31 @@ int uartlite_serial_tstc(const int port)
 
 static int uartlite_serial_init(const int port)
 {
-	if (userial_ports[port])
+	struct uartlite *regs = userial_ports[port];
+
+	if (regs) {
+		out_be32(&regs->control, 0);
+		out_be32(&regs->control,
+			 ULITE_CONTROL_RST_RX | ULITE_CONTROL_RST_TX);
+		in_be32(&regs->control);
 		return 0;
+	}
+
 	return -1;
 }
 
 /* Multi serial device functions */
 #define DECLARE_ESERIAL_FUNCTIONS(port) \
-	int userial##port##_init(void) \
+	static int userial##port##_init(void) \
 				{ return uartlite_serial_init(port); } \
-	void userial##port##_setbrg(void) {} \
-	int userial##port##_getc(void) \
+	static void userial##port##_setbrg(void) {} \
+	static int userial##port##_getc(void) \
 				{ return uartlite_serial_getc(port); } \
-	int userial##port##_tstc(void) \
+	static int userial##port##_tstc(void) \
 				{ return uartlite_serial_tstc(port); } \
-	void userial##port##_putc(const char c) \
+	static void userial##port##_putc(const char c) \
 				{ uartlite_serial_putc(c, port); } \
-	void userial##port##_puts(const char *s) \
+	static void userial##port##_puts(const char *s) \
 				{ uartlite_serial_puts(s, port); }
 
 /* Serial device descriptor */
diff --git a/drivers/serial/serial_zynq.c b/drivers/serial/serial_zynq.c
index 050b9c0625..53a8af02d6 100644
--- a/drivers/serial/serial_zynq.c
+++ b/drivers/serial/serial_zynq.c
@@ -6,10 +6,15 @@
  */
 
 #include <common.h>
+#include <fdtdec.h>
 #include <watchdog.h>
 #include <asm/io.h>
 #include <linux/compiler.h>
 #include <serial.h>
+#include <asm/arch/clk.h>
+#include <asm/arch/hardware.h>
+
+DECLARE_GLOBAL_DATA_PTR;
 
 #define ZYNQ_UART_SR_TXFULL	0x00000010 /* TX FIFO full */
 #define ZYNQ_UART_SR_RXEMPTY	0x00000002 /* RX FIFO empty */
@@ -21,10 +26,6 @@
 
 #define ZYNQ_UART_MR_PARITY_NONE	0x00000020  /* No parity mode */
 
-/* Some clock/baud constants */
-#define ZYNQ_UART_BDIV	15 /* Default/reset BDIV value */
-#define ZYNQ_UART_BASECLK	3125000L /* master / (bdiv + 1) */
-
 struct uart_zynq {
 	u32 control; /* Control Register [8:0] */
 	u32 mode; /* Mode Register [10:0] */
@@ -37,28 +38,24 @@ struct uart_zynq {
 };
 
 static struct uart_zynq *uart_zynq_ports[2] = {
-#ifdef CONFIG_ZYNQ_SERIAL_BASEADDR0
-	[0] = (struct uart_zynq *)CONFIG_ZYNQ_SERIAL_BASEADDR0,
+	[0] = (struct uart_zynq *)ZYNQ_SERIAL_BASEADDR0,
+	[1] = (struct uart_zynq *)ZYNQ_SERIAL_BASEADDR1,
+};
+
+#if !defined(CONFIG_ZYNQ_SERIAL_BAUDRATE0)
+# define CONFIG_ZYNQ_SERIAL_BAUDRATE0	CONFIG_BAUDRATE
 #endif
-#ifdef CONFIG_ZYNQ_SERIAL_BASEADDR1
-	[1] = (struct uart_zynq *)CONFIG_ZYNQ_SERIAL_BASEADDR1,
+#if !defined(CONFIG_ZYNQ_SERIAL_BAUDRATE1)
+# define CONFIG_ZYNQ_SERIAL_BAUDRATE1	CONFIG_BAUDRATE
 #endif
-};
 
 struct uart_zynq_params {
 	u32 baudrate;
-	u32 clock;
 };
 
 static struct uart_zynq_params uart_zynq_ports_param[2] = {
-#if defined(CONFIG_ZYNQ_SERIAL_BAUDRATE0) && defined(CONFIG_ZYNQ_SERIAL_CLOCK0)
 	[0].baudrate = CONFIG_ZYNQ_SERIAL_BAUDRATE0,
-	[0].clock = CONFIG_ZYNQ_SERIAL_CLOCK0,
-#endif
-#if defined(CONFIG_ZYNQ_SERIAL_BAUDRATE1) && defined(CONFIG_ZYNQ_SERIAL_CLOCK1)
 	[1].baudrate = CONFIG_ZYNQ_SERIAL_BAUDRATE1,
-	[1].clock = CONFIG_ZYNQ_SERIAL_CLOCK1,
-#endif
 };
 
 /* Set up the baud rate in gd struct */
@@ -68,7 +65,7 @@ static void uart_zynq_serial_setbrg(const int port)
 	unsigned int calc_bauderror, bdiv, bgen;
 	unsigned long calc_baud = 0;
 	unsigned long baud = uart_zynq_ports_param[port].baudrate;
-	unsigned long clock = uart_zynq_ports_param[port].clock;
+	unsigned long clock = get_uart_clk(port);
 	struct uart_zynq *regs = uart_zynq_ports[port];
 
 	/*                master clock
@@ -188,22 +185,46 @@ DECLARE_PSSERIAL_FUNCTIONS(1);
 struct serial_device uart_zynq_serial1_device =
 	INIT_PSSERIAL_STRUCTURE(1, "ttyPS1");
 
+#ifdef CONFIG_OF_CONTROL
+__weak struct serial_device *default_serial_console(void)
+{
+	const void *blob = gd->fdt_blob;
+	int node;
+	unsigned int base_addr;
+
+	node = fdt_path_offset(blob, "serial0");
+	if (node < 0)
+		return NULL;
+
+	base_addr = fdtdec_get_addr(blob, node, "reg");
+	if (base_addr == FDT_ADDR_T_NONE)
+		return NULL;
+
+	if (base_addr == ZYNQ_SERIAL_BASEADDR0)
+		return &uart_zynq_serial0_device;
+
+	if (base_addr == ZYNQ_SERIAL_BASEADDR1)
+		return &uart_zynq_serial1_device;
+
+	return NULL;
+}
+#else
 __weak struct serial_device *default_serial_console(void)
 {
+#if defined(CONFIG_ZYNQ_SERIAL_UART0)
 	if (uart_zynq_ports[0])
 		return &uart_zynq_serial0_device;
+#endif
+#if defined(CONFIG_ZYNQ_SERIAL_UART1)
 	if (uart_zynq_ports[1])
 		return &uart_zynq_serial1_device;
-
+#endif
 	return NULL;
 }
+#endif
 
 void zynq_serial_initalize(void)
 {
-#ifdef CONFIG_ZYNQ_SERIAL_BASEADDR0
 	serial_register(&uart_zynq_serial0_device);
-#endif
-#ifdef CONFIG_ZYNQ_SERIAL_BASEADDR1
 	serial_register(&uart_zynq_serial1_device);
-#endif
 }
diff --git a/drivers/serial/usbtty.h b/drivers/serial/usbtty.h
index e243a8e3b2..21a3ef4d97 100644
--- a/drivers/serial/usbtty.h
+++ b/drivers/serial/usbtty.h
@@ -16,16 +16,15 @@
 #include <usb/mpc8xx_udc.h>
 #elif defined(CONFIG_OMAP1510)
 #include <usb/omap1510_udc.h>
-#elif defined(CONFIG_MUSB_UDC)
-#include <usb/musb_udc.h>
 #elif defined(CONFIG_CPU_PXA27X)
 #include <usb/pxa27x_udc.h>
 #elif defined(CONFIG_DW_UDC)
 #include <usb/designware_udc.h>
-#elif defined(CONFIG_MV_UDC)
-#include <usb/mv_udc.h>
+#elif defined(CONFIG_CI_UDC)
+#include <usb/ci_udc.h>
 #endif
 
+#include <usb/udc.h>
 #include <version.h>
 
 /* If no VendorID/ProductID is defined in config.h, pretend to be Linux
diff --git a/drivers/sound/Makefile b/drivers/sound/Makefile
index c50dd1583f..981ed614b1 100644
--- a/drivers/sound/Makefile
+++ b/drivers/sound/Makefile
@@ -5,29 +5,9 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	:= $(obj)libsound.o
-
-COBJS-$(CONFIG_SOUND)	+= sound.o
-COBJS-$(CONFIG_I2S)	+= samsung-i2s.o
-COBJS-$(CONFIG_SOUND_WM8994)	+= wm8994.o
-COBJS-$(CONFIG_SOUND_MAX98095)	+= max98095.o
-
-COBJS	:= $(COBJS-y)
-SRCS	:= $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-
-all:	$(LIB)
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#
+obj-$(CONFIG_SOUND)	+= sound.o
+obj-$(CONFIG_I2S)	+= sound-i2s.o
+obj-$(CONFIG_I2S_SAMSUNG)	+= samsung-i2s.o
+obj-$(CONFIG_SOUND_SANDBOX)	+= sandbox.o
+obj-$(CONFIG_SOUND_WM8994)	+= wm8994.o
+obj-$(CONFIG_SOUND_MAX98095)	+= max98095.o
diff --git a/drivers/sound/sandbox.c b/drivers/sound/sandbox.c
new file mode 100644
index 0000000000..fe5c9e9b38
--- /dev/null
+++ b/drivers/sound/sandbox.c
@@ -0,0 +1,23 @@
+/*
+ * Copyright (c) 2013 Google, Inc
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/sound.h>
+#include <asm/sdl.h>
+
+int sound_play(uint32_t msec, uint32_t frequency)
+{
+	sandbox_sdl_sound_start(frequency);
+	mdelay(msec);
+	sandbox_sdl_sound_stop();
+
+	return 0;
+}
+
+int sound_init(const void *blob)
+{
+	return sandbox_sdl_sound_init();
+}
diff --git a/drivers/sound/sound-i2s.c b/drivers/sound/sound-i2s.c
new file mode 100644
index 0000000000..749bbbd031
--- /dev/null
+++ b/drivers/sound/sound-i2s.c
@@ -0,0 +1,208 @@
+/*
+ * Copyright (C) 2012 Samsung Electronics
+ * R. Chandrasekar <rcsekar@samsung.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <malloc.h>
+#include <common.h>
+#include <asm/io.h>
+#include <libfdt.h>
+#include <fdtdec.h>
+#include <i2c.h>
+#include <i2s.h>
+#include <sound.h>
+#include <asm/arch/sound.h>
+#include "wm8994.h"
+#include "max98095.h"
+
+/* defines */
+#define SOUND_400_HZ 400
+#define SOUND_BITS_IN_BYTE 8
+
+static struct i2stx_info g_i2stx_pri;
+
+/*
+ * get_sound_i2s_values gets values for i2s parameters
+ *
+ * @param i2stx_info	i2s transmitter transfer param structure
+ * @param blob		FDT blob if enabled else NULL
+ */
+static int get_sound_i2s_values(struct i2stx_info *i2s, const void *blob)
+{
+	int node;
+	int error = 0;
+	int base;
+
+	node = fdt_path_offset(blob, "i2s");
+	if (node <= 0) {
+		debug("EXYNOS_SOUND: No node for sound in device tree\n");
+		return -1;
+	}
+
+	/*
+	 * Get the pre-defined sound specific values from FDT.
+	 * All of these are expected to be correct otherwise
+	 * wrong register values in i2s setup parameters
+	 * may result in no sound play.
+	 */
+	base = fdtdec_get_addr(blob, node, "reg");
+	if (base == FDT_ADDR_T_NONE) {
+		debug("%s: Missing  i2s base\n", __func__);
+		return -1;
+	}
+	i2s->base_address = base;
+
+	i2s->audio_pll_clk = fdtdec_get_int(blob,
+				node, "samsung,i2s-epll-clock-frequency", -1);
+	error |= i2s->audio_pll_clk;
+	debug("audio_pll_clk = %d\n", i2s->audio_pll_clk);
+	i2s->samplingrate = fdtdec_get_int(blob,
+				node, "samsung,i2s-sampling-rate", -1);
+	error |= i2s->samplingrate;
+	debug("samplingrate = %d\n", i2s->samplingrate);
+	i2s->bitspersample = fdtdec_get_int(blob,
+				node, "samsung,i2s-bits-per-sample", -1);
+	error |= i2s->bitspersample;
+	debug("bitspersample = %d\n", i2s->bitspersample);
+	i2s->channels = fdtdec_get_int(blob,
+			node, "samsung,i2s-channels", -1);
+	error |= i2s->channels;
+	debug("channels = %d\n", i2s->channels);
+	i2s->rfs = fdtdec_get_int(blob,
+				node, "samsung,i2s-lr-clk-framesize", -1);
+	error |= i2s->rfs;
+	debug("rfs = %d\n", i2s->rfs);
+	i2s->bfs = fdtdec_get_int(blob,
+				node, "samsung,i2s-bit-clk-framesize", -1);
+	error |= i2s->bfs;
+	debug("bfs = %d\n", i2s->bfs);
+
+	i2s->id = fdtdec_get_int(blob, node, "samsung,i2s-id", -1);
+	error |= i2s->id;
+	debug("id = %d\n", i2s->id);
+
+	if (error == -1) {
+		debug("fail to get sound i2s node properties\n");
+		return -1;
+	}
+
+	return 0;
+}
+
+/*
+ * Init codec
+ *
+ * @param blob          FDT blob
+ * @param pi2s_tx	i2s parameters required by codec
+ * @return              int value, 0 for success
+ */
+static int codec_init(const void *blob, struct i2stx_info *pi2s_tx)
+{
+	int ret;
+	const char *codectype;
+	int node;
+
+	/* Get the node from FDT for sound */
+	node = fdt_path_offset(blob, "i2s");
+	if (node <= 0) {
+		debug("EXYNOS_SOUND: No node for sound in device tree\n");
+		debug("node = %d\n", node);
+		return -1;
+	}
+
+	/*
+	 * Get the pre-defined sound codec specific values from FDT.
+	 * All of these are expected to be correct otherwise sound
+	 * can not be played
+	 */
+	codectype = fdt_getprop(blob, node, "samsung,codec-type", NULL);
+	debug("device = %s\n", codectype);
+	if (!strcmp(codectype, "wm8994")) {
+		/* Check the codec type and initialise the same */
+		ret = wm8994_init(blob, pi2s_tx->id + 1,
+				  pi2s_tx->samplingrate,
+				  (pi2s_tx->samplingrate * (pi2s_tx->rfs)),
+				  pi2s_tx->bitspersample, pi2s_tx->channels);
+	} else if (!strcmp(codectype, "max98095")) {
+		ret = max98095_init(blob, pi2s_tx->id + 1,
+				    pi2s_tx->samplingrate,
+				    (pi2s_tx->samplingrate * (pi2s_tx->rfs)),
+				    pi2s_tx->bitspersample);
+	} else {
+		debug("%s: Unknown codec type %s\n", __func__, codectype);
+		return -1;
+	}
+
+	if (ret) {
+		debug("%s: Codec init failed\n", __func__);
+		return -1;
+	}
+
+	return 0;
+}
+
+int sound_init(const void *blob)
+{
+	int ret;
+	struct i2stx_info *pi2s_tx = &g_i2stx_pri;
+
+	/* Get the I2S Values */
+	if (get_sound_i2s_values(pi2s_tx, blob) < 0) {
+		debug(" FDT I2S values failed\n");
+		return -1;
+	}
+
+	if (codec_init(blob, pi2s_tx) < 0) {
+		debug(" Codec init failed\n");
+		return -1;
+	}
+
+	ret = i2s_tx_init(pi2s_tx);
+	if (ret) {
+		debug("%s: Failed to init i2c transmit: ret=%d\n", __func__,
+		      ret);
+		return ret;
+	}
+
+
+	return ret;
+}
+
+int sound_play(uint32_t msec, uint32_t frequency)
+{
+	unsigned int *data;
+	unsigned long data_size;
+	unsigned int ret = 0;
+
+	/*Buffer length computation */
+	data_size = g_i2stx_pri.samplingrate * g_i2stx_pri.channels;
+	data_size *= (g_i2stx_pri.bitspersample / SOUND_BITS_IN_BYTE);
+	data = malloc(data_size);
+
+	if (data == NULL) {
+		debug("%s: malloc failed\n", __func__);
+		return -1;
+	}
+
+	sound_create_square_wave((unsigned short *)data,
+				 data_size / sizeof(unsigned short),
+				 frequency);
+
+	while (msec >= 1000) {
+		ret = i2s_transfer_tx_data(&g_i2stx_pri, data,
+					   (data_size / sizeof(int)));
+		msec -= 1000;
+	}
+	if (msec) {
+		unsigned long size =
+			(data_size * msec) / (sizeof(int) * 1000);
+
+		ret = i2s_transfer_tx_data(&g_i2stx_pri, data, size);
+	}
+
+	free(data);
+
+	return ret;
+}
diff --git a/drivers/sound/sound.c b/drivers/sound/sound.c
index 9b8ce5a9ef..9dda2dba82 100644
--- a/drivers/sound/sound.c
+++ b/drivers/sound/sound.c
@@ -5,193 +5,10 @@
  * SPDX-License-Identifier:	GPL-2.0+
  */
 
-#include <malloc.h>
 #include <common.h>
-#include <asm/io.h>
-#include <libfdt.h>
-#include <fdtdec.h>
-#include <i2c.h>
-#include <i2s.h>
 #include <sound.h>
-#include <asm/arch/sound.h>
-#include "wm8994.h"
-#include "max98095.h"
 
-/* defines */
-#define SOUND_400_HZ 400
-#define SOUND_BITS_IN_BYTE 8
-
-static struct i2stx_info g_i2stx_pri;
-
-/*
- * get_sound_i2s_values gets values for i2s parameters
- *
- * @param i2stx_info	i2s transmitter transfer param structure
- * @param blob		FDT blob if enabled else NULL
- */
-static int get_sound_i2s_values(struct i2stx_info *i2s, const void *blob)
-{
-#ifdef CONFIG_OF_CONTROL
-	int node;
-	int error = 0;
-	int base;
-
-	node = fdt_path_offset(blob, "i2s");
-	if (node <= 0) {
-		debug("EXYNOS_SOUND: No node for sound in device tree\n");
-		return -1;
-	}
-
-	/*
-	 * Get the pre-defined sound specific values from FDT.
-	 * All of these are expected to be correct otherwise
-	 * wrong register values in i2s setup parameters
-	 * may result in no sound play.
-	 */
-	base = fdtdec_get_addr(blob, node, "reg");
-	if (base == FDT_ADDR_T_NONE) {
-		debug("%s: Missing  i2s base\n", __func__);
-		return -1;
-	}
-	i2s->base_address = base;
-
-	i2s->audio_pll_clk = fdtdec_get_int(blob,
-				node, "samsung,i2s-epll-clock-frequency", -1);
-	error |= i2s->audio_pll_clk;
-	debug("audio_pll_clk = %d\n", i2s->audio_pll_clk);
-	i2s->samplingrate = fdtdec_get_int(blob,
-				node, "samsung,i2s-sampling-rate", -1);
-	error |= i2s->samplingrate;
-	debug("samplingrate = %d\n", i2s->samplingrate);
-	i2s->bitspersample = fdtdec_get_int(blob,
-				node, "samsung,i2s-bits-per-sample", -1);
-	error |= i2s->bitspersample;
-	debug("bitspersample = %d\n", i2s->bitspersample);
-	i2s->channels = fdtdec_get_int(blob,
-			node, "samsung,i2s-channels", -1);
-	error |= i2s->channels;
-	debug("channels = %d\n", i2s->channels);
-	i2s->rfs = fdtdec_get_int(blob,
-				node, "samsung,i2s-lr-clk-framesize", -1);
-	error |= i2s->rfs;
-	debug("rfs = %d\n", i2s->rfs);
-	i2s->bfs = fdtdec_get_int(blob,
-				node, "samsung,i2s-bit-clk-framesize", -1);
-	error |= i2s->bfs;
-	debug("bfs = %d\n", i2s->bfs);
-
-	i2s->id = fdtdec_get_int(blob, node, "samsung,i2s-id", -1);
-	error |= i2s->id;
-	debug("id = %d\n", i2s->id);
-
-	if (error == -1) {
-		debug("fail to get sound i2s node properties\n");
-		return -1;
-	}
-#else
-	i2s->base_address = samsung_get_base_i2s();
-	i2s->audio_pll_clk = I2S_PLL_CLK;
-	i2s->samplingrate = I2S_SAMPLING_RATE;
-	i2s->bitspersample = I2S_BITS_PER_SAMPLE;
-	i2s->channels = I2S_CHANNELS;
-	i2s->rfs = I2S_RFS;
-	i2s->bfs = I2S_BFS;
-	i2s->id = 0;
-#endif
-	return 0;
-}
-
-/*
- * Init codec
- *
- * @param blob          FDT blob
- * @param pi2s_tx	i2s parameters required by codec
- * @return              int value, 0 for success
- */
-static int codec_init(const void *blob, struct i2stx_info *pi2s_tx)
-{
-	int ret;
-	const char *codectype;
-#ifdef CONFIG_OF_CONTROL
-	int node;
-
-	/* Get the node from FDT for sound */
-	node = fdt_path_offset(blob, "i2s");
-	if (node <= 0) {
-		debug("EXYNOS_SOUND: No node for sound in device tree\n");
-		debug("node = %d\n", node);
-		return -1;
-	}
-
-	/*
-	 * Get the pre-defined sound codec specific values from FDT.
-	 * All of these are expected to be correct otherwise sound
-	 * can not be played
-	 */
-	codectype = fdt_getprop(blob, node, "samsung,codec-type", NULL);
-	debug("device = %s\n", codectype);
-#else
-	codectype =  AUDIO_CODEC;
-#endif
-	if (!strcmp(codectype, "wm8994")) {
-		/* Check the codec type and initialise the same */
-		ret = wm8994_init(blob, pi2s_tx->id + 1,
-				  pi2s_tx->samplingrate,
-				  (pi2s_tx->samplingrate * (pi2s_tx->rfs)),
-				  pi2s_tx->bitspersample, pi2s_tx->channels);
-	} else if (!strcmp(codectype, "max98095")) {
-		ret = max98095_init(blob, pi2s_tx->id + 1,
-				    pi2s_tx->samplingrate,
-				    (pi2s_tx->samplingrate * (pi2s_tx->rfs)),
-				    pi2s_tx->bitspersample);
-	} else {
-		debug("%s: Unknown codec type %s\n", __func__, codectype);
-		return -1;
-	}
-
-	if (ret) {
-		debug("%s: Codec init failed\n", __func__);
-		return -1;
-	}
-
-	return 0;
-}
-
-int sound_init(const void *blob)
-{
-	int ret;
-	struct i2stx_info *pi2s_tx = &g_i2stx_pri;
-
-	/* Get the I2S Values */
-	if (get_sound_i2s_values(pi2s_tx, blob) < 0) {
-		debug(" FDT I2S values failed\n");
-		return -1;
-	}
-
-	if (codec_init(blob, pi2s_tx) < 0) {
-		debug(" Codec init failed\n");
-		return -1;
-	}
-
-	ret = i2s_tx_init(pi2s_tx);
-	if (ret) {
-		debug("%s: Failed to init i2c transmit: ret=%d\n", __func__,
-		      ret);
-		return ret;
-	}
-
-
-	return ret;
-}
-
-/*
- * Generates square wave sound data for 1 second
- *
- * @param data          data buffer pointer
- * @param size          size of the buffer
- * @param freq          frequency of the wave
- */
-static void sound_prepare_buffer(unsigned short *data, int size, uint32_t freq)
+void sound_create_square_wave(unsigned short *data, int size, uint32_t freq)
 {
 	const int sample = 48000;
 	const unsigned short amplitude = 16000; /* between 1 and 32767 */
@@ -218,39 +35,3 @@ static void sound_prepare_buffer(unsigned short *data, int size, uint32_t freq)
 		}
 	}
 }
-
-int sound_play(uint32_t msec, uint32_t frequency)
-{
-	unsigned int *data;
-	unsigned long data_size;
-	unsigned int ret = 0;
-
-	/*Buffer length computation */
-	data_size = g_i2stx_pri.samplingrate * g_i2stx_pri.channels;
-	data_size *= (g_i2stx_pri.bitspersample / SOUND_BITS_IN_BYTE);
-	data = malloc(data_size);
-
-	if (data == NULL) {
-		debug("%s: malloc failed\n", __func__);
-		return -1;
-	}
-
-	sound_prepare_buffer((unsigned short *)data,
-			     data_size / sizeof(unsigned short), frequency);
-
-	while (msec >= 1000) {
-		ret = i2s_transfer_tx_data(&g_i2stx_pri, data,
-					   (data_size / sizeof(int)));
-		msec -= 1000;
-	}
-	if (msec) {
-		unsigned long size =
-			(data_size * msec) / (sizeof(int) * 1000);
-
-		ret = i2s_transfer_tx_data(&g_i2stx_pri, data, size);
-	}
-
-	free(data);
-
-	return ret;
-}
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index e5941b09f6..81b6af6694 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -5,57 +5,38 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	:= $(obj)libspi.o
-
 # There are many options which enable SPI, so make this library available
-COBJS-y += spi.o
-
-COBJS-$(CONFIG_ALTERA_SPI) += altera_spi.o
-COBJS-$(CONFIG_ANDES_SPI) += andes_spi.o
-COBJS-$(CONFIG_ARMADA100_SPI) += armada100_spi.o
-COBJS-$(CONFIG_ATMEL_DATAFLASH_SPI) += atmel_dataflash_spi.o
-COBJS-$(CONFIG_ATMEL_SPI) += atmel_spi.o
-COBJS-$(CONFIG_BFIN_SPI) += bfin_spi.o
-COBJS-$(CONFIG_BFIN_SPI6XX) += bfin_spi6xx.o
-COBJS-$(CONFIG_CF_SPI) += cf_spi.o
-COBJS-$(CONFIG_CF_QSPI) += cf_qspi.o
-COBJS-$(CONFIG_DAVINCI_SPI) += davinci_spi.o
-COBJS-$(CONFIG_EXYNOS_SPI) += exynos_spi.o
-COBJS-$(CONFIG_ICH_SPI) +=  ich.o
-COBJS-$(CONFIG_KIRKWOOD_SPI) += kirkwood_spi.o
-COBJS-$(CONFIG_MPC52XX_SPI) += mpc52xx_spi.o
-COBJS-$(CONFIG_MPC8XXX_SPI) += mpc8xxx_spi.o
-COBJS-$(CONFIG_MXC_SPI) += mxc_spi.o
-COBJS-$(CONFIG_MXS_SPI) += mxs_spi.o
-COBJS-$(CONFIG_OC_TINY_SPI) += oc_tiny_spi.o
-COBJS-$(CONFIG_OMAP3_SPI) += omap3_spi.o
-COBJS-$(CONFIG_SOFT_SPI) += soft_spi.o
-COBJS-$(CONFIG_SH_SPI) += sh_spi.o
-COBJS-$(CONFIG_FSL_ESPI) += fsl_espi.o
-COBJS-$(CONFIG_FDT_SPI) += fdt_spi.o
-COBJS-$(CONFIG_TEGRA20_SFLASH) += tegra20_sflash.o
-COBJS-$(CONFIG_TEGRA20_SLINK) += tegra20_slink.o
-COBJS-$(CONFIG_TEGRA114_SPI) += tegra114_spi.o
-COBJS-$(CONFIG_TI_QSPI) += ti_qspi.o
-COBJS-$(CONFIG_XILINX_SPI) += xilinx_spi.o
-COBJS-$(CONFIG_ZYNQ_SPI) += zynq_spi.o
-
-COBJS	:= $(COBJS-y)
-SRCS	:= $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-
-all:	$(LIB)
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y += spi.o
+
+obj-$(CONFIG_ALTERA_SPI) += altera_spi.o
+obj-$(CONFIG_ANDES_SPI) += andes_spi.o
+obj-$(CONFIG_ARMADA100_SPI) += armada100_spi.o
+obj-$(CONFIG_ATMEL_DATAFLASH_SPI) += atmel_dataflash_spi.o
+obj-$(CONFIG_ATMEL_SPI) += atmel_spi.o
+obj-$(CONFIG_BFIN_SPI) += bfin_spi.o
+obj-$(CONFIG_BFIN_SPI6XX) += bfin_spi6xx.o
+obj-$(CONFIG_CF_SPI) += cf_spi.o
+obj-$(CONFIG_CF_QSPI) += cf_qspi.o
+obj-$(CONFIG_DAVINCI_SPI) += davinci_spi.o
+obj-$(CONFIG_EXYNOS_SPI) += exynos_spi.o
+obj-$(CONFIG_FTSSP010_SPI) += ftssp010_spi.o
+obj-$(CONFIG_ICH_SPI) +=  ich.o
+obj-$(CONFIG_KIRKWOOD_SPI) += kirkwood_spi.o
+obj-$(CONFIG_MPC52XX_SPI) += mpc52xx_spi.o
+obj-$(CONFIG_MPC8XXX_SPI) += mpc8xxx_spi.o
+obj-$(CONFIG_MXC_SPI) += mxc_spi.o
+obj-$(CONFIG_MXS_SPI) += mxs_spi.o
+obj-$(CONFIG_OC_TINY_SPI) += oc_tiny_spi.o
+obj-$(CONFIG_OMAP3_SPI) += omap3_spi.o
+obj-$(CONFIG_SANDBOX_SPI) += sandbox_spi.o
+obj-$(CONFIG_SOFT_SPI) += soft_spi.o
+obj-$(CONFIG_SH_SPI) += sh_spi.o
+obj-$(CONFIG_SH_QSPI) += sh_qspi.o
+obj-$(CONFIG_FSL_ESPI) += fsl_espi.o
+obj-$(CONFIG_FDT_SPI) += fdt_spi.o
+obj-$(CONFIG_TEGRA20_SFLASH) += tegra20_sflash.o
+obj-$(CONFIG_TEGRA20_SLINK) += tegra20_slink.o
+obj-$(CONFIG_TEGRA114_SPI) += tegra114_spi.o
+obj-$(CONFIG_TI_QSPI) += ti_qspi.o
+obj-$(CONFIG_XILINX_SPI) += xilinx_spi.o
+obj-$(CONFIG_ZYNQ_SPI) += zynq_spi.o
diff --git a/drivers/spi/atmel_dataflash_spi.c b/drivers/spi/atmel_dataflash_spi.c
index 8a5eddcbfd..a2e9c00ea6 100644
--- a/drivers/spi/atmel_dataflash_spi.c
+++ b/drivers/spi/atmel_dataflash_spi.c
@@ -102,33 +102,26 @@ void AT91F_SpiEnable(int cs)
 {
 	unsigned long mode;
 
+	mode = readl(ATMEL_BASE_SPI0 + AT91_SPI_MR);
+	mode &= ~AT91_SPI_PCS;
+
 	switch (cs) {
-	case 0:	/* Configure SPI CS0 for Serial DataFlash AT45DBxx */
-		mode = readl(ATMEL_BASE_SPI0 + AT91_SPI_MR);
-		mode &= 0xFFF0FFFF;
-		writel(mode | ((AT91_SPI_PCS0_DATAFLASH_CARD<<16) & AT91_SPI_PCS),
-		       ATMEL_BASE_SPI0 + AT91_SPI_MR);
+	case 0:
+		mode |= AT91_SPI_PCS0_DATAFLASH_CARD << 16;
 		break;
-	case 1:	/* Configure SPI CS1 for Serial DataFlash AT45DBxx */
-		mode = readl(ATMEL_BASE_SPI0 + AT91_SPI_MR);
-		mode &= 0xFFF0FFFF;
-		writel(mode | ((AT91_SPI_PCS1_DATAFLASH_CARD<<16) & AT91_SPI_PCS),
-		       ATMEL_BASE_SPI0 + AT91_SPI_MR);
+	case 1:
+		mode |= AT91_SPI_PCS1_DATAFLASH_CARD << 16;
 		break;
-	case 2:	/* Configure SPI CS2 for Serial DataFlash AT45DBxx */
-		mode = readl(ATMEL_BASE_SPI0 + AT91_SPI_MR);
-		mode &= 0xFFF0FFFF;
-		writel(mode | ((AT91_SPI_PCS2_DATAFLASH_CARD<<16) & AT91_SPI_PCS),
-		       ATMEL_BASE_SPI0 + AT91_SPI_MR);
+	case 2:
+		mode |= AT91_SPI_PCS2_DATAFLASH_CARD << 16;
 		break;
 	case 3:
-		mode = readl(ATMEL_BASE_SPI0 + AT91_SPI_MR);
-		mode &= 0xFFF0FFFF;
-		writel(mode | ((AT91_SPI_PCS3_DATAFLASH_CARD<<16) & AT91_SPI_PCS),
-		       ATMEL_BASE_SPI0 + AT91_SPI_MR);
+		mode |= AT91_SPI_PCS3_DATAFLASH_CARD << 16;
 		break;
 	}
 
+	writel(mode, ATMEL_BASE_SPI0 + AT91_SPI_MR);
+
 	/* SPI_Enable */
 	writel(AT91_SPI_SPIEN, ATMEL_BASE_SPI0 + AT91_SPI_CR);
 }
diff --git a/drivers/spi/bfin_spi.c b/drivers/spi/bfin_spi.c
index bb88f3008a..71a31d0127 100644
--- a/drivers/spi/bfin_spi.c
+++ b/drivers/spi/bfin_spi.c
@@ -13,6 +13,7 @@
 #include <spi.h>
 
 #include <asm/blackfin.h>
+#include <asm/clock.h>
 #include <asm/gpio.h>
 #include <asm/portmux.h>
 #include <asm/mach-common/bits/spi.h>
@@ -140,12 +141,12 @@ static const unsigned short cs_pins[][7] = {
 void spi_set_speed(struct spi_slave *slave, uint hz)
 {
 	struct bfin_spi_slave *bss = to_bfin_spi_slave(slave);
-	ulong sclk;
+	ulong clk;
 	u32 baud;
 
-	sclk = get_sclk();
+	clk = get_spi_clk();
 	/* baud should be rounded up */
-	baud = DIV_ROUND_UP(sclk, 2 * hz);
+	baud = DIV_ROUND_UP(clk, 2 * hz);
 	if (baud < 2)
 		baud = 2;
 	else if (baud > (u16)-1)
@@ -162,21 +163,22 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
 	if (!spi_cs_is_valid(bus, cs))
 		return NULL;
 
-	if (bus >= ARRAY_SIZE(pins) || pins[bus] == NULL) {
-		debug("%s: invalid bus %u\n", __func__, bus);
-		return NULL;
-	}
 	switch (bus) {
 #ifdef SPI0_CTL
-		case 0: mmr_base = SPI0_CTL; break;
+	case 0:
+		mmr_base = SPI0_CTL; break;
 #endif
 #ifdef SPI1_CTL
-		case 1: mmr_base = SPI1_CTL; break;
+	case 1:
+		mmr_base = SPI1_CTL; break;
 #endif
 #ifdef SPI2_CTL
-		case 2: mmr_base = SPI2_CTL; break;
+	case 2:
+		mmr_base = SPI2_CTL; break;
 #endif
-		default: return NULL;
+	default:
+		debug("%s: invalid bus %u\n", __func__, bus);
+		return NULL;
 	}
 
 	bss = spi_alloc_slave(struct bfin_spi_slave, bus, cs);
diff --git a/drivers/spi/bfin_spi6xx.c b/drivers/spi/bfin_spi6xx.c
index c25c4a9aea..eba01d16f5 100644
--- a/drivers/spi/bfin_spi6xx.c
+++ b/drivers/spi/bfin_spi6xx.c
@@ -22,6 +22,7 @@
 #include <spi.h>
 
 #include <asm/blackfin.h>
+#include <asm/clock.h>
 #include <asm/gpio.h>
 #include <asm/portmux.h>
 #include <asm/mach-common/bits/spi6xx.h>
@@ -135,11 +136,11 @@ static const unsigned short cs_pins[][7] = {
 void spi_set_speed(struct spi_slave *slave, uint hz)
 {
 	struct bfin_spi_slave *bss = to_bfin_spi_slave(slave);
-	ulong sclk;
+	ulong clk;
 	u32 clock;
 
-	sclk = get_sclk1();
-	clock = sclk / hz;
+	clk = get_spi_clk();
+	clock = clk / hz;
 	if (clock)
 		clock--;
 	bss->clock = clock;
@@ -154,10 +155,6 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
 	if (!spi_cs_is_valid(bus, cs))
 		return NULL;
 
-	if (bus >= ARRAY_SIZE(pins) || pins[bus] == NULL) {
-		debug("%s: invalid bus %u\n", __func__, bus);
-		return NULL;
-	}
 	switch (bus) {
 #ifdef SPI0_REGBASE
 	case 0:
@@ -175,6 +172,7 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
 		break;
 #endif
 	default:
+		debug("%s: invalid bus %u\n", __func__, bus);
 		return NULL;
 	}
 
diff --git a/drivers/spi/exynos_spi.c b/drivers/spi/exynos_spi.c
index 699c57eb6d..4d5def2d31 100644
--- a/drivers/spi/exynos_spi.c
+++ b/drivers/spi/exynos_spi.c
@@ -529,18 +529,18 @@ static int process_nodes(const void *blob, int node_list[], int count)
  * @param node		SPI peripheral node to use
  * @return 0 if ok, -1 on error
  */
-struct spi_slave *spi_setup_slave_fdt(const void *blob, int node,
-		unsigned int cs, unsigned int max_hz, unsigned int mode)
+struct spi_slave *spi_setup_slave_fdt(const void *blob, int slave_node,
+				      int spi_node)
 {
 	struct spi_bus *bus;
 	unsigned int i;
 
 	for (i = 0, bus = spi_bus; i < bus_count; i++, bus++) {
-		if (bus->node == node)
-			return spi_setup_slave(i, cs, max_hz, mode);
+		if (bus->node == spi_node)
+			return spi_base_setup_slave_fdt(blob, i, slave_node);
 	}
 
-	debug("%s: Failed to find bus node %d\n", __func__, node);
+	debug("%s: Failed to find bus node %d\n", __func__, spi_node);
 	return NULL;
 }
 
diff --git a/drivers/spi/ftssp010_spi.c b/drivers/spi/ftssp010_spi.c
new file mode 100644
index 0000000000..aa3b5a01cd
--- /dev/null
+++ b/drivers/spi/ftssp010_spi.c
@@ -0,0 +1,508 @@
+/*
+ * (C) Copyright 2013
+ * Faraday Technology Corporation. <http://www.faraday-tech.com/tw/>
+ * Kuo-Jung Su <dantesu@gmail.com>
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#include <common.h>
+#include <linux/compat.h>
+#include <asm/io.h>
+#include <malloc.h>
+#include <spi.h>
+
+#ifndef CONFIG_FTSSP010_BASE_LIST
+#define CONFIG_FTSSP010_BASE_LIST   { CONFIG_FTSSP010_BASE }
+#endif
+
+#ifndef CONFIG_FTSSP010_GPIO_BASE
+#define CONFIG_FTSSP010_GPIO_BASE   0
+#endif
+
+#ifndef CONFIG_FTSSP010_GPIO_LIST
+#define CONFIG_FTSSP010_GPIO_LIST   { CONFIG_FTSSP010_GPIO_BASE }
+#endif
+
+#ifndef CONFIG_FTSSP010_CLOCK
+#define CONFIG_FTSSP010_CLOCK       clk_get_rate("SSP");
+#endif
+
+#ifndef CONFIG_FTSSP010_TIMEOUT
+#define CONFIG_FTSSP010_TIMEOUT     100
+#endif
+
+/* FTSSP010 chip registers */
+struct ftssp010_regs {
+	uint32_t cr[3];/* control register */
+	uint32_t sr;   /* status register */
+	uint32_t icr;  /* interrupt control register */
+	uint32_t isr;  /* interrupt status register */
+	uint32_t dr;   /* data register */
+	uint32_t rsvd[17];
+	uint32_t revr; /* revision register */
+	uint32_t fear; /* feature register */
+};
+
+/* Control Register 0  */
+#define CR0_FFMT_MASK       (7 << 12)
+#define CR0_FFMT_SSP        (0 << 12)
+#define CR0_FFMT_SPI        (1 << 12)
+#define CR0_FFMT_MICROWIRE  (2 << 12)
+#define CR0_FFMT_I2S        (3 << 12)
+#define CR0_FFMT_AC97       (4 << 12)
+#define CR0_FLASH           (1 << 11)
+#define CR0_FSDIST(x)       (((x) & 0x03) << 8)
+#define CR0_LOOP            (1 << 7)  /* loopback mode */
+#define CR0_LSB             (1 << 6)  /* LSB */
+#define CR0_FSPO            (1 << 5)  /* fs atcive low (I2S only) */
+#define CR0_FSJUSTIFY       (1 << 4)
+#define CR0_OPM_SLAVE       (0 << 2)
+#define CR0_OPM_MASTER      (3 << 2)
+#define CR0_OPM_I2S_MSST    (3 << 2)  /* master stereo mode */
+#define CR0_OPM_I2S_MSMO    (2 << 2)  /* master mono mode */
+#define CR0_OPM_I2S_SLST    (1 << 2)  /* slave stereo mode */
+#define CR0_OPM_I2S_SLMO    (0 << 2)  /* slave mono mode */
+#define CR0_SCLKPO          (1 << 1)  /* clock polarity */
+#define CR0_SCLKPH          (1 << 0)  /* clock phase */
+
+/* Control Register 1 */
+#define CR1_PDL(x)   (((x) & 0xff) << 24) /* padding length */
+#define CR1_SDL(x)   ((((x) - 1) & 0x1f) << 16) /* data length */
+#define CR1_DIV(x)   (((x) - 1) & 0xffff) /* clock divider */
+
+/* Control Register 2 */
+#define CR2_CS(x)    (((x) & 3) << 10) /* CS/FS select */
+#define CR2_FS       (1 << 9) /* CS/FS signal level */
+#define CR2_TXEN     (1 << 8) /* tx enable */
+#define CR2_RXEN     (1 << 7) /* rx enable */
+#define CR2_RESET    (1 << 6) /* chip reset */
+#define CR2_TXFC     (1 << 3) /* tx fifo Clear */
+#define CR2_RXFC     (1 << 2) /* rx fifo Clear */
+#define CR2_TXDOE    (1 << 1) /* tx data output enable */
+#define CR2_EN       (1 << 0) /* chip enable */
+
+/* Status Register */
+#define SR_RFF       (1 << 0) /* rx fifo full */
+#define SR_TFNF      (1 << 1) /* tx fifo not full */
+#define SR_BUSY      (1 << 2) /* chip busy */
+#define SR_RFVE(reg) (((reg) >> 4) & 0x1f)  /* rx fifo valid entries */
+#define SR_TFVE(reg) (((reg) >> 12) & 0x1f) /* tx fifo valid entries */
+
+/* Feature Register */
+#define FEAR_BITS(reg)   ((((reg) >>  0) & 0xff) + 1) /* data width */
+#define FEAR_RFSZ(reg)   ((((reg) >>  8) & 0xff) + 1) /* rx fifo size */
+#define FEAR_TFSZ(reg)   ((((reg) >> 16) & 0xff) + 1) /* tx fifo size */
+#define FEAR_AC97        (1 << 24)
+#define FEAR_I2S         (1 << 25)
+#define FEAR_SPI_MWR     (1 << 26)
+#define FEAR_SSP         (1 << 27)
+#define FEAR_SPDIF       (1 << 28)
+
+/* FTGPIO010 chip registers */
+struct ftgpio010_regs {
+	uint32_t out;     /* 0x00: Data Output */
+	uint32_t in;      /* 0x04: Data Input */
+	uint32_t dir;     /* 0x08: Direction */
+	uint32_t bypass;  /* 0x0c: Bypass */
+	uint32_t set;     /* 0x10: Data Set */
+	uint32_t clr;     /* 0x14: Data Clear */
+	uint32_t pull_up; /* 0x18: Pull-Up Enabled */
+	uint32_t pull_st; /* 0x1c: Pull State (0=pull-down, 1=pull-up) */
+};
+
+struct ftssp010_gpio {
+	struct ftgpio010_regs *regs;
+	uint32_t pin;
+};
+
+struct ftssp010_spi {
+	struct spi_slave slave;
+	struct ftssp010_gpio gpio;
+	struct ftssp010_regs *regs;
+	uint32_t fifo;
+	uint32_t mode;
+	uint32_t div;
+	uint32_t clk;
+	uint32_t speed;
+	uint32_t revision;
+};
+
+static inline struct ftssp010_spi *to_ftssp010_spi(struct spi_slave *slave)
+{
+	return container_of(slave, struct ftssp010_spi, slave);
+}
+
+static int get_spi_chip(int bus, struct ftssp010_spi *chip)
+{
+	uint32_t fear, base[] = CONFIG_FTSSP010_BASE_LIST;
+
+	if (bus >= ARRAY_SIZE(base) || !base[bus])
+		return -1;
+
+	chip->regs = (struct ftssp010_regs *)base[bus];
+
+	chip->revision = readl(&chip->regs->revr);
+
+	fear = readl(&chip->regs->fear);
+	chip->fifo = min_t(uint32_t, FEAR_TFSZ(fear), FEAR_RFSZ(fear));
+
+	return 0;
+}
+
+static int get_spi_gpio(int bus, struct ftssp010_gpio *chip)
+{
+	uint32_t base[] = CONFIG_FTSSP010_GPIO_LIST;
+
+	if (bus >= ARRAY_SIZE(base) || !base[bus])
+		return -1;
+
+	chip->regs = (struct ftgpio010_regs *)(base[bus] & 0xfff00000);
+	chip->pin = base[bus] & 0x1f;
+
+	/* make it an output pin */
+	setbits_le32(&chip->regs->dir, 1 << chip->pin);
+
+	return 0;
+}
+
+static int ftssp010_wait(struct ftssp010_spi *chip)
+{
+	struct ftssp010_regs *regs = chip->regs;
+	int ret = -1;
+	ulong t;
+
+	/* wait until device idle */
+	for (t = get_timer(0); get_timer(t) < CONFIG_FTSSP010_TIMEOUT; ) {
+		if (readl(&regs->sr) & SR_BUSY)
+			continue;
+		ret = 0;
+		break;
+	}
+
+	if (ret)
+		puts("ftspi010: busy timeout\n");
+
+	return ret;
+}
+
+static int ftssp010_wait_tx(struct ftssp010_spi *chip)
+{
+	struct ftssp010_regs *regs = chip->regs;
+	int ret = -1;
+	ulong t;
+
+	/* wait until tx fifo not full */
+	for (t = get_timer(0); get_timer(t) < CONFIG_FTSSP010_TIMEOUT; ) {
+		if (!(readl(&regs->sr) & SR_TFNF))
+			continue;
+		ret = 0;
+		break;
+	}
+
+	if (ret)
+		puts("ftssp010: tx timeout\n");
+
+	return ret;
+}
+
+static int ftssp010_wait_rx(struct ftssp010_spi *chip)
+{
+	struct ftssp010_regs *regs = chip->regs;
+	int ret = -1;
+	ulong t;
+
+	/* wait until rx fifo not empty */
+	for (t = get_timer(0); get_timer(t) < CONFIG_FTSSP010_TIMEOUT; ) {
+		if (!SR_RFVE(readl(&regs->sr)))
+			continue;
+		ret = 0;
+		break;
+	}
+
+	if (ret)
+		puts("ftssp010: rx timeout\n");
+
+	return ret;
+}
+
+static int ftssp010_spi_work_transfer_v2(struct ftssp010_spi *chip,
+	const void *tx_buf, void *rx_buf, int len, uint flags)
+{
+	struct ftssp010_regs *regs = chip->regs;
+	const uint8_t *txb = tx_buf;
+	uint8_t       *rxb = rx_buf;
+
+	while (len > 0) {
+		int i, depth = min(chip->fifo >> 2, len);
+		uint32_t xmsk = 0;
+
+		if (tx_buf) {
+			for (i = 0; i < depth; ++i) {
+				ftssp010_wait_tx(chip);
+				writel(*txb++, &regs->dr);
+			}
+			xmsk |= CR2_TXEN | CR2_TXDOE;
+			if ((readl(&regs->cr[2]) & xmsk) != xmsk)
+				setbits_le32(&regs->cr[2], xmsk);
+		}
+		if (rx_buf) {
+			xmsk |= CR2_RXEN;
+			if ((readl(&regs->cr[2]) & xmsk) != xmsk)
+				setbits_le32(&regs->cr[2], xmsk);
+			for (i = 0; i < depth; ++i) {
+				ftssp010_wait_rx(chip);
+				*rxb++ = (uint8_t)readl(&regs->dr);
+			}
+		}
+
+		len -= depth;
+	}
+
+	return 0;
+}
+
+static int ftssp010_spi_work_transfer_v1(struct ftssp010_spi *chip,
+	const void *tx_buf, void *rx_buf, int len, uint flags)
+{
+	struct ftssp010_regs *regs = chip->regs;
+	const uint8_t *txb = tx_buf;
+	uint8_t       *rxb = rx_buf;
+
+	while (len > 0) {
+		int i, depth = min(chip->fifo >> 2, len);
+		uint32_t tmp;
+
+		for (i = 0; i < depth; ++i) {
+			ftssp010_wait_tx(chip);
+			writel(txb ? (*txb++) : 0, &regs->dr);
+		}
+		for (i = 0; i < depth; ++i) {
+			ftssp010_wait_rx(chip);
+			tmp = readl(&regs->dr);
+			if (rxb)
+				*rxb++ = (uint8_t)tmp;
+		}
+
+		len -= depth;
+	}
+
+	return 0;
+}
+
+static void ftssp010_cs_set(struct ftssp010_spi *chip, int high)
+{
+	struct ftssp010_regs *regs = chip->regs;
+	struct ftssp010_gpio *gpio = &chip->gpio;
+	uint32_t mask;
+
+	/* cs pull high/low */
+	if (chip->revision >= 0x11900) {
+		mask = CR2_CS(chip->slave.cs) | (high ? CR2_FS : 0);
+		writel(mask, &regs->cr[2]);
+	} else if (gpio->regs) {
+		mask = 1 << gpio->pin;
+		if (high)
+			writel(mask, &gpio->regs->set);
+		else
+			writel(mask, &gpio->regs->clr);
+	}
+
+	/* extra delay for signal propagation */
+	udelay_masked(1);
+}
+
+/*
+ * Determine if a SPI chipselect is valid.
+ * This function is provided by the board if the low-level SPI driver
+ * needs it to determine if a given chipselect is actually valid.
+ *
+ * Returns: 1 if bus:cs identifies a valid chip on this board, 0
+ * otherwise.
+ */
+int spi_cs_is_valid(unsigned int bus, unsigned int cs)
+{
+	struct ftssp010_spi chip;
+
+	if (get_spi_chip(bus, &chip))
+		return 0;
+
+	if (!cs)
+		return 1;
+	else if ((cs < 4) && (chip.revision >= 0x11900))
+		return 1;
+
+	return 0;
+}
+
+/*
+ * Activate a SPI chipselect.
+ * This function is provided by the board code when using a driver
+ * that can't control its chipselects automatically (e.g.
+ * common/soft_spi.c). When called, it should activate the chip select
+ * to the device identified by "slave".
+ */
+void spi_cs_activate(struct spi_slave *slave)
+{
+	struct ftssp010_spi *chip = to_ftssp010_spi(slave);
+	struct ftssp010_regs *regs = chip->regs;
+
+	/* cs pull */
+	if (chip->mode & SPI_CS_HIGH)
+		ftssp010_cs_set(chip, 1);
+	else
+		ftssp010_cs_set(chip, 0);
+
+	/* chip enable + fifo clear */
+	setbits_le32(&regs->cr[2], CR2_EN | CR2_TXFC | CR2_RXFC);
+}
+
+/*
+ * Deactivate a SPI chipselect.
+ * This function is provided by the board code when using a driver
+ * that can't control its chipselects automatically (e.g.
+ * common/soft_spi.c). When called, it should deactivate the chip
+ * select to the device identified by "slave".
+ */
+void spi_cs_deactivate(struct spi_slave *slave)
+{
+	struct ftssp010_spi *chip = to_ftssp010_spi(slave);
+
+	/* wait until chip idle */
+	ftssp010_wait(chip);
+
+	/* cs pull */
+	if (chip->mode & SPI_CS_HIGH)
+		ftssp010_cs_set(chip, 0);
+	else
+		ftssp010_cs_set(chip, 1);
+}
+
+void spi_init(void)
+{
+	/* nothing to do */
+}
+
+struct spi_slave *spi_setup_slave(uint bus, uint cs, uint max_hz, uint mode)
+{
+	struct ftssp010_spi *chip;
+
+	if (mode & SPI_3WIRE) {
+		puts("ftssp010: can't do 3-wire\n");
+		return NULL;
+	}
+
+	if (mode & SPI_SLAVE) {
+		puts("ftssp010: can't do slave mode\n");
+		return NULL;
+	}
+
+	if (mode & SPI_PREAMBLE) {
+		puts("ftssp010: can't skip preamble bytes\n");
+		return NULL;
+	}
+
+	if (!spi_cs_is_valid(bus, cs)) {
+		puts("ftssp010: invalid (bus, cs)\n");
+		return NULL;
+	}
+
+	chip = spi_alloc_slave(struct ftssp010_spi, bus, cs);
+	if (!chip)
+		return NULL;
+
+	if (get_spi_chip(bus, chip))
+		goto free_out;
+
+	if (chip->revision < 0x11900 && get_spi_gpio(bus, &chip->gpio)) {
+		puts("ftssp010: Before revision 1.19.0, its clock & cs are\n"
+		"controlled by tx engine which is not synced with rx engine,\n"
+		"so the clock & cs might be shutdown before rx engine\n"
+		"finishs its jobs.\n"
+		"If possible, please add a dedicated gpio for it.\n");
+	}
+
+	chip->mode = mode;
+	chip->clk = CONFIG_FTSSP010_CLOCK;
+	chip->div = 2;
+	if (max_hz) {
+		while (chip->div < 0xffff) {
+			if ((chip->clk / (2 * chip->div)) <= max_hz)
+				break;
+			chip->div += 1;
+		}
+	}
+	chip->speed = chip->clk / (2 * chip->div);
+
+	return &chip->slave;
+
+free_out:
+	free(chip);
+	return NULL;
+}
+
+void spi_free_slave(struct spi_slave *slave)
+{
+	free(slave);
+}
+
+int spi_claim_bus(struct spi_slave *slave)
+{
+	struct ftssp010_spi *chip = to_ftssp010_spi(slave);
+	struct ftssp010_regs *regs = chip->regs;
+
+	writel(CR1_SDL(8) | CR1_DIV(chip->div), &regs->cr[1]);
+
+	if (chip->revision >= 0x11900) {
+		writel(CR0_OPM_MASTER | CR0_FFMT_SPI | CR0_FSPO | CR0_FLASH,
+		       &regs->cr[0]);
+		writel(CR2_TXFC | CR2_RXFC,
+		       &regs->cr[2]);
+	} else {
+		writel(CR0_OPM_MASTER | CR0_FFMT_SPI | CR0_FSPO,
+		       &regs->cr[0]);
+		writel(CR2_TXFC | CR2_RXFC | CR2_EN | CR2_TXDOE,
+		       &regs->cr[2]);
+	}
+
+	if (chip->mode & SPI_LOOP)
+		setbits_le32(&regs->cr[0], CR0_LOOP);
+
+	if (chip->mode & SPI_CPOL)
+		setbits_le32(&regs->cr[0], CR0_SCLKPO);
+
+	if (chip->mode & SPI_CPHA)
+		setbits_le32(&regs->cr[0], CR0_SCLKPH);
+
+	spi_cs_deactivate(slave);
+
+	return 0;
+}
+
+void spi_release_bus(struct spi_slave *slave)
+{
+	struct ftssp010_spi *chip = to_ftssp010_spi(slave);
+	struct ftssp010_regs *regs = chip->regs;
+
+	writel(0, &regs->cr[2]);
+}
+
+int spi_xfer(struct spi_slave *slave, unsigned int bitlen,
+			 const void *dout, void *din, unsigned long flags)
+{
+	struct ftssp010_spi *chip = to_ftssp010_spi(slave);
+	uint32_t len = bitlen >> 3;
+
+	if (flags & SPI_XFER_BEGIN)
+		spi_cs_activate(slave);
+
+	if (chip->revision >= 0x11900)
+		ftssp010_spi_work_transfer_v2(chip, dout, din, len, flags);
+	else
+		ftssp010_spi_work_transfer_v1(chip, dout, din, len, flags);
+
+	if (flags & SPI_XFER_END)
+		spi_cs_deactivate(slave);
+
+	return 0;
+}
diff --git a/drivers/spi/mxc_spi.c b/drivers/spi/mxc_spi.c
index 95dd03f7b3..f3f029d634 100644
--- a/drivers/spi/mxc_spi.c
+++ b/drivers/spi/mxc_spi.c
@@ -115,7 +115,8 @@ static s32 spi_cfg_mxc(struct mxc_spi_slave *mxcs, unsigned int cs,
 {
 	u32 clk_src = mxc_get_clock(MXC_CSPI_CLK);
 	s32 reg_ctrl, reg_config;
-	u32 ss_pol = 0, sclkpol = 0, sclkpha = 0, pre_div = 0, post_div = 0;
+	u32 ss_pol = 0, sclkpol = 0, sclkpha = 0, sclkctl = 0;
+	u32 pre_div = 0, post_div = 0;
 	struct cspi_regs *regs = (struct cspi_regs *)mxcs->base;
 
 	if (max_hz == 0) {
@@ -164,8 +165,10 @@ static s32 spi_cfg_mxc(struct mxc_spi_slave *mxcs, unsigned int cs,
 	if (mode & SPI_CS_HIGH)
 		ss_pol = 1;
 
-	if (mode & SPI_CPOL)
+	if (mode & SPI_CPOL) {
 		sclkpol = 1;
+		sclkctl = 1;
+	}
 
 	if (mode & SPI_CPHA)
 		sclkpha = 1;
@@ -180,6 +183,8 @@ static s32 spi_cfg_mxc(struct mxc_spi_slave *mxcs, unsigned int cs,
 		(ss_pol << (cs + MXC_CSPICON_SSPOL));
 	reg_config = (reg_config & ~(1 << (cs + MXC_CSPICON_POL))) |
 		(sclkpol << (cs + MXC_CSPICON_POL));
+	reg_config = (reg_config & ~(1 << (cs + MXC_CSPICON_CTL))) |
+		(sclkctl << (cs + MXC_CSPICON_CTL));
 	reg_config = (reg_config & ~(1 << (cs + MXC_CSPICON_PHA))) |
 		(sclkpha << (cs + MXC_CSPICON_PHA));
 
diff --git a/drivers/spi/omap3_spi.c b/drivers/spi/omap3_spi.c
index e80be8eaac..651e46e4bd 100644
--- a/drivers/spi/omap3_spi.c
+++ b/drivers/spi/omap3_spi.c
@@ -20,8 +20,7 @@
 #include <asm/io.h>
 #include "omap3_spi.h"
 
-#define WORD_LEN	8
-#define SPI_WAIT_TIMEOUT 3000000;
+#define SPI_WAIT_TIMEOUT 3000000
 
 static void spi_reset(struct omap3_spi_slave *ds)
 {
@@ -185,7 +184,7 @@ int spi_claim_bus(struct spi_slave *slave)
 
 	/* wordlength */
 	conf &= ~OMAP3_MCSPI_CHCONF_WL_MASK;
-	conf |= (WORD_LEN - 1) << 7;
+	conf |= (ds->slave.wordlen - 1) << 7;
 
 	/* set chipselect polarity; manage with FORCE */
 	if (!(ds->mode & SPI_CS_HIGH))
@@ -223,7 +222,7 @@ void spi_release_bus(struct spi_slave *slave)
 	spi_reset(ds);
 }
 
-int omap3_spi_write(struct spi_slave *slave, unsigned int len, const u8 *txp,
+int omap3_spi_write(struct spi_slave *slave, unsigned int len, const void *txp,
 		    unsigned long flags)
 {
 	struct omap3_spi_slave *ds = to_omap3_spi(slave);
@@ -234,7 +233,8 @@ int omap3_spi_write(struct spi_slave *slave, unsigned int len, const u8 *txp,
 	/* Enable the channel */
 	omap3_spi_set_enable(ds,OMAP3_MCSPI_CHCTRL_EN);
 
-	chconf &= ~OMAP3_MCSPI_CHCONF_TRM_MASK;
+	chconf &= ~(OMAP3_MCSPI_CHCONF_TRM_MASK | OMAP3_MCSPI_CHCONF_WL_MASK);
+	chconf |= (ds->slave.wordlen - 1) << 7;
 	chconf |= OMAP3_MCSPI_CHCONF_TRM_TX_ONLY;
 	chconf |= OMAP3_MCSPI_CHCONF_FORCE;
 	omap3_spi_write_chconf(ds,chconf);
@@ -250,12 +250,19 @@ int omap3_spi_write(struct spi_slave *slave, unsigned int len, const u8 *txp,
 			}
 		}
 		/* Write the data */
-		writel(txp[i], &ds->regs->channel[ds->slave.cs].tx);
+		unsigned int *tx = &ds->regs->channel[ds->slave.cs].tx;
+		if (ds->slave.wordlen > 16)
+			writel(((u32 *)txp)[i], tx);
+		else if (ds->slave.wordlen > 8)
+			writel(((u16 *)txp)[i], tx);
+		else
+			writel(((u8 *)txp)[i], tx);
 	}
 
 	/* wait to finish of transfer */
-	while (!(readl(&ds->regs->channel[ds->slave.cs].chstat) &
-			 OMAP3_MCSPI_CHSTAT_EOT));
+	while ((readl(&ds->regs->channel[ds->slave.cs].chstat) &
+			 (OMAP3_MCSPI_CHSTAT_EOT | OMAP3_MCSPI_CHSTAT_TXS)) !=
+			 (OMAP3_MCSPI_CHSTAT_EOT | OMAP3_MCSPI_CHSTAT_TXS));
 
 	/* Disable the channel otherwise the next immediate RX will get affected */
 	omap3_spi_set_enable(ds,OMAP3_MCSPI_CHCTRL_DIS);
@@ -268,7 +275,7 @@ int omap3_spi_write(struct spi_slave *slave, unsigned int len, const u8 *txp,
 	return 0;
 }
 
-int omap3_spi_read(struct spi_slave *slave, unsigned int len, u8 *rxp,
+int omap3_spi_read(struct spi_slave *slave, unsigned int len, void *rxp,
 		   unsigned long flags)
 {
 	struct omap3_spi_slave *ds = to_omap3_spi(slave);
@@ -279,7 +286,8 @@ int omap3_spi_read(struct spi_slave *slave, unsigned int len, u8 *rxp,
 	/* Enable the channel */
 	omap3_spi_set_enable(ds,OMAP3_MCSPI_CHCTRL_EN);
 
-	chconf &= ~OMAP3_MCSPI_CHCONF_TRM_MASK;
+	chconf &= ~(OMAP3_MCSPI_CHCONF_TRM_MASK | OMAP3_MCSPI_CHCONF_WL_MASK);
+	chconf |= (ds->slave.wordlen - 1) << 7;
 	chconf |= OMAP3_MCSPI_CHCONF_TRM_RX_ONLY;
 	chconf |= OMAP3_MCSPI_CHCONF_FORCE;
 	omap3_spi_write_chconf(ds,chconf);
@@ -302,7 +310,13 @@ int omap3_spi_read(struct spi_slave *slave, unsigned int len, u8 *rxp,
 			omap3_spi_set_enable(ds,OMAP3_MCSPI_CHCTRL_DIS);
 
 		/* Read the data */
-		rxp[i] = readl(&ds->regs->channel[ds->slave.cs].rx);
+		unsigned int *rx = &ds->regs->channel[ds->slave.cs].rx;
+		if (ds->slave.wordlen > 16)
+			((u32 *)rxp)[i] = readl(rx);
+		else if (ds->slave.wordlen > 8)
+			((u16 *)rxp)[i] = (u16)readl(rx);
+		else
+			((u8 *)rxp)[i] = (u8)readl(rx);
 	}
 
 	if (flags & SPI_XFER_END) {
@@ -314,8 +328,8 @@ int omap3_spi_read(struct spi_slave *slave, unsigned int len, u8 *rxp,
 }
 
 /*McSPI Transmit Receive Mode*/
-int omap3_spi_txrx(struct spi_slave *slave,
-		unsigned int len, const u8 *txp, u8 *rxp, unsigned long flags)
+int omap3_spi_txrx(struct spi_slave *slave, unsigned int len,
+		   const void *txp, void *rxp, unsigned long flags)
 {
 	struct omap3_spi_slave *ds = to_omap3_spi(slave);
 	int timeout = SPI_WAIT_TIMEOUT;
@@ -327,7 +341,8 @@ int omap3_spi_txrx(struct spi_slave *slave,
 	omap3_spi_set_enable(ds,OMAP3_MCSPI_CHCTRL_EN);
 
 	/*set TRANSMIT-RECEIVE Mode*/
-	chconf &= ~OMAP3_MCSPI_CHCONF_TRM_MASK;
+	chconf &= ~(OMAP3_MCSPI_CHCONF_TRM_MASK | OMAP3_MCSPI_CHCONF_WL_MASK);
+	chconf |= (ds->slave.wordlen - 1) << 7;
 	chconf |= OMAP3_MCSPI_CHCONF_FORCE;
 	omap3_spi_write_chconf(ds,chconf);
 
@@ -344,7 +359,13 @@ int omap3_spi_txrx(struct spi_slave *slave,
 			}
 		}
 		/* Write the data */
-		writel(txp[i], &ds->regs->channel[ds->slave.cs].tx);
+		unsigned int *tx = &ds->regs->channel[ds->slave.cs].tx;
+		if (ds->slave.wordlen > 16)
+			writel(((u32 *)txp)[i], tx);
+		else if (ds->slave.wordlen > 8)
+			writel(((u16 *)txp)[i], tx);
+		else
+			writel(((u8 *)txp)[i], tx);
 
 		/*Read: wait for RX containing data (RXS == 1)*/
 		while (!(readl(&ds->regs->channel[ds->slave.cs].chstat) &
@@ -356,7 +377,13 @@ int omap3_spi_txrx(struct spi_slave *slave,
 			}
 		}
 		/* Read the data */
-		rxp[i] = readl(&ds->regs->channel[ds->slave.cs].rx);
+		unsigned int *rx = &ds->regs->channel[ds->slave.cs].rx;
+		if (ds->slave.wordlen > 16)
+			((u32 *)rxp)[i] = readl(rx);
+		else if (ds->slave.wordlen > 8)
+			((u16 *)rxp)[i] = (u16)readl(rx);
+		else
+			((u8 *)rxp)[i] = (u8)readl(rx);
 	}
 	/* Disable the channel */
 	omap3_spi_set_enable(ds,OMAP3_MCSPI_CHCTRL_DIS);
@@ -375,14 +402,17 @@ int spi_xfer(struct spi_slave *slave, unsigned int bitlen,
 {
 	struct omap3_spi_slave *ds = to_omap3_spi(slave);
 	unsigned int	len;
-	const u8	*txp = dout;
-	u8		*rxp = din;
 	int ret = -1;
 
-	if (bitlen % 8)
+	if (ds->slave.wordlen < 4 || ds->slave.wordlen > 32) {
+		printf("omap3_spi: invalid wordlen %d\n", ds->slave.wordlen);
+		return -1;
+	}
+
+	if (bitlen % ds->slave.wordlen)
 		return -1;
 
-	len = bitlen / 8;
+	len = bitlen / ds->slave.wordlen;
 
 	if (bitlen == 0) {	 /* only change CS */
 		int chconf = readl(&ds->regs->channel[ds->slave.cs].chconf);
@@ -400,11 +430,11 @@ int spi_xfer(struct spi_slave *slave, unsigned int bitlen,
 		ret = 0;
 	} else {
 		if (dout != NULL && din != NULL)
-			ret = omap3_spi_txrx(slave, len, txp, rxp, flags);
+			ret = omap3_spi_txrx(slave, len, dout, din, flags);
 		else if (dout != NULL)
-			ret = omap3_spi_write(slave, len, txp, flags);
+			ret = omap3_spi_write(slave, len, dout, flags);
 		else if (din != NULL)
-			ret = omap3_spi_read(slave, len, rxp, flags);
+			ret = omap3_spi_read(slave, len, din, flags);
 	}
 	return ret;
 }
diff --git a/drivers/spi/omap3_spi.h b/drivers/spi/omap3_spi.h
index 01537b6246..ab7cd84448 100644
--- a/drivers/spi/omap3_spi.h
+++ b/drivers/spi/omap3_spi.h
@@ -99,11 +99,11 @@ static inline struct omap3_spi_slave *to_omap3_spi(struct spi_slave *slave)
 	return container_of(slave, struct omap3_spi_slave, slave);
 }
 
-int omap3_spi_txrx(struct spi_slave *slave, unsigned int len, const u8 *txp,
-			u8 *rxp, unsigned long flags);
-int omap3_spi_write(struct spi_slave *slave, unsigned int len, const u8 *txp,
+int omap3_spi_txrx(struct spi_slave *slave, unsigned int len, const void *txp,
+			void *rxp, unsigned long flags);
+int omap3_spi_write(struct spi_slave *slave, unsigned int len, const void *txp,
 		    unsigned long flags);
-int omap3_spi_read(struct spi_slave *slave, unsigned int len, u8 *rxp,
+int omap3_spi_read(struct spi_slave *slave, unsigned int len, void *rxp,
 		   unsigned long flags);
 
 #endif /* _OMAP3_SPI_H_ */
diff --git a/drivers/spi/sandbox_spi.c b/drivers/spi/sandbox_spi.c
new file mode 100644
index 0000000000..12e9bdad38
--- /dev/null
+++ b/drivers/spi/sandbox_spi.c
@@ -0,0 +1,217 @@
+/*
+ * Simulate a SPI port
+ *
+ * Copyright (c) 2011-2013 The Chromium OS Authors.
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+#include <common.h>
+#include <malloc.h>
+#include <spi.h>
+#include <os.h>
+
+#include <asm/errno.h>
+#include <asm/spi.h>
+#include <asm/state.h>
+
+#ifndef CONFIG_SPI_IDLE_VAL
+# define CONFIG_SPI_IDLE_VAL 0xFF
+#endif
+
+struct sandbox_spi_slave {
+	struct spi_slave slave;
+	const struct sandbox_spi_emu_ops *ops;
+	void *priv;
+};
+
+#define to_sandbox_spi_slave(s) container_of(s, struct sandbox_spi_slave, slave)
+
+const char *sandbox_spi_parse_spec(const char *arg, unsigned long *bus,
+				   unsigned long *cs)
+{
+	char *endp;
+
+	*bus = simple_strtoul(arg, &endp, 0);
+	if (*endp != ':' || *bus >= CONFIG_SANDBOX_SPI_MAX_BUS)
+		return NULL;
+
+	*cs = simple_strtoul(endp + 1, &endp, 0);
+	if (*endp != ':' || *cs >= CONFIG_SANDBOX_SPI_MAX_CS)
+		return NULL;
+
+	return endp + 1;
+}
+
+int spi_cs_is_valid(unsigned int bus, unsigned int cs)
+{
+	return bus < CONFIG_SANDBOX_SPI_MAX_BUS &&
+		cs < CONFIG_SANDBOX_SPI_MAX_CS;
+}
+
+void spi_cs_activate(struct spi_slave *slave)
+{
+	struct sandbox_spi_slave *sss = to_sandbox_spi_slave(slave);
+
+	debug("sandbox_spi: activating CS\n");
+	if (sss->ops->cs_activate)
+		sss->ops->cs_activate(sss->priv);
+}
+
+void spi_cs_deactivate(struct spi_slave *slave)
+{
+	struct sandbox_spi_slave *sss = to_sandbox_spi_slave(slave);
+
+	debug("sandbox_spi: deactivating CS\n");
+	if (sss->ops->cs_deactivate)
+		sss->ops->cs_deactivate(sss->priv);
+}
+
+void spi_init(void)
+{
+}
+
+void spi_set_speed(struct spi_slave *slave, uint hz)
+{
+}
+
+struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
+		unsigned int max_hz, unsigned int mode)
+{
+	struct sandbox_spi_slave *sss;
+	struct sandbox_state *state = state_get_current();
+	const char *spec;
+
+	if (!spi_cs_is_valid(bus, cs)) {
+		debug("sandbox_spi: Invalid SPI bus/cs\n");
+		return NULL;
+	}
+
+	sss = spi_alloc_slave(struct sandbox_spi_slave, bus, cs);
+	if (!sss) {
+		debug("sandbox_spi: Out of memory\n");
+		return NULL;
+	}
+
+	spec = state->spi[bus][cs].spec;
+	sss->ops = state->spi[bus][cs].ops;
+	if (!spec || !sss->ops || sss->ops->setup(&sss->priv, spec)) {
+		free(sss);
+		printf("sandbox_spi: unable to locate a slave client\n");
+		return NULL;
+	}
+
+	return &sss->slave;
+}
+
+void spi_free_slave(struct spi_slave *slave)
+{
+	struct sandbox_spi_slave *sss = to_sandbox_spi_slave(slave);
+
+	debug("sandbox_spi: releasing slave\n");
+
+	if (sss->ops->free)
+		sss->ops->free(sss->priv);
+
+	free(sss);
+}
+
+static int spi_bus_claim_cnt[CONFIG_SANDBOX_SPI_MAX_BUS];
+
+int spi_claim_bus(struct spi_slave *slave)
+{
+	if (spi_bus_claim_cnt[slave->bus]++) {
+		printf("sandbox_spi: error: bus already claimed: %d!\n",
+		       spi_bus_claim_cnt[slave->bus]);
+	}
+
+	return 0;
+}
+
+void spi_release_bus(struct spi_slave *slave)
+{
+	if (--spi_bus_claim_cnt[slave->bus]) {
+		printf("sandbox_spi: error: bus freed too often: %d!\n",
+		       spi_bus_claim_cnt[slave->bus]);
+	}
+}
+
+int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
+		void *din, unsigned long flags)
+{
+	struct sandbox_spi_slave *sss = to_sandbox_spi_slave(slave);
+	uint bytes = bitlen / 8, i;
+	int ret = 0;
+	u8 *tx = (void *)dout, *rx = din;
+
+	if (bitlen == 0)
+		goto done;
+
+	/* we can only do 8 bit transfers */
+	if (bitlen % 8) {
+		printf("sandbox_spi: xfer: invalid bitlen size %u; needs to be 8bit\n",
+		       bitlen);
+		flags |= SPI_XFER_END;
+		goto done;
+	}
+
+	if (flags & SPI_XFER_BEGIN)
+		spi_cs_activate(slave);
+
+	/* make sure rx/tx buffers are full so clients can assume */
+	if (!tx) {
+		debug("sandbox_spi: xfer: auto-allocating tx scratch buffer\n");
+		tx = malloc(bytes);
+		if (!tx) {
+			debug("sandbox_spi: Out of memory\n");
+			return -ENOMEM;
+		}
+	}
+	if (!rx) {
+		debug("sandbox_spi: xfer: auto-allocating rx scratch buffer\n");
+		rx = malloc(bytes);
+		if (!rx) {
+			debug("sandbox_spi: Out of memory\n");
+			return -ENOMEM;
+		}
+	}
+
+	debug("sandbox_spi: xfer: bytes = %u\n tx:", bytes);
+	for (i = 0; i < bytes; ++i)
+		debug(" %u:%02x", i, tx[i]);
+	debug("\n");
+
+	ret = sss->ops->xfer(sss->priv, tx, rx, bytes);
+
+	debug("sandbox_spi: xfer: got back %i (that's %s)\n rx:",
+	      ret, ret ? "bad" : "good");
+	for (i = 0; i < bytes; ++i)
+		debug(" %u:%02x", i, rx[i]);
+	debug("\n");
+
+	if (tx != dout)
+		free(tx);
+	if (rx != din)
+		free(rx);
+
+ done:
+	if (flags & SPI_XFER_END)
+		spi_cs_deactivate(slave);
+
+	return ret;
+}
+
+/**
+ * Set up a new SPI slave for an fdt node
+ *
+ * @param blob		Device tree blob
+ * @param node		SPI peripheral node to use
+ * @return 0 if ok, -1 on error
+ */
+struct spi_slave *spi_setup_slave_fdt(const void *blob, int slave_node,
+				      int spi_node)
+{
+	return NULL;
+}
diff --git a/drivers/spi/sh_qspi.c b/drivers/spi/sh_qspi.c
new file mode 100644
index 0000000000..77ede6bba3
--- /dev/null
+++ b/drivers/spi/sh_qspi.c
@@ -0,0 +1,278 @@
+/*
+ * SH QSPI (Quad SPI) driver
+ *
+ * Copyright (C) 2013 Renesas Electronics Corporation
+ * Copyright (C) 2013 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0
+ */
+
+#include <common.h>
+#include <malloc.h>
+#include <spi.h>
+#include <asm/arch/rmobile.h>
+#include <asm/io.h>
+
+/* SH QSPI register bit masks <REG>_<BIT> */
+#define SPCR_MSTR	0x08
+#define SPCR_SPE	0x40
+#define SPSR_SPRFF	0x80
+#define SPSR_SPTEF	0x20
+#define SPPCR_IO3FV	0x04
+#define SPPCR_IO2FV	0x02
+#define SPPCR_IO1FV	0x01
+#define SPBDCR_RXBC0	(1 << 0)
+#define SPCMD_SCKDEN	(1 << 15)
+#define SPCMD_SLNDEN	(1 << 14)
+#define SPCMD_SPNDEN	(1 << 13)
+#define SPCMD_SSLKP	(1 << 7)
+#define SPCMD_BRDV0	(1 << 2)
+#define SPCMD_INIT1	SPCMD_SCKDEN | SPCMD_SLNDEN | \
+			SPCMD_SPNDEN | SPCMD_SSLKP | \
+			SPCMD_BRDV0
+#define SPCMD_INIT2	SPCMD_SPNDEN | SPCMD_SSLKP | \
+			SPCMD_BRDV0
+#define SPBFCR_TXRST	(1 << 7)
+#define SPBFCR_RXRST	(1 << 6)
+
+/* SH QSPI register set */
+struct sh_qspi_regs {
+	unsigned char spcr;
+	unsigned char sslp;
+	unsigned char sppcr;
+	unsigned char spsr;
+	unsigned long spdr;
+	unsigned char spscr;
+	unsigned char spssr;
+	unsigned char spbr;
+	unsigned char spdcr;
+	unsigned char spckd;
+	unsigned char sslnd;
+	unsigned char spnd;
+	unsigned char dummy0;
+	unsigned short spcmd0;
+	unsigned short spcmd1;
+	unsigned short spcmd2;
+	unsigned short spcmd3;
+	unsigned char spbfcr;
+	unsigned char dummy1;
+	unsigned short spbdcr;
+	unsigned long spbmul0;
+	unsigned long spbmul1;
+	unsigned long spbmul2;
+	unsigned long spbmul3;
+};
+
+struct sh_qspi_slave {
+	struct spi_slave	slave;
+	struct sh_qspi_regs	*regs;
+};
+
+static inline struct sh_qspi_slave *to_sh_qspi(struct spi_slave *slave)
+{
+	return container_of(slave, struct sh_qspi_slave, slave);
+}
+
+static void sh_qspi_init(struct sh_qspi_slave *ss)
+{
+	/* QSPI initialize */
+	/* Set master mode only */
+	writeb(SPCR_MSTR, &ss->regs->spcr);
+
+	/* Set SSL signal level */
+	writeb(0x00, &ss->regs->sslp);
+
+	/* Set MOSI signal value when transfer is in idle state */
+	writeb(SPPCR_IO3FV|SPPCR_IO2FV, &ss->regs->sppcr);
+
+	/* Set bit rate. See 58.3.8 Quad Serial Peripheral Interface */
+	writeb(0x01, &ss->regs->spbr);
+
+	/* Disable Dummy Data Transmission */
+	writeb(0x00, &ss->regs->spdcr);
+
+	/* Set clock delay value */
+	writeb(0x00, &ss->regs->spckd);
+
+	/* Set SSL negation delay value */
+	writeb(0x00, &ss->regs->sslnd);
+
+	/* Set next-access delay value */
+	writeb(0x00, &ss->regs->spnd);
+
+	/* Set equence command */
+	writew(SPCMD_INIT2, &ss->regs->spcmd0);
+
+	/* Reset transfer and receive Buffer */
+	setbits_8(&ss->regs->spbfcr, SPBFCR_TXRST|SPBFCR_RXRST);
+
+	/* Clear transfer and receive Buffer control bit */
+	clrbits_8(&ss->regs->spbfcr, SPBFCR_TXRST|SPBFCR_RXRST);
+
+	/* Set equence control method. Use equence0 only */
+	writeb(0x00, &ss->regs->spscr);
+
+	/* Enable SPI function */
+	setbits_8(&ss->regs->spcr, SPCR_SPE);
+}
+
+int spi_cs_is_valid(unsigned int bus, unsigned int cs)
+{
+	return 1;
+}
+
+void spi_cs_activate(struct spi_slave *slave)
+{
+	struct sh_qspi_slave *ss = to_sh_qspi(slave);
+
+	/* Set master mode only */
+	writeb(SPCR_MSTR, &ss->regs->spcr);
+
+	/* Set command */
+	writew(SPCMD_INIT1, &ss->regs->spcmd0);
+
+	/* Reset transfer and receive Buffer */
+	setbits_8(&ss->regs->spbfcr, SPBFCR_TXRST|SPBFCR_RXRST);
+
+	/* Clear transfer and receive Buffer control bit */
+	clrbits_8(&ss->regs->spbfcr, SPBFCR_TXRST|SPBFCR_RXRST);
+
+	/* Set equence control method. Use equence0 only */
+	writeb(0x00, &ss->regs->spscr);
+
+	/* Enable SPI function */
+	setbits_8(&ss->regs->spcr, SPCR_SPE);
+}
+
+void spi_cs_deactivate(struct spi_slave *slave)
+{
+	struct sh_qspi_slave *ss = to_sh_qspi(slave);
+
+	/* Disable SPI Function */
+	clrbits_8(&ss->regs->spcr, SPCR_SPE);
+}
+
+void spi_init(void)
+{
+	/* nothing to do */
+}
+
+struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
+		unsigned int max_hz, unsigned int mode)
+{
+	struct sh_qspi_slave *ss;
+
+	if (!spi_cs_is_valid(bus, cs))
+		return NULL;
+
+	ss = spi_alloc_slave(struct sh_qspi_slave, bus, cs);
+	if (!ss) {
+		printf("SPI_error: Fail to allocate sh_qspi_slave\n");
+		return NULL;
+	}
+
+	ss->regs = (struct sh_qspi_regs *)SH_QSPI_BASE;
+
+	/* Init SH QSPI */
+	sh_qspi_init(ss);
+
+	return &ss->slave;
+}
+
+void spi_free_slave(struct spi_slave *slave)
+{
+	struct sh_qspi_slave *spi = to_sh_qspi(slave);
+
+	free(spi);
+}
+
+int spi_claim_bus(struct spi_slave *slave)
+{
+	return 0;
+}
+
+void spi_release_bus(struct spi_slave *slave)
+{
+}
+
+int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
+	     void *din, unsigned long flags)
+{
+	struct sh_qspi_slave *ss = to_sh_qspi(slave);
+	unsigned long nbyte;
+	int ret = 0;
+	unsigned char dtdata = 0, drdata;
+	unsigned char *tdata = &dtdata, *rdata = &drdata;
+	unsigned long *spbmul0 = &ss->regs->spbmul0;
+
+	if (dout == NULL && din == NULL) {
+		if (flags & SPI_XFER_END)
+			spi_cs_deactivate(slave);
+		return 0;
+	}
+
+	if (bitlen % 8) {
+		printf("%s: bitlen is not 8bit alined %d", __func__, bitlen);
+		return 1;
+	}
+
+	nbyte = bitlen / 8;
+
+	if (flags & SPI_XFER_BEGIN) {
+		spi_cs_activate(slave);
+
+		/* Set 1048576 byte */
+		writel(0x100000, spbmul0);
+	}
+
+	if (flags & SPI_XFER_END)
+		writel(nbyte, spbmul0);
+
+	if (dout != NULL)
+		tdata = (unsigned char *)dout;
+
+	if (din != NULL)
+		rdata = din;
+
+	while (nbyte > 0) {
+		while (!(readb(&ss->regs->spsr) & SPSR_SPTEF)) {
+			if (ctrlc()) {
+				puts("abort\n");
+				return 1;
+			}
+			udelay(10);
+		}
+
+		writeb(*tdata, (unsigned char *)(&ss->regs->spdr));
+
+		while ((readw(&ss->regs->spbdcr) != SPBDCR_RXBC0)) {
+			if (ctrlc()) {
+				puts("abort\n");
+				return 1;
+			}
+			udelay(1);
+		}
+
+		while (!(readb(&ss->regs->spsr) & SPSR_SPRFF)) {
+			if (ctrlc()) {
+				puts("abort\n");
+				return 1;
+			}
+			udelay(10);
+		}
+
+		*rdata = readb((unsigned char *)(&ss->regs->spdr));
+
+		if (dout != NULL)
+			tdata++;
+		if (din != NULL)
+			rdata++;
+
+		nbyte--;
+	}
+
+	if (flags & SPI_XFER_END)
+		spi_cs_deactivate(slave);
+
+	return ret;
+}
diff --git a/drivers/spi/sh_spi.c b/drivers/spi/sh_spi.c
index 744afe3295..7ca5e363da 100644
--- a/drivers/spi/sh_spi.c
+++ b/drivers/spi/sh_spi.c
@@ -151,7 +151,6 @@ static int sh_spi_send(struct sh_spi *ss, const unsigned char *tx_data,
 {
 	int i, cur_len, ret = 0;
 	int remain = (int)len;
-	unsigned long tmp;
 
 	if (len >= SH_SPI_FIFO_SIZE)
 		sh_spi_set_bit(SH_SPI_SSA, &ss->regs->cr1);
@@ -183,9 +182,7 @@ static int sh_spi_send(struct sh_spi *ss, const unsigned char *tx_data,
 	}
 
 	if (flags & SPI_XFER_END) {
-		tmp = sh_spi_read(&ss->regs->cr1);
-		tmp = tmp & ~(SH_SPI_SSD | SH_SPI_SSDB);
-		sh_spi_write(tmp, &ss->regs->cr1);
+		sh_spi_clear_bit(SH_SPI_SSD | SH_SPI_SSDB, &ss->regs->cr1);
 		sh_spi_set_bit(SH_SPI_SSA, &ss->regs->cr1);
 		udelay(100);
 		write_fifo_empty_wait(ss);
@@ -198,16 +195,13 @@ static int sh_spi_receive(struct sh_spi *ss, unsigned char *rx_data,
 			  unsigned int len, unsigned long flags)
 {
 	int i;
-	unsigned long tmp;
 
 	if (len > SH_SPI_MAX_BYTE)
 		sh_spi_write(SH_SPI_MAX_BYTE, &ss->regs->cr3);
 	else
 		sh_spi_write(len, &ss->regs->cr3);
 
-	tmp = sh_spi_read(&ss->regs->cr1);
-	tmp = tmp & ~(SH_SPI_SSD | SH_SPI_SSDB);
-	sh_spi_write(tmp, &ss->regs->cr1);
+	sh_spi_clear_bit(SH_SPI_SSD | SH_SPI_SSDB, &ss->regs->cr1);
 	sh_spi_set_bit(SH_SPI_SSA, &ss->regs->cr1);
 
 	for (i = 0; i < len; i++) {
diff --git a/drivers/spi/spi.c b/drivers/spi/spi.c
index ea39d1a1ee..7ddea9b026 100644
--- a/drivers/spi/spi.c
+++ b/drivers/spi/spi.c
@@ -5,9 +5,22 @@
  */
 
 #include <common.h>
+#include <fdtdec.h>
 #include <malloc.h>
 #include <spi.h>
 
+int spi_set_wordlen(struct spi_slave *slave, unsigned int wordlen)
+{
+	if (wordlen == 0 || wordlen > 32) {
+		printf("spi: invalid wordlen %d\n", wordlen);
+		return -1;
+	}
+
+	slave->wordlen = wordlen;
+
+	return 0;
+}
+
 void *spi_do_alloc_slave(int offset, int size, unsigned int bus,
 			 unsigned int cs)
 {
@@ -20,7 +33,26 @@ void *spi_do_alloc_slave(int offset, int size, unsigned int bus,
 		slave = (struct spi_slave *)(ptr + offset);
 		slave->bus = bus;
 		slave->cs = cs;
+		slave->wordlen = SPI_DEFAULT_WORDLEN;
 	}
 
 	return ptr;
 }
+
+#ifdef CONFIG_OF_SPI
+struct spi_slave *spi_base_setup_slave_fdt(const void *blob, int busnum,
+					   int node)
+{
+	int cs, max_hz, mode = 0;
+
+	cs = fdtdec_get_int(blob, node, "reg", -1);
+	max_hz = fdtdec_get_int(blob, node, "spi-max-frequency", 100000);
+	if (fdtdec_get_bool(blob, node, "spi-cpol"))
+		mode |= SPI_CPOL;
+	if (fdtdec_get_bool(blob, node, "spi-cpha"))
+		mode |= SPI_CPHA;
+	if (fdtdec_get_bool(blob, node, "spi-cs-high"))
+		mode |= SPI_CS_HIGH;
+	return spi_setup_slave(busnum, cs, max_hz, mode);
+}
+#endif
diff --git a/drivers/spi/tegra114_spi.c b/drivers/spi/tegra114_spi.c
index 4d2af483d7..810fa4718c 100644
--- a/drivers/spi/tegra114_spi.c
+++ b/drivers/spi/tegra114_spi.c
@@ -289,9 +289,6 @@ int tegra114_spi_xfer(struct spi_slave *slave, unsigned int bitlen,
 	reg = readl(&regs->fifo_status);
 	writel(reg, &regs->fifo_status);
 
-	/* clear ready bit */
-	setbits_le32(&regs->xfer_status, SPI_XFER_STS_RDY);
-
 	clrsetbits_le32(&regs->command1, SPI_CMD1_CS_SW_VAL,
 			SPI_CMD1_RX_EN | SPI_CMD1_TX_EN | SPI_CMD1_LSBY_FE |
 			(slave->cs << SPI_CMD1_CS_SEL_SHIFT));
@@ -305,7 +302,6 @@ int tegra114_spi_xfer(struct spi_slave *slave, unsigned int bitlen,
 	/* handle data in 32-bit chunks */
 	while (num_bytes > 0) {
 		int bytes;
-		int is_read = 0;
 		int tm, i;
 
 		tmpdout = 0;
@@ -319,6 +315,9 @@ int tegra114_spi_xfer(struct spi_slave *slave, unsigned int bitlen,
 
 		num_bytes -= bytes;
 
+		/* clear ready bit */
+		setbits_le32(&regs->xfer_status, SPI_XFER_STS_RDY);
+
 		clrsetbits_le32(&regs->command1,
 				SPI_CMD1_BIT_LEN_MASK << SPI_CMD1_BIT_LEN_SHIFT,
 				(bytes * 8 - 1) << SPI_CMD1_BIT_LEN_SHIFT);
@@ -329,20 +328,14 @@ int tegra114_spi_xfer(struct spi_slave *slave, unsigned int bitlen,
 		 * Wait for SPI transmit FIFO to empty, or to time out.
 		 * The RX FIFO status will be read and cleared last
 		 */
-		for (tm = 0, is_read = 0; tm < SPI_TIMEOUT; ++tm) {
+		for (tm = 0; tm < SPI_TIMEOUT; ++tm) {
 			u32 fifo_status, xfer_status;
 
-			fifo_status = readl(&regs->fifo_status);
-
-			/* We can exit when we've had both RX and TX activity */
-			if (is_read &&
-			    (fifo_status & SPI_FIFO_STS_TX_FIFO_EMPTY))
-				break;
-
 			xfer_status = readl(&regs->xfer_status);
 			if (!(xfer_status & SPI_XFER_STS_RDY))
 				continue;
 
+			fifo_status = readl(&regs->fifo_status);
 			if (fifo_status & SPI_FIFO_STS_ERR) {
 				debug("%s: got a fifo error: ", __func__);
 				if (fifo_status & SPI_FIFO_STS_TX_FIFO_OVF)
@@ -367,7 +360,6 @@ int tegra114_spi_xfer(struct spi_slave *slave, unsigned int bitlen,
 
 			if (!(fifo_status & SPI_FIFO_STS_RX_FIFO_EMPTY)) {
 				tmpdin = readl(&regs->rx_fifo);
-				is_read = 1;
 
 				/* swap bytes read in */
 				if (din != NULL) {
@@ -377,6 +369,9 @@ int tegra114_spi_xfer(struct spi_slave *slave, unsigned int bitlen,
 					}
 					din += bytes;
 				}
+
+				/* We can exit when we've had both RX and TX */
+				break;
 			}
 		}
 
diff --git a/drivers/spi/ti_qspi.c b/drivers/spi/ti_qspi.c
index 5a5b482769..dfa5d0ca21 100644
--- a/drivers/spi/ti_qspi.c
+++ b/drivers/spi/ti_qspi.c
@@ -11,6 +11,8 @@
 #include <asm/arch/omap.h>
 #include <malloc.h>
 #include <spi.h>
+#include <asm/gpio.h>
+#include <asm/omap_gpio.h>
 
 /* ti qpsi register bit masks */
 #define QSPI_TIMEOUT                    2000000
@@ -39,7 +41,8 @@
 #define MM_SWITCH                       0x01
 #define MEM_CS                          0x100
 #define MEM_CS_UNSELECT                 0xfffff0ff
-#define MMAP_START_ADDR                 0x5c000000
+#define MMAP_START_ADDR_DRA		0x5c000000
+#define MMAP_START_ADDR_AM43x		0x30000000
 #define CORE_CTRL_IO                    0x4a002558
 
 #define QSPI_CMD_READ                   (0x3 << 0)
@@ -99,7 +102,11 @@ static void ti_spi_setup_spi_register(struct ti_qspi_slave *qslave)
 	struct spi_slave *slave = &qslave->slave;
 	u32 memval = 0;
 
-	slave->memory_map = (void *)MMAP_START_ADDR;
+#ifdef CONFIG_DRA7XX
+	slave->memory_map = (void *)MMAP_START_ADDR_DRA;
+#else
+	slave->memory_map = (void *)MMAP_START_ADDR_AM43x;
+#endif
 
 	memval |= QSPI_CMD_READ | QSPI_SETUP0_NUM_A_BYTES |
 			QSPI_SETUP0_NUM_D_BYTES_NO_BITS |
@@ -165,6 +172,11 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
 {
 	struct ti_qspi_slave *qslave;
 
+#ifdef CONFIG_AM43XX
+	gpio_request(CONFIG_QSPI_SEL_GPIO, "qspi_gpio");
+	gpio_direction_output(CONFIG_QSPI_SEL_GPIO, 1);
+#endif
+
 	qslave = spi_alloc_slave(struct ti_qspi_slave, bus, cs);
 	if (!qslave) {
 		printf("SPI_error: Fail to allocate ti_qspi_slave\n");
@@ -229,7 +241,11 @@ int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
 	const uchar *txp = dout;
 	uchar *rxp = din;
 	uint status;
-	int timeout, val;
+	int timeout;
+
+#ifdef CONFIG_DRA7XX
+	int val;
+#endif
 
 	debug("spi_xfer: bus:%i cs:%i bitlen:%i words:%i flags:%lx\n",
 	      slave->bus, slave->cs, bitlen, words, flags);
@@ -237,15 +253,19 @@ int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
 	/* Setup mmap flags */
 	if (flags & SPI_XFER_MMAP) {
 		writel(MM_SWITCH, &qslave->base->memswitch);
+#ifdef CONFIG_DRA7XX
 		val = readl(CORE_CTRL_IO);
 		val |= MEM_CS;
 		writel(val, CORE_CTRL_IO);
+#endif
 		return 0;
 	} else if (flags & SPI_XFER_MMAP_END) {
 		writel(~MM_SWITCH, &qslave->base->memswitch);
+#ifdef CONFIG_DRA7XX
 		val = readl(CORE_CTRL_IO);
 		val &= MEM_CS_UNSELECT;
 		writel(val, CORE_CTRL_IO);
+#endif
 		return 0;
 	}
 
@@ -265,6 +285,13 @@ int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
 		qslave->cmd |= QSPI_3_PIN;
 	qslave->cmd |= 0xfff;
 
+/* FIXME: This delay is required for successfull
+ * completion of read/write/erase. Once its root
+ * caused, it will be remove from the driver.
+ */
+#ifdef CONFIG_AM43XX
+	udelay(100);
+#endif
 	while (words--) {
 		if (txp) {
 			debug("tx cmd %08x dc %08x data %02x\n",
diff --git a/drivers/spi/xilinx_spi.c b/drivers/spi/xilinx_spi.c
index 5ac01846e4..56d99d17c7 100644
--- a/drivers/spi/xilinx_spi.c
+++ b/drivers/spi/xilinx_spi.c
@@ -149,6 +149,7 @@ int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
 	const unsigned char *txp = dout;
 	unsigned char *rxp = din;
 	unsigned rxecount = 17;	/* max. 16 elements in FIFO, leftover 1 */
+	unsigned global_timeout;
 
 	debug("%s: bus:%i cs:%i bitlen:%i bytes:%i flags:%lx\n", __func__,
 		slave->bus, slave->cs, bitlen, bytes, flags);
@@ -176,11 +177,12 @@ int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
 	if (flags & SPI_XFER_BEGIN)
 		spi_cs_activate(slave);
 
-	while (bytes--) {
-		unsigned timeout = /* at least 1usec or greater, leftover 1 */
-			xilspi->freq > XILSPI_MAX_XFER_BITS * 1000000 ? 2 :
+	/* at least 1usec or greater, leftover 1 */
+	global_timeout = xilspi->freq > XILSPI_MAX_XFER_BITS * 1000000 ? 2 :
 			(XILSPI_MAX_XFER_BITS * 1000000 / xilspi->freq) + 1;
 
+	while (bytes--) {
+		unsigned timeout = global_timeout;
 		/* get Tx element from data out buffer and count up */
 		unsigned char d = txp ? *txp++ : CONFIG_XILINX_SPI_IDLE_VAL;
 		debug("%s: tx:%x ", __func__, d);
diff --git a/drivers/tpm/Makefile b/drivers/tpm/Makefile
index 4457a78f8e..150570ee7e 100644
--- a/drivers/tpm/Makefile
+++ b/drivers/tpm/Makefile
@@ -3,31 +3,9 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB := $(obj)libtpm.o
-
-$(shell mkdir -p $(obj)slb9635_i2c)
-
 # TODO: Merge tpm_tis_lpc.c with tpm.c
-COBJS-$(CONFIG_TPM_ATMEL_TWI) += tpm_atmel_twi.o
-COBJS-$(CONFIG_TPM_TIS_I2C) += tpm.o
-COBJS-$(CONFIG_TPM_TIS_I2C) += tpm_tis_i2c.o
-COBJS-$(CONFIG_TPM_TIS_LPC) += tpm_tis_lpc.o
-
-COBJS	:= $(COBJS-y)
-SRCS	:= $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-
-all:	$(LIB)
-
-$(LIB): $(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-$(CONFIG_TPM_ATMEL_TWI) += tpm_atmel_twi.o
+obj-$(CONFIG_TPM_TIS_I2C) += tpm.o
+obj-$(CONFIG_TPM_TIS_I2C) += tpm_tis_i2c.o
+obj-$(CONFIG_TPM_TIS_LPC) += tpm_tis_lpc.o
+obj-$(CONFIG_TPM_TIS_SANDBOX) += tpm_tis_sandbox.o
diff --git a/drivers/tpm/tis_i2c.c b/drivers/tpm/tis_i2c.c
deleted file mode 100644
index 22554e1456..0000000000
--- a/drivers/tpm/tis_i2c.c
+++ /dev/null
@@ -1,185 +0,0 @@
-/*
- * Copyright (c) 2012 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include <config.h>
-#include <common.h>
-#include <fdtdec.h>
-#include <i2c.h>
-#include "slb9635_i2c/tpm.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-/* TPM configuration */
-struct tpm {
-	int i2c_bus;
-	int slave_addr;
-	char inited;
-	int old_bus;
-} tpm;
-
-
-static int tpm_select(void)
-{
-	int ret;
-
-	tpm.old_bus = i2c_get_bus_num();
-	if (tpm.old_bus != tpm.i2c_bus) {
-		ret = i2c_set_bus_num(tpm.i2c_bus);
-		if (ret) {
-			debug("%s: Fail to set i2c bus %d\n", __func__,
-			      tpm.i2c_bus);
-			return -1;
-		}
-	}
-	return 0;
-}
-
-static int tpm_deselect(void)
-{
-	int ret;
-
-	if (tpm.old_bus != i2c_get_bus_num()) {
-		ret = i2c_set_bus_num(tpm.old_bus);
-		if (ret) {
-			debug("%s: Fail to restore i2c bus %d\n",
-			      __func__, tpm.old_bus);
-			return -1;
-		}
-	}
-	tpm.old_bus = -1;
-	return 0;
-}
-
-/**
- * Decode TPM configuration.
- *
- * @param dev	Returns a configuration of TPM device
- * @return 0 if ok, -1 on error
- */
-static int tpm_decode_config(struct tpm *dev)
-{
-#ifdef CONFIG_OF_CONTROL
-	const void *blob = gd->fdt_blob;
-	int node, parent;
-	int i2c_bus;
-
-	node = fdtdec_next_compatible(blob, 0, COMPAT_INFINEON_SLB9635_TPM);
-	if (node < 0) {
-		node = fdtdec_next_compatible(blob, 0,
-					      COMPAT_INFINEON_SLB9645_TPM);
-	}
-	if (node < 0) {
-		debug("%s: Node not found\n", __func__);
-		return -1;
-	}
-	parent = fdt_parent_offset(blob, node);
-	if (parent < 0) {
-		debug("%s: Cannot find node parent\n", __func__);
-		return -1;
-	}
-	i2c_bus = i2c_get_bus_num_fdt(parent);
-	if (i2c_bus < 0)
-		return -1;
-	dev->i2c_bus = i2c_bus;
-	dev->slave_addr = fdtdec_get_addr(blob, node, "reg");
-#else
-	dev->i2c_bus = CONFIG_INFINEON_TPM_I2C_BUS;
-	dev->slave_addr = CONFIG_INFINEON_TPM_I2C_ADDR;
-#endif
-	return 0;
-}
-
-int tis_init(void)
-{
-	if (tpm.inited)
-		return 0;
-
-	if (tpm_decode_config(&tpm))
-		return -1;
-
-	if (tpm_select())
-		return -1;
-
-	/*
-	 * Probe TPM twice; the first probing might fail because TPM is asleep,
-	 * and the probing can wake up TPM.
-	 */
-	if (i2c_probe(tpm.slave_addr) && i2c_probe(tpm.slave_addr)) {
-		debug("%s: fail to probe i2c addr 0x%x\n", __func__,
-		      tpm.slave_addr);
-		return -1;
-	}
-
-	tpm_deselect();
-
-	tpm.inited = 1;
-
-	return 0;
-}
-
-int tis_open(void)
-{
-	int rc;
-
-	if (!tpm.inited)
-		return -1;
-
-	if (tpm_select())
-		return -1;
-
-	rc = tpm_open(tpm.slave_addr);
-
-	tpm_deselect();
-
-	return rc;
-}
-
-int tis_close(void)
-{
-	if (!tpm.inited)
-		return -1;
-
-	if (tpm_select())
-		return -1;
-
-	tpm_close();
-
-	tpm_deselect();
-
-	return 0;
-}
-
-int tis_sendrecv(const uint8_t *sendbuf, size_t sbuf_size,
-		uint8_t *recvbuf, size_t *rbuf_len)
-{
-	int len;
-	uint8_t buf[4096];
-
-	if (!tpm.inited)
-		return -1;
-
-	if (sizeof(buf) < sbuf_size)
-		return -1;
-
-	memcpy(buf, sendbuf, sbuf_size);
-
-	if (tpm_select())
-		return -1;
-
-	len = tpm_transmit(buf, sbuf_size);
-
-	tpm_deselect();
-
-	if (len < 10) {
-		*rbuf_len = 0;
-		return -1;
-	}
-
-	memcpy(recvbuf, buf, len);
-	*rbuf_len = len;
-
-	return 0;
-}
diff --git a/drivers/tpm/tpm_tis_sandbox.c b/drivers/tpm/tpm_tis_sandbox.c
new file mode 100644
index 0000000000..ed4b039127
--- /dev/null
+++ b/drivers/tpm/tpm_tis_sandbox.c
@@ -0,0 +1,260 @@
+/*
+ * Copyright (c) 2013 Google, Inc
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/state.h>
+#include <asm/unaligned.h>
+#include <linux/crc8.h>
+
+/* TPM NVRAM location indices. */
+#define FIRMWARE_NV_INDEX		0x1007
+#define KERNEL_NV_INDEX			0x1008
+
+#define NV_DATA_PUBLIC_PERMISSIONS_OFFSET	60
+
+/* Kernel TPM space - KERNEL_NV_INDEX, locked with physical presence */
+#define ROLLBACK_SPACE_KERNEL_VERSION	2
+#define ROLLBACK_SPACE_KERNEL_UID	0x4752574C  /* 'GRWL' */
+
+struct rollback_space_kernel {
+	/* Struct version, for backwards compatibility */
+	uint8_t struct_version;
+	/* Unique ID to detect space redefinition */
+	uint32_t uid;
+	/* Kernel versions */
+	uint32_t kernel_versions;
+	/* Reserved for future expansion */
+	uint8_t reserved[3];
+	/* Checksum (v2 and later only) */
+	uint8_t crc8;
+} __packed rollback_space_kernel;
+
+/*
+ * These numbers derive from adding the sizes of command fields as shown in
+ * the TPM commands manual.
+ */
+#define TPM_REQUEST_HEADER_LENGTH	10
+#define TPM_RESPONSE_HEADER_LENGTH	10
+
+/* These are the different non-volatile spaces that we emulate */
+enum {
+	NV_GLOBAL_LOCK,
+	NV_SEQ_FIRMWARE,
+	NV_SEQ_KERNEL,
+	NV_SEQ_COUNT,
+};
+
+/* Size of each non-volatile space */
+#define NV_DATA_SIZE		0x20
+
+/*
+ * Information about our TPM emulation. This is preserved in the sandbox
+ * state file if enabled.
+ */
+static struct tpm_state {
+	uint8_t nvdata[NV_SEQ_COUNT][NV_DATA_SIZE];
+} state;
+
+/**
+ * sandbox_tpm_read_state() - read the sandbox EC state from the state file
+ *
+ * If data is available, then blob and node will provide access to it. If
+ * not this function sets up an empty TPM.
+ *
+ * @blob: Pointer to device tree blob, or NULL if no data to read
+ * @node: Node offset to read from
+ */
+static int sandbox_tpm_read_state(const void *blob, int node)
+{
+	const char *prop;
+	int len;
+	int i;
+
+	if (!blob)
+		return 0;
+
+	for (i = 0; i < NV_SEQ_COUNT; i++) {
+		char prop_name[20];
+
+		sprintf(prop_name, "nvdata%d", i);
+		prop = fdt_getprop(blob, node, prop_name, &len);
+		if (prop && len == NV_DATA_SIZE)
+			memcpy(state.nvdata[i], prop, NV_DATA_SIZE);
+	}
+
+	return 0;
+}
+
+/**
+ * cros_ec_write_state() - Write out our state to the state file
+ *
+ * The caller will ensure that there is a node ready for the state. The node
+ * may already contain the old state, in which case it is overridden.
+ *
+ * @blob: Device tree blob holding state
+ * @node: Node to write our state into
+ */
+static int sandbox_tpm_write_state(void *blob, int node)
+{
+	int i;
+
+	/*
+	 * We are guaranteed enough space to write basic properties.
+	 * We could use fdt_add_subnode() to put each set of data in its
+	 * own node - perhaps useful if we add access informaiton to each.
+	 */
+	for (i = 0; i < NV_SEQ_COUNT; i++) {
+		char prop_name[20];
+
+		sprintf(prop_name, "nvdata%d", i);
+		fdt_setprop(blob, node, prop_name, state.nvdata[i],
+			    NV_DATA_SIZE);
+	}
+
+	return 0;
+}
+
+SANDBOX_STATE_IO(sandbox_tpm, "google,sandbox-tpm", sandbox_tpm_read_state,
+		 sandbox_tpm_write_state);
+
+static int index_to_seq(uint32_t index)
+{
+	switch (index) {
+	case FIRMWARE_NV_INDEX:
+		return NV_SEQ_FIRMWARE;
+	case KERNEL_NV_INDEX:
+		return NV_SEQ_KERNEL;
+	case 0:
+		return NV_GLOBAL_LOCK;
+	}
+
+	printf("Invalid nv index %#x\n", index);
+	return -1;
+}
+
+int tis_sendrecv(const u8 *sendbuf, size_t send_size,
+		 u8 *recvbuf, size_t *recv_len)
+{
+	struct tpm_state *tpm = &state;
+	uint32_t code, index, length, type;
+	uint8_t *data;
+	int seq;
+
+	code = get_unaligned_be32(sendbuf + sizeof(uint16_t) +
+				  sizeof(uint32_t));
+	printf("tpm: %zd bytes, recv_len %zd, cmd = %x\n", send_size,
+	       *recv_len, code);
+	print_buffer(0, sendbuf, 1, send_size, 0);
+	switch (code) {
+	case 0x65: /* get flags */
+		type = get_unaligned_be32(sendbuf + 14);
+		switch (type) {
+		case 4:
+			index = get_unaligned_be32(sendbuf + 18);
+			printf("Get flags index %#02x\n", index);
+			*recv_len = 22;
+			memset(recvbuf, '\0', *recv_len);
+			put_unaligned_be32(22, recvbuf +
+					   TPM_RESPONSE_HEADER_LENGTH);
+			data = recvbuf + TPM_RESPONSE_HEADER_LENGTH +
+					sizeof(uint32_t);
+			switch (index) {
+			case FIRMWARE_NV_INDEX:
+				break;
+			case KERNEL_NV_INDEX:
+				/* TPM_NV_PER_PPWRITE */
+				put_unaligned_be32(1, data +
+					NV_DATA_PUBLIC_PERMISSIONS_OFFSET);
+				break;
+			}
+			break;
+		case 0x11: /* TPM_CAP_NV_INDEX */
+			index = get_unaligned_be32(sendbuf + 18);
+			printf("Get cap nv index %#02x\n", index);
+			put_unaligned_be32(22, recvbuf +
+					   TPM_RESPONSE_HEADER_LENGTH);
+			break;
+		default:
+			printf("   ** Unknown 0x65 command type %#02x\n",
+			       type);
+			return -1;
+		}
+		break;
+	case 0xcd: /* nvwrite */
+		index = get_unaligned_be32(sendbuf + 10);
+		length = get_unaligned_be32(sendbuf + 18);
+		seq = index_to_seq(index);
+		if (seq < 0)
+			return -1;
+		printf("tpm: nvwrite index=%#02x, len=%#02x\n", index, length);
+		memcpy(&tpm->nvdata[seq], sendbuf + 22, length);
+		*recv_len = 12;
+		memset(recvbuf, '\0', *recv_len);
+		break;
+	case 0xcf: /* nvread */
+		index = get_unaligned_be32(sendbuf + 10);
+		length = get_unaligned_be32(sendbuf + 18);
+		seq = index_to_seq(index);
+		if (seq < 0)
+			return -1;
+		printf("tpm: nvread index=%#02x, len=%#02x\n", index, length);
+		*recv_len = TPM_RESPONSE_HEADER_LENGTH + sizeof(uint32_t) +
+					length;
+		memset(recvbuf, '\0', *recv_len);
+		put_unaligned_be32(length, recvbuf +
+				   TPM_RESPONSE_HEADER_LENGTH);
+		if (seq == NV_SEQ_KERNEL) {
+			struct rollback_space_kernel rsk;
+
+			data = recvbuf + TPM_RESPONSE_HEADER_LENGTH +
+					sizeof(uint32_t);
+			rsk.struct_version = 2;
+			rsk.uid = ROLLBACK_SPACE_KERNEL_UID;
+			rsk.kernel_versions = 0;
+			rsk.crc8 = crc8((unsigned char *)&rsk,
+					offsetof(struct rollback_space_kernel,
+						 crc8));
+			memcpy(data, &rsk, sizeof(rsk));
+		} else {
+			memcpy(recvbuf + TPM_RESPONSE_HEADER_LENGTH +
+			       sizeof(uint32_t), &tpm->nvdata[seq], length);
+		}
+		break;
+	case 0x14: /* tpm extend */
+	case 0x15: /* pcr read */
+	case 0x5d: /* force clear */
+	case 0x6f: /* physical enable */
+	case 0x72: /* physical set deactivated */
+	case 0x99: /* startup */
+	case 0x4000000a:  /* assert physical presence */
+		*recv_len = 12;
+		memset(recvbuf, '\0', *recv_len);
+		break;
+	default:
+		printf("Unknown tpm command %02x\n", code);
+		return -1;
+	}
+
+	return 0;
+}
+
+int tis_open(void)
+{
+	printf("%s\n", __func__);
+	return 0;
+}
+
+int tis_close(void)
+{
+	printf("%s\n", __func__);
+	return 0;
+}
+
+int tis_init(void)
+{
+	printf("%s\n", __func__);
+	return 0;
+}
diff --git a/drivers/twserial/Makefile b/drivers/twserial/Makefile
index ac2273556c..7cc7c4de82 100644
--- a/drivers/twserial/Makefile
+++ b/drivers/twserial/Makefile
@@ -5,26 +5,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	:= $(obj)libtws.o
-
-COBJS-$(CONFIG_SOFT_TWS) += soft_tws.o
-
-COBJS	:= $(COBJS-y)
-SRCS	:= $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-
-all:	$(LIB)
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-$(CONFIG_SOFT_TWS) += soft_tws.o
diff --git a/drivers/usb/eth/Makefile b/drivers/usb/eth/Makefile
index 04a8b58c89..94551c4c0c 100644
--- a/drivers/usb/eth/Makefile
+++ b/drivers/usb/eth/Makefile
@@ -3,31 +3,10 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	:= $(obj)libusb_eth.o
-
 # new USB host ethernet layer dependencies
-COBJS-$(CONFIG_USB_HOST_ETHER) += usb_ether.o
+obj-$(CONFIG_USB_HOST_ETHER) += usb_ether.o
 ifdef CONFIG_USB_ETHER_ASIX
-COBJS-y += asix.o
+obj-y += asix.o
 endif
-COBJS-$(CONFIG_USB_ETHER_SMSC95XX) += smsc95xx.o
-
-COBJS	:= $(COBJS-y)
-SRCS	:= $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-
-all:	$(LIB)
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-$(CONFIG_USB_ETHER_MCS7830) += mcs7830.o
+obj-$(CONFIG_USB_ETHER_SMSC95XX) += smsc95xx.o
diff --git a/drivers/usb/eth/asix.c b/drivers/usb/eth/asix.c
index 659533a8d4..ce133f0069 100644
--- a/drivers/usb/eth/asix.c
+++ b/drivers/usb/eth/asix.c
@@ -468,8 +468,6 @@ static int asix_send(struct eth_device *eth, void *packet, int length)
 
 	memcpy(msg, &packet_len, sizeof(packet_len));
 	memcpy(msg + sizeof(packet_len), (void *)packet, length);
-	if (length & 1)
-		length++;
 
 	err = usb_bulk_msg(dev->pusb_dev,
 				usb_sndbulkpipe(dev->pusb_dev, dev->ep_out),
diff --git a/drivers/usb/eth/mcs7830.c b/drivers/usb/eth/mcs7830.c
new file mode 100644
index 0000000000..c353286b60
--- /dev/null
+++ b/drivers/usb/eth/mcs7830.c
@@ -0,0 +1,812 @@
+/*
+ * Copyright (c) 2013 Gerhard Sittig <gsi@denx.de>
+ * based on the U-Boot Asix driver as well as information
+ * from the Linux Moschip driver
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * MOSCHIP MCS7830 based (7730/7830/7832) USB 2.0 Ethernet Devices
+ */
+
+#include <common.h>
+#include <errno.h>
+#include <linux/mii.h>
+#include <malloc.h>
+#include <usb.h>
+
+#include "usb_ether.h"
+
+#define MCS7830_BASE_NAME	"mcs"
+
+#define USBCALL_TIMEOUT		1000
+#define LINKSTATUS_TIMEOUT	5000	/* link status, connect timeout */
+#define LINKSTATUS_TIMEOUT_RES	50	/* link status, resolution in msec */
+
+#define MCS7830_RX_URB_SIZE	2048
+
+/* command opcodes */
+#define MCS7830_WR_BREQ		0x0d
+#define MCS7830_RD_BREQ		0x0e
+
+/* register layout, numerical offset specs for USB API calls */
+struct mcs7830_regs {
+	uint8_t multicast_hashes[8];
+	uint8_t packet_gap[2];
+	uint8_t phy_data[2];
+	uint8_t phy_command[2];
+	uint8_t configuration;
+	uint8_t ether_address[6];
+	uint8_t frame_drop_count;
+	uint8_t pause_threshold;
+};
+#define REG_MULTICAST_HASH	offsetof(struct mcs7830_regs, multicast_hashes)
+#define REG_PHY_DATA		offsetof(struct mcs7830_regs, phy_data)
+#define REG_PHY_CMD		offsetof(struct mcs7830_regs, phy_command)
+#define REG_CONFIG		offsetof(struct mcs7830_regs, configuration)
+#define REG_ETHER_ADDR		offsetof(struct mcs7830_regs, ether_address)
+#define REG_FRAME_DROP_COUNTER	offsetof(struct mcs7830_regs, frame_drop_count)
+#define REG_PAUSE_THRESHOLD	offsetof(struct mcs7830_regs, pause_threshold)
+
+/* bit masks and default values for the above registers */
+#define PHY_CMD1_READ		0x40
+#define PHY_CMD1_WRITE		0x20
+#define PHY_CMD1_PHYADDR	0x01
+
+#define PHY_CMD2_PEND		0x80
+#define PHY_CMD2_READY		0x40
+
+#define CONF_CFG		0x80
+#define CONF_SPEED100		0x40
+#define CONF_FDX_ENABLE		0x20
+#define CONF_RXENABLE		0x10
+#define CONF_TXENABLE		0x08
+#define CONF_SLEEPMODE		0x04
+#define CONF_ALLMULTICAST	0x02
+#define CONF_PROMISCUOUS	0x01
+
+#define PAUSE_THRESHOLD_DEFAULT	0
+
+/* bit masks for the status byte which follows received ethernet frames */
+#define STAT_RX_FRAME_CORRECT	0x20
+#define STAT_RX_LARGE_FRAME	0x10
+#define STAT_RX_CRC_ERROR	0x08
+#define STAT_RX_ALIGNMENT_ERROR	0x04
+#define STAT_RX_LENGTH_ERROR	0x02
+#define STAT_RX_SHORT_FRAME	0x01
+
+/*
+ * struct mcs7830_private - private driver data for an individual adapter
+ * @config:	shadow for the network adapter's configuration register
+ * @mchash:	shadow for the network adapter's multicast hash registers
+ */
+struct mcs7830_private {
+	uint8_t config;
+	uint8_t mchash[8];
+};
+
+/*
+ * mcs7830_read_reg() - read a register of the network adapter
+ * @dev:	network device to read from
+ * @idx:	index of the register to start reading from
+ * @size:	number of bytes to read
+ * @data:	buffer to read into
+ * Return: zero upon success, negative upon error
+ */
+static int mcs7830_read_reg(struct ueth_data *dev, uint8_t idx,
+			    uint16_t size, void *data)
+{
+	int len;
+	ALLOC_CACHE_ALIGN_BUFFER(uint8_t, buf, size);
+
+	debug("%s() idx=0x%04X sz=%d\n", __func__, idx, size);
+
+	len = usb_control_msg(dev->pusb_dev,
+			      usb_rcvctrlpipe(dev->pusb_dev, 0),
+			      MCS7830_RD_BREQ,
+			      USB_DIR_IN | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
+			      0, idx, buf, size,
+			      USBCALL_TIMEOUT);
+	if (len != size) {
+		debug("%s() len=%d != sz=%d\n", __func__, len, size);
+		return -EIO;
+	}
+	memcpy(data, buf, size);
+	return 0;
+}
+
+/*
+ * mcs7830_write_reg() - write a register of the network adapter
+ * @dev:	network device to write to
+ * @idx:	index of the register to start writing to
+ * @size:	number of bytes to write
+ * @data:	buffer holding the data to write
+ * Return: zero upon success, negative upon error
+ */
+static int mcs7830_write_reg(struct ueth_data *dev, uint8_t idx,
+			     uint16_t size, void *data)
+{
+	int len;
+	ALLOC_CACHE_ALIGN_BUFFER(uint8_t, buf, size);
+
+	debug("%s() idx=0x%04X sz=%d\n", __func__, idx, size);
+
+	memcpy(buf, data, size);
+	len = usb_control_msg(dev->pusb_dev,
+			      usb_sndctrlpipe(dev->pusb_dev, 0),
+			      MCS7830_WR_BREQ,
+			      USB_DIR_OUT | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
+			      0, idx, buf, size,
+			      USBCALL_TIMEOUT);
+	if (len != size) {
+		debug("%s() len=%d != sz=%d\n", __func__, len, size);
+		return -EIO;
+	}
+	return 0;
+}
+
+/*
+ * mcs7830_phy_emit_wait() - emit PHY read/write access, wait for its execution
+ * @dev:	network device to talk to
+ * @rwflag:	PHY_CMD1_READ or PHY_CMD1_WRITE opcode
+ * @index:	number of the PHY register to read or write
+ * Return: zero upon success, negative upon error
+ */
+static int mcs7830_phy_emit_wait(struct ueth_data *dev,
+				 uint8_t rwflag, uint8_t index)
+{
+	int rc;
+	int retry;
+	uint8_t cmd[2];
+
+	/* send the PHY read/write request */
+	cmd[0] = rwflag | PHY_CMD1_PHYADDR;
+	cmd[1] = PHY_CMD2_PEND | (index & 0x1f);
+	rc = mcs7830_write_reg(dev, REG_PHY_CMD, sizeof(cmd), cmd);
+	if (rc < 0)
+		return rc;
+
+	/* wait for the response to become available (usually < 1ms) */
+	retry = 10;
+	do {
+		rc = mcs7830_read_reg(dev, REG_PHY_CMD, sizeof(cmd), cmd);
+		if (rc < 0)
+			return rc;
+		if (cmd[1] & PHY_CMD2_READY)
+			return 0;
+		if (!retry--)
+			return -ETIMEDOUT;
+		mdelay(1);
+	} while (1);
+	/* UNREACH */
+}
+
+/*
+ * mcs7830_read_phy() - read a PHY register of the network adapter
+ * @dev:	network device to read from
+ * @index:	index of the PHY register to read from
+ * Return: non-negative 16bit register content, negative upon error
+ */
+static int mcs7830_read_phy(struct ueth_data *dev, uint8_t index)
+{
+	int rc;
+	uint16_t val;
+
+	/* issue the PHY read request and wait for its execution */
+	rc = mcs7830_phy_emit_wait(dev, PHY_CMD1_READ, index);
+	if (rc < 0)
+		return rc;
+
+	/* fetch the PHY data which was read */
+	rc = mcs7830_read_reg(dev, REG_PHY_DATA, sizeof(val), &val);
+	if (rc < 0)
+		return rc;
+	rc = le16_to_cpu(val);
+	debug("%s(%s, %d) => 0x%04X\n", __func__, dev->eth_dev.name, index, rc);
+	return rc;
+}
+
+/*
+ * mcs7830_write_phy() - write a PHY register of the network adapter
+ * @dev:	network device to write to
+ * @index:	index of the PHY register to write to
+ * @val:	value to write to the PHY register
+ * Return: zero upon success, negative upon error
+ */
+static int mcs7830_write_phy(struct ueth_data *dev, uint8_t index, uint16_t val)
+{
+	int rc;
+
+	debug("%s(%s, %d, 0x%04X)\n", __func__, dev->eth_dev.name, index, val);
+
+	/* setup the PHY data which is to get written */
+	val = cpu_to_le16(val);
+	rc = mcs7830_write_reg(dev, REG_PHY_DATA, sizeof(val), &val);
+	if (rc < 0)
+		return rc;
+
+	/* issue the PHY write request and wait for its execution */
+	rc = mcs7830_phy_emit_wait(dev, PHY_CMD1_WRITE, index);
+	if (rc < 0)
+		return rc;
+
+	return 0;
+}
+
+/*
+ * mcs7830_write_config() - write to the network adapter's config register
+ * @eth:	network device to write to
+ * Return: zero upon success, negative upon error
+ *
+ * the data which gets written is taken from the shadow config register
+ * within the device driver's private data
+ */
+static int mcs7830_write_config(struct ueth_data *dev)
+{
+	struct mcs7830_private *priv;
+	int rc;
+
+	debug("%s()\n", __func__);
+	priv = dev->dev_priv;
+
+	rc = mcs7830_write_reg(dev, REG_CONFIG,
+			       sizeof(priv->config), &priv->config);
+	if (rc < 0) {
+		debug("writing config to adapter failed\n");
+		return rc;
+	}
+
+	return 0;
+}
+
+/*
+ * mcs7830_write_mchash() - write the network adapter's multicast filter
+ * @eth:	network device to write to
+ * Return: zero upon success, negative upon error
+ *
+ * the data which gets written is taken from the shadow multicast hashes
+ * within the device driver's private data
+ */
+static int mcs7830_write_mchash(struct ueth_data *dev)
+{
+	struct mcs7830_private *priv;
+	int rc;
+
+	debug("%s()\n", __func__);
+	priv = dev->dev_priv;
+
+	rc = mcs7830_write_reg(dev, REG_MULTICAST_HASH,
+			       sizeof(priv->mchash), &priv->mchash);
+	if (rc < 0) {
+		debug("writing multicast hash to adapter failed\n");
+		return rc;
+	}
+
+	return 0;
+}
+
+/*
+ * mcs7830_set_autoneg() - setup and trigger ethernet link autonegotiation
+ * @eth:	network device to run link negotiation on
+ * Return: zero upon success, negative upon error
+ *
+ * the routine advertises available media and starts autonegotiation
+ */
+static int mcs7830_set_autoneg(struct ueth_data *dev)
+{
+	int adv, flg;
+	int rc;
+
+	debug("%s()\n", __func__);
+
+	/*
+	 * algorithm taken from the Linux driver, which took it from
+	 * "the original mcs7830 version 1.4 driver":
+	 *
+	 * enable all media, reset BMCR, enable auto neg, restart
+	 * auto neg while keeping the enable auto neg flag set
+	 */
+
+	adv = ADVERTISE_PAUSE_CAP | ADVERTISE_ALL | ADVERTISE_CSMA;
+	rc = mcs7830_write_phy(dev, MII_ADVERTISE, adv);
+
+	flg = 0;
+	if (!rc)
+		rc = mcs7830_write_phy(dev, MII_BMCR, flg);
+
+	flg |= BMCR_ANENABLE;
+	if (!rc)
+		rc = mcs7830_write_phy(dev, MII_BMCR, flg);
+
+	flg |= BMCR_ANRESTART;
+	if (!rc)
+		rc = mcs7830_write_phy(dev, MII_BMCR, flg);
+
+	return rc;
+}
+
+/*
+ * mcs7830_get_rev() - identify a network adapter's chip revision
+ * @eth:	network device to identify
+ * Return: non-negative number, reflecting the revision number
+ *
+ * currently, only "rev C and higher" and "below rev C" are needed, so
+ * the return value is #1 for "below rev C", and #2 for "rev C and above"
+ */
+static int mcs7830_get_rev(struct ueth_data *dev)
+{
+	uint8_t buf[2];
+	int rc;
+	int rev;
+
+	/* register 22 is readable in rev C and higher */
+	rc = mcs7830_read_reg(dev, REG_FRAME_DROP_COUNTER, sizeof(buf), buf);
+	if (rc < 0)
+		rev = 1;
+	else
+		rev = 2;
+	debug("%s() rc=%d, rev=%d\n", __func__, rc, rev);
+	return rev;
+}
+
+/*
+ * mcs7830_apply_fixup() - identify an adapter and potentially apply fixups
+ * @eth:	network device to identify and apply fixups to
+ * Return: zero upon success (no errors emitted from here)
+ *
+ * this routine identifies the network adapter's chip revision, and applies
+ * fixups for known issues
+ */
+static int mcs7830_apply_fixup(struct ueth_data *dev)
+{
+	int rev;
+	int i;
+	uint8_t thr;
+
+	rev = mcs7830_get_rev(dev);
+	debug("%s() rev=%d\n", __func__, rev);
+
+	/*
+	 * rev C requires setting the pause threshold (the Linux driver
+	 * is inconsistent, the implementation does it for "rev C
+	 * exactly", the introductory comment says "rev C and above")
+	 */
+	if (rev == 2) {
+		debug("%s: applying rev C fixup\n", dev->eth_dev.name);
+		thr = PAUSE_THRESHOLD_DEFAULT;
+		for (i = 0; i < 2; i++) {
+			(void)mcs7830_write_reg(dev, REG_PAUSE_THRESHOLD,
+						sizeof(thr), &thr);
+			mdelay(1);
+		}
+	}
+
+	return 0;
+}
+
+/*
+ * mcs7830_basic_reset() - bring the network adapter into a known first state
+ * @eth:	network device to act upon
+ * Return: zero upon success, negative upon error
+ *
+ * this routine initializes the network adapter such that subsequent invocations
+ * of the interface callbacks can exchange ethernet frames; link negotiation is
+ * triggered from here already and continues in background
+ */
+static int mcs7830_basic_reset(struct ueth_data *dev)
+{
+	struct mcs7830_private *priv;
+	int rc;
+
+	debug("%s()\n", __func__);
+	priv = dev->dev_priv;
+
+	/*
+	 * comment from the respective Linux driver, which
+	 * unconditionally sets the ALLMULTICAST flag as well:
+	 * should not be needed, but does not work otherwise
+	 */
+	priv->config = CONF_TXENABLE;
+	priv->config |= CONF_ALLMULTICAST;
+
+	rc = mcs7830_set_autoneg(dev);
+	if (rc < 0) {
+		error("setting autoneg failed\n");
+		return rc;
+	}
+
+	rc = mcs7830_write_mchash(dev);
+	if (rc < 0) {
+		error("failed to set multicast hash\n");
+		return rc;
+	}
+
+	rc = mcs7830_write_config(dev);
+	if (rc < 0) {
+		error("failed to set configuration\n");
+		return rc;
+	}
+
+	rc = mcs7830_apply_fixup(dev);
+	if (rc < 0) {
+		error("fixup application failed\n");
+		return rc;
+	}
+
+	return 0;
+}
+
+/*
+ * mcs7830_read_mac() - read an ethernet adapter's MAC address
+ * @eth:	network device to read from
+ * Return: zero upon success, negative upon error
+ *
+ * this routine fetches the MAC address stored within the ethernet adapter,
+ * and stores it in the ethernet interface's data structure
+ */
+static int mcs7830_read_mac(struct eth_device *eth)
+{
+	struct ueth_data *dev;
+	int rc;
+	uint8_t buf[ETH_ALEN];
+
+	debug("%s()\n", __func__);
+	dev = eth->priv;
+
+	rc = mcs7830_read_reg(dev, REG_ETHER_ADDR, ETH_ALEN, buf);
+	if (rc < 0) {
+		debug("reading MAC from adapter failed\n");
+		return rc;
+	}
+
+	memcpy(&eth->enetaddr[0], buf, ETH_ALEN);
+	return 0;
+}
+
+/*
+ * mcs7830_write_mac() - write an ethernet adapter's MAC address
+ * @eth:	network device to write to
+ * Return: zero upon success, negative upon error
+ *
+ * this routine takes the MAC address from the ethernet interface's data
+ * structure, and writes it into the ethernet adapter such that subsequent
+ * exchange of ethernet frames uses this address
+ */
+static int mcs7830_write_mac(struct eth_device *eth)
+{
+	struct ueth_data *dev;
+	int rc;
+
+	debug("%s()\n", __func__);
+	dev = eth->priv;
+
+	if (sizeof(eth->enetaddr) != ETH_ALEN)
+		return -EINVAL;
+	rc = mcs7830_write_reg(dev, REG_ETHER_ADDR, ETH_ALEN, eth->enetaddr);
+	if (rc < 0) {
+		debug("writing MAC to adapter failed\n");
+		return rc;
+	}
+	return 0;
+}
+
+/*
+ * mcs7830_init() - network interface's init callback
+ * @eth:	network device to initialize
+ * @bd:		board information
+ * Return: zero upon success, negative upon error
+ *
+ * after initial setup during probe() and get_info(), this init() callback
+ * ensures that the link is up and subsequent send() and recv() calls can
+ * exchange ethernet frames
+ */
+static int mcs7830_init(struct eth_device *eth, bd_t *bd)
+{
+	struct ueth_data *dev;
+	int timeout;
+	int have_link;
+
+	debug("%s()\n", __func__);
+	dev = eth->priv;
+
+	timeout = 0;
+	do {
+		have_link = mcs7830_read_phy(dev, MII_BMSR) & BMSR_LSTATUS;
+		if (have_link)
+			break;
+		udelay(LINKSTATUS_TIMEOUT_RES * 1000);
+		timeout += LINKSTATUS_TIMEOUT_RES;
+	} while (timeout < LINKSTATUS_TIMEOUT);
+	if (!have_link) {
+		debug("ethernet link is down\n");
+		return -ETIMEDOUT;
+	}
+	return 0;
+}
+
+/*
+ * mcs7830_send() - network interface's send callback
+ * @eth:	network device to send the frame from
+ * @packet:	ethernet frame content
+ * @length:	ethernet frame length
+ * Return: zero upon success, negative upon error
+ *
+ * this routine send an ethernet frame out of the network interface
+ */
+static int mcs7830_send(struct eth_device *eth, void *packet, int length)
+{
+	struct ueth_data *dev;
+	int rc;
+	int gotlen;
+	/* there is a status byte after the ethernet frame */
+	ALLOC_CACHE_ALIGN_BUFFER(uint8_t, buf, PKTSIZE + sizeof(uint8_t));
+
+	dev = eth->priv;
+
+	memcpy(buf, packet, length);
+	rc = usb_bulk_msg(dev->pusb_dev,
+			  usb_sndbulkpipe(dev->pusb_dev, dev->ep_out),
+			  &buf[0], length, &gotlen,
+			  USBCALL_TIMEOUT);
+	debug("%s() TX want len %d, got len %d, rc %d\n",
+	      __func__, length, gotlen, rc);
+	return rc;
+}
+
+/*
+ * mcs7830_recv() - network interface's recv callback
+ * @eth:	network device to receive frames from
+ * Return: zero upon success, negative upon error
+ *
+ * this routine checks for available ethernet frames that the network
+ * interface might have received, and notifies the network stack
+ */
+static int mcs7830_recv(struct eth_device *eth)
+{
+	struct ueth_data *dev;
+	ALLOC_CACHE_ALIGN_BUFFER(uint8_t, buf, MCS7830_RX_URB_SIZE);
+	int rc, wantlen, gotlen;
+	uint8_t sts;
+
+	debug("%s()\n", __func__);
+	dev = eth->priv;
+
+	/* fetch input data from the adapter */
+	wantlen = MCS7830_RX_URB_SIZE;
+	rc = usb_bulk_msg(dev->pusb_dev,
+			  usb_rcvbulkpipe(dev->pusb_dev, dev->ep_in),
+			  &buf[0], wantlen, &gotlen,
+			  USBCALL_TIMEOUT);
+	debug("%s() RX want len %d, got len %d, rc %d\n",
+	      __func__, wantlen, gotlen, rc);
+	if (rc != 0) {
+		error("RX: failed to receive\n");
+		return rc;
+	}
+	if (gotlen > wantlen) {
+		error("RX: got too many bytes (%d)\n", gotlen);
+		return -EIO;
+	}
+
+	/*
+	 * the bulk message that we received from USB contains exactly
+	 * one ethernet frame and a trailing status byte
+	 */
+	if (gotlen < sizeof(sts))
+		return -EIO;
+	gotlen -= sizeof(sts);
+	sts = buf[gotlen];
+
+	if (sts == STAT_RX_FRAME_CORRECT) {
+		debug("%s() got a frame, len=%d\n", __func__, gotlen);
+		NetReceive(buf, gotlen);
+		return 0;
+	}
+
+	debug("RX: frame error (sts 0x%02X, %s %s %s %s %s)\n",
+	      sts,
+	      (sts & STAT_RX_LARGE_FRAME) ? "large" : "-",
+	      (sts & STAT_RX_LENGTH_ERROR) ?  "length" : "-",
+	      (sts & STAT_RX_SHORT_FRAME) ? "short" : "-",
+	      (sts & STAT_RX_CRC_ERROR) ? "crc" : "-",
+	      (sts & STAT_RX_ALIGNMENT_ERROR) ?  "align" : "-");
+	return -EIO;
+}
+
+/*
+ * mcs7830_halt() - network interface's halt callback
+ * @eth:	network device to cease operation of
+ * Return: none
+ *
+ * this routine is supposed to undo the effect of previous initialization and
+ * ethernet frames exchange; in this implementation it's a NOP
+ */
+static void mcs7830_halt(struct eth_device *eth)
+{
+	debug("%s()\n", __func__);
+}
+
+/*
+ * mcs7830_iface_idx - index of detected network interfaces
+ *
+ * this counter keeps track of identified supported interfaces,
+ * to assign unique names as more interfaces are found
+ */
+static int mcs7830_iface_idx;
+
+/*
+ * mcs7830_eth_before_probe() - network driver's before_probe callback
+ * Return: none
+ *
+ * this routine initializes driver's internal data in preparation of
+ * subsequent probe callbacks
+ */
+void mcs7830_eth_before_probe(void)
+{
+	mcs7830_iface_idx = 0;
+}
+
+/*
+ * struct mcs7830_dongle - description of a supported Moschip ethernet dongle
+ * @vendor:	16bit USB vendor identification
+ * @product:	16bit USB product identification
+ *
+ * this structure describes a supported USB ethernet dongle by means of the
+ * vendor and product codes found during USB enumeration; no flags are held
+ * here since all supported dongles have identical behaviour, and required
+ * fixups get determined at runtime, such that no manual configuration is
+ * needed
+ */
+struct mcs7830_dongle {
+	uint16_t vendor;
+	uint16_t product;
+};
+
+/*
+ * mcs7830_dongles - the list of supported Moschip based USB ethernet dongles
+ */
+static const struct mcs7830_dongle const mcs7830_dongles[] = {
+	{ 0x9710, 0x7832, },	/* Moschip 7832 */
+	{ 0x9710, 0x7830, },	/* Moschip 7830 */
+	{ 0x9710, 0x7730, },	/* Moschip 7730 */
+	{ 0x0df6, 0x0021, },	/* Sitecom LN 30 */
+};
+
+/*
+ * mcs7830_eth_probe() - network driver's probe callback
+ * @dev:	detected USB device to check
+ * @ifnum:	detected USB interface to check
+ * @ss:		USB ethernet data structure to fill in upon match
+ * Return: #1 upon match, #0 upon mismatch or error
+ *
+ * this routine checks whether the found USB device is supported by
+ * this ethernet driver, and upon match fills in the USB ethernet
+ * data structure which later is passed to the get_info callback
+ */
+int mcs7830_eth_probe(struct usb_device *dev, unsigned int ifnum,
+		      struct ueth_data *ss)
+{
+	struct usb_interface *iface;
+	struct usb_interface_descriptor *iface_desc;
+	int i;
+	struct mcs7830_private *priv;
+	int ep_in_found, ep_out_found, ep_intr_found;
+
+	debug("%s()\n", __func__);
+
+	/* iterate the list of supported dongles */
+	iface = &dev->config.if_desc[ifnum];
+	iface_desc = &iface->desc;
+	for (i = 0; i < ARRAY_SIZE(mcs7830_dongles); i++) {
+		if (dev->descriptor.idVendor == mcs7830_dongles[i].vendor &&
+		    dev->descriptor.idProduct == mcs7830_dongles[i].product)
+			break;
+	}
+	if (i == ARRAY_SIZE(mcs7830_dongles))
+		return 0;
+	debug("detected USB ethernet device: %04X:%04X\n",
+	      dev->descriptor.idVendor, dev->descriptor.idProduct);
+
+	/* fill in driver private data */
+	priv = calloc(1, sizeof(*priv));
+	if (!priv)
+		return 0;
+
+	/* fill in the ueth_data structure, attach private data */
+	memset(ss, 0, sizeof(*ss));
+	ss->ifnum = ifnum;
+	ss->pusb_dev = dev;
+	ss->subclass = iface_desc->bInterfaceSubClass;
+	ss->protocol = iface_desc->bInterfaceProtocol;
+	ss->dev_priv = priv;
+
+	/*
+	 * a minimum of three endpoints is expected: in (bulk),
+	 * out (bulk), and interrupt; ignore all others
+	 */
+	ep_in_found = ep_out_found = ep_intr_found = 0;
+	for (i = 0; i < iface_desc->bNumEndpoints; i++) {
+		uint8_t eptype, epaddr;
+		bool is_input;
+
+		eptype = iface->ep_desc[i].bmAttributes;
+		eptype &= USB_ENDPOINT_XFERTYPE_MASK;
+
+		epaddr = iface->ep_desc[i].bEndpointAddress;
+		is_input = epaddr & USB_DIR_IN;
+		epaddr &= USB_ENDPOINT_NUMBER_MASK;
+
+		if (eptype == USB_ENDPOINT_XFER_BULK) {
+			if (is_input && !ep_in_found) {
+				ss->ep_in = epaddr;
+				ep_in_found++;
+			}
+			if (!is_input && !ep_out_found) {
+				ss->ep_out = epaddr;
+				ep_out_found++;
+			}
+		}
+
+		if (eptype == USB_ENDPOINT_XFER_INT) {
+			if (is_input && !ep_intr_found) {
+				ss->ep_int = epaddr;
+				ss->irqinterval = iface->ep_desc[i].bInterval;
+				ep_intr_found++;
+			}
+		}
+	}
+	debug("endpoints: in %d, out %d, intr %d\n",
+	      ss->ep_in, ss->ep_out, ss->ep_int);
+
+	/* apply basic sanity checks */
+	if (usb_set_interface(dev, iface_desc->bInterfaceNumber, 0) ||
+	    !ss->ep_in || !ss->ep_out || !ss->ep_int) {
+		debug("device probe incomplete\n");
+		return 0;
+	}
+
+	dev->privptr = ss;
+	return 1;
+}
+
+/*
+ * mcs7830_eth_get_info() - network driver's get_info callback
+ * @dev:	detected USB device
+ * @ss:		USB ethernet data structure filled in at probe()
+ * @eth:	ethernet interface data structure to fill in
+ * Return: #1 upon success, #0 upon error
+ *
+ * this routine registers the mandatory init(), send(), recv(), and
+ * halt() callbacks with the ethernet interface, can register the
+ * optional write_hwaddr() callback with the ethernet interface,
+ * and initiates configuration of the interface such that subsequent
+ * calls to those callbacks results in network communication
+ */
+int mcs7830_eth_get_info(struct usb_device *dev, struct ueth_data *ss,
+			 struct eth_device *eth)
+{
+	debug("%s()\n", __func__);
+	if (!eth) {
+		debug("%s: missing parameter.\n", __func__);
+		return 0;
+	}
+
+	snprintf(eth->name, sizeof(eth->name), "%s%d",
+		 MCS7830_BASE_NAME, mcs7830_iface_idx++);
+	eth->init = mcs7830_init;
+	eth->send = mcs7830_send;
+	eth->recv = mcs7830_recv;
+	eth->halt = mcs7830_halt;
+	eth->write_hwaddr = mcs7830_write_mac;
+	eth->priv = ss;
+
+	if (mcs7830_basic_reset(ss))
+		return 0;
+
+	if (mcs7830_read_mac(eth))
+		return 0;
+	debug("MAC %pM\n", eth->enetaddr);
+
+	return 1;
+}
diff --git a/drivers/usb/eth/smsc95xx.c b/drivers/usb/eth/smsc95xx.c
index 15fd9a9f78..7bf0a34078 100644
--- a/drivers/usb/eth/smsc95xx.c
+++ b/drivers/usb/eth/smsc95xx.c
@@ -14,6 +14,12 @@
 
 /* SMSC LAN95xx based USB 2.0 Ethernet Devices */
 
+/* LED defines */
+#define LED_GPIO_CFG			(0x24)
+#define LED_GPIO_CFG_SPD_LED		(0x01000000)
+#define LED_GPIO_CFG_LNK_LED		(0x00100000)
+#define LED_GPIO_CFG_FDX_LED		(0x00010000)
+
 /* Tx command words */
 #define TX_CMD_A_FIRST_SEG_		0x00002000
 #define TX_CMD_A_LAST_SEG_		0x00001000
@@ -591,6 +597,14 @@ static int smsc95xx_init(struct eth_device *eth, bd_t *bd)
 		return ret;
 	debug("ID_REV = 0x%08x\n", read_buf);
 
+	/* Configure GPIO pins as LED outputs */
+	write_buf = LED_GPIO_CFG_SPD_LED | LED_GPIO_CFG_LNK_LED |
+		LED_GPIO_CFG_FDX_LED;
+	ret = smsc95xx_write_reg(dev, LED_GPIO_CFG, write_buf);
+	if (ret < 0)
+		return ret;
+	debug("LED_GPIO_CFG set\n");
+
 	/* Init Tx */
 	write_buf = 0;
 	ret = smsc95xx_write_reg(dev, FLOW, write_buf);
diff --git a/drivers/usb/eth/usb_ether.c b/drivers/usb/eth/usb_ether.c
index 2c4126be36..1dda54c2f1 100644
--- a/drivers/usb/eth/usb_ether.c
+++ b/drivers/usb/eth/usb_ether.c
@@ -30,6 +30,13 @@ static const struct usb_eth_prob_dev prob_dev[] = {
 		.get_info = asix_eth_get_info,
 	},
 #endif
+#ifdef CONFIG_USB_ETHER_MCS7830
+	{
+		.before_probe = mcs7830_eth_before_probe,
+		.probe = mcs7830_eth_probe,
+		.get_info = mcs7830_eth_get_info,
+	},
+#endif
 #ifdef CONFIG_USB_ETHER_SMSC95XX
 	{
 		.before_probe = smsc95xx_eth_before_probe,
diff --git a/drivers/usb/gadget/Makefile b/drivers/usb/gadget/Makefile
index 1590c4a750..804a2bd412 100644
--- a/drivers/usb/gadget/Makefile
+++ b/drivers/usb/gadget/Makefile
@@ -5,58 +5,33 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	:= $(obj)libusb_gadget.o
-
-# if defined(CONFIG_USB_GADGET) || defined(CONFIG_USB_ETHER)
-#   Everytime you forget how crufty makefiles can get things like
-#   this remind you...
-ifneq (,$(CONFIG_USB_GADGET)$(CONFIG_USB_ETHER))
-COBJS-y += epautoconf.o config.o usbstring.o
-endif
+obj-$(CONFIG_USB_GADGET) += epautoconf.o config.o usbstring.o
+obj-$(CONFIG_USB_ETHER) += epautoconf.o config.o usbstring.o
 
 # new USB gadget layer dependencies
 ifdef CONFIG_USB_GADGET
-COBJS-$(CONFIG_USB_GADGET_ATMEL_USBA) += atmel_usba_udc.o
-COBJS-$(CONFIG_USB_GADGET_S3C_UDC_OTG) += s3c_udc_otg.o
-COBJS-$(CONFIG_USB_GADGET_FOTG210) += fotg210.o
-COBJS-$(CONFIG_USBDOWNLOAD_GADGET) += g_dnl.o
-COBJS-$(CONFIG_DFU_FUNCTION) += f_dfu.o
-COBJS-$(CONFIG_USB_GADGET_MASS_STORAGE) += f_mass_storage.o
+obj-$(CONFIG_USB_GADGET_ATMEL_USBA) += atmel_usba_udc.o
+obj-$(CONFIG_USB_GADGET_S3C_UDC_OTG) += s3c_udc_otg.o
+obj-$(CONFIG_USB_GADGET_FOTG210) += fotg210.o
+obj-$(CONFIG_THOR_FUNCTION) += f_thor.o
+obj-$(CONFIG_USBDOWNLOAD_GADGET) += g_dnl.o
+obj-$(CONFIG_DFU_FUNCTION) += f_dfu.o
+obj-$(CONFIG_USB_GADGET_MASS_STORAGE) += f_mass_storage.o
 endif
 ifdef CONFIG_USB_ETHER
-COBJS-y += ether.o
-COBJS-$(CONFIG_USB_ETH_RNDIS) += rndis.o
-COBJS-$(CONFIG_MV_UDC)	+= mv_udc.o
-COBJS-$(CONFIG_CPU_PXA25X) += pxa25x_udc.o
+obj-y += ether.o
+obj-$(CONFIG_USB_ETH_RNDIS) += rndis.o
+obj-$(CONFIG_CI_UDC)	+= ci_udc.o
+obj-$(CONFIG_CPU_PXA25X) += pxa25x_udc.o
 else
 # Devices not related to the new gadget layer depend on CONFIG_USB_DEVICE
 ifdef CONFIG_USB_DEVICE
-COBJS-y += core.o
-COBJS-y += ep0.o
-COBJS-$(CONFIG_DW_UDC) += designware_udc.o
-COBJS-$(CONFIG_OMAP1510) += omap1510_udc.o
-COBJS-$(CONFIG_OMAP1610) += omap1510_udc.o
-COBJS-$(CONFIG_MPC885_FAMILY) += mpc8xx_udc.o
-COBJS-$(CONFIG_CPU_PXA27X) += pxa27x_udc.o
+obj-y += core.o
+obj-y += ep0.o
+obj-$(CONFIG_DW_UDC) += designware_udc.o
+obj-$(CONFIG_OMAP1510) += omap1510_udc.o
+obj-$(CONFIG_OMAP1610) += omap1510_udc.o
+obj-$(CONFIG_MPC885_FAMILY) += mpc8xx_udc.o
+obj-$(CONFIG_CPU_PXA27X) += pxa27x_udc.o
 endif
 endif
-
-COBJS	:= $(COBJS-y)
-SRCS	:= $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-
-all:	$(LIB)
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
diff --git a/drivers/usb/gadget/ci_udc.c b/drivers/usb/gadget/ci_udc.c
new file mode 100644
index 0000000000..14b1e9b8bf
--- /dev/null
+++ b/drivers/usb/gadget/ci_udc.c
@@ -0,0 +1,737 @@
+/*
+ * Copyright 2011, Marvell Semiconductor Inc.
+ * Lei Wen <leiwen@marvell.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ *
+ * Back ported to the 8xx platform (from the 8260 platform) by
+ * Murray.Jensen@cmst.csiro.au, 27-Jan-01.
+ */
+
+#include <common.h>
+#include <command.h>
+#include <config.h>
+#include <net.h>
+#include <malloc.h>
+#include <asm/byteorder.h>
+#include <asm/errno.h>
+#include <asm/io.h>
+#include <asm/unaligned.h>
+#include <linux/types.h>
+#include <linux/usb/ch9.h>
+#include <linux/usb/gadget.h>
+#include <usb/ci_udc.h>
+#include "../host/ehci.h"
+#include "ci_udc.h"
+
+/*
+ * Check if the system has too long cachelines. If the cachelines are
+ * longer then 128b, the driver will not be able flush/invalidate data
+ * cache over separate QH entries. We use 128b because one QH entry is
+ * 64b long and there are always two QH list entries for each endpoint.
+ */
+#if ARCH_DMA_MINALIGN > 128
+#error This driver can not work on systems with caches longer than 128b
+#endif
+
+#ifndef DEBUG
+#define DBG(x...) do {} while (0)
+#else
+#define DBG(x...) printf(x)
+static const char *reqname(unsigned r)
+{
+	switch (r) {
+	case USB_REQ_GET_STATUS: return "GET_STATUS";
+	case USB_REQ_CLEAR_FEATURE: return "CLEAR_FEATURE";
+	case USB_REQ_SET_FEATURE: return "SET_FEATURE";
+	case USB_REQ_SET_ADDRESS: return "SET_ADDRESS";
+	case USB_REQ_GET_DESCRIPTOR: return "GET_DESCRIPTOR";
+	case USB_REQ_SET_DESCRIPTOR: return "SET_DESCRIPTOR";
+	case USB_REQ_GET_CONFIGURATION: return "GET_CONFIGURATION";
+	case USB_REQ_SET_CONFIGURATION: return "SET_CONFIGURATION";
+	case USB_REQ_GET_INTERFACE: return "GET_INTERFACE";
+	case USB_REQ_SET_INTERFACE: return "SET_INTERFACE";
+	default: return "*UNKNOWN*";
+	}
+}
+#endif
+
+static struct usb_endpoint_descriptor ep0_out_desc = {
+	.bLength = sizeof(struct usb_endpoint_descriptor),
+	.bDescriptorType = USB_DT_ENDPOINT,
+	.bEndpointAddress = 0,
+	.bmAttributes =	USB_ENDPOINT_XFER_CONTROL,
+};
+
+static struct usb_endpoint_descriptor ep0_in_desc = {
+	.bLength = sizeof(struct usb_endpoint_descriptor),
+	.bDescriptorType = USB_DT_ENDPOINT,
+	.bEndpointAddress = USB_DIR_IN,
+	.bmAttributes =	USB_ENDPOINT_XFER_CONTROL,
+};
+
+static int ci_pullup(struct usb_gadget *gadget, int is_on);
+static int ci_ep_enable(struct usb_ep *ep,
+		const struct usb_endpoint_descriptor *desc);
+static int ci_ep_disable(struct usb_ep *ep);
+static int ci_ep_queue(struct usb_ep *ep,
+		struct usb_request *req, gfp_t gfp_flags);
+static struct usb_request *
+ci_ep_alloc_request(struct usb_ep *ep, unsigned int gfp_flags);
+static void ci_ep_free_request(struct usb_ep *ep, struct usb_request *_req);
+
+static struct usb_gadget_ops ci_udc_ops = {
+	.pullup = ci_pullup,
+};
+
+static struct usb_ep_ops ci_ep_ops = {
+	.enable         = ci_ep_enable,
+	.disable        = ci_ep_disable,
+	.queue          = ci_ep_queue,
+	.alloc_request  = ci_ep_alloc_request,
+	.free_request   = ci_ep_free_request,
+};
+
+/* Init values for USB endpoints. */
+static const struct usb_ep ci_ep_init[2] = {
+	[0] = {	/* EP 0 */
+		.maxpacket	= 64,
+		.name		= "ep0",
+		.ops		= &ci_ep_ops,
+	},
+	[1] = {	/* EP 1..n */
+		.maxpacket	= 512,
+		.name		= "ep-",
+		.ops		= &ci_ep_ops,
+	},
+};
+
+static struct ci_drv controller = {
+	.gadget	= {
+		.name	= "ci_udc",
+		.ops	= &ci_udc_ops,
+		.is_dualspeed = 1,
+	},
+};
+
+/**
+ * ci_get_qh() - return queue head for endpoint
+ * @ep_num:	Endpoint number
+ * @dir_in:	Direction of the endpoint (IN = 1, OUT = 0)
+ *
+ * This function returns the QH associated with particular endpoint
+ * and it's direction.
+ */
+static struct ept_queue_head *ci_get_qh(int ep_num, int dir_in)
+{
+	return &controller.epts[(ep_num * 2) + dir_in];
+}
+
+/**
+ * ci_get_qtd() - return queue item for endpoint
+ * @ep_num:	Endpoint number
+ * @dir_in:	Direction of the endpoint (IN = 1, OUT = 0)
+ *
+ * This function returns the QH associated with particular endpoint
+ * and it's direction.
+ */
+static struct ept_queue_item *ci_get_qtd(int ep_num, int dir_in)
+{
+	return controller.items[(ep_num * 2) + dir_in];
+}
+
+/**
+ * ci_flush_qh - flush cache over queue head
+ * @ep_num:	Endpoint number
+ *
+ * This function flushes cache over QH for particular endpoint.
+ */
+static void ci_flush_qh(int ep_num)
+{
+	struct ept_queue_head *head = ci_get_qh(ep_num, 0);
+	const uint32_t start = (uint32_t)head;
+	const uint32_t end = start + 2 * sizeof(*head);
+
+	flush_dcache_range(start, end);
+}
+
+/**
+ * ci_invalidate_qh - invalidate cache over queue head
+ * @ep_num:	Endpoint number
+ *
+ * This function invalidates cache over QH for particular endpoint.
+ */
+static void ci_invalidate_qh(int ep_num)
+{
+	struct ept_queue_head *head = ci_get_qh(ep_num, 0);
+	uint32_t start = (uint32_t)head;
+	uint32_t end = start + 2 * sizeof(*head);
+
+	invalidate_dcache_range(start, end);
+}
+
+/**
+ * ci_flush_qtd - flush cache over queue item
+ * @ep_num:	Endpoint number
+ *
+ * This function flushes cache over qTD pair for particular endpoint.
+ */
+static void ci_flush_qtd(int ep_num)
+{
+	struct ept_queue_item *item = ci_get_qtd(ep_num, 0);
+	const uint32_t start = (uint32_t)item;
+	const uint32_t end_raw = start + 2 * sizeof(*item);
+	const uint32_t end = roundup(end_raw, ARCH_DMA_MINALIGN);
+
+	flush_dcache_range(start, end);
+}
+
+/**
+ * ci_invalidate_qtd - invalidate cache over queue item
+ * @ep_num:	Endpoint number
+ *
+ * This function invalidates cache over qTD pair for particular endpoint.
+ */
+static void ci_invalidate_qtd(int ep_num)
+{
+	struct ept_queue_item *item = ci_get_qtd(ep_num, 0);
+	const uint32_t start = (uint32_t)item;
+	const uint32_t end_raw = start + 2 * sizeof(*item);
+	const uint32_t end = roundup(end_raw, ARCH_DMA_MINALIGN);
+
+	invalidate_dcache_range(start, end);
+}
+
+static struct usb_request *
+ci_ep_alloc_request(struct usb_ep *ep, unsigned int gfp_flags)
+{
+	struct ci_ep *ci_ep = container_of(ep, struct ci_ep, ep);
+	return &ci_ep->req;
+}
+
+static void ci_ep_free_request(struct usb_ep *ep, struct usb_request *_req)
+{
+	return;
+}
+
+static void ep_enable(int num, int in, int maxpacket)
+{
+	struct ci_udc *udc = (struct ci_udc *)controller.ctrl->hcor;
+	unsigned n;
+
+	n = readl(&udc->epctrl[num]);
+	if (in)
+		n |= (CTRL_TXE | CTRL_TXR | CTRL_TXT_BULK);
+	else
+		n |= (CTRL_RXE | CTRL_RXR | CTRL_RXT_BULK);
+
+	if (num != 0) {
+		struct ept_queue_head *head = ci_get_qh(num, in);
+
+		head->config = CONFIG_MAX_PKT(maxpacket) | CONFIG_ZLT;
+		ci_flush_qh(num);
+	}
+	writel(n, &udc->epctrl[num]);
+}
+
+static int ci_ep_enable(struct usb_ep *ep,
+		const struct usb_endpoint_descriptor *desc)
+{
+	struct ci_ep *ci_ep = container_of(ep, struct ci_ep, ep);
+	int num, in;
+	num = desc->bEndpointAddress & USB_ENDPOINT_NUMBER_MASK;
+	in = (desc->bEndpointAddress & USB_DIR_IN) != 0;
+	ci_ep->desc = desc;
+
+	if (num) {
+		int max = get_unaligned_le16(&desc->wMaxPacketSize);
+
+		if ((max > 64) && (controller.gadget.speed == USB_SPEED_FULL))
+			max = 64;
+		if (ep->maxpacket != max) {
+			DBG("%s: from %d to %d\n", __func__,
+			    ep->maxpacket, max);
+			ep->maxpacket = max;
+		}
+	}
+	ep_enable(num, in, ep->maxpacket);
+	DBG("%s: num=%d maxpacket=%d\n", __func__, num, ep->maxpacket);
+	return 0;
+}
+
+static int ci_ep_disable(struct usb_ep *ep)
+{
+	struct ci_ep *ci_ep = container_of(ep, struct ci_ep, ep);
+
+	ci_ep->desc = NULL;
+	return 0;
+}
+
+static int ci_bounce(struct ci_ep *ep, int in)
+{
+	uint32_t addr = (uint32_t)ep->req.buf;
+	uint32_t ba;
+
+	/* Input buffer address is not aligned. */
+	if (addr & (ARCH_DMA_MINALIGN - 1))
+		goto align;
+
+	/* Input buffer length is not aligned. */
+	if (ep->req.length & (ARCH_DMA_MINALIGN - 1))
+		goto align;
+
+	/* The buffer is well aligned, only flush cache. */
+	ep->b_len = ep->req.length;
+	ep->b_buf = ep->req.buf;
+	goto flush;
+
+align:
+	/* Use internal buffer for small payloads. */
+	if (ep->req.length <= 64) {
+		ep->b_len = 64;
+		ep->b_buf = ep->b_fast;
+	} else {
+		ep->b_len = roundup(ep->req.length, ARCH_DMA_MINALIGN);
+		ep->b_buf = memalign(ARCH_DMA_MINALIGN, ep->b_len);
+		if (!ep->b_buf)
+			return -ENOMEM;
+	}
+	if (in)
+		memcpy(ep->b_buf, ep->req.buf, ep->req.length);
+
+flush:
+	ba = (uint32_t)ep->b_buf;
+	flush_dcache_range(ba, ba + ep->b_len);
+
+	return 0;
+}
+
+static void ci_debounce(struct ci_ep *ep, int in)
+{
+	uint32_t addr = (uint32_t)ep->req.buf;
+	uint32_t ba = (uint32_t)ep->b_buf;
+
+	if (in) {
+		if (addr == ba)
+			return;		/* not a bounce */
+		goto free;
+	}
+	invalidate_dcache_range(ba, ba + ep->b_len);
+
+	if (addr == ba)
+		return;		/* not a bounce */
+
+	memcpy(ep->req.buf, ep->b_buf, ep->req.length);
+free:
+	/* Large payloads use allocated buffer, free it. */
+	if (ep->b_buf != ep->b_fast)
+		free(ep->b_buf);
+}
+
+static int ci_ep_queue(struct usb_ep *ep,
+		struct usb_request *req, gfp_t gfp_flags)
+{
+	struct ci_ep *ci_ep = container_of(ep, struct ci_ep, ep);
+	struct ci_udc *udc = (struct ci_udc *)controller.ctrl->hcor;
+	struct ept_queue_item *item;
+	struct ept_queue_head *head;
+	int bit, num, len, in, ret;
+	num = ci_ep->desc->bEndpointAddress & USB_ENDPOINT_NUMBER_MASK;
+	in = (ci_ep->desc->bEndpointAddress & USB_DIR_IN) != 0;
+	item = ci_get_qtd(num, in);
+	head = ci_get_qh(num, in);
+	len = req->length;
+
+	ret = ci_bounce(ci_ep, in);
+	if (ret)
+		return ret;
+
+	item->next = TERMINATE;
+	item->info = INFO_BYTES(len) | INFO_IOC | INFO_ACTIVE;
+	item->page0 = (uint32_t)ci_ep->b_buf;
+	item->page1 = ((uint32_t)ci_ep->b_buf & 0xfffff000) + 0x1000;
+	ci_flush_qtd(num);
+
+	head->next = (unsigned) item;
+	head->info = 0;
+
+	DBG("ept%d %s queue len %x, buffer %p\n",
+	    num, in ? "in" : "out", len, ci_ep->b_buf);
+	ci_flush_qh(num);
+
+	if (in)
+		bit = EPT_TX(num);
+	else
+		bit = EPT_RX(num);
+
+	writel(bit, &udc->epprime);
+
+	return 0;
+}
+
+static void handle_ep_complete(struct ci_ep *ep)
+{
+	struct ept_queue_item *item;
+	int num, in, len;
+	num = ep->desc->bEndpointAddress & USB_ENDPOINT_NUMBER_MASK;
+	in = (ep->desc->bEndpointAddress & USB_DIR_IN) != 0;
+	if (num == 0)
+		ep->desc = &ep0_out_desc;
+	item = ci_get_qtd(num, in);
+	ci_invalidate_qtd(num);
+
+	if (item->info & 0xff)
+		printf("EP%d/%s FAIL info=%x pg0=%x\n",
+		       num, in ? "in" : "out", item->info, item->page0);
+
+	len = (item->info >> 16) & 0x7fff;
+	ep->req.length -= len;
+	ci_debounce(ep, in);
+
+	DBG("ept%d %s complete %x\n",
+			num, in ? "in" : "out", len);
+	ep->req.complete(&ep->ep, &ep->req);
+	if (num == 0) {
+		ep->req.length = 0;
+		usb_ep_queue(&ep->ep, &ep->req, 0);
+		ep->desc = &ep0_in_desc;
+	}
+}
+
+#define SETUP(type, request) (((type) << 8) | (request))
+
+static void handle_setup(void)
+{
+	struct usb_request *req = &controller.ep[0].req;
+	struct ci_udc *udc = (struct ci_udc *)controller.ctrl->hcor;
+	struct ept_queue_head *head;
+	struct usb_ctrlrequest r;
+	int status = 0;
+	int num, in, _num, _in, i;
+	char *buf;
+	head = ci_get_qh(0, 0);	/* EP0 OUT */
+
+	ci_invalidate_qh(0);
+	memcpy(&r, head->setup_data, sizeof(struct usb_ctrlrequest));
+	writel(EPT_RX(0), &udc->epstat);
+	DBG("handle setup %s, %x, %x index %x value %x\n", reqname(r.bRequest),
+	    r.bRequestType, r.bRequest, r.wIndex, r.wValue);
+
+	switch (SETUP(r.bRequestType, r.bRequest)) {
+	case SETUP(USB_RECIP_ENDPOINT, USB_REQ_CLEAR_FEATURE):
+		_num = r.wIndex & 15;
+		_in = !!(r.wIndex & 0x80);
+
+		if ((r.wValue == 0) && (r.wLength == 0)) {
+			req->length = 0;
+			for (i = 0; i < NUM_ENDPOINTS; i++) {
+				struct ci_ep *ep = &controller.ep[i];
+
+				if (!ep->desc)
+					continue;
+				num = ep->desc->bEndpointAddress
+						& USB_ENDPOINT_NUMBER_MASK;
+				in = (ep->desc->bEndpointAddress
+						& USB_DIR_IN) != 0;
+				if ((num == _num) && (in == _in)) {
+					ep_enable(num, in, ep->ep.maxpacket);
+					usb_ep_queue(controller.gadget.ep0,
+							req, 0);
+					break;
+				}
+			}
+		}
+		return;
+
+	case SETUP(USB_RECIP_DEVICE, USB_REQ_SET_ADDRESS):
+		/*
+		 * write address delayed (will take effect
+		 * after the next IN txn)
+		 */
+		writel((r.wValue << 25) | (1 << 24), &udc->devaddr);
+		req->length = 0;
+		usb_ep_queue(controller.gadget.ep0, req, 0);
+		return;
+
+	case SETUP(USB_DIR_IN | USB_RECIP_DEVICE, USB_REQ_GET_STATUS):
+		req->length = 2;
+		buf = (char *)req->buf;
+		buf[0] = 1 << USB_DEVICE_SELF_POWERED;
+		buf[1] = 0;
+		usb_ep_queue(controller.gadget.ep0, req, 0);
+		return;
+	}
+	/* pass request up to the gadget driver */
+	if (controller.driver)
+		status = controller.driver->setup(&controller.gadget, &r);
+	else
+		status = -ENODEV;
+
+	if (!status)
+		return;
+	DBG("STALL reqname %s type %x value %x, index %x\n",
+	    reqname(r.bRequest), r.bRequestType, r.wValue, r.wIndex);
+	writel((1<<16) | (1 << 0), &udc->epctrl[0]);
+}
+
+static void stop_activity(void)
+{
+	int i, num, in;
+	struct ept_queue_head *head;
+	struct ci_udc *udc = (struct ci_udc *)controller.ctrl->hcor;
+	writel(readl(&udc->epcomp), &udc->epcomp);
+	writel(readl(&udc->epstat), &udc->epstat);
+	writel(0xffffffff, &udc->epflush);
+
+	/* error out any pending reqs */
+	for (i = 0; i < NUM_ENDPOINTS; i++) {
+		if (i != 0)
+			writel(0, &udc->epctrl[i]);
+		if (controller.ep[i].desc) {
+			num = controller.ep[i].desc->bEndpointAddress
+				& USB_ENDPOINT_NUMBER_MASK;
+			in = (controller.ep[i].desc->bEndpointAddress
+				& USB_DIR_IN) != 0;
+			head = ci_get_qh(num, in);
+			head->info = INFO_ACTIVE;
+			ci_flush_qh(num);
+		}
+	}
+}
+
+void udc_irq(void)
+{
+	struct ci_udc *udc = (struct ci_udc *)controller.ctrl->hcor;
+	unsigned n = readl(&udc->usbsts);
+	writel(n, &udc->usbsts);
+	int bit, i, num, in;
+
+	n &= (STS_SLI | STS_URI | STS_PCI | STS_UI | STS_UEI);
+	if (n == 0)
+		return;
+
+	if (n & STS_URI) {
+		DBG("-- reset --\n");
+		stop_activity();
+	}
+	if (n & STS_SLI)
+		DBG("-- suspend --\n");
+
+	if (n & STS_PCI) {
+		int max = 64;
+		int speed = USB_SPEED_FULL;
+
+		bit = (readl(&udc->portsc) >> 26) & 3;
+		DBG("-- portchange %x %s\n", bit, (bit == 2) ? "High" : "Full");
+		if (bit == 2) {
+			speed = USB_SPEED_HIGH;
+			max = 512;
+		}
+		controller.gadget.speed = speed;
+		for (i = 1; i < NUM_ENDPOINTS; i++) {
+			if (controller.ep[i].ep.maxpacket > max)
+				controller.ep[i].ep.maxpacket = max;
+		}
+	}
+
+	if (n & STS_UEI)
+		printf("<UEI %x>\n", readl(&udc->epcomp));
+
+	if ((n & STS_UI) || (n & STS_UEI)) {
+		n = readl(&udc->epstat);
+		if (n & EPT_RX(0))
+			handle_setup();
+
+		n = readl(&udc->epcomp);
+		if (n != 0)
+			writel(n, &udc->epcomp);
+
+		for (i = 0; i < NUM_ENDPOINTS && n; i++) {
+			if (controller.ep[i].desc) {
+				num = controller.ep[i].desc->bEndpointAddress
+					& USB_ENDPOINT_NUMBER_MASK;
+				in = (controller.ep[i].desc->bEndpointAddress
+						& USB_DIR_IN) != 0;
+				bit = (in) ? EPT_TX(num) : EPT_RX(num);
+				if (n & bit)
+					handle_ep_complete(&controller.ep[i]);
+			}
+		}
+	}
+}
+
+int usb_gadget_handle_interrupts(void)
+{
+	u32 value;
+	struct ci_udc *udc = (struct ci_udc *)controller.ctrl->hcor;
+
+	value = readl(&udc->usbsts);
+	if (value)
+		udc_irq();
+
+	return value;
+}
+
+static int ci_pullup(struct usb_gadget *gadget, int is_on)
+{
+	struct ci_udc *udc = (struct ci_udc *)controller.ctrl->hcor;
+	if (is_on) {
+		/* RESET */
+		writel(USBCMD_ITC(MICRO_8FRAME) | USBCMD_RST, &udc->usbcmd);
+		udelay(200);
+
+		writel((unsigned)controller.epts, &udc->epinitaddr);
+
+		/* select DEVICE mode */
+		writel(USBMODE_DEVICE, &udc->usbmode);
+
+		writel(0xffffffff, &udc->epflush);
+
+		/* Turn on the USB connection by enabling the pullup resistor */
+		writel(USBCMD_ITC(MICRO_8FRAME) | USBCMD_RUN, &udc->usbcmd);
+	} else {
+		stop_activity();
+		writel(USBCMD_FS2, &udc->usbcmd);
+		udelay(800);
+		if (controller.driver)
+			controller.driver->disconnect(gadget);
+	}
+
+	return 0;
+}
+
+void udc_disconnect(void)
+{
+	struct ci_udc *udc = (struct ci_udc *)controller.ctrl->hcor;
+	/* disable pullup */
+	stop_activity();
+	writel(USBCMD_FS2, &udc->usbcmd);
+	udelay(800);
+	if (controller.driver)
+		controller.driver->disconnect(&controller.gadget);
+}
+
+static int ci_udc_probe(void)
+{
+	struct ept_queue_head *head;
+	uint8_t *imem;
+	int i;
+
+	const int num = 2 * NUM_ENDPOINTS;
+
+	const int eplist_min_align = 4096;
+	const int eplist_align = roundup(eplist_min_align, ARCH_DMA_MINALIGN);
+	const int eplist_raw_sz = num * sizeof(struct ept_queue_head);
+	const int eplist_sz = roundup(eplist_raw_sz, ARCH_DMA_MINALIGN);
+
+	const int ilist_align = roundup(ARCH_DMA_MINALIGN, 32);
+	const int ilist_ent_raw_sz = 2 * sizeof(struct ept_queue_item);
+	const int ilist_ent_sz = roundup(ilist_ent_raw_sz, ARCH_DMA_MINALIGN);
+	const int ilist_sz = NUM_ENDPOINTS * ilist_ent_sz;
+
+	/* The QH list must be aligned to 4096 bytes. */
+	controller.epts = memalign(eplist_align, eplist_sz);
+	if (!controller.epts)
+		return -ENOMEM;
+	memset(controller.epts, 0, eplist_sz);
+
+	/*
+	 * Each qTD item must be 32-byte aligned, each qTD touple must be
+	 * cacheline aligned. There are two qTD items for each endpoint and
+	 * only one of them is used for the endpoint at time, so we can group
+	 * them together.
+	 */
+	controller.items_mem = memalign(ilist_align, ilist_sz);
+	if (!controller.items_mem) {
+		free(controller.epts);
+		return -ENOMEM;
+	}
+	memset(controller.items_mem, 0, ilist_sz);
+
+	for (i = 0; i < 2 * NUM_ENDPOINTS; i++) {
+		/*
+		 * Configure QH for each endpoint. The structure of the QH list
+		 * is such that each two subsequent fields, N and N+1 where N is
+		 * even, in the QH list represent QH for one endpoint. The Nth
+		 * entry represents OUT configuration and the N+1th entry does
+		 * represent IN configuration of the endpoint.
+		 */
+		head = controller.epts + i;
+		if (i < 2)
+			head->config = CONFIG_MAX_PKT(EP0_MAX_PACKET_SIZE)
+				| CONFIG_ZLT | CONFIG_IOS;
+		else
+			head->config = CONFIG_MAX_PKT(EP_MAX_PACKET_SIZE)
+				| CONFIG_ZLT;
+		head->next = TERMINATE;
+		head->info = 0;
+
+		imem = controller.items_mem + ((i >> 1) * ilist_ent_sz);
+		if (i & 1)
+			imem += sizeof(struct ept_queue_item);
+
+		controller.items[i] = (struct ept_queue_item *)imem;
+
+		if (i & 1) {
+			ci_flush_qh(i - 1);
+			ci_flush_qtd(i - 1);
+		}
+	}
+
+	INIT_LIST_HEAD(&controller.gadget.ep_list);
+
+	/* Init EP 0 */
+	memcpy(&controller.ep[0].ep, &ci_ep_init[0], sizeof(*ci_ep_init));
+	controller.ep[0].desc = &ep0_in_desc;
+	controller.gadget.ep0 = &controller.ep[0].ep;
+	INIT_LIST_HEAD(&controller.gadget.ep0->ep_list);
+
+	/* Init EP 1..n */
+	for (i = 1; i < NUM_ENDPOINTS; i++) {
+		memcpy(&controller.ep[i].ep, &ci_ep_init[1],
+		       sizeof(*ci_ep_init));
+		list_add_tail(&controller.ep[i].ep.ep_list,
+			      &controller.gadget.ep_list);
+	}
+
+	return 0;
+}
+
+int usb_gadget_register_driver(struct usb_gadget_driver *driver)
+{
+	struct ci_udc *udc;
+	int ret;
+
+	if (!driver)
+		return -EINVAL;
+	if (!driver->bind || !driver->setup || !driver->disconnect)
+		return -EINVAL;
+	if (driver->speed != USB_SPEED_FULL && driver->speed != USB_SPEED_HIGH)
+		return -EINVAL;
+
+	ret = usb_lowlevel_init(0, USB_INIT_DEVICE, (void **)&controller.ctrl);
+	if (ret)
+		return ret;
+
+	ret = ci_udc_probe();
+	if (!ret) {
+		udc = (struct ci_udc *)controller.ctrl->hcor;
+
+		/* select ULPI phy */
+		writel(PTS(PTS_ENABLE) | PFSC, &udc->portsc);
+	}
+
+	ret = driver->bind(&controller.gadget);
+	if (ret) {
+		DBG("driver->bind() returned %d\n", ret);
+		return ret;
+	}
+	controller.driver = driver;
+
+	return 0;
+}
+
+int usb_gadget_unregister_driver(struct usb_gadget_driver *driver)
+{
+	return 0;
+}
diff --git a/drivers/usb/gadget/ci_udc.h b/drivers/usb/gadget/ci_udc.h
new file mode 100644
index 0000000000..42f6ef4ab3
--- /dev/null
+++ b/drivers/usb/gadget/ci_udc.h
@@ -0,0 +1,115 @@
+/*
+ * Copyright 2011, Marvell Semiconductor Inc.
+ *
+ * Licensed under the GPL-2 or later.
+ */
+#ifndef __GADGET__CI_UDC_H__
+#define __GADGET__CI_UDC_H__
+
+#define NUM_ENDPOINTS		6
+
+struct ci_udc {
+#define MICRO_8FRAME	0x8
+#define USBCMD_ITC(x)	((((x) > 0xff) ? 0xff : x) << 16)
+#define USBCMD_FS2	(1 << 15)
+#define USBCMD_RST	(1 << 1)
+#define USBCMD_RUN	(1)
+	u32 usbcmd;		/* 0x140 */
+#define STS_SLI		(1 << 8)
+#define STS_URI		(1 << 6)
+#define STS_PCI		(1 << 2)
+#define STS_UEI		(1 << 1)
+#define STS_UI		(1 << 0)
+	u32 usbsts;		/* 0x144 */
+	u32 pad1[3];
+	u32 devaddr;		/* 0x154 */
+	u32 epinitaddr;		/* 0x158 */
+	u32 pad2[10];
+#define PTS_ENABLE	2
+#define PTS(x)		(((x) & 0x3) << 30)
+#define PFSC		(1 << 24)
+	u32 portsc;		/* 0x184 */
+	u32 pad3[8];
+#define USBMODE_DEVICE	2
+	u32 usbmode;		/* 0x1a8 */
+	u32 epstat;		/* 0x1ac */
+#define EPT_TX(x)	(1 << (((x) & 0xffff) + 16))
+#define EPT_RX(x)	(1 << ((x) & 0xffff))
+	u32 epprime;		/* 0x1b0 */
+	u32 epflush;		/* 0x1b4 */
+	u32 pad4;
+	u32 epcomp;		/* 0x1bc */
+#define CTRL_TXE	(1 << 23)
+#define CTRL_TXR	(1 << 22)
+#define CTRL_RXE	(1 << 7)
+#define CTRL_RXR	(1 << 6)
+#define CTRL_TXT_BULK	(2 << 18)
+#define CTRL_RXT_BULK	(2 << 2)
+	u32 epctrl[16];		/* 0x1c0 */
+};
+
+struct ci_ep {
+	struct usb_ep ep;
+	struct list_head queue;
+	const struct usb_endpoint_descriptor *desc;
+
+	struct usb_request req;
+	uint8_t *b_buf;
+	uint32_t b_len;
+	uint8_t b_fast[64] __aligned(ARCH_DMA_MINALIGN);
+};
+
+struct ci_drv {
+	struct usb_gadget		gadget;
+	struct usb_gadget_driver	*driver;
+	struct ehci_ctrl		*ctrl;
+	struct ept_queue_head		*epts;
+	struct ept_queue_item		*items[2 * NUM_ENDPOINTS];
+	uint8_t				*items_mem;
+	struct ci_ep			ep[NUM_ENDPOINTS];
+};
+
+struct ept_queue_head {
+	unsigned config;
+	unsigned current;	/* read-only */
+
+	unsigned next;
+	unsigned info;
+	unsigned page0;
+	unsigned page1;
+	unsigned page2;
+	unsigned page3;
+	unsigned page4;
+	unsigned reserved_0;
+
+	unsigned char setup_data[8];
+
+	unsigned reserved_1;
+	unsigned reserved_2;
+	unsigned reserved_3;
+	unsigned reserved_4;
+};
+
+#define CONFIG_MAX_PKT(n)	((n) << 16)
+#define CONFIG_ZLT		(1 << 29)	/* stop on zero-len xfer */
+#define CONFIG_IOS		(1 << 15)	/* IRQ on setup */
+
+struct ept_queue_item {
+	unsigned next;
+	unsigned info;
+	unsigned page0;
+	unsigned page1;
+	unsigned page2;
+	unsigned page3;
+	unsigned page4;
+	unsigned reserved;
+};
+
+#define TERMINATE 1
+#define INFO_BYTES(n)		((n) << 16)
+#define INFO_IOC		(1 << 15)
+#define INFO_ACTIVE		(1 << 7)
+#define INFO_HALTED		(1 << 6)
+#define INFO_BUFFER_ERROR	(1 << 5)
+#define INFO_TX_ERROR		(1 << 3)
+#endif
diff --git a/drivers/usb/gadget/designware_udc.c b/drivers/usb/gadget/designware_udc.c
index 1aab31bbae..b7c10384a3 100644
--- a/drivers/usb/gadget/designware_udc.c
+++ b/drivers/usb/gadget/designware_udc.c
@@ -14,6 +14,7 @@
 #include <usbdevice.h>
 #include "ep0.h"
 #include <usb/designware_udc.h>
+#include <usb/udc.h>
 #include <asm/arch/hardware.h>
 
 #define UDC_INIT_MDELAY		80	/* Device settle delay */
diff --git a/drivers/usb/gadget/ether.c b/drivers/usb/gadget/ether.c
index 700d5fbfb2..cc6cc1f32a 100644
--- a/drivers/usb/gadget/ether.c
+++ b/drivers/usb/gadget/ether.c
@@ -635,6 +635,7 @@ fs_source_desc = {
 
 	.bEndpointAddress =	USB_DIR_IN,
 	.bmAttributes =		USB_ENDPOINT_XFER_BULK,
+	.wMaxPacketSize =	__constant_cpu_to_le16(64),
 };
 
 static struct usb_endpoint_descriptor
@@ -644,6 +645,7 @@ fs_sink_desc = {
 
 	.bEndpointAddress =	USB_DIR_OUT,
 	.bmAttributes =		USB_ENDPOINT_XFER_BULK,
+	.wMaxPacketSize =	__constant_cpu_to_le16(64),
 };
 
 static const struct usb_descriptor_header *fs_eth_function[11] = {
@@ -1534,6 +1536,8 @@ static int rx_submit(struct eth_dev *dev, struct usb_request *req,
 	 */
 
 	debug("%s\n", __func__);
+	if (!req)
+		return -EINVAL;
 
 	size = (ETHER_HDR_SIZE + dev->mtu + RX_EXTRA);
 	size += dev->out_ep->maxpacket - 1;
diff --git a/drivers/usb/gadget/f_dfu.c b/drivers/usb/gadget/f_dfu.c
index 37d04a1928..de75ff1339 100644
--- a/drivers/usb/gadget/f_dfu.c
+++ b/drivers/usb/gadget/f_dfu.c
@@ -40,6 +40,7 @@ struct f_dfu {
 
 	/* Send/received block number is handy for data integrity check */
 	int                             blk_seq_num;
+	unsigned int                    poll_timeout;
 };
 
 typedef int (*dfu_state_fn) (struct f_dfu *,
@@ -128,6 +129,33 @@ static struct usb_gadget_strings *dfu_strings[] = {
 	NULL,
 };
 
+static void dfu_set_poll_timeout(struct dfu_status *dstat, unsigned int ms)
+{
+	/*
+	 * The bwPollTimeout DFU_GETSTATUS request payload provides information
+	 * about minimum time, in milliseconds, that the host should wait before
+	 * sending a subsequent DFU_GETSTATUS request
+	 *
+	 * This permits the device to vary the delay depending on its need to
+	 * erase or program the memory
+	 *
+	 */
+
+	unsigned char *p = (unsigned char *)&ms;
+
+	if (!ms || (ms & ~DFU_POLL_TIMEOUT_MASK)) {
+		dstat->bwPollTimeout[0] = 0;
+		dstat->bwPollTimeout[1] = 0;
+		dstat->bwPollTimeout[2] = 0;
+
+		return;
+	}
+
+	dstat->bwPollTimeout[0] = *p++;
+	dstat->bwPollTimeout[1] = *p++;
+	dstat->bwPollTimeout[2] = *p;
+}
+
 /*-------------------------------------------------------------------------*/
 
 static void dnload_request_complete(struct usb_ep *ep, struct usb_request *req)
@@ -136,9 +164,14 @@ static void dnload_request_complete(struct usb_ep *ep, struct usb_request *req)
 
 	dfu_write(dfu_get_entity(f_dfu->altsetting), req->buf,
 		  req->length, f_dfu->blk_seq_num);
+}
 
-	if (req->length == 0)
-		puts("DOWNLOAD ... OK\nCtrl+C to exit ...\n");
+static void dnload_request_flush(struct usb_ep *ep, struct usb_request *req)
+{
+	struct f_dfu *f_dfu = req->context;
+
+	dfu_flush(dfu_get_entity(f_dfu->altsetting), req->buf,
+		  req->length, f_dfu->blk_seq_num);
 }
 
 static void handle_getstatus(struct usb_request *req)
@@ -146,22 +179,29 @@ static void handle_getstatus(struct usb_request *req)
 	struct dfu_status *dstat = (struct dfu_status *)req->buf;
 	struct f_dfu *f_dfu = req->context;
 
+	dfu_set_poll_timeout(dstat, 0);
+
 	switch (f_dfu->dfu_state) {
 	case DFU_STATE_dfuDNLOAD_SYNC:
 	case DFU_STATE_dfuDNBUSY:
 		f_dfu->dfu_state = DFU_STATE_dfuDNLOAD_IDLE;
 		break;
 	case DFU_STATE_dfuMANIFEST_SYNC:
+		f_dfu->dfu_state = DFU_STATE_dfuMANIFEST;
 		break;
+	case DFU_STATE_dfuMANIFEST:
+		dfu_set_poll_timeout(dstat, DFU_MANIFEST_POLL_TIMEOUT);
 	default:
 		break;
 	}
 
+	if (f_dfu->poll_timeout)
+		if (!(f_dfu->blk_seq_num %
+		      (dfu_get_buf_size() / DFU_USB_BUFSIZ)))
+			dfu_set_poll_timeout(dstat, f_dfu->poll_timeout);
+
 	/* send status response */
 	dstat->bStatus = f_dfu->dfu_status;
-	dstat->bwPollTimeout[0] = 0;
-	dstat->bwPollTimeout[1] = 0;
-	dstat->bwPollTimeout[2] = 0;
 	dstat->bState = f_dfu->dfu_state;
 	dstat->iString = 0;
 }
@@ -414,10 +454,11 @@ static int state_dfu_manifest_sync(struct f_dfu *f_dfu,
 	switch (ctrl->bRequest) {
 	case USB_REQ_DFU_GETSTATUS:
 		/* We're MainfestationTolerant */
-		f_dfu->dfu_state = DFU_STATE_dfuIDLE;
+		f_dfu->dfu_state = DFU_STATE_dfuMANIFEST;
 		handle_getstatus(req);
 		f_dfu->blk_seq_num = 0;
 		value = RET_STAT_LEN;
+		req->complete = dnload_request_flush;
 		break;
 	case USB_REQ_DFU_GETSTATE:
 		handle_getstate(req);
@@ -431,6 +472,33 @@ static int state_dfu_manifest_sync(struct f_dfu *f_dfu,
 	return value;
 }
 
+static int state_dfu_manifest(struct f_dfu *f_dfu,
+			      const struct usb_ctrlrequest *ctrl,
+			      struct usb_gadget *gadget,
+			      struct usb_request *req)
+{
+	int value = 0;
+
+	switch (ctrl->bRequest) {
+	case USB_REQ_DFU_GETSTATUS:
+		/* We're MainfestationTolerant */
+		f_dfu->dfu_state = DFU_STATE_dfuIDLE;
+		handle_getstatus(req);
+		f_dfu->blk_seq_num = 0;
+		value = RET_STAT_LEN;
+		puts("DOWNLOAD ... OK\nCtrl+C to exit ...\n");
+		break;
+	case USB_REQ_DFU_GETSTATE:
+		handle_getstate(req);
+		break;
+	default:
+		f_dfu->dfu_state = DFU_STATE_dfuERROR;
+		value = RET_STALL;
+		break;
+	}
+	return value;
+}
+
 static int state_dfu_upload_idle(struct f_dfu *f_dfu,
 				 const struct usb_ctrlrequest *ctrl,
 				 struct usb_gadget *gadget,
@@ -507,7 +575,7 @@ static dfu_state_fn dfu_state[] = {
 	state_dfu_dnbusy,        /* DFU_STATE_dfuDNBUSY */
 	state_dfu_dnload_idle,   /* DFU_STATE_dfuDNLOAD_IDLE */
 	state_dfu_manifest_sync, /* DFU_STATE_dfuMANIFEST_SYNC */
-	NULL,                    /* DFU_STATE_dfuMANIFEST */
+	state_dfu_manifest,	 /* DFU_STATE_dfuMANIFEST */
 	NULL,                    /* DFU_STATE_dfuMANIFEST_WAIT_RST */
 	state_dfu_upload_idle,   /* DFU_STATE_dfuUPLOAD_IDLE */
 	state_dfu_error          /* DFU_STATE_dfuERROR */
@@ -723,8 +791,9 @@ static int dfu_bind_config(struct usb_configuration *c)
 	f_dfu->usb_function.unbind = dfu_unbind;
 	f_dfu->usb_function.set_alt = dfu_set_alt;
 	f_dfu->usb_function.disable = dfu_disable;
-	f_dfu->usb_function.strings = dfu_generic_strings,
-	f_dfu->usb_function.setup = dfu_handle,
+	f_dfu->usb_function.strings = dfu_generic_strings;
+	f_dfu->usb_function.setup = dfu_handle;
+	f_dfu->poll_timeout = DFU_DEFAULT_POLL_TIMEOUT;
 
 	status = usb_add_function(c, &f_dfu->usb_function);
 	if (status)
diff --git a/drivers/usb/gadget/f_dfu.h b/drivers/usb/gadget/f_dfu.h
index cc2c45567b..0c29954add 100644
--- a/drivers/usb/gadget/f_dfu.h
+++ b/drivers/usb/gadget/f_dfu.h
@@ -82,4 +82,6 @@ struct dfu_function_descriptor {
 	__le16				wTransferSize;
 	__le16				bcdDFUVersion;
 } __packed;
+
+#define DFU_POLL_TIMEOUT_MASK           (0xFFFFFFUL)
 #endif /* __F_DFU_H_ */
diff --git a/drivers/usb/gadget/f_mass_storage.c b/drivers/usb/gadget/f_mass_storage.c
index 6ecdea3e14..f896169743 100644
--- a/drivers/usb/gadget/f_mass_storage.c
+++ b/drivers/usb/gadget/f_mass_storage.c
@@ -243,6 +243,7 @@
 #include <config.h>
 #include <malloc.h>
 #include <common.h>
+#include <usb.h>
 
 #include <linux/err.h>
 #include <linux/usb/ch9.h>
@@ -441,7 +442,7 @@ static void set_bulk_out_req_length(struct fsg_common *common,
 
 /*-------------------------------------------------------------------------*/
 
-struct ums_board_info			*ums_info;
+struct ums *ums;
 struct fsg_common *the_fsg_common;
 
 static int fsg_set_halt(struct fsg_dev *fsg, struct usb_ep *ep)
@@ -675,6 +676,18 @@ static int sleep_thread(struct fsg_common *common)
 			k++;
 		}
 
+		if (k == 10) {
+			/* Handle CTRL+C */
+			if (ctrlc())
+				return -EPIPE;
+#ifdef CONFIG_USB_CABLE_CHECK
+			/* Check cable connection */
+			if (!usb_cable_connected())
+				return -EIO;
+#endif
+			k = 0;
+		}
+
 		usb_gadget_handle_interrupts();
 	}
 	common->thread_wakeup_needed = 0;
@@ -757,14 +770,14 @@ static int do_read(struct fsg_common *common)
 		}
 
 		/* Perform the read */
-		nread = 0;
-		rc = ums_info->read_sector(&(ums_info->ums_dev),
-					   file_offset / SECTOR_SIZE,
-					   amount / SECTOR_SIZE,
-					   (char __user *)bh->buf);
-		if (rc)
+		rc = ums->read_sector(ums,
+				      file_offset / SECTOR_SIZE,
+				      amount / SECTOR_SIZE,
+				      (char __user *)bh->buf);
+		if (!rc)
 			return -EIO;
-		nread = amount;
+
+		nread = rc * SECTOR_SIZE;
 
 		VLDBG(curlun, "file read %u @ %llu -> %d\n", amount,
 				(unsigned long long) file_offset,
@@ -931,13 +944,13 @@ static int do_write(struct fsg_common *common)
 			amount = bh->outreq->actual;
 
 			/* Perform the write */
-			rc = ums_info->write_sector(&(ums_info->ums_dev),
+			rc = ums->write_sector(ums,
 					       file_offset / SECTOR_SIZE,
 					       amount / SECTOR_SIZE,
 					       (char __user *)bh->buf);
-			if (rc)
+			if (!rc)
 				return -EIO;
-			nwritten = amount;
+			nwritten = rc * SECTOR_SIZE;
 
 			VLDBG(curlun, "file write %u @ %llu -> %d\n", amount,
 					(unsigned long long) file_offset,
@@ -959,6 +972,8 @@ static int do_write(struct fsg_common *common)
 
 			/* If an error occurred, report it and its position */
 			if (nwritten < amount) {
+				printf("nwritten:%d amount:%d\n", nwritten,
+				       amount);
 				curlun->sense_data = SS_WRITE_ERROR;
 				curlun->info_valid = 1;
 				break;
@@ -1045,14 +1060,13 @@ static int do_verify(struct fsg_common *common)
 		}
 
 		/* Perform the read */
-		nread = 0;
-		rc = ums_info->read_sector(&(ums_info->ums_dev),
-					   file_offset / SECTOR_SIZE,
-					   amount / SECTOR_SIZE,
-					   (char __user *)bh->buf);
-		if (rc)
+		rc = ums->read_sector(ums,
+				      file_offset / SECTOR_SIZE,
+				      amount / SECTOR_SIZE,
+				      (char __user *)bh->buf);
+		if (!rc)
 			return -EIO;
-		nread = amount;
+		nread = rc * SECTOR_SIZE;
 
 		VLDBG(curlun, "file read %u @ %llu -> %d\n", amount,
 				(unsigned long long) file_offset,
@@ -1100,7 +1114,7 @@ static int do_inquiry(struct fsg_common *common, struct fsg_buffhd *bh)
 	buf[4] = 31;		/* Additional length */
 				/* No special options */
 	sprintf((char *) (buf + 8), "%-8s%-16s%04x", (char*) vendor_id ,
-			ums_info->name, (u16) 0xffff);
+			ums->name, (u16) 0xffff);
 
 	return 36;
 }
@@ -2386,6 +2400,7 @@ static void handle_exception(struct fsg_common *common)
 
 int fsg_main_thread(void *common_)
 {
+	int ret;
 	struct fsg_common	*common = the_fsg_common;
 	/* The main loop */
 	do {
@@ -2395,12 +2410,16 @@ int fsg_main_thread(void *common_)
 		}
 
 		if (!common->running) {
-			sleep_thread(common);
+			ret = sleep_thread(common);
+			if (ret)
+				return ret;
+
 			continue;
 		}
 
-		if (get_next_command(common))
-			continue;
+		ret = get_next_command(common);
+		if (ret)
+			return ret;
 
 		if (!exception_in_progress(common))
 			common->state = FSG_STATE_DATA_PHASE;
@@ -2496,7 +2515,7 @@ static struct fsg_common *fsg_common_init(struct fsg_common *common,
 buffhds_first_it:
 		bh->inreq_busy = 0;
 		bh->outreq_busy = 0;
-		bh->buf = kmalloc(FSG_BUFLEN, GFP_KERNEL);
+		bh->buf = memalign(CONFIG_SYS_CACHELINE_SIZE, FSG_BUFLEN);
 		if (unlikely(!bh->buf)) {
 			rc = -ENOMEM;
 			goto error_release;
@@ -2603,7 +2622,7 @@ usb_copy_descriptors(struct usb_descriptor_header **src)
 		bytes += (*tmp)->bLength;
 	bytes += (n_desc + 1) * sizeof(*tmp);
 
-	mem = kmalloc(bytes, GFP_KERNEL);
+	mem = memalign(CONFIG_SYS_CACHELINE_SIZE, bytes);
 	if (!mem)
 		return NULL;
 
@@ -2753,9 +2772,9 @@ int fsg_add(struct usb_configuration *c)
 	return fsg_bind_config(c->cdev, c, fsg_common);
 }
 
-int fsg_init(struct ums_board_info *ums)
+int fsg_init(struct ums *ums_dev)
 {
-	ums_info = ums;
+	ums = ums_dev;
 
 	return 0;
 }
diff --git a/drivers/usb/gadget/f_thor.c b/drivers/usb/gadget/f_thor.c
new file mode 100644
index 0000000000..f5c0224f21
--- /dev/null
+++ b/drivers/usb/gadget/f_thor.c
@@ -0,0 +1,1001 @@
+/*
+ * f_thor.c -- USB TIZEN THOR Downloader gadget function
+ *
+ * Copyright (C) 2013 Samsung Electronics
+ * Lukasz Majewski <l.majewski@samsung.com>
+ *
+ * Based on code from:
+ * git://review.tizen.org/kernel/u-boot
+ *
+ * Developed by:
+ * Copyright (C) 2009 Samsung Electronics
+ * Minkyu Kang <mk7.kang@samsung.com>
+ * Sanghee Kim <sh0130.kim@samsung.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <errno.h>
+#include <common.h>
+#include <malloc.h>
+#include <version.h>
+#include <linux/usb/ch9.h>
+#include <linux/usb/gadget.h>
+#include <linux/usb/composite.h>
+#include <linux/usb/cdc.h>
+#include <g_dnl.h>
+#include <dfu.h>
+
+#include "f_thor.h"
+
+static void thor_tx_data(unsigned char *data, int len);
+static void thor_set_dma(void *addr, int len);
+static int thor_rx_data(void);
+
+static struct f_thor *thor_func;
+static inline struct f_thor *func_to_thor(struct usb_function *f)
+{
+	return container_of(f, struct f_thor, usb_function);
+}
+
+DEFINE_CACHE_ALIGN_BUFFER(unsigned char, thor_tx_data_buf,
+			  sizeof(struct rsp_box));
+DEFINE_CACHE_ALIGN_BUFFER(unsigned char, thor_rx_data_buf,
+			  sizeof(struct rqt_box));
+
+/* ********************************************************** */
+/*         THOR protocol - transmission handling	      */
+/* ********************************************************** */
+DEFINE_CACHE_ALIGN_BUFFER(char, f_name, F_NAME_BUF_SIZE);
+static unsigned long long int thor_file_size;
+static int alt_setting_num;
+
+static void send_rsp(const struct rsp_box *rsp)
+{
+	memcpy(thor_tx_data_buf, rsp, sizeof(struct rsp_box));
+	thor_tx_data(thor_tx_data_buf, sizeof(struct rsp_box));
+
+	debug("-RSP: %d, %d\n", rsp->rsp, rsp->rsp_data);
+}
+
+static void send_data_rsp(s32 ack, s32 count)
+{
+	ALLOC_CACHE_ALIGN_BUFFER(struct data_rsp_box, rsp,
+				 sizeof(struct data_rsp_box));
+
+	rsp->ack = ack;
+	rsp->count = count;
+
+	memcpy(thor_tx_data_buf, rsp, sizeof(struct data_rsp_box));
+	thor_tx_data(thor_tx_data_buf, sizeof(struct data_rsp_box));
+
+	debug("-DATA RSP: %d, %d\n", ack, count);
+}
+
+static int process_rqt_info(const struct rqt_box *rqt)
+{
+	ALLOC_CACHE_ALIGN_BUFFER(struct rsp_box, rsp, sizeof(struct rsp_box));
+	memset(rsp, 0, sizeof(struct rsp_box));
+
+	rsp->rsp = rqt->rqt;
+	rsp->rsp_data = rqt->rqt_data;
+
+	switch (rqt->rqt_data) {
+	case RQT_INFO_VER_PROTOCOL:
+		rsp->int_data[0] = VER_PROTOCOL_MAJOR;
+		rsp->int_data[1] = VER_PROTOCOL_MINOR;
+		break;
+	case RQT_INIT_VER_HW:
+		snprintf(rsp->str_data[0], sizeof(rsp->str_data[0]),
+			 "%x", checkboard());
+		break;
+	case RQT_INIT_VER_BOOT:
+		sprintf(rsp->str_data[0], "%s", U_BOOT_VERSION);
+		break;
+	case RQT_INIT_VER_KERNEL:
+		sprintf(rsp->str_data[0], "%s", "k unknown");
+		break;
+	case RQT_INIT_VER_PLATFORM:
+		sprintf(rsp->str_data[0], "%s", "p unknown");
+		break;
+	case RQT_INIT_VER_CSC:
+		sprintf(rsp->str_data[0], "%s", "c unknown");
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	send_rsp(rsp);
+	return true;
+}
+
+static int process_rqt_cmd(const struct rqt_box *rqt)
+{
+	ALLOC_CACHE_ALIGN_BUFFER(struct rsp_box, rsp, sizeof(struct rsp_box));
+	memset(rsp, 0, sizeof(struct rsp_box));
+
+	rsp->rsp = rqt->rqt;
+	rsp->rsp_data = rqt->rqt_data;
+
+	switch (rqt->rqt_data) {
+	case RQT_CMD_REBOOT:
+		debug("TARGET RESET\n");
+		send_rsp(rsp);
+		g_dnl_unregister();
+		dfu_free_entities();
+		run_command("reset", 0);
+		break;
+	case RQT_CMD_POWEROFF:
+	case RQT_CMD_EFSCLEAR:
+		send_rsp(rsp);
+	default:
+		printf("Command not supported -> cmd: %d\n", rqt->rqt_data);
+		return -EINVAL;
+	}
+
+	return true;
+}
+
+static long long int download_head(unsigned long long total,
+				   unsigned int packet_size,
+				   long long int *left,
+				   int *cnt)
+{
+	long long int rcv_cnt = 0, left_to_rcv, ret_rcv;
+	void *transfer_buffer = dfu_get_buf();
+	void *buf = transfer_buffer;
+	int usb_pkt_cnt = 0, ret;
+
+	/*
+	 * Files smaller than THOR_STORE_UNIT_SIZE (now 32 MiB) are stored on
+	 * the medium.
+	 * The packet response is sent on the purpose after successful data
+	 * chunk write. There is a room for improvement when asynchronous write
+	 * is performed.
+	 */
+	while (total - rcv_cnt >= packet_size) {
+		thor_set_dma(buf, packet_size);
+		buf += packet_size;
+		ret_rcv = thor_rx_data();
+		if (ret_rcv < 0)
+			return ret_rcv;
+		rcv_cnt += ret_rcv;
+		debug("%d: RCV data count: %llu cnt: %d\n", usb_pkt_cnt,
+		      rcv_cnt, *cnt);
+
+		if ((rcv_cnt % THOR_STORE_UNIT_SIZE) == 0) {
+			ret = dfu_write(dfu_get_entity(alt_setting_num),
+					transfer_buffer, THOR_STORE_UNIT_SIZE,
+					(*cnt)++);
+			if (ret) {
+				error("DFU write failed [%d] cnt: %d",
+				      ret, *cnt);
+				return ret;
+			}
+			buf = transfer_buffer;
+		}
+		send_data_rsp(0, ++usb_pkt_cnt);
+	}
+
+	/* Calculate the amount of data to arrive from PC (in bytes) */
+	left_to_rcv = total - rcv_cnt;
+
+	/*
+	 * Calculate number of data already received. but not yet stored
+	 * on the medium (they are smaller than THOR_STORE_UNIT_SIZE)
+	 */
+	*left = left_to_rcv + buf - transfer_buffer;
+	debug("%s: left: %llu left_to_rcv: %llu buf: 0x%p\n", __func__,
+	      *left, left_to_rcv, buf);
+
+	if (left_to_rcv) {
+		thor_set_dma(buf, packet_size);
+		ret_rcv = thor_rx_data();
+		if (ret_rcv < 0)
+			return ret_rcv;
+		rcv_cnt += ret_rcv;
+		send_data_rsp(0, ++usb_pkt_cnt);
+	}
+
+	debug("%s: %llu total: %llu cnt: %d\n", __func__, rcv_cnt, total, *cnt);
+
+	return rcv_cnt;
+}
+
+static int download_tail(long long int left, int cnt)
+{
+	void *transfer_buffer = dfu_get_buf();
+	int ret;
+
+	debug("%s: left: %llu cnt: %d\n", __func__, left, cnt);
+
+	if (left) {
+		ret = dfu_write(dfu_get_entity(alt_setting_num),
+				transfer_buffer, left, cnt++);
+		if (ret) {
+			error("DFU write failed [%d]: left: %llu", ret, left);
+			return ret;
+		}
+	}
+
+	/*
+	 * To store last "packet" DFU storage backend requires dfu_write with
+	 * size parameter equal to 0
+	 *
+	 * This also frees memory malloc'ed by dfu_get_buf(), so no explicit
+	 * need fo call dfu_free_buf() is needed.
+	 */
+	ret = dfu_write(dfu_get_entity(alt_setting_num),
+			transfer_buffer, 0, cnt);
+	if (ret)
+		error("DFU write failed [%d] cnt: %d", ret, cnt);
+
+	return ret;
+}
+
+static long long int process_rqt_download(const struct rqt_box *rqt)
+{
+	ALLOC_CACHE_ALIGN_BUFFER(struct rsp_box, rsp, sizeof(struct rsp_box));
+	static long long int left, ret_head;
+	int file_type, ret = 0;
+	static int cnt;
+
+	memset(rsp, 0, sizeof(struct rsp_box));
+	rsp->rsp = rqt->rqt;
+	rsp->rsp_data = rqt->rqt_data;
+
+	switch (rqt->rqt_data) {
+	case RQT_DL_INIT:
+		thor_file_size = rqt->int_data[0];
+		debug("INIT: total %d bytes\n", rqt->int_data[0]);
+		break;
+	case RQT_DL_FILE_INFO:
+		file_type = rqt->int_data[0];
+		if (file_type == FILE_TYPE_PIT) {
+			puts("PIT table file - not supported\n");
+			rsp->ack = -ENOTSUPP;
+			ret = rsp->ack;
+			break;
+		}
+
+		thor_file_size = rqt->int_data[1];
+		memcpy(f_name, rqt->str_data[0], F_NAME_BUF_SIZE);
+
+		debug("INFO: name(%s, %d), size(%llu), type(%d)\n",
+		      f_name, 0, thor_file_size, file_type);
+
+		rsp->int_data[0] = THOR_PACKET_SIZE;
+
+		alt_setting_num = dfu_get_alt(f_name);
+		if (alt_setting_num < 0) {
+			error("Alt setting [%d] to write not found!",
+			      alt_setting_num);
+			rsp->ack = -ENODEV;
+			ret = rsp->ack;
+		}
+		break;
+	case RQT_DL_FILE_START:
+		send_rsp(rsp);
+		ret_head = download_head(thor_file_size, THOR_PACKET_SIZE,
+					 &left, &cnt);
+		if (ret_head < 0) {
+			left = 0;
+			cnt = 0;
+		}
+		return ret_head;
+	case RQT_DL_FILE_END:
+		debug("DL FILE_END\n");
+		rsp->ack = download_tail(left, cnt);
+		ret = rsp->ack;
+		left = 0;
+		cnt = 0;
+		break;
+	case RQT_DL_EXIT:
+		debug("DL EXIT\n");
+		break;
+	default:
+		error("Operation not supported: %d", rqt->rqt_data);
+		ret = -ENOTSUPP;
+	}
+
+	send_rsp(rsp);
+	return ret;
+}
+
+static int process_data(void)
+{
+	ALLOC_CACHE_ALIGN_BUFFER(struct rqt_box, rqt, sizeof(struct rqt_box));
+	int ret = -EINVAL;
+
+	memset(rqt, 0, sizeof(rqt));
+	memcpy(rqt, thor_rx_data_buf, sizeof(struct rqt_box));
+
+	debug("+RQT: %d, %d\n", rqt->rqt, rqt->rqt_data);
+
+	switch (rqt->rqt) {
+	case RQT_INFO:
+		ret = process_rqt_info(rqt);
+		break;
+	case RQT_CMD:
+		ret = process_rqt_cmd(rqt);
+		break;
+	case RQT_DL:
+		ret = (int) process_rqt_download(rqt);
+		break;
+	case RQT_UL:
+		puts("RQT: UPLOAD not supported!\n");
+		break;
+	default:
+		error("unknown request (%d)", rqt->rqt);
+	}
+
+	return ret;
+}
+
+/* ********************************************************** */
+/*         THOR USB Function				      */
+/* ********************************************************** */
+
+static inline struct usb_endpoint_descriptor *
+ep_desc(struct usb_gadget *g, struct usb_endpoint_descriptor *hs,
+	struct usb_endpoint_descriptor *fs)
+{
+	if (gadget_is_dualspeed(g) && g->speed == USB_SPEED_HIGH)
+		return hs;
+	return fs;
+}
+
+static struct usb_interface_descriptor thor_downloader_intf_data = {
+	.bLength =		sizeof(thor_downloader_intf_data),
+	.bDescriptorType =	USB_DT_INTERFACE,
+
+	.bNumEndpoints =	2,
+	.bInterfaceClass =	USB_CLASS_CDC_DATA,
+};
+
+static struct usb_endpoint_descriptor fs_in_desc = {
+	.bLength =		USB_DT_ENDPOINT_SIZE,
+	.bDescriptorType =	USB_DT_ENDPOINT,
+
+	.bEndpointAddress =	USB_DIR_IN,
+	.bmAttributes =	USB_ENDPOINT_XFER_BULK,
+};
+
+static struct usb_endpoint_descriptor fs_out_desc = {
+	.bLength =		USB_DT_ENDPOINT_SIZE,
+	.bDescriptorType =	USB_DT_ENDPOINT,
+
+	.bEndpointAddress =	USB_DIR_OUT,
+	.bmAttributes =	USB_ENDPOINT_XFER_BULK,
+};
+
+/* CDC configuration */
+static struct usb_interface_descriptor thor_downloader_intf_int = {
+	.bLength =		sizeof(thor_downloader_intf_int),
+	.bDescriptorType =	USB_DT_INTERFACE,
+
+	.bNumEndpoints =	1,
+	.bInterfaceClass =	USB_CLASS_COMM,
+	 /* 0x02 Abstract Line Control Model */
+	.bInterfaceSubClass =   USB_CDC_SUBCLASS_ACM,
+	/* 0x01 Common AT commands */
+	.bInterfaceProtocol =   USB_CDC_ACM_PROTO_AT_V25TER,
+};
+
+static struct usb_cdc_header_desc thor_downloader_cdc_header = {
+	.bLength         =    sizeof(thor_downloader_cdc_header),
+	.bDescriptorType =    0x24, /* CS_INTERFACE */
+	.bDescriptorSubType = 0x00,
+	.bcdCDC =             0x0110,
+};
+
+static struct usb_cdc_call_mgmt_descriptor thor_downloader_cdc_call = {
+	.bLength         =    sizeof(thor_downloader_cdc_call),
+	.bDescriptorType =    0x24, /* CS_INTERFACE */
+	.bDescriptorSubType = 0x01,
+	.bmCapabilities =     0x00,
+	.bDataInterface =     0x01,
+};
+
+static struct usb_cdc_acm_descriptor thor_downloader_cdc_abstract = {
+	.bLength         =    sizeof(thor_downloader_cdc_abstract),
+	.bDescriptorType =    0x24, /* CS_INTERFACE */
+	.bDescriptorSubType = 0x02,
+	.bmCapabilities =     0x00,
+};
+
+static struct usb_cdc_union_desc thor_downloader_cdc_union = {
+	.bLength         =     sizeof(thor_downloader_cdc_union),
+	.bDescriptorType =     0x24, /* CS_INTERFACE */
+	.bDescriptorSubType =  USB_CDC_UNION_TYPE,
+};
+
+static struct usb_endpoint_descriptor fs_int_desc = {
+	.bLength = USB_DT_ENDPOINT_SIZE,
+	.bDescriptorType = USB_DT_ENDPOINT,
+
+	.bEndpointAddress = 3 | USB_DIR_IN,
+	.bmAttributes = USB_ENDPOINT_XFER_INT,
+	.wMaxPacketSize = __constant_cpu_to_le16(16),
+
+	.bInterval = 0x9,
+};
+
+static struct usb_interface_assoc_descriptor
+thor_iad_descriptor = {
+	.bLength =		sizeof(thor_iad_descriptor),
+	.bDescriptorType =	USB_DT_INTERFACE_ASSOCIATION,
+
+	.bFirstInterface =	0,
+	.bInterfaceCount =	2,	/* control + data */
+	.bFunctionClass =	USB_CLASS_COMM,
+	.bFunctionSubClass =	USB_CDC_SUBCLASS_ACM,
+	.bFunctionProtocol =	USB_CDC_PROTO_NONE,
+};
+
+static struct usb_endpoint_descriptor hs_in_desc = {
+	.bLength =		USB_DT_ENDPOINT_SIZE,
+	.bDescriptorType =	USB_DT_ENDPOINT,
+
+	.bmAttributes =	USB_ENDPOINT_XFER_BULK,
+	.wMaxPacketSize =	__constant_cpu_to_le16(512),
+};
+
+static struct usb_endpoint_descriptor hs_out_desc = {
+	.bLength =		USB_DT_ENDPOINT_SIZE,
+	.bDescriptorType =	USB_DT_ENDPOINT,
+
+	.bmAttributes =	USB_ENDPOINT_XFER_BULK,
+	.wMaxPacketSize =	__constant_cpu_to_le16(512),
+};
+
+static struct usb_endpoint_descriptor hs_int_desc = {
+	.bLength = USB_DT_ENDPOINT_SIZE,
+	.bDescriptorType = USB_DT_ENDPOINT,
+
+	.bmAttributes = USB_ENDPOINT_XFER_INT,
+	.wMaxPacketSize = __constant_cpu_to_le16(16),
+
+	.bInterval = 0x9,
+};
+
+static struct usb_qualifier_descriptor dev_qualifier = {
+	.bLength =		sizeof(dev_qualifier),
+	.bDescriptorType =	USB_DT_DEVICE_QUALIFIER,
+
+	.bcdUSB =		__constant_cpu_to_le16(0x0200),
+	.bDeviceClass =	USB_CLASS_VENDOR_SPEC,
+
+	.bNumConfigurations =	2,
+};
+
+/*
+ * This attribute vendor descriptor is necessary for correct operation with
+ * Windows version of THOR download program
+ *
+ * It prevents windows driver from sending zero lenght packet (ZLP) after
+ * each THOR_PACKET_SIZE. This assures consistent behaviour with libusb
+ */
+static struct usb_cdc_attribute_vendor_descriptor thor_downloader_cdc_av = {
+	.bLength =              sizeof(thor_downloader_cdc_av),
+	.bDescriptorType =      0x24,
+	.bDescriptorSubType =   0x80,
+	.DAUType =              0x0002,
+	.DAULength =            0x0001,
+	.DAUValue =             0x00,
+};
+
+static const struct usb_descriptor_header *hs_thor_downloader_function[] = {
+	(struct usb_descriptor_header *)&thor_iad_descriptor,
+
+	(struct usb_descriptor_header *)&thor_downloader_intf_int,
+	(struct usb_descriptor_header *)&thor_downloader_cdc_header,
+	(struct usb_descriptor_header *)&thor_downloader_cdc_call,
+	(struct usb_descriptor_header *)&thor_downloader_cdc_abstract,
+	(struct usb_descriptor_header *)&thor_downloader_cdc_union,
+	(struct usb_descriptor_header *)&hs_int_desc,
+
+	(struct usb_descriptor_header *)&thor_downloader_intf_data,
+	(struct usb_descriptor_header *)&thor_downloader_cdc_av,
+	(struct usb_descriptor_header *)&hs_in_desc,
+	(struct usb_descriptor_header *)&hs_out_desc,
+	NULL,
+};
+
+/*-------------------------------------------------------------------------*/
+static struct usb_request *alloc_ep_req(struct usb_ep *ep, unsigned length)
+{
+	struct usb_request *req;
+
+	req = usb_ep_alloc_request(ep, 0);
+	if (!req)
+		return req;
+
+	req->length = length;
+	req->buf = memalign(CONFIG_SYS_CACHELINE_SIZE, length);
+	if (!req->buf) {
+		usb_ep_free_request(ep, req);
+		req = NULL;
+	}
+
+	return req;
+}
+
+static int thor_rx_data(void)
+{
+	struct thor_dev *dev = thor_func->dev;
+	int data_to_rx, tmp, status;
+
+	data_to_rx = dev->out_req->length;
+	tmp = data_to_rx;
+	do {
+		dev->out_req->length = data_to_rx;
+		debug("dev->out_req->length:%d dev->rxdata:%d\n",
+		      dev->out_req->length, dev->rxdata);
+
+		status = usb_ep_queue(dev->out_ep, dev->out_req, 0);
+		if (status) {
+			error("kill %s:  resubmit %d bytes --> %d",
+			      dev->out_ep->name, dev->out_req->length, status);
+			usb_ep_set_halt(dev->out_ep);
+			return -EAGAIN;
+		}
+
+		while (!dev->rxdata) {
+			usb_gadget_handle_interrupts();
+			if (ctrlc())
+				return -1;
+		}
+		dev->rxdata = 0;
+		data_to_rx -= dev->out_req->actual;
+	} while (data_to_rx);
+
+	return tmp;
+}
+
+static void thor_tx_data(unsigned char *data, int len)
+{
+	struct thor_dev *dev = thor_func->dev;
+	unsigned char *ptr = dev->in_req->buf;
+	int status;
+
+	memset(ptr, 0, len);
+	memcpy(ptr, data, len);
+
+	dev->in_req->length = len;
+
+	debug("%s: dev->in_req->length:%d to_cpy:%d\n", __func__,
+	      dev->in_req->length, sizeof(data));
+
+	status = usb_ep_queue(dev->in_ep, dev->in_req, 0);
+	if (status) {
+		error("kill %s:  resubmit %d bytes --> %d",
+		      dev->in_ep->name, dev->in_req->length, status);
+		usb_ep_set_halt(dev->in_ep);
+	}
+
+	/* Wait until tx interrupt received */
+	while (!dev->txdata)
+		usb_gadget_handle_interrupts();
+
+	dev->txdata = 0;
+}
+
+static void thor_rx_tx_complete(struct usb_ep *ep, struct usb_request *req)
+{
+	struct thor_dev *dev = thor_func->dev;
+	int status = req->status;
+
+	debug("%s: ep_ptr:%p, req_ptr:%p\n", __func__, ep, req);
+	switch (status) {
+	case 0:
+		if (ep == dev->out_ep)
+			dev->rxdata = 1;
+		else
+			dev->txdata = 1;
+
+		break;
+
+	/* this endpoint is normally active while we're configured */
+	case -ECONNABORTED:		/* hardware forced ep reset */
+	case -ECONNRESET:		/* request dequeued */
+	case -ESHUTDOWN:		/* disconnect from host */
+	case -EREMOTEIO:                /* short read */
+	case -EOVERFLOW:
+		error("ERROR:%d", status);
+		break;
+	}
+
+	debug("%s complete --> %d, %d/%d\n", ep->name,
+	      status, req->actual, req->length);
+}
+
+static struct usb_request *thor_start_ep(struct usb_ep *ep)
+{
+	struct usb_request *req;
+
+	req = alloc_ep_req(ep, THOR_PACKET_SIZE);
+	debug("%s: ep:%p req:%p\n", __func__, ep, req);
+
+	if (!req)
+		return NULL;
+
+	memset(req->buf, 0, req->length);
+	req->complete = thor_rx_tx_complete;
+
+	return req;
+}
+
+static void thor_setup_complete(struct usb_ep *ep, struct usb_request *req)
+{
+	if (req->status || req->actual != req->length)
+		debug("setup complete --> %d, %d/%d\n",
+		      req->status, req->actual, req->length);
+}
+
+static int
+thor_func_setup(struct usb_function *f, const struct usb_ctrlrequest *ctrl)
+{
+	struct thor_dev *dev = thor_func->dev;
+	struct usb_request *req = dev->req;
+	struct usb_gadget *gadget = dev->gadget;
+	int value = 0;
+
+	u16 len = le16_to_cpu(ctrl->wLength);
+
+	debug("Req_Type: 0x%x Req: 0x%x wValue: 0x%x wIndex: 0x%x wLen: 0x%x\n",
+	      ctrl->bRequestType, ctrl->bRequest, ctrl->wValue, ctrl->wIndex,
+	      ctrl->wLength);
+
+	switch (ctrl->bRequest) {
+	case USB_CDC_REQ_SET_CONTROL_LINE_STATE:
+		value = 0;
+		break;
+	case USB_CDC_REQ_SET_LINE_CODING:
+		value = len;
+		/* Line Coding set done = configuration done */
+		thor_func->dev->configuration_done = 1;
+		break;
+
+	default:
+		error("thor_setup: unknown request: %d", ctrl->bRequest);
+	}
+
+	if (value >= 0) {
+		req->length = value;
+		req->zero = value < len;
+		value = usb_ep_queue(gadget->ep0, req, 0);
+		if (value < 0) {
+			debug("%s: ep_queue: %d\n", __func__, value);
+			req->status = 0;
+		}
+	}
+
+	return value;
+}
+
+/* Specific to the THOR protocol */
+static void thor_set_dma(void *addr, int len)
+{
+	struct thor_dev *dev = thor_func->dev;
+
+	debug("in_req:%p, out_req:%p\n", dev->in_req, dev->out_req);
+	debug("addr:%p, len:%d\n", addr, len);
+
+	dev->out_req->buf = addr;
+	dev->out_req->length = len;
+}
+
+int thor_init(void)
+{
+	struct thor_dev *dev = thor_func->dev;
+
+	/* Wait for a device enumeration and configuration settings */
+	debug("THOR enumeration/configuration setting....\n");
+	while (!dev->configuration_done)
+		usb_gadget_handle_interrupts();
+
+	thor_set_dma(thor_rx_data_buf, strlen("THOR"));
+	/* detect the download request from Host PC */
+	if (thor_rx_data() < 0) {
+		printf("%s: Data not received!\n", __func__);
+		return -1;
+	}
+
+	if (!strncmp((char *)thor_rx_data_buf, "THOR", strlen("THOR"))) {
+		puts("Download request from the Host PC\n");
+		udelay(30 * 1000); /* 30 ms */
+
+		strcpy((char *)thor_tx_data_buf, "ROHT");
+		thor_tx_data(thor_tx_data_buf, strlen("ROHT"));
+	} else {
+		puts("Wrong reply information\n");
+		return -1;
+	}
+
+	return 0;
+}
+
+int thor_handle(void)
+{
+	int ret;
+
+	/* receive the data from Host PC */
+	while (1) {
+		thor_set_dma(thor_rx_data_buf, sizeof(struct rqt_box));
+		ret = thor_rx_data();
+
+		if (ret > 0) {
+			ret = process_data();
+			if (ret < 0)
+				return ret;
+		} else {
+			printf("%s: No data received!\n", __func__);
+			break;
+		}
+	}
+
+	return 0;
+}
+
+static int thor_func_bind(struct usb_configuration *c, struct usb_function *f)
+{
+	struct usb_gadget *gadget = c->cdev->gadget;
+	struct f_thor *f_thor = func_to_thor(f);
+	struct thor_dev *dev;
+	struct usb_ep *ep;
+	int status;
+
+	thor_func = f_thor;
+	dev = memalign(CONFIG_SYS_CACHELINE_SIZE, sizeof(*dev));
+	if (!dev)
+		return -ENOMEM;
+
+	memset(dev, 0, sizeof(*dev));
+	dev->gadget = gadget;
+	f_thor->dev = dev;
+
+	debug("%s: usb_configuration: 0x%p usb_function: 0x%p\n",
+	      __func__, c, f);
+	debug("f_thor: 0x%p thor: 0x%p\n", f_thor, dev);
+
+	/* EP0  */
+	/* preallocate control response and buffer */
+	dev->req = usb_ep_alloc_request(gadget->ep0, 0);
+	if (!dev->req) {
+		status = -ENOMEM;
+		goto fail;
+	}
+	dev->req->buf = memalign(CONFIG_SYS_CACHELINE_SIZE,
+				 gadget->ep0->maxpacket);
+	if (!dev->req->buf) {
+		status = -ENOMEM;
+		goto fail;
+	}
+
+	dev->req->complete = thor_setup_complete;
+
+	/* DYNAMIC interface numbers assignments */
+	status = usb_interface_id(c, f);
+
+	if (status < 0)
+		goto fail;
+
+	thor_downloader_intf_int.bInterfaceNumber = status;
+	thor_downloader_cdc_union.bMasterInterface0 = status;
+
+	status = usb_interface_id(c, f);
+
+	if (status < 0)
+		goto fail;
+
+	thor_downloader_intf_data.bInterfaceNumber = status;
+	thor_downloader_cdc_union.bSlaveInterface0 = status;
+
+	/* allocate instance-specific endpoints */
+	ep = usb_ep_autoconfig(gadget, &fs_in_desc);
+	if (!ep) {
+		status = -ENODEV;
+		goto fail;
+	}
+
+	if (gadget_is_dualspeed(gadget)) {
+		hs_in_desc.bEndpointAddress =
+				fs_in_desc.bEndpointAddress;
+	}
+
+	dev->in_ep = ep; /* Store IN EP for enabling @ setup */
+
+	ep = usb_ep_autoconfig(gadget, &fs_out_desc);
+	if (!ep) {
+		status = -ENODEV;
+		goto fail;
+	}
+
+	if (gadget_is_dualspeed(gadget))
+		hs_out_desc.bEndpointAddress =
+				fs_out_desc.bEndpointAddress;
+
+	dev->out_ep = ep; /* Store OUT EP for enabling @ setup */
+
+	ep = usb_ep_autoconfig(gadget, &fs_int_desc);
+	if (!ep) {
+		status = -ENODEV;
+		goto fail;
+	}
+
+	dev->int_ep = ep;
+
+	if (gadget_is_dualspeed(gadget)) {
+		hs_int_desc.bEndpointAddress =
+				fs_int_desc.bEndpointAddress;
+
+		f->hs_descriptors = (struct usb_descriptor_header **)
+			&hs_thor_downloader_function;
+
+		if (!f->hs_descriptors)
+			goto fail;
+	}
+
+	debug("%s: out_ep:%p out_req:%p\n", __func__,
+	      dev->out_ep, dev->out_req);
+
+	return 0;
+
+ fail:
+	free(dev);
+	return status;
+}
+
+static void free_ep_req(struct usb_ep *ep, struct usb_request *req)
+{
+	free(req->buf);
+	usb_ep_free_request(ep, req);
+}
+
+static void thor_unbind(struct usb_configuration *c, struct usb_function *f)
+{
+	struct f_thor *f_thor = func_to_thor(f);
+	struct thor_dev *dev = f_thor->dev;
+
+	free(dev);
+	memset(thor_func, 0, sizeof(*thor_func));
+	thor_func = NULL;
+}
+
+static void thor_func_disable(struct usb_function *f)
+{
+	struct f_thor *f_thor = func_to_thor(f);
+	struct thor_dev *dev = f_thor->dev;
+
+	debug("%s:\n", __func__);
+
+	/* Avoid freeing memory when ep is still claimed */
+	if (dev->in_ep->driver_data) {
+		free_ep_req(dev->in_ep, dev->in_req);
+		usb_ep_disable(dev->in_ep);
+		dev->in_ep->driver_data = NULL;
+	}
+
+	if (dev->out_ep->driver_data) {
+		dev->out_req->buf = NULL;
+		usb_ep_free_request(dev->out_ep, dev->out_req);
+		usb_ep_disable(dev->out_ep);
+		dev->out_ep->driver_data = NULL;
+	}
+
+	if (dev->int_ep->driver_data) {
+		usb_ep_disable(dev->int_ep);
+		dev->int_ep->driver_data = NULL;
+	}
+}
+
+static int thor_eps_setup(struct usb_function *f)
+{
+	struct usb_composite_dev *cdev = f->config->cdev;
+	struct usb_gadget *gadget = cdev->gadget;
+	struct thor_dev *dev = thor_func->dev;
+	struct usb_endpoint_descriptor *d;
+	struct usb_request *req;
+	struct usb_ep *ep;
+	int result;
+
+	ep = dev->in_ep;
+	d = ep_desc(gadget, &hs_in_desc, &fs_in_desc);
+	debug("(d)bEndpointAddress: 0x%x\n", d->bEndpointAddress);
+
+	result = usb_ep_enable(ep, d);
+	if (result)
+		goto exit;
+
+	ep->driver_data = cdev; /* claim */
+	req = thor_start_ep(ep);
+	if (!req) {
+		usb_ep_disable(ep);
+		result = -EIO;
+		goto exit;
+	}
+
+	dev->in_req = req;
+	ep = dev->out_ep;
+	d = ep_desc(gadget, &hs_out_desc, &fs_out_desc);
+	debug("(d)bEndpointAddress: 0x%x\n", d->bEndpointAddress);
+
+	result = usb_ep_enable(ep, d);
+	if (result)
+		goto exit;
+
+	ep->driver_data = cdev; /* claim */
+	req = thor_start_ep(ep);
+	if (!req) {
+		usb_ep_disable(ep);
+		result = -EIO;
+		goto exit;
+	}
+
+	dev->out_req = req;
+	/* ACM control EP */
+	ep = dev->int_ep;
+	ep->driver_data = cdev;	/* claim */
+
+ exit:
+	return result;
+}
+
+static int thor_func_set_alt(struct usb_function *f,
+			     unsigned intf, unsigned alt)
+{
+	struct thor_dev *dev = thor_func->dev;
+	int result;
+
+	debug("%s: func: %s intf: %d alt: %d\n",
+	      __func__, f->name, intf, alt);
+
+	switch (intf) {
+	case 0:
+		debug("ACM INTR interface\n");
+		break;
+	case 1:
+		debug("Communication Data interface\n");
+		result = thor_eps_setup(f);
+		if (result)
+			error("%s: EPs setup failed!", __func__);
+		dev->configuration_done = 1;
+		break;
+	}
+
+	return 0;
+}
+
+static int thor_func_init(struct usb_configuration *c)
+{
+	struct f_thor *f_thor;
+	int status;
+
+	debug("%s: cdev: 0x%p\n", __func__, c->cdev);
+
+	f_thor = memalign(CONFIG_SYS_CACHELINE_SIZE, sizeof(*f_thor));
+	if (!f_thor)
+		return -ENOMEM;
+
+	memset(f_thor, 0, sizeof(*f_thor));
+
+	f_thor->usb_function.name = "f_thor";
+	f_thor->usb_function.bind = thor_func_bind;
+	f_thor->usb_function.unbind = thor_unbind;
+	f_thor->usb_function.setup = thor_func_setup;
+	f_thor->usb_function.set_alt = thor_func_set_alt;
+	f_thor->usb_function.disable = thor_func_disable;
+
+	status = usb_add_function(c, &f_thor->usb_function);
+	if (status)
+		free(f_thor);
+
+	return status;
+}
+
+int thor_add(struct usb_configuration *c)
+{
+	debug("%s:\n", __func__);
+	return thor_func_init(c);
+}
diff --git a/drivers/usb/gadget/f_thor.h b/drivers/usb/gadget/f_thor.h
new file mode 100644
index 0000000000..833a9d24ae
--- /dev/null
+++ b/drivers/usb/gadget/f_thor.h
@@ -0,0 +1,124 @@
+/*
+ * f_thor.h - USB TIZEN THOR - internal gadget definitions
+ *
+ * Copyright (C) 2013 Samsung Electronics
+ * Lukasz Majewski  <l.majewski@samsung.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _USB_THOR_H_
+#define _USB_THOR_H_
+
+#include <linux/compiler.h>
+#include <linux/sizes.h>
+
+/* THOR Composite Gadget */
+#define STRING_MANUFACTURER_IDX	0
+#define STRING_PRODUCT_IDX		1
+#define STRING_SERIAL_IDX		2
+
+/* ********************************************************** */
+/*                   THOR protocol definitions		      */
+/* ********************************************************** */
+
+/*
+ * Attribute Vendor descriptor - necessary to prevent ZLP transmission
+ * from Windows XP HOST PC
+ */
+struct usb_cdc_attribute_vendor_descriptor {
+	__u8 bLength;
+	__u8 bDescriptorType;
+	__u8 bDescriptorSubType;
+	__u16 DAUType;
+	__u16 DAULength;
+	__u8 DAUValue;
+} __packed;
+
+#define VER_PROTOCOL_MAJOR	4
+#define VER_PROTOCOL_MINOR	0
+
+enum rqt {
+	RQT_INFO = 200,
+	RQT_CMD,
+	RQT_DL,
+	RQT_UL,
+};
+
+enum rqt_data {
+	/* RQT_INFO */
+	RQT_INFO_VER_PROTOCOL = 1,
+	RQT_INIT_VER_HW,
+	RQT_INIT_VER_BOOT,
+	RQT_INIT_VER_KERNEL,
+	RQT_INIT_VER_PLATFORM,
+	RQT_INIT_VER_CSC,
+
+	/* RQT_CMD */
+	RQT_CMD_REBOOT = 1,
+	RQT_CMD_POWEROFF,
+	RQT_CMD_EFSCLEAR,
+
+	/* RQT_DL */
+	RQT_DL_INIT = 1,
+	RQT_DL_FILE_INFO,
+	RQT_DL_FILE_START,
+	RQT_DL_FILE_END,
+	RQT_DL_EXIT,
+
+	/* RQT_UL */
+	RQT_UL_INIT = 1,
+	RQT_UL_START,
+	RQT_UL_END,
+	RQT_UL_EXIT,
+};
+
+struct rqt_box {		/* total: 256B */
+	s32 rqt;		/* request id */
+	s32 rqt_data;		/* request data id */
+	s32 int_data[14];	/* int data */
+	char str_data[5][32];	/* string data */
+	char md5[32];		/* md5 checksum */
+} __packed;
+
+struct rsp_box {		/* total: 128B */
+	s32 rsp;		/* response id (= request id) */
+	s32 rsp_data;		/* response data id */
+	s32 ack;		/* ack */
+	s32 int_data[5];	/* int data */
+	char str_data[3][32];	/* string data */
+} __packed;
+
+struct data_rsp_box {		/* total: 8B */
+	s32 ack;		/* response id (= request id) */
+	s32 count;		/* response data id */
+} __packed;
+
+enum {
+	FILE_TYPE_NORMAL,
+	FILE_TYPE_PIT,
+};
+
+struct thor_dev {
+	struct usb_gadget *gadget;
+	struct usb_request *req; /* EP0 -> control responses */
+
+	/* IN/OUT EP's and correspoinding requests */
+	struct usb_ep *in_ep, *out_ep, *int_ep;
+	struct usb_request *in_req, *out_req;
+
+	/* Control flow variables */
+	unsigned char configuration_done;
+	unsigned char rxdata;
+	unsigned char txdata;
+};
+
+struct f_thor {
+	struct usb_function usb_function;
+	struct thor_dev *dev;
+};
+
+#define F_NAME_BUF_SIZE 32
+#define THOR_PACKET_SIZE SZ_1M      /* 1 MiB */
+#define THOR_STORE_UNIT_SIZE SZ_32M /* 32 MiB */
+#endif /* _USB_THOR_H_ */
diff --git a/drivers/usb/gadget/fotg210.c b/drivers/usb/gadget/fotg210.c
index 6e19db15fa..3acf6a1f41 100644
--- a/drivers/usb/gadget/fotg210.c
+++ b/drivers/usb/gadget/fotg210.c
@@ -245,6 +245,7 @@ static int fotg210_dma(struct fotg210_ep *ep, struct fotg210_request *req)
 		if (ep->id == 0) {
 			/* Wait until cx/ep0 fifo empty */
 			fotg210_cxwait(chip, CXFIFO_CXFIFOE);
+			udelay(1);
 			writel(DMAFIFO_CX, &regs->dma_fifo);
 		} else {
 			/* Wait until epx fifo empty */
@@ -847,6 +848,13 @@ int usb_gadget_handle_interrupts(void)
 	/* CX interrupts */
 	if (gisr & GISR_GRP0) {
 		st = readl(&regs->gisr0);
+		/*
+		 * Write 1 and then 0 works for both W1C & RW.
+		 *
+		 * HW v1.11.0+: It's a W1C register (write 1 clear)
+		 * HW v1.10.0-: It's a R/W register (write 0 clear)
+		 */
+		writel(st & GISR0_CXABORT, &regs->gisr0);
 		writel(0, &regs->gisr0);
 
 		if (st & GISR0_CXERR)
@@ -873,6 +881,13 @@ int usb_gadget_handle_interrupts(void)
 	/* Device Status Interrupts */
 	if (gisr & GISR_GRP2) {
 		st = readl(&regs->gisr2);
+		/*
+		 * Write 1 and then 0 works for both W1C & RW.
+		 *
+		 * HW v1.11.0+: It's a W1C register (write 1 clear)
+		 * HW v1.10.0-: It's a R/W register (write 0 clear)
+		 */
+		writel(st, &regs->gisr2);
 		writel(0, &regs->gisr2);
 
 		if (st & GISR2_RESET)
diff --git a/drivers/usb/gadget/g_dnl.c b/drivers/usb/gadget/g_dnl.c
index 40868c034e..dd95afe86a 100644
--- a/drivers/usb/gadget/g_dnl.c
+++ b/drivers/usb/gadget/g_dnl.c
@@ -16,6 +16,7 @@
 #include <g_dnl.h>
 #include <usb_mass_storage.h>
 #include <dfu.h>
+#include <thor.h>
 
 #include "gadget_chips.h"
 #include "composite.c"
@@ -32,6 +33,9 @@
 #define STRING_PRODUCT 2
 /* Index of String Descriptor describing this configuration */
 #define STRING_USBDOWN 2
+/* Index of String serial */
+#define STRING_SERIAL  3
+#define MAX_STRING_SERIAL	32
 /* Number of supported configurations */
 #define CONFIGURATION_NUMBER 1
 
@@ -39,8 +43,16 @@
 
 static const char shortname[] = "usb_dnl_";
 static const char product[] = "USB download gadget";
+static char g_dnl_serial[MAX_STRING_SERIAL];
 static const char manufacturer[] = CONFIG_G_DNL_MANUFACTURER;
 
+void g_dnl_set_serialnumber(char *s)
+{
+	memset(g_dnl_serial, 0, MAX_STRING_SERIAL);
+	if (strlen(s) < MAX_STRING_SERIAL)
+		strncpy(g_dnl_serial, s, strlen(s));
+}
+
 static struct usb_device_descriptor device_desc = {
 	.bLength = sizeof device_desc,
 	.bDescriptorType = USB_DT_DEVICE,
@@ -52,6 +64,7 @@ static struct usb_device_descriptor device_desc = {
 	.idVendor = __constant_cpu_to_le16(CONFIG_G_DNL_VENDOR_NUM),
 	.idProduct = __constant_cpu_to_le16(CONFIG_G_DNL_PRODUCT_NUM),
 	.iProduct = STRING_PRODUCT,
+	.iSerialNumber = STRING_SERIAL,
 	.bNumConfigurations = 1,
 };
 
@@ -62,6 +75,7 @@ static struct usb_device_descriptor device_desc = {
 static struct usb_string g_dnl_string_defs[] = {
 	{.s = manufacturer},
 	{.s = product},
+	{.s = g_dnl_serial},
 	{ }		/* end of list */
 };
 
@@ -79,6 +93,8 @@ static int g_dnl_unbind(struct usb_composite_dev *cdev)
 {
 	struct usb_gadget *gadget = cdev->gadget;
 
+	free(cdev->config);
+	cdev->config = NULL;
 	debug("%s: calling usb_gadget_disconnect for "
 			"controller '%s'\n", shortname, gadget->name);
 	usb_gadget_disconnect(gadget);
@@ -99,30 +115,55 @@ static int g_dnl_do_config(struct usb_configuration *c)
 		ret = dfu_add(c);
 	else if (!strcmp(s, "usb_dnl_ums"))
 		ret = fsg_add(c);
+	else if (!strcmp(s, "usb_dnl_thor"))
+		ret = thor_add(c);
 
 	return ret;
 }
 
 static int g_dnl_config_register(struct usb_composite_dev *cdev)
 {
-	static struct usb_configuration config = {
-		.label = "usb_dnload",
-		.bmAttributes =	USB_CONFIG_ATT_ONE | USB_CONFIG_ATT_SELFPOWER,
-		.bConfigurationValue =	CONFIGURATION_NUMBER,
-		.iConfiguration =	STRING_USBDOWN,
+	struct usb_configuration *config;
+	const char *name = "usb_dnload";
+
+	config = memalign(CONFIG_SYS_CACHELINE_SIZE, sizeof(*config));
+	if (!config)
+		return -ENOMEM;
 
-		.bind = g_dnl_do_config,
-	};
+	memset(config, 0, sizeof(*config));
 
-	return usb_add_config(cdev, &config);
+	config->label = name;
+	config->bmAttributes = USB_CONFIG_ATT_ONE | USB_CONFIG_ATT_SELFPOWER;
+	config->bConfigurationValue = CONFIGURATION_NUMBER;
+	config->iConfiguration = STRING_USBDOWN;
+	config->bind = g_dnl_do_config;
+
+	return usb_add_config(cdev, config);
 }
 
 __weak
-int g_dnl_bind_fixup(struct usb_device_descriptor *dev)
+int g_dnl_bind_fixup(struct usb_device_descriptor *dev, const char *name)
 {
 	return 0;
 }
 
+__weak int g_dnl_get_board_bcd_device_number(int gcnum)
+{
+	return gcnum;
+}
+
+static int g_dnl_get_bcd_device_number(struct usb_composite_dev *cdev)
+{
+	struct usb_gadget *gadget = cdev->gadget;
+	int gcnum;
+
+	gcnum = usb_gadget_controller_number(gadget);
+	if (gcnum > 0)
+		gcnum += 0x200;
+
+	return g_dnl_get_board_bcd_device_number(gcnum);
+}
+
 static int g_dnl_bind(struct usb_composite_dev *cdev)
 {
 	struct usb_gadget *gadget = cdev->gadget;
@@ -145,16 +186,21 @@ static int g_dnl_bind(struct usb_composite_dev *cdev)
 	g_dnl_string_defs[1].id = id;
 	device_desc.iProduct = id;
 
-	g_dnl_bind_fixup(&device_desc);
+	id = usb_string_id(cdev);
+	if (id < 0)
+		return id;
+
+	g_dnl_string_defs[2].id = id;
+	device_desc.iSerialNumber = id;
+
+	g_dnl_bind_fixup(&device_desc, cdev->driver->name);
 	ret = g_dnl_config_register(cdev);
 	if (ret)
 		goto error;
 
-	gcnum = usb_gadget_controller_number(gadget);
-
-	debug("gcnum: %d\n", gcnum);
+	gcnum = g_dnl_get_bcd_device_number(cdev);
 	if (gcnum >= 0)
-		device_desc.bcdDevice = cpu_to_le16(0x0200 + gcnum);
+		device_desc.bcdDevice = cpu_to_le16(gcnum);
 	else {
 		debug("%s: controller '%s' not recognized\n",
 			shortname, gadget->name);
@@ -183,8 +229,8 @@ static struct usb_composite_driver g_dnl_driver = {
 
 int g_dnl_register(const char *type)
 {
-	/* We only allow "dfu" atm, so 3 should be enough */
-	static char name[sizeof(shortname) + 3];
+	/* The largest function name is 4 */
+	static char name[sizeof(shortname) + 4];
 	int ret;
 
 	if (!strcmp(type, "dfu")) {
@@ -193,6 +239,9 @@ int g_dnl_register(const char *type)
 	} else if (!strcmp(type, "ums")) {
 		strcpy(name, shortname);
 		strcat(name, type);
+	} else if (!strcmp(type, "thor")) {
+		strcpy(name, shortname);
+		strcat(name, type);
 	} else {
 		printf("%s: unknown command: %s\n", __func__, type);
 		return -EINVAL;
diff --git a/drivers/usb/gadget/gadget_chips.h b/drivers/usb/gadget/gadget_chips.h
index aa54b8547e..cc94771e32 100644
--- a/drivers/usb/gadget/gadget_chips.h
+++ b/drivers/usb/gadget/gadget_chips.h
@@ -144,10 +144,10 @@
 #define	gadget_is_m66592(g)	0
 #endif
 
-#ifdef CONFIG_MV_UDC
-#define gadget_is_mv(g)        (!strcmp("mv_udc", (g)->name))
+#ifdef CONFIG_CI_UDC
+#define gadget_is_ci(g)        (!strcmp("ci_udc", (g)->name))
 #else
-#define gadget_is_mv(g)        0
+#define gadget_is_ci(g)        0
 #endif
 
 #ifdef CONFIG_USB_GADGET_FOTG210
@@ -219,7 +219,7 @@ static inline int usb_gadget_controller_number(struct usb_gadget *gadget)
 		return 0x19;
 	else if (gadget_is_m66592(gadget))
 		return 0x20;
-	else if (gadget_is_mv(gadget))
+	else if (gadget_is_ci(gadget))
 		return 0x21;
 	else if (gadget_is_fotg210(gadget))
 		return 0x22;
diff --git a/drivers/usb/gadget/mpc8xx_udc.c b/drivers/usb/gadget/mpc8xx_udc.c
index 0207d391a8..7f72972dcc 100644
--- a/drivers/usb/gadget/mpc8xx_udc.c
+++ b/drivers/usb/gadget/mpc8xx_udc.c
@@ -47,6 +47,7 @@
 #include <commproc.h>
 #include <usbdevice.h>
 #include <usb/mpc8xx_udc.h>
+#include <usb/udc.h>
 
 #include "ep0.h"
 
diff --git a/drivers/usb/gadget/mv_udc.c b/drivers/usb/gadget/mv_udc.c
deleted file mode 100644
index e6700a80fd..0000000000
--- a/drivers/usb/gadget/mv_udc.c
+++ /dev/null
@@ -1,716 +0,0 @@
-/*
- * Copyright 2011, Marvell Semiconductor Inc.
- * Lei Wen <leiwen@marvell.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- *
- * Back ported to the 8xx platform (from the 8260 platform) by
- * Murray.Jensen@cmst.csiro.au, 27-Jan-01.
- */
-
-#include <common.h>
-#include <command.h>
-#include <config.h>
-#include <net.h>
-#include <malloc.h>
-#include <asm/io.h>
-#include <linux/types.h>
-#include <usb/mv_udc.h>
-
-#if CONFIG_USB_MAX_CONTROLLER_COUNT > 1
-#error This driver only supports one single controller.
-#endif
-
-/*
- * Check if the system has too long cachelines. If the cachelines are
- * longer then 128b, the driver will not be able flush/invalidate data
- * cache over separate QH entries. We use 128b because one QH entry is
- * 64b long and there are always two QH list entries for each endpoint.
- */
-#if ARCH_DMA_MINALIGN > 128
-#error This driver can not work on systems with caches longer than 128b
-#endif
-
-#ifndef DEBUG
-#define DBG(x...) do {} while (0)
-#else
-#define DBG(x...) printf(x)
-static const char *reqname(unsigned r)
-{
-	switch (r) {
-	case USB_REQ_GET_STATUS: return "GET_STATUS";
-	case USB_REQ_CLEAR_FEATURE: return "CLEAR_FEATURE";
-	case USB_REQ_SET_FEATURE: return "SET_FEATURE";
-	case USB_REQ_SET_ADDRESS: return "SET_ADDRESS";
-	case USB_REQ_GET_DESCRIPTOR: return "GET_DESCRIPTOR";
-	case USB_REQ_SET_DESCRIPTOR: return "SET_DESCRIPTOR";
-	case USB_REQ_GET_CONFIGURATION: return "GET_CONFIGURATION";
-	case USB_REQ_SET_CONFIGURATION: return "SET_CONFIGURATION";
-	case USB_REQ_GET_INTERFACE: return "GET_INTERFACE";
-	case USB_REQ_SET_INTERFACE: return "SET_INTERFACE";
-	default: return "*UNKNOWN*";
-	}
-}
-#endif
-
-static struct usb_endpoint_descriptor ep0_out_desc = {
-	.bLength = sizeof(struct usb_endpoint_descriptor),
-	.bDescriptorType = USB_DT_ENDPOINT,
-	.bEndpointAddress = 0,
-	.bmAttributes =	USB_ENDPOINT_XFER_CONTROL,
-};
-
-static struct usb_endpoint_descriptor ep0_in_desc = {
-	.bLength = sizeof(struct usb_endpoint_descriptor),
-	.bDescriptorType = USB_DT_ENDPOINT,
-	.bEndpointAddress = USB_DIR_IN,
-	.bmAttributes =	USB_ENDPOINT_XFER_CONTROL,
-};
-
-static int mv_pullup(struct usb_gadget *gadget, int is_on);
-static int mv_ep_enable(struct usb_ep *ep,
-		const struct usb_endpoint_descriptor *desc);
-static int mv_ep_disable(struct usb_ep *ep);
-static int mv_ep_queue(struct usb_ep *ep,
-		struct usb_request *req, gfp_t gfp_flags);
-static struct usb_request *
-mv_ep_alloc_request(struct usb_ep *ep, unsigned int gfp_flags);
-static void mv_ep_free_request(struct usb_ep *ep, struct usb_request *_req);
-
-static struct usb_gadget_ops mv_udc_ops = {
-	.pullup = mv_pullup,
-};
-
-static struct usb_ep_ops mv_ep_ops = {
-	.enable         = mv_ep_enable,
-	.disable        = mv_ep_disable,
-	.queue          = mv_ep_queue,
-	.alloc_request  = mv_ep_alloc_request,
-	.free_request   = mv_ep_free_request,
-};
-
-/* Init values for USB endpoints. */
-static const struct usb_ep mv_ep_init[2] = {
-	[0] = {	/* EP 0 */
-		.maxpacket	= 64,
-		.name		= "ep0",
-		.ops		= &mv_ep_ops,
-	},
-	[1] = {	/* EP 1..n */
-		.maxpacket	= 512,
-		.name		= "ep-",
-		.ops		= &mv_ep_ops,
-	},
-};
-
-static struct mv_drv controller = {
-	.gadget	= {
-		.name	= "mv_udc",
-		.ops	= &mv_udc_ops,
-	},
-};
-
-/**
- * mv_get_qh() - return queue head for endpoint
- * @ep_num:	Endpoint number
- * @dir_in:	Direction of the endpoint (IN = 1, OUT = 0)
- *
- * This function returns the QH associated with particular endpoint
- * and it's direction.
- */
-static struct ept_queue_head *mv_get_qh(int ep_num, int dir_in)
-{
-	return &controller.epts[(ep_num * 2) + dir_in];
-}
-
-/**
- * mv_get_qtd() - return queue item for endpoint
- * @ep_num:	Endpoint number
- * @dir_in:	Direction of the endpoint (IN = 1, OUT = 0)
- *
- * This function returns the QH associated with particular endpoint
- * and it's direction.
- */
-static struct ept_queue_item *mv_get_qtd(int ep_num, int dir_in)
-{
-	return controller.items[(ep_num * 2) + dir_in];
-}
-
-/**
- * mv_flush_qh - flush cache over queue head
- * @ep_num:	Endpoint number
- *
- * This function flushes cache over QH for particular endpoint.
- */
-static void mv_flush_qh(int ep_num)
-{
-	struct ept_queue_head *head = mv_get_qh(ep_num, 0);
-	const uint32_t start = (uint32_t)head;
-	const uint32_t end = start + 2 * sizeof(*head);
-
-	flush_dcache_range(start, end);
-}
-
-/**
- * mv_invalidate_qh - invalidate cache over queue head
- * @ep_num:	Endpoint number
- *
- * This function invalidates cache over QH for particular endpoint.
- */
-static void mv_invalidate_qh(int ep_num)
-{
-	struct ept_queue_head *head = mv_get_qh(ep_num, 0);
-	uint32_t start = (uint32_t)head;
-	uint32_t end = start + 2 * sizeof(*head);
-
-	invalidate_dcache_range(start, end);
-}
-
-/**
- * mv_flush_qtd - flush cache over queue item
- * @ep_num:	Endpoint number
- *
- * This function flushes cache over qTD pair for particular endpoint.
- */
-static void mv_flush_qtd(int ep_num)
-{
-	struct ept_queue_item *item = mv_get_qtd(ep_num, 0);
-	const uint32_t start = (uint32_t)item;
-	const uint32_t end_raw = start + 2 * sizeof(*item);
-	const uint32_t end = roundup(end_raw, ARCH_DMA_MINALIGN);
-
-	flush_dcache_range(start, end);
-}
-
-/**
- * mv_invalidate_qtd - invalidate cache over queue item
- * @ep_num:	Endpoint number
- *
- * This function invalidates cache over qTD pair for particular endpoint.
- */
-static void mv_invalidate_qtd(int ep_num)
-{
-	struct ept_queue_item *item = mv_get_qtd(ep_num, 0);
-	const uint32_t start = (uint32_t)item;
-	const uint32_t end_raw = start + 2 * sizeof(*item);
-	const uint32_t end = roundup(end_raw, ARCH_DMA_MINALIGN);
-
-	invalidate_dcache_range(start, end);
-}
-
-static struct usb_request *
-mv_ep_alloc_request(struct usb_ep *ep, unsigned int gfp_flags)
-{
-	struct mv_ep *mv_ep = container_of(ep, struct mv_ep, ep);
-	return &mv_ep->req;
-}
-
-static void mv_ep_free_request(struct usb_ep *ep, struct usb_request *_req)
-{
-	return;
-}
-
-static void ep_enable(int num, int in)
-{
-	struct ept_queue_head *head;
-	struct mv_udc *udc = (struct mv_udc *)controller.ctrl->hcor;
-	unsigned n;
-	head = mv_get_qh(num, in);
-
-	n = readl(&udc->epctrl[num]);
-	if (in)
-		n |= (CTRL_TXE | CTRL_TXR | CTRL_TXT_BULK);
-	else
-		n |= (CTRL_RXE | CTRL_RXR | CTRL_RXT_BULK);
-
-	if (num != 0) {
-		head->config = CONFIG_MAX_PKT(EP_MAX_PACKET_SIZE) | CONFIG_ZLT;
-		mv_flush_qh(num);
-	}
-	writel(n, &udc->epctrl[num]);
-}
-
-static int mv_ep_enable(struct usb_ep *ep,
-		const struct usb_endpoint_descriptor *desc)
-{
-	struct mv_ep *mv_ep = container_of(ep, struct mv_ep, ep);
-	int num, in;
-	num = desc->bEndpointAddress & USB_ENDPOINT_NUMBER_MASK;
-	in = (desc->bEndpointAddress & USB_DIR_IN) != 0;
-	ep_enable(num, in);
-	mv_ep->desc = desc;
-	return 0;
-}
-
-static int mv_ep_disable(struct usb_ep *ep)
-{
-	return 0;
-}
-
-static int mv_bounce(struct mv_ep *ep)
-{
-	uint32_t addr = (uint32_t)ep->req.buf;
-	uint32_t ba;
-
-	/* Input buffer address is not aligned. */
-	if (addr & (ARCH_DMA_MINALIGN - 1))
-		goto align;
-
-	/* Input buffer length is not aligned. */
-	if (ep->req.length & (ARCH_DMA_MINALIGN - 1))
-		goto align;
-
-	/* The buffer is well aligned, only flush cache. */
-	ep->b_len = ep->req.length;
-	ep->b_buf = ep->req.buf;
-	goto flush;
-
-align:
-	/* Use internal buffer for small payloads. */
-	if (ep->req.length <= 64) {
-		ep->b_len = 64;
-		ep->b_buf = ep->b_fast;
-	} else {
-		ep->b_len = roundup(ep->req.length, ARCH_DMA_MINALIGN);
-		ep->b_buf = memalign(ARCH_DMA_MINALIGN, ep->b_len);
-		if (!ep->b_buf)
-			return -ENOMEM;
-	}
-
-	memcpy(ep->b_buf, ep->req.buf, ep->req.length);
-
-flush:
-	ba = (uint32_t)ep->b_buf;
-	flush_dcache_range(ba, ba + ep->b_len);
-
-	return 0;
-}
-
-static void mv_debounce(struct mv_ep *ep)
-{
-	uint32_t addr = (uint32_t)ep->req.buf;
-	uint32_t ba = (uint32_t)ep->b_buf;
-
-	invalidate_dcache_range(ba, ba + ep->b_len);
-
-	/* Input buffer address is not aligned. */
-	if (addr & (ARCH_DMA_MINALIGN - 1))
-		goto copy;
-
-	/* Input buffer length is not aligned. */
-	if (ep->req.length & (ARCH_DMA_MINALIGN - 1))
-		goto copy;
-
-	/* The buffer is well aligned, only invalidate cache. */
-	return;
-
-copy:
-	memcpy(ep->req.buf, ep->b_buf, ep->req.length);
-
-	/* Large payloads use allocated buffer, free it. */
-	if (ep->req.length > 64)
-		free(ep->b_buf);
-}
-
-static int mv_ep_queue(struct usb_ep *ep,
-		struct usb_request *req, gfp_t gfp_flags)
-{
-	struct mv_ep *mv_ep = container_of(ep, struct mv_ep, ep);
-	struct mv_udc *udc = (struct mv_udc *)controller.ctrl->hcor;
-	struct ept_queue_item *item;
-	struct ept_queue_head *head;
-	int bit, num, len, in, ret;
-	num = mv_ep->desc->bEndpointAddress & USB_ENDPOINT_NUMBER_MASK;
-	in = (mv_ep->desc->bEndpointAddress & USB_DIR_IN) != 0;
-	item = mv_get_qtd(num, in);
-	head = mv_get_qh(num, in);
-	len = req->length;
-
-	ret = mv_bounce(mv_ep);
-	if (ret)
-		return ret;
-
-	item->next = TERMINATE;
-	item->info = INFO_BYTES(len) | INFO_IOC | INFO_ACTIVE;
-	item->page0 = (uint32_t)mv_ep->b_buf;
-	item->page1 = ((uint32_t)mv_ep->b_buf & 0xfffff000) + 0x1000;
-
-	head->next = (unsigned) item;
-	head->info = 0;
-
-	DBG("ept%d %s queue len %x, buffer %p\n",
-	    num, in ? "in" : "out", len, mv_ep->b_buf);
-
-	if (in)
-		bit = EPT_TX(num);
-	else
-		bit = EPT_RX(num);
-
-	mv_flush_qh(num);
-	mv_flush_qtd(num);
-
-	writel(bit, &udc->epprime);
-
-	return 0;
-}
-
-static void handle_ep_complete(struct mv_ep *ep)
-{
-	struct ept_queue_item *item;
-	int num, in, len;
-	num = ep->desc->bEndpointAddress & USB_ENDPOINT_NUMBER_MASK;
-	in = (ep->desc->bEndpointAddress & USB_DIR_IN) != 0;
-	if (num == 0)
-		ep->desc = &ep0_out_desc;
-	item = mv_get_qtd(num, in);
-	mv_invalidate_qtd(num);
-
-	if (item->info & 0xff)
-		printf("EP%d/%s FAIL nfo=%x pg0=%x\n",
-			num, in ? "in" : "out", item->info, item->page0);
-
-	len = (item->info >> 16) & 0x7fff;
-
-	mv_debounce(ep);
-
-	ep->req.length -= len;
-	DBG("ept%d %s complete %x\n",
-			num, in ? "in" : "out", len);
-	ep->req.complete(&ep->ep, &ep->req);
-	if (num == 0) {
-		ep->req.length = 0;
-		usb_ep_queue(&ep->ep, &ep->req, 0);
-		ep->desc = &ep0_in_desc;
-	}
-}
-
-#define SETUP(type, request) (((type) << 8) | (request))
-
-static void handle_setup(void)
-{
-	struct usb_request *req = &controller.ep[0].req;
-	struct mv_udc *udc = (struct mv_udc *)controller.ctrl->hcor;
-	struct ept_queue_head *head;
-	struct usb_ctrlrequest r;
-	int status = 0;
-	int num, in, _num, _in, i;
-	char *buf;
-	head = mv_get_qh(0, 0);	/* EP0 OUT */
-
-	mv_invalidate_qh(0);
-	memcpy(&r, head->setup_data, sizeof(struct usb_ctrlrequest));
-	writel(EPT_RX(0), &udc->epstat);
-	DBG("handle setup %s, %x, %x index %x value %x\n", reqname(r.bRequest),
-	    r.bRequestType, r.bRequest, r.wIndex, r.wValue);
-
-	switch (SETUP(r.bRequestType, r.bRequest)) {
-	case SETUP(USB_RECIP_ENDPOINT, USB_REQ_CLEAR_FEATURE):
-		_num = r.wIndex & 15;
-		_in = !!(r.wIndex & 0x80);
-
-		if ((r.wValue == 0) && (r.wLength == 0)) {
-			req->length = 0;
-			for (i = 0; i < NUM_ENDPOINTS; i++) {
-				if (!controller.ep[i].desc)
-					continue;
-				num = controller.ep[i].desc->bEndpointAddress
-						& USB_ENDPOINT_NUMBER_MASK;
-				in = (controller.ep[i].desc->bEndpointAddress
-						& USB_DIR_IN) != 0;
-				if ((num == _num) && (in == _in)) {
-					ep_enable(num, in);
-					usb_ep_queue(controller.gadget.ep0,
-							req, 0);
-					break;
-				}
-			}
-		}
-		return;
-
-	case SETUP(USB_RECIP_DEVICE, USB_REQ_SET_ADDRESS):
-		/*
-		 * write address delayed (will take effect
-		 * after the next IN txn)
-		 */
-		writel((r.wValue << 25) | (1 << 24), &udc->devaddr);
-		req->length = 0;
-		usb_ep_queue(controller.gadget.ep0, req, 0);
-		return;
-
-	case SETUP(USB_DIR_IN | USB_RECIP_DEVICE, USB_REQ_GET_STATUS):
-		req->length = 2;
-		buf = (char *)req->buf;
-		buf[0] = 1 << USB_DEVICE_SELF_POWERED;
-		buf[1] = 0;
-		usb_ep_queue(controller.gadget.ep0, req, 0);
-		return;
-	}
-	/* pass request up to the gadget driver */
-	if (controller.driver)
-		status = controller.driver->setup(&controller.gadget, &r);
-	else
-		status = -ENODEV;
-
-	if (!status)
-		return;
-	DBG("STALL reqname %s type %x value %x, index %x\n",
-	    reqname(r.bRequest), r.bRequestType, r.wValue, r.wIndex);
-	writel((1<<16) | (1 << 0), &udc->epctrl[0]);
-}
-
-static void stop_activity(void)
-{
-	int i, num, in;
-	struct ept_queue_head *head;
-	struct mv_udc *udc = (struct mv_udc *)controller.ctrl->hcor;
-	writel(readl(&udc->epcomp), &udc->epcomp);
-	writel(readl(&udc->epstat), &udc->epstat);
-	writel(0xffffffff, &udc->epflush);
-
-	/* error out any pending reqs */
-	for (i = 0; i < NUM_ENDPOINTS; i++) {
-		if (i != 0)
-			writel(0, &udc->epctrl[i]);
-		if (controller.ep[i].desc) {
-			num = controller.ep[i].desc->bEndpointAddress
-				& USB_ENDPOINT_NUMBER_MASK;
-			in = (controller.ep[i].desc->bEndpointAddress
-				& USB_DIR_IN) != 0;
-			head = mv_get_qh(num, in);
-			head->info = INFO_ACTIVE;
-			mv_flush_qh(num);
-		}
-	}
-}
-
-void udc_irq(void)
-{
-	struct mv_udc *udc = (struct mv_udc *)controller.ctrl->hcor;
-	unsigned n = readl(&udc->usbsts);
-	writel(n, &udc->usbsts);
-	int bit, i, num, in;
-
-	n &= (STS_SLI | STS_URI | STS_PCI | STS_UI | STS_UEI);
-	if (n == 0)
-		return;
-
-	if (n & STS_URI) {
-		DBG("-- reset --\n");
-		stop_activity();
-	}
-	if (n & STS_SLI)
-		DBG("-- suspend --\n");
-
-	if (n & STS_PCI) {
-		DBG("-- portchange --\n");
-		bit = (readl(&udc->portsc) >> 26) & 3;
-		if (bit == 2) {
-			controller.gadget.speed = USB_SPEED_HIGH;
-			for (i = 1; i < NUM_ENDPOINTS && n; i++)
-				if (controller.ep[i].desc)
-					controller.ep[i].ep.maxpacket = 512;
-		} else {
-			controller.gadget.speed = USB_SPEED_FULL;
-		}
-	}
-
-	if (n & STS_UEI)
-		printf("<UEI %x>\n", readl(&udc->epcomp));
-
-	if ((n & STS_UI) || (n & STS_UEI)) {
-		n = readl(&udc->epstat);
-		if (n & EPT_RX(0))
-			handle_setup();
-
-		n = readl(&udc->epcomp);
-		if (n != 0)
-			writel(n, &udc->epcomp);
-
-		for (i = 0; i < NUM_ENDPOINTS && n; i++) {
-			if (controller.ep[i].desc) {
-				num = controller.ep[i].desc->bEndpointAddress
-					& USB_ENDPOINT_NUMBER_MASK;
-				in = (controller.ep[i].desc->bEndpointAddress
-						& USB_DIR_IN) != 0;
-				bit = (in) ? EPT_TX(num) : EPT_RX(num);
-				if (n & bit)
-					handle_ep_complete(&controller.ep[i]);
-			}
-		}
-	}
-}
-
-int usb_gadget_handle_interrupts(void)
-{
-	u32 value;
-	struct mv_udc *udc = (struct mv_udc *)controller.ctrl->hcor;
-
-	value = readl(&udc->usbsts);
-	if (value)
-		udc_irq();
-
-	return value;
-}
-
-static int mv_pullup(struct usb_gadget *gadget, int is_on)
-{
-	struct mv_udc *udc = (struct mv_udc *)controller.ctrl->hcor;
-	if (is_on) {
-		/* RESET */
-		writel(USBCMD_ITC(MICRO_8FRAME) | USBCMD_RST, &udc->usbcmd);
-		udelay(200);
-
-		writel((unsigned)controller.epts, &udc->epinitaddr);
-
-		/* select DEVICE mode */
-		writel(USBMODE_DEVICE, &udc->usbmode);
-
-		writel(0xffffffff, &udc->epflush);
-
-		/* Turn on the USB connection by enabling the pullup resistor */
-		writel(USBCMD_ITC(MICRO_8FRAME) | USBCMD_RUN, &udc->usbcmd);
-	} else {
-		stop_activity();
-		writel(USBCMD_FS2, &udc->usbcmd);
-		udelay(800);
-		if (controller.driver)
-			controller.driver->disconnect(gadget);
-	}
-
-	return 0;
-}
-
-void udc_disconnect(void)
-{
-	struct mv_udc *udc = (struct mv_udc *)controller.ctrl->hcor;
-	/* disable pullup */
-	stop_activity();
-	writel(USBCMD_FS2, &udc->usbcmd);
-	udelay(800);
-	if (controller.driver)
-		controller.driver->disconnect(&controller.gadget);
-}
-
-static int mvudc_probe(void)
-{
-	struct ept_queue_head *head;
-	uint8_t *imem;
-	int i;
-
-	const int num = 2 * NUM_ENDPOINTS;
-
-	const int eplist_min_align = 4096;
-	const int eplist_align = roundup(eplist_min_align, ARCH_DMA_MINALIGN);
-	const int eplist_raw_sz = num * sizeof(struct ept_queue_head);
-	const int eplist_sz = roundup(eplist_raw_sz, ARCH_DMA_MINALIGN);
-
-	const int ilist_align = roundup(ARCH_DMA_MINALIGN, 32);
-	const int ilist_ent_raw_sz = 2 * sizeof(struct ept_queue_item);
-	const int ilist_ent_sz = roundup(ilist_ent_raw_sz, ARCH_DMA_MINALIGN);
-	const int ilist_sz = NUM_ENDPOINTS * ilist_ent_sz;
-
-	/* The QH list must be aligned to 4096 bytes. */
-	controller.epts = memalign(eplist_align, eplist_sz);
-	if (!controller.epts)
-		return -ENOMEM;
-	memset(controller.epts, 0, eplist_sz);
-
-	/*
-	 * Each qTD item must be 32-byte aligned, each qTD touple must be
-	 * cacheline aligned. There are two qTD items for each endpoint and
-	 * only one of them is used for the endpoint at time, so we can group
-	 * them together.
-	 */
-	controller.items_mem = memalign(ilist_align, ilist_sz);
-	if (!controller.items_mem) {
-		free(controller.epts);
-		return -ENOMEM;
-	}
-
-	for (i = 0; i < 2 * NUM_ENDPOINTS; i++) {
-		/*
-		 * Configure QH for each endpoint. The structure of the QH list
-		 * is such that each two subsequent fields, N and N+1 where N is
-		 * even, in the QH list represent QH for one endpoint. The Nth
-		 * entry represents OUT configuration and the N+1th entry does
-		 * represent IN configuration of the endpoint.
-		 */
-		head = controller.epts + i;
-		if (i < 2)
-			head->config = CONFIG_MAX_PKT(EP0_MAX_PACKET_SIZE)
-				| CONFIG_ZLT | CONFIG_IOS;
-		else
-			head->config = CONFIG_MAX_PKT(EP_MAX_PACKET_SIZE)
-				| CONFIG_ZLT;
-		head->next = TERMINATE;
-		head->info = 0;
-
-		imem = controller.items_mem + ((i >> 1) * ilist_ent_sz);
-		if (i & 1)
-			imem += sizeof(struct ept_queue_item);
-
-		controller.items[i] = (struct ept_queue_item *)imem;
-
-		if (i & 1) {
-			mv_flush_qh(i - 1);
-			mv_flush_qtd(i - 1);
-		}
-	}
-
-	INIT_LIST_HEAD(&controller.gadget.ep_list);
-
-	/* Init EP 0 */
-	memcpy(&controller.ep[0].ep, &mv_ep_init[0], sizeof(*mv_ep_init));
-	controller.ep[0].desc = &ep0_in_desc;
-	controller.gadget.ep0 = &controller.ep[0].ep;
-	INIT_LIST_HEAD(&controller.gadget.ep0->ep_list);
-
-	/* Init EP 1..n */
-	for (i = 1; i < NUM_ENDPOINTS; i++) {
-		memcpy(&controller.ep[i].ep, &mv_ep_init[1],
-		       sizeof(*mv_ep_init));
-		list_add_tail(&controller.ep[i].ep.ep_list,
-			      &controller.gadget.ep_list);
-	}
-
-	return 0;
-}
-
-int usb_gadget_register_driver(struct usb_gadget_driver *driver)
-{
-	struct mv_udc *udc;
-	int ret;
-
-	if (!driver)
-		return -EINVAL;
-	if (!driver->bind || !driver->setup || !driver->disconnect)
-		return -EINVAL;
-	if (driver->speed != USB_SPEED_FULL && driver->speed != USB_SPEED_HIGH)
-		return -EINVAL;
-
-	ret = usb_lowlevel_init(0, (void **)&controller.ctrl);
-	if (ret)
-		return ret;
-
-	ret = mvudc_probe();
-	if (!ret) {
-		udc = (struct mv_udc *)controller.ctrl->hcor;
-
-		/* select ULPI phy */
-		writel(PTS(PTS_ENABLE) | PFSC, &udc->portsc);
-	}
-
-	ret = driver->bind(&controller.gadget);
-	if (ret) {
-		DBG("driver->bind() returned %d\n", ret);
-		return ret;
-	}
-	controller.driver = driver;
-
-	return 0;
-}
-
-int usb_gadget_unregister_driver(struct usb_gadget_driver *driver)
-{
-	return 0;
-}
diff --git a/drivers/usb/gadget/omap1510_udc.c b/drivers/usb/gadget/omap1510_udc.c
index 8553fe5396..bdc1b886f5 100644
--- a/drivers/usb/gadget/omap1510_udc.c
+++ b/drivers/usb/gadget/omap1510_udc.c
@@ -20,6 +20,7 @@
 #endif
 #include <usbdevice.h>
 #include <usb/omap1510_udc.h>
+#include <usb/udc.h>
 
 #include "ep0.h"
 
diff --git a/drivers/usb/gadget/pxa27x_udc.c b/drivers/usb/gadget/pxa27x_udc.c
index 05d1b56667..733558def7 100644
--- a/drivers/usb/gadget/pxa27x_udc.c
+++ b/drivers/usb/gadget/pxa27x_udc.c
@@ -16,6 +16,7 @@
 #include <asm/arch/hardware.h>
 #include <asm/io.h>
 #include <usb/pxa27x_udc.h>
+#include <usb/udc.h>
 
 #include "ep0.h"
 
diff --git a/drivers/usb/gadget/regs-otg.h b/drivers/usb/gadget/regs-otg.h
index 84bfcc5a01..ac5d11213d 100644
--- a/drivers/usb/gadget/regs-otg.h
+++ b/drivers/usb/gadget/regs-otg.h
@@ -226,6 +226,11 @@ struct s3c_usbotg_reg {
 #define CLK_SEL_12MHZ                   (0x2 << 0)
 #define CLK_SEL_48MHZ                   (0x0 << 0)
 
+#define EXYNOS4X12_ID_PULLUP0		(0x01 << 3)
+#define EXYNOS4X12_COMMON_ON_N0	(0x01 << 4)
+#define EXYNOS4X12_CLK_SEL_12MHZ	(0x02 << 0)
+#define EXYNOS4X12_CLK_SEL_24MHZ	(0x05 << 0)
+
 /* Device Configuration Register DCFG */
 #define DEV_SPEED_HIGH_SPEED_20         (0x0 << 0)
 #define DEV_SPEED_FULL_SPEED_20         (0x1 << 0)
diff --git a/drivers/usb/gadget/s3c_udc_otg.c b/drivers/usb/gadget/s3c_udc_otg.c
index 7e2020915e..63d4487a9b 100644
--- a/drivers/usb/gadget/s3c_udc_otg.c
+++ b/drivers/usb/gadget/s3c_udc_otg.c
@@ -167,8 +167,13 @@ void otg_phy_init(struct s3c_udc *dev)
 		writel((readl(&phy->phypwr) &~(OTG_DISABLE_0 | ANALOG_PWRDOWN)
 			&~FORCE_SUSPEND_0), &phy->phypwr);
 
-	writel((readl(&phy->phyclk) &~(ID_PULLUP0 | COMMON_ON_N0)) |
-	       CLK_SEL_24MHZ, &phy->phyclk); /* PLL 24Mhz */
+	if (s5p_cpu_id == 0x4412)
+		writel((readl(&phy->phyclk) & ~(EXYNOS4X12_ID_PULLUP0 |
+			EXYNOS4X12_COMMON_ON_N0)) | EXYNOS4X12_CLK_SEL_24MHZ,
+		       &phy->phyclk); /* PLL 24Mhz */
+	else
+		writel((readl(&phy->phyclk) & ~(ID_PULLUP0 | COMMON_ON_N0)) |
+		       CLK_SEL_24MHZ, &phy->phyclk); /* PLL 24Mhz */
 
 	writel((readl(&phy->rstcon) &~(LINK_SW_RST | PHYLNK_SW_RST))
 	       | PHY_SW_RST0, &phy->rstcon);
@@ -838,7 +843,7 @@ static struct s3c_udc memory = {
 int s3c_udc_probe(struct s3c_plat_otg_data *pdata)
 {
 	struct s3c_udc *dev = &memory;
-	int retval = 0, i;
+	int retval = 0;
 
 	debug("%s: %p\n", __func__, pdata);
 
@@ -859,16 +864,15 @@ int s3c_udc_probe(struct s3c_plat_otg_data *pdata)
 
 	the_controller = dev;
 
-	for (i = 0; i < S3C_MAX_ENDPOINTS+1; i++) {
-		dev->dma_buf[i] = memalign(CONFIG_SYS_CACHELINE_SIZE,
-					   DMA_BUFFER_SIZE);
-		dev->dma_addr[i] = (dma_addr_t) dev->dma_buf[i];
-		invalidate_dcache_range((unsigned long) dev->dma_buf[i],
-					(unsigned long) (dev->dma_buf[i]
-							 + DMA_BUFFER_SIZE));
+	usb_ctrl = memalign(CONFIG_SYS_CACHELINE_SIZE,
+			    ROUND(sizeof(struct usb_ctrlrequest),
+				  CONFIG_SYS_CACHELINE_SIZE));
+	if (!usb_ctrl) {
+		error("No memory available for UDC!\n");
+		return -ENOMEM;
 	}
-	usb_ctrl = dev->dma_buf[0];
-	usb_ctrl_dma_addr = dev->dma_addr[0];
+
+	usb_ctrl_dma_addr = (dma_addr_t) usb_ctrl;
 
 	udc_reinit(dev);
 
diff --git a/drivers/usb/gadget/s3c_udc_otg_xfer_dma.c b/drivers/usb/gadget/s3c_udc_otg_xfer_dma.c
index d7af5e9034..06dfeed905 100644
--- a/drivers/usb/gadget/s3c_udc_otg_xfer_dma.c
+++ b/drivers/usb/gadget/s3c_udc_otg_xfer_dma.c
@@ -29,10 +29,6 @@ static inline void s3c_udc_ep0_zlp(struct s3c_udc *dev)
 {
 	u32 ep_ctrl;
 
-	flush_dcache_range((unsigned long) usb_ctrl_dma_addr,
-			   (unsigned long) usb_ctrl_dma_addr
-			   + DMA_BUFFER_SIZE);
-
 	writel(usb_ctrl_dma_addr, &reg->in_endp[EP0_CON].diepdma);
 	writel(DIEPT_SIZ_PKT_CNT(1), &reg->in_endp[EP0_CON].dieptsiz);
 
@@ -52,10 +48,6 @@ void s3c_udc_pre_setup(void)
 	debug_cond(DEBUG_IN_EP,
 		   "%s : Prepare Setup packets.\n", __func__);
 
-	invalidate_dcache_range((unsigned long) usb_ctrl_dma_addr,
-				(unsigned long) usb_ctrl_dma_addr
-				+ DMA_BUFFER_SIZE);
-
 	writel(DOEPT_SIZ_PKT_CNT(1) | sizeof(struct usb_ctrlrequest),
 	       &reg->out_endp[EP0_CON].doeptsiz);
 	writel(usb_ctrl_dma_addr, &reg->out_endp[EP0_CON].doepdma);
@@ -82,10 +74,6 @@ static inline void s3c_ep0_complete_out(void)
 	debug_cond(DEBUG_IN_EP,
 		"%s : Prepare Complete Out packet.\n", __func__);
 
-	invalidate_dcache_range((unsigned long) usb_ctrl_dma_addr,
-				(unsigned long) usb_ctrl_dma_addr
-				+ DMA_BUFFER_SIZE);
-
 	writel(DOEPT_SIZ_PKT_CNT(1) | sizeof(struct usb_ctrlrequest),
 	       &reg->out_endp[EP0_CON].doeptsiz);
 	writel(usb_ctrl_dma_addr, &reg->out_endp[EP0_CON].doepdma);
@@ -109,26 +97,20 @@ static int setdma_rx(struct s3c_ep *ep, struct s3c_request *req)
 	u32 ep_num = ep_index(ep);
 
 	buf = req->req.buf + req->req.actual;
-
-	length = min(req->req.length - req->req.actual, (int)ep->ep.maxpacket);
+	length = min(req->req.length - req->req.actual,
+		     ep_num ? DMA_BUFFER_SIZE : ep->ep.maxpacket);
 
 	ep->len = length;
 	ep->dma_buf = buf;
 
-	invalidate_dcache_range((unsigned long) ep->dev->dma_buf[ep_num],
-				(unsigned long) ep->dev->dma_buf[ep_num]
-				+ DMA_BUFFER_SIZE);
-
-	if (length == 0)
+	if (ep_num == EP0_CON || length == 0)
 		pktcnt = 1;
 	else
 		pktcnt = (length - 1)/(ep->ep.maxpacket) + 1;
 
-	pktcnt = 1;
 	ctrl =  readl(&reg->out_endp[ep_num].doepctl);
 
-	writel(the_controller->dma_addr[ep_index(ep)+1],
-	       &reg->out_endp[ep_num].doepdma);
+	writel((unsigned int) ep->dma_buf, &reg->out_endp[ep_num].doepdma);
 	writel(DOEPT_SIZ_PKT_CNT(pktcnt) | DOEPT_SIZ_XFER_SIZE(length),
 	       &reg->out_endp[ep_num].doeptsiz);
 	writel(DEPCTL_EPENA|DEPCTL_CNAK|ctrl, &reg->out_endp[ep_num].doepctl);
@@ -151,7 +133,6 @@ int setdma_tx(struct s3c_ep *ep, struct s3c_request *req)
 	u32 *buf, ctrl = 0;
 	u32 length, pktcnt;
 	u32 ep_num = ep_index(ep);
-	u32 *p = the_controller->dma_buf[ep_index(ep)+1];
 
 	buf = req->req.buf + req->req.actual;
 	length = req->req.length - req->req.actual;
@@ -161,10 +142,10 @@ int setdma_tx(struct s3c_ep *ep, struct s3c_request *req)
 
 	ep->len = length;
 	ep->dma_buf = buf;
-	memcpy(p, ep->dma_buf, length);
 
-	flush_dcache_range((unsigned long) p ,
-			   (unsigned long) p + DMA_BUFFER_SIZE);
+	flush_dcache_range((unsigned long) ep->dma_buf,
+			   (unsigned long) ep->dma_buf +
+			   ROUND(ep->len, CONFIG_SYS_CACHELINE_SIZE));
 
 	if (length == 0)
 		pktcnt = 1;
@@ -177,8 +158,7 @@ int setdma_tx(struct s3c_ep *ep, struct s3c_request *req)
 	while (readl(&reg->grstctl) & TX_FIFO_FLUSH)
 		;
 
-	writel(the_controller->dma_addr[ep_index(ep)+1],
-	       &reg->in_endp[ep_num].diepdma);
+	writel((unsigned long) ep->dma_buf, &reg->in_endp[ep_num].diepdma);
 	writel(DIEPT_SIZ_PKT_CNT(pktcnt) | DIEPT_SIZ_XFER_SIZE(length),
 	       &reg->in_endp[ep_num].dieptsiz);
 
@@ -211,7 +191,6 @@ static void complete_rx(struct s3c_udc *dev, u8 ep_num)
 	struct s3c_ep *ep = &dev->ep[ep_num];
 	struct s3c_request *req = NULL;
 	u32 ep_tsr = 0, xfer_size = 0, is_short = 0;
-	u32 *p = the_controller->dma_buf[ep_index(ep)+1];
 
 	if (list_empty(&ep->queue)) {
 		debug_cond(DEBUG_OUT_EP != 0,
@@ -231,10 +210,23 @@ static void complete_rx(struct s3c_udc *dev, u8 ep_num)
 
 	xfer_size = ep->len - xfer_size;
 
-	invalidate_dcache_range((unsigned long) p,
-				(unsigned long) p + DMA_BUFFER_SIZE);
-
-	memcpy(ep->dma_buf, p, ep->len);
+	/*
+	 * NOTE:
+	 *
+	 * Please be careful with proper buffer allocation for USB request,
+	 * which needs to be aligned to CONFIG_SYS_CACHELINE_SIZE, not only
+	 * with starting address, but also its size shall be a cache line
+	 * multiplication.
+	 *
+	 * This will prevent from corruption of data allocated immediatelly
+	 * before or after the buffer.
+	 *
+	 * For armv7, the cache_v7.c provides proper code to emit "ERROR"
+	 * message to warn users.
+	 */
+	invalidate_dcache_range((unsigned long) ep->dma_buf,
+				(unsigned long) ep->dma_buf +
+				ROUND(xfer_size, CONFIG_SYS_CACHELINE_SIZE));
 
 	req->req.actual += min(xfer_size, req->req.length - req->req.actual);
 	is_short = (xfer_size < ep->ep.maxpacket);
@@ -728,19 +720,14 @@ static int write_fifo_ep0(struct s3c_ep *ep, struct s3c_request *req)
 
 int s3c_fifo_read(struct s3c_ep *ep, u32 *cp, int max)
 {
-	u32 bytes;
-
-	bytes = sizeof(struct usb_ctrlrequest);
-
-	invalidate_dcache_range((unsigned long) ep->dev->dma_buf[ep_index(ep)],
-				(unsigned long) ep->dev->dma_buf[ep_index(ep)]
-				+ DMA_BUFFER_SIZE);
+	invalidate_dcache_range((unsigned long)cp, (unsigned long)cp +
+				ROUND(max, CONFIG_SYS_CACHELINE_SIZE));
 
 	debug_cond(DEBUG_EP0 != 0,
-		   "%s: bytes=%d, ep_index=%d %p\n", __func__,
-		   bytes, ep_index(ep), ep->dev->dma_buf[ep_index(ep)]);
+		   "%s: bytes=%d, ep_index=%d 0x%p\n", __func__,
+		   max, ep_index(ep), cp);
 
-	return bytes;
+	return max;
 }
 
 /**
@@ -872,14 +859,12 @@ static int s3c_ep0_write(struct s3c_udc *dev)
 	return 1;
 }
 
-u16	g_status;
-
 int s3c_udc_get_status(struct s3c_udc *dev,
 		struct usb_ctrlrequest *crq)
 {
 	u8 ep_num = crq->wIndex & 0x7F;
+	u16 g_status = 0;
 	u32 ep_ctrl;
-	u32 *p = the_controller->dma_buf[1];
 
 	debug_cond(DEBUG_SETUP != 0,
 		   "%s: *** USB_REQ_GET_STATUS\n", __func__);
@@ -917,12 +902,13 @@ int s3c_udc_get_status(struct s3c_udc *dev,
 		return 1;
 	}
 
-	memcpy(p, &g_status, sizeof(g_status));
+	memcpy(usb_ctrl, &g_status, sizeof(g_status));
 
-	flush_dcache_range((unsigned long) p,
-			   (unsigned long) p + DMA_BUFFER_SIZE);
+	flush_dcache_range((unsigned long) usb_ctrl,
+			   (unsigned long) usb_ctrl +
+			   ROUND(sizeof(g_status), CONFIG_SYS_CACHELINE_SIZE));
 
-	writel(the_controller->dma_addr[1], &reg->in_endp[EP0_CON].diepdma);
+	writel(usb_ctrl_dma_addr, &reg->in_endp[EP0_CON].diepdma);
 	writel(DIEPT_SIZ_PKT_CNT(1) | DIEPT_SIZ_XFER_SIZE(2),
 	       &reg->in_endp[EP0_CON].dieptsiz);
 
diff --git a/drivers/usb/gadget/storage_common.c b/drivers/usb/gadget/storage_common.c
index 866e7c7b8a..02803df23c 100644
--- a/drivers/usb/gadget/storage_common.c
+++ b/drivers/usb/gadget/storage_common.c
@@ -275,7 +275,6 @@ struct rw_semaphore { int i; };
 #define ETOOSMALL	525
 
 #include <usb_mass_storage.h>
-extern struct ums_board_info		*ums_info;
 
 /*-------------------------------------------------------------------------*/
 
@@ -573,36 +572,16 @@ static struct usb_gadget_strings	fsg_stringtab = {
 static int fsg_lun_open(struct fsg_lun *curlun, const char *filename)
 {
 	int				ro;
-	int				rc = -EINVAL;
-	loff_t				size;
-	loff_t				num_sectors;
-	loff_t				min_sectors;
 
 	/* R/W if we can, R/O if we must */
 	ro = curlun->initially_ro;
 
-	ums_info->get_capacity(&(ums_info->ums_dev), &size);
-	if (size < 0) {
-		printf("unable to find file size: %s\n", filename);
-		rc = (int) size;
-		goto out;
-	}
-	num_sectors = size >> 9;	/* File size in 512-byte blocks */
-	min_sectors = 1;
-	if (num_sectors < min_sectors) {
-		printf("file too small: %s\n", filename);
-		rc = -ETOOSMALL;
-		goto out;
-	}
-
 	curlun->ro = ro;
-	curlun->file_length = size;
-	curlun->num_sectors = num_sectors;
+	curlun->file_length = ums->num_sectors << 9;
+	curlun->num_sectors = ums->num_sectors;
 	debug("open backing file: %s\n", filename);
-	rc = 0;
 
-out:
-	return rc;
+	return 0;
 }
 
 static void fsg_lun_close(struct fsg_lun *curlun)
diff --git a/drivers/usb/host/Makefile b/drivers/usb/host/Makefile
index ff6c80e66f..578b097fc9 100644
--- a/drivers/usb/host/Makefile
+++ b/drivers/usb/host/Makefile
@@ -5,57 +5,39 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	:= $(obj)libusb_host.o
-
 # ohci
-COBJS-$(CONFIG_USB_OHCI_NEW) += ohci-hcd.o
-COBJS-$(CONFIG_USB_ATMEL) += ohci-at91.o
-COBJS-$(CONFIG_USB_OHCI_DA8XX) += ohci-da8xx.o
-COBJS-$(CONFIG_USB_ISP116X_HCD) += isp116x-hcd.o
-COBJS-$(CONFIG_USB_R8A66597_HCD) += r8a66597-hcd.o
-COBJS-$(CONFIG_USB_SL811HS) += sl811-hcd.o
-COBJS-$(CONFIG_USB_OHCI_S3C24XX) += ohci-s3c24xx.o
+obj-$(CONFIG_USB_OHCI_NEW) += ohci-hcd.o
+obj-$(CONFIG_USB_ATMEL) += ohci-at91.o
+obj-$(CONFIG_USB_OHCI_DA8XX) += ohci-da8xx.o
+obj-$(CONFIG_USB_ISP116X_HCD) += isp116x-hcd.o
+obj-$(CONFIG_USB_R8A66597_HCD) += r8a66597-hcd.o
+obj-$(CONFIG_USB_SL811HS) += sl811-hcd.o
+obj-$(CONFIG_USB_OHCI_S3C24XX) += ohci-s3c24xx.o
 
 # echi
-COBJS-$(CONFIG_USB_EHCI) += ehci-hcd.o
-COBJS-$(CONFIG_USB_EHCI_ARMADA100) += ehci-armada100.o utmi-armada100.o
-COBJS-$(CONFIG_USB_EHCI_ATMEL) += ehci-atmel.o
+obj-$(CONFIG_USB_EHCI) += ehci-hcd.o
+obj-$(CONFIG_USB_EHCI_ARMADA100) += ehci-armada100.o utmi-armada100.o
+obj-$(CONFIG_USB_EHCI_ATMEL) += ehci-atmel.o
 ifdef CONFIG_MPC512X
-COBJS-$(CONFIG_USB_EHCI_FSL) += ehci-mpc512x.o
+obj-$(CONFIG_USB_EHCI_FSL) += ehci-mpc512x.o
 else
-COBJS-$(CONFIG_USB_EHCI_FSL) += ehci-fsl.o
+obj-$(CONFIG_USB_EHCI_FSL) += ehci-fsl.o
 endif
-COBJS-$(CONFIG_USB_EHCI_FARADAY) += ehci-faraday.o
-COBJS-$(CONFIG_USB_EHCI_EXYNOS) += ehci-exynos.o
-COBJS-$(CONFIG_USB_EHCI_MXC) += ehci-mxc.o
-COBJS-$(CONFIG_USB_EHCI_MXS) += ehci-mxs.o
-COBJS-$(CONFIG_USB_EHCI_MX5) += ehci-mx5.o
-COBJS-$(CONFIG_USB_EHCI_MX6) += ehci-mx6.o
-COBJS-$(CONFIG_USB_EHCI_OMAP) += ehci-omap.o
-COBJS-$(CONFIG_USB_EHCI_PPC4XX) += ehci-ppc4xx.o
-COBJS-$(CONFIG_USB_EHCI_IXP4XX) += ehci-ixp.o
-COBJS-$(CONFIG_USB_EHCI_MARVELL) += ehci-marvell.o
-COBJS-$(CONFIG_USB_EHCI_PCI) += ehci-pci.o
-COBJS-$(CONFIG_USB_EHCI_SPEAR) += ehci-spear.o
-COBJS-$(CONFIG_USB_EHCI_TEGRA) += ehci-tegra.o
-COBJS-$(CONFIG_USB_EHCI_VCT) += ehci-vct.o
-
-COBJS	:= $(COBJS-y)
-SRCS	:= $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-
-all:	$(LIB)
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-$(CONFIG_USB_EHCI_FARADAY) += ehci-faraday.o
+obj-$(CONFIG_USB_EHCI_EXYNOS) += ehci-exynos.o
+obj-$(CONFIG_USB_EHCI_MXC) += ehci-mxc.o
+obj-$(CONFIG_USB_EHCI_MXS) += ehci-mxs.o
+obj-$(CONFIG_USB_EHCI_MX5) += ehci-mx5.o
+obj-$(CONFIG_USB_EHCI_MX6) += ehci-mx6.o
+obj-$(CONFIG_USB_EHCI_OMAP) += ehci-omap.o
+obj-$(CONFIG_USB_EHCI_PPC4XX) += ehci-ppc4xx.o
+obj-$(CONFIG_USB_EHCI_MARVELL) += ehci-marvell.o
+obj-$(CONFIG_USB_EHCI_PCI) += ehci-pci.o
+obj-$(CONFIG_USB_EHCI_SPEAR) += ehci-spear.o
+obj-$(CONFIG_USB_EHCI_TEGRA) += ehci-tegra.o
+obj-$(CONFIG_USB_EHCI_VCT) += ehci-vct.o
+
+# xhci
+obj-$(CONFIG_USB_XHCI) += xhci.o xhci-mem.o xhci-ring.o
+obj-$(CONFIG_USB_XHCI_EXYNOS) += xhci-exynos5.o
+obj-$(CONFIG_USB_XHCI_OMAP) += xhci-omap.o
diff --git a/drivers/usb/host/ehci-armada100.c b/drivers/usb/host/ehci-armada100.c
index 636b6e5da0..012eb3a1a4 100644
--- a/drivers/usb/host/ehci-armada100.c
+++ b/drivers/usb/host/ehci-armada100.c
@@ -22,7 +22,8 @@
 /*
  * EHCI host controller init
  */
-int ehci_hcd_init(int index, struct ehci_hccr **hccr, struct ehci_hcor **hcor)
+int ehci_hcd_init(int index, enum usb_init_type init,
+		struct ehci_hccr **hccr, struct ehci_hcor **hcor)
 {
 	if (utmi_init() < 0)
 		return -1;
diff --git a/drivers/usb/host/ehci-atmel.c b/drivers/usb/host/ehci-atmel.c
index 67444b26ef..9ffe5010be 100644
--- a/drivers/usb/host/ehci-atmel.c
+++ b/drivers/usb/host/ehci-atmel.c
@@ -21,7 +21,8 @@
  */
 #define EN_UPLL_TIMEOUT	500UL
 
-int ehci_hcd_init(int index, struct ehci_hccr **hccr, struct ehci_hcor **hcor)
+int ehci_hcd_init(int index, enum usb_init_type init,
+		struct ehci_hccr **hccr, struct ehci_hcor **hcor)
 {
 	at91_pmc_t *pmc = (at91_pmc_t *)ATMEL_BASE_PMC;
 	ulong start_time, tmp_time;
diff --git a/drivers/usb/host/ehci-exynos.c b/drivers/usb/host/ehci-exynos.c
index 155677e0d9..9356878eb2 100644
--- a/drivers/usb/host/ehci-exynos.c
+++ b/drivers/usb/host/ehci-exynos.c
@@ -16,6 +16,7 @@
 #include <asm/arch/ehci.h>
 #include <asm/arch/system.h>
 #include <asm/arch/power.h>
+#include <asm/gpio.h>
 #include <asm-generic/errno.h>
 #include <linux/compat.h>
 #include "ehci.h"
@@ -30,6 +31,7 @@ DECLARE_GLOBAL_DATA_PTR;
 struct exynos_ehci {
 	struct exynos_usb_phy *usb;
 	struct ehci_hccr *hcd;
+	struct fdt_gpio_state vbus_gpio;
 };
 
 static struct exynos_ehci exynos;
@@ -58,6 +60,9 @@ static int exynos_usb_parse_dt(const void *blob, struct exynos_ehci *exynos)
 
 	exynos->hcd = (struct ehci_hccr *)addr;
 
+	/* Vbus gpio */
+	fdtdec_decode_gpio(blob, node, "samsung,vbus-gpio", &exynos->vbus_gpio);
+
 	depth = 0;
 	node = fdtdec_next_compatible_subnode(blob, node,
 					COMPAT_SAMSUNG_EXYNOS_USB_PHY, &depth);
@@ -83,6 +88,8 @@ static int exynos_usb_parse_dt(const void *blob, struct exynos_ehci *exynos)
 /* Setup the EHCI host controller. */
 static void setup_usb_phy(struct exynos_usb_phy *usb)
 {
+	u32 hsic_ctrl;
+
 	set_usbhost_mode(USB20_PHY_CFG_HOST_LINK_EN);
 
 	set_usbhost_phy_ctrl(POWER_USB_HOST_PHY_CTRL_EN);
@@ -107,6 +114,32 @@ static void setup_usb_phy(struct exynos_usb_phy *usb)
 	clrbits_le32(&usb->usbphyctrl0,
 			HOST_CTRL0_LINKSWRST |
 			HOST_CTRL0_UTMISWRST);
+
+	/* HSIC Phy Setting */
+	hsic_ctrl = (HSIC_CTRL_FORCESUSPEND |
+			HSIC_CTRL_FORCESLEEP |
+			HSIC_CTRL_SIDDQ);
+
+	clrbits_le32(&usb->hsicphyctrl1, hsic_ctrl);
+	clrbits_le32(&usb->hsicphyctrl2, hsic_ctrl);
+
+	hsic_ctrl = (((HSIC_CTRL_REFCLKDIV_12 & HSIC_CTRL_REFCLKDIV_MASK)
+				<< HSIC_CTRL_REFCLKDIV_SHIFT)
+			| ((HSIC_CTRL_REFCLKSEL & HSIC_CTRL_REFCLKSEL_MASK)
+				<< HSIC_CTRL_REFCLKSEL_SHIFT)
+			| HSIC_CTRL_UTMISWRST);
+
+	setbits_le32(&usb->hsicphyctrl1, hsic_ctrl);
+	setbits_le32(&usb->hsicphyctrl2, hsic_ctrl);
+
+	udelay(10);
+
+	clrbits_le32(&usb->hsicphyctrl1, HSIC_CTRL_PHYSWRST |
+					HSIC_CTRL_UTMISWRST);
+
+	clrbits_le32(&usb->hsicphyctrl2, HSIC_CTRL_PHYSWRST |
+					HSIC_CTRL_UTMISWRST);
+
 	udelay(20);
 
 	/* EHCI Ctrl setting */
@@ -120,6 +153,8 @@ static void setup_usb_phy(struct exynos_usb_phy *usb)
 /* Reset the EHCI host controller. */
 static void reset_usb_phy(struct exynos_usb_phy *usb)
 {
+	u32 hsic_ctrl;
+
 	/* HOST_PHY reset */
 	setbits_le32(&usb->usbphyctrl0,
 			HOST_CTRL0_PHYSWRST |
@@ -128,6 +163,15 @@ static void reset_usb_phy(struct exynos_usb_phy *usb)
 			HOST_CTRL0_FORCESUSPEND |
 			HOST_CTRL0_FORCESLEEP);
 
+	/* HSIC Phy reset */
+	hsic_ctrl = (HSIC_CTRL_FORCESUSPEND |
+			HSIC_CTRL_FORCESLEEP |
+			HSIC_CTRL_SIDDQ |
+			HSIC_CTRL_PHYSWRST);
+
+	setbits_le32(&usb->hsicphyctrl1, hsic_ctrl);
+	setbits_le32(&usb->hsicphyctrl2, hsic_ctrl);
+
 	set_usbhost_phy_ctrl(POWER_USB_HOST_PHY_CTRL_DISABLE);
 }
 
@@ -136,7 +180,8 @@ static void reset_usb_phy(struct exynos_usb_phy *usb)
  * Create the appropriate control structures to manage
  * a new EHCI host controller.
  */
-int ehci_hcd_init(int index, struct ehci_hccr **hccr, struct ehci_hcor **hcor)
+int ehci_hcd_init(int index, enum usb_init_type init,
+		struct ehci_hccr **hccr, struct ehci_hcor **hcor)
 {
 	struct exynos_ehci *ctx = &exynos;
 
@@ -150,8 +195,16 @@ int ehci_hcd_init(int index, struct ehci_hccr **hccr, struct ehci_hcor **hcor)
 	ctx->hcd = (struct ehci_hccr *)samsung_get_base_usb_ehci();
 #endif
 
+#ifdef CONFIG_OF_CONTROL
+	/* setup the Vbus gpio here */
+	if (!fdtdec_setup_gpio(&ctx->vbus_gpio))
+		gpio_direction_output(ctx->vbus_gpio.gpio, 1);
+#endif
+
 	setup_usb_phy(ctx->usb);
 
+	board_usb_init(index, init);
+
 	*hccr = ctx->hcd;
 	*hcor = (struct ehci_hcor *)((uint32_t) *hccr
 				+ HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase)));
diff --git a/drivers/usb/host/ehci-faraday.c b/drivers/usb/host/ehci-faraday.c
index 4a36acdaec..3b761bc326 100644
--- a/drivers/usb/host/ehci-faraday.c
+++ b/drivers/usb/host/ehci-faraday.c
@@ -33,8 +33,8 @@ static inline int ehci_is_fotg2xx(union ehci_faraday_regs *regs)
  * Create the appropriate control structures to manage
  * a new EHCI host controller.
  */
-int ehci_hcd_init(int index, struct ehci_hccr **ret_hccr,
-		struct ehci_hcor **ret_hcor)
+int ehci_hcd_init(int index, enum usb_init_type init,
+		struct ehci_hccr **ret_hccr, struct ehci_hcor **ret_hcor)
 {
 	struct ehci_hccr *hccr;
 	struct ehci_hcor *hcor;
diff --git a/drivers/usb/host/ehci-fsl.c b/drivers/usb/host/ehci-fsl.c
index 0ef6f238d5..1ca7cf5d9b 100644
--- a/drivers/usb/host/ehci-fsl.c
+++ b/drivers/usb/host/ehci-fsl.c
@@ -35,9 +35,10 @@ static int usb_phy_clk_valid(struct usb_ehci *ehci)
  *
  * Excerpts from linux ehci fsl driver.
  */
-int ehci_hcd_init(int index, struct ehci_hccr **hccr, struct ehci_hcor **hcor)
+int ehci_hcd_init(int index, enum usb_init_type init,
+		struct ehci_hccr **hccr, struct ehci_hcor **hcor)
 {
-	struct usb_ehci *ehci;
+	struct usb_ehci *ehci = NULL;
 	const char *phy_type = NULL;
 	size_t len;
 #ifdef CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
@@ -46,7 +47,18 @@ int ehci_hcd_init(int index, struct ehci_hccr **hccr, struct ehci_hcor **hcor)
 	usb_phy[0] = '\0';
 #endif
 
-	ehci = (struct usb_ehci *)CONFIG_SYS_FSL_USB_ADDR;
+	switch (index) {
+	case 0:
+		ehci = (struct usb_ehci *)CONFIG_SYS_FSL_USB1_ADDR;
+		break;
+	case 1:
+		ehci = (struct usb_ehci *)CONFIG_SYS_FSL_USB2_ADDR;
+		break;
+	default:
+		printf("ERROR: wrong controller index!!\n");
+		break;
+	};
+
 	*hccr = (struct ehci_hccr *)((uint32_t)&ehci->caplength);
 	*hcor = (struct ehci_hcor *)((uint32_t) *hccr +
 			HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase)));
@@ -74,7 +86,7 @@ int ehci_hcd_init(int index, struct ehci_hccr **hccr, struct ehci_hcor **hcor)
 #endif
 	}
 
-	if (!strcmp(phy_type, "utmi")) {
+	if (!strncmp(phy_type, "utmi", 4)) {
 #if defined(CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY)
 		setbits_be32(&ehci->control, PHY_CLK_SEL_UTMI);
 		setbits_be32(&ehci->control, UTMI_PHY_EN);
diff --git a/drivers/usb/host/ehci-hcd.c b/drivers/usb/host/ehci-hcd.c
index 3ae04c0253..6017090ebe 100644
--- a/drivers/usb/host/ehci-hcd.c
+++ b/drivers/usb/host/ehci-hcd.c
@@ -201,6 +201,9 @@ static int ehci_shutdown(struct ehci_ctrl *ctrl)
 	int i, ret = 0;
 	uint32_t cmd, reg;
 
+	if (!ctrl || !ctrl->hcor)
+		return -EINVAL;
+
 	cmd = ehci_readl(&ctrl->hcor->or_usbcmd);
 	cmd &= ~(CMD_PSE | CMD_ASE);
 	ehci_writel(&ctrl->hcor->or_usbcmd, cmd);
@@ -392,6 +395,7 @@ ehci_submit_async(struct usb_device *dev, unsigned long pipe, void *buffer,
 		QH_ENDPT2_UFCMASK(0) | QH_ENDPT2_UFSMASK(0);
 	qh->qh_endpt2 = cpu_to_hc32(endpt);
 	qh->qh_overlay.qt_next = cpu_to_hc32(QT_NEXT_TERMINATE);
+	qh->qh_overlay.qt_altnext = cpu_to_hc32(QT_NEXT_TERMINATE);
 
 	tdp = &qh->qh_overlay.qt_next;
 
@@ -919,28 +923,33 @@ int usb_lowlevel_stop(int index)
 	return ehci_hcd_stop(index);
 }
 
-int usb_lowlevel_init(int index, void **controller)
+int usb_lowlevel_init(int index, enum usb_init_type init, void **controller)
 {
 	uint32_t reg;
 	uint32_t cmd;
 	struct QH *qh_list;
 	struct QH *periodic;
 	int i;
+	int rc;
 
-	if (ehci_hcd_init(index, &ehcic[index].hccr, &ehcic[index].hcor))
-		return -1;
+	rc = ehci_hcd_init(index, init, &ehcic[index].hccr, &ehcic[index].hcor);
+	if (rc)
+		return rc;
+	if (init == USB_INIT_DEVICE)
+		goto done;
 
 	/* EHCI spec section 4.1 */
 	if (ehci_reset(index))
 		return -1;
 
 #if defined(CONFIG_EHCI_HCD_INIT_AFTER_RESET)
-	if (ehci_hcd_init(index, &ehcic[index].hccr, &ehcic[index].hcor))
-		return -1;
+	rc = ehci_hcd_init(index, init, &ehcic[index].hccr, &ehcic[index].hcor);
+	if (rc)
+		return rc;
 #endif
 	/* Set the high address word (aka segment) for 64-bit controller */
 	if (ehci_readl(&ehcic[index].hccr->cr_hccparams) & 1)
-		ehci_writel(ehcic[index].hcor->or_ctrldssegment, 0);
+		ehci_writel(&ehcic[index].hcor->or_ctrldssegment, 0);
 
 	qh_list = &ehcic[index].qh_list;
 
@@ -1037,7 +1046,7 @@ int usb_lowlevel_init(int index, void **controller)
 	printf("USB EHCI %x.%02x\n", reg >> 8, reg & 0xff);
 
 	ehcic[index].rootdev = 0;
-
+done:
 	*controller = &ehcic[index];
 	return 0;
 }
@@ -1153,14 +1162,16 @@ create_int_queue(struct usb_device *dev, unsigned long pipe, int queuesize,
 		debug("ehci intr queue: out of memory\n");
 		goto fail1;
 	}
-	result->first = memalign(32, sizeof(struct QH) * queuesize);
+	result->first = memalign(USB_DMA_MINALIGN,
+				 sizeof(struct QH) * queuesize);
 	if (!result->first) {
 		debug("ehci intr queue: out of memory\n");
 		goto fail2;
 	}
 	result->current = result->first;
 	result->last = result->first + queuesize - 1;
-	result->tds = memalign(32, sizeof(struct qTD) * queuesize);
+	result->tds = memalign(USB_DMA_MINALIGN,
+			       sizeof(struct qTD) * queuesize);
 	if (!result->tds) {
 		debug("ehci intr queue: out of memory\n");
 		goto fail3;
@@ -1178,6 +1189,7 @@ create_int_queue(struct usb_device *dev, unsigned long pipe, int queuesize,
 			qh->qh_link = QH_LINK_TERMINATE;
 
 		qh->qh_overlay.qt_next = (uint32_t)td;
+		qh->qh_overlay.qt_altnext = QT_NEXT_TERMINATE;
 		qh->qh_endpt1 = (0 << 28) | /* No NAK reload (ehci 4.9) */
 			(usb_maxpacket(dev, pipe) << 16) | /* MPS */
 			(1 << 14) |
diff --git a/drivers/usb/host/ehci-ixp4xx.c b/drivers/usb/host/ehci-ixp4xx.c
deleted file mode 100644
index 56ef7e6c13..0000000000
--- a/drivers/usb/host/ehci-ixp4xx.c
+++ /dev/null
@@ -1,36 +0,0 @@
-/*
- * (C) Copyright 2008, Michael Trimarchi <trimarchimichael@yahoo.it>
- *
- * Author: Michael Trimarchi <trimarchimichael@yahoo.it>
- * This code is based on ehci freescale driver
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-#include <common.h>
-#include <usb.h>
-
-#include "ehci.h"
-/*
- * Create the appropriate control structures to manage
- * a new EHCI host controller.
- */
-int ehci_hcd_init(int index, struct ehci_hccr **hccr, struct ehci_hcor **hcor)
-{
-	*hccr = (struct ehci_hccr *)(0xcd000100);
-	*hcor = (struct ehci_hcor *)((uint32_t) *hccr
-			+ HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase)));
-
-	printf("IXP4XX init hccr %x and hcor %x hc_length %d\n",
-		(uint32_t)*hccr, (uint32_t)*hcor,
-		(uint32_t)HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase)));
-	return 0;
-}
-
-/*
- * Destroy the appropriate control structures corresponding
- * the the EHCI host controller.
- */
-int ehci_hcd_stop(int index)
-{
-	return 0;
-}
diff --git a/drivers/usb/host/ehci-marvell.c b/drivers/usb/host/ehci-marvell.c
index ee97fd2745..52c43fdc5a 100644
--- a/drivers/usb/host/ehci-marvell.c
+++ b/drivers/usb/host/ehci-marvell.c
@@ -74,7 +74,8 @@ static void usb_brg_adrdec_setup(void)
  * Create the appropriate control structures to manage
  * a new EHCI host controller.
  */
-int ehci_hcd_init(int index, struct ehci_hccr **hccr, struct ehci_hcor **hcor)
+int ehci_hcd_init(int index, enum usb_init_type init,
+		struct ehci_hccr **hccr, struct ehci_hcor **hcor)
 {
 	usb_brg_adrdec_setup();
 
diff --git a/drivers/usb/host/ehci-mpc512x.c b/drivers/usb/host/ehci-mpc512x.c
index bb6e7ac97f..b320c4a4e2 100644
--- a/drivers/usb/host/ehci-mpc512x.c
+++ b/drivers/usb/host/ehci-mpc512x.c
@@ -32,12 +32,13 @@ static void usb_platform_dr_init(volatile struct usb_ehci *ehci);
  * This code is derived from EHCI FSL USB Linux driver for MPC5121
  *
  */
-int ehci_hcd_init(int index, struct ehci_hccr **hccr, struct ehci_hcor **hcor)
+int ehci_hcd_init(int index, enum usb_init_type init,
+		struct ehci_hccr **hccr, struct ehci_hcor **hcor)
 {
 	volatile struct usb_ehci *ehci;
 
 	/* Hook the memory mapped registers for EHCI-Controller */
-	ehci = (struct usb_ehci *)CONFIG_SYS_FSL_USB_ADDR;
+	ehci = (struct usb_ehci *)CONFIG_SYS_FSL_USB1_ADDR;
 	*hccr = (struct ehci_hccr *)((uint32_t)&(ehci->caplength));
 	*hcor = (struct ehci_hcor *)((uint32_t) *hccr +
 				HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase)));
@@ -81,7 +82,7 @@ int ehci_hcd_stop(int index)
 	int exit_status = 0;
 
 	/* Reset the USB controller */
-	ehci = (struct usb_ehci *)CONFIG_SYS_FSL_USB_ADDR;
+	ehci = (struct usb_ehci *)CONFIG_SYS_FSL_USB1_ADDR;
 	exit_status = reset_usb_controller(ehci);
 
 	return exit_status;
diff --git a/drivers/usb/host/ehci-mx5.c b/drivers/usb/host/ehci-mx5.c
index dd11f535ad..7566c61284 100644
--- a/drivers/usb/host/ehci-mx5.c
+++ b/drivers/usb/host/ehci-mx5.c
@@ -218,7 +218,8 @@ void __weak board_ehci_hcd_postinit(struct usb_ehci *ehci, int port)
 {
 }
 
-int ehci_hcd_init(int index, struct ehci_hccr **hccr, struct ehci_hcor **hcor)
+int ehci_hcd_init(int index, enum usb_init_type init,
+		struct ehci_hccr **hccr, struct ehci_hcor **hcor)
 {
 	struct usb_ehci *ehci;
 
diff --git a/drivers/usb/host/ehci-mx6.c b/drivers/usb/host/ehci-mx6.c
index eb24af5974..c0a557b2ad 100644
--- a/drivers/usb/host/ehci-mx6.c
+++ b/drivers/usb/host/ehci-mx6.c
@@ -35,6 +35,7 @@
 #define USBPHY_CTRL_CLKGATE			0x40000000
 #define USBPHY_CTRL_ENUTMILEVEL3		0x00008000
 #define USBPHY_CTRL_ENUTMILEVEL2		0x00004000
+#define USBPHY_CTRL_OTG_ID			0x08000000
 
 #define ANADIG_USB2_CHRG_DETECT_EN_B		0x00100000
 #define ANADIG_USB2_CHRG_DETECT_CHK_CHRG_B	0x00080000
@@ -49,52 +50,84 @@
 #define UCTRL_OVER_CUR_DIS	(1 << 7) /* Disable OTG Overcurrent Detection */
 
 /* USBCMD */
-#define UH1_USBCMD_OFFSET	0x140
 #define UCMD_RUN_STOP           (1 << 0) /* controller run/stop */
 #define UCMD_RESET		(1 << 1) /* controller reset */
 
-static void usbh1_internal_phy_clock_gate(int on)
+static const unsigned phy_bases[] = {
+	USB_PHY0_BASE_ADDR,
+	USB_PHY1_BASE_ADDR,
+};
+
+static void usb_internal_phy_clock_gate(int index, int on)
 {
-	void __iomem *phy_reg = (void __iomem *)USB_PHY1_BASE_ADDR;
+	void __iomem *phy_reg;
+
+	if (index >= ARRAY_SIZE(phy_bases))
+		return;
 
+	phy_reg = (void __iomem *)phy_bases[index];
 	phy_reg += on ? USBPHY_CTRL_CLR : USBPHY_CTRL_SET;
 	__raw_writel(USBPHY_CTRL_CLKGATE, phy_reg);
 }
 
-static void usbh1_power_config(void)
+static void usb_power_config(int index)
 {
 	struct anatop_regs __iomem *anatop =
 		(struct anatop_regs __iomem *)ANATOP_BASE_ADDR;
+	void __iomem *chrg_detect;
+	void __iomem *pll_480_ctrl_clr;
+	void __iomem *pll_480_ctrl_set;
+
+	switch (index) {
+	case 0:
+		chrg_detect = &anatop->usb1_chrg_detect;
+		pll_480_ctrl_clr = &anatop->usb1_pll_480_ctrl_clr;
+		pll_480_ctrl_set = &anatop->usb1_pll_480_ctrl_set;
+		break;
+	case 1:
+		chrg_detect = &anatop->usb2_chrg_detect;
+		pll_480_ctrl_clr = &anatop->usb2_pll_480_ctrl_clr;
+		pll_480_ctrl_set = &anatop->usb2_pll_480_ctrl_set;
+		break;
+	default:
+		return;
+	}
 	/*
-	 * Some phy and power's special controls for host1
+	 * Some phy and power's special controls
 	 * 1. The external charger detector needs to be disabled
 	 * or the signal at DP will be poor
-	 * 2. The PLL's power and output to usb for host 1
+	 * 2. The PLL's power and output to usb
 	 * is totally controlled by IC, so the Software only needs
 	 * to enable them at initializtion.
 	 */
 	__raw_writel(ANADIG_USB2_CHRG_DETECT_EN_B |
 		     ANADIG_USB2_CHRG_DETECT_CHK_CHRG_B,
-		     &anatop->usb2_chrg_detect);
+		     chrg_detect);
 
 	__raw_writel(ANADIG_USB2_PLL_480_CTRL_BYPASS,
-		     &anatop->usb2_pll_480_ctrl_clr);
+		     pll_480_ctrl_clr);
 
 	__raw_writel(ANADIG_USB2_PLL_480_CTRL_ENABLE |
 		     ANADIG_USB2_PLL_480_CTRL_POWER |
 		     ANADIG_USB2_PLL_480_CTRL_EN_USB_CLKS,
-		     &anatop->usb2_pll_480_ctrl_set);
+		     pll_480_ctrl_set);
 }
 
-static int usbh1_phy_enable(void)
+/* Return 0 : host node, <>0 : device mode */
+static int usb_phy_enable(int index, struct usb_ehci *ehci)
 {
-	void __iomem *phy_reg = (void __iomem *)USB_PHY1_BASE_ADDR;
-	void __iomem *phy_ctrl = (void __iomem *)(phy_reg + USBPHY_CTRL);
-	void __iomem *usb_cmd =	(void __iomem *)(USBOH3_USB_BASE_ADDR +
-						 USB_H1REGS_OFFSET +
-						 UH1_USBCMD_OFFSET);
+	void __iomem *phy_reg;
+	void __iomem *phy_ctrl;
+	void __iomem *usb_cmd;
 	u32 val;
 
+	if (index >= ARRAY_SIZE(phy_bases))
+		return 0;
+
+	phy_reg = (void __iomem *)phy_bases[index];
+	phy_ctrl = (void __iomem *)(phy_reg + USBPHY_CTRL);
+	usb_cmd = (void __iomem *)&ehci->usbcmd;
+
 	/* Stop then Reset */
 	val = __raw_readl(usb_cmd);
 	val &= ~UCMD_RUN_STOP;
@@ -123,31 +156,41 @@ static int usbh1_phy_enable(void)
 	/* Power up the PHY */
 	__raw_writel(0, phy_reg + USBPHY_PWD);
 	/* enable FS/LS device */
-	val = __raw_readl(phy_reg + USBPHY_CTRL);
+	val = __raw_readl(phy_ctrl);
 	val |= (USBPHY_CTRL_ENUTMILEVEL2 | USBPHY_CTRL_ENUTMILEVEL3);
-	__raw_writel(val, phy_reg + USBPHY_CTRL);
+	__raw_writel(val, phy_ctrl);
 
-	return 0;
+	return val & USBPHY_CTRL_OTG_ID;
 }
 
-static void usbh1_oc_config(void)
+/* Base address for this IP block is 0x02184800 */
+struct usbnc_regs {
+	u32	ctrl[4];	/* otg/host1-3 */
+	u32	uh2_hsic_ctrl;
+	u32	uh3_hsic_ctrl;
+	u32	otg_phy_ctrl_0;
+	u32	uh1_phy_ctrl_0;
+};
+
+static void usb_oc_config(int index)
 {
-	void __iomem *usb_base = (void __iomem *)USBOH3_USB_BASE_ADDR;
-	void __iomem *usbother_base = usb_base + USB_OTHERREGS_OFFSET;
+	struct usbnc_regs *usbnc = (struct usbnc_regs *)(USBOH3_USB_BASE_ADDR +
+			USB_OTHERREGS_OFFSET);
+	void __iomem *ctrl = (void __iomem *)(&usbnc->ctrl[index]);
 	u32 val;
 
-	val = __raw_readl(usbother_base + USB_H1_CTRL_OFFSET);
+	val = __raw_readl(ctrl);
 #if CONFIG_MACH_TYPE == MACH_TYPE_MX6Q_ARM2
 	/* mx6qarm2 seems to required a different setting*/
 	val &= ~UCTRL_OVER_CUR_POL;
 #else
 	val |= UCTRL_OVER_CUR_POL;
 #endif
-	__raw_writel(val, usbother_base + USB_H1_CTRL_OFFSET);
+	__raw_writel(val, ctrl);
 
-	val = __raw_readl(usbother_base + USB_H1_CTRL_OFFSET);
+	val = __raw_readl(ctrl);
 	val |= UCTRL_OVER_CUR_DIS;
-	__raw_writel(val, usbother_base + USB_H1_CTRL_OFFSET);
+	__raw_writel(val, ctrl);
 }
 
 int __weak board_ehci_hcd_init(int port)
@@ -155,33 +198,42 @@ int __weak board_ehci_hcd_init(int port)
 	return 0;
 }
 
-int ehci_hcd_init(int index, struct ehci_hccr **hccr, struct ehci_hcor **hcor)
+int __weak board_ehci_power(int port, int on)
 {
-	struct usb_ehci *ehci;
+	return 0;
+}
+
+int ehci_hcd_init(int index, enum usb_init_type init,
+		struct ehci_hccr **hccr, struct ehci_hcor **hcor)
+{
+	enum usb_init_type type;
+	struct usb_ehci *ehci = (struct usb_ehci *)(USBOH3_USB_BASE_ADDR +
+		(0x200 * index));
 
+	if (index > 3)
+		return -EINVAL;
 	enable_usboh3_clk(1);
 	mdelay(1);
 
 	/* Do board specific initialization */
-	board_ehci_hcd_init(CONFIG_MXC_USB_PORT);
-
-#if CONFIG_MXC_USB_PORT == 1
-	/* USB Host 1 */
-	usbh1_power_config();
-	usbh1_oc_config();
-	usbh1_internal_phy_clock_gate(1);
-	usbh1_phy_enable();
-#else
-#error "MXC USB port not yet supported"
-#endif
+	board_ehci_hcd_init(index);
+
+	usb_power_config(index);
+	usb_oc_config(index);
+	usb_internal_phy_clock_gate(index, 1);
+	type = usb_phy_enable(index, ehci) ? USB_INIT_DEVICE : USB_INIT_HOST;
 
-	ehci = (struct usb_ehci *)(USBOH3_USB_BASE_ADDR +
-		(0x200 * CONFIG_MXC_USB_PORT));
 	*hccr = (struct ehci_hccr *)((uint32_t)&ehci->caplength);
 	*hcor = (struct ehci_hcor *)((uint32_t)*hccr +
 			HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase)));
-	setbits_le32(&ehci->usbmode, CM_HOST);
 
+	if ((type == init) || (type == USB_INIT_DEVICE))
+		board_ehci_power(index, (type == USB_INIT_DEVICE) ? 0 : 1);
+	if (type != init)
+		return -ENODEV;
+	if (type == USB_INIT_DEVICE)
+		return 0;
+	setbits_le32(&ehci->usbmode, CM_HOST);
 	__raw_writel(CONFIG_MXC_USB_PORTSC, &ehci->portsc);
 	setbits_le32(&ehci->portsc, USB_EN);
 
diff --git a/drivers/usb/host/ehci-mxc.c b/drivers/usb/host/ehci-mxc.c
index a3048d105a..f09c75a9b6 100644
--- a/drivers/usb/host/ehci-mxc.c
+++ b/drivers/usb/host/ehci-mxc.c
@@ -208,7 +208,8 @@ static int mxc_set_usbcontrol(int port, unsigned int flags)
 	return 0;
 }
 
-int ehci_hcd_init(int index, struct ehci_hccr **hccr, struct ehci_hcor **hcor)
+int ehci_hcd_init(int index, enum usb_init_type init,
+		struct ehci_hccr **hccr, struct ehci_hcor **hcor)
 {
 	struct usb_ehci *ehci;
 #ifdef CONFIG_MX31
diff --git a/drivers/usb/host/ehci-mxs.c b/drivers/usb/host/ehci-mxs.c
index 286a380de2..4d652b32db 100644
--- a/drivers/usb/host/ehci-mxs.c
+++ b/drivers/usb/host/ehci-mxs.c
@@ -77,7 +77,8 @@ static int ehci_mxs_toggle_clock(const struct ehci_mxs_port *port, int enable)
 	return 0;
 }
 
-int ehci_hcd_init(int index, struct ehci_hccr **hccr, struct ehci_hcor **hcor)
+int ehci_hcd_init(int index, enum usb_init_type init,
+		struct ehci_hccr **hccr, struct ehci_hcor **hcor)
 {
 
 	int ret;
diff --git a/drivers/usb/host/ehci-omap.c b/drivers/usb/host/ehci-omap.c
index 3c58f9e656..1b215c25f6 100644
--- a/drivers/usb/host/ehci-omap.c
+++ b/drivers/usb/host/ehci-omap.c
@@ -28,21 +28,48 @@ static struct omap_ehci *const ehci = (struct omap_ehci *)OMAP_EHCI_BASE;
 
 static int omap_uhh_reset(void)
 {
-/*
- * Soft resetting the UHH module causes instability issues on
- * all OMAPs so we just avoid it.
- *
- * See OMAP36xx Errata
- *  i571: USB host EHCI may stall when entering smart-standby mode
- *  i660: USBHOST Configured In Smart-Idle Can Lead To a Deadlock
- *
- * On OMAP4/5, soft-resetting the UHH module will put it into
- * Smart-Idle mode and lead to a deadlock.
- *
- * On OMAP3, this doesn't seem to be the case but still instabilities
- * are observed on beagle (3530 ES1.0) if soft-reset is used.
- * e.g. NFS root failures with Linux kernel.
- */
+	int timeout = 0;
+	u32 rev;
+
+	rev = readl(&uhh->rev);
+
+	/* Soft RESET */
+	writel(OMAP_UHH_SYSCONFIG_SOFTRESET, &uhh->sysc);
+
+	switch (rev) {
+	case OMAP_USBHS_REV1:
+		/* Wait for soft RESET to complete */
+		while (!(readl(&uhh->syss) & 0x1)) {
+			if (timeout > 100) {
+				printf("%s: RESET timeout\n", __func__);
+				return -1;
+			}
+			udelay(10);
+			timeout++;
+		}
+
+		/* Set No-Idle, No-Standby */
+		writel(OMAP_UHH_SYSCONFIG_VAL, &uhh->sysc);
+		break;
+
+	default:	/* Rev. 2 onwards */
+
+		udelay(2); /* Need to wait before accessing SYSCONFIG back */
+
+		/* Wait for soft RESET to complete */
+		while ((readl(&uhh->sysc) & 0x1)) {
+			if (timeout > 100) {
+				printf("%s: RESET timeout\n", __func__);
+				return -1;
+			}
+			udelay(10);
+			timeout++;
+		}
+
+		writel(OMAP_UHH_SYSCONFIG_VAL, &uhh->sysc);
+		break;
+	}
+
 	return 0;
 }
 
@@ -96,12 +123,6 @@ static void omap_ehci_soft_phy_reset(int port)
 }
 #endif
 
-inline int __board_usb_init(void)
-{
-	return 0;
-}
-int board_usb_init(void) __attribute__((weak, alias("__board_usb_init")));
-
 #if defined(CONFIG_OMAP_EHCI_PHY1_RESET_GPIO) || \
 	defined(CONFIG_OMAP_EHCI_PHY2_RESET_GPIO) || \
 	defined(CONFIG_OMAP_EHCI_PHY3_RESET_GPIO)
@@ -157,15 +178,15 @@ int omap_ehci_hcd_stop(void)
  * Based on "drivers/usb/host/ehci-omap.c" from Linux 3.1
  * See there for additional Copyrights.
  */
-int omap_ehci_hcd_init(struct omap_usbhs_board_data *usbhs_pdata,
-		struct ehci_hccr **hccr, struct ehci_hcor **hcor)
+int omap_ehci_hcd_init(int index, struct omap_usbhs_board_data *usbhs_pdata,
+		       struct ehci_hccr **hccr, struct ehci_hcor **hcor)
 {
 	int ret;
 	unsigned int i, reg = 0, rev = 0;
 
 	debug("Initializing OMAP EHCI\n");
 
-	ret = board_usb_init();
+	ret = board_usb_init(index, USB_INIT_HOST);
 	if (ret < 0)
 		return ret;
 
diff --git a/drivers/usb/host/ehci-pci.c b/drivers/usb/host/ehci-pci.c
index 90d7a6feb5..991b19998b 100644
--- a/drivers/usb/host/ehci-pci.c
+++ b/drivers/usb/host/ehci-pci.c
@@ -54,9 +54,31 @@ static pci_dev_t ehci_find_class(int index)
 					bdf += PCI_BDF(0, 0, 1)) {
 				pci_read_config_dword(bdf, PCI_CLASS_REVISION,
 						      &class);
-				if ((class >> 8 == PCI_CLASS_SERIAL_USB_EHCI)
-						&& !index--)
-					return bdf;
+				class >>= 8;
+				/*
+				 * Here be dragons! In case we have multiple
+				 * PCI EHCI controllers, this function will
+				 * be called multiple times as well. This
+				 * function will scan the PCI busses, always
+				 * starting from bus 0, device 0, function 0,
+				 * until it finds an USB controller. The USB
+				 * stack gives us an 'index' of a controller
+				 * that is currently being registered, which
+				 * is a number, starting from 0 and growing
+				 * in ascending order as controllers are added.
+				 * To avoid probing the same controller in tne
+				 * subsequent runs of this function, we will
+				 * skip 'index - 1' detected controllers and
+				 * report the index'th controller.
+				 */
+				if (class != PCI_CLASS_SERIAL_USB_EHCI)
+					continue;
+				if (index) {
+					index--;
+					continue;
+				}
+				/* Return index'th controller. */
+				return bdf;
 			}
 		}
 	}
@@ -69,8 +91,8 @@ static pci_dev_t ehci_find_class(int index)
  * Create the appropriate control structures to manage
  * a new EHCI host controller.
  */
-int ehci_hcd_init(int index, struct ehci_hccr **ret_hccr,
-		struct ehci_hcor **ret_hcor)
+int ehci_hcd_init(int index, enum usb_init_type init,
+		struct ehci_hccr **ret_hccr, struct ehci_hcor **ret_hcor)
 {
 	pci_dev_t pdev;
 	uint32_t cmd;
diff --git a/drivers/usb/host/ehci-ppc4xx.c b/drivers/usb/host/ehci-ppc4xx.c
index 462fcfbe4f..9aee3ff786 100644
--- a/drivers/usb/host/ehci-ppc4xx.c
+++ b/drivers/usb/host/ehci-ppc4xx.c
@@ -15,7 +15,8 @@
  * Create the appropriate control structures to manage
  * a new EHCI host controller.
  */
-int ehci_hcd_init(int index, struct ehci_hccr **hccr, struct ehci_hcor **hcor)
+int ehci_hcd_init(int index, enum usb_init_type init,
+		struct ehci_hccr **hccr, struct ehci_hcor **hcor)
 {
 	*hccr = (struct ehci_hccr *)(CONFIG_SYS_PPC4XX_USB_ADDR);
 	*hcor = (struct ehci_hcor *)((uint32_t) *hccr +
diff --git a/drivers/usb/host/ehci-spear.c b/drivers/usb/host/ehci-spear.c
index 6758316f7f..210ee9e88e 100644
--- a/drivers/usb/host/ehci-spear.c
+++ b/drivers/usb/host/ehci-spear.c
@@ -20,7 +20,8 @@
  * Create the appropriate control structures to manage
  * a new EHCI host controller.
  */
-int ehci_hcd_init(int index, struct ehci_hccr **hccr, struct ehci_hcor **hcor)
+int ehci_hcd_init(int index, enum usb_init_type init,
+		struct ehci_hccr **hccr, struct ehci_hcor **hcor)
 {
 	*hccr = (struct ehci_hccr *)(CONFIG_SYS_UHC0_EHCI_BASE + 0x100);
 	*hcor = (struct ehci_hcor *)((uint32_t)*hccr
diff --git a/drivers/usb/host/ehci-tegra.c b/drivers/usb/host/ehci-tegra.c
index c6da449e4b..0b42aa5b38 100644
--- a/drivers/usb/host/ehci-tegra.c
+++ b/drivers/usb/host/ehci-tegra.c
@@ -699,7 +699,7 @@ static int process_usb_nodes(const void *blob, int node_list[], int count)
 	return 0;
 }
 
-int board_usb_init(const void *blob)
+int usb_process_devicetree(const void *blob)
 {
 	int node_list[USB_PORTS_MAX];
 	int count, err = 0;
@@ -734,7 +734,8 @@ int board_usb_init(const void *blob)
  * @param hcor		returns start address of EHCI HCOR registers
  * @return 0 if ok, -1 on error (generally invalid port number)
  */
-int ehci_hcd_init(int index, struct ehci_hccr **hccr, struct ehci_hcor **hcor)
+int ehci_hcd_init(int index, enum usb_init_type init,
+		struct ehci_hccr **hccr, struct ehci_hcor **hcor)
 {
 	struct fdt_usb *config;
 	struct usb_ctlr *usbctlr;
diff --git a/drivers/usb/host/ehci-vct.c b/drivers/usb/host/ehci-vct.c
index 4252c272cf..512ad3fb78 100644
--- a/drivers/usb/host/ehci-vct.c
+++ b/drivers/usb/host/ehci-vct.c
@@ -15,7 +15,8 @@ int vct_ehci_hcd_init(u32 *hccr, u32 *hcor);
  * Create the appropriate control structures to manage
  * a new EHCI host controller.
  */
-int ehci_hcd_init(int index, struct ehci_hccr **hccr, struct ehci_hcor **hcor)
+int ehci_hcd_init(int index, enum usb_init_type init,
+		struct ehci_hccr **hccr, struct ehci_hcor **hcor)
 {
 	int ret;
 	u32 vct_hccr;
diff --git a/drivers/usb/host/ehci.h b/drivers/usb/host/ehci.h
index bd52afe262..093eb4b832 100644
--- a/drivers/usb/host/ehci.h
+++ b/drivers/usb/host/ehci.h
@@ -28,22 +28,6 @@
 #define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS	2
 #endif
 
-/* (shifted) direction/type/recipient from the USB 2.0 spec, table 9.2 */
-#define DeviceRequest \
-	((USB_DIR_IN | USB_TYPE_STANDARD | USB_RECIP_DEVICE) << 8)
-
-#define DeviceOutRequest \
-	((USB_DIR_OUT | USB_TYPE_STANDARD | USB_RECIP_DEVICE) << 8)
-
-#define InterfaceRequest \
-	((USB_DIR_IN | USB_TYPE_STANDARD | USB_RECIP_INTERFACE) << 8)
-
-#define EndpointRequest \
-	((USB_DIR_IN | USB_TYPE_STANDARD | USB_RECIP_INTERFACE) << 8)
-
-#define EndpointOutRequest \
-	((USB_DIR_OUT | USB_TYPE_STANDARD | USB_RECIP_INTERFACE) << 8)
-
 /*
  * Register Space.
  */
@@ -266,7 +250,8 @@ struct ehci_ctrl {
 };
 
 /* Low level init functions */
-int ehci_hcd_init(int index, struct ehci_hccr **hccr, struct ehci_hcor **hcor);
+int ehci_hcd_init(int index, enum usb_init_type init,
+		struct ehci_hccr **hccr, struct ehci_hcor **hcor);
 int ehci_hcd_stop(int index);
 
 #endif /* USB_EHCI_H */
diff --git a/drivers/usb/host/isp116x-hcd.c b/drivers/usb/host/isp116x-hcd.c
index 934550ad88..46e4cee1d0 100644
--- a/drivers/usb/host/isp116x-hcd.c
+++ b/drivers/usb/host/isp116x-hcd.c
@@ -254,105 +254,7 @@ static inline void dump_ptd_data(struct ptd *ptd, u8 * buf, int type)
 
 /* --- Virtual Root Hub ---------------------------------------------------- */
 
-/* Device descriptor */
-static __u8 root_hub_dev_des[] = {
-	0x12,			/*  __u8  bLength; */
-	0x01,			/*  __u8  bDescriptorType; Device */
-	0x10,			/*  __u16 bcdUSB; v1.1 */
-	0x01,
-	0x09,			/*  __u8  bDeviceClass; HUB_CLASSCODE */
-	0x00,			/*  __u8  bDeviceSubClass; */
-	0x00,			/*  __u8  bDeviceProtocol; */
-	0x08,			/*  __u8  bMaxPacketSize0; 8 Bytes */
-	0x00,			/*  __u16 idVendor; */
-	0x00,
-	0x00,			/*  __u16 idProduct; */
-	0x00,
-	0x00,			/*  __u16 bcdDevice; */
-	0x00,
-	0x00,			/*  __u8  iManufacturer; */
-	0x01,			/*  __u8  iProduct; */
-	0x00,			/*  __u8  iSerialNumber; */
-	0x01			/*  __u8  bNumConfigurations; */
-};
-
-/* Configuration descriptor */
-static __u8 root_hub_config_des[] = {
-	0x09,			/*  __u8  bLength; */
-	0x02,			/*  __u8  bDescriptorType; Configuration */
-	0x19,			/*  __u16 wTotalLength; */
-	0x00,
-	0x01,			/*  __u8  bNumInterfaces; */
-	0x01,			/*  __u8  bConfigurationValue; */
-	0x00,			/*  __u8  iConfiguration; */
-	0x40,			/*  __u8  bmAttributes;
-				   Bit 7: Bus-powered, 6: Self-powered, 5 Remote-wakwup, 4..0: resvd */
-	0x00,			/*  __u8  MaxPower; */
-
-	/* interface */
-	0x09,			/*  __u8  if_bLength; */
-	0x04,			/*  __u8  if_bDescriptorType; Interface */
-	0x00,			/*  __u8  if_bInterfaceNumber; */
-	0x00,			/*  __u8  if_bAlternateSetting; */
-	0x01,			/*  __u8  if_bNumEndpoints; */
-	0x09,			/*  __u8  if_bInterfaceClass; HUB_CLASSCODE */
-	0x00,			/*  __u8  if_bInterfaceSubClass; */
-	0x00,			/*  __u8  if_bInterfaceProtocol; */
-	0x00,			/*  __u8  if_iInterface; */
-
-	/* endpoint */
-	0x07,			/*  __u8  ep_bLength; */
-	0x05,			/*  __u8  ep_bDescriptorType; Endpoint */
-	0x81,			/*  __u8  ep_bEndpointAddress; IN Endpoint 1 */
-	0x03,			/*  __u8  ep_bmAttributes; Interrupt */
-	0x00,			/*  __u16 ep_wMaxPacketSize; ((MAX_ROOT_PORTS + 1) / 8 */
-	0x02,
-	0xff			/*  __u8  ep_bInterval; 255 ms */
-};
-
-static unsigned char root_hub_str_index0[] = {
-	0x04,			/*  __u8  bLength; */
-	0x03,			/*  __u8  bDescriptorType; String-descriptor */
-	0x09,			/*  __u8  lang ID */
-	0x04,			/*  __u8  lang ID */
-};
-
-static unsigned char root_hub_str_index1[] = {
-	0x22,			/*  __u8  bLength; */
-	0x03,			/*  __u8  bDescriptorType; String-descriptor */
-	'I',			/*  __u8  Unicode */
-	0,			/*  __u8  Unicode */
-	'S',			/*  __u8  Unicode */
-	0,			/*  __u8  Unicode */
-	'P',			/*  __u8  Unicode */
-	0,			/*  __u8  Unicode */
-	'1',			/*  __u8  Unicode */
-	0,			/*  __u8  Unicode */
-	'1',			/*  __u8  Unicode */
-	0,			/*  __u8  Unicode */
-	'6',			/*  __u8  Unicode */
-	0,			/*  __u8  Unicode */
-	'x',			/*  __u8  Unicode */
-	0,			/*  __u8  Unicode */
-	' ',			/*  __u8  Unicode */
-	0,			/*  __u8  Unicode */
-	'R',			/*  __u8  Unicode */
-	0,			/*  __u8  Unicode */
-	'o',			/*  __u8  Unicode */
-	0,			/*  __u8  Unicode */
-	'o',			/*  __u8  Unicode */
-	0,			/*  __u8  Unicode */
-	't',			/*  __u8  Unicode */
-	0,			/*  __u8  Unicode */
-	' ',			/*  __u8  Unicode */
-	0,			/*  __u8  Unicode */
-	'H',			/*  __u8  Unicode */
-	0,			/*  __u8  Unicode */
-	'u',			/*  __u8  Unicode */
-	0,			/*  __u8  Unicode */
-	'b',			/*  __u8  Unicode */
-	0,			/*  __u8  Unicode */
-};
+#include <usbroothubdes.h>
 
 /*
  * Hub class-specific descriptor is constructed dynamically
@@ -1377,7 +1279,7 @@ int isp116x_check_id(struct isp116x *isp116x)
 	return 0;
 }
 
-int usb_lowlevel_init(int index, void **controller))
+int usb_lowlevel_init(int index, enum usb_init_type init, void **controller))
 {
 	struct isp116x *isp116x = &isp116x_dev;
 
diff --git a/drivers/usb/host/ohci-at91.c b/drivers/usb/host/ohci-at91.c
index 9e90d59087..c24505e78e 100644
--- a/drivers/usb/host/ohci-at91.c
+++ b/drivers/usb/host/ohci-at91.c
@@ -18,15 +18,15 @@ int usb_cpu_init(void)
 {
 	at91_pmc_t *pmc	= (at91_pmc_t *)ATMEL_BASE_PMC;
 
-#if defined(CONFIG_AT91CAP9) || defined(CONFIG_AT91SAM9260) || \
-    defined(CONFIG_AT91SAM9263) || defined(CONFIG_AT91SAM9G20) || \
-    defined(CONFIG_AT91SAM9261)
+#ifdef CONFIG_USB_ATMEL_CLK_SEL_PLLB
 	/* Enable PLLB */
 	writel(get_pllb_init(), &pmc->pllbr);
 	while ((readl(&pmc->sr) & AT91_PMC_LOCKB) != AT91_PMC_LOCKB)
 		;
-#elif defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9M10G45) || \
-	defined(CONFIG_AT91SAM9X5) || defined(CONFIG_SAMA5D3)
+#ifdef CONFIG_AT91SAM9N12
+	writel(AT91_PMC_USBS_USB_PLLB | AT91_PMC_USB_DIV_2, &pmc->usb);
+#endif
+#elif defined(CONFIG_USB_ATMEL_CLK_SEL_UPLL)
 	/* Enable UPLL */
 	writel(readl(&pmc->uckr) | AT91_PMC_UPLLEN | AT91_PMC_BIASEN,
 		&pmc->uckr);
@@ -70,14 +70,15 @@ int usb_cpu_stop(void)
 	writel(ATMEL_PMC_UHP, &pmc->scdr);
 #endif
 
-#if defined(CONFIG_AT91CAP9) || defined(CONFIG_AT91SAM9260) || \
-    defined(CONFIG_AT91SAM9263) || defined(CONFIG_AT91SAM9G20)
+#ifdef CONFIG_USB_ATMEL_CLK_SEL_PLLB
+#ifdef CONFIG_AT91SAM9N12
+	writel(0, &pmc->usb);
+#endif
 	/* Disable PLLB */
 	writel(0, &pmc->pllbr);
 	while ((readl(&pmc->sr) & AT91_PMC_LOCKB) != 0)
 		;
-#elif defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9M10G45) || \
-	defined(CONFIG_AT91SAM9X5) || defined(CONFIG_SAMA5D3)
+#elif defined(CONFIG_USB_ATMEL_CLK_SEL_UPLL)
 	/* Disable UPLL */
 	writel(readl(&pmc->uckr) & (~AT91_PMC_UPLLEN), &pmc->uckr);
 	while ((readl(&pmc->sr) & AT91_PMC_LOCKU) == AT91_PMC_LOCKU)
diff --git a/drivers/usb/host/ohci-hcd.c b/drivers/usb/host/ohci-hcd.c
index c33c487ee5..dc0a4e3179 100644
--- a/drivers/usb/host/ohci-hcd.c
+++ b/drivers/usb/host/ohci-hcd.c
@@ -1094,103 +1094,7 @@ static int dl_done_list(ohci_t *ohci)
  * Virtual Root Hub
  *-------------------------------------------------------------------------*/
 
-/* Device descriptor */
-static __u8 root_hub_dev_des[] =
-{
-	0x12,	    /*	__u8  bLength; */
-	0x01,	    /*	__u8  bDescriptorType; Device */
-	0x10,	    /*	__u16 bcdUSB; v1.1 */
-	0x01,
-	0x09,	    /*	__u8  bDeviceClass; HUB_CLASSCODE */
-	0x00,	    /*	__u8  bDeviceSubClass; */
-	0x00,	    /*	__u8  bDeviceProtocol; */
-	0x08,	    /*	__u8  bMaxPacketSize0; 8 Bytes */
-	0x00,	    /*	__u16 idVendor; */
-	0x00,
-	0x00,	    /*	__u16 idProduct; */
-	0x00,
-	0x00,	    /*	__u16 bcdDevice; */
-	0x00,
-	0x00,	    /*	__u8  iManufacturer; */
-	0x01,	    /*	__u8  iProduct; */
-	0x00,	    /*	__u8  iSerialNumber; */
-	0x01	    /*	__u8  bNumConfigurations; */
-};
-
-/* Configuration descriptor */
-static __u8 root_hub_config_des[] =
-{
-	0x09,	    /*	__u8  bLength; */
-	0x02,	    /*	__u8  bDescriptorType; Configuration */
-	0x19,	    /*	__u16 wTotalLength; */
-	0x00,
-	0x01,	    /*	__u8  bNumInterfaces; */
-	0x01,	    /*	__u8  bConfigurationValue; */
-	0x00,	    /*	__u8  iConfiguration; */
-	0x40,	    /*	__u8  bmAttributes;
-	 Bit 7: Bus-powered, 6: Self-powered, 5 Remote-wakwup, 4..0: resvd */
-	0x00,	    /*	__u8  MaxPower; */
-
-	/* interface */
-	0x09,	    /*	__u8  if_bLength; */
-	0x04,	    /*	__u8  if_bDescriptorType; Interface */
-	0x00,	    /*	__u8  if_bInterfaceNumber; */
-	0x00,	    /*	__u8  if_bAlternateSetting; */
-	0x01,	    /*	__u8  if_bNumEndpoints; */
-	0x09,	    /*	__u8  if_bInterfaceClass; HUB_CLASSCODE */
-	0x00,	    /*	__u8  if_bInterfaceSubClass; */
-	0x00,	    /*	__u8  if_bInterfaceProtocol; */
-	0x00,	    /*	__u8  if_iInterface; */
-
-	/* endpoint */
-	0x07,	    /*	__u8  ep_bLength; */
-	0x05,	    /*	__u8  ep_bDescriptorType; Endpoint */
-	0x81,	    /*	__u8  ep_bEndpointAddress; IN Endpoint 1 */
-	0x03,	    /*	__u8  ep_bmAttributes; Interrupt */
-	0x02,	    /*	__u16 ep_wMaxPacketSize; ((MAX_ROOT_PORTS + 1) / 8 */
-	0x00,
-	0xff	    /*	__u8  ep_bInterval; 255 ms */
-};
-
-static unsigned char root_hub_str_index0[] =
-{
-	0x04,			/*  __u8  bLength; */
-	0x03,			/*  __u8  bDescriptorType; String-descriptor */
-	0x09,			/*  __u8  lang ID */
-	0x04,			/*  __u8  lang ID */
-};
-
-static unsigned char root_hub_str_index1[] =
-{
-	28,			/*  __u8  bLength; */
-	0x03,			/*  __u8  bDescriptorType; String-descriptor */
-	'O',			/*  __u8  Unicode */
-	0,				/*  __u8  Unicode */
-	'H',			/*  __u8  Unicode */
-	0,				/*  __u8  Unicode */
-	'C',			/*  __u8  Unicode */
-	0,				/*  __u8  Unicode */
-	'I',			/*  __u8  Unicode */
-	0,				/*  __u8  Unicode */
-	' ',			/*  __u8  Unicode */
-	0,				/*  __u8  Unicode */
-	'R',			/*  __u8  Unicode */
-	0,				/*  __u8  Unicode */
-	'o',			/*  __u8  Unicode */
-	0,				/*  __u8  Unicode */
-	'o',			/*  __u8  Unicode */
-	0,				/*  __u8  Unicode */
-	't',			/*  __u8  Unicode */
-	0,				/*  __u8  Unicode */
-	' ',			/*  __u8  Unicode */
-	0,				/*  __u8  Unicode */
-	'H',			/*  __u8  Unicode */
-	0,				/*  __u8  Unicode */
-	'u',			/*  __u8  Unicode */
-	0,				/*  __u8  Unicode */
-	'b',			/*  __u8  Unicode */
-	0,				/*  __u8  Unicode */
-};
+#include <usbroothubdes.h>
 
 /* Hub class-specific descriptor is constructed dynamically */
 
@@ -1548,7 +1452,7 @@ int submit_common_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
 	}
 
 	dev->status = stat;
-	dev->act_len = transfer_len;
+	dev->act_len = urb->actual_length;
 
 #ifdef DEBUG
 	pkt_print(urb, dev, pipe, buffer, transfer_len,
@@ -1847,7 +1751,7 @@ static void hc_release_ohci(ohci_t *ohci)
  */
 static char ohci_inited = 0;
 
-int usb_lowlevel_init(int index, void **controller)
+int usb_lowlevel_init(int index, enum usb_init_type init, void **controller)
 {
 #ifdef CONFIG_PCI_OHCI
 	pci_dev_t pdev;
@@ -1861,7 +1765,7 @@ int usb_lowlevel_init(int index, void **controller)
 
 #ifdef CONFIG_SYS_USB_OHCI_BOARD_INIT
 	/*  board dependant init */
-	if (usb_board_init())
+	if (board_usb_init(index, USB_INIT_HOST))
 		return -1;
 #endif
 	memset(&gohci, 0, sizeof(ohci_t));
@@ -1918,7 +1822,7 @@ int usb_lowlevel_init(int index, void **controller)
 		err ("can't reset usb-%s", gohci.slot_name);
 #ifdef CONFIG_SYS_USB_OHCI_BOARD_INIT
 		/* board dependant cleanup */
-		usb_board_init_fail();
+		board_usb_cleanup(index, USB_INIT_HOST);
 #endif
 
 #ifdef CONFIG_SYS_USB_OHCI_CPU_INIT
diff --git a/drivers/usb/host/ohci-s3c24xx.c b/drivers/usb/host/ohci-s3c24xx.c
index 879ac16624..3c659c60c9 100644
--- a/drivers/usb/host/ohci-s3c24xx.c
+++ b/drivers/usb/host/ohci-s3c24xx.c
@@ -873,100 +873,7 @@ static int dl_done_list(struct ohci *ohci, struct td *td_list)
  * Virtual Root Hub
  *-------------------------------------------------------------------------*/
 
-/* Device descriptor */
-static __u8 root_hub_dev_des[] = {
-	0x12,	/*  __u8  bLength; */
-	0x01,	/*  __u8  bDescriptorType; Device */
-	0x10,	/*  __u16 bcdUSB; v1.1 */
-	0x01,
-	0x09,	/*  __u8  bDeviceClass; HUB_CLASSCODE */
-	0x00,	/*  __u8  bDeviceSubClass; */
-	0x00,	/*  __u8  bDeviceProtocol; */
-	0x08,	/*  __u8  bMaxPacketSize0; 8 Bytes */
-	0x00,	/*  __u16 idVendor; */
-	0x00,
-	0x00,	/*  __u16 idProduct; */
-	0x00,
-	0x00,	/*  __u16 bcdDevice; */
-	0x00,
-	0x00,	/*  __u8  iManufacturer; */
-	0x01,	/*  __u8  iProduct; */
-	0x00,	/*  __u8  iSerialNumber; */
-	0x01	/*  __u8  bNumConfigurations; */
-};
-
-/* Configuration descriptor */
-static __u8 root_hub_config_des[] = {
-	0x09,	/*  __u8  bLength; */
-	0x02,	/*  __u8  bDescriptorType; Configuration */
-	0x19,	/*  __u16 wTotalLength; */
-	0x00,
-	0x01,	/*  __u8  bNumInterfaces; */
-	0x01,	/*  __u8  bConfigurationValue; */
-	0x00,	/*  __u8  iConfiguration; */
-	0x40,	/*  __u8  bmAttributes;
-		   Bit 7: Bus-powered, 6: Self-powered,
-		   5 Remote-wakwup, 4..0: resvd */
-	0x00,	/*  __u8  MaxPower; */
-
-	/* interface */
-	0x09,	/*  __u8  if_bLength; */
-	0x04,	/*  __u8  if_bDescriptorType; Interface */
-	0x00,	/*  __u8  if_bInterfaceNumber; */
-	0x00,	/*  __u8  if_bAlternateSetting; */
-	0x01,	/*  __u8  if_bNumEndpoints; */
-	0x09,	/*  __u8  if_bInterfaceClass; HUB_CLASSCODE */
-	0x00,	/*  __u8  if_bInterfaceSubClass; */
-	0x00,	/*  __u8  if_bInterfaceProtocol; */
-	0x00,	/*  __u8  if_iInterface; */
-
-	/* endpoint */
-	0x07,	/*  __u8  ep_bLength; */
-	0x05,	/*  __u8  ep_bDescriptorType; Endpoint */
-	0x81,	/*  __u8  ep_bEndpointAddress; IN Endpoint 1 */
-	0x03,	/*  __u8  ep_bmAttributes; Interrupt */
-	0x02,	/*  __u16 ep_wMaxPacketSize; ((MAX_ROOT_PORTS + 1) / 8 */
-	0x00,
-	0xff	/*  __u8  ep_bInterval; 255 ms */
-};
-
-static unsigned char root_hub_str_index0[] = {
-	0x04,	/*  __u8  bLength; */
-	0x03,	/*  __u8  bDescriptorType; String-descriptor */
-	0x09,	/*  __u8  lang ID */
-	0x04,	/*  __u8  lang ID */
-};
-
-static unsigned char root_hub_str_index1[] = {
-	28,	/*  __u8  bLength; */
-	0x03,	/*  __u8  bDescriptorType; String-descriptor */
-	'O',	/*  __u8  Unicode */
-	0,	/*  __u8  Unicode */
-	'H',	/*  __u8  Unicode */
-	0,	/*  __u8  Unicode */
-	'C',	/*  __u8  Unicode */
-	0,	/*  __u8  Unicode */
-	'I',	/*  __u8  Unicode */
-	0,	/*  __u8  Unicode */
-	' ',	/*  __u8  Unicode */
-	0,	/*  __u8  Unicode */
-	'R',	/*  __u8  Unicode */
-	0,	/*  __u8  Unicode */
-	'o',	/*  __u8  Unicode */
-	0,	/*  __u8  Unicode */
-	'o',	/*  __u8  Unicode */
-	0,	/*  __u8  Unicode */
-	't',	/*  __u8  Unicode */
-	0,	/*  __u8  Unicode */
-	' ',	/*  __u8  Unicode */
-	0,	/*  __u8  Unicode */
-	'H',	/*  __u8  Unicode */
-	0,	/*  __u8  Unicode */
-	'u',	/*  __u8  Unicode */
-	0,	/*  __u8  Unicode */
-	'b',	/*  __u8  Unicode */
-	0,	/*  __u8  Unicode */
-};
+#include <usbroothubdes.h>
 
 /* Hub class-specific descriptor is constructed dynamically */
 
@@ -1642,7 +1549,7 @@ static void hc_release_ohci(struct ohci *ohci)
  */
 static char ohci_inited = 0;
 
-int usb_lowlevel_init(int index, void **controller)
+int usb_lowlevel_init(int index, enum usb_init_type init, void **controller)
 {
 	struct s3c24x0_clock_power *clk_power = s3c24x0_get_base_clock_power();
 	struct s3c24x0_gpio *gpio = s3c24x0_get_base_gpio();
diff --git a/drivers/usb/host/ohci.h b/drivers/usb/host/ohci.h
index d977e8ff3c..9a4a2c2475 100644
--- a/drivers/usb/host/ohci.h
+++ b/drivers/usb/host/ohci.h
@@ -19,14 +19,11 @@
 #endif /* CONFIG_SYS_OHCI_SWAP_REG_ACCESS */
 
 /* functions for doing board or CPU specific setup/cleanup */
-extern int usb_board_init(void);
-extern int usb_board_stop(void);
-extern int usb_board_init_fail(void);
-
-extern int usb_cpu_init(void);
-extern int usb_cpu_stop(void);
-extern int usb_cpu_init_fail(void);
+int usb_board_stop(void);
 
+int usb_cpu_init(void);
+int usb_cpu_stop(void);
+int usb_cpu_init_fail(void);
 
 static int cc_to_error[16] = {
 
diff --git a/drivers/usb/host/r8a66597-hcd.c b/drivers/usb/host/r8a66597-hcd.c
index b503b356ce..dfe5423b8a 100644
--- a/drivers/usb/host/r8a66597-hcd.c
+++ b/drivers/usb/host/r8a66597-hcd.c
@@ -557,109 +557,7 @@ static int check_usb_device_connecting(struct r8a66597 *r8a66597)
  * Virtual Root Hub
  *-------------------------------------------------------------------------*/
 
-/* Device descriptor */
-static __u8 root_hub_dev_des[] =
-{
-	0x12,	    /*	__u8  bLength; */
-	0x01,	    /*	__u8  bDescriptorType; Device */
-	0x10,	    /*	__u16 bcdUSB; v1.1 */
-	0x01,
-	0x09,	    /*	__u8  bDeviceClass; HUB_CLASSCODE */
-	0x00,	    /*	__u8  bDeviceSubClass; */
-	0x00,	    /*	__u8  bDeviceProtocol; */
-	0x08,	    /*	__u8  bMaxPacketSize0; 8 Bytes */
-	0x00,	    /*	__u16 idVendor; */
-	0x00,
-	0x00,	    /*	__u16 idProduct; */
-	0x00,
-	0x00,	    /*	__u16 bcdDevice; */
-	0x00,
-	0x00,	    /*	__u8  iManufacturer; */
-	0x01,	    /*	__u8  iProduct; */
-	0x00,	    /*	__u8  iSerialNumber; */
-	0x01	    /*	__u8  bNumConfigurations; */
-};
-
-/* Configuration descriptor */
-static __u8 root_hub_config_des[] =
-{
-	0x09,	    /*	__u8  bLength; */
-	0x02,	    /*	__u8  bDescriptorType; Configuration */
-	0x19,	    /*	__u16 wTotalLength; */
-	0x00,
-	0x01,	    /*	__u8  bNumInterfaces; */
-	0x01,	    /*	__u8  bConfigurationValue; */
-	0x00,	    /*	__u8  iConfiguration; */
-	0x40,	    /*	__u8  bmAttributes; */
-
-	0x00,	    /*	__u8  MaxPower; */
-
-	/* interface */
-	0x09,	    /*	__u8  if_bLength; */
-	0x04,	    /*	__u8  if_bDescriptorType; Interface */
-	0x00,	    /*	__u8  if_bInterfaceNumber; */
-	0x00,	    /*	__u8  if_bAlternateSetting; */
-	0x01,	    /*	__u8  if_bNumEndpoints; */
-	0x09,	    /*	__u8  if_bInterfaceClass; HUB_CLASSCODE */
-	0x00,	    /*	__u8  if_bInterfaceSubClass; */
-	0x00,	    /*	__u8  if_bInterfaceProtocol; */
-	0x00,	    /*	__u8  if_iInterface; */
-
-	/* endpoint */
-	0x07,	    /*	__u8  ep_bLength; */
-	0x05,	    /*	__u8  ep_bDescriptorType; Endpoint */
-	0x81,	    /*	__u8  ep_bEndpointAddress; IN Endpoint 1 */
-	0x03,	    /*	__u8  ep_bmAttributes; Interrupt */
-	0x02,	    /*	__u16 ep_wMaxPacketSize; ((MAX_ROOT_PORTS + 1) / 8 */
-	0x00,
-	0xff	    /*	__u8  ep_bInterval; 255 ms */
-};
-
-static unsigned char root_hub_str_index0[] =
-{
-	0x04,			/*  __u8  bLength; */
-	0x03,			/*  __u8  bDescriptorType; String-descriptor */
-	0x09,			/*  __u8  lang ID */
-	0x04,			/*  __u8  lang ID */
-};
-
-static unsigned char root_hub_str_index1[] =
-{
-	34,			/*  __u8  bLength; */
-	0x03,			/*  __u8  bDescriptorType; String-descriptor */
-	'R',			/*  __u8  Unicode */
-	0,				/*  __u8  Unicode */
-	'8',			/*  __u8  Unicode */
-	0,				/*  __u8  Unicode */
-	'A',			/*  __u8  Unicode */
-	0,				/*  __u8  Unicode */
-	'6',			/*  __u8  Unicode */
-	0,				/*  __u8  Unicode */
-	'6',			/*  __u8  Unicode */
-	0,				/*  __u8  Unicode */
-	'5',			/*  __u8  Unicode */
-	0,				/*  __u8  Unicode */
-	'9',			/*  __u8  Unicode */
-	0,				/*  __u8  Unicode */
-	'7',			/*  __u8  Unicode */
-	0,				/*  __u8  Unicode */
-	' ',			/*  __u8  Unicode */
-	0,				/*  __u8  Unicode */
-	'R',			/*  __u8  Unicode */
-	0,				/*  __u8  Unicode */
-	'o',			/*  __u8  Unicode */
-	0,				/*  __u8  Unicode */
-	'o',			/*  __u8  Unicode */
-	0,				/*  __u8  Unicode */
-	't',			/*  __u8  Unicode */
-	0,				/*  __u8  Unicode */
-	'H',			/*  __u8  Unicode */
-	0,				/*  __u8  Unicode */
-	'u',			/*  __u8  Unicode */
-	0,				/*  __u8  Unicode */
-	'b',			/*  __u8  Unicode */
-	0,				/*  __u8  Unicode */
-};
+#include <usbroothubdes.h>
 
 static int r8a66597_submit_rh_msg(struct usb_device *dev, unsigned long pipe,
 			void *buffer, int transfer_len, struct devrequest *cmd)
@@ -903,7 +801,7 @@ int submit_int_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
 	return 0;
 }
 
-int usb_lowlevel_init(int index, void **controller)
+int usb_lowlevel_init(int index, enum usb_init_type init, void **controller)
 {
 	struct r8a66597 *r8a66597 = &gr8a66597;
 
diff --git a/drivers/usb/host/sl811-hcd.c b/drivers/usb/host/sl811-hcd.c
index 7ff4ffd880..b29c67e189 100644
--- a/drivers/usb/host/sl811-hcd.c
+++ b/drivers/usb/host/sl811-hcd.c
@@ -194,7 +194,7 @@ static int sl811_hc_reset(void)
 	return 1;
 }
 
-int usb_lowlevel_init(int index, void **controller)
+int usb_lowlevel_init(int index, enum usb_init_type init, void **controller)
 {
 	root_hub_devnum = 0;
 	sl811_hc_reset();
diff --git a/drivers/usb/host/xhci-exynos5.c b/drivers/usb/host/xhci-exynos5.c
new file mode 100644
index 0000000000..1146d101de
--- /dev/null
+++ b/drivers/usb/host/xhci-exynos5.c
@@ -0,0 +1,327 @@
+/*
+ * SAMSUNG EXYNOS5 USB HOST XHCI Controller
+ *
+ * Copyright (C) 2012 Samsung Electronics Co.Ltd
+ *	Vivek Gautam <gautam.vivek@samsung.com>
+ *	Vikas Sajjan <vikas.sajjan@samsung.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * This file is a conglomeration for DWC3-init sequence and further
+ * exynos5 specific PHY-init sequence.
+ */
+
+#include <common.h>
+#include <fdtdec.h>
+#include <libfdt.h>
+#include <malloc.h>
+#include <usb.h>
+#include <watchdog.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/power.h>
+#include <asm/arch/xhci-exynos.h>
+#include <asm/gpio.h>
+#include <asm-generic/errno.h>
+#include <linux/compat.h>
+#include <linux/usb/dwc3.h>
+
+#include "xhci.h"
+
+/* Declare global data pointer */
+DECLARE_GLOBAL_DATA_PTR;
+
+/**
+ * Contains pointers to register base addresses
+ * for the usb controller.
+ */
+struct exynos_xhci {
+	struct exynos_usb3_phy *usb3_phy;
+	struct xhci_hccr *hcd;
+	struct dwc3 *dwc3_reg;
+	struct fdt_gpio_state vbus_gpio;
+};
+
+static struct exynos_xhci exynos;
+
+#ifdef CONFIG_OF_CONTROL
+static int exynos_usb3_parse_dt(const void *blob, struct exynos_xhci *exynos)
+{
+	fdt_addr_t addr;
+	unsigned int node;
+	int depth;
+
+	node = fdtdec_next_compatible(blob, 0, COMPAT_SAMSUNG_EXYNOS5_XHCI);
+	if (node <= 0) {
+		debug("XHCI: Can't get device node for xhci\n");
+		return -ENODEV;
+	}
+
+	/*
+	 * Get the base address for XHCI controller from the device node
+	 */
+	addr = fdtdec_get_addr(blob, node, "reg");
+	if (addr == FDT_ADDR_T_NONE) {
+		debug("Can't get the XHCI register base address\n");
+		return -ENXIO;
+	}
+	exynos->hcd = (struct xhci_hccr *)addr;
+
+	/* Vbus gpio */
+	fdtdec_decode_gpio(blob, node, "samsung,vbus-gpio", &exynos->vbus_gpio);
+
+	depth = 0;
+	node = fdtdec_next_compatible_subnode(blob, node,
+				COMPAT_SAMSUNG_EXYNOS5_USB3_PHY, &depth);
+	if (node <= 0) {
+		debug("XHCI: Can't get device node for usb3-phy controller\n");
+		return -ENODEV;
+	}
+
+	/*
+	 * Get the base address for usbphy from the device node
+	 */
+	exynos->usb3_phy = (struct exynos_usb3_phy *)fdtdec_get_addr(blob, node,
+								"reg");
+	if (exynos->usb3_phy == NULL) {
+		debug("Can't get the usbphy register address\n");
+		return -ENXIO;
+	}
+
+	return 0;
+}
+#endif
+
+static void exynos5_usb3_phy_init(struct exynos_usb3_phy *phy)
+{
+	u32 reg;
+
+	/* enabling usb_drd phy */
+	set_usbdrd_phy_ctrl(POWER_USB_DRD_PHY_CTRL_EN);
+
+	/* Reset USB 3.0 PHY */
+	writel(0x0, &phy->phy_reg0);
+
+	clrbits_le32(&phy->phy_param0,
+			/* Select PHY CLK source */
+			PHYPARAM0_REF_USE_PAD |
+			/* Set Loss-of-Signal Detector sensitivity */
+			PHYPARAM0_REF_LOSLEVEL_MASK);
+	setbits_le32(&phy->phy_param0, PHYPARAM0_REF_LOSLEVEL);
+
+	writel(0x0, &phy->phy_resume);
+
+	/*
+	 * Setting the Frame length Adj value[6:1] to default 0x20
+	 * See xHCI 1.0 spec, 5.2.4
+	 */
+	setbits_le32(&phy->link_system,
+			LINKSYSTEM_XHCI_VERSION_CONTROL |
+			LINKSYSTEM_FLADJ(0x20));
+
+	/* Set Tx De-Emphasis level */
+	clrbits_le32(&phy->phy_param1, PHYPARAM1_PCS_TXDEEMPH_MASK);
+	setbits_le32(&phy->phy_param1, PHYPARAM1_PCS_TXDEEMPH);
+
+	setbits_le32(&phy->phy_batchg, PHYBATCHG_UTMI_CLKSEL);
+
+	/* PHYTEST POWERDOWN Control */
+	clrbits_le32(&phy->phy_test,
+			PHYTEST_POWERDOWN_SSP |
+			PHYTEST_POWERDOWN_HSP);
+
+	/* UTMI Power Control */
+	writel(PHYUTMI_OTGDISABLE, &phy->phy_utmi);
+
+		/* Use core clock from main PLL */
+	reg = PHYCLKRST_REFCLKSEL_EXT_REFCLK |
+		/* Default 24Mhz crystal clock */
+		PHYCLKRST_FSEL(FSEL_CLKSEL_24M) |
+		PHYCLKRST_MPLL_MULTIPLIER_24MHZ_REF |
+		PHYCLKRST_SSC_REFCLKSEL(0x88) |
+		/* Force PortReset of PHY */
+		PHYCLKRST_PORTRESET |
+		/* Digital power supply in normal operating mode */
+		PHYCLKRST_RETENABLEN |
+		/* Enable ref clock for SS function */
+		PHYCLKRST_REF_SSP_EN |
+		/* Enable spread spectrum */
+		PHYCLKRST_SSC_EN |
+		/* Power down HS Bias and PLL blocks in suspend mode */
+		PHYCLKRST_COMMONONN;
+
+	writel(reg, &phy->phy_clk_rst);
+
+	/* giving time to Phy clock to settle before resetting */
+	udelay(10);
+
+	reg &= ~PHYCLKRST_PORTRESET;
+	writel(reg, &phy->phy_clk_rst);
+}
+
+static void exynos5_usb3_phy_exit(struct exynos_usb3_phy *phy)
+{
+	setbits_le32(&phy->phy_utmi,
+			PHYUTMI_OTGDISABLE |
+			PHYUTMI_FORCESUSPEND |
+			PHYUTMI_FORCESLEEP);
+
+	clrbits_le32(&phy->phy_clk_rst,
+			PHYCLKRST_REF_SSP_EN |
+			PHYCLKRST_SSC_EN |
+			PHYCLKRST_COMMONONN);
+
+	/* PHYTEST POWERDOWN Control to remove leakage current */
+	setbits_le32(&phy->phy_test,
+			PHYTEST_POWERDOWN_SSP |
+			PHYTEST_POWERDOWN_HSP);
+
+	/* disabling usb_drd phy */
+	set_usbdrd_phy_ctrl(POWER_USB_DRD_PHY_CTRL_DISABLE);
+}
+
+void dwc3_set_mode(struct dwc3 *dwc3_reg, u32 mode)
+{
+	clrsetbits_le32(&dwc3_reg->g_ctl,
+			DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG),
+			DWC3_GCTL_PRTCAPDIR(mode));
+}
+
+static void dwc3_core_soft_reset(struct dwc3 *dwc3_reg)
+{
+	/* Before Resetting PHY, put Core in Reset */
+	setbits_le32(&dwc3_reg->g_ctl,
+			DWC3_GCTL_CORESOFTRESET);
+
+	/* Assert USB3 PHY reset */
+	setbits_le32(&dwc3_reg->g_usb3pipectl[0],
+			DWC3_GUSB3PIPECTL_PHYSOFTRST);
+
+	/* Assert USB2 PHY reset */
+	setbits_le32(&dwc3_reg->g_usb2phycfg,
+			DWC3_GUSB2PHYCFG_PHYSOFTRST);
+
+	mdelay(100);
+
+	/* Clear USB3 PHY reset */
+	clrbits_le32(&dwc3_reg->g_usb3pipectl[0],
+			DWC3_GUSB3PIPECTL_PHYSOFTRST);
+
+	/* Clear USB2 PHY reset */
+	clrbits_le32(&dwc3_reg->g_usb2phycfg,
+			DWC3_GUSB2PHYCFG_PHYSOFTRST);
+
+	/* After PHYs are stable we can take Core out of reset state */
+	clrbits_le32(&dwc3_reg->g_ctl,
+			DWC3_GCTL_CORESOFTRESET);
+}
+
+static int dwc3_core_init(struct dwc3 *dwc3_reg)
+{
+	u32 reg;
+	u32 revision;
+	unsigned int dwc3_hwparams1;
+
+	revision = readl(&dwc3_reg->g_snpsid);
+	/* This should read as U3 followed by revision number */
+	if ((revision & DWC3_GSNPSID_MASK) != 0x55330000) {
+		puts("this is not a DesignWare USB3 DRD Core\n");
+		return -EINVAL;
+	}
+
+	dwc3_core_soft_reset(dwc3_reg);
+
+	dwc3_hwparams1 = readl(&dwc3_reg->g_hwparams1);
+
+	reg = readl(&dwc3_reg->g_ctl);
+	reg &= ~DWC3_GCTL_SCALEDOWN_MASK;
+	reg &= ~DWC3_GCTL_DISSCRAMBLE;
+	switch (DWC3_GHWPARAMS1_EN_PWROPT(dwc3_hwparams1)) {
+	case DWC3_GHWPARAMS1_EN_PWROPT_CLK:
+		reg &= ~DWC3_GCTL_DSBLCLKGTNG;
+		break;
+	default:
+		debug("No power optimization available\n");
+	}
+
+	/*
+	 * WORKAROUND: DWC3 revisions <1.90a have a bug
+	 * where the device can fail to connect at SuperSpeed
+	 * and falls back to high-speed mode which causes
+	 * the device to enter a Connect/Disconnect loop
+	 */
+	if ((revision & DWC3_REVISION_MASK) < 0x190a)
+		reg |= DWC3_GCTL_U2RSTECN;
+
+	writel(reg, &dwc3_reg->g_ctl);
+
+	return 0;
+}
+
+static int exynos_xhci_core_init(struct exynos_xhci *exynos)
+{
+	int ret;
+
+	exynos5_usb3_phy_init(exynos->usb3_phy);
+
+	ret = dwc3_core_init(exynos->dwc3_reg);
+	if (ret) {
+		debug("failed to initialize core\n");
+		return -EINVAL;
+	}
+
+	/* We are hard-coding DWC3 core to Host Mode */
+	dwc3_set_mode(exynos->dwc3_reg, DWC3_GCTL_PRTCAP_HOST);
+
+	return 0;
+}
+
+static void exynos_xhci_core_exit(struct exynos_xhci *exynos)
+{
+	exynos5_usb3_phy_exit(exynos->usb3_phy);
+}
+
+int xhci_hcd_init(int index, struct xhci_hccr **hccr, struct xhci_hcor **hcor)
+{
+	struct exynos_xhci *ctx = &exynos;
+	int ret;
+
+#ifdef CONFIG_OF_CONTROL
+	exynos_usb3_parse_dt(gd->fdt_blob, ctx);
+#else
+	ctx->usb3_phy = (struct exynos_usb3_phy *)samsung_get_base_usb3_phy();
+	ctx->hcd = (struct xhci_hccr *)samsung_get_base_usb_xhci();
+#endif
+
+	ctx->dwc3_reg = (struct dwc3 *)((char *)(ctx->hcd) + DWC3_REG_OFFSET);
+
+#ifdef CONFIG_OF_CONTROL
+	/* setup the Vbus gpio here */
+	if (!fdtdec_setup_gpio(&ctx->vbus_gpio))
+		gpio_direction_output(ctx->vbus_gpio.gpio, 1);
+#endif
+
+	ret = exynos_xhci_core_init(ctx);
+	if (ret) {
+		puts("XHCI: failed to initialize controller\n");
+		return -EINVAL;
+	}
+
+	*hccr = (ctx->hcd);
+	*hcor = (struct xhci_hcor *)((uint32_t) *hccr
+				+ HC_LENGTH(xhci_readl(&(*hccr)->cr_capbase)));
+
+	debug("Exynos5-xhci: init hccr %x and hcor %x hc_length %d\n",
+		(uint32_t)*hccr, (uint32_t)*hcor,
+		(uint32_t)HC_LENGTH(xhci_readl(&(*hccr)->cr_capbase)));
+
+	return 0;
+}
+
+void xhci_hcd_stop(int index)
+{
+	struct exynos_xhci *ctx = &exynos;
+
+	exynos_xhci_core_exit(ctx);
+}
diff --git a/drivers/usb/host/xhci-mem.c b/drivers/usb/host/xhci-mem.c
new file mode 100644
index 0000000000..89908e8a80
--- /dev/null
+++ b/drivers/usb/host/xhci-mem.c
@@ -0,0 +1,720 @@
+/*
+ * USB HOST XHCI Controller stack
+ *
+ * Based on xHCI host controller driver in linux-kernel
+ * by Sarah Sharp.
+ *
+ * Copyright (C) 2008 Intel Corp.
+ * Author: Sarah Sharp
+ *
+ * Copyright (C) 2013 Samsung Electronics Co.Ltd
+ * Authors: Vivek Gautam <gautam.vivek@samsung.com>
+ *	    Vikas Sajjan <vikas.sajjan@samsung.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/byteorder.h>
+#include <usb.h>
+#include <malloc.h>
+#include <asm/cache.h>
+#include <asm-generic/errno.h>
+
+#include "xhci.h"
+
+#define CACHELINE_SIZE		CONFIG_SYS_CACHELINE_SIZE
+/**
+ * flushes the address passed till the length
+ *
+ * @param addr	pointer to memory region to be flushed
+ * @param len	the length of the cache line to be flushed
+ * @return none
+ */
+void xhci_flush_cache(uint32_t addr, u32 len)
+{
+	BUG_ON((void *)addr == NULL || len == 0);
+
+	flush_dcache_range(addr & ~(CACHELINE_SIZE - 1),
+				ALIGN(addr + len, CACHELINE_SIZE));
+}
+
+/**
+ * invalidates the address passed till the length
+ *
+ * @param addr	pointer to memory region to be invalidates
+ * @param len	the length of the cache line to be invalidated
+ * @return none
+ */
+void xhci_inval_cache(uint32_t addr, u32 len)
+{
+	BUG_ON((void *)addr == NULL || len == 0);
+
+	invalidate_dcache_range(addr & ~(CACHELINE_SIZE - 1),
+				ALIGN(addr + len, CACHELINE_SIZE));
+}
+
+
+/**
+ * frees the "segment" pointer passed
+ *
+ * @param ptr	pointer to "segement" to be freed
+ * @return none
+ */
+static void xhci_segment_free(struct xhci_segment *seg)
+{
+	free(seg->trbs);
+	seg->trbs = NULL;
+
+	free(seg);
+}
+
+/**
+ * frees the "ring" pointer passed
+ *
+ * @param ptr	pointer to "ring" to be freed
+ * @return none
+ */
+static void xhci_ring_free(struct xhci_ring *ring)
+{
+	struct xhci_segment *seg;
+	struct xhci_segment *first_seg;
+
+	BUG_ON(!ring);
+
+	first_seg = ring->first_seg;
+	seg = first_seg->next;
+	while (seg != first_seg) {
+		struct xhci_segment *next = seg->next;
+		xhci_segment_free(seg);
+		seg = next;
+	}
+	xhci_segment_free(first_seg);
+
+	free(ring);
+}
+
+/**
+ * frees the "xhci_container_ctx" pointer passed
+ *
+ * @param ptr	pointer to "xhci_container_ctx" to be freed
+ * @return none
+ */
+static void xhci_free_container_ctx(struct xhci_container_ctx *ctx)
+{
+	free(ctx->bytes);
+	free(ctx);
+}
+
+/**
+ * frees the virtual devices for "xhci_ctrl" pointer passed
+ *
+ * @param ptr	pointer to "xhci_ctrl" whose virtual devices are to be freed
+ * @return none
+ */
+static void xhci_free_virt_devices(struct xhci_ctrl *ctrl)
+{
+	int i;
+	int slot_id;
+	struct xhci_virt_device *virt_dev;
+
+	/*
+	 * refactored here to loop through all virt_dev
+	 * Slot ID 0 is reserved
+	 */
+	for (slot_id = 0; slot_id < MAX_HC_SLOTS; slot_id++) {
+		virt_dev = ctrl->devs[slot_id];
+		if (!virt_dev)
+			continue;
+
+		ctrl->dcbaa->dev_context_ptrs[slot_id] = 0;
+
+		for (i = 0; i < 31; ++i)
+			if (virt_dev->eps[i].ring)
+				xhci_ring_free(virt_dev->eps[i].ring);
+
+		if (virt_dev->in_ctx)
+			xhci_free_container_ctx(virt_dev->in_ctx);
+		if (virt_dev->out_ctx)
+			xhci_free_container_ctx(virt_dev->out_ctx);
+
+		free(virt_dev);
+		/* make sure we are pointing to NULL */
+		ctrl->devs[slot_id] = NULL;
+	}
+}
+
+/**
+ * frees all the memory allocated
+ *
+ * @param ptr	pointer to "xhci_ctrl" to be cleaned up
+ * @return none
+ */
+void xhci_cleanup(struct xhci_ctrl *ctrl)
+{
+	xhci_ring_free(ctrl->event_ring);
+	xhci_ring_free(ctrl->cmd_ring);
+	xhci_free_virt_devices(ctrl);
+	free(ctrl->erst.entries);
+	free(ctrl->dcbaa);
+	memset(ctrl, '\0', sizeof(struct xhci_ctrl));
+}
+
+/**
+ * Malloc the aligned memory
+ *
+ * @param size	size of memory to be allocated
+ * @return allocates the memory and returns the aligned pointer
+ */
+static void *xhci_malloc(unsigned int size)
+{
+	void *ptr;
+	size_t cacheline_size = max(XHCI_ALIGNMENT, CACHELINE_SIZE);
+
+	ptr = memalign(cacheline_size, ALIGN(size, cacheline_size));
+	BUG_ON(!ptr);
+	memset(ptr, '\0', size);
+
+	xhci_flush_cache((uint32_t)ptr, size);
+
+	return ptr;
+}
+
+/**
+ * Make the prev segment point to the next segment.
+ * Change the last TRB in the prev segment to be a Link TRB which points to the
+ * address of the next segment.  The caller needs to set any Link TRB
+ * related flags, such as End TRB, Toggle Cycle, and no snoop.
+ *
+ * @param prev	pointer to the previous segment
+ * @param next	pointer to the next segment
+ * @param link_trbs	flag to indicate whether to link the trbs or NOT
+ * @return none
+ */
+static void xhci_link_segments(struct xhci_segment *prev,
+				struct xhci_segment *next, bool link_trbs)
+{
+	u32 val;
+	u64 val_64 = 0;
+
+	if (!prev || !next)
+		return;
+	prev->next = next;
+	if (link_trbs) {
+		val_64 = (uintptr_t)next->trbs;
+		prev->trbs[TRBS_PER_SEGMENT-1].link.segment_ptr = val_64;
+
+		/*
+		 * Set the last TRB in the segment to
+		 * have a TRB type ID of Link TRB
+		 */
+		val = le32_to_cpu(prev->trbs[TRBS_PER_SEGMENT-1].link.control);
+		val &= ~TRB_TYPE_BITMASK;
+		val |= (TRB_LINK << TRB_TYPE_SHIFT);
+
+		prev->trbs[TRBS_PER_SEGMENT-1].link.control = cpu_to_le32(val);
+	}
+}
+
+/**
+ * Initialises the Ring's enqueue,dequeue,enq_seg pointers
+ *
+ * @param ring	pointer to the RING to be intialised
+ * @return none
+ */
+static void xhci_initialize_ring_info(struct xhci_ring *ring)
+{
+	/*
+	 * The ring is empty, so the enqueue pointer == dequeue pointer
+	 */
+	ring->enqueue = ring->first_seg->trbs;
+	ring->enq_seg = ring->first_seg;
+	ring->dequeue = ring->enqueue;
+	ring->deq_seg = ring->first_seg;
+
+	/*
+	 * The ring is initialized to 0. The producer must write 1 to the
+	 * cycle bit to handover ownership of the TRB, so PCS = 1.
+	 * The consumer must compare CCS to the cycle bit to
+	 * check ownership, so CCS = 1.
+	 */
+	ring->cycle_state = 1;
+}
+
+/**
+ * Allocates a generic ring segment from the ring pool, sets the dma address,
+ * initializes the segment to zero, and sets the private next pointer to NULL.
+ * Section 4.11.1.1:
+ * "All components of all Command and Transfer TRBs shall be initialized to '0'"
+ *
+ * @param	none
+ * @return pointer to the newly allocated SEGMENT
+ */
+static struct xhci_segment *xhci_segment_alloc(void)
+{
+	struct xhci_segment *seg;
+
+	seg = (struct xhci_segment *)malloc(sizeof(struct xhci_segment));
+	BUG_ON(!seg);
+
+	seg->trbs = (union xhci_trb *)xhci_malloc(SEGMENT_SIZE);
+
+	seg->next = NULL;
+
+	return seg;
+}
+
+/**
+ * Create a new ring with zero or more segments.
+ * TODO: current code only uses one-time-allocated single-segment rings
+ * of 1KB anyway, so we might as well get rid of all the segment and
+ * linking code (and maybe increase the size a bit, e.g. 4KB).
+ *
+ *
+ * Link each segment together into a ring.
+ * Set the end flag and the cycle toggle bit on the last segment.
+ * See section 4.9.2 and figures 15 and 16 of XHCI spec rev1.0.
+ *
+ * @param num_segs	number of segments in the ring
+ * @param link_trbs	flag to indicate whether to link the trbs or NOT
+ * @return pointer to the newly created RING
+ */
+struct xhci_ring *xhci_ring_alloc(unsigned int num_segs, bool link_trbs)
+{
+	struct xhci_ring *ring;
+	struct xhci_segment *prev;
+
+	ring = (struct xhci_ring *)malloc(sizeof(struct xhci_ring));
+	BUG_ON(!ring);
+
+	if (num_segs == 0)
+		return ring;
+
+	ring->first_seg = xhci_segment_alloc();
+	BUG_ON(!ring->first_seg);
+
+	num_segs--;
+
+	prev = ring->first_seg;
+	while (num_segs > 0) {
+		struct xhci_segment *next;
+
+		next = xhci_segment_alloc();
+		BUG_ON(!next);
+
+		xhci_link_segments(prev, next, link_trbs);
+
+		prev = next;
+		num_segs--;
+	}
+	xhci_link_segments(prev, ring->first_seg, link_trbs);
+	if (link_trbs) {
+		/* See section 4.9.2.1 and 6.4.4.1 */
+		prev->trbs[TRBS_PER_SEGMENT-1].link.control |=
+					cpu_to_le32(LINK_TOGGLE);
+	}
+	xhci_initialize_ring_info(ring);
+
+	return ring;
+}
+
+/**
+ * Allocates the Container context
+ *
+ * @param ctrl	Host controller data structure
+ * @param type type of XHCI Container Context
+ * @return NULL if failed else pointer to the context on success
+ */
+static struct xhci_container_ctx
+		*xhci_alloc_container_ctx(struct xhci_ctrl *ctrl, int type)
+{
+	struct xhci_container_ctx *ctx;
+
+	ctx = (struct xhci_container_ctx *)
+		malloc(sizeof(struct xhci_container_ctx));
+	BUG_ON(!ctx);
+
+	BUG_ON((type != XHCI_CTX_TYPE_DEVICE) && (type != XHCI_CTX_TYPE_INPUT));
+	ctx->type = type;
+	ctx->size = (MAX_EP_CTX_NUM + 1) *
+			CTX_SIZE(readl(&ctrl->hccr->cr_hccparams));
+	if (type == XHCI_CTX_TYPE_INPUT)
+		ctx->size += CTX_SIZE(readl(&ctrl->hccr->cr_hccparams));
+
+	ctx->bytes = (u8 *)xhci_malloc(ctx->size);
+
+	return ctx;
+}
+
+/**
+ * Allocating virtual device
+ *
+ * @param udev	pointer to USB deivce structure
+ * @return 0 on success else -1 on failure
+ */
+int xhci_alloc_virt_device(struct usb_device *udev)
+{
+	u64 byte_64 = 0;
+	unsigned int slot_id = udev->slot_id;
+	struct xhci_virt_device *virt_dev;
+	struct xhci_ctrl *ctrl = udev->controller;
+
+	/* Slot ID 0 is reserved */
+	if (ctrl->devs[slot_id]) {
+		printf("Virt dev for slot[%d] already allocated\n", slot_id);
+		return -EEXIST;
+	}
+
+	ctrl->devs[slot_id] = (struct xhci_virt_device *)
+					malloc(sizeof(struct xhci_virt_device));
+
+	if (!ctrl->devs[slot_id]) {
+		puts("Failed to allocate virtual device\n");
+		return -ENOMEM;
+	}
+
+	memset(ctrl->devs[slot_id], 0, sizeof(struct xhci_virt_device));
+	virt_dev = ctrl->devs[slot_id];
+
+	/* Allocate the (output) device context that will be used in the HC. */
+	virt_dev->out_ctx = xhci_alloc_container_ctx(ctrl,
+					XHCI_CTX_TYPE_DEVICE);
+	if (!virt_dev->out_ctx) {
+		puts("Failed to allocate out context for virt dev\n");
+		return -ENOMEM;
+	}
+
+	/* Allocate the (input) device context for address device command */
+	virt_dev->in_ctx = xhci_alloc_container_ctx(ctrl,
+					XHCI_CTX_TYPE_INPUT);
+	if (!virt_dev->in_ctx) {
+		puts("Failed to allocate in context for virt dev\n");
+		return -ENOMEM;
+	}
+
+	/* Allocate endpoint 0 ring */
+	virt_dev->eps[0].ring = xhci_ring_alloc(1, true);
+
+	byte_64 = (uintptr_t)(virt_dev->out_ctx->bytes);
+
+	/* Point to output device context in dcbaa. */
+	ctrl->dcbaa->dev_context_ptrs[slot_id] = byte_64;
+
+	xhci_flush_cache((uint32_t)&ctrl->dcbaa->dev_context_ptrs[slot_id],
+							sizeof(__le64));
+	return 0;
+}
+
+/**
+ * Allocates the necessary data structures
+ * for XHCI host controller
+ *
+ * @param ctrl	Host controller data structure
+ * @param hccr	pointer to HOST Controller Control Registers
+ * @param hcor	pointer to HOST Controller Operational Registers
+ * @return 0 if successful else -1 on failure
+ */
+int xhci_mem_init(struct xhci_ctrl *ctrl, struct xhci_hccr *hccr,
+					struct xhci_hcor *hcor)
+{
+	uint64_t val_64;
+	uint64_t trb_64;
+	uint32_t val;
+	unsigned long deq;
+	int i;
+	struct xhci_segment *seg;
+
+	/* DCBAA initialization */
+	ctrl->dcbaa = (struct xhci_device_context_array *)
+			xhci_malloc(sizeof(struct xhci_device_context_array));
+	if (ctrl->dcbaa == NULL) {
+		puts("unable to allocate DCBA\n");
+		return -ENOMEM;
+	}
+
+	val_64 = (uintptr_t)ctrl->dcbaa;
+	/* Set the pointer in DCBAA register */
+	xhci_writeq(&hcor->or_dcbaap, val_64);
+
+	/* Command ring control pointer register initialization */
+	ctrl->cmd_ring = xhci_ring_alloc(1, true);
+
+	/* Set the address in the Command Ring Control register */
+	trb_64 = (uintptr_t)ctrl->cmd_ring->first_seg->trbs;
+	val_64 = xhci_readq(&hcor->or_crcr);
+	val_64 = (val_64 & (u64) CMD_RING_RSVD_BITS) |
+		(trb_64 & (u64) ~CMD_RING_RSVD_BITS) |
+		ctrl->cmd_ring->cycle_state;
+	xhci_writeq(&hcor->or_crcr, val_64);
+
+	/* write the address of db register */
+	val = xhci_readl(&hccr->cr_dboff);
+	val &= DBOFF_MASK;
+	ctrl->dba = (struct xhci_doorbell_array *)((char *)hccr + val);
+
+	/* write the address of runtime register */
+	val = xhci_readl(&hccr->cr_rtsoff);
+	val &= RTSOFF_MASK;
+	ctrl->run_regs = (struct xhci_run_regs *)((char *)hccr + val);
+
+	/* writting the address of ir_set structure */
+	ctrl->ir_set = &ctrl->run_regs->ir_set[0];
+
+	/* Event ring does not maintain link TRB */
+	ctrl->event_ring = xhci_ring_alloc(ERST_NUM_SEGS, false);
+	ctrl->erst.entries = (struct xhci_erst_entry *)
+		xhci_malloc(sizeof(struct xhci_erst_entry) * ERST_NUM_SEGS);
+
+	ctrl->erst.num_entries = ERST_NUM_SEGS;
+
+	for (val = 0, seg = ctrl->event_ring->first_seg;
+			val < ERST_NUM_SEGS;
+			val++) {
+		trb_64 = 0;
+		trb_64 = (uintptr_t)seg->trbs;
+		struct xhci_erst_entry *entry = &ctrl->erst.entries[val];
+		xhci_writeq(&entry->seg_addr, trb_64);
+		entry->seg_size = cpu_to_le32(TRBS_PER_SEGMENT);
+		entry->rsvd = 0;
+		seg = seg->next;
+	}
+	xhci_flush_cache((uint32_t)ctrl->erst.entries,
+			ERST_NUM_SEGS * sizeof(struct xhci_erst_entry));
+
+	deq = (unsigned long)ctrl->event_ring->dequeue;
+
+	/* Update HC event ring dequeue pointer */
+	xhci_writeq(&ctrl->ir_set->erst_dequeue,
+				(u64)deq & (u64)~ERST_PTR_MASK);
+
+	/* set ERST count with the number of entries in the segment table */
+	val = xhci_readl(&ctrl->ir_set->erst_size);
+	val &= ERST_SIZE_MASK;
+	val |= ERST_NUM_SEGS;
+	xhci_writel(&ctrl->ir_set->erst_size, val);
+
+	/* this is the event ring segment table pointer */
+	val_64 = xhci_readq(&ctrl->ir_set->erst_base);
+	val_64 &= ERST_PTR_MASK;
+	val_64 |= ((u32)(ctrl->erst.entries) & ~ERST_PTR_MASK);
+
+	xhci_writeq(&ctrl->ir_set->erst_base, val_64);
+
+	/* initializing the virtual devices to NULL */
+	for (i = 0; i < MAX_HC_SLOTS; ++i)
+		ctrl->devs[i] = NULL;
+
+	/*
+	 * Just Zero'ing this register completely,
+	 * or some spurious Device Notification Events
+	 * might screw things here.
+	 */
+	xhci_writel(&hcor->or_dnctrl, 0x0);
+
+	return 0;
+}
+
+/**
+ * Give the input control context for the passed container context
+ *
+ * @param ctx	pointer to the context
+ * @return pointer to the Input control context data
+ */
+struct xhci_input_control_ctx
+		*xhci_get_input_control_ctx(struct xhci_container_ctx *ctx)
+{
+	BUG_ON(ctx->type != XHCI_CTX_TYPE_INPUT);
+	return (struct xhci_input_control_ctx *)ctx->bytes;
+}
+
+/**
+ * Give the slot context for the passed container context
+ *
+ * @param ctrl	Host controller data structure
+ * @param ctx	pointer to the context
+ * @return pointer to the slot control context data
+ */
+struct xhci_slot_ctx *xhci_get_slot_ctx(struct xhci_ctrl *ctrl,
+				struct xhci_container_ctx *ctx)
+{
+	if (ctx->type == XHCI_CTX_TYPE_DEVICE)
+		return (struct xhci_slot_ctx *)ctx->bytes;
+
+	return (struct xhci_slot_ctx *)
+		(ctx->bytes + CTX_SIZE(readl(&ctrl->hccr->cr_hccparams)));
+}
+
+/**
+ * Gets the EP context from based on the ep_index
+ *
+ * @param ctrl	Host controller data structure
+ * @param ctx	context container
+ * @param ep_index	index of the endpoint
+ * @return pointer to the End point context
+ */
+struct xhci_ep_ctx *xhci_get_ep_ctx(struct xhci_ctrl *ctrl,
+				    struct xhci_container_ctx *ctx,
+				    unsigned int ep_index)
+{
+	/* increment ep index by offset of start of ep ctx array */
+	ep_index++;
+	if (ctx->type == XHCI_CTX_TYPE_INPUT)
+		ep_index++;
+
+	return (struct xhci_ep_ctx *)
+		(ctx->bytes +
+		(ep_index * CTX_SIZE(readl(&ctrl->hccr->cr_hccparams))));
+}
+
+/**
+ * Copy output xhci_ep_ctx to the input xhci_ep_ctx copy.
+ * Useful when you want to change one particular aspect of the endpoint
+ * and then issue a configure endpoint command.
+ *
+ * @param ctrl	Host controller data structure
+ * @param in_ctx contains the input context
+ * @param out_ctx contains the input context
+ * @param ep_index index of the end point
+ * @return none
+ */
+void xhci_endpoint_copy(struct xhci_ctrl *ctrl,
+			struct xhci_container_ctx *in_ctx,
+			struct xhci_container_ctx *out_ctx,
+			unsigned int ep_index)
+{
+	struct xhci_ep_ctx *out_ep_ctx;
+	struct xhci_ep_ctx *in_ep_ctx;
+
+	out_ep_ctx = xhci_get_ep_ctx(ctrl, out_ctx, ep_index);
+	in_ep_ctx = xhci_get_ep_ctx(ctrl, in_ctx, ep_index);
+
+	in_ep_ctx->ep_info = out_ep_ctx->ep_info;
+	in_ep_ctx->ep_info2 = out_ep_ctx->ep_info2;
+	in_ep_ctx->deq = out_ep_ctx->deq;
+	in_ep_ctx->tx_info = out_ep_ctx->tx_info;
+}
+
+/**
+ * Copy output xhci_slot_ctx to the input xhci_slot_ctx.
+ * Useful when you want to change one particular aspect of the endpoint
+ * and then issue a configure endpoint command.
+ * Only the context entries field matters, but
+ * we'll copy the whole thing anyway.
+ *
+ * @param ctrl	Host controller data structure
+ * @param in_ctx contains the inpout context
+ * @param out_ctx contains the inpout context
+ * @return none
+ */
+void xhci_slot_copy(struct xhci_ctrl *ctrl, struct xhci_container_ctx *in_ctx,
+					struct xhci_container_ctx *out_ctx)
+{
+	struct xhci_slot_ctx *in_slot_ctx;
+	struct xhci_slot_ctx *out_slot_ctx;
+
+	in_slot_ctx = xhci_get_slot_ctx(ctrl, in_ctx);
+	out_slot_ctx = xhci_get_slot_ctx(ctrl, out_ctx);
+
+	in_slot_ctx->dev_info = out_slot_ctx->dev_info;
+	in_slot_ctx->dev_info2 = out_slot_ctx->dev_info2;
+	in_slot_ctx->tt_info = out_slot_ctx->tt_info;
+	in_slot_ctx->dev_state = out_slot_ctx->dev_state;
+}
+
+/**
+ * Setup an xHCI virtual device for a Set Address command
+ *
+ * @param udev pointer to the Device Data Structure
+ * @return returns negative value on failure else 0 on success
+ */
+void xhci_setup_addressable_virt_dev(struct usb_device *udev)
+{
+	struct usb_device *hop = udev;
+	struct xhci_virt_device *virt_dev;
+	struct xhci_ep_ctx *ep0_ctx;
+	struct xhci_slot_ctx *slot_ctx;
+	u32 port_num = 0;
+	u64 trb_64 = 0;
+	struct xhci_ctrl *ctrl = udev->controller;
+
+	virt_dev = ctrl->devs[udev->slot_id];
+
+	BUG_ON(!virt_dev);
+
+	/* Extract the EP0 and Slot Ctrl */
+	ep0_ctx = xhci_get_ep_ctx(ctrl, virt_dev->in_ctx, 0);
+	slot_ctx = xhci_get_slot_ctx(ctrl, virt_dev->in_ctx);
+
+	/* Only the control endpoint is valid - one endpoint context */
+	slot_ctx->dev_info |= cpu_to_le32(LAST_CTX(1) | 0);
+
+	switch (udev->speed) {
+	case USB_SPEED_SUPER:
+		slot_ctx->dev_info |= cpu_to_le32(SLOT_SPEED_SS);
+		break;
+	case USB_SPEED_HIGH:
+		slot_ctx->dev_info |= cpu_to_le32(SLOT_SPEED_HS);
+		break;
+	case USB_SPEED_FULL:
+		slot_ctx->dev_info |= cpu_to_le32(SLOT_SPEED_FS);
+		break;
+	case USB_SPEED_LOW:
+		slot_ctx->dev_info |= cpu_to_le32(SLOT_SPEED_LS);
+		break;
+	default:
+		/* Speed was set earlier, this shouldn't happen. */
+		BUG();
+	}
+
+	/* Extract the root hub port number */
+	if (hop->parent)
+		while (hop->parent->parent)
+			hop = hop->parent;
+	port_num = hop->portnr;
+	debug("port_num = %d\n", port_num);
+
+	slot_ctx->dev_info2 |=
+			cpu_to_le32(((port_num & ROOT_HUB_PORT_MASK) <<
+				ROOT_HUB_PORT_SHIFT));
+
+	/* Step 4 - ring already allocated */
+	/* Step 5 */
+	ep0_ctx->ep_info2 = cpu_to_le32(CTRL_EP << EP_TYPE_SHIFT);
+	debug("SPEED = %d\n", udev->speed);
+
+	switch (udev->speed) {
+	case USB_SPEED_SUPER:
+		ep0_ctx->ep_info2 |= cpu_to_le32(((512 & MAX_PACKET_MASK) <<
+					MAX_PACKET_SHIFT));
+		debug("Setting Packet size = 512bytes\n");
+		break;
+	case USB_SPEED_HIGH:
+	/* USB core guesses at a 64-byte max packet first for FS devices */
+	case USB_SPEED_FULL:
+		ep0_ctx->ep_info2 |= cpu_to_le32(((64 & MAX_PACKET_MASK) <<
+					MAX_PACKET_SHIFT));
+		debug("Setting Packet size = 64bytes\n");
+		break;
+	case USB_SPEED_LOW:
+		ep0_ctx->ep_info2 |= cpu_to_le32(((8 & MAX_PACKET_MASK) <<
+					MAX_PACKET_SHIFT));
+		debug("Setting Packet size = 8bytes\n");
+		break;
+	default:
+		/* New speed? */
+		BUG();
+	}
+
+	/* EP 0 can handle "burst" sizes of 1, so Max Burst Size field is 0 */
+	ep0_ctx->ep_info2 |=
+			cpu_to_le32(((0 & MAX_BURST_MASK) << MAX_BURST_SHIFT) |
+			((3 & ERROR_COUNT_MASK) << ERROR_COUNT_SHIFT));
+
+	trb_64 = (uintptr_t)virt_dev->eps[0].ring->first_seg->trbs;
+	ep0_ctx->deq = cpu_to_le64(trb_64 | virt_dev->eps[0].ring->cycle_state);
+
+	/* Steps 7 and 8 were done in xhci_alloc_virt_device() */
+
+	xhci_flush_cache((uint32_t)ep0_ctx, sizeof(struct xhci_ep_ctx));
+	xhci_flush_cache((uint32_t)slot_ctx, sizeof(struct xhci_slot_ctx));
+}
diff --git a/drivers/usb/host/xhci-omap.c b/drivers/usb/host/xhci-omap.c
new file mode 100644
index 0000000000..e667810bb3
--- /dev/null
+++ b/drivers/usb/host/xhci-omap.c
@@ -0,0 +1,158 @@
+/*
+ * OMAP USB HOST xHCI Controller
+ *
+ * (C) Copyright 2013
+ * Texas Instruments, <www.ti.com>
+ *
+ * Author: Dan Murphy <dmurphy@ti.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <usb.h>
+#include <asm-generic/errno.h>
+#include <asm/omap_common.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/sys_proto.h>
+
+#include <linux/compat.h>
+#include <linux/usb/dwc3.h>
+#include <linux/usb/xhci-omap.h>
+
+#include "xhci.h"
+
+/* Declare global data pointer */
+DECLARE_GLOBAL_DATA_PTR;
+
+static struct omap_xhci omap;
+
+inline int __board_usb_init(int index, enum usb_init_type init)
+{
+	return 0;
+}
+int board_usb_init(int index, enum usb_init_type init)
+	__attribute__((weak, alias("__board_usb_init")));
+
+static void dwc3_set_mode(struct dwc3 *dwc3_reg, u32 mode)
+{
+	clrsetbits_le32(&dwc3_reg->g_ctl,
+			DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG),
+			DWC3_GCTL_PRTCAPDIR(mode));
+}
+
+static void dwc3_core_soft_reset(struct dwc3 *dwc3_reg)
+{
+	/* Before Resetting PHY, put Core in Reset */
+	setbits_le32(&dwc3_reg->g_ctl, DWC3_GCTL_CORESOFTRESET);
+
+	omap_reset_usb_phy(dwc3_reg);
+
+	/* After PHYs are stable we can take Core out of reset state */
+	clrbits_le32(&dwc3_reg->g_ctl, DWC3_GCTL_CORESOFTRESET);
+}
+
+static int dwc3_core_init(struct dwc3 *dwc3_reg)
+{
+	u32 reg;
+	u32 revision;
+	unsigned int dwc3_hwparams1;
+
+	revision = readl(&dwc3_reg->g_snpsid);
+	/* This should read as U3 followed by revision number */
+	if ((revision & DWC3_GSNPSID_MASK) != 0x55330000) {
+		puts("this is not a DesignWare USB3 DRD Core\n");
+		return -1;
+	}
+
+	dwc3_core_soft_reset(dwc3_reg);
+
+	dwc3_hwparams1 = readl(&dwc3_reg->g_hwparams1);
+
+	reg = readl(&dwc3_reg->g_ctl);
+	reg &= ~DWC3_GCTL_SCALEDOWN_MASK;
+	reg &= ~DWC3_GCTL_DISSCRAMBLE;
+	switch (DWC3_GHWPARAMS1_EN_PWROPT(dwc3_hwparams1)) {
+	case DWC3_GHWPARAMS1_EN_PWROPT_CLK:
+		reg &= ~DWC3_GCTL_DSBLCLKGTNG;
+		break;
+	default:
+		debug("No power optimization available\n");
+	}
+
+	/*
+	 * WORKAROUND: DWC3 revisions <1.90a have a bug
+	 * where the device can fail to connect at SuperSpeed
+	 * and falls back to high-speed mode which causes
+	 * the device to enter a Connect/Disconnect loop
+	 */
+	if ((revision & DWC3_REVISION_MASK) < 0x190a)
+		reg |= DWC3_GCTL_U2RSTECN;
+
+	writel(reg, &dwc3_reg->g_ctl);
+
+	return 0;
+}
+
+static int omap_xhci_core_init(struct omap_xhci *omap)
+{
+	int ret = 0;
+
+	omap_enable_phy(omap);
+
+	ret = dwc3_core_init(omap->dwc3_reg);
+	if (ret) {
+		debug("%s:failed to initialize core\n", __func__);
+		return ret;
+	}
+
+	/* We are hard-coding DWC3 core to Host Mode */
+	dwc3_set_mode(omap->dwc3_reg, DWC3_GCTL_PRTCAP_HOST);
+
+	return ret;
+}
+
+static void omap_xhci_core_exit(struct omap_xhci *omap)
+{
+	usb_phy_power(0);
+}
+
+int xhci_hcd_init(int index, struct xhci_hccr **hccr, struct xhci_hcor **hcor)
+{
+	struct omap_xhci *ctx = &omap;
+	int ret = 0;
+
+	ctx->hcd = (struct xhci_hccr *)OMAP_XHCI_BASE;
+	ctx->dwc3_reg = (struct dwc3 *)((char *)(ctx->hcd) + DWC3_REG_OFFSET);
+	ctx->usb3_phy = (struct omap_usb3_phy *)OMAP_OCP1_SCP_BASE;
+	ctx->otg_wrapper = (struct omap_dwc_wrapper *)OMAP_OTG_WRAPPER_BASE;
+
+	ret = board_usb_init(index, USB_INIT_HOST);
+	if (ret != 0) {
+		puts("Failed to initialize board for USB\n");
+		return ret;
+	}
+
+	ret = omap_xhci_core_init(ctx);
+	if (ret < 0) {
+		puts("Failed to initialize xhci\n");
+		return ret;
+	}
+
+	*hccr = (struct xhci_hccr *)(OMAP_XHCI_BASE);
+	*hcor = (struct xhci_hcor *)((uint32_t) *hccr
+				+ HC_LENGTH(xhci_readl(&(*hccr)->cr_capbase)));
+
+	debug("omap-xhci: init hccr %x and hcor %x hc_length %d\n",
+	      (uint32_t)*hccr, (uint32_t)*hcor,
+	      (uint32_t)HC_LENGTH(xhci_readl(&(*hccr)->cr_capbase)));
+
+	return ret;
+}
+
+void xhci_hcd_stop(int index)
+{
+	struct omap_xhci *ctx = &omap;
+
+	omap_xhci_core_exit(ctx);
+}
diff --git a/drivers/usb/host/xhci-ring.c b/drivers/usb/host/xhci-ring.c
new file mode 100644
index 0000000000..19c3ec6211
--- /dev/null
+++ b/drivers/usb/host/xhci-ring.c
@@ -0,0 +1,939 @@
+/*
+ * USB HOST XHCI Controller stack
+ *
+ * Based on xHCI host controller driver in linux-kernel
+ * by Sarah Sharp.
+ *
+ * Copyright (C) 2008 Intel Corp.
+ * Author: Sarah Sharp
+ *
+ * Copyright (C) 2013 Samsung Electronics Co.Ltd
+ * Authors: Vivek Gautam <gautam.vivek@samsung.com>
+ *	    Vikas Sajjan <vikas.sajjan@samsung.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/byteorder.h>
+#include <usb.h>
+#include <asm/unaligned.h>
+#include <asm-generic/errno.h>
+
+#include "xhci.h"
+
+/**
+ * Is this TRB a link TRB or was the last TRB the last TRB in this event ring
+ * segment?  I.e. would the updated event TRB pointer step off the end of the
+ * event seg ?
+ *
+ * @param ctrl	Host controller data structure
+ * @param ring	pointer to the ring
+ * @param seg	poniter to the segment to which TRB belongs
+ * @param trb	poniter to the ring trb
+ * @return 1 if this TRB a link TRB else 0
+ */
+static int last_trb(struct xhci_ctrl *ctrl, struct xhci_ring *ring,
+			struct xhci_segment *seg, union xhci_trb *trb)
+{
+	if (ring == ctrl->event_ring)
+		return trb == &seg->trbs[TRBS_PER_SEGMENT];
+	else
+		return TRB_TYPE_LINK_LE32(trb->link.control);
+}
+
+/**
+ * Does this link TRB point to the first segment in a ring,
+ * or was the previous TRB the last TRB on the last segment in the ERST?
+ *
+ * @param ctrl	Host controller data structure
+ * @param ring	pointer to the ring
+ * @param seg	poniter to the segment to which TRB belongs
+ * @param trb	poniter to the ring trb
+ * @return 1 if this TRB is the last TRB on the last segment else 0
+ */
+static bool last_trb_on_last_seg(struct xhci_ctrl *ctrl,
+				 struct xhci_ring *ring,
+				 struct xhci_segment *seg,
+				 union xhci_trb *trb)
+{
+	if (ring == ctrl->event_ring)
+		return ((trb == &seg->trbs[TRBS_PER_SEGMENT]) &&
+			(seg->next == ring->first_seg));
+	else
+		return le32_to_cpu(trb->link.control) & LINK_TOGGLE;
+}
+
+/**
+ * See Cycle bit rules. SW is the consumer for the event ring only.
+ * Don't make a ring full of link TRBs.  That would be dumb and this would loop.
+ *
+ * If we've just enqueued a TRB that is in the middle of a TD (meaning the
+ * chain bit is set), then set the chain bit in all the following link TRBs.
+ * If we've enqueued the last TRB in a TD, make sure the following link TRBs
+ * have their chain bit cleared (so that each Link TRB is a separate TD).
+ *
+ * Section 6.4.4.1 of the 0.95 spec says link TRBs cannot have the chain bit
+ * set, but other sections talk about dealing with the chain bit set.  This was
+ * fixed in the 0.96 specification errata, but we have to assume that all 0.95
+ * xHCI hardware can't handle the chain bit being cleared on a link TRB.
+ *
+ * @param ctrl	Host controller data structure
+ * @param ring	pointer to the ring
+ * @param more_trbs_coming	flag to indicate whether more trbs
+ *				are expected or NOT.
+ *				Will you enqueue more TRBs before calling
+ *				prepare_ring()?
+ * @return none
+ */
+static void inc_enq(struct xhci_ctrl *ctrl, struct xhci_ring *ring,
+						bool more_trbs_coming)
+{
+	u32 chain;
+	union xhci_trb *next;
+
+	chain = le32_to_cpu(ring->enqueue->generic.field[3]) & TRB_CHAIN;
+	next = ++(ring->enqueue);
+
+	/*
+	 * Update the dequeue pointer further if that was a link TRB or we're at
+	 * the end of an event ring segment (which doesn't have link TRBS)
+	 */
+	while (last_trb(ctrl, ring, ring->enq_seg, next)) {
+		if (ring != ctrl->event_ring) {
+			/*
+			 * If the caller doesn't plan on enqueueing more
+			 * TDs before ringing the doorbell, then we
+			 * don't want to give the link TRB to the
+			 * hardware just yet.  We'll give the link TRB
+			 * back in prepare_ring() just before we enqueue
+			 * the TD at the top of the ring.
+			 */
+			if (!chain && !more_trbs_coming)
+				break;
+
+			/*
+			 * If we're not dealing with 0.95 hardware or
+			 * isoc rings on AMD 0.96 host,
+			 * carry over the chain bit of the previous TRB
+			 * (which may mean the chain bit is cleared).
+			 */
+			next->link.control &= cpu_to_le32(~TRB_CHAIN);
+			next->link.control |= cpu_to_le32(chain);
+
+			next->link.control ^= cpu_to_le32(TRB_CYCLE);
+			xhci_flush_cache((uint32_t)next,
+						sizeof(union xhci_trb));
+		}
+		/* Toggle the cycle bit after the last ring segment. */
+		if (last_trb_on_last_seg(ctrl, ring,
+					ring->enq_seg, next))
+			ring->cycle_state = (ring->cycle_state ? 0 : 1);
+
+		ring->enq_seg = ring->enq_seg->next;
+		ring->enqueue = ring->enq_seg->trbs;
+		next = ring->enqueue;
+	}
+}
+
+/**
+ * See Cycle bit rules. SW is the consumer for the event ring only.
+ * Don't make a ring full of link TRBs.  That would be dumb and this would loop.
+ *
+ * @param ctrl	Host controller data structure
+ * @param ring	Ring whose Dequeue TRB pointer needs to be incremented.
+ * return none
+ */
+static void inc_deq(struct xhci_ctrl *ctrl, struct xhci_ring *ring)
+{
+	do {
+		/*
+		 * Update the dequeue pointer further if that was a link TRB or
+		 * we're at the end of an event ring segment (which doesn't have
+		 * link TRBS)
+		 */
+		if (last_trb(ctrl, ring, ring->deq_seg, ring->dequeue)) {
+			if (ring == ctrl->event_ring &&
+					last_trb_on_last_seg(ctrl, ring,
+						ring->deq_seg, ring->dequeue)) {
+				ring->cycle_state = (ring->cycle_state ? 0 : 1);
+			}
+			ring->deq_seg = ring->deq_seg->next;
+			ring->dequeue = ring->deq_seg->trbs;
+		} else {
+			ring->dequeue++;
+		}
+	} while (last_trb(ctrl, ring, ring->deq_seg, ring->dequeue));
+}
+
+/**
+ * Generic function for queueing a TRB on a ring.
+ * The caller must have checked to make sure there's room on the ring.
+ *
+ * @param	more_trbs_coming:   Will you enqueue more TRBs before calling
+ *				prepare_ring()?
+ * @param ctrl	Host controller data structure
+ * @param ring	pointer to the ring
+ * @param more_trbs_coming	flag to indicate whether more trbs
+ * @param trb_fields	pointer to trb field array containing TRB contents
+ * @return pointer to the enqueued trb
+ */
+static struct xhci_generic_trb *queue_trb(struct xhci_ctrl *ctrl,
+					  struct xhci_ring *ring,
+					  bool more_trbs_coming,
+					  unsigned int *trb_fields)
+{
+	struct xhci_generic_trb *trb;
+	int i;
+
+	trb = &ring->enqueue->generic;
+
+	for (i = 0; i < 4; i++)
+		trb->field[i] = cpu_to_le32(trb_fields[i]);
+
+	xhci_flush_cache((uint32_t)trb, sizeof(struct xhci_generic_trb));
+
+	inc_enq(ctrl, ring, more_trbs_coming);
+
+	return trb;
+}
+
+/**
+ * Does various checks on the endpoint ring, and makes it ready
+ * to queue num_trbs.
+ *
+ * @param ctrl		Host controller data structure
+ * @param ep_ring	pointer to the EP Transfer Ring
+ * @param ep_state	State of the End Point
+ * @return error code in case of invalid ep_state, 0 on success
+ */
+static int prepare_ring(struct xhci_ctrl *ctrl, struct xhci_ring *ep_ring,
+							u32 ep_state)
+{
+	union xhci_trb *next = ep_ring->enqueue;
+
+	/* Make sure the endpoint has been added to xHC schedule */
+	switch (ep_state) {
+	case EP_STATE_DISABLED:
+		/*
+		 * USB core changed config/interfaces without notifying us,
+		 * or hardware is reporting the wrong state.
+		 */
+		puts("WARN urb submitted to disabled ep\n");
+		return -ENOENT;
+	case EP_STATE_ERROR:
+		puts("WARN waiting for error on ep to be cleared\n");
+		return -EINVAL;
+	case EP_STATE_HALTED:
+		puts("WARN halted endpoint, queueing URB anyway.\n");
+	case EP_STATE_STOPPED:
+	case EP_STATE_RUNNING:
+		debug("EP STATE RUNNING.\n");
+		break;
+	default:
+		puts("ERROR unknown endpoint state for ep\n");
+		return -EINVAL;
+	}
+
+	while (last_trb(ctrl, ep_ring, ep_ring->enq_seg, next)) {
+		/*
+		 * If we're not dealing with 0.95 hardware or isoc rings
+		 * on AMD 0.96 host, clear the chain bit.
+		 */
+		next->link.control &= cpu_to_le32(~TRB_CHAIN);
+
+		next->link.control ^= cpu_to_le32(TRB_CYCLE);
+
+		xhci_flush_cache((uint32_t)next, sizeof(union xhci_trb));
+
+		/* Toggle the cycle bit after the last ring segment. */
+		if (last_trb_on_last_seg(ctrl, ep_ring,
+					ep_ring->enq_seg, next))
+			ep_ring->cycle_state = (ep_ring->cycle_state ? 0 : 1);
+		ep_ring->enq_seg = ep_ring->enq_seg->next;
+		ep_ring->enqueue = ep_ring->enq_seg->trbs;
+		next = ep_ring->enqueue;
+	}
+
+	return 0;
+}
+
+/**
+ * Generic function for queueing a command TRB on the command ring.
+ * Check to make sure there's room on the command ring for one command TRB.
+ *
+ * @param ctrl		Host controller data structure
+ * @param ptr		Pointer address to write in the first two fields (opt.)
+ * @param slot_id	Slot ID to encode in the flags field (opt.)
+ * @param ep_index	Endpoint index to encode in the flags field (opt.)
+ * @param cmd		Command type to enqueue
+ * @return none
+ */
+void xhci_queue_command(struct xhci_ctrl *ctrl, u8 *ptr, u32 slot_id,
+			u32 ep_index, trb_type cmd)
+{
+	u32 fields[4];
+	u64 val_64 = (uintptr_t)ptr;
+
+	BUG_ON(prepare_ring(ctrl, ctrl->cmd_ring, EP_STATE_RUNNING));
+
+	fields[0] = lower_32_bits(val_64);
+	fields[1] = upper_32_bits(val_64);
+	fields[2] = 0;
+	fields[3] = TRB_TYPE(cmd) | EP_ID_FOR_TRB(ep_index) |
+		    SLOT_ID_FOR_TRB(slot_id) | ctrl->cmd_ring->cycle_state;
+
+	queue_trb(ctrl, ctrl->cmd_ring, false, fields);
+
+	/* Ring the command ring doorbell */
+	xhci_writel(&ctrl->dba->doorbell[0], DB_VALUE_HOST);
+}
+
+/**
+ * The TD size is the number of bytes remaining in the TD (including this TRB),
+ * right shifted by 10.
+ * It must fit in bits 21:17, so it can't be bigger than 31.
+ *
+ * @param remainder	remaining packets to be sent
+ * @return remainder if remainder is less than max else max
+ */
+static u32 xhci_td_remainder(unsigned int remainder)
+{
+	u32 max = (1 << (21 - 17 + 1)) - 1;
+
+	if ((remainder >> 10) >= max)
+		return max << 17;
+	else
+		return (remainder >> 10) << 17;
+}
+
+/**
+ * Finds out the remanining packets to be sent
+ *
+ * @param running_total	total size sent so far
+ * @param trb_buff_len	length of the TRB Buffer
+ * @param total_packet_count	total packet count
+ * @param maxpacketsize		max packet size of current pipe
+ * @param num_trbs_left		number of TRBs left to be processed
+ * @return 0 if running_total or trb_buff_len is 0, else remainder
+ */
+static u32 xhci_v1_0_td_remainder(int running_total,
+				int trb_buff_len,
+				unsigned int total_packet_count,
+				int maxpacketsize,
+				unsigned int num_trbs_left)
+{
+	int packets_transferred;
+
+	/* One TRB with a zero-length data packet. */
+	if (num_trbs_left == 0 || (running_total == 0 && trb_buff_len == 0))
+		return 0;
+
+	/*
+	 * All the TRB queueing functions don't count the current TRB in
+	 * running_total.
+	 */
+	packets_transferred = (running_total + trb_buff_len) / maxpacketsize;
+
+	if ((total_packet_count - packets_transferred) > 31)
+		return 31 << 17;
+	return (total_packet_count - packets_transferred) << 17;
+}
+
+/**
+ * Ring the doorbell of the End Point
+ *
+ * @param udev		pointer to the USB device structure
+ * @param ep_index	index of the endpoint
+ * @param start_cycle	cycle flag of the first TRB
+ * @param start_trb	pionter to the first TRB
+ * @return none
+ */
+static void giveback_first_trb(struct usb_device *udev, int ep_index,
+				int start_cycle,
+				struct xhci_generic_trb *start_trb)
+{
+	struct xhci_ctrl *ctrl = udev->controller;
+
+	/*
+	 * Pass all the TRBs to the hardware at once and make sure this write
+	 * isn't reordered.
+	 */
+	if (start_cycle)
+		start_trb->field[3] |= cpu_to_le32(start_cycle);
+	else
+		start_trb->field[3] &= cpu_to_le32(~TRB_CYCLE);
+
+	xhci_flush_cache((uint32_t)start_trb, sizeof(struct xhci_generic_trb));
+
+	/* Ringing EP doorbell here */
+	xhci_writel(&ctrl->dba->doorbell[udev->slot_id],
+				DB_VALUE(ep_index, 0));
+
+	return;
+}
+
+/**** POLLING mechanism for XHCI ****/
+
+/**
+ * Finalizes a handled event TRB by advancing our dequeue pointer and giving
+ * the TRB back to the hardware for recycling. Must call this exactly once at
+ * the end of each event handler, and not touch the TRB again afterwards.
+ *
+ * @param ctrl	Host controller data structure
+ * @return none
+ */
+void xhci_acknowledge_event(struct xhci_ctrl *ctrl)
+{
+	/* Advance our dequeue pointer to the next event */
+	inc_deq(ctrl, ctrl->event_ring);
+
+	/* Inform the hardware */
+	xhci_writeq(&ctrl->ir_set->erst_dequeue,
+		(uintptr_t)ctrl->event_ring->dequeue | ERST_EHB);
+}
+
+/**
+ * Checks if there is a new event to handle on the event ring.
+ *
+ * @param ctrl	Host controller data structure
+ * @return 0 if failure else 1 on success
+ */
+static int event_ready(struct xhci_ctrl *ctrl)
+{
+	union xhci_trb *event;
+
+	xhci_inval_cache((uint32_t)ctrl->event_ring->dequeue,
+					sizeof(union xhci_trb));
+
+	event = ctrl->event_ring->dequeue;
+
+	/* Does the HC or OS own the TRB? */
+	if ((le32_to_cpu(event->event_cmd.flags) & TRB_CYCLE) !=
+		ctrl->event_ring->cycle_state)
+		return 0;
+
+	return 1;
+}
+
+/**
+ * Waits for a specific type of event and returns it. Discards unexpected
+ * events. Caller *must* call xhci_acknowledge_event() after it is finished
+ * processing the event, and must not access the returned pointer afterwards.
+ *
+ * @param ctrl		Host controller data structure
+ * @param expected	TRB type expected from Event TRB
+ * @return pointer to event trb
+ */
+union xhci_trb *xhci_wait_for_event(struct xhci_ctrl *ctrl, trb_type expected)
+{
+	trb_type type;
+	unsigned long ts = get_timer(0);
+
+	do {
+		union xhci_trb *event = ctrl->event_ring->dequeue;
+
+		if (!event_ready(ctrl))
+			continue;
+
+		type = TRB_FIELD_TO_TYPE(le32_to_cpu(event->event_cmd.flags));
+		if (type == expected)
+			return event;
+
+		if (type == TRB_PORT_STATUS)
+		/* TODO: remove this once enumeration has been reworked */
+			/*
+			 * Port status change events always have a
+			 * successful completion code
+			 */
+			BUG_ON(GET_COMP_CODE(
+				le32_to_cpu(event->generic.field[2])) !=
+								COMP_SUCCESS);
+		else
+			printf("Unexpected XHCI event TRB, skipping... "
+				"(%08x %08x %08x %08x)\n",
+				le32_to_cpu(event->generic.field[0]),
+				le32_to_cpu(event->generic.field[1]),
+				le32_to_cpu(event->generic.field[2]),
+				le32_to_cpu(event->generic.field[3]));
+
+		xhci_acknowledge_event(ctrl);
+	} while (get_timer(ts) < XHCI_TIMEOUT);
+
+	if (expected == TRB_TRANSFER)
+		return NULL;
+
+	printf("XHCI timeout on event type %d... cannot recover.\n", expected);
+	BUG();
+}
+
+/*
+ * Stops transfer processing for an endpoint and throws away all unprocessed
+ * TRBs by setting the xHC's dequeue pointer to our enqueue pointer. The next
+ * xhci_bulk_tx/xhci_ctrl_tx on this enpoint will add new transfers there and
+ * ring the doorbell, causing this endpoint to start working again.
+ * (Careful: This will BUG() when there was no transfer in progress. Shouldn't
+ * happen in practice for current uses and is too complicated to fix right now.)
+ */
+static void abort_td(struct usb_device *udev, int ep_index)
+{
+	struct xhci_ctrl *ctrl = udev->controller;
+	struct xhci_ring *ring =  ctrl->devs[udev->slot_id]->eps[ep_index].ring;
+	union xhci_trb *event;
+	u32 field;
+
+	xhci_queue_command(ctrl, NULL, udev->slot_id, ep_index, TRB_STOP_RING);
+
+	event = xhci_wait_for_event(ctrl, TRB_TRANSFER);
+	field = le32_to_cpu(event->trans_event.flags);
+	BUG_ON(TRB_TO_SLOT_ID(field) != udev->slot_id);
+	BUG_ON(TRB_TO_EP_INDEX(field) != ep_index);
+	BUG_ON(GET_COMP_CODE(le32_to_cpu(event->trans_event.transfer_len
+		!= COMP_STOP)));
+	xhci_acknowledge_event(ctrl);
+
+	event = xhci_wait_for_event(ctrl, TRB_COMPLETION);
+	BUG_ON(TRB_TO_SLOT_ID(le32_to_cpu(event->event_cmd.flags))
+		!= udev->slot_id || GET_COMP_CODE(le32_to_cpu(
+		event->event_cmd.status)) != COMP_SUCCESS);
+	xhci_acknowledge_event(ctrl);
+
+	xhci_queue_command(ctrl, (void *)((uintptr_t)ring->enqueue |
+		ring->cycle_state), udev->slot_id, ep_index, TRB_SET_DEQ);
+	event = xhci_wait_for_event(ctrl, TRB_COMPLETION);
+	BUG_ON(TRB_TO_SLOT_ID(le32_to_cpu(event->event_cmd.flags))
+		!= udev->slot_id || GET_COMP_CODE(le32_to_cpu(
+		event->event_cmd.status)) != COMP_SUCCESS);
+	xhci_acknowledge_event(ctrl);
+}
+
+static void record_transfer_result(struct usb_device *udev,
+				   union xhci_trb *event, int length)
+{
+	udev->act_len = min(length, length -
+		EVENT_TRB_LEN(le32_to_cpu(event->trans_event.transfer_len)));
+
+	switch (GET_COMP_CODE(le32_to_cpu(event->trans_event.transfer_len))) {
+	case COMP_SUCCESS:
+		BUG_ON(udev->act_len != length);
+		/* fallthrough */
+	case COMP_SHORT_TX:
+		udev->status = 0;
+		break;
+	case COMP_STALL:
+		udev->status = USB_ST_STALLED;
+		break;
+	case COMP_DB_ERR:
+	case COMP_TRB_ERR:
+		udev->status = USB_ST_BUF_ERR;
+		break;
+	case COMP_BABBLE:
+		udev->status = USB_ST_BABBLE_DET;
+		break;
+	default:
+		udev->status = 0x80;  /* USB_ST_TOO_LAZY_TO_MAKE_A_NEW_MACRO */
+	}
+}
+
+/**** Bulk and Control transfer methods ****/
+/**
+ * Queues up the BULK Request
+ *
+ * @param udev		pointer to the USB device structure
+ * @param pipe		contains the DIR_IN or OUT , devnum
+ * @param length	length of the buffer
+ * @param buffer	buffer to be read/written based on the request
+ * @return returns 0 if successful else -1 on failure
+ */
+int xhci_bulk_tx(struct usb_device *udev, unsigned long pipe,
+			int length, void *buffer)
+{
+	int num_trbs = 0;
+	struct xhci_generic_trb *start_trb;
+	bool first_trb = 0;
+	int start_cycle;
+	u32 field = 0;
+	u32 length_field = 0;
+	struct xhci_ctrl *ctrl = udev->controller;
+	int slot_id = udev->slot_id;
+	int ep_index;
+	struct xhci_virt_device *virt_dev;
+	struct xhci_ep_ctx *ep_ctx;
+	struct xhci_ring *ring;		/* EP transfer ring */
+	union xhci_trb *event;
+
+	int running_total, trb_buff_len;
+	unsigned int total_packet_count;
+	int maxpacketsize;
+	u64 addr;
+	int ret;
+	u32 trb_fields[4];
+	u64 val_64 = (uintptr_t)buffer;
+
+	debug("dev=%p, pipe=%lx, buffer=%p, length=%d\n",
+		udev, pipe, buffer, length);
+
+	ep_index = usb_pipe_ep_index(pipe);
+	virt_dev = ctrl->devs[slot_id];
+
+	xhci_inval_cache((uint32_t)virt_dev->out_ctx->bytes,
+					virt_dev->out_ctx->size);
+
+	ep_ctx = xhci_get_ep_ctx(ctrl, virt_dev->out_ctx, ep_index);
+
+	ring = virt_dev->eps[ep_index].ring;
+	/*
+	 * How much data is (potentially) left before the 64KB boundary?
+	 * XHCI Spec puts restriction( TABLE 49 and 6.4.1 section of XHCI Spec)
+	 * that the buffer should not span 64KB boundary. if so
+	 * we send request in more than 1 TRB by chaining them.
+	 */
+	running_total = TRB_MAX_BUFF_SIZE -
+			(lower_32_bits(val_64) & (TRB_MAX_BUFF_SIZE - 1));
+	trb_buff_len = running_total;
+	running_total &= TRB_MAX_BUFF_SIZE - 1;
+
+	/*
+	 * If there's some data on this 64KB chunk, or we have to send a
+	 * zero-length transfer, we need at least one TRB
+	 */
+	if (running_total != 0 || length == 0)
+		num_trbs++;
+
+	/* How many more 64KB chunks to transfer, how many more TRBs? */
+	while (running_total < length) {
+		num_trbs++;
+		running_total += TRB_MAX_BUFF_SIZE;
+	}
+
+	/*
+	 * XXX: Calling routine prepare_ring() called in place of
+	 * prepare_trasfer() as there in 'Linux' since we are not
+	 * maintaining multiple TDs/transfer at the same time.
+	 */
+	ret = prepare_ring(ctrl, ring,
+			   le32_to_cpu(ep_ctx->ep_info) & EP_STATE_MASK);
+	if (ret < 0)
+		return ret;
+
+	/*
+	 * Don't give the first TRB to the hardware (by toggling the cycle bit)
+	 * until we've finished creating all the other TRBs.  The ring's cycle
+	 * state may change as we enqueue the other TRBs, so save it too.
+	 */
+	start_trb = &ring->enqueue->generic;
+	start_cycle = ring->cycle_state;
+
+	running_total = 0;
+	maxpacketsize = usb_maxpacket(udev, pipe);
+
+	total_packet_count = DIV_ROUND_UP(length, maxpacketsize);
+
+	/* How much data is in the first TRB? */
+	/*
+	 * How much data is (potentially) left before the 64KB boundary?
+	 * XHCI Spec puts restriction( TABLE 49 and 6.4.1 section of XHCI Spec)
+	 * that the buffer should not span 64KB boundary. if so
+	 * we send request in more than 1 TRB by chaining them.
+	 */
+	addr = val_64;
+
+	if (trb_buff_len > length)
+		trb_buff_len = length;
+
+	first_trb = true;
+
+	/* flush the buffer before use */
+	xhci_flush_cache((uint32_t)buffer, length);
+
+	/* Queue the first TRB, even if it's zero-length */
+	do {
+		u32 remainder = 0;
+		field = 0;
+		/* Don't change the cycle bit of the first TRB until later */
+		if (first_trb) {
+			first_trb = false;
+			if (start_cycle == 0)
+				field |= TRB_CYCLE;
+		} else {
+			field |= ring->cycle_state;
+		}
+
+		/*
+		 * Chain all the TRBs together; clear the chain bit in the last
+		 * TRB to indicate it's the last TRB in the chain.
+		 */
+		if (num_trbs > 1)
+			field |= TRB_CHAIN;
+		else
+			field |= TRB_IOC;
+
+		/* Only set interrupt on short packet for IN endpoints */
+		if (usb_pipein(pipe))
+			field |= TRB_ISP;
+
+		/* Set the TRB length, TD size, and interrupter fields. */
+		if (HC_VERSION(xhci_readl(&ctrl->hccr->cr_capbase)) < 0x100)
+			remainder = xhci_td_remainder(length - running_total);
+		else
+			remainder = xhci_v1_0_td_remainder(running_total,
+							   trb_buff_len,
+							   total_packet_count,
+							   maxpacketsize,
+							   num_trbs - 1);
+
+		length_field = ((trb_buff_len & TRB_LEN_MASK) |
+				remainder |
+				((0 & TRB_INTR_TARGET_MASK) <<
+				TRB_INTR_TARGET_SHIFT));
+
+		trb_fields[0] = lower_32_bits(addr);
+		trb_fields[1] = upper_32_bits(addr);
+		trb_fields[2] = length_field;
+		trb_fields[3] = field | (TRB_NORMAL << TRB_TYPE_SHIFT);
+
+		queue_trb(ctrl, ring, (num_trbs > 1), trb_fields);
+
+		--num_trbs;
+
+		running_total += trb_buff_len;
+
+		/* Calculate length for next transfer */
+		addr += trb_buff_len;
+		trb_buff_len = min((length - running_total), TRB_MAX_BUFF_SIZE);
+	} while (running_total < length);
+
+	giveback_first_trb(udev, ep_index, start_cycle, start_trb);
+
+	event = xhci_wait_for_event(ctrl, TRB_TRANSFER);
+	if (!event) {
+		debug("XHCI bulk transfer timed out, aborting...\n");
+		abort_td(udev, ep_index);
+		udev->status = USB_ST_NAK_REC;  /* closest thing to a timeout */
+		udev->act_len = 0;
+		return -ETIMEDOUT;
+	}
+	field = le32_to_cpu(event->trans_event.flags);
+
+	BUG_ON(TRB_TO_SLOT_ID(field) != slot_id);
+	BUG_ON(TRB_TO_EP_INDEX(field) != ep_index);
+	BUG_ON(*(void **)(uintptr_t)le64_to_cpu(event->trans_event.buffer) -
+		buffer > (size_t)length);
+
+	record_transfer_result(udev, event, length);
+	xhci_acknowledge_event(ctrl);
+	xhci_inval_cache((uint32_t)buffer, length);
+
+	return (udev->status != USB_ST_NOT_PROC) ? 0 : -1;
+}
+
+/**
+ * Queues up the Control Transfer Request
+ *
+ * @param udev	pointer to the USB device structure
+ * @param pipe		contains the DIR_IN or OUT , devnum
+ * @param req		request type
+ * @param length	length of the buffer
+ * @param buffer	buffer to be read/written based on the request
+ * @return returns 0 if successful else error code on failure
+ */
+int xhci_ctrl_tx(struct usb_device *udev, unsigned long pipe,
+			struct devrequest *req,	int length,
+			void *buffer)
+{
+	int ret;
+	int start_cycle;
+	int num_trbs;
+	u32 field;
+	u32 length_field;
+	u64 buf_64 = 0;
+	struct xhci_generic_trb *start_trb;
+	struct xhci_ctrl *ctrl = udev->controller;
+	int slot_id = udev->slot_id;
+	int ep_index;
+	u32 trb_fields[4];
+	struct xhci_virt_device *virt_dev = ctrl->devs[slot_id];
+	struct xhci_ring *ep_ring;
+	union xhci_trb *event;
+
+	debug("req=%u (%#x), type=%u (%#x), value=%u (%#x), index=%u\n",
+		req->request, req->request,
+		req->requesttype, req->requesttype,
+		le16_to_cpu(req->value), le16_to_cpu(req->value),
+		le16_to_cpu(req->index));
+
+	ep_index = usb_pipe_ep_index(pipe);
+
+	ep_ring = virt_dev->eps[ep_index].ring;
+
+	/*
+	 * Check to see if the max packet size for the default control
+	 * endpoint changed during FS device enumeration
+	 */
+	if (udev->speed == USB_SPEED_FULL) {
+		ret = xhci_check_maxpacket(udev);
+		if (ret < 0)
+			return ret;
+	}
+
+	xhci_inval_cache((uint32_t)virt_dev->out_ctx->bytes,
+				virt_dev->out_ctx->size);
+
+	struct xhci_ep_ctx *ep_ctx = NULL;
+	ep_ctx = xhci_get_ep_ctx(ctrl, virt_dev->out_ctx, ep_index);
+
+	/* 1 TRB for setup, 1 for status */
+	num_trbs = 2;
+	/*
+	 * Don't need to check if we need additional event data and normal TRBs,
+	 * since data in control transfers will never get bigger than 16MB
+	 * XXX: can we get a buffer that crosses 64KB boundaries?
+	 */
+
+	if (length > 0)
+		num_trbs++;
+	/*
+	 * XXX: Calling routine prepare_ring() called in place of
+	 * prepare_trasfer() as there in 'Linux' since we are not
+	 * maintaining multiple TDs/transfer at the same time.
+	 */
+	ret = prepare_ring(ctrl, ep_ring,
+				le32_to_cpu(ep_ctx->ep_info) & EP_STATE_MASK);
+
+	if (ret < 0)
+		return ret;
+
+	/*
+	 * Don't give the first TRB to the hardware (by toggling the cycle bit)
+	 * until we've finished creating all the other TRBs.  The ring's cycle
+	 * state may change as we enqueue the other TRBs, so save it too.
+	 */
+	start_trb = &ep_ring->enqueue->generic;
+	start_cycle = ep_ring->cycle_state;
+
+	debug("start_trb %p, start_cycle %d\n", start_trb, start_cycle);
+
+	/* Queue setup TRB - see section 6.4.1.2.1 */
+	/* FIXME better way to translate setup_packet into two u32 fields? */
+	field = 0;
+	field |= TRB_IDT | (TRB_SETUP << TRB_TYPE_SHIFT);
+	if (start_cycle == 0)
+		field |= 0x1;
+
+	/* xHCI 1.0 6.4.1.2.1: Transfer Type field */
+	if (HC_VERSION(xhci_readl(&ctrl->hccr->cr_capbase)) == 0x100) {
+		if (length > 0) {
+			if (req->requesttype & USB_DIR_IN)
+				field |= (TRB_DATA_IN << TRB_TX_TYPE_SHIFT);
+			else
+				field |= (TRB_DATA_OUT << TRB_TX_TYPE_SHIFT);
+		}
+	}
+
+	debug("req->requesttype = %d, req->request = %d,"
+		"le16_to_cpu(req->value) = %d,"
+		"le16_to_cpu(req->index) = %d,"
+		"le16_to_cpu(req->length) = %d\n",
+		req->requesttype, req->request, le16_to_cpu(req->value),
+		le16_to_cpu(req->index), le16_to_cpu(req->length));
+
+	trb_fields[0] = req->requesttype | req->request << 8 |
+				le16_to_cpu(req->value) << 16;
+	trb_fields[1] = le16_to_cpu(req->index) |
+			le16_to_cpu(req->length) << 16;
+	/* TRB_LEN | (TRB_INTR_TARGET) */
+	trb_fields[2] = (8 | ((0 & TRB_INTR_TARGET_MASK) <<
+			TRB_INTR_TARGET_SHIFT));
+	/* Immediate data in pointer */
+	trb_fields[3] = field;
+	queue_trb(ctrl, ep_ring, true, trb_fields);
+
+	/* Re-initializing field to zero */
+	field = 0;
+	/* If there's data, queue data TRBs */
+	/* Only set interrupt on short packet for IN endpoints */
+	if (usb_pipein(pipe))
+		field = TRB_ISP | (TRB_DATA << TRB_TYPE_SHIFT);
+	else
+		field = (TRB_DATA << TRB_TYPE_SHIFT);
+
+	length_field = (length & TRB_LEN_MASK) | xhci_td_remainder(length) |
+			((0 & TRB_INTR_TARGET_MASK) << TRB_INTR_TARGET_SHIFT);
+	debug("length_field = %d, length = %d,"
+		"xhci_td_remainder(length) = %d , TRB_INTR_TARGET(0) = %d\n",
+		length_field, (length & TRB_LEN_MASK),
+		xhci_td_remainder(length), 0);
+
+	if (length > 0) {
+		if (req->requesttype & USB_DIR_IN)
+			field |= TRB_DIR_IN;
+		buf_64 = (uintptr_t)buffer;
+
+		trb_fields[0] = lower_32_bits(buf_64);
+		trb_fields[1] = upper_32_bits(buf_64);
+		trb_fields[2] = length_field;
+		trb_fields[3] = field | ep_ring->cycle_state;
+
+		xhci_flush_cache((uint32_t)buffer, length);
+		queue_trb(ctrl, ep_ring, true, trb_fields);
+	}
+
+	/*
+	 * Queue status TRB -
+	 * see Table 7 and sections 4.11.2.2 and 6.4.1.2.3
+	 */
+
+	/* If the device sent data, the status stage is an OUT transfer */
+	field = 0;
+	if (length > 0 && req->requesttype & USB_DIR_IN)
+		field = 0;
+	else
+		field = TRB_DIR_IN;
+
+	trb_fields[0] = 0;
+	trb_fields[1] = 0;
+	trb_fields[2] = ((0 & TRB_INTR_TARGET_MASK) << TRB_INTR_TARGET_SHIFT);
+		/* Event on completion */
+	trb_fields[3] = field | TRB_IOC |
+			(TRB_STATUS << TRB_TYPE_SHIFT) |
+			ep_ring->cycle_state;
+
+	queue_trb(ctrl, ep_ring, false, trb_fields);
+
+	giveback_first_trb(udev, ep_index, start_cycle, start_trb);
+
+	event = xhci_wait_for_event(ctrl, TRB_TRANSFER);
+	if (!event)
+		goto abort;
+	field = le32_to_cpu(event->trans_event.flags);
+
+	BUG_ON(TRB_TO_SLOT_ID(field) != slot_id);
+	BUG_ON(TRB_TO_EP_INDEX(field) != ep_index);
+
+	record_transfer_result(udev, event, length);
+	xhci_acknowledge_event(ctrl);
+
+	/* Invalidate buffer to make it available to usb-core */
+	if (length > 0)
+		xhci_inval_cache((uint32_t)buffer, length);
+
+	if (GET_COMP_CODE(le32_to_cpu(event->trans_event.transfer_len))
+			== COMP_SHORT_TX) {
+		/* Short data stage, clear up additional status stage event */
+		event = xhci_wait_for_event(ctrl, TRB_TRANSFER);
+		if (!event)
+			goto abort;
+		BUG_ON(TRB_TO_SLOT_ID(field) != slot_id);
+		BUG_ON(TRB_TO_EP_INDEX(field) != ep_index);
+		xhci_acknowledge_event(ctrl);
+	}
+
+	return (udev->status != USB_ST_NOT_PROC) ? 0 : -1;
+
+abort:
+	debug("XHCI control transfer timed out, aborting...\n");
+	abort_td(udev, ep_index);
+	udev->status = USB_ST_NAK_REC;
+	udev->act_len = 0;
+	return -ETIMEDOUT;
+}
diff --git a/drivers/usb/host/xhci.c b/drivers/usb/host/xhci.c
new file mode 100644
index 0000000000..d1c2e5c455
--- /dev/null
+++ b/drivers/usb/host/xhci.c
@@ -0,0 +1,1030 @@
+/*
+ * USB HOST XHCI Controller stack
+ *
+ * Based on xHCI host controller driver in linux-kernel
+ * by Sarah Sharp.
+ *
+ * Copyright (C) 2008 Intel Corp.
+ * Author: Sarah Sharp
+ *
+ * Copyright (C) 2013 Samsung Electronics Co.Ltd
+ * Authors: Vivek Gautam <gautam.vivek@samsung.com>
+ *	    Vikas Sajjan <vikas.sajjan@samsung.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/**
+ * This file gives the xhci stack for usb3.0 looking into
+ * xhci specification Rev1.0 (5/21/10).
+ * The quirk devices support hasn't been given yet.
+ */
+
+#include <common.h>
+#include <asm/byteorder.h>
+#include <usb.h>
+#include <malloc.h>
+#include <watchdog.h>
+#include <asm/cache.h>
+#include <asm/unaligned.h>
+#include <asm-generic/errno.h>
+#include "xhci.h"
+
+#ifndef CONFIG_USB_MAX_CONTROLLER_COUNT
+#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
+#endif
+
+static struct descriptor {
+	struct usb_hub_descriptor hub;
+	struct usb_device_descriptor device;
+	struct usb_config_descriptor config;
+	struct usb_interface_descriptor interface;
+	struct usb_endpoint_descriptor endpoint;
+	struct usb_ss_ep_comp_descriptor ep_companion;
+} __attribute__ ((packed)) descriptor = {
+	{
+		0xc,		/* bDescLength */
+		0x2a,		/* bDescriptorType: hub descriptor */
+		2,		/* bNrPorts -- runtime modified */
+		cpu_to_le16(0x8), /* wHubCharacteristics */
+		10,		/* bPwrOn2PwrGood */
+		0,		/* bHubCntrCurrent */
+		{},		/* Device removable */
+		{}		/* at most 7 ports! XXX */
+	},
+	{
+		0x12,		/* bLength */
+		1,		/* bDescriptorType: UDESC_DEVICE */
+		cpu_to_le16(0x0300), /* bcdUSB: v3.0 */
+		9,		/* bDeviceClass: UDCLASS_HUB */
+		0,		/* bDeviceSubClass: UDSUBCLASS_HUB */
+		3,		/* bDeviceProtocol: UDPROTO_SSHUBSTT */
+		9,		/* bMaxPacketSize: 512 bytes  2^9 */
+		0x0000,		/* idVendor */
+		0x0000,		/* idProduct */
+		cpu_to_le16(0x0100), /* bcdDevice */
+		1,		/* iManufacturer */
+		2,		/* iProduct */
+		0,		/* iSerialNumber */
+		1		/* bNumConfigurations: 1 */
+	},
+	{
+		0x9,
+		2,		/* bDescriptorType: UDESC_CONFIG */
+		cpu_to_le16(0x1f), /* includes SS endpoint descriptor */
+		1,		/* bNumInterface */
+		1,		/* bConfigurationValue */
+		0,		/* iConfiguration */
+		0x40,		/* bmAttributes: UC_SELF_POWER */
+		0		/* bMaxPower */
+	},
+	{
+		0x9,		/* bLength */
+		4,		/* bDescriptorType: UDESC_INTERFACE */
+		0,		/* bInterfaceNumber */
+		0,		/* bAlternateSetting */
+		1,		/* bNumEndpoints */
+		9,		/* bInterfaceClass: UICLASS_HUB */
+		0,		/* bInterfaceSubClass: UISUBCLASS_HUB */
+		0,		/* bInterfaceProtocol: UIPROTO_HSHUBSTT */
+		0		/* iInterface */
+	},
+	{
+		0x7,		/* bLength */
+		5,		/* bDescriptorType: UDESC_ENDPOINT */
+		0x81,		/* bEndpointAddress: IN endpoint 1 */
+		3,		/* bmAttributes: UE_INTERRUPT */
+		8,		/* wMaxPacketSize */
+		255		/* bInterval */
+	},
+	{
+		0x06,		/* ss_bLength */
+		0x30,		/* ss_bDescriptorType: SS EP Companion */
+		0x00,		/* ss_bMaxBurst: allows 1 TX between ACKs */
+		/* ss_bmAttributes: 1 packet per service interval */
+		0x00,
+		/* ss_wBytesPerInterval: 15 bits for max 15 ports */
+		cpu_to_le16(0x02),
+	},
+};
+
+static struct xhci_ctrl xhcic[CONFIG_USB_MAX_CONTROLLER_COUNT];
+
+/**
+ * Waits for as per specified amount of time
+ * for the "result" to match with "done"
+ *
+ * @param ptr	pointer to the register to be read
+ * @param mask	mask for the value read
+ * @param done	value to be campared with result
+ * @param usec	time to wait till
+ * @return 0 if handshake is success else < 0 on failure
+ */
+static int handshake(uint32_t volatile *ptr, uint32_t mask,
+					uint32_t done, int usec)
+{
+	uint32_t result;
+
+	do {
+		result = xhci_readl(ptr);
+		if (result == ~(uint32_t)0)
+			return -ENODEV;
+		result &= mask;
+		if (result == done)
+			return 0;
+		usec--;
+		udelay(1);
+	} while (usec > 0);
+
+	return -ETIMEDOUT;
+}
+
+/**
+ * Set the run bit and wait for the host to be running.
+ *
+ * @param hcor	pointer to host controller operation registers
+ * @return status of the Handshake
+ */
+static int xhci_start(struct xhci_hcor *hcor)
+{
+	u32 temp;
+	int ret;
+
+	puts("Starting the controller\n");
+	temp = xhci_readl(&hcor->or_usbcmd);
+	temp |= (CMD_RUN);
+	xhci_writel(&hcor->or_usbcmd, temp);
+
+	/*
+	 * Wait for the HCHalted Status bit to be 0 to indicate the host is
+	 * running.
+	 */
+	ret = handshake(&hcor->or_usbsts, STS_HALT, 0, XHCI_MAX_HALT_USEC);
+	if (ret)
+		debug("Host took too long to start, "
+				"waited %u microseconds.\n",
+				XHCI_MAX_HALT_USEC);
+	return ret;
+}
+
+/**
+ * Resets the XHCI Controller
+ *
+ * @param hcor	pointer to host controller operation registers
+ * @return -EBUSY if XHCI Controller is not halted else status of handshake
+ */
+int xhci_reset(struct xhci_hcor *hcor)
+{
+	u32 cmd;
+	u32 state;
+	int ret;
+
+	/* Halting the Host first */
+	debug("// Halt the HC\n");
+	state = xhci_readl(&hcor->or_usbsts) & STS_HALT;
+	if (!state) {
+		cmd = xhci_readl(&hcor->or_usbcmd);
+		cmd &= ~CMD_RUN;
+		xhci_writel(&hcor->or_usbcmd, cmd);
+	}
+
+	ret = handshake(&hcor->or_usbsts,
+			STS_HALT, STS_HALT, XHCI_MAX_HALT_USEC);
+	if (ret) {
+		printf("Host not halted after %u microseconds.\n",
+				XHCI_MAX_HALT_USEC);
+		return -EBUSY;
+	}
+
+	debug("// Reset the HC\n");
+	cmd = xhci_readl(&hcor->or_usbcmd);
+	cmd |= CMD_RESET;
+	xhci_writel(&hcor->or_usbcmd, cmd);
+
+	ret = handshake(&hcor->or_usbcmd, CMD_RESET, 0, XHCI_MAX_RESET_USEC);
+	if (ret)
+		return ret;
+
+	/*
+	 * xHCI cannot write to any doorbells or operational registers other
+	 * than status until the "Controller Not Ready" flag is cleared.
+	 */
+	return handshake(&hcor->or_usbsts, STS_CNR, 0, XHCI_MAX_RESET_USEC);
+}
+
+/**
+ * Used for passing endpoint bitmasks between the core and HCDs.
+ * Find the index for an endpoint given its descriptor.
+ * Use the return value to right shift 1 for the bitmask.
+ *
+ * Index  = (epnum * 2) + direction - 1,
+ * where direction = 0 for OUT, 1 for IN.
+ * For control endpoints, the IN index is used (OUT index is unused), so
+ * index = (epnum * 2) + direction - 1 = (epnum * 2) + 1 - 1 = (epnum * 2)
+ *
+ * @param desc	USB enpdoint Descriptor
+ * @return index of the Endpoint
+ */
+static unsigned int xhci_get_ep_index(struct usb_endpoint_descriptor *desc)
+{
+	unsigned int index;
+
+	if (usb_endpoint_xfer_control(desc))
+		index = (unsigned int)(usb_endpoint_num(desc) * 2);
+	else
+		index = (unsigned int)((usb_endpoint_num(desc) * 2) -
+				(usb_endpoint_dir_in(desc) ? 0 : 1));
+
+	return index;
+}
+
+/**
+ * Issue a configure endpoint command or evaluate context command
+ * and wait for it to finish.
+ *
+ * @param udev	pointer to the Device Data Structure
+ * @param ctx_change	flag to indicate the Context has changed or NOT
+ * @return 0 on success, -1 on failure
+ */
+static int xhci_configure_endpoints(struct usb_device *udev, bool ctx_change)
+{
+	struct xhci_container_ctx *in_ctx;
+	struct xhci_virt_device *virt_dev;
+	struct xhci_ctrl *ctrl = udev->controller;
+	union xhci_trb *event;
+
+	virt_dev = ctrl->devs[udev->slot_id];
+	in_ctx = virt_dev->in_ctx;
+
+	xhci_flush_cache((uint32_t)in_ctx->bytes, in_ctx->size);
+	xhci_queue_command(ctrl, in_ctx->bytes, udev->slot_id, 0,
+			   ctx_change ? TRB_EVAL_CONTEXT : TRB_CONFIG_EP);
+	event = xhci_wait_for_event(ctrl, TRB_COMPLETION);
+	BUG_ON(TRB_TO_SLOT_ID(le32_to_cpu(event->event_cmd.flags))
+		!= udev->slot_id);
+
+	switch (GET_COMP_CODE(le32_to_cpu(event->event_cmd.status))) {
+	case COMP_SUCCESS:
+		debug("Successful %s command\n",
+			ctx_change ? "Evaluate Context" : "Configure Endpoint");
+		break;
+	default:
+		printf("ERROR: %s command returned completion code %d.\n",
+			ctx_change ? "Evaluate Context" : "Configure Endpoint",
+			GET_COMP_CODE(le32_to_cpu(event->event_cmd.status)));
+		return -EINVAL;
+	}
+
+	xhci_acknowledge_event(ctrl);
+
+	return 0;
+}
+
+/**
+ * Configure the endpoint, programming the device contexts.
+ *
+ * @param udev	pointer to the USB device structure
+ * @return returns the status of the xhci_configure_endpoints
+ */
+static int xhci_set_configuration(struct usb_device *udev)
+{
+	struct xhci_container_ctx *in_ctx;
+	struct xhci_container_ctx *out_ctx;
+	struct xhci_input_control_ctx *ctrl_ctx;
+	struct xhci_slot_ctx *slot_ctx;
+	struct xhci_ep_ctx *ep_ctx[MAX_EP_CTX_NUM];
+	int cur_ep;
+	int max_ep_flag = 0;
+	int ep_index;
+	unsigned int dir;
+	unsigned int ep_type;
+	struct xhci_ctrl *ctrl = udev->controller;
+	int num_of_ep;
+	int ep_flag = 0;
+	u64 trb_64 = 0;
+	int slot_id = udev->slot_id;
+	struct xhci_virt_device *virt_dev = ctrl->devs[slot_id];
+	struct usb_interface *ifdesc;
+
+	out_ctx = virt_dev->out_ctx;
+	in_ctx = virt_dev->in_ctx;
+
+	num_of_ep = udev->config.if_desc[0].no_of_ep;
+	ifdesc = &udev->config.if_desc[0];
+
+	ctrl_ctx = xhci_get_input_control_ctx(in_ctx);
+	/* Zero the input context control */
+	ctrl_ctx->add_flags = 0;
+	ctrl_ctx->drop_flags = 0;
+
+	/* EP_FLAG gives values 1 & 4 for EP1OUT and EP2IN */
+	for (cur_ep = 0; cur_ep < num_of_ep; cur_ep++) {
+		ep_flag = xhci_get_ep_index(&ifdesc->ep_desc[cur_ep]);
+		ctrl_ctx->add_flags |= cpu_to_le32(1 << (ep_flag + 1));
+		if (max_ep_flag < ep_flag)
+			max_ep_flag = ep_flag;
+	}
+
+	xhci_inval_cache((uint32_t)out_ctx->bytes, out_ctx->size);
+
+	/* slot context */
+	xhci_slot_copy(ctrl, in_ctx, out_ctx);
+	slot_ctx = xhci_get_slot_ctx(ctrl, in_ctx);
+	slot_ctx->dev_info &= ~(LAST_CTX_MASK);
+	slot_ctx->dev_info |= cpu_to_le32(LAST_CTX(max_ep_flag + 1) | 0);
+
+	xhci_endpoint_copy(ctrl, in_ctx, out_ctx, 0);
+
+	/* filling up ep contexts */
+	for (cur_ep = 0; cur_ep < num_of_ep; cur_ep++) {
+		struct usb_endpoint_descriptor *endpt_desc = NULL;
+
+		endpt_desc = &ifdesc->ep_desc[cur_ep];
+		trb_64 = 0;
+
+		ep_index = xhci_get_ep_index(endpt_desc);
+		ep_ctx[ep_index] = xhci_get_ep_ctx(ctrl, in_ctx, ep_index);
+
+		/* Allocate the ep rings */
+		virt_dev->eps[ep_index].ring = xhci_ring_alloc(1, true);
+		if (!virt_dev->eps[ep_index].ring)
+			return -ENOMEM;
+
+		/*NOTE: ep_desc[0] actually represents EP1 and so on */
+		dir = (((endpt_desc->bEndpointAddress) & (0x80)) >> 7);
+		ep_type = (((endpt_desc->bmAttributes) & (0x3)) | (dir << 2));
+		ep_ctx[ep_index]->ep_info2 =
+			cpu_to_le32(ep_type << EP_TYPE_SHIFT);
+		ep_ctx[ep_index]->ep_info2 |=
+			cpu_to_le32(MAX_PACKET
+			(get_unaligned(&endpt_desc->wMaxPacketSize)));
+
+		ep_ctx[ep_index]->ep_info2 |=
+			cpu_to_le32(((0 & MAX_BURST_MASK) << MAX_BURST_SHIFT) |
+			((3 & ERROR_COUNT_MASK) << ERROR_COUNT_SHIFT));
+
+		trb_64 = (uintptr_t)
+				virt_dev->eps[ep_index].ring->enqueue;
+		ep_ctx[ep_index]->deq = cpu_to_le64(trb_64 |
+				virt_dev->eps[ep_index].ring->cycle_state);
+	}
+
+	return xhci_configure_endpoints(udev, false);
+}
+
+/**
+ * Issue an Address Device command (which will issue a SetAddress request to
+ * the device).
+ *
+ * @param udev pointer to the Device Data Structure
+ * @return 0 if successful else error code on failure
+ */
+static int xhci_address_device(struct usb_device *udev)
+{
+	int ret = 0;
+	struct xhci_ctrl *ctrl = udev->controller;
+	struct xhci_slot_ctx *slot_ctx;
+	struct xhci_input_control_ctx *ctrl_ctx;
+	struct xhci_virt_device *virt_dev;
+	int slot_id = udev->slot_id;
+	union xhci_trb *event;
+
+	virt_dev = ctrl->devs[slot_id];
+
+	/*
+	 * This is the first Set Address since device plug-in
+	 * so setting up the slot context.
+	 */
+	debug("Setting up addressable devices\n");
+	xhci_setup_addressable_virt_dev(udev);
+
+	ctrl_ctx = xhci_get_input_control_ctx(virt_dev->in_ctx);
+	ctrl_ctx->add_flags = cpu_to_le32(SLOT_FLAG | EP0_FLAG);
+	ctrl_ctx->drop_flags = 0;
+
+	xhci_queue_command(ctrl, (void *)ctrl_ctx, slot_id, 0, TRB_ADDR_DEV);
+	event = xhci_wait_for_event(ctrl, TRB_COMPLETION);
+	BUG_ON(TRB_TO_SLOT_ID(le32_to_cpu(event->event_cmd.flags)) != slot_id);
+
+	switch (GET_COMP_CODE(le32_to_cpu(event->event_cmd.status))) {
+	case COMP_CTX_STATE:
+	case COMP_EBADSLT:
+		printf("Setup ERROR: address device command for slot %d.\n",
+								slot_id);
+		ret = -EINVAL;
+		break;
+	case COMP_TX_ERR:
+		puts("Device not responding to set address.\n");
+		ret = -EPROTO;
+		break;
+	case COMP_DEV_ERR:
+		puts("ERROR: Incompatible device"
+					"for address device command.\n");
+		ret = -ENODEV;
+		break;
+	case COMP_SUCCESS:
+		debug("Successful Address Device command\n");
+		udev->status = 0;
+		break;
+	default:
+		printf("ERROR: unexpected command completion code 0x%x.\n",
+			GET_COMP_CODE(le32_to_cpu(event->event_cmd.status)));
+		ret = -EINVAL;
+		break;
+	}
+
+	xhci_acknowledge_event(ctrl);
+
+	if (ret < 0)
+		/*
+		 * TODO: Unsuccessful Address Device command shall leave the
+		 * slot in default state. So, issue Disable Slot command now.
+		 */
+		return ret;
+
+	xhci_inval_cache((uint32_t)virt_dev->out_ctx->bytes,
+				virt_dev->out_ctx->size);
+	slot_ctx = xhci_get_slot_ctx(ctrl, virt_dev->out_ctx);
+
+	debug("xHC internal address is: %d\n",
+		le32_to_cpu(slot_ctx->dev_state) & DEV_ADDR_MASK);
+
+	return 0;
+}
+
+/**
+ * Issue Enable slot command to the controller to allocate
+ * device slot and assign the slot id. It fails if the xHC
+ * ran out of device slots, the Enable Slot command timed out,
+ * or allocating memory failed.
+ *
+ * @param udev	pointer to the Device Data Structure
+ * @return Returns 0 on succes else return error code on failure
+ */
+int usb_alloc_device(struct usb_device *udev)
+{
+	union xhci_trb *event;
+	struct xhci_ctrl *ctrl = udev->controller;
+	int ret;
+
+	/*
+	 * Root hub will be first device to be initailized.
+	 * If this device is root-hub, don't do any xHC related
+	 * stuff.
+	 */
+	if (ctrl->rootdev == 0) {
+		udev->speed = USB_SPEED_SUPER;
+		return 0;
+	}
+
+	xhci_queue_command(ctrl, NULL, 0, 0, TRB_ENABLE_SLOT);
+	event = xhci_wait_for_event(ctrl, TRB_COMPLETION);
+	BUG_ON(GET_COMP_CODE(le32_to_cpu(event->event_cmd.status))
+		!= COMP_SUCCESS);
+
+	udev->slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->event_cmd.flags));
+
+	xhci_acknowledge_event(ctrl);
+
+	ret = xhci_alloc_virt_device(udev);
+	if (ret < 0) {
+		/*
+		 * TODO: Unsuccessful Address Device command shall leave
+		 * the slot in default. So, issue Disable Slot command now.
+		 */
+		puts("Could not allocate xHCI USB device data structures\n");
+		return ret;
+	}
+
+	return 0;
+}
+
+/*
+ * Full speed devices may have a max packet size greater than 8 bytes, but the
+ * USB core doesn't know that until it reads the first 8 bytes of the
+ * descriptor.  If the usb_device's max packet size changes after that point,
+ * we need to issue an evaluate context command and wait on it.
+ *
+ * @param udev	pointer to the Device Data Structure
+ * @return returns the status of the xhci_configure_endpoints
+ */
+int xhci_check_maxpacket(struct usb_device *udev)
+{
+	struct xhci_ctrl *ctrl = udev->controller;
+	unsigned int slot_id = udev->slot_id;
+	int ep_index = 0;	/* control endpoint */
+	struct xhci_container_ctx *in_ctx;
+	struct xhci_container_ctx *out_ctx;
+	struct xhci_input_control_ctx *ctrl_ctx;
+	struct xhci_ep_ctx *ep_ctx;
+	int max_packet_size;
+	int hw_max_packet_size;
+	int ret = 0;
+	struct usb_interface *ifdesc;
+
+	ifdesc = &udev->config.if_desc[0];
+
+	out_ctx = ctrl->devs[slot_id]->out_ctx;
+	xhci_inval_cache((uint32_t)out_ctx->bytes, out_ctx->size);
+
+	ep_ctx = xhci_get_ep_ctx(ctrl, out_ctx, ep_index);
+	hw_max_packet_size = MAX_PACKET_DECODED(le32_to_cpu(ep_ctx->ep_info2));
+	max_packet_size = usb_endpoint_maxp(&ifdesc->ep_desc[0]);
+	if (hw_max_packet_size != max_packet_size) {
+		debug("Max Packet Size for ep 0 changed.\n");
+		debug("Max packet size in usb_device = %d\n", max_packet_size);
+		debug("Max packet size in xHCI HW = %d\n", hw_max_packet_size);
+		debug("Issuing evaluate context command.\n");
+
+		/* Set up the modified control endpoint 0 */
+		xhci_endpoint_copy(ctrl, ctrl->devs[slot_id]->in_ctx,
+				ctrl->devs[slot_id]->out_ctx, ep_index);
+		in_ctx = ctrl->devs[slot_id]->in_ctx;
+		ep_ctx = xhci_get_ep_ctx(ctrl, in_ctx, ep_index);
+		ep_ctx->ep_info2 &= cpu_to_le32(~MAX_PACKET_MASK);
+		ep_ctx->ep_info2 |= cpu_to_le32(MAX_PACKET(max_packet_size));
+
+		/*
+		 * Set up the input context flags for the command
+		 * FIXME: This won't work if a non-default control endpoint
+		 * changes max packet sizes.
+		 */
+		ctrl_ctx = xhci_get_input_control_ctx(in_ctx);
+		ctrl_ctx->add_flags = cpu_to_le32(EP0_FLAG);
+		ctrl_ctx->drop_flags = 0;
+
+		ret = xhci_configure_endpoints(udev, true);
+	}
+	return ret;
+}
+
+/**
+ * Clears the Change bits of the Port Status Register
+ *
+ * @param wValue	request value
+ * @param wIndex	request index
+ * @param addr		address of posrt status register
+ * @param port_status	state of port status register
+ * @return none
+ */
+static void xhci_clear_port_change_bit(u16 wValue,
+		u16 wIndex, volatile uint32_t *addr, u32 port_status)
+{
+	char *port_change_bit;
+	u32 status;
+
+	switch (wValue) {
+	case USB_PORT_FEAT_C_RESET:
+		status = PORT_RC;
+		port_change_bit = "reset";
+		break;
+	case USB_PORT_FEAT_C_CONNECTION:
+		status = PORT_CSC;
+		port_change_bit = "connect";
+		break;
+	case USB_PORT_FEAT_C_OVER_CURRENT:
+		status = PORT_OCC;
+		port_change_bit = "over-current";
+		break;
+	case USB_PORT_FEAT_C_ENABLE:
+		status = PORT_PEC;
+		port_change_bit = "enable/disable";
+		break;
+	case USB_PORT_FEAT_C_SUSPEND:
+		status = PORT_PLC;
+		port_change_bit = "suspend/resume";
+		break;
+	default:
+		/* Should never happen */
+		return;
+	}
+
+	/* Change bits are all write 1 to clear */
+	xhci_writel(addr, port_status | status);
+
+	port_status = xhci_readl(addr);
+	debug("clear port %s change, actual port %d status  = 0x%x\n",
+			port_change_bit, wIndex, port_status);
+}
+
+/**
+ * Save Read Only (RO) bits and save read/write bits where
+ * writing a 0 clears the bit and writing a 1 sets the bit (RWS).
+ * For all other types (RW1S, RW1CS, RW, and RZ), writing a '0' has no effect.
+ *
+ * @param state	state of the Port Status and Control Regsiter
+ * @return a value that would result in the port being in the
+ *	   same state, if the value was written to the port
+ *	   status control register.
+ */
+static u32 xhci_port_state_to_neutral(u32 state)
+{
+	/* Save read-only status and port state */
+	return (state & XHCI_PORT_RO) | (state & XHCI_PORT_RWS);
+}
+
+/**
+ * Submits the Requests to the XHCI Host Controller
+ *
+ * @param udev pointer to the USB device structure
+ * @param pipe contains the DIR_IN or OUT , devnum
+ * @param buffer buffer to be read/written based on the request
+ * @return returns 0 if successful else -1 on failure
+ */
+static int xhci_submit_root(struct usb_device *udev, unsigned long pipe,
+			void *buffer, struct devrequest *req)
+{
+	uint8_t tmpbuf[4];
+	u16 typeReq;
+	void *srcptr = NULL;
+	int len, srclen;
+	uint32_t reg;
+	volatile uint32_t *status_reg;
+	struct xhci_ctrl *ctrl = udev->controller;
+	struct xhci_hcor *hcor = ctrl->hcor;
+
+	if (((req->requesttype & USB_RT_PORT) &&
+	     le16_to_cpu(req->index)) > CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS) {
+		printf("The request port(%d) is not configured\n",
+			le16_to_cpu(req->index) - 1);
+		return -EINVAL;
+	}
+
+	status_reg = (volatile uint32_t *)
+		     (&hcor->portregs[le16_to_cpu(req->index) - 1].or_portsc);
+	srclen = 0;
+
+	typeReq = req->request | req->requesttype << 8;
+
+	switch (typeReq) {
+	case DeviceRequest | USB_REQ_GET_DESCRIPTOR:
+		switch (le16_to_cpu(req->value) >> 8) {
+		case USB_DT_DEVICE:
+			debug("USB_DT_DEVICE request\n");
+			srcptr = &descriptor.device;
+			srclen = 0x12;
+			break;
+		case USB_DT_CONFIG:
+			debug("USB_DT_CONFIG config\n");
+			srcptr = &descriptor.config;
+			srclen = 0x19;
+			break;
+		case USB_DT_STRING:
+			debug("USB_DT_STRING config\n");
+			switch (le16_to_cpu(req->value) & 0xff) {
+			case 0:	/* Language */
+				srcptr = "\4\3\11\4";
+				srclen = 4;
+				break;
+			case 1:	/* Vendor String  */
+				srcptr = "\16\3u\0-\0b\0o\0o\0t\0";
+				srclen = 14;
+				break;
+			case 2:	/* Product Name */
+				srcptr = "\52\3X\0H\0C\0I\0 "
+					 "\0H\0o\0s\0t\0 "
+					 "\0C\0o\0n\0t\0r\0o\0l\0l\0e\0r\0";
+				srclen = 42;
+				break;
+			default:
+				printf("unknown value DT_STRING %x\n",
+					le16_to_cpu(req->value));
+				goto unknown;
+			}
+			break;
+		default:
+			printf("unknown value %x\n", le16_to_cpu(req->value));
+			goto unknown;
+		}
+		break;
+	case USB_REQ_GET_DESCRIPTOR | ((USB_DIR_IN | USB_RT_HUB) << 8):
+		switch (le16_to_cpu(req->value) >> 8) {
+		case USB_DT_HUB:
+			debug("USB_DT_HUB config\n");
+			srcptr = &descriptor.hub;
+			srclen = 0x8;
+			break;
+		default:
+			printf("unknown value %x\n", le16_to_cpu(req->value));
+			goto unknown;
+		}
+		break;
+	case USB_REQ_SET_ADDRESS | (USB_RECIP_DEVICE << 8):
+		debug("USB_REQ_SET_ADDRESS\n");
+		ctrl->rootdev = le16_to_cpu(req->value);
+		break;
+	case DeviceOutRequest | USB_REQ_SET_CONFIGURATION:
+		/* Do nothing */
+		break;
+	case USB_REQ_GET_STATUS | ((USB_DIR_IN | USB_RT_HUB) << 8):
+		tmpbuf[0] = 1;	/* USB_STATUS_SELFPOWERED */
+		tmpbuf[1] = 0;
+		srcptr = tmpbuf;
+		srclen = 2;
+		break;
+	case USB_REQ_GET_STATUS | ((USB_RT_PORT | USB_DIR_IN) << 8):
+		memset(tmpbuf, 0, 4);
+		reg = xhci_readl(status_reg);
+		if (reg & PORT_CONNECT) {
+			tmpbuf[0] |= USB_PORT_STAT_CONNECTION;
+			switch (reg & DEV_SPEED_MASK) {
+			case XDEV_FS:
+				debug("SPEED = FULLSPEED\n");
+				break;
+			case XDEV_LS:
+				debug("SPEED = LOWSPEED\n");
+				tmpbuf[1] |= USB_PORT_STAT_LOW_SPEED >> 8;
+				break;
+			case XDEV_HS:
+				debug("SPEED = HIGHSPEED\n");
+				tmpbuf[1] |= USB_PORT_STAT_HIGH_SPEED >> 8;
+				break;
+			case XDEV_SS:
+				debug("SPEED = SUPERSPEED\n");
+				tmpbuf[1] |= USB_PORT_STAT_SUPER_SPEED >> 8;
+				break;
+			}
+		}
+		if (reg & PORT_PE)
+			tmpbuf[0] |= USB_PORT_STAT_ENABLE;
+		if ((reg & PORT_PLS_MASK) == XDEV_U3)
+			tmpbuf[0] |= USB_PORT_STAT_SUSPEND;
+		if (reg & PORT_OC)
+			tmpbuf[0] |= USB_PORT_STAT_OVERCURRENT;
+		if (reg & PORT_RESET)
+			tmpbuf[0] |= USB_PORT_STAT_RESET;
+		if (reg & PORT_POWER)
+			/*
+			 * XXX: This Port power bit (for USB 3.0 hub)
+			 * we are faking in USB 2.0 hub port status;
+			 * since there's a change in bit positions in
+			 * two:
+			 * USB 2.0 port status PP is at position[8]
+			 * USB 3.0 port status PP is at position[9]
+			 * So, we are still keeping it at position [8]
+			 */
+			tmpbuf[1] |= USB_PORT_STAT_POWER >> 8;
+		if (reg & PORT_CSC)
+			tmpbuf[2] |= USB_PORT_STAT_C_CONNECTION;
+		if (reg & PORT_PEC)
+			tmpbuf[2] |= USB_PORT_STAT_C_ENABLE;
+		if (reg & PORT_OCC)
+			tmpbuf[2] |= USB_PORT_STAT_C_OVERCURRENT;
+		if (reg & PORT_RC)
+			tmpbuf[2] |= USB_PORT_STAT_C_RESET;
+
+		srcptr = tmpbuf;
+		srclen = 4;
+		break;
+	case USB_REQ_SET_FEATURE | ((USB_DIR_OUT | USB_RT_PORT) << 8):
+		reg = xhci_readl(status_reg);
+		reg = xhci_port_state_to_neutral(reg);
+		switch (le16_to_cpu(req->value)) {
+		case USB_PORT_FEAT_ENABLE:
+			reg |= PORT_PE;
+			xhci_writel(status_reg, reg);
+			break;
+		case USB_PORT_FEAT_POWER:
+			reg |= PORT_POWER;
+			xhci_writel(status_reg, reg);
+			break;
+		case USB_PORT_FEAT_RESET:
+			reg |= PORT_RESET;
+			xhci_writel(status_reg, reg);
+			break;
+		default:
+			printf("unknown feature %x\n", le16_to_cpu(req->value));
+			goto unknown;
+		}
+		break;
+	case USB_REQ_CLEAR_FEATURE | ((USB_DIR_OUT | USB_RT_PORT) << 8):
+		reg = xhci_readl(status_reg);
+		reg = xhci_port_state_to_neutral(reg);
+		switch (le16_to_cpu(req->value)) {
+		case USB_PORT_FEAT_ENABLE:
+			reg &= ~PORT_PE;
+			break;
+		case USB_PORT_FEAT_POWER:
+			reg &= ~PORT_POWER;
+			break;
+		case USB_PORT_FEAT_C_RESET:
+		case USB_PORT_FEAT_C_CONNECTION:
+		case USB_PORT_FEAT_C_OVER_CURRENT:
+		case USB_PORT_FEAT_C_ENABLE:
+			xhci_clear_port_change_bit((le16_to_cpu(req->value)),
+							le16_to_cpu(req->index),
+							status_reg, reg);
+			break;
+		default:
+			printf("unknown feature %x\n", le16_to_cpu(req->value));
+			goto unknown;
+		}
+		xhci_writel(status_reg, reg);
+		break;
+	default:
+		puts("Unknown request\n");
+		goto unknown;
+	}
+
+	debug("scrlen = %d\n req->length = %d\n",
+		srclen, le16_to_cpu(req->length));
+
+	len = min(srclen, le16_to_cpu(req->length));
+
+	if (srcptr != NULL && len > 0)
+		memcpy(buffer, srcptr, len);
+	else
+		debug("Len is 0\n");
+
+	udev->act_len = len;
+	udev->status = 0;
+
+	return 0;
+
+unknown:
+	udev->act_len = 0;
+	udev->status = USB_ST_STALLED;
+
+	return -ENODEV;
+}
+
+/**
+ * Submits the INT request to XHCI Host cotroller
+ *
+ * @param udev	pointer to the USB device
+ * @param pipe		contains the DIR_IN or OUT , devnum
+ * @param buffer	buffer to be read/written based on the request
+ * @param length	length of the buffer
+ * @param interval	interval of the interrupt
+ * @return 0
+ */
+int
+submit_int_msg(struct usb_device *udev, unsigned long pipe, void *buffer,
+						int length, int interval)
+{
+	/*
+	 * TODO: Not addressing any interrupt type transfer requests
+	 * Add support for it later.
+	 */
+	return -EINVAL;
+}
+
+/**
+ * submit the BULK type of request to the USB Device
+ *
+ * @param udev	pointer to the USB device
+ * @param pipe		contains the DIR_IN or OUT , devnum
+ * @param buffer	buffer to be read/written based on the request
+ * @param length	length of the buffer
+ * @return returns 0 if successful else -1 on failure
+ */
+int
+submit_bulk_msg(struct usb_device *udev, unsigned long pipe, void *buffer,
+								int length)
+{
+	if (usb_pipetype(pipe) != PIPE_BULK) {
+		printf("non-bulk pipe (type=%lu)", usb_pipetype(pipe));
+		return -EINVAL;
+	}
+
+	return xhci_bulk_tx(udev, pipe, length, buffer);
+}
+
+/**
+ * submit the control type of request to the Root hub/Device based on the devnum
+ *
+ * @param udev	pointer to the USB device
+ * @param pipe		contains the DIR_IN or OUT , devnum
+ * @param buffer	buffer to be read/written based on the request
+ * @param length	length of the buffer
+ * @param setup		Request type
+ * @return returns 0 if successful else -1 on failure
+ */
+int
+submit_control_msg(struct usb_device *udev, unsigned long pipe, void *buffer,
+					int length, struct devrequest *setup)
+{
+	struct xhci_ctrl *ctrl = udev->controller;
+	int ret = 0;
+
+	if (usb_pipetype(pipe) != PIPE_CONTROL) {
+		printf("non-control pipe (type=%lu)", usb_pipetype(pipe));
+		return -EINVAL;
+	}
+
+	if (usb_pipedevice(pipe) == ctrl->rootdev)
+		return xhci_submit_root(udev, pipe, buffer, setup);
+
+	if (setup->request == USB_REQ_SET_ADDRESS)
+		return xhci_address_device(udev);
+
+	if (setup->request == USB_REQ_SET_CONFIGURATION) {
+		ret = xhci_set_configuration(udev);
+		if (ret) {
+			puts("Failed to configure xHCI endpoint\n");
+			return ret;
+		}
+	}
+
+	return xhci_ctrl_tx(udev, pipe, setup, length, buffer);
+}
+
+/**
+ * Intialises the XHCI host controller
+ * and allocates the necessary data structures
+ *
+ * @param index	index to the host controller data structure
+ * @return pointer to the intialised controller
+ */
+int usb_lowlevel_init(int index, enum usb_init_type init, void **controller)
+{
+	uint32_t val;
+	uint32_t val2;
+	uint32_t reg;
+	struct xhci_hccr *hccr;
+	struct xhci_hcor *hcor;
+	struct xhci_ctrl *ctrl;
+
+	if (xhci_hcd_init(index, &hccr, (struct xhci_hcor **)&hcor) != 0)
+		return -ENODEV;
+
+	if (xhci_reset(hcor) != 0)
+		return -ENODEV;
+
+	ctrl = &xhcic[index];
+
+	ctrl->hccr = hccr;
+	ctrl->hcor = hcor;
+
+	/*
+	 * Program the Number of Device Slots Enabled field in the CONFIG
+	 * register with the max value of slots the HC can handle.
+	 */
+	val = (xhci_readl(&hccr->cr_hcsparams1) & HCS_SLOTS_MASK);
+	val2 = xhci_readl(&hcor->or_config);
+	val |= (val2 & ~HCS_SLOTS_MASK);
+	xhci_writel(&hcor->or_config, val);
+
+	/* initializing xhci data structures */
+	if (xhci_mem_init(ctrl, hccr, hcor) < 0)
+		return -ENOMEM;
+
+	reg = xhci_readl(&hccr->cr_hcsparams1);
+	descriptor.hub.bNbrPorts = ((reg & HCS_MAX_PORTS_MASK) >>
+						HCS_MAX_PORTS_SHIFT);
+	printf("Register %x NbrPorts %d\n", reg, descriptor.hub.bNbrPorts);
+
+	/* Port Indicators */
+	reg = xhci_readl(&hccr->cr_hccparams);
+	if (HCS_INDICATOR(reg))
+		put_unaligned(get_unaligned(&descriptor.hub.wHubCharacteristics)
+				| 0x80, &descriptor.hub.wHubCharacteristics);
+
+	/* Port Power Control */
+	if (HCC_PPC(reg))
+		put_unaligned(get_unaligned(&descriptor.hub.wHubCharacteristics)
+				| 0x01, &descriptor.hub.wHubCharacteristics);
+
+	if (xhci_start(hcor)) {
+		xhci_reset(hcor);
+		return -ENODEV;
+	}
+
+	/* Zero'ing IRQ control register and IRQ pending register */
+	xhci_writel(&ctrl->ir_set->irq_control, 0x0);
+	xhci_writel(&ctrl->ir_set->irq_pending, 0x0);
+
+	reg = HC_VERSION(xhci_readl(&hccr->cr_capbase));
+	printf("USB XHCI %x.%02x\n", reg >> 8, reg & 0xff);
+
+	*controller = &xhcic[index];
+
+	return 0;
+}
+
+/**
+ * Stops the XHCI host controller
+ * and cleans up all the related data structures
+ *
+ * @param index	index to the host controller data structure
+ * @return none
+ */
+int usb_lowlevel_stop(int index)
+{
+	struct xhci_ctrl *ctrl = (xhcic + index);
+	u32 temp;
+
+	xhci_reset(ctrl->hcor);
+
+	debug("// Disabling event ring interrupts\n");
+	temp = xhci_readl(&ctrl->hcor->or_usbsts);
+	xhci_writel(&ctrl->hcor->or_usbsts, temp & ~STS_EINT);
+	temp = xhci_readl(&ctrl->ir_set->irq_pending);
+	xhci_writel(&ctrl->ir_set->irq_pending, ER_IRQ_DISABLE(temp));
+
+	xhci_hcd_stop(index);
+
+	xhci_cleanup(ctrl);
+
+	return 0;
+}
diff --git a/drivers/usb/host/xhci.h b/drivers/usb/host/xhci.h
new file mode 100644
index 0000000000..ceb1573d86
--- /dev/null
+++ b/drivers/usb/host/xhci.h
@@ -0,0 +1,1255 @@
+/*
+ * USB HOST XHCI Controller
+ *
+ * Based on xHCI host controller driver in linux-kernel
+ * by Sarah Sharp.
+ *
+ * Copyright (C) 2008 Intel Corp.
+ * Author: Sarah Sharp
+ *
+ * Copyright (C) 2013 Samsung Electronics Co.Ltd
+ * Authors: Vivek Gautam <gautam.vivek@samsung.com>
+ *	    Vikas Sajjan <vikas.sajjan@samsung.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef HOST_XHCI_H_
+#define HOST_XHCI_H_
+
+#include <asm/cache.h>
+#include <asm/io.h>
+#include <linux/list.h>
+
+#define upper_32_bits(n) (u32)((n) >> 32)
+#define lower_32_bits(n) (u32)(n)
+
+#define MAX_EP_CTX_NUM		31
+#define XHCI_ALIGNMENT		64
+/* Generic timeout for XHCI events */
+#define XHCI_TIMEOUT		5000
+/* Max number of USB devices for any host controller - limit in section 6.1 */
+#define MAX_HC_SLOTS            256
+/* Section 5.3.3 - MaxPorts */
+#define MAX_HC_PORTS            127
+
+/* Up to 16 ms to halt an HC */
+#define XHCI_MAX_HALT_USEC	(16*1000)
+
+#define XHCI_MAX_RESET_USEC	(250*1000)
+
+/*
+ * These bits are Read Only (RO) and should be saved and written to the
+ * registers: 0, 3, 10:13, 30
+ * connect status, over-current status, port speed, and device removable.
+ * connect status and port speed are also sticky - meaning they're in
+ * the AUX well and they aren't changed by a hot, warm, or cold reset.
+ */
+#define XHCI_PORT_RO ((1 << 0) | (1 << 3) | (0xf << 10) | (1 << 30))
+/*
+ * These bits are RW; writing a 0 clears the bit, writing a 1 sets the bit:
+ * bits 5:8, 9, 14:15, 25:27
+ * link state, port power, port indicator state, "wake on" enable state
+ */
+#define XHCI_PORT_RWS ((0xf << 5) | (1 << 9) | (0x3 << 14) | (0x7 << 25))
+/*
+ * These bits are RW; writing a 1 sets the bit, writing a 0 has no effect:
+ * bit 4 (port reset)
+ */
+#define XHCI_PORT_RW1S ((1 << 4))
+/*
+ * These bits are RW; writing a 1 clears the bit, writing a 0 has no effect:
+ * bits 1, 17, 18, 19, 20, 21, 22, 23
+ * port enable/disable, and
+ * change bits: connect, PED,
+ * warm port reset changed (reserved zero for USB 2.0 ports),
+ * over-current, reset, link state, and L1 change
+ */
+#define XHCI_PORT_RW1CS ((1 << 1) | (0x7f << 17))
+/*
+ * Bit 16 is RW, and writing a '1' to it causes the link state control to be
+ * latched in
+ */
+#define XHCI_PORT_RW ((1 << 16))
+/*
+ * These bits are Reserved Zero (RsvdZ) and zero should be written to them:
+ * bits 2, 24, 28:31
+ */
+#define XHCI_PORT_RZ ((1 << 2) | (1 << 24) | (0xf << 28))
+
+/*
+ * XHCI Register Space.
+ */
+struct xhci_hccr {
+	uint32_t cr_capbase;
+	uint32_t cr_hcsparams1;
+	uint32_t cr_hcsparams2;
+	uint32_t cr_hcsparams3;
+	uint32_t cr_hccparams;
+	uint32_t cr_dboff;
+	uint32_t cr_rtsoff;
+
+/* hc_capbase bitmasks */
+/* bits 7:0 - how long is the Capabilities register */
+#define HC_LENGTH(p)		XHCI_HC_LENGTH(p)
+/* bits 31:16	*/
+#define HC_VERSION(p)		(((p) >> 16) & 0xffff)
+
+/* HCSPARAMS1 - hcs_params1 - bitmasks */
+/* bits 0:7, Max Device Slots */
+#define HCS_MAX_SLOTS(p)	(((p) >> 0) & 0xff)
+#define HCS_SLOTS_MASK		0xff
+/* bits 8:18, Max Interrupters */
+#define HCS_MAX_INTRS(p)	(((p) >> 8) & 0x7ff)
+/* bits 24:31, Max Ports - max value is 0x7F = 127 ports */
+#define HCS_MAX_PORTS_SHIFT	24
+#define HCS_MAX_PORTS_MASK	(0x7f << HCS_MAX_PORTS_SHIFT)
+#define HCS_MAX_PORTS(p)	(((p) >> 24) & 0x7f)
+
+/* HCSPARAMS2 - hcs_params2 - bitmasks */
+/* bits 0:3, frames or uframes that SW needs to queue transactions
+ * ahead of the HW to meet periodic deadlines */
+#define HCS_IST(p)		(((p) >> 0) & 0xf)
+/* bits 4:7, max number of Event Ring segments */
+#define HCS_ERST_MAX(p)		(((p) >> 4) & 0xf)
+/* bit 26 Scratchpad restore - for save/restore HW state - not used yet */
+/* bits 27:31 number of Scratchpad buffers SW must allocate for the HW */
+#define HCS_MAX_SCRATCHPAD(p)   (((p) >> 27) & 0x1f)
+
+/* HCSPARAMS3 - hcs_params3 - bitmasks */
+/* bits 0:7, Max U1 to U0 latency for the roothub ports */
+#define HCS_U1_LATENCY(p)	(((p) >> 0) & 0xff)
+/* bits 16:31, Max U2 to U0 latency for the roothub ports */
+#define HCS_U2_LATENCY(p)	(((p) >> 16) & 0xffff)
+
+/* HCCPARAMS - hcc_params - bitmasks */
+/* true: HC can use 64-bit address pointers */
+#define HCC_64BIT_ADDR(p)	((p) & (1 << 0))
+/* true: HC can do bandwidth negotiation */
+#define HCC_BANDWIDTH_NEG(p)	((p) & (1 << 1))
+/* true: HC uses 64-byte Device Context structures
+ * FIXME 64-byte context structures aren't supported yet.
+ */
+#define HCC_64BYTE_CONTEXT(p)	((p) & (1 << 2))
+/* true: HC has port power switches */
+#define HCC_PPC(p)		((p) & (1 << 3))
+/* true: HC has port indicators */
+#define HCS_INDICATOR(p)	((p) & (1 << 4))
+/* true: HC has Light HC Reset Capability */
+#define HCC_LIGHT_RESET(p)	((p) & (1 << 5))
+/* true: HC supports latency tolerance messaging */
+#define HCC_LTC(p)		((p) & (1 << 6))
+/* true: no secondary Stream ID Support */
+#define HCC_NSS(p)		((p) & (1 << 7))
+/* Max size for Primary Stream Arrays - 2^(n+1), where n is bits 12:15 */
+#define HCC_MAX_PSA(p)		(1 << ((((p) >> 12) & 0xf) + 1))
+/* Extended Capabilities pointer from PCI base - section 5.3.6 */
+#define HCC_EXT_CAPS(p)		XHCI_HCC_EXT_CAPS(p)
+
+/* db_off bitmask - bits 0:1 reserved */
+#define	DBOFF_MASK	(~0x3)
+
+/* run_regs_off bitmask - bits 0:4 reserved */
+#define	RTSOFF_MASK	(~0x1f)
+
+};
+
+struct xhci_hcor_port_regs {
+	volatile uint32_t or_portsc;
+	volatile uint32_t or_portpmsc;
+	volatile uint32_t or_portli;
+	volatile uint32_t reserved_3;
+};
+
+struct xhci_hcor {
+	volatile uint32_t or_usbcmd;
+	volatile uint32_t or_usbsts;
+	volatile uint32_t or_pagesize;
+	volatile uint32_t reserved_0[2];
+	volatile uint32_t or_dnctrl;
+	volatile uint64_t or_crcr;
+	volatile uint32_t reserved_1[4];
+	volatile uint64_t or_dcbaap;
+	volatile uint32_t or_config;
+	volatile uint32_t reserved_2[241];
+	struct xhci_hcor_port_regs portregs[CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS];
+
+	uint32_t reserved_4[CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS * 254];
+};
+
+/* USBCMD - USB command - command bitmasks */
+/* start/stop HC execution - do not write unless HC is halted*/
+#define CMD_RUN		XHCI_CMD_RUN
+/* Reset HC - resets internal HC state machine and all registers (except
+ * PCI config regs).  HC does NOT drive a USB reset on the downstream ports.
+ * The xHCI driver must reinitialize the xHC after setting this bit.
+ */
+#define CMD_RESET	(1 << 1)
+/* Event Interrupt Enable - a '1' allows interrupts from the host controller */
+#define CMD_EIE		XHCI_CMD_EIE
+/* Host System Error Interrupt Enable - get out-of-band signal for HC errors */
+#define CMD_HSEIE	XHCI_CMD_HSEIE
+/* bits 4:6 are reserved (and should be preserved on writes). */
+/* light reset (port status stays unchanged) - reset completed when this is 0 */
+#define CMD_LRESET	(1 << 7)
+/* host controller save/restore state. */
+#define CMD_CSS		(1 << 8)
+#define CMD_CRS		(1 << 9)
+/* Enable Wrap Event - '1' means xHC generates an event when MFINDEX wraps. */
+#define CMD_EWE		XHCI_CMD_EWE
+/* MFINDEX power management - '1' means xHC can stop MFINDEX counter if all root
+ * hubs are in U3 (selective suspend), disconnect, disabled, or powered-off.
+ * '0' means the xHC can power it off if all ports are in the disconnect,
+ * disabled, or powered-off state.
+ */
+#define CMD_PM_INDEX	(1 << 11)
+/* bits 12:31 are reserved (and should be preserved on writes). */
+
+/* USBSTS - USB status - status bitmasks */
+/* HC not running - set to 1 when run/stop bit is cleared. */
+#define STS_HALT	XHCI_STS_HALT
+/* serious error, e.g. PCI parity error.  The HC will clear the run/stop bit. */
+#define STS_FATAL	(1 << 2)
+/* event interrupt - clear this prior to clearing any IP flags in IR set*/
+#define STS_EINT	(1 << 3)
+/* port change detect */
+#define STS_PORT	(1 << 4)
+/* bits 5:7 reserved and zeroed */
+/* save state status - '1' means xHC is saving state */
+#define STS_SAVE	(1 << 8)
+/* restore state status - '1' means xHC is restoring state */
+#define STS_RESTORE	(1 << 9)
+/* true: save or restore error */
+#define STS_SRE		(1 << 10)
+/* true: Controller Not Ready to accept doorbell or op reg writes after reset */
+#define STS_CNR		XHCI_STS_CNR
+/* true: internal Host Controller Error - SW needs to reset and reinitialize */
+#define STS_HCE		(1 << 12)
+/* bits 13:31 reserved and should be preserved */
+
+/*
+ * DNCTRL - Device Notification Control Register - dev_notification bitmasks
+ * Generate a device notification event when the HC sees a transaction with a
+ * notification type that matches a bit set in this bit field.
+ */
+#define	DEV_NOTE_MASK		(0xffff)
+#define ENABLE_DEV_NOTE(x)	(1 << (x))
+/* Most of the device notification types should only be used for debug.
+ * SW does need to pay attention to function wake notifications.
+ */
+#define	DEV_NOTE_FWAKE		ENABLE_DEV_NOTE(1)
+
+/* CRCR - Command Ring Control Register - cmd_ring bitmasks */
+/* bit 0 is the command ring cycle state */
+/* stop ring operation after completion of the currently executing command */
+#define CMD_RING_PAUSE		(1 << 1)
+/* stop ring immediately - abort the currently executing command */
+#define CMD_RING_ABORT		(1 << 2)
+/* true: command ring is running */
+#define CMD_RING_RUNNING	(1 << 3)
+/* bits 4:5 reserved and should be preserved */
+/* Command Ring pointer - bit mask for the lower 32 bits. */
+#define CMD_RING_RSVD_BITS	(0x3f)
+
+/* CONFIG - Configure Register - config_reg bitmasks */
+/* bits 0:7 - maximum number of device slots enabled (NumSlotsEn) */
+#define MAX_DEVS(p)	((p) & 0xff)
+/* bits 8:31 - reserved and should be preserved */
+
+/* PORTSC - Port Status and Control Register - port_status_base bitmasks */
+/* true: device connected */
+#define PORT_CONNECT	(1 << 0)
+/* true: port enabled */
+#define PORT_PE		(1 << 1)
+/* bit 2 reserved and zeroed */
+/* true: port has an over-current condition */
+#define PORT_OC		(1 << 3)
+/* true: port reset signaling asserted */
+#define PORT_RESET	(1 << 4)
+/* Port Link State - bits 5:8
+ * A read gives the current link PM state of the port,
+ * a write with Link State Write Strobe set sets the link state.
+ */
+#define PORT_PLS_MASK	(0xf << 5)
+#define XDEV_U0		(0x0 << 5)
+#define XDEV_U2		(0x2 << 5)
+#define XDEV_U3		(0x3 << 5)
+#define XDEV_RESUME	(0xf << 5)
+/* true: port has power (see HCC_PPC) */
+#define PORT_POWER	(1 << 9)
+/* bits 10:13 indicate device speed:
+ * 0 - undefined speed - port hasn't be initialized by a reset yet
+ * 1 - full speed
+ * 2 - low speed
+ * 3 - high speed
+ * 4 - super speed
+ * 5-15 reserved
+ */
+#define DEV_SPEED_MASK		(0xf << 10)
+#define	XDEV_FS			(0x1 << 10)
+#define	XDEV_LS			(0x2 << 10)
+#define	XDEV_HS			(0x3 << 10)
+#define	XDEV_SS			(0x4 << 10)
+#define DEV_UNDEFSPEED(p)	(((p) & DEV_SPEED_MASK) == (0x0<<10))
+#define DEV_FULLSPEED(p)	(((p) & DEV_SPEED_MASK) == XDEV_FS)
+#define DEV_LOWSPEED(p)		(((p) & DEV_SPEED_MASK) == XDEV_LS)
+#define DEV_HIGHSPEED(p)	(((p) & DEV_SPEED_MASK) == XDEV_HS)
+#define DEV_SUPERSPEED(p)	(((p) & DEV_SPEED_MASK) == XDEV_SS)
+/* Bits 20:23 in the Slot Context are the speed for the device */
+#define	SLOT_SPEED_FS		(XDEV_FS << 10)
+#define	SLOT_SPEED_LS		(XDEV_LS << 10)
+#define	SLOT_SPEED_HS		(XDEV_HS << 10)
+#define	SLOT_SPEED_SS		(XDEV_SS << 10)
+/* Port Indicator Control */
+#define PORT_LED_OFF	(0 << 14)
+#define PORT_LED_AMBER	(1 << 14)
+#define PORT_LED_GREEN	(2 << 14)
+#define PORT_LED_MASK	(3 << 14)
+/* Port Link State Write Strobe - set this when changing link state */
+#define PORT_LINK_STROBE	(1 << 16)
+/* true: connect status change */
+#define PORT_CSC	(1 << 17)
+/* true: port enable change */
+#define PORT_PEC	(1 << 18)
+/* true: warm reset for a USB 3.0 device is done.  A "hot" reset puts the port
+ * into an enabled state, and the device into the default state.  A "warm" reset
+ * also resets the link, forcing the device through the link training sequence.
+ * SW can also look at the Port Reset register to see when warm reset is done.
+ */
+#define PORT_WRC	(1 << 19)
+/* true: over-current change */
+#define PORT_OCC	(1 << 20)
+/* true: reset change - 1 to 0 transition of PORT_RESET */
+#define PORT_RC		(1 << 21)
+/* port link status change - set on some port link state transitions:
+ *  Transition				Reason
+ *  --------------------------------------------------------------------------
+ *  - U3 to Resume		Wakeup signaling from a device
+ *  - Resume to Recovery to U0	USB 3.0 device resume
+ *  - Resume to U0		USB 2.0 device resume
+ *  - U3 to Recovery to U0	Software resume of USB 3.0 device complete
+ *  - U3 to U0			Software resume of USB 2.0 device complete
+ *  - U2 to U0			L1 resume of USB 2.1 device complete
+ *  - U0 to U0 (???)		L1 entry rejection by USB 2.1 device
+ *  - U0 to disabled		L1 entry error with USB 2.1 device
+ *  - Any state to inactive	Error on USB 3.0 port
+ */
+#define PORT_PLC	(1 << 22)
+/* port configure error change - port failed to configure its link partner */
+#define PORT_CEC	(1 << 23)
+/* bit 24 reserved */
+/* wake on connect (enable) */
+#define PORT_WKCONN_E	(1 << 25)
+/* wake on disconnect (enable) */
+#define PORT_WKDISC_E	(1 << 26)
+/* wake on over-current (enable) */
+#define PORT_WKOC_E	(1 << 27)
+/* bits 28:29 reserved */
+/* true: device is removable - for USB 3.0 roothub emulation */
+#define PORT_DEV_REMOVE	(1 << 30)
+/* Initiate a warm port reset - complete when PORT_WRC is '1' */
+#define PORT_WR		(1 << 31)
+
+/* We mark duplicate entries with -1 */
+#define DUPLICATE_ENTRY ((u8)(-1))
+
+/* Port Power Management Status and Control - port_power_base bitmasks */
+/* Inactivity timer value for transitions into U1, in microseconds.
+ * Timeout can be up to 127us.  0xFF means an infinite timeout.
+ */
+#define PORT_U1_TIMEOUT(p)	((p) & 0xff)
+/* Inactivity timer value for transitions into U2 */
+#define PORT_U2_TIMEOUT(p)	(((p) & 0xff) << 8)
+/* Bits 24:31 for port testing */
+
+/* USB2 Protocol PORTSPMSC */
+#define	PORT_L1S_MASK		7
+#define	PORT_L1S_SUCCESS	1
+#define	PORT_RWE		(1 << 3)
+#define	PORT_HIRD(p)		(((p) & 0xf) << 4)
+#define	PORT_HIRD_MASK		(0xf << 4)
+#define	PORT_L1DS(p)		(((p) & 0xff) << 8)
+#define	PORT_HLE		(1 << 16)
+
+/**
+* struct xhci_intr_reg - Interrupt Register Set
+* @irq_pending:	IMAN - Interrupt Management Register.  Used to enable
+*			interrupts and check for pending interrupts.
+* @irq_control:	IMOD - Interrupt Moderation Register.
+*			Used to throttle interrupts.
+* @erst_size:		Number of segments in the
+			Event Ring Segment Table (ERST).
+* @erst_base:		ERST base address.
+* @erst_dequeue:	Event ring dequeue pointer.
+*
+* Each interrupter (defined by a MSI-X vector) has an event ring and an Event
+* Ring Segment Table (ERST) associated with it.
+* The event ring is comprised of  multiple segments of the same size.
+* The HC places events on the ring and  "updates the Cycle bit in the TRBs to
+* indicate to software the current  position of the Enqueue Pointer."
+* The HCD (Linux) processes those events and  updates the dequeue pointer.
+*/
+struct xhci_intr_reg {
+	volatile __le32	irq_pending;
+	volatile __le32	irq_control;
+	volatile __le32	erst_size;
+	volatile __le32	rsvd;
+	volatile __le64	erst_base;
+	volatile __le64	erst_dequeue;
+};
+
+/* irq_pending bitmasks */
+#define	ER_IRQ_PENDING(p)	((p) & 0x1)
+/* bits 2:31 need to be preserved */
+/* THIS IS BUGGY - FIXME - IP IS WRITE 1 TO CLEAR */
+#define	ER_IRQ_CLEAR(p)		((p) & 0xfffffffe)
+#define	ER_IRQ_ENABLE(p)	((ER_IRQ_CLEAR(p)) | 0x2)
+#define	ER_IRQ_DISABLE(p)	((ER_IRQ_CLEAR(p)) & ~(0x2))
+
+/* irq_control bitmasks */
+/* Minimum interval between interrupts (in 250ns intervals).  The interval
+ * between interrupts will be longer if there are no events on the event ring.
+ * Default is 4000 (1 ms).
+ */
+#define ER_IRQ_INTERVAL_MASK	(0xffff)
+/* Counter used to count down the time to the next interrupt - HW use only */
+#define ER_IRQ_COUNTER_MASK	(0xffff << 16)
+
+/* erst_size bitmasks */
+/* Preserve bits 16:31 of erst_size */
+#define	ERST_SIZE_MASK		(0xffff << 16)
+
+/* erst_dequeue bitmasks */
+/* Dequeue ERST Segment Index (DESI) - Segment number (or alias)
+ * where the current dequeue pointer lies.  This is an optional HW hint.
+ */
+#define ERST_DESI_MASK		(0x7)
+/* Event Handler Busy (EHB) - is the event ring scheduled to be serviced by
+ * a work queue (or delayed service routine)?
+ */
+#define ERST_EHB		(1 << 3)
+#define ERST_PTR_MASK		(0xf)
+
+/**
+ * struct xhci_run_regs
+ * @microframe_index:	MFINDEX - current microframe number
+ *
+ * Section 5.5 Host Controller Runtime Registers:
+ * "Software should read and write these registers using only Dword (32 bit)
+ * or larger accesses"
+ */
+struct xhci_run_regs {
+	__le32			microframe_index;
+	__le32			rsvd[7];
+	struct xhci_intr_reg	ir_set[128];
+};
+
+/**
+ * struct doorbell_array
+ *
+ * Bits  0 -  7: Endpoint target
+ * Bits  8 - 15: RsvdZ
+ * Bits 16 - 31: Stream ID
+ *
+ * Section 5.6
+ */
+struct xhci_doorbell_array {
+	volatile __le32	doorbell[256];
+};
+
+#define DB_VALUE(ep, stream)	((((ep) + 1) & 0xff) | ((stream) << 16))
+#define DB_VALUE_HOST		0x00000000
+
+/**
+ * struct xhci_protocol_caps
+ * @revision:		major revision, minor revision, capability ID,
+ *			and next capability pointer.
+ * @name_string:	Four ASCII characters to say which spec this xHC
+ *			follows, typically "USB ".
+ * @port_info:		Port offset, count, and protocol-defined information.
+ */
+struct xhci_protocol_caps {
+	u32	revision;
+	u32	name_string;
+	u32	port_info;
+};
+
+#define	XHCI_EXT_PORT_MAJOR(x)	(((x) >> 24) & 0xff)
+#define	XHCI_EXT_PORT_OFF(x)	((x) & 0xff)
+#define	XHCI_EXT_PORT_COUNT(x)	(((x) >> 8) & 0xff)
+
+/**
+ * struct xhci_container_ctx
+ * @type: Type of context.  Used to calculated offsets to contained contexts.
+ * @size: Size of the context data
+ * @bytes: The raw context data given to HW
+ * @dma: dma address of the bytes
+ *
+ * Represents either a Device or Input context.  Holds a pointer to the raw
+ * memory used for the context (bytes) and dma address of it (dma).
+ */
+struct xhci_container_ctx {
+	unsigned type;
+#define XHCI_CTX_TYPE_DEVICE  0x1
+#define XHCI_CTX_TYPE_INPUT   0x2
+
+	int size;
+	u8 *bytes;
+};
+
+/**
+ * struct xhci_slot_ctx
+ * @dev_info:	Route string, device speed, hub info, and last valid endpoint
+ * @dev_info2:	Max exit latency for device number, root hub port number
+ * @tt_info:	tt_info is used to construct split transaction tokens
+ * @dev_state:	slot state and device address
+ *
+ * Slot Context - section 6.2.1.1.  This assumes the HC uses 32-byte context
+ * structures.  If the HC uses 64-byte contexts, there is an additional 32 bytes
+ * reserved at the end of the slot context for HC internal use.
+ */
+struct xhci_slot_ctx {
+	__le32	dev_info;
+	__le32	dev_info2;
+	__le32	tt_info;
+	__le32	dev_state;
+	/* offset 0x10 to 0x1f reserved for HC internal use */
+	__le32	reserved[4];
+};
+
+/* dev_info bitmasks */
+/* Route String - 0:19 */
+#define ROUTE_STRING_MASK	(0xfffff)
+/* Device speed - values defined by PORTSC Device Speed field - 20:23 */
+#define DEV_SPEED		(0xf << 20)
+/* bit 24 reserved */
+/* Is this LS/FS device connected through a HS hub? - bit 25 */
+#define DEV_MTT			(0x1 << 25)
+/* Set if the device is a hub - bit 26 */
+#define DEV_HUB			(0x1 << 26)
+/* Index of the last valid endpoint context in this device context - 27:31 */
+#define LAST_CTX_MASK		(0x1f << 27)
+#define LAST_CTX(p)		((p) << 27)
+#define LAST_CTX_TO_EP_NUM(p)	(((p) >> 27) - 1)
+#define SLOT_FLAG		(1 << 0)
+#define EP0_FLAG		(1 << 1)
+
+/* dev_info2 bitmasks */
+/* Max Exit Latency (ms) - worst case time to wake up all links in dev path */
+#define MAX_EXIT			(0xffff)
+/* Root hub port number that is needed to access the USB device */
+#define ROOT_HUB_PORT(p)		(((p) & 0xff) << 16)
+#define ROOT_HUB_PORT_MASK		(0xff)
+#define ROOT_HUB_PORT_SHIFT		(16)
+#define DEVINFO_TO_ROOT_HUB_PORT(p)	(((p) >> 16) & 0xff)
+/* Maximum number of ports under a hub device */
+#define XHCI_MAX_PORTS(p)		(((p) & 0xff) << 24)
+
+/* tt_info bitmasks */
+/*
+ * TT Hub Slot ID - for low or full speed devices attached to a high-speed hub
+ * The Slot ID of the hub that isolates the high speed signaling from
+ * this low or full-speed device.  '0' if attached to root hub port.
+ */
+#define TT_SLOT			(0xff)
+/*
+ * The number of the downstream facing port of the high-speed hub
+ * '0' if the device is not low or full speed.
+ */
+#define TT_PORT			(0xff << 8)
+#define TT_THINK_TIME(p)	(((p) & 0x3) << 16)
+
+/* dev_state bitmasks */
+/* USB device address - assigned by the HC */
+#define DEV_ADDR_MASK	(0xff)
+/* bits 8:26 reserved */
+/* Slot state */
+#define SLOT_STATE		(0x1f << 27)
+#define GET_SLOT_STATE(p)	(((p) & (0x1f << 27)) >> 27)
+
+#define SLOT_STATE_DISABLED	0
+#define SLOT_STATE_ENABLED	SLOT_STATE_DISABLED
+#define SLOT_STATE_DEFAULT	1
+#define SLOT_STATE_ADDRESSED	2
+#define SLOT_STATE_CONFIGURED	3
+
+/**
+ * struct xhci_ep_ctx
+ * @ep_info:	endpoint state, streams, mult, and interval information.
+ * @ep_info2:	information on endpoint type, max packet size, max burst size,
+ *		error count, and whether the HC will force an event for all
+ *		transactions.
+ * @deq:	64-bit ring dequeue pointer address.  If the endpoint only
+ *		defines one stream, this points to the endpoint transfer ring.
+ *		Otherwise, it points to a stream context array, which has a
+ *		ring pointer for each flow.
+ * @tx_info:
+ *		Average TRB lengths for the endpoint ring and
+ *		max payload within an Endpoint Service Interval Time (ESIT).
+ *
+ * Endpoint Context - section 6.2.1.2.This assumes the HC uses 32-byte context
+ * structures.If the HC uses 64-byte contexts, there is an additional 32 bytes
+ * reserved at the end of the endpoint context for HC internal use.
+ */
+struct xhci_ep_ctx {
+	__le32	ep_info;
+	__le32	ep_info2;
+	__le64	deq;
+	__le32	tx_info;
+	/* offset 0x14 - 0x1f reserved for HC internal use */
+	__le32	reserved[3];
+};
+
+/* ep_info bitmasks */
+/*
+ * Endpoint State - bits 0:2
+ * 0 - disabled
+ * 1 - running
+ * 2 - halted due to halt condition - ok to manipulate endpoint ring
+ * 3 - stopped
+ * 4 - TRB error
+ * 5-7 - reserved
+ */
+#define EP_STATE_MASK		(0xf)
+#define EP_STATE_DISABLED	0
+#define EP_STATE_RUNNING	1
+#define EP_STATE_HALTED		2
+#define EP_STATE_STOPPED	3
+#define EP_STATE_ERROR		4
+/* Mult - Max number of burtst within an interval, in EP companion desc. */
+#define EP_MULT(p)		(((p) & 0x3) << 8)
+#define CTX_TO_EP_MULT(p)	(((p) >> 8) & 0x3)
+/* bits 10:14 are Max Primary Streams */
+/* bit 15 is Linear Stream Array */
+/* Interval - period between requests to an endpoint - 125u increments. */
+#define EP_INTERVAL(p)			(((p) & 0xff) << 16)
+#define EP_INTERVAL_TO_UFRAMES(p)	(1 << (((p) >> 16) & 0xff))
+#define CTX_TO_EP_INTERVAL(p)		(((p) >> 16) & 0xff)
+#define EP_MAXPSTREAMS_MASK		(0x1f << 10)
+#define EP_MAXPSTREAMS(p)		(((p) << 10) & EP_MAXPSTREAMS_MASK)
+/* Endpoint is set up with a Linear Stream Array (vs. Secondary Stream Array) */
+#define	EP_HAS_LSA			(1 << 15)
+
+/* ep_info2 bitmasks */
+/*
+ * Force Event - generate transfer events for all TRBs for this endpoint
+ * This will tell the HC to ignore the IOC and ISP flags (for debugging only).
+ */
+#define	FORCE_EVENT		(0x1)
+#define ERROR_COUNT(p)		(((p) & 0x3) << 1)
+#define ERROR_COUNT_SHIFT	(1)
+#define ERROR_COUNT_MASK	(0x3)
+#define CTX_TO_EP_TYPE(p)	(((p) >> 3) & 0x7)
+#define EP_TYPE(p)		((p) << 3)
+#define EP_TYPE_SHIFT		(3)
+#define ISOC_OUT_EP		1
+#define BULK_OUT_EP		2
+#define INT_OUT_EP		3
+#define CTRL_EP			4
+#define ISOC_IN_EP		5
+#define BULK_IN_EP		6
+#define INT_IN_EP		7
+/* bit 6 reserved */
+/* bit 7 is Host Initiate Disable - for disabling stream selection */
+#define MAX_BURST(p)		(((p)&0xff) << 8)
+#define MAX_BURST_MASK		(0xff)
+#define MAX_BURST_SHIFT		(8)
+#define CTX_TO_MAX_BURST(p)	(((p) >> 8) & 0xff)
+#define MAX_PACKET(p)		(((p)&0xffff) << 16)
+#define MAX_PACKET_MASK		(0xffff)
+#define MAX_PACKET_DECODED(p)	(((p) >> 16) & 0xffff)
+#define MAX_PACKET_SHIFT	(16)
+
+/* Get max packet size from ep desc. Bit 10..0 specify the max packet size.
+ * USB2.0 spec 9.6.6.
+ */
+#define GET_MAX_PACKET(p)	((p) & 0x7ff)
+
+/* tx_info bitmasks */
+#define AVG_TRB_LENGTH_FOR_EP(p)	((p) & 0xffff)
+#define MAX_ESIT_PAYLOAD_FOR_EP(p)	(((p) & 0xffff) << 16)
+#define CTX_TO_MAX_ESIT_PAYLOAD(p)	(((p) >> 16) & 0xffff)
+
+/* deq bitmasks */
+#define EP_CTX_CYCLE_MASK		(1 << 0)
+
+
+/**
+ * struct xhci_input_control_context
+ * Input control context; see section 6.2.5.
+ *
+ * @drop_context:	set the bit of the endpoint context you want to disable
+ * @add_context:	set the bit of the endpoint context you want to enable
+ */
+struct xhci_input_control_ctx {
+	volatile __le32	drop_flags;
+	volatile __le32	add_flags;
+	__le32	rsvd2[6];
+};
+
+
+/**
+ * struct xhci_device_context_array
+ * @dev_context_ptr	array of 64-bit DMA addresses for device contexts
+ */
+struct xhci_device_context_array {
+	/* 64-bit device addresses; we only write 32-bit addresses */
+	__le64			dev_context_ptrs[MAX_HC_SLOTS];
+};
+/* TODO: write function to set the 64-bit device DMA address */
+/*
+ * TODO: change this to be dynamically sized at HC mem init time since the HC
+ * might not be able to handle the maximum number of devices possible.
+ */
+
+
+struct xhci_transfer_event {
+	/* 64-bit buffer address, or immediate data */
+	__le64	buffer;
+	__le32	transfer_len;
+	/* This field is interpreted differently based on the type of TRB */
+	volatile __le32	flags;
+};
+
+/* Transfer event TRB length bit mask */
+/* bits 0:23 */
+#define EVENT_TRB_LEN(p)	((p) & 0xffffff)
+
+/** Transfer Event bit fields **/
+#define	TRB_TO_EP_ID(p)		(((p) >> 16) & 0x1f)
+
+/* Completion Code - only applicable for some types of TRBs */
+#define	COMP_CODE_MASK		(0xff << 24)
+#define	COMP_CODE_SHIFT		(24)
+#define GET_COMP_CODE(p)	(((p) & COMP_CODE_MASK) >> 24)
+
+typedef enum {
+	COMP_SUCCESS = 1,
+	/* Data Buffer Error */
+	COMP_DB_ERR, /* 2 */
+	/* Babble Detected Error */
+	COMP_BABBLE, /* 3 */
+	/* USB Transaction Error */
+	COMP_TX_ERR, /* 4 */
+	/* TRB Error - some TRB field is invalid */
+	COMP_TRB_ERR, /* 5 */
+	/* Stall Error - USB device is stalled */
+	COMP_STALL, /* 6 */
+	/* Resource Error - HC doesn't have memory for that device configuration */
+	COMP_ENOMEM, /* 7 */
+	/* Bandwidth Error - not enough room in schedule for this dev config */
+	COMP_BW_ERR, /* 8 */
+	/* No Slots Available Error - HC ran out of device slots */
+	COMP_ENOSLOTS, /* 9 */
+	/* Invalid Stream Type Error */
+	COMP_STREAM_ERR, /* 10 */
+	/* Slot Not Enabled Error - doorbell rung for disabled device slot */
+	COMP_EBADSLT, /* 11 */
+	/* Endpoint Not Enabled Error */
+	COMP_EBADEP,/* 12 */
+	/* Short Packet */
+	COMP_SHORT_TX, /* 13 */
+	/* Ring Underrun - doorbell rung for an empty isoc OUT ep ring */
+	COMP_UNDERRUN, /* 14 */
+	/* Ring Overrun - isoc IN ep ring is empty when ep is scheduled to RX */
+	COMP_OVERRUN, /* 15 */
+	/* Virtual Function Event Ring Full Error */
+	COMP_VF_FULL, /* 16 */
+	/* Parameter Error - Context parameter is invalid */
+	COMP_EINVAL, /* 17 */
+	/* Bandwidth Overrun Error - isoc ep exceeded its allocated bandwidth */
+	COMP_BW_OVER,/* 18 */
+	/* Context State Error - illegal context state transition requested */
+	COMP_CTX_STATE,/* 19 */
+	/* No Ping Response Error - HC didn't get PING_RESPONSE in time to TX */
+	COMP_PING_ERR,/* 20 */
+	/* Event Ring is full */
+	COMP_ER_FULL,/* 21 */
+	/* Incompatible Device Error */
+	COMP_DEV_ERR,/* 22 */
+	/* Missed Service Error - HC couldn't service an isoc ep within interval */
+	COMP_MISSED_INT,/* 23 */
+	/* Successfully stopped command ring */
+	COMP_CMD_STOP, /* 24 */
+	/* Successfully aborted current command and stopped command ring */
+	COMP_CMD_ABORT, /* 25 */
+	/* Stopped - transfer was terminated by a stop endpoint command */
+	COMP_STOP,/* 26 */
+	/* Same as COMP_EP_STOPPED, but the transferred length in the event
+	 * is invalid */
+	COMP_STOP_INVAL, /* 27*/
+	/* Control Abort Error - Debug Capability - control pipe aborted */
+	COMP_DBG_ABORT, /* 28 */
+	/* Max Exit Latency Too Large Error */
+	COMP_MEL_ERR,/* 29 */
+	/* TRB type 30 reserved */
+	/* Isoc Buffer Overrun - an isoc IN ep sent more data than could fit in TD */
+	COMP_BUFF_OVER = 31,
+	/* Event Lost Error - xHC has an "internal event overrun condition" */
+	COMP_ISSUES, /* 32 */
+	/* Undefined Error - reported when other error codes don't apply */
+	COMP_UNKNOWN, /* 33 */
+	/* Invalid Stream ID Error */
+	COMP_STRID_ERR, /* 34 */
+	/* Secondary Bandwidth Error - may be returned by a Configure Endpoint cmd */
+	COMP_2ND_BW_ERR, /* 35 */
+	/* Split Transaction Error */
+	COMP_SPLIT_ERR /* 36 */
+
+} xhci_comp_code;
+
+struct xhci_link_trb {
+	/* 64-bit segment pointer*/
+	volatile __le64 segment_ptr;
+	volatile __le32 intr_target;
+	volatile __le32 control;
+};
+
+/* control bitfields */
+#define LINK_TOGGLE (0x1 << 1)
+
+/* Command completion event TRB */
+struct xhci_event_cmd {
+	/* Pointer to command TRB, or the value passed by the event data trb */
+	volatile __le64 cmd_trb;
+	volatile __le32 status;
+	volatile __le32 flags;
+};
+
+/* flags bitmasks */
+/* bits 16:23 are the virtual function ID */
+/* bits 24:31 are the slot ID */
+#define	TRB_TO_SLOT_ID(p)		(((p) & (0xff << 24)) >> 24)
+#define	TRB_TO_SLOT_ID_SHIFT		(24)
+#define	TRB_TO_SLOT_ID_MASK		(0xff << TRB_TO_SLOT_ID_SHIFT)
+#define	SLOT_ID_FOR_TRB(p)		(((p) & 0xff) << 24)
+#define	SLOT_ID_FOR_TRB_MASK		(0xff)
+#define	SLOT_ID_FOR_TRB_SHIFT		(24)
+
+/* Stop Endpoint TRB - ep_index to endpoint ID for this TRB */
+#define TRB_TO_EP_INDEX(p)		((((p) & (0x1f << 16)) >> 16) - 1)
+#define	EP_ID_FOR_TRB(p)		((((p) + 1) & 0x1f) << 16)
+
+#define SUSPEND_PORT_FOR_TRB(p)		(((p) & 1) << 23)
+#define TRB_TO_SUSPEND_PORT(p)		(((p) & (1 << 23)) >> 23)
+#define LAST_EP_INDEX			30
+
+/* Set TR Dequeue Pointer command TRB fields */
+#define TRB_TO_STREAM_ID(p)		((((p) & (0xffff << 16)) >> 16))
+#define STREAM_ID_FOR_TRB(p)		((((p)) & 0xffff) << 16)
+
+
+/* Port Status Change Event TRB fields */
+/* Port ID - bits 31:24 */
+#define GET_PORT_ID(p)			(((p) & (0xff << 24)) >> 24)
+#define	PORT_ID_SHIFT			(24)
+#define	PORT_ID_MASK			(0xff << PORT_ID_SHIFT)
+
+/* Normal TRB fields */
+/* transfer_len bitmasks - bits 0:16 */
+#define	TRB_LEN(p)			((p) & 0x1ffff)
+#define	TRB_LEN_MASK			(0x1ffff)
+/* Interrupter Target - which MSI-X vector to target the completion event at */
+#define	TRB_INTR_TARGET_SHIFT		(22)
+#define	TRB_INTR_TARGET_MASK		(0x3ff)
+#define TRB_INTR_TARGET(p)		(((p) & 0x3ff) << 22)
+#define GET_INTR_TARGET(p)		(((p) >> 22) & 0x3ff)
+#define TRB_TBC(p)			(((p) & 0x3) << 7)
+#define TRB_TLBPC(p)			(((p) & 0xf) << 16)
+
+/* Cycle bit - indicates TRB ownership by HC or HCD */
+#define TRB_CYCLE		(1<<0)
+/*
+ * Force next event data TRB to be evaluated before task switch.
+ * Used to pass OS data back after a TD completes.
+ */
+#define TRB_ENT			(1<<1)
+/* Interrupt on short packet */
+#define TRB_ISP			(1<<2)
+/* Set PCIe no snoop attribute */
+#define TRB_NO_SNOOP		(1<<3)
+/* Chain multiple TRBs into a TD */
+#define TRB_CHAIN		(1<<4)
+/* Interrupt on completion */
+#define TRB_IOC			(1<<5)
+/* The buffer pointer contains immediate data */
+#define TRB_IDT			(1<<6)
+
+/* Block Event Interrupt */
+#define	TRB_BEI			(1<<9)
+
+/* Control transfer TRB specific fields */
+#define TRB_DIR_IN		(1<<16)
+#define	TRB_TX_TYPE(p)		((p) << 16)
+#define	TRB_TX_TYPE_SHIFT	(16)
+#define	TRB_DATA_OUT		2
+#define	TRB_DATA_IN		3
+
+/* Isochronous TRB specific fields */
+#define TRB_SIA			(1 << 31)
+
+struct xhci_generic_trb {
+	volatile __le32 field[4];
+};
+
+union xhci_trb {
+	struct xhci_link_trb		link;
+	struct xhci_transfer_event	trans_event;
+	struct xhci_event_cmd		event_cmd;
+	struct xhci_generic_trb		generic;
+};
+
+/* TRB bit mask */
+#define	TRB_TYPE_BITMASK	(0xfc00)
+#define TRB_TYPE(p)		((p) << 10)
+#define TRB_TYPE_SHIFT		(10)
+#define TRB_FIELD_TO_TYPE(p)	(((p) & TRB_TYPE_BITMASK) >> 10)
+
+/* TRB type IDs */
+typedef enum {
+	/* bulk, interrupt, isoc scatter/gather, and control data stage */
+	TRB_NORMAL = 1,
+	/* setup stage for control transfers */
+	TRB_SETUP, /* 2 */
+	/* data stage for control transfers */
+	TRB_DATA, /* 3 */
+	/* status stage for control transfers */
+	TRB_STATUS, /* 4 */
+	/* isoc transfers */
+	TRB_ISOC, /* 5 */
+	/* TRB for linking ring segments */
+	TRB_LINK, /* 6 */
+	/* TRB for EVENT DATA */
+	TRB_EVENT_DATA, /* 7 */
+	/* Transfer Ring No-op (not for the command ring) */
+	TRB_TR_NOOP, /* 8 */
+	/* Command TRBs */
+	/* Enable Slot Command */
+	TRB_ENABLE_SLOT, /* 9 */
+	/* Disable Slot Command */
+	TRB_DISABLE_SLOT, /* 10 */
+	/* Address Device Command */
+	TRB_ADDR_DEV, /* 11 */
+	/* Configure Endpoint Command */
+	TRB_CONFIG_EP, /* 12 */
+	/* Evaluate Context Command */
+	TRB_EVAL_CONTEXT, /* 13 */
+	/* Reset Endpoint Command */
+	TRB_RESET_EP, /* 14 */
+	/* Stop Transfer Ring Command */
+	TRB_STOP_RING, /* 15 */
+	/* Set Transfer Ring Dequeue Pointer Command */
+	TRB_SET_DEQ, /* 16 */
+	/* Reset Device Command */
+	TRB_RESET_DEV, /* 17 */
+	/* Force Event Command (opt) */
+	TRB_FORCE_EVENT, /* 18 */
+	/* Negotiate Bandwidth Command (opt) */
+	TRB_NEG_BANDWIDTH, /* 19 */
+	/* Set Latency Tolerance Value Command (opt) */
+	TRB_SET_LT, /* 20 */
+	/* Get port bandwidth Command */
+	TRB_GET_BW, /* 21 */
+	/* Force Header Command - generate a transaction or link management packet */
+	TRB_FORCE_HEADER, /* 22 */
+	/* No-op Command - not for transfer rings */
+	TRB_CMD_NOOP, /* 23 */
+	/* TRB IDs 24-31 reserved */
+	/* Event TRBS */
+	/* Transfer Event */
+	TRB_TRANSFER = 32,
+	/* Command Completion Event */
+	TRB_COMPLETION, /* 33 */
+	/* Port Status Change Event */
+	TRB_PORT_STATUS, /* 34 */
+	/* Bandwidth Request Event (opt) */
+	TRB_BANDWIDTH_EVENT, /* 35 */
+	/* Doorbell Event (opt) */
+	TRB_DOORBELL, /* 36 */
+	/* Host Controller Event */
+	TRB_HC_EVENT, /* 37 */
+	/* Device Notification Event - device sent function wake notification */
+	TRB_DEV_NOTE, /* 38 */
+	/* MFINDEX Wrap Event - microframe counter wrapped */
+	TRB_MFINDEX_WRAP, /* 39 */
+	/* TRB IDs 40-47 reserved, 48-63 is vendor-defined */
+	/* Nec vendor-specific command completion event. */
+	TRB_NEC_CMD_COMP = 48, /* 48 */
+	/* Get NEC firmware revision. */
+	TRB_NEC_GET_FW, /* 49 */
+} trb_type;
+
+#define TRB_TYPE_LINK(x)	(((x) & TRB_TYPE_BITMASK) == TRB_TYPE(TRB_LINK))
+/* Above, but for __le32 types -- can avoid work by swapping constants: */
+#define TRB_TYPE_LINK_LE32(x)	(((x) & cpu_to_le32(TRB_TYPE_BITMASK)) == \
+				 cpu_to_le32(TRB_TYPE(TRB_LINK)))
+#define TRB_TYPE_NOOP_LE32(x)	(((x) & cpu_to_le32(TRB_TYPE_BITMASK)) == \
+				 cpu_to_le32(TRB_TYPE(TRB_TR_NOOP)))
+
+/*
+ * TRBS_PER_SEGMENT must be a multiple of 4,
+ * since the command ring is 64-byte aligned.
+ * It must also be greater than 16.
+ */
+#define TRBS_PER_SEGMENT	64
+/* Allow two commands + a link TRB, along with any reserved command TRBs */
+#define MAX_RSVD_CMD_TRBS	(TRBS_PER_SEGMENT - 3)
+#define SEGMENT_SIZE		(TRBS_PER_SEGMENT*16)
+/* SEGMENT_SHIFT should be log2(SEGMENT_SIZE).
+ * Change this if you change TRBS_PER_SEGMENT!
+ */
+#define SEGMENT_SHIFT		10
+/* TRB buffer pointers can't cross 64KB boundaries */
+#define TRB_MAX_BUFF_SHIFT	16
+#define TRB_MAX_BUFF_SIZE	(1 << TRB_MAX_BUFF_SHIFT)
+
+struct xhci_segment {
+	union xhci_trb		*trbs;
+	/* private to HCD */
+	struct xhci_segment	*next;
+};
+
+struct xhci_ring {
+	struct xhci_segment	*first_seg;
+	union  xhci_trb		*enqueue;
+	struct xhci_segment	*enq_seg;
+	union  xhci_trb		*dequeue;
+	struct xhci_segment	*deq_seg;
+	/*
+	 * Write the cycle state into the TRB cycle field to give ownership of
+	 * the TRB to the host controller (if we are the producer), or to check
+	 * if we own the TRB (if we are the consumer).  See section 4.9.1.
+	 */
+	volatile u32		cycle_state;
+	unsigned int		num_segs;
+};
+
+struct xhci_erst_entry {
+	/* 64-bit event ring segment address */
+	__le64	seg_addr;
+	__le32	seg_size;
+	/* Set to zero */
+	__le32	rsvd;
+};
+
+struct xhci_erst {
+	struct xhci_erst_entry	*entries;
+	unsigned int		num_entries;
+	/* Num entries the ERST can contain */
+	unsigned int		erst_size;
+};
+
+/*
+ * Each segment table entry is 4*32bits long.  1K seems like an ok size:
+ * (1K bytes * 8bytes/bit) / (4*32 bits) = 64 segment entries in the table,
+ * meaning 64 ring segments.
+ * Initial allocated size of the ERST, in number of entries */
+#define	ERST_NUM_SEGS	3
+/* Initial number of event segment rings allocated */
+#define	ERST_ENTRIES	3
+/* Initial allocated size of the ERST, in number of entries */
+#define	ERST_SIZE	64
+/* Poll every 60 seconds */
+#define	POLL_TIMEOUT	60
+/* Stop endpoint command timeout (secs) for URB cancellation watchdog timer */
+#define XHCI_STOP_EP_CMD_TIMEOUT	5
+/* XXX: Make these module parameters */
+
+struct xhci_virt_ep {
+	struct xhci_ring		*ring;
+	unsigned int			ep_state;
+#define SET_DEQ_PENDING		(1 << 0)
+#define EP_HALTED		(1 << 1)	/* For stall handling */
+#define EP_HALT_PENDING		(1 << 2)	/* For URB cancellation */
+/* Transitioning the endpoint to using streams, don't enqueue URBs */
+#define EP_GETTING_STREAMS	(1 << 3)
+#define EP_HAS_STREAMS		(1 << 4)
+/* Transitioning the endpoint to not using streams, don't enqueue URBs */
+#define EP_GETTING_NO_STREAMS	(1 << 5)
+};
+
+#define CTX_SIZE(_hcc) (HCC_64BYTE_CONTEXT(_hcc) ? 64 : 32)
+
+struct xhci_virt_device {
+	struct usb_device		*udev;
+	/*
+	 * Commands to the hardware are passed an "input context" that
+	 * tells the hardware what to change in its data structures.
+	 * The hardware will return changes in an "output context" that
+	 * software must allocate for the hardware.  We need to keep
+	 * track of input and output contexts separately because
+	 * these commands might fail and we don't trust the hardware.
+	 */
+	struct xhci_container_ctx       *out_ctx;
+	/* Used for addressing devices and configuration changes */
+	struct xhci_container_ctx       *in_ctx;
+	/* Rings saved to ensure old alt settings can be re-instated */
+#define	XHCI_MAX_RINGS_CACHED	31
+	struct xhci_virt_ep		eps[31];
+};
+
+/* TODO: copied from ehci.h - can be refactored? */
+/* xHCI spec says all registers are little endian */
+static inline unsigned int xhci_readl(uint32_t volatile *regs)
+{
+	return readl(regs);
+}
+
+static inline void xhci_writel(uint32_t volatile *regs, const unsigned int val)
+{
+	writel(val, regs);
+}
+
+/*
+ * Registers should always be accessed with double word or quad word accesses.
+ * Some xHCI implementations may support 64-bit address pointers.  Registers
+ * with 64-bit address pointers should be written to with dword accesses by
+ * writing the low dword first (ptr[0]), then the high dword (ptr[1]) second.
+ * xHCI implementations that do not support 64-bit address pointers will ignore
+ * the high dword, and write order is irrelevant.
+ */
+static inline u64 xhci_readq(__le64 volatile *regs)
+{
+	__u32 *ptr = (__u32 *)regs;
+	u64 val_lo = readl(ptr);
+	u64 val_hi = readl(ptr + 1);
+	return val_lo + (val_hi << 32);
+}
+
+static inline void xhci_writeq(__le64 volatile *regs, const u64 val)
+{
+	__u32 *ptr = (__u32 *)regs;
+	u32 val_lo = lower_32_bits(val);
+	/* FIXME */
+	u32 val_hi = 0;
+	writel(val_lo, ptr);
+	writel(val_hi, ptr + 1);
+}
+
+int xhci_hcd_init(int index, struct xhci_hccr **ret_hccr,
+					struct xhci_hcor **ret_hcor);
+void xhci_hcd_stop(int index);
+
+
+/*************************************************************
+	EXTENDED CAPABILITY DEFINITIONS
+*************************************************************/
+/* Up to 16 ms to halt an HC */
+#define XHCI_MAX_HALT_USEC	(16*1000)
+/* HC not running - set to 1 when run/stop bit is cleared. */
+#define XHCI_STS_HALT		(1 << 0)
+
+/* HCCPARAMS offset from PCI base address */
+#define XHCI_HCC_PARAMS_OFFSET	0x10
+/* HCCPARAMS contains the first extended capability pointer */
+#define XHCI_HCC_EXT_CAPS(p)	(((p)>>16)&0xffff)
+
+/* Command and Status registers offset from the Operational Registers address */
+#define XHCI_CMD_OFFSET		0x00
+#define XHCI_STS_OFFSET		0x04
+
+#define XHCI_MAX_EXT_CAPS		50
+
+/* Capability Register */
+/* bits 7:0 - how long is the Capabilities register */
+#define XHCI_HC_LENGTH(p)	(((p) >> 00) & 0x00ff)
+
+/* Extended capability register fields */
+#define XHCI_EXT_CAPS_ID(p)	(((p) >> 0) & 0xff)
+#define XHCI_EXT_CAPS_NEXT(p)	(((p) >> 8) & 0xff)
+#define	XHCI_EXT_CAPS_VAL(p)	((p) >> 16)
+/* Extended capability IDs - ID 0 reserved */
+#define XHCI_EXT_CAPS_LEGACY	1
+#define XHCI_EXT_CAPS_PROTOCOL	2
+#define XHCI_EXT_CAPS_PM	3
+#define XHCI_EXT_CAPS_VIRT	4
+#define XHCI_EXT_CAPS_ROUTE	5
+/* IDs 6-9 reserved */
+#define XHCI_EXT_CAPS_DEBUG	10
+/* USB Legacy Support Capability - section 7.1.1 */
+#define XHCI_HC_BIOS_OWNED	(1 << 16)
+#define XHCI_HC_OS_OWNED	(1 << 24)
+
+/* USB Legacy Support Capability - section 7.1.1 */
+/* Add this offset, plus the value of xECP in HCCPARAMS to the base address */
+#define XHCI_LEGACY_SUPPORT_OFFSET	(0x00)
+
+/* USB Legacy Support Control and Status Register  - section 7.1.2 */
+/* Add this offset, plus the value of xECP in HCCPARAMS to the base address */
+#define XHCI_LEGACY_CONTROL_OFFSET	(0x04)
+/* bits 1:2, 5:12, and 17:19 need to be preserved; bits 21:28 should be zero */
+#define	XHCI_LEGACY_DISABLE_SMI		((0x3 << 1) + (0xff << 5) + (0x7 << 17))
+
+/* USB 2.0 xHCI 0.96 L1C capability - section 7.2.2.1.3.2 */
+#define XHCI_L1C               (1 << 16)
+
+/* USB 2.0 xHCI 1.0 hardware LMP capability - section 7.2.2.1.3.2 */
+#define XHCI_HLC               (1 << 19)
+
+/* command register values to disable interrupts and halt the HC */
+/* start/stop HC execution - do not write unless HC is halted*/
+#define XHCI_CMD_RUN		(1 << 0)
+/* Event Interrupt Enable - get irq when EINT bit is set in USBSTS register */
+#define XHCI_CMD_EIE		(1 << 2)
+/* Host System Error Interrupt Enable - get irq when HSEIE bit set in USBSTS */
+#define XHCI_CMD_HSEIE		(1 << 3)
+/* Enable Wrap Event - '1' means xHC generates an event when MFINDEX wraps. */
+#define XHCI_CMD_EWE		(1 << 10)
+
+#define XHCI_IRQS		(XHCI_CMD_EIE | XHCI_CMD_HSEIE | XHCI_CMD_EWE)
+
+/* true: Controller Not Ready to accept doorbell or op reg writes after reset */
+#define XHCI_STS_CNR		(1 << 11)
+
+struct xhci_ctrl {
+	struct xhci_hccr *hccr;	/* R/O registers, not need for volatile */
+	struct xhci_hcor *hcor;
+	struct xhci_doorbell_array *dba;
+	struct xhci_run_regs *run_regs;
+	struct xhci_device_context_array *dcbaa		\
+			__attribute__ ((aligned(ARCH_DMA_MINALIGN)));
+	struct xhci_ring *event_ring;
+	struct xhci_ring *cmd_ring;
+	struct xhci_ring *transfer_ring;
+	struct xhci_segment *seg;
+	struct xhci_intr_reg *ir_set;
+	struct xhci_erst erst;
+	struct xhci_erst_entry entry[ERST_NUM_SEGS];
+	struct xhci_virt_device *devs[MAX_HC_SLOTS];
+	int rootdev;
+};
+
+unsigned long trb_addr(struct xhci_segment *seg, union xhci_trb *trb);
+struct xhci_input_control_ctx
+		*xhci_get_input_control_ctx(struct xhci_container_ctx *ctx);
+struct xhci_slot_ctx *xhci_get_slot_ctx(struct xhci_ctrl *ctrl,
+					struct xhci_container_ctx *ctx);
+struct xhci_ep_ctx *xhci_get_ep_ctx(struct xhci_ctrl *ctrl,
+				    struct xhci_container_ctx *ctx,
+				    unsigned int ep_index);
+void xhci_endpoint_copy(struct xhci_ctrl *ctrl,
+			struct xhci_container_ctx *in_ctx,
+			struct xhci_container_ctx *out_ctx,
+			unsigned int ep_index);
+void xhci_slot_copy(struct xhci_ctrl *ctrl,
+		    struct xhci_container_ctx *in_ctx,
+		    struct xhci_container_ctx *out_ctx);
+void xhci_setup_addressable_virt_dev(struct usb_device *udev);
+void xhci_queue_command(struct xhci_ctrl *ctrl, u8 *ptr,
+			u32 slot_id, u32 ep_index, trb_type cmd);
+void xhci_acknowledge_event(struct xhci_ctrl *ctrl);
+union xhci_trb *xhci_wait_for_event(struct xhci_ctrl *ctrl, trb_type expected);
+int xhci_bulk_tx(struct usb_device *udev, unsigned long pipe,
+		 int length, void *buffer);
+int xhci_ctrl_tx(struct usb_device *udev, unsigned long pipe,
+		 struct devrequest *req, int length, void *buffer);
+int xhci_check_maxpacket(struct usb_device *udev);
+void xhci_flush_cache(uint32_t addr, u32 type_len);
+void xhci_inval_cache(uint32_t addr, u32 type_len);
+void xhci_cleanup(struct xhci_ctrl *ctrl);
+struct xhci_ring *xhci_ring_alloc(unsigned int num_segs, bool link_trbs);
+int xhci_alloc_virt_device(struct usb_device *udev);
+int xhci_mem_init(struct xhci_ctrl *ctrl, struct xhci_hccr *hccr,
+		  struct xhci_hcor *hcor);
+
+#endif /* HOST_XHCI_H_ */
diff --git a/drivers/usb/musb-new/Makefile b/drivers/usb/musb-new/Makefile
index 626af3e8cd..3facf0fc10 100644
--- a/drivers/usb/musb-new/Makefile
+++ b/drivers/usb/musb-new/Makefile
@@ -2,37 +2,13 @@
 # for USB OTG silicon based on Mentor Graphics INVENTRA designs
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	:= $(obj)libusb_musb-new.o
-
-COBJS-$(CONFIG_MUSB_GADGET) += musb_gadget.o musb_gadget_ep0.o musb_core.o
-COBJS-$(CONFIG_MUSB_GADGET) += musb_uboot.o
-COBJS-$(CONFIG_MUSB_HOST) += musb_host.o musb_core.o musb_uboot.o
-COBJS-$(CONFIG_USB_MUSB_DSPS) += musb_dsps.o
-COBJS-$(CONFIG_USB_MUSB_AM35X) += am35x.o
-COBJS-$(CONFIG_USB_MUSB_OMAP2PLUS) += omap2430.o
-
-CFLAGS_NO_WARN := $(call cc-option,-Wno-unused-variable) \
-			$(call cc-option,-Wno-unused-but-set-variable) \
-			$(call cc-option,-Wno-unused-label)
-CFLAGS += $(CFLAGS_NO_WARN)
-
-COBJS	:= $(sort $(COBJS-y))
-SRCS	:= $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-
-all:	$(LIB)
-
-#$(LIB):	$(OBJS)
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-$(CONFIG_MUSB_GADGET) += musb_gadget.o musb_gadget_ep0.o musb_core.o
+obj-$(CONFIG_MUSB_GADGET) += musb_uboot.o
+obj-$(CONFIG_MUSB_HOST) += musb_host.o musb_core.o musb_uboot.o
+obj-$(CONFIG_USB_MUSB_DSPS) += musb_dsps.o
+obj-$(CONFIG_USB_MUSB_AM35X) += am35x.o
+obj-$(CONFIG_USB_MUSB_OMAP2PLUS) += omap2430.o
+
+ccflags-y := $(call cc-option,-Wno-unused-variable) \
+		$(call cc-option,-Wno-unused-but-set-variable) \
+		$(call cc-option,-Wno-unused-label)
diff --git a/drivers/usb/musb-new/musb_uboot.c b/drivers/usb/musb-new/musb_uboot.c
index c2400328a3..05126803c3 100644
--- a/drivers/usb/musb-new/musb_uboot.c
+++ b/drivers/usb/musb-new/musb_uboot.c
@@ -112,7 +112,7 @@ int submit_int_msg(struct usb_device *dev, unsigned long pipe,
 	return submit_urb(&hcd, urb);
 }
 
-int usb_lowlevel_init(int index, void **controller)
+int usb_lowlevel_init(int index, enum usb_init_type init, void **controller)
 {
 	u8 power;
 	void *mbase;
diff --git a/drivers/usb/musb/Makefile b/drivers/usb/musb/Makefile
index aa2126dcb0..3c9ed98bc0 100644
--- a/drivers/usb/musb/Makefile
+++ b/drivers/usb/musb/Makefile
@@ -5,32 +5,10 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	:= $(obj)libusb_musb.o
-
-COBJS-$(CONFIG_MUSB_HCD) += musb_hcd.o musb_core.o
-COBJS-$(CONFIG_MUSB_UDC) += musb_udc.o musb_core.o
-COBJS-$(CONFIG_USB_BLACKFIN) += blackfin_usb.o
-COBJS-$(CONFIG_USB_DAVINCI) += davinci.o
-COBJS-$(CONFIG_USB_OMAP3) += omap3.o
-COBJS-$(CONFIG_USB_DA8XX) += da8xx.o
-COBJS-$(CONFIG_USB_AM35X) += am35x.o
-
-COBJS	:= $(COBJS-y)
-SRCS	:= $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-
-all:	$(LIB)
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-$(CONFIG_MUSB_HCD) += musb_hcd.o musb_core.o
+obj-$(CONFIG_MUSB_UDC) += musb_udc.o musb_core.o
+obj-$(CONFIG_USB_BLACKFIN) += blackfin_usb.o
+obj-$(CONFIG_USB_DAVINCI) += davinci.o
+obj-$(CONFIG_USB_OMAP3) += omap3.o
+obj-$(CONFIG_USB_DA8XX) += da8xx.o
+obj-$(CONFIG_USB_AM35X) += am35x.o
diff --git a/drivers/usb/musb/blackfin_usb.c b/drivers/usb/musb/blackfin_usb.c
index 35268ba58e..65fff887d3 100644
--- a/drivers/usb/musb/blackfin_usb.c
+++ b/drivers/usb/musb/blackfin_usb.c
@@ -11,6 +11,7 @@
 #include <usb.h>
 
 #include <asm/blackfin.h>
+#include <asm/clock.h>
 #include <asm/mach-common/bits/usb.h>
 
 #include "musb_core.h"
diff --git a/drivers/usb/musb/musb_hcd.c b/drivers/usb/musb/musb_hcd.c
index 708fa124a2..f0ba8aaaa3 100644
--- a/drivers/usb/musb/musb_hcd.c
+++ b/drivers/usb/musb/musb_hcd.c
@@ -28,99 +28,8 @@ static const struct musb_epinfo epinfo[3] = {
 static int rh_devnum;
 static u32 port_status;
 
-/* Device descriptor */
-static const u8 root_hub_dev_des[] = {
-	0x12,			/*  __u8  bLength; */
-	0x01,			/*  __u8  bDescriptorType; Device */
-	0x00,			/*  __u16 bcdUSB; v1.1 */
-	0x02,
-	0x09,			/*  __u8  bDeviceClass; HUB_CLASSCODE */
-	0x00,			/*  __u8  bDeviceSubClass; */
-	0x00,			/*  __u8  bDeviceProtocol; */
-	0x08,			/*  __u8  bMaxPacketSize0; 8 Bytes */
-	0x00,			/*  __u16 idVendor; */
-	0x00,
-	0x00,			/*  __u16 idProduct; */
-	0x00,
-	0x00,			/*  __u16 bcdDevice; */
-	0x00,
-	0x00,			/*  __u8  iManufacturer; */
-	0x01,			/*  __u8  iProduct; */
-	0x00,			/*  __u8  iSerialNumber; */
-	0x01			/*  __u8  bNumConfigurations; */
-};
-
-/* Configuration descriptor */
-static const u8 root_hub_config_des[] = {
-	0x09,			/*  __u8  bLength; */
-	0x02,			/*  __u8  bDescriptorType; Configuration */
-	0x19,			/*  __u16 wTotalLength; */
-	0x00,
-	0x01,			/*  __u8  bNumInterfaces; */
-	0x01,			/*  __u8  bConfigurationValue; */
-	0x00,			/*  __u8  iConfiguration; */
-	0x40,			/*  __u8  bmAttributes;
-				   Bit 7: Bus-powered, 6: Self-powered, 5 Remote-wakwup, 4..0: resvd */
-	0x00,			/*  __u8  MaxPower; */
-
-	/* interface */
-	0x09,			/*  __u8  if_bLength; */
-	0x04,			/*  __u8  if_bDescriptorType; Interface */
-	0x00,			/*  __u8  if_bInterfaceNumber; */
-	0x00,			/*  __u8  if_bAlternateSetting; */
-	0x01,			/*  __u8  if_bNumEndpoints; */
-	0x09,			/*  __u8  if_bInterfaceClass; HUB_CLASSCODE */
-	0x00,			/*  __u8  if_bInterfaceSubClass; */
-	0x00,			/*  __u8  if_bInterfaceProtocol; */
-	0x00,			/*  __u8  if_iInterface; */
-
-	/* endpoint */
-	0x07,			/*  __u8  ep_bLength; */
-	0x05,			/*  __u8  ep_bDescriptorType; Endpoint */
-	0x81,			/*  __u8  ep_bEndpointAddress; IN Endpoint 1 */
-	0x03,			/*  __u8  ep_bmAttributes; Interrupt */
-	0x00,			/*  __u16 ep_wMaxPacketSize; ((MAX_ROOT_PORTS + 1) / 8 */
-	0x02,
-	0xff			/*  __u8  ep_bInterval; 255 ms */
-};
+#include <usbroothubdes.h>
 
-static const unsigned char root_hub_str_index0[] = {
-	0x04,			/*  __u8  bLength; */
-	0x03,			/*  __u8  bDescriptorType; String-descriptor */
-	0x09,			/*  __u8  lang ID */
-	0x04,			/*  __u8  lang ID */
-};
-
-static const unsigned char root_hub_str_index1[] = {
-	0x1c,			/*  __u8  bLength; */
-	0x03,			/*  __u8  bDescriptorType; String-descriptor */
-	'M',			/*  __u8  Unicode */
-	0,			/*  __u8  Unicode */
-	'U',			/*  __u8  Unicode */
-	0,			/*  __u8  Unicode */
-	'S',			/*  __u8  Unicode */
-	0,			/*  __u8  Unicode */
-	'B',			/*  __u8  Unicode */
-	0,			/*  __u8  Unicode */
-	' ',			/*  __u8  Unicode */
-	0,			/*  __u8  Unicode */
-	'R',			/*  __u8  Unicode */
-	0,			/*  __u8  Unicode */
-	'o',			/*  __u8  Unicode */
-	0,			/*  __u8  Unicode */
-	'o',			/*  __u8  Unicode */
-	0,			/*  __u8  Unicode */
-	't',			/*  __u8  Unicode */
-	0,			/*  __u8  Unicode */
-	' ',			/*  __u8  Unicode */
-	0,			/*  __u8  Unicode */
-	'H',			/*  __u8  Unicode */
-	0,			/*  __u8  Unicode */
-	'u',			/*  __u8  Unicode */
-	0,			/*  __u8  Unicode */
-	'b',			/*  __u8  Unicode */
-	0,			/*  __u8  Unicode */
-};
 #endif
 
 /*
@@ -1089,7 +998,7 @@ int submit_bulk_msg(struct usb_device *dev, unsigned long pipe,
 /*
  * This function initializes the usb controller module.
  */
-int usb_lowlevel_init(int index, void **controller)
+int usb_lowlevel_init(int index, enum usb_init_type init, void **controller)
 {
 	u8  power;
 	u32 timeout;
diff --git a/drivers/usb/musb/musb_udc.c b/drivers/usb/musb/musb_udc.c
index 3e3e05ecfd..87640f4e32 100644
--- a/drivers/usb/musb/musb_udc.c
+++ b/drivers/usb/musb/musb_udc.c
@@ -39,7 +39,8 @@
  */
 
 #include <common.h>
-#include <usb/musb_udc.h>
+#include <usbdevice.h>
+#include <usb/udc.h>
 #include "../gadget/ep0.h"
 #include "musb_core.h"
 #if defined(CONFIG_USB_OMAP3)
diff --git a/drivers/usb/phy/Makefile b/drivers/usb/phy/Makefile
index f93121a3aa..93d147e26f 100644
--- a/drivers/usb/phy/Makefile
+++ b/drivers/usb/phy/Makefile
@@ -5,26 +5,5 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	:= $(obj)libusb_phy.o
-
-COBJS-$(CONFIG_TWL4030_USB) += twl4030.o
-
-COBJS	:= $(COBJS-y)
-SRCS	:= $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-
-all:	$(LIB)
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-$(CONFIG_TWL4030_USB) += twl4030.o
+obj-$(CONFIG_OMAP_USB_PHY) += omap_usb_phy.o
diff --git a/drivers/usb/phy/omap_usb_phy.c b/drivers/usb/phy/omap_usb_phy.c
new file mode 100644
index 0000000000..af46db2edd
--- /dev/null
+++ b/drivers/usb/phy/omap_usb_phy.c
@@ -0,0 +1,261 @@
+/*
+ * OMAP USB PHY Support
+ *
+ * (C) Copyright 2013
+ * Texas Instruments, <www.ti.com>
+ *
+ * Author: Dan Murphy <dmurphy@ti.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <usb.h>
+#include <asm-generic/errno.h>
+#include <asm/omap_common.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/sys_proto.h>
+
+#include <linux/compat.h>
+#include <linux/usb/dwc3.h>
+#include <linux/usb/xhci-omap.h>
+
+#include "../host/xhci.h"
+
+#ifdef CONFIG_OMAP_USB3PHY1_HOST
+struct usb_dpll_params {
+	u16	m;
+	u8	n;
+	u8	freq:3;
+	u8	sd;
+	u32	mf;
+};
+
+#define	NUM_USB_CLKS		6
+
+static struct usb_dpll_params omap_usb3_dpll_params[NUM_USB_CLKS] = {
+	{1250, 5, 4, 20, 0},		/* 12 MHz */
+	{3125, 20, 4, 20, 0},		/* 16.8 MHz */
+	{1172, 8, 4, 20, 65537},	/* 19.2 MHz */
+	{1250, 12, 4, 20, 0},		/* 26 MHz */
+	{3125, 47, 4, 20, 92843},	/* 38.4 MHz */
+	{1000, 7, 4, 10, 0},        /* 20 MHz */
+};
+
+static void omap_usb_dpll_relock(struct omap_usb3_phy *phy_regs)
+{
+	u32 val;
+
+	writel(SET_PLL_GO, &phy_regs->pll_go);
+	do {
+		val = readl(&phy_regs->pll_status);
+			if (val & PLL_LOCK)
+				break;
+	} while (1);
+}
+
+static void omap_usb_dpll_lock(struct omap_usb3_phy *phy_regs)
+{
+	u32 clk_index = get_sys_clk_index();
+	u32 val;
+
+	val = readl(&phy_regs->pll_config_1);
+	val &= ~PLL_REGN_MASK;
+	val |= omap_usb3_dpll_params[clk_index].n << PLL_REGN_SHIFT;
+	writel(val, &phy_regs->pll_config_1);
+
+	val = readl(&phy_regs->pll_config_2);
+	val &= ~PLL_SELFREQDCO_MASK;
+	val |= omap_usb3_dpll_params[clk_index].freq << PLL_SELFREQDCO_SHIFT;
+	writel(val, &phy_regs->pll_config_2);
+
+	val = readl(&phy_regs->pll_config_1);
+	val &= ~PLL_REGM_MASK;
+	val |= omap_usb3_dpll_params[clk_index].m << PLL_REGM_SHIFT;
+	writel(val, &phy_regs->pll_config_1);
+
+	val = readl(&phy_regs->pll_config_4);
+	val &= ~PLL_REGM_F_MASK;
+	val |= omap_usb3_dpll_params[clk_index].mf << PLL_REGM_F_SHIFT;
+	writel(val, &phy_regs->pll_config_4);
+
+	val = readl(&phy_regs->pll_config_3);
+	val &= ~PLL_SD_MASK;
+	val |= omap_usb3_dpll_params[clk_index].sd << PLL_SD_SHIFT;
+	writel(val, &phy_regs->pll_config_3);
+
+	omap_usb_dpll_relock(phy_regs);
+}
+
+static void usb3_phy_partial_powerup(struct omap_usb3_phy *phy_regs)
+{
+	u32 rate = get_sys_clk_freq()/1000000;
+	u32 val;
+
+	val = readl((*ctrl)->control_phy_power_usb);
+	val &= ~(USB3_PWRCTL_CLK_CMD_MASK | USB3_PWRCTL_CLK_FREQ_MASK);
+	val |= (USB3_PHY_PARTIAL_RX_POWERON | USB3_PHY_TX_RX_POWERON);
+	val |= rate << USB3_PWRCTL_CLK_FREQ_SHIFT;
+
+	writel(val, (*ctrl)->control_phy_power_usb);
+}
+
+void usb_phy_power(int on)
+{
+	u32 val;
+
+	val = readl((*ctrl)->control_phy_power_usb);
+	if (on) {
+		val &= ~USB3_PWRCTL_CLK_CMD_MASK;
+		val |= USB3_PHY_TX_RX_POWERON;
+	} else {
+		val &= (~USB3_PWRCTL_CLK_CMD_MASK & ~USB3_PHY_TX_RX_POWERON);
+	}
+
+	writel(val, (*ctrl)->control_phy_power_usb);
+}
+
+void omap_usb3_phy_init(struct omap_usb3_phy *phy_regs)
+{
+	omap_usb_dpll_lock(phy_regs);
+
+	usb3_phy_partial_powerup(phy_regs);
+	/*
+	 * Give enough time for the PHY to partially power-up before
+	 * powering it up completely. delay value suggested by the HW
+	 * team.
+	 */
+	mdelay(100);
+	usb3_phy_power(1);
+}
+
+static void omap_enable_usb3_phy(struct omap_xhci *omap)
+{
+	u32	val;
+
+	/* Setting OCP2SCP1 register */
+	setbits_le32((*prcm)->cm_l3init_ocp2scp1_clkctrl,
+		     OCP2SCP1_CLKCTRL_MODULEMODE_HW);
+
+	/* Turn on 32K AON clk */
+	setbits_le32((*prcm)->cm_coreaon_usb_phy_core_clkctrl,
+		     USBPHY_CORE_CLKCTRL_OPTFCLKEN_CLK32K);
+
+	/* Setting CM_L3INIT_CLKSTCTRL to 0x0 i.e NO sleep */
+	writel(0x0, (*prcm)->cm_l3init_clkstctrl);
+
+	val = (USBOTGSS_DMADISABLE |
+			USBOTGSS_STANDBYMODE_SMRT_WKUP |
+			USBOTGSS_IDLEMODE_NOIDLE);
+	writel(val, &omap->otg_wrapper->sysconfig);
+
+	/* Clear the utmi OTG status */
+	val = readl(&omap->otg_wrapper->utmi_otg_status);
+	writel(val, &omap->otg_wrapper->utmi_otg_status);
+
+	/* Enable interrupts */
+	writel(USBOTGSS_COREIRQ_EN, &omap->otg_wrapper->irqenable_set_0);
+	val = (USBOTGSS_IRQ_SET_1_IDPULLUP_FALL_EN |
+			USBOTGSS_IRQ_SET_1_DISCHRGVBUS_FALL_EN |
+			USBOTGSS_IRQ_SET_1_CHRGVBUS_FALL_EN	|
+			USBOTGSS_IRQ_SET_1_DRVVBUS_FALL_EN	|
+			USBOTGSS_IRQ_SET_1_IDPULLUP_RISE_EN	|
+			USBOTGSS_IRQ_SET_1_DISCHRGVBUS_RISE_EN	|
+			USBOTGSS_IRQ_SET_1_CHRGVBUS_RISE_EN |
+			USBOTGSS_IRQ_SET_1_DRVVBUS_RISE_EN |
+			USBOTGSS_IRQ_SET_1_OEVT_EN);
+	writel(val, &omap->otg_wrapper->irqenable_set_1);
+
+	/* Clear the IRQ status */
+	val = readl(&omap->otg_wrapper->irqstatus_1);
+	writel(val, &omap->otg_wrapper->irqstatus_1);
+	val = readl(&omap->otg_wrapper->irqstatus_0);
+	writel(val, &omap->otg_wrapper->irqstatus_0);
+
+	/* Enable the USB OTG Super speed clocks */
+	val = (OPTFCLKEN_REFCLK960M | OTG_SS_CLKCTRL_MODULEMODE_HW);
+	setbits_le32((*prcm)->cm_l3init_usb_otg_ss_clkctrl, val);
+
+};
+#endif /* CONFIG_OMAP_USB3PHY1_HOST */
+
+#ifdef CONFIG_OMAP_USB2PHY2_HOST
+static void omap_enable_usb2_phy2(struct omap_xhci *omap)
+{
+	u32 reg, val;
+
+	val = (~USB2PHY_AUTORESUME_EN & USB2PHY_DISCHGDET);
+	writel(val, (*ctrl)->control_srcomp_north_side);
+
+	setbits_le32((*prcm)->cm_coreaon_usb_phy2_core_clkctrl,
+			USBPHY_CORE_CLKCTRL_OPTFCLKEN_CLK32K);
+
+	setbits_le32((*prcm)->cm_l3init_hsusbhost_clkctrl,
+					(USBPHY_CORE_CLKCTRL_OPTFCLKEN_CLK32K |
+					 OTG_SS_CLKCTRL_MODULEMODE_HW));
+
+	/* This is an undocumented Reserved register */
+	reg = 0x4a0086c0;
+	val = readl(reg);
+	val |= 0x100;
+	setbits_le32(reg, val);
+}
+
+void usb_phy_power(int on)
+{
+	return;
+}
+#endif /* CONFIG_OMAP_USB2PHY2_HOST */
+
+#ifdef CONFIG_AM437X_USB2PHY2_HOST
+static void am437x_enable_usb2_phy2(struct omap_xhci *omap)
+{
+	const u32 usb_otg_ss_clk_val = (USBOTGSSX_CLKCTRL_MODULE_EN |
+				USBOTGSSX_CLKCTRL_OPTFCLKEN_REFCLK960);
+
+	writel(usb_otg_ss_clk_val, PRM_PER_USB_OTG_SS0_CLKCTRL);
+	writel(usb_otg_ss_clk_val, PRM_PER_USB_OTG_SS1_CLKCTRL);
+
+	writel(USBPHYOCPSCP_MODULE_EN, PRM_PER_USBPHYOCP2SCP0_CLKCTRL);
+	writel(USBPHYOCPSCP_MODULE_EN, PRM_PER_USBPHYOCP2SCP1_CLKCTRL);
+}
+
+void usb_phy_power(int on)
+{
+	return;
+}
+#endif /* CONFIG_AM437X_USB2PHY2_HOST */
+
+void omap_reset_usb_phy(struct dwc3 *dwc3_reg)
+{
+	/* Assert USB3 PHY reset */
+	setbits_le32(&dwc3_reg->g_usb3pipectl[0], DWC3_GUSB3PIPECTL_PHYSOFTRST);
+
+	/* Assert USB2 PHY reset */
+	setbits_le32(&dwc3_reg->g_usb2phycfg, DWC3_GUSB2PHYCFG_PHYSOFTRST);
+
+	mdelay(100);
+
+	/* Clear USB3 PHY reset */
+	clrbits_le32(&dwc3_reg->g_usb3pipectl[0], DWC3_GUSB3PIPECTL_PHYSOFTRST);
+
+	/* Clear USB2 PHY reset */
+	clrbits_le32(&dwc3_reg->g_usb2phycfg, DWC3_GUSB2PHYCFG_PHYSOFTRST);
+
+}
+
+void omap_enable_phy(struct omap_xhci *omap)
+{
+#ifdef CONFIG_OMAP_USB2PHY2_HOST
+	omap_enable_usb2_phy2(omap);
+#endif
+
+#ifdef CONFIG_AM437X_USB2PHY2_HOST
+	am437x_enable_usb2_phy2(omap);
+#endif
+
+#ifdef CONFIG_OMAP_USB3PHY1_HOST
+	omap_enable_usb3_phy(omap);
+	omap_usb3_phy_init(omap->usb3_phy);
+#endif
+}
diff --git a/drivers/usb/ulpi/Makefile b/drivers/usb/ulpi/Makefile
index ba5a1ab5bf..a21fe2c936 100644
--- a/drivers/usb/ulpi/Makefile
+++ b/drivers/usb/ulpi/Makefile
@@ -4,28 +4,6 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	:= $(obj)libusb_ulpi.o
-
-COBJS-$(CONFIG_USB_ULPI)		+= ulpi.o
-COBJS-$(CONFIG_USB_ULPI_VIEWPORT)	+= ulpi-viewport.o
-COBJS-$(CONFIG_USB_ULPI_VIEWPORT_OMAP)	+= omap-ulpi-viewport.o
-
-COBJS	:= $(COBJS-y)
-SRCS	:= $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-
-all:	$(LIB)
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-$(CONFIG_USB_ULPI)		+= ulpi.o
+obj-$(CONFIG_USB_ULPI_VIEWPORT)	+= ulpi-viewport.o
+obj-$(CONFIG_USB_ULPI_VIEWPORT_OMAP)	+= omap-ulpi-viewport.o
diff --git a/drivers/video/Makefile b/drivers/video/Makefile
index 6c208c596e..c527029241 100644
--- a/drivers/video/Makefile
+++ b/drivers/video/Makefile
@@ -5,58 +5,38 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	:= $(obj)libvideo.o
-
-COBJS-$(CONFIG_ATI_RADEON_FB) += ati_radeon_fb.o videomodes.o
-COBJS-$(CONFIG_ATMEL_HLCD) += atmel_hlcdfb.o
-COBJS-$(CONFIG_ATMEL_LCD) += atmel_lcdfb.o
-COBJS-$(CONFIG_CFB_CONSOLE) += cfb_console.o
-COBJS-$(CONFIG_EXYNOS_DP) += exynos_dp.o exynos_dp_lowlevel.o
-COBJS-$(CONFIG_EXYNOS_FB) += exynos_fb.o exynos_fimd.o
-COBJS-$(CONFIG_EXYNOS_MIPI_DSIM) += exynos_mipi_dsi.o exynos_mipi_dsi_common.o \
+obj-$(CONFIG_ATI_RADEON_FB) += ati_radeon_fb.o videomodes.o
+obj-$(CONFIG_ATMEL_HLCD) += atmel_hlcdfb.o
+obj-$(CONFIG_ATMEL_LCD) += atmel_lcdfb.o
+obj-$(CONFIG_CFB_CONSOLE) += cfb_console.o
+obj-$(CONFIG_EXYNOS_DP) += exynos_dp.o exynos_dp_lowlevel.o
+obj-$(CONFIG_EXYNOS_FB) += exynos_fb.o exynos_fimd.o
+obj-$(CONFIG_EXYNOS_MIPI_DSIM) += exynos_mipi_dsi.o exynos_mipi_dsi_common.o \
 				exynos_mipi_dsi_lowlevel.o
-COBJS-$(CONFIG_EXYNOS_PWM_BL) += exynos_pwm_bl.o
-COBJS-$(CONFIG_FSL_DIU_FB) += fsl_diu_fb.o videomodes.o
-COBJS-$(CONFIG_L5F31188) += l5f31188.o
-COBJS-$(CONFIG_MPC8XX_LCD) += mpc8xx_lcd.o
-COBJS-$(CONFIG_PXA_LCD) += pxa_lcd.o
-COBJS-$(CONFIG_S6E8AX0) += s6e8ax0.o
-COBJS-$(CONFIG_S6E63D6) += s6e63d6.o
-COBJS-$(CONFIG_LD9040) += ld9040.o
-COBJS-$(CONFIG_SED156X) += sed156x.o
-COBJS-$(CONFIG_VIDEO_BCM2835) += bcm2835.o
-COBJS-$(CONFIG_VIDEO_COREBOOT) += coreboot_fb.o
-COBJS-$(CONFIG_VIDEO_CT69000) += ct69000.o videomodes.o
-COBJS-$(CONFIG_VIDEO_DA8XX) += da8xx-fb.o videomodes.o
-COBJS-$(CONFIG_VIDEO_MB862xx) += mb862xx.o videomodes.o
-COBJS-$(CONFIG_VIDEO_MB86R0xGDC) += mb86r0xgdc.o videomodes.o
-COBJS-$(CONFIG_VIDEO_MX3) += mx3fb.o videomodes.o
-COBJS-$(CONFIG_VIDEO_IPUV3) += mxc_ipuv3_fb.o ipu_common.o ipu_disp.o
-COBJS-$(CONFIG_VIDEO_MXS) += mxsfb.o videomodes.o
-COBJS-$(CONFIG_VIDEO_OMAP3) += omap3_dss.o
-COBJS-$(CONFIG_VIDEO_SED13806) += sed13806.o
-COBJS-$(CONFIG_VIDEO_SM501) += sm501.o
-COBJS-$(CONFIG_VIDEO_SMI_LYNXEM) += smiLynxEM.o videomodes.o
-COBJS-$(CONFIG_VIDEO_TEGRA) += tegra.o
-COBJS-$(CONFIG_VIDEO_VCXK) += bus_vcxk.o
-COBJS-$(CONFIG_FORMIKE) += formike.o
-
-COBJS	:= $(sort $(COBJS-y))
-SRCS	:= $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-
-all:	$(LIB)
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-$(CONFIG_EXYNOS_PWM_BL) += exynos_pwm_bl.o
+obj-$(CONFIG_FSL_DIU_FB) += fsl_diu_fb.o videomodes.o
+obj-$(CONFIG_L5F31188) += l5f31188.o
+obj-$(CONFIG_MPC8XX_LCD) += mpc8xx_lcd.o
+obj-$(CONFIG_PXA_LCD) += pxa_lcd.o
+obj-$(CONFIG_SCF0403_LCD) += scf0403_lcd.o
+obj-$(CONFIG_S6E8AX0) += s6e8ax0.o
+obj-$(CONFIG_S6E63D6) += s6e63d6.o
+obj-$(CONFIG_LD9040) += ld9040.o
+obj-$(CONFIG_SED156X) += sed156x.o
+obj-$(CONFIG_VIDEO_BCM2835) += bcm2835.o
+obj-$(CONFIG_VIDEO_COREBOOT) += coreboot_fb.o
+obj-$(CONFIG_VIDEO_CT69000) += ct69000.o videomodes.o
+obj-$(CONFIG_VIDEO_DA8XX) += da8xx-fb.o videomodes.o
+obj-$(CONFIG_VIDEO_MB862xx) += mb862xx.o videomodes.o
+obj-$(CONFIG_VIDEO_MB86R0xGDC) += mb86r0xgdc.o videomodes.o
+obj-$(CONFIG_VIDEO_MX3) += mx3fb.o videomodes.o
+obj-$(CONFIG_VIDEO_IPUV3) += mxc_ipuv3_fb.o ipu_common.o ipu_disp.o
+obj-$(CONFIG_VIDEO_MXS) += mxsfb.o videomodes.o
+obj-$(CONFIG_VIDEO_OMAP3) += omap3_dss.o
+obj-$(CONFIG_VIDEO_SANDBOX_SDL) += sandbox_sdl.o
+obj-$(CONFIG_VIDEO_SED13806) += sed13806.o
+obj-$(CONFIG_VIDEO_SM501) += sm501.o
+obj-$(CONFIG_VIDEO_SMI_LYNXEM) += smiLynxEM.o videomodes.o
+obj-$(CONFIG_VIDEO_TEGRA) += tegra.o
+obj-$(CONFIG_VIDEO_VCXK) += bus_vcxk.o
+obj-$(CONFIG_FORMIKE) += formike.o
diff --git a/drivers/video/bcm2835.c b/drivers/video/bcm2835.c
index 58a616317a..1f18231ac6 100644
--- a/drivers/video/bcm2835.c
+++ b/drivers/video/bcm2835.c
@@ -14,6 +14,8 @@ DECLARE_GLOBAL_DATA_PTR;
 /* Global variables that lcd.c expects to exist */
 vidinfo_t panel_info;
 
+static u32 bcm2835_pitch;
+
 struct msg_query {
 	struct bcm2835_mbox_hdr hdr;
 	struct bcm2835_mbox_tag_physical_w_h physical_w_h;
@@ -30,6 +32,7 @@ struct msg_setup {
 	struct bcm2835_mbox_tag_virtual_offset virtual_offset;
 	struct bcm2835_mbox_tag_overscan overscan;
 	struct bcm2835_mbox_tag_allocate_buffer allocate_buffer;
+	struct bcm2835_mbox_tag_pitch pitch;
 	u32 end_tag;
 };
 
@@ -80,6 +83,7 @@ void lcd_ctrl_init(void *lcdbase)
 	msg_setup->overscan.body.req.right = 0;
 	BCM2835_MBOX_INIT_TAG(&msg_setup->allocate_buffer, ALLOCATE_BUFFER);
 	msg_setup->allocate_buffer.body.req.alignment = 0x100;
+	BCM2835_MBOX_INIT_TAG_NO_REQ(&msg_setup->pitch, GET_PITCH);
 
 	ret = bcm2835_mbox_call_prop(BCM2835_MBOX_PROP_CHAN, &msg_setup->hdr);
 	if (ret) {
@@ -90,6 +94,7 @@ void lcd_ctrl_init(void *lcdbase)
 
 	w = msg_setup->physical_w_h.body.resp.width;
 	h = msg_setup->physical_w_h.body.resp.height;
+	bcm2835_pitch = msg_setup->pitch.body.resp.pitch;
 
 	debug("bcm2835: Final resolution is %d x %d\n", w, h);
 
@@ -103,3 +108,9 @@ void lcd_ctrl_init(void *lcdbase)
 void lcd_enable(void)
 {
 }
+
+int lcd_get_size(int *line_length)
+{
+	*line_length = bcm2835_pitch;
+	return *line_length * panel_info.vl_row;
+}
diff --git a/drivers/video/bus_vcxk.c b/drivers/video/bus_vcxk.c
index 0138bca05e..60a5cc5b71 100644
--- a/drivers/video/bus_vcxk.c
+++ b/drivers/video/bus_vcxk.c
@@ -20,7 +20,6 @@ vu_long  *vcxk_bws_long = ((vu_long *) (CONFIG_SYS_VCXK_BASE));
 	#ifndef VCBITMASK
 		#define VCBITMASK(bitno)	(0x0001 << (bitno % 16))
 	#endif
-#ifndef CONFIG_AT91_LEGACY
 at91_pio_t *pio = (at91_pio_t *) AT91_PIO_BASE;
 #define VCXK_INIT_PIN(PORT, PIN, DDR, I0O1) \
 	do { \
@@ -37,20 +36,6 @@ at91_pio_t *pio = (at91_pio_t *) AT91_PIO_BASE;
 #define VCXK_ACKNOWLEDGE	\
 	(!(readl(&pio->CONFIG_SYS_VCXK_ACKNOWLEDGE_PORT.pdsr) & \
 			CONFIG_SYS_VCXK_ACKNOWLEDGE_PIN))
-#else
-	#define VCXK_INIT_PIN(PORT, PIN, DDR, I0O1) \
-		((AT91PS_PIO) PORT)->PIO_PER = PIN; \
-		((AT91PS_PIO) PORT)->DDR = PIN; \
-		((AT91PS_PIO) PORT)->PIO_MDDR = PIN; \
-		if (!I0O1) ((AT91PS_PIO) PORT)->PIO_PPUER = PIN;
-
-	#define VCXK_SET_PIN(PORT, PIN)	((AT91PS_PIO) PORT)->PIO_SODR  = PIN;
-	#define VCXK_CLR_PIN(PORT, PIN)	((AT91PS_PIO) PORT)->PIO_CODR  = PIN;
-
-	#define VCXK_ACKNOWLEDGE	\
-		(!(((AT91PS_PIO) CONFIG_SYS_VCXK_ACKNOWLEDGE_PORT)->\
-			PIO_PDSR & CONFIG_SYS_VCXK_ACKNOWLEDGE_PIN))
-#endif
 #elif defined(CONFIG_MCF52x2)
 	#include <asm/m5282.h>
 	#ifndef VCBITMASK
diff --git a/drivers/video/cfb_console.c b/drivers/video/cfb_console.c
index a2946c71f6..b52e9edd25 100644
--- a/drivers/video/cfb_console.c
+++ b/drivers/video/cfb_console.c
@@ -1473,7 +1473,11 @@ int video_display_bitmap(ulong bmp_image, int x, int y)
 			printf("Error: malloc in gunzip failed!\n");
 			return 1;
 		}
-		if (gunzip(dst, CONFIG_SYS_VIDEO_LOGO_MAX_SIZE,
+		/*
+		 * NB: we need to force offset of +2
+		 * See doc/README.displaying-bmps
+		 */
+		if (gunzip(dst+2, CONFIG_SYS_VIDEO_LOGO_MAX_SIZE-2,
 			   (uchar *) bmp_image,
 			   &len) != 0) {
 			printf("Error: no valid bmp or bmp.gz image at %lx\n",
@@ -1489,7 +1493,7 @@ int video_display_bitmap(ulong bmp_image, int x, int y)
 		/*
 		 * Set addr to decompressed image
 		 */
-		bmp = (bmp_image_t *) dst;
+		bmp = (bmp_image_t *)(dst+2);
 
 		if (!((bmp->header.signature[0] == 'B') &&
 		      (bmp->header.signature[1] == 'M'))) {
@@ -2108,6 +2112,24 @@ defined(CONFIG_SANDBOX) || defined(CONFIG_X86)
 	return 0;
 }
 
+void video_clear(void)
+{
+	if (!video_fb_address)
+		return;
+#ifdef VIDEO_HW_RECTFILL
+	video_hw_rectfill(VIDEO_PIXEL_SIZE,	/* bytes per pixel */
+			  0,			/* dest pos x */
+			  0,			/* dest pos y */
+			  VIDEO_VISIBLE_COLS,	/* frame width */
+			  VIDEO_VISIBLE_ROWS,	/* frame height */
+			  bgx			/* fill color */
+	);
+#else
+	memsetl(video_fb_address,
+		(VIDEO_VISIBLE_ROWS * VIDEO_LINE_LEN) / sizeof(int), bgx);
+#endif
+}
+
 static int video_init(void)
 {
 	unsigned char color8;
@@ -2194,6 +2216,8 @@ static int video_init(void)
 	}
 	eorx = fgx ^ bgx;
 
+	video_clear();
+
 #ifdef CONFIG_VIDEO_LOGO
 	/* Plot the logo and get start point of console */
 	debug("Video: Drawing the logo ...\n");
@@ -2297,21 +2321,3 @@ int video_get_screen_columns(void)
 {
 	return CONSOLE_COLS;
 }
-
-void video_clear(void)
-{
-	if (!video_fb_address)
-		return;
-#ifdef VIDEO_HW_RECTFILL
-	video_hw_rectfill(VIDEO_PIXEL_SIZE,	/* bytes per pixel */
-			  0,			/* dest pos x */
-			  0,			/* dest pos y */
-			  VIDEO_VISIBLE_COLS,	/* frame width */
-			  VIDEO_VISIBLE_ROWS,	/* frame height */
-			  bgx			/* fill color */
-	);
-#else
-	memsetl(video_fb_address,
-		(VIDEO_VISIBLE_ROWS * VIDEO_LINE_LEN) / sizeof(int), bgx);
-#endif
-}
diff --git a/drivers/video/exynos_fb.c b/drivers/video/exynos_fb.c
index 7d4c6e092d..e1e0d802f6 100644
--- a/drivers/video/exynos_fb.c
+++ b/drivers/video/exynos_fb.c
@@ -62,31 +62,6 @@ static void exynos_lcd_init(vidinfo_t *vid)
 	lcd_set_flush_dcache(1);
 }
 
-#ifdef CONFIG_CMD_BMP
-static void draw_logo(void)
-{
-	int x, y;
-	ulong addr;
-
-	if (panel_width >= panel_info.logo_width) {
-		x = ((panel_width - panel_info.logo_width) >> 1);
-	} else {
-		x = 0;
-		printf("Warning: image width is bigger than display width\n");
-	}
-
-	if (panel_height >= panel_info.logo_height) {
-		y = ((panel_height - panel_info.logo_height) >> 1) - 4;
-	} else {
-		y = 0;
-		printf("Warning: image height is bigger than display height\n");
-	}
-
-	addr = panel_info.logo_addr;
-	bmp_display(addr, x, y);
-}
-#endif
-
 void __exynos_cfg_lcd_gpio(void)
 {
 }
@@ -129,6 +104,13 @@ void __exynos_backlight_reset(void)
 void exynos_backlight_reset(void)
 	__attribute__((weak, alias("__exynos_backlight_reset")));
 
+int __exynos_lcd_misc_init(vidinfo_t *vid)
+{
+	return 0;
+}
+int exynos_lcd_misc_init(vidinfo_t *vid)
+	__attribute__((weak, alias("__exynos_lcd_misc_init")));
+
 static void lcd_panel_on(vidinfo_t *vid)
 {
 	udelay(vid->init_delay);
@@ -306,10 +288,15 @@ void lcd_ctrl_init(void *lcdbase)
 #ifdef CONFIG_OF_CONTROL
 	if (exynos_fimd_parse_dt(gd->fdt_blob))
 		debug("Can't get proper panel info\n");
+#ifdef CONFIG_EXYNOS_MIPI_DSIM
+	exynos_init_dsim_platform_data(&panel_info);
+#endif
+	exynos_lcd_misc_init(&panel_info);
 #else
 	/* initialize parameters which is specific to panel. */
 	init_panel_info(&panel_info);
 #endif
+
 	panel_width = panel_info.vl_width;
 	panel_height = panel_info.vl_height;
 
@@ -323,9 +310,6 @@ void lcd_enable(void)
 	if (panel_info.logo_on) {
 		memset((void *) gd->fb_base, 0, panel_width * panel_height *
 				(NBITS(panel_info.vl_bpix) >> 3));
-#ifdef CONFIG_CMD_BMP
-		draw_logo();
-#endif
 	}
 
 	lcd_panel_on(&panel_info);
diff --git a/drivers/video/exynos_fimd.c b/drivers/video/exynos_fimd.c
index f962c4f0a6..cebbba7581 100644
--- a/drivers/video/exynos_fimd.c
+++ b/drivers/video/exynos_fimd.c
@@ -73,18 +73,19 @@ static void exynos_fimd_set_par(unsigned int win_id)
 	/* DATAPATH is DMA */
 	cfg |= EXYNOS_WINCON_DATAPATH_DMA;
 
-	if (pvid->logo_on) /* To get proprietary LOGO */
-		cfg |= EXYNOS_WINCON_WSWP_ENABLE;
-	else /* To get output console on LCD */
-		cfg |= EXYNOS_WINCON_HAWSWP_ENABLE;
+	cfg |= EXYNOS_WINCON_HAWSWP_ENABLE;
 
 	/* dma burst is 16 */
 	cfg |= EXYNOS_WINCON_BURSTLEN_16WORD;
 
-	if (pvid->logo_on) /* To get proprietary LOGO */
-		cfg |= EXYNOS_WINCON_BPPMODE_24BPP_888;
-	else /* To get output console on LCD */
+	switch (pvid->vl_bpix) {
+	case 4:
 		cfg |= EXYNOS_WINCON_BPPMODE_16BPP_565;
+		break;
+	default:
+		cfg |= EXYNOS_WINCON_BPPMODE_24BPP_888;
+		break;
+	}
 
 	writel(cfg, (unsigned int)&fimd_ctrl->wincon0 +
 			EXYNOS_WINCON(win_id));
diff --git a/drivers/video/exynos_mipi_dsi.c b/drivers/video/exynos_mipi_dsi.c
index 8bb8feaa9c..7dd4652931 100644
--- a/drivers/video/exynos_mipi_dsi.c
+++ b/drivers/video/exynos_mipi_dsi.c
@@ -9,6 +9,8 @@
 
 #include <common.h>
 #include <malloc.h>
+#include <fdtdec.h>
+#include <libfdt.h>
 #include <linux/err.h>
 #include <asm/arch/dsim.h>
 #include <asm/arch/mipi_dsim.h>
@@ -22,7 +24,14 @@
 #define master_to_driver(a)	(a->dsim_lcd_drv)
 #define master_to_device(a)	(a->dsim_lcd_dev)
 
+DECLARE_GLOBAL_DATA_PTR;
+
 static struct exynos_platform_mipi_dsim *dsim_pd;
+#ifdef CONFIG_OF_CONTROL
+static struct mipi_dsim_config dsim_config_dt;
+static struct exynos_platform_mipi_dsim dsim_platform_data_dt;
+static struct mipi_dsim_lcd_device mipi_lcd_device_dt;
+#endif
 
 struct mipi_dsim_ddi {
 	int				bus_id;
@@ -238,3 +247,90 @@ void exynos_set_dsim_platform_data(struct exynos_platform_mipi_dsim *pd)
 
 	dsim_pd = pd;
 }
+
+#ifdef CONFIG_OF_CONTROL
+int exynos_dsim_config_parse_dt(const void *blob)
+{
+	int node;
+
+	node = fdtdec_next_compatible(blob, 0, COMPAT_SAMSUNG_EXYNOS_MIPI_DSI);
+	if (node <= 0) {
+		printf("exynos_mipi_dsi: Can't get device node for mipi dsi\n");
+		return -ENODEV;
+	}
+
+	dsim_config_dt.e_interface = fdtdec_get_int(blob, node,
+				"samsung,dsim-config-e-interface", 0);
+
+	dsim_config_dt.e_virtual_ch = fdtdec_get_int(blob, node,
+				"samsung,dsim-config-e-virtual-ch", 0);
+
+	dsim_config_dt.e_pixel_format = fdtdec_get_int(blob, node,
+				"samsung,dsim-config-e-pixel-format", 0);
+
+	dsim_config_dt.e_burst_mode = fdtdec_get_int(blob, node,
+				"samsung,dsim-config-e-burst-mode", 0);
+
+	dsim_config_dt.e_no_data_lane = fdtdec_get_int(blob, node,
+				"samsung,dsim-config-e-no-data-lane", 0);
+
+	dsim_config_dt.e_byte_clk = fdtdec_get_int(blob, node,
+				"samsung,dsim-config-e-byte-clk", 0);
+
+	dsim_config_dt.hfp = fdtdec_get_int(blob, node,
+				"samsung,dsim-config-hfp", 0);
+
+	dsim_config_dt.p = fdtdec_get_int(blob, node,
+					  "samsung,dsim-config-p", 0);
+	dsim_config_dt.m = fdtdec_get_int(blob, node,
+					  "samsung,dsim-config-m", 0);
+	dsim_config_dt.s = fdtdec_get_int(blob, node,
+					  "samsung,dsim-config-s", 0);
+
+	dsim_config_dt.pll_stable_time = fdtdec_get_int(blob, node,
+				"samsung,dsim-config-pll-stable-time", 0);
+
+	dsim_config_dt.esc_clk = fdtdec_get_int(blob, node,
+				"samsung,dsim-config-esc-clk", 0);
+
+	dsim_config_dt.stop_holding_cnt = fdtdec_get_int(blob, node,
+				"samsung,dsim-config-stop-holding-cnt", 0);
+
+	dsim_config_dt.bta_timeout = fdtdec_get_int(blob, node,
+				"samsung,dsim-config-bta-timeout", 0);
+
+	dsim_config_dt.rx_timeout = fdtdec_get_int(blob, node,
+				"samsung,dsim-config-rx-timeout", 0);
+
+	mipi_lcd_device_dt.name = fdtdec_get_config_string(blob,
+				"samsung,dsim-device-name");
+
+	mipi_lcd_device_dt.id = fdtdec_get_int(blob, node,
+				"samsung,dsim-device-id", 0);
+
+	mipi_lcd_device_dt.bus_id = fdtdec_get_int(blob, node,
+				"samsung,dsim-device-bus_id", 0);
+
+	mipi_lcd_device_dt.reverse_panel = fdtdec_get_int(blob, node,
+				"samsung,dsim-device-reverse-panel", 0);
+
+	return 0;
+}
+
+void exynos_init_dsim_platform_data(vidinfo_t *vid)
+{
+	if (exynos_dsim_config_parse_dt(gd->fdt_blob))
+		debug("Can't get proper dsim config.\n");
+
+	strcpy(dsim_platform_data_dt.lcd_panel_name, mipi_lcd_device_dt.name);
+	dsim_platform_data_dt.dsim_config = &dsim_config_dt;
+	dsim_platform_data_dt.mipi_power = mipi_power;
+	dsim_platform_data_dt.phy_enable = set_mipi_phy_ctrl;
+	dsim_platform_data_dt.lcd_panel_info = (void *)vid;
+
+	mipi_lcd_device_dt.platform_data = (void *)&dsim_platform_data_dt;
+	exynos_mipi_dsi_register_lcd_device(&mipi_lcd_device_dt);
+
+	dsim_pd = &dsim_platform_data_dt;
+}
+#endif
diff --git a/drivers/video/formike.c b/drivers/video/formike.c
index b9b6822138..138315843f 100644
--- a/drivers/video/formike.c
+++ b/drivers/video/formike.c
@@ -27,10 +27,11 @@ static int spi_write_tag_val(struct spi_slave *spi, unsigned char tag,
 	int ret;
 
 	buf[0] = tag;
-	buf[1] = val;
-	flags |= SPI_XFER_END;
+	ret = spi_xfer(spi, 8, buf, NULL, flags);
+	buf[0] = val;
+	flags = SPI_XFER_END;
+	ret = spi_xfer(spi, 8, buf, NULL, flags);
 
-	ret = spi_xfer(spi, 16, buf, NULL, flags);
 #ifdef KWH043ST20_F01_SPI_DEBUG
 	printf("spi_write_tag_val: tag=%02X, val=%02X ret: %d\n",
 	       tag, val, ret);
diff --git a/drivers/video/ipu_disp.c b/drivers/video/ipu_disp.c
index 2e913561d0..cefd2dc14a 100644
--- a/drivers/video/ipu_disp.c
+++ b/drivers/video/ipu_disp.c
@@ -889,7 +889,7 @@ int32_t ipu_init_sync_panel(int disp, uint32_t pixel_clk,
 	debug("panel size = %d x %d\n", width, height);
 
 	if ((v_sync_width == 0) || (h_sync_width == 0))
-		return EINVAL;
+		return -EINVAL;
 
 	adapt_panel_to_ipu_restricitions(&pixel_clk, width, height,
 					 h_start_width, h_end_width,
@@ -1178,7 +1178,7 @@ int32_t ipu_init_sync_panel(int disp, uint32_t pixel_clk,
 		if (sig.Vsync_pol)
 			di_gen |= DI_GEN_POLARITY_3;
 
-		if (sig.clk_pol)
+		if (!sig.clk_pol)
 			di_gen |= DI_GEN_POL_CLK;
 
 	}
diff --git a/drivers/video/ipu_regs.h b/drivers/video/ipu_regs.h
index 73e57ea999..21e9c99e0e 100644
--- a/drivers/video/ipu_regs.h
+++ b/drivers/video/ipu_regs.h
@@ -171,7 +171,7 @@ struct ipu_cm {
 	u32 gpr;
 	u32 reserved0[26];
 	u32 ch_db_mode_sel[2];
-	u32 reserved1[16];
+	u32 reserved1[4];
 	u32 alt_ch_db_mode_sel[2];
 	u32 reserved2[2];
 	u32 ch_trb_mode_sel[2];
@@ -188,7 +188,7 @@ struct ipu_idmac {
 	u32 sub_addr[5];
 	u32 bndm_en[2];
 	u32 sc_cord[2];
-	u32 reserved[45];
+	u32 reserved[44];
 	u32 ch_busy[2];
 };
 
diff --git a/drivers/video/sandbox_sdl.c b/drivers/video/sandbox_sdl.c
new file mode 100644
index 0000000000..ba4578e9d1
--- /dev/null
+++ b/drivers/video/sandbox_sdl.c
@@ -0,0 +1,79 @@
+/*
+ * Copyright (c) 2013 Google, Inc
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <fdtdec.h>
+#include <lcd.h>
+#include <malloc.h>
+#include <asm/sdl.h>
+#include <asm/u-boot-sandbox.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+enum {
+	/* Maximum LCD size we support */
+	LCD_MAX_WIDTH		= 1366,
+	LCD_MAX_HEIGHT		= 768,
+	LCD_MAX_LOG2_BPP	= 4,		/* 2^4 = 16 bpp */
+};
+
+vidinfo_t panel_info;
+
+void lcd_setcolreg(ushort regno, ushort red, ushort green, ushort blue)
+{
+}
+
+void lcd_ctrl_init(void *lcdbase)
+{
+	/*
+	 * Allocate memory to keep BMP color conversion map. This is required
+	 * for 8 bit BMPs only (hence 256 colors). If malloc fails - keep
+	 * going, it is not even clear if displyaing the bitmap will be
+	 * required on the way up.
+	 */
+	panel_info.cmap = malloc(256 * NBITS(panel_info.vl_bpix) / 8);
+}
+
+void lcd_enable(void)
+{
+	if (sandbox_sdl_init_display(panel_info.vl_col, panel_info.vl_row,
+				     panel_info.vl_bpix))
+		puts("LCD init failed\n");
+}
+
+int sandbox_lcd_sdl_early_init(void)
+{
+	const void *blob = gd->fdt_blob;
+	int xres = LCD_MAX_WIDTH, yres = LCD_MAX_HEIGHT;
+	int node;
+	int ret = 0;
+
+	/*
+	 * The code in common/lcd.c does not cope with not being able to
+	 * set up a frame buffer. It will just happily keep writing to
+	 * invalid memory. So here we make sure that at least some buffer
+	 * is available even if it actually won't be displayed.
+	 */
+	node = fdtdec_next_compatible(blob, 0, COMPAT_SANDBOX_LCD_SDL);
+	if (node >= 0) {
+		xres = fdtdec_get_int(blob, node, "xres", LCD_MAX_WIDTH);
+		yres = fdtdec_get_int(blob, node, "yres", LCD_MAX_HEIGHT);
+		if (xres < 0 || xres > LCD_MAX_WIDTH) {
+			xres = LCD_MAX_WIDTH;
+			ret = -EINVAL;
+		}
+		if (yres < 0 || yres > LCD_MAX_HEIGHT) {
+			yres = LCD_MAX_HEIGHT;
+			ret = -EINVAL;
+		}
+	}
+
+	panel_info.vl_col = xres;
+	panel_info.vl_row = yres;
+	panel_info.vl_bpix = LCD_COLOR16;
+
+	return ret;
+}
diff --git a/drivers/video/scf0403_lcd.c b/drivers/video/scf0403_lcd.c
new file mode 100644
index 0000000000..2bc8bcae8a
--- /dev/null
+++ b/drivers/video/scf0403_lcd.c
@@ -0,0 +1,296 @@
+/*
+ * scf0403.c -- support for DataImage SCF0403 LCD
+ *
+ * Copyright (c) 2013 Adapted from Linux driver:
+ * Copyright (c) 2012 Anders Electronics plc. All Rights Reserved.
+ * Copyright (c) 2012 CompuLab, Ltd
+ *           Dmitry Lifshitz <lifshitz@compulab.co.il>
+ *           Ilya Ledvich <ilya@compulab.co.il>
+ * Inspired by Alberto Panizzo <maramaopercheseimorto@gmail.com> &
+ *	Marek Vasut work in l4f00242t03.c
+ *
+ * U-Boot port: Nikita Kiryanov <nikita@compulab.co.il>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/gpio.h>
+#include <spi.h>
+
+struct scf0403_cmd {
+	u16 cmd;
+	u16 *params;
+	int count;
+};
+
+struct scf0403_initseq_entry {
+	struct scf0403_cmd cmd;
+	int delay_ms;
+};
+
+struct scf0403_priv {
+	struct spi_slave *spi;
+	unsigned int reset_gpio;
+	u32 rddid;
+	struct scf0403_initseq_entry *init_seq;
+	int seq_size;
+};
+
+struct scf0403_priv priv;
+
+#define SCF0403852GGU04_ID 0x000080
+
+/* SCF0403526GGU20 model commands parameters */
+static u16 extcmd_params_sn20[]		= {0xff, 0x98, 0x06};
+static u16 spiinttype_params_sn20[]	= {0x60};
+static u16 bc_params_sn20[]		= {
+		0x01, 0x10, 0x61, 0x74, 0x01, 0x01, 0x1B,
+		0x12, 0x71, 0x00, 0x00, 0x00, 0x01, 0x01,
+		0x05, 0x00, 0xFF, 0xF2, 0x01, 0x00, 0x40,
+};
+static u16 bd_params_sn20[] = {0x01, 0x23, 0x45, 0x67, 0x01, 0x23, 0x45, 0x67};
+static u16 be_params_sn20[] = {
+		0x01, 0x22, 0x22, 0xBA, 0xDC, 0x26, 0x28, 0x22,	0x22,
+};
+static u16 vcom_params_sn20[]		= {0x74};
+static u16 vmesur_params_sn20[]		= {0x7F, 0x0F, 0x00};
+static u16 powerctl_params_sn20[]	= {0x03, 0x0b, 0x00};
+static u16 lvglvolt_params_sn20[]	= {0x08};
+static u16 engsetting_params_sn20[]	= {0x00, 0x00, 0x00, 0x00, 0x00, 0x20};
+static u16 dispfunc_params_sn20[]	= {0xa0};
+static u16 dvddvolt_params_sn20[]	= {0x74};
+static u16 dispinv_params_sn20[]	= {0x00, 0x00, 0x00};
+static u16 panelres_params_sn20[]	= {0x82};
+static u16 framerate_params_sn20[]	= {0x00, 0x13, 0x13};
+static u16 timing_params_sn20[]		= {0x80, 0x05, 0x40, 0x28};
+static u16 powerctl2_params_sn20[]	= {0x17, 0x75, 0x79, 0x20};
+static u16 memaccess_params_sn20[]	= {0x00};
+static u16 pixfmt_params_sn20[]		= {0x66};
+static u16 pgamma_params_sn20[]		= {
+		0x00, 0x03, 0x0b, 0x0c, 0x0e, 0x08, 0xc5, 0x04,
+		0x08, 0x0c, 0x13, 0x11, 0x11, 0x14, 0x0c, 0x10,
+};
+static u16 ngamma_params_sn20[] = {
+		0x00, 0x0d, 0x11, 0x0c, 0x0c, 0x04, 0x76, 0x03,
+		0x08, 0x0b, 0x16, 0x10, 0x0d, 0x16, 0x0a, 0x00,
+};
+static u16 tearing_params_sn20[] = {0x00};
+
+/* SCF0403852GGU04 model commands parameters */
+static u16 memaccess_params_sn04[]	= {0x08};
+static u16 pixfmt_params_sn04[]		= {0x66};
+static u16 modectl_params_sn04[]	= {0x01};
+static u16 dispfunc_params_sn04[]	= {0x22, 0xe2, 0xFF, 0x04};
+static u16 vcom_params_sn04[]		= {0x00, 0x6A};
+static u16 pgamma_params_sn04[]		= {
+		0x00, 0x07, 0x0d, 0x10, 0x13, 0x19, 0x0f, 0x0c,
+		0x05, 0x08, 0x06, 0x13,	0x0f, 0x30, 0x20, 0x1f,
+};
+static u16 ngamma_params_sn04[]		= {
+		0x1F, 0x20, 0x30, 0x0F, 0x13, 0x06, 0x08, 0x05,
+		0x0C, 0x0F, 0x19, 0x13, 0x10, 0x0D, 0x07, 0x00,
+};
+static u16 dispinv_params_sn04[]	= {0x02};
+
+/* Common commands */
+static struct scf0403_cmd scf0403_cmd_slpout	= {0x11, NULL, 0};
+static struct scf0403_cmd scf0403_cmd_dison	= {0x29, NULL, 0};
+
+/* SCF0403852GGU04 init sequence */
+static struct scf0403_initseq_entry scf0403_initseq_sn04[] = {
+	{{0x36, memaccess_params_sn04,	ARRAY_SIZE(memaccess_params_sn04)}, 0},
+	{{0x3A, pixfmt_params_sn04,	ARRAY_SIZE(pixfmt_params_sn04)}, 0},
+	{{0xB6, dispfunc_params_sn04,	ARRAY_SIZE(dispfunc_params_sn04)}, 0},
+	{{0xC5, vcom_params_sn04,	ARRAY_SIZE(vcom_params_sn04)}, 0},
+	{{0xE0, pgamma_params_sn04,	ARRAY_SIZE(pgamma_params_sn04)}, 0},
+	{{0xE1, ngamma_params_sn04,	ARRAY_SIZE(ngamma_params_sn04)}, 20},
+	{{0xB0, modectl_params_sn04,	ARRAY_SIZE(modectl_params_sn04)}, 0},
+	{{0xB4, dispinv_params_sn04,	ARRAY_SIZE(dispinv_params_sn04)}, 100},
+};
+
+/* SCF0403526GGU20 init sequence */
+static struct scf0403_initseq_entry scf0403_initseq_sn20[] = {
+	{{0xff, extcmd_params_sn20,	ARRAY_SIZE(extcmd_params_sn20)}, 0},
+	{{0xba, spiinttype_params_sn20,	ARRAY_SIZE(spiinttype_params_sn20)}, 0},
+	{{0xbc, bc_params_sn20,		ARRAY_SIZE(bc_params_sn20)}, 0},
+	{{0xbd, bd_params_sn20,		ARRAY_SIZE(bd_params_sn20)}, 0},
+	{{0xbe, be_params_sn20,		ARRAY_SIZE(be_params_sn20)}, 0},
+	{{0xc7, vcom_params_sn20,	ARRAY_SIZE(vcom_params_sn20)}, 0},
+	{{0xed, vmesur_params_sn20,	ARRAY_SIZE(vmesur_params_sn20)}, 0},
+	{{0xc0, powerctl_params_sn20,	ARRAY_SIZE(powerctl_params_sn20)}, 0},
+	{{0xfc, lvglvolt_params_sn20,	ARRAY_SIZE(lvglvolt_params_sn20)}, 0},
+	{{0xb6, dispfunc_params_sn20,	ARRAY_SIZE(dispfunc_params_sn20)}, 0},
+	{{0xdf, engsetting_params_sn20,	ARRAY_SIZE(engsetting_params_sn20)}, 0},
+	{{0xf3, dvddvolt_params_sn20,	ARRAY_SIZE(dvddvolt_params_sn20)}, 0},
+	{{0xb4, dispinv_params_sn20,	ARRAY_SIZE(dispinv_params_sn20)}, 0},
+	{{0xf7, panelres_params_sn20,	ARRAY_SIZE(panelres_params_sn20)}, 0},
+	{{0xb1, framerate_params_sn20,	ARRAY_SIZE(framerate_params_sn20)}, 0},
+	{{0xf2, timing_params_sn20,	ARRAY_SIZE(timing_params_sn20)}, 0},
+	{{0xc1, powerctl2_params_sn20,	ARRAY_SIZE(powerctl2_params_sn20)}, 0},
+	{{0x36, memaccess_params_sn20,	ARRAY_SIZE(memaccess_params_sn20)}, 0},
+	{{0x3a, pixfmt_params_sn20,	ARRAY_SIZE(pixfmt_params_sn20)}, 0},
+	{{0xe0, pgamma_params_sn20,	ARRAY_SIZE(pgamma_params_sn20)}, 0},
+	{{0xe1, ngamma_params_sn20,	ARRAY_SIZE(ngamma_params_sn20)}, 0},
+	{{0x35, tearing_params_sn20,	ARRAY_SIZE(tearing_params_sn20)}, 0},
+};
+
+static void scf0403_gpio_reset(unsigned int gpio)
+{
+	if (!gpio_is_valid(gpio))
+		return;
+
+	gpio_set_value(gpio, 1);
+	mdelay(100);
+	gpio_set_value(gpio, 0);
+	mdelay(40);
+	gpio_set_value(gpio, 1);
+	mdelay(100);
+}
+
+static int scf0403_spi_read_rddid(struct spi_slave *spi, u32 *rddid)
+{
+	int error = 0;
+	u8 ids_buf = 0x00;
+	u16 dummy_buf = 0x00;
+	u16 cmd = 0x04;
+
+	error = spi_set_wordlen(spi, 9);
+	if (error)
+		return error;
+
+	/* Here 9 bits required to transmit a command */
+	error = spi_xfer(spi, 9, &cmd, NULL, SPI_XFER_ONCE);
+	if (error)
+		return error;
+
+	/*
+	 * Here 8 + 1 bits required to arrange extra clock cycle
+	 * before the first data bit.
+	 * According to the datasheet - first parameter is the dummy data.
+	 */
+	error = spi_xfer(spi, 9, NULL, &dummy_buf, SPI_XFER_ONCE);
+	if (error)
+		return error;
+
+	error = spi_set_wordlen(spi, 8);
+	if (error)
+		return error;
+
+	/* Read rest of the data */
+	error = spi_xfer(spi, 8, NULL, &ids_buf, SPI_XFER_ONCE);
+	if (error)
+		return error;
+
+	*rddid = ids_buf;
+
+	return 0;
+}
+
+static int scf0403_spi_transfer(struct spi_slave *spi, struct scf0403_cmd *cmd)
+{
+	int i, error;
+	u32 command = cmd->cmd;
+	u32 msg;
+
+	error = spi_set_wordlen(spi, 9);
+	if (error)
+		return error;
+
+	error = spi_xfer(spi, 9, &command, NULL, SPI_XFER_ONCE);
+	if (error)
+		return error;
+
+	for (i = 0; i < cmd->count; i++) {
+		msg = (cmd->params[i] | 0x100);
+		error = spi_xfer(spi, 9, &msg, NULL, SPI_XFER_ONCE);
+		if (error)
+			return error;
+	}
+
+	return 0;
+}
+
+static void scf0403_lcd_init(struct scf0403_priv *priv)
+{
+	int i;
+
+	/* reset LCD */
+	scf0403_gpio_reset(priv->reset_gpio);
+
+	for (i = 0; i < priv->seq_size; i++) {
+		if (scf0403_spi_transfer(priv->spi, &priv->init_seq[i].cmd) < 0)
+			puts("SPI transfer failed\n");
+
+		mdelay(priv->init_seq[i].delay_ms);
+	}
+}
+
+static int scf0403_request_reset_gpio(unsigned gpio)
+{
+	int err = gpio_request(gpio, "lcd reset");
+
+	if (err)
+		return err;
+
+	err = gpio_direction_output(gpio, 0);
+	if (err)
+		gpio_free(gpio);
+
+	return err;
+}
+
+int scf0403_init(int reset_gpio)
+{
+	int error;
+
+	if (gpio_is_valid(reset_gpio)) {
+		error = scf0403_request_reset_gpio(reset_gpio);
+		if (error) {
+			printf("Failed requesting reset GPIO%d: %d\n",
+			       reset_gpio, error);
+			return error;
+		}
+	}
+
+	priv.reset_gpio = reset_gpio;
+	priv.spi = spi_setup_slave(3, 0, 1000000, SPI_MODE_0);
+	error = spi_claim_bus(priv.spi);
+	if (error)
+		goto bus_claim_fail;
+
+	/* reset LCD */
+	scf0403_gpio_reset(reset_gpio);
+
+	error = scf0403_spi_read_rddid(priv.spi, &priv.rddid);
+	if (error) {
+		puts("IDs read failed\n");
+		goto readid_fail;
+	}
+
+	if (priv.rddid == SCF0403852GGU04_ID) {
+		priv.init_seq = scf0403_initseq_sn04;
+		priv.seq_size = ARRAY_SIZE(scf0403_initseq_sn04);
+	} else {
+		priv.init_seq = scf0403_initseq_sn20;
+		priv.seq_size = ARRAY_SIZE(scf0403_initseq_sn20);
+	}
+
+	scf0403_lcd_init(&priv);
+
+	/* Start operation */
+	scf0403_spi_transfer(priv.spi, &scf0403_cmd_dison);
+	mdelay(100);
+	scf0403_spi_transfer(priv.spi, &scf0403_cmd_slpout);
+	spi_release_bus(priv.spi);
+
+	return 0;
+
+readid_fail:
+	spi_release_bus(priv.spi);
+bus_claim_fail:
+	if (gpio_is_valid(priv.reset_gpio))
+		gpio_free(priv.reset_gpio);
+
+	return error;
+}
diff --git a/drivers/watchdog/Makefile b/drivers/watchdog/Makefile
index 3ade624702..06ced10c35 100644
--- a/drivers/watchdog/Makefile
+++ b/drivers/watchdog/Makefile
@@ -5,35 +5,13 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	:= $(obj)libwatchdog.o
-
-COBJS-$(CONFIG_AT91SAM9_WATCHDOG) += at91sam9_wdt.o
-COBJS-$(CONFIG_FTWDT010_WATCHDOG) += ftwdt010_wdt.o
+obj-$(CONFIG_AT91SAM9_WATCHDOG) += at91sam9_wdt.o
+obj-$(CONFIG_FTWDT010_WATCHDOG) += ftwdt010_wdt.o
 ifneq (,$(filter $(SOC), mx31 mx35 mx5 mx6 vf610))
-COBJS-y += imx_watchdog.o
+obj-y += imx_watchdog.o
 endif
-COBJS-$(CONFIG_TNETV107X_WATCHDOG) += tnetv107x_wdt.o
-COBJS-$(CONFIG_S5P)               += s5p_wdt.o
-COBJS-$(CONFIG_XILINX_TB_WATCHDOG) += xilinx_tb_wdt.o
-COBJS-$(CONFIG_BFIN_WATCHDOG)  += bfin_wdt.o
-COBJS-$(CONFIG_OMAP_WATCHDOG) += omap_wdt.o
-
-COBJS	:= $(COBJS-y)
-SRCS	:= $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-
-all:	$(LIB)
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-$(CONFIG_TNETV107X_WATCHDOG) += tnetv107x_wdt.o
+obj-$(CONFIG_S5P)               += s5p_wdt.o
+obj-$(CONFIG_XILINX_TB_WATCHDOG) += xilinx_tb_wdt.o
+obj-$(CONFIG_BFIN_WATCHDOG)  += bfin_wdt.o
+obj-$(CONFIG_OMAP_WATCHDOG) += omap_wdt.o
diff --git a/drivers/watchdog/imx_watchdog.c b/drivers/watchdog/imx_watchdog.c
index 50e602af12..d5993b4d26 100644
--- a/drivers/watchdog/imx_watchdog.c
+++ b/drivers/watchdog/imx_watchdog.c
@@ -19,6 +19,7 @@ struct watchdog_regs {
 #define WCR_WDBG	0x02
 #define WCR_WDE		0x04	/* WDOG enable */
 #define WCR_WDT		0x08
+#define WCR_SRS		0x10
 #define WCR_WDW		0x80
 #define SET_WCR_WT(x)	(x << 8)
 
@@ -45,7 +46,7 @@ void hw_watchdog_init(void)
 #define CONFIG_WATCHDOG_TIMEOUT_MSECS 128000
 #endif
 	timeout = (CONFIG_WATCHDOG_TIMEOUT_MSECS / 500) - 1;
-	writew(WCR_WDZST | WCR_WDBG | WCR_WDE | WCR_WDT |
+	writew(WCR_WDZST | WCR_WDBG | WCR_WDE | WCR_WDT | WCR_SRS |
 		WCR_WDW | SET_WCR_WT(timeout), &wdog->wcr);
 	hw_watchdog_reset();
 }
diff --git a/dts/.gitignore b/dts/.gitignore
new file mode 100644
index 0000000000..1b3718065c
--- /dev/null
+++ b/dts/.gitignore
@@ -0,0 +1,2 @@
+*.dtb
+*.dtb.S
diff --git a/dts/Makefile b/dts/Makefile
index 3cf991eaf2..e59550c9d2 100644
--- a/dts/Makefile
+++ b/dts/Makefile
@@ -7,86 +7,41 @@
 # This Makefile builds the internal U-Boot fdt if CONFIG_OF_CONTROL is
 # enabled. See doc/README.fdt-control for more details.
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)libdts.o
-
+DEVICE_TREE ?= $(CONFIG_DEFAULT_DEVICE_TREE:"%"=%)
 ifeq ($(DEVICE_TREE),)
-$(if $(CONFIG_DEFAULT_DEVICE_TREE),,\
-$(error Please define CONFIG_DEFAULT_DEVICE_TREE in your board header file))
-DEVICE_TREE = $(subst ",,$(CONFIG_DEFAULT_DEVICE_TREE))
+DEVICE_TREE := unset
 endif
 
-DTS_INCDIRS =  $(SRCTREE)/board/$(VENDOR)/$(BOARD)/dts
-DTS_INCDIRS += $(SRCTREE)/board/$(VENDOR)/dts
-DTS_INCDIRS += $(SRCTREE)/arch/$(ARCH)/dts
-
-DTS_CPPFLAGS := -x assembler-with-cpp -undef -D__DTS__ \
-		-nostdinc $(addprefix -I,$(DTS_INCDIRS))
-
-DTC_FLAGS := -R 4 -p 0x1000 \
-	$(addprefix -i ,$(DTS_INCDIRS))
-
-all:	$(obj).depend $(LIB)
-
-# Use a constant name for this so we can access it from C code.
-# objcopy doesn't seem to allow us to set the symbol name independently of
-# the filename.
-DT_BIN	:= $(obj)dt.dtb
-
-$(DT_BIN): $(TOPDIR)/board/$(VENDOR)/dts/$(DEVICE_TREE).dts
-	$(CPP) $(DTS_CPPFLAGS) $< -o $(DT_BIN).dts.tmp
-	$(DTC) $(DTC_FLAGS) -O dtb -o ${DT_BIN} $(DT_BIN).dts.tmp
-
-process_lds = \
-	$(1) | sed -r -n 's/^OUTPUT_$(2)[ ("]*([^")]*).*/\1/p'
-
-# Run the compiler and get the link script from the linker
-GET_LDS = $(CC) $(CFLAGS) $(LDFLAGS) -Wl,--verbose 2>&1
+DTB := arch/$(ARCH)/dts/$(DEVICE_TREE).dtb
 
-$(obj)dt.o: $(DT_BIN)
-	# We want the output format and arch.
-	# We also hope to win a prize for ugliest Makefile / shell interaction
-	# We look in the LDSCRIPT first.
-	# Then try the linker which should give us the answer.
-	# Then check it worked.
-	[ -n "$(LDSCRIPT)" ] && \
-		oformat=`$(call process_lds,cat $(LDSCRIPT),FORMAT)` && \
-		oarch=`$(call process_lds,cat $(LDSCRIPT),ARCH)` ;\
-	\
-	[ -z $${oformat} ] && \
-		oformat=`$(call process_lds,$(GET_LDS),FORMAT)` ;\
-	[ -z $${oarch} ] && \
-		oarch=`$(call process_lds,$(GET_LDS),ARCH)` ;\
-	\
-	[ -z $${oformat} ] && \
-		echo "Cannot read OUTPUT_FORMAT from lds file $(LDSCRIPT)" && \
-		exit 1 || true ;\
-	[ -z $${oarch} ] && \
-		echo "Cannot read OUTPUT_ARCH from lds file $(LDSCRIPT)" && \
-		exit 1 || true ;\
-	\
-	cd $(dir ${DT_BIN}) && \
-	$(OBJCOPY) -I binary -O $${oformat} -B $${oarch} \
-		$(notdir ${DT_BIN}) $@
-	rm $(DT_BIN)
+quiet_cmd_copy = COPY    $@
+      cmd_copy = cp $< $@
 
-OBJS-$(CONFIG_OF_EMBED)	:= dt.o
+$(obj)/dt.dtb: $(DTB) FORCE
+	$(call if_changed,copy)
 
-COBJS	:= $(OBJS-y)
+targets += dt.dtb
 
-OBJS	:= $(addprefix $(obj),$(COBJS))
+$(DTB): arch-dtbs
+	$(Q)test -e $@ || (						\
+	echo >&2;							\
+	echo >&2 "Device Tree Source is not correctly specified.";	\
+	echo >&2 "Please define 'CONFIG_DEFAULT_DEVICE_TREE'";		\
+	echo >&2 "or build with 'DEVICE_TREE=<device_tree>' argument";	\
+	echo >&2;							\
+	/bin/false)
 
-binary:	$(DT_BIN)
+arch-dtbs:
+	$(Q)$(MAKE) $(build)=arch/$(ARCH)/dts dtbs
 
-$(LIB):	$(OBJS) $(DTB)
-	$(call cmd_link_o_target, $(OBJS))
+.SECONDARY: $(obj)/dt.dtb.S
 
-#########################################################################
+obj-$(CONFIG_OF_EMBED) := dt.dtb.o
 
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
+dtbs: $(obj)/dt.dtb
+	@:
 
-sinclude $(obj).depend
+clean-files := dt.dtb.S
 
-#########################################################################
+# Let clean descend into dts directories
+subdir- += ../arch/arm/dts ../arch/microblaze/dts ../arch/sandbox/dts ../arch/x86/dts
diff --git a/examples/Makefile b/examples/Makefile
new file mode 100644
index 0000000000..18d008e7b5
--- /dev/null
+++ b/examples/Makefile
@@ -0,0 +1,9 @@
+ifndef CONFIG_SANDBOX
+
+ifdef FTRACE
+subdir-ccflags-y += -finstrument-functions -DFTRACE
+endif
+
+subdir-y += standalone
+subdir-$(CONFIG_API) += api
+endif
diff --git a/examples/api/Makefile b/examples/api/Makefile
index 4d683400e1..6cf23d10ac 100644
--- a/examples/api/Makefile
+++ b/examples/api/Makefile
@@ -11,64 +11,47 @@ ifeq ($(ARCH),arm)
 LOAD_ADDR = 0x1000000
 endif
 
-include $(TOPDIR)/config.mk
-
 # Resulting ELF and binary exectuables will be named demo and demo.bin
-OUTPUT-$(CONFIG_API) = $(obj)demo
-OUTPUT = $(OUTPUT-y)
+extra-y = demo
 
 # Source files located in the examples/api directory
-SOBJ_FILES-$(CONFIG_API) += crt0.o
-COBJ_FILES-$(CONFIG_API) += demo.o
-COBJ_FILES-$(CONFIG_API) += glue.o
-COBJ_FILES-$(CONFIG_API) += libgenwrap.o
+OBJ-y += crt0.o
+OBJ-y += demo.o
+OBJ-y += glue.o
+OBJ-y += libgenwrap.o
 
 # Source files which exist outside the examples/api directory
-EXT_COBJ_FILES-$(CONFIG_API) += lib/crc32.o
-EXT_COBJ_FILES-$(CONFIG_API) += lib/ctype.o
-EXT_COBJ_FILES-$(CONFIG_API) += lib/div64.o
-EXT_COBJ_FILES-$(CONFIG_API) += lib/string.o
-EXT_COBJ_FILES-$(CONFIG_API) += lib/time.o
-EXT_COBJ_FILES-$(CONFIG_API) += lib/vsprintf.o
-ifeq ($(ARCH),powerpc)
-EXT_SOBJ_FILES-$(CONFIG_API) += arch/powerpc/lib/ppcstring.o
-endif
-
-# Create a list of source files so their dependencies can be auto-generated
-SRCS	+= $(addprefix $(SRCTREE)/,$(EXT_COBJ_FILES-y:.o=.c))
-SRCS	+= $(addprefix $(SRCTREE)/,$(EXT_SOBJ_FILES-y:.o=.S))
-SRCS	+= $(addprefix $(SRCTREE)/examples/api/,$(COBJ_FILES-y:.o=.c))
-SRCS	+= $(addprefix $(SRCTREE)/examples/api/,$(SOBJ_FILES-y:.o=.S))
+EXT_COBJ-y += lib/crc32.o
+EXT_COBJ-y += lib/ctype.o
+EXT_COBJ-y += lib/div64.o
+EXT_COBJ-y += lib/string.o
+EXT_COBJ-y += lib/time.o
+EXT_COBJ-y += lib/vsprintf.o
+EXT_SOBJ-$(CONFIG_PPC) += arch/powerpc/lib/ppcstring.o
 
 # Create a list of object files to be compiled
-OBJS	+= $(addprefix $(obj),$(SOBJ_FILES-y))
-OBJS	+= $(addprefix $(obj),$(COBJ_FILES-y))
-OBJS	+= $(addprefix $(obj),$(notdir $(EXT_COBJ_FILES-y)))
-OBJS	+= $(addprefix $(obj),$(notdir $(EXT_SOBJ_FILES-y)))
+OBJS := $(OBJ-y) $(notdir $(EXT_COBJ-y) $(EXT_SOBJ-y))
+targets += $(OBJS)
+OBJS := $(addprefix $(obj)/,$(OBJS))
 
-CPPFLAGS += -I..
+#########################################################################
 
-all:	$(obj).depend $(OUTPUT)
+quiet_cmd_link_demo = LD      $@
+cmd_link_demo = $(LD) --gc-sections -Ttext $(LOAD_ADDR) -o $@ $(filter-out $(PHONY), $^) $(PLATFORM_LIBS)
 
-#########################################################################
+$(obj)/demo: $(OBJS) FORCE
+	$(call if_changed,link_demo)
 
-$(OUTPUT):	$(OBJS)
-		$(LD) -Ttext $(LOAD_ADDR) -o $@ $^ $(PLATFORM_LIBS)
-		$(OBJCOPY) -O binary $@ $(OUTPUT).bin 2>/dev/null
+# demo.bin is never genrated. Is this necessary?
+OBJCOPYFLAGS_demo.bin := -O binary
+$(obj)/demo.bin: $(obj)/demo FORCE
+	$(call if_changed,objcopy)
 
 # Rule to build generic library C files
-$(obj)%.o: $(SRCTREE)/lib/%.c
-	$(CC) -g $(CFLAGS) -c -o $@ $<
+$(addprefix $(obj)/,$(notdir $(EXT_COBJ-y))): $(obj)/%.o: lib/%.c FORCE
+	$(call cmd,force_checksrc)
+	$(call if_changed_rule,cc_o_c)
 
 # Rule to build architecture-specific library assembly files
-$(obj)%.o: $(SRCTREE)/arch/$(ARCH)/lib/%.S
-	$(CC) -g $(CFLAGS) -c -o $@ $<
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+$(addprefix $(obj)/,$(notdir $(EXT_SOBJ-y))): $(obj)/%.o: arch/powerpc/lib/%.S FORCE
+	$(call if_changed_dep,as_o_S)
diff --git a/examples/standalone/.gitignore b/examples/standalone/.gitignore
index 4d9ce66402..6d3a6166d2 100644
--- a/examples/standalone/.gitignore
+++ b/examples/standalone/.gitignore
@@ -1,6 +1,4 @@
-/82559_eeprom
 /atmel_df_pow2
-/eepro100_eeprom
 /hello_world
 /interrupt
 /mem_to_mem_idma2intr
diff --git a/examples/standalone/82559_eeprom.c b/examples/standalone/82559_eeprom.c
deleted file mode 100644
index 8dd7079ae7..0000000000
--- a/examples/standalone/82559_eeprom.c
+++ /dev/null
@@ -1,357 +0,0 @@
-
-/*
- * Copyright 1998-2001 by Donald Becker.
- * This software may be used and distributed according to the terms of
- * the GNU General Public License (GPL), incorporated herein by reference.
- * Contact the author for use under other terms.
- *
- * This program must be compiled with "-O"!
- * See the bottom of this file for the suggested compile-command.
- *
- * The author may be reached as becker@scyld.com, or C/O
- *  Scyld Computing Corporation
- *  410 Severn Ave., Suite 210
- *  Annapolis MD 21403
- *
- * Common-sense licensing statement: Using any portion of this program in
- * your own program means that you must give credit to the original author
- * and release the resulting code under the GPL.
- */
-
-#define _PPC_STRING_H_		/* avoid unnecessary str/mem functions */
-
-#include <common.h>
-#include <exports.h>
-#include <asm/io.h>
-
-
-/* Default EEPROM for i82559 */
-static unsigned short default_eeprom[64] = {
-	0x0100, 0x0302, 0x0504, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,
-	0xffff, 0xffff, 0x40c0, 0x0000, 0x0000, 0xffff, 0xffff, 0xffff,
-	0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,
-	0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,
-	0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,
-	0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,
-	0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,
-	0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff
-};
-
-static unsigned short eeprom[256];
-
-static int eeprom_size = 64;
-static int eeprom_addr_size = 6;
-
-static int debug = 0;
-
-static inline unsigned short swap16(unsigned short x)
-{
-	return (((x & 0xff) << 8) | ((x & 0xff00) >> 8));
-}
-
-
-void * memcpy(void * dest,const void *src,size_t count)
-{
-	char *tmp = (char *) dest, *s = (char *) src;
-
-	while (count--)
-		*tmp++ = *s++;
-
-	return dest;
-}
-
-
-/* The EEPROM commands include the alway-set leading bit. */
-#define EE_WRITE_CMD	(5)
-#define EE_READ_CMD		(6)
-#define EE_ERASE_CMD	(7)
-
-/* Serial EEPROM section. */
-#define EE_SHIFT_CLK	0x01	/* EEPROM shift clock. */
-#define EE_CS			0x02	/* EEPROM chip select. */
-#define EE_DATA_WRITE	0x04	/* EEPROM chip data in. */
-#define EE_DATA_READ	0x08	/* EEPROM chip data out. */
-#define EE_ENB			(0x4800 | EE_CS)
-#define EE_WRITE_0		0x4802
-#define EE_WRITE_1		0x4806
-#define EE_OFFSET		14
-
-/* Delay between EEPROM clock transitions. */
-#define eeprom_delay(ee_addr)	inw(ee_addr)
-
-/* Wait for the EEPROM to finish the previous operation. */
-static int eeprom_busy_poll(long ee_ioaddr)
-{
-	int i;
-	outw(EE_ENB, ee_ioaddr);
-	for (i = 0; i < 10000; i++)			/* Typical 2000 ticks */
-		if (inw(ee_ioaddr) & EE_DATA_READ)
-			break;
-	return i;
-}
-
-/* This executes a generic EEPROM command, typically a write or write enable.
-   It returns the data output from the EEPROM, and thus may also be used for
-   reads. */
-static int do_eeprom_cmd(long ioaddr, int cmd, int cmd_len)
-{
-	unsigned retval = 0;
-	long ee_addr = ioaddr + EE_OFFSET;
-
-	if (debug > 1)
-		printf(" EEPROM op 0x%x: ", cmd);
-
-	outw(EE_ENB | EE_SHIFT_CLK, ee_addr);
-
-	/* Shift the command bits out. */
-	do {
-		short dataval = (cmd & (1 << cmd_len)) ? EE_WRITE_1 : EE_WRITE_0;
-		outw(dataval, ee_addr);
-		eeprom_delay(ee_addr);
-		if (debug > 2)
-			printf("%X", inw(ee_addr) & 15);
-		outw(dataval | EE_SHIFT_CLK, ee_addr);
-		eeprom_delay(ee_addr);
-		retval = (retval << 1) | ((inw(ee_addr) & EE_DATA_READ) ? 1 : 0);
-	} while (--cmd_len >= 0);
-#if 0
-	outw(EE_ENB, ee_addr);
-#endif
-	/* Terminate the EEPROM access. */
-	outw(EE_ENB & ~EE_CS, ee_addr);
-	if (debug > 1)
-		printf(" EEPROM result is 0x%5.5x.\n", retval);
-	return retval;
-}
-
-static int read_eeprom(long ioaddr, int location, int addr_len)
-{
-	return do_eeprom_cmd(ioaddr, ((EE_READ_CMD << addr_len) | location)
-		<< 16 , 3 + addr_len + 16) & 0xffff;
-}
-
-static void write_eeprom(long ioaddr, int index, int value, int addr_len)
-{
-	long ee_ioaddr = ioaddr + EE_OFFSET;
-	int i;
-
-	/* Poll for previous op finished. */
-	eeprom_busy_poll(ee_ioaddr);			/* Typical 0 ticks */
-	/* Enable programming modes. */
-	do_eeprom_cmd(ioaddr, (0x4f << (addr_len-4)), 3 + addr_len);
-	/* Do the actual write. */
-	do_eeprom_cmd(ioaddr,
-				  (((EE_WRITE_CMD<<addr_len) | index)<<16) | (value & 0xffff),
-				  3 + addr_len + 16);
-	/* Poll for write finished. */
-	i = eeprom_busy_poll(ee_ioaddr);			/* Typical 2000 ticks */
-	if (debug)
-		printf(" Write finished after %d ticks.\n", i);
-	/* Disable programming. This command is not instantaneous, so we check
-	   for busy before the next op. */
-	do_eeprom_cmd(ioaddr, (0x40 << (addr_len-4)), 3 + addr_len);
-	eeprom_busy_poll(ee_ioaddr);
-}
-
-static int reset_eeprom(unsigned long ioaddr, unsigned char *hwaddr)
-{
-	unsigned short checksum = 0;
-	int size_test;
-	int i;
-
-	printf("Resetting i82559 EEPROM @ 0x%08lx ... ", ioaddr);
-
-	size_test = do_eeprom_cmd(ioaddr, (EE_READ_CMD << 8) << 16, 27);
-	eeprom_addr_size = (size_test & 0xffe0000) == 0xffe0000 ? 8 : 6;
-	eeprom_size = 1 << eeprom_addr_size;
-
-	memcpy(eeprom, default_eeprom, sizeof default_eeprom);
-
-	for (i = 0; i < 3; i++)
-		eeprom[i] = (hwaddr[i*2+1]<<8) + hwaddr[i*2];
-
-	/* Recalculate the checksum. */
-	for (i = 0; i < eeprom_size - 1; i++)
-		checksum += eeprom[i];
-	eeprom[i] = 0xBABA - checksum;
-
-	for (i = 0; i < eeprom_size; i++)
-		write_eeprom(ioaddr, i, eeprom[i], eeprom_addr_size);
-
-	for (i = 0; i < eeprom_size; i++)
-		if (read_eeprom(ioaddr, i, eeprom_addr_size) != eeprom[i]) {
-			printf("failed\n");
-			return 1;
-		}
-
-	printf("done\n");
-	return 0;
-}
-
-static unsigned int hatoi(char *p, char **errp)
-{
-	unsigned int res = 0;
-
-	while (1) {
-		switch (*p) {
-		case 'a':
-		case 'b':
-		case 'c':
-		case 'd':
-		case 'e':
-		case 'f':
-			res |= (*p - 'a' + 10);
-			break;
-		case 'A':
-		case 'B':
-		case 'C':
-		case 'D':
-		case 'E':
-		case 'F':
-			res |= (*p - 'A' + 10);
-			break;
-		case '0':
-		case '1':
-		case '2':
-		case '3':
-		case '4':
-		case '5':
-		case '6':
-		case '7':
-		case '8':
-		case '9':
-			res |= (*p - '0');
-			break;
-		default:
-			if (errp) {
-				*errp = p;
-			}
-		return res;
-		}
-		p++;
-		if (*p == 0) {
-			break;
-		}
-		res <<= 4;
-	}
-
-	if (errp) {
-		*errp = NULL;
-	}
-
-	return res;
-}
-
-static unsigned char *gethwaddr(char *in, unsigned char *out)
-{
-	char tmp[3];
-	int i;
-	char *err;
-
-	for (i=0;i<6;i++) {
-		if (in[i*3+2] == 0 && i == 5) {
-			out[i] = hatoi(&in[i*3], &err);
-			if (err) {
-				return NULL;
-			}
-		} else if (in[i*3+2] == ':' && i < 5) {
-			tmp[0] = in[i*3];
-			tmp[1] = in[i*3+1];
-			tmp[2] = 0;
-			out[i] = hatoi(tmp, &err);
-			if (err) {
-				return NULL;
-			}
-		} else {
-			return NULL;
-		}
-	}
-
-	return out;
-}
-
-static u32
-read_config_dword(int bus, int dev, int func, int reg)
-{
-	u32 res;
-
-	outl(0x80000000|(bus&0xff)<<16|(dev&0x1f)<<11|(func&7)<<8|(reg&0xfc),
-	     0xcf8);
-	res = inl(0xcfc);
-	outl(0, 0xcf8);
-	return res;
-}
-
-static u16
-read_config_word(int bus, int dev, int func, int reg)
-{
-	u32 res;
-
-	outl(0x80000000|(bus&0xff)<<16|(dev&0x1f)<<11|(func&7)<<8|(reg&0xfc),
-	     0xcf8);
-	res = inw(0xcfc + (reg & 2));
-	outl(0, 0xcf8);
-	return res;
-}
-
-static void
-write_config_word(int bus, int dev, int func, int reg, u16 data)
-{
-
-	outl(0x80000000|(bus&0xff)<<16|(dev&0x1f)<<11|(func&7)<<8|(reg&0xfc),
-	     0xcf8);
-	outw(data, 0xcfc + (reg & 2));
-	outl(0, 0xcf8);
-}
-
-
-int main (int argc, char * const argv[])
-{
-	unsigned char *eth_addr;
-	uchar buf[6];
-	int instance;
-
-	app_startup(argv);
-	if (argc != 2) {
-		printf ("call with base Ethernet address\n");
-		return 1;
-	}
-
-
-	eth_addr = gethwaddr(argv[1], buf);
-	if (NULL == eth_addr) {
-		printf ("Can not parse ethernet address\n");
-		return 1;
-	}
-	if (eth_addr[5] & 0x01) {
-		printf("Base Ethernet address must be even\n");
-	}
-
-
-	for (instance = 0; instance < 2; instance ++)  {
-		unsigned int io_addr;
-		unsigned char mac[6];
-		int bar1 = read_config_dword(0, 6+instance, 0, 0x14);
-		if (! (bar1 & 1)) {
-			printf("ETH%d is disabled %x\n", instance, bar1);
-		} else {
-			printf("ETH%d IO=0x%04x\n", instance, bar1 & ~3);
-		}
-		io_addr = (bar1 & (~3L));
-
-
-		write_config_word(0, 6+instance, 0, 4,
-				  read_config_word(0, 6+instance, 0, 4) | 1);
-		printf("ETH%d CMD %04x\n", instance,
-			   read_config_word(0, 6+instance, 0, 4));
-
-		memcpy(mac, eth_addr, 6);
-		mac[5] += instance;
-
-		printf("got io=%04x, ha=%02x:%02x:%02x:%02x:%02x:%02x\n",
-			   io_addr, mac[0], mac[1], mac[2],
-			   mac[3], mac[4], mac[5]);
-		reset_eeprom(io_addr, mac);
-	}
-	return 0;
-}
diff --git a/examples/standalone/Makefile b/examples/standalone/Makefile
index 4afedea065..9ab5446c68 100644
--- a/examples/standalone/Makefile
+++ b/examples/standalone/Makefile
@@ -5,98 +5,73 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-ELF-$(ARCH)  :=
-ELF-$(BOARD) :=
-ELF-$(CPU)   :=
-ELF-y        := hello_world
-
-ELF-$(CONFIG_SMC91111)           += smc91111_eeprom
-ELF-$(CONFIG_SMC911X)            += smc911x_eeprom
-ELF-$(CONFIG_SPI_FLASH_ATMEL)    += atmel_df_pow2
-ELF-i386                         += 82559_eeprom
-ELF-mpc5xxx                      += interrupt
-ELF-mpc8xx                       += test_burst timer
-ELF-mpc8260                      += mem_to_mem_idma2intr
-ELF-ppc                          += sched
-ELF-oxc                          += eepro100_eeprom
+extra-y        := hello_world
+extra-$(CONFIG_SMC91111)           += smc91111_eeprom
+extra-$(CONFIG_SMC911X)            += smc911x_eeprom
+extra-$(CONFIG_SPI_FLASH_ATMEL)    += atmel_df_pow2
+extra-$(CONFIG_MPC5xxx)            += interrupt
+extra-$(CONFIG_8xx)                += test_burst timer
+extra-$(CONFIG_MPC8260)            += mem_to_mem_idma2intr
+extra-$(CONFIG_PPC)                += sched
 
 #
 # Some versions of make do not handle trailing white spaces properly;
 # leading to build failures. The problem was found with GNU Make 3.80.
 # Using 'strip' as a workaround for the problem.
 #
-ELF := $(strip $(ELF-y) $(ELF-$(ARCH)) $(ELF-$(BOARD)) $(ELF-$(CPU)))
+ELF := $(strip $(extra-y))
 
-SREC := $(addsuffix .srec,$(ELF))
-BIN  := $(addsuffix .bin,$(ELF))
+extra-y += $(addsuffix .srec,$(extra-y)) $(addsuffix .bin,$(extra-y))
+clean-files  := $(extra-) $(addsuffix .srec,$(extra-)) $(addsuffix .bin,$(extra-))
 
 COBJS	:= $(ELF:=.o)
 
-LIB	= $(obj)libstubs.o
+LIB	= $(obj)/libstubs.o
 
-LIBAOBJS-$(ARCH)     :=
-LIBAOBJS-$(CPU)      :=
-LIBAOBJS-ppc         += $(ARCH)_longjmp.o $(ARCH)_setjmp.o
-LIBAOBJS-mpc8xx      += test_burst_lib.o
-LIBAOBJS := $(LIBAOBJS-$(ARCH)) $(LIBAOBJS-$(CPU))
+LIBOBJS-$(CONFIG_PPC) += ppc_longjmp.o ppc_setjmp.o
+LIBOBJS-$(CONFIG_8xx) += test_burst_lib.o
+LIBOBJS-y += stubs.o
 
-LIBCOBJS = stubs.o
+.SECONDARY: $(call objectify,$(COBJS))
+targets += $(patsubst $(obj)/%,%,$(LIB)) $(COBJS) $(LIBOBJS-y)
 
-LIBOBJS	= $(addprefix $(obj),$(LIBAOBJS) $(LIBCOBJS))
-
-SRCS	:= $(COBJS:.o=.c) $(LIBCOBJS:.o=.c) $(LIBAOBJS:.o=.S)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-ELF	:= $(addprefix $(obj),$(ELF))
-BIN	:= $(addprefix $(obj),$(BIN))
-SREC	:= $(addprefix $(obj),$(SREC))
+LIBOBJS	:= $(addprefix $(obj)/,$(LIBOBJS-y))
+ELF	:= $(addprefix $(obj)/,$(ELF))
 
 gcclibdir := $(shell dirname `$(CC) -print-libgcc-file-name`)
 
-CPPFLAGS += -I..
-
 # For PowerPC there's no need to compile standalone applications as a
 # relocatable executable.  The relocation data is not needed, and
 # also causes the entry point of the standalone application to be
 # inconsistent.
-ifeq ($(ARCH),powerpc)
-AFLAGS := $(filter-out $(RELFLAGS),$(AFLAGS))
-CFLAGS := $(filter-out $(RELFLAGS),$(CFLAGS))
-CPPFLAGS := $(filter-out $(RELFLAGS),$(CPPFLAGS))
+ifeq ($(CONFIG_PPC),y)
+PLATFORM_CPPFLAGS := $(filter-out $(RELFLAGS),$(PLATFORM_CPPFLAGS))
 endif
 
 # We don't want gcc reordering functions if possible.  This ensures that an
 # application's entry point will be the first function in the application's
 # source file.
-CFLAGS_NTR := $(call cc-option,-fno-toplevel-reorder)
-CFLAGS += $(CFLAGS_NTR)
-
-all:	$(obj).depend $(OBJS) $(LIB) $(SREC) $(BIN) $(ELF)
+ccflags-y += $(call cc-option,-fno-toplevel-reorder)
 
 #########################################################################
-$(LIB):	$(obj).depend $(LIBOBJS)
-	$(call cmd_link_o_target, $(LIBOBJS))
 
-$(ELF):
-$(obj)%:	$(obj)%.o $(LIB)
-		$(LD) $(LDFLAGS) -g -Ttext $(CONFIG_STANDALONE_LOAD_ADDR) \
-			-o $@ -e $(SYM_PREFIX)$(notdir $(<:.o=)) $< $(LIB) \
-			-L$(gcclibdir) -lgcc
+quiet_cmd_link_lib = LD      $@
+      cmd_link_lib = $(LD) $(ld_flags) -r -o $@ $(filter $(LIBOBJS), $^)
 
-$(SREC):
-$(obj)%.srec:	$(obj)%
-		$(OBJCOPY) -O srec $< $@ 2>/dev/null
+$(LIB):	$(LIBOBJS) FORCE
+	$(call if_changed,link_lib)
 
-$(BIN):
-$(obj)%.bin:	$(obj)%
-		$(OBJCOPY) -O binary $< $@ 2>/dev/null
+quiet_cmd_link_elf = LD      $@
+      cmd_link_elf = $(LD) $(LDFLAGS) -g -Ttext $(CONFIG_STANDALONE_LOAD_ADDR) \
+		     -o $@ -e $(SYM_PREFIX)$(@F) $< $(LIB) -L$(gcclibdir) -lgcc
 
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
+$(ELF): $(obj)/%: $(obj)/%.o $(LIB) FORCE
+	$(call if_changed,link_elf)
 
-sinclude $(obj).depend
+$(obj)/%.srec: OBJCOPYFLAGS := -O srec
+$(obj)/%.srec: $(obj)/% FORCE
+	$(call if_changed,objcopy)
 
-#########################################################################
+$(obj)/%.bin: OBJCOPYFLAGS := -O binary
+$(obj)/%.bin: $(obj)/% FORCE
+	$(call if_changed,objcopy)
diff --git a/examples/standalone/eepro100_eeprom.c b/examples/standalone/eepro100_eeprom.c
deleted file mode 100644
index 3c7f380977..0000000000
--- a/examples/standalone/eepro100_eeprom.c
+++ /dev/null
@@ -1,214 +0,0 @@
-/*
- * Copyright 1998-2001 by Donald Becker.
- * This software may be used and distributed according to the terms of
- * the GNU General Public License (GPL), incorporated herein by reference.
- * Contact the author for use under other terms.
- *
- * This program must be compiled with "-O"!
- * See the bottom of this file for the suggested compile-command.
- *
- * The author may be reached as becker@scyld.com, or C/O
- *  Scyld Computing Corporation
- *  410 Severn Ave., Suite 210
- *  Annapolis MD 21403
- *
- * Common-sense licensing statement: Using any portion of this program in
- * your own program means that you must give credit to the original author
- * and release the resulting code under the GPL.
- */
-
-/* avoid unnecessary memcpy function */
-#define _PPC_STRING_H_
-
-#include <common.h>
-#include <exports.h>
-
-static int reset_eeprom(unsigned long ioaddr, unsigned char *hwaddr);
-
-int eepro100_eeprom(int argc, char * const argv[])
-{
-	int ret = 0;
-
-	unsigned char hwaddr1[6] = { 0x00, 0x00, 0x02, 0x03, 0x04, 0x05 };
-	unsigned char hwaddr2[6] = { 0x00, 0x00, 0x02, 0x03, 0x04, 0x06 };
-
-	app_startup(argv);
-
-#if defined(CONFIG_OXC)
-	ret |= reset_eeprom(0x80000000, hwaddr1);
-	ret |= reset_eeprom(0x81000000, hwaddr2);
-#endif
-
-	return ret;
-}
-
-/* Default EEPROM for i82559 */
-static unsigned short default_eeprom[64] = {
-	0x0100, 0x0302, 0x0504, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,
-	0xffff, 0xffff, 0x40c0, 0x0000, 0x0000, 0xffff, 0xffff, 0xffff,
-	0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,
-	0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,
-	0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,
-	0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,
-	0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,
-	0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff
-};
-
-static unsigned short eeprom[256];
-
-static int eeprom_size = 64;
-static int eeprom_addr_size = 6;
-
-static int debug = 0;
-
-static inline unsigned short swap16(unsigned short x)
-{
-	return (((x & 0xff) << 8) | ((x & 0xff00) >> 8));
-}
-
-static inline void outw(short data, long addr)
-{
-	*(volatile short *)(addr) = swap16(data);
-}
-
-static inline short inw(long addr)
-{
-	return swap16(*(volatile short *)(addr));
-}
-
-void *memcpy(void *dst, const void *src, unsigned int len)
-{
-	char *ret = dst;
-	while (len-- > 0) {
-		*ret++ = *((char *)src);
-		src++;
-	}
-	return (void *)ret;
-}
-
-/* The EEPROM commands include the alway-set leading bit. */
-#define EE_WRITE_CMD	(5)
-#define EE_READ_CMD		(6)
-#define EE_ERASE_CMD	(7)
-
-/* Serial EEPROM section. */
-#define EE_SHIFT_CLK	0x01	/* EEPROM shift clock. */
-#define EE_CS			0x02	/* EEPROM chip select. */
-#define EE_DATA_WRITE	0x04	/* EEPROM chip data in. */
-#define EE_DATA_READ	0x08	/* EEPROM chip data out. */
-#define EE_ENB			(0x4800 | EE_CS)
-#define EE_WRITE_0		0x4802
-#define EE_WRITE_1		0x4806
-#define EE_OFFSET		14
-
-/* Delay between EEPROM clock transitions. */
-#define eeprom_delay(ee_addr)	inw(ee_addr)
-
-/* Wait for the EEPROM to finish the previous operation. */
-static int eeprom_busy_poll(long ee_ioaddr)
-{
-	int i;
-	outw(EE_ENB, ee_ioaddr);
-	for (i = 0; i < 10000; i++)			/* Typical 2000 ticks */
-		if (inw(ee_ioaddr) & EE_DATA_READ)
-			break;
-	return i;
-}
-
-/* This executes a generic EEPROM command, typically a write or write enable.
-   It returns the data output from the EEPROM, and thus may also be used for
-   reads. */
-static int do_eeprom_cmd(long ioaddr, int cmd, int cmd_len)
-{
-	unsigned retval = 0;
-	long ee_addr = ioaddr + EE_OFFSET;
-
-	if (debug > 1)
-		printf(" EEPROM op 0x%x: ", cmd);
-
-	outw(EE_ENB | EE_SHIFT_CLK, ee_addr);
-
-	/* Shift the command bits out. */
-	do {
-		short dataval = (cmd & (1 << cmd_len)) ? EE_WRITE_1 : EE_WRITE_0;
-		outw(dataval, ee_addr);
-		eeprom_delay(ee_addr);
-		if (debug > 2)
-			printf("%X", inw(ee_addr) & 15);
-		outw(dataval | EE_SHIFT_CLK, ee_addr);
-		eeprom_delay(ee_addr);
-		retval = (retval << 1) | ((inw(ee_addr) & EE_DATA_READ) ? 1 : 0);
-	} while (--cmd_len >= 0);
-#if 0
-	outw(EE_ENB, ee_addr);
-#endif
-	/* Terminate the EEPROM access. */
-	outw(EE_ENB & ~EE_CS, ee_addr);
-	if (debug > 1)
-		printf(" EEPROM result is 0x%5.5x.\n", retval);
-	return retval;
-}
-
-static int read_eeprom(long ioaddr, int location, int addr_len)
-{
-	return do_eeprom_cmd(ioaddr, ((EE_READ_CMD << addr_len) | location)
-		<< 16 , 3 + addr_len + 16) & 0xffff;
-}
-
-static void write_eeprom(long ioaddr, int index, int value, int addr_len)
-{
-	long ee_ioaddr = ioaddr + EE_OFFSET;
-	int i;
-
-	/* Poll for previous op finished. */
-	eeprom_busy_poll(ee_ioaddr);			/* Typical 0 ticks */
-	/* Enable programming modes. */
-	do_eeprom_cmd(ioaddr, (0x4f << (addr_len-4)), 3 + addr_len);
-	/* Do the actual write. */
-	do_eeprom_cmd(ioaddr,
-				  (((EE_WRITE_CMD<<addr_len) | index)<<16) | (value & 0xffff),
-				  3 + addr_len + 16);
-	/* Poll for write finished. */
-	i = eeprom_busy_poll(ee_ioaddr);			/* Typical 2000 ticks */
-	if (debug)
-		printf(" Write finished after %d ticks.\n", i);
-	/* Disable programming. This command is not instantaneous, so we check
-	   for busy before the next op. */
-	do_eeprom_cmd(ioaddr, (0x40 << (addr_len-4)), 3 + addr_len);
-	eeprom_busy_poll(ee_ioaddr);
-}
-
-static int reset_eeprom(unsigned long ioaddr, unsigned char *hwaddr)
-{
-	unsigned short checksum = 0;
-	int size_test;
-	int i;
-
-	printf("Resetting i82559 EEPROM @ 0x%08lX ... ", ioaddr);
-
-	size_test = do_eeprom_cmd(ioaddr, (EE_READ_CMD << 8) << 16, 27);
-	eeprom_addr_size = (size_test & 0xffe0000) == 0xffe0000 ? 8 : 6;
-	eeprom_size = 1 << eeprom_addr_size;
-
-	memcpy(eeprom, default_eeprom, sizeof default_eeprom);
-
-	for (i = 0; i < 3; i++)
-		eeprom[i] = (hwaddr[i*2+1]<<8) + hwaddr[i*2];
-
-	/* Recalculate the checksum. */
-	for (i = 0; i < eeprom_size - 1; i++)
-		checksum += eeprom[i];
-	eeprom[i] = 0xBABA - checksum;
-
-	for (i = 0; i < eeprom_size; i++)
-		write_eeprom(ioaddr, i, eeprom[i], eeprom_addr_size);
-
-	for (i = 0; i < eeprom_size; i++)
-		if (read_eeprom(ioaddr, i, eeprom_addr_size) != eeprom[i]) {
-			printf("failed\n");
-			return 1;
-		}
-
-	printf("done\n");
-	return 0;
-}
diff --git a/examples/standalone/stubs.c b/examples/standalone/stubs.c
index 8fb17653b0..c5c025dab3 100644
--- a/examples/standalone/stubs.c
+++ b/examples/standalone/stubs.c
@@ -39,17 +39,32 @@ gd_t *global_data;
 "	bctr\n"				\
 	: : "i"(offsetof(gd_t, jt)), "i"(XF_ ## x * sizeof(void *)) : "r11");
 #elif defined(CONFIG_ARM)
+#ifdef CONFIG_ARM64
 /*
- * r8 holds the pointer to the global_data, ip is a call-clobbered
+ * x18 holds the pointer to the global_data, x9 is a call-clobbered
  * register
  */
 #define EXPORT_FUNC(x) \
 	asm volatile (			\
 "	.globl " #x "\n"		\
 #x ":\n"				\
-"	ldr	ip, [r8, %0]\n"		\
+"	ldr	x9, [x18, %0]\n"		\
+"	ldr	x9, [x9, %1]\n"		\
+"	br	x9\n"		\
+	: : "i"(offsetof(gd_t, jt)), "i"(XF_ ## x * sizeof(void *)) : "x9");
+#else
+/*
+ * r9 holds the pointer to the global_data, ip is a call-clobbered
+ * register
+ */
+#define EXPORT_FUNC(x) \
+	asm volatile (			\
+"	.globl " #x "\n"		\
+#x ":\n"				\
+"	ldr	ip, [r9, %0]\n"		\
 "	ldr	pc, [ip, %1]\n"		\
 	: : "i"(offsetof(gd_t, jt)), "i"(XF_ ## x * sizeof(void *)) : "ip");
+#endif
 #elif defined(CONFIG_MIPS)
 /*
  * k0 ($26) holds the pointer to the global_data; t9 ($25) is a call-
@@ -195,6 +210,19 @@ gd_t *global_data;
 "	l.jr	r13\n"		\
 "	l.nop\n"				\
 	: : "i"(offsetof(gd_t, jt)), "i"(XF_ ## x * sizeof(void *)) : "r13");
+#elif defined(CONFIG_ARC)
+/*
+ * r25 holds the pointer to the global_data. r10 is call clobbered.
+  */
+#define EXPORT_FUNC(x) \
+	asm volatile( \
+"	.align 4\n" \
+"	.globl " #x "\n" \
+#x ":\n" \
+"	ld	r10, [r25, %0]\n" \
+"	ld	r10, [r10, %1]\n" \
+"	j	[r10]\n" \
+	: : "i"(offsetof(gd_t, jt)), "i"(XF_ ## x * sizeof(void *)) : "r10");
 #else
 /*"	addi	$sp, $sp, -24\n"	\
 "	br	$r16\n"			\*/
diff --git a/fs/Makefile b/fs/Makefile
index 7e753e9dd2..18221658fc 100644
--- a/fs/Makefile
+++ b/fs/Makefile
@@ -6,26 +6,19 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)libfs.o
-
-COBJS-y				+= fs.o
-
-COBJS	:= $(COBJS-y)
-SRCS	:= $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-
-all:	$(LIB)
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+ifdef CONFIG_SPL_BUILD
+obj-$(CONFIG_SPL_FAT_SUPPORT) += fat/
+else
+obj-y				+= fs.o
+
+obj-$(CONFIG_CMD_CBFS) += cbfs/
+obj-$(CONFIG_CMD_CRAMFS) += cramfs/
+obj-$(CONFIG_FS_EXT4) += ext4/
+obj-y += fat/
+obj-$(CONFIG_CMD_JFFS2) += jffs2/
+obj-$(CONFIG_CMD_REISER) += reiserfs/
+obj-$(CONFIG_SANDBOX) += sandbox/
+obj-$(CONFIG_CMD_UBIFS) += ubifs/
+obj-$(CONFIG_YAFFS2) += yaffs2/
+obj-$(CONFIG_CMD_ZFS) += zfs/
+endif
diff --git a/fs/cbfs/Makefile b/fs/cbfs/Makefile
index 190fd8e561..a106e05dd8 100644
--- a/fs/cbfs/Makefile
+++ b/fs/cbfs/Makefile
@@ -3,26 +3,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)libcbfs.o
-
-COBJS-$(CONFIG_CMD_CBFS)	:= cbfs.o
-
-SRCS	:= $(COBJS-y:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS-y))
-
-all:	$(LIB)
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	:= cbfs.o
diff --git a/fs/cramfs/Makefile b/fs/cramfs/Makefile
index 9b1a3d78a3..12d73a375e 100644
--- a/fs/cramfs/Makefile
+++ b/fs/cramfs/Makefile
@@ -5,30 +5,5 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)libcramfs.o
-
-AOBJS	=
-COBJS-$(CONFIG_CMD_CRAMFS) := cramfs.o
-COBJS-$(CONFIG_CMD_CRAMFS) += uncompress.o
-
-SRCS	:= $(AOBJS:.o=.S) $(COBJS-y:.o=.c)
-OBJS	:= $(addprefix $(obj),$(AOBJS) $(COBJS-y))
-
-#CPPFLAGS +=
-
-all:	$(LIB) $(AOBJS)
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y := cramfs.o
+obj-y += uncompress.o
diff --git a/fs/ext4/Makefile b/fs/ext4/Makefile
index f45bb324ec..8d15bdad67 100644
--- a/fs/ext4/Makefile
+++ b/fs/ext4/Makefile
@@ -9,28 +9,5 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)libext4fs.o
-
-AOBJS	=
-COBJS-$(CONFIG_FS_EXT4) := ext4fs.o ext4_common.o dev.o
-COBJS-$(CONFIG_EXT4_WRITE) += ext4_write.o ext4_journal.o crc16.o
-
-SRCS	:= $(AOBJS:.o=.S) $(COBJS-y:.o=.c)
-OBJS	:= $(addprefix $(obj),$(AOBJS) $(COBJS-y))
-
-
-all:	$(LIB) $(AOBJS)
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y := ext4fs.o ext4_common.o dev.o
+obj-$(CONFIG_EXT4_WRITE) += ext4_write.o ext4_journal.o crc16.o
diff --git a/fs/ext4/dev.c b/fs/ext4/dev.c
index 787e04133a..e0b513a4ef 100644
--- a/fs/ext4/dev.c
+++ b/fs/ext4/dev.c
@@ -41,7 +41,7 @@ void ext4fs_set_blk_dev(block_dev_desc_t *rbdd, disk_partition_t *info)
 	get_fs()->dev_desc = rbdd;
 	part_info = info;
 	part_offset = info->start;
-	get_fs()->total_sect = (info->size * info->blksz) >>
+	get_fs()->total_sect = ((uint64_t)info->size * info->blksz) >>
 		get_fs()->dev_desc->log2blksz;
 }
 
diff --git a/fs/ext4/ext4_common.c b/fs/ext4/ext4_common.c
index 352943ec51..02da75c084 100644
--- a/fs/ext4/ext4_common.c
+++ b/fs/ext4/ext4_common.c
@@ -445,9 +445,9 @@ restart:
 					goto fail;
 				}
 				put_ext4(((uint64_t)
-					  (g_parent_inode->b.
+					  ((uint64_t)g_parent_inode->b.
 					   blocks.dir_blocks[direct_blk_idx] *
-					   fs->blksz)), zero_buffer, fs->blksz);
+					   (uint64_t)fs->blksz)), zero_buffer, fs->blksz);
 				g_parent_inode->size =
 				    g_parent_inode->size + fs->blksz;
 				g_parent_inode->blockcnt =
@@ -864,8 +864,8 @@ long int ext4fs_get_new_blk_no(void)
 		for (i = 0; i < fs->no_blkgrp; i++) {
 			if (bgd[i].free_blocks) {
 				if (bgd[i].bg_flags & EXT4_BG_BLOCK_UNINIT) {
-					put_ext4(((uint64_t) (bgd[i].block_id *
-							      fs->blksz)),
+					put_ext4(((uint64_t) ((uint64_t)bgd[i].block_id *
+							      (uint64_t)fs->blksz)),
 						 zero_buffer, fs->blksz);
 					bgd[i].bg_flags =
 					    bgd[i].
@@ -929,8 +929,8 @@ restart:
 
 		if (bgd[bg_idx].bg_flags & EXT4_BG_BLOCK_UNINIT) {
 			memset(zero_buffer, '\0', fs->blksz);
-			put_ext4(((uint64_t) (bgd[bg_idx].block_id *
-					fs->blksz)), zero_buffer, fs->blksz);
+			put_ext4(((uint64_t) ((uint64_t)bgd[bg_idx].block_id *
+					(uint64_t)fs->blksz)), zero_buffer, fs->blksz);
 			memcpy(fs->blk_bmaps[bg_idx], zero_buffer, fs->blksz);
 			bgd[bg_idx].bg_flags = bgd[bg_idx].bg_flags &
 						~EXT4_BG_BLOCK_UNINIT;
@@ -996,8 +996,8 @@ int ext4fs_get_new_inode_no(void)
 						bgd[i].free_inodes;
 				if (bgd[i].bg_flags & EXT4_BG_INODE_UNINIT) {
 					put_ext4(((uint64_t)
-						  (bgd[i].inode_id *
-							fs->blksz)),
+						  ((uint64_t)bgd[i].inode_id *
+							(uint64_t)fs->blksz)),
 						 zero_buffer, fs->blksz);
 					bgd[i].bg_flags = bgd[i].bg_flags &
 							~EXT4_BG_INODE_UNINIT;
@@ -1037,8 +1037,8 @@ restart:
 		ibmap_idx = fs->curr_inode_no / inodes_per_grp;
 		if (bgd[ibmap_idx].bg_flags & EXT4_BG_INODE_UNINIT) {
 			memset(zero_buffer, '\0', fs->blksz);
-			put_ext4(((uint64_t) (bgd[ibmap_idx].inode_id *
-					      fs->blksz)), zero_buffer,
+			put_ext4(((uint64_t) ((uint64_t)bgd[ibmap_idx].inode_id *
+					      (uint64_t)fs->blksz)), zero_buffer,
 				 fs->blksz);
 			bgd[ibmap_idx].bg_flags =
 			    bgd[ibmap_idx].bg_flags & ~EXT4_BG_INODE_UNINIT;
@@ -1143,7 +1143,7 @@ static void alloc_single_indirect_block(struct ext2_inode *file_inode,
 		}
 
 		/* write the block to disk */
-		put_ext4(((uint64_t) (si_blockno * fs->blksz)),
+		put_ext4(((uint64_t) ((uint64_t)si_blockno * (uint64_t)fs->blksz)),
 			 si_start_addr, fs->blksz);
 		file_inode->b.blocks.indir_block = si_blockno;
 	}
@@ -1242,7 +1242,7 @@ static void alloc_double_indirect_block(struct ext2_inode *file_inode,
 					break;
 			}
 			/* write the block  table */
-			put_ext4(((uint64_t) (di_blockno_child * fs->blksz)),
+			put_ext4(((uint64_t) ((uint64_t)di_blockno_child * (uint64_t)fs->blksz)),
 				 di_child_buff_start, fs->blksz);
 			free(di_child_buff_start);
 			di_child_buff_start = NULL;
@@ -1250,7 +1250,7 @@ static void alloc_double_indirect_block(struct ext2_inode *file_inode,
 			if (*total_remaining_blocks == 0)
 				break;
 		}
-		put_ext4(((uint64_t) (di_blockno_parent * fs->blksz)),
+		put_ext4(((uint64_t) ((uint64_t)di_blockno_parent * (uint64_t)fs->blksz)),
 			 di_block_start_addr, fs->blksz);
 		file_inode->b.blocks.double_indir_block = di_blockno_parent;
 	}
@@ -1348,8 +1348,8 @@ static void alloc_triple_indirect_block(struct ext2_inode *file_inode,
 						break;
 				}
 				/* write the child block */
-				put_ext4(((uint64_t) (ti_child_blockno *
-						      fs->blksz)),
+				put_ext4(((uint64_t) ((uint64_t)ti_child_blockno *
+						      (uint64_t)fs->blksz)),
 					 ti_cbuff_start_addr, fs->blksz);
 				free(ti_cbuff_start_addr);
 
@@ -1357,7 +1357,7 @@ static void alloc_triple_indirect_block(struct ext2_inode *file_inode,
 					break;
 			}
 			/* write the parent block */
-			put_ext4(((uint64_t) (ti_parent_blockno * fs->blksz)),
+			put_ext4(((uint64_t) ((uint64_t)ti_parent_blockno * (uint64_t)fs->blksz)),
 				 ti_pbuff_start_addr, fs->blksz);
 			free(ti_pbuff_start_addr);
 
@@ -1365,7 +1365,7 @@ static void alloc_triple_indirect_block(struct ext2_inode *file_inode,
 				break;
 		}
 		/* write the grand parent block */
-		put_ext4(((uint64_t) (ti_gp_blockno * fs->blksz)),
+		put_ext4(((uint64_t) ((uint64_t)ti_gp_blockno * (uint64_t)fs->blksz)),
 			 ti_gp_buff_start_addr, fs->blksz);
 		file_inode->b.blocks.triple_indir_block = ti_gp_blockno;
 	}
@@ -1414,7 +1414,7 @@ static struct ext4_extent_header *ext4fs_get_extent_block
 {
 	struct ext4_extent_idx *index;
 	unsigned long long block;
-	struct ext_filesystem *fs = get_fs();
+	int blksz = EXT2_BLOCK_SIZE(data);
 	int i;
 
 	while (1) {
@@ -1430,7 +1430,7 @@ static struct ext4_extent_header *ext4fs_get_extent_block
 			i++;
 			if (i >= le16_to_cpu(ext_block->eh_entries))
 				break;
-		} while (fileblock > le32_to_cpu(index[i].ei_block));
+		} while (fileblock >= le32_to_cpu(index[i].ei_block));
 
 		if (--i < 0)
 			return 0;
@@ -1438,7 +1438,7 @@ static struct ext4_extent_header *ext4fs_get_extent_block
 		block = le16_to_cpu(index[i].ei_leaf_hi);
 		block = (block << 32) + le32_to_cpu(index[i].ei_leaf_lo);
 
-		if (ext4fs_devread((lbaint_t)block << log2_blksz, 0, fs->blksz,
+		if (ext4fs_devread((lbaint_t)block << log2_blksz, 0, blksz,
 				   buf))
 			ext_block = (struct ext4_extent_header *)buf;
 		else
diff --git a/fs/ext4/ext4_journal.c b/fs/ext4/ext4_journal.c
index d4a46ed8b6..3f613351a4 100644
--- a/fs/ext4/ext4_journal.c
+++ b/fs/ext4/ext4_journal.c
@@ -371,7 +371,7 @@ void recover_transaction(int prev_desc_logical_no)
 		blknr = read_allocated_block(&inode_journal, i);
 		ext4fs_devread((lbaint_t)blknr * fs->sect_perblk, 0,
 			       fs->blksz, metadata_buff);
-		put_ext4((uint64_t)(be32_to_cpu(tag->block) * fs->blksz),
+		put_ext4((uint64_t)((uint64_t)be32_to_cpu(tag->block) * (uint64_t)fs->blksz),
 			 metadata_buff, (uint32_t) fs->blksz);
 	} while (!(flags & EXT3_JOURNAL_FLAG_LAST_TAG));
 fail:
@@ -531,7 +531,7 @@ end:
 
 		blknr = read_allocated_block(&inode_journal,
 					 EXT2_JOURNAL_SUPERBLOCK);
-		put_ext4((uint64_t) (blknr * fs->blksz),
+		put_ext4((uint64_t) ((uint64_t)blknr * (uint64_t)fs->blksz),
 			 (struct journal_superblock_t *)temp_buff,
 			 (uint32_t) fs->blksz);
 		ext4fs_free_revoke_blks();
@@ -590,7 +590,7 @@ static void update_descriptor_block(long int blknr)
 	tag.flags = cpu_to_be32(EXT3_JOURNAL_FLAG_LAST_TAG);
 	memcpy(temp - sizeof(struct ext3_journal_block_tag), &tag,
 	       sizeof(struct ext3_journal_block_tag));
-	put_ext4((uint64_t) (blknr * fs->blksz), buf, (uint32_t) fs->blksz);
+	put_ext4((uint64_t) ((uint64_t)blknr * (uint64_t)fs->blksz), buf, (uint32_t) fs->blksz);
 
 	free(temp_buff);
 	free(buf);
@@ -625,7 +625,7 @@ static void update_commit_block(long int blknr)
 		return;
 	}
 	memcpy(buf, &jdb, sizeof(struct journal_header_t));
-	put_ext4((uint64_t) (blknr * fs->blksz), buf, (uint32_t) fs->blksz);
+	put_ext4((uint64_t) ((uint64_t)blknr * (uint64_t)fs->blksz), buf, (uint32_t) fs->blksz);
 
 	free(temp_buff);
 	free(buf);
diff --git a/fs/ext4/ext4_write.c b/fs/ext4/ext4_write.c
index 1e1924c806..b674b6faeb 100644
--- a/fs/ext4/ext4_write.c
+++ b/fs/ext4/ext4_write.c
@@ -40,18 +40,18 @@ static void ext4fs_update(void)
 	/* update block groups */
 	for (i = 0; i < fs->no_blkgrp; i++) {
 		fs->bgd[i].bg_checksum = ext4fs_checksum_update(i);
-		put_ext4((uint64_t)(fs->bgd[i].block_id * fs->blksz),
+		put_ext4((uint64_t)((uint64_t)fs->bgd[i].block_id * (uint64_t)fs->blksz),
 			 fs->blk_bmaps[i], fs->blksz);
 	}
 
 	/* update inode table groups */
 	for (i = 0; i < fs->no_blkgrp; i++) {
-		put_ext4((uint64_t) (fs->bgd[i].inode_id * fs->blksz),
+		put_ext4((uint64_t) ((uint64_t)fs->bgd[i].inode_id * (uint64_t)fs->blksz),
 			 fs->inode_bmaps[i], fs->blksz);
 	}
 
 	/* update the block group descriptor table */
-	put_ext4((uint64_t)(fs->gdtable_blkno * fs->blksz),
+	put_ext4((uint64_t)((uint64_t)fs->gdtable_blkno * (uint64_t)fs->blksz),
 		 (struct ext2_block_group *)fs->gdtable,
 		 (fs->blksz * fs->no_blk_pergdt));
 
@@ -709,7 +709,7 @@ void ext4fs_deinit(void)
 			       temp_buff);
 		jsb = (struct journal_superblock_t *)temp_buff;
 		jsb->s_start = cpu_to_be32(0);
-		put_ext4((uint64_t) (blknr * fs->blksz),
+		put_ext4((uint64_t) ((uint64_t)blknr * (uint64_t)fs->blksz),
 			 (struct journal_superblock_t *)temp_buff, fs->blksz);
 		free(temp_buff);
 	}
@@ -793,7 +793,7 @@ static int ext4fs_write_file(struct ext2_inode *file_inode,
 					delayed_next += blockend >> log2blksz;
 				} else {	/* spill */
 					put_ext4((uint64_t)
-						 (delayed_start << log2blksz),
+						 ((uint64_t)delayed_start << log2blksz),
 						 delayed_buf,
 						 (uint32_t) delayed_extent);
 					previous_block_number = blknr;
@@ -814,7 +814,7 @@ static int ext4fs_write_file(struct ext2_inode *file_inode,
 		} else {
 			if (previous_block_number != -1) {
 				/* spill */
-				put_ext4((uint64_t) (delayed_start <<
+				put_ext4((uint64_t) ((uint64_t)delayed_start <<
 						     log2blksz),
 					 delayed_buf,
 					 (uint32_t) delayed_extent);
@@ -826,7 +826,7 @@ static int ext4fs_write_file(struct ext2_inode *file_inode,
 	}
 	if (previous_block_number != -1) {
 		/* spill */
-		put_ext4((uint64_t) (delayed_start << log2blksz),
+		put_ext4((uint64_t) ((uint64_t)delayed_start << log2blksz),
 			 delayed_buf, (uint32_t) delayed_extent);
 		previous_block_number = -1;
 	}
diff --git a/fs/ext4/ext4fs.c b/fs/ext4/ext4fs.c
index 735b256417..417ce7b63b 100644
--- a/fs/ext4/ext4fs.c
+++ b/fs/ext4/ext4fs.c
@@ -174,6 +174,14 @@ int ext4fs_ls(const char *dirname)
 	return 0;
 }
 
+int ext4fs_exists(const char *filename)
+{
+	int file_len;
+
+	file_len = ext4fs_open(filename);
+	return file_len >= 0;
+}
+
 int ext4fs_read(char *buf, unsigned len)
 {
 	if (ext4fs_root == NULL || ext4fs_file == NULL)
diff --git a/fs/fat/Makefile b/fs/fat/Makefile
index c00681f31b..b60e8486c4 100644
--- a/fs/fat/Makefile
+++ b/fs/fat/Makefile
@@ -3,34 +3,9 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)libfat.o
-
-AOBJS	=
-COBJS-$(CONFIG_FS_FAT)	:= fat.o
-COBJS-$(CONFIG_FAT_WRITE):= fat_write.o
+obj-$(CONFIG_FS_FAT)	:= fat.o
+obj-$(CONFIG_FAT_WRITE):= fat_write.o
 
 ifndef CONFIG_SPL_BUILD
-COBJS-$(CONFIG_FS_FAT)	+= file.o
+obj-$(CONFIG_FS_FAT)	+= file.o
 endif
-
-SRCS	:= $(AOBJS:.o=.S) $(COBJS-y:.o=.c)
-OBJS	:= $(addprefix $(obj),$(AOBJS) $(COBJS-y))
-
-all:	$(LIB) $(AOBJS)
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-# SEE README.arm-unaligned-accesses
-$(obj)file.o: CFLAGS += $(PLATFORM_NO_UNALIGNED)
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
diff --git a/fs/fat/fat.c b/fs/fat/fat.c
index b41d62e3c3..54f42eae0d 100644
--- a/fs/fat/fat.c
+++ b/fs/fat/fat.c
@@ -808,7 +808,7 @@ __u8 do_fat_read_at_block[MAX_CLUSTSIZE]
 
 long
 do_fat_read_at(const char *filename, unsigned long pos, void *buffer,
-	       unsigned long maxsize, int dols)
+	       unsigned long maxsize, int dols, int dogetsize)
 {
 	char fnamecopy[2048];
 	boot_sector bs;
@@ -1152,7 +1152,10 @@ rootdir_done:
 			subname = nextname;
 	}
 
-	ret = get_contents(mydata, dentptr, pos, buffer, maxsize);
+	if (dogetsize)
+		ret = FAT2CPU32(dentptr->size);
+	else
+		ret = get_contents(mydata, dentptr, pos, buffer, maxsize);
 	debug("Size: %d, got: %ld\n", FAT2CPU32(dentptr->size), ret);
 
 exit:
@@ -1163,7 +1166,7 @@ exit:
 long
 do_fat_read(const char *filename, void *buffer, unsigned long maxsize, int dols)
 {
-	return do_fat_read_at(filename, 0, buffer, maxsize, dols);
+	return do_fat_read_at(filename, 0, buffer, maxsize, dols, 0);
 }
 
 int file_fat_detectfs(void)
@@ -1233,11 +1236,18 @@ int file_fat_ls(const char *dir)
 	return do_fat_read(dir, NULL, 0, LS_YES);
 }
 
+int fat_exists(const char *filename)
+{
+	int sz;
+	sz = do_fat_read_at(filename, 0, NULL, 0, LS_NO, 1);
+	return sz >= 0;
+}
+
 long file_fat_read_at(const char *filename, unsigned long pos, void *buffer,
 		      unsigned long maxsize)
 {
 	printf("reading %s\n", filename);
-	return do_fat_read_at(filename, pos, buffer, maxsize, LS_NO);
+	return do_fat_read_at(filename, pos, buffer, maxsize, LS_NO, 0);
 }
 
 long file_fat_read(const char *filename, void *buffer, unsigned long maxsize)
diff --git a/fs/fat/fat_write.c b/fs/fat/fat_write.c
index b7a21e05bf..9f5e911852 100644
--- a/fs/fat/fat_write.c
+++ b/fs/fat/fat_write.c
@@ -57,7 +57,7 @@ static void set_name(dir_entry *dirent, const char *filename)
 	if (len == 0)
 		return;
 
-	memcpy(s_name, filename, len);
+	strcpy(s_name, filename);
 	uppercase(s_name, len);
 
 	period = strchr(s_name, '.');
diff --git a/fs/fdos/Makefile b/fs/fdos/Makefile
deleted file mode 100644
index 867c5cadfa..0000000000
--- a/fs/fdos/Makefile
+++ /dev/null
@@ -1,38 +0,0 @@
-#
-# (C) Copyright 2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# (C) Copyright 2002
-# Stäubli Faverges - <www.staubli.com>
-# Pierre AUBERT  p.aubert@staubli.com
-#
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)libfdos.o
-
-AOBJS	=
-COBJS-$(CONFIG_CMD_FDOS) := fat.o vfat.o dev.o fdos.o fs.o subdir.o
-
-SRCS	:= $(AOBJS:.o=.S) $(COBJS-y:.o=.c)
-OBJS	:= $(addprefix $(obj),$(AOBJS) $(COBJS-y))
-
-#CPPFLAGS +=
-
-all:	$(LIB) $(AOBJS)
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
diff --git a/fs/fdos/dev.c b/fs/fdos/dev.c
deleted file mode 100644
index 4c48663e09..0000000000
--- a/fs/fdos/dev.c
+++ /dev/null
@@ -1,174 +0,0 @@
-/*
- * (C) Copyright 2002
- * Stäubli Faverges - <www.staubli.com>
- * Pierre AUBERT  p.aubert@staubli.com
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <config.h>
-
-#include "dos.h"
-#include "fdos.h"
-
-#define NB_HEADS        2
-#define NB_TRACKS       80
-#define NB_SECTORS      18
-
-
-static int lastwhere;
-
-/*-----------------------------------------------------------------------------
- * dev_open --
- *-----------------------------------------------------------------------------
- */
-int dev_open (void)
-{
-    lastwhere = 0;
-    return (0);
-}
-
-/*-----------------------------------------------------------------------------
- * dev_read -- len and where are sectors number
- *-----------------------------------------------------------------------------
- */
-int dev_read (void *buffer, int where, int len)
-{
-    PRINTF ("dev_read (len = %d, where = %d)\n", len, where);
-
-    /* Si on ne desire pas lire a la position courante, il faut un seek      */
-    if (where != lastwhere) {
-	if (!fdc_fdos_seek (where)) {
-	    PRINTF ("seek error in dev_read");
-	    lastwhere = -1;
-	    return (-1);
-	}
-    }
-
-    if (!fdc_fdos_read (buffer, len)) {
-	PRINTF ("read error\n");
-	lastwhere = -1;
-	return (-1);
-    }
-    lastwhere = where + len;
-    return (0);
-}
-/*-----------------------------------------------------------------------------
- * check_dev -- verify the diskette format
- *-----------------------------------------------------------------------------
- */
-int check_dev (BootSector_t *boot, Fs_t *fs)
-{
-    unsigned int heads, sectors, tracks;
-    int BootP, Infp0, InfpX, InfTm;
-    int sect_per_track;
-
-    /* Display Boot header                                                   */
-    PRINTF ("Jump to boot code                  0x%02x 0x%02x 0x%02x\n",
-	    boot -> jump [0], boot -> jump [1], boot -> jump[2]);
-    PRINTF ("OEM name & version                 '%*.*s'\n",
-	    BANNER_LG, BANNER_LG, boot -> banner );
-    PRINTF ("Bytes per sector hopefully 512     %d\n",
-	    __le16_to_cpu (boot -> secsiz));
-    PRINTF ("Cluster size in sectors            %d\n",
-	    boot -> clsiz);
-    PRINTF ("Number of reserved (boot) sectors  %d\n",
-	    __le16_to_cpu (boot -> nrsvsect));
-    PRINTF ("Number of FAT tables hopefully 2   %d\n",
-	    boot -> nfat);
-    PRINTF ("Number of directory slots          %d\n",
-	    __le16_to_cpu (boot -> dirents));
-    PRINTF ("Total sectors on disk              %d\n",
-	    __le16_to_cpu (boot -> psect));
-    PRINTF ("Media descriptor=first byte of FAT %d\n",
-	    boot -> descr);
-    PRINTF ("Sectors in FAT                     %d\n",
-	    __le16_to_cpu (boot -> fatlen));
-    PRINTF ("Sectors/track                      %d\n",
-	    __le16_to_cpu (boot -> nsect));
-    PRINTF ("Heads                              %d\n",
-	    __le16_to_cpu (boot -> nheads));
-    PRINTF ("number of hidden sectors           %d\n",
-	    __le32_to_cpu (boot -> nhs));
-    PRINTF ("big total sectors                  %d\n",
-	    __le32_to_cpu (boot -> bigsect));
-    PRINTF ("physical drive ?                   %d\n",
-	    boot -> physdrive);
-    PRINTF ("reserved                           %d\n",
-	    boot -> reserved);
-    PRINTF ("dos > 4.0 diskette                 %d\n",
-	    boot -> dos4);
-    PRINTF ("serial number                      %d\n",
-	    __le32_to_cpu (boot -> serial));
-    PRINTF ("disk label                         %*.*s\n",
-	    LABEL_LG, LABEL_LG, boot -> label);
-    PRINTF ("FAT type                           %8.8s\n",
-	    boot -> fat_type);
-    PRINTF ("reserved by 2M                     %d\n",
-	    boot -> res_2m);
-    PRINTF ("2M checksum (not used)             %d\n",
-	    boot -> CheckSum);
-    PRINTF ("2MF format version                 %d\n",
-	    boot -> fmt_2mf);
-    PRINTF ("1 if write track after format      %d\n",
-	    boot -> wt);
-    PRINTF ("data transfer rate on track 0      %d\n",
-	    boot -> rate_0);
-    PRINTF ("data transfer rate on track<>0     %d\n",
-	    boot -> rate_any);
-    PRINTF ("offset to boot program             %d\n",
-	    __le16_to_cpu (boot -> BootP));
-    PRINTF ("T1: information for track 0        %d\n",
-	    __le16_to_cpu (boot -> Infp0));
-    PRINTF ("T2: information for track<>0       %d\n",
-	    __le16_to_cpu (boot -> InfpX));
-    PRINTF ("T3: track sectors size table       %d\n",
-	    __le16_to_cpu (boot -> InfTm));
-    PRINTF ("Format date                        0x%04x\n",
-	    __le16_to_cpu (boot -> DateF));
-    PRINTF ("Format time                        0x%04x\n",
-	    __le16_to_cpu (boot -> TimeF));
-
-
-    /* information is extracted from boot sector                           */
-    heads = __le16_to_cpu (boot -> nheads);
-    sectors = __le16_to_cpu (boot -> nsect);
-    fs -> tot_sectors = __le32_to_cpu (boot -> bigsect);
-    if (__le16_to_cpu (boot -> psect) != 0) {
-	fs -> tot_sectors = __le16_to_cpu (boot -> psect);
-    }
-
-    sect_per_track = heads * sectors;
-    tracks = (fs -> tot_sectors + sect_per_track - 1) / sect_per_track;
-
-    BootP = __le16_to_cpu (boot -> BootP);
-    Infp0 = __le16_to_cpu (boot -> Infp0);
-    InfpX = __le16_to_cpu (boot -> InfpX);
-    InfTm = __le16_to_cpu (boot -> InfTm);
-
-    if (boot -> dos4 == EXTENDED_BOOT &&
-	strncmp( boot->banner,"2M", 2 ) == 0 &&
-	BootP < SZ_STD_SECTOR &&
-	Infp0 < SZ_STD_SECTOR &&
-	InfpX < SZ_STD_SECTOR &&
-	InfTm < SZ_STD_SECTOR &&
-	BootP >= InfTm + 2 &&
-	InfTm >= InfpX &&
-	InfpX >= Infp0 &&
-	Infp0 >= 76 ) {
-
-	return (-1);
-    }
-
-    if (heads != NB_HEADS ||
-	tracks != NB_TRACKS ||
-	sectors != NB_SECTORS ||
-	__le16_to_cpu (boot -> secsiz) != SZ_STD_SECTOR ||
-	fs -> tot_sectors == 0 ||
-	(fs -> tot_sectors % sectors) != 0) {
-	return (-1);
-    }
-
-    return (0);
-}
diff --git a/fs/fdos/dos.h b/fs/fdos/dos.h
deleted file mode 100644
index b0b7d2aa06..0000000000
--- a/fs/fdos/dos.h
+++ /dev/null
@@ -1,159 +0,0 @@
-/*
- * (C) Copyright 2002
- * Stäubli Faverges - <www.staubli.com>
- * Pierre AUBERT  p.aubert@staubli.com
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef _DOS_H_
-#define _DOS_H_
-
-/* Definitions for Dos diskettes                                             */
-
-/* General definitions                                                       */
-#define SZ_STD_SECTOR   512             /* Standard sector size              */
-#define MDIR_SIZE	32		/* Direntry size                     */
-#define FAT_BITS        12              /* Diskette use 12 bits fat          */
-
-#define MAX_PATH	128		/* Max size of the MSDOS PATH        */
-#define MAX_DIR_SECS	64		/* Taille max d'un repertoire (en    */
-					/* secteurs)                         */
-/* Misc. definitions                                                         */
-#define DELMARK         '\xe5'
-#define EXTENDED_BOOT   (0x29)
-#define MEDIA_STD       (0xf0)
-#define JUMP_0_1        (0xe9)
-#define JUMP_0_2        (0xeb)
-
-/* Boot size is 256 bytes, but we need to read almost a sector, then
-   assume bootsize is 512                                                    */
-#define BOOTSIZE        512
-
-/* Fat definitions for 12 bits fat                                           */
-#define FAT12_MAX_NB    4086
-#define FAT12_LAST      0x0ff6
-#define FAT12_END       0x0fff
-
-/* file attributes                                                           */
-#define ATTR_READONLY           0x01
-#define ATTR_HIDDEN             0x02
-#define ATTR_SYSTEM             0x04
-#define ATTR_VOLUME             0x08
-#define ATTR_DIRECTORY          0x10
-#define ATTR_ARCHIVE            0x20
-#define ATTR_VSE                0x0f
-
-/* Name format                                                               */
-#define EXTCASE                 0x10
-#define BASECASE                0x8
-
-/* Definition of the boot sector                                             */
-#define BANNER_LG               8
-#define LABEL_LG                11
-
-typedef struct bootsector
-{
-    unsigned char jump [3];	/* 0  Jump to boot code                      */
-    char banner [BANNER_LG];	/* 3  OEM name & version                     */
-    unsigned short secsiz;	/* 11 Bytes per sector hopefully 512         */
-    unsigned char clsiz;	/* 13 Cluster size in sectors                */
-    unsigned short nrsvsect;	/* 14 Number of reserved (boot) sectors      */
-    unsigned char nfat;		/* 16 Number of FAT tables hopefully 2       */
-    unsigned short dirents;	/* 17 Number of directory slots              */
-    unsigned short psect;	/* 19 Total sectors on disk                  */
-    unsigned char descr;	/* 21 Media descriptor=first byte of FAT     */
-    unsigned short fatlen;	/* 22 Sectors in FAT                         */
-    unsigned short nsect;	/* 24 Sectors/track                          */
-    unsigned short nheads;	/* 26 Heads                                  */
-    unsigned int nhs;	        /* 28 number of hidden sectors               */
-    unsigned int bigsect;	/* 32 big total sectors                      */
-    unsigned char physdrive;	/* 36 physical drive ?                       */
-    unsigned char reserved;	/* 37 reserved                               */
-    unsigned char dos4;		/* 38 dos > 4.0 diskette                     */
-    unsigned int serial;        /* 39 serial number                          */
-    char label [LABEL_LG];	/* 43 disk label                             */
-    char fat_type [8];		/* 54 FAT type                               */
-    unsigned char res_2m;	/* 62 reserved by 2M                         */
-    unsigned char CheckSum;	/* 63 2M checksum (not used)                 */
-    unsigned char fmt_2mf;	/* 64 2MF format version                     */
-    unsigned char wt;		/* 65 1 if write track after format          */
-    unsigned char rate_0;	/* 66 data transfer rate on track 0          */
-    unsigned char rate_any;	/* 67 data transfer rate on track<>0         */
-    unsigned short BootP;	/* 68 offset to boot program                 */
-    unsigned short Infp0;	/* 70 T1: information for track 0            */
-    unsigned short InfpX;	/* 72 T2: information for track<>0           */
-    unsigned short InfTm;	/* 74 T3: track sectors size table           */
-    unsigned short DateF;	/* 76 Format date                            */
-    unsigned short TimeF;	/* 78 Format time                            */
-    unsigned char junk [BOOTSIZE - 80];	/* 80 remaining data                 */
-} __attribute__ ((packed)) BootSector_t;
-
-/* Structure d'une entree de repertoire                                      */
-typedef struct directory {
-    char name [8];		/* file name                                 */
-    char ext [3];		/* file extension                            */
-    unsigned char attr;		/* attribute byte                            */
-    unsigned char Case;		/* case of short filename                    */
-    unsigned char reserved [9];	/* ??                                        */
-    unsigned char time [2];	/* time stamp                                */
-    unsigned char date [2];	/* date stamp                                */
-    unsigned short start;	/* starting cluster number                   */
-    unsigned int size;	        /* size of the file                          */
-} __attribute__ ((packed))  Directory_t;
-
-
-#define MAX_VFAT_SUBENTRIES 20
-#define VSE_NAMELEN 13
-
-#define VSE1SIZE 5
-#define VSE2SIZE 6
-#define VSE3SIZE 2
-
-#define VBUFSIZE ((MAX_VFAT_SUBENTRIES * VSE_NAMELEN) + 1)
-
-#define MAX_VNAMELEN (255)
-
-#define VSE_PRESENT 0x01
-#define VSE_LAST 0x40
-#define VSE_MASK 0x1f
-
-/* Flag used by vfat_lookup                                                  */
-#define DO_OPEN         1
-#define ACCEPT_PLAIN    0x20
-#define ACCEPT_DIR      0x10
-#define ACCEPT_LABEL    0x08
-#define SINGLE          2
-#define MATCH_ANY       0x40
-
-struct vfat_subentry {
-    unsigned char id;		        /* VSE_LAST pour la fin, VSE_MASK    */
-					/* pour un VSE                       */
-    char text1 [VSE1SIZE * 2];          /* Caracteres encodes sur 16 bits    */
-    unsigned char attribute;	        /* 0x0f pour les VFAT                */
-    unsigned char hash1;		/* toujours 0                        */
-    unsigned char sum;		        /* Checksum du nom court             */
-    char text2 [VSE2SIZE * 2];          /* Caracteres encodes sur 16 bits    */
-    unsigned char sector_l;             /* 0 pour les VFAT                   */
-    unsigned char sector_u;		/* 0 pour les VFAT                   */
-    char text3 [VSE3SIZE * 2];          /* Caracteres encodes sur 16 bits    */
-} __attribute__ ((packed)) ;
-
-struct vfat_state {
-    char name [VBUFSIZE];
-    int status;             /* is now a bit map of 32 bits                   */
-    int subentries;
-    unsigned char sum;      /* no need to remember the sum for each          */
-			    /*   entry, it is the same anyways               */
-} __attribute__ ((packed)) ;
-
-/* Conversion macros                                                         */
-#define	DOS_YEAR(dir) (((dir)->date[1] >> 1) + 1980)
-#define	DOS_MONTH(dir) (((((dir)->date[1]&0x1) << 3) + ((dir)->date[0] >> 5)))
-#define	DOS_DAY(dir) ((dir)->date[0] & 0x1f)
-#define	DOS_HOUR(dir) ((dir)->time[1] >> 3)
-#define	DOS_MINUTE(dir) (((((dir)->time[1]&0x7) << 3) + ((dir)->time[0] >> 5)))
-#define	DOS_SEC(dir) (((dir)->time[0] & 0x1f) * 2)
-
-
-#endif
diff --git a/fs/fdos/fat.c b/fs/fdos/fat.c
deleted file mode 100644
index 408fec7600..0000000000
--- a/fs/fdos/fat.c
+++ /dev/null
@@ -1,122 +0,0 @@
-/*
- * (C) Copyright 2002
- * Stäubli Faverges - <www.staubli.com>
- * Pierre AUBERT  p.aubert@staubli.com
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <config.h>
-#include <malloc.h>
-
-#include "dos.h"
-#include "fdos.h"
-
-
-/*-----------------------------------------------------------------------------
- * fat_decode --
- *-----------------------------------------------------------------------------
- */
-unsigned int fat_decode (Fs_t *fs, unsigned int num)
-{
-    unsigned int start = num * 3 / 2;
-    unsigned char *address = fs -> fat_buf + start;
-
-    if (num < 2 || start + 1 > (fs -> fat_len * SZ_STD_SECTOR))
-	return 1;
-
-    if (num & 1)
-	return ((address [1] & 0xff) << 4) | ((address [0] & 0xf0 ) >> 4);
-    else
-	return ((address [1] & 0xf) << 8) | (address [0] & 0xff );
-}
-/*-----------------------------------------------------------------------------
- * check_fat --
- *-----------------------------------------------------------------------------
- */
-static int check_fat (Fs_t *fs)
-{
-    int i, f;
-
-    /* Cluster verification                                                  */
-    for (i = 3 ; i < fs -> num_clus; i++){
-	f = fat_decode (fs, i);
-	if (f < FAT12_LAST && f > fs -> num_clus){
-	    /* Wrong cluster number detected                                 */
-	    return (-1);
-	}
-    }
-    return (0);
-}
-/*-----------------------------------------------------------------------------
- * read_one_fat --
- *-----------------------------------------------------------------------------
- */
-static int read_one_fat (BootSector_t *boot, Fs_t *fs, int nfat)
-{
-    if (dev_read (fs -> fat_buf,
-		  (fs -> fat_start + nfat * fs -> fat_len),
-		  fs -> fat_len) < 0) {
-	return (-1);
-    }
-
-    if (fs -> fat_buf [0] || fs -> fat_buf [1] || fs -> fat_buf [2]) {
-	if ((fs -> fat_buf [0] != boot -> descr &&
-	     (fs -> fat_buf [0] != 0xf9 || boot -> descr != MEDIA_STD)) ||
-	    fs -> fat_buf [0] < MEDIA_STD){
-	    /* Unknown Media                                                 */
-	    return (-1);
-	}
-	if (fs -> fat_buf [1] != 0xff || fs -> fat_buf [2] != 0xff){
-	    /* FAT doesn't start with good values                            */
-	    return (-1);
-	}
-    }
-
-    if (fs -> num_clus >= FAT12_MAX_NB) {
-	/* Too much clusters                                                 */
-	return (-1);
-    }
-
-    return check_fat (fs);
-}
-/*-----------------------------------------------------------------------------
- * read_fat --
- *-----------------------------------------------------------------------------
- */
-int read_fat (BootSector_t *boot, Fs_t *fs)
-{
-    unsigned int buflen;
-    int i;
-
-    /* Allocate Fat Buffer                                                   */
-    buflen = fs -> fat_len * SZ_STD_SECTOR;
-    if (fs -> fat_buf) {
-	free (fs -> fat_buf);
-    }
-
-    if ((fs -> fat_buf = malloc (buflen)) == NULL) {
-	return (-1);
-    }
-
-    /* Try to read each Fat                                                  */
-    for (i = 0; i< fs -> nb_fat; i++){
-	if (read_one_fat (boot, fs, i) == 0) {
-	    /* Fat is OK                                                     */
-	    fs -> num_fat = i;
-	    break;
-	}
-    }
-
-    if (i == fs -> nb_fat){
-	return (-1);
-    }
-
-    if (fs -> fat_len > (((fs -> num_clus + 2) *
-			  (FAT_BITS / 4) -1 ) / 2 /
-			 SZ_STD_SECTOR + 1)) {
-	return (-1);
-    }
-    return (0);
-}
diff --git a/fs/fdos/fdos.c b/fs/fdos/fdos.c
deleted file mode 100644
index 4e2f479191..0000000000
--- a/fs/fdos/fdos.c
+++ /dev/null
@@ -1,156 +0,0 @@
-/*
- * (C) Copyright 2002
- * Stäubli Faverges - <www.staubli.com>
- * Pierre AUBERT  p.aubert@staubli.com
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <config.h>
-#include <malloc.h>
-
-#include "dos.h"
-#include "fdos.h"
-
-
-const char *month [] = {"Jan", "Feb", "Mar", "Apr", "May", "Jun", "Jul", "Aug", "Sep", "Oct", "Nov", "Dec"};
-
-Fs_t    fs;
-File_t  file;
-
-/*-----------------------------------------------------------------------------
- * dos_open --
- *-----------------------------------------------------------------------------
- */
-int dos_open(char *name)
-{
-    int lg;
-    int entry;
-    char *fname;
-
-    /* We need to suppress the " char around the name                        */
-    if (name [0] == '"') {
-	name ++;
-    }
-    lg = strlen (name);
-    if (name [lg - 1] == '"') {
-	name [lg - 1] = '\0';
-    }
-
-    /* Open file system                                                      */
-    if (fs_init (&fs) < 0) {
-	return -1;
-    }
-
-    /* Init the file descriptor                                              */
-    file.name = name;
-    file.fs = &fs;
-
-    /* find the subdirectory containing the file                             */
-    if (open_subdir (&file) < 0) {
-	return (-1);
-    }
-
-    fname = basename (name);
-
-    /* if we try to open root directory                                      */
-    if (*fname == '\0') {
-	file.file = file.subdir;
-	return (0);
-    }
-
-    /* find the file in the subdir                                           */
-    entry = 0;
-    if (vfat_lookup (&file.subdir,
-		     file.fs,
-		     &file.file.dir,
-		     &entry,
-		     0,
-		     fname,
-		     ACCEPT_DIR | ACCEPT_PLAIN | SINGLE | DO_OPEN,
-		     0,
-		     &file.file) != 0) {
-	/* File not found                                                    */
-	printf ("File not found\n");
-	return (-1);
-    }
-
-    return 0;
-}
-
-/*-----------------------------------------------------------------------------
- * dos_read --
- *-----------------------------------------------------------------------------
- */
-int dos_read (ulong addr)
-{
-    int read = 0, nb;
-
-    /* Try to boot a directory ?                                             */
-    if (file.file.dir.attr & (ATTR_DIRECTORY | ATTR_VOLUME)) {
-	printf ("Unable to boot %s !!\n", file.name);
-	return (-1);
-    }
-    while (read < file.file.FileSize) {
-	PRINTF ("read_file (%ld)\n", (file.file.FileSize - read));
-	nb = read_file (&fs,
-			&file.file,
-			(char *)addr + read,
-			read,
-			(file.file.FileSize - read));
-	PRINTF ("read_file -> %d\n", nb);
-	if (nb < 0) {
-	    printf ("read error\n");
-	    return (-1);
-	}
-	read += nb;
-    }
-    return (read);
-}
-/*-----------------------------------------------------------------------------
- * dos_dir --
- *-----------------------------------------------------------------------------
- */
-int dos_dir (void)
-{
-    int entry;
-    Directory_t dir;
-    char *name;
-
-
-    if ((file.file.dir.attr & ATTR_DIRECTORY) == 0) {
-	printf ("%s: not a directory !!\n", file.name);
-	return (1);
-    }
-    entry = 0;
-    if ((name = malloc (MAX_VNAMELEN + 1)) == NULL) {
-	PRINTF ("Allcation error\n");
-	return (1);
-    }
-
-    while (vfat_lookup (&file.file,
-			file.fs,
-			&dir,
-			&entry,
-			0,
-			NULL,
-			ACCEPT_DIR | ACCEPT_PLAIN | MATCH_ANY,
-			name,
-			NULL) == 0) {
-	/* Display file info                                                 */
-	printf ("%3.3s %9d %s %02d %04d %02d:%02d:%02d %s\n",
-		(dir.attr & ATTR_DIRECTORY) ? "dir" : "   ",
-		__le32_to_cpu (dir.size),
-		month [DOS_MONTH (&dir) - 1],
-		DOS_DAY (&dir),
-		DOS_YEAR (&dir),
-		DOS_HOUR (&dir),
-		DOS_MINUTE (&dir),
-		DOS_SEC (&dir),
-		name);
-
-    }
-    free (name);
-    return (0);
-}
diff --git a/fs/fdos/fdos.h b/fs/fdos/fdos.h
deleted file mode 100644
index 2d8fe9d13d..0000000000
--- a/fs/fdos/fdos.h
+++ /dev/null
@@ -1,100 +0,0 @@
-/*
- * (C) Copyright 2002
- * Stäubli Faverges - <www.staubli.com>
- * Pierre AUBERT  p.aubert@staubli.com
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef _FDOS_H_
-#define _FDOS_H_
-
-
-#undef	FDOS_DEBUG
-
-#ifdef	FDOS_DEBUG
-#define	PRINTF(fmt,args...)	printf (fmt ,##args)
-#else
-#define PRINTF(fmt,args...)
-#endif
-
-/* Data structure describing media                                           */
-typedef struct fs
-{
-    unsigned long       tot_sectors;
-
-    int                 cluster_size;
-    int                 num_clus;
-
-    int                 fat_start;
-    int                 fat_len;
-    int                 nb_fat;
-    int                 num_fat;
-
-    int                 dir_start;
-    int                 dir_len;
-
-    unsigned char       *fat_buf;
-
-} Fs_t;
-
-/* Data structure describing one file system slot                            */
-typedef struct slot {
-    int (*map) (struct fs *fs,
-		struct slot *file,
-		int where,
-		int *len);
-    unsigned long FileSize;
-
-    unsigned short int FirstAbsCluNr;
-    unsigned short int PreviousAbsCluNr;
-    unsigned short int PreviousRelCluNr;
-
-    Directory_t dir;
-} Slot_t;
-
-typedef struct file {
-    char                *name;
-    int                 Case;
-    Fs_t                *fs;
-    Slot_t              subdir;
-    Slot_t              file;
-} File_t;
-
-
-/* dev.c                                                                     */
-int dev_read (void *buffer, int where, int len);
-int dev_open (void);
-int check_dev (BootSector_t *boot, Fs_t *fs);
-
-/* fat.c                                                                     */
-unsigned int fat_decode (Fs_t *fs, unsigned int num);
-int read_fat (BootSector_t *boot, Fs_t *fs);
-
-/* vfat.c                                                                    */
-int vfat_lookup (Slot_t *dir,
-		 Fs_t *fs,
-		 Directory_t *dirent,
-		 int *entry,
-		 int *vfat_start,
-		 char *filename,
-		 int flags,
-		 char *outname,
-		 Slot_t *file);
-
-/* subdir.c                                                                  */
-char *basename (char *name);
-int open_subdir (File_t *desc);
-int open_file (Slot_t *file, Directory_t *dir);
-int read_file (Fs_t *fs,
-	       Slot_t *file,
-	       char *buf,
-	       int where,
-	       int len);
-void init_subdir (void);
-
-/* fs.c                                                                      */
-int fs_init (Fs_t *fs);
-
-
-#endif
diff --git a/fs/fdos/fs.c b/fs/fdos/fs.c
deleted file mode 100644
index 39d3eae20d..0000000000
--- a/fs/fdos/fs.c
+++ /dev/null
@@ -1,98 +0,0 @@
-/*
- * (C) Copyright 2002
- * Stäubli Faverges - <www.staubli.com>
- * Pierre AUBERT  p.aubert@staubli.com
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <config.h>
-#include <malloc.h>
-
-#include "dos.h"
-#include "fdos.h"
-
-
-/*-----------------------------------------------------------------------------
- * fill_fs -- Read info on file system
- *-----------------------------------------------------------------------------
- */
-static int fill_fs (BootSector_t *boot, Fs_t *fs)
-{
-
-    fs -> fat_start = __le16_to_cpu (boot -> nrsvsect);
-    fs -> fat_len = __le16_to_cpu (boot -> fatlen);
-    fs -> nb_fat = boot -> nfat;
-
-    fs -> dir_start = fs -> fat_start + fs -> nb_fat * fs -> fat_len;
-    fs -> dir_len = __le16_to_cpu (boot -> dirents) * MDIR_SIZE / SZ_STD_SECTOR;
-    fs -> cluster_size = boot -> clsiz;
-    fs -> num_clus = (fs -> tot_sectors - fs -> dir_start - fs -> dir_len) / fs -> cluster_size;
-
-    return (0);
-}
-
-/*-----------------------------------------------------------------------------
- * fs_init --
- *-----------------------------------------------------------------------------
- */
-int fs_init (Fs_t *fs)
-{
-    BootSector_t *boot;
-
-    /* Initialize physical device                                            */
-    if (dev_open () < 0) {
-	PRINTF ("Unable to initialize the fdc\n");
-	return (-1);
-    }
-    init_subdir ();
-
-    /* Allocate space for read the boot sector                               */
-    if ((boot = (BootSector_t *)malloc (sizeof (BootSector_t))) == NULL) {
-	PRINTF ("Unable to allocate space for boot sector\n");
-	return (-1);
-    }
-
-    /* read boot sector                                                      */
-    if (dev_read (boot, 0, 1)){
-	PRINTF ("Error during boot sector read\n");
-	free (boot);
-	return (-1);
-    }
-
-    /* we verify it'a a DOS diskette                                         */
-    if (boot -> jump [0] !=  JUMP_0_1 && boot -> jump [0] !=  JUMP_0_2) {
-	PRINTF ("Not a DOS diskette\n");
-	free (boot);
-	return (-1);
-    }
-
-    if (boot -> descr < MEDIA_STD) {
-	/* We handle only recent medias (type F0)                            */
-	PRINTF ("unrecognized diskette type\n");
-	free (boot);
-	return (-1);
-    }
-
-    if (check_dev (boot, fs) < 0) {
-	PRINTF ("Bad diskette\n");
-	free (boot);
-	return (-1);
-    }
-
-    if (fill_fs (boot, fs) < 0) {
-	free (boot);
-
-	return (-1);
-    }
-
-    /* Read FAT                                                              */
-    if (read_fat (boot, fs) < 0) {
-	free (boot);
-	return (-1);
-    }
-
-    free (boot);
-    return (0);
-}
diff --git a/fs/fdos/subdir.c b/fs/fdos/subdir.c
deleted file mode 100644
index 97f6fb7102..0000000000
--- a/fs/fdos/subdir.c
+++ /dev/null
@@ -1,329 +0,0 @@
-/*
- * (C) Copyright 2002
- * Stäubli Faverges - <www.staubli.com>
- * Pierre AUBERT  p.aubert@staubli.com
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <config.h>
-#include <malloc.h>
-
-#include "dos.h"
-#include "fdos.h"
-
-static int cache_sect;
-static unsigned char cache [SZ_STD_SECTOR];
-
-
-#define min(x,y) ((x)<(y)?(x):(y))
-
-static int descend (Slot_t *parent,
-	     Fs_t *fs,
-		    char *path);
-
-/*-----------------------------------------------------------------------------
- * init_subdir --
- *-----------------------------------------------------------------------------
- */
-void init_subdir (void)
-{
-    cache_sect = -1;
-}
-/*-----------------------------------------------------------------------------
- * basename --
- *-----------------------------------------------------------------------------
- */
-char *basename (char *name)
-{
-    register char *cptr;
-
-    if (!name || !*name) {
-	return ("");
-    }
-
-    for (cptr= name; *cptr++; );
-    while (--cptr >= name) {
-	if (*cptr == '/')    {
-	    return (cptr + 1);
-	}
-    }
-    return(name);
-}
-/*-----------------------------------------------------------------------------
- * root_map --
- *-----------------------------------------------------------------------------
- */
-static int root_map (Fs_t *fs, Slot_t *file, int where, int *len)
-{
-    *len = min (*len, fs -> dir_len * SZ_STD_SECTOR - where);
-    if (*len < 0 ) {
-	*len = 0;
-	return (-1);
-    }
-    return fs -> dir_start * SZ_STD_SECTOR + where;
-}
-/*-----------------------------------------------------------------------------
- * normal_map --
- *-----------------------------------------------------------------------------
- */
-static int normal_map (Fs_t *fs, Slot_t *file, int where, int *len)
-{
-    int offset;
-    int NrClu;
-    unsigned short RelCluNr;
-    unsigned short CurCluNr;
-    unsigned short NewCluNr;
-    unsigned short AbsCluNr;
-    int clus_size;
-
-    clus_size = fs -> cluster_size * SZ_STD_SECTOR;
-    offset = where % clus_size;
-
-    *len = min (*len, file -> FileSize - where);
-
-    if (*len < 0 ) {
-	*len = 0;
-	return (0);
-    }
-
-    if (file -> FirstAbsCluNr < 2){
-	*len = 0;
-	return (0);
-    }
-
-    RelCluNr = where / clus_size;
-
-    if (RelCluNr >= file -> PreviousRelCluNr){
-	CurCluNr = file -> PreviousRelCluNr;
-	AbsCluNr = file -> PreviousAbsCluNr;
-    } else {
-	CurCluNr = 0;
-	AbsCluNr = file -> FirstAbsCluNr;
-    }
-
-
-    NrClu = (offset + *len - 1) / clus_size;
-    while (CurCluNr <= RelCluNr + NrClu) {
-	if (CurCluNr == RelCluNr){
-	    /* we have reached the beginning of our zone. Save
-	     * coordinates */
-	    file -> PreviousRelCluNr = RelCluNr;
-	    file -> PreviousAbsCluNr = AbsCluNr;
-	}
-	NewCluNr = fat_decode (fs, AbsCluNr);
-	if (NewCluNr == 1 || NewCluNr == 0) {
-	    PRINTF("Fat problem while decoding %d %x\n",
-		    AbsCluNr, NewCluNr);
-	    return (-1);
-	}
-	if (CurCluNr == RelCluNr + NrClu) {
-	    break;
-	}
-
-	if (CurCluNr < RelCluNr && NewCluNr == FAT12_END) {
-	    *len = 0;
-	    return 0;
-	}
-
-	if (CurCluNr >= RelCluNr && NewCluNr != AbsCluNr + 1)
-	    break;
-	CurCluNr++;
-	AbsCluNr = NewCluNr;
-    }
-
-    *len = min (*len, (1 + CurCluNr - RelCluNr) * clus_size - offset);
-
-    return (((file -> PreviousAbsCluNr - 2) * fs -> cluster_size +
-	     fs -> dir_start + fs -> dir_len) *
-	    SZ_STD_SECTOR + offset);
-}
-/*-----------------------------------------------------------------------------
- * open_subdir -- open the subdir containing the file
- *-----------------------------------------------------------------------------
- */
-int open_subdir (File_t *desc)
-{
-    char *pathname;
-    char *tmp, *s, *path;
-    char terminator;
-
-    if ((pathname = (char *)malloc (MAX_PATH)) == NULL) {
-	return (-1);
-    }
-
-    strcpy (pathname, desc -> name);
-
-    /* Suppress file name                                                    */
-    tmp = basename (pathname);
-    *tmp = '\0';
-
-    /* root directory  init                                                  */
-    desc -> subdir.FirstAbsCluNr = 0;
-    desc -> subdir.FileSize = -1;
-    desc -> subdir.map = root_map;
-    desc -> subdir.dir.attr = ATTR_DIRECTORY;
-
-    tmp = pathname;
-    for (s = tmp; ; ++s) {
-	if (*s == '/' || *s == '\0') {
-	    path = tmp;
-	    terminator = *s;
-	    *s = '\0';
-	    if (s != tmp && strcmp (path,".")) {
-		if (descend (&desc -> subdir, desc -> fs, path) < 0) {
-		    free (pathname);
-		    return (-1);
-		}
-	    }
-	    if (terminator == 0) {
-		break;
-	    }
-	    tmp = s + 1;
-	}
-    }
-    free (pathname);
-    return (0);
-}
-/*-----------------------------------------------------------------------------
- * descend --
- *-----------------------------------------------------------------------------
- */
-static int descend (Slot_t *parent,
-	     Fs_t *fs,
-	     char *path)
-{
-    int entry;
-    Slot_t SubDir;
-
-    if(path[0] == '\0' || strcmp (path, ".") == 0) {
-	return (0);
-    }
-
-
-    entry = 0;
-    if (vfat_lookup (parent,
-		     fs,
-		     &(SubDir.dir),
-		     &entry,
-		     0,
-		     path,
-		     ACCEPT_DIR | SINGLE | DO_OPEN,
-		     0,
-		     &SubDir) == 0) {
-	*parent = SubDir;
-	return (0);
-    }
-
-    if (strcmp(path, "..") == 0) {
-	parent -> FileSize = -1;
-	parent -> FirstAbsCluNr = 0;
-	parent -> map = root_map;
-	return (0);
-    }
-    return (-1);
-}
-/*-----------------------------------------------------------------------------
- * open_file --
- *-----------------------------------------------------------------------------
- */
-int open_file (Slot_t *file, Directory_t *dir)
-{
-    int first;
-    unsigned long size;
-
-    first = __le16_to_cpu (dir -> start);
-
-    if(first == 0 &&
-       (dir -> attr & ATTR_DIRECTORY) != 0) {
-	file -> FirstAbsCluNr = 0;
-	file -> FileSize = -1;
-	file -> map = root_map;
-	return (0);
-    }
-
-    if ((dir -> attr & ATTR_DIRECTORY) != 0) {
-	size = (1UL << 31) - 1;
-    }
-    else {
-	size = __le32_to_cpu (dir -> size);
-    }
-
-    file -> map = normal_map;
-    file -> FirstAbsCluNr = first;
-    file -> PreviousRelCluNr = 0xffff;
-    file -> FileSize = size;
-    return (0);
-}
-/*-----------------------------------------------------------------------------
- * read_file --
- *-----------------------------------------------------------------------------
- */
-int read_file (Fs_t *fs,
-	       Slot_t *file,
-	       char *buf,
-	       int where,
-	       int len)
-{
-    int pos;
-    int read, nb, sect, offset;
-
-    pos = file -> map (fs, file, where, &len);
-    if  (pos < 0) {
-	return -1;
-    }
-    if (len == 0) {
-	return (0);
-    }
-
-    /* Compute sector number                                                 */
-    sect = pos / SZ_STD_SECTOR;
-    offset = pos % SZ_STD_SECTOR;
-    read = 0;
-
-    if (offset) {
-	/* Read doesn't start at the sector beginning. We need to use our    */
-	/* cache                                                             */
-	if (sect != cache_sect) {
-	    if (dev_read (cache, sect, 1) < 0) {
-		return (-1);
-	    }
-	    cache_sect = sect;
-	}
-	nb = min (len, SZ_STD_SECTOR - offset);
-
-	memcpy (buf, cache + offset, nb);
-	read += nb;
-	len -= nb;
-	sect += 1;
-    }
-
-    if (len > SZ_STD_SECTOR) {
-	nb = (len - 1) / SZ_STD_SECTOR;
-	if (dev_read (buf + read, sect, nb) < 0) {
-	    return ((read) ? read : -1);
-	}
-	/* update sector position                                            */
-	sect += nb;
-
-	/* Update byte position                                              */
-	nb *= SZ_STD_SECTOR;
-	read += nb;
-	len -= nb;
-    }
-
-    if (len) {
-	if (sect != cache_sect) {
-	    if (dev_read (cache, sect, 1) < 0) {
-		return ((read) ? read : -1);
-		cache_sect = -1;
-	    }
-	    cache_sect = sect;
-	}
-
-	memcpy (buf + read, cache, len);
-	read += len;
-    }
-    return (read);
-}
diff --git a/fs/fdos/vfat.c b/fs/fdos/vfat.c
deleted file mode 100644
index 2b87d0f5a7..0000000000
--- a/fs/fdos/vfat.c
+++ /dev/null
@@ -1,336 +0,0 @@
-/*
- * (C) Copyright 2002
- * Stäubli Faverges - <www.staubli.com>
- * Pierre AUBERT  p.aubert@staubli.com
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <config.h>
-#include <linux/ctype.h>
-
-#include "dos.h"
-#include "fdos.h"
-
-static int dir_read (Fs_t *fs,
-		     Slot_t *dir,
-		     Directory_t *dirent,
-		     int num,
-		     struct vfat_state *v);
-
-static int unicode_read (char *in, char *out, int num);
-static int match (const char *s, const char *p);
-static unsigned char sum_shortname (char *name);
-static int check_vfat (struct vfat_state *v, Directory_t *dir);
-static char *conv_name (char *name, char *ext, char Case, char *ans);
-
-
-/*-----------------------------------------------------------------------------
- * clear_vfat --
- *-----------------------------------------------------------------------------
- */
-static void clear_vfat (struct vfat_state *v)
-{
-    v -> subentries = 0;
-    v -> status = 0;
-}
-
-/*-----------------------------------------------------------------------------
- * vfat_lookup --
- *-----------------------------------------------------------------------------
- */
-int vfat_lookup (Slot_t *dir,
-		 Fs_t *fs,
-		 Directory_t *dirent,
-		 int *entry,
-		 int *vfat_start,
-		 char *filename,
-		 int flags,
-		 char *outname,
-		 Slot_t *file)
-{
-    int found;
-    struct vfat_state vfat;
-    char newfile [VSE_NAMELEN];
-    int vfat_present = 0;
-
-    if (*entry == -1) {
-	return -1;
-    }
-
-    found = 0;
-    clear_vfat (&vfat);
-    while (1) {
-	if (dir_read (fs, dir, dirent, *entry, &vfat) < 0) {
-	    if (vfat_start) {
-		*vfat_start = *entry;
-	    }
-	    break;
-	}
-	(*entry)++;
-
-	/* Empty slot                                                        */
-	if (dirent -> name[0] == '\0'){
-	    if (vfat_start == 0) {
-		break;
-	    }
-	    continue;
-	}
-
-	if (dirent -> attr == ATTR_VSE) {
-	    /* VSE entry, continue                                           */
-	    continue;
-	}
-	if ( (dirent -> name [0] == DELMARK) ||
-	     ((dirent -> attr & ATTR_DIRECTORY) != 0 &&
-	      (flags & ACCEPT_DIR) == 0) ||
-	     ((dirent -> attr & ATTR_VOLUME) != 0 &&
-	      (flags & ACCEPT_LABEL) == 0) ||
-	     (((dirent -> attr & (ATTR_DIRECTORY | ATTR_VOLUME)) == 0) &&
-	      (flags & ACCEPT_PLAIN) == 0)) {
-	    clear_vfat (&vfat);
-	    continue;
-	}
-
-	vfat_present = check_vfat (&vfat, dirent);
-	if (vfat_start) {
-	    *vfat_start = *entry - 1;
-	    if (vfat_present) {
-		*vfat_start -= vfat.subentries;
-	    }
-	}
-
-	if (dirent -> attr & ATTR_VOLUME) {
-	    strncpy (newfile, dirent -> name, 8);
-	    newfile [8] = '\0';
-	    strncat (newfile, dirent -> ext, 3);
-	    newfile [11] = '\0';
-	}
-	else {
-	    conv_name (dirent -> name, dirent -> ext, dirent -> Case, newfile);
-	}
-
-	if (flags & MATCH_ANY) {
-	    found = 1;
-	    break;
-	}
-
-	if ((vfat_present && match (vfat.name, filename)) ||
-	    (match (newfile, filename))) {
-	    found = 1;
-	    break;
-	}
-	clear_vfat (&vfat);
-    }
-
-    if (found) {
-	if ((flags & DO_OPEN) && file) {
-	    if (open_file (file, dirent) < 0) {
-		return (-1);
-	    }
-	}
-	if (outname) {
-	    if (vfat_present) {
-		strcpy (outname, vfat.name);
-	    }
-	    else {
-		strcpy (outname, newfile);
-	    }
-	}
-	return (0);                    /* File found                         */
-    } else {
-	*entry = -1;
-	return -1;                      /* File not found                    */
-    }
-}
-
-/*-----------------------------------------------------------------------------
- * dir_read -- Read one directory entry
- *-----------------------------------------------------------------------------
- */
-static int dir_read (Fs_t *fs,
-	      Slot_t *dir,
-	      Directory_t *dirent,
-	      int num,
-	      struct vfat_state *v)
-{
-
-    /* read the directory entry                                              */
-    if (read_file (fs,
-		   dir,
-		   (char *)dirent,
-		   num * MDIR_SIZE,
-		   MDIR_SIZE) != MDIR_SIZE) {
-	return (-1);
-    }
-
-    if (v && (dirent -> attr == ATTR_VSE)) {
-	struct vfat_subentry *vse;
-	unsigned char id, last_flag;
-	char *c;
-
-	vse = (struct vfat_subentry *) dirent;
-	id = vse -> id & VSE_MASK;
-	last_flag = (vse -> id & VSE_LAST);
-	if (id > MAX_VFAT_SUBENTRIES) {
-	    /* Invalid VSE entry                                             */
-	    return (-1);
-	}
-
-
-	/* Decode VSE                                                        */
-	if(v -> sum != vse -> sum) {
-	    clear_vfat (v);
-	    v -> sum = vse -> sum;
-	}
-
-
-	v -> status |= 1 << (id - 1);
-	if (last_flag) {
-	    v -> subentries = id;
-	}
-
-	c = &(v -> name [VSE_NAMELEN * (id - 1)]);
-	c += unicode_read (vse->text1, c, VSE1SIZE);
-	c += unicode_read (vse->text2, c, VSE2SIZE);
-	c += unicode_read (vse->text3, c, VSE3SIZE);
-
-	if (last_flag) {
-	    *c = '\0';	        /* Null terminate long name                  */
-	}
-
-    }
-    return (0);
-}
-
-/*-----------------------------------------------------------------------------
- * unicode_read --
- *-----------------------------------------------------------------------------
- */
-static int unicode_read (char *in, char *out, int num)
-{
-    int j;
-
-    for (j = 0; j < num; ++j) {
-	if (in [1])
-	    *out = '_';
-	else
-	    *out = in [0];
-	out ++;
-	in += 2;
-    }
-    return num;
-}
-
-/*-----------------------------------------------------------------------------
- * match --
- *-----------------------------------------------------------------------------
- */
-static int match (const char *s, const char *p)
-{
-
-    for (; *p != '\0'; ) {
-	if (toupper (*s) != toupper (*p)) {
-	    return (0);
-	}
-	p++;
-	s++;
-    }
-
-    if (*s != '\0') {
-	return (0);
-    }
-    else {
-	return (1);
-    }
-}
-/*-----------------------------------------------------------------------------
- * sum_shortname --
- *-----------------------------------------------------------------------------
- */
-static unsigned char sum_shortname (char *name)
-{
-    unsigned char sum;
-    int j;
-
-    for (j = sum = 0; j < 11; ++j) {
-	sum = ((sum & 1) ? 0x80 : 0) + (sum >> 1) +
-	    (name [j] ? name [j] : ' ');
-    }
-    return (sum);
-}
-/*-----------------------------------------------------------------------------
- * check_vfat --
- * Return 1 if long name is valid, 0 else
- *-----------------------------------------------------------------------------
- */
-static int check_vfat (struct vfat_state *v, Directory_t *dir)
-{
-    char name[12];
-
-    if (v -> subentries == 0) {
-	return 0;
-    }
-
-    strncpy (name, dir -> name, 8);
-    strncpy (name + 8, dir -> ext, 3);
-    name [11] = '\0';
-
-    if (v -> sum != sum_shortname (name)) {
-	return 0;
-    }
-
-    if( (v -> status & ((1 << v -> subentries) - 1)) !=
-	(1 << v -> subentries) - 1) {
-	return 0;
-    }
-    v->name [VSE_NAMELEN * v -> subentries] = 0;
-
-    return 1;
-}
-/*-----------------------------------------------------------------------------
- * conv_name --
- *-----------------------------------------------------------------------------
- */
-static char *conv_name (char *name, char *ext, char Case, char *ans)
-{
-    char tname [9], text [4];
-    int i;
-
-    i = 0;
-    while (i < 8 && name [i] != ' ' && name [i] != '\0') {
-	tname [i] = name [i];
-	i++;
-    }
-    tname [i] = '\0';
-
-    if (Case & BASECASE) {
-	for (i = 0; i < 8 && tname [i]; i++) {
-	    tname [i] = tolower (tname [i]);
-	}
-    }
-
-    i = 0;
-    while (i < 3 && ext [i] != ' ' && ext [i] != '\0') {
-	text [i] = ext [i];
-	i++;
-    }
-    text [i] = '\0';
-
-    if (Case & EXTCASE){
-	for (i = 0; i < 3 && text [i]; i++) {
-	    text [i] = tolower (text [i]);
-	}
-    }
-
-    if (*text) {
-	strcpy (ans, tname);
-	strcat (ans, ".");
-	strcat (ans, text);
-    }
-    else {
-	strcpy(ans, tname);
-    }
-    return (ans);
-}
diff --git a/fs/fs.c b/fs/fs.c
index be1855d129..79d432d58f 100644
--- a/fs/fs.c
+++ b/fs/fs.c
@@ -41,6 +41,11 @@ static inline int fs_ls_unsupported(const char *dirname)
 	return -1;
 }
 
+static inline int fs_exists_unsupported(const char *filename)
+{
+	return 0;
+}
+
 static inline int fs_read_unsupported(const char *filename, void *buf,
 				      int offset, int len)
 {
@@ -59,9 +64,19 @@ static inline void fs_close_unsupported(void)
 
 struct fstype_info {
 	int fstype;
+	/*
+	 * Is it legal to pass NULL as .probe()'s  fs_dev_desc parameter? This
+	 * should be false in most cases. For "virtual" filesystems which
+	 * aren't based on a U-Boot block device (e.g. sandbox), this can be
+	 * set to true. This should also be true for the dumm entry at the end
+	 * of fstypes[], since that is essentially a "virtual" (non-existent)
+	 * filesystem.
+	 */
+	bool null_dev_desc_ok;
 	int (*probe)(block_dev_desc_t *fs_dev_desc,
 		     disk_partition_t *fs_partition);
 	int (*ls)(const char *dirname);
+	int (*exists)(const char *filename);
 	int (*read)(const char *filename, void *buf, int offset, int len);
 	int (*write)(const char *filename, void *buf, int offset, int len);
 	void (*close)(void);
@@ -71,36 +86,46 @@ static struct fstype_info fstypes[] = {
 #ifdef CONFIG_FS_FAT
 	{
 		.fstype = FS_TYPE_FAT,
+		.null_dev_desc_ok = false,
 		.probe = fat_set_blk_dev,
 		.close = fat_close,
 		.ls = file_fat_ls,
+		.exists = fat_exists,
 		.read = fat_read_file,
+		.write = fs_write_unsupported,
 	},
 #endif
 #ifdef CONFIG_FS_EXT4
 	{
 		.fstype = FS_TYPE_EXT,
+		.null_dev_desc_ok = false,
 		.probe = ext4fs_probe,
 		.close = ext4fs_close,
 		.ls = ext4fs_ls,
+		.exists = ext4fs_exists,
 		.read = ext4_read_file,
+		.write = fs_write_unsupported,
 	},
 #endif
 #ifdef CONFIG_SANDBOX
 	{
 		.fstype = FS_TYPE_SANDBOX,
+		.null_dev_desc_ok = true,
 		.probe = sandbox_fs_set_blk_dev,
 		.close = sandbox_fs_close,
 		.ls = sandbox_fs_ls,
+		.exists = sandbox_fs_exists,
 		.read = fs_read_sandbox,
 		.write = fs_write_sandbox,
 	},
 #endif
 	{
 		.fstype = FS_TYPE_ANY,
+		.null_dev_desc_ok = true,
 		.probe = fs_probe_unsupported,
 		.close = fs_close_unsupported,
 		.ls = fs_ls_unsupported,
+		.exists = fs_exists_unsupported,
 		.read = fs_read_unsupported,
 		.write = fs_write_unsupported,
 	},
@@ -150,6 +175,9 @@ int fs_set_blk_dev(const char *ifname, const char *dev_part_str, int fstype)
 				fstype != info->fstype)
 			continue;
 
+		if (!fs_dev_desc && !info->null_dev_desc_ok)
+			continue;
+
 		if (!info->probe(fs_dev_desc, &fs_partition)) {
 			fs_type = info->fstype;
 			return 0;
@@ -182,6 +210,19 @@ int fs_ls(const char *dirname)
 	return ret;
 }
 
+int fs_exists(const char *filename)
+{
+	int ret;
+
+	struct fstype_info *info = fs_get_info(fs_type);
+
+	ret = info->exists(filename);
+
+	fs_close();
+
+	return ret;
+}
+
 int fs_read(const char *filename, ulong addr, int offset, int len)
 {
 	struct fstype_info *info = fs_get_info(fs_type);
@@ -212,16 +253,11 @@ int fs_write(const char *filename, ulong addr, int offset, int len)
 	void *buf;
 	int ret;
 
-	/*
-	 * We don't actually know how many bytes are being read, since len==0
-	 * means read the whole file.
-	 */
 	buf = map_sysmem(addr, len);
 	ret = info->write(filename, buf, offset, len);
 	unmap_sysmem(buf);
 
-	/* If we requested a specific number of bytes, check we got it */
-	if (ret >= 0 && len && ret != len) {
+	if (ret >= 0 && ret != len) {
 		printf("** Unable to write file %s **\n", filename);
 		ret = -1;
 	}
@@ -312,6 +348,15 @@ int do_ls(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[],
 	return 0;
 }
 
+int file_exists(const char *dev_type, const char *dev_part, const char *file,
+		int fstype)
+{
+	if (fs_set_blk_dev(dev_type, dev_part, fstype))
+		return 0;
+
+	return fs_exists(file);
+}
+
 int do_save(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[],
 		int fstype)
 {
diff --git a/fs/jffs2/Makefile b/fs/jffs2/Makefile
index a11ca32e81..4cb0600cf9 100644
--- a/fs/jffs2/Makefile
+++ b/fs/jffs2/Makefile
@@ -5,37 +5,9 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)libjffs2.o
-
-AOBJS	=
-ifdef CONFIG_CMD_JFFS2
-COBJS-$(CONFIG_JFFS2_LZO) += compr_lzo.o
-COBJS-y += compr_rtime.o
-COBJS-y += compr_rubin.o
-COBJS-y += compr_zlib.o
-COBJS-y += jffs2_1pass.o
-COBJS-y += mini_inflate.o
-endif
-
-COBJS	:= $(COBJS-y)
-SRCS	:= $(AOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(AOBJS) $(COBJS))
-
-#CPPFLAGS +=
-
-all:	$(LIB) $(AOBJS)
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-$(CONFIG_JFFS2_LZO) += compr_lzo.o
+obj-y += compr_rtime.o
+obj-y += compr_rubin.o
+obj-y += compr_zlib.o
+obj-y += jffs2_1pass.o
+obj-y += mini_inflate.o
diff --git a/fs/jffs2/jffs2_1pass.c b/fs/jffs2/jffs2_1pass.c
index c856983ef4..3fb5db383e 100644
--- a/fs/jffs2/jffs2_1pass.c
+++ b/fs/jffs2/jffs2_1pass.c
@@ -114,6 +114,7 @@
 #include <common.h>
 #include <config.h>
 #include <malloc.h>
+#include <div64.h>
 #include <linux/stat.h>
 #include <linux/time.h>
 #include <watchdog.h>
@@ -1438,7 +1439,7 @@ jffs2_1pass_build_lists(struct part_info * part)
 {
 	struct b_lists *pL;
 	struct jffs2_unknown_node *node;
-	u32 nr_sectors = part->size/part->sector_size;
+	u32 nr_sectors;
 	u32 i;
 	u32 counter4 = 0;
 	u32 counterF = 0;
@@ -1447,6 +1448,7 @@ jffs2_1pass_build_lists(struct part_info * part)
 	u32 buf_size = DEFAULT_EMPTY_SCAN_SIZE;
 	char *buf;
 
+	nr_sectors = lldiv(part->size, part->sector_size);
 	/* turn off the lcd.  Refreshing the lcd adds 50% overhead to the */
 	/* jffs2 list building enterprise nope.  in newer versions the overhead is */
 	/* only about 5 %.  not enough to inconvenience people for. */
diff --git a/fs/reiserfs/Makefile b/fs/reiserfs/Makefile
index d81d71d392..5a692f0ee7 100644
--- a/fs/reiserfs/Makefile
+++ b/fs/reiserfs/Makefile
@@ -9,28 +9,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)libreiserfs.o
-
-AOBJS	=
-COBJS-$(CONFIG_CMD_REISER) := reiserfs.o dev.o mode_string.o
-
-SRCS	:= $(AOBJS:.o=.S) $(COBJS-y:.o=.c)
-OBJS	:= $(addprefix $(obj),$(AOBJS) $(COBJS-y))
-
-#CPPFLAGS +=
-
-all:	$(LIB) $(AOBJS)
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y := reiserfs.o dev.o mode_string.o
diff --git a/fs/sandbox/Makefile b/fs/sandbox/Makefile
index df2fc32414..ca238f6d7d 100644
--- a/fs/sandbox/Makefile
+++ b/fs/sandbox/Makefile
@@ -10,25 +10,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)libsandboxfs.o
-
-COBJS-$(CONFIG_SANDBOX) := sandboxfs.o
-
-SRCS	:= $(COBJS-y:.o=.c)
-OBJS	:= $(addprefix $(obj),$(AOBJS) $(COBJS-y))
-
-all:	$(LIB) $(AOBJS)
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y := sandboxfs.o
diff --git a/fs/sandbox/sandboxfs.c b/fs/sandbox/sandboxfs.c
index dd028da8e3..85079788c9 100644
--- a/fs/sandbox/sandboxfs.c
+++ b/fs/sandbox/sandboxfs.c
@@ -72,6 +72,14 @@ int sandbox_fs_ls(const char *dirname)
 	return 0;
 }
 
+int sandbox_fs_exists(const char *filename)
+{
+	ssize_t sz;
+
+	sz = os_get_filesize(filename);
+	return sz >= 0;
+}
+
 void sandbox_fs_close(void)
 {
 }
diff --git a/fs/ubifs/Makefile b/fs/ubifs/Makefile
index 47949c14be..8c8c6ac683 100644
--- a/fs/ubifs/Makefile
+++ b/fs/ubifs/Makefile
@@ -9,31 +9,7 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)libubifs.o
-
-COBJS-$(CONFIG_CMD_UBIFS) := ubifs.o io.o super.o sb.o master.o lpt.o
-COBJS-$(CONFIG_CMD_UBIFS) += lpt_commit.o scan.o lprops.o
-COBJS-$(CONFIG_CMD_UBIFS) += tnc.o tnc_misc.o debug.o crc16.o budget.o
-COBJS-$(CONFIG_CMD_UBIFS) += log.o orphan.o recovery.o replay.o
-
-SRCS	:= $(AOBJS:.o=.S) $(COBJS-y:.o=.c)
-OBJS	:= $(addprefix $(obj),$(AOBJS) $(COBJS-y))
-
-all:	$(LIB) $(AOBJS)
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-# SEE README.arm-unaligned-accesses
-$(obj)super.o: CFLAGS += $(PLATFORM_NO_UNALIGNED)
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y := ubifs.o io.o super.o sb.o master.o lpt.o
+obj-y += lpt_commit.o scan.o lprops.o
+obj-y += tnc.o tnc_misc.o debug.o crc16.o budget.o
+obj-y += log.o orphan.o recovery.o replay.o
diff --git a/fs/ubifs/ubifs.h b/fs/ubifs/ubifs.h
index 633631e4d4..2213201572 100644
--- a/fs/ubifs/ubifs.h
+++ b/fs/ubifs/ubifs.h
@@ -2137,6 +2137,13 @@ void ubifs_compress(const void *in_buf, int in_len, void *out_buf, int *out_len,
 int ubifs_decompress(const void *buf, int len, void *out, int *out_len,
 		     int compr_type);
 
+/* these are used in cmd_ubifs.c */
+int ubifs_init(void);
+int ubifs_mount(char *vol_name);
+void ubifs_umount(struct ubifs_info *c);
+int ubifs_ls(char *dir_name);
+int ubifs_load(char *filename, u32 addr, u32 size);
+
 #include "debug.h"
 #include "misc.h"
 #include "key.h"
diff --git a/fs/yaffs2/Makefile b/fs/yaffs2/Makefile
index 9b29d225a5..45ff7458c6 100644
--- a/fs/yaffs2/Makefile
+++ b/fs/yaffs2/Makefile
@@ -16,11 +16,7 @@
 #
 # $Id: Makefile,v 1.15 2007/07/18 19:40:38 charles Exp $
 
-include $(TOPDIR)/config.mk
-
-LIB = $(obj)libyaffs2.o
-
-COBJS-$(CONFIG_YAFFS2) := \
+obj-y := \
 	yaffs_allocator.o yaffs_attribs.o yaffs_bitmap.o yaffs_uboot_glue.o\
 	yaffs_checkptrw.o yaffs_ecc.o yaffs_error.o \
 	yaffsfs.o yaffs_guts.o yaffs_nameval.o yaffs_nand.o\
@@ -28,36 +24,6 @@ COBJS-$(CONFIG_YAFFS2) := \
 	yaffs_summary.o yaffs_tagscompat.o yaffs_verify.o yaffs_yaffs1.o \
 	yaffs_yaffs2.o yaffs_mtdif.o yaffs_mtdif2.o
 
-SRCS    := $(COBJS-y:.o=.c)
-OBJS    := $(addprefix $(obj),$(COBJS-y))
-
-YCFLAGS =  -DCONFIG_YAFFS_DIRECT -DCONFIG_YAFFS_SHORT_NAMES_IN_RAM
-YCFLAGS += -DCONFIG_YAFFS_YAFFS2 -DNO_Y_INLINE
-YCFLAGS += -DCONFIG_YAFFS_PROVIDE_DEFS -DCONFIG_YAFFSFS_PROVIDE_VALUES
-
-CFLAGS += $(YCFLAGS)
-CPPFLAGS +=  $(YCFLAGS)
-
-all:  $(LIB)
-
-$(obj)libyaffs2.a: $(obj).depend $(OBJS)
-	$(AR) $(ARFLAGS) $@ $(OBJS)
-
-$(obj)libyaffs2.o: $(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-.PHONY: clean distclean
-clean:
-	rm -f $(OBJS)
-
-distclean:  clean
-	rm -f $(LIB) core *.bak .depend
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+ccflags-y = -DCONFIG_YAFFS_DIRECT -DCONFIG_YAFFS_SHORT_NAMES_IN_RAM \
+		-DCONFIG_YAFFS_YAFFS2 -DNO_Y_INLINE \
+		-DCONFIG_YAFFS_PROVIDE_DEFS -DCONFIG_YAFFSFS_PROVIDE_VALUES
diff --git a/fs/yaffs2/yaffs_list.h b/fs/yaffs2/yaffs_list.h
deleted file mode 100644
index a7afaea27b..0000000000
--- a/fs/yaffs2/yaffs_list.h
+++ /dev/null
@@ -1,126 +0,0 @@
-/*
- * YAFFS: Yet another Flash File System . A NAND-flash specific file system.
- *
- * Copyright (C) 2002-2011 Aleph One Ltd.
- *   for Toby Churchill Ltd and Brightstar Engineering
- *
- * Created by Charles Manning <charles@aleph1.co.uk>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU Lesser General Public License version 2.1 as
- * published by the Free Software Foundation.
- *
- * Note: Only YAFFS headers are LGPL, YAFFS C code is covered by GPL.
- */
-
-/*
- * This file is just holds extra declarations of macros that would normally
- * be providesd in the Linux kernel. These macros have been written from
- * scratch but are functionally equivalent to the Linux ones.
- *
- */
-
-#ifndef __YAFFS_LIST_H__
-#define __YAFFS_LIST_H__
-
-
-/*
- * This is a simple doubly linked list implementation that matches the
- * way the Linux kernel doubly linked list implementation works.
- */
-
-struct list_head {
-	struct list_head *next; /* next in chain */
-	struct list_head *prev; /* previous in chain */
-};
-
-
-/* Initialise a static list */
-#define LIST_HEAD(name) \
-struct list_head name = { &(name), &(name)}
-
-
-
-/* Initialise a list head to an empty list */
-#define INIT_LIST_HEAD(p) \
-do { \
-	(p)->next = (p);\
-	(p)->prev = (p); \
-} while (0)
-
-
-/* Add an element to a list */
-static inline void list_add(struct list_head *new_entry,
-				struct list_head *list)
-{
-	struct list_head *list_next = list->next;
-
-	list->next = new_entry;
-	new_entry->prev = list;
-	new_entry->next = list_next;
-	list_next->prev = new_entry;
-
-}
-
-static inline void list_add_tail(struct list_head *new_entry,
-				 struct list_head *list)
-{
-	struct list_head *list_prev = list->prev;
-
-	list->prev = new_entry;
-	new_entry->next = list;
-	new_entry->prev = list_prev;
-	list_prev->next = new_entry;
-
-}
-
-
-/* Take an element out of its current list, with or without
- * reinitialising the links.of the entry*/
-static inline void list_del(struct list_head *entry)
-{
-	struct list_head *list_next = entry->next;
-	struct list_head *list_prev = entry->prev;
-
-	list_next->prev = list_prev;
-	list_prev->next = list_next;
-
-}
-
-static inline void list_del_init(struct list_head *entry)
-{
-	list_del(entry);
-	entry->next = entry->prev = entry;
-}
-
-
-/* Test if the list is empty */
-static inline int list_empty(struct list_head *entry)
-{
-	return (entry->next == entry);
-}
-
-
-/* list_entry takes a pointer to a list entry and offsets it to that
- * we can find a pointer to the object it is embedded in.
- */
-
-
-#define list_entry(entry, type, member) \
-	((type *)((char *)(entry)-(unsigned long)(&((type *)NULL)->member)))
-
-
-/* list_for_each and list_for_each_safe  iterate over lists.
- * list_for_each_safe uses temporary storage to make the list delete safe
- */
-
-#define list_for_each(itervar, list) \
-	for (itervar = (list)->next; itervar != (list); itervar = itervar->next)
-
-#define list_for_each_safe(itervar, save_var, list) \
-	for (itervar = (list)->next, save_var = (list)->next->next; \
-		itervar != (list); \
-		itervar = save_var, save_var = save_var->next)
-
-
-#endif
diff --git a/fs/yaffs2/yaffs_summary.c b/fs/yaffs2/yaffs_summary.c
index 46e42f6d7d..e9e1b5d857 100644
--- a/fs/yaffs2/yaffs_summary.c
+++ b/fs/yaffs2/yaffs_summary.c
@@ -232,7 +232,6 @@ int yaffs_summary_read(struct yaffs_dev *dev,
 	if (result == YAFFS_OK) {
 		/* Verify header */
 		if (hdr.version != YAFFS_SUMMARY_VERSION ||
-		    hdr.block != blk ||
 		    hdr.seq != bi->seq_number ||
 		    hdr.sum != yaffs_summary_sum(dev))
 			result = YAFFS_FAIL;
diff --git a/fs/yaffs2/yaffs_uboot_glue.c b/fs/yaffs2/yaffs_uboot_glue.c
index e113e4039e..50000a135b 100644
--- a/fs/yaffs2/yaffs_uboot_glue.c
+++ b/fs/yaffs2/yaffs_uboot_glue.c
@@ -20,6 +20,7 @@
  */
 
 #include <common.h>
+#include <div64.h>
 
 #include <config.h>
 #include "nand.h"
@@ -184,7 +185,7 @@ void cmd_yaffs_devconfig(char *_mp, int flash_dev,
 	}
 
 	if (end_block == 0)
-		end_block = mtd->size / mtd->erasesize - 1;
+		end_block = lldiv(mtd->size, mtd->erasesize - 1);
 
 	if (end_block < start_block) {
 		printf("Bad start/end\n");
diff --git a/fs/yaffs2/yaffsfs.c b/fs/yaffs2/yaffsfs.c
index ac4a010bdf..334598eedf 100644
--- a/fs/yaffs2/yaffsfs.c
+++ b/fs/yaffs2/yaffsfs.c
@@ -11,6 +11,7 @@
  * published by the Free Software Foundation.
  */
 
+#include <div64.h>
 #include "yaffsfs.h"
 #include "yaffs_guts.h"
 #include "yaffscfg.h"
@@ -1603,8 +1604,8 @@ static int yaffsfs_DoStat(struct yaffs_obj *obj, struct yaffs_stat *buf)
 		buf->st_rdev = obj->yst_rdev;
 		buf->st_size = yaffs_get_obj_length(obj);
 		buf->st_blksize = obj->my_dev->data_bytes_per_chunk;
-		buf->st_blocks = (buf->st_size + buf->st_blksize - 1) /
-		    buf->st_blksize;
+		buf->st_blocks = lldiv(buf->st_size + buf->st_blksize - 1,
+		    buf->st_blksize);
 #if CONFIG_YAFFS_WINCE
 		buf->yst_wince_atime[0] = obj->win_atime[0];
 		buf->yst_wince_atime[1] = obj->win_atime[1];
diff --git a/fs/yaffs2/ydirectenv.h b/fs/yaffs2/ydirectenv.h
index c2ffbfd56d..c6614f13b0 100644
--- a/fs/yaffs2/ydirectenv.h
+++ b/fs/yaffs2/ydirectenv.h
@@ -77,7 +77,7 @@ void yaffs_qsort(void *aa, size_t n, size_t es,
 #define YAFFS_ROOT_MODE			0666
 #define YAFFS_LOSTNFOUND_MODE		0666
 
-#include "yaffs_list.h"
+#include "linux/list.h"
 
 #include "yaffsfs.h"
 
diff --git a/fs/zfs/Makefile b/fs/zfs/Makefile
index 32070de58d..fa58b7fcde 100644
--- a/fs/zfs/Makefile
+++ b/fs/zfs/Makefile
@@ -5,27 +5,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)libzfs.o
-
-AOBJS	=
-COBJS-$(CONFIG_CMD_ZFS) := dev.o zfs.o zfs_fletcher.o zfs_sha256.o zfs_lzjb.o
-
-SRCS	:= $(AOBJS:.o=.S) $(COBJS-y:.o=.c)
-OBJS	:= $(addprefix $(obj),$(AOBJS) $(COBJS-y))
-
-
-all:	$(LIB) $(AOBJS)
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y := dev.o zfs.o zfs_fletcher.o zfs_sha256.o zfs_lzjb.o
diff --git a/include/.gitignore b/include/.gitignore
index 7cd3e90700..bf142fc2f9 100644
--- a/include/.gitignore
+++ b/include/.gitignore
@@ -1,5 +1,4 @@
 /autoconf.mk*
-/asm
 /bmp_logo.h
 /bmp_logo_data.h
 /config.h
diff --git a/include/amba_clcd.h b/include/amba_clcd.h
deleted file mode 100644
index db80517e53..0000000000
--- a/include/amba_clcd.h
+++ /dev/null
@@ -1,77 +0,0 @@
-/*
- * Register definitions for the AMBA CLCD logic cell.
- *
- * derived from David A Rusling, although rearranged as a C structure
- *     linux/include/asm-arm/hardware/amba_clcd.h -- Integrator LCD panel.
- *
- * Copyright (C) 2001 ARM Limited
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file COPYING in the main directory of this archive
- * for more details.
- */
-
-/*
- * CLCD Controller Internal Register addresses
- */
-struct clcd_registers {
-	u32 tim0;	/* 0x00 */
-	u32 tim1;
-	u32 tim2;
-	u32 tim3;
-	u32 ubas;	/* 0x10 */
-	u32 lbas;
-#if !defined(CONFIG_ARCH_VERSATILE) && !defined(CONFIG_ARCH_REALVIEW)
-	u32 ienb;
-	u32 cntl;
-#else /* Someone rearranged these two registers on the Versatile */
-	u32 cntl;
-	u32 ienb;
-#endif
-	u32 stat;	/* 0x20 */
-	u32 intr;
-	u32 ucur;
-	u32 lcur;
-	u32 unused[0x74];	/* 0x030..0x1ff */
-	u32 palette[0x80];	/* 0x200..0x3ff */
-};
-
-/* Bit definition for TIM2 */
-#define TIM2_CLKSEL		(1 << 5)
-#define TIM2_IVS		(1 << 11)
-#define TIM2_IHS		(1 << 12)
-#define TIM2_IPC		(1 << 13)
-#define TIM2_IOE		(1 << 14)
-#define TIM2_BCD		(1 << 26)
-
-/* Bit definitions for control register */
-#define CNTL_LCDEN		(1 << 0)
-#define CNTL_LCDBPP1		(0 << 1)
-#define CNTL_LCDBPP2		(1 << 1)
-#define CNTL_LCDBPP4		(2 << 1)
-#define CNTL_LCDBPP8		(3 << 1)
-#define CNTL_LCDBPP16		(4 << 1)
-#define CNTL_LCDBPP16_565	(6 << 1)
-#define CNTL_LCDBPP24		(5 << 1)
-#define CNTL_LCDBW		(1 << 4)
-#define CNTL_LCDTFT		(1 << 5)
-#define CNTL_LCDMONO8		(1 << 6)
-#define CNTL_LCDDUAL		(1 << 7)
-#define CNTL_BGR		(1 << 8)
-#define CNTL_BEBO		(1 << 9)
-#define CNTL_BEPO		(1 << 10)
-#define CNTL_LCDPWR		(1 << 11)
-#define CNTL_LCDVCOMP(x)	((x) << 12)
-#define CNTL_LDMAFIFOTIME	(1 << 15)
-#define CNTL_WATERMARK		(1 << 16)
-
-/* u-boot specific: information passed by the board file */
-struct clcd_config {
-	struct clcd_registers *address;
-	u32			tim0;
-	u32			tim1;
-	u32			tim2;
-	u32			tim3;
-	u32			cntl;
-	unsigned long		pixclock;
-};
diff --git a/include/asm-generic/global_data.h b/include/asm-generic/global_data.h
index 77e06fb4fe..707400e847 100644
--- a/include/asm-generic/global_data.h
+++ b/include/asm-generic/global_data.h
@@ -21,6 +21,8 @@
  */
 
 #ifndef __ASSEMBLY__
+#include <linux/list.h>
+
 typedef struct global_data {
 	bd_t *bd;
 	unsigned long flags;
@@ -61,6 +63,12 @@ typedef struct global_data {
 	unsigned long start_addr_sp;	/* start_addr_stackpointer */
 	unsigned long reloc_off;
 	struct global_data *new_gd;	/* relocated global data */
+
+#ifdef CONFIG_DM
+	struct device	*dm_root;	/* Root instance for Driver Model */
+	struct list_head uclass_root;	/* Head of core tree */
+#endif
+
 	const void *fdt_blob;	/* Our device tree, NULL if none */
 	void *new_fdt;		/* Relocated FDT */
 	unsigned long fdt_size;	/* Space reserved for relocated FDT */
@@ -72,6 +80,8 @@ typedef struct global_data {
 #if defined(CONFIG_SYS_I2C)
 	int		cur_i2c_bus;	/* current used i2c bus */
 #endif
+	unsigned long timebase_h;
+	unsigned long timebase_l;
 	struct arch_global_data arch;	/* architecture-specific data */
 } gd_t;
 #endif
diff --git a/include/asm-generic/global_data_flags.h b/include/asm-generic/global_data_flags.h
deleted file mode 100644
index bb57fb6c4a..0000000000
--- a/include/asm-generic/global_data_flags.h
+++ /dev/null
@@ -1,28 +0,0 @@
-/*
- * transitional header until we merge global_data.h
- *
- * (C) Copyright 2000-2010
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef __ASM_GENERIC_GLOBAL_DATA_FLAGS_H
-#define __ASM_GENERIC_GLOBAL_DATA_FLAGS_H
-
-/*
- * Global Data Flags
- *
- * Note: The low 16 bits are expected for common code.  If your arch
- *       really needs to add your own, use the high 16bits.
- */
-#define GD_FLG_RELOC		0x0001	/* Code was relocated to RAM */
-#define GD_FLG_DEVINIT		0x0002	/* Devices have been initialized */
-#define GD_FLG_SILENT		0x0004	/* Silent mode */
-#define GD_FLG_POSTFAIL		0x0008	/* Critical POST test failed */
-#define GD_FLG_POSTSTOP		0x0010	/* POST seqeunce aborted */
-#define GD_FLG_LOGINIT		0x0020	/* Log Buffer has been initialized */
-#define GD_FLG_DISABLE_CONSOLE	0x0040	/* Disable console (in & out) */
-#define GD_FLG_ENV_READY	0x0080	/* Environment imported into hash table */
-
-#endif
diff --git a/include/asm-generic/gpio.h b/include/asm-generic/gpio.h
index f54103980c..e325df40d9 100644
--- a/include/asm-generic/gpio.h
+++ b/include/asm-generic/gpio.h
@@ -78,4 +78,108 @@ int gpio_get_value(unsigned gpio);
  * @return 0 if ok, -1 on error
  */
 int gpio_set_value(unsigned gpio, int value);
+
+/* State of a GPIO, as reported by get_state() */
+enum {
+	GPIOF_INPUT = 0,
+	GPIOF_OUTPUT,
+	GPIOF_UNKNOWN,
+};
+
+struct device;
+
+/**
+ * struct struct dm_gpio_ops - Driver model GPIO operations
+ *
+ * Refer to functions above for description. These function largely copy
+ * the old API.
+ *
+ * This is trying to be close to Linux GPIO API. Once the U-Boot uses the
+ * new DM GPIO API, this should be really easy to flip over to the Linux
+ * GPIO API-alike interface.
+ *
+ * Akso it would be useful to standardise additional functions like
+ * pullup, slew rate and drive strength.
+ *
+ * gpio_request)( and gpio_free() are optional - if NULL then they will
+ * not be called.
+ *
+ * Note that @offset is the offset from the base GPIO of the device. So
+ * offset 0 is the device's first GPIO and offset o-1 is the last GPIO,
+ * where o is the number of GPIO lines controlled by the device. A device
+ * is typically used to control a single bank of GPIOs. Within complex
+ * SoCs there may be many banks and therefore many devices all referring
+ * to the different IO addresses within the SoC.
+ *
+ * The uclass combines all GPIO devices togther to provide a consistent
+ * numbering from 0 to n-1, where n is the number of GPIOs in total across
+ * all devices. Be careful not to confuse offset with gpio in the parameters.
+ */
+struct dm_gpio_ops {
+	int (*request)(struct device *dev, unsigned offset, const char *label);
+	int (*free)(struct device *dev, unsigned offset);
+	int (*direction_input)(struct device *dev, unsigned offset);
+	int (*direction_output)(struct device *dev, unsigned offset,
+				int value);
+	int (*get_value)(struct device *dev, unsigned offset);
+	int (*set_value)(struct device *dev, unsigned offset, int value);
+	int (*get_function)(struct device *dev, unsigned offset);
+	int (*get_state)(struct device *dev, unsigned offset, char *state,
+			 int maxlen);
+};
+
+/**
+ * struct gpio_dev_priv - information about a device used by the uclass
+ *
+ * The uclass combines all active GPIO devices into a unified numbering
+ * scheme. To do this it maintains some private information aobut each
+ * device.
+ *
+ * To implement driver model support in your GPIO driver, add a probe
+ * handler, and set @gpio_count and @bank_name correctly in that handler.
+ * This tells the uclass the name of the GPIO bank and the number of GPIOs
+ * it contains.
+ *
+ * @bank_name: Name of the GPIO device (e.g 'a' means GPIOs will be called
+ * 'A0', 'A1', etc.
+ * @gpio_count: Number of GPIOs in this device
+ * @gpio_base: Base GPIO number for this device. For the first active device
+ * this will be 0; the numbering for others will follow sequentially so that
+ * @gpio_base for device 1 will equal the number of GPIOs in device 0.
+ */
+struct gpio_dev_priv {
+	const char *bank_name;
+	unsigned gpio_count;
+	unsigned gpio_base;
+};
+
+/* Access the GPIO operations for a device */
+#define gpio_get_ops(dev)	((struct dm_gpio_ops *)(dev)->driver->ops)
+
+/**
+ * gpio_get_bank_info - Return information about a GPIO bank/device
+ *
+ * This looks up a device and returns both its GPIO base name and the number
+ * of GPIOs it controls.
+ *
+ * @dev: Device to look up
+ * @offset_count: Returns number of GPIOs within this bank
+ * @return bank name of this device
+ */
+const char *gpio_get_bank_info(struct device *dev, int *offset_count);
+
+/**
+ * gpio_lookup_name - Look up a GPIO name and return its details
+ *
+ * This is used to convert a named GPIO into a device, offset and GPIO
+ * number.
+ *
+ * @name: GPIO name to look up
+ * @devp: Returns pointer to device which contains this GPIO
+ * @offsetp: Returns the offset number within this device
+ * @gpiop: Returns the absolute GPIO number, numbered from 0
+ */
+int gpio_lookup_name(const char *name, struct device **devp,
+		     unsigned int *offsetp, unsigned int *gpiop);
+
 #endif	/* _ASM_GENERIC_GPIO_H_ */
diff --git a/include/asm-generic/sections.h b/include/asm-generic/sections.h
index 7e1eb4bf5e..458952fb58 100644
--- a/include/asm-generic/sections.h
+++ b/include/asm-generic/sections.h
@@ -63,28 +63,16 @@ extern char __image_copy_end[];
 extern void _start(void);
 
 /*
- * ARM needs to use offsets for symbols, since the values of some symbols
- * are not resolved prior to relocation (and are just 0). Maybe this can be
- * resolved, or maybe other architectures are similar, iwc this should be
- * promoted to an architecture option.
+ * ARM defines its symbols as char[]. Other arches define them as ulongs.
  */
 #ifdef CONFIG_ARM
-#define CONFIG_SYS_SYM_OFFSETS
-#endif
-
-#ifdef CONFIG_SYS_SYM_OFFSETS
-/* Start/end of the relocation entries, as an offset from _start */
-extern ulong _rel_dyn_start_ofs;
-extern ulong _rel_dyn_end_ofs;
-
-/* End of the region to be relocated, as an offset form _start */
-extern ulong _image_copy_end_ofs;
 
-extern ulong _bss_start_ofs;	/* BSS start relative to _start */
-extern ulong _bss_end_ofs;		/* BSS end relative to _start */
-extern ulong _end_ofs;		/* end of image relative to _start */
-
-extern ulong _TEXT_BASE;	/* code start */
+extern char __bss_start[];
+extern char __bss_end[];
+extern char __image_copy_start[];
+extern char __image_copy_end[];
+extern char __rel_dyn_start[];
+extern char __rel_dyn_end[];
 
 #else /* don't use offsets: */
 
diff --git a/include/asm-generic/u-boot.h b/include/asm-generic/u-boot.h
index 43872010c7..e78196797b 100644
--- a/include/asm-generic/u-boot.h
+++ b/include/asm-generic/u-boot.h
@@ -37,7 +37,7 @@ typedef struct bd_info {
 	unsigned long	bi_dsp_freq; /* dsp core frequency */
 	unsigned long	bi_ddr_freq; /* ddr frequency */
 #endif
-#if defined(CONFIG_5xx) || defined(CONFIG_8xx) || defined(CONFIG_8260) \
+#if defined(CONFIG_5xx) || defined(CONFIG_8xx) || defined(CONFIG_MPC8260) \
 	|| defined(CONFIG_E500) || defined(CONFIG_MPC86xx)
 	unsigned long	bi_immr_base;	/* base of IMMR register */
 #endif
diff --git a/include/at45.h b/include/at45.h
deleted file mode 100644
index e7e3711e3b..0000000000
--- a/include/at45.h
+++ /dev/null
@@ -1,69 +0,0 @@
-
-#ifndef	_AT45_H_
-#define	_AT45_H_
-#ifdef	CONFIG_DATAFLASH_MMC_SELECT
-extern	void AT91F_SelectMMC(void);
-extern	void AT91F_SelectSPI(void);
-extern	int AT91F_GetMuxStatus(void);
-#endif
-extern	void AT91F_SpiInit(void);
-extern	void AT91F_SpiEnable(int cs);
-extern	unsigned int AT91F_SpiWrite ( AT91PS_DataflashDesc pDesc );
-extern	AT91S_DataFlashStatus AT91F_DataFlashSendCommand(
-		AT91PS_DataFlash pDataFlash,
-		unsigned char OpCode,
-		unsigned int CmdSize,
-		unsigned int DataflashAddress);
-extern	AT91S_DataFlashStatus AT91F_DataFlashGetStatus (
-	AT91PS_DataflashDesc pDesc);
-extern	AT91S_DataFlashStatus AT91F_DataFlashWaitReady (
-	AT91PS_DataflashDesc pDataFlashDesc,
-	unsigned int timeout);
-extern	AT91S_DataFlashStatus AT91F_DataFlashContinuousRead (
-	AT91PS_DataFlash pDataFlash,
-	int src,
-	unsigned char *dataBuffer,
-	int sizeToRead );
-extern	AT91S_DataFlashStatus AT91F_DataFlashPagePgmBuf(
-	AT91PS_DataFlash pDataFlash,
-	unsigned char *src,
-	unsigned int dest,
-	unsigned int SizeToWrite);
-extern	AT91S_DataFlashStatus AT91F_MainMemoryToBufferTransfert(
-	AT91PS_DataFlash pDataFlash,
-	unsigned char BufferCommand,
-	unsigned int page);
-extern	AT91S_DataFlashStatus AT91F_DataFlashWriteBuffer (
-	AT91PS_DataFlash pDataFlash,
-	unsigned char BufferCommand,
-	unsigned char *dataBuffer,
-	unsigned int bufferAddress,
-	int SizeToWrite );
-extern	AT91S_DataFlashStatus AT91F_PageErase(
-	AT91PS_DataFlash pDataFlash,
-	unsigned int page);
-extern	AT91S_DataFlashStatus AT91F_BlockErase(
-	AT91PS_DataFlash pDataFlash,
-	unsigned int block);
-extern	AT91S_DataFlashStatus AT91F_WriteBufferToMain (
-	AT91PS_DataFlash pDataFlash,
-	unsigned char BufferCommand,
-	unsigned int dest );
-extern	AT91S_DataFlashStatus AT91F_PartialPageWrite (
-	AT91PS_DataFlash pDataFlash,
-	unsigned char *src,
-	unsigned int dest,
-	unsigned int size);
-extern	AT91S_DataFlashStatus AT91F_DataFlashWrite(
-	AT91PS_DataFlash pDataFlash,
-	unsigned char *src,
-	int dest,
-	int size );
-extern	int AT91F_DataFlashRead(
-	AT91PS_DataFlash pDataFlash,
-	unsigned long addr,
-	unsigned long size,
-	char *buffer);
-extern	int AT91F_DataflashProbe(int cs, AT91PS_DataflashDesc pDesc);
-
-#endif
diff --git a/include/at91rm9200_i2c.h b/include/at91rm9200_i2c.h
deleted file mode 100644
index 486660638c..0000000000
--- a/include/at91rm9200_i2c.h
+++ /dev/null
@@ -1,114 +0,0 @@
-/* ---------------------------------------------------------------------------- */
-/*	    ATMEL Microcontroller Software Support  -  ROUSSET	-		*/
-/* ---------------------------------------------------------------------------- */
-/*  The software is delivered "AS IS" without warranty or condition of any	*/
-/*  kind, either express, implied or statutory. This includes without		*/
-/*  limitation any warranty or condition with respect to merchantability or	*/
-/*  fitness for any particular purpose, or against the infringements of		*/
-/*  intellectual property rights of others.					*/
-/* ---------------------------------------------------------------------------- */
-/* File Name	       : at91rm9200_i2c.h					*/
-/* Object	       : AT91RM9200 / TWI definitions				*/
-/* Generated	       : AT91 SW Application Group  12/03/2002 (10:48:02)	*/
-/*										*/
-/* ---------------------------------------------------------------------------- */
-
-#ifndef AT91RM9200_TWI_H
-#define AT91RM9200_TWI_H
-
-/* ******************************************************************************/
-/*		SOFTWARE API DEFINITION	 FOR Two-wire Interface			*/
-/* ******************************************************************************/
-#ifndef __ASSEMBLY__
-
-typedef struct _AT91S_TWI {
-	AT91_REG	 TWI_CR;	/* Control Register			*/
-	AT91_REG	 TWI_MMR;	/* Master Mode Register			*/
-	AT91_REG	 TWI_SMR;	/* Slave Mode Register			*/
-	AT91_REG	 TWI_IADR;	/* Internal Address Register		*/
-	AT91_REG	 TWI_CWGR;	/* Clock Waveform Generator Register	*/
-	AT91_REG	 Reserved0[3];
-	AT91_REG	 TWI_SR;	/* Status Register			*/
-	AT91_REG	 TWI_IER;	/* Interrupt Enable Register		*/
-	AT91_REG	 TWI_IDR;	/* Interrupt Disable Register		*/
-	AT91_REG	 TWI_IMR;	/* Interrupt Mask Register		*/
-	AT91_REG	 TWI_RHR;	/* Receive Holding Register		*/
-	AT91_REG	 TWI_THR;	/* Transmit Holding Register		*/
-	AT91_REG	 Reserved1[50];
-	AT91_REG	 TWI_RPR;	/* Receive Pointer Register		*/
-	AT91_REG	 TWI_RCR;	/* Receive Counter Register		*/
-	AT91_REG	 TWI_TPR;	/* Transmit Pointer Register		*/
-	AT91_REG	 TWI_TCR;	/* Transmit Counter Register		*/
-	AT91_REG	 TWI_RNPR;	/* Receive Next Pointer Register	*/
-	AT91_REG	 TWI_RNCR;	/* Receive Next Counter Register	*/
-	AT91_REG	 TWI_TNPR;	/* Transmit Next Pointer Register	*/
-	AT91_REG	 TWI_TNCR;	/* Transmit Next Counter Register	*/
-	AT91_REG	 TWI_PTCR;	/* PDC Transfer Control Register	*/
-	AT91_REG	 TWI_PTSR;	/* PDC Transfer Status Register		*/
-} AT91S_TWI, *AT91PS_TWI;
-
-#endif
-
-/* -------- TWI_CR : (TWI Offset: 0x0) TWI Control Register --------		*/
-#define AT91C_TWI_START (0x1 <<	 0)	/* (TWI) Send a START Condition		*/
-#define AT91C_TWI_STOP	(0x1 <<	 1)	/* (TWI) Send a STOP Condition		*/
-#define AT91C_TWI_MSEN	(0x1 <<	 2)	/* (TWI) TWI Master Transfer Enabled	*/
-#define AT91C_TWI_MSDIS (0x1 <<	 3)	/* (TWI) TWI Master Transfer Disabled	*/
-#define AT91C_TWI_SVEN	(0x1 <<	 4)	/* (TWI) TWI Slave Transfer Enabled	*/
-#define AT91C_TWI_SVDIS (0x1 <<	 5)	/* (TWI) TWI Slave Transfer Disabled	*/
-#define AT91C_TWI_SWRST (0x1 <<	 7)	/* (TWI) Software Reset		*/
-/* -------- TWI_MMR : (TWI Offset: 0x4) TWI Master Mode Register --------	*/
-#define AT91C_TWI_IADRSZ      (0x3 <<  8) /* (TWI) Internal Device Address Size */
-#define	  AT91C_TWI_IADRSZ_NO	  (0x0 <<  8) /* (TWI) No internal device address	*/
-#define	  AT91C_TWI_IADRSZ_1_BYTE (0x1 <<  8) /* (TWI) One-byte internal device address */
-#define	  AT91C_TWI_IADRSZ_2_BYTE (0x2 <<  8) /* (TWI) Two-byte internal device address */
-#define	  AT91C_TWI_IADRSZ_3_BYTE (0x3 <<  8) /* (TWI) Three-byte internal device address */
-#define AT91C_TWI_MREAD (0x1 << 12)	/* (TWI) Master Read Direction		*/
-#define AT91C_TWI_DADR	(0x7F <<  6)	/* (TWI) Device Address			*/
-/* -------- TWI_SMR : (TWI Offset: 0x8) TWI Slave Mode Register --------	*/
-#define AT91C_TWI_SADR	(0x7F << 16)	/* (TWI) Slave Device Address		*/
-/* -------- TWI_CWGR : (TWI Offset: 0x10) TWI Clock Waveform Generator Register --------	*/
-#define AT91C_TWI_CLDIV	 (0xFF <<  0)	/* (TWI) Clock Low Divider		*/
-#define AT91C_TWI_CHDIV	 (0xFF <<  8)	/* (TWI) Clock High Divider		*/
-#define AT91C_TWI_CKDIV	 (0x7 << 16)	/* (TWI) Clock Divider			*/
-/* -------- TWI_SR : (TWI Offset: 0x20) TWI Status Register --------		*/
-#define AT91C_TWI_TXCOMP (0x1 <<  0)	/* (TWI) Transmission Completed		*/
-#define AT91C_TWI_RXRDY	 (0x1 <<  1)	/* (TWI) Receive holding register ReaDY */
-#define AT91C_TWI_TXRDY	 (0x1 <<  2)	/* (TWI) Transmit holding register ReaDY*/
-#define AT91C_TWI_SVREAD (0x1 <<  3)	/* (TWI) Slave Read			*/
-#define AT91C_TWI_SVACC	 (0x1 <<  4)	/* (TWI) Slave Access			*/
-#define AT91C_TWI_GCACC	 (0x1 <<  5)	/* (TWI) General Call Access		*/
-#define AT91C_TWI_OVRE	 (0x1 <<  6)	/* (TWI) Overrun Error			*/
-#define AT91C_TWI_UNRE	 (0x1 <<  7)	/* (TWI) Underrun Error			*/
-#define AT91C_TWI_NACK	 (0x1 <<  8)	/* (TWI) Not Acknowledged		*/
-#define AT91C_TWI_ARBLST (0x1 <<  9)	/* (TWI) Arbitration Lost		*/
-/* -------- TWI_IER : (TWI Offset: 0x24) TWI Interrupt Enable Register -------- */
-/* -------- TWI_IDR : (TWI Offset: 0x28) TWI Interrupt Disable Register ------- */
-/* -------- TWI_IMR : (TWI Offset: 0x2c) TWI Interrupt Mask Register --------	*/
-
-/*
-    i2c Support for Atmel's AT91RM9200 Two-Wire Interface
-
-    (c) Rick Bronson
-
- * SPDX-License-Identifier:	GPL-2.0+
-*/
-
-#ifndef AT91_I2C_H
-#define AT91_I2C_H
-
-#define AT91C_TWI_CLOCK		100000
-#define AT91C_TWI_SCLOCK	(10 * AT91C_MASTER_CLOCK / AT91C_TWI_CLOCK)
-#define AT91C_TWI_CKDIV1	(2 << 16)	/* TWI clock divider.  NOTE: see Errata #22 */
-
-#if (AT91C_TWI_SCLOCK % 10) >= 5
-#define AT91C_TWI_CLDIV2 ((AT91C_TWI_SCLOCK / 10) - 5)
-#else
-#define AT91C_TWI_CLDIV2 ((AT91C_TWI_SCLOCK / 10) - 6)
-#endif
-#define AT91C_TWI_CLDIV3 ((AT91C_TWI_CLDIV2 + (4 - AT91C_TWI_CLDIV2 % 4)) >> 2)
-
-#define AT91C_EEPROM_I2C_ADDRESS	(0x50 << 16)
-
-#endif	/* __ASSEMBLY__ */
-#endif	/* AT91RM9200_TWI_H */
diff --git a/include/at91rm9200_net.h b/include/at91rm9200_net.h
deleted file mode 100644
index 831cb1e260..0000000000
--- a/include/at91rm9200_net.h
+++ /dev/null
@@ -1,50 +0,0 @@
-/*
- * Ethernet:	An implementation of the Ethernet Device Driver suite for the
- *		uClinux 2.0.38 operating system. This Driver has been developed
- *		for AT75C220 board.
- *
- * NOTE:	The driver is implemented for one MAC
- *
- * Version:	@(#)at91rm9200_net.h	1.0.0	01/10/2001
- *
- * Authors:	Lineo Inc <www.lineo.com>
- *
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef AT91RM9200_ETHERNET
-#define AT91RM9200_ETHERNET
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/hardware.h>
-
-#define ETHERNET_ADDRESS_SIZE           6
-
-typedef unsigned char UCHAR;
-
-/* Interface to drive the physical layer */
-typedef struct _AT91S_PhyOps
-{
-	unsigned char (*Init)(AT91S_EMAC *pmac);
-	unsigned int (*IsPhyConnected)(AT91S_EMAC  *pmac);
-	unsigned char (*GetLinkSpeed)(AT91S_EMAC *pmac);
-	unsigned char (*AutoNegotiate)(AT91S_EMAC *pmac, int *);
-
-} AT91S_PhyOps,*AT91PS_PhyOps;
-
-
-#define EMAC_DESC_DONE 0x00000001  /* ownership bit */
-#define EMAC_DESC_WRAP 0x00000002  /* bit for wrap */
-
-/******************  function prototypes **********************/
-
-/* MII functions */
-void at91rm9200_EmacEnableMDIO(AT91PS_EMAC p_mac);
-void at91rm9200_EmacDisableMDIO(AT91PS_EMAC p_mac);
-UCHAR at91rm9200_EmacReadPhy(AT91PS_EMAC p_mac, unsigned char RegisterAddress, unsigned short *pInput);
-UCHAR at91rm9200_EmacWritePhy(AT91PS_EMAC p_mac, unsigned char RegisterAddress, unsigned short *pOutput);
-void at91rm9200_GetPhyInterface(AT91PS_PhyOps p_phyops);
-
-#endif /* AT91RM9200_ETHERNET */
diff --git a/include/bcm5221.h b/include/bcm5221.h
deleted file mode 100644
index 4719389cfd..0000000000
--- a/include/bcm5221.h
+++ /dev/null
@@ -1,88 +0,0 @@
-/*
- * Broadcom BCM5221 Ethernet PHY
- *
- * (C) Copyright 2005 REA Elektronik GmbH <www.rea.de>
- * Anders Larsen <alarsen@rea.de>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#define	BCM5221_BMCR		0	/* Basic Mode Control Register */
-#define BCM5221_BMSR		1	/* Basic Mode Status Register */
-#define BCM5221_PHYID1		2	/* PHY Identifier Register 1 */
-#define BCM5221_PHYID2		3	/* PHY Identifier Register 2 */
-#define BCM5221_ANAR		4	/* Auto-negotiation Advertisement Register  */
-#define BCM5221_ANLPAR		5	/* Auto-negotiation Link Partner Ability Register */
-#define BCM5221_ANER		6	/* Auto-negotiation Expansion Register  */
-#define BCM5221_ACSR		24	/* Auxiliary Control/Status Register */
-#define BCM5221_INTR		26	/* Interrupt Register */
-
-/* --Bit definitions: BCM5221_BMCR */
-#define BCM5221_RESET		(1 << 15)	/* 1= Software Reset; 0=Normal Operation */
-#define BCM5221_LOOPBACK	(1 << 14)	/* 1=loopback Enabled; 0=Normal Operation */
-#define BCM5221_SPEED_SELECT	(1 << 13)	/* 1=100Mbps; 0=10Mbps */
-#define BCM5221_AUTONEG		(1 << 12)
-#define BCM5221_POWER_DOWN	(1 << 11)
-#define BCM5221_ISOLATE		(1 << 10)
-#define BCM5221_RESTART_AUTONEG	(1 << 9)
-#define BCM5221_DUPLEX_MODE	(1 << 8)
-#define BCM5221_COLLISION_TEST	(1 << 7)
-
-/*--Bit definitions: BCM5221_BMSR */
-#define BCM5221_100BASE_T4	(1 << 15)
-#define BCM5221_100BASE_TX_FD	(1 << 14)
-#define BCM5221_100BASE_TX_HD	(1 << 13)
-#define BCM5221_10BASE_T_FD	(1 << 12)
-#define BCM5221_10BASE_T_HD	(1 << 11)
-#define BCM5221_MF_PREAMB_SUPPR	(1 << 6)
-#define BCM5221_AUTONEG_COMP	(1 << 5)
-#define BCM5221_REMOTE_FAULT	(1 << 4)
-#define BCM5221_AUTONEG_ABILITY	(1 << 3)
-#define BCM5221_LINK_STATUS	(1 << 2)
-#define BCM5221_JABBER_DETECT	(1 << 1)
-#define BCM5221_EXTEND_CAPAB	(1 << 0)
-
-/*--definitions: BCM5221_PHYID1 */
-#define BCM5221_PHYID1_OUI	0x1018
-#define BCM5221_LSB_MASK	0x3F
-
-/*--Bit definitions: BCM5221_ANAR, BCM5221_ANLPAR */
-#define BCM5221_NP		(1 << 15)
-#define BCM5221_ACK		(1 << 14)
-#define BCM5221_RF		(1 << 13)
-#define BCM5221_FCS		(1 << 10)
-#define BCM5221_T4		(1 << 9)
-#define BCM5221_TX_FDX		(1 << 8)
-#define BCM5221_TX_HDX		(1 << 7)
-#define BCM5221_10_FDX		(1 << 6)
-#define BCM5221_10_HDX		(1 << 5)
-#define BCM5221_AN_IEEE_802_3	0x0001
-
-/*--Bit definitions: BCM5221_ANER */
-#define BCM5221_PDF		(1 << 4)
-#define BCM5221_LP_NP_ABLE	(1 << 3)
-#define BCM5221_NP_ABLE		(1 << 2)
-#define BCM5221_PAGE_RX		(1 << 1)
-#define BCM5221_LP_AN_ABLE	(1 << 0)
-
-/*--Bit definitions: BCM5221_ACSR */
-#define BCM5221_100		(1 << 1)
-#define BCM5221_FDX		(1 << 0)
-
-/*--Bit definitions: BCM5221_INTR */
-#define BCM5221_FDX_LED		(1 << 15)
-#define BCM5221_INTR_ENABLE	(1 << 14)
-#define BCM5221_FDX_MASK	(1 << 11)
-#define BCM5221_SPD_MASK	(1 << 10)
-#define BCM5221_LINK_MASK	(1 << 9)
-#define BCM5221_INTR_MASK	(1 << 8)
-#define BCM5221_FDX_CHG		(1 << 3)
-#define BCM5221_SPD_CHG		(1 << 2)
-#define BCM5221_LINK_CHG	(1 << 1)
-#define BCM5221_INTR_STATUS	(1 << 0)
-
-/******************  function prototypes **********************/
-unsigned int  bcm5221_IsPhyConnected(AT91PS_EMAC p_mac);
-unsigned char bcm5221_GetLinkSpeed(AT91PS_EMAC p_mac);
-unsigned char bcm5221_AutoNegotiate(AT91PS_EMAC p_mac, int *status);
-unsigned char bcm5221_InitPhy(AT91PS_EMAC p_mac);
diff --git a/include/bitfield.h b/include/bitfield.h
new file mode 100644
index 0000000000..ec4815c8e0
--- /dev/null
+++ b/include/bitfield.h
@@ -0,0 +1,58 @@
+/*
+ * Copyright 2013 Broadcom Corporation.
+ *
+ * SPDX-License-Identifier:      GPL-2.0+
+ */
+
+/*
+ * Bitfield operations
+ *
+ * These are generic bitfield operations which allow manipulation of variable
+ * width bitfields within a word. One use of this would be to use data tables
+ * to determine how to reprogram fields within R/W hardware registers.
+ *
+ * Example:
+ *
+ *            old_reg_val
+ * +--------+----+---+--+-----+----------+
+ * |        |    |   |  | old |          |
+ * +--------+----+---+--+-----+----------+
+ *
+ *            new_reg_val
+ * +--------+----+---+--+-----+----------+
+ * |        |    |   |  | new |          |
+ * +--------+----+---+--+-----+----------+
+ *
+ * mask = bitfield_mask(10, 5);
+ * old = bitfield_extract(old_reg_val, 10, 5);
+ * new_reg_val = bitfield_replace(old_reg_val, 10, 5, new);
+ *
+ * The numbers 10 and 5 could for example come from data
+ * tables which describe all bitfields in all registers.
+ */
+
+#include <linux/types.h>
+
+/* Produces a mask of set bits covering a range of a uint value */
+static inline uint bitfield_mask(uint shift, uint width)
+{
+	return ((1 << width) - 1) << shift;
+}
+
+/* Extract the value of a bitfield found within a given register value */
+static inline uint bitfield_extract(uint reg_val, uint shift, uint width)
+{
+	return (reg_val & bitfield_mask(shift, width)) >> shift;
+}
+
+/*
+ * Replace the value of a bitfield found within a given register value
+ * Returns the newly modified uint value with the replaced field.
+ */
+static inline uint bitfield_replace(uint reg_val, uint shift, uint width,
+				    uint bitfield_val)
+{
+	uint mask = bitfield_mask(shift, width);
+
+	return (reg_val & ~mask) | (bitfield_val << shift);
+}
diff --git a/include/clk.h b/include/clk.h
new file mode 100644
index 0000000000..df4570c6f5
--- /dev/null
+++ b/include/clk.h
@@ -0,0 +1,6 @@
+#ifndef _CLK_H_
+#define _CLK_H_
+
+int soc_clk_dump(void);
+
+#endif /* _CLK_H_ */
diff --git a/include/command.h b/include/command.h
index f782779d8b..d3f700fc3c 100644
--- a/include/command.h
+++ b/include/command.h
@@ -64,6 +64,15 @@ extern int var_complete(int argc, char * const argv[], char last_char, int maxv,
 extern int cmd_auto_complete(const char *const prompt, char *buf, int *np, int *colp);
 #endif
 
+/**
+ * cmd_process_error() - report and process a possible error
+ *
+ * @cmdtp: Command which caused the error
+ * @err: Error code (0 if none, -ve for error, like -EIO)
+ * @return 0 if there is not error, 1 (CMD_RET_FAILURE) if an error is found
+ */
+int cmd_process_error(cmd_tbl_t *cmdtp, int err);
+
 /*
  * Monitor Command
  *
diff --git a/include/common.h b/include/common.h
index 409515f498..cbd3c9e043 100644
--- a/include/common.h
+++ b/include/common.h
@@ -8,9 +8,6 @@
 #ifndef __COMMON_H_
 #define __COMMON_H_	1
 
-#undef	_LINUX_CONFIG_H
-#define _LINUX_CONFIG_H 1	/* avoid reading Linux autoconf.h file	*/
-
 #ifndef __ASSEMBLY__		/* put C only stuff in this section */
 
 typedef unsigned char		uchar;
@@ -55,16 +52,13 @@ typedef volatile unsigned char	vu_char;
 #include <mpc5xxx.h>
 #elif defined(CONFIG_MPC512X)
 #include <asm/immap_512x.h>
-#elif defined(CONFIG_8260)
+#elif defined(CONFIG_MPC8260)
 #if   defined(CONFIG_MPC8247) \
    || defined(CONFIG_MPC8248) \
    || defined(CONFIG_MPC8271) \
    || defined(CONFIG_MPC8272)
 #define CONFIG_MPC8272_FAMILY	1
 #endif
-#if defined(CONFIG_MPC8272_FAMILY)
-#define CONFIG_MPC8260	1
-#endif
 #include <asm/immap_8260.h>
 #endif
 #ifdef CONFIG_MPC86xx
@@ -99,6 +93,10 @@ typedef volatile unsigned char	vu_char;
 #include <flash.h>
 #include <image.h>
 
+#ifdef __LP64__
+#define CONFIG_SYS_SUPPORT_64BIT_DATA
+#endif
+
 #ifdef DEBUG
 #define _DEBUG	1
 #else
@@ -305,10 +303,18 @@ int	checkdram     (void);
 int	last_stage_init(void);
 extern ulong monitor_flash_len;
 int mac_read_from_eeprom(void);
-extern u8 _binary_dt_dtb_start[];	/* embedded device tree blob */
+extern u8 __dtb_dt_begin[];	/* embedded device tree blob */
 int set_cpu_clk_info(void);
+#if defined(CONFIG_DISPLAY_CPUINFO)
 int print_cpuinfo(void);
+#else
+static inline int print_cpuinfo(void)
+{
+	return 0;
+}
+#endif
 int update_flash_size(int flash_size);
+int arch_early_init_r(void);
 
 /**
  * Show the DRAM size in a board-specific way
@@ -355,6 +361,11 @@ int do_ext2load(cmd_tbl_t *, int, int, char * const []);
 int	env_init     (void);
 void	env_relocate (void);
 int	envmatch     (uchar *, int);
+
+/* Avoid unfortunate conflict with libc's getenv() */
+#ifdef CONFIG_SANDBOX
+#define getenv uboot_getenv
+#endif
 char	*getenv	     (const char *);
 int	getenv_f     (const char *name, char *buf, unsigned len);
 ulong getenv_ulong(const char *name, int base, ulong default_val);
@@ -411,6 +422,9 @@ static inline int setenv_addr(const char *varname, const void *addr)
 #ifdef CONFIG_MIPS
 # include <asm/u-boot-mips.h>
 #endif /* CONFIG_MIPS */
+#ifdef CONFIG_ARC
+# include <asm/u-boot-arc.h>
+#endif /* CONFIG_ARC */
 
 #ifdef CONFIG_AUTO_COMPLETE
 int env_complete(char *var, int maxv, char *cmdv[], int maxsz, char *buf);
@@ -454,6 +468,7 @@ void	api_init (void);
 
 /* common/memsize.c */
 long	get_ram_size  (long *, long);
+phys_size_t get_effective_memsize(void);
 
 /* $(BOARD)/$(BOARD).c */
 void	reset_phy     (void);
@@ -657,7 +672,7 @@ int	get_clocks (void);
 int	get_clocks_866 (void);
 int	sdram_adjust_866 (void);
 int	adjust_sdram_tbs_8xx (void);
-#if defined(CONFIG_8260)
+#if defined(CONFIG_MPC8260)
 int	prt_8260_clks (void);
 #elif defined(CONFIG_MPC5xxx)
 int	prt_mpc5xxx_clks (void);
@@ -698,6 +713,10 @@ ulong get_ddr_freq(ulong);
 #if defined(CONFIG_MPC85xx)
 typedef MPC85xx_SYS_INFO sys_info_t;
 void	get_sys_info  ( sys_info_t * );
+#  if defined(CONFIG_OF_LIBFDT)
+	void ft_fixup_cpu(void *, u64);
+	void ft_fixup_num_cores(void *);
+#  endif
 #endif
 #if defined(CONFIG_MPC86xx)
 typedef MPC86xx_SYS_INFO sys_info_t;
@@ -721,7 +740,7 @@ void	get_sys_info  ( sys_info_t * );
 #endif
 
 /* $(CPU)/cpu_init.c */
-#if defined(CONFIG_8xx) || defined(CONFIG_8260)
+#if defined(CONFIG_8xx) || defined(CONFIG_MPC8260)
 void	cpu_init_f    (volatile immap_t *immr);
 #endif
 #if defined(CONFIG_4xx) || defined(CONFIG_MPC85xx) || defined(CONFIG_MCF52x2) ||defined(CONFIG_MPC86xx)
@@ -729,7 +748,7 @@ void	cpu_init_f    (void);
 #endif
 
 int	cpu_init_r    (void);
-#if defined(CONFIG_8260)
+#if defined(CONFIG_MPC8260)
 int	prt_8260_rsr  (void);
 #elif defined(CONFIG_MPC83xx)
 int	prt_83xx_rsr  (void);
@@ -803,8 +822,7 @@ void	udelay        (unsigned long);
 void mdelay(unsigned long);
 
 /* lib/uuid.c */
-void uuid_str_to_bin(const char *uuid, unsigned char *out);
-int uuid_str_valid(const char *uuid);
+#include <uuid.h>
 
 /* lib/vsprintf.c */
 #include <vsprintf.h>
@@ -816,9 +834,7 @@ char *	strmhz(char *buf, unsigned long hz);
 #include <u-boot/crc.h>
 
 /* lib/rand.c */
-#if defined(CONFIG_RANDOM_MACADDR) || \
-	defined(CONFIG_BOOTP_RANDOM_DELAY) || \
-	defined(CONFIG_CMD_LINK_LOCAL)
+#if defined(CONFIG_LIB_RAND) || defined(CONFIG_LIB_HW_RAND)
 #define RAND_MAX -1U
 void srand(unsigned int seed);
 unsigned int rand(void);
@@ -923,7 +939,7 @@ static inline void unmap_sysmem(const void *vaddr)
 {
 }
 
-static inline phys_addr_t map_to_sysmem(void *ptr)
+static inline phys_addr_t map_to_sysmem(const void *ptr)
 {
 	return (phys_addr_t)(uintptr_t)ptr;
 }
@@ -960,6 +976,22 @@ static inline phys_addr_t map_to_sysmem(void *ptr)
 #define DIV_ROUND_UP(n,d)	(((n) + (d) - 1) / (d))
 #define roundup(x, y)		((((x) + ((y) - 1)) / (y)) * (y))
 
+/*
+ * Divide positive or negative dividend by positive divisor and round
+ * to closest integer. Result is undefined for negative divisors and
+ * for negative dividends if the divisor variable type is unsigned.
+ */
+#define DIV_ROUND_CLOSEST(x, divisor)(			\
+{							\
+	typeof(x) __x = x;				\
+	typeof(divisor) __d = divisor;			\
+	(((typeof(x))-1) > 0 ||				\
+	 ((typeof(divisor))-1) > 0 || (__x) > 0) ?	\
+		(((__x) + ((__d) / 2)) / (__d)) :	\
+		(((__x) - ((__d) / 2)) / (__d));	\
+}							\
+)
+
 #define ALIGN(x,a)		__ALIGN_MASK((x),(typeof(x))(a)-1)
 #define __ALIGN_MASK(x,mask)	(((x)+(mask))&~(mask))
 
diff --git a/include/common_timing_params.h b/include/common_timing_params.h
new file mode 100644
index 0000000000..76338d4e6c
--- /dev/null
+++ b/include/common_timing_params.h
@@ -0,0 +1,57 @@
+/*
+ * Copyright 2008 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * Version 2 as published by the Free Software Foundation.
+ */
+
+#ifndef COMMON_TIMING_PARAMS_H
+#define COMMON_TIMING_PARAMS_H
+
+typedef struct {
+	/* parameters to constrict */
+
+	unsigned int tckmin_x_ps;
+	unsigned int tckmax_ps;
+	unsigned int tckmax_max_ps;
+	unsigned int trcd_ps;
+	unsigned int trp_ps;
+	unsigned int tras_ps;
+
+	unsigned int twr_ps;	/* maximum = 63750 ps */
+	unsigned int twtr_ps;	/* maximum = 63750 ps */
+	unsigned int trfc_ps;	/* maximum = 255 ns + 256 ns + .75 ns
+					   = 511750 ps */
+
+	unsigned int trrd_ps;	/* maximum = 63750 ps */
+	unsigned int trc_ps;	/* maximum = 254 ns + .75 ns = 254750 ps */
+
+	unsigned int refresh_rate_ps;
+	unsigned int extended_op_srt;
+
+	unsigned int tis_ps;	/* byte 32, spd->ca_setup */
+	unsigned int tih_ps;	/* byte 33, spd->ca_hold */
+	unsigned int tds_ps;	/* byte 34, spd->data_setup */
+	unsigned int tdh_ps;	/* byte 35, spd->data_hold */
+	unsigned int trtp_ps;	/* byte 38, spd->trtp */
+	unsigned int tdqsq_max_ps;	/* byte 44, spd->tdqsq */
+	unsigned int tqhs_ps;	/* byte 45, spd->tqhs */
+
+	unsigned int ndimms_present;
+	unsigned int lowest_common_SPD_caslat;
+	unsigned int highest_common_derated_caslat;
+	unsigned int additive_latency;
+	unsigned int all_dimms_burst_lengths_bitmask;
+	unsigned int all_dimms_registered;
+	unsigned int all_dimms_unbuffered;
+	unsigned int all_dimms_ecc_capable;
+
+	unsigned long long total_mem;
+	unsigned long long base_address;
+
+	/* DDR3 RDIMM */
+	unsigned char rcw[16];	/* Register Control Word 0-15 */
+} common_timing_params_t;
+
+#endif
diff --git a/include/commproc.h b/include/commproc.h
index 6959905efe..c10a79c839 100644
--- a/include/commproc.h
+++ b/include/commproc.h
@@ -20,7 +20,6 @@
 #ifndef __CPM_8XX__
 #define __CPM_8XX__
 
-#include <linux/config.h>
 #include <asm/8xx_immap.h>
 
 /* CPM Command register.
diff --git a/include/config_cmd_all.h b/include/config_cmd_all.h
index d84706969d..2c2a05bce1 100644
--- a/include/config_cmd_all.h
+++ b/include/config_cmd_all.h
@@ -23,6 +23,7 @@
 #define CONFIG_CMD_BSP		/* Board Specific functions	*/
 #define CONFIG_CMD_CACHE	/* icache, dcache		*/
 #define CONFIG_CMD_CDP		/* Cisco Discovery Protocol	*/
+#define CONFIG_CMD_CLK		/* Clock support		*/
 #define CONFIG_CMD_CONSOLE	/* coninfo			*/
 #define CONFIG_CMD_DATE		/* support for RTC, date/time...*/
 #define CONFIG_CMD_DHCP		/* DHCP Support			*/
@@ -37,7 +38,6 @@
 #define CONFIG_CMD_EXT2		/* EXT2 Support			*/
 #define CONFIG_CMD_FAT		/* FAT support			*/
 #define CONFIG_CMD_FDC		/* Floppy Disk Support		*/
-#define CONFIG_CMD_FDOS		/* Floppy DOS support		*/
 #define CONFIG_CMD_FLASH	/* flinfo, erase, protect	*/
 #define CONFIG_CMD_FPGA		/* FPGA configuration Support	*/
 #define CONFIG_CMD_FUSE		/* Device fuse support		*/
diff --git a/include/config_defaults.h b/include/config_defaults.h
index 567b46c87a..ad08c1d335 100644
--- a/include/config_defaults.h
+++ b/include/config_defaults.h
@@ -14,6 +14,7 @@
 #define CONFIG_BOOTM_NETBSD 1
 #define CONFIG_BOOTM_PLAN9 1
 #define CONFIG_BOOTM_RTEMS 1
+#define CONFIG_BOOTM_VXWORKS 1
 
 #define CONFIG_GZIP 1
 #define CONFIG_ZLIB 1
diff --git a/include/config_distro_defaults.h b/include/config_distro_defaults.h
new file mode 100644
index 0000000000..5d18a4b903
--- /dev/null
+++ b/include/config_distro_defaults.h
@@ -0,0 +1,56 @@
+/*
+ * Copyright 2013-2014 Red Hat, Inc.
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#ifndef _CONFIG_CMD_DISTRO_DEFAULTS_H
+#define _CONFIG_CMD_DISTRO_DEFAULTS_H
+
+/*
+ * List of all commands and options that when defined enables support for
+ * features required by distros to support boards in a standardised and
+ * consitant manner.
+ */
+
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_DNS
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_PXE
+#define CONFIG_BOOTP_SUBNETMASK
+
+#if defined(__arm__)
+#define CONFIG_BOOTP_PXE_CLIENTARCH     0x100
+#if defined(__ARM_ARCH_7__) || defined(__ARM_ARCH_7A__)
+#define CONFIG_BOOTP_VCI_STRING         "U-boot.armv7"
+#else
+#define CONFIG_BOOTP_VCI_STRING         "U-boot.arm"
+#endif
+#endif
+
+#define CONFIG_OF_LIBFDT
+
+#define CONFIG_CMD_BOOTZ
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_EXT4
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_FS_GENERIC
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_PXE
+
+#define CONFIG_CMDLINE_EDITING
+#define CONFIG_AUTO_COMPLETE
+#define CONFIG_BOOTDELAY     2
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_MENU
+#define CONFIG_DOS_PARTITION
+#define CONFIG_EFI_PARTITION
+#define CONFIG_SUPPORT_RAW_INITRD
+#define CONFIG_SYS_HUSH_PARSER
+
+#endif	/* _CONFIG_CMD_DISTRO_DEFAULTS_H */
diff --git a/include/config_fallbacks.h b/include/config_fallbacks.h
index e59ee963f7..e6fb47be0b 100644
--- a/include/config_fallbacks.h
+++ b/include/config_fallbacks.h
@@ -48,9 +48,35 @@
 	defined(CONFIG_CMD_SCSI) || \
 	defined(CONFIG_CMD_USB) || \
 	defined(CONFIG_CMD_PART) || \
+	defined(CONFIG_CMD_GPT) || \
 	defined(CONFIG_MMC) || \
-	defined(CONFIG_SYSTEMACE)
+	defined(CONFIG_SYSTEMACE) || \
+	defined(CONFIG_SANDBOX)
 #define HAVE_BLOCK_DEVICE
 #endif
 
+#if (defined(CONFIG_PARTITION_UUIDS) || \
+	defined(CONFIG_EFI_PARTITION) || \
+	defined(CONFIG_RANDOM_UUID) || \
+	defined(CONFIG_CMD_UUID) || \
+	defined(CONFIG_BOOTP_PXE)) && \
+	!defined(CONFIG_LIB_UUID)
+#define CONFIG_LIB_UUID
+#endif
+
+#if (defined(CONFIG_RANDOM_UUID) || \
+	defined(CONFIG_CMD_UUID)) && \
+	(!defined(CONFIG_LIB_RAND) && \
+	!defined(CONFIG_LIB_HW_RAND))
+#define CONFIG_LIB_RAND
+#endif
+
+#ifndef CONFIG_SYS_PROMPT
+#define CONFIG_SYS_PROMPT	"=> "
+#endif
+
+#ifndef CONFIG_SYS_HZ
+#define CONFIG_SYS_HZ		1000
+#endif
+
 #endif	/* __CONFIG_FALLBACKS_H */
diff --git a/include/configs/A3000.h b/include/configs/A3000.h
index 90a21768e9..35e3e6fa8b 100644
--- a/include/configs/A3000.h
+++ b/include/configs/A3000.h
@@ -25,7 +25,6 @@
  * (easy to change)
  */
 
-#define CONFIG_MPC824X		1
 #define CONFIG_MPC8245		1
 #define CONFIG_A3000		1
 
@@ -168,7 +167,6 @@
  */
 
 #define CONFIG_SYS_CLK_FREQ  33333333	/* external frequency to pll */
-#define CONFIG_SYS_HZ		     1000
 
 	/* Bit-field values for MCCR1.
 	 */
diff --git a/include/configs/APC405.h b/include/configs/APC405.h
index 7373c61082..2678f50bbb 100644
--- a/include/configs/APC405.h
+++ b/include/configs/APC405.h
@@ -19,7 +19,6 @@
  * (easy to change)
  */
 #define CONFIG_405GP		1	/* This is a PPC405 CPU		*/
-#define CONFIG_4xx		1	/* ...member of PPC4xx family   */
 #define CONFIG_APCG405		1	/* ...on a APC405 board		*/
 
 #define	CONFIG_SYS_TEXT_BASE	0xFFF80000
@@ -142,7 +141,6 @@
  * Miscellaneous configurable options
  */
 #define CONFIG_SYS_LONGHELP			/* undef to save memory */
-#define CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt */
 #define CONFIG_CMDLINE_EDITING	1	/* add command line history */
 
 #if defined(CONFIG_CMD_KGDB)
@@ -177,8 +175,6 @@
 #define CONFIG_SYS_LOAD_ADDR	0x100000	/* default load address */
 #define CONFIG_SYS_EXTBDINFO	1		/* To use extended board_into (bd_t) */
 
-#define	CONFIG_SYS_HZ		1000		/* decrementer freq: 1 ms ticks */
-
 #define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */
 
 /* Only interrupt boot if space is pressed */
diff --git a/include/configs/AR405.h b/include/configs/AR405.h
index b0206f5d79..45dd46a41e 100644
--- a/include/configs/AR405.h
+++ b/include/configs/AR405.h
@@ -18,7 +18,6 @@
  */
 
 #define CONFIG_405GP		1	/* This is a PPC405GP CPU	*/
-#define CONFIG_4xx		1	/* ...member of PPC4xx family	*/
 #define CONFIG_AR405		1	/* ...on a AR405 board		*/
 
 #define	CONFIG_SYS_TEXT_BASE	0xFFFA0000
@@ -91,7 +90,6 @@
  * Miscellaneous configurable options
  */
 #define CONFIG_SYS_LONGHELP			/* undef to save memory		*/
-#define CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt	*/
 #if defined(CONFIG_CMD_KGDB)
 #define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
 #else
@@ -128,8 +126,6 @@
 #define CONFIG_SYS_LOAD_ADDR	0x100000	/* default load address */
 #define CONFIG_SYS_EXTBDINFO	1		/* To use extended board_into (bd_t) */
 
-#define CONFIG_SYS_HZ		1000		/* decrementer freq: 1 ms ticks */
-
 #define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */
 
 /*-----------------------------------------------------------------------
diff --git a/include/configs/ASH405.h b/include/configs/ASH405.h
index a93d0c1037..2ff9b598c5 100644
--- a/include/configs/ASH405.h
+++ b/include/configs/ASH405.h
@@ -18,7 +18,6 @@
  */
 
 #define CONFIG_405EP		1	/* This is a PPC405 CPU		*/
-#define CONFIG_4xx		1	/* ...member of PPC4xx family	*/
 #define CONFIG_ASH405		1	/* ...on a ASH405 board		*/
 
 #define	CONFIG_SYS_TEXT_BASE	0xFFFC0000
@@ -86,7 +85,6 @@
  * Miscellaneous configurable options
  */
 #define CONFIG_SYS_LONGHELP			/* undef to save memory		*/
-#define CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt	*/
 
 #undef	CONFIG_SYS_HUSH_PARSER			/* use "hush" command parser	*/
 
@@ -123,8 +121,6 @@
 #define CONFIG_SYS_LOAD_ADDR	0x100000	/* default load address */
 #define CONFIG_SYS_EXTBDINFO	1		/* To use extended board_into (bd_t) */
 
-#define CONFIG_SYS_HZ		1000		/* decrementer freq: 1 ms ticks */
-
 #define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */
 
 #define CONFIG_VERSION_VARIABLE 1	/* include version env variable */
@@ -146,6 +142,8 @@
 
 #define CONFIG_SYS_NAND_SKIP_BAD_DOT_I	1	/* ".i" read skips bad blocks   */
 #define CONFIG_SYS_NAND_QUIET		1
+#define CONFIG_SYS_NAND_MAX_OOBFREE	2
+#define CONFIG_SYS_NAND_MAX_ECCPOS	56
 
 /*-----------------------------------------------------------------------
  * PCI stuff
diff --git a/include/configs/Adder.h b/include/configs/Adder.h
index 302d93fbe2..140f4439c1 100644
--- a/include/configs/Adder.h
+++ b/include/configs/Adder.h
@@ -72,7 +72,6 @@
 /*-----------------------------------------------------------------------
  * Miscellaneous configurable options
  */
-#define CONFIG_SYS_PROMPT		"=> "		/* Monitor Command Prompt	*/
 #define CONFIG_SYS_HUSH_PARSER
 #define CONFIG_SYS_LONGHELP				/* #undef to save memory	*/
 #define CONFIG_SYS_CBSIZE		256		/* Console I/O Buffer Size	*/
@@ -82,8 +81,6 @@
 
 #define CONFIG_SYS_LOAD_ADDR		0x400000	/* Default load address		*/
 
-#define CONFIG_SYS_HZ			1000		/* Decrementer freq: 1 ms ticks	*/
-
 /*-----------------------------------------------------------------------
  * RAM configuration (note that CONFIG_SYS_SDRAM_BASE must be zero)
  */
diff --git a/include/configs/AdderUSB.h b/include/configs/AdderUSB.h
deleted file mode 100644
index ef76ce4cfc..0000000000
--- a/include/configs/AdderUSB.h
+++ /dev/null
@@ -1,35 +0,0 @@
-/*
- * Copyright (C) 2006 CodeHermit.
- * Bryan O'Donoghue <bodonoghue@codehermit.ie>
- *
- * Provides support for USB console on the Analogue & Micro Adder87x
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef __ADDERUSB__
-#define __ADDERUSB__
-
-/* Include the board port */
-#include "Adder.h"
-
-#define CONFIG_USB_DEVICE		/* Include UDC driver */
-#define CONFIG_USB_TTY			/* Bind the TTY driver to UDC */
-#define CONFIG_SYS_USB_EXTC_CLK 0x02		/* Oscillator on EXTC_CLK 2 */
-#define CONFIG_SYS_USB_BRG_CLK	0x04		/* or use Baud rate generator 0x04 */
-#define CONFIG_SYS_CONSOLE_IS_IN_ENV		/* Console is in env */
-
-/* If you have a USB-IF assigned VendorID then you may wish to define
- * your own vendor specific values either in BoardName.h or directly in
- * usbd_vendor_info.h
- */
-
-/*
-#define CONFIG_USBD_MANUFACTURER	"CodeHermit.ie"
-#define CONFIG_USBD_PRODUCT_NAME	"Das U-Boot"
-#define CONFIG_USBD_VENDORID		0xFFFF
-#define CONFIG_USBD_PRODUCTID_GSERIAL	0xFFFF
-#define CONFIG_USBD_PRODUCTID_CDCACM	0xFFFE
-*/
-
-#endif /* __ADDERUSB_H__ */
diff --git a/include/configs/B4860QDS.h b/include/configs/B4860QDS.h
index 2f0bc6b062..b248302687 100644
--- a/include/configs/B4860QDS.h
+++ b/include/configs/B4860QDS.h
@@ -16,6 +16,8 @@
 #ifdef CONFIG_RAMBOOT_PBL
 #define CONFIG_RAMBOOT_TEXT_BASE	CONFIG_SYS_TEXT_BASE
 #define CONFIG_RESET_VECTOR_ADDRESS	0xfffffffc
+#define CONFIG_SYS_FSL_PBL_PBI	board/freescale/b4860qds/b4_pbi.cfg
+#define CONFIG_SYS_FSL_PBL_RCW	board/freescale/b4860qds/b4_rcw.cfg
 #endif
 
 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
@@ -32,11 +34,10 @@
 #define CONFIG_E500			/* BOOKE e500 family */
 #define CONFIG_E500MC			/* BOOKE e500mc family */
 #define CONFIG_SYS_BOOK3E_HV		/* Category E.HV supported */
-#define CONFIG_MPC85xx			/* MPC85xx/PQ3 platform */
 #define CONFIG_MP			/* support multiple processors */
 
 #ifndef CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_TEXT_BASE	0xeff80000
+#define CONFIG_SYS_TEXT_BASE	0xeff40000
 #endif
 
 #ifndef CONFIG_RESET_VECTOR_ADDRESS
@@ -113,7 +114,7 @@
 #define CONFIG_SYS_EXTRA_ENV_RELOC
 #define CONFIG_ENV_IS_IN_NAND
 #define CONFIG_ENV_SIZE			CONFIG_SYS_NAND_BLOCK_SIZE
-#define CONFIG_ENV_OFFSET		(5 * CONFIG_SYS_NAND_BLOCK_SIZE)
+#define CONFIG_ENV_OFFSET		(7 * CONFIG_SYS_NAND_BLOCK_SIZE)
 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
 #define CONFIG_ENV_IS_IN_REMOTE
 #define CONFIG_ENV_ADDR		0xffe20000
@@ -191,7 +192,7 @@ unsigned long get_board_ddr_clk(void);
 
 #define CONFIG_DDR_SPD
 #define CONFIG_SYS_DDR_RAW_TIMING
-#define CONFIG_FSL_DDR3
+#define CONFIG_SYS_FSL_DDR3
 #define CONFIG_FSL_DDR_INTERACTIVE
 
 #define CONFIG_SYS_SPD_BUS_NUM	0
@@ -287,6 +288,8 @@ unsigned long get_board_ddr_clk(void);
 
 /* NAND Flash on IFC */
 #define CONFIG_NAND_FSL_IFC
+#define CONFIG_SYS_NAND_MAX_ECCPOS	256
+#define CONFIG_SYS_NAND_MAX_OOBFREE	2
 #define CONFIG_SYS_NAND_BASE		0xff800000
 #ifdef CONFIG_PHYS_64BIT
 #define CONFIG_SYS_NAND_BASE_PHYS	(0xf00000000ull | CONFIG_SYS_NAND_BASE)
@@ -604,7 +607,7 @@ unsigned long get_board_ddr_clk(void);
 #define CONFIG_SYS_QE_FMAN_FW_ADDR	(512 * 1130)
 #elif defined(CONFIG_NAND)
 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND
-#define CONFIG_SYS_QE_FMAN_FW_ADDR	(6 * CONFIG_SYS_NAND_BLOCK_SIZE)
+#define CONFIG_SYS_QE_FMAN_FW_ADDR	(8 * CONFIG_SYS_NAND_BLOCK_SIZE)
 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
 /*
  * Slave has no ucode locally, it can fetch this from remote. When implementing
@@ -617,7 +620,7 @@ unsigned long get_board_ddr_clk(void);
 #define CONFIG_SYS_QE_FMAN_FW_ADDR	0xFFE00000
 #else
 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
-#define CONFIG_SYS_QE_FMAN_FW_ADDR		0xEFF40000
+#define CONFIG_SYS_QE_FMAN_FW_ADDR		0xEFF00000
 #endif
 #define CONFIG_SYS_QE_FMAN_FW_LENGTH	0x10000
 #define CONFIG_SYS_FDT_PAD		(0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
@@ -716,7 +719,6 @@ unsigned long get_board_ddr_clk(void);
 #define CONFIG_CMDLINE_EDITING			/* Command-line editing */
 #define CONFIG_AUTO_COMPLETE			/* add autocompletion support */
 #define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
-#define CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt */
 #ifdef CONFIG_CMD_KGDB
 #define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size */
 #else
@@ -725,7 +727,6 @@ unsigned long get_board_ddr_clk(void);
 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
 #define CONFIG_SYS_MAXARGS	16		/* max number of command args */
 #define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
-#define CONFIG_SYS_HZ		1000		/* decrementer freq: 1ms ticks*/
 
 /*
  * For booting Linux, the board info and command line data
@@ -737,7 +738,6 @@ unsigned long get_board_ddr_clk(void);
 
 #ifdef CONFIG_CMD_KGDB
 #define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
-#define CONFIG_KGDB_SER_INDEX	2	/* which serial port to use */
 #endif
 
 /*
@@ -841,8 +841,6 @@ unsigned long get_board_ddr_clk(void);
 
 #define CONFIG_BOOTCOMMAND		CONFIG_LINUX
 
-#ifdef CONFIG_SECURE_BOOT
 #include <asm/fsl_secure_boot.h>
-#endif
 
 #endif	/* __CONFIG_H */
diff --git a/include/configs/BC3450.h b/include/configs/BC3450.h
index fd9728ebdc..802e9cce1f 100644
--- a/include/configs/BC3450.h
+++ b/include/configs/BC3450.h
@@ -22,8 +22,7 @@
 /*
  * High Level Configuration Options
  */
-#define CONFIG_MPC5xxx		1	/* This is an MPC5xxx CPU	    */
-#define CONFIG_MPC5200		1	/* (more precisely a MPC5200 CPU)   */
+#define CONFIG_MPC5200		1	/* This is a MPC5200 CPU	    */
 #define CONFIG_TQM5200		1	/* ... on a TQM5200 module	    */
 
 #define CONFIG_BC3450		1	/* ... on a BC3450 mainboard	    */
@@ -427,7 +426,6 @@
  * Miscellaneous configurable options
  */
 #define CONFIG_SYS_LONGHELP				/* undef to save memory	    */
-#define CONFIG_SYS_PROMPT		"=> "		/* Monitor Command Prompt   */
 #if defined(CONFIG_CMD_KGDB)
 #define CONFIG_SYS_CBSIZE		1024		/* Console I/O Buffer Size  */
 #else
@@ -445,8 +443,6 @@
 
 #define CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address	    */
 
-#define CONFIG_SYS_HZ			1000		/* dec freq: 1ms ticks	    */
-
 #define CONFIG_SYS_CACHELINE_SIZE	32	/* For MPC5xxx CPUs		    */
 #if defined(CONFIG_CMD_KGDB)
 #  define CONFIG_SYS_CACHELINE_SHIFT	5	/* log base 2 of the above value    */
diff --git a/include/configs/BSC9131RDB.h b/include/configs/BSC9131RDB.h
index 948394eddd..a163e3d8f1 100644
--- a/include/configs/BSC9131RDB.h
+++ b/include/configs/BSC9131RDB.h
@@ -21,7 +21,7 @@
 #define CONFIG_SYS_RAMBOOT
 #define CONFIG_SYS_EXTRA_ENV_RELOC
 #define CONFIG_SYS_TEXT_BASE		0x11000000
-#define CONFIG_RESET_VECTOR_ADDRESS	0x1107fffc
+#define CONFIG_RESET_VECTOR_ADDRESS	0x110bfffc
 #endif
 
 #ifdef CONFIG_NAND
@@ -29,7 +29,7 @@
 #define CONFIG_SPL_INIT_MINIMAL
 #define CONFIG_SPL_SERIAL_SUPPORT
 #define CONFIG_SPL_NAND_SUPPORT
-#define CONFIG_SPL_NAND_MINIMAL
+#define CONFIG_SPL_NAND_BOOT
 #define CONFIG_SPL_FLUSH_IMAGE
 #define CONFIG_SPL_TARGET		"u-boot-with-spl.bin"
 
@@ -38,7 +38,7 @@
 #define CONFIG_SPL_MAX_SIZE		8192
 #define CONFIG_SPL_RELOC_TEXT_BASE	0x00100000
 #define CONFIG_SPL_RELOC_STACK		0x00100000
-#define CONFIG_SYS_NAND_U_BOOT_SIZE	((512 << 10) - 0x2000)
+#define CONFIG_SYS_NAND_U_BOOT_SIZE	((768 << 10) - 0x2000)
 #define CONFIG_SYS_NAND_U_BOOT_DST	(0x00200000 - CONFIG_SPL_MAX_SIZE)
 #define CONFIG_SYS_NAND_U_BOOT_START	0x00200000
 #define CONFIG_SYS_NAND_U_BOOT_OFFS	0
@@ -55,7 +55,6 @@
 /* High Level Configuration Options */
 #define CONFIG_BOOKE			/* BOOKE */
 #define CONFIG_E500			/* BOOKE e500 family */
-#define CONFIG_MPC85xx		/* MPC8540/60/55/41/48/P1020/P2020/P1010,etc*/
 #define CONFIG_FSL_IFC			/* Enable IFC Support */
 
 #define CONFIG_FSL_LAW			/* Use common FSL init code */
@@ -80,7 +79,7 @@
 #define CONFIG_SYS_MEMTEST_END		0x01ffffff
 
 /* DDR Setup */
-#define CONFIG_FSL_DDR3
+#define CONFIG_SYS_FSL_DDR3
 #undef CONFIG_SYS_DDR_RAW_TIMING
 #undef CONFIG_DDR_SPD
 #define CONFIG_SYS_SPD_BUS_NUM		0
@@ -181,18 +180,18 @@ extern unsigned long get_sdram_size(void);
 				| CSOR_NAND_PB(64))	/*Pages Per Block = 64*/
 
 /* NAND Flash Timing Params */
-#define CONFIG_SYS_NAND_FTIM0		(FTIM0_NAND_TCCST(0x08)  \
-					| FTIM0_NAND_TWP(0x06)   \
-					| FTIM0_NAND_TWCHT(0x03) \
+#define CONFIG_SYS_NAND_FTIM0		(FTIM0_NAND_TCCST(0x03)  \
+					| FTIM0_NAND_TWP(0x05)   \
+					| FTIM0_NAND_TWCHT(0x02) \
 					| FTIM0_NAND_TWH(0x04))
-#define CONFIG_SYS_NAND_FTIM1		(FTIM1_NAND_TADLE(0x18) \
-					| FTIM1_NAND_TWBE(0x23) \
-					| FTIM1_NAND_TRR(0x08)  \
+#define CONFIG_SYS_NAND_FTIM1		(FTIM1_NAND_TADLE(0x1C) \
+					| FTIM1_NAND_TWBE(0x1E) \
+					| FTIM1_NAND_TRR(0x07)  \
 					| FTIM1_NAND_TRP(0x05))
 #define CONFIG_SYS_NAND_FTIM2		(FTIM2_NAND_TRAD(0x08)  \
 					| FTIM2_NAND_TREH(0x04) \
-					| FTIM2_NAND_TWHRE(0x3f))
-#define CONFIG_SYS_NAND_FTIM3		FTIM3_NAND_TWW(0x22)
+					| FTIM2_NAND_TWHRE(0x11))
+#define CONFIG_SYS_NAND_FTIM3		FTIM3_NAND_TWW(0x04)
 
 #define CONFIG_SYS_NAND_BASE_LIST	{ CONFIG_SYS_NAND_BASE }
 #define CONFIG_SYS_MAX_NAND_DEVICE	1
@@ -326,7 +325,7 @@ extern unsigned long get_sdram_size(void);
 #define CONFIG_ENV_IS_IN_NAND
 #define CONFIG_SYS_EXTRA_ENV_RELOC
 #define CONFIG_ENV_SIZE		CONFIG_SYS_NAND_BLOCK_SIZE
-#define CONFIG_ENV_OFFSET	((512 * 1024) + CONFIG_SYS_NAND_BLOCK_SIZE)
+#define CONFIG_ENV_OFFSET	((768 * 1024) + CONFIG_SYS_NAND_BLOCK_SIZE)
 #define CONFIG_ENV_RANGE	(3 * CONFIG_ENV_SIZE)
 #elif defined(CONFIG_SYS_RAMBOOT)
 #define CONFIG_ENV_IS_NOWHERE	/* Store ENV in memory only */
@@ -361,7 +360,6 @@ extern unsigned long get_sdram_size(void);
 #define CONFIG_CMDLINE_EDITING			/* Command-line editing */
 #define CONFIG_AUTO_COMPLETE			/* add autocompletion support */
 #define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
-#define CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt */
 
 #if defined(CONFIG_CMD_KGDB)
 #define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size */
@@ -372,7 +370,6 @@ extern unsigned long get_sdram_size(void);
 						/* Print Buffer Size */
 #define CONFIG_SYS_MAXARGS	16		/* max number of command args */
 #define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
-#define CONFIG_SYS_HZ		1000	/* decrementer freq: 1ms ticks */
 
 /*
  * For booting Linux, the board info and command line data
@@ -384,7 +381,6 @@ extern unsigned long get_sdram_size(void);
 
 #if defined(CONFIG_CMD_KGDB)
 #define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
-#define CONFIG_KGDB_SER_INDEX	2	/* which serial port to use */
 #endif
 
 #define CONFIG_USB_EHCI
diff --git a/include/configs/BSC9132QDS.h b/include/configs/BSC9132QDS.h
index 03f3a4f803..052a0f1103 100644
--- a/include/configs/BSC9132QDS.h
+++ b/include/configs/BSC9132QDS.h
@@ -22,7 +22,7 @@
 #define CONFIG_SYS_RAMBOOT
 #define CONFIG_SYS_EXTRA_ENV_RELOC
 #define CONFIG_SYS_TEXT_BASE		0x11000000
-#define CONFIG_RESET_VECTOR_ADDRESS	0x1107fffc
+#define CONFIG_RESET_VECTOR_ADDRESS	0x110bfffc
 #endif
 #define CONFIG_SYS_FSL_ERRATUM_IFC_A002769	1
 #ifdef CONFIG_SPIFLASH
@@ -30,7 +30,7 @@
 #define CONFIG_SYS_RAMBOOT
 #define CONFIG_SYS_EXTRA_ENV_RELOC
 #define CONFIG_SYS_TEXT_BASE		0x11000000
-#define CONFIG_RESET_VECTOR_ADDRESS	0x1107fffc
+#define CONFIG_RESET_VECTOR_ADDRESS	0x110bfffc
 #endif
 
 #ifdef CONFIG_NAND
@@ -38,7 +38,7 @@
 #define CONFIG_SPL_INIT_MINIMAL
 #define CONFIG_SPL_SERIAL_SUPPORT
 #define CONFIG_SPL_NAND_SUPPORT
-#define CONFIG_SPL_NAND_MINIMAL
+#define CONFIG_SPL_NAND_BOOT
 #define CONFIG_SPL_FLUSH_IMAGE
 #define CONFIG_SPL_TARGET		"u-boot-with-spl.bin"
 
@@ -47,7 +47,7 @@
 #define CONFIG_SPL_MAX_SIZE		8192
 #define CONFIG_SPL_RELOC_TEXT_BASE	0x00100000
 #define CONFIG_SPL_RELOC_STACK		0x00100000
-#define CONFIG_SYS_NAND_U_BOOT_SIZE	((512 << 10) - 0x2000)
+#define CONFIG_SYS_NAND_U_BOOT_SIZE	((768 << 10) - 0x2000)
 #define CONFIG_SYS_NAND_U_BOOT_DST	(0x00200000 - CONFIG_SPL_MAX_SIZE)
 #define CONFIG_SYS_NAND_U_BOOT_START	0x00200000
 #define CONFIG_SYS_NAND_U_BOOT_OFFS	0
@@ -55,7 +55,7 @@
 #endif
 
 #ifndef CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_TEXT_BASE		0x8ff80000
+#define CONFIG_SYS_TEXT_BASE		0x8ff40000
 #endif
 
 #ifndef CONFIG_RESET_VECTOR_ADDRESS
@@ -71,7 +71,6 @@
 /* High Level Configuration Options */
 #define CONFIG_BOOKE			/* BOOKE */
 #define CONFIG_E500			/* BOOKE e500 family */
-#define CONFIG_MPC85xx
 #define CONFIG_FSL_IFC			/* Enable IFC Support */
 #define CONFIG_SYS_HAS_SERDES		/* common SERDES init code */
 
@@ -134,7 +133,7 @@
 #define CONFIG_SYS_MEMTEST_END		0x01ffffff
 
 /* DDR Setup */
-#define CONFIG_FSL_DDR3
+#define CONFIG_SYS_FSL_DDR3
 #define CONFIG_SYS_SPD_BUS_NUM		0
 #define SPD_EEPROM_ADDRESS1		0x54 /* I2C access */
 #define SPD_EEPROM_ADDRESS2		0x56 /* I2C access */
@@ -540,6 +539,7 @@ combinations. this should be removed later
  */
 #if defined(CONFIG_RAMBOOT_SDCARD)
 #define CONFIG_ENV_IS_IN_MMC
+#define CONFIG_FSL_FIXED_MMC_LOCATION
 #define CONFIG_SYS_MMC_ENV_DEV		0
 #define CONFIG_ENV_SIZE			0x2000
 #elif defined(CONFIG_RAMBOOT_SPIFLASH)
@@ -554,7 +554,7 @@ combinations. this should be removed later
 #elif defined(CONFIG_NAND)
 #define CONFIG_ENV_IS_IN_NAND
 #define CONFIG_ENV_SIZE		CONFIG_SYS_NAND_BLOCK_SIZE
-#define CONFIG_ENV_OFFSET	((512 * 1024) + CONFIG_SYS_NAND_BLOCK_SIZE)
+#define CONFIG_ENV_OFFSET	((768 * 1024) + CONFIG_SYS_NAND_BLOCK_SIZE)
 #define CONFIG_ENV_RANGE	(3 * CONFIG_ENV_SIZE)
 #elif defined(CONFIG_SYS_RAMBOOT)
 #define CONFIG_ENV_IS_NOWHERE		/* Store ENV in memory only */
@@ -562,13 +562,9 @@ combinations. this should be removed later
 #define CONFIG_ENV_SIZE			0x2000
 #else
 #define CONFIG_ENV_IS_IN_FLASH
-#if CONFIG_SYS_MONITOR_BASE > 0xfff80000
-#define CONFIG_ENV_ADDR	0xfff80000
-#else
 #define CONFIG_ENV_ADDR	(CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
-#endif
 #define CONFIG_ENV_SIZE		0x2000
-#define CONFIG_ENV_SECT_SIZE	0x20000 /* 128K (one sector) */
+#define CONFIG_ENV_SECT_SIZE	0x20000
 #endif
 
 #define CONFIG_LOADS_ECHO		/* echo on for serial download */
@@ -603,7 +599,6 @@ combinations. this should be removed later
 #define CONFIG_CMDLINE_EDITING			/* Command-line editing */
 #define CONFIG_AUTO_COMPLETE			/* add autocompletion support */
 #define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
-#define CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt */
 
 #if defined(CONFIG_CMD_KGDB)
 #define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size */
@@ -614,7 +609,6 @@ combinations. this should be removed later
 						/* Print Buffer Size */
 #define CONFIG_SYS_MAXARGS	16		/* max number of command args */
 #define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
-#define CONFIG_SYS_HZ		1000		/* decrementer freq:1ms ticks */
 
 
 /*
@@ -627,7 +621,6 @@ combinations. this should be removed later
 
 #if defined(CONFIG_CMD_KGDB)
 #define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
-#define CONFIG_KGDB_SER_INDEX	2	/* which serial port to use */
 #endif
 
 /*
diff --git a/include/configs/C29XPCIE.h b/include/configs/C29XPCIE.h
index 83779eff86..92913c8e79 100644
--- a/include/configs/C29XPCIE.h
+++ b/include/configs/C29XPCIE.h
@@ -20,25 +20,73 @@
 #ifdef CONFIG_SPIFLASH
 #define CONFIG_RAMBOOT_SPIFLASH
 #define CONFIG_SYS_TEXT_BASE		0x11000000
-#define CONFIG_RESET_VECTOR_ADDRESS	0x1107fffc
+#define CONFIG_RESET_VECTOR_ADDRESS	0x110bfffc
+#endif
+
+#ifdef CONFIG_NAND
+#define CONFIG_SPL
+#define CONFIG_TPL
+#ifdef CONFIG_TPL_BUILD
+#define CONFIG_SPL_NAND_BOOT
+#define CONFIG_SPL_FLUSH_IMAGE
+#define CONFIG_SPL_ENV_SUPPORT
+#define CONFIG_SPL_NAND_INIT
+#define CONFIG_SPL_SERIAL_SUPPORT
+#define CONFIG_SPL_LIBGENERIC_SUPPORT
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+#define CONFIG_SPL_I2C_SUPPORT
+#define CONFIG_SPL_DRIVERS_MISC_SUPPORT
+#define CONFIG_SPL_NAND_SUPPORT
+#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
+#define CONFIG_SPL_COMMON_INIT_DDR
+#define CONFIG_SPL_MAX_SIZE		(128 << 10)
+#define CONFIG_SPL_TEXT_BASE		0xf8f81000
+#define CONFIG_SYS_MPC85XX_NO_RESETVEC
+#define CONFIG_SYS_NAND_U_BOOT_SIZE	(832 << 10)
+#define CONFIG_SYS_NAND_U_BOOT_DST	(0x11000000)
+#define CONFIG_SYS_NAND_U_BOOT_START	(0x11000000)
+#define CONFIG_SYS_NAND_U_BOOT_OFFS	((128 + 128) << 10)
+#elif defined(CONFIG_SPL_BUILD)
+#define CONFIG_SPL_INIT_MINIMAL
+#define CONFIG_SPL_SERIAL_SUPPORT
+#define CONFIG_SPL_NAND_SUPPORT
+#define CONFIG_SPL_NAND_MINIMAL
+#define CONFIG_SPL_FLUSH_IMAGE
+#define CONFIG_SPL_TEXT_BASE		0xff800000
+#define CONFIG_SPL_MAX_SIZE		8192
+#define CONFIG_SYS_NAND_U_BOOT_SIZE	(128 << 10)
+#define CONFIG_SYS_NAND_U_BOOT_DST	0xf8f80000
+#define CONFIG_SYS_NAND_U_BOOT_START	0xf8f80000
+#define CONFIG_SYS_NAND_U_BOOT_OFFS	(128 << 10)
+#endif
+#define CONFIG_SPL_PAD_TO		0x20000
+#define CONFIG_TPL_PAD_TO		0x20000
+#define CONFIG_SPL_TARGET		"u-boot-with-spl.bin"
+#define CONFIG_SYS_TEXT_BASE		0x11001000
+#define CONFIG_SYS_LDSCRIPT	"arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
 #endif
 
 #ifndef CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_TEXT_BASE		0xeff80000
+#define CONFIG_SYS_TEXT_BASE		0xeff40000
 #endif
 
 #ifndef CONFIG_RESET_VECTOR_ADDRESS
 #define CONFIG_RESET_VECTOR_ADDRESS	0xeffffffc
 #endif
 
-#ifndef CONFIG_SYS_MONITOR_BASE
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SPL_TEXT_BASE
+#else
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE	/* start of monitor */
+#endif
+
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
 #endif
 
 /* High Level Configuration Options */
 #define CONFIG_BOOKE			/* BOOKE */
 #define CONFIG_E500			/* BOOKE e500 family */
-#define CONFIG_MPC85xx
 #define CONFIG_FSL_IFC			/* Enable IFC Support */
 #define CONFIG_SYS_HAS_SERDES		/* common SERDES init code */
 
@@ -103,7 +151,7 @@
 #define CONFIG_PANIC_HANG
 
 /* DDR Setup */
-#define CONFIG_FSL_DDR3
+#define CONFIG_SYS_FSL_DDR3
 #define CONFIG_DDR_SPD
 #define CONFIG_SYS_SPD_BUS_NUM		0
 #define SPD_EEPROM_ADDRESS		0x50
@@ -130,6 +178,10 @@
 			(0xf00000000ull | CONFIG_SYS_PLATFORM_SRAM_BASE)
 #define CONFIG_SYS_PLATFORM_SRAM_SIZE	(512 << 10)
 
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SYS_NO_FLASH
+#endif
+
 /*
  * IFC Definitions
  */
@@ -154,14 +206,16 @@
 				CSPR_V)
 #define CONFIG_SYS_NOR_AMASK	IFC_AMASK(64*1024*1024)
 #define CONFIG_SYS_NOR_CSOR	CSOR_NOR_ADM_SHIFT(4)
+
 #define CONFIG_SYS_NOR_FTIM0	(FTIM0_NOR_TACSE(0x4) | \
 				FTIM0_NOR_TEADC(0x5) | \
 				FTIM0_NOR_TEAHC(0x5))
-#define CONFIG_SYS_NOR_FTIM1	(FTIM1_NOR_TACO(0x1e) | \
-				FTIM1_NOR_TRAD_NOR(0x0f) | \
-				FTIM1_NOR_TSEQRAD_NOR(0x0f))
+#define CONFIG_SYS_NOR_FTIM1	(FTIM1_NOR_TACO(0x35) | \
+				FTIM1_NOR_TRAD_NOR(0x1A) |\
+				FTIM1_NOR_TSEQRAD_NOR(0x13))
 #define CONFIG_SYS_NOR_FTIM2	(FTIM2_NOR_TCS(0x4) | \
 				FTIM2_NOR_TCH(0x4) | \
+				FTIM2_NOR_TWPH(0x0E) | \
 				FTIM2_NOR_TWP(0x1c))
 #define CONFIG_SYS_NOR_FTIM3	0x0
 
@@ -181,7 +235,7 @@
 #define CONFIG_SYS_MAX_NAND_DEVICE	1
 #define CONFIG_MTD_NAND_VERIFY_WRITE
 #define CONFIG_CMD_NAND
-#define CONFIG_SYS_NAND_BLOCK_SIZE	(128 * 1024)
+#define CONFIG_SYS_NAND_BLOCK_SIZE	(1024 * 1024)
 
 /* 8Bit NAND Flash - K9F1G08U0B */
 #define CONFIG_SYS_NAND_CSPR	(CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
@@ -189,13 +243,14 @@
 				| CSPR_MSEL_NAND \
 				| CSPR_V)
 #define CONFIG_SYS_NAND_AMASK	IFC_AMASK(64*1024)
+#define CONFIG_SYS_NAND_OOBSIZE	0x00000280	/* 640b */
 #define CONFIG_SYS_NAND_CSOR	(CSOR_NAND_ECC_ENC_EN	/* ECC on encode */ \
 				| CSOR_NAND_ECC_DEC_EN	/* ECC on decode */ \
 				| CSOR_NAND_ECC_MODE_4	/* 4-bit ECC */ \
-				| CSOR_NAND_RAL_2	/* RAL = 2 Bytes */ \
-				| CSOR_NAND_PGS_2K	/* Page Size = 2k */ \
-				| CSOR_NAND_SPRZ_64	/* Spare size = 64 */ \
-				| CSOR_NAND_PB(64))	/* 64 Pages Per Block */
+				| CSOR_NAND_RAL_3	/* RAL = 3 Bytes */ \
+				| CSOR_NAND_PGS_8K	/* Page Size = 8K */ \
+				| CSOR_NAND_SPRZ_CSOR_EXT /*oob in csor_ext*/\
+				| CSOR_NAND_PB(128))	/*128 Pages Per Block*/
 #define CONFIG_SYS_NAND_FTIM0	(FTIM0_NAND_TCCST(0x01) | \
 				FTIM0_NAND_TWP(0x0c)   | \
 				FTIM0_NAND_TWCHT(0x08) | \
@@ -212,6 +267,23 @@
 #define CONFIG_SYS_NAND_DDR_LAW		11
 
 /* Set up IFC registers for boot location NOR/NAND */
+#ifdef CONFIG_NAND
+#define CONFIG_SYS_CSPR0		CONFIG_SYS_NAND_CSPR
+#define CONFIG_SYS_AMASK0		CONFIG_SYS_NAND_AMASK
+#define CONFIG_SYS_CSOR0		CONFIG_SYS_NAND_CSOR
+#define CONFIG_SYS_CSOR0_EXT		CONFIG_SYS_NAND_OOBSIZE
+#define CONFIG_SYS_CS0_FTIM0		CONFIG_SYS_NAND_FTIM0
+#define CONFIG_SYS_CS0_FTIM1		CONFIG_SYS_NAND_FTIM1
+#define CONFIG_SYS_CS0_FTIM2		CONFIG_SYS_NAND_FTIM2
+#define CONFIG_SYS_CS0_FTIM3		CONFIG_SYS_NAND_FTIM3
+#define CONFIG_SYS_CSPR1		CONFIG_SYS_NOR_CSPR
+#define CONFIG_SYS_AMASK1		CONFIG_SYS_NOR_AMASK
+#define CONFIG_SYS_CSOR1		CONFIG_SYS_NOR_CSOR
+#define CONFIG_SYS_CS1_FTIM0		CONFIG_SYS_NOR_FTIM0
+#define CONFIG_SYS_CS1_FTIM1		CONFIG_SYS_NOR_FTIM1
+#define CONFIG_SYS_CS1_FTIM2		CONFIG_SYS_NOR_FTIM2
+#define CONFIG_SYS_CS1_FTIM3		CONFIG_SYS_NOR_FTIM3
+#else
 #define CONFIG_SYS_CSPR0		CONFIG_SYS_NOR_CSPR
 #define CONFIG_SYS_AMASK0		CONFIG_SYS_NOR_AMASK
 #define CONFIG_SYS_CSOR0		CONFIG_SYS_NOR_CSOR
@@ -222,10 +294,12 @@
 #define CONFIG_SYS_CSPR1		CONFIG_SYS_NAND_CSPR
 #define CONFIG_SYS_AMASK1		CONFIG_SYS_NAND_AMASK
 #define CONFIG_SYS_CSOR1		CONFIG_SYS_NAND_CSOR
+#define CONFIG_SYS_CSOR1_EXT		CONFIG_SYS_NAND_OOBSIZE
 #define CONFIG_SYS_CS1_FTIM0		CONFIG_SYS_NAND_FTIM0
 #define CONFIG_SYS_CS1_FTIM1		CONFIG_SYS_NAND_FTIM1
 #define CONFIG_SYS_CS1_FTIM2		CONFIG_SYS_NAND_FTIM2
 #define CONFIG_SYS_CS1_FTIM3		CONFIG_SYS_NAND_FTIM3
+#endif
 
 /* CPLD on IFC, selected by CS2 */
 #define CONFIG_SYS_CPLD_BASE		0xffdf0000
@@ -265,7 +339,44 @@
 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 #define CONFIG_SYS_MONITOR_LEN		(512 * 1024)
-#define CONFIG_SYS_MALLOC_LEN		(1024 * 1024)
+#define CONFIG_SYS_MALLOC_LEN		(2 * 1024 * 1024)
+
+/*
+ * Config the L2 Cache as L2 SRAM
+ */
+#if defined(CONFIG_SPL_BUILD)
+#if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH)
+#define CONFIG_SYS_INIT_L2_ADDR		0xf8f80000
+#define CONFIG_SYS_INIT_L2_ADDR_PHYS	CONFIG_SYS_INIT_L2_ADDR
+#define CONFIG_SYS_L2_SIZE		(256 << 10)
+#define CONFIG_SYS_INIT_L2_END	(CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
+#define CONFIG_SPL_RELOC_TEXT_BASE	0xf8f81000
+#define CONFIG_SPL_RELOC_STACK		(CONFIG_SYS_INIT_L2_ADDR + 128 * 1024)
+#define CONFIG_SPL_RELOC_STACK_SIZE	(32 << 10)
+#define CONFIG_SPL_RELOC_MALLOC_ADDR	(CONFIG_SYS_INIT_L2_ADDR + 160 * 1024)
+#define CONFIG_SPL_RELOC_MALLOC_SIZE	(96 << 10)
+#define CONFIG_SPL_GD_ADDR		(CONFIG_SYS_INIT_L2_ADDR + 112 * 1024)
+#elif defined(CONFIG_NAND)
+#ifdef CONFIG_TPL_BUILD
+#define CONFIG_SYS_INIT_L2_ADDR		0xf8f80000
+#define CONFIG_SYS_INIT_L2_ADDR_PHYS	CONFIG_SYS_INIT_L2_ADDR
+#define CONFIG_SYS_L2_SIZE		(256 << 10)
+#define CONFIG_SYS_INIT_L2_END	(CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
+#define CONFIG_SPL_RELOC_TEXT_BASE	0xf8f81000
+#define CONFIG_SPL_RELOC_STACK		(CONFIG_SYS_INIT_L2_ADDR + 192 * 1024)
+#define CONFIG_SPL_RELOC_MALLOC_ADDR	(CONFIG_SYS_INIT_L2_ADDR + 208 * 1024)
+#define CONFIG_SPL_RELOC_MALLOC_SIZE	(48 << 10)
+#define CONFIG_SPL_GD_ADDR		(CONFIG_SYS_INIT_L2_ADDR + 176 * 1024)
+#else
+#define CONFIG_SYS_INIT_L2_ADDR		0xf8f80000
+#define CONFIG_SYS_INIT_L2_ADDR_PHYS	CONFIG_SYS_INIT_L2_ADDR
+#define CONFIG_SYS_L2_SIZE		(256 << 10)
+#define CONFIG_SYS_INIT_L2_END	(CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
+#define CONFIG_SPL_RELOC_TEXT_BASE	(CONFIG_SYS_INIT_L2_END - 0x3000)
+#define CONFIG_SPL_RELOC_STACK		((CONFIG_SYS_INIT_L2_END - 1) & ~0xF)
+#endif
+#endif
+#endif
 
 /* Serial Port */
 #define CONFIG_CONS_INDEX	1
@@ -274,6 +385,10 @@
 #define CONFIG_SYS_NS16550_REG_SIZE	1
 #define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)
 
+#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL)
+#define CONFIG_NS16550_MIN_FUNCTIONS
+#endif
+
 #define CONFIG_SERIAL_MULTI		/* Enable both serial ports */
 #define CONFIG_SYS_CONSOLE_IS_IN_ENV
 
@@ -360,13 +475,19 @@
 #define CONFIG_ENV_SECT_SIZE	0x10000
 #define CONFIG_ENV_SIZE		0x2000
 #endif
+#elif defined(CONFIG_NAND)
+#define CONFIG_ENV_IS_IN_NAND
+#ifdef CONFIG_TPL_BUILD
+#define CONFIG_ENV_SIZE		0x2000
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_INIT_L2_ADDR + (160 << 10))
 #else
-#define CONFIG_ENV_IS_IN_FLASH
-#if CONFIG_SYS_MONITOR_BASE > 0xfff80000
-#define CONFIG_ENV_ADDR	0xfff80000
+#define CONFIG_ENV_SIZE		CONFIG_SYS_NAND_BLOCK_SIZE
+#define CONFIG_ENV_RANGE	CONFIG_ENV_SIZE
+#endif
+#define CONFIG_ENV_OFFSET	CONFIG_SYS_NAND_BLOCK_SIZE
 #else
+#define CONFIG_ENV_IS_IN_FLASH
 #define CONFIG_ENV_ADDR	(CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
-#endif
 #define CONFIG_ENV_SIZE		0x2000
 #define CONFIG_ENV_SECT_SIZE	0x20000
 #endif
@@ -394,14 +515,12 @@
 #define CONFIG_CMDLINE_EDITING			/* Command-line editing */
 #define CONFIG_AUTO_COMPLETE			/* add autocompletion support */
 #define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
-#define CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt */
 
 #define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size */
 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
 						/* Print Buffer Size */
 #define CONFIG_SYS_MAXARGS	16		/* max number of command args */
 #define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
-#define CONFIG_SYS_HZ		1000		/* dec freq: 1ms ticks */
 
 /*
  * For booting Linux, the board info and command line data
@@ -431,6 +550,8 @@
 
 #define CONFIG_BAUDRATE		115200
 
+#define CONFIG_DEF_HWCONFIG	fsl_ddr:ecc=on
+
 #define	CONFIG_EXTRA_ENV_SETTINGS				\
 	"hwconfig=" __stringify(CONFIG_DEF_HWCONFIG)  "\0"	\
 	"netdev=eth0\0"						\
diff --git a/include/configs/CATcenter.h b/include/configs/CATcenter.h
index 47aec5f06c..27539d27d7 100644
--- a/include/configs/CATcenter.h
+++ b/include/configs/CATcenter.h
@@ -59,7 +59,6 @@
  */
 
 #define CONFIG_405EP		1	/* This is a PPC405 CPU		*/
-#define CONFIG_4xx		1	/* ...member of PPC4xx family	*/
 #define CONFIG_PPCHAMELEONEVB	1	/* ...on a PPChameleonEVB board */
 
 #define	CONFIG_SYS_TEXT_BASE	0xFFFB0000	/* Reserve 320 kB for Monitor */
@@ -154,7 +153,6 @@
  * Miscellaneous configurable options
  */
 #define CONFIG_SYS_LONGHELP			/* undef to save memory		*/
-#define CONFIG_SYS_PROMPT		"=> "	/* Monitor Command Prompt	*/
 
 #define	CONFIG_SYS_HUSH_PARSER			/* use "hush" command parser	*/
 
@@ -185,8 +183,6 @@
 #define CONFIG_SYS_LOAD_ADDR	0x100000	/* default load address */
 #define CONFIG_SYS_EXTBDINFO	1		/* To use extended board_into (bd_t) */
 
-#define CONFIG_SYS_HZ		1000		/* decrementer freq: 1 ms ticks */
-
 #define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */
 
 /*-----------------------------------------------------------------------
diff --git a/include/configs/CMS700.h b/include/configs/CMS700.h
index bd5d4e904b..5b872f61a0 100644
--- a/include/configs/CMS700.h
+++ b/include/configs/CMS700.h
@@ -18,7 +18,6 @@
  */
 
 #define CONFIG_405EP		1	/* This is a PPC405 CPU		*/
-#define CONFIG_4xx		1	/* ...member of PPC4xx family	*/
 #define CONFIG_VOM405		1	/* ...on a VOM405 board		*/
 
 #define	CONFIG_SYS_TEXT_BASE	0xFFFC8000
@@ -84,7 +83,6 @@
  * Miscellaneous configurable options
  */
 #define CONFIG_SYS_LONGHELP			/* undef to save memory		*/
-#define CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt	*/
 
 #undef	CONFIG_SYS_HUSH_PARSER			/* use "hush" command parser	*/
 
@@ -121,8 +119,6 @@
 #define CONFIG_SYS_LOAD_ADDR	0x100000	/* default load address */
 #define CONFIG_SYS_EXTBDINFO	1		/* To use extended board_into (bd_t) */
 
-#define CONFIG_SYS_HZ		1000		/* decrementer freq: 1 ms ticks */
-
 #define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */
 
 #define CONFIG_VERSION_VARIABLE 1	/* include version env variable */
@@ -152,6 +148,9 @@
 #define CONFIG_SYS_NAND_SKIP_BAD_DOT_I 1       /* ".i" read skips bad blocks   */
 #define CONFIG_SYS_NAND_QUIET          1
 
+#define CONFIG_SYS_NAND_MAX_OOBFREE	2
+#define CONFIG_SYS_NAND_MAX_ECCPOS	48
+
 /*
  * For booting Linux, the board info and command line data
  * have to be in the first 8 MB of memory, since this is
diff --git a/include/configs/CPC45.h b/include/configs/CPC45.h
index a01592168d..a75c52f2c7 100644
--- a/include/configs/CPC45.h
+++ b/include/configs/CPC45.h
@@ -25,7 +25,6 @@
  * (easy to change)
  */
 
-#define CONFIG_MPC824X		1
 #define CONFIG_MPC8245		1
 #define CONFIG_CPC45		1
 
@@ -74,7 +73,6 @@
  * Miscellaneous configurable options
  */
 #define CONFIG_SYS_LONGHELP			/* undef to save memory		*/
-#define CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt	*/
 #define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
 
 #if 1
@@ -180,7 +178,6 @@
  */
 
 #define CONFIG_SYS_CLK_FREQ	33000000
-#define CONFIG_SYS_HZ			1000
 
 
 /* Bit-field values for MCCR1.
diff --git a/include/configs/CPCI2DP.h b/include/configs/CPCI2DP.h
index f522d45090..05106cde90 100644
--- a/include/configs/CPCI2DP.h
+++ b/include/configs/CPCI2DP.h
@@ -18,7 +18,6 @@
  */
 
 #define CONFIG_405GP		1	/* This is a PPC405 CPU		*/
-#define CONFIG_4xx		1	/* ...member of PPC4xx family	*/
 
 #define	CONFIG_SYS_TEXT_BASE	0xFFFC0000
 
@@ -72,7 +71,6 @@
  * Miscellaneous configurable options
  */
 #define CONFIG_SYS_LONGHELP			/* undef to save memory		*/
-#define CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt	*/
 
 #undef	CONFIG_SYS_HUSH_PARSER			/* use "hush" command parser	*/
 
@@ -111,8 +109,6 @@
 #define CONFIG_SYS_LOAD_ADDR	0x100000	/* default load address */
 #define CONFIG_SYS_EXTBDINFO	1		/* To use extended board_into (bd_t) */
 
-#define CONFIG_SYS_HZ		1000		/* decrementer freq: 1 ms ticks */
-
 #define CONFIG_LOOPW            1       /* enable loopw command         */
 
 #define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */
diff --git a/include/configs/CPCI405.h b/include/configs/CPCI405.h
index ca716a2a7d..34252d4d3b 100644
--- a/include/configs/CPCI405.h
+++ b/include/configs/CPCI405.h
@@ -18,7 +18,6 @@
  */
 
 #define CONFIG_405GP		1	/* This is a PPC405 CPU		*/
-#define CONFIG_4xx		1	/* ...member of PPC4xx family	*/
 #define CONFIG_CPCI405		1	/* ...on a CPCI405 board	*/
 
 #define	CONFIG_SYS_TEXT_BASE	0xFFFC0000
@@ -87,7 +86,6 @@
  * Miscellaneous configurable options
  */
 #define CONFIG_SYS_LONGHELP			/* undef to save memory		*/
-#define CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt	*/
 
 #undef	CONFIG_SYS_HUSH_PARSER			/* use "hush" command parser	*/
 
@@ -124,8 +122,6 @@
 #define CONFIG_SYS_LOAD_ADDR	0x100000	/* default load address */
 #define CONFIG_SYS_EXTBDINFO	1		/* To use extended board_into (bd_t) */
 
-#define CONFIG_SYS_HZ		1000		/* decrementer freq: 1 ms ticks */
-
 #define CONFIG_LOOPW            1       /* enable loopw command         */
 
 #define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */
diff --git a/include/configs/CPCI4052.h b/include/configs/CPCI4052.h
index e11e85fc1b..bf85439802 100644
--- a/include/configs/CPCI4052.h
+++ b/include/configs/CPCI4052.h
@@ -18,7 +18,6 @@
  */
 
 #define CONFIG_405GP		1	/* This is a PPC405 CPU		*/
-#define CONFIG_4xx		1	/* ...member of PPC4xx family	*/
 #define CONFIG_CPCI405		1	/* ...on a CPCI405 board	*/
 #define CONFIG_CPCI405_VER2	1	/* ...version 2			*/
 #undef  CONFIG_CPCI405_6U               /* enable this for 6U boards    */
@@ -94,7 +93,6 @@
  * Miscellaneous configurable options
  */
 #define CONFIG_SYS_LONGHELP			/* undef to save memory		*/
-#define CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt	*/
 
 #undef	CONFIG_SYS_HUSH_PARSER			/* use "hush" command parser	*/
 
@@ -133,8 +131,6 @@
 #define CONFIG_SYS_LOAD_ADDR	0x100000	/* default load address */
 #define CONFIG_SYS_EXTBDINFO	1		/* To use extended board_into (bd_t) */
 
-#define CONFIG_SYS_HZ		1000		/* decrementer freq: 1 ms ticks */
-
 #define CONFIG_CMDLINE_EDITING		/* add command line history	*/
 
 #define CONFIG_LOOPW            1       /* enable loopw command         */
diff --git a/include/configs/CPCI405AB.h b/include/configs/CPCI405AB.h
index 44e691eaf2..7d58e9d13f 100644
--- a/include/configs/CPCI405AB.h
+++ b/include/configs/CPCI405AB.h
@@ -18,7 +18,6 @@
  */
 
 #define CONFIG_405GP		1	/* This is a PPC405 CPU		*/
-#define CONFIG_4xx		1	/* ...member of PPC4xx family	*/
 #define CONFIG_CPCI405		1	/* ...on a CPCI405 board	*/
 #define CONFIG_CPCI405_VER2	1	/* ...version 2			*/
 #define CONFIG_CPCI405AB	1	/* ...and special AB version	*/
@@ -95,7 +94,6 @@
  * Miscellaneous configurable options
  */
 #define CONFIG_SYS_LONGHELP			/* undef to save memory		*/
-#define CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt	*/
 
 #undef	CONFIG_SYS_HUSH_PARSER			/* use "hush" command parser	*/
 
@@ -132,8 +130,6 @@
 #define CONFIG_SYS_LOAD_ADDR	0x100000	/* default load address */
 #define CONFIG_SYS_EXTBDINFO	1		/* To use extended board_into (bd_t) */
 
-#define CONFIG_SYS_HZ		1000		/* decrementer freq: 1 ms ticks */
-
 #define CONFIG_CMDLINE_EDITING		/* add command line history	*/
 
 #define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */
diff --git a/include/configs/CPCI405DT.h b/include/configs/CPCI405DT.h
index 746b076912..c2598a3026 100644
--- a/include/configs/CPCI405DT.h
+++ b/include/configs/CPCI405DT.h
@@ -18,7 +18,6 @@
  */
 
 #define CONFIG_405GP		1	/* This is a PPC405 CPU		*/
-#define CONFIG_4xx		1	/* ...member of PPC4xx family	*/
 #define CONFIG_CPCI405		1	/* ...on a CPCI405 board	*/
 #define CONFIG_CPCI405_VER2	1	/* ...version 2			*/
 
@@ -95,7 +94,6 @@
  * Miscellaneous configurable options
  */
 #define CONFIG_SYS_LONGHELP			/* undef to save memory		*/
-#define CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt	*/
 
 #undef	CONFIG_SYS_HUSH_PARSER			/* use "hush" command parser	*/
 
@@ -134,8 +132,6 @@
 #define CONFIG_SYS_LOAD_ADDR	0x100000	/* default load address */
 #define CONFIG_SYS_EXTBDINFO	1		/* To use extended board_into (bd_t) */
 
-#define CONFIG_SYS_HZ		1000		/* decrementer freq: 1 ms ticks */
-
 #define CONFIG_LOOPW            1       /* enable loopw command         */
 
 #define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */
diff --git a/include/configs/CPCI750.h b/include/configs/CPCI750.h
index 0d561c7e85..304a12bea9 100644
--- a/include/configs/CPCI750.h
+++ b/include/configs/CPCI750.h
@@ -174,7 +174,6 @@
 
 #define CONFIG_SYS_GT_DUAL_CPU			/* also for JTAG even with one cpu */
 #define CONFIG_SYS_LONGHELP			/* undef to save memory		*/
-#define CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt	*/
 #if defined(CONFIG_CMD_KGDB)
 #define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
 #else
@@ -219,7 +218,6 @@
 
 #define CONFIG_SYS_LOAD_ADDR		0x00300000	/* default load address */
 
-#define CONFIG_SYS_HZ			1000		/* decr freq: 1ms ticks */
 #define CONFIG_SYS_BUS_CLK		133000000	/* 133 MHz (CPU = 5*Bus = 666MHz)		*/
 
 #define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
diff --git a/include/configs/CPCIISER4.h b/include/configs/CPCIISER4.h
index dc4df29455..25365f747c 100644
--- a/include/configs/CPCIISER4.h
+++ b/include/configs/CPCIISER4.h
@@ -18,7 +18,6 @@
  */
 
 #define CONFIG_405GP		1	/* This is a PPC405 CPU		*/
-#define CONFIG_4xx		1	/* ...member of PPC4xx family	*/
 #define CONFIG_CPCIISER4	1	/* ...on a CPCIISER4 board	*/
 
 #define	CONFIG_SYS_TEXT_BASE	0xFFFC0000
@@ -80,7 +79,6 @@
  * Miscellaneous configurable options
  */
 #define CONFIG_SYS_LONGHELP			/* undef to save memory		*/
-#define CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt	*/
 #if defined(CONFIG_CMD_KGDB)
 #define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
 #else
@@ -111,8 +109,6 @@
 #define CONFIG_SYS_LOAD_ADDR	0x100000	/* default load address */
 #define CONFIG_SYS_EXTBDINFO	1		/* To use extended board_into (bd_t) */
 
-#define CONFIG_SYS_HZ		1000		/* decrementer freq: 1 ms ticks */
-
 #define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */
 
 /*-----------------------------------------------------------------------
diff --git a/include/configs/CPU86.h b/include/configs/CPU86.h
index a85a418fb1..7be83b0787 100644
--- a/include/configs/CPU86.h
+++ b/include/configs/CPU86.h
@@ -17,7 +17,6 @@
  * (easy to change)
  */
 
-#define CONFIG_MPC8260		1	/* This is an MPC8260 CPU		*/
 #define CONFIG_CPU86		1	/* ...on a CPU86 board	*/
 #define CONFIG_CPM2		1	/* Has a CPM2 */
 
@@ -171,7 +170,6 @@
  * Miscellaneous configurable options
  */
 #define	CONFIG_SYS_LONGHELP			/* undef to save memory		*/
-#define	CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt	*/
 #if defined(CONFIG_CMD_KGDB)
 #define	CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
 #else
@@ -186,8 +184,6 @@
 
 #define	CONFIG_SYS_LOAD_ADDR	0x100000	/* default load address	*/
 
-#define	CONFIG_SYS_HZ		1000		/* decrementer freq: 1 ms ticks	*/
-
 #define	CONFIG_SYS_RESET_ADDRESS 0xFFF00100	/* "bad" address		*/
 
 /*
diff --git a/include/configs/CPU87.h b/include/configs/CPU87.h
index d975f0daad..d3a59e8ba7 100644
--- a/include/configs/CPU87.h
+++ b/include/configs/CPU87.h
@@ -17,7 +17,6 @@
  * (easy to change)
  */
 
-#define CONFIG_MPC8260		1	/* This is an MPC8260 CPU		*/
 #define CONFIG_CPU87		1	/* ...on a CPU87 board	*/
 #define CONFIG_PCI
 #define CONFIG_CPM2		1	/* Has a CPM2 */
@@ -185,7 +184,6 @@
  * Miscellaneous configurable options
  */
 #define CONFIG_SYS_LONGHELP			/* undef to save memory		*/
-#define CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt	*/
 #if defined(CONFIG_CMD_KGDB)
 #define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
 #else
@@ -200,8 +198,6 @@
 
 #define CONFIG_SYS_LOAD_ADDR	0x100000	/* default load address */
 
-#define CONFIG_SYS_HZ		1000		/* decrementer freq: 1 ms ticks */
-
 #define CONFIG_SYS_RESET_ADDRESS 0xFFF00100	/* "bad" address		*/
 
 #define CONFIG_LOOPW
diff --git a/include/configs/CRAYL1.h b/include/configs/CRAYL1.h
index 781a3b4d1d..788fa0f91c 100644
--- a/include/configs/CRAYL1.h
+++ b/include/configs/CRAYL1.h
@@ -19,7 +19,6 @@
  */
 
 #define CONFIG_405GP		1	/* This is a PPC405 CPU	*/
-#define CONFIG_4xx		    1   /* ...member of PPC405 family */
 
 /*
  * Note: I make an "image" from U-Boot itself, which prefixes 0x40
@@ -70,7 +69,6 @@
 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
 #define CONFIG_IDENT_STRING     "Cray L1"
 #define CONFIG_ENV_OVERWRITE     1
-#define	CONFIG_SYS_HZ		             1000	/* decrementer freq: 1 ms ticks	*/
 #define CONFIG_SYS_HUSH_PARSER			1
 #define CONFIG_SOURCE			1
 
@@ -130,7 +128,6 @@
 /*
  * Miscellaneous configurable options
  */
-#define CONFIG_SYS_PROMPT	"=> "				/* Monitor Command Prompt	*/
 #define	CONFIG_SYS_CBSIZE	256				/* Console I/O Buffer Size	*/
 #define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE			/* Boot Argument Buffer Size	*/
 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)	/* Print Buffer Size */
diff --git a/include/configs/CU824.h b/include/configs/CU824.h
index f6f05a45ac..dc98a560c8 100644
--- a/include/configs/CU824.h
+++ b/include/configs/CU824.h
@@ -25,7 +25,6 @@
  * (easy to change)
  */
 
-#define CONFIG_MPC824X		1
 #define CONFIG_MPC8240		1
 #define CONFIG_CU824		1
 
@@ -68,7 +67,6 @@
  * Miscellaneous configurable options
  */
 #define CONFIG_SYS_LONGHELP			/* undef to save memory		*/
-#define CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt	*/
 #define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
 
 #if 1
@@ -144,7 +142,6 @@
  */
 
 #define CONFIG_SYS_CLK_FREQ  33000000
-#define CONFIG_SYS_HZ		     1000
 
 	/* Bit-field values for MCCR1.
 	 */
diff --git a/include/configs/DB64360.h b/include/configs/DB64360.h
index bd230eceb0..b77c8b2894 100644
--- a/include/configs/DB64360.h
+++ b/include/configs/DB64360.h
@@ -255,7 +255,6 @@ ip=${ipaddr}:${serverip}${bootargs_end}; bootm 0x400000;\0"
 
 /* #define CONFIG_SYS_GT_DUAL_CPU	 also for JTAG even with one cpu */
 #define CONFIG_SYS_LONGHELP			/* undef to save memory		*/
-#define CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt	*/
 #if defined(CONFIG_CMD_KGDB)
 #define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
 #else
@@ -300,7 +299,6 @@ ip=${ipaddr}:${serverip}${bootargs_end}; bootm 0x400000;\0"
 
 #define CONFIG_SYS_LOAD_ADDR		0x00400000	/* default load address */
 
-#define CONFIG_SYS_HZ			1000		/* decr freq: 1ms ticks */
 /*ronen - this the Sys clock (cpu bus,internal dram and SDRAM) */
 #define CONFIG_SYS_BUS_CLK		133000000	/* 133 MHz (CPU = 5*Bus = 666MHz)		*/
 
diff --git a/include/configs/DB64460.h b/include/configs/DB64460.h
index 9f24eafd95..abc443499c 100644
--- a/include/configs/DB64460.h
+++ b/include/configs/DB64460.h
@@ -193,7 +193,6 @@ ip=${ipaddr}:${serverip}${bootargs_end}; bootm 0x400000;\0"
 
 /* #define CONFIG_SYS_GT_DUAL_CPU	 also for JTAG even with one cpu */
 #define CONFIG_SYS_LONGHELP			/* undef to save memory		*/
-#define CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt	*/
 #if defined(CONFIG_CMD_KGDB)
 #define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
 #else
@@ -238,7 +237,6 @@ ip=${ipaddr}:${serverip}${bootargs_end}; bootm 0x400000;\0"
 
 #define CONFIG_SYS_LOAD_ADDR		0x00400000	/* default load address */
 
-#define CONFIG_SYS_HZ			1000		/* decr freq: 1ms ticks */
 /*ronen - this the Sys clock (cpu bus,internal dram and SDRAM) */
 #define CONFIG_SYS_BUS_CLK		133000000	/* 133 MHz (CPU = 5*Bus = 666MHz)		*/
 
diff --git a/include/configs/DP405.h b/include/configs/DP405.h
index 8155caa5ed..68e4a7f405 100644
--- a/include/configs/DP405.h
+++ b/include/configs/DP405.h
@@ -18,7 +18,6 @@
  */
 
 #define CONFIG_405EP		1	/* This is a PPC405 CPU		*/
-#define CONFIG_4xx		1	/* ...member of PPC4xx family	*/
 #define CONFIG_DP405		1	/* ...on a DP405 board		*/
 
 #define	CONFIG_SYS_TEXT_BASE	0xFFFD0000
@@ -61,7 +60,6 @@
  * Miscellaneous configurable options
  */
 #define CONFIG_SYS_LONGHELP			/* undef to save memory		*/
-#define CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt	*/
 
 #undef	CONFIG_SYS_HUSH_PARSER			/* use "hush" command parser	*/
 
@@ -98,8 +96,6 @@
 #define CONFIG_SYS_LOAD_ADDR	0x100000	/* default load address */
 #define CONFIG_SYS_EXTBDINFO	1		/* To use extended board_into (bd_t) */
 
-#define CONFIG_SYS_HZ		1000		/* decrementer freq: 1 ms ticks */
-
 #define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */
 
 #define CONFIG_VERSION_VARIABLE 1	/* include version env variable */
diff --git a/include/configs/DU405.h b/include/configs/DU405.h
index b7764d4bc2..9be2310dbd 100644
--- a/include/configs/DU405.h
+++ b/include/configs/DU405.h
@@ -17,7 +17,6 @@
  * (easy to change)
  */
 #define CONFIG_405GP		1	/* This is a PPC405 CPU		*/
-#define CONFIG_4xx		1	/* ...member of PPC4xx family	*/
 #define CONFIG_DU405		1	/* ...on a DU405 board		*/
 
 #define	CONFIG_SYS_TEXT_BASE	0xFFFD0000
@@ -84,7 +83,6 @@
  * Miscellaneous configurable options
  */
 #define CONFIG_SYS_LONGHELP			/* undef to save memory		*/
-#define CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt	*/
 #if defined(CONFIG_CMD_KGDB)
 #define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
 #else
@@ -115,8 +113,6 @@
 #define CONFIG_SYS_LOAD_ADDR	0x100000	/* default load address */
 #define CONFIG_SYS_EXTBDINFO	1		/* To use extended board_into (bd_t) */
 
-#define CONFIG_SYS_HZ		1000		/* decrementer freq: 1 ms ticks */
-
 #define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */
 
 #define CONFIG_SYS_RX_ETH_BUFFER	16	/* use 16 rx buffer on 405 emac */
diff --git a/include/configs/DU440.h b/include/configs/DU440.h
index 5ffa6e4b44..be5494b2ec 100644
--- a/include/configs/DU440.h
+++ b/include/configs/DU440.h
@@ -21,7 +21,6 @@
  */
 #define CONFIG_DU440		1		/* Board is esd DU440	*/
 #define CONFIG_440EPX		1		/* Specific PPC440EPx	*/
-#define CONFIG_4xx		1		/* ... PPC4xx family	*/
 #define CONFIG_SYS_CLK_FREQ	33333400	/* external freq to pll	*/
 
 #ifndef CONFIG_SYS_TEXT_BASE
@@ -310,7 +309,6 @@ int du440_phy_addr(int devnum);
  * Miscellaneous configurable options
  */
 #define CONFIG_SYS_LONGHELP			/* undef to save memory		*/
-#define CONFIG_SYS_PROMPT	        "=> "	/* Monitor Command Prompt	*/
 #if defined(CONFIG_CMD_KGDB)
 #define CONFIG_SYS_CBSIZE	        1024	/* Console I/O Buffer Size	*/
 #else
@@ -327,8 +325,6 @@ int du440_phy_addr(int devnum);
 #define CONFIG_SYS_LOAD_ADDR		0x100000  /* default load address	*/
 #define CONFIG_SYS_EXTBDINFO		1	/* To use extended board_into (bd_t) */
 
-#define CONFIG_SYS_HZ		        1000	/* decrementer freq: 1 ms ticks	*/
-
 #define CONFIG_CMDLINE_EDITING	1	/* add command line history	*/
 #define CONFIG_LOOPW            1       /* enable loopw command         */
 #define CONFIG_MX_CYCLIC        1       /* enable mdc/mwc commands      */
@@ -409,7 +405,6 @@ int du440_phy_addr(int devnum);
 
 #if defined(CONFIG_CMD_KGDB)
 #define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
-#define CONFIG_KGDB_SER_INDEX	2	/* which serial port to use */
 #endif
 
 #define CONFIG_SOURCE		1
diff --git a/include/configs/ELPPC.h b/include/configs/ELPPC.h
index fb2f3befd6..0ffbd41b49 100644
--- a/include/configs/ELPPC.h
+++ b/include/configs/ELPPC.h
@@ -75,7 +75,6 @@
  * Miscellaneous configurable options
  */
 #define CONFIG_SYS_LONGHELP                    /* undef to save memory */
-#define CONFIG_SYS_PROMPT              "=> "   /* Monitor Command Prompt */
 
 /*
  * choose between COM1 and COM2 as serial console
@@ -96,8 +95,6 @@
 
 #define CONFIG_SYS_LOAD_ADDR           0x1000000   /* default load address    */
 
-#define CONFIG_SYS_HZ                  1000        /* dec. freq: 1 ms ticks */
-
 #define CONFIG_SYS_BAUDRATE_TABLE      { 9600, 19200, 38400, 57600, 115200, 230400 }
 
 /*
diff --git a/include/configs/ELPT860.h b/include/configs/ELPT860.h
index 69f44b1e62..a9d62c880f 100644
--- a/include/configs/ELPT860.h
+++ b/include/configs/ELPT860.h
@@ -120,8 +120,6 @@
 
 #define CONFIG_SYS_LOAD_ADDR		0x00100000	/* default load address */
 
-#define CONFIG_SYS_HZ		1000		/* decrementer freq: 1 ms ticks */
-
 /*
  * Environment Variables and Storages
  */
diff --git a/include/configs/EP88x.h b/include/configs/EP88x.h
deleted file mode 100644
index 6678fc21c7..0000000000
--- a/include/configs/EP88x.h
+++ /dev/null
@@ -1,190 +0,0 @@
-/*
- * Copyright (C) 2005 Arabella Software Ltd.
- * Yuli Barcohen <yuli@arabellasw.com>
- *
- * Support for Embedded Planet EP88x boards.
- * Tested on EP88xC with MPC885 CPU, 64MB SDRAM and 16MB flash.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#define CONFIG_MPC885
-
-#define CONFIG_EP88X				/* Embedded Planet EP88x board	*/
-
-#define	CONFIG_SYS_TEXT_BASE	0xFC000000
-
-#define CONFIG_BOARD_EARLY_INIT_F		/* Call board_early_init_f	*/
-
-/* Allow serial number (serial#) and MAC address (ethaddr) to be overwritten */
-#define CONFIG_ENV_OVERWRITE
-
-#define	CONFIG_8xx_CONS_SMC1	1		/* Console is on SMC1		*/
-#define CONFIG_BAUDRATE		38400
-
-#define	CONFIG_ETHER_ON_FEC1			/* Enable Ethernet on FEC1	*/
-#define	CONFIG_ETHER_ON_FEC2			/* Enable Ethernet on FEC2	*/
-#if defined(CONFIG_ETHER_ON_FEC1) || defined(CONFIG_ETHER_ON_FEC2)
-#define CONFIG_SYS_DISCOVER_PHY
-#define CONFIG_MII_INIT		1
-#define FEC_ENET
-#endif /* CONFIG_FEC_ENET */
-
-#define CONFIG_8xx_OSCLK		10000000 /* 10 MHz oscillator on EXTCLK */
-#define CONFIG_8xx_CPUCLK_DEFAULT	100000000
-#define CONFIG_SYS_8xx_CPUCLK_MIN		40000000
-#define CONFIG_SYS_8xx_CPUCLK_MAX		133000000
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_IMMAP
-#define CONFIG_CMD_MII
-#define CONFIG_CMD_PING
-
-
-#define CONFIG_BOOTDELAY	5		/* Autoboot after 5 seconds	*/
-#define CONFIG_BOOTCOMMAND	"bootm fe060000"	/* Autoboot command	*/
-#define CONFIG_BOOTARGS		"root=/dev/mtdblock1 rw mtdparts=phys:2M(ROM)ro,-(root)"
-
-#define CONFIG_BZIP2		/* Include support for bzip2 compressed images  */
-#undef	CONFIG_WATCHDOG		/* Disable platform specific watchdog		*/
-
-/*-----------------------------------------------------------------------
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_PROMPT		"=> "		/* Monitor Command Prompt	*/
-#define CONFIG_SYS_HUSH_PARSER
-#define CONFIG_SYS_LONGHELP				/* #undef to save memory	*/
-#define CONFIG_SYS_CBSIZE		256		/* Console I/O Buffer Size	*/
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)  /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS		16		/* Max number of command args	*/
-#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
-
-#define CONFIG_SYS_LOAD_ADDR		0x400000	/* Default load address		*/
-
-#define CONFIG_SYS_HZ			1000		/* Decrementer freq: 1 ms ticks	*/
-
-/*-----------------------------------------------------------------------
- * RAM configuration (note that CONFIG_SYS_SDRAM_BASE must be zero)
- */
-#define CONFIG_SYS_SDRAM_BASE		0x00000000
-#define CONFIG_SYS_SDRAM_MAX_SIZE	0x08000000	/* Up to 128 Mbyte		*/
-
-#define CONFIG_SYS_MAMR		0x00805000
-
-/*
- * 4096	Up to 4096 SDRAM rows
- * 1000	factor s -> ms
- * 32	PTP (pre-divider from MPTPR)
- * 4	Number of refresh cycles per period
- * 64	Refresh cycle in ms per number of rows
- */
-#define CONFIG_SYS_PTA_PER_CLK		((4096 * 32 * 1000) / (4 * 64))
-
-#define CONFIG_SYS_MEMTEST_START	0x00100000	/* memtest works on		*/
-#define CONFIG_SYS_MEMTEST_END		0x00500000	/* 1 ... 5 MB in SDRAM		*/
-
-#define CONFIG_SYS_RESET_ADDRESS	0x09900000
-
-/*-----------------------------------------------------------------------
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
-
-#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 KB for Monitor   */
-#ifdef CONFIG_BZIP2
-#define CONFIG_SYS_MALLOC_LEN		(4096 << 10)	/* Reserve ~4 MB for malloc()   */
-#else
-#define CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 KB for malloc()  */
-#endif /* CONFIG_BZIP2 */
-
-/*-----------------------------------------------------------------------
- * Flash organisation
- */
-#define CONFIG_SYS_FLASH_BASE		0xFC000000
-#define CONFIG_SYS_FLASH_CFI				/* The flash is CFI compatible  */
-#define CONFIG_FLASH_CFI_DRIVER			/* Use common CFI driver        */
-#define CONFIG_SYS_MAX_FLASH_BANKS	1		/* Max number of flash banks	*/
-#define CONFIG_SYS_MAX_FLASH_SECT	512		/* Max num of sects on one chip */
-
-/* Environment is in flash */
-#define CONFIG_ENV_IS_IN_FLASH
-#define CONFIG_ENV_SECT_SIZE	0x20000		/* We use one complete sector	*/
-#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
-
-#define CONFIG_SYS_OR0_PRELIM		0xFC000160
-#define CONFIG_SYS_BR0_PRELIM		(CONFIG_SYS_FLASH_BASE | BR_PS_32 | BR_MS_GPCM | BR_V)
-
-#define	CONFIG_SYS_DIRECT_FLASH_TFTP
-
-/*-----------------------------------------------------------------------
- * BCSR
- */
-#define CONFIG_SYS_OR3_PRELIM		0xFF0005B0
-#define CONFIG_SYS_BR3_PRELIM		(0xFA000000 |BR_PS_16 | BR_MS_GPCM | BR_V)
-
-#define CONFIG_SYS_BCSR		0xFA400000
-
-/*-----------------------------------------------------------------------
- * Internal Memory Map Register
- */
-#define CONFIG_SYS_IMMR		0xF0000000
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area (in DPRAM)
- */
-#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
-#define CONFIG_SYS_INIT_RAM_SIZE	0x2F00		/* Size of used area in DPRAM	*/
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
-
-/*-----------------------------------------------------------------------
- * Configuration registers
- */
-#ifdef CONFIG_WATCHDOG
-#define CONFIG_SYS_SYPCR		(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME  | \
-				 SYPCR_SWF  | SYPCR_SWE | SYPCR_SWRI | \
-				 SYPCR_SWP)
-#else
-#define CONFIG_SYS_SYPCR		(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME  | \
-				 SYPCR_SWF  | SYPCR_SWP)
-#endif /* CONFIG_WATCHDOG */
-
-#define CONFIG_SYS_SIUMCR		(SIUMCR_MLRC01 | SIUMCR_DBGC11)
-
-/* TBSCR - Time Base Status and Control Register */
-#define CONFIG_SYS_TBSCR		(TBSCR_TBF | TBSCR_TBE)
-
-/* PISCR - Periodic Interrupt Status and Control */
-#define CONFIG_SYS_PISCR		PISCR_PS
-
-/* SCCR - System Clock and reset Control Register */
-#define SCCR_MASK		SCCR_EBDF11
-#define CONFIG_SYS_SCCR		SCCR_RTSEL
-
-#define CONFIG_SYS_DER			0
-
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CONFIG_SYS_CACHELINE_SIZE	16	/* For all MPC8xx chips			*/
-
-#endif /* __CONFIG_H */
diff --git a/include/configs/ESTEEM192E.h b/include/configs/ESTEEM192E.h
index 7d2fb47d80..347f8b64a2 100644
--- a/include/configs/ESTEEM192E.h
+++ b/include/configs/ESTEEM192E.h
@@ -84,8 +84,6 @@
 
 #define	CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address	*/
 
-#define	CONFIG_SYS_HZ			1000		/* decrementer freq: 1 ms ticks	*/
-
 /*
  * Low Level Configuration Settings
  * (address mappings, register initial values, etc.)
diff --git a/include/configs/EVB64260.h b/include/configs/EVB64260.h
index fc8b921efc..8ec75d9618 100644
--- a/include/configs/EVB64260.h
+++ b/include/configs/EVB64260.h
@@ -110,7 +110,6 @@
  * Miscellaneous configurable options
  */
 #define	CONFIG_SYS_LONGHELP			/* undef to save memory		*/
-#define	CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt	*/
 #if defined(CONFIG_CMD_KGDB)
 #define	CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
 #else
@@ -124,8 +123,6 @@
 #define CONFIG_SYS_MEMTEST_END		0x00C00000	/* 4 ... 12 MB in DRAM	*/
 
 #define	CONFIG_SYS_LOAD_ADDR		0x00300000	/* default load address	*/
-
-#define	CONFIG_SYS_HZ			1000		/* decr freq: 1ms ticks	*/
 #define CONFIG_SYS_BUS_CLK		100000000	/* 100 MHz		*/
 
 #define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
diff --git a/include/configs/EXBITGEN.h b/include/configs/EXBITGEN.h
deleted file mode 100644
index c9cc0d075e..0000000000
--- a/include/configs/EXBITGEN.h
+++ /dev/null
@@ -1,194 +0,0 @@
-/*
- * (C) Copyright 2000-2004
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-/*
- * board/config.h - configuration options, board specific
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_405GP		1	/* This is a PPC405GP CPU	*/
-#define CONFIG_4xx		1	/* ...member of PPC4xx family   */
-#define CONFIG_EXBITGEN		1	/* on a Exbit Generic board     */
-
-#define CONFIG_BOARD_EARLY_INIT_F 1	/* Call board_early_init_f	*/
-
-#define CONFIG_SYS_CLK_FREQ     25000000 /* external frequency to pll   */
-
-/* I2C configuration */
-#define CONFIG_HARD_I2C		1	/* I2C with hardware support	*/
-#define CONFIG_SYS_I2C_SPEED		40000	/* I2C speed			*/
-#define CONFIG_SYS_I2C_SLAVE		0x7F	/* I2C slave address		*/
-
-/* environment is in EEPROM */
-#define CONFIG_ENV_IS_IN_EEPROM    1
-#undef CONFIG_ENV_IS_IN_FLASH
-#undef CONFIG_ENV_IS_IN_NVRAM
-
-#ifdef CONFIG_ENV_IS_IN_EEPROM
-#define CONFIG_SYS_I2C_EEPROM_ADDR		0x56    /* 1010110 */
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		1	/* 8-bit internal addressing */
-#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW	1	/* ... and 1 bit in I2C address */
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	3	/* 4 bytes per page */
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	40	/* write takes up to 40 msec */
-#define CONFIG_ENV_OFFSET		4	/* Offset of Environment Sector	*/
-#define	CONFIG_ENV_SIZE		350	/* that is 350 bytes only!	*/
-#endif
-
-#define CONFIG_BOOTDELAY	10	/* autoboot after 10 seconds	*/
-/* Explanation:
-   autbooting is altogether disabled and cannot be
-   enabled if CONFIG_BOOTDELAY is negative.
-   If you want shorter bootdelay, then
-   - "setenv bootdelay <delay>" to the proper value
-*/
-
-#define CONFIG_BOOTCOMMAND	"bootm 20400000 20800000"
-
-#define CONFIG_BOOTARGS		"root=/dev/ram "  \
-				"ramdisk_size=32768 " \
-				"console=ttyS0,115200 " \
-				"ram=128M debug"
-
-#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
-#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
-
-#define CONFIG_MII		1	/* MII PHY management		*/
-#define CONFIG_PHY_ADDR		0	/* PHY address			*/
-
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_PPC4xx_EMAC
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-
-#undef CONFIG_WATCHDOG			/* watchdog disabled		*/
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP			/* undef to save memory		*/
-#define CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt	*/
-#if defined(CONFIG_CMD_KGDB)
-#define	CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
-#else
-#define	CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
-#endif
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
-#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
-
-#define CONFIG_SYS_MEMTEST_START	0x0400000	/* memtest works on	*/
-#define CONFIG_SYS_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
-
-/* UART configuration */
-#define CONFIG_SYS_BASE_BAUD		691200
-
-/* Default baud rate */
-#define CONFIG_BAUDRATE		115200
-
-/* The following table includes the supported baudrates */
-#define CONFIG_SYS_BAUDRATE_TABLE      \
-	{ 300, 600, 1200, 2400, 4800, 9600, 19200, 38400,     \
-	 57600, 115200, 230400, 460800, 921600 }
-
-#define CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address */
-#define CONFIG_SYS_EXTBDINFO		1	/* To use extended board_into (bd_t) */
-
-#define	CONFIG_SYS_HZ			1000	/* decrementer freq: 1 ms ticks	*/
-
-/*-----------------------------------------------------------------------
- * PCI stuff
- *-----------------------------------------------------------------------
- */
-#undef CONFIG_PCI			/* no pci support	        */
-
-/*-----------------------------------------------------------------------
- * External peripheral base address
- *-----------------------------------------------------------------------
- */
-#undef  CONFIG_IDE_PCMCIA               /* no pcmcia interface required */
-#undef  CONFIG_IDE_LED                  /* no led for ide supported     */
-#undef  CONFIG_IDE_RESET                /* no reset for ide supported   */
-
-#define	CONFIG_SYS_KEY_REG_BASE_ADDR	0xF0100000
-#define	CONFIG_SYS_IR_REG_BASE_ADDR	0xF0200000
-#define	CONFIG_SYS_FPGA_REG_BASE_ADDR	0xF0300000
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
- */
-#define CONFIG_SYS_SDRAM_BASE		0x00000000
-#define CONFIG_SYS_FLASH0_BASE		0xFFF80000
-#define CONFIG_SYS_FLASH0_SIZE		0x00080000
-#define CONFIG_SYS_FLASH1_BASE		0x20000000
-#define CONFIG_SYS_FLASH1_SIZE		0x02000000
-#define CONFIG_SYS_FLASH_BASE		CONFIG_SYS_FLASH0_BASE
-#define CONFIG_SYS_FLASH_SIZE		CONFIG_SYS_FLASH0_SIZE
-#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_MONITOR_LEN		(192 * 1024)	/* Reserve 196 kB for Monitor	*/
-#define CONFIG_SYS_MALLOC_LEN		(128 * 1024)	/* Reserve 128 kB for malloc()	*/
-
-#if CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH0_BASE
-#define CONFIG_SYS_RAMSTART
-#endif
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-#define CONFIG_SYS_MAX_FLASH_BANKS	5	/* max number of memory banks		*/
-#define CONFIG_SYS_MAX_FLASH_SECT	128	/* max number of sectors on one chip	*/
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
-#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
-
-#ifdef CONFIG_ENV_IS_IN_FLASH
-#define CONFIG_ENV_OFFSET		0x00060000 /* Offset of Environment Sector      */
-#define	CONFIG_ENV_SIZE		0x00010000 /* Total Size of Environment Sector	*/
-#define CONFIG_ENV_SECT_SIZE	0x00010000 /* see README - env sector total size */
-#endif
-
-/* On Chip Memory location/size */
-#define CONFIG_SYS_OCM_DATA_ADDR	0xF8000000
-#define CONFIG_SYS_OCM_DATA_SIZE	0x1000
-
-/* Global info and initial stack */
-#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_OCM_DATA_ADDR /* inside of on-chip SRAM	*/
-#define CONFIG_SYS_INIT_RAM_SIZE	CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM	*/
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
-
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
-#define CONFIG_KGDB_SER_INDEX	2	/* which serial port to use */
-#endif
-#endif	/* __CONFIG_H */
diff --git a/include/configs/FADS823.h b/include/configs/FADS823.h
index 35c0c7eed1..50de4ea084 100644
--- a/include/configs/FADS823.h
+++ b/include/configs/FADS823.h
@@ -152,8 +152,6 @@
 
 #define CONFIG_SYS_LOAD_ADDR		0x00100000	/* default load address */
 
-#define	CONFIG_SYS_HZ		1000		/* decrementer freq: 1 ms ticks	*/
-
 /*
  * Low Level Configuration Settings
  * (address mappings, register initial values, etc.)
diff --git a/include/configs/FADS850SAR.h b/include/configs/FADS850SAR.h
index 559a83f527..d48460b9f5 100644
--- a/include/configs/FADS850SAR.h
+++ b/include/configs/FADS850SAR.h
@@ -98,8 +98,6 @@
 
 #define CONFIG_SYS_LOAD_ADDR		0x00100000	/* default load address */
 
-#define	CONFIG_SYS_HZ		1000		/* decrementer freq: 1 ms ticks	*/
-
 /*
  * Low Level Configuration Settings
  * (address mappings, register initial values, etc.)
diff --git a/include/configs/FLAGADM.h b/include/configs/FLAGADM.h
index 1c385f1097..d93223fa40 100644
--- a/include/configs/FLAGADM.h
+++ b/include/configs/FLAGADM.h
@@ -94,8 +94,6 @@
 
 #define CONFIG_SYS_LOAD_ADDR		0x40040000	/* default load address */
 
-#define CONFIG_SYS_HZ		1000		/* decrementer freq: 1 ms ticks */
-
 /*
  * Low Level Configuration Settings
  * (address mappings, register initial values, etc.)
diff --git a/include/configs/FPS850L.h b/include/configs/FPS850L.h
index 002a80413e..4ea24a631c 100644
--- a/include/configs/FPS850L.h
+++ b/include/configs/FPS850L.h
@@ -111,7 +111,6 @@
  * Miscellaneous configurable options
  */
 #define	CONFIG_SYS_LONGHELP			/* undef to save memory		*/
-#define	CONFIG_SYS_PROMPT		"=> "	/* Monitor Command Prompt	*/
 
 #define CONFIG_CMDLINE_EDITING	1	/* add command line history	*/
 #define CONFIG_SYS_HUSH_PARSER		1	/* Use the HUSH parser		*/
@@ -130,8 +129,6 @@
 
 #define	CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address	*/
 
-#define	CONFIG_SYS_HZ		1000		/* decrementer freq: 1 ms ticks	*/
-
 /*
  * Low Level Configuration Settings
  * (address mappings, register initial values, etc.)
diff --git a/include/configs/FPS860L.h b/include/configs/FPS860L.h
index 5eaf2f862f..c3688616af 100644
--- a/include/configs/FPS860L.h
+++ b/include/configs/FPS860L.h
@@ -111,7 +111,6 @@
  * Miscellaneous configurable options
  */
 #define	CONFIG_SYS_LONGHELP			/* undef to save memory		*/
-#define	CONFIG_SYS_PROMPT		"=> "	/* Monitor Command Prompt	*/
 
 #define CONFIG_CMDLINE_EDITING	1	/* add command line history	*/
 #define CONFIG_SYS_HUSH_PARSER		1	/* Use the HUSH parser		*/
@@ -130,8 +129,6 @@
 
 #define	CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address	*/
 
-#define	CONFIG_SYS_HZ		1000		/* decrementer freq: 1 ms ticks	*/
-
 /*
  * Low Level Configuration Settings
  * (address mappings, register initial values, etc.)
diff --git a/include/configs/G2000.h b/include/configs/G2000.h
index 818e82d4f4..0c66092e0b 100644
--- a/include/configs/G2000.h
+++ b/include/configs/G2000.h
@@ -18,7 +18,6 @@
  */
 
 #define CONFIG_405EP		1	/* This is a PPC405 CPU		*/
-#define CONFIG_4xx		1	/* ...member of PPC4xx family	*/
 #define CONFIG_G2000		1	/* ...on a PLU405 board		*/
 
 #define	CONFIG_SYS_TEXT_BASE	0xFFFC0000
@@ -111,7 +110,6 @@
  * Miscellaneous configurable options
  */
 #define CONFIG_SYS_LONGHELP			/* undef to save memory		*/
-#define CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt	*/
 
 #undef	CONFIG_SYS_HUSH_PARSER			/* use "hush" command parser	*/
 
@@ -150,8 +148,6 @@
 #define CONFIG_SYS_LOAD_ADDR	0x100000	/* default load address */
 #define CONFIG_SYS_EXTBDINFO	1		/* To use extended board_into (bd_t) */
 
-#define CONFIG_SYS_HZ		1000		/* decrementer freq: 1 ms ticks */
-
 #define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */
 #define CONFIG_BOOTDELAY	3	/* autoboot after 3 seconds	*/
 
diff --git a/include/configs/GEN860T.h b/include/configs/GEN860T.h
index 06c0e50c96..2822a08c0a 100644
--- a/include/configs/GEN860T.h
+++ b/include/configs/GEN860T.h
@@ -310,11 +310,6 @@
 #define	CONFIG_SYS_LOAD_ADDR		0x01000000
 
 /*
- * Set decrementer frequency (1 ms ticks)
- */
-#define	CONFIG_SYS_HZ				1000
-
-/*
  * Device memory map (after SDRAM remap to 0x0):
  *
  * CS		Device				Base Addr	Size
diff --git a/include/configs/GENIETV.h b/include/configs/GENIETV.h
index c5ca279d7d..6a34b12bc6 100644
--- a/include/configs/GENIETV.h
+++ b/include/configs/GENIETV.h
@@ -142,8 +142,6 @@
 
 #define CONFIG_SYS_LOAD_ADDR		0x00100000	/* default load address */
 
-#define	CONFIG_SYS_HZ		1000		/* decrementer freq: 1 ms ticks	*/
-
 #define CONFIG_SYS_BAUDRATE_TABLE	{ 4800, 9600, 19200, 38400, 57600, 115200 }
 
 /*
diff --git a/include/configs/HH405.h b/include/configs/HH405.h
index a55c874cab..033dcbfe26 100644
--- a/include/configs/HH405.h
+++ b/include/configs/HH405.h
@@ -24,7 +24,6 @@
  */
 
 #define CONFIG_405EP		1	/* This is a PPC405 CPU		*/
-#define CONFIG_4xx		1	/* ...member of PPC4xx family   */
 #define CONFIG_HH405		1	/* ...on a HH405 board	        */
 
 #define	CONFIG_SYS_TEXT_BASE	0xFFF80000
@@ -136,7 +135,6 @@
  * Miscellaneous configurable options
  */
 #define CONFIG_SYS_LONGHELP			/* undef to save memory		*/
-#define CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt	*/
 
 #undef	CONFIG_SYS_HUSH_PARSER			/* use "hush" command parser	*/
 
@@ -175,8 +173,6 @@
 #define CONFIG_SYS_LOAD_ADDR	0x100000	/* default load address */
 #define CONFIG_SYS_EXTBDINFO	1		/* To use extended board_into (bd_t) */
 
-#define	CONFIG_SYS_HZ		1000		/* decrementer freq: 1 ms ticks	*/
-
 #define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */
 
 #define CONFIG_VERSION_VARIABLE	1       /* include version env variable */
diff --git a/include/configs/HIDDEN_DRAGON.h b/include/configs/HIDDEN_DRAGON.h
index 79ab64c182..e0a233b28a 100644
--- a/include/configs/HIDDEN_DRAGON.h
+++ b/include/configs/HIDDEN_DRAGON.h
@@ -22,7 +22,6 @@
  * (easy to change)
  */
 
-#define CONFIG_MPC824X		1
 #define CONFIG_MPC8245		1
 #define CONFIG_HIDDEN_DRAGON	1
 
@@ -64,13 +63,11 @@
  * Miscellaneous configurable options
  */
 #define CONFIG_SYS_LONGHELP		1		/* undef to save memory		*/
-#define CONFIG_SYS_PROMPT		"=> "		/* Monitor Command Prompt	*/
 #define CONFIG_SYS_CBSIZE		256		/* Console I/O Buffer Size	*/
 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)	/* Print Buffer Size	*/
 #define CONFIG_SYS_MAXARGS		16		/* max number of command args	*/
 #define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
 #define CONFIG_SYS_LOAD_ADDR		0x00100000	/* default load address		*/
-#define CONFIG_SYS_HZ			1000		/* decrementer freq: 1 ms ticks */
 
 /*-----------------------------------------------------------------------
  * PCI stuff
diff --git a/include/configs/HUB405.h b/include/configs/HUB405.h
index 1906457f9f..1783b9ff15 100644
--- a/include/configs/HUB405.h
+++ b/include/configs/HUB405.h
@@ -18,7 +18,6 @@
  */
 
 #define CONFIG_405EP		1	/* This is a PPC405 CPU		*/
-#define CONFIG_4xx		1	/* ...member of PPC4xx family	*/
 #define CONFIG_HUB405		1	/* ...on a HUB405 board		*/
 
 #define	CONFIG_SYS_TEXT_BASE	0xFFFC0000
@@ -80,7 +79,6 @@
  * Miscellaneous configurable options
  */
 #define CONFIG_SYS_LONGHELP			/* undef to save memory		*/
-#define CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt	*/
 
 #undef	CONFIG_SYS_HUSH_PARSER			/* use "hush" command parser	*/
 
@@ -117,8 +115,6 @@
 #define CONFIG_SYS_LOAD_ADDR	0x100000	/* default load address */
 #define CONFIG_SYS_EXTBDINFO	1		/* To use extended board_into (bd_t) */
 
-#define CONFIG_SYS_HZ		1000		/* decrementer freq: 1 ms ticks */
-
 #define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */
 
 #define CONFIG_VERSION_VARIABLE 1	/* include version env variable */
diff --git a/include/configs/HWW1U1A.h b/include/configs/HWW1U1A.h
index 5aaa9767e9..6a3a11cb7f 100644
--- a/include/configs/HWW1U1A.h
+++ b/include/configs/HWW1U1A.h
@@ -13,7 +13,6 @@
 /* High-level system configuration options */
 #define CONFIG_BOOKE		/* Power/PowerPC Book-E			*/
 #define CONFIG_E500		/* e500 (Power ISA v2.03 with SPE)	*/
-#define CONFIG_MPC85xx		/* MPC8540/60/55/41/48 family		*/
 #define CONFIG_FSL_ELBC		/* FreeScale Enhanced LocalBus Cntlr	*/
 #define CONFIG_FSL_LAW		/* FreeScale Local Access Window	*/
 #define CONFIG_P2020		/* FreeScale P2020			*/
@@ -53,8 +52,6 @@
 
 /* Enable IRQs and watchdog with a 1000Hz system decrementer */
 #define CONFIG_CMD_IRQ
-#define CONFIG_SYS_HZ 1000
-
 
 /* -------------------------------------------------------------------- */
 
@@ -257,7 +254,7 @@
 /* -------------------------------------------------------------------- */
 
 /* FreeScale DDR2/3 SDRAM Controller */
-#define CONFIG_FSL_DDR2		/* Our SDRAM slot is DDR2		*/
+#define CONFIG_SYS_FSL_DDR2		/* Our SDRAM slot is DDR2		*/
 #define CONFIG_DDR_ECC		/* Enable ECC by default		*/
 #define CONFIG_DDR_SPD		/* Detect DDR config from SPD EEPROM	*/
 #define CONFIG_SPD_EEPROM	/* ...why 2 config variables for this?	*/
diff --git a/include/configs/ICU862.h b/include/configs/ICU862.h
index 40d0d7cab9..16af4bbcad 100644
--- a/include/configs/ICU862.h
+++ b/include/configs/ICU862.h
@@ -138,7 +138,6 @@
  * Miscellaneous configurable options
  */
 #define	CONFIG_SYS_LONGHELP			/* undef to save memory		*/
-#define	CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt	*/
 #if defined(CONFIG_CMD_KGDB)
 #define	CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
 #else
@@ -153,8 +152,6 @@
 
 #define CONFIG_SYS_LOAD_ADDR		0x00100000
 
-#define	CONFIG_SYS_HZ		1000		/* decrementer freq: 1 ms ticks	*/
-
 /*
  * Low Level Configuration Settings
  * (address mappings, register initial values, etc.)
diff --git a/include/configs/IDS8247.h b/include/configs/IDS8247.h
index 590abc30df..8ccb0ff9d8 100644
--- a/include/configs/IDS8247.h
+++ b/include/configs/IDS8247.h
@@ -17,7 +17,6 @@
  * (easy to change)
  */
 
-#define CONFIG_MPC8260		1	/* This is a MPC8260 CPU		*/
 #define CONFIG_MPC8272_FAMILY	1
 #define CONFIG_IDS8247		1
 #define CPU_ID_STR		"MPC8247"
@@ -181,7 +180,6 @@
  * Miscellaneous configurable options
  */
 #define	CONFIG_SYS_LONGHELP			/* undef to save memory		*/
-#define	CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt	*/
 #if defined(CONFIG_CMD_KGDB)
 #define	CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
 #else
@@ -196,8 +194,6 @@
 
 #define	CONFIG_SYS_LOAD_ADDR	0x100000	/* default load address	*/
 
-#define	CONFIG_SYS_HZ		1000		/* decrementer freq: 1 ms ticks	*/
-
 #define	CONFIG_SYS_RESET_ADDRESS 0xFDFFFFFC	/* "bad" address		*/
 
 /*
diff --git a/include/configs/IP860.h b/include/configs/IP860.h
index c852ca998b..97eda58442 100644
--- a/include/configs/IP860.h
+++ b/include/configs/IP860.h
@@ -99,7 +99,6 @@
  * Miscellaneous configurable options
  */
 #define	CONFIG_SYS_LONGHELP			/* undef to save memory		*/
-#define	CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt	*/
 #if defined(CONFIG_CMD_KGDB)
 #define	CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
 #else
@@ -116,8 +115,6 @@
 
 #define	CONFIG_SYS_PIO_MODE		0	/* IDE interface in PIO Mode 0	*/
 
-#define	CONFIG_SYS_HZ			1000	/* decrementer freq: 1 ms ticks	*/
-
 /*
  * Low Level Configuration Settings
  * (address mappings, register initial values, etc.)
diff --git a/include/configs/IPHASE4539.h b/include/configs/IPHASE4539.h
index 1f5dfa84f5..e402075d37 100644
--- a/include/configs/IPHASE4539.h
+++ b/include/configs/IPHASE4539.h
@@ -19,7 +19,6 @@
  * (easy to change)
  */
 
-#define CONFIG_MPC8260		1	/* This is an MPC8260 CPU   */
 #define CONFIG_IPHASE4539	1	/* ...on a Interphase 4539 PMC */
 
 #define	CONFIG_SYS_TEXT_BASE	0xffb00000
@@ -136,7 +135,6 @@
  * Miscellaneous configurable options
  */
 #define CONFIG_SYS_LONGHELP			/* undef to save memory		*/
-#define CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt	*/
 #if defined(CONFIG_CMD_KGDB)
 #define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
 #else
@@ -154,8 +152,6 @@
 
 #define CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address	*/
 
-#define CONFIG_SYS_HZ			1000	/* decrementer freq: 1 ms ticks	*/
-
 #define CONFIG_SYS_RESET_ADDRESS	0x04400000
 
 #define CONFIG_MISC_INIT_R	1	/* We need misc_init_r()	*/
diff --git a/include/configs/ISPAN.h b/include/configs/ISPAN.h
index ca126ef346..a2fdfd3274 100644
--- a/include/configs/ISPAN.h
+++ b/include/configs/ISPAN.h
@@ -13,7 +13,6 @@
 #ifndef __CONFIG_H
 #define __CONFIG_H
 
-#define CONFIG_MPC8260			/* This is an MPC8260 CPU               */
 #define CONFIG_ISPAN			/* ...on one of Interphase iSPAN boards */
 #define CONFIG_CPM2		1	/* Has a CPM2 */
 
@@ -128,7 +127,6 @@
 /*-----------------------------------------------------------------------
  * Miscellaneous configurable options
  */
-#define CONFIG_SYS_PROMPT		"=> "		/* Monitor Command Prompt	*/
 #define CONFIG_SYS_HUSH_PARSER
 #define CONFIG_SYS_LONGHELP				/* #undef to save memory	*/
 #define CONFIG_SYS_CBSIZE		256		/* Console I/O Buffer Size	*/
@@ -141,8 +139,6 @@
 
 #define CONFIG_SYS_LOAD_ADDR		0x100000	/* Default load address		*/
 
-#define CONFIG_SYS_HZ			1000		/* Decrementer freq: 1 ms ticks	*/
-
 #define CONFIG_SYS_RESET_ADDRESS	0x09900000
 
 #define CONFIG_MISC_INIT_R			/* We need misc_init_r()	*/
diff --git a/include/configs/IVML24.h b/include/configs/IVML24.h
index 53b51f3d5d..8aa4ac2156 100644
--- a/include/configs/IVML24.h
+++ b/include/configs/IVML24.h
@@ -85,7 +85,6 @@
  * Miscellaneous configurable options
  */
 #define	CONFIG_SYS_LONGHELP			/* undef to save memory		*/
-#define	CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt	*/
 #if defined(CONFIG_CMD_KGDB)
 #define	CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
 #else
@@ -111,8 +110,6 @@
 #define CONFIG_SYS_PC_ETH_RESET	((ushort)0x0010)	/* PC 11	*/
 #define CONFIG_SYS_PC_IDE_RESET	((ushort)0x0020)	/* PC 10	*/
 
-#define	CONFIG_SYS_HZ		1000		/* decrementer freq: 1 ms ticks	*/
-
 /*
  * Low Level Configuration Settings
  * (address mappings, register initial values, etc.)
diff --git a/include/configs/IVMS8.h b/include/configs/IVMS8.h
index 70e201a352..0b54af5950 100644
--- a/include/configs/IVMS8.h
+++ b/include/configs/IVMS8.h
@@ -84,7 +84,6 @@
  * Miscellaneous configurable options
  */
 #define	CONFIG_SYS_LONGHELP			/* undef to save memory		*/
-#define	CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt	*/
 #if defined(CONFIG_CMD_KGDB)
 #define	CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
 #else
@@ -108,8 +107,6 @@
 #define CONFIG_SYS_PC_ETH_RESET	((ushort)0x0010)	/* PC 11	*/
 #define CONFIG_SYS_PC_IDE_RESET	((ushort)0x0020)	/* PC 10	*/
 
-#define	CONFIG_SYS_HZ		1000		/* decrementer freq: 1 ms ticks	*/
-
 /*
  * Low Level Configuration Settings
  * (address mappings, register initial values, etc.)
diff --git a/include/configs/IceCube.h b/include/configs/IceCube.h
index 2d2394320c..1861aa86d9 100644
--- a/include/configs/IceCube.h
+++ b/include/configs/IceCube.h
@@ -13,8 +13,7 @@
  * (easy to change)
  */
 
-#define CONFIG_MPC5xxx		1	/* This is an MPC5xxx CPU */
-#define CONFIG_MPC5200		1	/* (more precisely a MPC5200 CPU) */
+#define CONFIG_MPC5200		1	/* This is a MPC5200 CPU */
 #define CONFIG_ICECUBE		1	/* ... on IceCube board */
 
 /*
@@ -297,7 +296,6 @@
  * Miscellaneous configurable options
  */
 #define CONFIG_SYS_LONGHELP			/* undef to save memory	    */
-#define CONFIG_SYS_PROMPT		"=> "	/* Monitor Command Prompt   */
 #if defined(CONFIG_CMD_KGDB)
 #define CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size  */
 #else
@@ -315,8 +313,6 @@
 
 #define CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address */
 
-#define CONFIG_SYS_HZ			1000	/* decrementer freq: 1 ms ticks */
-
 #define CONFIG_SYS_CACHELINE_SIZE	32	/* For MPC5xxx CPUs */
 #if defined(CONFIG_CMD_KGDB)
 #  define CONFIG_SYS_CACHELINE_SHIFT	5	/* log base 2 of the above value */
diff --git a/include/configs/JSE.h b/include/configs/JSE.h
index 0bea46c03c..5cc25576ae 100644
--- a/include/configs/JSE.h
+++ b/include/configs/JSE.h
@@ -20,8 +20,6 @@
 #define CONFIG_JSE 1
   /* JSE has a PPC405GPr */
 #define CONFIG_405GP 1
-  /* ... which is a 4xxx series */
-#define CONFIG_4x   1
   /* ... with a 33MHz OSC. connected to the SysCLK input */
 #define CONFIG_SYS_CLK_FREQ	33333333
   /* ... with on-chip memory here (4KBytes) */
@@ -156,7 +154,6 @@
  * Miscellaneous configurable options
  */
 #define CONFIG_SYS_LONGHELP			/* undef to save memory		*/
-#define CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt	*/
 
 #define CONFIG_SYS_HUSH_PARSER			/* use "hush" command parser	*/
 
@@ -192,8 +189,6 @@
 #define CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address */
 #define CONFIG_SYS_EXTBDINFO		1	/* To use extended board_into (bd_t) */
 
-#define CONFIG_SYS_HZ		1000		/* decrementer freq: 1 ms ticks */
-
 #define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_PPC4XX
 #define CONFIG_SYS_I2C_PPC4XX_CH0
@@ -277,6 +272,5 @@
 
 #if defined(CONFIG_CMD_KGDB)
 #define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
-#define CONFIG_KGDB_SER_INDEX	2	/* which serial port to use */
 #endif
 #endif	/* __CONFIG_H */
diff --git a/include/configs/KAREF.h b/include/configs/KAREF.h
index da447f5765..546b725317 100644
--- a/include/configs/KAREF.h
+++ b/include/configs/KAREF.h
@@ -23,7 +23,6 @@
 #define CONFIG_KAREF	     1		/* Board is Kamino Ref Variant */
 #define CONFIG_440GX		  1	     /* Specifc GX support	*/
 #define CONFIG_440		  1	     /* ... PPC440 family	*/
-#define CONFIG_4xx		  1	     /* ... PPC4xx family	*/
 #define CONFIG_BOARD_EARLY_INIT_F 1	     /* Call board_pre_init	*/
 #define CONFIG_MISC_INIT_F	  1	     /* Call board misc_init_f	*/
 #define CONFIG_MISC_INIT_R	  1	     /* Call board misc_init_r	*/
@@ -273,7 +272,6 @@
 
 #if defined(CONFIG_CMD_KGDB)
 #define CONFIG_KGDB_BAUDRATE  230400	     /* kgdb serial port baud	*/
-#define CONFIG_KGDB_SER_INDEX 2		     /* kgdb serial port	*/
 #endif
 
 /*-----------------------------------------------------------------------
@@ -283,7 +281,4 @@
 #define CONFIG_SYS_LOAD_ADDR	      0x8000000	     /* default load address	*/
 #define CONFIG_SYS_EXTBDINFO	      1		     /* use extended board_info */
 
-#define CONFIG_SYS_HZ		      100	     /* decr freq: 1 ms ticks	*/
-
-
 #endif	/* __CONFIG_H */
diff --git a/include/configs/KUP4K.h b/include/configs/KUP4K.h
index 3b8e781c9f..7cf09d01f6 100644
--- a/include/configs/KUP4K.h
+++ b/include/configs/KUP4K.h
@@ -154,7 +154,6 @@
  * Miscellaneous configurable options
  */
 #define CONFIG_SYS_LONGHELP			/* undef to save memory		*/
-#define CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt	*/
 #if defined(CONFIG_CMD_KGDB)
 #define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
 #else
@@ -172,8 +171,6 @@
 
 #define CONFIG_SYS_LOAD_ADDR		0x400000	/* default load address */
 
-#define CONFIG_SYS_HZ			1000		/* decrementer freq: 1 ms ticks */
-
 #define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 115200 }
 
 #define CONFIG_SYS_CONSOLE_INFO_QUIET 1
diff --git a/include/configs/KUP4X.h b/include/configs/KUP4X.h
index 748c8341ac..47d16233a3 100644
--- a/include/configs/KUP4X.h
+++ b/include/configs/KUP4X.h
@@ -177,7 +177,6 @@
  * Miscellaneous configurable options
  */
 #define CONFIG_SYS_LONGHELP			/* undef to save memory		*/
-#define CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt	*/
 #if defined(CONFIG_CMD_KGDB)
 #define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
 #else
@@ -191,8 +190,6 @@
 #define CONFIG_SYS_MEMTEST_END		0x003C00000	/* 4 ... 60 MB in DRAM	*/
 #define CONFIG_SYS_LOAD_ADDR		0x200000	/* default load address */
 
-#define CONFIG_SYS_HZ		1000		/* decrementer freq: 1 ms ticks */
-
 #define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 115200 }
 
 #define CONFIG_SYS_CONSOLE_INFO_QUIET 1
diff --git a/include/configs/M5208EVBE.h b/include/configs/M5208EVBE.h
index 51919dbb3f..66303773c3 100644
--- a/include/configs/M5208EVBE.h
+++ b/include/configs/M5208EVBE.h
@@ -113,7 +113,6 @@
 #define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Arg Buf Sz */
 #define CONFIG_SYS_LOAD_ADDR	0x40010000
 
-#define CONFIG_SYS_HZ		1000
 #define CONFIG_SYS_CLK		166666666	/* CPU Core Clock */
 #define CONFIG_SYS_PLL_ODR	0x36
 #define CONFIG_SYS_PLL_FDR	0x7D
diff --git a/include/configs/M52277EVB.h b/include/configs/M52277EVB.h
index 9aac784392..cde7305954 100644
--- a/include/configs/M52277EVB.h
+++ b/include/configs/M52277EVB.h
@@ -176,8 +176,6 @@
 
 #define CONFIG_SYS_LOAD_ADDR	(CONFIG_SYS_SDRAM_BASE + 0x10000)
 
-#define CONFIG_SYS_HZ		1000
-
 #define CONFIG_SYS_MBAR		0xFC000000
 
 /*
diff --git a/include/configs/M5235EVB.h b/include/configs/M5235EVB.h
index 774db310e0..0f6e2f72cf 100644
--- a/include/configs/M5235EVB.h
+++ b/include/configs/M5235EVB.h
@@ -133,7 +133,6 @@
 #define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size    */
 #define CONFIG_SYS_LOAD_ADDR		(CONFIG_SYS_SDRAM_BASE+0x20000)
 
-#define CONFIG_SYS_HZ			1000
 #define CONFIG_SYS_CLK			75000000
 #define CONFIG_SYS_CPU_CLK		CONFIG_SYS_CLK * 2
 
diff --git a/include/configs/M5249EVB.h b/include/configs/M5249EVB.h
index c6ebdc9f35..ae4fe45fce 100644
--- a/include/configs/M5249EVB.h
+++ b/include/configs/M5249EVB.h
@@ -46,7 +46,6 @@
 #define CONFIG_CMD_CACHE
 #undef CONFIG_CMD_NET
 
-#define CONFIG_SYS_PROMPT		"=> "
 #define CONFIG_SYS_LONGHELP				/* undef to save memory		*/
 
 #if defined(CONFIG_CMD_KGDB)
@@ -69,8 +68,6 @@
 #define CONFIG_SYS_MEMTEST_START	0x400
 #define CONFIG_SYS_MEMTEST_END		0x380000
 
-#define CONFIG_SYS_HZ			1000
-
 /*
  * Clock configuration: enable only one of the following options
  */
diff --git a/include/configs/M5253DEMO.h b/include/configs/M5253DEMO.h
index 240bc7ed80..3a1cbcae93 100644
--- a/include/configs/M5253DEMO.h
+++ b/include/configs/M5253DEMO.h
@@ -1,4 +1,4 @@
-TABILITY or FITNESS FO04-2007 Freescale Semiconductor, Inc.
+/* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
  * Hayden Fraser (Hayden.Fraser@freescale.com)
  *
  * SPDX-License-Identifier:	GPL-2.0+
@@ -107,7 +107,6 @@ TABILITY or FITNESS FO04-2007 Freescale Semiconductor, Inc.
 #define CONFIG_SYS_I2C_PINMUX_CLR	(0xFFFFE7FF)
 #define CONFIG_SYS_I2C_PINMUX_SET	(0)
 
-#define CONFIG_SYS_PROMPT		"=> "
 #define CONFIG_SYS_LONGHELP		/* undef to save memory */
 
 #if defined(CONFIG_CMD_KGDB)
@@ -124,8 +123,6 @@ TABILITY or FITNESS FO04-2007 Freescale Semiconductor, Inc.
 #define CONFIG_SYS_MEMTEST_START	0x400
 #define CONFIG_SYS_MEMTEST_END		0x380000
 
-#define CONFIG_SYS_HZ			1000
-
 #undef CONFIG_SYS_PLL_BYPASS		/* bypass PLL for test purpose */
 #define CONFIG_SYS_FAST_CLK
 #ifdef CONFIG_SYS_FAST_CLK
diff --git a/include/configs/M5253EVBE.h b/include/configs/M5253EVBE.h
index 629372a5f5..fabfdb93db 100644
--- a/include/configs/M5253EVBE.h
+++ b/include/configs/M5253EVBE.h
@@ -76,7 +76,6 @@
 #define CONFIG_SYS_ATA_ALT_OFFSET	0xC0	/* Offset for alternate registers */
 #define CONFIG_SYS_ATA_STRIDE		4	/* Interval between registers */
 
-#define CONFIG_SYS_PROMPT		"=> "
 #define CONFIG_SYS_LONGHELP		/* undef to save memory */
 
 #if defined(CONFIG_CMD_KGDB)
@@ -93,8 +92,6 @@
 #define CONFIG_SYS_MEMTEST_START	0x400
 #define CONFIG_SYS_MEMTEST_END		0x380000
 
-#define CONFIG_SYS_HZ			1000
-
 #undef CONFIG_SYS_PLL_BYPASS		/* bypass PLL for test purpose */
 #define CONFIG_SYS_FAST_CLK
 #ifdef CONFIG_SYS_FAST_CLK
diff --git a/include/configs/M5271EVB.h b/include/configs/M5271EVB.h
deleted file mode 100644
index b7b2e18e3e..0000000000
--- a/include/configs/M5271EVB.h
+++ /dev/null
@@ -1,235 +0,0 @@
-/*
- * Configuation settings for the Freescale M5271EVB
- *
- * Based on MC5272C3 and r5200 board configs
- * (C) Copyright 2006 Lab X Technologies <zachary.landau@labxtechnologies.com>
- * (C) Copyright 2003 Josef Baumgartner <josef.baumgartner@telex.de>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-/*
- * board/config.h - configuration options, board specific
- */
-
-#ifndef _M5271EVB_H
-#define _M5271EVB_H
-
-/*
- * High Level Configuration Options (easy to change)
- */
-#define CONFIG_MCF52x2		/* define processor family */
-#define CONFIG_M5271		/* define processor type */
-#define CONFIG_M5271EVB		/* define board type */
-
-#define CONFIG_MCFTMR
-
-#define CONFIG_MCFUART
-#define CONFIG_SYS_UART_PORT		(0)
-#define CONFIG_BAUDRATE		115200
-
-#undef CONFIG_WATCHDOG		/* disable watchdog */
-
-/* Configuration for environment
- * Environment is embedded in u-boot in the second sector of the flash
- */
-#ifndef CONFIG_MONITOR_IS_IN_RAM
-#define CONFIG_ENV_OFFSET		0x4000
-#else
-#define CONFIG_ENV_ADDR		0xffe04000
-#endif
-#define CONFIG_ENV_SECT_SIZE	0x2000
-#define CONFIG_ENV_IS_IN_FLASH	1
-#define	CONFIG_SYS_USE_PPCENV			/* Environment embedded in sect .ppcenv */
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_CACHE
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_NET
-#define CONFIG_CMD_MII
-#define CONFIG_CMD_ELF
-#define CONFIG_CMD_FLASH
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_MEMORY
-#define CONFIG_CMD_MISC
-
-#undef CONFIG_CMD_LOADS
-#define CONFIG_CMD_LOADB
-#define CONFIG_CMDLINE_EDITING	1 /* enables command line history */
-#define CONFIG_SYS_HUSH_PARSER /* Use the HUSH parser */
-
-#define CONFIG_MCFFEC
-#ifdef CONFIG_MCFFEC
-#	define CONFIG_MII		1
-#	define CONFIG_MII_INIT		1
-#	define CONFIG_SYS_DISCOVER_PHY
-#	define CONFIG_SYS_RX_ETH_BUFFER	8
-#	define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
-
-#	define CONFIG_SYS_FEC0_PINMUX		0
-#	define CONFIG_SYS_FEC0_MIIBASE		CONFIG_SYS_FEC0_IOBASE
-#	define MCFFEC_TOUT_LOOP		50000
-/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
-#	ifndef CONFIG_SYS_DISCOVER_PHY
-#		define FECDUPLEX	FULL
-#		define FECSPEED		_100BASET
-#	else
-#		ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
-#			define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
-#		endif
-#	endif			/* CONFIG_SYS_DISCOVER_PHY */
-#endif
-
-/* I2C */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_FSL
-#define CONFIG_SYS_FSL_I2C_SPEED	80000
-#define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
-#define CONFIG_SYS_FSL_I2C_OFFSET	0x00000300
-#define CONFIG_SYS_IMMR		CONFIG_SYS_MBAR
-
-#define CONFIG_BOOTDELAY	1	/* autoboot after 1 seconds */
-#define CONFIG_BOOTFILE		"u-boot.bin"
-#ifdef CONFIG_MCFFEC
-#	define CONFIG_NET_RETRY_COUNT	5
-#	define CONFIG_ETHADDR	00:e0:0c:bc:e5:60
-#	define CONFIG_IPADDR	192.162.1.2
-#	define CONFIG_NETMASK	255.255.255.0
-#	define CONFIG_SERVERIP	192.162.1.1
-#	define CONFIG_GATEWAYIP	192.162.1.1
-#	define CONFIG_OVERWRITE_ETHADDR_ONCE
-#endif				/* FEC_ENET */
-
-#define CONFIG_HOSTNAME		M5271EVB
-#define CONFIG_EXTRA_ENV_SETTINGS		\
-	"netdev=eth0\0"				\
-	"loadaddr=10000\0"			\
-	"uboot=u-boot.bin\0"		\
-	"load=tftp $loadaddr $uboot\0"	\
-	"upd=run load; run prog\0"		\
-	"prog=prot off ffe00000 ffe3ffff;"	\
-	"era ffe00000 ffe3ffff;"		\
-	"cp.b $loadaddr ffe00000 $filesize;"	\
-	"save\0"				\
-	""
-
-#define CONFIG_SYS_PROMPT		"=> "
-#define CONFIG_SYS_LONGHELP		/* undef to save memory */
-
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size      */
-#else
-#define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size      */
-#endif
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)	/* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS		16	/* max number of command args   */
-#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size    */
-
-#define CONFIG_SYS_LOAD_ADDR		0x00100000
-
-#define CONFIG_SYS_MEMTEST_START	0x400
-#define CONFIG_SYS_MEMTEST_END		0x380000
-
-#define CONFIG_SYS_HZ			1000000
-
-/* Clock configuration
- * The external oscillator is a 25.000 MHz
- * CONFIG_SYS_CLK for ColdFire V2 sets cpu_clk (not bus_clk)
- * bus_clk = (cpu_clk/2) (fixed ratio)
- *
- * If CONFIG_SYS_CLK is changed. the CONFIG_SYS_MCF_SYNCR must be updated to
- * match the new clock speed. Max cpu_clk is 150 MHz.
- */
-#define CONFIG_SYS_CLK			100000000
-#define CONFIG_SYS_MCF_SYNCR 	(MCF_SYNCR_MFD_4X | MCF_SYNCR_RFD_DIV1)
-
-/*
- * Low Level Configuration Settings
- * (address mappings, register initial values, etc.)
- * You should know what you are doing if you make changes here.
- */
-
-#define CONFIG_SYS_MBAR		0x40000000	/* Register Base Addrs */
-
-/*
- * Definitions for initial stack pointer and data area (in DPRAM)
- */
-#define CONFIG_SYS_INIT_RAM_ADDR	0x20000000
-#define CONFIG_SYS_INIT_RAM_SIZE	0x1000	/* Size of used area in internal SRAM    */
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
-
-/*
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
- */
-#define CONFIG_SYS_SDRAM_BASE		0x00000000
-#define CONFIG_SYS_SDRAM_SIZE		16	/* SDRAM size in MB */
-#define CONFIG_SYS_FLASH_BASE		0xffe00000
-
-#ifdef	CONFIG_MONITOR_IS_IN_RAM
-#define CONFIG_SYS_MONITOR_BASE	0x20000
-#else
-#define CONFIG_SYS_MONITOR_BASE	(CONFIG_SYS_FLASH_BASE + 0x400)
-#endif
-
-#define CONFIG_SYS_MONITOR_LEN		0x40000
-#define CONFIG_SYS_MALLOC_LEN		(256 << 10)
-#define CONFIG_SYS_BOOTPARAMS_LEN	(64*1024)
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization ??
- */
-#define CONFIG_SYS_BOOTMAPSZ		(CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
-
-/* FLASH organization */
-#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks           */
-#define CONFIG_SYS_MAX_FLASH_SECT	11	/* max number of sectors on one chip    */
-#define CONFIG_SYS_FLASH_ERASE_TOUT	1000
-
-#define CONFIG_SYS_FLASH_CFI		1
-#define CONFIG_FLASH_CFI_DRIVER	1
-#define CONFIG_SYS_FLASH_SIZE		0x200000
-
-/* Cache Configuration */
-#define CONFIG_SYS_CACHELINE_SIZE	16
-
-#define ICACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
-					 CONFIG_SYS_INIT_RAM_SIZE - 8)
-#define DCACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
-					 CONFIG_SYS_INIT_RAM_SIZE - 4)
-#define CONFIG_SYS_ICACHE_INV		(CF_CACR_CINV | CF_CACR_INVI)
-#define CONFIG_SYS_CACHE_ACR0		(CONFIG_SYS_SDRAM_BASE | \
-					 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
-					 CF_ACR_EN | CF_ACR_SM_ALL)
-#define CONFIG_SYS_CACHE_ICACR		(CF_CACR_CENB | CF_CACR_CINV | \
-					 CF_CACR_DISD | CF_CACR_INVI | \
-					 CF_CACR_CEIB | CF_CACR_DCM | \
-					 CF_CACR_EUSP)
-
-/* Chip Select 0  : Boot Flash */
-#define CONFIG_SYS_CS0_BASE	0xFFE00000
-#define CONFIG_SYS_CS0_MASK	0x001F0001
-#define CONFIG_SYS_CS0_CTRL	0x00001980
-
-/* Chip Select 1 : External SRAM */
-#define CONFIG_SYS_CS1_BASE	0x30000000
-#define CONFIG_SYS_CS1_MASK	0x00070001
-#define CONFIG_SYS_CS1_CTRL	0x00001900
-
-#endif				/* _M5271EVB_H */
diff --git a/include/configs/M5272C3.h b/include/configs/M5272C3.h
index 01d42ad6dc..4c84126559 100644
--- a/include/configs/M5272C3.h
+++ b/include/configs/M5272C3.h
@@ -129,7 +129,6 @@
 #define CONFIG_SYS_LOAD_ADDR		0x20000
 #define CONFIG_SYS_MEMTEST_START	0x400
 #define CONFIG_SYS_MEMTEST_END		0x380000
-#define CONFIG_SYS_HZ			1000
 #define CONFIG_SYS_CLK			66000000
 
 /*
diff --git a/include/configs/M5275EVB.h b/include/configs/M5275EVB.h
index f99a545fe6..4dddab7c1d 100644
--- a/include/configs/M5275EVB.h
+++ b/include/configs/M5275EVB.h
@@ -139,7 +139,6 @@
 	"save\0"				\
 	""
 
-#define CONFIG_SYS_HZ			1000
 #define CONFIG_SYS_CLK			150000000
 
 /*
diff --git a/include/configs/M5282EVB.h b/include/configs/M5282EVB.h
index d22018f127..fd970d0787 100644
--- a/include/configs/M5282EVB.h
+++ b/include/configs/M5282EVB.h
@@ -117,7 +117,6 @@
 #define CONFIG_SYS_MEMTEST_START	0x400
 #define CONFIG_SYS_MEMTEST_END		0x380000
 
-#define CONFIG_SYS_HZ			1000
 #define	CONFIG_SYS_CLK			64000000
 
 /* PLL Configuration: Ext Clock * 6 (see table 9-4 of MCF user manual) */
diff --git a/include/configs/M53017EVB.h b/include/configs/M53017EVB.h
index 3bf5989f2b..a100d9f316 100644
--- a/include/configs/M53017EVB.h
+++ b/include/configs/M53017EVB.h
@@ -133,7 +133,6 @@
 #define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Arg Buf Sz */
 #define CONFIG_SYS_LOAD_ADDR	0x40010000
 
-#define CONFIG_SYS_HZ		1000
 #define CONFIG_SYS_CLK		80000000
 #define CONFIG_SYS_CPU_CLK	CONFIG_SYS_CLK * 3
 
diff --git a/include/configs/M5329EVB.h b/include/configs/M5329EVB.h
index 85b4435d8b..78ea384375 100644
--- a/include/configs/M5329EVB.h
+++ b/include/configs/M5329EVB.h
@@ -126,7 +126,6 @@
 #define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size    */
 #define CONFIG_SYS_LOAD_ADDR		0x40010000
 
-#define CONFIG_SYS_HZ			1000
 #define CONFIG_SYS_CLK			80000000
 #define CONFIG_SYS_CPU_CLK		CONFIG_SYS_CLK * 3
 
diff --git a/include/configs/M5373EVB.h b/include/configs/M5373EVB.h
index ccb5d05f4e..849c26562a 100644
--- a/include/configs/M5373EVB.h
+++ b/include/configs/M5373EVB.h
@@ -126,7 +126,6 @@
 #define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size    */
 #define CONFIG_SYS_LOAD_ADDR		0x40010000
 
-#define CONFIG_SYS_HZ			1000
 #define CONFIG_SYS_CLK			80000000
 #define CONFIG_SYS_CPU_CLK		CONFIG_SYS_CLK * 3
 
diff --git a/include/configs/M54418TWR.h b/include/configs/M54418TWR.h
index 6271bdeebd..3d7dc1fb2d 100644
--- a/include/configs/M54418TWR.h
+++ b/include/configs/M54418TWR.h
@@ -77,7 +77,6 @@
 #define CONFIG_SYS_MAX_NAND_DEVICE	1
 #define NAND_MAX_CHIPS			CONFIG_SYS_MAX_NAND_DEVICE
 #define CONFIG_SYS_NAND_SELECT_DEVICE
-#define	CONFIG_SYS_64BIT_VSPRINTF	/* needed for nand_util.c */
 #endif
 
 /* Network configuration */
@@ -253,8 +252,6 @@
 
 #define CONFIG_SYS_LOAD_ADDR		(CONFIG_SYS_SDRAM_BASE + 0x10000)
 
-#define CONFIG_SYS_HZ			1000
-
 #define CONFIG_SYS_MBAR		0xFC000000
 
 /*
@@ -270,10 +267,8 @@
 /* End of used area in internal SRAM */
 #define CONFIG_SYS_INIT_RAM_SIZE	0x10000
 #define CONFIG_SYS_INIT_RAM_CTRL	0x221
-/* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_SIZE	256
 #define CONFIG_SYS_GBL_DATA_OFFSET	((CONFIG_SYS_INIT_RAM_SIZE - \
-					CONFIG_SYS_GBL_DATA_SIZE) - 32)
+					GENERATED_GBL_DATA_SIZE) - 32)
 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 #define CONFIG_SYS_SBFHDR_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - 32)
 
diff --git a/include/configs/M54451EVB.h b/include/configs/M54451EVB.h
index 7fc5153c0f..0f4b726f3a 100644
--- a/include/configs/M54451EVB.h
+++ b/include/configs/M54451EVB.h
@@ -187,8 +187,6 @@
 
 #define CONFIG_SYS_LOAD_ADDR		(CONFIG_SYS_SDRAM_BASE + 0x10000)
 
-#define CONFIG_SYS_HZ			1000
-
 #define CONFIG_SYS_MBAR			0xFC000000
 
 /*
diff --git a/include/configs/M54455EVB.h b/include/configs/M54455EVB.h
index d3e6457b12..7a55d3c619 100644
--- a/include/configs/M54455EVB.h
+++ b/include/configs/M54455EVB.h
@@ -177,7 +177,7 @@
 #define CONFIG_SYS_I2C_FSL
 #define CONFIG_SYS_FSL_I2C_SPEED	80000
 #define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
-#define CONFIG_SYS_FSLI2C_OFFSET	0x58000
+#define CONFIG_SYS_FSL_I2C_OFFSET	0x58000
 #define CONFIG_SYS_IMMR		CONFIG_SYS_MBAR
 
 /* DSPI and Serial Flash */
@@ -246,8 +246,6 @@
 
 #define CONFIG_SYS_LOAD_ADDR		(CONFIG_SYS_SDRAM_BASE + 0x10000)
 
-#define CONFIG_SYS_HZ			1000
-
 #define CONFIG_SYS_MBAR		0xFC000000
 
 /*
diff --git a/include/configs/M5475EVB.h b/include/configs/M5475EVB.h
index 75c2b0748b..e88a6bd8d3 100644
--- a/include/configs/M5475EVB.h
+++ b/include/configs/M5475EVB.h
@@ -172,7 +172,6 @@
 #define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size    */
 #define CONFIG_SYS_LOAD_ADDR		0x00010000
 
-#define CONFIG_SYS_HZ			1000
 #define CONFIG_SYS_CLK			CONFIG_SYS_BUSCLK
 #define CONFIG_SYS_CPU_CLK		CONFIG_SYS_CLK * 2
 
diff --git a/include/configs/M5485EVB.h b/include/configs/M5485EVB.h
index a15ee7dc13..e4128062a9 100644
--- a/include/configs/M5485EVB.h
+++ b/include/configs/M5485EVB.h
@@ -158,7 +158,6 @@
 #define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size    */
 #define CONFIG_SYS_LOAD_ADDR		0x00010000
 
-#define CONFIG_SYS_HZ			1000
 #define CONFIG_SYS_CLK			CONFIG_SYS_BUSCLK
 #define CONFIG_SYS_CPU_CLK		CONFIG_SYS_CLK * 2
 
diff --git a/include/configs/MBX.h b/include/configs/MBX.h
index b3cd12df90..96edd442d0 100644
--- a/include/configs/MBX.h
+++ b/include/configs/MBX.h
@@ -82,7 +82,6 @@
  * Miscellaneous configurable options
  */
 #define CONFIG_SYS_LONGHELP			/* undef to save memory		*/
-#define CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt	*/
 #undef	CONFIG_SYS_HUSH_PARSER			/* Hush parse for U-Boot	*/
 #if defined(CONFIG_CMD_KGDB)
 #define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
@@ -98,8 +97,6 @@
 
 #define CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address */
 
-#define CONFIG_SYS_HZ		1000		/* decrementer freq: 1 ms ticks */
-
 /*
  * Low Level Configuration Settings
  * (address mappings, register initial values, etc.)
diff --git a/include/configs/MBX860T.h b/include/configs/MBX860T.h
index 8d1ca48233..74f44df682 100644
--- a/include/configs/MBX860T.h
+++ b/include/configs/MBX860T.h
@@ -72,8 +72,6 @@
 
 #define	CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address	*/
 
-#define	CONFIG_SYS_HZ		1000		/* decrementer freq: 1 ms ticks	*/
-
 /*
  * Low Level Configuration Settings
  * (address mappings, register initial values, etc.)
diff --git a/include/configs/MERGERBOX.h b/include/configs/MERGERBOX.h
index ad9c77e1c8..19ea3167af 100644
--- a/include/configs/MERGERBOX.h
+++ b/include/configs/MERGERBOX.h
@@ -16,7 +16,6 @@
  * High Level Configuration Options
  */
 #define CONFIG_E300	1
-#define CONFIG_MPC83xx	1
 #define CONFIG_MPC837x	1
 #define CONFIG_MPC8377	1
 
@@ -122,9 +121,8 @@
 #define CONFIG_SYS_INIT_RAM_LOCK	1
 #define CONFIG_SYS_INIT_RAM_ADDR	0xE6000000 /* Initial RAM address */
 #define CONFIG_SYS_INIT_RAM_SIZE	0x1000 /* End of used area in RAM */
-#define CONFIG_SYS_GBL_DATA_SIZE	0x100 /* num bytes initial data */
 #define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE -\
-					 CONFIG_SYS_GBL_DATA_SIZE)
+					 GENERATED_GBL_DATA_SIZE)
 
 /*
  * Local Bus Configuration & Clock Setup
@@ -314,6 +312,7 @@
 #define CONFIG_BOOTP_NTPSERVER
 #define CONFIG_BOOTP_RANDOM_DELAY
 #define CONFIG_BOOTP_SEND_HOSTNAME
+#define CONFIG_LIB_RAND
 
 /*
  * Command line configuration.
@@ -361,13 +360,11 @@
 #define CONFIG_SYS_LONGHELP
 #define CONFIG_SYS_LOAD_ADDR	0x2000000
 #define CONFIG_LOADADDR		0x4000000
-#define CONFIG_SYS_PROMPT	"=> "
 #define CONFIG_SYS_CBSIZE	256
 
 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
 #define CONFIG_SYS_MAXARGS	16
 #define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE
-#define CONFIG_SYS_HZ		1000
 
 #define CONFIG_LOADS_ECHO		1
 #define CONFIG_SYS_LOADS_BAUD_CHANGE	1
diff --git a/include/configs/METROBOX.h b/include/configs/METROBOX.h
index abb6baa401..69ab5bb517 100644
--- a/include/configs/METROBOX.h
+++ b/include/configs/METROBOX.h
@@ -89,7 +89,6 @@
 #define CONFIG_METROBOX		  1	     /* Board is Metrobox	*/
 #define CONFIG_440GX		  1	     /* Specifc GX support	*/
 #define CONFIG_440		  1	     /* ... PPC440 family	*/
-#define CONFIG_4xx		  1	     /* ... PPC4xx family	*/
 #define CONFIG_BOARD_EARLY_INIT_F 1	     /* Call board_pre_init	*/
 #define CONFIG_MISC_INIT_F	  1	     /* Call board misc_init_f	*/
 #define CONFIG_MISC_INIT_R	  1	     /* Call board misc_init_r	*/
@@ -338,7 +337,6 @@
 
 #if defined(CONFIG_CMD_KGDB)
 #define CONFIG_KGDB_BAUDRATE  230400	     /* kgdb serial port baud	*/
-#define CONFIG_KGDB_SER_INDEX 2		     /* kgdb serial port	*/
 #endif
 
 /*-----------------------------------------------------------------------
@@ -348,7 +346,4 @@
 #define CONFIG_SYS_LOAD_ADDR	      0x8000000	     /* default load address	*/
 #define CONFIG_SYS_EXTBDINFO	      1		     /* use extended board_info */
 
-#define CONFIG_SYS_HZ		      100	     /* decr freq: 1 ms ticks	*/
-
-
 #endif	/* __CONFIG_H */
diff --git a/include/configs/MHPC.h b/include/configs/MHPC.h
index 0c7a466ba3..6314b5380d 100644
--- a/include/configs/MHPC.h
+++ b/include/configs/MHPC.h
@@ -129,7 +129,6 @@
  * Miscellaneous configurable options
  */
 #define CONFIG_SYS_LONGHELP			/* undef to save memory		*/
-#define CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt	*/
 #if defined(CONFIG_CMD_KGDB)
 #define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
 #else
@@ -144,8 +143,6 @@
 
 #define CONFIG_SYS_LOAD_ADDR		0x300000	/* default load address */
 
-#define CONFIG_SYS_HZ			1000		/* decrementer freq: 1 ms ticks */
-
 /*
  * Low Level Configuration Settings
  * (address mappings, register initial values, etc.)
diff --git a/include/configs/MIP405.h b/include/configs/MIP405.h
index 5ced2df71d..68824fd2d4 100644
--- a/include/configs/MIP405.h
+++ b/include/configs/MIP405.h
@@ -17,7 +17,6 @@
  * (easy to change)
  ***********************************************************/
 #define CONFIG_405GP		1	/* This is a PPC405 CPU		*/
-#define CONFIG_4xx		1	/* ...member of PPC4xx family	*/
 #define CONFIG_MIP405		1	/* ...on a MIP405 board		*/
 
 #define	CONFIG_SYS_TEXT_BASE	0xFFF80000
@@ -150,7 +149,6 @@
  * Miscellaneous configurable options
  **********************************************************/
 #define CONFIG_SYS_LONGHELP			/* undef to save memory		*/
-#define CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt	*/
 #if defined(CONFIG_CMD_KGDB)
 #define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
 #else
@@ -180,8 +178,6 @@
 #define CONFIG_SYS_LOAD_ADDR	0x400000	/* default load address */
 #define CONFIG_SYS_EXTBDINFO	1		/* To use extended board_into (bd_t) */
 
-#define CONFIG_SYS_HZ		1000		/* decrementer freq: 1 ms ticks */
-
 /*-----------------------------------------------------------------------
  * PCI stuff
  *-----------------------------------------------------------------------
@@ -399,7 +395,6 @@
  ************************************************************/
 #if defined(CONFIG_CMD_KGDB)
 #define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
-#define CONFIG_KGDB_SER_INDEX	2	/* which serial port to use */
 #endif
 
 /************************************************************
diff --git a/include/configs/MOUSSE.h b/include/configs/MOUSSE.h
index 3cdc0bb145..e84d12f3f8 100644
--- a/include/configs/MOUSSE.h
+++ b/include/configs/MOUSSE.h
@@ -29,7 +29,6 @@
  * (easy to change)
  */
 
-#define CONFIG_MPC824X      1
 #define CONFIG_MPC8240      1
 #define CONFIG_MOUSSE       1
 
@@ -78,7 +77,6 @@
  * Miscellaneous configurable options
  */
 #undef CONFIG_SYS_LONGHELP                /* undef to save memory     */
-#define CONFIG_SYS_PROMPT      "=>"  /* Monitor Command Prompt   */
 #define CONFIG_SYS_CBSIZE      256        /* Console I/O Buffer Size  */
 #define CONFIG_SYS_PBSIZE      (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
 #define CONFIG_SYS_MAXARGS     8           /* Max number of command args   */
@@ -153,7 +151,6 @@
 
 #define CONFIG_SYS_CLK_FREQ  33000000	/* external frequency to pll */
 #define CONFIG_PLL_PCI_TO_MEM_MULTIPLIER  2
-#define CONFIG_SYS_HZ               1000
 
 #define CONFIG_SYS_ETH_DEV_FN       0x00
 #define CONFIG_SYS_ETH_IOBASE       0x00104000
diff --git a/include/configs/MPC8260ADS.h b/include/configs/MPC8260ADS.h
index d461d004a2..39f7564b74 100644
--- a/include/configs/MPC8260ADS.h
+++ b/include/configs/MPC8260ADS.h
@@ -64,8 +64,6 @@
  * details. :-(
  */
 #define CONFIG_MPC8272		1
-#else
-#define CONFIG_MPC8260		1
 #endif /* CONFIG_ADSTYPE == CONFIG_SYS_8272ADS */
 
 #define CONFIG_BOARD_EARLY_INIT_F 1	/* Call board_early_init_f	*/
@@ -272,7 +270,6 @@
  */
 #define CONFIG_SYS_HUSH_PARSER
 #define CONFIG_SYS_LONGHELP			/* undef to save memory	    */
-#define CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt   */
 #if defined(CONFIG_CMD_KGDB)
 #define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size  */
 #else
@@ -287,8 +284,6 @@
 
 #define CONFIG_SYS_LOAD_ADDR		0x400000	/* default load address */
 
-#define CONFIG_SYS_HZ			1000	/* decrementer freq: 1 ms ticks */
-
 #define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
 
 #define CONFIG_SYS_FLASH_BASE		0xff800000
diff --git a/include/configs/MPC8266ADS.h b/include/configs/MPC8266ADS.h
index f71105157f..8d9c8fb45c 100644
--- a/include/configs/MPC8266ADS.h
+++ b/include/configs/MPC8266ADS.h
@@ -33,7 +33,6 @@
  * (easy to change)
  */
 
-#define CONFIG_MPC8260		1	/* This is an MPC8260 CPU	*/
 #define CONFIG_MPC8266ADS	1	/* ...on motorola ADS board	*/
 #define CONFIG_CPM2		1	/* Has a CPM2 */
 
@@ -211,7 +210,6 @@
  * Miscellaneous configurable options
  */
 #define CONFIG_SYS_LONGHELP			/* undef to save memory	    */
-#define CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt   */
 #if defined(CONFIG_CMD_KGDB)
 #define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size  */
 #else
@@ -229,8 +227,6 @@
 
 #define CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address */
 
-#define CONFIG_SYS_HZ			1000	/* decrementer freq: 1 ms ticks */
-
 #define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
 
 #define CONFIG_SYS_FLASH_BASE		0xFE000000
diff --git a/include/configs/MPC8308RDB.h b/include/configs/MPC8308RDB.h
index d315729b8b..bf974fd461 100644
--- a/include/configs/MPC8308RDB.h
+++ b/include/configs/MPC8308RDB.h
@@ -13,7 +13,6 @@
  * High Level Configuration Options
  */
 #define CONFIG_E300		1 /* E300 family */
-#define CONFIG_MPC83xx		1 /* MPC83xx family */
 #define CONFIG_MPC830x		1 /* MPC830x family */
 #define CONFIG_MPC8308		1 /* MPC8308 CPU specific */
 #define CONFIG_MPC8308RDB	1 /* MPC8308RDB board specific */
@@ -462,7 +461,6 @@
  */
 #define CONFIG_SYS_LONGHELP		/* undef to save memory */
 #define CONFIG_SYS_LOAD_ADDR		0x2000000 /* default load address */
-#define CONFIG_SYS_PROMPT		"=> "	/* Monitor Command Prompt */
 
 #define CONFIG_SYS_CBSIZE	1024 /* Console I/O Buffer Size */
 
@@ -471,7 +469,6 @@
 #define CONFIG_SYS_MAXARGS	16	/* max number of command args */
 /* Boot Argument Buffer Size */
 #define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE
-#define CONFIG_SYS_HZ		1000	/* decrementer freq: 1ms ticks */
 
 /*
  * For booting Linux, the board info and command line data
diff --git a/include/configs/MPC8313ERDB.h b/include/configs/MPC8313ERDB.h
index 34b960e1f4..69b2cb1970 100644
--- a/include/configs/MPC8313ERDB.h
+++ b/include/configs/MPC8313ERDB.h
@@ -14,7 +14,6 @@
  * High Level Configuration Options
  */
 #define CONFIG_E300		1
-#define CONFIG_MPC83xx		1
 #define CONFIG_MPC831x		1
 #define CONFIG_MPC8313		1
 #define CONFIG_MPC8313ERDB	1
@@ -511,7 +510,6 @@
  */
 #define CONFIG_SYS_LONGHELP			/* undef to save memory */
 #define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
-#define CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt */
 #define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size */
 
 						/* Print Buffer Size */
@@ -520,7 +518,6 @@
 #define CONFIG_SYS_MAXARGS	16	/* max number of command args */
 				/* Boot Argument Buffer Size */
 #define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE
-#define CONFIG_SYS_HZ		1000	/* decrementer freq: 1ms ticks */
 
 /*
  * For booting Linux, the board info and command line data
diff --git a/include/configs/MPC8315ERDB.h b/include/configs/MPC8315ERDB.h
index fef19d4b5f..3dd52ce30f 100644
--- a/include/configs/MPC8315ERDB.h
+++ b/include/configs/MPC8315ERDB.h
@@ -35,7 +35,6 @@
  * High Level Configuration Options
  */
 #define CONFIG_E300		1 /* E300 family */
-#define CONFIG_MPC83xx		1 /* MPC83xx family */
 #define CONFIG_MPC831x		1 /* MPC831x CPU family */
 #define CONFIG_MPC8315		1 /* MPC8315 CPU specific */
 #define CONFIG_MPC8315ERDB	1 /* MPC8315ERDB board specific */
@@ -519,7 +518,6 @@
  */
 #define CONFIG_SYS_LONGHELP		/* undef to save memory */
 #define CONFIG_SYS_LOAD_ADDR		0x2000000 /* default load address */
-#define CONFIG_SYS_PROMPT		"=> "	/* Monitor Command Prompt */
 
 #if defined(CONFIG_CMD_KGDB)
 	#define CONFIG_SYS_CBSIZE	1024 /* Console I/O Buffer Size */
@@ -532,7 +530,6 @@
 #define CONFIG_SYS_MAXARGS	16	/* max number of command args */
 				/* Boot Argument Buffer Size */
 #define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE
-#define CONFIG_SYS_HZ		1000	/* decrementer freq: 1ms ticks */
 
 /*
  * For booting Linux, the board info and command line data
@@ -636,7 +633,6 @@
 
 #if defined(CONFIG_CMD_KGDB)
 #define CONFIG_KGDB_BAUDRATE	230400	/* speed of kgdb serial port */
-#define CONFIG_KGDB_SER_INDEX	2	/* which serial port to use */
 #endif
 
 /*
diff --git a/include/configs/MPC8323ERDB.h b/include/configs/MPC8323ERDB.h
index d5db65df11..65a63e2b7f 100644
--- a/include/configs/MPC8323ERDB.h
+++ b/include/configs/MPC8323ERDB.h
@@ -14,7 +14,6 @@
  */
 #define CONFIG_E300		1	/* E300 family */
 #define CONFIG_QE		1	/* Has QE */
-#define CONFIG_MPC83xx		1	/* MPC83xx family */
 #define CONFIG_MPC832x		1	/* MPC832x CPU specific */
 
 #define	CONFIG_SYS_TEXT_BASE	0xFE000000
@@ -355,7 +354,6 @@
  */
 #define CONFIG_SYS_LONGHELP			/* undef to save memory */
 #define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
-#define CONFIG_SYS_PROMPT	"=> "	/* Monitor Command Prompt */
 
 #if (CONFIG_CMD_KGDB)
 	#define CONFIG_SYS_CBSIZE	1024	/* Console I/O Buffer Size */
@@ -368,7 +366,6 @@
 #define CONFIG_SYS_MAXARGS	16		/* max number of command args */
 				/* Boot Argument Buffer Size */
 #define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE
-#define CONFIG_SYS_HZ		1000	/* decrementer freq: 1ms ticks */
 
 /*
  * For booting Linux, the board info and command line data
@@ -483,7 +480,6 @@
 
 #if (CONFIG_CMD_KGDB)
 #define CONFIG_KGDB_BAUDRATE	230400	/* speed of kgdb serial port */
-#define CONFIG_KGDB_SER_INDEX	2	/* which serial port to use */
 #endif
 
 /*
diff --git a/include/configs/MPC832XEMDS.h b/include/configs/MPC832XEMDS.h
index 32e05af8ab..1735b3c521 100644
--- a/include/configs/MPC832XEMDS.h
+++ b/include/configs/MPC832XEMDS.h
@@ -12,7 +12,6 @@
  */
 #define CONFIG_E300		1	/* E300 family */
 #define CONFIG_QE		1	/* Has QE */
-#define CONFIG_MPC83xx		1	/* MPC83xx family */
 #define CONFIG_MPC832x		1	/* MPC832x CPU specific */
 #define CONFIG_MPC832XEMDS	1	/* MPC832XEMDS board specific */
 
@@ -441,7 +440,6 @@
  */
 #define CONFIG_SYS_LONGHELP	/* undef to save memory */
 #define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
-#define CONFIG_SYS_PROMPT	"=> "	/* Monitor Command Prompt */
 
 #if defined(CONFIG_CMD_KGDB)
 	#define CONFIG_SYS_CBSIZE	1024	/* Console I/O Buffer Size */
@@ -454,7 +452,6 @@
 #define CONFIG_SYS_MAXARGS	16	/* max number of command args */
 				/* Boot Argument Buffer Size */
 #define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE
-#define CONFIG_SYS_HZ		1000	/* decrementer freq: 1ms ticks */
 
 /*
  * For booting Linux, the board info and command line data
@@ -576,7 +573,6 @@
 
 #if defined(CONFIG_CMD_KGDB)
 #define CONFIG_KGDB_BAUDRATE	230400	/* speed of kgdb serial port */
-#define CONFIG_KGDB_SER_INDEX	2	/* which serial port to use */
 #endif
 
 /*
diff --git a/include/configs/MPC8349EMDS.h b/include/configs/MPC8349EMDS.h
index 8a7fad36f4..6b7d648944 100644
--- a/include/configs/MPC8349EMDS.h
+++ b/include/configs/MPC8349EMDS.h
@@ -17,7 +17,6 @@
  * High Level Configuration Options
  */
 #define CONFIG_E300		1	/* E300 Family */
-#define CONFIG_MPC83xx		1	/* MPC83xx family */
 #define CONFIG_MPC834x		1	/* MPC834x family */
 #define CONFIG_MPC8349		1	/* MPC8349 specific */
 #define CONFIG_MPC8349EMDS	1	/* MPC8349EMDS board specific */
@@ -62,11 +61,12 @@
 #define CONFIG_SPD_EEPROM		/* use SPD EEPROM for DDR setup*/
 
 /*
- * define CONFIG_FSL_DDR2 to use unified DDR driver
+ * define CONFIG_SYS_FSL_DDR2 to use unified DDR driver
  * undefine it to use old spd_sdram.c
  */
-#define CONFIG_FSL_DDR2
-#ifdef CONFIG_FSL_DDR2
+#define CONFIG_SYS_FSL_DDR2
+#ifdef CONFIG_SYS_FSL_DDR2
+#define CONFIG_SYS_FSL_DDRC_GEN2
 #define CONFIG_SYS_SPD_BUS_NUM	0
 #define SPD_EEPROM_ADDRESS1	0x52
 #define SPD_EEPROM_ADDRESS2	0x51
@@ -507,7 +507,6 @@
  */
 #define CONFIG_SYS_LONGHELP			/* undef to save memory */
 #define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
-#define CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt */
 
 #if defined(CONFIG_CMD_KGDB)
 	#define CONFIG_SYS_CBSIZE	1024	/* Console I/O Buffer Size */
@@ -520,7 +519,6 @@
 #define CONFIG_SYS_MAXARGS	16	/* max number of command args */
 				/* Boot Argument Buffer Size */
 #define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE
-#define CONFIG_SYS_HZ		1000	/* decrementer freq: 1ms ticks */
 
 /*
  * For booting Linux, the board info and command line data
@@ -738,7 +736,6 @@
 
 #if defined(CONFIG_CMD_KGDB)
 #define CONFIG_KGDB_BAUDRATE	230400	/* speed of kgdb serial port */
-#define CONFIG_KGDB_SER_INDEX	2	/* which serial port to use */
 #endif
 
 /*
diff --git a/include/configs/MPC8349ITX.h b/include/configs/MPC8349ITX.h
index c492d52fb5..398918a940 100644
--- a/include/configs/MPC8349ITX.h
+++ b/include/configs/MPC8349ITX.h
@@ -47,7 +47,6 @@
 /*
  * High Level Configuration Options
  */
-#define CONFIG_MPC83xx		1
 #define CONFIG_MPC834x		/* MPC834x family (8343, 8347, 8349) */
 #define CONFIG_MPC8349		/* MPC8349 specific */
 
@@ -562,7 +561,6 @@ boards, we say we have two, but don't display a message if we find only one. */
 #define CONFIG_SYS_MAXARGS	16	/* max number of command args */
 				/* Boot Argument Buffer Size */
 #define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE
-#define CONFIG_SYS_HZ		1000	/* decrementer freq: 1ms ticks */
 
 /*
  * For booting Linux, the board info and command line data
@@ -731,7 +729,6 @@ boards, we say we have two, but don't display a message if we find only one. */
 
 #if defined(CONFIG_CMD_KGDB)
 #define CONFIG_KGDB_BAUDRATE	230400	/* speed of kgdb serial port */
-#define CONFIG_KGDB_SER_INDEX	2	/* which serial port to use */
 #endif
 
 
diff --git a/include/configs/MPC8360EMDS.h b/include/configs/MPC8360EMDS.h
index 7c4f3ef8f1..aefde74fc5 100644
--- a/include/configs/MPC8360EMDS.h
+++ b/include/configs/MPC8360EMDS.h
@@ -14,7 +14,6 @@
  */
 #define CONFIG_E300		1 /* E300 family */
 #define CONFIG_QE		1 /* Has QE */
-#define CONFIG_MPC83xx		1 /* MPC83xx family */
 #define CONFIG_MPC8360		1 /* MPC8360 CPU specific */
 #define CONFIG_MPC8360EMDS	1 /* MPC8360EMDS board specific */
 
@@ -544,7 +543,6 @@
  */
 #define CONFIG_SYS_LONGHELP		/* undef to save memory */
 #define CONFIG_SYS_LOAD_ADDR		0x2000000 /* default load address */
-#define CONFIG_SYS_PROMPT		"=> "	/* Monitor Command Prompt */
 
 #if defined(CONFIG_CMD_KGDB)
 	#define CONFIG_SYS_CBSIZE	1024 /* Console I/O Buffer Size */
@@ -557,7 +555,6 @@
 #define CONFIG_SYS_MAXARGS	16	/* max number of command args */
 				/* Boot Argument Buffer Size */
 #define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE
-#define CONFIG_SYS_HZ		1000	/* decrementer freq: 1ms ticks */
 
 /*
  * For booting Linux, the board info and command line data
@@ -685,7 +682,6 @@
 
 #if defined(CONFIG_CMD_KGDB)
 #define CONFIG_KGDB_BAUDRATE	230400	/* speed of kgdb serial port */
-#define CONFIG_KGDB_SER_INDEX	2	/* which serial port to use */
 #endif
 
 /*
diff --git a/include/configs/MPC8360ERDK.h b/include/configs/MPC8360ERDK.h
index 1973447a23..1b8bad179b 100644
--- a/include/configs/MPC8360ERDK.h
+++ b/include/configs/MPC8360ERDK.h
@@ -19,7 +19,6 @@
  */
 #define CONFIG_E300		1 /* E300 family */
 #define CONFIG_QE		1 /* Has QE */
-#define CONFIG_MPC83xx		1 /* MPC83xx family */
 #define CONFIG_MPC8360		1 /* MPC8360 CPU specific */
 #define CONFIG_MPC8360ERDK	1 /* MPC8360ERDK board specific */
 
@@ -405,7 +404,6 @@
  */
 #define CONFIG_SYS_LONGHELP		/* undef to save memory */
 #define CONFIG_SYS_LOAD_ADDR		0x2000000 /* default load address */
-#define CONFIG_SYS_PROMPT		"=> "	/* Monitor Command Prompt */
 
 #if defined(CONFIG_CMD_KGDB)
 	#define CONFIG_SYS_CBSIZE	1024 /* Console I/O Buffer Size */
@@ -418,7 +416,6 @@
 #define CONFIG_SYS_MAXARGS	16	/* max number of command args */
 				/* Boot Argument Buffer Size */
 #define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE
-#define CONFIG_SYS_HZ		1000	/* decrementer freq: 1ms ticks */
 
 /*
  * For booting Linux, the board info and command line data
@@ -546,7 +543,6 @@
 
 #if defined(CONFIG_CMD_KGDB)
 #define CONFIG_KGDB_BAUDRATE	230400	/* speed of kgdb serial port */
-#define CONFIG_KGDB_SER_INDEX	2	/* which serial port to use */
 #endif
 
 /*
diff --git a/include/configs/MPC837XEMDS.h b/include/configs/MPC837XEMDS.h
index 51688a76bf..695e47bf07 100644
--- a/include/configs/MPC837XEMDS.h
+++ b/include/configs/MPC837XEMDS.h
@@ -12,7 +12,6 @@
  * High Level Configuration Options
  */
 #define CONFIG_E300		1 /* E300 family */
-#define CONFIG_MPC83xx		1 /* MPC83xx family */
 #define CONFIG_MPC837x		1 /* MPC837x CPU specific */
 #define CONFIG_MPC837XEMDS	1 /* MPC837XEMDS board specific */
 
@@ -523,7 +522,6 @@ extern int board_pci_host_broken(void);
  */
 #define CONFIG_SYS_LONGHELP		/* undef to save memory */
 #define CONFIG_SYS_LOAD_ADDR		0x2000000 /* default load address */
-#define CONFIG_SYS_PROMPT		"=> "	/* Monitor Command Prompt */
 
 #if defined(CONFIG_CMD_KGDB)
 	#define CONFIG_SYS_CBSIZE	1024 /* Console I/O Buffer Size */
@@ -536,7 +534,6 @@ extern int board_pci_host_broken(void);
 #define CONFIG_SYS_MAXARGS	16	/* max number of command args */
 				/* Boot Argument Buffer Size */
 #define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE
-#define CONFIG_SYS_HZ		1000	/* decrementer freq: 1ms ticks */
 
 /*
  * For booting Linux, the board info and command line data
@@ -664,7 +661,6 @@ extern int board_pci_host_broken(void);
 
 #if defined(CONFIG_CMD_KGDB)
 #define CONFIG_KGDB_BAUDRATE	230400	/* speed of kgdb serial port */
-#define CONFIG_KGDB_SER_INDEX	2	/* which serial port to use */
 #endif
 
 /*
diff --git a/include/configs/MPC837XERDB.h b/include/configs/MPC837XERDB.h
index a5fe220b14..1d1f4c0e22 100644
--- a/include/configs/MPC837XERDB.h
+++ b/include/configs/MPC837XERDB.h
@@ -13,7 +13,6 @@
  * High Level Configuration Options
  */
 #define CONFIG_E300		1 /* E300 family */
-#define CONFIG_MPC83xx		1 /* MPC83xx family */
 #define CONFIG_MPC837x		1 /* MPC837x CPU specific */
 #define CONFIG_MPC837XERDB	1
 
@@ -538,7 +537,6 @@
  */
 #define CONFIG_SYS_LONGHELP	/* undef to save memory */
 #define CONFIG_SYS_LOAD_ADDR	0x2000000 /* default load address */
-#define CONFIG_SYS_PROMPT	"=> "	/* Monitor Command Prompt */
 
 #if defined(CONFIG_CMD_KGDB)
 	#define CONFIG_SYS_CBSIZE	1024 /* Console I/O Buffer Size */
@@ -551,7 +549,6 @@
 #define CONFIG_SYS_MAXARGS	16	/* max number of command args */
 				/* Boot Argument Buffer Size */
 #define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE
-#define CONFIG_SYS_HZ		1000	/* decrementer freq: 1ms ticks */
 
 /*
  * For booting Linux, the board info and command line data
@@ -680,7 +677,6 @@
 
 #if defined(CONFIG_CMD_KGDB)
 #define CONFIG_KGDB_BAUDRATE	230400	/* speed of kgdb serial port */
-#define CONFIG_KGDB_SER_INDEX	2	/* which serial port to use */
 #endif
 
 /*
diff --git a/include/configs/MPC8536DS.h b/include/configs/MPC8536DS.h
index 8ff2c3a4fa..faa5495cb4 100644
--- a/include/configs/MPC8536DS.h
+++ b/include/configs/MPC8536DS.h
@@ -24,7 +24,7 @@
 #define CONFIG_SYS_TEXT_BASE_SPL 0xfff00000
 #define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE_SPL /* start of monitor */
 #else
-#define CONFIG_SYS_LDSCRIPT $(TOPDIR)/$(CPUDIR)/u-boot-nand.lds
+#define CONFIG_SYS_LDSCRIPT $(CPUDIR)/u-boot-nand.lds
 #define CONFIG_SYS_TEXT_BASE	0xf8f82000
 #endif /* CONFIG_NAND_SPL */
 #endif
@@ -42,7 +42,7 @@
 #endif
 
 #ifndef CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_TEXT_BASE	0xeff80000
+#define CONFIG_SYS_TEXT_BASE	0xeff40000
 #endif
 
 #ifndef	CONFIG_RESET_VECTOR_ADDRESS
@@ -56,7 +56,6 @@
 /* High Level Configuration Options */
 #define CONFIG_BOOKE		1	/* BOOKE */
 #define CONFIG_E500		1	/* BOOKE e500 family */
-#define CONFIG_MPC85xx		1	/* MPC8540/60/55/41/48 */
 #define CONFIG_MPC8536		1
 #define CONFIG_MPC8536DS	1
 
@@ -122,7 +121,7 @@
 
 /* DDR Setup */
 #define CONFIG_VERY_BIG_RAM
-#define CONFIG_FSL_DDR2
+#define CONFIG_SYS_FSL_DDR2
 #undef CONFIG_FSL_DDR_INTERACTIVE
 #define CONFIG_SPD_EEPROM		/* Use SPD EEPROM for DDR setup */
 #define CONFIG_DDR_SPD
@@ -327,7 +326,7 @@
 
 /* NAND boot: 4K NAND loader config */
 #define CONFIG_SYS_NAND_SPL_SIZE	0x1000
-#define CONFIG_SYS_NAND_U_BOOT_SIZE	((512 << 10) - 0x2000)
+#define CONFIG_SYS_NAND_U_BOOT_SIZE	((768 << 10) - 0x2000)
 #define CONFIG_SYS_NAND_U_BOOT_DST	(CONFIG_SYS_INIT_L2_ADDR)
 #define CONFIG_SYS_NAND_U_BOOT_START \
 		(CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_NAND_SPL_SIZE)
@@ -627,7 +626,7 @@
 #if defined(CONFIG_RAMBOOT_NAND)
 #define CONFIG_ENV_IS_IN_NAND	1
 #define CONFIG_ENV_SIZE		CONFIG_SYS_NAND_BLOCK_SIZE
-#define CONFIG_ENV_OFFSET ((512 * 1024) + CONFIG_SYS_NAND_BLOCK_SIZE)
+#define CONFIG_ENV_OFFSET ((768 * 1024) + CONFIG_SYS_NAND_BLOCK_SIZE)
 #define CONFIG_ENV_RANGE	(3 * CONFIG_ENV_SIZE)
 #elif defined(CONFIG_RAMBOOT_SPIFLASH)
 #define CONFIG_ENV_IS_IN_SPI_FLASH
@@ -650,11 +649,7 @@
 #endif
 #else
 	#define CONFIG_ENV_IS_IN_FLASH	1
-	#if CONFIG_SYS_MONITOR_BASE > 0xfff80000
-	#define CONFIG_ENV_ADDR		0xfff80000
-	#else
 	#define CONFIG_ENV_ADDR	(CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
-	#endif
 	#define CONFIG_ENV_SIZE		0x2000
 	#define CONFIG_ENV_SECT_SIZE	0x20000 /* 128K (one sector) */
 #endif
@@ -720,7 +715,6 @@
 #define CONFIG_CMDLINE_EDITING			/* Command-line editing */
 #define CONFIG_AUTO_COMPLETE			/* add autocompletion support */
 #define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
-#define CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt */
 #if defined(CONFIG_CMD_KGDB)
 #define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size */
 #else
@@ -730,7 +724,6 @@
 		+ sizeof(CONFIG_SYS_PROMPT) + 16) /* Print Buffer Size */
 #define CONFIG_SYS_MAXARGS	16		/* max number of command args */
 #define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-#define CONFIG_SYS_HZ		1000		/* decrementer freq: 1ms ticks */
 
 /*
  * For booting Linux, the board info and command line data
@@ -742,7 +735,6 @@
 
 #if defined(CONFIG_CMD_KGDB)
 #define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
-#define CONFIG_KGDB_SER_INDEX	2	/* which serial port to use */
 #endif
 
 /*
diff --git a/include/configs/MPC8540ADS.h b/include/configs/MPC8540ADS.h
index e7ded0127d..37c2b9415a 100644
--- a/include/configs/MPC8540ADS.h
+++ b/include/configs/MPC8540ADS.h
@@ -21,7 +21,6 @@
 /* High Level Configuration Options */
 #define CONFIG_BOOKE		1	/* BOOKE */
 #define CONFIG_E500		1	/* BOOKE e500 family */
-#define CONFIG_MPC85xx		1	/* MPC8540/MPC8560 */
 #define CONFIG_MPC8540		1	/* MPC8540 specific */
 #define CONFIG_MPC8540ADS	1	/* MPC8540ADS board specific */
 
@@ -78,7 +77,7 @@
 #define CONFIG_SYS_CCSRBAR_PHYS_LOW	CONFIG_SYS_CCSRBAR
 
 /* DDR Setup */
-#define CONFIG_FSL_DDR1
+#define CONFIG_SYS_FSL_DDR1
 #define CONFIG_SPD_EEPROM		/* Use SPD EEPROM for DDR setup*/
 #define CONFIG_DDR_SPD
 #undef CONFIG_FSL_DDR_INTERACTIVE
@@ -376,7 +375,6 @@
 #define CONFIG_CMDLINE_EDITING			/* Command-line editing */
 #define CONFIG_AUTO_COMPLETE			/* add autocompletion support */
 #define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
-#define CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt */
 
 #if defined(CONFIG_CMD_KGDB)
     #define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size */
@@ -387,7 +385,6 @@
 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
 #define CONFIG_SYS_MAXARGS	16		/* max number of command args */
 #define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size */
-#define CONFIG_SYS_HZ		1000		/* decrementer freq: 1ms ticks */
 
 /*
  * For booting Linux, the board info and command line data
@@ -399,7 +396,6 @@
 
 #if defined(CONFIG_CMD_KGDB)
 #define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
-#define CONFIG_KGDB_SER_INDEX	2	/* which serial port to use */
 #endif
 
 
diff --git a/include/configs/MPC8541CDS.h b/include/configs/MPC8541CDS.h
index 150e56ea38..5d229a0d20 100644
--- a/include/configs/MPC8541CDS.h
+++ b/include/configs/MPC8541CDS.h
@@ -16,7 +16,6 @@
 /* High Level Configuration Options */
 #define CONFIG_BOOKE		1	/* BOOKE */
 #define CONFIG_E500		1	/* BOOKE e500 family */
-#define CONFIG_MPC85xx		1	/* MPC8540/60/55/41 */
 #define CONFIG_CPM2		1	/* has CPM2 */
 #define CONFIG_MPC8541		1	/* MPC8541 specific */
 #define CONFIG_MPC8541CDS	1	/* MPC8541CDS board specific */
@@ -51,7 +50,7 @@ extern unsigned long get_clock_freq(void);
 #define CONFIG_SYS_CCSRBAR_PHYS_LOW	CONFIG_SYS_CCSRBAR
 
 /* DDR Setup */
-#define CONFIG_FSL_DDR1
+#define CONFIG_SYS_FSL_DDR1
 #define CONFIG_SPD_EEPROM		/* Use SPD EEPROM for DDR setup*/
 #define CONFIG_DDR_SPD
 #undef CONFIG_FSL_DDR_INTERACTIVE
@@ -391,7 +390,6 @@ extern unsigned long get_clock_freq(void);
 #define CONFIG_CMDLINE_EDITING			/* Command-line editing */
 #define CONFIG_AUTO_COMPLETE			/* add autocompletion support */
 #define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
-#define CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt */
 #if defined(CONFIG_CMD_KGDB)
 #define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size */
 #else
@@ -400,7 +398,6 @@ extern unsigned long get_clock_freq(void);
 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
 #define CONFIG_SYS_MAXARGS	16		/* max number of command args */
 #define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size */
-#define CONFIG_SYS_HZ		1000		/* decrementer freq: 1ms ticks */
 
 /*
  * For booting Linux, the board info and command line data
@@ -412,7 +409,6 @@ extern unsigned long get_clock_freq(void);
 
 #if defined(CONFIG_CMD_KGDB)
 #define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
-#define CONFIG_KGDB_SER_INDEX	2	/* which serial port to use */
 #endif
 
 /*
diff --git a/include/configs/MPC8544DS.h b/include/configs/MPC8544DS.h
index 7f1628592f..dade6d3b89 100644
--- a/include/configs/MPC8544DS.h
+++ b/include/configs/MPC8544DS.h
@@ -14,7 +14,6 @@
 /* High Level Configuration Options */
 #define CONFIG_BOOKE		1	/* BOOKE */
 #define CONFIG_E500		1	/* BOOKE e500 family */
-#define CONFIG_MPC85xx		1	/* MPC8540/60/55/41/48 */
 #define CONFIG_MPC8544		1
 #define CONFIG_MPC8544DS	1
 
@@ -63,7 +62,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
 #define CONFIG_SYS_CCSRBAR_PHYS_LOW	CONFIG_SYS_CCSRBAR
 
 /* DDR Setup */
-#define CONFIG_FSL_DDR2
+#define CONFIG_SYS_FSL_DDR2
 #undef CONFIG_FSL_DDR_INTERACTIVE
 #define CONFIG_SPD_EEPROM		/* Use SPD EEPROM for DDR setup */
 #define CONFIG_DDR_SPD
@@ -422,7 +421,6 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
 #define CONFIG_CMDLINE_EDITING			/* Command-line editing */
 #define CONFIG_AUTO_COMPLETE			/* add autocompletion support */
 #define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
-#define CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt */
 #if defined(CONFIG_CMD_KGDB)
 #define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size */
 #else
@@ -431,7 +429,6 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
 #define CONFIG_SYS_MAXARGS	16		/* max number of command args */
 #define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size */
-#define CONFIG_SYS_HZ		1000		/* decrementer freq: 1ms ticks */
 
 /*
  * For booting Linux, the board info and command line data
@@ -443,7 +440,6 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
 
 #if defined(CONFIG_CMD_KGDB)
 #define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
-#define CONFIG_KGDB_SER_INDEX	2	/* which serial port to use */
 #endif
 
 /*
diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h
index 8deb241c39..190c668303 100644
--- a/include/configs/MPC8548CDS.h
+++ b/include/configs/MPC8548CDS.h
@@ -20,7 +20,6 @@
 /* High Level Configuration Options */
 #define CONFIG_BOOKE		1	/* BOOKE */
 #define CONFIG_E500		1	/* BOOKE e500 family */
-#define CONFIG_MPC85xx		1	/* MPC8540/60/55/41/48 */
 #define CONFIG_MPC8548		1	/* MPC8548 specific */
 #define CONFIG_MPC8548CDS	1	/* MPC8548CDS board specific */
 
@@ -75,7 +74,7 @@ extern unsigned long get_clock_freq(void);
 #define CONFIG_SYS_CCSRBAR_PHYS_LOW	CONFIG_SYS_CCSRBAR
 
 /* DDR Setup */
-#define CONFIG_FSL_DDR2
+#define CONFIG_SYS_FSL_DDR2
 #undef CONFIG_FSL_DDR_INTERACTIVE
 #define CONFIG_SPD_EEPROM		/* Use SPD EEPROM for DDR setup*/
 #define CONFIG_DDR_SPD
@@ -516,7 +515,6 @@ extern unsigned long get_clock_freq(void);
 #define CONFIG_CMDLINE_EDITING			/* Command-line editing */
 #define CONFIG_AUTO_COMPLETE			/* add autocompletion support */
 #define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
-#define CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt */
 #if defined(CONFIG_CMD_KGDB)
 #define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size */
 #else
@@ -525,7 +523,6 @@ extern unsigned long get_clock_freq(void);
 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
 #define CONFIG_SYS_MAXARGS	16		/* max number of command args */
 #define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size */
-#define CONFIG_SYS_HZ		1000		/* decrementer freq: 1ms ticks */
 
 /*
  * For booting Linux, the board info and command line data
@@ -537,7 +534,6 @@ extern unsigned long get_clock_freq(void);
 
 #if defined(CONFIG_CMD_KGDB)
 #define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
-#define CONFIG_KGDB_SER_INDEX	2	/* which serial port to use */
 #endif
 
 /*
diff --git a/include/configs/MPC8555CDS.h b/include/configs/MPC8555CDS.h
index 285872ef3a..5263ffcc8d 100644
--- a/include/configs/MPC8555CDS.h
+++ b/include/configs/MPC8555CDS.h
@@ -16,7 +16,6 @@
 /* High Level Configuration Options */
 #define CONFIG_BOOKE		1	/* BOOKE */
 #define CONFIG_E500		1	/* BOOKE e500 family */
-#define CONFIG_MPC85xx		1	/* MPC8540/60/55/41 */
 #define CONFIG_CPM2		1	/* has CPM2 */
 #define CONFIG_MPC8555		1	/* MPC8555 specific */
 #define CONFIG_MPC8555CDS	1	/* MPC8555CDS board specific */
@@ -51,7 +50,7 @@ extern unsigned long get_clock_freq(void);
 #define CONFIG_SYS_CCSRBAR_PHYS_LOW	CONFIG_SYS_CCSRBAR
 
 /* DDR Setup */
-#define CONFIG_FSL_DDR1
+#define CONFIG_SYS_FSL_DDR1
 #define CONFIG_SPD_EEPROM		/* Use SPD EEPROM for DDR setup*/
 #define CONFIG_DDR_SPD
 #undef CONFIG_FSL_DDR_INTERACTIVE
@@ -389,7 +388,6 @@ extern unsigned long get_clock_freq(void);
 #define CONFIG_CMDLINE_EDITING			/* Command-line editing */
 #define CONFIG_AUTO_COMPLETE			/* add autocompletion support */
 #define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
-#define CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt */
 #if defined(CONFIG_CMD_KGDB)
 #define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size */
 #else
@@ -398,7 +396,6 @@ extern unsigned long get_clock_freq(void);
 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
 #define CONFIG_SYS_MAXARGS	16		/* max number of command args */
 #define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size */
-#define CONFIG_SYS_HZ		1000		/* decrementer freq: 1ms ticks */
 
 /*
  * For booting Linux, the board info and command line data
@@ -410,7 +407,6 @@ extern unsigned long get_clock_freq(void);
 
 #if defined(CONFIG_CMD_KGDB)
 #define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
-#define CONFIG_KGDB_SER_INDEX	2	/* which serial port to use */
 #endif
 
 /*
diff --git a/include/configs/MPC8560ADS.h b/include/configs/MPC8560ADS.h
index 24102ee8ab..ac78d481d6 100644
--- a/include/configs/MPC8560ADS.h
+++ b/include/configs/MPC8560ADS.h
@@ -21,7 +21,6 @@
 /* High Level Configuration Options */
 #define CONFIG_BOOKE		1	/* BOOKE */
 #define CONFIG_E500		1	/* BOOKE e500 family */
-#define CONFIG_MPC85xx		1	/* MPC8540/MPC8560 */
 #define CONFIG_CPM2		1	/* has CPM2 */
 #define CONFIG_MPC8560ADS	1	/* MPC8560ADS board specific */
 #define CONFIG_MPC8560		1
@@ -75,7 +74,7 @@
 #define CONFIG_SYS_CCSRBAR_PHYS_LOW	CONFIG_SYS_CCSRBAR
 
 /* DDR Setup */
-#define CONFIG_FSL_DDR1
+#define CONFIG_SYS_FSL_DDR1
 #define CONFIG_SPD_EEPROM		/* Use SPD EEPROM for DDR setup*/
 #define CONFIG_DDR_SPD
 #undef CONFIG_FSL_DDR_INTERACTIVE
@@ -417,7 +416,6 @@
 #define CONFIG_CMDLINE_EDITING			/* Command-line editing */
 #define CONFIG_AUTO_COMPLETE			/* add autocompletion support */
 #define CONFIG_SYS_LOAD_ADDR	0x1000000	/* default load address */
-#define CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt */
 
 #if defined(CONFIG_CMD_KGDB)
     #define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size */
@@ -428,7 +426,6 @@
 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
 #define CONFIG_SYS_MAXARGS	16		/* max number of command args */
 #define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size */
-#define CONFIG_SYS_HZ		1000		/* decrementer freq: 1ms ticks */
 
 /*
  * For booting Linux, the board info and command line data
@@ -440,7 +437,6 @@
 
 #if defined(CONFIG_CMD_KGDB)
 #define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
-#define CONFIG_KGDB_SER_INDEX	2	/* which serial port to use */
 #endif
 
 
diff --git a/include/configs/MPC8568MDS.h b/include/configs/MPC8568MDS.h
index 90b99b3b5e..02a5acf38e 100644
--- a/include/configs/MPC8568MDS.h
+++ b/include/configs/MPC8568MDS.h
@@ -13,7 +13,6 @@
 /* High Level Configuration Options */
 #define CONFIG_BOOKE		1	/* BOOKE */
 #define CONFIG_E500		1	/* BOOKE e500 family */
-#define CONFIG_MPC85xx		1	/* MPC8540/60/55/41/48/68 */
 #define CONFIG_MPC8568		1	/* MPC8568 specific */
 #define CONFIG_MPC8568MDS	1	/* MPC8568MDS board specific */
 
@@ -60,7 +59,7 @@ extern unsigned long get_clock_freq(void);
 #define CONFIG_SYS_CCSRBAR_PHYS_LOW	CONFIG_SYS_CCSRBAR
 
 /* DDR Setup */
-#define CONFIG_FSL_DDR2
+#define CONFIG_SYS_FSL_DDR2
 #undef CONFIG_FSL_DDR_INTERACTIVE
 #define CONFIG_SPD_EEPROM		/* Use SPD EEPROM for DDR setup*/
 #define CONFIG_DDR_SPD
@@ -411,7 +410,6 @@ extern unsigned long get_clock_freq(void);
 #define CONFIG_CMDLINE_EDITING			/* Command-line editing */
 #define CONFIG_AUTO_COMPLETE			/* add autocompletion support */
 #define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
-#define CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt */
 #if defined(CONFIG_CMD_KGDB)
 #define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size */
 #else
@@ -420,7 +418,6 @@ extern unsigned long get_clock_freq(void);
 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
 #define CONFIG_SYS_MAXARGS	16		/* max number of command args */
 #define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size */
-#define CONFIG_SYS_HZ		1000		/* decrementer freq: 1ms ticks */
 
 /*
  * For booting Linux, the board info and command line data
@@ -432,7 +429,6 @@ extern unsigned long get_clock_freq(void);
 
 #if defined(CONFIG_CMD_KGDB)
 #define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
-#define CONFIG_KGDB_SER_INDEX	2	/* which serial port to use */
 #endif
 
 /*
diff --git a/include/configs/MPC8569MDS.h b/include/configs/MPC8569MDS.h
index 3bf01b2c12..58b9c26e93 100644
--- a/include/configs/MPC8569MDS.h
+++ b/include/configs/MPC8569MDS.h
@@ -13,7 +13,6 @@
 /* High Level Configuration Options */
 #define CONFIG_BOOKE		1	/* BOOKE */
 #define CONFIG_E500		1	/* BOOKE e500 family */
-#define CONFIG_MPC85xx		1	/* MPC8540/60/55/41/48/68 */
 #define CONFIG_MPC8569		1	/* MPC8569 specific */
 #define CONFIG_MPC8569MDS	1	/* MPC8569MDS board specific */
 
@@ -57,7 +56,7 @@ extern unsigned long get_clock_freq(void);
 #define CONFIG_SYS_TEXT_BASE_SPL 0xfff00000
 #define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE_SPL /* start of monitor */
 #else
-#define CONFIG_SYS_LDSCRIPT $(TOPDIR)/$(CPUDIR)/u-boot-nand.lds
+#define CONFIG_SYS_LDSCRIPT $(CPUDIR)/u-boot-nand.lds
 #define CONFIG_SYS_TEXT_BASE	0xf8f82000
 #endif
 #endif
@@ -98,7 +97,7 @@ extern unsigned long get_clock_freq(void);
 #endif
 
 /* DDR Setup */
-#define CONFIG_FSL_DDR3
+#define CONFIG_SYS_FSL_DDR3
 #undef CONFIG_FSL_DDR_INTERACTIVE
 #define CONFIG_SPD_EEPROM		/* Use SPD EEPROM for DDR setup*/
 #define CONFIG_DDR_SPD
@@ -545,7 +544,6 @@ extern unsigned long get_clock_freq(void);
 #define CONFIG_CMDLINE_EDITING			/* Command-line editing */
 #define CONFIG_AUTO_COMPLETE			/* add autocompletion support */
 #define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
-#define CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt */
 #if defined(CONFIG_CMD_KGDB)
 #define CONFIG_SYS_CBSIZE	2048		/* Console I/O Buffer Size */
 #else
@@ -556,7 +554,6 @@ extern unsigned long get_clock_freq(void);
 #define CONFIG_SYS_MAXARGS	32		/* max number of command args */
 #define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE
 						/* Boot Argument Buffer Size */
-#define CONFIG_SYS_HZ	1000		/* decrementer freq: 1ms ticks */
 
 /*
  * For booting Linux, the board info and command line data
@@ -568,7 +565,6 @@ extern unsigned long get_clock_freq(void);
 
 #if defined(CONFIG_CMD_KGDB)
 #define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
-#define CONFIG_KGDB_SER_INDEX	2	/* which serial port to use */
 #endif
 
 /*
diff --git a/include/configs/MPC8572DS.h b/include/configs/MPC8572DS.h
index acd39816be..7b63945888 100644
--- a/include/configs/MPC8572DS.h
+++ b/include/configs/MPC8572DS.h
@@ -24,7 +24,7 @@
 #define CONFIG_SYS_TEXT_BASE_SPL 0xfff00000
 #define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE_SPL /* start of monitor */
 #else
-#define CONFIG_SYS_LDSCRIPT $(TOPDIR)/$(CPUDIR)/u-boot-nand.lds
+#define CONFIG_SYS_LDSCRIPT $(CPUDIR)/u-boot-nand.lds
 #define CONFIG_SYS_TEXT_BASE	0xf8f82000
 #endif /* CONFIG_NAND_SPL */
 #endif
@@ -44,7 +44,6 @@
 /* High Level Configuration Options */
 #define CONFIG_BOOKE		1	/* BOOKE */
 #define CONFIG_E500		1	/* BOOKE e500 family */
-#define CONFIG_MPC85xx		1	/* MPC8540/60/55/41/48 */
 #define CONFIG_MPC8572		1
 #define CONFIG_MPC8572DS	1
 #define CONFIG_MP		1	/* support multiple processors */
@@ -106,7 +105,7 @@
 
 /* DDR Setup */
 #define CONFIG_VERY_BIG_RAM
-#define CONFIG_FSL_DDR2
+#define CONFIG_SYS_FSL_DDR2
 #undef CONFIG_FSL_DDR_INTERACTIVE
 #define CONFIG_SPD_EEPROM		/* Use SPD EEPROM for DDR setup */
 #define CONFIG_DDR_SPD
@@ -322,6 +321,8 @@
 #define CONFIG_CMD_NAND		1
 #define CONFIG_NAND_FSL_ELBC	1
 #define CONFIG_SYS_NAND_BLOCK_SIZE    (128 * 1024)
+#define CONFIG_SYS_NAND_MAX_OOBFREE	5
+#define CONFIG_SYS_NAND_MAX_ECCPOS	56
 
 /* NAND boot: 4K NAND loader config */
 #define CONFIG_SYS_NAND_SPL_SIZE	0x1000
@@ -661,7 +662,6 @@
 #define CONFIG_CMDLINE_EDITING			/* Command-line editing */
 #define CONFIG_AUTO_COMPLETE			/* add autocompletion support */
 #define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
-#define CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt */
 #if defined(CONFIG_CMD_KGDB)
 #define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size */
 #else
@@ -670,7 +670,6 @@
 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
 #define CONFIG_SYS_MAXARGS	16		/* max number of command args */
 #define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size */
-#define CONFIG_SYS_HZ		1000		/* decrementer freq: 1ms ticks */
 
 /*
  * For booting Linux, the board info and command line data
@@ -682,7 +681,6 @@
 
 #if defined(CONFIG_CMD_KGDB)
 #define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
-#define CONFIG_KGDB_SER_INDEX	2	/* which serial port to use */
 #endif
 
 /*
diff --git a/include/configs/MPC8610HPCD.h b/include/configs/MPC8610HPCD.h
index 0b2cf87016..e6d570a6af 100644
--- a/include/configs/MPC8610HPCD.h
+++ b/include/configs/MPC8610HPCD.h
@@ -14,7 +14,6 @@
 #define __CONFIG_H
 
 /* High Level Configuration Options */
-#define CONFIG_MPC86xx		1	/* MPC86xx */
 #define CONFIG_MPC8610		1	/* MPC8610 specific */
 #define CONFIG_MPC8610HPCD	1	/* MPC8610HPCD board specific */
 #define CONFIG_LINUX_RESET_VEC	0x100	/* Reset vector used by Linux */
@@ -92,7 +91,7 @@
 #define CONFIG_SYS_CCSRBAR_PHYS		CONFIG_SYS_CCSRBAR_PHYS_LOW
 
 /* DDR Setup */
-#define CONFIG_FSL_DDR2
+#define CONFIG_SYS_FSL_DDR2
 #undef CONFIG_FSL_DDR_INTERACTIVE
 #define CONFIG_SPD_EEPROM		/* Use SPD for DDR */
 #define CONFIG_DDR_SPD
@@ -497,7 +496,6 @@
 #define CONFIG_SYS_LONGHELP			/* undef to save memory	*/
 #define CONFIG_CMDLINE_EDITING          /* Command-line editing */
 #define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
-#define CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt */
 
 #if defined(CONFIG_CMD_KGDB)
 #define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size */
@@ -508,7 +506,6 @@
 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
 #define CONFIG_SYS_MAXARGS	16		/* max number of command args */
 #define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size */
-#define CONFIG_SYS_HZ		1000		/* decrementer freq: 1ms ticks */
 
 /*
  * For booting Linux, the board info and command line data
@@ -519,7 +516,6 @@
 
 #if defined(CONFIG_CMD_KGDB)
 #define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
-#define CONFIG_KGDB_SER_INDEX	2	/* which serial port to use */
 #endif
 
 /*
diff --git a/include/configs/MPC8641HPCN.h b/include/configs/MPC8641HPCN.h
index e438b8ef38..7443acec80 100644
--- a/include/configs/MPC8641HPCN.h
+++ b/include/configs/MPC8641HPCN.h
@@ -17,7 +17,6 @@
 #define __CONFIG_H
 
 /* High Level Configuration Options */
-#define CONFIG_MPC86xx		1	/* MPC86xx */
 #define CONFIG_MPC8641		1	/* MPC8641 specific */
 #define CONFIG_MPC8641HPCN	1	/* MPC8641HPCN board specific */
 #define CONFIG_MP		1	/* support multiple processors */
@@ -108,7 +107,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
 /*
  * DDR Setup
  */
-#define CONFIG_FSL_DDR2
+#define CONFIG_SYS_FSL_DDR2
 #undef CONFIG_FSL_DDR_INTERACTIVE
 #define CONFIG_SPD_EEPROM		/* Use SPD EEPROM for DDR setup */
 #define CONFIG_DDR_SPD
@@ -650,7 +649,6 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
 #define CONFIG_SYS_LONGHELP			/* undef to save memory	*/
 #define CONFIG_CMDLINE_EDITING		/* Command-line editing */
 #define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
-#define CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt */
 
 #if defined(CONFIG_CMD_KGDB)
     #define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size */
@@ -661,7 +659,6 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
 #define CONFIG_SYS_MAXARGS	16		/* max number of command args */
 #define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size */
-#define CONFIG_SYS_HZ		1000		/* decrementer freq: 1ms ticks */
 
 /*
  * For booting Linux, the board info and command line data
@@ -672,7 +669,6 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
 
 #if defined(CONFIG_CMD_KGDB)
     #define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
-    #define CONFIG_KGDB_SER_INDEX	2	/* which serial port to use */
 #endif
 
 /*
diff --git a/include/configs/MUSENKI.h b/include/configs/MUSENKI.h
index caf6164a30..c5c929002d 100644
--- a/include/configs/MUSENKI.h
+++ b/include/configs/MUSENKI.h
@@ -25,7 +25,6 @@
  * (easy to change)
  */
 
-#define CONFIG_MPC824X		1
 #define CONFIG_MPC8245		1
 #define CONFIG_MUSENKI		1
 
@@ -56,7 +55,6 @@
  * Miscellaneous configurable options
  */
 #undef CONFIG_SYS_LONGHELP			/* undef to save memory		*/
-#define CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt	*/
 #define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
 
 /* Print Buffer Size
@@ -151,7 +149,6 @@
  */
 
 #define CONFIG_SYS_CLK_FREQ  33333333	/* external frequency to pll */
-#define CONFIG_SYS_HZ		     1000
 
 	/* Bit-field values for MCCR1.
 	 */
diff --git a/include/configs/MVBC_P.h b/include/configs/MVBC_P.h
index c03ac6b9d0..036396c781 100644
--- a/include/configs/MVBC_P.h
+++ b/include/configs/MVBC_P.h
@@ -13,7 +13,6 @@
 
 #include <version.h>
 
-#define CONFIG_MPC5xxx	1
 #define CONFIG_MPC5200 	1
 
 #ifndef CONFIG_SYS_TEXT_BASE
@@ -105,6 +104,7 @@
 #define CONFIG_BOOTP_NTPSERVER
 #define CONFIG_BOOTP_RANDOM_DELAY
 #define CONFIG_BOOTP_SEND_HOSTNAME
+#define CONFIG_LIB_RAND
 
 /*
  * Autoboot
@@ -253,7 +253,6 @@
 #define CONFIG_SYS_HUSH_PARSER
 #define CONFIG_CMDLINE_EDITING
 #undef 	CONFIG_SYS_LONGHELP
-#define CONFIG_SYS_PROMPT		"=> "
 #ifdef CONFIG_CMD_KGDB
 #define CONFIG_SYS_CBSIZE		1024
 #else
@@ -266,8 +265,6 @@
 #define CONFIG_SYS_MEMTEST_START	0x00800000
 #define CONFIG_SYS_MEMTEST_END		0x02f00000
 
-#define CONFIG_SYS_HZ			1000
-
 /* default load address */
 #define CONFIG_SYS_LOAD_ADDR		0x02000000
 /* default location for tftp and bootm */
diff --git a/include/configs/MVBLM7.h b/include/configs/MVBLM7.h
index d24f6a4b4e..27c2fa011d 100644
--- a/include/configs/MVBLM7.h
+++ b/include/configs/MVBLM7.h
@@ -17,7 +17,6 @@
  * High Level Configuration Options
  */
 #define CONFIG_E300	1
-#define CONFIG_MPC83xx	1
 #define CONFIG_MPC834x	1
 #define CONFIG_MPC8343	1
 
@@ -228,6 +227,7 @@
 #define CONFIG_BOOTP_NTPSERVER
 #define CONFIG_BOOTP_RANDOM_DELAY
 #define CONFIG_BOOTP_SEND_HOSTNAME
+#define CONFIG_LIB_RAND
 
 /* USB */
 #define CONFIG_SYS_USB_HOST
@@ -292,7 +292,6 @@
 			(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
 #define CONFIG_SYS_MAXARGS	16
 #define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE
-#define CONFIG_SYS_HZ		1000
 
 /*
  * For booting Linux, the board info and command line data
diff --git a/include/configs/MVBLUE.h b/include/configs/MVBLUE.h
index db9502ade3..aa2d9c02de 100644
--- a/include/configs/MVBLUE.h
+++ b/include/configs/MVBLUE.h
@@ -40,7 +40,6 @@
 #define ERR_LED(code)
 #endif
 
-#define CONFIG_MPC824X		1
 #define CONFIG_MPC8245		1
 #define CONFIG_MVBLUE		1
 
@@ -103,7 +102,6 @@
  * Miscellaneous configurable options
  */
 #define CONFIG_SYS_LONGHELP			/* undef to save memory		*/
-#define CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt	*/
 #define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
 
 #define CONFIG_SYS_PBSIZE	(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
@@ -209,7 +207,6 @@
  */
 
 #define CONFIG_SYS_CLK_FREQ  33000000
-#define CONFIG_SYS_HZ			 10000
 
 /* Bit-field values for MCCR1.  */
 #define CONFIG_SYS_ROMNAL      7
diff --git a/include/configs/MVS1.h b/include/configs/MVS1.h
deleted file mode 100644
index 2ddca10af4..0000000000
--- a/include/configs/MVS1.h
+++ /dev/null
@@ -1,387 +0,0 @@
-/*
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-/*
- * board/config.h - configuration options, board specific
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_MPC823		1	/* This is a MPC823 CPU		*/
-#define CONFIG_MVS		1	/* ...on a MVsensor module	*/
-#define CONFIG_MVS_16BIT_FLASH		/* ...with 16-bit flash access	*/
-#define CONFIG_8xx_GCLK_FREQ	50000000/* ... and a 50 MHz CPU		*/
-
-#define	CONFIG_CLOCKS_IN_MHZ	1	/* clocks passsed to Linux in MHz */
-
-#undef	CONFIG_8xx_CONS_SMC1		/* Console is *NOT* on SMC1	*/
-#define	CONFIG_8xx_CONS_SMC2	1	/* Console is on SMC2		*/
-#undef	CONFIG_8xx_CONS_NONE
-#define CONFIG_BAUDRATE		115200	/* console baudrate		*/
-#define CONFIG_BOOTDELAY	5	/* autoboot after this many seconds	*/
-
-#define CONFIG_PREBOOT		"echo;" \
-				"echo To mount root over NFS use \"run bootnet\";" \
-				"echo To mount root from FLASH use  \"run bootflash\";" \
-				"echo"
-#define	CONFIG_BOOTARGS		"root=/dev/mtdblock2 rw"
-#define CONFIG_BOOTCOMMAND							\
-	"bootp; "								\
-	"setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} "	\
-	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; "	\
-	"bootm"
-
-#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
-#undef	CONFIG_SYS_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/
-
-#define	CONFIG_WATCHDOG			/* watchdog disabled/enabled	*/
-
-#undef	CONFIG_STATUS_LED		/* Status LED disabled/enabled	*/
-
-#undef	CONFIG_CAN_DRIVER		/* CAN Driver support disabled	*/
-
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_SUBNETMASK
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_VENDOREX
-
-#undef CONFIG_MAC_PARTITION
-#undef CONFIG_DOS_PARTITION
-
-#define	CONFIG_RTC_MPC8xx		/* use internal RTC of MPC8xx	*/
-
-
-/*
- * Command line configuration.
- */
-#define CONFIG_CMD_LOADS
-#define CONFIG_CMD_LOADB
-#define CONFIG_CMD_IMI
-#define CONFIG_CMD_FLASH
-#define CONFIG_CMD_MEMORY
-#define CONFIG_CMD_NET
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_SAVEENV
-#define CONFIG_CMD_BOOTD
-#define CONFIG_CMD_RUN
-
-
-/*
- * Miscellaneous configurable options
- */
-#undef	CONFIG_SYS_LONGHELP			/* undef to save memory		*/
-#define	CONFIG_SYS_PROMPT		"=> "	/* Monitor Command Prompt	*/
-
-#undef	CONFIG_SYS_HUSH_PARSER			/* Hush parse for U-Boot ?? */
-
-#if defined(CONFIG_CMD_KGDB)
-#define	CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
-#else
-#define	CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
-#endif
-#define	CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define	CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
-#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
-
-#define CONFIG_SYS_MEMTEST_START	0x0400000	/* memtest works on	*/
-#define CONFIG_SYS_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
-
-#define	CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address	*/
-
-#define	CONFIG_SYS_HZ		1000		/* decrementer freq: 1 ms ticks	*/
-
-/*
- * Low Level Configuration Settings
- * (address mappings, register initial values, etc.)
- * You should know what you are doing if you make changes here.
- */
-/*-----------------------------------------------------------------------
- * Internal Memory Mapped Register
- */
-#define CONFIG_SYS_IMMR		0xFFF00000
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area (in DPRAM)
- */
-#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
-#define	CONFIG_SYS_INIT_RAM_SIZE	0x2F00	/* Size of used area in DPRAM	*/
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define	CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
- */
-#define	CONFIG_SYS_SDRAM_BASE		0x00000000
-#define CONFIG_SYS_FLASH_BASE		0x40000000
-
-#define	CONFIG_SYS_MONITOR_LEN		(128 << 10)	/* Reserve 192 kB for Monitor	*/
-
-#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_FLASH_BASE
-#define	CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define	CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux	*/
-
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
-#define CONFIG_SYS_MAX_FLASH_SECT	71	/* max number of sectors on one chip (for AMD320DB chip)	*/
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
-#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
-
-#define	CONFIG_ENV_IS_IN_FLASH	1
-
-/* 4MB flash - use bottom sectors of a bottom boot sector flash (16 bit access) */
-#define	CONFIG_ENV_OFFSET		0x8000	/* Offset of Environment Sector	(bottom boot sector) */
-#define	CONFIG_ENV_SIZE		0x2000	/* Used Size of Environment Sector 8k	*/
-
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CONFIG_SYS_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
-#endif
-
-/*-----------------------------------------------------------------------
- * SYPCR - System Protection Control				11-9
- * SYPCR can only be written once after reset!
- *-----------------------------------------------------------------------
- * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
- */
-#if defined(CONFIG_WATCHDOG)
-#define CONFIG_SYS_SYPCR   (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
-	     SYPCR_SWE	| SYPCR_SWRI| SYPCR_SWP)
-#else
-#define CONFIG_SYS_SYPCR   (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
-#endif
-
-/*-----------------------------------------------------------------------
- * SIUMCR - SIU Module Configuration				11-6
- *-----------------------------------------------------------------------
- * PCMCIA config., multi-function pin tri-state
- */
-#define CONFIG_SYS_SIUMCR  (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
-
-/*-----------------------------------------------------------------------
- * TBSCR - Time Base Status and Control				11-26
- *-----------------------------------------------------------------------
- * Clear Reference Interrupt Status, Timebase freezing enabled
- */
-#define CONFIG_SYS_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
-
-/*-----------------------------------------------------------------------
- * RTCSC - Real-Time Clock Status and Control Register		11-27
- *-----------------------------------------------------------------------
- */
-#define CONFIG_SYS_RTCSC	(RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
-
-/*-----------------------------------------------------------------------
- * PISCR - Periodic Interrupt Status and Control		11-31
- *-----------------------------------------------------------------------
- * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
- */
-#define CONFIG_SYS_PISCR	(PISCR_PS | PISCR_PITF)
-
-/*-----------------------------------------------------------------------
- * PLPRCR - PLL, Low-Power, and Reset Control Register		15-30
- *-----------------------------------------------------------------------
- * Reset PLL lock status sticky bit, timer expired status bit and timer
- * interrupt status bit
- *
- */
-#define CONFIG_SYS_PLPRCR	(PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
-
-/*-----------------------------------------------------------------------
- * SCCR - System Clock and reset Control Register		15-27
- *-----------------------------------------------------------------------
- * Set clock output, timebase and RTC source and divider,
- * power management and some other internal clocks
- */
-#define SCCR_MASK	SCCR_EBDF11
-#define CONFIG_SYS_SCCR	(SCCR_TBS     | \
-			 SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
-			 SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
-			 SCCR_DFALCD00)
-
-/*-----------------------------------------------------------------------
- * PCMCIA stuff
- *-----------------------------------------------------------------------
- *
- */
-#define CONFIG_SYS_PCMCIA_MEM_ADDR	(0xE0000000)
-#define CONFIG_SYS_PCMCIA_MEM_SIZE	( 64 << 20 )
-#define CONFIG_SYS_PCMCIA_DMA_ADDR	(0xE4000000)
-#define CONFIG_SYS_PCMCIA_DMA_SIZE	( 64 << 20 )
-#define CONFIG_SYS_PCMCIA_ATTRB_ADDR	(0xE8000000)
-#define CONFIG_SYS_PCMCIA_ATTRB_SIZE	( 64 << 20 )
-#define CONFIG_SYS_PCMCIA_IO_ADDR	(0xEC000000)
-#define CONFIG_SYS_PCMCIA_IO_SIZE	( 64 << 20 )
-
-/*-----------------------------------------------------------------------
- * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
- *-----------------------------------------------------------------------
- */
-
-#define	CONFIG_IDE_PCCARD	0	/* **DON'T** Use IDE with PC Card Adapter	*/
-
-#undef	CONFIG_IDE_PCMCIA		/* Direct IDE	 not supported	*/
-#undef	CONFIG_IDE_LED			/* LED	 for ide not supported	*/
-#undef	CONFIG_IDE_RESET		/* reset for ide not supported	*/
-
-#define CONFIG_SYS_IDE_MAXBUS		0	/* max. no. of IDE buses			*/
-#define CONFIG_SYS_IDE_MAXDEVICE	0	/* max. no. of drives per IDE bus	*/
-
-
-#define CONFIG_SYS_ATA_IDE0_OFFSET	0x0000
-
-#define CONFIG_SYS_ATA_BASE_ADDR	CONFIG_SYS_PCMCIA_MEM_ADDR
-
-/* Offset for data I/O			*/
-#define CONFIG_SYS_ATA_DATA_OFFSET	(CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
-
-/* Offset for normal register accesses	*/
-#define CONFIG_SYS_ATA_REG_OFFSET	(2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
-
-/* Offset for alternate registers	*/
-#define CONFIG_SYS_ATA_ALT_OFFSET	0x0100
-
-/*-----------------------------------------------------------------------
- *
- *-----------------------------------------------------------------------
- *
- */
-/*#define	CONFIG_SYS_DER	0x2002000F*/
-#define CONFIG_SYS_DER	0
-
-/*
- * Init Memory Controller:
- *
- * BR0/1 and OR0/1 (FLASH)
- */
-
-#define FLASH_BASE0_PRELIM	0x40000000	/* FLASH bank #0	*/
-#undef FLASH_BASE1_PRELIM
-
-/* used to re-map FLASH both when starting from SRAM or FLASH:
- * restrict access enough to keep SRAM working (if any)
- * but not too much to meddle with FLASH accesses
- */
-#define CONFIG_SYS_REMAP_OR_AM		0x80000000	/* OR addr mask */
-#define CONFIG_SYS_PRELIM_OR_AM	0xE0000000	/* OR addr mask */
-
-
-/*
- * FLASH timing:
- */
-/* 50 MHz CPU - 50 MHz bus: ACS = 00, TRLX = 1, CSNT = 1, SCY = 2, EHTR = 1 */
-#define CONFIG_SYS_OR_TIMING_FLASH	(OR_ACS_DIV1  | OR_TRLX | OR_CSNT_SAM | \
-				 OR_SCY_2_CLK | OR_EHTR | OR_BI)
-/* FLASH timing: ACS = 11, TRLX = 0, CSNT = 1, SCY = 5, EHTR = 1	*/
-/*
-#define CONFIG_SYS_OR_TIMING_FLASH	(OR_CSNT_SAM  | OR_ACS_DIV2 | OR_BI | \
-				 OR_SCY_5_CLK | OR_EHTR)
-*/
-
-#define CONFIG_SYS_OR0_REMAP	(CONFIG_SYS_REMAP_OR_AM  | CONFIG_SYS_OR_TIMING_FLASH)
-#define CONFIG_SYS_OR0_PRELIM	(CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
-#ifdef CONFIG_MVS_16BIT_FLASH
-#define CONFIG_SYS_BR0_PRELIM	((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V )
-#else
-#define CONFIG_SYS_BR0_PRELIM	((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_32 | BR_V )
-#endif
-
-#undef CONFIG_SYS_OR1_REMAP
-#undef CONFIG_SYS_OR1_PRELIM
-#undef CONFIG_SYS_BR1_PRELIM
-/*
- * BR2/3 and OR2/3 (SDRAM)
- *
- */
-#define SDRAM_BASE2_PRELIM	0x00000000	/* SDRAM bank #0	*/
-#undef SDRAM_BASE3_PRELIM
-#define	SDRAM_MAX_SIZE		0x04000000	/* max 64 MB per bank	*/
-
-/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care)	*/
-#define CONFIG_SYS_OR_TIMING_SDRAM	0x00000A00
-
-#define CONFIG_SYS_OR2_PRELIM	(CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM )
-#define CONFIG_SYS_BR2_PRELIM	((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
-
-#undef CONFIG_SYS_OR3_PRELIM
-#undef CONFIG_SYS_BR3_PRELIM
-
-
-/*
- * Memory Periodic Timer Prescaler
- *
- * The Divider for PTA (refresh timer) configuration is based on an
- * example SDRAM configuration (64 MBit, one bank). The adjustment to
- * the number of chip selects (NCS) and the actually needed refresh
- * rate is done by setting MPTPR.
- *
- * PTA is calculated from
- *	PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS)
- *
- *	gclk	  CPU clock (not bus clock!)
- *	Trefresh  Refresh cycle * 4 (four word bursts used)
- *
- * 4096  Rows from SDRAM example configuration
- * 1000  factor s -> ms
- *   32  PTP (pre-divider from MPTPR) from SDRAM example configuration
- *    4  Number of refresh cycles per period
- *   64  Refresh cycle in ms per number of rows
- * --------------------------------------------
- * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000
- *
- * 50 MHz => 50.000.000 / Divider =  98
- * 66 Mhz => 66.000.000 / Divider = 129
- * 80 Mhz => 80.000.000 / Divider = 156
- */
-#define CONFIG_SYS_MAMR_PTA		 98
-
-/* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit	*/
-#define CONFIG_SYS_MPTPR_2BK_4K	MPTPR_PTP_DIV16		/* setting for 2 banks	*/
-#define CONFIG_SYS_MPTPR_1BK_4K	MPTPR_PTP_DIV32		/* setting for 1 bank	*/
-
-/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit		*/
-#define CONFIG_SYS_MPTPR_2BK_8K	MPTPR_PTP_DIV8		/* setting for 2 banks	*/
-#define CONFIG_SYS_MPTPR_1BK_8K	MPTPR_PTP_DIV16		/* setting for 1 bank	*/
-
-/*
- * MAMR settings for SDRAM
- */
-
-/* 8 column SDRAM */
-#define CONFIG_SYS_MAMR_8COL	((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
-			 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 |	\
-			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
-/* 9 column SDRAM */
-#define CONFIG_SYS_MAMR_9COL	((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
-			 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A7 |	\
-			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
-
-#endif	/* __CONFIG_H */
diff --git a/include/configs/MVSMR.h b/include/configs/MVSMR.h
index 43a0f6e60c..ad15506fad 100644
--- a/include/configs/MVSMR.h
+++ b/include/configs/MVSMR.h
@@ -13,7 +13,6 @@
 
 #include <version.h>
 
-#define CONFIG_MPC5xxx	1
 #define CONFIG_MPC5200 	1
 
 #ifndef CONFIG_SYS_TEXT_BASE
@@ -93,6 +92,7 @@
 #define CONFIG_BOOTP_SEND_HOSTNAME
 #define CONFIG_BOOTP_SUBNETMASK
 #define CONFIG_BOOTP_VENDOREX
+#define CONFIG_LIB_RAND
 
 /*
  * Autoboot
@@ -223,7 +223,6 @@
 #define CONFIG_SYS_HUSH_PARSER
 #define CONFIG_CMDLINE_EDITING
 #undef 	CONFIG_SYS_LONGHELP
-#define CONFIG_SYS_PROMPT		"=> "
 #ifdef CONFIG_CMD_KGDB
 #define CONFIG_SYS_CBSIZE		1024
 #else
@@ -236,8 +235,6 @@
 #define CONFIG_SYS_MEMTEST_START	0x00800000
 #define CONFIG_SYS_MEMTEST_END		0x02f00000
 
-#define CONFIG_SYS_HZ			1000
-
 /* default load address */
 #define CONFIG_SYS_LOAD_ADDR		0x02000000
 /* default location for tftp and bootm */
diff --git a/include/configs/MigoR.h b/include/configs/MigoR.h
index dc4a7681be..88df94f112 100644
--- a/include/configs/MigoR.h
+++ b/include/configs/MigoR.h
@@ -10,8 +10,6 @@
 #define __MIGO_R_H
 
 #undef DEBUG
-#define CONFIG_SH		1
-#define CONFIG_SH4		1
 #define CONFIG_CPU_SH7722	1
 #define CONFIG_MIGO_R		1
 
@@ -43,7 +41,6 @@
 
 #define CONFIG_SYS_TEXT_BASE	0x8FFC0000
 #define CONFIG_SYS_LONGHELP			/* undef to save memory	*/
-#define CONFIG_SYS_PROMPT		"=> "	/* Monitor Command Prompt */
 #define CONFIG_SYS_CBSIZE		256		/* Buffer size for input from the Console */
 #define CONFIG_SYS_PBSIZE		256		/* Buffer size for Console output */
 #define CONFIG_SYS_MAXARGS		16		/* max args accepted for monitor commands */
@@ -123,7 +120,8 @@
 
 /* Board Clock */
 #define CONFIG_SYS_CLK_FREQ	33333333
+#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
+#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
 #define CONFIG_SYS_TMU_CLK_DIV		(4)	/* 4 (default), 16, 64, 256 or 1024 */
-#define CONFIG_SYS_HZ		1000
 
 #endif	/* __MIGO_R_H */
diff --git a/include/configs/NETPHONE.h b/include/configs/NETPHONE.h
index dbf2efc69e..08cfc9e4bc 100644
--- a/include/configs/NETPHONE.h
+++ b/include/configs/NETPHONE.h
@@ -118,7 +118,6 @@
  * Miscellaneous configurable options
  */
 #define	CONFIG_SYS_LONGHELP			/* undef to save memory		*/
-#define	CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt	*/
 
 #define CONFIG_SYS_HUSH_PARSER	1
 
@@ -136,8 +135,6 @@
 
 #define	CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address	*/
 
-#define	CONFIG_SYS_HZ		1000		/* decrementer freq: 1 ms ticks	*/
-
 /*
  * Low Level Configuration Settings
  * (address mappings, register initial values, etc.)
diff --git a/include/configs/NETTA.h b/include/configs/NETTA.h
index 53b0f13687..800a922678 100644
--- a/include/configs/NETTA.h
+++ b/include/configs/NETTA.h
@@ -131,7 +131,6 @@
  * Miscellaneous configurable options
  */
 #define	CONFIG_SYS_LONGHELP			/* undef to save memory		*/
-#define	CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt	*/
 
 #define CONFIG_SYS_HUSH_PARSER	1
 
@@ -149,8 +148,6 @@
 
 #define	CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address	*/
 
-#define	CONFIG_SYS_HZ		1000		/* decrementer freq: 1 ms ticks	*/
-
 /*
  * Low Level Configuration Settings
  * (address mappings, register initial values, etc.)
diff --git a/include/configs/NETTA2.h b/include/configs/NETTA2.h
index 18ab2cca15..55ae4b5338 100644
--- a/include/configs/NETTA2.h
+++ b/include/configs/NETTA2.h
@@ -119,7 +119,6 @@
  * Miscellaneous configurable options
  */
 #define	CONFIG_SYS_LONGHELP			/* undef to save memory		*/
-#define	CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt	*/
 
 #define CONFIG_SYS_HUSH_PARSER	1
 
@@ -137,8 +136,6 @@
 
 #define	CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address	*/
 
-#define	CONFIG_SYS_HZ		1000		/* decrementer freq: 1 ms ticks	*/
-
 /*
  * Low Level Configuration Settings
  * (address mappings, register initial values, etc.)
diff --git a/include/configs/NETVIA.h b/include/configs/NETVIA.h
index 0fd635dc27..4a0fa9e119 100644
--- a/include/configs/NETVIA.h
+++ b/include/configs/NETVIA.h
@@ -104,7 +104,6 @@
  * Miscellaneous configurable options
  */
 #define	CONFIG_SYS_LONGHELP			/* undef to save memory		*/
-#define	CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt	*/
 #if defined(CONFIG_CMD_KGDB)
 #define	CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
 #else
@@ -119,8 +118,6 @@
 
 #define	CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address	*/
 
-#define	CONFIG_SYS_HZ		1000		/* decrementer freq: 1 ms ticks	*/
-
 /*
  * Low Level Configuration Settings
  * (address mappings, register initial values, etc.)
diff --git a/include/configs/NSCU.h b/include/configs/NSCU.h
index 46faa5d6e9..a9c649abe9 100644
--- a/include/configs/NSCU.h
+++ b/include/configs/NSCU.h
@@ -118,7 +118,6 @@
  * Miscellaneous configurable options
  */
 #define	CONFIG_SYS_LONGHELP			/* undef to save memory		*/
-#define	CONFIG_SYS_PROMPT		"=> "	/* Monitor Command Prompt	*/
 
 #define CONFIG_CMDLINE_EDITING	1	/* add command line history
 */
@@ -138,8 +137,6 @@
 
 #define	CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address	*/
 
-#define	CONFIG_SYS_HZ			1000	/* decrementer freq: 1 ms ticks	*/
-
 /*
  * Low Level Configuration Settings
  * (address mappings, register initial values, etc.)
diff --git a/include/configs/NX823.h b/include/configs/NX823.h
index 9cfa087345..6d468dfcd1 100644
--- a/include/configs/NX823.h
+++ b/include/configs/NX823.h
@@ -68,7 +68,6 @@
  * Miscellaneous configurable options
  */
 #define CONFIG_SYS_LONGHELP			/* undef to save memory	    */
-#define CONFIG_SYS_PROMPT		"=> "	/* Monitor Command Prompt   */
 #if defined(CONFIG_CMD_KGDB)
 #define CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size  */
 #else
@@ -83,8 +82,6 @@
 
 #define CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address */
 
-#define CONFIG_SYS_HZ			1000	/* decrementer freq: 1 ms ticks */
-
 /*
  * Low Level Configuration Settings
  * (address mappings, register initial values, etc.)
diff --git a/include/configs/OCRTC.h b/include/configs/OCRTC.h
index 11e7b5baf8..4680afee07 100644
--- a/include/configs/OCRTC.h
+++ b/include/configs/OCRTC.h
@@ -18,7 +18,6 @@
  */
 
 #define CONFIG_405GP		1	/* This is a PPC405 CPU		*/
-#define CONFIG_4xx		1	/* ...member of PPC4xx family	*/
 #define CONFIG_OCRTC		1	/* ...on a OCRTC board		*/
 
 #define	CONFIG_SYS_TEXT_BASE	0xFFFD0000
@@ -75,7 +74,6 @@
  * Miscellaneous configurable options
  */
 #define CONFIG_SYS_LONGHELP			/* undef to save memory		*/
-#define CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt	*/
 #if defined(CONFIG_CMD_KGDB)
 #define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
 #else
@@ -107,8 +105,6 @@
 #define CONFIG_SYS_LOAD_ADDR	0x100000	/* default load address */
 #define CONFIG_SYS_EXTBDINFO	1		/* To use extended board_into (bd_t) */
 
-#define CONFIG_SYS_HZ		1000		/* decrementer freq: 1 ms ticks */
-
 #define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */
 
 /*-----------------------------------------------------------------------
diff --git a/include/configs/ORSG.h b/include/configs/ORSG.h
deleted file mode 100644
index b269a33cb0..0000000000
--- a/include/configs/ORSG.h
+++ /dev/null
@@ -1,285 +0,0 @@
-/*
- * (C) Copyright 2001
- * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-/*
- * board/config.h - configuration options, board specific
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_405GP		1	/* This is a PPC405 CPU		*/
-#define CONFIG_4xx		1	/* ...member of PPC4xx family	*/
-#define CONFIG_ORSG		1	/* ...on a ORSG board		*/
-
-#define CONFIG_BOARD_EARLY_INIT_F 1	/* call board_early_init_f()	*/
-
-#define CONFIG_SYS_CLK_FREQ	33000000 /* external frequency to pll	*/
-
-#define CONFIG_BAUDRATE		9600
-#define CONFIG_BOOTDELAY	3	/* autoboot after 3 seconds	*/
-
-#undef	CONFIG_BOOTARGS
-#define CONFIG_BOOTCOMMAND "go fff00100"
-
-#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
-#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
-
-#define CONFIG_PPC4xx_EMAC
-#define CONFIG_MII		1	/* MII PHY management		*/
-#define CONFIG_PHY_ADDR		0	/* PHY address			*/
-#define CONFIG_LXT971_NO_SLEEP  1       /* disable sleep mode in LXT971 */
-
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_PCI
-#define CONFIG_CMD_IRQ
-#define CONFIG_CMD_ASKENV
-#define CONFIG_CMD_ELF
-#define CONFIG_CMD_BSP
-#define CONFIG_CMD_EEPROM
-
-
-#define CONFIG_MAC_PARTITION
-#define CONFIG_DOS_PARTITION
-
-#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
-
-#define CONFIG_SDRAM_BANK0	1	/* init onboard SDRAM bank 0	*/
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP			/* undef to save memory		*/
-#define CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt	*/
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
-#else
-#define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
-#endif
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
-#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
-
-#define CONFIG_SYS_CONSOLE_INFO_QUIET	1	/* don't print console @ startup*/
-
-#define CONFIG_SYS_MEMTEST_START	0x0400000	/* memtest works on	*/
-#define CONFIG_SYS_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
-
-#define CONFIG_CONS_INDEX	1	/* Use UART0			*/
-#define CONFIG_SYS_NS16550
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE	1
-#define CONFIG_SYS_NS16550_CLK		get_serial_clock()
-
-#undef	CONFIG_SYS_EXT_SERIAL_CLOCK	       /* no external serial clock used */
-#define CONFIG_SYS_BASE_BAUD	    691200
-
-/* The following table includes the supported baudrates */
-#define CONFIG_SYS_BAUDRATE_TABLE	\
-	{ 300, 600, 1200, 2400, 4800, 9600, 19200, 38400,     \
-	 57600, 115200, 230400, 460800, 921600 }
-
-#define CONFIG_SYS_LOAD_ADDR	0x100000	/* default load address */
-#define CONFIG_SYS_EXTBDINFO	1		/* To use extended board_into (bd_t) */
-
-#define CONFIG_SYS_HZ		1000		/* decrementer freq: 1 ms ticks */
-
-#define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */
-
-/*-----------------------------------------------------------------------
- * PCI stuff
- *-----------------------------------------------------------------------
- */
-#define PCI_HOST_ADAPTER 0		/* configure as pci adapter	*/
-#define PCI_HOST_FORCE	1		/* configure as pci host	*/
-#define PCI_HOST_AUTO	2		/* detected via arbiter enable	*/
-
-#define CONFIG_PCI			/* include pci support		*/
-#define CONFIG_PCI_INDIRECT_BRIDGE	/* indirect PCI bridge support */
-#define CONFIG_PCI_HOST PCI_HOST_ADAPTER /* select pci adapter		*/
-#undef	CONFIG_PCI_PNP			/* no pci plug-and-play		*/
-					/* resource configuration	*/
-
-#undef	CONFIG_PCI_SCAN_SHOW		/* print pci devices @ startup	*/
-
-#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x12FE	/* PCI Vendor ID: esd gmbh	*/
-#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0411	/* PCI Device ID: ORSG		*/
-#define CONFIG_SYS_PCI_CLASSCODE	0x0b20	/* PCI Class Code: Processor/PPC*/
-#define CONFIG_SYS_PCI_PTM1LA	0x00000000	/* point to sdram		*/
-#define CONFIG_SYS_PCI_PTM1MS	0xfc000001	/* 64MB, enable hard-wired to 1 */
-#define CONFIG_SYS_PCI_PTM1PCI 0x00000000	/* Host: use this pci address	*/
-#define CONFIG_SYS_PCI_PTM2LA	0xffc00000	/* point to flash		*/
-#define CONFIG_SYS_PCI_PTM2MS	0xffc00001	/* 4MB, enable			*/
-#define CONFIG_SYS_PCI_PTM2PCI 0x04000000	/* Host: use this pci address	*/
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
- */
-#define CONFIG_SYS_SDRAM_BASE		0x00000000
-#define CONFIG_SYS_FLASH_BASE		0xFFFD0000
-#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_MONITOR_LEN		(192 * 1024)	/* Reserve 192 kB for Monitor	*/
-#define CONFIG_SYS_MALLOC_LEN		(128 * 1024)	/* Reserve 128 kB for malloc()	*/
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-#define CONFIG_SYS_MAX_FLASH_BANKS	2	/* max number of memory banks		*/
-#define CONFIG_SYS_MAX_FLASH_SECT	256	/* max number of sectors on one chip	*/
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
-#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
-
-#define CONFIG_SYS_FLASH_WORD_SIZE	unsigned short	/* flash word size (width)	*/
-#define CONFIG_SYS_FLASH_ADDR0		0x5555	/* 1st address for flash config cycles	*/
-#define CONFIG_SYS_FLASH_ADDR1		0x2AAA	/* 2nd address for flash config cycles	*/
-/*
- * The following defines are added for buggy IOP480 byte interface.
- * All other boards should use the standard values (CPCI405 etc.)
- */
-#define CONFIG_SYS_FLASH_READ0		0x0000	/* 0 is standard			*/
-#define CONFIG_SYS_FLASH_READ1		0x0001	/* 1 is standard			*/
-#define CONFIG_SYS_FLASH_READ2		0x0002	/* 2 is standard			*/
-
-#define CONFIG_SYS_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
-
-#if 0 /* Use NVRAM for environment variables */
-/*-----------------------------------------------------------------------
- * NVRAM organization
- */
-#define CONFIG_ENV_IS_IN_NVRAM	1	/* use NVRAM for environment vars	*/
-#define CONFIG_SYS_NVRAM_BASE_ADDR	0xf0200000		/* NVRAM base address	*/
-#define CONFIG_SYS_NVRAM_SIZE		(32*1024)		/* NVRAM size		*/
-#define CONFIG_ENV_SIZE		0x1000		/* Size of Environment vars	*/
-#define CONFIG_ENV_ADDR		\
-	(CONFIG_SYS_NVRAM_BASE_ADDR+CONFIG_SYS_NVRAM_SIZE-CONFIG_ENV_SIZE)	/* Env	*/
-#define CONFIG_SYS_NVRAM_VXWORKS_OFFS	0x6900		/* Offset for VxWorks eth-addr	*/
-
-#else /* Use EEPROM for environment variables */
-
-#define CONFIG_ENV_IS_IN_EEPROM	1	/* use EEPROM for environment vars */
-#define CONFIG_ENV_OFFSET		0x000	/* environment starts at the beginning of the EEPROM */
-#define CONFIG_ENV_SIZE		0x300	/* 768 bytes may be used for env vars */
-				   /* total size of a CAT24WC08 is 1024 bytes */
-#endif
-
-/*-----------------------------------------------------------------------
- * I2C EEPROM (CAT24WC08) for environment
- */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_PPC4XX
-#define CONFIG_SYS_I2C_PPC4XX_CH0
-#define CONFIG_SYS_I2C_PPC4XX_SPEED_0		400000
-#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0		0x7F
-
-#define CONFIG_SYS_I2C_EEPROM_ADDR	0x50	/* EEPROM CAT28WC08		*/
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1	/* Bytes of address		*/
-/* mask of address bits that overflow into the "EEPROM chip address"	*/
-#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW	0x07
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4	/* The Catalyst CAT24WC08 has	*/
-					/* 16 byte page write mode using*/
-					/* last 4 bits of the address	*/
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10   /* and takes up to 10 msec */
-
-/*
- * Init Memory Controller:
- *
- * BR0/1 and OR0/1 (FLASH)
- */
-
-#define FLASH_BASE0_PRELIM	0xFF800000	/* FLASH bank #0	*/
-#define FLASH_BASE1_PRELIM	0xFFC00000	/* FLASH bank #1	*/
-
-/*-----------------------------------------------------------------------
- * External Bus Controller (EBC) Setup
- */
-
-/* Memory Bank 0 (Flash Bank 0) initialization					*/
-#define CONFIG_SYS_EBC_PB0AP		0x92015480
-#define CONFIG_SYS_EBC_PB0CR		0xFFC5A000  /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
-
-/* Memory Bank 1 (Flash Bank 1) initialization					*/
-#define CONFIG_SYS_EBC_PB1AP		0x92015480
-#define CONFIG_SYS_EBC_PB1CR		0xFF85A000  /* BAS=0xFF8,BS=4MB,BU=R/W,BW=16bit */
-
-/* Memory Bank 2 (PLD - FPGA-boot) initialization				*/
-#define CONFIG_SYS_EBC_PB2AP		0x02015480  /* BME=0x0,TWT=0x04,CSN=0x0,OEN=0x1 */
-					    /* WBN=0x1,WBF=0x1,TH=0x2,RE=0x0,SOR=0x1,BEM=0x0,PEN=0x0*/
-#define CONFIG_SYS_EBC_PB2CR		0xF0018000  /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit	*/
-
-/* Memory Bank 3 (PLD - OSL) initialization					*/
-#define CONFIG_SYS_EBC_PB3AP		0x02015480  /* BME=0x0,TWT=0x04,CSN=0x0,OEN=0x1 */
-					    /* WBN=0x1,WBF=0x1,TH=0x2,RE=0x0,SOR=0x1,BEM=0x0,PEN=0x0*/
-#define CONFIG_SYS_EBC_PB3CR		0xF0118000  /* BAS=0xF01,BS=1MB,BU=R/W,BW=8bit	*/
-
-/* Memory Bank 4 (Spartan2 1) initialization					*/
-#define CONFIG_SYS_EBC_PB4AP		0x02015580  /* BME=0x0,TWT=0x04,CSN=0x0,OEN=0x1 */
-					    /* WBN=0x1,WBF=0x1,TH=0x2,RE=0x1,SOR=0x1,BEM=0x0,PEN=0x0*/
-#define CONFIG_SYS_EBC_PB4CR		0xF209C000  /* BAS=0xF20,BS=16MB,BU=R/W,BW=32bit*/
-
-/* Memory Bank 5 (Spartan2 2) initialization					*/
-#define CONFIG_SYS_EBC_PB5AP		0x02015580  /* BME=0x0,TWT=0x04,CSN=0x0,OEN=0x1 */
-					    /* WBN=0x1,WBF=0x1,TH=0x2,RE=0x1,SOR=0x1,BEM=0x0,PEN=0x0*/
-#define CONFIG_SYS_EBC_PB5CR		0xF309C000  /* BAS=0xF30,BS=16MB,BU=R/W,BW=32bit*/
-
-/* Memory Bank 6 (Virtex 1) initialization					*/
-#define CONFIG_SYS_EBC_PB6AP		0x02015580  /* BME=0x0,TWT=0x04,CSN=0x0,OEN=0x1 */
-					    /* WBN=0x1,WBF=0x1,TH=0x2,RE=0x1,SOR=0x1,BEM=0x0,PEN=0x0*/
-#define CONFIG_SYS_EBC_PB6CR		0xF409A000  /* BAS=0xF40,BS=16MB,BU=R/W,BW=16bit*/
-
-/* Memory Bank 7 (Virtex 2) initialization					*/
-#define CONFIG_SYS_EBC_PB7AP		0x02015580  /* BME=0x0,TWT=0x04,CSN=0x0,OEN=0x1 */
-					    /* WBN=0x1,WBF=0x1,TH=0x2,RE=0x1,SOR=0x1,BEM=0x0,PEN=0x0*/
-#define CONFIG_SYS_EBC_PB7CR		0xF509A000  /* BAS=0xF50,BS=16MB,BU=R/W,BW=16bit*/
-
-
-#define CONFIG_SYS_VXWORKS_MAC_PTR	0x00000000	/* Pass Ethernet MAC to VxWorks */
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area (in DPRAM)
- */
-
-/* use on chip memory ( OCM ) for temperary stack until sdram is tested */
-#define CONFIG_SYS_TEMP_STACK_OCM	  1
-
-/* On Chip Memory location */
-#define CONFIG_SYS_OCM_DATA_ADDR	0xF8000000
-#define CONFIG_SYS_OCM_DATA_SIZE	0x1000
-
-#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM		*/
-#define CONFIG_SYS_INIT_RAM_SIZE	CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM	*/
-#define CONFIG_SYS_GBL_DATA_OFFSET    (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
-
-#endif	/* __CONFIG_H */
diff --git a/include/configs/P1010RDB.h b/include/configs/P1010RDB.h
index ba3f7c2821..eabfc85f0f 100644
--- a/include/configs/P1010RDB.h
+++ b/include/configs/P1010RDB.h
@@ -21,23 +21,79 @@
 #define CONFIG_NAND_FSL_IFC
 
 #ifdef CONFIG_SDCARD
-#define CONFIG_RAMBOOT_SDCARD
-#define CONFIG_SYS_TEXT_BASE		0x11000000
-#define CONFIG_RESET_VECTOR_ADDRESS	0x1107fffc
+#define CONFIG_SPL
+#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
+#define CONFIG_SPL_DRIVERS_MISC_SUPPORT
+#define CONFIG_SPL_ENV_SUPPORT
+#define CONFIG_SPL_SERIAL_SUPPORT
+#define CONFIG_SPL_MMC_SUPPORT
+#define CONFIG_SPL_MMC_MINIMAL
+#define CONFIG_SPL_FLUSH_IMAGE
+#define CONFIG_SPL_TARGET		"u-boot-with-spl.bin"
+#define CONFIG_SPL_LIBGENERIC_SUPPORT
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+#define CONFIG_SPL_I2C_SUPPORT
+#define CONFIG_FSL_LAW                 /* Use common FSL init code */
+#define CONFIG_SYS_TEXT_BASE		0x11001000
+#define CONFIG_SPL_TEXT_BASE		0xD0001000
+#define CONFIG_SPL_PAD_TO		0x18000
+#define CONFIG_SPL_MAX_SIZE		(96 * 1024)
+#define CONFIG_SYS_MMC_U_BOOT_SIZE	(512 << 10)
+#define CONFIG_SYS_MMC_U_BOOT_DST	(0x11000000)
+#define CONFIG_SYS_MMC_U_BOOT_START	(0x11000000)
+#define CONFIG_SYS_MMC_U_BOOT_OFFS	(96 << 10)
+#define CONFIG_SYS_MPC85XX_NO_RESETVEC
+#define CONFIG_SYS_LDSCRIPT	"arch/powerpc/cpu/mpc85xx/u-boot.lds"
+#define CONFIG_SPL_MMC_BOOT
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SPL_COMMON_INIT_DDR
+#endif
 #endif
 
 #ifdef CONFIG_SPIFLASH
+#ifdef CONFIG_SECURE_BOOT
 #define CONFIG_RAMBOOT_SPIFLASH
 #define CONFIG_SYS_TEXT_BASE		0x11000000
 #define CONFIG_RESET_VECTOR_ADDRESS	0x1107fffc
+#else
+#define CONFIG_SPL
+#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
+#define CONFIG_SPL_DRIVERS_MISC_SUPPORT
+#define CONFIG_SPL_ENV_SUPPORT
+#define CONFIG_SPL_SERIAL_SUPPORT
+#define CONFIG_SPL_SPI_SUPPORT
+#define CONFIG_SPL_SPI_FLASH_SUPPORT
+#define CONFIG_SPL_SPI_FLASH_MINIMAL
+#define CONFIG_SPL_FLUSH_IMAGE
+#define CONFIG_SPL_TARGET		"u-boot-with-spl.bin"
+#define CONFIG_SPL_LIBGENERIC_SUPPORT
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+#define CONFIG_SPL_I2C_SUPPORT
+#define CONFIG_FSL_LAW         /* Use common FSL init code */
+#define CONFIG_SYS_TEXT_BASE			0x11001000
+#define CONFIG_SPL_TEXT_BASE			0xD0001000
+#define CONFIG_SPL_PAD_TO			0x18000
+#define CONFIG_SPL_MAX_SIZE			(96 * 1024)
+#define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE	(512 << 10)
+#define CONFIG_SYS_SPI_FLASH_U_BOOT_DST		(0x11000000)
+#define CONFIG_SYS_SPI_FLASH_U_BOOT_START	(0x11000000)
+#define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS	(96 << 10)
+#define CONFIG_SYS_MPC85XX_NO_RESETVEC
+#define CONFIG_SYS_LDSCRIPT	"arch/powerpc/cpu/mpc85xx/u-boot.lds"
+#define CONFIG_SPL_SPI_BOOT
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SPL_COMMON_INIT_DDR
+#endif
+#endif
 #endif
 
 #ifdef CONFIG_NAND
 #define CONFIG_SPL
+#ifdef CONFIG_SECURE_BOOT
 #define CONFIG_SPL_INIT_MINIMAL
 #define CONFIG_SPL_SERIAL_SUPPORT
 #define CONFIG_SPL_NAND_SUPPORT
-#define CONFIG_SPL_NAND_MINIMAL
+#define CONFIG_SPL_NAND_BOOT
 #define CONFIG_SPL_FLUSH_IMAGE
 #define CONFIG_SPL_TARGET		"u-boot-with-spl.bin"
 
@@ -46,22 +102,62 @@
 #define CONFIG_SPL_MAX_SIZE		8192
 #define CONFIG_SPL_RELOC_TEXT_BASE	0x00100000
 #define CONFIG_SPL_RELOC_STACK		0x00100000
-#define CONFIG_SYS_NAND_U_BOOT_SIZE	((512 << 10) - 0x2000)
+#define CONFIG_SYS_NAND_U_BOOT_SIZE	((768 << 10) - 0x2000)
 #define CONFIG_SYS_NAND_U_BOOT_DST	(0x00200000 - CONFIG_SPL_MAX_SIZE)
 #define CONFIG_SYS_NAND_U_BOOT_START	0x00200000
 #define CONFIG_SYS_NAND_U_BOOT_OFFS	0
 #define CONFIG_SYS_LDSCRIPT	"arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
+#else
+#define CONFIG_TPL
+#ifdef CONFIG_TPL_BUILD
+#define CONFIG_SPL_NAND_BOOT
+#define CONFIG_SPL_FLUSH_IMAGE
+#define CONFIG_SPL_ENV_SUPPORT
+#define CONFIG_SPL_NAND_INIT
+#define CONFIG_SPL_SERIAL_SUPPORT
+#define CONFIG_SPL_LIBGENERIC_SUPPORT
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+#define CONFIG_SPL_I2C_SUPPORT
+#define CONFIG_SPL_NAND_SUPPORT
+#define CONFIG_SPL_DRIVERS_MISC_SUPPORT
+#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
+#define CONFIG_SPL_COMMON_INIT_DDR
+#define CONFIG_SPL_MAX_SIZE		(128 << 10)
+#define CONFIG_SPL_TEXT_BASE		0xD0001000
+#define CONFIG_SYS_MPC85XX_NO_RESETVEC
+#define CONFIG_SYS_NAND_U_BOOT_SIZE	(576 << 10)
+#define CONFIG_SYS_NAND_U_BOOT_DST	(0x11000000)
+#define CONFIG_SYS_NAND_U_BOOT_START	(0x11000000)
+#define CONFIG_SYS_NAND_U_BOOT_OFFS	((128 + 128) << 10)
+#elif defined(CONFIG_SPL_BUILD)
+#define CONFIG_SPL_INIT_MINIMAL
+#define CONFIG_SPL_SERIAL_SUPPORT
+#define CONFIG_SPL_NAND_SUPPORT
+#define CONFIG_SPL_NAND_MINIMAL
+#define CONFIG_SPL_FLUSH_IMAGE
+#define CONFIG_SPL_TEXT_BASE		0xff800000
+#define CONFIG_SPL_MAX_SIZE		8192
+#define CONFIG_SYS_NAND_U_BOOT_SIZE	(128 << 10)
+#define CONFIG_SYS_NAND_U_BOOT_DST	0xD0000000
+#define CONFIG_SYS_NAND_U_BOOT_START	0xD0000000
+#define CONFIG_SYS_NAND_U_BOOT_OFFS	(128 << 10)
+#endif
+#define CONFIG_SPL_PAD_TO	0x20000
+#define CONFIG_TPL_PAD_TO	0x20000
+#define CONFIG_SPL_TARGET	"u-boot-with-spl.bin"
+#define CONFIG_SYS_TEXT_BASE	0x11001000
+#define CONFIG_SYS_LDSCRIPT	"arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
+#endif
 #endif
-
 
 #ifdef CONFIG_NAND_SECBOOT	/* NAND Boot */
 #define CONFIG_RAMBOOT_NAND
 #define CONFIG_SYS_TEXT_BASE		0x11000000
-#define CONFIG_RESET_VECTOR_ADDRESS	0x1107fffc
+#define CONFIG_RESET_VECTOR_ADDRESS	0x110bfffc
 #endif
 
 #ifndef CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_TEXT_BASE		0xeff80000
+#define CONFIG_SYS_TEXT_BASE		0xeff40000
 #endif
 
 #ifndef CONFIG_RESET_VECTOR_ADDRESS
@@ -77,7 +173,6 @@
 /* High Level Configuration Options */
 #define CONFIG_BOOKE			/* BOOKE */
 #define CONFIG_E500			/* BOOKE e500 family */
-#define CONFIG_MPC85xx
 #define CONFIG_FSL_IFC			/* Enable IFC Support */
 #define CONFIG_SYS_HAS_SERDES		/* common SERDES init code */
 
@@ -120,7 +215,11 @@
 #endif
 
 /* controller 2, Slot 2, tgtid 2, Base address 9000 */
+#if defined(CONFIG_P1010RDB_PA)
 #define CONFIG_SYS_PCIE2_NAME		"PCIe Slot"
+#elif defined(CONFIG_P1010RDB_PB)
+#define CONFIG_SYS_PCIE2_NAME		"mini PCIe Slot"
+#endif
 #define CONFIG_SYS_PCIE2_MEM_VIRT	0xa0000000
 #ifdef CONFIG_PHYS_64BIT
 #define CONFIG_SYS_PCIE2_MEM_BUS	0xc0000000
@@ -152,10 +251,7 @@
 #define CONFIG_DDR_CLK_FREQ	66666666 /* DDRCLK on P1010 RDB */
 #define CONFIG_SYS_CLK_FREQ	66666666 /* SYSCLK for P1010 RDB */
 
-#ifndef CONFIG_SDCARD
 #define CONFIG_MISC_INIT_R
-#endif
-
 #define CONFIG_HWCONFIG
 /*
  * These can be toggled for performance analysis, otherwise use default.
@@ -172,12 +268,12 @@
 #define CONFIG_SYS_NUM_ADDR_MAP		16	/* number of TLB1 entries */
 #endif
 
-#define CONFIG_SYS_MEMTEST_START	0x00000000	/* memtest works on */
+#define CONFIG_SYS_MEMTEST_START	0x00200000	/* memtest works on */
 #define CONFIG_SYS_MEMTEST_END		0x1fffffff
 #define CONFIG_PANIC_HANG		/* do not reset board on panic */
 
 /* DDR Setup */
-#define CONFIG_FSL_DDR3
+#define CONFIG_SYS_FSL_DDR3
 #define CONFIG_SYS_DDR_RAW_TIMING
 #define CONFIG_DDR_SPD
 #define CONFIG_SYS_SPD_BUS_NUM		1
@@ -203,25 +299,24 @@ extern unsigned long get_sdram_size(void);
 #define CONFIG_SYS_DDR_INIT_ADDR	0x00000000
 #define CONFIG_SYS_DDR_INIT_EXT_ADDR	0x00000000
 #define CONFIG_SYS_DDR_MODE_CONTROL	0x00000000
-
 #define CONFIG_SYS_DDR_ZQ_CONTROL	0x89080600
 #define CONFIG_SYS_DDR_SR_CNTR		0x00000000
 #define CONFIG_SYS_DDR_RCW_1		0x00000000
 #define CONFIG_SYS_DDR_RCW_2		0x00000000
-#define CONFIG_SYS_DDR_CONTROL		0x470C0000	/* Type = DDR3  */
-#define CONFIG_SYS_DDR_CONTROL_2	0x04401010
+#define CONFIG_SYS_DDR_CONTROL		0xc70c0008      /* Type = DDR3  */
+#define CONFIG_SYS_DDR_CONTROL_2	0x24401000
 #define CONFIG_SYS_DDR_TIMING_4		0x00000001
 #define CONFIG_SYS_DDR_TIMING_5		0x03402400
 
-#define CONFIG_SYS_DDR_TIMING_3_800	0x00020000
-#define CONFIG_SYS_DDR_TIMING_0_800	0x00330004
-#define CONFIG_SYS_DDR_TIMING_1_800	0x6f6B4644
+#define CONFIG_SYS_DDR_TIMING_3_800	0x00030000
+#define CONFIG_SYS_DDR_TIMING_0_800	0x00110104
+#define CONFIG_SYS_DDR_TIMING_1_800	0x6f6b8644
 #define CONFIG_SYS_DDR_TIMING_2_800	0x0FA888CF
 #define CONFIG_SYS_DDR_CLK_CTRL_800	0x03000000
-#define CONFIG_SYS_DDR_MODE_1_800	0x40461520
-#define CONFIG_SYS_DDR_MODE_2_800	0x8000c000
+#define CONFIG_SYS_DDR_MODE_1_800	0x00441420
+#define CONFIG_SYS_DDR_MODE_2_800	0x00000000
 #define CONFIG_SYS_DDR_INTERVAL_800	0x0C300100
-#define CONFIG_SYS_DDR_WRLVL_CONTROL_800	0x8655A608
+#define CONFIG_SYS_DDR_WRLVL_CONTROL_800 0x8675f608
 
 /* settings for DDR3 at 667MT/s */
 #define CONFIG_SYS_DDR_TIMING_3_667		0x00010000
@@ -256,10 +351,6 @@ extern unsigned long get_sdram_size(void);
  * 0xffe0_0000	0xffef_ffff	CCSR			1M non-cacheable
  */
 
-/* In case of SD card boot, IFC interface is not available because of muxing */
-#ifdef CONFIG_SDCARD
-#define CONFIG_SYS_NO_FLASH
-#else
 /*
  * IFC Definitions
  */
@@ -317,11 +408,20 @@ extern unsigned long get_sdram_size(void);
 #define CONFIG_SYS_NAND_BASE_PHYS	CONFIG_SYS_NAND_BASE
 #endif
 
+#define CONFIG_MTD_DEVICE
+#define CONFIG_MTD_PARTITION
+#define CONFIG_CMD_MTDPARTS
+#define MTDIDS_DEFAULT			"nand0=ff800000.flash"
+#define MTDPARTS_DEFAULT		\
+	"mtdparts=ff800000.flash:2m(uboot-env),1m(dtb),5m(kernel),56m(fs),-(usr)"
+
 #define CONFIG_SYS_NAND_CSPR	(CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 				| CSPR_PORT_SIZE_8	\
 				| CSPR_MSEL_NAND	\
 				| CSPR_V)
 #define CONFIG_SYS_NAND_AMASK	IFC_AMASK(64*1024)
+
+#if defined(CONFIG_P1010RDB_PA)
 #define CONFIG_SYS_NAND_CSOR	(CSOR_NAND_ECC_ENC_EN	/* ECC on encode */ \
 				| CSOR_NAND_ECC_DEC_EN	/* ECC on decode */ \
 				| CSOR_NAND_ECC_MODE_4	/* 4-bit ECC */ \
@@ -329,13 +429,26 @@ extern unsigned long get_sdram_size(void);
 				| CSOR_NAND_PGS_512	/* Page Size = 512b */ \
 				| CSOR_NAND_SPRZ_16	/* Spare size = 16 */ \
 				| CSOR_NAND_PB(32))	/* 32 Pages Per Block */
+#define CONFIG_SYS_NAND_BLOCK_SIZE	(16 * 1024)
+
+#elif defined(CONFIG_P1010RDB_PB)
+#define CONFIG_SYS_NAND_ONFI_DETECTION
+#define CONFIG_SYS_NAND_CSOR   (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
+				| CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
+				| CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
+				| CSOR_NAND_RAL_3       /* RAL = 3Byes */ \
+				| CSOR_NAND_PGS_4K      /* Page Size = 4K */ \
+				| CSOR_NAND_SPRZ_224    /* Spare size = 224 */ \
+				| CSOR_NAND_PB(128))  /*Pages Per Block = 128 */
+#define CONFIG_SYS_NAND_BLOCK_SIZE     (512 * 1024)
+#endif
 
 #define CONFIG_SYS_NAND_BASE_LIST	{ CONFIG_SYS_NAND_BASE }
 #define CONFIG_SYS_MAX_NAND_DEVICE	1
 #define CONFIG_MTD_NAND_VERIFY_WRITE
 #define CONFIG_CMD_NAND
-#define CONFIG_SYS_NAND_BLOCK_SIZE	(16 * 1024)
 
+#if defined(CONFIG_P1010RDB_PA)
 /* NAND Flash Timing Params */
 #define CONFIG_SYS_NAND_FTIM0		FTIM0_NAND_TCCST(0x01) | \
 					FTIM0_NAND_TWP(0x0C)   | \
@@ -350,6 +463,23 @@ extern unsigned long get_sdram_size(void);
 					FTIM2_NAND_TWHRE(0x0f)
 #define CONFIG_SYS_NAND_FTIM3		FTIM3_NAND_TWW(0x04)
 
+#elif defined(CONFIG_P1010RDB_PB)
+/* support MT29F16G08ABABAWP 4k-pagesize 2G-bytes NAND */
+/* ONFI NAND Flash mode0 Timing Params */
+#define CONFIG_SYS_NAND_FTIM0  (FTIM0_NAND_TCCST(0x07)| \
+					FTIM0_NAND_TWP(0x18)   | \
+					FTIM0_NAND_TWCHT(0x07) | \
+					FTIM0_NAND_TWH(0x0a))
+#define CONFIG_SYS_NAND_FTIM1  (FTIM1_NAND_TADLE(0x32)| \
+					FTIM1_NAND_TWBE(0x39)  | \
+					FTIM1_NAND_TRR(0x0e)   | \
+					FTIM1_NAND_TRP(0x18))
+#define CONFIG_SYS_NAND_FTIM2  (FTIM2_NAND_TRAD(0x0f) | \
+					FTIM2_NAND_TREH(0x0a)  | \
+					FTIM2_NAND_TWHRE(0x1e))
+#define CONFIG_SYS_NAND_FTIM3	0x0
+#endif
+
 #define CONFIG_SYS_NAND_DDR_LAW		11
 
 /* Set up IFC registers for boot location NOR/NAND */
@@ -410,7 +540,6 @@ extern unsigned long get_sdram_size(void);
 					FTIM2_GPCM_TCH(0x0) | \
 					FTIM2_GPCM_TWP(0x1f))
 #define CONFIG_SYS_CS3_FTIM3		0x0
-#endif	/* CONFIG_SDCARD */
 
 #if defined(CONFIG_RAMBOOT_SDCARD) || defined(CONFIG_RAMBOOT_SPIFLASH)
 #define CONFIG_SYS_RAMBOOT
@@ -440,6 +569,43 @@ extern unsigned long get_sdram_size(void);
 #define CONFIG_SYS_MONITOR_LEN		(256 * 1024) /* Reserve 256 kB for Mon*/
 #define CONFIG_SYS_MALLOC_LEN		(1024 * 1024)	/* Reserved for malloc*/
 
+/*
+ * Config the L2 Cache as L2 SRAM
+ */
+#if defined(CONFIG_SPL_BUILD)
+#if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH)
+#define CONFIG_SYS_INIT_L2_ADDR		0xD0000000
+#define CONFIG_SYS_INIT_L2_ADDR_PHYS	CONFIG_SYS_INIT_L2_ADDR
+#define CONFIG_SYS_L2_SIZE		(256 << 10)
+#define CONFIG_SYS_INIT_L2_END	(CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
+#define CONFIG_SPL_RELOC_TEXT_BASE	0xD0001000
+#define CONFIG_SPL_RELOC_STACK		(CONFIG_SYS_INIT_L2_ADDR + 112 * 1024)
+#define CONFIG_SPL_RELOC_STACK_SIZE	(16 << 10)
+#define CONFIG_SPL_RELOC_MALLOC_ADDR	(CONFIG_SYS_INIT_L2_ADDR + 128 * 1024)
+#define CONFIG_SPL_RELOC_MALLOC_SIZE	(128 << 10)
+#define CONFIG_SPL_GD_ADDR		(CONFIG_SYS_INIT_L2_ADDR + 96 * 1024)
+#elif defined(CONFIG_NAND)
+#ifdef CONFIG_TPL_BUILD
+#define CONFIG_SYS_INIT_L2_ADDR		0xD0000000
+#define CONFIG_SYS_INIT_L2_ADDR_PHYS	CONFIG_SYS_INIT_L2_ADDR
+#define CONFIG_SYS_L2_SIZE		(256 << 10)
+#define CONFIG_SYS_INIT_L2_END	(CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
+#define CONFIG_SPL_RELOC_TEXT_BASE	0xD0001000
+#define CONFIG_SPL_RELOC_STACK		(CONFIG_SYS_INIT_L2_ADDR + 192 * 1024)
+#define CONFIG_SPL_RELOC_MALLOC_ADDR	(CONFIG_SYS_INIT_L2_ADDR + 208 * 1024)
+#define CONFIG_SPL_RELOC_MALLOC_SIZE	(48 << 10)
+#define CONFIG_SPL_GD_ADDR		(CONFIG_SYS_INIT_L2_ADDR + 176 * 1024)
+#else
+#define CONFIG_SYS_INIT_L2_ADDR		0xD0000000
+#define CONFIG_SYS_INIT_L2_ADDR_PHYS	CONFIG_SYS_INIT_L2_ADDR
+#define CONFIG_SYS_L2_SIZE		(256 << 10)
+#define CONFIG_SYS_INIT_L2_END	(CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
+#define CONFIG_SPL_RELOC_TEXT_BASE	(CONFIG_SYS_INIT_L2_END - 0x3000)
+#define CONFIG_SPL_RELOC_STACK		((CONFIG_SYS_INIT_L2_END - 1) & ~0xF)
+#endif
+#endif
+#endif
+
 /* Serial Port */
 #define CONFIG_CONS_INDEX	1
 #undef	CONFIG_SERIAL_SOFTWARE_FIFO
@@ -447,7 +613,7 @@ extern unsigned long get_sdram_size(void);
 #define CONFIG_SYS_NS16550_SERIAL
 #define CONFIG_SYS_NS16550_REG_SIZE	1
 #define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)
-#ifdef CONFIG_SPL_BUILD
+#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL)
 #define CONFIG_NS16550_MIN_FUNCTIONS
 #endif
 
@@ -482,9 +648,21 @@ extern unsigned long get_sdram_size(void);
 #define CONFIG_SYS_FSL_I2C2_SPEED	400000
 #define CONFIG_SYS_FSL_I2C2_SLAVE	0x7F
 #define CONFIG_SYS_FSL_I2C2_OFFSET	0x3100
+#define I2C_PCA9557_ADDR1		0x18
+#define I2C_PCA9557_ADDR2		0x19
+#define I2C_PCA9557_BUS_NUM		0
 
 /* I2C EEPROM */
-#undef CONFIG_ID_EEPROM
+#if defined(CONFIG_P1010RDB_PB)
+#define CONFIG_ID_EEPROM
+#ifdef CONFIG_ID_EEPROM
+#define CONFIG_SYS_I2C_EEPROM_NXID
+#endif
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	1
+#define CONFIG_SYS_I2C_EEPROM_ADDR	0x57
+#define CONFIG_SYS_EEPROM_BUS_NUM	0
+#define MAX_NUM_PORTS			9 /* for 128Bytes EEPROM */
+#endif
 /* enable read and write access to EEPROM */
 #define CONFIG_CMD_EEPROM
 #define CONFIG_SYS_I2C_MULTI_EEPROMS
@@ -567,12 +745,7 @@ extern unsigned long get_sdram_size(void);
 #define CONFIG_LBA48
 #endif /* #ifdef CONFIG_FSL_SATA  */
 
-/*  SD interface will only be available in case of SD boot */
-#ifdef CONFIG_SDCARD
 #define CONFIG_MMC
-#define CONFIG_DEF_HWCONFIG		esdhc
-#endif
-
 #ifdef CONFIG_MMC
 #define CONFIG_CMD_MMC
 #define CONFIG_DOS_PARTITION
@@ -597,12 +770,12 @@ extern unsigned long get_sdram_size(void);
 /*
  * Environment
  */
-#if defined(CONFIG_RAMBOOT_SDCARD)
+#if defined(CONFIG_SDCARD)
 #define CONFIG_ENV_IS_IN_MMC
 #define CONFIG_FSL_FIXED_MMC_LOCATION
 #define CONFIG_SYS_MMC_ENV_DEV		0
 #define CONFIG_ENV_SIZE			0x2000
-#elif defined(CONFIG_RAMBOOT_SPIFLASH)
+#elif defined(CONFIG_SPIFLASH)
 #define CONFIG_ENV_IS_IN_SPI_FLASH
 #define CONFIG_ENV_SPI_BUS	0
 #define CONFIG_ENV_SPI_CS	0
@@ -613,20 +786,26 @@ extern unsigned long get_sdram_size(void);
 #define CONFIG_ENV_SIZE		0x2000
 #elif defined(CONFIG_NAND)
 #define CONFIG_ENV_IS_IN_NAND
+#ifdef CONFIG_TPL_BUILD
+#define CONFIG_ENV_SIZE		0x2000
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_INIT_L2_ADDR + (160 << 10))
+#else
+#if defined(CONFIG_P1010RDB_PA)
 #define CONFIG_ENV_SIZE		CONFIG_SYS_NAND_BLOCK_SIZE
-#define CONFIG_ENV_OFFSET	((512 * 1024) + CONFIG_SYS_NAND_BLOCK_SIZE)
-#define CONFIG_ENV_RANGE	(3 * CONFIG_ENV_SIZE)
+#define CONFIG_ENV_RANGE	(3 * CONFIG_ENV_SIZE) /* 3*16=48K for env */
+#elif defined(CONFIG_P1010RDB_PB)
+#define CONFIG_ENV_SIZE		(16 * 1024)
+#define CONFIG_ENV_RANGE	(32 * CONFIG_ENV_SIZE) /* new block size 512K */
+#endif
+#endif
+#define CONFIG_ENV_OFFSET	(1024 * 1024)
 #elif defined(CONFIG_SYS_RAMBOOT)
 #define CONFIG_ENV_IS_NOWHERE		/* Store ENV in memory only */
 #define CONFIG_ENV_ADDR			(CONFIG_SYS_MONITOR_BASE - 0x1000)
 #define CONFIG_ENV_SIZE			0x2000
 #else
 #define CONFIG_ENV_IS_IN_FLASH
-#if CONFIG_SYS_MONITOR_BASE > 0xfff80000
-#define CONFIG_ENV_ADDR	0xfff80000
-#else
 #define CONFIG_ENV_ADDR	(CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
-#endif
 #define CONFIG_ENV_SIZE		0x2000
 #define CONFIG_ENV_SECT_SIZE	0x20000 /* 128K (one sector) */
 #endif
@@ -664,7 +843,6 @@ extern unsigned long get_sdram_size(void);
 #define CONFIG_CMDLINE_EDITING			/* Command-line editing */
 #define CONFIG_AUTO_COMPLETE			/* add autocompletion support */
 #define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
-#define CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt */
 
 #if defined(CONFIG_CMD_KGDB)
 #define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size */
@@ -675,7 +853,6 @@ extern unsigned long get_sdram_size(void);
 						/* Print Buffer Size */
 #define CONFIG_SYS_MAXARGS	16		/* max number of command args */
 #define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
-#define CONFIG_SYS_HZ		1000		/* dec freq: 1ms ticks */
 
 /*
  * Internal Definitions
@@ -695,7 +872,6 @@ extern unsigned long get_sdram_size(void);
 
 #if defined(CONFIG_CMD_KGDB)
 #define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
-#define CONFIG_KGDB_SER_INDEX	2	/* which serial port to use */
 #endif
 
 /*
@@ -708,7 +884,6 @@ extern unsigned long get_sdram_size(void);
 #define CONFIG_HAS_ETH2
 #endif
 
-#define CONFIG_HOSTNAME		P1010RDB
 #define CONFIG_ROOTPATH		"/opt/nfsroot"
 #define CONFIG_BOOTFILE		"uImage"
 #define CONFIG_UBOOTPATH	u-boot.bin/* U-Boot image on TFTP server */
@@ -747,7 +922,31 @@ extern unsigned long get_sdram_size(void);
 	"ext2load usb 0:4 $loadaddr $bootfile;"		\
 	"ext2load usb 0:4 $fdtaddr $fdtfile;"	\
 	"ext2load usb 0:4 $ramdiskaddr $ramdiskfile;"	\
-	"bootm $loadaddr $ramdiskaddr $fdtaddr\0"		\
+	"bootm $loadaddr $ramdiskaddr $fdtaddr\0"	\
+	CONFIG_BOOTMODE
+
+#if defined(CONFIG_P1010RDB_PA)
+#define CONFIG_BOOTMODE \
+	"boot_bank0=i2c dev 0; i2c mw 18 1 f1; i2c mw 18 3 f0;" \
+	"mw.b ffb00011 0; mw.b ffb00009 0; reset\0" \
+	"boot_bank1=i2c dev 0; i2c mw 18 1 f1; i2c mw 18 3 f0;" \
+	"mw.b ffb00011 0; mw.b ffb00009 1; reset\0" \
+	"boot_nand=i2c dev 0; i2c mw 18 1 f9; i2c mw 18 3 f0;" \
+	"mw.b ffb00011 0; mw.b ffb00017 1; reset\0"
+
+#elif defined(CONFIG_P1010RDB_PB)
+#define CONFIG_BOOTMODE \
+	"boot_bank0=i2c dev 0; i2c mw 18 1 fe; i2c mw 18 3 0;" \
+	"i2c mw 19 1 2; i2c mw 19 3 e1; reset\0" \
+	"boot_bank1=i2c dev 0; i2c mw 18 1 fe; i2c mw 18 3 0;" \
+	"i2c mw 19 1 12; i2c mw 19 3 e1; reset\0" \
+	"boot_nand=i2c dev 0; i2c mw 18 1 fc; i2c mw 18 3 0;" \
+	"i2c mw 19 1 8; i2c mw 19 3 f7; reset\0" \
+	"boot_spi=i2c dev 0; i2c mw 18 1 fa; i2c mw 18 3 0;" \
+	"i2c mw 19 1 0; i2c mw 19 3 f7; reset\0" \
+	"boot_sd=i2c dev 0; i2c mw 18 1 f8; i2c mw 18 3 0;" \
+	"i2c mw 19 1 4; i2c mw 19 3 f3; reset\0"
+#endif
 
 #define CONFIG_RAMBOOTCOMMAND		\
 	"setenv bootargs root=/dev/ram rw "	\
@@ -759,8 +958,6 @@ extern unsigned long get_sdram_size(void);
 
 #define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND
 
-#ifdef CONFIG_SECURE_BOOT
 #include <asm/fsl_secure_boot.h>
-#endif
 
 #endif	/* __CONFIG_H */
diff --git a/include/configs/P1022DS.h b/include/configs/P1022DS.h
index edece1f9b5..139d4fed25 100644
--- a/include/configs/P1022DS.h
+++ b/include/configs/P1022DS.h
@@ -30,12 +30,12 @@
 #define CONFIG_FSL_LAW			/* Use common FSL init code */
 #define CONFIG_SYS_TEXT_BASE		0x11001000
 #define CONFIG_SPL_TEXT_BASE		0xf8f81000
-#define CONFIG_SPL_PAD_TO		0x18000
-#define CONFIG_SPL_MAX_SIZE		(96 * 1024)
-#define CONFIG_SYS_MMC_U_BOOT_SIZE	(512 << 10)
+#define CONFIG_SPL_PAD_TO		0x20000
+#define CONFIG_SPL_MAX_SIZE		(128 * 1024)
+#define CONFIG_SYS_MMC_U_BOOT_SIZE	(768 << 10)
 #define CONFIG_SYS_MMC_U_BOOT_DST	(0x11000000)
 #define CONFIG_SYS_MMC_U_BOOT_START	(0x11000000)
-#define CONFIG_SYS_MMC_U_BOOT_OFFS	(96 << 10)
+#define CONFIG_SYS_MMC_U_BOOT_OFFS	(128 << 10)
 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
 #define CONFIG_SYS_LDSCRIPT		"arch/powerpc/cpu/mpc85xx/u-boot.lds"
 #define CONFIG_SPL_MMC_BOOT
@@ -60,12 +60,12 @@
 #define CONFIG_FSL_LAW		/* Use common FSL init code */
 #define CONFIG_SYS_TEXT_BASE		0x11001000
 #define CONFIG_SPL_TEXT_BASE		0xf8f81000
-#define CONFIG_SPL_PAD_TO		0x18000
-#define CONFIG_SPL_MAX_SIZE		(96 * 1024)
-#define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE	(512 << 10)
+#define CONFIG_SPL_PAD_TO		0x20000
+#define CONFIG_SPL_MAX_SIZE		(128 * 1024)
+#define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE	(768 << 10)
 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST		(0x11000000)
 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START	(0x11000000)
-#define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS	(96 << 10)
+#define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS	(128 << 10)
 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
 #define CONFIG_SYS_LDSCRIPT	"arch/powerpc/cpu/mpc85xx/u-boot.lds"
 #define CONFIG_SPL_SPI_BOOT
@@ -75,6 +75,8 @@
 #endif
 
 #define CONFIG_NAND_FSL_ELBC
+#define CONFIG_SYS_NAND_MAX_ECCPOS	56
+#define CONFIG_SYS_NAND_MAX_OOBFREE	5
 
 #ifdef CONFIG_NAND
 #define CONFIG_SPL
@@ -94,7 +96,7 @@
 #define CONFIG_SPL_MAX_SIZE		(128 << 10)
 #define CONFIG_SPL_TEXT_BASE		0xf8f81000
 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
-#define CONFIG_SYS_NAND_U_BOOT_SIZE	(576 << 10)
+#define CONFIG_SYS_NAND_U_BOOT_SIZE	(832 << 10)
 #define CONFIG_SYS_NAND_U_BOOT_DST	(0x11000000)
 #define CONFIG_SYS_NAND_U_BOOT_START	(0x11000000)
 #define CONFIG_SYS_NAND_U_BOOT_OFFS	((128 + 128) << 10)
@@ -120,13 +122,12 @@
 /* High Level Configuration Options */
 #define CONFIG_BOOKE			/* BOOKE */
 #define CONFIG_E500			/* BOOKE e500 family */
-#define CONFIG_MPC85xx			/* MPC8540/60/55/41/48 */
 #define CONFIG_P1022
 #define CONFIG_P1022DS
 #define CONFIG_MP			/* support multiple processors */
 
 #ifndef CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_TEXT_BASE	0xeff80000
+#define CONFIG_SYS_TEXT_BASE	0xeff40000
 #endif
 
 #ifndef CONFIG_RESET_VECTOR_ADDRESS
@@ -177,7 +178,7 @@
 /* DDR Setup */
 #define CONFIG_DDR_SPD
 #define CONFIG_VERY_BIG_RAM
-#define CONFIG_FSL_DDR3
+#define CONFIG_SYS_FSL_DDR3
 
 #ifdef CONFIG_DDR_ECC
 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
@@ -364,10 +365,10 @@
 #define CONFIG_SYS_L2_SIZE		(256 << 10)
 #define CONFIG_SYS_INIT_L2_END	(CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
 #define CONFIG_SPL_RELOC_TEXT_BASE	0xf8f81000
-#define CONFIG_SPL_RELOC_STACK		(CONFIG_SYS_INIT_L2_ADDR + 128 * 1024)
+#define CONFIG_SPL_RELOC_STACK		(CONFIG_SYS_INIT_L2_ADDR + 116 * 1024)
 #define CONFIG_SPL_RELOC_STACK_SIZE	(32 << 10)
-#define CONFIG_SPL_RELOC_MALLOC_ADDR	(CONFIG_SYS_INIT_L2_ADDR + 160 * 1024)
-#define CONFIG_SPL_RELOC_MALLOC_SIZE	(96 << 10)
+#define CONFIG_SPL_RELOC_MALLOC_ADDR	(CONFIG_SYS_INIT_L2_ADDR + 148 * 1024)
+#define CONFIG_SPL_RELOC_MALLOC_SIZE	(108 << 10)
 #define CONFIG_SPL_GD_ADDR		(CONFIG_SYS_INIT_L2_ADDR + 112 * 1024)
 #elif defined(CONFIG_NAND)
 #ifdef CONFIG_TPL_BUILD
@@ -651,11 +652,7 @@
 #define CONFIG_ENV_SIZE		0x2000
 #else
 #define CONFIG_ENV_IS_IN_FLASH
-#if CONFIG_SYS_MONITOR_BASE > 0xfff80000
-#define CONFIG_ENV_ADDR	0xfff80000
-#else
 #define CONFIG_ENV_ADDR	(CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
-#endif
 #define CONFIG_ENV_SIZE		0x2000
 #define CONFIG_ENV_SECT_SIZE	0x20000 /* 128K (one sector) */
 #endif
@@ -705,7 +702,6 @@
 #define CONFIG_CMDLINE_EDITING			/* Command-line editing */
 #define CONFIG_AUTO_COMPLETE			/* add autocompletion support */
 #define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
-#define CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt */
 #ifdef CONFIG_CMD_KGDB
 #define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size */
 #else
@@ -715,7 +711,6 @@
 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
 #define CONFIG_SYS_MAXARGS	16
 #define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE
-#define CONFIG_SYS_HZ		1000
 
 /*
  * For booting Linux, the board info and command line data
@@ -727,7 +722,6 @@
 
 #ifdef CONFIG_CMD_KGDB
 #define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
-#define CONFIG_KGDB_SER_INDEX	2	/* which serial port to use */
 #endif
 
 /*
diff --git a/include/configs/P1023RDB.h b/include/configs/P1023RDB.h
index cd6d20c729..b41cb4a13e 100644
--- a/include/configs/P1023RDB.h
+++ b/include/configs/P1023RDB.h
@@ -11,7 +11,7 @@
 #define __CONFIG_H
 
 #ifndef CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_TEXT_BASE	0xeff80000
+#define CONFIG_SYS_TEXT_BASE	0xeff40000
 #endif
 
 #ifndef CONFIG_SYS_MONITOR_BASE
@@ -25,7 +25,6 @@
 /* High Level Configuration Options */
 #define CONFIG_BOOKE		/* BOOKE */
 #define CONFIG_E500		/* BOOKE e500 family */
-#define CONFIG_MPC85xx
 #define CONFIG_P1023
 #define CONFIG_MP		/* support multiple processors */
 
@@ -74,7 +73,7 @@ extern unsigned long get_clock_freq(void);
 #define CONFIG_CHIP_SELECTS_PER_CTRL	1
 
 #define CONFIG_DDR_SPD
-#define CONFIG_FSL_DDR3
+#define CONFIG_SYS_FSL_DDR3
 #define CONFIG_FSL_DDR_INTERACTIVE
 #define CONFIG_SYS_SDRAM_SIZE		512u	/* DDR is 512M */
 #define CONFIG_SYS_SPD_BUS_NUM          0
@@ -260,11 +259,7 @@ extern unsigned long get_clock_freq(void);
 #define CONFIG_ENV_OVERWRITE
 
 #define CONFIG_ENV_IS_IN_FLASH
-#if CONFIG_SYS_MONITOR_BASE > 0xfff80000
-#define CONFIG_ENV_ADDR		0xfff80000
-#else
 #define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
-#endif
 #define CONFIG_ENV_SIZE		0x2000
 #define CONFIG_ENV_SECT_SIZE	0x20000 /* 128K (one sector) */
 
@@ -312,7 +307,6 @@ extern unsigned long get_clock_freq(void);
 #define CONFIG_SYS_LONGHELP			/* undef to save memory	*/
 #define CONFIG_CMDLINE_EDITING		/* Command-line editing */
 #define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
-#define CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt */
 #if defined(CONFIG_CMD_KGDB)
 #define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size */
 #else
@@ -323,7 +317,6 @@ extern unsigned long get_clock_freq(void);
 #define CONFIG_SYS_MAXARGS	16		/* max number of command args */
 /* Boot Argument Buffer Size */
 #define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE
-#define CONFIG_SYS_HZ	1000		/* decrementer freq: 1ms ticks */
 
 /*
  * For booting Linux, the board info and command line data
@@ -367,7 +360,7 @@ extern unsigned long get_clock_freq(void);
 /* Default address of microcode for the Linux Fman driver */
 /* QE microcode/firmware address */
 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
-#define CONFIG_SYS_QE_FMAN_FW_ADDR	0xeff40000
+#define CONFIG_SYS_QE_FMAN_FW_ADDR	0xEFF00000
 #define CONFIG_SYS_QE_FMAN_FW_LENGTH	0x10000
 #define CONFIG_SYS_FDT_PAD		(0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
 
diff --git a/include/configs/P1023RDS.h b/include/configs/P1023RDS.h
index a8202c67fd..2ffa3546de 100644
--- a/include/configs/P1023RDS.h
+++ b/include/configs/P1023RDS.h
@@ -26,13 +26,13 @@
 #ifdef CONFIG_NAND_SPL
 #define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE_SPL /* start of monitor */
 #else
-#define CONFIG_SYS_LDSCRIPT $(TOPDIR)/$(CPUDIR)/u-boot-nand.lds
+#define CONFIG_SYS_LDSCRIPT $(CPUDIR)/u-boot-nand.lds
 #define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE	/* start of monitor */
 #endif /* CONFIG_NAND_SPL */
 #endif
 
 #ifndef CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_TEXT_BASE	0xeff80000
+#define CONFIG_SYS_TEXT_BASE	0xeff40000
 #endif
 
 #ifndef CONFIG_SYS_MONITOR_BASE
@@ -46,7 +46,6 @@
 /* High Level Configuration Options */
 #define CONFIG_BOOKE		/* BOOKE */
 #define CONFIG_E500		/* BOOKE e500 family */
-#define CONFIG_MPC85xx
 #define CONFIG_P1023
 #define CONFIG_P1023RDS
 #define CONFIG_MP		/* support multiple processors */
@@ -195,9 +194,8 @@ extern unsigned long get_clock_freq(void);
 #define CONFIG_SYS_INIT_RAM_ADDR	0xffd00000	/* Initial L1 address */
 #define CONFIG_SYS_INIT_RAM_END	0x00004000	/* End of used area in RAM */
 
-#define CONFIG_SYS_GBL_DATA_SIZE	128	/* num bytes initial data */
 #define CONFIG_SYS_GBL_DATA_OFFSET	\
-	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+	(CONFIG_SYS_INIT_RAM_END - GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 #define CONFIG_SYS_MONITOR_LEN	(256 * 1024) /* Reserve 256 kB for Mon */
@@ -220,7 +218,7 @@ extern unsigned long get_clock_freq(void);
 
 /* NAND boot: 4K NAND loader config */
 #define CONFIG_SYS_NAND_SPL_SIZE	0x1000
-#define CONFIG_SYS_NAND_U_BOOT_SIZE	((512 << 10) + CONFIG_SYS_NAND_SPL_SIZE)
+#define CONFIG_SYS_NAND_U_BOOT_SIZE	((768 << 10) + CONFIG_SYS_NAND_SPL_SIZE)
 #define CONFIG_SYS_NAND_U_BOOT_DST	(0x11000000 - CONFIG_SYS_NAND_SPL_SIZE)
 #define CONFIG_SYS_NAND_U_BOOT_START	0x11000000
 #define CONFIG_SYS_NAND_U_BOOT_OFFS	(0)
@@ -386,7 +384,7 @@ extern unsigned long get_clock_freq(void);
 #if defined(CONFIG_RAMBOOT_NAND)
 #define CONFIG_ENV_IS_IN_NAND
 #define CONFIG_ENV_SIZE		CONFIG_SYS_NAND_BLOCK_SIZE
-#define CONFIG_ENV_OFFSET	((512 * 1024) + CONFIG_SYS_NAND_BLOCK_SIZE)
+#define CONFIG_ENV_OFFSET	((768 * 1024) + CONFIG_SYS_NAND_BLOCK_SIZE)
 #else
 #define CONFIG_ENV_IS_NOWHERE	/* Store ENV in memory only */
 #define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - 0x4000)
@@ -394,11 +392,7 @@ extern unsigned long get_clock_freq(void);
 #endif
 #else
 #define CONFIG_ENV_IS_IN_FLASH
-#if CONFIG_SYS_MONITOR_BASE > 0xfff80000
-#define CONFIG_ENV_ADDR		0xfff80000
-#else
 #define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
-#endif
 #define CONFIG_ENV_SIZE		0x2000
 #define CONFIG_ENV_SECT_SIZE	0x20000 /* 128K (one sector) */
 #endif
@@ -448,7 +442,6 @@ extern unsigned long get_clock_freq(void);
 #define CONFIG_SYS_LONGHELP			/* undef to save memory	*/
 #define CONFIG_CMDLINE_EDITING		/* Command-line editing */
 #define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
-#define CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt */
 #if defined(CONFIG_CMD_KGDB)
 #define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size */
 #else
@@ -459,7 +452,6 @@ extern unsigned long get_clock_freq(void);
 #define CONFIG_SYS_MAXARGS	16		/* max number of command args */
 /* Boot Argument Buffer Size */
 #define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE
-#define CONFIG_SYS_HZ	1000		/* decrementer freq: 1ms ticks */
 
 /*
  * For booting Linux, the board info and command line data
@@ -471,7 +463,6 @@ extern unsigned long get_clock_freq(void);
 
 #if defined(CONFIG_CMD_KGDB)
 #define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
-#define CONFIG_KGDB_SER_INDEX	2	/* which serial port to use */
 #endif
 
 /*
@@ -509,7 +500,7 @@ extern unsigned long get_clock_freq(void);
 /* Default address of microcode for the Linux Fman driver */
 /* QE microcode/firmware address */
 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
-#define CONFIG_SYS_QE_FMAN_FW_ADDR	0xEFF40000
+#define CONFIG_SYS_QE_FMAN_FW_ADDR	0xEFF00000
 #else
 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND
 #define CONFIG_SYS_QE_FMAN_FW_ADDR	0x1f00000
diff --git a/include/configs/P1_P2_RDB.h b/include/configs/P1_P2_RDB.h
index adaed564f7..2ffaf5c0d9 100644
--- a/include/configs/P1_P2_RDB.h
+++ b/include/configs/P1_P2_RDB.h
@@ -38,7 +38,7 @@
 #define CONFIG_SYS_TEXT_BASE_SPL 0xfff00000
 #define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE_SPL /* start of monitor */
 #else
-#define CONFIG_SYS_LDSCRIPT $(TOPDIR)/$(CPUDIR)/u-boot-nand.lds
+#define CONFIG_SYS_LDSCRIPT $(CPUDIR)/u-boot-nand.lds
 #define CONFIG_SYS_TEXT_BASE		0xf8f82000
 #endif /* CONFIG_NAND_SPL */
 #endif
@@ -46,17 +46,17 @@
 #ifdef CONFIG_SDCARD
 #define CONFIG_RAMBOOT_SDCARD		1
 #define CONFIG_SYS_TEXT_BASE		0x11000000
-#define CONFIG_RESET_VECTOR_ADDRESS	0x1107fffc
+#define CONFIG_RESET_VECTOR_ADDRESS	0x110bfffc
 #endif
 
 #ifdef CONFIG_SPIFLASH
 #define CONFIG_RAMBOOT_SPIFLASH		1
 #define CONFIG_SYS_TEXT_BASE		0x11000000
-#define CONFIG_RESET_VECTOR_ADDRESS	0x1107fffc
+#define CONFIG_RESET_VECTOR_ADDRESS	0x110bfffc
 #endif
 
 #ifndef CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_TEXT_BASE		0xeff80000
+#define CONFIG_SYS_TEXT_BASE		0xeff40000
 #endif
 
 #ifndef CONFIG_RESET_VECTOR_ADDRESS
@@ -70,7 +70,6 @@
 /* High Level Configuration Options */
 #define CONFIG_BOOKE		1	/* BOOKE */
 #define CONFIG_E500		1	/* BOOKE e500 family */
-#define CONFIG_MPC85xx		1	/* MPC8540/60/55/41/48/P1020/P2020,etc*/
 #define CONFIG_FSL_ELBC		1	/* Enable eLBC Support */
 
 #define CONFIG_PCI		1	/* Enable PCI/PCIE */
@@ -141,7 +140,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
 #endif
 
 /* DDR Setup */
-#define CONFIG_FSL_DDR2
+#define CONFIG_SYS_FSL_DDR2
 #undef CONFIG_FSL_DDR_INTERACTIVE
 #undef CONFIG_SPD_EEPROM		/* Use SPD EEPROM for DDR setup */
 
@@ -267,7 +266,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
 
 /* NAND boot: 4K NAND loader config */
 #define CONFIG_SYS_NAND_SPL_SIZE	0x1000
-#define CONFIG_SYS_NAND_U_BOOT_SIZE	((512 << 10) - 0x2000)
+#define CONFIG_SYS_NAND_U_BOOT_SIZE	((768 << 10) - 0x2000)
 #define CONFIG_SYS_NAND_U_BOOT_DST	(CONFIG_SYS_INIT_L2_ADDR)
 #define CONFIG_SYS_NAND_U_BOOT_START	(CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_NAND_SPL_SIZE)
 #define CONFIG_SYS_NAND_U_BOOT_OFFS	(0)
@@ -495,7 +494,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
 #if defined(CONFIG_RAMBOOT_NAND)
 	#define CONFIG_ENV_IS_IN_NAND	1
 	#define CONFIG_ENV_SIZE		CONFIG_SYS_NAND_BLOCK_SIZE
-	#define CONFIG_ENV_OFFSET	((512 * 1024) + CONFIG_SYS_NAND_BLOCK_SIZE)
+	#define CONFIG_ENV_OFFSET	((768*1024)+CONFIG_SYS_NAND_BLOCK_SIZE)
 #elif defined(CONFIG_RAMBOOT_SDCARD)
 #define CONFIG_ENV_IS_IN_MMC
 #define CONFIG_FSL_FIXED_MMC_LOCATION
@@ -513,11 +512,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
 #endif
 #else
 	#define CONFIG_ENV_IS_IN_FLASH	1
-	#if CONFIG_SYS_MONITOR_BASE > 0xfff80000
-	#define CONFIG_ENV_ADDR		0xfff80000
-	#else
 	#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
-	#endif
 	#define CONFIG_ENV_SIZE		0x2000
 	#define CONFIG_ENV_SECT_SIZE	0x20000 /* 128K (one sector) */
 #endif
@@ -586,7 +581,6 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
 #define CONFIG_CMDLINE_EDITING			/* Command-line editing */
 #define CONFIG_AUTO_COMPLETE			/* add autocompletion support */
 #define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
-#define CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt */
 #if defined(CONFIG_CMD_KGDB)
 #define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size */
 #else
@@ -596,7 +590,6 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
 						/* Print Buffer Size */
 #define CONFIG_SYS_MAXARGS	16		/* max number of command args */
 #define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
-#define CONFIG_SYS_HZ		1000		/* decrementer freq: 1ms ticks */
 
 /*
  * For booting Linux, the board info and command line data
@@ -608,7 +601,6 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
 
 #if defined(CONFIG_CMD_KGDB)
 #define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
-#define CONFIG_KGDB_SER_INDEX	2	/* which serial port to use */
 #endif
 
 /*
diff --git a/include/configs/P2020COME.h b/include/configs/P2020COME.h
index 08d1c25914..d414b84dd2 100644
--- a/include/configs/P2020COME.h
+++ b/include/configs/P2020COME.h
@@ -29,7 +29,6 @@
 /* High Level Configuration Options */
 #define CONFIG_BOOKE		1	/* BOOKE */
 #define CONFIG_E500		1	/* BOOKE e500 family */
-#define CONFIG_MPC85xx		1	/* MPC8540/60/55/41/48/P1020/P2020,etc*/
 #define CONFIG_P2020		1
 #define CONFIG_P2020COME	1
 #define CONFIG_FSL_ELBC		1	/* Enable eLBC Support */
@@ -105,7 +104,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
 #define CONFIG_SYS_CCSRBAR_PHYS_LOW	CONFIG_SYS_CCSRBAR
 
 /* DDR Setup */
-#define CONFIG_FSL_DDR3
+#define CONFIG_SYS_FSL_DDR3
 #define CONFIG_SPD_EEPROM		/* Use SPD EEPROM for DDR setup */
 #define CONFIG_DDR_SPD
 
@@ -412,7 +411,6 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
 #define CONFIG_CMDLINE_EDITING			/* Command-line editing */
 #define CONFIG_AUTO_COMPLETE	1		/* add autocompletion support */
 #define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
-#define CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt */
 #if defined(CONFIG_CMD_KGDB)
 #define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size */
 #else
@@ -422,7 +420,6 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
 						/* Print Buffer Size */
 #define CONFIG_SYS_MAXARGS	16		/* max number of command args */
 #define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
-#define CONFIG_SYS_HZ		1000		/* decrementer freq: 1ms tick */
 
 /*
  * For booting Linux, the board info and command line data
@@ -434,7 +431,6 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
 
 #if defined(CONFIG_CMD_KGDB)
 #define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
-#define CONFIG_KGDB_SER_INDEX	2	/* which serial port to use */
 #endif
 
 /*
diff --git a/include/configs/P2020DS.h b/include/configs/P2020DS.h
index 785e497f20..3d0b5c2fbe 100644
--- a/include/configs/P2020DS.h
+++ b/include/configs/P2020DS.h
@@ -20,27 +20,26 @@
 #ifdef CONFIG_SDCARD
 #define CONFIG_SYS_RAMBOOT
 #define CONFIG_SYS_EXTRA_ENV_RELOC
-#define CONFIG_SYS_TEXT_BASE		0xf8f80000
+#define CONFIG_SYS_TEXT_BASE		0xf8f40000
 #define CONFIG_RESET_VECTOR_ADDRESS	0xf8fffffc
 #endif
 
 #ifdef CONFIG_SPIFLASH
 #define CONFIG_SYS_RAMBOOT
 #define CONFIG_SYS_EXTRA_ENV_RELOC
-#define CONFIG_SYS_TEXT_BASE		0xf8f80000
+#define CONFIG_SYS_TEXT_BASE		0xf8f40000
 #define CONFIG_RESET_VECTOR_ADDRESS	0xf8fffffc
 #endif
 
 /* High Level Configuration Options */
 #define CONFIG_BOOKE		1	/* BOOKE */
 #define CONFIG_E500		1	/* BOOKE e500 family */
-#define CONFIG_MPC85xx		1	/* MPC8540/60/55/41/48 */
 #define CONFIG_P2020		1
 #define CONFIG_P2020DS		1
 #define CONFIG_MP		1	/* support multiple processors */
 
 #ifndef CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_TEXT_BASE	0xeff80000
+#define CONFIG_SYS_TEXT_BASE	0xeff40000
 #endif
 
 #ifndef CONFIG_RESET_VECTOR_ADDRESS
@@ -109,9 +108,9 @@
 /* DDR Setup */
 #define CONFIG_VERY_BIG_RAM
 #ifdef CONFIG_DDR2
-#define CONFIG_FSL_DDR2
+#define CONFIG_SYS_FSL_DDR2
 #else
-#define CONFIG_FSL_DDR3		1
+#define CONFIG_SYS_FSL_DDR3		1
 #endif
 
 /* ECC will be enabled based on perf_mode environment variable */
@@ -578,11 +577,7 @@
 #define CONFIG_ENV_SECT_SIZE		0x10000
 #else
 #define CONFIG_ENV_IS_IN_FLASH	1
-#if CONFIG_SYS_MONITOR_BASE > 0xfff80000
-#define CONFIG_ENV_ADDR		0xfff80000
-#else
 #define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
-#endif
 #define CONFIG_ENV_SIZE		0x2000
 #define CONFIG_ENV_SECT_SIZE	0x20000 /* 128K (one sector) */
 #endif
@@ -651,7 +646,6 @@
 #define CONFIG_CMDLINE_EDITING			/* Command-line editing */
 #define CONFIG_AUTO_COMPLETE			/* add autocompletion support */
 #define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
-#define CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt */
 #if defined(CONFIG_CMD_KGDB)
 #define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size */
 #else
@@ -660,7 +654,6 @@
 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
 #define CONFIG_SYS_MAXARGS	16		/* max number of command args */
 #define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size */
-#define CONFIG_SYS_HZ		1000		/* decrementer freq: 1ms ticks */
 
 /*
  * For booting Linux, the board info and command line data
@@ -672,7 +665,6 @@
 
 #if defined(CONFIG_CMD_KGDB)
 #define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
-#define CONFIG_KGDB_SER_INDEX	2	/* which serial port to use */
 #endif
 
 /*
diff --git a/include/configs/P2041RDB.h b/include/configs/P2041RDB.h
index 862614b5c2..b3880f190f 100644
--- a/include/configs/P2041RDB.h
+++ b/include/configs/P2041RDB.h
@@ -18,8 +18,8 @@
 #ifdef CONFIG_RAMBOOT_PBL
 #define CONFIG_RAMBOOT_TEXT_BASE	CONFIG_SYS_TEXT_BASE
 #define CONFIG_RESET_VECTOR_ADDRESS	0xfffffffc
-#define CONFIG_PBLPBI_CONFIG $(SRCTREE)/board/freescale/corenet_ds/pbi.cfg
-#define CONFIG_PBLRCW_CONFIG $(SRCTREE)/board/freescale/corenet_ds/rcw_p2041rdb.cfg
+#define CONFIG_SYS_FSL_PBL_PBI board/freescale/corenet_ds/pbi.cfg
+#define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p2041rdb.cfg
 #endif
 
 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
@@ -36,11 +36,10 @@
 #define CONFIG_E500			/* BOOKE e500 family */
 #define CONFIG_E500MC			/* BOOKE e500mc family */
 #define CONFIG_SYS_BOOK3E_HV		/* Category E.HV supported */
-#define CONFIG_MPC85xx			/* MPC85xx/PQ3 platform */
 #define CONFIG_MP			/* support multiple processors */
 
 #ifndef CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_TEXT_BASE	0xeff80000
+#define CONFIG_SYS_TEXT_BASE	0xeff40000
 #endif
 
 #ifndef CONFIG_RESET_VECTOR_ADDRESS
@@ -93,12 +92,12 @@
 	#define CONFIG_FSL_FIXED_MMC_LOCATION
 	#define CONFIG_SYS_MMC_ENV_DEV          0
 	#define CONFIG_ENV_SIZE			0x2000
-	#define CONFIG_ENV_OFFSET		(512 * 1097)
+	#define CONFIG_ENV_OFFSET		(512 * 1658)
 #elif defined(CONFIG_NAND)
 #define CONFIG_SYS_EXTRA_ENV_RELOC
 #define CONFIG_ENV_IS_IN_NAND
 #define CONFIG_ENV_SIZE			CONFIG_SYS_NAND_BLOCK_SIZE
-#define CONFIG_ENV_OFFSET		(5 * CONFIG_SYS_NAND_BLOCK_SIZE)
+#define CONFIG_ENV_OFFSET		(7 * CONFIG_SYS_NAND_BLOCK_SIZE)
 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
 #define CONFIG_ENV_IS_IN_REMOTE
 #define CONFIG_ENV_ADDR		0xffe20000
@@ -175,7 +174,7 @@ unsigned long get_board_sys_clk(unsigned long dummy);
 #define CONFIG_CHIP_SELECTS_PER_CTRL	(4 * CONFIG_DIMM_SLOTS_PER_CTLR)
 
 #define CONFIG_DDR_SPD
-#define CONFIG_FSL_DDR3
+#define CONFIG_SYS_FSL_DDR3
 
 #define CONFIG_SYS_SPD_BUS_NUM	0
 #define SPD_EEPROM_ADDRESS	0x52
@@ -511,14 +510,14 @@ unsigned long get_board_sys_clk(unsigned long dummy);
 #elif defined(CONFIG_SDCARD)
 /*
  * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
- * about 545KB (1089 blocks), Env is stored after the image, and the env size is
- * 0x2000 (16 blocks), 8 + 1089 + 16 = 1113, enlarge it to 1130.
+ * about 825KB (1650 blocks), Env is stored after the image, and the env size is
+ * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680.
  */
 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC
-#define CONFIG_SYS_QE_FMAN_FW_ADDR	(512 * 1130)
+#define CONFIG_SYS_QE_FMAN_FW_ADDR	(512 * 1680)
 #elif defined(CONFIG_NAND)
 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND
-#define CONFIG_SYS_QE_FMAN_FW_ADDR	(6 * CONFIG_SYS_NAND_BLOCK_SIZE)
+#define CONFIG_SYS_QE_FMAN_FW_ADDR	(8 * CONFIG_SYS_NAND_BLOCK_SIZE)
 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
 /*
  * Slave has no ucode locally, it can fetch this from remote. When implementing
@@ -531,7 +530,7 @@ unsigned long get_board_sys_clk(unsigned long dummy);
 #define CONFIG_SYS_QE_FMAN_FW_ADDR	0xFFE00000
 #else
 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
-#define CONFIG_SYS_QE_FMAN_FW_ADDR	0xEFF40000
+#define CONFIG_SYS_QE_FMAN_FW_ADDR	0xEFF00000
 #endif
 #define CONFIG_SYS_QE_FMAN_FW_LENGTH	0x10000
 #define CONFIG_SYS_FDT_PAD		(0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
@@ -655,7 +654,6 @@ unsigned long get_board_sys_clk(unsigned long dummy);
 #define CONFIG_CMDLINE_EDITING			/* Command-line editing */
 #define CONFIG_AUTO_COMPLETE			/* add autocompletion support */
 #define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
-#define CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt */
 #ifdef CONFIG_CMD_KGDB
 #define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size */
 #else
@@ -667,7 +665,6 @@ unsigned long get_board_sys_clk(unsigned long dummy);
 #define CONFIG_SYS_MAXARGS	16		/* max number of command args */
 /* Boot Argument Buffer Size */
 #define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE
-#define CONFIG_SYS_HZ		1000		/* decrementer freq 1ms ticks */
 
 /*
  * For booting Linux, the board info and command line data
@@ -679,7 +676,6 @@ unsigned long get_board_sys_clk(unsigned long dummy);
 
 #ifdef CONFIG_CMD_KGDB
 #define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
-#define CONFIG_KGDB_SER_INDEX	2	/* which serial port to use */
 #endif
 
 /*
@@ -746,8 +742,6 @@ unsigned long get_board_sys_clk(unsigned long dummy);
 
 #define CONFIG_BOOTCOMMAND		CONFIG_HDBOOT
 
-#ifdef CONFIG_SECURE_BOOT
 #include <asm/fsl_secure_boot.h>
-#endif
 
 #endif	/* __CONFIG_H */
diff --git a/include/configs/P3G4.h b/include/configs/P3G4.h
index 354e9d211b..ac75d3ebfa 100644
--- a/include/configs/P3G4.h
+++ b/include/configs/P3G4.h
@@ -136,7 +136,6 @@
  * Miscellaneous configurable options
  */
 #define	CONFIG_SYS_LONGHELP			/* undef to save memory		*/
-#define	CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt	*/
 #if defined(CONFIG_CMD_KGDB)
 #define	CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
 #else
@@ -150,8 +149,6 @@
 #define CONFIG_SYS_MEMTEST_END		0x00C00000	/* 4 ... 12 MB in DRAM	*/
 
 #define	CONFIG_SYS_LOAD_ADDR		0x00300000	/* default load address	*/
-
-#define	CONFIG_SYS_HZ			1000		/* decr freq: 1ms ticks	*/
 #define CONFIG_SYS_BUS_CLK		133000000	/* 133 MHz		*/
 
 #define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
diff --git a/include/configs/P4080DS.h b/include/configs/P4080DS.h
index b0cd7d5c21..2f8900834d 100644
--- a/include/configs/P4080DS.h
+++ b/include/configs/P4080DS.h
@@ -17,6 +17,12 @@
 #define CONFIG_MMC
 #define CONFIG_PCIE3
 
+#define CONFIG_CMD_SATA
+#define CONFIG_SATA_SIL
+#define CONFIG_SYS_SATA_MAX_DEVICE  2
+#define CONFIG_LIBATA
+#define CONFIG_LBA48
+
 #define CONFIG_SYS_SRIO
 #define CONFIG_SRIO1			/* SRIO port 1 */
 #define CONFIG_SRIO2			/* SRIO port 2 */
diff --git a/include/configs/PATI.h b/include/configs/PATI.h
index 732fe64d4e..d823b0f3cc 100644
--- a/include/configs/PATI.h
+++ b/include/configs/PATI.h
@@ -94,8 +94,6 @@
 
 #define	CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address		*/
 
-#define	CONFIG_SYS_HZ			1000		/* Decrementer freq: 1 ms ticks	*/
-
 #define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 1250000 }
 
 
diff --git a/include/configs/PCI405.h b/include/configs/PCI405.h
index 53e0d9fd8f..0989407fc7 100644
--- a/include/configs/PCI405.h
+++ b/include/configs/PCI405.h
@@ -20,7 +20,6 @@
  * (easy to change)
  */
 #define CONFIG_405GP		1	/* This is a PPC405 CPU		*/
-#define CONFIG_4xx		1	/* ...member of PPC4xx family	*/
 #define CONFIG_PCI405		1	/* ...on a PCI405 board		*/
 
 #define	CONFIG_SYS_TEXT_BASE	0xFFFD0000
@@ -73,7 +72,6 @@
 /*
  * Miscellaneous configurable options
  */
-#define CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt	*/
 
 #define CONFIG_SYS_HUSH_PARSER			/* use "hush" command parser	*/
 
@@ -110,8 +108,6 @@
 #define CONFIG_SYS_LOAD_ADDR	0x100000	/* default load address */
 #define CONFIG_SYS_EXTBDINFO	1		/* To use extended board_into (bd_t) */
 
-#define CONFIG_SYS_HZ		1000		/* decrementer freq: 1 ms ticks */
-
 #undef CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */
 
 #define CONFIG_VERSION_VARIABLE 1	/* include version env variable */
diff --git a/include/configs/PCI5441.h b/include/configs/PCI5441.h
index 84ef49c9c5..7ae25d7b66 100644
--- a/include/configs/PCI5441.h
+++ b/include/configs/PCI5441.h
@@ -101,7 +101,6 @@
  * If the default period is acceptable, TMRCNT can be left undefined.
  * TMRMS represents the desired mecs per tick (msecs per interrupt).
  *----------------------------------------------------------------------*/
-#define CONFIG_SYS_HZ			1000	/* Always 1000 */
 #define CONFIG_SYS_LOW_RES_TIMER
 #define CONFIG_SYS_NIOS_TMRBASE	0x00920860	/* Tick timer base addr	*/
 #define CONFIG_SYS_NIOS_TMRIRQ		3	/* Timer IRQ num */
@@ -140,7 +139,6 @@
  * MISC
  *----------------------------------------------------------------------*/
 #define	CONFIG_SYS_LONGHELP				/* Provide extended help*/
-#define	CONFIG_SYS_PROMPT		"==> "		/* Command prompt	*/
 #define	CONFIG_SYS_CBSIZE		256		/* Console I/O buf size	*/
 #define	CONFIG_SYS_MAXARGS		16		/* Max command args	*/
 #define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot arg buf size	*/
diff --git a/include/configs/PIP405.h b/include/configs/PIP405.h
index c67e61f79a..a6f505aaa9 100644
--- a/include/configs/PIP405.h
+++ b/include/configs/PIP405.h
@@ -17,7 +17,6 @@
  * (easy to change)
  ***********************************************************/
 #define CONFIG_405GP		1	/* This is a PPC405 CPU		*/
-#define CONFIG_4xx		1	/* ...member of PPC4xx family	*/
 #define CONFIG_PIP405		1	/* ...on a PIP405 board		*/
 
 #define	CONFIG_SYS_TEXT_BASE	0xFFF80000
@@ -143,7 +142,6 @@
  * Miscellaneous configurable options
  **********************************************************/
 #define CONFIG_SYS_LONGHELP			/* undef to save memory		*/
-#define CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt	*/
 #if defined(CONFIG_CMD_KGDB)
 #define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
 #else
@@ -173,8 +171,6 @@
 #define CONFIG_SYS_LOAD_ADDR		0x400000	/* default load address */
 #define CONFIG_SYS_EXTBDINFO		1	/* To use extended board_into (bd_t) */
 
-#define CONFIG_SYS_HZ		1000		/* decrementer freq: 1 ms ticks */
-
 /*-----------------------------------------------------------------------
  * PCI stuff
  *-----------------------------------------------------------------------
@@ -356,7 +352,6 @@
  ************************************************************/
 #if defined(CONFIG_CMD_KGDB)
 #define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
-#define CONFIG_KGDB_SER_INDEX	2	/* which serial port to use */
 #endif
 
 /************************************************************
diff --git a/include/configs/PK1C20.h b/include/configs/PK1C20.h
index afa273d89f..e7d08647fc 100644
--- a/include/configs/PK1C20.h
+++ b/include/configs/PK1C20.h
@@ -111,7 +111,6 @@
  * If the default period is acceptable, TMRCNT can be left undefined.
  * TMRMS represents the desired mecs per tick (msecs per interrupt).
  *----------------------------------------------------------------------*/
-#define CONFIG_SYS_HZ			1000	/* Always 1000 */
 #define CONFIG_SYS_LOW_RES_TIMER
 #define CONFIG_SYS_NIOS_TMRBASE	0x02120820	/* Tick timer base addr */
 #define CONFIG_SYS_NIOS_TMRIRQ		3	/* Timer IRQ num */
@@ -213,7 +212,6 @@
  * MISC
  *----------------------------------------------------------------------*/
 #define CONFIG_SYS_LONGHELP				/* Provide extended help*/
-#define CONFIG_SYS_PROMPT		"==> "		/* Command prompt	*/
 #define CONFIG_SYS_CBSIZE		256		/* Console I/O buf size */
 #define CONFIG_SYS_MAXARGS		16		/* Max command args	*/
 #define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot arg buf size	*/
diff --git a/include/configs/PLU405.h b/include/configs/PLU405.h
index 912bcf59f8..8705161158 100644
--- a/include/configs/PLU405.h
+++ b/include/configs/PLU405.h
@@ -18,7 +18,6 @@
  */
 
 #define CONFIG_405EP		1	/* This is a PPC405 CPU		*/
-#define CONFIG_4xx		1	/* ...member of PPC4xx family	*/
 #define CONFIG_PLU405		1	/* ...on a PLU405 board		*/
 
 #define	CONFIG_SYS_TEXT_BASE	0xFFF80000
@@ -95,7 +94,6 @@
  * Miscellaneous configurable options
  */
 #define CONFIG_SYS_LONGHELP			/* undef to save memory		*/
-#define CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt	*/
 
 #undef	CONFIG_SYS_HUSH_PARSER			/* use "hush" command parser	*/
 
@@ -134,8 +132,6 @@
 #define CONFIG_SYS_LOAD_ADDR	0x100000	/* default load address */
 #define CONFIG_SYS_EXTBDINFO	1		/* To use extended board_into (bd_t) */
 
-#define CONFIG_SYS_HZ		1000		/* decrementer freq: 1 ms ticks */
-
 #define CONFIG_CMDLINE_EDITING	1	/* add command line history	*/
 #define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */
 #define CONFIG_BOOTDELAY	3	/* autoboot after 3 seconds	*/
diff --git a/include/configs/PM520.h b/include/configs/PM520.h
index 218dca0266..de46216422 100644
--- a/include/configs/PM520.h
+++ b/include/configs/PM520.h
@@ -14,8 +14,7 @@
  */
 
 #define CONFIG_MPC5200
-#define CONFIG_MPC5xxx		1	/* This is an MPC5xxx CPU */
-#define CONFIG_PM520		1	/* ... on PM520 board */
+#define CONFIG_PM520		1	/* PM520 board */
 
 #define	CONFIG_SYS_TEXT_BASE	0xfff00000
 
@@ -251,7 +250,6 @@
  * Miscellaneous configurable options
  */
 #define CONFIG_SYS_LONGHELP			/* undef to save memory	    */
-#define CONFIG_SYS_PROMPT		"=> "	/* Monitor Command Prompt   */
 #if defined(CONFIG_CMD_KGDB)
 #define CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size  */
 #else
@@ -266,8 +264,6 @@
 
 #define CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address */
 
-#define CONFIG_SYS_HZ			1000	/* decrementer freq: 1 ms ticks */
-
 #define CONFIG_SYS_CACHELINE_SIZE	32	/* For MPC5xxx CPUs */
 #if defined(CONFIG_CMD_KGDB)
 #  define CONFIG_SYS_CACHELINE_SHIFT	5	/* log base 2 of the above value */
diff --git a/include/configs/PM826.h b/include/configs/PM826.h
index b466513ea3..6416ad5227 100644
--- a/include/configs/PM826.h
+++ b/include/configs/PM826.h
@@ -19,7 +19,6 @@
  * (easy to change)
  */
 
-#define CONFIG_MPC8260		1	/* This is a MPC8260 CPU	*/
 #define CONFIG_PM826		1	/* ...on a PM8260 module	*/
 #define CONFIG_CPM2		1	/* Has a CPM2 */
 
@@ -168,7 +167,6 @@
  * Miscellaneous configurable options
  */
 #define	CONFIG_SYS_LONGHELP			/* undef to save memory		*/
-#define	CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt	*/
 #if defined(CONFIG_CMD_KGDB)
 #define	CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
 #else
@@ -183,8 +181,6 @@
 
 #define	CONFIG_SYS_LOAD_ADDR	0x100000	/* default load address	*/
 
-#define	CONFIG_SYS_HZ		1000		/* decrementer freq: 1 ms ticks	*/
-
 #define	CONFIG_SYS_RESET_ADDRESS 0xFDFFFFFC	/* "bad" address		*/
 
 /*
diff --git a/include/configs/PM828.h b/include/configs/PM828.h
index 8ca2400a08..e17fbfbbf8 100644
--- a/include/configs/PM828.h
+++ b/include/configs/PM828.h
@@ -19,7 +19,6 @@
  * (easy to change)
  */
 
-#define CONFIG_MPC8260		1	/* This is a MPC8260 CPU	*/
 #define CONFIG_PM828		1	/* ...on a PM828 module */
 #define CONFIG_CPM2		1	/* Has a CPM2 */
 
@@ -168,7 +167,6 @@
  * Miscellaneous configurable options
  */
 #define CONFIG_SYS_LONGHELP			/* undef to save memory		*/
-#define CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt	*/
 #if defined(CONFIG_CMD_KGDB)
 #define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
 #else
@@ -183,8 +181,6 @@
 
 #define CONFIG_SYS_LOAD_ADDR	0x100000	/* default load address */
 
-#define CONFIG_SYS_HZ		1000		/* decrementer freq: 1 ms ticks */
-
 #define CONFIG_SYS_RESET_ADDRESS 0xFDFFFFFC	/* "bad" address		*/
 
 /*
diff --git a/include/configs/PMC405.h b/include/configs/PMC405.h
index 67a96d29d4..c68d9a6ec6 100644
--- a/include/configs/PMC405.h
+++ b/include/configs/PMC405.h
@@ -13,7 +13,6 @@
  */
 
 #define CONFIG_405GP		1	/* This is a PPC405 CPU		*/
-#define CONFIG_4xx		1	/* ...member of PPC4xx family	*/
 #define CONFIG_PMC405		1	/* ...on a PMC405 board		*/
 
 #define	CONFIG_SYS_TEXT_BASE	0xFFF80000
@@ -90,7 +89,6 @@
  * Miscellaneous configurable options
  */
 #define CONFIG_SYS_LONGHELP			/* undef to save memory */
-#define CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt */
 
 #undef CONFIG_SYS_HUSH_PARSER			/* use "hush" command parser */
 
@@ -128,8 +126,6 @@
 #define CONFIG_SYS_LOAD_ADDR	0x100000	/* default load address */
 #define CONFIG_SYS_EXTBDINFO	1	/* To use extended board_into (bd_t) */
 
-#define CONFIG_SYS_HZ		1000	/* decrementer freq: 1 ms ticks */
-
 #define CONFIG_CMDLINE_EDITING	1	/* add command line history */
 #define CONFIG_LOOPW		1	/* enable loopw command */
 
diff --git a/include/configs/PMC405DE.h b/include/configs/PMC405DE.h
index 3d6dc91a0b..94b95475a8 100644
--- a/include/configs/PMC405DE.h
+++ b/include/configs/PMC405DE.h
@@ -9,7 +9,6 @@
 #define __CONFIG_H
 
 #define CONFIG_405EP		1	/* This is a PPC405 CPU		*/
-#define CONFIG_4xx		1	/* ...member of PPC4xx family	*/
 #define CONFIG_PMC405DE		1	/* ...on a PMC405DE board	*/
 
 #define	CONFIG_SYS_TEXT_BASE	0xFFFC0000
@@ -79,7 +78,6 @@
  * Miscellaneous configurable options
  */
 #define CONFIG_SYS_LONGHELP
-#define CONFIG_SYS_PROMPT	"=> "	/* Monitor Command Prompt */
 
 #define CONFIG_SYS_CBSIZE	256	/* Console I/O Buffer Size */
 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
@@ -104,8 +102,6 @@
 #define CONFIG_SYS_LOAD_ADDR	0x100000	/* default load address */
 #define CONFIG_SYS_EXTBDINFO	1	/* To use extended board_into (bd_t) */
 
-#define CONFIG_SYS_HZ		1000	/* decrementer freq: 1 ms ticks */
-
 #define CONFIG_CMDLINE_EDITING	1	/* add command line history     */
 #define CONFIG_LOOPW		1	/* enable loopw command         */
 #define CONFIG_MX_CYCLIC	1	/* enable mdc/mwc commands      */
diff --git a/include/configs/PMC440.h b/include/configs/PMC440.h
index a54c099ce4..c5e2f164ce 100644
--- a/include/configs/PMC440.h
+++ b/include/configs/PMC440.h
@@ -24,7 +24,6 @@
  *----------------------------------------------------------------------*/
 #define CONFIG_440EPX		1	/* Specific PPC440EPx   */
 #define CONFIG_440		1	/* ... PPC440 family    */
-#define CONFIG_4xx		1	/* ... PPC4xx family    */
 
 #ifndef CONFIG_SYS_TEXT_BASE
 #define CONFIG_SYS_TEXT_BASE	0xFFF90000
@@ -96,12 +95,7 @@
 /*-----------------------------------------------------------------------
  * Environment
  *----------------------------------------------------------------------*/
-#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
 #define CONFIG_ENV_IS_IN_EEPROM	1	/* use FLASH for environment vars */
-#else
-#define CONFIG_ENV_IS_IN_NAND	1	/* use NAND for environment vars */
-#define CONFIG_ENV_IS_EMBEDDED	1	/* use embedded environment */
-#endif
 
 /*-----------------------------------------------------------------------
  * RTC
@@ -143,69 +137,10 @@
 #define CONFIG_ENV_SIZE		0x1000	/* 4096 bytes may be used for env vars */
 #endif
 
-/*
- * IPL (Initial Program Loader, integrated inside CPU)
- * Will load first 4k from NAND (SPL) into cache and execute it from there.
- *
- * SPL (Secondary Program Loader)
- * Will load special U-Boot version (NUB) from NAND and execute it. This SPL
- * has to fit into 4kByte. It sets up the CPU and configures the SDRAM
- * controller and the NAND controller so that the special U-Boot image can be
- * loaded from NAND to SDRAM.
- *
- * NUB (NAND U-Boot)
- * This NAND U-Boot (NUB) is a special U-Boot version which can be started
- * from RAM. Therefore it mustn't (re-)configure the SDRAM controller.
- *
- * On 440EPx the SPL is copied to SDRAM before the NAND controller is
- * set up. While still running from cache, I experienced problems accessing
- * the NAND controller.	sr - 2006-08-25
- */
-#if defined (CONFIG_NAND_U_BOOT)
-#define CONFIG_SYS_NAND_BOOT_SPL_SRC	0xfffff000	/* SPL location                 */
-#define CONFIG_SYS_NAND_BOOT_SPL_SIZE	(4 << 10)	/* SPL size                     */
-#define CONFIG_SYS_NAND_BOOT_SPL_DST	(CONFIG_SYS_OCM_BASE + (12 << 10)) /* Copy SPL here    */
-#define CONFIG_SYS_NAND_U_BOOT_DST	0x01000000	/* Load NUB to this addr        */
-#define CONFIG_SYS_NAND_U_BOOT_START	CONFIG_SYS_NAND_U_BOOT_DST /* Start NUB from this addr */
-#define CONFIG_SYS_NAND_BOOT_SPL_DELTA	(CONFIG_SYS_NAND_BOOT_SPL_SRC - CONFIG_SYS_NAND_BOOT_SPL_DST)
-
-/*
- * Define the partitioning of the NAND chip (only RAM U-Boot is needed here)
- */
-#define CONFIG_SYS_NAND_U_BOOT_OFFS	(16 << 10)	/* Offset to RAM U-Boot image   */
-#define CONFIG_SYS_NAND_U_BOOT_SIZE	(384 << 10)	/* Size of RAM U-Boot image     */
-
-/*
- * Now the NAND chip has to be defined (no autodetection used!)
- */
-#define CONFIG_SYS_NAND_PAGE_SIZE	512	/* NAND chip page size          */
-#define CONFIG_SYS_NAND_BLOCK_SIZE	(16 << 10) /* NAND chip block size      */
-#define CONFIG_SYS_NAND_PAGE_COUNT	32	/* NAND chip page count         */
-#define CONFIG_SYS_NAND_BAD_BLOCK_POS	5	/* Location of bad block marker */
-#undef CONFIG_SYS_NAND_4_ADDR_CYCLE		/* No fourth addr used (<=32MB) */
-
-#define CONFIG_SYS_NAND_ECCSIZE	256
-#define CONFIG_SYS_NAND_ECCBYTES	3
-#define CONFIG_SYS_NAND_OOBSIZE	16
-#define CONFIG_SYS_NAND_ECCPOS		{0, 1, 2, 3, 6, 7}
-#endif
-
-#ifdef CONFIG_ENV_IS_IN_NAND
-/*
- * For NAND booting the environment is embedded in the U-Boot image. Please take
- * look at the file board/amcc/sequoia/u-boot-nand.lds for details.
- */
-#define CONFIG_ENV_SIZE		CONFIG_SYS_NAND_BLOCK_SIZE
-#define CONFIG_ENV_OFFSET		(CONFIG_SYS_NAND_U_BOOT_OFFS + CONFIG_ENV_SIZE)
-#define CONFIG_ENV_OFFSET_REDUND	(CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
-#endif
-
 /*-----------------------------------------------------------------------
  * DDR SDRAM
  *----------------------------------------------------------------------*/
-#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
 #define CONFIG_DDR_DATA_EYE	/* use DDR2 optimization        */
-#endif
 #define CONFIG_SYS_MEM_TOP_HIDE	(4 << 10) /* don't use last 4kbytes */
 						  /* 440EPx errata CHIP 11 */
 
@@ -372,7 +307,6 @@
  * Miscellaneous configurable options
  *----------------------------------------------------------------------*/
 #define CONFIG_SYS_LONGHELP			/* undef to save memory         */
-#define CONFIG_SYS_PROMPT		"=> "	/* Monitor Command Prompt       */
 #if defined(CONFIG_CMD_KGDB)
 #define CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size      */
 #else
@@ -388,8 +322,6 @@
 #define CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address      */
 #define CONFIG_SYS_EXTBDINFO		1	/* To use extended board_into (bd_t) */
 
-#define CONFIG_SYS_HZ			1000	/* decrementer freq: 1 ms ticks */
-
 #define CONFIG_CMDLINE_EDITING	1	/* add command line history     */
 #define CONFIG_LOOPW		1	/* enable loopw command         */
 #define CONFIG_MX_CYCLIC	1	/* enable mdc/mwc commands      */
@@ -452,7 +384,6 @@
 /*
  * On Sequoia CS0 and CS3 are switched when configuring for NAND booting
  */
-#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
 #define CONFIG_SYS_NAND_CS		2	/* NAND chip connected to CSx   */
 
 /* Memory Bank 0 (NOR-FLASH) initialization */
@@ -462,16 +393,6 @@
 /* Memory Bank 2 (NAND-FLASH) initialization */
 #define CONFIG_SYS_EBC_PB2AP		0x018003c0
 #define CONFIG_SYS_EBC_PB2CR		(CONFIG_SYS_NAND_ADDR | 0x1c000)
-#else
-#define CONFIG_SYS_NAND_CS		0	/* NAND chip connected to CSx   */
-/* Memory Bank 2 (NOR-FLASH) initialization */
-#define CONFIG_SYS_EBC_PB2AP		0x03017200
-#define CONFIG_SYS_EBC_PB2CR		(CONFIG_SYS_FLASH_BASE | 0xda000)
-
-/* Memory Bank 0 (NAND-FLASH) initialization */
-#define CONFIG_SYS_EBC_PB0AP		0x018003c0
-#define CONFIG_SYS_EBC_PB0CR		(CONFIG_SYS_NAND_ADDR | 0x1c000)
-#endif
 
 /* Memory Bank 1 (RESET) initialization */
 #define CONFIG_SYS_EBC_PB1AP		0x7f817200 /* 0x03017200 */
@@ -495,7 +416,6 @@
 
 #if defined(CONFIG_CMD_KGDB)
 #define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
-#define CONFIG_KGDB_SER_INDEX	2	/* which serial port to use */
 #endif
 
 /* pass open firmware flat tree */
diff --git a/include/configs/PN62.h b/include/configs/PN62.h
deleted file mode 100644
index fbf8a996ce..0000000000
--- a/include/configs/PN62.h
+++ /dev/null
@@ -1,287 +0,0 @@
-/*
- * (C) Copyright 2002
- * Wolfgang Grandegger, DENX Software Engineering, wg@denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-/* ------------------------------------------------------------------------- */
-
-/*
- * board/config.h - configuration options, board specific
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_MPC824X		1
-#define CONFIG_MPC8240		1
-#define CONFIG_PN62		1
-
-#define	CONFIG_SYS_TEXT_BASE	0xFFF00000
-
-#define CONFIG_CONS_INDEX	1
-
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_PCI
-#define CONFIG_CMD_BSP
-
-#undef CONFIG_CMD_FLASH
-#undef CONFIG_CMD_IMLS
-#undef CONFIG_CMD_LOADS
-#undef CONFIG_CMD_SAVEENV
-#undef CONFIG_CMD_SOURCE
-
-
-#define CONFIG_BAUDRATE		19200	/* console baudrate		*/
-
-#define CONFIG_BOOTDELAY	1	/* autoboot after n seconds	*/
-
-#define	CONFIG_CLOCKS_IN_MHZ	1	/* clocks passsed to Linux in MHz */
-
-#define CONFIG_SERVERIP		10.0.0.201
-#define CONFIG_IPADDR		10.0.0.200
-#define CONFIG_ROOTPATH		"/opt/eldk/ppc_82xx"
-#define CONFIG_NETMASK		255.255.255.0
-#undef CONFIG_BOOTARGS
-#if 0
-/* Boot Linux with NFS root filesystem */
-#define CONFIG_BOOTCOMMAND \
-			"setenv verify y;" \
-			"setenv bootargs console=ttyS0,19200 mem=31M quiet " \
-			"root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
-			"ip=${ipaddr}:${serverip}::${netmask}:pn62:eth0:off;" \
-			"loadp 100000; bootm"
-			/* "tftpboot 100000 uImage; bootm" */
-#else
-/* Boot Linux with RAMdisk based filesystem (initrd, BusyBox) */
-#define CONFIG_BOOTCOMMAND \
-			"setenv verify n;" \
-			"setenv bootargs console=ttyS0,19200 mem=31M quiet " \
-			"root=/dev/ram rw " \
-			"ip=${ipaddr}:${serverip}::${netmask}:pn62:eth0:off;" \
-			"loadp 200000; bootm"
-#endif
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP		1		/* undef to save memory		*/
-#define CONFIG_SYS_PROMPT		"=> "		/* Monitor Command Prompt	*/
-#define CONFIG_SYS_CBSIZE		256		/* Console I/O Buffer Size	*/
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)	/* Print Buffer Size	*/
-#define CONFIG_SYS_MAXARGS		16		/* max number of command args	*/
-#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
-#define CONFIG_SYS_LOAD_ADDR		0x00100000	/* default load address		*/
-#define CONFIG_SYS_HZ			1000		/* decrementer freq: 1 ms ticks */
-
-#define CONFIG_PRAM		1024		/* reserve 1 MB protected RAM	*/
-
-#define CONFIG_MISC_INIT_R	1		/* call misc_init_r() on init	*/
-
-#define CONFIG_HAS_ETH1		1		/* add support for eth1addr	*/
-
-#define CONFIG_SHOW_BOOT_PROGRESS 1		/* Show boot progress on LEDs   */
-
-/*
- * PCI stuff
- */
-#define CONFIG_PCI				/* include pci support		*/
-#define CONFIG_PCI_INDIRECT_BRIDGE	/* indirect PCI bridge support */
-#define CONFIG_PCI_PNP				/* we need Plug 'n Play		*/
-#if 0
-#define CONFIG_PCI_SCAN_SHOW			/* show PCI auto-scan at boot	*/
-#endif
-
-/*
- * Networking stuff
- */
-
-#define CONFIG_PCNET				/* there are 2 AMD PCnet 79C973	*/
-#define CONFIG_PCNET_79C973
-
-#define _IO_BASE		0xfe000000	/* points to PCI I/O space	*/
-
-
-/*
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
- */
-#define CONFIG_SYS_SDRAM_BASE		0x00000000
-#define CONFIG_SYS_MAX_RAM_SIZE	0x10000000
-
-#define CONFIG_SYS_RESET_ADDRESS	0xfff00100
-
-#undef	CONFIG_SYS_RAMBOOT
-#define CONFIG_SYS_MONITOR_LEN		0x00030000
-#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE
-
-
-#define CONFIG_SYS_INIT_RAM_ADDR	0x40000000
-#define CONFIG_SYS_INIT_RAM_SIZE	0x1000
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-
-
-#define CONFIG_SYS_NO_FLASH		1		/* There is no FLASH memory	*/
-
-#define CONFIG_ENV_IS_NOWHERE	1		/* Store ENV in memory only	*/
-#define CONFIG_ENV_OFFSET		0x00004000	/* Offset of Environment Sector */
-#define CONFIG_ENV_SIZE		0x00002000	/* Total Size of Environment Sector */
-
-#define CONFIG_SYS_MALLOC_LEN		(512 << 10)	/* Reserve 512 kB for malloc()	*/
-
-#define CONFIG_SYS_MEMTEST_START	0x00004000	/* memtest works on		*/
-#define CONFIG_SYS_MEMTEST_END		0x01f00000	/* 0 ... 32 MB in DRAM		*/
-
-/*
- * Serial port configuration
- */
-
-#define CONFIG_SYS_NS16550
-#define CONFIG_SYS_NS16550_SERIAL
-
-#define CONFIG_SYS_NS16550_REG_SIZE	1
-
-#define CONFIG_SYS_NS16550_CLK		1843200
-
-#define CONFIG_SYS_NS16550_COM1	0xff800008
-#define CONFIG_SYS_NS16550_COM2	0xff800000
-
-/*
- * Low Level Configuration Settings
- * (address mappings, register initial values, etc.)
- * You should know what you are doing if you make changes here.
- */
-
-#define CONFIG_SYS_CLK_FREQ  33333333	/* external frequency to pll */
-#define CONFIG_PLL_PCI_TO_MEM_MULTIPLIER  3
-
-#define CONFIG_SYS_EUMB_ADDR		0xFCE00000
-
-/* MCCR1 */
-#define CONFIG_SYS_ROMNAL		3	/* rom/flash next access time		*/
-#define CONFIG_SYS_ROMFAL		7	/* rom/flash access time		*/
-
-/* MCCR2 */
-#define CONFIG_SYS_ASRISE		6	/* ASRISE in clocks			*/
-#define CONFIG_SYS_ASFALL		12	/* ASFALL in clocks			*/
-#define CONFIG_SYS_REFINT		5600	/* REFINT in clocks			*/
-
-/* MCCR3 */
-#define CONFIG_SYS_BSTOPRE		0x3cf	/* Burst To Precharge			*/
-#define CONFIG_SYS_REFREC		2	/* Refresh to activate interval		*/
-#define CONFIG_SYS_RDLAT		3	/* data latency from read command	*/
-
-/* MCCR4 */
-#define CONFIG_SYS_PRETOACT		1	/* Precharge to activate interval	*/
-#define CONFIG_SYS_ACTTOPRE		3	/* Activate to Precharge interval	*/
-#define CONFIG_SYS_ACTORW		2	/* Activate to R/W			*/
-#define CONFIG_SYS_SDMODE_CAS_LAT	2	/* SDMODE CAS latency			*/
-#define CONFIG_SYS_SDMODE_WRAP		0	/* SDMODE Wrap type			*/
-#define CONFIG_SYS_SDMODE_BURSTLEN	2	/* SDMODE Burst length 2=4, 3=8		*/
-#define CONFIG_SYS_REGISTERD_TYPE_BUFFER   1
-
-/* Memory bank settings:
- *
- * only bits 20-29 are actually used from these vales to set the
- * start/qend address the upper two bits will be 0, and the lower 20
- * bits will be set to 0x00000 for a start address, or 0xfffff for an
- * end address
- */
-#define CONFIG_SYS_BANK0_START		0x00000000
-#define CONFIG_SYS_BANK0_END		(CONFIG_SYS_MAX_RAM_SIZE - 1)
-#define CONFIG_SYS_BANK0_ENABLE	1
-#define CONFIG_SYS_BANK1_START		0x00000000
-#define CONFIG_SYS_BANK1_END		0x00000000
-#define CONFIG_SYS_BANK1_ENABLE	0
-#define CONFIG_SYS_BANK2_START		0x00000000
-#define CONFIG_SYS_BANK2_END		0x00000000
-#define CONFIG_SYS_BANK2_ENABLE	0
-#define CONFIG_SYS_BANK3_START		0x00000000
-#define CONFIG_SYS_BANK3_END		0x00000000
-#define CONFIG_SYS_BANK3_ENABLE	0
-#define CONFIG_SYS_BANK4_START		0x00000000
-#define CONFIG_SYS_BANK4_END		0x00000000
-#define CONFIG_SYS_BANK4_ENABLE	0
-#define CONFIG_SYS_BANK5_START		0x00000000
-#define CONFIG_SYS_BANK5_END		0x00000000
-#define CONFIG_SYS_BANK5_ENABLE	0
-#define CONFIG_SYS_BANK6_START		0x00000000
-#define CONFIG_SYS_BANK6_END		0x00000000
-#define CONFIG_SYS_BANK6_ENABLE	0
-#define CONFIG_SYS_BANK7_START		0x00000000
-#define CONFIG_SYS_BANK7_END		0x00000000
-#define CONFIG_SYS_BANK7_ENABLE	0
-
-/*
- * Memory bank enable bitmask, specifying which of the banks defined above
- * are actually present. MSB is for bank #7, LSB is for bank #0.
- */
-#define CONFIG_SYS_BANK_ENABLE		0x01
-
-#define CONFIG_SYS_ODCR		0xff	/* configures line driver impedances,	*/
-					/* see 8240 book for bit definitions	*/
-#define CONFIG_SYS_PGMAX		0x32	/* how long the 8240 retains the	*/
-					/* currently accessed page in memory	*/
-					/* see 8240 book for details		*/
-
-/* SDRAM 0 - 256MB */
-#define CONFIG_SYS_IBAT0L	(CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT0U	(CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
-
-#define CONFIG_SYS_IBAT1L	(CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT1U	(CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
-
-/* PCI memory space */
-#define CONFIG_SYS_IBAT2L	(0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
-#define CONFIG_SYS_IBAT2U	(0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP)
-
-/* Config addrs, etc */
-#define CONFIG_SYS_IBAT3L	(0xF0000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
-#define CONFIG_SYS_IBAT3U	(0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
-
-#define CONFIG_SYS_DBAT0L	CONFIG_SYS_IBAT0L
-#define CONFIG_SYS_DBAT0U	CONFIG_SYS_IBAT0U
-#define CONFIG_SYS_DBAT1L	CONFIG_SYS_IBAT1L
-#define CONFIG_SYS_DBAT1U	CONFIG_SYS_IBAT1U
-#define CONFIG_SYS_DBAT2L	CONFIG_SYS_IBAT2L
-#define CONFIG_SYS_DBAT2U	CONFIG_SYS_IBAT2U
-#define CONFIG_SYS_DBAT3L	CONFIG_SYS_IBAT3L
-#define CONFIG_SYS_DBAT3U	CONFIG_SYS_IBAT3U
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
-
-/*
- * Cache Configuration
- */
-#define CONFIG_SYS_CACHELINE_SIZE	32	/* For MPC8240 CPU			*/
-#if defined(CONFIG_CMD_KGDB)
-#  define CONFIG_SYS_CACHELINE_SHIFT	5	/* log base 2 of the above value */
-#endif
-
-#endif	/* __CONFIG_H */
diff --git a/include/configs/PPChameleonEVB.h b/include/configs/PPChameleonEVB.h
index bdfe3c1b27..e277d0d933 100644
--- a/include/configs/PPChameleonEVB.h
+++ b/include/configs/PPChameleonEVB.h
@@ -59,7 +59,6 @@
  */
 
 #define CONFIG_405EP		1	/* This is a PPC405 CPU		*/
-#define CONFIG_4xx		1	/* ...member of PPC4xx family	*/
 #define CONFIG_PPCHAMELEONEVB	1	/* ...on a PPChameleonEVB board */
 
 #define	CONFIG_SYS_TEXT_BASE	0xFFFB0000	/* Reserve 320 kB for Monitor */
@@ -157,7 +156,6 @@
  * Miscellaneous configurable options
  */
 #define CONFIG_SYS_LONGHELP			/* undef to save memory		*/
-#define CONFIG_SYS_PROMPT		"=> "	/* Monitor Command Prompt	*/
 
 #undef	CONFIG_SYS_HUSH_PARSER			/* use "hush" command parser	*/
 
@@ -194,8 +192,6 @@
 #define CONFIG_SYS_LOAD_ADDR	0x100000	/* default load address */
 #define CONFIG_SYS_EXTBDINFO	1		/* To use extended board_into (bd_t) */
 
-#define CONFIG_SYS_HZ		1000		/* decrementer freq: 1 ms ticks */
-
 #define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */
 
 /*-----------------------------------------------------------------------
diff --git a/include/configs/QS823.h b/include/configs/QS823.h
index d712828245..6733460425 100644
--- a/include/configs/QS823.h
+++ b/include/configs/QS823.h
@@ -218,7 +218,6 @@
  * Miscellaneous configurable options
  */
 #define CONFIG_SYS_LONGHELP				/* undef to save memory */
-#define CONFIG_SYS_PROMPT		"=> "		/* Monitor Command Prompt */
 
 #define CONFIG_SYS_HUSH_PARSER		1		/* use "hush" command parser */
 
@@ -236,8 +235,6 @@
 
 #define CONFIG_SYS_LOAD_ADDR		0x400000	/* default load address */
 
-#define CONFIG_SYS_HZ			1000		/* decrementer freq: 1 ms ticks */
-
 /*-----------------------------------------------------------------------
  * Low Level Configuration Settings
  * (address mappings, register initial values, etc.)
diff --git a/include/configs/QS850.h b/include/configs/QS850.h
index 3229095ddf..f11421387c 100644
--- a/include/configs/QS850.h
+++ b/include/configs/QS850.h
@@ -218,7 +218,6 @@
  * Miscellaneous configurable options
  */
 #define CONFIG_SYS_LONGHELP				/* undef to save memory */
-#define CONFIG_SYS_PROMPT		"=> "		/* Monitor Command Prompt */
 
 #define CONFIG_SYS_HUSH_PARSER		1		/* use "hush" command parser */
 
@@ -236,8 +235,6 @@
 
 #define CONFIG_SYS_LOAD_ADDR		0x400000	/* default load address */
 
-#define CONFIG_SYS_HZ			1000		/* decrementer freq: 1 ms ticks */
-
 /*-----------------------------------------------------------------------
  * Low Level Configuration Settings
  * (address mappings, register initial values, etc.)
diff --git a/include/configs/QS860T.h b/include/configs/QS860T.h
index 7c77c6b854..9958c09d71 100644
--- a/include/configs/QS860T.h
+++ b/include/configs/QS860T.h
@@ -127,7 +127,6 @@ CONFIG_SPI
  * Miscellaneous configurable options
  */
 #define CONFIG_SYS_LONGHELP				/* undef to save memory */
-#define CONFIG_SYS_PROMPT		"=> "		/* Monitor Command Prompt */
 
 #define CONFIG_SYS_HUSH_PARSER		1		/* use "hush" command parser */
 
@@ -146,8 +145,6 @@ CONFIG_SPI
 
 #define CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address */
 
-#define CONFIG_SYS_HZ			1000		/* decrementer freq: 1 ms ticks */
-
 /*-----------------------------------------------------------------------
  * Low Level Configuration Settings
  * (address mappings, register initial values, etc.)
diff --git a/include/configs/R360MPI.h b/include/configs/R360MPI.h
index efe699538c..009d1cf976 100644
--- a/include/configs/R360MPI.h
+++ b/include/configs/R360MPI.h
@@ -134,7 +134,6 @@
 #define CONFIG_SYS_CONSOLE_IS_IN_ENV	1	/* must set console from env	*/
 
 #define	CONFIG_SYS_LONGHELP			/* undef to save memory		*/
-#define	CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt	*/
 #if defined(CONFIG_CMD_KGDB)
 #define	CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
 #else
@@ -149,8 +148,6 @@
 
 #define	CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address	*/
 
-#define	CONFIG_SYS_HZ		1000		/* decrementer freq: 1 ms ticks	*/
-
 /*
  * JFFS2 partitions
  */
diff --git a/include/configs/RBC823.h b/include/configs/RBC823.h
index 7b10d289b9..e7e061cb3e 100644
--- a/include/configs/RBC823.h
+++ b/include/configs/RBC823.h
@@ -119,7 +119,6 @@
  * Miscellaneous configurable options
  */
 #define	CONFIG_SYS_LONGHELP			/* undef to save memory		*/
-#define	CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt	*/
 #if defined(CONFIG_CMD_KGDB)
 #define	CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
 #else
@@ -134,8 +133,6 @@
 
 #define	CONFIG_SYS_LOAD_ADDR		0x0100000	/* default load address	*/
 
-#define	CONFIG_SYS_HZ		1000		/* decrementer freq: 1 ms ticks	*/
-
 /*
  * Low Level Configuration Settings
  * (address mappings, register initial values, etc.)
diff --git a/include/configs/RPXClassic.h b/include/configs/RPXClassic.h
index 6ba8a02bcb..0f07d0cfe9 100644
--- a/include/configs/RPXClassic.h
+++ b/include/configs/RPXClassic.h
@@ -101,7 +101,6 @@
  */
 #define CONFIG_SYS_RESET_ADDRESS	0x80000000
 #define	CONFIG_SYS_LONGHELP			/* undef to save memory		*/
-#define	CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt	*/
 #if defined(CONFIG_CMD_KGDB)
 #define	CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
 #else
@@ -116,8 +115,6 @@
 
 #define	CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address	*/
 
-#define	CONFIG_SYS_HZ		1000		/* decrementer freq: 1 ms ticks	*/
-
 /*
  * Low Level Configuration Settings
  * (address mappings, register initial values, etc.)
diff --git a/include/configs/RPXlite.h b/include/configs/RPXlite.h
index ada7e145c0..a28230a5d7 100644
--- a/include/configs/RPXlite.h
+++ b/include/configs/RPXlite.h
@@ -98,7 +98,6 @@
  * Miscellaneous configurable options
  */
 #define	CONFIG_SYS_LONGHELP			/* undef to save memory		*/
-#define	CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt	*/
 #if defined(CONFIG_CMD_KGDB)
 #define	CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
 #else
@@ -115,8 +114,6 @@
 
 #define	CONFIG_SYS_LOAD_ADDR		0x400000	/* default load address	*/
 
-#define	CONFIG_SYS_HZ			1000		/* decrementer freq: 1 ms ticks	*/
-
 /*
  * Low Level Configuration Settings
  * (address mappings, register initial values, etc.)
diff --git a/include/configs/RPXlite_DW.h b/include/configs/RPXlite_DW.h
index ffc84d2901..50c82c68eb 100644
--- a/include/configs/RPXlite_DW.h
+++ b/include/configs/RPXlite_DW.h
@@ -162,8 +162,6 @@
 #define CONFIG_SYS_MEMTEST_END		0x00C0000	/* 4 ... 12 MB in DRAM	*/
 #define CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address */
 
-#define CONFIG_SYS_HZ		1000		/* decrementer freq: 1 ms ticks */
-
 /*
  * Low Level Configuration Settings
  * (address mappings, register initial values, etc.)
diff --git a/include/configs/RPXsuper.h b/include/configs/RPXsuper.h
index d4d3d5738d..f5e0968011 100644
--- a/include/configs/RPXsuper.h
+++ b/include/configs/RPXsuper.h
@@ -148,7 +148,6 @@
 #define CONFIG_SYS_LONGHELP
 
 /* Monitor Command Prompt       */
-#define CONFIG_SYS_PROMPT              "=> "
 
 
 /*
@@ -185,7 +184,6 @@
  *
  *****************************************************************************/
 
-#define CONFIG_MPC8260          1       /* This is an MPC8260 CPU   */
 #define CONFIG_RPXSUPER         1       /* on an Embedded Planet RPX Super Board  */
 #define CONFIG_CPM2		1	/* Has a CPM2 */
 
@@ -214,7 +212,6 @@
 #define	CONFIG_CLOCKS_IN_MHZ	1	/* clocks passsed to Linux in MHz */
 
 #define CONFIG_SYS_LOAD_ADDR     0x100000     /* default load address */
-#define CONFIG_SYS_HZ            1000         /* decrementer freq: 1 ms ticks */
 
 /*
  * Low Level Configuration Settings
diff --git a/include/configs/RRvision.h b/include/configs/RRvision.h
index 06273a2ae1..97f779871f 100644
--- a/include/configs/RRvision.h
+++ b/include/configs/RRvision.h
@@ -145,7 +145,6 @@
  * Miscellaneous configurable options
  */
 #define	CONFIG_SYS_LONGHELP			/* undef to save memory		*/
-#define	CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt	*/
 #if defined(CONFIG_CMD_KGDB)
 #define	CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
 #else
@@ -160,8 +159,6 @@
 
 #define	CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address	*/
 
-#define	CONFIG_SYS_HZ		1000		/* decrementer freq: 1 ms ticks	*/
-
 /*
  * Low Level Configuration Settings
  * (address mappings, register initial values, etc.)
diff --git a/include/configs/Rattler.h b/include/configs/Rattler.h
index 7d4e5e72a6..a1e2ae9753 100644
--- a/include/configs/Rattler.h
+++ b/include/configs/Rattler.h
@@ -13,7 +13,6 @@
 #ifdef CONFIG_MPC8248
 #define CPU_ID_STR		"MPC8248"
 #else
-#define CONFIG_MPC8260
 #define CPU_ID_STR		"MPC8250"
 #endif /* CONFIG_MPC8248 */
 
@@ -155,7 +154,6 @@
  */
 #define CONFIG_SYS_HUSH_PARSER
 #define CONFIG_SYS_LONGHELP			/* undef to save memory	    */
-#define CONFIG_SYS_PROMPT		"=> "	/* Monitor Command Prompt   */
 #if defined(CONFIG_CMD_KGDB)
 #define CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size  */
 #else
@@ -170,8 +168,6 @@
 
 #define CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address */
 
-#define CONFIG_SYS_HZ			1000	/* decrementer freq: 1 ms ticks */
-
 #define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
 
 #define CONFIG_SYS_FLASH_BASE		0xFE000000
diff --git a/include/configs/SIMPC8313.h b/include/configs/SIMPC8313.h
index 1045afb0c2..46157ccc40 100644
--- a/include/configs/SIMPC8313.h
+++ b/include/configs/SIMPC8313.h
@@ -16,7 +16,6 @@
 #define CONFIG_NAND_U_BOOT
 
 #define CONFIG_E300			1
-#define CONFIG_MPC83xx			1
 #define CONFIG_MPC831x			1
 #define CONFIG_MPC8313			1
 
@@ -357,7 +356,6 @@
  */
 #define CONFIG_SYS_LONGHELP			/* undef to save memory */
 #define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
-#define CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt */
 #define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size */
 
 #define CONFIG_SYS_PBSIZE	(CONFIG_SYS_CBSIZE		\
@@ -366,7 +364,6 @@
 #define CONFIG_SYS_MAXARGS	16	/* max number of command args */
 				/* Boot Argument Buffer Size */
 #define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE
-#define CONFIG_SYS_HZ		1000	/* decrementer freq: 1ms ticks */
 
 /*
  * For booting Linux, the board info and command line data
diff --git a/include/configs/SM850.h b/include/configs/SM850.h
index 5d48f8f8c4..a7e44647a3 100644
--- a/include/configs/SM850.h
+++ b/include/configs/SM850.h
@@ -76,7 +76,6 @@
  * Miscellaneous configurable options
  */
 #define	CONFIG_SYS_LONGHELP			/* undef to save memory		*/
-#define	CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt	*/
 #if defined(CONFIG_CMD_KGDB) && defined(KGDB_DEBUG)
 #define	CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
 #else
@@ -91,8 +90,6 @@
 
 #define	CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address	*/
 
-#define	CONFIG_SYS_HZ		1000		/* decrementer freq: 1 ms ticks	*/
-
 /*
  * Low Level Configuration Settings
  * (address mappings, register initial values, etc.)
diff --git a/include/configs/SPD823TS.h b/include/configs/SPD823TS.h
index 147cf5bec1..a8b4fbb7f8 100644
--- a/include/configs/SPD823TS.h
+++ b/include/configs/SPD823TS.h
@@ -84,7 +84,6 @@
  * Miscellaneous configurable options
  */
 #define CONFIG_SYS_LONGHELP			/* undef to save memory		*/
-#define CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt	*/
 #if defined(CONFIG_CMD_KGDB)
 #define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
 #else
@@ -103,8 +102,6 @@
 
 #define CONFIG_SYS_PC_IDE_RESET	((ushort)0x0008)	/* PC 12	*/
 
-#define	CONFIG_SYS_HZ		1000		/* decrementer freq: 1 ms ticks	*/
-
 /*
  * Low Level Configuration Settings
  * (address mappings, register initial values, etc.)
diff --git a/include/configs/SXNI855T.h b/include/configs/SXNI855T.h
index e2b05de381..38940194fb 100644
--- a/include/configs/SXNI855T.h
+++ b/include/configs/SXNI855T.h
@@ -155,7 +155,6 @@
  * Miscellaneous configurable options
  */
 #define	CONFIG_SYS_LONGHELP			/* undef to save a little memory */
-#define	CONFIG_SYS_PROMPT		"=>"	/* Monitor Command Prompt	*/
 #if defined(CONFIG_CMD_KGDB)
 #define	CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
 #else
@@ -170,8 +169,6 @@
 
 #define CONFIG_SYS_LOAD_ADDR		0x00100000
 
-#define	CONFIG_SYS_HZ		1000		/* decrementer freq: 1 ms ticks	*/
-
 /*
  * Low Level Configuration Settings
  * (address mappings, register initial values, etc.)
diff --git a/include/configs/Sandpoint8240.h b/include/configs/Sandpoint8240.h
index ed8a32f7df..2c0cb89afa 100644
--- a/include/configs/Sandpoint8240.h
+++ b/include/configs/Sandpoint8240.h
@@ -19,7 +19,6 @@
  * (easy to change)
  */
 
-#define CONFIG_MPC824X		1
 #define CONFIG_MPC8240		1
 #define CONFIG_SANDPOINT	1
 
@@ -98,13 +97,11 @@
  * Miscellaneous configurable options
  */
 #define CONFIG_SYS_LONGHELP		1		/* undef to save memory		*/
-#define CONFIG_SYS_PROMPT		"=> "		/* Monitor Command Prompt	*/
 #define CONFIG_SYS_CBSIZE		256		/* Console I/O Buffer Size	*/
 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)	/* Print Buffer Size	*/
 #define CONFIG_SYS_MAXARGS		16		/* max number of command args	*/
 #define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
 #define CONFIG_SYS_LOAD_ADDR		0x00100000	/* default load address		*/
-#define CONFIG_SYS_HZ			1000		/* decrementer freq: 1 ms ticks */
 
 /*-----------------------------------------------------------------------
  * PCI stuff
diff --git a/include/configs/Sandpoint8245.h b/include/configs/Sandpoint8245.h
index 97e8968243..2664d5b169 100644
--- a/include/configs/Sandpoint8245.h
+++ b/include/configs/Sandpoint8245.h
@@ -19,7 +19,6 @@
  * (easy to change)
  */
 
-#define CONFIG_MPC824X		1
 #define CONFIG_MPC8245		1
 #define CONFIG_SANDPOINT	1
 
@@ -66,13 +65,11 @@
  * Miscellaneous configurable options
  */
 #define CONFIG_SYS_LONGHELP		1		/* undef to save memory		*/
-#define CONFIG_SYS_PROMPT		"=> "		/* Monitor Command Prompt	*/
 #define CONFIG_SYS_CBSIZE		256		/* Console I/O Buffer Size	*/
 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)	/* Print Buffer Size	*/
 #define CONFIG_SYS_MAXARGS		16		/* max number of command args	*/
 #define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
 #define CONFIG_SYS_LOAD_ADDR		0x00100000	/* default load address		*/
-#define CONFIG_SYS_HZ			1000		/* decrementer freq: 1 ms ticks */
 
 /*-----------------------------------------------------------------------
  * PCI stuff
diff --git a/include/configs/T1040QDS.h b/include/configs/T1040QDS.h
new file mode 100644
index 0000000000..993f9ae533
--- /dev/null
+++ b/include/configs/T1040QDS.h
@@ -0,0 +1,785 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * T1040 QDS board configuration file
+ */
+#define CONFIG_T1040QDS
+#define CONFIG_PHYS_64BIT
+
+#ifdef CONFIG_RAMBOOT_PBL
+#define CONFIG_RAMBOOT_TEXT_BASE	CONFIG_SYS_TEXT_BASE
+#define CONFIG_RESET_VECTOR_ADDRESS	0xfffffffc
+#define CONFIG_SYS_FSL_PBL_PBI board/freescale/t1040qds/t1040_pbi.cfg
+#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t1040qds/t1040_rcw.cfg
+#endif
+
+/* High Level Configuration Options */
+#define CONFIG_BOOKE
+#define CONFIG_E500			/* BOOKE e500 family */
+#define CONFIG_E500MC			/* BOOKE e500mc family */
+#define CONFIG_SYS_BOOK3E_HV		/* Category E.HV supported */
+#define CONFIG_MP			/* support multiple processors */
+
+#ifndef CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_TEXT_BASE	0xeff40000
+#endif
+
+#ifndef CONFIG_RESET_VECTOR_ADDRESS
+#define CONFIG_RESET_VECTOR_ADDRESS	0xeffffffc
+#endif
+
+#define CONFIG_SYS_FSL_CPC		/* Corenet Platform Cache */
+#define CONFIG_SYS_NUM_CPC		CONFIG_NUM_DDR_CONTROLLERS
+#define CONFIG_FSL_IFC			/* Enable IFC Support */
+#define CONFIG_PCI			/* Enable PCI/PCIE */
+#define CONFIG_PCI_INDIRECT_BRIDGE
+#define CONFIG_PCIE1			/* PCIE controler 1 */
+#define CONFIG_PCIE2			/* PCIE controler 2 */
+#define CONFIG_PCIE3			/* PCIE controler 3 */
+#define CONFIG_PCIE4			/* PCIE controler 4 */
+
+#define CONFIG_FSL_PCI_INIT		/* Use common FSL init code */
+#define CONFIG_SYS_PCI_64BIT		/* enable 64-bit PCI resources */
+
+#define CONFIG_FSL_LAW			/* Use common FSL init code */
+
+#define CONFIG_ENV_OVERWRITE
+
+#ifdef CONFIG_SYS_NO_FLASH
+#define CONFIG_ENV_IS_NOWHERE
+#else
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
+#endif
+
+#ifndef CONFIG_SYS_NO_FLASH
+#if defined(CONFIG_SPIFLASH)
+#define CONFIG_SYS_EXTRA_ENV_RELOC
+#define CONFIG_ENV_IS_IN_SPI_FLASH
+#define CONFIG_ENV_SPI_BUS              0
+#define CONFIG_ENV_SPI_CS               0
+#define CONFIG_ENV_SPI_MAX_HZ           10000000
+#define CONFIG_ENV_SPI_MODE             0
+#define CONFIG_ENV_SIZE                 0x2000          /* 8KB */
+#define CONFIG_ENV_OFFSET               0x100000        /* 1MB */
+#define CONFIG_ENV_SECT_SIZE            0x10000
+#elif defined(CONFIG_SDCARD)
+#define CONFIG_SYS_EXTRA_ENV_RELOC
+#define CONFIG_ENV_IS_IN_MMC
+#define CONFIG_SYS_MMC_ENV_DEV          0
+#define CONFIG_ENV_SIZE			0x2000
+#define CONFIG_ENV_OFFSET		(512 * 1658)
+#elif defined(CONFIG_NAND)
+#define CONFIG_SYS_EXTRA_ENV_RELOC
+#define CONFIG_ENV_IS_IN_NAND
+#define CONFIG_ENV_SIZE			CONFIG_SYS_NAND_BLOCK_SIZE
+#define CONFIG_ENV_OFFSET		(7 * CONFIG_SYS_NAND_BLOCK_SIZE)
+#else
+#define CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE		0x2000
+#define CONFIG_ENV_SECT_SIZE	0x20000 /* 128K (one sector) */
+#endif
+#else /* CONFIG_SYS_NO_FLASH */
+#define CONFIG_ENV_SIZE                0x2000
+#define CONFIG_ENV_SECT_SIZE   0x20000 /* 128K (one sector) */
+#endif
+
+#ifndef __ASSEMBLY__
+unsigned long get_board_sys_clk(void);
+unsigned long get_board_ddr_clk(void);
+#endif
+
+#define CONFIG_SYS_CLK_FREQ	get_board_sys_clk() /* sysclk for MPC85xx */
+#define CONFIG_DDR_CLK_FREQ	get_board_ddr_clk()
+
+/*
+ * These can be toggled for performance analysis, otherwise use default.
+ */
+#define CONFIG_SYS_CACHE_STASHING
+#define CONFIG_BACKSIDE_L2_CACHE
+#define CONFIG_SYS_INIT_L2CSR0		L2CSR0_L2E
+#define CONFIG_BTB			/* toggle branch predition */
+#define CONFIG_DDR_ECC
+#ifdef CONFIG_DDR_ECC
+#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
+#define CONFIG_MEM_INIT_VALUE		0xdeadbeef
+#endif
+
+#define CONFIG_ENABLE_36BIT_PHYS
+
+#define CONFIG_ADDR_MAP
+#define CONFIG_SYS_NUM_ADDR_MAP		64	/* number of TLB1 entries */
+
+#define CONFIG_SYS_MEMTEST_START	0x00200000	/* memtest works on */
+#define CONFIG_SYS_MEMTEST_END		0x00400000
+#define CONFIG_SYS_ALT_MEMTEST
+#define CONFIG_PANIC_HANG	/* do not reset board on panic */
+
+/*
+ *  Config the L3 Cache as L3 SRAM
+ */
+#define CONFIG_SYS_INIT_L3_ADDR		0xFFFC0000
+
+#define CONFIG_SYS_DCSRBAR		0xf0000000
+#define CONFIG_SYS_DCSRBAR_PHYS		0xf00000000ull
+
+/* EEPROM */
+#define CONFIG_ID_EEPROM
+#define CONFIG_SYS_I2C_EEPROM_NXID
+#define CONFIG_SYS_EEPROM_BUS_NUM	0
+#define CONFIG_SYS_I2C_EEPROM_ADDR	0x57
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	1
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
+
+/*
+ * DDR Setup
+ */
+#define CONFIG_VERY_BIG_RAM
+#define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000
+#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
+
+/* CONFIG_NUM_DDR_CONTROLLERS is defined in include/asm/config_mpc85xx.h */
+#define CONFIG_DIMM_SLOTS_PER_CTLR	1
+#define CONFIG_CHIP_SELECTS_PER_CTRL	(2 * CONFIG_DIMM_SLOTS_PER_CTLR)
+
+#define CONFIG_DDR_SPD
+#define CONFIG_SYS_FSL_DDR3
+#define CONFIG_FSL_DDR_INTERACTIVE
+
+#define CONFIG_SYS_SPD_BUS_NUM	0
+#define SPD_EEPROM_ADDRESS	0x51
+
+#define CONFIG_SYS_SDRAM_SIZE	4096	/* for fixed parameter use */
+
+/*
+ * IFC Definitions
+ */
+#define CONFIG_SYS_FLASH_BASE	0xe0000000
+#define CONFIG_SYS_FLASH_BASE_PHYS	(0xf00000000ull | CONFIG_SYS_FLASH_BASE)
+
+#define CONFIG_SYS_NOR0_CSPR_EXT	(0xf)
+#define CONFIG_SYS_NOR0_CSPR	(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
+				+ 0x8000000) | \
+				CSPR_PORT_SIZE_16 | \
+				CSPR_MSEL_NOR | \
+				CSPR_V)
+#define CONFIG_SYS_NOR1_CSPR_EXT	(0xf)
+#define CONFIG_SYS_NOR1_CSPR	(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
+				CSPR_PORT_SIZE_16 | \
+				CSPR_MSEL_NOR | \
+				CSPR_V)
+#define CONFIG_SYS_NOR_AMASK	IFC_AMASK(128*1024*1024)
+/* NOR Flash Timing Params */
+#define CONFIG_SYS_NOR_CSOR	CSOR_NAND_TRHZ_80
+#define CONFIG_SYS_NOR_FTIM0	(FTIM0_NOR_TACSE(0x4) | \
+				FTIM0_NOR_TEADC(0x5) | \
+				FTIM0_NOR_TEAHC(0x5))
+#define CONFIG_SYS_NOR_FTIM1	(FTIM1_NOR_TACO(0x35) | \
+				FTIM1_NOR_TRAD_NOR(0x1A) |\
+				FTIM1_NOR_TSEQRAD_NOR(0x13))
+#define CONFIG_SYS_NOR_FTIM2	(FTIM2_NOR_TCS(0x4) | \
+				FTIM2_NOR_TCH(0x4) | \
+				FTIM2_NOR_TWPH(0x0E) | \
+				FTIM2_NOR_TWP(0x1c))
+#define CONFIG_SYS_NOR_FTIM3	0x0
+
+#define CONFIG_SYS_FLASH_QUIET_TEST
+#define CONFIG_FLASH_SHOW_PROGRESS	45 /* count down from 45/5: 9..1 */
+
+#define CONFIG_SYS_MAX_FLASH_BANKS	2	/* number of banks */
+#define CONFIG_SYS_MAX_FLASH_SECT	1024	/* sectors per device */
+#define CONFIG_SYS_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */
+
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+#define CONFIG_SYS_FLASH_BANKS_LIST	{CONFIG_SYS_FLASH_BASE_PHYS \
+					+ 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
+#define CONFIG_FSL_QIXIS	/* use common QIXIS code */
+#define QIXIS_BASE		0xffdf0000
+#define QIXIS_BASE_PHYS		(0xf00000000ull | QIXIS_BASE)
+#define QIXIS_LBMAP_SWITCH		0x06
+#define QIXIS_LBMAP_MASK		0x0f
+#define QIXIS_LBMAP_SHIFT		0
+#define QIXIS_LBMAP_DFLTBANK		0x00
+#define QIXIS_LBMAP_ALTBANK		0x04
+#define QIXIS_RST_CTL_RESET		0x31
+#define QIXIS_RCFG_CTL_RECONFIG_IDLE	0x20
+#define QIXIS_RCFG_CTL_RECONFIG_START	0x21
+#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE	0x08
+#define	QIXIS_RST_FORCE_MEM		0x01
+
+#define CONFIG_SYS_CSPR3_EXT	(0xf)
+#define CONFIG_SYS_CSPR3	(CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
+				| CSPR_PORT_SIZE_8 \
+				| CSPR_MSEL_GPCM \
+				| CSPR_V)
+#define CONFIG_SYS_AMASK3	IFC_AMASK(4*1024)
+#define CONFIG_SYS_CSOR3	0x0
+/* QIXIS Timing parameters for IFC CS3 */
+#define CONFIG_SYS_CS3_FTIM0		(FTIM0_GPCM_TACSE(0x0e) | \
+					FTIM0_GPCM_TEADC(0x0e) | \
+					FTIM0_GPCM_TEAHC(0x0e))
+#define CONFIG_SYS_CS3_FTIM1		(FTIM1_GPCM_TACO(0xff) | \
+					FTIM1_GPCM_TRAD(0x3f))
+#define CONFIG_SYS_CS3_FTIM2		(FTIM2_GPCM_TCS(0x0e) | \
+					FTIM2_GPCM_TCH(0x8) | \
+					FTIM2_GPCM_TWP(0x1f))
+#define CONFIG_SYS_CS3_FTIM3		0x0
+
+#define CONFIG_NAND_FSL_IFC
+#define CONFIG_SYS_NAND_BASE		0xff800000
+#define CONFIG_SYS_NAND_BASE_PHYS	(0xf00000000ull | CONFIG_SYS_NAND_BASE)
+
+#define CONFIG_SYS_NAND_CSPR_EXT	(0xf)
+#define CONFIG_SYS_NAND_CSPR	(CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
+				| CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
+				| CSPR_MSEL_NAND	/* MSEL = NAND */ \
+				| CSPR_V)
+#define CONFIG_SYS_NAND_AMASK	IFC_AMASK(64*1024)
+
+#define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
+				| CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
+				| CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
+				| CSOR_NAND_RAL_3	/* RAL = 3Byes */ \
+				| CSOR_NAND_PGS_2K	/* Page Size = 2K */ \
+				| CSOR_NAND_SPRZ_64/* Spare size = 64 */ \
+				| CSOR_NAND_PB(64))	/*Pages Per Block = 64*/
+
+#define CONFIG_SYS_NAND_ONFI_DETECTION
+
+/* ONFI NAND Flash mode0 Timing Params */
+#define CONFIG_SYS_NAND_FTIM0		(FTIM0_NAND_TCCST(0x07) | \
+					FTIM0_NAND_TWP(0x18)   | \
+					FTIM0_NAND_TWCHT(0x07) | \
+					FTIM0_NAND_TWH(0x0a))
+#define CONFIG_SYS_NAND_FTIM1		(FTIM1_NAND_TADLE(0x32) | \
+					FTIM1_NAND_TWBE(0x39)  | \
+					FTIM1_NAND_TRR(0x0e)   | \
+					FTIM1_NAND_TRP(0x18))
+#define CONFIG_SYS_NAND_FTIM2		(FTIM2_NAND_TRAD(0x0f) | \
+					FTIM2_NAND_TREH(0x0a) | \
+					FTIM2_NAND_TWHRE(0x1e))
+#define CONFIG_SYS_NAND_FTIM3		0x0
+
+#define CONFIG_SYS_NAND_DDR_LAW		11
+#define CONFIG_SYS_NAND_BASE_LIST	{ CONFIG_SYS_NAND_BASE }
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+#define CONFIG_MTD_NAND_VERIFY_WRITE
+#define CONFIG_CMD_NAND
+
+#define CONFIG_SYS_NAND_BLOCK_SIZE	(128 * 1024)
+
+#if defined(CONFIG_NAND)
+#define CONFIG_SYS_CSPR0_EXT		CONFIG_SYS_NAND_CSPR_EXT
+#define CONFIG_SYS_CSPR0		CONFIG_SYS_NAND_CSPR
+#define CONFIG_SYS_AMASK0		CONFIG_SYS_NAND_AMASK
+#define CONFIG_SYS_CSOR0		CONFIG_SYS_NAND_CSOR
+#define CONFIG_SYS_CS0_FTIM0		CONFIG_SYS_NAND_FTIM0
+#define CONFIG_SYS_CS0_FTIM1		CONFIG_SYS_NAND_FTIM1
+#define CONFIG_SYS_CS0_FTIM2		CONFIG_SYS_NAND_FTIM2
+#define CONFIG_SYS_CS0_FTIM3		CONFIG_SYS_NAND_FTIM3
+#define CONFIG_SYS_CSPR1_EXT		CONFIG_SYS_NOR0_CSPR_EXT
+#define CONFIG_SYS_CSPR1		CONFIG_SYS_NOR0_CSPR
+#define CONFIG_SYS_AMASK1		CONFIG_SYS_NOR_AMASK
+#define CONFIG_SYS_CSOR1		CONFIG_SYS_NOR_CSOR
+#define CONFIG_SYS_CS1_FTIM0		CONFIG_SYS_NOR_FTIM0
+#define CONFIG_SYS_CS1_FTIM1		CONFIG_SYS_NOR_FTIM1
+#define CONFIG_SYS_CS1_FTIM2		CONFIG_SYS_NOR_FTIM2
+#define CONFIG_SYS_CS1_FTIM3		CONFIG_SYS_NOR_FTIM3
+#define CONFIG_SYS_CSPR2_EXT		CONFIG_SYS_NOR1_CSPR_EXT
+#define CONFIG_SYS_CSPR2		CONFIG_SYS_NOR1_CSPR
+#define CONFIG_SYS_AMASK2		CONFIG_SYS_NOR_AMASK
+#define CONFIG_SYS_CSOR2		CONFIG_SYS_NOR_CSOR
+#define CONFIG_SYS_CS2_FTIM0		CONFIG_SYS_NOR_FTIM0
+#define CONFIG_SYS_CS2_FTIM1		CONFIG_SYS_NOR_FTIM1
+#define CONFIG_SYS_CS2_FTIM2		CONFIG_SYS_NOR_FTIM2
+#define CONFIG_SYS_CS2_FTIM3		CONFIG_SYS_NOR_FTIM3
+#else
+#define CONFIG_SYS_CSPR0_EXT		CONFIG_SYS_NOR0_CSPR_EXT
+#define CONFIG_SYS_CSPR0		CONFIG_SYS_NOR0_CSPR
+#define CONFIG_SYS_AMASK0		CONFIG_SYS_NOR_AMASK
+#define CONFIG_SYS_CSOR0		CONFIG_SYS_NOR_CSOR
+#define CONFIG_SYS_CS0_FTIM0		CONFIG_SYS_NOR_FTIM0
+#define CONFIG_SYS_CS0_FTIM1		CONFIG_SYS_NOR_FTIM1
+#define CONFIG_SYS_CS0_FTIM2		CONFIG_SYS_NOR_FTIM2
+#define CONFIG_SYS_CS0_FTIM3		CONFIG_SYS_NOR_FTIM3
+#define CONFIG_SYS_CSPR1_EXT		CONFIG_SYS_NOR1_CSPR_EXT
+#define CONFIG_SYS_CSPR1		CONFIG_SYS_NOR1_CSPR
+#define CONFIG_SYS_AMASK1		CONFIG_SYS_NOR_AMASK
+#define CONFIG_SYS_CSOR1		CONFIG_SYS_NOR_CSOR
+#define CONFIG_SYS_CS1_FTIM0		CONFIG_SYS_NOR_FTIM0
+#define CONFIG_SYS_CS1_FTIM1		CONFIG_SYS_NOR_FTIM1
+#define CONFIG_SYS_CS1_FTIM2		CONFIG_SYS_NOR_FTIM2
+#define CONFIG_SYS_CS1_FTIM3		CONFIG_SYS_NOR_FTIM3
+#define CONFIG_SYS_CSPR2_EXT		CONFIG_SYS_NAND_CSPR_EXT
+#define CONFIG_SYS_CSPR2		CONFIG_SYS_NAND_CSPR
+#define CONFIG_SYS_AMASK2		CONFIG_SYS_NAND_AMASK
+#define CONFIG_SYS_CSOR2		CONFIG_SYS_NAND_CSOR
+#define CONFIG_SYS_CS2_FTIM0		CONFIG_SYS_NAND_FTIM0
+#define CONFIG_SYS_CS2_FTIM1		CONFIG_SYS_NAND_FTIM1
+#define CONFIG_SYS_CS2_FTIM2		CONFIG_SYS_NAND_FTIM2
+#define CONFIG_SYS_CS2_FTIM3		CONFIG_SYS_NAND_FTIM3
+#endif
+
+#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_TEXT_BASE
+
+#if defined(CONFIG_RAMBOOT_PBL)
+#define CONFIG_SYS_RAMBOOT
+#endif
+
+#define CONFIG_BOARD_EARLY_INIT_R
+#define CONFIG_MISC_INIT_R
+
+#define CONFIG_HWCONFIG
+
+/* define to use L1 as initial stack */
+#define CONFIG_L1_INIT_RAM
+#define CONFIG_SYS_INIT_RAM_LOCK
+#define CONFIG_SYS_INIT_RAM_ADDR	0xfdd00000	/* Initial L1 address */
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH	0xf
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW	0xfe0ec000
+/* The assembler doesn't like typecast */
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
+	((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
+	  CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
+#define CONFIG_SYS_INIT_RAM_SIZE		0x00004000
+
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - \
+					GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+#define CONFIG_SYS_MONITOR_LEN		(512 * 1024)
+#define CONFIG_SYS_MALLOC_LEN		(10 * 1024 * 1024)
+
+/* Serial Port - controlled on board with jumper J8
+ * open - index 2
+ * shorted - index 1
+ */
+#define CONFIG_CONS_INDEX	1
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	1
+#define CONFIG_SYS_NS16550_CLK		(get_bus_freq(0)/2)
+
+#define CONFIG_SYS_BAUDRATE_TABLE	\
+	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
+
+#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_CCSRBAR+0x11C500)
+#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_CCSRBAR+0x11C600)
+#define CONFIG_SYS_NS16550_COM3	(CONFIG_SYS_CCSRBAR+0x11D500)
+#define CONFIG_SYS_NS16550_COM4	(CONFIG_SYS_CCSRBAR+0x11D600)
+#define CONFIG_SERIAL_MULTI		/* Enable both serial ports */
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV	/* determine from environment */
+
+/* Use the HUSH parser */
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
+
+/* Video */
+#define CONFIG_FSL_DIU_FB
+#ifdef CONFIG_FSL_DIU_FB
+#define CONFIG_SYS_DIU_ADDR	(CONFIG_SYS_CCSRBAR + 0x180000)
+#define CONFIG_VIDEO
+#define CONFIG_CMD_BMP
+#define CONFIG_CFB_CONSOLE
+#define CONFIG_VIDEO_SW_CURSOR
+#define CONFIG_VGA_AS_SINGLE_DEVICE
+#define CONFIG_VIDEO_LOGO
+#define CONFIG_VIDEO_BMP_LOGO
+#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
+/*
+ * With CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS, flash I/O is really slow, so
+ * disable empty flash sector detection, which is I/O-intensive.
+ */
+#undef CONFIG_SYS_FLASH_EMPTY_INFO
+#endif
+
+/* pass open firmware flat tree */
+#define CONFIG_OF_LIBFDT
+#define CONFIG_OF_BOARD_SETUP
+#define CONFIG_OF_STDOUT_VIA_ALIAS
+
+/* new uImage format support */
+#define CONFIG_FIT
+#define CONFIG_FIT_VERBOSE	/* enable fit_format_{error,warning}() */
+
+/* I2C */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_FSL		/* Use FSL common I2C driver */
+#define CONFIG_SYS_FSL_I2C_SPEED	50000	/* I2C speed in Hz */
+#define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
+#define CONFIG_SYS_FSL_I2C2_SPEED	50000	/* I2C speed in Hz */
+#define CONFIG_SYS_FSL_I2C2_SLAVE	0x7F
+#define CONFIG_SYS_FSL_I2C_OFFSET	0x118000
+#define CONFIG_SYS_FSL_I2C2_OFFSET	0x119000
+
+#define I2C_MUX_PCA_ADDR		0x77
+#define I2C_MUX_PCA_ADDR_PRI		0x77 /* Primary Mux*/
+
+
+/* I2C bus multiplexer */
+#define I2C_MUX_CH_DEFAULT      0x8
+#define I2C_MUX_CH_DIU		0xC
+
+/* LDI/DVI Encoder for display */
+#define CONFIG_SYS_I2C_LDI_ADDR         0x38
+#define CONFIG_SYS_I2C_DVI_ADDR         0x75
+
+/*
+ * RTC configuration
+ */
+#define RTC
+#define CONFIG_RTC_DS3231               1
+#define CONFIG_SYS_I2C_RTC_ADDR         0x68
+
+/*
+ * eSPI - Enhanced SPI
+ */
+#define CONFIG_FSL_ESPI
+#define CONFIG_SPI_FLASH
+#define CONFIG_SPI_FLASH_STMICRO
+#define CONFIG_SPI_FLASH_SST
+#define CONFIG_SPI_FLASH_EON
+#define CONFIG_CMD_SF
+#define CONFIG_SF_DEFAULT_SPEED         10000000
+#define CONFIG_SF_DEFAULT_MODE          0
+
+/*
+ * General PCI
+ * Memory space is mapped 1-1, but I/O space must start from 0.
+ */
+
+#ifdef CONFIG_PCI
+/* controller 1, direct to uli, tgtid 3, Base address 20000 */
+#ifdef CONFIG_PCIE1
+#define	CONFIG_SYS_PCIE1_MEM_VIRT	0x80000000
+#define	CONFIG_SYS_PCIE1_MEM_BUS	0xe0000000
+#define	CONFIG_SYS_PCIE1_MEM_PHYS	0xc00000000ull
+#define CONFIG_SYS_PCIE1_MEM_SIZE	0x10000000	/* 256M */
+#define CONFIG_SYS_PCIE1_IO_VIRT	0xf8000000
+#define CONFIG_SYS_PCIE1_IO_BUS		0x00000000
+#define CONFIG_SYS_PCIE1_IO_PHYS	0xff8000000ull
+#define CONFIG_SYS_PCIE1_IO_SIZE	0x00010000	/* 64k */
+#endif
+
+/* controller 2, Slot 2, tgtid 2, Base address 201000 */
+#ifdef CONFIG_PCIE2
+#define CONFIG_SYS_PCIE2_MEM_VIRT	0x90000000
+#define CONFIG_SYS_PCIE2_MEM_BUS	0xe0000000
+#define CONFIG_SYS_PCIE2_MEM_PHYS	0xc10000000ull
+#define CONFIG_SYS_PCIE2_MEM_SIZE	0x10000000	/* 256M */
+#define CONFIG_SYS_PCIE2_IO_VIRT	0xf8010000
+#define CONFIG_SYS_PCIE2_IO_BUS		0x00000000
+#define CONFIG_SYS_PCIE2_IO_PHYS	0xff8010000ull
+#define CONFIG_SYS_PCIE2_IO_SIZE	0x00010000	/* 64k */
+#endif
+
+/* controller 3, Slot 1, tgtid 1, Base address 202000 */
+#ifdef CONFIG_PCIE3
+#define CONFIG_SYS_PCIE3_MEM_VIRT	0xa0000000
+#define CONFIG_SYS_PCIE3_MEM_BUS	0xe0000000
+#define CONFIG_SYS_PCIE3_MEM_PHYS	0xc20000000ull
+#define CONFIG_SYS_PCIE3_MEM_SIZE	0x10000000	/* 256M */
+#define CONFIG_SYS_PCIE3_IO_VIRT	0xf8020000
+#define CONFIG_SYS_PCIE3_IO_BUS		0x00000000
+#define CONFIG_SYS_PCIE3_IO_PHYS	0xff8020000ull
+#define CONFIG_SYS_PCIE3_IO_SIZE	0x00010000	/* 64k */
+#endif
+
+/* controller 4, Base address 203000 */
+#ifdef CONFIG_PCIE4
+#define CONFIG_SYS_PCIE4_MEM_VIRT	0xb0000000
+#define CONFIG_SYS_PCIE4_MEM_BUS	0xe0000000
+#define CONFIG_SYS_PCIE4_MEM_PHYS	0xc30000000ull
+#define CONFIG_SYS_PCIE4_MEM_SIZE	0x10000000	/* 256M */
+#define CONFIG_SYS_PCIE4_IO_VIRT	0xf8030000
+#define CONFIG_SYS_PCIE4_IO_BUS		0x00000000
+#define CONFIG_SYS_PCIE4_IO_PHYS	0xff8030000ull
+#define CONFIG_SYS_PCIE4_IO_SIZE	0x00010000	/* 64k */
+#endif
+
+#define CONFIG_PCI_PNP			/* do pci plug-and-play */
+#define CONFIG_E1000
+
+#define CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
+#define CONFIG_DOS_PARTITION
+#endif	/* CONFIG_PCI */
+
+/* SATA */
+#define CONFIG_FSL_SATA_V2
+#ifdef CONFIG_FSL_SATA_V2
+#define CONFIG_LIBATA
+#define CONFIG_FSL_SATA
+
+#define CONFIG_SYS_SATA_MAX_DEVICE	2
+#define CONFIG_SATA1
+#define CONFIG_SYS_SATA1		CONFIG_SYS_MPC85xx_SATA1_ADDR
+#define CONFIG_SYS_SATA1_FLAGS		FLAGS_DMA
+#define CONFIG_SATA2
+#define CONFIG_SYS_SATA2		CONFIG_SYS_MPC85xx_SATA2_ADDR
+#define CONFIG_SYS_SATA2_FLAGS		FLAGS_DMA
+
+#define CONFIG_LBA48
+#define CONFIG_CMD_SATA
+#define CONFIG_DOS_PARTITION
+#define CONFIG_CMD_EXT2
+#endif
+
+/*
+* USB
+*/
+#define CONFIG_HAS_FSL_DR_USB
+
+#ifdef CONFIG_HAS_FSL_DR_USB
+#define CONFIG_USB_EHCI
+
+#ifdef CONFIG_USB_EHCI
+#define CONFIG_CMD_USB
+#define CONFIG_USB_STORAGE
+#define CONFIG_USB_EHCI_FSL
+#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
+#define CONFIG_CMD_EXT2
+#endif
+#endif
+
+#define CONFIG_MMC
+
+#ifdef CONFIG_MMC
+#define CONFIG_FSL_ESDHC
+#define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
+#define CONFIG_CMD_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_FAT
+#define CONFIG_DOS_PARTITION
+#endif
+
+/* Qman/Bman */
+#ifndef CONFIG_NOBQFMAN
+#define CONFIG_SYS_DPAA_QBMAN		/* Support Q/Bman */
+#define CONFIG_SYS_BMAN_NUM_PORTALS	25
+#define CONFIG_SYS_BMAN_MEM_BASE	0xf4000000
+#define CONFIG_SYS_BMAN_MEM_PHYS	0xff4000000ull
+#define CONFIG_SYS_BMAN_MEM_SIZE	0x02000000
+#define CONFIG_SYS_QMAN_NUM_PORTALS	25
+#define CONFIG_SYS_QMAN_MEM_BASE	0xf6000000
+#define CONFIG_SYS_QMAN_MEM_PHYS	0xff6000000ull
+#define CONFIG_SYS_QMAN_MEM_SIZE	0x02000000
+
+#define CONFIG_SYS_DPAA_FMAN
+#define CONFIG_SYS_DPAA_PME
+
+/* Default address of microcode for the Linux Fman driver */
+#if defined(CONFIG_SPIFLASH)
+/*
+ * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
+ * env, so we got 0x110000.
+ */
+#define CONFIG_SYS_QE_FW_IN_SPIFLASH
+#define CONFIG_SYS_QE_FMAN_FW_ADDR	0x110000
+#elif defined(CONFIG_SDCARD)
+/*
+ * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
+ * about 825KB (1650 blocks), Env is stored after the image, and the env size is
+ * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680.
+ */
+#define CONFIG_SYS_QE_FMAN_FW_IN_MMC
+#define CONFIG_SYS_QE_FMAN_FW_ADDR	(512 * 1680)
+#elif defined(CONFIG_NAND)
+#define CONFIG_SYS_QE_FMAN_FW_IN_NAND
+#define CONFIG_SYS_QE_FMAN_FW_ADDR	(8 * CONFIG_SYS_NAND_BLOCK_SIZE)
+#else
+#define CONFIG_SYS_QE_FMAN_FW_IN_NOR
+#define CONFIG_SYS_QE_FMAN_FW_ADDR		0xEFF00000
+#endif
+#define CONFIG_SYS_QE_FMAN_FW_LENGTH	0x10000
+#define CONFIG_SYS_FDT_PAD		(0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
+#endif /* CONFIG_NOBQFMAN */
+
+#ifdef CONFIG_SYS_DPAA_FMAN
+#define CONFIG_FMAN_ENET
+#define CONFIG_PHYLIB_10G
+#define CONFIG_PHY_VITESSE
+#define CONFIG_PHY_REALTEK
+#define CONFIG_PHY_TERANETICS
+#define SGMII_CARD_PORT1_PHY_ADDR 0x1C
+#define SGMII_CARD_PORT2_PHY_ADDR 0x10
+#define SGMII_CARD_PORT3_PHY_ADDR 0x1E
+#define SGMII_CARD_PORT4_PHY_ADDR 0x11
+#endif
+
+#ifdef CONFIG_FMAN_ENET
+#define CONFIG_SYS_FM1_DTSEC4_PHY_ADDR	0x01
+#define CONFIG_SYS_FM1_DTSEC5_PHY_ADDR	0x02
+
+#define CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR    0x1c
+#define CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR    0x1d
+#define CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR    0x1e
+#define CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR    0x1f
+
+#define CONFIG_MII		/* MII PHY management */
+#define CONFIG_ETHPRIME		"FM1@DTSEC1"
+#define CONFIG_PHY_GIGE		/* Include GbE speed/duplex detection */
+#endif
+
+/*
+ * Environment
+ */
+#define CONFIG_LOADS_ECHO		/* echo on for serial download */
+#define CONFIG_SYS_LOADS_BAUD_CHANGE	/* allow baudrate change */
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_ERRATA
+#define CONFIG_CMD_GREPENV
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_REGINFO
+#define CONFIG_CMD_SETEXPR
+
+#ifdef CONFIG_PCI
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_NET
+#endif
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP			/* undef to save memory	*/
+#define CONFIG_CMDLINE_EDITING			/* Command-line editing */
+#define CONFIG_AUTO_COMPLETE			/* add autocompletion support */
+#define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
+#define CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt */
+#ifdef CONFIG_CMD_KGDB
+#define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size */
+#else
+#define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size */
+#endif
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
+#define CONFIG_SYS_MAXARGS	16		/* max number of command args */
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 64 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ	(64 << 20)	/* Initial map for Linux*/
+#define CONFIG_SYS_BOOTM_LEN	(64 << 20)	/* Increase max gunzip size */
+
+#ifdef CONFIG_CMD_KGDB
+#define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
+#endif
+
+/*
+ * Environment Configuration
+ */
+#define CONFIG_ROOTPATH		"/opt/nfsroot"
+#define CONFIG_BOOTFILE		"uImage"
+#define CONFIG_UBOOTPATH	"u-boot.bin"	/* U-Boot image on TFTP server*/
+
+/* default location for tftp and bootm */
+#define CONFIG_LOADADDR		1000000
+
+#define CONFIG_BOOTDELAY	10	/* -1 disables auto-boot */
+
+#define CONFIG_BAUDRATE	115200
+
+#define __USB_PHY_TYPE	utmi
+
+#define	CONFIG_EXTRA_ENV_SETTINGS				\
+	"hwconfig=fsl_ddr:ctlr_intlv=cacheline,"		\
+	"bank_intlv=cs0_cs1;"					\
+	"usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
+	"netdev=eth0\0"						\
+	"video-mode=fslfb:1024x768-32@60,monitor=dvi\0"		\
+	"uboot=" __stringify(CONFIG_UBOOTPATH) "\0"		\
+	"ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"	\
+	"tftpflash=tftpboot $loadaddr $uboot && "		\
+	"protect off $ubootaddr +$filesize && "			\
+	"erase $ubootaddr +$filesize && "			\
+	"cp.b $loadaddr $ubootaddr $filesize && "		\
+	"protect on $ubootaddr +$filesize && "			\
+	"cmp.b $loadaddr $ubootaddr $filesize\0"		\
+	"consoledev=ttyS0\0"					\
+	"ramdiskaddr=2000000\0"					\
+	"ramdiskfile=t1040qds/ramdisk.uboot\0"			\
+	"fdtaddr=c00000\0"					\
+	"fdtfile=t1040qds/t1040qds.dtb\0"			\
+	"bdev=sda3\0"						\
+	"c=ffe\0"
+
+#define CONFIG_LINUX                       \
+	"setenv bootargs root=/dev/ram rw "            \
+	"console=$consoledev,$baudrate $othbootargs;"  \
+	"setenv ramdiskaddr 0x02000000;"               \
+	"setenv fdtaddr 0x00c00000;"		       \
+	"setenv loadaddr 0x1000000;"		       \
+	"bootm $loadaddr $ramdiskaddr $fdtaddr"
+
+#define CONFIG_HDBOOT					\
+	"setenv bootargs root=/dev/$bdev rw "		\
+	"console=$consoledev,$baudrate $othbootargs;"	\
+	"tftp $loadaddr $bootfile;"			\
+	"tftp $fdtaddr $fdtfile;"			\
+	"bootm $loadaddr - $fdtaddr"
+
+#define CONFIG_NFSBOOTCOMMAND			\
+	"setenv bootargs root=/dev/nfs rw "	\
+	"nfsroot=$serverip:$rootpath "		\
+	"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
+	"console=$consoledev,$baudrate $othbootargs;"	\
+	"tftp $loadaddr $bootfile;"		\
+	"tftp $fdtaddr $fdtfile;"		\
+	"bootm $loadaddr - $fdtaddr"
+
+#define CONFIG_RAMBOOTCOMMAND				\
+	"setenv bootargs root=/dev/ram rw "		\
+	"console=$consoledev,$baudrate $othbootargs;"	\
+	"tftp $ramdiskaddr $ramdiskfile;"		\
+	"tftp $loadaddr $bootfile;"			\
+	"tftp $fdtaddr $fdtfile;"			\
+	"bootm $loadaddr $ramdiskaddr $fdtaddr"
+
+#define CONFIG_BOOTCOMMAND		CONFIG_LINUX
+
+#ifdef CONFIG_SECURE_BOOT
+#include <asm/fsl_secure_boot.h>
+#endif
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/T1040RDB.h b/include/configs/T1040RDB.h
new file mode 100644
index 0000000000..395845bd68
--- /dev/null
+++ b/include/configs/T1040RDB.h
@@ -0,0 +1,687 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * T1040 RDB board configuration file
+ */
+#define CONFIG_T104xRDB
+#define CONFIG_T1040RDB
+#define CONFIG_PHYS_64BIT
+
+#ifdef CONFIG_RAMBOOT_PBL
+#define CONFIG_RAMBOOT_TEXT_BASE	CONFIG_SYS_TEXT_BASE
+#define CONFIG_RESET_VECTOR_ADDRESS	0xfffffffc
+#endif
+
+/* High Level Configuration Options */
+#define CONFIG_BOOKE
+#define CONFIG_E500			/* BOOKE e500 family */
+#define CONFIG_E500MC			/* BOOKE e500mc family */
+#define CONFIG_SYS_BOOK3E_HV		/* Category E.HV supported */
+#define CONFIG_MP			/* support multiple processors */
+
+#ifndef CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_TEXT_BASE	0xeff40000
+#endif
+
+#ifndef CONFIG_RESET_VECTOR_ADDRESS
+#define CONFIG_RESET_VECTOR_ADDRESS	0xeffffffc
+#endif
+
+#define CONFIG_SYS_FSL_CPC		/* Corenet Platform Cache */
+#define CONFIG_SYS_NUM_CPC		CONFIG_NUM_DDR_CONTROLLERS
+#define CONFIG_FSL_IFC			/* Enable IFC Support */
+#define CONFIG_PCI			/* Enable PCI/PCIE */
+#define CONFIG_PCI_INDIRECT_BRIDGE
+#define CONFIG_PCIE1			/* PCIE controler 1 */
+#define CONFIG_PCIE2			/* PCIE controler 2 */
+#define CONFIG_PCIE3			/* PCIE controler 3 */
+#define CONFIG_PCIE4			/* PCIE controler 4 */
+
+#define CONFIG_FSL_PCI_INIT		/* Use common FSL init code */
+#define CONFIG_SYS_PCI_64BIT		/* enable 64-bit PCI resources */
+
+#define CONFIG_FSL_LAW			/* Use common FSL init code */
+
+#define CONFIG_ENV_OVERWRITE
+
+#ifdef CONFIG_SYS_NO_FLASH
+#define CONFIG_ENV_IS_NOWHERE
+#else
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
+#endif
+
+#ifndef CONFIG_SYS_NO_FLASH
+#if defined(CONFIG_SPIFLASH)
+#define CONFIG_SYS_EXTRA_ENV_RELOC
+#define CONFIG_ENV_IS_IN_SPI_FLASH
+#define CONFIG_ENV_SIZE                 0x2000          /* 8KB */
+#define CONFIG_ENV_OFFSET               0x100000        /* 1MB */
+#define CONFIG_ENV_SECT_SIZE            0x10000
+#elif defined(CONFIG_SDCARD)
+#define CONFIG_SYS_EXTRA_ENV_RELOC
+#define CONFIG_ENV_IS_IN_MMC
+#define CONFIG_SYS_MMC_ENV_DEV          0
+#define CONFIG_ENV_SIZE			0x2000
+#define CONFIG_ENV_OFFSET		(512 * 1658)
+#elif defined(CONFIG_NAND)
+#define CONFIG_SYS_EXTRA_ENV_RELOC
+#define CONFIG_ENV_IS_IN_NAND
+#define CONFIG_ENV_SIZE			CONFIG_SYS_NAND_BLOCK_SIZE
+#define CONFIG_ENV_OFFSET		(3 * CONFIG_SYS_NAND_BLOCK_SIZE)
+#else
+#define CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE		0x2000
+#define CONFIG_ENV_SECT_SIZE	0x20000 /* 128K (one sector) */
+#endif
+#else /* CONFIG_SYS_NO_FLASH */
+#define CONFIG_ENV_SIZE                0x2000
+#define CONFIG_ENV_SECT_SIZE   0x20000 /* 128K (one sector) */
+#endif
+
+#define CONFIG_SYS_CLK_FREQ	100000000
+#define CONFIG_DDR_CLK_FREQ	66666666
+
+/*
+ * These can be toggled for performance analysis, otherwise use default.
+ */
+#define CONFIG_SYS_CACHE_STASHING
+#define CONFIG_BACKSIDE_L2_CACHE
+#define CONFIG_SYS_INIT_L2CSR0		L2CSR0_L2E
+#define CONFIG_BTB			/* toggle branch predition */
+#define CONFIG_DDR_ECC
+#ifdef CONFIG_DDR_ECC
+#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
+#define CONFIG_MEM_INIT_VALUE		0xdeadbeef
+#endif
+
+#define CONFIG_ENABLE_36BIT_PHYS
+
+#define CONFIG_ADDR_MAP
+#define CONFIG_SYS_NUM_ADDR_MAP		64	/* number of TLB1 entries */
+
+#define CONFIG_SYS_MEMTEST_START	0x00200000	/* memtest works on */
+#define CONFIG_SYS_MEMTEST_END		0x00400000
+#define CONFIG_SYS_ALT_MEMTEST
+#define CONFIG_PANIC_HANG	/* do not reset board on panic */
+
+/*
+ *  Config the L3 Cache as L3 SRAM
+ */
+#define CONFIG_SYS_INIT_L3_ADDR		0xFFFC0000
+
+#define CONFIG_SYS_DCSRBAR		0xf0000000
+#define CONFIG_SYS_DCSRBAR_PHYS		0xf00000000ull
+
+/*
+ * DDR Setup
+ */
+#define CONFIG_VERY_BIG_RAM
+#define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000
+#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
+
+/* CONFIG_NUM_DDR_CONTROLLERS is defined in include/asm/config_mpc85xx.h */
+#define CONFIG_DIMM_SLOTS_PER_CTLR	1
+#define CONFIG_CHIP_SELECTS_PER_CTRL	(2 * CONFIG_DIMM_SLOTS_PER_CTLR)
+
+#define CONFIG_DDR_SPD
+#define CONFIG_SYS_DDR_RAW_TIMING
+#define CONFIG_SYS_FSL_DDR3
+
+#define CONFIG_SYS_SPD_BUS_NUM	0
+#define SPD_EEPROM_ADDRESS	0x51
+
+#define CONFIG_SYS_SDRAM_SIZE	4096	/* for fixed parameter use */
+
+/*
+ * IFC Definitions
+ */
+#define CONFIG_SYS_FLASH_BASE	0xe8000000
+#define CONFIG_SYS_FLASH_BASE_PHYS	(0xf00000000ull | CONFIG_SYS_FLASH_BASE)
+
+#define CONFIG_SYS_NOR_CSPR_EXT	(0xf)
+#define CONFIG_SYS_NOR_CSPR	(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE) | \
+				CSPR_PORT_SIZE_16 | \
+				CSPR_MSEL_NOR | \
+				CSPR_V)
+#define CONFIG_SYS_NOR_AMASK	IFC_AMASK(128*1024*1024)
+/* NOR Flash Timing Params */
+#define CONFIG_SYS_NOR_CSOR	CSOR_NAND_TRHZ_80
+#define CONFIG_SYS_NOR_FTIM0	(FTIM0_NOR_TACSE(0x4) | \
+				FTIM0_NOR_TEADC(0x5) | \
+				FTIM0_NOR_TEAHC(0x5))
+#define CONFIG_SYS_NOR_FTIM1	(FTIM1_NOR_TACO(0x35) | \
+				FTIM1_NOR_TRAD_NOR(0x1A) |\
+				FTIM1_NOR_TSEQRAD_NOR(0x13))
+#define CONFIG_SYS_NOR_FTIM2	(FTIM2_NOR_TCS(0x4) | \
+				FTIM2_NOR_TCH(0x4) | \
+				FTIM2_NOR_TWPH(0x0E) | \
+				FTIM2_NOR_TWP(0x1c))
+#define CONFIG_SYS_NOR_FTIM3	0x0
+
+#define CONFIG_SYS_FLASH_QUIET_TEST
+#define CONFIG_FLASH_SHOW_PROGRESS	45 /* count down from 45/5: 9..1 */
+
+#define CONFIG_SYS_MAX_FLASH_BANKS	2	/* number of banks */
+#define CONFIG_SYS_MAX_FLASH_SECT	1024	/* sectors per device */
+#define CONFIG_SYS_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */
+
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+#define CONFIG_SYS_FLASH_BANKS_LIST	{CONFIG_SYS_FLASH_BASE_PHYS}
+
+/* CPLD on IFC */
+#define CONFIG_SYS_CPLD_BASE	0xffdf0000
+#define CONFIG_SYS_CPLD_BASE_PHYS	(0xf00000000ull | CONFIG_SYS_CPLD_BASE)
+#define CONFIG_SYS_CSPR2_EXT	(0xf)
+#define CONFIG_SYS_CSPR2	(CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \
+				| CSPR_PORT_SIZE_8 \
+				| CSPR_MSEL_GPCM \
+				| CSPR_V)
+#define CONFIG_SYS_AMASK2	IFC_AMASK(64*1024)
+#define CONFIG_SYS_CSOR2	0x0
+/* CPLD Timing parameters for IFC CS2 */
+#define CONFIG_SYS_CS2_FTIM0		(FTIM0_GPCM_TACSE(0x0e) | \
+					FTIM0_GPCM_TEADC(0x0e) | \
+					FTIM0_GPCM_TEAHC(0x0e))
+#define CONFIG_SYS_CS2_FTIM1		(FTIM1_GPCM_TACO(0x0e) | \
+					FTIM1_GPCM_TRAD(0x1f))
+#define CONFIG_SYS_CS2_FTIM2		(FTIM2_GPCM_TCS(0x0e) | \
+					FTIM2_GPCM_TCH(0x0) | \
+					FTIM2_GPCM_TWP(0x1f))
+#define CONFIG_SYS_CS2_FTIM3		0x0
+
+/* NAND Flash on IFC */
+#define CONFIG_NAND_FSL_IFC
+#define CONFIG_SYS_NAND_BASE		0xff800000
+#define CONFIG_SYS_NAND_BASE_PHYS	(0xf00000000ull | CONFIG_SYS_NAND_BASE)
+
+#define CONFIG_SYS_NAND_CSPR_EXT	(0xf)
+#define CONFIG_SYS_NAND_CSPR	(CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
+				| CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
+				| CSPR_MSEL_NAND	/* MSEL = NAND */ \
+				| CSPR_V)
+#define CONFIG_SYS_NAND_AMASK	IFC_AMASK(64*1024)
+
+#define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
+				| CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
+				| CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
+				| CSOR_NAND_RAL_3	/* RAL = 3Byes */ \
+				| CSOR_NAND_PGS_4K	/* Page Size = 4K */ \
+				| CSOR_NAND_SPRZ_224/* Spare size = 224 */ \
+				| CSOR_NAND_PB(64))	/*Pages Per Block = 64*/
+
+#define CONFIG_SYS_NAND_ONFI_DETECTION
+
+/* ONFI NAND Flash mode0 Timing Params */
+#define CONFIG_SYS_NAND_FTIM0		(FTIM0_NAND_TCCST(0x07) | \
+					FTIM0_NAND_TWP(0x18)   | \
+					FTIM0_NAND_TWCHT(0x07) | \
+					FTIM0_NAND_TWH(0x0a))
+#define CONFIG_SYS_NAND_FTIM1		(FTIM1_NAND_TADLE(0x32) | \
+					FTIM1_NAND_TWBE(0x39)  | \
+					FTIM1_NAND_TRR(0x0e)   | \
+					FTIM1_NAND_TRP(0x18))
+#define CONFIG_SYS_NAND_FTIM2		(FTIM2_NAND_TRAD(0x0f) | \
+					FTIM2_NAND_TREH(0x0a) | \
+					FTIM2_NAND_TWHRE(0x1e))
+#define CONFIG_SYS_NAND_FTIM3		0x0
+
+#define CONFIG_SYS_NAND_DDR_LAW		11
+#define CONFIG_SYS_NAND_BASE_LIST	{ CONFIG_SYS_NAND_BASE }
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+#define CONFIG_MTD_NAND_VERIFY_WRITE
+#define CONFIG_CMD_NAND
+
+#define CONFIG_SYS_NAND_BLOCK_SIZE	(512 * 1024)
+
+#if defined(CONFIG_NAND)
+#define CONFIG_SYS_CSPR0_EXT		CONFIG_SYS_NAND_CSPR_EXT
+#define CONFIG_SYS_CSPR0		CONFIG_SYS_NAND_CSPR
+#define CONFIG_SYS_AMASK0		CONFIG_SYS_NAND_AMASK
+#define CONFIG_SYS_CSOR0		CONFIG_SYS_NAND_CSOR
+#define CONFIG_SYS_CS0_FTIM0		CONFIG_SYS_NAND_FTIM0
+#define CONFIG_SYS_CS0_FTIM1		CONFIG_SYS_NAND_FTIM1
+#define CONFIG_SYS_CS0_FTIM2		CONFIG_SYS_NAND_FTIM2
+#define CONFIG_SYS_CS0_FTIM3		CONFIG_SYS_NAND_FTIM3
+#define CONFIG_SYS_CSPR1_EXT		CONFIG_SYS_NOR_CSPR_EXT
+#define CONFIG_SYS_CSPR1		CONFIG_SYS_NOR_CSPR
+#define CONFIG_SYS_AMASK1		CONFIG_SYS_NOR_AMASK
+#define CONFIG_SYS_CSOR1		CONFIG_SYS_NOR_CSOR
+#define CONFIG_SYS_CS1_FTIM0		CONFIG_SYS_NOR_FTIM0
+#define CONFIG_SYS_CS1_FTIM1		CONFIG_SYS_NOR_FTIM1
+#define CONFIG_SYS_CS1_FTIM2		CONFIG_SYS_NOR_FTIM2
+#define CONFIG_SYS_CS1_FTIM3		CONFIG_SYS_NOR_FTIM3
+#else
+#define CONFIG_SYS_CSPR0_EXT		CONFIG_SYS_NOR_CSPR_EXT
+#define CONFIG_SYS_CSPR0		CONFIG_SYS_NOR_CSPR
+#define CONFIG_SYS_AMASK0		CONFIG_SYS_NOR_AMASK
+#define CONFIG_SYS_CSOR0		CONFIG_SYS_NOR_CSOR
+#define CONFIG_SYS_CS0_FTIM0		CONFIG_SYS_NOR_FTIM0
+#define CONFIG_SYS_CS0_FTIM1		CONFIG_SYS_NOR_FTIM1
+#define CONFIG_SYS_CS0_FTIM2		CONFIG_SYS_NOR_FTIM2
+#define CONFIG_SYS_CS0_FTIM3		CONFIG_SYS_NOR_FTIM3
+#define CONFIG_SYS_CSPR1_EXT		CONFIG_SYS_NAND_CSPR_EXT
+#define CONFIG_SYS_CSPR1		CONFIG_SYS_NAND_CSPR
+#define CONFIG_SYS_AMASK1		CONFIG_SYS_NAND_AMASK
+#define CONFIG_SYS_CSOR1		CONFIG_SYS_NAND_CSOR
+#define CONFIG_SYS_CS1_FTIM0		CONFIG_SYS_NAND_FTIM0
+#define CONFIG_SYS_CS1_FTIM1		CONFIG_SYS_NAND_FTIM1
+#define CONFIG_SYS_CS1_FTIM2		CONFIG_SYS_NAND_FTIM2
+#define CONFIG_SYS_CS1_FTIM3		CONFIG_SYS_NAND_FTIM3
+#endif
+
+#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_TEXT_BASE
+
+#if defined(CONFIG_RAMBOOT_PBL)
+#define CONFIG_SYS_RAMBOOT
+#endif
+
+#define CONFIG_BOARD_EARLY_INIT_R
+#define CONFIG_MISC_INIT_R
+
+#define CONFIG_HWCONFIG
+
+/* define to use L1 as initial stack */
+#define CONFIG_L1_INIT_RAM
+#define CONFIG_SYS_INIT_RAM_LOCK
+#define CONFIG_SYS_INIT_RAM_ADDR	0xfdd00000	/* Initial L1 address */
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH	0xf
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW	0xfe0ec000
+/* The assembler doesn't like typecast */
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
+	((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
+	  CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
+#define CONFIG_SYS_INIT_RAM_SIZE		0x00004000
+
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - \
+					GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+#define CONFIG_SYS_MONITOR_LEN		(512 * 1024)
+#define CONFIG_SYS_MALLOC_LEN		(4 * 1024 * 1024)
+
+/* Serial Port - controlled on board with jumper J8
+ * open - index 2
+ * shorted - index 1
+ */
+#define CONFIG_CONS_INDEX	1
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	1
+#define CONFIG_SYS_NS16550_CLK		(get_bus_freq(0)/2)
+
+#define CONFIG_SYS_BAUDRATE_TABLE	\
+	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
+
+#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_CCSRBAR+0x11C500)
+#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_CCSRBAR+0x11C600)
+#define CONFIG_SYS_NS16550_COM3	(CONFIG_SYS_CCSRBAR+0x11D500)
+#define CONFIG_SYS_NS16550_COM4	(CONFIG_SYS_CCSRBAR+0x11D600)
+#define CONFIG_SERIAL_MULTI		/* Enable both serial ports */
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV	/* determine from environment */
+
+/* Use the HUSH parser */
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
+
+/* pass open firmware flat tree */
+#define CONFIG_OF_LIBFDT
+#define CONFIG_OF_BOARD_SETUP
+#define CONFIG_OF_STDOUT_VIA_ALIAS
+
+/* new uImage format support */
+#define CONFIG_FIT
+#define CONFIG_FIT_VERBOSE	/* enable fit_format_{error,warning}() */
+
+/* I2C */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_FSL		/* Use FSL common I2C driver */
+#define CONFIG_SYS_FSL_I2C_SPEED	400000	/* I2C speed in Hz */
+#define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
+#define CONFIG_SYS_FSL_I2C2_SPEED	400000	/* I2C speed in Hz */
+#define CONFIG_SYS_FSL_I2C2_SLAVE	0x7F
+#define CONFIG_SYS_FSL_I2C_OFFSET	0x118000
+#define CONFIG_SYS_FSL_I2C2_OFFSET	0x119000
+
+/* I2C bus multiplexer */
+#define I2C_MUX_PCA_ADDR                0x70
+#define I2C_MUX_CH_DEFAULT      0x8
+
+
+/*
+ * eSPI - Enhanced SPI
+ */
+#define CONFIG_FSL_ESPI
+#define CONFIG_SPI_FLASH
+#define CONFIG_SPI_FLASH_STMICRO
+#define CONFIG_CMD_SF
+#define CONFIG_SF_DEFAULT_SPEED         10000000
+#define CONFIG_SF_DEFAULT_MODE          0
+#define CONFIG_ENV_SPI_BUS              0
+#define CONFIG_ENV_SPI_CS               0
+#define CONFIG_ENV_SPI_MAX_HZ           10000000
+#define CONFIG_ENV_SPI_MODE             0
+
+/*
+ * General PCI
+ * Memory space is mapped 1-1, but I/O space must start from 0.
+ */
+
+#ifdef CONFIG_PCI
+/* controller 1, direct to uli, tgtid 3, Base address 20000 */
+#ifdef CONFIG_PCIE1
+#define	CONFIG_SYS_PCIE1_MEM_VIRT	0x80000000
+#define	CONFIG_SYS_PCIE1_MEM_BUS	0xe0000000
+#define	CONFIG_SYS_PCIE1_MEM_PHYS	0xc00000000ull
+#define CONFIG_SYS_PCIE1_MEM_SIZE	0x10000000	/* 256M */
+#define CONFIG_SYS_PCIE1_IO_VIRT	0xf8000000
+#define CONFIG_SYS_PCIE1_IO_BUS		0x00000000
+#define CONFIG_SYS_PCIE1_IO_PHYS	0xff8000000ull
+#define CONFIG_SYS_PCIE1_IO_SIZE	0x00010000	/* 64k */
+#endif
+
+/* controller 2, Slot 2, tgtid 2, Base address 201000 */
+#ifdef CONFIG_PCIE2
+#define CONFIG_SYS_PCIE2_MEM_VIRT	0x90000000
+#define CONFIG_SYS_PCIE2_MEM_BUS	0xe0000000
+#define CONFIG_SYS_PCIE2_MEM_PHYS	0xc10000000ull
+#define CONFIG_SYS_PCIE2_MEM_SIZE	0x10000000	/* 256M */
+#define CONFIG_SYS_PCIE2_IO_VIRT	0xf8010000
+#define CONFIG_SYS_PCIE2_IO_BUS		0x00000000
+#define CONFIG_SYS_PCIE2_IO_PHYS	0xff8010000ull
+#define CONFIG_SYS_PCIE2_IO_SIZE	0x00010000	/* 64k */
+#endif
+
+/* controller 3, Slot 1, tgtid 1, Base address 202000 */
+#ifdef CONFIG_PCIE3
+#define CONFIG_SYS_PCIE3_MEM_VIRT	0xa0000000
+#define CONFIG_SYS_PCIE3_MEM_BUS	0xe0000000
+#define CONFIG_SYS_PCIE3_MEM_PHYS	0xc20000000ull
+#define CONFIG_SYS_PCIE3_MEM_SIZE	0x10000000	/* 256M */
+#define CONFIG_SYS_PCIE3_IO_VIRT	0xf8020000
+#define CONFIG_SYS_PCIE3_IO_BUS		0x00000000
+#define CONFIG_SYS_PCIE3_IO_PHYS	0xff8020000ull
+#define CONFIG_SYS_PCIE3_IO_SIZE	0x00010000	/* 64k */
+#endif
+
+/* controller 4, Base address 203000 */
+#ifdef CONFIG_PCIE4
+#define CONFIG_SYS_PCIE4_MEM_VIRT	0xb0000000
+#define CONFIG_SYS_PCIE4_MEM_BUS	0xe0000000
+#define CONFIG_SYS_PCIE4_MEM_PHYS	0xc30000000ull
+#define CONFIG_SYS_PCIE4_MEM_SIZE	0x10000000	/* 256M */
+#define CONFIG_SYS_PCIE4_IO_VIRT	0xf8030000
+#define CONFIG_SYS_PCIE4_IO_BUS		0x00000000
+#define CONFIG_SYS_PCIE4_IO_PHYS	0xff8030000ull
+#define CONFIG_SYS_PCIE4_IO_SIZE	0x00010000	/* 64k */
+#endif
+
+#define CONFIG_PCI_PNP			/* do pci plug-and-play */
+#define CONFIG_E1000
+
+#define CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
+#define CONFIG_DOS_PARTITION
+#endif	/* CONFIG_PCI */
+
+/* SATA */
+#define CONFIG_FSL_SATA_V2
+#ifdef CONFIG_FSL_SATA_V2
+#define CONFIG_LIBATA
+#define CONFIG_FSL_SATA
+
+#define CONFIG_SYS_SATA_MAX_DEVICE	1
+#define CONFIG_SATA1
+#define CONFIG_SYS_SATA1		CONFIG_SYS_MPC85xx_SATA1_ADDR
+#define CONFIG_SYS_SATA1_FLAGS		FLAGS_DMA
+
+#define CONFIG_LBA48
+#define CONFIG_CMD_SATA
+#define CONFIG_DOS_PARTITION
+#define CONFIG_CMD_EXT2
+#endif
+
+/*
+* USB
+*/
+#define CONFIG_HAS_FSL_DR_USB
+
+#ifdef CONFIG_HAS_FSL_DR_USB
+#define CONFIG_USB_EHCI
+
+#ifdef CONFIG_USB_EHCI
+#define CONFIG_CMD_USB
+#define CONFIG_USB_STORAGE
+#define CONFIG_USB_EHCI_FSL
+#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
+#define CONFIG_CMD_EXT2
+#endif
+#endif
+
+#define CONFIG_MMC
+
+#ifdef CONFIG_MMC
+#define CONFIG_FSL_ESDHC
+#define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
+#define CONFIG_CMD_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_FAT
+#define CONFIG_DOS_PARTITION
+#endif
+
+/* Qman/Bman */
+#ifndef CONFIG_NOBQFMAN
+#define CONFIG_SYS_DPAA_QBMAN		/* Support Q/Bman */
+#define CONFIG_SYS_BMAN_NUM_PORTALS	25
+#define CONFIG_SYS_BMAN_MEM_BASE	0xf4000000
+#define CONFIG_SYS_BMAN_MEM_PHYS	0xff4000000ull
+#define CONFIG_SYS_BMAN_MEM_SIZE	0x02000000
+#define CONFIG_SYS_QMAN_NUM_PORTALS	25
+#define CONFIG_SYS_QMAN_MEM_BASE	0xf6000000
+#define CONFIG_SYS_QMAN_MEM_PHYS	0xff6000000ull
+#define CONFIG_SYS_QMAN_MEM_SIZE	0x02000000
+
+#define CONFIG_SYS_DPAA_FMAN
+#define CONFIG_SYS_DPAA_PME
+
+/* Default address of microcode for the Linux Fman driver */
+#if defined(CONFIG_SPIFLASH)
+/*
+ * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
+ * env, so we got 0x110000.
+ */
+#define CONFIG_SYS_QE_FW_IN_SPIFLASH
+#define CONFIG_SYS_QE_FMAN_FW_ADDR	0x110000
+#elif defined(CONFIG_SDCARD)
+/*
+ * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
+ * about 825KB (1650 blocks), Env is stored after the image, and the env size is
+ * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680.
+ */
+#define CONFIG_SYS_QE_FMAN_FW_IN_MMC
+#define CONFIG_SYS_QE_FMAN_FW_ADDR	(512 * 1680)
+#elif defined(CONFIG_NAND)
+#define CONFIG_SYS_QE_FMAN_FW_IN_NAND
+#define CONFIG_SYS_QE_FMAN_FW_ADDR	(4 * CONFIG_SYS_NAND_BLOCK_SIZE)
+#else
+#define CONFIG_SYS_QE_FMAN_FW_IN_NOR
+#define CONFIG_SYS_QE_FMAN_FW_ADDR		0xEFF00000
+#endif
+#define CONFIG_SYS_QE_FMAN_FW_LENGTH	0x10000
+#define CONFIG_SYS_FDT_PAD		(0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
+#endif /* CONFIG_NOBQFMAN */
+
+#ifdef CONFIG_SYS_DPAA_FMAN
+#define CONFIG_FMAN_ENET
+#define CONFIG_PHY_VITESSE
+#define CONFIG_PHY_REALTEK
+#endif
+
+#ifdef CONFIG_FMAN_ENET
+#define CONFIG_SYS_SGMII1_PHY_ADDR		0x03
+#define CONFIG_SYS_RGMII1_PHY_ADDR		0x01
+#define CONFIG_SYS_RGMII2_PHY_ADDR		0x02
+
+#define CONFIG_MII		/* MII PHY management */
+#define CONFIG_ETHPRIME		"FM1@DTSEC4"
+#define CONFIG_PHY_GIGE		/* Include GbE speed/duplex detection */
+#endif
+
+/*
+ * Environment
+ */
+#define CONFIG_LOADS_ECHO		/* echo on for serial download */
+#define CONFIG_SYS_LOADS_BAUD_CHANGE	/* allow baudrate change */
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_ERRATA
+#define CONFIG_CMD_GREPENV
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_REGINFO
+#define CONFIG_CMD_SETEXPR
+
+#ifdef CONFIG_PCI
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_NET
+#endif
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP			/* undef to save memory	*/
+#define CONFIG_CMDLINE_EDITING			/* Command-line editing */
+#define CONFIG_AUTO_COMPLETE			/* add autocompletion support */
+#define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
+#define CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt */
+#ifdef CONFIG_CMD_KGDB
+#define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size */
+#else
+#define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size */
+#endif
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
+#define CONFIG_SYS_MAXARGS	16		/* max number of command args */
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 64 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ	(64 << 20)	/* Initial map for Linux*/
+#define CONFIG_SYS_BOOTM_LEN	(64 << 20)	/* Increase max gunzip size */
+
+#ifdef CONFIG_CMD_KGDB
+#define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
+#endif
+
+/*
+ * Environment Configuration
+ */
+#define CONFIG_ROOTPATH		"/opt/nfsroot"
+#define CONFIG_BOOTFILE		"uImage"
+#define CONFIG_UBOOTPATH	"u-boot.bin"	/* U-Boot image on TFTP server*/
+
+/* default location for tftp and bootm */
+#define CONFIG_LOADADDR		1000000
+
+#define CONFIG_BOOTDELAY	10	/*-1 disables auto-boot*/
+
+#define CONFIG_BAUDRATE	115200
+
+#define __USB_PHY_TYPE	utmi
+
+#define	CONFIG_EXTRA_ENV_SETTINGS				\
+	"hwconfig=fsl_ddr:bank_intlv=cs0_cs1;"			\
+	"usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) ";"\
+	"usb2:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
+	"netdev=eth0\0"						\
+	"uboot=" __stringify(CONFIG_UBOOTPATH) "\0"		\
+	"ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"	\
+	"tftpflash=tftpboot $loadaddr $uboot && "		\
+	"protect off $ubootaddr +$filesize && "			\
+	"erase $ubootaddr +$filesize && "			\
+	"cp.b $loadaddr $ubootaddr $filesize && "		\
+	"protect on $ubootaddr +$filesize && "			\
+	"cmp.b $loadaddr $ubootaddr $filesize\0"		\
+	"consoledev=ttyS0\0"					\
+	"ramdiskaddr=2000000\0"					\
+	"ramdiskfile=t1040rdb/ramdisk.uboot\0"			\
+	"fdtaddr=c00000\0"					\
+	"fdtfile=t1040rdb/t1040rdb.dtb\0"			\
+	"bdev=sda3\0"						\
+	"c=ffe\0"
+
+#define CONFIG_LINUX                       \
+	"setenv bootargs root=/dev/ram rw "            \
+	"console=$consoledev,$baudrate $othbootargs;"  \
+	"setenv ramdiskaddr 0x02000000;"               \
+	"setenv fdtaddr 0x00c00000;"		       \
+	"setenv loadaddr 0x1000000;"		       \
+	"bootm $loadaddr $ramdiskaddr $fdtaddr"
+
+#define CONFIG_HDBOOT					\
+	"setenv bootargs root=/dev/$bdev rw "		\
+	"console=$consoledev,$baudrate $othbootargs;"	\
+	"tftp $loadaddr $bootfile;"			\
+	"tftp $fdtaddr $fdtfile;"			\
+	"bootm $loadaddr - $fdtaddr"
+
+#define CONFIG_NFSBOOTCOMMAND			\
+	"setenv bootargs root=/dev/nfs rw "	\
+	"nfsroot=$serverip:$rootpath "		\
+	"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
+	"console=$consoledev,$baudrate $othbootargs;"	\
+	"tftp $loadaddr $bootfile;"		\
+	"tftp $fdtaddr $fdtfile;"		\
+	"bootm $loadaddr - $fdtaddr"
+
+#define CONFIG_RAMBOOTCOMMAND				\
+	"setenv bootargs root=/dev/ram rw "		\
+	"console=$consoledev,$baudrate $othbootargs;"	\
+	"tftp $ramdiskaddr $ramdiskfile;"		\
+	"tftp $loadaddr $bootfile;"			\
+	"tftp $fdtaddr $fdtfile;"			\
+	"bootm $loadaddr $ramdiskaddr $fdtaddr"
+
+#define CONFIG_BOOTCOMMAND		CONFIG_LINUX
+
+#ifdef CONFIG_SECURE_BOOT
+#include <asm/fsl_secure_boot.h>
+#endif
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/T1042RDB_PI.h b/include/configs/T1042RDB_PI.h
new file mode 100644
index 0000000000..68656e6ef1
--- /dev/null
+++ b/include/configs/T1042RDB_PI.h
@@ -0,0 +1,695 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * T1042RDB_PI board configuration file
+ */
+#define CONFIG_T104xRDB
+#define CONFIG_T1042RDB_PI
+#define CONFIG_PHYS_64BIT
+
+#ifdef CONFIG_RAMBOOT_PBL
+#define CONFIG_RAMBOOT_TEXT_BASE	CONFIG_SYS_TEXT_BASE
+#define CONFIG_RESET_VECTOR_ADDRESS	0xfffffffc
+#endif
+
+/* High Level Configuration Options */
+#define CONFIG_BOOKE
+#define CONFIG_E500			/* BOOKE e500 family */
+#define CONFIG_E500MC			/* BOOKE e500mc family */
+#define CONFIG_SYS_BOOK3E_HV		/* Category E.HV supported */
+#define CONFIG_MP			/* support multiple processors */
+
+#ifndef CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_TEXT_BASE	0xeff40000
+#endif
+
+#ifndef CONFIG_RESET_VECTOR_ADDRESS
+#define CONFIG_RESET_VECTOR_ADDRESS	0xeffffffc
+#endif
+
+#define CONFIG_SYS_FSL_CPC		/* Corenet Platform Cache */
+#define CONFIG_SYS_NUM_CPC		CONFIG_NUM_DDR_CONTROLLERS
+#define CONFIG_FSL_IFC			/* Enable IFC Support */
+#define CONFIG_PCI			/* Enable PCI/PCIE */
+#define CONFIG_PCI_INDIRECT_BRIDGE
+#define CONFIG_PCIE1			/* PCIE controler 1 */
+#define CONFIG_PCIE2			/* PCIE controler 2 */
+#define CONFIG_PCIE3			/* PCIE controler 3 */
+#define CONFIG_PCIE4			/* PCIE controler 4 */
+
+#define CONFIG_FSL_PCI_INIT		/* Use common FSL init code */
+#define CONFIG_SYS_PCI_64BIT		/* enable 64-bit PCI resources */
+
+#define CONFIG_FSL_LAW			/* Use common FSL init code */
+
+#define CONFIG_ENV_OVERWRITE
+
+#ifdef CONFIG_SYS_NO_FLASH
+#define CONFIG_ENV_IS_NOWHERE
+#else
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
+#endif
+
+#ifndef CONFIG_SYS_NO_FLASH
+#if defined(CONFIG_SPIFLASH)
+#define CONFIG_SYS_EXTRA_ENV_RELOC
+#define CONFIG_ENV_IS_IN_SPI_FLASH
+#define CONFIG_ENV_SIZE                 0x2000          /* 8KB */
+#define CONFIG_ENV_OFFSET               0x100000        /* 1MB */
+#define CONFIG_ENV_SECT_SIZE            0x10000
+#elif defined(CONFIG_SDCARD)
+#define CONFIG_SYS_EXTRA_ENV_RELOC
+#define CONFIG_ENV_IS_IN_MMC
+#define CONFIG_SYS_MMC_ENV_DEV          0
+#define CONFIG_ENV_SIZE			0x2000
+#define CONFIG_ENV_OFFSET		(512 * 1658)
+#elif defined(CONFIG_NAND)
+#define CONFIG_SYS_EXTRA_ENV_RELOC
+#define CONFIG_ENV_IS_IN_NAND
+#define CONFIG_ENV_SIZE			CONFIG_SYS_NAND_BLOCK_SIZE
+#define CONFIG_ENV_OFFSET		(3 * CONFIG_SYS_NAND_BLOCK_SIZE)
+#else
+#define CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE		0x2000
+#define CONFIG_ENV_SECT_SIZE	0x20000 /* 128K (one sector) */
+#endif
+#else /* CONFIG_SYS_NO_FLASH */
+#define CONFIG_ENV_SIZE                0x2000
+#define CONFIG_ENV_SECT_SIZE   0x20000 /* 128K (one sector) */
+#endif
+
+#define CONFIG_SYS_CLK_FREQ	100000000
+#define CONFIG_DDR_CLK_FREQ	66666666
+
+/*
+ * These can be toggled for performance analysis, otherwise use default.
+ */
+#define CONFIG_SYS_CACHE_STASHING
+#define CONFIG_BACKSIDE_L2_CACHE
+#define CONFIG_SYS_INIT_L2CSR0		L2CSR0_L2E
+#define CONFIG_BTB			/* toggle branch predition */
+#define CONFIG_DDR_ECC
+#ifdef CONFIG_DDR_ECC
+#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
+#define CONFIG_MEM_INIT_VALUE		0xdeadbeef
+#endif
+
+#define CONFIG_ENABLE_36BIT_PHYS
+
+#define CONFIG_ADDR_MAP
+#define CONFIG_SYS_NUM_ADDR_MAP		64	/* number of TLB1 entries */
+
+#define CONFIG_SYS_MEMTEST_START	0x00200000	/* memtest works on */
+#define CONFIG_SYS_MEMTEST_END		0x00400000
+#define CONFIG_SYS_ALT_MEMTEST
+#define CONFIG_PANIC_HANG	/* do not reset board on panic */
+
+/*
+ *  Config the L3 Cache as L3 SRAM
+ */
+#define CONFIG_SYS_INIT_L3_ADDR		0xFFFC0000
+
+#define CONFIG_SYS_DCSRBAR		0xf0000000
+#define CONFIG_SYS_DCSRBAR_PHYS		0xf00000000ull
+
+/*
+ * DDR Setup
+ */
+#define CONFIG_VERY_BIG_RAM
+#define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000
+#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
+
+/* CONFIG_NUM_DDR_CONTROLLERS is defined in include/asm/config_mpc85xx.h */
+#define CONFIG_DIMM_SLOTS_PER_CTLR	1
+#define CONFIG_CHIP_SELECTS_PER_CTRL	(2 * CONFIG_DIMM_SLOTS_PER_CTLR)
+
+#define CONFIG_DDR_SPD
+#define CONFIG_SYS_DDR_RAW_TIMING
+#define CONFIG_SYS_FSL_DDR3
+
+#define CONFIG_SYS_SPD_BUS_NUM	0
+#define SPD_EEPROM_ADDRESS	0x51
+
+#define CONFIG_SYS_SDRAM_SIZE	4096	/* for fixed parameter use */
+
+/*
+ * IFC Definitions
+ */
+#define CONFIG_SYS_FLASH_BASE	0xe8000000
+#define CONFIG_SYS_FLASH_BASE_PHYS	(0xf00000000ull | CONFIG_SYS_FLASH_BASE)
+
+#define CONFIG_SYS_NOR_CSPR_EXT	(0xf)
+#define CONFIG_SYS_NOR_CSPR	(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE) | \
+				CSPR_PORT_SIZE_16 | \
+				CSPR_MSEL_NOR | \
+				CSPR_V)
+#define CONFIG_SYS_NOR_AMASK	IFC_AMASK(128*1024*1024)
+/* NOR Flash Timing Params */
+#define CONFIG_SYS_NOR_CSOR	CSOR_NAND_TRHZ_80
+#define CONFIG_SYS_NOR_FTIM0	(FTIM0_NOR_TACSE(0x4) | \
+				FTIM0_NOR_TEADC(0x5) | \
+				FTIM0_NOR_TEAHC(0x5))
+#define CONFIG_SYS_NOR_FTIM1	(FTIM1_NOR_TACO(0x35) | \
+				FTIM1_NOR_TRAD_NOR(0x1A) |\
+				FTIM1_NOR_TSEQRAD_NOR(0x13))
+#define CONFIG_SYS_NOR_FTIM2	(FTIM2_NOR_TCS(0x4) | \
+				FTIM2_NOR_TCH(0x4) | \
+				FTIM2_NOR_TWPH(0x0E) | \
+				FTIM2_NOR_TWP(0x1c))
+#define CONFIG_SYS_NOR_FTIM3	0x0
+
+#define CONFIG_SYS_FLASH_QUIET_TEST
+#define CONFIG_FLASH_SHOW_PROGRESS	45 /* count down from 45/5: 9..1 */
+
+#define CONFIG_SYS_MAX_FLASH_BANKS	2	/* number of banks */
+#define CONFIG_SYS_MAX_FLASH_SECT	1024	/* sectors per device */
+#define CONFIG_SYS_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */
+
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+#define CONFIG_SYS_FLASH_BANKS_LIST	{CONFIG_SYS_FLASH_BASE_PHYS}
+
+/* CPLD on IFC */
+#define CONFIG_SYS_CPLD_BASE	0xffdf0000
+#define CONFIG_SYS_CPLD_BASE_PHYS	(0xf00000000ull | CONFIG_SYS_CPLD_BASE)
+#define CONFIG_SYS_CSPR2_EXT	(0xf)
+#define CONFIG_SYS_CSPR2	(CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \
+				| CSPR_PORT_SIZE_8 \
+				| CSPR_MSEL_GPCM \
+				| CSPR_V)
+#define CONFIG_SYS_AMASK2	IFC_AMASK(64*1024)
+#define CONFIG_SYS_CSOR2	0x0
+/* CPLD Timing parameters for IFC CS2 */
+#define CONFIG_SYS_CS2_FTIM0		(FTIM0_GPCM_TACSE(0x0e) | \
+					FTIM0_GPCM_TEADC(0x0e) | \
+					FTIM0_GPCM_TEAHC(0x0e))
+#define CONFIG_SYS_CS2_FTIM1		(FTIM1_GPCM_TACO(0x0e) | \
+					FTIM1_GPCM_TRAD(0x1f))
+#define CONFIG_SYS_CS2_FTIM2		(FTIM2_GPCM_TCS(0x0e) | \
+					FTIM2_GPCM_TCH(0x0) | \
+					FTIM2_GPCM_TWP(0x1f))
+#define CONFIG_SYS_CS2_FTIM3		0x0
+
+/* NAND Flash on IFC */
+#define CONFIG_NAND_FSL_IFC
+#define CONFIG_SYS_NAND_BASE		0xff800000
+#define CONFIG_SYS_NAND_BASE_PHYS	(0xf00000000ull | CONFIG_SYS_NAND_BASE)
+
+#define CONFIG_SYS_NAND_CSPR_EXT	(0xf)
+#define CONFIG_SYS_NAND_CSPR	(CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
+				| CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
+				| CSPR_MSEL_NAND	/* MSEL = NAND */ \
+				| CSPR_V)
+#define CONFIG_SYS_NAND_AMASK	IFC_AMASK(64*1024)
+
+#define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
+				| CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
+				| CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
+				| CSOR_NAND_RAL_3	/* RAL = 3Byes */ \
+				| CSOR_NAND_PGS_4K	/* Page Size = 4K */ \
+				| CSOR_NAND_SPRZ_224/* Spare size = 224 */ \
+				| CSOR_NAND_PB(64))	/*Pages Per Block = 64*/
+
+#define CONFIG_SYS_NAND_ONFI_DETECTION
+
+/* ONFI NAND Flash mode0 Timing Params */
+#define CONFIG_SYS_NAND_FTIM0		(FTIM0_NAND_TCCST(0x07) | \
+					FTIM0_NAND_TWP(0x18)   | \
+					FTIM0_NAND_TWCHT(0x07) | \
+					FTIM0_NAND_TWH(0x0a))
+#define CONFIG_SYS_NAND_FTIM1		(FTIM1_NAND_TADLE(0x32) | \
+					FTIM1_NAND_TWBE(0x39)  | \
+					FTIM1_NAND_TRR(0x0e)   | \
+					FTIM1_NAND_TRP(0x18))
+#define CONFIG_SYS_NAND_FTIM2		(FTIM2_NAND_TRAD(0x0f) | \
+					FTIM2_NAND_TREH(0x0a) | \
+					FTIM2_NAND_TWHRE(0x1e))
+#define CONFIG_SYS_NAND_FTIM3		0x0
+
+#define CONFIG_SYS_NAND_DDR_LAW		11
+#define CONFIG_SYS_NAND_BASE_LIST	{ CONFIG_SYS_NAND_BASE }
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+#define CONFIG_MTD_NAND_VERIFY_WRITE
+#define CONFIG_CMD_NAND
+
+#define CONFIG_SYS_NAND_BLOCK_SIZE	(512 * 1024)
+
+#if defined(CONFIG_NAND)
+#define CONFIG_SYS_CSPR0_EXT		CONFIG_SYS_NAND_CSPR_EXT
+#define CONFIG_SYS_CSPR0		CONFIG_SYS_NAND_CSPR
+#define CONFIG_SYS_AMASK0		CONFIG_SYS_NAND_AMASK
+#define CONFIG_SYS_CSOR0		CONFIG_SYS_NAND_CSOR
+#define CONFIG_SYS_CS0_FTIM0		CONFIG_SYS_NAND_FTIM0
+#define CONFIG_SYS_CS0_FTIM1		CONFIG_SYS_NAND_FTIM1
+#define CONFIG_SYS_CS0_FTIM2		CONFIG_SYS_NAND_FTIM2
+#define CONFIG_SYS_CS0_FTIM3		CONFIG_SYS_NAND_FTIM3
+#define CONFIG_SYS_CSPR1_EXT		CONFIG_SYS_NOR_CSPR_EXT
+#define CONFIG_SYS_CSPR1		CONFIG_SYS_NOR_CSPR
+#define CONFIG_SYS_AMASK1		CONFIG_SYS_NOR_AMASK
+#define CONFIG_SYS_CSOR1		CONFIG_SYS_NOR_CSOR
+#define CONFIG_SYS_CS1_FTIM0		CONFIG_SYS_NOR_FTIM0
+#define CONFIG_SYS_CS1_FTIM1		CONFIG_SYS_NOR_FTIM1
+#define CONFIG_SYS_CS1_FTIM2		CONFIG_SYS_NOR_FTIM2
+#define CONFIG_SYS_CS1_FTIM3		CONFIG_SYS_NOR_FTIM3
+#else
+#define CONFIG_SYS_CSPR0_EXT		CONFIG_SYS_NOR_CSPR_EXT
+#define CONFIG_SYS_CSPR0		CONFIG_SYS_NOR_CSPR
+#define CONFIG_SYS_AMASK0		CONFIG_SYS_NOR_AMASK
+#define CONFIG_SYS_CSOR0		CONFIG_SYS_NOR_CSOR
+#define CONFIG_SYS_CS0_FTIM0		CONFIG_SYS_NOR_FTIM0
+#define CONFIG_SYS_CS0_FTIM1		CONFIG_SYS_NOR_FTIM1
+#define CONFIG_SYS_CS0_FTIM2		CONFIG_SYS_NOR_FTIM2
+#define CONFIG_SYS_CS0_FTIM3		CONFIG_SYS_NOR_FTIM3
+#define CONFIG_SYS_CSPR1_EXT		CONFIG_SYS_NAND_CSPR_EXT
+#define CONFIG_SYS_CSPR1		CONFIG_SYS_NAND_CSPR
+#define CONFIG_SYS_AMASK1		CONFIG_SYS_NAND_AMASK
+#define CONFIG_SYS_CSOR1		CONFIG_SYS_NAND_CSOR
+#define CONFIG_SYS_CS1_FTIM0		CONFIG_SYS_NAND_FTIM0
+#define CONFIG_SYS_CS1_FTIM1		CONFIG_SYS_NAND_FTIM1
+#define CONFIG_SYS_CS1_FTIM2		CONFIG_SYS_NAND_FTIM2
+#define CONFIG_SYS_CS1_FTIM3		CONFIG_SYS_NAND_FTIM3
+#endif
+
+#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_TEXT_BASE
+
+#if defined(CONFIG_RAMBOOT_PBL)
+#define CONFIG_SYS_RAMBOOT
+#endif
+
+#define CONFIG_BOARD_EARLY_INIT_R
+#define CONFIG_MISC_INIT_R
+
+#define CONFIG_HWCONFIG
+
+/* define to use L1 as initial stack */
+#define CONFIG_L1_INIT_RAM
+#define CONFIG_SYS_INIT_RAM_LOCK
+#define CONFIG_SYS_INIT_RAM_ADDR	0xfdd00000	/* Initial L1 address */
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH	0xf
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW	0xfe0ec000
+/* The assembler doesn't like typecast */
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
+	((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
+	  CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
+#define CONFIG_SYS_INIT_RAM_SIZE		0x00004000
+
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - \
+					GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+#define CONFIG_SYS_MONITOR_LEN		(512 * 1024)
+#define CONFIG_SYS_MALLOC_LEN		(4 * 1024 * 1024)
+
+/* Serial Port - controlled on board with jumper J8
+ * open - index 2
+ * shorted - index 1
+ */
+#define CONFIG_CONS_INDEX	1
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	1
+#define CONFIG_SYS_NS16550_CLK		(get_bus_freq(0)/2)
+
+#define CONFIG_SYS_BAUDRATE_TABLE	\
+	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
+
+#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_CCSRBAR+0x11C500)
+#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_CCSRBAR+0x11C600)
+#define CONFIG_SYS_NS16550_COM3	(CONFIG_SYS_CCSRBAR+0x11D500)
+#define CONFIG_SYS_NS16550_COM4	(CONFIG_SYS_CCSRBAR+0x11D600)
+#define CONFIG_SERIAL_MULTI		/* Enable both serial ports */
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV	/* determine from environment */
+
+/* Use the HUSH parser */
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
+
+/* pass open firmware flat tree */
+#define CONFIG_OF_LIBFDT
+#define CONFIG_OF_BOARD_SETUP
+#define CONFIG_OF_STDOUT_VIA_ALIAS
+
+/* new uImage format support */
+#define CONFIG_FIT
+#define CONFIG_FIT_VERBOSE	/* enable fit_format_{error,warning}() */
+
+/* I2C */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_FSL		/* Use FSL common I2C driver */
+#define CONFIG_SYS_FSL_I2C_SPEED	400000	/* I2C speed in Hz */
+#define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
+#define CONFIG_SYS_FSL_I2C2_SPEED	400000	/* I2C speed in Hz */
+#define CONFIG_SYS_FSL_I2C2_SLAVE	0x7F
+#define CONFIG_SYS_FSL_I2C_OFFSET	0x118000
+#define CONFIG_SYS_FSL_I2C2_OFFSET	0x119000
+
+/* I2C bus multiplexer */
+#define I2C_MUX_PCA_ADDR                0x70
+
+/*
+ * RTC configuration
+ */
+#define RTC
+#define CONFIG_RTC_DS1337               1
+#define CONFIG_SYS_I2C_RTC_ADDR         0x68
+
+/*DVI encoder*/
+#define CONFIG_HDMI_ENCODER_I2C_ADDR  0x75
+
+/*
+ * eSPI - Enhanced SPI
+ */
+#define CONFIG_FSL_ESPI
+#define CONFIG_SPI_FLASH
+#define CONFIG_SPI_FLASH_STMICRO
+#define CONFIG_CMD_SF
+#define CONFIG_SF_DEFAULT_SPEED         10000000
+#define CONFIG_SF_DEFAULT_MODE          0
+#define CONFIG_ENV_SPI_BUS              0
+#define CONFIG_ENV_SPI_CS               0
+#define CONFIG_ENV_SPI_MAX_HZ           10000000
+#define CONFIG_ENV_SPI_MODE             0
+
+/*
+ * General PCI
+ * Memory space is mapped 1-1, but I/O space must start from 0.
+ */
+
+#ifdef CONFIG_PCI
+/* controller 1, direct to uli, tgtid 3, Base address 20000 */
+#ifdef CONFIG_PCIE1
+#define	CONFIG_SYS_PCIE1_MEM_VIRT	0x80000000
+#define	CONFIG_SYS_PCIE1_MEM_BUS	0xe0000000
+#define	CONFIG_SYS_PCIE1_MEM_PHYS	0xc00000000ull
+#define CONFIG_SYS_PCIE1_MEM_SIZE	0x10000000	/* 256M */
+#define CONFIG_SYS_PCIE1_IO_VIRT	0xf8000000
+#define CONFIG_SYS_PCIE1_IO_BUS		0x00000000
+#define CONFIG_SYS_PCIE1_IO_PHYS	0xff8000000ull
+#define CONFIG_SYS_PCIE1_IO_SIZE	0x00010000	/* 64k */
+#endif
+
+/* controller 2, Slot 2, tgtid 2, Base address 201000 */
+#ifdef CONFIG_PCIE2
+#define CONFIG_SYS_PCIE2_MEM_VIRT	0x90000000
+#define CONFIG_SYS_PCIE2_MEM_BUS	0xe0000000
+#define CONFIG_SYS_PCIE2_MEM_PHYS	0xc10000000ull
+#define CONFIG_SYS_PCIE2_MEM_SIZE	0x10000000	/* 256M */
+#define CONFIG_SYS_PCIE2_IO_VIRT	0xf8010000
+#define CONFIG_SYS_PCIE2_IO_BUS		0x00000000
+#define CONFIG_SYS_PCIE2_IO_PHYS	0xff8010000ull
+#define CONFIG_SYS_PCIE2_IO_SIZE	0x00010000	/* 64k */
+#endif
+
+/* controller 3, Slot 1, tgtid 1, Base address 202000 */
+#ifdef CONFIG_PCIE3
+#define CONFIG_SYS_PCIE3_MEM_VIRT	0xa0000000
+#define CONFIG_SYS_PCIE3_MEM_BUS	0xe0000000
+#define CONFIG_SYS_PCIE3_MEM_PHYS	0xc20000000ull
+#define CONFIG_SYS_PCIE3_MEM_SIZE	0x10000000	/* 256M */
+#define CONFIG_SYS_PCIE3_IO_VIRT	0xf8020000
+#define CONFIG_SYS_PCIE3_IO_BUS		0x00000000
+#define CONFIG_SYS_PCIE3_IO_PHYS	0xff8020000ull
+#define CONFIG_SYS_PCIE3_IO_SIZE	0x00010000	/* 64k */
+#endif
+
+/* controller 4, Base address 203000 */
+#ifdef CONFIG_PCIE4
+#define CONFIG_SYS_PCIE4_MEM_VIRT	0xb0000000
+#define CONFIG_SYS_PCIE4_MEM_BUS	0xe0000000
+#define CONFIG_SYS_PCIE4_MEM_PHYS	0xc30000000ull
+#define CONFIG_SYS_PCIE4_MEM_SIZE	0x10000000	/* 256M */
+#define CONFIG_SYS_PCIE4_IO_VIRT	0xf8030000
+#define CONFIG_SYS_PCIE4_IO_BUS		0x00000000
+#define CONFIG_SYS_PCIE4_IO_PHYS	0xff8030000ull
+#define CONFIG_SYS_PCIE4_IO_SIZE	0x00010000	/* 64k */
+#endif
+
+#define CONFIG_PCI_PNP			/* do pci plug-and-play */
+#define CONFIG_E1000
+
+#define CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
+#define CONFIG_DOS_PARTITION
+#endif	/* CONFIG_PCI */
+
+/* SATA */
+#define CONFIG_FSL_SATA_V2
+#ifdef CONFIG_FSL_SATA_V2
+#define CONFIG_LIBATA
+#define CONFIG_FSL_SATA
+
+#define CONFIG_SYS_SATA_MAX_DEVICE	1
+#define CONFIG_SATA1
+#define CONFIG_SYS_SATA1		CONFIG_SYS_MPC85xx_SATA1_ADDR
+#define CONFIG_SYS_SATA1_FLAGS		FLAGS_DMA
+
+#define CONFIG_LBA48
+#define CONFIG_CMD_SATA
+#define CONFIG_DOS_PARTITION
+#define CONFIG_CMD_EXT2
+#endif
+
+/*
+* USB
+*/
+#define CONFIG_HAS_FSL_DR_USB
+
+#ifdef CONFIG_HAS_FSL_DR_USB
+#define CONFIG_USB_EHCI
+
+#ifdef CONFIG_USB_EHCI
+#define CONFIG_CMD_USB
+#define CONFIG_USB_STORAGE
+#define CONFIG_USB_EHCI_FSL
+#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
+#define CONFIG_CMD_EXT2
+#endif
+#endif
+
+#define CONFIG_MMC
+
+#ifdef CONFIG_MMC
+#define CONFIG_FSL_ESDHC
+#define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
+#define CONFIG_CMD_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_FAT
+#define CONFIG_DOS_PARTITION
+#endif
+
+/* Qman/Bman */
+#ifndef CONFIG_NOBQFMAN
+#define CONFIG_SYS_DPAA_QBMAN		/* Support Q/Bman */
+#define CONFIG_SYS_BMAN_NUM_PORTALS	25
+#define CONFIG_SYS_BMAN_MEM_BASE	0xf4000000
+#define CONFIG_SYS_BMAN_MEM_PHYS	0xff4000000ull
+#define CONFIG_SYS_BMAN_MEM_SIZE	0x02000000
+#define CONFIG_SYS_QMAN_NUM_PORTALS	25
+#define CONFIG_SYS_QMAN_MEM_BASE	0xf6000000
+#define CONFIG_SYS_QMAN_MEM_PHYS	0xff6000000ull
+#define CONFIG_SYS_QMAN_MEM_SIZE	0x02000000
+
+#define CONFIG_SYS_DPAA_FMAN
+#define CONFIG_SYS_DPAA_PME
+
+/* Default address of microcode for the Linux Fman driver */
+#if defined(CONFIG_SPIFLASH)
+/*
+ * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
+ * env, so we got 0x110000.
+ */
+#define CONFIG_SYS_QE_FW_IN_SPIFLASH
+#define CONFIG_SYS_QE_FMAN_FW_ADDR	0x110000
+#elif defined(CONFIG_SDCARD)
+/*
+ * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
+ * about 825KB (1650 blocks), Env is stored after the image, and the env size is
+ * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680.
+ */
+#define CONFIG_SYS_QE_FMAN_FW_IN_MMC
+#define CONFIG_SYS_QE_FMAN_FW_ADDR	(512 * 1680)
+#elif defined(CONFIG_NAND)
+#define CONFIG_SYS_QE_FMAN_FW_IN_NAND
+#define CONFIG_SYS_QE_FMAN_FW_ADDR	(4 * CONFIG_SYS_NAND_BLOCK_SIZE)
+#else
+#define CONFIG_SYS_QE_FMAN_FW_IN_NOR
+#define CONFIG_SYS_QE_FMAN_FW_ADDR		0xEFF00000
+#endif
+#define CONFIG_SYS_QE_FMAN_FW_LENGTH	0x10000
+#define CONFIG_SYS_FDT_PAD		(0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
+#endif /* CONFIG_NOBQFMAN */
+
+#ifdef CONFIG_SYS_DPAA_FMAN
+#define CONFIG_FMAN_ENET
+#define CONFIG_PHY_VITESSE
+#define CONFIG_PHY_REALTEK
+#endif
+
+#ifdef CONFIG_FMAN_ENET
+#define CONFIG_SYS_RGMII1_PHY_ADDR		0x01
+#define CONFIG_SYS_RGMII2_PHY_ADDR		0x02
+
+#define CONFIG_MII		/* MII PHY management */
+#define CONFIG_ETHPRIME		"FM1@DTSEC4"
+#define CONFIG_PHY_GIGE		/* Include GbE speed/duplex detection */
+#endif
+
+/*
+ * Environment
+ */
+#define CONFIG_LOADS_ECHO		/* echo on for serial download */
+#define CONFIG_SYS_LOADS_BAUD_CHANGE	/* allow baudrate change */
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_ERRATA
+#define CONFIG_CMD_GREPENV
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_REGINFO
+#define CONFIG_CMD_SETEXPR
+
+#ifdef CONFIG_PCI
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_NET
+#endif
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP			/* undef to save memory	*/
+#define CONFIG_CMDLINE_EDITING			/* Command-line editing */
+#define CONFIG_AUTO_COMPLETE			/* add autocompletion support */
+#define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
+#define CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt */
+#ifdef CONFIG_CMD_KGDB
+#define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size */
+#else
+#define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size */
+#endif
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
+#define CONFIG_SYS_MAXARGS	16		/* max number of command args */
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 64 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ	(64 << 20)	/* Initial map for Linux*/
+#define CONFIG_SYS_BOOTM_LEN	(64 << 20)	/* Increase max gunzip size */
+
+#ifdef CONFIG_CMD_KGDB
+#define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
+#endif
+
+/*
+ * Environment Configuration
+ */
+#define CONFIG_ROOTPATH		"/opt/nfsroot"
+#define CONFIG_BOOTFILE		"uImage"
+#define CONFIG_UBOOTPATH	"u-boot.bin"	/* U-Boot image on TFTP server*/
+
+/* default location for tftp and bootm */
+#define CONFIG_LOADADDR		1000000
+
+#define CONFIG_BOOTDELAY	10	/*-1 disables auto-boot*/
+
+#define CONFIG_BAUDRATE	115200
+
+#define __USB_PHY_TYPE	utmi
+
+#define	CONFIG_EXTRA_ENV_SETTINGS				\
+	"hwconfig=fsl_ddr:bank_intlv=cs0_cs1;"			\
+	"usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) ";"\
+	"usb2:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
+	"netdev=eth0\0"						\
+	"uboot=" __stringify(CONFIG_UBOOTPATH) "\0"		\
+	"ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"	\
+	"tftpflash=tftpboot $loadaddr $uboot && "		\
+	"protect off $ubootaddr +$filesize && "			\
+	"erase $ubootaddr +$filesize && "			\
+	"cp.b $loadaddr $ubootaddr $filesize && "		\
+	"protect on $ubootaddr +$filesize && "			\
+	"cmp.b $loadaddr $ubootaddr $filesize\0"		\
+	"consoledev=ttyS0\0"					\
+	"ramdiskaddr=2000000\0"					\
+	"ramdiskfile=t1040rdb_pi/ramdisk.uboot\0"			\
+	"fdtaddr=c00000\0"					\
+	"fdtfile=t1040rdb_pi/t1040rdb_pi.dtb\0"				\
+	"bdev=sda3\0"						\
+	"c=ffe\0"
+
+#define CONFIG_LINUX                       \
+	"setenv bootargs root=/dev/ram rw "            \
+	"console=$consoledev,$baudrate $othbootargs;"  \
+	"setenv ramdiskaddr 0x02000000;"               \
+	"setenv fdtaddr 0x00c00000;"		       \
+	"setenv loadaddr 0x1000000;"		       \
+	"bootm $loadaddr $ramdiskaddr $fdtaddr"
+
+#define CONFIG_HDBOOT					\
+	"setenv bootargs root=/dev/$bdev rw "		\
+	"console=$consoledev,$baudrate $othbootargs;"	\
+	"tftp $loadaddr $bootfile;"			\
+	"tftp $fdtaddr $fdtfile;"			\
+	"bootm $loadaddr - $fdtaddr"
+
+#define CONFIG_NFSBOOTCOMMAND			\
+	"setenv bootargs root=/dev/nfs rw "	\
+	"nfsroot=$serverip:$rootpath "		\
+	"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
+	"console=$consoledev,$baudrate $othbootargs;"	\
+	"tftp $loadaddr $bootfile;"		\
+	"tftp $fdtaddr $fdtfile;"		\
+	"bootm $loadaddr - $fdtaddr"
+
+#define CONFIG_RAMBOOTCOMMAND				\
+	"setenv bootargs root=/dev/ram rw "		\
+	"console=$consoledev,$baudrate $othbootargs;"	\
+	"tftp $ramdiskaddr $ramdiskfile;"		\
+	"tftp $loadaddr $bootfile;"			\
+	"tftp $fdtaddr $fdtfile;"			\
+	"bootm $loadaddr $ramdiskaddr $fdtaddr"
+
+#define CONFIG_BOOTCOMMAND		CONFIG_LINUX
+
+#ifdef CONFIG_SECURE_BOOT
+#include <asm/fsl_secure_boot.h>
+#endif
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/T208xQDS.h b/include/configs/T208xQDS.h
new file mode 100644
index 0000000000..399ddbb791
--- /dev/null
+++ b/include/configs/T208xQDS.h
@@ -0,0 +1,816 @@
+/*
+ * Copyright 2011-2013 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+/*
+ * T2080/T2081 QDS board configuration file
+ */
+
+#ifndef __T208xQDS_H
+#define __T208xQDS_H
+
+#define CONFIG_ICS307_REFCLK_HZ 25000000  /* ICS307 ref clk freq */
+#define CONFIG_MMC
+#define CONFIG_SPI_FLASH
+#define CONFIG_USB_EHCI
+#if defined(CONFIG_PPC_T2080)
+#define CONFIG_T2080QDS
+#define CONFIG_FSL_SATA_V2
+#define CONFIG_SYS_SRIO		/* Enable Serial RapidIO Support */
+#define CONFIG_SRIO1		/* SRIO port 1 */
+#define CONFIG_SRIO2		/* SRIO port 2 */
+#elif defined(CONFIG_PPC_T2081)
+#define CONFIG_T2081QDS
+#endif
+
+/* High Level Configuration Options */
+#define CONFIG_PHYS_64BIT
+#define CONFIG_BOOKE
+#define CONFIG_E500		/* BOOKE e500 family */
+#define CONFIG_E500MC		/* BOOKE e500mc family */
+#define CONFIG_SYS_BOOK3E_HV	/* Category E.HV supported */
+#define CONFIG_MP		/* support multiple processors */
+#define CONFIG_ENABLE_36BIT_PHYS
+
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_ADDR_MAP 1
+#define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */
+#endif
+
+#define CONFIG_SYS_FSL_CPC	/* Corenet Platform Cache */
+#define CONFIG_SYS_NUM_CPC	CONFIG_NUM_DDR_CONTROLLERS
+#define CONFIG_FSL_IFC		/* Enable IFC Support */
+#define CONFIG_FSL_LAW		/* Use common FSL init code */
+#define CONFIG_ENV_OVERWRITE
+
+#ifdef CONFIG_RAMBOOT_PBL
+#define CONFIG_RAMBOOT_TEXT_BASE	CONFIG_SYS_TEXT_BASE
+#define CONFIG_RESET_VECTOR_ADDRESS	0xfffffffc
+#define CONFIG_SYS_FSL_PBL_PBI board/freescale/t208xqds/t208x_pbi.cfg
+#if defined(CONFIG_PPC_T2080)
+#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2080_rcw.cfg
+#elif defined(CONFIG_PPC_T2081)
+#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2081_rcw.cfg
+#endif
+#endif
+
+#define CONFIG_SRIO_PCIE_BOOT_MASTER
+#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
+/* Set 1M boot space */
+#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
+#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
+		(0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
+#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
+#define CONFIG_SYS_NO_FLASH
+#endif
+
+#ifndef CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_TEXT_BASE	0xeff40000
+#endif
+
+#ifndef CONFIG_RESET_VECTOR_ADDRESS
+#define CONFIG_RESET_VECTOR_ADDRESS	0xeffffffc
+#endif
+
+/*
+ * These can be toggled for performance analysis, otherwise use default.
+ */
+#define CONFIG_SYS_CACHE_STASHING
+#define CONFIG_BTB		/* toggle branch predition */
+#define CONFIG_DDR_ECC
+#ifdef CONFIG_DDR_ECC
+#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
+#define CONFIG_MEM_INIT_VALUE		0xdeadbeef
+#endif
+
+#ifdef CONFIG_SYS_NO_FLASH
+#if !defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) && !defined(CONFIG_RAMBOOT_PBL)
+#define CONFIG_ENV_IS_NOWHERE
+#endif
+#else
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
+#endif
+
+#if defined(CONFIG_SPIFLASH)
+#define CONFIG_SYS_EXTRA_ENV_RELOC
+#define CONFIG_ENV_IS_IN_SPI_FLASH
+#define CONFIG_ENV_SPI_BUS	0
+#define CONFIG_ENV_SPI_CS	0
+#define CONFIG_ENV_SPI_MAX_HZ	10000000
+#define CONFIG_ENV_SPI_MODE	0
+#define CONFIG_ENV_SIZE		0x2000	   /* 8KB */
+#define CONFIG_ENV_OFFSET	0x100000   /* 1MB */
+#define CONFIG_ENV_SECT_SIZE	0x10000
+#elif defined(CONFIG_SDCARD)
+#define CONFIG_SYS_EXTRA_ENV_RELOC
+#define CONFIG_ENV_IS_IN_MMC
+#define CONFIG_SYS_MMC_ENV_DEV	0
+#define CONFIG_ENV_SIZE		0x2000
+#define CONFIG_ENV_OFFSET	(512 * 1658)
+#elif defined(CONFIG_NAND)
+#define CONFIG_SYS_EXTRA_ENV_RELOC
+#define CONFIG_ENV_IS_IN_NAND
+#define CONFIG_ENV_SIZE		CONFIG_SYS_NAND_BLOCK_SIZE
+#define CONFIG_ENV_OFFSET	(7 * CONFIG_SYS_NAND_BLOCK_SIZE)
+#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
+#define CONFIG_ENV_IS_IN_REMOTE
+#define CONFIG_ENV_ADDR		0xffe20000
+#define CONFIG_ENV_SIZE		0x2000
+#elif defined(CONFIG_ENV_IS_NOWHERE)
+#define CONFIG_ENV_SIZE		0x2000
+#else
+#define CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE		0x2000
+#define CONFIG_ENV_SECT_SIZE	0x20000 /* 128K (one sector) */
+#endif
+
+#ifndef __ASSEMBLY__
+unsigned long get_board_sys_clk(void);
+unsigned long get_board_ddr_clk(void);
+#endif
+
+#define CONFIG_SYS_CLK_FREQ	get_board_sys_clk()
+#define CONFIG_DDR_CLK_FREQ	get_board_ddr_clk()
+
+/*
+ * Config the L3 Cache as L3 SRAM
+ */
+#define CONFIG_SYS_INIT_L3_ADDR	 CONFIG_RAMBOOT_TEXT_BASE
+
+#define CONFIG_SYS_DCSRBAR	0xf0000000
+#define CONFIG_SYS_DCSRBAR_PHYS	0xf00000000ull
+
+/* EEPROM */
+#define CONFIG_ID_EEPROM
+#define CONFIG_SYS_I2C_EEPROM_NXID
+#define CONFIG_SYS_EEPROM_BUS_NUM	0
+#define CONFIG_SYS_I2C_EEPROM_ADDR	0x57
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	1
+
+/*
+ * DDR Setup
+ */
+#define CONFIG_VERY_BIG_RAM
+#define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000
+#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
+#define CONFIG_DIMM_SLOTS_PER_CTLR	1
+#define CONFIG_CHIP_SELECTS_PER_CTRL	(4 * CONFIG_DIMM_SLOTS_PER_CTLR)
+#define CONFIG_DDR_SPD
+#define CONFIG_SYS_FSL_DDR3
+#undef CONFIG_FSL_DDR_INTERACTIVE
+#define CONFIG_SYS_SPD_BUS_NUM	0
+#define CONFIG_SYS_SDRAM_SIZE	2048	/* for fixed parameter use */
+#define SPD_EEPROM_ADDRESS1	0x51
+#define SPD_EEPROM_ADDRESS2	0x52
+#define SPD_EEPROM_ADDRESS	SPD_EEPROM_ADDRESS1
+#define CTRL_INTLV_PREFERED	cacheline
+
+/*
+ * IFC Definitions
+ */
+#define CONFIG_SYS_FLASH_BASE		0xe0000000
+#define CONFIG_SYS_FLASH_BASE_PHYS	(0xf00000000ull | CONFIG_SYS_FLASH_BASE)
+#define CONFIG_SYS_NOR0_CSPR_EXT	(0xf)
+#define CONFIG_SYS_NOR0_CSPR	(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
+				+ 0x8000000) | \
+				CSPR_PORT_SIZE_16 | \
+				CSPR_MSEL_NOR | \
+				CSPR_V)
+#define CONFIG_SYS_NOR1_CSPR_EXT	(0xf)
+#define CONFIG_SYS_NOR1_CSPR	(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
+				CSPR_PORT_SIZE_16 | \
+				CSPR_MSEL_NOR | \
+				CSPR_V)
+#define CONFIG_SYS_NOR_AMASK	IFC_AMASK(128*1024*1024)
+/* NOR Flash Timing Params */
+#define CONFIG_SYS_NOR_CSOR	CSOR_NAND_TRHZ_80
+
+#define CONFIG_SYS_NOR_FTIM0	(FTIM0_NOR_TACSE(0x4) | \
+				FTIM0_NOR_TEADC(0x5) | \
+				FTIM0_NOR_TEAHC(0x5))
+#define CONFIG_SYS_NOR_FTIM1	(FTIM1_NOR_TACO(0x35) | \
+				FTIM1_NOR_TRAD_NOR(0x1A) |\
+				FTIM1_NOR_TSEQRAD_NOR(0x13))
+#define CONFIG_SYS_NOR_FTIM2	(FTIM2_NOR_TCS(0x4) | \
+				FTIM2_NOR_TCH(0x4) | \
+				FTIM2_NOR_TWPH(0x0E) | \
+				FTIM2_NOR_TWP(0x1c))
+#define CONFIG_SYS_NOR_FTIM3	0x0
+
+#define CONFIG_SYS_FLASH_QUIET_TEST
+#define CONFIG_FLASH_SHOW_PROGRESS	45 /* count down from 45/5: 9..1 */
+
+#define CONFIG_SYS_MAX_FLASH_BANKS	2	/* number of banks */
+#define CONFIG_SYS_MAX_FLASH_SECT	1024	/* sectors per device */
+#define CONFIG_SYS_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */
+
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+#define CONFIG_SYS_FLASH_BANKS_LIST	{CONFIG_SYS_FLASH_BASE_PHYS \
+					+ 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
+
+#define CONFIG_FSL_QIXIS	/* use common QIXIS code */
+#define QIXIS_BASE			0xffdf0000
+#define QIXIS_LBMAP_SWITCH		6
+#define QIXIS_LBMAP_MASK		0x0f
+#define QIXIS_LBMAP_SHIFT		0
+#define QIXIS_LBMAP_DFLTBANK		0x00
+#define QIXIS_LBMAP_ALTBANK		0x04
+#define QIXIS_RST_CTL_RESET		0x83
+#define QIXIS_RST_FORCE_MEM		0x1
+#define QIXIS_RCFG_CTL_RECONFIG_IDLE	0x20
+#define QIXIS_RCFG_CTL_RECONFIG_START	0x21
+#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE	0x08
+#define QIXIS_BASE_PHYS		(0xf00000000ull | QIXIS_BASE)
+
+#define CONFIG_SYS_CSPR3_EXT	(0xf)
+#define CONFIG_SYS_CSPR3	(CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
+				| CSPR_PORT_SIZE_8 \
+				| CSPR_MSEL_GPCM \
+				| CSPR_V)
+#define CONFIG_SYS_AMASK3	IFC_AMASK(4*1024)
+#define CONFIG_SYS_CSOR3	0x0
+/* QIXIS Timing parameters for IFC CS3 */
+#define CONFIG_SYS_CS3_FTIM0		(FTIM0_GPCM_TACSE(0x0e) | \
+					FTIM0_GPCM_TEADC(0x0e) | \
+					FTIM0_GPCM_TEAHC(0x0e))
+#define CONFIG_SYS_CS3_FTIM1		(FTIM1_GPCM_TACO(0xff) | \
+					FTIM1_GPCM_TRAD(0x3f))
+#define CONFIG_SYS_CS3_FTIM2		(FTIM2_GPCM_TCS(0x0e) | \
+					FTIM2_GPCM_TCH(0x8) | \
+					FTIM2_GPCM_TWP(0x1f))
+#define CONFIG_SYS_CS3_FTIM3		0x0
+
+/* NAND Flash on IFC */
+#define CONFIG_NAND_FSL_IFC
+#define CONFIG_SYS_NAND_BASE		0xff800000
+#define CONFIG_SYS_NAND_BASE_PHYS	(0xf00000000ull | CONFIG_SYS_NAND_BASE)
+
+#define CONFIG_SYS_NAND_CSPR_EXT	(0xf)
+#define CONFIG_SYS_NAND_CSPR	(CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
+				| CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
+				| CSPR_MSEL_NAND	 /* MSEL = NAND */ \
+				| CSPR_V)
+#define CONFIG_SYS_NAND_AMASK	IFC_AMASK(64*1024)
+
+#define CONFIG_SYS_NAND_CSOR	(CSOR_NAND_ECC_ENC_EN	/* ECC on encode */ \
+				| CSOR_NAND_ECC_DEC_EN	/* ECC on decode */ \
+				| CSOR_NAND_ECC_MODE_4	/* 4-bit ECC */	    \
+				| CSOR_NAND_RAL_3	/* RAL = 2Byes */   \
+				| CSOR_NAND_PGS_2K	/* Page Size = 2K */\
+				| CSOR_NAND_SPRZ_64	/* Spare size = 64 */\
+				| CSOR_NAND_PB(64))	/*Pages Per Block = 64*/
+
+#define CONFIG_SYS_NAND_ONFI_DETECTION
+
+/* ONFI NAND Flash mode0 Timing Params */
+#define CONFIG_SYS_NAND_FTIM0		(FTIM0_NAND_TCCST(0x07) | \
+					FTIM0_NAND_TWP(0x18)    | \
+					FTIM0_NAND_TWCHT(0x07)  | \
+					FTIM0_NAND_TWH(0x0a))
+#define CONFIG_SYS_NAND_FTIM1		(FTIM1_NAND_TADLE(0x32) | \
+					FTIM1_NAND_TWBE(0x39)   | \
+					FTIM1_NAND_TRR(0x0e)    | \
+					FTIM1_NAND_TRP(0x18))
+#define CONFIG_SYS_NAND_FTIM2		(FTIM2_NAND_TRAD(0x0f)  | \
+					FTIM2_NAND_TREH(0x0a)   | \
+					FTIM2_NAND_TWHRE(0x1e))
+#define CONFIG_SYS_NAND_FTIM3		0x0
+
+#define CONFIG_SYS_NAND_DDR_LAW		11
+#define CONFIG_SYS_NAND_BASE_LIST	{ CONFIG_SYS_NAND_BASE }
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+#define CONFIG_MTD_NAND_VERIFY_WRITE
+#define CONFIG_CMD_NAND
+#define CONFIG_SYS_NAND_BLOCK_SIZE	(128 * 1024)
+
+#if defined(CONFIG_NAND)
+#define CONFIG_SYS_CSPR0_EXT		CONFIG_SYS_NAND_CSPR_EXT
+#define CONFIG_SYS_CSPR0		CONFIG_SYS_NAND_CSPR
+#define CONFIG_SYS_AMASK0		CONFIG_SYS_NAND_AMASK
+#define CONFIG_SYS_CSOR0		CONFIG_SYS_NAND_CSOR
+#define CONFIG_SYS_CS0_FTIM0		CONFIG_SYS_NAND_FTIM0
+#define CONFIG_SYS_CS0_FTIM1		CONFIG_SYS_NAND_FTIM1
+#define CONFIG_SYS_CS0_FTIM2		CONFIG_SYS_NAND_FTIM2
+#define CONFIG_SYS_CS0_FTIM3		CONFIG_SYS_NAND_FTIM3
+#define CONFIG_SYS_CSPR2_EXT		CONFIG_SYS_NOR0_CSPR_EXT
+#define CONFIG_SYS_CSPR2		CONFIG_SYS_NOR0_CSPR
+#define CONFIG_SYS_AMASK2		CONFIG_SYS_NOR_AMASK
+#define CONFIG_SYS_CSOR2		CONFIG_SYS_NOR_CSOR
+#define CONFIG_SYS_CS2_FTIM0		CONFIG_SYS_NOR_FTIM0
+#define CONFIG_SYS_CS2_FTIM1		CONFIG_SYS_NOR_FTIM1
+#define CONFIG_SYS_CS2_FTIM2		CONFIG_SYS_NOR_FTIM2
+#define CONFIG_SYS_CS2_FTIM3		CONFIG_SYS_NOR_FTIM3
+#else
+#define CONFIG_SYS_CSPR0_EXT		CONFIG_SYS_NOR0_CSPR_EXT
+#define CONFIG_SYS_CSPR0		CONFIG_SYS_NOR0_CSPR
+#define CONFIG_SYS_AMASK0		CONFIG_SYS_NOR_AMASK
+#define CONFIG_SYS_CSOR0		CONFIG_SYS_NOR_CSOR
+#define CONFIG_SYS_CS0_FTIM0		CONFIG_SYS_NOR_FTIM0
+#define CONFIG_SYS_CS0_FTIM1		CONFIG_SYS_NOR_FTIM1
+#define CONFIG_SYS_CS0_FTIM2		CONFIG_SYS_NOR_FTIM2
+#define CONFIG_SYS_CS0_FTIM3		CONFIG_SYS_NOR_FTIM3
+#define CONFIG_SYS_CSPR2_EXT		CONFIG_SYS_NAND_CSPR_EXT
+#define CONFIG_SYS_CSPR2		CONFIG_SYS_NAND_CSPR
+#define CONFIG_SYS_AMASK2		CONFIG_SYS_NAND_AMASK
+#define CONFIG_SYS_CSOR2		CONFIG_SYS_NAND_CSOR
+#define CONFIG_SYS_CS2_FTIM0		CONFIG_SYS_NAND_FTIM0
+#define CONFIG_SYS_CS2_FTIM1		CONFIG_SYS_NAND_FTIM1
+#define CONFIG_SYS_CS2_FTIM2		CONFIG_SYS_NAND_FTIM2
+#define CONFIG_SYS_CS2_FTIM3		CONFIG_SYS_NAND_FTIM3
+#endif
+#define CONFIG_SYS_CSPR1_EXT		CONFIG_SYS_NOR1_CSPR_EXT
+#define CONFIG_SYS_CSPR1		CONFIG_SYS_NOR1_CSPR
+#define CONFIG_SYS_AMASK1		CONFIG_SYS_NOR_AMASK
+#define CONFIG_SYS_CSOR1		CONFIG_SYS_NOR_CSOR
+#define CONFIG_SYS_CS1_FTIM0		CONFIG_SYS_NOR_FTIM0
+#define CONFIG_SYS_CS1_FTIM1		CONFIG_SYS_NOR_FTIM1
+#define CONFIG_SYS_CS1_FTIM2		CONFIG_SYS_NOR_FTIM2
+#define CONFIG_SYS_CS1_FTIM3		CONFIG_SYS_NOR_FTIM3
+
+#if defined(CONFIG_RAMBOOT_PBL)
+#define CONFIG_SYS_RAMBOOT
+#endif
+
+#define CONFIG_SYS_MONITOR_BASE	 CONFIG_SYS_TEXT_BASE
+#define CONFIG_BOARD_EARLY_INIT_R	/* call board_early_init_r function */
+#define CONFIG_MISC_INIT_R
+#define CONFIG_HWCONFIG
+
+/* define to use L1 as initial stack */
+#define CONFIG_L1_INIT_RAM
+#define CONFIG_SYS_INIT_RAM_LOCK
+#define CONFIG_SYS_INIT_RAM_ADDR	0xfdd00000 /* Initial L1 address */
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH	0xf
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW	0xfe0ec000
+/* The assembler doesn't like typecast */
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
+			((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
+			CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
+#define CONFIG_SYS_INIT_RAM_SIZE	0x00004000
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - \
+						GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+#define CONFIG_SYS_MONITOR_LEN		(512 * 1024)
+#define CONFIG_SYS_MALLOC_LEN		(4 * 1024 * 1024)
+
+/*
+ * Serial Port
+ */
+#define CONFIG_CONS_INDEX		1
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	1
+#define CONFIG_SYS_NS16550_CLK		(get_bus_freq(0)/2)
+#define CONFIG_SYS_BAUDRATE_TABLE	\
+	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
+#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
+#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
+#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
+#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
+
+/* Use the HUSH parser */
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
+
+/* pass open firmware flat tree */
+#define CONFIG_OF_LIBFDT
+#define CONFIG_OF_BOARD_SETUP
+#define CONFIG_OF_STDOUT_VIA_ALIAS
+
+/* new uImage format support */
+#define CONFIG_FIT
+#define CONFIG_FIT_VERBOSE	/* enable fit_format_{error,warning}() */
+
+/*
+ * I2C
+ */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_FSL
+#define CONFIG_SYS_FSL_I2C_SLAVE   0x7F
+#define CONFIG_SYS_FSL_I2C2_SLAVE  0x7F
+#define CONFIG_SYS_FSL_I2C3_SLAVE  0x7F
+#define CONFIG_SYS_FSL_I2C4_SLAVE  0x7F
+#define CONFIG_SYS_FSL_I2C_OFFSET  0x118000
+#define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100
+#define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000
+#define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100
+#define CONFIG_SYS_FSL_I2C_SPEED   100000
+#define CONFIG_SYS_FSL_I2C2_SPEED  100000
+#define CONFIG_SYS_FSL_I2C3_SPEED  100000
+#define CONFIG_SYS_FSL_I2C4_SPEED  100000
+#define I2C_MUX_PCA_ADDR_PRI	0x77 /* I2C bus multiplexer,primary */
+#define I2C_MUX_PCA_ADDR_SEC1	0x75 /* I2C bus multiplexer,secondary 1 */
+#define I2C_MUX_PCA_ADDR_SEC2	0x76 /* I2C bus multiplexer,secondary 2 */
+#define I2C_MUX_CH_DEFAULT	0x8
+
+
+/*
+ * RapidIO
+ */
+#define CONFIG_SYS_SRIO1_MEM_VIRT	0xa0000000
+#define CONFIG_SYS_SRIO1_MEM_PHYS	0xc20000000ull
+#define CONFIG_SYS_SRIO1_MEM_SIZE	0x10000000 /* 256M */
+#define CONFIG_SYS_SRIO2_MEM_VIRT	0xb0000000
+#define CONFIG_SYS_SRIO2_MEM_PHYS	0xc30000000ull
+#define CONFIG_SYS_SRIO2_MEM_SIZE	0x10000000 /* 256M */
+/*
+ * for slave u-boot IMAGE instored in master memory space,
+ * PHYS must be aligned based on the SIZE
+ */
+#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef080000ull
+#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff80000ull
+#define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE     0x80000 /* 512K */
+#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff80000ull
+/*
+ * for slave UCODE and ENV instored in master memory space,
+ * PHYS must be aligned based on the SIZE
+ */
+#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef040000ull
+#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
+#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE    0x40000	/* 256K */
+
+/* slave core release by master*/
+#define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
+#define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
+
+/*
+ * SRIO_PCIE_BOOT - SLAVE
+ */
+#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
+#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
+#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
+		(0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
+#endif
+
+/*
+ * eSPI - Enhanced SPI
+ */
+#ifdef CONFIG_SPI_FLASH
+#define CONFIG_FSL_ESPI
+#define CONFIG_SPI_FLASH_SST
+#define CONFIG_SPI_FLASH_STMICRO
+#if defined(CONFIG_T2080QDS)
+#define CONFIG_SPI_FLASH_SPANSION
+#elif defined(CONFIG_T2081QDS)
+#define CONFIG_SPI_FLASH_EON
+#endif
+
+#define CONFIG_CMD_SF
+#define CONFIG_SF_DEFAULT_SPEED	 10000000
+#define CONFIG_SF_DEFAULT_MODE	  0
+#endif
+
+/*
+ * General PCI
+ * Memory space is mapped 1-1, but I/O space must start from 0.
+ */
+#define CONFIG_PCI		/* Enable PCI/PCIE */
+#define CONFIG_PCIE1		/* PCIE controler 1 */
+#define CONFIG_PCIE2		/* PCIE controler 2 */
+#define CONFIG_PCIE3		/* PCIE controler 3 */
+#define CONFIG_PCIE4		/* PCIE controler 4 */
+#define CONFIG_FSL_PCI_INIT	/* Use common FSL init code */
+#define CONFIG_SYS_PCI_64BIT	/* enable 64-bit PCI resources */
+/* controller 1, direct to uli, tgtid 3, Base address 20000 */
+#define CONFIG_SYS_PCIE1_MEM_VIRT	0x80000000
+#define CONFIG_SYS_PCIE1_MEM_BUS	0xe0000000
+#define CONFIG_SYS_PCIE1_MEM_PHYS	0xc00000000ull
+#define CONFIG_SYS_PCIE1_MEM_SIZE	0x20000000      /* 512M */
+#define CONFIG_SYS_PCIE1_IO_VIRT	0xf8000000
+#define CONFIG_SYS_PCIE1_IO_BUS		0x00000000
+#define CONFIG_SYS_PCIE1_IO_PHYS	0xff8000000ull
+#define CONFIG_SYS_PCIE1_IO_SIZE	0x00010000	/* 64k */
+
+/* controller 2, Slot 2, tgtid 2, Base address 201000 */
+#define CONFIG_SYS_PCIE2_MEM_VIRT	0xa0000000
+#define CONFIG_SYS_PCIE2_MEM_BUS	0xe0000000
+#define CONFIG_SYS_PCIE2_MEM_PHYS	0xc20000000ull
+#define CONFIG_SYS_PCIE2_MEM_SIZE	0x10000000 /* 256M */
+#define CONFIG_SYS_PCIE2_IO_VIRT	0xf8010000
+#define CONFIG_SYS_PCIE2_IO_BUS		0x00000000
+#define CONFIG_SYS_PCIE2_IO_PHYS	0xff8010000ull
+#define CONFIG_SYS_PCIE2_IO_SIZE	0x00010000	/* 64k */
+
+/* controller 3, Slot 1, tgtid 1, Base address 202000 */
+#define CONFIG_SYS_PCIE3_MEM_VIRT	0xb0000000
+#define CONFIG_SYS_PCIE3_MEM_BUS	0xe0000000
+#define CONFIG_SYS_PCIE3_MEM_PHYS	0xc30000000ull
+#define CONFIG_SYS_PCIE3_MEM_SIZE	0x10000000	/* 256M */
+#define CONFIG_SYS_PCIE3_IO_VIRT	0xf8020000
+#define CONFIG_SYS_PCIE3_IO_BUS		0x00000000
+#define CONFIG_SYS_PCIE3_IO_PHYS	0xff8020000ull
+#define CONFIG_SYS_PCIE3_IO_SIZE	0x00010000	/* 64k */
+
+/* controller 4, Base address 203000 */
+#define CONFIG_SYS_PCIE4_MEM_VIRT       0xc0000000
+#define CONFIG_SYS_PCIE4_MEM_BUS	0xe0000000
+#define CONFIG_SYS_PCIE4_MEM_PHYS	0xc40000000ull
+#define CONFIG_SYS_PCIE4_MEM_SIZE	0x10000000	/* 256M */
+#define CONFIG_SYS_PCIE4_IO_BUS		0x00000000
+#define CONFIG_SYS_PCIE4_IO_PHYS	0xff8030000ull
+#define CONFIG_SYS_PCIE4_IO_SIZE	0x00010000	/* 64k */
+
+#ifdef CONFIG_PCI
+#define CONFIG_PCI_INDIRECT_BRIDGE
+#define CONFIG_FSL_PCIE_RESET	   /* need PCIe reset errata */
+#define CONFIG_NET_MULTI
+#define CONFIG_E1000
+#define CONFIG_PCI_PNP		/* do pci plug-and-play */
+#define CONFIG_PCI_SCAN_SHOW	/* show pci devices on startup */
+#define CONFIG_DOS_PARTITION
+#endif
+
+/* Qman/Bman */
+#ifndef CONFIG_NOBQFMAN
+#define CONFIG_SYS_DPAA_QBMAN		/* Support Q/Bman */
+#define CONFIG_SYS_BMAN_NUM_PORTALS	18
+#define CONFIG_SYS_BMAN_MEM_BASE	0xf4000000
+#define CONFIG_SYS_BMAN_MEM_PHYS	0xff4000000ull
+#define CONFIG_SYS_BMAN_MEM_SIZE	0x02000000
+#define CONFIG_SYS_QMAN_NUM_PORTALS	18
+#define CONFIG_SYS_QMAN_MEM_BASE	0xf6000000
+#define CONFIG_SYS_QMAN_MEM_PHYS	0xff6000000ull
+#define CONFIG_SYS_QMAN_MEM_SIZE	0x02000000
+
+#define CONFIG_SYS_DPAA_FMAN
+#define CONFIG_SYS_DPAA_PME
+#define CONFIG_SYS_PMAN
+#define CONFIG_SYS_DPAA_DCE
+#define CONFIG_SYS_DPAA_RMAN		/* RMan */
+#define CONFIG_SYS_INTERLAKEN
+
+/* Default address of microcode for the Linux Fman driver */
+#if defined(CONFIG_SPIFLASH)
+/*
+ * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
+ * env, so we got 0x110000.
+ */
+#define CONFIG_SYS_QE_FW_IN_SPIFLASH
+#define CONFIG_SYS_QE_FMAN_FW_ADDR	0x110000
+#elif defined(CONFIG_SDCARD)
+/*
+ * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
+ * about 825KB (1650 blocks), Env is stored after the image, and the env size is
+ * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680.
+ */
+#define CONFIG_SYS_QE_FMAN_FW_IN_MMC
+#define CONFIG_SYS_QE_FMAN_FW_ADDR	(512 * 1680)
+#elif defined(CONFIG_NAND)
+#define CONFIG_SYS_QE_FMAN_FW_IN_NAND
+#define CONFIG_SYS_QE_FMAN_FW_ADDR	(8 * CONFIG_SYS_NAND_BLOCK_SIZE)
+#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
+/*
+ * Slave has no ucode locally, it can fetch this from remote. When implementing
+ * in two corenet boards, slave's ucode could be stored in master's memory
+ * space, the address can be mapped from slave TLB->slave LAW->
+ * slave SRIO or PCIE outbound window->master inbound window->
+ * master LAW->the ucode address in master's memory space.
+ */
+#define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE
+#define CONFIG_SYS_QE_FMAN_FW_ADDR	0xFFE00000
+#else
+#define CONFIG_SYS_QE_FMAN_FW_IN_NOR
+#define CONFIG_SYS_QE_FMAN_FW_ADDR	0xEFF00000
+#endif
+#define CONFIG_SYS_QE_FMAN_FW_LENGTH	0x10000
+#define CONFIG_SYS_FDT_PAD		(0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
+#endif /* CONFIG_NOBQFMAN */
+
+#ifdef CONFIG_SYS_DPAA_FMAN
+#define CONFIG_FMAN_ENET
+#define CONFIG_PHYLIB_10G
+#define CONFIG_PHY_VITESSE
+#define CONFIG_PHY_REALTEK
+#define CONFIG_PHY_TERANETICS
+#define RGMII_PHY1_ADDR	0x1
+#define RGMII_PHY2_ADDR	0x2
+#define FM1_10GEC1_PHY_ADDR	  0x3
+#define SGMII_CARD_PORT1_PHY_ADDR 0x1C
+#define SGMII_CARD_PORT2_PHY_ADDR 0x1D
+#define SGMII_CARD_PORT3_PHY_ADDR 0x1E
+#define SGMII_CARD_PORT4_PHY_ADDR 0x1F
+#endif
+
+#ifdef CONFIG_FMAN_ENET
+#define CONFIG_MII		/* MII PHY management */
+#define CONFIG_ETHPRIME		"FM1@DTSEC3"
+#define CONFIG_PHY_GIGE		/* Include GbE speed/duplex detection */
+#endif
+
+/*
+ * SATA
+ */
+#ifdef CONFIG_FSL_SATA_V2
+#define CONFIG_LIBATA
+#define CONFIG_FSL_SATA
+#define CONFIG_SYS_SATA_MAX_DEVICE	2
+#define CONFIG_SATA1
+#define CONFIG_SYS_SATA1		CONFIG_SYS_MPC85xx_SATA1_ADDR
+#define CONFIG_SYS_SATA1_FLAGS		FLAGS_DMA
+#define CONFIG_SATA2
+#define CONFIG_SYS_SATA2		CONFIG_SYS_MPC85xx_SATA2_ADDR
+#define CONFIG_SYS_SATA2_FLAGS		FLAGS_DMA
+#define CONFIG_LBA48
+#define CONFIG_CMD_SATA
+#define CONFIG_DOS_PARTITION
+#define CONFIG_CMD_EXT2
+#endif
+
+/*
+ * USB
+ */
+#ifdef CONFIG_USB_EHCI
+#define CONFIG_CMD_USB
+#define CONFIG_USB_STORAGE
+#define CONFIG_USB_EHCI_FSL
+#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
+#define CONFIG_CMD_EXT2
+#define CONFIG_HAS_FSL_DR_USB
+#endif
+
+/*
+ * SDHC
+ */
+#ifdef CONFIG_MMC
+#define CONFIG_CMD_MMC
+#define CONFIG_FSL_ESDHC
+#define CONFIG_SYS_FSL_ESDHC_ADDR	CONFIG_SYS_MPC85xx_ESDHC_ADDR
+#define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
+#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
+#define CONFIG_GENERIC_MMC
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_FAT
+#define CONFIG_DOS_PARTITION
+#endif
+
+/*
+ * Environment
+ */
+#define CONFIG_LOADS_ECHO	/* echo on for serial download */
+#define CONFIG_SYS_LOADS_BAUD_CHANGE	/* allow baudrate change */
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_ERRATA
+#define CONFIG_CMD_GREPENV
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_SETEXPR
+#define CONFIG_CMD_REGINFO
+#define CONFIG_CMD_BDI
+
+#ifdef CONFIG_PCI
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_NET
+#endif
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP		/* undef to save memory */
+#define CONFIG_CMDLINE_EDITING		/* Command-line editing */
+#define CONFIG_AUTO_COMPLETE		/* add autocompletion support */
+#define CONFIG_SYS_LOAD_ADDR	0x2000000 /* default load address */
+#define CONFIG_SYS_PROMPT	"=> "	  /* Monitor Command Prompt */
+#ifdef CONFIG_CMD_KGDB
+#define CONFIG_SYS_CBSIZE	1024	  /* Console I/O Buffer Size */
+#else
+#define CONFIG_SYS_CBSIZE	256	  /* Console I/O Buffer Size */
+#endif
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
+#define CONFIG_SYS_MAXARGS	16	/* max number of command args */
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 64 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ	(64 << 20)	/* Initial map for Linux*/
+#define CONFIG_SYS_BOOTM_LEN	(64 << 20)	/* Increase max gunzip size */
+
+#ifdef CONFIG_CMD_KGDB
+#define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
+#define CONFIG_KGDB_SER_INDEX	2	/* which serial port to use */
+#endif
+
+/*
+ * Environment Configuration
+ */
+#define CONFIG_ROOTPATH	 "/opt/nfsroot"
+#define CONFIG_BOOTFILE	 "uImage"
+#define CONFIG_UBOOTPATH "u-boot.bin"	/* U-Boot image on TFTP server */
+
+/* default location for tftp and bootm */
+#define CONFIG_LOADADDR		1000000
+#define CONFIG_BAUDRATE		115200
+#define CONFIG_BOOTDELAY	10	/* -1 disables auto-boot */
+#define __USB_PHY_TYPE		utmi
+
+#define	CONFIG_EXTRA_ENV_SETTINGS				\
+	"hwconfig=fsl_ddr:"					\
+	"ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) ","	\
+	"bank_intlv=auto;"					\
+	"usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
+	"netdev=eth0\0"						\
+	"uboot=" __stringify(CONFIG_UBOOTPATH) "\0"		\
+	"ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"	\
+	"tftpflash=tftpboot $loadaddr $uboot && "		\
+	"protect off $ubootaddr +$filesize && "			\
+	"erase $ubootaddr +$filesize && "			\
+	"cp.b $loadaddr $ubootaddr $filesize && "		\
+	"protect on $ubootaddr +$filesize && "			\
+	"cmp.b $loadaddr $ubootaddr $filesize\0"		\
+	"consoledev=ttyS0\0"					\
+	"ramdiskaddr=2000000\0"					\
+	"ramdiskfile=t2080qds/ramdisk.uboot\0"			\
+	"fdtaddr=c00000\0"					\
+	"fdtfile=t2080qds/t2080qds.dtb\0"			\
+	"bdev=sda3\0"						\
+	"c=ffe\0"
+
+/*
+ * For emulation this causes u-boot to jump to the start of the
+ * proof point app code automatically
+ */
+#define CONFIG_PROOF_POINTS				\
+	"setenv bootargs root=/dev/$bdev rw "		\
+	"console=$consoledev,$baudrate $othbootargs;"	\
+	"cpu 1 release 0x29000000 - - -;"		\
+	"cpu 2 release 0x29000000 - - -;"		\
+	"cpu 3 release 0x29000000 - - -;"		\
+	"cpu 4 release 0x29000000 - - -;"		\
+	"cpu 5 release 0x29000000 - - -;"		\
+	"cpu 6 release 0x29000000 - - -;"		\
+	"cpu 7 release 0x29000000 - - -;"		\
+	"go 0x29000000"
+
+#define CONFIG_HVBOOT				\
+	"setenv bootargs config-addr=0x60000000; "	\
+	"bootm 0x01000000 - 0x00f00000"
+
+#define CONFIG_ALU				\
+	"setenv bootargs root=/dev/$bdev rw "		\
+	"console=$consoledev,$baudrate $othbootargs;"	\
+	"cpu 1 release 0x01000000 - - -;"		\
+	"cpu 2 release 0x01000000 - - -;"		\
+	"cpu 3 release 0x01000000 - - -;"		\
+	"cpu 4 release 0x01000000 - - -;"		\
+	"cpu 5 release 0x01000000 - - -;"		\
+	"cpu 6 release 0x01000000 - - -;"		\
+	"cpu 7 release 0x01000000 - - -;"		\
+	"go 0x01000000"
+
+#define CONFIG_LINUX				\
+	"setenv bootargs root=/dev/ram rw "		\
+	"console=$consoledev,$baudrate $othbootargs;"	\
+	"setenv ramdiskaddr 0x02000000;"		\
+	"setenv fdtaddr 0x00c00000;"			\
+	"setenv loadaddr 0x1000000;"			\
+	"bootm $loadaddr $ramdiskaddr $fdtaddr"
+
+#define CONFIG_HDBOOT					\
+	"setenv bootargs root=/dev/$bdev rw "		\
+	"console=$consoledev,$baudrate $othbootargs;"	\
+	"tftp $loadaddr $bootfile;"			\
+	"tftp $fdtaddr $fdtfile;"			\
+	"bootm $loadaddr - $fdtaddr"
+
+#define CONFIG_NFSBOOTCOMMAND			\
+	"setenv bootargs root=/dev/nfs rw "	\
+	"nfsroot=$serverip:$rootpath "		\
+	"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
+	"console=$consoledev,$baudrate $othbootargs;"	\
+	"tftp $loadaddr $bootfile;"		\
+	"tftp $fdtaddr $fdtfile;"		\
+	"bootm $loadaddr - $fdtaddr"
+
+#define CONFIG_RAMBOOTCOMMAND				\
+	"setenv bootargs root=/dev/ram rw "		\
+	"console=$consoledev,$baudrate $othbootargs;"	\
+	"tftp $ramdiskaddr $ramdiskfile;"		\
+	"tftp $loadaddr $bootfile;"			\
+	"tftp $fdtaddr $fdtfile;"			\
+	"bootm $loadaddr $ramdiskaddr $fdtaddr"
+
+#define CONFIG_BOOTCOMMAND		CONFIG_LINUX
+
+#ifdef CONFIG_SECURE_BOOT
+#include <asm/fsl_secure_boot.h>
+#undef CONFIG_CMD_USB
+#endif
+
+#endif	/* __T208xQDS_H */
diff --git a/include/configs/T208xRDB.h b/include/configs/T208xRDB.h
new file mode 100644
index 0000000000..743eee3161
--- /dev/null
+++ b/include/configs/T208xRDB.h
@@ -0,0 +1,779 @@
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+/*
+ * T2080 RDB/PCIe board configuration file
+ */
+
+#ifndef __T2080RDB_H
+#define __T2080RDB_H
+
+#define CONFIG_T2080RDB
+#define CONFIG_ICS307_REFCLK_HZ 25000000  /* ICS307 ref clk freq */
+#define CONFIG_MMC
+#define CONFIG_SPI_FLASH
+#define CONFIG_USB_EHCI
+#define CONFIG_FSL_SATA_V2
+
+/* High Level Configuration Options */
+#define CONFIG_PHYS_64BIT
+#define CONFIG_BOOKE
+#define CONFIG_E500		/* BOOKE e500 family */
+#define CONFIG_E500MC		/* BOOKE e500mc family */
+#define CONFIG_SYS_BOOK3E_HV	/* Category E.HV supported */
+#define CONFIG_MP		/* support multiple processors */
+#define CONFIG_ENABLE_36BIT_PHYS
+
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_ADDR_MAP 1
+#define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */
+#endif
+
+#define CONFIG_SYS_FSL_CPC	/* Corenet Platform Cache */
+#define CONFIG_SYS_NUM_CPC	CONFIG_NUM_DDR_CONTROLLERS
+#define CONFIG_FSL_IFC		/* Enable IFC Support */
+#define CONFIG_FSL_LAW		/* Use common FSL init code */
+#define CONFIG_ENV_OVERWRITE
+
+#ifdef CONFIG_RAMBOOT_PBL
+#define CONFIG_RAMBOOT_TEXT_BASE	CONFIG_SYS_TEXT_BASE
+#define CONFIG_RESET_VECTOR_ADDRESS	0xfffffffc
+#define CONFIG_SYS_FSL_PBL_PBI board/freescale/t208xrdb/t2080_pbi.cfg
+#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xrdb/t2080_rcw.cfg
+#endif
+
+#define CONFIG_SRIO_PCIE_BOOT_MASTER
+#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
+/* Set 1M boot space */
+#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
+#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
+		(0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
+#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
+#define CONFIG_SYS_NO_FLASH
+#endif
+
+#ifndef CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_TEXT_BASE	0xeff40000
+#endif
+
+#ifndef CONFIG_RESET_VECTOR_ADDRESS
+#define CONFIG_RESET_VECTOR_ADDRESS	0xeffffffc
+#endif
+
+/*
+ * These can be toggled for performance analysis, otherwise use default.
+ */
+#define CONFIG_SYS_CACHE_STASHING
+#define CONFIG_BTB		/* toggle branch predition */
+#define CONFIG_DDR_ECC
+#ifdef CONFIG_DDR_ECC
+#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
+#define CONFIG_MEM_INIT_VALUE		0xdeadbeef
+#endif
+
+#ifdef CONFIG_SYS_NO_FLASH
+#if !defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) && !defined(CONFIG_RAMBOOT_PBL)
+#define CONFIG_ENV_IS_NOWHERE
+#endif
+#else
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
+#endif
+
+#if defined(CONFIG_SPIFLASH)
+#define CONFIG_SYS_EXTRA_ENV_RELOC
+#define CONFIG_ENV_IS_IN_SPI_FLASH
+#define CONFIG_ENV_SPI_BUS	0
+#define CONFIG_ENV_SPI_CS	0
+#define CONFIG_ENV_SPI_MAX_HZ	10000000
+#define CONFIG_ENV_SPI_MODE	0
+#define CONFIG_ENV_SIZE		0x2000	   /* 8KB */
+#define CONFIG_ENV_OFFSET	0x100000   /* 1MB */
+#define CONFIG_ENV_SECT_SIZE	0x10000
+#elif defined(CONFIG_SDCARD)
+#define CONFIG_SYS_EXTRA_ENV_RELOC
+#define CONFIG_ENV_IS_IN_MMC
+#define CONFIG_SYS_MMC_ENV_DEV	0
+#define CONFIG_ENV_SIZE		0x2000
+#define CONFIG_ENV_OFFSET	(512 * 1658)
+#elif defined(CONFIG_NAND)
+#define CONFIG_SYS_EXTRA_ENV_RELOC
+#define CONFIG_ENV_IS_IN_NAND
+#define CONFIG_ENV_SIZE		CONFIG_SYS_NAND_BLOCK_SIZE
+#define CONFIG_ENV_OFFSET	(2 * CONFIG_SYS_NAND_BLOCK_SIZE)
+#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
+#define CONFIG_ENV_IS_IN_REMOTE
+#define CONFIG_ENV_ADDR		0xffe20000
+#define CONFIG_ENV_SIZE		0x2000
+#elif defined(CONFIG_ENV_IS_NOWHERE)
+#define CONFIG_ENV_SIZE		0x2000
+#else
+#define CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE		0x2000
+#define CONFIG_ENV_SECT_SIZE	0x20000 /* 128K (one sector) */
+#endif
+
+#ifndef __ASSEMBLY__
+unsigned long get_board_sys_clk(void);
+unsigned long get_board_ddr_clk(void);
+#endif
+
+#define CONFIG_SYS_CLK_FREQ	66660000
+#define CONFIG_DDR_CLK_FREQ	133330000
+
+/*
+ * Config the L3 Cache as L3 SRAM
+ */
+#define CONFIG_SYS_INIT_L3_ADDR	 CONFIG_RAMBOOT_TEXT_BASE
+
+#define CONFIG_SYS_DCSRBAR	0xf0000000
+#define CONFIG_SYS_DCSRBAR_PHYS	0xf00000000ull
+
+/* EEPROM */
+#define CONFIG_ID_EEPROM
+#define CONFIG_SYS_I2C_EEPROM_NXID
+#define CONFIG_SYS_EEPROM_BUS_NUM	0
+#define CONFIG_SYS_I2C_EEPROM_ADDR	0x50
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	1
+
+/*
+ * DDR Setup
+ */
+#define CONFIG_VERY_BIG_RAM
+#define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000
+#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
+#define CONFIG_DIMM_SLOTS_PER_CTLR	1
+#define CONFIG_CHIP_SELECTS_PER_CTRL	(4 * CONFIG_DIMM_SLOTS_PER_CTLR)
+#define CONFIG_DDR_SPD
+#define CONFIG_SYS_FSL_DDR3
+#undef CONFIG_FSL_DDR_INTERACTIVE
+#define CONFIG_SYS_SPD_BUS_NUM	0
+#define CONFIG_SYS_SDRAM_SIZE	2048	/* for fixed parameter use */
+#define SPD_EEPROM_ADDRESS1	0x51
+#define SPD_EEPROM_ADDRESS2	0x52
+#define SPD_EEPROM_ADDRESS	SPD_EEPROM_ADDRESS1
+#define CTRL_INTLV_PREFERED	cacheline
+
+/*
+ * IFC Definitions
+ */
+#define CONFIG_SYS_FLASH_BASE		0xe8000000
+#define CONFIG_SYS_FLASH_BASE_PHYS	(0xf00000000ull | CONFIG_SYS_FLASH_BASE)
+#define CONFIG_SYS_NOR0_CSPR_EXT	(0xf)
+#define CONFIG_SYS_NOR0_CSPR	(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
+				CSPR_PORT_SIZE_16 | \
+				CSPR_MSEL_NOR | \
+				CSPR_V)
+#define CONFIG_SYS_NOR_AMASK	IFC_AMASK(128*1024*1024)
+
+/* NOR Flash Timing Params */
+#define CONFIG_SYS_NOR_CSOR	CSOR_NAND_TRHZ_80
+
+#define CONFIG_SYS_NOR_FTIM0	(FTIM0_NOR_TACSE(0x4) | \
+				FTIM0_NOR_TEADC(0x5) | \
+				FTIM0_NOR_TEAHC(0x5))
+#define CONFIG_SYS_NOR_FTIM1	(FTIM1_NOR_TACO(0x35) | \
+				FTIM1_NOR_TRAD_NOR(0x1A) |\
+				FTIM1_NOR_TSEQRAD_NOR(0x13))
+#define CONFIG_SYS_NOR_FTIM2	(FTIM2_NOR_TCS(0x4) | \
+				FTIM2_NOR_TCH(0x4) | \
+				FTIM2_NOR_TWPH(0x0E) | \
+				FTIM2_NOR_TWP(0x1c))
+#define CONFIG_SYS_NOR_FTIM3	0x0
+
+#define CONFIG_SYS_FLASH_QUIET_TEST
+#define CONFIG_FLASH_SHOW_PROGRESS	45 /* count down from 45/5: 9..1 */
+
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* number of banks */
+#define CONFIG_SYS_MAX_FLASH_SECT	1024	/* sectors per device */
+#define CONFIG_SYS_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+#define CONFIG_SYS_FLASH_BANKS_LIST	{CONFIG_SYS_FLASH_BASE_PHYS }
+
+/* CPLD on IFC */
+#define CONFIG_SYS_CPLD_BASE	0xffdf0000
+#define CONFIG_SYS_CPLD_BASE_PHYS	(0xf00000000ull | CONFIG_SYS_CPLD_BASE)
+#define CONFIG_SYS_CSPR2_EXT	(0xf)
+#define CONFIG_SYS_CSPR2	(CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE) \
+				| CSPR_PORT_SIZE_8 \
+				| CSPR_MSEL_GPCM \
+				| CSPR_V)
+#define CONFIG_SYS_AMASK2	IFC_AMASK(64*1024)
+#define CONFIG_SYS_CSOR2	0x0
+
+/* CPLD Timing parameters for IFC CS2 */
+#define CONFIG_SYS_CS2_FTIM0		(FTIM0_GPCM_TACSE(0x0e) | \
+					FTIM0_GPCM_TEADC(0x0e) | \
+					FTIM0_GPCM_TEAHC(0x0e))
+#define CONFIG_SYS_CS2_FTIM1		(FTIM1_GPCM_TACO(0x0e) | \
+					FTIM1_GPCM_TRAD(0x1f))
+#define CONFIG_SYS_CS2_FTIM2		(FTIM2_GPCM_TCS(0x0e) | \
+					FTIM2_GPCM_TCH(0x0) | \
+					FTIM2_GPCM_TWP(0x1f))
+#define CONFIG_SYS_CS2_FTIM3		0x0
+
+/* NAND Flash on IFC */
+#define CONFIG_NAND_FSL_IFC
+#define CONFIG_SYS_NAND_BASE		0xff800000
+#define CONFIG_SYS_NAND_BASE_PHYS	(0xf00000000ull | CONFIG_SYS_NAND_BASE)
+
+#define CONFIG_SYS_NAND_CSPR_EXT	(0xf)
+#define CONFIG_SYS_NAND_CSPR	(CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
+				| CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
+				| CSPR_MSEL_NAND	 /* MSEL = NAND */ \
+				| CSPR_V)
+#define CONFIG_SYS_NAND_AMASK	IFC_AMASK(64*1024)
+
+#define CONFIG_SYS_NAND_CSOR	(CSOR_NAND_ECC_ENC_EN	/* ECC on encode */ \
+				| CSOR_NAND_ECC_DEC_EN	/* ECC on decode */ \
+				| CSOR_NAND_ECC_MODE_4	/* 4-bit ECC */	    \
+				| CSOR_NAND_RAL_3	/* RAL = 2Byes */   \
+				| CSOR_NAND_PGS_2K	/* Page Size = 2K */\
+				| CSOR_NAND_SPRZ_64	/* Spare size = 64 */\
+				| CSOR_NAND_PB(64))	/*Pages Per Block = 64*/
+
+#define CONFIG_SYS_NAND_ONFI_DETECTION
+
+/* ONFI NAND Flash mode0 Timing Params */
+#define CONFIG_SYS_NAND_FTIM0		(FTIM0_NAND_TCCST(0x07) | \
+					FTIM0_NAND_TWP(0x18)    | \
+					FTIM0_NAND_TWCHT(0x07)  | \
+					FTIM0_NAND_TWH(0x0a))
+#define CONFIG_SYS_NAND_FTIM1		(FTIM1_NAND_TADLE(0x32) | \
+					FTIM1_NAND_TWBE(0x39)   | \
+					FTIM1_NAND_TRR(0x0e)    | \
+					FTIM1_NAND_TRP(0x18))
+#define CONFIG_SYS_NAND_FTIM2		(FTIM2_NAND_TRAD(0x0f)  | \
+					FTIM2_NAND_TREH(0x0a)   | \
+					FTIM2_NAND_TWHRE(0x1e))
+#define CONFIG_SYS_NAND_FTIM3		0x0
+
+#define CONFIG_SYS_NAND_DDR_LAW		11
+#define CONFIG_SYS_NAND_BASE_LIST	{ CONFIG_SYS_NAND_BASE }
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+#define CONFIG_MTD_NAND_VERIFY_WRITE
+#define CONFIG_CMD_NAND
+#define CONFIG_SYS_NAND_BLOCK_SIZE	(512 * 1024)
+
+#if defined(CONFIG_NAND)
+#define CONFIG_SYS_CSPR0_EXT		CONFIG_SYS_NAND_CSPR_EXT
+#define CONFIG_SYS_CSPR0		CONFIG_SYS_NAND_CSPR
+#define CONFIG_SYS_AMASK0		CONFIG_SYS_NAND_AMASK
+#define CONFIG_SYS_CSOR0		CONFIG_SYS_NAND_CSOR
+#define CONFIG_SYS_CS0_FTIM0		CONFIG_SYS_NAND_FTIM0
+#define CONFIG_SYS_CS0_FTIM1		CONFIG_SYS_NAND_FTIM1
+#define CONFIG_SYS_CS0_FTIM2		CONFIG_SYS_NAND_FTIM2
+#define CONFIG_SYS_CS0_FTIM3		CONFIG_SYS_NAND_FTIM3
+#define CONFIG_SYS_CSPR1_EXT		CONFIG_SYS_NOR0_CSPR_EXT
+#define CONFIG_SYS_CSPR1		CONFIG_SYS_NOR0_CSPR
+#define CONFIG_SYS_AMASK1		CONFIG_SYS_NOR_AMASK
+#define CONFIG_SYS_CSOR1		CONFIG_SYS_NOR_CSOR
+#define CONFIG_SYS_CS1_FTIM0		CONFIG_SYS_NOR_FTIM0
+#define CONFIG_SYS_CS1_FTIM1		CONFIG_SYS_NOR_FTIM1
+#define CONFIG_SYS_CS1_FTIM2		CONFIG_SYS_NOR_FTIM2
+#define CONFIG_SYS_CS1_FTIM3		CONFIG_SYS_NOR_FTIM3
+#else
+#define CONFIG_SYS_CSPR0_EXT		CONFIG_SYS_NOR0_CSPR_EXT
+#define CONFIG_SYS_CSPR0		CONFIG_SYS_NOR0_CSPR
+#define CONFIG_SYS_AMASK0		CONFIG_SYS_NOR_AMASK
+#define CONFIG_SYS_CSOR0		CONFIG_SYS_NOR_CSOR
+#define CONFIG_SYS_CS0_FTIM0		CONFIG_SYS_NOR_FTIM0
+#define CONFIG_SYS_CS0_FTIM1		CONFIG_SYS_NOR_FTIM1
+#define CONFIG_SYS_CS0_FTIM2		CONFIG_SYS_NOR_FTIM2
+#define CONFIG_SYS_CS0_FTIM3		CONFIG_SYS_NOR_FTIM3
+#define CONFIG_SYS_CSPR1_EXT		CONFIG_SYS_NAND_CSPR_EXT
+#define CONFIG_SYS_CSPR1		CONFIG_SYS_NAND_CSPR
+#define CONFIG_SYS_AMASK1		CONFIG_SYS_NAND_AMASK
+#define CONFIG_SYS_CSOR1		CONFIG_SYS_NAND_CSOR
+#define CONFIG_SYS_CS1_FTIM0		CONFIG_SYS_NAND_FTIM0
+#define CONFIG_SYS_CS1_FTIM1		CONFIG_SYS_NAND_FTIM1
+#define CONFIG_SYS_CS1_FTIM2		CONFIG_SYS_NAND_FTIM2
+#define CONFIG_SYS_CS1_FTIM3		CONFIG_SYS_NAND_FTIM3
+#endif
+
+#if defined(CONFIG_RAMBOOT_PBL)
+#define CONFIG_SYS_RAMBOOT
+#endif
+
+#define CONFIG_SYS_MONITOR_BASE	 CONFIG_SYS_TEXT_BASE
+#define CONFIG_BOARD_EARLY_INIT_R	/* call board_early_init_r function */
+#define CONFIG_MISC_INIT_R
+#define CONFIG_HWCONFIG
+
+/* define to use L1 as initial stack */
+#define CONFIG_L1_INIT_RAM
+#define CONFIG_SYS_INIT_RAM_LOCK
+#define CONFIG_SYS_INIT_RAM_ADDR	0xfdd00000 /* Initial L1 address */
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH	0xf
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW	0xfe0ec000
+/* The assembler doesn't like typecast */
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
+			((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
+			CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
+#define CONFIG_SYS_INIT_RAM_SIZE	0x00004000
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - \
+						GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+#define CONFIG_SYS_MONITOR_LEN		(512 * 1024)
+#define CONFIG_SYS_MALLOC_LEN		(4 * 1024 * 1024)
+
+/*
+ * Serial Port
+ */
+#define CONFIG_CONS_INDEX		1
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	1
+#define CONFIG_SYS_NS16550_CLK		(get_bus_freq(0)/2)
+#define CONFIG_SYS_BAUDRATE_TABLE	\
+	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
+#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
+#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
+#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
+#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
+
+/* Use the HUSH parser */
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
+
+/* pass open firmware flat tree */
+#define CONFIG_OF_LIBFDT
+#define CONFIG_OF_BOARD_SETUP
+#define CONFIG_OF_STDOUT_VIA_ALIAS
+
+/* new uImage format support */
+#define CONFIG_FIT
+#define CONFIG_FIT_VERBOSE	/* enable fit_format_{error,warning}() */
+
+/*
+ * I2C
+ */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_FSL
+#define CONFIG_SYS_FSL_I2C_SLAVE   0x7F
+#define CONFIG_SYS_FSL_I2C2_SLAVE  0x7F
+#define CONFIG_SYS_FSL_I2C3_SLAVE  0x7F
+#define CONFIG_SYS_FSL_I2C4_SLAVE  0x7F
+#define CONFIG_SYS_FSL_I2C_OFFSET  0x118000
+#define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100
+#define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000
+#define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100
+#define CONFIG_SYS_FSL_I2C_SPEED   100000
+#define CONFIG_SYS_FSL_I2C2_SPEED  100000
+#define CONFIG_SYS_FSL_I2C3_SPEED  100000
+#define CONFIG_SYS_FSL_I2C4_SPEED  100000
+#define I2C_MUX_PCA_ADDR_PRI	0x77 /* I2C bus multiplexer,primary */
+#define I2C_MUX_PCA_ADDR_SEC1	0x75 /* I2C bus multiplexer,secondary 1 */
+#define I2C_MUX_PCA_ADDR_SEC2	0x76 /* I2C bus multiplexer,secondary 2 */
+#define I2C_MUX_CH_DEFAULT	0x8
+
+
+/*
+ * RapidIO
+ */
+#define CONFIG_SYS_SRIO1_MEM_VIRT	0xa0000000
+#define CONFIG_SYS_SRIO1_MEM_PHYS	0xc20000000ull
+#define CONFIG_SYS_SRIO1_MEM_SIZE	0x10000000 /* 256M */
+#define CONFIG_SYS_SRIO2_MEM_VIRT	0xb0000000
+#define CONFIG_SYS_SRIO2_MEM_PHYS	0xc30000000ull
+#define CONFIG_SYS_SRIO2_MEM_SIZE	0x10000000 /* 256M */
+/*
+ * for slave u-boot IMAGE instored in master memory space,
+ * PHYS must be aligned based on the SIZE
+ */
+#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef080000ull
+#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff80000ull
+#define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE     0x80000 /* 512K */
+#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff80000ull
+/*
+ * for slave UCODE and ENV instored in master memory space,
+ * PHYS must be aligned based on the SIZE
+ */
+#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef040000ull
+#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
+#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE    0x40000	/* 256K */
+
+/* slave core release by master*/
+#define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
+#define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
+
+/*
+ * SRIO_PCIE_BOOT - SLAVE
+ */
+#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
+#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
+#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
+		(0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
+#endif
+
+/*
+ * eSPI - Enhanced SPI
+ */
+#ifdef CONFIG_SPI_FLASH
+#define CONFIG_FSL_ESPI
+#define CONFIG_SPI_FLASH_STMICRO
+#define CONFIG_SPI_FLASH_BAR
+#define CONFIG_CMD_SF
+#define CONFIG_SF_DEFAULT_SPEED	 10000000
+#define CONFIG_SF_DEFAULT_MODE	  0
+#endif
+
+/*
+ * General PCI
+ * Memory space is mapped 1-1, but I/O space must start from 0.
+ */
+#define CONFIG_PCI		/* Enable PCI/PCIE */
+#define CONFIG_PCIE1		/* PCIE controler 1 */
+#define CONFIG_PCIE2		/* PCIE controler 2 */
+#define CONFIG_PCIE3		/* PCIE controler 3 */
+#define CONFIG_PCIE4		/* PCIE controler 4 */
+#define CONFIG_FSL_PCI_INIT	/* Use common FSL init code */
+#define CONFIG_SYS_PCI_64BIT	/* enable 64-bit PCI resources */
+/* controller 1, direct to uli, tgtid 3, Base address 20000 */
+#define CONFIG_SYS_PCIE1_MEM_VIRT	0x80000000
+#define CONFIG_SYS_PCIE1_MEM_BUS	0xe0000000
+#define CONFIG_SYS_PCIE1_MEM_PHYS	0xc00000000ull
+#define CONFIG_SYS_PCIE1_MEM_SIZE	0x20000000      /* 512M */
+#define CONFIG_SYS_PCIE1_IO_VIRT	0xf8000000
+#define CONFIG_SYS_PCIE1_IO_BUS		0x00000000
+#define CONFIG_SYS_PCIE1_IO_PHYS	0xff8000000ull
+#define CONFIG_SYS_PCIE1_IO_SIZE	0x00010000	/* 64k */
+
+/* controller 2, Slot 2, tgtid 2, Base address 201000 */
+#define CONFIG_SYS_PCIE2_MEM_VIRT	0xa0000000
+#define CONFIG_SYS_PCIE2_MEM_BUS	0xe0000000
+#define CONFIG_SYS_PCIE2_MEM_PHYS	0xc20000000ull
+#define CONFIG_SYS_PCIE2_MEM_SIZE	0x10000000 /* 256M */
+#define CONFIG_SYS_PCIE2_IO_VIRT	0xf8010000
+#define CONFIG_SYS_PCIE2_IO_BUS		0x00000000
+#define CONFIG_SYS_PCIE2_IO_PHYS	0xff8010000ull
+#define CONFIG_SYS_PCIE2_IO_SIZE	0x00010000	/* 64k */
+
+/* controller 3, Slot 1, tgtid 1, Base address 202000 */
+#define CONFIG_SYS_PCIE3_MEM_VIRT	0xb0000000
+#define CONFIG_SYS_PCIE3_MEM_BUS	0xe0000000
+#define CONFIG_SYS_PCIE3_MEM_PHYS	0xc30000000ull
+#define CONFIG_SYS_PCIE3_MEM_SIZE	0x10000000	/* 256M */
+#define CONFIG_SYS_PCIE3_IO_VIRT	0xf8020000
+#define CONFIG_SYS_PCIE3_IO_BUS		0x00000000
+#define CONFIG_SYS_PCIE3_IO_PHYS	0xff8020000ull
+#define CONFIG_SYS_PCIE3_IO_SIZE	0x00010000	/* 64k */
+
+/* controller 4, Base address 203000 */
+#define CONFIG_SYS_PCIE4_MEM_VIRT       0xc0000000
+#define CONFIG_SYS_PCIE4_MEM_BUS	0xe0000000
+#define CONFIG_SYS_PCIE4_MEM_PHYS	0xc40000000ull
+#define CONFIG_SYS_PCIE4_MEM_SIZE	0x10000000	/* 256M */
+#define CONFIG_SYS_PCIE4_IO_BUS		0x00000000
+#define CONFIG_SYS_PCIE4_IO_PHYS	0xff8030000ull
+#define CONFIG_SYS_PCIE4_IO_SIZE	0x00010000	/* 64k */
+
+#ifdef CONFIG_PCI
+#define CONFIG_PCI_INDIRECT_BRIDGE
+#define CONFIG_FSL_PCIE_RESET           /* need PCIe reset errata LSZ ADD */
+#define CONFIG_NET_MULTI
+#define CONFIG_E1000
+#define CONFIG_PCI_PNP		/* do pci plug-and-play */
+#define CONFIG_PCI_SCAN_SHOW	/* show pci devices on startup */
+#define CONFIG_DOS_PARTITION
+#endif
+
+/* Qman/Bman */
+#ifndef CONFIG_NOBQFMAN
+#define CONFIG_SYS_DPAA_QBMAN		/* Support Q/Bman */
+#define CONFIG_SYS_BMAN_NUM_PORTALS	18
+#define CONFIG_SYS_BMAN_MEM_BASE	0xf4000000
+#define CONFIG_SYS_BMAN_MEM_PHYS	0xff4000000ull
+#define CONFIG_SYS_BMAN_MEM_SIZE	0x02000000
+#define CONFIG_SYS_QMAN_NUM_PORTALS	18
+#define CONFIG_SYS_QMAN_MEM_BASE	0xf6000000
+#define CONFIG_SYS_QMAN_MEM_PHYS	0xff6000000ull
+#define CONFIG_SYS_QMAN_MEM_SIZE	0x02000000
+
+#define CONFIG_SYS_DPAA_FMAN
+#define CONFIG_SYS_DPAA_PME
+#define CONFIG_SYS_PMAN
+#define CONFIG_SYS_DPAA_DCE
+#define CONFIG_SYS_DPAA_RMAN		/* RMan */
+#define CONFIG_SYS_INTERLAKEN
+
+/* Default address of microcode for the Linux Fman driver */
+#if defined(CONFIG_SPIFLASH)
+/*
+ * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
+ * env, so we got 0x110000.
+ */
+#define CONFIG_SYS_QE_FW_IN_SPIFLASH
+#define CONFIG_SYS_QE_FMAN_FW_ADDR	0x110000
+#define CONFIG_CORTINA_FW_ADDR		0x120000
+
+#elif defined(CONFIG_SDCARD)
+/*
+ * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
+ * about 825KB (1650 blocks), Env is stored after the image, and the env size is
+ * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680.
+ */
+#define CONFIG_SYS_QE_FMAN_FW_IN_MMC
+#define CONFIG_SYS_QE_FMAN_FW_ADDR	(512 * 1680)
+#define CONFIG_CORTINA_FW_ADDR		(512 * 1808)
+
+#elif defined(CONFIG_NAND)
+#define CONFIG_SYS_QE_FMAN_FW_IN_NAND
+#define CONFIG_SYS_QE_FMAN_FW_ADDR	(6 * CONFIG_SYS_NAND_BLOCK_SIZE)
+#define CONFIG_CORTINA_FW_ADDR		(7 * CONFIG_SYS_NAND_BLOCK_SIZE)
+#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
+/*
+ * Slave has no ucode locally, it can fetch this from remote. When implementing
+ * in two corenet boards, slave's ucode could be stored in master's memory
+ * space, the address can be mapped from slave TLB->slave LAW->
+ * slave SRIO or PCIE outbound window->master inbound window->
+ * master LAW->the ucode address in master's memory space.
+ */
+#define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE
+#define CONFIG_SYS_QE_FMAN_FW_ADDR	0xFFE00000
+#define CONFIG_CORTINA_FW_ADDR		0xFFE10000
+#else
+#define CONFIG_SYS_QE_FMAN_FW_IN_NOR
+#define CONFIG_SYS_QE_FMAN_FW_ADDR	0xEFF00000
+#define CONFIG_CORTINA_FW_ADDR		0xEFE00000
+#endif
+#define CONFIG_SYS_QE_FMAN_FW_LENGTH	0x10000
+#define CONFIG_SYS_FDT_PAD		(0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
+#endif /* CONFIG_NOBQFMAN */
+
+#ifdef CONFIG_SYS_DPAA_FMAN
+#define CONFIG_FMAN_ENET
+#define CONFIG_PHYLIB_10G
+#define CONFIG_PHY_CORTINA
+#define CONFIG_PHY_AQ1202
+#define CONFIG_PHY_REALTEK
+#define CONFIG_CORTINA_FW_LENGTH	0x40000
+#define RGMII_PHY1_ADDR		0x01  /* RealTek RTL8211E */
+#define RGMII_PHY2_ADDR		0x02
+#define CORTINA_PHY_ADDR1	0x0c  /* Cortina CS4315 */
+#define CORTINA_PHY_ADDR2	0x0d
+#define FM1_10GEC3_PHY_ADDR	0x00  /* Aquantia AQ1202 10G Base-T */
+#define FM1_10GEC4_PHY_ADDR	0x01
+#endif
+
+
+#ifdef CONFIG_FMAN_ENET
+#define CONFIG_MII		/* MII PHY management */
+#define CONFIG_ETHPRIME		"FM1@DTSEC3"
+#define CONFIG_PHY_GIGE		/* Include GbE speed/duplex detection */
+#endif
+
+/*
+ * SATA
+ */
+#ifdef CONFIG_FSL_SATA_V2
+#define CONFIG_LIBATA
+#define CONFIG_FSL_SATA
+#define CONFIG_SYS_SATA_MAX_DEVICE	2
+#define CONFIG_SATA1
+#define CONFIG_SYS_SATA1		CONFIG_SYS_MPC85xx_SATA1_ADDR
+#define CONFIG_SYS_SATA1_FLAGS		FLAGS_DMA
+#define CONFIG_SATA2
+#define CONFIG_SYS_SATA2		CONFIG_SYS_MPC85xx_SATA2_ADDR
+#define CONFIG_SYS_SATA2_FLAGS		FLAGS_DMA
+#define CONFIG_LBA48
+#define CONFIG_CMD_SATA
+#define CONFIG_DOS_PARTITION
+#define CONFIG_CMD_EXT2
+#endif
+
+/*
+ * USB
+ */
+#ifdef CONFIG_USB_EHCI
+#define CONFIG_CMD_USB
+#define CONFIG_USB_STORAGE
+#define CONFIG_USB_EHCI_FSL
+#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
+#define CONFIG_CMD_EXT2
+#define CONFIG_HAS_FSL_DR_USB
+#endif
+
+/*
+ * SDHC
+ */
+#ifdef CONFIG_MMC
+#define CONFIG_CMD_MMC
+#define CONFIG_FSL_ESDHC
+#define CONFIG_SYS_FSL_ESDHC_ADDR	CONFIG_SYS_MPC85xx_ESDHC_ADDR
+#define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
+#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
+#define CONFIG_GENERIC_MMC
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_FAT
+#define CONFIG_DOS_PARTITION
+#endif
+
+/*
+ * Environment
+ */
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_ECHO
+#define CONFIG_CMD_SETEXPR
+#define CONFIG_CMD_REGINFO
+#define CONFIG_CMD_BDI
+
+#ifdef CONFIG_PCI
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_NET
+#endif
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP		/* undef to save memory */
+#define CONFIG_CMDLINE_EDITING		/* Command-line editing */
+#define CONFIG_AUTO_COMPLETE		/* add autocompletion support */
+#define CONFIG_SYS_LOAD_ADDR	0x2000000 /* default load address */
+#define CONFIG_SYS_PROMPT	"=> "	  /* Monitor Command Prompt */
+#ifdef CONFIG_CMD_KGDB
+#define CONFIG_SYS_CBSIZE	1024	  /* Console I/O Buffer Size */
+#else
+#define CONFIG_SYS_CBSIZE	256	  /* Console I/O Buffer Size */
+#endif
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
+#define CONFIG_SYS_MAXARGS	16	/* max number of command args */
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
+#define CONFIG_SYS_HZ		1000	/* decrementer freq: 1ms ticks*/
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 64 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ	(64 << 20)	/* Initial map for Linux*/
+#define CONFIG_SYS_BOOTM_LEN	(64 << 20)	/* Increase max gunzip size */
+
+#ifdef CONFIG_CMD_KGDB
+#define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
+#define CONFIG_KGDB_SER_INDEX	2	/* which serial port to use */
+#endif
+
+/*
+ * Environment Configuration
+ */
+#define CONFIG_ROOTPATH	 "/opt/nfsroot"
+#define CONFIG_BOOTFILE	 "uImage"
+#define CONFIG_UBOOTPATH "u-boot.bin"	/* U-Boot image on TFTP server */
+
+/* default location for tftp and bootm */
+#define CONFIG_LOADADDR		1000000
+#define CONFIG_BAUDRATE		115200
+#define CONFIG_BOOTDELAY	10	/* -1 disables auto-boot */
+#define __USB_PHY_TYPE		utmi
+
+#define	CONFIG_EXTRA_ENV_SETTINGS				\
+	"hwconfig=fsl_ddr:"					\
+	"ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) ","	\
+	"bank_intlv=auto;"					\
+	"usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
+	"netdev=eth0\0"						\
+	"uboot=" __stringify(CONFIG_UBOOTPATH) "\0"		\
+	"ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"	\
+	"tftpflash=tftpboot $loadaddr $uboot && "		\
+	"protect off $ubootaddr +$filesize && "			\
+	"erase $ubootaddr +$filesize && "			\
+	"cp.b $loadaddr $ubootaddr $filesize && "		\
+	"protect on $ubootaddr +$filesize && "			\
+	"cmp.b $loadaddr $ubootaddr $filesize\0"		\
+	"consoledev=ttyS0\0"					\
+	"ramdiskaddr=2000000\0"					\
+	"ramdiskfile=t2080rdb/ramdisk.uboot\0"			\
+	"fdtaddr=c00000\0"					\
+	"fdtfile=t2080rdb/t2080rdb.dtb\0"			\
+	"bdev=sda3\0"						\
+	"c=ffe\0"
+
+/*
+ * For emulation this causes u-boot to jump to the start of the
+ * proof point app code automatically
+ */
+#define CONFIG_PROOF_POINTS				\
+	"setenv bootargs root=/dev/$bdev rw "		\
+	"console=$consoledev,$baudrate $othbootargs;"	\
+	"cpu 1 release 0x29000000 - - -;"		\
+	"cpu 2 release 0x29000000 - - -;"		\
+	"cpu 3 release 0x29000000 - - -;"		\
+	"cpu 4 release 0x29000000 - - -;"		\
+	"cpu 5 release 0x29000000 - - -;"		\
+	"cpu 6 release 0x29000000 - - -;"		\
+	"cpu 7 release 0x29000000 - - -;"		\
+	"go 0x29000000"
+
+#define CONFIG_HVBOOT				\
+	"setenv bootargs config-addr=0x60000000; "	\
+	"bootm 0x01000000 - 0x00f00000"
+
+#define CONFIG_ALU				\
+	"setenv bootargs root=/dev/$bdev rw "		\
+	"console=$consoledev,$baudrate $othbootargs;"	\
+	"cpu 1 release 0x01000000 - - -;"		\
+	"cpu 2 release 0x01000000 - - -;"		\
+	"cpu 3 release 0x01000000 - - -;"		\
+	"cpu 4 release 0x01000000 - - -;"		\
+	"cpu 5 release 0x01000000 - - -;"		\
+	"cpu 6 release 0x01000000 - - -;"		\
+	"cpu 7 release 0x01000000 - - -;"		\
+	"go 0x01000000"
+
+#define CONFIG_LINUX				\
+	"setenv bootargs root=/dev/ram rw "		\
+	"console=$consoledev,$baudrate $othbootargs;"	\
+	"setenv ramdiskaddr 0x02000000;"		\
+	"setenv fdtaddr 0x00c00000;"			\
+	"setenv loadaddr 0x1000000;"			\
+	"bootm $loadaddr $ramdiskaddr $fdtaddr"
+
+#define CONFIG_HDBOOT					\
+	"setenv bootargs root=/dev/$bdev rw "		\
+	"console=$consoledev,$baudrate $othbootargs;"	\
+	"tftp $loadaddr $bootfile;"			\
+	"tftp $fdtaddr $fdtfile;"			\
+	"bootm $loadaddr - $fdtaddr"
+
+#define CONFIG_NFSBOOTCOMMAND			\
+	"setenv bootargs root=/dev/nfs rw "	\
+	"nfsroot=$serverip:$rootpath "		\
+	"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
+	"console=$consoledev,$baudrate $othbootargs;"	\
+	"tftp $loadaddr $bootfile;"		\
+	"tftp $fdtaddr $fdtfile;"		\
+	"bootm $loadaddr - $fdtaddr"
+
+#define CONFIG_RAMBOOTCOMMAND				\
+	"setenv bootargs root=/dev/ram rw "		\
+	"console=$consoledev,$baudrate $othbootargs;"	\
+	"tftp $ramdiskaddr $ramdiskfile;"		\
+	"tftp $loadaddr $bootfile;"			\
+	"tftp $fdtaddr $fdtfile;"			\
+	"bootm $loadaddr $ramdiskaddr $fdtaddr"
+
+#define CONFIG_BOOTCOMMAND		CONFIG_LINUX
+
+#ifdef CONFIG_SECURE_BOOT
+#include <asm/fsl_secure_boot.h>
+#undef CONFIG_CMD_USB
+#endif
+
+#endif	/* __T2080RDB_H */
diff --git a/include/configs/T4240EMU.h b/include/configs/T4240EMU.h
index 5e228f3556..c81c4577e3 100644
--- a/include/configs/T4240EMU.h
+++ b/include/configs/T4240EMU.h
@@ -98,7 +98,7 @@
 #define CONFIG_SYS_INTERLAKEN
 
 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
-#define CONFIG_SYS_QE_FMAN_FW_ADDR		0xEFF40000
+#define CONFIG_SYS_QE_FMAN_FW_ADDR		0xEFF00000
 #define CONFIG_SYS_QE_FMAN_FW_LENGTH	0x10000
 #define CONFIG_SYS_FDT_PAD		(0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
 
@@ -122,7 +122,7 @@
 	"bank_intlv=auto;"					\
 	"netdev=eth0\0"						\
 	"uboot=" __stringify(CONFIG_UBOOTPATH) "\0"			\
-	"ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"		\
+"ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"		\
 	"consoledev=ttyS0\0"					\
 	"ramdiskaddr=2000000\0"					\
 	"ramdiskfile=t4240emu/ramdisk.uboot\0"			\
diff --git a/include/configs/T4240QDS.h b/include/configs/T4240QDS.h
index 92a30ab09f..56e1293720 100644
--- a/include/configs/T4240QDS.h
+++ b/include/configs/T4240QDS.h
@@ -21,8 +21,8 @@
 #ifdef CONFIG_RAMBOOT_PBL
 #define CONFIG_RAMBOOT_TEXT_BASE	CONFIG_SYS_TEXT_BASE
 #define CONFIG_RESET_VECTOR_ADDRESS	0xfffffffc
-#define CONFIG_PBLPBI_CONFIG $(SRCTREE)/board/freescale/t4qds/t4_pbi.cfg
-#define CONFIG_PBLRCW_CONFIG $(SRCTREE)/board/freescale/t4qds/t4_rcw.cfg
+#define CONFIG_SYS_FSL_PBL_PBI board/freescale/t4qds/t4_pbi.cfg
+#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t4qds/t4_rcw.cfg
 #endif
 
 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
@@ -64,12 +64,12 @@
 #define CONFIG_ENV_IS_IN_MMC
 #define CONFIG_SYS_MMC_ENV_DEV          0
 #define CONFIG_ENV_SIZE			0x2000
-#define CONFIG_ENV_OFFSET		(512 * 1097)
+#define CONFIG_ENV_OFFSET		(512 * 1658)
 #elif defined(CONFIG_NAND)
 #define CONFIG_SYS_EXTRA_ENV_RELOC
 #define CONFIG_ENV_IS_IN_NAND
 #define CONFIG_ENV_SIZE			CONFIG_SYS_NAND_BLOCK_SIZE
-#define CONFIG_ENV_OFFSET		(5 * CONFIG_SYS_NAND_BLOCK_SIZE)
+#define CONFIG_ENV_OFFSET		(7 * CONFIG_SYS_NAND_BLOCK_SIZE)
 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
 #define CONFIG_ENV_IS_IN_REMOTE
 #define CONFIG_ENV_ADDR		0xffe20000
@@ -165,6 +165,9 @@ unsigned long get_board_ddr_clk(void);
 #define QIXIS_RCFG_CTL_RECONFIG_IDLE	0x20
 #define QIXIS_RCFG_CTL_RECONFIG_START	0x21
 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE	0x08
+#define QIXIS_BRDCFG5			0x55
+#define QIXIS_MUX_SDHC			2
+#define QIXIS_MUX_SDHC_WIDTH8		1
 #define QIXIS_BASE_PHYS		(0xf00000000ull | QIXIS_BASE)
 
 #define CONFIG_SYS_CSPR3_EXT	(0xf)
@@ -229,6 +232,8 @@ unsigned long get_board_ddr_clk(void);
 #define CONFIG_CMD_NAND
 
 #define CONFIG_SYS_NAND_BLOCK_SIZE	(128 * 1024)
+#define CONFIG_SYS_NAND_MAX_OOBFREE	2
+#define CONFIG_SYS_NAND_MAX_ECCPOS	256
 
 #if defined(CONFIG_NAND)
 #define CONFIG_SYS_CSPR0_EXT		CONFIG_SYS_NAND_CSPR_EXT
@@ -374,14 +379,14 @@ unsigned long get_board_ddr_clk(void);
 #elif defined(CONFIG_SDCARD)
 /*
  * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
- * about 545KB (1089 blocks), Env is stored after the image, and the env size is
- * 0x2000 (16 blocks), 8 + 1089 + 16 = 1113, enlarge it to 1130.
+ * about 825KB (1650 blocks), Env is stored after the image, and the env size is
+ * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680.
  */
 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC
-#define CONFIG_SYS_QE_FMAN_FW_ADDR	(512 * 1130)
+#define CONFIG_SYS_QE_FMAN_FW_ADDR	(512 * 1680)
 #elif defined(CONFIG_NAND)
 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND
-#define CONFIG_SYS_QE_FMAN_FW_ADDR	(6 * CONFIG_SYS_NAND_BLOCK_SIZE)
+#define CONFIG_SYS_QE_FMAN_FW_ADDR	(8 * CONFIG_SYS_NAND_BLOCK_SIZE)
 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
 /*
  * Slave has no ucode locally, it can fetch this from remote. When implementing
@@ -394,7 +399,7 @@ unsigned long get_board_ddr_clk(void);
 #define CONFIG_SYS_QE_FMAN_FW_ADDR	0xFFE00000
 #else
 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
-#define CONFIG_SYS_QE_FMAN_FW_ADDR		0xEFF40000
+#define CONFIG_SYS_QE_FMAN_FW_ADDR		0xEFF00000
 #endif
 #define CONFIG_SYS_QE_FMAN_FW_LENGTH	0x10000
 #define CONFIG_SYS_FDT_PAD		(0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
@@ -463,6 +468,12 @@ unsigned long get_board_ddr_clk(void);
 #define CONFIG_CMD_EXT2
 #define CONFIG_CMD_FAT
 #define CONFIG_DOS_PARTITION
+#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
+#define CONFIG_ESDHC_DETECT_QUIRK \
+	(!(readb(QIXIS_BASE + QIXIS_BRDCFG5) & QIXIS_MUX_SDHC) || \
+	IS_SVR_REV(get_svr(), 1, 0))
+#define CONFIG_ESDHC_DETECT_8_BIT_QUIRK \
+	(!(readb(QIXIS_BASE + QIXIS_BRDCFG5) & QIXIS_MUX_SDHC_WIDTH8))
 #endif
 
 #define CONFIG_BOOTDELAY	10	/* -1 disables auto-boot */
@@ -553,8 +564,6 @@ unsigned long get_board_ddr_clk(void);
 
 #define CONFIG_BOOTCOMMAND		CONFIG_LINUX
 
-#ifdef CONFIG_SECURE_BOOT
 #include <asm/fsl_secure_boot.h>
-#endif
 
 #endif	/* __CONFIG_H */
diff --git a/include/configs/TASREG.h b/include/configs/TASREG.h
index e1a2c12c61..5ad9383622 100644
--- a/include/configs/TASREG.h
+++ b/include/configs/TASREG.h
@@ -61,7 +61,6 @@
 
 #define CONFIG_BOOTDELAY	3
 
-#define CONFIG_SYS_PROMPT		"=> "
 #define CONFIG_SYS_LONGHELP				/* undef to save memory		*/
 
 #if defined(CONFIG_CMD_KGDB)
@@ -84,8 +83,6 @@
 #define CONFIG_SYS_MEMTEST_START	0x400
 #define CONFIG_SYS_MEMTEST_END		0x380000
 
-#define CONFIG_SYS_HZ			1000
-
 /*
  * Clock configuration: enable only one of the following options
  */
diff --git a/include/configs/TB5200.h b/include/configs/TB5200.h
index 47e74e7999..b4daedceea 100644
--- a/include/configs/TB5200.h
+++ b/include/configs/TB5200.h
@@ -16,8 +16,7 @@
  * (easy to change)
  */
 
-#define CONFIG_MPC5xxx		1	/* This is an MPC5xxx CPU */
-#define CONFIG_MPC5200		1	/* (more precisely an MPC5200 CPU) */
+#define CONFIG_MPC5200		1	/* This is an MPC5200 CPU */
 #define CONFIG_TQM5200		1	/* ... on TQM5200 module */
 #define CONFIG_TB5200		1	/* ... on a TB5200 base board */
 
@@ -386,7 +385,6 @@
  * Miscellaneous configurable options
  */
 #define CONFIG_SYS_LONGHELP			/* undef to save memory	    */
-#define CONFIG_SYS_PROMPT		"=> "	/* Monitor Command Prompt   */
 #define CONFIG_CMDLINE_EDITING	1	/* add command line history */
 #if defined(CONFIG_CMD_KGDB)
 #define CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size  */
@@ -410,8 +408,6 @@
 
 #define CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address */
 
-#define CONFIG_SYS_HZ			1000	/* decrementer freq: 1 ms ticks */
-
 /*
  * Enable loopw command.
  */
diff --git a/include/configs/TK885D.h b/include/configs/TK885D.h
index 4ad857e98d..5e1c52d85a 100644
--- a/include/configs/TK885D.h
+++ b/include/configs/TK885D.h
@@ -154,7 +154,6 @@
  * Miscellaneous configurable options
  */
 #define CONFIG_SYS_LONGHELP			/* undef to save memory		*/
-#define CONFIG_SYS_PROMPT		"=> "	/* Monitor Command Prompt	*/
 
 #define CONFIG_CMDLINE_EDITING	1	/* add command line history	*/
 #define CONFIG_SYS_HUSH_PARSER		1	/* Use the HUSH parser		*/
@@ -175,8 +174,6 @@
 
 #define CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address */
 
-#define CONFIG_SYS_HZ			1000	/* decrementer freq: 1 ms ticks */
-
 /*
  * Enable loopw command.
  */
diff --git a/include/configs/TOP5200.h b/include/configs/TOP5200.h
index b5f330fb6f..92128b9588 100644
--- a/include/configs/TOP5200.h
+++ b/include/configs/TOP5200.h
@@ -25,8 +25,7 @@
  * (easy to change)
  */
 
-#define CONFIG_MPC5xxx		1	/* This is an MPC5xxx CPU */
-#define CONFIG_MPC5200		1	/* More exactly a MPC5200 */
+#define CONFIG_MPC5200		1	/* This is a MPC5200 CPU */
 #define CONFIG_TOP5200		1	/* ... on TOP5200 board - we need this for FEC.C */
 
 /*
@@ -317,7 +316,6 @@
  * Miscellaneous configurable options
  */
 #define CONFIG_SYS_LONGHELP			/* undef to save memory	    */
-#define CONFIG_SYS_PROMPT		"=> "	/* Monitor Command Prompt   */
 #if defined(CONFIG_CMD_KGDB)
 #  define CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size  */
 #else
@@ -332,8 +330,6 @@
 
 #define CONFIG_SYS_LOAD_ADDR		0x200000	/* default load address */
 
-#define CONFIG_SYS_HZ			1000	/* decrementer freq: 1 ms ticks */
-
 #define CONFIG_SYS_CACHELINE_SIZE	32	/* For MPC5xxx CPUs */
 #if defined(CONFIG_CMD_KGDB)
 #  define CONFIG_SYS_CACHELINE_SHIFT	5	/* log base 2 of the above value */
diff --git a/include/configs/TOP860.h b/include/configs/TOP860.h
index 5c5ce84ff1..da68503a69 100644
--- a/include/configs/TOP860.h
+++ b/include/configs/TOP860.h
@@ -68,7 +68,6 @@
 #define	CONFIG_SYS_CPUCLOCK	CONFIG_SYSCLK
 #define	CONFIG_SYS_BRGCLOCK	CONFIG_SYSCLK
 #define	CONFIG_SYS_BUSCLOCK	(CONFIG_SYSCLK >> CONFIG_EBDF)
-#define CONFIG_SYS_HZ			1000	/* decrementer freq: 1 ms ticks */
 #define	CONFIG_8xx_GCLK_FREQ	CONFIG_SYSCLK
 
 /*-----------------------------------------------------------------------
@@ -118,7 +117,6 @@
 
 
 #define CONFIG_SYS_LONGHELP			/* undef to save memory		*/
-#define CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt	*/
 
 #undef	CONFIG_SYS_HUSH_PARSER			/* Hush parse for U-Boot	*/
 
diff --git a/include/configs/TQM5200.h b/include/configs/TQM5200.h
index 6a9f64e17b..69c0336cae 100644
--- a/include/configs/TQM5200.h
+++ b/include/configs/TQM5200.h
@@ -16,8 +16,7 @@
  * (easy to change)
  */
 
-#define CONFIG_MPC5xxx		1	/* This is an MPC5xxx CPU		*/
-#define CONFIG_MPC5200		1	/* (more precisely an MPC5200 CPU)	*/
+#define CONFIG_MPC5200		1	/* This is an MPC5200 CPU		*/
 #define CONFIG_TQM5200		1	/* ... on TQM5200 module		*/
 #undef CONFIG_TQM5200_REV100		/*  define for revision 100 modules	*/
 
@@ -605,7 +604,6 @@
  * Miscellaneous configurable options
  */
 #define CONFIG_SYS_LONGHELP			/* undef to save memory	    */
-#define CONFIG_SYS_PROMPT		"=> "	/* Monitor Command Prompt   */
 
 #define CONFIG_CMDLINE_EDITING	1	/* add command line history	*/
 #define	CONFIG_SYS_HUSH_PARSER		1	/* use "hush" command parser	*/
@@ -632,8 +630,6 @@
 
 #define CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address */
 
-#define CONFIG_SYS_HZ			1000	/* decrementer freq: 1 ms ticks */
-
 /*
  * Enable loopw command.
  */
diff --git a/include/configs/TQM823L.h b/include/configs/TQM823L.h
index 0221d16a44..cc2204586e 100644
--- a/include/configs/TQM823L.h
+++ b/include/configs/TQM823L.h
@@ -127,7 +127,6 @@
  * Miscellaneous configurable options
  */
 #define	CONFIG_SYS_LONGHELP			/* undef to save memory		*/
-#define	CONFIG_SYS_PROMPT		"=> "	/* Monitor Command Prompt	*/
 
 #define CONFIG_CMDLINE_EDITING	1	/* add command line history	*/
 #define CONFIG_SYS_HUSH_PARSER		1	/* Use the HUSH parser		*/
@@ -146,8 +145,6 @@
 
 #define	CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address	*/
 
-#define	CONFIG_SYS_HZ			1000	/* decrementer freq: 1 ms ticks	*/
-
 /*
  * Low Level Configuration Settings
  * (address mappings, register initial values, etc.)
diff --git a/include/configs/TQM823M.h b/include/configs/TQM823M.h
index 514bbecd54..4fd070f27d 100644
--- a/include/configs/TQM823M.h
+++ b/include/configs/TQM823M.h
@@ -122,7 +122,6 @@
  * Miscellaneous configurable options
  */
 #define	CONFIG_SYS_LONGHELP			/* undef to save memory		*/
-#define	CONFIG_SYS_PROMPT		"=> "	/* Monitor Command Prompt	*/
 
 #define CONFIG_CMDLINE_EDITING	1	/* add command line history	*/
 #define CONFIG_SYS_HUSH_PARSER		1	/* Use the HUSH parser		*/
@@ -141,8 +140,6 @@
 
 #define	CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address	*/
 
-#define	CONFIG_SYS_HZ			1000	/* decrementer freq: 1 ms ticks	*/
-
 /*
  * Low Level Configuration Settings
  * (address mappings, register initial values, etc.)
diff --git a/include/configs/TQM8260.h b/include/configs/TQM8260.h
index 1b02cbbca7..7fd12d3fbc 100644
--- a/include/configs/TQM8260.h
+++ b/include/configs/TQM8260.h
@@ -30,7 +30,6 @@
 
 #define	CONFIG_SYS_TEXT_BASE	0x40000000
 
-#define CONFIG_MPC8260		1	/* This is a MPC8260 CPU		*/
 
 #if 0
 #define CONFIG_TQM8260		100	/* ...on a TQM8260 module Rev.100	*/
@@ -228,7 +227,6 @@
  * Miscellaneous configurable options
  */
 #define	CONFIG_SYS_LONGHELP			/* undef to save memory		*/
-#define	CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt	*/
 
 #define CONFIG_CMDLINE_EDITING	1	/* add command line history	*/
 #define CONFIG_SYS_HUSH_PARSER		1	/* Use the HUSH parser		*/
@@ -247,8 +245,6 @@
 
 #define	CONFIG_SYS_LOAD_ADDR	0x100000	/* default load address	*/
 
-#define	CONFIG_SYS_HZ		1000		/* decrementer freq: 1 ms ticks	*/
-
 #define	CONFIG_SYS_RESET_ADDRESS 0xFFFFFFFC	/* "bad" address		*/
 
 /*
diff --git a/include/configs/TQM8272.h b/include/configs/TQM8272.h
index 3f586fbbc1..9c7e16305d 100644
--- a/include/configs/TQM8272.h
+++ b/include/configs/TQM8272.h
@@ -17,7 +17,6 @@
  * (easy to change)
  */
 
-#define CONFIG_MPC8260		1	/* This is a MPC8260 CPU		*/
 #define CONFIG_MPC8272_FAMILY   1
 #define CONFIG_TQM8272		1
 
@@ -290,7 +289,6 @@
  * Miscellaneous configurable options
  */
 #define	CONFIG_SYS_LONGHELP			/* undef to save memory		*/
-#define	CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt	*/
 
 #if 0
 #define CONFIG_CMDLINE_EDITING	1	/* add command line history	*/
@@ -311,8 +309,6 @@
 
 #define	CONFIG_SYS_LOAD_ADDR	0x300000	/* default load address	*/
 
-#define	CONFIG_SYS_HZ		1000		/* decrementer freq: 1 ms ticks	*/
-
 #define	CONFIG_SYS_RESET_ADDRESS 0x40000104	/* "bad" address		*/
 
 /*
diff --git a/include/configs/TQM834x.h b/include/configs/TQM834x.h
index 194dc8b62a..6762e3a57e 100644
--- a/include/configs/TQM834x.h
+++ b/include/configs/TQM834x.h
@@ -16,7 +16,6 @@
  * High Level Configuration Options
  */
 #define CONFIG_E300		1	/* E300 Family */
-#define CONFIG_MPC83xx		1	/* MPC83xx family */
 #define CONFIG_MPC834x		1	/* MPC834x specific */
 #define CONFIG_MPC8349		1	/* MPC8349 specific */
 #define CONFIG_TQM834X		1	/* TQM834X board specific */
@@ -316,7 +315,6 @@
  */
 #define CONFIG_SYS_LONGHELP			/* undef to save memory	*/
 #define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
-#define CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt */
 
 #define CONFIG_CMDLINE_EDITING	1	/* add command line history */
 #define CONFIG_AUTO_COMPLETE		/* add autocompletion support */
@@ -334,7 +332,6 @@
 #define CONFIG_SYS_MAXARGS	16	/* max number of command args */
 				/* Boot Argument Buffer Size */
 #define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE
-#define CONFIG_SYS_HZ		1000	/* decrementer freq: 1ms ticks */
 
 #undef CONFIG_WATCHDOG		/* watchdog disabled */
 
@@ -497,7 +494,6 @@
 
 #if defined(CONFIG_CMD_KGDB)
 #define CONFIG_KGDB_BAUDRATE	230400	/* speed of kgdb serial port */
-#define CONFIG_KGDB_SER_INDEX	2	/* which serial port to use */
 #endif
 
 /*
diff --git a/include/configs/TQM850L.h b/include/configs/TQM850L.h
index fc854d9916..ca3750d407 100644
--- a/include/configs/TQM850L.h
+++ b/include/configs/TQM850L.h
@@ -111,7 +111,6 @@
  * Miscellaneous configurable options
  */
 #define	CONFIG_SYS_LONGHELP			/* undef to save memory		*/
-#define	CONFIG_SYS_PROMPT		"=> "	/* Monitor Command Prompt	*/
 
 #define CONFIG_CMDLINE_EDITING	1	/* add command line history	*/
 #define CONFIG_SYS_HUSH_PARSER		1	/* Use the HUSH parser		*/
@@ -130,8 +129,6 @@
 
 #define	CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address	*/
 
-#define	CONFIG_SYS_HZ			1000	/* decrementer freq: 1 ms ticks	*/
-
 /*
  * Low Level Configuration Settings
  * (address mappings, register initial values, etc.)
diff --git a/include/configs/TQM850M.h b/include/configs/TQM850M.h
index 7bf685da05..659c9ad1c3 100644
--- a/include/configs/TQM850M.h
+++ b/include/configs/TQM850M.h
@@ -112,7 +112,6 @@
  * Miscellaneous configurable options
  */
 #define	CONFIG_SYS_LONGHELP			/* undef to save memory		*/
-#define	CONFIG_SYS_PROMPT		"=> "	/* Monitor Command Prompt	*/
 
 #define CONFIG_CMDLINE_EDITING	1	/* add command line history	*/
 #define CONFIG_SYS_HUSH_PARSER		1	/* Use the HUSH parser		*/
@@ -131,8 +130,6 @@
 
 #define	CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address	*/
 
-#define	CONFIG_SYS_HZ			1000	/* decrementer freq: 1 ms ticks	*/
-
 /*
  * Low Level Configuration Settings
  * (address mappings, register initial values, etc.)
diff --git a/include/configs/TQM855L.h b/include/configs/TQM855L.h
index f8bf75b713..906d79b0c8 100644
--- a/include/configs/TQM855L.h
+++ b/include/configs/TQM855L.h
@@ -115,7 +115,6 @@
  * Miscellaneous configurable options
  */
 #define	CONFIG_SYS_LONGHELP			/* undef to save memory		*/
-#define	CONFIG_SYS_PROMPT		"=> "	/* Monitor Command Prompt	*/
 
 #define CONFIG_CMDLINE_EDITING	1	/* add command line history	*/
 #define CONFIG_SYS_HUSH_PARSER		1	/* Use the HUSH parser		*/
@@ -134,8 +133,6 @@
 
 #define	CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address	*/
 
-#define	CONFIG_SYS_HZ			1000	/* decrementer freq: 1 ms ticks	*/
-
 /*
  * Low Level Configuration Settings
  * (address mappings, register initial values, etc.)
diff --git a/include/configs/TQM855M.h b/include/configs/TQM855M.h
index 37e3541d68..44d456e165 100644
--- a/include/configs/TQM855M.h
+++ b/include/configs/TQM855M.h
@@ -145,7 +145,6 @@
  * Miscellaneous configurable options
  */
 #define	CONFIG_SYS_LONGHELP			/* undef to save memory		*/
-#define	CONFIG_SYS_PROMPT		"=> "	/* Monitor Command Prompt	*/
 
 #define CONFIG_CMDLINE_EDITING	1	/* add command line history	*/
 #define CONFIG_SYS_HUSH_PARSER		1	/* Use the HUSH parser		*/
@@ -164,8 +163,6 @@
 
 #define	CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address	*/
 
-#define	CONFIG_SYS_HZ			1000	/* decrementer freq: 1 ms ticks	*/
-
 /*
  * Low Level Configuration Settings
  * (address mappings, register initial values, etc.)
diff --git a/include/configs/TQM860L.h b/include/configs/TQM860L.h
index a6e36b3de3..855b0cddc4 100644
--- a/include/configs/TQM860L.h
+++ b/include/configs/TQM860L.h
@@ -114,7 +114,6 @@
  * Miscellaneous configurable options
  */
 #define	CONFIG_SYS_LONGHELP			/* undef to save memory		*/
-#define	CONFIG_SYS_PROMPT		"=> "	/* Monitor Command Prompt	*/
 
 #define CONFIG_CMDLINE_EDITING	1	/* add command line history	*/
 #define CONFIG_SYS_HUSH_PARSER		1	/* Use the HUSH parser		*/
@@ -133,8 +132,6 @@
 
 #define	CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address	*/
 
-#define	CONFIG_SYS_HZ			1000	/* decrementer freq: 1 ms ticks	*/
-
 /*
  * Low Level Configuration Settings
  * (address mappings, register initial values, etc.)
diff --git a/include/configs/TQM860M.h b/include/configs/TQM860M.h
index 78ecb47692..8109379ae9 100644
--- a/include/configs/TQM860M.h
+++ b/include/configs/TQM860M.h
@@ -115,7 +115,6 @@
  * Miscellaneous configurable options
  */
 #define	CONFIG_SYS_LONGHELP			/* undef to save memory		*/
-#define	CONFIG_SYS_PROMPT		"=> "	/* Monitor Command Prompt	*/
 
 #define CONFIG_CMDLINE_EDITING	1	/* add command line history	*/
 #define CONFIG_SYS_HUSH_PARSER		1	/* Use the HUSH parser		*/
@@ -134,8 +133,6 @@
 
 #define	CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address	*/
 
-#define	CONFIG_SYS_HZ			1000	/* decrementer freq: 1 ms ticks	*/
-
 /*
  * Low Level Configuration Settings
  * (address mappings, register initial values, etc.)
diff --git a/include/configs/TQM862L.h b/include/configs/TQM862L.h
index 379698a55f..da4af93d25 100644
--- a/include/configs/TQM862L.h
+++ b/include/configs/TQM862L.h
@@ -118,7 +118,6 @@
  * Miscellaneous configurable options
  */
 #define	CONFIG_SYS_LONGHELP			/* undef to save memory		*/
-#define	CONFIG_SYS_PROMPT		"=> "	/* Monitor Command Prompt	*/
 
 #define CONFIG_CMDLINE_EDITING	1	/* add command line history	*/
 #define CONFIG_SYS_HUSH_PARSER		1	/* Use the HUSH parser		*/
@@ -137,8 +136,6 @@
 
 #define	CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address	*/
 
-#define	CONFIG_SYS_HZ			1000	/* decrementer freq: 1 ms ticks	*/
-
 /*
  * Low Level Configuration Settings
  * (address mappings, register initial values, etc.)
diff --git a/include/configs/TQM862M.h b/include/configs/TQM862M.h
index ca7dd35fc0..ec3a57b961 100644
--- a/include/configs/TQM862M.h
+++ b/include/configs/TQM862M.h
@@ -118,7 +118,6 @@
  * Miscellaneous configurable options
  */
 #define	CONFIG_SYS_LONGHELP			/* undef to save memory		*/
-#define	CONFIG_SYS_PROMPT		"=> "	/* Monitor Command Prompt	*/
 
 #define CONFIG_CMDLINE_EDITING	1	/* add command line history	*/
 #define CONFIG_SYS_HUSH_PARSER		1	/* Use the HUSH parser		*/
@@ -137,8 +136,6 @@
 
 #define	CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address	*/
 
-#define	CONFIG_SYS_HZ			1000	/* decrementer freq: 1 ms ticks	*/
-
 /*
  * Low Level Configuration Settings
  * (address mappings, register initial values, etc.)
diff --git a/include/configs/TQM866M.h b/include/configs/TQM866M.h
index 30e94013b0..cb8b84d3a1 100644
--- a/include/configs/TQM866M.h
+++ b/include/configs/TQM866M.h
@@ -158,7 +158,6 @@
  * Miscellaneous configurable options
  */
 #define CONFIG_SYS_LONGHELP			/* undef to save memory		*/
-#define CONFIG_SYS_PROMPT		"=> "	/* Monitor Command Prompt	*/
 
 #define CONFIG_CMDLINE_EDITING	1	/* add command line history	*/
 #define CONFIG_SYS_HUSH_PARSER		1	/* Use the HUSH parser		*/
@@ -177,8 +176,6 @@
 
 #define CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address */
 
-#define CONFIG_SYS_HZ			1000	/* decrementer freq: 1 ms ticks */
-
 /*
  * Low Level Configuration Settings
  * (address mappings, register initial values, etc.)
diff --git a/include/configs/TQM885D.h b/include/configs/TQM885D.h
index 8263752573..d1e6c5b2bb 100644
--- a/include/configs/TQM885D.h
+++ b/include/configs/TQM885D.h
@@ -152,7 +152,6 @@
  * Miscellaneous configurable options
  */
 #define CONFIG_SYS_LONGHELP			/* undef to save memory		*/
-#define CONFIG_SYS_PROMPT		"=> "	/* Monitor Command Prompt	*/
 
 #define CONFIG_CMDLINE_EDITING	1	/* add command line history	*/
 #define CONFIG_SYS_HUSH_PARSER		1	/* Use the HUSH parser		*/
@@ -173,8 +172,6 @@
 
 #define CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address */
 
-#define CONFIG_SYS_HZ			1000	/* decrementer freq: 1 ms ticks */
-
 /*
  * Enable loopw command.
  */
diff --git a/include/configs/Total5200.h b/include/configs/Total5200.h
index dbd281415b..a58eecab84 100644
--- a/include/configs/Total5200.h
+++ b/include/configs/Total5200.h
@@ -24,8 +24,7 @@
  * (easy to change)
  */
 
-#define CONFIG_MPC5xxx		1	/* This is an MPC5xxx CPU */
-#define CONFIG_MPC5200		1	/* (more precisely a MPC5200 CPU) */
+#define CONFIG_MPC5200		1	/* This is a MPC5200 CPU */
 #define CONFIG_TOTAL5200	1	/* ... on Total5200 board */
 
 /*
@@ -279,7 +278,6 @@
  * Miscellaneous configurable options
  */
 #define CONFIG_SYS_LONGHELP			/* undef to save memory	    */
-#define CONFIG_SYS_PROMPT		"=> "	/* Monitor Command Prompt   */
 #if defined(CONFIG_CMD_KGDB)
 #define CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size  */
 #else
@@ -294,8 +292,6 @@
 
 #define CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address */
 
-#define CONFIG_SYS_HZ			1000	/* decrementer freq: 1 ms ticks */
-
 #define CONFIG_SYS_CACHELINE_SIZE	32	/* For MPC5xxx CPUs */
 #if defined(CONFIG_CMD_KGDB)
 #  define CONFIG_SYS_CACHELINE_SHIFT	5	/* log base 2 of the above value */
diff --git a/include/configs/VCMA9.h b/include/configs/VCMA9.h
index 20344937bd..d40185e1e2 100644
--- a/include/configs/VCMA9.h
+++ b/include/configs/VCMA9.h
@@ -73,12 +73,12 @@
  * the MPL VCMA9 is equipped with an ATMEL 24C256 EEPROM at
  * address 0x50 with 16bit addressing
  */
-#define CONFIG_HARD_I2C				/* I2C with hardware support */
-#define CONFIG_SYS_I2C_SPEED		100000	/* I2C speed */
-#define CONFIG_SYS_I2C_SLAVE		0x7F	/* I2C slave addr */
+#define CONFIG_SYS_I2C
 
 /* we use the built-in I2C controller */
-#define CONFIG_DRIVER_S3C24X0_I2C
+#define CONFIG_SYS_I2C_S3C24X0
+#define CONFIG_SYS_I2C_S3C24X0_SPEED    100000	/* I2C speed */
+#define CONFIG_SYS_I2C_S3C24X0_SLAVE    0x7F	/* I2C slave addr */
 
 #define CONFIG_SYS_I2C_EEPROM_ADDR	0x50
 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	2
@@ -138,8 +138,6 @@
 #if defined(CONFIG_CMD_KGDB)
 /* speed to run kgdb serial port */
 #define CONFIG_KGDB_BAUDRATE		115200
-/* what's this ? it's not used anywhere */
-#define CONFIG_KGDB_SER_INDEX		2	/* which serial port to use */
 #endif
 
 /* Miscellaneous configurable options */
@@ -162,7 +160,6 @@
 #define CONFIG_SYS_LOAD_ADDR		0x30800000
 
 /* we configure PWM Timer 4 to 1ms 1000Hz  */
-#define CONFIG_SYS_HZ			1000
 
 /* support additional compression methods */
 #define CONFIG_BZIP2
diff --git a/include/configs/VOH405.h b/include/configs/VOH405.h
index 91fd93b331..d4a4b68c80 100644
--- a/include/configs/VOH405.h
+++ b/include/configs/VOH405.h
@@ -18,7 +18,6 @@
  */
 
 #define CONFIG_405EP		1	/* This is a PPC405 CPU		*/
-#define CONFIG_4xx		1	/* ...member of PPC4xx family	*/
 #define CONFIG_VOH405		1	/* ...on a VOH405 board		*/
 
 #define	CONFIG_SYS_TEXT_BASE	0xFFF80000
@@ -93,7 +92,6 @@
  * Miscellaneous configurable options
  */
 #define CONFIG_SYS_LONGHELP			/* undef to save memory		*/
-#define CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt	*/
 
 #undef	CONFIG_SYS_HUSH_PARSER			/* use "hush" command parser	*/
 
@@ -132,8 +130,6 @@
 #define CONFIG_SYS_LOAD_ADDR	0x100000	/* default load address */
 #define CONFIG_SYS_EXTBDINFO	1		/* To use extended board_into (bd_t) */
 
-#define CONFIG_SYS_HZ		1000		/* decrementer freq: 1 ms ticks */
-
 #define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */
 
 #define CONFIG_VERSION_VARIABLE 1	/* include version env variable */
diff --git a/include/configs/VOM405.h b/include/configs/VOM405.h
index 4a2ee91dda..c06897b893 100644
--- a/include/configs/VOM405.h
+++ b/include/configs/VOM405.h
@@ -16,7 +16,6 @@
  * (easy to change)
  */
 #define CONFIG_405EP		1	/* This is a PPC405 CPU		*/
-#define CONFIG_4xx		1	/* ...member of PPC4xx family	*/
 #define CONFIG_VOM405		1	/* ...on a VOM405 board		*/
 
 #define	CONFIG_SYS_TEXT_BASE	0xFFFC8000
@@ -82,7 +81,6 @@
  * Miscellaneous configurable options
  */
 #define CONFIG_SYS_LONGHELP			/* undef to save memory		*/
-#define CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt	*/
 
 #undef	CONFIG_SYS_HUSH_PARSER			/* use "hush" command parser	*/
 
@@ -119,8 +117,6 @@
 #define CONFIG_SYS_LOAD_ADDR	0x100000	/* default load address */
 #define CONFIG_SYS_EXTBDINFO	1		/* To use extended board_into (bd_t) */
 
-#define CONFIG_SYS_HZ		1000		/* decrementer freq: 1 ms ticks */
-
 #define CONFIG_CMDLINE_EDITING	1	/* add command line history	*/
 #define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */
 
diff --git a/include/configs/VoVPN-GW.h b/include/configs/VoVPN-GW.h
index c4f680bec7..1ceef113d6 100644
--- a/include/configs/VoVPN-GW.h
+++ b/include/configs/VoVPN-GW.h
@@ -203,7 +203,6 @@
 #define	CONFIG_SYS_LONGHELP
 
 /* monitor command prompt */
-#define	CONFIG_SYS_PROMPT			"=> "
 
 /* console i/o buffer size */
 #if defined(CONFIG_CMD_KGDB)
@@ -232,7 +231,6 @@
 #define	CONFIG_SYS_LOAD_ADDR			0x00100000
 
 /* decrementer freq: 1 ms ticks	*/
-#define	CONFIG_SYS_HZ				1000
 
 /* configure flash */
 #define CONFIG_SYS_FLASH_BASE			0xff800000
diff --git a/include/configs/W7OLMC.h b/include/configs/W7OLMC.h
index 54ca4997b5..895ad4611b 100644
--- a/include/configs/W7OLMC.h
+++ b/include/configs/W7OLMC.h
@@ -18,7 +18,6 @@
  */
 
 #define CONFIG_405GP		1		/* This is a PPC405GP CPU	*/
-#define CONFIG_4xx		1		/* ...member of PPC405 family	*/
 #define CONFIG_W7O		1		/* ...on a Wave 7 Optics board	*/
 #define CONFIG_W7OLMC		1		/* ...specifically an LMC	*/
 
@@ -126,8 +125,6 @@
 #define CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address		*/
 #define CONFIG_SYS_EXTBDINFO		1		/* use extended board_info (bd_t) */
 
-#define CONFIG_SYS_HZ			1000		/* decrementer freq: 1 ms ticks */
-
 /*-----------------------------------------------------------------------
  * PCI stuff
  *-----------------------------------------------------------------------
@@ -303,7 +300,6 @@
 
 #if defined(CONFIG_CMD_KGDB)
 #define CONFIG_KGDB_BAUDRATE	230400		/* speed to run kgdb serial port */
-#define CONFIG_KGDB_SER_INDEX	2		/* which serial port to use	*/
 #endif
 
 /*
diff --git a/include/configs/W7OLMG.h b/include/configs/W7OLMG.h
index ac194a4efa..2a38116dd1 100644
--- a/include/configs/W7OLMG.h
+++ b/include/configs/W7OLMG.h
@@ -18,7 +18,6 @@
  */
 
 #define CONFIG_405GP		1		/* This is a PPC405GP CPU	*/
-#define CONFIG_4xx		1		/* ...member of PPC405 family	*/
 #define CONFIG_W7O		1		/* ...on a Wave 7 Optics board	*/
 #define CONFIG_W7OLMG		1		/* ...specifically an LMG	*/
 
@@ -134,8 +133,6 @@
 #define CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address		*/
 #define CONFIG_SYS_EXTBDINFO		1		/* use extended board_info (bd_t) */
 
-#define CONFIG_SYS_HZ			1000		/* decrementer freq: 1 ms ticks */
-
 /*-----------------------------------------------------------------------
  * PCI stuff
  *-----------------------------------------------------------------------
@@ -306,7 +303,6 @@
 
 #if defined(CONFIG_CMD_KGDB)
 #define CONFIG_KGDB_BAUDRATE	230400		/* speed to run kgdb serial port */
-#define CONFIG_KGDB_SER_INDEX	2		/* which serial port to use	*/
 #endif
 
 /*
diff --git a/include/configs/WUH405.h b/include/configs/WUH405.h
index 6999384653..e4f0d19a41 100644
--- a/include/configs/WUH405.h
+++ b/include/configs/WUH405.h
@@ -19,7 +19,6 @@
 #define CONFIG_IDENT_STRING     " $Name:  $"
 
 #define CONFIG_405EP		1	/* This is a PPC405 CPU		*/
-#define CONFIG_4xx		1	/* ...member of PPC4xx family	*/
 #define CONFIG_WUH405		1	/* ...on a WUH405 board		*/
 
 #define	CONFIG_SYS_TEXT_BASE	0xFFFC0000
@@ -84,7 +83,6 @@
  * Miscellaneous configurable options
  */
 #define CONFIG_SYS_LONGHELP			/* undef to save memory		*/
-#define CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt	*/
 
 #undef	CONFIG_SYS_HUSH_PARSER			/* use "hush" command parser	*/
 
@@ -121,8 +119,6 @@
 #define CONFIG_SYS_LOAD_ADDR	0x100000	/* default load address */
 #define CONFIG_SYS_EXTBDINFO	1		/* To use extended board_into (bd_t) */
 
-#define CONFIG_SYS_HZ		1000		/* decrementer freq: 1 ms ticks */
-
 #define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */
 
 #define CONFIG_VERSION_VARIABLE 1	/* include version env variable */
diff --git a/include/configs/ZPC1900.h b/include/configs/ZPC1900.h
index c28f21d1fb..d76a140728 100644
--- a/include/configs/ZPC1900.h
+++ b/include/configs/ZPC1900.h
@@ -11,7 +11,6 @@
 #ifndef __CONFIG_H
 #define __CONFIG_H
 
-#define CONFIG_MPC8260		1	/* This is an MPC8260 CPU      */
 #define CONFIG_ZPC1900		1	/* ...on Zephyr ZPC.1900 board */
 
 #define	CONFIG_SYS_TEXT_BASE	0xFE000000
@@ -139,7 +138,6 @@
  */
 #define CONFIG_SYS_HUSH_PARSER
 #define CONFIG_SYS_LONGHELP			/* undef to save memory	    */
-#define CONFIG_SYS_PROMPT		"=> "	/* Monitor Command Prompt   */
 #if defined(CONFIG_CMD_KGDB)
 #define CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size  */
 #else
@@ -154,8 +152,6 @@
 
 #define CONFIG_SYS_LOAD_ADDR		0x400000	/* default load address */
 
-#define CONFIG_SYS_HZ			1000	/* decrementer freq: 1 ms ticks */
-
 #define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
 
 #define CONFIG_SYS_SDRAM_BASE		0x00000000
diff --git a/include/configs/ZUMA.h b/include/configs/ZUMA.h
index 80a381595c..cac6a677ba 100644
--- a/include/configs/ZUMA.h
+++ b/include/configs/ZUMA.h
@@ -131,7 +131,6 @@
  * Miscellaneous configurable options
  */
 #define CONFIG_SYS_LONGHELP			/* undef to save memory		*/
-#define CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt	*/
 #if defined(CONFIG_CMD_KGDB)
 #define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
 #else
@@ -146,8 +145,6 @@
 
 #define CONFIG_SYS_LOAD_ADDR		0x00300000	/* default load address */
 
-#define CONFIG_SYS_HZ			1000		/* decr freq: 1ms ticks */
-
 #define CONFIG_SYS_BUS_CLK		133000000	/* 133 MHz		*/
 
 #define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
diff --git a/include/configs/a320evb.h b/include/configs/a320evb.h
index bcb7ab47ba..0d3cf369b6 100644
--- a/include/configs/a320evb.h
+++ b/include/configs/a320evb.h
@@ -37,7 +37,6 @@
 /*
  * Timer
  */
-#define CONFIG_SYS_HZ		1000	/* timer ticks per second */
 
 /*
  * Real Time Clock
diff --git a/include/configs/a3m071.h b/include/configs/a3m071.h
index 43d3d99bcb..205adfd8ce 100644
--- a/include/configs/a3m071.h
+++ b/include/configs/a3m071.h
@@ -13,8 +13,7 @@
  */
 
 #define CONFIG_MPC5200
-#define CONFIG_MPC5xxx		1	/* This is an MPC5xxx CPU */
-#define CONFIG_A3M071			/* ... on A3M071 board */
+#define CONFIG_A3M071			/* A3M071 board */
 
 #define	CONFIG_SYS_TEXT_BASE	0x01000000	/* boot low for 32 MiB boards */
 
@@ -59,6 +58,7 @@
 #define CONFIG_BOOTP_SERVERIP
 #define CONFIG_NET_RETRY_COUNT 3
 #define CONFIG_CMD_LINK_LOCAL
+#define CONFIG_LIB_RAND
 #define CONFIG_NETCONSOLE
 #define CONFIG_SYS_CONSOLE_IS_IN_ENV
 #define CONFIG_CMD_PING
@@ -245,7 +245,6 @@
  * Miscellaneous configurable options
  */
 #define CONFIG_SYS_LONGHELP
-#define CONFIG_SYS_PROMPT		"=> "
 
 #define CONFIG_CMDLINE_EDITING
 #define	CONFIG_SYS_HUSH_PARSER
@@ -265,7 +264,6 @@
 
 #define CONFIG_SYS_LOAD_ADDR		0x00100000
 
-#define CONFIG_SYS_HZ			1000
 #define CONFIG_LOOPW
 #define CONFIG_SYS_CONSOLE_INFO_QUIET	/* don't print console @ startup*/
 
diff --git a/include/configs/a4m072.h b/include/configs/a4m072.h
index 75b6526127..cc88ac1618 100644
--- a/include/configs/a4m072.h
+++ b/include/configs/a4m072.h
@@ -16,8 +16,7 @@
  * (easy to change)
  */
 
-#define CONFIG_MPC5xxx		1	/* This is an MPC5xxx CPU */
-#define CONFIG_MPC5200		1	/* (more precisely a MPC5200 CPU) */
+#define CONFIG_MPC5200		1	/* This is a MPC5200 CPU */
 #define CONFIG_A4M072		1	/* ... on A4M072 board */
 #define CONFIG_MPC5200_DDR	1	/* ... use DDR RAM */
 
@@ -271,7 +270,6 @@
 #define CONFIG_SYS_HUSH_PARSER
 #define CONFIG_CMDLINE_EDITING	1
 #define CONFIG_SYS_LONGHELP			/* undef to save memory	    */
-#define CONFIG_SYS_PROMPT		"=> "	/* Monitor Command Prompt   */
 #if defined(CONFIG_CMD_KGDB)
 #define CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size  */
 #else
@@ -286,8 +284,6 @@
 
 #define CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address */
 
-#define CONFIG_SYS_HZ			1000	/* decrementer freq: 1 ms ticks */
-
 #define CONFIG_SYS_CACHELINE_SIZE	32	/* For MPC5xxx CPUs */
 #if defined(CONFIG_CMD_KGDB)
 #  define CONFIG_SYS_CACHELINE_SHIFT	5	/* log base 2 of the above value */
diff --git a/include/configs/ac14xx.h b/include/configs/ac14xx.h
index a2090dac86..f57820d8f5 100644
--- a/include/configs/ac14xx.h
+++ b/include/configs/ac14xx.h
@@ -27,7 +27,6 @@
  * High Level Configuration Options
  */
 #define CONFIG_E300		1	/* E300 Family */
-#define CONFIG_MPC512X		1	/* MPC512X family */
 
 #define CONFIG_SYS_TEXT_BASE	0xFFF00000
 
@@ -290,9 +289,8 @@
 #define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_SRAM_BASE
 #define CONFIG_SYS_INIT_RAM_END		CONFIG_SYS_SRAM_SIZE
 
-#define CONFIG_SYS_GBL_DATA_SIZE	0x100
 #define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - \
-					 CONFIG_SYS_GBL_DATA_SIZE)
+					 GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 #define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_TEXT_BASE
@@ -440,9 +438,6 @@
 /* Boot Argument Buffer Size */
 #define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE
 
-/* decrementer freq: 1ms ticks */
-#define CONFIG_SYS_HZ		1000
-
 /*
  * For booting Linux, the board info and command line data
  * have to be in the first 8 MB of memory, since this is
@@ -474,7 +469,6 @@
 
 #ifdef CONFIG_CMD_KGDB
 #define CONFIG_KGDB_BAUDRATE		230400	/* speed of kgdb serial port */
-#define CONFIG_KGDB_SER_INDEX		2	/* which serial port to use */
 #endif
 
 /*
diff --git a/include/configs/acadia.h b/include/configs/acadia.h
index f23d549497..4dd5720d2f 100644
--- a/include/configs/acadia.h
+++ b/include/configs/acadia.h
@@ -16,7 +16,6 @@
  * High Level Configuration Options
  *----------------------------------------------------------------------*/
 #define CONFIG_ACADIA		1		/* Board is Acadia	*/
-#define CONFIG_4xx		1		/* ... PPC4xx family	*/
 #define CONFIG_405EZ		1		/* Specifc 405EZ support*/
 
 #ifndef CONFIG_SYS_TEXT_BASE
@@ -83,17 +82,11 @@
 /*-----------------------------------------------------------------------
  * Environment
  *----------------------------------------------------------------------*/
-#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
 #define CONFIG_ENV_IS_IN_FLASH     1	/* use FLASH for environment vars	*/
-#else
-#define CONFIG_ENV_IS_IN_NAND	1	/* use NAND for environment vars	*/
-#define CONFIG_ENV_IS_EMBEDDED	1	/* use embedded environment */
-#endif
 
 /*-----------------------------------------------------------------------
  * FLASH related
  *----------------------------------------------------------------------*/
-#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
 #define CONFIG_SYS_FLASH_CFI			/* The flash is CFI compatible	*/
 #define CONFIG_FLASH_CFI_DRIVER		/* Use common CFI driver	*/
 
@@ -107,16 +100,6 @@
 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1	/* use buffered writes (20x faster)	*/
 #define CONFIG_SYS_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
 
-#else
-/*
- * No NOR-flash on Acadia when NAND-booting. We need to undef the
- * NOR device-tree fixup code as well, since flash_info is not defined
- * in this case.
- */
-#define	CONFIG_SYS_NO_FLASH		1
-#undef CONFIG_FDT_FIXUP_NOR_FLASH_SIZE
-#endif
-
 #ifdef CONFIG_ENV_IS_IN_FLASH
 #define CONFIG_ENV_SECT_SIZE	0x40000 /* size of one complete sector	*/
 #define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE-CONFIG_ENV_SECT_SIZE)
@@ -127,61 +110,6 @@
 #define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SIZE)
 #endif
 
-/*
- * IPL (Initial Program Loader, integrated inside CPU)
- * Will load first 4k from NAND (SPL) into cache and execute it from there.
- *
- * SPL (Secondary Program Loader)
- * Will load special U-Boot version (NUB) from NAND and execute it. This SPL
- * has to fit into 4kByte. It sets up the CPU and configures the SDRAM
- * controller and the NAND controller so that the special U-Boot image can be
- * loaded from NAND to SDRAM.
- *
- * NUB (NAND U-Boot)
- * This NAND U-Boot (NUB) is a special U-Boot version which can be started
- * from RAM. Therefore it mustn't (re-)configure the SDRAM controller.
- *
- * On 440EPx the SPL is copied to SDRAM before the NAND controller is
- * set up. While still running from cache, I experienced problems accessing
- * the NAND controller.	sr - 2006-08-25
- */
-#define CONFIG_SYS_NAND_BOOT_SPL_SRC	0xfffff000	/* SPL location			*/
-#define CONFIG_SYS_NAND_BOOT_SPL_SIZE	(4 << 10)	/* SPL size			*/
-#define CONFIG_SYS_NAND_BOOT_SPL_DST	(CONFIG_SYS_OCM_DATA_ADDR + (16 << 10)) /* Copy SPL here*/
-#define CONFIG_SYS_NAND_U_BOOT_DST	0x01000000	/* Load NUB to this addr	*/
-#define CONFIG_SYS_NAND_U_BOOT_START	CONFIG_SYS_NAND_U_BOOT_DST /* Start NUB from this addr	*/
-#define CONFIG_SYS_NAND_BOOT_SPL_DELTA	(CONFIG_SYS_NAND_BOOT_SPL_SRC - CONFIG_SYS_NAND_BOOT_SPL_DST)
-
-/*
- * Define the partitioning of the NAND chip (only RAM U-Boot is needed here)
- */
-#define CONFIG_SYS_NAND_U_BOOT_OFFS	(16 << 10)	/* Offset to RAM U-Boot image	*/
-#define CONFIG_SYS_NAND_U_BOOT_SIZE	(384 << 10)	/* Size of RAM U-Boot image	*/
-
-/*
- * Now the NAND chip has to be defined (no autodetection used!)
- */
-#define CONFIG_SYS_NAND_PAGE_SIZE	512		/* NAND chip page size		*/
-#define CONFIG_SYS_NAND_BLOCK_SIZE	(16 << 10)	/* NAND chip block size		*/
-#define CONFIG_SYS_NAND_PAGE_COUNT	32		/* NAND chip page count		*/
-#define CONFIG_SYS_NAND_BAD_BLOCK_POS	5		/* Location of bad block marker	*/
-#undef CONFIG_SYS_NAND_4_ADDR_CYCLE			/* No fourth addr used (<=32MB)	*/
-
-#define CONFIG_SYS_NAND_ECCSIZE	256
-#define CONFIG_SYS_NAND_ECCBYTES	3
-#define CONFIG_SYS_NAND_OOBSIZE	16
-#define CONFIG_SYS_NAND_ECCPOS		{0, 1, 2, 3, 6, 7}
-
-#ifdef CONFIG_ENV_IS_IN_NAND
-/*
- * For NAND booting the environment is embedded in the U-Boot image. Please take
- * look at the file board/amcc/sequoia/u-boot-nand.lds for details.
- */
-#define CONFIG_ENV_SIZE		CONFIG_SYS_NAND_BLOCK_SIZE
-#define CONFIG_ENV_OFFSET		(CONFIG_SYS_NAND_U_BOOT_OFFS + CONFIG_ENV_SIZE)
-#define CONFIG_ENV_OFFSET_REDUND	(CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
-#endif
-
 /*-----------------------------------------------------------------------
  * RAM (CRAM)
  *----------------------------------------------------------------------*/
@@ -220,7 +148,6 @@
 	CONFIG_AMCC_DEF_ENV_POWERPC					\
 	CONFIG_AMCC_DEF_ENV_PPC_OLD					\
 	CONFIG_AMCC_DEF_ENV_NOR_UPD					\
-	CONFIG_AMCC_DEF_ENV_NAND_UPD					\
 	"kernel_addr=fff10000\0"					\
 	"ramdisk_addr=fff20000\0"					\
 	"kozio=bootm ffc60000\0"					\
@@ -243,14 +170,6 @@
 #define CONFIG_CMD_NAND
 #define CONFIG_CMD_USB
 
-/*
- * No NOR on Acadia when NAND-booting
- */
-#if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
-#undef CONFIG_CMD_FLASH
-#undef CONFIG_CMD_IMLS
-#endif
-
 /*-----------------------------------------------------------------------
  * NAND FLASH
  *----------------------------------------------------------------------*/
@@ -261,7 +180,6 @@
 /*-----------------------------------------------------------------------
  * External Bus Controller (EBC) Setup
  *----------------------------------------------------------------------*/
-#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
 #define CONFIG_SYS_NAND_CS		3
 /* Memory Bank 0 (Flash) initialization						*/
 #define CONFIG_SYS_EBC_PB0AP		0x03337200
@@ -279,24 +197,6 @@
 /* Memory Bank 2 (CRAM) initialization						*/
 #define CONFIG_SYS_EBC_PB2AP		0x030400c0
 #define CONFIG_SYS_EBC_PB2CR		0x020bc000
-#else
-#define CONFIG_SYS_NAND_CS		0		/* NAND chip connected to CSx	*/
-/* Memory Bank 0 (NAND-FLASH) initialization					*/
-#define CONFIG_SYS_EBC_PB0AP		0x018003c0
-#define CONFIG_SYS_EBC_PB0CR		(CONFIG_SYS_NAND_ADDR | 0x1c000)
-
-/*
- * When NAND-booting the CRAM EBC setup must be done in sync mode, since the
- * NAND-SPL already initialized the CRAM and EBC to sync mode.
- */
-/* Memory Bank 1 (CRAM) initialization						*/
-#define CONFIG_SYS_EBC_PB1AP		0x9C0201C0
-#define CONFIG_SYS_EBC_PB1CR		0x000bc000
-
-/* Memory Bank 2 (CRAM) initialization						*/
-#define CONFIG_SYS_EBC_PB2AP		0x9C0201C0
-#define CONFIG_SYS_EBC_PB2CR		0x020bc000
-#endif
 
 /* Memory Bank 4 (CPLD) initialization						*/
 #define CONFIG_SYS_EBC_PB4AP		0x04006000
diff --git a/include/configs/actux1.h b/include/configs/actux1.h
deleted file mode 100644
index 33669c2e83..0000000000
--- a/include/configs/actux1.h
+++ /dev/null
@@ -1,230 +0,0 @@
-/*
- * (C) Copyright 2007
- * Michael Schwingen, michael@schwingen.org
- *
- * Configuration settings for the AcTux-1 board.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#define CONFIG_IXP425			1
-#define CONFIG_ACTUX1			1
-
-#define	CONFIG_MACH_TYPE		1479
-
-#define CONFIG_DISPLAY_CPUINFO		1
-#define CONFIG_DISPLAY_BOARDINFO	1
-
-#define CONFIG_IXP_SERIAL
-#define CONFIG_SYS_IXP425_CONSOLE		IXP425_UART2
-#define CONFIG_BAUDRATE			115200
-#define CONFIG_BOOTDELAY		3
-#define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */
-#define CONFIG_BOARD_EARLY_INIT_F	1
-#define CONFIG_SYS_LDSCRIPT	"board/actux1/u-boot.lds"
-
-/***************************************************************
- * U-boot generic defines start here.
- ***************************************************************/
-/*
- * Size of malloc() pool
- */
-#define CONFIG_SYS_MALLOC_LEN			(CONFIG_ENV_SIZE + 128*1024)
-
-/* allow to overwrite serial and ethaddr */
-#define CONFIG_ENV_OVERWRITE
-
-/* Command line configuration. */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_ELF
-#ifdef CONFIG_PCI
-#define CONFIG_CMD_PCI
-#define CONFIG_PCI_PNP
-#define CONFIG_IXP_PCI
-#define CONFIG_PCI_SCAN_SHOW
-#define CONFIG_CMD_PCI_ENUM
-#endif
-
-#define CONFIG_BOOTCOMMAND		"run boot_flash"
-/* enable passing of ATAGs */
-#define CONFIG_CMDLINE_TAG		1
-#define CONFIG_SETUP_MEMORY_TAGS	1
-#define CONFIG_INITRD_TAG		1
-#define CONFIG_REVISION_TAG		1
-
-#if defined(CONFIG_CMD_KGDB)
-# define CONFIG_KGDB_BAUDRATE		230400
-/* which serial port to use */
-# define CONFIG_KGDB_SER_INDEX		1
-#endif
-
-/* Miscellaneous configurable options */
-#define CONFIG_SYS_LONGHELP
-#define CONFIG_SYS_PROMPT			"=> "
-/* Console I/O Buffer Size */
-#define CONFIG_SYS_CBSIZE			256
-/* Print Buffer Size */
-#define CONFIG_SYS_PBSIZE			(CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
-/* max number of command args */
-#define CONFIG_SYS_MAXARGS			16
-/* Boot Argument Buffer Size */
-#define CONFIG_SYS_BARGSIZE			CONFIG_SYS_CBSIZE
-
-#define CONFIG_SYS_MEMTEST_START		0x00400000
-#define CONFIG_SYS_MEMTEST_END			0x00800000
-
-/* timer clock - 2* OSC_IN system clock */
-#define CONFIG_IXP425_TIMER_CLK                 66666666
-#define CONFIG_SYS_HZ				1000
-
-/* default load address */
-#define CONFIG_SYS_LOAD_ADDR			0x00010000
-
-/* valid baudrates */
-#define CONFIG_SYS_BAUDRATE_TABLE		{ 9600, 19200, 38400, 57600,	\
-					  115200, 230400 }
-#define CONFIG_SERIAL_RTS_ACTIVE	1
-
-/* Expansion bus settings */
-#define CONFIG_SYS_EXP_CS0			0xbd113842
-
-/* SDRAM settings */
-#define CONFIG_NR_DRAM_BANKS		1
-#define PHYS_SDRAM_1			0x00000000
-#define CONFIG_SYS_SDRAM_BASE			0x00000000
-
-#ifdef CONFIG_RAM_32MB
-# define CONFIG_SYS_SDR_CONFIG			0x18
-# define PHYS_SDRAM_1_SIZE		0x02000000
-# define CONFIG_SYS_SDRAM_REFRESH_CNT		0x81a
-# define CONFIG_SYS_SDR_MODE_CONFIG		0x1
-# define CONFIG_SYS_DRAM_SIZE			0x02000000
-#else /* 16MB SDRAM */
-# define CONFIG_SYS_SDR_CONFIG			0x3A
-# define PHYS_SDRAM_1_SIZE		0x01000000
-# define CONFIG_SYS_SDRAM_REFRESH_CNT		0x81a
-# define CONFIG_SYS_SDR_MODE_CONFIG		0x1
-# define CONFIG_SYS_DRAM_SIZE			0x01000000
-#endif
-
-/* FLASH organization */
-#define CONFIG_SYS_TEXT_BASE		0x50000000
-#ifdef CONFIG_FLASH2X2
-# define CONFIG_SYS_MAX_FLASH_BANKS		2
-/* max number of sectors on one chip */
-# define CONFIG_SYS_MAX_FLASH_SECT		40
-# define PHYS_FLASH_1			0x50000000
-# define PHYS_FLASH_2			0x50200000
-# define CONFIG_SYS_FLASH_BANKS_LIST		{ PHYS_FLASH_1, PHYS_FLASH_2 }
-#endif
-#ifdef CONFIG_FLASH1X8
-# define CONFIG_SYS_MAX_FLASH_BANKS		1
-/* max number of sectors on one chip */
-# define CONFIG_SYS_MAX_FLASH_SECT		140
-# define PHYS_FLASH_1			0x50000000
-# define CONFIG_SYS_FLASH_BANKS_LIST		{ PHYS_FLASH_1 }
-#endif
-
-#define CONFIG_SYS_FLASH_BASE			PHYS_FLASH_1
-#define CONFIG_SYS_MONITOR_BASE		PHYS_FLASH_1
-#define CONFIG_SYS_MONITOR_LEN			(256 << 10)
-#define CONFIG_BOARD_SIZE_LIMIT			262144
-
-/* Use common CFI driver */
-#define CONFIG_SYS_FLASH_CFI
-#define CONFIG_FLASH_CFI_DRIVER
-/* no byte writes on IXP4xx */
-#define CONFIG_SYS_FLASH_CFI_WIDTH		FLASH_CFI_16BIT
-/* print 'E' for empty sector on flinfo */
-#define CONFIG_SYS_FLASH_EMPTY_INFO
-
-/* Ethernet */
-
-/* include IXP4xx NPE support */
-#define CONFIG_IXP4XX_NPE		1
-/* NPE0 PHY address */
-#define	CONFIG_PHY_ADDR			0
-/* NPE1 PHY address (HW Release E only) */
-#define	CONFIG_PHY1_ADDR		1
-/* MII PHY management */
-#define CONFIG_MII			1
-/* Number of ethernet rx buffers & descriptors */
-#define CONFIG_SYS_RX_ETH_BUFFER		16
-#define CONFIG_RESET_PHY_R		1
-
-#define CONFIG_HAS_ETH1			1
-
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_NET
-#define CONFIG_CMD_MII
-#define CONFIG_CMD_PING
-#undef  CONFIG_CMD_NFS
-
-/* BOOTP options */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-/* Cache Configuration */
-#define CONFIG_SYS_CACHELINE_SIZE		32
-
-/*
- * environment organization:
- * one flash sector, embedded in uboot area (bottom bootblock flash)
- */
-#define	CONFIG_ENV_IS_IN_FLASH		1
-#define CONFIG_ENV_SIZE			0x2000
-#define CONFIG_ENV_ADDR			(PHYS_FLASH_1 + 0x4000)
-#define CONFIG_SYS_USE_PPCENV			1
-
-#define CONFIG_EXTRA_ENV_SETTINGS					\
-	"npe_ucode=50040000\0"						\
-	"mtd=IXP4XX-Flash.0:256k(uboot),64k(ucode),1152k(linux),-(root)\0" \
-	"kerneladdr=50050000\0"						\
-	"kernelfile=actux1/uImage\0"					\
-	"rootfile=actux1/rootfs\0"					\
-	"rootaddr=50170000\0"						\
-	"loadaddr=10000\0"						\
-	"updateboot_ser=mw.b 10000 ff 40000;"				\
-	" loady ${loadaddr};"						\
-	" run eraseboot writeboot\0"					\
-	"updateboot_net=mw.b 10000 ff 40000;"				\
-	" tftp ${loadaddr} actux1/u-boot.bin;"				\
-	" run eraseboot writeboot\0"					\
-	"eraseboot=protect off 50000000 50003fff;"			\
-	" protect off 50006000 5003ffff;"				\
-	" erase 50000000 50003fff;"					\
-	" erase 50006000 5003ffff\0"					\
-	"writeboot=cp.b 10000 50000000 4000;"				\
-	" cp.b 16000 50006000 3a000\0"					\
-	"updateucode=loady;"						\
-	" era ${npe_ucode} +${filesize};"				\
-	" cp.b ${loadaddr} ${npe_ucode} ${filesize}\0"			\
-	"updateroot=tftp ${loadaddr} ${rootfile};"			\
-	" era ${rootaddr} +${filesize};"				\
-	" cp.b ${loadaddr} ${rootaddr} ${filesize}\0"			\
-	"updatekern=tftp ${loadaddr} ${kernelfile};"			\
-	" era ${kerneladdr} +${filesize};"				\
-	" cp.b ${loadaddr} ${kerneladdr} ${filesize}\0"			\
-	"flashargs=setenv bootargs mtdparts=${mtd} root=/dev/mtdblock3"	\
-	" rootfstype=squashfs,jffs2 init=/etc/preinit\0"		\
-	"netargs=setenv bootargs mtdparts=${mtd} root=/dev/mtdblock3"	\
-	" rootfstype=squashfs,jffs2 init=/etc/preinit\0"		\
-	"addtty=setenv bootargs ${bootargs} console=ttyS1,${baudrate}\0" \
-	"addeth=setenv bootargs ${bootargs} ethaddr=${ethaddr}\0"	\
-	"boot_flash=run flashargs addtty addeth;"			\
-	" bootm ${kerneladdr}\0"					\
-	"boot_net=run netargs addtty addeth;"				\
-	" tftpboot ${loadaddr} ${kernelfile};"				\
-	" bootm\0"
-
-/* additions for new relocation code, must be added to all boards */
-#define CONFIG_SYS_INIT_SP_ADDR						\
-	(CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE)
-
-#endif /* __CONFIG_H */
diff --git a/include/configs/actux2.h b/include/configs/actux2.h
deleted file mode 100644
index 533f46976a..0000000000
--- a/include/configs/actux2.h
+++ /dev/null
@@ -1,210 +0,0 @@
-/*
- * (C) Copyright 2007
- * Michael Schwingen, michael@schwingen.org
- *
- * Configuration settings for the AcTux-2 board.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#define CONFIG_IXP425			1
-#define CONFIG_ACTUX2			1
-
-#define	CONFIG_MACH_TYPE		1480
-
-#define CONFIG_DISPLAY_CPUINFO		1
-#define CONFIG_DISPLAY_BOARDINFO	1
-
-#define CONFIG_IXP_SERIAL
-#define CONFIG_SYS_IXP425_CONSOLE		IXP425_UART2
-#define CONFIG_BAUDRATE			115200
-#define CONFIG_BOOTDELAY		5
-#define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */
-#define CONFIG_BOARD_EARLY_INIT_F	1
-#define CONFIG_SYS_LDSCRIPT	"board/actux2/u-boot.lds"
-
-/***************************************************************
- * U-boot generic defines start here.
- ***************************************************************/
-/* Size of malloc() pool */
-#define CONFIG_SYS_MALLOC_LEN			(CONFIG_ENV_SIZE + 128*1024)
-
-/* allow to overwrite serial and ethaddr */
-#define CONFIG_ENV_OVERWRITE
-
-/* Command line configuration. */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_ELF
-#undef CONFIG_CMD_PCI
-#undef CONFIG_PCI
-
-#define CONFIG_BOOTCOMMAND		"run boot_flash"
-/* enable passing of ATAGs */
-#define CONFIG_CMDLINE_TAG		1
-#define CONFIG_SETUP_MEMORY_TAGS	1
-#define CONFIG_INITRD_TAG		1
-#define CONFIG_REVISION_TAG		1
-
-#if defined(CONFIG_CMD_KGDB)
-# define CONFIG_KGDB_BAUDRATE		230400
-/* which serial port to use */
-# define CONFIG_KGDB_SER_INDEX		1
-#endif
-
-/* Miscellaneous configurable options */
-#define CONFIG_SYS_LONGHELP
-#define CONFIG_SYS_PROMPT			"=> "
-/* Console I/O Buffer Size */
-#define CONFIG_SYS_CBSIZE			256
-/* Print Buffer Size */
-#define CONFIG_SYS_PBSIZE			(CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
-/* max number of command args */
-#define CONFIG_SYS_MAXARGS			16
-/* Boot Argument Buffer Size */
-#define CONFIG_SYS_BARGSIZE			CONFIG_SYS_CBSIZE
-
-#define CONFIG_SYS_MEMTEST_START		0x00400000
-#define CONFIG_SYS_MEMTEST_END			0x00800000
-
-/* timer clock - 2* OSC_IN system clock */
-#define CONFIG_IXP425_TIMER_CLK                 66666666
-#define CONFIG_SYS_HZ				1000
-
-/* default load address */
-#define CONFIG_SYS_LOAD_ADDR			0x00010000
-
-/* valid baudrates */
-#define CONFIG_SYS_BAUDRATE_TABLE		{ 9600, 19200, 38400, 57600, \
-					  115200, 230400 }
-#define CONFIG_SERIAL_RTS_ACTIVE	1
-
-/* Expansion bus settings */
-#define CONFIG_SYS_EXP_CS0			0xbd113042
-
-/* SDRAM settings */
-#define CONFIG_NR_DRAM_BANKS		1
-#define PHYS_SDRAM_1			0x00000000
-#define CONFIG_SYS_SDRAM_BASE			0x00000000
-
-/* 16MB SDRAM */
-#define CONFIG_SYS_SDR_CONFIG			0x3A
-#define PHYS_SDRAM_1_SIZE		0x01000000
-#define CONFIG_SYS_SDRAM_REFRESH_CNT		0x81a
-#define CONFIG_SYS_SDR_MODE_CONFIG		0x1
-#define CONFIG_SYS_DRAM_SIZE			0x01000000
-
-/* FLASH organization */
-#define CONFIG_SYS_TEXT_BASE		0x50000000
-#define CONFIG_SYS_MAX_FLASH_BANKS		1
-/* max number of sectors on one chip */
-#define CONFIG_SYS_MAX_FLASH_SECT		140
-#define PHYS_FLASH_1			0x50000000
-#define CONFIG_SYS_FLASH_BANKS_LIST		{ PHYS_FLASH_1 }
-
-#define CONFIG_SYS_FLASH_BASE			PHYS_FLASH_1
-#define CONFIG_SYS_MONITOR_BASE		PHYS_FLASH_1
-#define CONFIG_SYS_MONITOR_LEN			(256 << 10)
-#define CONFIG_BOARD_SIZE_LIMIT			262144
-
-/* Use common CFI driver */
-#define CONFIG_SYS_FLASH_CFI
-#define CONFIG_FLASH_CFI_DRIVER
-/* no byte writes on IXP4xx */
-#define CONFIG_SYS_FLASH_CFI_WIDTH		FLASH_CFI_16BIT
-
-/* print 'E' for empty sector on flinfo */
-#define CONFIG_SYS_FLASH_EMPTY_INFO
-
-/* Ethernet */
-
-/* include IXP4xx NPE support */
-#define CONFIG_IXP4XX_NPE		1
-/* NPE0 PHY address */
-#define	CONFIG_PHY_ADDR			0x00
-/* MII PHY management */
-#define CONFIG_MII			1
-/* fixed-speed switch without standard PHY registers on MII */
-#define CONFIG_MII_NPE0_FIXEDLINK       1
-#define CONFIG_MII_NPE0_SPEED           100
-#define CONFIG_MII_NPE0_FULLDUPLEX      1
-
-/* Number of ethernet rx buffers & descriptors */
-#define CONFIG_SYS_RX_ETH_BUFFER		16
-#define CONFIG_RESET_PHY_R		1
-/* ethernet switch connected to MII port */
-#define CONFIG_MII_ETHSWITCH		1
-
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_NET
-#define CONFIG_CMD_MII
-#define CONFIG_CMD_PING
-#undef  CONFIG_CMD_NFS
-
-/* BOOTP options */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-/* Cache Configuration */
-#define CONFIG_SYS_CACHELINE_SIZE		32
-
-/*
- * environment organization:
- * one flash sector, embedded in uboot area (bottom bootblock flash)
- */
-#define	CONFIG_ENV_IS_IN_FLASH		1
-#define CONFIG_ENV_SIZE			0x2000
-#define CONFIG_ENV_ADDR			(PHYS_FLASH_1 + 0x4000)
-#define CONFIG_SYS_USE_PPCENV			1
-
-#define CONFIG_EXTRA_ENV_SETTINGS					\
-	"npe_ucode=50040000\0"						\
-	"mtd=IXP4XX-Flash.0:256k(uboot),64k(ucode),1152k(linux),-(root)\0" \
-	"kerneladdr=50050000\0"						\
-	"kernelfile=actux2/uImage\0"					\
-	"rootfile=actux2/rootfs\0"					\
-	"rootaddr=50170000\0"						\
-	"loadaddr=10000\0"						\
-	"updateboot_ser=mw.b 10000 ff 40000;"				\
-	" loady ${loadaddr};"						\
-	" run eraseboot writeboot\0"					\
-	"updateboot_net=mw.b 10000 ff 40000;"				\
-	" tftp ${loadaddr} actux2/u-boot.bin;"				\
-	" run eraseboot writeboot\0"					\
-	"eraseboot=protect off 50000000 50003fff;"			\
-	" protect off 50006000 5003ffff;"				\
-	" erase 50000000 50003fff;"					\
-	" erase 50006000 5003ffff\0"					\
-	"writeboot=cp.b 10000 50000000 4000;"				\
-	" cp.b 16000 50006000 3a000\0"					\
-	"updateucode=loady;"						\
-	" era ${npe_ucode} +${filesize};"				\
-	" cp.b ${loadaddr} ${npe_ucode} ${filesize}\0"			\
-	"updateroot=tftp ${loadaddr} ${rootfile};"			\
-	" era ${rootaddr} +${filesize};"				\
-	" cp.b ${loadaddr} ${rootaddr} ${filesize}\0"			\
-	"updatekern=tftp ${loadaddr} ${kernelfile};"			\
-	" era ${kerneladdr} +${filesize};"				\
-	" cp.b ${loadaddr} ${kerneladdr} ${filesize}\0"			\
-	"flashargs=setenv bootargs mtdparts=${mtd} root=/dev/mtdblock3"	\
-	" rootfstype=squashfs,jffs2 init=/etc/preinit\0"		\
-	"netargs=setenv bootargs mtdparts=${mtd} root=/dev/mtdblock3"	\
-	" rootfstype=squashfs,jffs2 init=/etc/preinit\0"		\
-	"addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0" \
-	"addeth=setenv bootargs ${bootargs} ethaddr=${ethaddr}\0"	\
-	"boot_flash=run flashargs addtty addeth;"			\
-	" bootm ${kerneladdr}\0"					\
-	"boot_net=run netargs addtty addeth;"				\
-	" tftpboot ${loadaddr} ${kernelfile};"				\
-	" bootm\0"
-
-/* additions for new relocation code, must be added to all boards */
-#define CONFIG_SYS_INIT_SP_ADDR						\
-	(CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE)
-
-#endif /* __CONFIG_H */
diff --git a/include/configs/actux3.h b/include/configs/actux3.h
deleted file mode 100644
index 76b5efd8a1..0000000000
--- a/include/configs/actux3.h
+++ /dev/null
@@ -1,209 +0,0 @@
-/*
- * (C) Copyright 2007
- * Michael Schwingen, michael@schwingen.org
- *
- * Configuration settings for the AcTux-3 board.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#define CONFIG_IXP425			1
-#define CONFIG_ACTUX3			1
-
-#define	CONFIG_MACH_TYPE		1481
-
-#define CONFIG_DISPLAY_CPUINFO		1
-#define CONFIG_DISPLAY_BOARDINFO	1
-
-#define CONFIG_IXP_SERIAL
-#define CONFIG_SYS_IXP425_CONSOLE		IXP425_UART2
-#define CONFIG_BAUDRATE			115200
-#define CONFIG_BOOTDELAY		3
-#define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */
-#define CONFIG_BOARD_EARLY_INIT_F	1
-#define CONFIG_SYS_LDSCRIPT	"board/actux3/u-boot.lds"
-
-/***************************************************************
- * U-boot generic defines start here.
- ***************************************************************/
-/* Size of malloc() pool */
-#define CONFIG_SYS_MALLOC_LEN			(CONFIG_ENV_SIZE + 128*1024)
-
-/* allow to overwrite serial and ethaddr */
-#define CONFIG_ENV_OVERWRITE
-
-/* Command line configuration. */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_ELF
-
-#define CONFIG_BOOTCOMMAND		"run boot_flash"
-/* enable passing of ATAGs */
-#define CONFIG_CMDLINE_TAG		1
-#define CONFIG_SETUP_MEMORY_TAGS	1
-#define CONFIG_INITRD_TAG		1
-#define CONFIG_REVISION_TAG		1
-
-#if defined(CONFIG_CMD_KGDB)
-# define CONFIG_KGDB_BAUDRATE		230400
-/* which serial port to use */
-# define CONFIG_KGDB_SER_INDEX		1
-#endif
-
-/* Miscellaneous configurable options */
-#define CONFIG_SYS_LONGHELP
-#define CONFIG_SYS_PROMPT			"=> "
-/* Console I/O Buffer Size */
-#define CONFIG_SYS_CBSIZE			256
-/* Print Buffer Size */
-#define CONFIG_SYS_PBSIZE			(CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
-/* max number of command args */
-#define CONFIG_SYS_MAXARGS			16
-/* Boot Argument Buffer Size */
-#define CONFIG_SYS_BARGSIZE			CONFIG_SYS_CBSIZE
-
-#define CONFIG_SYS_MEMTEST_START		0x00400000
-#define CONFIG_SYS_MEMTEST_END			0x00800000
-
-/* timer clock - 2* OSC_IN system clock */
-#define CONFIG_IXP425_TIMER_CLK                 66666666
-#define CONFIG_SYS_HZ				1000
-
-/* default load address */
-#define CONFIG_SYS_LOAD_ADDR			0x00010000
-
-/* valid baudrates */
-#define CONFIG_SYS_BAUDRATE_TABLE		{ 9600, 19200, 38400, 57600, \
-					  115200, 230400 }
-#define CONFIG_SERIAL_RTS_ACTIVE	1
-
-/* Expansion bus settings */
-#define CONFIG_SYS_EXP_CS0			0xbd113442
-
-/* SDRAM settings */
-#define CONFIG_NR_DRAM_BANKS		1
-#define PHYS_SDRAM_1			0x00000000
-#define CONFIG_SYS_SDRAM_BASE			0x00000000
-
-/* 16MB SDRAM */
-#define CONFIG_SYS_SDR_CONFIG			0x3A
-#define PHYS_SDRAM_1_SIZE		0x01000000
-#define CONFIG_SYS_SDRAM_REFRESH_CNT		0x81a
-#define CONFIG_SYS_SDR_MODE_CONFIG		0x1
-#define CONFIG_SYS_DRAM_SIZE			0x01000000
-
-/* FLASH organization */
-#define CONFIG_SYS_TEXT_BASE		0x50000000
-#define CONFIG_SYS_MAX_FLASH_BANKS		1
-/* max number of sectors on one chip */
-#define CONFIG_SYS_MAX_FLASH_SECT		140
-#define PHYS_FLASH_1			0x50000000
-#define CONFIG_SYS_FLASH_BANKS_LIST		{ PHYS_FLASH_1 }
-
-#define CONFIG_SYS_FLASH_BASE			PHYS_FLASH_1
-#define CONFIG_SYS_MONITOR_BASE		PHYS_FLASH_1
-#define CONFIG_SYS_MONITOR_LEN			(256 << 10)
-#define CONFIG_BOARD_SIZE_LIMIT			262144
-
-/* Use common CFI driver */
-#define CONFIG_SYS_FLASH_CFI
-#define CONFIG_FLASH_CFI_DRIVER
-/* no byte writes on IXP4xx */
-#define CONFIG_SYS_FLASH_CFI_WIDTH		FLASH_CFI_16BIT
-
-/* print 'E' for empty sector on flinfo */
-#define CONFIG_SYS_FLASH_EMPTY_INFO
-
-/* Ethernet */
-
-/* include IXP4xx NPE support */
-#define CONFIG_IXP4XX_NPE		1
-
-/* NPE0 PHY address */
-#define	CONFIG_PHY_ADDR			0x10
-/* MII PHY management */
-#define CONFIG_MII			1
-/* fixed-speed switch without standard PHY registers on MII */
-#define CONFIG_MII_NPE0_FIXEDLINK       1
-#define CONFIG_MII_NPE0_SPEED           100
-#define CONFIG_MII_NPE0_FULLDUPLEX      1
-
-/* Number of ethernet rx buffers & descriptors */
-#define CONFIG_SYS_RX_ETH_BUFFER		16
-#define CONFIG_RESET_PHY_R		1
-/* ethernet switch connected to MII port */
-#define CONFIG_MII_ETHSWITCH		1
-
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_NET
-#define CONFIG_CMD_MII
-#define CONFIG_CMD_PING
-#undef  CONFIG_CMD_NFS
-
-/* BOOTP options */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-/* Cache Configuration */
-#define CONFIG_SYS_CACHELINE_SIZE		32
-
-/*
- * environment organization:
- * one flash sector, embedded in uboot area (bottom bootblock flash)
- */
-#define	CONFIG_ENV_IS_IN_FLASH		1
-#define CONFIG_ENV_SIZE			0x2000
-#define CONFIG_ENV_ADDR			(PHYS_FLASH_1 + 0x4000)
-#define CONFIG_SYS_USE_PPCENV			1
-
-#define CONFIG_EXTRA_ENV_SETTINGS					\
-	"npe_ucode=50040000\0"						\
-	"mtd=IXP4XX-Flash.0:256k(uboot),64k(ucode),1152k(linux),-(root)\0" \
-	"kerneladdr=50050000\0"						\
-	"kernelfile=actux3/uImage\0"					\
-	"rootfile=actux3/rootfs\0"					\
-	"rootaddr=50170000\0"						\
-	"loadaddr=10000\0"						\
-	"updateboot_ser=mw.b 10000 ff 40000;"				\
-	" loady ${loadaddr};"						\
-	" run eraseboot writeboot\0"					\
-	"updateboot_net=mw.b 10000 ff 40000;"				\
-	" tftp ${loadaddr} actux3/u-boot.bin;"				\
-	" run eraseboot writeboot\0"					\
-	"eraseboot=protect off 50000000 50003fff;"			\
-	" protect off 50006000 5003ffff;"				\
-	" erase 50000000 50003fff;"					\
-	" erase 50006000 5003ffff\0"					\
-	"writeboot=cp.b 10000 50000000 4000;"				\
-	" cp.b 16000 50006000 3a000\0"					\
-	"updateucode=loady;"						\
-	" era ${npe_ucode} +${filesize};"				\
-	" cp.b ${loadaddr} ${npe_ucode} ${filesize}\0"			\
-	"updateroot=tftp ${loadaddr} ${rootfile};"			\
-	" era ${rootaddr} +${filesize};"				\
-	" cp.b ${loadaddr} ${rootaddr} ${filesize}\0"			\
-	"updatekern=tftp ${loadaddr} ${kernelfile};"			\
-	" era ${kerneladdr} +${filesize};"				\
-	" cp.b ${loadaddr} ${kerneladdr} ${filesize}\0"			\
-	"flashargs=setenv bootargs mtdparts=${mtd} root=/dev/mtdblock3"	\
-	" rootfstype=squashfs,jffs2 init=/etc/preinit\0"		\
-	"netargs=setenv bootargs mtdparts=${mtd} root=/dev/mtdblock3"	\
-	" rootfstype=squashfs,jffs2 init=/etc/preinit\0"		\
-	"addtty=setenv bootargs ${bootargs} console=ttyS1,${baudrate}\0" \
-	"addeth=setenv bootargs ${bootargs} ethaddr=${ethaddr}\0"	\
-	"boot_flash=run flashargs addtty addeth;"			\
-	" bootm ${kerneladdr}\0"					\
-	"boot_net=run netargs addtty addeth;"				\
-	" tftpboot ${loadaddr} ${kernelfile};"				\
-	" bootm\0"
-
-/* additions for new relocation code, must be added to all boards */
-#define CONFIG_SYS_INIT_SP_ADDR						\
-	(CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE)
-
-#endif /* __CONFIG_H */
diff --git a/include/configs/actux4.h b/include/configs/actux4.h
deleted file mode 100644
index 1df0a7caab..0000000000
--- a/include/configs/actux4.h
+++ /dev/null
@@ -1,208 +0,0 @@
-/*
- * (C) Copyright 2007
- * Michael Schwingen, michael@schwingen.org
- *
- * Configuration settings for the AcTux-4 board.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#define CONFIG_IXP425			1
-#define CONFIG_ACTUX4			1
-
-#define	CONFIG_MACH_TYPE		1532
-
-#define CONFIG_DISPLAY_CPUINFO		1
-#define CONFIG_DISPLAY_BOARDINFO	1
-
-#define CONFIG_IXP_SERIAL
-#define CONFIG_SYS_IXP425_CONSOLE		IXP425_UART1
-#define CONFIG_BAUDRATE			115200
-#define CONFIG_BOOTDELAY		3
-#define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */
-#define CONFIG_BOARD_EARLY_INIT_F	1
-
-/***************************************************************
- * U-boot generic defines start here.
- ***************************************************************/
-/* Size of malloc() pool */
-#define CONFIG_SYS_MALLOC_LEN			(CONFIG_ENV_SIZE + 128*1024)
-
-/* allow to overwrite serial and ethaddr */
-#define CONFIG_ENV_OVERWRITE
-
-/* Command line configuration */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_ELF
-
-#define CONFIG_PCI
-#ifdef CONFIG_PCI
-#define CONFIG_CMD_PCI
-#define CONFIG_PCI_PNP
-#define CONFIG_IXP_PCI
-#define CONFIG_PCI_SCAN_SHOW
-#define CONFIG_CMD_PCI_ENUM
-#endif
-
-#define CONFIG_BOOTCOMMAND		"run boot_flash"
-/* enable passing of ATAGs */
-#define CONFIG_CMDLINE_TAG		1
-#define CONFIG_SETUP_MEMORY_TAGS	1
-#define CONFIG_INITRD_TAG		1
-
-#if defined(CONFIG_CMD_KGDB)
-# define CONFIG_KGDB_BAUDRATE		230400
-/* which serial port to use */
-# define CONFIG_KGDB_SER_INDEX		1
-#endif
-
-/* Miscellaneous configurable options */
-#define CONFIG_SYS_LONGHELP
-#define CONFIG_SYS_PROMPT			"=> "
-/* Console I/O Buffer Size */
-#define CONFIG_SYS_CBSIZE			256
-/* Print Buffer Size */
-#define CONFIG_SYS_PBSIZE			(CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
-/* max number of command args */
-#define CONFIG_SYS_MAXARGS			16
-/* Boot Argument Buffer Size */
-#define CONFIG_SYS_BARGSIZE			CONFIG_SYS_CBSIZE
-
-#define CONFIG_SYS_MEMTEST_START		0x00400000
-#define CONFIG_SYS_MEMTEST_END			0x00800000
-
-/* timer clock - 2* OSC_IN system clock */
-#define CONFIG_IXP425_TIMER_CLK                 66000000
-#define CONFIG_SYS_HZ				1000
-
-/* default load address */
-#define CONFIG_SYS_LOAD_ADDR			0x00010000
-
-/* valid baudrates */
-#define CONFIG_SYS_BAUDRATE_TABLE		{ 9600, 19200, 38400, 57600, \
-					  115200, 230400 }
-#define CONFIG_SERIAL_RTS_ACTIVE	1
-
-/* Expansion bus settings */
-#define CONFIG_SYS_EXP_CS0			0xbd113003
-
-/* SDRAM settings */
-#define CONFIG_NR_DRAM_BANKS		1
-#define PHYS_SDRAM_1			0x00000000
-#define CONFIG_SYS_SDRAM_BASE			0x00000000
-
-/* 32MB SDRAM */
-#define CONFIG_SYS_SDR_CONFIG			0x18
-#define PHYS_SDRAM_1_SIZE		0x02000000
-#define CONFIG_SYS_SDRAM_REFRESH_CNT		0x81a
-#define CONFIG_SYS_SDR_MODE_CONFIG		0x1
-#define CONFIG_SYS_DRAM_SIZE			0x02000000
-
-/* FLASH organization */
-#define CONFIG_SYS_TEXT_BASE		0x50000000
-#define CONFIG_SYS_MAX_FLASH_BANKS		2
-/* max # of sectors per chip */
-#define CONFIG_SYS_MAX_FLASH_SECT		70
-#define PHYS_FLASH_1			0x50000000
-#define PHYS_FLASH_2			0x51000000
-#define CONFIG_SYS_FLASH_BANKS_LIST		{ PHYS_FLASH_1, PHYS_FLASH_2 }
-
-#define CONFIG_SYS_FLASH_BASE			PHYS_FLASH_1
-#define CONFIG_SYS_MONITOR_BASE		PHYS_FLASH_1
-#define CONFIG_SYS_MONITOR_LEN			(252 << 10)
-#define CONFIG_BOARD_SIZE_LIMIT			258048
-
-/* Use common CFI driver */
-#define CONFIG_SYS_FLASH_CFI
-#define CONFIG_FLASH_CFI_DRIVER
-/* board provides its own flash_init code */
-#define CONFIG_FLASH_CFI_LEGACY		1
-/* no byte writes on IXP4xx */
-#define CONFIG_SYS_FLASH_CFI_WIDTH		FLASH_CFI_16BIT
-/* SST 39VF020 etc. support */
-#define CONFIG_SYS_FLASH_LEGACY_256Kx8	1
-
-/* print 'E' for empty sector on flinfo */
-#define CONFIG_SYS_FLASH_EMPTY_INFO
-
-/* Ethernet */
-
-/* include IXP4xx NPE support */
-#define CONFIG_IXP4XX_NPE		1
-
-/* NPE0 PHY address */
-#define	CONFIG_PHY_ADDR			0x1C
-/* MII PHY management */
-#define CONFIG_MII			1
-
-/* Number of ethernet rx buffers & descriptors */
-#define CONFIG_SYS_RX_ETH_BUFFER		16
-
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_NET
-#define CONFIG_CMD_MII
-#define CONFIG_CMD_PING
-#undef  CONFIG_CMD_NFS
-
-/* BOOTP options */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-/* Cache Configuration */
-#define CONFIG_SYS_CACHELINE_SIZE		32
-
-/* environment organization: one complete 4k flash sector */
-#define	CONFIG_ENV_IS_IN_FLASH		1
-#define CONFIG_ENV_SIZE			0x1000
-#define CONFIG_ENV_ADDR			(PHYS_FLASH_1 + 0x3f000)
-
-#define CONFIG_EXTRA_ENV_SETTINGS					\
-	"npe_ucode=51000000\0"						\
-	"mtd=IXP4XX-Flash.0:252k(uboot),4k(uboot_env);"			\
-	"IXP4XX-Flash.1:128k(ucode),1280k(linux),-(root)\0"		\
-	"kerneladdr=51020000\0"						\
-	"kernelfile=actux4/uImage\0"					\
-	"rootfile=actux4/rootfs\0"					\
-	"rootaddr=51160000\0"						\
-	"loadaddr=10000\0"						\
-	"updateboot_ser=mw.b 10000 ff 40000;"				\
-	" loady ${loadaddr};"						\
-	" run eraseboot writeboot\0"					\
-	"updateboot_net=mw.b 10000 ff 40000;"				\
-	" tftp ${loadaddr} actux4/u-boot.bin;"					\
-	" run eraseboot writeboot\0"					\
-	"eraseboot=protect off 50000000 5003efff;"			\
-	" erase 50000000 +${filesize}\0"				\
-	"writeboot=cp.b 10000 50000000 ${filesize}\0"			\
-	"updateucode=loady;"						\
-	" era ${npe_ucode} +${filesize};"				\
-	" cp.b ${loadaddr} ${npe_ucode} ${filesize}\0"			\
-	"updateroot=tftp ${loadaddr} ${rootfile};"			\
-	" era ${rootaddr} +${filesize};"				\
-	" cp.b ${loadaddr} ${rootaddr} ${filesize}\0"			\
-	"updatekern=tftp ${loadaddr} ${kernelfile};"			\
-	" era ${kerneladdr} +${filesize};"				\
-	" cp.b ${loadaddr} ${kerneladdr} ${filesize}\0"			\
-	"flashargs=setenv bootargs mtdparts=${mtd} root=/dev/mtdblock4"	\
-	" rootfstype=squashfs,jffs2 init=/etc/preinit\0"		\
-	"netargs=setenv bootargs mtdparts=${mtd} root=/dev/mtdblock4"	\
-	" rootfstype=squashfs,jffs2 init=/etc/preinit\0"		\
-	"addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0" \
-	"addeth=setenv bootargs ${bootargs} ethaddr=${ethaddr}\0"	\
-	"boot_flash=run flashargs addtty addeth;"			\
-	" bootm ${kerneladdr}\0"					\
-	"boot_net=run netargs addtty addeth;"				\
-	" tftpboot ${loadaddr} ${kernelfile};"				\
-	" bootm\0"
-
-/* additions for new relocation code, must be added to all boards */
-#define CONFIG_SYS_INIT_SP_ADDR						\
-	(CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE)
-
-#endif /* __CONFIG_H */
diff --git a/include/configs/adp-ag101.h b/include/configs/adp-ag101.h
index 81f71b9b72..e318c7543f 100644
--- a/include/configs/adp-ag101.h
+++ b/include/configs/adp-ag101.h
@@ -40,12 +40,6 @@
 /*
  * Timer
  */
-
-/*
- * According to the discussion in u-boot mailing list before,
- * CONFIG_SYS_HZ at 1000 is mandatory.
- */
-#define CONFIG_SYS_HZ		1000
 #define CONFIG_SYS_CLK_FREQ	48000000
 #define VERSION_CLOCK		CONFIG_SYS_CLK_FREQ
 
@@ -145,11 +139,6 @@
 #define CONFIG_SYS_MALLOC_LEN		(512 << 10)
 
 /*
- * size in bytes reserved for initial data
- */
-#define CONFIG_SYS_GBL_DATA_SIZE	128
-
-/*
  * AHB Controller configuration
  */
 #define CONFIG_FTAHBC020S
diff --git a/include/configs/adp-ag101p.h b/include/configs/adp-ag101p.h
index 48afbf4467..24904b0b7c 100644
--- a/include/configs/adp-ag101p.h
+++ b/include/configs/adp-ag101p.h
@@ -40,12 +40,6 @@
 /*
  * Timer
  */
-
-/*
- * According to the discussion in u-boot mailing list before,
- * CONFIG_SYS_HZ at 1000 is mandatory.
- */
-#define CONFIG_SYS_HZ		1000
 #define CONFIG_SYS_CLK_FREQ	39062500
 #define VERSION_CLOCK		CONFIG_SYS_CLK_FREQ
 
@@ -145,11 +139,6 @@
 #define CONFIG_SYS_MALLOC_LEN		(512 << 10)
 
 /*
- * size in bytes reserved for initial data
- */
-#define CONFIG_SYS_GBL_DATA_SIZE	128
-
-/*
  * AHB Controller configuration
  */
 #define CONFIG_FTAHBC020S
diff --git a/include/configs/adp-ag102.h b/include/configs/adp-ag102.h
index 681dfa251c..39f7a3cd46 100644
--- a/include/configs/adp-ag102.h
+++ b/include/configs/adp-ag102.h
@@ -32,12 +32,6 @@
 /*
  * Timer
  */
-
-/*
- * According to the discussion in u-boot mailing list before,
- * CONFIG_SYS_HZ at 1000 is mandatory.
- */
-#define CONFIG_SYS_HZ		1000
 #define CONFIG_SYS_CLK_FREQ	(66000000 * 2)
 #define VERSION_CLOCK		CONFIG_SYS_CLK_FREQ
 
@@ -210,11 +204,6 @@
 #define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 128 * 1024)
 
 /*
- * size in bytes reserved for initial data
-*/
-#define CONFIG_SYS_GBL_DATA_SIZE	128
-
-/*
  * AHB Controller configuration
  */
 #define CONFIG_FTAHBC020S
diff --git a/include/configs/aev.h b/include/configs/aev.h
index 33d7815e98..2dffcfbed3 100644
--- a/include/configs/aev.h
+++ b/include/configs/aev.h
@@ -16,8 +16,7 @@
  * (easy to change)
  */
 
-#define CONFIG_MPC5xxx		1	/* This is an MPC5xxx CPU */
-#define CONFIG_MPC5200		1	/* (more precisely an MPC5200 CPU) */
+#define CONFIG_MPC5200		1	/* This is an MPC5200 CPU */
 #define CONFIG_TQM5200		1	/* ... on TQM5200 module */
 #undef CONFIG_TQM5200_REV100		/*  define for revision 100 modules */
 #define CONFIG_STK52XX		1	/* ... on a STK52XX base board */
@@ -320,7 +319,6 @@
  * Miscellaneous configurable options
  */
 #define CONFIG_SYS_LONGHELP			/* undef to save memory	    */
-#define CONFIG_SYS_PROMPT		"=> "	/* Monitor Command Prompt   */
 #if defined(CONFIG_CMD_KGDB)
 #define CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size  */
 #else
@@ -338,8 +336,6 @@
 
 #define CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address */
 
-#define CONFIG_SYS_HZ			1000	/* decrementer freq: 1 ms ticks */
-
 #define CONFIG_SYS_CACHELINE_SIZE	32	/* For MPC5xxx CPUs */
 #if defined(CONFIG_CMD_KGDB)
 #  define CONFIG_SYS_CACHELINE_SHIFT	5	/* log base 2 of the above value */
diff --git a/include/configs/afeb9260.h b/include/configs/afeb9260.h
index be2f207055..14bac155a3 100644
--- a/include/configs/afeb9260.h
+++ b/include/configs/afeb9260.h
@@ -17,7 +17,6 @@
 /* ARM asynchronous clock */
 #define CONFIG_SYS_AT91_MAIN_CLOCK		18429952	/* from 18.432 MHz crystal */
 #define CONFIG_SYS_AT91_SLOW_CLOCK		32768
-#define CONFIG_SYS_HZ				1000
 
 #define CONFIG_BOARD_EARLY_INIT_F
 #define CONFIG_DISPLAY_CPUINFO
@@ -107,11 +106,12 @@
 /* Ethernet */
 #define CONFIG_MACB
 #define CONFIG_RESET_PHY_R
-
+#define CONFIG_AT91_WANTS_COMMON_PHY
 #define CONFIG_NET_RETRY_COUNT		20
 
 /* USB */
 #define CONFIG_USB_ATMEL
+#define CONFIG_USB_ATMEL_CLK_SEL_PLLB
 #define CONFIG_USB_OHCI_NEW
 #define CONFIG_DOS_PARTITION
 #define CONFIG_SYS_USB_OHCI_CPU_INIT
diff --git a/include/configs/alpr.h b/include/configs/alpr.h
index f0a89623c3..7849b222b0 100644
--- a/include/configs/alpr.h
+++ b/include/configs/alpr.h
@@ -14,7 +14,6 @@
 #define CONFIG_ALPR		1	    /* Board is ebony		*/
 #define CONFIG_440GX		1	    /* Specifc GX support	*/
 #define CONFIG_440		1	    /* ... PPC440 family	*/
-#define CONFIG_4xx		1	    /* ... PPC4xx family	*/
 #define CONFIG_BOARD_EARLY_INIT_F 1	    /* Call board_pre_init	*/
 #define CONFIG_LAST_STAGE_INIT	1	    /* call last_stage_init()	*/
 
@@ -238,7 +237,6 @@
  * Miscellaneous configurable options
  */
 #define CONFIG_SYS_LONGHELP			/* undef to save memory		*/
-#define CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt	*/
 #if defined(CONFIG_CMD_KGDB)
 #define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
 #else
@@ -255,8 +253,6 @@
 #define CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address */
 #define CONFIG_SYS_EXTBDINFO		1	/* To use extended board_into (bd_t) */
 
-#define CONFIG_SYS_HZ			1000	/* decrementer freq: 1 ms ticks */
-
 #define CONFIG_CMDLINE_EDITING	1	/* add command line history	*/
 #define CONFIG_LOOPW            1       /* enable loopw command         */
 #define CONFIG_MX_CYCLIC	1       /* enable mdc/mwc commands      */
@@ -327,6 +323,8 @@
 #define CONFIG_SYS_NAND_BASE_LIST	{ CONFIG_SYS_NAND_BASE + 0, CONFIG_SYS_NAND_BASE + 2,	\
 				  CONFIG_SYS_NAND_BASE + 4, CONFIG_SYS_NAND_BASE + 6 }
 #define CONFIG_SYS_NAND_QUIET_TEST	1	/* don't warn upon unknown NAND flash	*/
+#define CONFIG_SYS_NAND_MAX_OOBFREE	2
+#define CONFIG_SYS_NAND_MAX_ECCPOS	56
 
 /*-----------------------------------------------------------------------
  * External Bus Controller (EBC) Setup
@@ -350,7 +348,6 @@
 
 #if defined(CONFIG_CMD_KGDB)
 #define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
-#define CONFIG_KGDB_SER_INDEX	2	/* which serial port to use */
 #endif
 
 /* pass open firmware flat tree */
diff --git a/include/configs/am335x_evm.h b/include/configs/am335x_evm.h
index c2ba7e35d8..ea9e758a69 100644
--- a/include/configs/am335x_evm.h
+++ b/include/configs/am335x_evm.h
@@ -20,6 +20,7 @@
 
 #define MACH_TYPE_TIAM335EVM		3589	/* Until the next sync */
 #define CONFIG_MACH_TYPE		MACH_TYPE_TIAM335EVM
+#define CONFIG_BOARD_LATE_INIT
 
 /* Clock Defines */
 #define V_OSCK				24000000  /* Clock output from T2 */
@@ -31,6 +32,12 @@
 /* Always 128 KiB env size */
 #define CONFIG_ENV_SIZE			(128 << 10)
 
+/* Enhance our eMMC support / experience. */
+#define CONFIG_CMD_GPT
+#define CONFIG_EFI_PARTITION
+#define CONFIG_PARTITION_UUIDS
+#define CONFIG_CMD_PART
+
 #ifdef CONFIG_NAND
 #define NANDARGS \
 	"mtdids=" MTDIDS_DEFAULT "\0" \
@@ -39,15 +46,13 @@
 		"${optargs} " \
 		"root=${nandroot} " \
 		"rootfstype=${nandrootfstype}\0" \
-	"dfu_alt_info_nand=" DFU_ALT_INFO_NAND "\0" \
 	"nandroot=ubi0:rootfs rw ubi.mtd=7,2048\0" \
 	"nandrootfstype=ubifs rootwait=1\0" \
-	"nandsrcaddr=0x280000\0" \
-		"nandboot=echo Booting from nand ...; " \
+	"nandboot=echo Booting from nand ...; " \
 		"run nandargs; " \
-		"nand read ${loadaddr} ${nandsrcaddr} ${nandimgsize}; " \
-		"bootz ${loadaddr}\0" \
-	"nandimgsize=0x500000\0"
+		"nand read ${fdtaddr} u-boot-spl-os; " \
+		"nand read ${loadaddr} kernel; " \
+		"bootz ${loadaddr} - ${fdtaddr}\0"
 #else
 #define NANDARGS ""
 #endif
@@ -66,9 +71,10 @@
 	"bootfile=zImage\0" \
 	"fdtfile=undefined\0" \
 	"console=ttyO0,115200n8\0" \
+	"partitions=" \
+		"uuid_disk=${uuid_gpt_disk};" \
+		"name=rootfs,start=2MiB,size=-,uuid=${uuid_gpt_rootfs}\0" \
 	"optargs=\0" \
-	"dfu_alt_info_mmc=" DFU_ALT_INFO_MMC "\0" \
-	"dfu_alt_info_emmc=rawemmc mmc 0 3751936\0" \
 	"mmcdev=0\0" \
 	"mmcroot=/dev/mmcblk0p2 ro\0" \
 	"mmcrootfstype=ext4 rootwait\0" \
@@ -100,7 +106,6 @@
 	"loadbootenv=load mmc ${mmcdev} ${loadaddr} ${bootenv}\0" \
 	"importbootenv=echo Importing environment from mmc ...; " \
 		"env import -t $loadaddr $filesize\0" \
-	"dfu_alt_info_ram=" DFU_ALT_INFO_RAM "\0" \
 	"ramargs=setenv bootargs console=${console} " \
 		"${optargs} " \
 		"root=${ramroot} " \
@@ -163,7 +168,8 @@
 			"setenv fdtfile am335x-evmsk.dtb; fi; " \
 		"if test $fdtfile = undefined; then " \
 			"echo WARNING: Could not determine device tree to use; fi; \0" \
-	NANDARGS
+	NANDARGS \
+	DFUARGS
 #endif
 
 #define CONFIG_BOOTCOMMAND \
@@ -183,7 +189,6 @@
 #define CONFIG_SYS_NS16550_COM6		0x481aa000	/* UART5 */
 #define CONFIG_BAUDRATE			115200
 
-/* I2C Configuration */
 #define CONFIG_CMD_EEPROM
 #define CONFIG_ENV_EEPROM_IS_ON_I2C
 #define CONFIG_SYS_I2C_EEPROM_ADDR	0x50	/* Main EEPROM */
@@ -199,8 +204,9 @@
 #define CONFIG_SPL_POWER_SUPPORT
 #define CONFIG_SPL_YMODEM_SUPPORT
 
-/* CPSW support */
-#define CONFIG_SPL_ETH_SUPPORT
+/* Bootcount using the RTC block */
+#define CONFIG_BOOTCOUNT_LIMIT
+#define CONFIG_BOOTCOUNT_AM33XX
 
 /* USB gadget RNDIS */
 #define CONFIG_SPL_MUSB_NEW_SUPPORT
@@ -221,6 +227,8 @@
 #define CONFIG_SPL_LDSCRIPT		"$(CPUDIR)/am33xx/u-boot-spl.lds"
 
 #ifdef CONFIG_NAND
+#define CONFIG_NAND_OMAP_GPMC
+#define CONFIG_NAND_OMAP_ELM
 #define CONFIG_SYS_NAND_5_ADDR_CYCLE
 #define CONFIG_SYS_NAND_PAGE_COUNT	(CONFIG_SYS_NAND_BLOCK_SIZE / \
 					 CONFIG_SYS_NAND_PAGE_SIZE)
@@ -238,7 +246,8 @@
 
 #define CONFIG_SYS_NAND_ECCSIZE		512
 #define CONFIG_SYS_NAND_ECCBYTES	14
-
+#define CONFIG_SYS_NAND_ONFI_DETECTION
+#define CONFIG_NAND_OMAP_ECCSCHEME	OMAP_ECC_BCH8_CODE_HW
 #define CONFIG_SYS_NAND_U_BOOT_START	CONFIG_SYS_TEXT_BASE
 #define CONFIG_SYS_NAND_U_BOOT_OFFS	0x80000
 #endif
@@ -293,6 +302,9 @@
 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_USBETH_SUPPORT)
 /* disable host part of MUSB in SPL */
 #undef CONFIG_MUSB_HOST
+/* disable EFI partitions and partition UUID support */
+#undef CONFIG_PARTITION_UUIDS
+#undef CONFIG_EFI_PARTITION
 /*
  * Disable CPSW SPL support so we fit within the 101KiB limit.
  */
@@ -304,6 +316,7 @@
 #define CONFIG_DFU_MMC
 #define CONFIG_CMD_DFU
 #define DFU_ALT_INFO_MMC \
+	"dfu_alt_info_mmc=" \
 	"boot part 0 1;" \
 	"rootfs part 0 2;" \
 	"MLO fat 0 1;" \
@@ -314,10 +327,11 @@
 	"spl-os-args fat 0 1;" \
 	"spl-os-image fat 0 1;" \
 	"u-boot.img fat 0 1;" \
-	"uEnv.txt fat 0 1"
+	"uEnv.txt fat 0 1\0"
 #ifdef CONFIG_NAND
 #define CONFIG_DFU_NAND
 #define DFU_ALT_INFO_NAND \
+	"dfu_alt_info_nand=" \
 	"SPL part 0 1;" \
 	"SPL.backup1 part 0 2;" \
 	"SPL.backup2 part 0 3;" \
@@ -325,13 +339,21 @@
 	"u-boot part 0 5;" \
 	"u-boot-spl-os part 0 6;" \
 	"kernel part 0 8;" \
-	"rootfs part 0 9"
+	"rootfs part 0 9\0"
+#else
+#define DFU_ALT_INFO_NAND ""
 #endif
 #define CONFIG_DFU_RAM
 #define DFU_ALT_INFO_RAM \
+	"dfu_alt_info_ram=" \
 	"kernel ram 0x80200000 0xD80000;" \
 	"fdt ram 0x80F80000 0x80000;" \
-	"ramdisk ram 0x81000000 0x4000000"
+	"ramdisk ram 0x81000000 0x4000000\0"
+#define DFUARGS \
+	"dfu_alt_info_emmc=rawemmc mmc 0 3751936\0" \
+	DFU_ALT_INFO_MMC \
+	DFU_ALT_INFO_RAM \
+	DFU_ALT_INFO_NAND
 
 /*
  * Default to using SPI for environment, etc.
@@ -373,13 +395,11 @@
 /* Network. */
 #define CONFIG_PHY_GIGE
 #define CONFIG_PHYLIB
-#define CONFIG_PHY_ADDR			0
 #define CONFIG_PHY_SMSC
 
 /* NAND support */
 #ifdef CONFIG_NAND
 #define CONFIG_CMD_NAND
-#define GPMC_NAND_ECC_LP_x16_LAYOUT	1
 #if !defined(CONFIG_SPI_BOOT) && !defined(CONFIG_NOR_BOOT)
 #define MTDIDS_DEFAULT			"nand0=omap2-nand.0"
 #define MTDPARTS_DEFAULT		"mtdparts=omap2-nand.0:128k(SPL)," \
@@ -419,6 +439,8 @@
 #define CONFIG_SYS_FLASH_BASE		(0x08000000)
 #define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_16BIT
 #define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_FLASH_BASE
+/* Reduce SPL size by removing unlikey targets */
+#undef CONFIG_SPL_SPI_SUPPORT
 #ifdef CONFIG_NOR_BOOT
 #define CONFIG_ENV_IS_IN_FLASH
 #define CONFIG_ENV_SECT_SIZE		(128 << 10)	/* 128 KiB */
diff --git a/include/configs/am335x_igep0033.h b/include/configs/am335x_igep0033.h
new file mode 100644
index 0000000000..c17327fef4
--- /dev/null
+++ b/include/configs/am335x_igep0033.h
@@ -0,0 +1,289 @@
+/*
+ * Copyright (C) 2013, ISEE 2007 SL - http://www.isee.biz/
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __CONFIG_IGEP0033_H
+#define __CONFIG_IGEP0033_H
+
+#define CONFIG_AM33XX
+#define CONFIG_OMAP
+#define CONFIG_OMAP_COMMON
+
+#include <asm/arch/omap.h>
+
+/* Mach type */
+#define MACH_TYPE_IGEP0033		4521	/* Until the next sync */
+#define CONFIG_MACH_TYPE		MACH_TYPE_IGEP0033
+
+/* Clock defines */
+#define V_OSCK				24000000  /* Clock output from T2 */
+#define V_SCLK				(V_OSCK)
+
+#define CONFIG_ENV_SIZE			(128 << 10)	/* 128 KiB */
+#define CONFIG_SYS_MALLOC_LEN		(1024 << 10)
+#define CONFIG_SYS_LONGHELP		/* undef to save memory */
+#define CONFIG_SYS_HUSH_PARSER		/* use "hush" command parser */
+#define CONFIG_SYS_PROMPT		"U-Boot# "
+#define CONFIG_SYS_NO_FLASH
+
+/* Display cpuinfo */
+#define CONFIG_DISPLAY_CPUINFO
+
+/* Flattened Device Tree */
+#define CONFIG_OF_LIBFDT
+
+/* Commands to include */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_BOOTZ
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_ECHO
+#define CONFIG_CMD_EXT4
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_FS_GENERIC
+#define CONFIG_CMD_MMC
+#define CONFIG_CMD_MTDPARTS
+#define CONFIG_CMD_NAND
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_UBI
+#define CONFIG_CMD_UBIFS
+
+/* Make the verbose messages from UBI stop printing */
+#define CONFIG_UBI_SILENCE_MSG
+#define CONFIG_UBIFS_SILENCE_MSG
+
+#define CONFIG_BOOTDELAY		1	/* negative for no autoboot */
+#define CONFIG_ENV_VARS_UBOOT_CONFIG
+#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"loadaddr=0x80F80000\0" \
+	"dtbaddr=0x80200000\0" \
+	"bootdir=/boot\0" \
+	"bootfile=zImage\0" \
+	"dtbfile=am335x-base0033.dtb\0" \
+	"console=ttyO0,115200n8\0" \
+	"mtdids=" MTDIDS_DEFAULT "\0" \
+	"mtdparts=" MTDPARTS_DEFAULT "\0" \
+	"mmcdev=0\0" \
+	"mmcroot=/dev/mmcblk0p2 rw\0" \
+	"ubiroot=ubi0:filesystem rw ubi.mtd=3,2048\0" \
+	"mmcrootfstype=ext4 rootwait\0" \
+	"ubirootfstype=ubifs rootwait\0" \
+	"mmcargs=setenv bootargs console=${console} " \
+		"root=${mmcroot} " \
+		"rootfstype=${mmcrootfstype}\0" \
+	"ubiargs=setenv bootargs console=${console} " \
+		"root=${ubiroot} " \
+		"rootfstype=${ubirootfstype}\0" \
+	"bootenv=uEnv.txt\0" \
+	"loadbootenv=load mmc ${mmcdev} ${loadaddr} ${bootenv}\0" \
+	"importbootenv=echo Importing environment from mmc ...; " \
+		"env import -t ${loadaddr} ${filesize}\0" \
+	"mmcload=load mmc ${mmcdev}:2 ${loadaddr} ${bootdir}/${bootfile}; " \
+		"load mmc ${mmcdev}:2 ${dtbaddr} ${bootdir}/${dtbfile}\0" \
+	"ubiload=ubi part filesystem 2048; ubifsmount ubi0; " \
+		"ubifsload ${loadaddr} ${bootdir}/${bootfile}; " \
+		"ubifsload ${dtbaddr} ${bootdir}/${dtbfile} \0" \
+	"mmcboot=echo Booting from mmc ...; " \
+		"run mmcargs; " \
+		"bootz ${loadaddr} - ${dtbaddr}\0" \
+	"ubiboot=echo Booting from nand (ubifs) ...; " \
+		"run ubiargs; run ubiload; " \
+		"bootz ${loadaddr} - ${dtbaddr}\0" \
+
+#define CONFIG_BOOTCOMMAND \
+	"mmc dev ${mmcdev}; if mmc rescan; then " \
+		"echo SD/MMC found on device ${mmcdev};" \
+		"if run loadbootenv; then " \
+			"echo Loaded environment from ${bootenv};" \
+			"run importbootenv;" \
+		"fi;" \
+		"if test -n $uenvcmd; then " \
+			"echo Running uenvcmd ...;" \
+			"run uenvcmd;" \
+		"fi;" \
+		"if run mmcload; then " \
+			"run mmcboot;" \
+		"fi;" \
+	"else " \
+		"run ubiboot;" \
+	"fi;" \
+
+/* Max number of command args */
+#define CONFIG_SYS_MAXARGS		16
+
+/* Console I/O Buffer Size */
+#define CONFIG_SYS_CBSIZE		512
+
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE \
+					+ sizeof(CONFIG_SYS_PROMPT) + 16)
+
+/* Boot Argument Buffer Size */
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE
+#define CONFIG_SYS_LOAD_ADDR		0x81000000 /* Default load address */
+
+/* Physical Memory Map */
+#define CONFIG_NR_DRAM_BANKS		1		/*  1 bank of DRAM */
+#define CONFIG_MAX_RAM_BANK_SIZE	(1024 << 20)	/* 1GB */
+
+#define CONFIG_SYS_SDRAM_BASE		0x80000000
+#define CONFIG_SYS_INIT_SP_ADDR         (NON_SECURE_SRAM_END - \
+						GENERATED_GBL_DATA_SIZE)
+/* Platform/Board specific defs */
+#define CONFIG_SYS_TIMERBASE		0x48040000	/* Use Timer2 */
+#define CONFIG_SYS_PTV			2	/* Divisor: 2^(PTV+1) => 8 */
+
+/* NS16550 Configuration */
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	(-4)
+#define CONFIG_SYS_NS16550_CLK		(48000000)
+#define CONFIG_SYS_NS16550_COM1		0x44e09000	/* UART0 */
+
+#define CONFIG_CONS_INDEX		1
+#define CONFIG_BAUDRATE			115200
+
+/* CPU */
+#define CONFIG_ARCH_CPU_INIT
+
+#define CONFIG_ENV_OVERWRITE		1
+#define CONFIG_SYS_CONSOLE_INFO_QUIET
+
+/* MMC support */
+#define CONFIG_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_OMAP_HSMMC
+#define CONFIG_DOS_PARTITION
+
+/* GPIO support */
+#define CONFIG_OMAP_GPIO
+
+/* Ethernet support */
+#define CONFIG_DRIVER_TI_CPSW
+#define CONFIG_MII
+#define CONFIG_BOOTP_DNS
+#define CONFIG_BOOTP_DNS2
+#define CONFIG_BOOTP_SEND_HOSTNAME
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_NET_RETRY_COUNT         10
+#define CONFIG_NET_MULTI
+#define CONFIG_PHYLIB
+#define CONFIG_PHY_SMSC
+
+/* NAND support */
+#define CONFIG_NAND
+#define CONFIG_NAND_OMAP_GPMC
+#define CONFIG_NAND_OMAP_ELM
+#define CONFIG_SYS_NAND_BASE		(0x08000000)	/* phys address CS0 */
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+#define CONFIG_SYS_NAND_ONFI_DETECTION	1
+#define CONFIG_SYS_ENV_SECT_SIZE	(128 << 10)	/* 128 KiB */
+#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
+#define CONFIG_ENV_IS_IN_NAND
+#define CONFIG_ENV_OFFSET		0x180000 /* environment starts here */
+#define CONFIG_ENV_ADDR_REDUND		(CONFIG_ENV_OFFSET + CONFIG_SYS_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE_REDUND		(CONFIG_ENV_SIZE)
+
+#define CONFIG_MTD_PARTITIONS
+#define CONFIG_MTD_DEVICE
+#define CONFIG_RBTREE
+#define CONFIG_LZO
+
+#define MTDIDS_DEFAULT			"nand0=omap2-nand.0"
+#define MTDPARTS_DEFAULT		"mtdparts=omap2-nand.0:512k(spl),"\
+					"1m(uboot),256k(environment),"\
+					"-(filesystem)"
+
+/* Unsupported features */
+#undef CONFIG_USE_IRQ
+
+/* Defines for SPL */
+#define CONFIG_SPL
+#define CONFIG_SPL_FRAMEWORK
+/*
+ * Place the image at the start of the ROM defined image space.
+ * We limit our size to the ROM-defined downloaded image area, and use the
+ * rest of the space for stack.
+ */
+#define CONFIG_SPL_TEXT_BASE		0x402F0400
+#define CONFIG_SPL_MAX_SIZE		(0x4030C000 - CONFIG_SPL_TEXT_BASE)
+#define CONFIG_SPL_STACK		CONFIG_SYS_INIT_SP_ADDR
+
+#define CONFIG_SPL_BSS_START_ADDR	0x80000000
+#define CONFIG_SPL_BSS_MAX_SIZE		0x80000		/* 512 KB */
+
+#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR	0x300 /* address 0x60000 */
+#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS	0x200 /* 256 KB */
+#define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION	1
+#define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME	"u-boot.img"
+#define CONFIG_SPL_MMC_SUPPORT
+#define CONFIG_SPL_FAT_SUPPORT
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+#define CONFIG_SPL_LIBDISK_SUPPORT
+#define CONFIG_SPL_LIBGENERIC_SUPPORT
+#define CONFIG_SPL_SERIAL_SUPPORT
+#define CONFIG_SPL_GPIO_SUPPORT
+#define CONFIG_SPL_YMODEM_SUPPORT
+#define CONFIG_SPL_LDSCRIPT		"$(CPUDIR)/am33xx/u-boot-spl.lds"
+
+#define CONFIG_SPL_BOARD_INIT
+#define CONFIG_SPL_NAND_AM33XX_BCH
+#define CONFIG_SPL_NAND_SUPPORT
+#define CONFIG_SPL_NAND_BASE
+#define CONFIG_SPL_NAND_DRIVERS
+#define CONFIG_SPL_NAND_ECC
+#define CONFIG_SYS_NAND_5_ADDR_CYCLE
+#define CONFIG_SYS_NAND_PAGE_COUNT	(CONFIG_SYS_NAND_BLOCK_SIZE / \
+					 CONFIG_SYS_NAND_PAGE_SIZE)
+#define CONFIG_SYS_NAND_PAGE_SIZE	2048
+#define CONFIG_SYS_NAND_OOBSIZE		64
+#define CONFIG_SYS_NAND_BLOCK_SIZE	(128*1024)
+#define CONFIG_SYS_NAND_BAD_BLOCK_POS	NAND_LARGE_BADBLOCK_POS
+#define CONFIG_SYS_NAND_ECCPOS		{ 2, 3, 4, 5, 6, 7, 8, 9, \
+					 10, 11, 12, 13, 14, 15, 16, 17, \
+					 18, 19, 20, 21, 22, 23, 24, 25, \
+					 26, 27, 28, 29, 30, 31, 32, 33, \
+					 34, 35, 36, 37, 38, 39, 40, 41, \
+					 42, 43, 44, 45, 46, 47, 48, 49, \
+					 50, 51, 52, 53, 54, 55, 56, 57, }
+
+#define CONFIG_SYS_NAND_ECCSIZE		512
+#define CONFIG_SYS_NAND_ECCBYTES	14
+#define CONFIG_NAND_OMAP_ECCSCHEME	OMAP_ECC_BCH8_CODE_HW
+
+#define	CONFIG_SYS_NAND_U_BOOT_START	CONFIG_SYS_TEXT_BASE
+
+#define CONFIG_SYS_NAND_U_BOOT_OFFS	0x80000
+
+/*
+ * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM
+ * 64 bytes before this address should be set aside for u-boot.img's
+ * header. That is 0x800FFFC0--0x80100000 should not be used for any
+ * other needs.
+ */
+#define CONFIG_SYS_TEXT_BASE		0x80800000
+#define CONFIG_SYS_SPL_MALLOC_START	0x80208000
+#define CONFIG_SYS_SPL_MALLOC_SIZE	0x100000
+
+/*
+ * Since SPL did pll and ddr initialization for us,
+ * we don't need to do it twice.
+ */
+#ifndef CONFIG_SPL_BUILD
+#define CONFIG_SKIP_LOWLEVEL_INIT
+#endif
+
+#endif	/* ! __CONFIG_IGEP0033_H */
diff --git a/include/configs/am3517_crane.h b/include/configs/am3517_crane.h
index 1fd2508fe9..4407b454dd 100644
--- a/include/configs/am3517_crane.h
+++ b/include/configs/am3517_crane.h
@@ -142,10 +142,10 @@
 #undef CONFIG_CMD_IMLS		/* List all found images	*/
 
 #define CONFIG_SYS_NO_FLASH
-#define CONFIG_HARD_I2C			1
-#define CONFIG_SYS_I2C_SPEED		100000
-#define CONFIG_SYS_I2C_SLAVE		1
-#define CONFIG_DRIVER_OMAP34XX_I2C	1
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_OMAP24_I2C_SPEED	100000
+#define CONFIG_SYS_OMAP24_I2C_SLAVE	1
+#define CONFIG_SYS_I2C_OMAP34XX
 
 #undef CONFIG_CMD_NET
 #undef CONFIG_CMD_NFS
@@ -239,7 +239,6 @@
  */
 #define CONFIG_SYS_TIMERBASE		OMAP34XX_GPT2
 #define CONFIG_SYS_PTV			2	/* Divisor: 2^(PTV+1) => 8 */
-#define CONFIG_SYS_HZ			1000
 
 /*-----------------------------------------------------------------------
  * Physical Memory Map
@@ -269,7 +268,6 @@
 #define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_FLASH_BASE
 
 #define CONFIG_NAND_OMAP_GPMC
-#define GPMC_NAND_ECC_LP_x16_LAYOUT	1
 #define CONFIG_ENV_IS_IN_NAND		1
 #define SMNAND_ENV_OFFSET		0x260000 /* environment starts here */
 
@@ -341,6 +339,7 @@
 						10, 11, 12, 13}
 #define CONFIG_SYS_NAND_ECCSIZE		512
 #define CONFIG_SYS_NAND_ECCBYTES	3
+#define CONFIG_NAND_OMAP_ECCSCHEME	OMAP_ECC_HAM1_CODE_HW
 #define CONFIG_SYS_NAND_U_BOOT_START	CONFIG_SYS_TEXT_BASE
 #define CONFIG_SYS_NAND_U_BOOT_OFFS	0x80000
 
diff --git a/include/configs/am3517_evm.h b/include/configs/am3517_evm.h
index 6500878121..0102ff5b7f 100644
--- a/include/configs/am3517_evm.h
+++ b/include/configs/am3517_evm.h
@@ -58,6 +58,11 @@
  */
 
 /*
+ * OMAP GPIO configuration
+ */
+#define CONFIG_OMAP_GPIO
+
+/*
  * NS16550 Configuration
  */
 #define V_NS16550_CLK			48000000	/* 48MHz (APLL96/2) */
@@ -136,13 +141,23 @@
 #undef CONFIG_CMD_IMLS		/* List all found images	*/
 
 #define CONFIG_SYS_NO_FLASH
-#define CONFIG_HARD_I2C			1
-#define CONFIG_SYS_I2C_SPEED		100000
-#define CONFIG_SYS_I2C_SLAVE		1
-#define CONFIG_DRIVER_OMAP34XX_I2C	1
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_OMAP24_I2C_SPEED	100000
+#define CONFIG_SYS_OMAP24_I2C_SLAVE	1
+#define CONFIG_SYS_I2C_OMAP34XX
+
+/*
+ * Ethernet
+ */
+#define CONFIG_DRIVER_TI_EMAC
+#define CONFIG_DRIVER_TI_EMAC_USE_RMII
+#define CONFIG_MII
+#define CONFIG_BOOTP_DEFAULT
+#define CONFIG_BOOTP_DNS
+#define CONFIG_BOOTP_DNS2
+#define CONFIG_BOOTP_SEND_HOSTNAME
+#define CONFIG_NET_RETRY_COUNT		10
 
-#undef CONFIG_CMD_NET
-#undef CONFIG_CMD_NFS
 /*
  * Board NAND Info.
  */
@@ -231,7 +246,6 @@
  */
 #define CONFIG_SYS_TIMERBASE		OMAP34XX_GPT2
 #define CONFIG_SYS_PTV			2	/* Divisor: 2^(PTV+1) => 8 */
-#define CONFIG_SYS_HZ			1000
 
 /*-----------------------------------------------------------------------
  * Physical Memory Map
@@ -263,7 +277,6 @@
 #define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_FLASH_BASE
 
 #define CONFIG_NAND_OMAP_GPMC
-#define GPMC_NAND_ECC_LP_x16_LAYOUT	1
 #define CONFIG_ENV_IS_IN_NAND		1
 #define SMNAND_ENV_OFFSET		0x260000 /* environment starts here */
 
@@ -335,6 +348,7 @@
 						10, 11, 12, 13}
 #define CONFIG_SYS_NAND_ECCSIZE		512
 #define CONFIG_SYS_NAND_ECCBYTES	3
+#define CONFIG_NAND_OMAP_ECCSCHEME	OMAP_ECC_HAM1_CODE_HW
 #define CONFIG_SYS_NAND_U_BOOT_START	CONFIG_SYS_TEXT_BASE
 #define CONFIG_SYS_NAND_U_BOOT_OFFS	0x80000
 
diff --git a/include/configs/am43xx_evm.h b/include/configs/am43xx_evm.h
index 5c802a1546..614857dd25 100644
--- a/include/configs/am43xx_evm.h
+++ b/include/configs/am43xx_evm.h
@@ -10,126 +10,225 @@
 #define __CONFIG_AM43XX_EVM_H
 
 #define CONFIG_AM43XX
-#define CONFIG_OMAP
-#define CONFIG_OMAP_COMMON
+
+#define CONFIG_BOARD_LATE_INIT
+#define CONFIG_ARCH_CPU_INIT
+#define CONFIG_SYS_CACHELINE_SIZE       32
+#define CONFIG_MAX_RAM_BANK_SIZE	(1024 << 20)	/* 1GB */
+#define CONFIG_SYS_TIMERBASE		0x48040000	/* Use Timer2 */
 
 #include <asm/arch/omap.h>
 
-#define CONFIG_DMA_COHERENT
-#define CONFIG_DMA_COHERENT_SIZE	(1 << 20)
+/* NS16550 Configuration */
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	(-4)
+#define CONFIG_SYS_NS16550_CLK		48000000
+
+/* I2C Configuration */
+#define CONFIG_CMD_EEPROM
+#define CONFIG_ENV_EEPROM_IS_ON_I2C
+#define CONFIG_SYS_I2C_EEPROM_ADDR	0x50	/* Main EEPROM */
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	2
+#define CONFIG_SYS_I2C_MULTI_EEPROMS
+
+/* SPL defines. */
+#define CONFIG_SPL_TEXT_BASE		0x40300350
+#define CONFIG_SPL_MAX_SIZE		(220 << 10)	/* 220KB */
+#define CONFIG_SPL_YMODEM_SUPPORT
 
-#define CONFIG_ENV_SIZE			(128 << 10)	/* 128 KiB */
-#define CONFIG_SYS_MALLOC_LEN		(1024 << 10)
-#define CONFIG_SYS_LONGHELP		/* undef to save memory */
-#define CONFIG_SYS_HUSH_PARSER		/* use "hush" command parser */
-#define CONFIG_SYS_PROMPT		"U-Boot# "
-#define CONFIG_SYS_NO_FLASH
+/* Enabling L2 Cache */
+#define CONFIG_SYS_L2_PL310
+#define CONFIG_SYS_PL310_BASE	0x48242000
+#define CONFIG_SYS_CACHELINE_SIZE	32
 
-#define CONFIG_OF_LIBFDT
-#define CONFIG_CMD_BOOTZ
-#define CONFIG_CMDLINE_TAG		/* enable passing of ATAGs */
-#define CONFIG_CMDLINE_EDITING
-#define CONFIG_SETUP_MEMORY_TAGS
-#define CONFIG_INITRD_TAG
+/*
+ * Since SPL did pll and ddr initialization for us,
+ * we don't need to do it twice.
+ */
+#if !defined(CONFIG_SPL_BUILD) && !defined(CONFIG_NOR_BOOT)
+#define CONFIG_SKIP_LOWLEVEL_INIT
+#endif
 
-/* commands to include */
-#include <config_cmd_default.h>
+/* Now bring in the rest of the common code. */
+#include <configs/ti_armv7_common.h>
 
-#define CONFIG_CMD_ASKENV
-#define CONFIG_VERSION_VARIABLE
+/* Always 128 KiB env size */
+#define CONFIG_ENV_SIZE			(128 << 10)
 
-/* set to negative value for no autoboot */
-#define CONFIG_BOOTDELAY		1
-#define CONFIG_ENV_VARS_UBOOT_CONFIG
 #define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
 
 /* Clock Defines */
 #define V_OSCK				24000000  /* Clock output from T2 */
 #define V_SCLK				(V_OSCK)
 
-#define CONFIG_CMD_ECHO
-
-/* max number of command args */
-#define CONFIG_SYS_MAXARGS		64
-
-/* Console I/O Buffer Size */
-#define CONFIG_SYS_CBSIZE		512
-
-/* Print Buffer Size */
-#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE \
-					+ sizeof(CONFIG_SYS_PROMPT) + 16)
-
-/* Boot Argument Buffer Size */
-#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE
-
- /* Physical Memory Map */
-#define CONFIG_NR_DRAM_BANKS		1		/*  1 bank of DRAM */
-#define PHYS_DRAM_1			0x80000000	/* DRAM Bank #1 */
-#define CONFIG_MAX_RAM_BANK_SIZE	(1024 << 20)	/* 1GB */
-
-#define CONFIG_SYS_SDRAM_BASE		PHYS_DRAM_1
-#define CONFIG_SYS_INIT_SP_ADDR         (NON_SECURE_SRAM_END - \
-						GENERATED_GBL_DATA_SIZE)
-/* Platform/Board specific defs */
-#define CONFIG_SYS_LOAD_ADDR		0x81000000 /* Default load address */
-
-#define CONFIG_SYS_TIMERBASE		0x48040000	/* Use Timer2 */
-#define CONFIG_SYS_PTV			2	/* Divisor: 2^(PTV+1) => 8 */
-#define CONFIG_SYS_HZ			1000
-
 /* NS16550 Configuration */
-#define CONFIG_SYS_NS16550
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE	(-4)
-#define CONFIG_SYS_NS16550_CLK		(48000000)
 #define CONFIG_SYS_NS16550_COM1		0x44e09000	/* Base EVM has UART0 */
 
-#define CONFIG_BAUDRATE		115200
-#define CONFIG_SYS_BAUDRATE_TABLE	{ 110, 300, 600, 1200, 2400, \
-4800, 9600, 14400, 19200, 28800, 38400, 56000, 57600, 115200 }
-
-/* CPU */
-#define CONFIG_ARCH_CPU_INIT
-
-#define CONFIG_ENV_OVERWRITE		1
-#define CONFIG_SYS_CONSOLE_INFO_QUIET
-
 #define CONFIG_ENV_IS_NOWHERE
 
-/*
- * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM
- * 64 bytes before this address should be set aside for u-boot.img's
- * header. That is 0x800FFFC0--0x80100000 should not be used for any
- * other needs.
- */
-#define CONFIG_SYS_TEXT_BASE		0x80800000
-
-#ifndef	CONFIG_SPL_BUILD
-#define CONFIG_SKIP_LOWLEVEL_INIT
-#endif
-
-/* Defines for SPL */
-#define CONFIG_SPL
-#define CONFIG_SPL_FRAMEWORK
-#define CONFIG_SPL_TEXT_BASE		0x402F0400
-#define CONFIG_SPL_MAX_SIZE		(101 * 1024)
-#define CONFIG_SPL_STACK		CONFIG_SYS_INIT_SP_ADDR
-
-#define CONFIG_SPL_BSS_START_ADDR	0x80a00000
-#define CONFIG_SPL_BSS_MAX_SIZE		0x80000		/* 512 KB */
-
-#define CONFIG_SPL_LIBCOMMON_SUPPORT
-#define CONFIG_SPL_LIBDISK_SUPPORT
-#define CONFIG_SPL_LIBGENERIC_SUPPORT
-#define CONFIG_SPL_SERIAL_SUPPORT
-#define CONFIG_SPL_YMODEM_SUPPORT
 #define CONFIG_SPL_LDSCRIPT		"$(CPUDIR)/omap-common/u-boot-spl.lds"
 
-#define CONFIG_SPL_BOARD_INIT
-#define CONFIG_SYS_SPL_MALLOC_START	0x80a08000
-#define CONFIG_SYS_SPL_MALLOC_SIZE	0x100000
+/* SPL USB Support */
+#define CONFIG_SPL_USB_SUPPORT
+#define CONFIG_SPL_USB_HOST_SUPPORT
+#define CONFIG_SYS_USB_FAT_BOOT_PARTITION		1
+
+#define CONFIG_CMD_USB
+#define CONFIG_USB_HOST
+#define CONFIG_USB_XHCI
+#define CONFIG_USB_XHCI_OMAP
+#define CONFIG_USB_STORAGE
+#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2
+
+#define CONFIG_OMAP_USB_PHY
+#define CONFIG_AM437X_USB2PHY2_HOST
+
+/* SPI */
+#undef CONFIG_OMAP3_SPI
+#define CONFIG_TI_QSPI
+#define CONFIG_SPI_FLASH
+#define CONFIG_SPI_FLASH_MACRONIX
+#define CONFIG_CMD_SF
+#define CONFIG_CMD_SPI
+#define CONFIG_TI_SPI_MMAP
+#define CONFIG_QSPI_SEL_GPIO                   48
+#define CONFIG_SF_DEFAULT_SPEED                48000000
+#define CONFIG_DEFAULT_SPI_MODE                SPI_MODE_3
+
+/* SPI SPL */
+#define CONFIG_SPL_SPI_SUPPORT
+#define CONFIG_SPL_SPI_LOAD
+#define CONFIG_SPL_SPI_FLASH_SUPPORT
+#define CONFIG_SPL_SPI_BUS             0
+#define CONFIG_SPL_SPI_CS              0
+#define CONFIG_SYS_SPI_U_BOOT_OFFS     0x20000
+
+/* Enhance our eMMC support / experience. */
+#define CONFIG_CMD_GPT
+#define CONFIG_EFI_PARTITION
+#define CONFIG_PARTITION_UUIDS
+#define CONFIG_CMD_PART
+
+#ifndef CONFIG_SPL_BUILD
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"loadaddr=0x80200000\0" \
+	"fdtaddr=0x80F80000\0" \
+	"fdt_high=0xffffffff\0" \
+	"rdaddr=0x81000000\0" \
+	"fdtfile=undefined\0" \
+	"bootpart=0:2\0" \
+	"bootdir=/boot\0" \
+	"bootfile=zImage\0" \
+	"console=ttyO0,115200n8\0" \
+	"partitions=" \
+		"uuid_disk=${uuid_gpt_disk};" \
+		"name=rootfs,start=2MiB,size=-,uuid=${uuid_gpt_rootfs}\0" \
+	"optargs=\0" \
+	"mmcdev=0\0" \
+	"mmcroot=/dev/mmcblk0p2 rw\0" \
+	"mmcrootfstype=ext4 rootwait\0" \
+	"usbroot=/dev/sda2 rw\0" \
+	"usbrootfstype=ext4 rootwait\0" \
+	"usbdev=0\0" \
+	"ramroot=/dev/ram0 rw ramdisk_size=65536 initrd=${rdaddr},64M\0" \
+	"ramrootfstype=ext2\0" \
+	"mmcargs=setenv bootargs console=${console} " \
+		"${optargs} " \
+		"root=${mmcroot} " \
+		"rootfstype=${mmcrootfstype}\0" \
+	"usbargs=setenv bootargs console=${console} " \
+		"${optargs} " \
+		"root=${usbroot} " \
+		"rootfstype=${usbrootfstype}\0" \
+	"bootenv=uEnv.txt\0" \
+	"loadbootenv=load ${devtype} ${devnum} ${loadaddr} ${bootenv}\0" \
+	"importbootenv=echo Importing environment from mmc ...; " \
+		"env import -t $loadaddr $filesize\0" \
+	"ramargs=setenv bootargs console=${console} " \
+		"${optargs} " \
+		"root=${ramroot} " \
+		"rootfstype=${ramrootfstype}\0" \
+	"loadramdisk=load ${devtype} ${devnum} ${rdaddr} ramdisk.gz\0" \
+	"loadimage=load ${devtype} ${bootpart} ${loadaddr} ${bootdir}/${bootfile}\0" \
+	"loadfdt=load ${devtype} ${bootpart} ${fdtaddr} ${bootdir}/${fdtfile}\0" \
+	"mmcboot=mmc dev ${mmcdev}; " \
+		"setenv devnum ${mmcdev}; " \
+		"if mmc rescan; then " \
+			"echo SD/MMC found on device ${devnum};" \
+			"if run loadbootenv; then " \
+				"echo Loaded environment from ${bootenv};" \
+				"run importbootenv;" \
+			"fi;" \
+			"if test -n $uenvcmd; then " \
+				"echo Running uenvcmd ...;" \
+				"run uenvcmd;" \
+			"fi;" \
+			"if run loadimage; then " \
+				"run loadfdt; " \
+				"echo Booting from mmc${mmcdev} ...; " \
+				"run mmcargs; " \
+				"bootz ${loadaddr} - ${fdtaddr}; " \
+			"fi;" \
+		"fi;\0" \
+	"usbboot=" \
+		"setenv devnum ${usbdev}; " \
+		"setenv devtype usb; " \
+		"usb start ${usbdev}; " \
+		"if usb dev ${usbdev}; then " \
+			"if run loadbootenv; then " \
+				"echo Loaded environment from ${bootenv};" \
+				"run importbootenv;" \
+			"fi;" \
+			"if test -n $uenvcmd; then " \
+				"echo Running uenvcmd ...;" \
+				"run uenvcmd;" \
+			"fi;" \
+			"if run loadimage; then " \
+				"run loadfdt; " \
+				"echo Booting from usb ${usbdev}...; " \
+				"run usbargs;" \
+				"bootz ${loadaddr} - ${fdtaddr}; " \
+			"fi;" \
+		"fi\0" \
+	"findfdt="\
+		"if test $board_name = AM43EPOS; then " \
+			"setenv fdtfile am43x-epos-evm.dtb; fi; " \
+		"if test $board_name = AM43__GP; then " \
+			"setenv fdtfile am437x-gp-evm.dtb; fi; " \
+		"if test $fdtfile = undefined; then " \
+			"echo WARNING: Could not determine device tree; fi; \0"
+
+#define CONFIG_BOOTCOMMAND \
+	"run findfdt; " \
+	"run mmcboot;" \
+	"run usbboot;"
+
+#endif
 
-/* Unsupported features */
-#undef CONFIG_USE_IRQ
+/* CPSW Ethernet */
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_MII
+#define CONFIG_DRIVER_TI_CPSW
+#define CONFIG_MII
+#define CONFIG_BOOTP_DEFAULT
+#define CONFIG_BOOTP_DNS
+#define CONFIG_BOOTP_DNS2
+#define CONFIG_BOOTP_SEND_HOSTNAME
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_NET_RETRY_COUNT		10
+#define CONFIG_NET_MULTI
+#define CONFIG_PHY_GIGE
+#define CONFIG_PHYLIB
+
+#define CONFIG_SPL_ENV_SUPPORT
+#define CONFIG_SPL_NET_VCI_STRING	"AM43xx U-Boot SPL"
+
+#define CONFIG_SPL_ETH_SUPPORT
+#define CONFIG_SPL_NET_SUPPORT
+#define CONFIG_SYS_RX_ETH_BUFFER	64
 
 #endif	/* __CONFIG_AM43XX_EVM_H */
diff --git a/include/configs/amcc-common.h b/include/configs/amcc-common.h
index 580d079ed1..2aea89937a 100644
--- a/include/configs/amcc-common.h
+++ b/include/configs/amcc-common.h
@@ -74,7 +74,6 @@
  */
 #define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
 #define CONFIG_SYS_LONGHELP			/* undef to save memory		*/
-#define CONFIG_SYS_PROMPT		"=> "	/* Monitor Command Prompt	*/
 #if defined(CONFIG_CMD_KGDB)
 #define CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size	*/
 #else
@@ -90,8 +89,6 @@
 #define CONFIG_SYS_LOAD_ADDR		0x100000  /* default load address	*/
 #define CONFIG_SYS_EXTBDINFO			/* To use extended board_into (bd_t) */
 
-#define CONFIG_SYS_HZ			1000	/* decrementer freq: 1 ms ticks	*/
-
 #define CONFIG_CMDLINE_EDITING		/* add command line history	*/
 #define CONFIG_AUTO_COMPLETE		/* add autocompletion support	*/
 #define CONFIG_LOOPW			/* enable loopw command         */
@@ -128,7 +125,6 @@
  */
 #if defined(CONFIG_CMD_KGDB)
 #define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port*/
-#define CONFIG_KGDB_SER_INDEX	2	/* which serial port to use	*/
 #endif
 
 /*
@@ -257,10 +253,4 @@
 		"cp.b ${fileaddr} " __stringify(CONFIG_SYS_MONITOR_BASE) " ${filesize}\0" \
 	"upd=run load update\0"						\
 
-#define CONFIG_AMCC_DEF_ENV_NAND_UPD					\
-	"u-boot-nand=" __stringify(CONFIG_HOSTNAME) "/u-boot-nand.bin\0"\
-	"nload=tftp 200000 ${u-boot-nand}\0"				\
-	"nupdate=nand erase 0 100000;nand write 200000 0 100000\0"	\
-	"nupd=run nload nupdate\0"
-
 #endif /* __AMCC_COMMON_H */
diff --git a/include/configs/ap325rxa.h b/include/configs/ap325rxa.h
index af3a4277e2..462b2e2910 100644
--- a/include/configs/ap325rxa.h
+++ b/include/configs/ap325rxa.h
@@ -11,8 +11,6 @@
 #define __AP325RXA_H
 
 #undef DEBUG
-#define CONFIG_SH		1
-#define CONFIG_SH4		1
 #define CONFIG_CPU_SH7723	1
 #define CONFIG_AP325RXA	1
 
@@ -51,7 +49,6 @@
 /* undef to save memory	*/
 #define CONFIG_SYS_LONGHELP
 /* Monitor Command Prompt */
-#define CONFIG_SYS_PROMPT		"=> "
 /* Buffer size for input from the Console */
 #define CONFIG_SYS_CBSIZE		256
 /* Buffer size for Console output */
@@ -155,7 +152,8 @@
 
 /* Board Clock */
 #define CONFIG_SYS_CLK_FREQ	33333333
+#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
+#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
 #define CONFIG_SYS_TMU_CLK_DIV		(4)	/* 4 (default), 16, 64, 256 or 1024 */
-#define CONFIG_SYS_HZ		1000
 
 #endif	/* __AP325RXA_H */
diff --git a/include/configs/ap_sh4a_4a.h b/include/configs/ap_sh4a_4a.h
index b9112910e7..4282d70266 100644
--- a/include/configs/ap_sh4a_4a.h
+++ b/include/configs/ap_sh4a_4a.h
@@ -10,9 +10,6 @@
 #define __AP_SH4A_4A_H
 
 #undef DEBUG
-#define CONFIG_SH		1
-#define CONFIG_SH4		1
-#define CONFIG_SH4A		1
 #define CONFIG_CPU_SH7734	1
 #define CONFIG_AP_SH4A_4A	1
 #define CONFIG_400MHZ_MODE	1
@@ -67,7 +64,6 @@
 /* undef to save memory	*/
 #define CONFIG_SYS_LONGHELP
 /* Monitor Command Prompt */
-#define CONFIG_SYS_PROMPT		"=> "
 /* Buffer size for input from the Console */
 #define CONFIG_SYS_CBSIZE		256
 /* Buffer size for Console output */
@@ -138,8 +134,6 @@
 #define CONFIG_SYS_MONITOR_LEN	(256 * 1024)
 /* Size of DRAM reserved for malloc() use */
 #define CONFIG_SYS_MALLOC_LEN	(256 * 1024)
-/* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_SIZE	(256)
 #define CONFIG_SYS_BOOTMAPSZ	(8 * 1024 * 1024)
 
 /* ENV setting */
@@ -158,7 +152,8 @@
 #else
 #define CONFIG_SYS_CLK_FREQ 44444444
 #endif
+#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
+#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
 #define CONFIG_SYS_TMU_CLK_DIV      4
-#define CONFIG_SYS_HZ       1000
 
 #endif	/* __AP_SH4A_4A_H */
diff --git a/include/configs/apf27.h b/include/configs/apf27.h
index e7e258fa60..b10c48c20e 100644
--- a/include/configs/apf27.h
+++ b/include/configs/apf27.h
@@ -321,11 +321,12 @@
  */
 
 #ifdef CONFIG_CMD_I2C
-#define CONFIG_HARD_I2C
-#define CONFIG_I2C_MXC
-#define CONFIG_SYS_I2C_BASE		IMX_I2C1_BASE
-#define CONFIG_SYS_I2C_SPEED		100000	/* 100 kHz */
-#define CONFIG_SYS_I2C_SLAVE		0x7F
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_MXC_I2C1_SPEED	100000	/* 100 kHz */
+#define CONFIG_SYS_MXC_I2C1_SLAVE	0x7F
+#define CONFIG_SYS_MXC_I2C2_SPEED	100000	/* 100 kHz */
+#define CONFIG_SYS_MXC_I2C2_SLAVE	0x7F
 #define CONFIG_SYS_I2C_NOPROBES		{ }
 
 #ifdef CONFIG_CMD_EEPROM
@@ -355,11 +356,6 @@
 #endif /* CONFIG_CMD_DATE */
 
 /*
- * Clocks
- */
-#define	CONFIG_SYS_HZ			1000	/* Ticks per second */
-
-/*
  * PLL
  *
  *  31 | x  |x| x x x x |x x x x x x x x x x |x x|x x x x|x x x x x x x x x x| 0
diff --git a/include/configs/arcangel4-be.h b/include/configs/arcangel4-be.h
new file mode 100644
index 0000000000..88d27db08b
--- /dev/null
+++ b/include/configs/arcangel4-be.h
@@ -0,0 +1,92 @@
+/*
+ * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _CONFIG_ARCANGEL4_H_
+#define _CONFIG_ARCANGEL4_H_
+
+/*
+ *  CPU configuration
+ */
+#define CONFIG_SYS_BIG_ENDIAN
+#define CONFIG_ARC700
+#define CONFIG_ARC_MMU_VER		3
+#define CONFIG_SYS_CACHELINE_SIZE	64
+#define CONFIG_SYS_CLK_FREQ		70000000
+#define CONFIG_SYS_TIMER_RATE		CONFIG_SYS_CLK_FREQ
+
+/*
+ * Board configuration
+ */
+#define CONFIG_SYS_GENERIC_BOARD
+#define CONFIG_SKIP_LOWLEVEL_INIT	/* U-Boot is in RAM already */
+
+#define CONFIG_ARCH_EARLY_INIT_R
+
+/*
+ * Memory configuration
+ */
+#define CONFIG_SYS_TEXT_BASE		0x81000000
+#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_TEXT_BASE
+
+#define CONFIG_SYS_DDR_SDRAM_BASE	0x80000000
+#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
+#define CONFIG_SYS_SDRAM_SIZE		0x10000000	/* 256 Mb */
+
+#define CONFIG_SYS_INIT_SP_ADDR		\
+	(CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE)
+
+#define CONFIG_SYS_MALLOC_LEN		0x200000	/* 2 MB */
+#define CONFIG_SYS_BOOTM_LEN		0x2000000	/* 32 MB */
+#define CONFIG_SYS_LOAD_ADDR		0x82000000
+
+#define CONFIG_SYS_NO_FLASH
+
+/*
+ * UART configuration
+ *
+ */
+#define CONFIG_ARC_SERIAL
+#define CONFIG_ARC_UART_BASE		0xC0FC1000
+#define CONFIG_BAUDRATE			115200
+
+/*
+ * Command line configuration
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ELF
+
+#define CONFIG_OF_LIBFDT
+
+#define CONFIG_AUTO_COMPLETE
+#define CONFIG_SYS_MAXARGS		16
+
+/*
+ * Environment settings
+ */
+#define CONFIG_ENV_IS_NOWHERE
+#define CONFIG_ENV_SIZE			0x00200		/* 512 bytes */
+#define CONFIG_ENV_OFFSET		0
+
+/*
+ * Environment configuration
+ */
+#define CONFIG_BOOTDELAY		3
+#define CONFIG_BOOTFILE			"uImage"
+#define CONFIG_BOOTARGS			"console=ttyARC0,115200n8"
+#define CONFIG_LOADADDR			CONFIG_SYS_LOAD_ADDR
+
+/*
+ * Console configuration
+ */
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_SYS_PROMPT		"arcangel4# "
+#define CONFIG_SYS_CBSIZE		256
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE
+#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
+						sizeof(CONFIG_SYS_PROMPT) + 16)
+
+#endif /* _CONFIG_ARCANGEL4_H_ */
diff --git a/include/configs/arcangel4.h b/include/configs/arcangel4.h
new file mode 100644
index 0000000000..4579eb97c2
--- /dev/null
+++ b/include/configs/arcangel4.h
@@ -0,0 +1,91 @@
+/*
+ * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _CONFIG_ARCANGEL4_H_
+#define _CONFIG_ARCANGEL4_H_
+
+/*
+ *  CPU configuration
+ */
+#define CONFIG_ARC700
+#define CONFIG_ARC_MMU_VER		3
+#define CONFIG_SYS_CACHELINE_SIZE	64
+#define CONFIG_SYS_CLK_FREQ		70000000
+#define CONFIG_SYS_TIMER_RATE		CONFIG_SYS_CLK_FREQ
+
+/*
+ * Board configuration
+ */
+#define CONFIG_SYS_GENERIC_BOARD
+#define CONFIG_SKIP_LOWLEVEL_INIT	/* U-Boot is in RAM already */
+
+#define CONFIG_ARCH_EARLY_INIT_R
+
+/*
+ * Memory configuration
+ */
+#define CONFIG_SYS_TEXT_BASE		0x81000000
+#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_TEXT_BASE
+
+#define CONFIG_SYS_DDR_SDRAM_BASE	0x80000000
+#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
+#define CONFIG_SYS_SDRAM_SIZE		0x10000000	/* 256 Mb */
+
+#define CONFIG_SYS_INIT_SP_ADDR		\
+	(CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE)
+
+#define CONFIG_SYS_MALLOC_LEN		0x200000	/* 2 MB */
+#define CONFIG_SYS_BOOTM_LEN		0x2000000	/* 32 MB */
+#define CONFIG_SYS_LOAD_ADDR		0x82000000
+
+#define CONFIG_SYS_NO_FLASH
+
+/*
+ * UART configuration
+ *
+ */
+#define CONFIG_ARC_SERIAL
+#define CONFIG_ARC_UART_BASE		0xC0FC1000
+#define CONFIG_BAUDRATE			115200
+
+/*
+ * Command line configuration
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ELF
+
+#define CONFIG_OF_LIBFDT
+
+#define CONFIG_AUTO_COMPLETE
+#define CONFIG_SYS_MAXARGS		16
+
+/*
+ * Environment settings
+ */
+#define CONFIG_ENV_IS_NOWHERE
+#define CONFIG_ENV_SIZE			0x00200		/* 512 bytes */
+#define CONFIG_ENV_OFFSET		0
+
+/*
+ * Environment configuration
+ */
+#define CONFIG_BOOTDELAY		3
+#define CONFIG_BOOTFILE			"uImage"
+#define CONFIG_BOOTARGS			"console=ttyARC0,115200n8"
+#define CONFIG_LOADADDR			CONFIG_SYS_LOAD_ADDR
+
+/*
+ * Console configuration
+ */
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_SYS_PROMPT		"arcangel4# "
+#define CONFIG_SYS_CBSIZE		256
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE
+#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
+						sizeof(CONFIG_SYS_PROMPT) + 16)
+
+#endif /* _CONFIG_ARCANGEL4_H_ */
diff --git a/include/configs/aria.h b/include/configs/aria.h
index b5e212e9d8..c36cf33f07 100644
--- a/include/configs/aria.h
+++ b/include/configs/aria.h
@@ -31,7 +31,6 @@
  * High Level Configuration Options
  */
 #define CONFIG_E300		1	/* E300 Family */
-#define CONFIG_MPC512X		1	/* MPC512X family */
 #define CONFIG_FSL_DIU_FB	1	/* FSL DIU */
 
 #define	CONFIG_SYS_TEXT_BASE	0xFFF00000
@@ -469,7 +468,6 @@
  */
 #define CONFIG_SYS_LONGHELP			/* undef to save memory */
 #define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
-#define CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt */
 
 #ifdef CONFIG_CMD_KGDB
 # define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size */
@@ -485,8 +483,6 @@
 /* Boot Argument Buffer Size */
 #define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE
 
-#define CONFIG_SYS_HZ		1000
-
 /*
  * For booting Linux, the board info and command line data
  * have to be in the first 256 MB of memory, since this is
@@ -510,7 +506,6 @@
 
 #ifdef CONFIG_CMD_KGDB
 #define CONFIG_KGDB_BAUDRATE		230400	/* speed of kgdb serial port */
-#define CONFIG_KGDB_SER_INDEX		2	/* which serial port to use */
 #endif
 
 /*
diff --git a/include/configs/armadillo-800eva.h b/include/configs/armadillo-800eva.h
index 9f357eadb2..17a2da034d 100644
--- a/include/configs/armadillo-800eva.h
+++ b/include/configs/armadillo-800eva.h
@@ -60,7 +60,6 @@
 #define ARMADILLO_800EVA_SDRAM_SIZE	(512 * 1024 * 1024)
 
 #define CONFIG_SYS_LONGHELP
-#define CONFIG_SYS_PROMPT		"=> "
 #define CONFIG_SYS_CBSIZE		256
 #define CONFIG_SYS_PBSIZE		256
 #define CONFIG_SYS_MAXARGS		16
@@ -95,7 +94,6 @@
 #define CONFIG_SYS_MONITOR_BASE		0x00000000
 #define CONFIG_SYS_MONITOR_LEN		(256 * 1024)
 #define CONFIG_SYS_MALLOC_LEN		(1 * 1024 * 1024)
-#define CONFIG_SYS_GBL_DATA_SIZE	(256)
 #define CONFIG_SYS_BOOTMAPSZ		(8 * 1024 * 1024)
 #define CONFIG_SYS_TEXT_BASE	0xE80C0000
 
@@ -138,7 +136,8 @@
 
 /* Board Clock */
 #define CONFIG_SYS_CLK_FREQ	50000000
+#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
+#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
 #define CONFIG_SYS_TMU_CLK_DIV	4
-#define CONFIG_SYS_HZ		1000
 
 #endif	/* __ARMADILLO_800EVA_H */
diff --git a/include/configs/arndale.h b/include/configs/arndale.h
index ed44a0424c..515facfd67 100644
--- a/include/configs/arndale.h
+++ b/include/configs/arndale.h
@@ -22,8 +22,6 @@
 #define CONFIG_DISPLAY_CPUINFO
 #define CONFIG_DISPLAY_BOARDINFO
 
-/* Enable fdt support for Exynos5250 */
-#define CONFIG_ARCH_DEVICE_TREE		exynos5250
 #define CONFIG_OF_CONTROL
 #define CONFIG_OF_SEPARATE
 
@@ -85,6 +83,7 @@
 #define CONFIG_DWMMC
 #define CONFIG_EXYNOS_DWMMC
 #define CONFIG_SUPPORT_EMMC_BOOT
+#define CONFIG_BOUNCE_BUFFER
 
 
 #define CONFIG_BOARD_EARLY_INIT_F
@@ -116,7 +115,12 @@
 #define CONFIG_USB_EHCI_EXYNOS
 #define CONFIG_USB_STORAGE
 
+#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS	3
+#define CONFIG_USB_HOST_ETHER
+#define CONFIG_USB_ETHER_ASIX
+
 /* MMC SPL */
+#define CONFIG_EXYNOS_SPL
 #define CONFIG_SPL
 #define COPY_BL2_FNPTR_ADDR	0x02020030
 
@@ -144,8 +148,6 @@
 #define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_SDRAM_BASE + 0x5E00000)
 #define CONFIG_SYS_LOAD_ADDR		(CONFIG_SYS_SDRAM_BASE + 0x3E00000)
 
-#define CONFIG_SYS_HZ			1000
-
 #define CONFIG_RD_LVL
 
 #define CONFIG_NR_DRAM_BANKS	8
@@ -200,10 +202,6 @@
 #define BL2_START_OFFSET	(CONFIG_BL2_OFFSET/512)
 #define BL2_SIZE_BLOC_COUNT	(CONFIG_BL2_SIZE/512)
 
-#define CONFIG_SPI_BOOTING
-#define EXYNOS_COPY_SPI_FNPTR_ADDR	0x02020058
-#define SPI_FLASH_UBOOT_POS		(CONFIG_SEC_FW_SIZE + CONFIG_BL1_SIZE)
-
 #define CONFIG_DOS_PARTITION
 #define CONFIG_EFI_PARTITION
 #define CONFIG_CMD_PART
@@ -216,13 +214,12 @@
 
 /* I2C */
 #define CONFIG_SYS_I2C_INIT_BOARD
-#define CONFIG_HARD_I2C
+#define CONFIG_SYS_I2C
 #define CONFIG_CMD_I2C
-#define CONFIG_SYS_I2C_SPEED	100000		/* 100 Kbps */
-#define CONFIG_DRIVER_S3C24X0_I2C
-#define CONFIG_I2C_MULTI_BUS
+#define CONFIG_SYS_I2C_S3C24X0_SPEED	100000		/* 100 Kbps */
+#define CONFIG_SYS_I2C_S3C24X0
 #define CONFIG_MAX_I2C_NUM	8
-#define CONFIG_SYS_I2C_SLAVE    0x0
+#define CONFIG_SYS_I2C_S3C24X0_SLAVE    0x0
 #define CONFIG_I2C_EDID
 
 /* PMIC */
diff --git a/include/configs/astro_mcf5373l.h b/include/configs/astro_mcf5373l.h
index f0dd6ccb74..d875753a66 100644
--- a/include/configs/astro_mcf5373l.h
+++ b/include/configs/astro_mcf5373l.h
@@ -110,10 +110,8 @@
 /*
  * Defines processor clock - important for correct timings concerning serial
  * interface etc.
- * CONFIG_SYS_HZ gives unit: 1000 -> 1 Hz ^= 1000 ms
  */
 
-#define CONFIG_SYS_HZ			1000
 #define CONFIG_SYS_CLK			80000000
 #define CONFIG_SYS_CPU_CLK		(CONFIG_SYS_CLK * 3)
 #define CONFIG_SYS_SDRAM_SIZE		32		/* SDRAM size in MB */
diff --git a/include/configs/at91rm9200ek.h b/include/configs/at91rm9200ek.h
index e158b0dd2d..a30c016b41 100644
--- a/include/configs/at91rm9200ek.h
+++ b/include/configs/at91rm9200ek.h
@@ -14,7 +14,7 @@
 #ifndef __AT91RM9200EK_CONFIG_H__
 #define __AT91RM9200EK_CONFIG_H__
 
-#include <asm/sizes.h>
+#include <linux/sizes.h>
 
 /*
  * set some initial configurations depending on configure target
@@ -43,7 +43,6 @@
 #define AT91C_MAIN_CLOCK		((AT91C_XTAL_CLOCK / 4) * 39)
 #define AT91C_MASTER_CLOCK		(AT91C_MAIN_CLOCK / 3 )
 #define CONFIG_SYS_HZ_CLOCK		(AT91C_MASTER_CLOCK / 2)
-#define CONFIG_SYS_HZ			1000
 
 /* CPU configuration */
 #define CONFIG_AT91RM9200
@@ -154,6 +153,7 @@
  * USB Config
  */
 #define CONFIG_USB_ATMEL			1
+#define CONFIG_USB_ATMEL_CLK_SEL_PLLB
 #define CONFIG_USB_OHCI_NEW			1
 #define CONFIG_USB_KEYBOARD			1
 #define CONFIG_USB_STORAGE			1
diff --git a/include/configs/at91sam9260ek.h b/include/configs/at91sam9260ek.h
index d7fd6b089c..73917b0ec1 100644
--- a/include/configs/at91sam9260ek.h
+++ b/include/configs/at91sam9260ek.h
@@ -28,7 +28,6 @@
 /* ARM asynchronous clock */
 #define CONFIG_SYS_AT91_SLOW_CLOCK	32768		/* slow clock xtal */
 #define CONFIG_SYS_AT91_MAIN_CLOCK	18432000	/* main clock xtal */
-#define CONFIG_SYS_HZ			1000
 
 /* Define actual evaluation board type from used processor type */
 #ifdef CONFIG_AT91SAM9G20
@@ -182,9 +181,11 @@
 #define CONFIG_RMII			1
 #define CONFIG_NET_RETRY_COUNT		20
 #define CONFIG_RESET_PHY_R		1
+#define CONFIG_AT91_WANTS_COMMON_PHY
 
 /* USB */
 #define CONFIG_USB_ATMEL
+#define CONFIG_USB_ATMEL_CLK_SEL_PLLB
 #define CONFIG_USB_OHCI_NEW		1
 #define CONFIG_SYS_USB_OHCI_CPU_INIT		1
 #define CONFIG_SYS_USB_OHCI_REGS_BASE		0x00500000	/* AT91SAM9260_UHP_BASE */
diff --git a/include/configs/at91sam9261ek.h b/include/configs/at91sam9261ek.h
index af56604396..226f8c1612 100644
--- a/include/configs/at91sam9261ek.h
+++ b/include/configs/at91sam9261ek.h
@@ -14,7 +14,6 @@
 /* ARM asynchronous clock */
 #define CONFIG_SYS_AT91_SLOW_CLOCK	32768		/* slow clock xtal */
 #define CONFIG_SYS_AT91_MAIN_CLOCK	18432000	/* 18.432 MHz crystal */
-#define CONFIG_SYS_HZ			1000
 
 #ifdef CONFIG_AT91SAM9G10
 #define CONFIG_AT91SAM9G10EK		/* It's an Atmel AT91SAM9G10 EK*/
@@ -146,6 +145,7 @@
 
 /* USB */
 #define CONFIG_USB_ATMEL
+#define CONFIG_USB_ATMEL_CLK_SEL_PLLB
 #define CONFIG_USB_OHCI_NEW
 #define CONFIG_DOS_PARTITION
 #define CONFIG_SYS_USB_OHCI_CPU_INIT
diff --git a/include/configs/at91sam9263ek.h b/include/configs/at91sam9263ek.h
index 40e167c10a..48c12ea880 100644
--- a/include/configs/at91sam9263ek.h
+++ b/include/configs/at91sam9263ek.h
@@ -26,7 +26,6 @@
 /* ARM asynchronous clock */
 #define CONFIG_SYS_AT91_MAIN_CLOCK	16367660 /* 16.367 MHz crystal */
 #define CONFIG_SYS_AT91_SLOW_CLOCK	32768
-#define CONFIG_SYS_HZ			1000
 
 #define CONFIG_AT91SAM9263EK	1	/* It's an AT91SAM9263EK Board */
 
@@ -104,6 +103,7 @@
 #define CONFIG_CMD_PING		1
 #define CONFIG_CMD_DHCP		1
 #define CONFIG_CMD_NAND		1
+#define CONFIG_CMD_MMC
 #define CONFIG_CMD_USB		1
 
 /* SDRAM */
@@ -124,6 +124,18 @@
 #define DATAFLASH_TCSS			(0x1a << 16)
 #define DATAFLASH_TCHS			(0x1 << 24)
 
+/* MMC */
+#ifdef CONFIG_CMD_MMC
+#define CONFIG_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_GENERIC_ATMEL_MCI
+#endif
+
+/* FAT */
+#ifdef CONFIG_CMD_FAT
+#define CONFIG_DOS_PARTITION
+#endif
+
 /* NOR flash, if populated */
 #ifdef CONFIG_SYS_USE_NORFLASH
 #define CONFIG_SYS_FLASH_CFI			1
@@ -276,9 +288,11 @@
 #define CONFIG_RMII			1
 #define CONFIG_NET_RETRY_COUNT		20
 #define CONFIG_RESET_PHY_R		1
+#define CONFIG_AT91_WANTS_COMMON_PHY
 
 /* USB */
 #define CONFIG_USB_ATMEL
+#define CONFIG_USB_ATMEL_CLK_SEL_PLLB
 #define CONFIG_USB_OHCI_NEW		1
 #define CONFIG_DOS_PARTITION		1
 #define CONFIG_SYS_USB_OHCI_CPU_INIT		1
diff --git a/include/configs/at91sam9m10g45ek.h b/include/configs/at91sam9m10g45ek.h
index fc4ecec7ad..ccfda71c95 100644
--- a/include/configs/at91sam9m10g45ek.h
+++ b/include/configs/at91sam9m10g45ek.h
@@ -15,13 +15,11 @@
 
 #define CONFIG_SYS_TEXT_BASE		0x73f00000
 
-#define CONFIG_AT91_LEGACY
 #define CONFIG_ATMEL_LEGACY		/* required until (g)pio is fixed */
 
 /* ARM asynchronous clock */
 #define CONFIG_SYS_AT91_SLOW_CLOCK      32768
 #define CONFIG_SYS_AT91_MAIN_CLOCK      12000000 /* from 12 MHz crystal */
-#define CONFIG_SYS_HZ		        1000
 
 #define CONFIG_AT91SAM9M10G45EK
 #define CONFIG_AT91FAMILY
@@ -78,6 +76,10 @@
 /*
  * Command line configuration.
  */
+
+/* No NOR flash */
+#define CONFIG_SYS_NO_FLASH
+
 #include <config_cmd_default.h>
 #undef CONFIG_CMD_BDI
 #undef CONFIG_CMD_FPGA
@@ -98,9 +100,6 @@
 #define CONFIG_SYS_INIT_SP_ADDR \
 	(CONFIG_SYS_SDRAM_BASE + 4 * 1024 - GENERATED_GBL_DATA_SIZE)
 
-/* No NOR flash */
-#define CONFIG_SYS_NO_FLASH
-
 /* NAND flash */
 #ifdef CONFIG_CMD_NAND
 #define CONFIG_NAND_ATMEL
@@ -121,6 +120,7 @@
 #define CONFIG_RMII
 #define CONFIG_NET_RETRY_COUNT		20
 #define CONFIG_RESET_PHY_R
+#define CONFIG_AT91_WANTS_COMMON_PHY
 
 /* USB */
 #define CONFIG_USB_EHCI
diff --git a/include/configs/at91sam9n12ek.h b/include/configs/at91sam9n12ek.h
index 28a79258df..e23549d444 100644
--- a/include/configs/at91sam9n12ek.h
+++ b/include/configs/at91sam9n12ek.h
@@ -24,7 +24,6 @@
 /* ARM asynchronous clock */
 #define CONFIG_SYS_AT91_SLOW_CLOCK	32768		/* slow clock xtal */
 #define CONFIG_SYS_AT91_MAIN_CLOCK	16000000	/* main clock xtal */
-#define CONFIG_SYS_HZ			1000
 
 /* Misc CPU related */
 #define CONFIG_CMDLINE_TAG		/* enable passing of ATAGs */
@@ -83,6 +82,7 @@
 #define CONFIG_CMD_SF
 #define CONFIG_CMD_MMC
 #define CONFIG_CMD_FAT
+#define CONFIG_CMD_USB
 
 #define CONFIG_NR_DRAM_BANKS		1
 #define CONFIG_SYS_SDRAM_BASE		0x20000000
@@ -113,8 +113,8 @@
 #define CONFIG_SYS_NAND_BASE		0x40000000
 #define CONFIG_SYS_NAND_MASK_ALE	(1 << 21)
 #define CONFIG_SYS_NAND_MASK_CLE	(1 << 22)
-#define CONFIG_SYS_NAND_ENABLE_PIN	AT91_PIO_PORTD, 4
-#define CONFIG_SYS_NAND_READY_PIN	AT91_PIO_PORTD, 5
+#define CONFIG_SYS_NAND_ENABLE_PIN	GPIO_PIN_PD(4)
+#define CONFIG_SYS_NAND_READY_PIN	GPIO_PIN_PD(5)
 
 /* PMECC & PMERRLOC */
 #define CONFIG_ATMEL_NAND_HWECC
@@ -163,6 +163,18 @@
 #define CONFIG_SYS_MEMTEST_START	CONFIG_SYS_SDRAM_BASE
 #define CONFIG_SYS_MEMTEST_END		0x26e00000
 
+/* USB host */
+#ifdef CONFIG_CMD_USB
+#define CONFIG_USB_ATMEL
+#define CONFIG_USB_ATMEL_CLK_SEL_PLLB
+#define CONFIG_USB_OHCI_NEW
+#define CONFIG_SYS_USB_OHCI_CPU_INIT
+#define CONFIG_SYS_USB_OHCI_REGS_BASE	ATMEL_BASE_OHCI
+#define CONFIG_SYS_USB_OHCI_SLOT_NAME	"at91sam9n12"
+#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS	1
+#define CONFIG_USB_STORAGE
+#endif
+
 #ifdef CONFIG_SYS_USE_SPIFLASH
 
 /* bootstrap + u-boot + env + linux in dataflash on CS0 */
diff --git a/include/configs/at91sam9rlek.h b/include/configs/at91sam9rlek.h
index b08848ef73..3747098d2a 100644
--- a/include/configs/at91sam9rlek.h
+++ b/include/configs/at91sam9rlek.h
@@ -18,7 +18,6 @@
 /* ARM asynchronous clock */
 #define CONFIG_SYS_AT91_SLOW_CLOCK	32768		/* slow clock xtal */
 #define CONFIG_SYS_AT91_MAIN_CLOCK	12000000	/* main clock xtal */
-#define CONFIG_SYS_HZ			1000
 
 #define CONFIG_AT91SAM9RLEK		1	/* It's an AT91SAM9RLEK Board */
 
diff --git a/include/configs/at91sam9x5ek.h b/include/configs/at91sam9x5ek.h
index 4a2ac9aabd..f0a6757ff6 100644
--- a/include/configs/at91sam9x5ek.h
+++ b/include/configs/at91sam9x5ek.h
@@ -16,7 +16,6 @@
 /* ARM asynchronous clock */
 #define CONFIG_SYS_AT91_SLOW_CLOCK	32768
 #define CONFIG_SYS_AT91_MAIN_CLOCK	12000000	/* 12 MHz crystal */
-#define CONFIG_SYS_HZ			1000
 
 #define CONFIG_AT91SAM9X5EK
 #define CONFIG_AT91FAMILY
@@ -45,7 +44,6 @@
 #define LCD_BPP			LCD_COLOR16
 #define LCD_OUTPUT_BPP		24
 #define CONFIG_LCD_LOGO
-#undef LCD_TEST_PATTERN
 #define CONFIG_LCD_INFO
 #define CONFIG_LCD_INFO_BELOW_LOGO
 #define CONFIG_SYS_WHITE_ON_BLACK
@@ -63,14 +61,15 @@
 #define CONFIG_BOOTP_GATEWAY
 #define CONFIG_BOOTP_HOSTNAME
 
+/* no NOR flash */
+#define CONFIG_SYS_NO_FLASH
+
 /*
  * Command line configuration.
  */
 #include <config_cmd_default.h>
 #undef CONFIG_CMD_FPGA
 #undef CONFIG_CMD_IMI
-#undef CONFIG_CMD_IMLS
-#undef CONFIG_CMD_LOADS
 
 #define CONFIG_CMD_PING
 #define CONFIG_CMD_DHCP
@@ -102,9 +101,6 @@
 #define CONFIG_SF_DEFAULT_SPEED		30000000
 #endif
 
-/* no NOR flash */
-#define CONFIG_SYS_NO_FLASH
-
 /* NAND flash */
 #ifdef CONFIG_CMD_NAND
 #define CONFIG_NAND_ATMEL
@@ -159,13 +155,14 @@
 #define CONFIG_USB_EHCI_ATMEL
 #define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS	2
 #else
+#define CONFIG_USB_ATMEL
+#define CONFIG_USB_ATMEL_CLK_SEL_UPLL
 #define CONFIG_USB_OHCI_NEW
 #define CONFIG_SYS_USB_OHCI_CPU_INIT
 #define CONFIG_SYS_USB_OHCI_REGS_BASE		ATMEL_BASE_OHCI
 #define CONFIG_SYS_USB_OHCI_SLOT_NAME		"at91sam9x5"
 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS	3
 #endif
-#define CONFIG_USB_ATMEL
 #define CONFIG_USB_STORAGE
 #endif
 
@@ -244,8 +241,4 @@
  */
 #define CONFIG_SYS_MALLOC_LEN		(512 * 1024 + 0x1000)
 
-#ifdef CONFIG_USE_IRQ
-#error CONFIG_USE_IRQ not supported
-#endif
-
 #endif
diff --git a/include/configs/atc.h b/include/configs/atc.h
index b661e95e04..77fa79a185 100644
--- a/include/configs/atc.h
+++ b/include/configs/atc.h
@@ -17,7 +17,6 @@
  * (easy to change)
  */
 
-#define CONFIG_MPC8260		1	/* This is an MPC8260 CPU		*/
 #define CONFIG_ATC		1	/* ...on a ATC board	*/
 #define CONFIG_CPM2		1	/* Has a CPM2 */
 
@@ -136,7 +135,6 @@
  * Miscellaneous configurable options
  */
 #define	CONFIG_SYS_LONGHELP			/* undef to save memory		*/
-#define	CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt	*/
 #if defined(CONFIG_CMD_KGDB)
 #define	CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
 #else
@@ -153,8 +151,6 @@
 
 #define CONFIG_SYS_PIO_MODE		0	/* IDE interface in PIO Mode 0	*/
 
-#define	CONFIG_SYS_HZ		1000		/* decrementer freq: 1 ms ticks	*/
-
 #define	CONFIG_SYS_RESET_ADDRESS 0xFFF00100	/* "bad" address		*/
 
 #define CONFIG_SYS_ALLOC_DPRAM
diff --git a/include/configs/atngw100.h b/include/configs/atngw100.h
index c87e4147cd..9c81e3199f 100644
--- a/include/configs/atngw100.h
+++ b/include/configs/atngw100.h
@@ -10,13 +10,10 @@
 
 #include <asm/arch/hardware.h>
 
-#define CONFIG_AVR32
 #define CONFIG_AT32AP
 #define CONFIG_AT32AP7000
 #define CONFIG_ATNGW100
 
-#define CONFIG_SYS_HZ				1000
-
 /*
  * Set up the PLL to run at 140 MHz, the CPU to run at the PLL
  * frequency, the HSB and PBB busses to run at 1/2 the PLL frequency
diff --git a/include/configs/atngw100mkii.h b/include/configs/atngw100mkii.h
index 8e4ad073cd..066d09ab0a 100644
--- a/include/configs/atngw100mkii.h
+++ b/include/configs/atngw100mkii.h
@@ -12,18 +12,11 @@
 
 #include <asm/arch/hardware.h>
 
-#define CONFIG_AVR32
 #define CONFIG_AT32AP
 #define CONFIG_AT32AP7000
 #define CONFIG_ATNGW100MKII
 
 /*
- * Timer clock frequency. We're using the CPU-internal COUNT register
- * for this, so this is equivalent to the CPU core clock frequency
- */
-#define CONFIG_SYS_HZ			1000
-
-/*
  * Set up the PLL to run at 140 MHz, the CPU to run at the PLL
  * frequency, the HSB and PBB busses to run at 1/2 the PLL frequency
  * and the PBA bus to run at 1/4 the PLL frequency.
diff --git a/include/configs/atstk1002.h b/include/configs/atstk1002.h
index 5be563ce0d..8f3fd0bb00 100644
--- a/include/configs/atstk1002.h
+++ b/include/configs/atstk1002.h
@@ -10,19 +10,12 @@
 
 #include <asm/arch/hardware.h>
 
-#define CONFIG_AVR32
 #define CONFIG_AT32AP
 #define CONFIG_AT32AP7000
 #define CONFIG_ATSTK1002
 #define CONFIG_ATSTK1000
 
 /*
- * Timer clock frequency. We're using the CPU-internal COUNT register
- * for this, so this is equivalent to the CPU core clock frequency
- */
-#define CONFIG_SYS_HZ				1000
-
-/*
  * Set up the PLL to run at 140 MHz, the CPU to run at the PLL
  * frequency, the HSB and PBB at 1/2, and the PBA to run at 1/4 the
  * PLL frequency.
diff --git a/include/configs/atstk1003.h b/include/configs/atstk1003.h
index a49d0add82..63704b1987 100644
--- a/include/configs/atstk1003.h
+++ b/include/configs/atstk1003.h
@@ -10,19 +10,12 @@
 
 #include <asm/arch/hardware.h>
 
-#define CONFIG_AVR32
 #define CONFIG_AT32AP
 #define CONFIG_AT32AP7001
 #define CONFIG_ATSTK1003
 #define CONFIG_ATSTK1000
 
 /*
- * Timer clock frequency. We're using the CPU-internal COUNT register
- * for this, so this is equivalent to the CPU core clock frequency
- */
-#define CONFIG_SYS_HZ				1000
-
-/*
  * Set up the PLL to run at 140 MHz, the CPU to run at the PLL
  * frequency, the HSB and PBB at 1/2, and the PBA to run at 1/4 the
  * PLL frequency.
diff --git a/include/configs/atstk1004.h b/include/configs/atstk1004.h
index 7f3976c54f..331a60d76a 100644
--- a/include/configs/atstk1004.h
+++ b/include/configs/atstk1004.h
@@ -10,19 +10,12 @@
 
 #include <asm/arch/hardware.h>
 
-#define CONFIG_AVR32
 #define CONFIG_AT32AP
 #define CONFIG_AT32AP7002
 #define CONFIG_ATSTK1004
 #define CONFIG_ATSTK1000
 
 /*
- * Timer clock frequency. We're using the CPU-internal COUNT register
- * for this, so this is equivalent to the CPU core clock frequency
- */
-#define CONFIG_SYS_HZ				1000
-
-/*
  * Set up the PLL to run at 140 MHz, the CPU to run at the PLL
  * frequency, the HSB and PBB at 1/2, and the PBA to run at 1/4 the
  * PLL frequency.
diff --git a/include/configs/atstk1006.h b/include/configs/atstk1006.h
index 97470dfad8..bbe0aea861 100644
--- a/include/configs/atstk1006.h
+++ b/include/configs/atstk1006.h
@@ -10,17 +10,11 @@
 
 #include <asm/arch/hardware.h>
 
-#define CONFIG_AVR32
 #define CONFIG_AT32AP
 #define CONFIG_AT32AP7000
 #define CONFIG_ATSTK1006
 #define CONFIG_ATSTK1000
 
-/*
- * Timer clock frequency. We're using the CPU-internal COUNT register
- * for this, so this is equivalent to the CPU core clock frequency
- */
-#define CONFIG_SYS_HZ				1000
 
 /*
  * Set up the PLL to run at 140 MHz, the CPU to run at the PLL
diff --git a/include/configs/axs101.h b/include/configs/axs101.h
new file mode 100644
index 0000000000..f6b569abfd
--- /dev/null
+++ b/include/configs/axs101.h
@@ -0,0 +1,181 @@
+/*
+ * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _CONFIG_AXS101_H_
+#define _CONFIG_AXS101_H_
+
+/*
+ *  CPU configuration
+ */
+#define CONFIG_ARC700
+#define CONFIG_ARC_MMU_VER		3
+#define CONFIG_SYS_CACHELINE_SIZE	32
+#define CONFIG_SYS_CLK_FREQ		750000000
+#define CONFIG_SYS_TIMER_RATE		CONFIG_SYS_CLK_FREQ
+
+/* dwgmac doesn't work with D$ enabled now */
+#define CONFIG_SYS_DCACHE_OFF
+
+/*
+ * Board configuration
+ */
+#define CONFIG_SYS_GENERIC_BOARD
+#define CONFIG_SKIP_LOWLEVEL_INIT	/* U-Boot is in RAM already */
+
+#define CONFIG_ARCH_EARLY_INIT_R
+
+#define ARC_FPGA_PERIPHERAL_BASE	0xE0000000
+#define ARC_APB_PERIPHERAL_BASE		0xF0000000
+#define ARC_DWMMC_BASE			(ARC_FPGA_PERIPHERAL_BASE + 0x15000)
+#define ARC_DWGMAC_BASE			(ARC_FPGA_PERIPHERAL_BASE + 0x18000)
+
+/*
+ * Memory configuration
+ */
+#define CONFIG_SYS_TEXT_BASE		0x81000000
+#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_TEXT_BASE
+
+#define CONFIG_SYS_DDR_SDRAM_BASE	0x80000000
+#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
+#define CONFIG_SYS_SDRAM_SIZE		0x10000000	/* 256 Mb */
+
+#define CONFIG_SYS_INIT_SP_ADDR		\
+	(CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE)
+
+#define CONFIG_SYS_MALLOC_LEN		0x200000	/* 2 MB */
+#define CONFIG_SYS_BOOTM_LEN		0x2000000	/* 32 MB */
+#define CONFIG_SYS_LOAD_ADDR		0x82000000
+
+/*
+ * NAND Flash configuration
+ */
+#define CONFIG_SYS_NO_FLASH
+#define CONFIG_SYS_NAND_BASE		(ARC_FPGA_PERIPHERAL_BASE + 0x16000)
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+
+/*
+ * UART configuration
+ *
+ * CONFIG_CONS_INDEX = 1 - Debug UART
+ * CONFIG_CONS_INDEX = 4 - FPGA UART connected to FTDI/USB
+ */
+#define CONFIG_CONS_INDEX		4
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	-4
+#if (CONFIG_CONS_INDEX == 1)
+	/* Debug UART */
+#	define CONFIG_SYS_NS16550_CLK		33333000
+#else
+	/* FPGA UARTs use different clock */
+#	define CONFIG_SYS_NS16550_CLK		33333333
+#endif
+#define CONFIG_SYS_NS16550_COM1		(ARC_APB_PERIPHERAL_BASE + 0x5000)
+#define CONFIG_SYS_NS16550_COM2		(ARC_FPGA_PERIPHERAL_BASE + 0x20000)
+#define CONFIG_SYS_NS16550_COM3		(ARC_FPGA_PERIPHERAL_BASE + 0x21000)
+#define CONFIG_SYS_NS16550_COM4		(ARC_FPGA_PERIPHERAL_BASE + 0x22000)
+#define CONFIG_SYS_NS16550_MEM32
+
+#define CONFIG_BAUDRATE			115200
+/*
+ * I2C configuration
+ */
+#define CONFIG_HARD_I2C
+#define CONFIG_DW_I2C
+#define CONFIG_I2C_MULTI_BUS
+#define CONFIG_I2C_ENV_EEPROM_BUS	2
+#define CONFIG_SYS_I2C_SPEED		100000
+#define CONFIG_SYS_I2C_SLAVE		0
+#define CONFIG_SYS_I2C_BASE		0xE001D000
+#define CONFIG_SYS_I2C_BASE1		0xE001E000
+#define CONFIG_SYS_I2C_BASE2		0xE001F000
+#define CONFIG_SYS_I2C_BUS_MAX		3
+#define IC_CLK				50
+
+/*
+ * EEPROM configuration
+ */
+#define CONFIG_SYS_I2C_MULTI_EEPROMS
+#define CONFIG_SYS_I2C_EEPROM_ADDR		(0xA8 >> 1)
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		1
+#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW	1
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	3
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	32
+
+/*
+ * SD/MMC configuration
+ */
+#define CONFIG_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_DWMMC
+#define CONFIG_DOS_PARTITION
+
+/*
+ * Ethernet PHY configuration
+ */
+#define CONFIG_PHYLIB
+#define CONFIG_MII
+#define CONFIG_PHY_GIGE
+
+/*
+ * Ethernet configuration
+ */
+#define CONFIG_DESIGNWARE_ETH
+#define CONFIG_DW_AUTONEG
+#define CONFIG_DW_SEARCH_PHY
+#define CONFIG_NET_MULTI
+
+/*
+ * Command line configuration
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_MMC
+#define CONFIG_CMD_NAND
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_RARP
+
+#define CONFIG_OF_LIBFDT
+
+#define CONFIG_AUTO_COMPLETE
+#define CONFIG_SYS_MAXARGS		16
+
+/*
+ * Environment settings
+ */
+#define CONFIG_ENV_IS_IN_EEPROM
+#define CONFIG_ENV_SIZE			0x00200		/* 512 bytes */
+#define CONFIG_ENV_OFFSET		0
+
+/*
+ * Environment configuration
+ */
+#define CONFIG_BOOTDELAY		3
+#define CONFIG_BOOTFILE			"uImage"
+#define CONFIG_BOOTARGS			"console=ttyS3,115200n8"
+#define CONFIG_LOADADDR			CONFIG_SYS_LOAD_ADDR
+
+/*
+ * Console configuration
+ */
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_SYS_PROMPT		"AXS# "
+#define CONFIG_SYS_CBSIZE		256
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE
+#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
+						sizeof(CONFIG_SYS_PROMPT) + 16)
+
+/*
+ * Misc utility configuration
+ */
+#define CONFIG_BOUNCE_BUFFER
+
+#endif /* _CONFIG_AXS101_H_ */
diff --git a/include/configs/balloon3.h b/include/configs/balloon3.h
index cbf2853549..5228ba6ef7 100644
--- a/include/configs/balloon3.h
+++ b/include/configs/balloon3.h
@@ -61,7 +61,6 @@
  */
 #ifdef	CONFIG_CMD_KGDB
 #define	CONFIG_KGDB_BAUDRATE		230400	/* kgdb serial port speed */
-#define	CONFIG_KGDB_SER_INDEX		2	/* which serial port to use */
 #endif
 
 /*
@@ -73,7 +72,6 @@
 #ifdef	CONFIG_SYS_HUSH_PARSER
 #define	CONFIG_SYS_PROMPT		"$ "
 #else
-#define	CONFIG_SYS_PROMPT		"=> "
 #endif
 #define	CONFIG_SYS_CBSIZE		256
 #define	CONFIG_SYS_PBSIZE		\
@@ -86,7 +84,6 @@
  * Clock Configuration
  */
 #undef	CONFIG_SYS_CLKS_IN_HZ
-#define	CONFIG_SYS_HZ			3250000		/* Timer @ 3250000 Hz */
 #define	CONFIG_SYS_CPUSPEED		0x290		/* 520MHz */
 
 /*
@@ -129,10 +126,10 @@
 
 #define	CONFIG_SYS_FLASH_USE_BUFFER_WRITE	1
 
-#define	CONFIG_SYS_FLASH_ERASE_TOUT	(2*CONFIG_SYS_HZ)
-#define	CONFIG_SYS_FLASH_WRITE_TOUT	(2*CONFIG_SYS_HZ)
-#define	CONFIG_SYS_FLASH_LOCK_TOUT	(2*CONFIG_SYS_HZ)
-#define	CONFIG_SYS_FLASH_UNLOCK_TOUT	(2*CONFIG_SYS_HZ)
+#define	CONFIG_SYS_FLASH_ERASE_TOUT	240000
+#define	CONFIG_SYS_FLASH_WRITE_TOUT	240000
+#define	CONFIG_SYS_FLASH_LOCK_TOUT	240000
+#define	CONFIG_SYS_FLASH_UNLOCK_TOUT	240000
 #define	CONFIG_SYS_FLASH_PROTECTION
 #define	CONFIG_ENV_IS_IN_FLASH
 #else
diff --git a/include/configs/bamboo.h b/include/configs/bamboo.h
index 326e3d6692..6ba4aaf8cb 100644
--- a/include/configs/bamboo.h
+++ b/include/configs/bamboo.h
@@ -17,7 +17,6 @@
 #define CONFIG_BAMBOO		1	/* Board is BAMBOO              */
 #define CONFIG_440EP		1	/* Specific PPC440EP support    */
 #define CONFIG_440		1	/* ... PPC440 family	        */
-#define CONFIG_4xx		1	/* ... PPC4xx family	        */
 #define CONFIG_SYS_CLK_FREQ	33333333    /* external freq to pll	*/
 
 #ifndef CONFIG_SYS_TEXT_BASE
@@ -87,12 +86,7 @@
 /*-----------------------------------------------------------------------
  * Environment
  *----------------------------------------------------------------------*/
-#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
 #define CONFIG_ENV_IS_IN_FLASH     1	/* use FLASH for environment vars	*/
-#else
-#define CONFIG_ENV_IS_IN_NAND	1	/* use NAND for environment vars	*/
-#define CONFIG_ENV_IS_EMBEDDED	1	/* use embedded environment */
-#endif
 
 /*-----------------------------------------------------------------------
  * FLASH related
@@ -121,61 +115,6 @@
 #define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SIZE)
 #endif /* CONFIG_ENV_IS_IN_FLASH */
 
-/*
- * IPL (Initial Program Loader, integrated inside CPU)
- * Will load first 4k from NAND (SPL) into cache and execute it from there.
- *
- * SPL (Secondary Program Loader)
- * Will load special U-Boot version (NUB) from NAND and execute it. This SPL
- * has to fit into 4kByte. It sets up the CPU and configures the SDRAM
- * controller and the NAND controller so that the special U-Boot image can be
- * loaded from NAND to SDRAM.
- *
- * NUB (NAND U-Boot)
- * This NAND U-Boot (NUB) is a special U-Boot version which can be started
- * from RAM. Therefore it mustn't (re-)configure the SDRAM controller.
- *
- * On 440EPx the SPL is copied to SDRAM before the NAND controller is
- * set up. While still running from cache, I experienced problems accessing
- * the NAND controller.	sr - 2006-08-25
- */
-#define CONFIG_SYS_NAND_BOOT_SPL_SRC	0xfffff000	/* SPL location			*/
-#define CONFIG_SYS_NAND_BOOT_SPL_SIZE	(4 << 10)	/* SPL size			*/
-#define CONFIG_SYS_NAND_BOOT_SPL_DST	0x00800000	/* Copy SPL here		*/
-#define CONFIG_SYS_NAND_U_BOOT_DST	0x01000000	/* Load NUB to this addr	*/
-#define CONFIG_SYS_NAND_U_BOOT_START	CONFIG_SYS_NAND_U_BOOT_DST /* Start NUB from this addr	*/
-#define CONFIG_SYS_NAND_BOOT_SPL_DELTA	(CONFIG_SYS_NAND_BOOT_SPL_SRC - CONFIG_SYS_NAND_BOOT_SPL_DST)
-
-/*
- * Define the partitioning of the NAND chip (only RAM U-Boot is needed here)
- */
-#define CONFIG_SYS_NAND_U_BOOT_OFFS	(16 << 10)	/* Offset to RAM U-Boot image	*/
-#define CONFIG_SYS_NAND_U_BOOT_SIZE	(384 << 10)	/* Size of RAM U-Boot image	*/
-
-/*
- * Now the NAND chip has to be defined (no autodetection used!)
- */
-#define CONFIG_SYS_NAND_PAGE_SIZE	512		/* NAND chip page size		*/
-#define CONFIG_SYS_NAND_BLOCK_SIZE	(16 << 10)	/* NAND chip block size		*/
-#define CONFIG_SYS_NAND_PAGE_COUNT	32		/* NAND chip page count		*/
-#define CONFIG_SYS_NAND_BAD_BLOCK_POS	5		/* Location of bad block marker	*/
-#define CONFIG_SYS_NAND_4_ADDR_CYCLE	1		/* Fourth addr used (>32MB)	*/
-
-#define CONFIG_SYS_NAND_ECCSIZE	256
-#define CONFIG_SYS_NAND_ECCBYTES	3
-#define CONFIG_SYS_NAND_OOBSIZE	16
-#define CONFIG_SYS_NAND_ECCPOS		{0, 1, 2, 3, 6, 7}
-
-#ifdef CONFIG_ENV_IS_IN_NAND
-/*
- * For NAND booting the environment is embedded in the U-Boot image. Please take
- * look at the file board/amcc/sequoia/u-boot-nand.lds for details.
- */
-#define CONFIG_ENV_SIZE		CONFIG_SYS_NAND_BLOCK_SIZE
-#define CONFIG_ENV_OFFSET		(CONFIG_SYS_NAND_U_BOOT_OFFS + CONFIG_ENV_SIZE)
-#define CONFIG_ENV_OFFSET_REDUND	(CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
-#endif
-
 /*-----------------------------------------------------------------------
  * NAND FLASH
  *----------------------------------------------------------------------*/
@@ -183,15 +122,7 @@
 #define CONFIG_SYS_NAND_BASE		(CONFIG_SYS_NAND_ADDR + CONFIG_SYS_NAND_CS)
 #define CONFIG_SYS_NAND_BASE_LIST	{ CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_ADDR + 2 }
 #define CONFIG_SYS_NAND_SELECT_DEVICE  1	/* nand driver supports mutipl. chips	*/
-
-#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
 #define CONFIG_SYS_NAND_CS		1
-#else
-#define CONFIG_SYS_NAND_CS		0		/* NAND chip connected to CSx	*/
-/* Memory Bank 0 (NAND-FLASH) initialization					*/
-#define CONFIG_SYS_EBC_PB0AP		0x018003c0
-#define CONFIG_SYS_EBC_PB0CR		(CONFIG_SYS_NAND_ADDR | 0x1c000)
-#endif
 
 /*-----------------------------------------------------------------------
  * DDR SDRAM
@@ -227,7 +158,6 @@
 	CONFIG_AMCC_DEF_ENV_POWERPC					\
 	CONFIG_AMCC_DEF_ENV_PPC_OLD					\
 	CONFIG_AMCC_DEF_ENV_NOR_UPD					\
-	CONFIG_AMCC_DEF_ENV_NAND_UPD					\
 	"kernel_addr=fff00000\0"					\
 	"ramdisk_addr=fff10000\0"					\
 	""
diff --git a/include/configs/bcm28155_ap.h b/include/configs/bcm28155_ap.h
new file mode 100644
index 0000000000..e93b855f8f
--- /dev/null
+++ b/include/configs/bcm28155_ap.h
@@ -0,0 +1,140 @@
+/*
+ * Copyright 2013 Broadcom Corporation.
+ *
+ * SPDX-License-Identifier:      GPL-2.0+
+ */
+
+#ifndef __BCM28155_AP_H
+#define __BCM28155_AP_H
+
+#include <linux/sizes.h>
+#include <asm/arch/sysmap.h>
+
+/* Architecture, CPU, chip, mach, etc */
+#define CONFIG_ARMV7
+#define CONFIG_KONA
+#define CONFIG_SKIP_LOWLEVEL_INIT
+
+/*
+ * Memory configuration
+ */
+#define CONFIG_SYS_TEXT_BASE		0xae000000
+
+#define CONFIG_SYS_SDRAM_BASE		0x80000000
+#define CONFIG_SYS_SDRAM_SIZE		0x80000000
+#define CONFIG_NR_DRAM_BANKS		1
+
+#define CONFIG_SYS_MALLOC_LEN		SZ_4M	/* see armv7/start.S. */
+#define CONFIG_STACKSIZE		SZ_256K
+
+/* GPIO Driver */
+#define CONFIG_KONA_GPIO
+
+/* MMC/SD Driver */
+#define CONFIG_SDHCI
+#define CONFIG_MMC_SDMA
+#define CONFIG_KONA_SDHCI
+#define CONFIG_MMC
+#define CONFIG_GENERIC_MMC
+
+#define CONFIG_SYS_SDIO_BASE0 SDIO1_BASE_ADDR
+#define CONFIG_SYS_SDIO_BASE1 SDIO2_BASE_ADDR
+#define CONFIG_SYS_SDIO_BASE2 SDIO3_BASE_ADDR
+#define CONFIG_SYS_SDIO_BASE3 SDIO4_BASE_ADDR
+#define CONFIG_SYS_SDIO0_MAX_CLK 48000000
+#define CONFIG_SYS_SDIO1_MAX_CLK 48000000
+#define CONFIG_SYS_SDIO2_MAX_CLK 48000000
+#define CONFIG_SYS_SDIO3_MAX_CLK 48000000
+#define CONFIG_SYS_SDIO0 "sdio1"
+#define CONFIG_SYS_SDIO1 "sdio2"
+#define CONFIG_SYS_SDIO2 "sdio3"
+#define CONFIG_SYS_SDIO3 "sdio4"
+
+/* I2C Driver */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_KONA
+#define CONFIG_SYS_SPD_BUS_NUM	3	/* Start with PMU bus */
+#define CONFIG_SYS_MAX_I2C_BUS	4
+#define CONFIG_SYS_I2C_BASE0	BSC1_BASE_ADDR
+#define CONFIG_SYS_I2C_BASE1	BSC2_BASE_ADDR
+#define CONFIG_SYS_I2C_BASE2	BSC3_BASE_ADDR
+#define CONFIG_SYS_I2C_BASE3	PMU_BSC_BASE_ADDR
+
+/* Timer Driver */
+#define CONFIG_SYS_TIMER_RATE		32000
+#define CONFIG_SYS_TIMER_COUNTER	(TIMER_BASE_ADDR + 4) /* STCLO offset */
+
+/* Init functions */
+#define CONFIG_MISC_INIT_R	/* board's misc_init_r function */
+
+/* Some commands use this as the default load address */
+#define CONFIG_SYS_LOAD_ADDR		CONFIG_SYS_SDRAM_BASE
+
+/* No mtest functions as recommended */
+#undef CONFIG_CMD_MEMORY
+
+/*
+ * This is the initial SP which is used only briefly for relocating the u-boot
+ * image to the top of SDRAM. After relocation u-boot moves the stack to the
+ * proper place.
+ */
+#define CONFIG_SYS_INIT_SP_ADDR		CONFIG_SYS_TEXT_BASE
+
+/* Serial Info */
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+/* Post pad 3 bytes after each reg addr */
+#define CONFIG_SYS_NS16550_REG_SIZE	(-4)
+#define CONFIG_SYS_NS16550_CLK		13000000
+#define CONFIG_CONS_INDEX		1
+#define CONFIG_SYS_NS16550_COM1		0x3e000000
+
+#define CONFIG_BAUDRATE			115200
+
+#define CONFIG_ENV_SIZE			0x10000
+#define CONFIG_ENV_IS_NOWHERE
+
+#define CONFIG_SYS_NO_FLASH	/* Not using NAND/NOR unmanaged flash */
+
+/* console configuration */
+#define CONFIG_SYS_CBSIZE		1024	/* Console buffer size */
+#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
+			sizeof(CONFIG_SYS_PROMPT) + 16)	/* Printbuffer size */
+#define CONFIG_SYS_MAXARGS		64
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE
+
+/*
+ * One partition type must be defined for part.c
+ * This is necessary for the fatls command to work on an SD card
+ * for example.
+ */
+#define CONFIG_DOS_PARTITION
+
+/* version string, parser, etc */
+#define CONFIG_VERSION_VARIABLE
+#define CONFIG_AUTO_COMPLETE
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_CMDLINE_EDITING
+#define CONFIG_SYS_LONGHELP
+
+#define CONFIG_CRC32_VERIFY
+#define CONFIG_MX_CYCLIC
+
+/* Initial upstream - boot to cmd prompt only */
+#define CONFIG_BOOTCOMMAND		""
+
+/* Commands */
+#include <config_cmd_default.h>
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_GPIO
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_MMC
+#define CONFIG_CMD_BOOTZ
+#define CONFIG_FAT_WRITE
+
+#undef CONFIG_CMD_NET
+#undef CONFIG_CMD_NFS
+
+#endif /* __BCM28155_AP_H */
diff --git a/include/configs/bct-brettl2.h b/include/configs/bct-brettl2.h
index ce09c2e138..06f095cc41 100644
--- a/include/configs/bct-brettl2.h
+++ b/include/configs/bct-brettl2.h
@@ -111,8 +111,8 @@
  * it linked after the configuration sector.
  */
 # define LDS_BOARD_TEXT \
-	arch/blackfin/lib/libblackfin.o (.text*); \
-	arch/blackfin/cpu/libblackfin.o (.text*); \
+	arch/blackfin/lib/built-in.o (.text*); \
+	arch/blackfin/cpu/built-in.o (.text*); \
 	. = DEFINED(env_offset) ? env_offset : .; \
 	common/env_embedded.o (.text*);
 #endif
@@ -136,7 +136,7 @@
 #define CONFIG_MTD_DEVICE
 #define CONFIG_MTD_PARTITIONS
 #define CONFIG_SYS_HUSH_PARSER
-
+#define CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED
 
 /*
  * Pull in common ADI header for remaining command/environment setup
diff --git a/include/configs/beaver.h b/include/configs/beaver.h
index 801caca24f..df9a98bca6 100644
--- a/include/configs/beaver.h
+++ b/include/configs/beaver.h
@@ -17,7 +17,7 @@
 #ifndef __CONFIG_H
 #define __CONFIG_H
 
-#include <asm/sizes.h>
+#include <linux/sizes.h>
 
 #include "tegra30-common.h"
 
diff --git a/include/configs/bf506f-ezkit.h b/include/configs/bf506f-ezkit.h
index 77b6735a70..eed2d5bcef 100644
--- a/include/configs/bf506f-ezkit.h
+++ b/include/configs/bf506f-ezkit.h
@@ -56,6 +56,7 @@
 /*
  * Flash Settings
  */
+
 #define CONFIG_FLASH_CFI_DRIVER
 #define CONFIG_SYS_FLASH_BASE		0x20000000
 #define CONFIG_SYS_FLASH_CFI
@@ -63,7 +64,9 @@
 #define CONFIG_SYS_MAX_FLASH_SECT	71
 #define CONFIG_CMD_FLASH
 #define CONFIG_MONITOR_IS_IN_RAM
-
+/*
+#define CONFIG_SYS_NO_FLASH
+*/
 
 /*
  * SPI Settings
@@ -71,11 +74,12 @@
 #define CONFIG_BFIN_SPI
 #define CONFIG_ENV_SPI_MAX_HZ	30000000
 #define CONFIG_SF_DEFAULT_SPEED	30000000
+/*
 #define CONFIG_SPI_FLASH
 #define CONFIG_SPI_FLASH_STMICRO
 #define CONFIG_CMD_SF
 #define CONFIG_CMD_SPI
-
+*/
 
 /*
  * Env Storage Settings
@@ -94,6 +98,7 @@
 #define CONFIG_DCACHE_OFF
 #define CONFIG_UART_CONSOLE	0
 #define CONFIG_BAUDRATE 115200
+#define CONFIG_BFIN_SERIAL
 
 #define CONFIG_CMD_MEMORY
 #undef CONFIG_GZIP
diff --git a/include/configs/bf518f-ezbrd.h b/include/configs/bf518f-ezbrd.h
index a97972b81c..9eb85ebf3d 100644
--- a/include/configs/bf518f-ezbrd.h
+++ b/include/configs/bf518f-ezbrd.h
@@ -155,7 +155,7 @@
 #define CONFIG_MISC_INIT_R
 #define CONFIG_RTC_BFIN
 #define CONFIG_UART_CONSOLE	0
-
+#define CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED
 
 /*
  * Pull in common ADI header for remaining command/environment setup
diff --git a/include/configs/bf525-ucr2.h b/include/configs/bf525-ucr2.h
index 1f65130f6c..008f4b5ec8 100644
--- a/include/configs/bf525-ucr2.h
+++ b/include/configs/bf525-ucr2.h
@@ -85,6 +85,7 @@
 #define CONFIG_UART_CONSOLE	0
 
 #define CONFIG_BAUDRATE		115200
+#define CONFIG_BFIN_SERIAL
 #define CONFIG_BOOTARGS		"root=/dev/mtdblock0 rw"
 #define CONFIG_BOOTCOMMAND	"run sfboot"
 #define CONFIG_BOOTDELAY	5
diff --git a/include/configs/bf526-ezbrd.h b/include/configs/bf526-ezbrd.h
index 003109329a..3065d22f0b 100644
--- a/include/configs/bf526-ezbrd.h
+++ b/include/configs/bf526-ezbrd.h
@@ -153,6 +153,7 @@
 #define CONFIG_MISC_INIT_R
 #define CONFIG_RTC_BFIN
 #define CONFIG_UART_CONSOLE	1
+#define CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED
 
 /* define to enable run status via led */
 /* #define CONFIG_STATUS_LED */
diff --git a/include/configs/bf527-ad7160-eval.h b/include/configs/bf527-ad7160-eval.h
index fa05103e5a..c0dfe2685b 100644
--- a/include/configs/bf527-ad7160-eval.h
+++ b/include/configs/bf527-ad7160-eval.h
@@ -136,7 +136,7 @@
  */
 #define CONFIG_MISC_INIT_R
 #define CONFIG_UART_CONSOLE	0
-
+#define CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED
 
 /*
  * Pull in common ADI header for remaining command/environment setup
diff --git a/include/configs/bf527-ezkit.h b/include/configs/bf527-ezkit.h
index db1b6136f3..748ddb3b15 100644
--- a/include/configs/bf527-ezkit.h
+++ b/include/configs/bf527-ezkit.h
@@ -179,7 +179,7 @@
 #define CONFIG_MISC_INIT_R
 #define CONFIG_RTC_BFIN
 #define CONFIG_UART_CONSOLE	1
-
+#define CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED
 
 /*
  * Pull in common ADI header for remaining command/environment setup
diff --git a/include/configs/bf527-sdp.h b/include/configs/bf527-sdp.h
index c0e8b5adc8..458868af72 100644
--- a/include/configs/bf527-sdp.h
+++ b/include/configs/bf527-sdp.h
@@ -112,7 +112,7 @@
  */
 #define CONFIG_MISC_INIT_R
 #define CONFIG_UART_CONSOLE	0
-
+#define CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED
 
 /*
  * Pull in common ADI header for remaining command/environment setup
diff --git a/include/configs/bf533-ezkit.h b/include/configs/bf533-ezkit.h
index beab1271a4..b50352823e 100644
--- a/include/configs/bf533-ezkit.h
+++ b/include/configs/bf533-ezkit.h
@@ -110,7 +110,7 @@
 #define CONFIG_MISC_INIT_R
 #define CONFIG_RTC_BFIN
 #define CONFIG_UART_CONSOLE	0
-
+#define CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED
 
 /*
  * Pull in common ADI header for remaining command/environment setup
diff --git a/include/configs/bf533-stamp.h b/include/configs/bf533-stamp.h
index 7144c6319f..d82c5b203d 100644
--- a/include/configs/bf533-stamp.h
+++ b/include/configs/bf533-stamp.h
@@ -80,33 +80,8 @@
 /*
  * Software (bit-bang) I2C driver configuration
  */
-#define PF_SCL			PF3
-#define PF_SDA			PF2
-#define I2C_INIT		(*pFIO_DIR |=  PF_SCL); asm("ssync;")
-#define I2C_ACTIVE		(*pFIO_DIR |=  PF_SDA); \
-				*pFIO_INEN &= ~PF_SDA; asm("ssync;")
-#define I2C_TRISTATE		(*pFIO_DIR &= ~PF_SDA); \
-				*pFIO_INEN |= PF_SDA; asm("ssync;")
-#define I2C_READ		((volatile)(*pFIO_FLAG_D & PF_SDA) != 0); \
-				asm("ssync;")
-#define I2C_SDA(bit)	if (bit) { \
-				*pFIO_FLAG_S = PF_SDA; \
-				asm("ssync;"); \
-				} \
-			else	{ \
-				*pFIO_FLAG_C = PF_SDA; \
-				asm("ssync;"); \
-				}
-#define I2C_SCL(bit)	if (bit) { \
-				*pFIO_FLAG_S = PF_SCL; \
-				asm("ssync;"); \
-				} \
-			else	{ \
-				*pFIO_FLAG_C = PF_SCL; \
-				asm("ssync;"); \
-				}
-#define I2C_DELAY		udelay(5)	/* 1/4 I2C clock duration */
-
+#define CONFIG_SOFT_I2C_GPIO_SCL	GPIO_PF3
+#define CONFIG_SOFT_I2C_GPIO_SDA	GPIO_PF2
 
 /*
  * Flash Settings
@@ -155,8 +130,8 @@
  * it linked after the configuration sector.
  */
 # define LDS_BOARD_TEXT \
-	arch/blackfin/lib/libblackfin.o (.text*); \
-	arch/blackfin/cpu/libblackfin.o (.text*); \
+	arch/blackfin/lib/built-in.o (.text*); \
+	arch/blackfin/cpu/built-in.o (.text*); \
 	. = DEFINED(env_offset) ? env_offset : .; \
 	common/env_embedded.o (.text*);
 #endif
@@ -210,6 +185,7 @@
  */
 #define CONFIG_RTC_BFIN
 #define CONFIG_UART_CONSOLE	0
+#define CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED
 
 /* FLASH/ETHERNET uses the same async bank */
 #define SHARED_RESOURCES 	1
diff --git a/include/configs/bf537-minotaur.h b/include/configs/bf537-minotaur.h
index feb9d7344a..156eeabb06 100644
--- a/include/configs/bf537-minotaur.h
+++ b/include/configs/bf537-minotaur.h
@@ -136,6 +136,7 @@
 
 #define CONFIG_BAUDRATE		57600
 #define CONFIG_UART_CONSOLE	0
+#define CONFIG_BFIN_SERIAL
 
 #define CONFIG_PANIC_HANG	1
 #define CONFIG_RTC_BFIN		1
diff --git a/include/configs/bf537-pnav.h b/include/configs/bf537-pnav.h
index 62bd3bf085..3aa3d50a89 100644
--- a/include/configs/bf537-pnav.h
+++ b/include/configs/bf537-pnav.h
@@ -111,8 +111,8 @@
  * it linked after the configuration sector.
  */
 # define LDS_BOARD_TEXT \
-	arch/blackfin/lib/libblackfin.o (.text*); \
-	arch/blackfin/cpu/libblackfin.o (.text*); \
+	arch/blackfin/lib/built-in.o (.text*); \
+	arch/blackfin/cpu/built-in.o (.text*); \
 	. = DEFINED(env_offset) ? env_offset : .; \
 	common/env_embedded.o (.text*);
 #endif
diff --git a/include/configs/bf537-srv1.h b/include/configs/bf537-srv1.h
index 1de8ffe2df..e12d761a24 100644
--- a/include/configs/bf537-srv1.h
+++ b/include/configs/bf537-srv1.h
@@ -136,6 +136,7 @@
 
 #define CONFIG_BAUDRATE		115200
 #define CONFIG_UART_CONSOLE	0
+#define CONFIG_BFIN_SERIAL
 
 #define CONFIG_PANIC_HANG	1
 #define CONFIG_RTC_BFIN		1
diff --git a/include/configs/bf537-stamp.h b/include/configs/bf537-stamp.h
index 25cebf880f..e1705cadae 100644
--- a/include/configs/bf537-stamp.h
+++ b/include/configs/bf537-stamp.h
@@ -118,8 +118,8 @@
  * it linked after the configuration sector.
  */
 # define LDS_BOARD_TEXT \
-	arch/blackfin/lib/libblackfin.o (.text*); \
-	arch/blackfin/cpu/libblackfin.o (.text*); \
+	arch/blackfin/lib/built-in.o (.text*); \
+	arch/blackfin/cpu/built-in.o (.text*); \
 	. = DEFINED(env_offset) ? env_offset : .; \
 	common/env_embedded.o (.text*);
 #endif
@@ -254,6 +254,7 @@
 #define CONFIG_MISC_INIT_R
 #define CONFIG_RTC_BFIN
 #define CONFIG_UART_CONSOLE	0
+#define CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED
 
 /* Define if want to do post memory test */
 #undef CONFIG_POST
diff --git a/include/configs/bf538f-ezkit.h b/include/configs/bf538f-ezkit.h
index 77822e792f..742c299d23 100644
--- a/include/configs/bf538f-ezkit.h
+++ b/include/configs/bf538f-ezkit.h
@@ -115,8 +115,8 @@
  * it linked after the configuration sector.
  */
 # define LDS_BOARD_TEXT \
-	arch/blackfin/lib/libblackfin.o (.text*); \
-	arch/blackfin/cpu/libblackfin.o (.text*); \
+	arch/blackfin/lib/built-in.o (.text*); \
+	arch/blackfin/cpu/built-in.o (.text*); \
 	. = DEFINED(env_offset) ? env_offset : .; \
 	common/env_embedded.o (.text*);
 #endif
@@ -134,7 +134,7 @@
  */
 #define CONFIG_RTC_BFIN
 #define CONFIG_UART_CONSOLE	0
-
+#define CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED
 
 /*
  * Pull in common ADI header for remaining command/environment setup
diff --git a/include/configs/bf548-ezkit.h b/include/configs/bf548-ezkit.h
index da5f029435..1a245a2b81 100644
--- a/include/configs/bf548-ezkit.h
+++ b/include/configs/bf548-ezkit.h
@@ -181,6 +181,7 @@
 #define CONFIG_RTC_BFIN
 #define CONFIG_UART_CONSOLE	1
 #define CONFIG_BFIN_SPI_IMG_SIZE 0x50000
+#define CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED
 
 #define CONFIG_ADI_GPIO2
 
diff --git a/include/configs/bf561-acvilon.h b/include/configs/bf561-acvilon.h
index ee585c0ffd..3db917e37b 100644
--- a/include/configs/bf561-acvilon.h
+++ b/include/configs/bf561-acvilon.h
@@ -53,7 +53,7 @@
 #define CONFIG_EBIU_AMBCTL0_VAL		0xffc2ffc2
 #define CONFIG_EBIU_AMBCTL1_VAL		0x99b35554
 
-#define CONFIG_SYS_MONITOR_LEN		(256 * 1024)
+#define CONFIG_SYS_MONITOR_LEN		(384 * 1024)
 #define CONFIG_SYS_MALLOC_LEN		(128 * 1024)
 
 
@@ -160,7 +160,7 @@
 #define CONFIG_UART_CONSOLE			0
 #define CONFIG_BAUDRATE				57600
 #define CONFIG_SYS_PROMPT "Acvilon> "
-
+#define CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED
 
 /*
  * Pull in common ADI header for remaining command/environment setup
diff --git a/include/configs/bf561-ezkit.h b/include/configs/bf561-ezkit.h
index 404039ac23..0a309d9269 100644
--- a/include/configs/bf561-ezkit.h
+++ b/include/configs/bf561-ezkit.h
@@ -90,6 +90,7 @@
  */
 #define CONFIG_SYS_I2C_SOFT
 #ifdef CONFIG_SYS_I2C_SOFT
+#define CONFIG_SYS_I2C
 #define CONFIG_SOFT_I2C_GPIO_SCL GPIO_PF0
 #define CONFIG_SOFT_I2C_GPIO_SDA GPIO_PF1
 #define I2C_DELAY		udelay(5)	/* 1/4 I2C clock duration */
@@ -101,6 +102,7 @@
  * Misc Settings
  */
 #define CONFIG_UART_CONSOLE	0
+#define CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED
 
 /*
  * Run core 1 from L1 SRAM start address when init uboot on core 0
diff --git a/include/configs/bf609-ezkit.h b/include/configs/bf609-ezkit.h
index 1a43e1b433..12192ffb5d 100644
--- a/include/configs/bf609-ezkit.h
+++ b/include/configs/bf609-ezkit.h
@@ -72,12 +72,13 @@
 #define CONFIG_NET_MULTI
 #define CONFIG_HOSTNAME		"bf609-ezkit"
 #define CONFIG_DESIGNWARE_ETH
+#define CONFIG_PHY_ADDR		1
 #define CONFIG_DW_PORTS		1
-#define CONFIG_DW_AUTONEG
 #define CONFIG_DW_ALTDESCRIPTOR
 #define CONFIG_CMD_NET
 #define CONFIG_CMD_MII
 #define CONFIG_MII
+#define CONFIG_PHYLIB
 
 /* i2c Settings */
 #define CONFIG_BFIN_TWI_I2C
diff --git a/include/configs/bfin_adi_common.h b/include/configs/bfin_adi_common.h
index 08ccce0b9a..ea9acf69d1 100644
--- a/include/configs/bfin_adi_common.h
+++ b/include/configs/bfin_adi_common.h
@@ -17,6 +17,7 @@
 #  define CONFIG_BOOTP_DNS
 #  define CONFIG_BOOTP_NTPSERVER
 #  define CONFIG_BOOTP_RANDOM_DELAY
+#  define CONFIG_LIB_RAND
 #  define CONFIG_KEEP_SERVERADDR
 #  define CONFIG_CMD_DNS
 #  define CONFIG_CMD_PING
diff --git a/include/configs/bg0900.h b/include/configs/bg0900.h
new file mode 100644
index 0000000000..507d972f34
--- /dev/null
+++ b/include/configs/bg0900.h
@@ -0,0 +1,97 @@
+/*
+ * Copyright (C) 2013 Marek Vasut <marex@denx.de>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+#ifndef __CONFIGS_BG0900_H__
+#define __CONFIGS_BG0900_H__
+
+/* System configurations */
+#define CONFIG_MX28				/* i.MX28 SoC */
+
+/* U-Boot Commands */
+#define CONFIG_SYS_NO_FLASH
+#include <config_cmd_default.h>
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DOS_PARTITION
+
+#define CONFIG_CMD_BOOTZ
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_GPIO
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NAND
+#define CONFIG_CMD_NAND_TRIMFFS
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_SAVEENV
+#define CONFIG_CMD_SETEXPR
+#define CONFIG_CMD_SF
+#define CONFIG_CMD_SPI
+
+/* Memory configuration */
+#define CONFIG_NR_DRAM_BANKS		1		/* 1 bank of DRAM */
+#define PHYS_SDRAM_1			0x40000000	/* Base address */
+#define PHYS_SDRAM_1_SIZE		0x10000000	/* Max 256 MB RAM */
+#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
+
+/* Environment */
+#define CONFIG_ENV_SIZE			(16 * 1024)
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_ENV_IS_NOWHERE
+
+/* FEC Ethernet on SoC */
+#ifdef	CONFIG_CMD_NET
+#define CONFIG_FEC_MXC
+#define CONFIG_NET_MULTI
+#endif
+
+/* SPI */
+#ifdef CONFIG_CMD_SPI
+#define CONFIG_DEFAULT_SPI_BUS		2
+#define CONFIG_DEFAULT_SPI_CS		0
+#define CONFIG_DEFAULT_SPI_MODE		SPI_MODE_0
+
+/* SPI FLASH */
+#ifdef CONFIG_CMD_SF
+#define CONFIG_SPI_FLASH
+#define CONFIG_SPI_FLASH_BAR
+#define CONFIG_SPI_FLASH_STMICRO
+#define CONFIG_SF_DEFAULT_BUS		2
+#define CONFIG_SF_DEFAULT_CS		0
+#define CONFIG_SF_DEFAULT_SPEED		40000000
+#define CONFIG_SF_DEFAULT_MODE		SPI_MODE_0
+
+#define CONFIG_ENV_SPI_BUS		2
+#define CONFIG_ENV_SPI_CS		0
+#define CONFIG_ENV_SPI_MAX_HZ		40000000
+#define CONFIG_ENV_SPI_MODE		SPI_MODE_0
+#endif
+
+#endif
+
+/* Boot Linux */
+#define CONFIG_BOOTDELAY	3
+#define CONFIG_BOOTFILE		"uImage"
+#define CONFIG_BOOTARGS		"console=ttyAMA0,115200"
+#define CONFIG_BOOTCOMMAND	"bootm"
+#define CONFIG_LOADADDR		0x42000000
+#define CONFIG_SYS_LOAD_ADDR	CONFIG_LOADADDR
+
+/* Extra Environment */
+#define CONFIG_EXTRA_ENV_SETTINGS					\
+	"update_spi_firmware_filename=u-boot.sb\0"			\
+	"update_spi_firmware_maxsz=0x80000\0"				\
+	"update_spi_firmware="	/* Update the SPI flash firmware */	\
+		"if sf probe 2:0 ; then "				\
+		"if tftp ${update_spi_firmware_filename} ; then "	\
+		"sf erase 0x0 +${filesize} ; "				\
+		"sf write ${loadaddr} 0x0 ${filesize} ; "		\
+		"fi ; "							\
+		"fi\0"
+
+/* The rest of the configuration is shared */
+#include <configs/mxs.h>
+
+#endif /* __CONFIGS_BG0900_H__ */
diff --git a/include/configs/blackstamp.h b/include/configs/blackstamp.h
index 5b3aac7954..7de425349f 100644
--- a/include/configs/blackstamp.h
+++ b/include/configs/blackstamp.h
@@ -195,6 +195,7 @@
 #define CONFIG_BAUDRATE		57600
 #define CONFIG_LOADS_ECHO	1
 #define CONFIG_UART_CONSOLE	0
+#define CONFIG_BFIN_SERIAL
 
 /*
  * I2C settings
diff --git a/include/configs/blackvme.h b/include/configs/blackvme.h
index cd37f9adb9..6e5774c6ba 100644
--- a/include/configs/blackvme.h
+++ b/include/configs/blackvme.h
@@ -177,6 +177,7 @@
 #define CONFIG_BAUDRATE		57600
 #define CONFIG_LOADS_ECHO	1
 #define CONFIG_UART_CONSOLE	0
+#define CONFIG_BFIN_SERIAL
 
 /*
  * U-Boot environment variables. Use "printenv" to examine.
diff --git a/include/configs/bluestone.h b/include/configs/bluestone.h
index 33e04963e6..8bd71c6a15 100644
--- a/include/configs/bluestone.h
+++ b/include/configs/bluestone.h
@@ -16,7 +16,6 @@
 #define CONFIG_APM821XX		1	/* APM821XX series    */
 #define CONFIG_HOSTNAME		bluestone
 
-#define CONFIG_4xx		1	/* ... PPC4xx family */
 #define CONFIG_440		1
 
 #ifndef CONFIG_SYS_TEXT_BASE
diff --git a/include/configs/br4.h b/include/configs/br4.h
index ef3752dcd5..f8d3158d47 100644
--- a/include/configs/br4.h
+++ b/include/configs/br4.h
@@ -135,7 +135,7 @@
 #define CONFIG_BOOTCOMMAND	"run nandboot"
 #define CONFIG_BOOTDELAY	2
 #define CONFIG_LOADADDR		0x2000000
-
+#define CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED
 
 /*
  * Pull in common ADI header for remaining command/environment setup
diff --git a/include/configs/bubinga.h b/include/configs/bubinga.h
index 2b9c1c96e4..ea7b104729 100644
--- a/include/configs/bubinga.h
+++ b/include/configs/bubinga.h
@@ -18,7 +18,6 @@
  */
 
 #define CONFIG_405EP		1	/* This is a PPC405 CPU		*/
-#define CONFIG_4xx		1	/* ...member of PPC4xx family   */
 #define CONFIG_BUBINGA	        1	/* ...on a BUBINGA board	*/
 
 #define	CONFIG_SYS_TEXT_BASE	0xFFFC0000
diff --git a/include/configs/bur_am335x_common.h b/include/configs/bur_am335x_common.h
new file mode 100644
index 0000000000..7adc8c0fd7
--- /dev/null
+++ b/include/configs/bur_am335x_common.h
@@ -0,0 +1,196 @@
+/*
+ * bur_am335x_common.h
+ *
+ * common parts used by B&R AM335x based boards
+ *
+ * Copyright (C) 2013 Hannes Petermaier <oe5hpm@oevsv.at> -
+ * Bernecker & Rainer Industrieelektronik GmbH - http://www.br-automation.com
+ *
+ * SPDX-License-Identifier:        GPL-2.0+
+ */
+
+#ifndef __BUR_AM335X_COMMON_H__
+#define __BUR_AM335X_COMMON_H__
+/* ------------------------------------------------------------------------- */
+#define CONFIG_AM33XX
+#define CONFIG_OMAP
+#define CONFIG_OMAP_COMMON
+#define CONFIG_BOARD_LATE_INIT
+#define CONFIG_SYS_CACHELINE_SIZE	64
+#define CONFIG_MAX_RAM_BANK_SIZE	(1024 << 20)	/* 1GB */
+
+/* Timer information */
+#define CONFIG_SYS_PTV			2	/* Divisor: 2^(PTV+1) => 8 */
+#define CONFIG_SYS_TIMERBASE		0x48040000	/* Use Timer2 */
+#define CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC	/* enable 32kHz OSC at bootime */
+#define CONFIG_SPL_POWER_SUPPORT
+#define CONFIG_POWER_TPS65217
+
+#define CONFIG_SYS_NO_FLASH		/* have no NOR-flash */
+
+#include <asm/arch/omap.h>
+
+/* NS16550 Configuration */
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	(-4)
+#define CONFIG_SYS_NS16550_CLK		48000000
+#define CONFIG_SYS_NS16550_COM1		0x44e09000	/* UART0 */
+#define CONFIG_BAUDRATE			115200
+
+/* Network defines */
+#define CONFIG_CMD_NET			/* 'bootp' and 'tftp' */
+#define CONFIG_CMD_DHCP
+#define CONFIG_BOOTP_DNS		/* Configurable parts of CMD_DHCP */
+#define CONFIG_BOOTP_SEND_HOSTNAME
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_NET_RETRY_COUNT		4
+#define CONFIG_CMD_PING
+#define CONFIG_DRIVER_TI_CPSW		/* Driver for IP block */
+#define CONFIG_MII			/* Required in net/eth.c */
+#define CONFIG_SPL_ETH_SUPPORT
+#define CONFIG_PHYLIB
+#define CONFIG_PHY_NATSEMI
+#define CONFIG_SPL_NET_SUPPORT
+#define CONFIG_SPL_ENV_SUPPORT		/* used for a fetching MAC-Address */
+#define CONFIG_SPL_NET_VCI_STRING	"AM335x U-Boot SPL"
+
+/*
+ * SPL related defines.  The Public RAM memory map the ROM defines the
+ * area between 0x402F0400 and 0x4030B800 as a download area and
+ * 0x4030B800 to 0x4030CE00 as a public stack area.  The ROM also
+ * supports X-MODEM loading via UART, and we leverage this and then use
+ * Y-MODEM to load u-boot.img, when booted over UART.
+ */
+#define CONFIG_SPL_TEXT_BASE		0x402F0400
+#define CONFIG_SPL_MAX_SIZE		(0x4030B800 - CONFIG_SPL_TEXT_BASE)
+
+/*
+ * Since SPL did pll and ddr initialization for us,
+ * we don't need to do it twice.
+ */
+#if !defined(CONFIG_SPL_BUILD) && !defined(CONFIG_NOR_BOOT)
+#define CONFIG_SKIP_LOWLEVEL_INIT
+#endif /* !CONFIG_SPL_BUILD, ... */
+/*
+ * Our DDR memory always starts at 0x80000000 and U-Boot shall have
+ * relocated itself to higher in memory by the time this value is used.
+ */
+#define CONFIG_SYS_LOAD_ADDR		0x80000000
+/*
+ * ----------------------------------------------------------------------------
+ * DDR information.  We say (for simplicity) that we have 1 bank,
+ * always, even when we have more.  We always start at 0x80000000,
+ * and we place the initial stack pointer in our SRAM.
+ */
+#define CONFIG_NR_DRAM_BANKS		1
+#define CONFIG_SYS_SDRAM_BASE		0x80000000
+#define CONFIG_SYS_INIT_SP_ADDR		(NON_SECURE_SRAM_END - \
+					GENERATED_GBL_DATA_SIZE)
+
+/* I2C */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_OMAP24_I2C_SPEED	100000
+#define CONFIG_SYS_OMAP24_I2C_SLAVE	1
+#define CONFIG_SYS_I2C_OMAP24XX
+
+/* GPIO */
+#define CONFIG_OMAP_GPIO
+#define CONFIG_CMD_GPIO
+/*
+ * ----------------------------------------------------------------------------
+ * The following are general good-enough settings for U-Boot.  We set a
+ * large malloc pool as we generally have a lot of DDR, and we opt for
+ * function over binary size in the main portion of U-Boot as this is
+ * generally easily constrained later if needed.  We enable the config
+ * options that give us information in the environment about what board
+ * we are on so we do not need to rely on the command prompt.  We set a
+ * console baudrate of 115200 and use the default baud rate table.
+ */
+#define CONFIG_SYS_MALLOC_LEN		(1024 << 10)
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT		"U-Boot (BuR V2.0)# "
+#define CONFIG_SYS_CONSOLE_INFO_QUIET
+#define CONFIG_ENV_OVERWRITE		/* Overwrite ethaddr / serial# */
+
+/* As stated above, the following choices are optional. */
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_AUTO_COMPLETE
+#define CONFIG_CMDLINE_EDITING
+#define CONFIG_VERSION_VARIABLE
+
+/* We set the max number of command args high to avoid HUSH bugs. */
+#define CONFIG_SYS_MAXARGS		64
+
+/* Console I/O Buffer Size */
+#define CONFIG_SYS_CBSIZE		512
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE +\
+					sizeof(CONFIG_SYS_PROMPT) + 16)
+/* Boot Argument Buffer Size */
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE
+/*
+ * For commands to use, we take the default list and add a few other
+ * useful commands.  Note that we must have set CONFIG_SYS_NO_FLASH
+ * prior to this include, in order to skip a few commands.  When we do
+ * have flash, if we expect these commands they must be enabled in that
+ * config.  If desired, a specific list of desired commands can be used
+ * instead.
+ */
+#include <config_cmd_default.h>
+/* undefine commands, which we do not need */
+#undef CONFIG_CMD_EDITENV
+#undef CONFIG_CMD_FPGA
+#undef CONFIG_CMD_IMI
+#undef CONFIG_CMD_ITEST
+#undef CONFIG_CMD_LOADS
+#undef CONFIG_CMD_LOADB
+#undef CONFIG_CMD_NFS
+#undef CONFIG_CMD_SETGETDCR
+#undef CONFIG_CMD_XIMG
+#undef CONFIG_CMD_CRC32
+/* define command we need always */
+#define CONFIG_CMD_ECHO
+#define CONFIG_CMD_SOURCE
+
+/*
+ * Our platforms make use of SPL to initalize the hardware (primarily
+ * memory) enough for full U-Boot to be loaded.  We also support Falcon
+ * Mode so that the Linux kernel can be booted directly from SPL
+ * instead, if desired.  We make use of the general SPL framework found
+ * under common/spl/.  Given our generally common memory map, we set a
+ * number of related defaults and sizes here.
+ */
+#define CONFIG_SPL
+#define CONFIG_SPL_FRAMEWORK
+/*
+ * Place the image at the start of the ROM defined image space.
+ * We limit our size to the ROM-defined downloaded image area, and use the
+ * rest of the space for stack.  We load U-Boot itself into memory at
+ * 0x80800000 for legacy reasons (to not conflict with older SPLs).  We
+ * have our BSS be placed 1MiB after this, to allow for the default
+ * Linux kernel address of 0x80008000 to work, in the Falcon Mode case.
+ * We have the SPL malloc pool at the end of the BSS area.
+ *
+ * ----------------------------------------------------------------------------
+ */
+#define CONFIG_SPL_STACK		CONFIG_SYS_INIT_SP_ADDR
+#undef  CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_TEXT_BASE		0x80800000
+#define CONFIG_SPL_BSS_START_ADDR	0x80A00000
+#define CONFIG_SPL_BSS_MAX_SIZE		0x80000		/* 512 KB */
+#define CONFIG_SYS_SPL_MALLOC_START	(CONFIG_SPL_BSS_START_ADDR + \
+					CONFIG_SPL_BSS_MAX_SIZE)
+#define CONFIG_SYS_SPL_MALLOC_SIZE	CONFIG_SYS_MALLOC_LEN
+
+/* General parts of the framework, required. */
+#define CONFIG_SPL_I2C_SUPPORT
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+#define CONFIG_SPL_LIBGENERIC_SUPPORT
+#define CONFIG_SPL_SERIAL_SUPPORT
+#define CONFIG_SPL_BOARD_INIT
+#define CONFIG_SPL_YMODEM_SUPPORT
+#define CONFIG_SPL_LDSCRIPT		"$(CPUDIR)/am33xx/u-boot-spl.lds"
+
+#endif	/* ! __BUR_AM335X_COMMON_H__ */
diff --git a/include/configs/calimain.h b/include/configs/calimain.h
index d20074c731..febee45b3b 100644
--- a/include/configs/calimain.h
+++ b/include/configs/calimain.h
@@ -31,7 +31,6 @@
 #define CONFIG_SYS_OSCIN_FREQ		calimain_get_osc_freq()
 #define CONFIG_SYS_TIMERBASE		DAVINCI_TIMER0_BASE
 #define CONFIG_SYS_HZ_CLOCK		clk_get(DAVINCI_AUXCLK_CLKID)
-#define CONFIG_SYS_HZ			1000
 #define CONFIG_SYS_TEXT_BASE		0x60000000
 #define CONFIG_DA850_LOWLEVEL
 #define CONFIG_SYS_DA850_PLL_INIT
diff --git a/include/configs/cam_enc_4xx.h b/include/configs/cam_enc_4xx.h
index 2e024f54a9..8182a7577b 100644
--- a/include/configs/cam_enc_4xx.h
+++ b/include/configs/cam_enc_4xx.h
@@ -17,7 +17,6 @@
 #define CONFIG_ARM926EJS				/* arm926ejs CPU */
 #define CONFIG_SYS_TIMERBASE		0x01c21400	/* use timer 0 */
 #define CONFIG_SYS_HZ_CLOCK		24000000	/* timer0 freq */
-#define CONFIG_SYS_HZ			1000
 #define CONFIG_SOC_DM365
 
 #define CONFIG_MACH_TYPE	MACH_TYPE_DAVINCI_DM365_EVM
@@ -237,6 +236,8 @@
 #define CONFIG_SYS_NAND_BAD_BLOCK_POS	0
 #define CONFIG_SYS_NAND_ECCSIZE		0x200
 #define CONFIG_SYS_NAND_ECCBYTES	10
+#define CONFIG_SYS_NAND_MAX_OOBFREE	2
+#define CONFIG_SYS_NAND_MAX_ECCPOS	56
 #define CONFIG_SYS_NAND_OOBSIZE		64
 #define CONFIG_SYS_NAND_5_ADDR_CYCLE
 
diff --git a/include/configs/canmb.h b/include/configs/canmb.h
index 485bf1658e..c90179380f 100644
--- a/include/configs/canmb.h
+++ b/include/configs/canmb.h
@@ -13,8 +13,7 @@
  * (easy to change)
  */
 
-#define CONFIG_MPC5xxx		1	/* This is an MPC5xxx CPU */
-#define CONFIG_MPC5200		1	/* More exactly a MPC5200 */
+#define CONFIG_MPC5200		1	/* This is a MPC5200 CPU */
 #define CONFIG_CANMB		1	/* ... on canmb board - we need this for FEC.C */
 
 /*
@@ -174,7 +173,6 @@
  * Miscellaneous configurable options
  */
 #define CONFIG_SYS_LONGHELP			/* undef to save memory	    */
-#define CONFIG_SYS_PROMPT		"=> "	/* Monitor Command Prompt   */
 #if defined(CONFIG_CMD_KGDB)
 #  define CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size  */
 #else
@@ -189,8 +187,6 @@
 
 #define CONFIG_SYS_LOAD_ADDR		0x200000	/* default load address */
 
-#define CONFIG_SYS_HZ			1000	/* decrementer freq: 1 ms ticks */
-
 #define CONFIG_RTC_MPC5200	1	/* use internal MPC5200 RTC */
 
 #define CONFIG_SYS_CACHELINE_SIZE	32	/* For MPC5xxx CPUs */
diff --git a/include/configs/canyonlands.h b/include/configs/canyonlands.h
index f6faeec06c..8eeb15c0e1 100644
--- a/include/configs/canyonlands.h
+++ b/include/configs/canyonlands.h
@@ -33,7 +33,6 @@
 #endif
 
 #define CONFIG_440		1
-#define CONFIG_4xx		1	/* ... PPC4xx family */
 
 #ifndef CONFIG_SYS_TEXT_BASE
 #define CONFIG_SYS_TEXT_BASE	0xFFF80000
@@ -126,78 +125,9 @@
 /*
  * Define here the location of the environment variables (FLASH).
  */
-#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
 #define	CONFIG_ENV_IS_IN_FLASH	1	/* use FLASH for environment vars */
 #define CONFIG_SYS_NOR_CS		0	/* NOR chip connected to CSx */
 #define CONFIG_SYS_NAND_CS		3	/* NAND chip connected to CSx */
-#else
-#define	CONFIG_ENV_IS_IN_NAND	1	/* use NAND for environment vars  */
-#define CONFIG_SYS_NOR_CS		3	/* NOR chip connected to CSx */
-#define CONFIG_SYS_NAND_CS		0	/* NAND chip connected to CSx */
-#define CONFIG_ENV_IS_EMBEDDED	1	/* use embedded environment */
-#endif
-
-/*
- * IPL (Initial Program Loader, integrated inside CPU)
- * Will load first 4k from NAND (SPL) into cache and execute it from there.
- *
- * SPL (Secondary Program Loader)
- * Will load special U-Boot version (NUB) from NAND and execute it. This SPL
- * has to fit into 4kByte. It sets up the CPU and configures the SDRAM
- * controller and the NAND controller so that the special U-Boot image can be
- * loaded from NAND to SDRAM.
- *
- * NUB (NAND U-Boot)
- * This NAND U-Boot (NUB) is a special U-Boot version which can be started
- * from RAM. Therefore it mustn't (re-)configure the SDRAM controller.
- *
- * On 440EPx the SPL is copied to SDRAM before the NAND controller is
- * set up. While still running from cache, I experienced problems accessing
- * the NAND controller.	sr - 2006-08-25
- *
- * This is the first official implementation of booting from 2k page sized
- * NAND devices (e.g. Micron 29F2G08AA 256Mbit * 8)
- */
-#define CONFIG_SYS_NAND_BOOT_SPL_SRC	0xfffff000	/* SPL location		      */
-#define CONFIG_SYS_NAND_BOOT_SPL_SIZE	(4 << 10)	/* SPL size		      */
-#define CONFIG_SYS_NAND_BOOT_SPL_DST	(CONFIG_SYS_OCM_BASE + (12 << 10)) /* Copy SPL here  */
-#define CONFIG_SYS_NAND_U_BOOT_DST	0x01000000	/* Load NUB to this addr      */
-#define CONFIG_SYS_NAND_U_BOOT_START	CONFIG_SYS_NAND_U_BOOT_DST	/* Start NUB from     */
-							/*   this addr	      */
-#define CONFIG_SYS_NAND_BOOT_SPL_DELTA	(CONFIG_SYS_NAND_BOOT_SPL_SRC - CONFIG_SYS_NAND_BOOT_SPL_DST)
-
-/*
- * Define the partitioning of the NAND chip (only RAM U-Boot is needed here)
- */
-#define CONFIG_SYS_NAND_U_BOOT_OFFS	(128 << 10)	/* Offset to RAM U-Boot image */
-#define CONFIG_SYS_NAND_U_BOOT_SIZE	(1 << 20)	/* Size of RAM U-Boot image   */
-
-/*
- * Now the NAND chip has to be defined (no autodetection used!)
- */
-#define CONFIG_SYS_NAND_PAGE_SIZE	(2 << 10)	/* NAND chip page size	      */
-#define CONFIG_SYS_NAND_BLOCK_SIZE	(128 << 10)	/* NAND chip block size	      */
-#define CONFIG_SYS_NAND_PAGE_COUNT	(CONFIG_SYS_NAND_BLOCK_SIZE / CONFIG_SYS_NAND_PAGE_SIZE)
-						/* NAND chip page count	      */
-#define CONFIG_SYS_NAND_BAD_BLOCK_POS	0		/* Location of bad block marker*/
-#define CONFIG_SYS_NAND_5_ADDR_CYCLE			/* Fifth addr used (<=128MB)  */
-
-#define CONFIG_SYS_NAND_ECCSIZE	256
-#define CONFIG_SYS_NAND_ECCBYTES	3
-#define CONFIG_SYS_NAND_OOBSIZE	64
-#define CONFIG_SYS_NAND_ECCPOS		{40, 41, 42, 43, 44, 45, 46, 47, \
-				 48, 49, 50, 51, 52, 53, 54, 55, \
-				 56, 57, 58, 59, 60, 61, 62, 63}
-
-#ifdef CONFIG_ENV_IS_IN_NAND
-/*
- * For NAND booting the environment is embedded in the U-Boot image. Please take
- * look at the file board/amcc/canyonlands/u-boot-nand.lds for details.
- */
-#define CONFIG_ENV_SIZE		CONFIG_SYS_NAND_BLOCK_SIZE
-#define CONFIG_ENV_OFFSET		(CONFIG_SYS_NAND_U_BOOT_OFFS + CONFIG_ENV_SIZE)
-#define CONFIG_ENV_OFFSET_REDUND	(CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
-#endif
 
 /*-----------------------------------------------------------------------
  * FLASH related
@@ -236,7 +166,6 @@
 /*------------------------------------------------------------------------------
  * DDR SDRAM
  *----------------------------------------------------------------------------*/
-#if !defined(CONFIG_NAND_U_BOOT)
 #if !defined(CONFIG_ARCHES)
 /*
  * NAND booting U-Boot version uses a fixed initialization, since the whole
@@ -309,7 +238,6 @@
 #define CONFIG_SYS_SDRAM0_MMODE		0x00000432
 #define CONFIG_SYS_SDRAM0_MEMODE	0x00000004
 #endif	/* !defined(CONFIG_ARCHES) */
-#endif	/* !defined(CONFIG_NAND_U_BOOT) */
 
 #define CONFIG_SYS_MBYTES_SDRAM	512	/* 512MB			*/
 
@@ -422,7 +350,6 @@
 	CONFIG_AMCC_DEF_ENV						\
 	CONFIG_AMCC_DEF_ENV_POWERPC					\
 	CONFIG_AMCC_DEF_ENV_NOR_UPD					\
-	CONFIG_AMCC_DEF_ENV_NAND_UPD					\
 	"kernel_addr=fc000000\0"					\
 	"fdt_addr=fc1e0000\0"						\
 	"ramdisk_addr=fc200000\0"					\
@@ -557,15 +484,6 @@
  * 0xfe00.0000 -> 4.ce00.0000
  */
 
-#if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
-/* Memory Bank 3 (NOR-FLASH) initialization					*/
-#define CONFIG_SYS_EBC_PB3AP		0x10055e00
-#define CONFIG_SYS_EBC_PB3CR		(CONFIG_SYS_BOOT_BASE_ADDR | 0x9a000)
-
-/* Memory Bank 0 (NAND-FLASH) initialization						*/
-#define CONFIG_SYS_EBC_PB0AP		0x018003c0
-#define CONFIG_SYS_EBC_PB0CR		(CONFIG_SYS_NAND_ADDR | 0x1E000) /* BAS=NAND,BS=1MB,BU=R/W,BW=32bit*/
-#else
 /* Memory Bank 0 (NOR-FLASH) initialization					*/
 #define CONFIG_SYS_EBC_PB0AP		0x10055e00
 #define CONFIG_SYS_EBC_PB0CR		(CONFIG_SYS_BOOT_BASE_ADDR | 0x9a000)
@@ -575,7 +493,6 @@
 #define CONFIG_SYS_EBC_PB3AP		0x018003c0
 #define CONFIG_SYS_EBC_PB3CR		(CONFIG_SYS_NAND_ADDR | 0x1E000) /* BAS=NAND,BS=1MB,BU=R/W,BW=32bit*/
 #endif
-#endif	/*defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL) */
 
 #if !defined(CONFIG_ARCHES)
 /* Memory Bank 2 (CPLD) initialization						*/
diff --git a/include/configs/cardhu.h b/include/configs/cardhu.h
index 4abb03ea56..e15b52737b 100644
--- a/include/configs/cardhu.h
+++ b/include/configs/cardhu.h
@@ -17,7 +17,7 @@
 #ifndef __CONFIG_H
 #define __CONFIG_H
 
-#include <asm/sizes.h>
+#include <linux/sizes.h>
 
 #include "tegra30-common.h"
 
@@ -30,6 +30,10 @@
 #define V_PROMPT		"Tegra30 (Cardhu) # "
 #define CONFIG_TEGRA_BOARD_STRING	"NVIDIA Cardhu"
 
+#define BOARD_EXTRA_ENV_SETTINGS \
+	"board_name=cardhu-a04\0" \
+	"fdtfile=tegra30-cardhu-a04.dtb\0"
+
 /* Board-specific serial config */
 #define CONFIG_SERIAL_MULTI
 #define CONFIG_TEGRA_ENABLE_UARTA
diff --git a/include/configs/cgtqmx6eval.h b/include/configs/cgtqmx6eval.h
index 5cf456a78e..b189bf116f 100644
--- a/include/configs/cgtqmx6eval.h
+++ b/include/configs/cgtqmx6eval.h
@@ -75,13 +75,13 @@
 
 #define CONFIG_EXTRA_ENV_SETTINGS \
 	"script=boot.scr\0" \
-	"uimage=uImage\0" \
+	"image=zImage\0" \
 	"fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \
 	"boot_dir=/boot\0" \
 	"console=ttymxc1\0" \
 	"fdt_high=0xffffffff\0" \
 	"initrd_high=0xffffffff\0" \
-	"fdt_addr=0x11000000\0" \
+	"fdt_addr=0x18000000\0" \
 	"boot_fdt=try\0" \
 	"mmcdev=1\0" \
 	"mmcpart=1\0" \
@@ -92,24 +92,24 @@
 		"ext2load mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
 	"bootscript=echo Running bootscript from mmc ...; " \
 		"source\0" \
-	"loaduimage=ext2load mmc ${mmcdev}:${mmcpart} ${loadaddr} " \
-		"${boot_dir}/${uimage}\0" \
+	"loadimage=ext2load mmc ${mmcdev}:${mmcpart} ${loadaddr} " \
+		"${boot_dir}/${image}\0" \
 	"loadfdt=ext2load mmc ${mmcdev}:${mmcpart} ${fdt_addr} " \
 		"${boot_dir}/${fdt_file}\0" \
 	"mmcboot=echo Booting from mmc ...; " \
 		"run mmcargs; " \
 		"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
 			"if run loadfdt; then " \
-				"bootm ${loadaddr} - ${fdt_addr}; " \
+				"bootz ${loadaddr} - ${fdt_addr}; " \
 			"else " \
 				"if test ${boot_fdt} = try; then " \
-					"bootm; " \
+					"bootz; " \
 				"else " \
 					"echo WARN: Cannot load the DT; " \
 				"fi; " \
 			"fi; " \
 		"else " \
-			"bootm; " \
+			"bootz; " \
 		"fi;\0"
 
 #define CONFIG_BOOTCOMMAND \
@@ -118,7 +118,7 @@
 		   "if run loadbootscript; then " \
 			   "run bootscript; " \
 		   "else " \
-			   "if run loaduimage; then " \
+			   "if run loadimage; then " \
 				   "run mmcboot; " \
 			   "else "\
 				   "echo ERR: Fail to boot from mmc; " \
@@ -143,7 +143,6 @@
 #define CONFIG_SYS_MEMTEST_SCRATCH     0x10800000
 
 #define CONFIG_SYS_LOAD_ADDR	       CONFIG_LOADADDR
-#define CONFIG_SYS_HZ		       1000
 
 #define CONFIG_CMDLINE_EDITING
 
diff --git a/include/configs/cm-bf527.h b/include/configs/cm-bf527.h
index b15a1eb7a2..384d8715ad 100644
--- a/include/configs/cm-bf527.h
+++ b/include/configs/cm-bf527.h
@@ -128,7 +128,7 @@
 #define FLASHBOOT_ENV_SETTINGS \
 	"flashboot=flread 20040000 1000000 300000;" \
 	"bootm 0x1000000\0"
-
+#define CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED
 
 /*
  * Pull in common ADI header for remaining command/environment setup
diff --git a/include/configs/cm-bf533.h b/include/configs/cm-bf533.h
index e2b954c063..8bd499a7d2 100644
--- a/include/configs/cm-bf533.h
+++ b/include/configs/cm-bf533.h
@@ -97,7 +97,7 @@
 #define CONFIG_UART_CONSOLE	0
 #define CONFIG_BOOTCOMMAND	"run flashboot"
 #define FLASHBOOT_ENV_SETTINGS	"flashboot=bootm 0x20040000\0"
-
+#define CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED
 
 /*
  * Pull in common ADI header for remaining command/environment setup
diff --git a/include/configs/cm-bf537e.h b/include/configs/cm-bf537e.h
index 77f47d9457..67cf801a3f 100644
--- a/include/configs/cm-bf537e.h
+++ b/include/configs/cm-bf537e.h
@@ -55,7 +55,7 @@
 #define CONFIG_EBIU_AMBCTL0_VAL	(B1WAT_7 | B1RAT_11 | B1HT_2 | B1ST_3 | B0WAT_7 | B0RAT_11 | B0HT_2 | B0ST_3)
 #define CONFIG_EBIU_AMBCTL1_VAL	(B3WAT_7 | B3RAT_11 | B3HT_2 | B3ST_3 | B2WAT_7 | B2RAT_11 | B2HT_2 | B2ST_3)
 
-#define CONFIG_SYS_MONITOR_LEN	(512 * 1024)
+#define CONFIG_SYS_MONITOR_LEN	(768 * 1024)
 #define CONFIG_SYS_MALLOC_LEN	(128 * 1024)
 
 
@@ -112,8 +112,8 @@
  * it linked after the configuration sector.
  */
 # define LDS_BOARD_TEXT \
-	arch/blackfin/lib/libblackfin.o (.text*); \
-	arch/blackfin/cpu/libblackfin.o (.text*); \
+	arch/blackfin/lib/built-in.o (.text*); \
+	arch/blackfin/cpu/built-in.o (.text*); \
 	. = DEFINED(env_offset) ? env_offset : .; \
 	common/env_embedded.o (.text*);
 #endif
@@ -145,7 +145,8 @@
 #define FLASHBOOT_ENV_SETTINGS \
 	"flashboot=flread 20040000 1000000 3c0000;" \
 	"bootm 0x1000000\0"
-
+#define CONFIG_BOARD_SIZE_LIMIT $$((384 * 1024))
+#define CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED
 
 /*
  * Pull in common ADI header for remaining command/environment setup
diff --git a/include/configs/cm-bf537u.h b/include/configs/cm-bf537u.h
index 55e61d674f..34ce75baeb 100644
--- a/include/configs/cm-bf537u.h
+++ b/include/configs/cm-bf537u.h
@@ -54,7 +54,7 @@
 #define CONFIG_EBIU_AMBCTL0_VAL	(B1WAT_7 | B1RAT_11 | B1HT_2 | B1ST_3 | B0WAT_7 | B0RAT_11 | B0HT_2 | B0ST_3)
 #define CONFIG_EBIU_AMBCTL1_VAL	(B3WAT_7 | B3RAT_11 | B3HT_2 | B3ST_3 | B2WAT_7 | B2RAT_11 | B2HT_2 | B2ST_3)
 
-#define CONFIG_SYS_MONITOR_LEN	(512 * 1024)
+#define CONFIG_SYS_MONITOR_LEN	(768 * 1024)
 #define CONFIG_SYS_MALLOC_LEN	(128 * 1024)
 
 
@@ -110,8 +110,8 @@
  * it linked after the configuration sector.
  */
 # define LDS_BOARD_TEXT \
-	arch/blackfin/lib/libblackfin.o (.text*); \
-	arch/blackfin/cpu/libblackfin.o (.text*); \
+	arch/blackfin/lib/built-in.o (.text*); \
+	arch/blackfin/cpu/built-in.o (.text*); \
 	. = DEFINED(env_offset) ? env_offset : .; \
 	common/env_embedded.o (.text*);
 #endif
@@ -142,7 +142,8 @@
 #define FLASHBOOT_ENV_SETTINGS \
 	"flashboot=flread 20040000 1000000 300000;" \
 	"bootm 0x1000000\0"
-
+#define CONFIG_BOARD_SIZE_LIMIT $$((384 * 1024))
+#define CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED
 
 /*
  * Pull in common ADI header for remaining command/environment setup
diff --git a/include/configs/cm-bf548.h b/include/configs/cm-bf548.h
index 3c9eeb58a3..346e27f3eb 100644
--- a/include/configs/cm-bf548.h
+++ b/include/configs/cm-bf548.h
@@ -117,6 +117,9 @@
 #define CONFIG_UART_CONSOLE	1
 #define CONFIG_BOOTCOMMAND	"run flashboot"
 #define FLASHBOOT_ENV_SETTINGS	"flashboot=bootm 0x20040000\0"
+#define CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED
+
+#define CONFIG_ADI_GPIO2
 
 #ifndef __ADSPBF542__
 /* Don't waste time transferring a logo over the UART */
diff --git a/include/configs/cm-bf561.h b/include/configs/cm-bf561.h
index 93e3c8677e..5265e5f6ef 100644
--- a/include/configs/cm-bf561.h
+++ b/include/configs/cm-bf561.h
@@ -99,7 +99,7 @@
 #define CONFIG_UART_CONSOLE	0
 #define CONFIG_BOOTCOMMAND	"run flashboot"
 #define FLASHBOOT_ENV_SETTINGS	"flashboot=bootm 0x20040000\0"
-
+#define CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED
 
 /*
  * Pull in common ADI header for remaining command/environment setup
diff --git a/include/configs/cm4008.h b/include/configs/cm4008.h
index 9447c0b935..1cb54b3225 100644
--- a/include/configs/cm4008.h
+++ b/include/configs/cm4008.h
@@ -75,8 +75,6 @@
 
 #define CONFIG_SYS_LOAD_ADDR		0x00008000	/* default load address */
 
-#define CONFIG_SYS_HZ			(1000)		/* 1ms resolution ticks */
-
 /*-----------------------------------------------------------------------
  * Physical Memory Map
  */
diff --git a/include/configs/cm41xx.h b/include/configs/cm41xx.h
index 306684ac0d..adebd4b7b0 100644
--- a/include/configs/cm41xx.h
+++ b/include/configs/cm41xx.h
@@ -75,8 +75,6 @@
 
 #define CONFIG_SYS_LOAD_ADDR		0x00008000	/* default load address */
 
-#define CONFIG_SYS_HZ			(1000)		/* 1ms resolution ticks */
-
 /*-----------------------------------------------------------------------
  * Physical Memory Map
  */
diff --git a/include/configs/cm5200.h b/include/configs/cm5200.h
index 17824ec9a9..7c693d62d1 100644
--- a/include/configs/cm5200.h
+++ b/include/configs/cm5200.h
@@ -11,8 +11,7 @@
 /*
  * High Level Configuration Options
  */
-#define CONFIG_MPC5xxx		1	/* This is an MPC5xxx CPU */
-#define CONFIG_MPC5200		1	/* (more precisely an MPC5200 CPU) */
+#define CONFIG_MPC5200		1	/* This is an MPC5200 CPU */
 #define CONFIG_CM5200		1	/* ... on CM5200 platform */
 
 #define	CONFIG_SYS_TEXT_BASE	0xfc000000
@@ -283,7 +282,6 @@
  * Miscellaneous configurable options
  */
 #define CONFIG_SYS_LONGHELP		1	/* undef to save memory */
-#define CONFIG_SYS_PROMPT		"=> "	/* Monitor Command Prompt */
 #define CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size */
 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
 #define CONFIG_SYS_MAXARGS		16	/* max number of command args */
@@ -296,7 +294,6 @@
 #define CONFIG_LOOPW		1
 
 #define CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address */
-#define CONFIG_SYS_HZ			1000	/* decrementer freq: 1 ms ticks */
 
 /*
  * Various low-level settings
diff --git a/include/configs/cm_t335.h b/include/configs/cm_t335.h
new file mode 100644
index 0000000000..26b615b8c5
--- /dev/null
+++ b/include/configs/cm_t335.h
@@ -0,0 +1,181 @@
+/*
+ * Config file for Compulab CM-T335 board
+ *
+ * Copyright (C) 2013, Compulab Ltd - http://compulab.co.il/
+ *
+ * Author: Ilya Ledvich <ilya@compulab.co.il>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_CM_T335_H
+#define __CONFIG_CM_T335_H
+
+#define CONFIG_CM_T335
+#define CONFIG_NAND
+
+#include <configs/ti_am335x_common.h>
+
+#undef CONFIG_BOARD_LATE_INIT
+#undef CONFIG_SPI
+#undef CONFIG_OMAP3_SPI
+#undef CONFIG_CMD_SPI
+#undef CONFIG_SPL_OS_BOOT
+#undef CONFIG_BOOTCOUNT_LIMIT
+#undef CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC
+
+#undef CONFIG_MAX_RAM_BANK_SIZE
+#define CONFIG_MAX_RAM_BANK_SIZE	(512 << 20)	/* 512MB */
+
+#undef CONFIG_SYS_PROMPT
+#define CONFIG_SYS_PROMPT		"CM-T335 # "
+
+#define CONFIG_OMAP_COMMON
+
+#define MACH_TYPE_CM_T335		4586	/* Until the next sync */
+#define CONFIG_MACH_TYPE		MACH_TYPE_CM_T335
+
+/* Clock Defines */
+#define V_OSCK				25000000  /* Clock output from T2 */
+#define V_SCLK				(V_OSCK)
+
+#define CONFIG_ENV_SIZE			(16 << 10)	/* 16 KiB */
+
+#ifndef CONFIG_SPL_BUILD
+#define MMCARGS \
+	"mmcdev=0\0" \
+	"mmcroot=/dev/mmcblk0p2 rw rootwait\0" \
+	"mmcrootfstype=ext4\0" \
+	"mmcargs=setenv bootargs console=${console} " \
+		"root=${mmcroot} " \
+		"rootfstype=${mmcrootfstype}\0" \
+	"mmcboot=echo Booting from mmc ...; " \
+		"run mmcargs; " \
+		"bootm ${loadaddr}\0"
+
+#define NANDARGS \
+	"mtdids=" MTDIDS_DEFAULT "\0" \
+	"mtdparts=" MTDPARTS_DEFAULT "\0" \
+	"nandroot=ubi0:rootfs rw\0" \
+	"nandrootfstype=ubifs\0" \
+	"nandargs=setenv bootargs console=${console} " \
+		"root=${nandroot} " \
+		"rootfstype=${nandrootfstype} " \
+		"ubi.mtd=${rootfs_name}\0" \
+	"nandboot=echo Booting from nand ...; " \
+		"run nandargs; " \
+		"nboot ${loadaddr} nand0 900000; " \
+		"bootm ${loadaddr}\0"
+
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"loadaddr=82000000\0" \
+	"console=ttyO0,115200n8\0" \
+	"rootfs_name=rootfs\0" \
+	"loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
+	"bootscript=echo Running bootscript from mmc ...; " \
+		"source ${loadaddr}\0" \
+	"loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \
+	MMCARGS \
+	NANDARGS
+
+#define CONFIG_BOOTCOMMAND \
+	"mmc dev ${mmcdev}; if mmc rescan; then " \
+		"if run loadbootscript; then " \
+			"run bootscript; " \
+		"else " \
+			"if run loaduimage; then " \
+				"run mmcboot; " \
+			"else run nandboot; " \
+			"fi; " \
+		"fi; " \
+	"else run nandboot; fi"
+#endif /* CONFIG_SPL_BUILD */
+
+#define CONFIG_TIMESTAMP
+#define CONFIG_SYS_AUTOLOAD		"no"
+
+/* Serial console configuration */
+#define CONFIG_CONS_INDEX		1
+#define CONFIG_SERIAL1			1	/* UART0 */
+
+/* NS16550 Configuration */
+#define CONFIG_SYS_NS16550_COM1		0x44e09000	/* UART0 */
+#define CONFIG_SYS_NS16550_COM2		0x48022000	/* UART1 */
+#define CONFIG_BAUDRATE			115200
+
+/* I2C Configuration */
+#define CONFIG_SYS_I2C_EEPROM_ADDR	0x50	/* Main EEPROM */
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	1
+
+/* SPL */
+#define CONFIG_SPL_LDSCRIPT		"$(CPUDIR)/am33xx/u-boot-spl.lds"
+
+/* Network. */
+#define CONFIG_PHY_GIGE
+#define CONFIG_PHYLIB
+#define CONFIG_PHY_ATHEROS
+
+/* NAND support */
+#define CONFIG_SYS_NAND_5_ADDR_CYCLE
+#define CONFIG_SYS_NAND_PAGE_COUNT	(CONFIG_SYS_NAND_BLOCK_SIZE / \
+					 CONFIG_SYS_NAND_PAGE_SIZE)
+#define CONFIG_SYS_NAND_PAGE_SIZE	2048
+#define CONFIG_SYS_NAND_OOBSIZE		64
+#define CONFIG_SYS_NAND_BLOCK_SIZE	(128 * 1024)
+#define CONFIG_SYS_NAND_BAD_BLOCK_POS	NAND_LARGE_BADBLOCK_POS
+#define CONFIG_SYS_NAND_ECCPOS		{ 2, 3, 4, 5, 6, 7, 8, 9, \
+					 10, 11, 12, 13, 14, 15, 16, 17, \
+					 18, 19, 20, 21, 22, 23, 24, 25, \
+					 26, 27, 28, 29, 30, 31, 32, 33, \
+					 34, 35, 36, 37, 38, 39, 40, 41, \
+					 42, 43, 44, 45, 46, 47, 48, 49, \
+					 50, 51, 52, 53, 54, 55, 56, 57, }
+
+#define CONFIG_SYS_NAND_ECCSIZE		512
+#define CONFIG_SYS_NAND_ECCBYTES	14
+
+#define CONFIG_SYS_NAND_U_BOOT_START	CONFIG_SYS_TEXT_BASE
+
+#undef CONFIG_SYS_NAND_U_BOOT_OFFS
+#define CONFIG_SYS_NAND_U_BOOT_OFFS	0x200000
+
+#define CONFIG_CMD_NAND
+#define GPMC_NAND_ECC_LP_x8_LAYOUT
+#define MTDIDS_DEFAULT			"nand0=nand"
+#define MTDPARTS_DEFAULT		"mtdparts=nand:2m(spl)," \
+					"1m(u-boot),1m(u-boot-env)," \
+					"1m(dtb),4m(splash)," \
+					"6m(kernel),-(rootfs)"
+#define CONFIG_ENV_IS_IN_NAND
+#define CONFIG_ENV_OFFSET		0x300000 /* environment starts here */
+#define CONFIG_SYS_ENV_SECT_SIZE	(128 << 10)	/* 128 KiB */
+#define CONFIG_SYS_NAND_ONFI_DETECTION
+
+/* GPIO pin + bank to pin ID mapping */
+#define GPIO_PIN(_bank, _pin)		((_bank << 5) + _pin)
+
+/* Status LED */
+#define CONFIG_STATUS_LED
+#define CONFIG_GPIO_LED
+#define CONFIG_BOARD_SPECIFIC_LED
+#define STATUS_LED_BIT			GPIO_PIN(2, 0)
+/* Status LED polarity is inversed, so init it in the "off" state */
+#define STATUS_LED_STATE		STATUS_LED_OFF
+#define STATUS_LED_PERIOD		(CONFIG_SYS_HZ / 2)
+#define STATUS_LED_BOOT			0
+
+#ifndef CONFIG_SPL_BUILD
+/*
+ * Enable PCA9555 at I2C0-0x26.
+ * First select the I2C0 bus with "i2c dev 0", then use "pca953x" command.
+ */
+#define CONFIG_PCA953X
+#define CONFIG_CMD_PCA953X
+#define CONFIG_CMD_PCA953X_INFO
+#define CONFIG_SYS_I2C_PCA953X_ADDR	0x26
+#define CONFIG_SYS_I2C_PCA953X_WIDTH	{ {0x26, 16} }
+#endif /* CONFIG_SPL_BUILD */
+
+#endif	/* __CONFIG_CM_T335_H */
+
diff --git a/include/configs/cm_t35.h b/include/configs/cm_t35.h
index bc5b66c6dc..aae05e0333 100644
--- a/include/configs/cm_t35.h
+++ b/include/configs/cm_t35.h
@@ -23,11 +23,10 @@
 #define CONFIG_OMAP	/* in a TI OMAP core */
 #define CONFIG_OMAP34XX	/* which is a 34XX */
 #define CONFIG_OMAP_GPIO
+#define CONFIG_CMD_GPIO
 #define CONFIG_CM_T3X	/* working with CM-T35 and CM-T3730 */
 #define CONFIG_OMAP_COMMON
 
-#define CONFIG_SYS_TEXT_BASE	0x80008000
-
 #define CONFIG_SDRC	/* The chip has SDRC controller */
 
 #include <asm/arch/cpu.h>		/* get chip and board defs */
@@ -46,13 +45,6 @@
 #define CONFIG_MISC_INIT_R
 
 #define CONFIG_OF_LIBFDT		1
-/*
- * The early kernel mapping on ARM currently only maps from the base of DRAM
- * to the end of the kernel image.  The kernel is loaded at DRAM base + 0x8000.
- * The early kernel pagetable uses DRAM base + 0x4000 to DRAM base + 0x8000,
- * so that leaves DRAM base to DRAM base + 0x4000 available.
- */
-#define CONFIG_SYS_BOOTMAPSZ	        0x4000
 
 #define CONFIG_CMDLINE_TAG		/* enable passing of ATAGs */
 #define CONFIG_SETUP_MEMORY_TAGS
@@ -103,8 +95,6 @@
 #define CONFIG_USB_OMAP3
 #define CONFIG_USB_EHCI
 #define CONFIG_USB_EHCI_OMAP
-#define CONFIG_USB_ULPI
-#define CONFIG_USB_ULPI_VIEWPORT_OMAP
 #define CONFIG_USB_STORAGE
 #define CONFIG_MUSB_UDC
 #define CONFIG_TWL4030_USB
@@ -114,6 +104,8 @@
 #define CONFIG_USB_DEVICE
 #define CONFIG_USB_TTY
 #define CONFIG_SYS_CONSOLE_IS_IN_ENV
+/* This delay is really for slow-to-power-on USB sticks, not the hub */
+#define CONFIG_USB_HUB_MIN_POWER_ON_DELAY 500
 
 /* commands to include */
 #include <config_cmd_default.h>
@@ -140,10 +132,10 @@
 #undef CONFIG_CMD_IMLS		/* List all found images	*/
 
 #define CONFIG_SYS_NO_FLASH
-#define CONFIG_HARD_I2C
-#define CONFIG_SYS_I2C_SPEED		100000
-#define CONFIG_SYS_I2C_SLAVE		1
-#define CONFIG_DRIVER_OMAP34XX_I2C
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_OMAP24_I2C_SPEED	100000
+#define CONFIG_SYS_OMAP24_I2C_SLAVE	1
+#define CONFIG_SYS_I2C_OMAP34XX
 #define CONFIG_SYS_I2C_EEPROM_ADDR	0x50
 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	1
 #define CONFIG_I2C_MULTI_BUS
@@ -164,18 +156,18 @@
 #define CONFIG_SYS_NAND_BASE		NAND_BASE	/* physical address */
 							/* to access nand at */
 							/* CS0 */
-#define GPMC_NAND_ECC_LP_x8_LAYOUT
-
 #define CONFIG_SYS_MAX_NAND_DEVICE	1		/* Max number of NAND */
 							/* devices */
+#define GPMC_NAND_ECC_LP_x8_LAYOUT
+
 /* Environment information */
-#define CONFIG_BOOTDELAY		10
+#define CONFIG_BOOTDELAY		3
 #define CONFIG_ZERO_BOOTDELAY_CHECK
 
 #define CONFIG_EXTRA_ENV_SETTINGS \
 	"loadaddr=0x82000000\0" \
 	"usbtty=cdc_acm\0" \
-	"console=ttyS2,115200n8\0" \
+	"console=ttyO2,115200n8\0" \
 	"mpurate=500\0" \
 	"vram=12M\0" \
 	"dvimode=1024x768MR-16@60\0" \
@@ -189,7 +181,6 @@
 		"mpurate=${mpurate} " \
 		"vram=${vram} " \
 		"omapfb.mode=dvi:${dvimode} " \
-		"omapfb.debug=y " \
 		"omapdss.def_disp=${defaultdisplay} " \
 		"root=${mmcroot} " \
 		"rootfstype=${mmcrootfstype}\0" \
@@ -197,7 +188,6 @@
 		"mpurate=${mpurate} " \
 		"vram=${vram} " \
 		"omapfb.mode=dvi:${dvimode} " \
-		"omapfb.debug=y " \
 		"omapdss.def_disp=${defaultdisplay} " \
 		"root=${nandroot} " \
 		"rootfstype=${nandrootfstype}\0" \
@@ -213,6 +203,7 @@
 		"nand read ${loadaddr} 2a0000 400000; " \
 		"bootm ${loadaddr}\0" \
 
+#define CONFIG_CMD_BOOTZ
 #define CONFIG_BOOTCOMMAND \
 	"mmc dev ${mmcdev}; if mmc rescan; then " \
 		"if run loadbootscript; then " \
@@ -258,7 +249,6 @@
  */
 #define CONFIG_SYS_TIMERBASE		(OMAP34XX_GPT2)
 #define CONFIG_SYS_PTV			2       /* Divisor: 2^(PTV+1) => 8 */
-#define CONFIG_SYS_HZ			1000
 
 /*-----------------------------------------------------------------------
  * Physical Memory Map
@@ -302,12 +292,13 @@
 /* Status LED */
 #define CONFIG_STATUS_LED		/* Status LED enabled */
 #define CONFIG_BOARD_SPECIFIC_LED
-#define STATUS_LED_GREEN		0
-#define STATUS_LED_BIT			STATUS_LED_GREEN
+#define CONFIG_GPIO_LED
+#define GREEN_LED_GPIO			186 /* CM-T35 Green LED is GPIO186 */
+#define GREEN_LED_DEV			0
+#define STATUS_LED_BIT			GREEN_LED_GPIO
 #define STATUS_LED_STATE		STATUS_LED_ON
 #define STATUS_LED_PERIOD		(CONFIG_SYS_HZ / 2)
-#define STATUS_LED_BOOT			STATUS_LED_BIT
-#define GREEN_LED_GPIO			186 /* CM-T35 Green LED is GPIO186 */
+#define STATUS_LED_BOOT			GREEN_LED_DEV
 
 #define CONFIG_SPLASHIMAGE_GUARD
 
@@ -318,6 +309,7 @@
 
 /* Display Configuration */
 #define CONFIG_OMAP3_GPIO_2
+#define CONFIG_OMAP3_GPIO_5
 #define CONFIG_VIDEO_OMAP3
 #define LCD_BPP		LCD_COLOR16
 
@@ -325,5 +317,71 @@
 #define CONFIG_SPLASH_SCREEN
 #define CONFIG_CMD_BMP
 #define CONFIG_BMP_16BPP
+#define CONFIG_SCF0403_LCD
+
+#define CONFIG_OMAP3_SPI
+
+/* Defines for SPL */
+#define CONFIG_SPL
+#define CONFIG_SPL_FRAMEWORK
+#define CONFIG_SPL_NAND_SIMPLE
+
+#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR	0x300 /* address 0x60000 */
+#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS	0x200 /* 256 KB */
+#define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION	1
+#define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME	"u-boot.img"
+
+#define CONFIG_SPL_BOARD_INIT
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+#define CONFIG_SPL_LIBDISK_SUPPORT
+#define CONFIG_SPL_I2C_SUPPORT
+#define CONFIG_SPL_LIBGENERIC_SUPPORT
+#define CONFIG_SPL_MMC_SUPPORT
+#define CONFIG_SPL_FAT_SUPPORT
+#define CONFIG_SPL_SERIAL_SUPPORT
+#define CONFIG_SPL_NAND_SUPPORT
+#define CONFIG_SPL_NAND_BASE
+#define CONFIG_SPL_NAND_DRIVERS
+#define CONFIG_SPL_NAND_ECC
+#define CONFIG_SPL_GPIO_SUPPORT
+#define CONFIG_SPL_POWER_SUPPORT
+#define CONFIG_SPL_OMAP3_ID_NAND
+#define CONFIG_SPL_LDSCRIPT		"$(CPUDIR)/omap-common/u-boot-spl.lds"
+
+/* NAND boot config */
+#define CONFIG_SYS_NAND_5_ADDR_CYCLE
+#define CONFIG_SYS_NAND_PAGE_COUNT	64
+#define CONFIG_SYS_NAND_PAGE_SIZE	2048
+#define CONFIG_SYS_NAND_OOBSIZE		64
+#define CONFIG_SYS_NAND_BLOCK_SIZE	(128 * 1024)
+#define CONFIG_SYS_NAND_BAD_BLOCK_POS	NAND_LARGE_BADBLOCK_POS
+/*
+ * Use the ECC/OOB layout from omap_gpmc.h that matches your chip:
+ * SP vs LP, 8bit vs 16bit: GPMC_NAND_HW_ECC_LAYOUT
+ */
+#define CONFIG_SYS_NAND_ECCPOS		{ 1, 2, 3, 4, 5, 6, 7, 8, 9, \
+					 10, 11, 12 }
+#define CONFIG_SYS_NAND_ECCSIZE		512
+#define CONFIG_SYS_NAND_ECCBYTES	3
+#define CONFIG_NAND_OMAP_ECCSCHEME	OMAP_ECC_HAM1_CODE_HW
+
+#define CONFIG_SYS_NAND_U_BOOT_START	CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_NAND_U_BOOT_OFFS	0x80000
+
+#define CONFIG_SPL_TEXT_BASE		0x40200800
+#define CONFIG_SPL_MAX_SIZE		(54 * 1024)	/* 8 KB for stack */
+#define CONFIG_SPL_STACK		LOW_LEVEL_SRAM_STACK
+
+/*
+ * Use 0x80008000 as TEXT_BASE here for compatibility reasons with the
+ * older x-loader implementations. And move the BSS area so that it
+ * doesn't overlap with TEXT_BASE.
+ */
+#define CONFIG_SYS_TEXT_BASE		0x80008000
+#define CONFIG_SPL_BSS_START_ADDR	0x80100000
+#define CONFIG_SPL_BSS_MAX_SIZE		0x80000		/* 512 KB */
+
+#define CONFIG_SYS_SPL_MALLOC_START	0x80208000
+#define CONFIG_SYS_SPL_MALLOC_SIZE	0x100000
 
 #endif /* __CONFIG_H */
diff --git a/include/configs/cmi_mpc5xx.h b/include/configs/cmi_mpc5xx.h
index 417c873574..32cecbdc9c 100644
--- a/include/configs/cmi_mpc5xx.h
+++ b/include/configs/cmi_mpc5xx.h
@@ -82,7 +82,6 @@
  */
 
 #define	CONFIG_SYS_LONGHELP				/* undef to save memory		*/
-#define	CONFIG_SYS_PROMPT		"=> "		/* Monitor Command Prompt	*/
 #if defined(CONFIG_CMD_KGDB)
 #define	CONFIG_SYS_CBSIZE		1024		/* Console I/O Buffer Size	*/
 #else
@@ -97,8 +96,6 @@
 
 #define	CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address		*/
 
-#define	CONFIG_SYS_HZ			1000		/* Decrementer freq: 1 ms ticks	*/
-
 #define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 1250000 }
 
 
diff --git a/include/configs/cobra5272.h b/include/configs/cobra5272.h
index b13898815a..464436930d 100644
--- a/include/configs/cobra5272.h
+++ b/include/configs/cobra5272.h
@@ -37,11 +37,9 @@
 /* ---
  * Defines processor clock - important for correct timings concerning serial
  * interface etc.
- * CONFIG_SYS_HZ gives unit: 1000 -> 1 Hz ^= 1000 ms
  * ---
  */
 
-#define CONFIG_SYS_HZ			1000
 #define CONFIG_SYS_CLK			66000000
 #define CONFIG_SYS_SDRAM_SIZE		16		/* SDRAM size in MB */
 
diff --git a/include/configs/cogent_mpc8260.h b/include/configs/cogent_mpc8260.h
index 4a8e5830e1..02b25c6444 100644
--- a/include/configs/cogent_mpc8260.h
+++ b/include/configs/cogent_mpc8260.h
@@ -124,7 +124,6 @@
  * Miscellaneous configurable options
  */
 #define	CONFIG_SYS_LONGHELP			/* undef to save memory		*/
-#define	CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt	*/
 #if defined(CONFIG_CMD_KGDB)
 #define	CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
 #else
@@ -139,8 +138,6 @@
 
 #define	CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address	*/
 
-#define	CONFIG_SYS_HZ		1000		/* decrementer freq: 1 ms ticks	*/
-
 #define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
 
 /*
diff --git a/include/configs/cogent_mpc8xx.h b/include/configs/cogent_mpc8xx.h
index c57d70279f..c98b687c09 100644
--- a/include/configs/cogent_mpc8xx.h
+++ b/include/configs/cogent_mpc8xx.h
@@ -89,7 +89,6 @@
  * Miscellaneous configurable options
  */
 #define	CONFIG_SYS_LONGHELP			/* undef to save memory		*/
-#define	CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt	*/
 #if defined(CONFIG_CMD_KGDB)
 #define	CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
 #else
@@ -104,8 +103,6 @@
 
 #define	CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address	*/
 
-#define	CONFIG_SYS_HZ		1000		/* decrementer freq: 1 ms ticks	*/
-
 #define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
 
 #define CONFIG_SYS_ALLOC_DPRAM
diff --git a/include/configs/colibri_pxa270.h b/include/configs/colibri_pxa270.h
index ee0342b44b..08bd276b44 100644
--- a/include/configs/colibri_pxa270.h
+++ b/include/configs/colibri_pxa270.h
@@ -86,7 +86,6 @@
 #ifdef	CONFIG_SYS_HUSH_PARSER
 #define	CONFIG_SYS_PROMPT		"$ "
 #else
-#define	CONFIG_SYS_PROMPT		"=> "
 #endif
 #define	CONFIG_SYS_CBSIZE		256
 #define	CONFIG_SYS_PBSIZE		\
@@ -101,7 +100,6 @@
 /*
  * Clock Configuration
  */
-#define	CONFIG_SYS_HZ			1000		/* Timer @ 3250000 Hz */
 #define	CONFIG_SYS_CPUSPEED		0x290		/* 520MHz */
 
 /*
diff --git a/include/configs/colibri_vf.h b/include/configs/colibri_vf.h
new file mode 100644
index 0000000000..77e649002d
--- /dev/null
+++ b/include/configs/colibri_vf.h
@@ -0,0 +1,199 @@
+/*
+ * Copyright 2013 Toradex, Inc.
+ *
+ * Configuration settings for the Toradex VF61 module.
+ *
+ * Based on vf610twr.h:
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <asm/arch/imx-regs.h>
+#include <config_cmd_default.h>
+
+#define CONFIG_VF610
+
+#define CONFIG_SYS_GENERIC_BOARD
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DISPLAY_BOARDINFO
+
+#define CONFIG_SKIP_LOWLEVEL_INIT
+
+/* Enable passing of ATAGs */
+#define CONFIG_CMDLINE_TAG
+
+#define CONFIG_CMD_FUSE
+#ifdef CONFIG_CMD_FUSE
+#define CONFIG_MXC_OCOTP
+#endif
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 2 * 1024 * 1024)
+
+#define CONFIG_BOARD_EARLY_INIT_F
+
+#define CONFIG_FSL_LPUART
+#define LPUART_BASE			UART0_BASE
+
+/* Allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_BAUDRATE			115200
+
+/* NAND support */
+#define CONFIG_CMD_NAND
+#define CONFIG_CMD_WRITEBCB
+#define CONFIG_NAND_FSL_NFC
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+#define CONFIG_SYS_NAND_BASE		NFC_BASE_ADDR
+
+/* Dynamic MTD partition support */
+#define CONFIG_CMD_MTDPARTS	/* Enable 'mtdparts' command line support */
+#define CONFIG_MTD_PARTITIONS
+#define CONFIG_MTD_DEVICE	/* needed for mtdparts commands */
+#define MTDIDS_DEFAULT		"nand0=fsl_nfc"
+#define MTDPARTS_DEFAULT	"mtdparts=fsl_nfc:"		\
+				"128k(vf-bcb)ro,"		\
+				"1408k(u-boot)ro,"		\
+				"512k(u-boot-env)ro,"		\
+				"8m(kernel-ubi),"		\
+				"-(rootfs-ubi)"
+
+#undef CONFIG_CMD_IMLS
+
+#define CONFIG_MMC
+#define CONFIG_FSL_ESDHC
+#define CONFIG_SYS_FSL_ESDHC_ADDR	0
+#define CONFIG_SYS_FSL_ESDHC_NUM	1
+
+#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
+
+#define CONFIG_CMD_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_CMD_FAT
+#define CONFIG_DOS_PARTITION
+
+#define CONFIG_RBTREE
+#define CONFIG_LZO
+#define CONFIG_CMD_FS_GENERIC
+#define CONFIG_CMD_BOOTZ
+#define CONFIG_CMD_UBI
+#define CONFIG_CMD_UBIFS	/* increases size by almost 60 KB */
+
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NET
+#define CONFIG_FEC_MXC
+#define CONFIG_MII
+#define IMX_FEC_BASE			ENET1_BASE_ADDR
+#define CONFIG_FEC_XCV_TYPE		RMII
+#define CONFIG_FEC_MXC_PHYADDR          0
+#define CONFIG_PHYLIB
+#define CONFIG_PHY_MICREL
+
+#define CONFIG_IPADDR		192.168.10.2
+#define CONFIG_NETMASK		255.255.255.0
+#define CONFIG_SERVERIP		192.168.10.1
+
+#define CONFIG_BOOTDELAY		1
+
+#define CONFIG_BOARD_LATE_INIT
+#define CONFIG_TRDX_CFG_BLOCK_OFFSET	0x800
+#define CONFIG_REVISION_TAG
+#define CONFIG_SERIAL_TAG
+
+#define CONFIG_LOADADDR			0x80010000
+#define CONFIG_SYS_TEXT_BASE		0x3f408000
+
+#define DEFAULT_BOOTCOMMAND					\
+	"run ubiboot; run nfsboot"
+
+#define MMC_BOOTCMD						\
+	"run setup; "						\
+	"setenv bootargs ${defargs} ${mmcargs} ${mtdparts} ${setupargs}; " \
+	"echo Booting from MMC/SD card...; "			\
+	"mmc part 0; fatload mmc 0:1 ${loadaddr} uImage && bootm"
+
+#define NFS_BOOTCMD						\
+	"run setup; "						\
+	"setenv bootargs ${defargs} ${nfsargs} ${mtdparts} ${setupargs}; " \
+	"echo Booting from NFS...; "				\
+	"dhcp && bootm"
+
+#define UBI_BOOTCMD						\
+	"run setup; "						\
+	"setenv bootargs ${defargs} ${ubiargs} ${mtdparts} ${setupargs}; " \
+	"echo Booting from NAND...; "				\
+	"ubi part kernel-ubi && ubi read ${loadaddr} kernel && bootm"
+
+#define CONFIG_BOOTCOMMAND	DEFAULT_BOOTCOMMAND
+#define CONFIG_NFSBOOTCOMMAND	NFS_BOOTCMD
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"defargs=vmalloc=64M usb_high_speed=1\0" \
+	"mmcargs=root=/dev/mmcblk0p2 rw rootwait\0" \
+	"sdboot=" MMC_BOOTCMD "\0" \
+	"mtdparts=" MTDPARTS_DEFAULT "\0" \
+	"nfsargs=ip=:::::eth0: root=/dev/nfs\0" \
+	"setup=setenv setupargs " \
+	"fec_mac=${ethaddr} no_console_suspend=1 console=tty1 console=ttymxc0" \
+		",${baudrate}n8 ${memargs}\0" \
+	"ubiargs=ubi.mtd=rootfs-ubi root=ubi0:rootfs rootfstype=ubifs\0" \
+	"ubiboot=" UBI_BOOTCMD "\0" \
+	""
+
+/* Miscellaneous configurable options */
+#define CONFIG_SYS_LONGHELP		/* undef to save memory */
+#define CONFIG_SYS_HUSH_PARSER		/* use "hush" command parser */
+#define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
+#define CONFIG_SYS_PROMPT		"Colibri VFxx # "
+#undef CONFIG_AUTO_COMPLETE
+#define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size */
+#define CONFIG_SYS_PBSIZE		\
+			(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS		16	/* max number of command args */
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE
+
+#define CONFIG_CMD_MEMTEST
+#define CONFIG_SYS_MEMTEST_START	0x80010000
+#define CONFIG_SYS_MEMTEST_END		0x87C00000
+
+#define CONFIG_SYS_LOAD_ADDR		CONFIG_LOADADDR
+#define CONFIG_SYS_HZ			1000
+#define CONFIG_CMDLINE_EDITING
+
+/*
+ * Stack sizes
+ * The stack sizes are set up in start.S using the settings below
+ */
+#define CONFIG_STACKSIZE		(128 * 1024)	/* regular stack */
+
+/* Physical memory map */
+#define CONFIG_NR_DRAM_BANKS		1
+#define PHYS_SDRAM			(0x80000000)
+#define PHYS_SDRAM_SIZE			(256 * 1024 * 1024)
+
+#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM
+#define CONFIG_SYS_INIT_RAM_ADDR	IRAM_BASE_ADDR
+#define CONFIG_SYS_INIT_RAM_SIZE	IRAM_SIZE
+
+#define CONFIG_SYS_INIT_SP_OFFSET \
+	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR \
+	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+
+/* Environment organization */
+#define CONFIG_ENV_IS_IN_NAND
+#define CONFIG_ENV_SIZE			(64 * 2048)
+#define CONFIG_ENV_OFFSET		(6 * 64 * 2048)
+
+#define CONFIG_OF_LIBFDT
+#define CONFIG_CMD_BOOTZ
+
+#define CONFIG_SYS_NO_FLASH
+
+#endif
diff --git a/include/configs/controlcenterd.h b/include/configs/controlcenterd.h
index c6aad01dba..868813f29b 100644
--- a/include/configs/controlcenterd.h
+++ b/include/configs/controlcenterd.h
@@ -41,7 +41,6 @@
 /* High Level Configuration Options */
 #define CONFIG_BOOKE			/* BOOKE */
 #define CONFIG_E500			/* BOOKE e500 family */
-#define CONFIG_MPC85xx			/* MPC8540/60/55/41/48 */
 #define CONFIG_P1022
 #define CONFIG_CONTROLCENTERD
 #define CONFIG_MP			/* support multiple processors */
@@ -138,7 +137,7 @@
 #define CONFIG_SYS_SDRAM_SIZE 1024
 #define CONFIG_VERY_BIG_RAM
 
-#define CONFIG_FSL_DDR3
+#define CONFIG_SYS_FSL_DDR3
 #define CONFIG_NUM_DDR_CONTROLLERS	1
 #define CONFIG_DIMM_SLOTS_PER_CTLR	1
 #define CONFIG_CHIP_SELECTS_PER_CTRL	(2 * CONFIG_DIMM_SLOTS_PER_CTLR)
@@ -383,7 +382,6 @@
 #endif /* CONFIG_TRAILBLAZER */
 
 #define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
-#define CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt */
 #ifdef CONFIG_CMD_KGDB
 #define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size */
 #else
@@ -440,7 +438,6 @@
 /*
  * Miscellaneous configurable options
  */
-#define CONFIG_SYS_HZ		1000
 #define CONFIG_HW_WATCHDOG
 #define CONFIG_LOADS_ECHO
 #define CONFIG_SYS_LOADS_BAUD_CHANGE
diff --git a/include/configs/coreboot.h b/include/configs/coreboot.h
index d1be5e3c0c..d1d732f211 100644
--- a/include/configs/coreboot.h
+++ b/include/configs/coreboot.h
@@ -204,7 +204,6 @@
 
 #if defined(CONFIG_CMD_KGDB)
 #define CONFIG_KGDB_BAUDRATE			115200
-#define CONFIG_KGDB_SER_INDEX			2
 #endif
 
 /*
@@ -222,7 +221,6 @@
 #define CONFIG_SYS_MEMTEST_START		0x00100000
 #define CONFIG_SYS_MEMTEST_END			0x01000000
 #define CONFIG_SYS_LOAD_ADDR			0x100000
-#define CONFIG_SYS_HZ				1000
 
 /*-----------------------------------------------------------------------
  * SDRAM Configuration
diff --git a/include/configs/corenet_ds.h b/include/configs/corenet_ds.h
index c3fb80c8d0..1e4bfc49fc 100644
--- a/include/configs/corenet_ds.h
+++ b/include/configs/corenet_ds.h
@@ -15,15 +15,15 @@
 #ifdef CONFIG_RAMBOOT_PBL
 #define CONFIG_RAMBOOT_TEXT_BASE	CONFIG_SYS_TEXT_BASE
 #define CONFIG_RESET_VECTOR_ADDRESS	0xfffffffc
-#define CONFIG_PBLPBI_CONFIG $(SRCTREE)/board/freescale/corenet_ds/pbi.cfg
+#define CONFIG_SYS_FSL_PBL_PBI board/freescale/corenet_ds/pbi.cfg
 #if defined(CONFIG_P3041DS)
-#define CONFIG_PBLRCW_CONFIG $(SRCTREE)/board/freescale/corenet_ds/rcw_p3041ds.cfg
+#define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p3041ds.cfg
 #elif defined(CONFIG_P4080DS)
-#define CONFIG_PBLRCW_CONFIG $(SRCTREE)/board/freescale/corenet_ds/rcw_p4080ds.cfg
+#define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p4080ds.cfg
 #elif defined(CONFIG_P5020DS)
-#define CONFIG_PBLRCW_CONFIG $(SRCTREE)/board/freescale/corenet_ds/rcw_p5020ds.cfg
+#define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p5020ds.cfg
 #elif defined(CONFIG_P5040DS)
-#define CONFIG_PBLRCW_CONFIG $(SRCTREE)/board/freescale/corenet_ds/rcw_p5040ds.cfg
+#define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p5040ds.cfg
 #endif
 #endif
 
@@ -41,11 +41,10 @@
 #define CONFIG_E500			/* BOOKE e500 family */
 #define CONFIG_E500MC			/* BOOKE e500mc family */
 #define CONFIG_SYS_BOOK3E_HV		/* Category E.HV supported */
-#define CONFIG_MPC85xx			/* MPC85xx/PQ3 platform */
 #define CONFIG_MP			/* support multiple processors */
 
 #ifndef CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_TEXT_BASE	0xeff80000
+#define CONFIG_SYS_TEXT_BASE	0xeff40000
 #endif
 
 #ifndef CONFIG_RESET_VECTOR_ADDRESS
@@ -91,12 +90,12 @@
 #define CONFIG_FSL_FIXED_MMC_LOCATION
 #define CONFIG_SYS_MMC_ENV_DEV          0
 #define CONFIG_ENV_SIZE			0x2000
-#define CONFIG_ENV_OFFSET		(512 * 1097)
+#define CONFIG_ENV_OFFSET		(512 * 1658)
 #elif defined(CONFIG_NAND)
 #define CONFIG_SYS_EXTRA_ENV_RELOC
 #define CONFIG_ENV_IS_IN_NAND
 #define CONFIG_ENV_SIZE			CONFIG_SYS_NAND_BLOCK_SIZE
-#define CONFIG_ENV_OFFSET		(5 * CONFIG_SYS_NAND_BLOCK_SIZE)
+#define CONFIG_ENV_OFFSET		(7 * CONFIG_SYS_NAND_BLOCK_SIZE)
 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
 #define CONFIG_ENV_IS_IN_REMOTE
 #define CONFIG_ENV_ADDR		0xffe20000
@@ -173,7 +172,7 @@
 #define CONFIG_CHIP_SELECTS_PER_CTRL	(4 * CONFIG_DIMM_SLOTS_PER_CTLR)
 
 #define CONFIG_DDR_SPD
-#define CONFIG_FSL_DDR3
+#define CONFIG_SYS_FSL_DDR3
 
 #define CONFIG_SYS_SPD_BUS_NUM	1
 #define SPD_EEPROM_ADDRESS1	0x51
@@ -514,14 +513,14 @@
 #elif defined(CONFIG_SDCARD)
 /*
  * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
- * about 545KB (1089 blocks), Env is stored after the image, and the env size is
- * 0x2000 (16 blocks), 8 + 1089 + 16 = 1113, enlarge it to 1130.
+ * about 825KB (1650 blocks), Env is stored after the image, and the env size is
+ * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680.
  */
 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC
-#define CONFIG_SYS_QE_FMAN_FW_ADDR	(512 * 1130)
+#define CONFIG_SYS_QE_FMAN_FW_ADDR	(512 * 1680)
 #elif defined(CONFIG_NAND)
 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND
-#define CONFIG_SYS_QE_FMAN_FW_ADDR	(6 * CONFIG_SYS_NAND_BLOCK_SIZE)
+#define CONFIG_SYS_QE_FMAN_FW_ADDR	(8 * CONFIG_SYS_NAND_BLOCK_SIZE)
 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
 /*
  * Slave has no ucode locally, it can fetch this from remote. When implementing
@@ -534,7 +533,7 @@
 #define CONFIG_SYS_QE_FMAN_FW_ADDR	0xFFE00000
 #else
 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
-#define CONFIG_SYS_QE_FMAN_FW_ADDR		0xEFF40000
+#define CONFIG_SYS_QE_FMAN_FW_ADDR		0xEFF00000
 #endif
 #define CONFIG_SYS_QE_FMAN_FW_LENGTH	0x10000
 #define CONFIG_SYS_FDT_PAD		(0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
@@ -653,7 +652,6 @@
 #define CONFIG_CMDLINE_EDITING			/* Command-line editing */
 #define CONFIG_AUTO_COMPLETE			/* add autocompletion support */
 #define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
-#define CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt */
 #ifdef CONFIG_CMD_KGDB
 #define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size */
 #else
@@ -662,7 +660,6 @@
 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
 #define CONFIG_SYS_MAXARGS	16		/* max number of command args */
 #define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size */
-#define CONFIG_SYS_HZ		1000		/* decrementer freq: 1ms ticks */
 
 /*
  * For booting Linux, the board info and command line data
@@ -674,7 +671,6 @@
 
 #ifdef CONFIG_CMD_KGDB
 #define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
-#define CONFIG_KGDB_SER_INDEX	2	/* which serial port to use */
 #endif
 
 /*
@@ -700,8 +696,8 @@
 #define	CONFIG_EXTRA_ENV_SETTINGS				\
 	"hwconfig=fsl_ddr:ctlr_intlv=cacheline,"		\
 	"bank_intlv=cs0_cs1;"					\
-	"usb2:dr_mode=peripheral,phy_type=" __stringify(__USB_PHY_TYPE) ";"\
-	"usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
+	"usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) ";"\
+	"usb2:dr_mode=peripheral,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
 	"netdev=eth0\0"						\
 	"uboot=" __stringify(CONFIG_UBOOTPATH) "\0"		\
 	"ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"	\
@@ -745,8 +741,6 @@
 
 #define CONFIG_BOOTCOMMAND		CONFIG_HDBOOT
 
-#ifdef CONFIG_SECURE_BOOT
 #include <asm/fsl_secure_boot.h>
-#endif
 
 #endif	/* __CONFIG_H */
diff --git a/include/configs/corvus.h b/include/configs/corvus.h
new file mode 100644
index 0000000000..959e188d9a
--- /dev/null
+++ b/include/configs/corvus.h
@@ -0,0 +1,164 @@
+/*
+ * Common board functions for siemens AT91SAM9G45 based boards
+ * (C) Copyright 2013 Siemens AG
+ *
+ * Based on:
+ * U-Boot file: include/configs/at91sam9m10g45ek.h
+ * (C) Copyright 2007-2008
+ * Stelian Pop <stelian@popies.net>
+ * Lead Tech Design <www.leadtechdesign.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <asm/hardware.h>
+
+#define MACH_TYPE_CORVUS               2066
+
+/*
+ * Warning: changing CONFIG_SYS_TEXT_BASE requires
+ * adapting the initial boot program.
+ * Since the linker has to swallow that define, we must use a pure
+ * hex number here!
+ */
+
+#define CONFIG_SYS_TEXT_BASE  0x73f00000
+
+#define CONFIG_AT91_LEGACY
+#define CONFIG_ATMEL_LEGACY		/* required until (g)pio is fixed */
+
+/* ARM asynchronous clock */
+#define CONFIG_SYS_AT91_SLOW_CLOCK      32768
+#define CONFIG_SYS_AT91_MAIN_CLOCK      12000000 /* from 12 MHz crystal */
+
+#define CONFIG_AT91FAMILY
+
+#define CONFIG_CMDLINE_TAG		/* enable passing of ATAGs	*/
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+#define CONFIG_SKIP_LOWLEVEL_INIT
+#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_DISPLAY_CPUINFO
+
+#define CONFIG_CMD_BOOTZ
+#define CONFIG_OF_LIBFDT
+
+/* general purpose I/O */
+#define CONFIG_ATMEL_LEGACY		/* required until (g)pio is fixed */
+#define CONFIG_AT91_GPIO
+#define CONFIG_AT91_GPIO_PULLUP	1	/* keep pullups on peripheral pins */
+
+/* serial console */
+#define CONFIG_ATMEL_USART
+#define CONFIG_USART_BASE		ATMEL_BASE_DBGU
+#define CONFIG_USART_ID			ATMEL_ID_SYS
+
+/* LED */
+#define CONFIG_AT91_LED
+#define CONFIG_RED_LED		AT91_PIN_PD31	/* this is the user1 led */
+#define CONFIG_GREEN_LED	AT91_PIN_PD0	/* this is the user2 led */
+
+#define CONFIG_BOOTDELAY	3
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+#undef CONFIG_CMD_BDI
+#undef CONFIG_CMD_FPGA
+#undef CONFIG_CMD_IMI
+#undef CONFIG_CMD_IMLS
+#undef CONFIG_CMD_LOADS
+
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_NAND
+#define CONFIG_CMD_USB
+
+/* SDRAM */
+#define CONFIG_NR_DRAM_BANKS		1
+#define CONFIG_SYS_SDRAM_BASE           ATMEL_BASE_CS6
+#define CONFIG_SYS_SDRAM_SIZE		0x08000000
+
+#define CONFIG_SYS_INIT_SP_ADDR \
+	(CONFIG_SYS_SDRAM_BASE + 4 * 1024 - GENERATED_GBL_DATA_SIZE)
+
+/* No NOR flash */
+#define CONFIG_SYS_NO_FLASH
+
+/* NAND flash */
+#ifdef CONFIG_CMD_NAND
+#define CONFIG_NAND_ATMEL
+#define CONFIG_SYS_MAX_NAND_DEVICE		1
+#define CONFIG_SYS_NAND_BASE			ATMEL_BASE_CS3
+#define CONFIG_SYS_NAND_DBW_8
+/* our ALE is AD21 */
+#define CONFIG_SYS_NAND_MASK_ALE		(1 << 21)
+/* our CLE is AD22 */
+#define CONFIG_SYS_NAND_MASK_CLE		(1 << 22)
+#define CONFIG_SYS_NAND_ENABLE_PIN		AT91_PIN_PC14
+#define CONFIG_SYS_NAND_READY_PIN		AT91_PIN_PC8
+
+#endif
+
+/* Ethernet */
+#define CONFIG_MACB
+#define CONFIG_RMII
+#define CONFIG_NET_RETRY_COUNT		20
+#define CONFIG_AT91_WANTS_COMMON_PHY
+
+/* USB */
+#define CONFIG_USB_EHCI
+#define CONFIG_USB_EHCI_ATMEL
+#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS	2
+#define CONFIG_DOS_PARTITION
+#define CONFIG_USB_STORAGE
+
+#define CONFIG_SYS_LOAD_ADDR		0x72000000	/* load address */
+
+/* bootstrap + u-boot + env in nandflash */
+#define CONFIG_ENV_IS_IN_NAND
+#define CONFIG_ENV_OFFSET		0x100000
+#define CONFIG_ENV_OFFSET_REDUND	0x180000
+#define CONFIG_ENV_SIZE			0x20000
+
+#define CONFIG_BOOTCOMMAND						\
+	"nand read 0x70000000 0x200000 0x300000;"			\
+	"bootm 0x70000000"
+#define CONFIG_BOOTARGS							\
+	"console=ttyS0,115200 earlyprintk "				\
+	"mtdparts=atmel_nand:256k(bootstrap)ro,512k(uboot)ro,"		\
+	"256k(env),256k(env_redundant),256k(spare),"			\
+	"512k(dtb),6M(kernel)ro,-(rootfs) "				\
+	"root=/dev/mtdblock7 rw rootfstype=jffs2"
+
+#define CONFIG_BAUDRATE			115200
+
+#define CONFIG_SYS_PROMPT		"U-Boot> "
+#define CONFIG_SYS_CBSIZE		256
+#define CONFIG_SYS_MAXARGS		16
+#define CONFIG_SYS_PBSIZE	(CONFIG_SYS_CBSIZE +	\
+				 sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_CMDLINE_EDITING
+#define CONFIG_AUTO_COMPLETE
+#define CONFIG_SYS_HUSH_PARSER
+
+/*
+ * Size of malloc() pool
+ */
+#define CONFIG_SYS_MALLOC_LEN	ROUND(3 * CONFIG_ENV_SIZE + \
+				128*1024, 0x1000)
+
+#endif
diff --git a/include/configs/cpci5200.h b/include/configs/cpci5200.h
index eb56f96988..ec926fd22d 100644
--- a/include/configs/cpci5200.h
+++ b/include/configs/cpci5200.h
@@ -23,8 +23,7 @@
  * (easy to change)
  */
 
-#define CONFIG_MPC5200		1	/* This is an MPC5xxx CPU */
-#define CONFIG_MPC5xxx		1	/* This is an MPC5xxx CPU */
+#define CONFIG_MPC5200		1	/* This is an MPC5200 CPU */
 #define CONFIG_ICECUBE		1	/* ... on IceCube board	  */
 #define CONFIG_CPCI5200		1	/* ... on CPCI5200  board */
 #define CONFIG_MPC5200_DDR	1	/* ... use DDR RAM	  */
@@ -253,7 +252,6 @@
  * Miscellaneous configurable options
  */
 #define CONFIG_SYS_LONGHELP		/* undef to save memory	    */
-#define CONFIG_SYS_PROMPT		"=> "	/* Monitor Command Prompt   */
 #if defined(CONFIG_CMD_KGDB)
 #define CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size  */
 #else
@@ -268,8 +266,6 @@
 
 #define CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address */
 
-#define CONFIG_SYS_HZ			1000	/* decrementer freq: 1 ms ticks */
-
 #define CONFIG_SYS_VXWORKS_MAC_PTR	0x00000000	/* Pass Ethernet MAC to VxWorks */
 
 #define CONFIG_SYS_CACHELINE_SIZE	32	/* For MPC5xxx CPUs */
diff --git a/include/configs/cpu9260.h b/include/configs/cpu9260.h
index 5b79ace5fa..39f7062388 100644
--- a/include/configs/cpu9260.h
+++ b/include/configs/cpu9260.h
@@ -20,7 +20,6 @@
 #define AT91_DBGU	(0xfffff200 - AT91_BASE_SYS)
 
 #define CONFIG_SYS_AT91_MAIN_CLOCK	18432000
-#define CONFIG_SYS_HZ		1000
 #define CONFIG_SYS_AT91_SLOW_CLOCK	32768
 
 #if defined(CONFIG_CPU9G20)
@@ -281,8 +280,8 @@
 #define CONFIG_SYS_MAX_NAND_DEVICE		1
 #define CONFIG_SYS_NAND_BASE			0x40000000
 #define CONFIG_SYS_NAND_DBW_8			1
-#define CONFIG_SYS_NAND_READY_PIN		AT91_PIO_PORTC, 13
-#define CONFIG_SYS_NAND_ENABLE_PIN		AT91_PIO_PORTC, 14
+#define CONFIG_SYS_NAND_READY_PIN		GPIO_PIN_PC(13)
+#define CONFIG_SYS_NAND_ENABLE_PIN		GPIO_PIN_PC(14)
 #define CONFIG_SYS_NAND_MASK_ALE		(1 << 21)
 #define CONFIG_SYS_NAND_MASK_CLE		(1 << 22)
 
@@ -311,6 +310,7 @@
 #define CONFIG_RMII
 #define CONFIG_NET_RETRY_COUNT			20
 #define CONFIG_MACB_SEARCH_PHY
+#define CONFIG_AT91_WANTS_COMMON_PHY
 
 /* LEDS */
 /* Status LED */
@@ -346,6 +346,7 @@
 
 /* USB */
 #define CONFIG_USB_ATMEL
+#define CONFIG_USB_ATMEL_CLK_SEL_PLLB
 #define CONFIG_USB_OHCI_NEW
 #define CONFIG_DOS_PARTITION
 #define CONFIG_SYS_USB_OHCI_CPU_INIT
diff --git a/include/configs/cpuat91.h b/include/configs/cpuat91.h
index 6742dbcd92..ce521012f2 100644
--- a/include/configs/cpuat91.h
+++ b/include/configs/cpuat91.h
@@ -10,7 +10,7 @@
 #ifndef _CONFIG_CPUAT91_H
 #define _CONFIG_CPUAT91_H
 
-#include <asm/sizes.h>
+#include <linux/sizes.h>
 
 #ifdef CONFIG_RAMBOOT
 #define CONFIG_SKIP_LOWLEVEL_INIT
@@ -25,7 +25,6 @@
 #define AT91C_MAIN_CLOCK		((AT91C_XTAL_CLOCK / 4) * 39)
 #define AT91C_MASTER_CLOCK		(AT91C_MAIN_CLOCK / 3)
 #define CONFIG_SYS_HZ_CLOCK		(AT91C_MASTER_CLOCK / 2)
-#define CONFIG_SYS_HZ			1000
 
 #define CONFIG_ARM920T
 #define CONFIG_AT91RM9200
@@ -160,6 +159,7 @@
 
 #if defined(CONFIG_CMD_USB)
 #define CONFIG_USB_ATMEL
+#define CONFIG_USB_ATMEL_CLK_SEL_PLLB
 #define CONFIG_USB_OHCI_NEW
 #define CONFIG_USB_STORAGE
 #define CONFIG_DOS_PARTITION
diff --git a/include/configs/csb272.h b/include/configs/csb272.h
index 6ae19e4b87..a5c6f8474b 100644
--- a/include/configs/csb272.h
+++ b/include/configs/csb272.h
@@ -18,7 +18,6 @@
  */
 
 #define CONFIG_405GP		1	/* This is a PPC405GP CPU	*/
-#define CONFIG_4xx		1	/* ...member of PPC4xx family   */
 #define CONFIG_CSB272		1	/* on a Cogent CSB272 board     */
 #define CONFIG_BOARD_EARLY_INIT_F 1	/* Call board_early_init_f()    */
 #define CONFIG_LAST_STAGE_INIT	1	/* Call last_stage_init()	*/
@@ -99,7 +98,6 @@
  */
 #if defined(CONFIG_CMD_KGDB)
 #define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
-#define CONFIG_KGDB_SER_INDEX	2	/* which serial port to use */
 #endif
 
 /*
@@ -109,7 +107,6 @@
 #undef	CONFIG_SYS_HUSH_PARSER			/* use "hush" command parser */
 
 #define CONFIG_SYS_LONGHELP			/* undef to save memory	*/
-#define CONFIG_SYS_PROMPT		"=> "	/* Monitor Command Prompt */
 #if defined(CONFIG_CMD_KGDB)
 #define	CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size */
 #else
@@ -121,8 +118,6 @@
 
 #define CONFIG_SYS_MEMTEST_START	0x0400000 /* memtest works on */
 #define CONFIG_SYS_MEMTEST_END		0x0C00000 /* 4 ... 12 MB in DRAM */
-
-#define	CONFIG_SYS_HZ			1000	/* decrementer freq: 1 ms ticks	*/
 #define CONFIG_SYS_EXTBDINFO		1	/* To use extended board_info (bd_t) */
 #define CONFIG_SYS_LOAD_ADDR		0x100000 /* default load address */
 
diff --git a/include/configs/csb472.h b/include/configs/csb472.h
index 0c467c51f8..6aa98efd4e 100644
--- a/include/configs/csb472.h
+++ b/include/configs/csb472.h
@@ -18,7 +18,6 @@
  */
 
 #define CONFIG_405GP		1	/* This is a PPC405GP CPU	*/
-#define CONFIG_4xx		1	/* ...member of PPC4xx family   */
 #define CONFIG_CSB472		1	/* on a Cogent CSB472 board     */
 #define CONFIG_BOARD_EARLY_INIT_F 1	/* Call board_early_init_f()    */
 #define CONFIG_LAST_STAGE_INIT	1	/* Call last_stage_init()	*/
@@ -98,7 +97,6 @@
  */
 #if defined(CONFIG_CMD_KGDB)
 #define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
-#define CONFIG_KGDB_SER_INDEX	2	/* which serial port to use */
 #endif
 
 /*
@@ -108,7 +106,6 @@
 #undef	CONFIG_SYS_HUSH_PARSER			/* use "hush" command parser */
 
 #define CONFIG_SYS_LONGHELP			/* undef to save memory	*/
-#define CONFIG_SYS_PROMPT		"=> "	/* Monitor Command Prompt */
 #if defined(CONFIG_CMD_KGDB)
 #define	CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size */
 #else
@@ -121,7 +118,6 @@
 #define CONFIG_SYS_MEMTEST_START	0x0400000 /* memtest works on */
 #define CONFIG_SYS_MEMTEST_END		0x0C00000 /* 4 ... 12 MB in DRAM */
 
-#define	CONFIG_SYS_HZ			1000	/* decrementer freq: 1 ms ticks	*/
 #define CONFIG_SYS_EXTBDINFO		1	/* To use extended board_info (bd_t) */
 #define CONFIG_SYS_LOAD_ADDR		0x100000 /* default load address */
 
diff --git a/include/configs/da830evm.h b/include/configs/da830evm.h
index 3e71ae5a3e..c4cc62ecb4 100644
--- a/include/configs/da830evm.h
+++ b/include/configs/da830evm.h
@@ -28,7 +28,6 @@
 #define CONFIG_SYS_OSCIN_FREQ		24000000
 #define CONFIG_SYS_TIMERBASE		DAVINCI_TIMER0_BASE
 #define CONFIG_SYS_HZ_CLOCK		clk_get(DAVINCI_AUXCLK_CLKID)
-#define CONFIG_SYS_HZ			1000
 #define CONFIG_SKIP_LOWLEVEL_INIT
 #define CONFIG_SYS_TEXT_BASE		0xc1080000
 
diff --git a/include/configs/da850evm.h b/include/configs/da850evm.h
index 9845506039..509fe20d2c 100644
--- a/include/configs/da850evm.h
+++ b/include/configs/da850evm.h
@@ -33,7 +33,6 @@
 #define CONFIG_SYS_OSCIN_FREQ		24000000
 #define CONFIG_SYS_TIMERBASE		DAVINCI_TIMER0_BASE
 #define CONFIG_SYS_HZ_CLOCK		clk_get(DAVINCI_AUXCLK_CLKID)
-#define CONFIG_SYS_HZ			1000
 #define CONFIG_SYS_DA850_PLL_INIT
 #define CONFIG_SYS_DA850_DDR_INIT
 
diff --git a/include/configs/dalmore.h b/include/configs/dalmore.h
index bdf012b2b8..fd774a3314 100644
--- a/include/configs/dalmore.h
+++ b/include/configs/dalmore.h
@@ -17,7 +17,7 @@
 #ifndef __CONFIG_H
 #define __CONFIG_H
 
-#include <asm/sizes.h>
+#include <linux/sizes.h>
 
 #include "tegra114-common.h"
 
diff --git a/include/configs/davinci_dm355evm.h b/include/configs/davinci_dm355evm.h
index 07b1bdd082..6382e75b95 100644
--- a/include/configs/davinci_dm355evm.h
+++ b/include/configs/davinci_dm355evm.h
@@ -18,7 +18,6 @@
 #define CONFIG_ARM926EJS				/* arm926ejs CPU */
 #define CONFIG_SYS_TIMERBASE		0x01c21400	/* use timer 0 */
 #define CONFIG_SYS_HZ_CLOCK		24000000	/* timer0 freq */
-#define CONFIG_SYS_HZ			1000
 #define CONFIG_SOC_DM355
 
 /* Memory Info */
diff --git a/include/configs/davinci_dm355leopard.h b/include/configs/davinci_dm355leopard.h
index f7adbd86ce..234bbc0996 100644
--- a/include/configs/davinci_dm355leopard.h
+++ b/include/configs/davinci_dm355leopard.h
@@ -17,7 +17,6 @@
 #define CONFIG_ARM926EJS				/* arm926ejs CPU */
 #define CONFIG_SYS_TIMERBASE		0x01c21400	/* use timer 0 */
 #define CONFIG_SYS_HZ_CLOCK		24000000	/* timer0 freq */
-#define CONFIG_SYS_HZ			1000
 #define CONFIG_SOC_DM355				/* DM355 based board */
 
 /* Memory Info */
diff --git a/include/configs/davinci_dm365evm.h b/include/configs/davinci_dm365evm.h
index 1f49e514ac..b547289d2d 100644
--- a/include/configs/davinci_dm365evm.h
+++ b/include/configs/davinci_dm365evm.h
@@ -18,7 +18,6 @@
 #define CONFIG_ARM926EJS				/* arm926ejs CPU */
 #define CONFIG_SYS_TIMERBASE		0x01c21400	/* use timer 0 */
 #define CONFIG_SYS_HZ_CLOCK		24000000	/* timer0 freq */
-#define CONFIG_SYS_HZ			1000
 #define CONFIG_SOC_DM365
 
 /* Memory Info */
diff --git a/include/configs/davinci_dm6467evm.h b/include/configs/davinci_dm6467evm.h
index 7f57877752..2132342eb7 100644
--- a/include/configs/davinci_dm6467evm.h
+++ b/include/configs/davinci_dm6467evm.h
@@ -27,7 +27,6 @@ extern unsigned int davinci_arm_clk_get(void);
 /* Timer Input clock freq */
 #define CONFIG_SYS_HZ_CLOCK		(CONFIG_SYS_CLK_FREQ/2)
 #define CONFIG_SYS_TIMERBASE		0x01c21400	/* use timer 0 */
-#define CONFIG_SYS_HZ			1000
 #define CONFIG_SOC_DM646X
 
 /* EEPROM definitions for EEPROM */
diff --git a/include/configs/davinci_dvevm.h b/include/configs/davinci_dvevm.h
index ca2cb2db72..d8fa64600a 100644
--- a/include/configs/davinci_dvevm.h
+++ b/include/configs/davinci_dvevm.h
@@ -44,7 +44,6 @@
 #define CONFIG_ARM926EJS			/* arm926ejs CPU core */
 #define CONFIG_SYS_TIMERBASE		0x01c21400	/* use timer 0 */
 #define CONFIG_SYS_HZ_CLOCK		27000000	/* Timer Input clock freq */
-#define CONFIG_SYS_HZ			1000
 #define CONFIG_SOC_DM644X
 /*====================================================*/
 /* EEPROM definitions for Atmel 24C256BN SEEPROM chip */
diff --git a/include/configs/davinci_schmoogie.h b/include/configs/davinci_schmoogie.h
index 299a2e8bb2..f9a0a76d36 100644
--- a/include/configs/davinci_schmoogie.h
+++ b/include/configs/davinci_schmoogie.h
@@ -22,7 +22,6 @@
 #define CONFIG_ARM926EJS			/* arm926ejs CPU core */
 #define CONFIG_SYS_TIMERBASE		0x01c21400	/* use timer 0 */
 #define CONFIG_SYS_HZ_CLOCK		27000000	/* Timer Input clock freq */
-#define CONFIG_SYS_HZ			1000
 #define CONFIG_SOC_DM644X
 /*=============*/
 /* Memory Info */
diff --git a/include/configs/davinci_sffsdr.h b/include/configs/davinci_sffsdr.h
index 6ebbe818a5..44449df9cd 100644
--- a/include/configs/davinci_sffsdr.h
+++ b/include/configs/davinci_sffsdr.h
@@ -19,7 +19,6 @@
 #define CONFIG_ARM926EJS			/* arm926ejs CPU core */
 #define CONFIG_SYS_TIMERBASE		0x01c21400	/* use timer 0 */
 #define CONFIG_SYS_HZ_CLOCK		27000000	/* Timer Input clock freq */
-#define CONFIG_SYS_HZ			1000
 #define CONFIG_SOC_DM644X
 /* EEPROM definitions for Atmel 24LC64 EEPROM chip */
 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		2
diff --git a/include/configs/davinci_sonata.h b/include/configs/davinci_sonata.h
index a81364ce55..ac543f8d94 100644
--- a/include/configs/davinci_sonata.h
+++ b/include/configs/davinci_sonata.h
@@ -46,7 +46,6 @@
 #define CONFIG_ARM926EJS			/* arm926ejs CPU core */
 #define CONFIG_SYS_TIMERBASE		0x01c21400	/* use timer 0 */
 #define CONFIG_SYS_HZ_CLOCK		27000000	/* Timer Input clock freq */
-#define CONFIG_SYS_HZ			1000
 #define CONFIG_SOC_DM644X
 /*====================================================*/
 /* EEPROM definitions for Atmel 24C256BN SEEPROM chip */
diff --git a/include/configs/dbau1x00.h b/include/configs/dbau1x00.h
index 07c60abec4..e0bf3dc61e 100644
--- a/include/configs/dbau1x00.h
+++ b/include/configs/dbau1x00.h
@@ -12,7 +12,6 @@
 #ifndef __CONFIG_H
 #define __CONFIG_H
 
-#define CONFIG_MIPS32		1  /* MIPS32 CPU core	*/
 #define CONFIG_DBAU1X00		1
 #define CONFIG_SOC_AU1X00	1  /* alchemy series cpu */
 
@@ -133,8 +132,6 @@
 
 #define CONFIG_SYS_MIPS_TIMER_FREQ	(CONFIG_SYS_MHZ * 1000000)
 
-#define CONFIG_SYS_HZ			1000
-
 #define CONFIG_SYS_SDRAM_BASE		0x80000000     /* Cached addr */
 
 #define	CONFIG_SYS_LOAD_ADDR		0x81000000     /* default load address	*/
diff --git a/include/configs/debris.h b/include/configs/debris.h
index c9fb8d78cb..4631b8621a 100644
--- a/include/configs/debris.h
+++ b/include/configs/debris.h
@@ -94,7 +94,6 @@
  * (easy to change)
  */
 
-#define CONFIG_MPC824X		1
 #define CONFIG_MPC8245		1
 #define CONFIG_DEBRIS		1
 
@@ -143,13 +142,11 @@
  * Miscellaneous configurable options
  */
 #define CONFIG_SYS_LONGHELP		1		/* undef to save memory		*/
-#define CONFIG_SYS_PROMPT		"=> "		/* Monitor Command Prompt	*/
 #define CONFIG_SYS_CBSIZE		256		/* Console I/O Buffer Size	*/
 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)	/* Print Buffer Size	*/
 #define CONFIG_SYS_MAXARGS		16		/* max number of command args	*/
 #define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
 #define CONFIG_SYS_LOAD_ADDR		0x00100000	/* default load address		*/
-#define CONFIG_SYS_HZ			1000		/* decrementer freq: 1 ms ticks */
 
 /*-----------------------------------------------------------------------
  * PCI stuff
diff --git a/include/configs/devkit3250.h b/include/configs/devkit3250.h
index ed8ba1abc4..bd96a7d3f4 100644
--- a/include/configs/devkit3250.h
+++ b/include/configs/devkit3250.h
@@ -10,7 +10,7 @@
 #define __CONFIG_DEVKIT3250_H__
 
 /* SoC and board defines */
-#include <asm/sizes.h>
+#include <linux/sizes.h>
 #include <asm/arch/cpu.h>
 
 /*
@@ -29,7 +29,6 @@
  */
 #define CONFIG_NR_DRAM_BANKS		1
 #define CONFIG_SYS_MALLOC_LEN		SZ_1M
-#define CONFIG_SYS_GBL_DATA_SIZE	128
 #define CONFIG_SYS_SDRAM_BASE		EMC_DYCS0_BASE
 #define CONFIG_SYS_SDRAM_SIZE		SZ_64M
 #define CONFIG_SYS_TEXT_BASE		0x83FA0000
@@ -61,7 +60,6 @@
  * U-Boot General Configurations
  */
 #define CONFIG_SYS_LONGHELP
-#define CONFIG_SYS_PROMPT		"=> "
 #define CONFIG_SYS_CBSIZE		1024
 #define CONFIG_SYS_PBSIZE		\
 	(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
diff --git a/include/configs/devkit8000.h b/include/configs/devkit8000.h
index c1e996e448..16a00ebe86 100644
--- a/include/configs/devkit8000.h
+++ b/include/configs/devkit8000.h
@@ -90,10 +90,10 @@
 #define CONFIG_DOS_PARTITION		1
 
 /* I2C */
-#define CONFIG_HARD_I2C			1
-#define CONFIG_SYS_I2C_SPEED		100000
-#define CONFIG_SYS_I2C_SLAVE		1
-#define CONFIG_DRIVER_OMAP34XX_I2C	1
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_OMAP24_I2C_SPEED	100000
+#define CONFIG_SYS_OMAP24_I2C_SLAVE	1
+#define CONFIG_SYS_I2C_OMAP34XX
 
 /* TWL4030 */
 #define CONFIG_TWL4030_POWER		1
@@ -116,8 +116,6 @@
 #define CONFIG_SYS_NAND_BASE		NAND_BASE	/* physical address */
 							/* to access nand at */
 							/* CS0 */
-#define GPMC_NAND_ECC_LP_x16_LAYOUT	1
-
 #define CONFIG_SYS_MAX_NAND_DEVICE	1		/* Max number of NAND */
 							/* devices */
 #define CONFIG_JFFS2_NAND
@@ -257,7 +255,6 @@
  */
 #define CONFIG_SYS_TIMERBASE		(OMAP34XX_GPT2)
 #define CONFIG_SYS_PTV			2 /* Divisor: 2^(PTV+1) => 8 */
-#define CONFIG_SYS_HZ			1000
 
 /*  Physical Memory Map  */
 #define CONFIG_NR_DRAM_BANKS		2 /* CS1 may or may not be populated */
@@ -328,6 +325,7 @@
 
 #define CONFIG_SYS_NAND_ECCSIZE		512
 #define CONFIG_SYS_NAND_ECCBYTES	3
+#define CONFIG_NAND_OMAP_ECCSCHEME	OMAP_ECC_HAM1_CODE_HW
 
 #define CONFIG_SYS_NAND_U_BOOT_START   CONFIG_SYS_TEXT_BASE
 
diff --git a/include/configs/dig297.h b/include/configs/dig297.h
index 08d49fb00d..af6f56bb34 100644
--- a/include/configs/dig297.h
+++ b/include/configs/dig297.h
@@ -123,10 +123,10 @@
 #undef CONFIG_CMD_NFS		/* NFS support			*/
 
 #define CONFIG_SYS_NO_FLASH
-#define CONFIG_HARD_I2C
-#define CONFIG_SYS_I2C_SPEED		100000
-#define CONFIG_SYS_I2C_SLAVE		1
-#define CONFIG_DRIVER_OMAP34XX_I2C	1
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_OMAP24_I2C_SPEED	100000
+#define CONFIG_SYS_OMAP24_I2C_SLAVE	1
+#define CONFIG_SYS_I2C_OMAP34XX
 
 /*
  * TWL4030
@@ -143,8 +143,6 @@
 #define CONFIG_SYS_NAND_BASE		NAND_BASE	/* physical address */
 							/* to access nand at */
 							/* CS0 */
-#define GPMC_NAND_ECC_LP_x16_LAYOUT
-
 #define CONFIG_SYS_MAX_NAND_DEVICE	1		/* Max number of NAND */
 
 #if defined(CONFIG_CMD_NET)
@@ -239,7 +237,6 @@
  */
 #define CONFIG_SYS_TIMERBASE		(OMAP34XX_GPT2)
 #define CONFIG_SYS_PTV			2       /* Divisor: 2^(PTV+1) => 8 */
-#define CONFIG_SYS_HZ			1000
 
 /*-----------------------------------------------------------------------
  * Physical Memory Map
diff --git a/include/configs/digsy_mtc.h b/include/configs/digsy_mtc.h
index a5215db298..2a8cb3940b 100644
--- a/include/configs/digsy_mtc.h
+++ b/include/configs/digsy_mtc.h
@@ -20,8 +20,7 @@
  * High Level Configuration Options
  */
 
-#define CONFIG_MPC5xxx		1	/* This is an MPC5xxx CPU */
-#define CONFIG_MPC5200		1	/* (more precisely an MPC5200 CPU) */
+#define CONFIG_MPC5200		1	/* This is an MPC5200 CPU */
 #define CONFIG_DIGSY_MTC	1	/* ... on InterControl digsyMTC board */
 
 /*
@@ -393,7 +392,6 @@
 #define CONFIG_SYS_LONGHELP
 #define CONFIG_AUTO_COMPLETE	1
 #define CONFIG_CMDLINE_EDITING	1
-#define CONFIG_SYS_PROMPT	"=> "
 #define CONFIG_SYS_HUSH_PARSER
 
 #define CONFIG_AUTOBOOT_KEYED
@@ -416,8 +414,6 @@
 
 #define CONFIG_SYS_LOAD_ADDR		0x00100000
 
-#define CONFIG_SYS_HZ			1000
-
 /*
  * Various low-level settings
  */
diff --git a/include/configs/dlvision-10g.h b/include/configs/dlvision-10g.h
index c527be4909..78778970f4 100644
--- a/include/configs/dlvision-10g.h
+++ b/include/configs/dlvision-10g.h
@@ -9,7 +9,6 @@
 #define __CONFIG_H
 
 #define CONFIG_405EP		1	/* this is a PPC405 CPU */
-#define CONFIG_4xx		1	/*  member of PPC4xx family */
 #define CONFIG_DLVISION_10G	1	/*  on a DLVision-10G board */
 
 #define	CONFIG_SYS_TEXT_BASE	0xFFFC0000
@@ -218,9 +217,8 @@
 #define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_OCM_DATA_ADDR /* in SDRAM */
 #define CONFIG_SYS_INIT_RAM_END	CONFIG_SYS_OCM_DATA_SIZE /* End of used area */
 
-#define CONFIG_SYS_GBL_DATA_SIZE	128  /* size/bytes res'd for init data*/
 #define CONFIG_SYS_GBL_DATA_OFFSET \
-	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+	(CONFIG_SYS_INIT_RAM_END - GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 /*
diff --git a/include/configs/dlvision.h b/include/configs/dlvision.h
index c97963a3f8..1e86c556ab 100644
--- a/include/configs/dlvision.h
+++ b/include/configs/dlvision.h
@@ -9,7 +9,6 @@
 #define __CONFIG_H
 
 #define CONFIG_405EP		1	/* this is a PPC405 CPU */
-#define CONFIG_4xx		1	/*  member of PPC4xx family */
 #define CONFIG_DLVISION	        1	/*  on a Neo board */
 
 #define	CONFIG_SYS_TEXT_BASE	0xFFFC0000
diff --git a/include/configs/dnp5370.h b/include/configs/dnp5370.h
index f2f41028eb..4f2c742a5d 100644
--- a/include/configs/dnp5370.h
+++ b/include/configs/dnp5370.h
@@ -85,8 +85,8 @@
 
 #define ENV_IS_EMBEDDED
 #define LDS_BOARD_TEXT \
-	arch/blackfin/lib/libblackfin.o (.text*); \
-	arch/blackfin/cpu/libblackfin.o (.text*); \
+	arch/blackfin/lib/built-in.o (.text*); \
+	arch/blackfin/cpu/built-in.o (.text*); \
 	. = DEFINED(env_offset) ? env_offset : .; \
 	common/env_embedded.o (.text*);
 
@@ -103,6 +103,7 @@
 #define CONFIG_DNP5370_EXT_WD_DISABLE 1
 
 #define CONFIG_UART_CONSOLE 0
+#define CONFIG_BFIN_SERIAL
 #define CONFIG_BAUDRATE     115200
 #define CONFIG_BOOTCOMMAND  "bootm 0x20030000"
 #define CONFIG_BOOTARGS     "console=ttyBF0,115200 root=/dev/mtdblock3 rootfstype=ext2"
diff --git a/include/configs/dns325.h b/include/configs/dns325.h
index 0f0dd21c23..96db44f518 100644
--- a/include/configs/dns325.h
+++ b/include/configs/dns325.h
@@ -52,7 +52,6 @@
 
 /* Remove or override few declarations from mv-common.h */
 #undef CONFIG_SYS_PROMPT
-#define CONFIG_SYS_PROMPT		"=> "
 
 /*
  * Ethernet Driver configuration
diff --git a/include/configs/dra7xx_evm.h b/include/configs/dra7xx_evm.h
index 3a4c06bc8f..291c538a34 100644
--- a/include/configs/dra7xx_evm.h
+++ b/include/configs/dra7xx_evm.h
@@ -4,7 +4,7 @@
  * Lokesh Vutla	  <lokeshvutla@ti.com>
  *
  * Configuration settings for the TI DRA7XX board.
- * See omap5_common.h for omap5 common settings.
+ * See ti_omap5_common.h for omap5 common settings.
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */
@@ -22,14 +22,30 @@
 #define CONFIG_SYS_REDUNDAND_ENVIRONMENT
 #define CONFIG_CMD_SAVEENV
 
+#if (CONFIG_CONS_INDEX == 1)
 #define CONSOLEDEV			"ttyO0"
-#define CONFIG_CONS_INDEX		1
-#define CONFIG_SYS_NS16550_COM1		UART1_BASE
+#elif (CONFIG_CONS_INDEX == 3)
+#define CONSOLEDEV			"ttyO2"
+#endif
+#define CONFIG_SYS_NS16550_COM1		UART1_BASE	/* Base EVM has UART0 */
+#define CONFIG_SYS_NS16550_COM2		UART2_BASE	/* UART2 */
+#define CONFIG_SYS_NS16550_COM3		UART3_BASE	/* UART3 */
 #define CONFIG_BAUDRATE			115200
 
 #define CONFIG_SYS_OMAP_ABE_SYSCK
 
-#include <configs/omap5_common.h>
+/* Define the default GPT table for eMMC */
+#define PARTS_DEFAULT \
+	"uuid_disk=${uuid_gpt_disk};" \
+	"name=rootfs,start=2MiB,size=-,uuid=${uuid_gpt_rootfs}"
+
+#include <configs/ti_omap5_common.h>
+
+/* Enhance our eMMC support / experience. */
+#define CONFIG_CMD_GPT
+#define CONFIG_EFI_PARTITION
+#define CONFIG_PARTITION_UUIDS
+#define CONFIG_CMD_PART
 
 /* CPSW Ethernet */
 #define CONFIG_CMD_NET			/* 'bootp' and 'tftp' */
@@ -46,7 +62,6 @@
 #define CONFIG_MII			/* Required in net/eth.c */
 #define CONFIG_PHY_GIGE			/* per-board part of CPSW */
 #define CONFIG_PHYLIB
-#define CONFIG_PHY_ADDR			2
 
 /* SPI */
 #undef	CONFIG_OMAP3_SPI
@@ -55,6 +70,7 @@
 #define CONFIG_SPI_FLASH_SPANSION
 #define CONFIG_CMD_SF
 #define CONFIG_CMD_SPI
+#define CONFIG_SPI_FLASH_BAR
 #define CONFIG_TI_SPI_MMAP
 #define CONFIG_SF_DEFAULT_SPEED                48000000
 #define CONFIG_DEFAULT_SPI_MODE                SPI_MODE_3
@@ -67,4 +83,28 @@
 #define CONFIG_SPL_SPI_CS              0
 #define CONFIG_SYS_SPI_U_BOOT_OFFS     0x20000
 
+#define CONFIG_SUPPORT_EMMC_BOOT
+
+/* USB xHCI HOST */
+#define CONFIG_CMD_USB
+#define CONFIG_USB_HOST
+#define CONFIG_USB_XHCI
+#define CONFIG_USB_XHCI_OMAP
+#define CONFIG_USB_STORAGE
+#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2
+
+#define CONFIG_OMAP_USB_PHY
+#define CONFIG_OMAP_USB2PHY2_HOST
+
+/* SATA */
+#define CONFIG_BOARD_LATE_INIT
+#define CONFIG_CMD_SCSI
+#define CONFIG_LIBATA
+#define CONFIG_SCSI_AHCI
+#define CONFIG_SCSI_AHCI_PLAT
+#define CONFIG_SYS_SCSI_MAX_SCSI_ID	1
+#define CONFIG_SYS_SCSI_MAX_LUN		1
+#define CONFIG_SYS_SCSI_MAX_DEVICE	(CONFIG_SYS_SCSI_MAX_SCSI_ID * \
+						CONFIG_SYS_SCSI_MAX_LUN)
+
 #endif /* __CONFIG_DRA7XX_EVM_H */
diff --git a/include/configs/dvlhost.h b/include/configs/dvlhost.h
deleted file mode 100644
index 141879540f..0000000000
--- a/include/configs/dvlhost.h
+++ /dev/null
@@ -1,226 +0,0 @@
-/*
- * (C) Copyright 2009
- * Michael Schwingen, michael@schwingen.org
- *
- * Configuration settings for the
- * dLAN200 AV Wireless G ("dvlhost") board.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#define CONFIG_IXP425			1
-#define CONFIG_DVLHOST			1
-
-#define	CONFIG_MACH_TYPE		1343
-
-#define CONFIG_DISPLAY_CPUINFO		1
-#define CONFIG_DISPLAY_BOARDINFO	1
-
-#define CONFIG_IXP_SERIAL
-#define CONFIG_SYS_IXP425_CONSOLE	IXP425_UART2
-#define CONFIG_BAUDRATE			115200
-#define CONFIG_BOOTDELAY		3
-#define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */
-#define CONFIG_BOARD_EARLY_INIT_F	1
-#define CONFIG_SYS_LDSCRIPT	"board/dvlhost/u-boot.lds"
-
-/***************************************************************
- * U-boot generic defines start here.
- ***************************************************************/
-/* Size of malloc() pool */
-#define CONFIG_SYS_MALLOC_LEN			(CONFIG_ENV_SIZE + 128*1024)
-
-/* allow to overwrite serial and ethaddr */
-#define CONFIG_ENV_OVERWRITE
-
-/* Command line configuration. */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_ELF
-#define CONFIG_PCI
-#ifdef CONFIG_PCI
-#define CONFIG_CMD_PCI
-#define CONFIG_PCI_PNP
-#define CONFIG_IXP_PCI
-#define CONFIG_PCI_SCAN_SHOW
-#define CONFIG_CMD_PCI_ENUM
-#endif
-
-#define CONFIG_BOOTCOMMAND		"run boot_flash"
-/* enable passing of ATAGs */
-#define CONFIG_CMDLINE_TAG		1
-#define CONFIG_SETUP_MEMORY_TAGS	1
-#define CONFIG_INITRD_TAG		1
-
-#if defined(CONFIG_CMD_KGDB)
-# define CONFIG_KGDB_BAUDRATE		230400
-/* which serial port to use */
-# define CONFIG_KGDB_SER_INDEX		1
-#endif
-
-/* Miscellaneous configurable options */
-#define CONFIG_SYS_LONGHELP
-#define CONFIG_SYS_PROMPT		"=> "
-/* Console I/O Buffer Size */
-#define CONFIG_SYS_CBSIZE		256
-/* Print Buffer Size */
-#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
-/* max number of command args */
-#define CONFIG_SYS_MAXARGS		16
-/* Boot Argument Buffer Size */
-#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE
-
-#define CONFIG_SYS_MEMTEST_START	0x00000000
-#define CONFIG_SYS_MEMTEST_END		0x01D80000
-
-/* timer clock - 2* OSC_IN system clock */
-#define CONFIG_IXP425_TIMER_CLK         66666666
-#define CONFIG_SYS_HZ			1000
-
-/* default load address */
-#define CONFIG_SYS_LOAD_ADDR		0x00010000
-
-/* valid baudrates */
-#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, \
-					  115200, 230400 }
-#define CONFIG_SERIAL_RTS_ACTIVE	1
-
-/* Expansion bus settings */
-#define CONFIG_SYS_EXP_CS0		0xbd113442
-
-/* SDRAM settings */
-#define CONFIG_NR_DRAM_BANKS		1
-#define PHYS_SDRAM_1			0x00000000
-#define CONFIG_SYS_SDRAM_BASE		0x00000000
-
-/* 32MB SDRAM: 2* 8Mx16, CL3 */
-#define CONFIG_SYS_SDR_CONFIG		0x18
-#define PHYS_SDRAM_1_SIZE		0x02000000
-#define CONFIG_SYS_SDRAM_REFRESH_CNT	0x800
-#define CONFIG_SYS_SDR_MODE_CONFIG	0x1
-#define CONFIG_SYS_DRAM_SIZE		PHYS_SDRAM_1_SIZE
-
-/* FLASH organization: one Spansion S29AL032D-04 Flash */
-#define CONFIG_SYS_TEXT_BASE		0x50000000
-#define CONFIG_SYS_MAX_FLASH_BANKS	1
-/* max number of sectors on one chip */
-#define CONFIG_SYS_MAX_FLASH_SECT	140
-#define PHYS_FLASH_1			0x50000000
-#define CONFIG_SYS_FLASH_BANKS_LIST	{ PHYS_FLASH_1 }
-
-#define CONFIG_SYS_FLASH_BASE		PHYS_FLASH_1
-#define CONFIG_SYS_MONITOR_BASE		PHYS_FLASH_1
-#define CONFIG_SYS_MONITOR_LEN		(256 << 10)
-#define CONFIG_BOARD_SIZE_LIMIT         262144
-
-/* Use common CFI driver */
-#define CONFIG_SYS_FLASH_CFI
-#define CONFIG_FLASH_CFI_DRIVER
-/* no byte writes on IXP4xx */
-#define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_16BIT
-
-/* print 'E' for empty sector on flinfo */
-#define CONFIG_SYS_FLASH_EMPTY_INFO
-
-/* Ethernet */
-
-/* include IXP4xx NPE support */
-#define CONFIG_IXP4XX_NPE		1
-
-/* NPE0 PHY: MII dLAN200 AVmodule, 100BaseT-FDX fixed */
-#define	CONFIG_PHY_ADDR			0x18
-/* NPE1 PHY: MII IP175 switch, port 5 is host port */
-#define	CONFIG_PHY1_ADDR		0x05
-/* MII PHY management */
-#define CONFIG_MII			1
-/* fixed-speed powerline modem without standard PHY registers on MII */
-#define CONFIG_MII_NPE0_FIXEDLINK       1
-#define CONFIG_MII_NPE0_SPEED           100
-#define CONFIG_MII_NPE0_FULLDUPLEX      1
-/* fixed-speed switch without standard PHY registers on MII */
-#define CONFIG_MII_NPE1_FIXEDLINK       1
-#define CONFIG_MII_NPE1_SPEED           100
-#define CONFIG_MII_NPE1_FULLDUPLEX      1
-
-/* Number of ethernet rx buffers & descriptors */
-#define CONFIG_SYS_RX_ETH_BUFFER	16
-#define CONFIG_RESET_PHY_R		1
-/* ethernet switch connected to MII port */
-#define CONFIG_MII_ETHSWITCH		1
-#define CONFIG_HAS_ETH1			1
-
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_NET
-#define CONFIG_CMD_MII
-#define CONFIG_CMD_PING
-#undef  CONFIG_CMD_NFS
-
-/* BOOTP options */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-/* Cache Configuration */
-#define CONFIG_SYS_CACHELINE_SIZE	32
-
-/*
- * environment organization:
- * one flash sector, embedded in uboot area (bottom bootblock flash)
- */
-#define	CONFIG_ENV_IS_IN_FLASH		1
-#define CONFIG_ENV_SIZE			0x2000
-#define CONFIG_ENV_ADDR			(PHYS_FLASH_1 + 0x4000)
-#define CONFIG_SYS_USE_PPCENV		1
-
-#define CONFIG_EXTRA_ENV_SETTINGS					\
-	"npe_ucode=50040000\0"						\
-	"ethprime=NPE1\0"						\
-	"ethrotate=no\0"						\
-	"mtd=IXP4XX-Flash.0:256k(uboot),64k(ucode),1152k(linux),-(root),\0" \
-	"kerneladdr=50050000\0"						\
-	"kernelfile=dvlhost/uImage\0"					\
-	"rootfile=dvlhost/rootfs\0"					\
-	"rootaddr=50170000\0"						\
-	"loadaddr=10000\0"						\
-	"updateboot_ser=mw.b 10000 ff 40000;"				\
-	" loady ${loadaddr};"						\
-	" run eraseboot writeboot\0"					\
-	"updateboot_net=mw.b 10000 ff 40000;"				\
-	" tftp ${loadaddr} dvlhost/u-boot.bin;"				\
-	" run eraseboot writeboot\0"					\
-	"eraseboot=protect off 50000000 50003fff;"			\
-	" protect off 50006000 5003ffff;"				\
-	" erase 50000000 50003fff;"					\
-	" erase 50006000 5003ffff\0"					\
-	"writeboot=cp.b 10000 50000000 4000;"				\
-	" cp.b 16000 50006000 3a000\0"					\
-	"updateucode=loady;"						\
-	" era ${npe_ucode} +${filesize};"				\
-	" cp.b ${loadaddr} ${npe_ucode} ${filesize}\0"			\
-	"updateroot=tftp ${loadaddr} ${rootfile};"			\
-	" era ${rootaddr} +${filesize};"				\
-	" cp.b ${loadaddr} ${rootaddr} ${filesize}\0"			\
-	"updatekern=tftp ${loadaddr} ${kernelfile};"			\
-	" era ${kerneladdr} +${filesize};"				\
-	" cp.b ${loadaddr} ${kerneladdr} ${filesize}\0"			\
-	"flashargs=setenv bootargs mtdparts=${mtd} root=/dev/mtdblock3"	\
-	" rootfstype=squashfs,jffs2 init=/etc/preinit\0"		\
-	"netargs=setenv bootargs mtdparts=${mtd} root=/dev/mtdblock3"	\
-	" rootfstype=squashfs,jffs2 init=/etc/preinit\0"		\
-	"addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0" \
-	"addeth=setenv bootargs ${bootargs} ethaddr=${ethaddr}\0"	\
-	"boot_flash=run flashargs addtty addeth;"			\
-	" bootm ${kerneladdr}\0"					\
-	"boot_net=run netargs addtty addeth;"				\
-	" tftpboot ${loadaddr} ${kernelfile};"				\
-	" bootm\0"
-
-/* additions for new relocation code, must be added to all boards */
-#define CONFIG_SYS_INIT_SP_ADDR						\
-	(CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE)
-
-#endif /* __CONFIG_H */
diff --git a/include/configs/dxr2.h b/include/configs/dxr2.h
index cd553ec55b..75f7812e7d 100644
--- a/include/configs/dxr2.h
+++ b/include/configs/dxr2.h
@@ -21,11 +21,12 @@
 
 #define CONFIG_SYS_MPUCLK	275
 #define DXR2_IOCTRL_VAL	0x18b
-#define DDR_PLL_FREQ	266
-#define CONFIG_SPL_AM33XX_DO_NOT_ENABLE_RTC32K
+#define DDR_PLL_FREQ	303
+#undef CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC
 
 #define BOARD_DFU_BUTTON_GPIO	27
 #define BOARD_DFU_BUTTON_LED	64
+#define GPIO_LAN9303_NRST	88	/* GPIO2_24 = gpio88 */
 
 #undef CONFIG_DOS_PARTITION
 #undef CONFIG_CMD_FAT
@@ -49,7 +50,6 @@
 
 #undef CONFIG_MII
 #undef CONFIG_PHY_GIGE
-#define CONFIG_PHY_ADDR			0
 #define CONFIG_PHY_SMSC
 
 #define CONFIG_FACTORYSET
@@ -62,7 +62,7 @@
 /* Default env settings */
 #define CONFIG_EXTRA_ENV_SETTINGS \
 	"hostname=dxr2\0" \
-	"nand_img_size=0x300000\0" \
+	"nand_img_size=0x400000\0" \
 	"optargs=\0" \
 	CONFIG_COMMON_ENV_SETTINGS
 
@@ -75,10 +75,9 @@
 	"run dfu_start; " \
 	"reset; " \
 "fi;" \
-"if ping ${serverip}; then " \
-	"run net_nfs; " \
-"fi;" \
-"run nand_boot;"
+"run nand_boot;" \
+"reset;"
+
 
 #else
 #define CONFIG_BOOTDELAY		0
diff --git a/include/configs/eXalion.h b/include/configs/eXalion.h
index 0767df1993..940be1f5d0 100644
--- a/include/configs/eXalion.h
+++ b/include/configs/eXalion.h
@@ -19,7 +19,6 @@
  * (easy to change)
  */
 
-#define CONFIG_MPC824X		1
 /* #define CONFIG_MPC8240	   1 */
 #define CONFIG_MPC8245		1
 #define CONFIG_EXALION		1
@@ -71,7 +70,6 @@
  * Miscellaneous configurable options
  */
 #define CONFIG_SYS_LONGHELP		1	/* undef to save memory		*/
-#define CONFIG_SYS_PROMPT		"=> "	/* Monitor Command Prompt	*/
 #define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size	*/
 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)	/* Print Buffer Size	*/
 #define CONFIG_SYS_MAXARGS		8	/* max number of command args	*/
@@ -217,7 +215,6 @@
  * (address mappings, register initial values, etc.)
  * You should know what you are doing if you make changes here.
  */
-#define CONFIG_SYS_HZ			1000
 
 #define CONFIG_SYS_CLK_FREQ	33333333	/* external frequency to pll	*/
 #define CONFIG_PLL_PCI_TO_MEM_MULTIPLIER  2	/* for MPC8240 only		*/
diff --git a/include/configs/ea20.h b/include/configs/ea20.h
index e08423a097..58e40ed888 100644
--- a/include/configs/ea20.h
+++ b/include/configs/ea20.h
@@ -35,7 +35,6 @@
 #define CONFIG_SYS_OSCIN_FREQ		24000000
 #define CONFIG_SYS_TIMERBASE		DAVINCI_TIMER0_BASE
 #define CONFIG_SYS_HZ_CLOCK		clk_get(DAVINCI_AUXCLK_CLKID)
-#define CONFIG_SYS_HZ			1000
 #define CONFIG_SKIP_LOWLEVEL_INIT
 #define CONFIG_SYS_TEXT_BASE		0xc1080000
 #define CONFIG_DA8XX_GPIO
diff --git a/include/configs/eb_cpu5282.h b/include/configs/eb_cpu5282.h
index 08ba883f4c..bdca705874 100644
--- a/include/configs/eb_cpu5282.h
+++ b/include/configs/eb_cpu5282.h
@@ -98,7 +98,6 @@
 /*----------------------------------------------------------------------*
  * Clock and PLL Configuration						*
  *----------------------------------------------------------------------*/
-#define CONFIG_SYS_HZ			1000
 #define	CONFIG_SYS_CLK			80000000      /* 8MHz * 8 */
 
 /* PLL Configuration: Ext Clock * 8 (see table 9-4 of MCF user manual) */
@@ -153,7 +152,7 @@
 #define	CONFIG_SYS_SDRAM_SIZE		CONFIG_SYS_SDRAM_SIZE0
 
 #define CONFIG_SYS_MONITOR_LEN		0x20000
-#define CONFIG_SYS_MALLOC_LEN		(256 << 10)
+#define CONFIG_SYS_MALLOC_LEN		(4 * 1024 * 1024)
 #define CONFIG_SYS_BOOTPARAMS_LEN	64*1024
 
 /*
diff --git a/include/configs/eb_cpux9k2.h b/include/configs/eb_cpux9k2.h
index b8e672f82b..f7e70aa573 100644
--- a/include/configs/eb_cpux9k2.h
+++ b/include/configs/eb_cpux9k2.h
@@ -36,15 +36,11 @@
 #define CONFIG_SYS_TEXT_BASE		0x00000000
 #else
 #define CONFIG_SKIP_LOWLEVEL_INIT
-#define CONFIG_SYS_TEXT_BASE		0x21f00000
+#define CONFIG_SYS_TEXT_BASE		0x21800000
 #endif
 #define CONFIG_SYS_LOAD_ADDR		0x21000000  /* default load address */
 #define CONFIG_STANDALONE_LOAD_ADDR	0x21000000
 
-#define CONFIG_SYS_BOOT_SIZE		0x00 /* 0 KBytes */
-#define CONFIG_SYS_U_BOOT_BASE		PHYS_FLASH_1
-#define CONFIG_SYS_U_BOOT_SIZE		0x60000 /* 384 KBytes */
-
 #define CONFIG_BOOT_RETRY_TIME		30
 #define CONFIG_CMDLINE_EDITING
 
@@ -60,7 +56,6 @@
 
 #define AT91C_MAIN_CLOCK	179404800	/* from 12.288 MHz * 73 / 5 */
 #define AT91C_MASTER_CLOCK	(AT91C_MAIN_CLOCK / 3)
-#define CONFIG_SYS_HZ		1000
 #define CONFIG_SYS_HZ_CLOCK 	(AT91C_MASTER_CLOCK / 2)
 
 #define CONFIG_SYS_AT91_SLOW_CLOCK	32768		/* slow clock */
@@ -133,6 +128,7 @@
 #define CONFIG_CMD_UBI
 #define CONFIG_CMD_MTDPARTS
 #define CONFIG_CMD_UBIFS
+
 #define CONFIG_SYS_LONGHELP
 
 /*
@@ -162,6 +158,7 @@
  * Hardware drivers
  */
 #define CONFIG_USB_ATMEL
+#define CONFIG_USB_ATMEL_CLK_SEL_PLLB
 #define CONFIG_USB_OHCI_NEW
 #define CONFIG_AT91C_PQFP_UHPBUG
 #define CONFIG_USB_STORAGE
diff --git a/include/configs/ebony.h b/include/configs/ebony.h
index 8dc654ea50..3f0ad69738 100644
--- a/include/configs/ebony.h
+++ b/include/configs/ebony.h
@@ -17,7 +17,6 @@
 #define CONFIG_EBONY		1	    /* Board is ebony		*/
 #define CONFIG_440GP		1	    /* Specifc GP support	*/
 #define CONFIG_440		1	    /* ... PPC440 family	*/
-#define CONFIG_4xx		1	    /* ... PPC4xx family	*/
 #define CONFIG_BOARD_EARLY_INIT_F 1	    /* Call board_early_init_f	*/
 #define CONFIG_SYS_CLK_FREQ	33333333    /* external freq to pll	*/
 
diff --git a/include/configs/ecovec.h b/include/configs/ecovec.h
index 2c9594be03..e26591c14f 100644
--- a/include/configs/ecovec.h
+++ b/include/configs/ecovec.h
@@ -23,9 +23,6 @@
  */
 
 #undef DEBUG
-#define CONFIG_SH		1
-#define CONFIG_SH4		1
-#define CONFIG_SH4A		1
 #define CONFIG_CPU_SH7724	1
 #define CONFIG_BOARD_LATE_INIT		1
 #define CONFIG_ECOVEC		1
@@ -58,18 +55,17 @@
 
 /* I2C */
 #define CONFIG_CMD_I2C
-#define CONFIG_SH_I2C 1
-#define CONFIG_HARD_I2C		1
-#define CONFIG_I2C_MULTI_BUS	1
-#define CONFIG_SYS_MAX_I2C_BUS	2
-#define CONFIG_SYS_I2C_MODULE	1
-#define CONFIG_SYS_I2C_SPEED	100000 /* 100 kHz */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_SH
 #define CONFIG_SYS_I2C_SLAVE	0x7F
+#define CONFIG_SYS_I2C_SH_NUM_CONTROLLERS 2
+#define CONFIG_SYS_I2C_SH_BASE0	0xA4470000
+#define CONFIG_SYS_I2C_SH_SPEED0	100000
+#define CONFIG_SYS_I2C_SH_BASE1	0xA4750000
+#define CONFIG_SYS_I2C_SH_SPEED1	100000
 #define CONFIG_SH_I2C_DATA_HIGH	4
 #define CONFIG_SH_I2C_DATA_LOW 	5
 #define CONFIG_SH_I2C_CLOCK  	41666666
-#define CONFIG_SH_I2C_BASE0		0xA4470000
-#define CONFIG_SH_I2C_BASE1		0xA4750000
 
 /* Ether */
 #define CONFIG_SH_ETHER 1
@@ -92,7 +88,6 @@
 /* undef to save memory	*/
 #define CONFIG_SYS_LONGHELP
 /* Monitor Command Prompt */
-#define CONFIG_SYS_PROMPT		"=> "
 /* Buffer size for input from the Console */
 #define CONFIG_SYS_CBSIZE		256
 /* Buffer size for Console output */
@@ -163,8 +158,6 @@
 #define CONFIG_SYS_MONITOR_LEN	(256 * 1024)
 /* Size of DRAM reserved for malloc() use */
 #define CONFIG_SYS_MALLOC_LEN	(256 * 1024)
-/* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_SIZE	(256)
 #define CONFIG_SYS_BOOTMAPSZ	(8 * 1024 * 1024)
 
 /* ENV setting */
@@ -179,7 +172,8 @@
 
 /* Board Clock */
 #define CONFIG_SYS_CLK_FREQ 41666666
+#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
+#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
 #define CONFIG_SYS_TMU_CLK_DIV      4
-#define CONFIG_SYS_HZ       1000
 
 #endif	/* __ECOVEC_H */
diff --git a/include/configs/edminiv2.h b/include/configs/edminiv2.h
index 9c701099ad..8b9f66a29c 100644
--- a/include/configs/edminiv2.h
+++ b/include/configs/edminiv2.h
@@ -34,8 +34,6 @@
  * CLKs configurations
  */
 
-#define CONFIG_SYS_HZ		1000
-
 /*
  * Board-specific values for Orion5x MPP low level init:
  * - MPPs 12 to 15 are SATA LEDs (mode 5)
diff --git a/include/configs/enbw_cmc.h b/include/configs/enbw_cmc.h
index 90033fa10f..03b74a2dab 100644
--- a/include/configs/enbw_cmc.h
+++ b/include/configs/enbw_cmc.h
@@ -33,7 +33,6 @@
 #define CONFIG_SYS_OSCIN_FREQ		24000000
 #define CONFIG_SYS_TIMERBASE		DAVINCI_TIMER0_BASE
 #define CONFIG_SYS_HZ_CLOCK		clk_get(DAVINCI_AUXCLK_CLKID)
-#define CONFIG_SYS_HZ			1000
 #define CONFIG_DA850_LOWLEVEL
 #define CONFIG_ARCH_CPU_INIT
 #define CONFIG_SYS_DA850_PLL_INIT
@@ -228,7 +227,6 @@
  * U-Boot general configuration
  */
 #define CONFIG_BOOTFILE		"uImage" /* Boot file name */
-#define CONFIG_SYS_PROMPT	"=> " /* Command Prompt */
 #define CONFIG_SYS_CBSIZE	1024 /* Console I/O Buffer Size	*/
 #define CONFIG_SYS_PBSIZE	(CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
 #define CONFIG_SYS_MAXARGS	16 /* max number of command args */
diff --git a/include/configs/ep8248.h b/include/configs/ep8248.h
index e95d312f9e..f1af96ddbb 100644
--- a/include/configs/ep8248.h
+++ b/include/configs/ep8248.h
@@ -139,7 +139,6 @@
  */
 #define CONFIG_SYS_HUSH_PARSER
 #define CONFIG_SYS_LONGHELP			/* undef to save memory	    */
-#define CONFIG_SYS_PROMPT		"=> "	/* Monitor Command Prompt   */
 #if defined(CONFIG_CMD_KGDB)
 #define CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size  */
 #else
@@ -154,8 +153,6 @@
 
 #define CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address */
 
-#define CONFIG_SYS_HZ			1000	/* decrementer freq: 1 ms ticks */
-
 #define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
 
 #define CONFIG_SYS_FLASH_BASE		0xFF800000
diff --git a/include/configs/ep8260.h b/include/configs/ep8260.h
index aba3392234..9cd3054a15 100644
--- a/include/configs/ep8260.h
+++ b/include/configs/ep8260.h
@@ -266,7 +266,6 @@
 #define CONFIG_SYS_LONGHELP
 
 /* Monitor Command Prompt       */
-#define CONFIG_SYS_PROMPT              "=> "
 
 /* Define this variable to enable the "hush" shell (from
    Busybox) as command line interpreter, thus enabling
@@ -326,7 +325,6 @@
  *
  *****************************************************************************/
 
-#define CONFIG_MPC8260          1       /* This is an MPC8260 CPU   */
 #define CONFIG_EP8260           11      /* on an Embedded Planet EP8260 Board, Rev. 11 */
 
 #define CONFIG_BOARD_EARLY_INIT_F 1	    /* Call board_early_init_f	*/
@@ -359,8 +357,6 @@
 
 #define CONFIG_SYS_LOAD_ADDR     0x00100000   /* default load address */
 
-#define CONFIG_SYS_HZ            1000         /* decrementer freq: 1 ms ticks */
-
 /*
  * Low Level Configuration Settings
  * (address mappings, register initial values, etc.)
diff --git a/include/configs/ep82xxm.h b/include/configs/ep82xxm.h
index a3b3349598..cf31f0f141 100644
--- a/include/configs/ep82xxm.h
+++ b/include/configs/ep82xxm.h
@@ -9,7 +9,6 @@
 #ifndef __CONFIG_H
 #define __CONFIG_H
 
-#define CONFIG_MPC8260
 #define CPU_ID_STR		"MPC8270"
 
 #define CONFIG_EP82XXM	/* Embedded Planet EP82xxM H 1.0 board */
@@ -165,8 +164,6 @@
 
 #define CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address */
 
-#define CONFIG_SYS_HZ			1000	/* decrementer freq: 1 ms ticks */
-
 #define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
 
 /*-----------------------------------------------------------------------
diff --git a/include/configs/espt.h b/include/configs/espt.h
index e906efbdba..de16be70b2 100644
--- a/include/configs/espt.h
+++ b/include/configs/espt.h
@@ -10,8 +10,6 @@
 #ifndef __ESPT_H
 #define __ESPT_H
 
-#define CONFIG_SH		1
-#define CONFIG_SH4		1
 #define CONFIG_CPU_SH7763	1
 #define CONFIG_ESPT	1
 #define __LITTLE_ENDIAN		1
@@ -43,7 +41,6 @@
 
 #define CONFIG_SYS_TEXT_BASE	0x8FFC0000
 #define CONFIG_SYS_LONGHELP		/* undef to save memory */
-#define CONFIG_SYS_PROMPT		"=> "	/* Monitor Command Prompt */
 #define CONFIG_SYS_CBSIZE		256	/* Buffer size for input from the Console */
 #define CONFIG_SYS_PBSIZE		256	/* Buffer size for Console output */
 #define CONFIG_SYS_MAXARGS		16	/* max args accepted for monitor commands */
@@ -98,8 +95,9 @@
 
 /* Clock */
 #define CONFIG_SYS_CLK_FREQ	66666666
+#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
+#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
 #define CONFIG_SYS_TMU_CLK_DIV      4
-#define CONFIG_SYS_HZ       1000
 
 /* Ether */
 #define CONFIG_SH_ETHER 1
diff --git a/include/configs/ethernut5.h b/include/configs/ethernut5.h
index adf14be365..480d8678c6 100644
--- a/include/configs/ethernut5.h
+++ b/include/configs/ethernut5.h
@@ -31,7 +31,6 @@
 /* ARM asynchronous clock */
 #define CONFIG_SYS_AT91_SLOW_CLOCK	32768	/* slow clock xtal */
 #define CONFIG_SYS_AT91_MAIN_CLOCK	18432000 /* 18.432 MHz crystal */
-#define CONFIG_SYS_HZ			1000
 
 /* 32kB internal SRAM */
 #define CONFIG_SRAM_BASE	0x00300000 /*AT91SAM9XE_SRAM_BASE */
@@ -150,7 +149,7 @@
 #define CONFIG_SYS_NAND_MASK_ALE	(1 << 21)
 /* our CLE is AD22 */
 #define CONFIG_SYS_NAND_MASK_CLE	(1 << 22)
-#define CONFIG_SYS_NAND_ENABLE_PIN	AT91_PIO_PORTC, 14
+#define CONFIG_SYS_NAND_ENABLE_PIN	GPIO_PIN_PC(14)
 #endif
 
 /* JFFS2 */
@@ -178,6 +177,7 @@
 /* USB */
 #ifdef CONFIG_CMD_USB
 #define CONFIG_USB_ATMEL
+#define CONFIG_USB_ATMEL_CLK_SEL_PLLB
 #define CONFIG_USB_OHCI_NEW
 #define CONFIG_SYS_USB_OHCI_CPU_INIT
 #define CONFIG_SYS_USB_OHCI_REGS_BASE	0x00500000
diff --git a/include/configs/exynos4-dt.h b/include/configs/exynos4-dt.h
new file mode 100644
index 0000000000..2040bf7784
--- /dev/null
+++ b/include/configs/exynos4-dt.h
@@ -0,0 +1,138 @@
+/*
+ * Copyright (C) 2014 Samsung Electronics
+ *
+ * Configuration settings for the SAMSUNG EXYNOS5 board.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/* High Level Configuration Options */
+#define CONFIG_SAMSUNG			/* in a SAMSUNG core */
+#define CONFIG_S5P			/* S5P Family */
+#define CONFIG_EXYNOS4			/* which is in a Exynos4 Family */
+
+#include <asm/arch/cpu.h>		/* get chip and board defs */
+
+#define CONFIG_ARCH_CPU_INIT
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DISPLAY_BOARDINFO
+#define CONFIG_BOARD_COMMON
+
+/* Enable fdt support */
+#define CONFIG_OF_CONTROL
+#define CONFIG_OF_SEPARATE
+
+#define CONFIG_SYS_CACHELINE_SIZE	32
+
+/* input clock of PLL: EXYNOS4 boards have 24MHz input clock */
+#define CONFIG_SYS_CLK_FREQ		24000000
+
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_REVISION_TAG
+#define CONFIG_INITRD_TAG
+#define CONFIG_CMDLINE_EDITING
+
+#include <linux/sizes.h>
+
+/* SD/MMC configuration */
+#define CONFIG_GENERIC_MMC
+#define CONFIG_MMC
+#define CONFIG_S5P_SDHCI
+#define CONFIG_SDHCI
+#define CONFIG_MMC_SDMA
+#define CONFIG_MMC_DEFAULT_DEV	0
+
+/* PWM */
+#define CONFIG_PWM
+
+#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_SKIP_LOWLEVEL_INIT
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+
+/* Command definition*/
+#include <config_cmd_default.h>
+
+#undef CONFIG_CMD_FPGA
+#undef CONFIG_CMD_MISC
+#undef CONFIG_CMD_NET
+#undef CONFIG_CMD_NFS
+#undef CONFIG_CMD_XIMG
+#undef CONFIG_CMD_CACHE
+#undef CONFIG_CMD_ONENAND
+#undef CONFIG_CMD_MTDPARTS
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_MMC
+#define CONFIG_CMD_DFU
+#define CONFIG_CMD_GPT
+#define CONFIG_CMD_PMIC
+#define CONFIG_CMD_SETEXPR
+
+#define CONFIG_BOOTDELAY		3
+#define CONFIG_ZERO_BOOTDELAY_CHECK
+
+/* FAT */
+#define CONFIG_CMD_FAT
+#define CONFIG_FAT_WRITE
+
+/* EXT4 */
+#define CONFIG_CMD_EXT4
+#define CONFIG_CMD_EXT4_WRITE
+
+/* USB Composite download gadget - g_dnl */
+#define CONFIG_USBDOWNLOAD_GADGET
+
+/* TIZEN THOR downloader support */
+#define CONFIG_CMD_THOR_DOWNLOAD
+#define CONFIG_THOR_FUNCTION
+
+#define CONFIG_DFU_FUNCTION
+#define CONFIG_DFU_MMC
+#define CONFIG_SYS_DFU_DATA_BUF_SIZE SZ_32M
+#define DFU_DEFAULT_POLL_TIMEOUT 300
+
+/* USB Samsung's IDs */
+#define CONFIG_G_DNL_VENDOR_NUM 0x04E8
+#define CONFIG_G_DNL_PRODUCT_NUM 0x6601
+#define CONFIG_G_DNL_THOR_VENDOR_NUM CONFIG_G_DNL_VENDOR_NUM
+#define CONFIG_G_DNL_THOR_PRODUCT_NUM 0x685D
+#define CONFIG_G_DNL_MANUFACTURER "Samsung"
+
+/* Miscellaneous configurable options */
+#define CONFIG_SYS_LONGHELP		/* undef to save memory */
+#define CONFIG_SYS_HUSH_PARSER		/* use "hush" command parser	*/
+#define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size */
+#define CONFIG_SYS_PBSIZE		384	/* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS		16	/* max number of command args */
+/* Boot Argument Buffer Size */
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE
+
+/* FLASH and environment organization */
+#define CONFIG_SYS_NO_FLASH
+#undef CONFIG_CMD_IMLS
+
+#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 2 sectors */
+
+#define CONFIG_DOS_PARTITION
+#define CONFIG_EFI_PARTITION
+#define CONFIG_CMD_PART
+#define CONFIG_PARTITION_UUIDS
+
+#define CONFIG_USB_GADGET
+#define CONFIG_USB_GADGET_S3C_UDC_OTG
+#define CONFIG_USB_GADGET_DUALSPEED
+#define CONFIG_USB_GADGET_VBUS_DRAW	2
+#define CONFIG_USB_CABLE_CHECK
+
+#define CONFIG_CMD_USB_MASS_STORAGE
+#define CONFIG_USB_GADGET_MASS_STORAGE
+
+/* Enable devicetree support */
+#define CONFIG_OF_LIBFDT
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/exynos5-dt.h b/include/configs/exynos5-dt.h
new file mode 100644
index 0000000000..414db420dc
--- /dev/null
+++ b/include/configs/exynos5-dt.h
@@ -0,0 +1,291 @@
+/*
+ * Copyright (C) 2013 Samsung Electronics
+ *
+ * Configuration settings for the SAMSUNG EXYNOS5 board.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/* High Level Configuration Options */
+#define CONFIG_SAMSUNG			/* in a SAMSUNG core */
+#define CONFIG_S5P			/* S5P Family */
+#define CONFIG_EXYNOS5			/* which is in a Exynos5 Family */
+
+#include <asm/arch/cpu.h>		/* get chip and board defs */
+
+#define CONFIG_SYS_GENERIC_BOARD
+#define CONFIG_ARCH_CPU_INIT
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DISPLAY_BOARDINFO
+#define CONFIG_BOARD_COMMON
+#define CONFIG_ARCH_EARLY_INIT_R
+#define CONFIG_EXYNOS_SPL
+
+/* Enable fdt support for Exynos5250 */
+#define CONFIG_OF_CONTROL
+#define CONFIG_OF_SEPARATE
+
+/* Allow tracing to be enabled */
+#define CONFIG_TRACE
+#define CONFIG_CMD_TRACE
+#define CONFIG_TRACE_BUFFER_SIZE	(16 << 20)
+#define CONFIG_TRACE_EARLY_SIZE		(8 << 20)
+#define CONFIG_TRACE_EARLY
+#define CONFIG_TRACE_EARLY_ADDR		0x50000000
+
+/* Keep L2 Cache Disabled */
+#define CONFIG_SYS_DCACHE_OFF
+#define CONFIG_SYS_CACHELINE_SIZE	64
+
+/* Enable ACE acceleration for SHA1 and SHA256 */
+#define CONFIG_EXYNOS_ACE_SHA
+#define CONFIG_SHA_HW_ACCEL
+
+/* input clock of PLL: SMDK5250 has 24MHz input clock */
+#define CONFIG_SYS_CLK_FREQ		24000000
+
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_INITRD_TAG
+#define CONFIG_CMDLINE_EDITING
+
+/* Power Down Modes */
+#define S5P_CHECK_SLEEP			0x00000BAD
+#define S5P_CHECK_DIDLE			0xBAD00000
+#define S5P_CHECK_LPA			0xABAD0000
+
+/* Offset for inform registers */
+#define INFORM0_OFFSET			0x800
+#define INFORM1_OFFSET			0x804
+#define INFORM2_OFFSET			0x808
+#define INFORM3_OFFSET			0x80c
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + (4 << 20))
+
+/* select serial console configuration */
+#define CONFIG_BAUDRATE			115200
+#define EXYNOS5_DEFAULT_UART_OFFSET	0x010000
+#define CONFIG_SILENT_CONSOLE
+
+/* Enable keyboard */
+#define CONFIG_CROS_EC		/* CROS_EC protocol */
+#define CONFIG_CROS_EC_SPI		/* Support CROS_EC over SPI */
+#define CONFIG_CROS_EC_I2C		/* Support CROS_EC over I2C */
+#define CONFIG_CROS_EC_KEYB	/* CROS_EC keyboard input */
+#define CONFIG_CMD_CROS_EC
+#define CONFIG_KEYBOARD
+
+/* Console configuration */
+#define CONFIG_CONSOLE_MUX
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV
+#define EXYNOS_DEVICE_SETTINGS \
+		"stdin=serial,cros-ec-keyb\0" \
+		"stdout=serial,lcd\0" \
+		"stderr=serial,lcd\0"
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	EXYNOS_DEVICE_SETTINGS
+
+/* SD/MMC configuration */
+#define CONFIG_GENERIC_MMC
+#define CONFIG_MMC
+#define CONFIG_SDHCI
+#define CONFIG_S5P_SDHCI
+#define CONFIG_DWMMC
+#define CONFIG_EXYNOS_DWMMC
+#define CONFIG_SUPPORT_EMMC_BOOT
+#define CONFIG_BOUNCE_BUFFER
+
+#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_SKIP_LOWLEVEL_INIT
+
+/* PWM */
+#define CONFIG_PWM
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+
+/* Command definition*/
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_MMC
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_HASH
+
+#define CONFIG_BOOTDELAY		3
+#define CONFIG_ZERO_BOOTDELAY_CHECK
+
+/* Thermal Management Unit */
+#define CONFIG_EXYNOS_TMU
+#define CONFIG_CMD_DTT
+#define CONFIG_TMU_CMD_DTT
+
+/* TPM */
+#define CONFIG_TPM
+#define CONFIG_CMD_TPM
+#define CONFIG_TPM_TIS_I2C
+#define CONFIG_TPM_TIS_I2C_BUS_NUMBER	3
+#define CONFIG_TPM_TIS_I2C_SLAVE_ADDR	0x20
+
+/* MMC SPL */
+#define CONFIG_SPL
+#define COPY_BL2_FNPTR_ADDR	0x02020030
+
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+#define CONFIG_SPL_GPIO_SUPPORT
+
+/* specific .lds file */
+#define CONFIG_SPL_LDSCRIPT	"board/samsung/common/exynos-uboot-spl.lds"
+#define CONFIG_SPL_MAX_FOOTPRINT	(14 * 1024)
+
+
+/* Miscellaneous configurable options */
+#define CONFIG_SYS_LONGHELP		/* undef to save memory */
+#define CONFIG_SYS_HUSH_PARSER		/* use "hush" command parser	*/
+#define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size */
+#define CONFIG_SYS_PBSIZE		384	/* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS		16	/* max number of command args */
+#define CONFIG_DEFAULT_CONSOLE		"console=ttySAC1,115200n8\0"
+/* Boot Argument Buffer Size */
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE
+/* memtest works on */
+#define CONFIG_SYS_MEMTEST_START	CONFIG_SYS_SDRAM_BASE
+#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_SDRAM_BASE + 0x5E00000)
+#define CONFIG_SYS_LOAD_ADDR		(CONFIG_SYS_SDRAM_BASE + 0x3E00000)
+
+#define CONFIG_RD_LVL
+
+#define CONFIG_NR_DRAM_BANKS	8
+#define SDRAM_BANK_SIZE		(256UL << 20UL)	/* 256 MB */
+#define PHYS_SDRAM_1		CONFIG_SYS_SDRAM_BASE
+#define PHYS_SDRAM_1_SIZE	SDRAM_BANK_SIZE
+#define PHYS_SDRAM_2		(CONFIG_SYS_SDRAM_BASE + SDRAM_BANK_SIZE)
+#define PHYS_SDRAM_2_SIZE	SDRAM_BANK_SIZE
+#define PHYS_SDRAM_3		(CONFIG_SYS_SDRAM_BASE + (2 * SDRAM_BANK_SIZE))
+#define PHYS_SDRAM_3_SIZE	SDRAM_BANK_SIZE
+#define PHYS_SDRAM_4		(CONFIG_SYS_SDRAM_BASE + (3 * SDRAM_BANK_SIZE))
+#define PHYS_SDRAM_4_SIZE	SDRAM_BANK_SIZE
+#define PHYS_SDRAM_5		(CONFIG_SYS_SDRAM_BASE + (4 * SDRAM_BANK_SIZE))
+#define PHYS_SDRAM_5_SIZE	SDRAM_BANK_SIZE
+#define PHYS_SDRAM_6		(CONFIG_SYS_SDRAM_BASE + (5 * SDRAM_BANK_SIZE))
+#define PHYS_SDRAM_6_SIZE	SDRAM_BANK_SIZE
+#define PHYS_SDRAM_7		(CONFIG_SYS_SDRAM_BASE + (6 * SDRAM_BANK_SIZE))
+#define PHYS_SDRAM_7_SIZE	SDRAM_BANK_SIZE
+#define PHYS_SDRAM_8		(CONFIG_SYS_SDRAM_BASE + (7 * SDRAM_BANK_SIZE))
+#define PHYS_SDRAM_8_SIZE	SDRAM_BANK_SIZE
+
+#define CONFIG_SYS_MONITOR_BASE	0x00000000
+
+/* FLASH and environment organization */
+#define CONFIG_SYS_NO_FLASH
+#undef CONFIG_CMD_IMLS
+
+#define CONFIG_SYS_MMC_ENV_DEV		0
+
+#define CONFIG_SECURE_BL1_ONLY
+
+/* Secure FW size configuration */
+#ifdef CONFIG_SECURE_BL1_ONLY
+#define CONFIG_SEC_FW_SIZE (8 << 10) /* 8KB */
+#else
+#define CONFIG_SEC_FW_SIZE 0
+#endif
+
+/* Configuration of BL1, BL2, ENV Blocks on mmc */
+#define CONFIG_RES_BLOCK_SIZE	(512)
+#define CONFIG_BL1_SIZE	(16 << 10) /*16 K reserved for BL1*/
+#define CONFIG_BL2_SIZE	(512UL << 10UL) /* 512 KB */
+#define CONFIG_ENV_SIZE	(16 << 10) /* 16 KB */
+
+#define CONFIG_BL1_OFFSET	(CONFIG_RES_BLOCK_SIZE + CONFIG_SEC_FW_SIZE)
+#define CONFIG_BL2_OFFSET	(CONFIG_BL1_OFFSET + CONFIG_BL1_SIZE)
+#define CONFIG_ENV_OFFSET	(CONFIG_BL2_OFFSET + CONFIG_BL2_SIZE)
+
+/* U-boot copy size from boot Media to DRAM.*/
+#define BL2_START_OFFSET	(CONFIG_BL2_OFFSET/512)
+#define BL2_SIZE_BLOC_COUNT	(CONFIG_BL2_SIZE/512)
+
+#define CONFIG_SPI_BOOTING
+#define EXYNOS_COPY_SPI_FNPTR_ADDR	0x02020058
+#define SPI_FLASH_UBOOT_POS	(CONFIG_SEC_FW_SIZE + CONFIG_BL1_SIZE)
+
+#define CONFIG_DOS_PARTITION
+#define CONFIG_EFI_PARTITION
+#define CONFIG_CMD_PART
+#define CONFIG_PARTITION_UUIDS
+
+/* I2C */
+#define CONFIG_SYS_I2C_INIT_BOARD
+#define CONFIG_SYS_I2C
+#define CONFIG_CMD_I2C
+#define CONFIG_SYS_I2C_S3C24X0_SPEED	100000		/* 100 Kbps */
+#define CONFIG_SYS_I2C_S3C24X0
+#define CONFIG_I2C_MULTI_BUS
+#define CONFIG_SYS_I2C_S3C24X0_SLAVE    0x0
+#define CONFIG_I2C_EDID
+
+/* SPI */
+#define CONFIG_ENV_IS_IN_SPI_FLASH
+#define CONFIG_SPI_FLASH
+#define CONFIG_ENV_SPI_BASE	0x12D30000
+
+#ifdef CONFIG_SPI_FLASH
+#define CONFIG_EXYNOS_SPI
+#define CONFIG_CMD_SF
+#define CONFIG_CMD_SPI
+#define CONFIG_SPI_FLASH_WINBOND
+#define CONFIG_SPI_FLASH_GIGADEVICE
+#define CONFIG_SF_DEFAULT_MODE		SPI_MODE_0
+#define CONFIG_SF_DEFAULT_SPEED		50000000
+#define EXYNOS5_SPI_NUM_CONTROLLERS	5
+#define CONFIG_OF_SPI
+#endif
+
+#ifdef CONFIG_ENV_IS_IN_SPI_FLASH
+#define CONFIG_ENV_SPI_MODE	SPI_MODE_0
+#define CONFIG_ENV_SECT_SIZE	CONFIG_ENV_SIZE
+#define CONFIG_ENV_SPI_BUS	1
+#define CONFIG_ENV_SPI_MAX_HZ	50000000
+#endif
+
+/* PMIC */
+#define CONFIG_POWER
+#define CONFIG_POWER_I2C
+
+/* Ethernet Controllor Driver */
+#ifdef CONFIG_CMD_NET
+#define CONFIG_SMC911X
+#define CONFIG_SMC911X_BASE		0x5000000
+#define CONFIG_SMC911X_16_BIT
+#define CONFIG_ENV_SROM_BANK		1
+#endif /*CONFIG_CMD_NET*/
+
+/* Enable PXE Support */
+#ifdef CONFIG_CMD_NET
+#define CONFIG_CMD_PXE
+#define CONFIG_MENU
+#endif
+
+/* Enable devicetree support */
+#define CONFIG_OF_LIBFDT
+
+/* SHA hashing */
+#define CONFIG_CMD_HASH
+#define CONFIG_HASH_VERIFY
+#define CONFIG_SHA1
+#define CONFIG_SHA256
+
+/* Enable Time Command */
+#define CONFIG_CMD_TIME
+
+#define CONFIG_CMD_BOOTZ
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/exynos5250-dt.h b/include/configs/exynos5250-dt.h
index 8c21909d63..b7ff47236b 100644
--- a/include/configs/exynos5250-dt.h
+++ b/include/configs/exynos5250-dt.h
@@ -1,3 +1,4 @@
+
 /*
  * Copyright (C) 2012 Samsung Electronics
  *
@@ -6,134 +7,24 @@
  * SPDX-License-Identifier:	GPL-2.0+
  */
 
-#ifndef __CONFIG_H
-#define __CONFIG_H
+#ifndef __CONFIG_5250_H
+#define __CONFIG_5250_H
 
-/* High Level Configuration Options */
-#define CONFIG_SAMSUNG			/* in a SAMSUNG core */
-#define CONFIG_S5P			/* S5P Family */
-#define CONFIG_EXYNOS5			/* which is in a Exynos5 Family */
+#include <configs/exynos5-dt.h>
 #define CONFIG_EXYNOS5250
 
-#include <asm/arch/cpu.h>		/* get chip and board defs */
-
-#define CONFIG_SYS_GENERIC_BOARD
-#define CONFIG_ARCH_CPU_INIT
-#define CONFIG_DISPLAY_CPUINFO
-#define CONFIG_DISPLAY_BOARDINFO
-
-/* Enable fdt support for Exynos5250 */
-#define CONFIG_OF_CONTROL
-#define CONFIG_OF_SEPARATE
-
-/* Allow tracing to be enabled */
-#define CONFIG_TRACE
-#define CONFIG_CMD_TRACE
-#define CONFIG_TRACE_BUFFER_SIZE	(16 << 20)
-#define CONFIG_TRACE_EARLY_SIZE		(8 << 20)
-#define CONFIG_TRACE_EARLY
-#define CONFIG_TRACE_EARLY_ADDR		0x50000000
-
-/* Keep L2 Cache Disabled */
-#define CONFIG_SYS_DCACHE_OFF
-
-/* Enable ACE acceleration for SHA1 and SHA256 */
-#define CONFIG_EXYNOS_ACE_SHA
-#define CONFIG_SHA_HW_ACCEL
-
 #define CONFIG_SYS_SDRAM_BASE		0x40000000
 #define CONFIG_SYS_TEXT_BASE		0x43E00000
 
-/* input clock of PLL: SMDK5250 has 24MHz input clock */
-#define CONFIG_SYS_CLK_FREQ		24000000
-
-#define CONFIG_SETUP_MEMORY_TAGS
-#define CONFIG_CMDLINE_TAG
-#define CONFIG_INITRD_TAG
-#define CONFIG_CMDLINE_EDITING
-
 /* MACH_TYPE_SMDK5250 macro will be removed once added to mach-types */
 #define MACH_TYPE_SMDK5250		3774
 #define CONFIG_MACH_TYPE		MACH_TYPE_SMDK5250
 
-/* Power Down Modes */
-#define S5P_CHECK_SLEEP			0x00000BAD
-#define S5P_CHECK_DIDLE			0xBAD00000
-#define S5P_CHECK_LPA			0xABAD0000
-
-/* Offset for inform registers */
-#define INFORM0_OFFSET			0x800
-#define INFORM1_OFFSET			0x804
-
-/* Size of malloc() pool */
-#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + (4 << 20))
-
-/* select serial console configuration */
-#define CONFIG_BAUDRATE			115200
-#define EXYNOS5_DEFAULT_UART_OFFSET	0x010000
-#define CONFIG_SILENT_CONSOLE
-
-/* Enable keyboard */
-#define CONFIG_CROS_EC		/* CROS_EC protocol */
-#define CONFIG_CROS_EC_SPI		/* Support CROS_EC over SPI */
-#define CONFIG_CROS_EC_I2C		/* Support CROS_EC over I2C */
-#define CONFIG_CROS_EC_KEYB	/* CROS_EC keyboard input */
-#define CONFIG_CMD_CROS_EC
-#define CONFIG_KEYBOARD
-
-/* Console configuration */
-#define CONFIG_CONSOLE_MUX
-#define CONFIG_SYS_CONSOLE_IS_IN_ENV
-#define EXYNOS_DEVICE_SETTINGS \
-		"stdin=serial,cros-ec-keyb\0" \
-		"stdout=serial,lcd\0" \
-		"stderr=serial,lcd\0"
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
-	EXYNOS_DEVICE_SETTINGS
-
-/* SD/MMC configuration */
-#define CONFIG_GENERIC_MMC
-#define CONFIG_MMC
-#define CONFIG_SDHCI
-#define CONFIG_S5P_SDHCI
-#define CONFIG_DWMMC
-#define CONFIG_EXYNOS_DWMMC
-#define CONFIG_SUPPORT_EMMC_BOOT
-
-
-#define CONFIG_BOARD_EARLY_INIT_F
-#define CONFIG_SKIP_LOWLEVEL_INIT
-
-/* PWM */
-#define CONFIG_PWM
-
-/* allow to overwrite serial and ethaddr */
-#define CONFIG_ENV_OVERWRITE
-
-/* Command definition*/
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_ELF
-#define CONFIG_CMD_MMC
-#define CONFIG_CMD_EXT2
-#define CONFIG_CMD_FAT
-#define CONFIG_CMD_NET
-#define CONFIG_CMD_HASH
-
-#define CONFIG_BOOTDELAY		3
-#define CONFIG_ZERO_BOOTDELAY_CHECK
-
-/* Thermal Management Unit */
-#define CONFIG_EXYNOS_TMU
-#define CONFIG_CMD_DTT
-#define CONFIG_TMU_CMD_DTT
-
 /* USB */
 #define CONFIG_CMD_USB
-#define CONFIG_USB_EHCI
-#define CONFIG_USB_EHCI_EXYNOS
+#define CONFIG_USB_XHCI
+#define CONFIG_USB_XHCI_EXYNOS
+#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS	2
 #define CONFIG_USB_STORAGE
 
 /* USB boot mode */
@@ -142,205 +33,32 @@
 #define EXYNOS_USB_SECONDARY_BOOT	0xfeed0002
 #define EXYNOS_IRAM_SECONDARY_BASE	0x02020018
 
-/* TPM */
-#define CONFIG_TPM
-#define CONFIG_CMD_TPM
-#define CONFIG_TPM_TIS_I2C
-#define CONFIG_TPM_TIS_I2C_BUS_NUMBER	3
-#define CONFIG_TPM_TIS_I2C_SLAVE_ADDR	0x20
-
-/* MMC SPL */
-#define CONFIG_SPL
-#define COPY_BL2_FNPTR_ADDR	0x02020030
-
-#define CONFIG_SPL_LIBCOMMON_SUPPORT
-
-/* specific .lds file */
-#define CONFIG_SPL_LDSCRIPT	"board/samsung/common/exynos-uboot-spl.lds"
 #define CONFIG_SPL_TEXT_BASE	0x02023400
-#define CONFIG_SPL_MAX_FOOTPRINT	(14 * 1024)
 
 #define CONFIG_BOOTCOMMAND	"mmc read 40007000 451 2000; bootm 40007000"
 
-/* Miscellaneous configurable options */
-#define CONFIG_SYS_LONGHELP		/* undef to save memory */
-#define CONFIG_SYS_HUSH_PARSER		/* use "hush" command parser	*/
 #define CONFIG_SYS_PROMPT		"SMDK5250 # "
-#define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size */
-#define CONFIG_SYS_PBSIZE		384	/* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS		16	/* max number of command args */
-#define CONFIG_DEFAULT_CONSOLE		"console=ttySAC1,115200n8\0"
-/* Boot Argument Buffer Size */
-#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE
-/* memtest works on */
-#define CONFIG_SYS_MEMTEST_START	CONFIG_SYS_SDRAM_BASE
-#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_SDRAM_BASE + 0x5E00000)
-#define CONFIG_SYS_LOAD_ADDR		(CONFIG_SYS_SDRAM_BASE + 0x3E00000)
-
-#define CONFIG_SYS_HZ			1000
-
-#define CONFIG_RD_LVL
-
-#define CONFIG_NR_DRAM_BANKS	8
-#define SDRAM_BANK_SIZE		(256UL << 20UL)	/* 256 MB */
-#define PHYS_SDRAM_1		CONFIG_SYS_SDRAM_BASE
-#define PHYS_SDRAM_1_SIZE	SDRAM_BANK_SIZE
-#define PHYS_SDRAM_2		(CONFIG_SYS_SDRAM_BASE + SDRAM_BANK_SIZE)
-#define PHYS_SDRAM_2_SIZE	SDRAM_BANK_SIZE
-#define PHYS_SDRAM_3		(CONFIG_SYS_SDRAM_BASE + (2 * SDRAM_BANK_SIZE))
-#define PHYS_SDRAM_3_SIZE	SDRAM_BANK_SIZE
-#define PHYS_SDRAM_4		(CONFIG_SYS_SDRAM_BASE + (3 * SDRAM_BANK_SIZE))
-#define PHYS_SDRAM_4_SIZE	SDRAM_BANK_SIZE
-#define PHYS_SDRAM_5		(CONFIG_SYS_SDRAM_BASE + (4 * SDRAM_BANK_SIZE))
-#define PHYS_SDRAM_5_SIZE	SDRAM_BANK_SIZE
-#define PHYS_SDRAM_6		(CONFIG_SYS_SDRAM_BASE + (5 * SDRAM_BANK_SIZE))
-#define PHYS_SDRAM_6_SIZE	SDRAM_BANK_SIZE
-#define PHYS_SDRAM_7		(CONFIG_SYS_SDRAM_BASE + (6 * SDRAM_BANK_SIZE))
-#define PHYS_SDRAM_7_SIZE	SDRAM_BANK_SIZE
-#define PHYS_SDRAM_8		(CONFIG_SYS_SDRAM_BASE + (7 * SDRAM_BANK_SIZE))
-#define PHYS_SDRAM_8_SIZE	SDRAM_BANK_SIZE
-
-#define CONFIG_SYS_MONITOR_BASE	0x00000000
-
-/* FLASH and environment organization */
-#define CONFIG_SYS_NO_FLASH
-#undef CONFIG_CMD_IMLS
 #define CONFIG_IDENT_STRING		" for SMDK5250"
 
-#define CONFIG_SYS_MMC_ENV_DEV		0
-
-#define CONFIG_SECURE_BL1_ONLY
-
-/* Secure FW size configuration */
-#ifdef	CONFIG_SECURE_BL1_ONLY
-#define	CONFIG_SEC_FW_SIZE		(8 << 10)	/* 8KB */
-#else
-#define	CONFIG_SEC_FW_SIZE		0
-#endif
-
-/* Configuration of BL1, BL2, ENV Blocks on mmc */
-#define CONFIG_RES_BLOCK_SIZE	(512)
-#define CONFIG_BL1_SIZE		(16 << 10) /*16 K reserved for BL1*/
-#define	CONFIG_BL2_SIZE		(512UL << 10UL)	/* 512 KB */
-#define CONFIG_ENV_SIZE		(16 << 10)	/* 16 KB */
-
-#define CONFIG_BL1_OFFSET	(CONFIG_RES_BLOCK_SIZE + CONFIG_SEC_FW_SIZE)
-#define CONFIG_BL2_OFFSET	(CONFIG_BL1_OFFSET + CONFIG_BL1_SIZE)
-#define CONFIG_ENV_OFFSET	(CONFIG_BL2_OFFSET + CONFIG_BL2_SIZE)
-
-/* U-boot copy size from boot Media to DRAM.*/
-#define BL2_START_OFFSET	(CONFIG_BL2_OFFSET/512)
-#define BL2_SIZE_BLOC_COUNT	(CONFIG_BL2_SIZE/512)
-
-#define CONFIG_SPI_BOOTING
-#define EXYNOS_COPY_SPI_FNPTR_ADDR	0x02020058
-#define SPI_FLASH_UBOOT_POS		(CONFIG_SEC_FW_SIZE + CONFIG_BL1_SIZE)
-
-#define CONFIG_DOS_PARTITION
-#define CONFIG_EFI_PARTITION
-#define CONFIG_CMD_PART
-#define CONFIG_PARTITION_UUIDS
-
-
 #define CONFIG_IRAM_STACK	0x02050000
 
 #define CONFIG_SYS_INIT_SP_ADDR	CONFIG_IRAM_STACK
 
-/* I2C */
-#define CONFIG_SYS_I2C_INIT_BOARD
-#define CONFIG_HARD_I2C
-#define CONFIG_CMD_I2C
-#define CONFIG_SYS_I2C_SPEED	100000		/* 100 Kbps */
-#define CONFIG_DRIVER_S3C24X0_I2C
-#define CONFIG_I2C_MULTI_BUS
-#define CONFIG_MAX_I2C_NUM	8
-#define CONFIG_SYS_I2C_SLAVE    0x0
-#define CONFIG_I2C_EDID
-
 /* PMIC */
-#define CONFIG_PMIC
-#define CONFIG_PMIC_I2C
 #define CONFIG_PMIC_MAX77686
 
-/* SPI */
-#define CONFIG_ENV_IS_IN_SPI_FLASH
-#define CONFIG_SPI_FLASH
-
-#ifdef CONFIG_SPI_FLASH
-#define CONFIG_EXYNOS_SPI
-#define CONFIG_CMD_SF
-#define CONFIG_CMD_SPI
-#define CONFIG_SPI_FLASH_WINBOND
-#define CONFIG_SPI_FLASH_GIGADEVICE
-#define CONFIG_SF_DEFAULT_MODE		SPI_MODE_0
-#define CONFIG_SF_DEFAULT_SPEED		50000000
-#define EXYNOS5_SPI_NUM_CONTROLLERS	5
-#endif
-
-#ifdef CONFIG_ENV_IS_IN_SPI_FLASH
-#define CONFIG_ENV_SPI_MODE	SPI_MODE_0
-#define CONFIG_ENV_SECT_SIZE	CONFIG_ENV_SIZE
-#define CONFIG_ENV_SPI_BUS	1
-#define CONFIG_ENV_SPI_MAX_HZ	50000000
-#endif
-
-/* PMIC */
-#define CONFIG_POWER
-#define CONFIG_POWER_I2C
-#define CONFIG_POWER_MAX77686
-
-/* SPI */
-#define CONFIG_ENV_IS_IN_SPI_FLASH
-#define CONFIG_SPI_FLASH
-
-#ifdef CONFIG_SPI_FLASH
-#define CONFIG_EXYNOS_SPI
-#define CONFIG_CMD_SF
-#define CONFIG_CMD_SPI
-#define CONFIG_SPI_FLASH_WINBOND
-#define CONFIG_SF_DEFAULT_MODE		SPI_MODE_0
-#define CONFIG_SF_DEFAULT_SPEED		50000000
-#define EXYNOS5_SPI_NUM_CONTROLLERS	5
-#endif
-
-#ifdef CONFIG_ENV_IS_IN_SPI_FLASH
-#define CONFIG_ENV_SPI_MODE	SPI_MODE_0
-#define CONFIG_ENV_SECT_SIZE	CONFIG_ENV_SIZE
-#define CONFIG_ENV_SPI_BUS	1
-#define CONFIG_ENV_SPI_MAX_HZ	50000000
-#endif
-
-/* Ethernet Controllor Driver */
-#ifdef CONFIG_CMD_NET
-#define CONFIG_SMC911X
-#define CONFIG_SMC911X_BASE		0x5000000
-#define CONFIG_SMC911X_16_BIT
-#define CONFIG_ENV_SROM_BANK		1
-#endif /*CONFIG_CMD_NET*/
-
-/* Enable PXE Support */
-#ifdef CONFIG_CMD_NET
-#define CONFIG_CMD_PXE
-#define CONFIG_MENU
-#endif
-
 /* Sound */
 #define CONFIG_CMD_SOUND
 #ifdef CONFIG_CMD_SOUND
 #define CONFIG_SOUND
+#define CONFIG_I2S_SAMSUNG
 #define CONFIG_I2S
 #define CONFIG_SOUND_MAX98095
 #define CONFIG_SOUND_WM8994
 #endif
 
-/* Enable devicetree support */
-#define CONFIG_OF_LIBFDT
-
-/* SHA hashing */
-#define CONFIG_CMD_HASH
-#define CONFIG_HASH_VERIFY
-#define CONFIG_SHA1
-#define CONFIG_SHA256
+/* I2C */
+#define CONFIG_MAX_I2C_NUM	8
 
 /* Display */
 #define CONFIG_LCD
@@ -351,8 +69,4 @@
 #define LCD_YRES			1600
 #define LCD_BPP			LCD_COLOR16
 #endif
-
-/* Enable Time Command */
-#define CONFIG_CMD_TIME
-
-#endif	/* __CONFIG_H */
+#endif  /* __CONFIG_5250_H */
diff --git a/include/configs/favr-32-ezkit.h b/include/configs/favr-32-ezkit.h
index 14f0784817..338d3dc782 100644
--- a/include/configs/favr-32-ezkit.h
+++ b/include/configs/favr-32-ezkit.h
@@ -10,7 +10,6 @@
 
 #include <asm/arch/hardware.h>
 
-#define CONFIG_AVR32
 #define CONFIG_AT32AP
 #define CONFIG_AT32AP7000
 #define CONFIG_FAVR32_EZKIT
@@ -18,12 +17,6 @@
 #define CONFIG_FAVR32_EZKIT_EXT_FLASH
 
 /*
- * Timer clock frequency. We're using the CPU-internal COUNT register
- * for this, so this is equivalent to the CPU core clock frequency
- */
-#define CONFIG_SYS_HZ				1000
-
-/*
  * Set up the PLL to run at 140 MHz, the CPU to run at the PLL
  * frequency, the HSB and PBB at 1/2, and the PBA to run at 1/4 the
  * PLL frequency.
diff --git a/include/configs/flea3.h b/include/configs/flea3.h
index 655df67961..84175676c2 100644
--- a/include/configs/flea3.h
+++ b/include/configs/flea3.h
@@ -50,11 +50,10 @@
 /*
  * Hardware drivers
  */
-#define CONFIG_HARD_I2C
-#define CONFIG_I2C_MXC
-#define CONFIG_SYS_I2C_BASE		I2C3_BASE_ADDR
-#define CONFIG_SYS_I2C_SPEED		100000
-#define CONFIG_SYS_I2C_SLAVE		0xfe
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_SPD_BUS_NUM		2 /* I2C3 */
+#define CONFIG_SYS_MXC_I2C3_SLAVE	0xfe
 #define CONFIG_MXC_SPI
 #define CONFIG_MXC_GPIO
 
@@ -130,8 +129,6 @@
 
 #define CONFIG_SYS_LOAD_ADDR		CONFIG_LOADADDR
 
-#define CONFIG_SYS_HZ				1000
-
 /*
  * Physical Memory Map
  */
diff --git a/include/configs/galaxy5200.h b/include/configs/galaxy5200.h
index 011a3b315c..b555d82ddc 100644
--- a/include/configs/galaxy5200.h
+++ b/include/configs/galaxy5200.h
@@ -23,8 +23,7 @@
  * High Level Configuration Options
  * (easy to change)
  */
-#define CONFIG_MPC5xxx		1	/* This is an MPC5xxx CPU */
-#define CONFIG_MPC5200		1	/* (more precisely an MPC5200 CPU) */
+#define CONFIG_MPC5200		1	/* This is an MPC5200 CPU */
 #define CONFIG_SYS_MPC5XXX_CLKIN 33333333	/* ... running at 33.333333MHz */
 
 /*
@@ -352,7 +351,6 @@
 #define CONFIG_SYS_MEMTEST_END 0x00f00000	/* 1 ... 15 MB in DRAM */
 
 #define CONFIG_SYS_LOAD_ADDR 0x400000		/* default load address */
-#define CONFIG_SYS_HZ 1000			/* decrementer freq: 1 ms ticks */
 
 #define CONFIG_DISPLAY_BOARDINFO 1
 
diff --git a/include/configs/gdppc440etx.h b/include/configs/gdppc440etx.h
index a6f1afff97..6810b3befc 100644
--- a/include/configs/gdppc440etx.h
+++ b/include/configs/gdppc440etx.h
@@ -21,7 +21,6 @@
 #define CONFIG_440GR		1		/* Specific PPC440GR support */
 #define CONFIG_HOSTNAME		gdppc440etx
 #define CONFIG_440		1		/* ... PPC440 family         */
-#define CONFIG_4xx		1		/* ... PPC4xx family         */
 #define CONFIG_SYS_CLK_FREQ	66666666	/* external freq to pll      */
 
 #define	CONFIG_SYS_TEXT_BASE	0xFFF80000
diff --git a/include/configs/gr_cpci_ax2000.h b/include/configs/gr_cpci_ax2000.h
index 86de48e496..2437b4b613 100644
--- a/include/configs/gr_cpci_ax2000.h
+++ b/include/configs/gr_cpci_ax2000.h
@@ -289,7 +289,6 @@
  * Miscellaneous configurable options
  */
 #define CONFIG_SYS_LONGHELP		/* undef to save memory     */
-#define CONFIG_SYS_PROMPT		"=> "	/* Monitor Command Prompt   */
 #if defined(CONFIG_CMD_KGDB)
 #define CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size  */
 #else
@@ -304,8 +303,6 @@
 
 #define CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address */
 
-#define CONFIG_SYS_HZ			1000	/* decrementer freq: 1 ms ticks */
-
 /*
  * Various low-level settings
  */
diff --git a/include/configs/gr_ep2s60.h b/include/configs/gr_ep2s60.h
index cb651b0b0c..2cd6eaedcc 100644
--- a/include/configs/gr_ep2s60.h
+++ b/include/configs/gr_ep2s60.h
@@ -278,7 +278,6 @@
  * Miscellaneous configurable options
  */
 #define CONFIG_SYS_LONGHELP		/* undef to save memory     */
-#define CONFIG_SYS_PROMPT		"=> "	/* Monitor Command Prompt   */
 #if defined(CONFIG_CMD_KGDB)
 #define CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size  */
 #else
@@ -293,8 +292,6 @@
 
 #define CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address */
 
-#define CONFIG_SYS_HZ			1000	/* decrementer freq: 1 ms ticks */
-
 /*-----------------------------------------------------------------------
  * USB stuff
  *-----------------------------------------------------------------------
diff --git a/include/configs/gr_xc3s_1500.h b/include/configs/gr_xc3s_1500.h
index 50cf3f6f52..39036cdf7e 100644
--- a/include/configs/gr_xc3s_1500.h
+++ b/include/configs/gr_xc3s_1500.h
@@ -237,7 +237,6 @@
  * Miscellaneous configurable options
  */
 #define CONFIG_SYS_LONGHELP		/* undef to save memory     */
-#define CONFIG_SYS_PROMPT		"=> "	/* Monitor Command Prompt   */
 #if defined(CONFIG_CMD_KGDB)
 #define CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size  */
 #else
@@ -252,8 +251,6 @@
 
 #define CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address */
 
-#define CONFIG_SYS_HZ			1000	/* decrementer freq: 1 ms ticks */
-
 /*
  * Various low-level settings
  */
diff --git a/include/configs/grasshopper.h b/include/configs/grasshopper.h
index c288b39f2d..73534addfc 100644
--- a/include/configs/grasshopper.h
+++ b/include/configs/grasshopper.h
@@ -11,17 +11,10 @@
 
 #include <asm/arch/hardware.h>
 
-#define CONFIG_AVR32
 #define CONFIG_AT32AP
 #define CONFIG_AT32AP7000
 
 /*
- * Timer clock frequency. We're using the CPU-internal COUNT register
- * for this, so this is equivalent to the CPU core clock frequency
- */
-#define CONFIG_SYS_HZ			1000
-
-/*
  * Set up the PLL to run at 140 MHz, the CPU to run at the PLL
  * frequency, the HSB and PBB at 1/2, and the PBA to run at 1/4 the
  * PLL frequency.
diff --git a/include/configs/grsim.h b/include/configs/grsim.h
index 69ac0c10bf..2d977ceeb6 100644
--- a/include/configs/grsim.h
+++ b/include/configs/grsim.h
@@ -264,7 +264,6 @@
  * Miscellaneous configurable options
  */
 #define CONFIG_SYS_LONGHELP		/* undef to save memory     */
-#define CONFIG_SYS_PROMPT		"=> "	/* Monitor Command Prompt   */
 #if defined(CONFIG_CMD_KGDB)
 #define CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size  */
 #else
@@ -279,8 +278,6 @@
 
 #define CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address */
 
-#define CONFIG_SYS_HZ			1000	/* decrementer freq: 1 ms ticks */
-
 /***** Gaisler GRLIB IP-Cores Config ********/
 
 /* AMBA Plug & Play info display on startup */
diff --git a/include/configs/grsim_leon2.h b/include/configs/grsim_leon2.h
index 531c4bc4be..36ebaf7ff7 100644
--- a/include/configs/grsim_leon2.h
+++ b/include/configs/grsim_leon2.h
@@ -262,7 +262,6 @@
  * Miscellaneous configurable options
  */
 #define CONFIG_SYS_LONGHELP		/* undef to save memory     */
-#define CONFIG_SYS_PROMPT		"=> "	/* Monitor Command Prompt   */
 #if defined(CONFIG_CMD_KGDB)
 #define CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size  */
 #else
@@ -277,8 +276,6 @@
 
 #define CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address */
 
-#define CONFIG_SYS_HZ			1000	/* decrementer freq: 1 ms ticks */
-
 /***** Gaisler GRLIB IP-Cores Config ********/
 
 #define CONFIG_SYS_GRLIB_SDRAM    0
diff --git a/include/configs/gw8260.h b/include/configs/gw8260.h
index 545fa85377..262c9e9e9a 100644
--- a/include/configs/gw8260.h
+++ b/include/configs/gw8260.h
@@ -291,7 +291,6 @@
 #define CONFIG_SYS_LONGHELP
 
 /* Monitor Command Prompt */
-#define CONFIG_SYS_PROMPT      "=> "
 
 
 /*
@@ -326,7 +325,6 @@
  *
  *****************************************************************************/
 
-#define CONFIG_MPC8260      1   /* This is an MPC8260 CPU   */
 #define CONFIG_GW8260       1   /* on an GW8260 Board  */
 #define CONFIG_CPM2		1	/* Has a CPM2 */
 
@@ -352,7 +350,6 @@
 #define CONFIG_CLOCKS_IN_MHZ
 
 #define CONFIG_SYS_LOAD_ADDR   0x100000 /* default load address */
-#define CONFIG_SYS_HZ          1000     /* decrementer freq: 1 ms ticks */
 
 
 /* memtest works from the end of the exception vector table
diff --git a/include/configs/gw_ventana.h b/include/configs/gw_ventana.h
new file mode 100644
index 0000000000..33983907f2
--- /dev/null
+++ b/include/configs/gw_ventana.h
@@ -0,0 +1,425 @@
+/*
+ * Copyright (C) 2013 Gateworks Corporation
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include "mx6_common.h"
+#define CONFIG_MX6
+#define CONFIG_DISPLAY_CPUINFO         /* display cpu info */
+#define CONFIG_DISPLAY_BOARDINFO_LATE  /* display board info (after reloc) */
+
+#define CONFIG_MACH_TYPE	4520   /* Gateworks Ventana Platform */
+
+#include <asm/arch/imx-regs.h>
+#include <asm/imx-common/gpio.h>
+
+/* ATAGs */
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+#define CONFIG_SERIAL_TAG
+#define CONFIG_REVISION_TAG
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN		(10 * 1024 * 1024)
+
+/* Init Functions */
+#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_MISC_INIT_R
+
+/* GPIO */
+#define CONFIG_MXC_GPIO
+
+/* Serial */
+#define CONFIG_MXC_UART
+#define CONFIG_MXC_UART_BASE	       UART2_BASE
+
+#ifdef CONFIG_SPI_FLASH
+
+/* SPI */
+#define CONFIG_CMD_SF
+#ifdef CONFIG_CMD_SF
+  #define CONFIG_MXC_SPI
+  #define CONFIG_SPI_FLASH_MTD
+  #define CONFIG_SPI_FLASH_BAR
+  #define CONFIG_SPI_FLASH_WINBOND
+  #define CONFIG_SF_DEFAULT_BUS              0
+  #define CONFIG_SF_DEFAULT_CS               (0|(IMX_GPIO_NR(3, 19)<<8))
+					     /* GPIO 3-19 (21248) */
+  #define CONFIG_SF_DEFAULT_SPEED            30000000
+  #define CONFIG_SF_DEFAULT_MODE             (SPI_MODE_0)
+#endif
+
+#else
+/* Enable NAND support */
+#define CONFIG_CMD_TIME
+#define CONFIG_CMD_NAND
+#define CONFIG_CMD_NAND_TRIMFFS
+#ifdef CONFIG_CMD_NAND
+  #define CONFIG_NAND_MXS
+  #define CONFIG_SYS_MAX_NAND_DEVICE	1
+  #define CONFIG_SYS_NAND_BASE		0x40000000
+  #define CONFIG_SYS_NAND_5_ADDR_CYCLE
+  #define CONFIG_SYS_NAND_ONFI_DETECTION
+
+  /* DMA stuff, needed for GPMI/MXS NAND support */
+  #define CONFIG_APBH_DMA
+  #define CONFIG_APBH_DMA_BURST
+  #define CONFIG_APBH_DMA_BURST8
+#endif
+
+#endif /* CONFIG_SPI_FLASH */
+
+/* Flattened Image Tree Suport */
+#define CONFIG_FIT
+#define CONFIG_FIT_VERBOSE
+
+/* I2C Configs */
+#define CONFIG_CMD_I2C
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_I2C_SPEED		  100000
+
+/* MMC Configs */
+#define CONFIG_FSL_ESDHC
+#define CONFIG_FSL_USDHC
+#define CONFIG_SYS_FSL_ESDHC_ADDR      0
+#define CONFIG_SYS_FSL_USDHC_NUM       1
+#define CONFIG_MMC
+#define CONFIG_CMD_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_BOUNCE_BUFFER
+
+/* Filesystem support */
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_UBIFS
+#define CONFIG_DOS_PARTITION
+
+/* Network config - Allow larger/faster download for TFTP/NFS */
+#define CONFIG_IP_DEFRAG
+#define CONFIG_TFTP_BLOCKSIZE 4096
+#define CONFIG_NFS_READ_SIZE  4096
+
+/*
+ * SATA Configs
+ */
+#define CONFIG_CMD_SATA
+#ifdef CONFIG_CMD_SATA
+  #define CONFIG_DWC_AHSATA
+  #define CONFIG_SYS_SATA_MAX_DEVICE	1
+  #define CONFIG_DWC_AHSATA_PORT_ID	0
+  #define CONFIG_DWC_AHSATA_BASE_ADDR	SATA_ARB_BASE_ADDR
+  #define CONFIG_LBA48
+  #define CONFIG_LIBATA
+#endif
+
+/*
+ * PCI express
+ */
+#define CONFIG_CMD_PCI
+#ifdef CONFIG_CMD_PCI
+#define CONFIG_PCI
+#define CONFIG_PCI_PNP
+#define CONFIG_PCI_SCAN_SHOW
+#define CONFIG_PCIE_IMX
+#endif
+
+/*
+ * PMIC
+ */
+#define CONFIG_POWER
+#define CONFIG_POWER_I2C
+#define CONFIG_POWER_PFUZE100
+#define CONFIG_POWER_PFUZE100_I2C_ADDR	0x08
+
+/* Various command support */
+#include <config_cmd_default.h>
+#undef CONFIG_CMD_IMLS
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_BMODE         /* set eFUSE shadow for a boot dev and reset */
+#define CONFIG_CMD_HDMIDETECT    /* detect HDMI output device */
+#define CONFIG_CMD_SETEXPR
+#define CONFIG_CMD_BOOTZ
+#define CONFIG_CMD_GSC
+#define CONFIG_CMD_UBI
+#define CONFIG_RBTREE
+#define CONFIG_LZO
+#define CONFIG_CMD_FUSE          /* eFUSE read/write support */
+#ifdef CONFIG_CMD_FUSE
+#define CONFIG_MXC_OCOTP
+#endif
+
+
+/* Ethernet support */
+#define CONFIG_FEC_MXC
+#define CONFIG_MII
+#define IMX_FEC_BASE             ENET_BASE_ADDR
+#define CONFIG_FEC_XCV_TYPE      RGMII
+#define CONFIG_ETHPRIME          "FEC"
+#define CONFIG_FEC_MXC_PHYADDR   0
+#define CONFIG_PHYLIB
+#define CONFIG_ARP_TIMEOUT       200UL
+
+/* USB Configs */
+#define CONFIG_CMD_USB
+#define CONFIG_USB_EHCI
+#define CONFIG_USB_EHCI_MX6
+#define CONFIG_USB_STORAGE
+#define CONFIG_USB_HOST_ETHER
+#define CONFIG_USB_ETHER_ASIX
+#define CONFIG_USB_ETHER_SMSC95XX
+#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
+#define CONFIG_EHCI_HCD_INIT_AFTER_RESET  /* For OTG port */
+#define CONFIG_MXC_USB_PORTSC     (PORT_PTS_UTMI | PORT_PTS_PTW)
+#define CONFIG_MXC_USB_FLAGS      0
+#define CONFIG_USB_KEYBOARD
+#define CONFIG_CI_UDC
+#define CONFIG_USBD_HS
+#define CONFIG_USB_GADGET_DUALSPEED
+#define CONFIG_USB_ETHER
+#define CONFIG_USB_ETH_CDC
+#define CONFIG_NETCONSOLE
+#define CONFIG_SYS_USB_EVENT_POLL_VIA_CONTROL_EP
+#define CONFIG_USB_HUB_MIN_POWER_ON_DELAY 1200
+
+/* serial console (ttymxc1,115200) */
+#define CONFIG_CONS_INDEX              1
+#define CONFIG_BAUDRATE                115200
+
+/* Miscellaneous configurable options */
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT	             "Ventana > "
+#define CONFIG_SYS_CBSIZE	             1024
+#define CONFIG_AUTO_COMPLETE
+#define CONFIG_CMDLINE_EDITING
+#define CONFIG_HWCONFIG
+
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS	           16
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
+
+/* Memory configuration */
+#define CONFIG_SYS_MEMTEST_START       0x10000000
+#define CONFIG_SYS_MEMTEST_END	       0x10010000
+#define CONFIG_SYS_MEMTEST_SCRATCH     0x10800000
+#define CONFIG_SYS_TEXT_BASE	         0x17800000
+#define CONFIG_SYS_LOAD_ADDR           0x12000000
+
+/* Physical Memory Map */
+#define CONFIG_NR_DRAM_BANKS           1
+#define PHYS_SDRAM                     MMDC0_ARB_BASE_ADDR
+#define CONFIG_SYS_SDRAM_BASE          PHYS_SDRAM
+#define CONFIG_SYS_INIT_RAM_ADDR       IRAM_BASE_ADDR
+#define CONFIG_SYS_INIT_RAM_SIZE       IRAM_SIZE
+
+#define CONFIG_SYS_INIT_SP_OFFSET \
+	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR \
+	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+
+/* FLASH and environment organization */
+#define CONFIG_SYS_NO_FLASH  /* no NOR flash */
+
+/*
+ * MTD Command for mtdparts
+ */
+#define CONFIG_CMD_MTDPARTS
+#define CONFIG_MTD_DEVICE
+#define CONFIG_MTD_PARTITIONS
+#ifdef CONFIG_SPI_FLASH
+#define MTDIDS_DEFAULT    "nor0=nor"
+#define MTDPARTS_DEFAULT  \
+	"mtdparts=nor:512k(uboot),64k(env),2m(kernel),-(rootfs)"
+#else
+#define MTDIDS_DEFAULT    "nand0=nand"
+#define MTDPARTS_DEFAULT  "mtdparts=nand:16m(uboot),1m(env),-(rootfs)"
+#endif
+
+/* Persistent Environment Config */
+#define CONFIG_ENV_OVERWRITE    /* allow to overwrite serial and ethaddr */
+#ifdef CONFIG_SPI_FLASH
+#define CONFIG_ENV_IS_IN_SPI_FLASH
+#else
+#define CONFIG_ENV_IS_IN_NAND
+#endif
+#if defined(CONFIG_ENV_IS_IN_MMC)
+  #define CONFIG_ENV_OFFSET              (6 * 64 * 1024)
+  #define CONFIG_ENV_SIZE                (8 * 1024)
+  #define CONFIG_SYS_MMC_ENV_DEV         0
+#elif defined(CONFIG_ENV_IS_IN_NAND)
+  #define CONFIG_ENV_OFFSET              (16 << 20)
+  #define CONFIG_ENV_SECT_SIZE           (128 << 10)
+  #define CONFIG_ENV_SIZE                CONFIG_ENV_SECT_SIZE
+  #define CONFIG_ENV_OFFSET_REDUND       (CONFIG_ENV_OFFSET + (512 << 10))
+  #define CONFIG_ENV_SIZE_REDUND         CONFIG_ENV_SIZE
+#elif defined(CONFIG_ENV_IS_IN_SPI_FLASH)
+  #define CONFIG_ENV_OFFSET              (512 * 1024)
+  #define CONFIG_ENV_SECT_SIZE           (64 * 1024)
+  #define CONFIG_ENV_SIZE                (8 * 1024)
+  #define CONFIG_ENV_SPI_BUS             CONFIG_SF_DEFAULT_BUS
+  #define CONFIG_ENV_SPI_CS              CONFIG_SF_DEFAULT_CS
+  #define CONFIG_ENV_SPI_MODE            CONFIG_SF_DEFAULT_MODE
+  #define CONFIG_ENV_SPI_MAX_HZ          CONFIG_SF_DEFAULT_SPEED
+#endif
+
+/* Environment */
+#define CONFIG_BOOTDELAY          3
+#define CONFIG_LOADADDR           CONFIG_SYS_LOAD_ADDR
+#define CONFIG_IPADDR             192.168.1.1
+#define CONFIG_SERVERIP           192.168.1.146
+#define HWCONFIG_DEFAULT \
+	"hwconfig=rs232;" \
+	"dio0:mode=gpio;dio1:mode=gpio;dio2:mode=gpio;dio3:mode=gpio\0" \
+
+#define CONFIG_EXTRA_ENV_SETTINGS_COMMON \
+	"console=ttymxc1\0" \
+	"bootdevs=usb mmc sata flash\0" \
+	HWCONFIG_DEFAULT \
+	"video=\0" \
+	\
+	"mtdparts=" MTDPARTS_DEFAULT "\0" \
+	"mtdids=" MTDIDS_DEFAULT "\0" \
+	\
+	"fdt_high=0xffffffff\0" \
+	"fdt_addr=0x18000000\0" \
+	"loadfdt=" \
+		"if ${fsload} ${fdt_addr} boot/${fdt_file}; then " \
+			"echo Loaded DTB from boot/${fdt_file}; " \
+		"elif ${fsload} ${fdt_addr} boot/${fdt_file1}; then " \
+			"echo Loaded DTB from boot/${fdt_file1}; " \
+		"elif ${fsload} ${fdt_addr} boot/${fdt_file2}; then " \
+				"echo Loaded DTB from boot/${fdt_file2}; " \
+		"fi\0" \
+	\
+	"script=boot/6x_bootscript-ventana\0" \
+	"loadscript=" \
+		"if ${fsload} ${loadaddr} ${script}; then " \
+			"source; " \
+		"fi\0" \
+	\
+	"uimage=boot/uImage\0" \
+	"mmc_root=/dev/mmcblk0p1 rootfstype=ext4 rootwait rw\0" \
+	"mmc_boot=" \
+		"setenv fsload 'ext2load mmc 0:1'; " \
+		"mmc dev 0 && mmc rescan && " \
+		"run loadscript; " \
+		"if ${fsload} ${loadaddr} ${uimage}; then " \
+			"setenv bootargs console=${console},${baudrate} " \
+				"root=/dev/mmcblk0p1 rootfstype=ext4 " \
+				"rootwait rw ${video} ${extra}; " \
+			"if run loadfdt && fdt addr ${fdt_addr}; then " \
+				"bootm ${loadaddr} - ${fdt_addr}; " \
+			"else " \
+				"bootm; " \
+			"fi; " \
+		"fi\0" \
+	\
+	"sata_boot=" \
+		"setenv fsload 'ext2load sata 0:1'; sata init && " \
+		"run loadscript; " \
+		"if ${fsload} ${loadaddr} ${uimage}; then " \
+			"setenv bootargs console=${console},${baudrate} " \
+				"root=/dev/sda1 rootfstype=ext4 " \
+				"rootwait rw ${video} ${extra}; " \
+			"if run loadfdt && fdt addr ${fdt_addr}; then " \
+				"bootm ${loadaddr} - ${fdt_addr}; " \
+			"else " \
+				"bootm; " \
+			"fi; " \
+		"fi\0" \
+	"usb_boot=" \
+		"setenv fsload 'ext2load usb 0:1'; usb start && usb dev 0 && " \
+		"run loadscript; " \
+		"if ${fsload} ${loadaddr} ${uimage}; then " \
+			"setenv bootargs console=${console},${baudrate} " \
+				"root=/dev/sda1 rootfstype=ext4 " \
+				"rootwait rw ${video} ${extra}; " \
+			"if run loadfdt && fdt addr ${fdt_addr}; then " \
+				"bootm ${loadaddr} - ${fdt_addr}; " \
+			"else " \
+				"bootm; " \
+			"fi; " \
+		"fi\0"
+
+#ifdef CONFIG_SPI_FLASH
+	#define CONFIG_EXTRA_ENV_SETTINGS \
+	CONFIG_EXTRA_ENV_SETTINGS_COMMON \
+	"image_os=ventana/openwrt-imx6-imx6q-gw5400-a-squashfs.bin\0" \
+	"image_uboot=ventana/u-boot_spi.imx\0" \
+	\
+	"spi_koffset=0x90000\0" \
+	"spi_klen=0x200000\0" \
+	\
+	"spi_updateuboot=echo Updating uboot from " \
+		"${serverip}:${image_uboot}...; " \
+		"tftpboot ${loadaddr} ${image_uboot} && " \
+		"sf probe && sf erase 0 80000 && " \
+			"sf write ${loadaddr} 400 ${filesize}\0" \
+	"spi_update=echo Updating OS from ${serverip}:${image_os} " \
+		"to ${spi_koffset} ...; " \
+		"tftp ${loadaddr} ${image_os} && " \
+		"sf probe && " \
+		"sf update ${loadaddr} ${spi_koffset} ${filesize}\0" \
+	\
+	"flash_boot=" \
+		"if sf probe && " \
+		"sf read ${loadaddr} ${spi_koffset} ${spi_klen}; then " \
+			"setenv bootargs console=${console},${baudrate} " \
+				"root=/dev/mtdblock3 " \
+				"rootfstype=squashfs,jffs2 " \
+				"${video} ${extra}; " \
+			"bootm; " \
+		"fi\0"
+#else
+	#define CONFIG_EXTRA_ENV_SETTINGS \
+	CONFIG_EXTRA_ENV_SETTINGS_COMMON \
+	"image_rootfs=openwrt-imx6-ventana-rootfs.ubi\0" \
+	\
+	"nand_update=echo Updating NAND from ${serverip}:${image_rootfs}...; " \
+		"tftp ${loadaddr} ${image_rootfs} && " \
+		"nand erase.part rootfs && " \
+		"nand write ${loadaddr} rootfs ${filesize}\0" \
+	\
+	"flash_boot=" \
+		"setenv fsload 'ubifsload'; " \
+		"ubi part rootfs && ubifsmount ubi0:rootfs; " \
+		"run loadscript; " \
+		"if ${fsload} ${loadaddr} ${uimage}; then " \
+			"setenv bootargs console=${console},${baudrate} " \
+				"root=ubi0:rootfs ubi.mtd=2 " \
+				"rootfstype=ubifs ${video} ${extra}; " \
+			"if run loadfdt && fdt addr ${fdt_addr}; then " \
+				"ubifsumount; " \
+				"bootm ${loadaddr} - ${fdt_addr}; " \
+			"else " \
+				"ubifsumount; bootm; " \
+			"fi; " \
+		"fi\0"
+#endif
+
+#define CONFIG_BOOTCOMMAND \
+	"for btype in ${bootdevs}; do " \
+		"echo; echo Attempting ${btype} boot...; " \
+		"if run ${btype}_boot; then; fi; " \
+	"done"
+
+/* Device Tree Support */
+#define CONFIG_OF_BOARD_SETUP
+#define CONFIG_OF_LIBFDT
+#define CONFIG_FDT_FIXUP_PARTITIONS
+
+#ifndef CONFIG_SYS_DCACHE_OFF
+  #define CONFIG_CMD_CACHE
+#endif
+
+#endif			       /* __CONFIG_H */
diff --git a/include/configs/h2200.h b/include/configs/h2200.h
index 19ecc9ad6c..d02648420f 100644
--- a/include/configs/h2200.h
+++ b/include/configs/h2200.h
@@ -17,8 +17,6 @@
 
 #define CONFIG_SYS_NO_FLASH
 
-#define CONFIG_SYS_HZ			1000
-
 #define CONFIG_NR_DRAM_BANKS		1
 #define PHYS_SDRAM_1			0xa0000000 /* SDRAM Bank #1 */
 #define PHYS_SDRAM_1_SIZE		0x04000000 /* 64 MB */
diff --git a/include/configs/h2_p2_dbg_board.h b/include/configs/h2_p2_dbg_board.h
deleted file mode 100644
index 4ba2c55e98..0000000000
--- a/include/configs/h2_p2_dbg_board.h
+++ /dev/null
@@ -1,120 +0,0 @@
-/*
- *
- * BRIEF MODULE DESCRIPTION
- *   TI H2 and P2 Debug Board hardware map
- *
- * Copyright (C) 2004 MPC-Data Limited. (http://www.mpc-data.co.uk)
- * Author: MPC-Data Limited
- *	   Dave Peverley
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef __INCLUDED_H2_P2_DBH_BOARD_H
-#define __INCLUDED_H2_P2_DBH_BOARD_H
-
-#include <asm/sizes.h>
-
-/*
- * The Debug board is designed to function with the P2 Sample, H2
- * Sample and 1610 Innovator boards. The main difference AFAICT is
- * the chip selects used with each system ;
- *
- *   P2 Sample : CS1 of OMAP730 is used to select the CPLD & LAN regs
- *   H2 Sample : CS1a is used to select the CPLD registers.
- *
- */
-
-/***************************************************************************
- * CPLD Registers
- **************************************************************************/
-
-#define H2DBG_CPLD_REVISION        0x04000010
-#define H2DBG_BOARD_REVISION       0x04000012
-#define H2DBG_GPIO_REGISTER        0x04000014
-#define H2DBG_LED_CONTROL          0x04000016
-#define H2DBG_MISC_INPUT           0x04000018
-#define H2DBG_LAN_STATUS           0x0400001A
-#define H2DBG_LAN_RESET            0x0400001C
-#define H2DBG_ETH_REG_BASE         0x04000300
-
-/***************************************************************************
- * Ethernet Control Registers
- * These are for the LAN91C96 on the debug board
- **************************************************************************/
-
-/* Bank 0 in IO space */
-
-#define ETH_TCR            (H2DBG_ETH_REG_BASE + 0x00)   /* Transmit Control Register */
-#define ETH_EPH_STATUS     (H2DBG_ETH_REG_BASE + 0x02)   /* EPH Status Register */
-#define ETH_RCR            (H2DBG_ETH_REG_BASE + 0x04)   /* Receive Control Register */
-#define ETH_COUNTER        (H2DBG_ETH_REG_BASE + 0x06)   /* Counter Register */
-#define ETH_MIR            (H2DBG_ETH_REG_BASE + 0x08)   /* Memory Information Register */
-#define ETH_MCR            (H2DBG_ETH_REG_BASE + 0x0A)   /* Memory Configuration Register */
-
-/* Bank 1 in IO space */
-
-#define ETH_CONFIG         (H2DBG_ETH_REG_BASE + 0x00)   /* Configuration Register */
-#define ETH_BASE           (H2DBG_ETH_REG_BASE + 0x02)   /* Base Address Register */
-#define ETH_IA0            (H2DBG_ETH_REG_BASE + 0x04)   /* Individual Address Register - 0 */
-#define ETH_IA1            (H2DBG_ETH_REG_BASE + 0x05)   /* Individual Address Register - 1 */
-#define ETH_IA2            (H2DBG_ETH_REG_BASE + 0x06)   /* Individual Address Register - 2 */
-#define ETH_IA3            (H2DBG_ETH_REG_BASE + 0x07)   /* Individual Address Register - 3 */
-#define ETH_IA4            (H2DBG_ETH_REG_BASE + 0x08)   /* Individual Address Register - 4 */
-#define ETH_IA5            (H2DBG_ETH_REG_BASE + 0x09)   /* Individual Address Register - 5 */
-#define ETH_GEN_PURPOSE    (H2DBG_ETH_REG_BASE + 0x0A)   /* General Address Registers */
-#define ETH_CONTROL        (H2DBG_ETH_REG_BASE + 0x0B)   /* Control Register */
-
-/* Bank 2 in IO space */
-
-#define ETH_MMU            (H2DBG_ETH_REG_BASE + 0x00)   /* MMU Command Register */
-#define ETH_AUTO_TX_START  (H2DBG_ETH_REG_BASE + 0x01)   /* Auto Tx Start Register */
-#define ETH_PNR            (H2DBG_ETH_REG_BASE + 0x02)   /* Packet Number Register */
-#define ETH_ARR            (H2DBG_ETH_REG_BASE + 0x03)   /* Allocation Result Register */
-#define ETH_FIFO           (H2DBG_ETH_REG_BASE + 0x04)   /* FIFO Ports Register */
-#define ETH_POINTER        (H2DBG_ETH_REG_BASE + 0x06)   /* Pointer Register */
-#define ETH_DATA_HIGH      (H2DBG_ETH_REG_BASE + 0x08)   /* Data High Register */
-#define ETH_DATA_LOW       (H2DBG_ETH_REG_BASE + 0x0A)   /* Data Low Register */
-#define ETH_INT_STATS      (H2DBG_ETH_REG_BASE + 0x0C)   /* Interrupt Status Register - RO */
-#define ETH_INT_ACK        (H2DBG_ETH_REG_BASE + 0x0C)   /* Interrupt Acknowledge Register -WO */
-#define ETH_INT_MASK       (H2DBG_ETH_REG_BASE + 0x0D)   /* Interrupt Mask Register */
-
-
-#ifndef __ASSEMBLY__
-
-/*
- * A couple of utility inlines to aid debugging using the LED's on the
- * debug board.
- */
-
-static inline void set_led_state(int state)
-{
-	static unsigned long hw_led_state = 0;
-	volatile unsigned short *led_address = (volatile unsigned short *)0x04000016;
-
-	hw_led_state = ((unsigned long)state);
-	*((unsigned short *) (led_address)) = (unsigned short) (~hw_led_state & 0xFFFF);
-}
-
-
-static inline void spin_up_leds(void)
-{
-	volatile int i, j, k;
-
-	for (k = 0; k < 2; k++) {
-		for (i = 0; i < 16; i++) {
-			for (j = 0; j < 5000; j++) {
-				set_led_state(1 << i);
-			}
-		}
-		for (i = 15; i >= 0; i--) {
-			for (j = 0; j < 5000; j++) {
-				set_led_state(1 << i);
-			}
-		}
-	}
-}
-
-#endif    /* !  __ASSEMBLY__ */
-
-#endif    /* !  __INCLUDED_H2_P2_DBH_BOARD_H */
diff --git a/include/configs/hammerhead.h b/include/configs/hammerhead.h
index 38c70aca32..4f0603abc1 100644
--- a/include/configs/hammerhead.h
+++ b/include/configs/hammerhead.h
@@ -8,13 +8,10 @@
 #ifndef __CONFIG_H
 #define __CONFIG_H
 
-#define CONFIG_AVR32
 #define CONFIG_AT32AP
 #define CONFIG_AT32AP7000
 #define CONFIG_HAMMERHEAD
 
-#define CONFIG_SYS_HZ				1000
-
 /*
  * Set up the PLL to run at 125 MHz, the CPU to run at the PLL
  * frequency, the HSB and PBB busses to run at 1/2 the PLL frequency
diff --git a/include/configs/harmony.h b/include/configs/harmony.h
index d733be9cd5..3ec0e418c1 100644
--- a/include/configs/harmony.h
+++ b/include/configs/harmony.h
@@ -8,7 +8,7 @@
 #ifndef __CONFIG_H
 #define __CONFIG_H
 
-#include <asm/sizes.h>
+#include <linux/sizes.h>
 #include "tegra20-common.h"
 
 /* Enable fdt support for Harmony. Flash the image in u-boot-dtb.bin */
@@ -61,8 +61,9 @@
 
 /* USB networking support */
 #define CONFIG_USB_HOST_ETHER
-#define CONFIG_USB_ETHER_SMSC95XX
 #define CONFIG_USB_ETHER_ASIX
+#define CONFIG_USB_ETHER_MCS7830
+#define CONFIG_USB_ETHER_SMSC95XX
 
 /* General networking support */
 #define CONFIG_CMD_NET
diff --git a/include/configs/hawkboard.h b/include/configs/hawkboard.h
index b8197ac189..73e1624375 100644
--- a/include/configs/hawkboard.h
+++ b/include/configs/hawkboard.h
@@ -28,7 +28,6 @@
 #define CONFIG_SYS_OSCIN_FREQ		24000000
 #define CONFIG_SYS_TIMERBASE		DAVINCI_TIMER0_BASE
 #define CONFIG_SYS_HZ_CLOCK		clk_get(DAVINCI_AUXCLK_CLKID)
-#define CONFIG_SYS_HZ			1000
 #define CONFIG_SKIP_LOWLEVEL_INIT
 #define CONFIG_BOARD_EARLY_INIT_F
 #define CONFIG_AIS_CONFIG_FILE		"board/$(BOARDDIR)/hawkboard-ais-nand.cfg"
diff --git a/include/configs/hermes.h b/include/configs/hermes.h
index 1af529627e..736ffb613d 100644
--- a/include/configs/hermes.h
+++ b/include/configs/hermes.h
@@ -70,7 +70,6 @@
  * Miscellaneous configurable options
  */
 #define	CONFIG_SYS_LONGHELP			/* undef to save memory		*/
-#define	CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt	*/
 #if defined(CONFIG_CMD_KGDB)
 #define	CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
 #else
@@ -87,8 +86,6 @@
 
 #define	CONFIG_SYS_PIO_MODE		0	/* IDE interface in PIO Mode 0	*/
 
-#define	CONFIG_SYS_HZ			1000	/* decrementer freq: 1 ms ticks	*/
-
 #define	CONFIG_SYS_ALLOC_DPRAM		1	/* use allocation routines	*/
 /*
  * Low Level Configuration Settings
diff --git a/include/configs/highbank.h b/include/configs/highbank.h
index afb6e64e1b..7dbee3cdb9 100644
--- a/include/configs/highbank.h
+++ b/include/configs/highbank.h
@@ -8,12 +8,9 @@
 #define __CONFIG_H
 
 #define CONFIG_SYS_DCACHE_OFF
-#define CONFIG_L2_OFF
 #define CONFIG_SYS_THUMB_BUILD
 
 #define CONFIG_SYS_NO_FLASH
-#define CFG_HZ				1000
-#define CONFIG_SYS_HZ			CFG_HZ
 
 #define CONFIG_OF_LIBFDT
 #define CONFIG_OF_BOARD_SETUP
@@ -21,6 +18,10 @@
 #define CONFIG_SUPPORT_RAW_INITRD
 #define CONFIG_SYS_BOOTMAPSZ		(16 << 20)
 
+#define CONFIG_SYS_TIMER_RATE		(150000000/256)
+#define CONFIG_SYS_TIMER_COUNTER	(0xFFF34000 + 0x4)
+#define CONFIG_SYS_TIMER_COUNTS_DOWN
+
 /*
  * Size of malloc() pool
  */
@@ -80,7 +81,7 @@
 #define CONFIG_RESET_TO_RETRY
 #define CONFIG_AUTOBOOT_KEYED
 #define CONFIG_AUTOBOOT_PROMPT "Autobooting in %d seconds...\nPress <s> to stop or <d> to delay\n", bootdelay
-
+#define CONFIG_AUTOBOOT_KEYED_CTRLC
 /*
  * Miscellaneous configurable options
  */
diff --git a/include/configs/hmi1001.h b/include/configs/hmi1001.h
index 9073d7e6c7..a1a88b5e33 100644
--- a/include/configs/hmi1001.h
+++ b/include/configs/hmi1001.h
@@ -13,9 +13,8 @@
  * (easy to change)
  */
 
-#define CONFIG_MPC5xxx		1	/* This is an MPC5xxx CPU		*/
-#define CONFIG_MPC5200		1	/* (more precisely an MPC5200 CPU)	*/
-#define CONFIG_HMI1001		1	/* HMI1001 board			*/
+#define CONFIG_MPC5200		1	/* This is an MPC5200 CPU	*/
+#define CONFIG_HMI1001		1	/* HMI1001 board		*/
 
 #ifndef CONFIG_SYS_TEXT_BASE
 #define CONFIG_SYS_TEXT_BASE	0xFFF00000
@@ -214,7 +213,6 @@
  * Miscellaneous configurable options
  */
 #define CONFIG_SYS_LONGHELP			/* undef to save memory	    */
-#define CONFIG_SYS_PROMPT		"=> "	/* Monitor Command Prompt   */
 #if defined(CONFIG_CMD_KGDB)
 #define CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size  */
 #else
@@ -237,8 +235,6 @@
 
 #define CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address */
 
-#define CONFIG_SYS_HZ			1000	/* decrementer freq: 1 ms ticks */
-
 /*
  * Enable loopw command.
  */
diff --git a/include/configs/hummingboard.h b/include/configs/hummingboard.h
new file mode 100644
index 0000000000..2895523344
--- /dev/null
+++ b/include/configs/hummingboard.h
@@ -0,0 +1,225 @@
+/*
+ * Copyright (C) 2013 Freescale Semiconductor, Inc.
+ * Copyright (C) 2013 SolidRun ltd.
+ * Copyright (C) 2013 Jon Nettleton <jon.nettleton@gmail.com>
+ *
+ * Configuration settings for the SolidRun Hummingboard.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include "mx6_common.h"
+#include <asm/arch/imx-regs.h>
+#include <asm/imx-common/gpio.h>
+#include <linux/sizes.h>
+
+#define CONFIG_MX6
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DISPLAY_BOARDINFO
+
+#define CONFIG_MACH_TYPE		4773
+
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+#define CONFIG_REVISION_TAG
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN		(2 * SZ_1M)
+
+#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_MXC_GPIO
+
+#define CONFIG_MXC_UART
+#define CONFIG_MXC_UART_BASE		UART1_BASE
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_CONS_INDEX		1
+#define CONFIG_BAUDRATE			115200
+
+/* Command definition */
+#include <config_cmd_default.h>
+
+#undef CONFIG_CMD_IMLS
+#undef CONFIG_CMD_I2C
+
+#define CONFIG_CMD_BMODE
+#define CONFIG_CMD_SETEXPR
+#define CONFIG_CMD_MEMTEST
+#define CONFIG_BOOTDELAY		3
+
+#define CONFIG_SYS_MEMTEST_START	0x10000000
+#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_MEMTEST_START + 500 * SZ_1M)
+#define CONFIG_LOADADDR			0x12000000
+#define CONFIG_SYS_TEXT_BASE		0x17800000
+
+/* MMC Configuration */
+#define CONFIG_FSL_ESDHC
+#define CONFIG_FSL_USDHC
+#define CONFIG_SYS_FSL_USDHC_NUM	1
+#define CONFIG_SYS_FSL_ESDHC_ADDR	0
+
+#define CONFIG_MMC
+#define CONFIG_CMD_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_BOUNCE_BUFFER
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_FAT
+#define CONFIG_DOS_PARTITION
+
+/* Ethernet Configuration */
+#define CONFIG_FEC_MXC
+#ifdef CONFIG_FEC_MXC
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NET
+#define CONFIG_MII
+#define IMX_FEC_BASE			ENET_BASE_ADDR
+#define CONFIG_FEC_XCV_TYPE		RGMII
+#define CONFIG_FEC_MXC_PHYADDR		0
+#define CONFIG_PHYLIB
+#define CONFIG_PHY_ATHEROS
+#endif
+
+#if defined(CONFIG_MX6S)
+#define CONFIG_DEFAULT_FDT_FILE		"imx6dl-hummingboard.dtb"
+#endif
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"script=boot.scr\0" \
+	"image=zImage\0" \
+	"console=ttymxc0\0" \
+	"splashpos=m,m\0" \
+	"fdt_high=0xffffffff\0" \
+	"initrd_high=0xffffffff\0" \
+	"fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \
+	"fdt_addr=0x18000000\0" \
+	"boot_fdt=try\0" \
+	"ip_dyn=yes\0" \
+	"mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \
+	"mmcpart=1\0" \
+	"mmcroot=/dev/mmcblk0p2 rootwait rw\0" \
+	"update_sd_firmware_filename=u-boot.imx\0" \
+	"update_sd_firmware=" \
+		"if test ${ip_dyn} = yes; then " \
+			"setenv get_cmd dhcp; " \
+		"else " \
+			"setenv get_cmd tftp; " \
+		"fi; " \
+		"if mmc dev ${mmcdev}; then "	\
+			"if ${get_cmd} ${update_sd_firmware_filename}; then " \
+				"setexpr fw_sz ${filesize} / 0x200; " \
+				"setexpr fw_sz ${fw_sz} + 1; "	\
+				"mmc write ${loadaddr} 0x2 ${fw_sz}; " \
+			"fi; "	\
+		"fi\0" \
+	"mmcargs=setenv bootargs console=${console},${baudrate} " \
+		"root=${mmcroot}\0" \
+	"loadbootscript=" \
+		"fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
+	"bootscript=echo Running bootscript from mmc ...; " \
+		"source\0" \
+	"loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
+	"loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
+	"mmcboot=echo Booting from mmc ...; " \
+		"run mmcargs; " \
+		"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
+			"if run loadfdt; then " \
+				"bootz ${loadaddr} - ${fdt_addr}; " \
+			"else " \
+				"if test ${boot_fdt} = try; then " \
+					"bootz; " \
+				"else " \
+					"echo WARN: Cannot load the DT; " \
+				"fi; " \
+			"fi; " \
+		"else " \
+			"bootz; " \
+		"fi;\0" \
+	"netargs=setenv bootargs console=${console},${baudrate} " \
+		"root=/dev/nfs " \
+	"ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
+		"netboot=echo Booting from net ...; " \
+		"run netargs; " \
+		"if test ${ip_dyn} = yes; then " \
+			"setenv get_cmd dhcp; " \
+		"else " \
+			"setenv get_cmd tftp; " \
+		"fi; " \
+		"${get_cmd} ${image}; " \
+		"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
+			"if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
+				"bootz ${loadaddr} - ${fdt_addr}; " \
+			"else " \
+				"if test ${boot_fdt} = try; then " \
+					"bootz; " \
+				"else " \
+					"echo WARN: Cannot load the DT; " \
+				"fi; " \
+			"fi; " \
+		"else " \
+			"bootz; " \
+		"fi;\0"
+
+#define CONFIG_BOOTCOMMAND \
+	   "mmc dev ${mmcdev}; if mmc rescan; then " \
+		   "if run loadbootscript; then " \
+			   "run bootscript; " \
+		   "else " \
+			   "if run loadimage; then " \
+				   "run mmcboot; " \
+			   "else run netboot; " \
+			   "fi; " \
+		   "fi; " \
+	   "else run netboot; fi"
+
+/* Miscellaneous configurable options */
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_AUTO_COMPLETE
+#define CONFIG_SYS_CBSIZE		1024
+
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS	       16
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
+
+#define CONFIG_SYS_LOAD_ADDR		CONFIG_LOADADDR
+
+#define CONFIG_CMDLINE_EDITING
+
+/* Physical Memory Map */
+#define CONFIG_NR_DRAM_BANKS		1
+#define PHYS_SDRAM			MMDC0_ARB_BASE_ADDR
+
+#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM
+#define CONFIG_SYS_INIT_RAM_ADDR	IRAM_BASE_ADDR
+#define CONFIG_SYS_INIT_RAM_SIZE	IRAM_SIZE
+
+#define CONFIG_SYS_INIT_SP_OFFSET \
+	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR \
+	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+
+/* FLASH and environment organization */
+#define CONFIG_SYS_NO_FLASH
+
+#define CONFIG_ENV_SIZE			(8 * 1024)
+
+#define CONFIG_ENV_IS_IN_MMC
+#define CONFIG_ENV_OFFSET		(6 * 64 * 1024)
+#define CONFIG_SYS_MMC_ENV_DEV		0
+
+#define CONFIG_OF_LIBFDT
+#define CONFIG_CMD_BOOTZ
+
+#ifndef CONFIG_SYS_DCACHE_OFF
+#define CONFIG_CMD_CACHE
+#endif
+
+#endif			       /* __CONFIG_H * */
diff --git a/include/configs/hymod.h b/include/configs/hymod.h
index f73de6814d..c973365e12 100644
--- a/include/configs/hymod.h
+++ b/include/configs/hymod.h
@@ -17,7 +17,6 @@
  * (easy to change)
  */
 
-#define CONFIG_MPC8260		1	/* This is an MPC8260 CPU	*/
 #define CONFIG_HYMOD		1	/* ...on a Hymod board		*/
 #define CONFIG_CPM2		1	/* Has a CPM2 */
 
@@ -256,7 +255,6 @@
  * Miscellaneous configurable options
  */
 #define	CONFIG_SYS_LONGHELP			/* undef to save memory		*/
-#define	CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt	*/
 #if defined(CONFIG_CMD_KGDB)
 #define	CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
 #else
@@ -271,8 +269,6 @@
 
 #define	CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address	*/
 
-#define	CONFIG_SYS_HZ		1000		/* decrementer freq: 1 ms ticks	*/
-
 #define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
 
 #define	CONFIG_SYS_I2C_SPEED		50000
diff --git a/include/configs/ib62x0.h b/include/configs/ib62x0.h
index 7fa0c5356c..186fd35fdb 100644
--- a/include/configs/ib62x0.h
+++ b/include/configs/ib62x0.h
@@ -28,6 +28,11 @@
 #define CONFIG_MACH_TYPE	MACH_TYPE_NAS6210
 
 /*
+ * Enable device tree support
+ */
+#define CONFIG_OF_LIBFDT
+
+/*
  * Compression configuration
  */
 #define CONFIG_BZIP2
@@ -41,6 +46,7 @@
 #define CONFIG_SYS_MVFS
 #include <config_cmd_default.h>
 #define CONFIG_CMD_ENV
+#define CONFIG_CMD_BOOTZ
 #define CONFIG_CMD_IDE
 #define CONFIG_CMD_MII
 #define CONFIG_CMD_NAND
@@ -66,7 +72,7 @@
 #define CONFIG_ENV_IS_NOWHERE
 #endif
 #define CONFIG_ENV_SIZE		0x20000
-#define CONFIG_ENV_OFFSET	0x80000
+#define CONFIG_ENV_OFFSET	0xe0000
 
 /*
  * Default environment variables
@@ -74,24 +80,26 @@
 #define CONFIG_BOOTCOMMAND \
 	"setenv bootargs ${console} ${mtdparts} ${bootargs_root}; "	\
 	"ubi part root; "						\
-	"ubifsmount ubi:root; "						\
+	"ubifsmount ubi:rootfs; "					\
 	"ubifsload 0x800000 ${kernel}; "				\
-	"ubifsload 0x1100000 ${initrd}; "				\
-	"bootm 0x800000 0x1100000"
-
-#define CONFIG_MTDPARTS				\
-	"mtdparts=orion_nand:"			\
-	"0x80000@0x0(uboot),"			\
-	"0x20000@0x80000(uboot_env),"		\
-	"-@0xa0000(root)\0"
-
-#define CONFIG_EXTRA_ENV_SETTINGS					\
+	"ubifsload 0x700000 ${fdt}; "					\
+	"ubifsumount; "							\
+	"fdt addr 0x700000; fdt resize; fdt chosen; "			\
+	"bootz 0x800000 - 0x700000"
+
+#define CONFIG_MTDPARTS \
+	"mtdparts=orion_nand:"						\
+	"0xe0000@0x0(uboot),"						\
+	"0x20000@0xe0000(uboot_env),"					\
+	"-@0x100000(root)\0"
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
 	"console=console=ttyS0,115200\0"				\
 	"mtdids=nand0=orion_nand\0"					\
 	"mtdparts="CONFIG_MTDPARTS					\
-	"kernel=/boot/uImage\0"						\
-	"initrd=/boot/uInitrd\0"					\
-	"bootargs_root=ubi.mtd=2 root=ubi0:root rootfstype=ubifs\0"
+	"kernel=/boot/zImage\0"						\
+	"fdt=/boot/ib62x0.dtb\0"					\
+	"bootargs_root=ubi.mtd=2 root=ubi0:rootfs rootfstype=ubifs rw\0"
 
 /*
  * Ethernet driver configuration
diff --git a/include/configs/ibf-dsp561.h b/include/configs/ibf-dsp561.h
index 5291755121..ac5ca9af37 100644
--- a/include/configs/ibf-dsp561.h
+++ b/include/configs/ibf-dsp561.h
@@ -95,8 +95,8 @@
  * it linked after the configuration sector.
  */
 # define LDS_BOARD_TEXT \
-	arch/blackfin/lib/libblackfin.o (.text*); \
-	arch/blackfin/cpu/libblackfin.o (.text*); \
+	arch/blackfin/lib/built-in.o (.text*); \
+	arch/blackfin/cpu/built-in.o (.text*); \
 	. = DEFINED(env_offset) ? env_offset : .; \
 	common/env_embedded.o (.text*);
 #endif
diff --git a/include/configs/icon.h b/include/configs/icon.h
index eafcf5aeaf..bbe9b59b53 100644
--- a/include/configs/icon.h
+++ b/include/configs/icon.h
@@ -16,7 +16,6 @@
  * High Level Configuration Options
  */
 #define CONFIG_ICON		1		/* Board is icon	*/
-#define CONFIG_4xx		1		/* ... PPC4xx family	*/
 #define CONFIG_440		1		/* ... PPC440 family	*/
 #define CONFIG_440SPE		1		/* Specifc SPe support	*/
 
diff --git a/include/configs/idmr.h b/include/configs/idmr.h
deleted file mode 100644
index 3cae30a0b4..0000000000
--- a/include/configs/idmr.h
+++ /dev/null
@@ -1,241 +0,0 @@
-/*
- * Configuration settings for the iDMR board
- *
- * Based on MC5272C3, r5200  and M5271EVB board configs
- * (C) Copyright 2006 Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- * (C) Copyright 2006 Lab X Technologies <zachary.landau@labxtechnologies.com>
- * (C) Copyright 2003 Josef Baumgartner <josef.baumgartner@telex.de>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef _IDMR_H
-#define _IDMR_H
-
-
-/*
- * High Level Configuration Options (easy to change)
- */
-
-#define CONFIG_MCF52x2		/* define processor family */
-#define CONFIG_M5271		/* define processor type */
-#define CONFIG_IDMR		/* define board type */
-
-#undef CONFIG_WATCHDOG		/* disable watchdog */
-
-/*
- * Default environment settings
- */
-#define CONFIG_BOOTCOMMAND	"run net_nfs"
-#define CONFIG_BOOTDELAY	5
-#define CONFIG_MCFUART
-#define CONFIG_SYS_UART_PORT		(0)
-#define CONFIG_BAUDRATE		19200
-#define CONFIG_ETHADDR		00:06:3b:01:41:55
-#define CONFIG_ETHPRIME
-#define CONFIG_IPADDR		192.168.30.1
-#define CONFIG_SERVERIP		192.168.1.1
-#define CONFIG_ROOTPATH		""
-#define CONFIG_GATEWAYIP	192.168.1.1
-#define CONFIG_NETMASK		255.255.0.0
-#define CONFIG_HOSTNAME		idmr
-#define CONFIG_BOOTFILE		"/tftpboot/idmr/uImage"
-#define CONFIG_PREBOOT		"echo;echo Type \\\"run flash_nfs\\\" to mount root " \
-				"filesystem over NFS; echo"
-
-#define CONFIG_MCFTMR
-
-#define CONFIG_EXTRA_ENV_SETTINGS					\
-	"netdev=eth0\0"							\
-	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
-	"addip=setenv bootargs $(bootargs) "				\
-		"ip=$(ipaddr):$(serverip):$(gatewayip):"		\
-		"$(netmask):$(hostname):$(netdev):off panic=1\0"	\
-	"flash_nfs=run nfsargs addip;bootm $(kernel_addr)\0"		\
-	"flash_self=run ramargs addip;bootm $(kernel_addr) "		\
-		"$(ramdisk_addr)\0"					\
-	"net_nfs=tftp 200000 $(bootfile);run nfsargs addip;bootm\0"	\
-	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
-		"nfsroot=$(serverip):$(rootpath)\0"			\
-	"ethact=FEC\0	"						\
-	"update=prot off ff800000 ff81ffff; era ff800000 ff81ffff; "	\
-		"cp.b 200000 ff800000 $(filesize);"			\
-		"prot on ff800000 ff81ffff\0"				\
-	"load=tftp 200000 $(u-boot)\0"					\
-	"u-boot=/tftpboot/idmr/u-boot.bin\0"				\
-	""
-
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_JFFS2
-#define CONFIG_CMD_NET
-
-#undef CONFIG_CMD_LOADS
-#undef CONFIG_CMD_LOADB
-
-
-/*
- * Low Level Configuration Settings
- * (address mappings, register initial values, etc.)
- * You should know what you are doing if you make changes here.
- */
-
-/*
- * Configuration for environment, which occupies third sector in flash.
- */
-#ifndef CONFIG_MONITOR_IS_IN_RAM
-#define CONFIG_ENV_ADDR		0xff820000
-#define CONFIG_ENV_SECT_SIZE	0x10000
-#define CONFIG_ENV_SIZE		0x2000
-#define CONFIG_ENV_IS_IN_FLASH
-#else /* CONFIG_MONITOR_IS_IN_RAM */
-#define CONFIG_ENV_OFFSET		0x4000
-#define CONFIG_ENV_SECT_SIZE	0x2000
-#define CONFIG_ENV_IS_IN_FLASH
-#endif /* !CONFIG_MONITOR_IS_IN_RAM */
-
-#define	CONFIG_SYS_USE_PPCENV			/* Environment embedded in sect .ppcenv */
-
-#define CONFIG_SYS_PROMPT		"=> "
-#define CONFIG_SYS_LONGHELP				/* undef to save memory */
-
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CBSIZE		1024		/* Console I/O Buffer Size */
-#else
-#define CONFIG_SYS_CBSIZE		256		/* Console I/O Buffer Size */
-#endif
-
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS		16		/* max number of command args */
-#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size */
-
-#define CONFIG_SYS_LOAD_ADDR		0x00100000
-
-#define CONFIG_SYS_MEMTEST_START	0x400
-#define CONFIG_SYS_MEMTEST_END		0x380000
-
-#define CONFIG_SYS_HZ			(50000000 / 64)
-#define CONFIG_SYS_CLK			100000000
-
-#define CONFIG_SYS_MBAR		0x40000000	/* Register Base Addrs */
-
-/*
- * Ethernet
- */
-#define CONFIG_MCFFEC
-#ifdef CONFIG_MCFFEC
-#	define CONFIG_MII		1
-#	define CONFIG_MII_INIT		1
-#	define CONFIG_SYS_DISCOVER_PHY
-#	define CONFIG_SYS_RX_ETH_BUFFER	8
-#	define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
-
-#	define CONFIG_SYS_FEC0_PINMUX		0
-#	define CONFIG_SYS_FEC0_MIIBASE		CONFIG_SYS_FEC0_IOBASE
-#	define MCFFEC_TOUT_LOOP		50000
-/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
-#	ifndef CONFIG_SYS_DISCOVER_PHY
-#		define FECDUPLEX	FULL
-#		define FECSPEED		_100BASET
-#	else
-#		ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
-#			define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
-#		endif
-#	endif			/* CONFIG_SYS_DISCOVER_PHY */
-#endif
-
-/*
- * Definitions for initial stack pointer and data area (in DPRAM)
- */
-#define CONFIG_SYS_INIT_RAM_ADDR	0x20000000
-#define CONFIG_SYS_INIT_RAM_SIZE	0x1000	/* Size of used area in internal SRAM */
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
-
-/*
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
- */
-#define CONFIG_SYS_SDRAM_BASE		0x00000000
-#define CONFIG_SYS_SDRAM_SIZE		16		/* SDRAM size in MB */
-#define CONFIG_SYS_FLASH_BASE		0xff800000
-
-#ifdef CONFIG_MONITOR_IS_IN_RAM
-#define CONFIG_SYS_MONITOR_BASE	0x20000
-#else /* !CONFIG_MONITOR_IS_IN_RAM */
-#define CONFIG_SYS_MONITOR_BASE	(CONFIG_SYS_FLASH_BASE + 0x400)
-#endif /* CONFIG_MONITOR_IS_IN_RAM */
-
-#define CONFIG_SYS_MONITOR_LEN		0x20000
-#define CONFIG_SYS_MALLOC_LEN		(256 << 10)
-#define CONFIG_SYS_BOOTPARAMS_LEN	(64*1024)
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization ??
- */
-#define CONFIG_SYS_BOOTMAPSZ		(CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
-
-/* FLASH organization */
-#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks */
-#define CONFIG_SYS_MAX_FLASH_SECT	128	/* max number of sectors on one chip */
-#define CONFIG_SYS_FLASH_ERASE_TOUT	1000
-
-#define CONFIG_SYS_FLASH_SIZE		0x800000
-/*
- * #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE	1
- */
-
-/* Cache Configuration */
-#define CONFIG_SYS_CACHELINE_SIZE	16
-
-#define ICACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
-					 CONFIG_SYS_INIT_RAM_SIZE - 8)
-#define DCACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
-					 CONFIG_SYS_INIT_RAM_SIZE - 4)
-#define CONFIG_SYS_ICACHE_INV		(CF_CACR_CINV | CF_CACR_INVI)
-#define CONFIG_SYS_CACHE_ACR0		(CONFIG_SYS_SDRAM_BASE | \
-					 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
-					 CF_ACR_EN | CF_ACR_SM_ALL)
-#define CONFIG_SYS_CACHE_ICACR		(CF_CACR_CENB | CF_CACR_CINV | \
-					 CF_CACR_DISD | CF_CACR_INVI | \
-					 CF_CACR_CEIB | CF_CACR_DCM | \
-					 CF_CACR_EUSP)
-
-/* Port configuration */
-#define CONFIG_SYS_FECI2C		0xF0
-
-
-/* Dynamic MTD partition support */
-#define CONFIG_CMD_MTDPARTS
-#define CONFIG_MTD_DEVICE		/* needed for mtdparts commands */
-#define CONFIG_FLASH_CFI_MTD
-#define MTDIDS_DEFAULT		"nor0=idmr-0"
-
-#define MTDPARTS_DEFAULT	"mtdparts=idmr-0:128k(u-boot),"	\
-						"64k(env),"	\
-						"640k(kernel),"	\
-						"2m(rootfs),"	\
-						"-(user)";
-
-#if defined(CONFIG_CMD_MII)
-#error "MII commands don't work on iDMR board and should not be enabled."
-#endif
-
-#endif /* _IDMR_H */
diff --git a/include/configs/igep0033.h b/include/configs/igep0033.h
deleted file mode 100644
index 3e18a657fa..0000000000
--- a/include/configs/igep0033.h
+++ /dev/null
@@ -1,290 +0,0 @@
-/*
- * Copyright (C) 2013, ISEE 2007 SL - http://www.isee.biz/
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation version 2.
- *
- * This program is distributed "as is" WITHOUT ANY WARRANTY of any
- * kind, whether express or implied; without even the implied warranty
- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#ifndef __CONFIG_IGEP0033_H
-#define __CONFIG_IGEP0033_H
-
-#define CONFIG_AM33XX
-#define CONFIG_OMAP
-#define CONFIG_OMAP_COMMON
-
-#include <asm/arch/omap.h>
-
-/* Mach type */
-#define MACH_TYPE_IGEP0033		4521	/* Until the next sync */
-#define CONFIG_MACH_TYPE		MACH_TYPE_IGEP0033
-
-/* Clock defines */
-#define V_OSCK				24000000  /* Clock output from T2 */
-#define V_SCLK				(V_OSCK)
-
-#define CONFIG_ENV_SIZE			(128 << 10)	/* 128 KiB */
-#define CONFIG_SYS_MALLOC_LEN		(1024 << 10)
-#define CONFIG_SYS_LONGHELP		/* undef to save memory */
-#define CONFIG_SYS_HUSH_PARSER		/* use "hush" command parser */
-#define CONFIG_SYS_PROMPT		"U-Boot# "
-#define CONFIG_SYS_NO_FLASH
-
-/* Display cpuinfo */
-#define CONFIG_DISPLAY_CPUINFO
-
-/* Flattened Device Tree */
-#define CONFIG_OF_LIBFDT
-
-/* Commands to include */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_ASKENV
-#define CONFIG_CMD_BOOTZ
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_ECHO
-#define CONFIG_CMD_EXT4
-#define CONFIG_CMD_FAT
-#define CONFIG_CMD_FS_GENERIC
-#define CONFIG_CMD_MMC
-#define CONFIG_CMD_MTDPARTS
-#define CONFIG_CMD_NAND
-#define CONFIG_CMD_NET
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_UBI
-#define CONFIG_CMD_UBIFS
-
-/* Make the verbose messages from UBI stop printing */
-#define CONFIG_UBI_SILENCE_MSG
-#define CONFIG_UBIFS_SILENCE_MSG
-
-#define CONFIG_BOOTDELAY		1	/* negative for no autoboot */
-#define CONFIG_ENV_VARS_UBOOT_CONFIG
-#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
-#define CONFIG_EXTRA_ENV_SETTINGS \
-	"loadaddr=0x80F80000\0" \
-	"dtbaddr=0x80200000\0" \
-	"bootdir=/boot\0" \
-	"bootfile=zImage\0" \
-	"dtbfile=am335x-base0033.dtb\0" \
-	"console=ttyO0,115200n8\0" \
-	"mtdids=" MTDIDS_DEFAULT "\0" \
-	"mtdparts=" MTDPARTS_DEFAULT "\0" \
-	"mmcdev=0\0" \
-	"mmcroot=/dev/mmcblk0p2 rw\0" \
-	"ubiroot=ubi0:filesystem rw ubi.mtd=3,2048\0" \
-	"mmcrootfstype=ext4 rootwait\0" \
-	"ubirootfstype=ubifs rootwait\0" \
-	"mmcargs=setenv bootargs console=${console} " \
-		"root=${mmcroot} " \
-		"rootfstype=${mmcrootfstype}\0" \
-	"ubiargs=setenv bootargs console=${console} " \
-		"root=${ubiroot} " \
-		"rootfstype=${ubirootfstype}\0" \
-	"bootenv=uEnv.txt\0" \
-	"loadbootenv=load mmc ${mmcdev} ${loadaddr} ${bootenv}\0" \
-	"importbootenv=echo Importing environment from mmc ...; " \
-		"env import -t ${loadaddr} ${filesize}\0" \
-	"mmcload=load mmc ${mmcdev}:2 ${loadaddr} ${bootdir}/${bootfile}; " \
-		"load mmc ${mmcdev}:2 ${dtbaddr} ${bootdir}/${dtbfile}\0" \
-	"ubiload=ubi part filesystem 2048; ubifsmount ubi0; " \
-		"ubifsload ${loadaddr} ${bootdir}/${bootfile}; " \
-		"ubifsload ${dtbaddr} ${bootdir}/${dtbfile} \0" \
-	"mmcboot=echo Booting from mmc ...; " \
-		"run mmcargs; " \
-		"bootz ${loadaddr} - ${dtbaddr}\0" \
-	"ubiboot=echo Booting from nand (ubifs) ...; " \
-		"run ubiargs; run ubiload; " \
-		"bootz ${loadaddr} - ${dtbaddr}\0" \
-
-#define CONFIG_BOOTCOMMAND \
-	"mmc dev ${mmcdev}; if mmc rescan; then " \
-		"echo SD/MMC found on device ${mmcdev};" \
-		"if run loadbootenv; then " \
-			"echo Loaded environment from ${bootenv};" \
-			"run importbootenv;" \
-		"fi;" \
-		"if test -n $uenvcmd; then " \
-			"echo Running uenvcmd ...;" \
-			"run uenvcmd;" \
-		"fi;" \
-		"if run mmcload; then " \
-			"run mmcboot;" \
-		"fi;" \
-	"else " \
-		"run ubiboot;" \
-	"fi;" \
-
-/* Max number of command args */
-#define CONFIG_SYS_MAXARGS		16
-
-/* Console I/O Buffer Size */
-#define CONFIG_SYS_CBSIZE		512
-
-/* Print Buffer Size */
-#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE \
-					+ sizeof(CONFIG_SYS_PROMPT) + 16)
-
-/* Boot Argument Buffer Size */
-#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE
-#define CONFIG_SYS_LOAD_ADDR		0x81000000 /* Default load address */
-
-/* Physical Memory Map */
-#define CONFIG_NR_DRAM_BANKS		1		/*  1 bank of DRAM */
-#define CONFIG_MAX_RAM_BANK_SIZE	(1024 << 20)	/* 1GB */
-
-#define CONFIG_SYS_SDRAM_BASE		0x80000000
-#define CONFIG_SYS_INIT_SP_ADDR         (NON_SECURE_SRAM_END - \
-						GENERATED_GBL_DATA_SIZE)
-/* Platform/Board specific defs */
-#define CONFIG_SYS_TIMERBASE		0x48040000	/* Use Timer2 */
-#define CONFIG_SYS_PTV			2	/* Divisor: 2^(PTV+1) => 8 */
-#define CONFIG_SYS_HZ			1000	/* 1ms clock */
-
-/* NS16550 Configuration */
-#define CONFIG_SYS_NS16550
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE	(-4)
-#define CONFIG_SYS_NS16550_CLK		(48000000)
-#define CONFIG_SYS_NS16550_COM1		0x44e09000	/* UART0 */
-
-#define CONFIG_CONS_INDEX		1
-#define CONFIG_BAUDRATE			115200
-
-/* CPU */
-#define CONFIG_ARCH_CPU_INIT
-
-#define CONFIG_ENV_OVERWRITE		1
-#define CONFIG_SYS_CONSOLE_INFO_QUIET
-
-/* MMC support */
-#define CONFIG_MMC
-#define CONFIG_GENERIC_MMC
-#define CONFIG_OMAP_HSMMC
-#define CONFIG_DOS_PARTITION
-
-/* GPIO support */
-#define CONFIG_OMAP_GPIO
-
-/* Ethernet support */
-#define CONFIG_DRIVER_TI_CPSW
-#define CONFIG_MII
-#define CONFIG_BOOTP_DNS
-#define CONFIG_BOOTP_DNS2
-#define CONFIG_BOOTP_SEND_HOSTNAME
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_SUBNETMASK
-#define CONFIG_NET_RETRY_COUNT         10
-#define CONFIG_NET_MULTI
-#define CONFIG_PHYLIB
-#define CONFIG_PHY_ADDR			0
-#define CONFIG_PHY_SMSC
-
-/* NAND support */
-#define CONFIG_NAND
-#define CONFIG_NAND_OMAP_GPMC
-#define GPMC_NAND_ECC_LP_x16_LAYOUT	1
-#define CONFIG_SYS_NAND_BASE		(0x08000000)	/* phys address CS0 */
-#define CONFIG_SYS_MAX_NAND_DEVICE	1
-#define CONFIG_SYS_NAND_ONFI_DETECTION	1
-#define CONFIG_SYS_ENV_SECT_SIZE	(128 << 10)	/* 128 KiB */
-#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
-#define CONFIG_ENV_IS_IN_NAND
-#define CONFIG_ENV_OFFSET		0x180000 /* environment starts here */
-#define CONFIG_ENV_ADDR_REDUND		(CONFIG_ENV_OFFSET + CONFIG_SYS_ENV_SECT_SIZE)
-#define CONFIG_ENV_SIZE_REDUND		(CONFIG_ENV_SIZE)
-
-#define CONFIG_MTD_PARTITIONS
-#define CONFIG_MTD_DEVICE
-#define CONFIG_RBTREE
-#define CONFIG_LZO
-
-#define MTDIDS_DEFAULT			"nand0=omap2-nand.0"
-#define MTDPARTS_DEFAULT		"mtdparts=omap2-nand.0:512k(spl),"\
-					"1m(uboot),256k(environment),"\
-					"-(filesystem)"
-
-/* Unsupported features */
-#undef CONFIG_USE_IRQ
-
-/* Defines for SPL */
-#define CONFIG_SPL
-#define CONFIG_SPL_FRAMEWORK
-/*
- * Place the image at the start of the ROM defined image space.
- * We limit our size to the ROM-defined downloaded image area, and use the
- * rest of the space for stack.
- */
-#define CONFIG_SPL_TEXT_BASE		0x402F0400
-#define CONFIG_SPL_MAX_SIZE		(0x4030C000 - CONFIG_SPL_TEXT_BASE)
-#define CONFIG_SPL_STACK		CONFIG_SYS_INIT_SP_ADDR
-
-#define CONFIG_SPL_BSS_START_ADDR	0x80000000
-#define CONFIG_SPL_BSS_MAX_SIZE		0x80000		/* 512 KB */
-
-#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR	0x300 /* address 0x60000 */
-#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS	0x200 /* 256 KB */
-#define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION	1
-#define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME	"u-boot.img"
-#define CONFIG_SPL_MMC_SUPPORT
-#define CONFIG_SPL_FAT_SUPPORT
-#define CONFIG_SPL_LIBCOMMON_SUPPORT
-#define CONFIG_SPL_LIBDISK_SUPPORT
-#define CONFIG_SPL_LIBGENERIC_SUPPORT
-#define CONFIG_SPL_SERIAL_SUPPORT
-#define CONFIG_SPL_GPIO_SUPPORT
-#define CONFIG_SPL_YMODEM_SUPPORT
-#define CONFIG_SPL_LDSCRIPT		"$(CPUDIR)/am33xx/u-boot-spl.lds"
-
-#define CONFIG_SPL_BOARD_INIT
-#define CONFIG_SPL_NAND_AM33XX_BCH
-#define CONFIG_SPL_NAND_SUPPORT
-#define CONFIG_SPL_NAND_BASE
-#define CONFIG_SPL_NAND_DRIVERS
-#define CONFIG_SPL_NAND_ECC
-#define CONFIG_SYS_NAND_5_ADDR_CYCLE
-#define CONFIG_SYS_NAND_PAGE_COUNT	(CONFIG_SYS_NAND_BLOCK_SIZE / \
-					 CONFIG_SYS_NAND_PAGE_SIZE)
-#define CONFIG_SYS_NAND_PAGE_SIZE	2048
-#define CONFIG_SYS_NAND_OOBSIZE		64
-#define CONFIG_SYS_NAND_BLOCK_SIZE	(128*1024)
-#define CONFIG_SYS_NAND_BAD_BLOCK_POS	NAND_LARGE_BADBLOCK_POS
-#define CONFIG_SYS_NAND_ECCPOS		{ 2, 3, 4, 5, 6, 7, 8, 9, \
-					 10, 11, 12, 13, 14, 15, 16, 17, \
-					 18, 19, 20, 21, 22, 23, 24, 25, \
-					 26, 27, 28, 29, 30, 31, 32, 33, \
-					 34, 35, 36, 37, 38, 39, 40, 41, \
-					 42, 43, 44, 45, 46, 47, 48, 49, \
-					 50, 51, 52, 53, 54, 55, 56, 57, }
-
-#define CONFIG_SYS_NAND_ECCSIZE		512
-#define CONFIG_SYS_NAND_ECCBYTES	14
-
-#define	CONFIG_SYS_NAND_U_BOOT_START	CONFIG_SYS_TEXT_BASE
-
-#define CONFIG_SYS_NAND_U_BOOT_OFFS	0x80000
-
-/*
- * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM
- * 64 bytes before this address should be set aside for u-boot.img's
- * header. That is 0x800FFFC0--0x80100000 should not be used for any
- * other needs.
- */
-#define CONFIG_SYS_TEXT_BASE		0x80800000
-#define CONFIG_SYS_SPL_MALLOC_START	0x80208000
-#define CONFIG_SYS_SPL_MALLOC_SIZE	0x100000
-
-/*
- * Since SPL did pll and ddr initialization for us,
- * we don't need to do it twice.
- */
-#ifndef CONFIG_SPL_BUILD
-#define CONFIG_SKIP_LOWLEVEL_INIT
-#endif
-
-#endif	/* ! __CONFIG_IGEP0033_H */
diff --git a/include/configs/igep00x0.h b/include/configs/igep00x0.h
deleted file mode 100644
index e92bb68484..0000000000
--- a/include/configs/igep00x0.h
+++ /dev/null
@@ -1,370 +0,0 @@
-/*
- * Common configuration settings for IGEP technology based boards
- *
- * (C) Copyright 2012
- * ISEE 2007 SL, <www.iseebcn.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef __IGEP00X0_H
-#define __IGEP00X0_H
-
-#include <asm/sizes.h>
-
-/*
- * High Level Configuration Options
- */
-#define CONFIG_OMAP		1	/* in a TI OMAP core */
-#define CONFIG_OMAP34XX		1	/* which is a 34XX */
-#define CONFIG_OMAP_GPIO
-#define CONFIG_OMAP_COMMON
-
-#define CONFIG_SDRC	/* The chip has SDRC controller */
-
-#include <asm/arch/cpu.h>
-#include <asm/arch/omap3.h>
-#include <asm/mach-types.h>
-
-/*
- * Display CPU and Board information
- */
-#define CONFIG_DISPLAY_CPUINFO		1
-#define CONFIG_DISPLAY_BOARDINFO	1
-
-/* Clock Defines */
-#define V_OSCK			26000000	/* Clock output from T2 */
-#define V_SCLK			(V_OSCK >> 1)
-
-#define CONFIG_MISC_INIT_R
-
-#define CONFIG_CMDLINE_TAG		1	/* enable passing of ATAGs */
-#define CONFIG_SETUP_MEMORY_TAGS	1
-#define CONFIG_INITRD_TAG		1
-#define CONFIG_REVISION_TAG		1
-
-#define CONFIG_OF_LIBFDT
-#define CONFIG_CMD_BOOTZ
-#define CONFIG_SUPPORT_RAW_INITRD
-
-/*
- * NS16550 Configuration
- */
-
-#define V_NS16550_CLK			48000000	/* 48MHz (APLL96/2) */
-
-#define CONFIG_SYS_NS16550
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE	(-4)
-#define CONFIG_SYS_NS16550_CLK		V_NS16550_CLK
-
-/* select serial console configuration */
-#define CONFIG_CONS_INDEX		3
-#define CONFIG_SYS_NS16550_COM3		OMAP34XX_UART3
-#define CONFIG_SERIAL3			3
-
-/* allow to overwrite serial and ethaddr */
-#define CONFIG_ENV_OVERWRITE
-#define CONFIG_BAUDRATE			115200
-#define CONFIG_SYS_BAUDRATE_TABLE	{4800, 9600, 19200, 38400, 57600, \
-					115200}
-#define CONFIG_GENERIC_MMC		1
-#define CONFIG_MMC			1
-#define CONFIG_OMAP_HSMMC		1
-#define CONFIG_DOS_PARTITION		1
-
-/* define to enable boot progress via leds */
-#if (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0020) || \
-    (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0030)
-#define CONFIG_SHOW_BOOT_PROGRESS
-#endif
-
-/* USB */
-#define CONFIG_MUSB_UDC			1
-#define CONFIG_USB_OMAP3		1
-#define CONFIG_TWL4030_USB		1
-
-/* USB device configuration */
-#define CONFIG_USB_DEVICE		1
-#define CONFIG_USB_TTY			1
-#define CONFIG_SYS_CONSOLE_IS_IN_ENV	1
-
-/* Change these to suit your needs */
-#define CONFIG_USBD_VENDORID		0x0451
-#define CONFIG_USBD_PRODUCTID		0x5678
-#define CONFIG_USBD_MANUFACTURER	"Texas Instruments"
-#define CONFIG_USBD_PRODUCT_NAME	"IGEP"
-
-/* commands to include */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_CACHE
-#define CONFIG_CMD_EXT4
-#define CONFIG_CMD_FAT		/* FAT support			*/
-#define CONFIG_CMD_FS_GENERIC
-#define CONFIG_CMD_I2C		/* I2C serial bus support	*/
-#define CONFIG_CMD_MMC		/* MMC support			*/
-#ifdef CONFIG_BOOT_ONENAND
-#define CONFIG_CMD_ONENAND	/* ONENAND support		*/
-#endif
-#ifdef CONFIG_BOOT_NAND
-#define CONFIG_CMD_NAND
-#endif
-#if (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0020) || \
-    (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0032)
-#define CONFIG_CMD_NET		/* bootp, tftpboot, rarpboot	*/
-#endif
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_NFS		/* NFS support			*/
-#define CONFIG_CMD_MTDPARTS	/* Enable MTD parts commands	*/
-#define CONFIG_MTD_DEVICE
-
-#undef CONFIG_CMD_FLASH		/* flinfo, erase, protect	*/
-#undef CONFIG_CMD_IMLS		/* List all found images	*/
-
-#define CONFIG_SYS_NO_FLASH
-#define CONFIG_HARD_I2C			1
-#define CONFIG_SYS_I2C_SPEED		100000
-#define CONFIG_SYS_I2C_SLAVE		1
-#define CONFIG_DRIVER_OMAP34XX_I2C	1
-
-/*
- * TWL4030
- */
-#define CONFIG_TWL4030_POWER		1
-
-#define CONFIG_BOOTDELAY		3
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
-	"usbtty=cdc_acm\0" \
-	"loadaddr=0x82000000\0" \
-	"dtbaddr=0x81600000\0" \
-	"bootdir=/boot\0" \
-	"bootfile=zImage\0" \
-	"usbtty=cdc_acm\0" \
-	"console=ttyO2,115200n8\0" \
-	"mpurate=auto\0" \
-	"vram=12M\0" \
-	"dvimode=1024x768MR-16@60\0" \
-	"defaultdisplay=dvi\0" \
-	"mmcdev=0\0" \
-	"mmcroot=/dev/mmcblk0p2 rw\0" \
-	"mmcrootfstype=ext4 rootwait\0" \
-	"nandroot=/dev/mtdblock4 rw\0" \
-	"nandrootfstype=jffs2\0" \
-	"mmcargs=setenv bootargs console=${console} " \
-		"mpurate=${mpurate} " \
-		"vram=${vram} " \
-		"omapfb.mode=dvi:${dvimode} " \
-		"omapfb.debug=y " \
-		"omapdss.def_disp=${defaultdisplay} " \
-		"root=${mmcroot} " \
-		"rootfstype=${mmcrootfstype}\0" \
-	"nandargs=setenv bootargs console=${console} " \
-		"mpurate=${mpurate} " \
-		"vram=${vram} " \
-		"omapfb.mode=dvi:${dvimode} " \
-		"omapfb.debug=y " \
-		"omapdss.def_disp=${defaultdisplay} " \
-		"root=${nandroot} " \
-		"rootfstype=${nandrootfstype}\0" \
-	"loadbootenv=load mmc ${mmcdev} ${loadaddr} uEnv.txt\0" \
-	"importbootenv=echo Importing environment from mmc ...; " \
-		"env import -t $loadaddr $filesize\0" \
-	"loadzimage=load mmc ${mmcdev}:2 ${loadaddr} ${bootdir}/${bootfile}\0" \
-	"loadfdt=load mmc ${mmcdev}:2 ${dtbaddr} ${bootdir}/${dtbfile}\0" \
-	"mmcboot=echo Booting from mmc ...; " \
-		"run mmcargs; " \
-		"bootz ${loadaddr}\0" \
-	"mmcbootfdt=echo Booting with DT from mmc ...; " \
-		"bootz ${loadaddr} - ${dtbaddr}\0" \
-	"nandboot=echo Booting from onenand ...; " \
-		"run nandargs; " \
-		"onenand read ${loadaddr} 280000 400000; " \
-		"bootz ${loadaddr}\0" \
-
-#define CONFIG_BOOTCOMMAND \
-	"mmc dev ${mmcdev}; if mmc rescan; then " \
-		"echo SD/MMC found on device ${mmcdev};" \
-		"if run loadbootenv; then " \
-			"run importbootenv;" \
-		"fi;" \
-		"if test -n $uenvcmd; then " \
-			"echo Running uenvcmd ...;" \
-			"run uenvcmd;" \
-		"fi;" \
-		"if run loadzimage; then " \
-			"if test -n $dtbfile; then " \
-				"if run loadfdt; then " \
-					"run mmcbootfdt;" \
-				"fi;" \
-			"fi;" \
-			"run mmcboot;" \
-		"fi;" \
-	"fi;" \
-	"run nandboot;" \
-
-#define CONFIG_AUTO_COMPLETE		1
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP		/* undef to save memory */
-#define CONFIG_SYS_HUSH_PARSER		/* use "hush" command parser */
-#define CONFIG_SYS_PROMPT		"U-Boot # "
-#define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size */
-/* Print Buffer Size */
-#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
-					sizeof(CONFIG_SYS_PROMPT) + 16)
-#define CONFIG_SYS_MAXARGS		16	/* max number of command args */
-/* Boot Argument Buffer Size */
-#define CONFIG_SYS_BARGSIZE		(CONFIG_SYS_CBSIZE)
-
-#define CONFIG_SYS_MEMTEST_START	(OMAP34XX_SDRC_CS0)	/* memtest */
-								/* works on */
-#define CONFIG_SYS_MEMTEST_END		(OMAP34XX_SDRC_CS0 + \
-					0x01F00000) /* 31MB */
-
-#define CONFIG_SYS_LOAD_ADDR		(OMAP34XX_SDRC_CS0)	/* default */
-							/* load address */
-
-#define CONFIG_SYS_MONITOR_LEN		(256 << 10)
-
-/*
- * OMAP3 has 12 GP timers, they can be driven by the system clock
- * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
- * This rate is divided by a local divisor.
- */
-#define CONFIG_SYS_TIMERBASE		(OMAP34XX_GPT2)
-#define CONFIG_SYS_PTV			2       /* Divisor: 2^(PTV+1) => 8 */
-#define CONFIG_SYS_HZ			1000
-
-/*
- * Physical Memory Map
- *
- */
-#define CONFIG_NR_DRAM_BANKS	2	/* CS1 may or may not be populated */
-#define PHYS_SDRAM_1		OMAP34XX_SDRC_CS0
-#define PHYS_SDRAM_2		OMAP34XX_SDRC_CS1
-
-/*
- * FLASH and environment organization
- */
-
-#ifdef CONFIG_BOOT_ONENAND
-#define PISMO1_ONEN_SIZE		GPMC_SIZE_128M /* Configure the PISMO */
-
-#define CONFIG_SYS_ONENAND_BASE		ONENAND_MAP
-
-#define ONENAND_ENV_OFFSET		0x260000 /* environment starts here */
-
-#define CONFIG_ENV_IS_IN_ONENAND	1
-#define CONFIG_ENV_SIZE			(512 << 10) /* Total Size Environment */
-#define CONFIG_ENV_ADDR			ONENAND_ENV_OFFSET
-#endif
-
-#ifdef CONFIG_BOOT_NAND
-#define PISMO1_NAND_SIZE		GPMC_SIZE_128M /* Configure the PISMO */
-#define CONFIG_NAND_OMAP_GPMC
-#define CONFIG_SYS_NAND_BASE		NAND_BASE
-#define GPMC_NAND_ECC_LP_x16_LAYOUT	1
-#define CONFIG_ENV_OFFSET		0x260000 /* environment starts here */
-#define CONFIG_ENV_IS_IN_NAND	        1
-#define CONFIG_ENV_SIZE			(512 << 10) /* Total Size Environment */
-#define CONFIG_ENV_ADDR			NAND_ENV_OFFSET
-#define CONFIG_SYS_MAX_NAND_DEVICE      1
-#endif
-
-/*
- * Size of malloc() pool
- */
-#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + (128 << 10))
-
-/*
- * SMSC911x Ethernet
- */
-#if defined(CONFIG_CMD_NET)
-#define CONFIG_SMC911X
-#define CONFIG_SMC911X_32_BIT
-#define CONFIG_SMC911X_BASE	0x2C000000
-#endif /* (CONFIG_CMD_NET) */
-
-/*
- * Leave it at 0x80008000 to allow booting new u-boot.bin with X-loader
- * and older u-boot.bin with the new U-Boot SPL.
- */
-#define CONFIG_SYS_TEXT_BASE		0x80008000
-#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
-#define CONFIG_SYS_INIT_RAM_ADDR	0x4020f800
-#define CONFIG_SYS_INIT_RAM_SIZE	0x800
-#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_INIT_RAM_ADDR + \
-					 CONFIG_SYS_INIT_RAM_SIZE - \
-					 GENERATED_GBL_DATA_SIZE)
-
-/* SPL */
-#define CONFIG_SPL
-#define CONFIG_SPL_FRAMEWORK
-#define CONFIG_SPL_NAND_SIMPLE
-#define CONFIG_SPL_TEXT_BASE		0x40200800
-#define CONFIG_SPL_MAX_SIZE		(54 * 1024)
-#define CONFIG_SPL_STACK		LOW_LEVEL_SRAM_STACK
-
-/* move malloc and bss high to prevent clashing with the main image */
-#define CONFIG_SYS_SPL_MALLOC_START	0x87000000
-#define CONFIG_SYS_SPL_MALLOC_SIZE	0x80000
-#define CONFIG_SPL_BSS_START_ADDR	0x87080000	/* end of minimum RAM */
-#define CONFIG_SPL_BSS_MAX_SIZE		0x80000		/* 512 KB */
-
-/* MMC boot config */
-#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR	0x300 /* address 0x60000 */
-#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS	0x200 /* 256 KB */
-#define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION	1
-#define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME	"u-boot.img"
-
-#define CONFIG_SPL_BOARD_INIT
-#define CONFIG_SPL_LIBCOMMON_SUPPORT
-#define CONFIG_SPL_LIBDISK_SUPPORT
-#define CONFIG_SPL_I2C_SUPPORT
-#define CONFIG_SPL_LIBGENERIC_SUPPORT
-#define CONFIG_SPL_MMC_SUPPORT
-#define CONFIG_SPL_FAT_SUPPORT
-#define CONFIG_SPL_SERIAL_SUPPORT
-
-#define CONFIG_SPL_POWER_SUPPORT
-#define CONFIG_SPL_LDSCRIPT		"$(CPUDIR)/omap-common/u-boot-spl.lds"
-
-#ifdef CONFIG_BOOT_ONENAND
-#define CONFIG_SPL_ONENAND_SUPPORT
-
-/* OneNAND boot config */
-#define CONFIG_SYS_ONENAND_U_BOOT_OFFS  0x80000
-#define CONFIG_SYS_ONENAND_PAGE_SIZE	2048
-#define CONFIG_SPL_ONENAND_LOAD_ADDR    0x80000
-#define CONFIG_SPL_ONENAND_LOAD_SIZE    \
-	(512 * 1024 - CONFIG_SPL_ONENAND_LOAD_ADDR)
-
-#endif
-
-#ifdef CONFIG_BOOT_NAND
-#define CONFIG_SPL_NAND_SUPPORT
-#define CONFIG_SPL_NAND_BASE
-#define CONFIG_SPL_NAND_DRIVERS
-#define CONFIG_SPL_NAND_ECC
-
-/* NAND boot config */
-#define CONFIG_SYS_NAND_5_ADDR_CYCLE
-#define CONFIG_SYS_NAND_PAGE_COUNT	64
-#define CONFIG_SYS_NAND_PAGE_SIZE	2048
-#define CONFIG_SYS_NAND_OOBSIZE		64
-#define CONFIG_SYS_NAND_BLOCK_SIZE	(128*1024)
-#define CONFIG_SYS_NAND_BAD_BLOCK_POS	0
-#define CONFIG_SYS_NAND_ECCPOS		{2, 3, 4, 5, 6, 7, 8, 9,\
-						10, 11, 12, 13}
-#define CONFIG_SYS_NAND_ECCSIZE		512
-#define CONFIG_SYS_NAND_ECCBYTES	3
-#define CONFIG_SYS_NAND_U_BOOT_START	CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_NAND_U_BOOT_OFFS	0x80000
-#endif
-
-#endif /* __IGEP00X0_H */
diff --git a/include/configs/ima3-mx53.h b/include/configs/ima3-mx53.h
index ae6828bd78..ad1614abbb 100644
--- a/include/configs/ima3-mx53.h
+++ b/include/configs/ima3-mx53.h
@@ -111,7 +111,6 @@
 
 #define CONFIG_SYS_LOAD_ADDR		CONFIG_LOADADDR
 
-#define CONFIG_SYS_HZ		1000
 #define CONFIG_CMDLINE_EDITING
 
 /* Physical Memory Map */
diff --git a/include/configs/imx27lite-common.h b/include/configs/imx27lite-common.h
index c6b852969b..9c25efe851 100644
--- a/include/configs/imx27lite-common.h
+++ b/include/configs/imx27lite-common.h
@@ -16,7 +16,6 @@
 #define CONFIG_ARM926EJS			/* arm926ejs CPU core */
 #define CONFIG_MX27
 #define CONFIG_MX27_CLK32	32768		/* OSC32K frequency */
-#define CONFIG_SYS_HZ		1000
 
 #define CONFIG_DISPLAY_BOARDINFO
 #define CONFIG_DISPLAY_CPUINFO
@@ -160,7 +159,6 @@
 /*
  * U-Boot general configuration
  */
-#define CONFIG_SYS_PROMPT	"=> "	/* Monitor Command Prompt */
 #define CONFIG_SYS_CBSIZE	1024	/* Console I/O Buffer Size  */
 /* Print buffer sz */
 #define CONFIG_SYS_PBSIZE	(CONFIG_SYS_CBSIZE + \
diff --git a/include/configs/imx31_litekit.h b/include/configs/imx31_litekit.h
index 0d0715869d..8428d84496 100644
--- a/include/configs/imx31_litekit.h
+++ b/include/configs/imx31_litekit.h
@@ -117,8 +117,6 @@
 
 #define CONFIG_SYS_LOAD_ADDR		0 /* default load address */
 
-#define CONFIG_SYS_HZ			1000
-
 #define CONFIG_CMDLINE_EDITING	1
 
 /*-----------------------------------------------------------------------
diff --git a/include/configs/imx31_phycore.h b/include/configs/imx31_phycore.h
index 1e2b12cb25..ffb67c2ebe 100644
--- a/include/configs/imx31_phycore.h
+++ b/include/configs/imx31_phycore.h
@@ -35,11 +35,9 @@
  * Hardware drivers
  */
 
-#define CONFIG_HARD_I2C
-#define CONFIG_I2C_MXC
-#define CONFIG_SYS_I2C_BASE		I2C2_BASE_ADDR
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_MXC
 #define CONFIG_SYS_I2C_CLK_OFFSET	I2C2_CLK_OFFSET
-#define CONFIG_SYS_I2C_SPEED		100000
 
 #define CONFIG_MXC_UART
 #define CONFIG_MXC_UART_BASE		UART1_BASE
@@ -121,8 +119,6 @@
 
 #define CONFIG_SYS_LOAD_ADDR		0 /* default load address */
 
-#define CONFIG_SYS_HZ			1000
-
 #define CONFIG_CMDLINE_EDITING
 
 /*
diff --git a/include/configs/incaip.h b/include/configs/incaip.h
index 0ff9a7ff82..e11d1843b9 100644
--- a/include/configs/incaip.h
+++ b/include/configs/incaip.h
@@ -12,7 +12,6 @@
 #ifndef __CONFIG_H
 #define __CONFIG_H
 
-#define CONFIG_MIPS32		1	/* MIPS 4Kc CPU core	*/
 #define CONFIG_INCA_IP		1	/* on a INCA-IP Board	*/
 
 #define CONFIG_XWAY_SWAP_BYTES
@@ -106,8 +105,6 @@
 
 #define CONFIG_SYS_MIPS_TIMER_FREQ	(incaip_get_cpuclk() / 2)
 
-#define CONFIG_SYS_HZ			1000
-
 #define CONFIG_SYS_SDRAM_BASE		0x80000000
 
 #define	CONFIG_SYS_LOAD_ADDR		0x80100000	/* default load address	*/
diff --git a/include/configs/inka4x0.h b/include/configs/inka4x0.h
index 6242a94172..f321975c47 100644
--- a/include/configs/inka4x0.h
+++ b/include/configs/inka4x0.h
@@ -16,9 +16,8 @@
  * (easy to change)
  */
 
-#define CONFIG_MPC5xxx		1	/* This is an MPC5xxx CPU		*/
-#define CONFIG_MPC5200		1	/* (more precisely an MPC5200 CPU)	*/
-#define CONFIG_INKA4X0		1	/* INKA4x0 board			*/
+#define CONFIG_MPC5200		1	/* This is an MPC5200 CPU	*/
+#define CONFIG_INKA4X0		1	/* INKA4x0 board		*/
 
 /*
  * Valid values for CONFIG_SYS_TEXT_BASE are:
@@ -325,7 +324,6 @@ static inline void tws_data_config_output(unsigned output)
  * Miscellaneous configurable options
  */
 #define CONFIG_SYS_LONGHELP			/* undef to save memory	    */
-#define CONFIG_SYS_PROMPT		"=> "	/* Monitor Command Prompt   */
 #if defined(CONFIG_CMD_KGDB)
 #define CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size  */
 #else
@@ -348,8 +346,6 @@ static inline void tws_data_config_output(unsigned output)
 
 #define CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address */
 
-#define CONFIG_SYS_HZ			1000	/* decrementer freq: 1 ms ticks */
-
 /*
  * Enable loopw command.
  */
diff --git a/include/configs/integrator-common.h b/include/configs/integrator-common.h
index 94cdfd29da..267a92b2d0 100644
--- a/include/configs/integrator-common.h
+++ b/include/configs/integrator-common.h
@@ -12,7 +12,6 @@
 #define CONFIG_SYS_TEXT_BASE		0x01000000
 #define CONFIG_SYS_MEMTEST_START	0x100000
 #define CONFIG_SYS_MEMTEST_END		0x10000000
-#define CONFIG_SYS_HZ			1000
 #define CONFIG_SYS_TIMERBASE		0x13000100	/* Timer1 */
 #define CONFIG_SYS_LOAD_ADDR		0x7fc0	/* default load address */
 #define CONFIG_SYS_LONGHELP
diff --git a/include/configs/intip.h b/include/configs/intip.h
index d3d7a441b6..b56b3aa340 100644
--- a/include/configs/intip.h
+++ b/include/configs/intip.h
@@ -30,7 +30,6 @@
 #define CONFIG_IDENT_STRING	" intip 0.06"
 #endif
 #define CONFIG_440		1
-#define CONFIG_4xx		1	/* ... PPC4xx family */
 
 #ifndef CONFIG_SYS_TEXT_BASE
 #define CONFIG_SYS_TEXT_BASE	0xFFFA0000
diff --git a/include/configs/io.h b/include/configs/io.h
index 2d67cfc66a..9da6cc6855 100644
--- a/include/configs/io.h
+++ b/include/configs/io.h
@@ -9,7 +9,6 @@
 #define __CONFIG_H
 
 #define CONFIG_405EP		1	/* this is a PPC405 CPU */
-#define CONFIG_4xx		1	/*  member of PPC4xx family */
 #define CONFIG_IO	        1	/*  on a Io board */
 
 #define	CONFIG_SYS_TEXT_BASE	0xFFFC0000
@@ -199,9 +198,8 @@
 #define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_OCM_DATA_ADDR /* in SDRAM */
 #define CONFIG_SYS_INIT_RAM_END	CONFIG_SYS_OCM_DATA_SIZE /* End of used area */
 
-#define CONFIG_SYS_GBL_DATA_SIZE	128  /* size/bytes res'd for init data*/
 #define CONFIG_SYS_GBL_DATA_OFFSET \
-	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+	(CONFIG_SYS_INIT_RAM_END - GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 /*
diff --git a/include/configs/io64.h b/include/configs/io64.h
index 39ed2850d2..6915b2071c 100644
--- a/include/configs/io64.h
+++ b/include/configs/io64.h
@@ -20,7 +20,6 @@
  * High Level Configuration Options
  *----------------------------------------------------------------------*/
 #define CONFIG_IO64		1		/* Board is Io64 */
-#define CONFIG_4xx		1		/* ... PPC4xx family */
 #define CONFIG_405EX		1		/* Specifc 405EX support*/
 #define CONFIG_SYS_CLK_FREQ	33333333	/* ext frequency to pll */
 
diff --git a/include/configs/iocon.h b/include/configs/iocon.h
index 788c715a2f..f36c2a3504 100644
--- a/include/configs/iocon.h
+++ b/include/configs/iocon.h
@@ -9,7 +9,6 @@
 #define __CONFIG_H
 
 #define CONFIG_405EP		1	/* this is a PPC405 CPU */
-#define CONFIG_4xx		1	/*  member of PPC4xx family */
 #define CONFIG_IOCON		1	/*  on a IoCon board */
 
 #define	CONFIG_SYS_TEXT_BASE	0xFFFC0000
@@ -239,9 +238,8 @@ int fpga_gpio_get(unsigned int bus, int pin);
 #define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_OCM_DATA_ADDR /* in SDRAM */
 #define CONFIG_SYS_INIT_RAM_END	CONFIG_SYS_OCM_DATA_SIZE /* End of used area */
 
-#define CONFIG_SYS_GBL_DATA_SIZE	128  /* size/bytes res'd for init data*/
 #define CONFIG_SYS_GBL_DATA_OFFSET \
-	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+	(CONFIG_SYS_INIT_RAM_END - GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 /*
diff --git a/include/configs/ip04.h b/include/configs/ip04.h
index d36ae43664..0efa2b7b9f 100644
--- a/include/configs/ip04.h
+++ b/include/configs/ip04.h
@@ -132,6 +132,7 @@
 #define CONFIG_BAUDRATE		115200
 #define CONFIG_MISC_INIT_R	/* needed for MAC address */
 #define CONFIG_UART_CONSOLE	0
+#define CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED
 
 #undef CONFIG_SHOW_BOOT_PROGRESS
 /* Enable this if bootretry required; currently it's disabled */
diff --git a/include/configs/ipam390.h b/include/configs/ipam390.h
index 82d4298007..fdd5680741 100644
--- a/include/configs/ipam390.h
+++ b/include/configs/ipam390.h
@@ -33,7 +33,6 @@
 #define CONFIG_SYS_OSCIN_FREQ		24000000
 #define CONFIG_SYS_TIMERBASE		DAVINCI_TIMER0_BASE
 #define CONFIG_SYS_HZ_CLOCK		clk_get(DAVINCI_AUXCLK_CLKID)
-#define CONFIG_SYS_HZ			1000
 #define CONFIG_SYS_DA850_PLL_INIT
 #define CONFIG_SYS_DA850_DDR_INIT
 #define CONFIG_SYS_TEXT_BASE		0xc1080000
@@ -122,13 +121,13 @@
 	(3 << DV_DDR_SDCR_IBANK_SHIFT) |	\
 	(2 << DV_DDR_SDCR_PAGESIZE_SHIFT))
 
-#define CONFIG_SYS_DA850_CS3CFG	(DAVINCI_ABCR_WSETUP(2)	| \
+#define CONFIG_SYS_DA850_CS3CFG	(DAVINCI_ABCR_WSETUP(1)	| \
 				DAVINCI_ABCR_WSTROBE(2)	| \
-				DAVINCI_ABCR_WHOLD(1)	| \
+				DAVINCI_ABCR_WHOLD(0)	| \
 				DAVINCI_ABCR_RSETUP(1)	| \
-				DAVINCI_ABCR_RSTROBE(4)	| \
-				DAVINCI_ABCR_RHOLD(0)	| \
-				DAVINCI_ABCR_TA(1)	| \
+				DAVINCI_ABCR_RSTROBE(2)	| \
+				DAVINCI_ABCR_RHOLD(1)	| \
+				DAVINCI_ABCR_TA(0)	| \
 				DAVINCI_ABCR_ASIZE_8BIT)
 
 
@@ -161,6 +160,7 @@
 #undef CONFIG_SYS_NAND_HW_ECC
 #define CONFIG_SYS_MAX_NAND_DEVICE	1 /* Max number of NAND devices */
 #define CONFIG_SYS_NAND_HW_ECC_OOBFIRST
+#define CONFIG_NAND_6BYTES_OOB_FREE_10BYTES_ECC
 #define CONFIG_SYS_NAND_5_ADDR_CYCLE
 #define CONFIG_SYS_NAND_PAGE_SIZE	(2 << 10)
 #define CONFIG_SYS_NAND_BLOCK_SIZE	(128 << 10)
@@ -173,11 +173,10 @@
 					CONFIG_SYS_MALLOC_LEN -       \
 					GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_NAND_ECCPOS		{				\
-				24, 25, 26, 27, 28, \
-				29, 30, 31, 32, 33, 34, 35, 36, 37, 38, \
-				39, 40, 41, 42, 43, 44, 45, 46, 47, 48, \
-				49, 50, 51, 52, 53, 54, 55, 56, 57, 58, \
-				59, 60, 61, 62, 63 }
+			6,   7,  8,  9, 10,	11, 12, 13, 14, 15,	\
+			22, 23, 24, 25, 26,	27, 28, 29, 30, 31,	\
+			38, 39, 40, 41, 42,	43, 44, 45, 46, 47,	\
+			54, 55, 56, 57, 58,	59, 60, 61, 62, 63}
 #define CONFIG_SYS_NAND_PAGE_COUNT	64
 #define CONFIG_SYS_NAND_BAD_BLOCK_POS	0
 #define CONFIG_SYS_NAND_ECCSIZE		512
@@ -230,15 +229,24 @@
 #define CONFIG_CMDLINE_TAG
 #define CONFIG_REVISION_TAG
 #define CONFIG_SETUP_MEMORY_TAGS
-#define CONFIG_BOOTARGS		\
-	"mem=128M console=ttyS0,115200n8 root=/dev/mtdblock0p4 rw noinitrd ip=dhcp"
-#define CONFIG_BOOTDELAY	3
+#define CONFIG_BOOTDELAY	2
 #define CONFIG_EXTRA_ENV_SETTINGS \
+	"defbootargs=setenv bootargs mem=128M console=ttyS0,115200n8 " \
+		"root=/dev/mtdblock5 rw noinitrd " \
+		"rootfstype=jffs2 noinitrd\0" \
 	"hwconfig=dsp:wake=yes\0" \
+	"bootcmd=nboot kernel;run defbootargs addmtd;bootm 0xc0700000\0" \
+	"bootfile=uImage\0" \
 	"addmtd=setenv bootargs ${bootargs} ${mtdparts}\0"	\
+	"mtddevname=uboot-env\0" \
+	"mtddevnum=0\0" \
 	"mtdids=" MTDIDS_DEFAULT "\0"				\
 	"mtdparts=" MTDPARTS_DEFAULT "\0"			\
+	"u-boot=/tftpboot/ipam390/u-boot.ais\0"			\
+	"upd_uboot=tftp c0000000 ${u-boot};nand erase.part u-boot;" \
+		"nand write c0000000 20000 ${filesize}\0"	\
 	"setbootparms=nand read c0100000 200000 400000;"	\
+		"run defbootargs addmtd;"			\
 		"spl export atags c0100000;"			\
 		"nand erase.part bootparms;"			\
 		"nand write c0000100 180000 20000\0"		\
diff --git a/include/configs/ipek01.h b/include/configs/ipek01.h
index d2351cc53a..41ced15c48 100644
--- a/include/configs/ipek01.h
+++ b/include/configs/ipek01.h
@@ -16,9 +16,8 @@
  */
 
 #define CONFIG_MPC5200
-#define CONFIG_MPC5xxx		1	/* This is an MPC5xxx CPU */
-#define CONFIG_MPX5200		1	/* ... on MPX5200 board */
-#define CONFIG_MPC5200_DDR	1	/* ... use DDR RAM */
+#define CONFIG_MPX5200		1	/* MPX5200 board */
+#define CONFIG_MPC5200_DDR	1	/* use DDR RAM */
 #define CONFIG_IPEK01           	/* Motherboard is ipek01 */
 
 #define	CONFIG_SYS_TEXT_BASE	0xfc000000
@@ -278,7 +277,6 @@
  * Miscellaneous configurable options
  */
 #define CONFIG_SYS_LONGHELP			/* undef to save memory	*/
-#define CONFIG_SYS_PROMPT		"=> "	/* Monitor Command Prompt */
 #ifdef CONFIG_CMD_KGDB
 #define CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size */
 #else
@@ -297,7 +295,6 @@
 
 #define CONFIG_SYS_LOAD_ADDR		0x100000 /* default load address */
 
-#define CONFIG_SYS_HZ			1000 /* decrementer freq: 1 ms ticks */
 #define CONFIG_LOOPW
 
 /*
diff --git a/include/configs/jadecpu.h b/include/configs/jadecpu.h
index d0609f6250..b34e3422da 100644
--- a/include/configs/jadecpu.h
+++ b/include/configs/jadecpu.h
@@ -12,7 +12,6 @@
 
 #define CONFIG_MB86R0x
 #define CONFIG_MB86R0x_IOCLK	get_bus_freq(0)
-#define CONFIG_SYS_HZ		1000
 #define CONFIG_SYS_TEXT_BASE	0x10000000
 
 #define CONFIG_ARM926EJS	1	/* This is an ARM926EJS Core	*/
diff --git a/include/configs/jornada.h b/include/configs/jornada.h
index 71f1e72528..7e18d8e7b5 100644
--- a/include/configs/jornada.h
+++ b/include/configs/jornada.h
@@ -70,7 +70,6 @@
 #define CONFIG_SYS_BARGSIZE		256	/* Boot Argument Buffer Size */
 #define CONFIG_SYS_MEMTEST_START	0xc0040000	/* memtest works on */
 #define CONFIG_SYS_MEMTEST_END		0xc2000000	/* 4..128 MB */
-#define CONFIG_SYS_HZ			1000
 #define CONFIG_SYS_CPUSPEED		0x0a /* core clock 206MHz */
 #define CONFIG_SYS_BAUDRATE_TABLE	{ 19200, 38400, 57600, 115200 }
 
diff --git a/include/configs/jupiter.h b/include/configs/jupiter.h
index 01c087b0d3..7dfaa221ee 100644
--- a/include/configs/jupiter.h
+++ b/include/configs/jupiter.h
@@ -13,8 +13,7 @@
  * (easy to change)
  */
 
-#define CONFIG_MPC5xxx		1	/* This is an MPC5xxx CPU */
-#define CONFIG_MPC5200		1	/* especially an MPC5200 */
+#define CONFIG_MPC5200		1	/* This is an MPC5200 CPU */
 #define CONFIG_JUPITER		1	/* ... on Jupiter board */
 
 /*
@@ -243,7 +242,6 @@
  * Miscellaneous configurable options
  */
 #define CONFIG_SYS_LONGHELP			/* undef to save memory	    */
-#define CONFIG_SYS_PROMPT		"=> "	/* Monitor Command Prompt   */
 
 #define CONFIG_CMDLINE_EDITING	1	/* add command line history	*/
 #define CONFIG_SYS_HUSH_PARSER		1	/* Use the HUSH parser		*/
@@ -262,8 +260,6 @@
 
 #define CONFIG_SYS_LOAD_ADDR		0x200000	/* default load address */
 
-#define CONFIG_SYS_HZ			1000	/* decrementer freq: 1 ms ticks */
-
 #define CONFIG_SYS_CACHELINE_SIZE	32	/* For MPC5xxx CPUs */
 #if defined(CONFIG_CMD_KGDB)
 #  define CONFIG_SYS_CACHELINE_SHIFT	5	/* log base 2 of the above value */
diff --git a/include/configs/katmai.h b/include/configs/katmai.h
index ca0df2d0ce..fa72eb02f3 100644
--- a/include/configs/katmai.h
+++ b/include/configs/katmai.h
@@ -18,7 +18,6 @@
  * High Level Configuration Options
  *----------------------------------------------------------------------*/
 #define CONFIG_KATMAI			1	/* Board is Katmai	*/
-#define CONFIG_4xx			1	/* ... PPC4xx family	*/
 #define CONFIG_440			1	/* ... PPC440 family	*/
 #define CONFIG_440SPE			1	/* Specifc SPe support	*/
 #define CONFIG_440SPE_REVA		1	/* Support old Rev A.	*/
diff --git a/include/configs/kilauea.h b/include/configs/kilauea.h
index d2acc281cd..1990b2df15 100644
--- a/include/configs/kilauea.h
+++ b/include/configs/kilauea.h
@@ -19,7 +19,6 @@
  * High Level Configuration Options
  *----------------------------------------------------------------------*/
 #define CONFIG_KILAUEA		1		/* Board is Kilauea	*/
-#define CONFIG_4xx		1		/* ... PPC4xx family	*/
 #define CONFIG_405EX		1		/* Specifc 405EX support*/
 #define CONFIG_SYS_CLK_FREQ	33333333	/* ext frequency to pll	*/
 
@@ -119,12 +118,7 @@
 /*-----------------------------------------------------------------------
  * Environment
  *----------------------------------------------------------------------*/
-#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
 #define CONFIG_ENV_IS_IN_FLASH     1	/* use FLASH for environment vars	*/
-#else
-#define CONFIG_ENV_IS_IN_NAND	1	/* use NAND for environment vars	*/
-#define CONFIG_ENV_IS_EMBEDDED	1	/* use embedded environment */
-#endif
 
 /*-----------------------------------------------------------------------
  * FLASH related
@@ -152,61 +146,6 @@
 #define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SIZE)
 #endif /* CONFIG_ENV_IS_IN_FLASH */
 
-/*
- * IPL (Initial Program Loader, integrated inside CPU)
- * Will load first 4k from NAND (SPL) into cache and execute it from there.
- *
- * SPL (Secondary Program Loader)
- * Will load special U-Boot version (NUB) from NAND and execute it. This SPL
- * has to fit into 4kByte. It sets up the CPU and configures the SDRAM
- * controller and the NAND controller so that the special U-Boot image can be
- * loaded from NAND to SDRAM.
- *
- * NUB (NAND U-Boot)
- * This NAND U-Boot (NUB) is a special U-Boot version which can be started
- * from RAM. Therefore it mustn't (re-)configure the SDRAM controller.
- *
- * On 405EX the SPL is copied to SDRAM before the NAND controller is
- * set up. While still running from location 0xfffff000...0xffffffff the
- * NAND controller cannot be accessed since it is attached to CS0 too.
- */
-#define CONFIG_SYS_NAND_BOOT_SPL_SRC	0xfffff000	/* SPL location			*/
-#define CONFIG_SYS_NAND_BOOT_SPL_SIZE	(4 << 10)	/* SPL size			*/
-#define CONFIG_SYS_NAND_BOOT_SPL_DST	0x00800000	/* Copy SPL here		*/
-#define CONFIG_SYS_NAND_U_BOOT_DST	0x01000000	/* Load NUB to this addr	*/
-#define CONFIG_SYS_NAND_U_BOOT_START	CONFIG_SYS_NAND_U_BOOT_DST /* Start NUB from this addr	*/
-#define CONFIG_SYS_NAND_BOOT_SPL_DELTA	(CONFIG_SYS_NAND_BOOT_SPL_SRC - CONFIG_SYS_NAND_BOOT_SPL_DST)
-
-/*
- * Define the partitioning of the NAND chip (only RAM U-Boot is needed here)
- */
-#define CONFIG_SYS_NAND_U_BOOT_OFFS	(16 << 10)	/* Offset to RAM U-Boot image	*/
-#define CONFIG_SYS_NAND_U_BOOT_SIZE	(384 << 10)	/* Size of RAM U-Boot image	*/
-
-/*
- * Now the NAND chip has to be defined (no autodetection used!)
- */
-#define CONFIG_SYS_NAND_PAGE_SIZE	512		/* NAND chip page size		*/
-#define CONFIG_SYS_NAND_BLOCK_SIZE	(16 << 10)	/* NAND chip block size		*/
-#define CONFIG_SYS_NAND_PAGE_COUNT	32		/* NAND chip page count		*/
-#define CONFIG_SYS_NAND_BAD_BLOCK_POS	5		/* Location of bad block marker	*/
-#define CONFIG_SYS_NAND_4_ADDR_CYCLE	1		/* Fourth addr used (>32MB)	*/
-
-#define CONFIG_SYS_NAND_ECCSIZE	256
-#define CONFIG_SYS_NAND_ECCBYTES	3
-#define CONFIG_SYS_NAND_OOBSIZE	16
-#define CONFIG_SYS_NAND_ECCPOS		{0, 1, 2, 3, 6, 7}
-
-#ifdef CONFIG_ENV_IS_IN_NAND
-/*
- * For NAND booting the environment is embedded in the U-Boot image. Please take
- * look at the file board/amcc/sequoia/u-boot-nand.lds for details.
- */
-#define CONFIG_ENV_SIZE		CONFIG_SYS_NAND_BLOCK_SIZE
-#define CONFIG_ENV_OFFSET		(CONFIG_SYS_NAND_U_BOOT_OFFS + CONFIG_ENV_SIZE)
-#define CONFIG_ENV_OFFSET_REDUND	(CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
-#endif
-
 /*-----------------------------------------------------------------------
  * NAND FLASH
  *----------------------------------------------------------------------*/
@@ -231,11 +170,9 @@
  *
  * DDR Autocalibration Method_B is the default.
  */
-#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
 #define	CONFIG_PPC4xx_DDR_AUTOCALIBRATION	/* IBM DDR autocalibration */
 #define	DEBUG_PPC4xx_DDR_AUTOCALIBRATION	/* dynamic DDR autocal debug */
 #undef	CONFIG_PPC4xx_DDR_METHOD_A
-#endif
 
 #define	CONFIG_SYS_SDRAM0_MB0CF_BASE	((  0 << 20) + CONFIG_SYS_SDRAM_BASE)
 
@@ -417,7 +354,6 @@
 	CONFIG_AMCC_DEF_ENV_POWERPC					\
 	CONFIG_AMCC_DEF_ENV_PPC_OLD					\
 	CONFIG_AMCC_DEF_ENV_NOR_UPD					\
-	CONFIG_AMCC_DEF_ENV_NAND_UPD					\
 	"logversion=2\0"						\
 	"kernel_addr=fc000000\0"					\
 	"fdt_addr=fc1e0000\0"						\
@@ -435,16 +371,7 @@
 #define CONFIG_CMD_PCI
 #define CONFIG_CMD_SNTP
 
-/*
- * Don't run the memory POST on the NAND-booting version. It will
- * overwrite part of the U-Boot image which is already loaded from NAND
- * to SDRAM.
- */
-#if defined(CONFIG_NAND_U_BOOT)
-#define CONFIG_SYS_POST_MEMORY_ON	0
-#else
 #define CONFIG_SYS_POST_MEMORY_ON	CONFIG_SYS_POST_MEMORY
-#endif
 
 /* POST support */
 #define CONFIG_POST		(CONFIG_SYS_POST_CACHE		| \
@@ -495,18 +422,6 @@
 /*-----------------------------------------------------------------------
  * External Bus Controller (EBC) Setup
  *----------------------------------------------------------------------*/
-#if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
-/* booting from NAND, so NAND chips select has to be on CS 0 */
-#define CONFIG_SYS_NAND_CS		0		/* NAND chip connected to CSx	*/
-
-/* Memory Bank 1 (NOR-FLASH) initialization					*/
-#define CONFIG_SYS_EBC_PB1AP		0x05806500
-#define CONFIG_SYS_EBC_PB1CR           0xFC0DA000  /* BAS=0xFC0,BS=64MB,BU=R/W,BW=16bit*/
-
-/* Memory Bank 0 (NAND-FLASH) initialization					*/
-#define CONFIG_SYS_EBC_PB0AP		0x018003c0
-#define CONFIG_SYS_EBC_PB0CR		(CONFIG_SYS_NAND_ADDR | 0x1e000)
-#else
 #define CONFIG_SYS_NAND_CS		1		/* NAND chip connected to CSx	*/
 
 /* Memory Bank 0 (NOR-FLASH) initialization					*/
@@ -516,7 +431,6 @@
 /* Memory Bank 1 (NAND-FLASH) initialization					*/
 #define CONFIG_SYS_EBC_PB1AP		0x018003c0
 #define CONFIG_SYS_EBC_PB1CR		(CONFIG_SYS_NAND_ADDR | 0x1e000)
-#endif
 
 /* Memory Bank 2 (FPGA) initialization					*/
 #define CONFIG_SYS_EBC_PB2AP		(EBC_BXAP_BME_ENABLED |		\
diff --git a/include/configs/km/keymile-common.h b/include/configs/km/keymile-common.h
index 91ca480f48..517f46a3a3 100644
--- a/include/configs/km/keymile-common.h
+++ b/include/configs/km/keymile-common.h
@@ -39,7 +39,6 @@
  */
 #define CONFIG_SYS_HUSH_PARSER
 #define CONFIG_SYS_LONGHELP			/* undef to save memory	  */
-#define CONFIG_SYS_PROMPT		"=> "	/* Monitor Command Prompt */
 #if defined(CONFIG_CMD_KGDB)
 #define CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size */
 #else
@@ -55,16 +54,12 @@
 
 #define CONFIG_SYS_ALT_MEMTEST		/* memory test, takes time */
 
-#define CONFIG_SYS_HZ			1000	/* decr. freq: 1 ms ticks */
-
 #define CONFIG_BAUDRATE			115200
 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
 
 #define CONFIG_LOADS_ECHO
 #define CONFIG_SYS_LOADS_BAUD_CHANGE
 
-#define CONFIG_SYS_I2C_INIT_BOARD
-
 /* Support the IVM EEprom */
 #define	CONFIG_SYS_IVM_EEPROM_ADR	0x50
 #define CONFIG_SYS_IVM_EEPROM_MAX_LEN	0x400
@@ -80,8 +75,6 @@
 #define CONFIG_BOOTP_GATEWAY
 #define CONFIG_BOOTP_HOSTNAME
 
-#define CONFIG_SYS_MALLOC_LEN		(4 * 1024 * 1024)
-
 /* UBI Support for all Keymile boards */
 #define CONFIG_CMD_UBI
 #define CONFIG_RBTREE
@@ -106,11 +99,16 @@
 #define CONFIG_KM_UBI_PARTITION_NAME_BOOT	"ubi0"
 #endif /* CONFIG_KM_UBI_PARTITION_NAME_BOOT */
 
+#ifndef CONFIG_KM_UBI_PART_BOOT_OPTS
+#define CONFIG_KM_UBI_PART_BOOT_OPTS		""
+#endif /* CONFIG_KM_UBI_PART_BOOT_OPTS */
+
 #ifndef CONFIG_KM_UBI_PARTITION_NAME_APP
 /* one flash chip only called boot */
 /* boot: CONFIG_KM_UBI_PARTITION_NAME_BOOT */
 # define CONFIG_KM_UBI_LINUX_MTD					\
-	"ubi.mtd=" CONFIG_KM_UBI_PARTITION_NAME_BOOT
+	"ubi.mtd=" CONFIG_KM_UBI_PARTITION_NAME_BOOT			\
+	CONFIG_KM_UBI_PART_BOOT_OPTS
 # define CONFIG_KM_DEV_ENV_FLASH_BOOT_UBI				\
 	"ubiattach=ubi part " CONFIG_KM_UBI_PARTITION_NAME_BOOT "\0"
 #else /* CONFIG_KM_UBI_PARTITION_NAME_APP */
@@ -118,7 +116,8 @@
 /* boot: CONFIG_KM_UBI_PARTITION_NAME_BOOT */
 /* app:  CONFIG_KM_UBI_PARTITION_NAME_APP */
 # define CONFIG_KM_UBI_LINUX_MTD					\
-	"ubi.mtd=" CONFIG_KM_UBI_PARTITION_NAME_BOOT " "		\
+	"ubi.mtd=" CONFIG_KM_UBI_PARTITION_NAME_BOOT			\
+	CONFIG_KM_UBI_PART_BOOT_OPTS " "				\
 	"ubi.mtd=" CONFIG_KM_UBI_PARTITION_NAME_APP
 # define CONFIG_KM_DEV_ENV_FLASH_BOOT_UBI				\
 	"ubiattach=if test ${boot_bank} -eq 0; then; "			\
@@ -142,8 +141,8 @@
  * - 'release': for a standalone system		kernel/rootfs from flash
  */
 #define CONFIG_KM_DEF_ENV_BOOTTARGETS					\
-	"subbootcmds=ubiattach ubicopy cramfsloadfdt cramfsloadkernel "	\
-		"flashargs add_default addpanic boot\0"			\
+	"subbootcmds=ubiattach ubicopy cramfsloadfdt set_fdthigh "	\
+		"cramfsloadkernel flashargs add_default addpanic boot\0"\
 	"develop="							\
 		"tftp 200000 scripts/develop-${arch}.txt && "		\
 		"env import -t 200000 ${filesize} && "			\
@@ -167,7 +166,7 @@
 	"add_default="							\
 		"setenv bootargs ${bootargs} "				\
 		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
-		":${hostname}:${netdev}:off3"				\
+		":${hostname}:${netdev}:off:"				\
 		" console=" CONFIG_KM_CONSOLE_TTY ",${baudrate}"	\
 		" mem=${kernelmem} init=${init}"			\
 		CONFIG_KM_ECC_MODE					\
@@ -227,6 +226,7 @@
 	CONFIG_KM_DEF_ENV_FLASH_BOOT					\
 	CONFIG_KM_DEF_ENV_CONSTANTS					\
 	"altbootcmd=run bootcmd\0"					\
+	"boot=bootm ${load_addr_r} - ${fdt_addr_r}\0"			\
 	"bootcmd=km_checkbidhwk &&  "					\
 		"setenv bootcmd \'if km_checktestboot; then; "          \
 				"setenv boot_bank ${test_bank}; else; " \
@@ -236,6 +236,10 @@
 			"run ${subbootcmds}; reset\' && "		\
 		"saveenv && saveenv && boot\0"				\
 	"bootlimit=3\0"							\
+	"cramfsloadfdt="						\
+		"cramfsload ${fdt_addr_r} "				\
+		"fdt_0x${IVM_BoardId}_0x${IVM_HWKey}.dtb\0"		\
+	"fdt_addr_r="__stringify(CONFIG_KM_FDT_ADDR) "\0"		\
 	"init=/sbin/init-overlay.sh\0"					\
 	"load_addr_r="__stringify(CONFIG_KM_KERNEL_ADDR) "\0"		\
 	"load=tftpboot ${load_addr_r} ${u-boot}\0"			\
diff --git a/include/configs/km/km-powerpc.h b/include/configs/km/km-powerpc.h
index 8ee0ac6dbf..763c5bad82 100644
--- a/include/configs/km/km-powerpc.h
+++ b/include/configs/km/km-powerpc.h
@@ -17,6 +17,9 @@
 #define CONFIG_CMD_DTT
 #define CONFIG_JFFS2_CMDLINE
 
+/* standard km ethernet_present for piggy */
+#define CONFIG_KM_COMMON_ETH_INIT
+
 /* EEprom support 24C08, 24C16, 24C64 */
 #define CONFIG_SYS_I2C_MULTI_EEPROMS
 #define CONFIG_SYS_EEPROM_PAGE_WRITE_ENABLE
@@ -32,6 +35,9 @@
 
 #define CONFIG_SYS_LOAD_ADDR	0x100000	/* default load address */
 
+/* Reserve 4 MB for malloc */
+#define CONFIG_SYS_MALLOC_LEN		(4 * 1024 * 1024)
+
 /******************************************************************************
  * (PRAM usage)
  * ... -------------------------------------------------------
@@ -64,11 +70,6 @@
 #define CONFIG_KM_DEF_BOOT_ARGS_CPU		""
 
 #define CONFIG_KM_DEF_ENV_CPU						\
-	"boot=bootm ${load_addr_r} - ${fdt_addr_r}\0"			\
-	"cramfsloadfdt="						\
-		"cramfsload ${fdt_addr_r} "				\
-		"fdt_0x${IVM_BoardId}_0x${IVM_HWKey}.dtb\0"		\
-	"fdt_addr_r=" __stringify(CONFIG_KM_FDT_ADDR) "\0"		\
 	"u-boot="__stringify(CONFIG_HOSTNAME) "/u-boot.bin\0"		\
 	"update="							\
 		"protect off " __stringify(BOOTFLASH_START) " +${filesize} && "\
@@ -76,6 +77,7 @@
 		"cp.b ${load_addr_r} " __stringify(BOOTFLASH_START)	\
 		"  ${filesize} && "					\
 		"protect on " __stringify(BOOTFLASH_START) "  +${filesize}\0"\
+	"set_fdthigh=true\0"						\
 	""
 
 #endif /* __CONFIG_KEYMILE_POWERPC_H */
diff --git a/include/configs/km/km8309-common.h b/include/configs/km/km8309-common.h
index 47355abed9..29c6f60971 100644
--- a/include/configs/km/km8309-common.h
+++ b/include/configs/km/km8309-common.h
@@ -15,7 +15,6 @@
  */
 #define CONFIG_E300		1	/* E300 family */
 #define CONFIG_QE		1	/* Has QE */
-#define CONFIG_MPC83xx		1	/* MPC83xx family */
 #define CONFIG_MPC830x		1	/* MPC830x family */
 #define CONFIG_MPC8309		1	/* MPC8309 CPU specific */
 
diff --git a/include/configs/km/km83xx-common.h b/include/configs/km/km83xx-common.h
index 5e075c8dd2..ae6b6dcf24 100644
--- a/include/configs/km/km83xx-common.h
+++ b/include/configs/km/km83xx-common.h
@@ -84,7 +84,6 @@
 #define CONFIG_SYS_INIT_RAM_LOCK
 #define CONFIG_SYS_INIT_RAM_ADDR	0xE6000000 /* Initial RAM address */
 #define CONFIG_SYS_INIT_RAM_SIZE	0x1000 /* End of used area in RAM */
-#define CONFIG_SYS_GBL_DATA_SIZE	0x100 /* num bytes initial data */
 #define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - \
 						GENERATED_GBL_DATA_SIZE)
 
diff --git a/include/configs/km/km_arm.h b/include/configs/km/km_arm.h
index e0368cb894..6d77680c82 100644
--- a/include/configs/km/km_arm.h
+++ b/include/configs/km/km_arm.h
@@ -54,6 +54,9 @@
 #define CONFIG_ENV_SPI_MODE		SPI_MODE_3
 #endif
 
+/* Reserve 4 MB for malloc */
+#define CONFIG_SYS_MALLOC_LEN		(4 * 1024 * 1024)
+
 #include "asm/arch/config.h"
 
 #define CONFIG_SYS_TEXT_BASE	0x07d00000	/* code address before reloc */
@@ -67,7 +70,8 @@
 #define CONFIG_KM_PHRAM		0x17F000
 
 #define CONFIG_KM_CRAMFS_ADDR	0x2400000
-#define CONFIG_KM_KERNEL_ADDR	0x2000000	/* 4096KBytes */
+#define CONFIG_KM_KERNEL_ADDR	0x2000000	/* 3098KBytes */
+#define CONFIG_KM_FDT_ADDR	0x23E0000	/*  128KBytes */
 
 /* architecture specific default bootargs */
 #define CONFIG_KM_DEF_BOOT_ARGS_CPU					\
@@ -75,15 +79,17 @@
 		" boardid=0x${IVM_BoardId} hwkey=0x${IVM_HWKey}"
 
 #define CONFIG_KM_DEF_ENV_CPU						\
-	"boot=bootm ${load_addr_r} - -\0"				\
-	"cramfsloadfdt=true\0"						\
 	"u-boot="__stringify(CONFIG_HOSTNAME) "/u-boot.kwb\0"		\
 	CONFIG_KM_UPDATE_UBOOT						\
+	"set_fdthigh=setenv fdt_high ${kernelmem}\0"			\
 	""
 
 #define CONFIG_SKIP_LOWLEVEL_INIT	/* disable board lowlevel_init */
 #define CONFIG_MISC_INIT_R
 
+/* Pass open firmware flat tree */
+#define CONFIG_OF_LIBFDT
+
 /*
  * NS16550 Configuration
  */
@@ -161,6 +167,7 @@
 #define CONFIG_MVGBE_PORTS	{1, 0}	/* enable port 0 only */
 #define CONFIG_PHY_BASE_ADR	0
 #define CONFIG_ENV_OVERWRITE	/* ethaddr can be reprogrammed */
+#define CONFIG_KM_COMMON_ETH_INIT /* standard km ethernet_present for piggy */
 
 /*
  * UBI related stuff
@@ -173,10 +180,9 @@
 #undef CONFIG_I2C_MVTWSI
 #define CONFIG_SYS_I2C
 #define	CONFIG_SYS_I2C_SOFT	/* I2C bit-banged	*/
+#define CONFIG_SYS_I2C_INIT_BOARD
 
 #define	CONFIG_KIRKWOOD_GPIO		/* Enable GPIO Support */
-#if defined(CONFIG_SYS_I2C_SOFT)
-
 #define CONFIG_SYS_NUM_I2C_BUSES	6
 #define CONFIG_SYS_I2C_MAX_HOPS		1
 #define CONFIG_SYS_I2C_BUSES	{	{0, {I2C_NULL_HOP} }, \
@@ -211,7 +217,6 @@ int get_scl(void);
 
 #define	CONFIG_SYS_I2C_SOFT_SLAVE	0x0
 #define	CONFIG_SYS_I2C_SOFT_SPEED	100000
-#endif
 
 /* EEprom support 24C128, 24C256 valid for environment eeprom */
 #define CONFIG_SYS_I2C_MULTI_EEPROMS
@@ -287,10 +292,15 @@ int get_scl(void);
 		" ${addr} " __stringify(CONFIG_ENV_OFFSET_REDUND) " 4\0"
 #endif
 
+#ifndef CONFIG_KM_BOARD_EXTRA_ENV
+#define CONFIG_KM_BOARD_EXTRA_ENV       ""
+#endif
+
 /*
  * Default environment variables
  */
 #define CONFIG_EXTRA_ENV_SETTINGS					\
+	CONFIG_KM_BOARD_EXTRA_ENV					\
 	CONFIG_KM_DEF_ENV						\
 	CONFIG_KM_NEW_ENV						\
 	"arch=arm\0"							\
diff --git a/include/configs/km/kmp204x-common.h b/include/configs/km/kmp204x-common.h
new file mode 100644
index 0000000000..582978afe2
--- /dev/null
+++ b/include/configs/km/kmp204x-common.h
@@ -0,0 +1,466 @@
+/*
+ * (C) Copyright 2013 Keymile AG
+ * Valentin Longchamp <valentin.longchamp@keymile.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _CONFIG_KMP204X_H
+#define _CONFIG_KMP204X_H
+
+#define CONFIG_PHYS_64BIT
+#define CONFIG_PPC_P2041
+
+#define CONFIG_SYS_TEXT_BASE	0xfff80000
+
+#define CONFIG_KM_DEF_NETDEV	"netdev=eth0\0"
+
+/* an additionnal option is required for UBI as subpage access is
+ * supported in u-boot */
+#define CONFIG_KM_UBI_PART_BOOT_OPTS		",2048"
+
+#define CONFIG_NAND_ECC_BCH
+
+/* common KM defines */
+#include "keymile-common.h"
+
+#define CONFIG_SYS_RAMBOOT
+#define CONFIG_RAMBOOT_PBL
+#define CONFIG_RAMBOOT_TEXT_BASE	CONFIG_SYS_TEXT_BASE
+#define CONFIG_RESET_VECTOR_ADDRESS	0xfffffffc
+#define CONFIG_SYS_FSL_PBL_PBI board/keymile/kmp204x/pbi.cfg
+#define CONFIG_SYS_FSL_PBL_RCW board/keymile/kmp204x/rcw_kmp204x.cfg
+
+/* High Level Configuration Options */
+#define CONFIG_BOOKE
+#define CONFIG_E500			/* BOOKE e500 family */
+#define CONFIG_E500MC			/* BOOKE e500mc family */
+#define CONFIG_SYS_BOOK3E_HV		/* Category E.HV supported */
+#define CONFIG_FSL_CORENET		/* Freescale CoreNet platform */
+#define CONFIG_MP			/* support multiple processors */
+
+#define CONFIG_SYS_FSL_CPC		/* Corenet Platform Cache */
+#define CONFIG_SYS_NUM_CPC		CONFIG_NUM_DDR_CONTROLLERS
+#define CONFIG_FSL_ELBC			/* Has Enhanced localbus controller */
+#define CONFIG_PCI			/* Enable PCI/PCIE */
+#define CONFIG_PCIE1			/* PCIE controler 1 */
+#define CONFIG_PCIE3			/* PCIE controler 3 */
+#define CONFIG_FSL_PCI_INIT		/* Use common FSL init code */
+#define CONFIG_SYS_PCI_64BIT		/* enable 64-bit PCI resources */
+
+#define CONFIG_SYS_DPAA_RMAN		/* RMan */
+
+#define CONFIG_FSL_LAW			/* Use common FSL init code */
+
+/* Environment in SPI Flash */
+#define CONFIG_SYS_EXTRA_ENV_RELOC
+#define CONFIG_ENV_IS_IN_SPI_FLASH
+#define CONFIG_ENV_SPI_BUS              0
+#define CONFIG_ENV_SPI_CS               0
+#define CONFIG_ENV_SPI_MAX_HZ           20000000
+#define CONFIG_ENV_SPI_MODE             0
+#define CONFIG_ENV_OFFSET               0x100000	/* 1MB for u-boot */
+#define CONFIG_ENV_SIZE			0x004000	/* 16K env */
+#define CONFIG_ENV_SECT_SIZE            0x010000
+#define CONFIG_ENV_OFFSET_REDUND	0x110000
+#define CONFIG_ENV_TOTAL_SIZE		0x020000
+
+#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
+
+#ifndef __ASSEMBLY__
+unsigned long get_board_sys_clk(unsigned long dummy);
+#endif
+#define CONFIG_SYS_CLK_FREQ	get_board_sys_clk(0)
+
+/*
+ * These can be toggled for performance analysis, otherwise use default.
+ */
+#define CONFIG_SYS_CACHE_STASHING
+#define CONFIG_BACKSIDE_L2_CACHE
+#define CONFIG_SYS_INIT_L2CSR0		L2CSR0_L2E
+#define CONFIG_BTB			/* toggle branch predition */
+
+#define CONFIG_ENABLE_36BIT_PHYS
+
+#define CONFIG_ADDR_MAP
+#define CONFIG_SYS_NUM_ADDR_MAP		64	/* number of TLB1 entries */
+
+#define CONFIG_POST CONFIG_SYS_POST_MEMORY	/* test POST memory test */
+#define CONFIG_SYS_MEMTEST_START	0x00100000	/* memtest works on */
+#define CONFIG_SYS_MEMTEST_END		0x00800000
+#define CONFIG_SYS_ALT_MEMTEST
+#define CONFIG_PANIC_HANG	/* do not reset board on panic */
+
+/*
+ *  Config the L3 Cache as L3 SRAM
+ */
+#define CONFIG_SYS_INIT_L3_ADDR		CONFIG_RAMBOOT_TEXT_BASE
+#define CONFIG_SYS_INIT_L3_ADDR_PHYS	(0xf00000000ull | \
+		CONFIG_RAMBOOT_TEXT_BASE)
+#define CONFIG_SYS_L3_SIZE		(1024 << 10)
+#define CONFIG_SYS_INIT_L3_END (CONFIG_SYS_INIT_L3_ADDR + CONFIG_SYS_L3_SIZE)
+
+#define CONFIG_SYS_DCSRBAR		0xf0000000
+#define CONFIG_SYS_DCSRBAR_PHYS		0xf00000000ull
+
+/*
+ * DDR Setup
+ */
+#define CONFIG_VERY_BIG_RAM
+#define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000
+#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
+
+#define CONFIG_DIMM_SLOTS_PER_CTLR	1
+#define CONFIG_CHIP_SELECTS_PER_CTRL	(4 * CONFIG_DIMM_SLOTS_PER_CTLR)
+
+#define CONFIG_DDR_SPD
+#define CONFIG_SYS_FSL_DDR3
+#define CONFIG_FSL_DDR_INTERACTIVE
+
+#define CONFIG_SYS_SPD_BUS_NUM	0
+#define SPD_EEPROM_ADDRESS	0x54
+#define CONFIG_SYS_SDRAM_SIZE	4096	/* for fixed parameter use */
+
+#define CONFIG_SYS_LOAD_ADDR	0x100000	/* default load address */
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	2
+
+/******************************************************************************
+ * (PRAM usage)
+ * ... -------------------------------------------------------
+ * ... |ROOTFSSIZE | PNVRAM |PHRAM |RESERVED_PRAM | END_OF_RAM
+ * ... |<------------------- pram -------------------------->|
+ * ... -------------------------------------------------------
+ * @END_OF_RAM:
+ * @CONFIG_KM_RESERVED_PRAM: reserved pram for special purpose
+ * @CONFIG_KM_PHRAM: address for /var
+ * @CONFIG_KM_PNVRAM: address for PNVRAM (for the application)
+ * @CONFIG_KM_ROOTFSSIZE: address for rootfilesystem in RAM
+ */
+
+/* size of rootfs in RAM */
+#define CONFIG_KM_ROOTFSSIZE	0x0
+/* pseudo-non volatile RAM [hex] */
+#define CONFIG_KM_PNVRAM	0x80000
+/* physical RAM MTD size [hex] */
+#define CONFIG_KM_PHRAM		0x100000
+/* resereved pram area at the end of memroy [hex] */
+#define CONFIG_KM_RESERVED_PRAM	0x0
+/* enable protected RAM */
+#define CONFIG_PRAM		0
+
+#define CONFIG_KM_CRAMFS_ADDR	0x2000000
+#define CONFIG_KM_KERNEL_ADDR	0x1000000	/* max kernel size 15.5Mbytes */
+#define CONFIG_KM_FDT_ADDR	0x1F80000	/* max dtb    size  0.5Mbytes */
+
+/*
+ * Local Bus Definitions
+ */
+
+/* Set the local bus clock 1/8 of plat clk, 2 clk delay LALE */
+#define CONFIG_SYS_LBC_LCRR		(LCRR_CLKDIV_8 | LCRR_EADC_2)
+
+/* Nand Flash */
+#define CONFIG_NAND_FSL_ELBC
+#define CONFIG_SYS_NAND_BASE		0xffa00000
+#define CONFIG_SYS_NAND_BASE_PHYS	0xfffa00000ull
+
+#define CONFIG_SYS_NAND_BASE_LIST     {CONFIG_SYS_NAND_BASE}
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+#define CONFIG_MTD_NAND_VERIFY_WRITE
+#define CONFIG_CMD_NAND
+#define CONFIG_SYS_NAND_BLOCK_SIZE    (128 * 1024)
+
+#define CONFIG_BCH
+
+/* NAND flash config */
+#define CONFIG_SYS_NAND_BR_PRELIM  (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
+			       | BR_PS_8	       /* Port Size = 8 bit */ \
+			       | BR_MS_FCM	       /* MSEL = FCM */ \
+			       | BR_V)		       /* valid */
+
+#define CONFIG_SYS_NAND_OR_PRELIM  (OR_AM_256KB	      /* length 256K */ \
+			       | OR_FCM_BCTLD	/* LBCTL not ass */	\
+			       | OR_FCM_SCY_1	/* 1 clk wait cycle */	\
+			       | OR_FCM_RST	/* 1 clk read setup */	\
+			       | OR_FCM_PGS	/* Large page size */	\
+			       | OR_FCM_CST)	/* 0.25 command setup */
+
+#define CONFIG_SYS_BR0_PRELIM  CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
+#define CONFIG_SYS_OR0_PRELIM  CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
+
+/* QRIO FPGA */
+#define CONFIG_SYS_QRIO_BASE		0xfb000000
+#define CONFIG_SYS_QRIO_BASE_PHYS	0xffb000000ull
+
+#define CONFIG_SYS_QRIO_BR_PRELIM  (BR_PHYS_ADDR(CONFIG_SYS_QRIO_BASE_PHYS) \
+				| BR_PS_8	/* Port Size 8 bits */ \
+				| BR_DECC_OFF	/* no error corr */ \
+				| BR_MS_GPCM	/* MSEL = GPCM */ \
+				| BR_V)		/* valid */
+
+#define CONFIG_SYS_QRIO_OR_PRELIM  (OR_AM_64KB	/* length 64K */ \
+				| OR_GPCM_BCTLD /* no LCTL assert */ \
+				| OR_GPCM_ACS_DIV4 /* LCS 1/4 clk after */ \
+				| OR_GPCM_SCY_2 /* 2 clk wait cycles */ \
+				| OR_GPCM_TRLX /* relaxed tmgs */ \
+				| OR_GPCM_EAD) /* extra bus clk cycles */
+
+#define CONFIG_SYS_BR1_PRELIM  CONFIG_SYS_QRIO_BR_PRELIM /* QRIO Base Address */
+#define CONFIG_SYS_OR1_PRELIM  CONFIG_SYS_QRIO_OR_PRELIM /* QRIO Options */
+
+/* bootcounter in QRIO */
+#define CONFIG_BOOTCOUNT_LIMIT
+#define CONFIG_SYS_BOOTCOUNT_ADDR	(CONFIG_SYS_QRIO_BASE + 0x20)
+
+#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_BOARD_EARLY_INIT_R	/* call board_early_init_r function */
+#define CONFIG_MISC_INIT_F
+#define CONFIG_MISC_INIT_R
+#define CONFIG_LAST_STAGE_INIT
+
+#define CONFIG_HWCONFIG
+
+/* define to use L1 as initial stack */
+#define CONFIG_L1_INIT_RAM
+#define CONFIG_SYS_INIT_RAM_LOCK
+#define CONFIG_SYS_INIT_RAM_ADDR	0xffd00000	/* Initial L1 address */
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR
+/* The assembler doesn't like typecast */
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
+	((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
+	  CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
+#define CONFIG_SYS_INIT_RAM_SIZE	0x00004000
+
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - \
+					GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_MONITOR_LEN		(512 * 1024)
+#define CONFIG_SYS_MALLOC_LEN		(1024 * 1024)
+
+/* Serial Port - controlled on board with jumper J8
+ * open - index 2
+ * shorted - index 1
+ */
+#define CONFIG_CONS_INDEX	1
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	1
+#define CONFIG_SYS_NS16550_CLK		(get_bus_freq(0)/2)
+
+#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_CCSRBAR+0x11C500)
+#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_CCSRBAR+0x11C600)
+#define CONFIG_SYS_NS16550_COM3	(CONFIG_SYS_CCSRBAR+0x11D500)
+#define CONFIG_SYS_NS16550_COM4	(CONFIG_SYS_CCSRBAR+0x11D600)
+
+#define CONFIG_KM_CONSOLE_TTY	"ttyS0"
+
+/* Use the HUSH parser */
+#define CONFIG_SYS_HUSH_PARSER
+
+/* pass open firmware flat tree */
+#define CONFIG_OF_LIBFDT
+#define CONFIG_OF_BOARD_SETUP
+#define CONFIG_OF_STDOUT_VIA_ALIAS
+
+/* new uImage format support */
+#define CONFIG_FIT
+#define CONFIG_FIT_VERBOSE	/* enable fit_format_{error,warning}() */
+
+/* I2C */
+
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_INIT_BOARD
+#define CONFIG_SYS_I2C_SPEED		100000 /* deblocking */
+#define CONFIG_SYS_NUM_I2C_BUSES	3
+#define CONFIG_SYS_I2C_MAX_HOPS		1
+#define CONFIG_SYS_I2C_FSL		/* Use FSL I2C driver */
+#define CONFIG_I2C_MULTI_BUS
+#define CONFIG_I2C_CMD_TREE
+#define CONFIG_SYS_FSL_I2C_SPEED	400000
+#define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
+#define CONFIG_SYS_FSL_I2C_OFFSET	0x118000
+#define CONFIG_SYS_I2C_BUSES	{	{0, {I2C_NULL_HOP} }, \
+					{0, {{I2C_MUX_PCA9547, 0x70, 1 } } }, \
+					{0, {{I2C_MUX_PCA9547, 0x70, 2 } } }, \
+				}
+#ifndef __ASSEMBLY__
+void set_sda(int state);
+void set_scl(int state);
+int get_sda(void);
+int get_scl(void);
+#endif
+
+#define CONFIG_KM_IVM_BUS		1	/* I2C1 (Mux-Port 1)*/
+
+/*
+ * eSPI - Enhanced SPI
+ */
+#define CONFIG_FSL_ESPI
+#define CONFIG_SPI_FLASH
+#define CONFIG_SPI_FLASH_BAR	/* 4 byte-addressing */
+#define CONFIG_SPI_FLASH_STMICRO
+#define CONFIG_SPI_FLASH_SPANSION
+#define CONFIG_CMD_SF
+#define CONFIG_SF_DEFAULT_SPEED         20000000
+#define CONFIG_SF_DEFAULT_MODE          0
+
+/*
+ * General PCI
+ * Memory space is mapped 1-1, but I/O space must start from 0.
+ */
+
+/* controller 1, direct to uli, tgtid 3, Base address 20000 */
+#define CONFIG_SYS_PCIE1_MEM_VIRT	0x80000000
+#define CONFIG_SYS_PCIE1_MEM_BUS	0xe0000000
+#define CONFIG_SYS_PCIE1_MEM_PHYS	0xc00000000ull
+#define CONFIG_SYS_PCIE1_MEM_SIZE	0x20000000	/* 512M */
+#define CONFIG_SYS_PCIE1_IO_VIRT	0xf8000000
+#define CONFIG_SYS_PCIE1_IO_BUS		0x00000000
+#define CONFIG_SYS_PCIE1_IO_PHYS	0xff8000000ull
+#define CONFIG_SYS_PCIE1_IO_SIZE	0x00010000	/* 64k */
+
+/* controller 3, Slot 1, tgtid 1, Base address 202000 */
+#define CONFIG_SYS_PCIE3_MEM_VIRT	0xa0000000
+#define CONFIG_SYS_PCIE3_MEM_BUS	0xe0000000
+#define CONFIG_SYS_PCIE3_MEM_PHYS	0xc20000000ull
+#define CONFIG_SYS_PCIE3_MEM_SIZE	0x20000000	/* 512M */
+#define CONFIG_SYS_PCIE3_IO_VIRT	0xf8010000
+#define CONFIG_SYS_PCIE3_IO_BUS		0x00000000
+#define CONFIG_SYS_PCIE3_IO_PHYS	0xff8010000ull
+#define CONFIG_SYS_PCIE3_IO_SIZE	0x00010000	/* 64k */
+
+/* Qman/Bman */
+#define CONFIG_SYS_DPAA_QBMAN		/* Support Q/Bman */
+#define CONFIG_SYS_BMAN_NUM_PORTALS	10
+#define CONFIG_SYS_BMAN_MEM_BASE	0xf4000000
+#define CONFIG_SYS_BMAN_MEM_PHYS	0xff4000000ull
+#define CONFIG_SYS_BMAN_MEM_SIZE	0x00200000
+#define CONFIG_SYS_QMAN_NUM_PORTALS	10
+#define CONFIG_SYS_QMAN_MEM_BASE	0xf4200000
+#define CONFIG_SYS_QMAN_MEM_PHYS	0xff4200000ull
+#define CONFIG_SYS_QMAN_MEM_SIZE	0x00200000
+
+#define CONFIG_SYS_DPAA_FMAN
+#define CONFIG_SYS_DPAA_PME
+/* Default address of microcode for the Linux Fman driver
+ * env is stored at 0x100000, sector size is 0x10000, x2 (redundant)
+ * ucode is stored after env, so we got 0x120000.
+ */
+#define CONFIG_SYS_QE_FW_IN_SPIFLASH
+#define CONFIG_SYS_QE_FMAN_FW_ADDR	0x120000
+#define CONFIG_SYS_QE_FMAN_FW_LENGTH	0x10000
+#define CONFIG_SYS_FDT_PAD		(0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
+
+#define CONFIG_FMAN_ENET
+#define CONFIG_PHYLIB_10G
+#define CONFIG_PHY_MARVELL		/* there is a marvell phy */
+
+#define CONFIG_PCI_INDIRECT_BRIDGE
+#define CONFIG_PCI_PNP			/* do pci plug-and-play */
+#define CONFIG_E1000
+
+#define CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
+#define CONFIG_DOS_PARTITION
+
+/* RGMII (FM1@DTESC5) is used as debug itf, it's the only one configured */
+#define CONFIG_SYS_FM1_DTSEC5_PHY_ADDR	0x11
+#define CONFIG_SYS_TBIPA_VALUE	8
+#define CONFIG_PHYLIB		/* recommended PHY management */
+#define CONFIG_ETHPRIME		"FM1@DTSEC5"
+#define CONFIG_PHY_GIGE		/* Include GbE speed/duplex detection */
+
+/*
+ * Environment
+ */
+#define CONFIG_LOADS_ECHO		/* echo on for serial download */
+#define CONFIG_SYS_LOADS_BAUD_CHANGE	/* allow baudrate change */
+
+/*
+ * additionnal command line configuration.
+ */
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_NET
+
+/* we don't need flash support */
+#define CONFIG_SYS_NO_FLASH
+#undef CONFIG_CMD_IMLS
+#undef CONFIG_CMD_FLASH
+#undef CONFIG_FLASH_CFI_MTD
+#undef CONFIG_JFFS2_CMDLINE
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 64 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ	(64 << 20)	/* Initial Memory for Linux */
+#define CONFIG_SYS_BOOTM_LEN	(64 << 20)	/* Increase max gunzip size */
+
+#ifdef CONFIG_CMD_KGDB
+#define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
+#endif
+
+#define __USB_PHY_TYPE	utmi
+
+/*
+ * Environment Configuration
+ */
+#define CONFIG_ENV_OVERWRITE
+#ifndef CONFIG_KM_DEF_ENV		/* if not set by keymile-common.h */
+#define CONFIG_KM_DEF_ENV "km-common=empty\0"
+#endif
+
+#ifndef MTDIDS_DEFAULT
+# define MTDIDS_DEFAULT		"nand0=fsl_elbc_nand"
+#endif /* MTDIDS_DEFAULT */
+
+#ifndef MTDPARTS_DEFAULT
+# define MTDPARTS_DEFAULT	"mtdparts="			\
+	"fsl_elbc_nand:"						\
+		"-(" CONFIG_KM_UBI_PARTITION_NAME_BOOT ");"
+#endif /* MTDPARTS_DEFAULT */
+
+/* architecture specific default bootargs */
+#define CONFIG_KM_DEF_BOOT_ARGS_CPU		""
+
+/* FIXME: FDT_ADDR is unspecified */
+#define CONFIG_KM_DEF_ENV_CPU						\
+	"boot=bootm ${load_addr_r} - ${fdt_addr_r}\0"			\
+	"cramfsloadfdt="						\
+		"cramfsload ${fdt_addr_r} "				\
+		"fdt_0x${IVM_BoardId}_0x${IVM_HWKey}.dtb\0"		\
+	"fdt_addr_r=" __stringify(CONFIG_KM_FDT_ADDR) "\0"		\
+	"u-boot="__stringify(CONFIG_HOSTNAME) "/u-boot.pbl\0"		\
+	"update="							\
+		"sf probe 0;sf erase 0 +${filesize};"			\
+		"sf write ${load_addr_r} 0 ${filesize};\0"		\
+	"set_fdthigh=true\0"						\
+	""
+
+#define CONFIG_HW_ENV_SETTINGS						\
+	"hwconfig=fsl_ddr:ctlr_intlv=cacheline\0"			\
+	"usb_phy_type=" __stringify(__USB_PHY_TYPE) "\0"		\
+	"usb_dr_mode=host\0"
+
+#define CONFIG_KM_NEW_ENV						\
+	"newenv=sf probe 0;"						\
+		"sf erase " __stringify(CONFIG_ENV_OFFSET) " "		\
+		__stringify(CONFIG_ENV_TOTAL_SIZE)"\0"
+
+/* ppc_82xx is the equivalent to ppc_6xx, the generic ppc toolchain */
+#ifndef CONFIG_KM_DEF_ARCH
+#define CONFIG_KM_DEF_ARCH	"arch=ppc_82xx\0"
+#endif
+
+#define CONFIG_EXTRA_ENV_SETTINGS					\
+	CONFIG_KM_DEF_ENV						\
+	CONFIG_KM_DEF_ARCH						\
+	CONFIG_KM_NEW_ENV						\
+	CONFIG_HW_ENV_SETTINGS						\
+	"EEprom_ivm=pca9547:70:9\0"					\
+	""
+
+#endif /* _CONFIG_KMP204X_H */
diff --git a/include/configs/km82xx.h b/include/configs/km82xx.h
index 986c65f1e6..029c348285 100644
--- a/include/configs/km82xx.h
+++ b/include/configs/km82xx.h
@@ -227,6 +227,7 @@
 /* enable I2C and select the hardware/software driver */
 #define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_SOFT		/* I2C bit-banged */
+#define CONFIG_SYS_I2C_INIT_BOARD
 #define CONFIG_SYS_NUM_I2C_BUSES	3
 #define CONFIG_SYS_I2C_MAX_HOPS		1
 #define CONFIG_SYS_I2C_SOFT_SPEED	50000
@@ -237,6 +238,7 @@
 			{0, {{I2C_MUX_PCA9542, 0x70, 1} } } }
 
 #define CONFIG_KM_IVM_BUS		1	/* I2C2 (Mux-Port 1)*/
+#define CONFIG_KM_I2C_ABORT
 
 /*
  * Software (bit-bang) I2C driver configuration
diff --git a/include/configs/km_kirkwood.h b/include/configs/km_kirkwood.h
index 0e6073c642..9eb1ad3397 100644
--- a/include/configs/km_kirkwood.h
+++ b/include/configs/km_kirkwood.h
@@ -35,14 +35,30 @@
 #define CONFIG_KM_IVM_BUS		1	/* I2C2 (Mux-Port 1)*/
 #define CONFIG_KM_FPGA_CONFIG
 
-/* KM_NUSA */
-#elif defined(CONFIG_KM_NUSA)
+/* KM_KIRKWOOD_128M16 */
+#elif defined(CONFIG_KM_KIRKWOOD_128M16)
+#define CONFIG_IDENT_STRING		"\nKeymile Kirkwood 128M16"
+#define CONFIG_HOSTNAME			km_kirkwood_128m16
+#undef CONFIG_SYS_KWD_CONFIG
+#define CONFIG_SYS_KWD_CONFIG $(CONFIG_BOARDDIR)/kwbimage_128M16_1.cfg
+#define CONFIG_KM_DISABLE_PCIE
+#define CONFIG_KM_IVM_BUS		1	/* I2C2 (Mux-Port 1)*/
+
+/* KM_NUSA / KM_SUGP1 */
+#elif defined(CONFIG_KM_NUSA) || defined(CONFIG_KM_SUGP1)
 #define CONFIG_KM_IVM_BUS		1	/* I2C2 (Mux-Port 1)*/
+
+# if defined(CONFIG_KM_NUSA)
 #define CONFIG_IDENT_STRING		"\nKeymile NUSA"
 #define CONFIG_HOSTNAME			kmnusa
+# elif defined(CONFIG_KM_SUGP1)
+#define CONFIG_IDENT_STRING		"\nKeymile SUGP1"
+#define CONFIG_HOSTNAME			kmsugp1
+#define KM_PCIE_RESET_MPP7
+#endif
+
 #undef CONFIG_SYS_KWD_CONFIG
-#define CONFIG_SYS_KWD_CONFIG \
-		$(SRCTREE)/$(CONFIG_BOARDDIR)/kwbimage_128M16_1.cfg
+#define CONFIG_SYS_KWD_CONFIG $(CONFIG_BOARDDIR)/kwbimage_128M16_1.cfg
 #define CONFIG_KM_ENV_IS_IN_SPI_NOR
 #define CONFIG_KM_FPGA_CONFIG
 #define CONFIG_KM_PIGGY4_88E6352
@@ -55,8 +71,7 @@
 #define CONFIG_HOSTNAME			mgcoge3un
 #define CONFIG_KM_IVM_BUS		1	/* I2C2 (Mux-Port 1)*/
 #undef CONFIG_SYS_KWD_CONFIG
-#define CONFIG_SYS_KWD_CONFIG \
-		$(SRCTREE)/$(CONFIG_BOARDDIR)/kwbimage-memphis.cfg
+#define CONFIG_SYS_KWD_CONFIG $(CONFIG_BOARDDIR)/kwbimage-memphis.cfg
 #define CONFIG_KM_BOARD_EXTRA_ENV	"waitforne=true\0"
 #define CONFIG_PIGGY_MAC_ADRESS_OFFSET  3
 #define CONFIG_KM_DISABLE_PCIE
@@ -67,8 +82,7 @@
 #define CONFIG_IDENT_STRING		"\nKeymile COGE5UN"
 #define CONFIG_KM_IVM_BUS		1	/* I2C2 (Mux-Port 1)*/
 #undef	CONFIG_SYS_KWD_CONFIG
-#define CONFIG_SYS_KWD_CONFIG \
-		$(SRCTREE)/$(CONFIG_BOARDDIR)/kwbimage_256M8_1.cfg
+#define CONFIG_SYS_KWD_CONFIG $(CONFIG_BOARDDIR)/kwbimage_256M8_1.cfg
 #define CONFIG_KM_ENV_IS_IN_SPI_NOR
 #define CONFIG_PIGGY_MAC_ADRESS_OFFSET	3
 #define CONFIG_HOSTNAME			kmcoge5un
@@ -87,6 +101,8 @@
 #define CONFIG_KM_IVM_BUS		1	/* I2C2 (Mux-Port 1)*/
 #define CONFIG_IDENT_STRING		"\nKeymile SUV31"
 #define CONFIG_HOSTNAME			kmsuv31
+#undef CONFIG_SYS_KWD_CONFIG
+#define CONFIG_SYS_KWD_CONFIG $(CONFIG_BOARDDIR)/kwbimage_128M16_1.cfg
 #define CONFIG_KM_ENV_IS_IN_SPI_NOR
 #define CONFIG_KM_FPGA_CONFIG
 
diff --git a/include/configs/kmp204x.h b/include/configs/kmp204x.h
new file mode 100644
index 0000000000..8bb3571691
--- /dev/null
+++ b/include/configs/kmp204x.h
@@ -0,0 +1,73 @@
+/*
+ * (C) Copyright 2013 Keymile AG
+ * Valentin Longchamp <valentin.longchamp@keymile.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/* KMLION1 */
+#if defined(CONFIG_KMLION1)
+#define CONFIG_HOSTNAME		kmlion1
+#define CONFIG_KM_BOARD_NAME	"kmlion1"
+
+/* KMCOGE4 */
+#elif defined(CONFIG_KMCOGE4)
+#define CONFIG_HOSTNAME		kmcoge4
+#define CONFIG_KM_BOARD_NAME	"kmcoge4"
+
+#else
+#error ("Board not supported")
+#endif
+
+#define CONFIG_KMP204X
+
+#include "km/kmp204x-common.h"
+
+#if defined(CONFIG_KMLION1)
+/* App1 Local bus */
+#define CONFIG_SYS_LBAPP1_BASE		0xD0000000
+#define CONFIG_SYS_LBAPP1_BASE_PHYS	0xFD0000000ull
+
+#define CONFIG_SYS_LBAPP1_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_LBAPP1_BASE_PHYS) \
+				| BR_PS_8	/* Port Size 8 bits */ \
+				| BR_DECC_OFF	/* no error corr */ \
+				| BR_MS_GPCM	/* MSEL = GPCM */ \
+				| BR_V)		/* valid */
+
+#define CONFIG_SYS_LBAPP1_OR_PRELIM (OR_AM_256MB	/* length 256MB */ \
+				| OR_GPCM_ACS_DIV2 /* LCS 1/2 clk after */ \
+				| OR_GPCM_CSNT /* LCS 1/4 clk before */ \
+				| OR_GPCM_SCY_2 /* 2 clk wait cycles */ \
+				| OR_GPCM_TRLX /* relaxed tmgs */ \
+				| OR_GPCM_EAD) /* extra bus clk cycles */
+/* Local bus app1 Base Address */
+#define CONFIG_SYS_BR2_PRELIM  CONFIG_SYS_LBAPP1_BR_PRELIM
+/* Local bus app1 Options */
+#define CONFIG_SYS_OR2_PRELIM  CONFIG_SYS_LBAPP1_OR_PRELIM
+#endif
+
+/* App2 Local bus */
+#define CONFIG_SYS_LBAPP2_BASE		0xE0000000
+#define CONFIG_SYS_LBAPP2_BASE_PHYS	0xFE0000000ull
+
+#define CONFIG_SYS_LBAPP2_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_LBAPP2_BASE_PHYS) \
+				| BR_PS_8	/* Port Size 8 bits */ \
+				| BR_DECC_OFF	/* no error corr */ \
+				| BR_MS_GPCM	/* MSEL = GPCM */ \
+				| BR_V)		/* valid */
+
+#define CONFIG_SYS_LBAPP2_OR_PRELIM (OR_AM_256MB	/* length 256MB */ \
+				| OR_GPCM_ACS_DIV2 /* LCS 1/2 clk after */ \
+				| OR_GPCM_CSNT /* LCS 1/4 clk before */ \
+				| OR_GPCM_SCY_2 /* 2 clk wait cycles */ \
+				| OR_GPCM_TRLX /* relaxed tmgs */ \
+				| OR_GPCM_EAD) /* extra bus clk cycles */
+/* Local bus app2 Base Address */
+#define CONFIG_SYS_BR3_PRELIM  CONFIG_SYS_LBAPP2_BR_PRELIM
+/* Local bus app2 Options */
+#define CONFIG_SYS_OR3_PRELIM  CONFIG_SYS_LBAPP2_OR_PRELIM
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/koelsch.h b/include/configs/koelsch.h
new file mode 100644
index 0000000000..90e2d7a030
--- /dev/null
+++ b/include/configs/koelsch.h
@@ -0,0 +1,192 @@
+/*
+ * include/configs/koelsch.h
+ *
+ * Copyright (C) 2013 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#ifndef __KOELSCH_H
+#define __KOELSCH_H
+
+#undef DEBUG
+#define CONFIG_ARMV7
+#define CONFIG_R8A7791
+#define CONFIG_RMOBILE
+#define CONFIG_RMOBILE_BOARD_STRING "Koelsch"
+#define CONFIG_SH_GPIO_PFC
+
+#include <asm/arch/rmobile.h>
+
+#define CONFIG_CMD_EDITENV
+#define CONFIG_CMD_SAVEENV
+#define CONFIG_CMD_MEMORY
+#define CONFIG_CMD_DFL
+#define CONFIG_CMD_SDRAM
+#define CONFIG_CMD_RUN
+#define CONFIG_CMD_LOADS
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_BOOTZ
+
+#if defined(CONFIG_SYS_USE_BOOT_NORFLASH)
+#define	CONFIG_CMD_FLASH
+#define CONFIG_SYS_TEXT_BASE	0x00000000
+#else
+/* SPI flash boot is default. */
+#define CONFIG_CMD_SF
+#define CONFIG_CMD_SPI
+#define CONFIG_SYS_TEXT_BASE	0xE6304000
+#endif
+
+#define	CONFIG_CMDLINE_TAG
+#define	CONFIG_SETUP_MEMORY_TAGS
+#define	CONFIG_INITRD_TAG
+#define	CONFIG_CMDLINE_EDITING
+
+#define CONFIG_OF_LIBFDT
+#define BOARD_LATE_INIT
+
+#define CONFIG_BAUDRATE		38400
+#define CONFIG_BOOTDELAY	3
+#define CONFIG_BOOTARGS		""
+
+#define CONFIG_VERSION_VARIABLE
+#undef	CONFIG_SHOW_BOOT_PROGRESS
+
+#define CONFIG_ARCH_CPU_INIT
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DISPLAY_BOARDINFO
+#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_USE_ARCH_MEMSET
+#define CONFIG_USE_ARCH_MEMCPY
+#define CONFIG_TMU_TIMER
+
+/* STACK */
+#define CONFIG_SYS_INIT_SP_ADDR		0xE633fffc
+#define STACK_AREA_SIZE				0xC000
+#define LOW_LEVEL_MERAM_STACK	\
+		(CONFIG_SYS_INIT_SP_ADDR + STACK_AREA_SIZE - 4)
+
+/* MEMORY */
+#define KOELSCH_SDRAM_BASE	0x40000000
+#define KOELSCH_SDRAM_SIZE	(2048u * 1024 * 1024)
+#define KOELSCH_UBOOT_SDRAM_SIZE	(512 * 1024 * 1024)
+
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_SYS_CBSIZE		256
+#define CONFIG_SYS_PBSIZE		256
+#define CONFIG_SYS_MAXARGS		16
+#define CONFIG_SYS_BARGSIZE		512
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 38400, 115200 }
+
+/* SCIF */
+#define CONFIG_SCIF_CONSOLE
+#define CONFIG_CONS_SCIF0
+#define SCIF0_BASE		0xe6e60000
+#undef	CONFIG_SYS_CONSOLE_INFO_QUIET
+#undef	CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
+#undef	CONFIG_SYS_CONSOLE_ENV_OVERWRITE
+
+#define CONFIG_SYS_MEMTEST_START	(KOELSCH_SDRAM_BASE)
+#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_MEMTEST_START + \
+					 504 * 1024 * 1024)
+#undef	CONFIG_SYS_ALT_MEMTEST
+#undef	CONFIG_SYS_MEMTEST_SCRATCH
+#undef	CONFIG_SYS_LOADS_BAUD_CHANGE
+
+#define CONFIG_SYS_SDRAM_BASE		(KOELSCH_SDRAM_BASE)
+#define CONFIG_SYS_SDRAM_SIZE		(KOELSCH_UBOOT_SDRAM_SIZE)
+#define CONFIG_SYS_LOAD_ADDR		(CONFIG_SYS_SDRAM_BASE + 0x7fc0)
+#define CONFIG_NR_DRAM_BANKS		1
+
+#define CONFIG_SYS_MONITOR_BASE		0x00000000
+#define CONFIG_SYS_MONITOR_LEN		(256 * 1024)
+#define CONFIG_SYS_MALLOC_LEN		(1 * 1024 * 1024)
+#define CONFIG_SYS_BOOTMAPSZ		(8 * 1024 * 1024)
+
+/* FLASH */
+#if defined(CONFIG_SYS_USE_BOOT_NORFLASH)
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_16BIT
+#define	CONFIG_FLASH_CFI_DRIVER
+#define	CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
+#define	CONFIG_FLASH_SHOW_PROGRESS	45
+#define CONFIG_SYS_FLASH_BASE		0x00000000
+#define	CONFIG_SYS_FLASH_SIZE		0x04000000	/* 64 MB */
+#define CONFIG_SYS_MAX_FLASH_SECT	1024
+#define CONFIG_SYS_MAX_FLASH_BANKS	1
+#define CONFIG_SYS_FLASH_BANKS_LIST	{ (CONFIG_SYS_FLASH_BASE) }
+#define	CONFIG_SYS_FLASH_BANKS_SIZES	{ (CONFIG_SYS_FLASH_SIZE) }
+#define CONFIG_SYS_FLASH_ERASE_TOUT	3000
+#define CONFIG_SYS_FLASH_WRITE_TOUT	3000
+#define CONFIG_SYS_FLASH_LOCK_TOUT	3000
+#define CONFIG_SYS_FLASH_UNLOCK_TOUT	3000
+/* ENV setting */
+#define CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + \
+				 CONFIG_SYS_MONITOR_LEN)
+
+#else /* CONFIG_SYS_USE_BOOT_NORFLASH */
+
+#define CONFIG_SYS_NO_FLASH
+#define CONFIG_SPI
+#define CONFIG_SH_QSPI
+#define CONFIG_SPI_FLASH
+#define CONFIG_SPI_FLASH_BAR
+#define CONFIG_SPI_FLASH_SPANSION
+/* ENV setting */
+#define CONFIG_ENV_IS_IN_SPI_FLASH
+#define CONFIG_ENV_ADDR	0xC0000
+
+#endif /* CONFIG_SYS_USE_BOOT_NORFLASH */
+
+/* Common ENV setting */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_ENV_SECT_SIZE	(256 * 1024)
+#define CONFIG_ENV_OFFSET	(CONFIG_ENV_ADDR)
+#define CONFIG_ENV_SIZE		(CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE_REDUND	(CONFIG_SYS_MONITOR_LEN)
+
+/* SH Ether */
+#define	CONFIG_NET_MULTI
+#define CONFIG_SH_ETHER
+#define CONFIG_SH_ETHER_USE_PORT	0
+#define CONFIG_SH_ETHER_PHY_ADDR	0x1
+#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII
+#define CONFIG_SH_ETHER_CACHE_WRITEBACK
+#define CONFIG_SH_ETHER_CACHE_INVALIDATE
+#define CONFIG_PHYLIB
+#define CONFIG_PHY_MICREL
+#define CONFIG_BITBANGMII
+#define CONFIG_BITBANGMII_MULTI
+#define CONFIG_SH_ETHER_ALIGNE_SIZE 64
+
+/* Board Clock */
+#define	CONFIG_SYS_CLK_FREQ	10000000
+#define CONFIG_SH_TMU_CLK_FREQ	CONFIG_SYS_CLK_FREQ
+#define CONFIG_SH_SCIF_CLK_FREQ	14745600
+#define CONFIG_SYS_TMU_CLK_DIV	4
+
+/* i2c */
+#define CONFIG_CMD_I2C
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_SH
+#define CONFIG_SYS_I2C_SLAVE	0x7F
+#define CONFIG_SYS_I2C_SH_NUM_CONTROLLERS	3
+#define CONFIG_SYS_I2C_SH_BASE0		0xE6500000
+#define CONFIG_SYS_I2C_SH_SPEED0	400000
+#define CONFIG_SYS_I2C_SH_BASE1		0xE6510000
+#define CONFIG_SYS_I2C_SH_SPEED1	400000
+#define CONFIG_SYS_I2C_SH_BASE2		0xE60B0000
+#define CONFIG_SYS_I2C_SH_SPEED2	400000
+#define CONFIG_SH_I2C_DATA_HIGH	4
+#define CONFIG_SH_I2C_DATA_LOW	5
+#define CONFIG_SH_I2C_CLOCK	10000000
+
+#define CONFIG_SYS_I2C_POWERIC_ADDR 0x58 /* da9063 */
+
+#endif	/* __KOELSCH_H */
diff --git a/include/configs/korat.h b/include/configs/korat.h
index 7c7a305175..5494a6007d 100644
--- a/include/configs/korat.h
+++ b/include/configs/korat.h
@@ -22,7 +22,6 @@
  * High Level Configuration Options
  */
 #define CONFIG_440EPX		1	/* Specific PPC440EPx		*/
-#define CONFIG_4xx		1	/* ... PPC4xx family		*/
 #define CONFIG_SYS_CLK_FREQ	33333333
 
 #ifdef CONFIG_KORAT_PERMANENT
@@ -307,7 +306,6 @@
  * Miscellaneous configurable options
  */
 #define CONFIG_SYS_LONGHELP			/* undef to save memory		*/
-#define CONFIG_SYS_PROMPT	        "=> "	/* Monitor Command Prompt	*/
 #if defined(CONFIG_CMD_KGDB)
 #define CONFIG_SYS_CBSIZE	        1024	/* Console I/O Buffer Size	*/
 #else
@@ -324,8 +322,6 @@
 #define CONFIG_SYS_LOAD_ADDR		0x100000  /* default load address	*/
 #define CONFIG_SYS_EXTBDINFO		1  /* To use extended board_into (bd_t)	*/
 
-#define CONFIG_SYS_HZ		        1000	/* decrementer freq: 1 ms ticks	*/
-
 #define CONFIG_CMDLINE_EDITING	1	/* add command line history	*/
 #define CONFIG_LOOPW		1	/* enable loopw command		*/
 #define CONFIG_MX_CYCLIC	1	/* enable mdc/mwc commands	*/
@@ -545,7 +541,6 @@
 
 #if defined(CONFIG_CMD_KGDB)
 #define CONFIG_KGDB_BAUDRATE	230400 /* speed to run kgdb serial port	*/
-#define CONFIG_KGDB_SER_INDEX	2	/* which serial port to use	*/
 #endif
 
 /* Pass open firmware flat tree */
diff --git a/include/configs/kvme080.h b/include/configs/kvme080.h
index 23270e68f5..c352a1c804 100644
--- a/include/configs/kvme080.h
+++ b/include/configs/kvme080.h
@@ -8,7 +8,6 @@
 #ifndef __CONFIG_H
 #define __CONFIG_H
 
-#define CONFIG_MPC824X		1
 #define CONFIG_MPC8245		1
 #define CONFIG_KVME080		1
 
@@ -86,7 +85,6 @@
 #define CONFIG_NETCONSOLE
 
 #define CONFIG_SYS_LONGHELP
-#define CONFIG_SYS_PROMPT		"=> "
 #define CONFIG_SYS_CBSIZE		256
 #define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
 #define CONFIG_SYS_MAXARGS		16
@@ -96,7 +94,6 @@
 #define CONFIG_SYS_MEMTEST_END		0x07C00000
 
 #define CONFIG_SYS_LOAD_ADDR		0x00100000
-#define CONFIG_SYS_HZ			1000
 
 #define CONFIG_SYS_INIT_RAM_ADDR	0x40000000
 #define CONFIG_SYS_INIT_RAM_SIZE	0x1000
diff --git a/include/configs/kwb.h b/include/configs/kwb.h
new file mode 100644
index 0000000000..0f631c0f60
--- /dev/null
+++ b/include/configs/kwb.h
@@ -0,0 +1,128 @@
+/*
+ * kwb.h
+ *
+ * specific parts for B&R KWB Motherboard
+ *
+ * Copyright (C) 2013 Hannes Petermaier <oe5hpm@oevsv.at> -
+ * Bernecker & Rainer Industrieelektronik GmbH - http://www.br-automation.com
+ *
+ * SPDX-License-Identifier:        GPL-2.0+
+ */
+
+#ifndef __CONFIG_KWB_H__
+#define __CONFIG_KWB_H__
+
+#include <configs/bur_am335x_common.h>
+/* ------------------------------------------------------------------------- */
+/* Clock Defines */
+#define V_OSCK				26000000  /* Clock output from T2 */
+#define V_SCLK				(V_OSCK)
+
+#define CONFIG_POWER_TPS65217
+
+#define CONFIG_MACH_TYPE		3589
+/* I2C IP block */
+#define CONFIG_SYS_OMAP24_I2C_SPEED_PSOC	20000
+
+/* GPIO */
+#define CONFIG_SPL_GPIO_SUPPORT
+
+/* MMC/SD IP block */
+#define CONFIG_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_OMAP_HSMMC
+#define CONFIG_CMD_MMC
+#define CONFIG_SUPPORT_EMMC_BOOT
+/* RAW SD card / eMMC locations. */
+#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR	0x300 /*addr. 0x60000 */
+#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS		0x200 /* 256 KB */
+#define CONFIG_SPL_MMC_SUPPORT
+
+#undef CONFIG_SPL_OS_BOOT
+#ifdef CONFIG_SPL_OS_BOOT
+#define CONFIG_SYS_SPL_ARGS_ADDR		0x80F80000
+
+/* RAW SD card / eMMC */
+#define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR	0x900	/* address 0x120000 */
+#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR	0x80	/* address 0x10000 */
+#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS	0x80	/* 64KiB */
+
+#endif /* CONFIG_SPL_OS_BOOT */
+
+/* Always 128 KiB env size */
+#define CONFIG_ENV_SIZE			(128 << 10)
+
+#ifndef CONFIG_SPL_BUILD
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"autoload=0\0" \
+	"loadaddr=0x80100000\0" \
+	"bootfile=arimg\0" \
+	"usbboot=echo Booting from USB-Stick ...; " \
+		"usb start; " \
+		"fatload usb 0 ${loadaddr} ${bootfile}; " \
+		"usb stop; " \
+		"go ${loadaddr};\0" \
+	"netboot=echo Booting from network ...; " \
+		"setenv autoload 0; " \
+		"dhcp; " \
+		"tftp ${loadaddr} arimg; " \
+		"go ${loadaddr}\0" \
+	"usbupdate=echo Updating UBOOT from USB-Stick ...; " \
+		"usb start; " \
+		"fatload usb 0 0x80000000 updateubootusb.img; " \
+		"source;\0" \
+	"netupdate=echo Updating UBOOT from Network (TFTP) ...; " \
+		"setenv autoload 0; " \
+		"dhcp;" \
+		"tftp 0x80000000 updateUBOOT.img;" \
+		"source;\0"
+#endif /* !CONFIG_SPL_BUILD*/
+
+#define CONFIG_BOOTCOMMAND \
+	"run usbupdate;"
+#define CONFIG_BOOTDELAY		1 /* TODO: für release auf 0 setzen */
+
+/* undefine command which we not need here */
+#undef	CONFIG_BOOTM_LINUX
+#undef	CONFIG_BOOTM_NETBSD
+#undef	CONFIG_BOOTM_PLAN9
+#undef	CONFIG_BOOTM_RTEMS
+#undef	CONFIG_GZIP
+#undef	CONFIG_ZLIB
+#undef CONFIG_CMD_CRC32
+
+/* USB configuration */
+#define CONFIG_USB_MUSB_DSPS
+#define CONFIG_ARCH_MISC_INIT
+#define CONFIG_MUSB_PIO_ONLY
+#define CONFIG_MUSB_DISABLE_BULK_COMBINE_SPLIT
+/* attention! not only for gadget, enables also highspeed in hostmode */
+#define CONFIG_USB_GADGET_DUALSPEED
+#define CONFIG_MUSB_HOST
+#define CONFIG_AM335X_USB0
+#define CONFIG_AM335X_USB0_MODE	MUSB_HOST
+
+#ifdef CONFIG_MUSB_HOST
+#define CONFIG_CMD_USB
+#define CONFIG_USB_STORAGE
+#endif /* CONFIG_MUSB_HOST */
+
+#undef CONFIG_ENV_IS_NOWHERE
+#define CONFIG_ENV_IS_IN_MMC
+#define CONFIG_SYS_MMC_ENV_DEV		1
+#define CONFIG_SYS_MMC_ENV_PART		2
+#define CONFIG_ENV_OFFSET		0x40000	/* TODO: Adresse definieren */
+#define CONFIG_ENV_OFFSET_REDUND	(CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
+#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
+/*
+ * Common filesystems support.  When we have removable storage we
+ * enabled a number of useful commands and support.
+ */
+#if defined(CONFIG_MMC) || defined(CONFIG_USB_STORAGE)
+#define CONFIG_DOS_PARTITION
+#define CONFIG_CMD_FAT
+#define CONFIG_FAT_WRITE
+#define CONFIG_CMD_FS_GENERIC
+#endif /* CONFIG_MMC, ... */
+
+#endif	/* ! __CONFIG_TSERIES_H__ */
diff --git a/include/configs/kzm9g.h b/include/configs/kzm9g.h
index 222725cd1f..5a13ad1139 100644
--- a/include/configs/kzm9g.h
+++ b/include/configs/kzm9g.h
@@ -15,6 +15,7 @@
 #define CONFIG_KZM_A9_GT
 #define CONFIG_RMOBILE_BOARD_STRING	"KMC KZM-A9-GT"
 #define CONFIG_MACH_TYPE MACH_TYPE_KZM9G
+#define CONFIG_SYS_GENERIC_BOARD
 
 #include <asm/arch/rmobile.h>
 
@@ -22,7 +23,6 @@
 #define CONFIG_DISPLAY_CPUINFO
 #define CONFIG_DISPLAY_BOARDINFO
 #define CONFIG_BOARD_EARLY_INIT_F
-#define CONFIG_L2_OFF
 #define CONFIG_OF_LIBFDT
 
 #include <config_cmd_default.h>
@@ -89,7 +89,6 @@
 
 #define CONFIG_SYS_MONITOR_BASE	(KZM_FLASH_BASE)
 #define CONFIG_SYS_MALLOC_LEN	(CONFIG_ENV_SIZE + 128 * 1024)
-#define CONFIG_SYS_GBL_DATA_SIZE	(256)
 #define CONFIG_SYS_BOOTMAPSZ	(8 * 1024 * 1024)
 
 #define CONFIG_SYS_TEXT_BASE		0x00000000
@@ -125,9 +124,8 @@
 #define CONFIG_GLOBAL_TIMER
 #define CONFIG_SYS_CLK_FREQ	(48000000)
 #define CONFIG_SYS_CPU_CLK	(1196000000)
+#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
 #define TMU_CLK_DIVIDER		(4)	/* 4 (default), 16, 64, 256 or 1024 */
-#define CFG_HZ              (1000)
-#define CONFIG_SYS_HZ		CFG_HZ
 
 /* Ether */
 #define CONFIG_NET_MULTI
@@ -140,21 +138,22 @@
 
 /* I2C */
 #define CONFIG_CMD_I2C
-#define CONFIG_SH_I2C 1
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_SH
+#define CONFIG_SYS_I2C_SH_NUM_CONTROLLERS 5
+#define CONFIG_SYS_I2C_SH_BASE0	0xE6820000
+#define CONFIG_SYS_I2C_SH_SPEED0	100000
+#define CONFIG_SYS_I2C_SH_BASE1	0xE6822000
+#define CONFIG_SYS_I2C_SH_SPEED1	100000
+#define CONFIG_SYS_I2C_SH_BASE2	0xE6824000
+#define CONFIG_SYS_I2C_SH_SPEED2	100000
+#define CONFIG_SYS_I2C_SH_BASE3	0xE6826000
+#define CONFIG_SYS_I2C_SH_SPEED3	100000
+#define CONFIG_SYS_I2C_SH_BASE4	0xE6828000
+#define CONFIG_SYS_I2C_SH_SPEED4	100000
 #define CONFIG_SH_I2C_8BIT
-#define CONFIG_HARD_I2C
-#define CONFIG_I2C_MULTI_BUS
-#define CONFIG_SYS_MAX_I2C_BUS  (5)
-#define CONFIG_SYS_I2C_MODULE
-#define CONFIG_SYS_I2C_SPEED    (100000) /* 100 kHz */
-#define CONFIG_SYS_I2C_SLAVE    (0x7F)
-#define CONFIG_SH_I2C_DATA_HIGH (4)
-#define CONFIG_SH_I2C_DATA_LOW  (5)
-#define CONFIG_SH_I2C_CLOCK     (104000000) /* 104 MHz */
-#define CONFIG_SH_I2C_BASE0     (0xE6820000)
-#define CONFIG_SH_I2C_BASE1     (0xE6822000)
-#define CONFIG_SH_I2C_BASE2     (0xE6824000)
-#define CONFIG_SH_I2C_BASE3     (0xE6826000)
-#define CONFIG_SH_I2C_BASE4     (0xE6828000)
+#define CONFIG_SH_I2C_DATA_HIGH 4
+#define CONFIG_SH_I2C_DATA_LOW  5
+#define CONFIG_SH_I2C_CLOCK     104000000 /* 104 MHz */
 
 #endif /* __KZM9G_H */
diff --git a/include/configs/lacie_kw.h b/include/configs/lacie_kw.h
index f6e79ba350..2d2e23a2a9 100644
--- a/include/configs/lacie_kw.h
+++ b/include/configs/lacie_kw.h
@@ -80,9 +80,9 @@
  * from the Network Space v2
  */
 #if defined(CONFIG_INETSPACE_V2)
-#define CONFIG_SYS_KWD_CONFIG $(SRCTREE)/$(CONFIG_BOARDDIR)/kwbimage-is2.cfg
+#define CONFIG_SYS_KWD_CONFIG $(CONFIG_BOARDDIR)/kwbimage-is2.cfg
 #elif defined(CONFIG_NETSPACE_LITE_V2) || defined(CONFIG_NETSPACE_MINI_V2)
-#define CONFIG_SYS_KWD_CONFIG $(SRCTREE)/$(CONFIG_BOARDDIR)/kwbimage-ns2l.cfg
+#define CONFIG_SYS_KWD_CONFIG $(CONFIG_BOARDDIR)/kwbimage-ns2l.cfg
 #endif
 
 /*
diff --git a/include/configs/lager.h b/include/configs/lager.h
new file mode 100644
index 0000000000..b420e45e63
--- /dev/null
+++ b/include/configs/lager.h
@@ -0,0 +1,199 @@
+/*
+ * include/configs/lager.h
+ *     This file is lager board configuration.
+ *
+ * Copyright (C) 2013 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#ifndef __LAGER_H
+#define __LAGER_H
+
+#undef DEBUG
+#define CONFIG_ARMV7
+#define CONFIG_R8A7790
+#define CONFIG_RMOBILE
+#define CONFIG_RMOBILE_BOARD_STRING "Lager"
+#define CONFIG_SH_GPIO_PFC
+#define MACH_TYPE_LAGER		4538
+#define CONFIG_MACH_TYPE	MACH_TYPE_LAGER
+
+#include <asm/arch/rmobile.h>
+
+#define	CONFIG_CMD_EDITENV
+#define	CONFIG_CMD_SAVEENV
+#define CONFIG_CMD_MEMORY
+#define CONFIG_CMD_DFL
+#define CONFIG_CMD_SDRAM
+#define CONFIG_CMD_RUN
+#define CONFIG_CMD_LOADS
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_BOOTZ
+
+#if defined(CONFIG_SYS_USE_BOOT_NORFLASH)
+#define CONFIG_CMD_FLASH
+#define CONFIG_SYS_TEXT_BASE	0x00000000
+#else
+#define CONFIG_CMD_SF
+#define CONFIG_CMD_SPI
+#define CONFIG_SYS_TEXT_BASE	0xE8080000
+#endif
+
+#define	CONFIG_CMDLINE_TAG
+#define	CONFIG_SETUP_MEMORY_TAGS
+#define	CONFIG_INITRD_TAG
+#define	CONFIG_CMDLINE_EDITING
+#define	CONFIG_OF_LIBFDT
+
+/* #define CONFIG_OF_LIBFDT */
+#define BOARD_LATE_INIT
+
+#define CONFIG_BAUDRATE		38400
+#define CONFIG_BOOTDELAY	3
+#define CONFIG_BOOTARGS		""
+
+#define CONFIG_VERSION_VARIABLE
+#undef	CONFIG_SHOW_BOOT_PROGRESS
+
+#define CONFIG_ARCH_CPU_INIT
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DISPLAY_BOARDINFO
+#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_USE_ARCH_MEMSET
+#define CONFIG_USE_ARCH_MEMCPY
+#define CONFIG_TMU_TIMER
+
+/* STACK */
+#define CONFIG_SYS_INIT_SP_ADDR		0xE827fffc
+#define STACK_AREA_SIZE				0xC000
+#define LOW_LEVEL_MERAM_STACK	\
+		(CONFIG_SYS_INIT_SP_ADDR + STACK_AREA_SIZE - 4)
+
+/* MEMORY */
+#define LAGER_SDRAM_BASE	0x40000000
+#define LAGER_SDRAM_SIZE	(2048u * 1024 * 1024)
+#define LAGER_UBOOT_SDRAM_SIZE	(512 * 1024 * 1024)
+
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_SYS_CBSIZE		256
+#define CONFIG_SYS_PBSIZE		256
+#define CONFIG_SYS_MAXARGS		16
+#define CONFIG_SYS_BARGSIZE		512
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 38400, 115200 }
+
+/* SCIF */
+#define CONFIG_SCIF_CONSOLE
+#define CONFIG_CONS_SCIF0
+#define SCIF0_BASE		0xe6e60000
+#undef	CONFIG_SYS_CONSOLE_INFO_QUIET
+#undef	CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
+#undef	CONFIG_SYS_CONSOLE_ENV_OVERWRITE
+
+#define CONFIG_SYS_MEMTEST_START	(LAGER_SDRAM_BASE)
+#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_MEMTEST_START + \
+					 504 * 1024 * 1024)
+#undef	CONFIG_SYS_ALT_MEMTEST
+#undef	CONFIG_SYS_MEMTEST_SCRATCH
+#undef	CONFIG_SYS_LOADS_BAUD_CHANGE
+
+#define CONFIG_SYS_SDRAM_BASE		(LAGER_SDRAM_BASE)
+#define CONFIG_SYS_SDRAM_SIZE		(LAGER_UBOOT_SDRAM_SIZE)
+#define CONFIG_SYS_LOAD_ADDR		(CONFIG_SYS_SDRAM_BASE + 0x7fc0)
+#define CONFIG_NR_DRAM_BANKS		1
+
+#define CONFIG_SYS_MONITOR_BASE		0x00000000
+#define CONFIG_SYS_MONITOR_LEN		(256 * 1024)
+#define CONFIG_SYS_MALLOC_LEN		(1 * 1024 * 1024)
+#define CONFIG_SYS_BOOTMAPSZ		(8 * 1024 * 1024)
+
+#if defined(CONFIG_SYS_USE_BOOT_NORFLASH)
+/* USE NOR FLASH */
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_16BIT
+#define	CONFIG_FLASH_CFI_DRIVER
+#define	CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
+#define	CONFIG_FLASH_SHOW_PROGRESS	45
+#define CONFIG_SYS_FLASH_BASE		0x00000000
+#define	CONFIG_SYS_FLASH_SIZE		0x04000000	/* 64 MB */
+#define CONFIG_SYS_MAX_FLASH_SECT	1024
+#define CONFIG_SYS_MAX_FLASH_BANKS	1
+#define CONFIG_SYS_FLASH_BANKS_LIST	{ (CONFIG_SYS_FLASH_BASE) }
+#define	CONFIG_SYS_FLASH_BANKS_SIZES	{ (CONFIG_SYS_FLASH_SIZE) }
+#define CONFIG_SYS_FLASH_ERASE_TOUT	3000
+#define CONFIG_SYS_FLASH_WRITE_TOUT	3000
+#define CONFIG_SYS_FLASH_LOCK_TOUT	3000
+#define CONFIG_SYS_FLASH_UNLOCK_TOUT	3000
+
+/* ENV setting */
+#define CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + \
+				 CONFIG_SYS_MONITOR_LEN)
+
+#else /* CONFIG_SYS_USE_BOOT_NORFLASH */
+
+/* USE SPI */
+#define CONFIG_SPI
+#define CONFIG_SPI_FLASH_BAR
+#define CONFIG_SH_QSPI
+#define CONFIG_SPI_FLASH
+#define CONFIG_SPI_FLASH_SPANSION
+#define CONFIG_SYS_NO_FLASH
+
+/* ENV setting */
+#define CONFIG_ENV_IS_IN_SPI_FLASH
+#define CONFIG_ENV_ADDR	0xC0000
+#endif
+
+/* Common ENV setting */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_ENV_SECT_SIZE	(256 * 1024)
+#define CONFIG_ENV_OFFSET	(CONFIG_ENV_ADDR)
+#define CONFIG_ENV_SIZE		(CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE_REDUND	(CONFIG_SYS_MONITOR_LEN)
+
+/* SH Ether */
+#define	CONFIG_NET_MULTI
+#define CONFIG_SH_ETHER
+#define CONFIG_SH_ETHER_USE_PORT	0
+#define CONFIG_SH_ETHER_PHY_ADDR	0x1
+#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII
+#define CONFIG_SH_ETHER_ALIGNE_SIZE	64
+#define CONFIG_SH_ETHER_CACHE_WRITEBACK
+#define CONFIG_SH_ETHER_CACHE_INVALIDATE
+#define CONFIG_PHYLIB
+#define CONFIG_PHY_MICREL
+#define CONFIG_BITBANGMII
+#define CONFIG_BITBANGMII_MULTI
+
+/* I2C */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_RCAR
+#define CONFIG_SYS_RCAR_I2C0_BASE	0xE6508000
+#define CONFIG_SYS_RCAR_I2C0_SPEED	400000
+#define CONFIG_SYS_RCAR_I2C1_BASE	0xE6518000
+#define CONFIG_SYS_RCAR_I2C1_SPEED	400000
+#define CONFIG_SYS_RCAR_I2C2_BASE	0xE6530000
+#define CONFIG_SYS_RCAR_I2C2_SPEED	400000
+#define CONFIG_SYS_RCAR_I2C3_BASE	0xE6540000
+#define CONFIG_SYS_RCAR_I2C3_SPEED	400000
+#define CONFIF_SYS_RCAR_I2C_NUM_CONTROLLERS	4
+
+#define CONFIG_SYS_I2C_POWERIC_ADDR 0x58 /* da9063 */
+
+/* Board Clock */
+#define CONFIG_BASE_CLK_FREQ	20000000u
+#define CONFIG_SH_TMU_CLK_FREQ	(CONFIG_BASE_CLK_FREQ / 2) /* EXT / 2 */
+#define CONFIG_PLL1_CLK_FREQ	(CONFIG_BASE_CLK_FREQ * 156 / 2)
+#define CONFIG_PLL1_DIV2_CLK_FREQ	(CONFIG_PLL1_CLK_FREQ / 2)
+#define CONFIG_MP_CLK_FREQ	(CONFIG_PLL1_DIV2_CLK_FREQ / 15)
+#define CONFIG_HP_CLK_FREQ	(CONFIG_PLL1_CLK_FREQ / 12)
+#define CONFIG_SH_SCIF_CLK_FREQ	CONFIG_MP_CLK_FREQ
+
+#define CONFIG_SYS_TMU_CLK_DIV	4
+
+#endif	/* __LAGER_H */
diff --git a/include/configs/linkstation.h b/include/configs/linkstation.h
deleted file mode 100644
index 1bd467f59f..0000000000
--- a/include/configs/linkstation.h
+++ /dev/null
@@ -1,506 +0,0 @@
-/*
- * Copyright (C) 2006 Mihai Georgian <u-boot@linuxnotincluded.org.uk>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * Valid values for CONFIG_SYS_TEXT_BASE are:
- *
- * Standard configuration - all models
- * 0xFFF00000	boot from flash
- *
- * Test configuration (boot from RAM using uloader.o)
- * LinkStation HD-HLAN and KuroBox Standard
- * 0x03F00000	boot from RAM
- * LinkStation HD-HGLAN and KuroBox HG
- * 0x07F00000	boot from RAM
- */
-#ifndef CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_TEXT_BASE	0xFFF00000
-#endif
-
-#if 0
-#define DEBUG
-#endif
-
-#define CONFIG_BOARD_EARLY_INIT_F 1	/* Call board_early_init_f	*/
-
-/*-----------------------------------------------------------------------
- * User configurable settings:
- *   Mandatory settings:
- *     CONFIG_IPADDR_LS		- the IP address of the LinkStation
- *     CONFIG_SERVERIP_LS	- the address of the server for NFS/TFTP/DHCP/BOOTP
- *   Optional settins:
- *     CONFIG_NCIP_LS		- the adress of the computer running net console
- *							  if not configured, it will be set to
- *							  CONFIG_SERVERIP_LS
- */
-
-
-#define CONFIG_IPADDR_LS	192.168.11.150
-#define CONFIG_SERVERIP_LS	192.168.11.149
-
-#if !defined(CONFIG_IPADDR_LS) || !defined(CONFIG_SERVERIP_LS)
-#error Both CONFIG_IPADDR_LS and CONFIG_SERVERIP_LS must be defined
-#endif
-
-#if !defined(CONFIG_NCIP_LS)
-#define CONFIG_NCIP_LS		CONFIG_SERVERIP_LS
-#endif
-
-/*----------------------------------------------------------------------
- * DO NOT CHANGE ANYTHING BELOW, UNLESS YOU KNOW WHAT YOU ARE DOING
- *---------------------------------------------------------------------*/
-
-#define CONFIG_MPC8245		1
-#define CONFIG_LINKSTATION	1
-
-/*---------------------------------------
- * Supported models
- *
- * LinkStation HDLAN /KuroBox Standard (CONFIG_HLAN)
- * LinkStation old model               (CONFIG_LAN) - totally untested
- * LinkStation HGLAN / KuroBox HG      (CONFIG_HGLAN)
- *
- * Models not supported yet
- * TeraStatin                          (CONFIG_HTGL)
- */
-
-#if defined(CONFIG_HLAN) || defined(CONFIG_LAN)
-#define CONFIG_IDENT_STRING		" LinkStation / KuroBox"
-#elif defined(CONFIG_HGLAN)
-#define CONFIG_IDENT_STRING		" LinkStation HG / KuroBox HG"
-#elif defined(CONFIG_HTGL)
-#define CONFIG_IDENT_STRING		" TeraStation"
-#else
-#error No LinkStation model defined
-#endif
-
-#define CONFIG_BOOTDELAY	5
-#define CONFIG_ZERO_BOOTDELAY_CHECK
-#undef CONFIG_BOOT_RETRY_TIME
-
-#define CONFIG_AUTOBOOT_KEYED
-#define CONFIG_AUTOBOOT_PROMPT		\
-	"Boot in %02d seconds ('s' to stop)...", bootdelay
-#define CONFIG_AUTOBOOT_STOP_STR	"s"
-
-#define CONFIG_CMD_IDE
-#define CONFIG_CMD_PCI
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_EXT2
-
-#define CONFIG_BOOTP_SUBNETMASK
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-#define CONFIG_BOOTP_NISDOMAIN
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_DNS
-#define CONFIG_BOOTP_DNS2
-#define CONFIG_BOOTP_SEND_HOSTNAME
-#define CONFIG_BOOTP_NTPSERVER
-#define CONFIG_BOOTP_TIMEOFFSET
-
-#define CONFIG_OF_LIBFDT	1
-
-#define OF_STDOUT_PATH		"/soc10x/serial@80004600"
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <config_cmd_default.h>
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP				/* undef to save memory		*/
-#define CONFIG_SYS_PROMPT		"=> "		/* Monitor Command Prompt	*/
-#define CONFIG_SYS_CBSIZE		256		/* Console I/O Buffer Size	*/
-
-#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
-#define CONFIG_SYS_MAXARGS		16		/* Max number of command args	*/
-#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
-#define CONFIG_SYS_LOAD_ADDR		0x00800000	/* Default load address: 8 MB	*/
-
-#define CONFIG_BOOTCOMMAND	"run bootcmd1"
-#define CONFIG_BOOTARGS		"root=/dev/sda1 console=ttyS1,57600 netconsole=@192.168.1.7/eth0,@192.168.1.1/00:50:BF:A4:59:71 rtc-rs5c372.probe=0,0x32 debug"
-#define CONFIG_NFSBOOTCOMMAND	"bootp;run nfsargs;bootm"
-
-#define CONFIG_SYS_CONSOLE_IS_IN_ENV
-
-#if defined(CONFIG_HLAN) || defined(CONFIG_LAN)
-#define UBFILE			"share/u-boot/u-boot-hd.flash.bin"
-#elif defined(CONFIG_HGLAN)
-#define UBFILE			"share/u-boot/u-boot-hg.flash.bin"
-#elif defined(CONFIG_HTGL)
-#define UBFILE			"share/u-boot/u-boot-ht.flash.bin"
-#else
-#error No LinkStation model defined
-#endif
-
-#define CONFIG_EXTRA_ENV_SETTINGS						\
-	"autoload=no\0"								\
-	"stdin=nc\0"								\
-	"stdout=nc\0"								\
-	"stderr=nc\0"								\
-	"ipaddr="__stringify(CONFIG_IPADDR_LS)"\0"			\
-	"netmask=255.255.255.0\0"						\
-	"serverip="__stringify(CONFIG_SERVERIP_LS)"\0"			\
-	"ncip="__stringify(CONFIG_NCIP_LS)"\0"				\
-	"netretry=no\0"								\
-	"nc=setenv stdin nc;setenv stdout nc;setenv stderr nc\0"		\
-	"ser=setenv stdin serial;setenv stdout serial;setenv stderr serial\0"	\
-	"ldaddr=800000\0"							\
-	"hdpart=0:1\0"								\
-	"hdfile=boot/uImage\0"							\
-	"hdload=echo Loading ${hdpart}:${hdfile};ext2load ide ${hdpart} ${ldaddr} ${hdfile};ext2load ide ${hdpart} 7f0000 boot/kuroboxHG.dtb\0"	\
-	"boothd=setenv bootargs " CONFIG_BOOTARGS ";bootm ${ldaddr} - 7f0000\0"	\
-	"hdboot=run hdload;run boothd\0"					\
-	"flboot=setenv bootargs root=/dev/hda1;bootm ffc00000\0"		\
-	"emboot=setenv bootargs root=/dev/ram0;bootm ffc00000\0"		\
-	"nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} "	\
-	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off\0"	\
-	"bootretry=30\0"							\
-	"bootcmd1=run hdboot;run flboot\0"					\
-	"bootcmd2=run flboot\0"							\
-	"bootcmd3=run emboot\0"							\
-	"writeng=protect off fff70000 fff7ffff;era fff70000 fff7ffff;mw.l 800000 4e474e47 1;cp.b 800000 fff70000 4\0" \
-	"writeok=protect off fff70000 fff7ffff;era fff70000 fff7ffff;mw.l 800000 4f4b4f4b 1;cp.b 800000 fff70000 4\0" \
-	"ubpart=0:3\0"								\
-	"ubfile="UBFILE"\0"							\
-	"ubload=echo Loading ${ubpart}:${ubfile};ext2load ide ${ubpart} ${ldaddr} ${ubfile}\0" \
-	"ubsaddr=fff00000\0"							\
-	"ubeaddr=fff2ffff\0"							\
-	"ubflash=protect off ${ubsaddr} ${ubeaddr};era ${ubsaddr} ${ubeaddr};cp.b ${ldaddr} ${ubsaddr} ${filesize};cmp.b ${ldaddr} ${ubsaddr} ${filesize}\0" \
-	"upgrade=run ubload ubflash\0"
-
-/*-----------------------------------------------------------------------
- * PCI stuff
- */
-#define CONFIG_PCI
-#define CONFIG_PCI_INDIRECT_BRIDGE
-/* Verified: CONFIG_PCI_PNP doesn't work */
-#undef CONFIG_PCI_PNP
-#define CONFIG_PCI_SCAN_SHOW
-
-#ifndef CONFIG_PCI_PNP
-/* Keep the following defines in sync with the BAT mappings */
-
-#define PCI_ETH_IOADDR      0xbfff00
-#define PCI_ETH_MEMADDR     0xbffffc00
-#define PCI_IDE_IOADDR      0xbffed0
-#define PCI_IDE_MEMADDR     0xbffffb00
-#define PCI_USB0_IOADDR     0
-#define PCI_USB0_MEMADDR    0xbfffe000
-#define PCI_USB1_IOADDR     0
-#define PCI_USB1_MEMADDR    0xbfffd000
-#define PCI_USB2_IOADDR     0
-#define PCI_USB2_MEMADDR    0xbfffcf00
-
-#endif
-
-/*-----------------------------------------------------------------------
- * Ethernet stuff
- */
-
-#if defined(CONFIG_LAN) || defined(CONFIG_HLAN)
-#define CONFIG_TULIP
-#define CONFIG_TULIP_USE_IO
-#elif defined(CONFIG_HGLAN) || defined(CONFIG_HTGL)
-#define CONFIG_RTL8169
-#endif
-
-#define CONFIG_NET_RETRY_COUNT		5
-
-#define CONFIG_NETCONSOLE
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
- */
-#define CONFIG_SYS_SDRAM_BASE		0x00000000
-
-#define CONFIG_SYS_FLASH_BASE		0xFFC00000
-#define CONFIG_SYS_FLASH_SIZE		0x00400000
-#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE
-
-#define CONFIG_SYS_RESET_ADDRESS	0xFFF00100
-#define CONFIG_SYS_EUMB_ADDR		0x80000000
-#define CONFIG_SYS_PCI_MEM_ADDR	0xB0000000
-#define CONFIG_SYS_MISC_REGION_ADDR	0xFE000000
-
-#define CONFIG_SYS_MONITOR_LEN		0x00040000	/* 256 kB			*/
-#define CONFIG_SYS_MALLOC_LEN		(512 << 10)	/* Reserve some kB for malloc()	*/
-
-#define CONFIG_SYS_MEMTEST_START	0x00100000	/* memtest works on		*/
-#define CONFIG_SYS_MEMTEST_END		0x00800000	/* 1M ... 8M in DRAM		*/
-
-/* Maximum amount of RAM */
-#if defined(CONFIG_HLAN) || defined(CONFIG_LAN)
-#define CONFIG_SYS_MAX_RAM_SIZE	0x04000000	/* 64MB of SDRAM  */
-#elif defined(CONFIG_HGLAN) || defined(CONFIG_HTGL)
-#define CONFIG_SYS_MAX_RAM_SIZE	0x08000000	/* 128MB of SDRAM */
-#else
-#error Unknown LinkStation type
-#endif
-
-/*-----------------------------------------------------------------------
- * Change CONFIG_SYS_TEXT_BASE in bord/linkstation/config.mk to get a RAM build
- *
- * RAM based builds are for testing purposes. A Linux module, uloader.o,
- * exists to load U-Boot and pass control to it
- *
- * Always do "make clean" after changing the build type
- */
-#if CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_RAMBOOT
-#endif
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area
- */
-#if 1 /* RAM is available when the first C function is called */
-#define CONFIG_SYS_INIT_RAM_ADDR	(CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_MAX_RAM_SIZE - 0x1000)
-#else
-#define CONFIG_SYS_INIT_RAM_ADDR	0x40000000
-#endif
-#define CONFIG_SYS_INIT_RAM_SIZE	0x1000
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-
-/*----------------------------------------------------------------------
- * Serial configuration
- */
-#define CONFIG_CONS_INDEX	1
-#define CONFIG_BAUDRATE		57600
-
-#define CONFIG_SYS_NS16550
-#define CONFIG_SYS_NS16550_SERIAL
-
-#define CONFIG_SYS_NS16550_REG_SIZE	1
-
-#define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)
-
-#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_EUMB_ADDR + 0x4600)	/* Console port	*/
-#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_EUMB_ADDR + 0x4500)	/* AVR port	*/
-
-/*
- * Low Level Configuration Settings
- * (address mappings, register initial values, etc.)
- * You should know what you are doing if you make changes here.
- * For the detail description refer to the MPC8245 user's manual.
- *
- * Unless indicated otherwise, the values are
- * taken from the orignal Linkstation boot code
- *
- * Most of the low level configuration setttings are normally used
- * in arch/powerpc/cpu/mpc824x/cpu_init.c which is NOT used by this implementation.
- * Low level initialisation is done in board/linkstation/early_init.S
- * The values below are included for reference purpose only
- */
-
-/* FIXME: 32.768 MHz is the crystal frequency but */
-/* the real frequency is lower by about 0.75%     */
-#define CONFIG_SYS_CLK_FREQ	32768000
-#define CONFIG_SYS_HZ			1000
-
-/* Bit-field values for MCCR1.  */
-#define CONFIG_SYS_ROMNAL      0
-#define CONFIG_SYS_ROMFAL      11
-
-#define CONFIG_SYS_BANK0_ROW	2       /* Only bank 0 used: 13 x n x 4 */
-#define CONFIG_SYS_BANK1_ROW	0
-#define CONFIG_SYS_BANK2_ROW	0
-#define CONFIG_SYS_BANK3_ROW	0
-#define CONFIG_SYS_BANK4_ROW	0
-#define CONFIG_SYS_BANK5_ROW	0
-#define CONFIG_SYS_BANK6_ROW	0
-#define CONFIG_SYS_BANK7_ROW	0
-
-/* Bit-field values for MCCR2.  */
-#define CONFIG_SYS_TSWAIT      0
-#if defined(CONFIG_LAN) || defined(CONFIG_HLAN)
-#define CONFIG_SYS_REFINT      0x15e0
-#elif defined(CONFIG_HGLAN) || defined(CONFIG_HTGL)
-#define CONFIG_SYS_REFINT      0x1580
-#endif
-
-/* Burst To Precharge. Bits of this value go to MCCR3 and MCCR4. */
-#define CONFIG_SYS_BSTOPRE	0x91c
-
-/* Bit-field values for MCCR3.  */
-#define CONFIG_SYS_REFREC      7
-
-/* Bit-field values for MCCR4.  */
-#define CONFIG_SYS_PRETOACT		2
-#define CONFIG_SYS_ACTTOPRE		2	/* Original value was 2	*/
-#define CONFIG_SYS_ACTORW		2
-#if defined(CONFIG_LAN) || defined(CONFIG_HLAN)
-#define CONFIG_SYS_SDMODE_CAS_LAT	2	/* For 100MHz bus	*/
-/*#define CONFIG_SYS_SDMODE_BURSTLEN	3*/
-#elif defined(CONFIG_HGLAN) || defined(CONFIG_HTGL)
-#define CONFIG_SYS_SDMODE_CAS_LAT	3	/* For 133MHz bus	*/
-/*#define CONFIG_SYS_SDMODE_BURSTLEN	2*/
-#endif
-#define CONFIG_SYS_REGISTERD_TYPE_BUFFER 1
-#define CONFIG_SYS_EXTROM		1	/* Original setting but there is no EXTROM */
-#define CONFIG_SYS_REGDIMM		0
-#define CONFIG_SYS_DBUS_SIZE2		1
-#define CONFIG_SYS_SDMODE_WRAP		0
-
-#define CONFIG_SYS_PGMAX		0x32	/* All boards use this setting. Original 0x92 */
-#define CONFIG_SYS_SDRAM_DSCD		0x30
-
-/* Memory bank settings.
- * Only bits 20-29 are actually used from these vales to set the
- * start/end addresses. The upper two bits will always be 0, and the lower
- * 20 bits will be 0x00000 for a start address, or 0xfffff for an end
- * address. Refer to the MPC8240 book.
- */
-
-#define CONFIG_SYS_BANK0_START	    0x00000000
-#define CONFIG_SYS_BANK0_END	    (CONFIG_SYS_MAX_RAM_SIZE - 1)
-#define CONFIG_SYS_BANK0_ENABLE    1
-#define CONFIG_SYS_BANK1_START     0x3ff00000
-#define CONFIG_SYS_BANK1_END       0x3fffffff
-#define CONFIG_SYS_BANK1_ENABLE    0
-#define CONFIG_SYS_BANK2_START     0x3ff00000
-#define CONFIG_SYS_BANK2_END       0x3fffffff
-#define CONFIG_SYS_BANK2_ENABLE    0
-#define CONFIG_SYS_BANK3_START     0x3ff00000
-#define CONFIG_SYS_BANK3_END       0x3fffffff
-#define CONFIG_SYS_BANK3_ENABLE    0
-#define CONFIG_SYS_BANK4_START     0x3ff00000
-#define CONFIG_SYS_BANK4_END       0x3fffffff
-#define CONFIG_SYS_BANK4_ENABLE    0
-#define CONFIG_SYS_BANK5_START     0x3ff00000
-#define CONFIG_SYS_BANK5_END       0x3fffffff
-#define CONFIG_SYS_BANK5_ENABLE    0
-#define CONFIG_SYS_BANK6_START     0x3ff00000
-#define CONFIG_SYS_BANK6_END       0x3fffffff
-#define CONFIG_SYS_BANK6_ENABLE    0
-#define CONFIG_SYS_BANK7_START     0x3ff00000
-#define CONFIG_SYS_BANK7_END       0x3fffffff
-#define CONFIG_SYS_BANK7_ENABLE    0
-
-#define CONFIG_SYS_ODCR	    0x15
-
-/*----------------------------------------------------------------------
- * Initial BAT mappings
- */
-
-/* NOTES:
- * 1) GUARDED and WRITETHROUGH not allowed in IBATS
- * 2) CACHEINHIBIT and WRITETHROUGH not allowed together in same BAT
- */
-
-/* SDRAM */
-#define CONFIG_SYS_IBAT0L	(CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT0U	(CONFIG_SYS_SDRAM_BASE | BATU_BL_128M | BATU_VS | BATU_VP)
-
-#define CONFIG_SYS_DBAT0L	CONFIG_SYS_IBAT0L
-#define CONFIG_SYS_DBAT0U	CONFIG_SYS_IBAT0U
-
-/* EUMB: 1MB of address space */
-#define CONFIG_SYS_IBAT1L	(CONFIG_SYS_EUMB_ADDR | BATL_PP_10 | BATL_CACHEINHIBIT)
-#define CONFIG_SYS_IBAT1U	(CONFIG_SYS_EUMB_ADDR | BATU_BL_1M | BATU_VS | BATU_VP)
-
-#define CONFIG_SYS_DBAT1L	(CONFIG_SYS_IBAT1L | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_DBAT1U	CONFIG_SYS_IBAT1U
-
-/* PCI Mem: 256MB of address space */
-#define CONFIG_SYS_IBAT2L	(CONFIG_SYS_PCI_MEM_ADDR | BATL_PP_10 | BATL_CACHEINHIBIT)
-#define CONFIG_SYS_IBAT2U	(CONFIG_SYS_PCI_MEM_ADDR | BATU_BL_256M | BATU_VS | BATU_VP)
-
-#define CONFIG_SYS_DBAT2L	(CONFIG_SYS_IBAT2L | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_DBAT2U	CONFIG_SYS_IBAT2U
-
-/* PCI and local ROM/Flash: last 32MB of address space */
-#define CONFIG_SYS_IBAT3L	(CONFIG_SYS_MISC_REGION_ADDR | BATL_PP_10 | BATL_CACHEINHIBIT)
-#define CONFIG_SYS_IBAT3U	(CONFIG_SYS_MISC_REGION_ADDR | BATU_BL_32M | BATU_VS | BATU_VP)
-
-#define CONFIG_SYS_DBAT3L	(CONFIG_SYS_IBAT3L | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_DBAT3U	CONFIG_SYS_IBAT3U
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- *
- * FIXME: This doesn't appear to be true for the newer kernels
- * which map more that 8 MB
- */
-#define CONFIG_SYS_BOOTMAPSZ	(8 << 20)	/* Initial Memory map for Linux */
-
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-#define CONFIG_SYS_FLASH_CFI			/* The flash is CFI compatible	*/
-#define CONFIG_FLASH_CFI_DRIVER		/* Use common CFI driver	*/
-
-#undef  CONFIG_SYS_FLASH_PROTECTION
-#define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH_BASE }
-#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* Max number of flash banks		*/
-#define CONFIG_SYS_MAX_FLASH_SECT	72	/* Max number of sectors per flash	*/
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT	12000
-#define CONFIG_SYS_FLASH_WRITE_TOUT	1000
-
-#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1	/* use buffered writes (20x faster)	*/
-
-#define CONFIG_SYS_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
-#define CONFIG_SYS_FLASH_QUIET_TEST	1	/* don't warn upon unknown flash	*/
-
-#define CONFIG_ENV_IS_IN_FLASH
-/*
- * The original LinkStation flash organisation uses
- * 448 kB (0xFFF00000 - 0xFFF6FFFF) for the boot loader
- * We use the last sector of this area to store the environment
- * which leaves max. 384 kB for the U-Boot itself
- */
-#define CONFIG_ENV_ADDR		0xFFF60000
-#define CONFIG_ENV_SIZE		0x00010000
-#define CONFIG_ENV_SECT_SIZE	0x00010000
-
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CONFIG_SYS_CACHELINE_SIZE	32
-#ifdef CONFIG_CMD_KGDB
-#define CONFIG_SYS_CACHELINE_SHIFT	5	/* log base 2 of the above value	*/
-#endif
-
-/*-----------------------------------------------------------------------
- * IDE/ATA definitions
- */
-#undef  CONFIG_IDE_LED				/* No IDE LED			*/
-#define CONFIG_IDE_RESET			/* no reset for ide supported	*/
-#define CONFIG_IDE_PREINIT			/* check for units		*/
-#define CONFIG_LBA48				/* 48 bit LBA supported		*/
-
-#if defined(CONFIG_LAN) || defined(CONFIG_HLAN) || defined(CONFIG_HGLAN)
-#define CONFIG_SYS_IDE_MAXBUS		1		/* Scan only 1 IDE bus		*/
-#define CONFIG_SYS_IDE_MAXDEVICE	1		/* Only 1 drive per IDE bus	*/
-#elif defined(CONFIG_HGTL)
-#define CONFIG_SYS_IDE_MAXBUS		2		/* Max. 2 IDE busses		*/
-#define CONFIG_SYS_IDE_MAXDEVICE	2		/* max. 2 drives per IDE bus	*/
-#else
-#error Config IDE: Unknown LinkStation type
-#endif
-
-#define CONFIG_SYS_ATA_BASE_ADDR	0
-
-#define CONFIG_SYS_ATA_DATA_OFFSET	0		/* Offset for data I/O		*/
-#define CONFIG_SYS_ATA_REG_OFFSET	0		/* Offset for normal registers	*/
-#define CONFIG_SYS_ATA_ALT_OFFSET	0		/* Offset for alternate registers */
-
-/*-----------------------------------------------------------------------
- * Partitions and file system
- */
-#define CONFIG_DOS_PARTITION
-
-#endif	/* __CONFIG_H */
diff --git a/include/configs/lp8x4x.h b/include/configs/lp8x4x.h
index 6df6f2b464..a26937265a 100644
--- a/include/configs/lp8x4x.h
+++ b/include/configs/lp8x4x.h
@@ -20,18 +20,18 @@
 #define	CONFIG_SYS_MALLOC_LEN		(128*1024)
 #define	CONFIG_ARCH_CPU_INIT
 #define	CONFIG_BOOTCOMMAND		\
-	"bootm 80000;"
+	"bootm 80000 - 240000;"
 
 #define	CONFIG_BOOTARGS			\
-	"console=ttySA0,115200 mem=128M root=/dev/mmcblk0p1 rw" \
-	"init=/sbin/init rootfstype=ext3"
+	"console=ttyS0,115200 mem=128M root=/dev/mmcblk0p1 rw" \
+	"init=/sbin/init rootfstype=ext4 rootwait"
 
 #define	CONFIG_TIMESTAMP
 #define	CONFIG_BOOTDELAY		2	/* Autoboot delay */
 #define	CONFIG_CMDLINE_TAG
 #define	CONFIG_SETUP_MEMORY_TAGS
 #define	CONFIG_LZMA			/* LZMA compression support */
-#undef	CONFIG_OF_LIBFDT
+#define	CONFIG_OF_LIBFDT
 
 /*
  * Serial Console Configuration
@@ -93,7 +93,6 @@
  */
 #ifdef	CONFIG_CMD_KGDB
 #define	CONFIG_KGDB_BAUDRATE		230400	/* kgdb serial port speed */
-#define	CONFIG_KGDB_SER_INDEX		2	/* which serial port to use */
 #endif
 
 /*
@@ -101,11 +100,10 @@
  */
 #define	CONFIG_SYS_HUSH_PARSER		1
 
-#undef	CONFIG_SYS_LONGHELP
+#define	CONFIG_SYS_LONGHELP
 #ifdef	CONFIG_SYS_HUSH_PARSER
 #define	CONFIG_SYS_PROMPT		"$ "
 #else
-#define	CONFIG_SYS_PROMPT		"=> "
 #endif
 #define	CONFIG_SYS_CBSIZE		256
 #define	CONFIG_SYS_PBSIZE		\
@@ -117,11 +115,6 @@
 #define	CONFIG_AUTO_COMPLETE		1
 
 /*
- * Clock Configuration
- */
-#define	CONFIG_SYS_HZ			1000		/* Timer @ 3250000 Hz */
-
-/*
  * DRAM Map
  */
 #define	CONFIG_NR_DRAM_BANKS		1		/* 1 bank of DRAM */
@@ -150,7 +143,7 @@
 #define	CONFIG_ENV_SECT_SIZE		0x40000
 
 #define	PHYS_FLASH_1			0x00000000	/* Flash Bank #1 */
-#define	PHYS_FLASH_2			0x02000000	/* Flash Bank #2 */
+#define	PHYS_FLASH_2			0x04000000	/* Flash Bank #2 */
 
 #define	CONFIG_SYS_FLASH_CFI
 #define	CONFIG_FLASH_CFI_DRIVER		1
@@ -190,7 +183,7 @@
 #define	CONFIG_SYS_GAFR1_L_VAL	0x999a955a
 #define	CONFIG_SYS_GAFR1_U_VAL	0xaaa5a00a
 #define	CONFIG_SYS_GAFR2_L_VAL	0xaaaaaaaa
-#define	CONFIG_SYS_GAFR2_U_VAL	0x55f0a402
+#define	CONFIG_SYS_GAFR2_U_VAL	0x55f9a402
 #define	CONFIG_SYS_GAFR3_L_VAL	0x540a950c
 #define	CONFIG_SYS_GAFR3_U_VAL	0x00001599
 
@@ -238,7 +231,6 @@
  */
 #ifdef	CONFIG_CMD_USB
 #define	CONFIG_USB_OHCI_NEW
-#define	CONFIG_SYS_USB_OHCI_CPU_INIT
 #define	CONFIG_SYS_USB_OHCI_BOARD_INIT
 #define	CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS	2
 #define	CONFIG_SYS_USB_OHCI_REGS_BASE	0x4C000000
diff --git a/include/configs/lsxl.h b/include/configs/lsxl.h
index 52d8377a1b..96a889fe87 100644
--- a/include/configs/lsxl.h
+++ b/include/configs/lsxl.h
@@ -13,12 +13,12 @@
  */
 #if defined(CONFIG_LSCHLV2)
 #define CONFIG_IDENT_STRING " LS-CHLv2"
-#define CONFIG_SYS_KWD_CONFIG $(SRCTREE)/$(CONFIG_BOARDDIR)/kwbimage-lschl.cfg
+#define CONFIG_SYS_KWD_CONFIG $(CONFIG_BOARDDIR)/kwbimage-lschl.cfg
 #define CONFIG_MACH_TYPE 3006
 #define CONFIG_SYS_TCLK 166666667 /* 166 MHz */
 #elif defined(CONFIG_LSXHL)
 #define CONFIG_IDENT_STRING " LS-XHL"
-#define CONFIG_SYS_KWD_CONFIG $(SRCTREE)/$(CONFIG_BOARDDIR)/kwbimage-lsxhl.cfg
+#define CONFIG_SYS_KWD_CONFIG $(CONFIG_BOARDDIR)/kwbimage-lsxhl.cfg
 #define CONFIG_MACH_TYPE 2663
 /* CONFIG_SYS_TCLK is 200000000 by default */
 #else
@@ -37,6 +37,7 @@
 #define CONFIG_SHOW_BOOT_PROGRESS
 
 #define CONFIG_RANDOM_MACADDR
+#define CONFIG_LIB_RAND
 #define CONFIG_KIRKWOOD_GPIO
 #define CONFIG_OF_LIBFDT
 
@@ -85,7 +86,6 @@
 
 
 #undef CONFIG_SYS_PROMPT
-#define CONFIG_SYS_PROMPT		"=> "
 #define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
 
 /*
diff --git a/include/configs/luan.h b/include/configs/luan.h
index 67f75c79a1..15e4a7e5c8 100644
--- a/include/configs/luan.h
+++ b/include/configs/luan.h
@@ -17,7 +17,6 @@
  *----------------------------------------------------------------------*/
 #define CONFIG_LUAN		1	/* Board is Luan		*/
 #define CONFIG_440SP		1	/* Specific PPC440SP support    */
-#define CONFIG_4xx		1	/* PPC4xx family	        */
 #define CONFIG_440		1
 #define CONFIG_SYS_CLK_FREQ	33333333 /* external freq to pll	*/
 
diff --git a/include/configs/lubbock.h b/include/configs/lubbock.h
index bab71f2aec..4ffe165dec 100644
--- a/include/configs/lubbock.h
+++ b/include/configs/lubbock.h
@@ -86,7 +86,6 @@
 
 #if defined(CONFIG_CMD_KGDB)
 #define CONFIG_KGDB_BAUDRATE	230400		/* speed to run kgdb serial port */
-#define CONFIG_KGDB_SER_INDEX	2		/* which serial port to use */
 #endif
 
 /*
@@ -98,7 +97,6 @@
 #ifdef CONFIG_SYS_HUSH_PARSER
 #define CONFIG_SYS_PROMPT		"$ "		/* Monitor Command Prompt */
 #else
-#define CONFIG_SYS_PROMPT		"=> "		/* Monitor Command Prompt */
 #endif
 #define CONFIG_SYS_CBSIZE		256		/* Console I/O Buffer Size	*/
 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
@@ -111,7 +109,6 @@
 
 #define CONFIG_SYS_LOAD_ADDR	(CONFIG_SYS_DRAM_BASE + 0x8000) /* default load address */
 
-#define CONFIG_SYS_HZ			1000
 #define CONFIG_SYS_CPUSPEED		0x161		/* set core clock to 400/200/100 MHz */
 
 #ifdef CONFIG_MMC
diff --git a/include/configs/lwmon.h b/include/configs/lwmon.h
index a2aa56bd2d..f204587336 100644
--- a/include/configs/lwmon.h
+++ b/include/configs/lwmon.h
@@ -193,7 +193,6 @@
  * Miscellaneous configurable options
  */
 #define CONFIG_SYS_LONGHELP			/* undef to save memory		*/
-#define CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt	*/
 
 #define	CONFIG_SYS_HUSH_PARSER		1	/* use "hush" command parser	*/
 
@@ -213,8 +212,6 @@
 
 #define CONFIG_SYS_PIO_MODE		0	/* IDE interface in PIO Mode 0	*/
 
-#define CONFIG_SYS_HZ			1000	/* decrementer freq: 1 ms ticks */
-
 /*
  * When the watchdog is enabled, output must be fast enough in Linux.
  */
diff --git a/include/configs/lwmon5.h b/include/configs/lwmon5.h
index 96f3ba5a13..07ddfc4014 100644
--- a/include/configs/lwmon5.h
+++ b/include/configs/lwmon5.h
@@ -22,7 +22,6 @@
 #define CONFIG_LWMON5		1		/* Board is lwmon5	*/
 #define CONFIG_440EPX		1		/* Specific PPC440EPx	*/
 #define CONFIG_440		1		/* ... PPC440 family	*/
-#define CONFIG_4xx		1		/* ... PPC4xx family	*/
 
 #ifdef CONFIG_LCD4_LWMON5
 #define	CONFIG_SYS_TEXT_BASE	0x01000000 /* SPL U-Boot TEXT_BASE */
@@ -463,7 +462,6 @@
 #define CONFIG_SUPPORT_VFAT
 
 #define CONFIG_SYS_LONGHELP			/* undef to save memory		*/
-#define CONFIG_SYS_PROMPT	        "=> "	/* Monitor Command Prompt	*/
 
 #define CONFIG_SYS_HUSH_PARSER		1	/* Use the HUSH parser		*/
 
@@ -482,8 +480,6 @@
 #define CONFIG_SYS_LOAD_ADDR		0x100000  /* default load address	*/
 #define CONFIG_SYS_EXTBDINFO		1	/* To use extended board_into (bd_t) */
 
-#define CONFIG_SYS_HZ		        1000	/* decrementer freq: 1 ms ticks	*/
-
 #define CONFIG_CMDLINE_EDITING	1	/* add command line history	*/
 #define CONFIG_LOOPW            1       /* enable loopw command         */
 #define CONFIG_MX_CYCLIC        1       /* enable mdc/mwc commands      */
@@ -663,7 +659,6 @@
 
 #if defined(CONFIG_CMD_KGDB)
 #define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
-#define CONFIG_KGDB_SER_INDEX	2	    /* which serial port to use */
 #endif
 
 /*
diff --git a/include/configs/m53evk.h b/include/configs/m53evk.h
index 024d3a5aaf..f401470251 100644
--- a/include/configs/m53evk.h
+++ b/include/configs/m53evk.h
@@ -10,7 +10,6 @@
 
 #define CONFIG_MX53
 #define CONFIG_MXC_GPIO
-#define CONFIG_SYS_HZ		1000
 
 #include <asm/arch/imx-regs.h>
 
@@ -38,19 +37,22 @@
 #define CONFIG_CMD_PING
 #define CONFIG_CMD_SATA
 #define CONFIG_CMD_USB
+#define CONFIG_VIDEO
+
+#define CONFIG_REGEX			/* Enable regular expression support */
 
 /*
  * Memory configurations
  */
 #define CONFIG_NR_DRAM_BANKS		2
 #define PHYS_SDRAM_1			CSD0_BASE_ADDR
-#define PHYS_SDRAM_1_SIZE		(512 * 1024 * 1024)
+#define PHYS_SDRAM_1_SIZE		(gd->bd->bi_dram[0].size)
 #define PHYS_SDRAM_2			CSD1_BASE_ADDR
-#define PHYS_SDRAM_2_SIZE		(512 * 1024 * 1024)
-#define PHYS_SDRAM_SIZE			(PHYS_SDRAM_1_SIZE + PHYS_SDRAM_2_SIZE)
+#define PHYS_SDRAM_2_SIZE		(gd->bd->bi_dram[1].size)
+#define PHYS_SDRAM_SIZE			(gd->ram_size)
 #define CONFIG_SYS_MALLOC_LEN		(10 * 1024 * 1024)
 #define CONFIG_SYS_MEMTEST_START	0x70000000
-#define CONFIG_SYS_MEMTEST_END		0xaff00000
+#define CONFIG_SYS_MEMTEST_END		0x8ff00000
 
 #define CONFIG_SYS_SDRAM_BASE		(PHYS_SDRAM_1)
 #define CONFIG_SYS_INIT_RAM_ADDR	(IRAM_BASE_ADDR)
@@ -67,7 +69,6 @@
  * U-Boot general configurations
  */
 #define CONFIG_SYS_LONGHELP
-#define CONFIG_SYS_PROMPT	"=> "
 #define CONFIG_SYS_CBSIZE	1024		/* Console I/O buffer size */
 #define CONFIG_SYS_PBSIZE	\
 	(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
@@ -129,9 +130,9 @@
 #define CONFIG_LZO
 #define CONFIG_MTD_DEVICE
 #define CONFIG_MTD_PARTITIONS
-#define MTDIDS_DEFAULT			"nand0=mxc-nand"
+#define MTDIDS_DEFAULT			"nand0=mxc_nand"
 #define MTDPARTS_DEFAULT			\
-	"mtdparts=mxc-nand:"			\
+	"mtdparts=mxc_nand:"			\
 		"1m(bootloader)ro,"		\
 		"512k(environment),"		\
 		"512k(redundant-environment),"	\
@@ -161,10 +162,9 @@
  * I2C
  */
 #ifdef CONFIG_CMD_I2C
-#define CONFIG_HARD_I2C
-#define CONFIG_I2C_MXC
-#define CONFIG_SYS_I2C_BASE		I2C2_BASE_ADDR
-#define CONFIG_SYS_I2C_SPEED		100000
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_SPD_BUS_NUM		1 /* I2C2 */
 #endif
 
 /*
@@ -185,6 +185,7 @@
 #define CONFIG_USB_STORAGE
 #define CONFIG_USB_HOST_ETHER
 #define CONFIG_USB_ETHER_ASIX
+#define CONFIG_USB_ETHER_MCS7830
 #define CONFIG_USB_ETHER_SMSC95XX
 #define CONFIG_MXC_USB_PORT		1
 #define CONFIG_MXC_USB_PORTSC		(PORT_PTS_UTMI | PORT_PTS_PTW)
@@ -204,6 +205,21 @@
 #endif
 
 /*
+ * LCD
+ */
+#ifdef CONFIG_VIDEO
+#define CONFIG_VIDEO_IPUV3
+#define CONFIG_CFB_CONSOLE
+#define CONFIG_VGA_AS_SINGLE_DEVICE
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV
+#define CONFIG_VIDEO_BMP_RLE8
+#define CONFIG_SPLASH_SCREEN
+#define CONFIG_BMP_16BPP
+#define CONFIG_VIDEO_LOGO
+#define CONFIG_IPUV3_CLK	200000000
+#endif
+
+/*
  * Boot Linux
  */
 #define CONFIG_CMDLINE_TAG
diff --git a/include/configs/makalu.h b/include/configs/makalu.h
index d6207eb11f..fd4c26eb94 100644
--- a/include/configs/makalu.h
+++ b/include/configs/makalu.h
@@ -19,7 +19,6 @@
  * High Level Configuration Options
  *----------------------------------------------------------------------*/
 #define CONFIG_MAKALU		1		/* Board is Makalu	*/
-#define CONFIG_4xx		1		/* ... PPC4xx family	*/
 #define CONFIG_405EX		1		/* Specifc 405EX support*/
 #define CONFIG_SYS_CLK_FREQ	33330000	/* ext frequency to pll	*/
 
diff --git a/include/configs/malta.h b/include/configs/malta.h
new file mode 100644
index 0000000000..cc574ed040
--- /dev/null
+++ b/include/configs/malta.h
@@ -0,0 +1,125 @@
+/*
+ * Copyright (C) 2013 Gabor Juhos <juhosg@openwrt.org>
+ *
+ * SPDX-License-Identifier:	GPL-2.0
+ */
+
+#ifndef _MALTA_CONFIG_H
+#define _MALTA_CONFIG_H
+
+#include <asm/addrspace.h>
+#include <asm/malta.h>
+
+/*
+ * System configuration
+ */
+#define CONFIG_MALTA
+
+#define CONFIG_MEMSIZE_IN_BYTES
+
+#define CONFIG_PCI
+#define CONFIG_PCI_GT64120
+#define CONFIG_PCI_MSC01
+#define CONFIG_PCI_PNP
+#define CONFIG_PCNET
+#define CONFIG_PCNET_79C973
+#define PCNET_HAS_PROM
+
+#define CONFIG_MISC_INIT_R
+#define CONFIG_RTC_MC146818
+#define CONFIG_SYS_ISA_IO_BASE_ADDRESS	0
+
+/*
+ * CPU Configuration
+ */
+#define CONFIG_SYS_MHZ			250	/* arbitrary value */
+#define CONFIG_SYS_MIPS_TIMER_FREQ	(CONFIG_SYS_MHZ * 1000000)
+
+#define CONFIG_SWAP_IO_SPACE
+
+/*
+ * Memory map
+ */
+#define CONFIG_SYS_TEXT_BASE		0xbe000000 /* Rom version */
+#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_TEXT_BASE
+
+#define CONFIG_SYS_SDRAM_BASE		0x80000000 /* Cached addr */
+#define CONFIG_SYS_MEM_SIZE		(256 * 1024 * 1024)
+
+#define CONFIG_SYS_INIT_SP_OFFSET	0x400000
+
+#define CONFIG_SYS_LOAD_ADDR		0x81000000
+#define CONFIG_SYS_MEMTEST_START	0x80100000
+#define CONFIG_SYS_MEMTEST_END		0x80800000
+
+#define CONFIG_SYS_MALLOC_LEN		(128 * 1024)
+#define CONFIG_SYS_BOOTPARAMS_LEN	(128 * 1024)
+#define CONFIG_SYS_BOOTM_LEN		(64 * 1024 * 1024)
+
+/*
+ * Console configuration
+ */
+#if defined(CONFIG_SYS_LITTLE_ENDIAN)
+#define CONFIG_SYS_PROMPT		"maltael # "
+#else
+#define CONFIG_SYS_PROMPT		"malta # "
+#endif
+
+#define CONFIG_SYS_CBSIZE		256
+#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
+					 sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS		16
+
+#define CONFIG_AUTO_COMPLETE
+#define CONFIG_CMDLINE_EDITING
+
+/*
+ * Serial driver
+ */
+#define CONFIG_BAUDRATE			115200
+
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	1
+#define CONFIG_SYS_NS16550_CLK		(115200 * 16)
+#define CONFIG_SYS_NS16550_COM1		CKSEG1ADDR(MALTA_GT_UART0_BASE)
+#define CONFIG_SYS_NS16550_COM2		CKSEG1ADDR(MALTA_MSC01_UART0_BASE)
+#define CONFIG_CONS_INDEX		1
+
+/*
+ * Flash configuration
+ */
+#define CONFIG_SYS_FLASH_BASE		(KSEG1 | MALTA_FLASH_BASE)
+#define CONFIG_SYS_MAX_FLASH_BANKS	1
+#define CONFIG_SYS_MAX_FLASH_SECT	128
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
+
+/*
+ * Environment
+ */
+#define CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_SECT_SIZE		0x20000
+#define CONFIG_ENV_SIZE			CONFIG_ENV_SECT_SIZE
+#define CONFIG_ENV_ADDR \
+	(CONFIG_SYS_FLASH_BASE + (4 << 20) - CONFIG_ENV_SIZE)
+
+/*
+ * Commands
+ */
+#include <config_cmd_default.h>
+
+#undef CONFIG_CMD_FPGA
+#undef CONFIG_CMD_LOADB
+#undef CONFIG_CMD_LOADS
+#undef CONFIG_CMD_NFS
+
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_PING
+
+#define CONFIG_SYS_LONGHELP		/* verbose help, undef to save memory */
+
+#endif /* _MALTA_CONFIG_H */
diff --git a/include/configs/manroland/common.h b/include/configs/manroland/common.h
index a55b39b4bf..ab4a4710c7 100644
--- a/include/configs/manroland/common.h
+++ b/include/configs/manroland/common.h
@@ -99,7 +99,6 @@
  * Miscellaneous configurable options
  */
 #define CONFIG_SYS_LONGHELP			/* undef to save memory	    */
-#define CONFIG_SYS_PROMPT		"=> "	/* Monitor Command Prompt   */
 #if defined(CONFIG_CMD_KGDB)
 #define CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size  */
 #else
diff --git a/include/configs/manroland/mpc5200-common.h b/include/configs/manroland/mpc5200-common.h
index 98bfcc5506..60e8716a79 100644
--- a/include/configs/manroland/mpc5200-common.h
+++ b/include/configs/manroland/mpc5200-common.h
@@ -12,8 +12,7 @@
  * High Level Configuration Options
  * (easy to change)
  */
-#define CONFIG_MPC5xxx		1	/* This is an MPC5xxx CPU		*/
-#define CONFIG_MPC5200		1	/* (more precisely an MPC5200 CPU)	*/
+#define CONFIG_MPC5200		1	/* MPC5200 CPU */
 
 #define CONFIG_SYS_MPC5XXX_CLKIN	33000000 /* ... running at 33.000000MHz	*/
 
@@ -143,8 +142,6 @@
 /*use  Hardware WDT */
 #define CONFIG_HW_WATCHDOG
 
-#define CONFIG_SYS_HZ			1000	/* decrementer freq: 1 ms ticks */
-
 #define CONFIG_SYS_CACHELINE_SIZE	32	/* For MPC5xxx CPUs		*/
 #if defined(CONFIG_CMD_KGDB)
 #  define CONFIG_SYS_CACHELINE_SHIFT	5	/* log base 2 of the above value*/
diff --git a/include/configs/mcc200.h b/include/configs/mcc200.h
index d73d2e4373..a317782dbe 100644
--- a/include/configs/mcc200.h
+++ b/include/configs/mcc200.h
@@ -14,8 +14,7 @@
  */
 
 #define CONFIG_MPC5200
-#define CONFIG_MPC5xxx		1	/* This is an MPC5xxx CPU		*/
-#define CONFIG_MCC200		1	/* ... on MCC200 board			*/
+#define CONFIG_MCC200		1	/* MCC200 board */
 
 /*
  * Valid values for CONFIG_SYS_TEXT_BASE are:
@@ -288,7 +287,6 @@
  * Miscellaneous configurable options
  */
 #define CONFIG_SYS_LONGHELP			/* undef to save memory		*/
-#define CONFIG_SYS_PROMPT		"=> "	/* Monitor Command Prompt	*/
 #if defined(CONFIG_CMD_KGDB)
 #define CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size	*/
 #else
@@ -303,8 +301,6 @@
 
 #define CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address */
 
-#define CONFIG_SYS_HZ			1000	/* decrementer freq: 1 ms ticks */
-
 #define CONFIG_SYS_CACHELINE_SIZE	32	/* For MPC5xxx CPUs			*/
 #if defined(CONFIG_CMD_KGDB)
 #  define CONFIG_SYS_CACHELINE_SHIFT	5	/* log base 2 of the above value	*/
diff --git a/include/configs/mcx.h b/include/configs/mcx.h
index 5e27ab2e4c..47244c0034 100644
--- a/include/configs/mcx.h
+++ b/include/configs/mcx.h
@@ -98,6 +98,7 @@
 
 /* EHCI */
 #define CONFIG_USB_STORAGE
+#define CONFIG_OMAP3_GPIO_2
 #define CONFIG_OMAP3_GPIO_5
 #define CONFIG_USB_EHCI
 #define CONFIG_USB_EHCI_OMAP
@@ -137,10 +138,10 @@
 #undef CONFIG_CMD_IMLS		/* List all found images	*/
 
 #define CONFIG_SYS_NO_FLASH
-#define CONFIG_HARD_I2C
-#define CONFIG_SYS_I2C_SPEED		100000
-#define CONFIG_SYS_I2C_SLAVE		1
-#define CONFIG_DRIVER_OMAP34XX_I2C
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_OMAP24_I2C_SPEED	100000
+#define CONFIG_SYS_OMAP24_I2C_SLAVE	1
+#define CONFIG_SYS_I2C_OMAP34XX
 
 /* RTC */
 #define CONFIG_RTC_DS1337
@@ -263,10 +264,9 @@
 			"${mtdparts} "					\
 			"vram=6M omapfb.vram=1:2M,2:2M,3:2M "		\
 			"omapdss.def_disp=lcd;"				\
-		"bootm 0x82000000 0x84000000\0"
-
-#define CONFIG_BOOTCOMMAND \
-	"run nandboot"
+		"bootm 0x82000000 0x84000000\0"				\
+	"bootcmd=mmc rescan;if fatload mmc 0 82000000 loadbootscr.scr;"	\
+		"then source 82000000;else run nandboot;fi\0"
 
 #define CONFIG_AUTO_COMPLETE
 #define CONFIG_CMDLINE_EDITING
@@ -303,7 +303,6 @@
  */
 #define CONFIG_SYS_TIMERBASE		OMAP34XX_GPT2
 #define CONFIG_SYS_PTV			2	/* Divisor: 2^(PTV+1) => 8 */
-#define CONFIG_SYS_HZ			1000
 
 /*
  * Physical Memory Map
@@ -322,7 +321,6 @@
 #define PISMO1_NAND_SIZE		GPMC_SIZE_128M
 
 #define CONFIG_NAND_OMAP_GPMC
-#define GPMC_NAND_ECC_LP_x16_LAYOUT
 #define CONFIG_ENV_IS_IN_NAND
 #define SMNAND_ENV_OFFSET		0x180000 /* environment starts here */
 
@@ -354,7 +352,6 @@
 #define CONFIG_SPL_FRAMEWORK
 #define CONFIG_SPL_BOARD_INIT
 #define CONFIG_SPL_NAND_SIMPLE
-#define CONFIG_SPL_NAND_SOFTECC
 
 #define CONFIG_SPL_LIBCOMMON_SUPPORT
 #define CONFIG_SPL_LIBDISK_SUPPORT
@@ -396,6 +393,8 @@
 					 56, 57, 58, 59, 60, 61, 62, 63}
 #define CONFIG_SYS_NAND_ECCSIZE		256
 #define CONFIG_SYS_NAND_ECCBYTES	3
+#define CONFIG_NAND_OMAP_ECCSCHEME	OMAP_ECC_HAM1_CODE_SW
+#define CONFIG_SPL_NAND_SOFTECC
 
 #define CONFIG_SYS_NAND_U_BOOT_START   CONFIG_SYS_TEXT_BASE
 
diff --git a/include/configs/mecp5123.h b/include/configs/mecp5123.h
index b48872b267..6c19817f86 100644
--- a/include/configs/mecp5123.h
+++ b/include/configs/mecp5123.h
@@ -29,7 +29,6 @@
  * High Level Configuration Options
  */
 #define CONFIG_E300		1	/* E300 Family */
-#define CONFIG_MPC512X		1	/* MPC512X family */
 
 #define	CONFIG_SYS_TEXT_BASE	0xFFF00000
 
@@ -327,7 +326,6 @@
  */
 #define CONFIG_SYS_LONGHELP			/* undef to save memory */
 #define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
-#define CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt */
 
 #ifdef CONFIG_CMD_KGDB
 # define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size */
@@ -343,8 +341,6 @@
 /* Boot Argument Buffer Size */
 #define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE
 
-#define CONFIG_SYS_HZ		1000
-
 /*
  * For booting Linux, the board info and command line data
  * have to be in the first 256 MB of memory, since this is
@@ -367,7 +363,6 @@
 
 #ifdef CONFIG_CMD_KGDB
 #define CONFIG_KGDB_BAUDRATE	230400	/* speed of kgdb serial port */
-#define CONFIG_KGDB_SER_INDEX	2	/* which serial port to use */
 #endif
 
 /*
diff --git a/include/configs/mecp5200.h b/include/configs/mecp5200.h
index 8b1e092208..b270429dd8 100644
--- a/include/configs/mecp5200.h
+++ b/include/configs/mecp5200.h
@@ -23,8 +23,7 @@
  * (easy to change)
  */
 
-#define CONFIG_MPC5200		1	/* This is an MPC5xxx CPU */
-#define CONFIG_MPC5xxx		1	/* This is an MPC5xxx CPU */
+#define CONFIG_MPC5200		1	/* This is an MPC5200 CPU */
 #define CONFIG_ICECUBE		1	/* ... on IceCube board */
 #define CONFIG_MECP5200		1	/* ... on MECP5200  board */
 #define CONFIG_MPC5200_DDR      1       /* ... use DDR RAM      */
@@ -235,7 +234,6 @@
  * Miscellaneous configurable options
  */
 #define CONFIG_SYS_LONGHELP			/* undef to save memory	    */
-#define CONFIG_SYS_PROMPT		"=> "	/* Monitor Command Prompt   */
 #if defined(CONFIG_CMD_KGDB)
 #define CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size  */
 #else
@@ -250,8 +248,6 @@
 
 #define CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address */
 
-#define CONFIG_SYS_HZ			1000		/* decrementer freq: 1 ms ticks */
-
 #define CONFIG_SYS_VXWORKS_MAC_PTR	0x00000000	/* Pass Ethernet MAC to VxWorks */
 
 #define CONFIG_SYS_CACHELINE_SIZE	32	/* For MPC5xxx CPUs */
diff --git a/include/configs/meesc.h b/include/configs/meesc.h
index d2ec83cd1f..86ce5f2397 100644
--- a/include/configs/meesc.h
+++ b/include/configs/meesc.h
@@ -40,7 +40,6 @@
 /* ARM asynchronous clock */
 #define CONFIG_SYS_AT91_SLOW_CLOCK	32768	/* 32.768 kHz crystal */
 #define CONFIG_SYS_AT91_MAIN_CLOCK	16000000/* 16.0 MHz crystal */
-#define CONFIG_SYS_HZ			1000	/* decrementer freq */
 
 /* Misc CPU related */
 #define CONFIG_SKIP_LOWLEVEL_INIT
@@ -144,8 +143,8 @@
 # define CONFIG_SYS_NAND_DBW_8
 # define CONFIG_SYS_NAND_MASK_ALE		(1 << 21)
 # define CONFIG_SYS_NAND_MASK_CLE		(1 << 22)
-# define CONFIG_SYS_NAND_ENABLE_PIN		AT91_PIO_PORTD, 15
-# define CONFIG_SYS_NAND_READY_PIN		AT91_PIO_PORTA, 22
+# define CONFIG_SYS_NAND_ENABLE_PIN		GPIO_PIN_PD(15)
+# define CONFIG_SYS_NAND_READY_PIN		GPIO_PIN_PA(22)
 #endif
 
 /* Ethernet */
@@ -157,6 +156,7 @@
 
 /* USB */
 #define CONFIG_USB_ATMEL
+#define CONFIG_USB_ATMEL_CLK_SEL_PLLB
 #define CONFIG_USB_OHCI_NEW
 #define CONFIG_DOS_PARTITION
 #define CONFIG_SYS_USB_OHCI_CPU_INIT
@@ -190,7 +190,6 @@
 
 #endif
 
-#define CONFIG_SYS_PROMPT		"=> "
 #define CONFIG_SYS_CBSIZE		512
 #define CONFIG_SYS_MAXARGS		16
 #define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
diff --git a/include/configs/microblaze-generic.h b/include/configs/microblaze-generic.h
index 0e3de777b2..486787e147 100644
--- a/include/configs/microblaze-generic.h
+++ b/include/configs/microblaze-generic.h
@@ -200,7 +200,8 @@
 # define CONFIG_SYS_MAX_FLASH_SECT	512
 /* hardware flash protection */
 # define CONFIG_SYS_FLASH_PROTECTION
-
+/* use buffered writes (20x faster) */
+# define	CONFIG_SYS_FLASH_USE_BUFFER_WRITE	1
 # ifdef	RAMENV
 #  define CONFIG_ENV_IS_NOWHERE	1
 #  define CONFIG_ENV_SIZE	0x1000
@@ -399,7 +400,6 @@
 
 /* architecture dependent code */
 #define	CONFIG_SYS_USR_EXCEP	/* user exception */
-#define CONFIG_SYS_HZ	1000
 
 #define	CONFIG_PREBOOT	"echo U-BOOT for ${hostname};setenv preboot;echo"
 
@@ -447,4 +447,64 @@
 # undef CONFIG_PHYLIB
 #endif
 
+/* SPL part */
+#define CONFIG_SPL
+#define CONFIG_CMD_SPL
+#define CONFIG_SPL_FRAMEWORK
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+#define CONFIG_SPL_LIBGENERIC_SUPPORT
+#define CONFIG_SPL_SERIAL_SUPPORT
+#define CONFIG_SPL_BOARD_INIT
+
+#define CONFIG_SPL_LDSCRIPT	"arch/microblaze/cpu/u-boot-spl.lds"
+
+#define CONFIG_SPL_RAM_DEVICE
+#define CONFIG_SPL_NOR_SUPPORT
+
+/* for booting directly linux */
+#define CONFIG_SPL_OS_BOOT
+
+#define CONFIG_SYS_OS_BASE		(CONFIG_SYS_FLASH_BASE + \
+					 0x60000)
+#define CONFIG_SYS_FDT_BASE		(CONFIG_SYS_FLASH_BASE + \
+					 0x40000)
+#define CONFIG_SYS_SPL_ARGS_ADDR	(CONFIG_SYS_TEXT_BASE + \
+					 0x1000000)
+
+/* SP location before relocation, must use scratch RAM */
+/* BRAM start */
+#define CONFIG_SYS_INIT_RAM_ADDR	0x0
+/* BRAM size - will be generated */
+#define CONFIG_SYS_INIT_RAM_SIZE	0x10000
+/* Stack pointer prior relocation, must situated at on-chip RAM */
+#define CONFIG_SYS_SPL_MALLOC_END	(CONFIG_SYS_INIT_RAM_ADDR + \
+					 CONFIG_SYS_INIT_RAM_SIZE - \
+					 GENERATED_GBL_DATA_SIZE)
+
+#define CONFIG_SYS_SPL_MALLOC_SIZE	0x100
+
+/*
+ * The main reason to do it in this way is that MALLOC_START
+ * can't be defined - common/spl/spl.c
+ */
+#if (CONFIG_SYS_SPL_MALLOC_SIZE != 0)
+# define CONFIG_SYS_SPL_MALLOC_START	(CONFIG_SYS_SPL_MALLOC_END - \
+					 CONFIG_SYS_SPL_MALLOC_SIZE)
+# define CONFIG_SPL_STACK_ADDR		CONFIG_SYS_SPL_MALLOC_START
+#else
+# define CONFIG_SPL_STACK_ADDR		CONFIG_SYS_SPL_MALLOC_END
+#endif
+
+/* Just for sure that there is a space for stack */
+#define CONFIG_SPL_STACK_SIZE		0x100
+
+#define CONFIG_SYS_UBOOT_BASE		CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_UBOOT_START		CONFIG_SYS_TEXT_BASE
+
+#define CONFIG_SPL_MAX_FOOTPRINT	(CONFIG_SYS_INIT_RAM_SIZE - \
+					 CONFIG_SYS_INIT_RAM_ADDR - \
+					 GENERATED_GBL_DATA_SIZE - \
+					 CONFIG_SYS_SPL_MALLOC_SIZE - \
+					 CONFIG_SPL_STACK_SIZE)
+
 #endif	/* __CONFIG_H */
diff --git a/include/configs/mimc200.h b/include/configs/mimc200.h
index 82f653ed5c..fc7ecfaee4 100644
--- a/include/configs/mimc200.h
+++ b/include/configs/mimc200.h
@@ -10,15 +10,12 @@
 
 #include <asm/arch/hardware.h>
 
-#define CONFIG_AVR32
 #define CONFIG_AT32AP
 #define CONFIG_AT32AP7000
 #define CONFIG_MIMC200
 
 #define CONFIG_MIMC200_EXT_FLASH
 
-#define CONFIG_SYS_HZ				1000
-
 /*
  * Set up the PLL to run at 140 MHz, the CPU to run at the PLL
  * frequency, the HSB and PBB busses to run at 1/2 the PLL frequency
diff --git a/include/configs/mini2440.h b/include/configs/mini2440.h
deleted file mode 100644
index 5e9e98d2fc..0000000000
--- a/include/configs/mini2440.h
+++ /dev/null
@@ -1,170 +0,0 @@
-/*
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- * Gary Jennejohn <gj@denx.de>
- * David Mueller <d.mueller@elsoft.ch>
- *
- * (C) Copyright 2009-2010
- * Michel Pollet <buserror@gmail.com>
- *
- * (C) Copyright 2012
- * Gabriel Huau <contact@huau-gabriel.fr>
- *
- * Configuation settings for the MINI2440 board.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#define CONFIG_SYS_TEXT_BASE 0x0
-#define CONFIG_S3C2440_GPIO
-
-/*
- * High Level Configuration Options
- */
-#define CONFIG_ARM920T			/* This is an ARM920T Core	*/
-#define CONFIG_S3C24X0			/* in a SAMSUNG S3C24X0 SoC */
-#define CONFIG_S3C2440			/* in a SAMSUNG S3C2440 SoC */
-#define CONFIG_MINI2440			/* on a MIN2440 Board       */
-
-#define MACH_TYPE_MINI2440	1999
-#define CONFIG_MACH_TYPE	MACH_TYPE_MINI2440
-
-/*
- * We don't use lowlevel_init
- */
-#define CONFIG_SKIP_LOWLEVEL_INIT
-#define CONFIG_BOARD_EARLY_INIT_F
-
-/*
- * input clock of PLL
- */
-/* MINI2440 has 12.0000MHz input clock */
-#define CONFIG_SYS_CLK_FREQ	12000000
-
-/*
- * Size of malloc() pool
- */
-#define CONFIG_SYS_MALLOC_LEN	(CONFIG_ENV_SIZE + 2048*1024)
-
-/*
- * Hardware drivers
- */
-#define CONFIG_DRIVER_DM9000
-#define CONFIG_DRIVER_DM9000_NO_EEPROM
-#define CONFIG_DM9000_BASE				0x20000300
-#define DM9000_IO		CONFIG_DM9000_BASE
-#define DM9000_DATA		(CONFIG_DM9000_BASE+4)
-
-/*
- * select serial console configuration
- */
-#define CONFIG_S3C24X0_SERIAL
-#define CONFIG_SERIAL1
-
-/*
- * allow to overwrite serial and ethaddr
- */
-#define CONFIG_ENV_OVERWRITE
-
-/*
- * Command definition
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_PORTIO
-#define CONFIG_CMD_REGINFO
-#define CONFIG_CMD_SAVES
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_LONGHELP
-#define CONFIG_SYS_PROMPT	"MINI2440 => "
-#define CONFIG_SYS_CBSIZE	256
-#define CONFIG_SYS_PBSIZE	(CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
-#define CONFIG_SYS_MAXARGS	32
-#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE
-
-#define CONFIG_SYS_MEMTEST_START	0x30000000
-#define CONFIG_SYS_MEMTEST_END		0x34000000	/* 64MB in DRAM	*/
-
-/* default load address	*/
-#define CONFIG_SYS_LOAD_ADDR		0x32000000
-
-/* boot parameters address */
-#define CONFIG_BOOT_PARAM_ADDR		0x30000100
-
-/*
- * the PWM TImer 4 uses a counter of 15625 for 10 ms, so we need
- * it to wrap 100 times (total 1562500) to get 1 sec.
- */
-#define CONFIG_SYS_HZ			1562500
-
-/*
- * valid baudrates
- */
-#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
-#define CONFIG_BAUDRATE		115200
-
-/*
- * Stack sizes
- * The stack sizes are set up in start.S using the settings below
- */
-#define CONFIG_STACKSIZE	(128*1024)	/* regular stack */
-#ifdef CONFIG_USE_IRQ
-#define CONFIG_STACKSIZE_IRQ	(8*1024)	/* IRQ stack */
-#define CONFIG_STACKSIZE_FIQ	(4*1024)	/* FIQ stack */
-#endif
-
-/*
- * Physical Memory Map
- */
-#define CONFIG_NR_DRAM_BANKS        1          /* we have 1 bank of DRAM */
-#define PHYS_SDRAM_SIZE             (64*1024*1024) /* 64MB of DRAM */
-#define CONFIG_SYS_SDRAM_BASE       0x30000000
-#define CONFIG_SYS_FLASH_BASE		0x0
-
-/*
- * Stack should be on the SRAM because
- * DRAM is not init
- */
-#define CONFIG_SYS_INIT_SP_ADDR		(0x40001000 - GENERATED_GBL_DATA_SIZE)
-
-/*
- * NOR FLASH organization
- * Now uses the standard CFI interface
- * FLASH and environment organization
- */
-#define CONFIG_SYS_FLASH_CFI
-#define CONFIG_FLASH_CFI_DRIVER
-#define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_16BIT
-#define CONFIG_SYS_MONITOR_BASE		0x0
-/* max number of memory banks */
-#define CONFIG_SYS_MAX_FLASH_BANKS	1
-/* 512 * 4096 sectors, or 32 * 64k blocks */
-#define CONFIG_SYS_MAX_FLASH_SECT	512
-#define CONFIG_FLASH_SHOW_PROGRESS  1
-
-/*
- * Config for NOR flash
- */
-#define CONFIG_ENV_IS_IN_FLASH
-#define CONFIG_MY_ENV_OFFSET	0x40000
-/* addr of environment */
-#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + CONFIG_MY_ENV_OFFSET)
-/* 16k Total Size of Environment Sector */
-#define CONFIG_ENV_SIZE		0x4000
-
-/* ATAG configuration */
-#define CONFIG_INITRD_TAG
-#define CONFIG_SETUP_MEMORY_TAGS
-#define CONFIG_CMDLINE_TAG
-#define CONFIG_CMDLINE_EDITING
-#define CONFIG_AUTO_COMPLETE
-
-#endif	/* __CONFIG_H */
diff --git a/include/configs/motionpro.h b/include/configs/motionpro.h
index 2a81849875..e8b05932a1 100644
--- a/include/configs/motionpro.h
+++ b/include/configs/motionpro.h
@@ -15,8 +15,7 @@
  */
 
 /* CPU and board */
-#define CONFIG_MPC5xxx		1	/* This is an MPC5xxx CPU */
-#define CONFIG_MPC5200		1	/* More exactly a MPC5200 */
+#define CONFIG_MPC5200		1	/* This is a MPC5200 CPU */
 #define CONFIG_MOTIONPRO	1	/* ... on Promess Motion-PRO board */
 
 #define CONFIG_HIGH_BATS	1	/* High BATs supported */
@@ -368,7 +367,6 @@ extern void __led_set(led_id_t id, int state);
  * Miscellaneous configurable options
  */
 #define CONFIG_SYS_LONGHELP			/* undef to save memory    */
-#define CONFIG_SYS_PROMPT		"=> "	/* Monitor Command Prompt   */
 #define CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size */
 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)	/* Print Buffer Size */
 #define CONFIG_SYS_MAXARGS		16		/* max number of command args */
@@ -380,8 +378,6 @@ extern void __led_set(led_id_t id, int state);
 
 #define CONFIG_SYS_LOAD_ADDR		0x200000	/* default kernel load addr */
 
-#define CONFIG_SYS_HZ			1000	/* decrementer freq: 1 ms ticks */
-
 /*
  * Various low-level settings
  */
diff --git a/include/configs/mpc5121ads.h b/include/configs/mpc5121ads.h
index 2af947a231..7de245b33c 100644
--- a/include/configs/mpc5121ads.h
+++ b/include/configs/mpc5121ads.h
@@ -29,7 +29,6 @@
  * High Level Configuration Options
  */
 #define CONFIG_E300		1	/* E300 Family */
-#define CONFIG_MPC512X		1	/* MPC512X family */
 
 #define	CONFIG_SYS_TEXT_BASE	0xFFF00000
 
@@ -486,7 +485,6 @@
  */
 #define CONFIG_SYS_LONGHELP			/* undef to save memory */
 #define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
-#define CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt */
 
 #ifdef CONFIG_CMD_KGDB
 	#define CONFIG_SYS_CBSIZE	1024	/* Console I/O Buffer Size */
@@ -498,7 +496,6 @@
 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) /* Print Buffer Size */
 #define CONFIG_SYS_MAXARGS	16		/* max number of command args */
 #define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size */
-#define CONFIG_SYS_HZ		1000		/* decrementer freq: 1ms ticks */
 
 /*
  * For booting Linux, the board info and command line data
@@ -522,7 +519,6 @@
 
 #ifdef CONFIG_CMD_KGDB
 #define CONFIG_KGDB_BAUDRATE	230400	/* speed of kgdb serial port */
-#define CONFIG_KGDB_SER_INDEX	2	/* which serial port to use */
 #endif
 
 /*
diff --git a/include/configs/mpc7448hpc2.h b/include/configs/mpc7448hpc2.h
index 37cc4349f6..0308c52bc7 100644
--- a/include/configs/mpc7448hpc2.h
+++ b/include/configs/mpc7448hpc2.h
@@ -169,7 +169,6 @@
 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		1	/* Bytes of address */
 
 #define CONFIG_SYS_LONGHELP		/* undef to save memory */
-#define CONFIG_SYS_PROMPT	"=> "	/* Monitor Command Prompt */
 
 #if defined(CONFIG_CMD_KGDB)
 #define CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size */
@@ -187,8 +186,6 @@
 
 #define CONFIG_SYS_LOAD_ADDR	0x00400000	/* default load address */
 
-#define CONFIG_SYS_HZ		1000		/* decr freq: 1ms ticks */
-
 /*
  * Low Level Configuration Settings
  * (address mappings, register initial values, etc.)
diff --git a/include/configs/mpc8308_p1m.h b/include/configs/mpc8308_p1m.h
index 6875cf4c5b..4ae9afd4e5 100644
--- a/include/configs/mpc8308_p1m.h
+++ b/include/configs/mpc8308_p1m.h
@@ -13,7 +13,6 @@
  * High Level Configuration Options
  */
 #define CONFIG_E300		1 /* E300 family */
-#define CONFIG_MPC83xx		1 /* MPC83xx family */
 #define CONFIG_MPC830x		1 /* MPC830x family */
 #define CONFIG_MPC8308		1 /* MPC8308 CPU specific */
 #define CONFIG_MPC8308_P1M	1 /* mpc8308_p1m board specific */
@@ -412,7 +411,6 @@
  */
 #define CONFIG_SYS_LONGHELP		/* undef to save memory */
 #define CONFIG_SYS_LOAD_ADDR		0x2000000 /* default load address */
-#define CONFIG_SYS_PROMPT		"=> "	/* Monitor Command Prompt */
 
 #define CONFIG_SYS_CBSIZE	1024 /* Console I/O Buffer Size */
 
@@ -421,7 +419,6 @@
 #define CONFIG_SYS_MAXARGS	16	/* max number of command args */
 /* Boot Argument Buffer Size */
 #define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE
-#define CONFIG_SYS_HZ		1000	/* decrementer freq: 1ms ticks */
 
 /*
  * For booting Linux, the board info and command line data
diff --git a/include/configs/mpq101.h b/include/configs/mpq101.h
deleted file mode 100644
index 55d93da598..0000000000
--- a/include/configs/mpq101.h
+++ /dev/null
@@ -1,361 +0,0 @@
-/*
- * Copyright 2011 Alex Dubov <oakad@yahoo.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-/*
- * Merury Computers MPQ101 board configuration file
- *
- */
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#ifdef CONFIG_36BIT
-# define CONFIG_PHYS_64BIT
-#endif
-
-/* High Level Configuration Options */
-#define CONFIG_BOOKE      /* BOOKE */
-#define CONFIG_E500       /* BOOKE e500 family */
-#define CONFIG_MPC85xx    /* MPC8540/60/55/41/48 */
-#define CONFIG_MPC8548    /* MPC8548 specific */
-#define CONFIG_MPQ101     /* MPQ101 board specific */
-
-#define CONFIG_SYS_SRIO   /* enable serial RapidIO */
-#define CONFIG_TSEC_ENET  /* tsec ethernet support */
-#define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */
-#define CONFIG_FSL_LAW    /* Use common FSL init code */
-
-/*
- * These can be toggled for performance analysis, otherwise use default.
- */
-#define CONFIG_L2_CACHE   /* toggle L2 cache */
-#define CONFIG_BTB        /* toggle branch predition */
-
-#define CONFIG_PANIC_HANG
-
-/*
- * Only possible on E500 Version 2 or newer cores.
- */
-#define CONFIG_ENABLE_36BIT_PHYS
-
-#ifdef CONFIG_PHYS_64BIT
-# define CONFIG_ADDR_MAP
-# define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */
-#endif
-
-
-#define CONFIG_SYS_CLK_FREQ      33000000 /* sysclk for MPC85xx */
-
-#define CONFIG_SYS_CCSRBAR		0xe0000000
-#define CONFIG_SYS_CCSRBAR_PHYS_LOW	CONFIG_SYS_CCSRBAR
-
-/* DDR Setup */
-#define CONFIG_FSL_DDR2
-
-#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */
-
-#define CONFIG_MEM_INIT_VALUE        0xDeadBeef
-#define CONFIG_SYS_DDR_SDRAM_BASE    0x00000000 /* DDR is system memory*/
-#define CONFIG_SYS_SDRAM_BASE        CONFIG_SYS_DDR_SDRAM_BASE
-
-#define CONFIG_NUM_DDR_CONTROLLERS   1
-#define CONFIG_DIMM_SLOTS_PER_CTLR   1
-#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
-
-/* Fixed 512MB DDR2 parameters */
-#define CONFIG_SYS_SDRAM_SIZE_LOG    29 /* DDR is 512MB */
-#define CONFIG_SYS_DDR_CS0_BNDS      0x0000001f
-#define CONFIG_SYS_DDR_CS0_CONFIG    0x80014102
-#define CONFIG_SYS_DDR_TIMING_3      0x00010000
-#define CONFIG_SYS_DDR_TIMING_0      0x00260802
-#define CONFIG_SYS_DDR_TIMING_1      0x5c47a432
-#define CONFIG_SYS_DDR_TIMING_1_PERF 0x49352322
-#define CONFIG_SYS_DDR_TIMING_2      0x03984cce
-#define CONFIG_SYS_DDR_TIMING_2_PERF 0x14904cca
-#define CONFIG_SYS_DDR_MODE_1        0x00400442
-#define CONFIG_SYS_DDR_MODE_1_PERF   0x00480432
-#define CONFIG_SYS_DDR_MODE_2        0x00000000
-#define CONFIG_SYS_DDR_MODE_2_PERF   0x00000000
-#define CONFIG_SYS_DDR_INTERVAL      0x08200100
-#define CONFIG_SYS_DDR_INTERVAL_PERF 0x06180100
-#define CONFIG_SYS_DDR_CLK_CTRL      0x03800000
-#define CONFIG_SYS_DDR_CONTROL       0xc3008000 /* Type = DDR2 */
-#define CONFIG_SYS_DDR_CONTROL2      0x04400000
-
-#define CONFIG_SYS_ALT_MEMTEST
-#define CONFIG_SYS_MEMTEST_START     0x0ff00000 /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END       0x0ffffffc
-
-/*
- * RAM definitions
- */
-#define CONFIG_SYS_INIT_RAM_LOCK
-#define CONFIG_SYS_INIT_RAM_ADDR   0xe4010000 /* Initial RAM address */
-#define CONFIG_SYS_INIT_RAM_SIZE   0x4000     /* Size of used area in RAM */
-
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE \
-				    - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET  CONFIG_SYS_GBL_DATA_OFFSET
-
-#define CONFIG_SYS_MONITOR_LEN     (256 * 1024)  /* Reserve 256 kB for Mon */
-#define CONFIG_SYS_MALLOC_LEN      (1024 * 1024) /* Reserved for malloc */
-
-/*
- * Local Bus Definitions
- */
-#define CONFIG_SYS_LBC_LCRR 0x00000004 /* LB clock ratio reg */
-#define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */
-
-
-/*
- * FLASH on the Local Bus
- * One bank, 128M, using the CFI driver.
- */
-#define CONFIG_SYS_BOOT_BLOCK 0xf8000000            /* boot TLB block */
-#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_BOOT_BLOCK /* start of FLASH 128M */
-
-#ifdef CONFIG_PHYS_64BIT
-# define CONFIG_SYS_FLASH_BASE_PHYS 0xff8000000ull
-#else
-# define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
-#endif
-
-/* 0xf8001801 */
-#define CONFIG_SYS_BR0_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \
-			       | BR_PS_32 | BR_V)
-
-/* 0xf8006ff7 */
-#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(128) | OR_GPCM_XAM | OR_GPCM_CSNT \
-			       | OR_GPCM_ACS_DIV2 | OR_GPCM_XACS \
-			       | OR_GPCM_SCY_15 | OR_GPCM_TRLX \
-			       | OR_GPCM_EHTR | OR_GPCM_EAD)
-
-#define CONFIG_SYS_FLASH_BANKS_LIST    {CONFIG_SYS_FLASH_BASE_PHYS}
-#define CONFIG_FLASH_SHOW_PROGRESS     45   /* count down from 45/5: 9..1 */
-
-#define CONFIG_SYS_MAX_FLASH_BANKS     1    /* number of banks */
-#define CONFIG_SYS_MAX_FLASH_SECT      512  /* sectors per device */
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT    60000 /* Flash Erase Timeout (ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT    500   /* Flash Write Timeout (ms) */
-
-#define CONFIG_FLASH_CFI_DRIVER
-#define CONFIG_SYS_FLASH_CFI
-#define CONFIG_SYS_FLASH_EMPTY_INFO
-#define CONFIG_SYS_FLASH_AMD_CHECK_DQ7
-/*
- * When initializing flash, if we cannot find the manufacturer ID,
- * assume this is the AMD flash.
- */
-#define CONFIG_ASSUME_AMD_FLASH
-
-/*
- * Environment parameters
- */
-#define CONFIG_ENV_IS_IN_FLASH
-#define CONFIG_ENV_OVERWRITE
-#define CONFIG_SYS_USE_PPCENV
-#define ENV_IS_EMBEDDED
-#define CONFIG_ENV_SECT_SIZE 0x40000   /* 256K */
-#define CONFIG_ENV_SIZE      0x800
-
-/* Environment at the start of flash sector, before text. */
-#define CONFIG_ENV_ADDR         (CONFIG_SYS_TEXT_BASE - CONFIG_ENV_SIZE)
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
-#define CONFIG_SYS_TEXT_BASE    0xfffc0800
-#define CONFIG_SYS_LDSCRIPT     "board/mercury/mpq101/u-boot.lds"
-
-/*
- * Cypress CY7C67200 USB controller on the Local Bus.
- * Not supported by u-boot at present.
- */
-#define CONFIG_SYS_LBC_OPTION_BASE 0xf0000000
-
-#ifdef CONFIG_PHYS_64BIT
-# define CONFIG_SYS_LBC_OPTION_BASE_PHYS 0xff0000000ull
-#else
-# define CONFIG_SYS_LBC_OPTION_BASE_PHYS CONFIG_SYS_LBC_OPTION_BASE
-#endif
-
-/* 0xf0001001 */
-#define CONFIG_SYS_BR1_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_LBC_OPTION_BASE_PHYS) \
-			       | BR_PS_16 | BR_V)
-
-/* fffff002 */
-#define CONFIG_SYS_OR1_PRELIM (P2SZ_TO_AM(0x8000) | OR_GPCM_XAM \
-			       | OR_GPCM_BCTLD | OR_GPCM_EHTR)
-
-/*
- * Serial Ports
- */
-#define CONFIG_CONS_INDEX           2
-#define CONFIG_SYS_NS16550
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE 1
-#define CONFIG_SYS_NS16550_CLK      get_bus_freq(0)
-
-#define CONFIG_SYS_BAUDRATE_TABLE   {300, 600, 1200, 2400, 4800, 9600, \
-				     19200, 38400, 115200}
-
-#define CONFIG_SYS_NS16550_COM1     (CONFIG_SYS_CCSRBAR+0x4500)
-#define CONFIG_SYS_NS16550_COM2     (CONFIG_SYS_CCSRBAR+0x4600)
-
-/*
- * I2C buses and peripherals
- */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_FSL
-#define CONFIG_SYS_FSL_I2C_SPEED	400000
-#define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
-#define CONFIG_SYS_FSL_I2C_OFFSET	0x3000
-#define CONFIG_SYS_FSL_I2C2_SPEED	400000
-#define CONFIG_SYS_FSL_I2C2_SLAVE	0x7F
-#define CONFIG_SYS_FSL_I2C2_OFFSET	0x3100
-#define CONFIG_SYS_I2C_NOPROBES		{ {0, 0x69} }
-
-/* I2C RTC - M41T81 */
-#define CONFIG_RTC_M41T62
-#define CONFIG_SYS_I2C_RTC_ADDR     0x68
-#define CONFIG_SYS_M41T11_BASE_YEAR 2000
-
-/* I2C EEPROM - 24C256 */
-#define CONFIG_SYS_I2C_EEPROM_ADDR            0x50
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS     6
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 12
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN        2
-#define CONFIG_SYS_EEPROM_BUS_NUM             1
-
-/*
- * RapidIO MMU
- */
-#ifdef CONFIG_SYS_SRIO
-# define CONFIG_SRIO1
-# define CONFIG_SYS_SRIO1_MEM_VIRT  0xc0000000
-# define CONFIG_SYS_SRIO1_MEM_SIZE  0x20000000 /* 512M */
-
-# ifdef CONFIG_PHYS_64BIT
-#  define CONFIG_SYS_SRIO1_MEM_PHYS 0xfc0000000ull
-# else
-#  define CONFIG_SYS_SRIO1_MEM_PHYS CONFIG_SYS_SRIO1_MEM_VIRT
-# endif
-#endif
-
-/*
- * Ethernet
- */
-#ifdef CONFIG_TSEC_ENET
-
-# define CONFIG_MII                /* MII PHY management */
-# define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */
-
-# define CONFIG_TSEC1
-# define CONFIG_TSEC1_NAME       "eTSEC0"
-# define TSEC1_PHY_ADDR          0x10
-# define TSEC1_PHYIDX            0
-# define TSEC1_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
-
-# define CONFIG_TSEC2
-# define CONFIG_TSEC2_NAME       "eTSEC1"
-# define TSEC2_PHY_ADDR          0x11
-# define TSEC2_PHYIDX            0
-# define TSEC2_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
-
-# define CONFIG_TSEC3
-# define CONFIG_TSEC3_NAME       "eTSEC2"
-# define TSEC3_PHY_ADDR          0x12
-# define TSEC3_PHYIDX            0
-# define TSEC3_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
-
-# define CONFIG_TSEC4
-# define CONFIG_TSEC4_NAME       "eTSEC3"
-# define TSEC4_PHY_ADDR          0x13
-# define TSEC4_PHYIDX            0
-# define TSEC4_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
-
-/* Options are: eTSEC[0-3] */
-# define CONFIG_ETHPRIME         "eTSEC0"
-# define CONFIG_PHY_GIGE         /* Include GbE speed/duplex detection */
-#endif
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_DATE
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_SNTP
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_EEPROM
-#define CONFIG_CMD_MII
-#define CONFIG_CMD_ELF
-#define CONFIG_CMD_IRQ
-#define CONFIG_CMD_SETEXPR
-#define CONFIG_CMD_JFFS2
-
-/*
- * Miscellaneous configurable options
- */
-
-/* pass open firmware flat tree */
-#define CONFIG_OF_LIBFDT
-#define CONFIG_OF_BOARD_SETUP
-#define CONFIG_OF_STDOUT_VIA_ALIAS
-
-#define CONFIG_FIT         /* new uImage format support */
-#define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */
-
-/* Use the HUSH parser */
-#define CONFIG_SYS_HUSH_PARSER
-
-
-#define CONFIG_LOADS_ECHO            /* echo on for serial download */
-#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
-
-#define CONFIG_SYS_LONGHELP          /* undef to save memory */
-#define CONFIG_CMDLINE_EDITING       /* Command-line editing */
-#define CONFIG_AUTO_COMPLETE         /* add autocompletion support */
-
-#define CONFIG_SYS_LOAD_ADDR         0x2000000    /* default load address */
-#define CONFIG_SYS_PROMPT            "MPQ-101=> " /* Monitor Command Prompt */
-
-/* Console I/O Buffer Size */
-#ifdef CONFIG_CMD_KGDB
-# define CONFIG_SYS_CBSIZE 1024
-#else
-# define CONFIG_SYS_CBSIZE 256
-#endif
-
-/* Print Buffer Size */
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT)+16)
-
-#define CONFIG_SYS_MAXARGS  16                /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-#define CONFIG_SYS_HZ       1000              /* decrementer freq: 1ms ticks */
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 16 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/
-#define CONFIG_SYS_BOOTM_LEN (16 << 20) /* Increase max gunzip size */
-
-#ifdef CONFIG_CMD_KGDB
-# define CONFIG_KGDB_BAUDRATE  230400 /* speed to run kgdb serial port */
-# define CONFIG_KGDB_SER_INDEX 2      /* which serial port to use */
-#endif
-
-/*
- * Basic Environment Configuration
- */
-#define CONFIG_BAUDRATE  115200
-#define CONFIG_BOOTDELAY 5            /* -1 disables auto-boot */
-
-/*default location for tftp and bootm*/
-#define CONFIG_LOADADDR  CONFIG_SYS_LOAD_ADDR
-
-#endif /* __CONFIG_H */
diff --git a/include/configs/mpr2.h b/include/configs/mpr2.h
index 7e18723723..8ae497c6d5 100644
--- a/include/configs/mpr2.h
+++ b/include/configs/mpr2.h
@@ -24,14 +24,11 @@
 #define CONFIG_VERSION_VARIABLE
 
 /* CPU and platform */
-#define CONFIG_SH		1
-#define CONFIG_SH3		1
 #define CONFIG_CPU_SH7720	1
 #define CONFIG_MPR2		1
 
 /* U-Boot internals */
 #define CONFIG_SYS_LONGHELP			/* undef to save memory	*/
-#define CONFIG_SYS_PROMPT		"=> "	/* Monitor Command Prompt */
 #define CONFIG_SYS_CBSIZE		256	/* Buffer size for input from the Console */
 #define CONFIG_SYS_PBSIZE		256	/* Buffer size for Console output */
 #define CONFIG_SYS_MAXARGS		16	/* max args accepted for monitor commands */
@@ -67,8 +64,9 @@
 
 /* Clocks */
 #define CONFIG_SYS_CLK_FREQ	24000000
+#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
+#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
 #define CONFIG_SYS_TMU_CLK_DIV		4	/* 4 (default), 16, 64, 256 or 1024 */
-#define CONFIG_SYS_HZ		1000
 
 /* UART */
 #define CONFIG_SCIF_CONSOLE	1
diff --git a/include/configs/ms7720se.h b/include/configs/ms7720se.h
index bc8bb8d5a7..585d68f208 100644
--- a/include/configs/ms7720se.h
+++ b/include/configs/ms7720se.h
@@ -9,8 +9,6 @@
 #ifndef __MS7720SE_H
 #define __MS7720SE_H
 
-#define CONFIG_SH		1
-#define CONFIG_SH3		1
 #define CONFIG_CPU_SH7720	1
 #define CONFIG_MS7720SE		1
 
@@ -38,7 +36,6 @@
 
 #define CONFIG_SYS_TEXT_BASE	0x8FFC0000
 #define CONFIG_SYS_LONGHELP		/* undef to save memory	*/
-#define CONFIG_SYS_PROMPT	"=> "	/* Monitor Command Prompt */
 #define CONFIG_SYS_CBSIZE	256	/* Buffer size for input from the Console */
 #define CONFIG_SYS_PBSIZE	256	/* Buffer size for Console output */
 #define CONFIG_SYS_MAXARGS	16	/* max args accepted for monitor commands */
@@ -85,8 +82,9 @@
 
 /* Board Clock */
 #define CONFIG_SYS_CLK_FREQ	33333333
+#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
+#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
 #define CONFIG_SYS_TMU_CLK_DIV		4	/* 4 (default), 16, 64, 256 or 1024 */
-#define CONFIG_SYS_HZ		1000
 
 /* PCMCIA */
 #define CONFIG_IDE_PCMCIA	1
diff --git a/include/configs/ms7722se.h b/include/configs/ms7722se.h
index a757737f84..1c8ada6c03 100644
--- a/include/configs/ms7722se.h
+++ b/include/configs/ms7722se.h
@@ -9,8 +9,6 @@
 #ifndef __MS7722SE_H
 #define __MS7722SE_H
 
-#define CONFIG_SH		1
-#define CONFIG_SH4		1
 #define CONFIG_CPU_SH7722	1
 #define CONFIG_MS7722SE		1
 
@@ -41,7 +39,6 @@
 
 #define CONFIG_SYS_TEXT_BASE	0x8FFC0000
 #define CONFIG_SYS_LONGHELP				/* undef to save memory	*/
-#define CONFIG_SYS_PROMPT		"=> "		/* Monitor Command Prompt */
 #define CONFIG_SYS_CBSIZE		256		/* Buffer size for input from the Console */
 #define CONFIG_SYS_PBSIZE		256		/* Buffer size for Console output */
 #define CONFIG_SYS_MAXARGS		16		/* max args accepted for monitor commands */
@@ -111,7 +108,8 @@
 
 /* Board Clock */
 #define CONFIG_SYS_CLK_FREQ	33333333
+#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
+#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
 #define CONFIG_SYS_TMU_CLK_DIV		(4)	/* 4 (default), 16, 64, 256 or 1024 */
-#define CONFIG_SYS_HZ		1000
 
 #endif	/* __MS7722SE_H */
diff --git a/include/configs/ms7750se.h b/include/configs/ms7750se.h
index c4c96bfb2d..4cf8efeca0 100644
--- a/include/configs/ms7750se.h
+++ b/include/configs/ms7750se.h
@@ -9,8 +9,6 @@
 #ifndef __MS7750SE_H
 #define __MS7750SE_H
 
-#define CONFIG_SH		1
-#define CONFIG_SH4		1
 #define CONFIG_CPU_SH7750	1
 /* #define CONFIG_CPU_SH7751	1 */
 /* #define CONFIG_CPU_TYPE_R	1 */
@@ -39,7 +37,6 @@
 #define CONFIG_SYS_SDRAM_SIZE		(64 * 1024 * 1024)
 
 #define CONFIG_SYS_LONGHELP
-#define CONFIG_SYS_PROMPT		"=> "
 #define CONFIG_SYS_CBSIZE		256
 #define CONFIG_SYS_PBSIZE		256
 #define CONFIG_SYS_MAXARGS		16
@@ -82,7 +79,8 @@
 
 /* Board Clock */
 #define CONFIG_SYS_CLK_FREQ	33333333
+#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
+#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
 #define CONFIG_SYS_TMU_CLK_DIV		4
-#define CONFIG_SYS_HZ		1000
 
 #endif /* __MS7750SE_H */
diff --git a/include/configs/muas3001.h b/include/configs/muas3001.h
index 8eba0228b2..7343c947ca 100644
--- a/include/configs/muas3001.h
+++ b/include/configs/muas3001.h
@@ -13,8 +13,6 @@
  * (easy to change)
  */
 
-#define CONFIG_8260		1
-#define CONFIG_MPC8260		1
 #define CONFIG_MUAS3001		1
 
 #define	CONFIG_SYS_TEXT_BASE	0xFF000000
@@ -181,7 +179,6 @@
  */
 #define CONFIG_SYS_HUSH_PARSER
 #define CONFIG_SYS_LONGHELP			/* undef to save memory	    */
-#define CONFIG_SYS_PROMPT		"=> "	/* Monitor Command Prompt   */
 #if defined(CONFIG_CMD_KGDB)
 #define CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size  */
 #else
@@ -196,8 +193,6 @@
 
 #define CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address */
 
-#define CONFIG_SYS_HZ			1000	/* decrementer freq: 1 ms ticks */
-
 #define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
 
 #define CONFIG_SYS_SDRAM_BASE		0x00000000
diff --git a/include/configs/munices.h b/include/configs/munices.h
index f98360d96d..e65a14af23 100644
--- a/include/configs/munices.h
+++ b/include/configs/munices.h
@@ -11,8 +11,7 @@
  * High Level Configuration Options
  * (easy to change)
  */
-#define CONFIG_MPC5xxx		1	/* This is an MPC5xxx CPU */
-#define CONFIG_MPC5200		1	/* (more precisely an MPC5200 CPU) */
+#define CONFIG_MPC5200		1	/* This is an MPC5200 CPU */
 #define CONFIG_MPC5200_DDR	1	/* (with DDR-SDRAM) */
 #define CONFIG_MUNICES		1	/* ... on MUNICes board */
 
@@ -166,7 +165,6 @@
  * Miscellaneous configurable options
  */
 #define CONFIG_SYS_LONGHELP			/* undef to save memory	    */
-#define CONFIG_SYS_PROMPT		"=> "	/* Monitor Command Prompt   */
 #define CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size  */
 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)	/* Print Buffer Size */
 #define CONFIG_SYS_MAXARGS		16		/* max number of command args	*/
@@ -176,7 +174,6 @@
 #define CONFIG_SYS_MEMTEST_END		0x00f00000	/* 1 ... 15 MB in DRAM	*/
 
 #define CONFIG_SYS_LOAD_ADDR		0x200000	/* default load address */
-#define CONFIG_SYS_HZ			1000	/* decrementer freq: 1 ms ticks */
 
 #define CONFIG_DISPLAY_BOARDINFO 1
 #define CONFIG_CMDLINE_EDITING  1
diff --git a/include/configs/mv-common.h b/include/configs/mv-common.h
index c458dd9734..721b75daee 100644
--- a/include/configs/mv-common.h
+++ b/include/configs/mv-common.h
@@ -35,7 +35,6 @@
 /*
  * CLKs configurations
  */
-#define CONFIG_SYS_HZ		1000
 
 /*
  * NS16550 Configuration
diff --git a/include/configs/mx1ads.h b/include/configs/mx1ads.h
deleted file mode 100644
index 70d1dee6aa..0000000000
--- a/include/configs/mx1ads.h
+++ /dev/null
@@ -1,166 +0,0 @@
-/*
- * include/configs/mx1ads.h
- *
- * (c) Copyright 2004
- * Techware Information Technology, Inc.
- * http://www.techware.com.tw/
- *
- * Ming-Len Wu <minglen_wu@techware.com.tw>
- *
- * This is the Configuration setting for Motorola MX1ADS board
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-#define CONFIG_ARM920T		1	/* This is an ARM920T Core		*/
-#define CONFIG_IMX		1	/* It's a Motorola MC9328 SoC		*/
-#define CONFIG_MX1ADS		1	/* on a Motorola MX1ADS Board		*/
-
-/*
- * Select serial console configuration
-  */
-#define CONFIG_IMX_SERIAL
-#define CONFIG_IMX_SERIAL1		/* internal uart 1 */
-/* #define _CONFIG_UART2 */		/* internal uart 2 */
-/* #define CONFIG_SILENT_CONSOLE */	/* use this to disable output */
-
-#define CONFIG_BOARD_LATE_INIT
-#define USE_920T_MMU		1
-
-#if 0
-#define CONFIG_SYS_MX1_GPCR		0x000003AB	/* for MX1ADS 0L44N		*/
-#define CONFIG_SYS_MX1_GPCR		0x000003AB	/* for MX1ADS 0L44N		*/
-#define CONFIG_SYS_MX1_GPCR		0x000003AB	/* for MX1ADS 0L44N		*/
-#endif
-
-/*
- * Size of malloc() pool
- */
-
-#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 128*1024)
-
-/*
- *  CS8900 Ethernet drivers
- */
-#define CONFIG_CS8900		/* we have a CS8900 on-board */
-#define CONFIG_CS8900_BASE	0x15000300
-#define CONFIG_CS8900_BUS16	/* the Linux driver does accesses as shorts */
-
-/*
- * select serial console configuration
- */
-
-/* #define CONFIG_UART1			*/
-/* #define CONFIG_UART2		1	*/
-
-#define CONFIG_BAUDRATE		115200
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_CACHE
-#define CONFIG_CMD_REGINFO
-#define CONFIG_CMD_ELF
-
-#define CONFIG_BOOTDELAY	3
-#define CONFIG_BOOTARGS		"root=/dev/msdk mem=48M"
-#define CONFIG_BOOTFILE		"mx1ads"
-#define CONFIG_BOOTCOMMAND	"tftp; bootm"
-
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_KGDB_BAUDRATE	115200		/* speed to run kgdb serial port */
-						/* what's this ? it's not used anywhere */
-#define CONFIG_KGDB_SER_INDEX	1		/* which serial port to use */
-#endif
-
-/*
- * Miscellaneous configurable options
- */
-
-#define CONFIG_SYS_HUSH_PARSER		1
-
-#define CONFIG_SYS_LONGHELP				/* undef to save memory		*/
-
-#ifdef CONFIG_SYS_HUSH_PARSER
-#define CONFIG_SYS_PROMPT		"MX1ADS$ "	/* Monitor Command Prompt */
-#else
-#define CONFIG_SYS_PROMPT		"MX1ADS=> "	/* Monitor Command Prompt */
-#endif
-
-#define CONFIG_SYS_CBSIZE		256		/* Console I/O Buffer Size	*/
-#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
-						/* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS		16		/* max number of command args	*/
-#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
-
-#define CONFIG_SYS_MEMTEST_START	0x09000000	/* memtest works on	*/
-#define CONFIG_SYS_MEMTEST_END		0x0AF00000	/* 63 MB in DRAM	*/
-
-#define CONFIG_SYS_LOAD_ADDR		0x08800000	/* default load address */
-/*#define	CONFIG_SYS_HZ			1000 */
-#define CONFIG_SYS_HZ			3686400
-#define CONFIG_SYS_CPUSPEED		0x141
-
-/*-----------------------------------------------------------------------
- * Physical Memory Map
- */
-
-#define CONFIG_NR_DRAM_BANKS	1		/* we have 1 bank of SDRAM	*/
-#define PHYS_SDRAM_1		0x08000000	/* SDRAM  on CSD0		*/
-#define PHYS_SDRAM_1_SIZE	0x04000000	/* 64 MB			*/
-
-#define CONFIG_SYS_TEXT_BASE	0x10000000
-
-#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
-#define CONFIG_SYS_INIT_RAM_ADDR	0x00300000
-#define CONFIG_SYS_INIT_RAM_SIZE	0x000FFFFF
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - \
-						GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_ADDR	(CONFIG_SYS_INIT_RAM_ADDR + \
-						CONFIG_SYS_GBL_DATA_OFFSET)
-
-#define CONFIG_SYS_MAX_FLASH_BANKS	1		/* 1 bank of SyncFlash		*/
-#define CONFIG_SYS_FLASH_BASE		0x0C000000	/* SyncFlash on CSD1		*/
-#define FLASH_BANK_SIZE		0x01000000	/* 16 MB Total			*/
-
-/*-----------------------------------------------------------------------
- * FLASH and environment organization
- */
-
-#define CONFIG_SYNCFLASH	1
-#define PHYS_FLASH_SIZE		0x01000000
-#define CONFIG_SYS_MAX_FLASH_SECT	(16)
-#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE+0x00ff8000)
-
-#define CONFIG_ENV_IS_IN_FLASH	1
-#define CONFIG_ENV_SIZE		0x04000 /* Total Size of Environment Sector */
-#define CONFIG_ENV_SECT_SIZE	0x100000
-
-/*-----------------------------------------------------------------------
- * Enable passing ATAGS
- */
-
-#define CONFIG_CMDLINE_TAG		1	/* enable passing of ATAGs */
-#define CONFIG_SETUP_MEMORY_TAGS	1
-
-#define CONFIG_SYS_CLK_FREQ 16780000
-#define CONFIG_SYSPLL_CLK_FREQ 16000000
-
-#endif	/* __CONFIG_H */
diff --git a/include/configs/mx23evk.h b/include/configs/mx23evk.h
index 1b40a36fcf..b496892f06 100644
--- a/include/configs/mx23evk.h
+++ b/include/configs/mx23evk.h
@@ -84,7 +84,7 @@
 		"fi ; "	\
 		"fi\0" \
 	"script=boot.scr\0"	\
-	"uimage=uImage\0" \
+	"image=zImage\0" \
 	"console=ttyAMA0\0" \
 	"fdt_file=imx23-evk.dtb\0" \
 	"fdt_addr=0x41000000\0" \
@@ -98,22 +98,22 @@
 		"fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
 	"bootscript=echo Running bootscript from mmc ...; "	\
 		"source\0" \
-	"loaduimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${uimage}\0" \
+	"loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
 	"loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
 	"mmcboot=echo Booting from mmc ...; " \
 		"run mmcargs; " \
 		"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
 			"if run loadfdt; then " \
-				"bootm ${loadaddr} - ${fdt_addr}; " \
+				"bootz ${loadaddr} - ${fdt_addr}; " \
 			"else " \
 				"if test ${boot_fdt} = try; then " \
-					"bootm; " \
+					"bootz; " \
 				"else " \
 					"echo WARN: Cannot load the DT; " \
 				"fi; " \
 			"fi; " \
 		"else " \
-			"bootm; " \
+			"bootz; " \
 		"fi;\0"
 
 #define CONFIG_BOOTCOMMAND \
@@ -121,7 +121,7 @@
 		"if run loadbootscript; then " \
 			"run bootscript; " \
 		"else " \
-			"if run loaduimage; then " \
+			"if run loadimage; then " \
 				"run mmcboot; " \
 			"else " \
 				"echo ERR: Fail to boot from MMC; " \
diff --git a/include/configs/mx25pdk.h b/include/configs/mx25pdk.h
index 543c4159ef..aff2419f85 100644
--- a/include/configs/mx25pdk.h
+++ b/include/configs/mx25pdk.h
@@ -12,10 +12,13 @@
 /* High Level Configuration Options */
 
 #define CONFIG_MX25
-#define CONFIG_SYS_HZ			1000
 #define CONFIG_SYS_TEXT_BASE		0x81200000
 #define CONFIG_MXC_GPIO
 
+#define CONFIG_SYS_TIMER_RATE		32768
+#define CONFIG_SYS_TIMER_COUNTER	\
+	(&((struct gpt_regs *)IMX_GPT1_BASE)->counter)
+
 #define CONFIG_DISPLAY_CPUINFO
 #define CONFIG_DISPLAY_BOARDINFO
 
@@ -59,15 +62,15 @@
 /* No NOR flash present */
 #define CONFIG_ENV_OFFSET      (6 * 64 * 1024)
 #define CONFIG_ENV_SIZE        (8 * 1024)
+#define CONFIG_SYS_MMC_ENV_DEV		0
 
 #define CONFIG_SYS_NO_FLASH
 #define CONFIG_ENV_IS_IN_MMC
 #define CONFIG_SYS_MMC_ENV_DEV 0
 
 /* U-Boot general configuration */
-#define CONFIG_SYS_PROMPT	"MX25PDK U-Boot > "
 #define CONFIG_AUTO_COMPLETE
-#define CONFIG_SYS_CBSIZE	256	/* Console I/O Buffer Size  */
+#define CONFIG_SYS_CBSIZE	1024	/* Console I/O Buffer Size  */
 /* Print buffer sz */
 #define CONFIG_SYS_PBSIZE	(CONFIG_SYS_CBSIZE + \
 		sizeof(CONFIG_SYS_PROMPT) + 16)
@@ -111,10 +114,8 @@
 
 /* I2C Configs */
 #define CONFIG_CMD_I2C
-#define CONFIG_HARD_I2C
-#define CONFIG_I2C_MXC
-#define CONFIG_SYS_I2C_BASE		IMX_I2C_BASE
-#define CONFIG_SYS_I2C_SPEED		100000
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_MXC
 
 /* RTC */
 #define CONFIG_RTC_IMXDI
@@ -132,12 +133,104 @@
 #define CONFIG_LOADADDR		0x81000000	/* loadaddr env var */
 #define CONFIG_SYS_LOAD_ADDR	CONFIG_LOADADDR
 
+#define CONFIG_DEFAULT_FDT_FILE		"imx25-pdk.dtb"
+
 #define CONFIG_EXTRA_ENV_SETTINGS \
 	"script=boot.scr\0" \
-	"uimage=uImage\0" \
-	"netargs=setenv bootargs console=ttymxc0,${baudrate} " \
+	"image=zImage\0" \
+	"console=ttymxc0\0" \
+	"splashpos=m,m\0" \
+	"fdt_high=0xffffffff\0" \
+	"initrd_high=0xffffffff\0" \
+	"fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \
+	"fdt_addr=0x82000000\0" \
+	"boot_fdt=try\0" \
+	"ip_dyn=yes\0" \
+	"mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \
+	"mmcpart=1\0" \
+	"mmcroot=/dev/mmcblk0p2 rootwait rw\0" \
+	"update_sd_firmware_filename=u-boot.imx\0" \
+	"update_sd_firmware=" \
+		"if test ${ip_dyn} = yes; then " \
+			"setenv get_cmd dhcp; " \
+		"else " \
+			"setenv get_cmd tftp; " \
+		"fi; " \
+		"if mmc dev ${mmcdev}; then "	\
+			"if ${get_cmd} ${update_sd_firmware_filename}; then " \
+				"setexpr fw_sz ${filesize} / 0x200; " \
+				"setexpr fw_sz ${fw_sz} + 1; "	\
+				"mmc write ${loadaddr} 0x2 ${fw_sz}; " \
+			"fi; "	\
+		"fi\0" \
+	"mmcargs=setenv bootargs console=${console},${baudrate} " \
+		"root=${mmcroot}\0" \
+	"loadbootscript=" \
+		"fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
+	"bootscript=echo Running bootscript from mmc ...; " \
+		"source\0" \
+	"loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
+	"loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
+	"mmcboot=echo Booting from mmc ...; " \
+		"run mmcargs; " \
+		"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
+			"if run loadfdt; then " \
+				"bootz ${loadaddr} - ${fdt_addr}; " \
+			"else " \
+				"if test ${boot_fdt} = try; then " \
+					"bootz; " \
+				"else " \
+					"echo WARN: Cannot load the DT; " \
+				"fi; " \
+			"fi; " \
+		"else " \
+			"bootz; " \
+		"fi;\0" \
+	"netargs=setenv bootargs console=${console},${baudrate} " \
 		"root=/dev/nfs " \
-		"ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
-	"bootcmd=run netargs; dhcp ${uimage}; bootm\0" \
+	"ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
+		"netboot=echo Booting from net ...; " \
+		"run netargs; " \
+		"if test ${ip_dyn} = yes; then " \
+			"setenv get_cmd dhcp; " \
+		"else " \
+			"setenv get_cmd tftp; " \
+		"fi; " \
+		"${get_cmd} ${image}; " \
+		"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
+			"if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
+				"bootz ${loadaddr} - ${fdt_addr}; " \
+			"else " \
+				"if test ${boot_fdt} = try; then " \
+					"bootz; " \
+				"else " \
+					"echo WARN: Cannot load the DT; " \
+				"fi; " \
+			"fi; " \
+		"else " \
+			"bootz; " \
+		"fi;\0"
+
+#define CONFIG_BOOTCOMMAND \
+	   "mmc dev ${mmcdev}; if mmc rescan; then " \
+		   "if run loadbootscript; then " \
+			   "run bootscript; " \
+		   "else " \
+			   "if run loadimage; then " \
+				   "run mmcboot; " \
+			   "else run netboot; " \
+			   "fi; " \
+		   "fi; " \
+	   "else run netboot; fi"
+
+/* Miscellaneous configurable options */
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_AUTO_COMPLETE
+
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS	       16
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
 
 #endif /* __CONFIG_H */
diff --git a/include/configs/mx28evk.h b/include/configs/mx28evk.h
index 07f88ca4c7..9b9124ac14 100644
--- a/include/configs/mx28evk.h
+++ b/include/configs/mx28evk.h
@@ -14,7 +14,6 @@
 /* System configurations */
 #define CONFIG_MX28				/* i.MX28 SoC */
 #define CONFIG_MACH_TYPE	MACH_TYPE_MX28EVK
-#define CONFIG_SYS_PROMPT	"MX28EVK U-Boot > "
 
 /* U-Boot Commands */
 #define CONFIG_SYS_NO_FLASH
@@ -97,7 +96,7 @@
 		"512k(environment),"		\
 		"512k(redundant-environment),"	\
 		"4m(kernel),"			\
-		"128k(fdt),"			\
+		"512k(fdt),"			\
 		"8m(ramdisk),"			\
 		"-(filesystem)"
 #endif
@@ -161,9 +160,9 @@
 
 /* Extra Environment */
 #define CONFIG_EXTRA_ENV_SETTINGS \
+	"ubifs_file=filesystem.ubifs\0" \
 	"update_nand_full_filename=u-boot.nand\0" \
 	"update_nand_firmware_filename=u-boot.sb\0"	\
-	"update_sd_firmware_filename=u-boot.sd\0" \
 	"update_nand_firmware_maxsz=0x100000\0"	\
 	"update_nand_stride=0x40\0"	/* MX28 datasheet ch. 12.12 */ \
 	"update_nand_count=0x4\0"	/* MX28 datasheet ch. 12.12 */ \
@@ -172,7 +171,7 @@
 		"nand info ; " \
 		"setexpr fcb_sz ${update_nand_stride} * ${update_nand_count};" \
 		"setexpr update_nand_fcb ${fcb_sz} * ${nand_writesize}\0" \
-	"update_nand_full="		    /* Update FCB, DBBT and FW */ \
+	"update_nand_firmware_full=" /* Update FCB, DBBT and FW */ \
 		"if tftp ${update_nand_full_filename} ; then " \
 		"run update_nand_get_fcb_size ; " \
 		"nand scrub -y 0x0 ${filesize} ; " \
@@ -191,6 +190,55 @@
 		"nand write ${loadaddr} ${fcb_sz} ${filesize} ; " \
 		"nand write ${loadaddr} ${fw_off} ${filesize} ; " \
 		"fi\0" \
+	"update_nand_kernel="		/* Update kernel */ \
+		"mtdparts default; " \
+		"nand erase.part kernel; " \
+		"if test ${ip_dyn} = yes; then " \
+			"setenv get_cmd dhcp; " \
+		"else " \
+			"setenv get_cmd tftp; " \
+		"fi; " \
+		"${get_cmd} ${image}; " \
+		"nand write ${loadaddr} kernel ${filesize}\0" \
+	"update_nand_fdt="		/* Update fdt */ \
+		"mtdparts default; " \
+		"nand erase.part fdt; " \
+		"if test ${ip_dyn} = yes; then " \
+			"setenv get_cmd dhcp; " \
+		"else " \
+			"setenv get_cmd tftp; " \
+		"fi; " \
+		"${get_cmd} ${fdt_file}; " \
+		"nand write ${loadaddr} fdt ${filesize}\0" \
+	"update_nand_filesystem="		/* Update filesystem */ \
+		"mtdparts default; " \
+		"nand erase.part filesystem; " \
+		"if test ${ip_dyn} = yes; then " \
+			"setenv get_cmd dhcp; " \
+		"else " \
+			"setenv get_cmd tftp; " \
+		"fi; " \
+		"${get_cmd} ${ubifs_file}; " \
+		"ubi part filesystem; " \
+		"ubi create filesystem; " \
+		"ubi write ${loadaddr} filesystem ${filesize}\0" \
+	"nandargs=setenv bootargs console=${console_mainline},${baudrate} " \
+		"rootfstype=ubifs ubi.mtd=6 root=ubi0_0 ${mtdparts}\0" \
+	"nandboot="		/* Boot from NAND */ \
+		"mtdparts default; " \
+		"run nandargs; " \
+		"nand read ${loadaddr} kernel 0x00400000; " \
+		"if test ${boot_fdt} = yes; then " \
+			"nand read ${fdt_addr} fdt 0x00080000; " \
+			"bootz ${loadaddr} - ${fdt_addr}; " \
+		"else " \
+			"if test ${boot_fdt} = no; then " \
+				"bootz; " \
+			"else " \
+				"echo \"ERROR: Set boot_fdt to yes or no.\"; " \
+			"fi; " \
+		"fi\0" \
+	"update_sd_firmware_filename=u-boot.sd\0" \
 	"update_sd_firmware="		/* Update the SD firmware partition */ \
 		"if mmc rescan ; then "	\
 		"if tftp ${update_sd_firmware_filename} ; then " \
@@ -200,7 +248,7 @@
 		"fi ; "	\
 		"fi\0" \
 	"script=boot.scr\0"	\
-	"uimage=uImage\0" \
+	"image=zImage\0" \
 	"console_fsl=ttyAM0\0" \
 	"console_mainline=ttyAMA0\0" \
 	"fdt_file=imx28-evk.dtb\0" \
@@ -216,22 +264,22 @@
 		"fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
 	"bootscript=echo Running bootscript from mmc ...; "	\
 		"source\0" \
-	"loaduimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${uimage}\0" \
+	"loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
 	"loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
 	"mmcboot=echo Booting from mmc ...; " \
 		"run mmcargs; " \
 		"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
 			"if run loadfdt; then " \
-				"bootm ${loadaddr} - ${fdt_addr}; " \
+				"bootz ${loadaddr} - ${fdt_addr}; " \
 			"else " \
 				"if test ${boot_fdt} = try; then " \
-					"bootm; " \
+					"bootz; " \
 				"else " \
 					"echo WARN: Cannot load the DT; " \
 				"fi; " \
 			"fi; " \
 		"else " \
-			"bootm; " \
+			"bootz; " \
 		"fi;\0" \
 	"netargs=setenv bootargs console=${console_mainline},${baudrate} " \
 		"root=/dev/nfs " \
@@ -243,19 +291,19 @@
 		"else " \
 			"setenv get_cmd tftp; " \
 		"fi; " \
-		"${get_cmd} ${uimage}; " \
+		"${get_cmd} ${image}; " \
 		"if test ${boot_fdt} = yes; then " \
 			"if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
-				"bootm ${loadaddr} - ${fdt_addr}; " \
+				"bootz ${loadaddr} - ${fdt_addr}; " \
 			"else " \
 				"if test ${boot_fdt} = try; then " \
-					"bootm; " \
+					"bootz; " \
 				"else " \
 					"echo WARN: Cannot load the DT; " \
 				"fi;" \
 			"fi; " \
 		"else " \
-			"bootm; " \
+			"bootz; " \
 		"fi;\0"
 
 #define CONFIG_BOOTCOMMAND \
@@ -263,7 +311,7 @@
 		"if run loadbootscript; then " \
 			"run bootscript; " \
 		"else " \
-			"if run loaduimage; then " \
+			"if run loadimage; then " \
 				"run mmcboot; " \
 			"else run netboot; " \
 			"fi; " \
diff --git a/include/configs/mx31ads.h b/include/configs/mx31ads.h
index 2736e3d7dc..51b1a141eb 100644
--- a/include/configs/mx31ads.h
+++ b/include/configs/mx31ads.h
@@ -123,7 +123,6 @@
  * Miscellaneous configurable options
  */
 #define CONFIG_SYS_LONGHELP		/* undef to save memory */
-#define CONFIG_SYS_PROMPT		"=> "
 #define CONFIG_SYS_CBSIZE		256		/* Console I/O Buffer Size */
 /* Print Buffer Size */
 #define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
@@ -135,8 +134,6 @@
 
 #define CONFIG_SYS_LOAD_ADDR		CONFIG_LOADADDR
 
-#define CONFIG_SYS_HZ			1000
-
 #define CONFIG_CMDLINE_EDITING	1
 
 /*-----------------------------------------------------------------------
diff --git a/include/configs/mx31pdk.h b/include/configs/mx31pdk.h
index d41f2cd411..f223788e5e 100644
--- a/include/configs/mx31pdk.h
+++ b/include/configs/mx31pdk.h
@@ -120,7 +120,6 @@
  * Miscellaneous configurable options
  */
 #define CONFIG_SYS_LONGHELP	/* undef to save memory */
-#define CONFIG_SYS_PROMPT	"MX31PDK U-Boot > "
 #define CONFIG_SYS_CBSIZE	256	/* Console I/O Buffer Size */
 /* Print Buffer Size */
 #define CONFIG_SYS_PBSIZE	(CONFIG_SYS_CBSIZE + \
@@ -137,8 +136,6 @@
 /* default load address */
 #define CONFIG_SYS_LOAD_ADDR		0x81000000
 
-#define CONFIG_SYS_HZ			1000
-
 #define CONFIG_CMDLINE_EDITING
 
 /*-----------------------------------------------------------------------
diff --git a/include/configs/mx35pdk.h b/include/configs/mx35pdk.h
index 2f59104b83..0a46f4c305 100644
--- a/include/configs/mx35pdk.h
+++ b/include/configs/mx35pdk.h
@@ -40,10 +40,8 @@
 /*
  * Hardware drivers
  */
-#define CONFIG_HARD_I2C
-#define CONFIG_I2C_MXC
-#define CONFIG_SYS_I2C_BASE		I2C1_BASE_ADDR
-#define CONFIG_SYS_I2C_SPEED		100000
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_MXC
 #define CONFIG_MXC_SPI
 #define CONFIG_MXC_GPIO
 
@@ -136,7 +134,6 @@
  * Miscellaneous configurable options
  */
 #define CONFIG_SYS_LONGHELP	/* undef to save memory */
-#define CONFIG_SYS_PROMPT	"MX35 U-Boot > "
 #define CONFIG_CMDLINE_EDITING
 #define CONFIG_SYS_HUSH_PARSER	/* Use the HUSH parser */
 
@@ -154,8 +151,6 @@
 
 #define CONFIG_SYS_LOAD_ADDR		CONFIG_LOADADDR
 
-#define CONFIG_SYS_HZ				1000
-
 /*
  * Physical Memory Map
  */
diff --git a/include/configs/mx51_efikamx.h b/include/configs/mx51_efikamx.h
index 0772dd23c8..0f2a4ef973 100644
--- a/include/configs/mx51_efikamx.h
+++ b/include/configs/mx51_efikamx.h
@@ -29,7 +29,6 @@
 
 #define CONFIG_SYS_TEXT_BASE		0x97800000
 
-#define	CONFIG_L2_OFF
 #define	CONFIG_SYS_ICACHE_OFF
 #define	CONFIG_SYS_DCACHE_OFF
 
@@ -227,7 +226,6 @@
 
 #define CONFIG_SYS_LOAD_ADDR		CONFIG_LOADADDR
 
-#define CONFIG_SYS_HZ			1000
 #define CONFIG_CMDLINE_EDITING
 
 /*-----------------------------------------------------------------------
diff --git a/include/configs/mx51evk.h b/include/configs/mx51evk.h
index 04f518a22a..b389475ebe 100644
--- a/include/configs/mx51evk.h
+++ b/include/configs/mx51evk.h
@@ -143,7 +143,7 @@
 
 #define CONFIG_EXTRA_ENV_SETTINGS \
 	"script=boot.scr\0" \
-	"uimage=uImage\0" \
+	"image=zImage\0" \
 	"fdt_file=imx51-babbage.dtb\0" \
 	"fdt_addr=0x91000000\0" \
 	"boot_fdt=try\0" \
@@ -157,22 +157,22 @@
 		"fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
 	"bootscript=echo Running bootscript from mmc ...; " \
 		"source\0" \
-	"loaduimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${uimage}\0" \
+	"loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
 	"loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
 	"mmcboot=echo Booting from mmc ...; " \
 		"run mmcargs; " \
 		"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
 			"if run loadfdt; then " \
-				"bootm ${loadaddr} - ${fdt_addr}; " \
+				"bootz ${loadaddr} - ${fdt_addr}; " \
 			"else " \
 				"if test ${boot_fdt} = try; then " \
-					"bootm; " \
+					"bootz; " \
 				"else " \
 					"echo WARN: Cannot load the DT; " \
 				"fi; " \
 			"fi; " \
 		"else " \
-			"bootm; " \
+			"bootz; " \
 		"fi;\0" \
 	"netargs=setenv bootargs console=ttymxc0,${baudrate} " \
 		"root=/dev/nfs " \
@@ -184,20 +184,20 @@
 		"else " \
 			"setenv get_cmd tftp; " \
 		"fi; " \
-		"${get_cmd} ${uimage}; " \
+		"${get_cmd} ${image}; " \
 		"if test ${boot_fdt} = yes ||  test ${boot_fdt} = try; then " \
 			"if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
-				"bootm ${loadaddr} - ${fdt_addr}; " \
+				"bootz ${loadaddr} - ${fdt_addr}; " \
 			"else " \
 				"if test ${boot_fdt} = try; then " \
-					"bootm; " \
+					"bootz; " \
 				"else " \
 					"echo ERROR: Cannot load the DT; " \
 					"exit; " \
 				"fi; " \
 			"fi; " \
 		"else " \
-			"bootm; " \
+			"bootz; " \
 		"fi;\0"
 
 #define CONFIG_BOOTCOMMAND \
@@ -205,7 +205,7 @@
 		"if run loadbootscript; then " \
 			"run bootscript; " \
 		"else " \
-			"if run loaduimage; then " \
+			"if run loadimage; then " \
 				"run mmcboot; " \
 			"else run netboot; " \
 			"fi; " \
@@ -219,7 +219,6 @@
  */
 #define CONFIG_SYS_LONGHELP		/* undef to save memory */
 #define CONFIG_SYS_HUSH_PARSER		/* use "hush" command parser */
-#define CONFIG_SYS_PROMPT		"MX51EVK U-Boot > "
 #define CONFIG_AUTO_COMPLETE
 #define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size */
 /* Print Buffer Size */
@@ -232,7 +231,6 @@
 
 #define CONFIG_SYS_LOAD_ADDR		CONFIG_LOADADDR
 
-#define CONFIG_SYS_HZ		1000
 #define CONFIG_CMDLINE_EDITING
 
 /*-----------------------------------------------------------------------
diff --git a/include/configs/mx53ard.h b/include/configs/mx53ard.h
index 7956083c35..797a637bf7 100644
--- a/include/configs/mx53ard.h
+++ b/include/configs/mx53ard.h
@@ -44,10 +44,8 @@
 
 /* I2C Configs */
 #define CONFIG_CMD_I2C
-#define CONFIG_HARD_I2C
-#define CONFIG_I2C_MXC
-#define CONFIG_SYS_I2C_BASE		I2C2_BASE_ADDR
-#define CONFIG_SYS_I2C_SPEED            100000
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_MXC
 
 /* MMC Configs */
 #define CONFIG_FSL_ESDHC
@@ -200,7 +198,6 @@
 
 #define CONFIG_SYS_LOAD_ADDR		CONFIG_LOADADDR
 
-#define CONFIG_SYS_HZ		1000
 #define CONFIG_CMDLINE_EDITING
 
 /* Physical Memory Map */
diff --git a/include/configs/mx53evk.h b/include/configs/mx53evk.h
index fe5cf3c701..3f0d80ac68 100644
--- a/include/configs/mx53evk.h
+++ b/include/configs/mx53evk.h
@@ -37,10 +37,8 @@
 
 /* I2C Configs */
 #define CONFIG_CMD_I2C
-#define CONFIG_HARD_I2C
-#define CONFIG_I2C_MXC
-#define CONFIG_SYS_I2C_BASE		I2C2_BASE_ADDR
-#define CONFIG_SYS_I2C_SPEED            100000
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_MXC
 
 /* PMIC Configs */
 #define CONFIG_POWER
@@ -136,7 +134,6 @@
 /* Miscellaneous configurable options */
 #define CONFIG_SYS_LONGHELP		/* undef to save memory */
 #define CONFIG_SYS_HUSH_PARSER		/* use "hush" command parser */
-#define CONFIG_SYS_PROMPT		"MX53EVK U-Boot > "
 #define CONFIG_AUTO_COMPLETE
 #define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size */
 
@@ -150,7 +147,6 @@
 
 #define CONFIG_SYS_LOAD_ADDR		CONFIG_LOADADDR
 
-#define CONFIG_SYS_HZ		1000
 #define CONFIG_CMDLINE_EDITING
 
 /* Physical Memory Map */
diff --git a/include/configs/mx53loco.h b/include/configs/mx53loco.h
index bd2fa43b95..5859f360e0 100644
--- a/include/configs/mx53loco.h
+++ b/include/configs/mx53loco.h
@@ -65,16 +65,15 @@
 #define CONFIG_USB_STORAGE
 #define CONFIG_USB_HOST_ETHER
 #define CONFIG_USB_ETHER_ASIX
+#define CONFIG_USB_ETHER_MCS7830
 #define CONFIG_USB_ETHER_SMSC95XX
 #define CONFIG_MXC_USB_PORT	1
 #define CONFIG_MXC_USB_PORTSC	(PORT_PTS_UTMI | PORT_PTS_PTW)
 #define CONFIG_MXC_USB_FLAGS	0
 
 /* I2C Configs */
-#define CONFIG_HARD_I2C
-#define CONFIG_I2C_MXC
-#define CONFIG_SYS_I2C_BASE		I2C1_BASE_ADDR
-#define CONFIG_SYS_I2C_SPEED		100000
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_MXC
 
 /* PMIC Controller */
 #define CONFIG_POWER
@@ -105,7 +104,7 @@
 
 #define CONFIG_EXTRA_ENV_SETTINGS \
 	"script=boot.scr\0" \
-	"uimage=uImage\0" \
+	"image=zImage\0" \
 	"fdt_file=imx53-qsb.dtb\0" \
 	"fdt_addr=0x71000000\0" \
 	"boot_fdt=try\0" \
@@ -118,22 +117,22 @@
 		"fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
 	"bootscript=echo Running bootscript from mmc ...; " \
 		"source\0" \
-	"loaduimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${uimage}\0" \
+	"loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
 	"loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
 	"mmcboot=echo Booting from mmc ...; " \
 		"run mmcargs; " \
 		"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
 			"if run loadfdt; then " \
-				"bootm ${loadaddr} - ${fdt_addr}; " \
+				"bootz ${loadaddr} - ${fdt_addr}; " \
 			"else " \
 				"if test ${boot_fdt} = try; then " \
-					"bootm; " \
+					"bootz; " \
 				"else " \
 					"echo WARN: Cannot load the DT; " \
 				"fi; " \
 			"fi; " \
 		"else " \
-			"bootm; " \
+			"bootz; " \
 		"fi;\0" \
 	"netargs=setenv bootargs console=ttymxc0,${baudrate} " \
 		"root=/dev/nfs " \
@@ -145,20 +144,20 @@
 		"else " \
 			"setenv get_cmd tftp; " \
 		"fi; " \
-		"${get_cmd} ${uimage}; " \
+		"${get_cmd} ${image}; " \
 		"if test ${boot_fdt} = yes ||  test ${boot_fdt} = try; then " \
 			"if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
-				"bootm ${loadaddr} - ${fdt_addr}; " \
+				"bootz ${loadaddr} - ${fdt_addr}; " \
 			"else " \
 				"if test ${boot_fdt} = try; then " \
-					"bootm; " \
+					"bootz; " \
 				"else " \
 					"echo ERROR: Cannot load the DT; " \
 					"exit; " \
 				"fi; " \
 			"fi; " \
 		"else " \
-			"bootm; " \
+			"bootz; " \
 		"fi;\0"
 
 #define CONFIG_BOOTCOMMAND \
@@ -166,7 +165,7 @@
 		"if run loadbootscript; then " \
 			"run bootscript; " \
 		"else " \
-			"if run loaduimage; then " \
+			"if run loadimage; then " \
 				"run mmcboot; " \
 			"else run netboot; " \
 			"fi; " \
@@ -178,7 +177,6 @@
 /* Miscellaneous configurable options */
 #define CONFIG_SYS_LONGHELP		/* undef to save memory */
 #define CONFIG_SYS_HUSH_PARSER		/* use "hush" command parser */
-#define CONFIG_SYS_PROMPT		"MX53LOCO U-Boot > "
 #define CONFIG_AUTO_COMPLETE
 #define CONFIG_SYS_CBSIZE		512	/* Console I/O Buffer Size */
 
@@ -192,16 +190,15 @@
 
 #define CONFIG_SYS_LOAD_ADDR		CONFIG_LOADADDR
 
-#define CONFIG_SYS_HZ		1000
 #define CONFIG_CMDLINE_EDITING
 
 /* Physical Memory Map */
 #define CONFIG_NR_DRAM_BANKS	2
-#define PHYS_SDRAM_1		CSD0_BASE_ADDR
-#define PHYS_SDRAM_1_SIZE	(512 * 1024 * 1024)
-#define PHYS_SDRAM_2		CSD1_BASE_ADDR
-#define PHYS_SDRAM_2_SIZE	(512 * 1024 * 1024)
-#define PHYS_SDRAM_SIZE         (PHYS_SDRAM_1_SIZE + PHYS_SDRAM_2_SIZE)
+#define PHYS_SDRAM_1			CSD0_BASE_ADDR
+#define PHYS_SDRAM_1_SIZE		(gd->bd->bi_dram[0].size)
+#define PHYS_SDRAM_2			CSD1_BASE_ADDR
+#define PHYS_SDRAM_2_SIZE		(gd->bd->bi_dram[1].size)
+#define PHYS_SDRAM_SIZE			(gd->ram_size)
 
 #define CONFIG_SYS_SDRAM_BASE		(PHYS_SDRAM_1)
 #define CONFIG_SYS_INIT_RAM_ADDR	(IRAM_BASE_ADDR)
diff --git a/include/configs/mx53smd.h b/include/configs/mx53smd.h
index 12b2c0de86..a04e7c7a3e 100644
--- a/include/configs/mx53smd.h
+++ b/include/configs/mx53smd.h
@@ -34,10 +34,8 @@
 
 /* I2C Configs */
 #define CONFIG_CMD_I2C
-#define CONFIG_HARD_I2C
-#define CONFIG_I2C_MXC
-#define CONFIG_SYS_I2C_BASE		I2C2_BASE_ADDR
-#define CONFIG_SYS_I2C_SPEED            100000
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_MXC
 
 /* MMC Configs */
 #define CONFIG_FSL_ESDHC
@@ -121,7 +119,6 @@
 /* Miscellaneous configurable options */
 #define CONFIG_SYS_LONGHELP		/* undef to save memory */
 #define CONFIG_SYS_HUSH_PARSER		/* use "hush" command parser */
-#define CONFIG_SYS_PROMPT		"MX53SMD U-Boot > "
 #define CONFIG_AUTO_COMPLETE
 #define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size */
 
@@ -135,7 +132,6 @@
 
 #define CONFIG_SYS_LOAD_ADDR		CONFIG_LOADADDR
 
-#define CONFIG_SYS_HZ		1000
 #define CONFIG_CMDLINE_EDITING
 
 /* Physical Memory Map */
diff --git a/include/configs/mx6_common.h b/include/configs/mx6_common.h
index 674bcd3f6d..8a8920f6cc 100644
--- a/include/configs/mx6_common.h
+++ b/include/configs/mx6_common.h
@@ -20,5 +20,13 @@
 #define CONFIG_ARM_ERRATA_742230
 #define CONFIG_ARM_ERRATA_743622
 #define CONFIG_ARM_ERRATA_751472
+#define CONFIG_ARM_ERRATA_794072
+#define CONFIG_ARM_ERRATA_761320
+#define CONFIG_BOARD_POSTCLK_INIT
+
+#ifndef CONFIG_SYS_L2CACHE_OFF
+#define CONFIG_SYS_L2_PL310
+#define CONFIG_SYS_PL310_BASE	L2_PL310_BASE
+#endif
 
 #endif
diff --git a/include/configs/mx6qarm2.h b/include/configs/mx6qarm2.h
index ef3058c18f..fd651cfa50 100644
--- a/include/configs/mx6qarm2.h
+++ b/include/configs/mx6qarm2.h
@@ -72,7 +72,7 @@
 
 #define CONFIG_EXTRA_ENV_SETTINGS \
 	"script=boot.scr\0" \
-	"uimage=uImage\0" \
+	"image=zImage\0" \
 	"console=ttymxc3\0" \
 	"fdt_high=0xffffffff\0" \
 	"initrd_high=0xffffffff\0" \
@@ -85,16 +85,16 @@
 		"fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
 	"bootscript=echo Running bootscript from mmc ...; " \
 		"source\0" \
-	"loaduimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${uimage}\0" \
+	"loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
 	"mmcboot=echo Booting from mmc ...; " \
 		"run mmcargs; " \
-		"bootm\0" \
+		"bootz\0" \
 	"netargs=setenv bootargs console=${console},${baudrate} " \
 		"root=/dev/nfs " \
 		"ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
 	"netboot=echo Booting from net ...; " \
 		"run netargs; " \
-		"dhcp ${uimage}; bootm\0" \
+		"dhcp ${image}; bootz\0" \
 
 #define CONFIG_BOOTCOMMAND \
 	"mmc dev ${mmcdev};" \
@@ -102,7 +102,7 @@
 		"if run loadbootscript; then " \
 			"run bootscript; " \
 		"else " \
-			"if run loaduimage; then " \
+			"if run loadimage; then " \
 				"run mmcboot; " \
 			"else run netboot; " \
 			"fi; " \
@@ -114,7 +114,6 @@
 /* Miscellaneous configurable options */
 #define CONFIG_SYS_LONGHELP
 #define CONFIG_SYS_HUSH_PARSER
-#define CONFIG_SYS_PROMPT		"MX6QARM2 U-Boot > "
 #define CONFIG_AUTO_COMPLETE
 #define CONFIG_SYS_CBSIZE		256
 
@@ -127,7 +126,6 @@
 #define CONFIG_SYS_MEMTEST_END		0x10010000
 
 #define CONFIG_SYS_LOAD_ADDR		CONFIG_LOADADDR
-#define CONFIG_SYS_HZ			1000
 
 #define CONFIG_CMDLINE_EDITING
 
diff --git a/include/configs/mx6qsabreauto.h b/include/configs/mx6qsabreauto.h
index 5530fc6f2b..bd0144f5cb 100644
--- a/include/configs/mx6qsabreauto.h
+++ b/include/configs/mx6qsabreauto.h
@@ -23,7 +23,8 @@
 #define CONFIG_USB_STORAGE
 #define CONFIG_USB_HOST_ETHER
 #define CONFIG_USB_ETHER_ASIX
-#define CONFIG_MXC_USB_PORT	1
+#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
+#define CONFIG_EHCI_HCD_INIT_AFTER_RESET	/* For OTG port */
 #define CONFIG_MXC_USB_PORTSC	(PORT_PTS_UTMI | PORT_PTS_PTW)
 #define CONFIG_MXC_USB_FLAGS	0
 
@@ -36,8 +37,11 @@
 
 /* I2C Configs */
 #define CONFIG_CMD_I2C
-#define CONFIG_I2C_MULTI_BUS
-#define CONFIG_I2C_MXC
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_MXC
 #define CONFIG_SYS_I2C_SPEED		100000
 
+#define CONFIG_OF_SEPARATE
+#define CONFIG_DEFAULT_DEVICE_TREE   imx6q-sabreauto
+
 #endif                         /* __MX6QSABREAUTO_CONFIG_H */
diff --git a/include/configs/mx6sabre_common.h b/include/configs/mx6sabre_common.h
index bf6113b2aa..7a2c172d4a 100644
--- a/include/configs/mx6sabre_common.h
+++ b/include/configs/mx6sabre_common.h
@@ -12,12 +12,13 @@
 #define CONFIG_MX6
 
 #include "mx6_common.h"
-#include <asm/sizes.h>
+#include <linux/sizes.h>
 
 #define CONFIG_DISPLAY_CPUINFO
 #define CONFIG_DISPLAY_BOARDINFO
 
 #include <asm/arch/imx-regs.h>
+#include <asm/imx-common/gpio.h>
 
 #define CONFIG_CMDLINE_TAG
 #define CONFIG_SETUP_MEMORY_TAGS
@@ -33,6 +34,11 @@
 
 #define CONFIG_MXC_UART
 
+#define CONFIG_CMD_FUSE
+#ifdef CONFIG_CMD_FUSE
+#define CONFIG_MXC_OCOTP
+#endif
+
 /* MMC Configs */
 #define CONFIG_FSL_ESDHC
 #define CONFIG_FSL_USDHC
@@ -60,6 +66,17 @@
 #define CONFIG_PHYLIB
 #define CONFIG_PHY_ATHEROS
 
+#define CONFIG_CMD_SF
+#ifdef CONFIG_CMD_SF
+#define CONFIG_SPI_FLASH
+#define CONFIG_SPI_FLASH_STMICRO
+#define CONFIG_MXC_SPI
+#define CONFIG_SF_DEFAULT_BUS		0
+#define CONFIG_SF_DEFAULT_CS		(0 | (IMX_GPIO_NR(4, 9) << 8))
+#define CONFIG_SF_DEFAULT_SPEED		20000000
+#define CONFIG_SF_DEFAULT_MODE		SPI_MODE_0
+#endif
+
 /* allow to overwrite serial and ethaddr */
 #define CONFIG_ENV_OVERWRITE
 #define CONFIG_CONS_INDEX              1
@@ -78,11 +95,33 @@
 #define CONFIG_LOADADDR                        0x12000000
 #define CONFIG_SYS_TEXT_BASE           0x17800000
 
+#ifdef CONFIG_SUPPORT_EMMC_BOOT
+#define EMMC_ENV \
+	"emmcdev=2\0" \
+	"update_emmc_firmware=" \
+		"if test ${ip_dyn} = yes; then " \
+			"setenv get_cmd dhcp; " \
+		"else " \
+			"setenv get_cmd tftp; " \
+		"fi; " \
+		"if ${get_cmd} ${update_sd_firmware_filename}; then " \
+			"if mmc dev ${emmcdev} && " \
+				"mmc open ${emmcdev} 1; then "	\
+				"setexpr fw_sz ${filesize} / 0x200; " \
+				"setexpr fw_sz ${fw_sz} + 1; "	\
+				"mmc write ${loadaddr} 0x2 ${fw_sz}; " \
+				"mmc close ${emmcdev} 1; " \
+			"fi; "	\
+		"fi\0"
+#else
+#define EMMC_ENV ""
+#endif
+
 #define CONFIG_EXTRA_ENV_SETTINGS \
 	"script=boot.scr\0" \
-	"uimage=uImage\0" \
+	"image=zImage\0" \
 	"fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \
-	"fdt_addr=0x11000000\0" \
+	"fdt_addr=0x18000000\0" \
 	"boot_fdt=try\0" \
 	"ip_dyn=yes\0" \
 	"console=" CONFIG_CONSOLE_DEV "\0" \
@@ -104,28 +143,29 @@
 				"mmc write ${loadaddr} 0x2 ${fw_sz}; " \
 			"fi; "	\
 		"fi\0" \
+	EMMC_ENV	  \
 	"mmcargs=setenv bootargs console=${console},${baudrate} " \
 		"root=${mmcroot}\0" \
 	"loadbootscript=" \
 		"fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
 	"bootscript=echo Running bootscript from mmc ...; " \
 		"source\0" \
-	"loaduimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${uimage}\0" \
+	"loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
 	"loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
 	"mmcboot=echo Booting from mmc ...; " \
 		"run mmcargs; " \
 		"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
 			"if run loadfdt; then " \
-				"bootm ${loadaddr} - ${fdt_addr}; " \
+				"bootz ${loadaddr} - ${fdt_addr}; " \
 			"else " \
 				"if test ${boot_fdt} = try; then " \
-					"bootm; " \
+					"bootz; " \
 				"else " \
 					"echo WARN: Cannot load the DT; " \
 				"fi; " \
 			"fi; " \
 		"else " \
-			"bootm; " \
+			"bootz; " \
 		"fi;\0" \
 	"netargs=setenv bootargs console=${console},${baudrate} " \
 		"root=/dev/nfs " \
@@ -137,19 +177,19 @@
 		"else " \
 			"setenv get_cmd tftp; " \
 		"fi; " \
-		"${get_cmd} ${uimage}; " \
+		"${get_cmd} ${image}; " \
 		"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
 			"if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
-				"bootm ${loadaddr} - ${fdt_addr}; " \
+				"bootz ${loadaddr} - ${fdt_addr}; " \
 			"else " \
 				"if test ${boot_fdt} = try; then " \
-					"bootm; " \
+					"bootz; " \
 				"else " \
 					"echo WARN: Cannot load the DT; " \
 				"fi; " \
 			"fi; " \
 		"else " \
-			"bootm; " \
+			"bootz; " \
 		"fi;\0"
 
 #define CONFIG_BOOTCOMMAND \
@@ -158,7 +198,7 @@
 		"if run loadbootscript; then " \
 		"run bootscript; " \
 		"else " \
-			"if run loaduimage; then " \
+			"if run loadimage; then " \
 				"run mmcboot; " \
 			"else run netboot; " \
 			"fi; " \
@@ -171,7 +211,6 @@
 #define CONFIG_SYS_LONGHELP
 #define CONFIG_SYS_HUSH_PARSER
 #define CONFIG_SYS_PROMPT_HUSH_PS2     "> "
-#define CONFIG_SYS_PROMPT              "U-Boot > "
 #define CONFIG_AUTO_COMPLETE
 #define CONFIG_SYS_CBSIZE              256
 
@@ -185,7 +224,6 @@
 #define CONFIG_SYS_MEMTEST_SCRATCH     0x10800000
 
 #define CONFIG_SYS_LOAD_ADDR           CONFIG_LOADADDR
-#define CONFIG_SYS_HZ                  1000
 
 #define CONFIG_CMDLINE_EDITING
 #define CONFIG_STACKSIZE               (128 * 1024)
diff --git a/include/configs/mx6sabresd.h b/include/configs/mx6sabresd.h
index 3229bc70d8..5d02d23ec7 100644
--- a/include/configs/mx6sabresd.h
+++ b/include/configs/mx6sabresd.h
@@ -23,6 +23,8 @@
 #endif
 #define PHYS_SDRAM_SIZE		(1u * 1024 * 1024 * 1024)
 
+#define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */
+
 #include "mx6sabre_common.h"
 
 #define CONFIG_SYS_FSL_USDHC_NUM	3
@@ -46,4 +48,14 @@
 #define CONFIG_IPUV3_CLK 260000000
 #define CONFIG_IMX_HDMI
 
+#define CONFIG_CMD_PCI
+#ifdef CONFIG_CMD_PCI
+#define CONFIG_PCI
+#define CONFIG_PCI_PNP
+#define CONFIG_PCI_SCAN_SHOW
+#define CONFIG_PCIE_IMX
+#define CONFIG_PCIE_IMX_PERST_GPIO	IMX_GPIO_NR(7, 12)
+#define CONFIG_PCIE_IMX_POWER_GPIO	IMX_GPIO_NR(3, 19)
+#endif
+
 #endif                         /* __MX6QSABRESD_CONFIG_H */
diff --git a/include/configs/mx6slevk.h b/include/configs/mx6slevk.h
index 792f17cea4..1876dbf35a 100644
--- a/include/configs/mx6slevk.h
+++ b/include/configs/mx6slevk.h
@@ -10,7 +10,8 @@
 #define __CONFIG_H
 
 #include <asm/arch/imx-regs.h>
-#include <asm/sizes.h>
+#include <linux/sizes.h>
+#include "mx6_common.h"
 
 #define CONFIG_MX6
 #define CONFIG_DISPLAY_CPUINFO
@@ -75,12 +76,12 @@
 
 #define CONFIG_EXTRA_ENV_SETTINGS \
 	"script=boot.scr\0" \
-	"uimage=uImage\0" \
+	"image=zImage\0" \
 	"console=ttymxc0\0" \
 	"fdt_high=0xffffffff\0" \
 	"initrd_high=0xffffffff\0" \
 	"fdt_file=imx6sl-evk.dtb\0" \
-	"fdt_addr=0x81000000\0" \
+	"fdt_addr=0x88000000\0" \
 	"boot_fdt=try\0" \
 	"ip_dyn=yes\0" \
 	"mmcdev=0\0" \
@@ -92,22 +93,22 @@
 		"fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
 	"bootscript=echo Running bootscript from mmc ...; " \
 		"source\0" \
-	"loaduimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${uimage}\0" \
+	"loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
 	"loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
 	"mmcboot=echo Booting from mmc ...; " \
 		"run mmcargs; " \
 		"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
 			"if run loadfdt; then " \
-				"bootm ${loadaddr} - ${fdt_addr}; " \
+				"bootz ${loadaddr} - ${fdt_addr}; " \
 			"else " \
 				"if test ${boot_fdt} = try; then " \
-					"bootm; " \
+					"bootz; " \
 				"else " \
 					"echo WARN: Cannot load the DT; " \
 				"fi; " \
 			"fi; " \
 		"else " \
-			"bootm; " \
+			"bootz; " \
 		"fi;\0" \
 	"netargs=setenv bootargs console=${console},${baudrate} " \
 		"root=/dev/nfs " \
@@ -119,19 +120,19 @@
 		"else " \
 			"setenv get_cmd tftp; " \
 		"fi; " \
-		"${get_cmd} ${uimage}; " \
+		"${get_cmd} ${image}; " \
 		"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
 			"if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
-				"bootm ${loadaddr} - ${fdt_addr}; " \
+				"bootz ${loadaddr} - ${fdt_addr}; " \
 			"else " \
 				"if test ${boot_fdt} = try; then " \
-					"bootm; " \
+					"bootz; " \
 				"else " \
 					"echo WARN: Cannot load the DT; " \
 				"fi; " \
 			"fi; " \
 		"else " \
-			"bootm; " \
+			"bootz; " \
 		"fi;\0"
 
 #define CONFIG_BOOTCOMMAND \
@@ -140,7 +141,7 @@
 		   "if run loadbootscript; then " \
 			   "run bootscript; " \
 		   "else " \
-			   "if run loaduimage; then " \
+			   "if run loadimage; then " \
 				   "run mmcboot; " \
 			   "else run netboot; " \
 			   "fi; " \
@@ -150,7 +151,6 @@
 /* Miscellaneous configurable options */
 #define CONFIG_SYS_LONGHELP
 #define CONFIG_SYS_HUSH_PARSER
-#define CONFIG_SYS_PROMPT		"=> "
 #define CONFIG_AUTO_COMPLETE
 #define CONFIG_SYS_CBSIZE		256
 
@@ -163,7 +163,6 @@
 #define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_MEMTEST_START + SZ_512M)
 
 #define CONFIG_SYS_LOAD_ADDR		CONFIG_LOADADDR
-#define CONFIG_SYS_HZ			1000
 
 #define CONFIG_CMDLINE_EDITING
 #define CONFIG_STACKSIZE		SZ_128K
diff --git a/include/configs/mxs.h b/include/configs/mxs.h
index 124dc1e6cb..ba55177e72 100644
--- a/include/configs/mxs.h
+++ b/include/configs/mxs.h
@@ -41,9 +41,6 @@
  * CPU specifics
  */
 
-/* Ticks per second */
-#define CONFIG_SYS_HZ		1000
-
 /* MXS uses FDT */
 #define CONFIG_OF_LIBFDT
 
@@ -62,7 +59,6 @@
 
 /* Memory sizes */
 #define CONFIG_SYS_MALLOC_LEN		0x00400000	/* 4 MB for malloc */
-#define CONFIG_SYS_GBL_DATA_SIZE	128		/* Initial data */
 #define CONFIG_SYS_MEMTEST_START	0x40000000	/* Memtest start adr */
 #define CONFIG_SYS_MEMTEST_END		0x40400000	/* 4 MB RAM test */
 
@@ -84,13 +80,20 @@
  * We need to sacrifice first 4 bytes of RAM here to avoid triggering some
  * strange BUG in ROM corrupting first 4 bytes of RAM when loading U-Boot
  * binary. In case there was more of this mess, 0x100 bytes are skipped.
+ *
+ * In case of a HAB boot, we cannot for some weird reason use the first 4KiB
+ * of DRAM when loading. Moreover, we use the first 4 KiB for IVT and CST
+ * blocks, thus U-Boot starts at offset +8 KiB of DRAM start.
+ *
+ * As for the SPL, we must avoid the first 4 KiB as well, but we load the
+ * IVT and CST to 0x8000, so we don't need to waste the subsequent 4 KiB.
  */
-#define CONFIG_SYS_TEXT_BASE		0x40000100
+#define CONFIG_SYS_TEXT_BASE		0x40002000
+#define CONFIG_SPL_TEXT_BASE		0x00001000
 
 /* U-Boot general configuration */
 #define CONFIG_SYS_LONGHELP
 #ifndef CONFIG_SYS_PROMPT
-#define CONFIG_SYS_PROMPT	"=> "
 #endif
 #define CONFIG_SYS_CBSIZE	1024		/* Console I/O buffer size */
 #define CONFIG_SYS_PBSIZE	\
@@ -179,6 +182,11 @@
 #define CONFIG_SYS_NAND_5_ADDR_CYCLE
 #endif
 
+/* OCOTP */
+#ifdef CONFIG_CMD_FUSE
+#define CONFIG_MXS_OCOTP
+#endif
+
 /* SPI */
 #ifdef CONFIG_CMD_SPI
 #define CONFIG_HARD_SPI
diff --git a/include/configs/neo.h b/include/configs/neo.h
index 62ea8eca86..d549985886 100644
--- a/include/configs/neo.h
+++ b/include/configs/neo.h
@@ -10,7 +10,6 @@
 
 
 #define CONFIG_405EP		1	/* this is a PPC405 CPU */
-#define CONFIG_4xx		1	/*  member of PPC4xx family */
 #define CONFIG_NEO	        1	/*  on a Neo board */
 
 #define	CONFIG_SYS_TEXT_BASE	0xFFFC0000
diff --git a/include/configs/nhk8815.h b/include/configs/nhk8815.h
index 181a6bfd41..4d3428cb81 100644
--- a/include/configs/nhk8815.h
+++ b/include/configs/nhk8815.h
@@ -76,7 +76,6 @@
 #define CONFIG_BOARD_LATE_INIT	/* call board_late_init during start up */
 
 /* timing informazion */
-#define CONFIG_SYS_HZ		1000 /* Mandatory... */
 #define CONFIG_SYS_TIMERBASE	0x101E2000
 
 /* serial port (PL011) configuration */
diff --git a/include/configs/nios2-generic.h b/include/configs/nios2-generic.h
index 3f34496065..1578b010b9 100644
--- a/include/configs/nios2-generic.h
+++ b/include/configs/nios2-generic.h
@@ -39,7 +39,6 @@
 #define CONFIG_SYS_LOW_RES_TIMER
 #define CONFIG_SYS_NIOS_TMRBASE	CONFIG_SYS_TIMER_BASE
 #define CONFIG_SYS_NIOS_TMRIRQ		CONFIG_SYS_TIMER_IRQ
-#define CONFIG_SYS_HZ			1000	/* Always 1000 */
 #define CONFIG_SYS_NIOS_TMRMS		10	/* Desired period (msec)*/
 #define CONFIG_SYS_NIOS_TMRCNT \
 	(CONFIG_SYS_NIOS_TMRMS * (CONFIG_SYS_TIMER_FREQ / 1000) - 1)
@@ -120,7 +119,6 @@
  * MISC
  */
 #define CONFIG_SYS_LONGHELP		/* Provide extended help */
-#define CONFIG_SYS_PROMPT		"==> "	/* Command prompt	*/
 #define CONFIG_SYS_CBSIZE		256	/* Console I/O buf size */
 #define CONFIG_SYS_MAXARGS		16	/* Max command args	*/
 #define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE /* Bootarg buf size */
diff --git a/include/configs/nitrogen6x.h b/include/configs/nitrogen6x.h
index 3454b862a8..f7e7315a9b 100644
--- a/include/configs/nitrogen6x.h
+++ b/include/configs/nitrogen6x.h
@@ -10,6 +10,7 @@
 #ifndef __CONFIG_H
 #define __CONFIG_H
 
+#include "mx6_common.h"
 #define CONFIG_MX6
 #define CONFIG_DISPLAY_CPUINFO
 #define CONFIG_DISPLAY_BOARDINFO
@@ -30,6 +31,12 @@
 #define CONFIG_BOARD_EARLY_INIT_F
 #define CONFIG_MISC_INIT_R
 #define CONFIG_MXC_GPIO
+#define CONFIG_CI_UDC
+#define CONFIG_USBD_HS
+#define CONFIG_USB_GADGET_DUALSPEED
+#define CONFIG_USB_ETHER
+#define CONFIG_USB_ETH_CDC
+#define CONFIG_NETCONSOLE
 
 #define CONFIG_CMD_FUSE
 #ifdef CONFIG_CMD_FUSE
@@ -52,20 +59,10 @@
 
 /* I2C Configs */
 #define CONFIG_CMD_I2C
-#define CONFIG_I2C_MULTI_BUS
-#define CONFIG_I2C_MXC
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_MXC
 #define CONFIG_SYS_I2C_SPEED		100000
 
-/* OCOTP Configs */
-#define CONFIG_CMD_IMXOTP
-#ifdef CONFIG_CMD_IMXOTP
-#define CONFIG_IMX_OTP
-#define IMX_OTP_BASE			OCOTP_BASE_ADDR
-#define IMX_OTP_ADDR_MAX		0x7F
-#define IMX_OTP_DATA_ERROR_VAL		0xBADABADA
-#define IMX_OTPWRITE_ENABLED
-#endif
-
 /* MMC Configs */
 #define CONFIG_FSL_ESDHC
 #define CONFIG_FSL_USDHC
@@ -118,8 +115,10 @@
 #define CONFIG_USB_STORAGE
 #define CONFIG_USB_HOST_ETHER
 #define CONFIG_USB_ETHER_ASIX
+#define CONFIG_USB_ETHER_MCS7830
 #define CONFIG_USB_ETHER_SMSC95XX
-#define CONFIG_MXC_USB_PORT	1
+#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
+#define CONFIG_EHCI_HCD_INIT_AFTER_RESET	/* For OTG port */
 #define CONFIG_MXC_USB_PORTSC	(PORT_PTS_UTMI | PORT_PTS_PTW)
 #define CONFIG_MXC_USB_FLAGS	0
 
@@ -182,7 +181,7 @@
 	"fdt_high=0xffffffff\0" \
 	"initrd_high=0xffffffff\0" \
 	"fdt_file=imx6q-sabrelite.dtb\0" \
-	"fdt_addr=0x11000000\0" \
+	"fdt_addr=0x18000000\0" \
 	"boot_fdt=try\0" \
 	"ip_dyn=yes\0" \
 	"mmcdev=0\0" \
@@ -299,7 +298,6 @@
 #define CONFIG_SYS_MEMTEST_SCRATCH     0x10800000
 
 #define CONFIG_SYS_LOAD_ADDR	       CONFIG_LOADADDR
-#define CONFIG_SYS_HZ		       1000
 
 #define CONFIG_CMDLINE_EDITING
 
@@ -355,4 +353,14 @@
 #define CONFIG_SUPPORT_RAW_INITRD
 #define CONFIG_CMD_FS_GENERIC
 
+/*
+ * PCI express
+ */
+#ifdef CONFIG_CMD_PCI
+#define CONFIG_PCI
+#define CONFIG_PCI_PNP
+#define CONFIG_PCI_SCAN_SHOW
+#define CONFIG_PCIE_IMX
+#endif
+
 #endif	       /* __CONFIG_H */
diff --git a/include/configs/nokia_rx51.h b/include/configs/nokia_rx51.h
index 64db0eb944..e0c0fac8e1 100644
--- a/include/configs/nokia_rx51.h
+++ b/include/configs/nokia_rx51.h
@@ -157,10 +157,10 @@
 #undef CONFIG_CMD_SETGETDCR		/* DCR support on 4xx */
 
 #define CONFIG_OMAP3_SPI
-#define CONFIG_HARD_I2C
-#define CONFIG_SYS_I2C_SPEED		100000
-#define CONFIG_SYS_I2C_SLAVE		1
-#define CONFIG_DRIVER_OMAP34XX_I2C
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_OMAP24_I2C_SPEED	100000
+#define CONFIG_SYS_OMAP24_I2C_SLAVE	1
+#define CONFIG_SYS_I2C_OMAP34XX
 
 /*
  * TWL4030
@@ -426,7 +426,6 @@ int rx51_kp_getc(void);
  */
 #define CONFIG_SYS_TIMERBASE		(OMAP34XX_GPT2)
 #define CONFIG_SYS_PTV			2	/* Divisor: 2^(PTV+1) => 8 */
-#define CONFIG_SYS_HZ			1000
 
 /*
  * Stack sizes
diff --git a/include/configs/o2dnt-common.h b/include/configs/o2dnt-common.h
index f079289c5a..133dc6f8cd 100644
--- a/include/configs/o2dnt-common.h
+++ b/include/configs/o2dnt-common.h
@@ -16,7 +16,6 @@
 /*
  * High Level Configuration Options
  */
-#define CONFIG_MPC5xxx		1	/* This is an MPC5xxx CPU */
 #define CONFIG_MPC5200
 
 #define CONFIG_SYS_MPC5XXX_CLKIN	33000000 /* running at 33.000000MHz */
@@ -276,10 +275,8 @@
 #define CONFIG_SYS_INIT_RAM_END		MPC5XXX_SRAM_SIZE
 #endif
 
-/* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_SIZE	128
 #define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - \
-					 CONFIG_SYS_GBL_DATA_SIZE)
+					 GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 #define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_TEXT_BASE
@@ -311,7 +308,6 @@
  * Miscellaneous configurable options
  */
 #define CONFIG_SYS_LONGHELP			/* undef to save memory	    */
-#define CONFIG_SYS_PROMPT		"=> "	/* Monitor Command Prompt   */
 #define CONFIG_CMDLINE_EDITING
 #define CONFIG_SYS_HUSH_PARSER
 
@@ -332,7 +328,6 @@
 #define CONFIG_SYS_LOAD_ADDR		0x100000
 
 /* decrementer freq: 1 ms ticks */
-#define CONFIG_SYS_HZ			1000
 
 /*
  * Various low-level settings
diff --git a/include/configs/ocotea.h b/include/configs/ocotea.h
index f3fb5852f9..4ff2f05c88 100644
--- a/include/configs/ocotea.h
+++ b/include/configs/ocotea.h
@@ -26,7 +26,6 @@
 #define CONFIG_OCOTEA		1	    /* Board is ebony		*/
 #define CONFIG_440GX		1	    /* Specifc GX support	*/
 #define CONFIG_440		1	    /* ... PPC440 family	*/
-#define CONFIG_4xx		1	    /* ... PPC4xx family	*/
 #define CONFIG_BOARD_EARLY_INIT_F 1	    /* Call board_pre_init	*/
 #define CONFIG_SYS_CLK_FREQ	33333333    /* external freq to pll	*/
 
diff --git a/include/configs/omap1510.h b/include/configs/omap1510.h
index a578edd0d8..41f7973f2b 100644
--- a/include/configs/omap1510.h
+++ b/include/configs/omap1510.h
@@ -10,7 +10,7 @@
  * SPDX-License-Identifier:	GPL-2.0+
  */
 
-#include <asm/sizes.h>
+#include <linux/sizes.h>
 
 /*
   There are 2 sets of general I/O -->
diff --git a/include/configs/omap3_beagle.h b/include/configs/omap3_beagle.h
index 9fcd50b523..0b57421537 100644
--- a/include/configs/omap3_beagle.h
+++ b/include/configs/omap3_beagle.h
@@ -118,14 +118,15 @@
 #define CONFIG_USB_EHCI_OMAP
 #define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO	147
 
-#define CONFIG_USB_ULPI
-#define CONFIG_USB_ULPI_VIEWPORT_OMAP
-
 #define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3
 #define CONFIG_USB_HOST_ETHER
-#define CONFIG_USB_ETHER_SMSC95XX
 #define CONFIG_USB_ETHER_ASIX
+#define CONFIG_USB_ETHER_MCS7830
+#define CONFIG_USB_ETHER_SMSC95XX
 
+/* GPIO banks */
+#define CONFIG_OMAP3_GPIO_5		/* GPIO128..159 is in GPIO bank 5 */
+#define CONFIG_OMAP3_GPIO_6		/* GPIO160..191 is in GPIO bank 6 */
 
 /* commands to include */
 #include <config_cmd_default.h>
@@ -161,11 +162,10 @@
 #undef CONFIG_CMD_IMLS		/* List all found images	*/
 
 #define CONFIG_SYS_NO_FLASH
-#define CONFIG_HARD_I2C			1
-#define CONFIG_SYS_I2C_SPEED		100000
-#define CONFIG_SYS_I2C_SLAVE		1
-#define CONFIG_I2C_MULTI_BUS		1
-#define CONFIG_DRIVER_OMAP34XX_I2C	1
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_OMAP24_I2C_SPEED	100000
+#define CONFIG_SYS_OMAP24_I2C_SLAVE	1
+#define CONFIG_SYS_I2C_OMAP34XX
 #define CONFIG_VIDEO_OMAP3	/* DSS Support			*/
 
 /*
@@ -184,8 +184,6 @@
 #define CONFIG_SYS_NAND_BASE		NAND_BASE	/* physical address */
 							/* to access nand at */
 							/* CS0 */
-#define GPMC_NAND_ECC_LP_x16_LAYOUT	1
-
 #define CONFIG_SYS_MAX_NAND_DEVICE	1		/* Max number of NAND */
 							/* devices */
 
@@ -242,6 +240,8 @@
 			"setenv fdtfile omap3-beagle.dtb; fi; " \
 		"if test $beaglerev = Cx; then " \
 			"setenv fdtfile omap3-beagle.dtb; fi; " \
+		"if test $beaglerev = C4; then " \
+			"setenv fdtfile omap3-beagle.dtb; fi; " \
 		"if test $beaglerev = xMAB; then " \
 			"setenv fdtfile omap3-beagle-xm.dtb; fi; " \
 		"if test $beaglerev = xMC; then " \
@@ -341,7 +341,6 @@
  */
 #define CONFIG_SYS_TIMERBASE		(OMAP34XX_GPT2)
 #define CONFIG_SYS_PTV			2       /* Divisor: 2^(PTV+1) => 8 */
-#define CONFIG_SYS_HZ			1000
 
 /*-----------------------------------------------------------------------
  * Physical Memory Map
@@ -433,6 +432,7 @@
 						10, 11, 12, 13}
 #define CONFIG_SYS_NAND_ECCSIZE		512
 #define CONFIG_SYS_NAND_ECCBYTES	3
+#define CONFIG_NAND_OMAP_ECCSCHEME	OMAP_ECC_HAM1_CODE_HW
 #define CONFIG_SYS_NAND_U_BOOT_START	CONFIG_SYS_TEXT_BASE
 #define CONFIG_SYS_NAND_U_BOOT_OFFS	0x80000
 
diff --git a/include/configs/omap3_evm.h b/include/configs/omap3_evm.h
index 3ace8bb6e5..b7638fb8a6 100644
--- a/include/configs/omap3_evm.h
+++ b/include/configs/omap3_evm.h
@@ -107,6 +107,7 @@
 						10, 11, 12, 13}
 #define CONFIG_SYS_NAND_ECCSIZE		512
 #define CONFIG_SYS_NAND_ECCBYTES	3
+#define CONFIG_NAND_OMAP_ECCSCHEME	OMAP_ECC_HAM1_CODE_HW
 #define CONFIG_SYS_NAND_U_BOOT_START   CONFIG_SYS_TEXT_BASE
 #define CONFIG_SYS_NAND_U_BOOT_OFFS	0x80000
 
diff --git a/include/configs/omap3_evm_common.h b/include/configs/omap3_evm_common.h
index edf6543443..7f3424b4f0 100644
--- a/include/configs/omap3_evm_common.h
+++ b/include/configs/omap3_evm_common.h
@@ -35,7 +35,6 @@
  */
 #define CONFIG_SYS_TIMERBASE		OMAP34XX_GPT2
 #define CONFIG_SYS_PTV			2	/* Divisor: 2^(PTV+1) => 8 */
-#define CONFIG_SYS_HZ			1000
 
 /* Size of environment - 128KB */
 #define CONFIG_ENV_SIZE			(128 << 10)
@@ -88,11 +87,10 @@
 /*
  * I2C
  */
-#define CONFIG_HARD_I2C
-#define CONFIG_DRIVER_OMAP34XX_I2C
-
-#define CONFIG_SYS_I2C_SPEED		100000
-#define CONFIG_SYS_I2C_SLAVE		1
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_OMAP24_I2C_SPEED	100000
+#define CONFIG_SYS_OMAP24_I2C_SLAVE	1
+#define CONFIG_SYS_I2C_OMAP34XX
 
 /*
  * PISMO support
@@ -210,7 +208,6 @@
 #define CONFIG_SYS_FLASH_BASE		PISMO1_NAND_BASE
 
 #define CONFIG_NAND_OMAP_GPMC
-#define GPMC_NAND_ECC_LP_x16_LAYOUT
 #define CONFIG_ENV_OFFSET		SMNAND_ENV_OFFSET
 #elif defined(CONFIG_CMD_ONENAND)
 #define CONFIG_SYS_FLASH_BASE		PISMO1_ONEN_BASE
diff --git a/include/configs/omap3_evm_quick_nand.h b/include/configs/omap3_evm_quick_nand.h
index 9ecd70d55b..4427e88b7e 100644
--- a/include/configs/omap3_evm_quick_nand.h
+++ b/include/configs/omap3_evm_quick_nand.h
@@ -86,6 +86,7 @@
 						10, 11, 12, 13}
 #define CONFIG_SYS_NAND_ECCSIZE		512
 #define CONFIG_SYS_NAND_ECCBYTES	3
+#define CONFIG_NAND_OMAP_ECCSCHEME	OMAP_ECC_HAM1_CODE_HW
 #define CONFIG_SYS_NAND_U_BOOT_START   CONFIG_SYS_TEXT_BASE
 #define CONFIG_SYS_NAND_U_BOOT_OFFS	0x80000
 
diff --git a/include/configs/omap3_igep00x0.h b/include/configs/omap3_igep00x0.h
new file mode 100644
index 0000000000..d56d5b00cc
--- /dev/null
+++ b/include/configs/omap3_igep00x0.h
@@ -0,0 +1,203 @@
+/*
+ * Common configuration settings for IGEP technology based boards
+ *
+ * (C) Copyright 2012
+ * ISEE 2007 SL, <www.iseebcn.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __IGEP00X0_H
+#define __IGEP00X0_H
+
+#ifdef CONFIG_BOOT_NAND
+#define CONFIG_NAND
+#endif
+
+#define CONFIG_NR_DRAM_BANKS            2
+
+#include <configs/ti_omap3_common.h>
+#include <asm/mach-types.h>
+
+/*
+ * Display CPU and Board information
+ */
+#define CONFIG_DISPLAY_CPUINFO		1
+#define CONFIG_DISPLAY_BOARDINFO	1
+
+#define CONFIG_MISC_INIT_R
+
+#define CONFIG_REVISION_TAG		1
+
+#define CONFIG_SUPPORT_RAW_INITRD
+
+/* define to enable boot progress via leds */
+#if (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0020) || \
+    (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0030)
+#define CONFIG_SHOW_BOOT_PROGRESS
+#endif
+
+/* GPIO banks */
+#define CONFIG_OMAP3_GPIO_3		/* GPIO64 .. 95 is in GPIO bank 3 */
+#define CONFIG_OMAP3_GPIO_5		/* GPIO128..159 is in GPIO bank 5 */
+#define CONFIG_OMAP3_GPIO_6		/* GPIO160..191 is in GPIO bank 6 */
+
+/* USB */
+#define CONFIG_MUSB_UDC			1
+#define CONFIG_USB_OMAP3		1
+#define CONFIG_TWL4030_USB		1
+
+/* USB device configuration */
+#define CONFIG_USB_DEVICE		1
+#define CONFIG_USB_TTY			1
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV	1
+
+/* Change these to suit your needs */
+#define CONFIG_USBD_VENDORID		0x0451
+#define CONFIG_USBD_PRODUCTID		0x5678
+#define CONFIG_USBD_MANUFACTURER	"Texas Instruments"
+#define CONFIG_USBD_PRODUCT_NAME	"IGEP"
+
+#define CONFIG_CMD_CACHE
+#ifdef CONFIG_BOOT_ONENAND
+#define CONFIG_CMD_ONENAND	/* ONENAND support		*/
+#endif
+#if (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0020) || \
+    (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0032)
+#define CONFIG_CMD_NET		/* bootp, tftpboot, rarpboot	*/
+#endif
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_NFS		/* NFS support			*/
+
+/*#undef CONFIG_ENV_IS_NOWHERE*/
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"usbtty=cdc_acm\0" \
+	"loadaddr=0x82000000\0" \
+	"dtbaddr=0x81600000\0" \
+	"bootdir=/boot\0" \
+	"bootfile=zImage\0" \
+	"usbtty=cdc_acm\0" \
+	"console=ttyO2,115200n8\0" \
+	"mpurate=auto\0" \
+	"vram=12M\0" \
+	"dvimode=1024x768MR-16@60\0" \
+	"defaultdisplay=dvi\0" \
+	"mmcdev=0\0" \
+	"mmcroot=/dev/mmcblk0p2 rw\0" \
+	"mmcrootfstype=ext4 rootwait\0" \
+	"nandroot=/dev/mtdblock4 rw\0" \
+	"nandrootfstype=jffs2\0" \
+	"mmcargs=setenv bootargs console=${console} " \
+		"mpurate=${mpurate} " \
+		"vram=${vram} " \
+		"omapfb.mode=dvi:${dvimode} " \
+		"omapfb.debug=y " \
+		"omapdss.def_disp=${defaultdisplay} " \
+		"root=${mmcroot} " \
+		"rootfstype=${mmcrootfstype}\0" \
+	"nandargs=setenv bootargs console=${console} " \
+		"mpurate=${mpurate} " \
+		"vram=${vram} " \
+		"omapfb.mode=dvi:${dvimode} " \
+		"omapfb.debug=y " \
+		"omapdss.def_disp=${defaultdisplay} " \
+		"root=${nandroot} " \
+		"rootfstype=${nandrootfstype}\0" \
+	"loadbootenv=load mmc ${mmcdev} ${loadaddr} uEnv.txt\0" \
+	"importbootenv=echo Importing environment from mmc ...; " \
+		"env import -t $loadaddr $filesize\0" \
+	"loadzimage=load mmc ${mmcdev}:2 ${loadaddr} ${bootdir}/${bootfile}\0" \
+	"loadfdt=load mmc ${mmcdev}:2 ${dtbaddr} ${bootdir}/${dtbfile}\0" \
+	"mmcboot=echo Booting from mmc ...; " \
+		"run mmcargs; " \
+		"bootz ${loadaddr}\0" \
+	"mmcbootfdt=echo Booting with DT from mmc ...; " \
+		"bootz ${loadaddr} - ${dtbaddr}\0" \
+	"nandboot=echo Booting from onenand ...; " \
+		"run nandargs; " \
+		"onenand read ${loadaddr} 280000 400000; " \
+		"bootz ${loadaddr}\0" \
+
+#define CONFIG_BOOTCOMMAND \
+	"mmc dev ${mmcdev}; if mmc rescan; then " \
+		"echo SD/MMC found on device ${mmcdev};" \
+		"if run loadbootenv; then " \
+			"run importbootenv;" \
+		"fi;" \
+		"if test -n $uenvcmd; then " \
+			"echo Running uenvcmd ...;" \
+			"run uenvcmd;" \
+		"fi;" \
+		"if run loadzimage; then " \
+			"if test -n $dtbfile; then " \
+				"if run loadfdt; then " \
+					"run mmcbootfdt;" \
+				"fi;" \
+			"fi;" \
+			"run mmcboot;" \
+		"fi;" \
+	"fi;" \
+	"run nandboot;" \
+
+/*
+ * FLASH and environment organization
+ */
+
+#ifdef CONFIG_BOOT_ONENAND
+#define PISMO1_ONEN_SIZE		GPMC_SIZE_128M /* Configure the PISMO */
+
+#define CONFIG_SYS_ONENAND_BASE		ONENAND_MAP
+
+#define ONENAND_ENV_OFFSET		0x260000 /* environment starts here */
+
+#define CONFIG_ENV_IS_IN_ONENAND	1
+#define CONFIG_ENV_SIZE			(512 << 10) /* Total Size Environment */
+#define CONFIG_ENV_ADDR			ONENAND_ENV_OFFSET
+#endif
+
+#ifdef CONFIG_NAND
+#define PISMO1_NAND_SIZE		GPMC_SIZE_128M /* Configure the PISMO */
+#define CONFIG_ENV_OFFSET		0x260000 /* environment starts here */
+#define CONFIG_ENV_IS_IN_NAND	        1
+#define CONFIG_ENV_SIZE			(512 << 10) /* Total Size Environment */
+#define CONFIG_ENV_ADDR			NAND_ENV_OFFSET
+#endif
+
+/*
+ * SMSC911x Ethernet
+ */
+#if defined(CONFIG_CMD_NET)
+#define CONFIG_SMC911X
+#define CONFIG_SMC911X_32_BIT
+#define CONFIG_SMC911X_BASE	0x2C000000
+#endif /* (CONFIG_CMD_NET) */
+
+/* OneNAND boot config */
+#ifdef CONFIG_BOOT_ONENAND
+#define CONFIG_SPL_ONENAND_SUPPORT
+#define CONFIG_SYS_ONENAND_U_BOOT_OFFS  0x80000
+#define CONFIG_SYS_ONENAND_PAGE_SIZE	2048
+#define CONFIG_SPL_ONENAND_LOAD_ADDR    0x80000
+#define CONFIG_SPL_ONENAND_LOAD_SIZE    \
+	(512 * 1024 - CONFIG_SPL_ONENAND_LOAD_ADDR)
+
+#endif
+
+/* NAND boot config */
+#ifdef CONFIG_NAND
+#define CONFIG_SYS_NAND_5_ADDR_CYCLE
+#define CONFIG_SYS_NAND_PAGE_COUNT	64
+#define CONFIG_SYS_NAND_PAGE_SIZE	2048
+#define CONFIG_SYS_NAND_OOBSIZE		64
+#define CONFIG_SYS_NAND_BLOCK_SIZE	(128*1024)
+#define CONFIG_SYS_NAND_BAD_BLOCK_POS	0
+#define CONFIG_SYS_NAND_ECCPOS		{2, 3, 4, 5, 6, 7, 8, 9,\
+						10, 11, 12, 13}
+#define CONFIG_SYS_NAND_ECCSIZE		512
+#define CONFIG_SYS_NAND_ECCBYTES	3
+#define CONFIG_NAND_OMAP_ECCSCHEME	OMAP_ECC_HAM1_CODE_HW
+#endif
+
+#endif /* __IGEP00X0_H */
diff --git a/include/configs/omap3_logic.h b/include/configs/omap3_logic.h
index 42cea012da..0d03c75ce3 100644
--- a/include/configs/omap3_logic.h
+++ b/include/configs/omap3_logic.h
@@ -118,12 +118,10 @@
 /*
  * I2C
  */
-#define CONFIG_HARD_I2C
-#define CONFIG_DRIVER_OMAP34XX_I2C
-
-#define CONFIG_SYS_I2C_SPEED		100000
-#define CONFIG_SYS_I2C_SLAVE		1
-#define CONFIG_I2C_MULTI_BUS
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_OMAP24_I2C_SPEED	100000
+#define CONFIG_SYS_OMAP24_I2C_SLAVE	1
+#define CONFIG_SYS_I2C_OMAP34XX
 
 /*
  * TWL4030
@@ -265,7 +263,6 @@
  */
 #define CONFIG_SYS_TIMERBASE		(OMAP34XX_GPT2)
 #define CONFIG_SYS_PTV			2	/* Divisor: 2^(PTV+1) => 8 */
-#define CONFIG_SYS_HZ			1000
 
 /*
  * Physical Memory Map
@@ -298,7 +295,6 @@
 
 #if defined(CONFIG_CMD_NAND)
 #define CONFIG_NAND_OMAP_GPMC
-#define GPMC_NAND_ECC_LP_x16_LAYOUT	1
 #define CONFIG_ENV_IS_IN_NAND
 #define CONFIG_ENV_OFFSET		SMNAND_ENV_OFFSET
 #endif
diff --git a/include/configs/omap3_mvblx.h b/include/configs/omap3_mvblx.h
index 73d5d30f01..8d11010f84 100644
--- a/include/configs/omap3_mvblx.h
+++ b/include/configs/omap3_mvblx.h
@@ -128,11 +128,10 @@
 #define CONFIG_CMD_PING
 #define CONFIG_CMD_FPGA
 
-#define CONFIG_HARD_I2C			1
-#define CONFIG_SYS_I2C_SPEED		100000
-#define CONFIG_SYS_I2C_SLAVE		0
-#define CONFIG_DRIVER_OMAP34XX_I2C	1
-#define CONFIG_I2C_MULTI_BUS		1
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_OMAP24_I2C_SPEED	100000
+#define CONFIG_SYS_OMAP24_I2C_SLAVE	1
+#define CONFIG_SYS_I2C_OMAP34XX
 
 /*
  * TWL4030
@@ -236,7 +235,6 @@
  */
 #define CONFIG_SYS_TIMERBASE		(OMAP34XX_GPT2)
 #define CONFIG_SYS_PTV			2       /* Divisor: 2^(PTV+1) => 8 */
-#define CONFIG_SYS_HZ			1000
 
 /*-----------------------------------------------------------------------
  * Physical Memory Map
diff --git a/include/configs/omap3_overo.h b/include/configs/omap3_overo.h
index 88380a42c6..007e27f9f1 100644
--- a/include/configs/omap3_overo.h
+++ b/include/configs/omap3_overo.h
@@ -98,11 +98,10 @@
 #define CONFIG_CMD_NET		/* bootp, tftpboot, rarpboot	*/
 
 #define CONFIG_SYS_NO_FLASH
-#define CONFIG_HARD_I2C
-#define CONFIG_SYS_I2C_SPEED		100000
-#define CONFIG_SYS_I2C_SLAVE		1
-#define CONFIG_I2C_MULTI_BUS
-#define CONFIG_DRIVER_OMAP34XX_I2C
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_OMAP24_I2C_SPEED	100000
+#define CONFIG_SYS_OMAP24_I2C_SLAVE	1
+#define CONFIG_SYS_I2C_OMAP34XX
 
 /*
  * TWL4030
@@ -120,8 +119,6 @@
 #define CONFIG_SYS_NAND_BASE		NAND_BASE	/* physical address */
 							/* to access nand */
 							/* at CS0 */
-#define GPMC_NAND_ECC_LP_x16_LAYOUT
-
 #define CONFIG_SYS_MAX_NAND_DEVICE	1	/* Max number of NAND */
 						/* devices */
 #define CONFIG_JFFS2_NAND
@@ -217,7 +214,6 @@
  */
 #define CONFIG_SYS_TIMERBASE		OMAP34XX_GPT2
 #define CONFIG_SYS_PTV			2	/* Divisor: 2^(PTV+1) => 8 */
-#define CONFIG_SYS_HZ			1000
 
 /*-----------------------------------------------------------------------
  * Physical Memory Map
@@ -326,6 +322,7 @@
 						10, 11, 12, 13}
 #define CONFIG_SYS_NAND_ECCSIZE		512
 #define CONFIG_SYS_NAND_ECCBYTES	3
+#define CONFIG_NAND_OMAP_ECCSCHEME	OMAP_ECC_HAM1_CODE_HW
 #define CONFIG_SYS_NAND_U_BOOT_START	CONFIG_SYS_TEXT_BASE
 #define CONFIG_SYS_NAND_U_BOOT_OFFS	0x80000
 
diff --git a/include/configs/omap3_pandora.h b/include/configs/omap3_pandora.h
index ee448bb812..da67787e69 100644
--- a/include/configs/omap3_pandora.h
+++ b/include/configs/omap3_pandora.h
@@ -111,10 +111,10 @@
 #undef CONFIG_CMD_NFS		/* NFS support			*/
 
 #define CONFIG_SYS_NO_FLASH
-#define CONFIG_HARD_I2C			1
-#define CONFIG_SYS_I2C_SPEED		100000
-#define CONFIG_SYS_I2C_SLAVE		1
-#define CONFIG_DRIVER_OMAP34XX_I2C	1
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_OMAP24_I2C_SPEED	100000
+#define CONFIG_SYS_OMAP24_I2C_SLAVE	1
+#define CONFIG_SYS_I2C_OMAP34XX
 
 /*
  * TWL4030
@@ -131,8 +131,6 @@
 #define CONFIG_SYS_NAND_BASE		NAND_BASE	/* physical address */
 							/* to access nand */
 							/* at CS0 */
-#define GPMC_NAND_ECC_LP_x16_LAYOUT	1
-
 #define CONFIG_SYS_MAX_NAND_DEVICE	1	/* Max number of NAND */
 						/* devices */
 
@@ -201,7 +199,6 @@
  */
 #define CONFIG_SYS_TIMERBASE		OMAP34XX_GPT2
 #define CONFIG_SYS_PTV			2	/* Divisor: 2^(PTV+1) => 8 */
-#define CONFIG_SYS_HZ			1000
 
 /*-----------------------------------------------------------------------
  * Physical Memory Map
diff --git a/include/configs/omap3_sdp3430.h b/include/configs/omap3_sdp3430.h
index fc219fa478..a3e8a59972 100644
--- a/include/configs/omap3_sdp3430.h
+++ b/include/configs/omap3_sdp3430.h
@@ -16,7 +16,7 @@
 /* TODO: REMOVE THE FOLLOWING
  * Retained the following till size.h is removed in u-boot
  */
-#include <asm/sizes.h>
+#include <linux/sizes.h>
 /*
  * High Level Configuration Options
  */
@@ -114,10 +114,10 @@
 /*
  * I2C for power management setup
  */
-#define CONFIG_HARD_I2C			1
-#define CONFIG_SYS_I2C_SPEED		100000
-#define CONFIG_SYS_I2C_SLAVE		1
-#define CONFIG_DRIVER_OMAP34XX_I2C	1
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_OMAP24_I2C_SPEED	100000
+#define CONFIG_SYS_OMAP24_I2C_SLAVE	1
+#define CONFIG_SYS_I2C_OMAP34XX
 
 /* OMITTED:  single 1 Gbit MT29F1G NAND flash */
 
@@ -273,7 +273,6 @@
  */
 #define CONFIG_SYS_TIMERBASE		(OMAP34XX_GPT2)
 #define CONFIG_SYS_PTV			2	/* Divisor: 2^(PTV+1) => 8 */
-#define CONFIG_SYS_HZ			1000
 
 #define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
 #define CONFIG_SYS_INIT_RAM_ADDR	0x4020f800
diff --git a/include/configs/omap3_zoom1.h b/include/configs/omap3_zoom1.h
index a4a739e4a0..f0fa96efcb 100644
--- a/include/configs/omap3_zoom1.h
+++ b/include/configs/omap3_zoom1.h
@@ -118,10 +118,10 @@
 #undef CONFIG_CMD_NFS		/* NFS support			*/
 
 #define CONFIG_SYS_NO_FLASH
-#define CONFIG_HARD_I2C			1
-#define CONFIG_SYS_I2C_SPEED		100000
-#define CONFIG_SYS_I2C_SLAVE		1
-#define CONFIG_DRIVER_OMAP34XX_I2C	1
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_OMAP24_I2C_SPEED	100000
+#define CONFIG_SYS_OMAP24_I2C_SLAVE	1
+#define CONFIG_SYS_I2C_OMAP34XX
 
 /*
  * TWL4030
@@ -138,8 +138,6 @@
 #define CONFIG_SYS_NAND_BASE		NAND_BASE	/* physical address */
 							/* to access nand at */
 							/* CS0 */
-#define GPMC_NAND_ECC_LP_x16_LAYOUT	1
-
 #define CONFIG_SYS_MAX_NAND_DEVICE	1		/* Max number of NAND */
 							/* devices */
 #define CONFIG_JFFS2_NAND
@@ -228,7 +226,6 @@
  */
 #define CONFIG_SYS_TIMERBASE		OMAP34XX_GPT2
 #define CONFIG_SYS_PTV			2	/* Divisor: 2^(PTV+1) => 8 */
-#define CONFIG_SYS_HZ			1000
 
 /*-----------------------------------------------------------------------
  * Physical Memory Map
diff --git a/include/configs/omap3_zoom2.h b/include/configs/omap3_zoom2.h
deleted file mode 100644
index cb8c7ec6f0..0000000000
--- a/include/configs/omap3_zoom2.h
+++ /dev/null
@@ -1,237 +0,0 @@
-/*
- * (C) Copyright 2006-2009
- * Texas Instruments.
- * Richard Woodruff <r-woodruff2@ti.com>
- * Syed Mohammed Khasim <x0khasim@ti.com>
- * Nishanth Menon <nm@ti.com>
- * Tom Rix <Tom.Rix@windriver.com>
- *
- * Configuration settings for the TI OMAP3430 Zoom II board.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- */
-#define CONFIG_OMAP		1	/* in a TI OMAP core */
-#define CONFIG_OMAP34XX		1	/* which is a 34XX */
-#define CONFIG_OMAP3_ZOOM2	1	/* working with Zoom II */
-#define CONFIG_OMAP_GPIO
-#define CONFIG_OMAP_COMMON
-
-#define CONFIG_SDRC	/* The chip has SDRC controller */
-
-#include <asm/arch/cpu.h>	/* get chip and board defs */
-#include <asm/arch/omap3.h>
-
-/*
- * Display CPU and Board information
- */
-#define CONFIG_DISPLAY_CPUINFO		1
-#define CONFIG_DISPLAY_BOARDINFO	1
-
-/* Clock Defines */
-#define V_OSCK			26000000	/* Clock output from T2 */
-#define V_SCLK			(V_OSCK >> 1)
-
-#define CONFIG_MISC_INIT_R
-
-#define CONFIG_CMDLINE_TAG		1	/* enable passing of ATAGs */
-#define CONFIG_SETUP_MEMORY_TAGS	1
-#define CONFIG_INITRD_TAG		1
-#define CONFIG_REVISION_TAG		1
-
-#define CONFIG_OF_LIBFDT		1
-
-/*
- * Size of malloc() pool
- */
-#define CONFIG_ENV_SIZE			(128 << 10)	/* 128 KiB */
-						/* Sector */
-#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + (128 << 10))
-/*
- * Hardware drivers
- */
-
-/*
- * NS16550 Configuration
- * Zoom2 uses the TL16CP754C on the debug board
- */
-/*
- * 0 - 1 : first  USB with respect to the left edge of the debug board
- * 2 - 3 : second USB with respect to the left edge of the debug board
- */
-#define ZOOM2_DEFAULT_SERIAL_DEVICE	0
-
-#define V_NS16550_CLK			(1843200)	/* 1.8432 Mhz */
-
-#define CONFIG_SYS_NS16550
-#define CONFIG_SYS_NS16550_REG_SIZE	(-2)
-#define CONFIG_SYS_NS16550_CLK		V_NS16550_CLK
-#define CONFIG_BAUDRATE			115200
-#define CONFIG_SYS_BAUDRATE_TABLE	{115200}
-
-/* allow to overwrite serial and ethaddr */
-#define CONFIG_ENV_OVERWRITE
-
-#define CONFIG_GENERIC_MMC		1
-#define CONFIG_MMC			1
-#define CONFIG_OMAP_HSMMC		1
-#define CONFIG_DOS_PARTITION		1
-
-/* Status LED */
-#define CONFIG_STATUS_LED		1 /* Status LED enabled	*/
-#define CONFIG_BOARD_SPECIFIC_LED	1
-#define STATUS_LED_BLUE			0
-#define STATUS_LED_RED			1
-/* Blue */
-#define STATUS_LED_BIT			STATUS_LED_BLUE
-#define STATUS_LED_STATE		STATUS_LED_ON
-#define STATUS_LED_PERIOD		(CONFIG_SYS_HZ / 2)
-/* Red */
-#define STATUS_LED_BIT1			STATUS_LED_RED
-#define STATUS_LED_STATE1		STATUS_LED_OFF
-#define STATUS_LED_PERIOD1		(CONFIG_SYS_HZ / 2)
-/* Optional value */
-#define STATUS_LED_BOOT			STATUS_LED_BIT
-
-/* GPIO banks */
-#ifdef CONFIG_STATUS_LED
-#define CONFIG_OMAP3_GPIO_2 /* ZOOM2_LED_BLUE2 */
-#define CONFIG_OMAP3_GPIO_6 /* ZOOM2_LED_RED */
-#endif
-#define CONFIG_OMAP3_GPIO_3 /* board revision */
-#define CONFIG_OMAP3_GPIO_5 /* debug board detection, ZOOM2_LED_BLUE */
-
-/* USB */
-#define CONFIG_MUSB_UDC			1
-#define CONFIG_USB_OMAP3		1
-#define CONFIG_TWL4030_USB		1
-
-/* USB device configuration */
-#define CONFIG_USB_DEVICE		1
-#define CONFIG_USB_TTY			1
-/* Change these to suit your needs */
-#define CONFIG_USBD_VENDORID		0x0451
-#define CONFIG_USBD_PRODUCTID		0x5678
-#define CONFIG_USBD_MANUFACTURER	"Texas Instruments"
-#define CONFIG_USBD_PRODUCT_NAME	"Zoom2"
-
-/* commands to include */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_FAT			/* FAT support			*/
-#define CONFIG_CMD_I2C			/* I2C serial bus support	*/
-#define CONFIG_CMD_MMC			/* MMC support			*/
-#define CONFIG_CMD_NAND			/* NAND support			*/
-#define CONFIG_CMD_NAND_LOCK_UNLOCK	/* Enable lock/unlock support	*/
-
-#undef CONFIG_CMD_FLASH			/* flinfo, erase, protect	*/
-#undef CONFIG_CMD_FPGA			/* FPGA configuration Support	*/
-#undef CONFIG_CMD_IMI			/* iminfo			*/
-#undef CONFIG_CMD_IMLS			/* List all found images	*/
-#undef CONFIG_CMD_NET			/* bootp, tftpboot, rarpboot	*/
-#undef CONFIG_CMD_NFS			/* NFS support			*/
-
-#define CONFIG_SYS_NO_FLASH
-#define CONFIG_HARD_I2C			1
-#define CONFIG_SYS_I2C_SPEED		100000
-#define CONFIG_SYS_I2C_SLAVE		1
-#define CONFIG_DRIVER_OMAP34XX_I2C	1
-
-/*
- * TWL4030
- */
-#define CONFIG_TWL4030_POWER		1
-#define CONFIG_TWL4030_LED		1
-
-/*
- * Board NAND Info.
- */
-#define CONFIG_NAND_OMAP_GPMC
-#define CONFIG_SYS_NAND_ADDR		NAND_BASE	/* physical address */
-							/* to access nand */
-#define CONFIG_SYS_NAND_BASE		NAND_BASE	/* physical address */
-							/* to access nand at */
-							/* CS0 */
-#define GPMC_NAND_ECC_LP_x16_LAYOUT	1
-#define CONFIG_SYS_MAX_NAND_DEVICE	1
-
-/* Environment information */
-#define CONFIG_BOOTDELAY		10
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
-	"usbtty=cdc_acm\0" \
-
-#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
-#define CONFIG_SYS_INIT_RAM_ADDR	0x4020f800
-#define CONFIG_SYS_INIT_RAM_SIZE	0x800
-#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_INIT_RAM_ADDR + \
-					 CONFIG_SYS_INIT_RAM_SIZE - \
-					 GENERATED_GBL_DATA_SIZE)
-/*
- * Miscellaneous configurable options
- */
-
-#define CONFIG_SYS_PROMPT		"OMAP3 Zoom2 # "
-#define CONFIG_SYS_LONGHELP
-#define CONFIG_SYS_CBSIZE		512
-#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
-					 sizeof(CONFIG_SYS_PROMPT) + 16)
-#define CONFIG_SYS_MAXARGS		16
-#define CONFIG_SYS_BARGSIZE		(CONFIG_SYS_CBSIZE)
-/* Memtest from start of memory to 31MB */
-#define CONFIG_SYS_MEMTEST_START	(OMAP34XX_SDRC_CS0)
-#define CONFIG_SYS_MEMTEST_END		(OMAP34XX_SDRC_CS0 + 0x01F00000)
-/* The default load address is the start of memory */
-#define CONFIG_SYS_LOAD_ADDR		(OMAP34XX_SDRC_CS0)
-/* everything, incl board info, in Hz */
-#undef CONFIG_SYS_CLKS_IN_HZ
-/*
- * 2430 has 12 GP timers, they can be driven by the SysClk (12/13/19.2) or by
- * 32KHz clk, or from external sig. This rate is divided by a local divisor.
- */
-#define CONFIG_SYS_TIMERBASE		(OMAP34XX_GPT2)
-#define CONFIG_SYS_PTV			7	/* 2^(PTV+1) */
-#define CONFIG_SYS_HZ			((V_SCLK) / (2 << CONFIG_SYS_PTV))
-
-/*-----------------------------------------------------------------------
- * Physical Memory Map
- */
-#define CONFIG_NR_DRAM_BANKS	2	/* CS1 may or may not be populated */
-#define PHYS_SDRAM_1		OMAP34XX_SDRC_CS0
-#define PHYS_SDRAM_2		OMAP34XX_SDRC_CS1
-
-/*-----------------------------------------------------------------------
- * FLASH and environment organization
- */
-
-/* **** PISMO SUPPORT *** */
-
-/* Configure the PISMO */
-#define PISMO1_NAND_SIZE		GPMC_SIZE_128M
-#define PISMO1_ONEN_SIZE		GPMC_SIZE_128M
-
-#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 2 sectors */
-
-#if defined(CONFIG_CMD_NAND)
-#define CONFIG_SYS_FLASH_BASE		PISMO1_NAND_BASE
-#endif
-
-/* Monitor at start of flash */
-#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_FLASH_BASE
-
-#define CONFIG_ENV_IS_IN_NAND		1
-#define SMNAND_ENV_OFFSET		0x0c0000 /* environment starts here */
-
-#define CONFIG_SYS_ENV_SECT_SIZE	(128 << 10)	/* 128 KiB */
-#define CONFIG_ENV_OFFSET		SMNAND_ENV_OFFSET
-#define CONFIG_ENV_ADDR			SMNAND_ENV_OFFSET
-
-#define CONFIG_SYS_CACHELINE_SIZE	64
-
-#endif /* __CONFIG_H */
diff --git a/include/configs/omap4_common.h b/include/configs/omap4_common.h
deleted file mode 100644
index e9f2383f7c..0000000000
--- a/include/configs/omap4_common.h
+++ /dev/null
@@ -1,291 +0,0 @@
-/*
- * (C) Copyright 2010
- * Texas Instruments Incorporated.
- * Aneesh V       <aneesh@ti.com>
- * Steve Sakoman  <steve@sakoman.com>
- *
- * TI OMAP4 common configuration settings
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef __CONFIG_OMAP4_COMMON_H
-#define __CONFIG_OMAP4_COMMON_H
-
-/*
- * High Level Configuration Options
- */
-#define CONFIG_ARMV7		1	/* This is an ARM V7 CPU core */
-#define CONFIG_OMAP		1	/* in a TI OMAP core */
-#define CONFIG_OMAP44XX		1	/* which is a 44XX */
-#define CONFIG_OMAP4430		1	/* which is in a 4430 */
-#define CONFIG_OMAP_GPIO
-#define CONFIG_OMAP_COMMON
-
-/* Get CPU defs */
-#include <asm/arch/cpu.h>
-#include <asm/arch/omap.h>
-
-/* Display CPU and Board Info */
-#define CONFIG_DISPLAY_CPUINFO		1
-#define CONFIG_DISPLAY_BOARDINFO	1
-
-#define CONFIG_MISC_INIT_R
-
-#define CONFIG_OF_LIBFDT		1
-#define CONFIG_CMD_BOOTZ
-#define CONFIG_CMDLINE_TAG		1	/* enable passing of ATAGs */
-#define CONFIG_SETUP_MEMORY_TAGS	1
-#define CONFIG_INITRD_TAG		1
-#define CONFIG_REVISION_TAG		1
-
-/*
- * Size of malloc() pool
- * Total Size Environment - 128k
- * Malloc - add 256k
- */
-#define CONFIG_ENV_SIZE			(128 << 10)
-#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + (256 << 10))
-/* Vector Base */
-#define CONFIG_SYS_CA9_VECTOR_BASE	SRAM_ROM_VECT_BASE
-
-/*
- * Hardware drivers
- */
-
-/*
- * serial port - NS16550 compatible
- */
-#define V_NS16550_CLK			48000000
-
-#define CONFIG_SYS_NS16550
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE	(-4)
-#define CONFIG_SYS_NS16550_CLK		V_NS16550_CLK
-#define CONFIG_CONS_INDEX		3
-#define CONFIG_SYS_NS16550_COM3		UART3_BASE
-
-#define CONFIG_BAUDRATE			115200
-#define CONFIG_SYS_BAUDRATE_TABLE	{4800, 9600, 19200, 38400, 57600,\
-					115200}
-
-/* CPU */
-#define CONFIG_ARCH_CPU_INIT
-
-/* I2C  */
-#define CONFIG_HARD_I2C			1
-#define CONFIG_SYS_I2C_SPEED		100000
-#define CONFIG_SYS_I2C_SLAVE		1
-#define CONFIG_DRIVER_OMAP34XX_I2C	1
-#define CONFIG_I2C_MULTI_BUS		1
-
-/* TWL6030 */
-#ifndef CONFIG_SPL_BUILD
-#define CONFIG_TWL6030_POWER		1
-#endif
-
-/* MMC */
-#define CONFIG_GENERIC_MMC		1
-#define CONFIG_MMC			1
-#define CONFIG_OMAP_HSMMC		1
-#define CONFIG_DOS_PARTITION		1
-
-
-/* USB */
-#define CONFIG_MUSB_UDC			1
-#define CONFIG_USB_OMAP3		1
-
-/* USB device configuration */
-#define CONFIG_USB_DEVICE		1
-#define CONFIG_USB_TTY			1
-#define CONFIG_SYS_CONSOLE_IS_IN_ENV	1
-
-/* Flash */
-#define CONFIG_SYS_NO_FLASH	1
-
-/* commands to include */
-#include <config_cmd_default.h>
-
-/* Enabled commands */
-#define CONFIG_CMD_EXT2		/* EXT2 Support                 */
-#define CONFIG_CMD_FAT		/* FAT support                  */
-#define CONFIG_CMD_I2C		/* I2C serial bus support	*/
-#define CONFIG_CMD_MMC		/* MMC support                  */
-
-/* Disabled commands */
-#undef CONFIG_CMD_NET
-#undef CONFIG_CMD_NFS
-#undef CONFIG_CMD_FPGA		/* FPGA configuration Support   */
-#undef CONFIG_CMD_IMLS		/* List all found images        */
-
-/*
- * Environment setup
- */
-
-#define CONFIG_BOOTDELAY	3
-#define CONFIG_ENV_VARS_UBOOT_CONFIG
-#define CONFIG_CMD_FS_GENERIC
-#define CONFIG_CMD_EXT2
-#define CONFIG_CMD_EXT4
-
-#define CONFIG_ENV_OVERWRITE
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
-	"loadaddr=0x82000000\0" \
-	"console=ttyO2,115200n8\0" \
-	"fdt_high=0xffffffff\0" \
-	"fdtaddr=0x80f80000\0" \
-	"fdtfile=undefined\0" \
-	"bootpart=0:2\0" \
-	"bootdir=/boot\0" \
-	"bootfile=zImage\0" \
-	"usbtty=cdc_acm\0" \
-	"vram=16M\0" \
-	"mmcdev=0\0" \
-	"mmcroot=/dev/mmcblk0p2 rw\0" \
-	"mmcrootfstype=ext3 rootwait\0" \
-	"mmcargs=setenv bootargs console=${console} " \
-		"vram=${vram} " \
-		"root=${mmcroot} " \
-		"rootfstype=${mmcrootfstype}\0" \
-	"loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
-	"bootscript=echo Running bootscript from mmc${mmcdev} ...; " \
-		"source ${loadaddr}\0" \
-	"loadbootenv=fatload mmc ${mmcdev} ${loadaddr} uEnv.txt\0" \
-	"importbootenv=echo Importing environment from mmc${mmcdev} ...; " \
-		"env import -t ${loadaddr} ${filesize}\0" \
-	"loadimage=load mmc ${bootpart} ${loadaddr} ${bootdir}/${bootfile}\0" \
-	"mmcboot=echo Booting from mmc${mmcdev} ...; " \
-		"run mmcargs; " \
-		"bootz ${loadaddr} - ${fdtaddr}\0" \
-	"findfdt="\
-		"if test $board_name = sdp4430; then " \
-			"setenv fdtfile omap4-sdp.dtb; fi; " \
-		"if test $board_name = panda; then " \
-			"setenv fdtfile omap4-panda.dtb; fi;" \
-		"if test $board_name = panda-a4; then " \
-			"setenv fdtfile omap4-panda-a4.dtb; fi;" \
-		"if test $board_name = panda-es; then " \
-			"setenv fdtfile omap4-panda-es.dtb; fi;" \
-		"if test $fdtfile = undefined; then " \
-			"echo WARNING: Could not determine device tree to use; fi; \0" \
-	"loadfdt=load mmc ${bootpart} ${fdtaddr} ${bootdir}/${fdtfile}\0" \
-
-#define CONFIG_BOOTCOMMAND \
-	"run findfdt; " \
-	"mmc dev ${mmcdev}; if mmc rescan; then " \
-		"echo SD/MMC found on device ${mmcdev};" \
-		"if run loadbootscript; then " \
-			"run bootscript; " \
-		"else " \
-			"if run loadbootenv; then " \
-				"run importbootenv; " \
-			"fi;" \
-			"if test -n ${uenvcmd}; then " \
-				"echo Running uenvcmd ...;" \
-				"run uenvcmd;" \
-			"fi;" \
-		"fi;" \
-		"if run loadimage; then " \
-			"run loadfdt;" \
-			"run mmcboot; " \
-		"fi; " \
-	"fi"
-
-#define CONFIG_AUTO_COMPLETE		1
-
-/*
- * Miscellaneous configurable options
- */
-
-#define CONFIG_SYS_LONGHELP	/* undef to save memory */
-#define CONFIG_SYS_HUSH_PARSER	/* use "hush" command parser */
-#define CONFIG_SYS_CBSIZE		512
-/* Print Buffer Size */
-#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
-					sizeof(CONFIG_SYS_PROMPT) + 16)
-#define CONFIG_SYS_MAXARGS		16
-/* Boot Argument Buffer Size */
-#define CONFIG_SYS_BARGSIZE		(CONFIG_SYS_CBSIZE)
-
-/*
- * memtest setup
- */
-#define CONFIG_SYS_MEMTEST_START	0x80000000
-#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_MEMTEST_START + (32 << 20))
-
-/* Default load address */
-#define CONFIG_SYS_LOAD_ADDR		0x80000000
-
-/* Use General purpose timer 1 */
-#define CONFIG_SYS_TIMERBASE		GPT2_BASE
-#define CONFIG_SYS_PTV			2	/* Divisor: 2^(PTV+1) => 8 */
-#define CONFIG_SYS_HZ			1000
-
-/*
- * SDRAM Memory Map
- * Even though we use two CS all the memory
- * is mapped to one contiguous block
- */
-#define CONFIG_NR_DRAM_BANKS	1
-
-#define CONFIG_SYS_SDRAM_BASE		0x80000000
-#define CONFIG_SYS_INIT_SP_ADDR         (NON_SECURE_SRAM_END - \
-					 GENERATED_GBL_DATA_SIZE)
-
-#ifndef CONFIG_SYS_L2CACHE_OFF
-#define CONFIG_SYS_L2_PL310		1
-#define CONFIG_SYS_PL310_BASE	0x48242000
-#endif
-#define CONFIG_SYS_CACHELINE_SIZE	32
-
-/* Defines for SDRAM init */
-#define CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
-
-#ifndef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
-#define CONFIG_SYS_AUTOMATIC_SDRAM_DETECTION
-#define CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS
-#endif
-
-/* Defines for SPL */
-#define CONFIG_SPL
-#define CONFIG_SPL_FRAMEWORK
-#define CONFIG_SPL_TEXT_BASE		0x40304350
-#define CONFIG_SPL_MAX_SIZE		(38 * 1024)
-#define CONFIG_SPL_STACK		CONFIG_SYS_INIT_SP_ADDR
-#define CONFIG_SPL_DISPLAY_PRINT
-
-/*
- * 64 bytes before this address should be set aside for u-boot.img's
- * header. That is 80E7FFC0--0x80E80000 should not be used for any
- * other needs.
- */
-#define CONFIG_SYS_TEXT_BASE		0x80E80000
-
-/*
- * BSS and malloc area 64MB into memory to allow enough
- * space for the kernel at the beginning of memory
- */
-#define CONFIG_SPL_BSS_START_ADDR	0x84000000
-#define CONFIG_SPL_BSS_MAX_SIZE		0x100000	/* 1 MB */
-#define CONFIG_SYS_SPL_MALLOC_START	0x84100000
-#define CONFIG_SYS_SPL_MALLOC_SIZE	0x100000	/* 1 MB */
-
-#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR	0x300 /* address 0x60000 */
-#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS	0x200 /* 256 KB */
-#define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION	1
-#define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME	"u-boot.img"
-
-#define CONFIG_SPL_LIBCOMMON_SUPPORT
-#define CONFIG_SPL_LIBDISK_SUPPORT
-#define CONFIG_SPL_I2C_SUPPORT
-#define CONFIG_SPL_MMC_SUPPORT
-#define CONFIG_SPL_FAT_SUPPORT
-#define CONFIG_SPL_LIBGENERIC_SUPPORT
-#define CONFIG_SPL_SERIAL_SUPPORT
-#define CONFIG_SPL_GPIO_SUPPORT
-#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds"
-
-#define CONFIG_SYS_THUMB_BUILD
-
-#endif /* __CONFIG_OMAP4_COMMON_H */
diff --git a/include/configs/omap4_panda.h b/include/configs/omap4_panda.h
index 82946229a4..7378acdb21 100644
--- a/include/configs/omap4_panda.h
+++ b/include/configs/omap4_panda.h
@@ -4,7 +4,7 @@
  * Steve Sakoman  <steve@sakoman.com>
  *
  * Configuration settings for the TI OMAP4 Panda board.
- * See omap4_common.h for OMAP4 common part
+ * See ti_omap4_common.h for OMAP4 common part
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */
@@ -36,10 +36,7 @@
 #define CONFIG_CMD_PING
 #define CONFIG_CMD_DHCP
 
-#define CONFIG_USB_ULPI
-#define CONFIG_USB_ULPI_VIEWPORT_OMAP
-
-#include <configs/omap4_common.h>
+#include <configs/ti_omap4_common.h>
 #define CONFIG_CMD_NET
 
 /* GPIO */
@@ -48,8 +45,6 @@
 /* ENV related config options */
 #define CONFIG_ENV_IS_NOWHERE
 
-#define CONFIG_SYS_PROMPT		"Panda # "
-
 #define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
 
 #endif /* __CONFIG_PANDA_H */
diff --git a/include/configs/omap4_sdp4430.h b/include/configs/omap4_sdp4430.h
index acced46062..a83797454c 100644
--- a/include/configs/omap4_sdp4430.h
+++ b/include/configs/omap4_sdp4430.h
@@ -5,7 +5,7 @@
  * Steve Sakoman  <steve@sakoman.com>
  *
  * Configuration settings for the TI SDP4430 board.
- * See omap4_common.h for OMAP4 common part
+ * See ti_omap4_common.h for OMAP4 common part
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */
@@ -19,7 +19,7 @@
 #define CONFIG_4430SDP		1	/* working with SDP */
 #define CONFIG_MACH_TYPE	MACH_TYPE_OMAP_4430SDP
 
-#include <configs/omap4_common.h>
+#include <configs/ti_omap4_common.h>
 
 /* Battery Charger */
 #ifndef CONFIG_SPL_BUILD
@@ -32,6 +32,4 @@
 #define CONFIG_ENV_OFFSET		0xE0000
 #define CONFIG_CMD_SAVEENV
 
-#define CONFIG_SYS_PROMPT		"OMAP4430 SDP # "
-
 #endif /* __CONFIG_SDP4430_H */
diff --git a/include/configs/omap5912osk.h b/include/configs/omap5912osk.h
index c2b9e13c72..376dfdb14c 100644
--- a/include/configs/omap5912osk.h
+++ b/include/configs/omap5912osk.h
@@ -94,7 +94,6 @@
 
 #if defined(CONFIG_CMD_KGDB)
 #define CONFIG_KGDB_BAUDRATE	115200	/* speed to run kgdb serial port */
-#define CONFIG_KGDB_SER_INDEX	1	/* which serial port to use */
 #endif
 
 /*
@@ -118,7 +117,6 @@
  */
 #define CONFIG_SYS_TIMERBASE	0xFFFEC500	/* use timer 1 */
 #define CONFIG_SYS_PTV		7	/* 2^(PTV+1), divide by 256 */
-#define CONFIG_SYS_HZ		1000
 
 /*-----------------------------------------------------------------------
  * Physical Memory Map
diff --git a/include/configs/omap5_common.h b/include/configs/omap5_common.h
deleted file mode 100644
index 827eaabca8..0000000000
--- a/include/configs/omap5_common.h
+++ /dev/null
@@ -1,148 +0,0 @@
-/*
- * (C) Copyright 2013
- * Texas Instruments Incorporated.
- * Sricharan R	  <r.sricharan@ti.com>
- *
- * Derived from OMAP4 done by:
- *	Aneesh V <aneesh@ti.com>
- *
- * TI OMAP5 AND DRA7XX common configuration settings
- *
- * SPDX-License-Identifier:	GPL-2.0+
- *
- * For more details, please see the technical documents listed at
- * http://www.ti.com/product/omap5432
- */
-
-#ifndef __CONFIG_OMAP5_COMMON_H
-#define __CONFIG_OMAP5_COMMON_H
-
-#define CONFIG_OMAP54XX
-#define CONFIG_DISPLAY_CPUINFO
-#define CONFIG_DISPLAY_BOARDINFO
-#define CONFIG_MISC_INIT_R
-#define CONFIG_ARCH_CPU_INIT
-
-#define CONFIG_SYS_CACHELINE_SIZE	64
-
-/* Use General purpose timer 1 */
-#define CONFIG_SYS_TIMERBASE		GPT2_BASE
-
-/*
- * For the DDR timing information we can either dynamically determine
- * the timings to use or use pre-determined timings (based on using the
- * dynamic method.  Default to the static timing infomation.
- */
-#define CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
-#ifndef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
-#define CONFIG_SYS_AUTOMATIC_SDRAM_DETECTION
-#define CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS
-#endif
-
-#ifndef CONFIG_SPL_BUILD
-#define CONFIG_PALMAS_POWER
-#endif
-
-#include <asm/arch/cpu.h>
-#include <asm/arch/omap.h>
-
-#define CONFIG_ENV_SIZE			(128 << 10)
-
-#include <configs/ti_armv7_common.h>
-
-/*
- * Hardware drivers
- */
-#define CONFIG_SYS_NS16550
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE	(-4)
-#define CONFIG_SYS_NS16550_CLK		48000000
-
-/* Per-SoC commands */
-#undef CONFIG_CMD_NET
-#undef CONFIG_CMD_NFS
-
-/*
- * Environment setup
- */
-#ifndef PARTS_DEFAULT
-#define PARTS_DEFAULT
-#endif
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
-	"loadaddr=0x82000000\0" \
-	"console=" CONSOLEDEV ",115200n8\0" \
-	"fdt_high=0xffffffff\0" \
-	"fdtaddr=0x80f80000\0" \
-	"fdtfile=undefined\0" \
-	"bootpart=0:2\0" \
-	"bootdir=/boot\0" \
-	"bootfile=zImage\0" \
-	"usbtty=cdc_acm\0" \
-	"vram=16M\0" \
-	"partitions=" PARTS_DEFAULT "\0" \
-	"optargs=\0" \
-	"mmcdev=0\0" \
-	"mmcroot=/dev/mmcblk1p2 rw\0" \
-	"mmcrootfstype=ext4 rootwait\0" \
-	"mmcargs=setenv bootargs console=${console} " \
-		"${optargs} " \
-		"vram=${vram} " \
-		"root=${mmcroot} " \
-		"rootfstype=${mmcrootfstype}\0" \
-	"loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
-	"bootscript=echo Running bootscript from mmc${mmcdev} ...; " \
-		"source ${loadaddr}\0" \
-	"loadbootenv=fatload mmc ${mmcdev} ${loadaddr} uEnv.txt\0" \
-	"importbootenv=echo Importing environment from mmc${mmcdev} ...; " \
-		"env import -t ${loadaddr} ${filesize}\0" \
-	"loadimage=load mmc ${bootpart} ${loadaddr} ${bootdir}/${bootfile}\0" \
-	"mmcboot=mmc dev ${mmcdev}; " \
-		"if mmc rescan; then " \
-			"echo SD/MMC found on device ${mmcdev};" \
-			"if run loadbootenv; then " \
-				"echo Loaded environment from ${bootenv};" \
-				"run importbootenv;" \
-			"fi;" \
-			"if test -n $uenvcmd; then " \
-				"echo Running uenvcmd ...;" \
-				"run uenvcmd;" \
-			"fi;" \
-			"if run loadimage; then " \
-				"run loadfdt; " \
-				"echo Booting from mmc${mmcdev} ...; " \
-				"run mmcargs; " \
-				"bootz ${loadaddr} - ${fdtaddr}; " \
-			"fi;" \
-		"fi;\0" \
-	"findfdt="\
-		"if test $board_name = omap5_uevm; then " \
-			"setenv fdtfile omap5-uevm.dtb; fi; " \
-		"if test $board_name = dra7xx; then " \
-			"setenv fdtfile dra7-evm.dtb; fi;" \
-		"if test $fdtfile = undefined; then " \
-			"echo WARNING: Could not determine device tree to use; fi; \0" \
-	"loadfdt=load mmc ${bootpart} ${fdtaddr} ${bootdir}/${fdtfile};\0" \
-
-#define CONFIG_BOOTCOMMAND \
-	"run findfdt; " \
-	"run mmcboot;" \
-	"setenv mmcdev 1; " \
-	"setenv bootpart 1:2; " \
-	"setenv mmcroot /dev/mmcblk0p2 rw; " \
-	"run mmcboot;" \
-
-
-/*
- * SPL related defines.  The Public RAM memory map the ROM defines the
- * area between 0x40300000 and 0x4031E000 as a download area for OMAP5
- * (dra7xx is larger, but we do not need to be larger at this time).  We
- * set CONFIG_SPL_DISPLAY_PRINT to have omap_rev_string() called and
- * print some information.
- */
-#define CONFIG_SPL_TEXT_BASE		0x40300000
-#define CONFIG_SPL_MAX_SIZE		(0x4031E000 - CONFIG_SPL_TEXT_BASE)
-#define CONFIG_SPL_DISPLAY_PRINT
-#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds"
-
-#endif /* __CONFIG_OMAP5_COMMON_H */
diff --git a/include/configs/omap5_uevm.h b/include/configs/omap5_uevm.h
index 4d3a800298..783b7c3e32 100644
--- a/include/configs/omap5_uevm.h
+++ b/include/configs/omap5_uevm.h
@@ -4,7 +4,7 @@
  * Sricharan R	  <r.sricharan@ti.com>
  *
  * Configuration settings for the TI EVM5430 board.
- * See omap5_common.h for omap5 common settings.
+ * See ti_omap5_common.h for omap5 common settings.
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */
@@ -17,7 +17,7 @@
 	"uuid_disk=${uuid_gpt_disk};" \
 	"name=rootfs,start=2MiB,size=-,uuid=${uuid_gpt_rootfs}"
 
-#include <configs/omap5_common.h>
+#include <configs/ti_omap5_common.h>
 
 #define CONFIG_CONS_INDEX		3
 #define CONFIG_SYS_NS16550_COM3		UART3_BASE
@@ -36,6 +36,8 @@
 #define CONFIG_EFI_PARTITION
 #define CONFIG_PARTITION_UUIDS
 #define CONFIG_CMD_PART
+#define CONFIG_HSMMC2_8BIT
+#define CONFIG_SUPPORT_EMMC_BOOT
 
 /* Required support for the TCA642X GPIO we have on the uEVM */
 #define CONFIG_TCA642X
@@ -69,4 +71,14 @@
 /* Max time to hold reset on this board, see doc/README.omap-reset-time */
 #define CONFIG_OMAP_PLATFORM_RESET_TIME_MAX_USEC	16296
 
+#define CONFIG_BOARD_LATE_INIT
+#define CONFIG_CMD_SCSI
+#define CONFIG_LIBATA
+#define CONFIG_SCSI_AHCI
+#define CONFIG_SCSI_AHCI_PLAT
+#define CONFIG_SYS_SCSI_MAX_SCSI_ID	1
+#define CONFIG_SYS_SCSI_MAX_LUN		1
+#define CONFIG_SYS_SCSI_MAX_DEVICE	(CONFIG_SYS_SCSI_MAX_SCSI_ID * \
+						CONFIG_SYS_SCSI_MAX_LUN)
+
 #endif /* __CONFIG_OMAP5_EVM_H */
diff --git a/include/configs/omap730.h b/include/configs/omap730.h
deleted file mode 100644
index b54e0fb2da..0000000000
--- a/include/configs/omap730.h
+++ /dev/null
@@ -1,246 +0,0 @@
-/*
- *
- * BRIEF MODULE DESCRIPTION
- *   OMAP730 hardware map
- *
- * Copyright (C) 2004 MPC-Data Limited. (http://www.mpc-data.co.uk)
- * Author: MPC-Data Limited
- *	   Dave Peverley
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef __INCLUDED_OMAP730_H
-#define __INCLUDED_OMAP730_H
-
-#include <asm/sizes.h>
-
-/***************************************************************************
- * OMAP730 Configuration Registers
- **************************************************************************/
-
-#define PERSEUS2_MPU_DEV_ID               ((unsigned int)(0xFFFE1000))
-#define PERSEUS2_GSM_DEV_ID0              ((unsigned int)(0xFFFE1000))
-#define PERSEUS2_GDM_DEV_ID1              ((unsigned int)(0xFFFE1002))
-#define DSP_CONF                          ((unsigned int)(0xFFFE1004))
-#define PERSEUS2_MPU_DIE_ID0              ((unsigned int)(0xFFFE1008))
-#define GSM_ASIC_CONF                     ((unsigned int)(0xFFFE1008))
-#define PERSEUS2_MPU_DIE_ID1              ((unsigned int)(0xFFFE100C))
-#define PERSEUS2_MODE1                    ((unsigned int)(0xFFFE1010))
-#define PERSEUS2_GSM_DIE_ID0              ((unsigned int)(0xFFFE1010))
-#define PERSEUS2_GSM_DIE_ID1              ((unsigned int)(0xFFFE1012))
-#define PERSEUS2_MODE2                    ((unsigned int)(0xFFFE1014))
-#define PERSEUS2_GSM_DIE_ID2              ((unsigned int)(0xFFFE1014))
-#define PERSEUS2_GSM_DIE_ID3              ((unsigned int)(0xFFFE1016))
-#define PERSEUS2_ANALOG_CELLS_CONF        ((unsigned int)(0xFFFE1018))
-#define SPECCTL                           ((unsigned int)(0xFFFE101C))
-#define SPARE1                            ((unsigned int)(0xFFFE1020))
-#define SPARE2                            ((unsigned int)(0xFFFE1024))
-#define GSM_PBG_IRQ                       ((unsigned int)(0xFFFE1028))
-#define DMA_REQ_CONF                      ((unsigned int)(0xFFFE1030))
-#define PE_CONF_NO_DUAL                   ((unsigned int)(0xFFFE1060))
-#define PERSEUS2_IO_CONF0                 ((unsigned int)(0xFFFE1070))
-#define PERSEUS2_IO_CONF1                 ((unsigned int)(0xFFFE1074))
-#define PERSEUS2_IO_CONF2                 ((unsigned int)(0xFFFE1078))
-#define PERSEUS2_IO_CONF3                 ((unsigned int)(0xFFFE107C))
-#define PERSEUS2_IO_CONF4                 ((unsigned int)(0xFFFE1080))
-#define PERSEUS2_IO_CONF5                 ((unsigned int)(0xFFFE1084))
-#define PERSEUS2_IO_CONF6                 ((unsigned int)(0xFFFE1088))
-#define PERSEUS2_IO_CONF7                 ((unsigned int)(0xFFFE108C))
-#define PERSEUS2_IO_CONF8                 ((unsigned int)(0xFFFE1090))
-#define PERSEUS2_IO_CONF9                 ((unsigned int)(0xFFFE1094))
-#define PERSEUS2_IO_CONF10                ((unsigned int)(0xFFFE1098))
-#define PERSEUS2_IO_CONF11                ((unsigned int)(0xFFFE109C))
-#define PERSEUS2_IO_CONF12                ((unsigned int)(0xFFFE10A0))
-#define PERSEUS2_IO_CONF13                ((unsigned int)(0xFFFE10A4))
-#define PERSEUS_PCC_CONF_REG              ((unsigned int)(0xFFFE10B4))
-#define BIST_STATUS_INTERNAL              ((unsigned int)(0xFFFE10B8))
-#define BIST_CONTROL                      ((unsigned int)(0xFFFE10C0))
-#define BOOT_ROM_REG                      ((unsigned int)(0xFFFE10C4))
-#define PRODUCTION_ID_REG                 ((unsigned int)(0xFFFE10C8))
-#define BIST_SECROM_SIGNATURE1_INTERNAL   ((unsigned int)(0xFFFE10D0))
-#define BIST_SECROM_SIGNATURE2_INTERNAL   ((unsigned int)(0xFFFE10D4))
-#define BIST_CONTROL_2                    ((unsigned int)(0xFFFE10D8))
-#define DEBUG1                            ((unsigned int)(0xFFFE10E0))
-#define DEBUG2                            ((unsigned int)(0xFFFE10E4))
-#define DEBUG_DMA_IRQ                     ((unsigned int)(0xFFFE10E8))
-
-/***************************************************************************
- * OMAP730 EMIFS Registers                                       (TRM 2.5.7)
- **************************************************************************/
-
-#define TCMIF_BASE                 0xFFFECC00
-
-#define EMIFS_LRUREG               (TCMIF_BASE + 0x04)
-#define EMIFS_CONFIG               (TCMIF_BASE + 0x0C)
-#define FLASH_CFG_0                (TCMIF_BASE + 0x10)
-#define FLASH_CFG_1                (TCMIF_BASE + 0x14)
-#define FLASH_CFG_2                (TCMIF_BASE + 0x18)
-#define FLASH_CFG_3                (TCMIF_BASE + 0x1C)
-#define FL_CFG_DYN_WAIT            (TCMIF_BASE + 0x40)
-#define EMIFS_TIMEOUT1_REG         (TCMIF_BASE + 0x28)
-#define EMIFS_TIMEOUT2_REG         (TCMIF_BASE + 0x2C)
-#define EMIFS_TIMEOUT3_REG         (TCMIF_BASE + 0x30)
-#define EMIFS_ABORT_ADDR           (TCMIF_BASE + 0x44)
-#define EMIFS_ABORT_TYPE           (TCMIF_BASE + 0x48)
-#define EMIFS_ABORT_TOUT           (TCMIF_BASE + 0x4C)
-#define FLASH_ACFG_0_1             (TCMIF_BASE + 0x50)
-#define FLASH_ACFG_1_1             (TCMIF_BASE + 0x54)
-#define FLASH_ACFG_2_1             (TCMIF_BASE + 0x58)
-#define FLASH_ACFG_3_1             (TCMIF_BASE + 0x5C)
-
-/***************************************************************************
- * OMAP730 Interrupt handlers
- **************************************************************************/
-
-#define OMAP_IH1_BASE		0xFFFECB00     /* MPU Level 1 IRQ handler */
-#define OMAP_IH2_BASE           0xfffe0000
-
-/***************************************************************************
- * OMAP730 Timers
- *
- * There are three general purpose OS timers in the 730 that can be
- * configured in autoreload or one-shot modes.
- **************************************************************************/
-
-#define OMAP730_32kHz_TIMER_BASE  0xFFFB9000
-
-/* 32k Timer Registers */
-#define TIMER32k_CR               0x08
-#define TIMER32k_TVR              0x00
-#define TIMER32k_TCR              0x04
-
-/* 32k Timer Control Register definition */
-#define TIMER32k_TSS              (1<<0)
-#define TIMER32k_TRB              (1<<1)
-#define TIMER32k_INT              (1<<2)
-#define TIMER32k_ARL              (1<<3)
-
-/* MPU Timer base addresses  */
-#define OMAP730_MPUTIMER_BASE	0xfffec500
-#define OMAP730_MPUTIMER_OFF	0x00000100
-
-#define OMAP730_TIMER1_BASE	0xFFFEC500
-#define OMAP730_TIMER2_BASE	0xFFFEC600
-#define OMAP730_TIMER3_BASE	0xFFFEC700
-
-/* MPU Timer Register offsets */
-#define CNTL_TIMER	           0x00   /* MPU_CNTL_TIMER */
-#define LOAD_TIM	           0x04   /* MPU_LOAD_TIMER */
-#define READ_TIM	           0x08   /* MPU_READ_TIMER */
-
-/* MPU_CNTL_TIMER register bits */
-#define MPUTIM_FREE               (1<<6)
-#define MPUTIM_CLOCK_ENABLE       (1<<5)
-#define MPUTIM_PTV_MASK           (0x7<<MPUTIM_PTV_BIT)
-#define MPUTIM_PTV_BIT            2
-#define MPUTIM_AR                 (1<<1)
-#define MPUTIM_ST                 (1<<0)
-
-/***************************************************************************
- * OMAP730 GPIO
- *
- * The GPIO control is split over 6 register bases in the OMAP730 to allow
- * access to all the (6 x 32) GPIO pins!
- **************************************************************************/
-
-#define OMAP730_GPIO_BASE_1        0xFFFBC000
-#define OMAP730_GPIO_BASE_2        0xFFFBC800
-#define OMAP730_GPIO_BASE_3        0xFFFBD000
-#define OMAP730_GPIO_BASE_4        0xFFFBD800
-#define OMAP730_GPIO_BASE_5        0xFFFBE000
-#define OMAP730_GPIO_BASE_6        0xFFFBE800
-
-#define GPIO_DATA_INPUT            0x00
-#define GPIO_DATA_OUTPUT           0x04
-#define GPIO_DIRECTION_CONTROL     0x08
-#define GPIO_INTERRUPT_CONTROL     0x0C
-#define GPIO_INTERRUPT_MASK        0x10
-#define GPIO_INTERRUPT_STATUS      0x14
-
-#define GPIO_DATA_INPUT_1            ((unsigned int)(OMAP730_GPIO_BASE_1 + GPIO_DATA_INPUT))
-#define GPIO_DATA_OUTPUT_1           ((unsigned int)(OMAP730_GPIO_BASE_1 + GPIO_DATA_OUTPUT))
-#define GPIO_DIRECTION_CONTROL_1     ((unsigned int)(OMAP730_GPIO_BASE_1 + GPIO_DIRECTION_CONTROL))
-#define GPIO_INTERRUPT_CONTROL_1     ((unsigned int)(OMAP730_GPIO_BASE_1 + GPIO_INTERRUPT_CONTROL))
-#define GPIO_INTERRUPT_MASK_1        ((unsigned int)(OMAP730_GPIO_BASE_1 + GPIO_INTERRUPT_MASK))
-#define GPIO_INTERRUPT_STATUS_1      ((unsigned int)(OMAP730_GPIO_BASE_1 + GPIO_INTERRUPT_STATUS))
-
-#define GPIO_DATA_INPUT_2            ((unsigned int)(OMAP730_GPIO_BASE_2 + GPIO_DATA_INPUT))
-#define GPIO_DATA_OUTPUT_2           ((unsigned int)(OMAP730_GPIO_BASE_2 + GPIO_DATA_OUTPUT))
-#define GPIO_DIRECTION_CONTROL_2     ((unsigned int)(OMAP730_GPIO_BASE_2 + GPIO_DIRECTION_CONTROL))
-#define GPIO_INTERRUPT_CONTROL_2     ((unsigned int)(OMAP730_GPIO_BASE_2 + GPIO_INTERRUPT_CONTROL))
-#define GPIO_INTERRUPT_MASK_2        ((unsigned int)(OMAP730_GPIO_BASE_2 + GPIO_INTERRUPT_MASK))
-#define GPIO_INTERRUPT_STATUS_2      ((unsigned int)(OMAP730_GPIO_BASE_2 + GPIO_INTERRUPT_STATUS))
-
-#define GPIO_DATA_INPUT_3            ((unsigned int)(OMAP730_GPIO_BASE_3 + GPIO_DATA_INPUT))
-#define GPIO_DATA_OUTPUT_3           ((unsigned int)(OMAP730_GPIO_BASE_3 + GPIO_DATA_OUTPUT))
-#define GPIO_DIRECTION_CONTROL_3     ((unsigned int)(OMAP730_GPIO_BASE_3 + GPIO_DIRECTION_CONTROL))
-#define GPIO_INTERRUPT_CONTROL_3     ((unsigned int)(OMAP730_GPIO_BASE_3 + GPIO_INTERRUPT_CONTROL))
-#define GPIO_INTERRUPT_MASK_3        ((unsigned int)(OMAP730_GPIO_BASE_3 + GPIO_INTERRUPT_MASK))
-#define GPIO_INTERRUPT_STATUS_3      ((unsigned int)(OMAP730_GPIO_BASE_3 + GPIO_INTERRUPT_STATUS))
-
-#define GPIO_DATA_INPUT_4            ((unsigned int)(OMAP730_GPIO_BASE_4 + GPIO_DATA_INPUT))
-#define GPIO_DATA_OUTPUT_4           ((unsigned int)(OMAP730_GPIO_BASE_4 + GPIO_DATA_OUTPUT))
-#define GPIO_DIRECTION_CONTROL_4     ((unsigned int)(OMAP730_GPIO_BASE_4 + GPIO_DIRECTION_CONTROL))
-#define GPIO_INTERRUPT_CONTROL_4     ((unsigned int)(OMAP730_GPIO_BASE_4 + GPIO_INTERRUPT_CONTROL))
-#define GPIO_INTERRUPT_MASK_4        ((unsigned int)(OMAP730_GPIO_BASE_4 + GPIO_INTERRUPT_MASK))
-#define GPIO_INTERRUPT_STATUS_4      ((unsigned int)(OMAP730_GPIO_BASE_4 + GPIO_INTERRUPT_STATUS))
-
-#define GPIO_DATA_INPUT_5            ((unsigned int)(OMAP730_GPIO_BASE_5 + GPIO_DATA_INPUT))
-#define GPIO_DATA_OUTPUT_5           ((unsigned int)(OMAP730_GPIO_BASE_5 + GPIO_DATA_OUTPUT))
-#define GPIO_DIRECTION_CONTROL_5     ((unsigned int)(OMAP730_GPIO_BASE_5 + GPIO_DIRECTION_CONTROL))
-#define GPIO_INTERRUPT_CONTROL_5     ((unsigned int)(OMAP730_GPIO_BASE_5 + GPIO_INTERRUPT_CONTROL))
-#define GPIO_INTERRUPT_MASK_5        ((unsigned int)(OMAP730_GPIO_BASE_5 + GPIO_INTERRUPT_MASK))
-#define GPIO_INTERRUPT_STATUS_5      ((unsigned int)(OMAP730_GPIO_BASE_5 + GPIO_INTERRUPT_STATUS))
-
-#define GPIO_DATA_INPUT_6            ((unsigned int)(OMAP730_GPIO_BASE_6 + GPIO_DATA_INPUT))
-#define GPIO_DATA_OUTPUT_6           ((unsigned int)(OMAP730_GPIO_BASE_6 + GPIO_DATA_OUTPUT))
-#define GPIO_DIRECTION_CONTROL_6     ((unsigned int)(OMAP730_GPIO_BASE_6 + GPIO_DIRECTION_CONTROL))
-#define GPIO_INTERRUPT_CONTROL_6     ((unsigned int)(OMAP730_GPIO_BASE_6 + GPIO_INTERRUPT_CONTROL))
-#define GPIO_INTERRUPT_MASK_6        ((unsigned int)(OMAP730_GPIO_BASE_6 + GPIO_INTERRUPT_MASK))
-#define GPIO_INTERRUPT_STATUS_6      ((unsigned int)(OMAP730_GPIO_BASE_6 + GPIO_INTERRUPT_STATUS))
-
-/***************************************************************************
- * OMAP730 Watchdog timers
- **************************************************************************/
-
-#define WDTIM_BASE                 0xFFFEC800
-#define WDTIM_CONTROL              (WDTIM_BASE + 0x00)    /* MPU_CNTL_TIMER */
-#define WDTIM_LOAD                 (WDTIM_BASE + 0x04)    /* MPU_LOAD_TIMER */
-#define WDTIM_READ                 (WDTIM_BASE + 0x04)    /* MPU_READ_TIMER */
-#define WDTIM_MODE                 (WDTIM_BASE + 0x08)    /* MPU_TIMER_MODE */
-
-/***************************************************************************
- * OMAP730 Interrupt Registers
- **************************************************************************/
-
-/* Interrupt Register offsets */
-
-#define IRQ_ITR                               0x00
-#define IRQ_MIR                               0x04
-#define IRQ_SIR_IRQ                           0x10
-#define IRQ_SIR_FIQ                           0x14
-#define IRQ_CONTROL_REG                       0x18
-#define IRQ_ILR0                              0x1C  /* ILRx == ILR0 + (0x4 * x) */
-#define IRQ_SIR                               0x9C  /* a.k.a.IRQ_ISR */
-#define IRQ_GMIR                              0xA0
-
-#define REG_IHL1_MIR  (OMAP_IH1_BASE + IRQ_MIR)
-#define REG_IHL2_MIR  (OMAP_IH2_BASE + IRQ_MIR)
-
-/***************************************************************************
- * OMAP730 Intersystem Communication Register                      (TRM 4.5)
- **************************************************************************/
-
-#define ICR_BASE                   0xFFFBB800
-
-#define M_ICR                      (ICR_BASE + 0x00)
-#define G_ICR                      (ICR_BASE + 0x02)
-#define M_CTL                      (ICR_BASE + 0x04)
-#define G_CTL                      (ICR_BASE + 0x06)
-#define PM_BA                      (ICR_BASE + 0x0A)
-#define DM_BA                      (ICR_BASE + 0x0C)
-#define RM_BA                      (ICR_BASE + 0x0E)
-#define SSPI_TAS                   (ICR_BASE + 0x12)
-
-#endif /* ! __INCLUDED_OMAP730_H */
diff --git a/include/configs/omap730p2.h b/include/configs/omap730p2.h
deleted file mode 100644
index 947f27bae5..0000000000
--- a/include/configs/omap730p2.h
+++ /dev/null
@@ -1,173 +0,0 @@
-/*
- * (C) Copyright 2003-2004
- * MPC Data Limited (http://www.mpc-data.co.uk)
- * Dave Peverley <dpeverley at mpc-data.co.uk>
- *
- * Configuation settings for the TI OMAP Perseus 2 board.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/* allow to overwrite serial and ethaddr */
-#define CONFIG_ENV_OVERWRITE
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_ARM926EJS	   1	     /* This is an arm926ejs CPU core  */
-#define CONFIG_OMAP		   1	     /* in a TI OMAP core    */
-#define CONFIG_OMAP730		   1	     /* which is in a 730  */
-#define CONFIG_P2_OMAP730	   1	     /*	 a Perseus 2 Board  */
-
-/*
- * Input clock of PLL
- * The OMAP730 Perseus 2 has 13MHz input clock
- */
-
-#define CONFIG_SYS_CLK_FREQ	   13000000
-
-#define CONFIG_CMDLINE_TAG	   1	     /* enable passing of ATAGs	 */
-#define CONFIG_SETUP_MEMORY_TAGS   1
-
-/*
- * Size of malloc() pool
- */
-
-#define CONFIG_SYS_MALLOC_LEN		   (CONFIG_ENV_SIZE + 128*1024)
-
-/*
- * Hardware drivers
- */
-
-#define CONFIG_LAN91C96
-#define CONFIG_LAN91C96_BASE	   0x04000300
-#define CONFIG_LAN91C96_EXT_PHY
-
-/*
- * NS16550 Configuration
- */
-
-#define CONFIG_SYS_NS16550
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE	   (1)
-#define CONFIG_SYS_NS16550_CLK		   (48000000)	  /* can be 12M/32Khz or 48Mhz */
-#define CONFIG_SYS_NS16550_COM1	   0xfffb0000	  /* uart1, bluetooth uart
-						   * on perseus */
-
-/*
- * select serial console configuration
- */
-
-#define CONFIG_SERIAL1		   1	     /* we use SERIAL 1 on OMAP730 Perseus 2 */
-
-#define CONFIG_CONS_INDEX	   1
-#define CONFIG_BAUDRATE		   115200
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_DHCP
-
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_SUBNETMASK
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-#define CONFIG_BOOTP_BOOTPATH
-
-
-#include <configs/omap730.h>
-#include <configs/h2_p2_dbg_board.h>
-
-#define CONFIG_BOOTDELAY	   3
-#define CONFIG_BOOTARGS		   "mem=32M console=ttyS0,115200n8 noinitrd root=/dev/nfs rw ip=bootp"
-
-#define CONFIG_LOADADDR		   0x10000000
-
-#define CONFIG_ETHADDR
-#define CONFIG_NETMASK		   255.255.255.0
-#define CONFIG_IPADDR		   192.168.0.23
-#define CONFIG_SERVERIP		   192.150.0.100
-#define CONFIG_BOOTFILE		   "uImage"  /* File to load */
-
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_KGDB_BAUDRATE	   115200    /* Speed to run kgdb serial port */
-#define CONFIG_KGDB_SER_INDEX	   1	     /* Which serial port to use */
-#endif
-
-/*
- * Miscellaneous configurable options
- */
-
-#define CONFIG_SYS_LONGHELP				       /* undef to save memory	   */
-#define CONFIG_SYS_PROMPT		   "OMAP730 P2 # "     /* Monitor Command Prompt   */
-#define CONFIG_SYS_CBSIZE		   256		       /* Console I/O Buffer Size  */
-/* Print Buffer Size */
-#define CONFIG_SYS_PBSIZE		   (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
-#define CONFIG_SYS_MAXARGS		   16		       /* max number of command args   */
-#define CONFIG_SYS_BARGSIZE		   CONFIG_SYS_CBSIZE	       /* Boot Argument Buffer Size    */
-
-#define CONFIG_SYS_MEMTEST_START	   0x10000000	       /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END		   0x12000000	       /* 32 MB in DRAM	   */
-
-#define CONFIG_SYS_LOAD_ADDR		   0x10000000	       /* default load address */
-
-/* The OMAP730 has 3 general purpose MPU timers, they can be driven by
- * the RefClk (12Mhz) or by DPLL1. This time is further subdivided by a
- * local divisor.
- */
-#define CONFIG_SYS_TIMERBASE		0xFFFEC500	/* use timer 1 */
-#define CONFIG_SYS_PTV			7	/* 2^(PTV+1), divide by 256 */
-#define CONFIG_SYS_HZ			((CONFIG_SYS_CLK_FREQ)/(2 << CONFIG_SYS_PTV))
-
-/*-----------------------------------------------------------------------
- * Physical Memory Map
- */
-
-#define CONFIG_NR_DRAM_BANKS	   1		  /* we have 1 bank of DRAM */
-#define PHYS_SDRAM_1		   0x10000000	  /* SDRAM Bank #1 */
-#define PHYS_SDRAM_1_SIZE	   0x02000000	  /* 32 MB */
-
-#if defined(CONFIG_CS0_BOOT)
-#define PHYS_FLASH_1		   0x0C000000
-#elif defined(CONFIG_CS3_BOOT)
-#define PHYS_FLASH_1		   0x00000000
-#else
-#error Unknown Boot Chip-Select number
-#endif
-
-#define PHYS_SRAM		0x20000000
-
-#define CONFIG_SYS_FLASH_BASE		   PHYS_FLASH_1
-
-/*-----------------------------------------------------------------------
- * FLASH and environment organization
- */
-
-#define CONFIG_SYS_MAX_FLASH_BANKS	   1		  /* max number of memory banks */
-#define PHYS_FLASH_SIZE		   0x02000000	  /* 32MB */
-#define CONFIG_SYS_MAX_FLASH_SECT	   (259)	  /* max number of sectors on one chip */
-/* addr of environment */
-#define CONFIG_ENV_ADDR		   (CONFIG_SYS_FLASH_BASE + 0x020000)
-
-/* timeout values are in ticks */
-#define CONFIG_SYS_FLASH_ERASE_TOUT	    (20*CONFIG_SYS_HZ)	  /* Timeout for Flash Erase */
-#define CONFIG_SYS_FLASH_WRITE_TOUT	    (20*CONFIG_SYS_HZ)	  /* Timeout for Flash Write */
-
-#define CONFIG_ENV_IS_IN_FLASH	   1
-#define CONFIG_ENV_SIZE		   0x20000	  /* Total Size of Environment Sector */
-#define CONFIG_ENV_OFFSET		   0x20000	  /* environment starts here  */
-
-#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
-#define CONFIG_SYS_INIT_SP_ADDR 	PHYS_SRAM
-
-#endif	  /* ! __CONFIG_H */
diff --git a/include/configs/openrisc-generic.h b/include/configs/openrisc-generic.h
index ad3775e031..d4de3c3550 100644
--- a/include/configs/openrisc-generic.h
+++ b/include/configs/openrisc-generic.h
@@ -55,7 +55,6 @@
 /*
  * TIMER
  */
-#define CONFIG_SYS_HZ			1000
 #define CONFIG_SYS_OPENRISC_TMR_HZ	100
 
 /*
@@ -101,7 +100,6 @@
  * MISC
  */
 #define CONFIG_SYS_LONGHELP		/* Provide extended help */
-#define CONFIG_SYS_PROMPT		"==> "	/* Command prompt	*/
 #define CONFIG_SYS_CBSIZE		256	/* Console I/O buf size */
 #define CONFIG_SYS_MAXARGS		16	/* Max command args	*/
 #define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE /* Bootarg buf size */
diff --git a/include/configs/origen.h b/include/configs/origen.h
index da135740e4..82583382f7 100644
--- a/include/configs/origen.h
+++ b/include/configs/origen.h
@@ -6,119 +6,71 @@
  * SPDX-License-Identifier:	GPL-2.0+
  */
 
-#ifndef __CONFIG_H
-#define __CONFIG_H
+#ifndef __CONFIG_ORIGEN_H
+#define __CONFIG_ORIGEN_H
+
+#include <configs/exynos4-dt.h>
+
+#define CONFIG_SYS_PROMPT		"ORIGEN # "
+
+#undef CONFIG_DEFAULT_DEVICE_TREE
+#define CONFIG_DEFAULT_DEVICE_TREE	exynos4210-origen
 
 /* High Level Configuration Options */
-#define CONFIG_SAMSUNG			1	/* SAMSUNG core */
-#define CONFIG_S5P			1	/* S5P Family */
 #define CONFIG_EXYNOS4210		1	/* which is a EXYNOS4210 SoC */
 #define CONFIG_ORIGEN			1	/* working with ORIGEN*/
 
-#include <asm/arch/cpu.h>		/* get chip and board defs */
-
-#define CONFIG_ARCH_CPU_INIT
-#define CONFIG_DISPLAY_CPUINFO
-#define CONFIG_DISPLAY_BOARDINFO
-#define CONFIG_BOARD_EARLY_INIT_F
-
-/* Keep L2 Cache Disabled */
-#define CONFIG_L2_OFF			1
 #define CONFIG_SYS_DCACHE_OFF		1
 
+/* ORIGEN has 4 bank of DRAM */
+#define CONFIG_NR_DRAM_BANKS		4
 #define CONFIG_SYS_SDRAM_BASE		0x40000000
-#define CONFIG_SYS_TEXT_BASE		0x43E00000
+#define PHYS_SDRAM_1			CONFIG_SYS_SDRAM_BASE
+#define SDRAM_BANK_SIZE			(256 << 20)	/* 256 MB */
 
-/* input clock of PLL: ORIGEN has 24MHz input clock */
-#define CONFIG_SYS_CLK_FREQ		24000000
+/* memtest works on */
+#define CONFIG_SYS_MEMTEST_START	CONFIG_SYS_SDRAM_BASE
+#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_SDRAM_BASE + 0x6000000)
+#define CONFIG_SYS_LOAD_ADDR		(CONFIG_SYS_SDRAM_BASE + 0x3E00000)
 
-#define CONFIG_SETUP_MEMORY_TAGS
-#define CONFIG_CMDLINE_TAG
-#define CONFIG_INITRD_TAG
-#define CONFIG_CMDLINE_EDITING
+#define CONFIG_SYS_TEXT_BASE		0x43E00000
 
 #define CONFIG_MACH_TYPE		MACH_TYPE_ORIGEN
 
-/* Power Down Modes */
-#define S5P_CHECK_SLEEP			0x00000BAD
-#define S5P_CHECK_DIDLE			0xBAD00000
-#define S5P_CHECK_LPA			0xABAD0000
-
 /* Size of malloc() pool */
-#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + (1 << 20))
+#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + (80 * SZ_1M))
 
 /* select serial console configuration */
-#define CONFIG_SERIAL2			1	/* use SERIAL 2 */
+#define CONFIG_SERIAL2
 #define CONFIG_BAUDRATE			115200
-#define EXYNOS4_DEFAULT_UART_OFFSET	0x020000
-
-#define CONFIG_SKIP_LOWLEVEL_INIT
 
-/* SD/MMC configuration */
-#define CONFIG_GENERIC_MMC
-#define CONFIG_MMC
-#define CONFIG_SDHCI
-#define CONFIG_S5P_SDHCI
+/* Console configuration */
+#define CONFIG_SYS_CONSOLE_INFO_QUIET
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV
+#define CONFIG_DEFAULT_CONSOLE		"console=ttySAC1,115200n8\0"
 
-/* PWM */
-#define CONFIG_PWM			1
+#define CONFIG_SYS_MEM_TOP_HIDE	(1 << 20)	/* ram console */
 
-/* allow to overwrite serial and ethaddr */
-#define CONFIG_ENV_OVERWRITE
+#define CONFIG_SYS_MONITOR_BASE	0x00000000
 
-/* Command definition*/
-#include <config_cmd_default.h>
+/* Power Down Modes */
+#define S5P_CHECK_SLEEP			0x00000BAD
+#define S5P_CHECK_DIDLE			0xBAD00000
+#define S5P_CHECK_LPA			0xABAD0000
 
 #undef CONFIG_CMD_PING
 #define CONFIG_CMD_ELF
 #define CONFIG_CMD_DHCP
-#define CONFIG_CMD_MMC
-#define CONFIG_CMD_FAT
 #undef CONFIG_CMD_NET
 #undef CONFIG_CMD_NFS
 
-#define CONFIG_BOOTDELAY		3
-#define CONFIG_ZERO_BOOTDELAY_CHECK
 /* MMC SPL */
 #define CONFIG_SPL
 #define COPY_BL2_FNPTR_ADDR	0x02020030
-
 #define CONFIG_SPL_TEXT_BASE	0x02021410
 
 #define CONFIG_BOOTCOMMAND	"fatload mmc 0 40007000 uImage; bootm 40007000"
 
-/* Miscellaneous configurable options */
-#define CONFIG_SYS_LONGHELP		/* undef to save memory */
-#define CONFIG_SYS_HUSH_PARSER		/* use "hush" command parser	*/
-#define CONFIG_SYS_PROMPT		"ORIGEN # "
-#define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size*/
-#define CONFIG_SYS_PBSIZE		384	/* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS		16	/* max number of command args */
-#define CONFIG_DEFAULT_CONSOLE		"console=ttySAC2,115200n8\0"
-/* Boot Argument Buffer Size */
-#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE
-/* memtest works on */
-#define CONFIG_SYS_MEMTEST_START	CONFIG_SYS_SDRAM_BASE
-#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_SDRAM_BASE + 0x6000000)
-#define CONFIG_SYS_LOAD_ADDR		(CONFIG_SYS_SDRAM_BASE + 0x3E00000)
-
-#define CONFIG_SYS_HZ			1000
-
-/* ORIGEN has 4 bank of DRAM */
-#define CONFIG_NR_DRAM_BANKS	4
-#define SDRAM_BANK_SIZE		(256UL << 20UL)	/* 256 MB */
-#define PHYS_SDRAM_1		CONFIG_SYS_SDRAM_BASE
-#define PHYS_SDRAM_1_SIZE	SDRAM_BANK_SIZE
-#define PHYS_SDRAM_2		(CONFIG_SYS_SDRAM_BASE + SDRAM_BANK_SIZE)
-#define PHYS_SDRAM_2_SIZE	SDRAM_BANK_SIZE
-#define PHYS_SDRAM_3		(CONFIG_SYS_SDRAM_BASE + (2 * SDRAM_BANK_SIZE))
-#define PHYS_SDRAM_3_SIZE	SDRAM_BANK_SIZE
-#define PHYS_SDRAM_4		(CONFIG_SYS_SDRAM_BASE + (3 * SDRAM_BANK_SIZE))
-#define PHYS_SDRAM_4_SIZE	SDRAM_BANK_SIZE
-
-/* FLASH and environment organization */
-#define CONFIG_SYS_NO_FLASH		1
-#undef CONFIG_CMD_IMLS
 #define CONFIG_IDENT_STRING		" for ORIGEN"
 
 #define CONFIG_CLK_1000_400_200
@@ -126,13 +78,12 @@
 /* MIU (Memory Interleaving Unit) */
 #define CONFIG_MIU_2BIT_21_7_INTERLEAVED
 
-#define CONFIG_ENV_IS_IN_MMC		1
+#define CONFIG_ENV_IS_IN_MMC
 #define CONFIG_SYS_MMC_ENV_DEV		0
 #define CONFIG_ENV_SIZE			(16 << 10)	/* 16 KB */
 #define RESERVE_BLOCK_SIZE		(512)
 #define BL1_SIZE			(16 << 10) /*16 K reserved for BL1*/
 #define CONFIG_ENV_OFFSET		(RESERVE_BLOCK_SIZE + BL1_SIZE)
-#define CONFIG_DOS_PARTITION		1
 
 #define CONFIG_SPL_LDSCRIPT	"board/samsung/common/exynos-uboot-spl.lds"
 #define CONFIG_SPL_MAX_FOOTPRINT	(14 * 1024)
@@ -144,7 +95,4 @@
 #define BL2_START_OFFSET	((CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)/512)
 #define BL2_SIZE_BLOC_COUNT	(COPY_BL2_SIZE/512)
 
-/* Enable devicetree support */
-#define CONFIG_OF_LIBFDT
-
 #endif	/* __CONFIG_H */
diff --git a/include/configs/otc570.h b/include/configs/otc570.h
index 543209cb9d..629967d054 100644
--- a/include/configs/otc570.h
+++ b/include/configs/otc570.h
@@ -39,7 +39,6 @@
 /* ARM asynchronous clock */
 #define CONFIG_SYS_AT91_SLOW_CLOCK	32768	/* 32.768 kHz crystal */
 #define CONFIG_SYS_AT91_MAIN_CLOCK	16000000/* 16.0 MHz crystal */
-#define CONFIG_SYS_HZ			1000	/* decrementer freq */
 
 /* Misc CPU related */
 #define CONFIG_SKIP_LOWLEVEL_INIT
@@ -194,8 +193,8 @@
 # define CONFIG_SYS_NAND_DBW_8
 # define CONFIG_SYS_NAND_MASK_ALE		(1 << 21)
 # define CONFIG_SYS_NAND_MASK_CLE		(1 << 22)
-# define CONFIG_SYS_NAND_ENABLE_PIN		AT91_PIO_PORTD, 15
-# define CONFIG_SYS_NAND_READY_PIN		AT91_PIO_PORTA, 22
+# define CONFIG_SYS_NAND_ENABLE_PIN		GPIO_PIN_PD(15)
+# define CONFIG_SYS_NAND_READY_PIN		GPIO_PIN_PA(22)
 #endif
 
 /* Ethernet */
@@ -207,6 +206,7 @@
 
 /* USB */
 #define CONFIG_USB_ATMEL
+#define CONFIG_USB_ATMEL_CLK_SEL_PLLB
 #define CONFIG_USB_OHCI_NEW
 #define CONFIG_DOS_PARTITION
 #define CONFIG_SYS_USB_OHCI_CPU_INIT
@@ -242,7 +242,6 @@
 
 #endif
 
-#define CONFIG_SYS_PROMPT		"=> "
 #define CONFIG_SYS_CBSIZE		512
 #define CONFIG_SYS_MAXARGS		16
 #define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h
index 5f0c4fb254..07b61795bb 100644
--- a/include/configs/p1_p2_rdb_pc.h
+++ b/include/configs/p1_p2_rdb_pc.h
@@ -144,65 +144,110 @@
 #define CONFIG_SYS_L2_SIZE	(512 << 10)
 #endif
 
-#if CONFIG_SYS_L2_SIZE >= (512 << 10)
-/* must be 32-bit */
-#define CONFIG_SYS_INIT_L2_ADDR	0xf8f80000
-#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
-#define CONFIG_SYS_INIT_L2_END  (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
-#endif
-
 #ifdef CONFIG_SDCARD
-#define CONFIG_RAMBOOT_SDCARD
-#define CONFIG_SYS_RAMBOOT
-#define CONFIG_SYS_EXTRA_ENV_RELOC
-#define CONFIG_SYS_TEXT_BASE		0x11000000
-#define CONFIG_RESET_VECTOR_ADDRESS	0x1107fffc
+#define CONFIG_SPL
+#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
+#define CONFIG_SPL_ENV_SUPPORT
+#define CONFIG_SPL_SERIAL_SUPPORT
+#define CONFIG_SPL_MMC_SUPPORT
+#define CONFIG_SPL_MMC_MINIMAL
+#define CONFIG_SPL_FLUSH_IMAGE
+#define CONFIG_SPL_TARGET		"u-boot-with-spl.bin"
+#define CONFIG_SPL_LIBGENERIC_SUPPORT
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+#define CONFIG_SPL_I2C_SUPPORT
+#define CONFIG_FSL_LAW                 /* Use common FSL init code */
+#define CONFIG_SYS_TEXT_BASE		0x11001000
+#define CONFIG_SPL_TEXT_BASE		0xf8f81000
+#define CONFIG_SPL_PAD_TO		0x20000
+#define CONFIG_SPL_MAX_SIZE		(128 * 1024)
+#define CONFIG_SYS_MMC_U_BOOT_SIZE	(768 << 10)
+#define CONFIG_SYS_MMC_U_BOOT_DST	(0x11000000)
+#define CONFIG_SYS_MMC_U_BOOT_START	(0x11000000)
+#define CONFIG_SYS_MMC_U_BOOT_OFFS	(128 << 10)
+#define CONFIG_SYS_MPC85XX_NO_RESETVEC
+#define CONFIG_SYS_LDSCRIPT	"arch/powerpc/cpu/mpc85xx/u-boot.lds"
+#define CONFIG_SPL_MMC_BOOT
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SPL_COMMON_INIT_DDR
+#endif
 #endif
 
 #ifdef CONFIG_SPIFLASH
-#define CONFIG_RAMBOOT_SPIFLASH
-#define CONFIG_SYS_RAMBOOT
-#define CONFIG_SYS_EXTRA_ENV_RELOC
-#define CONFIG_SYS_TEXT_BASE		0x11000000
-#define CONFIG_RESET_VECTOR_ADDRESS	0x1107fffc
+#define CONFIG_SPL
+#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
+#define CONFIG_SPL_ENV_SUPPORT
+#define CONFIG_SPL_SERIAL_SUPPORT
+#define CONFIG_SPL_SPI_SUPPORT
+#define CONFIG_SPL_SPI_FLASH_SUPPORT
+#define CONFIG_SPL_SPI_FLASH_MINIMAL
+#define CONFIG_SPL_FLUSH_IMAGE
+#define CONFIG_SPL_TARGET		"u-boot-with-spl.bin"
+#define CONFIG_SPL_LIBGENERIC_SUPPORT
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+#define CONFIG_SPL_I2C_SUPPORT
+#define CONFIG_FSL_LAW         /* Use common FSL init code */
+#define CONFIG_SYS_TEXT_BASE		0x11001000
+#define CONFIG_SPL_TEXT_BASE		0xf8f81000
+#define CONFIG_SPL_PAD_TO		0x20000
+#define CONFIG_SPL_MAX_SIZE		(128 * 1024)
+#define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE	(768 << 10)
+#define CONFIG_SYS_SPI_FLASH_U_BOOT_DST		(0x11000000)
+#define CONFIG_SYS_SPI_FLASH_U_BOOT_START	(0x11000000)
+#define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS	(128 << 10)
+#define CONFIG_SYS_MPC85XX_NO_RESETVEC
+#define CONFIG_SYS_LDSCRIPT	"arch/powerpc/cpu/mpc85xx/u-boot.lds"
+#define CONFIG_SPL_SPI_BOOT
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SPL_COMMON_INIT_DDR
+#endif
 #endif
 
 #ifdef CONFIG_NAND
 #define CONFIG_SPL
+#define CONFIG_TPL
+#ifdef CONFIG_TPL_BUILD
+#define CONFIG_SPL_NAND_BOOT
+#define CONFIG_SPL_FLUSH_IMAGE
+#define CONFIG_SPL_ENV_SUPPORT
+#define CONFIG_SPL_NAND_INIT
+#define CONFIG_SPL_SERIAL_SUPPORT
+#define CONFIG_SPL_LIBGENERIC_SUPPORT
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+#define CONFIG_SPL_I2C_SUPPORT
+#define CONFIG_SPL_NAND_SUPPORT
+#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
+#define CONFIG_SPL_COMMON_INIT_DDR
+#define CONFIG_SPL_MAX_SIZE		(128 << 10)
+#define CONFIG_SPL_TEXT_BASE		0xf8f81000
+#define CONFIG_SYS_MPC85XX_NO_RESETVEC
+#define CONFIG_SYS_NAND_U_BOOT_SIZE	(832 << 10)
+#define CONFIG_SYS_NAND_U_BOOT_DST	(0x11000000)
+#define CONFIG_SYS_NAND_U_BOOT_START	(0x11000000)
+#define CONFIG_SYS_NAND_U_BOOT_OFFS	((128 + 128) << 10)
+#elif defined(CONFIG_SPL_BUILD)
 #define CONFIG_SPL_INIT_MINIMAL
 #define CONFIG_SPL_SERIAL_SUPPORT
 #define CONFIG_SPL_NAND_SUPPORT
 #define CONFIG_SPL_FLUSH_IMAGE
 #define CONFIG_SPL_TARGET		"u-boot-with-spl.bin"
-
-#define CONFIG_SPL_TEXT_BASE		0xfffff000
+#define CONFIG_SPL_TEXT_BASE		0xff800000
 #define CONFIG_SPL_MAX_SIZE		4096
-
-#ifdef CONFIG_SYS_INIT_L2_ADDR
-/* We multiply CONFIG_SPL_MAX_SIZE by two to leave some room for BSS. */
-#define CONFIG_SYS_TEXT_BASE		0xf8f82000
-#define CONFIG_SPL_RELOC_TEXT_BASE	\
-	(CONFIG_SYS_INIT_L2_END - CONFIG_SPL_MAX_SIZE * 2)
-#define CONFIG_SPL_RELOC_STACK		\
-	(CONFIG_SYS_INIT_L2_END - CONFIG_SPL_MAX_SIZE * 2)
-#define CONFIG_SYS_NAND_U_BOOT_DST	(CONFIG_SYS_INIT_L2_ADDR)
-#define CONFIG_SYS_NAND_U_BOOT_START	\
-	(CONFIG_SYS_INIT_L2_ADDR + CONFIG_SPL_MAX_SIZE)
-#else
-#define CONFIG_SYS_TEXT_BASE		0x00201000
-#define CONFIG_SPL_RELOC_TEXT_BASE	0x00100000
-#define CONFIG_SPL_RELOC_STACK		0x00100000
-#define CONFIG_SYS_NAND_U_BOOT_DST	(0x00200000 - CONFIG_SPL_MAX_SIZE)
-#define CONFIG_SYS_NAND_U_BOOT_START	0x00200000
-#endif
-
-#define CONFIG_SYS_NAND_U_BOOT_SIZE	((512 << 10) - 0x2000)
-#define CONFIG_SYS_NAND_U_BOOT_OFFS	0
-#define CONFIG_SYS_LDSCRIPT		"arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
+#define CONFIG_SYS_NAND_U_BOOT_SIZE	(128 << 10)
+#define CONFIG_SYS_NAND_U_BOOT_DST	0xf8f80000
+#define CONFIG_SYS_NAND_U_BOOT_START	0xf8f80000
+#define CONFIG_SYS_NAND_U_BOOT_OFFS	(128 << 10)
+#endif /* not CONFIG_TPL_BUILD */
+
+#define CONFIG_SPL_PAD_TO		0x20000
+#define CONFIG_TPL_PAD_TO		0x20000
+#define CONFIG_SPL_TARGET		"u-boot-with-spl.bin"
+#define CONFIG_SYS_TEXT_BASE		0x11001000
+#define CONFIG_SYS_LDSCRIPT	"arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
 #endif
 
 #ifndef CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_TEXT_BASE		0xeff80000
+#define CONFIG_SYS_TEXT_BASE		0xeff40000
 #endif
 
 #ifndef CONFIG_RESET_VECTOR_ADDRESS
@@ -220,7 +265,6 @@
 /* High Level Configuration Options */
 #define CONFIG_BOOKE
 #define CONFIG_E500
-#define CONFIG_MPC85xx
 
 #define CONFIG_MP
 
@@ -280,7 +324,7 @@
 #endif
 
 /* DDR Setup */
-#define CONFIG_FSL_DDR3
+#define CONFIG_SYS_FSL_DDR3
 #define CONFIG_SYS_DDR_RAW_TIMING
 #define CONFIG_DDR_SPD
 #define CONFIG_SYS_SPD_BUS_NUM 1
@@ -526,6 +570,44 @@
 #define CONFIG_VSC7385_IMAGE_SIZE	8192
 #endif
 
+/*
+ * Config the L2 Cache as L2 SRAM
+*/
+#if defined(CONFIG_SPL_BUILD)
+#if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH)
+#define CONFIG_SYS_INIT_L2_ADDR		0xf8f80000
+#define CONFIG_SYS_INIT_L2_ADDR_PHYS	CONFIG_SYS_INIT_L2_ADDR
+#define CONFIG_SYS_INIT_L2_END	(CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
+#define CONFIG_SPL_RELOC_TEXT_BASE	0xf8f81000
+#define CONFIG_SPL_GD_ADDR		(CONFIG_SYS_INIT_L2_ADDR + 112 * 1024)
+#define CONFIG_SPL_RELOC_STACK		(CONFIG_SYS_INIT_L2_ADDR + 116 * 1024)
+#define CONFIG_SPL_RELOC_STACK_SIZE	(32 << 10)
+#define CONFIG_SPL_RELOC_MALLOC_ADDR	(CONFIG_SYS_INIT_L2_ADDR + 148 * 1024)
+#if defined(CONFIG_P2020RDB)
+#define CONFIG_SPL_RELOC_MALLOC_SIZE	(364 << 10)
+#else
+#define CONFIG_SPL_RELOC_MALLOC_SIZE	(108 << 10)
+#endif
+#elif defined(CONFIG_NAND)
+#ifdef CONFIG_TPL_BUILD
+#define CONFIG_SYS_INIT_L2_ADDR		0xf8f80000
+#define CONFIG_SYS_INIT_L2_ADDR_PHYS	CONFIG_SYS_INIT_L2_ADDR
+#define CONFIG_SYS_INIT_L2_END	(CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
+#define CONFIG_SPL_RELOC_TEXT_BASE	0xf8f81000
+#define CONFIG_SPL_RELOC_STACK		(CONFIG_SYS_INIT_L2_ADDR + 192 * 1024)
+#define CONFIG_SPL_RELOC_MALLOC_ADDR	(CONFIG_SYS_INIT_L2_ADDR + 208 * 1024)
+#define CONFIG_SPL_RELOC_MALLOC_SIZE	(48 << 10)
+#define CONFIG_SPL_GD_ADDR		(CONFIG_SYS_INIT_L2_ADDR + 176 * 1024)
+#else
+#define CONFIG_SYS_INIT_L2_ADDR		0xf8f80000
+#define CONFIG_SYS_INIT_L2_ADDR_PHYS	CONFIG_SYS_INIT_L2_ADDR
+#define CONFIG_SYS_INIT_L2_END	(CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
+#define CONFIG_SPL_RELOC_TEXT_BASE	(CONFIG_SYS_INIT_L2_END - 0x2000)
+#define CONFIG_SPL_RELOC_STACK		((CONFIG_SYS_INIT_L2_END - 1) & ~0xF)
+#endif /* CONFIG_TPL_BUILD */
+#endif
+#endif
+
 /* Serial Port - controlled on board with jumper J8
  * open - index 2
  * shorted - index 1
@@ -536,7 +618,7 @@
 #define CONFIG_SYS_NS16550_SERIAL
 #define CONFIG_SYS_NS16550_REG_SIZE	1
 #define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)
-#ifdef CONFIG_SPL_BUILD
+#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL)
 #define CONFIG_NS16550_MIN_FUNCTIONS
 #endif
 
@@ -733,7 +815,7 @@
 /*
  * Environment
  */
-#ifdef CONFIG_RAMBOOT_SPIFLASH
+#ifdef CONFIG_SPIFLASH
 #define CONFIG_ENV_IS_IN_SPI_FLASH
 #define CONFIG_ENV_SPI_BUS	0
 #define CONFIG_ENV_SPI_CS	0
@@ -742,15 +824,20 @@
 #define CONFIG_ENV_SIZE		0x2000	/* 8KB */
 #define CONFIG_ENV_OFFSET	0x100000	/* 1MB */
 #define CONFIG_ENV_SECT_SIZE	0x10000
-#elif defined(CONFIG_RAMBOOT_SDCARD)
+#elif defined(CONFIG_SDCARD)
 #define CONFIG_ENV_IS_IN_MMC
 #define CONFIG_FSL_FIXED_MMC_LOCATION
 #define CONFIG_ENV_SIZE		0x2000
 #define CONFIG_SYS_MMC_ENV_DEV	0
 #elif defined(CONFIG_NAND)
-#define CONFIG_ENV_IS_IN_NAND
+#ifdef CONFIG_TPL_BUILD
+#define CONFIG_ENV_SIZE		0x2000
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_INIT_L2_ADDR + (160 << 10))
+#else
 #define CONFIG_ENV_SIZE		CONFIG_SYS_NAND_BLOCK_SIZE
-#define CONFIG_ENV_OFFSET	((512 * 1024) + CONFIG_SYS_NAND_BLOCK_SIZE)
+#endif
+#define CONFIG_ENV_IS_IN_NAND
+#define CONFIG_ENV_OFFSET	(1024 * 1024)
 #define CONFIG_ENV_RANGE	(3 * CONFIG_ENV_SIZE)
 #elif defined(CONFIG_SYS_RAMBOOT)
 #define CONFIG_ENV_IS_NOWHERE	/* Store ENV in memory only */
@@ -758,11 +845,7 @@
 #define CONFIG_ENV_SIZE		0x2000
 #else
 #define CONFIG_ENV_IS_IN_FLASH
-#if CONFIG_SYS_MONITOR_BASE > 0xfff80000
-#define CONFIG_ENV_ADDR	0xfff80000
-#else
 #define CONFIG_ENV_ADDR	(CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
-#endif
 #define CONFIG_ENV_SIZE		0x2000
 #define CONFIG_ENV_SECT_SIZE	0x20000 /* 128K (one sector) */
 #endif
@@ -824,7 +907,6 @@
 #define CONFIG_SYS_LONGHELP			/* undef to save memory */
 #define CONFIG_CMDLINE_EDITING			/* Command-line editing */
 #define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
-#define CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt */
 #if defined(CONFIG_CMD_KGDB)
 #define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size */
 #else
@@ -834,7 +916,6 @@
 	/* Print Buffer Size */
 #define CONFIG_SYS_MAXARGS	16	/* max number of command args */
 #define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
-#define CONFIG_SYS_HZ		1000	/* decrementer freq: 1ms tick */
 
 /*
  * For booting Linux, the board info and command line data
@@ -846,7 +927,6 @@
 
 #if defined(CONFIG_CMD_KGDB)
 #define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
-#define CONFIG_KGDB_SER_INDEX	2	/* which serial port to use */
 #endif
 
 /*
diff --git a/include/configs/p1_twr.h b/include/configs/p1_twr.h
index 4aa706422e..c296a07599 100644
--- a/include/configs/p1_twr.h
+++ b/include/configs/p1_twr.h
@@ -24,11 +24,11 @@
 #define CONFIG_SYS_RAMBOOT
 #define CONFIG_SYS_EXTRA_ENV_RELOC
 #define CONFIG_SYS_TEXT_BASE		0x11000000
-#define CONFIG_RESET_VECTOR_ADDRESS	0x1107fffc
+#define CONFIG_RESET_VECTOR_ADDRESS	0x110bfffc
 #endif
 
 #ifndef CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_TEXT_BASE		0xeff80000
+#define CONFIG_SYS_TEXT_BASE		0xeff40000
 #endif
 
 #ifndef CONFIG_RESET_VECTOR_ADDRESS
@@ -42,7 +42,6 @@
 /* High Level Configuration Options */
 #define CONFIG_BOOKE
 #define CONFIG_E500
-#define CONFIG_MPC85xx
 
 #define CONFIG_MP
 
@@ -89,7 +88,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
 #define CONFIG_SYS_CCSRBAR_PHYS_LOW	CONFIG_SYS_CCSRBAR
 
 /* DDR Setup */
-#define CONFIG_FSL_DDR3
+#define CONFIG_SYS_FSL_DDR3
 
 #define CONFIG_SYS_SDRAM_SIZE_LAW	LAW_SIZE_512M
 #define CONFIG_CHIP_SELECTS_PER_CTRL	1
@@ -239,9 +238,6 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
 #define CONFIG_OF_BOARD_SETUP
 #define CONFIG_OF_STDOUT_VIA_ALIAS
 
-#define CONFIG_SYS_64BIT_VSPRINTF
-#define CONFIG_SYS_64BIT_STRTOUL
-
 /* new uImage format support */
 #define CONFIG_FIT
 #define CONFIG_FIT_VERBOSE	/* enable fit_format_{error,warning}() */
@@ -407,11 +403,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
 #endif
 #else
 #define CONFIG_ENV_IS_IN_FLASH
-#if CONFIG_SYS_MONITOR_BASE > 0xfff80000
-#define CONFIG_ENV_ADDR	0xfff80000
-#else
 #define CONFIG_ENV_ADDR	(CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
-#endif
 #define CONFIG_ENV_SIZE		0x2000
 #define CONFIG_ENV_SECT_SIZE	0x20000 /* 128K (one sector) */
 #endif
@@ -472,7 +464,6 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
 #define CONFIG_SYS_LONGHELP			/* undef to save memory */
 #define CONFIG_CMDLINE_EDITING			/* Command-line editing */
 #define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
-#define CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt */
 #if defined(CONFIG_CMD_KGDB)
 #define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size */
 #else
@@ -482,7 +473,6 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
 	/* Print Buffer Size */
 #define CONFIG_SYS_MAXARGS	16	/* max number of command args */
 #define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
-#define CONFIG_SYS_HZ		1000	/* decrementer freq: 1ms tick */
 
 /*
  * For booting Linux, the board info and command line data
diff --git a/include/configs/p3mx.h b/include/configs/p3mx.h
index 8157f47cce..a210e293a9 100644
--- a/include/configs/p3mx.h
+++ b/include/configs/p3mx.h
@@ -269,7 +269,6 @@
 #define CONFIG_SYS_HUSH_PARSER
 
 #define CONFIG_SYS_LONGHELP			/* undef to save memory		*/
-#define CONFIG_SYS_PROMPT	        "=> "	/* Monitor Command Prompt	*/
 #if defined(CONFIG_CMD_KGDB)
 #define CONFIG_SYS_CBSIZE	        1024	/* Console I/O Buffer Size	*/
 #else
@@ -284,8 +283,6 @@
 
 #define CONFIG_SYS_LOAD_ADDR		0x08000000	/* default load address */
 
-#define CONFIG_SYS_HZ		        1000	/* decrementer freq: 1 ms ticks */
-
 #define CONFIG_CMDLINE_EDITING	1	/* add command line history	*/
 #define CONFIG_LOOPW            1       /* enable loopw command         */
 #define CONFIG_MX_CYCLIC        1       /* enable mdc/mwc commands      */
diff --git a/include/configs/p3p440.h b/include/configs/p3p440.h
index f6cb813bc8..225567bd90 100644
--- a/include/configs/p3p440.h
+++ b/include/configs/p3p440.h
@@ -20,7 +20,6 @@
 #define CONFIG_P3P440		1	    /* Board is P3P440		*/
 #define CONFIG_440GP		1	    /* Specifc GP support	*/
 #define CONFIG_440		1	    /* ... PPC440 family	*/
-#define CONFIG_4xx		1	    /* ... PPC4xx family	*/
 #define CONFIG_BOARD_EARLY_INIT_F 1	    /* Call board_early_init_f	*/
 #define CONFIG_MISC_INIT_R	1	    /* Call misc_init_r		*/
 
@@ -197,7 +196,6 @@
  * Miscellaneous configurable options
  *----------------------------------------------------------------------*/
 #define CONFIG_SYS_LONGHELP			/* undef to save memory		*/
-#define CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt	*/
 #if defined(CONFIG_CMD_KGDB)
 #define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
 #else
@@ -213,8 +211,6 @@
 #define CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address */
 #define CONFIG_SYS_EXTBDINFO		1	/* To use extended board_into (bd_t) */
 
-#define CONFIG_SYS_HZ		1000		/* decrementer freq: 1 ms ticks */
-
 #define CONFIG_AUTO_COMPLETE	1       /* add autocompletion support   */
 #define CONFIG_LOOPW            1       /* enable loopw command         */
 #define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */
@@ -306,6 +302,5 @@
 
 #if defined(CONFIG_CMD_KGDB)
 #define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
-#define CONFIG_KGDB_SER_INDEX	2	/* which serial port to use */
 #endif
 #endif	/* __CONFIG_H */
diff --git a/include/configs/palmld.h b/include/configs/palmld.h
index 03020902bb..9480d8daf2 100644
--- a/include/configs/palmld.h
+++ b/include/configs/palmld.h
@@ -93,7 +93,6 @@
  */
 #ifdef	CONFIG_CMD_KGDB
 #define	CONFIG_KGDB_BAUDRATE		230400	/* kgdb serial port speed */
-#define	CONFIG_KGDB_SER_INDEX		2	/* which serial port to use */
 #endif
 
 /*
@@ -104,8 +103,6 @@
 #define	CONFIG_SYS_LONGHELP
 #ifdef	CONFIG_SYS_HUSH_PARSER
 #define	CONFIG_SYS_PROMPT		"$ "
-#else
-#define	CONFIG_SYS_PROMPT		"=> "
 #endif
 #define	CONFIG_SYS_CBSIZE		256
 #define	CONFIG_SYS_PBSIZE		\
@@ -118,7 +115,6 @@
  * Clock Configuration
  */
 #undef	CONFIG_SYS_CLKS_IN_HZ
-#define	CONFIG_SYS_HZ			3250000		/* Timer @ 3250000 Hz */
 #define	CONFIG_SYS_CPUSPEED		0x210		/* 416MHz ; N=2,L=16 */
 
 /*
@@ -161,10 +157,10 @@
 
 #define	CONFIG_SYS_FLASH_USE_BUFFER_WRITE	1
 
-#define	CONFIG_SYS_FLASH_ERASE_TOUT	(25*CONFIG_SYS_HZ)
-#define	CONFIG_SYS_FLASH_WRITE_TOUT	(25*CONFIG_SYS_HZ)
-#define	CONFIG_SYS_FLASH_LOCK_TOUT	(25*CONFIG_SYS_HZ)
-#define	CONFIG_SYS_FLASH_UNLOCK_TOUT	(25*CONFIG_SYS_HZ)
+#define	CONFIG_SYS_FLASH_ERASE_TOUT	240000
+#define	CONFIG_SYS_FLASH_WRITE_TOUT	240000
+#define	CONFIG_SYS_FLASH_LOCK_TOUT	240000
+#define	CONFIG_SYS_FLASH_UNLOCK_TOUT	240000
 #define	CONFIG_SYS_FLASH_PROTECTION
 
 #define	CONFIG_ENV_IS_IN_FLASH		1
diff --git a/include/configs/palmtc.h b/include/configs/palmtc.h
index d838356366..8abce1b425 100644
--- a/include/configs/palmtc.h
+++ b/include/configs/palmtc.h
@@ -95,7 +95,6 @@
  */
 #ifdef	CONFIG_CMD_KGDB
 #define	CONFIG_KGDB_BAUDRATE		230400	/* kgdb serial port speed */
-#define	CONFIG_KGDB_SER_INDEX		2	/* which serial port to use */
 #endif
 
 /*
@@ -106,8 +105,6 @@
 #define	CONFIG_SYS_LONGHELP
 #ifdef	CONFIG_SYS_HUSH_PARSER
 #define	CONFIG_SYS_PROMPT		"$ "
-#else
-#define	CONFIG_SYS_PROMPT		"=> "
 #endif
 #define	CONFIG_SYS_CBSIZE		256
 #define	CONFIG_SYS_PBSIZE		\
@@ -120,7 +117,6 @@
  * Clock Configuration
  */
 #undef	CONFIG_SYS_CLKS_IN_HZ
-#define	CONFIG_SYS_HZ			3686400		/* Timer @ 3686400 Hz */
 #define	CONFIG_SYS_CPUSPEED		0x161		/* 400MHz;L=1 M=3 T=1 */
 
 /*
@@ -158,10 +154,10 @@
 
 #define	CONFIG_SYS_FLASH_USE_BUFFER_WRITE	1
 
-#define	CONFIG_SYS_FLASH_ERASE_TOUT	(2*CONFIG_SYS_HZ)
-#define	CONFIG_SYS_FLASH_WRITE_TOUT	(2*CONFIG_SYS_HZ)
-#define	CONFIG_SYS_FLASH_LOCK_TOUT	(2*CONFIG_SYS_HZ)
-#define	CONFIG_SYS_FLASH_UNLOCK_TOUT	(2*CONFIG_SYS_HZ)
+#define	CONFIG_SYS_FLASH_ERASE_TOUT	240000
+#define	CONFIG_SYS_FLASH_WRITE_TOUT	240000
+#define	CONFIG_SYS_FLASH_LOCK_TOUT	240000
+#define	CONFIG_SYS_FLASH_UNLOCK_TOUT	240000
 #define	CONFIG_SYS_FLASH_PROTECTION
 
 #define	CONFIG_ENV_IS_IN_FLASH		1
diff --git a/include/configs/palmtreo680.h b/include/configs/palmtreo680.h
index 2ab6fd2e8a..36626639d3 100644
--- a/include/configs/palmtreo680.h
+++ b/include/configs/palmtreo680.h
@@ -94,7 +94,6 @@
  */
 #ifdef CONFIG_CMD_KGDB
 #define CONFIG_KGDB_BAUDRATE            230400  /* kgdb serial port speed */
-#define CONFIG_KGDB_SER_INDEX           2       /* which serial port to use */
 #endif
 
 /*
@@ -107,7 +106,6 @@
 #ifdef CONFIG_SYS_HUSH_PARSER
 #define CONFIG_SYS_PROMPT               "$ "
 #else
-#define CONFIG_SYS_PROMPT               "=> "
 #endif
 #define CONFIG_SYS_CBSIZE               256
 #define CONFIG_SYS_PBSIZE               \
@@ -120,7 +118,6 @@
  * Clock Configuration
  */
 #undef  CONFIG_SYS_CLKS_IN_HZ
-#define CONFIG_SYS_HZ                   1000 /* decrementer freq: 1 ms ticks */
 #define CONFIG_SYS_CPUSPEED             0x210           /* 416MHz ; N=2,L=16 */
 
 /*
diff --git a/include/configs/paz00.h b/include/configs/paz00.h
index 9e2686ac44..dd0abf8de6 100644
--- a/include/configs/paz00.h
+++ b/include/configs/paz00.h
@@ -17,7 +17,7 @@
 #ifndef __CONFIG_H
 #define __CONFIG_H
 
-#include <asm/sizes.h>
+#include <linux/sizes.h>
 #include "tegra20-common.h"
 
 /* Enable fdt support for Paz00. Flash the image in u-boot-dtb.bin */
diff --git a/include/configs/pb1x00.h b/include/configs/pb1x00.h
index cab9192de3..f92496571b 100644
--- a/include/configs/pb1x00.h
+++ b/include/configs/pb1x00.h
@@ -12,7 +12,6 @@
 #ifndef __CONFIG_H
 #define __CONFIG_H
 
-#define CONFIG_MIPS32		1  /* MIPS32 CPU core	*/
 #define CONFIG_PB1X00		1
 #define CONFIG_SOC_AU1X00	1  /* alchemy series cpu */
 
@@ -66,8 +65,6 @@
 
 #define CONFIG_SYS_MIPS_TIMER_FREQ	396000000
 
-#define CONFIG_SYS_HZ			1000
-
 #define CONFIG_SYS_SDRAM_BASE		0x80000000     /* Cached addr */
 
 #define	CONFIG_SYS_LOAD_ADDR		0x81000000     /* default load address	*/
diff --git a/include/configs/pcm030.h b/include/configs/pcm030.h
index 423e2fa6db..31a93c87de 100644
--- a/include/configs/pcm030.h
+++ b/include/configs/pcm030.h
@@ -20,8 +20,7 @@
 High Level Configuration Options
 (easy to change)
 -----------------------------------------------------------------------------*/
-#define CONFIG_MPC5xxx		1	/* This is an MPC5xxx CPU */
-#define CONFIG_MPC5200		1	/* (more precisely an MPC5200 CPU) */
+#define CONFIG_MPC5200		1	/* This is an MPC5200 CPU */
 #define CONFIG_MPC5200_DDR	1	/* (with DDR-SDRAM) */
 #define CONFIG_PHYCORE_MPC5200B_TINY 1	/* phyCORE-MPC5200B -> */
 					/* FEC configuration and IDE */
@@ -364,7 +363,6 @@ RTC configuration
 #define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
 
 #define CONFIG_SYS_LOAD_ADDR 0x400000 /* default load address */
-#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
 
 #define CONFIG_DISPLAY_BOARDINFO 1
 
diff --git a/include/configs/pcm051.h b/include/configs/pcm051.h
index 2fff0beffa..9af3efd4b1 100644
--- a/include/configs/pcm051.h
+++ b/include/configs/pcm051.h
@@ -155,7 +155,6 @@
  /* Platform/Board specific defs */
 #define CONFIG_SYS_TIMERBASE		0x48040000	/* Use Timer2 */
 #define CONFIG_SYS_PTV			2	/* Divisor: 2^(PTV+1) => 8 */
-#define CONFIG_SYS_HZ			1000	/* 1ms clock */
 
 #define CONFIG_CONS_INDEX		1
 /* NS16550 Configuration */
@@ -173,11 +172,10 @@
 /* I2C Configuration */
 #define CONFIG_I2C
 #define CONFIG_CMD_I2C
-#define CONFIG_HARD_I2C
-#define CONFIG_SYS_I2C_SPEED		100000
-#define CONFIG_SYS_I2C_SLAVE		1
-#define CONFIG_I2C_MULTI_BUS
-#define CONFIG_DRIVER_OMAP24XX_I2C
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_OMAP24_I2C_SPEED	100000
+#define CONFIG_SYS_OMAP24_I2C_SLAVE	1
+#define CONFIG_SYS_I2C_OMAP24XX
 #define CONFIG_CMD_EEPROM
 #define CONFIG_ENV_EEPROM_IS_ON_I2C
 #define CONFIG_SYS_I2C_EEPROM_ADDR	0x50	/* Main EEPROM */
@@ -299,7 +297,6 @@
 #define CONFIG_NET_MULTI
 #define CONFIG_PHY_GIGE
 #define CONFIG_PHYLIB
-#define CONFIG_PHY_ADDR			0
 #define CONFIG_PHY_SMSC
 
 #endif	/* ! __CONFIG_PCM051_H */
diff --git a/include/configs/pcs440ep.h b/include/configs/pcs440ep.h
index 7cf22ba763..e6e06f2d2e 100644
--- a/include/configs/pcs440ep.h
+++ b/include/configs/pcs440ep.h
@@ -23,7 +23,6 @@
 #define CONFIG_PCS440EP		1	/* Board is PCS440EP            */
 #define CONFIG_440EP		1	/* Specific PPC440EP support    */
 #define CONFIG_440		1	/* ... PPC440 family	        */
-#define CONFIG_4xx		1	/* ... PPC4xx family	        */
 
 #define	CONFIG_SYS_TEXT_BASE	0xFFFA0000
 
@@ -276,7 +275,6 @@
  * Miscellaneous configurable options
  */
 #define CONFIG_SYS_LONGHELP			/* undef to save memory		*/
-#define CONFIG_SYS_PROMPT	        "=> "	/* Monitor Command Prompt	*/
 #if defined(CONFIG_CMD_KGDB)
 #define CONFIG_SYS_CBSIZE	        1024	/* Console I/O Buffer Size	*/
 #else
@@ -293,8 +291,6 @@
 #define CONFIG_SYS_EXTBDINFO		1	/* To use extended board_into (bd_t) */
 #define CONFIG_LYNXKDI          1       /* support kdi files            */
 
-#define CONFIG_SYS_HZ		        1000	/* decrementer freq: 1 ms ticks */
-
 /*-----------------------------------------------------------------------
  * PCI stuff
  *-----------------------------------------------------------------------
@@ -430,7 +426,6 @@
 
 #if defined(CONFIG_CMD_KGDB)
 #define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
-#define CONFIG_KGDB_SER_INDEX	2	/* which serial port to use */
 #endif
 
 /*-----------------------------------------------------------------------
diff --git a/include/configs/pdm360ng.h b/include/configs/pdm360ng.h
index d31c137967..553eb8f967 100644
--- a/include/configs/pdm360ng.h
+++ b/include/configs/pdm360ng.h
@@ -30,7 +30,6 @@
  * High Level Configuration Options
  */
 #define CONFIG_E300		1	/* E300 Family */
-#define CONFIG_MPC512X		1	/* MPC512X family */
 #define CONFIG_FSL_DIU_FB	1	/* FSL DIU */
 
 #define	CONFIG_SYS_TEXT_BASE	0xF0000000
@@ -402,7 +401,6 @@
  */
 #define CONFIG_SYS_LONGHELP			/* undef to save memory */
 #define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
-#define CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt */
 
 #ifdef CONFIG_CMD_KGDB
 	#define CONFIG_SYS_CBSIZE	1024	/* Console I/O Buffer Size */
@@ -417,7 +415,6 @@
 /* Boot Argument Buffer Size */
 #define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE
 /* Decrementer freq: 1ms ticks */
-#define CONFIG_SYS_HZ		1000
 
 /*
  * For booting Linux, the board info and command line data
@@ -443,7 +440,6 @@
 
 #ifdef CONFIG_CMD_KGDB
 #define CONFIG_KGDB_BAUDRATE	230400	/* speed of kgdb serial port */
-#define CONFIG_KGDB_SER_INDEX	2	/* which serial port to use */
 #endif
 
 /* POST support */
diff --git a/include/configs/pdnb3.h b/include/configs/pdnb3.h
deleted file mode 100644
index d3e9017a00..0000000000
--- a/include/configs/pdnb3.h
+++ /dev/null
@@ -1,322 +0,0 @@
-/*
- * (C) Copyright 2006-2007
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * Configuation settings for the PDNB3 board.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-#define CONFIG_IXP425		1       /* This is an IXP425 CPU	*/
-#define CONFIG_PDNB3		1       /* on an PDNB3 board		*/
-
-#define	CONFIG_MACH_TYPE	1002
-
-#define CONFIG_DISPLAY_CPUINFO	1	/* display cpu info (and speed)	*/
-#define CONFIG_DISPLAY_BOARDINFO 1	/* display board info		*/
-
-/*
- * Ethernet
- */
-#define CONFIG_IXP4XX_NPE	1	/* include IXP4xx NPE support	*/
-#define	CONFIG_PHY_ADDR		16	/* NPE0 PHY address		*/
-#define CONFIG_HAS_ETH1
-#define CONFIG_PHY1_ADDR	18	/* NPE1 PHY address		*/
-#define CONFIG_MII		1	/* MII PHY management		*/
-#define CONFIG_SYS_RX_ETH_BUFFER	16	/* Number of ethernet rx buffers & descriptors */
-
-/*
- * Misc configuration options
- */
-#define CONFIG_BOOTCOUNT_LIMIT		/* support for bootcount limit	*/
-#define CONFIG_SYS_BOOTCOUNT_ADDR	0x60003000 /* inside qmrg sram		*/
-
-#define CONFIG_CMDLINE_TAG	1	/* enable passing of ATAGs	*/
-#define CONFIG_SETUP_MEMORY_TAGS 1
-#define CONFIG_INITRD_TAG	1
-
-/*
- * Size of malloc() pool
- */
-#define CONFIG_SYS_MALLOC_LEN		(1 << 20)
-
-/* allow to overwrite serial and ethaddr */
-#define CONFIG_ENV_OVERWRITE
-
-#define CONFIG_IXP_SERIAL
-#define CONFIG_BAUDRATE         115200
-#define CONFIG_SYS_IXP425_CONSOLE	IXP425_UART1   /* we use UART1 for console */
-
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_DATE
-#define CONFIG_CMD_NET
-#define CONFIG_CMD_MII
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_ELF
-#define CONFIG_CMD_PING
-
-#if !defined(CONFIG_SCPU)
-#define CONFIG_CMD_NAND
-#endif
-
-
-#define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */
-#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP                            /* undef to save memory         */
-#define CONFIG_SYS_PROMPT              "=> "   /* Monitor Command Prompt       */
-#define CONFIG_SYS_CBSIZE              256             /* Console I/O Buffer Size      */
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS             16              /* max number of command args   */
-#define CONFIG_SYS_BARGSIZE            CONFIG_SYS_CBSIZE      /* Boot Argument Buffer Size    */
-
-#define CONFIG_SYS_MEMTEST_START       0x00400000      /* memtest works on     */
-#define CONFIG_SYS_MEMTEST_END         0x00800000      /* 4 ... 8 MB in DRAM   */
-#define CONFIG_SYS_LOAD_ADDR           0x00010000      /* default load address */
-
-#define CONFIG_IXP425_TIMER_CLK		66666666
-#define CONFIG_SYS_HZ			1000		/* decrementer freq: 1 ms ticks */
-
-/***************************************************************
- * Platform/Board specific defines start here.
- ***************************************************************/
-
-/*-----------------------------------------------------------------------
- * Default configuration (environment varibles...)
- *----------------------------------------------------------------------*/
-#define CONFIG_PREBOOT	"echo;"	\
-	"echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
-	"echo"
-
-#undef	CONFIG_BOOTARGS
-
-#define	CONFIG_EXTRA_ENV_SETTINGS					\
-	"netdev=eth0\0"							\
-	"hostname=pdnb3\0"						\
-	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
-		"nfsroot=${serverip}:${rootpath}\0"			\
-	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
-	"addip=setenv bootargs ${bootargs} ethaddr=${ethaddr} "		\
-		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
-		":${hostname}:${netdev}:off panic=1\0"			\
-	"addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate} "	\
-	"mtdparts=${mtdparts}\0"					\
-	"flash_nfs=run nfsargs addip addtty;"				\
-		"bootm ${kernel_addr}\0"				\
-	"flash_self=run ramargs addip addtty;"				\
-		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
-	"net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;"     \
-		"bootm\0"						\
-	"rootpath=/opt/buildroot\0"					\
-	"bootfile=/tftpboot/netbox/uImage\0"				\
-	"kernel_addr=50080000\0"					\
-	"ramdisk_addr=50200000\0"					\
-	"load=tftp 100000 /tftpboot/netbox/u-boot.bin\0"		\
-	"update=protect off 50000000 5007dfff;era 50000000 5007dfff;"	\
-		"cp.b 100000 50000000 ${filesize};"			\
-		"setenv filesize;saveenv\0"				\
-	"upd=run load update\0"						\
-	"ipaddr=10.0.0.233\0"						\
-	"serverip=10.0.0.152\0"						\
-	"netmask=255.255.0.0\0"						\
-	"ethaddr=c6:6f:13:36:f3:81\0"					\
-	"eth1addr=c6:6f:13:36:f3:82\0"					\
-	"mtdparts=IXP4XX-Flash.0:504k@0(uboot),4k@504k(env),"		\
-	"4k@508k(renv)\0"						\
-	""
-#define CONFIG_BOOTCOMMAND	"run net_nfs"
-
-/*
- * Physical Memory Map
- */
-#define CONFIG_NR_DRAM_BANKS    1          /* we have 1 bank of DRAM */
-#define PHYS_SDRAM_1            0x00000000 /* SDRAM Bank #1 */
-#define PHYS_SDRAM_1_SIZE       0x02000000 /* 32 MB */
-
-#define CONFIG_SYS_TEXT_BASE	       0x50000000
-#define CONFIG_SYS_FLASH_BASE          0x50000000
-#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_FLASH_BASE
-#if defined(CONFIG_SCPU)
-#define CONFIG_SYS_MONITOR_LEN		(384 << 10)	/* Reserve 512 kB for Monitor	*/
-#else
-#define CONFIG_SYS_MONITOR_LEN		(504 << 10)	/* Reserve 512 kB for Monitor	*/
-#endif
-
-/*
- * Expansion bus settings
- */
-#if defined(CONFIG_SCPU)
-#define CONFIG_SYS_EXP_CS0		0x94d23C42	/* 8bit, max size		*/
-#else
-#define CONFIG_SYS_EXP_CS0		0x94913C43	/* 8bit, max size		*/
-#endif
-#define CONFIG_SYS_EXP_CS1		0x85000043	/* 8bit, 512bytes		*/
-
-/*
- * SDRAM settings
- */
-#define CONFIG_SYS_SDR_CONFIG		0x18
-#define CONFIG_SYS_SDR_MODE_CONFIG	0x1
-#define CONFIG_SYS_SDRAM_REFRESH_CNT	0x81a
-
-/*
- * FLASH and environment organization
- */
-#if defined(CONFIG_SCPU)
-#define CONFIG_SYS_FLASH_CFI				/* The flash is CFI compatible	*/
-#define CONFIG_FLASH_CFI_DRIVER			/* Use common CFI driver	*/
-#define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_16BIT	/* no byte writes on IXP4xx	*/
-#endif
-
-#define FLASH_BASE0_PRELIM	CONFIG_SYS_FLASH_BASE		/* FLASH bank #0	*/
-
-#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
-#define CONFIG_SYS_MAX_FLASH_SECT	256	/* max number of sectors on one chip	*/
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
-#define CONFIG_SYS_FLASH_WRITE_TOUT	1000	/* Timeout for Flash Write (in ms)	*/
-
-#define CONFIG_SYS_FLASH_WORD_SIZE	unsigned char	/* flash word size (width)	*/
-#define CONFIG_SYS_FLASH_ADDR0		0x5555	/* 1st address for flash config cycles	*/
-#define CONFIG_SYS_FLASH_ADDR1		0x2AAA	/* 2nd address for flash config cycles	*/
-/*
- * The following defines are added for buggy IOP480 byte interface.
- * All other boards should use the standard values (CPCI405 etc.)
- */
-#define CONFIG_SYS_FLASH_READ0		0x0000	/* 0 is standard			*/
-#define CONFIG_SYS_FLASH_READ1		0x0001	/* 1 is standard			*/
-#define CONFIG_SYS_FLASH_READ2		0x0002	/* 2 is standard			*/
-
-#define CONFIG_SYS_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
-
-#define	CONFIG_ENV_IS_IN_FLASH	1
-
-#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN)
-#if defined(CONFIG_SCPU)
-/* no redundant environment on SCPU */
-#define CONFIG_ENV_SECT_SIZE	0x20000 /* size of one complete sector		*/
-#define	CONFIG_ENV_SIZE		0x4000	/* Total Size of Environment Sector	*/
-#else
-#define CONFIG_ENV_SECT_SIZE	0x1000	/* size of one complete sector		*/
-#define	CONFIG_ENV_SIZE		0x1000	/* Total Size of Environment Sector	*/
-
-/* Address and size of Redundant Environment Sector	*/
-#define CONFIG_ENV_ADDR_REDUND	(CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
-#define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SIZE)
-#endif
-
-#if !defined(CONFIG_SCPU)
-/*
- * NAND-FLASH stuff
- */
-#define CONFIG_SYS_MAX_NAND_DEVICE	1
-#define CONFIG_SYS_NAND_BASE		0x51000000	/* NAND FLASH Base Address */
-#endif
-
-/*
- * GPIO settings
- */
-
-/* FPGA program pin configuration */
-#define CONFIG_SYS_GPIO_PRG		12		/* FPGA program pin (cpu output)*/
-#define CONFIG_SYS_GPIO_CLK		10		/* FPGA clk pin (cpu output)    */
-#define CONFIG_SYS_GPIO_DATA		14		/* FPGA data pin (cpu output)   */
-#define CONFIG_SYS_GPIO_INIT		13		/* FPGA init pin (cpu input)    */
-#define CONFIG_SYS_GPIO_DONE		11		/* FPGA done pin (cpu input)    */
-
-/* other GPIO's */
-#define CONFIG_SYS_GPIO_RESTORE_INT	0
-#define CONFIG_SYS_GPIO_RESTART_INT	1
-#define CONFIG_SYS_GPIO_SYS_RUNNING	2
-#define CONFIG_SYS_GPIO_PCI_INTA	3
-#define CONFIG_SYS_GPIO_PCI_INTB	4
-#define CONFIG_SYS_GPIO_I2C_SCL	6
-#define CONFIG_SYS_GPIO_I2C_SDA	7
-#define CONFIG_SYS_GPIO_FPGA_RESET	9
-#define CONFIG_SYS_GPIO_CLK_33M	15
-
-/*
- * I2C stuff
- */
-
-/* enable I2C and select the hardware/software driver */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_SOFT		/* I2C bit-banged */
-#define CONFIG_SYS_I2C_SOFT_SPEED	83000	/* 83 kHz is supposed to work */
-#define CONFIG_SYS_I2C_SOFT_SLAVE	0xFE
-/*
- * Software (bit-bang) I2C driver configuration
- */
-#define PB_SCL		(1 << CONFIG_SYS_GPIO_I2C_SCL)
-#define PB_SDA		(1 << CONFIG_SYS_GPIO_I2C_SDA)
-
-#define I2C_INIT	GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_I2C_SCL)
-#define I2C_ACTIVE	GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_I2C_SDA)
-#define I2C_TRISTATE	GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_I2C_SDA)
-#define I2C_READ	((*IXP425_GPIO_GPINR & PB_SDA) != 0)
-#define I2C_SDA(bit)	if (bit) GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_I2C_SDA);	\
-			else     GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_I2C_SDA)
-#define I2C_SCL(bit)	if (bit) GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_I2C_SCL);	\
-			else     GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_I2C_SCL)
-#define I2C_DELAY	udelay(3)	/* 1/4 I2C clock duration */
-
-/*
- * I2C RTC
- */
-#if 0 /* test-only */
-#define CONFIG_RTC_DS1340	1
-#define CONFIG_SYS_I2C_RTC_ADDR	0x68
-#else
-/* M41T11 Serial Access Timekeeper(R) SRAM */
-#define CONFIG_RTC_M41T11	1
-#define CONFIG_SYS_I2C_RTC_ADDR	0x68
-#define CONFIG_SYS_M41T11_BASE_YEAR	1900	/* play along with the linux driver */
-#endif
-
-/*
- * Spartan3 FPGA configuration support
- */
-#define CONFIG_SYS_FPGA_MAX_SIZE	700*1024	/* 700kByte for XC3S500E	*/
-
-#define CONFIG_SYS_FPGA_PRG	(1 << CONFIG_SYS_GPIO_PRG)	/* FPGA program pin (cpu output)*/
-#define CONFIG_SYS_FPGA_CLK	(1 << CONFIG_SYS_GPIO_CLK)	/* FPGA clk pin (cpu output)    */
-#define CONFIG_SYS_FPGA_DATA	(1 << CONFIG_SYS_GPIO_DATA)	/* FPGA data pin (cpu output)   */
-#define CONFIG_SYS_FPGA_INIT	(1 << CONFIG_SYS_GPIO_INIT)	/* FPGA init pin (cpu input)    */
-#define CONFIG_SYS_FPGA_DONE	(1 << CONFIG_SYS_GPIO_DONE)	/* FPGA done pin (cpu input)    */
-
-/*
- * Cache Configuration
- */
-#define CONFIG_SYS_CACHELINE_SIZE	32
-
-/* additions for new relocation code, must be added to all boards */
-#define CONFIG_SYS_SDRAM_BASE		0x00000000
-#define CONFIG_SYS_INIT_SP_ADDR        \
-	(CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE)
-
-#endif  /* __CONFIG_H */
diff --git a/include/configs/pengwyn.h b/include/configs/pengwyn.h
new file mode 100644
index 0000000000..fc25966e0f
--- /dev/null
+++ b/include/configs/pengwyn.h
@@ -0,0 +1,207 @@
+/*
+ * pengwyn.h
+ *
+ * Copyright (C) 2013 Lothar Felten <lothar.felten@gmail.com>
+ *
+ * based on am335x_evm.h, Copyright (C) 2011 Texas Instruments Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_PENGWYN_H
+#define __CONFIG_PENGWYN_H
+
+#define CONFIG_NAND
+#define CONFIG_SERIAL1
+#define CONFIG_CONS_INDEX		1
+
+#include <configs/ti_am335x_common.h>
+
+/* Clock Defines */
+#define V_OSCK				24000000
+#define V_SCLK				V_OSCK
+
+/* set env size */
+#define CONFIG_ENV_SIZE			0x4000
+
+#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+
+#ifndef CONFIG_SPL_BUILD
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"loadaddr=0x80200000\0" \
+	"fdtaddr=0x80F80000\0" \
+	"bootpart=0:2\0" \
+	"bootdir=/boot\0" \
+	"bootfile=zImage\0" \
+	"fdtfile=am335x-pengwyn.dtb\0" \
+	"console=ttyO0,115200n8\0" \
+	"optargs=\0" \
+	"mmcdev=0\0" \
+	"mmcroot=/dev/mmcblk0p2 ro\0" \
+	"mmcrootfstype=ext4 rootwait\0" \
+	"rootpath=/export/rootfs\0" \
+	"nfsopts=nolock\0" \
+	"static_ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}" \
+		"::off\0" \
+	"mmcargs=setenv bootargs console=${console} " \
+		"${optargs} " \
+		"root=${mmcroot} " \
+		"rootfstype=${mmcrootfstype}\0" \
+	"netargs=setenv bootargs console=${console} " \
+		"${optargs} " \
+		"root=/dev/nfs " \
+		"nfsroot=${serverip}:${rootpath},${nfsopts} rw " \
+		"ip=dhcp\0" \
+	"bootenv=uEnv.txt\0" \
+	"loadbootenv=load mmc ${mmcdev} ${loadaddr} ${bootenv}\0" \
+	"importbootenv=echo Importing environment from mmc ...; " \
+		"env import -t $loadaddr $filesize\0" \
+	"loadimage=load mmc ${bootpart} ${loadaddr} ${bootdir}/${bootfile}\0" \
+	"loadfdt=load mmc ${bootpart} ${fdtaddr} ${bootdir}/${fdtfile}\0" \
+	"mmcloados=run mmcargs; " \
+		"bootz ${loadaddr} - ${fdtaddr};\0" \
+	"mmcboot=mmc dev ${mmcdev}; " \
+		"if mmc rescan; then " \
+			"echo SD/MMC found on device ${mmcdev};" \
+			"if run loadbootenv; then " \
+				"echo Loaded environment from ${bootenv};" \
+				"run importbootenv;" \
+			"fi;" \
+			"if test -n $uenvcmd; then " \
+				"echo Running uenvcmd ...;" \
+				"run uenvcmd;" \
+			"fi;" \
+			"if run loadimage; then " \
+				"run loadfdt;" \
+				"run mmcloados;" \
+			"fi;" \
+		"fi;\0" \
+	"netboot=echo Booting from network ...; " \
+		"setenv autoload no; " \
+		"dhcp; " \
+		"tftp ${loadaddr} ${bootfile}; " \
+		"tftp ${fdtaddr} ${fdtfile}; " \
+		"run netargs; " \
+		"bootz ${loadaddr} - ${fdtaddr}\0" \
+	"mtdids=" MTDIDS_DEFAULT "\0" \
+	"mtdparts=" MTDPARTS_DEFAULT "\0" \
+	"nandargs=setenv bootargs console=${console} " \
+		"${optargs} " \
+		"root=${nandroot} " \
+		"rootfstype=${nandrootfstype}\0" \
+	"nandroot=ubi0:rootfs rw ubi.mtd=7,2048\0" \
+	"nandrootfstype=ubifs rootwait=1\0" \
+	"nandboot=echo Booting from nand ...; " \
+		"run nandargs; " \
+		"nand read ${fdtaddr} u-boot-spl-os; " \
+		"nand read ${loadaddr} kernel; " \
+		"bootz ${loadaddr} - ${fdtaddr}\0"
+#endif
+
+#define CONFIG_BOOTCOMMAND \
+	"run mmcboot;" \
+	"run nandboot;"
+
+/* NS16550 Configuration: primary UART via FDTI */
+#define CONFIG_SYS_NS16550_COM1		0x44e09000
+#define CONFIG_BAUDRATE			115200
+
+/* I2C Configuration */
+#define	CONFIG_SYS_I2C_SPEED		100000
+#define CONFIG_CMD_EEPROM
+#define CONFIG_ENV_EEPROM_IS_ON_I2C
+#define CONFIG_SYS_I2C_EEPROM_ADDR	0x50
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	2
+#define CONFIG_SYS_I2C_MULTI_EEPROMS
+
+/* SPL */
+#define CONFIG_SPL_POWER_SUPPORT
+#define CONFIG_SPL_YMODEM_SUPPORT
+
+/* General network SPL */
+#define CONFIG_SPL_NET_SUPPORT
+#define CONFIG_SPL_ENV_SUPPORT
+#define CONFIG_SPL_NET_VCI_STRING	"AM335x U-Boot SPL"
+
+/* NAND support */
+#define CONFIG_CMD_NAND
+#define CONFIG_NAND_OMAP_GPMC
+#define CONFIG_NAND_OMAP_ELM
+#define CONFIG_SYS_NAND_5_ADDR_CYCLE
+#define CONFIG_SYS_NAND_PAGE_COUNT	(CONFIG_SYS_NAND_BLOCK_SIZE / \
+					 CONFIG_SYS_NAND_PAGE_SIZE)
+#define CONFIG_SYS_NAND_PAGE_SIZE	2048
+#define CONFIG_SYS_NAND_OOBSIZE		64
+#define CONFIG_SYS_NAND_BLOCK_SIZE	(128*1024)
+#define CONFIG_SYS_NAND_BAD_BLOCK_POS	NAND_LARGE_BADBLOCK_POS
+#define CONFIG_SYS_NAND_ECCPOS		{ 2, 3, 4, 5, 6, 7, 8, 9, \
+					 10, 11, 12, 13, 14, 15, 16, 17, \
+					 18, 19, 20, 21, 22, 23, 24, 25, \
+					 26, 27, 28, 29, 30, 31, 32, 33, \
+					 34, 35, 36, 37, 38, 39, 40, 41, \
+					 42, 43, 44, 45, 46, 47, 48, 49, \
+					 50, 51, 52, 53, 54, 55, 56, 57, }
+
+#define CONFIG_SYS_NAND_ECCSIZE		512
+#define CONFIG_SYS_NAND_ECCBYTES	14
+#define CONFIG_SYS_NAND_ONFI_DETECTION
+#define CONFIG_NAND_OMAP_ECCSCHEME	OMAP_ECC_BCH8_CODE_HW
+#define CONFIG_SYS_NAND_U_BOOT_START	CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_NAND_U_BOOT_OFFS	0x80000
+
+#define GPMC_NAND_ECC_LP_x8_LAYOUT	1
+#define MTDIDS_DEFAULT			"nand0=omap2-nand.0"
+#define MTDPARTS_DEFAULT		"mtdparts=omap2-nand.0:128k(SPL)," \
+					"128k(SPL.backup1)," \
+					"128k(SPL.backup2)," \
+					"128k(SPL.backup3),1792k(u-boot)," \
+					"128k(u-boot-spl-os)," \
+					"128k(u-boot-env),5m(kernel),-(rootfs)"
+#define CONFIG_ENV_IS_IN_NAND
+#define CONFIG_ENV_OFFSET		0x260000 /* environment starts here */
+#define CONFIG_SYS_ENV_SECT_SIZE	(128 << 10)	/* 128 KiB */
+
+/*
+ * USB configuration.  We enable MUSB support, both for host and for
+ * gadget.  We set USB0 as peripheral and USB1 as host, based on the
+ * board schematic and physical port wired to each.  Then for host we
+ * add mass storage support.
+ */
+#define CONFIG_USB_MUSB_DSPS
+#define CONFIG_ARCH_MISC_INIT
+#define CONFIG_MUSB_GADGET
+#define CONFIG_MUSB_PIO_ONLY
+#define CONFIG_MUSB_DISABLE_BULK_COMBINE_SPLIT
+#define CONFIG_USB_GADGET
+#define CONFIG_USB_GADGET_DUALSPEED
+#define CONFIG_USB_GADGET_VBUS_DRAW	2
+#define CONFIG_MUSB_HOST
+#define CONFIG_AM335X_USB0
+#define CONFIG_AM335X_USB0_MODE	MUSB_PERIPHERAL
+#define CONFIG_AM335X_USB1
+#define CONFIG_AM335X_USB1_MODE MUSB_HOST
+
+#if defined(CONFIG_MUSB_HOST)
+#define CONFIG_CMD_USB
+#define CONFIG_USB_STORAGE
+#endif
+
+#if defined(CONFIG_SPL_BUILD)
+/* disable host part of MUSB in SPL */
+#undef CONFIG_MUSB_HOST
+/* Disable CPSW SPL support so we fit within the 101KiB limit. */
+#undef CONFIG_SPL_ETH_SUPPORT
+#endif
+
+/* Network */
+#define CONFIG_CMD_MII
+#define CONFIG_PHYLIB
+#define CONFIG_PHY_RESET	1
+#define CONFIG_PHY_NATSEMI
+
+/* CPSW support */
+#define CONFIG_SPL_ETH_SUPPORT
+
+#define CONFIG_SPL_LDSCRIPT		"$(CPUDIR)/am33xx/u-boot-spl.lds"
+
+#endif	/* ! __CONFIG_PENGWYN_H */
diff --git a/include/configs/pf5200.h b/include/configs/pf5200.h
index bb3351812e..be76478c30 100644
--- a/include/configs/pf5200.h
+++ b/include/configs/pf5200.h
@@ -22,8 +22,7 @@
  * (easy to change)
  */
 
-#define CONFIG_MPC5200		1	/* This is an MPC5xxx CPU */
-#define CONFIG_MPC5xxx		1	/* This is an MPC5xxx CPU */
+#define CONFIG_MPC5200		1	/* This is an MPC5200 CPU */
 #define CONFIG_ICECUBE		1	/* ... on IceCube board */
 #define CONFIG_PF5200		1	/* ... on PF5200  board */
 #define CONFIG_MPC5200_DDR	1	/* ... use DDR RAM	*/
@@ -239,7 +238,6 @@
  * Miscellaneous configurable options
  */
 #define CONFIG_SYS_LONGHELP		/* undef to save memory	    */
-#define CONFIG_SYS_PROMPT		"=> "	/* Monitor Command Prompt   */
 #if defined(CONFIG_CMD_KGDB)
 #define CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size  */
 #else
@@ -254,8 +252,6 @@
 
 #define CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address */
 
-#define CONFIG_SYS_HZ			1000	/* decrementer freq: 1 ms ticks */
-
 #define CONFIG_SYS_VXWORKS_MAC_PTR	0x00000000	/* Pass Ethernet MAC to VxWorks */
 
 #define CONFIG_SYS_CACHELINE_SIZE	32	/* For MPC5xxx CPUs */
diff --git a/include/configs/pm9261.h b/include/configs/pm9261.h
index 67b40b2fcc..4a71927217 100644
--- a/include/configs/pm9261.h
+++ b/include/configs/pm9261.h
@@ -28,8 +28,6 @@
 #define CONFIG_SYS_AT91_SLOW_CLOCK	32768		/* slow clock xtal */
 #define CONFIG_SYS_AT91_MAIN_CLOCK	18432000
 
-#define CONFIG_SYS_HZ		1000
-
 #define CONFIG_SYS_AT91_CPU_NAME	"AT91SAM9261"
 #define CONFIG_PM9261		1	/* on a Ronetix PM9261 Board	*/
 #define CONFIG_ARCH_CPU_INIT
@@ -52,15 +50,13 @@
 #define	CONFIG_SYS_MCKR1_VAL		\
 		(AT91_PMC_MCKR_CSS_SLOW |	\
 		 AT91_PMC_MCKR_PRES_1 |	\
-		 AT91_PMC_MCKR_MDIV_2 |	\
-		 AT91_PMC_MCKR_PLLADIV_1)
+		 AT91_PMC_MCKR_MDIV_2)
 
 /* PCK/2 = MCK Master Clock from PLLA */
 #define	CONFIG_SYS_MCKR2_VAL		\
 		(AT91_PMC_MCKR_CSS_PLLA |	\
 		 AT91_PMC_MCKR_PRES_1 |	\
-		 AT91_PMC_MCKR_MDIV_2 |	\
-		 AT91_PMC_MCKR_PLLADIV_1)
+		 AT91_PMC_MCKR_MDIV_2)
 
 /* define PDC[31:16] as DATA[31:16] */
 #define CONFIG_SYS_PIOC_PDR_VAL1	0xFFFF0000
@@ -168,9 +164,9 @@
 
 /* LED */
 #define CONFIG_AT91_LED
-#define	CONFIG_RED_LED		AT91_PIO_PORTC, 12
-#define	CONFIG_GREEN_LED	AT91_PIO_PORTC, 13
-#define	CONFIG_YELLOW_LED	AT91_PIO_PORTC, 15
+#define CONFIG_RED_LED		GPIO_PIN_PC(12)
+#define CONFIG_GREEN_LED	GPIO_PIN_PC(13)
+#define CONFIG_YELLOW_LED	GPIO_PIN_PC(15)
 
 #define CONFIG_BOOTDELAY	3
 
@@ -223,8 +219,8 @@
 #define CONFIG_SYS_NAND_MASK_ALE		(1 << 22)
 /* our CLE is AD21 */
 #define CONFIG_SYS_NAND_MASK_CLE		(1 << 21)
-#define CONFIG_SYS_NAND_ENABLE_PIN		AT91_PIO_PORTC, 14
-#define CONFIG_SYS_NAND_READY_PIN		AT91_PIO_PORTA, 16
+#define CONFIG_SYS_NAND_ENABLE_PIN		GPIO_PIN_PC(14)
+#define CONFIG_SYS_NAND_READY_PIN		GPIO_PIN_PA(16)
 
 /* NOR flash */
 #define CONFIG_SYS_FLASH_CFI			1
@@ -245,6 +241,7 @@
 
 /* USB */
 #define CONFIG_USB_ATMEL
+#define CONFIG_USB_ATMEL_CLK_SEL_PLLB
 #define CONFIG_USB_OHCI_NEW			1
 #define CONFIG_DOS_PARTITION			1
 #define CONFIG_SYS_USB_OHCI_CPU_INIT		1
diff --git a/include/configs/pm9263.h b/include/configs/pm9263.h
index 2b4335e78e..d9c04d14b9 100644
--- a/include/configs/pm9263.h
+++ b/include/configs/pm9263.h
@@ -28,8 +28,6 @@
 #define CONFIG_SYS_AT91_MAIN_CLOCK	18432000
 #define CONFIG_SYS_AT91_SLOW_CLOCK	32768		/* slow clock xtal */
 
-#define CONFIG_SYS_HZ		1000
-
 #define CONFIG_SYS_AT91_CPU_NAME	"AT91SAM9263"
 #define CONFIG_PM9263		1	/* on a Ronetix PM9263 Board	*/
 #define CONFIG_ARCH_CPU_INIT
@@ -181,8 +179,8 @@
 
 /* LED */
 #define CONFIG_AT91_LED
-#define	CONFIG_RED_LED		AT91_PIO_PORTB, 7	/* this is the power led */
-#define	CONFIG_GREEN_LED	AT91_PIO_PORTB, 8	/* this is the user1 led */
+#define CONFIG_RED_LED		GPIO_PIN_PB(7) /* this is the power led */
+#define CONFIG_GREEN_LED	GPIO_PIN_PB(8) /* this is the user1 led */
 
 #define CONFIG_BOOTDELAY	3
 
@@ -243,8 +241,8 @@
 #define CONFIG_SYS_NAND_MASK_ALE	(1 << 21)
 /* our CLE is AD22 */
 #define CONFIG_SYS_NAND_MASK_CLE	(1 << 22)
-#define CONFIG_SYS_NAND_ENABLE_PIN	AT91_PIO_PORTD, 15
-#define CONFIG_SYS_NAND_READY_PIN	AT91_PIO_PORTB, 30
+#define CONFIG_SYS_NAND_ENABLE_PIN	GPIO_PIN_PD(15)
+#define CONFIG_SYS_NAND_READY_PIN	GPIO_PIN_PB(30)
 
 #endif
 
@@ -272,6 +270,7 @@
 
 /* USB */
 #define CONFIG_USB_ATMEL
+#define CONFIG_USB_ATMEL_CLK_SEL_PLLB
 #define CONFIG_USB_OHCI_NEW			1
 #define CONFIG_DOS_PARTITION			1
 #define CONFIG_SYS_USB_OHCI_CPU_INIT		1
diff --git a/include/configs/pm9g45.h b/include/configs/pm9g45.h
index 7d16bd8b25..f78e0ec173 100644
--- a/include/configs/pm9g45.h
+++ b/include/configs/pm9g45.h
@@ -31,7 +31,6 @@
 /* ARM asynchronous clock */
 #define CONFIG_SYS_AT91_MAIN_CLOCK	12000000 /* from 12 MHz crystal */
 #define CONFIG_SYS_AT91_SLOW_CLOCK	32768		/* slow clock xtal */
-#define CONFIG_SYS_HZ			1000
 #define CONFIG_SYS_TEXT_BASE		0x73f00000
 
 #define CONFIG_ARCH_CPU_INIT
@@ -55,8 +54,8 @@
 
 /* LED */
 #define CONFIG_AT91_LED
-#define	CONFIG_RED_LED		AT91_PIO_PORTD, 31 /* this is the user1 led */
-#define	CONFIG_GREEN_LED	AT91_PIO_PORTD, 0 /* this is the user2 led */
+#define CONFIG_RED_LED		GPIO_PIN_PD(31) /* this is the user1 led */
+#define CONFIG_GREEN_LED	GPIO_PIN_PD(0)  /* this is the user2 led */
 
 #define CONFIG_BOOTDELAY	3
 
@@ -107,8 +106,8 @@
 #define CONFIG_SYS_NAND_MASK_ALE	(1 << 21)
 /* our CLE is AD22 */
 #define CONFIG_SYS_NAND_MASK_CLE	(1 << 22)
-#define CONFIG_SYS_NAND_ENABLE_PIN	AT91_PIO_PORTC, 14
-#define CONFIG_SYS_NAND_READY_PIN	AT91_PIO_PORTD, 3
+#define CONFIG_SYS_NAND_ENABLE_PIN	GPIO_PIN_PC(14)
+#define CONFIG_SYS_NAND_READY_PIN	GPIO_PIN_PD(3)
 
 #endif
 
@@ -120,6 +119,7 @@
 
 /* USB */
 #define CONFIG_USB_ATMEL
+#define CONFIG_USB_ATMEL_CLK_SEL_UPLL
 #define CONFIG_USB_OHCI_NEW		1
 #define CONFIG_DOS_PARTITION		1
 #define CONFIG_SYS_USB_OHCI_CPU_INIT	1
diff --git a/include/configs/ppmc7xx.h b/include/configs/ppmc7xx.h
index 3f9fdd444d..18f9a6cc20 100644
--- a/include/configs/ppmc7xx.h
+++ b/include/configs/ppmc7xx.h
@@ -272,7 +272,6 @@
 #define CONFIG_SYS_MEMTEST_START	0x00040000
 #define CONFIG_SYS_MEMTEST_END		0x00040100
 #define CONFIG_SYS_PBSIZE		1024
-#define CONFIG_SYS_PROMPT		"=> "
 
 
 /*
@@ -363,7 +362,6 @@
  */
 
 #define CONFIG_SYS_BUS_CLK		CONFIG_BUS_CLK
-#define CONFIG_SYS_HZ			1000
 
 
 /*
diff --git a/include/configs/ppmc8260.h b/include/configs/ppmc8260.h
index 752321c2fb..5dcd9cc0d0 100644
--- a/include/configs/ppmc8260.h
+++ b/include/configs/ppmc8260.h
@@ -267,7 +267,6 @@
 #define CONFIG_SYS_LONGHELP
 
 /* Monitor Command Prompt */
-#define CONFIG_SYS_PROMPT		"=> "
 
 
 /*
@@ -294,7 +293,6 @@
  *
  *****************************************************************************/
 
-#define CONFIG_MPC8260		1	/* This is an MPC8260 CPU   */
 #define CONFIG_PPMC8260		1	/* on an Wind River PPMC8260 Board  */
 #define CONFIG_CPM2		1	/* Has a CPM2 */
 
@@ -315,7 +313,6 @@
 #define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size	   */
 
 #define CONFIG_SYS_LOAD_ADDR		0x140000   /* default load address */
-#define CONFIG_SYS_HZ			1000	/* decrementer freq: 1 ms ticks */
 
 #define CONFIG_SYS_MEMTEST_START	0x2000	/* memtest works from the end of */
 					/* the exception vector table */
diff --git a/include/configs/pr1.h b/include/configs/pr1.h
index 03d4269584..e96ed4b4f2 100644
--- a/include/configs/pr1.h
+++ b/include/configs/pr1.h
@@ -135,7 +135,7 @@
 #define CONFIG_BOOTCOMMAND	"run nandboot"
 #define CONFIG_BOOTDELAY	2
 #define CONFIG_LOADADDR		0x2000000
-
+#define CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED
 
 /*
  * Pull in common ADI header for remaining command/environment setup
diff --git a/include/configs/pxa-common.h b/include/configs/pxa-common.h
index 5856ee180b..f0ecc34587 100644
--- a/include/configs/pxa-common.h
+++ b/include/configs/pxa-common.h
@@ -16,7 +16,6 @@
  */
 #ifdef	CONFIG_CMD_KGDB
 #define	CONFIG_KGDB_BAUDRATE		230400
-#define	CONFIG_KGDB_SER_INDEX		2
 #endif
 
 /*
diff --git a/include/configs/pxa255_idp.h b/include/configs/pxa255_idp.h
index 5ea7e67da5..af7c076df0 100644
--- a/include/configs/pxa255_idp.h
+++ b/include/configs/pxa255_idp.h
@@ -199,7 +199,6 @@
 
 #if defined(CONFIG_CMD_KGDB)
 #define CONFIG_KGDB_BAUDRATE	115200		/* speed to run kgdb serial port */
-#define CONFIG_KGDB_SER_INDEX	2		/* which serial port to use */
 #endif
 
 /*
@@ -211,7 +210,6 @@
 #ifdef CONFIG_SYS_HUSH_PARSER
 #define CONFIG_SYS_PROMPT		"$ "		/* Monitor Command Prompt */
 #else
-#define CONFIG_SYS_PROMPT		"=> "		/* Monitor Command Prompt */
 #endif
 #define CONFIG_SYS_CBSIZE		256		/* Console I/O Buffer Size	*/
 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
@@ -224,7 +222,6 @@
 
 #define CONFIG_SYS_LOAD_ADDR		0xa0800000	/* default load address */
 
-#define CONFIG_SYS_HZ			1000
 #define CONFIG_SYS_CPUSPEED		0x161		/* set core clock to 400/200/100 MHz */
 
 #define RTC	1				/* enable 32KHz osc */
diff --git a/include/configs/pxm2.h b/include/configs/pxm2.h
index 20b0f9ab4d..6276d43395 100644
--- a/include/configs/pxm2.h
+++ b/include/configs/pxm2.h
@@ -44,7 +44,6 @@
 #undef CONFIG_SPL_NET_VCI_STRING
 #undef CONFIG_SPL_ETH_SUPPORT
 
-#define CONFIG_PHY_ADDR			0
 #define CONFIG_PHY_ATHEROS
 
 #define CONFIG_FACTORYSET
@@ -70,6 +69,7 @@
 	"hostname=pxm2\0" \
 	"nand_img_size=0x500000\0" \
 	"optargs=\0" \
+	"splashpos=m,m\0"	\
 	CONFIG_COMMON_ENV_SETTINGS \
 	"mmc_dev=0\0" \
 	"mmc_root=/dev/mmcblk0p2 rw\0" \
@@ -118,9 +118,7 @@
 		"fi;" \
 	"fi;" \
 	"run nand_boot;" \
-	"if ping ${serverip}; then " \
-		"run net_nfs; " \
-	"fi; "
+	"reset;"
 
 #else
 #define CONFIG_BOOTDELAY		0
@@ -148,6 +146,8 @@
 #define DA8XX_LCD_CNTL_BASE	LCD_CNTL_BASE
 #define PWM_TICKS	0x1388
 #define PWM_DUTY	0x200
+#define CONFIG_SYS_CONSOLE_BG_COL	0xff
+#define CONFIG_SYS_CONSOLE_FG_COL	0x00
 #endif
 
 #endif	/* ! __CONFIG_PXM2_H */
diff --git a/include/configs/qemu-malta.h b/include/configs/qemu-malta.h
deleted file mode 100644
index 4e7ad33230..0000000000
--- a/include/configs/qemu-malta.h
+++ /dev/null
@@ -1,114 +0,0 @@
-/*
- * Copyright (C) 2013 Gabor Juhos <juhosg@openwrt.org>
- *
- * SPDX-License-Identifier:	GPL-2.0
- */
-
-#ifndef _QEMU_MALTA_CONFIG_H
-#define _QEMU_MALTA_CONFIG_H
-
-#include <asm/addrspace.h>
-#include <asm/malta.h>
-
-/*
- * System configuration
- */
-#define CONFIG_QEMU_MALTA
-
-#define CONFIG_PCI
-#define CONFIG_PCI_GT64120
-#define CONFIG_PCI_PNP
-#define CONFIG_PCNET
-
-/*
- * CPU Configuration
- */
-#define CONFIG_SYS_MHZ			250	/* arbitrary value */
-#define CONFIG_SYS_MIPS_TIMER_FREQ	(CONFIG_SYS_MHZ * 1000000)
-#define CONFIG_SYS_HZ			1000
-
-#define CONFIG_SYS_DCACHE_SIZE		16384	/* arbitrary value */
-#define CONFIG_SYS_ICACHE_SIZE		16384	/* arbitrary value */
-#define CONFIG_SYS_CACHELINE_SIZE	32	/* arbitrary value */
-
-#define CONFIG_SWAP_IO_SPACE
-
-/*
- * Memory map
- */
-#define CONFIG_SYS_TEXT_BASE		0xbfc00000 /* Rom version */
-#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_FLASH_BASE
-
-#define CONFIG_SYS_SDRAM_BASE		0x80000000 /* Cached addr */
-#define CONFIG_SYS_MEM_SIZE		(256 * 1024 * 1024)
-
-#define CONFIG_SYS_INIT_SP_OFFSET	0x400000
-
-#define CONFIG_SYS_LOAD_ADDR		0x81000000
-#define CONFIG_SYS_MEMTEST_START	0x80100000
-#define CONFIG_SYS_MEMTEST_END		0x80800000
-
-#define CONFIG_SYS_MALLOC_LEN		(128 * 1024)
-#define CONFIG_SYS_BOOTPARAMS_LEN	(128 * 1024)
-
-/*
- * Console configuration
- */
-#if defined(CONFIG_SYS_LITTLE_ENDIAN)
-#define CONFIG_SYS_PROMPT		"qemu-maltael # "
-#else
-#define CONFIG_SYS_PROMPT		"qemu-malta # "
-#endif
-
-#define CONFIG_SYS_CBSIZE		256
-#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
-					 sizeof(CONFIG_SYS_PROMPT) + 16)
-#define CONFIG_SYS_MAXARGS		16
-
-#define CONFIG_AUTO_COMPLETE
-#define CONFIG_CMDLINE_EDITING
-
-/*
- * Serial driver
- */
-#define CONFIG_BAUDRATE			115200
-
-#define CONFIG_SYS_NS16550
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE	1
-#define CONFIG_SYS_NS16550_CLK		115200
-#define CONFIG_SYS_NS16550_COM1		CKSEG1ADDR(MALTA_UART_BASE)
-#define CONFIG_CONS_INDEX		1
-
-/*
- * Environment
- */
-#define CONFIG_ENV_IS_NOWHERE
-#define CONFIG_ENV_SIZE			0x10000
-
-/*
- * Flash configuration
- */
-#define CONFIG_SYS_FLASH_BASE		(KSEG1 | MALTA_FLASH_BASE)
-#define CONFIG_SYS_MAX_FLASH_BANKS	1
-#define CONFIG_SYS_MAX_FLASH_SECT	128
-#define CONFIG_SYS_FLASH_CFI
-#define CONFIG_FLASH_CFI_DRIVER
-#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
-
-/*
- * Commands
- */
-#include <config_cmd_default.h>
-
-#undef CONFIG_CMD_FPGA
-#undef CONFIG_CMD_LOADB
-#undef CONFIG_CMD_LOADS
-#undef CONFIG_CMD_NFS
-
-#define CONFIG_CMD_PCI
-#define CONFIG_CMD_PING
-
-#define CONFIG_SYS_LONGHELP		/* verbose help, undef to save memory */
-
-#endif /* _QEMU_MALTA_CONFIG_H */
diff --git a/include/configs/qemu-mips.h b/include/configs/qemu-mips.h
index c3a69c5327..98ed8bc97f 100644
--- a/include/configs/qemu-mips.h
+++ b/include/configs/qemu-mips.h
@@ -12,7 +12,6 @@
 #ifndef __CONFIG_H
 #define __CONFIG_H
 
-#define CONFIG_MIPS32			/* MIPS32 CPU core */
 #define CONFIG_QEMU_MIPS
 #define CONFIG_MISC_INIT_R
 
@@ -106,8 +105,6 @@
 
 #define CONFIG_SYS_MIPS_TIMER_FREQ	(CONFIG_SYS_MHZ * 1000000)
 
-#define CONFIG_SYS_HZ			1000
-
 /* Cached addr */
 #define CONFIG_SYS_SDRAM_BASE		0x80000000
 
diff --git a/include/configs/qemu-mips64.h b/include/configs/qemu-mips64.h
index 7267a8115e..e8f5a4c9e8 100644
--- a/include/configs/qemu-mips64.h
+++ b/include/configs/qemu-mips64.h
@@ -12,7 +12,6 @@
 #ifndef __CONFIG_H
 #define __CONFIG_H
 
-#define CONFIG_MIPS64			/* MIPS64 CPU core */
 #define CONFIG_QEMU_MIPS
 #define CONFIG_MISC_INIT_R
 
@@ -108,8 +107,6 @@
 
 #define CONFIG_SYS_MIPS_TIMER_FREQ	(CONFIG_SYS_MHZ * 1000000)
 
-#define CONFIG_SYS_HZ			1000
-
 /* Cached addr */
 #define CONFIG_SYS_SDRAM_BASE		0xffffffff80000000
 
diff --git a/include/configs/qong.h b/include/configs/qong.h
index ee2ff7f043..f9d6642cc4 100644
--- a/include/configs/qong.h
+++ b/include/configs/qong.h
@@ -174,7 +174,6 @@
  * Miscellaneous configurable options
  */
 #define CONFIG_SYS_LONGHELP		/* undef to save memory */
-#define CONFIG_SYS_PROMPT		"=> "
 #define CONFIG_SYS_CBSIZE		512	/* Console I/O Buffer Size */
 /* Print Buffer Size */
 #define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
@@ -189,8 +188,6 @@
 
 #define CONFIG_SYS_LOAD_ADDR		CONFIG_LOADADDR
 
-#define CONFIG_SYS_HZ			1000
-
 #define CONFIG_CMDLINE_EDITING
 #define CONFIG_SYS_HUSH_PARSER			/* Use the HUSH parser */
 
diff --git a/include/configs/quad100hd.h b/include/configs/quad100hd.h
index e0925f6934..e91e805bb9 100644
--- a/include/configs/quad100hd.h
+++ b/include/configs/quad100hd.h
@@ -15,7 +15,6 @@
  * High Level Configuration Options
  *----------------------------------------------------------------------*/
 #define CONFIG_QUAD100HD	1		/* Board is Quad100hd	*/
-#define CONFIG_4xx		1		/* ... PPC4xx family	*/
 #define CONFIG_405EP		1		/* Specifc 405EP support*/
 
 #define	CONFIG_SYS_TEXT_BASE	0xFFFC0000
@@ -106,7 +105,6 @@
  * Miscellaneous configurable options
  *----------------------------------------------------------------------*/
 #define CONFIG_SYS_LONGHELP			/* undef to save memory		*/
-#define CONFIG_SYS_PROMPT	        "=> "	/* Monitor Command Prompt	*/
 #if defined(CONFIG_CMD_KGDB)
 #define CONFIG_SYS_CBSIZE	        1024	/* Console I/O Buffer Size	*/
 #else
@@ -122,8 +120,6 @@
 #define CONFIG_SYS_LOAD_ADDR		0x100000  /* default load address	*/
 #define CONFIG_SYS_EXTBDINFO		1	/* To use extended board_info (bd_t) */
 
-#define CONFIG_SYS_HZ		        1000	/* decrementer freq: 1 ms ticks	*/
-
 #define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
 #define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
 
@@ -268,7 +264,6 @@
 
 #if defined(CONFIG_CMD_KGDB)
 #define CONFIG_KGDB_BAUDRATE	230400		/* speed to run kgdb serial port */
-#define CONFIG_KGDB_SER_INDEX	2		/* which serial port to use */
 #endif
 
 /* ENVIRONMENT VARS */
diff --git a/include/configs/quantum.h b/include/configs/quantum.h
index 73156498ff..f3540c1421 100644
--- a/include/configs/quantum.h
+++ b/include/configs/quantum.h
@@ -109,7 +109,6 @@
  * Miscellaneous configurable options
  */
 #define CONFIG_SYS_LONGHELP			/* undef to save memory		*/
-#define CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt	*/
 #if defined(CONFIG_CMD_KGDB)
 #define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
 #else
@@ -124,8 +123,6 @@
 
 #define CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address */
 
-#define CONFIG_SYS_HZ		1000		/* decrementer freq: 1 ms ticks */
-
 /*
  * Low Level Configuration Settings
  * (address mappings, register initial values, etc.)
diff --git a/include/configs/r0p7734.h b/include/configs/r0p7734.h
index 080448090d..a71709bc7c 100644
--- a/include/configs/r0p7734.h
+++ b/include/configs/r0p7734.h
@@ -10,9 +10,6 @@
 #define __R0P7734_H
 
 #undef DEBUG
-#define CONFIG_SH		1
-#define CONFIG_SH4		1
-#define CONFIG_SH4A		1
 #define CONFIG_CPU_SH7734	1
 #define CONFIG_R0P7734		1
 #define CONFIG_400MHZ_MODE	1
@@ -73,7 +70,6 @@
 /* undef to save memory	*/
 #define CONFIG_SYS_LONGHELP
 /* Monitor Command Prompt */
-#define CONFIG_SYS_PROMPT		"=> "
 /* Buffer size for input from the Console */
 #define CONFIG_SYS_CBSIZE		256
 /* Buffer size for Console output */
@@ -144,8 +140,6 @@
 #define CONFIG_SYS_MONITOR_LEN	(256 * 1024)
 /* Size of DRAM reserved for malloc() use */
 #define CONFIG_SYS_MALLOC_LEN	(256 * 1024)
-/* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_SIZE	(256)
 #define CONFIG_SYS_BOOTMAPSZ	(8 * 1024 * 1024)
 
 /* ENV setting */
@@ -164,7 +158,8 @@
 #else
 #define CONFIG_SYS_CLK_FREQ 44444444
 #endif
+#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
+#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
 #define CONFIG_SYS_TMU_CLK_DIV      4
-#define CONFIG_SYS_HZ       1000
 
 #endif	/* __R0P7734_H */
diff --git a/include/configs/r2dplus.h b/include/configs/r2dplus.h
index 65dcffb29b..24d0c34db6 100644
--- a/include/configs/r2dplus.h
+++ b/include/configs/r2dplus.h
@@ -3,8 +3,6 @@
 
 #undef DEBUG
 
-#define CONFIG_SH		1
-#define CONFIG_SH4		1
 #define CONFIG_CPU_SH7751	1
 #define CONFIG_CPU_SH_TYPE_R	1
 #define CONFIG_R2DPLUS		1
@@ -41,7 +39,6 @@
 
 #define CONFIG_SYS_TEXT_BASE	0x0FFC0000
 #define CONFIG_SYS_LONGHELP
-#define CONFIG_SYS_PROMPT		"=> "
 #define CONFIG_SYS_CBSIZE		256
 #define CONFIG_SYS_PBSIZE		256
 #define CONFIG_SYS_MAXARGS		16
@@ -77,8 +74,9 @@
  * SuperH Clock setting
  */
 #define CONFIG_SYS_CLK_FREQ	60000000
+#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
+#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
 #define CONFIG_SYS_TMU_CLK_DIV		4
-#define CONFIG_SYS_HZ		1000
 #define	CONFIG_SYS_PLL_SETTLING_TIME	100/* in us */
 
 /*
diff --git a/include/configs/r7780mp.h b/include/configs/r7780mp.h
index dd1caf18bc..8156724f7f 100644
--- a/include/configs/r7780mp.h
+++ b/include/configs/r7780mp.h
@@ -11,8 +11,6 @@
 #define __R7780RP_H
 
 #undef DEBUG
-#define CONFIG_SH		1
-#define CONFIG_SH4A		1
 #define CONFIG_CPU_SH7780	1
 #define CONFIG_R7780MP		1
 #define CONFIG_SYS_R7780MP_OLD_FLASH	1
@@ -49,7 +47,6 @@
 #define CONFIG_SYS_SDRAM_SIZE		(128 * 1024 * 1024)
 
 #define CONFIG_SYS_LONGHELP
-#define CONFIG_SYS_PROMPT		"=> "
 #define CONFIG_SYS_CBSIZE		256
 #define CONFIG_SYS_PBSIZE		256
 #define CONFIG_SYS_MAXARGS		16
@@ -102,8 +99,9 @@
 
 /* Board Clock */
 #define CONFIG_SYS_CLK_FREQ	33333333
+#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
+#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
 #define CONFIG_SYS_TMU_CLK_DIV		4
-#define CONFIG_SYS_HZ		1000
 
 /* PCI Controller */
 #if defined(CONFIG_CMD_PCI)
diff --git a/include/configs/redwood.h b/include/configs/redwood.h
index c8bd02e710..622b7c79e6 100644
--- a/include/configs/redwood.h
+++ b/include/configs/redwood.h
@@ -12,7 +12,6 @@
 /*-----------------------------------------------------------------------
  * High Level Configuration Options
  *----------------------------------------------------------------------*/
-#define CONFIG_4xx			1	/* ... PPC4xx family	*/
 #define CONFIG_440			1	/* ... PPC460 family	*/
 #define CONFIG_460SX			1	/* ... PPC460 family	*/
 #define CONFIG_BOARD_EARLY_INIT_F	1	/* Call board_pre_init	*/
@@ -121,7 +120,6 @@
 	CONFIG_AMCC_DEF_ENV						\
 	CONFIG_AMCC_DEF_ENV_POWERPC					\
 	CONFIG_AMCC_DEF_ENV_NOR_UPD					\
-	CONFIG_AMCC_DEF_ENV_NAND_UPD					\
 	"kernel_addr=fc000000\0"					\
 	"fdt_addr=fc1e0000\0"						\
 	"ramdisk_addr=fc200000\0"					\
diff --git a/include/configs/rpi_b.h b/include/configs/rpi_b.h
index 216c6cb70b..ed8b4dfb51 100644
--- a/include/configs/rpi_b.h
+++ b/include/configs/rpi_b.h
@@ -17,7 +17,7 @@
 #ifndef __CONFIG_H
 #define __CONFIG_H
 
-#include <asm/sizes.h>
+#include <linux/sizes.h>
 
 /* Architecture, CPU, etc.*/
 #define CONFIG_ARM1176
@@ -30,9 +30,6 @@
  */
 #define CONFIG_MACH_TYPE		MACH_TYPE_BCM2708
 
-/* Timer */
-#define CONFIG_SYS_HZ			1000
-
 /* Memory layout */
 #define CONFIG_NR_DRAM_BANKS		1
 #define CONFIG_SYS_SDRAM_BASE		0x00000000
@@ -98,12 +95,25 @@
 #define CONFIG_SYS_LOAD_ADDR		0x1000000
 #define CONFIG_CONSOLE_MUX
 #define CONFIG_SYS_CONSOLE_IS_IN_ENV
+#define CONFIG_PREBOOT \
+	"if load mmc 0:1 ${loadaddr} /uEnv.txt; then " \
+		"env import -t ${loadaddr} ${filesize}; " \
+	"fi"
+
+#define ENV_DEVICE_SETTINGS \
+	"stdin=serial,lcd\0" \
+	"stdout=serial,lcd\0" \
+	"stderr=serial,lcd\0"
+
 /*
  * Memory layout for where various images get loaded by boot scripts:
  *
  * scriptaddr can be pretty much anywhere that doesn't conflict with something
  *   else. Put it low in memory to avoid conflicts.
  *
+ * pxefile_addr_r can be pretty much anywhere that doesn't conflict with
+ *   something else. Put it low in memory to avoid conflicts.
+ *
  * kernel_addr_r must be within the first 128M of RAM in order for the
  *   kernel's CONFIG_AUTO_ZRELADDR option to work. Since the kernel will
  *   decompress itself to 0x8000 after the start of RAM, kernel_addr_r
@@ -119,67 +129,112 @@
  * ramdisk_addr_r simply shouldn't overlap anything else. Choosing 33M allows
  *   for the FDT/DTB to be up to 1M, which is hopefully plenty.
  */
-#define CONFIG_EXTRA_ENV_SETTINGS \
-	"stdin=serial\0" \
-	"stderr=serial,lcd\0" \
-	"stdout=serial,lcd\0" \
+#define ENV_MEM_LAYOUT_SETTINGS \
 	"scriptaddr=0x00000000\0" \
+	"pxefile_addr_r=0x00100000\0" \
 	"kernel_addr_r=0x01000000\0" \
 	"fdt_addr_r=0x02000000\0" \
+	"fdtfile=bcm2835-rpi-b.dtb\0" \
 	"ramdisk_addr_r=0x02100000\0" \
-	"boot_targets=mmc0\0" \
-	\
-	"script_boot=" \
-		"if fatload ${devtype} ${devnum}:1 " \
-					"${scriptaddr} boot.scr.uimg; then " \
-			"source ${scriptaddr}; " \
-		"fi;\0" \
-	\
+
+#define BOOTCMDS_MMC \
 	"mmc_boot=" \
 		"setenv devtype mmc; " \
 		"if mmc dev ${devnum}; then " \
-			"run script_boot; " \
+			"run scan_boot; " \
 		"fi\0" \
+	"bootcmd_mmc0=setenv devnum 0; run mmc_boot;\0"
+#define BOOT_TARGETS_MMC "mmc0"
+
+#define BOOTCMDS_COMMON \
+	"rootpart=1\0" \
+	\
+	"do_script_boot="                                                 \
+		"load ${devtype} ${devnum}:${rootpart} "                  \
+			"${scriptaddr} ${prefix}${script}; "              \
+		"source ${scriptaddr}\0"                                  \
+	\
+	"script_boot="                                                    \
+		"for script in ${boot_scripts}; do "                      \
+			"if test -e ${devtype} ${devnum}:${rootpart} "    \
+					"${prefix}${script}; then "       \
+				"echo Found ${prefix}${script}; "         \
+				"run do_script_boot; "                    \
+				"echo SCRIPT FAILED: continuing...; "     \
+			"fi; "                                            \
+		"done\0"                                                  \
+	\
+	"do_sysboot_boot="                                                \
+		"sysboot ${devtype} ${devnum}:${rootpart} any "           \
+			"${scriptaddr} ${prefix}extlinux/extlinux.conf\0" \
+	\
+	"sysboot_boot="                                                   \
+		"if test -e ${devtype} ${devnum}:${rootpart} "            \
+				"${prefix}extlinux/extlinux.conf; then "  \
+			"echo Found ${prefix}extlinux/extlinux.conf; "    \
+			"run do_sysboot_boot; "                           \
+			"echo SCRIPT FAILED: continuing...; "             \
+		"fi\0"                                                    \
+	\
+	"scan_boot="                                                      \
+		"echo Scanning ${devtype} ${devnum}...; "                 \
+		"for prefix in ${boot_prefixes}; do "                     \
+			"run sysboot_boot; "                              \
+			"run script_boot; "                               \
+		"done\0"                                                  \
+	\
+	"boot_targets=" \
+		BOOT_TARGETS_MMC " " \
+		"\0" \
+	\
+	"boot_prefixes=/\0" \
+	\
+	"boot_scripts=boot.scr.uimg\0" \
 	\
-	"bootcmd_mmc0=setenv devnum 0; run mmc_boot\0" \
+	BOOTCMDS_MMC
 
 #define CONFIG_BOOTCOMMAND \
 	"for target in ${boot_targets}; do run bootcmd_${target}; done"
 
-#define CONFIG_BOOTDELAY		2
+#define CONFIG_BOOTCOMMAND \
+	"for target in ${boot_targets}; do run bootcmd_${target}; done"
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	ENV_DEVICE_SETTINGS \
+	ENV_MEM_LAYOUT_SETTINGS \
+	BOOTCMDS_COMMON
+
+#define CONFIG_BOOTDELAY 2
 
 /* Shell */
-#define CONFIG_SYS_HUSH_PARSER
 #define CONFIG_SYS_MAXARGS		8
 #define CONFIG_SYS_PROMPT		"U-Boot> "
-#define CONFIG_SYS_LONGHELP
-#define CONFIG_CMDLINE_EDITING
 #define CONFIG_COMMAND_HISTORY
-#define CONFIG_AUTO_COMPLETE
 
 /* Commands */
 #include <config_cmd_default.h>
-#define CONFIG_CMD_BOOTZ
 #define CONFIG_CMD_GPIO
 #define CONFIG_CMD_MMC
-#define CONFIG_DOS_PARTITION
 #define CONFIG_PARTITION_UUIDS
 #define CONFIG_CMD_PART
-#define CONFIG_CMD_FS_GENERIC
-#define CONFIG_CMD_FAT
-#define CONFIG_CMD_EXT
-/* Some things don't make sense on this HW or yet */
-#undef CONFIG_CMD_FPGA
-#undef CONFIG_CMD_NET
-#undef CONFIG_CMD_NFS
-#undef CONFIG_CMD_SAVEENV
 
-/* Device tree support for bootm/bootz */
-#define CONFIG_OF_LIBFDT
+/* Device tree support */
 #define CONFIG_OF_BOARD_SETUP
 /* ATAGs support for bootm/bootz */
 #define CONFIG_SETUP_MEMORY_TAGS
 #define CONFIG_CMDLINE_TAG
 #define CONFIG_INITRD_TAG
 
+#include <config_distro_defaults.h>
+
+/* Some things don't make sense on this HW or yet */
+#undef CONFIG_CMD_FPGA
+#undef CONFIG_CMD_NET
+#undef CONFIG_CMD_NFS
+#undef CONFIG_CMD_SAVEENV
+#undef CONFIG_CMD_DHCP
+#undef CONFIG_CMD_MII
+#undef CONFIG_CMD_NET
+#undef CONFIG_CMD_PING
+
 #endif
diff --git a/include/configs/rsdproto.h b/include/configs/rsdproto.h
index 2743c9afe0..06211380d4 100644
--- a/include/configs/rsdproto.h
+++ b/include/configs/rsdproto.h
@@ -19,7 +19,6 @@
  * (easy to change)
  */
 
-#define CONFIG_MPC8260		1	/* This is an MPC8260 CPU	*/
 #define CONFIG_RSD_PROTO	1	/* on a R&S Protocol Board      */
 #define CONFIG_CPM2		1	/* Has a CPM2 */
 
@@ -121,14 +120,12 @@
 
 #if defined(CONFIG_CMD_KGDB)
 #define CONFIG_KGDB_BAUDRATE	230400		/* speed to run kgdb serial port */
-#define CONFIG_KGDB_SER_INDEX	2		/* which serial port to use */
 #endif
 
 /*
  * Miscellaneous configurable options
  */
 #define	CONFIG_SYS_LONGHELP				/* undef to save memory		*/
-#define	CONFIG_SYS_PROMPT		"=> "		/* Monitor Command Prompt	*/
 #if defined(CONFIG_CMD_KGDB)
 #define	CONFIG_SYS_CBSIZE		1024		/* Console I/O Buffer Size	*/
 #else
@@ -143,8 +140,6 @@
 
 #define	CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address	*/
 
-#define	CONFIG_SYS_HZ			1000		/* decrementer freq: 1 ms ticks	*/
-
 /*
  * Low Level Configuration Settings
  * (address mappings, register initial values, etc.)
diff --git a/include/configs/rsk7203.h b/include/configs/rsk7203.h
index d7473c3e62..5436324580 100644
--- a/include/configs/rsk7203.h
+++ b/include/configs/rsk7203.h
@@ -11,8 +11,6 @@
 #define __RSK7203_H
 
 #undef DEBUG
-#define CONFIG_SH		1
-#define CONFIG_SH2		1
 #define CONFIG_SH2A		1
 #define CONFIG_CPU_SH7203	1
 #define CONFIG_RSK7203	1
@@ -40,7 +38,6 @@
 
 #define CONFIG_SYS_TEXT_BASE	0x0C7C0000
 #define CONFIG_SYS_LONGHELP		/* undef to save memory	*/
-#define CONFIG_SYS_PROMPT	"=> "	/* Monitor Command Prompt */
 #define CONFIG_SYS_CBSIZE	256	/* Buffer size for input from the Console */
 #define CONFIG_SYS_PBSIZE	256	/* Buffer size for Console output */
 #define CONFIG_SYS_MAXARGS	16	/* max args accepted for monitor commands */
@@ -85,8 +82,10 @@
 
 /* Board Clock */
 #define CONFIG_SYS_CLK_FREQ	33333333
+#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
+#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
 #define CMT_CLK_DIVIDER	32	/* 8 (default), 32, 128 or 512 */
-#define CONFIG_SYS_HZ			(CONFIG_SYS_CLK_FREQ / CMT_CLK_DIVIDER)
+#define CONFIG_SH_CMT_CLK_FREQ (CONFIG_SYS_CLK_FREQ / CMT_CLK_DIVIDER)
 
 /* Network interface */
 #define CONFIG_SMC911X
diff --git a/include/configs/rsk7264.h b/include/configs/rsk7264.h
index 783467af5e..4aaa3ef74b 100644
--- a/include/configs/rsk7264.h
+++ b/include/configs/rsk7264.h
@@ -12,8 +12,6 @@
 #define __RSK7264_H
 
 #undef DEBUG
-#define CONFIG_SH		1
-#define CONFIG_SH2		1
 #define CONFIG_SH2A		1
 #define CONFIG_CPU_SH7264	1
 #define CONFIG_RSK7264		1
@@ -28,7 +26,6 @@
 #define CONFIG_SYS_BAUDRATE_TABLE	{ CONFIG_BAUDRATE }
 
 #define CONFIG_SYS_LONGHELP	1	/* undef to save memory	*/
-#define CONFIG_SYS_PROMPT	"=> "	/* Monitor Command Prompt */
 #define CONFIG_SYS_CBSIZE	256	/* Buffer size for input from the Console */
 #define CONFIG_SYS_PBSIZE	256	/* Buffer size for Console output */
 #define CONFIG_SYS_MAXARGS	16	/* max args accepted for monitor commands */
@@ -65,8 +62,10 @@
 
 /* Board Clock */
 #define CONFIG_SYS_CLK_FREQ	36000000
+#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
+#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
 #define CMT_CLK_DIVIDER		32	/* 8 (default), 32, 128 or 512 */
-#define CONFIG_SYS_HZ		(CONFIG_SYS_CLK_FREQ / CMT_CLK_DIVIDER)
+#define CONFIG_SH_CMT_CLK_FREQ (CONFIG_SYS_CLK_FREQ / CMT_CLK_DIVIDER)
 
 /* Network interface */
 #define CONFIG_SMC911X
diff --git a/include/configs/rsk7269.h b/include/configs/rsk7269.h
index 11c2a93c1a..11fc231fa6 100644
--- a/include/configs/rsk7269.h
+++ b/include/configs/rsk7269.h
@@ -11,8 +11,6 @@
 #define __RSK7269_H
 
 #undef DEBUG
-#define CONFIG_SH		1
-#define CONFIG_SH2		1
 #define CONFIG_SH2A		1
 #define CONFIG_CPU_SH7269	1
 #define CONFIG_RSK7269		1
@@ -27,7 +25,6 @@
 #define CONFIG_SYS_BAUDRATE_TABLE	{ CONFIG_BAUDRATE }
 
 #define CONFIG_SYS_LONGHELP		/* undef to save memory	*/
-#define CONFIG_SYS_PROMPT	"=> "	/* Monitor Command Prompt */
 #define CONFIG_SYS_CBSIZE	256	/* Boot Argument Buffer Size */
 #define CONFIG_SYS_PBSIZE	256	/* Print Buffer Size */
 #define CONFIG_SYS_MAXARGS	16	/* max number of command args */
@@ -64,8 +61,10 @@
 
 /* Board Clock */
 #define CONFIG_SYS_CLK_FREQ	66125000
+#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
+#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
 #define CMT_CLK_DIVIDER		32	/* 8 (default), 32, 128 or 512 */
-#define CONFIG_SYS_HZ		(CONFIG_SYS_CLK_FREQ / CMT_CLK_DIVIDER)
+#define CONFIG_SH_CMT_CLK_FREQ (CONFIG_SYS_CLK_FREQ / CMT_CLK_DIVIDER)
 
 /* Network interface */
 #define CONFIG_SMC911X
diff --git a/include/configs/rut.h b/include/configs/rut.h
index 7c94644de8..6bddededae 100644
--- a/include/configs/rut.h
+++ b/include/configs/rut.h
@@ -41,7 +41,6 @@
 #undef CONFIG_SPL_NET_VCI_STRING
 #undef CONFIG_SPL_ETH_SUPPORT
 
-#define CONFIG_PHY_ADDR			1
 #define CONFIG_PHY_NATSEMI
 
 #define CONFIG_FACTORYSET
@@ -65,7 +64,8 @@
 /* Default env settings */
 #define CONFIG_EXTRA_ENV_SETTINGS \
 	"hostname=rut\0" \
-	"splashpos=488,352\0" \
+	"nand_img_size=0x500000\0" \
+	"splashpos=m,m\0" \
 	"optargs=fixrtc --no-log consoleblank=0 \0" \
 	CONFIG_COMMON_ENV_SETTINGS \
 	"mmc_dev=0\0" \
@@ -111,9 +111,7 @@
 		"fi;" \
 	"fi;" \
 	"run nand_boot;" \
-	"if ping ${serverip}; then " \
-		"run net_nfs; " \
-	"fi; "
+	"reset;"
 
 #else
 #define CONFIG_BOOTDELAY		0
@@ -151,6 +149,9 @@
 #define BOARD_LCD_RESET		115	/* Bank 3 pin 19 */
 #define CONFIG_ARCH_EARLY_INIT_R
 #define CONFIG_FORMIKE
+#define DISPL_PLL_SPREAD_SPECTRUM
+#define CONFIG_SYS_CONSOLE_BG_COL	0xff
+#define CONFIG_SYS_CONSOLE_FG_COL	0x00
 #endif
 
 #endif	/* ! __CONFIG_RUT_H */
diff --git a/include/configs/s5p_goni.h b/include/configs/s5p_goni.h
index c303244f98..991c43e1cc 100644
--- a/include/configs/s5p_goni.h
+++ b/include/configs/s5p_goni.h
@@ -34,6 +34,7 @@
 
 #define CONFIG_SETUP_MEMORY_TAGS
 #define CONFIG_CMDLINE_TAG
+#define CONFIG_REVISION_TAG
 #define CONFIG_INITRD_TAG
 #define CONFIG_CMDLINE_EDITING
 
@@ -113,8 +114,13 @@
 
 #define CONFIG_UBIFS_OPTION	"rootflags=bulk_read,no_chk_data_crc"
 
+#define CONFIG_MISC_COMMON
+#define CONFIG_MISC_INIT_R
+
 #define CONFIG_ENV_OVERWRITE
 #define CONFIG_SYS_CONSOLE_IS_IN_ENV
+#define CONFIG_ENV_VARS_UBOOT_CONFIG
+#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
 #define CONFIG_EXTRA_ENV_SETTINGS					\
 	CONFIG_UPDATEB \
 	"updatek=" \
@@ -173,8 +179,6 @@
 #define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_SDRAM_BASE + 0x5000000)
 #define CONFIG_SYS_LOAD_ADDR		(CONFIG_SYS_SDRAM_BASE + 0x4000000)
 
-#define CONFIG_SYS_HZ			1000
-
 /* Goni has 3 banks of DRAM, but swap the bank */
 #define CONFIG_NR_DRAM_BANKS	3
 #define PHYS_SDRAM_1		CONFIG_SYS_SDRAM_BASE	/* OneDRAM Bank #0 */
@@ -210,8 +214,8 @@
 /*
  * I2C Settings
  */
-#define CONFIG_SOFT_I2C_GPIO_SCL s5pc110_gpio_get_nr(j4, 3)
-#define CONFIG_SOFT_I2C_GPIO_SDA s5pc110_gpio_get_nr(j4, 0)
+#define CONFIG_SOFT_I2C_GPIO_SCL s5pc110_gpio_get(j4, 3)
+#define CONFIG_SOFT_I2C_GPIO_SDA s5pc110_gpio_get(j4, 0)
 
 #define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_SOFT		/* I2C bit-banged */
diff --git a/include/configs/s5pc210_universal.h b/include/configs/s5pc210_universal.h
index 97a4008e36..2da887109d 100644
--- a/include/configs/s5pc210_universal.h
+++ b/include/configs/s5pc210_universal.h
@@ -7,78 +7,56 @@
  * SPDX-License-Identifier:	GPL-2.0+
  */
 
-#ifndef __CONFIG_H
-#define __CONFIG_H
+#ifndef __CONFIG_UNIVERSAL_H
+#define __CONFIG_UNIVERSAL_H
 
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-#define CONFIG_SAMSUNG		1	/* in a SAMSUNG core */
-#define CONFIG_S5P		1	/* which is in a S5P Family */
-#define CONFIG_EXYNOS4210	1	/* which is in a EXYNOS4210 */
-#define CONFIG_UNIVERSAL	1	/* working with Universal */
-#define CONFIG_TIZEN		1	/* TIZEN lib */
+#include <configs/exynos4-dt.h>
 
-#include <asm/arch/cpu.h>		/* get chip and board defs */
+#define CONFIG_SYS_PROMPT	"Universal # "	/* Monitor Command Prompt */
 
-#define CONFIG_ARCH_CPU_INIT
-#define CONFIG_DISPLAY_CPUINFO
-#define CONFIG_DISPLAY_BOARDINFO
+#undef CONFIG_DEFAULT_DEVICE_TREE
+#define CONFIG_DEFAULT_DEVICE_TREE	exynos4210-universal_c210
+
+#define CONFIG_TIZEN			/* TIZEN lib */
 
 /* Keep L2 Cache Disabled */
 #define CONFIG_SYS_L2CACHE_OFF		1
 
+/* Universal has 2 banks of DRAM */
+#define CONFIG_NR_DRAM_BANKS		2
 #define CONFIG_SYS_SDRAM_BASE		0x40000000
-#define CONFIG_SYS_TEXT_BASE		0x44800000
-
-/* input clock of PLL: Universal has 24MHz input clock at EXYNOS4210 */
-#define CONFIG_SYS_CLK_FREQ_C210	24000000
-#define CONFIG_SYS_CLK_FREQ		CONFIG_SYS_CLK_FREQ_C210
+#define PHYS_SDRAM_1			CONFIG_SYS_SDRAM_BASE
 
-#define CONFIG_SETUP_MEMORY_TAGS
-#define CONFIG_CMDLINE_TAG
-#define CONFIG_INITRD_TAG
-#define CONFIG_REVISION_TAG
-#define CONFIG_CMDLINE_EDITING
-#define CONFIG_SKIP_LOWLEVEL_INIT
-#define CONFIG_BOARD_EARLY_INIT_F
+#define SDRAM_BANK_SIZE			(256 << 20)	/* 256 MB */
 
 /* Size of malloc() pool */
-#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + (1 << 20))
+#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + (80 * SZ_1M))
 
 /* select serial console configuration */
-#define CONFIG_SERIAL2		1	/* use SERIAL 2 */
-#define CONFIG_BAUDRATE		115200
-
-/* MMC */
-#define CONFIG_GENERIC_MMC
-#define CONFIG_MMC
-#define CONFIG_SDHCI
-#define CONFIG_S5P_SDHCI
-
-/* PWM */
-#define CONFIG_PWM			1
-
-/* It should define before config_cmd_default.h */
-#define CONFIG_SYS_NO_FLASH		1
-
-/* Command definition */
-#include <config_cmd_default.h>
-
-#undef CONFIG_CMD_FPGA
-#undef CONFIG_CMD_MISC
-#undef CONFIG_CMD_NET
-#undef CONFIG_CMD_NFS
-#undef CONFIG_CMD_XIMG
-#define CONFIG_CMD_CACHE
-#define CONFIG_CMD_ONENAND
-#define CONFIG_CMD_MTDPARTS
-#define CONFIG_CMD_MMC
-#define CONFIG_CMD_FAT
-
-#define CONFIG_BOOTDELAY		1
-#define CONFIG_ZERO_BOOTDELAY_CHECK
+#define CONFIG_SERIAL2
+#define CONFIG_BAUDRATE			115200
+
+/* Console configuration */
+#define CONFIG_SYS_CONSOLE_INFO_QUIET
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV
+
+#define CONFIG_BOOTARGS			"Please use defined boot"
+#define CONFIG_BOOTCOMMAND		"run mmcboot"
+#define CONFIG_DEFAULT_CONSOLE		"console=ttySAC1,115200n8\0"
+
+#define CONFIG_SYS_INIT_SP_ADDR	(CONFIG_SYS_LOAD_ADDR \
+					- GENERATED_GBL_DATA_SIZE)
+
+#define CONFIG_SYS_MEM_TOP_HIDE	(1 << 20)	/* ram console */
+
+#define CONFIG_SYS_MONITOR_BASE	0x00000000
+
+/* memtest works on */
+#define CONFIG_SYS_MEMTEST_START	CONFIG_SYS_SDRAM_BASE
+#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_SDRAM_BASE + 0x5000000)
+#define CONFIG_SYS_LOAD_ADDR		(CONFIG_SYS_SDRAM_BASE + 0x4800000)
+
+#define CONFIG_SYS_TEXT_BASE		0x44800000
 
 #define CONFIG_MTD_DEVICE
 #define CONFIG_MTD_PARTITIONS
@@ -106,23 +84,23 @@
 				",100M(swap)"\
 				",-(UMS)\0"
 
-#define CONFIG_BOOTARGS		"Please use defined boot"
-#define CONFIG_BOOTCOMMAND	"run mmcboot"
-#define CONFIG_DEFAULT_CONSOLE	"console=ttySAC2,115200n8\0"
-
 #define CONFIG_ENV_UBI_MTD	" ubi.mtd=${ubiblock} ubi.mtd=4 ubi.mtd=7"
 #define CONFIG_BOOTBLOCK	"10"
 #define CONFIG_UBIBLOCK		"9"
 
+#define CONFIG_ENV_IS_IN_MMC
+#define CONFIG_SYS_MMC_ENV_DEV		CONFIG_MMC_DEFAULT_DEV
+#define CONFIG_ENV_SIZE			4096
+#define CONFIG_ENV_OFFSET		((32 - 4) << 10) /* 32KiB - 4KiB */
+
 #define CONFIG_ENV_UBIFS_OPTION	" rootflags=bulk_read,no_chk_data_crc "
 #define CONFIG_ENV_FLASHBOOT	CONFIG_ENV_UBI_MTD CONFIG_ENV_UBIFS_OPTION \
 				"${mtdparts}"
 
 #define CONFIG_ENV_COMMON_BOOT	"${console} ${meminfo}"
 
-#define CONFIG_ENV_OVERWRITE
-#define CONFIG_SYS_CONSOLE_INFO_QUIET
-#define CONFIG_SYS_CONSOLE_IS_IN_ENV
+#define CONFIG_ENV_VARS_UBOOT_CONFIG
+#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
 
 #define CONFIG_EXTRA_ENV_SETTINGS					\
 	"updateb=" \
@@ -184,55 +162,18 @@
 	"mmcrootpart=3\0" \
 	"opts=always_resume=1"
 
-/* Miscellaneous configurable options */
-#define CONFIG_SYS_LONGHELP		/* undef to save memory */
-#define CONFIG_SYS_HUSH_PARSER		/* use "hush" command parser	*/
-#define CONFIG_SYS_PROMPT	"Universal # "
-#define CONFIG_SYS_CBSIZE	256	/* Console I/O Buffer Size */
-#define CONFIG_SYS_PBSIZE	384	/* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS	16	/* max number of command args */
-/* Boot Argument Buffer Size */
-#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE
-/* memtest works on */
-#define CONFIG_SYS_MEMTEST_START	CONFIG_SYS_SDRAM_BASE
-#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_SDRAM_BASE + 0x5000000)
-#define CONFIG_SYS_LOAD_ADDR		(CONFIG_SYS_SDRAM_BASE + 0x4800000)
-
-#define CONFIG_SYS_HZ			1000
-
-/* Universal has 2 banks of DRAM */
-#define CONFIG_NR_DRAM_BANKS	2
-#define PHYS_SDRAM_1		CONFIG_SYS_SDRAM_BASE	/* LDDDR2 DMC 0 */
-#define PHYS_SDRAM_1_SIZE	(256 << 20)		/* 256 MB in CS 0 */
-#define PHYS_SDRAM_2		0x50000000		/* LPDDR2 DMC 1 */
-#define PHYS_SDRAM_2_SIZE	(256 << 20)		/* 256 MB in CS 0 */
-
-#define CONFIG_SYS_MEM_TOP_HIDE		(1 << 20)	/* ram console */
-
-#define CONFIG_SYS_MONITOR_BASE		0x00000000
-#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 2 sectors */
-
 #define CONFIG_USE_ONENAND_BOARD_INIT
 #define CONFIG_SAMSUNG_ONENAND
 #define CONFIG_SYS_ONENAND_BASE		0x0C000000
 
-#define CONFIG_ENV_IS_IN_MMC		1
-#define CONFIG_SYS_MMC_ENV_DEV		0
-#define CONFIG_ENV_SIZE			4096
-#define CONFIG_ENV_OFFSET		((32 - 4) << 10)/* 32KiB - 4KiB */
-
-#define CONFIG_DOS_PARTITION		1
-
-#define CONFIG_SYS_INIT_SP_ADDR	(CONFIG_SYS_LOAD_ADDR - GENERATED_GBL_DATA_SIZE)
-
-#define CONFIG_SYS_CACHELINE_SIZE       32
-
 #include <asm/arch/gpio.h>
 /*
  * I2C Settings
  */
-#define CONFIG_SOFT_I2C_GPIO_SCL exynos4_gpio_part1_get_nr(b, 7)
-#define CONFIG_SOFT_I2C_GPIO_SDA exynos4_gpio_part1_get_nr(b, 6)
+#define CONFIG_SOFT_I2C_GPIO_SCL exynos4_gpio_get(1, b, 7)
+#define CONFIG_SOFT_I2C_GPIO_SDA exynos4_gpio_get(1, b, 6)
+
+#define CONFIG_CMD_I2C
 
 #define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_SOFT		/* I2C bit-banged */
@@ -255,10 +196,10 @@
  */
 #define CONFIG_SOFT_SPI
 #define CONFIG_SOFT_SPI_MODE SPI_MODE_3
-#define CONFIG_SOFT_SPI_GPIO_SCLK exynos4_gpio_part2_get_nr(y3, 1)
-#define CONFIG_SOFT_SPI_GPIO_MOSI exynos4_gpio_part2_get_nr(y3, 3)
-#define CONFIG_SOFT_SPI_GPIO_MISO exynos4_gpio_part2_get_nr(y3, 0)
-#define CONFIG_SOFT_SPI_GPIO_CS exynos4_gpio_part2_get_nr(y4, 3)
+#define CONFIG_SOFT_SPI_GPIO_SCLK exynos4_gpio_get(2, y3, 1)
+#define CONFIG_SOFT_SPI_GPIO_MOSI exynos4_gpio_get(2, y3, 3)
+#define CONFIG_SOFT_SPI_GPIO_MISO exynos4_gpio_get(2, y3, 0)
+#define CONFIG_SOFT_SPI_GPIO_CS exynos4_gpio_get(2, y4, 3)
 
 #define SPI_DELAY udelay(1)
 #undef SPI_INIT
@@ -271,16 +212,45 @@ void universal_spi_sda(int bit);
 int universal_spi_read(void);
 #endif
 
+/* Common misc for Samsung */
+#define CONFIG_MISC_COMMON
+
+#define CONFIG_MISC_INIT_R
+
+/* Download menu - Samsung common */
+#define CONFIG_LCD_MENU
+#define CONFIG_LCD_MENU_BOARD
+
+/* Download menu - definitions for check keys */
+#ifndef __ASSEMBLY__
+#include <power/max8998_pmic.h>
+
+#define KEY_PWR_PMIC_NAME		"MAX8998_PMIC"
+#define KEY_PWR_STATUS_REG		MAX8998_REG_STATUS1
+#define KEY_PWR_STATUS_MASK		(1 << 7)
+#define KEY_PWR_INTERRUPT_REG		MAX8998_REG_IRQ1
+#define KEY_PWR_INTERRUPT_MASK		(1 << 7)
+
+#define KEY_VOL_UP_GPIO			exynos4_gpio_get(2, x2, 0)
+#define KEY_VOL_DOWN_GPIO		exynos4_gpio_get(2, x2, 1)
+#endif /* __ASSEMBLY__ */
+
+/* LCD console */
+#define LCD_BPP			LCD_COLOR16
+#define CONFIG_SYS_WHITE_ON_BLACK
+
 /*
  * LCD Settings
  */
 #define CONFIG_EXYNOS_FB
 #define CONFIG_LCD
 #define CONFIG_CMD_BMP
-#define CONFIG_BMP_32BPP
+#define CONFIG_BMP_16BPP
 #define CONFIG_LD9040
-#define CONFIG_EXYNOS_MIPI_DSIM
 #define CONFIG_VIDEO_BMP_GZIP
-#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE ((520 * 120 * 4) + (1 << 12))
+#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE ((500 * 160 * 4) + 54)
+
+#define LCD_XRES	480
+#define LCD_YRES	800
 
 #endif	/* __CONFIG_H */
diff --git a/include/configs/sacsng.h b/include/configs/sacsng.h
index 033c1f30de..b5064ab37c 100644
--- a/include/configs/sacsng.h
+++ b/include/configs/sacsng.h
@@ -457,6 +457,7 @@
 #endif /* CONFIG_BOOT_ROOT_NFS */
 
 #define CONFIG_BOOTP_RANDOM_DELAY       /* Randomize the BOOTP retry delay */
+#define CONFIG_LIB_RAND
 
 /*
  * BOOTP options
@@ -475,7 +476,6 @@
 #define CONFIG_SYS_LONGHELP
 
 /* Monitor Command Prompt */
-#define CONFIG_SYS_PROMPT		"=> "
 
 #undef  CONFIG_SYS_HUSH_PARSER
 #ifdef  CONFIG_SYS_HUSH_PARSER
@@ -525,7 +525,6 @@
  *
  *****************************************************************************/
 
-#define CONFIG_MPC8260		1	/* This is an MPC8260 CPU   */
 #define CONFIG_SACSng		1	/* munged for the SACSng */
 #define CONFIG_CPM2		1	/* Has a CPM2 */
 
@@ -584,7 +583,6 @@
 #define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size	   */
 
 #define CONFIG_SYS_LOAD_ADDR		0x400000   /* default load address */
-#define CONFIG_SYS_HZ			1000	/* decrementer freq: 1 ms ticks */
 
 #define CONFIG_SYS_ALT_MEMTEST                 /* Select full-featured memory test */
 #define CONFIG_SYS_MEMTEST_START	0x2000	/* memtest works from the end of */
diff --git a/include/configs/sama5d3_xplained.h b/include/configs/sama5d3_xplained.h
new file mode 100644
index 0000000000..91cc7d8e58
--- /dev/null
+++ b/include/configs/sama5d3_xplained.h
@@ -0,0 +1,203 @@
+/*
+ * Configuration settings for the SAMA5D3 Xplained board.
+ *
+ * Copyright (C) 2014 Atmel Corporation
+ *		      Bo Shen <voice.shen@atmel.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <asm/hardware.h>
+
+#define CONFIG_SYS_TEXT_BASE		0x26f00000
+
+/* ARM asynchronous clock */
+#define CONFIG_SYS_AT91_SLOW_CLOCK      32768
+#define CONFIG_SYS_AT91_MAIN_CLOCK      12000000 /* from 12 MHz crystal */
+#define CONFIG_SYS_HZ		        1000
+
+#define CONFIG_AT91FAMILY
+#define CONFIG_ARCH_CPU_INIT
+#define CONFIG_SKIP_LOWLEVEL_INIT
+#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_DISPLAY_CPUINFO
+
+#define CONFIG_CMD_BOOTZ
+#define CONFIG_OF_LIBFDT		/* Device Tree support */
+
+/* general purpose I/O */
+#define CONFIG_AT91_GPIO
+
+/* serial console */
+#define CONFIG_ATMEL_USART
+#define CONFIG_USART_BASE		ATMEL_BASE_DBGU
+#define CONFIG_USART_ID			ATMEL_ID_DBGU
+
+/*
+ * This needs to be defined for the OHCI code to work but it is defined as
+ * ATMEL_ID_UHPHS in the CPU specific header files.
+ */
+#define ATMEL_ID_UHP			ATMEL_ID_UHPHS
+
+/*
+ * Specify the clock enable bit in the PMC_SCER register.
+ */
+#define ATMEL_PMC_UHP			AT91SAM926x_PMC_UHP
+
+#define CONFIG_BOOTDELAY		3
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+/* No NOR flash */
+#define CONFIG_SYS_NO_FLASH
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+#undef CONFIG_CMD_FPGA
+#undef CONFIG_CMD_IMI
+#undef CONFIG_CMD_LOADS
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_DHCP
+
+/* SDRAM */
+#define CONFIG_NR_DRAM_BANKS		1
+#define CONFIG_SYS_SDRAM_BASE           ATMEL_BASE_DDRCS
+#define CONFIG_SYS_SDRAM_SIZE		0x10000000
+
+#define CONFIG_SYS_INIT_SP_ADDR \
+	(CONFIG_SYS_SDRAM_BASE + 4 * 1024 - GENERATED_GBL_DATA_SIZE)
+
+/* NAND flash */
+#define CONFIG_CMD_NAND
+
+#ifdef CONFIG_CMD_NAND
+#define CONFIG_NAND_ATMEL
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+#define CONFIG_SYS_NAND_BASE		ATMEL_BASE_CS3
+/* our ALE is AD21 */
+#define CONFIG_SYS_NAND_MASK_ALE	(1 << 21)
+/* our CLE is AD22 */
+#define CONFIG_SYS_NAND_MASK_CLE	(1 << 22)
+#define CONFIG_SYS_NAND_ONFI_DETECTION
+/* PMECC & PMERRLOC */
+#define CONFIG_ATMEL_NAND_HWECC
+#define CONFIG_ATMEL_NAND_HW_PMECC
+#define CONFIG_PMECC_CAP		4
+#define CONFIG_PMECC_SECTOR_SIZE	512
+#define CONFIG_CMD_NAND_TRIMFFS
+#define CONFIG_CMD_MTDPARTS
+
+#define CONFIG_MTD_DEVICE
+#define CONFIG_MTD_PARTITIONS
+#define CONFIG_RBTREE
+#define CONFIG_LZO
+#define CONFIG_CMD_UBI
+#define CONFIG_CMD_UBIFS
+#endif
+
+/* Ethernet Hardware */
+#define CONFIG_MACB
+#define CONFIG_RMII
+#define CONFIG_NET_MULTI
+#define CONFIG_NET_RETRY_COUNT		20
+#define CONFIG_MACB_SEARCH_PHY
+#define CONFIG_RGMII
+#define CONFIG_CMD_MII
+#define CONFIG_PHYLIB
+
+/* MMC */
+#define CONFIG_CMD_MMC
+
+#ifdef CONFIG_CMD_MMC
+#define CONFIG_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_GENERIC_ATMEL_MCI
+#define CONFIG_ATMEL_MCI_8BIT
+#endif
+
+/* USB */
+#define CONFIG_CMD_USB
+
+#ifdef CONFIG_CMD_USB
+#define CONFIG_USB_ATMEL
+#define CONFIG_USB_ATMEL_CLK_SEL_UPLL
+#define CONFIG_USB_OHCI_NEW
+#define CONFIG_SYS_USB_OHCI_CPU_INIT
+#define CONFIG_SYS_USB_OHCI_REGS_BASE		ATMEL_BASE_OHCI
+#define CONFIG_SYS_USB_OHCI_SLOT_NAME		"SAMA5D3 Xplained"
+#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS	2
+#define CONFIG_DOS_PARTITION
+#define CONFIG_USB_STORAGE
+#endif
+
+#if defined(CONFIG_CMD_USB) || defined(CONFIG_CMD_MMC)
+#define CONFIG_CMD_FAT
+#define CONFIG_FAT_WRITE
+#define CONFIG_CMD_EXT4
+#define CONFIG_CMD_EXT4_WRITE
+#endif
+
+#define CONFIG_SYS_LOAD_ADDR			0x22000000 /* load address */
+
+#if CONFIG_SYS_USE_NANDFLASH
+/* bootstrap + u-boot + env in nandflash */
+#define CONFIG_ENV_IS_IN_NAND
+#define CONFIG_ENV_OFFSET		0xc0000
+#define CONFIG_ENV_OFFSET_REDUND	0x100000
+#define CONFIG_ENV_SIZE			0x20000
+#define CONFIG_BOOTCOMMAND	"nand read 0x21000000 0x180000 0x80000;" \
+				"nand read 0x22000000 0x200000 0x600000;" \
+				"bootz 0x22000000 - 0x21000000"
+#elif CONFIG_SYS_USE_MMC
+/* bootstrap + u-boot + env in sd card */
+#define CONFIG_ENV_IS_IN_MMC
+#define CONFIG_ENV_OFFSET	0x2000
+#define CONFIG_ENV_SIZE		0x1000
+#define CONFIG_BOOTCOMMAND	"fatload mmc 0:1 0x21000000 at91-sama5d3_xplained.dtb; " \
+				"fatload mmc 0:1 0x22000000 zImage; " \
+				"bootz 0x22000000 - 0x21000000"
+#define CONFIG_SYS_MMC_ENV_DEV	0
+#else
+#define CONFIG_ENV_IS_NOWHERE
+#endif
+
+#ifdef CONFIG_SYS_USE_MMC
+#define CONFIG_BOOTARGS							\
+	"console=ttyS0,115200 earlyprintk "				\
+	"root=/dev/mmcblk0p2 rw rootwait"
+#else
+#define CONFIG_BOOTARGS							\
+	"console=ttyS0,115200 earlyprintk "				\
+	"mtdparts=atmel_nand:256k(bootstrap)ro,512k(uboot)ro,"		\
+	"256K(env),256k(evn_redundent),256k(spare),"			\
+	"512k(dtb),6M(kernel)ro,-(rootfs) "				\
+	"rootfstype=ubifs ubi.mtd=7 root=ubi0:rootfs"
+#endif
+
+#define CONFIG_BAUDRATE			115200
+
+#define CONFIG_SYS_PROMPT		"U-Boot> "
+#define CONFIG_SYS_CBSIZE		256
+#define CONFIG_SYS_MAXARGS		16
+#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
+					sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_CMDLINE_EDITING
+#define CONFIG_AUTO_COMPLETE
+#define CONFIG_SYS_HUSH_PARSER
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN		(4 * 1024 * 1024)
+
+#endif
diff --git a/include/configs/sama5d3xek.h b/include/configs/sama5d3xek.h
index 79c00684dd..516be85fe0 100644
--- a/include/configs/sama5d3xek.h
+++ b/include/configs/sama5d3xek.h
@@ -20,12 +20,14 @@
 /* ARM asynchronous clock */
 #define CONFIG_SYS_AT91_SLOW_CLOCK      32768
 #define CONFIG_SYS_AT91_MAIN_CLOCK      12000000 /* from 12 MHz crystal */
-#define CONFIG_SYS_HZ		        1000
 
 #define CONFIG_AT91FAMILY
 #define CONFIG_ARCH_CPU_INIT
 
+#ifndef CONFIG_SPL_BUILD
 #define CONFIG_SKIP_LOWLEVEL_INIT
+#endif
+
 #define CONFIG_BOARD_EARLY_INIT_F
 #define CONFIG_DISPLAY_CPUINFO
 
@@ -94,8 +96,12 @@
 #define CONFIG_SYS_SDRAM_BASE           ATMEL_BASE_DDRCS
 #define CONFIG_SYS_SDRAM_SIZE		0x20000000
 
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SYS_INIT_SP_ADDR		0x310000
+#else
 #define CONFIG_SYS_INIT_SP_ADDR \
 	(CONFIG_SYS_SDRAM_BASE + 4 * 1024 - GENERATED_GBL_DATA_SIZE)
+#endif
 
 /* SerialFlash */
 #define CONFIG_CMD_SF
@@ -153,6 +159,7 @@
 
 #ifdef CONFIG_CMD_USB
 #define CONFIG_USB_ATMEL
+#define CONFIG_USB_ATMEL_CLK_SEL_UPLL
 #define CONFIG_USB_OHCI_NEW
 #define CONFIG_SYS_USB_OHCI_CPU_INIT
 #define CONFIG_SYS_USB_OHCI_REGS_BASE		ATMEL_BASE_OHCI
@@ -235,4 +242,54 @@
 /* Size of malloc() pool */
 #define CONFIG_SYS_MALLOC_LEN		(1024 * 1024)
 
+/* SPL */
+#define CONFIG_SPL
+#define CONFIG_SPL_FRAMEWORK
+#define CONFIG_SPL_TEXT_BASE		0x300000
+#define CONFIG_SPL_MAX_SIZE		0x10000
+#define CONFIG_SPL_BSS_START_ADDR	0x20000000
+#define CONFIG_SPL_BSS_MAX_SIZE		0x80000
+#define CONFIG_SYS_SPL_MALLOC_START	0x20080000
+#define CONFIG_SYS_SPL_MALLOC_SIZE	0x80000
+
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+#define CONFIG_SPL_LIBGENERIC_SUPPORT
+#define CONFIG_SPL_GPIO_SUPPORT
+#define CONFIG_SPL_SERIAL_SUPPORT
+
+#define CONFIG_SPL_BOARD_INIT
+#define CONFIG_SYS_MONITOR_LEN		(512 << 10)
+
+#ifdef CONFIG_SYS_USE_MMC
+#define CONFIG_SPL_LDSCRIPT		arch/arm/cpu/at91-common/u-boot-spl.lds
+#define CONFIG_SPL_MMC_SUPPORT
+#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS	0x400
+#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x200
+#define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION	1
+#define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME	"u-boot.img"
+#define CONFIG_SPL_FAT_SUPPORT
+#define CONFIG_SPL_LIBDISK_SUPPORT
+
+#elif CONFIG_SYS_USE_NANDFLASH
+#define CONFIG_SPL_NAND_SUPPORT
+#define CONFIG_SPL_NAND_DRIVERS
+#define CONFIG_SPL_NAND_BASE
+#define CONFIG_SYS_NAND_U_BOOT_OFFS	0x40000
+#define CONFIG_SYS_NAND_5_ADDR_CYCLE
+#define CONFIG_SYS_NAND_PAGE_SIZE	0x800
+#define CONFIG_SYS_NAND_PAGE_COUNT	64
+#define CONFIG_SYS_NAND_OOBSIZE		64
+#define CONFIG_SYS_NAND_BLOCK_SIZE	0x20000
+#define CONFIG_SYS_NAND_BAD_BLOCK_POS	0x0
+
+#elif CONFIG_SYS_USE_SERIALFLASH
+#define CONFIG_SPL_SPI_SUPPORT
+#define CONFIG_SPL_SPI_FLASH_SUPPORT
+#define CONFIG_SPL_SPI_LOAD
+#define CONFIG_SPL_SPI_BUS		0
+#define CONFIG_SPL_SPI_CS		0
+#define CONFIG_SYS_SPI_U_BOOT_OFFS	0x8400
+
+#endif
+
 #endif
diff --git a/include/configs/sandbox.h b/include/configs/sandbox.h
index 4027030384..fa62cb6cd5 100644
--- a/include/configs/sandbox.h
+++ b/include/configs/sandbox.h
@@ -16,8 +16,18 @@
 
 #endif
 
+#define CONFIG_SYS_TIMER_RATE		1000000
+
 #define CONFIG_BOOTSTAGE
 #define CONFIG_BOOTSTAGE_REPORT
+#define CONFIG_DM
+#define CONFIG_CMD_DEMO
+#define CONFIG_CMD_DM
+#define CONFIG_DM_DEMO
+#define CONFIG_DM_DEMO_SIMPLE
+#define CONFIG_DM_DEMO_SHAPE
+#define CONFIG_DM_GPIO
+#define CONFIG_DM_TEST
 
 /* Number of bits in a C 'long' on this architecture */
 #define CONFIG_SANDBOX_BITS_PER_LONG	64
@@ -30,6 +40,7 @@
 #define CONFIG_FIT_SIGNATURE
 #define CONFIG_RSA
 #define CONFIG_CMD_FDT
+#define CONFIG_DEFAULT_DEVICE_TREE	sandbox
 
 #define CONFIG_FS_FAT
 #define CONFIG_FS_EXT4
@@ -37,19 +48,26 @@
 #define CONFIG_CMD_FAT
 #define CONFIG_CMD_EXT4
 #define CONFIG_CMD_EXT4_WRITE
+#define CONFIG_CMD_PART
+#define CONFIG_DOS_PARTITION
+#define CONFIG_HOST_MAX_DEVICES 4
+#define CONFIG_CMD_FS_GENERIC
 
 #define CONFIG_SYS_VSNPRINTF
 
 #define CONFIG_CMD_GPIO
 #define CONFIG_SANDBOX_GPIO
-#define CONFIG_SANDBOX_GPIO_COUNT	20
+#define CONFIG_SANDBOX_GPIO_COUNT	128
+
+#define CONFIG_CMD_GPT
+#define CONFIG_PARTITION_UUIDS
+#define CONFIG_EFI_PARTITION
 
 /*
  * Size of malloc() pool, although we don't actually use this yet.
  */
-#define CONFIG_SYS_MALLOC_LEN		(4 << 20)	/* 4MB  */
+#define CONFIG_SYS_MALLOC_LEN		(32 << 20)	/* 32MB  */
 
-#define CONFIG_SYS_PROMPT		"=>"	/* Command Prompt */
 #define CONFIG_SYS_HUSH_PARSER
 #define CONFIG_SYS_LONGHELP			/* #undef to save memory */
 #define CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size */
@@ -62,18 +80,30 @@
 #define CONFIG_CMDLINE_EDITING
 #define CONFIG_COMMAND_HISTORY
 #define CONFIG_AUTO_COMPLETE
+#define CONFIG_BOOTDELAY	3
 
 #define CONFIG_ENV_SIZE		8192
 #define CONFIG_ENV_IS_NOWHERE
 
-#define CONFIG_SYS_HZ			1000
+/* SPI */
+#define CONFIG_SANDBOX_SPI
+#define CONFIG_CMD_SF
+#define CONFIG_CMD_SF_TEST
+#define CONFIG_CMD_SPI
+#define CONFIG_SPI_FLASH
+#define CONFIG_OF_SPI
+#define CONFIG_OF_SPI_FLASH
+#define CONFIG_SPI_FLASH_SANDBOX
+#define CONFIG_SPI_FLASH_STMICRO
+#define CONFIG_SPI_FLASH_WINBOND
 
 /* Memory things - we don't really want a memory test */
 #define CONFIG_SYS_LOAD_ADDR		0x00000000
 #define CONFIG_SYS_MEMTEST_START	0x00100000
 #define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_MEMTEST_START + 0x1000)
-#define CONFIG_PHYS_64BIT
-#define CONFIG_SYS_FDT_LOAD_ADDR	0x1000000
+#define CONFIG_SYS_FDT_LOAD_ADDR	        0x100
+
+#define CONFIG_PHYSMEM
 
 /* Size of our emulated memory */
 #define CONFIG_SYS_SDRAM_BASE		0
@@ -101,17 +131,44 @@
 #define CONFIG_SHA1
 #define CONFIG_SHA256
 
+#define CONFIG_TPM_TIS_SANDBOX
+
 #define CONFIG_CMD_SANDBOX
 
 #define CONFIG_BOOTARGS ""
 
-#define CONFIG_EXTRA_ENV_SETTINGS	"stdin=serial\0" \
-					"stdout=serial\0" \
-					"stderr=serial\0"
+#define CONFIG_CROS_EC
+#define CONFIG_CMD_CROS_EC
+#define CONFIG_CROS_EC_SANDBOX
+#define CONFIG_KEYBOARD
+#define CONFIG_CROS_EC_KEYB
+#define CONFIG_ARCH_EARLY_INIT_R
+#define CONFIG_BOARD_LATE_INIT
+
+#define CONFIG_SOUND
+#define CONFIG_SOUND_SANDBOX
+#define CONFIG_CMD_SOUND
+
+#define CONFIG_SANDBOX_SDL
+#define CONFIG_LCD
+#define CONFIG_VIDEO_SANDBOX_SDL
+#define CONFIG_CMD_BMP
+#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_CONSOLE_MUX
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV
+#define LCD_BPP			LCD_COLOR16
+
+#define CONFIG_EXTRA_ENV_SETTINGS	"stdin=serial,cros-ec-keyb\0" \
+					"stdout=serial,lcd\0" \
+					"stderr=serial,lcd\0"
 
 #define CONFIG_GZIP_COMPRESSED
 #define CONFIG_BZIP2
 #define CONFIG_LZO
 #define CONFIG_LZMA
 
+#define CONFIG_TPM_TIS_SANDBOX
+
+#define CONFIG_CMD_LZMADEC
+
 #endif
diff --git a/include/configs/sansa_fuze_plus.h b/include/configs/sansa_fuze_plus.h
index a85eb1c3fc..8cce34af76 100644
--- a/include/configs/sansa_fuze_plus.h
+++ b/include/configs/sansa_fuze_plus.h
@@ -56,7 +56,7 @@
 #define CONFIG_EHCI_MXS_PORT0
 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
 
-#define CONFIG_MV_UDC		/* ChipIdea CI13xxx UDC */
+#define CONFIG_CI_UDC		/* ChipIdea CI13xxx UDC */
 #define CONFIG_USB_GADGET_DUALSPEED
 
 #define CONFIG_USB_ETHER
diff --git a/include/configs/sbc35_a9g20.h b/include/configs/sbc35_a9g20.h
index 4ba224252a..a1b5751d09 100644
--- a/include/configs/sbc35_a9g20.h
+++ b/include/configs/sbc35_a9g20.h
@@ -12,7 +12,7 @@
 
 /* SoC type is defined in boards.cfg */
 #include <asm/hardware.h>
-#include <asm/sizes.h>
+#include <linux/sizes.h>
 
 #if defined(CONFIG_SYS_USE_NANDFLASH)
 #define CONFIG_ENV_IS_IN_NAND
@@ -26,7 +26,6 @@
 /* ARM asynchronous clock */
 #define CONFIG_SYS_AT91_SLOW_CLOCK	32768		/* slow clock xtal */
 #define CONFIG_SYS_AT91_MAIN_CLOCK	12000000	/* 12.000 MHz crystal */
-#define CONFIG_SYS_HZ		        1000
 
 #define CONFIG_ARCH_CPU_INIT
 
@@ -116,9 +115,11 @@
 #define CONFIG_NET_RETRY_COUNT		20
 #define CONFIG_RESET_PHY_R
 #define CONFIG_MACB_SEARCH_PHY
+#define CONFIG_AT91_WANTS_COMMON_PHY
 
 /* USB */
 #define CONFIG_USB_ATMEL
+#define CONFIG_USB_ATMEL_CLK_SEL_PLLB
 #define CONFIG_USB_OHCI_NEW
 #define CONFIG_DOS_PARTITION
 #define CONFIG_SYS_USB_OHCI_CPU_INIT
diff --git a/include/configs/sbc405.h b/include/configs/sbc405.h
index a139590be8..69dc210917 100644
--- a/include/configs/sbc405.h
+++ b/include/configs/sbc405.h
@@ -17,7 +17,6 @@
  */
 
 #define CONFIG_405GP		1	/* This is a PPC405 CPU		*/
-#define CONFIG_4xx		1	/* ...member of PPC4xx family	*/
 #define CONFIG_SBC405		1	/* ...on a WR SBC405 board	*/
 
 #define	CONFIG_SYS_TEXT_BASE	0xFFFC0000
@@ -113,7 +112,6 @@
  * Miscellaneous configurable options
  */
 #define CONFIG_SYS_LONGHELP			/* undef to save memory		*/
-#define CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt	*/
 
 #undef CONFIG_SYS_HUSH_PARSER			/* use "hush" command parser	*/
 
@@ -146,8 +144,6 @@
 #define CONFIG_SYS_LOAD_ADDR	0x100000	/* default load address */
 #define CONFIG_SYS_EXTBDINFO	1		/* To use extended board_info (bd_t) */
 
-#define CONFIG_SYS_HZ		1000		/* decrementer freq: 1 ms ticks */
-
 #define CONFIG_VERSION_VARIABLE	1	/* include version env variable */
 
 #define CONFIG_SYS_RX_ETH_BUFFER	16	/* use 16 rx buffer on 405 emac */
diff --git a/include/configs/sbc8349.h b/include/configs/sbc8349.h
index 63ee4537d6..2516a3e97e 100644
--- a/include/configs/sbc8349.h
+++ b/include/configs/sbc8349.h
@@ -19,7 +19,6 @@
  * High Level Configuration Options
  */
 #define CONFIG_E300		1	/* E300 Family */
-#define CONFIG_MPC83xx		1	/* MPC83xx family */
 #define CONFIG_MPC834x		1	/* MPC834x family */
 #define CONFIG_MPC8349		1	/* MPC8349 specific */
 #define CONFIG_SBC8349		1	/* WRS SBC8349 board specific */
@@ -438,7 +437,6 @@
  */
 #define CONFIG_SYS_LONGHELP			/* undef to save memory */
 #define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
-#define CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt */
 
 #if defined(CONFIG_CMD_KGDB)
 	#define CONFIG_SYS_CBSIZE	1024	/* Console I/O Buffer Size */
@@ -451,7 +449,6 @@
 #define CONFIG_SYS_MAXARGS	16	/* max number of command args */
 				/* Boot Argument Buffer Size */
 #define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE
-#define CONFIG_SYS_HZ		1000	/* decrementer freq: 1ms ticks */
 
 /*
  * For booting Linux, the board info and command line data
@@ -645,7 +642,6 @@
 
 #if defined(CONFIG_CMD_KGDB)
 #define CONFIG_KGDB_BAUDRATE	230400	/* speed of kgdb serial port */
-#define CONFIG_KGDB_SER_INDEX	2	/* which serial port to use */
 #endif
 
 /*
diff --git a/include/configs/sbc8548.h b/include/configs/sbc8548.h
index 84be5246b9..f28f350fcc 100644
--- a/include/configs/sbc8548.h
+++ b/include/configs/sbc8548.h
@@ -38,7 +38,6 @@
  */
 #define CONFIG_BOOKE		1	/* BOOKE */
 #define CONFIG_E500		1	/* BOOKE e500 family */
-#define CONFIG_MPC85xx		1	/* MPC8540/60/55/41/48 */
 #define CONFIG_MPC8548		1	/* MPC8548 specific */
 #define CONFIG_SBC8548		1	/* SBC8548 board specific */
 
@@ -102,7 +101,7 @@
 #define CONFIG_SYS_CCSRBAR_PHYS_LOW	CONFIG_SYS_CCSRBAR
 
 /* DDR Setup */
-#define CONFIG_FSL_DDR2
+#define CONFIG_SYS_FSL_DDR2
 #undef CONFIG_FSL_DDR_INTERACTIVE
 #undef CONFIG_DDR_ECC			/* only for ECC DDR module */
 /*
@@ -557,7 +556,6 @@
 #define CONFIG_AUTO_COMPLETE			/* add autocompletion support */
 #define CONFIG_SYS_LONGHELP			/* undef to save memory	*/
 #define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
-#define CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt */
 #if defined(CONFIG_CMD_KGDB)
 #define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size */
 #else
@@ -566,7 +564,6 @@
 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
 #define CONFIG_SYS_MAXARGS	16		/* max number of command args */
 #define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size */
-#define CONFIG_SYS_HZ		1000		/* decrementer freq: 1ms ticks */
 
 /*
  * For booting Linux, the board info and command line data
@@ -577,7 +574,6 @@
 
 #if defined(CONFIG_CMD_KGDB)
 #define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
-#define CONFIG_KGDB_SER_INDEX	2	/* which serial port to use */
 #endif
 
 /*
diff --git a/include/configs/sbc8641d.h b/include/configs/sbc8641d.h
index a489bb1211..8eb7276618 100644
--- a/include/configs/sbc8641d.h
+++ b/include/configs/sbc8641d.h
@@ -21,7 +21,6 @@
 #define __CONFIG_H
 
 /* High Level Configuration Options */
-#define CONFIG_MPC86xx		1	/* MPC86xx */
 #define CONFIG_MPC8641		1	/* MPC8641 specific */
 #define CONFIG_SBC8641D		1	/* SBC8641D board specific */
 #define CONFIG_MP		1	/* support multiple processors */
@@ -496,7 +495,6 @@
  */
 #define CONFIG_SYS_LONGHELP			/* undef to save memory	*/
 #define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
-#define CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt */
 
 #if defined(CONFIG_CMD_KGDB)
     #define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size */
@@ -507,7 +505,6 @@
 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
 #define CONFIG_SYS_MAXARGS	16		/* max number of command args */
 #define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size */
-#define CONFIG_SYS_HZ		1000		/* decrementer freq: 1ms ticks */
 
 /*
  * For booting Linux, the board info and command line data
@@ -525,7 +522,6 @@
 
 #if defined(CONFIG_CMD_KGDB)
 #define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
-#define CONFIG_KGDB_SER_INDEX	2	/* which serial port to use */
 #endif
 
 /*
diff --git a/include/configs/sc3.h b/include/configs/sc3.h
index 60710ba829..14e033dd80 100644
--- a/include/configs/sc3.h
+++ b/include/configs/sc3.h
@@ -43,7 +43,6 @@
  */
 
 #define CONFIG_SC3	1
-#define CONFIG_4xx	1
 #define CONFIG_405GP	1
 
 #define	CONFIG_SYS_TEXT_BASE	0xFFFA0000
@@ -224,8 +223,6 @@
 #define CONFIG_SYS_LOAD_ADDR		0x1000000	/* default load address */
 #define CONFIG_SYS_EXTBDINFO		1	/* To use extended board_into (bd_t) */
 
-#define	CONFIG_SYS_HZ			1000	/* decrementer freq: 1 ms ticks	*/
-
 /*-----------------------------------------------------------------------
  * IIC stuff
  *-----------------------------------------------------------------------
diff --git a/include/configs/scb9328.h b/include/configs/scb9328.h
index a09310c889..e6d272dd1f 100644
--- a/include/configs/scb9328.h
+++ b/include/configs/scb9328.h
@@ -69,7 +69,6 @@
 #define CONFIG_SYS_MEMTEST_START	0x08100000	      /* memtest test area   */
 #define CONFIG_SYS_MEMTEST_END		0x08F00000
 
-#define CONFIG_SYS_HZ			3686400	     /* incrementer freq: 3.6864 MHz */
 #define CONFIG_SYS_CPUSPEED		0x141	     /* core clock - register value  */
 
 #define CONFIG_BAUDRATE 115200
@@ -143,8 +142,8 @@
    now.*/
 #undef	CONFIG_SYS_FLASH_CFI
 
-#define CONFIG_SYS_FLASH_ERASE_TOUT	(2*CONFIG_SYS_HZ)    /* timeout for Erase operation */
-#define CONFIG_SYS_FLASH_WRITE_TOUT	(2*CONFIG_SYS_HZ)    /* timeout for Write operation */
+#define CONFIG_SYS_FLASH_ERASE_TOUT	240000    /* timeout for Erase operation */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	240000    /* timeout for Write operation */
 
 #define CONFIG_SYS_FLASH_BASE		SCB9328_FLASH_BASE
 
diff --git a/include/configs/seaboard.h b/include/configs/seaboard.h
index 2a24ef3c64..fc4f976d8d 100644
--- a/include/configs/seaboard.h
+++ b/include/configs/seaboard.h
@@ -8,7 +8,7 @@
 #ifndef __CONFIG_H
 #define __CONFIG_H
 
-#include <asm/sizes.h>
+#include <linux/sizes.h>
 
 /* LP0 suspend / resume */
 #define CONFIG_TEGRA_LP0
diff --git a/include/configs/sequoia.h b/include/configs/sequoia.h
index d2dedac4ed..b6a5e6a59c 100644
--- a/include/configs/sequoia.h
+++ b/include/configs/sequoia.h
@@ -27,7 +27,6 @@
 #define CONFIG_HOSTNAME		rainier
 #endif
 #define CONFIG_440		1	/* ... PPC440 family		*/
-#define CONFIG_4xx		1	/* ... PPC4xx family		*/
 
 #ifndef CONFIG_SYS_TEXT_BASE
 #define CONFIG_SYS_TEXT_BASE	0xFFF80000
@@ -98,10 +97,7 @@
 /*
  * Environment
  */
-#if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
-#define CONFIG_ENV_IS_IN_NAND		/* use NAND for environ vars	*/
-#define CONFIG_ENV_IS_EMBEDDED		/* use embedded environment	*/
-#elif defined(CONFIG_SYS_RAMBOOT)
+#if defined(CONFIG_SYS_RAMBOOT)
 #define CONFIG_ENV_IS_NOWHERE		/* Store env in memory only	*/
 #define CONFIG_ENV_SIZE		(8 << 10)
 /*
@@ -150,67 +146,10 @@
 #endif /* CONFIG_CMD_FLASH */
 
 /*
- * IPL (Initial Program Loader, integrated inside CPU)
- * Will load first 4k from NAND (SPL) into cache and execute it from there.
- *
- * SPL (Secondary Program Loader)
- * Will load special U-Boot version (NUB) from NAND and execute it. This SPL
- * has to fit into 4kByte. It sets up the CPU and configures the SDRAM
- * controller and the NAND controller so that the special U-Boot image can be
- * loaded from NAND to SDRAM.
- *
- * NUB (NAND U-Boot)
- * This NAND U-Boot (NUB) is a special U-Boot version which can be started
- * from RAM. Therefore it mustn't (re-)configure the SDRAM controller.
- *
- * On 440EPx the SPL is copied to SDRAM before the NAND controller is
- * set up. While still running from cache, I experienced problems accessing
- * the NAND controller.	sr - 2006-08-25
- */
-#define CONFIG_SYS_NAND_BOOT_SPL_SRC	0xfffff000	/* SPL location		      */
-#define CONFIG_SYS_NAND_BOOT_SPL_SIZE	(4 << 10)	/* SPL size		      */
-#define CONFIG_SYS_NAND_BOOT_SPL_DST	(CONFIG_SYS_OCM_BASE + (12 << 10)) /* Copy SPL here  */
-#define CONFIG_SYS_NAND_U_BOOT_DST	0x01000000	/* Load NUB to this addr      */
-#define CONFIG_SYS_NAND_U_BOOT_START	CONFIG_SYS_NAND_U_BOOT_DST	/* Start NUB from     */
-							/*   this addr	      */
-#define CONFIG_SYS_NAND_BOOT_SPL_DELTA	(CONFIG_SYS_NAND_BOOT_SPL_SRC - CONFIG_SYS_NAND_BOOT_SPL_DST)
-
-/*
- * Define the partitioning of the NAND chip (only RAM U-Boot is needed here)
- */
-#define CONFIG_SYS_NAND_U_BOOT_OFFS	(16 << 10)	/* Offset to RAM U-Boot image */
-#define CONFIG_SYS_NAND_U_BOOT_SIZE	(512 << 10)	/* Size of RAM U-Boot image   */
-
-/*
- * Now the NAND chip has to be defined (no autodetection used!)
- */
-#define CONFIG_SYS_NAND_PAGE_SIZE	512		/* NAND chip page size	      */
-#define CONFIG_SYS_NAND_BLOCK_SIZE	(16 << 10)	/* NAND chip block size	      */
-#define CONFIG_SYS_NAND_PAGE_COUNT	32		/* NAND chip page count	      */
-#define CONFIG_SYS_NAND_BAD_BLOCK_POS	5	      /* Location of bad block marker */
-#undef CONFIG_SYS_NAND_4_ADDR_CYCLE		      /* No fourth addr used (<=32MB) */
-
-#define CONFIG_SYS_NAND_ECCSIZE	256
-#define CONFIG_SYS_NAND_ECCBYTES	3
-#define CONFIG_SYS_NAND_OOBSIZE	16
-#define CONFIG_SYS_NAND_ECCPOS		{0, 1, 2, 3, 6, 7}
-
-#ifdef CONFIG_ENV_IS_IN_NAND
-/*
- * For NAND booting the environment is embedded in the U-Boot image. Please take
- * look at the file board/amcc/sequoia/u-boot-nand.lds for details.
- */
-#define CONFIG_ENV_SIZE		CONFIG_SYS_NAND_BLOCK_SIZE
-#define CONFIG_ENV_OFFSET		(CONFIG_SYS_NAND_U_BOOT_OFFS + CONFIG_ENV_SIZE)
-#define CONFIG_ENV_OFFSET_REDUND	(CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
-#endif
-
-/*
  * DDR SDRAM
  */
 #define CONFIG_SYS_MBYTES_SDRAM        (256)	/* 256MB			*/
-#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) && \
-    !defined(CONFIG_SYS_RAMBOOT)
+#if !defined(CONFIG_SYS_RAMBOOT)
 #define CONFIG_DDR_DATA_EYE		/* use DDR2 optimization	*/
 #endif
 #define CONFIG_SYS_MEM_TOP_HIDE	(4 << 10) /* don't use last 4kbytes	*/
@@ -248,7 +187,6 @@
 	CONFIG_AMCC_DEF_ENV_POWERPC					\
 	CONFIG_AMCC_DEF_ENV_PPC_OLD					\
 	CONFIG_AMCC_DEF_ENV_NOR_UPD					\
-	CONFIG_AMCC_DEF_ENV_NAND_UPD					\
 	"kernel_addr=FC000000\0"					\
 	"ramdisk_addr=FC180000\0"					\
 	""
@@ -322,7 +260,7 @@
  * overwrite part of the U-Boot image which is already loaded from NAND
  * to SDRAM.
  */
-#if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_SYS_RAMBOOT)
+#if defined(CONFIG_SYS_RAMBOOT)
 #define CONFIG_SYS_POST_MEMORY_ON	0
 #else
 #define CONFIG_SYS_POST_MEMORY_ON	CONFIG_SYS_POST_MEMORY
@@ -371,8 +309,7 @@
 /*
  * On Sequoia CS0 and CS3 are switched when configuring for NAND booting
  */
-#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) && \
-    !defined(CONFIG_SYS_RAMBOOT)
+#if !defined(CONFIG_SYS_RAMBOOT)
 #define CONFIG_SYS_NAND_CS		3	/* NAND chip connected to CSx	*/
 /* Memory Bank 0 (NOR-FLASH) initialization				*/
 #define CONFIG_SYS_EBC_PB0AP		0x03017200
diff --git a/include/configs/sh7752evb.h b/include/configs/sh7752evb.h
index fb4dc6fde4..f06abbca0c 100644
--- a/include/configs/sh7752evb.h
+++ b/include/configs/sh7752evb.h
@@ -10,8 +10,6 @@
 #define __SH7752EVB_H
 
 #undef DEBUG
-#define CONFIG_SH		1
-#define CONFIG_SH4A		1
 #define CONFIG_SH_32BIT		1
 #define CONFIG_CPU_SH7752	1
 #define CONFIG_SH7752EVB	1
@@ -51,7 +49,6 @@
 #define SH7752EVB_SDRAM_SIZE		(512 * 1024 * 1024)
 
 #define CONFIG_SYS_LONGHELP
-#define CONFIG_SYS_PROMPT		"=> "
 #define CONFIG_SYS_CBSIZE		256
 #define CONFIG_SYS_PBSIZE		256
 #define CONFIG_SYS_MAXARGS		16
@@ -132,6 +129,7 @@
 
 /* Board Clock */
 #define CONFIG_SYS_CLK_FREQ	48000000
+#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
+#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
 #define CONFIG_SYS_TMU_CLK_DIV	4
-#define CONFIG_SYS_HZ		1000
 #endif	/* __SH7752EVB_H */
diff --git a/include/configs/sh7753evb.h b/include/configs/sh7753evb.h
new file mode 100644
index 0000000000..e400db08ad
--- /dev/null
+++ b/include/configs/sh7753evb.h
@@ -0,0 +1,135 @@
+/*
+ * Configuation settings for the sh7753evb board
+ *
+ * Copyright (C) 2012 Renesas Solutions Corp.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __SH7753EVB_H
+#define __SH7753EVB_H
+
+#undef DEBUG
+#define CONFIG_SH_32BIT		1
+#define CONFIG_CPU_SH7753	1
+#define CONFIG_SH7753EVB	1
+
+#define CONFIG_SYS_TEXT_BASE	0x5ff80000
+#define CONFIG_SYS_LDSCRIPT	"board/renesas/sh7753evb/u-boot.lds"
+
+#define CONFIG_CMD_MEMORY
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_DFL
+#define CONFIG_CMD_SDRAM
+#define CONFIG_CMD_SF
+#define CONFIG_CMD_RUN
+#define CONFIG_CMD_SAVEENV
+#define CONFIG_CMD_MD5SUM
+#define CONFIG_MD5
+#define CONFIG_CMD_LOADS
+#define CONFIG_CMD_MMC
+#define CONFIG_CMD_EXT2
+#define CONFIG_DOS_PARTITION
+#define CONFIG_MAC_PARTITION
+
+#define CONFIG_BAUDRATE		115200
+#define CONFIG_BOOTDELAY	3
+#define CONFIG_BOOTARGS		"console=ttySC2,115200 root=/dev/nfs ip=dhcp"
+
+#define CONFIG_VERSION_VARIABLE
+#undef	CONFIG_SHOW_BOOT_PROGRESS
+#define CONFIG_CMDLINE_EDITING
+#define CONFIG_AUTO_COMPLETE
+
+/* MEMORY */
+#define SH7753EVB_SDRAM_BASE		(0x40000000)
+#define SH7753EVB_SDRAM_SIZE		(512 * 1024 * 1024)
+
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_SYS_CBSIZE		256
+#define CONFIG_SYS_PBSIZE		256
+#define CONFIG_SYS_MAXARGS		16
+#define CONFIG_SYS_BARGSIZE		512
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 115200 }
+
+/* SCIF */
+#define CONFIG_SCIF_CONSOLE	1
+#define CONFIG_CONS_SCIF2	1
+#undef	CONFIG_SYS_CONSOLE_INFO_QUIET
+#undef	CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
+#undef	CONFIG_SYS_CONSOLE_ENV_OVERWRITE
+
+#define CONFIG_SYS_MEMTEST_START	(SH7753EVB_SDRAM_BASE)
+#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_MEMTEST_START + \
+					 480 * 1024 * 1024)
+#undef	CONFIG_SYS_ALT_MEMTEST
+#undef	CONFIG_SYS_MEMTEST_SCRATCH
+#undef	CONFIG_SYS_LOADS_BAUD_CHANGE
+
+#define CONFIG_SYS_SDRAM_BASE		(SH7753EVB_SDRAM_BASE)
+#define CONFIG_SYS_SDRAM_SIZE		(SH7753EVB_SDRAM_SIZE)
+#define CONFIG_SYS_LOAD_ADDR		(CONFIG_SYS_SDRAM_BASE + \
+					 128 * 1024 * 1024)
+
+#define CONFIG_SYS_MONITOR_BASE		0x00000000
+#define CONFIG_SYS_MONITOR_LEN		(512 * 1024)
+#define CONFIG_SYS_MALLOC_LEN		(4 * 1024 * 1024)
+#define CONFIG_SYS_BOOTMAPSZ		(8 * 1024 * 1024)
+
+/* FLASH */
+#define CONFIG_SYS_NO_FLASH
+
+/* Ether */
+#define CONFIG_SH_ETHER			1
+#define CONFIG_SH_ETHER_USE_PORT	0
+#define CONFIG_SH_ETHER_PHY_ADDR	18
+#define CONFIG_SH_ETHER_CACHE_WRITEBACK	1
+#define CONFIG_SH_ETHER_USE_GETHER	1
+#define CONFIG_PHYLIB
+#define CONFIG_BITBANGMII
+#define CONFIG_BITBANGMII_MULTI
+#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RGMII
+#define CONFIG_PHY_VITESSE
+
+#define SH7753EVB_ETHERNET_MAC_BASE_SPI	0x00090000
+#define SH7753EVB_SPI_SECTOR_SIZE	(64 * 1024)
+#define SH7753EVB_ETHERNET_MAC_BASE	SH7753EVB_ETHERNET_MAC_BASE_SPI
+#define SH7753EVB_ETHERNET_MAC_SIZE	17
+#define SH7753EVB_ETHERNET_NUM_CH	2
+#define CONFIG_BOARD_LATE_INIT
+
+/* SPI */
+#define CONFIG_SH_SPI			1
+#define CONFIG_SH_SPI_BASE		0xfe002000
+#define CONFIG_SPI_FLASH
+#define CONFIG_SPI_FLASH_STMICRO	1
+#define CONFIG_SPI_FLASH_MACRONIX	1
+
+/* MMCIF */
+#define CONFIG_MMC			1
+#define CONFIG_GENERIC_MMC		1
+#define CONFIG_SH_MMCIF			1
+#define CONFIG_SH_MMCIF_ADDR		0xffcb0000
+#define CONFIG_SH_MMCIF_CLK		48000000
+
+/* ENV setting */
+#define CONFIG_ENV_IS_EMBEDDED
+#define CONFIG_ENV_IS_IN_SPI_FLASH
+#define CONFIG_ENV_SECT_SIZE	(64 * 1024)
+#define CONFIG_ENV_ADDR		(0x00080000)
+#define CONFIG_ENV_OFFSET	(CONFIG_ENV_ADDR)
+#define CONFIG_ENV_OVERWRITE	1
+#define CONFIG_ENV_SIZE		(CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SECT_SIZE)
+#define CONFIG_EXTRA_ENV_SETTINGS				\
+		"netboot=bootp; bootm\0"
+
+/* Board Clock */
+#define CONFIG_SYS_CLK_FREQ	48000000
+#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
+#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
+#define CONFIG_SYS_TMU_CLK_DIV	4
+#endif	/* __SH7753EVB_H */
diff --git a/include/configs/sh7757lcr.h b/include/configs/sh7757lcr.h
index af76f49dd2..08bff1da3f 100644
--- a/include/configs/sh7757lcr.h
+++ b/include/configs/sh7757lcr.h
@@ -10,8 +10,6 @@
 #define __SH7757LCR_H
 
 #undef DEBUG
-#define CONFIG_SH		1
-#define CONFIG_SH4A		1
 #define CONFIG_SH_32BIT		1
 #define CONFIG_CPU_SH7757	1
 #define CONFIG_SH7757LCR	1
@@ -51,7 +49,6 @@
 #define SH7757LCR_SDRAM_DVC_SIZE	(16 * 1024 * 1024)
 
 #define CONFIG_SYS_LONGHELP
-#define CONFIG_SYS_PROMPT		"=> "
 #define CONFIG_SYS_CBSIZE		256
 #define CONFIG_SYS_PBSIZE		256
 #define CONFIG_SYS_MAXARGS		16
@@ -140,6 +137,7 @@
 
 /* Board Clock */
 #define CONFIG_SYS_CLK_FREQ	48000000
+#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
+#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
 #define CONFIG_SYS_TMU_CLK_DIV	4
-#define CONFIG_SYS_HZ		1000
 #endif	/* __SH7757LCR_H */
diff --git a/include/configs/sh7763rdp.h b/include/configs/sh7763rdp.h
index c1d33d87ba..2438318fca 100644
--- a/include/configs/sh7763rdp.h
+++ b/include/configs/sh7763rdp.h
@@ -10,8 +10,6 @@
 #ifndef __SH7763RDP_H
 #define __SH7763RDP_H
 
-#define CONFIG_SH		1
-#define CONFIG_SH4		1
 #define CONFIG_CPU_SH7763	1
 #define CONFIG_SH7763RDP	1
 #define __LITTLE_ENDIAN		1
@@ -43,7 +41,6 @@
 
 #define CONFIG_SYS_TEXT_BASE	0x8FFC0000
 #define CONFIG_SYS_LONGHELP		/* undef to save memory */
-#define CONFIG_SYS_PROMPT		"=> "	/* Monitor Command Prompt */
 #define CONFIG_SYS_CBSIZE		256	/* Buffer size for input from the Console */
 #define CONFIG_SYS_PBSIZE		256	/* Buffer size for Console output */
 #define CONFIG_SYS_MAXARGS		16	/* max args accepted for monitor commands */
@@ -98,8 +95,9 @@
 
 /* Clock */
 #define CONFIG_SYS_CLK_FREQ	66666666
+#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
+#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
 #define CONFIG_SYS_TMU_CLK_DIV		(4)	/* 4 (default), 16, 64, 256 or 1024 */
-#define CONFIG_SYS_HZ		1000
 
 /* Ether */
 #define CONFIG_SH_ETHER 1
diff --git a/include/configs/sh7785lcr.h b/include/configs/sh7785lcr.h
index 04f1d2284e..2723eaf2d3 100644
--- a/include/configs/sh7785lcr.h
+++ b/include/configs/sh7785lcr.h
@@ -10,8 +10,6 @@
 #define __SH7785LCR_H
 
 #undef DEBUG
-#define CONFIG_SH		1
-#define CONFIG_SH4A		1
 #define CONFIG_CPU_SH7785	1
 #define CONFIG_SH7785LCR	1
 
@@ -65,7 +63,6 @@
 #endif
 
 #define CONFIG_SYS_LONGHELP
-#define CONFIG_SYS_PROMPT		"=> "
 #define CONFIG_SYS_CBSIZE		256
 #define CONFIG_SYS_PBSIZE		256
 #define CONFIG_SYS_MAXARGS		16
@@ -172,7 +169,8 @@
 /* Board Clock */
 /* The SCIF used external clock. system clock only used timer. */
 #define CONFIG_SYS_CLK_FREQ	50000000
+#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
+#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
 #define CONFIG_SYS_TMU_CLK_DIV		4
-#define CONFIG_SYS_HZ		1000
 
 #endif	/* __SH7785LCR_H */
diff --git a/include/configs/shmin.h b/include/configs/shmin.h
index 5fb71760f8..4d38f6c554 100644
--- a/include/configs/shmin.h
+++ b/include/configs/shmin.h
@@ -9,8 +9,6 @@
 #ifndef __SHMIN_H
 #define __SHMIN_H
 
-#define CONFIG_SH		1
-#define CONFIG_SH3		1
 #define CONFIG_CPU_SH7706	1
 /* T-SH7706LAN */
 #define CONFIG_SHMIN		1
@@ -42,7 +40,6 @@
 
 #define CONFIG_SYS_TEXT_BASE	0x8DFB0000
 #define CONFIG_SYS_LONGHELP		/* undef to save memory	*/
-#define CONFIG_SYS_PROMPT	"=> "	/* Monitor Command Prompt */
 #define CONFIG_SYS_CBSIZE	256	/* Buffer size for input from the Console */
 #define CONFIG_SYS_PBSIZE	256	/* Buffer size for Console output */
 #define CONFIG_SYS_MAXARGS	16	/* max args accepted for monitor commands */
@@ -65,7 +62,6 @@
 #define CONFIG_SYS_MONITOR_BASE		(SHMIN_FLASH_BASE_1 + CONFIG_ENV_SECT_SIZE)
 #define CONFIG_SYS_MONITOR_LEN		(128 * 1024)
 #define CONFIG_SYS_MALLOC_LEN		(256 * 1024)
-#define CONFIG_SYS_GBL_DATA_SIZE	256
 #define CONFIG_SYS_BOOTMAPSZ		(8 * 1024 * 1024)
 
 /* FLASH */
@@ -103,8 +99,9 @@
 #else
 #define CONFIG_SYS_CLK_FREQ 33333333
 #endif /* CONFIG_T_SH7706LSR */
+#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
+#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
 #define CONFIG_SYS_TMU_CLK_DIV	4
-#define CONFIG_SYS_HZ	1000
 
 /* Network device */
 #define CONFIG_DRIVER_NE2000
diff --git a/include/configs/siemens-am33x-common.h b/include/configs/siemens-am33x-common.h
index 5426ee8720..721c4e6bad 100644
--- a/include/configs/siemens-am33x-common.h
+++ b/include/configs/siemens-am33x-common.h
@@ -85,7 +85,6 @@
 					+ (8 * 1024 * 1024))
 
 #define CONFIG_SYS_LOAD_ADDR		0x81000000 /* Default load address */
-#define CONFIG_SYS_HZ			1000 /* 1ms clock */
 
 #define CONFIG_MMC
 #define CONFIG_GENERIC_MMC
@@ -113,7 +112,6 @@
  /* Platform/Board specific defs */
 #define CONFIG_SYS_TIMERBASE		0x48040000	/* Use Timer2 */
 #define CONFIG_SYS_PTV			2	/* Divisor: 2^(PTV+1) => 8 */
-#define CONFIG_SYS_HZ			1000
 
 /* NS16550 Configuration */
 #define CONFIG_SYS_NS16550
@@ -133,11 +131,10 @@
 /* I2C Configuration */
 #define CONFIG_I2C
 #define CONFIG_CMD_I2C
-#define CONFIG_HARD_I2C
-#define CONFIG_SYS_I2C_SLAVE		1
-#define CONFIG_I2C_MULTI_BUS
-#define CONFIG_DRIVER_OMAP24XX_I2C
-
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_OMAP24_I2C_SPEED	OMAP_I2C_STANDARD
+#define CONFIG_SYS_OMAP24_I2C_SLAVE	1
+#define CONFIG_SYS_I2C_OMAP24XX
 
 /* Defines for SPL */
 #define CONFIG_SPL
@@ -198,6 +195,7 @@
 
 #define CONFIG_SYS_NAND_ECCSIZE		512
 #define CONFIG_SYS_NAND_ECCBYTES	14
+#define CONFIG_NAND_OMAP_ECCSCHEME	OMAP_ECC_BCH8_CODE_HW
 
 #define CONFIG_SYS_NAND_ECCSTEPS	4
 #define	CONFIG_SYS_NAND_ECCTOTAL	(CONFIG_SYS_NAND_ECCBYTES * \
@@ -256,17 +254,18 @@
 #define CONFIG_USB_GADGET
 #define CONFIG_USBDOWNLOAD_GADGET
 
-/* USB TI's IDs */
+/* USB DRACO ID as default */
 #define CONFIG_USBD_HS
-#define CONFIG_G_DNL_VENDOR_NUM 0x0525
-#define CONFIG_G_DNL_PRODUCT_NUM 0x4a47
-#define CONFIG_G_DNL_MANUFACTURER "Texas Instruments"
+#define CONFIG_G_DNL_VENDOR_NUM 0x0908
+#define CONFIG_G_DNL_PRODUCT_NUM 0x02d2
+#define CONFIG_G_DNL_MANUFACTURER "Siemens AG"
 
 /* USB Device Firmware Update support */
 #define CONFIG_DFU_FUNCTION
 #define CONFIG_DFU_NAND
 #define CONFIG_CMD_DFU
 #define CONFIG_SYS_DFU_DATA_BUF_SIZE	(1 << 20)
+#define DFU_MANIFEST_POLL_TIMEOUT	25000
 
 #endif /* CONFIG_SPL_BUILD */
 
@@ -360,31 +359,38 @@
 #define CONFIG_COMMON_ENV_SETTINGS \
 	"verify=no \0" \
 	"project_dir=systemone\0" \
+	"upgrade_available=0\0" \
+	"altbootcmd=run bootcmd\0" \
+	"bootlimit=3\0" \
+	"partitionset_active=A\0" \
 	"loadaddr=0x82000000\0" \
 	"kloadaddr=0x81000000\0" \
 	"script_addr=0x81900000\0" \
-	"console=console=ttyMTD,mtdoops console=ttyO0,115200n8\0" \
-	"active_set=a\0" \
+	"console=console=ttyMTD,mtdoops console=ttyO0,115200n8 panic=5\0" \
 	"nand_active_ubi_vol=rootfs_a\0" \
+	"nand_active_ubi_vol_A=rootfs_a\0" \
+	"nand_active_ubi_vol_B=rootfs_b\0" \
 	"nand_root_fs_type=ubifs rootwait=1\0" \
 	"nand_src_addr=0x280000\0" \
-	"nand_src_addr_a=0x280000\0" \
-	"nand_src_addr_b=0x780000\0" \
+	"nand_src_addr_A=0x280000\0" \
+	"nand_src_addr_B=0x780000\0" \
 	"nfsopts=nolock rw mem=128M\0" \
 	"ip_method=none\0" \
 	"bootenv=uEnv.txt\0" \
 	"bootargs_defaults=setenv bootargs " \
 		"console=${console} " \
+		"${testargs} " \
 		"${optargs}\0" \
 	"nand_args=run bootargs_defaults;" \
 		"mtdparts default;" \
-		"setenv nand_active_ubi_vol rootfs_${active_set};" \
-		"setenv ${active_set} true;" \
-		"if test -n ${a}; then " \
-			"setenv nand_src_addr ${nand_src_addr_a};" \
+		"setenv ${partitionset_active} true;" \
+		"if test -n ${A}; then " \
+			"setenv nand_active_ubi_vol ${nand_active_ubi_vol_A};" \
+			"setenv nand_src_addr ${nand_src_addr_A};" \
 		"fi;" \
-		"if test -n ${b}; then " \
-			"setenv nand_src_addr ${nand_src_addr_b};" \
+		"if test -n ${B}; then " \
+			"setenv nand_active_ubi_vol ${nand_active_ubi_vol_B};" \
+			"setenv nand_src_addr ${nand_src_addr_B};" \
 		"fi;" \
 		"setenv nand_root ubi0:${nand_active_ubi_vol} rw " \
 		"ubi.mtd=9,2048;" \
@@ -396,7 +402,7 @@
 	"dfu_args=run bootargs_defaults;" \
 		"setenv bootargs ${bootargs} ;" \
 		"mtdparts default; " \
-		"dfu nand 0; \0" \
+		"dfu 0 nand 0; \0" \
 		"dfu_alt_info=" DFU_ALT_INFO_NAND "\0" \
 	"net_args=run bootargs_defaults;" \
 		"mtdparts default;" \
@@ -405,9 +411,26 @@
 		"setenv bootargs ${bootargs} " \
 		"root=/dev/nfs ${mtdparts} " \
 		"nfsroot=${serverip}:${rootpath},${nfsopts} " \
-		"addip=setenv bootargs ${bootargs} ip=${ipaddr}:${serverip}:" \
+		"ip=${ipaddr}:${serverip}:" \
 		"${gatewayip}:${netmask}:${hostname}:eth0:off\0" \
-	"nand_boot=echo Booting from nand, active set ${active_set} ...; " \
+	"nand_boot=echo Booting from nand; " \
+		"if test ${upgrade_available} -eq 1; then " \
+			"if test ${bootcount} -gt ${bootlimit}; " \
+				"then " \
+				"setenv upgrade_available 0;" \
+				"setenv ${partitionset_active} true;" \
+				"if test -n ${A}; then " \
+					"setenv partitionset_active B; " \
+					"env delete A; " \
+				"fi;" \
+				"if test -n ${B}; then " \
+					"setenv partitionset_active A; " \
+					"env delete B; " \
+				"fi;" \
+				"saveenv; " \
+			"fi;" \
+		"fi;" \
+		"echo set ${partitionset_active}...;" \
 		"run nand_args; " \
 		"nand read.i ${kloadaddr} ${nand_src_addr} " \
 		"${nand_img_size}; bootm ${kloadaddr}\0" \
@@ -416,7 +439,7 @@
 		"tftpboot ${kloadaddr} ${serverip}:${bootfile}; " \
 		"bootm ${kloadaddr}\0" \
 	"flash_self=run nand_boot\0" \
-	"flash_self_test=setenv bootargs_defaults ${bootargs_defaults} test; " \
+	"flash_self_test=setenv testargs test; " \
 		"run nand_boot\0" \
 	"dfu_start=echo Preparing for dfu mode ...; " \
 		"run dfu_args; \0" \
@@ -427,13 +450,14 @@
 		"mode; echo Not ready yet: 'run flash_nfs' to use kernel " \
 		"from memory and root filesystem over NFS; echo Type " \
 		"'run net_nfs' to get Kernel over TFTP and mount root " \
-		"filesystem over NFS; echo Set active_set variable to 'a' " \
-		"or 'b' to select kernel and rootfs partition; " \
+		"filesystem over NFS; " \
+		"echo Set partitionset_active variable to 'A' " \
+		"or 'B' to select kernel and rootfs partition; " \
 		"echo" \
 		"\0"
 
 #define CONFIG_NAND_OMAP_GPMC
-#define GPMC_NAND_ECC_LP_x16_LAYOUT	1
+#define CONFIG_NAND_OMAP_ELM
 #define CONFIG_SYS_NAND_BASE		(0x08000000)	/* physical address */
 							/* to access nand at */
 							/* CS0 */
@@ -458,4 +482,15 @@
 #define CONFIG_AUTOBOOT_PROMPT	"Autobooting in %d seconds, "		\
 				"press \"<Esc><Esc>\" to stop\n", bootdelay
 
+/* Reboot after 60 sec if bootcmd fails */
+#define CONFIG_RESET_TO_RETRY
+#define CONFIG_BOOT_RETRY_TIME 60
+
+#define CONFIG_BOOTCOUNT_LIMIT
+#define CONFIG_BOOTCOUNT_ENV
+
+/* Enable Device-Tree (FDT) support */
+#define CONFIG_OF_LIBFDT
+#define CONFIG_CMD_FDT
+
 #endif	/* ! __CONFIG_SIEMENS_AM33X_COMMON_H */
diff --git a/include/configs/smdk2410.h b/include/configs/smdk2410.h
index b787270670..d4ae19f96c 100644
--- a/include/configs/smdk2410.h
+++ b/include/configs/smdk2410.h
@@ -101,8 +101,6 @@
 
 #if defined(CONFIG_CMD_KGDB)
 #define CONFIG_KGDB_BAUDRATE	115200	/* speed to run kgdb serial port */
-/* what's this ? it's not used anywhere */
-#define CONFIG_KGDB_SER_INDEX	2	/* which serial port to use */
 #endif
 
 /*
@@ -124,8 +122,6 @@
 
 #define CONFIG_SYS_LOAD_ADDR		0x30800000
 
-#define CONFIG_SYS_HZ			1000
-
 /* support additional compression methods */
 #define CONFIG_BZIP2
 #define CONFIG_LZO
diff --git a/include/configs/smdk5420.h b/include/configs/smdk5420.h
new file mode 100644
index 0000000000..b96eea8890
--- /dev/null
+++ b/include/configs/smdk5420.h
@@ -0,0 +1,54 @@
+/*
+ * Copyright (C) 2013 Samsung Electronics
+ *
+ * Configuration settings for the SAMSUNG EXYNOS5420 board.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_5420_H
+#define __CONFIG_5420_H
+
+#include <configs/exynos5-dt.h>
+
+#define CONFIG_EXYNOS5420		/* which is in a Exynos5 Family */
+#define CONFIG_SMDK5420			/* which is in a SMDK5420 */
+
+#undef CONFIG_DEFAULT_DEVICE_TREE
+#define CONFIG_DEFAULT_DEVICE_TREE	exynos5420-smdk5420
+
+#define CONFIG_VAR_SIZE_SPL
+
+#define CONFIG_SYS_SDRAM_BASE		0x20000000
+#define CONFIG_SYS_TEXT_BASE		0x23E00000
+
+#define CONFIG_BOARD_REV_GPIO_COUNT	2
+
+/* MACH_TYPE_SMDK5420 macro will be removed once added to mach-types */
+#define MACH_TYPE_SMDK5420		8002 /* Temporary number */
+#define CONFIG_MACH_TYPE		MACH_TYPE_SMDK5420
+
+/* select serial console configuration */
+#define CONFIG_SERIAL3			/* use SERIAL 3 */
+
+#ifdef CONFIG_VAR_SIZE_SPL
+#define CONFIG_SPL_TEXT_BASE		0x02024410
+#else
+#define CONFIG_SPL_TEXT_BASE	0x02024400
+#endif
+
+#define CONFIG_BOOTCOMMAND	"mmc read 20007000 451 2000; bootm 20007000"
+
+#define CONFIG_SYS_PROMPT		"SMDK5420 # "
+#define CONFIG_IDENT_STRING		" for SMDK5420"
+
+#define CONFIG_IRAM_TOP		0x02074000
+/*
+ * Put the initial stack pointer 1KB below this to allow room for the
+ * SPL marker. This value is arbitrary, but gd_t is placed starting here.
+ */
+#define CONFIG_SYS_INIT_SP_ADDR	(CONFIG_IRAM_TOP - 0x800)
+
+#define CONFIG_MAX_I2C_NUM	11
+
+#endif	/* __CONFIG_5420_H */
diff --git a/include/configs/smdkc100.h b/include/configs/smdkc100.h
index 507a5d309e..c9a2e1568f 100644
--- a/include/configs/smdkc100.h
+++ b/include/configs/smdkc100.h
@@ -166,8 +166,6 @@
 #define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_SDRAM_BASE + 0x5e00000)
 #define CONFIG_SYS_LOAD_ADDR		CONFIG_SYS_SDRAM_BASE
 
-#define CONFIG_SYS_HZ			1000
-
 /* SMDKC100 has 1 banks of DRAM, we use only one in U-Boot */
 #define CONFIG_NR_DRAM_BANKS	1
 #define PHYS_SDRAM_1		CONFIG_SYS_SDRAM_BASE	/* SDRAM Bank #1 */
diff --git a/include/configs/smdkv310.h b/include/configs/smdkv310.h
index 0496661b20..1388f49986 100644
--- a/include/configs/smdkv310.h
+++ b/include/configs/smdkv310.h
@@ -25,9 +25,6 @@
 /* Mach Type */
 #define CONFIG_MACH_TYPE		MACH_TYPE_SMDKV310
 
-/* Keep L2 Cache Disabled */
-#define CONFIG_L2_OFF			1
-
 #define CONFIG_SYS_SDRAM_BASE		0x40000000
 #define CONFIG_SYS_TEXT_BASE		0x43E00000
 
@@ -101,8 +98,6 @@
 #define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_SDRAM_BASE + 0x6000000)
 #define CONFIG_SYS_LOAD_ADDR		(CONFIG_SYS_SDRAM_BASE + 0x3E00000)
 
-#define CONFIG_SYS_HZ			1000
-
 /* SMDKV310 has 4 bank of DRAM */
 #define CONFIG_NR_DRAM_BANKS	4
 #define SDRAM_BANK_SIZE		(512UL << 20UL)	/* 512 MB */
diff --git a/include/configs/snapper9260.h b/include/configs/snapper9260.h
index 17eb5f2455..1ebee714ba 100644
--- a/include/configs/snapper9260.h
+++ b/include/configs/snapper9260.h
@@ -13,14 +13,13 @@
 
 /* SoC type is defined in boards.cfg */
 #include <asm/hardware.h>
-#include <asm/sizes.h>
+#include <linux/sizes.h>
 
 #define CONFIG_SYS_TEXT_BASE		0x20000000
 
 /* ARM asynchronous clock */
 #define CONFIG_SYS_AT91_MAIN_CLOCK	18432000 /* External Crystal, in Hz */
 #define CONFIG_SYS_AT91_SLOW_CLOCK	32768
-#define CONFIG_SYS_HZ			1000
 
 /* CPU */
 #define CONFIG_ARCH_CPU_INIT
@@ -60,11 +59,13 @@
 #define CONFIG_RMII
 #define CONFIG_NET_RETRY_COUNT		20
 #define CONFIG_RESET_PHY_R
+#define CONFIG_AT91_WANTS_COMMON_PHY
 #define CONFIG_TFTP_PORT
 #define CONFIG_TFTP_TSIZE
 
 /* USB */
 #define CONFIG_USB_ATMEL
+#define CONFIG_USB_ATMEL_CLK_SEL_PLLB
 #define CONFIG_USB_OHCI_NEW
 #define CONFIG_DOS_PARTITION
 #define CONFIG_SYS_USB_OHCI_CPU_INIT
@@ -74,7 +75,6 @@
 #define CONFIG_USB_STORAGE
 
 /* GPIOs and IO expander */
-#define CONFIG_AT91_LEGACY
 #define CONFIG_ATMEL_LEGACY
 #define CONFIG_AT91_GPIO
 #define CONFIG_AT91_GPIO_PULLUP		1
diff --git a/include/configs/snowball.h b/include/configs/snowball.h
index edc426aa0d..dacb5604cd 100644
--- a/include/configs/snowball.h
+++ b/include/configs/snowball.h
@@ -23,11 +23,9 @@
  * (easy to change)
  */
 #define CONFIG_U8500
-#define CONFIG_L2_OFF
 
 #define CONFIG_SYS_MEMTEST_START	0x00000000
 #define CONFIG_SYS_MEMTEST_END	0x1FFFFFFF
-#define CONFIG_SYS_HZ		1000		/* must be 1000 */
 
 /*-----------------------------------------------------------------------
  * Size of environment and malloc() pool
@@ -43,8 +41,6 @@
 #define CONFIG_ENV_SIZE		(8*1024)
 #define CONFIG_SYS_MALLOC_LEN	(CONFIG_ENV_SIZE + 256*1024)
 
-#define CONFIG_SYS_GBL_DATA_SIZE	128	/* for initial data */
-
 #define CONFIG_ENV_IS_IN_MMC
 #define CONFIG_CMD_ENV
 #define CONFIG_CMD_SAVEENV
diff --git a/include/configs/socfpga_cyclone5.h b/include/configs/socfpga_cyclone5.h
index 346ca72327..0254249751 100644
--- a/include/configs/socfpga_cyclone5.h
+++ b/include/configs/socfpga_cyclone5.h
@@ -8,6 +8,7 @@
 
 #include <asm/arch/socfpga_base_addrs.h>
 #include "../../board/altera/socfpga/pinmux_config.h"
+#include "../../board/altera/socfpga/pll_config.h"
 
 /*
  * High level configuration
@@ -16,7 +17,6 @@
 #define CONFIG_SOCFPGA_VIRTUAL_TARGET
 
 #define CONFIG_ARMV7
-#define CONFIG_L2_OFF
 #define CONFIG_SYS_DCACHE_OFF
 #undef CONFIG_USE_IRQ
 
@@ -196,12 +196,12 @@
 /* reload value when timer count to zero */
 #define TIMER_LOAD_VAL			0xFFFFFFFF
 /* Timer info */
-#define CONFIG_SYS_HZ			1000
 #ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
-#define CONFIG_TIMER_CLOCK_KHZ		2400
+#define CONFIG_SYS_TIMER_RATE		2400000
 #else
-#define CONFIG_TIMER_CLOCK_KHZ		25000
+#define CONFIG_SYS_TIMER_RATE		25000000
 #endif
+#define CONFIG_SYS_TIMER_COUNTER	(CONFIG_SYS_TIMERBASE + 0x4)
 
 #define CONFIG_ENV_IS_NOWHERE
 
diff --git a/include/configs/socrates.h b/include/configs/socrates.h
index 5250d47166..c654a0e4eb 100644
--- a/include/configs/socrates.h
+++ b/include/configs/socrates.h
@@ -25,7 +25,6 @@
 /* High Level Configuration Options */
 #define CONFIG_BOOKE		1	/* BOOKE			*/
 #define CONFIG_E500		1	/* BOOKE e500 family		*/
-#define CONFIG_MPC85xx		1	/* MPC8540/60/55/41		*/
 #define CONFIG_MPC8544		1
 #define CONFIG_SOCRATES		1
 
@@ -80,7 +79,7 @@
 #define CONFIG_SYS_CCSRBAR_PHYS_LOW	CONFIG_SYS_CCSRBAR
 
 /* DDR Setup */
-#define CONFIG_FSL_DDR2
+#define CONFIG_SYS_FSL_DDR2
 #undef CONFIG_FSL_DDR_INTERACTIVE
 #define CONFIG_SPD_EEPROM		/* Use SPD EEPROM for DDR setup */
 #define CONFIG_DDR_SPD
@@ -343,7 +342,6 @@
  */
 #define CONFIG_SYS_LONGHELP			/* undef to save memory		*/
 #define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address		*/
-#define CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt	*/
 
 #if defined(CONFIG_CMD_KGDB)
     #define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
@@ -354,7 +352,6 @@
 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buf Size	*/
 #define CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
 #define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
-#define CONFIG_SYS_HZ		1000		/* decrementer freq: 1ms ticks	*/
 
 /*
  * For booting Linux, the board info and command line data
@@ -365,7 +362,6 @@
 
 #if defined(CONFIG_CMD_KGDB)
 #define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port*/
-#define CONFIG_KGDB_SER_INDEX	2	/* which serial port to use	*/
 #endif
 
 
diff --git a/include/configs/spc1920.h b/include/configs/spc1920.h
index a5b3b781ae..127de000f0 100644
--- a/include/configs/spc1920.h
+++ b/include/configs/spc1920.h
@@ -95,7 +95,6 @@
  * Miscellaneous configurable options
  */
 #define	CONFIG_SYS_LONGHELP				/* undef to save memory		*/
-#define	CONFIG_SYS_PROMPT		"=>"		/* Monitor Command Prompt	*/
 #define CONFIG_SYS_HUSH_PARSER
 
 #if defined(CONFIG_CMD_KGDB)
@@ -110,8 +109,6 @@
 
 #define CONFIG_SYS_LOAD_ADDR		0x00100000
 
-#define	CONFIG_SYS_HZ		        1000	/* decrementer freq: 1 ms ticks */
-
 #define CONFIG_SYS_BAUDRATE_TABLE	{ 2400, 4800, 9600, 19200 }
 
 /*
diff --git a/include/configs/spear-common.h b/include/configs/spear-common.h
index c11c2b4d05..c0eba3721d 100644
--- a/include/configs/spear-common.h
+++ b/include/configs/spear-common.h
@@ -17,11 +17,9 @@
 /* Ethernet driver configuration */
 #define CONFIG_MII
 #define CONFIG_DESIGNWARE_ETH
-#define CONFIG_DW_SEARCH_PHY
-#define CONFIG_DW0_PHY				1
 #define CONFIG_NET_MULTI
+#define CONFIG_PHYLIB
 #define CONFIG_PHY_RESET_DELAY			10000		/* in usec */
-#define CONFIG_DW_AUTONEG
 #define CONFIG_PHY_GIGE			/* Include GbE speed/duplex detection */
 
 /* USBD driver configuration */
@@ -41,13 +39,21 @@
 /* I2C driver configuration */
 #define CONFIG_HARD_I2C
 #define CONFIG_DW_I2C
+#if defined(CONFIG_SPEAR600)
+#define CONFIG_SYS_I2C_BASE			0xD0200000
+#elif defined(CONFIG_SPEAR300)
+#define CONFIG_SYS_I2C_BASE			0xD0180000
+#elif defined(CONFIG_SPEAR310)
+#define CONFIG_SYS_I2C_BASE			0xD0180000
+#elif defined(CONFIG_SPEAR320)
+#define CONFIG_SYS_I2C_BASE			0xD0180000
+#endif
 #define CONFIG_SYS_I2C_SPEED			400000
 #define CONFIG_SYS_I2C_SLAVE			0x02
 
 #define CONFIG_I2C_CHIPADDRESS			0x50
 
 /* Timer, HZ specific defines */
-#define CONFIG_SYS_HZ				1000
 
 /* Flash configuration */
 #if defined(CONFIG_FLASH_PNOR)
diff --git a/include/configs/spear6xx_evb.h b/include/configs/spear6xx_evb.h
index 7f4dc5801c..28dddcc5b9 100644
--- a/include/configs/spear6xx_evb.h
+++ b/include/configs/spear6xx_evb.h
@@ -37,6 +37,9 @@
 #define CONFIG_SYS_FSMC_NAND_8BIT
 #define CONFIG_SYS_NAND_BASE			0xD2000000
 
+/* Ethernet PHY configuration */
+#define CONFIG_PHY_NATSEMI
+
 /* Environment Settings */
 #define CONFIG_EXTRA_ENV_SETTINGS              CONFIG_EXTRA_ENV_USBTTY
 
diff --git a/include/configs/spieval.h b/include/configs/spieval.h
deleted file mode 100644
index 231263f2b5..0000000000
--- a/include/configs/spieval.h
+++ /dev/null
@@ -1,497 +0,0 @@
-/*
- * (C) Copyright 2003-2005
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * (C) Copyright 2004-2005
- * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_MPC5xxx		1	/* This is an MPC5xxx CPU */
-#define CONFIG_MPC5200		1	/* (more precisely an MPC5200 CPU) */
-#define CONFIG_TQM5200		1	/* ... on TQM5200 module */
-#undef CONFIG_TQM5200_REV100		/*  define for revision 100 modules */
-#define CONFIG_STK52XX		1	/* ... on a STK52XX base board */
-#define CONFIG_STK52XX_REV100	1	/*  define for revision 100 baseboards */
-
-#define CONFIG_SYS_MPC5XXX_CLKIN	33000000 /* ... running at 33.000000MHz */
-
-#define CONFIG_HIGH_BATS	1	/* High BATs supported */
-
-/*
- * Serial console configuration
- */
-#define CONFIG_PSC_CONSOLE	6	/* console is on PSC6 */
-#define CONFIG_BAUDRATE		115200	/* ... at 115200 bps */
-#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
-
-#ifdef CONFIG_STK52XX
-#undef CONFIG_PS2KBD			/* AT-PS/2 Keyboard		*/
-#define CONFIG_PS2MULT			/* .. on PS/2 Multiplexer	*/
-#define CONFIG_PS2SERIAL	6	/* .. on PSC6			*/
-#define CONFIG_PS2MULT_DELAY	(CONFIG_SYS_HZ/2)	/* Initial delay	*/
-#define CONFIG_BOARD_EARLY_INIT_R
-#endif /* CONFIG_STK52XX */
-
-/*
- * PCI Mapping:
- * 0x40000000 - 0x4fffffff - PCI Memory
- * 0x50000000 - 0x50ffffff - PCI IO Space
- */
-#ifdef CONFIG_STK52XX
-#define CONFIG_PCI		1
-#define CONFIG_PCI_PNP		1
-/* #define CONFIG_PCI_SCAN_SHOW	1 */
-
-#define CONFIG_PCI_MEM_BUS	0x40000000
-#define CONFIG_PCI_MEM_PHYS	CONFIG_PCI_MEM_BUS
-#define CONFIG_PCI_MEM_SIZE	0x10000000
-
-#define CONFIG_PCI_IO_BUS	0x50000000
-#define CONFIG_PCI_IO_PHYS	CONFIG_PCI_IO_BUS
-#define CONFIG_PCI_IO_SIZE	0x01000000
-
-#define CONFIG_EEPRO100		1
-#define CONFIG_SYS_RX_ETH_BUFFER	8  /* use 8 rx buffer on eepro100  */
-#define CONFIG_NS8382X		1
-#endif	/* CONFIG_STK52XX */
-
-/*
- * Video console
- */
-#if 1
-#define CONFIG_VIDEO
-#define CONFIG_VIDEO_SM501
-#define CONFIG_VIDEO_SM501_32BPP
-#define CONFIG_CFB_CONSOLE
-#define CONFIG_VIDEO_LOGO
-#define CONFIG_VGA_AS_SINGLE_DEVICE
-#define CONFIG_CONSOLE_EXTRA_INFO
-#define CONFIG_VIDEO_SW_CURSOR
-#define CONFIG_SPLASH_SCREEN
-#define CONFIG_SYS_CONSOLE_IS_IN_ENV
-#endif
-
-/* Partitions */
-#define CONFIG_MAC_PARTITION
-#define CONFIG_DOS_PARTITION
-#define CONFIG_ISO_PARTITION
-
-/* USB */
-#ifdef CONFIG_STK52XX
-#define CONFIG_USB_OHCI
-#define CONFIG_USB_STORAGE
-#endif
-
-/* POST support */
-#define CONFIG_POST		(CONFIG_SYS_POST_MEMORY   | \
-				 CONFIG_SYS_POST_CPU	   | \
-				 CONFIG_SYS_POST_I2C)
-
-#ifdef CONFIG_POST
-/* preserve space for the post_word at end of on-chip SRAM */
-#define MPC5XXX_SRAM_POST_SIZE MPC5XXX_SRAM_SIZE-4
-#endif
-
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_ASKENV
-#define CONFIG_CMD_DATE
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_ECHO
-#define CONFIG_CMD_EEPROM
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_MII
-#define CONFIG_CMD_NFS
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_REGINFO
-#define CONFIG_CMD_SNTP
-
-#if defined(CONFIG_MINIFAP) || defined(CONFIG_STK52XX)
-    #define CONFIG_CMD_IDE
-    #define CONFIG_CMD_FAT
-    #define CONFIG_CMD_EXT2
-#endif
-
-#ifdef CONFIG_STK52XX
-    #define CONFIG_CMD_USB
-    #define CONFIG_CMD_FAT
-#endif
-
-#ifdef CONFIG_VIDEO
-    #define CONFIG_CMD_BMP
-#endif
-
-#ifdef CONFIG_PCI
-    #define CONFIG_CMD_PCI
-    #define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE	1
-#endif
-
-#ifdef CONFIG_POST
-#define CONFIG_CMD_DIAG
-#endif
-
-
-#define	CONFIG_TIMESTAMP		/* display image timestamps */
-
-#if (CONFIG_SYS_TEXT_BASE == 0xFC000000)		/* Boot low */
-#   define CONFIG_SYS_LOWBOOT		1
-#endif
-
-/*
- * Autobooting
- */
-#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds */
-
-#define CONFIG_PREBOOT	"echo;" \
-	"echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
-	"echo"
-
-#undef	CONFIG_BOOTARGS
-
-#define CONFIG_EXTRA_ENV_SETTINGS					\
-	"netdev=eth0\0"							\
-	"rootpath=/opt/eldk/ppc_6xx\0"					\
-	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
-	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
-		"nfsroot=${serverip}:${rootpath}\0"			\
-	"addip=setenv bootargs ${bootargs} "				\
-		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
-		":${hostname}:${netdev}:off panic=1\0"			\
-	"flash_self=run ramargs addip;"					\
-		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
-	"flash_nfs=run nfsargs addip;"					\
-		"bootm ${kernel_addr}\0"				\
-	"net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0"	\
-	"bootfile=/tftpboot/tqm5200/uImage\0"				\
-	"load=tftp 200000 ${u-boot}\0"					\
-	"u-boot=/tftpboot/tqm5200/u-boot.bin\0"				\
-	"update=protect off FC000000 FC05FFFF;"				\
-		"erase FC000000 FC05FFFF;"				\
-		"cp.b 200000 FC000000 ${filesize};"			\
-		"protect on FC000000 FC05FFFF\0"			\
-	""
-
-#define CONFIG_BOOTCOMMAND	"run net_nfs"
-
-/*
- * IPB Bus clocking configuration.
- */
-#define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK		/* define for 133MHz speed */
-
-#if defined(CONFIG_SYS_IPBCLK_EQUALS_XLBCLK)
-/*
- * PCI Bus clocking configuration
- *
- * Actually a PCI Clock of 66 MHz is only set (in cpu_init.c) if
- * CONFIG_SYS_IPBCLK_EQUALS_XLBCLK is defined. This is because a PCI Clock
- * of 66 MHz yet hasn't been tested with a IPB Bus Clock of 66 MHz.
- */
-#define CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2	/* define for 66MHz speed */
-#endif
-
-/*
- * I2C configuration
- */
-#define CONFIG_HARD_I2C		1	/* I2C with hardware support */
-#ifdef CONFIG_TQM5200_REV100
-#define CONFIG_SYS_I2C_MODULE		1	/* Select I2C module #1 for rev. 100 board */
-#else
-#define CONFIG_SYS_I2C_MODULE		2	/* Select I2C module #2 for all other revs */
-#endif
-
-/*
- * I2C clock frequency
- *
- * Please notice, that the resulting clock frequency could differ from the
- * configured value. This is because the I2C clock is derived from system
- * clock over a frequency divider with only a few divider values. U-boot
- * calculates the best approximation for CONFIG_SYS_I2C_SPEED. However the calculated
- * approximation allways lies below the configured value, never above.
- */
-#define CONFIG_SYS_I2C_SPEED		100000 /* 100 kHz */
-#define CONFIG_SYS_I2C_SLAVE		0x7F
-
-/*
- * EEPROM configuration for onboard EEPROM M24C32 (M24C64 should work
- * also). For other EEPROMs configuration should be verified. On Mini-FAP the
- * EEPROM (24C64) is on the same I2C address (but on other I2C bus), so the
- * same configuration could be used.
- */
-#define CONFIG_SYS_I2C_EEPROM_ADDR		0x50	/* 1010000x */
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		2
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	5	/* =32 Bytes per write */
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	20
-
-/*
- * HW-Monitor configuration on Mini-FAP
- */
-#if defined (CONFIG_MINIFAP)
-#define CONFIG_SYS_I2C_HWMON_ADDR		0x2C
-#endif
-
-/* List of I2C addresses to be verified by POST */
-#if defined (CONFIG_MINIFAP)
-#undef CONFIG_SYS_POST_I2C_ADDRS
-#define CONFIG_SYS_POST_I2C_ADDRS	{CONFIG_SYS_I2C_EEPROM_ADDR,	\
-					 CONFIG_SYS_I2C_HWMON_ADDR,	\
-					 CONFIG_SYS_I2C_SLAVE}
-#endif
-
-/*
- * Flash configuration
- */
-#define CONFIG_SYS_FLASH_BASE		CONFIG_SYS_TEXT_BASE /* 0xFC000000 */
-
-/* use CFI flash driver if no module variant is spezified */
-#define CONFIG_SYS_FLASH_CFI		1	/* Flash is CFI conformant */
-#define CONFIG_FLASH_CFI_DRIVER	1	/* Use the common driver */
-#define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_BOOTCS_START }
-#define CONFIG_SYS_FLASH_EMPTY_INFO
-#define CONFIG_SYS_FLASH_SIZE		0x04000000 /* 64 MByte */
-#define CONFIG_SYS_MAX_FLASH_SECT	512	/* max num of sects on one chip */
-#undef CONFIG_SYS_FLASH_USE_BUFFER_WRITE	/* not supported yet for AMD */
-
-#if !defined(CONFIG_SYS_LOWBOOT)
-#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + 0x00760000 + 0x00800000)
-#else	/* CONFIG_SYS_LOWBOOT */
-#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + 0x00060000)
-#endif	/* CONFIG_SYS_LOWBOOT */
-#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max num of flash banks
-					   (= chip selects) */
-#define CONFIG_SYS_FLASH_ERASE_TOUT	240000	/* Flash Erase Timeout (in ms)	*/
-#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (in ms)	*/
-
-
-/*
- * Environment settings
- */
-#define CONFIG_ENV_IS_IN_FLASH	1
-#define CONFIG_ENV_SIZE		0x10000
-#define CONFIG_ENV_SECT_SIZE	0x20000
-#define CONFIG_ENV_ADDR_REDUND	(CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
-#define	CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SIZE)
-
-/*
- * Memory map
- */
-#define CONFIG_SYS_MBAR		0xF0000000
-#define CONFIG_SYS_SDRAM_BASE		0x00000000
-#define CONFIG_SYS_DEFAULT_MBAR	0x80000000
-
-/* Use ON-Chip SRAM until RAM will be available */
-#define CONFIG_SYS_INIT_RAM_ADDR	MPC5XXX_SRAM
-#ifdef CONFIG_POST
-/* preserve space for the post_word at end of on-chip SRAM */
-#define CONFIG_SYS_INIT_RAM_SIZE	MPC5XXX_SRAM_POST_SIZE
-#else
-#define CONFIG_SYS_INIT_RAM_SIZE	MPC5XXX_SRAM_SIZE
-#endif
-
-
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
-
-#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE
-#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
-#   define CONFIG_SYS_RAMBOOT		1
-#endif
-
-#define CONFIG_SYS_MONITOR_LEN		(384 << 10)	/* Reserve 384 kB for Monitor	*/
-#define CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
-#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
-
-/*
- * Ethernet configuration
- */
-#define CONFIG_MPC5xxx_FEC	1
-/*
- * Define CONFIG_FEC_10MBIT to force FEC at 10Mb
- */
-/* #define CONFIG_FEC_10MBIT 1 */
-#define CONFIG_PHY_ADDR		0x00
-
-/*
- * GPIO configuration
- *
- * use pin gpio_wkup_6 as second SDRAM chip select (mem_cs1):
- *	Bit 0 (mask: 0x80000000): 1
- * use ALT CAN position: Bits 2-3 (mask: 0x30000000):
- *	00 -> No Alternatives, CAN1/2 on PSC2 according to PSC2 setting.
- *	01 -> CAN1 on I2C1, CAN2 on Tmr0/1.
- *	      Use for REV200 STK52XX boards. Do not use with REV100 modules
- *	      (because, there I2C1 is used as I2C bus)
- * use PSC1 as UART: Bits 28-31 (mask: 0x00000007): 0100
- * use PSC2 as CAN: Bits 25:27 (mask: 0x00000030)
- *	000 -> All PSC2 pins are GIOPs
- *	001 -> CAN1/2 on PSC2 pins
- *	       Use for REV100 STK52xx boards
- * use PSC6:
- *   on STK52xx:
- *	use as UART. Pins PSC6_0 to PSC6_3 are used.
- *	Bits 9:11 (mask: 0x00700000):
- *	   101 -> PSC6 : Extended POST test is not available
- *   on MINI-FAP and TQM5200_IB:
- *	use PSC6_0 to PSC6_3 as GPIO: Bits 9:11 (mask: 0x00700000):
- *	   000 -> PSC6 could not be used as UART, CODEC or IrDA
- *   GPIO on PSC6_3 is used in post_hotkeys_pressed() to enable extended POST
- *   tests.
- */
-#if defined (CONFIG_MINIFAP)
-# define CONFIG_SYS_GPS_PORT_CONFIG	0x91000004
-#elif defined (CONFIG_STK52XX)
-# if defined (CONFIG_STK52XX_REV100)
-#  define CONFIG_SYS_GPS_PORT_CONFIG	0x81500014
-# else /* STK52xx REV200 and above */
-#  if defined (CONFIG_TQM5200_REV100)
-#   error TQM5200 REV100 not supported on STK52XX REV200 or above
-#  else/* TQM5200 REV200 and above */
-#   define CONFIG_SYS_GPS_PORT_CONFIG	0x91500004
-#  endif
-# endif
-#else  /* TMQ5200 Inbetriebnahme-Board */
-# define CONFIG_SYS_GPS_PORT_CONFIG	0x81000004
-#endif
-
-/*
- * RTC configuration
- */
-#define CONFIG_RTC_MPC5200	1	/* use internal MPC5200 RTC */
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP			/* undef to save memory	    */
-#define CONFIG_SYS_PROMPT		"=> "	/* Monitor Command Prompt   */
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size  */
-#else
-#define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size  */
-#endif
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS		16	/* max number of command args	*/
-#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
-
-/* Enable an alternate, more extensive memory test */
-#define CONFIG_SYS_ALT_MEMTEST
-
-#define CONFIG_SYS_MEMTEST_START	0x00100000	/* memtest works on */
-#define CONFIG_SYS_MEMTEST_END		0x00f00000	/* 1 ... 15 MB in DRAM	*/
-
-#define CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address */
-
-#define CONFIG_SYS_HZ			1000	/* decrementer freq: 1 ms ticks */
-
-#define CONFIG_SYS_CACHELINE_SIZE	32	/* For MPC5xxx CPUs */
-#if defined(CONFIG_CMD_KGDB)
-#  define CONFIG_SYS_CACHELINE_SHIFT	5	/* log base 2 of the above value */
-#endif
-
-/*
- * Enable loopw command.
- */
-#define CONFIG_LOOPW
-
-/*
- * Various low-level settings
- */
-#define CONFIG_SYS_HID0_INIT		HID0_ICE | HID0_ICFI
-#define CONFIG_SYS_HID0_FINAL		HID0_ICE
-
-#define CONFIG_SYS_BOOTCS_START	CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_BOOTCS_SIZE		CONFIG_SYS_FLASH_SIZE
-#ifdef CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2
-#define CONFIG_SYS_BOOTCS_CFG		0x0008DF30 /* for pci_clk  = 66 MHz */
-#else
-#define CONFIG_SYS_BOOTCS_CFG		0x0004DF30 /* for pci_clk = 33 MHz */
-#endif
-#define CONFIG_SYS_CS0_START		CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_CS0_SIZE		CONFIG_SYS_FLASH_SIZE
-
-#define CONFIG_LAST_STAGE_INIT
-
-/*
- * SRAM - Do not map below 2 GB in address space, because this area is used
- * for SDRAM autosizing.
- */
-#define CONFIG_SYS_CS2_START		0xE5000000
-#define CONFIG_SYS_CS2_SIZE		0x100000	/* 1 MByte */
-#define CONFIG_SYS_CS2_CFG		0x0004D930
-
-/*
- * Grafic controller - Do not map below 2 GB in address space, because this
- * area is used for SDRAM autosizing.
- */
-#define SM501_FB_BASE		0xE0000000
-#define CONFIG_SYS_CS1_START		(SM501_FB_BASE)
-#define CONFIG_SYS_CS1_SIZE		0x4000000	/* 64 MByte */
-#define CONFIG_SYS_CS1_CFG		0x8F48FF70
-#define SM501_MMIO_BASE		CONFIG_SYS_CS1_START + 0x03E00000
-
-#define CONFIG_SYS_CS_BURST		0x00000000
-#define CONFIG_SYS_CS_DEADCYCLE	0x33333311	/* 1 dead cycle for flash and SM501 */
-
-#define CONFIG_SYS_RESET_ADDRESS	0xff000000
-
-/*-----------------------------------------------------------------------
- * USB stuff
- *-----------------------------------------------------------------------
- */
-#define CONFIG_USB_CLOCK	0x0001BBBB
-#define CONFIG_USB_CONFIG	0x00001000
-
-/*-----------------------------------------------------------------------
- * IDE/ATA stuff Supports IDE harddisk
- *-----------------------------------------------------------------------
- */
-
-#undef	CONFIG_IDE_8xx_PCCARD		/* Use IDE with PC Card Adapter */
-
-#undef	CONFIG_IDE_8xx_DIRECT		/* Direct IDE	 not supported	*/
-#undef	CONFIG_IDE_LED			/* LED	 for ide not supported	*/
-
-#define CONFIG_IDE_RESET		/* reset for ide supported	*/
-#define CONFIG_IDE_PREINIT
-
-#define CONFIG_SYS_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
-#define CONFIG_SYS_IDE_MAXDEVICE	2	/* max. 2 drives per IDE bus	*/
-
-#define CONFIG_SYS_ATA_IDE0_OFFSET	0x0000
-
-#define CONFIG_SYS_ATA_BASE_ADDR	MPC5XXX_ATA
-
-/* Offset for data I/O			*/
-#define CONFIG_SYS_ATA_DATA_OFFSET	(0x0060)
-
-/* Offset for normal register accesses	*/
-#define CONFIG_SYS_ATA_REG_OFFSET	(CONFIG_SYS_ATA_DATA_OFFSET)
-
-/* Offset for alternate registers	*/
-#define CONFIG_SYS_ATA_ALT_OFFSET	(0x005C)
-
-/* Interval between registers						     */
-#define CONFIG_SYS_ATA_STRIDE		4
-
-#endif /* __CONFIG_H */
diff --git a/include/configs/stamp9g20.h b/include/configs/stamp9g20.h
index a9973315c2..01085dc5c1 100644
--- a/include/configs/stamp9g20.h
+++ b/include/configs/stamp9g20.h
@@ -35,7 +35,6 @@
 /* ARM asynchronous clock */
 #define CONFIG_SYS_AT91_SLOW_CLOCK	32768		/* slow clock xtal */
 #define CONFIG_SYS_AT91_MAIN_CLOCK	18432000	/* 18.432MHz crystal */
-#define CONFIG_SYS_HZ			1000		/* 1ms resolution */
 
 /* misc settings */
 #define CONFIG_CMDLINE_TAG		/* pass commandline to Kernel */
@@ -141,11 +140,15 @@
  * can enable it here if your baseboard features ethernet.
  */
 
-/* #define CONFIG_MACB */
+#define CONFIG_MACB
+#define CONFIG_USB_HOST_ETHER
+#define CONFIG_USB_ETHER_ASIX
+#define CONFIG_USB_ETHER_MCS7830
 
 #ifdef CONFIG_MACB
 # define CONFIG_RMII			/* use reduced MII inteface */
 # define CONFIG_NET_RETRY_COUNT	20      /* # of DHCP/BOOTP retries */
+#define CONFIG_AT91_WANTS_COMMON_PHY
 
 /* BOOTP and DHCP options */
 # define CONFIG_BOOTP_BOOTFILESIZE
@@ -165,6 +168,7 @@
 
 /* USB configuration */
 #define CONFIG_USB_ATMEL
+#define CONFIG_USB_ATMEL_CLK_SEL_PLLB
 #define CONFIG_USB_OHCI_NEW
 #define CONFIG_USB_STORAGE
 #define CONFIG_DOS_PARTITION
diff --git a/include/configs/stxgp3.h b/include/configs/stxgp3.h
index 100dae742e..5fb40ebf8b 100644
--- a/include/configs/stxgp3.h
+++ b/include/configs/stxgp3.h
@@ -22,7 +22,6 @@
 /* High Level Configuration Options */
 #define CONFIG_BOOKE		1	/* BOOKE		*/
 #define CONFIG_E500		1	/* BOOKE e500 family	*/
-#define CONFIG_MPC85xx		1	/* MPC8540/MPC8560	*/
 #define CONFIG_CPM2		1	/* has CPM2 */
 #define CONFIG_STXGP3		1	/* Silicon Tx GPPP board specific*/
 #define CONFIG_MPC8560		1
@@ -98,7 +97,7 @@
 #define CONFIG_SYS_CCSRBAR_PHYS_LOW	CONFIG_SYS_CCSRBAR
 
 /* DDR Setup */
-#define CONFIG_FSL_DDR1
+#define CONFIG_SYS_FSL_DDR1
 #define CONFIG_SPD_EEPROM		/* Use SPD EEPROM for DDR setup*/
 #define CONFIG_DDR_SPD
 #undef CONFIG_FSL_DDR_INTERACTIVE
@@ -331,7 +330,6 @@
 #define CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
 #define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
 #define CONFIG_SYS_LOAD_ADDR	0x1000000	/* default load address */
-#define CONFIG_SYS_HZ		1000		/* decrementer freq: 1 ms ticks */
 
 /*
  * For booting Linux, the board info and command line data
@@ -342,7 +340,6 @@
 
 #if defined(CONFIG_CMD_KGDB)
 #define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
-#define CONFIG_KGDB_SER_INDEX	2	/* which serial port to use */
 #endif
 
 /*Note: change below for your network setting!!! */
diff --git a/include/configs/stxssa.h b/include/configs/stxssa.h
index e82a4b1c6f..914d821905 100644
--- a/include/configs/stxssa.h
+++ b/include/configs/stxssa.h
@@ -22,7 +22,6 @@
 /* High Level Configuration Options */
 #define CONFIG_BOOKE		1	/* BOOKE		*/
 #define CONFIG_E500		1	/* BOOKE e500 family	*/
-#define CONFIG_MPC85xx		1	/* MPC8540/MPC8560	*/
 #define CONFIG_CPM2		1	/* has CPM2 */
 #define CONFIG_STXSSA		1	/* Silicon Tx GPPP SSA board specific*/
 #define CONFIG_MPC8560		1
@@ -112,7 +111,7 @@
 #define CONFIG_SYS_CCSRBAR_PHYS_LOW	CONFIG_SYS_CCSRBAR
 
 /* DDR Setup */
-#define CONFIG_FSL_DDR1
+#define CONFIG_SYS_FSL_DDR1
 #define CONFIG_SPD_EEPROM		/* Use SPD EEPROM for DDR setup*/
 #define CONFIG_DDR_SPD
 #undef CONFIG_FSL_DDR_INTERACTIVE
@@ -366,7 +365,6 @@
 #define CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
 #define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
 #define CONFIG_SYS_LOAD_ADDR	0x1000000	/* default load address */
-#define CONFIG_SYS_HZ		1000		/* decrementer freq: 1 ms ticks */
 
 /*
  * For booting Linux, the board info and command line data
@@ -377,7 +375,6 @@
 
 #if defined(CONFIG_CMD_KGDB)
 #define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
-#define CONFIG_KGDB_SER_INDEX	2	/* which serial port to use */
 #endif
 
 /*Note: change below for your network setting!!! */
diff --git a/include/configs/stxxtc.h b/include/configs/stxxtc.h
index ead67453b9..4e3b7277f4 100644
--- a/include/configs/stxxtc.h
+++ b/include/configs/stxxtc.h
@@ -132,8 +132,6 @@
 
 #define	CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address	*/
 
-#define	CONFIG_SYS_HZ		1000		/* decrementer freq: 1 ms ticks	*/
-
 /*
  * Low Level Configuration Settings
  * (address mappings, register initial values, etc.)
diff --git a/include/configs/svm_sc8xx.h b/include/configs/svm_sc8xx.h
index a6c1f9927b..b4aa948565 100644
--- a/include/configs/svm_sc8xx.h
+++ b/include/configs/svm_sc8xx.h
@@ -140,7 +140,6 @@
  * Miscellaneous configurable options
  */
 #define	CONFIG_SYS_LONGHELP			/* undef to save memory		*/
-#define	CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt	*/
 
 #ifdef  CONFIG_SYS_HUSH_PARSER
 #endif
@@ -159,8 +158,6 @@
 
 #define	CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address	*/
 
-#define	CONFIG_SYS_HZ		1000		/* decrementer freq: 1 ms ticks	*/
-
 /*
  * Low Level Configuration Settings
  * (address mappings, register initial values, etc.)
diff --git a/include/configs/t3corp.h b/include/configs/t3corp.h
index 9ab99244cf..502e795976 100644
--- a/include/configs/t3corp.h
+++ b/include/configs/t3corp.h
@@ -16,7 +16,6 @@
  */
 #define CONFIG_460GT		1	/* Specific PPC460GT	*/
 #define CONFIG_440		1
-#define CONFIG_4xx		1	/* ... PPC4xx family */
 
 #ifndef CONFIG_SYS_TEXT_BASE
 #define CONFIG_SYS_TEXT_BASE	0xFFFA0000
diff --git a/include/configs/t4qds.h b/include/configs/t4qds.h
index 3e82fc2558..bd324ba2fa 100644
--- a/include/configs/t4qds.h
+++ b/include/configs/t4qds.h
@@ -17,11 +17,10 @@
 #define CONFIG_E500			/* BOOKE e500 family */
 #define CONFIG_E500MC			/* BOOKE e500mc family */
 #define CONFIG_SYS_BOOK3E_HV		/* Category E.HV supported */
-#define CONFIG_MPC85xx			/* MPC85xx/PQ3 platform */
 #define CONFIG_MP			/* support multiple processors */
 
 #ifndef CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_TEXT_BASE	0xeff80000
+#define CONFIG_SYS_TEXT_BASE	0xeff40000
 #endif
 
 #ifndef CONFIG_RESET_VECTOR_ADDRESS
@@ -87,7 +86,7 @@
 #define CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
 
 #define CONFIG_DDR_SPD
-#define CONFIG_FSL_DDR3
+#define CONFIG_SYS_FSL_DDR3
 
 
 /*
@@ -284,7 +283,6 @@
 #define CONFIG_CMDLINE_EDITING			/* Command-line editing */
 #define CONFIG_AUTO_COMPLETE			/* add autocompletion support */
 #define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
-#define CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt */
 #ifdef CONFIG_CMD_KGDB
 #define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size */
 #else
@@ -293,7 +291,6 @@
 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
 #define CONFIG_SYS_MAXARGS	16		/* max number of command args */
 #define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
-#define CONFIG_SYS_HZ		1000		/* decrementer freq: 1ms ticks*/
 
 /*
  * For booting Linux, the board info and command line data
@@ -305,7 +302,6 @@
 
 #ifdef CONFIG_CMD_KGDB
 #define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
-#define CONFIG_KGDB_SER_INDEX	2	/* which serial port to use */
 #endif
 
 /*
diff --git a/include/configs/taihu.h b/include/configs/taihu.h
index 4ebaf2e2a5..5c0ce7a2e4 100644
--- a/include/configs/taihu.h
+++ b/include/configs/taihu.h
@@ -13,7 +13,6 @@
 
 
 #define CONFIG_405EP		1	/* this is a PPC405 CPU */
-#define CONFIG_4xx		1	/*  member of PPC4xx family */
 #define CONFIG_TAIHU	        1	/*  on a taihu board */
 
 #define	CONFIG_SYS_TEXT_BASE	0xFFFC0000
diff --git a/include/configs/taishan.h b/include/configs/taishan.h
index 3dbfc6ad1d..3d5c351b1a 100644
--- a/include/configs/taishan.h
+++ b/include/configs/taishan.h
@@ -18,7 +18,6 @@
 #define CONFIG_TAISHAN		1	/* Board is taishan		*/
 #define CONFIG_440GX		1	/* Specifc GX support		*/
 #define CONFIG_440		1	/* ... PPC440 family		*/
-#define CONFIG_4xx		1	/* ... PPC4xx family		*/
 #define CONFIG_SYS_CLK_FREQ	33333333 /* external freq to pll	*/
 
 #define	CONFIG_SYS_TEXT_BASE	0xFFFC0000
diff --git a/include/configs/tam3517-common.h b/include/configs/tam3517-common.h
index 60dd8ff11a..3522c1a07a 100644
--- a/include/configs/tam3517-common.h
+++ b/include/configs/tam3517-common.h
@@ -117,14 +117,13 @@
 #undef CONFIG_CMD_IMLS
 
 #define CONFIG_SYS_NO_FLASH
-#define CONFIG_HARD_I2C
-#define CONFIG_SYS_I2C_SPEED		400000
-#define CONFIG_SYS_I2C_SLAVE		1
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_OMAP24_I2C_SPEED	400000
+#define CONFIG_SYS_OMAP24_I2C_SLAVE	1
+#define CONFIG_SYS_I2C_OMAP34XX
 #define CONFIG_SYS_I2C_EEPROM_ADDR	0x50		/* base address */
 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	1		/* bytes of address */
 #define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW	0x07
-#define CONFIG_DRIVER_OMAP34XX_I2C
-
 
 /*
  * Board NAND Info.
@@ -169,7 +168,6 @@
  */
 #define CONFIG_SYS_TIMERBASE		OMAP34XX_GPT2
 #define CONFIG_SYS_PTV			2	/* Divisor: 2^(PTV+1) => 8 */
-#define CONFIG_SYS_HZ			1000
 
 /*
  * Physical Memory Map
@@ -188,7 +186,6 @@
 #define PISMO1_NAND_SIZE		GPMC_SIZE_128M
 
 #define CONFIG_NAND_OMAP_GPMC
-#define GPMC_NAND_ECC_LP_x16_LAYOUT
 #define CONFIG_ENV_IS_IN_NAND
 #define SMNAND_ENV_OFFSET		0x180000 /* environment starts here */
 
@@ -263,6 +260,7 @@
 					 56, 57, 58, 59, 60, 61, 62, 63}
 #define CONFIG_SYS_NAND_ECCSIZE		256
 #define CONFIG_SYS_NAND_ECCBYTES	3
+#define CONFIG_NAND_OMAP_ECCSCHEME	OMAP_ECC_HAM1_CODE_SW
 
 #define CONFIG_SYS_NAND_U_BOOT_START	CONFIG_SYS_TEXT_BASE
 
@@ -370,7 +368,7 @@ struct tam3517_module_info {
 
 #define TAM3517_READ_EEPROM(info, ret) \
 do {								\
-	i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);	\
+	i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE); \
 	if (eeprom_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0,		\
 		(void *)info, sizeof(*info)))			\
 		ret = 1;					\
diff --git a/include/configs/tao3530.h b/include/configs/tao3530.h
new file mode 100644
index 0000000000..9c04c23ab7
--- /dev/null
+++ b/include/configs/tao3530.h
@@ -0,0 +1,370 @@
+/*
+ * Configuration settings for the TechNexion TAO-3530 SOM
+ * equipped on Thunder baseboard.
+ *
+ * Edward Lin <linuxfae@technexion.com>
+ * Tapani Utriainen <linuxfae@technexion.com>
+ *
+ * Copyright (C) 2013 Stefan Roese <sr@denx.de>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_ARMV7			/* This is an ARM V7 CPU core */
+#define CONFIG_OMAP			/* in a TI OMAP core */
+#define CONFIG_OMAP34XX			/* which is a 34XX */
+
+#define CONFIG_OMAP_GPIO
+#define CONFIG_OMAP_COMMON
+
+#define MACH_TYPE_OMAP3_TAO3530		2836
+
+#define CONFIG_SDRC			/* Has an SDRC controller */
+
+#include <asm/arch/cpu.h>		/* get chip and board defs */
+#include <asm/arch/omap3.h>
+
+/*
+ * Display CPU and Board information
+ */
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DISPLAY_BOARDINFO
+
+/* Clock Defines */
+#define V_OSCK			26000000	/* Clock output from T2 */
+#define V_SCLK			(V_OSCK >> 1)
+
+#define CONFIG_MISC_INIT_R
+
+#define CONFIG_OF_LIBFDT
+
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+#define CONFIG_REVISION_TAG
+
+/*
+ * Size of malloc() pool
+ */
+#define CONFIG_SYS_MALLOC_LEN		(4 << 20)
+#define CONFIG_ENV_SIZE			(128 << 10)	/* 128 KiB sector */
+
+/*
+ * Hardware drivers
+ */
+
+/*
+ * NS16550 Configuration
+ */
+#define V_NS16550_CLK			48000000	/* 48MHz (APLL96/2) */
+
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	(-4)
+#define CONFIG_SYS_NS16550_CLK		V_NS16550_CLK
+
+/*
+ * select serial console configuration
+ */
+#define CONFIG_CONS_INDEX		3
+#define CONFIG_SYS_NS16550_COM3		OMAP34XX_UART3
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_BAUDRATE			115200
+#define CONFIG_GENERIC_MMC
+#define CONFIG_MMC
+#define CONFIG_OMAP_HSMMC
+#define CONFIG_DOS_PARTITION
+
+/* GPIO banks */
+#define CONFIG_OMAP3_GPIO_2		/* GPIO32 ..63  is in GPIO bank 2 */
+#define CONFIG_OMAP3_GPIO_3		/* GPIO64 ..95  is in GPIO bank 3 */
+#define CONFIG_OMAP3_GPIO_4		/* GPIO96 ..127 is in GPIO bank 4 */
+#define CONFIG_OMAP3_GPIO_5		/* GPIO128..159 is in GPIO bank 5 */
+#define CONFIG_OMAP3_GPIO_6		/* GPIO160..191 is in GPIO bank 6 */
+
+/* commands to include */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_EXT2		/* EXT2 Support			*/
+#define CONFIG_CMD_FAT		/* FAT support			*/
+#define CONFIG_CMD_MTDPARTS	/* Enable MTD parts commands */
+#define CONFIG_MTD_DEVICE	/* needed for mtdparts commands */
+#define MTDIDS_DEFAULT			"nand0=nand"
+#define MTDPARTS_DEFAULT		"mtdparts=nand:512k(x-loader),"\
+					"1920k(u-boot),128k(u-boot-env),"\
+					"4m(kernel),-(fs)"
+
+#define CONFIG_CMD_I2C		/* I2C serial bus support	*/
+#define CONFIG_CMD_MMC		/* MMC support			*/
+#define CONFIG_CMD_NAND		/* NAND support			*/
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_PING
+
+#undef CONFIG_CMD_FLASH		/* flinfo, erase, protect	*/
+#undef CONFIG_CMD_FPGA		/* FPGA configuration Support	*/
+#undef CONFIG_CMD_IMI		/* iminfo			*/
+#undef CONFIG_CMD_IMLS		/* List all found images	*/
+
+#define CONFIG_SYS_NO_FLASH
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_OMAP34XX
+#define CONFIG_SYS_OMAP24_I2C_SPEED	100000
+#define CONFIG_SYS_OMAP24_I2C_SLAVE	1
+#define CONFIG_I2C_MULTI_BUS
+
+/*
+ * TWL4030
+ */
+#define CONFIG_TWL4030_POWER
+#define CONFIG_TWL4030_LED
+
+/*
+ * Board NAND Info.
+ */
+#define CONFIG_SYS_NAND_QUIET_TEST
+#define CONFIG_NAND_OMAP_GPMC
+#define CONFIG_SYS_NAND_ADDR		NAND_BASE	/* physical address */
+							/* to access nand */
+#define CONFIG_SYS_NAND_BASE		NAND_BASE	/* physical address */
+							/* to access nand at */
+							/* CS0 */
+#define GPMC_NAND_ECC_LP_x16_LAYOUT
+
+#define CONFIG_SYS_MAX_NAND_DEVICE	1		/* Max number of NAND */
+							/* devices */
+/* Environment information */
+#define CONFIG_BOOTDELAY		3
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"loadaddr=0x82000000\0" \
+	"console=ttyO2,115200n8\0" \
+	"mpurate=600\0" \
+	"dvi_mode=omapfb.mode=dvi:1280x720-24@60\0" \
+	"tv_mode=omapfb.mode=tv:ntsc\0" \
+	"video_mode=omapdss.def_disp=lcd vram=6M omapfb.vram=0:2M,1:2M,2:2M\0" \
+	"lcd_mode=omapfb.mode=lcd:800x480@60 \0" \
+	"extra_options= \0" \
+	"mmcdev=0\0" \
+	"mmcroot=/dev/mmcblk0p2 rw\0" \
+	"mmcrootfstype=ext3 rootwait\0" \
+	"nandroot=ubi0:rootfs ubi.mtd=4\0" \
+	"nandrootfstype=ubifs\0" \
+	"mmcargs=setenv bootargs console=${console} " \
+		"mpurate=${mpurate} " \
+		"${video_mode} " \
+		"root=${mmcroot} " \
+		"rootfstype=${mmcrootfstype} " \
+		"${extra_options}\0" \
+	"nandargs=setenv bootargs console=${console} " \
+		"mpurate=${mpurate} " \
+		"${video_mode} " \
+		"${network_setting} " \
+		"root=${nandroot} " \
+		"rootfstype=${nandrootfstype} "\
+		"${extra_options}\0" \
+	"loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
+	"bootscript=echo Running bootscript from mmc ...; " \
+		"source ${loadaddr}\0" \
+	"loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \
+	"mmcboot=echo Booting from mmc ...; " \
+		"run mmcargs; " \
+		"bootm ${loadaddr}\0" \
+	"nandboot=echo Booting from nand ...; " \
+		"run nandargs; " \
+		"nand read ${loadaddr} 280000 400000; " \
+		"bootm ${loadaddr}\0" \
+
+#define CONFIG_BOOTCOMMAND \
+	"if mmc rescan ${mmcdev}; then " \
+		"if run loadbootscript; then " \
+			"run bootscript; " \
+		"else " \
+			"if run loaduimage; then " \
+				"run mmcboot; " \
+			"else run nandboot; " \
+			"fi; " \
+		"fi; " \
+	"else run nandboot; fi"
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP		/* undef to save memory */
+#define CONFIG_SYS_HUSH_PARSER		/* use "hush" command parser */
+#define CONFIG_SYS_PROMPT		"TAO-3530 # "
+#define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size */
+
+/* turn on command-line edit/hist/auto */
+#define CONFIG_CMDLINE_EDITING
+#define CONFIG_COMMAND_HISTORY
+#define CONFIG_AUTO_COMPLETE
+
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
+					sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS		16	/* max number of command args */
+/* Boot Argument Buffer Size */
+#define CONFIG_SYS_BARGSIZE		(CONFIG_SYS_CBSIZE)
+
+#define CONFIG_SYS_ALT_MEMTEST		1
+#define CONFIG_SYS_MEMTEST_START	(0x82000000)		/* memtest */
+								/* defaults */
+#define CONFIG_SYS_MEMTEST_END		(0x83FFFFFF)		/* 64MB */
+#define CONFIG_SYS_MEMTEST_SCRATCH	(0x81000000)	/* dummy address */
+
+#define CONFIG_SYS_LOAD_ADDR		(OMAP34XX_SDRC_CS0)	/* default */
+							/* load address */
+#define CONFIG_SYS_TEXT_BASE		0x80008000
+
+/*
+ * OMAP3 has 12 GP timers, they can be driven by the system clock
+ * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
+ * This rate is divided by a local divisor.
+ */
+#define CONFIG_SYS_TIMERBASE		(OMAP34XX_GPT2)
+#define CONFIG_SYS_PTV			2       /* Divisor: 2^(PTV+1) => 8 */
+
+/*
+ * Stack sizes
+ *
+ * The stack sizes are set up in start.S using the settings below
+ */
+#define CONFIG_STACKSIZE	(128 << 10)	/* regular stack 128 KiB */
+
+/*
+ * Physical Memory Map
+ */
+#define CONFIG_NR_DRAM_BANKS	2	/* CS1 may or may not be populated */
+#define PHYS_SDRAM_1		OMAP34XX_SDRC_CS0
+#define PHYS_SDRAM_1_SIZE	(32 << 20)	/* at least 32 MiB */
+#define PHYS_SDRAM_2		OMAP34XX_SDRC_CS1
+
+/*
+ * FLASH and environment organization
+ */
+
+/* **** PISMO SUPPORT *** */
+
+/* Configure the PISMO */
+#define PISMO1_NAND_SIZE		GPMC_SIZE_128M
+#define PISMO1_ONEN_SIZE		GPMC_SIZE_128M
+
+#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 2 sectors */
+#define CONFIG_SYS_FLASH_BASE		PISMO1_NAND_BASE
+
+/* Monitor at start of flash */
+#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_ONENAND_BASE		ONENAND_MAP
+
+#define CONFIG_ENV_IS_IN_NAND		1
+#define ONENAND_ENV_OFFSET		0x260000 /* environment starts here */
+#define SMNAND_ENV_OFFSET		0x260000 /* environment starts here */
+
+#define CONFIG_SYS_ENV_SECT_SIZE	(128 << 10)
+#define CONFIG_ENV_OFFSET		SMNAND_ENV_OFFSET
+#define CONFIG_ENV_ADDR			CONFIG_ENV_OFFSET
+
+#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
+#define CONFIG_SYS_INIT_RAM_ADDR	0x4020f800
+#define CONFIG_SYS_INIT_RAM_SIZE	0x800
+#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_INIT_RAM_ADDR + \
+					 CONFIG_SYS_INIT_RAM_SIZE - \
+					 GENERATED_GBL_DATA_SIZE)
+
+#define CONFIG_OMAP3_SPI
+
+/*
+ * USB
+ *
+ * Currently only EHCI is enabled, the MUSB OTG controller
+ * is not enabled.
+ */
+
+/* USB EHCI */
+#define CONFIG_CMD_USB
+#define CONFIG_USB_EHCI
+#define CONFIG_USB_EHCI_OMAP
+#define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO	162
+
+#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3
+#define CONFIG_USB_HOST_ETHER
+#define CONFIG_USB_ETHER_SMSC95XX
+
+#define CONFIG_USB_ETHER
+#define CONFIG_USB_ETHER_RNDIS
+#define CONFIG_USB_STORAGE
+#define CONGIG_CMD_STORAGE
+
+/* Defines for SPL */
+#define CONFIG_SPL
+#define CONFIG_SPL_FRAMEWORK
+#define CONFIG_SPL_NAND_SIMPLE
+
+#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR	0x300 /* address 0x60000 */
+#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS	0x200 /* 256 KB */
+#define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION	1
+#define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME	"u-boot.img"
+
+#define CONFIG_SPL_BOARD_INIT
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+#define CONFIG_SPL_LIBDISK_SUPPORT
+#define CONFIG_SPL_I2C_SUPPORT
+#define CONFIG_SPL_LIBGENERIC_SUPPORT
+#define CONFIG_SPL_MMC_SUPPORT
+#define CONFIG_SPL_FAT_SUPPORT
+#define CONFIG_SPL_SERIAL_SUPPORT
+#define CONFIG_SPL_NAND_SUPPORT
+#define CONFIG_SPL_NAND_BASE
+#define CONFIG_SPL_NAND_DRIVERS
+#define CONFIG_SPL_NAND_ECC
+#define CONFIG_SPL_GPIO_SUPPORT
+#define CONFIG_SPL_POWER_SUPPORT
+#define CONFIG_SPL_OMAP3_ID_NAND
+#define CONFIG_SPL_LDSCRIPT		"$(CPUDIR)/omap-common/u-boot-spl.lds"
+
+/* NAND boot config */
+#define CONFIG_SYS_NAND_5_ADDR_CYCLE
+#define CONFIG_SYS_NAND_PAGE_COUNT	64
+#define CONFIG_SYS_NAND_PAGE_SIZE	2048
+#define CONFIG_SYS_NAND_OOBSIZE		64
+#define CONFIG_SYS_NAND_BLOCK_SIZE	(128 * 1024)
+#define CONFIG_SYS_NAND_BAD_BLOCK_POS	NAND_LARGE_BADBLOCK_POS
+/*
+ * Use the ECC/OOB layout from omap_gpmc.h that matches your chip:
+ * SP vs LP, 8bit vs 16bit: GPMC_NAND_HW_ECC_LAYOUT
+ */
+#define CONFIG_SYS_NAND_ECCPOS		{ 2, 3, 4, 5, 6, 7, 8, 9, \
+					 10, 11, 12, 13 }
+#define CONFIG_SYS_NAND_ECCSIZE		512
+#define CONFIG_SYS_NAND_ECCBYTES	3
+#define CONFIG_NAND_OMAP_ECCSCHEME	OMAP_ECC_HAM1_CODE_HW
+
+#define CONFIG_SYS_NAND_U_BOOT_START	CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_NAND_U_BOOT_OFFS	0x80000
+
+#define CONFIG_SPL_TEXT_BASE		0x40200800
+#define CONFIG_SPL_MAX_SIZE		(54 * 1024)	/* 8 KB for stack */
+#define CONFIG_SPL_STACK		LOW_LEVEL_SRAM_STACK
+
+/*
+ * Use 0x80008000 as TEXT_BASE here for compatibility reasons with the
+ * older x-loader implementations. And move the BSS area so that it
+ * doesn't overlap with TEXT_BASE.
+ */
+#define CONFIG_SYS_TEXT_BASE		0x80008000
+#define CONFIG_SPL_BSS_START_ADDR	0x80100000
+#define CONFIG_SPL_BSS_MAX_SIZE		0x80000		/* 512 KB */
+
+#define CONFIG_SYS_SPL_MALLOC_START	0x80208000
+#define CONFIG_SYS_SPL_MALLOC_SIZE	0x100000
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/taurus.h b/include/configs/taurus.h
new file mode 100644
index 0000000000..20d4cee011
--- /dev/null
+++ b/include/configs/taurus.h
@@ -0,0 +1,159 @@
+/*
+ * Common board functions for Siemens TAURUS (AT91SAM9G20) based boards
+ * (C) Copyright 2013 Siemens AG
+ *
+ * Based on:
+ * U-Boot file: include/configs/at91sam9260ek.h
+ *
+ * (C) Copyright 2007-2008
+ * Stelian Pop <stelian@popies.net>
+ * Lead Tech Design <www.leadtechdesign.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * SoC must be defined first, before hardware.h is included.
+ * In this case SoC is defined in boards.cfg.
+ */
+#include <asm/hardware.h>
+
+#define MACH_TYPE_TAURUS		2067
+#define MACH_TYPE_AXM			2068
+
+/*
+ * Warning: changing CONFIG_SYS_TEXT_BASE requires
+ * adapting the initial boot program.
+ * Since the linker has to swallow that define, we must use a pure
+ * hex number here!
+ */
+
+
+#define CONFIG_SYS_TEXT_BASE		0x23f00000
+
+/* ARM asynchronous clock */
+#define CONFIG_SYS_AT91_SLOW_CLOCK	32768		/* slow clock xtal */
+#define CONFIG_SYS_AT91_MAIN_CLOCK	18432000	/* main clock xtal */
+
+/* Misc CPU related */
+#define CONFIG_ARCH_CPU_INIT
+#define CONFIG_CMDLINE_TAG		/* enable passing of ATAGs */
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+#define CONFIG_SKIP_LOWLEVEL_INIT
+#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_DISPLAY_CPUINFO
+
+#define CONFIG_CMD_BOOTZ
+#define CONFIG_OF_LIBFDT
+
+/* general purpose I/O */
+#define CONFIG_ATMEL_LEGACY		/* required until (g)pio is fixed */
+#define CONFIG_AT91_GPIO
+#define CONFIG_AT91_GPIO_PULLUP	1	/* keep pullups on peripheral pins */
+
+/* serial console */
+#define CONFIG_ATMEL_USART
+#define CONFIG_USART_BASE		ATMEL_BASE_DBGU
+#define CONFIG_USART_ID			ATMEL_ID_SYS
+#define CONFIG_BAUDRATE			115200
+
+#define CONFIG_BOOTDELAY	3
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+#undef CONFIG_CMD_BDI
+#undef CONFIG_CMD_FPGA
+#undef CONFIG_CMD_IMI
+#undef CONFIG_CMD_IMLS
+#undef CONFIG_CMD_LOADS
+#undef CONFIG_CMD_SOURCE
+
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_NAND
+
+/*
+ * SDRAM: 1 bank, min 32, max 128 MB
+ * Initialized before u-boot gets started.
+ */
+#define CONFIG_NR_DRAM_BANKS		1
+#define CONFIG_SYS_SDRAM_BASE		ATMEL_BASE_CS1
+#define CONFIG_SYS_SDRAM_SIZE		(128 * 1024 * 1024)
+
+/*
+ * Initial stack pointer: 4k - GENERATED_GBL_DATA_SIZE in internal SRAM,
+ * leaving the correct space for initial global data structure above
+ * that address while providing maximum stack area below.
+ */
+# define CONFIG_SYS_INIT_SP_ADDR \
+	(ATMEL_BASE_SRAM1 + 0x1000 - GENERATED_GBL_DATA_SIZE)
+
+/* NAND flash */
+#ifdef CONFIG_CMD_NAND
+#define CONFIG_NAND_ATMEL
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+#define CONFIG_SYS_NAND_BASE		ATMEL_BASE_CS3
+#define CONFIG_SYS_NAND_DBW_8
+#define CONFIG_SYS_NAND_MASK_ALE	(1 << 21)
+#define CONFIG_SYS_NAND_MASK_CLE	(1 << 22)
+#define CONFIG_SYS_NAND_ENABLE_PIN	AT91_PIN_PC14
+#define CONFIG_SYS_NAND_READY_PIN	AT91_PIN_PC13
+#endif
+
+/* NOR flash - no real flash on this board */
+#define CONFIG_SYS_NO_FLASH			1
+
+/* Ethernet */
+#define CONFIG_MACB
+#define CONFIG_RMII
+#define CONFIG_AT91_WANTS_COMMON_PHY
+
+/* USB */
+#if defined(CONFIG_BOARD_TAURUS)
+#define CONFIG_USB_ATMEL
+#define CONFIG_USB_OHCI_NEW
+#define CONFIG_SYS_USB_OHCI_CPU_INIT
+#define CONFIG_SYS_USB_OHCI_REGS_BASE		0x00500000
+#define CONFIG_SYS_USB_OHCI_SLOT_NAME		"at91sam9260"
+#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS	2
+#define CONFIG_USB_STORAGE
+#endif
+
+/* load address */
+#define CONFIG_SYS_LOAD_ADDR			0x22000000
+
+/* bootstrap in spi flash , u-boot + env + linux in nandflash */
+#define CONFIG_ENV_IS_IN_NAND
+#define CONFIG_ENV_OFFSET		0x100000
+#define CONFIG_ENV_OFFSET_REDUND	0x180000
+#define CONFIG_ENV_SIZE		0x20000		/* 1 sector = 128 kB */
+#define CONFIG_BOOTCOMMAND	"nand read 0x22000000 0x200000 0x300000; bootm"
+#define CONFIG_BOOTARGS							\
+	"console=ttyS0,115200 earlyprintk "				\
+	"mtdparts=atmel_nand:256k(bootstrap)ro,512k(uboot)ro,"		\
+	"256k(env),256k(env_redundant),256k(spare),"			\
+	"512k(dtb),6M(kernel)ro,-(rootfs) "				\
+	"root=/dev/mtdblock7 rw rootfstype=jffs2"
+
+#define CONFIG_SYS_PROMPT		"U-Boot> "
+#define CONFIG_SYS_CBSIZE		256
+#define CONFIG_SYS_MAXARGS		16
+#define CONFIG_SYS_PBSIZE \
+	(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_CMDLINE_EDITING
+#define CONFIG_AUTO_COMPLETE
+
+/*
+ * Size of malloc() pool
+ */
+#define CONFIG_SYS_MALLOC_LEN \
+	ROUND(3 * CONFIG_ENV_SIZE + 128*1024, 0x1000)
+
+#endif
diff --git a/include/configs/tb0229.h b/include/configs/tb0229.h
deleted file mode 100644
index 132e299167..0000000000
--- a/include/configs/tb0229.h
+++ /dev/null
@@ -1,177 +0,0 @@
-/*
- * (C) Copyright 2003
- * Masami Komiya <mkomiya@sonare.it>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-/*
- * Config header file for TANBAC TB0229 board using an VR4131 CPU module
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#define CONFIG_MIPS32		1	/* MIPS 4Kc CPU core	*/
-#define CONFIG_TB0229		1	/* on a TB0229 Board	*/
-
-#ifndef CPU_CLOCK_RATE
-#define CPU_CLOCK_RATE	200000000	/* 200 MHz clock for the MIPS core */
-#endif
-#define CPU_TCLOCK_RATE 16588800	/* 16.5888 MHz for TClock */
-
-#define CONFIG_CONS_INDEX	1
-#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
-
-#define CONFIG_BAUDRATE		115200
-
-#define CONFIG_TIMESTAMP		/* Print image info with timestamp */
-
-#define CONFIG_PREBOOT	"echo;" \
-	"echo Type \\\"boot\\\" for the network boot using DHCP, TFTP and NFS;" \
-	"echo Type \\\"run netboot_initrd\\\" for the network boot with initrd;" \
-	"echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
-	"echo Type \\\"run flash_local\\\" to mount local root filesystem;" \
-	"echo"
-
-#undef	CONFIG_BOOTARGS
-
-#define CONFIG_EXTRA_ENV_SETTINGS					\
-	"netboot=dhcp;tftp;run netargs; bootm\0"			\
-	"nfsargs=setenv bootargs root=/dev/nfs ip=dhcp\0"		\
-	"localargs=setenv bootargs root=1F02 ip=dhcp\0"			\
-	"addmisc=setenv bootargs ${bootargs} "				\
-		"console=ttyS0,${baudrate} "				\
-		"read-only=readonly\0"					\
-	"netargs=run nfsargs addmisc\0"					\
-	"flash_nfs=run nfsargs addmisc;"				\
-		"bootm ${kernel_addr}\0"				\
-	"flash_local=run localargs addmisc;"				\
-		"bootm ${kernel_addr}\0"				\
-	"netboot_initrd=dhcp;tftp;tftp 80600000 initrd;"		\
-		"setenv bootargs root=/dev/ram ramdisk_size=8192 ip=dhcp;"\
-		"run addmisc;"						\
-		"bootm 80400000 80600000\0"				\
-	"rootpath=/export/miniroot-mipsel\0"				\
-	"autoload=no\0"							\
-	"kernel_addr=BFC60000\0"					\
-	"ramdisk_addr=B0100000\0"					\
-	"u-boot=u-boot.bin\0"						\
-	"bootfile=uImage\0"						\
-	"load=dhcp;tftp 80400000 ${u-boot}\0"				\
-	"load_kernel=dhcp;tftp 80400000 ${bootfile}\0"			\
-	"update_uboot=run load;"					\
-		"protect off BFC00000 BFC3FFFF;"			\
-		"erase BFC00000 BFC3FFFF;"				\
-		"cp.b 80400000 BFC00000 ${filesize}\0"			\
-	"update_kernel=run load_kernel;"				\
-		"erase BFC60000 BFD5FFFF;"				\
-		"cp.b 80400000 BFC60000 ${filesize}\0"			\
-	"initenv=erase bfc40000 bfc5ffff\0"				\
-	""
-/*#define CONFIG_BOOTCOMMAND	"run flash_local" */
-#define CONFIG_BOOTCOMMAND	"run netboot"
-
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_ASKENV
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_PCI
-#define CONFIG_CMD_ELF
-
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP				/* undef to save memory	     */
-#define CONFIG_SYS_PROMPT		"# "		/* Monitor Command Prompt    */
-#define CONFIG_SYS_CBSIZE		256		/* Console I/O Buffer Size   */
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)  /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS		16		/* max number of command args*/
-
-#define CONFIG_SYS_MALLOC_LEN		128*1024
-
-#define CONFIG_SYS_BOOTPARAMS_LEN	128*1024
-
-#define CONFIG_SYS_MIPS_TIMER_FREQ	(CPU_TCLOCK_RATE/4)
-
-#define CONFIG_SYS_HZ			1000
-
-#define CONFIG_SYS_SDRAM_BASE		0x80000000
-
-#define CONFIG_SYS_LOAD_ADDR		0x80400000	/* default load address */
-
-#define CONFIG_SYS_MEMTEST_START	0x80000000
-#define CONFIG_SYS_MEMTEST_END		0x80800000
-
-/*-----------------------------------------------------------------------
- * FLASH and environment organization
- */
-#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks */
-#define CONFIG_SYS_MAX_FLASH_SECT	(128)	/* max number of sectors on one chip */
-
-#define PHYS_FLASH_1		0xbfc00000 /* Flash Bank #1 */
-
-/* The following #defines are needed to get flash environment right */
-#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_MONITOR_LEN		(192 << 10)
-
-#define CONFIG_SYS_INIT_SP_OFFSET	0x400000
-
-#define CONFIG_SYS_FLASH_BASE		PHYS_FLASH_1
-
-/* timeout values are in ticks */
-#define CONFIG_SYS_FLASH_ERASE_TOUT	(20 * CONFIG_SYS_HZ) /* Timeout for Flash Erase */
-#define CONFIG_SYS_FLASH_WRITE_TOUT	(2 * CONFIG_SYS_HZ) /* Timeout for Flash Write */
-
-#define CONFIG_ENV_IS_IN_FLASH	1
-
-/* Address and size of Primary Environment Sector	*/
-#define CONFIG_ENV_ADDR		0xBFC40000
-#define CONFIG_ENV_SIZE		0x20000
-
-#define CONFIG_SYS_DIRECT_FLASH_TFTP
-
-#define CONFIG_NR_DRAM_BANKS	1
-
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CONFIG_SYS_DCACHE_SIZE		16384
-#define CONFIG_SYS_ICACHE_SIZE		16384
-#define CONFIG_SYS_CACHELINE_SIZE	16
-
-/*-----------------------------------------------------------------------
- * Serial Configuration
- */
-#define CONFIG_SYS_NS16550
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE	 1
-#define CONFIG_SYS_NS16550_CLK		 18432000
-#define CONFIG_SYS_NS16550_COM1	 0xaf000800
-
-/*-----------------------------------------------------------------------
- * PCI stuff
- */
-#define CONFIG_PCI
-#define CONFIG_PCI_PNP
-#define CONFIG_EEPRO100
-#define CONFIG_SYS_RX_ETH_BUFFER	8		/* use 8 rx buffer on eepro100	*/
-
-#define CONFIG_RTL8139
-
-#endif	/* __CONFIG_H */
diff --git a/include/configs/tcm-bf518.h b/include/configs/tcm-bf518.h
index 241f21051e..1ff34d517d 100644
--- a/include/configs/tcm-bf518.h
+++ b/include/configs/tcm-bf518.h
@@ -116,7 +116,7 @@
 #define CONFIG_UART_CONSOLE	0
 #define CONFIG_BOOTCOMMAND	"run flashboot"
 #define FLASHBOOT_ENV_SETTINGS	"flashboot=bootm 0x20040000\0"
-
+#define CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED
 
 /*
  * Pull in common ADI header for remaining command/environment setup
diff --git a/include/configs/tcm-bf537.h b/include/configs/tcm-bf537.h
index 2adb071ddb..370d97ffe0 100644
--- a/include/configs/tcm-bf537.h
+++ b/include/configs/tcm-bf537.h
@@ -55,7 +55,7 @@
 #define CONFIG_EBIU_AMBCTL0_VAL	(B1WAT_7 | B1RAT_11 | B1HT_2 | B1ST_3 | B0WAT_7 | B0RAT_11 | B0HT_2 | B0ST_3)
 #define CONFIG_EBIU_AMBCTL1_VAL	(B3WAT_7 | B3RAT_11 | B3HT_2 | B3ST_3 | B2WAT_7 | B2RAT_11 | B2HT_2 | B2ST_3)
 
-#define CONFIG_SYS_MONITOR_LEN	(512 * 1024)
+#define CONFIG_SYS_MONITOR_LEN	(768 * 1024)
 #define CONFIG_SYS_MALLOC_LEN	(128 * 1024)
 
 
@@ -112,8 +112,8 @@
  * it linked after the configuration sector.
  */
 # define LDS_BOARD_TEXT \
-	arch/blackfin/lib/libblackfin.o (.text*); \
-	arch/blackfin/cpu/libblackfin.o (.text*); \
+	arch/blackfin/lib/built-in.o (.text*); \
+	arch/blackfin/cpu/built-in.o (.text*); \
 	. = DEFINED(env_offset) ? env_offset : .; \
 	common/env_embedded.o (.text*);
 #endif
@@ -144,7 +144,8 @@
 #define FLASHBOOT_ENV_SETTINGS \
 	"flashboot=flread 20040000 1000000 300000;" \
 	"bootm 0x1000000\0"
-
+#define CONFIG_BOARD_SIZE_LIMIT $$((384 * 1024))
+#define CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED
 
 /*
  * Pull in common ADI header for remaining command/environment setup
diff --git a/include/configs/tec-ng.h b/include/configs/tec-ng.h
new file mode 100644
index 0000000000..13baa76f91
--- /dev/null
+++ b/include/configs/tec-ng.h
@@ -0,0 +1,84 @@
+/*
+ * (C) Copyright 2013
+ * Avionic Design GmbH <www.avionic-design.de>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include "tegra30-common.h"
+
+/* Enable fdt support for tec-ng. Flash the image in u-boot-dtb.bin */
+#define CONFIG_DEFAULT_DEVICE_TREE	tegra30-tec-ng
+#define CONFIG_OF_CONTROL
+#define CONFIG_OF_SEPARATE
+
+/* High-level configuration options */
+#define V_PROMPT			"Tegra30 (TEC-NG) # "
+#define CONFIG_TEGRA_BOARD_STRING	"Avionic Design Tamonten™ NG Evaluation Carrier"
+
+/* Board-specific serial config */
+#define CONFIG_SERIAL_MULTI
+#define CONFIG_TEGRA_ENABLE_UARTD
+#define CONFIG_SYS_NS16550_COM1		NV_PA_APB_UARTD_BASE
+
+#define CONFIG_BOARD_EARLY_INIT_F
+
+/* I2C */
+#define CONFIG_SYS_I2C_TEGRA
+#define CONFIG_SYS_I2C_INIT_BOARD
+#define CONFIG_I2C_MULTI_BUS
+#define CONFIG_SYS_MAX_I2C_BUS		TEGRA_I2C_NUM_CONTROLLERS
+#define CONFIG_SYS_I2C_SPEED		100000
+#define CONFIG_CMD_I2C
+#define CONFIG_SYS_I2C
+
+/* SD/MMC */
+#define CONFIG_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_TEGRA_MMC
+#define CONFIG_CMD_MMC
+
+/* Environment in eMMC, at the end of 2nd "boot sector" */
+#define CONFIG_ENV_IS_IN_MMC
+#define CONFIG_ENV_OFFSET		(-CONFIG_ENV_SIZE)
+#define CONFIG_SYS_MMC_ENV_DEV		0
+#define CONFIG_SYS_MMC_ENV_PART		2
+
+/* SPI */
+#define CONFIG_TEGRA20_SLINK
+#define CONFIG_TEGRA_SLINK_CTRLS       6
+#define CONFIG_SPI_FLASH
+#define CONFIG_SPI_FLASH_WINBOND
+#define CONFIG_SF_DEFAULT_MODE         SPI_MODE_0
+#define CONFIG_SF_DEFAULT_SPEED        24000000
+#define CONFIG_CMD_SPI
+#define CONFIG_CMD_SF
+#define CONFIG_SPI_FLASH_SIZE          (4 << 20)
+
+/* USB Host support */
+#define CONFIG_USB_EHCI
+#define CONFIG_USB_EHCI_TEGRA
+#define CONFIG_USB_STORAGE
+#define CONFIG_CMD_USB
+
+/* USB networking support */
+#define CONFIG_USB_HOST_ETHER
+#define CONFIG_USB_ETHER_SMSC95XX
+
+/* General networking support */
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_DHCP
+
+/* Tag support */
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+/* support the new (FDT-based) image format */
+#define CONFIG_FIT
+
+#include "tegra-common-post.h"
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/tegra-common-post.h b/include/configs/tegra-common-post.h
index a3242fe612..76dad4e88c 100644
--- a/include/configs/tegra-common-post.h
+++ b/include/configs/tegra-common-post.h
@@ -66,27 +66,63 @@
 #define BOOT_TARGETS_DHCP ""
 #endif
 
+#if defined(CONFIG_CMD_DHCP) && defined(CONFIG_CMD_PXE)
+#define BOOTCMDS_PXE \
+	"bootcmd_pxe=" \
+		BOOTCMD_INIT_USB \
+		"dhcp; " \
+		"if pxe get; then " \
+			"pxe boot; " \
+		"fi\0"
+#define BOOT_TARGETS_PXE "pxe"
+#else
+#define BOOTCMDS_PXE ""
+#define BOOT_TARGETS_PXE ""
+#endif
+
 #define BOOTCMDS_COMMON \
 	"rootpart=1\0" \
 	\
+	"do_script_boot="                                                 \
+		"load ${devtype} ${devnum}:${rootpart} "                  \
+			"${scriptaddr} ${prefix}${script}; "              \
+		"source ${scriptaddr}\0"                                  \
+	\
 	"script_boot="                                                    \
-		"if load ${devtype} ${devnum}:${rootpart} "               \
-				"${scriptaddr} ${prefix}${script}; then " \
-			"echo ${script} found! Executing ...;"            \
-			"source ${scriptaddr};"                           \
-		"fi;\0"                                                   \
+		"for script in ${boot_scripts}; do "                      \
+			"if test -e ${devtype} ${devnum}:${rootpart} "    \
+					"${prefix}${script}; then "       \
+				"echo Found U-Boot script "               \
+					"${prefix}${script}; "            \
+				"run do_script_boot; "                    \
+				"echo SCRIPT FAILED: continuing...; "     \
+			"fi; "                                            \
+		"done\0"                                                  \
+	\
+	"do_sysboot_boot="                                                \
+		"sysboot ${devtype} ${devnum}:${rootpart} any "           \
+			"${scriptaddr} ${prefix}extlinux.conf\0"          \
+	\
+	"sysboot_boot="                                                   \
+		"if test -e ${devtype} ${devnum}:${rootpart} "            \
+				"${prefix}extlinux.conf; then "           \
+			"echo Found extlinux config "                     \
+				"${prefix}extlinux.conf; "                \
+			"run do_sysboot_boot; "                           \
+			"echo SCRIPT FAILED: continuing...; "             \
+		"fi\0"                                                    \
 	\
 	"scan_boot="                                                      \
 		"echo Scanning ${devtype} ${devnum}...; "                 \
 		"for prefix in ${boot_prefixes}; do "                     \
-			"for script in ${boot_scripts}; do "              \
-				"run script_boot; "                       \
-			"done; "                                          \
-		"done;\0"                                                 \
+			"run sysboot_boot; "                              \
+			"run script_boot; "                               \
+		"done\0"                                                  \
 	\
 	"boot_targets=" \
 		BOOT_TARGETS_MMC " " \
 		BOOT_TARGETS_USB " " \
+		BOOT_TARGETS_PXE " " \
 		BOOT_TARGETS_DHCP " " \
 		"\0" \
 	\
@@ -96,9 +132,11 @@
 	\
 	BOOTCMDS_MMC \
 	BOOTCMDS_USB \
-	BOOTCMDS_DHCP
+	BOOTCMDS_DHCP \
+	BOOTCMDS_PXE
 
 #define CONFIG_BOOTCOMMAND \
+	"set usb_need_init; " \
 	"for target in ${boot_targets}; do run bootcmd_${target}; done"
 
 #endif
@@ -129,10 +167,15 @@
 	"stderr=serial" STDOUT_LCD "\0" \
 	""
 
+#ifndef BOARD_EXTRA_ENV_SETTINGS
+#define BOARD_EXTRA_ENV_SETTINGS
+#endif
+
 #define CONFIG_EXTRA_ENV_SETTINGS \
 	TEGRA_DEVICE_SETTINGS \
 	MEM_LAYOUT_ENV_SETTINGS \
-	BOOTCMDS_COMMON
+	BOOTCMDS_COMMON \
+	BOARD_EXTRA_ENV_SETTINGS
 
 #if defined(CONFIG_TEGRA20_SFLASH) || defined(CONFIG_TEGRA20_SLINK) || defined(CONFIG_TEGRA114_SPI)
 #define CONFIG_FDT_SPI
diff --git a/include/configs/tegra-common.h b/include/configs/tegra-common.h
index ba6c6bb9f5..ae786cfd7a 100644
--- a/include/configs/tegra-common.h
+++ b/include/configs/tegra-common.h
@@ -7,7 +7,7 @@
 
 #ifndef _TEGRA_COMMON_H_
 #define _TEGRA_COMMON_H_
-#include <asm/sizes.h>
+#include <linux/sizes.h>
 #include <linux/stringify.h>
 
 /*
@@ -19,6 +19,9 @@
 
 #include <asm/arch/tegra.h>		/* get chip and board defs */
 
+#define CONFIG_SYS_TIMER_RATE		1000000
+#define CONFIG_SYS_TIMER_COUNTER	NV_PA_TMRUS_BASE
+
 /*
  * Display CPU and Board information
  */
@@ -26,7 +29,6 @@
 #define CONFIG_DISPLAY_BOARDINFO
 
 #define CONFIG_CMDLINE_TAG		/* enable passing of ATAGs */
-#define CONFIG_OF_LIBFDT		/* enable passing of devicetree */
 
 /* Environment */
 #define CONFIG_ENV_VARS_UBOOT_CONFIG
@@ -66,33 +68,20 @@
 #undef CONFIG_CMD_NET		/* network support */
 
 /* turn on command-line edit/hist/auto */
-#define CONFIG_CMDLINE_EDITING
 #define CONFIG_COMMAND_HISTORY
-#define CONFIG_AUTO_COMPLETE
 
 /* turn on commonly used storage-related commands */
-
-#define CONFIG_DOS_PARTITION
-#define CONFIG_EFI_PARTITION
 #define CONFIG_PARTITION_UUIDS
-#define CONFIG_FS_EXT4
-#define CONFIG_FS_FAT
-#define CONFIG_CMD_EXT2
-#define CONFIG_CMD_FAT
-#define CONFIG_CMD_FS_GENERIC
 #define CONFIG_CMD_PART
 
 #define CONFIG_SYS_NO_FLASH
 
 #define CONFIG_CONSOLE_MUX
 #define CONFIG_SYS_CONSOLE_IS_IN_ENV
-#define CONFIG_BOOTDELAY	2		/* -1 to disable auto boot */
 
 /*
  * Miscellaneous configurable options
  */
-#define CONFIG_SYS_LONGHELP		/* undef to save memory */
-#define CONFIG_SYS_HUSH_PARSER		/* use "hush" command parser */
 #define CONFIG_SYS_PROMPT		V_PROMPT
 /*
  * Increasing the size of the IO buffer as default nfsargs size is more
@@ -109,8 +98,6 @@
 #define CONFIG_SYS_MEMTEST_START	(NV_PA_SDRC_CS0 + 0x600000)
 #define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_MEMTEST_START + 0x100000)
 
-#define CONFIG_SYS_HZ			1000
-
 /*-----------------------------------------------------------------------
  * Physical Memory Map
  */
@@ -132,8 +119,6 @@
 #define CONFIG_TEGRA_GPIO
 #define CONFIG_CMD_GPIO
 #define CONFIG_CMD_ENTERRCM
-#define CONFIG_CMD_BOOTZ
-#define CONFIG_SUPPORT_RAW_INITRD
 
 /* Defines for SPL */
 #define CONFIG_SPL
@@ -150,10 +135,18 @@
 #define CONFIG_SPL_SERIAL_SUPPORT
 #define CONFIG_SPL_GPIO_SUPPORT
 
+#ifdef CONFIG_SPL_BUILD
+# define CONFIG_USE_PRIVATE_LIBGCC
+#endif
+
 #define CONFIG_SYS_GENERIC_BOARD
 
 /* Misc utility code */
 #define CONFIG_BOUNCE_BUFFER
 #define CONFIG_CRC32_VERIFY
 
+#ifndef CONFIG_SPL_BUILD
+#include <config_distro_defaults.h>
+#endif
+
 #endif /* _TEGRA_COMMON_H_ */
diff --git a/include/configs/tegra114-common.h b/include/configs/tegra114-common.h
index c3de9a999e..555c237cbf 100644
--- a/include/configs/tegra114-common.h
+++ b/include/configs/tegra114-common.h
@@ -26,11 +26,6 @@
  */
 #define V_NS16550_CLK		408000000	/* 408MHz (pllp_out0) */
 
-/*
- * High Level Configuration Options
- */
-#define CONFIG_TEGRA114			/* in a NVidia Tegra114 core */
-
 /* Environment information, boards can override if required */
 #define CONFIG_LOADADDR		0x80408000	/* def. location for kernel */
 
@@ -51,6 +46,9 @@
  * scriptaddr can be pretty much anywhere that doesn't conflict with something
  *   else. Put it above BOOTMAPSZ to eliminate conflicts.
  *
+ * pxefile_addr_r can be pretty much anywhere that doesn't conflict with
+ *   something else. Put it above BOOTMAPSZ to eliminate conflicts.
+ *
  * kernel_addr_r must be within the first 128M of RAM in order for the
  *   kernel's CONFIG_AUTO_ZRELADDR option to work. Since the kernel will
  *   decompress itself to 0x8000 after the start of RAM, kernel_addr_r
@@ -68,6 +66,7 @@
  */
 #define MEM_LAYOUT_ENV_SETTINGS \
 	"scriptaddr=0x90000000\0" \
+	"pxefile_addr_r=0x90100000\0" \
 	"kernel_addr_r=0x81000000\0" \
 	"fdt_addr_r=0x82000000\0" \
 	"ramdisk_addr_r=0x82100000\0"
@@ -82,5 +81,7 @@
 
 /* For USB EHCI controller */
 #define CONFIG_EHCI_IS_TDI
+#define CONFIG_USB_EHCI_TXFIFO_THRESH	0x10
+#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 1
 
 #endif /* _TEGRA114_COMMON_H_ */
diff --git a/include/configs/tegra124-common.h b/include/configs/tegra124-common.h
new file mode 100644
index 0000000000..61e5026574
--- /dev/null
+++ b/include/configs/tegra124-common.h
@@ -0,0 +1,79 @@
+/*
+ * (C) Copyright 2013
+ * NVIDIA Corporation <www.nvidia.com>
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#ifndef _TEGRA124_COMMON_H_
+#define _TEGRA124_COMMON_H_
+
+#include "tegra-common.h"
+
+/* Cortex-A15 uses a cache line size of 64 bytes */
+#define CONFIG_SYS_CACHELINE_SIZE	64
+
+/*
+ * NS16550 Configuration
+ */
+#define V_NS16550_CLK		408000000	/* 408MHz (pllp_out0) */
+
+/* Environment information, boards can override if required */
+#define CONFIG_LOADADDR		0x80408000	/* def. location for kernel */
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LOAD_ADDR	0x80A00800	/* default */
+#define CONFIG_STACKBASE	0x82800000	/* 40MB */
+
+/*-----------------------------------------------------------------------
+ * Physical Memory Map
+ */
+#define CONFIG_SYS_TEXT_BASE	0x8010E000
+
+/*
+ * Memory layout for where various images get loaded by boot scripts:
+ *
+ * scriptaddr can be pretty much anywhere that doesn't conflict with something
+ *   else. Put it above BOOTMAPSZ to eliminate conflicts.
+ *
+ * pxefile_addr_r can be pretty much anywhere that doesn't conflict with
+ *   something else. Put it above BOOTMAPSZ to eliminate conflicts.
+ *
+ * kernel_addr_r must be within the first 128M of RAM in order for the
+ *   kernel's CONFIG_AUTO_ZRELADDR option to work. Since the kernel will
+ *   decompress itself to 0x8000 after the start of RAM, kernel_addr_r
+ *   should not overlap that area, or the kernel will have to copy itself
+ *   somewhere else before decompression. Similarly, the address of any other
+ *   data passed to the kernel shouldn't overlap the start of RAM. Pushing
+ *   this up to 16M allows for a sizable kernel to be decompressed below the
+ *   compressed load address.
+ *
+ * fdt_addr_r simply shouldn't overlap anything else. Choosing 32M allows for
+ *   the compressed kernel to be up to 16M too.
+ *
+ * ramdisk_addr_r simply shouldn't overlap anything else. Choosing 33M allows
+ *   for the FDT/DTB to be up to 1M, which is hopefully plenty.
+ */
+#define MEM_LAYOUT_ENV_SETTINGS \
+	"scriptaddr=0x90000000\0" \
+	"pxefile_addr_r=0x90100000\0" \
+	"kernel_addr_r=0x81000000\0" \
+	"fdt_addr_r=0x82000000\0" \
+	"ramdisk_addr_r=0x82100000\0"
+
+/* Defines for SPL */
+#define CONFIG_SPL_TEXT_BASE		0x80108000
+#define CONFIG_SYS_SPL_MALLOC_START	0x80090000
+#define CONFIG_SPL_STACK		0x800ffffc
+
+/* Total I2C ports on Tegra124 */
+#define TEGRA_I2C_NUM_CONTROLLERS	5
+
+/* For USB EHCI controller */
+#define CONFIG_EHCI_IS_TDI
+#define CONFIG_USB_EHCI_TXFIFO_THRESH	0x10
+#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 1
+
+#endif /* _TEGRA124_COMMON_H_ */
diff --git a/include/configs/tegra20-common.h b/include/configs/tegra20-common.h
index b009a316b1..21bf977174 100644
--- a/include/configs/tegra20-common.h
+++ b/include/configs/tegra20-common.h
@@ -24,11 +24,6 @@
  */
 #define V_NS16550_CLK		216000000	/* 216MHz (pllp_out0) */
 
-/*
- * High Level Configuration Options
- */
-#define CONFIG_TEGRA20				/* in a NVidia Tegra20 core */
-
 /* Environment information, boards can override if required */
 #define CONFIG_LOADADDR		0x00408000	/* def. location for kernel */
 
@@ -49,6 +44,9 @@
  * scriptaddr can be pretty much anywhere that doesn't conflict with something
  *   else. Put it above BOOTMAPSZ to eliminate conflicts.
  *
+ * pxefile_addr_r can be pretty much anywhere that doesn't conflict with
+ *   something else. Put it above BOOTMAPSZ to eliminate conflicts.
+ *
  * kernel_addr_r must be within the first 128M of RAM in order for the
  *   kernel's CONFIG_AUTO_ZRELADDR option to work. Since the kernel will
  *   decompress itself to 0x8000 after the start of RAM, kernel_addr_r
@@ -66,6 +64,7 @@
  */
 #define MEM_LAYOUT_ENV_SETTINGS \
 	"scriptaddr=0x10000000\0" \
+	"pxefile_addr_r=0x10100000\0" \
 	"kernel_addr_r=0x01000000\0" \
 	"fdt_addr_r=0x02000000\0" \
 	"ramdisk_addr_r=0x02100000\0"
@@ -96,6 +95,7 @@
  */
 #define CONFIG_USB_EHCI_TXFIFO_THRESH	10
 #define CONFIG_EHCI_IS_TDI
+#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 1
 
 /* Total I2C ports on Tegra20 */
 #define TEGRA_I2C_NUM_CONTROLLERS	4
diff --git a/include/configs/tegra30-common.h b/include/configs/tegra30-common.h
index 99acbfd28b..443c842240 100644
--- a/include/configs/tegra30-common.h
+++ b/include/configs/tegra30-common.h
@@ -23,11 +23,6 @@
  */
 #define V_NS16550_CLK		408000000	/* 408MHz (pllp_out0) */
 
-/*
- * High Level Configuration Options
- */
-#define CONFIG_TEGRA30			/* in a NVidia Tegra30 core */
-
 /* Environment information, boards can override if required */
 #define CONFIG_LOADADDR		0x80408000	/* def. location for kernel */
 
@@ -48,6 +43,9 @@
  * scriptaddr can be pretty much anywhere that doesn't conflict with something
  *   else. Put it above BOOTMAPSZ to eliminate conflicts.
  *
+ * pxefile_addr_r can be pretty much anywhere that doesn't conflict with
+ *   something else. Put it above BOOTMAPSZ to eliminate conflicts.
+ *
  * kernel_addr_r must be within the first 128M of RAM in order for the
  *   kernel's CONFIG_AUTO_ZRELADDR option to work. Since the kernel will
  *   decompress itself to 0x8000 after the start of RAM, kernel_addr_r
@@ -65,6 +63,7 @@
  */
 #define MEM_LAYOUT_ENV_SETTINGS \
 	"scriptaddr=0x90000000\0" \
+	"pxefile_addr_r=0x90100000\0" \
 	"kernel_addr_r=0x81000000\0" \
 	"fdt_addr_r=0x82000000\0" \
 	"ramdisk_addr_r=0x82100000\0"
@@ -79,5 +78,7 @@
 
 /* For USB EHCI controller */
 #define CONFIG_EHCI_IS_TDI
+#define CONFIG_USB_EHCI_TXFIFO_THRESH	0x10
+#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 1
 
 #endif /* _TEGRA30_COMMON_H_ */
diff --git a/include/configs/ti814x_evm.h b/include/configs/ti814x_evm.h
index 2fc2c10676..b51400c464 100644
--- a/include/configs/ti814x_evm.h
+++ b/include/configs/ti814x_evm.h
@@ -122,7 +122,6 @@
 					+ PHYS_DRAM_1_SIZE - (8 << 12))
 
 #define CONFIG_SYS_LOAD_ADDR		0x81000000	/* Default */
-#define CONFIG_SYS_HZ			1000		/* 1ms clock */
 
 #define CONFIG_OMAP_GPIO
 #define CONFIG_MMC
@@ -149,7 +148,6 @@
  */
 #define CONFIG_SYS_TIMERBASE		0x4802E000
 #define CONFIG_SYS_PTV			2	/* Divisor: 2^(PTV+1) => 8 */
-#define CONFIG_SYS_HZ			1000
 
 /* NS16550 Configuration */
 #define CONFIG_SYS_NS16550
@@ -235,7 +233,6 @@
 #define CONFIG_NET_MULTI
 #define CONFIG_PHY_GIGE
 #define CONFIG_PHYLIB
-#define CONFIG_PHY_ADDR			1
 #define CONFIG_PHY_ET1011C
 #define CONFIG_PHY_ET1011C_TX_CLK_FIX
 
diff --git a/include/configs/ti816x_evm.h b/include/configs/ti816x_evm.h
index e90490c750..b8c0d54ab3 100644
--- a/include/configs/ti816x_evm.h
+++ b/include/configs/ti816x_evm.h
@@ -60,7 +60,6 @@
 
 #undef  CONFIG_SYS_CLKS_IN_HZ
 #define CONFIG_SYS_LOAD_ADDR		0x81000000 /* Default load address */
-#define CONFIG_SYS_HZ			1000	   /* 1ms clock */
 
 #define CONFIG_CMD_ASKEN
 #define CONFIG_CMD_ECHO
diff --git a/include/configs/ti_am335x_common.h b/include/configs/ti_am335x_common.h
index d2e34aeed4..50c32037ff 100644
--- a/include/configs/ti_am335x_common.h
+++ b/include/configs/ti_am335x_common.h
@@ -13,11 +13,11 @@
 #define __CONFIG_TI_AM335X_COMMON_H__
 
 #define CONFIG_AM33XX
-#define CONFIG_BOARD_LATE_INIT
 #define CONFIG_ARCH_CPU_INIT
 #define CONFIG_SYS_CACHELINE_SIZE       64
 #define CONFIG_MAX_RAM_BANK_SIZE	(1024 << 20)	/* 1GB */
 #define CONFIG_SYS_TIMERBASE		0x48040000	/* Use Timer2 */
+#define CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC
 
 #include <asm/arch/omap.h>
 
@@ -30,6 +30,7 @@
 /* Network defines. */
 #define CONFIG_CMD_NET			/* 'bootp' and 'tftp' */
 #define CONFIG_CMD_DHCP
+#define CONFIG_CMD_MII
 #define CONFIG_BOOTP_DNS		/* Configurable parts of CMD_DHCP */
 #define CONFIG_BOOTP_DNS2
 #define CONFIG_BOOTP_SEND_HOSTNAME
@@ -41,6 +42,17 @@
 #define CONFIG_MII			/* Required in net/eth.c */
 
 /*
+ * RTC related defines. To use bootcount you must set bootlimit in the
+ * environment to a non-zero value and enable CONFIG_BOOTCOUNT_LIMIT
+ * in the board config.
+ */
+#define CONFIG_SYS_BOOTCOUNT_ADDR	0x44E3E000
+
+/* Enable the HW watchdog, since we can use this with bootcount */
+#define CONFIG_HW_WATCHDOG
+#define CONFIG_OMAP_WATCHDOG
+
+/*
  * SPL related defines.  The Public RAM memory map the ROM defines the
  * area between 0x402F0400 and 0x4030B800 as a download area and
  * 0x4030B800 to 0x4030CE00 as a public stack area.  The ROM also
@@ -50,6 +62,9 @@
 #define CONFIG_SPL_TEXT_BASE		0x402F0400
 #define CONFIG_SPL_MAX_SIZE		(0x4030B800 - CONFIG_SPL_TEXT_BASE)
 
+/* Enable the watchdog inside of SPL */
+#define CONFIG_SPL_WATCHDOG_SUPPORT
+
 /*
  * Since SPL did pll and ddr initialization for us,
  * we don't need to do it twice.
@@ -58,6 +73,10 @@
 #define CONFIG_SKIP_LOWLEVEL_INIT
 #endif
 
+#ifdef CONFIG_NAND
+#define CONFIG_SPL_NAND_AM33XX_BCH	/* ELM support */
+#endif
+
 /* Now bring in the rest of the common code. */
 #include <configs/ti_armv7_common.h>
 
diff --git a/include/configs/ti_armv7_common.h b/include/configs/ti_armv7_common.h
index e89e8744df..69d69a5421 100644
--- a/include/configs/ti_armv7_common.h
+++ b/include/configs/ti_armv7_common.h
@@ -45,27 +45,29 @@
 #define CONFIG_BOOTDELAY		1
 
 /*
- * DDR information.  We say (for simplicity) that we have 1 bank,
- * always, even when we have more.  We always start at 0x80000000,
- * and we place the initial stack pointer in our SRAM.
+ * DDR information.  If the CONFIG_NR_DRAM_BANKS is not defined,
+ * we say (for simplicity) that we have 1 bank, always, even when
+ * we have more.  We always start at 0x80000000, and we place the
+ * initial stack pointer in our SRAM. Otherwise, we can define
+ * CONFIG_NR_DRAM_BANKS before including this file.
  */
+#ifndef CONFIG_NR_DRAM_BANKS
 #define CONFIG_NR_DRAM_BANKS		1
+#endif
 #define CONFIG_SYS_SDRAM_BASE		0x80000000
 #define CONFIG_SYS_INIT_SP_ADDR         (NON_SECURE_SRAM_END - \
 						GENERATED_GBL_DATA_SIZE)
 
 /* Timer information. */
 #define CONFIG_SYS_PTV			2	/* Divisor: 2^(PTV+1) => 8 */
-#define CONFIG_SYS_HZ			1000	/* 1ms clock */
 
 /* I2C IP block */
 #define CONFIG_I2C
-#define CONFIG_HARD_I2C
-#define CONFIG_SYS_I2C_SPEED		100000
-#define CONFIG_SYS_I2C_SLAVE		1
-#define CONFIG_I2C_MULTI_BUS
-#define CONFIG_DRIVER_OMAP24XX_I2C
 #define CONFIG_CMD_I2C
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_OMAP24_I2C_SPEED	100000
+#define CONFIG_SYS_OMAP24_I2C_SLAVE	1
+#define CONFIG_SYS_I2C_OMAP24XX
 
 /* MMC/SD IP block */
 #define CONFIG_MMC
@@ -202,7 +204,7 @@
 #define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME	"u-boot.img"
 
 #ifdef CONFIG_SPL_OS_BOOT
-#define CONFIG_SYS_SPL_ARGS_ADDR		(CONFIG_SYS_SDRAM_BASE + 0x100)
+#define CONFIG_SYS_SPL_ARGS_ADDR		0x80F80000
 
 /* FAT */
 #define CONFIG_SPL_FAT_LOAD_KERNEL_NAME		"uImage"
@@ -239,7 +241,6 @@
 #define CONFIG_SPL_BOARD_INIT
 
 #ifdef CONFIG_NAND
-#define CONFIG_SPL_NAND_AM33XX_BCH	/* OMAP4 and later ELM support */
 #define CONFIG_SPL_NAND_SUPPORT
 #define CONFIG_SPL_NAND_BASE
 #define CONFIG_SPL_NAND_DRIVERS
diff --git a/include/configs/ti_omap3_common.h b/include/configs/ti_omap3_common.h
new file mode 100644
index 0000000000..854cb78882
--- /dev/null
+++ b/include/configs/ti_omap3_common.h
@@ -0,0 +1,73 @@
+/*
+ * ti_omap3_common.h
+ *
+ * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ *
+ * For more details, please see the technical documents listed at
+ *   http://www.ti.com/product/omap3530
+ *   http://www.ti.com/product/omap3630
+ *   http://www.ti.com/product/dm3730
+ */
+
+#ifndef __CONFIG_TI_OMAP3_COMMON_H__
+#define __CONFIG_TI_OMAP3_COMMON_H__
+
+#define CONFIG_OMAP34XX
+
+#include <asm/arch/cpu.h>
+#include <asm/arch/omap3.h>
+
+/* The chip has SDRC controller */
+#define CONFIG_SDRC
+
+/* Clock Defines */
+#define V_OSCK			26000000	/* Clock output from T2 */
+#define V_SCLK			(V_OSCK >> 1)
+
+/* NS16550 Configuration */
+#define V_NS16550_CLK			48000000	/* 48MHz (APLL96/2) */
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	(-4)
+#define CONFIG_SYS_NS16550_CLK		V_NS16550_CLK
+#define CONFIG_SYS_BAUDRATE_TABLE	{4800, 9600, 19200, 38400, 57600, \
+					115200}
+
+/* Select serial console configuration */
+#define CONFIG_CONS_INDEX		3
+#define CONFIG_SYS_NS16550_COM3		OMAP34XX_UART3
+#define CONFIG_SERIAL3			3
+
+/* Physical Memory Map */
+#define PHYS_SDRAM_1		OMAP34XX_SDRC_CS0
+#define PHYS_SDRAM_2		OMAP34XX_SDRC_CS1
+
+/*
+ * OMAP3 has 12 GP timers, they can be driven by the system clock
+ * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
+ * This rate is divided by a local divisor.
+ */
+#define CONFIG_SYS_TIMERBASE		(OMAP34XX_GPT2)
+
+#define CONFIG_SYS_MONITOR_LEN		(256 << 10)
+
+/* TWL4030 */
+#define CONFIG_TWL4030_POWER		1
+
+/* SPL */
+#define CONFIG_SPL_TEXT_BASE		0x40200800
+#define CONFIG_SPL_MAX_SIZE		(54 * 1024)
+#define CONFIG_SPL_LDSCRIPT		"$(CPUDIR)/omap-common/u-boot-spl.lds"
+#define CONFIG_SPL_POWER_SUPPORT
+
+#ifdef CONFIG_NAND
+#define CONFIG_SPL_NAND_SUPPORT
+#define CONFIG_SPL_NAND_SIMPLE
+#endif
+
+/* Now bring in the rest of the common code. */
+#include <configs/ti_armv7_common.h>
+
+#endif	/* __CONFIG_TI_OMAP3_COMMON_H__ */
diff --git a/include/configs/ti_omap4_common.h b/include/configs/ti_omap4_common.h
new file mode 100644
index 0000000000..bcb5eabd75
--- /dev/null
+++ b/include/configs/ti_omap4_common.h
@@ -0,0 +1,172 @@
+/*
+ * (C) Copyright 2010
+ * Texas Instruments Incorporated.
+ * Aneesh V       <aneesh@ti.com>
+ * Steve Sakoman  <steve@sakoman.com>
+ *
+ * TI OMAP4 common configuration settings
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_TI_OMAP4_COMMON_H
+#define __CONFIG_TI_OMAP4_COMMON_H
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_OMAP44XX		1	/* which is a 44XX */
+#define CONFIG_OMAP4430		1	/* which is in a 4430 */
+#define CONFIG_MISC_INIT_R
+#define CONFIG_ARCH_CPU_INIT
+#define CONFIG_DISPLAY_CPUINFO		1
+#define CONFIG_DISPLAY_BOARDINFO	1
+
+#define CONFIG_SYS_THUMB_BUILD
+
+#ifndef CONFIG_SYS_L2CACHE_OFF
+#define CONFIG_SYS_L2_PL310		1
+#define CONFIG_SYS_PL310_BASE	0x48242000
+#endif
+#define CONFIG_SYS_CACHELINE_SIZE	32
+
+/* Get CPU defs */
+#include <asm/arch/cpu.h>
+#include <asm/arch/omap.h>
+
+/* Use General purpose timer 1 */
+#define CONFIG_SYS_TIMERBASE		GPT2_BASE
+
+/*
+ * Total Size Environment - 128k
+ */
+#define CONFIG_ENV_SIZE			(128 << 10)
+
+/*
+ * For the DDR timing information we can either dynamically determine
+ * the timings to use or use pre-determined timings (based on using the
+ * dynamic method.  Default to the static timing infomation.
+ */
+#define CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
+#ifndef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
+#define CONFIG_SYS_AUTOMATIC_SDRAM_DETECTION
+#define CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS
+#endif
+
+#include <configs/ti_armv7_common.h>
+
+/*
+ * Hardware drivers
+ */
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	(-4)
+#define CONFIG_SYS_NS16550_CLK		48000000
+#define CONFIG_CONS_INDEX		3
+#define CONFIG_SYS_NS16550_COM3		UART3_BASE
+
+/* TWL6030 */
+#ifndef CONFIG_SPL_BUILD
+#define CONFIG_TWL6030_POWER		1
+#endif
+
+/* USB */
+#define CONFIG_MUSB_UDC			1
+#define CONFIG_USB_OMAP3		1
+
+/* USB device configuration */
+#define CONFIG_USB_DEVICE		1
+#define CONFIG_USB_TTY			1
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV	1
+
+/* Per-Soc commands */
+#undef CONFIG_CMD_NET
+#undef CONFIG_CMD_NFS
+
+/*
+ * Environment setup
+ */
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"loadaddr=0x82000000\0" \
+	"console=ttyO2,115200n8\0" \
+	"fdt_high=0xffffffff\0" \
+	"fdtaddr=0x80f80000\0" \
+	"fdtfile=undefined\0" \
+	"bootpart=0:2\0" \
+	"bootdir=/boot\0" \
+	"bootfile=zImage\0" \
+	"usbtty=cdc_acm\0" \
+	"vram=16M\0" \
+	"mmcdev=0\0" \
+	"mmcroot=/dev/mmcblk0p2 rw\0" \
+	"mmcrootfstype=ext3 rootwait\0" \
+	"mmcargs=setenv bootargs console=${console} " \
+		"vram=${vram} " \
+		"root=${mmcroot} " \
+		"rootfstype=${mmcrootfstype}\0" \
+	"loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
+	"bootscript=echo Running bootscript from mmc${mmcdev} ...; " \
+		"source ${loadaddr}\0" \
+	"loadbootenv=fatload mmc ${mmcdev} ${loadaddr} uEnv.txt\0" \
+	"importbootenv=echo Importing environment from mmc${mmcdev} ...; " \
+		"env import -t ${loadaddr} ${filesize}\0" \
+	"loadimage=load mmc ${bootpart} ${loadaddr} ${bootdir}/${bootfile}\0" \
+	"mmcboot=echo Booting from mmc${mmcdev} ...; " \
+		"run mmcargs; " \
+		"bootz ${loadaddr} - ${fdtaddr}\0" \
+	"findfdt="\
+		"if test $board_name = sdp4430; then " \
+			"setenv fdtfile omap4-sdp.dtb; fi; " \
+		"if test $board_name = panda; then " \
+			"setenv fdtfile omap4-panda.dtb; fi;" \
+		"if test $board_name = panda-a4; then " \
+			"setenv fdtfile omap4-panda-a4.dtb; fi;" \
+		"if test $board_name = panda-es; then " \
+			"setenv fdtfile omap4-panda-es.dtb; fi;" \
+		"if test $fdtfile = undefined; then " \
+			"echo WARNING: Could not determine device tree to use; fi; \0" \
+	"loadfdt=load mmc ${bootpart} ${fdtaddr} ${bootdir}/${fdtfile}\0" \
+
+#define CONFIG_BOOTCOMMAND \
+	"run findfdt; " \
+	"mmc dev ${mmcdev}; if mmc rescan; then " \
+		"echo SD/MMC found on device ${mmcdev};" \
+		"if run loadbootscript; then " \
+			"run bootscript; " \
+		"else " \
+			"if run loadbootenv; then " \
+				"run importbootenv; " \
+			"fi;" \
+			"if test -n ${uenvcmd}; then " \
+				"echo Running uenvcmd ...;" \
+				"run uenvcmd;" \
+			"fi;" \
+		"fi;" \
+		"if run loadimage; then " \
+			"run loadfdt;" \
+			"run mmcboot; " \
+		"fi; " \
+	"fi"
+
+/*
+ * Defines for SPL
+ * It is known that this will break HS devices. Since the current size of
+ * SPL is overlapped with public stack and breaking non HS devices to boot.
+ * So moving TEXT_BASE down to non-HS limit.
+ */
+#define CONFIG_SPL_TEXT_BASE		0x40300000
+#define CONFIG_SPL_MAX_SIZE		(0x4030C000 - CONFIG_SPL_TEXT_BASE)
+#define CONFIG_SPL_DISPLAY_PRINT
+#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds"
+
+#ifdef CONFIG_NAND
+#define CONFIG_SPL_NAND_AM33XX_BCH	/* ELM support */
+#endif
+
+#ifdef CONFIG_SPL_BUILD
+/* No need for i2c in SPL mode as we will use SRI2C for PMIC access on OMAP4 */
+#undef CONFIG_SYS_I2C
+#undef CONFIG_SYS_I2C_OMAP24XX
+#endif
+
+#endif /* __CONFIG_TI_OMAP4_COMMON_H */
diff --git a/include/configs/ti_omap5_common.h b/include/configs/ti_omap5_common.h
new file mode 100644
index 0000000000..7b10fbd28a
--- /dev/null
+++ b/include/configs/ti_omap5_common.h
@@ -0,0 +1,153 @@
+/*
+ * (C) Copyright 2013
+ * Texas Instruments Incorporated.
+ * Sricharan R	  <r.sricharan@ti.com>
+ *
+ * Derived from OMAP4 done by:
+ *	Aneesh V <aneesh@ti.com>
+ *
+ * TI OMAP5 AND DRA7XX common configuration settings
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ *
+ * For more details, please see the technical documents listed at
+ * http://www.ti.com/product/omap5432
+ */
+
+#ifndef __CONFIG_TI_OMAP5_COMMON_H
+#define __CONFIG_TI_OMAP5_COMMON_H
+
+#define CONFIG_OMAP54XX
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DISPLAY_BOARDINFO
+#define CONFIG_MISC_INIT_R
+#define CONFIG_ARCH_CPU_INIT
+
+#define CONFIG_SYS_CACHELINE_SIZE	64
+
+/* Use General purpose timer 1 */
+#define CONFIG_SYS_TIMERBASE		GPT2_BASE
+
+/*
+ * For the DDR timing information we can either dynamically determine
+ * the timings to use or use pre-determined timings (based on using the
+ * dynamic method.  Default to the static timing infomation.
+ */
+#define CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
+#ifndef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
+#define CONFIG_SYS_AUTOMATIC_SDRAM_DETECTION
+#define CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS
+#endif
+
+#ifndef CONFIG_SPL_BUILD
+#define CONFIG_PALMAS_POWER
+#endif
+
+#include <asm/arch/cpu.h>
+#include <asm/arch/omap.h>
+
+#define CONFIG_ENV_SIZE			(128 << 10)
+
+#include <configs/ti_armv7_common.h>
+
+/*
+ * Hardware drivers
+ */
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	(-4)
+#define CONFIG_SYS_NS16550_CLK		48000000
+
+/* Per-SoC commands */
+#undef CONFIG_CMD_NET
+#undef CONFIG_CMD_NFS
+
+/*
+ * Environment setup
+ */
+#ifndef PARTS_DEFAULT
+#define PARTS_DEFAULT
+#endif
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"loadaddr=0x80200000\0" \
+	"fdtaddr=0x80F80000\0" \
+	"fdt_high=0xffffffff\0" \
+	"rdaddr=0x81000000\0" \
+	"console=" CONSOLEDEV ",115200n8\0" \
+	"fdtfile=undefined\0" \
+	"bootpart=0:2\0" \
+	"bootdir=/boot\0" \
+	"bootfile=zImage\0" \
+	"usbtty=cdc_acm\0" \
+	"vram=16M\0" \
+	"partitions=" PARTS_DEFAULT "\0" \
+	"optargs=\0" \
+	"mmcdev=0\0" \
+	"mmcroot=/dev/mmcblk1p2 rw\0" \
+	"mmcrootfstype=ext4 rootwait\0" \
+	"mmcargs=setenv bootargs console=${console} " \
+		"${optargs} " \
+		"vram=${vram} " \
+		"root=${mmcroot} " \
+		"rootfstype=${mmcrootfstype}\0" \
+	"loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
+	"bootscript=echo Running bootscript from mmc${mmcdev} ...; " \
+		"source ${loadaddr}\0" \
+	"loadbootenv=fatload mmc ${mmcdev} ${loadaddr} uEnv.txt\0" \
+	"importbootenv=echo Importing environment from mmc${mmcdev} ...; " \
+		"env import -t ${loadaddr} ${filesize}\0" \
+	"loadimage=load mmc ${bootpart} ${loadaddr} ${bootdir}/${bootfile}\0" \
+	"mmcboot=mmc dev ${mmcdev}; " \
+		"if mmc rescan; then " \
+			"echo SD/MMC found on device ${mmcdev};" \
+			"if run loadbootenv; then " \
+				"echo Loaded environment from ${bootenv};" \
+				"run importbootenv;" \
+			"fi;" \
+			"if test -n $uenvcmd; then " \
+				"echo Running uenvcmd ...;" \
+				"run uenvcmd;" \
+			"fi;" \
+			"if run loadimage; then " \
+				"run loadfdt; " \
+				"echo Booting from mmc${mmcdev} ...; " \
+				"run mmcargs; " \
+				"bootz ${loadaddr} - ${fdtaddr}; " \
+			"fi;" \
+		"fi;\0" \
+	"findfdt="\
+		"if test $board_name = omap5_uevm; then " \
+			"setenv fdtfile omap5-uevm.dtb; fi; " \
+		"if test $board_name = dra7xx; then " \
+			"setenv fdtfile dra7-evm.dtb; fi;" \
+		"if test $fdtfile = undefined; then " \
+			"echo WARNING: Could not determine device tree to use; fi; \0" \
+	"loadfdt=load mmc ${bootpart} ${fdtaddr} ${bootdir}/${fdtfile};\0" \
+
+#define CONFIG_BOOTCOMMAND \
+	"run findfdt; " \
+	"run mmcboot;" \
+	"setenv mmcdev 1; " \
+	"setenv bootpart 1:2; " \
+	"setenv mmcroot /dev/mmcblk0p2 rw; " \
+	"run mmcboot;" \
+
+
+/*
+ * SPL related defines.  The Public RAM memory map the ROM defines the
+ * area between 0x40300000 and 0x4031E000 as a download area for OMAP5
+ * (dra7xx is larger, but we do not need to be larger at this time).  We
+ * set CONFIG_SPL_DISPLAY_PRINT to have omap_rev_string() called and
+ * print some information.
+ */
+#define CONFIG_SPL_TEXT_BASE		0x40300000
+#define CONFIG_SPL_MAX_SIZE		(0x4031E000 - CONFIG_SPL_TEXT_BASE)
+#define CONFIG_SPL_DISPLAY_PRINT
+#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds"
+
+#ifdef CONFIG_NAND
+#define CONFIG_SPL_NAND_AM33XX_BCH	/* ELM support */
+#endif
+
+#endif /* __CONFIG_TI_OMAP5_COMMON_H */
diff --git a/include/configs/titanium.h b/include/configs/titanium.h
index 077e25e16e..f9e00c5b8b 100644
--- a/include/configs/titanium.h
+++ b/include/configs/titanium.h
@@ -13,6 +13,7 @@
 #ifndef __CONFIG_H
 #define __CONFIG_H
 
+#include "mx6_common.h"
 #include <asm/arch/imx-regs.h>
 #include <asm/imx-common/gpio.h>
 
@@ -41,8 +42,8 @@
 
 /* I2C Configs */
 #define CONFIG_CMD_I2C
-#define CONFIG_I2C_MULTI_BUS
-#define CONFIG_I2C_MXC
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_MXC
 #define CONFIG_SYS_I2C_SPEED		100000
 
 /* MMC Configs */
@@ -194,7 +195,6 @@
 #define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE
 
 #define CONFIG_SYS_LOAD_ADDR		CONFIG_LOADADDR
-#define CONFIG_SYS_HZ			1000
 
 /* Physical Memory Map */
 #define CONFIG_NR_DRAM_BANKS		1
diff --git a/include/configs/tnetv107x_evm.h b/include/configs/tnetv107x_evm.h
index 27efa69abc..162826f7d3 100644
--- a/include/configs/tnetv107x_evm.h
+++ b/include/configs/tnetv107x_evm.h
@@ -11,7 +11,7 @@
 #ifndef __CONFIG_H
 #define __CONFIG_H
 
-#include <asm/sizes.h>
+#include <linux/sizes.h>
 #include <asm/arch/hardware.h>
 #include <asm/arch/clock.h>
 
@@ -30,7 +30,6 @@
 
 #define CONFIG_SYS_TIMERBASE		TNETV107X_TIMER0_BASE
 #define CONFIG_SYS_HZ_CLOCK		clk_get_rate(TNETV107X_LPSC_TIMER0)
-#define CONFIG_SYS_HZ			1000
 
 #define CONFIG_PLL_SYS_EXT_FREQ		25000000
 #define CONFIG_PLL_TDM_EXT_FREQ		19200000
diff --git a/include/configs/tny_a9260.h b/include/configs/tny_a9260.h
index f841ba828b..32f6b00bbf 100644
--- a/include/configs/tny_a9260.h
+++ b/include/configs/tny_a9260.h
@@ -40,7 +40,6 @@
 /* ARM asynchronous clock */
 #define CONFIG_SYS_AT91_SLOW_CLOCK	32768		/* slow clock xtal */
 #define CONFIG_SYS_AT91_MAIN_CLOCK	12000000	/* 12 MHz crystal */
-#define CONFIG_SYS_HZ		        1000
 
 #define CONFIG_ARCH_CPU_INIT
 #define CONFIG_CMDLINE_TAG	        /* enable passing of ATAGs	*/
diff --git a/include/configs/top9000.h b/include/configs/top9000.h
index a6d692872c..a96a9cb416 100644
--- a/include/configs/top9000.h
+++ b/include/configs/top9000.h
@@ -51,7 +51,6 @@
 /* ARM asynchronous clock */
 #define CONFIG_SYS_AT91_SLOW_CLOCK	32768		/* slow clock xtal */
 #define CONFIG_SYS_AT91_MAIN_CLOCK	18432000	/* main clock xtal */
-#define CONFIG_SYS_HZ			1000
 
 /* Misc CPU related */
 #define CONFIG_ARCH_CPU_INIT
@@ -174,6 +173,7 @@
 
 /* USB */
 #define CONFIG_USB_ATMEL
+#define CONFIG_USB_ATMEL_CLK_SEL_PLLB
 #define CONFIG_USB_OHCI_NEW
 #define CONFIG_DOS_PARTITION
 #define CONFIG_SYS_USB_OHCI_CPU_INIT
diff --git a/include/configs/trats.h b/include/configs/trats.h
index 24ea06b927..5d8bd60583 100644
--- a/include/configs/trats.h
+++ b/include/configs/trats.h
@@ -7,139 +7,120 @@
  * SPDX-License-Identifier:	GPL-2.0+
  */
 
-#ifndef __CONFIG_H
-#define __CONFIG_H
+#ifndef __CONFIG_TRATS_H
+#define __CONFIG_TRATS_H
 
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-#define CONFIG_SAMSUNG		/* in a SAMSUNG core */
-#define CONFIG_S5P		/* which is in a S5P Family */
-#define CONFIG_EXYNOS4210	/* which is in a EXYNOS4210 */
-#define CONFIG_TRATS		/* working with TRATS */
-#define CONFIG_TIZEN		/* TIZEN lib */
+#include <configs/exynos4-dt.h>
+
+#define CONFIG_SYS_PROMPT	"Trats # "	/* Monitor Command Prompt */
 
-#include <asm/arch/cpu.h>	/* get chip and board defs */
+#define CONFIG_TRATS
 
-#define CONFIG_ARCH_CPU_INIT
-#define CONFIG_DISPLAY_CPUINFO
-#define CONFIG_DISPLAY_BOARDINFO
+#undef CONFIG_DEFAULT_DEVICE_TREE
+#define CONFIG_DEFAULT_DEVICE_TREE	exynos4210-trats
 
+#define CONFIG_TIZEN			/* TIZEN lib */
+
+#define CONFIG_SYS_L2CACHE_OFF
 #ifndef CONFIG_SYS_L2CACHE_OFF
 #define CONFIG_SYS_L2_PL310
 #define CONFIG_SYS_PL310_BASE	0x10502000
 #endif
 
+/* TRATS has 4 banks of DRAM */
+#define CONFIG_NR_DRAM_BANKS		4
 #define CONFIG_SYS_SDRAM_BASE		0x40000000
+#define PHYS_SDRAM_1			CONFIG_SYS_SDRAM_BASE
 #define CONFIG_SYS_TEXT_BASE		0x63300000
+#define SDRAM_BANK_SIZE			(256 << 20)	/* 256 MB */
 
-/* input clock of PLL: TRATS has 24MHz input clock at EXYNOS4210 */
-#define CONFIG_SYS_CLK_FREQ_C210	24000000
-#define CONFIG_SYS_CLK_FREQ		CONFIG_SYS_CLK_FREQ_C210
-
-#define CONFIG_SETUP_MEMORY_TAGS
-#define CONFIG_CMDLINE_TAG
-#define CONFIG_REVISION_TAG
-#define CONFIG_CMDLINE_EDITING
-#define CONFIG_SKIP_LOWLEVEL_INIT
-#define CONFIG_BOARD_EARLY_INIT_F
+/* memtest works on */
+#define CONFIG_SYS_MEMTEST_START	CONFIG_SYS_SDRAM_BASE
+#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_SDRAM_BASE + 0x5000000)
+#define CONFIG_SYS_LOAD_ADDR		(CONFIG_SYS_SDRAM_BASE + 0x4800000)
 
-/* MACH_TYPE_TRATS macro will be removed once added to mach-types */
-#define MACH_TYPE_TRATS			3928
-#define CONFIG_MACH_TYPE		MACH_TYPE_TRATS
+#define CONFIG_SYS_TEXT_BASE		0x63300000
 
+#include <linux/sizes.h>
 /* Size of malloc() pool */
-#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + (16 << 20))
+#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + (80 * SZ_1M))
 
 /* select serial console configuration */
-#define CONFIG_SERIAL2			/* use SERIAL 2 */
+#define CONFIG_SERIAL2
 #define CONFIG_BAUDRATE			115200
 
-/* MMC */
-#define CONFIG_GENERIC_MMC
-#define CONFIG_MMC
-#define CONFIG_S5P_SDHCI
-#define CONFIG_SDHCI
-#define CONFIG_MMC_SDMA
-
-/* PWM */
-#define CONFIG_PWM
-
-/* It should define before config_cmd_default.h */
-#define CONFIG_SYS_NO_FLASH
-
-/* Command definition */
-#include <config_cmd_default.h>
-
-#undef CONFIG_CMD_FPGA
-#undef CONFIG_CMD_MISC
-#undef CONFIG_CMD_NET
-#undef CONFIG_CMD_NFS
-#undef CONFIG_CMD_XIMG
-#undef CONFIG_CMD_CACHE
-#undef CONFIG_CMD_ONENAND
-#undef CONFIG_CMD_MTDPARTS
-#define CONFIG_CMD_MMC
-#define CONFIG_CMD_DFU
-#define CONFIG_CMD_GPT
-#define CONFIG_CMD_SETEXPR
-
-/* FAT */
-#define CONFIG_CMD_FAT
-#define CONFIG_FAT_WRITE
-
-/* USB Composite download gadget - g_dnl */
-#define CONFIG_USBDOWNLOAD_GADGET
-#define CONFIG_DFU_FUNCTION
-#define CONFIG_DFU_MMC
-
-/* USB Samsung's IDs */
-#define CONFIG_G_DNL_VENDOR_NUM 0x04E8
-#define CONFIG_G_DNL_PRODUCT_NUM 0x6601
-#define CONFIG_G_DNL_MANUFACTURER "Samsung"
-
-#define CONFIG_BOOTDELAY		1
-#define CONFIG_ZERO_BOOTDELAY_CHECK
+/* Console configuration */
+#define CONFIG_SYS_CONSOLE_INFO_QUIET
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV
+
+/* MACH_TYPE_TRATS macro will be removed once added to mach-types */
+#define MACH_TYPE_TRATS			3928
+#define CONFIG_MACH_TYPE		MACH_TYPE_TRATS
+
 #define CONFIG_BOOTARGS			"Please use defined boot"
 #define CONFIG_BOOTCOMMAND		"run mmcboot"
+#define CONFIG_DEFAULT_CONSOLE		"console=ttySAC1,115200n8\0"
+
+#define CONFIG_SYS_INIT_SP_ADDR	(CONFIG_SYS_LOAD_ADDR \
+					- GENERATED_GBL_DATA_SIZE)
+
+#define CONFIG_SYS_MEM_TOP_HIDE	(1 << 20)	/* ram console */
+
+#define CONFIG_SYS_MONITOR_BASE	0x00000000
 
-#define CONFIG_DEFAULT_CONSOLE		"console=ttySAC2,115200n8\0"
 #define CONFIG_BOOTBLOCK		"10"
 #define CONFIG_ENV_COMMON_BOOT		"${console} ${meminfo}"
 
+#define CONFIG_ENV_IS_IN_MMC
+#define CONFIG_SYS_MMC_ENV_DEV		CONFIG_MMC_DEFAULT_DEV
+#define CONFIG_ENV_SIZE			4096
+#define CONFIG_ENV_OFFSET		((32 - 4) << 10) /* 32KiB - 4KiB */
+
+#define CONFIG_ENV_OVERWRITE
+
+#define CONFIG_ENV_VARS_UBOOT_CONFIG
+#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+
 /* Tizen - partitions definitions */
 #define PARTS_CSA		"csa-mmc"
-#define PARTS_BOOTLOADER	"u-boot"
 #define PARTS_BOOT		"boot"
+#define PARTS_QBOOT		"qboot"
+#define PARTS_CSC		"csc"
 #define PARTS_ROOT		"platform"
 #define PARTS_DATA		"data"
-#define PARTS_CSC		"csc"
 #define PARTS_UMS		"ums"
 
 #define PARTS_DEFAULT \
 	"uuid_disk=${uuid_gpt_disk};" \
-	"name="PARTS_CSA",size=8MiB,uuid=${uuid_gpt_"PARTS_CSA"};" \
-	"name="PARTS_BOOTLOADER",size=60MiB," \
-		"uuid=${uuid_gpt_"PARTS_BOOTLOADER"};" \
-	"name="PARTS_BOOT",size=100MiB,uuid=${uuid_gpt_"PARTS_BOOT"};" \
-	"name="PARTS_ROOT",size=1GiB,uuid=${uuid_gpt_"PARTS_ROOT"};" \
-	"name="PARTS_DATA",size=3GiB,uuid=${uuid_gpt_"PARTS_DATA"};" \
+	"name="PARTS_CSA",start=5MiB,size=8MiB,uuid=${uuid_gpt_"PARTS_CSA"};" \
+	"name="PARTS_BOOT",size=60MiB,uuid=${uuid_gpt_"PARTS_BOOT"};" \
+	"name="PARTS_QBOOT",size=100MiB,uuid=${uuid_gpt_"PARTS_QBOOT"};" \
 	"name="PARTS_CSC",size=150MiB,uuid=${uuid_gpt_"PARTS_CSC"};" \
+	"name="PARTS_ROOT",size=1536MiB,uuid=${uuid_gpt_"PARTS_ROOT"};" \
+	"name="PARTS_DATA",size=3000MiB,uuid=${uuid_gpt_"PARTS_DATA"};" \
 	"name="PARTS_UMS",size=-,uuid=${uuid_gpt_"PARTS_UMS"}\0" \
 
 #define CONFIG_DFU_ALT \
 	"u-boot mmc 80 400;" \
 	"uImage ext4 0 2;" \
-	"exynos4210-trats.dtb ext4 0 2\0"
-
-#define CONFIG_ENV_OVERWRITE
-#define CONFIG_SYS_CONSOLE_INFO_QUIET
-#define CONFIG_SYS_CONSOLE_IS_IN_ENV
+	"modem.bin ext4 0 2;" \
+	"exynos4210-trats.dtb ext4 0 2;" \
+	""PARTS_CSA" part 0 1;" \
+	""PARTS_BOOT" part 0 2;" \
+	""PARTS_QBOOT" part 0 3;" \
+	""PARTS_CSC" part 0 4;" \
+	""PARTS_ROOT" part 0 5;" \
+	""PARTS_DATA" part 0 6;" \
+	""PARTS_UMS" part 0 7;" \
+	"params.bin mmc 0x38 0x8\0"
 
 #define CONFIG_EXTRA_ENV_SETTINGS \
 	"bootk=" \
-		"run loaddtb; run loaduimage; bootm 0x40007FC0 - ${fdtaddr}\0" \
+		"run loaduimage;" \
+		"if run loaddtb; then " \
+			"bootm 0x40007FC0 - ${fdtaddr};" \
+		"fi;" \
+		"bootm 0x40007FC0;\0" \
 	"updatemmc=" \
 		"mmc boot 0 1 1 1; mmc write 0 0x42008000 0 0x200;" \
 		"mmc boot 0 1 1 0\0" \
@@ -162,7 +143,7 @@
 	"mmcboot=" \
 		"setenv bootargs root=/dev/mmcblk${mmcdev}p${mmcrootpart} " \
 		"${lpj} rootwait ${console} ${meminfo} ${opts} ${lcdinfo}; " \
-		"run loaddtb; run loaduimage; bootm 0x40007FC0 - ${fdtaddr}\0" \
+		"run bootk\0" \
 	"bootchart=setenv opts init=/sbin/bootchartd; run bootcmd\0" \
 	"boottrace=setenv opts initcall_debug; run bootcmd\0" \
 	"mmcoops=mmc read 0 0x40000000 0x40 8; md 0x40000000 0x400\0" \
@@ -201,91 +182,35 @@
 		   "setenv spl_imgaddr;" \
 		   "setenv spl_addr_tmp;\0" \
 	"fdtaddr=40800000\0" \
-	"fdtfile=exynos4210-trats.dtb\0"
-
-
-/* Miscellaneous configurable options */
-#define CONFIG_SYS_LONGHELP		/* undef to save memory */
-#define CONFIG_SYS_HUSH_PARSER		/* use "hush" command parser */
-#define CONFIG_SYS_PROMPT		"TRATS # "
-#define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size */
-#define CONFIG_SYS_PBSIZE		384	/* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS		16	/* max number of command args */
-/* Boot Argument Buffer Size */
-#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE
-/* memtest works on */
-#define CONFIG_SYS_MEMTEST_START	CONFIG_SYS_SDRAM_BASE
-#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_SDRAM_BASE + 0x5000000)
-#define CONFIG_SYS_LOAD_ADDR		(CONFIG_SYS_SDRAM_BASE + 0x4800000)
-
-#define CONFIG_SYS_HZ			1000
-
-/* TRATS has 4 banks of DRAM */
-#define CONFIG_NR_DRAM_BANKS	4
-#define SDRAM_BANK_SIZE		(256UL << 20UL)	/* 256 MB */
-#define PHYS_SDRAM_1		CONFIG_SYS_SDRAM_BASE
-#define PHYS_SDRAM_1_SIZE	SDRAM_BANK_SIZE
-#define PHYS_SDRAM_2		(CONFIG_SYS_SDRAM_BASE + SDRAM_BANK_SIZE)
-#define PHYS_SDRAM_2_SIZE	SDRAM_BANK_SIZE
-#define PHYS_SDRAM_3		(CONFIG_SYS_SDRAM_BASE + (2 * SDRAM_BANK_SIZE))
-#define PHYS_SDRAM_3_SIZE	SDRAM_BANK_SIZE
-#define PHYS_SDRAM_4		(CONFIG_SYS_SDRAM_BASE + (3 * SDRAM_BANK_SIZE))
-#define PHYS_SDRAM_4_SIZE	SDRAM_BANK_SIZE
-
-#define CONFIG_SYS_MEM_TOP_HIDE		(1 << 20)	/* ram console */
-
-#define CONFIG_SYS_MONITOR_BASE		0x00000000
-#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 2 sectors */
-
-#define CONFIG_ENV_IS_IN_MMC
-#define CONFIG_SYS_MMC_ENV_DEV		0
-#define CONFIG_ENV_SIZE			4096
-#define CONFIG_ENV_OFFSET		((32 - 4) << 10) /* 32KiB - 4KiB */
-
-#define CONFIG_DOS_PARTITION
-#define CONFIG_EFI_PARTITION
 
-/* EXT4 */
-#define CONFIG_CMD_EXT4
-#define CONFIG_CMD_EXT4_WRITE
 /* Falcon mode definitions */
 #define CONFIG_CMD_SPL
-#define CONFIG_SYS_SPL_ARGS_ADDR        PHYS_SDRAM_1 + 0x100
+#define CONFIG_SYS_SPL_ARGS_ADDR        CONFIG_SYS_SDRAM_BASE + 0x100
 
 /* GPT */
-#define CONFIG_EFI_PARTITION
-#define CONFIG_PARTITION_UUIDS
+#define CONFIG_RANDOM_UUID
 
-#define CONFIG_SYS_INIT_SP_ADDR	(CONFIG_SYS_LOAD_ADDR - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_CACHELINE_SIZE       32
+/* I2C */
+#include <asm/arch/gpio.h>
+
+#define CONFIG_CMD_I2C
 
 #define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_S3C24X0
+#define CONFIG_SYS_I2C_S3C24X0_SPEED	100000
+#define CONFIG_SYS_I2C_S3C24X0_SLAVE	0xFE
+#define CONFIG_MAX_I2C_NUM		8
 #define CONFIG_SYS_I2C_SOFT		/* I2C bit-banged */
 #define CONFIG_SYS_I2C_SOFT_SPEED	50000
-#define CONFIG_SYS_I2C_SOFT_SLAVE	0xFE
-#define I2C_SOFT_DECLARATIONS2
-#define CONFIG_SYS_I2C_SOFT_SPEED_2     50000
-#define CONFIG_SYS_I2C_SOFT_SLAVE_2     0x7F
+#define CONFIG_SYS_I2C_SOFT_SLAVE	0x7F
 #define CONFIG_SOFT_I2C_READ_REPEATED_START
 #define CONFIG_SYS_I2C_INIT_BOARD
-#define CONFIG_I2C_MULTI_BUS
-#define CONFIG_SOFT_I2C_MULTI_BUS
-#define CONFIG_SYS_MAX_I2C_BUS	15
-
-#include <asm/arch/gpio.h>
-
-/* I2C PMIC */
-#define CONFIG_SOFT_I2C_I2C5_SCL exynos4_gpio_part1_get_nr(b, 7)
-#define CONFIG_SOFT_I2C_I2C5_SDA exynos4_gpio_part1_get_nr(b, 6)
 
 /* I2C FG */
-#define CONFIG_SOFT_I2C_I2C9_SCL exynos4_gpio_part2_get_nr(y4, 1)
-#define CONFIG_SOFT_I2C_I2C9_SDA exynos4_gpio_part2_get_nr(y4, 0)
-
-#define CONFIG_SOFT_I2C_GPIO_SCL get_multi_scl_pin()
-#define CONFIG_SOFT_I2C_GPIO_SDA get_multi_sda_pin()
-#define I2C_INIT multi_i2c_init()
+#define CONFIG_SOFT_I2C_GPIO_SCL exynos4_gpio_get(2, y4, 1)
+#define CONFIG_SOFT_I2C_GPIO_SDA exynos4_gpio_get(2, y4, 0)
 
+/* POWER */
 #define CONFIG_POWER
 #define CONFIG_POWER_I2C
 #define CONFIG_POWER_MAX8997
@@ -296,28 +221,50 @@
 #define CONFIG_POWER_MUIC_MAX8997
 #define CONFIG_POWER_BATTERY
 #define CONFIG_POWER_BATTERY_TRATS
-#define CONFIG_USB_GADGET
-#define CONFIG_USB_GADGET_S3C_UDC_OTG
-#define CONFIG_USB_GADGET_DUALSPEED
-#define CONFIG_USB_GADGET_VBUS_DRAW	2
+
+/* Security subsystem - enable hw_rand() */
+#define CONFIG_EXYNOS_ACE_SHA
+#define CONFIG_LIB_HW_RAND
+
+/* Common misc for Samsung */
+#define CONFIG_MISC_COMMON
+
+#define CONFIG_MISC_INIT_R
+
+/* Download menu - Samsung common */
+#define CONFIG_LCD_MENU
+#define CONFIG_LCD_MENU_BOARD
+
+/* Download menu - definitions for check keys */
+#ifndef __ASSEMBLY__
+#include <power/max8997_pmic.h>
+
+#define KEY_PWR_PMIC_NAME		"MAX8997_PMIC"
+#define KEY_PWR_STATUS_REG		MAX8997_REG_STATUS1
+#define KEY_PWR_STATUS_MASK		(1 << 0)
+#define KEY_PWR_INTERRUPT_REG		MAX8997_REG_INT1
+#define KEY_PWR_INTERRUPT_MASK		(1 << 0)
+
+#define KEY_VOL_UP_GPIO			exynos4_gpio_get(2, x2, 0)
+#define KEY_VOL_DOWN_GPIO		exynos4_gpio_get(2, x2, 1)
+#endif /* __ASSEMBLY__ */
+
+/* LCD console */
+#define LCD_BPP			LCD_COLOR16
+#define CONFIG_SYS_WHITE_ON_BLACK
 
 /* LCD */
 #define CONFIG_EXYNOS_FB
 #define CONFIG_LCD
 #define CONFIG_CMD_BMP
-#define CONFIG_BMP_32BPP
+#define CONFIG_BMP_16BPP
 #define CONFIG_FB_ADDR		0x52504000
 #define CONFIG_S6E8AX0
 #define CONFIG_EXYNOS_MIPI_DSIM
 #define CONFIG_VIDEO_BMP_GZIP
-#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE ((500 * 120 * 4) + (1 << 12))
-
-#define CONFIG_CMD_USB_MASS_STORAGE
-#if defined(CONFIG_CMD_USB_MASS_STORAGE)
-#define CONFIG_USB_GADGET_MASS_STORAGE
-#endif
+#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE  ((500 * 160 * 4) + 54)
 
-/* Pass open firmware flat tree */
-#define CONFIG_OF_LIBFDT    1
+#define LCD_XRES	720
+#define LCD_YRES	1280
 
 #endif	/* __CONFIG_H */
diff --git a/include/configs/trats2.h b/include/configs/trats2.h
index 0e93836c0c..53d449c291 100644
--- a/include/configs/trats2.h
+++ b/include/configs/trats2.h
@@ -8,156 +8,109 @@
  * SPDX-License-Identifier:	GPL-2.0+
  */
 
-#ifndef __CONFIG_H
-#define __CONFIG_H
+#ifndef __CONFIG_TRATS2_H
+#define __CONFIG_TRATS2_H
 
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-#define CONFIG_SAMSUNG		/* in a SAMSUNG core */
-#define CONFIG_S5P		/* which is in a S5P Family */
-#define CONFIG_EXYNOS4		/* which is in a EXYNOS4XXX */
-#define CONFIG_TIZEN		/* TIZEN lib */
-
-#define PLATFORM_NO_UNALIGNED
+#include <configs/exynos4-dt.h>
 
-#include <asm/arch/cpu.h>		/* get chip and board defs */
-
-#define CONFIG_ARCH_CPU_INIT
-#define CONFIG_DISPLAY_CPUINFO
-#define CONFIG_DISPLAY_BOARDINFO
+#define CONFIG_SYS_PROMPT	"Trats2 # "	/* Monitor Command Prompt */
 
-#define CONFIG_SKIP_LOWLEVEL_INIT
+#undef CONFIG_DEFAULT_DEVICE_TREE
+#define CONFIG_DEFAULT_DEVICE_TREE	exynos4412-trats2
 
-#define CONFIG_SYS_CACHELINE_SIZE	32
+#define CONFIG_TIZEN			/* TIZEN lib */
 
+#define CONFIG_SYS_L2CACHE_OFF
 #ifndef CONFIG_SYS_L2CACHE_OFF
 #define CONFIG_SYS_L2_PL310
 #define CONFIG_SYS_PL310_BASE	0x10502000
 #endif
 
-#define CONFIG_NR_DRAM_BANKS	4
-#define PHYS_SDRAM_1		0x40000000	/* LDDDR2 DMC 0 */
-#define PHYS_SDRAM_1_SIZE	(256 << 20)	/* 256 MB in CS 0 */
-#define PHYS_SDRAM_2		0x50000000	/* LPDDR2 DMC 1 */
-#define PHYS_SDRAM_2_SIZE	(256 << 20)	/* 256 MB in CS 0 */
-#define PHYS_SDRAM_3		0x60000000	/* LPDDR2 DMC 1 */
-#define PHYS_SDRAM_3_SIZE	(256 << 20)	/* 256 MB in CS 0 */
-#define PHYS_SDRAM_4		0x70000000	/* LPDDR2 DMC 1 */
-#define PHYS_SDRAM_4_SIZE	(256 << 20)	/* 256 MB in CS 0 */
-#define PHYS_SDRAM_END		0x80000000
-
-#define CONFIG_SYS_MEM_TOP_HIDE		(1 << 20)	/* ram console */
-
-#define CONFIG_SYS_SDRAM_BASE		(PHYS_SDRAM_1)
-#define CONFIG_SYS_TEXT_BASE		0x78100000
-
-#define CONFIG_SYS_CLK_FREQ		24000000
-
-#define CONFIG_SETUP_MEMORY_TAGS
-#define CONFIG_CMDLINE_TAG
-#define CONFIG_REVISION_TAG
-
-/* MACH_TYPE_TRATS2 */
-#define MACH_TYPE_TRATS2		3765
-#define CONFIG_MACH_TYPE		MACH_TYPE_TRATS2
+/* TRATS2 has 4 banks of DRAM */
+#define CONFIG_NR_DRAM_BANKS		4
+#define CONFIG_SYS_SDRAM_BASE		0x40000000
+#define PHYS_SDRAM_1			CONFIG_SYS_SDRAM_BASE
+#define SDRAM_BANK_SIZE			(256 << 20)	/* 256 MB */
+/* memtest works on */
+#define CONFIG_SYS_MEMTEST_START	CONFIG_SYS_SDRAM_BASE
+#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_SDRAM_BASE + 0x5E00000)
+#define CONFIG_SYS_LOAD_ADDR		(CONFIG_SYS_SDRAM_BASE + 0x3E00000)
 
-#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_SYS_TEXT_BASE		0x43e00000
 
-/*
- * Size of malloc() pool
- */
-#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + (2 << 20))
+#include <linux/sizes.h>
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + (80 * SZ_1M))
 
 /* select serial console configuration */
 #define CONFIG_SERIAL2
-
-#define CONFIG_SYS_HUSH_PARSER		/* use "hush" command parser	*/
-#define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
-
-#define CONFIG_CMDLINE_EDITING
-
 #define CONFIG_BAUDRATE			115200
 
-/* It should define before config_cmd_default.h */
-#define CONFIG_SYS_NO_FLASH
-
-/***********************************************************
- * Command definition
- ***********************************************************/
-#include <config_cmd_default.h>
-
-#undef CONFIG_CMD_ECHO
-#undef CONFIG_CMD_FPGA
-#undef CONFIG_CMD_FLASH
-#undef CONFIG_CMD_IMLS
-#undef CONFIG_CMD_NAND
-#undef CONFIG_CMD_MISC
-#undef CONFIG_CMD_NFS
-#undef CONFIG_CMD_SOURCE
-#undef CONFIG_CMD_XIMG
-#define CONFIG_CMD_CACHE
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_MMC
-#define CONFIG_CMD_GPT
-#define CONFIG_CMD_PMIC
-
-#define CONFIG_BOOTDELAY	3
-#define CONFIG_ZERO_BOOTDELAY_CHECK
-
-#define CONFIG_CMD_FAT
-#define CONFIG_FAT_WRITE
+/* Console configuration */
+#define CONFIG_SYS_CONSOLE_INFO_QUIET
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV
 
-/* EXT4 */
-#define CONFIG_CMD_EXT4
-#define CONFIG_CMD_EXT4_WRITE
+#define CONFIG_BOOTARGS			"Please use defined boot"
+#define CONFIG_BOOTCOMMAND		"run mmcboot"
+#define CONFIG_DEFAULT_CONSOLE		"console=ttySAC1,115200n8\0"
 
-/* To use the TFTPBOOT over USB, Please enable the CONFIG_CMD_NET */
-#undef CONFIG_CMD_NET
+#define CONFIG_SYS_INIT_SP_ADDR	(CONFIG_SYS_LOAD_ADDR \
+					- GENERATED_GBL_DATA_SIZE)
 
-/* MMC */
-#define CONFIG_GENERIC_MMC
-#define CONFIG_MMC
-#define CONFIG_S5P_SDHCI
-#define CONFIG_SDHCI
-#define CONFIG_MMC_SDMA
-#define CONFIG_MMC_DEFAULT_DEV	0
+#define CONFIG_SYS_MEM_TOP_HIDE	(1 << 20)	/* ram console */
 
-/* PWM */
-#define CONFIG_PWM
+#define CONFIG_SYS_MONITOR_BASE	0x00000000
 
-#define CONFIG_BOOTARGS		"Please use defined boot"
-#define CONFIG_BOOTCOMMAND	"run mmcboot"
-#define CONFIG_DEFAULT_CONSOLE	"console=ttySAC2,115200n8\0"
+#define CONFIG_ENV_IS_IN_MMC
+#define CONFIG_SYS_MMC_ENV_DEV		CONFIG_MMC_DEFAULT_DEV
+#define CONFIG_ENV_SIZE			4096
+#define CONFIG_ENV_OFFSET		((32 - 4) << 10) /* 32KiB - 4KiB */
 
 #define CONFIG_ENV_OVERWRITE
-#define CONFIG_SYS_CONSOLE_INFO_QUIET
-#define CONFIG_SYS_CONSOLE_IS_IN_ENV
+
+#define CONFIG_ENV_VARS_UBOOT_CONFIG
+#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
 
 /* Tizen - partitions definitions */
 #define PARTS_CSA		"csa-mmc"
-#define PARTS_BOOTLOADER	"u-boot"
 #define PARTS_BOOT		"boot"
+#define PARTS_QBOOT		"qboot"
+#define PARTS_CSC		"csc"
 #define PARTS_ROOT		"platform"
 #define PARTS_DATA		"data"
-#define PARTS_CSC		"csc"
 #define PARTS_UMS		"ums"
 
 #define PARTS_DEFAULT \
 	"uuid_disk=${uuid_gpt_disk};" \
-	"name="PARTS_CSA",size=8MiB,uuid=${uuid_gpt_"PARTS_CSA"};" \
-	"name="PARTS_BOOTLOADER",size=60MiB," \
-		"uuid=${uuid_gpt_"PARTS_BOOTLOADER"};" \
-	"name="PARTS_BOOT",size=100MiB,uuid=${uuid_gpt_"PARTS_BOOT"};" \
-	"name="PARTS_ROOT",size=1GiB,uuid=${uuid_gpt_"PARTS_ROOT"};" \
-	"name="PARTS_DATA",size=3GiB,uuid=${uuid_gpt_"PARTS_DATA"};" \
+	"name="PARTS_CSA",start=5MiB,size=8MiB,uuid=${uuid_gpt_"PARTS_CSA"};" \
+	"name="PARTS_BOOT",size=60MiB,uuid=${uuid_gpt_"PARTS_BOOT"};" \
+	"name="PARTS_QBOOT",size=100MiB,uuid=${uuid_gpt_"PARTS_QBOOT"};" \
 	"name="PARTS_CSC",size=150MiB,uuid=${uuid_gpt_"PARTS_CSC"};" \
+	"name="PARTS_ROOT",size=1536MiB,uuid=${uuid_gpt_"PARTS_ROOT"};" \
+	"name="PARTS_DATA",size=3000MiB,uuid=${uuid_gpt_"PARTS_DATA"};" \
 	"name="PARTS_UMS",size=-,uuid=${uuid_gpt_"PARTS_UMS"}\0" \
 
+#define CONFIG_DFU_ALT \
+	"u-boot mmc 80 800;" \
+	"uImage ext4 0 2;" \
+	"modem.bin ext4 0 2;" \
+	"exynos4412-trats2.dtb ext4 0 2;" \
+	""PARTS_CSA" part 0 1;" \
+	""PARTS_BOOT" part 0 2;" \
+	""PARTS_QBOOT" part 0 3;" \
+	""PARTS_CSC" part 0 4;" \
+	""PARTS_ROOT" part 0 5;" \
+	""PARTS_DATA" part 0 6;" \
+	""PARTS_UMS" part 0 7;" \
+	"params.bin mmc 0x38 0x8\0"
+
 #define CONFIG_EXTRA_ENV_SETTINGS \
 	"bootk=" \
-		"run loaddtb; run loaduimage; bootm 0x40007FC0 - ${fdtaddr}\0" \
+		"run loaduimage;" \
+		"if run loaddtb; then " \
+			"bootm 0x40007FC0 - ${fdtaddr};" \
+		"fi;" \
+		"bootm 0x40007FC0;\0" \
 	"updatemmc=" \
 		"mmc boot 0 1 1 1; mmc write 0x42008000 0 0x200;" \
 		"mmc boot 0 1 1 0\0" \
@@ -171,22 +124,23 @@
 	"mmcboot=" \
 		"setenv bootargs root=/dev/mmcblk${mmcdev}p${mmcrootpart} " \
 		"${lpj} rootwait ${console} ${meminfo} ${opts} ${lcdinfo}; " \
-		"run loaddtb; run loaduimage; bootm 0x40007FC0 - ${fdtaddr}\0" \
+		"run bootk\0" \
 	"bootchart=set opts init=/sbin/bootchartd; run bootcmd\0" \
 	"boottrace=setenv opts initcall_debug; run bootcmd\0" \
 	"verify=n\0" \
 	"rootfstype=ext4\0" \
 	"console=" CONFIG_DEFAULT_CONSOLE \
 	"kernelname=uImage\0" \
-	"loaduimage=ext4load mmc ${mmcdev}:${mmcbootpart} 0x40007FC0 uImage\0" \
-		"0x40007FC0 ${kernelname}\0" \
+	"loaduimage=ext4load mmc ${mmcdev}:${mmcbootpart} 0x40007FC0 " \
+		"${kernelname}\0" \
 	"loaddtb=ext4load mmc ${mmcdev}:${mmcbootpart} ${fdtaddr} " \
 		"${fdtfile}\0" \
-	"mmcdev=0\0" \
+	"mmcdev=" __stringify(CONFIG_MMC_DEFAULT_DEV) "\0" \
 	"mmcbootpart=2\0" \
 	"mmcrootpart=5\0" \
 	"opts=always_resume=1\0" \
 	"partitions=" PARTS_DEFAULT \
+	"dfu_alt_info=" CONFIG_DFU_ALT \
 	"uartpath=ap\0" \
 	"usbpath=ap\0" \
 	"consoleon=set console console=ttySAC2,115200n8; save; reset\0" \
@@ -211,79 +165,35 @@
 		   "setenv spl_imgaddr;" \
 		   "setenv spl_addr_tmp;\0" \
 	"fdtaddr=40800000\0" \
-	"fdtfile=exynos4412-trats2.dtb\0"
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP			/* undef to save memory */
-#define CONFIG_SYS_PROMPT	"Trats2 # "	/* Monitor Command Prompt */
-#define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size */
-#define CONFIG_SYS_PBSIZE	384		/* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS	32		/* max number of command args */
-
-/* Boot Argument Buffer Size */
-#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE
-
-/* memtest works on */
-#define CONFIG_SYS_MEMTEST_START	CONFIG_SYS_SDRAM_BASE
-#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_SDRAM_BASE + 0x5000000)
-#define CONFIG_SYS_LOAD_ADDR		(CONFIG_SYS_SDRAM_BASE + 0x4800000)
-
-#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_LOAD_ADDR \
-					- GENERATED_GBL_DATA_SIZE)
-
-#define CONFIG_SYS_HZ			1000
-
-/* valid baudrates */
-#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
-
-#define CONFIG_SYS_MONITOR_BASE		0x00000000
-
-/*-----------------------------------------------------------------------
- * FLASH and environment organization
- */
-
-#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 2 sectors */
-
-#define CONFIG_ENV_IS_IN_MMC
-#define CONFIG_SYS_MMC_ENV_DEV		CONFIG_MMC_DEFAULT_DEV
-#define CONFIG_ENV_SIZE			4096
-#define CONFIG_ENV_OFFSET		((32 - 4) << 10) /* 32KiB - 4KiB */
-#define CONFIG_EFI_PARTITION
-#define CONFIG_PARTITION_UUIDS
 
-#define CONFIG_MISC_INIT_R
-#define CONFIG_BOARD_EARLY_INIT_F
+/* GPT */
+#define CONFIG_RANDOM_UUID
 
 /* I2C */
 #include <asm/arch/gpio.h>
 
+#define CONFIG_CMD_I2C
+
 #define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_SOFT		/* I2C bit-banged */
+#define CONFIG_SYS_I2C_S3C24X0
+#define CONFIG_SYS_I2C_S3C24X0_SPEED	100000
+#define CONFIG_SYS_I2C_S3C24X0_SLAVE	0
+#define CONFIG_MAX_I2C_NUM		8
+#define CONFIG_SYS_I2C_SOFT
 #define CONFIG_SYS_I2C_SOFT_SPEED	50000
 #define CONFIG_SYS_I2C_SOFT_SLAVE	0x00
 #define I2C_SOFT_DECLARATIONS2
 #define CONFIG_SYS_I2C_SOFT_SPEED_2     50000
 #define CONFIG_SYS_I2C_SOFT_SLAVE_2     0x00
-#define I2C_SOFT_DECLARATIONS3
-#define CONFIG_SYS_I2C_SOFT_SPEED_3     50000
-#define CONFIG_SYS_I2C_SOFT_SLAVE_3     0x00
 #define CONFIG_SOFT_I2C_READ_REPEATED_START
 #define CONFIG_SYS_I2C_INIT_BOARD
-#define CONFIG_I2C_MULTI_BUS
-#define CONFIG_SOFT_I2C_MULTI_BUS
-#define CONFIG_SYS_MAX_I2C_BUS		15
-
-#define CONFIG_SOFT_I2C_I2C5_SCL exynos4x12_gpio_part1_get_nr(d0, 3)
-#define CONFIG_SOFT_I2C_I2C5_SDA exynos4x12_gpio_part1_get_nr(d0, 2)
-#define CONFIG_SOFT_I2C_I2C9_SCL exynos4x12_gpio_part1_get_nr(f1, 4)
-#define CONFIG_SOFT_I2C_I2C9_SDA exynos4x12_gpio_part1_get_nr(f1, 5)
-#define CONFIG_SOFT_I2C_I2C10_SCL exynos4x12_gpio_part2_get_nr(m2, 1)
-#define CONFIG_SOFT_I2C_I2C10_SDA exynos4x12_gpio_part2_get_nr(m2, 0)
-#define CONFIG_SOFT_I2C_GPIO_SCL get_multi_scl_pin()
-#define CONFIG_SOFT_I2C_GPIO_SDA get_multi_sda_pin()
-#define I2C_INIT multi_i2c_init()
+
+#ifndef __ASSEMBLY__
+int get_soft_i2c_scl_pin(void);
+int get_soft_i2c_sda_pin(void);
+#endif
+#define CONFIG_SOFT_I2C_GPIO_SCL	get_soft_i2c_scl_pin()
+#define CONFIG_SOFT_I2C_GPIO_SDA	get_soft_i2c_sda_pin()
 
 /* POWER */
 #define CONFIG_POWER
@@ -294,18 +204,49 @@
 #define CONFIG_POWER_FG_MAX77693
 #define CONFIG_POWER_BATTERY_TRATS2
 
+/* Security subsystem - enable hw_rand() */
+#define CONFIG_EXYNOS_ACE_SHA
+#define CONFIG_LIB_HW_RAND
+
+/* Common misc for Samsung */
+#define CONFIG_MISC_COMMON
+
+#define CONFIG_MISC_INIT_R
+
+/* Download menu - Samsung common */
+#define CONFIG_LCD_MENU
+#define CONFIG_LCD_MENU_BOARD
+
+/* Download menu - definitions for check keys */
+#ifndef __ASSEMBLY__
+#include <power/max77686_pmic.h>
+
+#define KEY_PWR_PMIC_NAME		"MAX77686_PMIC"
+#define KEY_PWR_STATUS_REG		MAX77686_REG_PMIC_STATUS1
+#define KEY_PWR_STATUS_MASK		(1 << 0)
+#define KEY_PWR_INTERRUPT_REG		MAX77686_REG_PMIC_INT1
+#define KEY_PWR_INTERRUPT_MASK		(1 << 1)
+
+#define KEY_VOL_UP_GPIO			exynos4x12_gpio_get(2, x2, 2)
+#define KEY_VOL_DOWN_GPIO		exynos4x12_gpio_get(2, x3, 3)
+#endif /* __ASSEMBLY__ */
+
+/* LCD console */
+#define LCD_BPP                 LCD_COLOR16
+#define CONFIG_SYS_WHITE_ON_BLACK
+
 /* LCD */
 #define CONFIG_EXYNOS_FB
 #define CONFIG_LCD
 #define CONFIG_CMD_BMP
-#define CONFIG_BMP_32BPP
+#define CONFIG_BMP_16BPP
 #define CONFIG_FB_ADDR		0x52504000
 #define CONFIG_S6E8AX0
 #define CONFIG_EXYNOS_MIPI_DSIM
 #define CONFIG_VIDEO_BMP_GZIP
-#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE ((500 * 250 * 4) + (1 << 12))
+#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE ((500 * 160 * 4) + 54)
 
-/* Pass open firmware flat tree */
-#define CONFIG_OF_LIBFDT    1
+#define LCD_XRES	720
+#define LCD_YRES	1280
 
 #endif	/* __CONFIG_H */
diff --git a/include/configs/tricorder.h b/include/configs/tricorder.h
index b102739a0e..80985a2655 100644
--- a/include/configs/tricorder.h
+++ b/include/configs/tricorder.h
@@ -39,6 +39,9 @@
 #define CONFIG_DISPLAY_CPUINFO
 #define CONFIG_DISPLAY_BOARDINFO
 
+#define CONFIG_SILENT_CONSOLE
+#define CONFIG_ZERO_BOOTDELAY_CHECK
+
 /* Clock Defines */
 #define V_OSCK				26000000 /* Clock output from T2 */
 #define V_SCLK				(V_OSCK >> 1)
@@ -53,12 +56,30 @@
 #define CONFIG_OF_LIBFDT
 
 /* Size of malloc() pool */
-#define CONFIG_ENV_SIZE			(128 << 10)	/* 128 KiB */
-						/* Sector */
 #define CONFIG_SYS_MALLOC_LEN		(1024*1024)
 
 /* Hardware drivers */
 
+/* GPIO support */
+#define CONFIG_OMAP_GPIO
+
+/* GPIO banks */
+#define CONFIG_OMAP3_GPIO_2		/* GPIO32..63 are in GPIO bank 2 */
+
+/* LED support */
+#define CONFIG_STATUS_LED
+#define CONFIG_BOARD_SPECIFIC_LED
+#define CONFIG_CMD_LED			/* LED command */
+#define STATUS_LED_BIT			(1 << 0)
+#define STATUS_LED_STATE		STATUS_LED_ON
+#define STATUS_LED_PERIOD		(CONFIG_SYS_HZ / 2)
+#define STATUS_LED_BIT1			(1 << 1)
+#define STATUS_LED_STATE1		STATUS_LED_ON
+#define STATUS_LED_PERIOD1		(CONFIG_SYS_HZ / 2)
+#define STATUS_LED_BIT2			(1 << 2)
+#define STATUS_LED_STATE2		STATUS_LED_ON
+#define STATUS_LED_PERIOD2		(CONFIG_SYS_HZ / 2)
+
 /* NS16550 Configuration */
 #define CONFIG_SYS_NS16550
 #define CONFIG_SYS_NS16550_SERIAL
@@ -80,10 +101,17 @@
 #define CONFIG_DOS_PARTITION
 
 /* I2C */
-#define CONFIG_HARD_I2C
-#define CONFIG_SYS_I2C_SPEED		100000
-#define CONFIG_SYS_I2C_SLAVE		1
-#define CONFIG_DRIVER_OMAP34XX_I2C	1
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_OMAP24_I2C_SPEED	100000
+#define CONFIG_SYS_OMAP24_I2C_SLAVE	1
+#define CONFIG_SYS_I2C_OMAP34XX
+ 
+
+/* EEPROM */
+#define CONFIG_SYS_I2C_MULTI_EEPROMS
+#define CONFIG_CMD_EEPROM
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	2
+#define CONFIG_SYS_EEPROM_BUS_NUM	1
 
 /* TWL4030 */
 #define CONFIG_TWL4030_POWER
@@ -92,13 +120,16 @@
 /* Board NAND Info */
 #define CONFIG_SYS_NO_FLASH		/* no NOR flash */
 #define CONFIG_MTD_DEVICE		/* needed for mtdparts commands */
-#define MTDIDS_DEFAULT			"nand0=nand"
-#define MTDPARTS_DEFAULT		"mtdparts=nand:" \
-						"512k(u-boot-spl)," \
-						"1920k(u-boot)," \
-						"128k(u-boot-env)," \
-						"4m(kernel)," \
-						"-(fs)"
+#define MTDIDS_DEFAULT			"nand0=omap2-nand.0"
+#define MTDPARTS_DEFAULT		"mtdparts=omap2-nand.0:" \
+						"128k(SPL)," \
+						"1m(u-boot)," \
+						"384k(u-boot-env1)," \
+						"1152k(mtdoops)," \
+						"384k(u-boot-env2)," \
+						"5m(kernel)," \
+						"2m(fdt)," \
+						"-(ubi)"
 
 #define CONFIG_NAND_OMAP_GPMC
 #define CONFIG_SYS_NAND_ADDR		NAND_BASE	/* physical address */
@@ -106,12 +137,11 @@
 #define CONFIG_SYS_NAND_BASE		NAND_BASE	/* physical address */
 							/* to access nand at */
 							/* CS0 */
-#define GPMC_NAND_ECC_LP_x16_LAYOUT	1
-
 #define CONFIG_SYS_MAX_NAND_DEVICE	1		/* Max number of NAND */
 							/* devices */
-#define CONFIG_NAND_OMAP_BCH8
 #define CONFIG_BCH
+#define CONFIG_SYS_NAND_MAX_OOBFREE	2
+#define CONFIG_SYS_NAND_MAX_ECCPOS	56
 
 /* commands to include */
 #include <config_cmd_default.h>
@@ -138,53 +168,104 @@
 #define CONFIG_MTD_DEVICE       /* needed for mtdparts commands */
 #define CONFIG_MTD_PARTITIONS
 
-/* Environment information */
-#define CONFIG_ENV_OVERWRITE /* allow to overwrite serial and ethaddr */
+/* Environment information (this is the common part) */
 
-#define CONFIG_BOOTDELAY		3
+#define CONFIG_BOOTDELAY		0
 
-#define CONFIG_EXTRA_ENV_SETTINGS \
-	"loadaddr=0x82000000\0" \
+/* hang() the board on panic() */
+#define CONFIG_PANIC_HANG
+
+/* environment placement (for NAND), is different for FLASHCARD but does not
+ * harm there */
+#define CONFIG_ENV_OFFSET		0x120000    /* env start */
+#define CONFIG_ENV_OFFSET_REDUND	0x2A0000    /* redundant env start */
+#define CONFIG_ENV_SIZE			(16 << 10)  /* use 16KiB for env */
+#define CONFIG_ENV_RANGE		(384 << 10) /* allow badblocks in env */
+
+/* the loadaddr is the same as CONFIG_SYS_LOAD_ADDR, unfortunately the defiend
+ * value can not be used here! */
+#define CONFIG_LOADADDR		0x82000000
+
+#define CONFIG_COMMON_ENV_SETTINGS \
 	"console=ttyO2,115200n8\0" \
 	"mmcdev=0\0" \
-	"vram=12M\0" \
-	"lcdmode=800x600\0" \
+	"vram=3M\0" \
 	"defaultdisplay=lcd\0" \
-	"kernelopts=rw rootwait\0" \
+	"kernelopts=mtdoops.mtddev=3\0" \
+	"mtdparts=" MTDPARTS_DEFAULT "\0" \
+	"mtdids=" MTDIDS_DEFAULT "\0" \
 	"commonargs=" \
 		"setenv bootargs console=${console} " \
+		"${mtdparts} " \
+		"${kernelopts} " \
+		"vt.global_cursor_default=0 " \
 		"vram=${vram} " \
-		"omapfb.mode=lcd:${lcdmode} " \
-		"omapdss.def_disp=${defaultdisplay}\0" \
+		"omapdss.def_disp=${defaultdisplay}\0"
+
+#define CONFIG_BOOTCOMMAND "run autoboot"
+
+/* specific environment settings for different use cases
+ * FLASHCARD: used to run a rdimage from sdcard to program the device
+ * 'NORMAL': used to boot kernel from sdcard, nand, ...
+ *
+ * The main aim for the FLASHCARD skin is to have an embedded environment
+ * which will not be influenced by any data already on the device.
+ */
+#ifdef CONFIG_FLASHCARD
+
+#define CONFIG_ENV_IS_NOWHERE
+
+/* the rdaddr is 16 MiB before the loadaddr */
+#define CONFIG_ENV_RDADDR	"rdaddr=0x81000000\0"
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	CONFIG_COMMON_ENV_SETTINGS \
+	CONFIG_ENV_RDADDR \
+	"autoboot=" \
+	"run commonargs; " \
+	"setenv bootargs ${bootargs} " \
+		"flashy_updateimg=/dev/mmcblk0p1:corscience_update.img " \
+		"rdinit=/sbin/init; " \
+	"mmc dev ${mmcdev}; mmc rescan; " \
+	"fatload mmc ${mmcdev} ${loadaddr} uImage; " \
+	"fatload mmc ${mmcdev} ${rdaddr} uRamdisk; " \
+	"bootm ${loadaddr} ${rdaddr}\0"
+
+#else /* CONFIG_FLASHCARD */
+
+#define CONFIG_ENV_OVERWRITE /* allow to overwrite serial and ethaddr */
+
+#define CONFIG_ENV_IS_IN_NAND
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	CONFIG_COMMON_ENV_SETTINGS \
 	"mmcargs=" \
 		"run commonargs; " \
 		"setenv bootargs ${bootargs} " \
 		"root=/dev/mmcblk0p2 " \
-		"${kernelopts}\0" \
+		"rootwait " \
+		"rw\0" \
 	"nandargs=" \
 		"run commonargs; " \
 		"setenv bootargs ${bootargs} " \
-		"omapfb.mode=lcd:${lcdmode} " \
-		"omapdss.def_disp=${defaultdisplay} " \
 		"root=ubi0:root " \
-		"ubi.mtd=4 " \
+		"ubi.mtd=7 " \
 		"rootfstype=ubifs " \
-		"${kernelopts}\0" \
+		"ro\0" \
 	"loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
 	"bootscript=echo Running bootscript from mmc ...; " \
 		"source ${loadaddr}\0" \
 	"loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \
-	"eraseenv=nand unlock 0x260000 0x20000; nand erase 0x260000 0x20000\0" \
 	"mmcboot=echo Booting from mmc ...; " \
 		"run mmcargs; " \
 		"bootm ${loadaddr}\0" \
-	"loaduimage_ubi=mtd default; " \
-		"ubi part fs; " \
+	"loaduimage_ubi=ubi part ubi; " \
 		"ubifsmount ubi:root; " \
 		"ubifsload ${loadaddr} /boot/uImage\0" \
+	"loaduimage_nand=nand read ${loadaddr} kernel 0x500000\0" \
 	"nandboot=echo Booting from nand ...; " \
 		"run nandargs; " \
-		"run loaduimage_ubi; " \
+		"run loaduimage_nand; " \
 		"bootm ${loadaddr}\0" \
 	"autoboot=mmc dev ${mmcdev}; if mmc rescan; then " \
 			"if run loadbootscript; then " \
@@ -197,12 +278,12 @@
 			"fi; " \
 		"else run nandboot; fi\0"
 
-
-#define CONFIG_BOOTCOMMAND "run autoboot"
+#endif /* CONFIG_FLASHCARD */
 
 /* Miscellaneous configurable options */
 #define CONFIG_SYS_LONGHELP		/* undef to save memory */
 #define CONFIG_SYS_HUSH_PARSER		/* use "hush" command parser */
+#define CONFIG_CMDLINE_EDITING		/* enable cmdline history */
 #define CONFIG_AUTO_COMPLETE
 #define CONFIG_SYS_PROMPT		"OMAP3 Tricorder # "
 #define CONFIG_SYS_CBSIZE		512	/* Console I/O Buffer Size */
@@ -214,9 +295,9 @@
 /* Boot Argument Buffer Size */
 #define CONFIG_SYS_BARGSIZE		(CONFIG_SYS_CBSIZE)
 
-#define CONFIG_SYS_MEMTEST_START	(OMAP34XX_SDRC_CS0 + 0x07000000)
+#define CONFIG_SYS_MEMTEST_START	(OMAP34XX_SDRC_CS0 + 0x00000000)
 #define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_MEMTEST_START + \
-					0x01000000) /* 16MB */
+					0x07000000) /* 112 MB */
 
 #define CONFIG_SYS_LOAD_ADDR		(OMAP34XX_SDRC_CS0 + 0x02000000)
 
@@ -227,7 +308,6 @@
  */
 #define CONFIG_SYS_TIMERBASE		(OMAP34XX_GPT2)
 #define CONFIG_SYS_PTV			2 /* Divisor: 2^(PTV+1) => 8 */
-#define CONFIG_SYS_HZ			1000
 
 /*  Physical Memory Map  */
 #define CONFIG_NR_DRAM_BANKS		2 /* CS1 may or may not be populated */
@@ -239,9 +319,6 @@
 
 #define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 2 sectors */
 
-#define CONFIG_ENV_IS_IN_NAND		1
-#define CONFIG_ENV_OFFSET		0x260000 /* environment starts here */
-
 #define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
 #define CONFIG_SYS_INIT_RAM_ADDR	0x4020f800
 #define CONFIG_SYS_INIT_RAM_SIZE	0x800
@@ -259,6 +336,7 @@
 #define CONFIG_SPL_NAND_SIMPLE
 
 #define CONFIG_SPL_BOARD_INIT
+#define CONFIG_SPL_GPIO_SUPPORT
 #define CONFIG_SPL_LIBCOMMON_SUPPORT
 #define CONFIG_SPL_LIBDISK_SUPPORT
 #define CONFIG_SPL_I2C_SUPPORT
@@ -277,7 +355,7 @@
 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */
 
 #define CONFIG_SPL_TEXT_BASE		0x40200000 /*CONFIG_SYS_SRAM_START*/
-#define CONFIG_SPL_MAX_SIZE		(55 * 1024)	/* 7 KB for stack */
+#define CONFIG_SPL_MAX_SIZE		(57 * 1024)	/* 7 KB for stack */
 #define CONFIG_SPL_STACK		LOW_LEVEL_SRAM_STACK
 
 #define CONFIG_SPL_BSS_START_ADDR	0x80000000 /*CONFIG_SYS_SDRAM_BASE*/
@@ -290,21 +368,25 @@
 #define CONFIG_SYS_NAND_OOBSIZE		64
 #define CONFIG_SYS_NAND_BLOCK_SIZE	(128*1024)
 #define CONFIG_SYS_NAND_BAD_BLOCK_POS	NAND_LARGE_BADBLOCK_POS
-#define CONFIG_SYS_NAND_ECCPOS		{12, 13, 14, 15, 16, 17, 18, 19, 20,\
-			21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33,\
-			34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46,\
-			47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59,\
-			60, 61, 62, 63}
+#define CONFIG_SYS_NAND_ECCPOS		{2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, \
+					 13, 14, 16, 17, 18, 19, 20, 21, 22, \
+					 23, 24, 25, 26, 27, 28, 30, 31, 32, \
+					 33, 34, 35, 36, 37, 38, 39, 40, 41, \
+					 42, 44, 45, 46, 47, 48, 49, 50, 51, \
+					 52, 53, 54, 55, 56}
 
 #define CONFIG_SYS_NAND_ECCSIZE		512
 #define CONFIG_SYS_NAND_ECCBYTES	13
+#define CONFIG_NAND_OMAP_ECCSCHEME	OMAP_ECC_BCH8_CODE_HW_DETECTION_SW
 
 #define CONFIG_SYS_NAND_U_BOOT_START	CONFIG_SYS_TEXT_BASE
 
-#define CONFIG_SYS_NAND_U_BOOT_OFFS	0x80000
-#define CONFIG_SYS_NAND_U_BOOT_SIZE	0x200000
+#define CONFIG_SYS_NAND_U_BOOT_OFFS	0x20000
+#define CONFIG_SYS_NAND_U_BOOT_SIZE	0x100000
 
 #define CONFIG_SYS_SPL_MALLOC_START	0x80208000
 #define CONFIG_SYS_SPL_MALLOC_SIZE	0x100000	/* 1 MB */
 
+#define CONFIG_SYS_ALT_MEMTEST
+#define CONFIG_SYS_MEMTEST_SCRATCH	0x81000000
 #endif /* __CONFIG_H */
diff --git a/include/configs/trimslice.h b/include/configs/trimslice.h
index 8e03f6f4c4..f81cfa2e35 100644
--- a/include/configs/trimslice.h
+++ b/include/configs/trimslice.h
@@ -8,7 +8,7 @@
 #ifndef __CONFIG_H
 #define __CONFIG_H
 
-#include <asm/sizes.h>
+#include <linux/sizes.h>
 #include "tegra20-common.h"
 
 /* Enable fdt support for TrimSlice. Flash the image in u-boot-dtb.bin */
diff --git a/include/configs/trizepsiv.h b/include/configs/trizepsiv.h
index 885b3eeddc..b7804d2872 100644
--- a/include/configs/trizepsiv.h
+++ b/include/configs/trizepsiv.h
@@ -125,7 +125,6 @@
 
 #if defined(CONFIG_CMD_KGDB)
 #define CONFIG_KGDB_BAUDRATE	230400		/* speed to run kgdb serial port */
-#define CONFIG_KGDB_SER_INDEX	2		/* which serial port to use */
 #endif
 
 /*
@@ -137,7 +136,6 @@
 #ifdef CONFIG_SYS_HUSH_PARSER
 #define CONFIG_SYS_PROMPT		"$ "		/* Monitor Command Prompt */
 #else
-#define CONFIG_SYS_PROMPT		"=> "		/* Monitor Command Prompt */
 #endif
 #define CONFIG_SYS_CBSIZE		256		/* Console I/O Buffer Size	*/
 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
@@ -150,7 +148,6 @@
 
 #define CONFIG_SYS_LOAD_ADDR		0xa1000000	/* default load address */
 
-#define CONFIG_SYS_HZ			1000
 #define CONFIG_SYS_CPUSPEED		0x207		/* need to look more closely, I think this is Turbo = 2x, L=91Mhz */
 
 #ifdef CONFIG_MMC
diff --git a/include/configs/tseries.h b/include/configs/tseries.h
new file mode 100644
index 0000000000..8fb87ac441
--- /dev/null
+++ b/include/configs/tseries.h
@@ -0,0 +1,265 @@
+/*
+ * tseries.h
+ *
+ * specific parts for B&R T-Series Motherboard
+ *
+ * Copyright (C) 2013 Hannes Petermaier <oe5hpm@oevsv.at> -
+ * Bernecker & Rainer Industrieelektronik GmbH - http://www.br-automation.com
+ *
+ * SPDX-License-Identifier:        GPL-2.0+
+ */
+
+#ifndef __CONFIG_TSERIES_H__
+#define __CONFIG_TSERIES_H__
+
+#include <configs/bur_am335x_common.h>
+/* ------------------------------------------------------------------------- */
+/* Clock Defines */
+#define V_OSCK				26000000  /* Clock output from T2 */
+#define V_SCLK				(V_OSCK)
+
+#define CONFIG_POWER_TPS65217
+
+/* Support both device trees and ATAGs. */
+#define CONFIG_OF_LIBFDT
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+#define CONFIG_CMD_BOOTZ
+/*#define CONFIG_MACH_TYPE		3589*/
+#define CONFIG_MACH_TYPE		0xFFFFFFFF /* TODO: check with kernel*/
+
+/* MMC/SD IP block */
+#if defined(CONFIG_EMMC_BOOT)
+ #define CONFIG_MMC
+ #define CONFIG_GENERIC_MMC
+ #define CONFIG_OMAP_HSMMC
+ #define CONFIG_CMD_MMC
+ #define CONFIG_SUPPORT_EMMC_BOOT
+/* RAW SD card / eMMC locations. */
+ #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR	0x300 /*addr. 0x60000 */
+ #define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS		0x200 /* 256 KB */
+ #define CONFIG_SPL_MMC_SUPPORT
+#endif /* CONFIG_EMMC_BOOT */
+
+/*
+ * When we have SPI or NAND flash we expect to be making use of mtdparts,
+ * both for ease of use in U-Boot and for passing information on to
+ * the Linux kernel.
+ */
+#if defined(CONFIG_SPI_BOOT) || defined(CONFIG_NAND)
+#define CONFIG_MTD_DEVICE		/* Required for mtdparts */
+#define CONFIG_CMD_MTDPARTS
+#endif /* CONFIG_SPI_BOOT, ... */
+
+#undef CONFIG_SPL_OS_BOOT
+#ifdef CONFIG_SPL_OS_BOOT
+#define CONFIG_SYS_SPL_ARGS_ADDR		0x80F80000
+
+/* RAW SD card / eMMC */
+#define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR	0x900	/* address 0x120000 */
+#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR	0x80	/* address 0x10000 */
+#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS	0x80	/* 64KiB */
+
+/* NAND */
+#ifdef CONFIG_NAND
+#define CONFIG_CMD_SPL_NAND_OFS			0x080000 /* end of u-boot */
+#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS		0x140000
+#define CONFIG_CMD_SPL_WRITE_SIZE		0x2000
+#endif /* CONFIG_NAND */
+#endif /* CONFIG_SPL_OS_BOOT */
+
+#ifdef CONFIG_NAND
+#define CONFIG_SPL_NAND_AM33XX_BCH	/* OMAP4 and later ELM support */
+#define CONFIG_SPL_NAND_SUPPORT
+#define CONFIG_SPL_NAND_BASE
+#define CONFIG_SPL_NAND_DRIVERS
+#define CONFIG_SPL_NAND_ECC
+#define CONFIG_SYS_NAND_U_BOOT_START	CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_NAND_U_BOOT_OFFS	0x80000
+#endif /* CONFIG_NAND */
+
+/* Always 128 KiB env size */
+#define CONFIG_ENV_SIZE			(128 << 10)
+
+#ifdef CONFIG_NAND
+#define NANDARGS \
+	"mtdids=" MTDIDS_DEFAULT "\0" \
+	"mtdparts=" MTDPARTS_DEFAULT "\0" \
+	"nandargs=setenv bootargs console=${console} " \
+		"${optargs} " \
+		"root=${nandroot} " \
+		"rootfstype=${nandrootfstype}\0" \
+	"nandroot=ubi0:rootfs rw ubi.mtd=8,2048\0" \
+	"nandrootfstype=ubifs rootwait=1\0" \
+	"nandimgsize=0x500000\0" \
+	"nandboot=echo Booting from nand ...; " \
+		"run nandargs; " \
+		"nand read ${loadaddr} kernel ${nandimgsize}; " \
+		"bootz ${loadaddr}\0"
+#else
+#define NANDARGS ""
+#endif /* CONFIG_NAND */
+
+#ifdef CONFIG_MMC
+#define MMCARGS \
+	"silent=1\0"
+#else
+#define MMCARGS ""
+#endif /* CONFIG_MMC */
+
+#ifndef CONFIG_SPL_BUILD
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"autoload=0\0" \
+	"loadaddr=0x80200000\0" \
+	"bootfile=zImage\0" \
+	"console=ttyO0,115200n8\0" \
+	"optargs=\0" \
+	"rootpath=/tftpboot/tseries/rootfs-small\0" \
+	"nfsopts=nolock\0" \
+	"netargs=setenv bootargs console=${console} " \
+		"${optargs} " \
+		"root=/dev/nfs " \
+		"nfsroot=${serverip}:${rootpath},${nfsopts} rw " \
+		"ip=dhcp\0" \
+	"netboot=echo Booting from network ...; " \
+		"setenv autoload no; " \
+		"dhcp; " \
+		"tftp ${loadaddr} ${bootfile}; " \
+		"run netargs; " \
+		"bootm ${loadaddr}\0" \
+	"usbupdate=echo Updating UBOOT from USB-Stick ...; " \
+		"usb start; " \
+		"fatload usb 0 0x80000000 updateubootusb.img; " \
+		"source;\0" \
+	"netupdate=echo Updating UBOOT from Network (TFTP) ...; " \
+		"setenv autoload 0; " \
+		"dhcp;" \
+		"tftp 0x80000000 updateUBOOT.img;" \
+		"source;\0" \
+	NANDARGS \
+	MMCARGS
+#endif /* !CONFIG_SPL_BUILD*/
+
+#define CONFIG_BOOTCOMMAND \
+	"run mmcboot1;"
+#define CONFIG_BOOTDELAY		1 /* TODO: für release auf 0 setzen */
+
+#ifdef CONFIG_NAND
+/*
+ * GPMC  block.  We support 1 device and the physical address to
+ * access CS0 at is 0x8000000.
+ */
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+#define CONFIG_SYS_NAND_BASE		0x8000000
+#define CONFIG_NAND_OMAP_GPMC
+#define CONFIG_CMD_NAND
+/* don't change OMAP_ELM, ECCSCHEME. ROM code only supports this */
+#define CONFIG_NAND_OMAP_ELM
+#define CONFIG_NAND_OMAP_ECCSCHEME	OMAP_ECC_BCH8_CODE_HW
+#define GPMC_NAND_ECC_LP_x16_LAYOUT	1
+#define CONFIG_SYS_NAND_5_ADDR_CYCLE
+#define CONFIG_SYS_NAND_BLOCK_SIZE	(128*1024)
+#define CONFIG_SYS_NAND_PAGE_SIZE	2048
+#define CONFIG_SYS_NAND_PAGE_COUNT	(CONFIG_SYS_NAND_BLOCK_SIZE / \
+					CONFIG_SYS_NAND_PAGE_SIZE)
+#define CONFIG_SYS_NAND_OOBSIZE		64
+#define CONFIG_SYS_NAND_BAD_BLOCK_POS	NAND_LARGE_BADBLOCK_POS
+#define CONFIG_SYS_NAND_ECCPOS		{2, 3, 4, 5, 6, 7, 8, 9, \
+					10, 11, 12, 13, 14, 15, 16, 17, \
+					18, 19, 20, 21, 22, 23, 24, 25, \
+					26, 27, 28, 29, 30, 31, 32, 33, \
+					34, 35, 36, 37, 38, 39, 40, 41, \
+					42, 43, 44, 45, 46, 47, 48, 49, \
+					50, 51, 52, 53, 54, 55, 56, 57, }
+
+#define CONFIG_SYS_NAND_ECCSIZE		512
+#define CONFIG_SYS_NAND_ECCBYTES	14
+
+#define CONFIG_SYS_NAND_U_BOOT_START	CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_NAND_U_BOOT_OFFS	0x80000
+
+#define MTDIDS_DEFAULT			"nand0=omap2-nand.0"
+#define MTDPARTS_DEFAULT		"mtdparts=omap2-nand.0:" \
+					"128k(SPL)," \
+					"128k(SPL.backup1)," \
+					"128k(SPL.backup2)," \
+					"128k(SPL.backup3)," \
+					"512k(u-boot)," \
+					"128k(u-boot-spl-os)," \
+					"128k(u-boot-env)," \
+					"5m(kernel),"\
+					"-(rootfs)"
+#endif /* CONFIG_NAND */
+
+/* USB configuration */
+#define CONFIG_USB_MUSB_DSPS
+#define CONFIG_ARCH_MISC_INIT
+#define CONFIG_MUSB_PIO_ONLY
+#define CONFIG_MUSB_DISABLE_BULK_COMBINE_SPLIT
+/* attention! not only for gadget, enables also highspeed in hostmode */
+#define CONFIG_USB_GADGET_DUALSPEED
+#define CONFIG_MUSB_HOST
+#define CONFIG_AM335X_USB0
+#define CONFIG_AM335X_USB0_MODE	MUSB_HOST
+#define CONFIG_AM335X_USB1
+#define CONFIG_AM335X_USB1_MODE MUSB_HOST
+
+#ifdef CONFIG_MUSB_HOST
+#define CONFIG_CMD_USB
+#define CONFIG_USB_STORAGE
+#endif /* CONFIG_MUSB_HOST */
+
+#if defined(CONFIG_SPI_BOOT)
+/* McSPI IP block */
+#define CONFIG_SPI
+#define CONFIG_OMAP3_SPI
+#define CONFIG_CMD_SPI
+#define CONFIG_CMD_SF
+#define CONFIG_SPI_FLASH
+#define CONFIG_SPI_FLASH_STMICRO
+#define CONFIG_SF_DEFAULT_SPEED		24000000
+
+#define CONFIG_SPL_SPI_SUPPORT
+#define CONFIG_SPL_SPI_FLASH_SUPPORT
+#define CONFIG_SPL_SPI_LOAD
+#define CONFIG_SPL_SPI_BUS		0
+#define CONFIG_SPL_SPI_CS		0
+#define CONFIG_SYS_SPI_U_BOOT_OFFS	0x20000
+#undef CONFIG_ENV_IS_NOWHERE
+#define CONFIG_ENV_IS_IN_SPI_FLASH
+#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
+#define CONFIG_ENV_SPI_MAX_HZ		CONFIG_SF_DEFAULT_SPEED
+#define CONFIG_ENV_SECT_SIZE		(4 << 10) /* 4 KB sectors */
+#define CONFIG_ENV_OFFSET		(768 << 10) /* 768 KiB in */
+#define CONFIG_ENV_OFFSET_REDUND	(896 << 10) /* 896 KiB in */
+
+#elif defined(CONFIG_EMMC_BOOT)
+#undef CONFIG_ENV_IS_NOWHERE
+#define CONFIG_ENV_IS_IN_MMC
+#define CONFIG_SYS_MMC_ENV_DEV		1
+#define CONFIG_SYS_MMC_ENV_PART		2
+#define CONFIG_ENV_OFFSET		0x40000	/* TODO: Adresse definieren */
+#define CONFIG_ENV_OFFSET_REDUND	(CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
+#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
+
+#elif defined(CONFIG_NAND)
+#undef CONFIG_ENV_IS_NOWHERE
+#define CONFIG_ENV_IS_IN_NAND
+#define CONFIG_ENV_OFFSET		0x120000 /* TODO: Adresse definieren */
+#define CONFIG_SYS_ENV_SECT_SIZE	CONFIG_ENV_SIZE
+#else
+#error "no storage for Environment defined!"
+#endif
+/*
+ * Common filesystems support.  When we have removable storage we
+ * enabled a number of useful commands and support.
+ */
+#if defined(CONFIG_MMC) || defined(CONFIG_USB_STORAGE)
+#define CONFIG_DOS_PARTITION
+#define CONFIG_CMD_FAT
+#define CONFIG_FAT_WRITE
+#define CONFIG_CMD_FS_GENERIC
+#endif /* CONFIG_MMC, ... */
+
+#endif	/* ! __CONFIG_TSERIES_H__ */
diff --git a/include/configs/tt01.h b/include/configs/tt01.h
index 5942bdf21d..0937653fc2 100644
--- a/include/configs/tt01.h
+++ b/include/configs/tt01.h
@@ -239,8 +239,6 @@
 /* Boot Argument Buffer Size */
 #define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE
 
-#define CONFIG_SYS_HZ			1000
-
 #define CONFIG_CMDLINE_EDITING
 
 /* MMC boot support */
diff --git a/include/configs/twister.h b/include/configs/twister.h
index b6ca59c33c..f24dc136ca 100644
--- a/include/configs/twister.h
+++ b/include/configs/twister.h
@@ -50,4 +50,7 @@
 #define CONFIG_SYS_SPL_ARGS_ADDR	(PHYS_SDRAM_1 + 0x100)
 #define CONFIG_SPL_BOARD_INIT
 
+/* gpio 55 is used as SPL_OS_BOOT_KEY */
+#define CONFIG_OMAP3_GPIO_2
+
 #endif /* __CONFIG_H */
diff --git a/include/configs/tx25.h b/include/configs/tx25.h
index 6910036492..5ac6e6441c 100644
--- a/include/configs/tx25.h
+++ b/include/configs/tx25.h
@@ -15,7 +15,9 @@
  */
 #define CONFIG_MX25
 #define CONFIG_MX25_CLK32		32000	/* OSC32K frequency */
-#define CONFIG_SYS_HZ			1000
+#define CONFIG_SYS_TIMER_RATE		CONFIG_MX25_CLK32
+#define CONFIG_SYS_TIMER_COUNTER	\
+	(&((struct gpt_regs *)IMX_GPT1_BASE)->counter)
 
 #define	CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* 256 kB for U-Boot */
 
@@ -110,7 +112,6 @@
 #define CONFIG_SYS_NAND_LARGEPAGE
 
 /* U-Boot general configuration */
-#define CONFIG_SYS_PROMPT	"=> "	/* Monitor Command Prompt */
 #define CONFIG_SYS_CBSIZE	1024	/* Console I/O Buffer Size  */
 /* Print buffer sz */
 #define CONFIG_SYS_PBSIZE	(CONFIG_SYS_CBSIZE + \
diff --git a/include/configs/u8500_href.h b/include/configs/u8500_href.h
index 0c97ab1894..8d7970a376 100644
--- a/include/configs/u8500_href.h
+++ b/include/configs/u8500_href.h
@@ -12,11 +12,9 @@
  * (easy to change)
  */
 #define CONFIG_U8500
-#define CONFIG_L2_OFF
 
 #define CONFIG_SYS_MEMTEST_START	0x00000000
 #define CONFIG_SYS_MEMTEST_END	0x1FFFFFFF
-#define CONFIG_SYS_HZ		1000		/* must be 1000 */
 
 #define CONFIG_BOARD_EARLY_INIT_F
 #define CONFIG_BOARD_LATE_INIT
@@ -31,7 +29,6 @@
 #define CONFIG_ENV_SIZE		(128*1024)
 #define CONFIG_SYS_MALLOC_LEN	(CONFIG_ENV_SIZE + 256*1024)
 #endif
-#define CONFIG_SYS_GBL_DATA_SIZE	128	/* for initial data */
 
 /*
  * PL011 Configuration
diff --git a/include/configs/uc100.h b/include/configs/uc100.h
index faae7ffd26..cad897f70b 100644
--- a/include/configs/uc100.h
+++ b/include/configs/uc100.h
@@ -141,7 +141,6 @@
  * Miscellaneous configurable options
  */
 #define	CONFIG_SYS_LONGHELP			/* undef to save memory		*/
-#define	CONFIG_SYS_PROMPT		"=> "	/* Monitor Command Prompt	*/
 
 #if 0
 #define	CONFIG_SYS_HUSH_PARSER		1	/* use "hush" command parser	*/
@@ -161,8 +160,6 @@
 
 #define	CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address	*/
 
-#define	CONFIG_SYS_HZ			1000	/* decrementer freq: 1 ms ticks	*/
-
 #define CONFIG_AUTO_COMPLETE	1       /* add autocompletion support   */
 
 /*
diff --git a/include/configs/udoo.h b/include/configs/udoo.h
new file mode 100644
index 0000000000..a0306de6a3
--- /dev/null
+++ b/include/configs/udoo.h
@@ -0,0 +1,234 @@
+/*
+ * Copyright (C) 2013 Freescale Semiconductor, Inc.
+ *
+ * Configuration settings for Udoo board.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include "mx6_common.h"
+#include <asm/arch/imx-regs.h>
+#include <asm/imx-common/gpio.h>
+#include <linux/sizes.h>
+
+#define CONFIG_MX6
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DISPLAY_BOARDINFO
+
+#define MACH_TYPE_UDOO		4800
+#define CONFIG_MACH_TYPE	MACH_TYPE_UDOO
+
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+#define CONFIG_REVISION_TAG
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN		(2 * SZ_1M)
+
+#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_MXC_GPIO
+
+#define CONFIG_MXC_UART
+#define CONFIG_MXC_UART_BASE		UART2_BASE
+
+/* SATA Configs */
+
+#define CONFIG_CMD_SATA
+#ifdef CONFIG_CMD_SATA
+#define CONFIG_DWC_AHSATA
+#define CONFIG_SYS_SATA_MAX_DEVICE	1
+#define CONFIG_DWC_AHSATA_PORT_ID	0
+#define CONFIG_DWC_AHSATA_BASE_ADDR	SATA_ARB_BASE_ADDR
+#define CONFIG_LBA48
+#define CONFIG_LIBATA
+#endif
+
+/* Network support */
+
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NET
+#define CONFIG_FEC_MXC
+#define CONFIG_MII
+#define IMX_FEC_BASE                    ENET_BASE_ADDR
+#define CONFIG_FEC_XCV_TYPE             RGMII
+#define CONFIG_ETHPRIME                 "FEC"
+#define CONFIG_FEC_MXC_PHYADDR          6
+#define CONFIG_PHYLIB
+#define CONFIG_PHY_MICREL
+#define CONFIG_PHY_MICREL_KSZ9031
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_CONS_INDEX		1
+#define CONFIG_BAUDRATE			115200
+
+/* Command definition */
+#include <config_cmd_default.h>
+
+#undef CONFIG_CMD_IMLS
+
+#define CONFIG_CMD_BMODE
+#define CONFIG_CMD_SETEXPR
+
+#define CONFIG_BOOTDELAY		3
+
+#define CONFIG_SYS_MEMTEST_START	0x10000000
+#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_MEMTEST_START + 500 * SZ_1M)
+#define CONFIG_LOADADDR			0x12000000
+#define CONFIG_SYS_TEXT_BASE		0x17800000
+
+/* MMC Configuration */
+#define CONFIG_FSL_ESDHC
+#define CONFIG_FSL_USDHC
+#define CONFIG_SYS_FSL_ESDHC_ADDR	0
+
+#define CONFIG_MMC
+#define CONFIG_CMD_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_BOUNCE_BUFFER
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_FAT
+#define CONFIG_DOS_PARTITION
+
+#define CONFIG_DEFAULT_FDT_FILE		"imx6q-udoo.dtb"
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"script=boot.scr\0" \
+	"image=zImage\0" \
+	"console=ttymxc1\0" \
+	"splashpos=m,m\0" \
+	"fdt_high=0xffffffff\0" \
+	"initrd_high=0xffffffff\0" \
+	"fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \
+	"fdt_addr=0x18000000\0" \
+	"boot_fdt=try\0" \
+	"ip_dyn=yes\0" \
+	"mmcdev=0\0" \
+	"mmcpart=1\0" \
+	"mmcroot=/dev/mmcblk0p2 rootwait rw\0" \
+	"update_sd_firmware_filename=u-boot.imx\0" \
+	"update_sd_firmware=" \
+		"if test ${ip_dyn} = yes; then " \
+			"setenv get_cmd dhcp; " \
+		"else " \
+			"setenv get_cmd tftp; " \
+		"fi; " \
+		"if mmc dev ${mmcdev}; then "	\
+			"if ${get_cmd} ${update_sd_firmware_filename}; then " \
+				"setexpr fw_sz ${filesize} / 0x200; " \
+				"setexpr fw_sz ${fw_sz} + 1; "	\
+				"mmc write ${loadaddr} 0x2 ${fw_sz}; " \
+			"fi; "	\
+		"fi\0" \
+	"mmcargs=setenv bootargs console=${console},${baudrate} " \
+		"root=${mmcroot}\0" \
+	"loadbootscript=" \
+		"fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
+	"bootscript=echo Running bootscript from mmc ...; " \
+		"source\0" \
+	"loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
+	"loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
+	"mmcboot=echo Booting from mmc ...; " \
+		"run mmcargs; " \
+		"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
+			"if run loadfdt; then " \
+				"bootz ${loadaddr} - ${fdt_addr}; " \
+			"else " \
+				"if test ${boot_fdt} = try; then " \
+					"bootz; " \
+				"else " \
+					"echo WARN: Cannot load the DT; " \
+				"fi; " \
+			"fi; " \
+		"else " \
+			"bootz; " \
+		"fi;\0" \
+	"netargs=setenv bootargs console=${console},${baudrate} " \
+		"root=/dev/nfs " \
+	"ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
+		"netboot=echo Booting from net ...; " \
+		"run netargs; " \
+		"if test ${ip_dyn} = yes; then " \
+			"setenv get_cmd dhcp; " \
+		"else " \
+			"setenv get_cmd tftp; " \
+		"fi; " \
+		"${get_cmd} ${image}; " \
+		"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
+			"if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
+				"bootz ${loadaddr} - ${fdt_addr}; " \
+			"else " \
+				"if test ${boot_fdt} = try; then " \
+					"bootz; " \
+				"else " \
+					"echo WARN: Cannot load the DT; " \
+				"fi; " \
+			"fi; " \
+		"else " \
+			"bootz; " \
+		"fi;\0"
+
+#define CONFIG_BOOTCOMMAND \
+	   "mmc dev ${mmcdev}; if mmc rescan; then " \
+		   "if run loadbootscript; then " \
+			   "run bootscript; " \
+		   "else " \
+			   "if run loadimage; then " \
+				   "run mmcboot; " \
+			   "else run netboot; " \
+			   "fi; " \
+		   "fi; " \
+	   "else run netboot; fi"
+
+/* Miscellaneous configurable options */
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT	       "=> "
+#define CONFIG_AUTO_COMPLETE
+#define CONFIG_SYS_CBSIZE		256
+
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS	       16
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
+
+#define CONFIG_SYS_LOAD_ADDR		CONFIG_LOADADDR
+
+#define CONFIG_CMDLINE_EDITING
+
+/* Physical Memory Map */
+#define CONFIG_NR_DRAM_BANKS		1
+#define PHYS_SDRAM			MMDC0_ARB_BASE_ADDR
+
+#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM
+#define CONFIG_SYS_INIT_RAM_ADDR	IRAM_BASE_ADDR
+#define CONFIG_SYS_INIT_RAM_SIZE	IRAM_SIZE
+
+#define CONFIG_SYS_INIT_SP_OFFSET \
+	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR \
+	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+
+/* FLASH and environment organization */
+#define CONFIG_SYS_NO_FLASH
+
+#define CONFIG_ENV_SIZE			(8 * 1024)
+
+#define CONFIG_ENV_IS_IN_MMC
+#define CONFIG_ENV_OFFSET		(6 * 64 * 1024)
+#define CONFIG_SYS_MMC_ENV_DEV		0
+
+#define CONFIG_OF_LIBFDT
+#define CONFIG_CMD_BOOTZ
+
+#ifndef CONFIG_SYS_DCACHE_OFF
+#define CONFIG_CMD_CACHE
+#endif
+
+#endif			       /* __CONFIG_H * */
diff --git a/include/configs/usb_a9263.h b/include/configs/usb_a9263.h
new file mode 100644
index 0000000000..3c54870783
--- /dev/null
+++ b/include/configs/usb_a9263.h
@@ -0,0 +1,168 @@
+/*
+ * (C) Copyright 2007-2013
+ * Stelian Pop <stelian.pop@leadtechdesign.com>
+ * Lead Tech Design <www.leadtechdesign.com>
+ * Thomas Petazzoni, Free Electrons, <thomas.petazzoni@free-electrons.com>
+ * Mateusz Kulikowski <mateusz.kulikowski@gmail.com>
+ *
+ * Settings for Calao USB-A9263 board
+ *
+ * U-Boot image has to be less than 200704 bytes, otherwise at91bootstrap
+ * installed on board will not be able to load it properly.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+#include <asm/hardware.h>
+
+/* ARM asynchronous clock */
+#define CONFIG_SYS_AT91_MAIN_CLOCK	12000000	/* 12 MHz crystal */
+#define CONFIG_SYS_AT91_SLOW_CLOCK	32768
+
+#define CONFIG_MACH_TYPE		MACH_TYPE_USB_A9263
+
+#define CONFIG_ARCH_CPU_INIT
+
+#define CONFIG_CMDLINE_TAG	/* enable passing of ATAGs      */
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+
+#define CONFIG_SKIP_LOWLEVEL_INIT
+
+#define CONFIG_DISPLAY_CPUINFO
+
+#define CONFIG_OF_LIBFDT
+#define CONFIG_SYS_GENERIC_BOARD
+#define CONFIG_SYS_TEXT_BASE		0x23f00000
+
+/*
+ * Hardware drivers
+ */
+#define CONFIG_AT91_GPIO
+
+/* serial console */
+#define CONFIG_ATMEL_USART
+#define CONFIG_USART_BASE		ATMEL_BASE_DBGU
+#define CONFIG_USART_ID			ATMEL_ID_SYS
+#define CONFIG_BAUDRATE			115200
+
+#define CONFIG_BOOTDELAY 3
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+#undef CONFIG_CMD_BDI
+#undef CONFIG_CMD_FPGA
+#undef CONFIG_CMD_IMI
+#undef CONFIG_CMD_IMLS
+#undef CONFIG_CMD_ITEST
+#undef CONFIG_CMD_LOADB
+#undef CONFIG_CMD_LOADS
+
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_NAND
+
+/* SDRAM */
+#define CONFIG_NR_DRAM_BANKS		1
+#define CONFIG_SYS_SDRAM_BASE		ATMEL_BASE_CS1
+#define CONFIG_SYS_SDRAM_SIZE		0x04000000
+
+#define CONFIG_SYS_INIT_SP_ADDR \
+	(ATMEL_BASE_SRAM1 + 0x1000 - GENERATED_GBL_DATA_SIZE)
+
+/* DataFlash */
+#define CONFIG_ATMEL_DATAFLASH_SPI
+#define CONFIG_HAS_DATAFLASH
+#define CONFIG_SYS_SPI_WRITE_TOUT		(5*CONFIG_SYS_HZ)
+#define CONFIG_SYS_MAX_DATAFLASH_BANKS		1
+#define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0	0xC0000000
+#define AT91_SPI_CLK				8000000
+#define DATAFLASH_TCSS				(0x1a << 16)
+#define DATAFLASH_TCHS				(0x1 << 24)
+
+/* no NOR flash */
+#define CONFIG_SYS_NO_FLASH
+
+/* NAND flash */
+#ifdef CONFIG_CMD_NAND
+#define CONFIG_NAND_ATMEL
+#define CONFIG_SYS_MAX_NAND_DEVICE		1
+#define CONFIG_SYS_NAND_BASE			ATMEL_BASE_CS3
+/* our ALE is AD21 */
+#define CONFIG_SYS_NAND_MASK_ALE		(1 << 21)
+/* our CLE is AD22 */
+#define CONFIG_SYS_NAND_MASK_CLE		(1 << 22)
+#define CONFIG_SYS_NAND_ENABLE_PIN		GPIO_PIN_PD(15)
+#define CONFIG_SYS_NAND_READY_PIN		GPIO_PIN_PA(22)
+#endif
+
+#define MTDPARTS_DEFAULT \
+	"mtdparts=atmel_nand:16m(kernel)ro,120m(root1),-(root2)"
+
+/* Ethernet */
+#define CONFIG_MACB
+#define CONFIG_RMII
+#define CONFIG_NET_RETRY_COUNT			20
+#define CONFIG_AT91_WANTS_COMMON_PHY
+
+/* USB */
+#ifdef CONFIG_CMD_USB
+#define CONFIG_USB_ATMEL
+#define CONFIG_USB_OHCI_NEW
+#define CONFIG_DOS_PARTITION
+#define CONFIG_SYS_USB_OHCI_CPU_INIT
+#define CONFIG_SYS_USB_OHCI_REGS_BASE		0x00a00000
+#define CONFIG_SYS_USB_OHCI_SLOT_NAME		"at91sam9263"
+#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS	2
+#define CONFIG_USB_STORAGE
+#define CONFIG_CMD_FAT
+#endif
+
+#define CONFIG_SYS_LOAD_ADDR			0x22000000
+
+#define CONFIG_SYS_MEMTEST_START		CONFIG_SYS_SDRAM_BASE
+#define CONFIG_SYS_MEMTEST_END			0x23e00000
+
+/* bootstrap + u-boot + env in dataflash on CS0 */
+#define CONFIG_ENV_IS_IN_DATAFLASH
+#define CONFIG_SYS_MONITOR_BASE	(CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 + 0x4000)
+#define CONFIG_ENV_OFFSET	0x2000
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 + \
+				 CONFIG_ENV_OFFSET)
+#define CONFIG_ENV_SIZE		0x2000
+#define CONFIG_BOOTCOMMAND	"nboot 21000000 0"
+#define CONFIG_BOOTARGS		"console=ttyS0,115200 " \
+	"root=/dev/mtdblock1 " \
+	"mtdparts=" MTDPARTS_DEFAULT " " \
+	"rw rootfstype=jffs2"
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"mtdparts=" MTDPARTS_DEFAULT "\0" \
+
+#define CONFIG_SYS_PROMPT		"U-Boot> "
+#define CONFIG_SYS_CBSIZE		256
+#define CONFIG_SYS_MAXARGS		16
+#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
+					 sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_CMDLINE_EDITING
+#define CONFIG_AUTO_COMPLETE
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_LONGHELP
+
+/*
+ * Size of malloc() pool
+ */
+#define CONFIG_SYS_MALLOC_LEN	ROUND(3 * CONFIG_ENV_SIZE + 128*1024, 0x1000)
+
+#endif
diff --git a/include/configs/utx8245.h b/include/configs/utx8245.h
index 8f4a4702ac..5be62ecb2d 100644
--- a/include/configs/utx8245.h
+++ b/include/configs/utx8245.h
@@ -30,7 +30,6 @@
  * (easy to change)
  */
 
-#define CONFIG_MPC824X		1
 #define CONFIG_MPC8245		1
 #define CONFIG_UTX8245		1
 
@@ -107,7 +106,6 @@ protect on ${u-boot_startaddr} ${u-boot_endaddr}"
  * Miscellaneous configurable options
  */
 #define CONFIG_SYS_LONGHELP				/* undef to save memory		*/
-#define CONFIG_SYS_PROMPT	"=> "			/* Monitor Command Prompt	*/
 #define CONFIG_SYS_CBSIZE	256				/* Console I/O Buffer Size	*/
 
 /* Print Buffer Size */
@@ -209,7 +207,6 @@ protect on ${u-boot_startaddr} ${u-boot_endaddr}"
  *------------------------------------------------------------------*/
 
 #define CONFIG_SYS_CLK_FREQ  33000000
-#define CONFIG_SYS_HZ				1000
 
 /*#define CONFIG_SYS_ETH_DEV_FN	     0x7800 */
 /*#define CONFIG_SYS_ETH_IOBASE	     0x00104000 */
diff --git a/include/configs/v37.h b/include/configs/v37.h
index 0fa55d6f3a..0d01fe207e 100644
--- a/include/configs/v37.h
+++ b/include/configs/v37.h
@@ -110,7 +110,6 @@
  * Miscellaneous configurable options
  */
 #define	CONFIG_SYS_LONGHELP			/* undef to save memory		*/
-#define	CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt	*/
 #if defined(CONFIG_CMD_KGDB)
 #define	CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
 #else
@@ -125,8 +124,6 @@
 
 #define	CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address	*/
 
-#define	CONFIG_SYS_HZ		1000		/* decrementer freq: 1 ms ticks	*/
-
 /*
  * Low Level Configuration Settings
  * (address mappings, register initial values, etc.)
diff --git a/include/configs/v38b.h b/include/configs/v38b.h
index 501010eb9c..7f6b0c7cb2 100644
--- a/include/configs/v38b.h
+++ b/include/configs/v38b.h
@@ -12,7 +12,6 @@
  * High Level Configuration Options
  * (easy to change)
  */
-#define CONFIG_MPC5xxx			1	/* This is an MPC5xxx CPU */
 #define CONFIG_MPC5200			1	/* This is an MPC5200 CPU */
 #define CONFIG_V38B			1	/* ...on V38B board */
 
@@ -244,7 +243,6 @@
  * Miscellaneous configurable options
  */
 #define CONFIG_SYS_LONGHELP			/* undef to save memory */
-#define CONFIG_SYS_PROMPT		"=> "	/* Monitor Command Prompt */
 #if defined(CONFIG_CMD_KGDB)
 #define CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size */
 #else
@@ -259,8 +257,6 @@
 
 #define CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address */
 
-#define CONFIG_SYS_HZ			1000	/* decrementer freq: 1 ms ticks */
-
 #define CONFIG_SYS_CACHELINE_SIZE	32	/* For MPC5xxx CPUs */
 #if defined(CONFIG_CMD_KGDB)
 #  define CONFIG_SYS_CACHELINE_SHIFT	5	/* log base 2 of the above value */
diff --git a/include/configs/vct.h b/include/configs/vct.h
index 85a6c11137..5ab4de3274 100644
--- a/include/configs/vct.h
+++ b/include/configs/vct.h
@@ -25,10 +25,8 @@
 #ifndef __CONFIG_H
 #define __CONFIG_H
 
-#define CONFIG_MIPS32				/* MIPS 4Kc CPU core	*/
 #define CPU_CLOCK_RATE			324000000 /* Clock for the MIPS core */
 #define CONFIG_SYS_MIPS_TIMER_FREQ	(CPU_CLOCK_RATE / 2)
-#define CONFIG_SYS_HZ			1000
 
 #define CONFIG_SKIP_LOWLEVEL_INIT	/* SDRAM is initialized by the bootstrap code */
 
diff --git a/include/configs/ve8313.h b/include/configs/ve8313.h
index 5527511df2..00787bbb28 100644
--- a/include/configs/ve8313.h
+++ b/include/configs/ve8313.h
@@ -17,7 +17,6 @@
  * High Level Configuration Options
  */
 #define CONFIG_E300		1
-#define CONFIG_MPC83xx		1
 #define CONFIG_MPC831x		1
 #define CONFIG_MPC8313		1
 #define CONFIG_VE8313		1
@@ -345,13 +344,11 @@
  */
 #define CONFIG_SYS_LONGHELP			/* undef to save memory */
 #define CONFIG_SYS_LOAD_ADDR	0x100000	/* default load address */
-#define CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt */
 #define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size */
 
 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
 #define CONFIG_SYS_MAXARGS	16		/* max number of cmd args */
 #define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE /* Boot arg Buffer size */
-#define CONFIG_SYS_HZ		1000		/* 1ms ticks */
 
 /*
  * For booting Linux, the board info and command line data
diff --git a/include/configs/venice2.h b/include/configs/venice2.h
new file mode 100644
index 0000000000..2d75f5013f
--- /dev/null
+++ b/include/configs/venice2.h
@@ -0,0 +1,79 @@
+/*
+ * (C) Copyright 2013-2014
+ * NVIDIA Corporation <www.nvidia.com>
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <linux/sizes.h>
+
+#include "tegra124-common.h"
+
+/* Enable fdt support for Venice2. Flash the image in u-boot-dtb.bin */
+#define CONFIG_DEFAULT_DEVICE_TREE	tegra124-venice2
+#define CONFIG_OF_CONTROL
+#define CONFIG_OF_SEPARATE
+
+/* High-level configuration options */
+#define V_PROMPT			"Tegra124 (Venice2) # "
+#define CONFIG_TEGRA_BOARD_STRING	"NVIDIA Venice2"
+
+/* Board-specific serial config */
+#define CONFIG_SERIAL_MULTI
+#define CONFIG_TEGRA_ENABLE_UARTA
+#define CONFIG_SYS_NS16550_COM1		NV_PA_APB_UARTA_BASE
+
+#define CONFIG_BOARD_EARLY_INIT_F
+
+/* I2C */
+#define CONFIG_SYS_I2C_TEGRA
+#define CONFIG_SYS_I2C_INIT_BOARD
+#define CONFIG_I2C_MULTI_BUS
+#define CONFIG_SYS_MAX_I2C_BUS		TEGRA_I2C_NUM_CONTROLLERS
+#define CONFIG_SYS_I2C_SPEED		100000
+#define CONFIG_CMD_I2C
+#define CONFIG_SYS_I2C
+
+/* SD/MMC */
+#define CONFIG_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_TEGRA_MMC
+#define CONFIG_CMD_MMC
+
+/* Environment in eMMC, at the end of 2nd "boot sector" */
+#define CONFIG_ENV_IS_IN_MMC
+#define CONFIG_SYS_MMC_ENV_DEV		0
+#define CONFIG_SYS_MMC_ENV_PART		2
+#define CONFIG_ENV_OFFSET		(-CONFIG_ENV_SIZE)
+
+/* SPI */
+#define CONFIG_TEGRA114_SPI		/* Compatible w/ Tegra114 SPI */
+#define CONFIG_TEGRA114_SPI_CTRLS	6
+#define CONFIG_SPI_FLASH
+#define CONFIG_SPI_FLASH_WINBOND
+#define CONFIG_SF_DEFAULT_MODE         SPI_MODE_0
+#define CONFIG_SF_DEFAULT_SPEED        24000000
+#define CONFIG_CMD_SPI
+#define CONFIG_CMD_SF
+#define CONFIG_SPI_FLASH_SIZE          (4 << 20)
+
+/* USB Host support */
+#define CONFIG_USB_EHCI
+#define CONFIG_USB_EHCI_TEGRA
+#define CONFIG_USB_STORAGE
+#define CONFIG_CMD_USB
+
+/* USB networking support */
+#define CONFIG_USB_HOST_ETHER
+#define CONFIG_USB_ETHER_ASIX
+
+/* General networking support */
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_DHCP
+
+#include "tegra-common-post.h"
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/ventana.h b/include/configs/ventana.h
index 5c02c968f9..edf3720b61 100644
--- a/include/configs/ventana.h
+++ b/include/configs/ventana.h
@@ -8,7 +8,7 @@
 #ifndef __CONFIG_H
 #define __CONFIG_H
 
-#include <asm/sizes.h>
+#include <linux/sizes.h>
 #include "tegra20-common.h"
 
 /* Enable fdt support for Ventana. Flash the image in u-boot-dtb.bin */
diff --git a/include/configs/versatile.h b/include/configs/versatile.h
index 36daeb34a0..29c32fee51 100644
--- a/include/configs/versatile.h
+++ b/include/configs/versatile.h
@@ -25,12 +25,11 @@
 
 #define CONFIG_SYS_MEMTEST_START	0x100000
 #define CONFIG_SYS_MEMTEST_END		0x10000000
-#define CONFIG_SYS_HZ			(1000000 / 256)
-#define CONFIG_SYS_TIMERBASE		0x101E2000	/* Timer 0 and 1 base */
 
-#define CONFIG_SYS_TIMER_INTERVAL	10000
-#define CONFIG_SYS_TIMER_RELOAD		(CONFIG_SYS_TIMER_INTERVAL >> 4)
-#define CONFIG_SYS_TIMER_CTRL		0x84		/* Enable, Clock / 16 */
+#define CONFIG_SYS_TIMERBASE		0x101E2000	/* Timer 0 and 1 base */
+#define CONFIG_SYS_TIMER_RATE		(1000000 / 256)
+#define CONFIG_SYS_TIMER_COUNTER	(CONFIG_SYS_TIMERBASE + 0x4)
+#define CONFIG_SYS_TIMER_COUNTS_DOWN
 
 /*
  * control registers
@@ -102,7 +101,8 @@
 
 #define CONFIG_BOOTDELAY	2
 #define CONFIG_BOOTARGS		"root=/dev/nfs mem=128M ip=dhcp "\
-				"netdev=25,0,0xf1010000,0xf1010010,eth0"
+				"netdev=25,0,0xf1010000,0xf1010010,eth0 "\
+				"console=ttyAMA0,38400n1"
 
 /*
  * Static configuration when assigning fixed address
diff --git a/include/configs/vexpress_aemv8a.h b/include/configs/vexpress_aemv8a.h
new file mode 100644
index 0000000000..dff6adcc7c
--- /dev/null
+++ b/include/configs/vexpress_aemv8a.h
@@ -0,0 +1,196 @@
+/*
+ * Configuration for Versatile Express. Parts were derived from other ARM
+ *   configurations.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __VEXPRESS_AEMV8A_H
+#define __VEXPRESS_AEMV8A_H
+
+#define DEBUG
+
+#define CONFIG_REMAKE_ELF
+
+#define CONFIG_GICV3
+
+/*#define CONFIG_ARMV8_SWITCH_TO_EL1*/
+
+/*#define CONFIG_SYS_GENERIC_BOARD*/
+
+#define CONFIG_SYS_NO_FLASH
+
+#define CONFIG_SUPPORT_RAW_INITRD
+
+/* Cache Definitions */
+#define CONFIG_SYS_DCACHE_OFF
+#define CONFIG_SYS_ICACHE_OFF
+
+#define CONFIG_IDENT_STRING		" vexpress_aemv8a"
+#define CONFIG_BOOTP_VCI_STRING		"U-boot.armv8.vexpress_aemv8a"
+
+/* Link Definitions */
+#define CONFIG_SYS_TEXT_BASE		0x80000000
+#define CONFIG_SYS_INIT_SP_ADDR         (CONFIG_SYS_SDRAM_BASE + 0x7fff0)
+
+/* Flat Device Tree Definitions */
+#define CONFIG_OF_LIBFDT
+
+#define CONFIG_DEFAULT_DEVICE_TREE	vexpress64
+
+/* SMP Spin Table Definitions */
+#define CPU_RELEASE_ADDR		(CONFIG_SYS_SDRAM_BASE + 0x7fff0)
+
+/* CS register bases for the original memory map. */
+#define V2M_PA_CS0			0x00000000
+#define V2M_PA_CS1			0x14000000
+#define V2M_PA_CS2			0x18000000
+#define V2M_PA_CS3			0x1c000000
+#define V2M_PA_CS4			0x0c000000
+#define V2M_PA_CS5			0x10000000
+
+#define V2M_PERIPH_OFFSET(x)		(x << 16)
+#define V2M_SYSREGS			(V2M_PA_CS3 + V2M_PERIPH_OFFSET(1))
+#define V2M_SYSCTL			(V2M_PA_CS3 + V2M_PERIPH_OFFSET(2))
+#define V2M_SERIAL_BUS_PCI		(V2M_PA_CS3 + V2M_PERIPH_OFFSET(3))
+
+#define V2M_BASE			0x80000000
+
+/*
+ * Physical addresses, offset from V2M_PA_CS0-3
+ */
+#define V2M_NOR0			(V2M_PA_CS0)
+#define V2M_NOR1			(V2M_PA_CS4)
+#define V2M_SRAM			(V2M_PA_CS1)
+
+/* Common peripherals relative to CS7. */
+#define V2M_AACI			(V2M_PA_CS3 + V2M_PERIPH_OFFSET(4))
+#define V2M_MMCI			(V2M_PA_CS3 + V2M_PERIPH_OFFSET(5))
+#define V2M_KMI0			(V2M_PA_CS3 + V2M_PERIPH_OFFSET(6))
+#define V2M_KMI1			(V2M_PA_CS3 + V2M_PERIPH_OFFSET(7))
+
+#define V2M_UART0			(V2M_PA_CS3 + V2M_PERIPH_OFFSET(9))
+#define V2M_UART1			(V2M_PA_CS3 + V2M_PERIPH_OFFSET(10))
+#define V2M_UART2			(V2M_PA_CS3 + V2M_PERIPH_OFFSET(11))
+#define V2M_UART3			(V2M_PA_CS3 + V2M_PERIPH_OFFSET(12))
+
+#define V2M_WDT				(V2M_PA_CS3 + V2M_PERIPH_OFFSET(15))
+
+#define V2M_TIMER01			(V2M_PA_CS3 + V2M_PERIPH_OFFSET(17))
+#define V2M_TIMER23			(V2M_PA_CS3 + V2M_PERIPH_OFFSET(18))
+
+#define V2M_SERIAL_BUS_DVI		(V2M_PA_CS3 + V2M_PERIPH_OFFSET(22))
+#define V2M_RTC				(V2M_PA_CS3 + V2M_PERIPH_OFFSET(23))
+
+#define V2M_CF				(V2M_PA_CS3 + V2M_PERIPH_OFFSET(26))
+
+#define V2M_CLCD			(V2M_PA_CS3 + V2M_PERIPH_OFFSET(31))
+
+/* System register offsets. */
+#define V2M_SYS_CFGDATA			(V2M_SYSREGS + 0x0a0)
+#define V2M_SYS_CFGCTRL			(V2M_SYSREGS + 0x0a4)
+#define V2M_SYS_CFGSTAT			(V2M_SYSREGS + 0x0a8)
+
+/* Generic Timer Definitions */
+#define COUNTER_FREQUENCY		(0x1800000)	/* 24MHz */
+
+/* Generic Interrupt Controller Definitions */
+#ifdef CONFIG_GICV3
+#define GICD_BASE			(0x2f000000)
+#define GICR_BASE			(0x2f100000)
+#else
+#define GICD_BASE			(0x2C001000)
+#define GICC_BASE			(0x2C002000)
+#endif
+
+#define CONFIG_SYS_MEMTEST_START	V2M_BASE
+#define CONFIG_SYS_MEMTEST_END		(V2M_BASE + 0x80000000)
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 128 * 1024)
+
+/* SMSC91C111 Ethernet Configuration */
+#define CONFIG_SMC91111			1
+#define CONFIG_SMC91111_BASE		(0x01A000000)
+
+/* PL011 Serial Configuration */
+#define CONFIG_PL011_SERIAL
+#define CONFIG_PL011_CLOCK		24000000
+#define CONFIG_PL01x_PORTS		{(void *)CONFIG_SYS_SERIAL0, \
+					 (void *)CONFIG_SYS_SERIAL1}
+#define CONFIG_CONS_INDEX		0
+
+#define CONFIG_BAUDRATE			115200
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+#define CONFIG_SYS_SERIAL0		V2M_UART0
+#define CONFIG_SYS_SERIAL1		V2M_UART1
+
+/* Command line configuration */
+#define CONFIG_MENU
+/*#define CONFIG_MENU_SHOW*/
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_BDI
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_PXE
+#define CONFIG_CMD_ENV
+#define CONFIG_CMD_FLASH
+#define CONFIG_CMD_IMI
+#define CONFIG_CMD_MEMORY
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_SAVEENV
+#define CONFIG_CMD_RUN
+#define CONFIG_CMD_BOOTD
+#define CONFIG_CMD_ECHO
+#define CONFIG_CMD_SOURCE
+#define CONFIG_CMD_FAT
+#define CONFIG_DOS_PARTITION
+
+/* BOOTP options */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_PXE
+#define CONFIG_BOOTP_PXE_CLIENTARCH	0x100
+
+/* Miscellaneous configurable options */
+#define CONFIG_SYS_LOAD_ADDR		(V2M_BASE + 0x10000000)
+
+/* Physical Memory Map */
+#define CONFIG_NR_DRAM_BANKS		1
+#define PHYS_SDRAM_1			(V2M_BASE)	/* SDRAM Bank #1 */
+#define PHYS_SDRAM_1_SIZE		0x80000000	/* 2048 MB */
+#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
+
+/* Initial environment variables */
+#define CONFIG_EXTRA_ENV_SETTINGS	\
+					"kernel_addr=0x200000\0"	\
+					"initrd_addr=0xa00000\0"	\
+					"initrd_size=0x2000000\0"	\
+					"fdt_addr=0x100000\0"		\
+					"fdt_high=0xa0000000\0"
+
+#define CONFIG_BOOTARGS			"console=ttyAMA0 root=/dev/ram0"
+#define CONFIG_BOOTCOMMAND		"bootm $kernel_addr " \
+					"$initrd_addr:$initrd_size $fdt_addr"
+#define CONFIG_BOOTDELAY		-1
+
+/* Do not preserve environment */
+#define CONFIG_ENV_IS_NOWHERE		1
+#define CONFIG_ENV_SIZE			0x1000
+
+/* Monitor Command Prompt */
+#define CONFIG_SYS_CBSIZE		512	/* Console I/O Buffer Size */
+#define CONFIG_SYS_PROMPT		"VExpress64# "
+#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
+					sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_CMDLINE_EDITING		1
+#define CONFIG_SYS_MAXARGS		64	/* max command args */
+
+#endif /* __VEXPRESS_AEMV8A_H */
diff --git a/include/configs/vexpress_common.h b/include/configs/vexpress_common.h
index 5598961aa7..7e78f8ac8f 100644
--- a/include/configs/vexpress_common.h
+++ b/include/configs/vexpress_common.h
@@ -117,7 +117,6 @@
 
 #define CONFIG_SYS_MEMTEST_START	V2M_BASE
 #define CONFIG_SYS_MEMTEST_END		0x20000000
-#define CONFIG_SYS_HZ			1000
 
 #define CONFIG_CMDLINE_TAG		1	/* enable passing of ATAGs */
 #define CONFIG_SETUP_MEMORY_TAGS	1
@@ -132,6 +131,10 @@
 #define SCTL_BASE			V2M_SYSCTL
 #define VEXPRESS_FLASHPROG_FLVPPEN	(1 << 0)
 
+#define CONFIG_SYS_TIMER_RATE		1000000
+#define CONFIG_SYS_TIMER_COUNTER	(V2M_TIMER01 + 0x4)
+#define CONFIG_SYS_TIMER_COUNTS_DOWN
+
 /* SMSC9115 Ethernet from SMSC9118 family */
 #define CONFIG_SMC911X			1
 #define CONFIG_SMC911X_32_BIT		1
diff --git a/include/configs/vf610twr.h b/include/configs/vf610twr.h
index 5a7a066377..500fd2fd61 100644
--- a/include/configs/vf610twr.h
+++ b/include/configs/vf610twr.h
@@ -70,10 +70,9 @@
 
 /* I2C Configs */
 #define CONFIG_CMD_I2C
-#define CONFIG_HARD_I2C
-#define CONFIG_I2C_MXC
-#define CONFIG_SYS_I2C_BASE		I2C0_BASE_ADDR
-#define CONFIG_SYS_I2C_SPEED		100000
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_SPD_BUS_NUM		0
 
 #define CONFIG_BOOTDELAY		3
 
@@ -82,7 +81,7 @@
 
 #define CONFIG_EXTRA_ENV_SETTINGS \
 	"script=boot.scr\0" \
-	"uimage=uImage\0" \
+	"image=zImage\0" \
 	"console=ttyLP1\0" \
 	"fdt_high=0xffffffff\0" \
 	"initrd_high=0xffffffff\0" \
@@ -113,22 +112,22 @@
 		"fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
 	"bootscript=echo Running bootscript from mmc ...; " \
 		"source\0" \
-	"loaduimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${uimage}\0" \
+	"loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
 	"loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
 	"mmcboot=echo Booting from mmc ...; " \
 		"run mmcargs; " \
 		"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
 			"if run loadfdt; then " \
-				"bootm ${loadaddr} - ${fdt_addr}; " \
+				"bootz ${loadaddr} - ${fdt_addr}; " \
 			"else " \
 				"if test ${boot_fdt} = try; then " \
-					"bootm; " \
+					"bootz; " \
 				"else " \
 					"echo WARN: Cannot load the DT; " \
 				"fi; " \
 			"fi; " \
 		"else " \
-			"bootm; " \
+			"bootz; " \
 		"fi;\0" \
 	"netargs=setenv bootargs console=${console},${baudrate} " \
 		"root=/dev/nfs " \
@@ -140,19 +139,19 @@
 		"else " \
 			"setenv get_cmd tftp; " \
 		"fi; " \
-		"${get_cmd} ${uimage}; " \
+		"${get_cmd} ${image}; " \
 		"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
 			"if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
-				"bootm ${loadaddr} - ${fdt_addr}; " \
+				"bootz ${loadaddr} - ${fdt_addr}; " \
 			"else " \
 				"if test ${boot_fdt} = try; then " \
-					"bootm; " \
+					"bootz; " \
 				"else " \
 					"echo WARN: Cannot load the DT; " \
 				"fi; " \
 			"fi; " \
 		"else " \
-			"bootm; " \
+			"bootz; " \
 		"fi;\0"
 
 #define CONFIG_BOOTCOMMAND \
@@ -160,7 +159,7 @@
 		   "if run loadbootscript; then " \
 			   "run bootscript; " \
 		   "else " \
-			   "if run loaduimage; then " \
+			   "if run loadimage; then " \
 				   "run mmcboot; " \
 			   "else run netboot; " \
 			   "fi; " \
@@ -171,7 +170,6 @@
 #define CONFIG_SYS_LONGHELP		/* undef to save memory */
 #define CONFIG_SYS_HUSH_PARSER		/* use "hush" command parser */
 #define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
-#define CONFIG_SYS_PROMPT		"=> "
 #undef CONFIG_AUTO_COMPLETE
 #define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size */
 #define CONFIG_SYS_PBSIZE		\
@@ -184,7 +182,6 @@
 #define CONFIG_SYS_MEMTEST_END		0x87C00000
 
 #define CONFIG_SYS_LOAD_ADDR		CONFIG_LOADADDR
-#define CONFIG_SYS_HZ			1000
 
 /*
  * Stack sizes
diff --git a/include/configs/virtlab2.h b/include/configs/virtlab2.h
index cf88d68ea1..0457cdfcf0 100644
--- a/include/configs/virtlab2.h
+++ b/include/configs/virtlab2.h
@@ -120,7 +120,6 @@
  * Miscellaneous configurable options
  */
 #define	CONFIG_SYS_LONGHELP			/* undef to save memory		*/
-#define	CONFIG_SYS_PROMPT		"=> "	/* Monitor Command Prompt	*/
 
 #define CONFIG_CMDLINE_EDITING	1	/* add command line history	*/
 #define	CONFIG_SYS_HUSH_PARSER		1	/* use "hush" command parser	*/
@@ -139,8 +138,6 @@
 
 #define	CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address	*/
 
-#define	CONFIG_SYS_HZ			1000	/* decrementer freq: 1 ms ticks	*/
-
 /*
  * Low Level Configuration Settings
  * (address mappings, register initial values, etc.)
diff --git a/include/configs/vision2.h b/include/configs/vision2.h
index 4744d7cb68..6891bf8b15 100644
--- a/include/configs/vision2.h
+++ b/include/configs/vision2.h
@@ -157,7 +157,6 @@
 
 #define CONFIG_SYS_LOAD_ADDR		CONFIG_LOADADDR
 
-#define CONFIG_SYS_HZ			1000
 #define CONFIG_CMDLINE_EDITING
 #define CONFIG_SYS_HUSH_PARSER
 
diff --git a/include/configs/vl_ma2sc.h b/include/configs/vl_ma2sc.h
index e171ae4c40..14c6e675c1 100644
--- a/include/configs/vl_ma2sc.h
+++ b/include/configs/vl_ma2sc.h
@@ -116,6 +116,7 @@
 
 /* USB */
 #define CONFIG_USB_ATMEL
+#define CONFIG_USB_ATMEL_CLK_SEL_PLLB
 #define CONFIG_USB_OHCI_NEW
 #define CONFIG_DOS_PARTITION
 #define CONFIG_SYS_USB_OHCI_CPU_INIT
@@ -198,7 +199,6 @@
 
 /* clocks */
 
-#define CONFIG_SYS_HZ			1000
 #define CONFIG_SYS_AT91_SLOW_CLOCK	32768		/* slow clock */
 
 #define MHZ180
@@ -320,9 +320,8 @@
 #define CONFIG_SYS_NAND_DBW_8		1
 #define CONFIG_SYS_NAND_MASK_ALE	(1 << 21)	/* our ALE is AD21 */
 #define CONFIG_SYS_NAND_MASK_CLE	(1 << 22)	/* our CLE is AD22 */
-#define CONFIG_SYS_NAND_ENABLE_PIN	AT91_PIO_PORTD, 15
-#define CONFIG_SYS_NAND_READY_PIN	AT91_PIO_PORTB, 0
-#define CONFIG_SYS_64BIT_VSPRINTF	/* needed for nand_util.c */
+#define CONFIG_SYS_NAND_ENABLE_PIN	GPIO_PIN_PD(15)
+#define CONFIG_SYS_NAND_READY_PIN	GPIO_PIN_PB(0)
 #endif
 
 /* Ethernet */
@@ -330,6 +329,7 @@
 #define CONFIG_RMII
 #define CONFIG_NET_MULTI
 #define CONFIG_NET_RETRY_COUNT		5
+#define CONFIG_AT91_WANTS_COMMON_PHY
 
 #define CONFIG_OVERWRITE_ETHADDR_ONCE
 
@@ -362,7 +362,6 @@
  */
 #define CONFIG_SYS_MALLOC_LEN		\
 	ROUND(3 * CONFIG_ENV_SIZE + 128 * 1024, 0x1000)
-#define CONFIG_SYS_GBL_DATA_SIZE	128	/* 128 bytes for initial data */
 
 #ifndef CONFIG_RAMLOAD
 #define CONFIG_BOOTCOMMAND		"run nfsboot"
diff --git a/include/configs/vme8349.h b/include/configs/vme8349.h
index d5666227e3..175311cad9 100644
--- a/include/configs/vme8349.h
+++ b/include/configs/vme8349.h
@@ -29,7 +29,6 @@
  * High Level Configuration Options
  */
 #define CONFIG_E300		1	/* E300 Family */
-#define CONFIG_MPC83xx		1	/* MPC83xx family */
 #define CONFIG_MPC834x		1	/* MPC834x family */
 #define CONFIG_MPC8349		1	/* MPC8349 specific */
 #define CONFIG_VME8349		1	/* ESD VME8349 board specific */
@@ -386,7 +385,6 @@
  */
 #define CONFIG_SYS_LONGHELP			/* undef to save memory */
 #define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
-#define CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt */
 
 #if defined(CONFIG_CMD_KGDB)
 	#define CONFIG_SYS_CBSIZE	1024	/* Console I/O Buffer Size */
@@ -397,7 +395,6 @@
 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
 #define CONFIG_SYS_MAXARGS	16		/* max num of command args */
 #define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE /* Boot Argument Buf Size */
-#define CONFIG_SYS_HZ		1000		/* decr freq: 1ms ticks */
 
 /*
  * For booting Linux, the board info and command line data
@@ -541,7 +538,6 @@
 
 #if defined(CONFIG_CMD_KGDB)
 #define CONFIG_KGDB_BAUDRATE	230400	/* speed of kgdb serial port */
-#define CONFIG_KGDB_SER_INDEX	2	/* which serial port to use */
 #endif
 
 /*
diff --git a/include/configs/vpac270.h b/include/configs/vpac270.h
index ba92db3de6..c6d47635b3 100644
--- a/include/configs/vpac270.h
+++ b/include/configs/vpac270.h
@@ -124,7 +124,6 @@
  */
 #ifdef	CONFIG_CMD_KGDB
 #define	CONFIG_KGDB_BAUDRATE		230400	/* kgdb serial port speed */
-#define	CONFIG_KGDB_SER_INDEX		2	/* which serial port to use */
 #endif
 
 /*
@@ -136,7 +135,6 @@
 #ifdef	CONFIG_SYS_HUSH_PARSER
 #define	CONFIG_SYS_PROMPT		"$ "
 #else
-#define	CONFIG_SYS_PROMPT		"=> "
 #endif
 #define	CONFIG_SYS_CBSIZE		256
 #define	CONFIG_SYS_PBSIZE		\
@@ -150,7 +148,6 @@
 /*
  * Clock Configuration
  */
-#define	CONFIG_SYS_HZ			1000		/* Timer @ 3250000 Hz */
 #define	CONFIG_SYS_CPUSPEED		0x190		/* 312MHz */
 
 
@@ -289,7 +286,7 @@
 /*
  * Memory settings
  */
-#define	CONFIG_SYS_MSC0_VAL	0x3ffc95fa
+#define	CONFIG_SYS_MSC0_VAL	0x3ffc95f9
 #define	CONFIG_SYS_MSC1_VAL	0x02ccf974
 #define	CONFIG_SYS_MSC2_VAL	0x00000000
 #ifdef	CONFIG_RAM_256M
diff --git a/include/configs/walnut.h b/include/configs/walnut.h
index a5691825ee..8b803a2ee0 100644
--- a/include/configs/walnut.h
+++ b/include/configs/walnut.h
@@ -18,7 +18,6 @@
  */
 
 #define CONFIG_405GP		1	/* This is a PPC405 CPU		*/
-#define CONFIG_4xx		1	/* ...member of PPC4xx family	*/
 #define CONFIG_WALNUT		1	/* ...on a WALNUT board		*/
 					/* ...or on a SYCAMORE board	*/
 
diff --git a/include/configs/wandboard.h b/include/configs/wandboard.h
index 442a9841ca..6c74c72952 100644
--- a/include/configs/wandboard.h
+++ b/include/configs/wandboard.h
@@ -9,9 +9,10 @@
 #ifndef __CONFIG_H
 #define __CONFIG_H
 
+#include "mx6_common.h"
 #include <asm/arch/imx-regs.h>
 #include <asm/imx-common/gpio.h>
-#include <asm/sizes.h>
+#include <linux/sizes.h>
 
 #define CONFIG_MX6
 #define CONFIG_DISPLAY_CPUINFO
@@ -107,13 +108,13 @@
 
 #define CONFIG_EXTRA_ENV_SETTINGS \
 	"script=boot.scr\0" \
-	"uimage=uImage\0" \
+	"image=zImage\0" \
 	"console=ttymxc0\0" \
 	"splashpos=m,m\0" \
 	"fdt_high=0xffffffff\0" \
 	"initrd_high=0xffffffff\0" \
 	"fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \
-	"fdt_addr=0x11000000\0" \
+	"fdt_addr=0x18000000\0" \
 	"boot_fdt=try\0" \
 	"ip_dyn=yes\0" \
 	"mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \
@@ -139,22 +140,22 @@
 		"fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
 	"bootscript=echo Running bootscript from mmc ...; " \
 		"source\0" \
-	"loaduimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${uimage}\0" \
+	"loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
 	"loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
 	"mmcboot=echo Booting from mmc ...; " \
 		"run mmcargs; " \
 		"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
 			"if run loadfdt; then " \
-				"bootm ${loadaddr} - ${fdt_addr}; " \
+				"bootz ${loadaddr} - ${fdt_addr}; " \
 			"else " \
 				"if test ${boot_fdt} = try; then " \
-					"bootm; " \
+					"bootz; " \
 				"else " \
 					"echo WARN: Cannot load the DT; " \
 				"fi; " \
 			"fi; " \
 		"else " \
-			"bootm; " \
+			"bootz; " \
 		"fi;\0" \
 	"netargs=setenv bootargs console=${console},${baudrate} " \
 		"root=/dev/nfs " \
@@ -166,19 +167,19 @@
 		"else " \
 			"setenv get_cmd tftp; " \
 		"fi; " \
-		"${get_cmd} ${uimage}; " \
+		"${get_cmd} ${image}; " \
 		"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
 			"if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
-				"bootm ${loadaddr} - ${fdt_addr}; " \
+				"bootz ${loadaddr} - ${fdt_addr}; " \
 			"else " \
 				"if test ${boot_fdt} = try; then " \
-					"bootm; " \
+					"bootz; " \
 				"else " \
 					"echo WARN: Cannot load the DT; " \
 				"fi; " \
 			"fi; " \
 		"else " \
-			"bootm; " \
+			"bootz; " \
 		"fi;\0"
 
 #define CONFIG_BOOTCOMMAND \
@@ -186,7 +187,7 @@
 		   "if run loadbootscript; then " \
 			   "run bootscript; " \
 		   "else " \
-			   "if run loaduimage; then " \
+			   "if run loadimage; then " \
 				   "run mmcboot; " \
 			   "else run netboot; " \
 			   "fi; " \
@@ -196,7 +197,6 @@
 /* Miscellaneous configurable options */
 #define CONFIG_SYS_LONGHELP
 #define CONFIG_SYS_HUSH_PARSER
-#define CONFIG_SYS_PROMPT	       "=> "
 #define CONFIG_AUTO_COMPLETE
 #define CONFIG_SYS_CBSIZE		256
 
@@ -206,7 +206,6 @@
 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
 
 #define CONFIG_SYS_LOAD_ADDR		CONFIG_LOADADDR
-#define CONFIG_SYS_HZ			1000
 
 #define CONFIG_CMDLINE_EDITING
 
diff --git a/include/configs/whistler.h b/include/configs/whistler.h
index d5c7e3bbd6..9e09f03d52 100644
--- a/include/configs/whistler.h
+++ b/include/configs/whistler.h
@@ -8,7 +8,7 @@
 #ifndef __CONFIG_H
 #define __CONFIG_H
 
-#include <asm/sizes.h>
+#include <linux/sizes.h>
 #include "tegra20-common.h"
 
 /* Enable fdt support for Whistler. Flash the image in u-boot-dtb.bin */
diff --git a/include/configs/woodburn_common.h b/include/configs/woodburn_common.h
index 5c442ad865..695bc230c0 100644
--- a/include/configs/woodburn_common.h
+++ b/include/configs/woodburn_common.h
@@ -45,10 +45,9 @@
 /*
  * Hardware drivers
  */
-#define CONFIG_HARD_I2C
-#define CONFIG_I2C_MXC
-#define CONFIG_SYS_I2C_BASE		I2C1_BASE_ADDR
-#define CONFIG_SYS_I2C_SPEED		100000
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_SPD_BUS_NUM		0
 #define CONFIG_MXC_SPI
 #define CONFIG_MXC_GPIO
 
@@ -152,9 +151,6 @@
 
 #define CONFIG_SYS_LOAD_ADDR		CONFIG_LOADADDR
 
-#define CONFIG_SYS_HZ				1000
-
-
 /*
  * Stack sizes
  *
diff --git a/include/configs/woodburn_sd.h b/include/configs/woodburn_sd.h
index 10e1d170ba..437472f3ed 100644
--- a/include/configs/woodburn_sd.h
+++ b/include/configs/woodburn_sd.h
@@ -17,8 +17,6 @@
 /* Set TEXT in RAM */
 #define CONFIG_SYS_TEXT_BASE	0x82000000
 
-#define CONFIG_BOOT_INTERNAL
-
 /*
  * SPL
  */
diff --git a/include/configs/x600.h b/include/configs/x600.h
index 89cd501644..7405419f0e 100644
--- a/include/configs/x600.h
+++ b/include/configs/x600.h
@@ -20,7 +20,6 @@
 #include <asm/arch/hardware.h>
 
 /* Timer, HZ specific defines */
-#define CONFIG_SYS_HZ				1000
 #define CONFIG_SYS_HZ_CLOCK			8300000
 
 #define	CONFIG_SYS_TEXT_BASE			0x00800040
@@ -75,10 +74,9 @@
 /* Ethernet config options */
 #define CONFIG_MII
 #define CONFIG_DESIGNWARE_ETH
-#define CONFIG_DW_SEARCH_PHY
 #define CONFIG_NET_MULTI
+#define CONFIG_PHYLIB
 #define CONFIG_PHY_RESET_DELAY			10000		/* in usec */
-#define CONFIG_DW_AUTONEG
 #define CONFIG_PHY_ADDR		0	/* PHY address */
 #define CONFIG_PHY_GIGE			/* Include GbE speed/duplex detection */
 
@@ -87,6 +85,7 @@
 /* I2C config options */
 #define CONFIG_HARD_I2C
 #define CONFIG_DW_I2C
+#define CONFIG_SYS_I2C_BASE			0xD0200000
 #define CONFIG_SYS_I2C_SPEED			400000
 #define CONFIG_SYS_I2C_SLAVE			0x02
 #define CONFIG_I2C_CHIPADDRESS			0x50
@@ -172,7 +171,6 @@
 #define CONFIG_SYS_BARGSIZE			CONFIG_SYS_CBSIZE
 #define CONFIG_SYS_LOAD_ADDR			0x00800000
 #define CONFIG_SYS_CONSOLE_INFO_QUIET
-#define CONFIG_SYS_64BIT_VSPRINTF
 
 /* Use last 2 lwords in internal SRAM for bootcounter */
 #define CONFIG_BOOTCOUNT_LIMIT
diff --git a/include/configs/xaeniax.h b/include/configs/xaeniax.h
index 5f34fc7694..2999d1b0f5 100644
--- a/include/configs/xaeniax.h
+++ b/include/configs/xaeniax.h
@@ -84,7 +84,6 @@
 
 #if defined(CONFIG_CMD_KGDB)
 #define CONFIG_KGDB_BAUDRATE	115200			/* speed to run kgdb serial port */
-#define CONFIG_KGDB_SER_INDEX	1			/* which serial port to use */
 #endif
 
 /*
@@ -116,7 +115,6 @@
 
 #define CONFIG_SYS_LOAD_ADDR		0xa1000000	/* default load address */
 
-#define CONFIG_SYS_HZ			1000
 #define CONFIG_SYS_CPUSPEED		0x141		/* set core clock to 400/200/100 MHz */
 
 /*
diff --git a/include/configs/xfi3.h b/include/configs/xfi3.h
index 022bc95927..8e6b365364 100644
--- a/include/configs/xfi3.h
+++ b/include/configs/xfi3.h
@@ -55,7 +55,7 @@
 #define CONFIG_EHCI_MXS_PORT0
 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
 
-#define CONFIG_MV_UDC		/* ChipIdea CI13xxx UDC */
+#define CONFIG_CI_UDC		/* ChipIdea CI13xxx UDC */
 #define CONFIG_USB_GADGET_DUALSPEED
 
 #define CONFIG_USB_ETHER
diff --git a/include/configs/xilinx-ppc.h b/include/configs/xilinx-ppc.h
index f4f42c510d..0ccd73a868 100644
--- a/include/configs/xilinx-ppc.h
+++ b/include/configs/xilinx-ppc.h
@@ -64,7 +64,6 @@
 					/* default load address       */
 #define CONFIG_SYS_EXTBDINFO		1
 					/* Extended board_into (bd_t) */
-#define CONFIG_SYS_HZ			1000
 					/* decrementer freq: 1 ms ticks */
 #define CONFIG_CMDLINE_EDITING		/* add command line history     */
 #define CONFIG_AUTO_COMPLETE		/* add autocompletion support   */
diff --git a/include/configs/xilinx-ppc405.h b/include/configs/xilinx-ppc405.h
index 431e331f5c..a0151fe8f4 100644
--- a/include/configs/xilinx-ppc405.h
+++ b/include/configs/xilinx-ppc405.h
@@ -15,7 +15,6 @@
 
 /* cpu parameter */
 #define CONFIG_405		1
-#define CONFIG_4xx		1
 #define CONFIG_XILINX_405	1
 
 #include <configs/xilinx-ppc.h>
diff --git a/include/configs/xilinx-ppc440.h b/include/configs/xilinx-ppc440.h
index 2ec3dd18dd..f45700878e 100644
--- a/include/configs/xilinx-ppc440.h
+++ b/include/configs/xilinx-ppc440.h
@@ -9,7 +9,6 @@
 #define __CONFIG_GEN_H
 
 /*CPU*/
-#define CONFIG_4xx		1
 #define CONFIG_440		1
 #define CONFIG_XILINX_440	1
 
diff --git a/include/configs/xpedite1000.h b/include/configs/xpedite1000.h
index a1dea657af..ca322b2e82 100644
--- a/include/configs/xpedite1000.h
+++ b/include/configs/xpedite1000.h
@@ -18,7 +18,6 @@
 #define CONFIG_XPEDITE1000	1
 #define CONFIG_SYS_BOARD_NAME	"XPedite1000"
 #define CONFIG_SYS_FORM_PMC	1
-#define CONFIG_4xx		1		/* ... PPC4xx family */
 #define CONFIG_440		1
 #define CONFIG_440GX		1		/* 440 GX */
 #define CONFIG_BOARD_EARLY_INIT_F 1		/* Call board_pre_init	*/
@@ -209,12 +208,10 @@ extern void out32(unsigned int, unsigned long);
  */
 #define CONFIG_SYS_LONGHELP			/* undef to save memory */
 #define CONFIG_SYS_LOAD_ADDR	0x100000	/* default load address */
-#define CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt */
 #define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size */
 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
 #define CONFIG_SYS_MAXARGS	16		/* max number of command args */
 #define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size */
-#define CONFIG_SYS_HZ		1000		/* decrementer freq: 1 ms ticks */
 #define CONFIG_CMDLINE_EDITING	1		/* Command-line editing */
 #define CONFIG_BOOTDELAY	3		/* -1 disables auto-boot */
 #define CONFIG_PANIC_HANG			/* do not reset board on panic */
diff --git a/include/configs/xpedite517x.h b/include/configs/xpedite517x.h
index 97ce3eb542..cbf4b8e0f7 100644
--- a/include/configs/xpedite517x.h
+++ b/include/configs/xpedite517x.h
@@ -14,7 +14,6 @@
 /*
  * High Level Configuration Options
  */
-#define CONFIG_MPC86xx		1	/* MPC86xx */
 #define CONFIG_MPC8641		1	/* MPC8641 specific */
 #define CONFIG_XPEDITE5140	1	/* MPC8641HPCN board specific */
 #define CONFIG_SYS_BOARD_NAME	"XPedite5170"
@@ -40,7 +39,7 @@
 /*
  * DDR config
  */
-#define CONFIG_FSL_DDR2
+#define CONFIG_SYS_FSL_DDR2
 #define CONFIG_SPD_EEPROM		/* Use SPD EEPROM for DDR setup */
 #define CONFIG_DDR_SPD
 #define CONFIG_MEM_INIT_VALUE		0xdeadbeef
@@ -556,12 +555,10 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
  */
 #define CONFIG_SYS_LONGHELP			/* undef to save memory	*/
 #define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
-#define CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt */
 #define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size */
 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
 #define CONFIG_SYS_MAXARGS	16		/* max number of command args */
 #define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size */
-#define CONFIG_SYS_HZ		1000		/* decrementer freq: 1ms ticks */
 #define CONFIG_CMDLINE_EDITING	1		/* Command-line editing */
 #define CONFIG_LOADADDR		0x1000000	/* default location for tftp and bootm */
 #define CONFIG_BOOTDELAY	3		/* -1 disables auto-boot */
diff --git a/include/configs/xpedite520x.h b/include/configs/xpedite520x.h
index 372135a89f..baa30395aa 100644
--- a/include/configs/xpedite520x.h
+++ b/include/configs/xpedite520x.h
@@ -16,7 +16,6 @@
  */
 #define CONFIG_BOOKE		1	/* BOOKE */
 #define CONFIG_E500		1	/* BOOKE e500 family */
-#define CONFIG_MPC85xx		1	/* MPC8540/60/55/41/48 */
 #define CONFIG_MPC8548		1
 #define CONFIG_XPEDITE5200	1
 #define CONFIG_SYS_BOARD_NAME	"XPedite5200"
@@ -39,7 +38,7 @@
 /*
  * DDR config
  */
-#define CONFIG_FSL_DDR2
+#define CONFIG_SYS_FSL_DDR2
 #undef CONFIG_FSL_DDR_INTERACTIVE
 #define CONFIG_SPD_EEPROM		/* Use SPD EEPROM for DDR setup */
 #define CONFIG_DDR_SPD
@@ -337,12 +336,10 @@
  */
 #define CONFIG_SYS_LONGHELP			/* undef to save memory	*/
 #define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
-#define CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt */
 #define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size */
 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
 #define CONFIG_SYS_MAXARGS	16		/* max number of command args */
 #define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size */
-#define CONFIG_SYS_HZ		1000		/* decrementer freq: 1ms ticks */
 #define CONFIG_CMDLINE_EDITING	1		/* add command line history	*/
 #define CONFIG_AUTO_COMPLETE	1		/* add autocompletion support */
 #define CONFIG_LOADADDR		0x1000000	/* default location for tftp and bootm */
diff --git a/include/configs/xpedite537x.h b/include/configs/xpedite537x.h
index 31330eaa30..bdf55763d5 100644
--- a/include/configs/xpedite537x.h
+++ b/include/configs/xpedite537x.h
@@ -16,7 +16,6 @@
  */
 #define CONFIG_BOOKE		1	/* BOOKE */
 #define CONFIG_E500		1	/* BOOKE e500 family */
-#define CONFIG_MPC85xx		1	/* MPC8540/60/55/41/48 */
 #define CONFIG_MPC8572		1
 #define CONFIG_XPEDITE5370	1
 #define CONFIG_SYS_BOARD_NAME	"XPedite5370"
@@ -49,7 +48,7 @@
 /*
  * DDR config
  */
-#define CONFIG_FSL_DDR2
+#define CONFIG_SYS_FSL_DDR2
 #undef CONFIG_FSL_DDR_INTERACTIVE
 #define CONFIG_SPD_EEPROM		/* Use SPD EEPROM for DDR setup */
 #define CONFIG_DDR_SPD
@@ -411,12 +410,10 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
  */
 #define CONFIG_SYS_LONGHELP			/* undef to save memory	*/
 #define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
-#define CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt */
 #define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size */
 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
 #define CONFIG_SYS_MAXARGS	16		/* max number of command args */
 #define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size */
-#define CONFIG_SYS_HZ		1000		/* decrementer freq: 1ms ticks */
 #define CONFIG_CMDLINE_EDITING	1		/* add command line history	*/
 #define CONFIG_AUTO_COMPLETE	1		/* add autocompletion support */
 #define CONFIG_LOADADDR		0x1000000	/* default location for tftp and bootm */
diff --git a/include/configs/xpedite550x.h b/include/configs/xpedite550x.h
index 340d4be4c6..0b24f3e8d7 100644
--- a/include/configs/xpedite550x.h
+++ b/include/configs/xpedite550x.h
@@ -16,7 +16,6 @@
  */
 #define CONFIG_BOOKE		1	/* BOOKE */
 #define CONFIG_E500		1	/* BOOKE e500 family */
-#define CONFIG_MPC85xx		1	/* MPC8540/60/55/41/48 */
 #define CONFIG_P2020		1
 #define CONFIG_XPEDITE550X	1
 #define CONFIG_SYS_BOARD_NAME	"XPedite5500"
@@ -49,7 +48,7 @@
 /*
  * DDR config
  */
-#define CONFIG_FSL_DDR3
+#define CONFIG_SYS_FSL_DDR3
 #define CONFIG_SPD_EEPROM		/* Use SPD EEPROM for DDR setup */
 #define CONFIG_DDR_SPD
 #define CONFIG_MEM_INIT_VALUE		0xdeadbeef
@@ -396,12 +395,10 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
  */
 #define CONFIG_SYS_LONGHELP			/* undef to save memory	*/
 #define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
-#define CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt */
 #define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size */
 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
 #define CONFIG_SYS_MAXARGS	16		/* max number of command args */
 #define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size */
-#define CONFIG_SYS_HZ		1000		/* decrementer freq: 1ms ticks */
 #define CONFIG_CMDLINE_EDITING	1		/* add command line history	*/
 #define CONFIG_AUTO_COMPLETE	1		/* add autocompletion support */
 #define CONFIG_LOADADDR		0x1000000	/* default location for tftp and bootm */
diff --git a/include/configs/yosemite.h b/include/configs/yosemite.h
index 2dd742e327..8508a8029e 100644
--- a/include/configs/yosemite.h
+++ b/include/configs/yosemite.h
@@ -23,7 +23,6 @@
 #define CONFIG_HOSTNAME		yellowstone
 #endif
 #define CONFIG_440		1	/* ... PPC440 family		*/
-#define CONFIG_4xx		1	/* ... PPC4xx family		*/
 #define CONFIG_SYS_CLK_FREQ	66666666    /* external freq to pll	*/
 
 #define	CONFIG_SYS_TEXT_BASE	0xFFF80000
diff --git a/include/configs/yucca.h b/include/configs/yucca.h
index 5d584fbad4..76717e4579 100644
--- a/include/configs/yucca.h
+++ b/include/configs/yucca.h
@@ -18,7 +18,6 @@
 /*-----------------------------------------------------------------------
  * High Level Configuration Options
  *----------------------------------------------------------------------*/
-#define CONFIG_4xx			1	/* ... PPC4xx family	*/
 #define CONFIG_440			1	/* ... PPC440 family	*/
 #define CONFIG_440SPE			1	/* Specifc SPe support	*/
 #define CONFIG_440SPE_REVA		1	/* Support old Rev A.	*/
diff --git a/include/configs/zeus.h b/include/configs/zeus.h
index 237fcb1512..4d7a7fc755 100644
--- a/include/configs/zeus.h
+++ b/include/configs/zeus.h
@@ -15,7 +15,6 @@
  * High Level Configuration Options
  *----------------------------------------------------------------------*/
 #define CONFIG_ZEUS		1		/* Board is Zeus	*/
-#define CONFIG_4xx		1		/* ... PPC4xx family	*/
 #define CONFIG_405EP		1		/* Specifc 405EP support*/
 
 #define	CONFIG_SYS_TEXT_BASE	0xFFFC0000
@@ -122,7 +121,6 @@
  * Miscellaneous configurable options
  *----------------------------------------------------------------------*/
 #define CONFIG_SYS_LONGHELP			/* undef to save memory		*/
-#define CONFIG_SYS_PROMPT	        "=> "	/* Monitor Command Prompt	*/
 #if defined(CONFIG_CMD_KGDB)
 #define CONFIG_SYS_CBSIZE	        1024	/* Console I/O Buffer Size	*/
 #else
@@ -138,8 +136,6 @@
 #define CONFIG_SYS_LOAD_ADDR		0x100000  /* default load address	*/
 #define CONFIG_SYS_EXTBDINFO		1	/* To use extended board_into (bd_t) */
 
-#define CONFIG_SYS_HZ		        1000	/* decrementer freq: 1 ms ticks	*/
-
 #define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
 #define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
 
@@ -286,7 +282,6 @@
 
 #if defined(CONFIG_CMD_KGDB)
 #define CONFIG_KGDB_BAUDRATE	230400		/* speed to run kgdb serial port */
-#define CONFIG_KGDB_SER_INDEX	2		/* which serial port to use */
 #endif
 
 /*
diff --git a/include/configs/zipitz2.h b/include/configs/zipitz2.h
index 69aafa74cd..41a7c99edc 100644
--- a/include/configs/zipitz2.h
+++ b/include/configs/zipitz2.h
@@ -117,7 +117,6 @@ unsigned char zipitz2_spi_read(void);
  */
 #ifdef	CONFIG_CMD_KGDB
 #define	CONFIG_KGDB_BAUDRATE		230400		/* speed to run kgdb serial port */
-#define	CONFIG_KGDB_SER_INDEX		2		/* which serial port to use */
 #endif
 
 /*
@@ -128,8 +127,6 @@ unsigned char zipitz2_spi_read(void);
 #define	CONFIG_SYS_LONGHELP				/* undef to save memory	*/
 #ifdef	CONFIG_SYS_HUSH_PARSER
 #define	CONFIG_SYS_PROMPT		"$ "		/* Monitor Command Prompt */
-#else
-#define	CONFIG_SYS_PROMPT		"=> "		/* Monitor Command Prompt */
 #endif
 #define	CONFIG_SYS_CBSIZE		256		/* Console I/O Buffer Size */
 #define	CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)	/* Print Buffer Size */
@@ -141,7 +138,6 @@ unsigned char zipitz2_spi_read(void);
  * Clock Configuration
  */
 #undef	CONFIG_SYS_CLKS_IN_HZ
-#define	CONFIG_SYS_HZ			3250000		/* Timer @ 3250000 Hz */
 #define CONFIG_SYS_CPUSPEED		0x190		/* standard setting for 312MHz; L=16, N=1.5, A=0, SDCLK!=SystemBus */
 
 /*
@@ -188,10 +184,10 @@ unsigned char zipitz2_spi_read(void);
 
 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE	1
 
-#define CONFIG_SYS_FLASH_ERASE_TOUT	(2*CONFIG_SYS_HZ)
-#define CONFIG_SYS_FLASH_WRITE_TOUT	(2*CONFIG_SYS_HZ)
-#define CONFIG_SYS_FLASH_LOCK_TOUT	(2*CONFIG_SYS_HZ)
-#define CONFIG_SYS_FLASH_UNLOCK_TOUT	(2*CONFIG_SYS_HZ)
+#define CONFIG_SYS_FLASH_ERASE_TOUT	240000
+#define CONFIG_SYS_FLASH_WRITE_TOUT	240000
+#define CONFIG_SYS_FLASH_LOCK_TOUT	240000
+#define CONFIG_SYS_FLASH_UNLOCK_TOUT	240000
 #define CONFIG_SYS_FLASH_PROTECTION
 
 /*
diff --git a/include/configs/zmx25.h b/include/configs/zmx25.h
index 765b849e25..8ffe6f1e08 100644
--- a/include/configs/zmx25.h
+++ b/include/configs/zmx25.h
@@ -10,11 +10,16 @@
 #ifndef __CONFIG_H
 #define __CONFIG_H
 
+#include <asm/arch/imx-regs.h>
+
 #define CONFIG_ARM926EJS			/* arm926ejs CPU core */
 #define CONFIG_MX25
-#define CONFIG_SYS_HZ			1000
 #define CONFIG_SYS_TEXT_BASE		0xA0000000
 
+#define CONFIG_SYS_TIMER_RATE		32768
+#define CONFIG_SYS_TIMER_COUNTER	\
+	(&((struct gpt_regs *)IMX_GPT1_BASE)->counter)
+
 #define CONFIG_MACH_TYPE	MACH_TYPE_ZMX25
 /*
  * Environment settings
diff --git a/include/configs/zynq-common.h b/include/configs/zynq-common.h
new file mode 100644
index 0000000000..731e69b5fd
--- /dev/null
+++ b/include/configs/zynq-common.h
@@ -0,0 +1,309 @@
+/*
+ * (C) Copyright 2012 Michal Simek <monstr@monstr.eu>
+ * (C) Copyright 2013 Xilinx, Inc.
+ *
+ * Common configuration options for all Zynq boards.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_ZYNQ_COMMON_H
+#define __CONFIG_ZYNQ_COMMON_H
+
+/* High Level configuration Options */
+#define CONFIG_ARMV7
+#define CONFIG_ZYNQ
+
+/* CPU clock */
+#ifndef CONFIG_CPU_FREQ_HZ
+# define CONFIG_CPU_FREQ_HZ	800000000
+#endif
+
+/* Cache options */
+#define CONFIG_CMD_CACHE
+#define CONFIG_SYS_CACHELINE_SIZE	32
+
+#define CONFIG_SYS_L2CACHE_OFF
+#ifndef CONFIG_SYS_L2CACHE_OFF
+# define CONFIG_SYS_L2_PL310
+# define CONFIG_SYS_PL310_BASE		0xf8f02000
+#endif
+
+/* Serial drivers */
+#define CONFIG_BAUDRATE		115200
+/* The following table includes the supported baudrates */
+#define CONFIG_SYS_BAUDRATE_TABLE  \
+	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400}
+
+/* DCC driver */
+#if defined(CONFIG_ZYNQ_DCC)
+# define CONFIG_ARM_DCC
+# define CONFIG_CPU_V6 /* Required by CONFIG_ARM_DCC */
+#else
+# define CONFIG_ZYNQ_SERIAL
+#endif
+
+/* Ethernet driver */
+#if defined(CONFIG_ZYNQ_GEM0) || defined(CONFIG_ZYNQ_GEM1)
+# define CONFIG_NET_MULTI
+# define CONFIG_ZYNQ_GEM
+# define CONFIG_MII
+# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
+# define CONFIG_PHYLIB
+# define CONFIG_PHY_MARVELL
+#endif
+
+/* SPI */
+#ifdef CONFIG_ZYNQ_SPI
+# define CONFIG_SPI_FLASH
+# define CONFIG_SPI_FLASH_SST
+# define CONFIG_CMD_SF
+#endif
+
+/* NOR */
+#ifndef CONFIG_SYS_NO_FLASH
+# define CONFIG_SYS_FLASH_BASE		0xE2000000
+# define CONFIG_SYS_FLASH_SIZE		(16 * 1024 * 1024)
+# define CONFIG_SYS_MAX_FLASH_BANKS	1
+# define CONFIG_SYS_MAX_FLASH_SECT	512
+# define CONFIG_SYS_FLASH_ERASE_TOUT	1000
+# define CONFIG_SYS_FLASH_WRITE_TOUT	5000
+# define CONFIG_FLASH_SHOW_PROGRESS	10
+# define CONFIG_SYS_FLASH_CFI
+# undef CONFIG_SYS_FLASH_EMPTY_INFO
+# define CONFIG_FLASH_CFI_DRIVER
+# undef CONFIG_SYS_FLASH_PROTECTION
+# define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
+#endif
+
+/* MMC */
+#if defined(CONFIG_ZYNQ_SDHCI0) || defined(CONFIG_ZYNQ_SDHCI1)
+# define CONFIG_MMC
+# define CONFIG_GENERIC_MMC
+# define CONFIG_SDHCI
+# define CONFIG_ZYNQ_SDHCI
+# define CONFIG_CMD_MMC
+# define CONFIG_CMD_FAT
+# define CONFIG_SUPPORT_VFAT
+# define CONFIG_CMD_EXT2
+# define CONFIG_DOS_PARTITION
+#endif
+
+#define CONFIG_SYS_I2C_ZYNQ
+/* I2C */
+#if defined(CONFIG_SYS_I2C_ZYNQ)
+# define CONFIG_CMD_I2C
+# define CONFIG_SYS_I2C
+# define CONFIG_SYS_I2C_ZYNQ_SPEED		100000
+# define CONFIG_SYS_I2C_ZYNQ_SLAVE		0
+#endif
+
+/* EEPROM */
+#ifdef CONFIG_ZYNQ_EEPROM
+# define CONFIG_CMD_EEPROM
+# define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		1
+# define CONFIG_SYS_I2C_EEPROM_ADDR		0x54
+# define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	4
+# define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	5
+# define CONFIG_SYS_EEPROM_SIZE			1024 /* Bytes */
+#endif
+
+#define CONFIG_BOOTP_SERVERIP
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_MAY_FAIL
+
+/* Total Size of Environment Sector */
+#define CONFIG_ENV_SIZE			(128 << 10)
+
+/* Allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+
+/* Environment */
+#ifndef CONFIG_ENV_IS_NOWHERE
+# ifndef CONFIG_SYS_NO_FLASH
+#  define CONFIG_ENV_IS_IN_FLASH
+# elif defined(CONFIG_SYS_NO_FLASH)
+#  define CONFIG_ENV_IS_NOWHERE
+# endif
+
+# define CONFIG_ENV_SECT_SIZE		CONFIG_ENV_SIZE
+# define CONFIG_ENV_OFFSET		0xE0000
+# define CONFIG_CMD_SAVEENV
+#endif
+
+/* Default environment */
+#define CONFIG_EXTRA_ENV_SETTINGS	\
+	"fit_image=fit.itb\0"		\
+	"load_addr=0x2000000\0"		\
+	"fit_size=0x800000\0"		\
+	"flash_off=0x100000\0"		\
+	"nor_flash_off=0xE2100000\0"	\
+	"fdt_high=0x20000000\0"		\
+	"initrd_high=0x20000000\0"	\
+	"norboot=echo Copying FIT from NOR flash to RAM... && " \
+		"cp.b ${nor_flash_off} ${load_addr} ${fit_size} && " \
+		"bootm ${load_addr}\0" \
+	"sdboot=echo Copying FIT from SD to RAM... && " \
+		"fatload mmc 0 ${load_addr} ${fit_image} && " \
+		"bootm ${load_addr}\0" \
+	"jtagboot=echo TFTPing FIT to RAM... && " \
+		"tftpboot ${load_addr} ${fit_image} && " \
+		"bootm ${load_addr}\0"
+#define CONFIG_BOOTCOMMAND		"run $modeboot"
+#define CONFIG_BOOTDELAY		3 /* -1 to Disable autoboot */
+#define CONFIG_SYS_LOAD_ADDR		0 /* default? */
+
+/* Miscellaneous configurable options */
+#define CONFIG_SYS_PROMPT		"zynq-uboot> "
+#define CONFIG_SYS_HUSH_PARSER
+
+#define CONFIG_CMDLINE_EDITING
+#define CONFIG_AUTO_COMPLETE
+#define CONFIG_BOARD_LATE_INIT
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_CLOCKS
+#define CONFIG_CMD_CLK
+#define CONFIG_SYS_MAXARGS		15 /* max number of command args */
+#define CONFIG_SYS_CBSIZE		256 /* Console I/O Buffer Size */
+#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
+					sizeof(CONFIG_SYS_PROMPT) + 16)
+
+/* Physical Memory map */
+#define CONFIG_SYS_TEXT_BASE		0x4000000
+
+#define CONFIG_NR_DRAM_BANKS		1
+#define CONFIG_SYS_SDRAM_BASE		0
+
+#define CONFIG_SYS_MEMTEST_START	CONFIG_SYS_SDRAM_BASE
+#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_SDRAM_BASE + 0x1000)
+
+#define CONFIG_SYS_MALLOC_LEN		0x400000
+#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_SDRAM_BASE
+#define CONFIG_SYS_INIT_RAM_SIZE	CONFIG_SYS_MALLOC_LEN
+#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_INIT_RAM_ADDR + \
+					CONFIG_SYS_INIT_RAM_SIZE - \
+					GENERATED_GBL_DATA_SIZE)
+
+/* Enable the PL to be downloaded */
+#define CONFIG_FPGA
+#define CONFIG_FPGA_XILINX
+#define CONFIG_FPGA_ZYNQPL
+#define CONFIG_CMD_FPGA
+
+/* Open Firmware flat tree */
+#define CONFIG_OF_LIBFDT
+
+/* FIT support */
+#define CONFIG_FIT
+#define CONFIG_FIT_VERBOSE	1 /* enable fit_format_{error,warning}() */
+
+/* FDT support */
+#define CONFIG_OF_CONTROL
+#define CONFIG_OF_SEPARATE
+#define CONFIG_DISPLAY_BOARDINFO_LATE
+
+/* RSA support */
+#define CONFIG_FIT_SIGNATURE
+#define CONFIG_RSA
+
+/* Extend size of kernel image for uncompression */
+#define CONFIG_SYS_BOOTM_LEN	(20 * 1024 * 1024)
+
+/* Boot FreeBSD/vxWorks from an ELF image */
+#if defined(CONFIG_ZYNQ_BOOT_FREEBSD)
+# define CONFIG_API
+# define CONFIG_CMD_ELF
+# define CONFIG_SYS_MMC_MAX_DEVICE	1
+#endif
+
+#define CONFIG_SYS_LDSCRIPT  "arch/arm/cpu/armv7/zynq/u-boot.lds"
+
+/* Commands */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_TFTPPUT
+
+/* SPL part */
+#define CONFIG_SPL
+#define CONFIG_CMD_SPL
+#define CONFIG_SPL_FRAMEWORK
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+#define CONFIG_SPL_LIBGENERIC_SUPPORT
+#define CONFIG_SPL_SERIAL_SUPPORT
+
+#define CONFIG_SPL_LDSCRIPT	"arch/arm/cpu/armv7/zynq/u-boot-spl.lds"
+
+/* Disable dcache for SPL just for sure */
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SYS_DCACHE_OFF
+#undef CONFIG_FPGA
+#undef CONFIG_OF_CONTROL
+#endif
+
+/* MMC support */
+#ifdef CONFIG_ZYNQ_SDHCI0
+#define CONFIG_SPL_MMC_SUPPORT
+#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */
+#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS      0x200 /* 256 KB */
+#define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION    1
+#define CONFIG_SPL_LIBDISK_SUPPORT
+#define CONFIG_SPL_FAT_SUPPORT
+#define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME     "u-boot.img"
+#endif
+
+/* Address in RAM where the parameters must be copied by SPL. */
+#define CONFIG_SYS_SPL_ARGS_ADDR	0x10000000
+
+#define CONFIG_SPL_FAT_LOAD_ARGS_NAME		"system.dtb"
+#define CONFIG_SPL_FAT_LOAD_KERNEL_NAME		"uImage"
+
+/* Not using MMC raw mode - just for compilation purpose */
+#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR	0
+#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS	0
+#define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR	0
+
+/* qspi mode is working fine */
+#ifdef CONFIG_ZYNQ_QSPI
+#define CONFIG_SPL_SPI_SUPPORT
+#define CONFIG_SPL_SPI_LOAD
+#define CONFIG_SPL_SPI_FLASH_SUPPORT
+#define CONFIG_SPL_SPI_BUS	0
+#define CONFIG_SYS_SPI_U_BOOT_OFFS	0x100000
+#define CONFIG_SPL_SPI_CS	0
+#endif
+
+/* for booting directly linux */
+#define CONFIG_SPL_OS_BOOT
+
+/* SP location before relocation, must use scratch RAM */
+#define CONFIG_SPL_TEXT_BASE	0x0
+
+/* 3 * 64kB blocks of OCM - one is on the top because of bootrom */
+#define CONFIG_SPL_MAX_SIZE	0x30000
+
+/* The highest 64k OCM address */
+#define OCM_HIGH_ADDR	0xffff0000
+
+/* Just define any reasonable size */
+#define CONFIG_SPL_STACK_SIZE	0x1000
+
+/* SPL stack position - and stack goes down */
+#define CONFIG_SPL_STACK	(OCM_HIGH_ADDR + CONFIG_SPL_STACK_SIZE)
+
+/* On the top of OCM space */
+#define CONFIG_SYS_SPL_MALLOC_START	(CONFIG_SPL_STACK + \
+					 GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_SPL_MALLOC_SIZE	0x1000
+
+/* BSS setup */
+#define CONFIG_SPL_BSS_START_ADDR	0x100000
+#define CONFIG_SPL_BSS_MAX_SIZE		0x100000
+
+#define CONFIG_SYS_UBOOT_START	CONFIG_SYS_TEXT_BASE
+
+#endif /* __CONFIG_ZYNQ_COMMON_H */
diff --git a/include/configs/zynq.h b/include/configs/zynq.h
deleted file mode 100644
index b9f381f645..0000000000
--- a/include/configs/zynq.h
+++ /dev/null
@@ -1,140 +0,0 @@
-/*
- * (C) Copyright 2012 Michal Simek <monstr@monstr.eu>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef __CONFIG_ZYNQ_H
-#define __CONFIG_ZYNQ_H
-
-#define CONFIG_ARMV7 /* This is an ARM V7 CPU core */
-#define CONFIG_ZYNQ
-
-/* CPU clock */
-#define CONFIG_CPU_FREQ_HZ	800000000
-#define CONFIG_SYS_HZ		1000
-
-/* Ram */
-#define CONFIG_NR_DRAM_BANKS		1
-#define CONFIG_SYS_TEXT_BASE		0
-#define CONFIG_SYS_SDRAM_BASE		0
-#define CONFIG_SYS_SDRAM_SIZE		0x40000000
-#define CONFIG_SYS_MEMTEST_START	CONFIG_SYS_SDRAM_BASE
-#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_SDRAM_BASE + 0x1000)
-
-/* The following table includes the supported baudrates */
-#define CONFIG_SYS_BAUDRATE_TABLE  \
-	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400}
-
-#define CONFIG_BAUDRATE		115200
-
-/* XPSS Serial driver */
-#define CONFIG_ZYNQ_SERIAL
-#define CONFIG_ZYNQ_SERIAL_BASEADDR0	0xE0001000
-#define CONFIG_ZYNQ_SERIAL_BAUDRATE0	CONFIG_BAUDRATE
-#define CONFIG_ZYNQ_SERIAL_CLOCK0	50000000
-
-/* Ethernet driver */
-#define CONFIG_NET_MULTI
-#define CONFIG_ZYNQ_GEM
-#define CONFIG_ZYNQ_GEM0
-#define CONFIG_ZYNQ_GEM_PHY_ADDR0	7
-
-#define CONFIG_ZYNQ_SDHCI
-#define CONFIG_ZYNQ_SDHCI0
-
-/* MMC */
-#if defined(CONFIG_ZYNQ_SDHCI0) || defined(CONFIG_ZYNQ_SDHCI1)
-# define CONFIG_MMC
-# define CONFIG_GENERIC_MMC
-# define CONFIG_SDHCI
-# define CONFIG_ZYNQ_SDHCI
-# define CONFIG_CMD_MMC
-# define CONFIG_CMD_FAT
-# define CONFIG_SUPPORT_VFAT
-# define CONFIG_CMD_EXT2
-# define CONFIG_DOS_PARTITION
-#endif
-
-#define CONFIG_ZYNQ_I2C0
-
-/* I2C */
-#if defined(CONFIG_ZYNQ_I2C0) || defined(CONFIG_ZYNQ_I2C1)
-# define CONFIG_CMD_I2C
-# define CONFIG_ZYNQ_I2C
-# define CONFIG_HARD_I2C
-# define CONFIG_SYS_I2C_SPEED		100000
-# define CONFIG_SYS_I2C_SLAVE		1
-#endif
-
-#if defined(CONFIG_ZYNQ_DCC)
-# define CONFIG_ARM_DCC
-# define CONFIG_CPU_V6 /* Required by CONFIG_ARM_DCC */
-#endif
-
-#define CONFIG_ZYNQ_SPI
-
-/* SPI */
-#ifdef CONFIG_ZYNQ_SPI
-# define CONFIG_SPI_FLASH
-# define CONFIG_SPI_FLASH_SST
-# define CONFIG_CMD_SF
-#endif
-
-/* Enable the PL to be downloaded */
-#define CONFIG_FPGA
-#define CONFIG_FPGA_XILINX
-#define CONFIG_FPGA_ZYNQPL
-#define CONFIG_CMD_FPGA
-
-#define CONFIG_BOOTP_SERVERIP
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-#define CONFIG_BOOTP_MAY_FAIL
-
-/* MII and Phylib */
-#define CONFIG_MII
-#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
-#define CONFIG_PHYLIB
-#define CONFIG_PHY_MARVELL
-
-/* Environment */
-#define CONFIG_ENV_IS_NOWHERE
-#define CONFIG_ENV_SIZE 0x10000
-
-#define CONFIG_SYS_NO_FLASH
-
-#define CONFIG_SYS_MALLOC_LEN		0x400000
-#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_SDRAM_BASE
-#define CONFIG_SYS_INIT_RAM_SIZE	CONFIG_SYS_MALLOC_LEN
-#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_INIT_RAM_ADDR + \
-						CONFIG_SYS_INIT_RAM_SIZE - \
-						GENERATED_GBL_DATA_SIZE)
-
-#define CONFIG_SYS_PROMPT	"U-Boot> "
-#define CONFIG_SYS_CBSIZE	256 /* Console I/O Buffer Size */
-#define CONFIG_SYS_PBSIZE	(CONFIG_SYS_CBSIZE + \
-					sizeof(CONFIG_SYS_PROMPT) + 16)
-
-#define CONFIG_SYS_LOAD_ADDR	0
-#define CONFIG_SYS_MAXARGS	15 /* max number of command args */
-#define CONFIG_SYS_LONGHELP
-#define CONFIG_AUTO_COMPLETE
-#define CONFIG_CMDLINE_EDITING
-
-#define CONFIG_SYS_HUSH_PARSER
-#define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
-
-/* OF */
-#define CONFIG_FIT
-#define CONFIG_OF_LIBFDT
-
-/* Commands */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_MII
-
-#endif /* __CONFIG_ZYNQ_H */
diff --git a/include/configs/zynq_microzed.h b/include/configs/zynq_microzed.h
new file mode 100644
index 0000000000..b0328a2cc1
--- /dev/null
+++ b/include/configs/zynq_microzed.h
@@ -0,0 +1,26 @@
+/*
+ * (C) Copyright 2013 Xilinx, Inc.
+ *
+ * Configuration for Micro Zynq Evaluation and Development Board - MicroZedBoard
+ * See zynq-common.h for Zynq common configs
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_ZYNQ_MICROZED_H
+#define __CONFIG_ZYNQ_MICROZED_H
+
+#define CONFIG_SYS_SDRAM_SIZE		(1024 * 1024 * 1024)
+
+#define CONFIG_ZYNQ_SERIAL_UART1
+#define CONFIG_ZYNQ_GEM0
+#define CONFIG_ZYNQ_GEM_PHY_ADDR0	0
+
+#define CONFIG_SYS_NO_FLASH
+
+#define CONFIG_ZYNQ_SDHCI0
+#define CONFIG_DEFAULT_DEVICE_TREE	zynq-microzed
+
+#include <configs/zynq-common.h>
+
+#endif /* __CONFIG_ZYNQ_MICROZED_H */
diff --git a/include/configs/zynq_zc70x.h b/include/configs/zynq_zc70x.h
new file mode 100644
index 0000000000..de0e24129c
--- /dev/null
+++ b/include/configs/zynq_zc70x.h
@@ -0,0 +1,29 @@
+/*
+ * (C) Copyright 2013 Xilinx, Inc.
+ *
+ * Configuration settings for the Xilinx Zynq ZC702 and ZC706 boards
+ * See zynq-common.h for Zynq common configs
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_ZYNQ_ZC70X_H
+#define __CONFIG_ZYNQ_ZC70X_H
+
+#define CONFIG_SYS_SDRAM_SIZE		(1024 * 1024 * 1024)
+
+#define CONFIG_ZYNQ_SERIAL_UART1
+#define CONFIG_ZYNQ_GEM0
+#define CONFIG_ZYNQ_GEM_PHY_ADDR0	7
+
+#define CONFIG_SYS_NO_FLASH
+
+#define CONFIG_ZYNQ_SDHCI0
+#define CONFIG_ZYNQ_I2C0
+#define CONFIG_ZYNQ_EEPROM
+#define CONFIG_ZYNQ_BOOT_FREEBSD
+#define CONFIG_DEFAULT_DEVICE_TREE	zynq-zc702
+
+#include <configs/zynq-common.h>
+
+#endif /* __CONFIG_ZYNQ_ZC70X_H */
diff --git a/include/configs/zynq_zc770.h b/include/configs/zynq_zc770.h
new file mode 100644
index 0000000000..8aa96e7121
--- /dev/null
+++ b/include/configs/zynq_zc770.h
@@ -0,0 +1,42 @@
+/*
+ * (C) Copyright 2013 Xilinx, Inc.
+ *
+ * Configuration settings for the Xilinx Zynq ZC770 board.
+ * See zynq-common.h for Zynq common configs
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#ifndef __CONFIG_ZYNQ_ZC770_H
+#define __CONFIG_ZYNQ_ZC770_H
+
+#define CONFIG_SYS_SDRAM_SIZE		(1024 * 1024 * 1024)
+
+#define CONFIG_SYS_NO_FLASH
+
+#if defined(CONFIG_ZC770_XM010)
+# define CONFIG_ZYNQ_SERIAL_UART1
+# define CONFIG_ZYNQ_GEM0
+# define CONFIG_ZYNQ_GEM_PHY_ADDR0	7
+# define CONFIG_ZYNQ_SDHCI0
+# define CONFIG_ZYNQ_SPI
+# define CONFIG_DEFAULT_DEVICE_TREE	zynq-zc770-xm010
+
+#elif defined(CONFIG_ZC770_XM012)
+# define CONFIG_ZYNQ_SERIAL_UART1
+# undef CONFIG_SYS_NO_FLASH
+# define CONFIG_DEFAULT_DEVICE_TREE	zynq-zc770-xm012
+
+#elif defined(CONFIG_ZC770_XM013)
+# define CONFIG_ZYNQ_SERIAL_UART0
+# define CONFIG_ZYNQ_GEM1
+# define CONFIG_ZYNQ_GEM_PHY_ADDR1	7
+# define CONFIG_DEFAULT_DEVICE_TREE	zynq-zc770-xm013
+
+#else
+# define CONFIG_ZYNQ_SERIAL_UART0
+#endif
+
+#include <configs/zynq-common.h>
+
+#endif /* __CONFIG_ZYNQ_ZC770_H */
diff --git a/include/configs/zynq_zed.h b/include/configs/zynq_zed.h
new file mode 100644
index 0000000000..274140cb3f
--- /dev/null
+++ b/include/configs/zynq_zed.h
@@ -0,0 +1,27 @@
+/*
+ * (C) Copyright 2013 Xilinx, Inc.
+ *
+ * Configuration for Zynq Evaluation and Development Board - ZedBoard
+ * See zynq-common.h for Zynq common configs
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_ZYNQ_ZED_H
+#define __CONFIG_ZYNQ_ZED_H
+
+#define CONFIG_SYS_SDRAM_SIZE		(512 * 1024 * 1024)
+
+#define CONFIG_ZYNQ_SERIAL_UART1
+#define CONFIG_ZYNQ_GEM0
+#define CONFIG_ZYNQ_GEM_PHY_ADDR0	0
+
+#define CONFIG_SYS_NO_FLASH
+
+#define CONFIG_ZYNQ_SDHCI0
+#define CONFIG_ZYNQ_BOOT_FREEBSD
+#define CONFIG_DEFAULT_DEVICE_TREE	zynq-zed
+
+#include <configs/zynq-common.h>
+
+#endif /* __CONFIG_ZYNQ_ZED_H */
diff --git a/include/cpsw.h b/include/cpsw.h
index 743cb96e7e..a73843d2f7 100644
--- a/include/cpsw.h
+++ b/include/cpsw.h
@@ -19,7 +19,7 @@
 struct cpsw_slave_data {
 	u32		slave_reg_ofs;
 	u32		sliver_reg_ofs;
-	int		phy_id;
+	int		phy_addr;
 	int		phy_if;
 };
 
diff --git a/include/cramfs/cramfs_fs_sb.h b/include/cramfs/cramfs_fs_sb.h
deleted file mode 100644
index bc23f94b94..0000000000
--- a/include/cramfs/cramfs_fs_sb.h
+++ /dev/null
@@ -1,19 +0,0 @@
-#ifndef _CRAMFS_FS_SB
-#define _CRAMFS_FS_SB
-
-/*
- * cramfs super-block data in memory
- */
-struct cramfs_sb_info {
-			unsigned long magic;
-			unsigned long size;
-			unsigned long blocks;
-			unsigned long files;
-			unsigned long flags;
-#ifdef CONFIG_CRAMFS_LINEAR
-			unsigned long linear_phys_addr;
-			char *        linear_virt_addr;
-#endif
-};
-
-#endif
diff --git a/include/cros_ec.h b/include/cros_ec.h
index 1e89f29eea..1e4d8db96b 100644
--- a/include/cros_ec.h
+++ b/include/cros_ec.h
@@ -20,6 +20,7 @@ enum cros_ec_interface_t {
 	CROS_EC_IF_SPI,
 	CROS_EC_IF_I2C,
 	CROS_EC_IF_LPC,	/* Intel Low Pin Count interface */
+	CROS_EC_IF_SANDBOX,
 };
 
 /* Our configuration information */
@@ -33,7 +34,7 @@ struct cros_ec_dev {
 	unsigned int bus_num;		/* Bus number (for I2C) */
 	unsigned int max_frequency;	/* Maximum interface frequency */
 	struct fdt_gpio_state ec_int;	/* GPIO used as EC interrupt line */
-	int cmd_version_is_supported;   /* Device supports command versions */
+	int protocol_version;           /* Protocol version to use */
 	int optimise_flash_write;	/* Don't write erased flash blocks */
 
 	/*
@@ -63,6 +64,17 @@ struct mbkp_keyscan {
 	uint8_t data[CROS_EC_KEYSCAN_COLS];
 };
 
+/* Holds information about the Chrome EC */
+struct fdt_cros_ec {
+	struct fmap_entry flash;	/* Address and size of EC flash */
+	/*
+	 * Byte value of erased flash, or -1 if not known. It is normally
+	 * 0xff but some flash devices use 0 (e.g. STM32Lxxx)
+	 */
+	int flash_erase_value;
+	struct fmap_entry region[EC_FLASH_REGION_COUNT];
+};
+
 /**
  * Read the ID of the CROS-EC device
  *
@@ -140,7 +152,7 @@ enum {
 };
 
 /**
- * Set up the Chromium OS matrix keyboard protocol
+ * Initialise the Chromium OS EC driver
  *
  * @param blob		Device tree blob containing setup information
  * @param cros_ecp        Returns pointer to the cros_ec device, or NULL if none
@@ -157,7 +169,7 @@ int cros_ec_init(const void *blob, struct cros_ec_dev **cros_ecp);
  * @param info		Place to put the info structure
  */
 int cros_ec_info(struct cros_ec_dev *dev,
-		struct ec_response_cros_ec_info *info);
+		struct ec_response_mkbp_info *info);
 
 /**
  * Read the host event flags
@@ -226,6 +238,7 @@ struct cros_ec_dev *board_get_cros_ec_dev(void);
 int cros_ec_i2c_init(struct cros_ec_dev *dev, const void *blob);
 int cros_ec_spi_init(struct cros_ec_dev *dev, const void *blob);
 int cros_ec_lpc_init(struct cros_ec_dev *dev, const void *blob);
+int cros_ec_sandbox_init(struct cros_ec_dev *dev, const void *blob);
 
 /**
  * Read information from the fdt for the i2c cros_ec interface
@@ -246,11 +259,19 @@ int cros_ec_i2c_decode_fdt(struct cros_ec_dev *dev, const void *blob);
 int cros_ec_spi_decode_fdt(struct cros_ec_dev *dev, const void *blob);
 
 /**
+ * Read information from the fdt for the sandbox cros_ec interface
+ *
+ * @param dev		CROS-EC device
+ * @param blob		Device tree blob
+ * @return 0 if ok, -1 if we failed to read all required information
+ */
+int cros_ec_sandbox_decode_fdt(struct cros_ec_dev *dev, const void *blob);
+
+/**
  * Check whether the LPC interface supports new-style commands.
  *
  * LPC has its own way of doing this, which involves checking LPC values
- * visible to the host. Do this, and update dev->cmd_version_is_supported
- * accordingly.
+ * visible to the host. Do this, and update dev->protocol_version accordingly.
  *
  * @param dev		CROS-EC device to check
  */
@@ -302,6 +323,21 @@ int cros_ec_spi_command(struct cros_ec_dev *dev, uint8_t cmd, int cmd_version,
 		     uint8_t **dinp, int din_len);
 
 /**
+ * Send a packet to a CROS-EC device and return the response packet.
+ *
+ * Expects the request packet to be stored in dev->dout.  Stores the response
+ * packet in dev->din.
+ *
+ * @param dev		CROS-EC device
+ * @param out_bytes	Size of request packet to output
+ * @param in_bytes	Maximum size of response packet to receive
+ * @return number of bytes in response packet, or <0 on error
+ */
+int cros_ec_spi_packet(struct cros_ec_dev *dev, int out_bytes, int in_bytes);
+int cros_ec_sandbox_packet(struct cros_ec_dev *dev, int out_bytes,
+			   int in_bytes);
+
+/**
  * Dump a block of data for a command.
  *
  * @param name	Name for data (e.g. 'in', 'out')
@@ -431,4 +467,52 @@ int cros_ec_set_ldo(struct cros_ec_dev *dev, uint8_t index, uint8_t state);
  * @return 0 if ok, -1 on error
  */
 int cros_ec_get_ldo(struct cros_ec_dev *dev, uint8_t index, uint8_t *state);
+
+/**
+ * Initialize the Chrome OS EC at board initialization time.
+ *
+ * @return 0 if ok, -ve on error
+ */
+int cros_ec_board_init(void);
+
+/**
+ * Get access to the error reported when cros_ec_board_init() was called
+ *
+ * This permits delayed reporting of the EC error if it failed during
+ * early init.
+ *
+ * @return error (0 if there was no error, -ve if there was an error)
+ */
+int cros_ec_get_error(void);
+
+/**
+ * Returns information from the FDT about the Chrome EC flash
+ *
+ * @param blob		FDT blob to use
+ * @param config	Structure to use to return information
+ */
+int cros_ec_decode_ec_flash(const void *blob, struct fdt_cros_ec *config);
+
+/**
+ * Check the current keyboard state, in case recovery mode is requested.
+ * This function is for sandbox only.
+ *
+ * @param ec		CROS-EC device
+ */
+void cros_ec_check_keyboard(struct cros_ec_dev *dev);
+
+/*
+ * Tunnel an I2C transfer to the EC
+ *
+ * @param dev		CROS-EC device
+ * @param chip		Chip address (7-bit I2C address)
+ * @param addr		Register address to read/write
+ * @param alen		Length of register address in bytes
+ * @param buffer	Buffer containing data to read/write
+ * @param len		Length of buffer
+ * @param is_read	1 if this is a read, 0 if this is a write
+ */
+int cros_ec_i2c_xfer(struct cros_ec_dev *dev, uchar chip, uint addr,
+		     int alen, uchar *buffer, int len, int is_read);
+
 #endif
diff --git a/include/cros_ec_message.h b/include/cros_ec_message.h
index b1da53db1b..36e2d83ce1 100644
--- a/include/cros_ec_message.h
+++ b/include/cros_ec_message.h
@@ -23,7 +23,7 @@ enum {
 	MSG_PROTO_BYTES		= MSG_HEADER_BYTES + MSG_TRAILER_BYTES,
 
 	/* Max length of messages */
-	MSG_BYTES		= EC_HOST_PARAM_SIZE + MSG_PROTO_BYTES,
+	MSG_BYTES		= EC_PROTO2_MAX_PARAM_SIZE + MSG_PROTO_BYTES,
 };
 
 #endif
diff --git a/include/da9030.h b/include/da9030.h
deleted file mode 100644
index 275d6813b0..0000000000
--- a/include/da9030.h
+++ /dev/null
@@ -1,102 +0,0 @@
-/*
- * (C) Copyright 2006 DENX Software Engineering
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-/* DA9030 register definitions */
-#define CID			0x00
-#define EVENT_A			0x01
-#define EVENT_B			0x02
-#define EVENT_C			0x03
-#define STATUS			0x04
-#define IRQ_MASK_A		0x05
-#define IRQ_MASK_B		0x06
-#define IRQ_MASK_C		0x07
-#define SYS_CONTROL_A		0x08
-#define SYS_CONTROL_B		0x09
-#define FAULT_LOG		0x0A
-#define LDO_10_11		0x10
-#define LDO_15			0x11
-#define LDO_14_16		0x12
-#define LDO_18_19		0x13
-#define LDO_17_SIMCP0		0x14
-#define BUCK2_DVC1		0x15
-#define BUCK2_DVC2		0x16
-#define REG_CONTROL_1_17	0x17
-#define REG_CONTROL_2_18	0x18
-#define USBPUMP			0x19
-#define SLEEP_CONTROL		0x1A
-#define STARTUP_CONTROL		0x1B
-#define LED1_CONTROL		0x20
-#define LED2_CONTROL		0x21
-#define LED3_CONTROL		0x22
-#define LED4_CONTROL		0x23
-#define LEDPC_CONTROL		0x24
-#define WLED_CONTROL		0x25
-#define MISC_CONTROLA		0x26
-#define MISC_CONTROLB		0x27
-#define CHARGE_CONTROL		0x28
-#define CCTR_CONTROL		0x29
-#define TCTR_CONTROL		0x2A
-#define CHARGE_PULSE		0x2B
-
-/* ... some missing ...*/
-
-#define LDO1			0x90
-#define LDO2_3			0x91
-#define LDO4_5			0x92
-#define LDO6_SIMCP		0x93
-#define LDO7_8			0x94
-#define LDO9_12			0x95
-#define BUCK			0x96
-#define REG_CONTROL_1_97	0x97
-#define REG_CONTROL_2_98	0x98
-#define REG_SLEEP_CONTROL1	0x99
-#define REG_SLEEP_CONTROL2	0x9A
-#define REG_SLEEP_CONTROL3	0x9B
-#define ADC_MAN_CONTROL		0xA0
-#define ADC_AUTO_CONTROL	0xA1
-#define VBATMON			0xA2
-#define VBATMONTXMON		0xA3
-#define TBATHIGHP		0xA4
-#define TBATHIGHN		0xA5
-#define TBATLOW			0xA6
-#define MAN_RES			0xB0
-#define VBAT_RES		0xB1
-#define VBATMIN_RES		0xB2
-#define VBATMINTXON_RES		0xB3
-#define ICHMAX_RES		0xB4
-#define ICHMIN_RES		0xB5
-#define ICHAVERAGE_RES		0xB6
-#define VCHMAX_RES		0xB7
-#define VCHMIN_RES		0xB8
-#define TBAT_RES		0xB9
-#define ADC_IN4_RES		0xBA
-
-#define STATUS_ONKEY_N		0x1	/* current ONKEY_N value */
-#define STATUS_PWREN1		(1<<1)	/* PWREN1 value */
-#define STATUS_EXTON		(1<<2)	/* EXTON value */
-#define STATUS_CHDET		(1<<3)	/* Charger detection status */
-#define STATUS_TBAT		(1<<4)	/* Battery over/under temperature status */
-#define STATUS_VBATMON		(1<<5)	/* VBATMON comparison status */
-#define STATUS_VBATMONTXON	(1<<6)	/* VBATMONTXON comparison status */
-#define STATUS_CHIOVER		(1<<7)	/* Charge overcurrent */
-
-#define SYS_CONTROL_A_SLEEP_N_PIN_ENABLE	0x1
-#define SYS_CONTROL_A_SHUT_DOWN			(1<<1)
-#define SYS_CONTROL_A_HWRES_ENABLE		(1<<2)
-#define SYS_CONTROL_A_WDOG_ACTION		(1<<3)
-#define SYS_CONTROL_A_WATCHDOG			(1<<7)
-
-#define MISC_CONTROLB_USB_INT_RISING		(1<<2)
-#define MISC_CONTROLB_SESSION_VALID_EN		(1<<3)
-
-#define USB_PUMP_USBVE				(1<<0)
-#define USB_PUMP_USBVEP				(1<<1)
-#define USB_PUMP_SRP_DETECT			(1<<2)
-#define USB_PUMP_SESSION_VALID			(1<<3)
-#define USB_PUMP_VBUS_VALID_4_0			(1<<4)
-#define USB_PUMP_VBUS_VALID_4_4			(1<<5)
-#define USB_PUMP_EN_USBVE			(1<<6)
-#define USB_PUMP_EN_USBVEP			(1<<7)
diff --git a/include/ddr_spd.h b/include/ddr_spd.h
index f5809e5e1b..15a3e8d351 100644
--- a/include/ddr_spd.h
+++ b/include/ddr_spd.h
@@ -126,8 +126,8 @@ typedef struct ddr2_spd_eeprom_s {
 	unsigned char tdqsq;       /* 44 Max DQS to DQ skew (tDQSQ max) */
 	unsigned char tqhs;        /* 45 Max Read DataHold skew (tQHS) */
 	unsigned char pll_relock;  /* 46 PLL Relock time */
-	unsigned char Tcasemax;    /* 47 Tcasemax */
-	unsigned char psiTAdram;   /* 48 Thermal Resistance of DRAM Package from
+	unsigned char t_casemax;    /* 47 Tcasemax */
+	unsigned char psi_ta_dram;  /* 48 Thermal Resistance of DRAM Package from
 					 Top (Case) to Ambient (Psi T-A DRAM) */
 	unsigned char dt0_mode;    /* 49 DRAM Case Temperature Rise from Ambient
 					 due to Activate-Precharge/Mode Bits
@@ -153,9 +153,9 @@ typedef struct ddr2_spd_eeprom_s {
 	unsigned char dt7;         /* 57 DRAM Case Temperature Rise from Ambient
 					 due to Bank Interleave Reads with
 					 Auto-Precharge (DT7) */
-	unsigned char psiTApll;    /* 58 Thermal Resistance of PLL Package form
+	unsigned char psi_ta_pll;  /* 58 Thermal Resistance of PLL Package form
 					 Top (Case) to Ambient (Psi T-A PLL) */
-	unsigned char psiTAreg;    /* 59 Thermal Reisitance of Register Package
+	unsigned char psi_ta_reg;    /* 59 Thermal Reisitance of Register Package
 					 from Top (Case) to Ambient
 					 (Psi T-A Register) */
 	unsigned char dtpllactive; /* 60 PLL Case Temperature Rise from Ambient
@@ -191,41 +191,41 @@ typedef struct ddr3_spd_eeprom_s {
 					     Dividend / Divisor */
 	unsigned char mtb_dividend;    /* 10 Medium Timebase (MTB) Dividend */
 	unsigned char mtb_divisor;     /* 11 Medium Timebase (MTB) Divisor */
-	unsigned char tCK_min;         /* 12 SDRAM Minimum Cycle Time */
+	unsigned char tck_min;         /* 12 SDRAM Minimum Cycle Time */
 	unsigned char res_13;          /* 13 Reserved */
 	unsigned char caslat_lsb;      /* 14 CAS Latencies Supported,
 					     Least Significant Byte */
 	unsigned char caslat_msb;      /* 15 CAS Latencies Supported,
 					     Most Significant Byte */
-	unsigned char tAA_min;         /* 16 Min CAS Latency Time */
-	unsigned char tWR_min;         /* 17 Min Write REcovery Time */
-	unsigned char tRCD_min;        /* 18 Min RAS# to CAS# Delay Time */
-	unsigned char tRRD_min;        /* 19 Min Row Active to
+	unsigned char taa_min;         /* 16 Min CAS Latency Time */
+	unsigned char twr_min;         /* 17 Min Write REcovery Time */
+	unsigned char trcd_min;        /* 18 Min RAS# to CAS# Delay Time */
+	unsigned char trrd_min;        /* 19 Min Row Active to
 					     Row Active Delay Time */
-	unsigned char tRP_min;         /* 20 Min Row Precharge Delay Time */
-	unsigned char tRAS_tRC_ext;    /* 21 Upper Nibbles for tRAS and tRC */
-	unsigned char tRAS_min_lsb;    /* 22 Min Active to Precharge
+	unsigned char trp_min;         /* 20 Min Row Precharge Delay Time */
+	unsigned char tras_trc_ext;    /* 21 Upper Nibbles for tRAS and tRC */
+	unsigned char tras_min_lsb;    /* 22 Min Active to Precharge
 					     Delay Time */
-	unsigned char tRC_min_lsb;     /* 23 Min Active to Active/Refresh
+	unsigned char trc_min_lsb;     /* 23 Min Active to Active/Refresh
 					     Delay Time, LSB */
-	unsigned char tRFC_min_lsb;    /* 24 Min Refresh Recovery Delay Time */
-	unsigned char tRFC_min_msb;    /* 25 Min Refresh Recovery Delay Time */
-	unsigned char tWTR_min;        /* 26 Min Internal Write to
+	unsigned char trfc_min_lsb;    /* 24 Min Refresh Recovery Delay Time */
+	unsigned char trfc_min_msb;    /* 25 Min Refresh Recovery Delay Time */
+	unsigned char twtr_min;        /* 26 Min Internal Write to
 					     Read Command Delay Time */
-	unsigned char tRTP_min;        /* 27 Min Internal Read to Precharge
+	unsigned char trtp_min;        /* 27 Min Internal Read to Precharge
 					     Command Delay Time */
-	unsigned char tFAW_msb;        /* 28 Upper Nibble for tFAW */
-	unsigned char tFAW_min;        /* 29 Min Four Activate Window
+	unsigned char tfaw_msb;        /* 28 Upper Nibble for tFAW */
+	unsigned char tfaw_min;        /* 29 Min Four Activate Window
 					     Delay Time*/
 	unsigned char opt_features;    /* 30 SDRAM Optional Features */
 	unsigned char therm_ref_opt;   /* 31 SDRAM Thermal and Refresh Opts */
 	unsigned char therm_sensor;    /* 32 Module Thermal Sensor */
 	unsigned char device_type;     /* 33 SDRAM device type */
-	int8_t fine_tCK_min;	       /* 34 Fine offset for tCKmin */
-	int8_t fine_tAA_min;	       /* 35 Fine offset for tAAmin */
-	int8_t fine_tRCD_min;	       /* 36 Fine offset for tRCDmin */
-	int8_t fine_tRP_min;	       /* 37 Fine offset for tRPmin */
-	int8_t fine_tRC_min;	       /* 38 Fine offset for tRCmin */
+	int8_t fine_tck_min;	       /* 34 Fine offset for tCKmin */
+	int8_t fine_taa_min;	       /* 35 Fine offset for tAAmin */
+	int8_t fine_trcd_min;	       /* 36 Fine offset for tRCDmin */
+	int8_t fine_trp_min;	       /* 37 Fine offset for tRPmin */
+	int8_t fine_trc_min;	       /* 38 Fine offset for tRCmin */
 	unsigned char res_39_59[21];   /* 39-59 Reserved, General Section */
 
 	/* Module-Specific Section: Bytes 60-116 */
diff --git a/include/dfu.h b/include/dfu.h
index b2ecf1bebe..6c71ecbe35 100644
--- a/include/dfu.h
+++ b/include/dfu.h
@@ -77,6 +77,12 @@ static inline unsigned int get_mmc_blk_size(int dev)
 #ifndef CONFIG_SYS_DFU_MAX_FILE_SIZE
 #define CONFIG_SYS_DFU_MAX_FILE_SIZE CONFIG_SYS_DFU_DATA_BUF_SIZE
 #endif
+#ifndef DFU_DEFAULT_POLL_TIMEOUT
+#define DFU_DEFAULT_POLL_TIMEOUT 0
+#endif
+#ifndef DFU_MANIFEST_POLL_TIMEOUT
+#define DFU_MANIFEST_POLL_TIMEOUT	DFU_DEFAULT_POLL_TIMEOUT
+#endif
 
 struct dfu_entity {
 	char			name[DFU_NAME_SIZE];
@@ -126,11 +132,16 @@ const char *dfu_get_layout(enum dfu_layout l);
 struct dfu_entity *dfu_get_entity(int alt);
 char *dfu_extract_token(char** e, int *n);
 void dfu_trigger_reset(void);
+int dfu_get_alt(char *name);
 bool dfu_reset(void);
 int dfu_init_env_entities(char *interface, int dev);
+unsigned char *dfu_get_buf(void);
+unsigned char *dfu_free_buf(void);
+unsigned long dfu_get_buf_size(void);
 
 int dfu_read(struct dfu_entity *de, void *buf, int size, int blk_seq_num);
 int dfu_write(struct dfu_entity *de, void *buf, int size, int blk_seq_num);
+int dfu_flush(struct dfu_entity *de, void *buf, int size, int blk_seq_num);
 /* Device specific */
 #ifdef CONFIG_DFU_MMC
 extern int dfu_fill_entity_mmc(struct dfu_entity *dfu, char *s);
diff --git a/include/dm-demo.h b/include/dm-demo.h
new file mode 100644
index 0000000000..6e38d3c5b3
--- /dev/null
+++ b/include/dm-demo.h
@@ -0,0 +1,36 @@
+/*
+ * Copyright (c) 2013 Google, Inc
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __DM_DEMO_H
+#define __DM_DEMO_H
+
+#include <dm.h>
+
+/**
+ * struct dm_demo_pdata - configuration data for demo instance
+ *
+ * @colour: Color of the demo
+ * @sides: Numbers of sides
+ * @default_char: Default ASCII character to output (65 = 'A')
+ */
+struct dm_demo_pdata {
+	const char *colour;
+	int sides;
+	int default_char;
+};
+
+struct demo_ops {
+	int (*hello)(struct device *dev, int ch);
+	int (*status)(struct device *dev, int *status);
+};
+
+int demo_hello(struct device *dev, int ch);
+int demo_status(struct device *dev, int *status);
+int demo_list(void);
+
+int demo_parse_dt(struct device *dev);
+
+#endif
diff --git a/include/dm.h b/include/dm.h
new file mode 100644
index 0000000000..8bbb21b575
--- /dev/null
+++ b/include/dm.h
@@ -0,0 +1,14 @@
+/*
+ * Copyright (c) 2013 Google, Inc
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _DM_H_
+#define _DM_H
+
+#include <dm/device.h>
+#include <dm/platdata.h>
+#include <dm/uclass.h>
+
+#endif
diff --git a/include/dm/device-internal.h b/include/dm/device-internal.h
new file mode 100644
index 0000000000..c026e8e49c
--- /dev/null
+++ b/include/dm/device-internal.h
@@ -0,0 +1,87 @@
+/*
+ * Copyright (C) 2013 Google, Inc
+ *
+ * (C) Copyright 2012
+ * Pavel Herrmann <morpheus.ibis@gmail.com>
+ * Marek Vasut <marex@denx.de>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _DM_DEVICE_INTERNAL_H
+#define _DM_DEVICE_INTERNAL_H
+
+struct device;
+
+/**
+ * device_bind() - Create a device and bind it to a driver
+ *
+ * Called to set up a new device attached to a driver. The device will either
+ * have platdata, or a device tree node which can be used to create the
+ * platdata.
+ *
+ * Once bound a device exists but is not yet active until device_probe() is
+ * called.
+ *
+ * @parent: Pointer to device's parent, under which this driver will exist
+ * @drv: Device's driver
+ * @name: Name of device (e.g. device tree node name)
+ * @platdata: Pointer to data for this device - the structure is device-
+ * specific but may include the device's I/O address, etc.. This is NULL for
+ * devices which use device tree.
+ * @of_offset: Offset of device tree node for this device. This is -1 for
+ * devices which don't use device tree.
+ * @devp: Returns a pointer to the bound device
+ * @return 0 if OK, -ve on error
+ */
+int device_bind(struct device *parent, struct driver *drv,
+		const char *name, void *platdata, int of_offset,
+		struct device **devp);
+
+/**
+ * device_bind_by_name: Create a device and bind it to a driver
+ *
+ * This is a helper function used to bind devices which do not use device
+ * tree.
+ *
+ * @parent: Pointer to device's parent
+ * @info: Name and platdata for this device
+ * @devp: Returns a pointer to the bound device
+ * @return 0 if OK, -ve on error
+ */
+int device_bind_by_name(struct device *parent, const struct driver_info *info,
+			struct device **devp);
+
+/**
+ * device_probe() - Probe a device, activating it
+ *
+ * Activate a device so that it is ready for use. All its parents are probed
+ * first.
+ *
+ * @dev: Pointer to device to probe
+ * @return 0 if OK, -ve on error
+ */
+int device_probe(struct device *dev);
+
+/**
+ * device_remove() - Remove a device, de-activating it
+ *
+ * De-activate a device so that it is no longer ready for use. All its
+ * children are deactivated first.
+ *
+ * @dev: Pointer to device to remove
+ * @return 0 if OK, -ve on error (an error here is normally a very bad thing)
+ */
+int device_remove(struct device *dev);
+
+/**
+ * device_unbind() - Unbind a device, destroying it
+ *
+ * Unbind a device and remove all memory used by it
+ *
+ * @dev: Pointer to device to unbind
+ * @return 0 if OK, -ve on error
+ */
+int device_unbind(struct device *dev);
+
+#endif
diff --git a/include/dm/device.h b/include/dm/device.h
new file mode 100644
index 0000000000..4cd38ed2d0
--- /dev/null
+++ b/include/dm/device.h
@@ -0,0 +1,159 @@
+/*
+ * Copyright (c) 2013 Google, Inc
+ *
+ * (C) Copyright 2012
+ * Pavel Herrmann <morpheus.ibis@gmail.com>
+ * Marek Vasut <marex@denx.de>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _DM_DEVICE_H
+#define _DM_DEVICE_H
+
+#include <dm/uclass-id.h>
+#include <linker_lists.h>
+#include <linux/list.h>
+
+struct driver_info;
+
+/* Driver is active (probed). Cleared when it is removed */
+#define DM_FLAG_ACTIVATED	(1 << 0)
+
+/* DM is responsible for allocating and freeing platdata */
+#define DM_FLAG_ALLOC_PDATA	(2 << 0)
+
+/**
+ * struct device - An instance of a driver
+ *
+ * This holds information about a device, which is a driver bound to a
+ * particular port or peripheral (essentially a driver instance).
+ *
+ * A device will come into existence through a 'bind' call, either due to
+ * a U_BOOT_DEVICE() macro (in which case platdata is non-NULL) or a node
+ * in the device tree (in which case of_offset is >= 0). In the latter case
+ * we translate the device tree information into platdata in a function
+ * implemented by the driver ofdata_to_platdata method (called just before the
+ * probe method if the device has a device tree node.
+ *
+ * All three of platdata, priv and uclass_priv can be allocated by the
+ * driver, or you can use the auto_alloc_size members of struct driver and
+ * struct uclass_driver to have driver model do this automatically.
+ *
+ * @driver: The driver used by this device
+ * @name: Name of device, typically the FDT node name
+ * @platdata: Configuration data for this device
+ * @of_offset: Device tree node offset for this device (- for none)
+ * @parent: Parent of this device, or NULL for the top level device
+ * @priv: Private data for this device
+ * @uclass: Pointer to uclass for this device
+ * @uclass_priv: The uclass's private data for this device
+ * @uclass_node: Used by uclass to link its devices
+ * @child_head: List of children of this device
+ * @sibling_node: Next device in list of all devices
+ * @flags: Flags for this device DM_FLAG_...
+ */
+struct device {
+	struct driver *driver;
+	const char *name;
+	void *platdata;
+	int of_offset;
+	struct device *parent;
+	void *priv;
+	struct uclass *uclass;
+	void *uclass_priv;
+	struct list_head uclass_node;
+	struct list_head child_head;
+	struct list_head sibling_node;
+	uint32_t flags;
+};
+
+/* Returns the operations for a device */
+#define device_get_ops(dev)	(dev->driver->ops)
+
+/* Returns non-zero if the device is active (probed and not removed) */
+#define device_active(dev)	((dev)->flags & DM_FLAG_ACTIVATED)
+
+/**
+ * struct device_id - Lists the compatible strings supported by a driver
+ * @compatible: Compatible string
+ * @data: Data for this compatible string
+ */
+struct device_id {
+	const char *compatible;
+	ulong data;
+};
+
+/**
+ * struct driver - A driver for a feature or peripheral
+ *
+ * This holds methods for setting up a new device, and also removing it.
+ * The device needs information to set itself up - this is provided either
+ * by platdata or a device tree node (which we find by looking up
+ * matching compatible strings with of_match).
+ *
+ * Drivers all belong to a uclass, representing a class of devices of the
+ * same type. Common elements of the drivers can be implemented in the uclass,
+ * or the uclass can provide a consistent interface to the drivers within
+ * it.
+ *
+ * @name: Device name
+ * @id: Identiies the uclass we belong to
+ * @of_match: List of compatible strings to match, and any identifying data
+ * for each.
+ * @bind: Called to bind a device to its driver
+ * @probe: Called to probe a device, i.e. activate it
+ * @remove: Called to remove a device, i.e. de-activate it
+ * @unbind: Called to unbind a device from its driver
+ * @ofdata_to_platdata: Called before probe to decode device tree data
+ * @priv_auto_alloc_size: If non-zero this is the size of the private data
+ * to be allocated in the device's ->priv pointer. If zero, then the driver
+ * is responsible for allocating any data required.
+ * @platdata_auto_alloc_size: If non-zero this is the size of the
+ * platform data to be allocated in the device's ->platdata pointer.
+ * This is typically only useful for device-tree-aware drivers (those with
+ * an of_match), since drivers which use platdata will have the data
+ * provided in the U_BOOT_DEVICE() instantiation.
+ * ops: Driver-specific operations. This is typically a list of function
+ * pointers defined by the driver, to implement driver functions required by
+ * the uclass.
+ */
+struct driver {
+	char *name;
+	enum uclass_id id;
+	const struct device_id *of_match;
+	int (*bind)(struct device *dev);
+	int (*probe)(struct device *dev);
+	int (*remove)(struct device *dev);
+	int (*unbind)(struct device *dev);
+	int (*ofdata_to_platdata)(struct device *dev);
+	int priv_auto_alloc_size;
+	int platdata_auto_alloc_size;
+	const void *ops;	/* driver-specific operations */
+};
+
+/* Declare a new U-Boot driver */
+#define U_BOOT_DRIVER(__name)						\
+	ll_entry_declare(struct driver, __name, driver)
+
+/**
+ * dev_get_platdata() - Get the platform data for a device
+ *
+ * This checks that dev is not NULL, but no other checks for now
+ *
+ * @dev		Device to check
+ * @return platform data, or NULL if none
+ */
+void *dev_get_platdata(struct device *dev);
+
+/**
+ * dev_get_priv() - Get the private data for a device
+ *
+ * This checks that dev is not NULL, but no other checks for now
+ *
+ * @dev		Device to check
+ * @return private data, or NULL if none
+ */
+void *dev_get_priv(struct device *dev);
+
+#endif
diff --git a/include/dm/lists.h b/include/dm/lists.h
new file mode 100644
index 0000000000..0d09f9a14f
--- /dev/null
+++ b/include/dm/lists.h
@@ -0,0 +1,39 @@
+/*
+ * Copyright (c) 2013 Google, Inc
+ *
+ * (C) Copyright 2012
+ * Pavel Herrmann <morpheus.ibis@gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _DM_LISTS_H_
+#define _DM_LISTS_H_
+
+#include <dm/uclass-id.h>
+
+/**
+ * lists_driver_lookup_name() - Return u_boot_driver corresponding to name
+ *
+ * This function returns a pointer to a driver given its name. This is used
+ * for binding a driver given its name and platdata.
+ *
+ * @name: Name of driver to look up
+ * @return pointer to driver, or NULL if not found
+ */
+struct driver *lists_driver_lookup_name(const char *name);
+
+/**
+ * lists_uclass_lookup() - Return uclass_driver based on ID of the class
+ * id:		ID of the class
+ *
+ * This function returns the pointer to uclass_driver, which is the class's
+ * base structure based on the ID of the class. Returns NULL on error.
+ */
+struct uclass_driver *lists_uclass_lookup(enum uclass_id id);
+
+int lists_bind_drivers(struct device *parent);
+
+int lists_bind_fdt(struct device *parent, const void *blob, int offset);
+
+#endif
diff --git a/include/dm/platdata.h b/include/dm/platdata.h
new file mode 100644
index 0000000000..0ef3353e74
--- /dev/null
+++ b/include/dm/platdata.h
@@ -0,0 +1,22 @@
+/*
+ * Copyright (c) 2013 Google, Inc
+ *
+ * (C) Copyright 2012
+ * Pavel Herrmann <morpheus.ibis@gmail.com>
+ * Marek Vasut <marex@denx.de>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _DM_PLATDATA_H
+#define _DM_PLATDATA_H
+
+struct driver_info {
+	const char	*name;
+	const void	*platdata;
+};
+
+#define U_BOOT_DEVICE(__name)						\
+	ll_entry_declare(struct driver_info, __name, driver_info)
+
+#endif
diff --git a/include/dm/root.h b/include/dm/root.h
new file mode 100644
index 0000000000..0ebccda355
--- /dev/null
+++ b/include/dm/root.h
@@ -0,0 +1,53 @@
+/*
+ * Copyright (c) 2013 Google, Inc
+ *
+ * (C) Copyright 2012
+ * Pavel Herrmann <morpheus.ibis@gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _DM_ROOT_H_
+#define _DM_ROOT_H_
+
+struct device;
+
+/**
+ * dm_root() - Return pointer to the top of the driver tree
+ *
+ * This function returns pointer to the root node of the driver tree,
+ *
+ * @return pointer to root device, or NULL if not inited yet
+ */
+struct device *dm_root(void);
+
+/**
+ * dm_scan_platdata() - Scan all platform data and bind drivers
+ *
+ * This scans all available platdata and creates drivers for each
+ *
+ * @return 0 if OK, -ve on error
+ */
+int dm_scan_platdata(void);
+
+/**
+ * dm_scan_fdt() - Scan the device tree and bind drivers
+ *
+ * This scans the device tree and creates a driver for each node
+ *
+ * @blob: Pointer to device tree blob
+ * @return 0 if OK, -ve on error
+ */
+int dm_scan_fdt(const void *blob);
+
+/**
+ * dm_init() - Initialize Driver Model structures
+ *
+ * This function will initialize roots of driver tree and class tree.
+ * This needs to be called before anything uses the DM
+ *
+ * @return 0 if OK, -ve on error
+ */
+int dm_init(void);
+
+#endif
diff --git a/include/dm/test.h b/include/dm/test.h
new file mode 100644
index 0000000000..eeaa2eb2f4
--- /dev/null
+++ b/include/dm/test.h
@@ -0,0 +1,167 @@
+/*
+ * Copyright (c) 2013 Google, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __DM_TEST_H
+#define __DM_TEST_H
+
+#include <dm.h>
+
+/**
+ * struct dm_test_cdata - configuration data for test instance
+ *
+ * @ping_add: Amonut to add each time we get a ping
+ * @base: Base address of this device
+ */
+struct dm_test_pdata {
+	int ping_add;
+	uint32_t base;
+};
+
+/**
+ * struct test_ops - Operations supported by the test device
+ *
+ * @ping: Ping operation
+ *	@dev: Device to operate on
+ *	@pingval: Value to ping the device with
+ *	@pingret: Returns resulting value from driver
+ *	@return 0 if OK, -ve on error
+ */
+struct test_ops {
+	int (*ping)(struct device *dev, int pingval, int *pingret);
+};
+
+/* Operations that our test driver supports */
+enum {
+	DM_TEST_OP_BIND = 0,
+	DM_TEST_OP_UNBIND,
+	DM_TEST_OP_PROBE,
+	DM_TEST_OP_REMOVE,
+
+	/* For uclass */
+	DM_TEST_OP_POST_BIND,
+	DM_TEST_OP_PRE_UNBIND,
+	DM_TEST_OP_POST_PROBE,
+	DM_TEST_OP_PRE_REMOVE,
+	DM_TEST_OP_INIT,
+	DM_TEST_OP_DESTROY,
+
+	DM_TEST_OP_COUNT,
+};
+
+/* Test driver types */
+enum {
+	DM_TEST_TYPE_FIRST = 0,
+	DM_TEST_TYPE_SECOND,
+};
+
+/* The number added to the ping total on each probe */
+#define DM_TEST_START_TOTAL	5
+
+/**
+ * struct dm_test_priv - private data for the test devices
+ */
+struct dm_test_priv {
+	int ping_total;
+	int op_count[DM_TEST_OP_COUNT];
+};
+
+/**
+ * struct dm_test_perdev_class_priv - private per-device data for test uclass
+ */
+struct dm_test_uclass_perdev_priv {
+	int base_add;
+};
+
+/**
+ * struct dm_test_uclass_priv - private data for test uclass
+ */
+struct dm_test_uclass_priv {
+	int total_add;
+};
+
+/*
+ * Operation counts for the test driver, used to check that each method is
+ * called correctly
+ */
+extern int dm_testdrv_op_count[DM_TEST_OP_COUNT];
+
+extern struct dm_test_state global_test_state;
+
+/*
+ * struct dm_test_state - Entire state of dm test system
+ *
+ * This is often abreviated to dms.
+ *
+ * @root: Root device
+ * @testdev: Test device
+ * @fail_count: Number of tests that failed
+ * @force_fail_alloc: Force all memory allocs to fail
+ * @skip_post_probe: Skip uclass post-probe processing
+ */
+struct dm_test_state {
+	struct device *root;
+	struct device *testdev;
+	int fail_count;
+	int force_fail_alloc;
+	int skip_post_probe;
+};
+
+/* Test flags for each test */
+enum {
+	DM_TESTF_SCAN_PDATA	= 1 << 0,	/* test needs platform data */
+	DM_TESTF_PROBE_TEST	= 1 << 1,	/* probe test uclass */
+	DM_TESTF_SCAN_FDT	= 1 << 2,	/* scan device tree */
+};
+
+/**
+ * struct dm_test - Information about a driver model test
+ *
+ * @name: Name of test
+ * @func: Function to call to perform test
+ * @flags: Flags indicated pre-conditions for test
+ */
+struct dm_test {
+	const char *name;
+	int (*func)(struct dm_test_state *dms);
+	int flags;
+};
+
+/* Declare a new driver model test */
+#define DM_TEST(_name, _flags)						\
+	ll_entry_declare(struct dm_test, _name, dm_test) = {		\
+		.name = #_name,						\
+		.flags = _flags,					\
+		.func = _name,						\
+	}
+
+/* Declare ping methods for the drivers */
+int test_ping(struct device *dev, int pingval, int *pingret);
+int testfdt_ping(struct device *dev, int pingval, int *pingret);
+
+/**
+ * dm_check_operations() - Check that we can perform ping operations
+ *
+ * This checks that the ping operations work as expected for a device
+ *
+ * @dms: Overall test state
+ * @dev: Device to test
+ * @base: Base address, used to check ping return value
+ * @priv: Pointer to private test information
+ * @return 0 if OK, -ve on error
+ */
+int dm_check_operations(struct dm_test_state *dms, struct device *dev,
+			uint32_t base, struct dm_test_priv *priv);
+
+/**
+ * dm_test_main() - Run all the tests
+ *
+ * This runs all available driver model tests
+ *
+ * @return 0 if OK, -ve on error
+ */
+int dm_test_main(void);
+
+#endif
diff --git a/include/dm/uclass-id.h b/include/dm/uclass-id.h
new file mode 100644
index 0000000000..f0e691c18c
--- /dev/null
+++ b/include/dm/uclass-id.h
@@ -0,0 +1,28 @@
+/*
+ * Copyright (c) 2013 Google, Inc
+ *
+ * (C) Copyright 2012
+ * Pavel Herrmann <morpheus.ibis@gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _DM_UCLASS_ID_H
+#define _DM_UCLASS_ID_H
+
+/* TODO(sjg@chromium.org): this could be compile-time generated */
+enum uclass_id {
+	/* These are used internally by driver model */
+	UCLASS_ROOT = 0,
+	UCLASS_DEMO,
+	UCLASS_TEST,
+	UCLASS_TEST_FDT,
+
+	/* U-Boot uclasses start here */
+	UCLASS_GPIO,
+
+	UCLASS_COUNT,
+	UCLASS_INVALID = -1,
+};
+
+#endif
diff --git a/include/dm/uclass-internal.h b/include/dm/uclass-internal.h
new file mode 100644
index 0000000000..cc65d5259f
--- /dev/null
+++ b/include/dm/uclass-internal.h
@@ -0,0 +1,85 @@
+/*
+ * Copyright (c) 2013 Google, Inc
+ *
+ * (C) Copyright 2012
+ * Pavel Herrmann <morpheus.ibis@gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _DM_UCLASS_INTERNAL_H
+#define _DM_UCLASS_INTERNAL_H
+
+/**
+ * uclass_find_device() - Return n-th child of uclass
+ * @id:		Id number of the uclass
+ * @index:	Position of the child in uclass's list
+ * #devp:	Returns pointer to device, or NULL on error
+ *
+ * The device is not prepared for use - this is an internal function
+ *
+ * @return the uclass pointer of a child at the given index or
+ * return NULL on error.
+ */
+int uclass_find_device(enum uclass_id id, int index, struct device **devp);
+
+/**
+ * uclass_bind_device() - Associate device with a uclass
+ *
+ * Connect the device into uclass's list of devices.
+ *
+ * @dev:	Pointer to the device
+ * #return 0 on success, -ve on error
+ */
+int uclass_bind_device(struct device *dev);
+
+/**
+ * uclass_unbind_device() - Deassociate device with a uclass
+ *
+ * Disconnect the device from uclass's list of devices.
+ *
+ * @dev:	Pointer to the device
+ * #return 0 on success, -ve on error
+ */
+int uclass_unbind_device(struct device *dev);
+
+/**
+ * uclass_post_probe_device() - Deal with a device that has just been probed
+ *
+ * Perform any post-processing of a probed device that is needed by the
+ * uclass.
+ *
+ * @dev:	Pointer to the device
+ * #return 0 on success, -ve on error
+ */
+int uclass_post_probe_device(struct device *dev);
+
+/**
+ * uclass_pre_remove_device() - Handle a device which is about to be removed
+ *
+ * Perform any pre-processing of a device that is about to be removed.
+ *
+ * @dev:	Pointer to the device
+ * #return 0 on success, -ve on error
+ */
+int uclass_pre_remove_device(struct device *dev);
+
+/**
+ * uclass_find() - Find uclass by its id
+ *
+ * @id:		Id to serach for
+ * @return pointer to uclass, or NULL if not found
+ */
+struct uclass *uclass_find(enum uclass_id key);
+
+/**
+ * uclass_destroy() - Destroy a uclass
+ *
+ * Destroy a uclass and all its devices
+ *
+ * @uc: uclass to destroy
+ * @return 0 on success, -ve on error
+ */
+int uclass_destroy(struct uclass *uc);
+
+#endif
diff --git a/include/dm/uclass.h b/include/dm/uclass.h
new file mode 100644
index 0000000000..cd23cfed16
--- /dev/null
+++ b/include/dm/uclass.h
@@ -0,0 +1,142 @@
+/*
+ * Copyright (c) 2013 Google, Inc
+ *
+ * (C) Copyright 2012
+ * Pavel Herrmann <morpheus.ibis@gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _DM_UCLASS_H
+#define _DM_UCLASS_H
+
+#include <dm/uclass-id.h>
+#include <linux/list.h>
+
+/**
+ * struct uclass - a U-Boot drive class, collecting together similar drivers
+ *
+ * A uclass provides an interface to a particular function, which is
+ * implemented by one or more drivers. Every driver belongs to a uclass even
+ * if it is the only driver in that uclass. An example uclass is GPIO, which
+ * provides the ability to change read inputs, set and clear outputs, etc.
+ * There may be drivers for on-chip SoC GPIO banks, I2C GPIO expanders and
+ * PMIC IO lines, all made available in a unified way through the uclass.
+ *
+ * @priv: Private data for this uclass
+ * @uc_drv: The driver for the uclass itself, not to be confused with a
+ * 'struct driver'
+ * dev_head: List of devices in this uclass (devices are attached to their
+ * uclass when their bind method is called)
+ * @sibling_node: Next uclass in the linked list of uclasses
+ */
+struct uclass {
+	void *priv;
+	struct uclass_driver *uc_drv;
+	struct list_head dev_head;
+	struct list_head sibling_node;
+};
+
+struct device;
+
+/**
+ * struct uclass_driver - Driver for the uclass
+ *
+ * A uclass_driver provides a consistent interface to a set of related
+ * drivers.
+ *
+ * @name: Name of uclass driver
+ * @id: ID number of this uclass
+ * @post_bind: Called after a new device is bound to this uclass
+ * @pre_unbind: Called before a device is unbound from this uclass
+ * @post_probe: Called after a new device is probed
+ * @pre_remove: Called before a device is removed
+ * @init: Called to set up the uclass
+ * @destroy: Called to destroy the uclass
+ * @priv_auto_alloc_size: If non-zero this is the size of the private data
+ * to be allocated in the uclass's ->priv pointer. If zero, then the uclass
+ * driver is responsible for allocating any data required.
+ * @per_device_auto_alloc_size: Each device can hold private data owned
+ * by the uclass. If required this will be automatically allocated if this
+ * value is non-zero.
+ * @ops: Uclass operations, providing the consistent interface to devices
+ * within the uclass.
+ */
+struct uclass_driver {
+	const char *name;
+	enum uclass_id id;
+	int (*post_bind)(struct device *dev);
+	int (*pre_unbind)(struct device *dev);
+	int (*post_probe)(struct device *dev);
+	int (*pre_remove)(struct device *dev);
+	int (*init)(struct uclass *class);
+	int (*destroy)(struct uclass *class);
+	int priv_auto_alloc_size;
+	int per_device_auto_alloc_size;
+	const void *ops;
+};
+
+/* Declare a new uclass_driver */
+#define UCLASS_DRIVER(__name)						\
+	ll_entry_declare(struct uclass_driver, __name, uclass)
+
+/**
+ * uclass_get() - Get a uclass based on an ID, creating it if needed
+ *
+ * Every uclass is identified by an ID, a number from 0 to n-1 where n is
+ * the number of uclasses. This function allows looking up a uclass by its
+ * ID.
+ *
+ * @key: ID to look up
+ * @ucp: Returns pointer to uclass (there is only one per ID)
+ * @return 0 if OK, -ve on error
+ */
+int uclass_get(enum uclass_id key, struct uclass **ucp);
+
+/**
+ * uclass_get_device() - Get a uclass device based on an ID and index
+ *
+ * id: ID to look up
+ * @index: Device number within that uclass (0=first)
+ * @ucp: Returns pointer to uclass (there is only one per for each ID)
+ * @return 0 if OK, -ve on error
+ */
+int uclass_get_device(enum uclass_id id, int index, struct device **ucp);
+
+/**
+ * uclass_first_device() - Get the first device in a uclass
+ *
+ * @id: Uclass ID to look up
+ * @devp: Returns pointer to the first device in that uclass, or NULL if none
+ * @return 0 if OK (found or not found), -1 on error
+ */
+int uclass_first_device(enum uclass_id id, struct device **devp);
+
+/**
+ * uclass_next_device() - Get the next device in a uclass
+ *
+ * @devp: On entry, pointer to device to lookup. On exit, returns pointer
+ * to the next device in the same uclass, or NULL if none
+ * @return 0 if OK (found or not found), -1 on error
+ */
+int uclass_next_device(struct device **devp);
+
+/**
+ * uclass_foreach_dev() - Helper function to iteration through devices
+ *
+ * This creates a for() loop which works through the available devices in
+ * a uclass in order from start to end.
+ *
+ * @pos: struct device * to hold the current device. Set to NULL when there
+ * are no more devices.
+ * uc: uclass to scan
+ */
+#define uclass_foreach_dev(pos, uc)					\
+	for (pos = list_entry((&(uc)->dev_head)->next, typeof(*pos),	\
+			uclass_node);					\
+	     prefetch(pos->uclass_node.next),				\
+			&pos->uclass_node != (&(uc)->dev_head);		\
+	     pos = list_entry(pos->uclass_node.next, typeof(*pos),	\
+			uclass_node))
+
+#endif
diff --git a/include/dm/ut.h b/include/dm/ut.h
new file mode 100644
index 0000000000..fa9eac0226
--- /dev/null
+++ b/include/dm/ut.h
@@ -0,0 +1,95 @@
+/*
+ * Simple unit test library for driver model
+ *
+ * Copyright (c) 2013 Google, Inc
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __DM_UT_H
+#define __DM_UT_H
+
+struct dm_test_state;
+
+/**
+ * ut_fail() - Record failure of a unit test
+ *
+ * @dms: Test state
+ * @fname: Filename where the error occured
+ * @line: Line number where the error occured
+ * @func: Function name where the error occured
+ * @cond: The condition that failed
+ */
+void ut_fail(struct dm_test_state *dms, const char *fname, int line,
+	     const char *func, const char *cond);
+
+/**
+ * ut_failf() - Record failure of a unit test
+ *
+ * @dms: Test state
+ * @fname: Filename where the error occured
+ * @line: Line number where the error occured
+ * @func: Function name where the error occured
+ * @cond: The condition that failed
+ * @fmt: printf() format string for the error, followed by args
+ */
+void ut_failf(struct dm_test_state *dms, const char *fname, int line,
+	      const char *func, const char *cond, const char *fmt, ...)
+			__attribute__ ((format (__printf__, 6, 7)));
+
+
+/* Assert that a condition is non-zero */
+#define ut_assert(cond)							\
+	if (!(cond)) {							\
+		ut_fail(dms, __FILE__, __LINE__, __func__, #cond);	\
+		return -1;						\
+	}
+
+/* Assert that a condition is non-zero, with printf() string */
+#define ut_assertf(cond, fmt, args...)					\
+	if (!(cond)) {							\
+		ut_failf(dms, __FILE__, __LINE__, __func__, #cond,	\
+			 fmt, ##args);					\
+		return -1;						\
+	}
+
+/* Assert that two int expressions are equal */
+#define ut_asserteq(expr1, expr2) {					\
+	unsigned int val1 = (expr1), val2 = (expr2);			\
+									\
+	if (val1 != val2) {						\
+		ut_failf(dms, __FILE__, __LINE__, __func__,		\
+			 #expr1 " == " #expr2,				\
+			 "Expected %d, got %d", val1, val2);		\
+		return -1;						\
+	}								\
+}
+
+/* Assert that two string expressions are equal */
+#define ut_asserteq_str(expr1, expr2) {					\
+	const char *val1 = (expr1), *val2 = (expr2);			\
+									\
+	if (strcmp(val1, val2)) {					\
+		ut_failf(dms, __FILE__, __LINE__, __func__,		\
+			 #expr1 " = " #expr2,				\
+			 "Expected \"%s\", got \"%s\"", val1, val2);	\
+		return -1;						\
+	}								\
+}
+
+/* Assert that two pointers are equal */
+#define ut_asserteq_ptr(expr1, expr2) {					\
+	const void *val1 = (expr1), *val2 = (expr2);			\
+									\
+	if (val1 != val2) {						\
+		ut_failf(dms, __FILE__, __LINE__, __func__,		\
+			 #expr1 " = " #expr2,				\
+			 "Expected %p, got %p", val1, val2);		\
+		return -1;						\
+	}								\
+}
+
+/* Assert that an operation succeeds (returns 0) */
+#define ut_assertok(cond)	ut_asserteq(0, cond)
+
+#endif
diff --git a/include/dm/util.h b/include/dm/util.h
new file mode 100644
index 0000000000..8be64a921d
--- /dev/null
+++ b/include/dm/util.h
@@ -0,0 +1,29 @@
+/*
+ * Copyright (c) 2013 Google, Inc
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __DM_UTIL_H
+
+void dm_warn(const char *fmt, ...);
+
+#ifdef DEBUG
+void dm_dbg(const char *fmt, ...);
+#else
+static inline void dm_dbg(const char *fmt, ...)
+{
+}
+#endif
+
+struct list_head;
+
+/**
+ * list_count_items() - Count number of items in a list
+ *
+ * @param head:		Head of list
+ * @return number of items, or 0 if empty
+ */
+int list_count_items(struct list_head *head);
+
+#endif
diff --git a/include/dm9161.h b/include/dm9161.h
deleted file mode 100644
index bd85e4287e..0000000000
--- a/include/dm9161.h
+++ /dev/null
@@ -1,127 +0,0 @@
-/*
- * NOTE:	DAVICOM ethernet Physical layer
- *
- * Version:	@(#)DM9161.h	1.0.0	01/10/2001
- *
- * Authors:	ATMEL Rousset
- *
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-
-/* DAVICOM PHYSICAL LAYER TRANSCEIVER DM9161 */
-
-#define	DM9161_BMCR		0	/* Basic Mode Control Register */
-#define DM9161_BMSR		1	/* Basic Mode Status Register */
-#define DM9161_PHYID1		2	/* PHY Idendifier Register 1 */
-#define DM9161_PHYID2		3	/* PHY Idendifier Register 2 */
-#define DM9161_ANAR		4	/* Auto_Negotiation Advertisement Register  */
-#define DM9161_ANLPAR		5	/* Auto_negotiation Link Partner Ability Register */
-#define DM9161_ANER		6	/* Auto-negotiation Expansion Register  */
-#define DM9161_DSCR		16	/* Specified Configuration Register */
-#define DM9161_DSCSR		17	/* Specified Configuration and Status Register */
-#define DM9161_10BTCSR		18	/* 10BASE-T Configuration and Satus Register */
-#define DM9161_MDINTR		21	/* Specified Interrupt Register */
-#define DM9161_RECR		22	/* Specified Receive Error Counter Register */
-#define DM9161_DISCR		23	/* Specified Disconnect Counter Register */
-#define DM9161_RLSR		24	/* Hardware Reset Latch State Register */
-
-
-/* --Bit definitions: DM9161_BMCR */
-#define DM9161_RESET	         (1 << 15)	/* 1= Software Reset; 0=Normal Operation */
-#define DM9161_LOOPBACK	         (1 << 14)	/* 1=loopback Enabled; 0=Normal Operation */
-#define DM9161_SPEED_SELECT      (1 << 13)	/* 1=100Mbps; 0=10Mbps */
-#define DM9161_AUTONEG	         (1 << 12)
-#define DM9161_POWER_DOWN        (1 << 11)
-#define DM9161_ISOLATE           (1 << 10)
-#define DM9161_RESTART_AUTONEG   (1 << 9)
-#define DM9161_DUPLEX_MODE       (1 << 8)
-#define DM9161_COLLISION_TEST    (1 << 7)
-
-/*--Bit definitions: DM9161_BMSR */
-#define DM9161_100BASE_TX        (1 << 15)
-#define DM9161_100BASE_TX_FD     (1 << 14)
-#define DM9161_100BASE_TX_HD     (1 << 13)
-#define DM9161_10BASE_T_FD       (1 << 12)
-#define DM9161_10BASE_T_HD       (1 << 11)
-#define DM9161_MF_PREAMB_SUPPR   (1 << 6)
-#define DM9161_AUTONEG_COMP      (1 << 5)
-#define DM9161_REMOTE_FAULT      (1 << 4)
-#define DM9161_AUTONEG_ABILITY   (1 << 3)
-#define DM9161_LINK_STATUS       (1 << 2)
-#define DM9161_JABBER_DETECT     (1 << 1)
-#define DM9161_EXTEND_CAPAB      (1 << 0)
-
-/*--definitions: DM9161_PHYID1 */
-#define DM9161_PHYID1_OUI	 0x606E
-#define DM9161_LSB_MASK	         0x3F
-
-/*--Bit definitions: DM9161_ANAR, DM9161_ANLPAR */
-#define DM9161_NP               (1 << 15)
-#define DM9161_ACK              (1 << 14)
-#define DM9161_RF               (1 << 13)
-#define DM9161_FCS              (1 << 10)
-#define DM9161_T4               (1 << 9)
-#define DM9161_TX_FDX           (1 << 8)
-#define DM9161_TX_HDX           (1 << 7)
-#define DM9161_10_FDX           (1 << 6)
-#define DM9161_10_HDX           (1 << 5)
-#define DM9161_AN_IEEE_802_3	0x0001
-
-/*--Bit definitions: DM9161_ANER */
-#define DM9161_PDF              (1 << 4)
-#define DM9161_LP_NP_ABLE       (1 << 3)
-#define DM9161_NP_ABLE          (1 << 2)
-#define DM9161_PAGE_RX          (1 << 1)
-#define DM9161_LP_AN_ABLE       (1 << 0)
-
-/*--Bit definitions: DM9161_DSCR */
-#define DM9161_BP4B5B           (1 << 15)
-#define DM9161_BP_SCR           (1 << 14)
-#define DM9161_BP_ALIGN         (1 << 13)
-#define DM9161_BP_ADPOK         (1 << 12)
-#define DM9161_REPEATER         (1 << 11)
-#define DM9161_TX               (1 << 10)
-#define DM9161_RMII_ENABLE      (1 << 8)
-#define DM9161_F_LINK_100       (1 << 7)
-#define DM9161_SPLED_CTL        (1 << 6)
-#define DM9161_COLLED_CTL       (1 << 5)
-#define DM9161_RPDCTR_EN        (1 << 4)
-#define DM9161_SM_RST           (1 << 3)
-#define DM9161_MFP SC           (1 << 2)
-#define DM9161_SLEEP            (1 << 1)
-#define DM9161_RLOUT            (1 << 0)
-
-/*--Bit definitions: DM9161_DSCSR */
-#define DM9161_100FDX           (1 << 15)
-#define DM9161_100HDX           (1 << 14)
-#define DM9161_10FDX            (1 << 13)
-#define DM9161_10HDX            (1 << 12)
-
-/*--Bit definitions: DM9161_10BTCSR */
-#define DM9161_LP_EN           (1 << 14)
-#define DM9161_HBE             (1 << 13)
-#define DM9161_SQUELCH         (1 << 12)
-#define DM9161_JABEN           (1 << 11)
-#define DM9161_10BT_SER        (1 << 10)
-#define DM9161_POLR            (1 << 0)
-
-
-/*--Bit definitions: DM9161_MDINTR */
-#define DM9161_INTR_PEND       (1 << 15)
-#define DM9161_FDX_MASK        (1 << 11)
-#define DM9161_SPD_MASK        (1 << 10)
-#define DM9161_LINK_MASK       (1 << 9)
-#define DM9161_INTR_MASK       (1 << 8)
-#define DM9161_FDX_CHANGE      (1 << 4)
-#define DM9161_SPD_CHANGE      (1 << 3)
-#define DM9161_LINK_CHANGE     (1 << 2)
-#define DM9161_INTR_STATUS     (1 << 0)
-
-
-/******************  function prototypes **********************/
-unsigned int  dm9161_IsPhyConnected(AT91PS_EMAC p_mac);
-unsigned char dm9161_GetLinkSpeed(AT91PS_EMAC p_mac);
-unsigned char dm9161_AutoNegotiate(AT91PS_EMAC p_mac, int *status);
-unsigned char dm9161_InitPhy(AT91PS_EMAC p_mac);
diff --git a/include/dwmmc.h b/include/dwmmc.h
index 08ced0bf1f..c9bdf51a67 100644
--- a/include/dwmmc.h
+++ b/include/dwmmc.h
@@ -123,6 +123,9 @@
 #define DWMCI_BMOD_IDMAC_FB	(1 << 1)
 #define DWMCI_BMOD_IDMAC_EN	(1 << 7)
 
+/* quirks */
+#define DWMCI_QUIRK_DISABLE_SMU		(1 << 0)
+
 struct dwmci_host {
 	char *name;
 	void *ioaddr;
@@ -138,7 +141,10 @@ struct dwmci_host {
 	struct mmc *mmc;
 
 	void (*clksel)(struct dwmci_host *host);
-	unsigned int (*mmc_clk)(int dev_index);
+	void (*board_init)(struct dwmci_host *host);
+	unsigned int (*get_mmc_clk)(struct dwmci_host *host);
+
+	struct mmc_config cfg;
 };
 
 struct dwmci_idmac {
diff --git a/include/ec_commands.h b/include/ec_commands.h
index 12811cc070..78baab1641 100644
--- a/include/ec_commands.h
+++ b/include/ec_commands.h
@@ -1,4 +1,4 @@
-/* Copyright (c) 2012 The Chromium OS Authors. All rights reserved.
+/* Copyright (c) 2013 The Chromium OS Authors. All rights reserved.
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -42,13 +42,19 @@
 #define EC_LPC_ADDR_HOST_CMD   0x204
 
 /* I/O addresses for host command args and params */
-#define EC_LPC_ADDR_HOST_ARGS  0x800
-#define EC_LPC_ADDR_HOST_PARAM 0x804
-#define EC_HOST_PARAM_SIZE     0x0fc  /* Size of param area in bytes */
-
-/* I/O addresses for host command params, old interface */
-#define EC_LPC_ADDR_OLD_PARAM  0x880
-#define EC_OLD_PARAM_SIZE      0x080  /* Size of param area in bytes */
+/* Protocol version 2 */
+#define EC_LPC_ADDR_HOST_ARGS    0x800  /* And 0x801, 0x802, 0x803 */
+#define EC_LPC_ADDR_HOST_PARAM   0x804  /* For version 2 params; size is
+					 * EC_PROTO2_MAX_PARAM_SIZE */
+/* Protocol version 3 */
+#define EC_LPC_ADDR_HOST_PACKET  0x800  /* Offset of version 3 packet */
+#define EC_LPC_HOST_PACKET_SIZE  0x100  /* Max size of version 3 packet */
+
+/* The actual block is 0x800-0x8ff, but some BIOSes think it's 0x880-0x8ff
+ * and they tell the kernel that so we have to think of it as two parts. */
+#define EC_HOST_CMD_REGION0    0x800
+#define EC_HOST_CMD_REGION1    0x880
+#define EC_HOST_CMD_REGION_SIZE 0x80
 
 /* EC command register bit functions */
 #define EC_LPC_CMDR_DATA	(1 << 0)  /* Data ready for host to read */
@@ -122,8 +128,8 @@
 #define EC_SWITCH_LID_OPEN               0x01
 #define EC_SWITCH_POWER_BUTTON_PRESSED   0x02
 #define EC_SWITCH_WRITE_PROTECT_DISABLED 0x04
-/* Recovery requested via keyboard */
-#define EC_SWITCH_KEYBOARD_RECOVERY      0x08
+/* Was recovery requested via keyboard; now unused. */
+#define EC_SWITCH_IGNORE1		 0x08
 /* Recovery requested via dedicated signal (from servo board) */
 #define EC_SWITCH_DEDICATED_RECOVERY     0x10
 /* Was fake developer mode switch; now unused.  Remove in next refactor. */
@@ -132,10 +138,13 @@
 /* Host command interface flags */
 /* Host command interface supports LPC args (LPC interface only) */
 #define EC_HOST_CMD_FLAG_LPC_ARGS_SUPPORTED  0x01
+/* Host command interface supports version 3 protocol */
+#define EC_HOST_CMD_FLAG_VERSION_3   0x02
 
 /* Wireless switch flags */
 #define EC_WIRELESS_SWITCH_WLAN      0x01
 #define EC_WIRELESS_SWITCH_BLUETOOTH 0x02
+#define EC_WIRELESS_SWITCH_WWAN      0x04
 
 /*
  * This header file is used in coreboot both in C and ACPI code.  The ACPI code
@@ -191,6 +200,9 @@ enum ec_status {
 	EC_RES_UNAVAILABLE = 9,		/* No response available */
 	EC_RES_TIMEOUT = 10,		/* We got a timeout */
 	EC_RES_OVERFLOW = 11,		/* Table / data overflow */
+	EC_RES_INVALID_HEADER = 12,     /* Header contains invalid data */
+	EC_RES_REQUEST_TRUNCATED = 13,  /* Didn't get the entire request */
+	EC_RES_RESPONSE_TOO_BIG = 14    /* Response was too big to handle */
 };
 
 /*
@@ -272,6 +284,105 @@ struct ec_lpc_host_args {
  */
 #define EC_HOST_ARGS_FLAG_TO_HOST   0x02
 
+/*****************************************************************************/
+
+/*
+ * Protocol version 2 for I2C and SPI send a request this way:
+ *
+ *	0	EC_CMD_VERSION0 + (command version)
+ *	1	Command number
+ *	2	Length of params = N
+ *	3..N+2	Params, if any
+ *	N+3	8-bit checksum of bytes 0..N+2
+ *
+ * The corresponding response is:
+ *
+ *	0	Result code (EC_RES_*)
+ *	1	Length of params = M
+ *	2..M+1	Params, if any
+ *	M+2	8-bit checksum of bytes 0..M+1
+ */
+#define EC_PROTO2_REQUEST_HEADER_BYTES 3
+#define EC_PROTO2_REQUEST_TRAILER_BYTES 1
+#define EC_PROTO2_REQUEST_OVERHEAD (EC_PROTO2_REQUEST_HEADER_BYTES +	\
+				    EC_PROTO2_REQUEST_TRAILER_BYTES)
+
+#define EC_PROTO2_RESPONSE_HEADER_BYTES 2
+#define EC_PROTO2_RESPONSE_TRAILER_BYTES 1
+#define EC_PROTO2_RESPONSE_OVERHEAD (EC_PROTO2_RESPONSE_HEADER_BYTES +	\
+				     EC_PROTO2_RESPONSE_TRAILER_BYTES)
+
+/* Parameter length was limited by the LPC interface */
+#define EC_PROTO2_MAX_PARAM_SIZE 0xfc
+
+/* Maximum request and response packet sizes for protocol version 2 */
+#define EC_PROTO2_MAX_REQUEST_SIZE (EC_PROTO2_REQUEST_OVERHEAD +	\
+				    EC_PROTO2_MAX_PARAM_SIZE)
+#define EC_PROTO2_MAX_RESPONSE_SIZE (EC_PROTO2_RESPONSE_OVERHEAD +	\
+				     EC_PROTO2_MAX_PARAM_SIZE)
+
+/*****************************************************************************/
+
+/*
+ * Value written to legacy command port / prefix byte to indicate protocol
+ * 3+ structs are being used.  Usage is bus-dependent.
+ */
+#define EC_COMMAND_PROTOCOL_3 0xda
+
+#define EC_HOST_REQUEST_VERSION 3
+
+/* Version 3 request from host */
+struct ec_host_request {
+	/* Struct version (=3)
+	 *
+	 * EC will return EC_RES_INVALID_HEADER if it receives a header with a
+	 * version it doesn't know how to parse.
+	 */
+	uint8_t struct_version;
+
+	/*
+	 * Checksum of request and data; sum of all bytes including checksum
+	 * should total to 0.
+	 */
+	uint8_t checksum;
+
+	/* Command code */
+	uint16_t command;
+
+	/* Command version */
+	uint8_t command_version;
+
+	/* Unused byte in current protocol version; set to 0 */
+	uint8_t reserved;
+
+	/* Length of data which follows this header */
+	uint16_t data_len;
+} __packed;
+
+#define EC_HOST_RESPONSE_VERSION 3
+
+/* Version 3 response from EC */
+struct ec_host_response {
+	/* Struct version (=3) */
+	uint8_t struct_version;
+
+	/*
+	 * Checksum of response and data; sum of all bytes including checksum
+	 * should total to 0.
+	 */
+	uint8_t checksum;
+
+	/* Result code (EC_RES_*) */
+	uint16_t result;
+
+	/* Length of data which follows this header */
+	uint16_t data_len;
+
+	/* Unused bytes in current protocol version; set to 0 */
+	uint16_t reserved;
+} __packed;
+
+/*****************************************************************************/
 /*
  * Notes on commands:
  *
@@ -411,6 +522,46 @@ struct ec_response_get_comms_status {
 	uint32_t flags;		/* Mask of enum ec_comms_status */
 } __packed;
 
+/*
+ * Fake a variety of responses, purely for testing purposes.
+ * FIXME: Would be nice to force checksum errors.
+ */
+#define EC_CMD_TEST_PROTOCOL		0x0a
+
+/* Tell the EC what to send back to us. */
+struct ec_params_test_protocol {
+	uint32_t ec_result;
+	uint32_t ret_len;
+	uint8_t buf[32];
+} __packed;
+
+/* Here it comes... */
+struct ec_response_test_protocol {
+	uint8_t buf[32];
+} __packed;
+
+/* Get prococol information */
+#define EC_CMD_GET_PROTOCOL_INFO	0x0b
+
+/* Flags for ec_response_get_protocol_info.flags */
+/* EC_RES_IN_PROGRESS may be returned if a command is slow */
+#define EC_PROTOCOL_INFO_IN_PROGRESS_SUPPORTED (1 << 0)
+
+struct ec_response_get_protocol_info {
+	/* Fields which exist if at least protocol version 3 supported */
+
+	/* Bitmask of protocol versions supported (1 << n means version n)*/
+	uint32_t protocol_versions;
+
+	/* Maximum request packet size, in bytes */
+	uint16_t max_request_packet_size;
+
+	/* Maximum response packet size, in bytes */
+	uint16_t max_response_packet_size;
+
+	/* Flags; see EC_PROTOCOL_INFO_* */
+	uint32_t flags;
+} __packed;
 
 /*****************************************************************************/
 /* Flash commands */
@@ -452,15 +603,15 @@ struct ec_params_flash_read {
 
 /* Write flash */
 #define EC_CMD_FLASH_WRITE 0x12
+#define EC_VER_FLASH_WRITE 1
+
+/* Version 0 of the flash command supported only 64 bytes of data */
+#define EC_FLASH_WRITE_VER0_SIZE 64
 
 struct ec_params_flash_write {
 	uint32_t offset;   /* Byte offset to write */
 	uint32_t size;     /* Size to write in bytes */
-	/*
-	 * Data to write.  Could really use EC_PARAM_SIZE - 8, but tidiest to
-	 * use a power of 2 so writes stay aligned.
-	 */
-	uint8_t data[64];
+	/* Followed by data to write */
 } __packed;
 
 /* Erase flash */
@@ -536,7 +687,7 @@ struct ec_response_flash_protect {
 
 enum ec_flash_region {
 	/* Region which holds read-only EC image */
-	EC_FLASH_REGION_RO,
+	EC_FLASH_REGION_RO = 0,
 	/* Region which holds rewritable EC image */
 	EC_FLASH_REGION_RW,
 	/*
@@ -544,6 +695,8 @@ enum ec_flash_region {
 	 * EC_FLASH_REGION_RO)
 	 */
 	EC_FLASH_REGION_WP_RO,
+	/* Number of regions */
+	EC_FLASH_REGION_COUNT,
 };
 
 struct ec_params_flash_region_info {
@@ -727,6 +880,49 @@ enum lightbar_command {
 };
 
 /*****************************************************************************/
+/* LED control commands */
+
+#define EC_CMD_LED_CONTROL 0x29
+
+enum ec_led_id {
+	EC_LED_ID_BATTERY_LED = 0,
+	EC_LED_ID_POWER_BUTTON_LED,
+	EC_LED_ID_ADAPTER_LED,
+};
+
+/* LED control flags */
+#define EC_LED_FLAGS_QUERY (1 << 0) /* Query LED capability only */
+#define EC_LED_FLAGS_AUTO  (1 << 1) /* Switch LED back to automatic control */
+
+enum ec_led_colors {
+	EC_LED_COLOR_RED = 0,
+	EC_LED_COLOR_GREEN,
+	EC_LED_COLOR_BLUE,
+	EC_LED_COLOR_YELLOW,
+	EC_LED_COLOR_WHITE,
+
+	EC_LED_COLOR_COUNT
+};
+
+struct ec_params_led_control {
+	uint8_t led_id;     /* Which LED to control */
+	uint8_t flags;      /* Control flags */
+
+	uint8_t brightness[EC_LED_COLOR_COUNT];
+} __packed;
+
+struct ec_response_led_control {
+	/*
+	 * Available brightness value range.
+	 *
+	 * Range 0 means color channel not present.
+	 * Range 1 means on/off control.
+	 * Other values means the LED is control by PWM.
+	 */
+	uint8_t brightness_range[EC_LED_COLOR_COUNT];
+} __packed;
+
+/*****************************************************************************/
 /* Verified boot commands */
 
 /*
@@ -914,57 +1110,57 @@ struct ec_params_tmp006_set_calibration {
 } __packed;
 
 /*****************************************************************************/
-/* CROS_EC - Matrix KeyBoard Protocol */
+/* MKBP - Matrix KeyBoard Protocol */
 
 /*
  * Read key state
  *
- * Returns raw data for keyboard cols; see ec_response_cros_ec_info.cols for
+ * Returns raw data for keyboard cols; see ec_response_mkbp_info.cols for
  * expected response size.
  */
-#define EC_CMD_CROS_EC_STATE 0x60
+#define EC_CMD_MKBP_STATE 0x60
 
 /* Provide information about the matrix : number of rows and columns */
-#define EC_CMD_CROS_EC_INFO 0x61
+#define EC_CMD_MKBP_INFO 0x61
 
-struct ec_response_cros_ec_info {
+struct ec_response_mkbp_info {
 	uint32_t rows;
 	uint32_t cols;
 	uint8_t switches;
 } __packed;
 
 /* Simulate key press */
-#define EC_CMD_CROS_EC_SIMULATE_KEY 0x62
+#define EC_CMD_MKBP_SIMULATE_KEY 0x62
 
-struct ec_params_cros_ec_simulate_key {
+struct ec_params_mkbp_simulate_key {
 	uint8_t col;
 	uint8_t row;
 	uint8_t pressed;
 } __packed;
 
 /* Configure keyboard scanning */
-#define EC_CMD_CROS_EC_SET_CONFIG 0x64
-#define EC_CMD_CROS_EC_GET_CONFIG 0x65
+#define EC_CMD_MKBP_SET_CONFIG 0x64
+#define EC_CMD_MKBP_GET_CONFIG 0x65
 
 /* flags */
-enum cros_ec_config_flags {
-	EC_CROS_EC_FLAGS_ENABLE = 1,	/* Enable keyboard scanning */
+enum mkbp_config_flags {
+	EC_MKBP_FLAGS_ENABLE = 1,	/* Enable keyboard scanning */
 };
 
-enum cros_ec_config_valid {
-	EC_CROS_EC_VALID_SCAN_PERIOD		= 1 << 0,
-	EC_CROS_EC_VALID_POLL_TIMEOUT		= 1 << 1,
-	EC_CROS_EC_VALID_MIN_POST_SCAN_DELAY	= 1 << 3,
-	EC_CROS_EC_VALID_OUTPUT_SETTLE		= 1 << 4,
-	EC_CROS_EC_VALID_DEBOUNCE_DOWN		= 1 << 5,
-	EC_CROS_EC_VALID_DEBOUNCE_UP		= 1 << 6,
-	EC_CROS_EC_VALID_FIFO_MAX_DEPTH		= 1 << 7,
+enum mkbp_config_valid {
+	EC_MKBP_VALID_SCAN_PERIOD		= 1 << 0,
+	EC_MKBP_VALID_POLL_TIMEOUT		= 1 << 1,
+	EC_MKBP_VALID_MIN_POST_SCAN_DELAY	= 1 << 3,
+	EC_MKBP_VALID_OUTPUT_SETTLE		= 1 << 4,
+	EC_MKBP_VALID_DEBOUNCE_DOWN		= 1 << 5,
+	EC_MKBP_VALID_DEBOUNCE_UP		= 1 << 6,
+	EC_MKBP_VALID_FIFO_MAX_DEPTH		= 1 << 7,
 };
 
 /* Configuration for our key scanning algorithm */
-struct ec_cros_ec_config {
+struct ec_mkbp_config {
 	uint32_t valid_mask;		/* valid fields */
-	uint8_t flags;		/* some flags (enum cros_ec_config_flags) */
+	uint8_t flags;		/* some flags (enum mkbp_config_flags) */
 	uint8_t valid_flags;		/* which flags are valid */
 	uint16_t scan_period_us;	/* period between start of scans */
 	/* revert to interrupt mode after no activity for this long */
@@ -983,12 +1179,12 @@ struct ec_cros_ec_config {
 	uint8_t fifo_max_depth;
 } __packed;
 
-struct ec_params_cros_ec_set_config {
-	struct ec_cros_ec_config config;
+struct ec_params_mkbp_set_config {
+	struct ec_mkbp_config config;
 } __packed;
 
-struct ec_response_cros_ec_get_config {
-	struct ec_cros_ec_config config;
+struct ec_response_mkbp_get_config {
+	struct ec_mkbp_config config;
 } __packed;
 
 /* Run the key scan emulation */
@@ -1144,7 +1340,7 @@ struct ec_response_gpio_get {
 #define EC_CMD_I2C_READ 0x94
 
 struct ec_params_i2c_read {
-	uint16_t addr;
+	uint16_t addr; /* 8-bit address (7-bit shifted << 1) */
 	uint8_t read_size; /* Either 8 or 16. */
 	uint8_t port;
 	uint8_t offset;
@@ -1158,7 +1354,7 @@ struct ec_response_i2c_read {
 
 struct ec_params_i2c_write {
 	uint16_t data;
-	uint16_t addr;
+	uint16_t addr; /* 8-bit address (7-bit shifted << 1) */
 	uint8_t write_size; /* Either 8 or 16. */
 	uint8_t port;
 	uint8_t offset;
@@ -1242,6 +1438,61 @@ struct ec_response_ldo_get {
 } __packed;
 
 /*****************************************************************************/
+/* Power info. */
+
+/*
+ * Get power info.
+ */
+#define EC_CMD_POWER_INFO 0x9d
+
+struct ec_response_power_info {
+	uint32_t usb_dev_type;
+	uint16_t voltage_ac;
+	uint16_t voltage_system;
+	uint16_t current_system;
+	uint16_t usb_current_limit;
+} __packed;
+
+/*****************************************************************************/
+/* I2C passthru command */
+
+#define EC_CMD_I2C_PASSTHRU 0x9e
+
+/* Slave address is 10 (not 7) bit */
+#define EC_I2C_FLAG_10BIT	(1 << 16)
+
+/* Read data; if not present, message is a write */
+#define EC_I2C_FLAG_READ	(1 << 15)
+
+/* Mask for address */
+#define EC_I2C_ADDR_MASK	0x3ff
+
+#define EC_I2C_STATUS_NAK	(1 << 0) /* Transfer was not acknowledged */
+#define EC_I2C_STATUS_TIMEOUT	(1 << 1) /* Timeout during transfer */
+
+/* Any error */
+#define EC_I2C_STATUS_ERROR	(EC_I2C_STATUS_NAK | EC_I2C_STATUS_TIMEOUT)
+
+struct ec_params_i2c_passthru_msg {
+	uint16_t addr_flags;	/* I2C slave address (7 or 10 bits) and flags */
+	uint16_t len;		/* Number of bytes to read or write */
+} __packed;
+
+struct ec_params_i2c_passthru {
+	uint8_t port;		/* I2C port number */
+	uint8_t num_msgs;	/* Number of messages */
+	struct ec_params_i2c_passthru_msg msg[];
+	/* Data to write for all messages is concatenated here */
+} __packed;
+
+struct ec_response_i2c_passthru {
+	uint8_t i2c_status;	/* Status flags (EC_I2C_STATUS_...) */
+	uint8_t num_msgs;	/* Number of messages processed */
+	uint8_t data[];		/* Data read by messages concatenated here */
+} __packed;
+
+
+/*****************************************************************************/
 /* Temporary debug commands. TODO: remove this crosbug.com/p/13849 */
 
 /*
@@ -1257,7 +1508,16 @@ struct ec_response_ldo_get {
 #define EC_CMD_CHARGE_CURRENT_LIMIT 0xa1
 
 struct ec_params_current_limit {
-	uint32_t limit;
+	uint32_t limit; /* in mA */
+} __packed;
+
+/*
+ * Set maximum external power current.
+ */
+#define EC_CMD_EXT_POWER_CURRENT_LIMIT 0xa2
+
+struct ec_params_ext_power_current_limit {
+	uint32_t limit; /* in mA */
 } __packed;
 
 /*****************************************************************************/
diff --git a/include/ext4fs.h b/include/ext4fs.h
index 2429380396..aacb147de2 100644
--- a/include/ext4fs.h
+++ b/include/ext4fs.h
@@ -134,6 +134,7 @@ int ext4fs_read(char *buf, unsigned len);
 int ext4fs_mount(unsigned part_length);
 void ext4fs_close(void);
 int ext4fs_ls(const char *dirname);
+int ext4fs_exists(const char *filename);
 void ext4fs_free_node(struct ext2fs_node *node, struct ext2fs_node *currroot);
 int ext4fs_devread(lbaint_t sector, int byte_offset, int byte_len, char *buf);
 void ext4fs_set_blk_dev(block_dev_desc_t *rbdd, disk_partition_t *info);
diff --git a/include/fat.h b/include/fat.h
index 2c951e7d79..c8eb7ccd29 100644
--- a/include/fat.h
+++ b/include/fat.h
@@ -188,6 +188,7 @@ file_read_func		file_fat_read;
 int file_cd(const char *path);
 int file_fat_detectfs(void);
 int file_fat_ls(const char *dir);
+int fat_exists(const char *filename);
 long file_fat_read_at(const char *filename, unsigned long pos, void *buffer,
 		      unsigned long maxsize);
 long file_fat_read(const char *filename, void *buffer, unsigned long maxsize);
diff --git a/include/fdtdec.h b/include/fdtdec.h
index 6bf83bf7c1..3196cf6683 100644
--- a/include/fdtdec.h
+++ b/include/fdtdec.h
@@ -59,6 +59,7 @@ enum fdt_compat_id {
 	COMPAT_NVIDIA_TEGRA20_NAND,	/* Tegra2 NAND controller */
 	COMPAT_NVIDIA_TEGRA20_PWM,	/* Tegra 2 PWM controller */
 	COMPAT_NVIDIA_TEGRA20_DC,	/* Tegra 2 Display controller */
+	COMPAT_NVIDIA_TEGRA124_SDMMC,	/* Tegra124 SDMMC controller */
 	COMPAT_NVIDIA_TEGRA30_SDMMC,	/* Tegra30 SDMMC controller */
 	COMPAT_NVIDIA_TEGRA20_SDMMC,	/* Tegra20 SDMMC controller */
 	COMPAT_NVIDIA_TEGRA20_SFLASH,	/* Tegra 2 SPI flash controller */
@@ -73,11 +74,15 @@ enum fdt_compat_id {
 	COMPAT_GOOGLE_CROS_EC,		/* Google CROS_EC Protocol */
 	COMPAT_GOOGLE_CROS_EC_KEYB,	/* Google CROS_EC Keyboard */
 	COMPAT_SAMSUNG_EXYNOS_EHCI,	/* Exynos EHCI controller */
+	COMPAT_SAMSUNG_EXYNOS5_XHCI,	/* Exynos5 XHCI controller */
 	COMPAT_SAMSUNG_EXYNOS_USB_PHY,	/* Exynos phy controller for usb2.0 */
+	COMPAT_SAMSUNG_EXYNOS5_USB3_PHY,/* Exynos phy controller for usb3.0 */
 	COMPAT_SAMSUNG_EXYNOS_TMU,	/* Exynos TMU */
 	COMPAT_SAMSUNG_EXYNOS_FIMD,	/* Exynos Display controller */
+	COMPAT_SAMSUNG_EXYNOS_MIPI_DSI,	/* Exynos mipi dsi */
 	COMPAT_SAMSUNG_EXYNOS5_DP,	/* Exynos Display port controller */
 	COMPAT_SAMSUNG_EXYNOS5_DWMMC,	/* Exynos5 DWMMC controller */
+	COMPAT_SAMSUNG_EXYNOS_MMC,	/* Exynos MMC controller */
 	COMPAT_SAMSUNG_EXYNOS_SERIAL,	/* Exynos UART */
 	COMPAT_MAXIM_MAX77686_PMIC,	/* MAX77686 PMIC */
 	COMPAT_GENERIC_SPI_FLASH,	/* Generic SPI Flash chip */
@@ -85,6 +90,8 @@ enum fdt_compat_id {
 	COMPAT_INFINEON_SLB9635_TPM,	/* Infineon SLB9635 TPM */
 	COMPAT_INFINEON_SLB9645_TPM,	/* Infineon SLB9645 TPM */
 	COMPAT_SAMSUNG_EXYNOS5_I2C,	/* Exynos5 High Speed I2C Controller */
+	COMPAT_SANDBOX_HOST_EMULATION,	/* Sandbox emulation of a function */
+	COMPAT_SANDBOX_LCD_SDL,		/* Sandbox LCD emulation with SDL */
 
 	COMPAT_COUNT,
 };
@@ -527,4 +534,22 @@ const u8 *fdtdec_locate_byte_array(const void *blob, int node,
  */
 int fdtdec_decode_region(const void *blob, int node,
 		const char *prop_name, void **ptrp, size_t *size);
+
+/* A flash map entry, containing an offset and length */
+struct fmap_entry {
+	uint32_t offset;
+	uint32_t length;
+};
+
+/**
+ * Read a flash entry from the fdt
+ *
+ * @param blob		FDT blob
+ * @param node		Offset of node to read
+ * @param name		Name of node being read
+ * @param entry		Place to put offset and size of this node
+ * @return 0 if ok, -ve on error
+ */
+int fdtdec_read_fmap_entry(const void *blob, int node, const char *name,
+			   struct fmap_entry *entry);
 #endif
diff --git a/include/fm_eth.h b/include/fm_eth.h
index 90562dc9f0..98edfcf4ad 100644
--- a/include/fm_eth.h
+++ b/include/fm_eth.h
@@ -22,6 +22,8 @@ enum fm_port {
 	FM1_DTSEC10,
 	FM1_10GEC1,
 	FM1_10GEC2,
+	FM1_10GEC3,
+	FM1_10GEC4,
 	FM2_DTSEC1,
 	FM2_DTSEC2,
 	FM2_DTSEC3,
@@ -85,6 +87,22 @@ enum fm_eth_type {
 	.compat_offset	= CONFIG_SYS_FSL_FM##idx##_OFFSET +		\
 				offsetof(struct ccsr_fman, memac[n-1+8]),\
 }
+
+#if (CONFIG_SYS_NUM_FM1_10GEC >= 3)
+#define FM_TGEC_INFO_INITIALIZER2(idx, n) \
+{									\
+	FM_ETH_INFO_INITIALIZER(idx, CONFIG_SYS_FM1_TGEC_MDIO_ADDR)	\
+	.index		= idx,						\
+	.num		= n - 1,					\
+	.type		= FM_ETH_10G_E,					\
+	.port		= FM##idx##_10GEC##n,				\
+	.rx_port_id	= RX_PORT_10G_BASE2 + n - 3,			\
+	.tx_port_id	= TX_PORT_10G_BASE2 + n - 3,			\
+	.compat_offset	= CONFIG_SYS_FSL_FM##idx##_OFFSET +		\
+				offsetof(struct ccsr_fman, memac[n-1-2]),\
+}
+#endif
+
 #else
 #define FM_DTSEC_INFO_INITIALIZER(idx, n) \
 {									\
@@ -149,5 +167,10 @@ void fm_info_set_phy_address(enum fm_port port, int address);
 int fm_info_get_phy_address(enum fm_port port);
 void fm_info_set_mdio(enum fm_port port, struct mii_dev *bus);
 void fm_disable_port(enum fm_port port);
+void fm_enable_port(enum fm_port port);
+void set_sgmii_phy(struct mii_dev *bus, enum fm_port base_port,
+		unsigned int port_num, int phy_base_addr);
+int is_qsgmii_riser_card(struct mii_dev *bus, int phy_base_addr,
+		unsigned int port_num, unsigned regnum);
 
 #endif
diff --git a/include/fs.h b/include/fs.h
index 7d9403ed87..26de0539f7 100644
--- a/include/fs.h
+++ b/include/fs.h
@@ -44,6 +44,13 @@ int fs_set_blk_dev(const char *ifname, const char *dev_part_str, int fstype);
 int fs_ls(const char *dirname);
 
 /*
+ * Determine whether a file exists
+ *
+ * Returns 1 if the file exists, 0 if it doesn't exist.
+ */
+int fs_exists(const char *filename);
+
+/*
  * Read file "filename" from the partition previously set by fs_set_blk_dev(),
  * to address "addr", starting at byte offset "offset", and reading "len"
  * bytes. "offset" may be 0 to read from the start of the file. "len" may be
@@ -55,6 +62,16 @@ int fs_ls(const char *dirname);
 int fs_read(const char *filename, ulong addr, int offset, int len);
 
 /*
+ * Write file "filename" to the partition previously set by fs_set_blk_dev(),
+ * from address "addr", starting at byte offset "offset", and writing "len"
+ * bytes. "offset" may be 0 to write to the start of the file. Note that not
+ * all filesystem types support offset!=0.
+ *
+ * Returns number of bytes read on success. Returns <= 0 on error.
+ */
+int fs_write(const char *filename, ulong addr, int offset, int len);
+
+/*
  * Common implementation for various filesystem commands, optionally limited
  * to a specific filesystem type via the fstype parameter.
  */
@@ -62,6 +79,8 @@ int do_load(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[],
 		int fstype);
 int do_ls(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[],
 		int fstype);
+int file_exists(const char *dev_type, const char *dev_part, const char *file,
+		int fstype);
 int do_save(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[],
 		int fstype);
 
diff --git a/include/fsl_ddr.h b/include/fsl_ddr.h
new file mode 100644
index 0000000000..72c0b2e94e
--- /dev/null
+++ b/include/fsl_ddr.h
@@ -0,0 +1,114 @@
+/*
+ * Copyright 2008-2011 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * Version 2 as published by the Free Software Foundation.
+ */
+
+#ifndef FSL_DDR_MAIN_H
+#define FSL_DDR_MAIN_H
+
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr_dimm_params.h>
+
+#include <common_timing_params.h>
+
+#ifdef CONFIG_SYS_FSL_DDR_LE
+#define ddr_in32(a)	in_le32(a)
+#define ddr_out32(a, v)	out_le32(a, v)
+#else
+#define ddr_in32(a)	in_be32(a)
+#define ddr_out32(a, v)	out_be32(a, v)
+#endif
+
+#if defined(CONFIG_DDR_SPD) || defined(CONFIG_SPD_EEPROM)
+/*
+ * Bind the main DDR setup driver's generic names
+ * to this specific DDR technology.
+ */
+static __inline__ int
+compute_dimm_parameters(const generic_spd_eeprom_t *spd,
+			dimm_params_t *pdimm,
+			unsigned int dimm_number)
+{
+	return ddr_compute_dimm_parameters(spd, pdimm, dimm_number);
+}
+#endif
+
+/*
+ * Data Structures
+ *
+ * All data structures have to be on the stack
+ */
+#define CONFIG_SYS_NUM_DDR_CTLRS CONFIG_NUM_DDR_CONTROLLERS
+#define CONFIG_SYS_DIMM_SLOTS_PER_CTLR CONFIG_DIMM_SLOTS_PER_CTLR
+
+typedef struct {
+	generic_spd_eeprom_t
+	   spd_installed_dimms[CONFIG_SYS_NUM_DDR_CTLRS][CONFIG_SYS_DIMM_SLOTS_PER_CTLR];
+	struct dimm_params_s
+	   dimm_params[CONFIG_SYS_NUM_DDR_CTLRS][CONFIG_SYS_DIMM_SLOTS_PER_CTLR];
+	memctl_options_t memctl_opts[CONFIG_SYS_NUM_DDR_CTLRS];
+	common_timing_params_t common_timing_params[CONFIG_SYS_NUM_DDR_CTLRS];
+	fsl_ddr_cfg_regs_t fsl_ddr_config_reg[CONFIG_SYS_NUM_DDR_CTLRS];
+} fsl_ddr_info_t;
+
+/* Compute steps */
+#define STEP_GET_SPD                 (1 << 0)
+#define STEP_COMPUTE_DIMM_PARMS      (1 << 1)
+#define STEP_COMPUTE_COMMON_PARMS    (1 << 2)
+#define STEP_GATHER_OPTS             (1 << 3)
+#define STEP_ASSIGN_ADDRESSES        (1 << 4)
+#define STEP_COMPUTE_REGS            (1 << 5)
+#define STEP_PROGRAM_REGS            (1 << 6)
+#define STEP_ALL                     0xFFF
+
+unsigned long long
+fsl_ddr_compute(fsl_ddr_info_t *pinfo, unsigned int start_step,
+				       unsigned int size_only);
+
+const char *step_to_string(unsigned int step);
+
+unsigned int compute_fsl_memctl_config_regs(const memctl_options_t *popts,
+			       fsl_ddr_cfg_regs_t *ddr,
+			       const common_timing_params_t *common_dimm,
+			       const dimm_params_t *dimm_parameters,
+			       unsigned int dbw_capacity_adjust,
+			       unsigned int size_only);
+unsigned int compute_lowest_common_dimm_parameters(
+				const dimm_params_t *dimm_params,
+				common_timing_params_t *outpdimm,
+				unsigned int number_of_dimms);
+unsigned int populate_memctl_options(int all_dimms_registered,
+				memctl_options_t *popts,
+				dimm_params_t *pdimm,
+				unsigned int ctrl_num);
+void check_interleaving_options(fsl_ddr_info_t *pinfo);
+
+unsigned int mclk_to_picos(unsigned int mclk);
+unsigned int get_memory_clk_period_ps(void);
+unsigned int picos_to_mclk(unsigned int picos);
+void fsl_ddr_set_lawbar(
+		const common_timing_params_t *memctl_common_params,
+		unsigned int memctl_interleaved,
+		unsigned int ctrl_num);
+
+int fsl_ddr_interactive_env_var_exists(void);
+unsigned long long fsl_ddr_interactive(fsl_ddr_info_t *pinfo, int var_is_set);
+void fsl_ddr_get_spd(generic_spd_eeprom_t *ctrl_dimms_spd,
+			   unsigned int ctrl_num);
+
+int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]);
+unsigned int check_fsl_memctl_config_regs(const fsl_ddr_cfg_regs_t *ddr);
+void board_add_ram_info(int use_default);
+
+/* processor specific function */
+void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
+				   unsigned int ctrl_num, int step);
+
+/* board specific function */
+int fsl_ddr_get_dimm_params(dimm_params_t *pdimm,
+			unsigned int controller_number,
+			unsigned int dimm_number);
+#endif
diff --git a/include/fsl_ddr_dimm_params.h b/include/fsl_ddr_dimm_params.h
new file mode 100644
index 0000000000..99a72bc6e1
--- /dev/null
+++ b/include/fsl_ddr_dimm_params.h
@@ -0,0 +1,101 @@
+/*
+ * Copyright 2008 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * Version 2 as published by the Free Software Foundation.
+ */
+
+#ifndef DDR2_DIMM_PARAMS_H
+#define DDR2_DIMM_PARAMS_H
+
+#define EDC_DATA_PARITY	1
+#define EDC_ECC		2
+#define EDC_AC_PARITY	4
+
+/* Parameters for a DDR2 dimm computed from the SPD */
+typedef struct dimm_params_s {
+
+	/* DIMM organization parameters */
+	char mpart[19];		/* guaranteed null terminated */
+
+	unsigned int n_ranks;
+	unsigned long long rank_density;
+	unsigned long long capacity;
+	unsigned int data_width;
+	unsigned int primary_sdram_width;
+	unsigned int ec_sdram_width;
+	unsigned int registered_dimm;
+	unsigned int device_width;	/* x4, x8, x16 components */
+
+	/* SDRAM device parameters */
+	unsigned int n_row_addr;
+	unsigned int n_col_addr;
+	unsigned int edc_config;	/* 0 = none, 1 = parity, 2 = ECC */
+	unsigned int n_banks_per_sdram_device;
+	unsigned int burst_lengths_bitmask;	/* BL=4 bit 2, BL=8 = bit 3 */
+	unsigned int row_density;
+
+	/* used in computing base address of DIMMs */
+	unsigned long long base_address;
+	/* mirrored DIMMs */
+	unsigned int mirrored_dimm;	/* only for ddr3 */
+
+	/* DIMM timing parameters */
+
+	unsigned int mtb_ps;	/* medium timebase ps, only for ddr3 */
+	unsigned int ftb_10th_ps; /* fine timebase, in 1/10 ps, only for ddr3 */
+	unsigned int taa_ps;	/* minimum CAS latency time, only for ddr3 */
+	unsigned int tfaw_ps;	/* four active window delay, only for ddr3 */
+
+	/*
+	 * SDRAM clock periods
+	 * The range for these are 1000-10000 so a short should be sufficient
+	 */
+	unsigned int tckmin_x_ps;
+	unsigned int tckmin_x_minus_1_ps;
+	unsigned int tckmin_x_minus_2_ps;
+	unsigned int tckmax_ps;
+
+	/* SPD-defined CAS latencies */
+	unsigned int caslat_x;
+	unsigned int caslat_x_minus_1;
+	unsigned int caslat_x_minus_2;
+
+	unsigned int caslat_lowest_derated;	/* Derated CAS latency */
+
+	/* basic timing parameters */
+	unsigned int trcd_ps;
+	unsigned int trp_ps;
+	unsigned int tras_ps;
+
+	unsigned int twr_ps;	/* maximum = 63750 ps */
+	unsigned int twtr_ps;	/* maximum = 63750 ps */
+	unsigned int trfc_ps;   /* max = 255 ns + 256 ns + .75 ns
+				       = 511750 ps */
+
+	unsigned int trrd_ps;	/* maximum = 63750 ps */
+	unsigned int trc_ps;	/* maximum = 254 ns + .75 ns = 254750 ps */
+
+	unsigned int refresh_rate_ps;
+	unsigned int extended_op_srt;
+
+	/* DDR3 doesn't need these as below */
+	unsigned int tis_ps;	/* byte 32, spd->ca_setup */
+	unsigned int tih_ps;	/* byte 33, spd->ca_hold */
+	unsigned int tds_ps;	/* byte 34, spd->data_setup */
+	unsigned int tdh_ps;	/* byte 35, spd->data_hold */
+	unsigned int trtp_ps;	/* byte 38, spd->trtp */
+	unsigned int tdqsq_max_ps;	/* byte 44, spd->tdqsq */
+	unsigned int tqhs_ps;	/* byte 45, spd->tqhs */
+
+	/* DDR3 RDIMM */
+	unsigned char rcw[16];	/* Register Control Word 0-15 */
+} dimm_params_t;
+
+extern unsigned int ddr_compute_dimm_parameters(
+					 const generic_spd_eeprom_t *spd,
+					 dimm_params_t *pdimm,
+					 unsigned int dimm_number);
+
+#endif
diff --git a/include/fsl_ddr_sdram.h b/include/fsl_ddr_sdram.h
new file mode 100644
index 0000000000..2a36431146
--- /dev/null
+++ b/include/fsl_ddr_sdram.h
@@ -0,0 +1,378 @@
+/*
+ * Copyright 2008-2011 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * Version 2 as published by the Free Software Foundation.
+ */
+
+#ifndef FSL_DDR_MEMCTL_H
+#define FSL_DDR_MEMCTL_H
+
+/*
+ * Pick a basic DDR Technology.
+ */
+#include <ddr_spd.h>
+
+#define SDRAM_TYPE_DDR1    2
+#define SDRAM_TYPE_DDR2    3
+#define SDRAM_TYPE_LPDDR1  6
+#define SDRAM_TYPE_DDR3    7
+
+#define DDR_BL4		4	/* burst length 4 */
+#define DDR_BC4		DDR_BL4	/* burst chop for ddr3 */
+#define DDR_OTF		6	/* on-the-fly BC4 and BL8 */
+#define DDR_BL8		8	/* burst length 8 */
+
+#define DDR3_RTT_OFF		0
+#define DDR3_RTT_60_OHM		1 /* RTT_Nom = RZQ/4 */
+#define DDR3_RTT_120_OHM	2 /* RTT_Nom = RZQ/2 */
+#define DDR3_RTT_40_OHM		3 /* RTT_Nom = RZQ/6 */
+#define DDR3_RTT_20_OHM		4 /* RTT_Nom = RZQ/12 */
+#define DDR3_RTT_30_OHM		5 /* RTT_Nom = RZQ/8 */
+
+#define DDR2_RTT_OFF		0
+#define DDR2_RTT_75_OHM		1
+#define DDR2_RTT_150_OHM	2
+#define DDR2_RTT_50_OHM		3
+
+#if defined(CONFIG_SYS_FSL_DDR1)
+#define FSL_DDR_MIN_TCKE_PULSE_WIDTH_DDR	(1)
+typedef ddr1_spd_eeprom_t generic_spd_eeprom_t;
+#ifndef CONFIG_FSL_SDRAM_TYPE
+#define CONFIG_FSL_SDRAM_TYPE	SDRAM_TYPE_DDR1
+#endif
+#elif defined(CONFIG_SYS_FSL_DDR2)
+#define FSL_DDR_MIN_TCKE_PULSE_WIDTH_DDR	(3)
+typedef ddr2_spd_eeprom_t generic_spd_eeprom_t;
+#ifndef CONFIG_FSL_SDRAM_TYPE
+#define CONFIG_FSL_SDRAM_TYPE	SDRAM_TYPE_DDR2
+#endif
+#elif defined(CONFIG_SYS_FSL_DDR3)
+#define FSL_DDR_MIN_TCKE_PULSE_WIDTH_DDR	(3)	/* FIXME */
+typedef ddr3_spd_eeprom_t generic_spd_eeprom_t;
+#ifndef CONFIG_FSL_SDRAM_TYPE
+#define CONFIG_FSL_SDRAM_TYPE	SDRAM_TYPE_DDR3
+#endif
+#endif	/* #if defined(CONFIG_SYS_FSL_DDR1) */
+
+#define FSL_DDR_ODT_NEVER		0x0
+#define FSL_DDR_ODT_CS			0x1
+#define FSL_DDR_ODT_ALL_OTHER_CS	0x2
+#define FSL_DDR_ODT_OTHER_DIMM		0x3
+#define FSL_DDR_ODT_ALL			0x4
+#define FSL_DDR_ODT_SAME_DIMM		0x5
+#define FSL_DDR_ODT_CS_AND_OTHER_DIMM	0x6
+#define FSL_DDR_ODT_OTHER_CS_ONSAMEDIMM	0x7
+
+/* define bank(chip select) interleaving mode */
+#define FSL_DDR_CS0_CS1			0x40
+#define FSL_DDR_CS2_CS3			0x20
+#define FSL_DDR_CS0_CS1_AND_CS2_CS3	(FSL_DDR_CS0_CS1 | FSL_DDR_CS2_CS3)
+#define FSL_DDR_CS0_CS1_CS2_CS3		(FSL_DDR_CS0_CS1_AND_CS2_CS3 | 0x04)
+
+/* define memory controller interleaving mode */
+#define FSL_DDR_CACHE_LINE_INTERLEAVING	0x0
+#define FSL_DDR_PAGE_INTERLEAVING	0x1
+#define FSL_DDR_BANK_INTERLEAVING	0x2
+#define FSL_DDR_SUPERBANK_INTERLEAVING	0x3
+#define FSL_DDR_256B_INTERLEAVING	0x8
+#define FSL_DDR_3WAY_1KB_INTERLEAVING	0xA
+#define FSL_DDR_3WAY_4KB_INTERLEAVING	0xC
+#define FSL_DDR_3WAY_8KB_INTERLEAVING	0xD
+/* placeholder for 4-way interleaving */
+#define FSL_DDR_4WAY_1KB_INTERLEAVING	0x1A
+#define FSL_DDR_4WAY_4KB_INTERLEAVING	0x1C
+#define FSL_DDR_4WAY_8KB_INTERLEAVING	0x1D
+
+#define SDRAM_CS_CONFIG_EN		0x80000000
+
+/* DDR_SDRAM_CFG - DDR SDRAM Control Configuration
+ */
+#define SDRAM_CFG_MEM_EN		0x80000000
+#define SDRAM_CFG_SREN			0x40000000
+#define SDRAM_CFG_ECC_EN		0x20000000
+#define SDRAM_CFG_RD_EN			0x10000000
+#define SDRAM_CFG_SDRAM_TYPE_DDR1	0x02000000
+#define SDRAM_CFG_SDRAM_TYPE_DDR2	0x03000000
+#define SDRAM_CFG_SDRAM_TYPE_MASK	0x07000000
+#define SDRAM_CFG_SDRAM_TYPE_SHIFT	24
+#define SDRAM_CFG_DYN_PWR		0x00200000
+#define SDRAM_CFG_DBW_MASK		0x00180000
+#define SDRAM_CFG_DBW_SHIFT		19
+#define SDRAM_CFG_32_BE			0x00080000
+#define SDRAM_CFG_16_BE			0x00100000
+#define SDRAM_CFG_8_BE			0x00040000
+#define SDRAM_CFG_NCAP			0x00020000
+#define SDRAM_CFG_2T_EN			0x00008000
+#define SDRAM_CFG_BI			0x00000001
+
+#define SDRAM_CFG2_D_INIT		0x00000010
+#define SDRAM_CFG2_ODT_CFG_MASK		0x00600000
+#define SDRAM_CFG2_ODT_NEVER		0
+#define SDRAM_CFG2_ODT_ONLY_WRITE	1
+#define SDRAM_CFG2_ODT_ONLY_READ	2
+#define SDRAM_CFG2_ODT_ALWAYS		3
+
+#define TIMING_CFG_2_CPO_MASK	0x0F800000
+
+#if defined(CONFIG_P4080)
+#define RD_TO_PRE_MASK		0xf
+#define RD_TO_PRE_SHIFT		13
+#define WR_DATA_DELAY_MASK	0xf
+#define WR_DATA_DELAY_SHIFT	9
+#else
+#define RD_TO_PRE_MASK		0x7
+#define RD_TO_PRE_SHIFT		13
+#define WR_DATA_DELAY_MASK	0x7
+#define WR_DATA_DELAY_SHIFT	10
+#endif
+
+/* DDR_MD_CNTL */
+#define MD_CNTL_MD_EN		0x80000000
+#define MD_CNTL_CS_SEL_CS0	0x00000000
+#define MD_CNTL_CS_SEL_CS1	0x10000000
+#define MD_CNTL_CS_SEL_CS2	0x20000000
+#define MD_CNTL_CS_SEL_CS3	0x30000000
+#define MD_CNTL_CS_SEL_CS0_CS1	0x40000000
+#define MD_CNTL_CS_SEL_CS2_CS3	0x50000000
+#define MD_CNTL_MD_SEL_MR	0x00000000
+#define MD_CNTL_MD_SEL_EMR	0x01000000
+#define MD_CNTL_MD_SEL_EMR2	0x02000000
+#define MD_CNTL_MD_SEL_EMR3	0x03000000
+#define MD_CNTL_SET_REF		0x00800000
+#define MD_CNTL_SET_PRE		0x00400000
+#define MD_CNTL_CKE_CNTL_LOW	0x00100000
+#define MD_CNTL_CKE_CNTL_HIGH	0x00200000
+#define MD_CNTL_WRCW		0x00080000
+#define MD_CNTL_MD_VALUE(x)	(x & 0x0000FFFF)
+
+/* DDR_CDR1 */
+#define DDR_CDR1_DHC_EN	0x80000000
+#define DDR_CDR1_ODT_SHIFT	17
+#define DDR_CDR1_ODT_MASK	0x6
+#define DDR_CDR2_ODT_MASK	0x1
+#define DDR_CDR1_ODT(x) ((x & DDR_CDR1_ODT_MASK) << DDR_CDR1_ODT_SHIFT)
+#define DDR_CDR2_ODT(x) (x & DDR_CDR2_ODT_MASK)
+
+#if (defined(CONFIG_SYS_FSL_DDR_VER) && \
+	(CONFIG_SYS_FSL_DDR_VER >= FSL_DDR_VER_4_7))
+#define DDR_CDR_ODT_OFF		0x0
+#define DDR_CDR_ODT_120ohm	0x1
+#define DDR_CDR_ODT_180ohm	0x2
+#define DDR_CDR_ODT_75ohm	0x3
+#define DDR_CDR_ODT_110ohm	0x4
+#define DDR_CDR_ODT_60hm	0x5
+#define DDR_CDR_ODT_70ohm	0x6
+#define DDR_CDR_ODT_47ohm	0x7
+#else
+#define DDR_CDR_ODT_75ohm	0x0
+#define DDR_CDR_ODT_55ohm	0x1
+#define DDR_CDR_ODT_60ohm	0x2
+#define DDR_CDR_ODT_50ohm	0x3
+#define DDR_CDR_ODT_150ohm	0x4
+#define DDR_CDR_ODT_43ohm	0x5
+#define DDR_CDR_ODT_120ohm	0x6
+#endif
+
+/* Record of register values computed */
+typedef struct fsl_ddr_cfg_regs_s {
+	struct {
+		unsigned int bnds;
+		unsigned int config;
+		unsigned int config_2;
+	} cs[CONFIG_CHIP_SELECTS_PER_CTRL];
+	unsigned int timing_cfg_3;
+	unsigned int timing_cfg_0;
+	unsigned int timing_cfg_1;
+	unsigned int timing_cfg_2;
+	unsigned int ddr_sdram_cfg;
+	unsigned int ddr_sdram_cfg_2;
+	unsigned int ddr_sdram_mode;
+	unsigned int ddr_sdram_mode_2;
+	unsigned int ddr_sdram_mode_3;
+	unsigned int ddr_sdram_mode_4;
+	unsigned int ddr_sdram_mode_5;
+	unsigned int ddr_sdram_mode_6;
+	unsigned int ddr_sdram_mode_7;
+	unsigned int ddr_sdram_mode_8;
+	unsigned int ddr_sdram_md_cntl;
+	unsigned int ddr_sdram_interval;
+	unsigned int ddr_data_init;
+	unsigned int ddr_sdram_clk_cntl;
+	unsigned int ddr_init_addr;
+	unsigned int ddr_init_ext_addr;
+	unsigned int timing_cfg_4;
+	unsigned int timing_cfg_5;
+	unsigned int ddr_zq_cntl;
+	unsigned int ddr_wrlvl_cntl;
+	unsigned int ddr_wrlvl_cntl_2;
+	unsigned int ddr_wrlvl_cntl_3;
+	unsigned int ddr_sr_cntr;
+	unsigned int ddr_sdram_rcw_1;
+	unsigned int ddr_sdram_rcw_2;
+	unsigned int ddr_eor;
+	unsigned int ddr_cdr1;
+	unsigned int ddr_cdr2;
+	unsigned int err_disable;
+	unsigned int err_int_en;
+	unsigned int debug[32];
+} fsl_ddr_cfg_regs_t;
+
+typedef struct memctl_options_partial_s {
+	unsigned int all_dimms_ecc_capable;
+	unsigned int all_dimms_tckmax_ps;
+	unsigned int all_dimms_burst_lengths_bitmask;
+	unsigned int all_dimms_registered;
+	unsigned int all_dimms_unbuffered;
+	/*	unsigned int lowest_common_SPD_caslat; */
+	unsigned int all_dimms_minimum_trcd_ps;
+} memctl_options_partial_t;
+
+#define DDR_DATA_BUS_WIDTH_64 0
+#define DDR_DATA_BUS_WIDTH_32 1
+#define DDR_DATA_BUS_WIDTH_16 2
+/*
+ * Generalized parameters for memory controller configuration,
+ * might be a little specific to the FSL memory controller
+ */
+typedef struct memctl_options_s {
+	/*
+	 * Memory organization parameters
+	 *
+	 * if DIMM is present in the system
+	 * where DIMMs are with respect to chip select
+	 * where chip selects are with respect to memory boundaries
+	 */
+	unsigned int registered_dimm_en;    /* use registered DIMM support */
+
+	/* Options local to a Chip Select */
+	struct cs_local_opts_s {
+		unsigned int auto_precharge;
+		unsigned int odt_rd_cfg;
+		unsigned int odt_wr_cfg;
+		unsigned int odt_rtt_norm;
+		unsigned int odt_rtt_wr;
+	} cs_local_opts[CONFIG_CHIP_SELECTS_PER_CTRL];
+
+	/* Special configurations for chip select */
+	unsigned int memctl_interleaving;
+	unsigned int memctl_interleaving_mode;
+	unsigned int ba_intlv_ctl;
+	unsigned int addr_hash;
+
+	/* Operational mode parameters */
+	unsigned int ecc_mode;	 /* Use ECC? */
+	/* Initialize ECC using memory controller? */
+	unsigned int ecc_init_using_memctl;
+	unsigned int dqs_config;	/* Use DQS? maybe only with DDR2? */
+	/* SREN - self-refresh during sleep */
+	unsigned int self_refresh_in_sleep;
+	unsigned int dynamic_power;	/* DYN_PWR */
+	/* memory data width to use (16-bit, 32-bit, 64-bit) */
+	unsigned int data_bus_width;
+	unsigned int burst_length;	/* BL4, OTF and BL8 */
+	/* On-The-Fly Burst Chop enable */
+	unsigned int otf_burst_chop_en;
+	/* mirrior DIMMs for DDR3 */
+	unsigned int mirrored_dimm;
+	unsigned int quad_rank_present;
+	unsigned int ap_en;	/* address parity enable for RDIMM */
+	unsigned int x4_en;	/* enable x4 devices */
+
+	/* Global Timing Parameters */
+	unsigned int cas_latency_override;
+	unsigned int cas_latency_override_value;
+	unsigned int use_derated_caslat;
+	unsigned int additive_latency_override;
+	unsigned int additive_latency_override_value;
+
+	unsigned int clk_adjust;		/* */
+	unsigned int cpo_override;
+	unsigned int write_data_delay;		/* DQS adjust */
+
+	unsigned int wrlvl_override;
+	unsigned int wrlvl_sample;		/* Write leveling */
+	unsigned int wrlvl_start;
+	unsigned int wrlvl_ctl_2;
+	unsigned int wrlvl_ctl_3;
+
+	unsigned int half_strength_driver_enable;
+	unsigned int twot_en;
+	unsigned int threet_en;
+	unsigned int bstopre;
+	unsigned int tcke_clock_pulse_width_ps;	/* tCKE */
+	unsigned int tfaw_window_four_activates_ps;	/* tFAW --  FOUR_ACT */
+
+	/* Rtt impedance */
+	unsigned int rtt_override;		/* rtt_override enable */
+	unsigned int rtt_override_value;	/* that is Rtt_Nom for DDR3 */
+	unsigned int rtt_wr_override_value;	/* this is Rtt_WR for DDR3 */
+
+	/* Automatic self refresh */
+	unsigned int auto_self_refresh_en;
+	unsigned int sr_it;
+	/* ZQ calibration */
+	unsigned int zq_en;
+	/* Write leveling */
+	unsigned int wrlvl_en;
+	/* RCW override for RDIMM */
+	unsigned int rcw_override;
+	unsigned int rcw_1;
+	unsigned int rcw_2;
+	/* control register 1 */
+	unsigned int ddr_cdr1;
+	unsigned int ddr_cdr2;
+
+	unsigned int trwt_override;
+	unsigned int trwt;			/* read-to-write turnaround */
+} memctl_options_t;
+
+extern phys_size_t fsl_ddr_sdram(void);
+extern phys_size_t fsl_ddr_sdram_size(void);
+extern int fsl_use_spd(void);
+extern void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
+					unsigned int ctrl_num, int step);
+u32 fsl_ddr_get_intl3r(void);
+
+static void __board_assert_mem_reset(void)
+{
+}
+
+static void __board_deassert_mem_reset(void)
+{
+}
+
+void board_assert_mem_reset(void)
+	__attribute__((weak, alias("__board_assert_mem_reset")));
+
+void board_deassert_mem_reset(void)
+	__attribute__((weak, alias("__board_deassert_mem_reset")));
+
+static int __board_need_mem_reset(void)
+{
+	return 0;
+}
+
+int board_need_mem_reset(void)
+	__attribute__((weak, alias("__board_need_mem_reset")));
+
+/*
+ * The 85xx boards have a common prototype for fixed_sdram so put the
+ * declaration here.
+ */
+#ifdef CONFIG_MPC85xx
+extern phys_size_t fixed_sdram(void);
+#endif
+
+#if defined(CONFIG_DDR_ECC)
+extern void ddr_enable_ecc(unsigned int dram_size);
+#endif
+
+
+typedef struct fixed_ddr_parm{
+	int min_freq;
+	int max_freq;
+	fsl_ddr_cfg_regs_t *ddr_settings;
+} fixed_ddr_parm_t;
+#endif
diff --git a/include/fsl_esdhc.h b/include/fsl_esdhc.h
index 89bcbd1700..a6e3a5dc9a 100644
--- a/include/fsl_esdhc.h
+++ b/include/fsl_esdhc.h
@@ -13,6 +13,9 @@
 #include <asm/errno.h>
 #include <asm/byteorder.h>
 
+/* needed for the mmc_cfg definition */
+#include <mmc.h>
+
 /* FSL eSDHC-specific constants */
 #define SYSCTL			0x0002e02c
 #define SYSCTL_INITA		0x08000000
@@ -155,6 +158,7 @@ struct fsl_esdhc_cfg {
 	u32	esdhc_base;
 	u32	sdhc_clk;
 	u8	max_bus_width;
+	struct mmc_config cfg;
 };
 
 /* Select the correct accessors depending on endianess */
diff --git a/include/fsl_ifc.h b/include/fsl_ifc.h
new file mode 100644
index 0000000000..58a6efdfe0
--- /dev/null
+++ b/include/fsl_ifc.h
@@ -0,0 +1,1004 @@
+/*
+ * Copyright 2010-2011 Freescale Semiconductor, Inc.
+ * Author: Dipen Dudhat <dipen.dudhat@freescale.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __FSL_IFC_H
+#define __FSL_IFC_H
+
+#ifdef CONFIG_FSL_IFC
+#include <config.h>
+#include <common.h>
+
+
+#ifdef CONFIG_SYS_FSL_IFC_LE
+#define ifc_in32(a)       in_le32(a)
+#define ifc_out32(a, v)   out_le32(a, v)
+#define ifc_in16(a)       in_le16(a)
+#elif defined(CONFIG_SYS_FSL_IFC_BE)
+#define ifc_in32(a)       in_be32(a)
+#define ifc_out32(a, v)   out_be32(a, v)
+#define ifc_in16(a)       in_be16(a)
+#else
+#error Neither CONFIG_SYS_FSL_IFC_LE nor CONFIG_SYS_FSL_IFC_BE is defined
+#endif
+
+
+/*
+ * CSPR - Chip Select Property Register
+ */
+#define CSPR_BA				0xFFFF0000
+#define CSPR_BA_SHIFT			16
+#define CSPR_PORT_SIZE			0x00000180
+#define CSPR_PORT_SIZE_SHIFT		7
+/* Port Size 8 bit */
+#define CSPR_PORT_SIZE_8		0x00000080
+/* Port Size 16 bit */
+#define CSPR_PORT_SIZE_16		0x00000100
+/* Port Size 32 bit */
+#define CSPR_PORT_SIZE_32		0x00000180
+/* Write Protect */
+#define CSPR_WP				0x00000040
+#define CSPR_WP_SHIFT			6
+/* Machine Select */
+#define CSPR_MSEL			0x00000006
+#define CSPR_MSEL_SHIFT			1
+/* NOR */
+#define CSPR_MSEL_NOR			0x00000000
+/* NAND */
+#define CSPR_MSEL_NAND			0x00000002
+/* GPCM */
+#define CSPR_MSEL_GPCM			0x00000004
+/* Bank Valid */
+#define CSPR_V				0x00000001
+#define CSPR_V_SHIFT			0
+
+/* Convert an address into the right format for the CSPR Registers */
+#define CSPR_PHYS_ADDR(x)		(((uint64_t)x) & 0xffff0000)
+
+/*
+ * Address Mask Register
+ */
+#define IFC_AMASK_MASK			0xFFFF0000
+#define IFC_AMASK_SHIFT			16
+#define IFC_AMASK(n)			(IFC_AMASK_MASK << \
+					(__ilog2(n) - IFC_AMASK_SHIFT))
+
+/*
+ * Chip Select Option Register IFC_NAND Machine
+ */
+/* Enable ECC Encoder */
+#define CSOR_NAND_ECC_ENC_EN		0x80000000
+#define CSOR_NAND_ECC_MODE_MASK		0x30000000
+/* 4 bit correction per 520 Byte sector */
+#define CSOR_NAND_ECC_MODE_4		0x00000000
+/* 8 bit correction per 528 Byte sector */
+#define CSOR_NAND_ECC_MODE_8		0x10000000
+/* Enable ECC Decoder */
+#define CSOR_NAND_ECC_DEC_EN		0x04000000
+/* Row Address Length */
+#define CSOR_NAND_RAL_MASK		0x01800000
+#define CSOR_NAND_RAL_SHIFT		20
+#define CSOR_NAND_RAL_1			0x00000000
+#define CSOR_NAND_RAL_2			0x00800000
+#define CSOR_NAND_RAL_3			0x01000000
+#define CSOR_NAND_RAL_4			0x01800000
+/* Page Size 512b, 2k, 4k */
+#define CSOR_NAND_PGS_MASK		0x00180000
+#define CSOR_NAND_PGS_SHIFT		16
+#define CSOR_NAND_PGS_512		0x00000000
+#define CSOR_NAND_PGS_2K		0x00080000
+#define CSOR_NAND_PGS_4K		0x00100000
+#define CSOR_NAND_PGS_8K		0x00180000
+/* Spare region Size */
+#define CSOR_NAND_SPRZ_MASK		0x0000E000
+#define CSOR_NAND_SPRZ_SHIFT		13
+#define CSOR_NAND_SPRZ_16		0x00000000
+#define CSOR_NAND_SPRZ_64		0x00002000
+#define CSOR_NAND_SPRZ_128		0x00004000
+#define CSOR_NAND_SPRZ_210		0x00006000
+#define CSOR_NAND_SPRZ_218		0x00008000
+#define CSOR_NAND_SPRZ_224		0x0000A000
+#define CSOR_NAND_SPRZ_CSOR_EXT	0x0000C000
+/* Pages Per Block */
+#define CSOR_NAND_PB_MASK		0x00000700
+#define CSOR_NAND_PB_SHIFT		8
+#define CSOR_NAND_PB(n)		((__ilog2(n) - 5) << CSOR_NAND_PB_SHIFT)
+/* Time for Read Enable High to Output High Impedance */
+#define CSOR_NAND_TRHZ_MASK		0x0000001C
+#define CSOR_NAND_TRHZ_SHIFT		2
+#define CSOR_NAND_TRHZ_20		0x00000000
+#define CSOR_NAND_TRHZ_40		0x00000004
+#define CSOR_NAND_TRHZ_60		0x00000008
+#define CSOR_NAND_TRHZ_80		0x0000000C
+#define CSOR_NAND_TRHZ_100		0x00000010
+/* Buffer control disable */
+#define CSOR_NAND_BCTLD			0x00000001
+
+/*
+ * Chip Select Option Register - NOR Flash Mode
+ */
+/* Enable Address shift Mode */
+#define CSOR_NOR_ADM_SHFT_MODE_EN	0x80000000
+/* Page Read Enable from NOR device */
+#define CSOR_NOR_PGRD_EN		0x10000000
+/* AVD Toggle Enable during Burst Program */
+#define CSOR_NOR_AVD_TGL_PGM_EN		0x01000000
+/* Address Data Multiplexing Shift */
+#define CSOR_NOR_ADM_MASK		0x0003E000
+#define CSOR_NOR_ADM_SHIFT_SHIFT	13
+#define CSOR_NOR_ADM_SHIFT(n)	((n) << CSOR_NOR_ADM_SHIFT_SHIFT)
+/* Type of the NOR device hooked */
+#define CSOR_NOR_NOR_MODE_AYSNC_NOR	0x00000000
+#define CSOR_NOR_NOR_MODE_AVD_NOR	0x00000020
+/* Time for Read Enable High to Output High Impedance */
+#define CSOR_NOR_TRHZ_MASK		0x0000001C
+#define CSOR_NOR_TRHZ_SHIFT		2
+#define CSOR_NOR_TRHZ_20		0x00000000
+#define CSOR_NOR_TRHZ_40		0x00000004
+#define CSOR_NOR_TRHZ_60		0x00000008
+#define CSOR_NOR_TRHZ_80		0x0000000C
+#define CSOR_NOR_TRHZ_100		0x00000010
+/* Buffer control disable */
+#define CSOR_NOR_BCTLD			0x00000001
+
+/*
+ * Chip Select Option Register - GPCM Mode
+ */
+/* GPCM Mode - Normal */
+#define CSOR_GPCM_GPMODE_NORMAL		0x00000000
+/* GPCM Mode - GenericASIC */
+#define CSOR_GPCM_GPMODE_ASIC		0x80000000
+/* Parity Mode odd/even */
+#define CSOR_GPCM_PARITY_EVEN		0x40000000
+/* Parity Checking enable/disable */
+#define CSOR_GPCM_PAR_EN		0x20000000
+/* GPCM Timeout Count */
+#define CSOR_GPCM_GPTO_MASK		0x0F000000
+#define CSOR_GPCM_GPTO_SHIFT		24
+#define CSOR_GPCM_GPTO(n)	((__ilog2(n) - 8) << CSOR_GPCM_GPTO_SHIFT)
+/* GPCM External Access Termination mode for read access */
+#define CSOR_GPCM_RGETA_EXT		0x00080000
+/* GPCM External Access Termination mode for write access */
+#define CSOR_GPCM_WGETA_EXT		0x00040000
+/* Address Data Multiplexing Shift */
+#define CSOR_GPCM_ADM_MASK		0x0003E000
+#define CSOR_GPCM_ADM_SHIFT_SHIFT	13
+#define CSOR_GPCM_ADM_SHIFT(n)	((n) << CSOR_GPCM_ADM_SHIFT_SHIFT)
+/* Generic ASIC Parity error indication delay */
+#define CSOR_GPCM_GAPERRD_MASK		0x00000180
+#define CSOR_GPCM_GAPERRD_SHIFT		7
+#define CSOR_GPCM_GAPERRD(n)	(((n) - 1) << CSOR_GPCM_GAPERRD_SHIFT)
+/* Time for Read Enable High to Output High Impedance */
+#define CSOR_GPCM_TRHZ_MASK		0x0000001C
+#define CSOR_GPCM_TRHZ_20		0x00000000
+#define CSOR_GPCM_TRHZ_40		0x00000004
+#define CSOR_GPCM_TRHZ_60		0x00000008
+#define CSOR_GPCM_TRHZ_80		0x0000000C
+#define CSOR_GPCM_TRHZ_100		0x00000010
+/* Buffer control disable */
+#define CSOR_GPCM_BCTLD			0x00000001
+
+/*
+ * Flash Timing Registers (FTIM0 - FTIM2_CSn)
+ */
+/*
+ * FTIM0 - NAND Flash Mode
+ */
+#define FTIM0_NAND			0x7EFF3F3F
+#define FTIM0_NAND_TCCST_SHIFT	25
+#define FTIM0_NAND_TCCST(n)	((n) << FTIM0_NAND_TCCST_SHIFT)
+#define FTIM0_NAND_TWP_SHIFT	16
+#define FTIM0_NAND_TWP(n)	((n) << FTIM0_NAND_TWP_SHIFT)
+#define FTIM0_NAND_TWCHT_SHIFT	8
+#define FTIM0_NAND_TWCHT(n)	((n) << FTIM0_NAND_TWCHT_SHIFT)
+#define FTIM0_NAND_TWH_SHIFT	0
+#define FTIM0_NAND_TWH(n)	((n) << FTIM0_NAND_TWH_SHIFT)
+/*
+ * FTIM1 - NAND Flash Mode
+ */
+#define FTIM1_NAND			0xFFFF3FFF
+#define FTIM1_NAND_TADLE_SHIFT	24
+#define FTIM1_NAND_TADLE(n)	((n) << FTIM1_NAND_TADLE_SHIFT)
+#define FTIM1_NAND_TWBE_SHIFT	16
+#define FTIM1_NAND_TWBE(n)	((n) << FTIM1_NAND_TWBE_SHIFT)
+#define FTIM1_NAND_TRR_SHIFT	8
+#define FTIM1_NAND_TRR(n)	((n) << FTIM1_NAND_TRR_SHIFT)
+#define FTIM1_NAND_TRP_SHIFT	0
+#define FTIM1_NAND_TRP(n)	((n) << FTIM1_NAND_TRP_SHIFT)
+/*
+ * FTIM2 - NAND Flash Mode
+ */
+#define FTIM2_NAND			0x1FE1F8FF
+#define FTIM2_NAND_TRAD_SHIFT	21
+#define FTIM2_NAND_TRAD(n)	((n) << FTIM2_NAND_TRAD_SHIFT)
+#define FTIM2_NAND_TREH_SHIFT	11
+#define FTIM2_NAND_TREH(n)	((n) << FTIM2_NAND_TREH_SHIFT)
+#define FTIM2_NAND_TWHRE_SHIFT	0
+#define FTIM2_NAND_TWHRE(n)	((n) << FTIM2_NAND_TWHRE_SHIFT)
+/*
+ * FTIM3 - NAND Flash Mode
+ */
+#define FTIM3_NAND			0xFF000000
+#define FTIM3_NAND_TWW_SHIFT	24
+#define FTIM3_NAND_TWW(n)	((n) << FTIM3_NAND_TWW_SHIFT)
+
+/*
+ * FTIM0 - NOR Flash Mode
+ */
+#define FTIM0_NOR			0xF03F3F3F
+#define FTIM0_NOR_TACSE_SHIFT	28
+#define FTIM0_NOR_TACSE(n)	((n) << FTIM0_NOR_TACSE_SHIFT)
+#define FTIM0_NOR_TEADC_SHIFT	16
+#define FTIM0_NOR_TEADC(n)	((n) << FTIM0_NOR_TEADC_SHIFT)
+#define FTIM0_NOR_TAVDS_SHIFT	8
+#define FTIM0_NOR_TAVDS(n)	((n) << FTIM0_NOR_TAVDS_SHIFT)
+#define FTIM0_NOR_TEAHC_SHIFT	0
+#define FTIM0_NOR_TEAHC(n)	((n) << FTIM0_NOR_TEAHC_SHIFT)
+/*
+ * FTIM1 - NOR Flash Mode
+ */
+#define FTIM1_NOR			0xFF003F3F
+#define FTIM1_NOR_TACO_SHIFT	24
+#define FTIM1_NOR_TACO(n)	((n) << FTIM1_NOR_TACO_SHIFT)
+#define FTIM1_NOR_TRAD_NOR_SHIFT	8
+#define FTIM1_NOR_TRAD_NOR(n)	((n) << FTIM1_NOR_TRAD_NOR_SHIFT)
+#define FTIM1_NOR_TSEQRAD_NOR_SHIFT	0
+#define FTIM1_NOR_TSEQRAD_NOR(n)	((n) << FTIM1_NOR_TSEQRAD_NOR_SHIFT)
+/*
+ * FTIM2 - NOR Flash Mode
+ */
+#define FTIM2_NOR			0x0F3CFCFF
+#define FTIM2_NOR_TCS_SHIFT		24
+#define FTIM2_NOR_TCS(n)	((n) << FTIM2_NOR_TCS_SHIFT)
+#define FTIM2_NOR_TCH_SHIFT		18
+#define FTIM2_NOR_TCH(n)	((n) << FTIM2_NOR_TCH_SHIFT)
+#define FTIM2_NOR_TWPH_SHIFT	10
+#define FTIM2_NOR_TWPH(n)	((n) << FTIM2_NOR_TWPH_SHIFT)
+#define FTIM2_NOR_TWP_SHIFT		0
+#define FTIM2_NOR_TWP(n)	((n) << FTIM2_NOR_TWP_SHIFT)
+
+/*
+ * FTIM0 - Normal GPCM Mode
+ */
+#define FTIM0_GPCM			0xF03F3F3F
+#define FTIM0_GPCM_TACSE_SHIFT	28
+#define FTIM0_GPCM_TACSE(n)	((n) << FTIM0_GPCM_TACSE_SHIFT)
+#define FTIM0_GPCM_TEADC_SHIFT	16
+#define FTIM0_GPCM_TEADC(n)	((n) << FTIM0_GPCM_TEADC_SHIFT)
+#define FTIM0_GPCM_TAVDS_SHIFT	8
+#define FTIM0_GPCM_TAVDS(n)	((n) << FTIM0_GPCM_TAVDS_SHIFT)
+#define FTIM0_GPCM_TEAHC_SHIFT	0
+#define FTIM0_GPCM_TEAHC(n)	((n) << FTIM0_GPCM_TEAHC_SHIFT)
+/*
+ * FTIM1 - Normal GPCM Mode
+ */
+#define FTIM1_GPCM			0xFF003F00
+#define FTIM1_GPCM_TACO_SHIFT	24
+#define FTIM1_GPCM_TACO(n)	((n) << FTIM1_GPCM_TACO_SHIFT)
+#define FTIM1_GPCM_TRAD_SHIFT	8
+#define FTIM1_GPCM_TRAD(n)	((n) << FTIM1_GPCM_TRAD_SHIFT)
+/*
+ * FTIM2 - Normal GPCM Mode
+ */
+#define FTIM2_GPCM			0x0F3C00FF
+#define FTIM2_GPCM_TCS_SHIFT	24
+#define FTIM2_GPCM_TCS(n)	((n) << FTIM2_GPCM_TCS_SHIFT)
+#define FTIM2_GPCM_TCH_SHIFT	18
+#define FTIM2_GPCM_TCH(n)	((n) << FTIM2_GPCM_TCH_SHIFT)
+#define FTIM2_GPCM_TWP_SHIFT	0
+#define FTIM2_GPCM_TWP(n)	((n) << FTIM2_GPCM_TWP_SHIFT)
+
+/*
+ * Ready Busy Status Register (RB_STAT)
+ */
+/* CSn is READY */
+#define IFC_RB_STAT_READY_CS0		0x80000000
+#define IFC_RB_STAT_READY_CS1		0x40000000
+#define IFC_RB_STAT_READY_CS2		0x20000000
+#define IFC_RB_STAT_READY_CS3		0x10000000
+
+/*
+ * General Control Register (GCR)
+ */
+#define IFC_GCR_MASK			0x8000F800
+/* reset all IFC hardware */
+#define IFC_GCR_SOFT_RST_ALL		0x80000000
+/* Turnaroud Time of external buffer */
+#define IFC_GCR_TBCTL_TRN_TIME		0x0000F800
+#define IFC_GCR_TBCTL_TRN_TIME_SHIFT	11
+
+/*
+ * Common Event and Error Status Register (CM_EVTER_STAT)
+ */
+/* Chip select error */
+#define IFC_CM_EVTER_STAT_CSER		0x80000000
+
+/*
+ * Common Event and Error Enable Register (CM_EVTER_EN)
+ */
+/* Chip select error checking enable */
+#define IFC_CM_EVTER_EN_CSEREN		0x80000000
+
+/*
+ * Common Event and Error Interrupt Enable Register (CM_EVTER_INTR_EN)
+ */
+/* Chip select error interrupt enable */
+#define IFC_CM_EVTER_INTR_EN_CSERIREN	0x80000000
+
+/*
+ * Common Transfer Error Attribute Register-0 (CM_ERATTR0)
+ */
+/* transaction type of error Read/Write */
+#define IFC_CM_ERATTR0_ERTYP_READ	0x80000000
+#define IFC_CM_ERATTR0_ERAID		0x0FF00000
+#define IFC_CM_ERATTR0_ESRCID		0x0000FF00
+
+/*
+ * Clock Control Register (CCR)
+ */
+#define IFC_CCR_MASK			0x0F0F8800
+/* Clock division ratio */
+#define IFC_CCR_CLK_DIV_MASK		0x0F000000
+#define IFC_CCR_CLK_DIV_SHIFT		24
+#define IFC_CCR_CLK_DIV(n)		((n-1) << IFC_CCR_CLK_DIV_SHIFT)
+/* IFC Clock Delay */
+#define IFC_CCR_CLK_DLY_MASK		0x000F0000
+#define IFC_CCR_CLK_DLY_SHIFT		16
+#define IFC_CCR_CLK_DLY(n)		((n) << IFC_CCR_CLK_DLY_SHIFT)
+/* Invert IFC clock before sending out */
+#define IFC_CCR_INV_CLK_EN		0x00008000
+/* Fedback IFC Clock */
+#define IFC_CCR_FB_IFC_CLK_SEL		0x00000800
+
+/*
+ * Clock Status Register (CSR)
+ */
+/* Clk is stable */
+#define IFC_CSR_CLK_STAT_STABLE		0x80000000
+
+/*
+ * IFC_NAND Machine Specific Registers
+ */
+/*
+ * NAND Configuration Register (NCFGR)
+ */
+/* Auto Boot Mode */
+#define IFC_NAND_NCFGR_BOOT		0x80000000
+/* Addressing Mode-ROW0+n/COL0 */
+#define IFC_NAND_NCFGR_ADDR_MODE_RC0	0x00000000
+/* Addressing Mode-ROW0+n/COL0+n */
+#define IFC_NAND_NCFGR_ADDR_MODE_RC1	0x00400000
+/* Number of loop iterations of FIR sequences for multi page operations */
+#define IFC_NAND_NCFGR_NUM_LOOP_MASK	0x0000F000
+#define IFC_NAND_NCFGR_NUM_LOOP_SHIFT	12
+#define IFC_NAND_NCFGR_NUM_LOOP(n)	((n) << IFC_NAND_NCFGR_NUM_LOOP_SHIFT)
+/* Number of wait cycles */
+#define IFC_NAND_NCFGR_NUM_WAIT_MASK	0x000000FF
+#define IFC_NAND_NCFGR_NUM_WAIT_SHIFT	0
+
+/*
+ * NAND Flash Command Registers (NAND_FCR0/NAND_FCR1)
+ */
+/* General purpose FCM flash command bytes CMD0-CMD7 */
+#define IFC_NAND_FCR0_CMD0		0xFF000000
+#define IFC_NAND_FCR0_CMD0_SHIFT	24
+#define IFC_NAND_FCR0_CMD1		0x00FF0000
+#define IFC_NAND_FCR0_CMD1_SHIFT	16
+#define IFC_NAND_FCR0_CMD2		0x0000FF00
+#define IFC_NAND_FCR0_CMD2_SHIFT	8
+#define IFC_NAND_FCR0_CMD3		0x000000FF
+#define IFC_NAND_FCR0_CMD3_SHIFT	0
+#define IFC_NAND_FCR1_CMD4		0xFF000000
+#define IFC_NAND_FCR1_CMD4_SHIFT	24
+#define IFC_NAND_FCR1_CMD5		0x00FF0000
+#define IFC_NAND_FCR1_CMD5_SHIFT	16
+#define IFC_NAND_FCR1_CMD6		0x0000FF00
+#define IFC_NAND_FCR1_CMD6_SHIFT	8
+#define IFC_NAND_FCR1_CMD7		0x000000FF
+#define IFC_NAND_FCR1_CMD7_SHIFT	0
+
+/*
+ * Flash ROW and COL Address Register (ROWn, COLn)
+ */
+/* Main/spare region locator */
+#define IFC_NAND_COL_MS			0x80000000
+/* Column Address */
+#define IFC_NAND_COL_CA_MASK		0x00000FFF
+
+/*
+ * NAND Flash Byte Count Register (NAND_BC)
+ */
+/* Byte Count for read/Write */
+#define IFC_NAND_BC			0x000001FF
+
+/*
+ * NAND Flash Instruction Registers (NAND_FIR0/NAND_FIR1/NAND_FIR2)
+ */
+/* NAND Machine specific opcodes OP0-OP14*/
+#define IFC_NAND_FIR0_OP0		0xFC000000
+#define IFC_NAND_FIR0_OP0_SHIFT		26
+#define IFC_NAND_FIR0_OP1		0x03F00000
+#define IFC_NAND_FIR0_OP1_SHIFT		20
+#define IFC_NAND_FIR0_OP2		0x000FC000
+#define IFC_NAND_FIR0_OP2_SHIFT		14
+#define IFC_NAND_FIR0_OP3		0x00003F00
+#define IFC_NAND_FIR0_OP3_SHIFT		8
+#define IFC_NAND_FIR0_OP4		0x000000FC
+#define IFC_NAND_FIR0_OP4_SHIFT		2
+#define IFC_NAND_FIR1_OP5		0xFC000000
+#define IFC_NAND_FIR1_OP5_SHIFT		26
+#define IFC_NAND_FIR1_OP6		0x03F00000
+#define IFC_NAND_FIR1_OP6_SHIFT		20
+#define IFC_NAND_FIR1_OP7		0x000FC000
+#define IFC_NAND_FIR1_OP7_SHIFT		14
+#define IFC_NAND_FIR1_OP8		0x00003F00
+#define IFC_NAND_FIR1_OP8_SHIFT		8
+#define IFC_NAND_FIR1_OP9		0x000000FC
+#define IFC_NAND_FIR1_OP9_SHIFT		2
+#define IFC_NAND_FIR2_OP10		0xFC000000
+#define IFC_NAND_FIR2_OP10_SHIFT	26
+#define IFC_NAND_FIR2_OP11		0x03F00000
+#define IFC_NAND_FIR2_OP11_SHIFT	20
+#define IFC_NAND_FIR2_OP12		0x000FC000
+#define IFC_NAND_FIR2_OP12_SHIFT	14
+#define IFC_NAND_FIR2_OP13		0x00003F00
+#define IFC_NAND_FIR2_OP13_SHIFT	8
+#define IFC_NAND_FIR2_OP14		0x000000FC
+#define IFC_NAND_FIR2_OP14_SHIFT	2
+
+/*
+ * Instruction opcodes to be programmed
+ * in FIR registers- 6bits
+ */
+enum ifc_nand_fir_opcodes {
+	IFC_FIR_OP_NOP,
+	IFC_FIR_OP_CA0,
+	IFC_FIR_OP_CA1,
+	IFC_FIR_OP_CA2,
+	IFC_FIR_OP_CA3,
+	IFC_FIR_OP_RA0,
+	IFC_FIR_OP_RA1,
+	IFC_FIR_OP_RA2,
+	IFC_FIR_OP_RA3,
+	IFC_FIR_OP_CMD0,
+	IFC_FIR_OP_CMD1,
+	IFC_FIR_OP_CMD2,
+	IFC_FIR_OP_CMD3,
+	IFC_FIR_OP_CMD4,
+	IFC_FIR_OP_CMD5,
+	IFC_FIR_OP_CMD6,
+	IFC_FIR_OP_CMD7,
+	IFC_FIR_OP_CW0,
+	IFC_FIR_OP_CW1,
+	IFC_FIR_OP_CW2,
+	IFC_FIR_OP_CW3,
+	IFC_FIR_OP_CW4,
+	IFC_FIR_OP_CW5,
+	IFC_FIR_OP_CW6,
+	IFC_FIR_OP_CW7,
+	IFC_FIR_OP_WBCD,
+	IFC_FIR_OP_RBCD,
+	IFC_FIR_OP_BTRD,
+	IFC_FIR_OP_RDSTAT,
+	IFC_FIR_OP_NWAIT,
+	IFC_FIR_OP_WFR,
+	IFC_FIR_OP_SBRD,
+	IFC_FIR_OP_UA,
+	IFC_FIR_OP_RB,
+};
+
+/*
+ * NAND Chip Select Register (NAND_CSEL)
+ */
+#define IFC_NAND_CSEL			0x0C000000
+#define IFC_NAND_CSEL_SHIFT		26
+#define IFC_NAND_CSEL_CS0		0x00000000
+#define IFC_NAND_CSEL_CS1		0x04000000
+#define IFC_NAND_CSEL_CS2		0x08000000
+#define IFC_NAND_CSEL_CS3		0x0C000000
+
+/*
+ * NAND Operation Sequence Start (NANDSEQ_STRT)
+ */
+/* NAND Flash Operation Start */
+#define IFC_NAND_SEQ_STRT_FIR_STRT	0x80000000
+/* Automatic Erase */
+#define IFC_NAND_SEQ_STRT_AUTO_ERS	0x00800000
+/* Automatic Program */
+#define IFC_NAND_SEQ_STRT_AUTO_PGM	0x00100000
+/* Automatic Copyback */
+#define IFC_NAND_SEQ_STRT_AUTO_CPB	0x00020000
+/* Automatic Read Operation */
+#define IFC_NAND_SEQ_STRT_AUTO_RD	0x00004000
+/* Automatic Status Read */
+#define IFC_NAND_SEQ_STRT_AUTO_STAT_RD	0x00000800
+
+/*
+ * NAND Event and Error Status Register (NAND_EVTER_STAT)
+ */
+/* Operation Complete */
+#define IFC_NAND_EVTER_STAT_OPC		0x80000000
+/* Flash Timeout Error */
+#define IFC_NAND_EVTER_STAT_FTOER	0x08000000
+/* Write Protect Error */
+#define IFC_NAND_EVTER_STAT_WPER	0x04000000
+/* ECC Error */
+#define IFC_NAND_EVTER_STAT_ECCER	0x02000000
+/* RCW Load Done */
+#define IFC_NAND_EVTER_STAT_RCW_DN	0x00008000
+/* Boot Loadr Done */
+#define IFC_NAND_EVTER_STAT_BOOT_DN	0x00004000
+/* Bad Block Indicator search select */
+#define IFC_NAND_EVTER_STAT_BBI_SRCH_SE	0x00000800
+
+/*
+ * NAND Flash Page Read Completion Event Status Register
+ * (PGRDCMPL_EVT_STAT)
+ */
+#define PGRDCMPL_EVT_STAT_MASK		0xFFFF0000
+/* Small Page 0-15 Done */
+#define PGRDCMPL_EVT_STAT_SECTION_SP(n)	(1 << (31 - (n)))
+/* Large Page(2K) 0-3 Done */
+#define PGRDCMPL_EVT_STAT_LP_2K(n)	(0xF << (28 - (n)*4))
+/* Large Page(4K) 0-1 Done */
+#define PGRDCMPL_EVT_STAT_LP_4K(n)	(0xFF << (24 - (n)*8))
+
+/*
+ * NAND Event and Error Enable Register (NAND_EVTER_EN)
+ */
+/* Operation complete event enable */
+#define IFC_NAND_EVTER_EN_OPC_EN	0x80000000
+/* Page read complete event enable */
+#define IFC_NAND_EVTER_EN_PGRDCMPL_EN	0x20000000
+/* Flash Timeout error enable */
+#define IFC_NAND_EVTER_EN_FTOER_EN	0x08000000
+/* Write Protect error enable */
+#define IFC_NAND_EVTER_EN_WPER_EN	0x04000000
+/* ECC error logging enable */
+#define IFC_NAND_EVTER_EN_ECCER_EN	0x02000000
+
+/*
+ * NAND Event and Error Interrupt Enable Register (NAND_EVTER_INTR_EN)
+ */
+/* Enable interrupt for operation complete */
+#define IFC_NAND_EVTER_INTR_OPCIR_EN		0x80000000
+/* Enable interrupt for Page read complete */
+#define IFC_NAND_EVTER_INTR_PGRDCMPLIR_EN	0x20000000
+/* Enable interrupt for Flash timeout error */
+#define IFC_NAND_EVTER_INTR_FTOERIR_EN		0x08000000
+/* Enable interrupt for Write protect error */
+#define IFC_NAND_EVTER_INTR_WPERIR_EN		0x04000000
+/* Enable interrupt for ECC error*/
+#define IFC_NAND_EVTER_INTR_ECCERIR_EN		0x02000000
+
+/*
+ * NAND Transfer Error Attribute Register-0 (NAND_ERATTR0)
+ */
+#define IFC_NAND_ERATTR0_MASK		0x0C080000
+/* Error on CS0-3 for NAND */
+#define IFC_NAND_ERATTR0_ERCS_CS0	0x00000000
+#define IFC_NAND_ERATTR0_ERCS_CS1	0x04000000
+#define IFC_NAND_ERATTR0_ERCS_CS2	0x08000000
+#define IFC_NAND_ERATTR0_ERCS_CS3	0x0C000000
+/* Transaction type of error Read/Write */
+#define IFC_NAND_ERATTR0_ERTTYPE_READ	0x00080000
+
+/*
+ * NAND Flash Status Register (NAND_FSR)
+ */
+/* First byte of data read from read status op */
+#define IFC_NAND_NFSR_RS0		0xFF000000
+/* Second byte of data read from read status op */
+#define IFC_NAND_NFSR_RS1		0x00FF0000
+
+/*
+ * ECC Error Status Registers (ECCSTAT0-ECCSTAT3)
+ */
+/* Number of ECC errors on sector n (n = 0-15) */
+#define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR0_MASK	0x0F000000
+#define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR0_SHIFT	24
+#define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR1_MASK	0x000F0000
+#define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR1_SHIFT	16
+#define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR2_MASK	0x00000F00
+#define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR2_SHIFT	8
+#define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR3_MASK	0x0000000F
+#define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR3_SHIFT	0
+#define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR4_MASK	0x0F000000
+#define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR4_SHIFT	24
+#define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR5_MASK	0x000F0000
+#define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR5_SHIFT	16
+#define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR6_MASK	0x00000F00
+#define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR6_SHIFT	8
+#define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR7_MASK	0x0000000F
+#define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR7_SHIFT	0
+#define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR8_MASK	0x0F000000
+#define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR8_SHIFT	24
+#define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR9_MASK	0x000F0000
+#define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR9_SHIFT	16
+#define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR10_MASK	0x00000F00
+#define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR10_SHIFT	8
+#define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR11_MASK	0x0000000F
+#define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR11_SHIFT	0
+#define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR12_MASK	0x0F000000
+#define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR12_SHIFT	24
+#define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR13_MASK	0x000F0000
+#define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR13_SHIFT	16
+#define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR14_MASK	0x00000F00
+#define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR14_SHIFT	8
+#define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR15_MASK	0x0000000F
+#define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR15_SHIFT	0
+
+/*
+ * NAND Control Register (NANDCR)
+ */
+#define IFC_NAND_NCR_FTOCNT_MASK	0x1E000000
+#define IFC_NAND_NCR_FTOCNT_SHIFT	25
+#define IFC_NAND_NCR_FTOCNT(n)	((_ilog2(n) - 8)  << IFC_NAND_NCR_FTOCNT_SHIFT)
+
+/*
+ * NAND_AUTOBOOT_TRGR
+ */
+/* Trigger RCW load */
+#define IFC_NAND_AUTOBOOT_TRGR_RCW_LD	0x80000000
+/* Trigget Auto Boot */
+#define IFC_NAND_AUTOBOOT_TRGR_BOOT_LD	0x20000000
+
+/*
+ * NAND_MDR
+ */
+/* 1st read data byte when opcode SBRD */
+#define IFC_NAND_MDR_RDATA0		0xFF000000
+/* 2nd read data byte when opcode SBRD */
+#define IFC_NAND_MDR_RDATA1		0x00FF0000
+
+/*
+ * NOR Machine Specific Registers
+ */
+/*
+ * NOR Event and Error Status Register (NOR_EVTER_STAT)
+ */
+/* NOR Command Sequence Operation Complete */
+#define IFC_NOR_EVTER_STAT_OPC_NOR	0x80000000
+/* Write Protect Error */
+#define IFC_NOR_EVTER_STAT_WPER		0x04000000
+/* Command Sequence Timeout Error */
+#define IFC_NOR_EVTER_STAT_STOER	0x01000000
+
+/*
+ * NOR Event and Error Enable Register (NOR_EVTER_EN)
+ */
+/* NOR Command Seq complete event enable */
+#define IFC_NOR_EVTER_EN_OPCEN_NOR	0x80000000
+/* Write Protect Error Checking Enable */
+#define IFC_NOR_EVTER_EN_WPEREN		0x04000000
+/* Timeout Error Enable */
+#define IFC_NOR_EVTER_EN_STOEREN	0x01000000
+
+/*
+ * NOR Event and Error Interrupt Enable Register (NOR_EVTER_INTR_EN)
+ */
+/* Enable interrupt for OPC complete */
+#define IFC_NOR_EVTER_INTR_OPCEN_NOR	0x80000000
+/* Enable interrupt for write protect error */
+#define IFC_NOR_EVTER_INTR_WPEREN	0x04000000
+/* Enable interrupt for timeout error */
+#define IFC_NOR_EVTER_INTR_STOEREN	0x01000000
+
+/*
+ * NOR Transfer Error Attribute Register-0 (NOR_ERATTR0)
+ */
+/* Source ID for error transaction */
+#define IFC_NOR_ERATTR0_ERSRCID		0xFF000000
+/* AXI ID for error transation */
+#define IFC_NOR_ERATTR0_ERAID		0x000FF000
+/* Chip select corresponds to NOR error */
+#define IFC_NOR_ERATTR0_ERCS_CS0	0x00000000
+#define IFC_NOR_ERATTR0_ERCS_CS1	0x00000010
+#define IFC_NOR_ERATTR0_ERCS_CS2	0x00000020
+#define IFC_NOR_ERATTR0_ERCS_CS3	0x00000030
+/* Type of transaction read/write */
+#define IFC_NOR_ERATTR0_ERTYPE_READ	0x00000001
+
+/*
+ * NOR Transfer Error Attribute Register-2 (NOR_ERATTR2)
+ */
+#define IFC_NOR_ERATTR2_ER_NUM_PHASE_EXP	0x000F0000
+#define IFC_NOR_ERATTR2_ER_NUM_PHASE_PER	0x00000F00
+
+/*
+ * NOR Control Register (NORCR)
+ */
+#define IFC_NORCR_MASK			0x0F0F0000
+/* No. of Address/Data Phase */
+#define IFC_NORCR_NUM_PHASE_MASK	0x0F000000
+#define IFC_NORCR_NUM_PHASE_SHIFT	24
+#define IFC_NORCR_NUM_PHASE(n)	((n-1) << IFC_NORCR_NUM_PHASE_SHIFT)
+/* Sequence Timeout Count */
+#define IFC_NORCR_STOCNT_MASK		0x000F0000
+#define IFC_NORCR_STOCNT_SHIFT		16
+#define IFC_NORCR_STOCNT(n)	((__ilog2(n) - 8) << IFC_NORCR_STOCNT_SHIFT)
+
+/*
+ * GPCM Machine specific registers
+ */
+/*
+ * GPCM Event and Error Status Register (GPCM_EVTER_STAT)
+ */
+/* Timeout error */
+#define IFC_GPCM_EVTER_STAT_TOER	0x04000000
+/* Parity error */
+#define IFC_GPCM_EVTER_STAT_PER		0x01000000
+
+/*
+ * GPCM Event and Error Enable Register (GPCM_EVTER_EN)
+ */
+/* Timeout error enable */
+#define IFC_GPCM_EVTER_EN_TOER_EN	0x04000000
+/* Parity error enable */
+#define IFC_GPCM_EVTER_EN_PER_EN	0x01000000
+
+/*
+ * GPCM Event and Error Interrupt Enable Register (GPCM_EVTER_INTR_EN)
+ */
+/* Enable Interrupt for timeout error */
+#define IFC_GPCM_EEIER_TOERIR_EN	0x04000000
+/* Enable Interrupt for Parity error */
+#define IFC_GPCM_EEIER_PERIR_EN		0x01000000
+
+/*
+ * GPCM Transfer Error Attribute Register-0 (GPCM_ERATTR0)
+ */
+/* Source ID for error transaction */
+#define IFC_GPCM_ERATTR0_ERSRCID	0xFF000000
+/* AXI ID for error transaction */
+#define IFC_GPCM_ERATTR0_ERAID		0x000FF000
+/* Chip select corresponds to GPCM error */
+#define IFC_GPCM_ERATTR0_ERCS_CS0	0x00000000
+#define IFC_GPCM_ERATTR0_ERCS_CS1	0x00000040
+#define IFC_GPCM_ERATTR0_ERCS_CS2	0x00000080
+#define IFC_GPCM_ERATTR0_ERCS_CS3	0x000000C0
+/* Type of transaction read/Write */
+#define IFC_GPCM_ERATTR0_ERTYPE_READ	0x00000001
+
+/*
+ * GPCM Transfer Error Attribute Register-2 (GPCM_ERATTR2)
+ */
+/* On which beat of address/data parity error is observed */
+#define IFC_GPCM_ERATTR2_PERR_BEAT		0x00000C00
+/* Parity Error on byte */
+#define IFC_GPCM_ERATTR2_PERR_BYTE		0x000000F0
+/* Parity Error reported in addr or data phase */
+#define IFC_GPCM_ERATTR2_PERR_DATA_PHASE	0x00000001
+
+/*
+ * GPCM Status Register (GPCM_STAT)
+ */
+#define IFC_GPCM_STAT_BSY		0x80000000  /* GPCM is busy */
+
+
+#ifndef __ASSEMBLY__
+#include <asm/io.h>
+
+extern void print_ifc_regs(void);
+extern void init_early_memctl_regs(void);
+
+#define IFC_BASE_ADDR ((struct fsl_ifc *)CONFIG_SYS_IFC_ADDR)
+
+#define get_ifc_cspr_ext(i) (ifc_in32(&(IFC_BASE_ADDR)->cspr_cs[i].cspr_ext))
+#define get_ifc_cspr(i) (ifc_in32(&(IFC_BASE_ADDR)->cspr_cs[i].cspr))
+#define get_ifc_csor_ext(i) (ifc_in32(&(IFC_BASE_ADDR)->csor_cs[i].csor_ext))
+#define get_ifc_csor(i) (ifc_in32(&(IFC_BASE_ADDR)->csor_cs[i].csor))
+#define get_ifc_amask(i) (ifc_in32(&(IFC_BASE_ADDR)->amask_cs[i].amask))
+#define get_ifc_ftim(i, j) (ifc_in32(&(IFC_BASE_ADDR)->ftim_cs[i].ftim[j]))
+
+#define set_ifc_cspr_ext(i, v) \
+			(ifc_out32(&(IFC_BASE_ADDR)->cspr_cs[i].cspr_ext, v))
+#define set_ifc_cspr(i, v) (ifc_out32(&(IFC_BASE_ADDR)->cspr_cs[i].cspr, v))
+#define set_ifc_csor_ext(i, v) \
+			(ifc_out32(&(IFC_BASE_ADDR)->csor_cs[i].csor_ext, v))
+#define set_ifc_csor(i, v) (ifc_out32(&(IFC_BASE_ADDR)->csor_cs[i].csor, v))
+#define set_ifc_amask(i, v) (ifc_out32(&(IFC_BASE_ADDR)->amask_cs[i].amask, v))
+#define set_ifc_ftim(i, j, v) \
+			(ifc_out32(&(IFC_BASE_ADDR)->ftim_cs[i].ftim[j], v))
+
+enum ifc_chip_sel {
+	IFC_CS0,
+	IFC_CS1,
+	IFC_CS2,
+	IFC_CS3,
+	IFC_CS4,
+	IFC_CS5,
+	IFC_CS6,
+	IFC_CS7,
+};
+
+enum ifc_ftims {
+	IFC_FTIM0,
+	IFC_FTIM1,
+	IFC_FTIM2,
+	IFC_FTIM3,
+};
+
+/*
+ * IFC Controller NAND Machine registers
+ */
+struct fsl_ifc_nand {
+	u32 ncfgr;
+	u32 res1[0x4];
+	u32 nand_fcr0;
+	u32 nand_fcr1;
+	u32 res2[0x8];
+	u32 row0;
+	u32 res3;
+	u32 col0;
+	u32 res4;
+	u32 row1;
+	u32 res5;
+	u32 col1;
+	u32 res6;
+	u32 row2;
+	u32 res7;
+	u32 col2;
+	u32 res8;
+	u32 row3;
+	u32 res9;
+	u32 col3;
+	u32 res10[0x24];
+	u32 nand_fbcr;
+	u32 res11;
+	u32 nand_fir0;
+	u32 nand_fir1;
+	u32 nand_fir2;
+	u32 res12[0x10];
+	u32 nand_csel;
+	u32 res13;
+	u32 nandseq_strt;
+	u32 res14;
+	u32 nand_evter_stat;
+	u32 res15;
+	u32 pgrdcmpl_evt_stat;
+	u32 res16[0x2];
+	u32 nand_evter_en;
+	u32 res17[0x2];
+	u32 nand_evter_intr_en;
+	u32 res18[0x2];
+	u32 nand_erattr0;
+	u32 nand_erattr1;
+	u32 res19[0x10];
+	u32 nand_fsr;
+	u32 res20;
+	u32 nand_eccstat[4];
+	u32 res21[0x20];
+	u32 nanndcr;
+	u32 res22[0x2];
+	u32 nand_autoboot_trgr;
+	u32 res23;
+	u32 nand_mdr;
+	u32 res24[0x5C];
+};
+
+/*
+ * IFC controller NOR Machine registers
+ */
+struct fsl_ifc_nor {
+	u32 nor_evter_stat;
+	u32 res1[0x2];
+	u32 nor_evter_en;
+	u32 res2[0x2];
+	u32 nor_evter_intr_en;
+	u32 res3[0x2];
+	u32 nor_erattr0;
+	u32 nor_erattr1;
+	u32 nor_erattr2;
+	u32 res4[0x4];
+	u32 norcr;
+	u32 res5[0xEF];
+};
+
+/*
+ * IFC controller GPCM Machine registers
+ */
+struct fsl_ifc_gpcm {
+	u32 gpcm_evter_stat;
+	u32 res1[0x2];
+	u32 gpcm_evter_en;
+	u32 res2[0x2];
+	u32 gpcm_evter_intr_en;
+	u32 res3[0x2];
+	u32 gpcm_erattr0;
+	u32 gpcm_erattr1;
+	u32 gpcm_erattr2;
+	u32 gpcm_stat;
+	u32 res4[0x1F3];
+};
+
+#ifdef CONFIG_SYS_FSL_IFC_BANK_COUNT
+#if (CONFIG_SYS_FSL_IFC_BANK_COUNT <= 8)
+#define IFC_CSPR_REG_LEN	148
+#define IFC_AMASK_REG_LEN	144
+#define IFC_CSOR_REG_LEN	144
+#define IFC_FTIM_REG_LEN	576
+
+#define IFC_CSPR_USED_LEN	sizeof(struct fsl_ifc_cspr) * \
+					CONFIG_SYS_FSL_IFC_BANK_COUNT
+#define IFC_AMASK_USED_LEN	sizeof(struct fsl_ifc_amask) * \
+					CONFIG_SYS_FSL_IFC_BANK_COUNT
+#define IFC_CSOR_USED_LEN	sizeof(struct fsl_ifc_csor) * \
+					CONFIG_SYS_FSL_IFC_BANK_COUNT
+#define IFC_FTIM_USED_LEN	sizeof(struct fsl_ifc_ftim) * \
+					CONFIG_SYS_FSL_IFC_BANK_COUNT
+#else
+#error IFC BANK count not vaild
+#endif
+#else
+#error IFC BANK count not defined
+#endif
+
+struct fsl_ifc_cspr {
+	u32 cspr_ext;
+	u32 cspr;
+	u32 res;
+};
+
+struct fsl_ifc_amask {
+	u32 amask;
+	u32 res[0x2];
+};
+
+struct fsl_ifc_csor {
+	u32 csor;
+	u32 csor_ext;
+	u32 res;
+};
+
+struct fsl_ifc_ftim {
+	u32 ftim[4];
+	u32 res[0x8];
+};
+
+/*
+ * IFC Controller Registers
+ */
+struct fsl_ifc {
+	u32 ifc_rev;
+	u32 res1[0x2];
+	struct fsl_ifc_cspr cspr_cs[CONFIG_SYS_FSL_IFC_BANK_COUNT];
+	u8 res2[IFC_CSPR_REG_LEN - IFC_CSPR_USED_LEN];
+	struct fsl_ifc_amask amask_cs[CONFIG_SYS_FSL_IFC_BANK_COUNT];
+	u8 res3[IFC_AMASK_REG_LEN - IFC_AMASK_USED_LEN];
+	struct fsl_ifc_csor csor_cs[CONFIG_SYS_FSL_IFC_BANK_COUNT];
+	u8 res4[IFC_CSOR_REG_LEN - IFC_CSOR_USED_LEN];
+	struct fsl_ifc_ftim ftim_cs[CONFIG_SYS_FSL_IFC_BANK_COUNT];
+	u8 res5[IFC_FTIM_REG_LEN - IFC_FTIM_USED_LEN];
+	u32 rb_stat;
+	u32 res6[0x2];
+	u32 ifc_gcr;
+	u32 res7[0x2];
+	u32 cm_evter_stat;
+	u32 res8[0x2];
+	u32 cm_evter_en;
+	u32 res9[0x2];
+	u32 cm_evter_intr_en;
+	u32 res10[0x2];
+	u32 cm_erattr0;
+	u32 cm_erattr1;
+	u32 res11[0x2];
+	u32 ifc_ccr;
+	u32 ifc_csr;
+	u32 res12[0x2EB];
+	struct fsl_ifc_nand ifc_nand;
+	struct fsl_ifc_nor ifc_nor;
+	struct fsl_ifc_gpcm ifc_gpcm;
+};
+
+#ifdef CONFIG_SYS_FSL_ERRATUM_IFC_A002769
+#undef CSPR_MSEL_NOR
+#define CSPR_MSEL_NOR	CSPR_MSEL_GPCM
+#endif
+#endif /* CONFIG_FSL_IFC */
+
+#endif /* __ASSEMBLY__ */
+#endif /* __FSL_IFC_H */
diff --git a/include/fsl_immap.h b/include/fsl_immap.h
new file mode 100644
index 0000000000..00902cae08
--- /dev/null
+++ b/include/fsl_immap.h
@@ -0,0 +1,112 @@
+/*
+ * Common internal memory map for some Freescale SoCs
+ *
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __FSL_IMMAP_H
+#define __FSL_IMMAP_H
+/*
+ * DDR memory controller registers
+ * This structure works for mpc83xx (DDR2 and DDR3), mpc85xx, mpc86xx.
+ */
+struct ccsr_ddr {
+	u32	cs0_bnds;		/* Chip Select 0 Memory Bounds */
+	u8	res_04[4];
+	u32	cs1_bnds;		/* Chip Select 1 Memory Bounds */
+	u8	res_0c[4];
+	u32	cs2_bnds;		/* Chip Select 2 Memory Bounds */
+	u8	res_14[4];
+	u32	cs3_bnds;		/* Chip Select 3 Memory Bounds */
+	u8	res_1c[100];
+	u32	cs0_config;		/* Chip Select Configuration */
+	u32	cs1_config;		/* Chip Select Configuration */
+	u32	cs2_config;		/* Chip Select Configuration */
+	u32	cs3_config;		/* Chip Select Configuration */
+	u8	res_90[48];
+	u32	cs0_config_2;		/* Chip Select Configuration 2 */
+	u32	cs1_config_2;		/* Chip Select Configuration 2 */
+	u32	cs2_config_2;		/* Chip Select Configuration 2 */
+	u32	cs3_config_2;		/* Chip Select Configuration 2 */
+	u8	res_d0[48];
+	u32	timing_cfg_3;		/* SDRAM Timing Configuration 3 */
+	u32	timing_cfg_0;		/* SDRAM Timing Configuration 0 */
+	u32	timing_cfg_1;		/* SDRAM Timing Configuration 1 */
+	u32	timing_cfg_2;		/* SDRAM Timing Configuration 2 */
+	u32	sdram_cfg;		/* SDRAM Control Configuration */
+	u32	sdram_cfg_2;		/* SDRAM Control Configuration 2 */
+	u32	sdram_mode;		/* SDRAM Mode Configuration */
+	u32	sdram_mode_2;		/* SDRAM Mode Configuration 2 */
+	u32	sdram_md_cntl;		/* SDRAM Mode Control */
+	u32	sdram_interval;		/* SDRAM Interval Configuration */
+	u32	sdram_data_init;	/* SDRAM Data initialization */
+	u8	res_12c[4];
+	u32	sdram_clk_cntl;		/* SDRAM Clock Control */
+	u8	res_134[20];
+	u32	init_addr;		/* training init addr */
+	u32	init_ext_addr;		/* training init extended addr */
+	u8	res_150[16];
+	u32	timing_cfg_4;		/* SDRAM Timing Configuration 4 */
+	u32	timing_cfg_5;		/* SDRAM Timing Configuration 5 */
+	u8	reg_168[8];
+	u32	ddr_zq_cntl;		/* ZQ calibration control*/
+	u32	ddr_wrlvl_cntl;		/* write leveling control*/
+	u8	reg_178[4];
+	u32	ddr_sr_cntr;		/* self refresh counter */
+	u32	ddr_sdram_rcw_1;	/* Control Words 1 */
+	u32	ddr_sdram_rcw_2;	/* Control Words 2 */
+	u8	reg_188[8];
+	u32	ddr_wrlvl_cntl_2;	/* write leveling control 2 */
+	u32	ddr_wrlvl_cntl_3;	/* write leveling control 3 */
+	u8	res_198[104];
+	u32	sdram_mode_3;		/* SDRAM Mode Configuration 3 */
+	u32	sdram_mode_4;		/* SDRAM Mode Configuration 4 */
+	u32	sdram_mode_5;		/* SDRAM Mode Configuration 5 */
+	u32	sdram_mode_6;		/* SDRAM Mode Configuration 6 */
+	u32	sdram_mode_7;		/* SDRAM Mode Configuration 7 */
+	u32	sdram_mode_8;		/* SDRAM Mode Configuration 8 */
+	u8	res_218[0x908];
+	u32	ddr_dsr1;		/* Debug Status 1 */
+	u32	ddr_dsr2;		/* Debug Status 2 */
+	u32	ddr_cdr1;		/* Control Driver 1 */
+	u32	ddr_cdr2;		/* Control Driver 2 */
+	u8	res_b30[200];
+	u32	ip_rev1;		/* IP Block Revision 1 */
+	u32	ip_rev2;		/* IP Block Revision 2 */
+	u32	eor;			/* Enhanced Optimization Register */
+	u8	res_c04[252];
+	u32	mtcr;			/* Memory Test Control Register */
+	u8	res_d04[28];
+	u32	mtp1;			/* Memory Test Pattern 1 */
+	u32	mtp2;			/* Memory Test Pattern 2 */
+	u32	mtp3;			/* Memory Test Pattern 3 */
+	u32	mtp4;			/* Memory Test Pattern 4 */
+	u32	mtp5;			/* Memory Test Pattern 5 */
+	u32	mtp6;			/* Memory Test Pattern 6 */
+	u32	mtp7;			/* Memory Test Pattern 7 */
+	u32	mtp8;			/* Memory Test Pattern 8 */
+	u32	mtp9;			/* Memory Test Pattern 9 */
+	u32	mtp10;			/* Memory Test Pattern 10 */
+	u8	res_d48[184];
+	u32	data_err_inject_hi;	/* Data Path Err Injection Mask High */
+	u32	data_err_inject_lo;	/* Data Path Err Injection Mask Low */
+	u32	ecc_err_inject;		/* Data Path Err Injection Mask ECC */
+	u8	res_e0c[20];
+	u32	capture_data_hi;	/* Data Path Read Capture High */
+	u32	capture_data_lo;	/* Data Path Read Capture Low */
+	u32	capture_ecc;		/* Data Path Read Capture ECC */
+	u8	res_e2c[20];
+	u32	err_detect;		/* Error Detect */
+	u32	err_disable;		/* Error Disable */
+	u32	err_int_en;
+	u32	capture_attributes;	/* Error Attrs Capture */
+	u32	capture_address;	/* Error Addr Capture */
+	u32	capture_ext_address;	/* Error Extended Addr Capture */
+	u32	err_sbe;		/* Single-Bit ECC Error Management */
+	u8	res_e5c[164];
+	u32	debug[32];		/* debug_1 to debug_32 */
+	u8	res_f80[128];
+};
+#endif /* __FSL_IMMAP_H */
diff --git a/include/fsl_mdio.h b/include/fsl_mdio.h
index 9c0b762773..b58713d896 100644
--- a/include/fsl_mdio.h
+++ b/include/fsl_mdio.h
@@ -1,5 +1,5 @@
 /*
- * Copyright 2009-2012 Freescale Semiconductor, Inc.
+ * Copyright 2009-2012, 2013 Freescale Semiconductor, Inc.
  *	Jun-jie Zhang <b18070@freescale.com>
  *	Mingkai Hu <Mingkai.hu@freescale.com>
  *
@@ -31,9 +31,9 @@
 #define MIIMIND_BUSY		0x00000001
 #define MIIMIND_NOTVALID	0x00000004
 
-void tsec_local_mdio_write(struct tsec_mii_mng *phyregs, int port_addr,
+void tsec_local_mdio_write(struct tsec_mii_mng __iomem *phyregs, int port_addr,
 		int dev_addr, int reg, int value);
-int tsec_local_mdio_read(struct tsec_mii_mng *phyregs, int port_addr,
+int tsec_local_mdio_read(struct tsec_mii_mng __iomem *phyregs, int port_addr,
 		int dev_addr, int regnum);
 int tsec_phy_read(struct mii_dev *bus, int addr, int dev_addr, int regnum);
 int tsec_phy_write(struct mii_dev *bus, int addr, int dev_addr, int regnum,
@@ -44,7 +44,7 @@ int memac_mdio_read(struct mii_dev *bus, int port_addr, int dev_addr,
 		int regnum);
 
 struct fsl_pq_mdio_info {
-	struct tsec_mii_mng *regs;
+	struct tsec_mii_mng __iomem *regs;
 	char *name;
 };
 int fsl_pq_mdio_init(bd_t *bis, struct fsl_pq_mdio_info *info);
diff --git a/include/fsl_usb.h b/include/fsl_usb.h
index 915774cba8..8b63cdd88c 100644
--- a/include/fsl_usb.h
+++ b/include/fsl_usb.h
@@ -52,13 +52,32 @@ struct ccsr_usb_phy {
 #define CONFIG_SYS_FSL_USB_PLLPRG2_MFI (5 << 16)
 #define CONFIG_SYS_FSL_USB_PLLPRG2_PLL_EN (1 << 21)
 #define CONFIG_SYS_FSL_USB_SYS_CLK_VALID (1 << 0)
+#define CONFIG_SYS_FSL_USB_XCVRPRG_HS_DCNT_PROG_EN (1 << 7)
+#define CONFIG_SYS_FSL_USB_XCVRPRG_HS_DCNT_PROG_MASK (3 << 4)
+
+#define INC_DCNT_THRESHOLD_25MV        (0 << 4)
+#define INC_DCNT_THRESHOLD_50MV        (1 << 4)
+#define DEC_DCNT_THRESHOLD_25MV        (2 << 4)
+#define DEC_DCNT_THRESHOLD_50MV        (3 << 4)
 #else
 struct ccsr_usb_phy {
-	u8	res0[0x18];
+	u32     config1;
+	u32     config2;
+	u32     config3;
+	u32     config4;
+	u32     config5;
+	u32     status1;
 	u32	usb_enable_override;
 	u8	res[0xe4];
 };
-#define	CONFIG_SYS_FSL_USB_ENABLE_OVERRIDE	1
+#define CONFIG_SYS_FSL_USB_HS_DISCNCT_INC (3 << 22)
+#define CONFIG_SYS_FSL_USB_RX_AUTO_CAL_RD_WR_SEL (1 << 20)
+#define CONFIG_SYS_FSL_USB_SQUELCH_PROG_WR_0 13
+#define CONFIG_SYS_FSL_USB_SQUELCH_PROG_WR_3 16
+#define CONFIG_SYS_FSL_USB_SQUELCH_PROG_RD_0 0
+#define CONFIG_SYS_FSL_USB_SQUELCH_PROG_RD_3 3
+#define CONFIG_SYS_FSL_USB_ENABLE_OVERRIDE 1
+#define CONFIG_SYS_FSL_USB_SQUELCH_PROG_MASK 0x07
 #endif
 
 #endif /*_ASM_FSL_USB_H_ */
diff --git a/include/g_dnl.h b/include/g_dnl.h
index 2b2f11a62f..8f813c21ee 100644
--- a/include/g_dnl.h
+++ b/include/g_dnl.h
@@ -10,10 +10,9 @@
 
 #include <linux/usb/ch9.h>
 #include <linux/usb/gadget.h>
-int g_dnl_bind_fixup(struct usb_device_descriptor *);
+int g_dnl_bind_fixup(struct usb_device_descriptor *, const char *);
 int g_dnl_register(const char *s);
 void g_dnl_unregister(void);
+void g_dnl_set_serialnumber(char *);
 
-/* USB initialization declaration - board specific */
-void board_usb_init(void);
 #endif /* __G_DOWNLOAD_H_ */
diff --git a/include/i2c.h b/include/i2c.h
index 8fd17d190a..1b4078ed62 100644
--- a/include/i2c.h
+++ b/include/i2c.h
@@ -68,6 +68,7 @@ struct i2c_adapter {
 	uint		(*set_bus_speed)(struct i2c_adapter *adap,
 				uint speed);
 	int		speed;
+	int		waitdelay;
 	int		slaveaddr;
 	int		init_done;
 	int		hwadapnr;
@@ -135,6 +136,8 @@ extern struct i2c_bus_hose	i2c_bus[];
 #define I2C_MUX_PCA9544		{I2C_MUX_PCA9544_ID, "PCA9544A"}
 #define I2C_MUX_PCA9547_ID	4
 #define I2C_MUX_PCA9547		{I2C_MUX_PCA9547_ID, "PCA9547A"}
+#define I2C_MUX_PCA9548_ID	5
+#define I2C_MUX_PCA9548		{I2C_MUX_PCA9548_ID, "PCA9548"}
 #endif
 
 #ifndef I2C_SOFT_DECLARATIONS
@@ -145,7 +148,7 @@ extern struct i2c_bus_hose	i2c_bus[];
 
 # elif (defined(CONFIG_AT91RM9200) || \
 	defined(CONFIG_AT91SAM9260) ||  defined(CONFIG_AT91SAM9261) || \
-	defined(CONFIG_AT91SAM9263)) && !defined(CONFIG_AT91_LEGACY)
+	defined(CONFIG_AT91SAM9263))
 #  define I2C_SOFT_DECLARATIONS	at91_pio_t *pio	= (at91_pio_t *) ATMEL_BASE_PIOA;
 # else
 #  define I2C_SOFT_DECLARATIONS
diff --git a/include/image.h b/include/image.h
index ee6eb8d246..6afd57bafd 100644
--- a/include/image.h
+++ b/include/image.h
@@ -99,9 +99,9 @@ struct lmb;
 #endif
 
 #ifdef CONFIG_OF_BOARD_SETUP
-# define IMAAGE_OF_BOARD_SETUP		1
+# define IMAGE_OF_BOARD_SETUP		1
 #else
-# define IMAAGE_OF_BOARD_SETUP		0
+# define IMAGE_OF_BOARD_SETUP		0
 #endif
 
 /*
@@ -156,6 +156,8 @@ struct lmb;
 #define IH_ARCH_SANDBOX		19	/* Sandbox architecture (test only) */
 #define IH_ARCH_NDS32	        20	/* ANDES Technology - NDS32  */
 #define IH_ARCH_OPENRISC        21	/* OpenRISC 1000  */
+#define IH_ARCH_ARM64		22	/* ARM64	*/
+#define IH_ARCH_ARC		23	/* Synopsys DesignWare ARC */
 
 /*
  * Image Types
diff --git a/include/ks8721.h b/include/ks8721.h
deleted file mode 100644
index 90ed178087..0000000000
--- a/include/ks8721.h
+++ /dev/null
@@ -1,75 +0,0 @@
-/*
- * NOTE:	MICREL ethernet Physical layer
- *
- * Version:	KS8721.h
- *
- * Authors:	Eric Benard (based on dm9161.h)
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-/* MICREL PHYSICAL LAYER TRANSCEIVER KS8721 */
-
-#define	KS8721_BMCR		0
-#define KS8721_BMSR		1
-#define KS8721_PHYID1		2
-#define KS8721_PHYID2		3
-#define KS8721_ANAR		4
-#define KS8721_ANLPAR		5
-#define KS8721_ANER		6
-#define KS8721_RECR		15
-#define KS8721_MDINTR		27
-#define KS8721_100BT		31
-
-/* --Bit definitions: KS8721_BMCR */
-#define KS8721_RESET		(1 << 15)
-#define KS8721_LOOPBACK		(1 << 14)
-#define KS8721_SPEED_SELECT	(1 << 13)
-#define KS8721_AUTONEG		(1 << 12)
-#define KS8721_POWER_DOWN	(1 << 11)
-#define KS8721_ISOLATE		(1 << 10)
-#define KS8721_RESTART_AUTONEG	(1 << 9)
-#define KS8721_DUPLEX_MODE	(1 << 8)
-#define KS8721_COLLISION_TEST	(1 << 7)
-#define	KS8721_DISABLE		(1 << 0)
-
-/*--Bit definitions: KS8721_BMSR */
-#define KS8721_100BASE_T4	(1 << 15)
-#define KS8721_100BASE_TX_FD	(1 << 14)
-#define KS8721_100BASE_T4_HD	(1 << 13)
-#define KS8721_10BASE_T_FD	(1 << 12)
-#define KS8721_10BASE_T_HD	(1 << 11)
-#define KS8721_MF_PREAMB_SUPPR	(1 << 6)
-#define KS8721_AUTONEG_COMP	(1 << 5)
-#define KS8721_REMOTE_FAULT	(1 << 4)
-#define KS8721_AUTONEG_ABILITY	(1 << 3)
-#define KS8721_LINK_STATUS	(1 << 2)
-#define KS8721_JABBER_DETECT	(1 << 1)
-#define KS8721_EXTEND_CAPAB	(1 << 0)
-
-/*--Bit definitions: KS8721_PHYID */
-#define KS8721_PHYID_OUI	0x0885
-#define KS8721_LSB_MASK		0x3F
-
-#define	KS8721BL_MODEL		0x21
-#define	KS8721_MODELMASK	0x3F0
-#define	KS8721BL_REV		0x9
-#define KS8721_REVMASK		0xF
-
-/*--Bit definitions: KS8721_ANAR, KS8721_ANLPAR */
-#define KS8721_NP		(1 << 15)
-#define KS8721_ACK		(1 << 14)
-#define KS8721_RF		(1 << 13)
-#define KS8721_PAUSE		(1 << 10)
-#define KS8721_T4		(1 << 9)
-#define KS8721_TX_FDX		(1 << 8)
-#define KS8721_TX_HDX		(1 << 7)
-#define KS8721_10_FDX		(1 << 6)
-#define KS8721_10_HDX		(1 << 5)
-#define KS8721_AN_IEEE_802_3	0x0001
-
-/******************  function prototypes **********************/
-unsigned int  ks8721_isphyconnected(AT91PS_EMAC p_mac);
-unsigned char ks8721_getlinkspeed(AT91PS_EMAC p_mac);
-unsigned char ks8721_autonegotiate(AT91PS_EMAC p_mac, int *status);
-unsigned char ks8721_initphy(AT91PS_EMAC p_mac);
diff --git a/include/lcd.h b/include/lcd.h
index 40e8d2a86b..5f84cd3c5b 100644
--- a/include/lcd.h
+++ b/include/lcd.h
@@ -223,6 +223,8 @@ typedef struct vidinfo {
 	unsigned int logo_on;
 	unsigned int logo_width;
 	unsigned int logo_height;
+	int logo_x_offset;
+	int logo_y_offset;
 	unsigned long logo_addr;
 	unsigned int rgb_mode;
 	unsigned int resolution;
@@ -311,6 +313,9 @@ int lcd_get_size(int *line_length);
 int lcd_dt_simplefb_add_node(void *blob);
 int lcd_dt_simplefb_enable_existing_node(void *blob);
 
+/* Update the LCD / flush the cache */
+void lcd_sync(void);
+
 /************************************************************************/
 /* ** BITMAP DISPLAY SUPPORT						*/
 /************************************************************************/
diff --git a/include/linker_lists.h b/include/linker_lists.h
index 1eebb95fbb..997d149b71 100644
--- a/include/linker_lists.h
+++ b/include/linker_lists.h
@@ -8,6 +8,9 @@
  * SPDX-License-Identifier:	GPL-2.0+
  */
 
+#ifndef __LINKER_LISTS_H__
+#define __LINKER_LISTS_H__
+
 /*
  * There is no use in including this from ASM files, but that happens
  * anyway, e.g. PPC kgdb.S includes command.h which incluse us.
@@ -97,9 +100,6 @@
  *   %u_boot_list_2_drivers_3
  */
 
-#ifndef __LINKER_LISTS_H__
-#define __LINKER_LISTS_H__
-
 /**
  * ll_entry_declare() - Declare linker-generated array entry
  * @_type:	Data type of the entry
diff --git a/include/linux/config.h b/include/linux/config.h
deleted file mode 100644
index a0194cb7c7..0000000000
--- a/include/linux/config.h
+++ /dev/null
@@ -1,6 +0,0 @@
-#ifndef _LINUX_CONFIG_H
-#define _LINUX_CONFIG_H
-
-/* #include <linux/autoconf.h> */
-
-#endif
diff --git a/include/linux/crc8.h b/include/linux/crc8.h
new file mode 100644
index 0000000000..b5fd2ac9d6
--- /dev/null
+++ b/include/linux/crc8.h
@@ -0,0 +1,23 @@
+/*
+ * Copyright (c) 2013 Google, Inc
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+
+#ifndef __linux_crc8_h
+#define __linux_crc8_h
+
+/**
+ * crc8() - Calculate and return CRC-8 of the data
+ *
+ * This uses an x^8 + x^2 + x + 1 polynomial.  A table-based algorithm would
+ * be faster, but for only a few bytes it isn't worth the code size
+ *
+ * @vptr: Buffer to checksum
+ * @len: Length of buffer in bytes
+ * @return CRC8 checksum
+ */
+unsigned int crc8(const unsigned char *vptr, int len);
+
+#endif
diff --git a/include/linux/fb.h b/include/linux/fb.h
index 111372c9fd..652cf3bab7 100644
--- a/include/linux/fb.h
+++ b/include/linux/fb.h
@@ -612,6 +612,8 @@ struct fb_videomode {
 	u32 flag;
 };
 
+int board_video_skip(void);
+
 #endif /* __KERNEL__ */
 
 #endif /* _LINUX_FB_H */
diff --git a/include/linux/linkage.h b/include/linux/linkage.h
index 9ddf830284..7435fcd026 100644
--- a/include/linux/linkage.h
+++ b/include/linux/linkage.h
@@ -10,7 +10,6 @@
 #define _LINUX_LINKAGE_H
 
 #include <asm/linkage.h>
-#include <linux/config.h>
 
 #ifdef __cplusplus
 #define CPP_ASMLINKAGE		extern "C"
@@ -49,6 +48,10 @@
 	.globl SYMBOL_NAME(name); \
 	LENTRY(name)
 
+#define WEAK(name) \
+	.weak SYMBOL_NAME(name); \
+	LENTRY(name)
+
 #ifndef END
 #define END(name) \
 	.size name, .-name
diff --git a/include/linux/mtd/inftl-user.h b/include/linux/mtd/inftl-user.h
deleted file mode 100644
index 45220ed76f..0000000000
--- a/include/linux/mtd/inftl-user.h
+++ /dev/null
@@ -1,89 +0,0 @@
-/*
- * $Id: inftl-user.h,v 1.2 2005/11/07 11:14:56 gleixner Exp $
- *
- * Parts of INFTL headers shared with userspace
- *
- */
-
-#ifndef __MTD_INFTL_USER_H__
-#define __MTD_INFTL_USER_H__
-
-#define	OSAK_VERSION	0x5120
-#define	PERCENTUSED	98
-
-#define	SECTORSIZE	512
-
-/* Block Control Information */
-
-struct inftl_bci {
-	uint8_t ECCsig[6];
-	uint8_t Status;
-	uint8_t Status1;
-} __attribute__((packed));
-
-struct inftl_unithead1 {
-	uint16_t virtualUnitNo;
-	uint16_t prevUnitNo;
-	uint8_t ANAC;
-	uint8_t NACs;
-	uint8_t parityPerField;
-	uint8_t discarded;
-} __attribute__((packed));
-
-struct inftl_unithead2 {
-	uint8_t parityPerField;
-	uint8_t ANAC;
-	uint16_t prevUnitNo;
-	uint16_t virtualUnitNo;
-	uint8_t NACs;
-	uint8_t discarded;
-} __attribute__((packed));
-
-struct inftl_unittail {
-	uint8_t Reserved[4];
-	uint16_t EraseMark;
-	uint16_t EraseMark1;
-} __attribute__((packed));
-
-union inftl_uci {
-	struct inftl_unithead1 a;
-	struct inftl_unithead2 b;
-	struct inftl_unittail c;
-};
-
-struct inftl_oob {
-	struct inftl_bci b;
-	union inftl_uci u;
-};
-
-
-/* INFTL Media Header */
-
-struct INFTLPartition {
-	__u32 virtualUnits;
-	__u32 firstUnit;
-	__u32 lastUnit;
-	__u32 flags;
-	__u32 spareUnits;
-	__u32 Reserved0;
-	__u32 Reserved1;
-} __attribute__((packed));
-
-struct INFTLMediaHeader {
-	char bootRecordID[8];
-	__u32 NoOfBootImageBlocks;
-	__u32 NoOfBinaryPartitions;
-	__u32 NoOfBDTLPartitions;
-	__u32 BlockMultiplierBits;
-	__u32 FormatFlags;
-	__u32 OsakVersion;
-	__u32 PercentUsed;
-	struct INFTLPartition Partitions[4];
-} __attribute__((packed));
-
-/* Partition flag types */
-#define	INFTL_BINARY	0x20000000
-#define	INFTL_BDTL	0x40000000
-#define	INFTL_LAST	0x80000000
-
-#endif /* __MTD_INFTL_USER_H__ */
diff --git a/include/linux/mtd/jffs2-user.h b/include/linux/mtd/jffs2-user.h
deleted file mode 100644
index d508ef0ae0..0000000000
--- a/include/linux/mtd/jffs2-user.h
+++ /dev/null
@@ -1,35 +0,0 @@
-/*
- * $Id: jffs2-user.h,v 1.1 2004/05/05 11:57:54 dwmw2 Exp $
- *
- * JFFS2 definitions for use in user space only
- */
-
-#ifndef __JFFS2_USER_H__
-#define __JFFS2_USER_H__
-
-/* This file is blessed for inclusion by userspace */
-#include <linux/jffs2.h>
-#include <endian.h>
-#include <byteswap.h>
-
-#undef cpu_to_je16
-#undef cpu_to_je32
-#undef cpu_to_jemode
-#undef je16_to_cpu
-#undef je32_to_cpu
-#undef jemode_to_cpu
-
-extern int target_endian;
-
-#define t16(x) ({ uint16_t __b = (x); (target_endian==__BYTE_ORDER)?__b:bswap_16(__b); })
-#define t32(x) ({ uint32_t __b = (x); (target_endian==__BYTE_ORDER)?__b:bswap_32(__b); })
-
-#define cpu_to_je16(x) ((jint16_t){t16(x)})
-#define cpu_to_je32(x) ((jint32_t){t32(x)})
-#define cpu_to_jemode(x) ((jmode_t){t32(x)})
-
-#define je16_to_cpu(x) (t16((x).v16))
-#define je32_to_cpu(x) (t32((x).v32))
-#define jemode_to_cpu(x) (t32((x).m))
-
-#endif /* __JFFS2_USER_H__ */
diff --git a/include/linux/mtd/mtd.h b/include/linux/mtd/mtd.h
index 6f44abdc16..a65b681551 100644
--- a/include/linux/mtd/mtd.h
+++ b/include/linux/mtd/mtd.h
@@ -96,6 +96,29 @@ struct mtd_oob_ops {
 	uint8_t		*oobbuf;
 };
 
+#ifdef CONFIG_SYS_NAND_MAX_OOBFREE
+#define MTD_MAX_OOBFREE_ENTRIES_LARGE	CONFIG_SYS_NAND_MAX_OOBFREE
+#else
+#define MTD_MAX_OOBFREE_ENTRIES_LARGE	32
+#endif
+
+#ifdef CONFIG_SYS_NAND_MAX_ECCPOS
+#define MTD_MAX_ECCPOS_ENTRIES_LARGE	CONFIG_SYS_NAND_MAX_ECCPOS
+#else
+#define MTD_MAX_ECCPOS_ENTRIES_LARGE	640
+#endif
+
+/*
+ * ECC layout control structure. Exported to userspace for
+ * diagnosis and to allow creation of raw images
+ */
+struct nand_ecclayout {
+	uint32_t eccbytes;
+	uint32_t eccpos[MTD_MAX_ECCPOS_ENTRIES_LARGE];
+	uint32_t oobavail;
+	struct nand_oobfree oobfree[MTD_MAX_OOBFREE_ENTRIES_LARGE];
+};
+
 struct mtd_info {
 	u_char type;
 	u_int32_t flags;
diff --git a/arch/arm/include/asm/arch-am33xx/elm.h b/include/linux/mtd/omap_elm.h
index 45454eaf0f..45454eaf0f 100644
--- a/arch/arm/include/asm/arch-am33xx/elm.h
+++ b/include/linux/mtd/omap_elm.h
diff --git a/include/linux/mtd/omap_gpmc.h b/include/linux/mtd/omap_gpmc.h
new file mode 100644
index 0000000000..22f6573969
--- /dev/null
+++ b/include/linux/mtd/omap_gpmc.h
@@ -0,0 +1,84 @@
+/*
+ * (C) Copyright 2004-2008 Texas Instruments, <www.ti.com>
+ * Rohit Choraria <rohitkc@ti.com>
+ *
+ * (C) Copyright 2013 Andreas Bießmann <andreas.devel@googlemail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+#ifndef __ASM_OMAP_GPMC_H
+#define __ASM_OMAP_GPMC_H
+
+#define GPMC_BUF_EMPTY	0
+#define GPMC_BUF_FULL	1
+
+enum omap_ecc {
+	/* 1-bit  ECC calculation by Software, Error detection by Software */
+	OMAP_ECC_HAM1_CODE_SW = 1, /* avoid un-initialized int can be 0x0 */
+	/* 1-bit  ECC calculation by GPMC, Error detection by Software */
+	/* ECC layout compatible to legacy ROMCODE. */
+	OMAP_ECC_HAM1_CODE_HW,
+	/* 4-bit  ECC calculation by GPMC, Error detection by Software */
+	OMAP_ECC_BCH4_CODE_HW_DETECTION_SW,
+	/* 4-bit  ECC calculation by GPMC, Error detection by ELM */
+	OMAP_ECC_BCH4_CODE_HW,
+	/* 8-bit  ECC calculation by GPMC, Error detection by Software */
+	OMAP_ECC_BCH8_CODE_HW_DETECTION_SW,
+	/* 8-bit  ECC calculation by GPMC, Error detection by ELM */
+	OMAP_ECC_BCH8_CODE_HW,
+};
+
+struct gpmc_cs {
+	u32 config1;		/* 0x00 */
+	u32 config2;		/* 0x04 */
+	u32 config3;		/* 0x08 */
+	u32 config4;		/* 0x0C */
+	u32 config5;		/* 0x10 */
+	u32 config6;		/* 0x14 */
+	u32 config7;		/* 0x18 */
+	u32 nand_cmd;		/* 0x1C */
+	u32 nand_adr;		/* 0x20 */
+	u32 nand_dat;		/* 0x24 */
+	u8 res[8];		/* blow up to 0x30 byte */
+};
+
+struct bch_res_0_3 {
+	u32 bch_result_x[4];
+};
+
+struct gpmc {
+	u8 res1[0x10];
+	u32 sysconfig;		/* 0x10 */
+	u8 res2[0x4];
+	u32 irqstatus;		/* 0x18 */
+	u32 irqenable;		/* 0x1C */
+	u8 res3[0x20];
+	u32 timeout_control;	/* 0x40 */
+	u8 res4[0xC];
+	u32 config;		/* 0x50 */
+	u32 status;		/* 0x54 */
+	u8 res5[0x8];		/* 0x58 */
+	struct gpmc_cs cs[8];	/* 0x60, 0x90, .. */
+	u8 res6[0x14];		/* 0x1E0 */
+	u32 ecc_config;		/* 0x1F4 */
+	u32 ecc_control;	/* 0x1F8 */
+	u32 ecc_size_config;	/* 0x1FC */
+	u32 ecc1_result;	/* 0x200 */
+	u32 ecc2_result;	/* 0x204 */
+	u32 ecc3_result;	/* 0x208 */
+	u32 ecc4_result;	/* 0x20C */
+	u32 ecc5_result;	/* 0x210 */
+	u32 ecc6_result;	/* 0x214 */
+	u32 ecc7_result;	/* 0x218 */
+	u32 ecc8_result;	/* 0x21C */
+	u32 ecc9_result;	/* 0x220 */
+	u8 res7[12];		/* 0x224 */
+	u32 testmomde_ctrl;	/* 0x230 */
+	u8 res8[12];		/* 0x234 */
+	struct bch_res_0_3 bch_result_0_3[2];	/* 0x240 */
+};
+
+/* Used for board specific gpmc initialization */
+extern struct gpmc *gpmc_cfg;
+
+#endif /* __ASM_OMAP_GPMC_H */
diff --git a/include/linux/sizes.h b/include/linux/sizes.h
new file mode 100644
index 0000000000..ce3e8150c1
--- /dev/null
+++ b/include/linux/sizes.h
@@ -0,0 +1,47 @@
+/*
+ * include/linux/sizes.h
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#ifndef __LINUX_SIZES_H__
+#define __LINUX_SIZES_H__
+
+#define SZ_1				0x00000001
+#define SZ_2				0x00000002
+#define SZ_4				0x00000004
+#define SZ_8				0x00000008
+#define SZ_16				0x00000010
+#define SZ_32				0x00000020
+#define SZ_64				0x00000040
+#define SZ_128				0x00000080
+#define SZ_256				0x00000100
+#define SZ_512				0x00000200
+
+#define SZ_1K				0x00000400
+#define SZ_2K				0x00000800
+#define SZ_4K				0x00001000
+#define SZ_8K				0x00002000
+#define SZ_16K				0x00004000
+#define SZ_32K				0x00008000
+#define SZ_64K				0x00010000
+#define SZ_128K				0x00020000
+#define SZ_256K				0x00040000
+#define SZ_512K				0x00080000
+
+#define SZ_1M				0x00100000
+#define SZ_2M				0x00200000
+#define SZ_4M				0x00400000
+#define SZ_8M				0x00800000
+#define SZ_16M				0x01000000
+#define SZ_32M				0x02000000
+#define SZ_64M				0x04000000
+#define SZ_128M				0x08000000
+#define SZ_256M				0x10000000
+#define SZ_512M				0x20000000
+
+#define SZ_1G				0x40000000
+#define SZ_2G				0x80000000
+
+#endif /* __LINUX_SIZES_H__ */
diff --git a/include/linux/types.h b/include/linux/types.h
index f07ba41b72..9aebc4e8cf 100644
--- a/include/linux/types.h
+++ b/include/linux/types.h
@@ -1,10 +1,6 @@
 #ifndef _LINUX_TYPES_H
 #define _LINUX_TYPES_H
 
-#ifdef	__KERNEL__
-#include <linux/config.h>
-#endif
-
 #include <linux/posix_types.h>
 #include <asm/types.h>
 #include <stdbool.h>
diff --git a/include/linux/usb/dwc3.h b/include/linux/usb/dwc3.h
new file mode 100644
index 0000000000..97d179a6e9
--- /dev/null
+++ b/include/linux/usb/dwc3.h
@@ -0,0 +1,188 @@
+/* include/linux/usb/dwc3.h
+ *
+ * Copyright (c) 2012 Samsung Electronics Co. Ltd
+ *
+ * Designware SuperSpeed USB 3.0 DRD Controller global and OTG registers
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __DWC3_H_
+#define __DWC3_H_
+
+/* Global constants */
+#define DWC3_ENDPOINTS_NUM			32
+
+#define DWC3_EVENT_BUFFERS_SIZE			PAGE_SIZE
+#define DWC3_EVENT_TYPE_MASK			0xfe
+
+#define DWC3_EVENT_TYPE_DEV			0
+#define DWC3_EVENT_TYPE_CARKIT			3
+#define DWC3_EVENT_TYPE_I2C			4
+
+#define DWC3_DEVICE_EVENT_DISCONNECT		0
+#define DWC3_DEVICE_EVENT_RESET			1
+#define DWC3_DEVICE_EVENT_CONNECT_DONE		2
+#define DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE	3
+#define DWC3_DEVICE_EVENT_WAKEUP		4
+#define DWC3_DEVICE_EVENT_EOPF			6
+#define DWC3_DEVICE_EVENT_SOF			7
+#define DWC3_DEVICE_EVENT_ERRATIC_ERROR		9
+#define DWC3_DEVICE_EVENT_CMD_CMPL		10
+#define DWC3_DEVICE_EVENT_OVERFLOW		11
+
+#define DWC3_GEVNTCOUNT_MASK			0xfffc
+#define DWC3_GSNPSID_MASK			0xffff0000
+#define DWC3_GSNPSID_SHIFT			16
+#define DWC3_GSNPSREV_MASK			0xffff
+
+#define DWC3_REVISION_MASK			0xffff
+
+#define DWC3_REG_OFFSET				0xC100
+
+struct g_event_buffer {
+	u64 g_evntadr;
+	u32 g_evntsiz;
+	u32 g_evntcount;
+};
+
+struct d_physical_endpoint {
+	u32 d_depcmdpar2;
+	u32 d_depcmdpar1;
+	u32 d_depcmdpar0;
+	u32 d_depcmd;
+};
+
+struct dwc3 {					/* offset: 0xC100 */
+	u32 g_sbuscfg0;
+	u32 g_sbuscfg1;
+	u32 g_txthrcfg;
+	u32 g_rxthrcfg;
+	u32 g_ctl;
+
+	u32 reserved1;
+
+	u32 g_sts;
+
+	u32 reserved2;
+
+	u32 g_snpsid;
+	u32 g_gpio;
+	u32 g_uid;
+	u32 g_uctl;
+	u64 g_buserraddr;
+	u64 g_prtbimap;
+
+	u32 g_hwparams0;
+	u32 g_hwparams1;
+	u32 g_hwparams2;
+	u32 g_hwparams3;
+	u32 g_hwparams4;
+	u32 g_hwparams5;
+	u32 g_hwparams6;
+	u32 g_hwparams7;
+
+	u32 g_dbgfifospace;
+	u32 g_dbgltssm;
+	u32 g_dbglnmcc;
+	u32 g_dbgbmu;
+	u32 g_dbglspmux;
+	u32 g_dbglsp;
+	u32 g_dbgepinfo0;
+	u32 g_dbgepinfo1;
+
+	u64 g_prtbimap_hs;
+	u64 g_prtbimap_fs;
+
+	u32 reserved3[28];
+
+	u32 g_usb2phycfg[16];
+	u32 g_usb2i2cctl[16];
+	u32 g_usb2phyacc[16];
+	u32 g_usb3pipectl[16];
+
+	u32 g_txfifosiz[32];
+	u32 g_rxfifosiz[32];
+
+	struct g_event_buffer g_evnt_buf[32];
+
+	u32 g_hwparams8;
+
+	u32 reserved4[63];
+
+	u32 d_cfg;
+	u32 d_ctl;
+	u32 d_evten;
+	u32 d_sts;
+	u32 d_gcmdpar;
+	u32 d_gcmd;
+
+	u32 reserved5[2];
+
+	u32 d_alepena;
+
+	u32 reserved6[55];
+
+	struct d_physical_endpoint d_phy_ep_cmd[32];
+
+	u32 reserved7[128];
+
+	u32 o_cfg;
+	u32 o_ctl;
+	u32 o_evt;
+	u32 o_evten;
+	u32 o_sts;
+
+	u32 reserved8[3];
+
+	u32 adp_cfg;
+	u32 adp_ctl;
+	u32 adp_evt;
+	u32 adp_evten;
+
+	u32 bc_cfg;
+
+	u32 reserved9;
+
+	u32 bc_evt;
+	u32 bc_evten;
+};
+
+/* Global Configuration Register */
+#define DWC3_GCTL_PWRDNSCALE(n)			((n) << 19)
+#define DWC3_GCTL_U2RSTECN			(1 << 16)
+#define DWC3_GCTL_RAMCLKSEL(x)			\
+		(((x) & DWC3_GCTL_CLK_MASK) << 6)
+#define DWC3_GCTL_CLK_BUS			(0)
+#define DWC3_GCTL_CLK_PIPE			(1)
+#define DWC3_GCTL_CLK_PIPEHALF			(2)
+#define DWC3_GCTL_CLK_MASK			(3)
+#define DWC3_GCTL_PRTCAP(n)			(((n) & (3 << 12)) >> 12)
+#define DWC3_GCTL_PRTCAPDIR(n)			((n) << 12)
+#define DWC3_GCTL_PRTCAP_HOST			1
+#define DWC3_GCTL_PRTCAP_DEVICE			2
+#define DWC3_GCTL_PRTCAP_OTG			3
+#define DWC3_GCTL_CORESOFTRESET			(1 << 11)
+#define DWC3_GCTL_SCALEDOWN(n)			((n) << 4)
+#define DWC3_GCTL_SCALEDOWN_MASK		DWC3_GCTL_SCALEDOWN(3)
+#define DWC3_GCTL_DISSCRAMBLE			(1 << 3)
+#define DWC3_GCTL_DSBLCLKGTNG			(1 << 0)
+
+/* Global HWPARAMS1 Register */
+#define DWC3_GHWPARAMS1_EN_PWROPT(n)		(((n) & (3 << 24)) >> 24)
+#define DWC3_GHWPARAMS1_EN_PWROPT_NO		0
+#define DWC3_GHWPARAMS1_EN_PWROPT_CLK		1
+
+/* Global USB2 PHY Configuration Register */
+#define DWC3_GUSB2PHYCFG_PHYSOFTRST		(1 << 31)
+#define DWC3_GUSB2PHYCFG_SUSPHY			(1 << 6)
+
+/* Global USB3 PIPE Control Register */
+#define DWC3_GUSB3PIPECTL_PHYSOFTRST		(1 << 31)
+#define DWC3_GUSB3PIPECTL_SUSPHY		(1 << 17)
+
+/* Global TX Fifo Size Register */
+#define DWC3_GTXFIFOSIZ_TXFDEF(n)		((n) & 0xffff)
+#define DWC3_GTXFIFOSIZ_TXFSTADDR(n)		((n) & 0xffff0000)
+
+#endif /* __DWC3_H_ */
diff --git a/include/linux/usb/xhci-omap.h b/include/linux/usb/xhci-omap.h
new file mode 100644
index 0000000000..82630adc71
--- /dev/null
+++ b/include/linux/usb/xhci-omap.h
@@ -0,0 +1,140 @@
+/*
+ * (C) Copyright 2013
+ * Texas Instruments Inc, <www.ti.com>
+ *
+ * Author: Dan Murphy <dmurphy@ti.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _ASM_ARCH_XHCI_OMAP_H_
+#define _ASM_ARCH_XHCI_OMAP_H_
+
+#ifdef CONFIG_DRA7XX
+#define OMAP_XHCI_BASE 0x488d0000
+#define OMAP_OCP1_SCP_BASE 0x4A081000
+#define OMAP_OTG_WRAPPER_BASE 0x488c0000
+#elif defined CONFIG_AM43XX
+#define OMAP_XHCI_BASE 0x483d0000
+#define OMAP_OCP1_SCP_BASE 0x483E8000
+#define OMAP_OTG_WRAPPER_BASE 0x483dc100
+#else
+/* Default to the OMAP5 XHCI defines */
+#define OMAP_XHCI_BASE 0x4a030000
+#define OMAP_OCP1_SCP_BASE 0x4a084c00
+#define OMAP_OTG_WRAPPER_BASE 0x4A020000
+#endif
+
+/* Phy register MACRO definitions */
+#define	PLL_REGM_MASK		0x001FFE00
+#define	PLL_REGM_SHIFT		0x9
+#define	PLL_REGM_F_MASK		0x0003FFFF
+#define	PLL_REGM_F_SHIFT	0x0
+#define	PLL_REGN_MASK		0x000001FE
+#define	PLL_REGN_SHIFT		0x1
+#define	PLL_SELFREQDCO_MASK	0x0000000E
+#define	PLL_SELFREQDCO_SHIFT	0x1
+#define	PLL_SD_MASK		0x0003FC00
+#define	PLL_SD_SHIFT		0x9
+#define	SET_PLL_GO		0x1
+#define	PLL_TICOPWDN		0x10000
+#define	PLL_LOCK		0x2
+#define	PLL_IDLE		0x1
+
+#define USB3_PWRCTL_CLK_CMD_MASK	0x3FE000
+#define USB3_PWRCTL_CLK_FREQ_MASK	0xFFC
+#define USB3_PHY_PARTIAL_RX_POWERON     (1 << 6)
+#define USB3_PHY_RX_POWERON		(1 << 14)
+#define USB3_PHY_TX_POWERON		(1 << 15)
+#define USB3_PHY_TX_RX_POWERON	(USB3_PHY_RX_POWERON | USB3_PHY_TX_POWERON)
+#define USB3_PWRCTL_CLK_CMD_SHIFT   14
+#define USB3_PWRCTL_CLK_FREQ_SHIFT	22
+
+/* USBOTGSS_WRAPPER definitions */
+#define USBOTGSS_WRAPRESET	(1 << 17)
+#define USBOTGSS_DMADISABLE (1 << 16)
+#define USBOTGSS_STANDBYMODE_NO_STANDBY (1 << 4)
+#define USBOTGSS_STANDBYMODE_SMRT		(1 << 5)
+#define USBOTGSS_STANDBYMODE_SMRT_WKUP (0x3 << 4)
+#define USBOTGSS_IDLEMODE_NOIDLE (1 << 2)
+#define USBOTGSS_IDLEMODE_SMRT (1 << 3)
+#define USBOTGSS_IDLEMODE_SMRT_WKUP (0x3 << 2)
+
+/* USBOTGSS_IRQENABLE_SET_0 bit */
+#define USBOTGSS_COREIRQ_EN	(1 << 0)
+
+/* USBOTGSS_IRQENABLE_SET_1 bits */
+#define USBOTGSS_IRQ_SET_1_IDPULLUP_FALL_EN	(1 << 0)
+#define USBOTGSS_IRQ_SET_1_DISCHRGVBUS_FALL_EN	(1 << 3)
+#define USBOTGSS_IRQ_SET_1_CHRGVBUS_FALL_EN	(1 << 4)
+#define USBOTGSS_IRQ_SET_1_DRVVBUS_FALL_EN	(1 << 5)
+#define USBOTGSS_IRQ_SET_1_IDPULLUP_RISE_EN	(1 << 8)
+#define USBOTGSS_IRQ_SET_1_DISCHRGVBUS_RISE_EN	(1 << 11)
+#define USBOTGSS_IRQ_SET_1_CHRGVBUS_RISE_EN	(1 << 12)
+#define USBOTGSS_IRQ_SET_1_DRVVBUS_RISE_EN	(1 << 13)
+#define USBOTGSS_IRQ_SET_1_OEVT_EN	(1 << 16)
+#define USBOTGSS_IRQ_SET_1_DMADISABLECLR_EN	(1 << 17)
+
+/*
+ * USBOTGSS_WRAPPER registers
+ */
+struct omap_dwc_wrapper {
+	u32 revision;
+
+	u32 reserve_1[3];
+
+	u32 sysconfig; /* offset of 0x10 */
+
+	u32 reserve_2[3];
+	u16 reserve_3;
+
+	u32 irqstatus_raw_0; /* offset of 0x24 */
+	u32 irqstatus_0;
+	u32 irqenable_set_0;
+	u32 irqenable_clr_0;
+
+	u32 irqstatus_raw_1; /* offset of 0x34 */
+	u32 irqstatus_1;
+	u32 irqenable_set_1;
+	u32 irqenable_clr_1;
+
+	u32 reserve_4[15];
+
+	u32 utmi_otg_ctrl; /* offset of 0x80 */
+	u32 utmi_otg_status;
+
+	u32 reserve_5[30];
+
+	u32 mram_offset; /* offset of 0x100 */
+	u32 fladj;
+	u32 dbg_config;
+	u32 dbg_data;
+	u32 dev_ebc_en;
+};
+
+/* XHCI PHY register structure */
+struct omap_usb3_phy {
+	u32 reserve1;
+	u32 pll_status;
+	u32 pll_go;
+	u32 pll_config_1;
+	u32 pll_config_2;
+	u32 pll_config_3;
+	u32 pll_ssc_config_1;
+	u32 pll_ssc_config_2;
+	u32 pll_config_4;
+};
+
+struct omap_xhci {
+	struct omap_dwc_wrapper *otg_wrapper;
+	struct omap_usb3_phy *usb3_phy;
+	struct xhci_hccr *hcd;
+	struct dwc3 *dwc3_reg;
+};
+
+/* USB PHY functions */
+void omap_enable_phy(struct omap_xhci *omap);
+void omap_reset_usb_phy(struct dwc3 *dwc3_reg);
+void usb_phy_power(int on);
+
+#endif /* _ASM_ARCH_XHCI_OMAP_H_ */
diff --git a/include/mmc.h b/include/mmc.h
index 214b9edc8d..42d01251b5 100644
--- a/include/mmc.h
+++ b/include/mmc.h
@@ -148,7 +148,9 @@
  * EXT_CSD fields
  */
 #define EXT_CSD_GP_SIZE_MULT		143	/* R/W */
+#define EXT_CSD_PARTITIONS_ATTRIBUTE	156	/* R/W */
 #define EXT_CSD_PARTITIONING_SUPPORT	160	/* RO */
+#define EXT_CSD_RST_N_FUNCTION		162	/* R/W */
 #define EXT_CSD_RPMB_MULT		168	/* RO */
 #define EXT_CSD_ERASE_GROUP_DEF		175	/* R/W */
 #define EXT_CSD_BOOT_BUS_WIDTH		177
@@ -186,6 +188,9 @@
 #define EXT_CSD_BOOT_PART_NUM(x)	(x << 3)
 #define EXT_CSD_PARTITION_ACCESS(x)	(x << 0)
 
+#define EXT_CSD_BOOT_BUS_WIDTH_MODE(x)	(x << 3)
+#define EXT_CSD_BOOT_BUS_WIDTH_RESET(x)	(x << 2)
+#define EXT_CSD_BOOT_BUS_WIDTH_WIDTH(x)	(x)
 
 #define R1_ILLEGAL_COMMAND		(1 << 22)
 #define R1_APP_CMD			(1 << 5)
@@ -210,6 +215,7 @@
 #define MMCPART_NOAVAILABLE	(0xff)
 #define PART_ACCESS_MASK	(0x7)
 #define PART_SUPPORT		(0x1)
+#define PART_ENH_ATTRIB		(0x1f)
 
 /* Maximum block size for MMC */
 #define MMC_MAX_BLOCK_LEN	512
@@ -245,21 +251,43 @@ struct mmc_data {
 	uint blocksize;
 };
 
+/* forward decl. */
+struct mmc;
+
+struct mmc_ops {
+	int (*send_cmd)(struct mmc *mmc,
+			struct mmc_cmd *cmd, struct mmc_data *data);
+	void (*set_ios)(struct mmc *mmc);
+	int (*init)(struct mmc *mmc);
+	int (*getcd)(struct mmc *mmc);
+	int (*getwp)(struct mmc *mmc);
+};
+
+struct mmc_config {
+	const char *name;
+	const struct mmc_ops *ops;
+	uint host_caps;
+	uint voltages;
+	uint f_min;
+	uint f_max;
+	uint b_max;
+	unsigned char part_type;
+};
+
+/* TODO struct mmc should be in mmc_private but it's hard to fix right now */
 struct mmc {
 	struct list_head link;
-	char name[32];
-	void *priv;
-	uint voltages;
+	const struct mmc_config *cfg;	/* provided configuration */
 	uint version;
+	void *priv;
 	uint has_init;
-	uint f_min;
-	uint f_max;
 	int high_capacity;
 	uint bus_width;
 	uint clock;
 	uint card_caps;
-	uint host_caps;
 	uint ocr;
+	uint dsr;
+	uint dsr_imp;
 	uint scr[2];
 	uint csd[4];
 	uint cid[4];
@@ -276,13 +304,6 @@ struct mmc {
 	u64 capacity_rpmb;
 	u64 capacity_gp[4];
 	block_dev_desc_t block_dev;
-	int (*send_cmd)(struct mmc *mmc,
-			struct mmc_cmd *cmd, struct mmc_data *data);
-	void (*set_ios)(struct mmc *mmc);
-	int (*init)(struct mmc *mmc);
-	int (*getcd)(struct mmc *mmc);
-	int (*getwp)(struct mmc *mmc);
-	uint b_max;
 	char op_cond_pending;	/* 1 if we are waiting on an op_cond command */
 	char init_in_progress;	/* 1 if we have done mmc_start_init() */
 	char preinit;		/* start init as early as possible */
@@ -290,6 +311,8 @@ struct mmc {
 };
 
 int mmc_register(struct mmc *mmc);
+struct mmc *mmc_create(const struct mmc_config *cfg, void *priv);
+void mmc_destroy(struct mmc *mmc);
 int mmc_initialize(bd_t *bis);
 int mmc_init(struct mmc *mmc);
 int mmc_read(struct mmc *mmc, u64 src, uchar *dst, int size);
@@ -302,12 +325,16 @@ int board_mmc_getcd(struct mmc *mmc);
 int mmc_switch_part(int dev_num, unsigned int part_num);
 int mmc_getcd(struct mmc *mmc);
 int mmc_getwp(struct mmc *mmc);
-void spl_mmc_load(void) __noreturn;
+int mmc_set_dsr(struct mmc *mmc, u16 val);
 /* Function to change the size of boot partition and rpmb partitions */
 int mmc_boot_partition_size_change(struct mmc *mmc, unsigned long bootsize,
 					unsigned long rpmbsize);
-/* Function to send commands to open/close the specified boot partition */
-int mmc_boot_part_access(struct mmc *mmc, u8 ack, u8 part_num, u8 access);
+/* Function to modify the PARTITION_CONFIG field of EXT_CSD */
+int mmc_set_part_conf(struct mmc *mmc, u8 ack, u8 part_num, u8 access);
+/* Function to modify the BOOT_BUS_WIDTH field of EXT_CSD */
+int mmc_set_boot_bus_width(struct mmc *mmc, u8 width, u8 reset, u8 mode);
+/* Function to modify the RST_n_FUNCTION field of EXT_CSD */
+int mmc_set_rst_n_function(struct mmc *mmc, u8 enable);
 
 /**
  * Start device initialization and return immediately; it does not block on
@@ -336,7 +363,7 @@ void mmc_set_preinit(struct mmc *mmc, int preinit);
 
 #ifdef CONFIG_GENERIC_MMC
 #ifdef CONFIG_MMC_SPI
-#define mmc_host_is_spi(mmc)	((mmc)->host_caps & MMC_MODE_SPI)
+#define mmc_host_is_spi(mmc)	((mmc)->cfg->host_caps & MMC_MODE_SPI)
 #else
 #define mmc_host_is_spi(mmc)	0
 #endif
@@ -345,4 +372,11 @@ struct mmc *mmc_spi_init(uint bus, uint cs, uint speed, uint mode);
 int mmc_legacy_init(int verbose);
 #endif
 
+int board_mmc_init(bd_t *bis);
+
+/* Set block count limit because of 16 bit register limit on some hardware*/
+#ifndef CONFIG_SYS_MMC_MAX_BLK_COUNT
+#define CONFIG_SYS_MMC_MAX_BLK_COUNT 65535
+#endif
+
 #endif /* _MMC_H_ */
diff --git a/include/msc01.h b/include/msc01.h
new file mode 100644
index 0000000000..37cf963f13
--- /dev/null
+++ b/include/msc01.h
@@ -0,0 +1,135 @@
+/*
+ * Copyright (C) 2013 Imagination Technologies
+ * Author: Paul Burton <paul.burton@imgtec.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __MSC01_H__
+#define __MSC01_H__
+
+/*
+ * Bus Interface Unit
+ */
+
+#define MSC01_BIU_IP1BAS1L_OFS		0x0208
+#define MSC01_BIU_IP1MSK1L_OFS		0x0218
+#define MSC01_BIU_IP1BAS2L_OFS		0x0248
+#define MSC01_BIU_IP1MSK2L_OFS		0x0258
+#define MSC01_BIU_IP2BAS1L_OFS		0x0288
+#define MSC01_BIU_IP2MSK1L_OFS		0x0298
+#define MSC01_BIU_IP2BAS2L_OFS		0x02c8
+#define MSC01_BIU_IP2MSK2L_OFS		0x02d8
+#define MSC01_BIU_IP3BAS1L_OFS		0x0308
+#define MSC01_BIU_IP3MSK1L_OFS		0x0318
+#define MSC01_BIU_IP3BAS2L_OFS		0x0348
+#define MSC01_BIU_IP3MSK2L_OFS		0x0358
+#define MSC01_BIU_MCBAS1L_OFS		0x0388
+#define MSC01_BIU_MCMSK1L_OFS		0x0398
+#define MSC01_BIU_MCBAS2L_OFS		0x03c8
+#define MSC01_BIU_MCMSK2L_OFS		0x03d8
+
+/*
+ * PCI Bridge
+ */
+
+#define MSC01_PCI_SC2PMBASL_OFS		0x0208
+#define MSC01_PCI_SC2PMMSKL_OFS		0x0218
+#define MSC01_PCI_SC2PMMAPL_OFS		0x0228
+#define MSC01_PCI_SC2PIOBASL_OFS	0x0248
+#define MSC01_PCI_SC2PIOMSKL_OFS	0x0258
+#define MSC01_PCI_SC2PIOMAPL_OFS	0x0268
+#define MSC01_PCI_P2SCMSKL_OFS		0x0308
+#define MSC01_PCI_P2SCMAPL_OFS		0x0318
+#define MSC01_PCI_INTSTAT_OFS		0x0608
+#define MSC01_PCI_CFGADDR_OFS		0x0610
+#define MSC01_PCI_CFGDATA_OFS		0x0618
+#define MSC01_PCI_HEAD0_OFS		0x2000
+#define MSC01_PCI_HEAD1_OFS		0x2008
+#define MSC01_PCI_HEAD2_OFS		0x2010
+#define MSC01_PCI_HEAD3_OFS		0x2018
+#define MSC01_PCI_HEAD4_OFS		0x2020
+#define MSC01_PCI_HEAD5_OFS		0x2028
+#define MSC01_PCI_HEAD6_OFS		0x2030
+#define MSC01_PCI_HEAD7_OFS		0x2038
+#define MSC01_PCI_HEAD8_OFS		0x2040
+#define MSC01_PCI_HEAD9_OFS		0x2048
+#define MSC01_PCI_HEAD10_OFS		0x2050
+#define MSC01_PCI_HEAD11_OFS		0x2058
+#define MSC01_PCI_HEAD12_OFS		0x2060
+#define MSC01_PCI_HEAD13_OFS		0x2068
+#define MSC01_PCI_HEAD14_OFS		0x2070
+#define MSC01_PCI_HEAD15_OFS		0x2078
+#define MSC01_PCI_BAR0_OFS		0x2220
+#define MSC01_PCI_CFG_OFS		0x2380
+#define MSC01_PCI_SWAP_OFS		0x2388
+
+#define MSC01_PCI_SC2PMMSKL_MSK_MSK	0xff000000
+#define MSC01_PCI_SC2PIOMSKL_MSK_MSK	0xff000000
+
+#define MSC01_PCI_INTSTAT_TA_SHF	6
+#define MSC01_PCI_INTSTAT_TA_MSK	(0x1 << MSC01_PCI_INTSTAT_TA_SHF)
+#define MSC01_PCI_INTSTAT_MA_SHF	7
+#define MSC01_PCI_INTSTAT_MA_MSK	(0x1 << MSC01_PCI_INTSTAT_MA_SHF)
+
+#define MSC01_PCI_CFGADDR_BNUM_SHF	16
+#define MSC01_PCI_CFGADDR_BNUM_MSK	(0xff << MSC01_PCI_CFGADDR_BNUM_SHF)
+#define MSC01_PCI_CFGADDR_DNUM_SHF	11
+#define MSC01_PCI_CFGADDR_DNUM_MSK	(0x1f << MSC01_PCI_CFGADDR_DNUM_SHF)
+#define MSC01_PCI_CFGADDR_FNUM_SHF	8
+#define MSC01_PCI_CFGADDR_FNUM_MSK	(0x3 << MSC01_PCI_CFGADDR_FNUM_SHF)
+#define MSC01_PCI_CFGADDR_RNUM_SHF	2
+#define MSC01_PCI_CFGADDR_RNUM_MSK	(0x3f << MSC01_PCI_CFGADDR_RNUM_SHF)
+
+#define MSC01_PCI_HEAD0_VENDORID_SHF	0
+#define MSC01_PCI_HEAD0_DEVICEID_SHF	16
+
+#define MSC01_PCI_HEAD2_REV_SHF		0
+#define MSC01_PCI_HEAD2_CLASS_SHF	16
+
+#define MSC01_PCI_CFG_EN_SHF		15
+#define MSC01_PCI_CFG_EN_MSK		(0x1 << MSC01_PCI_CFG_EN_SHF)
+#define MSC01_PCI_CFG_G_SHF		16
+#define MSC01_PCI_CFG_G_MSK		(0x1 << MSC01_PCI_CFG_G_SHF)
+#define MSC01_PCI_CFG_RA_SHF		17
+#define MSC01_PCI_CFG_RA_MSK		(0x1 << MSC01_PCI_CFG_RA_SHF)
+
+#define MSC01_PCI_SWAP_BAR0_BSWAP_SHF	0
+#define MSC01_PCI_SWAP_IO_BSWAP_SHF	18
+
+/*
+ * Peripheral Bus Controller
+ */
+
+#define MSC01_PBC_CLKCFG_OFS		0x0100
+#define MSC01_PBC_CS0CFG_OFS		0x0400
+#define MSC01_PBC_CS0TIM_OFS		0x0500
+#define MSC01_PBC_CS0RW_OFS		0x0600
+
+#define MSC01_PBC_CLKCFG_SHF		0
+#define MSC01_PBC_CLKCFG_MSK		(0x1f << MSC01_PBC_CLKCFG_SHF)
+
+#define MSC01_PBC_CS0CFG_WS_SHF		0
+#define MSC01_PBC_CS0CFG_WS_MSK		(0x1f << MSC01_PBC_CS0CFG_WS_SHF)
+#define MSC01_PBC_CS0CFG_WSIDLE_SHF	8
+#define MSC01_PBC_CS0CFG_WSIDLE_MSK	(0x1f << MSC01_PBC_CS0CFG_WSIDLE_SHF)
+#define MSC01_PBC_CS0CFG_DTYP_SHF	16
+#define MSC01_PBC_CS0CFG_DTYP_MSK	(0x3 << MSC01_PBC_CS0CFG_DTYP_SHF)
+#define MSC01_PBC_CS0CFG_ADM_SHF	20
+#define MSC01_PBC_CS0CFG_ADM_MSK	(0x1 << MSC01_PBC_CS0CFG_ADM_SHF)
+
+#define MSC01_PBC_CS0TIM_CAT_SHF	0
+#define MSC01_PBC_CS0TIM_CAT_MSK	(0x1f << MSC01_PBC_CS0TIM_CAT_SHF)
+#define MSC01_PBC_CS0TIM_CDT_SHF	8
+#define MSC01_PBC_CS0TIM_CDT_MSK	(0x1f << MSC01_PBC_CS0TIM_CDT_SHF)
+
+#define MSC01_PBC_CS0RW_WAT_SHF		0
+#define MSC01_PBC_CS0RW_WAT_MSK		(0x1f << MSC01_PBC_CS0RW_WAT_SHF)
+#define MSC01_PBC_CS0RW_WDT_SHF		8
+#define MSC01_PBC_CS0RW_WDT_MSK		(0x1f << MSC01_PBC_CS0RW_WDT_SHF)
+#define MSC01_PBC_CS0RW_RAT_SHF		16
+#define MSC01_PBC_CS0RW_RAT_MSK		(0x1f << MSC01_PBC_CS0RW_RAT_SHF)
+#define MSC01_PBC_CS0RW_RDT_SHF		24
+#define MSC01_PBC_CS0RW_RDT_MSK		(0x1f << MSC01_PBC_CS0RW_RDT_SHF)
+
+#endif /* __MSC01_H__ */
diff --git a/include/mtd/mtd-abi.h b/include/mtd/mtd-abi.h
index d51c1abd18..ac3c298760 100644
--- a/include/mtd/mtd-abi.h
+++ b/include/mtd/mtd-abi.h
@@ -155,18 +155,6 @@ struct nand_oobfree {
 	uint32_t length;
 };
 
-#define MTD_MAX_OOBFREE_ENTRIES	8
-/*
- * ECC layout control structure. Exported to userspace for
- * diagnosis and to allow creation of raw images
- */
-struct nand_ecclayout {
-	uint32_t eccbytes;
-	uint32_t eccpos[128];
-	uint32_t oobavail;
-	struct nand_oobfree oobfree[MTD_MAX_OOBFREE_ENTRIES];
-};
-
 /**
  * struct mtd_ecc_stats - error correction stats
  *
diff --git a/include/nand.h b/include/nand.h
index 84116f4937..fc735d1ec4 100644
--- a/include/nand.h
+++ b/include/nand.h
@@ -21,10 +21,16 @@
  * at the same time, so do it here.  When all drivers are
  * converted, this will go away.
  */
+#ifdef CONFIG_SPL_BUILD
+#if defined(CONFIG_NAND_FSL_ELBC) || defined(CONFIG_NAND_FSL_IFC)
+#define CONFIG_SYS_NAND_SELF_INIT
+#endif
+#else
 #if defined(CONFIG_NAND_FSL_ELBC) || defined(CONFIG_NAND_ATMEL)\
 	|| defined(CONFIG_NAND_FSL_IFC)
 #define CONFIG_SYS_NAND_SELF_INIT
 #endif
+#endif
 
 extern void nand_init(void);
 
diff --git a/include/net.h b/include/net.h
index 5aedc17aa6..0802fad876 100644
--- a/include/net.h
+++ b/include/net.h
@@ -89,7 +89,7 @@ struct eth_device {
 	int  (*recv) (struct eth_device *);
 	void (*halt) (struct eth_device *);
 #ifdef CONFIG_MCAST_TFTP
-	int (*mcast) (struct eth_device *, u32 ip, u8 set);
+	int (*mcast) (struct eth_device *, const u8 *enetaddr, u8 set);
 #endif
 	int  (*write_hwaddr) (struct eth_device *);
 	struct eth_device *next;
diff --git a/include/netdev.h b/include/netdev.h
index 47fa80d6fc..32b5073ef0 100644
--- a/include/netdev.h
+++ b/include/netdev.h
@@ -36,7 +36,7 @@ int calxedaxgmac_initialize(u32 id, ulong base_addr);
 int cs8900_initialize(u8 dev_num, int base_addr);
 int davinci_emac_initialize(void);
 int dc21x4x_initialize(bd_t *bis);
-int designware_initialize(u32 id, ulong base_addr, u32 phy_addr, u32 interface);
+int designware_initialize(ulong base_addr, u32 interface);
 int dm9000_initialize(bd_t *bis);
 int dnet_eth_initialize(int id, void *regs, unsigned int phy_addr);
 int e1000_initialize(bd_t *bis);
@@ -86,10 +86,12 @@ int uli526x_initialize(bd_t *bis);
 int armada100_fec_register(unsigned long base_addr);
 int xilinx_axiemac_initialize(bd_t *bis, unsigned long base_addr,
 							unsigned long dma_addr);
+int xilinx_emaclite_of_init(const void *blob);
 int xilinx_emaclite_initialize(bd_t *bis, unsigned long base_addr,
 							int txpp, int rxpp);
 int xilinx_ll_temac_eth_init(bd_t *bis, unsigned long base_addr, int flags,
 						unsigned long ctrl_addr);
+int zynq_gem_of_init(const void *blob);
 int zynq_gem_initialize(bd_t *bis, int base_addr, int phy_addr, u32 emio);
 /*
  * As long as the Xilinx xps_ll_temac ethernet driver has not its own interface
diff --git a/include/os.h b/include/os.h
index 8665f70edb..0230a7f40d 100644
--- a/include/os.h
+++ b/include/os.h
@@ -11,6 +11,8 @@
 #ifndef __OS_H__
 #define __OS_H__
 
+#include <linux/types.h>
+
 struct sandbox_state;
 
 /**
@@ -82,6 +84,14 @@ int os_open(const char *pathname, int flags);
 int os_close(int fd);
 
 /**
+ * Access to the OS unlink() system call
+ *
+ * \param pathname Path of file to delete
+ * \return 0 for success, other for error
+ */
+int os_unlink(const char *pathname);
+
+/**
  * Access to the OS exit() system call
  *
  * This exits with the supplied return code, which should be 0 to indicate
@@ -93,8 +103,12 @@ void os_exit(int exit_code) __attribute__((noreturn));
 
 /**
  * Put tty into raw mode to mimic serial console better
+ *
+ * @param fd		File descriptor of stdin (normally 0)
+ * @param allow_sigs	Allow Ctrl-C, Ctrl-Z to generate signals rather than
+ *			be handled by U-Boot
  */
-void os_tty_raw(int fd);
+void os_tty_raw(int fd, bool allow_sigs);
 
 /**
  * Acquires some memory from the underlying os.
@@ -105,6 +119,35 @@ void os_tty_raw(int fd);
 void *os_malloc(size_t length);
 
 /**
+ * Free memory previous allocated with os_malloc()/os_realloc()
+ *
+ * This returns the memory to the OS.
+ *
+ * \param ptr		Pointer to memory block to free
+ */
+void os_free(void *ptr);
+
+/**
+ * Reallocate previously-allocated memory to increase/decrease space
+ *
+ * This works in a similar way to the C library realloc() function. If
+ * length is 0, then ptr is freed. Otherwise the space used by ptr is
+ * expanded or reduced depending on whether length is larger or smaller
+ * than before.
+ *
+ * If ptr is NULL, then this is similar to calling os_malloc().
+ *
+ * This function may need to move the memory block to make room for any
+ * extra space, in which case the new pointer is returned.
+ *
+ * \param ptr		Pointer to memory block to reallocate
+ * \param length	New length for memory block
+ * \return pointer to new memory block, or NULL on failure or if length
+ *	is 0.
+ */
+void *os_realloc(void *ptr, size_t length);
+
+/**
  * Access to the usleep function of the os
  *
  * \param usec Time to sleep in micro seconds
@@ -116,7 +159,7 @@ void os_usleep(unsigned long usec);
  *
  * \return A monotonic increasing time scaled in nano seconds
  */
-u64 os_get_nsec(void);
+uint64_t os_get_nsec(void);
 
 /**
  * Parse arguments and update sandbox state.
@@ -178,4 +221,59 @@ const char *os_dirent_get_typename(enum os_dirent_t type);
  */
 ssize_t os_get_filesize(const char *fname);
 
+/**
+ * Write a character to the controlling OS terminal
+ *
+ * This bypasses the U-Boot console support and writes directly to the OS
+ * stdout file descriptor.
+ *
+ * @param ch	Character to write
+ */
+void os_putc(int ch);
+
+/**
+ * Write a string to the controlling OS terminal
+ *
+ * This bypasses the U-Boot console support and writes directly to the OS
+ * stdout file descriptor.
+ *
+ * @param str	String to write (note that \n is not appended)
+ */
+void os_puts(const char *str);
+
+/**
+ * Write the sandbox RAM buffer to a existing file
+ *
+ * @param fname		Filename to write memory to (simple binary format)
+ * @return 0 if OK, -ve on error
+ */
+int os_write_ram_buf(const char *fname);
+
+/**
+ * Read the sandbox RAM buffer from an existing file
+ *
+ * @param fname		Filename containing memory (simple binary format)
+ * @return 0 if OK, -ve on error
+ */
+int os_read_ram_buf(const char *fname);
+
+/**
+ * Jump to a new executable image
+ *
+ * This uses exec() to run a new executable image, after putting it in a
+ * temporary file. The same arguments and environment are passed to this
+ * new image, with the addition of:
+ *
+ *	-j <filename>	Specifies the filename the image was written to. The
+ *			calling image may want to delete this at some point.
+ *	-m <filename>	Specifies the file containing the sandbox memory
+ *			(ram_buf) from this image, so that the new image can
+ *			have access to this. It also means that the original
+ *			memory filename passed to U-Boot will be left intact.
+ *
+ * @param dest		Buffer containing executable image
+ * @param size		Size of buffer
+ */
+int os_jump_to_image(const void *dest, int size);
+
 #endif
diff --git a/include/palmas.h b/include/palmas.h
index f74f08e2d8..eaf367086c 100644
--- a/include/palmas.h
+++ b/include/palmas.h
@@ -31,6 +31,7 @@
 /* LDOUSB control/voltage */
 #define LDOUSB_CTRL		0x64
 #define LDOUSB_VOLTAGE		0x65
+#define LDO_CTRL		0x6a
 
 /* Control of 32 kHz audio clock */
 #define CLK32KGAUDIO_CTRL	0xd5
@@ -62,6 +63,10 @@
 #define SMPS9_CTRL		0x38
 #define SMPS9_VOLTAGE		0x3b
 
+/* SMPS10_CTRL */
+#define SMPS10_CTRL		0x3c
+#define SMPS10_MODE_ACTIVE_D	0x0d
+
 /* Bit field definitions for SMPSx_CTRL */
 #define SMPS_MODE_ACT_AUTO	1
 #define SMPS_MODE_ACT_ECO	2
@@ -114,5 +119,6 @@ int palmas_mmc1_poweron_ldo(void);
 int twl603x_mmc1_set_ldo9(u8 vsel);
 int twl603x_audio_power(u8 on);
 int twl603x_enable_bb_charge(u8 bb_fields);
+int palmas_enable_ss_ldo(void);
 
 #endif /* PALMAS_H */
diff --git a/include/part.h b/include/part.h
index ce840bd841..4beb6db89b 100644
--- a/include/part.h
+++ b/include/part.h
@@ -58,6 +58,8 @@ typedef struct block_dev_desc {
 #define IF_TYPE_MMC		6
 #define IF_TYPE_SD		7
 #define IF_TYPE_SATA		8
+#define IF_TYPE_HOST		9
+#define IF_TYPE_MAX		10	/* Max number of IF_TYPE_* supported */
 
 /* Part types */
 #define PART_TYPE_UNKNOWN	0x00
@@ -102,6 +104,8 @@ block_dev_desc_t* usb_stor_get_dev(int dev);
 block_dev_desc_t* mmc_get_dev(int dev);
 block_dev_desc_t* systemace_get_dev(int dev);
 block_dev_desc_t* mg_disk_get_dev(int dev);
+block_dev_desc_t *host_get_dev(int dev);
+int host_get_dev_err(int dev, block_dev_desc_t **blk_devp);
 
 /* disk/part.c */
 int get_partition_info (block_dev_desc_t * dev_desc, int part, disk_partition_t *info);
@@ -123,6 +127,7 @@ static inline block_dev_desc_t* usb_stor_get_dev(int dev) { return NULL; }
 static inline block_dev_desc_t* mmc_get_dev(int dev) { return NULL; }
 static inline block_dev_desc_t* systemace_get_dev(int dev) { return NULL; }
 static inline block_dev_desc_t* mg_disk_get_dev(int dev) { return NULL; }
+static inline block_dev_desc_t *host_get_dev(int dev) { return NULL; }
 
 static inline int get_partition_info (block_dev_desc_t * dev_desc, int part,
 	disk_partition_t *info) { return -1; }
diff --git a/include/pci.h b/include/pci.h
index 911ba89ac3..461f17c058 100644
--- a/include/pci.h
+++ b/include/pci.h
@@ -410,10 +410,15 @@
 #define PCI_MAX_PCI_DEVICES	32
 #define PCI_MAX_PCI_FUNCTIONS	8
 
+#define PCI_FIND_CAP_TTL 0x48
+#define CAP_START_POS 0x40
+
 /* Include the ID list */
 
 #include <pci_ids.h>
 
+#ifndef __ASSEMBLY__
+
 #ifdef CONFIG_SYS_PCI_64BIT
 typedef u64 pci_addr_t;
 typedef u64 pci_size_t;
@@ -647,6 +652,13 @@ extern int pci_hose_config_device(struct pci_controller *hose,
 				  pci_addr_t mem,
 				  unsigned long command);
 
+extern int pci_hose_find_capability(struct pci_controller *hose, pci_dev_t dev,
+				    int cap);
+extern int pci_hose_find_cap_start(struct pci_controller *hose, pci_dev_t dev,
+				   u8 hdr_type);
+extern int pci_find_cap(struct pci_controller *hose, pci_dev_t dev, int pos,
+			int cap);
+
 const char * pci_class_str(u8 class);
 int pci_last_busno(void);
 
@@ -657,4 +669,6 @@ extern void pci_mpc824x_init (struct pci_controller *hose);
 #ifdef CONFIG_MPC85xx
 extern void pci_mpc85xx_init (struct pci_controller *hose);
 #endif
-#endif	/* _PCI_H */
+
+#endif /* __ASSEMBLY__ */
+#endif /* _PCI_H */
diff --git a/include/pci_ids.h b/include/pci_ids.h
index 2c6dfd4044..6bab677449 100644
--- a/include/pci_ids.h
+++ b/include/pci_ids.h
@@ -2170,6 +2170,9 @@
 #define PCI_DEVICE_ID_ENE_720		0x1421
 #define PCI_DEVICE_ID_ENE_722		0x1422
 
+#define PCI_VENDOR_ID_MIPS		0x153f
+#define PCI_DEVICE_ID_MIPS_MSC01	0x0001
+
 #define PCI_SUBVENDOR_ID_PERLE          0x155f
 #define PCI_SUBDEVICE_ID_PCI_RAS4       0xf001
 #define PCI_SUBDEVICE_ID_PCI_RAS8       0xf010
diff --git a/include/pci_msc01.h b/include/pci_msc01.h
new file mode 100644
index 0000000000..54945a7a8f
--- /dev/null
+++ b/include/pci_msc01.h
@@ -0,0 +1,17 @@
+/*
+ * Copyright (C) 2013 Imagination Technologies
+ * Author: Paul Burton <paul.burton@imgtec.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __PCI_MSC01_H__
+#define __PCI_MSC01_H__
+
+extern void msc01_pci_init(void *base, unsigned long sys_bus,
+			   unsigned long sys_phys, unsigned long sys_size,
+			   unsigned long mem_bus, unsigned long mem_phys,
+			   unsigned long mem_size, unsigned long io_bus,
+			   unsigned long io_phys, unsigned long io_size);
+
+#endif /* __PCI_MSC01_H__ */
diff --git a/include/phy.h b/include/phy.h
index f0f522a9c2..d3ecd6378b 100644
--- a/include/phy.h
+++ b/include/phy.h
@@ -125,6 +125,9 @@ struct phy_driver {
 	/* Called when bringing down the controller */
 	int (*shutdown)(struct phy_device *phydev);
 
+	int (*readext)(struct phy_device *phydev, int addr, int devad, int reg);
+	int (*writeext)(struct phy_device *phydev, int addr, int devad, int reg,
+			u16 val);
 	struct list_head list;
 };
 
@@ -160,6 +163,14 @@ struct phy_device {
 	u32 flags;
 };
 
+struct fixed_link {
+	int phy_id;
+	int duplex;
+	int link_speed;
+	int pause;
+	int asym_pause;
+};
+
 static inline int phy_read(struct phy_device *phydev, int devad, int regnum)
 {
 	struct mii_dev *bus = phydev->bus;
@@ -223,6 +234,8 @@ int phy_smsc_init(void);
 int phy_teranetics_init(void);
 int phy_vitesse_init(void);
 
+int board_phy_config(struct phy_device *phydev);
+
 /* PHY UIDs for various PHYs that are referenced in external code */
 #define PHY_UID_TN2020	0x00a19410
 
diff --git a/include/power/max77686_pmic.h b/include/power/max77686_pmic.h
index 16e9016089..c2a772a895 100644
--- a/include/power/max77686_pmic.h
+++ b/include/power/max77686_pmic.h
@@ -8,6 +8,8 @@
 #ifndef __MAX77686_H_
 #define __MAX77686_H_
 
+#include <power/pmic.h>
+
 enum {
 	MAX77686_REG_PMIC_ID		= 0x0,
 	MAX77686_REG_PMIC_INTSRC,
diff --git a/include/power/pfuze100_pmic.h b/include/power/pfuze100_pmic.h
new file mode 100644
index 0000000000..2a9032a1f9
--- /dev/null
+++ b/include/power/pfuze100_pmic.h
@@ -0,0 +1,96 @@
+/*
+ *  Copyright (C) 2014 Gateworks Corporation
+ *  Tim Harvey <tharvey@gateworks.com>
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#ifndef __PFUZE100_PMIC_H_
+#define __PFUZE100_PMIC_H_
+
+/* PFUZE100 registers */
+enum {
+	PFUZE100_DEVICEID	= 0x00,
+	PFUZE100_REVID		= 0x03,
+	PFUZE100_FABID		= 0x04,
+
+	PFUZE100_SW1ABVOL	= 0x20,
+	PFUZE100_SW1CVOL	= 0x2e,
+	PFUZE100_SW2VOL		= 0x35,
+	PFUZE100_SW3AVOL	= 0x3c,
+	PFUZE100_SW3BVOL	= 0x43,
+	PFUZE100_SW4VOL		= 0x4a,
+	PFUZE100_SWBSTCON1	= 0x66,
+	PFUZE100_VREFDDRCON	= 0x6a,
+	PFUZE100_VSNVSVOL	= 0x6b,
+	PFUZE100_VGEN1VOL	= 0x6c,
+	PFUZE100_VGEN2VOL	= 0x6d,
+	PFUZE100_VGEN3VOL	= 0x6e,
+	PFUZE100_VGEN4VOL	= 0x6f,
+	PFUZE100_VGEN5VOL	= 0x70,
+	PFUZE100_VGEN6VOL	= 0x71,
+
+	PMIC_NUM_OF_REGS	= 0x7f,
+};
+
+/*
+ * LDO Configuration
+ */
+
+/* VGEN1/2 Voltage Configuration */
+#define LDOA_0_80V	0
+#define LDOA_0_85V	1
+#define LDOA_0_90V	2
+#define LDOA_0_95V	3
+#define LDOA_1_00V	4
+#define LDOA_1_05V	5
+#define LDOA_1_10V	6
+#define LDOA_1_15V	7
+#define LDOA_1_20V	8
+#define LDOA_1_25V	9
+#define LDOA_1_30V	10
+#define LDOA_1_35V	11
+#define LDOA_1_40V	12
+#define LDOA_1_45V	13
+#define LDOA_1_50V	14
+#define LDOA_1_55V	15
+
+/* VGEN3/4/5/6 Voltage Configuration */
+#define LDOB_1_80V	0
+#define LDOB_1_90V	1
+#define LDOB_2_00V	2
+#define LDOB_2_10V	3
+#define LDOB_2_20V	4
+#define LDOB_2_30V	5
+#define LDOB_2_40V	6
+#define LDOB_2_50V	7
+#define LDOB_2_60V	8
+#define LDOB_2_70V	9
+#define LDOB_2_80V	10
+#define LDOB_2_90V	11
+#define LDOB_3_00V	12
+#define LDOB_3_10V	13
+#define LDOB_3_20V	14
+#define LDOB_3_30V	15
+
+#define LDO_VOL_MASK	0xf
+#define LDO_EN		4
+
+/*
+ * Boost Regulator
+ */
+
+/* SWBST Output Voltage */
+#define SWBST_5_00V	0
+#define SWBST_5_05V	1
+#define SWBST_5_10V	2
+#define SWBST_5_15V	3
+
+#define SWBST_VOL_MASK	0x3
+#define SWBST_MODE_MASK	0x6
+#define SWBST_MODE_OFF	(2 << 0)
+#define SWBST_MODE_PFM	(2 << 1)
+#define SWBST_MODE_AUTO	(2 << 2)
+#define SWBST_MODE_APS	(2 << 3)
+
+#endif
diff --git a/include/power/pmic.h b/include/power/pmic.h
index 0e7aa31492..8f282dd2f2 100644
--- a/include/power/pmic.h
+++ b/include/power/pmic.h
@@ -8,7 +8,6 @@
 #ifndef __CORE_PMIC_H_
 #define __CORE_PMIC_H_
 
-#include <common.h>
 #include <linux/list.h>
 #include <i2c.h>
 #include <power/power_chrg.h>
diff --git a/include/ppc_asm.tmpl b/include/ppc_asm.tmpl
index 331b666459..5fcef9cebb 100644
--- a/include/ppc_asm.tmpl
+++ b/include/ppc_asm.tmpl
@@ -135,7 +135,7 @@
 
 #define PLPRCR	0x00000284
 
-#elif defined(CONFIG_8260)
+#elif defined(CONFIG_MPC8260)
 
 #define HID2		1011
 
diff --git a/include/samsung/misc.h b/include/samsung/misc.h
new file mode 100644
index 0000000000..ede6c1583a
--- /dev/null
+++ b/include/samsung/misc.h
@@ -0,0 +1,29 @@
+#ifndef __SAMSUNG_MISC_COMMON_H__
+#define __SAMSUNG_MISC_COMMON_H__
+
+#ifdef CONFIG_REVISION_TAG
+u32 get_board_rev(void);
+#endif
+
+#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+void set_board_info(void);
+#endif
+
+#ifdef CONFIG_LCD_MENU
+enum {
+	BOOT_MODE_INFO,
+	BOOT_MODE_THOR,
+	BOOT_MODE_UMS,
+	BOOT_MODE_DFU,
+	BOOT_MODE_EXIT,
+};
+
+void keys_init(void);
+void check_boot_mode(void);
+#endif /* CONFIG_LCD_MENU */
+
+#ifdef CONFIG_CMD_BMP
+void draw_logo(void);
+#endif
+
+#endif /* __SAMSUNG_MISC_COMMON_H__ */
diff --git a/include/sandboxblockdev.h b/include/sandboxblockdev.h
new file mode 100644
index 0000000000..627787aa32
--- /dev/null
+++ b/include/sandboxblockdev.h
@@ -0,0 +1,18 @@
+/*
+ * Copyright (c) 2013, Henrik Nordstrom <henrik@henriknordstrom.net>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __SANDBOX_BLOCK_DEV__
+#define __SANDBOX_BLOCK_DEV__
+
+struct host_block_dev {
+	block_dev_desc_t blk_dev;
+	char *filename;
+	int fd;
+};
+
+int host_dev_bind(int dev, char *filename);
+
+#endif
diff --git a/include/sandboxfs.h b/include/sandboxfs.h
index 8ea8cb7e2e..a51ad13044 100644
--- a/include/sandboxfs.h
+++ b/include/sandboxfs.h
@@ -25,6 +25,7 @@ long sandbox_fs_read_at(const char *filename, unsigned long pos,
 
 void sandbox_fs_close(void);
 int sandbox_fs_ls(const char *dirname);
+int sandbox_fs_exists(const char *filename);
 int fs_read_sandbox(const char *filename, void *buf, int offset, int len);
 int fs_write_sandbox(const char *filename, void *buf, int offset, int len);
 
diff --git a/include/scf0403_lcd.h b/include/scf0403_lcd.h
new file mode 100644
index 0000000000..d71896bbda
--- /dev/null
+++ b/include/scf0403_lcd.h
@@ -0,0 +1,11 @@
+/*
+ * Copyright (c) 2013, Compulab Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+#ifndef SCF0403_LCD_H_
+#define SCF0403_LCD_H_
+
+int scf0403_init(int reset_gpio);
+
+#endif
diff --git a/include/sdhci.h b/include/sdhci.h
index 74d06ae18a..aa4a0e9654 100644
--- a/include/sdhci.h
+++ b/include/sdhci.h
@@ -12,6 +12,7 @@
 
 #include <asm/io.h>
 #include <mmc.h>
+#include <fdtdec.h>
 
 /*
  * Controller registers
@@ -244,9 +245,15 @@ struct sdhci_host {
 	const struct sdhci_ops *ops;
 	int index;
 
+	int bus_width;
+	struct fdt_gpio_state pwr_gpio;	/* Power GPIO */
+	struct fdt_gpio_state cd_gpio;		/* Card Detect GPIO */
+
 	void (*set_control_reg)(struct sdhci_host *host);
 	void (*set_clock)(int dev_index, unsigned int div);
 	uint	voltages;
+
+	struct mmc_config cfg;
 };
 
 #ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS
diff --git a/include/sh_tmu.h b/include/sh_tmu.h
index 96c589da50..61afc7136d 100644
--- a/include/sh_tmu.h
+++ b/include/sh_tmu.h
@@ -47,7 +47,7 @@ struct tmu_regs {
 };
 #endif /* CONFIG_SH3 */
 
-#if defined(CONFIG_SH4) || defined(CONFIG_SH4A) || defined(CONFIG_RMOBILE)
+#if defined(CONFIG_SH4) || defined(CONFIG_RMOBILE)
 struct tmu_regs {
 	u32 reserved;
 	u8  tstr;
@@ -69,7 +69,7 @@ struct tmu_regs {
 
 static inline unsigned long get_tmu0_clk_rate(void)
 {
-	return CONFIG_SYS_CLK_FREQ;
+	return CONFIG_SH_TMU_CLK_FREQ;
 }
 
 #endif	/* __SH_TMU_H */
diff --git a/include/smiLynxEM.h b/include/smiLynxEM.h
deleted file mode 100644
index c020115f86..0000000000
--- a/include/smiLynxEM.h
+++ /dev/null
@@ -1,163 +0,0 @@
-/*
- * (C) Copyright 1997-2002 ELTEC Elektronik AG
- * Frank Gottschling <fgottschling@eltec.de>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-/*
- * smiLynxEM.h
- * Silicon Motion graphic interface for sm810/sm710/sm712 accelerator
- *
- *
- *  modification history
- *  --------------------
- *  04-18-2002 Rewritten for U-Boot <fgottschling@eltec.de>.
- */
-
-#ifndef _SMI_LYNX_EM_H_
-#define _SMI_LYNX_EM_H_
-
-/*
- * SMI 710/712 have 4MB internal RAM; SMI 810 2MB internal + 2MB external
- */
-#define VIDEO_MEM_SIZE  0x400000
-
-/*
- * Supported video modes for SMI Lynx E/EM/EM+
- */
-#define VIDEO_MODES             7
-#define DUAL_800_600            0   /* SMI710:VGA1:75Hz     (pitch=1600) */
-				    /*        VGA2:60/120Hz (pitch=1600) */
-				    /* SMI810:VGA1:75Hz     (pitch=1600) */
-				    /*        VGA2:75Hz     (pitch=1600) */
-#define DUAL_1024_768           1   /* VGA1:75Hz VGA2:73Hz (pitch=2048)  */
-#define SINGLE_800_600          2   /* VGA1:75Hz (pitch=800)             */
-#define SINGLE_1024_768         3   /* VGA1:75Hz (pitch=1024)            */
-#define SINGLE_1280_1024        4   /* VGA1:75Hz (pitch=1280)            */
-#define TV_MODE_CCIR            5   /* VGA1:50Hz (h=720;v=576;pitch=720) */
-#define TV_MODE_EIA             6   /* VGA1:60Hz (h=720;v=484;pitch=720) */
-
-
-/*
- * ISA mapped regs
- */
-#define SMI_INDX_C4             (pGD->isaBase + 0x03c4)    /* index reg */
-#define SMI_DATA_C5             (pGD->isaBase + 0x03c5)    /* data reg */
-#define SMI_INDX_D4             (pGD->isaBase + 0x03d4)    /* index reg */
-#define SMI_DATA_D5             (pGD->isaBase + 0x03d5)    /* data reg */
-#define SMI_INDX_CE             (pGD->isaBase + 0x03ce)    /* index reg */
-#define SMI_DATA_CF             (pGD->isaBase + 0x03cf)    /* data reg */
-#define SMI_LOCK_REG            (pGD->isaBase + 0x03c3)    /* unlock/lock ext crt reg */
-#define SMI_MISC_REG            (pGD->isaBase + 0x03c2)    /* misc reg */
-#define SMI_LUT_MASK            (pGD->isaBase + 0x03c6)    /* lut mask reg */
-#define SMI_LUT_START           (pGD->isaBase + 0x03c8)    /* lut start index */
-#define SMI_LUT_RGB             (pGD->isaBase + 0x03c9)    /* lut colors auto incr.*/
-
-
-/*
- * Video processor control
- */
-typedef struct {
-    unsigned int   control;
-    unsigned int   colorKey;
-    unsigned int   colorKeyMask;
-    unsigned int   start;
-    unsigned short offset;
-    unsigned short width;
-    unsigned int   fifoPrio;
-    unsigned int   fifoERL;
-    unsigned int   YUVtoRGB;
-} SmiVideoProc;
-
-/*
- * Video window control
- */
-typedef struct {
-    unsigned short top;
-    unsigned short left;
-    unsigned short bottom;
-    unsigned short right;
-    unsigned int   srcStart;
-    unsigned short width;
-    unsigned short offset;
-    unsigned char  hStretch;
-    unsigned char  vStretch;
-} SmiVideoWin;
-
-/*
- * Capture port control
- */
-typedef struct {
-    unsigned int   control;
-    unsigned short topClip;
-    unsigned short leftClip;
-    unsigned short srcHeight;
-    unsigned short srcWidth;
-    unsigned int   srcBufStart1;
-    unsigned int   srcBufStart2;
-    unsigned short srcOffset;
-    unsigned short fifoControl;
-} SmiCapturePort;
-
-
-/******************************************************************************/
-/* Export Graphic Driver Control                                              */
-/******************************************************************************/
-
-typedef struct {
-    unsigned int isaBase;
-    unsigned int pciBase;
-    unsigned int dprBase;
-    unsigned int vprBase;
-    unsigned int cprBase;
-    unsigned int frameAdrs;
-    unsigned int memSize;
-    unsigned int mode;
-    unsigned int gdfIndex;
-    unsigned int gdfBytesPP;
-    unsigned int fg;
-    unsigned int bg;
-    unsigned int plnSizeX;
-    unsigned int plnSizeY;
-    unsigned int winSizeX;
-    unsigned int winSizeY;
-    char modeIdent[80];
-} GraphicDevice;
-
-extern GraphicDevice smi;
-
-
-/******************************************************************************/
-/* Export Graphic Functions                                                   */
-/******************************************************************************/
-
-void *video_hw_init (void);       /* returns GraphicDevice struct or NULL */
-
-void video_hw_bitblt (
-    unsigned int bpp,             /* bytes per pixel */
-    unsigned int src_x,           /* source pos x */
-    unsigned int src_y,           /* source pos y */
-    unsigned int dst_x,           /* dest pos x */
-    unsigned int dst_y,           /* dest pos y */
-    unsigned int dim_x,           /* frame width */
-    unsigned int dim_y            /* frame height */
-    );
-
-void video_hw_rectfill (
-    unsigned int bpp,             /* bytes per pixel */
-    unsigned int dst_x,           /* dest pos x */
-    unsigned int dst_y,           /* dest pos y */
-    unsigned int dim_x,           /* frame width */
-    unsigned int dim_y,           /* frame height */
-    unsigned int color            /* fill color */
-     );
-
-void video_set_lut (
-    unsigned int index,           /* color number */
-    unsigned char r,              /* red */
-    unsigned char g,              /* green */
-    unsigned char b               /* blue */
-    );
-
-#endif /*_SMI_LYNX_EM_H_ */
diff --git a/include/sound.h b/include/sound.h
index a06ab85386..155e1b40e2 100644
--- a/include/sound.h
+++ b/include/sound.h
@@ -30,6 +30,15 @@ struct sound_codec_info {
 };
 
 /*
+ * Generates square wave sound data for 1 second
+ *
+ * @param data          data buffer pointer
+ * @param size          size of the buffer
+ * @param freq          frequency of the wave
+ */
+void sound_create_square_wave(unsigned short *data, int size, uint32_t freq);
+
+/*
  * Initialises audio sub system
  * @param blob	Pointer of device tree node or NULL if none.
  * @return	int value 0 for success, -1 for error
diff --git a/include/spi.h b/include/spi.h
index ad9248bee0..ffd66478b1 100644
--- a/include/spi.h
+++ b/include/spi.h
@@ -29,10 +29,31 @@
 #define SPI_XFER_END		0x02	/* Deassert CS after transfer */
 #define SPI_XFER_MMAP		0x08	/* Memory Mapped start */
 #define SPI_XFER_MMAP_END	0x10	/* Memory Mapped End */
+#define SPI_XFER_ONCE		(SPI_XFER_BEGIN | SPI_XFER_END)
+#define SPI_XFER_U_PAGE		(1 << 5)
+
+/* SPI TX operation modes */
+#define SPI_OPM_TX_QPP		1 << 0
+
+/* SPI RX operation modes */
+#define SPI_OPM_RX_AS		1 << 0
+#define SPI_OPM_RX_DOUT		1 << 1
+#define SPI_OPM_RX_DIO		1 << 2
+#define SPI_OPM_RX_QOF		1 << 3
+#define SPI_OPM_RX_QIOF		1 << 4
+#define SPI_OPM_RX_EXTN		SPI_OPM_RX_AS | SPI_OPM_RX_DOUT | \
+				SPI_OPM_RX_DIO | SPI_OPM_RX_QOF | \
+				SPI_OPM_RX_QIOF
+
+/* SPI bus connection options */
+#define SPI_CONN_DUAL_SHARED	1 << 0
+#define SPI_CONN_DUAL_SEPARATED	1 << 1
 
 /* Header byte that marks the start of the message */
 #define SPI_PREAMBLE_END_BYTE	0xec
 
+#define SPI_DEFAULT_WORDLEN 8
+
 /**
  * struct spi_slave - Representation of a SPI slave
  *
@@ -40,15 +61,25 @@
  *
  * @bus:		ID of the bus that the slave is attached to.
  * @cs:			ID of the chip select connected to the slave.
+ * @op_mode_rx:		SPI RX operation mode.
+ * @op_mode_tx:		SPI TX operation mode.
+ * @wordlen:		Size of SPI word in number of bits
  * @max_write_size:	If non-zero, the maximum number of bytes which can
  *			be written at once, excluding command bytes.
  * @memory_map:		Address of read-only SPI flash access.
+ * @option:		Varies SPI bus options - separate, shared bus.
+ * @flags:		Indication of SPI flags.
  */
 struct spi_slave {
 	unsigned int bus;
 	unsigned int cs;
+	u8 op_mode_rx;
+	u8 op_mode_tx;
+	unsigned int wordlen;
 	unsigned int max_write_size;
 	void *memory_map;
+	u8 option;
+	u8 flags;
 };
 
 /**
@@ -153,6 +184,18 @@ int spi_claim_bus(struct spi_slave *slave);
 void spi_release_bus(struct spi_slave *slave);
 
 /**
+ * Set the word length for SPI transactions
+ *
+ * Set the word length (number of bits per word) for SPI transactions.
+ *
+ * @slave:	The SPI slave
+ * @wordlen:	The number of bits in a word
+ *
+ * Returns: 0 on success, -1 on failure.
+ */
+int spi_set_wordlen(struct spi_slave *slave, unsigned int wordlen);
+
+/**
  * SPI transfer
  *
  * This writes "bitlen" bits out the SPI MOSI port and simultaneously clocks
@@ -242,13 +285,24 @@ static inline int spi_w8r8(struct spi_slave *slave, unsigned char byte)
  * spi_free_slave() to free it later.
  *
  * @param blob:		Device tree blob
- * @param node:		SPI peripheral node to use
- * @param cs:		Chip select to use
- * @param max_hz:	Maximum SCK rate in Hz (0 for default)
- * @param mode:		Clock polarity, clock phase and other parameters
+ * @param slave_node:	Slave node to use
+ * @param spi_node:	SPI peripheral node to use
  * @return pointer to new spi_slave structure
  */
-struct spi_slave *spi_setup_slave_fdt(const void *blob, int node,
-		unsigned int cs, unsigned int max_hz, unsigned int mode);
+struct spi_slave *spi_setup_slave_fdt(const void *blob, int slave_node,
+				      int spi_node);
+
+/**
+ * spi_base_setup_slave_fdt() - helper function to set up a SPI slace
+ *
+ * This decodes SPI properties from the slave node to determine the
+ * chip select and SPI parameters.
+ *
+ * @blob:	Device tree blob
+ * @busnum:	Bus number to use
+ * @node:	Device tree node for the SPI bus
+ */
+struct spi_slave *spi_base_setup_slave_fdt(const void *blob, int busnum,
+					   int node);
 
 #endif	/* _SPI_H_ */
diff --git a/include/spi_flash.h b/include/spi_flash.h
index 25ca8f177b..1a11286224 100644
--- a/include/spi_flash.h
+++ b/include/spi_flash.h
@@ -19,11 +19,60 @@
 #include <linux/types.h>
 #include <linux/compiler.h>
 
+/* sf param flags */
+#define SECT_4K		1 << 1
+#define SECT_32K	1 << 2
+#define E_FSR		1 << 3
+#define WR_QPP		1 << 4
+
+/* Enum list - Full read commands */
+enum spi_read_cmds {
+	ARRAY_SLOW = 1 << 0,
+	DUAL_OUTPUT_FAST = 1 << 1,
+	DUAL_IO_FAST = 1 << 2,
+	QUAD_OUTPUT_FAST = 1 << 3,
+	QUAD_IO_FAST = 1 << 4,
+};
+#define RD_EXTN		ARRAY_SLOW | DUAL_OUTPUT_FAST | DUAL_IO_FAST
+#define RD_FULL		RD_EXTN | QUAD_OUTPUT_FAST | QUAD_IO_FAST
+
+/* Dual SPI flash memories */
+enum spi_dual_flash {
+	SF_SINGLE_FLASH = 0,
+	SF_DUAL_STACKED_FLASH = 1 << 0,
+	SF_DUAL_PARALLEL_FLASH = 1 << 1,
+};
+
+/**
+ * struct spi_flash_params - SPI/QSPI flash device params structure
+ *
+ * @name:		Device name ([MANUFLETTER][DEVTYPE][DENSITY][EXTRAINFO])
+ * @jedec:		Device jedec ID (0x[1byte_manuf_id][2byte_dev_id])
+ * @ext_jedec:		Device ext_jedec ID
+ * @sector_size:	Sector size of this device
+ * @nr_sectors:		No.of sectors on this device
+ * @e_rd_cmd:		Enum list for read commands
+ * @flags:		Important param, for flash specific behaviour
+ */
+struct spi_flash_params {
+	const char *name;
+	u32 jedec;
+	u16 ext_jedec;
+	u32 sector_size;
+	u32 nr_sectors;
+	u8 e_rd_cmd;
+	u16 flags;
+};
+
+extern const struct spi_flash_params spi_flash_params_table[];
+
 /**
  * struct spi_flash - SPI flash structure
  *
  * @spi:		SPI slave
  * @name:		Name of SPI flash
+ * @dual_flash:		Indicates dual flash memories - dual stacked, parallel
+ * @shift:		Flash shift useful in dual parallel
  * @size:		Total flash size
  * @page_size:		Write (page) size
  * @sector_size:	Sector size
@@ -33,18 +82,23 @@
  * @bank_curr:		Current flash bank
  * @poll_cmd:		Poll cmd - for flash erase/program
  * @erase_cmd:		Erase cmd 4K, 32K, 64K
+ * @read_cmd:		Read cmd - Array Fast, Extn read and quad read.
+ * @write_cmd:		Write cmd - page and quad program.
+ * @dummy_byte:		Dummy cycles for read operation.
  * @memory_map:		Address of read-only SPI flash access
  * @read:		Flash read ops: Read len bytes at offset into buf
  *			Supported cmds: Fast Array Read
- * @write:		Flash write ops: Write len bytes from buf into offeset
+ * @write:		Flash write ops: Write len bytes from buf into offset
  *			Supported cmds: Page Program
  * @erase:		Flash erase ops: Erase len bytes from offset
  *			Supported cmds: Sector erase 4K, 32K, 64K
- * return 0 - Sucess, 1 - Failure
+ * return 0 - Success, 1 - Failure
  */
 struct spi_flash {
 	struct spi_slave *spi;
 	const char *name;
+	u8 dual_flash;
+	u8 shift;
 
 	u32 size;
 	u32 page_size;
@@ -57,6 +111,9 @@ struct spi_flash {
 #endif
 	u8 poll_cmd;
 	u8 erase_cmd;
+	u8 read_cmd;
+	u8 write_cmd;
+	u8 dummy_byte;
 
 	void *memory_map;
 	int (*read)(struct spi_flash *flash, u32 offset, size_t len, void *buf);
@@ -67,6 +124,19 @@ struct spi_flash {
 
 struct spi_flash *spi_flash_probe(unsigned int bus, unsigned int cs,
 		unsigned int max_hz, unsigned int spi_mode);
+
+/**
+ * Set up a new SPI flash from an fdt node
+ *
+ * @param blob		Device tree blob
+ * @param slave_node	Pointer to this SPI slave node in the device tree
+ * @param spi_node	Cached pointer to the SPI interface this node belongs
+ *			to
+ * @return 0 if ok, -1 on error
+ */
+struct spi_flash *spi_flash_probe_fdt(const void *blob, int slave_node,
+				      int spi_node);
+
 void spi_flash_free(struct spi_flash *flash);
 
 static inline int spi_flash_read(struct spi_flash *flash, u32 offset,
diff --git a/include/spl.h b/include/spl.h
index 2bd6e16a0e..a7e41da7fd 100644
--- a/include/spl.h
+++ b/include/spl.h
@@ -11,10 +11,12 @@
 #include <linux/compiler.h>
 #include <asm/spl.h>
 
+
 /* Boot type */
 #define MMCSD_MODE_UNDEFINED	0
 #define MMCSD_MODE_RAW		1
 #define MMCSD_MODE_FAT		2
+#define MMCSD_MODE_EMMCBOOT	3
 
 struct spl_image_info {
 	const char *name;
@@ -60,6 +62,16 @@ void spl_spi_load_image(void);
 /* Ethernet SPL functions */
 void spl_net_load_image(const char *device);
 
+/* USB SPL functions */
+void spl_usb_load_image(void);
+
+/* SATA SPL functions */
+void spl_sata_load_image(void);
+
+/* SPL FAT image functions */
+int spl_load_image_fat(block_dev_desc_t *block_dev, int partition, const char *filename);
+int spl_load_image_fat_os(block_dev_desc_t *block_dev, int partition);
+
 #ifdef CONFIG_SPL_BOARD_INIT
 void spl_board_init(void);
 #endif
diff --git a/include/sx151x.h b/include/sx151x.h
new file mode 100644
index 0000000000..be42b0681b
--- /dev/null
+++ b/include/sx151x.h
@@ -0,0 +1,17 @@
+/*
+ * (C) Copyright 2013
+ * Viktar Palstsiuk, Promwad, viktar.palstsiuk@promwad.com
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __SX151X_H_
+#define __SX151X_H_
+
+int sx151x_get_value(int chip, int gpio);
+int sx151x_set_value(int chip, int gpio, int val);
+int sx151x_direction_input(int chip, int gpio);
+int sx151x_direction_output(int chip, int gpio);
+int sx151x_reset(int chip);
+
+#endif /* __SX151X_H_ */
diff --git a/include/thor.h b/include/thor.h
new file mode 100644
index 0000000000..afeade4564
--- /dev/null
+++ b/include/thor.h
@@ -0,0 +1,27 @@
+/*
+ * thor.h -- USB THOR Downloader protocol
+ *
+ * Copyright (C) 2013 Samsung Electronics
+ * Lukasz Majewski  <l.majewski@samsung.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ *
+ */
+
+#ifndef __THOR_H_
+#define __THOR_H_
+
+#include <linux/usb/composite.h>
+
+int thor_handle(void);
+int thor_init(void);
+
+#ifdef CONFIG_THOR_FUNCTION
+int thor_add(struct usb_configuration *c);
+#else
+int thor_add(struct usb_configuration *c)
+{
+	return 0;
+}
+#endif
+#endif /* __THOR_H_ */
diff --git a/include/tsec.h b/include/tsec.h
index f0f3d4d59b..1046426c5c 100644
--- a/include/tsec.h
+++ b/include/tsec.h
@@ -7,7 +7,7 @@
  *  terms of the GNU Public License, Version 2, incorporated
  *  herein by reference.
  *
- * Copyright 2004, 2007, 2009, 2011  Freescale Semiconductor, Inc.
+ * Copyright 2004, 2007, 2009, 2011, 2013 Freescale Semiconductor, Inc.
  * (C) Copyright 2003, Motorola, Inc.
  * maintained by Xianghua Xiao (x.xiao@motorola.com)
  * author Andy Fleming
@@ -27,13 +27,26 @@
 
 #define CONFIG_SYS_MDIO_BASE_ADDR (MDIO_BASE_ADDR + 0x520)
 
+#define TSEC_GET_REGS(num, offset) \
+	(struct tsec __iomem *)\
+	(TSEC_BASE_ADDR + (((num) - 1) * (offset)))
+
+#define TSEC_GET_REGS_BASE(num) \
+	TSEC_GET_REGS((num), TSEC_SIZE)
+
+#define TSEC_GET_MDIO_REGS(num, offset) \
+	(struct tsec_mii_mng __iomem *)\
+	(CONFIG_SYS_MDIO_BASE_ADDR  + ((num) - 1) * (offset))
+
+#define TSEC_GET_MDIO_REGS_BASE(num) \
+	TSEC_GET_MDIO_REGS((num), TSEC_MDIO_OFFSET)
+
 #define DEFAULT_MII_NAME "FSL_MDIO"
 
 #define STD_TSEC_INFO(num) \
 {			\
-	.regs = (tsec_t *)(TSEC_BASE_ADDR + ((num - 1) * TSEC_SIZE)), \
-	.miiregs_sgmii = (struct tsec_mii_mng *)(CONFIG_SYS_MDIO_BASE_ADDR \
-					 + (num - 1) * TSEC_MDIO_OFFSET), \
+	.regs = TSEC_GET_REGS_BASE(num), \
+	.miiregs_sgmii = TSEC_GET_MDIO_REGS_BASE(num), \
 	.devname = CONFIG_TSEC##num##_NAME, \
 	.phyaddr = TSEC##num##_PHY_ADDR, \
 	.flags = TSEC##num##_FLAGS, \
@@ -42,9 +55,8 @@
 
 #define SET_STD_TSEC_INFO(x, num) \
 {			\
-	x.regs = (tsec_t *)(TSEC_BASE_ADDR + ((num - 1) * TSEC_SIZE)); \
-	x.miiregs_sgmii = (struct tsec_mii_mng *)(CONFIG_SYS_MDIO_BASE_ADDR \
-					  + (num - 1) * TSEC_MDIO_OFFSET); \
+	x.regs = TSEC_GET_REGS_BASE(num); \
+	x.miiregs_sgmii = TSEC_GET_MDIO_REGS_BASE(num); \
 	x.devname = CONFIG_TSEC##num##_NAME; \
 	x.phyaddr = TSEC##num##_PHY_ADDR; \
 	x.flags = TSEC##num##_FLAGS;\
@@ -186,195 +198,190 @@
 #define RXBD_TRUNCATED		0x0001
 #define RXBD_STATS		0x003f
 
-typedef struct txbd8
-{
-	ushort	     status;	     /* Status Fields */
-	ushort	     length;	     /* Buffer length */
-	uint	     bufPtr;	     /* Buffer Pointer */
-} txbd8_t;
-
-typedef struct rxbd8
-{
-	ushort	     status;	     /* Status Fields */
-	ushort	     length;	     /* Buffer Length */
-	uint	     bufPtr;	     /* Buffer Pointer */
-} rxbd8_t;
-
-typedef struct rmon_mib
-{
+struct txbd8 {
+	uint16_t     status;	     /* Status Fields */
+	uint16_t     length;	     /* Buffer length */
+	uint32_t     bufptr;	     /* Buffer Pointer */
+};
+
+struct rxbd8 {
+	uint16_t     status;	     /* Status Fields */
+	uint16_t     length;	     /* Buffer Length */
+	uint32_t     bufptr;	     /* Buffer Pointer */
+};
+
+struct tsec_rmon_mib {
 	/* Transmit and Receive Counters */
-	uint	tr64;		/* Transmit and Receive 64-byte Frame Counter */
-	uint	tr127;		/* Transmit and Receive 65-127 byte Frame Counter */
-	uint	tr255;		/* Transmit and Receive 128-255 byte Frame Counter */
-	uint	tr511;		/* Transmit and Receive 256-511 byte Frame Counter */
-	uint	tr1k;		/* Transmit and Receive 512-1023 byte Frame Counter */
-	uint	trmax;		/* Transmit and Receive 1024-1518 byte Frame Counter */
-	uint	trmgv;		/* Transmit and Receive 1519-1522 byte Good VLAN Frame */
+	u32	tr64;		/* Tx/Rx 64-byte Frame Counter */
+	u32	tr127;		/* Tx/Rx 65-127 byte Frame Counter */
+	u32	tr255;		/* Tx/Rx 128-255 byte Frame Counter */
+	u32	tr511;		/* Tx/Rx 256-511 byte Frame Counter */
+	u32	tr1k;		/* Tx/Rx 512-1023 byte Frame Counter */
+	u32	trmax;		/* Tx/Rx 1024-1518 byte Frame Counter */
+	u32	trmgv;		/* Tx/Rx 1519-1522 byte Good VLAN Frame */
 	/* Receive Counters */
-	uint	rbyt;		/* Receive Byte Counter */
-	uint	rpkt;		/* Receive Packet Counter */
-	uint	rfcs;		/* Receive FCS Error Counter */
-	uint	rmca;		/* Receive Multicast Packet (Counter) */
-	uint	rbca;		/* Receive Broadcast Packet */
-	uint	rxcf;		/* Receive Control Frame Packet */
-	uint	rxpf;		/* Receive Pause Frame Packet */
-	uint	rxuo;		/* Receive Unknown OP Code */
-	uint	raln;		/* Receive Alignment Error */
-	uint	rflr;		/* Receive Frame Length Error */
-	uint	rcde;		/* Receive Code Error */
-	uint	rcse;		/* Receive Carrier Sense Error */
-	uint	rund;		/* Receive Undersize Packet */
-	uint	rovr;		/* Receive Oversize Packet */
-	uint	rfrg;		/* Receive Fragments */
-	uint	rjbr;		/* Receive Jabber */
-	uint	rdrp;		/* Receive Drop */
+	u32	rbyt;		/* Receive Byte Counter */
+	u32	rpkt;		/* Receive Packet Counter */
+	u32	rfcs;		/* Receive FCS Error Counter */
+	u32	rmca;		/* Receive Multicast Packet (Counter) */
+	u32	rbca;		/* Receive Broadcast Packet */
+	u32	rxcf;		/* Receive Control Frame Packet */
+	u32	rxpf;		/* Receive Pause Frame Packet */
+	u32	rxuo;		/* Receive Unknown OP Code */
+	u32	raln;		/* Receive Alignment Error */
+	u32	rflr;		/* Receive Frame Length Error */
+	u32	rcde;		/* Receive Code Error */
+	u32	rcse;		/* Receive Carrier Sense Error */
+	u32	rund;		/* Receive Undersize Packet */
+	u32	rovr;		/* Receive Oversize Packet */
+	u32	rfrg;		/* Receive Fragments */
+	u32	rjbr;		/* Receive Jabber */
+	u32	rdrp;		/* Receive Drop */
 	/* Transmit Counters */
-	uint	tbyt;		/* Transmit Byte Counter */
-	uint	tpkt;		/* Transmit Packet */
-	uint	tmca;		/* Transmit Multicast Packet */
-	uint	tbca;		/* Transmit Broadcast Packet */
-	uint	txpf;		/* Transmit Pause Control Frame */
-	uint	tdfr;		/* Transmit Deferral Packet */
-	uint	tedf;		/* Transmit Excessive Deferral Packet */
-	uint	tscl;		/* Transmit Single Collision Packet */
+	u32	tbyt;		/* Transmit Byte Counter */
+	u32	tpkt;		/* Transmit Packet */
+	u32	tmca;		/* Transmit Multicast Packet */
+	u32	tbca;		/* Transmit Broadcast Packet */
+	u32	txpf;		/* Transmit Pause Control Frame */
+	u32	tdfr;		/* Transmit Deferral Packet */
+	u32	tedf;		/* Transmit Excessive Deferral Packet */
+	u32	tscl;		/* Transmit Single Collision Packet */
 	/* (0x2_n700) */
-	uint	tmcl;		/* Transmit Multiple Collision Packet */
-	uint	tlcl;		/* Transmit Late Collision Packet */
-	uint	txcl;		/* Transmit Excessive Collision Packet */
-	uint	tncl;		/* Transmit Total Collision */
-
-	uint	res2;
-
-	uint	tdrp;		/* Transmit Drop Frame */
-	uint	tjbr;		/* Transmit Jabber Frame */
-	uint	tfcs;		/* Transmit FCS Error */
-	uint	txcf;		/* Transmit Control Frame */
-	uint	tovr;		/* Transmit Oversize Frame */
-	uint	tund;		/* Transmit Undersize Frame */
-	uint	tfrg;		/* Transmit Fragments Frame */
+	u32	tmcl;		/* Transmit Multiple Collision Packet */
+	u32	tlcl;		/* Transmit Late Collision Packet */
+	u32	txcl;		/* Transmit Excessive Collision Packet */
+	u32	tncl;		/* Transmit Total Collision */
+
+	u32	res2;
+
+	u32	tdrp;		/* Transmit Drop Frame */
+	u32	tjbr;		/* Transmit Jabber Frame */
+	u32	tfcs;		/* Transmit FCS Error */
+	u32	txcf;		/* Transmit Control Frame */
+	u32	tovr;		/* Transmit Oversize Frame */
+	u32	tund;		/* Transmit Undersize Frame */
+	u32	tfrg;		/* Transmit Fragments Frame */
 	/* General Registers */
-	uint	car1;		/* Carry Register One */
-	uint	car2;		/* Carry Register Two */
-	uint	cam1;		/* Carry Register One Mask */
-	uint	cam2;		/* Carry Register Two Mask */
-} rmon_mib_t;
-
-typedef struct tsec_hash_regs
-{
-	uint	iaddr0;		/* Individual Address Register 0 */
-	uint	iaddr1;		/* Individual Address Register 1 */
-	uint	iaddr2;		/* Individual Address Register 2 */
-	uint	iaddr3;		/* Individual Address Register 3 */
-	uint	iaddr4;		/* Individual Address Register 4 */
-	uint	iaddr5;		/* Individual Address Register 5 */
-	uint	iaddr6;		/* Individual Address Register 6 */
-	uint	iaddr7;		/* Individual Address Register 7 */
-	uint	res1[24];
-	uint	gaddr0;		/* Group Address Register 0 */
-	uint	gaddr1;		/* Group Address Register 1 */
-	uint	gaddr2;		/* Group Address Register 2 */
-	uint	gaddr3;		/* Group Address Register 3 */
-	uint	gaddr4;		/* Group Address Register 4 */
-	uint	gaddr5;		/* Group Address Register 5 */
-	uint	gaddr6;		/* Group Address Register 6 */
-	uint	gaddr7;		/* Group Address Register 7 */
-	uint	res2[24];
-} tsec_hash_t;
-
-typedef struct tsec
-{
+	u32	car1;		/* Carry Register One */
+	u32	car2;		/* Carry Register Two */
+	u32	cam1;		/* Carry Register One Mask */
+	u32	cam2;		/* Carry Register Two Mask */
+};
+
+struct tsec_hash_regs {
+	u32	iaddr0;		/* Individual Address Register 0 */
+	u32	iaddr1;		/* Individual Address Register 1 */
+	u32	iaddr2;		/* Individual Address Register 2 */
+	u32	iaddr3;		/* Individual Address Register 3 */
+	u32	iaddr4;		/* Individual Address Register 4 */
+	u32	iaddr5;		/* Individual Address Register 5 */
+	u32	iaddr6;		/* Individual Address Register 6 */
+	u32	iaddr7;		/* Individual Address Register 7 */
+	u32	res1[24];
+	u32	gaddr0;		/* Group Address Register 0 */
+	u32	gaddr1;		/* Group Address Register 1 */
+	u32	gaddr2;		/* Group Address Register 2 */
+	u32	gaddr3;		/* Group Address Register 3 */
+	u32	gaddr4;		/* Group Address Register 4 */
+	u32	gaddr5;		/* Group Address Register 5 */
+	u32	gaddr6;		/* Group Address Register 6 */
+	u32	gaddr7;		/* Group Address Register 7 */
+	u32	res2[24];
+};
+
+struct tsec {
 	/* General Control and Status Registers (0x2_n000) */
-	uint	res000[4];
+	u32	res000[4];
 
-	uint	ievent;		/* Interrupt Event */
-	uint	imask;		/* Interrupt Mask */
-	uint	edis;		/* Error Disabled */
-	uint	res01c;
-	uint	ecntrl;		/* Ethernet Control */
-	uint	minflr;		/* Minimum Frame Length */
-	uint	ptv;		/* Pause Time Value */
-	uint	dmactrl;	/* DMA Control */
-	uint	tbipa;		/* TBI PHY Address */
+	u32	ievent;		/* Interrupt Event */
+	u32	imask;		/* Interrupt Mask */
+	u32	edis;		/* Error Disabled */
+	u32	res01c;
+	u32	ecntrl;		/* Ethernet Control */
+	u32	minflr;		/* Minimum Frame Length */
+	u32	ptv;		/* Pause Time Value */
+	u32	dmactrl;	/* DMA Control */
+	u32	tbipa;		/* TBI PHY Address */
 
-	uint	res034[3];
-	uint	res040[48];
+	u32	res034[3];
+	u32	res040[48];
 
 	/* Transmit Control and Status Registers (0x2_n100) */
-	uint	tctrl;		/* Transmit Control */
-	uint	tstat;		/* Transmit Status */
-	uint	res108;
-	uint	tbdlen;		/* Tx BD Data Length */
-	uint	res110[5];
-	uint	ctbptr;		/* Current TxBD Pointer */
-	uint	res128[23];
-	uint	tbptr;		/* TxBD Pointer */
-	uint	res188[30];
+	u32	tctrl;		/* Transmit Control */
+	u32	tstat;		/* Transmit Status */
+	u32	res108;
+	u32	tbdlen;		/* Tx BD Data Length */
+	u32	res110[5];
+	u32	ctbptr;		/* Current TxBD Pointer */
+	u32	res128[23];
+	u32	tbptr;		/* TxBD Pointer */
+	u32	res188[30];
 	/* (0x2_n200) */
-	uint	res200;
-	uint	tbase;		/* TxBD Base Address */
-	uint	res208[42];
-	uint	ostbd;		/* Out of Sequence TxBD */
-	uint	ostbdp;		/* Out of Sequence Tx Data Buffer Pointer */
-	uint	res2b8[18];
+	u32	res200;
+	u32	tbase;		/* TxBD Base Address */
+	u32	res208[42];
+	u32	ostbd;		/* Out of Sequence TxBD */
+	u32	ostbdp;		/* Out of Sequence Tx Data Buffer Pointer */
+	u32	res2b8[18];
 
 	/* Receive Control and Status Registers (0x2_n300) */
-	uint	rctrl;		/* Receive Control */
-	uint	rstat;		/* Receive Status */
-	uint	res308;
-	uint	rbdlen;		/* RxBD Data Length */
-	uint	res310[4];
-	uint	res320;
-	uint	crbptr;	/* Current Receive Buffer Pointer */
-	uint	res328[6];
-	uint	mrblr;	/* Maximum Receive Buffer Length */
-	uint	res344[16];
-	uint	rbptr;	/* RxBD Pointer */
-	uint	res388[30];
+	u32	rctrl;		/* Receive Control */
+	u32	rstat;		/* Receive Status */
+	u32	res308;
+	u32	rbdlen;		/* RxBD Data Length */
+	u32	res310[4];
+	u32	res320;
+	u32	crbptr;	/* Current Receive Buffer Pointer */
+	u32	res328[6];
+	u32	mrblr;	/* Maximum Receive Buffer Length */
+	u32	res344[16];
+	u32	rbptr;	/* RxBD Pointer */
+	u32	res388[30];
 	/* (0x2_n400) */
-	uint	res400;
-	uint	rbase;	/* RxBD Base Address */
-	uint	res408[62];
+	u32	res400;
+	u32	rbase;	/* RxBD Base Address */
+	u32	res408[62];
 
 	/* MAC Registers (0x2_n500) */
-	uint	maccfg1;	/* MAC Configuration #1 */
-	uint	maccfg2;	/* MAC Configuration #2 */
-	uint	ipgifg;		/* Inter Packet Gap/Inter Frame Gap */
-	uint	hafdup;		/* Half-duplex */
-	uint	maxfrm;		/* Maximum Frame */
-	uint	res514;
-	uint	res518;
+	u32	maccfg1;	/* MAC Configuration #1 */
+	u32	maccfg2;	/* MAC Configuration #2 */
+	u32	ipgifg;		/* Inter Packet Gap/Inter Frame Gap */
+	u32	hafdup;		/* Half-duplex */
+	u32	maxfrm;		/* Maximum Frame */
+	u32	res514;
+	u32	res518;
 
-	uint	res51c;
+	u32	res51c;
 
-	uint	resmdio[6];
+	u32	resmdio[6];
 
-	uint	res538;
+	u32	res538;
 
-	uint	ifstat;		/* Interface Status */
-	uint	macstnaddr1;	/* Station Address, part 1 */
-	uint	macstnaddr2;	/* Station Address, part 2 */
-	uint	res548[46];
+	u32	ifstat;		/* Interface Status */
+	u32	macstnaddr1;	/* Station Address, part 1 */
+	u32	macstnaddr2;	/* Station Address, part 2 */
+	u32	res548[46];
 
 	/* (0x2_n600) */
-	uint	res600[32];
+	u32	res600[32];
 
 	/* RMON MIB Registers (0x2_n680-0x2_n73c) */
-	rmon_mib_t	rmon;
-	uint	res740[48];
+	struct tsec_rmon_mib	rmon;
+	u32	res740[48];
 
 	/* Hash Function Registers (0x2_n800) */
-	tsec_hash_t	hash;
+	struct tsec_hash_regs	hash;
 
-	uint	res900[128];
+	u32	res900[128];
 
 	/* Pattern Registers (0x2_nb00) */
-	uint	resb00[62];
-	uint	attr;	   /* Default Attribute Register */
-	uint	attreli;	   /* Default Attribute Extract Length and Index */
+	u32	resb00[62];
+	u32	attr; /* Default Attribute Register */
+	u32	attreli; /* Default Attribute Extract Length and Index */
 
 	/* TSEC Future Expansion Space (0x2_nc00-0x2_nffc) */
-	uint	resc00[256];
-} tsec_t;
+	u32	resc00[256];
+};
 
 #define TSEC_GIGABIT (1 << 0)
 
@@ -383,8 +390,8 @@ typedef struct tsec
 #define TSEC_SGMII	(1 << 2)	/* MAC-PHY interface uses SGMII */
 
 struct tsec_private {
-	tsec_t *regs;
-	struct tsec_mii_mng *phyregs_sgmii;
+	struct tsec __iomem *regs;
+	struct tsec_mii_mng __iomem *phyregs_sgmii;
 	struct phy_device *phydev;
 	phy_interface_t interface;
 	struct mii_dev *bus;
@@ -394,8 +401,8 @@ struct tsec_private {
 };
 
 struct tsec_info_struct {
-	tsec_t *regs;
-	struct tsec_mii_mng *miiregs_sgmii;
+	struct tsec __iomem *regs;
+	struct tsec_mii_mng __iomem *miiregs_sgmii;
 	char *devname;
 	char *mii_devname;
 	phy_interface_t interface;
diff --git a/include/twl6030.h b/include/twl6030.h
index b4035ba4fe..7898699eac 100644
--- a/include/twl6030.h
+++ b/include/twl6030.h
@@ -110,9 +110,47 @@
 #define CTRL_P2_EOCP2	(1 << 1)
 #define CTRL_P2_BUSY	(1 << 0)
 
+#define TWL6032_CTRL_P1	0x36
+#define CTRL_P1_SP1	(1 << 3)
+
 #define GPCH0_LSB	0x57
 #define GPCH0_MSB	0x58
 
+#define TWL6032_GPCH0_LSB	0x3b
+
+#define TWL6032_GPSELECT_ISB	0x35
+
+#define USB_PRODUCT_ID_LSB	0x02
+
+#define TWL6030_GPADC_VBAT_CHNL	0x07
+#define TWL6032_GPADC_VBAT_CHNL	0x12
+
+#define TWL6030_GPADC_CTRL	0x2e
+#define TWL6032_GPADC_CTRL2	0x2f
+#define GPADC_CTRL2_CH18_SCALER_EN	(1 << 2)
+#define GPADC_CTRL_SCALER_DIV4		(1 << 3)
+
+#define TWL6030_VBAT_MULT	40 * 1000
+#define TWL6032_VBAT_MULT	25 * 1000
+
+#define TWL6030_VBAT_SHIFT	(10 + 3)
+#define TWL6032_VBAT_SHIFT	(12 + 2)
+
+enum twl603x_chip_type{
+	chip_TWL6030,
+	chip_TWL6032,
+	chip_TWL603X_cnt
+};
+
+struct twl6030_data{
+	u8 chip_type;
+	u8 adc_rbase;
+	u8 adc_ctrl;
+	u8 adc_enable;
+	int vbat_mult;
+	int vbat_shift;
+};
+
 /* Functions to read and write from TWL6030 */
 static inline int twl6030_i2c_write_u8(u8 chip_no, u8 reg, u8 val)
 {
diff --git a/include/usb.h b/include/usb.h
index 60db897cb2..736730e896 100644
--- a/include/usb.h
+++ b/include/usb.h
@@ -125,6 +125,18 @@ struct usb_device {
 	struct usb_device *children[USB_MAXCHILDREN];
 
 	void *controller;		/* hardware controller private data */
+	/* slot_id - for xHCI enabled devices */
+	unsigned int slot_id;
+};
+
+/*
+ * You can initialize platform's USB host or device
+ * ports by passing this enum as an argument to
+ * board_usb_init().
+ */
+enum usb_init_type {
+	USB_INIT_HOST,
+	USB_INIT_DEVICE
 };
 
 /**********************************************************************
@@ -138,9 +150,9 @@ struct usb_device {
 	defined(CONFIG_USB_OMAP3) || defined(CONFIG_USB_DA8XX) || \
 	defined(CONFIG_USB_BLACKFIN) || defined(CONFIG_USB_AM35X) || \
 	defined(CONFIG_USB_MUSB_DSPS) || defined(CONFIG_USB_MUSB_AM35X) || \
-	defined(CONFIG_USB_MUSB_OMAP2PLUS)
+	defined(CONFIG_USB_MUSB_OMAP2PLUS) || defined(CONFIG_USB_XHCI)
 
-int usb_lowlevel_init(int index, void **controller);
+int usb_lowlevel_init(int index, enum usb_init_type init, void **controller);
 int usb_lowlevel_stop(int index);
 
 int submit_bulk_msg(struct usb_device *dev, unsigned long pipe,
@@ -165,8 +177,34 @@ int submit_int_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
 
 extern void udc_disconnect(void);
 
-#else
-#error USB Lowlevel not defined
+#endif
+
+/*
+ * board-specific hardware initialization, called by
+ * usb drivers and u-boot commands
+ *
+ * @param index USB controller number
+ * @param init initializes controller as USB host or device
+ */
+int board_usb_init(int index, enum usb_init_type init);
+
+/*
+ * can be used to clean up after failed USB initialization attempt
+ * vide: board_usb_init()
+ *
+ * @param index USB controller number for selective cleanup
+ * @param init usb_init_type passed to board_usb_init()
+ */
+int board_usb_cleanup(int index, enum usb_init_type init);
+
+/*
+ * If CONFIG_USB_CABLE_CHECK is set then this function
+ * should be defined in board file.
+ *
+ * @return 1 if cable is connected and 0 otherwise.
+ */
+#ifdef CONFIG_USB_CABLE_CHECK
+int usb_cable_connected(void);
 #endif
 
 #ifdef CONFIG_USB_STORAGE
@@ -338,6 +376,10 @@ int usb_set_interface(struct usb_device *dev, int interface, int alternate);
 #define usb_pipecontrol(pipe)	(usb_pipetype((pipe)) == PIPE_CONTROL)
 #define usb_pipebulk(pipe)	(usb_pipetype((pipe)) == PIPE_BULK)
 
+#define usb_pipe_ep_index(pipe)	\
+		usb_pipecontrol(pipe) ? (usb_pipeendpoint(pipe) * 2) : \
+				((usb_pipeendpoint(pipe) * 2) - \
+				 (usb_pipein(pipe) ? 0 : 1))
 
 /*************************************************************************
  * Hub Stuff
@@ -382,5 +424,6 @@ struct usb_device *usb_alloc_new_device(void *controller);
 
 int usb_new_device(struct usb_device *dev);
 void usb_free_device(void);
+int usb_alloc_device(struct usb_device *dev);
 
 #endif /*_USB_H_ */
diff --git a/include/usb/ci_udc.h b/include/usb/ci_udc.h
new file mode 100644
index 0000000000..0dee50461e
--- /dev/null
+++ b/include/usb/ci_udc.h
@@ -0,0 +1,14 @@
+/*
+ * Copyright 2011, Marvell Semiconductor Inc.
+ * Lei Wen <leiwen@marvell.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+
+#ifndef __CI_UDC_H__
+#define __CI_UDC_H__
+
+#define EP_MAX_PACKET_SIZE	0x200
+#define EP0_MAX_PACKET_SIZE	64
+#endif /* __CI_UDC_H__ */
diff --git a/include/usb/designware_udc.h b/include/usb/designware_udc.h
index 2e29a7e2a6..2e1cdf138f 100644
--- a/include/usb/designware_udc.h
+++ b/include/usb/designware_udc.h
@@ -174,19 +174,6 @@ struct udcfifo_regs {
 };
 
 /*
- * USBTTY definitions
- */
-#define  EP0_MAX_PACKET_SIZE		64
-#define  UDC_INT_ENDPOINT		1
-#define  UDC_INT_PACKET_SIZE		64
-#define  UDC_OUT_ENDPOINT		2
-#define  UDC_BULK_PACKET_SIZE		64
-#define  UDC_BULK_HS_PACKET_SIZE	512
-#define  UDC_IN_ENDPOINT		3
-#define  UDC_OUT_PACKET_SIZE		64
-#define  UDC_IN_PACKET_SIZE		64
-
-/*
  * UDC endpoint definitions
  */
 #define  UDC_EP0			0
@@ -194,22 +181,4 @@ struct udcfifo_regs {
 #define  UDC_EP2			2
 #define  UDC_EP3			3
 
-/*
- * Function declarations
- */
-
-void udc_irq(void);
-
-void udc_set_nak(int epid);
-void udc_unset_nak(int epid);
-int udc_endpoint_write(struct usb_endpoint_instance *endpoint);
-int udc_init(void);
-void udc_enable(struct usb_device_instance *device);
-void udc_disable(void);
-void udc_connect(void);
-void udc_disconnect(void);
-void udc_startup_events(struct usb_device_instance *device);
-void udc_setup_ep(struct usb_device_instance *device, unsigned int ep,
-		  struct usb_endpoint_instance *endpoint);
-
 #endif /* __DW_UDC_H */
diff --git a/include/usb/ehci-fsl.h b/include/usb/ehci-fsl.h
index 9e106fc422..734305b9db 100644
--- a/include/usb/ehci-fsl.h
+++ b/include/usb/ehci-fsl.h
@@ -149,11 +149,18 @@
 #define MPC83XX_SCCR_USB_DRCM_10	0x00200000
 
 #if defined(CONFIG_MPC83xx)
-#define CONFIG_SYS_FSL_USB_ADDR CONFIG_SYS_MPC83xx_USB_ADDR
+#define CONFIG_SYS_FSL_USB1_ADDR CONFIG_SYS_MPC83xx_USB1_ADDR
+#if defined(CONFIG_MPC834x)
+#define CONFIG_SYS_FSL_USB2_ADDR CONFIG_SYS_MPC83xx_USB2_ADDR
+#else
+#define CONFIG_SYS_FSL_USB2_ADDR	0
+#endif
 #elif defined(CONFIG_MPC85xx)
-#define CONFIG_SYS_FSL_USB_ADDR CONFIG_SYS_MPC85xx_USB_ADDR
+#define CONFIG_SYS_FSL_USB1_ADDR CONFIG_SYS_MPC85xx_USB1_ADDR
+#define CONFIG_SYS_FSL_USB2_ADDR CONFIG_SYS_MPC85xx_USB2_ADDR
 #elif defined(CONFIG_MPC512X)
-#define CONFIG_SYS_FSL_USB_ADDR CONFIG_SYS_MPC512x_USB_ADDR
+#define CONFIG_SYS_FSL_USB1_ADDR CONFIG_SYS_MPC512x_USB1_ADDR
+#define CONFIG_SYS_FSL_USB2_ADDR	0
 #endif
 
 /*
diff --git a/include/usb/mpc8xx_udc.h b/include/usb/mpc8xx_udc.h
index 475dd41664..9906c75f6a 100644
--- a/include/usb/mpc8xx_udc.h
+++ b/include/usb/mpc8xx_udc.h
@@ -111,11 +111,9 @@
 
 /* UDC device defines */
 #define EP0_MAX_PACKET_SIZE	EP_MAX_PKT
-#define UDC_OUT_ENDPOINT	0x02
+
 #define UDC_OUT_PACKET_SIZE	EP_MIN_PACKET_SIZE
-#define UDC_IN_ENDPOINT		0x03
 #define UDC_IN_PACKET_SIZE	EP_MIN_PACKET_SIZE
-#define UDC_INT_ENDPOINT	0x01
 #define UDC_INT_PACKET_SIZE	UDC_IN_PACKET_SIZE
 #define UDC_BULK_PACKET_SIZE	EP_MIN_PACKET_SIZE
 
@@ -178,18 +176,3 @@ typedef enum mpc8xx_udc_state{
 	STATE_READY,
 }mpc8xx_udc_state_t;
 
-/* Declarations */
-int udc_init(void);
-void udc_irq(void);
-int udc_endpoint_write(struct usb_endpoint_instance *endpoint);
-void udc_setup_ep(struct usb_device_instance *device, unsigned int ep,
-		  struct usb_endpoint_instance *endpoint);
-void udc_connect(void);
-void udc_disconnect(void);
-void udc_enable(struct usb_device_instance *device);
-void udc_disable(void);
-void udc_startup_events(struct usb_device_instance *device);
-
-/* Flow control */
-void udc_set_nak(int epid);
-void udc_unset_nak (int epid);
diff --git a/include/usb/musb_udc.h b/include/usb/musb_udc.h
deleted file mode 100644
index 3500c7ae96..0000000000
--- a/include/usb/musb_udc.h
+++ /dev/null
@@ -1,40 +0,0 @@
-/*
- * Copyright (c) 2009 Wind River Systems, Inc.
- * Tom Rix <Tom.Rix@windriver.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-#ifndef __MUSB_UDC_H__
-#define __MUSB_UDC_H__
-
-#include <usbdevice.h>
-
-/* UDC level routines */
-void udc_irq(void);
-void udc_set_nak(int ep_num);
-void udc_unset_nak(int ep_num);
-int udc_endpoint_write(struct usb_endpoint_instance *endpoint);
-void udc_setup_ep(struct usb_device_instance *device, unsigned int id,
-		  struct usb_endpoint_instance *endpoint);
-void udc_connect(void);
-void udc_disconnect(void);
-void udc_enable(struct usb_device_instance *device);
-void udc_disable(void);
-void udc_startup_events(struct usb_device_instance *device);
-int udc_init(void);
-
-/* usbtty */
-#ifdef CONFIG_USB_TTY
-
-#define EP0_MAX_PACKET_SIZE	64 /* MUSB_EP0_FIFOSIZE */
-#define UDC_INT_ENDPOINT	1
-#define UDC_INT_PACKET_SIZE	64
-#define UDC_OUT_ENDPOINT	2
-#define UDC_OUT_PACKET_SIZE	64
-#define UDC_IN_ENDPOINT		3
-#define UDC_IN_PACKET_SIZE	64
-#define UDC_BULK_PACKET_SIZE	64
-
-#endif /* CONFIG_USB_TTY */
-
-#endif /* __MUSB_UDC_H__ */
diff --git a/include/usb/mv_udc.h b/include/usb/mv_udc.h
deleted file mode 100644
index c71516cf6d..0000000000
--- a/include/usb/mv_udc.h
+++ /dev/null
@@ -1,132 +0,0 @@
-/*
- * Copyright 2011, Marvell Semiconductor Inc.
- * Lei Wen <leiwen@marvell.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-
-#ifndef __MV_UDC_H__
-#define __MV_UDC_H__
-
-#include <asm/byteorder.h>
-#include <asm/errno.h>
-#include <linux/usb/ch9.h>
-#include <linux/usb/gadget.h>
-
-#include "../../drivers/usb/host/ehci.h"
-
-#define NUM_ENDPOINTS		6
-
-/* Endpoint parameters */
-#define MAX_ENDPOINTS		4
-
-#define EP_MAX_PACKET_SIZE	0x200
-#define EP0_MAX_PACKET_SIZE	64
-
-struct mv_udc {
-#define MICRO_8FRAME	0x8
-#define USBCMD_ITC(x)	((((x) > 0xff) ? 0xff : x) << 16)
-#define USBCMD_FS2	(1 << 15)
-#define USBCMD_RST	(1 << 1)
-#define USBCMD_RUN	(1)
-	u32 usbcmd;		/* 0x140 */
-#define STS_SLI		(1 << 8)
-#define STS_URI		(1 << 6)
-#define STS_PCI		(1 << 2)
-#define STS_UEI		(1 << 1)
-#define STS_UI		(1 << 0)
-	u32 usbsts;		/* 0x144 */
-	u32 pad1[3];
-	u32 devaddr;		/* 0x154 */
-	u32 epinitaddr;		/* 0x158 */
-	u32 pad2[10];
-#define PTS_ENABLE	2
-#define PTS(x)		(((x) & 0x3) << 30)
-#define PFSC		(1 << 24)
-	u32 portsc;		/* 0x184 */
-	u32 pad3[8];
-#define USBMODE_DEVICE	2
-	u32 usbmode;		/* 0x1a8 */
-	u32 epstat;		/* 0x1ac */
-#define EPT_TX(x)	(1 << (((x) & 0xffff) + 16))
-#define EPT_RX(x)	(1 << ((x) & 0xffff))
-	u32 epprime;		/* 0x1b0 */
-	u32 epflush;		/* 0x1b4 */
-	u32 pad4;
-	u32 epcomp;		/* 0x1bc */
-#define CTRL_TXE	(1 << 23)
-#define CTRL_TXR	(1 << 22)
-#define CTRL_RXE	(1 << 7)
-#define CTRL_RXR	(1 << 6)
-#define CTRL_TXT_BULK	(2 << 18)
-#define CTRL_RXT_BULK	(2 << 2)
-	u32 epctrl[16];		/* 0x1c0 */
-};
-
-struct mv_ep {
-	struct usb_ep ep;
-	struct list_head queue;
-	const struct usb_endpoint_descriptor *desc;
-
-	struct usb_request req;
-	uint8_t *b_buf;
-	uint32_t b_len;
-	uint8_t b_fast[64] __aligned(ARCH_DMA_MINALIGN);
-};
-
-struct mv_drv {
-	struct usb_gadget		gadget;
-	struct usb_gadget_driver	*driver;
-	struct ehci_ctrl		*ctrl;
-	struct ept_queue_head		*epts;
-	struct ept_queue_item		*items[2 * NUM_ENDPOINTS];
-	uint8_t				*items_mem;
-	struct mv_ep			ep[NUM_ENDPOINTS];
-};
-
-struct ept_queue_head {
-	unsigned config;
-	unsigned current;	/* read-only */
-
-	unsigned next;
-	unsigned info;
-	unsigned page0;
-	unsigned page1;
-	unsigned page2;
-	unsigned page3;
-	unsigned page4;
-	unsigned reserved_0;
-
-	unsigned char setup_data[8];
-
-	unsigned reserved_1;
-	unsigned reserved_2;
-	unsigned reserved_3;
-	unsigned reserved_4;
-};
-
-#define CONFIG_MAX_PKT(n)	((n) << 16)
-#define CONFIG_ZLT		(1 << 29)	/* stop on zero-len xfer */
-#define CONFIG_IOS		(1 << 15)	/* IRQ on setup */
-
-struct ept_queue_item {
-	unsigned next;
-	unsigned info;
-	unsigned page0;
-	unsigned page1;
-	unsigned page2;
-	unsigned page3;
-	unsigned page4;
-	unsigned reserved;
-};
-
-#define TERMINATE 1
-#define INFO_BYTES(n)		((n) << 16)
-#define INFO_IOC		(1 << 15)
-#define INFO_ACTIVE		(1 << 7)
-#define INFO_HALTED		(1 << 6)
-#define INFO_BUFFER_ERROR	(1 << 5)
-#define INFO_TX_ERROR		(1 << 3)
-
-#endif /* __MV_UDC_H__ */
diff --git a/include/usb/omap1510_udc.h b/include/usb/omap1510_udc.h
index ece0e95b61..adfbf54996 100644
--- a/include/usb/omap1510_udc.h
+++ b/include/usb/omap1510_udc.h
@@ -162,32 +162,13 @@
 #define UDC_VBUS_MODE	    (1 << 18)
 
 /* OMAP Endpoint parameters */
-#define EP0_MAX_PACKET_SIZE 64
-#define UDC_OUT_ENDPOINT 2
-#define UDC_OUT_PACKET_SIZE 64
-#define UDC_IN_ENDPOINT	1
-#define UDC_IN_PACKET_SIZE 64
-#define UDC_INT_ENDPOINT 5
+#define UDC_OUT_PACKET_SIZE	64
+#define UDC_IN_PACKET_SIZE	64
 #define UDC_INT_PACKET_SIZE	16
-#define UDC_BULK_PACKET_SIZE 16
-
-void udc_irq (void);
-/* Flow control */
-void udc_set_nak(int epid);
-void udc_unset_nak (int epid);
-
-/* Higher level functions for abstracting away from specific device */
-int udc_endpoint_write(struct usb_endpoint_instance *endpoint);
-
-int  udc_init (void);
+#define UDC_BULK_PACKET_SIZE	16
 
-void udc_enable(struct usb_device_instance *device);
-void udc_disable(void);
-
-void udc_connect(void);
-void udc_disconnect(void);
-
-void udc_startup_events(struct usb_device_instance *device);
-void udc_setup_ep(struct usb_device_instance *device, unsigned int ep, struct usb_endpoint_instance *endpoint);
+#define UDC_INT_ENDPOINT 5
+#define UDC_OUT_ENDPOINT 2
+#define UDC_IN_ENDPOINT	1
 
 #endif
diff --git a/include/usb/pxa27x_udc.h b/include/usb/pxa27x_udc.h
index 7fdbe2ae0f..7eaa000303 100644
--- a/include/usb/pxa27x_udc.h
+++ b/include/usb/pxa27x_udc.h
@@ -22,35 +22,11 @@
 
 /* Endpoint parameters */
 #define MAX_ENDPOINTS		4
-#define EP_MAX_PACKET_SIZE	64
 
 #define EP0_MAX_PACKET_SIZE     16
+
 #define UDC_OUT_ENDPOINT        0x02
-#define UDC_OUT_PACKET_SIZE     EP_MAX_PACKET_SIZE
 #define UDC_IN_ENDPOINT         0x01
-#define UDC_IN_PACKET_SIZE      EP_MAX_PACKET_SIZE
 #define UDC_INT_ENDPOINT        0x05
-#define UDC_INT_PACKET_SIZE     EP_MAX_PACKET_SIZE
-#define UDC_BULK_PACKET_SIZE    EP_MAX_PACKET_SIZE
-
-void udc_irq(void);
-/* Flow control */
-void udc_set_nak(int epid);
-void udc_unset_nak(int epid);
-
-/* Higher level functions for abstracting away from specific device */
-int udc_endpoint_write(struct usb_endpoint_instance *endpoint);
-
-int  udc_init(void);
-
-void udc_enable(struct usb_device_instance *device);
-void udc_disable(void);
-
-void udc_connect(void);
-void udc_disconnect(void);
-
-void udc_startup_events(struct usb_device_instance *device);
-void udc_setup_ep(struct usb_device_instance *device,
-	 unsigned int ep, struct usb_endpoint_instance *endpoint);
 
 #endif
diff --git a/include/usb/s3c_udc.h b/include/usb/s3c_udc.h
index 734c6cd2f7..70e48f88ee 100644
--- a/include/usb/s3c_udc.h
+++ b/include/usb/s3c_udc.h
@@ -10,6 +10,7 @@
 #define __S3C_USB_GADGET
 
 #include <asm/errno.h>
+#include <linux/sizes.h>
 #include <linux/usb/ch9.h>
 #include <linux/usb/gadget.h>
 #include <linux/list.h>
@@ -19,7 +20,7 @@
 
 /*-------------------------------------------------------------------------*/
 /* DMA bounce buffer size, 16K is enough even for mass storage */
-#define DMA_BUFFER_SIZE	(4096*4)
+#define DMA_BUFFER_SIZE	(16*SZ_1K)
 
 #define EP0_FIFO_SIZE		64
 #define EP_FIFO_SIZE		512
@@ -81,9 +82,6 @@ struct s3c_udc {
 
 	struct s3c_plat_otg_data *pdata;
 
-	void *dma_buf[S3C_MAX_ENDPOINTS+1];
-	dma_addr_t dma_addr[S3C_MAX_ENDPOINTS+1];
-
 	int ep0state;
 	struct s3c_ep ep[S3C_MAX_ENDPOINTS];
 
diff --git a/include/usb/udc.h b/include/usb/udc.h
new file mode 100644
index 0000000000..1f545ec1b0
--- /dev/null
+++ b/include/usb/udc.h
@@ -0,0 +1,53 @@
+/*
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+#ifndef USB_UDC_H
+#define USB_UDC_H
+
+#ifndef EP0_MAX_PACKET_SIZE
+#define EP0_MAX_PACKET_SIZE     64
+#endif
+
+#ifndef EP_MAX_PACKET_SIZE
+#define EP_MAX_PACKET_SIZE	64
+#endif
+
+#if !defined(CONFIG_PPC) && !defined(CONFIG_OMAP1510)
+/* omap1510_udc.h and mpc8xx_udc.h will set these values */
+#define UDC_OUT_PACKET_SIZE     EP_MAX_PACKET_SIZE
+#define UDC_IN_PACKET_SIZE      EP_MAX_PACKET_SIZE
+#define UDC_INT_PACKET_SIZE     EP_MAX_PACKET_SIZE
+#define UDC_BULK_PACKET_SIZE    EP_MAX_PACKET_SIZE
+#endif
+
+#define UDC_BULK_HS_PACKET_SIZE	512
+
+#ifndef UDC_INT_ENDPOINT
+#define UDC_INT_ENDPOINT	1
+#endif
+
+#ifndef UDC_OUT_ENDPOINT
+#define UDC_OUT_ENDPOINT	2
+#endif
+
+#ifndef UDC_IN_ENDPOINT
+#define UDC_IN_ENDPOINT		3
+#endif
+
+/* function declarations */
+int udc_init(void);
+void udc_irq(void);
+int udc_endpoint_write(struct usb_endpoint_instance *endpoint);
+void udc_setup_ep(struct usb_device_instance *device, unsigned int ep,
+		  struct usb_endpoint_instance *endpoint);
+void udc_connect(void);
+void udc_disconnect(void);
+void udc_enable(struct usb_device_instance *device);
+void udc_disable(void);
+void udc_startup_events(struct usb_device_instance *device);
+
+/* Flow control */
+void udc_set_nak(int epid);
+void udc_unset_nak(int epid);
+
+#endif
diff --git a/include/usb_defs.h b/include/usb_defs.h
index 0cf5f2da89..236a5ecdf6 100644
--- a/include/usb_defs.h
+++ b/include/usb_defs.h
@@ -63,6 +63,25 @@
 #define USB_DIR_OUT           0
 #define USB_DIR_IN            0x80
 
+/*
+ * bmRequestType: USB Device Requests, table 9.2 USB 2.0 spec.
+ * (shifted) direction/type/recipient.
+ */
+#define DeviceRequest \
+	((USB_DIR_IN | USB_TYPE_STANDARD | USB_RECIP_DEVICE) << 8)
+
+#define DeviceOutRequest \
+	((USB_DIR_OUT | USB_TYPE_STANDARD | USB_RECIP_DEVICE) << 8)
+
+#define InterfaceRequest \
+	((USB_DIR_IN | USB_TYPE_STANDARD | USB_RECIP_INTERFACE) << 8)
+
+#define EndpointRequest \
+	((USB_DIR_IN | USB_TYPE_STANDARD | USB_RECIP_INTERFACE) << 8)
+
+#define EndpointOutRequest \
+	((USB_DIR_OUT | USB_TYPE_STANDARD | USB_RECIP_INTERFACE) << 8)
+
 /* Descriptor types */
 #define USB_DT_DEVICE        0x01
 #define USB_DT_CONFIG        0x02
diff --git a/include/usb_ether.h b/include/usb_ether.h
index 678c9dff25..35700a21b5 100644
--- a/include/usb_ether.h
+++ b/include/usb_ether.h
@@ -40,23 +40,25 @@ struct ueth_data {
 };
 
 /*
- * Function definitions for each USB ethernet driver go here, bracketed by
- * #ifdef CONFIG_USB_ETHER_xxx...#endif
+ * Function definitions for each USB ethernet driver go here
+ * (declaration is unconditional, compilation is conditional)
  */
-#ifdef CONFIG_USB_ETHER_ASIX
 void asix_eth_before_probe(void);
 int asix_eth_probe(struct usb_device *dev, unsigned int ifnum,
 		      struct ueth_data *ss);
 int asix_eth_get_info(struct usb_device *dev, struct ueth_data *ss,
 		      struct eth_device *eth);
-#endif
 
-#ifdef CONFIG_USB_ETHER_SMSC95XX
+void mcs7830_eth_before_probe(void);
+int mcs7830_eth_probe(struct usb_device *dev, unsigned int ifnum,
+		      struct ueth_data *ss);
+int mcs7830_eth_get_info(struct usb_device *dev, struct ueth_data *ss,
+			 struct eth_device *eth);
+
 void smsc95xx_eth_before_probe(void);
 int smsc95xx_eth_probe(struct usb_device *dev, unsigned int ifnum,
 			struct ueth_data *ss);
 int smsc95xx_eth_get_info(struct usb_device *dev, struct ueth_data *ss,
 			struct eth_device *eth);
-#endif
 
 #endif /* __USB_ETHER_H__ */
diff --git a/include/usb_mass_storage.h b/include/usb_mass_storage.h
index e08deb4ddf..058dcf1174 100644
--- a/include/usb_mass_storage.h
+++ b/include/usb_mass_storage.h
@@ -9,36 +9,37 @@
 #define __USB_MASS_STORAGE_H__
 
 #define SECTOR_SIZE		0x200
-
 #include <mmc.h>
 #include <linux/usb/composite.h>
 
-struct ums_device {
-	struct mmc *mmc;
-	int dev_num;
-	int offset;
-	int part_size;
-};
+#ifndef UMS_START_SECTOR
+#define UMS_START_SECTOR	0
+#endif
 
-struct ums_board_info {
-	int (*read_sector)(struct ums_device *ums_dev,
+#ifndef UMS_NUM_SECTORS
+#define UMS_NUM_SECTORS		0
+#endif
+
+/* Wait at maximum 60 seconds for cable connection */
+#define UMS_CABLE_READY_TIMEOUT	60
+
+struct ums {
+	int (*read_sector)(struct ums *ums_dev,
 			   ulong start, lbaint_t blkcnt, void *buf);
-	int (*write_sector)(struct ums_device *ums_dev,
+	int (*write_sector)(struct ums *ums_dev,
 			    ulong start, lbaint_t blkcnt, const void *buf);
-	void (*get_capacity)(struct ums_device *ums_dev,
-			     long long int *capacity);
+	unsigned int start_sector;
+	unsigned int num_sectors;
 	const char *name;
-	struct ums_device ums_dev;
+	struct mmc *mmc;
 };
 
-extern void board_usb_init(void);
+extern struct ums *ums;
 
-extern int fsg_init(struct ums_board_info *);
-extern void fsg_cleanup(void);
-extern struct ums_board_info *board_ums_init(unsigned int,
-					     unsigned int, unsigned int);
-extern int usb_gadget_handle_interrupts(void);
-extern int fsg_main_thread(void *);
+int fsg_init(struct ums *);
+void fsg_cleanup(void);
+struct ums *ums_init(unsigned int);
+int fsg_main_thread(void *);
 
 #ifdef CONFIG_USB_GADGET_MASS_STORAGE
 int fsg_add(struct usb_configuration *c);
diff --git a/include/usbroothubdes.h b/include/usbroothubdes.h
new file mode 100644
index 0000000000..adb70cd6af
--- /dev/null
+++ b/include/usbroothubdes.h
@@ -0,0 +1,129 @@
+/*
+ * USB virtual root hub descriptors
+ *
+ * (C) Copyright 2014
+ * Stephen Warren swarren@wwwdotorg.org
+ *
+ * Based on ohci-hcd.c
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __USBROOTHUBDES_H__
+#define __USBROOTHUBDES_H__
+
+/* Device descriptor */
+static __u8 root_hub_dev_des[] = {
+	0x12,		/* __u8  bLength; */
+	0x01,		/* __u8  bDescriptorType; Device */
+	0x10,		/* __u16 bcdUSB; v1.1 */
+	0x01,
+	0x09,		/* __u8  bDeviceClass; HUB_CLASSCODE */
+	0x00,		/* __u8  bDeviceSubClass; */
+	0x00,		/* __u8  bDeviceProtocol; */
+	0x08,		/* __u8  bMaxPacketSize0; 8 Bytes */
+	0x00,		/* __u16 idVendor; */
+	0x00,
+	0x00,		/* __u16 idProduct; */
+	0x00,
+	0x00,		/* __u16 bcdDevice; */
+	0x00,
+	0x00,		/* __u8  iManufacturer; */
+	0x01,		/* __u8  iProduct; */
+	0x00,		/* __u8  iSerialNumber; */
+	0x01,		/* __u8  bNumConfigurations; */
+};
+
+/* Configuration descriptor */
+static __u8 root_hub_config_des[] = {
+	0x09,		/* __u8  bLength; */
+	0x02,		/* __u8  bDescriptorType; Configuration */
+	0x19,		/* __u16 wTotalLength; */
+	0x00,
+	0x01,		/* __u8  bNumInterfaces; */
+	0x01,		/* __u8  bConfigurationValue; */
+	0x00,		/* __u8  iConfiguration; */
+	0x40,		/* __u8  bmAttributes;
+			 *       Bit 7: Bus-powered
+			 *       6: Self-powered,
+			 *       5 Remote-wakwup,
+			 *       4..0: resvd
+			 */
+	0x00,		/* __u8  MaxPower; */
+	/* interface */
+	0x09,		/* __u8  if_bLength; */
+	0x04,		/* __u8  if_bDescriptorType; Interface */
+	0x00,		/* __u8  if_bInterfaceNumber; */
+	0x00,		/* __u8  if_bAlternateSetting; */
+	0x01,		/* __u8  if_bNumEndpoints; */
+	0x09,		/* __u8  if_bInterfaceClass; HUB_CLASSCODE */
+	0x00,		/* __u8  if_bInterfaceSubClass; */
+	0x00,		/* __u8  if_bInterfaceProtocol; */
+	0x00,		/* __u8  if_iInterface; */
+	/* endpoint */
+	0x07,		/* __u8  ep_bLength; */
+	0x05,		/* __u8  ep_bDescriptorType; Endpoint */
+	0x81,		/* __u8  ep_bEndpointAddress; IN Endpoint 1 */
+	0x03,		/* __u8  ep_bmAttributes; Interrupt */
+	0x02,		/* __u16 ep_wMaxPacketSize; ((MAX_ROOT_PORTS + 1) / 8 */
+	0x00,
+	0xff,		/* __u8  ep_bInterval; 255 ms */
+};
+
+#ifdef WANT_USB_ROOT_HUB_HUB_DES
+static unsigned char root_hub_hub_des[] = {
+	0x09,		/* __u8  bLength; */
+	0x29,		/* __u8  bDescriptorType; Hub-descriptor */
+	0x02,		/* __u8  bNbrPorts; */
+	0x00,		/* __u16 wHubCharacteristics; */
+	0x00,
+	0x01,		/* __u8  bPwrOn2pwrGood; 2ms */
+	0x00,		/* __u8  bHubContrCurrent; 0 mA */
+	0x00,		/* __u8  DeviceRemovable; *** 7 Ports max *** */
+	0xff,		/* __u8  PortPwrCtrlMask; *** 7 ports max *** */
+};
+#endif
+
+static unsigned char root_hub_str_index0[] = {
+	0x04,		/* __u8  bLength; */
+	0x03,		/* __u8  bDescriptorType; String-descriptor */
+	0x09,		/* __u8  lang ID */
+	0x04,		/* __u8  lang ID */
+};
+
+static unsigned char root_hub_str_index1[] = {
+	32,		/* __u8  bLength; */
+	0x03,		/* __u8  bDescriptorType; String-descriptor */
+	'U',		/* __u8  Unicode */
+	0,		/* __u8  Unicode */
+	'-',		/* __u8  Unicode */
+	0,		/* __u8  Unicode */
+	'B',		/* __u8  Unicode */
+	0,		/* __u8  Unicode */
+	'o',		/* __u8  Unicode */
+	0,		/* __u8  Unicode */
+	'o',		/* __u8  Unicode */
+	0,		/* __u8  Unicode */
+	't',		/* __u8  Unicode */
+	0,		/* __u8  Unicode */
+	' ',		/* __u8  Unicode */
+	0,		/* __u8  Unicode */
+	'R',		/* __u8  Unicode */
+	0,		/* __u8  Unicode */
+	'o',		/* __u8  Unicode */
+	0,		/* __u8  Unicode */
+	'o',		/* __u8  Unicode */
+	0,		/* __u8  Unicode */
+	't',		/* __u8  Unicode */
+	0,		/* __u8  Unicode */
+	' ',		/* __u8  Unicode */
+	0,		/* __u8  Unicode */
+	'H',		/* __u8  Unicode */
+	0,		/* __u8  Unicode */
+	'u',		/* __u8  Unicode */
+	0,		/* __u8  Unicode */
+	'b',		/* __u8  Unicode */
+	0,		/* __u8  Unicode */
+};
+
+#endif
diff --git a/include/uuid.h b/include/uuid.h
new file mode 100644
index 0000000000..93027c1b28
--- /dev/null
+++ b/include/uuid.h
@@ -0,0 +1,41 @@
+/*
+ * Copyright (C) 2014 Samsung Electronics
+ * Przemyslaw Marczak <p.marczak@samsung.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+#ifndef __UUID_H__
+#define __UUID_H__
+
+/* This is structure is in big-endian */
+struct uuid {
+	unsigned int time_low;
+	unsigned short time_mid;
+	unsigned short time_hi_and_version;
+	unsigned char clock_seq_hi_and_reserved;
+	unsigned char clock_seq_low;
+	unsigned char node[6];
+} __packed;
+
+enum {
+	UUID_STR_FORMAT_STD,
+	UUID_STR_FORMAT_GUID
+};
+
+#define UUID_STR_LEN		36
+#define UUID_BIN_LEN		sizeof(struct uuid)
+
+#define UUID_VERSION_MASK	0xf000
+#define UUID_VERSION_SHIFT	12
+#define UUID_VERSION		0x4
+
+#define UUID_VARIANT_MASK	0xc0
+#define UUID_VARIANT_SHIFT	7
+#define UUID_VARIANT		0x1
+
+int uuid_str_valid(const char *uuid);
+int uuid_str_to_bin(char *uuid_str, unsigned char *uuid_bin, int str_format);
+void uuid_bin_to_str(unsigned char *uuid_bin, char *uuid_str, int str_format);
+void gen_rand_uuid(unsigned char *uuid_bin);
+void gen_rand_uuid_str(char *uuid_str, int str_format);
+#endif
diff --git a/include/video_fb.h b/include/video_fb.h
index 028e2a6aea..6cd4e377c2 100644
--- a/include/video_fb.h
+++ b/include/video_fb.h
@@ -18,8 +18,13 @@
 #ifndef _VIDEO_FB_H_
 #define _VIDEO_FB_H_
 
+#if defined(CONFIG_SYS_CONSOLE_FG_COL) && defined(CONFIG_SYS_CONSOLE_BG_COL)
+#define CONSOLE_BG_COL            CONFIG_SYS_CONSOLE_BG_COL
+#define CONSOLE_FG_COL            CONFIG_SYS_CONSOLE_FG_COL
+#else
 #define CONSOLE_BG_COL            0x00
 #define CONSOLE_FG_COL            0xa0
+#endif
 
 /*
  * Graphic Data Format (GDF) bits for VIDEO_DATA_FORMAT
diff --git a/include/video_font_4x6.h b/include/video_font_4x6.h
index 0dcd2debcb..6aeed092ad 100644
--- a/include/video_font_4x6.h
+++ b/include/video_font_4x6.h
@@ -1,4 +1,3 @@
-
 /* Hand composed "Minuscule" 4x6 font, with binary data generated using
  * Perl stub.
  *
diff --git a/include/vxworks.h b/include/vxworks.h
index c5d1577f9c..122043c941 100644
--- a/include/vxworks.h
+++ b/include/vxworks.h
@@ -9,6 +9,9 @@
 #define _VXWORKS_H_
 
 int do_bootvx(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]);
+void boot_prep_vxworks(bootm_headers_t *images);
+void boot_jump_vxworks(bootm_headers_t *images);
+void do_bootvx_fdt(bootm_headers_t *images);
 
 /*
  * Use bootaddr to find the location in memory that VxWorks
diff --git a/include/zynqpl.h b/include/zynqpl.h
index 6107cbf3a5..c81446e986 100644
--- a/include/zynqpl.h
+++ b/include/zynqpl.h
@@ -17,6 +17,7 @@ extern int zynq_dump(Xilinx_desc *desc, const void *buf, size_t bsize);
 extern int zynq_info(Xilinx_desc *desc);
 
 #define XILINX_ZYNQ_7010	0x2
+#define XILINX_ZYNQ_7015	0x1b
 #define XILINX_ZYNQ_7020	0x7
 #define XILINX_ZYNQ_7030	0xc
 #define XILINX_ZYNQ_7045	0x11
@@ -24,6 +25,7 @@ extern int zynq_info(Xilinx_desc *desc);
 
 /* Device Image Sizes */
 #define XILINX_XC7Z010_SIZE	16669920/8
+#define XILINX_XC7Z015_SIZE	28085344/8
 #define XILINX_XC7Z020_SIZE	32364512/8
 #define XILINX_XC7Z030_SIZE	47839328/8
 #define XILINX_XC7Z045_SIZE	106571232/8
@@ -33,6 +35,9 @@ extern int zynq_info(Xilinx_desc *desc);
 #define XILINX_XC7Z010_DESC(cookie) \
 { xilinx_zynq, devcfg, XILINX_XC7Z010_SIZE, NULL, cookie, "7z010" }
 
+#define XILINX_XC7Z015_DESC(cookie) \
+{ xilinx_zynq, devcfg, XILINX_XC7Z015_SIZE, NULL, cookie, "7z015" }
+
 #define XILINX_XC7Z020_DESC(cookie) \
 { xilinx_zynq, devcfg, XILINX_XC7Z020_SIZE, NULL, cookie, "7z020" }
 
diff --git a/lib/Makefile b/lib/Makefile
index df0cdd4252..27e4f78bfd 100644
--- a/lib/Makefile
+++ b/lib/Makefile
@@ -5,78 +5,63 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
+ifndef CONFIG_SPL_BUILD
 
-LIB	= $(obj)libgeneric.o
+obj-$(CONFIG_RSA) += rsa/
+obj-$(CONFIG_LZMA) += lzma/
+obj-$(CONFIG_LZO) += lzo/
+obj-$(CONFIG_ZLIB) += zlib/
+obj-$(CONFIG_TIZEN) += tizen/
 
-ifndef CONFIG_SPL_BUILD
-COBJS-$(CONFIG_AES) += aes.o
-COBJS-$(CONFIG_BZIP2) += bzlib.o
-COBJS-$(CONFIG_BZIP2) += bzlib_crctable.o
-COBJS-$(CONFIG_BZIP2) += bzlib_decompress.o
-COBJS-$(CONFIG_BZIP2) += bzlib_randtable.o
-COBJS-$(CONFIG_BZIP2) += bzlib_huffman.o
-COBJS-$(CONFIG_USB_TTY) += circbuf.o
-COBJS-y += crc7.o
-COBJS-y += crc16.o
-COBJS-$(CONFIG_OF_CONTROL) += fdtdec.o
-COBJS-$(CONFIG_TEST_FDTDEC) += fdtdec_test.o
-COBJS-$(CONFIG_GZIP) += gunzip.o
-COBJS-$(CONFIG_GZIP_COMPRESSED) += gzip.o
-COBJS-y += initcall.o
-COBJS-$(CONFIG_LMB) += lmb.o
-COBJS-y += ldiv.o
-COBJS-$(CONFIG_MD5) += md5.o
-COBJS-y += net_utils.o
-COBJS-$(CONFIG_PHYSMEM) += physmem.o
-COBJS-y += qsort.o
-COBJS-$(CONFIG_SHA1) += sha1.o
-COBJS-$(CONFIG_SHA256) += sha256.o
-COBJS-y	+= strmhz.o
-COBJS-$(CONFIG_TPM) += tpm.o
-COBJS-$(CONFIG_RBTREE)	+= rbtree.o
-COBJS-$(CONFIG_BITREVERSE) += bitrev.o
+obj-$(CONFIG_AES) += aes.o
+obj-$(CONFIG_BZIP2) += bzlib.o
+obj-$(CONFIG_BZIP2) += bzlib_crctable.o
+obj-$(CONFIG_BZIP2) += bzlib_decompress.o
+obj-$(CONFIG_BZIP2) += bzlib_randtable.o
+obj-$(CONFIG_BZIP2) += bzlib_huffman.o
+obj-$(CONFIG_USB_TTY) += circbuf.o
+obj-y += crc7.o
+obj-y += crc8.o
+obj-y += crc16.o
+obj-$(CONFIG_OF_CONTROL) += fdtdec.o
+obj-$(CONFIG_TEST_FDTDEC) += fdtdec_test.o
+obj-$(CONFIG_GZIP) += gunzip.o
+obj-$(CONFIG_GZIP_COMPRESSED) += gzip.o
+obj-y += initcall.o
+obj-$(CONFIG_LMB) += lmb.o
+obj-y += ldiv.o
+obj-$(CONFIG_MD5) += md5.o
+obj-y += net_utils.o
+obj-$(CONFIG_PHYSMEM) += physmem.o
+obj-y += qsort.o
+obj-$(CONFIG_SHA1) += sha1.o
+obj-$(CONFIG_SHA256) += sha256.o
+obj-y	+= strmhz.o
+obj-$(CONFIG_TPM) += tpm.o
+obj-$(CONFIG_RBTREE)	+= rbtree.o
+obj-$(CONFIG_BITREVERSE) += bitrev.o
 endif
 
 ifdef CONFIG_SPL_BUILD
-COBJS-$(CONFIG_SPL_YMODEM_SUPPORT) += crc16.o
-COBJS-$(CONFIG_SPL_NET_SUPPORT) += net_utils.o
+obj-$(CONFIG_SPL_YMODEM_SUPPORT) += crc16.o
+obj-$(CONFIG_SPL_NET_SUPPORT) += net_utils.o
 endif
-COBJS-$(CONFIG_ADDR_MAP) += addr_map.o
-COBJS-y += hashtable.o
-COBJS-y += errno.o
-COBJS-y += display_options.o
-COBJS-$(CONFIG_BCH) += bch.o
-COBJS-y += crc32.o
-COBJS-y += ctype.o
-COBJS-y += div64.o
-COBJS-y += hang.o
-COBJS-y += linux_string.o
-COBJS-$(CONFIG_REGEX) += slre.o
-COBJS-y += string.o
-COBJS-y += time.o
-COBJS-$(CONFIG_TRACE) += trace.o
-COBJS-$(CONFIG_BOOTP_PXE) += uuid.o
-COBJS-y += vsprintf.o
-COBJS-$(CONFIG_RANDOM_MACADDR) += rand.o
-COBJS-$(CONFIG_BOOTP_RANDOM_DELAY) += rand.o
-COBJS-$(CONFIG_CMD_LINK_LOCAL) += rand.o
-
-COBJS	:= $(sort $(COBJS-y))
-SRCS	:= $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-# SEE README.arm-unaligned-accesses
-$(obj)bzlib.o: CFLAGS += $(PLATFORM_NO_UNALIGNED)
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
+obj-$(CONFIG_ADDR_MAP) += addr_map.o
+obj-y += hashtable.o
+obj-y += errno.o
+obj-y += display_options.o
+obj-$(CONFIG_BCH) += bch.o
+obj-y += crc32.o
+obj-y += ctype.o
+obj-y += div64.o
+obj-y += hang.o
+obj-y += linux_string.o
+obj-$(CONFIG_REGEX) += slre.o
+obj-y += string.o
+obj-y += time.o
+obj-$(CONFIG_TRACE) += trace.o
+obj-$(CONFIG_LIB_UUID) += uuid.o
+obj-y += vsprintf.o
+obj-$(CONFIG_LIB_RAND) += rand.o
 
-#########################################################################
+subdir-ccflags-$(CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED) += -O2
diff --git a/lib/crc8.c b/lib/crc8.c
new file mode 100644
index 0000000000..8b68a29e40
--- /dev/null
+++ b/lib/crc8.c
@@ -0,0 +1,25 @@
+/*
+ * Copyright (c) 2013 Google, Inc
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include "linux/crc8.h"
+
+unsigned int crc8(const unsigned char *vptr, int len)
+{
+	const unsigned char *data = vptr;
+	unsigned int crc = 0;
+	int i, j;
+
+	for (j = len; j; j--, data++) {
+		crc ^= (*data << 8);
+		for (i = 8; i; i--) {
+			if (crc & 0x8000)
+				crc ^= (0x1070 << 3);
+			crc <<= 1;
+		}
+	}
+
+	return (crc >> 8) & 0xff;
+}
diff --git a/lib/display_options.c b/lib/display_options.c
index 4a972b08a4..4c0c886d61 100644
--- a/lib/display_options.c
+++ b/lib/display_options.c
@@ -87,11 +87,19 @@ int print_buffer(ulong addr, const void *data, uint width, uint count,
 {
 	/* linebuf as a union causes proper alignment */
 	union linebuf {
+#ifdef CONFIG_SYS_SUPPORT_64BIT_DATA
+		uint64_t uq[MAX_LINE_LENGTH_BYTES/sizeof(uint64_t) + 1];
+#endif
 		uint32_t ui[MAX_LINE_LENGTH_BYTES/sizeof(uint32_t) + 1];
 		uint16_t us[MAX_LINE_LENGTH_BYTES/sizeof(uint16_t) + 1];
 		uint8_t  uc[MAX_LINE_LENGTH_BYTES/sizeof(uint8_t) + 1];
 	} lb;
 	int i;
+#ifdef CONFIG_SYS_SUPPORT_64BIT_DATA
+	uint64_t x;
+#else
+	uint32_t x;
+#endif
 
 	if (linelen*width > MAX_LINE_LENGTH_BYTES)
 		linelen = MAX_LINE_LENGTH_BYTES / width;
@@ -108,14 +116,21 @@ int print_buffer(ulong addr, const void *data, uint width, uint count,
 
 		/* Copy from memory into linebuf and print hex values */
 		for (i = 0; i < thislinelen; i++) {
-			uint32_t x;
 			if (width == 4)
 				x = lb.ui[i] = *(volatile uint32_t *)data;
+#ifdef CONFIG_SYS_SUPPORT_64BIT_DATA
+			else if (width == 8)
+				x = lb.uq[i] = *(volatile uint64_t *)data;
+#endif
 			else if (width == 2)
 				x = lb.us[i] = *(volatile uint16_t *)data;
 			else
 				x = lb.uc[i] = *(volatile uint8_t *)data;
+#ifdef CONFIG_SYS_SUPPORT_64BIT_DATA
+			printf(" %0*llx", width * 2, x);
+#else
 			printf(" %0*x", width * 2, x);
+#endif
 			data += width;
 		}
 
diff --git a/lib/fdtdec.c b/lib/fdtdec.c
index dc358562d1..33265ecfb2 100644
--- a/lib/fdtdec.c
+++ b/lib/fdtdec.c
@@ -32,6 +32,7 @@ static const char * const compat_names[COMPAT_COUNT] = {
 	COMPAT(NVIDIA_TEGRA20_NAND, "nvidia,tegra20-nand"),
 	COMPAT(NVIDIA_TEGRA20_PWM, "nvidia,tegra20-pwm"),
 	COMPAT(NVIDIA_TEGRA20_DC, "nvidia,tegra20-dc"),
+	COMPAT(NVIDIA_TEGRA124_SDMMC, "nvidia,tegra124-sdhci"),
 	COMPAT(NVIDIA_TEGRA30_SDMMC, "nvidia,tegra30-sdhci"),
 	COMPAT(NVIDIA_TEGRA20_SDMMC, "nvidia,tegra20-sdhci"),
 	COMPAT(NVIDIA_TEGRA20_SFLASH, "nvidia,tegra20-sflash"),
@@ -46,11 +47,15 @@ static const char * const compat_names[COMPAT_COUNT] = {
 	COMPAT(GOOGLE_CROS_EC, "google,cros-ec"),
 	COMPAT(GOOGLE_CROS_EC_KEYB, "google,cros-ec-keyb"),
 	COMPAT(SAMSUNG_EXYNOS_EHCI, "samsung,exynos-ehci"),
+	COMPAT(SAMSUNG_EXYNOS5_XHCI, "samsung,exynos5250-xhci"),
 	COMPAT(SAMSUNG_EXYNOS_USB_PHY, "samsung,exynos-usb-phy"),
+	COMPAT(SAMSUNG_EXYNOS5_USB3_PHY, "samsung,exynos5250-usb3-phy"),
 	COMPAT(SAMSUNG_EXYNOS_TMU, "samsung,exynos-tmu"),
 	COMPAT(SAMSUNG_EXYNOS_FIMD, "samsung,exynos-fimd"),
+	COMPAT(SAMSUNG_EXYNOS_MIPI_DSI, "samsung,exynos-mipi-dsi"),
 	COMPAT(SAMSUNG_EXYNOS5_DP, "samsung,exynos5-dp"),
 	COMPAT(SAMSUNG_EXYNOS5_DWMMC, "samsung,exynos5250-dwmmc"),
+	COMPAT(SAMSUNG_EXYNOS_MMC, "samsung,exynos-mmc"),
 	COMPAT(SAMSUNG_EXYNOS_SERIAL, "samsung,exynos4210-uart"),
 	COMPAT(MAXIM_MAX77686_PMIC, "maxim,max77686_pmic"),
 	COMPAT(GENERIC_SPI_FLASH, "spi-flash"),
@@ -58,6 +63,8 @@ static const char * const compat_names[COMPAT_COUNT] = {
 	COMPAT(INFINEON_SLB9635_TPM, "infineon,slb9635-tpm"),
 	COMPAT(INFINEON_SLB9645_TPM, "infineon,slb9645-tpm"),
 	COMPAT(SAMSUNG_EXYNOS5_I2C, "samsung,exynos5-hsi2c"),
+	COMPAT(SANDBOX_HOST_EMULATION, "sandbox,host-emulation"),
+	COMPAT(SANDBOX_LCD_SDL, "sandbox,lcd-sdl"),
 };
 
 const char *fdtdec_get_compatible(enum fdt_compat_id id)
@@ -84,10 +91,10 @@ fdt_addr_t fdtdec_get_addr_size(const void *blob, int node,
 			size = (fdt_size_t *)((char *)cell +
 					sizeof(fdt_addr_t));
 			*sizep = fdt_size_to_cpu(*size);
-			debug("addr=%p, size=%p\n", (void *)addr,
-			      (void *)*sizep);
+			debug("addr=%08lx, size=%08x\n",
+			      (ulong)addr, *sizep);
 		} else {
-			debug("%p\n", (void *)addr);
+			debug("%08lx\n", (ulong)addr);
 		}
 		return addr;
 	}
@@ -609,8 +616,32 @@ int fdtdec_decode_region(const void *blob, int node,
 	if (!cell || (len != sizeof(fdt_addr_t) * 2))
 		return -1;
 
-	*ptrp = (void *)fdt_addr_to_cpu(*cell);
+	*ptrp = map_sysmem(fdt_addr_to_cpu(*cell), *size);
 	*size = fdt_size_to_cpu(cell[1]);
 	debug("%s: size=%zx\n", __func__, *size);
 	return 0;
 }
+
+/**
+ * Read a flash entry from the fdt
+ *
+ * @param blob		FDT blob
+ * @param node		Offset of node to read
+ * @param name		Name of node being read
+ * @param entry		Place to put offset and size of this node
+ * @return 0 if ok, -ve on error
+ */
+int fdtdec_read_fmap_entry(const void *blob, int node, const char *name,
+			   struct fmap_entry *entry)
+{
+	u32 reg[2];
+
+	if (fdtdec_get_int_array(blob, node, "reg", reg, 2)) {
+		debug("Node '%s' has bad/missing 'reg' property\n", name);
+		return -FDT_ERR_NOTFOUND;
+	}
+	entry->offset = reg[0];
+	entry->length = reg[1];
+
+	return 0;
+}
diff --git a/lib/hashtable.c b/lib/hashtable.c
index c5a2b08bec..4356b234ec 100644
--- a/lib/hashtable.c
+++ b/lib/hashtable.c
@@ -564,7 +564,7 @@ static int match_entry(ENTRY *ep, int flag,
 	int arg;
 	void *priv = NULL;
 
-	for (arg = 1; arg < argc; ++arg) {
+	for (arg = 0; arg < argc; ++arg) {
 #ifdef CONFIG_REGEX
 		struct slre slre;
 
diff --git a/lib/libfdt/Makefile b/lib/libfdt/Makefile
index 07373df99a..a02c9b02ad 100644
--- a/lib/libfdt/Makefile
+++ b/lib/libfdt/Makefile
@@ -5,30 +5,7 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)libfdt.o
-
-SOBJS	=
-
 COBJS-libfdt += fdt.o fdt_ro.o fdt_rw.o fdt_strerror.o fdt_sw.o fdt_wip.o fdt_empty_tree.o
 
-COBJS-$(CONFIG_OF_LIBFDT) += $(COBJS-libfdt)
-COBJS-$(CONFIG_FIT) += $(COBJS-libfdt)
-
-
-COBJS	:= $(sort $(COBJS-y))
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS))
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-$(CONFIG_OF_LIBFDT) += $(COBJS-libfdt)
+obj-$(CONFIG_FIT) += $(COBJS-libfdt)
diff --git a/lib/lzma/LzmaTools.c b/lib/lzma/LzmaTools.c
index 0aec2f9c76..90d31cdcf8 100644
--- a/lib/lzma/LzmaTools.c
+++ b/lib/lzma/LzmaTools.c
@@ -102,7 +102,7 @@ int lzmaBuffToBuffDecompress (unsigned char *outStream, SizeT *uncompressedSize,
         return SZ_ERROR_OUTPUT_EOF;
 
     /* Decompress */
-    outProcessed = *uncompressedSize;
+    outProcessed = outSizeFull;
 
     WATCHDOG_RESET();
 
@@ -111,6 +111,9 @@ int lzmaBuffToBuffDecompress (unsigned char *outStream, SizeT *uncompressedSize,
         inStream + LZMA_DATA_OFFSET, &compressedSize,
         inStream, LZMA_PROPS_SIZE, LZMA_FINISH_END, &state, &g_Alloc);
     *uncompressedSize = outProcessed;
+
+    debug("LZMA: Uncompresed ................ 0x%zx\n", outProcessed);
+
     if (res != SZ_OK)  {
         return res;
     }
diff --git a/lib/lzma/Makefile b/lib/lzma/Makefile
index 412e187c57..b6c80671b9 100644
--- a/lib/lzma/Makefile
+++ b/lib/lzma/Makefile
@@ -8,28 +8,6 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
+ccflags-y += -D_LZMA_PROB32
 
-LIB	= $(obj)liblzma.o
-
-SOBJS	=
-
-CFLAGS += -D_LZMA_PROB32
-
-COBJS-$(CONFIG_LZMA) += LzmaDec.o LzmaTools.o
-
-COBJS	= $(COBJS-y)
-SRCS 	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS))
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y += LzmaDec.o LzmaTools.o
diff --git a/lib/lzo/Makefile b/lib/lzo/Makefile
index 516519a1f8..2936544abc 100644
--- a/lib/lzo/Makefile
+++ b/lib/lzo/Makefile
@@ -5,26 +5,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)liblzo.o
-
-SOBJS	=
-
-COBJS-$(CONFIG_LZO) += lzo1x_decompress.o
-
-COBJS	= $(COBJS-y)
-SRCS 	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS))
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y += lzo1x_decompress.o
diff --git a/lib/rsa/Makefile b/lib/rsa/Makefile
index decd6e509d..164ab39964 100644
--- a/lib/rsa/Makefile
+++ b/lib/rsa/Makefile
@@ -7,26 +7,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)librsa.o
-
-ifdef CONFIG_FIT_SIGNATURE
-COBJS-$(CONFIG_RSA) += rsa-verify.o
-endif
-
-COBJS	:= $(sort $(COBJS-y))
-SRCS	:= $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-$(CONFIG_FIT_SIGNATURE) += rsa-verify.o
diff --git a/lib/time.c b/lib/time.c
index 68b8ff4190..73c3b6ad7f 100644
--- a/lib/time.c
+++ b/lib/time.c
@@ -7,11 +7,93 @@
 
 #include <common.h>
 #include <watchdog.h>
+#include <div64.h>
+#include <asm/io.h>
+
+#if CONFIG_SYS_HZ != 1000
+#warning "CONFIG_SYS_HZ must be 1000 and should not be defined by platforms"
+#endif
 
 #ifndef CONFIG_WD_PERIOD
 # define CONFIG_WD_PERIOD	(10 * 1000 * 1000)	/* 10 seconds default*/
 #endif
 
+DECLARE_GLOBAL_DATA_PTR;
+
+#ifdef CONFIG_SYS_TIMER_RATE
+ulong notrace get_tbclk(void)
+{
+	return CONFIG_SYS_TIMER_RATE;
+}
+#endif
+
+#ifdef CONFIG_SYS_TIMER_COUNTER
+unsigned long notrace timer_read_counter(void)
+{
+#ifdef CONFIG_SYS_TIMER_COUNTS_DOWN
+	return ~readl(CONFIG_SYS_TIMER_COUNTER);
+#else
+	return readl(CONFIG_SYS_TIMER_COUNTER);
+#endif
+}
+#else
+extern unsigned long __weak timer_read_counter(void);
+#endif
+
+unsigned long long __weak notrace get_ticks(void)
+{
+	unsigned long now = timer_read_counter();
+
+	/* increment tbu if tbl has rolled over */
+	if (now < gd->timebase_l)
+		gd->timebase_h++;
+	gd->timebase_l = now;
+	return ((unsigned long long)gd->timebase_h << 32) | gd->timebase_l;
+}
+
+static unsigned long long notrace tick_to_time(uint64_t tick)
+{
+	unsigned int div = get_tbclk();
+
+	tick *= CONFIG_SYS_HZ;
+	do_div(tick, div);
+	return tick;
+}
+
+int __weak timer_init(void)
+{
+	return 0;
+}
+
+ulong __weak get_timer(ulong base)
+{
+	return tick_to_time(get_ticks()) - base;
+}
+
+unsigned long __weak notrace timer_get_us(void)
+{
+	return tick_to_time(get_ticks() * 1000);
+}
+static unsigned long long usec_to_tick(unsigned long usec)
+{
+	uint64_t tick = usec;
+	tick *= get_tbclk();
+	do_div(tick, 1000000);
+	return tick;
+}
+
+void __weak __udelay(unsigned long usec)
+{
+	unsigned long long tmp;
+	ulong tmo;
+
+	tmo = usec_to_tick(usec);
+	tmp = get_ticks() + tmo;	/* get current timestamp */
+
+	while (get_ticks() < tmp)	/* loop till event */
+		 /*NOP*/;
+}
+
 /* ------------------------------------------------------------------------- */
 
 void udelay(unsigned long usec)
diff --git a/lib/tizen/Makefile b/lib/tizen/Makefile
index 80d76cfef2..e1a9cf4547 100644
--- a/lib/tizen/Makefile
+++ b/lib/tizen/Makefile
@@ -5,26 +5,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)libtizen.o
-
-SOBJS	=
-
-COBJS-$(CONFIG_TIZEN) += tizen.o
-
-COBJS	:= $(sort $(COBJS-y))
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS))
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-$(CONFIG_TIZEN) += tizen.o
diff --git a/lib/tizen/tizen.c b/lib/tizen/tizen.c
index e872591cd1..814ed18329 100644
--- a/lib/tizen/tizen.c
+++ b/lib/tizen/tizen.c
@@ -9,18 +9,25 @@
 #include <lcd.h>
 #include <libtizen.h>
 
-#include "tizen_hd_logo.h"
-#include "tizen_hd_logo_data.h"
+#include "tizen_logo_16bpp.h"
+#include "tizen_logo_16bpp_gzip.h"
 
 void get_tizen_logo_info(vidinfo_t *vid)
 {
-	switch (vid->resolution) {
-	case HD_RESOLUTION:
-		vid->logo_width = TIZEN_HD_LOGO_WIDTH;
-		vid->logo_height = TIZEN_HD_LOGO_HEIGHT;
-		vid->logo_addr = (ulong)tizen_hd_logo;
+	switch (vid->vl_bpix) {
+	case 4:
+		vid->logo_width = TIZEN_LOGO_16BPP_WIDTH;
+		vid->logo_height = TIZEN_LOGO_16BPP_HEIGHT;
+		vid->logo_x_offset = TIZEN_LOGO_16BPP_X_OFFSET;
+		vid->logo_y_offset = TIZEN_LOGO_16BPP_Y_OFFSET;
+#if defined(CONFIG_VIDEO_BMP_GZIP)
+		vid->logo_addr = (ulong)tizen_logo_16bpp_gzip;
+#else
+		vid->logo_addr = (ulong)tizen_logo_16bpp;
+#endif
 		break;
 	default:
+		vid->logo_addr = 0;
 		break;
 	}
 }
diff --git a/lib/tizen/tizen_hd_logo.h b/lib/tizen/tizen_hd_logo.h
deleted file mode 100644
index 28377b75c9..0000000000
--- a/lib/tizen/tizen_hd_logo.h
+++ /dev/null
@@ -1,5057 +0,0 @@
-/*
- * (C) Copyright 2012 Samsung Electronics
- * Donghwa Lee <dh09.lee@samsung.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef _TIZEN_HD_LOGO_H_
-#define _TIZEN_HD_LOGO_H_
-
-unsigned char tizen_hd_logo[]={
-0x1f,0x8b,0x08,0x08,0xe0,0x6f,0x8f,0x4f,0x00,0x03,0x74,0x72,0x61,0x74,0x73,0x2e,
-0x62,0x6d,0x70,0x00,0xbc,0x5c,0xe9,0x53,0x1c,0x57,0x92,0xaf,0x6a,0xa0,0x81,0xa6,
-0xb9,0x1b,0x04,0x48,0x02,0x04,0x7d,0xd0,0xdd,0x1c,0x12,0xba,0xd1,0x61,0x59,0x48,
-0x96,0x67,0xc6,0xf6,0x8e,0x2f,0xc5,0x44,0xec,0x7c,0xd9,0x88,0x89,0x99,0xfd,0x60,
-0x8f,0x23,0xc6,0x3b,0xf6,0xce,0x8c,0x67,0x6d,0x79,0xac,0x70,0x6c,0x38,0x24,0x3c,
-0x06,0x74,0x41,0x83,0x0c,0x36,0x97,0x04,0x88,0xc3,0x5c,0x7d,0x09,0x79,0x3d,0x92,
-0x6c,0x61,0x4b,0x8a,0x18,0xeb,0x1f,0xd9,0x3f,0x60,0x2b,0xab,0x3b,0xab,0xf3,0x65,
-0xbd,0x6a,0xba,0x25,0x79,0x2b,0x78,0x51,0xd5,0x55,0xaf,0xde,0xcb,0x97,0x99,0x2f,
-0x7f,0x99,0xf9,0x5e,0x71,0xfc,0xc5,0xa5,0xc9,0x1c,0x05,0x8e,0x7d,0x5a,0x69,0xd1,
-0xca,0xff,0xaa,0x8a,0xf2,0x9f,0xda,0x59,0x55,0x1a,0xf5,0xfb,0x1f,0x24,0x9f,0xf3,
-0x43,0xd5,0xff,0xc4,0xdf,0xc6,0x3d,0x55,0xa8,0xa4,0xea,0xbf,0x55,0xb1,0xf2,0x53,
-0x39,0x58,0x3b,0xaa,0x6a,0xee,0xff,0x29,0x75,0x93,0x59,0x4b,0x16,0xb5,0xf0,0x7d,
-0x7a,0x16,0xf8,0x45,0xde,0xa5,0xcf,0x38,0x3f,0x71,0x7c,0x70,0xa6,0xc5,0xa6,0x2a,
-0x36,0xbd,0xd8,0x92,0x67,0x52,0xf0,0xb9,0x51,0x5f,0x31,0x9f,0xf9,0x3b,0x7a,0x7d,
-0x1b,0xe9,0x23,0x1d,0xbd,0x2a,0x19,0x13,0xab,0x4b,0xdf,0x91,0xb5,0x63,0x6a,0x93,
-0xd6,0x63,0x63,0xe4,0x7d,0xd2,0x3a,0x30,0xee,0x1c,0x9b,0x92,0x03,0x05,0x79,0x80,
-0x75,0x78,0xdb,0xf0,0x4c,0xaf,0xab,0x6a,0x75,0xb5,0x6b,0x41,0x2e,0x84,0x1f,0xf0,
-0x1c,0xeb,0x51,0x1a,0xb0,0x5f,0xe4,0x13,0xd4,0xc9,0xcd,0x51,0x72,0x73,0x72,0x12,
-0x7d,0x5b,0xc9,0x8d,0xca,0x43,0x18,0x2b,0x1d,0x5f,0x1a,0x5d,0x12,0xc6,0xa3,0x0a,
-0xd5,0x84,0x9a,0x48,0xbb,0xde,0xd7,0xd3,0x9b,0x69,0x19,0x1d,0x52,0x79,0x2a,0x29,
-0xfd,0xcb,0xb6,0x2d,0x78,0x0f,0x78,0x9b,0x9f,0xab,0xe4,0xdb,0x73,0x14,0xbb,0x2e,
-0x5f,0x19,0x1f,0x89,0xee,0xc9,0xda,0xc9,0xa4,0x67,0x3e,0x1f,0x50,0xaf,0xf2,0x72,
-0x94,0x3c,0xe8,0x1f,0xe8,0xa0,0xed,0x43,0x1d,0x7b,0xae,0x62,0x77,0xd8,0x15,0x47,
-0x61,0x9e,0x52,0x08,0xf5,0x4c,0x3c,0x57,0x53,0xf2,0x90,0xe9,0x26,0xad,0x8b,0x7a,
-0x00,0xf5,0xa0,0x5d,0x18,0x6f,0x9e,0x4d,0xc9,0x43,0x59,0x66,0xc3,0x43,0xd9,0x9c,
-0x33,0x3d,0x7b,0x02,0xdd,0x10,0x78,0xaa,0x26,0xf5,0x5b,0x49,0xe9,0x7e,0xba,0xb6,
-0x33,0xea,0x97,0xd8,0xc2,0x4c,0xe9,0x31,0xfa,0x55,0xc9,0xbc,0x22,0x74,0x66,0x42,
-0x5b,0xba,0x3e,0x33,0x99,0xa3,0xb2,0xf7,0xa5,0xbf,0x55,0x42,0x0f,0xb3,0xe3,0xdc,
-0x26,0xd3,0xfb,0xfa,0x3d,0x85,0xd8,0x36,0x2b,0x3b,0xa0,0x5a,0xd0,0x6b,0x35,0xe6,
-0x34,0x36,0x9e,0xea,0x12,0xed,0x47,0xb0,0x87,0x32,0x4e,0xa8,0xe6,0xb1,0x4b,0xfb,
-0xce,0x52,0x0f,0x1f,0x5b,0x7f,0xd2,0xd8,0xcc,0x6c,0xfb,0x90,0x8e,0x59,0x36,0x5e,
-0x62,0xff,0x4d,0xf6,0x89,0xd2,0x43,0xf0,0x4d,0x90,0x85,0x2a,0xc1,0x66,0x9b,0x19,
-0xdb,0x05,0x9b,0x42,0x71,0xd3,0x96,0xb0,0x27,0x88,0x8f,0xfa,0xbb,0xf8,0xbe,0x92,
-0xf2,0x09,0x68,0xbf,0xc6,0x50,0xd8,0xfc,0xc6,0xb6,0xe9,0xf8,0xe9,0x7d,0x4e,0x83,
-0xc0,0x13,0xc2,0x07,0xaa,0xbf,0xc6,0x33,0x9c,0x0f,0xdc,0xa7,0xe1,0xb8,0x6e,0x33,
-0xdb,0x40,0xc3,0x6e,0x52,0xbc,0x96,0xd9,0xbb,0xa4,0x6d,0x35,0xda,0xb3,0xe0,0x99,
-0x8e,0xe7,0x36,0x25,0x57,0x2f,0x80,0xeb,0xb6,0x24,0xfe,0x33,0xde,0x70,0xd9,0xd0,
-0xfe,0xa8,0xad,0x96,0xf2,0x54,0xa6,0x47,0x16,0x36,0x4f,0x6f,0x0f,0xe5,0x07,0xfd,
-0x64,0x38,0xaf,0x9e,0xd6,0x21,0x93,0xbd,0xa1,0x73,0x59,0xd2,0x01,0xef,0x00,0x4e,
-0x16,0xe4,0x2a,0x05,0x79,0xb9,0x09,0x6c,0xa3,0xb2,0x10,0xfa,0xb4,0xc9,0xf9,0x22,
-0xe8,0x8d,0x15,0xcd,0x16,0xba,0xa4,0xf7,0x9d,0xa7,0x14,0x00,0xbe,0x42,0xbf,0xb4,
-0x3e,0xd0,0x53,0x64,0x57,0x8a,0x8a,0xf2,0x95,0x22,0xc0,0x7b,0x5d,0xee,0x6c,0x7c,
-0x86,0x3e,0xaa,0x29,0xff,0x91,0xfa,0xd6,0x82,0x9e,0x83,0xef,0xa2,0xe9,0x90,0x8e,
-0xe5,0x5a,0x81,0xbe,0xb9,0xff,0x62,0xe5,0xb3,0x98,0xc6,0x23,0x99,0x77,0x94,0x37,
-0x4f,0xaa,0x0d,0x32,0x7e,0x65,0x82,0x21,0xc6,0x5c,0x48,0x47,0x81,0x85,0x5e,0x5b,
-0xd2,0x41,0x0b,0xb5,0x4f,0xd9,0x8e,0x52,0xb5,0xb8,0x96,0xd0,0x22,0x6b,0x5b,0x98,
-0xb7,0x69,0xe8,0x15,0x68,0x67,0x31,0x0b,0x9d,0x2b,0x96,0x31,0x19,0x19,0x2f,0xe7,
-0x83,0x15,0xfd,0x59,0xd1,0x22,0x69,0x57,0x98,0xcf,0x16,0x32,0xe6,0xf3,0xed,0xff,
-0xdb,0xe6,0x6c,0xda,0x9b,0xe4,0x79,0x3a,0x3a,0x37,0xa3,0x3f,0x2d,0xff,0x59,0x7f,
-0x02,0xcf,0x54,0xf3,0x33,0x6a,0xa3,0xa8,0xfe,0x52,0xb9,0x18,0x58,0x4e,0x8b,0x24,
-0x86,0xe7,0xbe,0xa1,0x81,0x8b,0x6a,0x0a,0xcb,0x28,0xa6,0x99,0xfc,0x01,0xa6,0xc7,
-0xc2,0xbc,0x52,0xcc,0x74,0x09,0x76,0x80,0xf8,0x08,0xf4,0x1d,0x3a,0x1f,0xf1,0x5d,
-0x2b,0x9b,0x46,0xf5,0x87,0xc6,0xcc,0x10,0x2f,0x83,0x7d,0x34,0xec,0x3f,0xda,0x74,
-0x62,0x43,0x29,0x16,0x4b,0x63,0x3e,0x25,0x59,0x27,0x27,0x51,0x47,0xc0,0x75,0x66,
-0xcf,0xa0,0x3f,0xb0,0xc1,0x50,0xa0,0x3e,0xf5,0x25,0x38,0xb6,0x51,0xcc,0xa7,0xe3,
-0x13,0x70,0x5e,0x15,0xe9,0xe5,0x63,0x35,0xe9,0x0d,0xd3,0x11,0xc1,0x0f,0xf9,0xa9,
-0xe7,0x96,0x2a,0xd2,0xc6,0xe5,0x43,0x73,0x21,0xd9,0x1c,0x40,0x3f,0x60,0x65,0x81,
-0x3d,0x81,0xa9,0xba,0x0c,0xd4,0x64,0x1e,0x84,0xf2,0xd4,0x96,0xe2,0x9d,0xe5,0xdc,
-0x52,0x53,0x74,0x9a,0xc8,0x67,0x7e,0x2e,0xea,0x3e,0xf8,0x11,0x85,0xf6,0x44,0xec,
-0x4d,0x65,0x09,0xf2,0x75,0xe6,0x2b,0xce,0xe2,0x02,0xa5,0x18,0xe2,0x73,0x3d,0x76,
-0x67,0x7a,0x69,0xe8,0xa1,0x6c,0xee,0xa0,0x2e,0x22,0x7f,0x20,0x26,0xd7,0xe2,0x71,
-0xf0,0x1d,0xa0,0x20,0x96,0x73,0x3f,0x32,0x13,0x9e,0x09,0xf6,0x97,0xcd,0xa3,0x6c,
-0xf9,0x6f,0xd1,0xb8,0x6a,0x9a,0x03,0xd8,0xb6,0x45,0x0f,0xdc,0x57,0xa5,0xcd,0xc9,
-0xe6,0x7a,0xc6,0xa4,0xb0,0xfe,0xb3,0xf1,0x79,0xd2,0xd1,0x91,0x1a,0xaa,0x45,0x3b,
-0x6c,0x5e,0x9a,0x9e,0x99,0x1a,0x17,0x69,0x35,0xd9,0xdc,0xa4,0xfe,0xa2,0x6e,0xcb,
-0xf2,0xa9,0x56,0x7d,0xa6,0xa5,0x33,0x0d,0x7d,0x86,0x7e,0x30,0x5f,0x42,0x66,0xa7,
-0xa9,0x5c,0xf8,0x6f,0xe9,0xd8,0x49,0x1f,0x26,0x1c,0x78,0x9a,0xfa,0xc8,0xfa,0xde,
-0xac,0xcd,0x8c,0x9f,0xa7,0xa9,0xc5,0xc7,0x20,0xb5,0x27,0x92,0xfb,0x82,0x9e,0x4a,
-0xf4,0xcd,0x54,0x8f,0xeb,0x0d,0xc5,0x75,0x8a,0x73,0x2c,0x7e,0xb5,0xcc,0xcb,0xab,
-0x29,0xec,0x41,0xdc,0x33,0xde,0x57,0x45,0x1b,0x65,0xf4,0x4b,0xed,0x88,0x4c,0x2f,
-0x2c,0x8a,0xcc,0x07,0xa5,0xcc,0x21,0xcc,0x36,0xeb,0x19,0x9f,0xcb,0x6a,0x2a,0x3e,
-0x45,0xac,0xa6,0xb1,0x0e,0x9f,0xb3,0x18,0x03,0xca,0x62,0x6b,0xa3,0x8e,0x2d,0x11,
-0x3b,0xe9,0x78,0x6d,0x4b,0xe5,0x55,0x8d,0x3e,0x6d,0xa4,0x8e,0x16,0xb7,0xd1,0xf8,
-0x8a,0xdb,0x32,0x83,0xaf,0x2a,0xc9,0xe5,0x2b,0xc4,0xff,0x4a,0xc6,0x3a,0x74,0xcc,
-0x26,0x79,0x53,0x5b,0x4d,0xe6,0x39,0x9d,0x67,0x98,0xab,0xa6,0x71,0xfa,0x4f,0x79,
-0x50,0x1c,0x91,0xf1,0x2f,0x5b,0xbf,0x42,0xc7,0x4d,0x8d,0x9f,0xf9,0x79,0x4a,0x3e,
-0x60,0xaa,0x8e,0xe7,0x2a,0xf3,0xcf,0x92,0xf5,0x36,0xc3,0x73,0x4a,0x9b,0xac,0x2f,
-0x01,0xcb,0x93,0xfa,0x0d,0x7e,0x04,0xc4,0xdf,0x80,0xe9,0xd4,0xd7,0x03,0x9a,0x1c,
-0xf9,0x8a,0xa3,0xd4,0xa1,0x94,0x3a,0x0b,0x14,0x27,0xd4,0xe3,0xbe,0x0a,0xf2,0xde,
-0xf0,0x15,0xc9,0x5c,0xa3,0x34,0x60,0x7f,0xd0,0x06,0x8c,0x11,0xf2,0xf6,0x86,0xdf,
-0x92,0x9c,0x6b,0x99,0xe2,0x1b,0x1f,0x3b,0xc7,0x8e,0x4c,0xdb,0x90,0xb6,0x2b,0xb1,
-0x27,0x46,0x5f,0xe9,0x6c,0x1f,0xf3,0x8f,0xf1,0x82,0xd3,0x9c,0xee,0x39,0xad,0x27,
-0xc3,0xc4,0x74,0x98,0x61,0x69,0xe3,0x55,0x73,0x5d,0xde,0x7f,0x5a,0x5d,0x95,0x3c,
-0xe1,0x63,0xc5,0xc2,0xf3,0xa2,0x56,0xb9,0x53,0x53,0x1e,0x86,0x72,0x56,0x35,0x1a,
-0x7d,0x2c,0x39,0xa6,0xd5,0x03,0x72,0x87,0xda,0x54,0x4e,0x33,0x6d,0x43,0xc8,0x31,
-0x61,0x07,0x8a,0xf8,0xae,0x54,0x5e,0x92,0x79,0x68,0xc2,0xb9,0x34,0x3c,0x7e,0x9a,
-0x87,0xa5,0x7c,0x09,0xce,0x3c,0x4e,0x3b,0xb2,0xf1,0x08,0xba,0x46,0x79,0xa5,0x8a,
-0xf7,0x4d,0xed,0x31,0xbb,0x6e,0x9a,0x87,0x36,0x11,0xd3,0x69,0x0c,0x4b,0x71,0x9a,
-0xc7,0x13,0x68,0x8f,0x0c,0x8c,0xcc,0x49,0x15,0xd3,0xba,0x20,0x9d,0x5f,0x16,0x72,
-0x35,0xe1,0xa1,0x2a,0xe2,0x19,0xcf,0x01,0x58,0x8d,0xcb,0xa8,0xab,0xb0,0xf6,0x14,
-0xd1,0x17,0xc1,0xb8,0xd9,0x88,0x9d,0x99,0xfd,0x85,0xfa,0xb4,0x9e,0x81,0xeb,0x44,
-0xa6,0x98,0x0f,0xd5,0xf1,0x9a,0xad,0xe5,0x52,0x7f,0x09,0xeb,0x80,0x8d,0xd6,0xd7,
-0x5d,0x6d,0x89,0xd8,0x8d,0xce,0x47,0xa4,0x0f,0x79,0x8f,0x32,0xc4,0x36,0xa8,0xbd,
-0x34,0xd9,0x28,0x94,0x79,0x72,0x8e,0x0b,0xf3,0x91,0xd9,0x73,0x01,0x4f,0x1e,0x23,
-0x3e,0xce,0xf4,0xb0,0xd2,0x69,0x94,0x89,0x81,0x4d,0x59,0xcc,0x52,0xa8,0x0b,0xb2,
-0x82,0xf8,0x17,0x73,0xda,0x34,0x97,0x82,0xf5,0xd0,0x37,0xe2,0x3c,0xe1,0x73,0xc6,
-0xaa,0x0f,0xea,0x0f,0x20,0xff,0x01,0x53,0x21,0xfe,0xd6,0x63,0x6f,0xad,0x3f,0x1c,
-0x13,0x3c,0x07,0x8c,0xaf,0x28,0x52,0x2a,0x4a,0x0b,0x95,0x52,0x88,0xa5,0xa1,0x6f,
-0x3a,0x6e,0xf8,0x0d,0x74,0x53,0x5d,0x32,0xe6,0x88,0x22,0xfa,0x21,0x30,0xff,0xc0,
-0x5f,0x80,0x36,0xa1,0x2f,0x7b,0x5e,0x12,0xcb,0x73,0x08,0xbf,0xac,0x38,0x46,0xc6,
-0x49,0xc7,0x62,0xd8,0x8c,0x27,0xc4,0x70,0x3a,0x26,0x83,0x47,0xd4,0x2f,0xb3,0x68,
-0x5d,0xe6,0xcf,0xc9,0x9e,0x53,0xfc,0x14,0xf4,0x96,0xcb,0x4a,0x15,0xc7,0xa6,0xd3,
-0xc2,0xd6,0xe0,0xb8,0x0d,0x95,0xb5,0x41,0xdb,0xb6,0xec,0x2b,0x1d,0x1f,0x36,0xc1,
-0x1a,0x3a,0x4f,0x85,0xdc,0xa8,0x2a,0x9e,0xd1,0x8f,0xb7,0x5a,0x4b,0xa1,0xb6,0x42,
-0xaa,0xc3,0xe9,0x28,0xc6,0xf7,0xa8,0x1e,0x28,0x62,0x3b,0xc2,0xf8,0x99,0x14,0xb9,
-0x2e,0xd1,0x6b,0x53,0xc1,0x71,0x2a,0xe6,0x7c,0xad,0xc9,0xee,0x53,0xf9,0xb0,0x7b,
-0x26,0xcc,0x20,0x74,0xcb,0x64,0x94,0x8d,0xcc,0xb2,0x39,0x04,0x9d,0xe5,0xbe,0xd4,
-0x63,0xb4,0x41,0xef,0x99,0xe6,0x0b,0xb5,0xd9,0xaa,0x79,0xbc,0x26,0xbe,0xf0,0x39,
-0xa0,0x30,0x19,0xa8,0x72,0x6c,0x36,0xf2,0xca,0x39,0x04,0xf3,0xc9,0xba,0x1f,0xc5,
-0x7b,0xac,0x4f,0x71,0x52,0xba,0xd6,0x4c,0xc7,0x43,0xe6,0x95,0x09,0x8f,0x99,0x5d,
-0x15,0x72,0x07,0x7c,0x2c,0x64,0xbc,0x56,0xbe,0x2d,0x1f,0x2b,0xd0,0x88,0x6b,0x93,
-0x14,0x8f,0x0d,0x9a,0x92,0xb6,0x18,0xeb,0x19,0xb8,0xce,0xfa,0xc3,0xb6,0x00,0x5f,
-0xf8,0x1a,0x27,0xf2,0x48,0x5f,0x07,0x25,0xf9,0x53,0x69,0x7f,0x0a,0xc3,0x74,0xe2,
-0x03,0x21,0x9f,0xb9,0x5d,0x14,0xe6,0x18,0xf9,0xcd,0xf5,0x82,0xf2,0x17,0x65,0x94,
-0x6d,0xac,0xf7,0x38,0x07,0xca,0x59,0x88,0x43,0xd5,0x44,0xde,0x3c,0xeb,0x58,0x53,
-0xab,0x0b,0x74,0x03,0xae,0x62,0x1c,0x0c,0xb9,0x11,0xd4,0x33,0xec,0x8f,0xb6,0x2d,
-0xd8,0x3e,0x6e,0xdb,0x2c,0xe8,0x35,0xf9,0xab,0xc9,0x5c,0x3a,0xe0,0x35,0xe4,0x06,
-0x90,0x66,0xa8,0x07,0x98,0x5b,0xe9,0x54,0x2a,0x5d,0xc5,0x8a,0x0b,0xea,0x40,0x5d,
-0x4a,0x2f,0xae,0xb9,0xa3,0xfe,0xf0,0x38,0x1b,0xe9,0xd0,0x73,0x42,0xda,0x58,0x20,
-0x1e,0x87,0xb1,0x41,0x5b,0xa8,0x4f,0x5c,0x1f,0x36,0xe3,0xb7,0xc9,0x2e,0xd2,0x39,
-0xf7,0x38,0x87,0x9a,0xb2,0x67,0xa8,0x43,0x74,0x8d,0x83,0xb7,0x2d,0xcc,0x49,0x59,
-0xdf,0xcc,0x76,0x51,0xf9,0xe0,0xfb,0xbc,0x2e,0xc7,0x15,0xd9,0xbc,0x37,0x6c,0x20,
-0x6d,0xff,0x27,0xb2,0xf5,0xb2,0xf6,0xa5,0x76,0x88,0xee,0x97,0x90,0xc4,0x48,0xc6,
-0xde,0x24,0xb2,0x5f,0x55,0xc0,0x3a,0x6e,0xd3,0x39,0x0e,0xc8,0x68,0xe2,0x36,0x9e,
-0xfb,0x06,0x0a,0xc3,0x0c,0xd5,0xe8,0x48,0x8a,0x97,0x56,0x63,0x36,0xe9,0x97,0x6a,
-0x91,0x73,0x90,0xf9,0x28,0x9c,0x36,0x0b,0x3c,0x97,0xe1,0x15,0x9f,0xcb,0x74,0xcc,
-0x4f,0x2a,0xc3,0x74,0xf7,0x32,0xe1,0x4d,0xba,0x3e,0x64,0xba,0xc2,0x7f,0xcb,0xf4,
-0xd9,0x18,0x2f,0x9b,0x4b,0xd4,0x9e,0xd2,0xe7,0xd4,0x9f,0xa2,0x3a,0x68,0xe4,0x93,
-0x69,0x2c,0x6b,0x4b,0xad,0x1b,0x1b,0xb6,0x49,0x25,0xc5,0x96,0xc2,0x2e,0x2c,0x88,
-0xed,0x74,0xbd,0x59,0x16,0x8f,0x73,0x3c,0xe6,0xfa,0xc1,0xf7,0x04,0x0b,0x71,0xb8,
-0x22,0x69,0xc3,0x26,0xc7,0x75,0xea,0x1f,0xe0,0x7e,0x23,0xb0,0xd3,0x74,0xcf,0xb4,
-0xc0,0x4f,0x35,0x99,0xe7,0x25,0xf1,0xb5,0xe0,0x9f,0x10,0xdc,0xc7,0x76,0x74,0x8c,
-0x41,0xbf,0x87,0xe0,0x02,0xb4,0x0f,0x36,0x1b,0x72,0xa9,0xb8,0x2e,0xca,0x63,0x6f,
-0x1d,0x03,0x6c,0x09,0x7e,0x23,0xde,0x1b,0x38,0x4f,0xf6,0xd6,0x53,0xb9,0x1b,0x7a,
-0x21,0xb1,0xe1,0xdc,0x46,0x60,0xbc,0xa9,0x63,0xba,0xfa,0x13,0x62,0x3a,0xe1,0x1f,
-0xd5,0x31,0x1d,0xcf,0x93,0xfc,0xca,0x26,0x47,0x00,0x75,0x81,0xb7,0x25,0x85,0x4a,
-0x09,0x14,0xe4,0x1f,0x8e,0x03,0xbb,0x44,0x3b,0x69,0x22,0x85,0xd8,0x2c,0xd9,0x88,
-0x75,0xde,0x93,0x75,0x0f,0xf4,0x6d,0x41,0x56,0xe5,0x45,0x4a,0xb9,0x8e,0xd7,0xb6,
-0xc4,0x9e,0x76,0xa8,0x07,0x72,0x74,0x39,0x15,0xd7,0x96,0x52,0x65,0x4b,0xb9,0x43,
-0x29,0xd7,0xb1,0x9e,0xb4,0xaf,0x63,0x74,0xd2,0xcf,0xe3,0x78,0x6e,0xc4,0xb4,0x4a,
-0x62,0x8f,0x1c,0x3c,0x87,0x9c,0x03,0x8c,0x0b,0xf0,0x1c,0xf7,0xdc,0xf1,0x7c,0x4d,
-0x3a,0x56,0xcb,0xe4,0xfd,0xa4,0xb2,0xe5,0xb6,0x5a,0xf0,0x45,0x2c,0xda,0x96,0x62,
-0x87,0xc2,0xf0,0x82,0xd9,0x63,0x69,0xbf,0xcc,0x57,0x95,0xf9,0xe7,0xc2,0x3c,0x20,
-0xef,0xca,0x1a,0x34,0x3d,0x57,0x85,0x1b,0xd6,0x78,0x60,0xc1,0x41,0x61,0xce,0xb2,
-0xdc,0xa5,0x6c,0x4d,0xd2,0x2a,0x2e,0x92,0xca,0x6c,0x33,0x9a,0xc4,0xc1,0x08,0x7c,
-0xe2,0xb6,0x81,0xe3,0x01,0xe7,0x91,0x8c,0xd7,0x69,0xfb,0x64,0xe3,0x47,0x3c,0x31,
-0x70,0x45,0x25,0x3c,0x91,0xac,0x1f,0xc8,0x70,0x5e,0xd8,0x37,0x25,0xc3,0x05,0x89,
-0xfc,0xa5,0xfa,0x90,0x05,0xfd,0x66,0x36,0xa6,0x7e,0x64,0xf5,0x0e,0x93,0x81,0x89,
-0x3f,0xb2,0x77,0x55,0x51,0xe6,0xd4,0x56,0xf2,0x79,0x43,0x1a,0x93,0xfa,0x65,0xbc,
-0x0f,0x19,0x0f,0x4d,0xf9,0xe2,0x9c,0x44,0x4e,0x99,0x9e,0x0d,0x9c,0x26,0x71,0x38,
-0xd5,0x5d,0x3d,0x0e,0xcc,0x25,0x31,0x30,0xf9,0xe6,0xc6,0x84,0xed,0x32,0xbc,0x4d,
-0x53,0xd2,0xee,0xc9,0xa3,0x6d,0x61,0x9c,0xa5,0x9a,0x73,0xe1,0xd4,0x47,0x40,0xbb,
-0xab,0xc7,0xcf,0xb9,0x29,0x5b,0x8a,0x78,0x83,0x98,0x4d,0xb1,0x1f,0xf3,0xf4,0x74,
-0x4e,0xd3,0xf5,0x5d,0xdc,0xe3,0xcc,0x63,0x3d,0xfd,0x9b,0xa6,0xbc,0x44,0xce,0x18,
-0xd7,0x81,0x65,0x36,0x1e,0x79,0x4c,0x7d,0x1b,0xba,0xa6,0x6f,0xc8,0x8e,0xe9,0xb3,
-0x55,0xce,0x8e,0x16,0x9a,0x4f,0x10,0x62,0xe7,0xa7,0x7c,0x18,0xf3,0x8e,0xea,0xae,
-0x92,0xf0,0x29,0x30,0x47,0x90,0x69,0xcf,0xc0,0x7f,0x88,0x87,0x21,0xb7,0x5d,0xe6,
-0x50,0xca,0x50,0x4e,0xa0,0x53,0xc0,0x2f,0x9d,0x6f,0x49,0x1e,0xa1,0x1f,0xc4,0xe7,
-0x87,0x15,0xc6,0xe9,0x7c,0x53,0x44,0x39,0xe1,0x5e,0x76,0xc0,0xea,0x0a,0x87,0x52,
-0x01,0xb9,0x6f,0x6c,0x0f,0x78,0xe7,0x2a,0x52,0x5c,0x5b,0xcb,0x94,0xad,0xd5,0xc5,
-0x4a,0x35,0xc8,0x92,0xfa,0x10,0x3a,0x96,0xe7,0x26,0xde,0x37,0xe2,0xec,0x1c,0xb2,
-0xcf,0x92,0xf0,0x01,0x9e,0xc3,0x3e,0x3a,0x18,0x13,0xe4,0x00,0xf4,0x3c,0x7b,0x12,
-0xff,0xf5,0x71,0x49,0xf8,0x23,0xb3,0x1b,0xd4,0xc6,0x19,0x7d,0xa8,0x62,0xdd,0x4c,
-0x0f,0x19,0x86,0x23,0x06,0x99,0xb0,0x53,0x15,0xdf,0xa1,0xb6,0x49,0xd6,0xb0,0x51,
-0xdf,0x42,0x0e,0xbc,0x7f,0xee,0xdf,0x9b,0xf0,0x8a,0xe8,0x15,0xa5,0x87,0xf2,0x26,
-0xdd,0x38,0xb3,0xe1,0x0e,0xc5,0x0c,0x83,0x3e,0xb6,0x37,0x87,0xe6,0x38,0x65,0x36,
-0x92,0x8e,0x47,0xea,0xd7,0xa8,0xec,0xbc,0x09,0x0d,0x26,0x0c,0x27,0xfc,0x93,0xe1,
-0xb6,0x70,0xe6,0xb6,0x41,0xb1,0xa0,0x29,0x8b,0x43,0xf0,0x1b,0x18,0x7d,0xd4,0xe7,
-0xe1,0xfe,0x8f,0x74,0xef,0x16,0xc1,0x71,0xbe,0xa6,0x22,0x3c,0x47,0x79,0xf0,0xfd,
-0xd4,0x0c,0xfb,0xb2,0x1d,0x07,0xbf,0x61,0x9c,0xd3,0xcc,0xc9,0x74,0x7a,0x6d,0x75,
-0xcf,0xc4,0x2f,0xc5,0x2c,0x47,0xa9,0x2d,0x97,0xdd,0xb7,0xb8,0xe6,0xfc,0xa6,0xb8,
-0x4e,0x31,0x5a,0xb7,0x57,0xb9,0x04,0xdf,0xc9,0x77,0x5a,0x78,0x8d,0xf5,0xc0,0x06,
-0xa3,0x8d,0xa3,0x31,0x8b,0x2c,0x26,0x17,0x6c,0x4a,0x12,0x8f,0x29,0x2e,0xd3,0xf9,
-0xa3,0xfb,0xbd,0x0c,0xb3,0xd3,0xd9,0x24,0x99,0x3f,0x8d,0x79,0x51,0xa0,0x0f,0x63,
-0x68,0xc4,0x5a,0xca,0x1b,0xb4,0xf3,0x88,0xd9,0x42,0xbc,0xae,0x26,0x62,0x79,0x18,
-0xa7,0xfe,0x1d,0x72,0x72,0x2f,0x34,0xf7,0x75,0xe0,0x3d,0x78,0x8e,0xb9,0x55,0x68,
-0x0f,0xd7,0xd5,0x71,0x9e,0x63,0x0c,0x4b,0xf3,0xfc,0xb8,0x16,0x4b,0xd7,0xfc,0x85,
-0xb9,0x48,0x75,0xc0,0x4a,0xbe,0x4a,0xc2,0xcf,0xc1,0xb1,0x66,0x1b,0x27,0x67,0x7b,
-0x70,0xac,0xc1,0x71,0xa0,0xcf,0x94,0x69,0x3b,0x50,0x17,0x70,0xaf,0xaa,0x58,0xa9,
-0x02,0x4c,0xc7,0x18,0x96,0xe6,0x38,0x50,0xdf,0x84,0xb9,0xa5,0xa6,0xf0,0x5a,0xb0,
-0xfb,0x8c,0x46,0xae,0xe7,0xe0,0x97,0x95,0x15,0x2a,0x65,0x5b,0x4a,0x94,0x2d,0x20,
-0x27,0xe4,0x11,0x3c,0x83,0xfe,0x1b,0x2a,0x95,0x86,0x6d,0x15,0xca,0x36,0xd8,0x07,
-0xc7,0xd7,0xd4,0x81,0x2e,0xcc,0xc1,0x70,0x3d,0xc7,0xfe,0x40,0x67,0xa1,0x0e,0xe0,
-0x38,0xe4,0xec,0xa1,0x2f,0xd8,0x57,0xa7,0x7f,0x8b,0x97,0xc9,0x7a,0x08,0x8e,0x4b,
-0x86,0x77,0x9b,0xe0,0x58,0xda,0x23,0x69,0xcf,0x8d,0x1c,0x85,0x8d,0xed,0xa1,0x64,
-0x78,0x89,0xe3,0xe6,0x7a,0x98,0x6a,0x8a,0x15,0x22,0x13,0xa1,0xde,0x26,0x3e,0xbd,
-0xcc,0x46,0xcb,0xf8,0x91,0x16,0x23,0xf1,0x9a,0xf5,0x2f,0xd0,0xca,0xfd,0x15,0x25,
-0x25,0x57,0x3c,0x1b,0x39,0xca,0x9c,0xd4,0xfe,0x5a,0x2c,0x42,0x4e,0x12,0xf3,0x74,
-0x36,0x39,0xce,0x70,0x1a,0x65,0x36,0xde,0xf8,0x4d,0xde,0xe5,0x36,0x4e,0x36,0xc7,
-0xd3,0xda,0x7e,0x49,0x11,0xc6,0x4b,0x71,0x90,0xf0,0x54,0x46,0x97,0x89,0xbf,0x32,
-0xfa,0x89,0xde,0x50,0x19,0x53,0x59,0x53,0xdb,0x6c,0x7c,0xcf,0x99,0x26,0xbe,0xe7,
-0xbc,0x90,0xe9,0x8a,0x6c,0x6e,0xc8,0x64,0x6f,0xc5,0xf3,0x74,0x07,0xe7,0x1d,0x6b,
-0x44,0xa5,0x67,0xe1,0x31,0xf7,0x3f,0x29,0xff,0x54,0x56,0x4f,0xe2,0x9f,0xa5,0xcd,
-0x53,0x50,0xfc,0xb6,0xc8,0x79,0xf0,0xb8,0x98,0xe2,0x3a,0xd8,0x3c,0xc4,0x68,0x38,
-0xc3,0x6f,0xfa,0xbd,0x2c,0xd5,0x6b,0x03,0x2f,0x93,0xf5,0x71,0xff,0xae,0xc9,0xe6,
-0x49,0xbe,0x71,0xe7,0x31,0x35,0xfd,0x7e,0x8e,0xee,0x1b,0x36,0x6c,0x8f,0x4d,0x2e,
-0x73,0xee,0x47,0x0b,0xfb,0x52,0x48,0xfc,0x0c,0x34,0x81,0x6d,0xc5,0x3d,0x50,0x74,
-0x1f,0x9b,0x6e,0x8b,0x93,0x71,0x15,0xc4,0x65,0xb0,0x77,0x09,0xde,0x31,0xfe,0x77,
-0x8c,0x9a,0xfa,0x1f,0x20,0xb8,0x77,0x8b,0xe2,0x3a,0xf2,0x43,0xc7,0x7c,0xad,0x0f,
-0xc8,0xb1,0x42,0x5c,0xe6,0xb4,0x2b,0x4e,0xfc,0xa6,0xda,0xe0,0x3d,0xf9,0xff,0x25,
-0x88,0x5b,0xfa,0xbd,0xe4,0x1e,0x3c,0x43,0xde,0xaa,0xe8,0xa7,0x22,0x3e,0xc9,0x6c,
-0x24,0xd6,0xd1,0xf7,0x65,0x6b,0xf4,0xe9,0xbe,0x44,0xf2,0xfb,0xaa,0x4c,0x75,0x39,
-0x2b,0x9d,0x27,0x3e,0x15,0xa5,0x45,0xc7,0x73,0xf6,0x3f,0x59,0xd2,0xb5,0x03,0xe3,
-0x07,0xec,0xac,0x29,0x55,0x6a,0x00,0xff,0x40,0x77,0xd0,0x2f,0x44,0x59,0xa3,0xce,
-0x09,0x76,0x5f,0x4d,0xad,0xdf,0xcb,0xec,0x17,0xf2,0x99,0xda,0x65,0x3d,0xaf,0x5f,
-0xa0,0x94,0xd4,0x95,0x2a,0x75,0x10,0x7f,0x03,0xaf,0xa1,0x3e,0x8c,0x01,0xf0,0xb7,
-0xa9,0x4a,0x69,0x72,0x57,0x2b,0x6e,0x78,0x06,0xfc,0x43,0xde,0xe1,0xb8,0x80,0xaf,
-0xc8,0x5b,0xb4,0xef,0x74,0xfc,0xd0,0x17,0xe8,0x05,0xe4,0xeb,0xab,0x4b,0x94,0x6a,
-0xcc,0xe7,0xe3,0x7e,0x76,0xab,0xb8,0x5c,0x60,0x08,0xb3,0x65,0xc2,0xf8,0x1e,0x53,
-0x96,0xc6,0x1c,0x61,0x31,0xa5,0xcc,0x6e,0xc9,0xf0,0x82,0x3f,0x17,0x74,0x32,0x29,
-0x0b,0x8a,0x0d,0x7a,0xbd,0x4d,0x70,0x9c,0xda,0x2b,0x2b,0x3f,0xc0,0xb8,0x96,0xe0,
-0x11,0xc7,0x72,0x19,0x6f,0xac,0xb0,0x1d,0xed,0x0d,0x8f,0xb9,0xf5,0x92,0x9c,0x83,
-0xba,0x1d,0x4c,0xae,0xd5,0x51,0x59,0xa3,0x1d,0xe2,0x63,0x4b,0xd7,0xaf,0x71,0x4f,
-0x15,0x71,0x4f,0xea,0xd7,0x70,0x3f,0x9e,0xc9,0x9f,0xdb,0x70,0x93,0x9c,0x24,0x18,
-0x42,0x79,0x44,0xe7,0x8f,0x09,0xfb,0x55,0xb1,0x3f,0xa3,0x9d,0x4c,0xb5,0x8e,0xb6,
-0x49,0x68,0xa4,0xff,0x03,0x84,0xae,0xdf,0x0a,0xb1,0x58,0x9a,0xef,0xab,0x65,0x71,
-0xa1,0x54,0x9f,0x64,0xba,0x9b,0x21,0xed,0xdc,0x4f,0xe1,0xd8,0xcc,0xf5,0x10,0xab,
-0x82,0xee,0x94,0x95,0x2a,0x65,0xb5,0xb5,0x6a,0x6d,0x6d,0x8d,0x52,0x5b,0x59,0xa1,
-0x56,0xda,0xed,0x09,0xbb,0xc2,0xdb,0x12,0xda,0xe3,0x73,0x85,0xc9,0x97,0xe2,0xb6,
-0x54,0x3f,0x24,0xfe,0x1e,0xae,0x7f,0x5a,0xc5,0xeb,0xfa,0xf7,0x35,0x79,0x09,0x7c,
-0xc6,0xff,0x8f,0x65,0xec,0xfd,0x42,0x7c,0xcf,0x4d,0xf9,0xaf,0xf4,0x1d,0xc4,0x44,
-0x7c,0x0f,0x7c,0x02,0xc4,0xf6,0xa2,0x22,0x5b,0x51,0xcd,0x96,0xdc,0x9a,0xed,0xdb,
-0xed,0xdb,0xb7,0xd6,0xe5,0x6d,0x2d,0x2f,0xcf,0x29,0xb7,0xdb,0x55,0x3b,0xca,0x96,
-0xae,0xe5,0x1b,0x39,0x7e,0x9a,0x27,0x20,0xfe,0x01,0xda,0x6d,0x61,0xff,0x1e,0xc3,
-0x75,0xfd,0x59,0x4e,0x6a,0x2d,0x1c,0x63,0x68,0x88,0x0b,0x13,0xb8,0xac,0x16,0x96,
-0x97,0xe7,0x95,0x6f,0xdd,0x5a,0xb0,0xb5,0xa1,0xbe,0xb0,0xa1,0x79,0x87,0xa3,0xb9,
-0xa5,0xb9,0xb0,0xc5,0xef,0x2e,0xf4,0xfb,0x9a,0x0b,0x7d,0x4d,0x3b,0x1c,0x4d,0x8d,
-0x0d,0x8e,0xc6,0xfa,0x7a,0x47,0x3d,0x9c,0xe1,0xb7,0xaf,0xd9,0xe1,0x0b,0x78,0x0a,
-0x03,0x7e,0xb7,0xc3,0xef,0xde,0xe1,0x70,0xef,0x68,0x28,0xda,0xd1,0xb4,0xc3,0xd9,
-0xe4,0x75,0x3b,0xbd,0x81,0x16,0x67,0xa0,0xdd,0xef,0x6c,0xef,0x0c,0x3a,0x3b,0x77,
-0xb7,0x3a,0x77,0xef,0x0c,0x3a,0x77,0x06,0x5b,0x8a,0x83,0x5e,0x8f,0xd3,0xeb,0x71,
-0x17,0x7b,0x3c,0x9e,0x62,0x8f,0xd7,0x5b,0xec,0x6d,0xf1,0x16,0xb7,0x04,0x5a,0x8a,
-0x03,0x70,0xf6,0x7a,0x8a,0xbd,0x50,0xfc,0xde,0x62,0x7f,0xc0,0x57,0x1c,0xf0,0xb8,
-0x4b,0x3c,0x6e,0x77,0x89,0xdb,0xeb,0x29,0xd1,0xee,0x97,0x7a,0xe1,0x1a,0x8a,0xc7,
-0x53,0xe2,0x81,0x67,0x7a,0xd1,0xae,0xe1,0x99,0xd7,0x5d,0xea,0xf5,0x78,0x4a,0xb5,
-0x7b,0x5a,0xf1,0x94,0x79,0xfc,0xbe,0x52,0x7f,0xbb,0xbf,0xa4,0x3d,0xd8,0x52,0x1a,
-0xf4,0x79,0xcb,0x7c,0x70,0xbf,0xa9,0xb9,0xb4,0xa9,0x7e,0x7b,0x49,0x7d,0x45,0x85,
-0xa3,0x42,0x63,0x68,0xee,0x93,0xa2,0xbc,0xc1,0x77,0x8c,0x53,0x94,0x44,0xec,0x87,
-0xbe,0x5f,0x26,0xd8,0x03,0xef,0x80,0xbe,0x54,0x39,0x95,0xaa,0xed,0x15,0xca,0x76,
-0xc0,0x41,0x67,0x81,0xcd,0x59,0x53,0xe5,0xa8,0x69,0xde,0x51,0xde,0xec,0x71,0x57,
-0x6a,0xe3,0xab,0xf4,0x06,0x7c,0x95,0x01,0x9f,0xb7,0xd2,0xe7,0x76,0xbb,0xb4,0xf1,
-0x57,0x6a,0x63,0x74,0x69,0x63,0x75,0x69,0xcf,0x5c,0x5e,0xa8,0x03,0xd7,0xf0,0xcc,
-0xed,0xae,0x74,0xbb,0x3d,0x70,0xd6,0xea,0x69,0xf7,0x7c,0x5e,0x97,0xcf,0xef,0x75,
-0xf9,0xf5,0xe2,0x73,0xf9,0xdb,0x03,0xae,0xf6,0xae,0x9d,0x15,0x5d,0x47,0x3a,0x2b,
-0x8e,0x74,0x04,0x5c,0x1d,0xd8,0x4e,0x87,0xdf,0xd5,0x71,0x7c,0x4f,0xf9,0xf1,0x9f,
-0x1f,0x28,0xff,0xf9,0xd1,0xce,0x8a,0xa3,0x50,0x0f,0xda,0x76,0xbb,0xab,0x34,0xfe,
-0x57,0x69,0xfd,0xbb,0x02,0x70,0x0f,0x4a,0x6b,0x8b,0xab,0x35,0xe0,0xab,0x0a,0x78,
-0xdd,0x95,0xde,0x9a,0xea,0xd2,0x1a,0x4d,0xf9,0xf3,0x60,0x2c,0xa0,0x5b,0xe0,0xc3,
-0xc1,0xba,0x7b,0x5d,0x99,0x52,0x07,0x7b,0xe9,0xc0,0x77,0x40,0xbf,0x31,0xdd,0x7a,
-0xb9,0xd4,0xf6,0xb1,0xfd,0xa6,0x58,0x57,0x53,0x7a,0x5b,0x49,0x49,0x51,0x49,0x7d,
-0x83,0xab,0xde,0xed,0xde,0xa2,0x8d,0x77,0x8b,0x7b,0xdb,0x36,0xd7,0x36,0x67,0x71,
-0x91,0x53,0x85,0x56,0x08,0x6f,0xb1,0x3d,0x9c,0x9f,0xc2,0x1e,0x3c,0x62,0xf7,0x29,
-0xce,0xd1,0x78,0x07,0x1f,0x73,0x3b,0xc9,0xff,0x47,0x9c,0xc9,0x8f,0xa2,0xb9,0x37,
-0xba,0xef,0x5f,0x96,0x67,0x60,0x78,0x21,0xe0,0x38,0xfa,0x49,0xda,0xe1,0xaa,0x2c,
-0x73,0xb9,0x9b,0x6b,0xdc,0xfe,0x96,0x3a,0xbf,0xd7,0x53,0xeb,0xad,0xab,0x73,0xd5,
-0x15,0x39,0x0a,0x8b,0xb8,0x9e,0x99,0xec,0x32,0xf1,0xfd,0x4d,0xf9,0xc8,0xa4,0xbd,
-0xa2,0xc5,0xc8,0x33,0x12,0x0c,0x37,0x68,0xb7,0x49,0xec,0x29,0x1f,0x8b,0x84,0x16,
-0xca,0x97,0x4c,0x71,0xc8,0xe4,0x0f,0x61,0x0c,0xa4,0x88,0xfe,0xbd,0x6c,0x4e,0x59,
-0x62,0x3a,0x65,0x0b,0xf7,0x13,0x78,0xdf,0x04,0xf7,0x0d,0x1d,0x21,0x71,0x86,0x0c,
-0xa3,0xa4,0xb4,0xb0,0x3e,0x11,0x6b,0x4c,0xeb,0x19,0x64,0x9f,0x36,0x8d,0xe1,0x84,
-0xfd,0x55,0x56,0x71,0x3d,0x79,0xc6,0xff,0xa7,0x53,0x3a,0xbf,0x31,0x5b,0xac,0x47,
-0x7e,0xd9,0xf3,0x15,0xbb,0xd7,0xab,0x7a,0x4f,0xbf,0x9a,0x73,0xfa,0x0f,0xbf,0xcf,
-0xfb,0xc3,0xfb,0x7f,0xb1,0xbf,0x7f,0xf6,0x43,0xfb,0x59,0x28,0x67,0xfe,0xcb,0x7e,
-0xe6,0x9d,0xb7,0xed,0xef,0xfc,0xfa,0x5f,0x73,0x7f,0xbd,0x6b,0x97,0xba,0xab,0xc8,
-0xa9,0x14,0x51,0xbe,0xc9,0xf8,0x42,0xdb,0xa6,0x73,0x51,0xaa,0x33,0x12,0x5f,0x52,
-0xe6,0x13,0xd2,0x38,0x99,0xe6,0x90,0x71,0xff,0xb6,0x8e,0xe9,0xc9,0xd8,0x96,0x62,
-0xb5,0xae,0xff,0xb8,0xef,0x8c,0xe4,0xeb,0xe1,0x3e,0xd4,0x41,0xdc,0xdc,0xb6,0x25,
-0x67,0xdb,0xc9,0x63,0x8e,0x93,0x6f,0xfd,0x7b,0xc5,0x5b,0x7f,0x7b,0xaf,0xfa,0x6f,
-0x9f,0x7c,0x54,0xf3,0x49,0xcf,0x7f,0xd7,0xf5,0x9c,0xfb,0xb8,0xf6,0xdc,0xc7,0x1f,
-0xd4,0x7c,0xfc,0xa7,0xb7,0xab,0xff,0xf4,0xfa,0x2b,0xa5,0xaf,0x7b,0xdc,0xf9,0x9e,
-0x7c,0x7b,0x62,0x1d,0x1b,0x73,0xee,0xa6,0x35,0x81,0x1c,0xf3,0xbe,0x62,0xc1,0xe7,
-0x4e,0xd2,0xcd,0xeb,0xe8,0xf9,0x77,0x5b,0x22,0x4e,0x03,0xba,0xbc,0x4d,0x05,0xde,
-0x5f,0xbd,0x52,0xfe,0xab,0x0f,0xdf,0xad,0xfd,0xb0,0xe7,0xa3,0x86,0x9e,0xde,0x4f,
-0x9a,0x7a,0xfb,0xce,0x35,0xf7,0x41,0xe9,0x3f,0xe7,0xee,0xbf,0x78,0xae,0xf9,0xe2,
-0x95,0xf3,0xcd,0x57,0xae,0x9c,0x6f,0xba,0x72,0xe9,0x7c,0xf3,0xa5,0x0b,0xe7,0x3d,
-0x17,0xfa,0xcf,0x7b,0xfa,0xa1,0x5c,0x3c,0xef,0xb9,0x78,0xe9,0xbc,0xe7,0xd2,0x60,
-0x8f,0x7b,0x70,0xa0,0xc7,0x3d,0x70,0xa5,0xc7,0x7b,0xe5,0x52,0x8f,0xe7,0xd2,0xc0,
-0x67,0xbe,0x81,0xc1,0xde,0x96,0xc1,0x50,0xaf,0x2f,0x34,0xdc,0xeb,0x1b,0xfe,0xbc,
-0xd7,0xfb,0xf9,0x68,0x9f,0x6f,0x74,0xa4,0xcf,0x3b,0x72,0xb5,0xb7,0xe5,0xea,0x60,
-0x5f,0x60,0x70,0xa0,0x37,0x30,0x00,0x67,0x28,0x43,0x7d,0x81,0xa1,0xe1,0xbe,0xc0,
-0xf0,0x50,0x5f,0x70,0x68,0xb0,0x2f,0x38,0x18,0xea,0x0b,0x86,0x86,0xfb,0x03,0xc3,
-0x57,0xfb,0x83,0x57,0x43,0xfd,0xc1,0x50,0xa8,0xaf,0x2d,0x14,0xea,0x6f,0x0b,0x0d,
-0xf5,0xb5,0x0e,0x19,0xd7,0xfd,0x6d,0x43,0x43,0x17,0xda,0x87,0x86,0xfa,0x53,0x65,
-0xf8,0x42,0xc7,0xf0,0x70,0x7f,0xc7,0xf0,0x50,0x7f,0x87,0x7e,0x3d,0x72,0xa1,0x6d,
-0x64,0xf4,0x42,0xdb,0xe8,0xc8,0xc5,0x8e,0x91,0xab,0x17,0x3a,0xae,0x0e,0x5f,0xd8,
-0x39,0x3c,0xd0,0xdb,0x31,0xd0,0xfb,0x49,0x6b,0xef,0x47,0xef,0xf9,0x3e,0x7a,0xfd,
-0xd5,0x6d,0xaf,0x37,0x36,0x96,0x36,0x66,0x82,0xbb,0x32,0xfd,0x36,0xec,0x36,0x59,
-0x7f,0x85,0xdf,0x98,0xd3,0xe1,0x31,0x8b,0xb4,0x0d,0xad,0x80,0x0e,0xf9,0xea,0x0b,
-0x7d,0x2f,0x3d,0x5b,0xf5,0xd2,0x9b,0xbf,0x69,0x7c,0xf3,0xfc,0x99,0xe0,0xf9,0x81,
-0x73,0x3b,0x07,0x46,0x2e,0xee,0x1b,0xf9,0xf2,0xca,0x81,0x2f,0xc7,0x06,0x0e,0x8c,
-0x4d,0x0c,0xec,0x9f,0x18,0x1f,0x38,0x38,0x0e,0xd7,0x5f,0x0e,0x1c,0xfc,0x72,0x6c,
-0xf0,0xe0,0xd8,0xf8,0x20,0xfc,0xd6,0xce,0x03,0x5d,0xe3,0x63,0x83,0x5d,0x63,0x63,
-0x83,0x87,0xb4,0x7b,0x70,0x7d,0x68,0x6c,0x62,0xb0,0x6b,0x62,0x3c,0xd4,0x35,0x3e,
-0x39,0xd8,0x35,0x39,0x19,0xea,0x9a,0x9c,0x0a,0x75,0x4d,0x5d,0x0b,0x1d,0xbc,0x36,
-0x1b,0xda,0x3b,0xbb,0x38,0xb8,0x67,0x71,0x36,0xb4,0x6f,0x76,0x2a,0x74,0x68,0x6a,
-0x62,0xe8,0xf0,0xc4,0xb5,0x50,0xd7,0xb5,0xc5,0xd0,0xde,0xc5,0xb5,0xd0,0xae,0xb5,
-0xa5,0xa1,0xdd,0x4b,0xb3,0xa1,0x03,0xda,0xb3,0xc3,0x53,0x93,0xc3,0x47,0xb4,0x77,
-0x8f,0x4c,0x5e,0x1b,0x3a,0x74,0x6d,0x66,0xe8,0xd0,0xcc,0xf4,0x50,0xd7,0x34,0x9c,
-0xaf,0x0f,0x1d,0xbe,0x0e,0x65,0x72,0xe0,0xf0,0xe4,0x70,0xdf,0xc1,0xe1,0x4f,0xcf,
-0x76,0x7e,0xfa,0xda,0x2b,0xcd,0xaf,0xb5,0xf9,0x2a,0xda,0x1a,0x2a,0x6d,0x0d,0x90,
-0xaf,0x87,0x5c,0x3e,0xe4,0xd9,0x8d,0xff,0x29,0x87,0xdf,0xba,0x49,0x38,0x4d,0x6d,
-0x9c,0x6c,0xed,0x08,0x79,0x5d,0x52,0xe2,0x2c,0x79,0xe6,0x58,0xe3,0x33,0xef,0xfd,
-0x65,0xe7,0x7b,0xa1,0xbf,0x1f,0x0a,0x4d,0x0c,0x1e,0x9b,0x98,0xfe,0xfc,0xf8,0xf4,
-0xf4,0xe7,0xdd,0xd3,0xe3,0x03,0xc7,0xc6,0x07,0x7a,0xba,0x06,0xde,0x79,0xbb,0xe3,
-0x9d,0xc3,0x87,0x1b,0x0f,0x17,0x15,0x15,0x16,0xf1,0x6f,0x38,0xe8,0x1a,0xbf,0x50,
-0xd8,0xfc,0xe7,0xcf,0xa8,0xcf,0x6f,0x8a,0x05,0x25,0xe3,0xe0,0x7b,0x6e,0x38,0x96,
-0x43,0x7b,0x86,0x5d,0x25,0xbe,0x04,0x8d,0x5d,0x75,0xdf,0xd0,0xa6,0xe6,0x54,0x57,
-0x97,0x55,0x9f,0x3a,0xe5,0x39,0xf5,0xf1,0xfb,0xfb,0x3e,0xfe,0xe2,0xe2,0xb3,0x5f,
-0xcc,0x7d,0xf1,0xdc,0xdc,0xe2,0xf8,0xf3,0x8b,0xf3,0x5f,0x9e,0x9a,0x9f,0x1a,0xec,
-0x9e,0xba,0x78,0xfe,0xd0,0xc5,0xdf,0xfe,0xa6,0xfd,0xb7,0x6d,0xad,0xdb,0xda,0xf2,
-0xed,0x79,0xf9,0x5c,0xbf,0x68,0x5e,0x82,0xee,0x61,0x34,0xf6,0xd4,0x24,0xed,0x1a,
-0xfc,0x1f,0x23,0x3d,0x0f,0x49,0xbe,0x3d,0x48,0xf7,0xff,0x36,0xd3,0xcd,0x09,0x99,
-0x4d,0x35,0x30,0x87,0xb7,0x45,0xe6,0x91,0x2c,0x16,0xe3,0x3c,0xb7,0xe2,0xbd,0x91,
-0x9f,0x90,0x51,0xa6,0x8a,0xd5,0xa8,0xbc,0x04,0xde,0x5b,0x61,0x3c,0xd7,0x17,0x45,
-0xa4,0xc5,0xd2,0xaf,0xb1,0xf0,0x6d,0x8c,0x6b,0xd2,0x27,0xdf,0x6b,0xc8,0xf7,0x6b,
-0xf3,0xbd,0xd7,0xb2,0x3d,0x56,0x34,0xb6,0xa0,0xbf,0x85,0x1c,0xbf,0xc4,0xa7,0xcc,
-0xc4,0xff,0xc1,0x23,0x37,0x4f,0xc9,0x0d,0x06,0xd5,0xe0,0x5b,0xbf,0xcf,0x7d,0xab,
-0xf7,0x53,0x7b,0xef,0x48,0x28,0x7f,0x64,0xec,0x6a,0xc1,0xd8,0xf8,0x48,0xe1,0x78,
-0xaa,0x38,0xc6,0xc7,0x46,0x1c,0x63,0xa3,0xc3,0x8e,0xd1,0xcb,0x7d,0x8e,0xcb,0x1f,
-0xbc,0x97,0xff,0xc1,0xd1,0x23,0xb9,0x47,0x0b,0xf2,0x95,0x02,0xca,0x3b,0xa1,0x3f,
-0x95,0x8a,0x51,0xee,0xd7,0x49,0x7d,0x18,0x7a,0x66,0xba,0xca,0x75,0x96,0xe7,0xa4,
-0xf0,0xff,0x71,0x42,0x8e,0x19,0x30,0x1d,0x62,0x0f,0x28,0x80,0xd5,0x98,0xbf,0xd6,
-0xf1,0xdd,0x9e,0x98,0x17,0x58,0xaa,0xca,0x6d,0x55,0xaf,0xbe,0xe4,0x7c,0xb5,0xe7,
-0x6c,0x75,0xcf,0x64,0x68,0xeb,0xe4,0x8d,0x2f,0xb6,0xdf,0x98,0x1f,0xab,0x9f,0x9f,
-0x1f,0xd7,0xca,0x44,0xa3,0x5e,0xe6,0xc6,0x1b,0xe7,0x66,0xc7,0x1a,0x67,0xa7,0x46,
-0x1b,0xa7,0x06,0xfb,0xb7,0x0f,0xbe,0xfb,0x1f,0x55,0xef,0x36,0xd6,0xe7,0x37,0xf2,
-0xef,0xec,0xe8,0xb7,0x68,0xba,0x0f,0x91,0x97,0xf0,0xa3,0xe9,0xff,0x53,0xa1,0xf9,
-0x1c,0x9c,0xc3,0x74,0x9e,0x42,0xd9,0xbe,0x35,0x7f,0xfb,0xef,0xfe,0xad,0xfa,0x77,
-0x83,0x7f,0x6f,0x1a,0xbc,0xf1,0x85,0xf7,0xc6,0xca,0xa4,0x6f,0x25,0x3c,0xd5,0x12,
-0x5e,0xbb,0xee,0x5f,0x5b,0xbd,0x1e,0x58,0x5d,0x9e,0x0e,0x2e,0x2f,0x4d,0xb7,0x2e,
-0x41,0x59,0xbe,0xde,0xba,0xbc,0x36,0x1d,0x5c,0x0b,0x5f,0x0f,0x84,0xc3,0xd3,0xc1,
-0xf0,0xea,0x74,0xeb,0xea,0xf2,0x4c,0xdb,0xf2,0xf2,0x4c,0xfb,0xf2,0xca,0x4c,0xfb,
-0xca,0xea,0x4c,0xfb,0x6a,0x64,0xa6,0x35,0x12,0x9d,0x0e,0x46,0xa3,0xd3,0x6d,0xd1,
-0xf0,0x6c,0x47,0x78,0x6d,0xb6,0x63,0x0d,0x0a,0x5c,0x47,0x67,0xda,0xa3,0xb1,0xd9,
-0xb6,0xd8,0xfa,0x4c,0xdb,0x3a,0x94,0xd8,0x6c,0x47,0x2c,0x7c,0x63,0x57,0x38,0x3c,
-0xd7,0x99,0x2c,0xbb,0xc3,0xd1,0x1b,0xbb,0xa2,0xb1,0x1b,0xbb,0x62,0xb1,0xb9,0xce,
-0x58,0x64,0x6e,0x4f,0x24,0x32,0xbf,0x3b,0x12,0x9b,0xef,0x8c,0xc5,0xe7,0x3a,0xe3,
-0xd1,0xf9,0x3d,0xd1,0xc8,0xfc,0x5e,0xed,0xf7,0xde,0x58,0x74,0x7e,0x6f,0xd4,0x38,
-0x2f,0xec,0x8b,0xe9,0x65,0x7e,0x5f,0x2c,0xbe,0xb0,0x2f,0x0e,0xd7,0xf1,0xc5,0x7d,
-0xf1,0xf8,0xc2,0x7e,0xad,0x1c,0x88,0xdf,0x5c,0xd8,0x7f,0xf3,0xeb,0xf9,0xbd,0x5f,
-0xdf,0x5a,0xd8,0x7b,0x6b,0x7d,0xe1,0xc0,0xfa,0xcd,0xc5,0x03,0x37,0xe3,0x8b,0x07,
-0xe3,0x37,0x17,0x0f,0xde,0x8c,0x2e,0x1c,0x8c,0x2e,0x4f,0xef,0x5f,0x9e,0x18,0xde,
-0x3d,0xf1,0xc6,0x1b,0xcd,0x6f,0xd4,0xd6,0x16,0xd7,0x5a,0xf9,0xd8,0x56,0x47,0xc2,
-0xe6,0xa6,0x78,0x8d,0xba,0xa5,0xaf,0xb7,0x68,0x85,0xef,0x45,0xe7,0x87,0x26,0xc8,
-0xbc,0x40,0xa0,0x32,0xf0,0xc7,0x37,0x3d,0x7f,0xbc,0x76,0xb1,0xfd,0xda,0xfa,0xc4,
-0xee,0xf5,0x6f,0xe6,0x0f,0x7e,0x73,0x7b,0xe9,0xe8,0xed,0xbb,0xcb,0xcf,0xdc,0xbd,
-0xb3,0xfa,0xec,0x9d,0xdb,0x6b,0xc7,0x6f,0xdf,0x5d,0x3b,0x76,0x17,0xca,0x9d,0xb5,
-0xe3,0x77,0xee,0xae,0x1d,0xbf,0x0b,0xf7,0xee,0xac,0x75,0xdf,0xb9,0x1b,0x3e,0x7e,
-0xf7,0x6e,0xf8,0x44,0xa2,0x44,0xe0,0x7c,0x32,0x79,0x3e,0x71,0xf7,0xdb,0xc8,0x89,
-0x6f,0xbf,0x0d,0x77,0x7f,0xfb,0x5d,0xa4,0xfb,0xbb,0x7b,0xe1,0xee,0x7b,0x50,0x36,
-0xc2,0xc7,0x37,0xee,0xaf,0x1e,0xbd,0x7f,0x7f,0xf5,0xc8,0xfd,0x8d,0x70,0xf7,0xc6,
-0x77,0xd1,0x93,0xdf,0xdd,0x8b,0x9c,0xbc,0x07,0xbf,0x1f,0x2d,0xed,0x7b,0xf4,0x68,
-0xf9,0xc0,0xa3,0x07,0x6b,0xcf,0x3c,0xd8,0x88,0x9c,0xd4,0x9e,0x9d,0xfa,0x6e,0x23,
-0xfa,0xfc,0xc6,0x46,0xf4,0xe4,0xc6,0xfd,0x70,0xf7,0xfd,0xfb,0x91,0xee,0xfb,0x3f,
-0x44,0x4e,0xfc,0xf0,0x7d,0xf4,0xe4,0xf7,0x3f,0x44,0x9f,0xd3,0xce,0xcf,0x7d,0xbf,
-0x11,0xff,0xd9,0xc6,0x46,0xec,0xf9,0x8d,0x7b,0x91,0x53,0xf7,0x6e,0x2f,0x3c,0x7b,
-0x7b,0x65,0x64,0xff,0xca,0x99,0xb7,0x3d,0x67,0x3a,0x5b,0x4a,0x3b,0x2b,0x9d,0x6a,
-0x25,0xcc,0x0b,0xc4,0x72,0xab,0x38,0x0a,0xe6,0x19,0xd5,0x57,0xe3,0xff,0xe2,0x11,
-0x9b,0xe3,0x70,0x14,0x3a,0x4e,0x9d,0x6a,0x3e,0x35,0xf4,0xd9,0xe1,0xa1,0xf5,0xc5,
-0xe7,0xd7,0xef,0xc5,0x7e,0x71,0xef,0x87,0x9b,0x2f,0xfc,0xf0,0x60,0xfd,0x85,0x07,
-0x0f,0x6e,0xbd,0xf8,0xe0,0xe1,0xad,0x17,0x1f,0x3e,0x5c,0x7f,0xf1,0xe1,0xfd,0xf5,
-0x17,0xee,0x6f,0xc4,0x5e,0xd8,0xb8,0xb5,0xf8,0xfc,0xad,0xe1,0xcf,0xba,0x86,0x8f,
-0x1d,0x69,0x38,0x56,0xe2,0xb0,0x97,0xc8,0xd6,0xec,0x2d,0xfd,0x7b,0x8a,0xe3,0x92,
-0x9c,0xbf,0x81,0x1b,0xa4,0x1d,0x8a,0xe1,0xc2,0xb7,0xb0,0x92,0xbd,0x50,0x38,0x6e,
-0xc3,0x86,0x51,0x0c,0x27,0x7d,0x96,0x97,0x3b,0xcb,0x4f,0xbf,0x1e,0x38,0x3d,0x16,
-0xea,0x1e,0xbb,0xb3,0xf2,0xd2,0x9d,0x87,0xb7,0x7e,0xf9,0xf0,0xc7,0x6f,0x5e,0xfe,
-0xf1,0xd1,0x37,0xaf,0x3c,0x7a,0xf4,0x8f,0x44,0xf9,0xf1,0x1f,0x2f,0xff,0xf8,0xcf,
-0xff,0x79,0xf9,0x9f,0xdf,0xc7,0x7f,0xf9,0x7d,0x7c,0xee,0x17,0xf1,0xb3,0x1f,0x1e,
-0x3c,0xeb,0x6f,0xd9,0xe6,0x07,0x3f,0xc0,0xf0,0xff,0x73,0x53,0xdf,0x92,0xea,0x6b,
-0x6d,0x49,0x1b,0xc5,0xe3,0x11,0x5c,0x23,0xa2,0xff,0x97,0x90,0xe6,0xff,0x64,0x18,
-0xce,0xf1,0x89,0xf2,0x4b,0x16,0x4f,0x72,0xac,0x97,0xda,0x68,0x55,0x82,0x37,0x92,
-0x58,0x98,0xf2,0x50,0x88,0xef,0x54,0x11,0x9f,0x28,0xcf,0xb9,0x0e,0xd2,0xf7,0xe8,
-0x4d,0xa1,0x4d,0x8e,0xe9,0x12,0xfa,0xad,0xf0,0x47,0x8a,0xf3,0x69,0x0e,0x01,0xbb,
-0xd8,0xff,0x40,0xa1,0x7b,0x18,0x8c,0x78,0x2e,0x37,0xb1,0x36,0xc2,0xbf,0xcf,0xe2,
-0x7b,0xaa,0x64,0xfe,0xa5,0x95,0x5f,0x20,0xf3,0x9b,0xf0,0x77,0x65,0xa5,0x5a,0x79,
-0xfa,0x35,0xdb,0xe9,0xcb,0x7d,0xf6,0xcb,0x63,0x23,0xf9,0x63,0x13,0xa3,0xf9,0x13,
-0x50,0xc6,0x47,0x0b,0xc6,0x27,0x47,0x0b,0x27,0x27,0x46,0x0b,0x27,0x12,0xc5,0x91,
-0x2c,0x45,0x7a,0x99,0x1c,0x75,0x4e,0x8e,0x0e,0x15,0x8d,0xfe,0xf5,0xcf,0xf9,0x7f,
-0xad,0xab,0x53,0xeb,0xe8,0xfa,0x1c,0xed,0x8f,0xca,0x49,0xca,0x4b,0xaa,0x2f,0xec,
-0xff,0xc1,0x0a,0x73,0x8d,0x7f,0x0b,0x2e,0xb9,0xcf,0x7d,0x27,0xba,0xef,0x0b,0x72,
-0x8c,0xb0,0xf6,0x08,0xf1,0x08,0x9c,0xe1,0xb7,0xbe,0xaf,0xd7,0xa9,0x96,0xed,0xd9,
-0x59,0xb0,0xe7,0xcc,0x9f,0xab,0xce,0x5c,0x1b,0xd9,0x7e,0x6d,0x6e,0xbc,0x7e,0x6e,
-0x61,0xa2,0x7e,0x61,0x71,0xbc,0x7e,0xf1,0xab,0x89,0xfa,0xaf,0x96,0xc6,0xeb,0x97,
-0x96,0x26,0xeb,0x97,0xe0,0x7a,0x71,0xa2,0x61,0x71,0x61,0xb2,0x71,0x61,0x61,0x72,
-0xc7,0xc2,0xdc,0xd4,0x8e,0xb9,0xf9,0xc9,0xa6,0xf9,0xa1,0x4b,0xf5,0x43,0x2f,0xff,
-0x4b,0xe9,0xcb,0xe5,0xa5,0x39,0xe5,0x28,0x37,0x41,0xae,0xf8,0xdd,0xb7,0x3d,0xe9,
-0x63,0x93,0x79,0x49,0x65,0x89,0x39,0x76,0xfd,0xfb,0xa4,0x62,0x5b,0xf9,0x73,0xdd,
-0x25,0xcf,0xf5,0xf7,0x34,0xf6,0x2f,0x4c,0xb5,0x2c,0x2c,0x5d,0xf7,0x2f,0xad,0x4c,
-0xfb,0x57,0x56,0xa6,0x5b,0x56,0xc2,0xd7,0xfd,0xe1,0xc8,0x75,0x5f,0x24,0x7a,0xbd,
-0x25,0x1a,0x9e,0xf6,0x6b,0xb8,0x1d,0x5c,0x5d,0x99,0x09,0xae,0x2c,0xcd,0xb4,0x2e,
-0xad,0xcc,0xb4,0x69,0xb8,0x1d,0x5c,0x8d,0x4c,0x07,0x34,0xdc,0xf6,0x47,0x75,0x5c,
-0x9f,0x69,0x5b,0x5d,0x9d,0x6d,0x5f,0x5d,0x99,0x6d,0x5f,0x59,0x9b,0x6d,0x5f,0x8b,
-0xcc,0xb4,0x45,0xe2,0x33,0xc1,0x78,0x6c,0xa6,0x35,0x16,0x9e,0x6d,0xd7,0x31,0x3d,
-0x7c,0x63,0x67,0x38,0x32,0xdb,0x11,0x89,0xce,0xb6,0x47,0xe3,0x37,0xda,0xe3,0xeb,
-0x33,0xad,0xeb,0xb7,0x66,0x82,0xb7,0xe2,0xb3,0x1d,0xf1,0xf0,0x5c,0x02,0xd3,0x23,
-0x73,0x9d,0x11,0x28,0xb1,0x1b,0x9d,0x1a,0x9e,0xef,0x8a,0x45,0xe7,0x76,0x47,0x01,
-0xcf,0xe1,0x1c,0x9b,0xdb,0xad,0xe1,0xf5,0x9e,0x18,0xe0,0x79,0x74,0x21,0x81,0xe5,
-0xb1,0x85,0x3d,0x31,0xfd,0x7a,0x01,0xae,0xf7,0xea,0x58,0x9e,0xc0,0xf0,0xfd,0x3a,
-0x86,0x43,0x89,0x2f,0x6a,0xbf,0xb5,0xb2,0xbe,0xb0,0x6f,0xfd,0xeb,0x85,0xbd,0x5f,
-0x43,0x41,0x4c,0xbf,0xf9,0xd5,0xc1,0x64,0xe9,0xba,0xb9,0xfe,0x55,0xd7,0x7a,0x7c,
-0xb1,0x2b,0x3e,0x72,0x79,0xd7,0xc8,0x89,0xee,0xda,0x13,0x0e,0x47,0xae,0x23,0xa1,
-0x4a,0x9b,0x1f,0x88,0xe7,0xa8,0x13,0xc8,0x73,0x90,0x03,0xff,0x66,0xdb,0x78,0x47,
-0x9b,0x31,0xc5,0xc5,0xff,0xc7,0xda,0x99,0x3f,0xb5,0x71,0xa6,0x79,0x1c,0x04,0xe2,
-0x34,0x14,0xc1,0x47,0x7c,0x00,0x06,0x3b,0x36,0x36,0xe0,0x03,0x1b,0x84,0xb9,0x2c,
-0x04,0x58,0x98,0xcb,0x57,0xc6,0xc9,0x54,0x76,0x7e,0x98,0x99,0xaa,0xad,0x9a,0x1c,
-0xb3,0xc9,0x56,0x66,0x92,0xdd,0xd9,0x6c,0x12,0x67,0x37,0x5e,0x4f,0xa6,0xbc,0xc9,
-0x66,0x72,0x39,0x33,0x49,0x1c,0xc0,0x46,0xe2,0x96,0x10,0x92,0x5a,0xea,0xd6,0xc1,
-0x8d,0x6e,0x81,0xb8,0x9c,0x7f,0x66,0xdf,0xe7,0x7d,0xfb,0x6d,0xbd,0xdd,0x6a,0xb0,
-0x53,0x35,0x54,0x3d,0xf5,0xb6,0x84,0x10,0xad,0x3e,0xde,0xcf,0xfb,0xfd,0x3e,0xcf,
-0xfb,0x2a,0xab,0xa0,0xb1,0xe1,0x60,0xe3,0xbd,0xff,0x3a,0x77,0xcf,0x3d,0xd1,0xe2,
-0x5e,0x71,0x34,0xaf,0xc4,0x66,0x1a,0x62,0xb1,0x19,0x5d,0x2c,0xe4,0x68,0x0e,0x05,
-0x9d,0x97,0x83,0x01,0xee,0x72,0x60,0xc5,0x6d,0x40,0x0c,0x37,0x2c,0x07,0xb8,0xb6,
-0xc0,0x8a,0x4b,0x8f,0x79,0x8e,0x99,0x8e,0x38,0xbe,0xec,0x06,0x9e,0x77,0xac,0xe0,
-0xe0,0xc5,0x10,0x39,0x0e,0xdb,0x41,0xbe,0x13,0x71,0xbc,0x3d,0x14,0x74,0x77,0x04,
-0xc3,0x7c,0x47,0x98,0xf0,0xbc,0x23,0x1c,0x75,0xb5,0x45,0x23,0xee,0xf6,0x08,0x70,
-0x3c,0x28,0x18,0x83,0x51,0xde,0x10,0xdd,0x70,0x34,0x6e,0x6c,0xd9,0x75,0x5b,0x09,
-0xae,0x35,0x11,0xe1,0x3b,0x23,0x61,0x4f,0x57,0x38,0x24,0x74,0x85,0x80,0xe5,0x71,
-0x77,0x47,0x3c,0xee,0x36,0xc4,0x81,0xe7,0x11,0xa1,0x13,0xb1,0xfc,0x4a,0x34,0xe2,
-0x01,0x96,0x77,0x85,0x23,0xde,0xee,0x48,0xd4,0x63,0x8c,0xae,0xf1,0xed,0x6b,0x1b,
-0x5c,0xeb,0xc6,0x86,0xab,0x65,0x23,0xce,0xe9,0xe3,0xa6,0x07,0x97,0x4c,0x7d,0xc6,
-0xd2,0xbe,0xe7,0x0a,0xb3,0x9e,0xa3,0xf5,0xf9,0xca,0x7e,0x13,0xf7,0xff,0x2a,0xf5,
-0xd3,0xf4,0x5e,0x87,0x7b,0x0e,0x3d,0x91,0x59,0x79,0x72,0x7f,0xe5,0x27,0x77,0x1a,
-0x3e,0x59,0x71,0x75,0xaf,0x10,0x7e,0x93,0xc0,0x0c,0x57,0x89,0x35,0x7f,0xef,0x5a,
-0xc2,0xd7,0x97,0x48,0xf8,0x7b,0x12,0x4b,0xce,0xae,0xa5,0x3b,0xef,0xd7,0xdd,0x29,
-0x3f,0xba,0xb7,0x1c,0x9d,0x98,0x0c,0xa9,0x7f,0xd6,0x88,0x63,0x08,0xc6,0x97,0xa4,
-0xfd,0x47,0x0a,0x93,0x54,0xb4,0x0c,0xcb,0x70,0x59,0x2e,0x4c,0xd1,0xa7,0xb2,0x63,
-0x04,0x19,0x3f,0xd2,0xe5,0xef,0x43,0x5f,0x03,0x2d,0xba,0x89,0x73,0x75,0xba,0x12,
-0xdd,0x83,0xcf,0xdb,0x1e,0xc4,0x7d,0xd7,0xe3,0x9b,0x8b,0x37,0x37,0x93,0x41,0x59,
-0x2e,0x6e,0x2f,0xdd,0xda,0xdc,0x5a,0xba,0xb5,0x95,0x7c,0xee,0xe6,0x66,0x80,0xeb,
-0x09,0xfc,0xf2,0x17,0xd5,0xbf,0xdc,0xff,0x5c,0xce,0xfe,0xfc,0xac,0xf4,0x7c,0xf0,
-0x13,0x81,0xdd,0x05,0xd9,0x69,0x05,0xd0,0x27,0xd1,0xfc,0x5a,0x0a,0xc3,0x35,0x0a,
-0x1d,0x47,0xf7,0x3b,0x5d,0x76,0xf2,0x52,0x8e,0x01,0x7b,0x9c,0x52,0xfc,0x88,0x1d,
-0xf4,0xfd,0xae,0xc1,0x78,0xe9,0x12,0x5f,0xd9,0x96,0x3d,0x8e,0x69,0x72,0x06,0xb0,
-0xfb,0xa9,0xdc,0xe7,0xa7,0xd1,0x34,0x85,0x27,0xac,0x8e,0x64,0xc7,0x5c,0x0a,0xc6,
-0x48,0xf3,0x55,0xd3,0x52,0x7d,0x1c,0xd6,0x8f,0x51,0x65,0x24,0xfb,0x39,0x55,0xfa,
-0x16,0xba,0x41,0xdf,0x47,0xa9,0xdd,0xd9,0xba,0x6d,0x99,0x37,0xac,0x9c,0xa7,0xa5,
-0xb8,0x2e,0xd9,0x9a,0x47,0xba,0xce,0x85,0x54,0x7b,0x9d,0xa1,0xce,0xf8,0x43,0x87,
-0xd2,0x0e,0xbd,0xf1,0x6a,0xc6,0x1b,0x03,0xdf,0x65,0x0d,0x0c,0x0f,0x66,0x0f,0xd3,
-0x30,0x0d,0xe5,0x98,0x70,0x50,0x96,0x0f,0xe5,0x4a,0x2c,0x37,0x0f,0xe6,0x9b,0xcd,
-0x43,0x28,0x70,0xbb,0x07,0xf1,0x7e,0x8f,0xe9,0xde,0x7f,0xe7,0xde,0xab,0xa9,0xd1,
-0xd4,0x68,0xb5,0x69,0x5a,0x35,0x5e,0xb3,0x21,0xdd,0x2b,0x2a,0xe3,0x29,0xd9,0x7d,
-0x9a,0xae,0x32,0x76,0x61,0xae,0x65,0xe5,0xef,0x95,0x63,0x4e,0x25,0xd7,0x69,0xae,
-0x1c,0x6a,0xbf,0xf0,0x1c,0xa0,0x3d,0x69,0xc5,0x87,0x8b,0xd3,0x0f,0x77,0x1b,0x72,
-0xba,0xbf,0xbe,0x7f,0xe0,0x6b,0xeb,0xa3,0x12,0xeb,0xb4,0xa9,0x74,0x1a,0x58,0x8e,
-0xc3,0x4c,0x5a,0xcc,0x74,0xc4,0x73,0x87,0xb9,0xcc,0x01,0x61,0x37,0x1d,0xb5,0xdb,
-0xcc,0xe5,0x36,0xab,0xf9,0xb8,0xd5,0x3a,0x72,0xcc,0x0a,0xad,0xe9,0xc7,0x0a,0xd3,
-0x9b,0xaf,0xee,0x7b,0xf3,0xc8,0xc1,0xcc,0x23,0x3b,0x9d,0x47,0x5a,0x87,0x47,0xc7,
-0xde,0xb4,0x3e,0x9d,0xe6,0x0b,0xe9,0xbe,0x16,0x17,0x65,0x14,0xbf,0x74,0xbd,0xf8,
-0xa5,0x47,0xdf,0x1e,0x7f,0x64,0x1f,0x3b,0x85,0x74,0xf7,0x69,0x87,0x63,0x9c,0x46,
-0x15,0xd2,0xda,0x55,0x4e,0xd7,0xd8,0x29,0xa4,0xc3,0x4f,0xb9,0x85,0xf1,0x4a,0x86,
-0xe9,0x35,0x4e,0xc7,0xe4,0x19,0x07,0x61,0x7a,0x0d,0x62,0x7a,0x35,0xcf,0x4f,0x90,
-0x70,0x4f,0x9c,0x71,0x83,0x3e,0xe7,0x26,0xcf,0xe1,0xe0,0x27,0xcf,0xf2,0xfc,0xe4,
-0x19,0xde,0x35,0x85,0xf4,0xf9,0xd4,0x79,0x14,0xb5,0x88,0xe9,0xe7,0xdc,0xfc,0xd4,
-0x79,0x5e,0x98,0x3a,0x27,0xf8,0xa6,0xce,0xfa,0xe6,0x26,0x6a,0xe6,0x7c,0x93,0x67,
-0x7d,0xfc,0x54,0x2d,0xe2,0x78,0x2d,0x0f,0xfa,0x9c,0xb7,0x5c,0xe4,0x29,0xc3,0x05,
-0x4b,0x9d,0x20,0x58,0x51,0x6b,0xad,0x63,0xa2,0x5e,0x10,0xa6,0x75,0x02,0xe1,0x78,
-0x9d,0x87,0x70,0x1d,0x69,0x73,0x9b,0x4e,0xe4,0xb9,0x18,0x36,0x60,0x3a,0x62,0xb6,
-0x0d,0x31,0x7d,0x06,0x69,0x74,0xc4,0xef,0x59,0x5b,0xfd,0xec,0x82,0xb5,0x6e,0x61,
-0xce,0xa6,0x9b,0xf3,0xdb,0x1a,0xfd,0xfe,0x19,0x1a,0x4d,0x7e,0xc2,0xf4,0x66,0xdc,
-0x8e,0x0c,0xd4,0x8d,0xbc,0xfc,0x52,0xe9,0xcb,0x85,0x85,0x59,0x85,0x4f,0xbd,0xff,
-0x19,0x6d,0xc9,0xf6,0xe7,0xf0,0x18,0xae,0x07,0xb8,0x16,0x70,0xad,0x19,0xf3,0x3e,
-0x59,0xd9,0x19,0x59,0x35,0xd5,0xcf,0xd5,0xbc,0xfb,0x76,0xcd,0xbb,0xdc,0x78,0x0b,
-0xb7,0xe0,0x34,0x2c,0x2c,0x71,0x6d,0x4b,0x01,0x67,0x6b,0x20,0x32,0xd3,0x18,0x09,
-0x3b,0x9a,0xc2,0x01,0xe7,0xe5,0x40,0xd0,0xd9,0x1a,0x0c,0x38,0xf5,0x01,0xd0,0xe2,
-0xc0,0xf3,0x20,0xd7,0x16,0x0c,0xb8,0x0c,0x81,0x65,0x77,0xfb,0x72,0xc0,0xdd,0x1e,
-0x58,0xe6,0x59,0x96,0x27,0x19,0xbe,0xc2,0x13,0x7d,0x1e,0x70,0x77,0x22,0x5d,0xde,
-0x1e,0xa4,0x9a,0x1c,0x07,0x62,0x3a,0xf0,0x3c,0xe2,0x36,0x20,0x96,0x77,0x62,0x96,
-0x83,0x0e,0x07,0x3d,0x9e,0x70,0xb6,0x24,0xd6,0x9c,0xad,0x6b,0x51,0xbe,0x3d,0x1a,
-0x16,0x8c,0xe1,0x90,0x07,0x58,0x6e,0x44,0x2c,0x6f,0x47,0x2c,0x6f,0x8b,0xc7,0xf9,
-0xf6,0x78,0x4c,0xe8,0x8c,0x41,0x60,0x6d,0xee,0xb9,0x1a,0x89,0x78,0xaf,0x46,0x62,
-0x82,0x31,0x96,0x70,0xb7,0x25,0x36,0x9d,0x4d,0x9b,0x9b,0xce,0xe6,0xcd,0x75,0xb7,
-0x7e,0x7d,0x8d,0xef,0x58,0x8b,0xf3,0x57,0xe2,0x36,0xb3,0xde,0x76,0xfb,0xc5,0x17,
-0x6e,0xa3,0x81,0x6d,0x21,0x3b,0x3c,0x92,0xb1,0x50,0x65,0x8d,0x26,0xda,0x37,0x6a,
-0xb5,0x1a,0xed,0xc5,0x0b,0x07,0x2f,0x7e,0xf5,0xbf,0x2d,0x5f,0x85,0x85,0x9e,0x30,
-0xe1,0x78,0x7f,0x5c,0x6a,0xe7,0xfa,0x19,0xa6,0xf7,0xad,0xae,0xcd,0xf6,0xad,0x01,
-0xc3,0xd7,0xfd,0xbd,0xeb,0x09,0x7f,0x6f,0x22,0x31,0xd7,0x97,0x58,0x9d,0xeb,0x5f,
-0x8d,0x78,0xfa,0x22,0x5f,0x7c,0xd2,0xfc,0xc5,0xd9,0x9a,0xe7,0xcf,0xa2,0x7f,0xa2,
-0x65,0xef,0x79,0x56,0x8f,0x4b,0x3c,0x52,0x7c,0x0f,0x8e,0xb2,0x2f,0xa1,0xaf,0x63,
-0xc7,0xd4,0x30,0xd6,0x56,0x72,0x51,0xd5,0x27,0x56,0xf3,0x03,0x98,0xfe,0x6b,0x4f,
-0x7e,0xce,0x9e,0x9b,0xfd,0x95,0x37,0xed,0x13,0x5d,0x76,0xac,0xc5,0x95,0x0c,0x5f,
-0xba,0x95,0xe4,0xf8,0xe2,0xcd,0xad,0xad,0x85,0x5b,0x5b,0x5b,0x8b,0x37,0xb6,0xb6,
-0x17,0x6e,0x6c,0x6f,0x2d,0x5c,0xdf,0xda,0x9e,0xbf,0xbe,0xfd,0x64,0xfe,0xda,0x93,
-0x30,0xd7,0x13,0x7e,0xfb,0xf5,0x73,0x6f,0x57,0x94,0xe4,0x57,0xc0,0x75,0x48,0xe7,
-0xfe,0x53,0x8e,0xe3,0xda,0x54,0x65,0x3e,0x40,0xe1,0x4f,0xb0,0xe7,0x8b,0xdd,0xff,
-0x9d,0xf4,0x9e,0x2a,0x9b,0xd9,0xda,0x1d,0xfa,0x9a,0x1d,0x6a,0xbe,0x54,0x35,0x2c,
-0xcb,0x66,0xc5,0x7d,0x27,0x63,0xf5,0x3f,0xf0,0x47,0x39,0xe6,0xa4,0x1b,0xd2,0x63,
-0xc5,0xff,0xdd,0x49,0xbb,0x4b,0x9f,0x4f,0x5c,0x1f,0x1b,0xb7,0x2a,0xe7,0x5e,0x75,
-0xbc,0xb8,0x0b,0xe7,0xd9,0x63,0x20,0xe5,0x4f,0x19,0xdd,0xce,0xf2,0x40,0x9a,0x73,
-0xa5,0xdd,0x99,0xf5,0x74,0x3d,0x10,0xd9,0x73,0x19,0x64,0xad,0x6f,0xea,0x35,0x15,
-0x17,0xa5,0x15,0xff,0xfe,0x35,0xcd,0xef,0x87,0x7e,0xc8,0x1a,0x32,0x0d,0x66,0x61,
-0x4d,0x6e,0x1a,0x22,0xda,0xdc,0x34,0x98,0x23,0x46,0xae,0x69,0x78,0x28,0x17,0xf1,
-0x3d,0x4f,0xce,0x74,0xc4,0x73,0xac,0xd3,0x87,0xf6,0x98,0x80,0xe9,0x8f,0x07,0xf6,
-0x3c,0xbe,0xfb,0x51,0xde,0xdd,0x9a,0x6a,0x4d,0x0d,0x8c,0xb1,0xd5,0xb4,0x78,0x8a,
-0xe7,0xc1,0x7a,0x63,0x3b,0x1c,0x67,0x56,0x8b,0xcb,0xc6,0x2c,0x1a,0xb9,0x5f,0x26,
-0xf3,0x26,0x54,0xae,0x65,0x35,0xae,0x03,0xcf,0x0d,0xcd,0xd9,0x86,0x6f,0x3f,0xdd,
-0xff,0xad,0xed,0xf1,0x11,0x9b,0x7d,0xb8,0xc4,0x6e,0x1f,0x3e,0x62,0x9f,0x19,0x2e,
-0x45,0x3a,0xbc,0xd4,0x66,0x33,0x95,0xd9,0x08,0xd7,0x8f,0x22,0xae,0x1f,0x9d,0x06,
-0x8e,0xdb,0x4d,0x48,0xab,0x53,0x9e,0x8f,0x54,0x58,0x49,0x1c,0xb3,0x5a,0x46,0x8e,
-0x5b,0x4c,0x0f,0xcb,0x4d,0xaf,0xfd,0xf3,0xbe,0xd7,0xa0,0x7e,0x0e,0x1f,0x7f,0x0d,
-0x73,0xfe,0xb4,0xc9,0x1a,0x16,0x29,0x5f,0x9f,0x4d,0xe6,0x8a,0xb1,0xf3,0xc0,0x0b,
-0xf3,0x35,0x85,0xfd,0x57,0x8b,0xfa,0x07,0xbf,0x3d,0x3e,0x08,0x2c,0x07,0x3d,0xee,
-0x1c,0x3b,0x85,0x75,0x39,0xe8,0x73,0x60,0x3b,0xd1,0xe9,0x55,0x4e,0x6e,0xec,0x34,
-0x07,0x2c,0x77,0x8d,0x57,0xb9,0xb8,0xf1,0x2a,0x0e,0x98,0x0e,0x1c,0xc7,0x5c,0xc7,
-0x1e,0xfb,0x19,0xa7,0x6b,0xe2,0x8c,0xcb,0x3d,0x51,0xe3,0xc6,0x1e,0xfb,0x44,0x8d,
-0xe0,0x9e,0x44,0x5c,0x9f,0x24,0x5c,0x07,0x5d,0xce,0x4d,0x9d,0xe7,0x92,0x3c,0x3f,
-0x2f,0xf1,0xdc,0x33,0x75,0xce,0x03,0x3a,0xdd,0x3b,0x75,0xce,0x0b,0x3c,0x17,0x2c,
-0xb5,0x02,0x69,0x91,0x26,0xa7,0x4c,0xc7,0x2c,0x27,0xda,0x9c,0x6c,0xd7,0x8b,0x3c,
-0x4f,0x86,0xd7,0x5a,0x8f,0xf8,0x5d,0x4f,0x18,0x6e,0xd5,0x21,0x86,0xeb,0x7c,0x10,
-0x58,0xa7,0x8b,0x9e,0x3b,0x30,0x1d,0xc2,0x6f,0x6b,0x10,0x35,0x7a,0xc3,0xdc,0xac,
-0xad,0x61,0xd6,0x6f,0xbb,0x84,0xf9,0x0d,0x1a,0xdd,0x6f,0x47,0x4c,0xb7,0x37,0x63,
-0xa6,0x43,0x98,0x1e,0xd6,0x99,0x6e,0x5c,0x3b,0x72,0x23,0x3f,0x5f,0x9b,0xff,0x2c,
-0xf7,0x3e,0x5c,0x47,0xd2,0x18,0x4b,0x9c,0x2f,0x0e,0xd7,0x01,0xcc,0xfb,0x82,0x96,
-0x5c,0x8b,0xe9,0xe9,0x7b,0xf7,0xe6,0xec,0xed,0xe9,0x2a,0xeb,0x31,0xff,0xa8,0x33,
-0xcf,0x3b,0xf4,0xf3,0x8b,0xae,0xb6,0xc5,0x45,0xce,0xb0,0xb8,0xcc,0xe9,0x97,0x57,
-0xb8,0xcb,0x2b,0x2b,0x4e,0x14,0x9c,0x1e,0x47,0xc8,0xd1,0x12,0x02,0x7d,0x8e,0xf5,
-0xb8,0x1b,0x3c,0x76,0xa4,0xd3,0xdd,0x06,0xb2,0x8d,0x18,0x8e,0xb5,0x39,0x62,0x3d,
-0xf8,0xe9,0xb0,0x1d,0xe0,0x3b,0x02,0xd8,0x67,0x17,0xd9,0x8e,0x35,0xb9,0xab,0x3d,
-0x0c,0xfa,0x3c,0xec,0x36,0x84,0x29,0xd3,0xa3,0x2e,0x43,0x34,0xc2,0x77,0x44,0x42,
-0xc2,0x95,0x10,0x04,0x7d,0x2e,0xea,0x6e,0x8f,0x82,0xf6,0x26,0x2c,0x37,0x86,0x80,
-0xe7,0x11,0xfe,0x4a,0x04,0x74,0xf9,0xaa,0xcb,0xb0,0x1a,0xe3,0xdb,0x63,0x31,0x1e,
-0x58,0x0e,0xda,0xbc,0x2b,0x02,0x3c,0x8f,0xf1,0x57,0x62,0xeb,0xae,0xcb,0xeb,0xdb,
-0x8e,0xc6,0xed,0x27,0x8e,0xc6,0x27,0x1b,0xae,0xcb,0x1b,0xa0,0xd3,0xe3,0x9e,0x2b,
-0xf1,0xa8,0xe7,0x6a,0x34,0xea,0xed,0x8e,0x5a,0x4c,0x06,0x4b,0x4f,0x77,0x79,0x0f,
-0xea,0x58,0x72,0x94,0xe3,0x1f,0x76,0x9e,0x08,0xbb,0xfe,0x0f,0xf6,0x3c,0x32,0x34,
-0x19,0x35,0xd5,0xfb,0x6b,0xbe,0xf8,0x4b,0xf3,0x17,0x11,0x4f,0x6f,0x04,0x33,0xdc,
-0x2f,0xe7,0xb7,0xd4,0xfa,0x7b,0x57,0x81,0xe3,0x09,0x7f,0x37,0xd6,0xe4,0x6b,0xb3,
-0xbd,0x6b,0x6b,0xb3,0xfd,0x62,0x5c,0x5b,0x5b,0x9b,0xbb,0xb6,0x16,0x11,0x7a,0x23,
-0x9f,0x7d,0xdc,0xf8,0x19,0xd4,0xf4,0xa1,0x41,0x97,0x56,0x59,0x4f,0xa3,0xb6,0xf6,
-0x33,0xdb,0xb7,0x62,0xaf,0x80,0xc9,0x75,0xe1,0xb1,0xb2,0x36,0x39,0xd7,0x85,0xf5,
-0xc3,0x94,0x7d,0x50,0x8a,0x36,0x55,0xe6,0x30,0xc5,0x80,0xdc,0xf7,0xed,0x5b,0xa7,
-0x6f,0xcf,0xdb,0x7b,0xe6,0xe5,0x9a,0x3c,0x55,0x9f,0x6f,0x2d,0xdc,0x24,0x1c,0x9f,
-0xbf,0xb6,0x9d,0x8c,0x7e,0x1c,0x4f,0xe6,0xfa,0x9e,0x3c,0x99,0xef,0x7f,0x12,0xb0,
-0x77,0x07,0xde,0xfa,0xdd,0x99,0xb7,0x8e,0x1c,0xc8,0x3d,0x42,0xf3,0x7f,0x6a,0xf5,
-0x36,0x6a,0xe3,0x0e,0xca,0x29,0x99,0xb6,0x51,0xf8,0x28,0xb2,0xf7,0xd1,0xc8,0xb5,
-0xce,0x6e,0x7e,0xef,0x4e,0xff,0x4f,0x96,0x3f,0x55,0xd1,0xca,0x74,0x9f,0xd8,0x9b,
-0xef,0x1f,0x42,0xf2,0xa7,0xbd,0xc7,0x33,0x8c,0xeb,0x71,0xab,0xd4,0x93,0x3b,0xf0,
-0x26,0x65,0x6c,0xb3,0x83,0x8f,0x21,0xe3,0x58,0xda,0xce,0x63,0x17,0xf6,0x7f,0xb1,
-0xe7,0x88,0xb2,0x81,0xce,0xb7,0xa2,0x3a,0x8f,0x5d,0xf3,0x8b,0x5d,0x6b,0x8c,0x9d,
-0xc3,0xc0,0xd6,0x9c,0xe4,0xe5,0xa4,0xe5,0xdd,0xbe,0xa1,0xb9,0x3d,0xf4,0x9d,0x76,
-0xc8,0x3c,0xa8,0x45,0x5a,0x3b,0x9b,0xc4,0x50,0xb6,0x19,0x73,0x7c,0x48,0xe4,0x39,
-0xd5,0xe8,0xc0,0xf2,0x21,0xd1,0x6b,0xc7,0x6c,0x27,0x4c,0x07,0xcf,0x1d,0x6b,0x74,
-0xc4,0xf5,0x47,0x0f,0x0b,0x1e,0xbd,0xf3,0x87,0xdc,0x77,0xca,0xca,0xd2,0xcb,0x52,
-0x78,0xae,0xa2,0xc3,0x53,0x8e,0x89,0x4a,0xb0,0xaf,0x53,0xce,0x21,0x90,0xd5,0x1b,
-0xb2,0xad,0xb2,0x06,0x31,0x23,0x2d,0x65,0xae,0x26,0x1c,0x87,0x8a,0x32,0x6d,0xc5,
-0xdd,0xf7,0xf7,0xdd,0xb5,0x3c,0x2a,0xb1,0x00,0xc3,0xed,0x26,0xc2,0x73,0xe0,0xba,
-0x63,0xb8,0xc4,0xe1,0x30,0x95,0x3a,0x66,0x4c,0x88,0xed,0xe6,0xa3,0x36,0x08,0xf0,
-0xd9,0x6d,0xa6,0x72,0x1b,0xb0,0xdc,0x66,0xae,0xb0,0x61,0x6d,0x2e,0xc5,0x71,0xac,
-0xd3,0x1f,0x7e,0x7b,0xf4,0xe1,0xad,0x1b,0x45,0xb7,0x0a,0x0b,0x32,0x0a,0x59,0x8f,
-0x4f,0x76,0xde,0xc4,0x73,0x85,0xfd,0xb5,0x9c,0xb4,0x02,0x9c,0xdf,0x87,0x5c,0x40,
-0x7e,0x7a,0x51,0xc3,0xc5,0xfc,0x86,0x07,0xff,0x57,0xfe,0xc0,0x3e,0x0a,0xba,0xfc,
-0x94,0x03,0xc2,0x39,0x76,0x1a,0xb3,0x9b,0x1b,0x3b,0xc5,0xc1,0x36,0xb0,0x1c,0xf3,
-0x1c,0x18,0x3e,0x46,0x38,0x0e,0x4c,0xc7,0x31,0x51,0x8d,0xa2,0xc6,0x05,0x4c,0x07,
-0x9e,0xe3,0xbc,0x39,0xe2,0x37,0xe8,0x73,0xcf,0x44,0xb5,0xc7,0x33,0x5e,0xed,0x81,
-0x6d,0xcc,0xf2,0x49,0xc4,0xf2,0xc9,0xf3,0x92,0x3e,0x77,0x59,0x08,0xd3,0x21,0x80,
-0xe9,0x94,0xe5,0xd4,0x6b,0x07,0xa6,0x0b,0x96,0x0b,0x98,0xe7,0x98,0xdf,0xd4,0x6f,
-0x07,0xa6,0x5b,0xeb,0x3c,0xa0,0xcf,0xc1,0x57,0xc7,0xfa,0xdc,0xaa,0x13,0x99,0xae,
-0x93,0x33,0x7d,0x5a,0x64,0xba,0x4d,0xe7,0x23,0x9e,0xbb,0xce,0x47,0x78,0x0e,0xfe,
-0xfa,0x25,0xcc,0x74,0xff,0xcc,0x25,0x3f,0xb0,0x9c,0x30,0xbd,0x91,0x68,0x73,0xe0,
-0xf9,0x0c,0xe2,0xb9,0x1d,0xf1,0x1c,0xb6,0x6d,0xcd,0xbe,0xbf,0x7d,0x5e,0xfb,0xb7,
-0x4b,0xba,0xfd,0x97,0x70,0x0d,0xbc,0xca,0xbd,0xcb,0xfe,0xe0,0xbe,0x5e,0x93,0x5c,
-0x63,0x0f,0xae,0x07,0xba,0xbe,0x1a,0x68,0x22,0x74,0x81,0x64,0x1e,0x3b,0x56,0x70,
-0xec,0x8d,0xdf,0x55,0xbe,0x31,0x33,0xd2,0x34,0xb3,0xc8,0x01,0xc7,0x69,0xe8,0x11,
-0xcf,0xdb,0x96,0x81,0xe9,0xd0,0x82,0x56,0x07,0xb6,0x83,0xe7,0x1e,0xe0,0xf4,0x98,
-0xe7,0x4b,0xee,0xf6,0xa5,0x25,0x77,0xc7,0x12,0xe1,0x7a,0xfb,0x0a,0x0e,0x37,0x0d,
-0xa2,0xd1,0x41,0x8f,0x43,0x80,0x3e,0x07,0x96,0x53,0x8e,0x43,0x4b,0x73,0xe7,0x11,
-0x97,0x21,0x02,0xec,0x06,0x6d,0x1e,0x12,0x3a,0x43,0x44,0xab,0xb7,0x47,0x40,0xa3,
-0x87,0x04,0x63,0x28,0xe8,0xe9,0x0a,0x82,0xc7,0x0e,0x2c,0xc7,0x81,0xb6,0x21,0x5f,
-0x0e,0xda,0x1c,0x22,0x2a,0x74,0x46,0xc1,0x87,0x07,0x9e,0xc7,0xf9,0x8e,0xf8,0xba,
-0xab,0x75,0x7d,0xcb,0xd9,0xb8,0xb5,0xe5,0x68,0xdc,0xda,0xe4,0x5a,0x36,0x41,0xa7,
-0xc7,0x3d,0x9d,0xf1,0x98,0xf7,0x6a,0x2c,0xea,0xeb,0x46,0x3c,0xef,0x89,0x86,0xbd,
-0x3d,0xe1,0x1f,0xbe,0x6e,0xfd,0xe1,0x6c,0xcd,0x81,0xb3,0x99,0x99,0xe9,0x52,0x8d,
-0x26,0x3e,0x56,0x4c,0xdd,0x07,0xeb,0xef,0xc2,0xcf,0xa1,0xe7,0x0b,0x0e,0xdd,0xf9,
-0x53,0xfd,0x9d,0x90,0xd0,0x13,0x92,0x3c,0x76,0x3f,0xf5,0xd9,0x81,0xe1,0x7d,0xd8,
-0x57,0x5f,0xf3,0x75,0xaf,0xad,0xfb,0xbb,0xd7,0x21,0x40,0x93,0x83,0x46,0x07,0x7e,
-0x13,0x8e,0xf7,0xaf,0x25,0x66,0xfb,0xc9,0x73,0x88,0xed,0x41,0x77,0x77,0xf0,0x8f,
-0xff,0x72,0xfe,0x8f,0x07,0xf6,0xe7,0x1f,0x60,0xe7,0x70,0x4a,0x3e,0xa3,0x46,0xb1,
-0x8e,0xae,0x26,0x39,0x1f,0x9b,0x8e,0x97,0x71,0x4e,0x2b,0x33,0xb9,0xc6,0x84,0x92,
-0xe3,0x6c,0x9f,0xa3,0x5a,0x87,0xac,0xc2,0x71,0x08,0xb4,0x03,0x99,0x7a,0x7d,0xb9,
-0xde,0x3b,0xdd,0xed,0x85,0x9c,0x38,0xb0,0x7b,0x63,0xf1,0xd6,0x06,0xcb,0x71,0xd0,
-0xe3,0x24,0x77,0x7e,0x73,0x13,0x58,0x0e,0x3a,0xfc,0xc9,0x5c,0xff,0x93,0x9f,0xe6,
-0xfa,0x7e,0x02,0x86,0xff,0x34,0x8f,0xda,0x79,0x60,0x39,0x7a,0x7e,0xe1,0xfa,0x93,
-0xad,0xf9,0xeb,0x5b,0xfc,0xd8,0x55,0xfe,0xc5,0x6b,0x27,0x5e,0xcc,0xcf,0xd3,0xe6,
-0xcb,0x6a,0x13,0x14,0xeb,0xd9,0xca,0xd8,0xc3,0xac,0x59,0xa1,0xcc,0x23,0xa8,0x79,
-0xb7,0xb2,0xc8,0x48,0x9d,0xd7,0xaf,0x96,0x3f,0x67,0x6e,0x26,0xf9,0x3e,0xb0,0xda,
-0x4b,0xd1,0xbf,0xcb,0xfc,0x76,0xe6,0xd1,0xcf,0xd5,0xe7,0xec,0x7b,0xed,0xa6,0x81,
-0x7f,0xce,0xfb,0xa9,0xb1,0x36,0xe5,0x73,0xec,0xc2,0x79,0xd9,0x98,0x48,0xc1,0x23,
-0x65,0x1d,0x83,0x72,0xac,0x49,0x77,0x82,0xfd,0x3c,0x2c,0xd7,0x64,0x35,0x54,0x62,
-0xce,0x95,0xd6,0x4f,0x50,0xcd,0x87,0x5b,0x95,0xda,0x6e,0x88,0x8b,0xe7,0xd3,0x2e,
-0xfe,0xf5,0x7e,0xe6,0x5f,0xcd,0x83,0x59,0x66,0xf3,0x40,0x96,0x79,0x64,0x20,0x6b,
-0x64,0x64,0x30,0x6b,0x84,0x70,0x3d,0x07,0x31,0x3a,0xc7,0x4c,0xf5,0xb9,0x2c,0x77,
-0x3e,0x44,0xf5,0x39,0xf1,0xd9,0xa1,0x25,0x51,0x80,0xfe,0xae,0xc0,0xfc,0xdd,0x37,
-0x7b,0xbe,0xbb,0xfd,0x8b,0xac,0xdb,0x79,0xb9,0xe9,0x79,0x6a,0xc7,0x12,0x8f,0x85,
-0xd3,0xe4,0xd7,0xcd,0x8e,0xde,0x86,0xe2,0x7a,0x51,0xde,0x6f,0x2c,0x9f,0x65,0xb5,
-0x08,0x8a,0xf9,0xe7,0xaa,0x91,0x99,0xa6,0xfd,0xed,0xaf,0x0a,0x7f,0x3b,0x3a,0x70,
-0x64,0xd4,0x62,0x2a,0xb5,0x58,0x87,0x4b,0xad,0xd3,0xa6,0x92,0x69,0xdb,0x70,0x89,
-0x6d,0x66,0xb8,0x64,0xc6,0x31,0x5c,0xea,0x70,0x9a,0x4a,0x9d,0x4e,0x53,0x89,0x93,
-0x70,0xbd,0x0c,0x73,0x1d,0x74,0x3a,0xe1,0x7b,0x85,0xcd,0x36,0xa2,0xe4,0xfa,0x71,
-0xeb,0x94,0xe9,0xf8,0xd4,0xfd,0x7b,0x25,0xf7,0x6b,0xcf,0xe5,0xd5,0x66,0x69,0xd3,
-0x93,0xe3,0xa8,0x8c,0x64,0x2d,0x3d,0x9d,0x53,0x47,0xcf,0x11,0xcd,0xed,0x97,0x3e,
-0x9f,0x51,0xfa,0xc1,0x1f,0x0e,0x7e,0xe0,0x30,0x9d,0x74,0x70,0xa3,0x95,0x88,0xdd,
-0x95,0x4e,0xc7,0x38,0x30,0xfd,0xb4,0x83,0xe8,0x72,0xd0,0xea,0x49,0x9e,0x93,0xa8,
-0xc6,0x5c,0xa7,0x3c,0x77,0x4f,0x54,0xbb,0x21,0x77,0x0e,0x79,0x73,0x60,0x3b,0xcd,
-0x9d,0x43,0xd0,0xdc,0x39,0x04,0x6c,0x83,0x36,0xe7,0xa6,0xce,0x89,0xfa,0xfc,0x3c,
-0xe3,0xbb,0xd7,0xba,0x81,0xe3,0xa0,0xd1,0x85,0xa9,0xf3,0x02,0xd4,0xc0,0xf1,0x53,
-0x24,0x77,0x4e,0x7c,0xf6,0x0b,0x02,0xc9,0x99,0x5f,0xf0,0xb0,0x7e,0x3b,0x30,0x9d,
-0x06,0xcb,0x73,0xa8,0x83,0xf3,0x4d,0xd7,0xfb,0x48,0x34,0x60,0x96,0x43,0xbe,0x9c,
-0x06,0x66,0x3b,0x65,0xba,0x8d,0xe6,0xcc,0xc1,0x7f,0xbf,0x34,0x3b,0x37,0xd3,0x30,
-0x07,0x9e,0x3b,0xcd,0xa1,0x03,0xcb,0x31,0xd3,0x91,0x46,0x17,0xac,0x4d,0xc2,0x7b,
-0xff,0x76,0xea,0xbd,0xc3,0x87,0x73,0x0f,0xab,0xf6,0x07,0xcc,0x0f,0xd5,0xe7,0x74,
-0x1c,0x0c,0xdb,0x70,0x1e,0x0e,0x16,0xa6,0x1d,0xdc,0x57,0xa8,0xd9,0x57,0x7b,0xee,
-0xb9,0xda,0x3b,0xff,0x59,0x73,0x87,0x9b,0x6c,0xe5,0x16,0xb8,0xb6,0x05,0x08,0x60,
-0x39,0x6d,0x97,0x9c,0xfa,0x25,0xca,0x73,0xa8,0x7f,0x0b,0x3a,0x5b,0x82,0x11,0x7b,
-0x53,0x04,0x74,0x3a,0xa9,0x7b,0x63,0x72,0xe6,0x62,0x0b,0xde,0x3b,0xf8,0xee,0x24,
-0x67,0xde,0x91,0xac,0x81,0x43,0x4c,0x0f,0xb9,0x0d,0xa1,0xb0,0xab,0x2d,0x0c,0x3c,
-0x87,0x5a,0xb8,0x80,0x70,0x25,0x10,0xe4,0xaf,0x04,0x89,0x46,0xef,0x08,0x03,0xcf,
-0xe5,0x5a,0x1d,0xb1,0x5c,0x40,0x2c,0x17,0x75,0xb9,0x14,0x5e,0xe2,0xb9,0x47,0xf9,
-0x8e,0x28,0x68,0xf3,0xb0,0xc7,0x28,0xb1,0x7c,0x83,0x6b,0xd9,0xd8,0x76,0x5c,0xda,
-0x26,0x2c,0x6f,0xde,0x4c,0xb8,0xf4,0x89,0x55,0xa1,0x63,0x35,0xe6,0xe9,0x8a,0x81,
-0x2e,0x07,0x96,0x47,0x7d,0x3d,0xd1,0x88,0xaf,0x27,0x12,0xe2,0xaf,0x86,0x3e,0xf8,
-0xf7,0x0b,0x1f,0x14,0x17,0x65,0x17,0xd3,0xef,0x56,0x63,0xd7,0x65,0xa0,0xde,0x34,
-0x3d,0xaa,0xda,0x2c,0x8d,0xf6,0xe6,0xf5,0x13,0x37,0x17,0xec,0xc6,0x05,0xcc,0x70,
-0xcc,0xf1,0x5e,0xd4,0x92,0x58,0xf5,0x01,0xcb,0x7b,0xd6,0x12,0xbe,0xab,0x09,0x12,
-0x44,0x93,0x63,0xbd,0x3e,0x27,0xe6,0xd0,0xb1,0x36,0xef,0x23,0x31,0xd7,0x87,0xd9,
-0x0e,0xcf,0x39,0x46,0x3a,0x1d,0xc6,0xf6,0xa3,0xc6,0xdc,0x9c,0x8c,0x5c,0x56,0xab,
-0xb2,0xfe,0x1e,0xcb,0x70,0x3a,0x3e,0xa6,0xda,0x46,0xb5,0x6e,0x4c,0x99,0x1f,0x56,
-0xae,0x6b,0xae,0xf2,0x5d,0xf0,0x6c,0x5f,0x84,0x3a,0xec,0x8c,0xba,0xba,0xc3,0x75,
-0xc3,0x3f,0xb4,0x0f,0x53,0x96,0xe3,0x58,0x90,0xb7,0x58,0x93,0x2f,0xdc,0x20,0x81,
-0x58,0xbd,0x3d,0x27,0x6a,0x71,0x14,0xa0,0xcf,0x81,0xe3,0xd8,0x77,0x07,0x1f,0x5e,
-0x8c,0x8d,0xb9,0xeb,0x1b,0x7f,0xff,0x5c,0xff,0xf7,0xaa,0xd3,0x07,0xaa,0xd8,0x7a,
-0x40,0x35,0x6f,0x82,0xed,0xbf,0xd4,0xd6,0x8e,0x51,0x6a,0x1a,0xba,0x16,0xa6,0xb2,
-0xee,0x3a,0xc5,0x4b,0x67,0x78,0xbc,0x23,0xb7,0xd5,0x9e,0x4f,0x97,0xf3,0x4a,0x76,
-0xdf,0xfd,0x4c,0x0a,0xef,0xc6,0x7c,0xe5,0x58,0x41,0xe6,0xad,0x3f,0xc3,0x73,0xbb,
-0xbe,0x7f,0x7a,0xaa,0x5e,0x57,0xe3,0xfb,0x4e,0x9e,0xf1,0x53,0x43,0x99,0xd7,0x61,
-0xce,0x6f,0xca,0x6e,0x30,0xd7,0x36,0xe5,0x3b,0xcd,0xd1,0xd2,0xef,0x43,0x96,0x34,
-0xa0,0x58,0xe3,0xbd,0xb7,0x30,0x6d,0xef,0x9b,0xaf,0x69,0xde,0x7c,0xfc,0xbd,0xf6,
-0xf1,0xc8,0xa0,0x16,0x73,0x9c,0x44,0xf6,0xc8,0xe8,0x60,0xf6,0x28,0xb4,0x24,0x72,
-0x70,0x10,0xbf,0x9d,0x68,0x74,0xf3,0x50,0x1e,0xce,0x9b,0x13,0x7d,0x4e,0x74,0x79,
-0xb2,0x2d,0x30,0x9b,0x06,0x0a,0x4c,0x1f,0xdf,0xc9,0xfd,0xb8,0xea,0xb4,0xa6,0x6a,
-0xb7,0x6b,0x40,0x79,0xef,0x28,0xc7,0x88,0xca,0x79,0xfb,0xd2,0xeb,0xd2,0x76,0x38,
-0xa6,0x19,0xc9,0x3c,0x9f,0x6c,0x7d,0x57,0x26,0x87,0x4d,0xbd,0x56,0x68,0xcb,0x4a,
-0x32,0xcb,0xbe,0xff,0xf2,0xe0,0xf7,0x53,0xc3,0x25,0x53,0x53,0xa6,0xd2,0x29,0x60,
-0xba,0xc5,0x54,0x66,0xb1,0x9a,0xca,0xac,0xb8,0x16,0xce,0x04,0xb5,0x70,0xa5,0x33,
-0xc0,0x72,0xca,0x73,0xf0,0xdd,0xad,0xe6,0x72,0x2b,0xd6,0xe9,0xc0,0x73,0xa4,0xd3,
-0x67,0xcc,0xe5,0xe8,0xf9,0x63,0xd3,0xe0,0xb7,0x93,0x7c,0xfa,0x71,0xeb,0xe8,0xd0,
-0xb1,0xd1,0x5f,0xff,0x53,0xf1,0xaf,0x21,0x0f,0xbe,0x53,0x2e,0x1d,0x7b,0xfe,0xcc,
-0x1c,0x39,0x38,0x37,0x6d,0x8d,0xf9,0x6d,0x13,0x0f,0x8f,0x4f,0xb8,0x46,0x4f,0xba,
-0xdc,0xa3,0x27,0xdd,0xd0,0xba,0x46,0x2b,0x5d,0x54,0x97,0xd3,0x3c,0xba,0xa4,0xcd,
-0x99,0x20,0x3c,0xaf,0x46,0x3c,0xaf,0x12,0x79,0x5e,0xe5,0x16,0x26,0xaa,0x05,0xe0,
-0x3b,0xf8,0xed,0x12,0xd7,0x81,0xdf,0xc0,0x72,0xe0,0xfb,0x14,0xd1,0xe8,0x49,0xa6,
-0x13,0x7d,0x2e,0x67,0xfa,0x79,0x0f,0x04,0xc9,0x9f,0x5f,0xc0,0xf9,0x73,0xe0,0x39,
-0xd4,0xc3,0x61,0x9e,0x5b,0x88,0x4e,0xa7,0x5c,0xf7,0x5a,0x2f,0x7a,0xbd,0xd6,0x3a,
-0x2f,0xae,0x6d,0x9f,0x4e,0xd6,0xb6,0x13,0x5d,0x5e,0xef,0xf3,0x5b,0xeb,0xfd,0x54,
-0xa7,0xb3,0x2c,0xf7,0x4f,0x37,0xf8,0x67,0xa7,0x1b,0x66,0x09,0xd7,0x09,0xd3,0x81,
-0xe7,0xa0,0xd1,0xe7,0x6c,0x97,0xe6,0x30,0xcb,0x25,0x9e,0x37,0xf9,0x67,0xed,0xcd,
-0xb3,0x7e,0x7b,0x8b,0x7f,0x72,0x58,0x37,0xd9,0x76,0xf9,0x60,0x1b,0xea,0xb8,0x76,
-0x5d,0xe7,0x0d,0xae,0x1d,0xe8,0x03,0x69,0xae,0x85,0x9e,0x83,0x92,0xbd,0xe9,0x25,
-0xed,0x4d,0x45,0xed,0xf7,0xef,0x9e,0xb9,0x2f,0x58,0x5b,0x85,0x05,0x4e,0x2f,0xb2,
-0x5c,0x2f,0xb2,0xdc,0x80,0x35,0xfa,0xb2,0x53,0xbf,0x0c,0x5e,0x3b,0xd5,0xe9,0x90,
-0x43,0x8f,0xd8,0x1b,0x11,0xcf,0xdb,0xe4,0x3c,0x77,0x19,0x56,0xa0,0x3e,0x8e,0x6a,
-0xf4,0x80,0xab,0x1d,0x33,0x1d,0x3c,0x77,0x5a,0x0f,0x07,0x8f,0xc3,0x2e,0x7d,0x38,
-0xe2,0xd2,0x47,0x42,0x2e,0x43,0x08,0xd7,0xb8,0xf3,0x57,0x70,0x04,0x85,0xce,0x20,
-0xa9,0x67,0xef,0x0c,0x41,0x0e,0x1d,0xd7,0xc4,0x61,0xdf,0xdd,0x88,0xb5,0xb8,0xd4,
-0x32,0x5c,0x87,0x1a,0x76,0xa8,0x67,0x87,0xfa,0x37,0x60,0x39,0xd4,0xc4,0x01,0xbb,
-0xb7,0x9c,0x4d,0x48,0x97,0x5f,0xc2,0x2c,0x5f,0x77,0xe9,0xd7,0x81,0xe5,0x51,0x4f,
-0x17,0xe2,0xf8,0x55,0xcc,0xf2,0x88,0xaf,0x3b,0x02,0x01,0xdb,0x31,0x5f,0x77,0xcc,
-0x6b,0x69,0xf7,0x36,0xe9,0x0e,0x35,0xb1,0xb5,0x1d,0xd2,0xda,0x77,0x8a,0xbe,0xe7,
-0xc0,0x81,0x82,0x03,0x0f,0xbf,0x6a,0x7d,0x18,0xf5,0xf7,0x46,0x31,0xc7,0x45,0x96,
-0x83,0xaf,0x0e,0x1c,0xa7,0x81,0x39,0x8e,0x5a,0xe2,0xbd,0xf7,0xc9,0x19,0xee,0xef,
-0x63,0x78,0x4e,0x74,0x7a,0x62,0xb6,0x2f,0xb1,0xea,0xeb,0x5d,0xbd,0xf7,0xa1,0xee,
-0xde,0xa1,0xe7,0xf3,0x0e,0xd1,0x3e,0x51,0xe2,0x9a,0x86,0xac,0x93,0x24,0xdd,0x3f,
-0xe2,0x78,0x98,0xe6,0xac,0x94,0xdf,0x49,0x24,0xe3,0xb7,0x62,0xfd,0xa7,0x94,0x9c,
-0xb2,0x26,0xb5,0x4f,0xa2,0xed,0xa9,0xca,0xfd,0xa7,0xbe,0xbc,0xdf,0xfa,0x65,0xdc,
-0x7f,0x3d,0x8e,0xd9,0xad,0xe4,0xf7,0x3c,0xe1,0x37,0x8e,0x05,0xd2,0x6e,0xcf,0xdf,
-0xd8,0x86,0x5c,0x39,0x04,0xbc,0x66,0x73,0xe1,0x46,0xd2,0x8b,0x5f,0xbc,0xb5,0x45,
-0xf3,0xec,0xb0,0xbd,0xe8,0xec,0x5f,0xfc,0xcd,0xaf,0xaa,0x7f,0x93,0x9b,0x9b,0x9d,
-0x4b,0x3f,0x27,0xfd,0xbe,0x05,0xe5,0xbc,0x73,0x35,0xad,0x42,0xd7,0xb6,0x66,0xd7,
-0x98,0x49,0x99,0x3f,0x95,0xce,0xf8,0x1b,0xe9,0x8a,0xfa,0x2f,0x15,0x1f,0x60,0x47,
-0x0d,0xae,0xe4,0xac,0x0a,0x1e,0x77,0xbb,0x17,0x77,0x42,0xea,0xcf,0xfe,0x9b,0x74,
-0x91,0xf1,0x8a,0x71,0x84,0x9a,0x26,0x7e,0xea,0xff,0x62,0xde,0x47,0x96,0x3b,0x50,
-0x72,0x2b,0x4d,0x45,0x87,0xb2,0xf3,0xc9,0x33,0xe4,0x75,0x6c,0xac,0x57,0x2c,0x5b,
-0x3b,0x7f,0xa7,0x31,0x24,0xfb,0x39,0x14,0x63,0x4f,0xe5,0x5a,0x63,0xc0,0x0d,0xa8,
-0xbb,0xa8,0x3b,0x9b,0x56,0xf7,0xf9,0x9f,0x33,0x3f,0x1f,0x1b,0xd0,0x8e,0x4d,0x0c,
-0x6a,0x27,0xc6,0x06,0xb3,0xc6,0xc6,0x06,0xb3,0xc7,0x80,0xe5,0xf2,0xc8,0x41,0x91,
-0x3b,0x4a,0xfc,0xf6,0x3c,0x29,0xb0,0xcf,0x8e,0x19,0x4e,0x75,0x7a,0x81,0x49,0xd2,
-0xe8,0x43,0x85,0xe6,0xef,0x1f,0xec,0xf9,0xfe,0x5a,0xaf,0xf6,0x1a,0xe4,0xae,0x64,
-0xc7,0x9a,0x3d,0x66,0x2a,0x5c,0x4f,0xe1,0x79,0xba,0x7c,0xfc,0xa3,0x5a,0xcb,0xa1,
-0xf0,0x43,0xe8,0x5a,0x2c,0x6c,0x0e,0x8d,0x7a,0x13,0xec,0x7c,0x90,0x57,0x5e,0xde,
-0xf3,0xca,0xc4,0xe3,0x92,0x09,0xc2,0x71,0xc2,0x72,0x36,0x70,0xce,0xdc,0x2c,0x72,
-0xdd,0x4c,0xb4,0x39,0xb0,0x9c,0xf0,0xbc,0x62,0x9a,0x30,0x1d,0xf1,0x7c,0xa4,0x7c,
-0x06,0xd8,0x3e,0x3d,0x72,0x7c,0x1a,0xc2,0x3a,0x4a,0x98,0xfe,0xe9,0x9f,0x4b,0x3e,
-0xad,0x3c,0x91,0x5d,0xc9,0xd6,0x41,0xb0,0xeb,0x40,0xb0,0x3a,0x9d,0xea,0xf3,0x0f,
-0xdf,0x39,0xf8,0x21,0x37,0x7a,0x82,0xe3,0x46,0x4f,0x72,0xae,0x31,0x60,0xfa,0x09,
-0xb7,0x30,0x7a,0x52,0x80,0xe0,0x47,0x2b,0x79,0xa8,0x81,0xc3,0x6c,0xa7,0xf9,0xf3,
-0xf1,0xd3,0x9c,0x94,0x37,0x07,0xcf,0x1d,0xbc,0x76,0xc4,0x74,0xa8,0x7f,0x13,0x26,
-0xaa,0x04,0x61,0xbc,0x4a,0x00,0x7f,0x1d,0xb8,0x8e,0x7d,0xf6,0x49,0xf0,0xd9,0x81,
-0xe5,0xe7,0xc4,0xba,0x38,0x60,0x39,0xc9,0x9f,0x13,0x8e,0xa3,0xd6,0x02,0x7e,0x7b,
-0x2d,0x61,0xba,0x45,0x64,0x3a,0xae,0x65,0x47,0x1a,0x5d,0xac,0x6f,0xc7,0x3a,0xdd,
-0x4a,0xf4,0x39,0xcc,0x53,0x83,0x60,0xb5,0x39,0xf0,0xdc,0x67,0xad,0xf3,0x81,0xcf,
-0x0e,0x2c,0x17,0xa6,0x1b,0x04,0x8f,0xad,0xc1,0x43,0x18,0x5e,0xef,0x87,0xa0,0x35,
-0xed,0x38,0x6c,0x3a,0xec,0xad,0xcf,0xda,0x74,0xb3,0xc0,0x75,0xec,0xb7,0xcf,0x40,
-0xee,0x1c,0x31,0x7d,0xe6,0x52,0x92,0xe7,0xa2,0xd7,0x0e,0x2c,0x27,0x3c,0x6f,0x46,
-0xe3,0x81,0x26,0xdf,0x5b,0x6f,0x9c,0x7c,0xab,0xa8,0x28,0xab,0xe8,0x69,0xfd,0x05,
-0xce,0x33,0xa1,0xe3,0x4d,0xd7,0x4e,0xc9,0xcf,0x49,0xcf,0x37,0xd4,0x17,0x1a,0xbe,
-0xfa,0x9f,0xca,0xaf,0xbc,0xd6,0x66,0xef,0x82,0x13,0x58,0xae,0x97,0xb4,0x39,0x0e,
-0x17,0xd2,0xe6,0x2e,0xfd,0x12,0xce,0x9b,0x3b,0x5b,0xc5,0xdc,0xf9,0x65,0x5c,0xe7,
-0x8e,0x79,0x2e,0xce,0x4f,0x03,0xbf,0x5d,0xe2,0x39,0xf6,0xda,0x0d,0x44,0x9f,0xbb,
-0x3a,0x24,0x9e,0x13,0x6e,0x77,0x04,0x80,0xe1,0x51,0xae,0x35,0x8a,0x79,0xce,0xb7,
-0x87,0x40,0x9b,0xe3,0x00,0xa6,0x0b,0xc6,0x00,0xd4,0xc0,0x05,0x79,0x63,0x10,0xfc,
-0x76,0x60,0x39,0x3c,0x96,0x3c,0x76,0xc6,0x6b,0xc7,0x5a,0x1c,0x38,0x8e,0x02,0x7b,
-0xec,0x88,0xeb,0xe0,0xb9,0x27,0x5c,0x97,0x13,0xeb,0x5c,0xeb,0x3a,0x04,0x70,0x7d,
-0x8d,0x37,0xac,0xad,0xf2,0x88,0xe5,0xde,0xae,0x28,0xd4,0xba,0x47,0xbc,0x3d,0x11,
-0xd0,0xe5,0xe0,0xb7,0xc7,0xbc,0xdd,0x31,0xf0,0xde,0xe3,0xde,0xae,0x38,0xd4,0xcd,
-0xbd,0xfb,0xaf,0x67,0xdf,0xc5,0x7e,0x5e,0x26,0x59,0xb3,0x4f,0x8d,0xe5,0xf0,0xd3,
-0xa6,0x3f,0xd6,0xb6,0xcc,0x5d,0x5d,0x96,0xd5,0xb2,0x23,0x96,0xaf,0xfa,0x7b,0x56,
-0x49,0x4b,0xf8,0x0d,0xbf,0x67,0x39,0x9e,0xf0,0xf7,0x21,0x66,0x8b,0x9e,0xbb,0xe8,
-0xb1,0x27,0xe6,0xfa,0x71,0x5d,0x1c,0x3c,0x0f,0x3c,0x87,0xc7,0xfc,0xa4,0x91,0xaf,
-0xab,0x3d,0x5c,0x07,0x79,0x10,0x3a,0x3f,0x1d,0xf6,0x09,0xcf,0x3f,0x15,0xd7,0x33,
-0x84,0xf3,0x28,0xad,0x9f,0xa8,0x4d,0x7e,0x97,0x91,0x5a,0x1e,0x94,0xd5,0xaa,0x29,
-0x3e,0xf4,0x0e,0xdf,0xad,0x40,0xfb,0xa8,0x43,0x07,0x8b,0x0e,0x7d,0xf4,0x27,0xdd,
-0x47,0x21,0xa1,0x3f,0x44,0xb5,0x38,0xe1,0x38,0xa9,0x6d,0x23,0x39,0xf1,0x6b,0xb8,
-0xd6,0x8d,0x68,0xf3,0xeb,0x92,0xf6,0x26,0xbe,0xfb,0x2d,0x71,0x9b,0xd6,0xcc,0xbd,
-0x28,0xd6,0xbc,0xbf,0xb8,0x45,0x79,0x0e,0x75,0x75,0x9f,0xdd,0x6d,0xf9,0xec,0x58,
-0x79,0xd1,0x31,0x36,0x27,0x87,0x73,0xea,0x4c,0xfe,0x54,0x5a,0x17,0x0e,0xfa,0xb6,
-0x8c,0x54,0xce,0xef,0xb4,0xde,0x85,0xda,0x18,0x45,0xf2,0x4b,0xd3,0xd3,0x34,0x29,
-0xeb,0x8e,0xab,0x30,0x7e,0x57,0x1e,0xfe,0x8c,0x9f,0x67,0x19,0x13,0xd0,0x5f,0x3c,
-0xf5,0x7d,0x94,0x9e,0x80,0xca,0xdf,0x2b,0x59,0xaf,0xdc,0x7e,0x16,0xf6,0x4b,0xc7,
-0x40,0xc1,0xaf,0x14,0xdd,0xce,0xf0,0x8b,0xad,0x25,0x55,0xce,0x55,0x57,0xd6,0x98,
-0x4a,0xdf,0xad,0xc0,0xcc,0xd9,0x92,0x69,0x79,0x05,0xe7,0x29,0x57,0xe0,0xbc,0xdf,
-0xbe,0xa9,0xb9,0xfd,0xf0,0x1b,0xed,0x43,0xe0,0xf8,0xf8,0x80,0x76,0x1c,0xc7,0x60,
-0xd6,0xf8,0xc4,0x40,0xf6,0xc4,0xf8,0x60,0x36,0x7a,0x8c,0x02,0xb7,0x39,0xa8,0xcd,
-0x1d,0x1f,0x19,0xcc,0x1d,0x49,0xd6,0xb9,0xe7,0x49,0xf9,0x73,0xf0,0xdb,0xe5,0x3a,
-0x9d,0xf0,0x7c,0x78,0xa0,0x60,0xf8,0xf5,0x57,0x73,0x5e,0xdf,0xb7,0x5f,0xb3,0x4f,
-0x3a,0x28,0xe9,0x2a,0xd7,0xc5,0xb3,0xfa,0x1a,0x8a,0x7b,0x93,0xbd,0x4e,0x95,0x35,
-0x0b,0xca,0xfa,0x37,0x3a,0x5e,0x65,0x73,0x6b,0x05,0xb9,0x69,0x05,0x77,0xdf,0xdf,
-0x7b,0xd7,0x6a,0x2a,0xb1,0x5a,0x4c,0x25,0x16,0xd2,0x96,0xa2,0xb6,0xd4,0x4a,0xf9,
-0x0e,0x3a,0xdd,0x6a,0x3a,0x8a,0x03,0x7b,0xec,0x26,0xc4,0x73,0x13,0x62,0xb9,0xa9,
-0x7c,0x1a,0xd7,0xc0,0x99,0x49,0x2d,0x9c,0xa4,0xd3,0x47,0x2a,0x66,0x20,0xa6,0xcd,
-0x88,0xe9,0x23,0x2f,0x58,0x1f,0x3f,0xac,0x78,0x7c,0xb9,0xa5,0xe0,0x32,0x78,0xee,
-0x74,0x3f,0x25,0xff,0x84,0x59,0x6f,0x16,0xd7,0xba,0xa3,0xb1,0xd6,0x81,0xe2,0x8c,
-0x03,0x83,0xdf,0x94,0x0f,0x02,0xcb,0x09,0xd3,0x2b,0x71,0x60,0xa6,0x8f,0x9c,0x14,
-0xbc,0xa3,0x27,0xbc,0xbe,0xd1,0x13,0x3e,0xcc,0xf6,0x31,0xc4,0xf6,0xf1,0xd3,0x2e,
-0xca,0x73,0xe2,0xb3,0x57,0xe1,0xba,0x38,0xd0,0xe5,0xe0,0xb5,0x93,0xf9,0x6a,0xc0,
-0xf3,0x2a,0x8f,0x67,0xfc,0xb4,0xc7,0x3b,0x5e,0xe5,0xa5,0x4c,0x4f,0xea,0xf4,0xf3,
-0xae,0x14,0x9e,0x43,0xfe,0x1c,0xe6,0xa7,0xe1,0x79,0xe7,0xd0,0x82,0x26,0xaf,0xe5,
-0xc1,0x73,0xc7,0x21,0xe6,0xcf,0x69,0x8d,0x3b,0xe1,0x79,0x2d,0xd2,0xe4,0xd0,0x5e,
-0x24,0x5c,0x9f,0x46,0x4c,0x47,0xdb,0x3e,0xeb,0x45,0x1f,0xd6,0xea,0x74,0xfe,0xb9,
-0xa8,0xd3,0x81,0xe7,0x74,0xbe,0x1a,0x6c,0xc3,0xbc,0xf3,0xd9,0x69,0xdd,0x2c,0x61,
-0x7a,0xfd,0x2c,0xd4,0xc3,0xf9,0x66,0x1a,0x92,0x73,0xd5,0x6c,0xf2,0x1a,0x77,0x1c,
-0x76,0x12,0xc0,0xf5,0x81,0x07,0x17,0x07,0x8e,0x96,0xe6,0x1d,0xdd,0xfd,0xc6,0x4f,
-0xf2,0x1c,0xe6,0x2a,0xc2,0xd8,0xb6,0xa2,0x34,0xb7,0xe2,0xee,0xbb,0x2f,0xdc,0x5d,
-0x98,0xb8,0xb8,0xb0,0xe4,0x68,0x59,0x9a,0x77,0xea,0xe7,0x81,0xe7,0xf2,0xdc,0x39,
-0xe2,0x39,0xa7,0xc7,0xb5,0xed,0xc0,0x73,0xd0,0xe6,0x01,0x67,0x4b,0x20,0x6e,0xd3,
-0xc5,0xc3,0xf6,0xa6,0x30,0xd4,0xb5,0x13,0x6d,0x6e,0x10,0x59,0x0e,0x73,0xd0,0x81,
-0xe5,0x6d,0x81,0xa0,0xcb,0x10,0xc4,0xbe,0x3b,0xd5,0xe6,0xee,0xce,0x95,0xa0,0xdb,
-0x10,0x04,0x96,0xc7,0xb8,0x96,0x58,0xd8,0xdd,0x16,0x26,0x8c,0xef,0x4c,0xf2,0x1c,
-0x6b,0x74,0x23,0xf1,0xdf,0x81,0xeb,0x10,0x1e,0x23,0xf1,0xd9,0x65,0x79,0x73,0x23,
-0xae,0x85,0x23,0x2c,0x37,0x12,0x96,0xbb,0xda,0xe2,0xeb,0x5c,0xcb,0x3a,0xc4,0xaa,
-0xdb,0xb0,0x8a,0xeb,0xdc,0x3d,0xc6,0x28,0xe6,0x38,0xd4,0xc7,0x79,0xa9,0x1e,0xef,
-0x8e,0x92,0xdc,0xf9,0xd5,0x68,0xcc,0x63,0x8c,0xc5,0x3d,0xc6,0xf8,0xaa,0xe7,0xca,
-0x2a,0xb4,0x96,0x1f,0x5b,0x2c,0x05,0x79,0xda,0x02,0x7a,0x5f,0xed,0xd4,0xc7,0xbd,
-0xf7,0x1f,0xf5,0xef,0xc5,0x7c,0x7d,0x31,0x98,0x4b,0x4e,0x83,0xe4,0xcf,0x91,0x46,
-0x9f,0xed,0x5d,0x85,0xba,0x38,0x65,0x1e,0x1d,0xd7,0xc1,0x41,0x3e,0x5d,0xd4,0xe5,
-0xd8,0x73,0x9f,0x13,0x39,0x3f,0xdb,0x43,0x58,0x8e,0xa3,0x3f,0x11,0xf3,0xf6,0xc5,
-0x5e,0x79,0xa9,0xfa,0x95,0x3d,0xb9,0x99,0xb8,0x66,0x14,0xd6,0xd9,0x85,0x35,0x69,
-0xe9,0x77,0xe1,0x00,0xd3,0xa5,0xf9,0x5c,0xcc,0x7a,0x72,0xac,0x2f,0xcd,0xf2,0xef,
-0xff,0x69,0x3b,0xd3,0xa7,0xb6,0xce,0x2c,0x8d,0x83,0x31,0x18,0x1b,0xc7,0x71,0x6c,
-0x36,0x63,0x63,0xd2,0x98,0xd5,0x8e,0x31,0x8b,0xd8,0xbc,0x01,0x36,0x9b,0x8d,0x6d,
-0xec,0x4c,0x55,0xaa,0x3f,0x74,0x4f,0x55,0x57,0x77,0xe5,0xcb,0x74,0x92,0xa9,0x8a,
-0x97,0xa4,0x93,0xee,0x9a,0x9a,0xae,0xee,0x0f,0xd3,0x35,0xd3,0x53,0xc9,0x4c,0x9c,
-0x1e,0xa7,0x52,0x09,0x90,0x00,0x5a,0x40,0x3b,0x02,0xa1,0x5d,0x02,0x8c,0x10,0x9b,
-0x90,0x58,0xf2,0xcf,0xcc,0x3d,0xe7,0xdc,0xf7,0xde,0xf7,0x5e,0xdd,0x2b,0xa7,0xbb,
-0xba,0xa9,0x7a,0x7d,0x25,0x8c,0xad,0x05,0x49,0xbf,0xfb,0x9c,0xf3,0x9c,0xe7,0xd5,
-0xd2,0xa9,0x7c,0x8e,0x87,0x66,0x2d,0x50,0xb8,0x7c,0xfc,0xf8,0xb1,0xe3,0xef,0xfd,
-0xaa,0xe9,0xbd,0x25,0xd7,0xdd,0xa5,0x74,0xec,0x61,0x7a,0x37,0x2a,0x68,0x6c,0x41,
-0x67,0x93,0x16,0xbf,0xbf,0x07,0x2c,0xdf,0x8b,0x3e,0xd8,0xdb,0x8d,0x8e,0xee,0x4a,
-0x1a,0x3c,0xa6,0xf2,0xb9,0x2b,0xfc,0xef,0x6f,0xef,0xca,0xba,0xfc,0x11,0x7a,0xde,
-0x69,0x8d,0xee,0x7b,0x2c,0x03,0x9e,0xfe,0xde,0xf2,0xfe,0x63,0x47,0x72,0xa9,0x3e,
-0x22,0xe6,0x56,0x48,0xcc,0xce,0x97,0x8f,0xbc,0x36,0x51,0xef,0xb7,0xa3,0xa5,0x7d,
-0xf4,0x6a,0xa3,0x8a,0x7a,0x3b,0xa7,0x77,0x79,0xad,0xaa,0xfb,0xbe,0xfa,0x47,0x7d,
-0x69,0xdc,0xbe,0x6e,0x1d,0x20,0x0b,0xcf,0x35,0x6b,0xf1,0x5a,0x75,0x06,0x95,0xce,
-0xfc,0x91,0x77,0x31,0x57,0xcd,0x35,0xf5,0x73,0xaa,0xd0,0x99,0x9c,0xe7,0x8b,0xef,
-0xc1,0x2a,0x32,0x4b,0xb9,0xfa,0x31,0xef,0x5d,0xe7,0xfd,0x8c,0xea,0xfe,0x08,0xe8,
-0xd7,0x77,0x7f,0x95,0xf7,0xee,0xc4,0xd7,0xe0,0x69,0xcf,0x9f,0xc2,0x3a,0xfb,0x58,
-0x81,0xd1,0x34,0x5e,0x60,0x42,0xbe,0x0b,0x1c,0x9f,0x19,0x3f,0x32,0x33,0x3b,0x5e,
-0x38,0x6b,0x1d,0x2f,0xb4,0xce,0x4e,0x14,0xce,0x9a,0xc7,0x0a,0xcd,0xc4,0x74,0xa6,
-0xcd,0x69,0x21,0xc3,0xc7,0xb9,0xfe,0xb9,0xc0,0x72,0x5c,0xdf,0x9d,0x98,0xfe,0xfd,
-0xbf,0x1d,0xfb,0x7d,0x5d,0xed,0xa1,0x3a,0xc5,0xf3,0xa8,0xee,0xd3,0xe4,0x72,0x97,
-0x73,0x32,0x9f,0x17,0x75,0x4d,0x43,0xed,0x57,0x57,0xfb,0x3f,0xd4,0xfd,0x30,0x35,
-0xdb,0x99,0x5e,0xaf,0xac,0xc8,0xab,0x7c,0xfe,0x5f,0x65,0xcf,0xed,0x93,0x67,0xed,
-0xb6,0xc9,0x73,0xc8,0x71,0x60,0x3a,0xf4,0xcf,0xe1,0x32,0x9b,0x57,0xc3,0xef,0x4f,
-0x57,0xd9,0x6d,0xd3,0x6f,0xda,0x48,0x97,0x57,0x91,0xd7,0x5d,0x9c,0x3f,0x77,0x18,
-0xab,0xf1,0xe8,0x34,0x02,0xd3,0xab,0x45,0xa6,0x57,0xbb,0x1c,0xc6,0x1a,0xc7,0xec,
-0x54,0xcd,0xec,0x4f,0xdf,0x29,0xfe,0xe9,0xb1,0xa2,0x43,0xc7,0xd8,0xe3,0x54,0x73,
-0x9d,0xf7,0xc5,0x35,0x5d,0x3c,0xda,0x64,0x1d,0xaf,0xb1,0xce,0x9b,0x41,0x9b,0xd7,
-0x2f,0x10,0xcf,0xe9,0x32,0xd4,0xdc,0x7d,0xe6,0x5a,0x81,0xe9,0x35,0x81,0x90,0xa9,
-0x26,0x04,0x0b,0xf8,0xee,0x33,0xd7,0xfb,0x60,0x66,0x0d,0xfd,0xed,0x33,0xe4,0x89,
-0x5b,0x9c,0x11,0x38,0x6e,0x6e,0xf4,0xc1,0xac,0x9a,0xcc,0xf3,0x8b,0xfe,0xa0,0xe5,
-0x62,0x10,0x98,0x0e,0xbd,0x73,0xea,0xa7,0x93,0x36,0x67,0xb5,0xf6,0x79,0x6b,0x0b,
-0xd5,0xdc,0x6d,0xcd,0x58,0x6b,0xc7,0x7a,0x3b,0xd6,0xd8,0xe5,0xd9,0x73,0x56,0x67,
-0x27,0xa6,0x1b,0x16,0xb1,0x6f,0x2e,0x32,0x3d,0x68,0x6b,0x09,0xd2,0x6a,0xc3,0x05,
-0x4c,0x0f,0xd9,0xdb,0x42,0xa0,0xd3,0x69,0xfe,0x1c,0x78,0xde,0x89,0x0b,0x7d,0xed,
-0xce,0xae,0x80,0xdf,0xd9,0xe5,0x87,0xfa,0x3a,0xf0,0x3c,0xea,0x68,0x8f,0xc2,0x31,
-0xe2,0xe8,0x88,0xc0,0xbc,0x5a,0xc4,0xd9,0x19,0x09,0xbb,0xba,0xc3,0x41,0x37,0x78,
-0xdb,0x89,0xe7,0xb2,0x46,0x97,0x59,0x1e,0x76,0x5f,0x0f,0xbb,0x4c,0x5d,0x2e,0x43,
-0x6b,0xb1,0x41,0xf8,0x70,0xce,0x9a,0xf3,0x86,0xf9,0xbd,0x05,0x39,0x45,0xa7,0x8b,
-0x72,0x4e,0x9f,0x2d,0x3e,0x7c,0xf6,0xe7,0xef,0x54,0xfd,0x3c,0x68,0x34,0x04,0x37,
-0xed,0x6d,0x9b,0x30,0x5b,0x4e,0xda,0x9c,0x96,0xd4,0x3b,0x5f,0xe8,0x43,0x9e,0xc7,
-0xe7,0xae,0xc7,0x61,0x41,0xdd,0x1d,0xe7,0xd6,0x04,0x6d,0x0e,0x33,0x6b,0xcc,0xdb,
-0x4e,0xda,0x9c,0xb1,0xbc,0x4f,0x60,0x79,0x6f,0x3c,0xee,0xed,0x8d,0x93,0x36,0x17,
-0xf5,0xb9,0xb0,0xd6,0x17,0x6e,0xae,0x6f,0x79,0xae,0x6d,0x6d,0x78,0xae,0x6f,0xc4,
-0xbd,0xb7,0xe2,0x99,0xda,0x7c,0x20,0x4e,0x6b,0x30,0xae,0xe0,0xb9,0xc0,0x72,0xd4,
-0xe9,0x92,0x2e,0xef,0x5f,0xc7,0x19,0x74,0x1f,0xb1,0x7c,0x7b,0xa1,0x67,0x1b,0x72,
-0x66,0x76,0x3d,0xdd,0xbb,0xdb,0xde,0xde,0x6d,0xe0,0xf8,0x7a,0x80,0x18,0x0e,0x79,
-0x32,0x8c,0xe5,0x38,0x8b,0x2e,0x70,0x7c,0xcb,0x3f,0xbc,0x85,0x1c,0xf7,0x0d,0x6c,
-0x27,0xfd,0xfd,0x49,0xe2,0xf9,0xd0,0x56,0xc4,0x79,0x3b,0x52,0x75,0xbe,0xa4,0x4a,
-0xfa,0x5c,0xe3,0x3e,0xdd,0xa4,0xf7,0xaa,0x40,0x79,0xeb,0x44,0xaf,0x95,0xf7,0xbf,
-0x49,0x97,0xa5,0xec,0x98,0x11,0xf2,0xc2,0x41,0xcd,0x5d,0xf4,0xb5,0xe3,0x75,0x41,
-0x8f,0x4b,0x33,0xe8,0x5c,0x8d,0x1d,0x96,0x7c,0xfd,0xfe,0x4e,0x2a,0x7c,0x2f,0xf5,
-0x87,0x4f,0x0d,0x7f,0xa8,0x2c,0xcd,0xaf,0x84,0x7c,0x79,0x58,0xb0,0x9f,0x1c,0xb0,
-0x9c,0xe5,0xcc,0xe3,0xfc,0x99,0xc8,0x67,0xf5,0x7b,0x5c,0x51,0x97,0xd6,0xd3,0xe5,
-0x5a,0x7d,0x64,0x6e,0x09,0x1f,0xb6,0x05,0xa3,0x0f,0x2e,0x8c,0xce,0xcf,0x0c,0xcd,
-0xa7,0xa3,0xa3,0x69,0xe2,0x35,0xe3,0xf6,0x28,0x31,0x1d,0x2f,0x73,0x7d,0x74,0xe4,
-0xf5,0x23,0x8e,0xdb,0x8f,0x14,0x35,0x76,0x64,0x78,0x94,0xf8,0x8d,0xbd,0x74,0xf0,
-0xba,0xc7,0xa0,0xa7,0xfe,0x60,0x3f,0xe1,0x1d,0x49,0xfc,0xec,0x9f,0xea,0x7e,0x06,
-0xe7,0x53,0x8a,0xf3,0x7d,0xf1,0x9c,0x1f,0x16,0x9f,0x5f,0xa1,0x38,0x8f,0xc9,0x56,
-0xbf,0x54,0x7b,0xfe,0x54,0x7b,0x53,0x68,0x71,0x4f,0x97,0x8b,0xff,0xc0,0xaf,0x6c,
-0xb7,0xa3,0xd0,0xc9,0x2a,0x1e,0x6b,0xd5,0xc8,0x7f,0xd4,0xf9,0x88,0xea,0x5c,0x40,
-0xab,0x1e,0x91,0xed,0x7c,0x42,0xf3,0x7e,0xab,0x79,0xc7,0x9f,0x47,0x69,0x68,0x53,
-0x45,0xfe,0x18,0xe7,0x41,0x95,0x6a,0xca,0xfc,0xde,0x24,0xaa,0xd7,0x34,0xfc,0x7b,
-0xc8,0x63,0xff,0xf0,0xfd,0xbc,0x0f,0xbf,0xfb,0x26,0xff,0xbb,0xc9,0xf1,0x82,0x49,
-0x58,0x34,0xab,0x46,0xf3,0x6a,0xe0,0x87,0xc3,0x3e,0xfa,0x58,0x21,0xd6,0xdb,0xcd,
-0xe3,0x47,0xcd,0x50,0x73,0x37,0x4e,0x1c,0x35,0x4e,0x4f,0x1c,0x9d,0xa6,0xfe,0xf9,
-0xb1,0x69,0xe3,0x44,0x91,0xd1,0x38,0x5e,0x64,0x44,0x96,0x8f,0xbf,0x26,0xf7,0xcf,
-0x27,0xa0,0xf6,0x7e,0x62,0xfa,0x8b,0xff,0x2e,0xfa,0xc2,0xd0,0x9a,0x67,0x90,0xce,
-0xf7,0x34,0x9e,0x7b,0xfe,0xb9,0xd3,0xbc,0xcc,0xf8,0x9e,0xa3,0x5f,0x83,0x57,0xfb,
-0xd9,0xd9,0x9c,0x1e,0xeb,0x57,0xf0,0xac,0x67,0xef,0xf9,0xa6,0x4b,0xf9,0x4d,0xdf,
-0x7c,0x79,0xe6,0x1b,0x60,0x39,0xe8,0x73,0xc7,0xe4,0x39,0x87,0x63,0x12,0xe6,0xce,
-0x2b,0x1d,0x34,0xa7,0x76,0xce,0x09,0x47,0xea,0x99,0xd3,0xbc,0x1a,0xab,0xb5,0xc3,
-0xb2,0x4d,0x43,0x8e,0x0c,0x69,0x74,0xe2,0x3a,0xd4,0xdf,0xab,0x1d,0xc0,0x74,0x58,
-0x58,0x77,0x17,0x34,0xfa,0xfb,0xbf,0x2e,0x7b,0xff,0x8d,0x93,0x79,0x6f,0xb0,0xd7,
-0x97,0xf4,0xf8,0x55,0xf5,0x12,0x78,0xdf,0xde,0xea,0x39,0x71,0xcb,0x6d,0xac,0x75,
-0x7b,0x4c,0x75,0x1e,0x58,0xe8,0x87,0x33,0xd5,0x7b,0x58,0xed,0x1d,0x96,0xcf,0x54,
-0xef,0xf3,0x9b,0x6a,0xfd,0x21,0x63,0x4d,0x28,0x62,0xbc,0x10,0x89,0x1a,0x2f,0x44,
-0xc3,0xa6,0x9a,0xb0,0xcf,0xd2,0xe0,0x83,0x2c,0x38,0x60,0x3a,0xcc,0xab,0x91,0x27,
-0x0e,0x6a,0xee,0x8d,0x12,0xcf,0x81,0xe5,0x21,0x4b,0x63,0x28,0x38,0x73,0x29,0x88,
-0x73,0x6b,0xd6,0x26,0xaf,0x77,0xb6,0xd9,0x8b,0x1e,0x77,0x71,0x06,0x9d,0xb4,0x3a,
-0xd5,0xd9,0x41,0x97,0x43,0xed,0xdd,0x37,0x4b,0x73,0x6a,0xe0,0x87,0x83,0xef,0x91,
-0xc7,0x9d,0xd5,0xde,0x95,0x4c,0x0f,0xdb,0x5a,0xc2,0x21,0x5b,0x73,0x28,0x64,0x6b,
-0x0d,0x91,0x36,0x17,0xf4,0xba,0x94,0x25,0xd3,0x19,0xe0,0x99,0x8e,0xf5,0x77,0x67,
-0xa7,0xc4,0x74,0xc8,0x87,0x03,0xa6,0xc3,0xbc,0x5a,0xd4,0xd1,0x11,0xc5,0xcb,0x4e,
-0xf2,0xc2,0x49,0x33,0xe8,0x6e,0xd9,0x13,0xc7,0x6a,0xee,0xb0,0x7c,0xb6,0xab,0xbe,
-0x3b,0x43,0x95,0x77,0x60,0xc6,0x29,0xdb,0x7b,0x17,0x9e,0x73,0x60,0x41,0xf9,0xeb,
-0xb9,0xe5,0x43,0xd7,0x4f,0x0d,0xb9,0xbf,0x37,0xb8,0xe3,0xae,0xce,0xf8,0xa6,0xbd,
-0x75,0xf3,0xa5,0xfb,0xea,0xcb,0x25,0x0f,0xf4,0xcc,0x05,0x9e,0x7b,0x7a,0x15,0x4c,
-0xa7,0xd9,0xf3,0xeb,0xab,0xa8,0xd1,0xe7,0x7b,0x5e,0x92,0x2f,0xae,0x67,0x65,0x79,
-0xa1,0x6f,0x19,0x7a,0xe7,0xd4,0x3f,0xef,0x5b,0x01,0x4d,0x8e,0xba,0x7c,0xbe,0x27,
-0xbe,0xb6,0xd0,0xbb,0x06,0x97,0xb1,0xee,0x0e,0xfa,0xdc,0x7b,0xfb,0x65,0x62,0xbe,
-0x27,0xb1,0x3d,0xd7,0xbd,0xbd,0xed,0xee,0xde,0x86,0xfe,0x39,0xd4,0xde,0x89,0xe3,
-0x4c,0x97,0x0b,0x1c,0x5f,0x14,0x97,0x9a,0xe9,0x58,0x73,0x27,0x4f,0x1c,0x31,0x7c,
-0x00,0x3d,0x72,0x34,0x7f,0xde,0xb7,0xb5,0x3b,0x77,0x75,0x77,0x77,0xae,0x7b,0x37,
-0xb9,0xd0,0x93,0xc4,0x79,0xb5,0xc0,0xb0,0xa0,0xdb,0x29,0x17,0x8e,0x6a,0xec,0x22,
-0xcb,0xfd,0x43,0x1b,0x9b,0xbe,0x81,0xcd,0x6d,0x5f,0xff,0x76,0xd2,0x77,0x3b,0x09,
-0x0b,0x59,0x0e,0xf5,0xf6,0xe0,0x9d,0xcd,0xb8,0x77,0x38,0xde,0xdc,0x52,0xd9,0x9c,
-0xf1,0xf9,0xc4,0x7d,0xc6,0xbd,0xfe,0xfa,0xf1,0xd7,0xfd,0xd6,0x7e,0x3f,0xb0,0x7b,
-0x33,0x34,0xb2,0x29,0x71,0x5c,0x5c,0xc9,0x20,0x30,0xfc,0xce,0xce,0x4e,0x00,0x7c,
-0x70,0x77,0xb0,0x7f,0xae,0xf4,0xc2,0xb1,0x39,0x74,0xd1,0xd7,0x0e,0x1a,0x5d,0x58,
-0xa9,0xf0,0x48,0x2a,0x15,0xba,0x9b,0xda,0x0d,0x0c,0xef,0xee,0x05,0x06,0xf7,0xa6,
-0x5f,0x74,0x4d,0xd7,0x57,0xe6,0xd7,0xc3,0x9e,0x33,0xb8,0x5f,0x8c,0xb8,0x2f,0x3b,
-0xaf,0x45,0x71,0x4f,0xd8,0xc3,0x62,0x56,0x13,0x37,0xdf,0x93,0xe1,0x13,0xd3,0x98,
-0xdd,0xca,0x56,0x63,0x87,0xd7,0xd2,0xb5,0xab,0xe7,0xae,0x99,0xbe,0xed,0x37,0x81,
-0xf6,0xc6,0x85,0x0c,0x67,0x1a,0x1c,0xbc,0xed,0x82,0x5e,0xc7,0xfc,0xb7,0xb7,0xd3,
-0x72,0x16,0x9c,0xe8,0x77,0x8f,0x3d,0x92,0xb5,0x79,0x8c,0xd5,0xe8,0x47,0xf7,0xc8,
-0x13,0x77,0x1f,0x67,0xd5,0x68,0x7e,0x6d,0x14,0xd9,0x0e,0x2b,0x19,0xb8,0x9f,0xfc,
-0xe0,0x97,0x57,0x3e,0x28,0x3b,0x55,0x58,0xc6,0x67,0xca,0xb0,0x7d,0x25,0xd4,0x7b,
-0xd8,0x6b,0x79,0xd3,0xf9,0xc7,0xc6,0xd7,0x20,0xd4,0xba,0x4e,0xaf,0x06,0xfd,0xb7,
-0x7e,0xa9,0xff,0x0f,0xad,0xdb,0xf9,0x9b,0xff,0x2f,0xce,0x3f,0xa6,0x77,0xbf,0x35,
-0x6f,0x9f,0xd5,0xab,0x55,0xda,0x9b,0xd7,0x93,0x5a,0xb7,0xad,0xf8,0x59,0xd5,0xbf,
-0x51,0x68,0x72,0x95,0x9e,0xd7,0x3b,0xcf,0xe0,0xae,0x28,0x3d,0x60,0x1a,0x9e,0xba,
-0x8c,0xcc,0xfe,0x7c,0x99,0xef,0x6c,0x8e,0x0d,0xf6,0xba,0x86,0x05,0xd7,0xcf,0x96,
-0xe7,0x9c,0xfd,0xe4,0xc9,0xe1,0x4f,0x26,0xbf,0xcd,0x9f,0x04,0x5f,0x3b,0xfa,0xdb,
-0x85,0xc5,0x32,0xe1,0x80,0xe7,0xf2,0xec,0x79,0xe1,0x14,0x30,0x1c,0x75,0xf9,0xf8,
-0x51,0xe4,0x38,0xf3,0xc3,0x49,0x3c,0x17,0x33,0x65,0x48,0x9f,0xcb,0x1a,0xfd,0x2f,
-0xff,0x73,0xfc,0x2f,0x9d,0xed,0x87,0x3b,0xa5,0xf3,0x9b,0x5c,0xee,0x39,0x54,0x3f,
-0x27,0x3c,0xcb,0xb3,0xf8,0x30,0x24,0xbe,0xab,0xf2,0x0f,0x14,0x3c,0xe7,0xfa,0x4b,
-0x6c,0x0f,0x16,0x85,0x37,0x44,0xf8,0xd9,0xb6,0x96,0xc2,0xb6,0xb1,0x17,0x15,0x63,
-0xe0,0x83,0xb3,0x4e,0x9d,0xb3,0x92,0x3e,0x3f,0x6f,0x97,0x79,0x4e,0x2c,0xa7,0x19,
-0xb6,0xf3,0x34,0x73,0x8e,0xf9,0x70,0x55,0x2e,0x98,0x57,0x03,0x7d,0xce,0xea,0xed,
-0xd4,0x4b,0xaf,0x76,0x40,0xcf,0xdc,0x61,0xba,0x40,0x47,0xec,0xa5,0xd7,0x38,0x9e,
-0x3d,0x3e,0xf3,0xac,0xb8,0x38,0xaf,0x58,0x5d,0xd3,0xe2,0xeb,0x10,0xac,0x37,0x78,
-0x67,0xe8,0xe4,0x9d,0x39,0x73,0xfd,0x1c,0x78,0xda,0xb1,0xe6,0x6e,0xae,0xa7,0x65,
-0x69,0xc0,0xa3,0xd7,0x5c,0xef,0x05,0x8f,0x1c,0x68,0x72,0xbf,0xb9,0xde,0x0f,0xb5,
-0x77,0xe0,0x79,0xcc,0x78,0x21,0x16,0x31,0xd6,0x46,0x82,0xe6,0xba,0x20,0xd4,0xd8,
-0x71,0xfe,0xdc,0x02,0x73,0xe7,0x97,0x16,0x80,0xe9,0x4c,0x9b,0xe3,0x9a,0x69,0x0c,
-0x86,0x2d,0x8d,0x61,0xb8,0xec,0x9b,0xb9,0xec,0x83,0x2c,0x38,0xc8,0x95,0x81,0xac,
-0x57,0xe6,0x83,0x63,0x5e,0x38,0x38,0x12,0xc7,0x5b,0x16,0x65,0x86,0x43,0xae,0x4c,
-0x1b,0x2d,0xbb,0x41,0x5c,0x50,0x77,0x27,0x6f,0x3b,0xe8,0xf2,0x88,0xad,0x25,0x02,
-0x2b,0x6c,0x07,0xb6,0x0b,0x5c,0x77,0x18,0x82,0xe4,0x7f,0xa3,0x79,0x35,0xc6,0x72,
-0xe2,0x79,0x17,0xea,0x74,0xc8,0x93,0x81,0x5a,0x7b,0xd4,0x61,0x88,0xc6,0x1c,0x86,
-0x18,0xb0,0x1c,0xd6,0x92,0xa3,0x7d,0x89,0xe9,0xf4,0xb0,0xfb,0x6a,0x58,0xed,0x6f,
-0x67,0x3c,0xf7,0x3b,0xae,0xf9,0x1f,0x8e,0x56,0x3d,0x14,0x7e,0xc9,0x05,0x39,0x59,
-0xbe,0xe0,0x39,0x07,0x9e,0x37,0x9c,0x3f,0xd2,0xf0,0xd9,0xbf,0x37,0x7e,0xf6,0xd2,
-0xd9,0xfd,0x32,0xee,0xee,0x8a,0x6f,0x38,0xdb,0x36,0x64,0x7d,0xde,0xab,0x59,0x6f,
-0xa7,0x3a,0x3b,0xf1,0x7c,0x79,0x5e,0xe0,0xb8,0x97,0x38,0xce,0xf7,0xcd,0xe3,0x0b,
-0x3d,0xf1,0xd5,0x85,0x9e,0xd5,0xb5,0xf9,0x9b,0x6b,0x6b,0xf3,0x3d,0x6b,0xa8,0xd1,
-0x17,0x6e,0x61,0xcd,0x1d,0x6a,0xef,0x5b,0x73,0xd7,0xb6,0x52,0xee,0x8e,0x14,0x1c,
-0x51,0x9b,0x4b,0x2c,0xe7,0xeb,0xed,0xb2,0x46,0x5f,0xf5,0x8b,0xbd,0x74,0x3f,0x5f,
-0x77,0x57,0xf6,0xcf,0xc1,0xd7,0x0e,0xb5,0x75,0xd0,0xe4,0x90,0x2b,0x03,0x2c,0xc7,
-0x5e,0x7a,0x80,0xb2,0x64,0x12,0x81,0xe1,0x04,0xd4,0xd7,0x61,0x16,0x1d,0xea,0xee,
-0x5b,0xbe,0xfe,0x2d,0xe8,0xa7,0xef,0x2c,0xde,0xda,0x81,0x39,0xf4,0xa4,0x6f,0x20,
-0x09,0x3a,0x1d,0xfa,0xe8,0x50,0x83,0x5f,0xf3,0xdd,0x59,0xeb,0xe8,0xa8,0xea,0xe0,
-0x9f,0x33,0xe9,0x73,0x51,0xfc,0x2a,0x2d,0x3d,0x55,0x1a,0x76,0x0c,0x84,0xb1,0xc6,
-0x2e,0x32,0x5c,0x9a,0x31,0x67,0x7e,0xf6,0xc0,0x10,0x71,0x1c,0x35,0xb9,0x58,0x5b,
-0x97,0xbc,0x70,0x23,0x49,0xd4,0xe3,0xd0,0x3b,0x17,0x8e,0x12,0xc3,0xfd,0x03,0x7b,
-0xfb,0x81,0xfe,0xfd,0x7d,0x7f,0xff,0xfe,0x5e,0x60,0x60,0xcf,0xf9,0xfd,0x35,0x67,
-0x75,0x45,0x7e,0x35,0xf4,0xc9,0x81,0xd7,0x8c,0x67,0x2c,0x6f,0x51,0x2f,0x0f,0x35,
-0x23,0x8b,0x23,0x4f,0x3b,0x47,0x46,0x4f,0x97,0xc3,0x5c,0x3d,0xec,0x8f,0xf3,0xf9,
-0x7f,0xdc,0xfc,0x7c,0x27,0xf2,0x70,0x87,0xf8,0x3d,0xba,0xcb,0xfa,0xe1,0xc4,0xf2,
-0x47,0xc4,0x70,0x9e,0xdb,0x12,0xbf,0x1f,0xa2,0x86,0x87,0x79,0x35,0x38,0x22,0xaf,
-0x45,0x5f,0x1c,0xe9,0xf2,0xd1,0x03,0xc6,0x70,0x9c,0x5b,0x8b,0x92,0x3e,0x4f,0x85,
-0xee,0xa5,0x9e,0xfe,0x4b,0xcb,0xd3,0x8a,0xe2,0xa3,0x15,0xe8,0xef,0xd3,0x62,0x78,
-0x6e,0x8e,0x6e,0x36,0xa8,0xae,0xcf,0x4a,0x87,0x3d,0xd9,0xde,0x2b,0x7f,0xcf,0x2f,
-0xbd,0xdb,0xd2,0xe2,0x73,0x36,0x66,0xbf,0xea,0x36,0xb2,0x69,0x6d,0x05,0x5f,0x54,
-0xfa,0x5d,0x8f,0x43,0x8a,0xdb,0xe7,0xf8,0xcf,0xff,0x9d,0xde,0xff,0x9f,0xf1,0x7d,
-0xfe,0x36,0xf9,0xff,0x9f,0xe7,0x01,0xcf,0xf7,0xdc,0xcc,0xf9,0x6a,0x5e,0xbb,0x63,
-0x5d,0x57,0x78,0xdd,0x57,0x55,0xe4,0x56,0xfd,0xee,0x69,0xde,0xef,0xa6,0xbf,0xc9,
-0x9f,0x36,0x8d,0xe5,0x0b,0x1a,0x3c,0xdf,0xc4,0xea,0xed,0xcc,0xd3,0x4e,0x2c,0xa7,
-0xbc,0x57,0xd6,0x37,0xa7,0xdc,0x57,0x95,0x27,0x4e,0xe1,0x73,0x17,0x74,0xf9,0xf8,
-0x09,0x49,0x9f,0xbf,0xf8,0xe2,0xf8,0x8b,0xee,0xce,0xc3,0xdd,0x5a,0x75,0x07,0x5d,
-0x96,0xeb,0x3d,0x3f,0x1a,0x7d,0x1f,0xfe,0xba,0x56,0xdf,0x5c,0x6b,0x4f,0x22,0xd6,
-0x6b,0x6a,0x6f,0x3b,0xd2,0x3e,0xf6,0xe2,0xcc,0x18,0xb0,0x1c,0x16,0xf6,0xcc,0x27,
-0xcf,0x63,0xdf,0x1c,0x98,0x4e,0x35,0xf7,0x4a,0x07,0xf1,0xbc,0xd2,0xcd,0x3c,0xee,
-0x73,0x53,0x94,0x0d,0x87,0x5c,0x87,0x19,0x74,0xb1,0xce,0xce,0xcf,0xab,0xa1,0xcf,
-0x5d,0xd0,0xe6,0xb0,0x3e,0x7a,0x5c,0xfe,0x51,0x49,0x71,0x5e,0x89,0x56,0x8d,0x4f,
-0xfd,0xb8,0xfa,0x6f,0x9f,0xec,0x77,0x99,0xea,0x5d,0x73,0xa6,0xba,0x39,0xe4,0xba,
-0xa0,0xcd,0x61,0x11,0xe3,0x1b,0x3c,0xe0,0x83,0x03,0xa6,0x83,0x2f,0x0e,0x74,0x7a,
-0xc0,0x54,0x87,0xfd,0xf4,0xb0,0xa9,0x36,0x1c,0x35,0xd5,0x44,0xa3,0xc6,0x9a,0x28,
-0x63,0x3a,0xcc,0x9f,0x03,0xd7,0x17,0x66,0x2f,0x2f,0x78,0x2d,0x94,0x25,0x13,0xb0,
-0x34,0xa2,0x3e,0x0f,0x99,0x85,0x25,0x1c,0x59,0xde,0x2b,0x71,0xfd,0xb2,0x0f,0xb2,
-0x5e,0x21,0x1f,0x8e,0xe6,0xcf,0x5b,0x24,0x8f,0x3b,0xd6,0xda,0x25,0xa6,0x37,0xfb,
-0x98,0xa7,0x1d,0x38,0x4e,0xf9,0xed,0xb4,0xd8,0xbc,0x1a,0xe8,0xf2,0x88,0xb5,0x25,
-0x12,0xb5,0x36,0x47,0x91,0xeb,0xb6,0xd6,0x30,0xd4,0xdd,0x81,0xe7,0x52,0x0f,0x5d,
-0xcc,0x78,0xa5,0xd5,0x25,0x2d,0x98,0x3d,0x67,0x2c,0x87,0x9c,0xb8,0x65,0x87,0x61,
-0x79,0xd9,0x6e,0x58,0x8e,0x3a,0xbb,0xa2,0xc0,0x74,0x64,0x39,0xc7,0x74,0xf4,0xc4,
-0xcd,0x5d,0x0b,0xf9,0xed,0x57,0xfd,0xa3,0xf7,0xcf,0x8f,0x42,0x56,0xd9,0xab,0xde,
-0xf3,0xf0,0xb9,0xff,0xce,0xc8,0x99,0x77,0x62,0xe6,0xd6,0x58,0xdc,0xd5,0x15,0x5f,
-0x75,0x5f,0x5d,0x5d,0x73,0x76,0xac,0x41,0xff,0x9c,0xf9,0xe1,0xd4,0x3c,0x07,0xaf,
-0x3b,0xf4,0xce,0x41,0xa3,0x83,0x2f,0x0e,0x79,0x2e,0xea,0x72,0x49,0x9b,0xcf,0xf7,
-0xac,0xc6,0x3d,0x3d,0x71,0xd0,0xe6,0x09,0xcf,0xcd,0x04,0xf1,0xbc,0x2f,0x4e,0x79,
-0x32,0xb7,0x56,0xd7,0x3d,0x37,0xd6,0x53,0xae,0xf6,0x54,0xca,0xd5,0x91,0x5a,0x9f,
-0xbf,0xb9,0xce,0xb2,0x65,0x88,0xe1,0xfd,0xb2,0x4e,0xf7,0x91,0x4e,0x97,0x7c,0x71,
-0x92,0x36,0xa7,0x7a,0xbb,0xc4,0x74,0x41,0x9b,0x83,0x8f,0x7d,0xd3,0xdb,0x87,0xf9,
-0xae,0x98,0xd3,0x2e,0xf0,0x1d,0x33,0x60,0x03,0xc3,0x6b,0xc0,0x71,0x62,0xfa,0x10,
-0x79,0xde,0x05,0x4d,0x0e,0x2c,0xdf,0x59,0xec,0xdb,0x01,0xaf,0x3b,0x1c,0x93,0xbe,
-0xfe,0xe4,0x66,0x60,0x68,0x93,0xb1,0x1c,0xe6,0xd6,0xe2,0xbe,0xe1,0x78,0x5b,0x6b,
-0x65,0x9b,0xfa,0xbd,0xca,0x7f,0xaa,0x96,0x95,0x9f,0x2a,0x0b,0x39,0x07,0x43,0xc4,
-0x73,0xf0,0xb5,0xdf,0xdd,0x02,0x1f,0x1c,0xcc,0x99,0x23,0xc7,0x83,0xc3,0x49,0xf0,
-0xa8,0x53,0x2f,0x5d,0xd4,0xe3,0x58,0x7b,0x1f,0x91,0xf8,0x0e,0x4c,0x4f,0x05,0x81,
-0xe3,0x03,0xbb,0x07,0x8b,0xb7,0x0e,0x0e,0x16,0xfb,0x70,0xed,0xf9,0x6f,0xef,0x01,
-0xcb,0xd3,0xc1,0xe1,0xf4,0xdc,0x74,0xcf,0x5c,0x45,0xe9,0x91,0x0a,0x3e,0xb7,0x81,
-0x65,0x36,0xb0,0xbd,0x18,0x98,0x7e,0x05,0x8d,0xae,0x99,0xad,0xc5,0x74,0xb9,0x46,
-0x3e,0xa6,0xa6,0x4f,0xec,0x50,0xee,0x21,0x98,0xab,0xff,0xf4,0xc3,0xf6,0x4f,0x37,
-0x03,0xa3,0x9b,0xc8,0x6d,0xe0,0x77,0xec,0x61,0x1a,0xb4,0x77,0x3a,0x26,0x2c,0xf6,
-0x3d,0xe1,0x08,0xd7,0x65,0x86,0x43,0x4f,0xfd,0x01,0x6a,0x70,0x76,0xd4,0x5c,0xb1,
-0x07,0xa2,0x26,0x7f,0x20,0xd5,0xda,0xe1,0x98,0x0e,0x3f,0x48,0x3f,0x7d,0xaf,0xed,
-0x69,0xc9,0xe9,0x63,0x25,0xea,0x3e,0x81,0xba,0x0e,0xc9,0xeb,0x98,0x8c,0xde,0x2a,
-0xf7,0xf9,0xf9,0x63,0x58,0xf8,0x77,0xf9,0x12,0xb5,0xab,0x74,0x39,0x47,0x66,0xa1,
-0xc4,0x5a,0xee,0xef,0xf9,0xcf,0x7b,0xfe,0x67,0xf4,0x34,0x3d,0xcf,0xd5,0xac,0x77,
-0x43,0xe7,0x31,0x4b,0xcf,0x07,0xcf,0x71,0x2d,0xed,0xa8,0xc7,0x2a,0x0d,0x5d,0xa9,
-0x7b,0x99,0x67,0x74,0x4e,0x66,0x5d,0x44,0xfd,0xd8,0xd9,0xfd,0xd6,0xd3,0x7b,0xea,
-0x7d,0x3e,0x18,0xdf,0xe1,0x3d,0x71,0xee,0x4c,0xce,0xb9,0xdf,0x3e,0xcd,0xfb,0xed,
-0xd4,0xb7,0xf9,0x53,0xd8,0x33,0x1f,0xcb,0x37,0x93,0xbf,0xbd,0xc0,0x8c,0x4c,0x1f,
-0xa3,0x19,0x74,0x60,0xba,0x82,0xe7,0xa0,0xd3,0x79,0x2f,0xdc,0x04,0x65,0xc3,0xb1,
-0x1e,0x3a,0xef,0x87,0x43,0x9e,0x3f,0xe7,0x78,0x9e,0xa3,0x9a,0xaf,0xe7,0xd9,0xac,
-0xfa,0x9e,0xfa,0xf1,0xf2,0x3f,0xa7,0xf6,0x71,0x68,0xf6,0x89,0xd8,0x3e,0xd2,0x87,
-0xe4,0x39,0x4d,0x75,0x96,0x4b,0x67,0x5b,0x61,0xe7,0xc4,0x8b,0x8a,0x09,0x56,0x6f,
-0x97,0x3d,0x70,0xa0,0xd3,0x99,0x56,0x17,0xb3,0x5e,0xa7,0xcf,0xa3,0x46,0x07,0x96,
-0xc3,0x72,0x4d,0x57,0xb9,0xa4,0xfe,0x39,0xf6,0xce,0x05,0xbd,0x8e,0x7d,0xf4,0x6a,
-0xe1,0x72,0xb5,0xec,0x73,0x17,0x78,0xfe,0xec,0x49,0xf9,0xb3,0xe2,0xd3,0xa4,0xcf,
-0xd9,0xfd,0xe2,0xdf,0x83,0xfc,0xb9,0x74,0xbb,0xe1,0xb5,0x76,0xfb,0x74,0xbd,0xdd,
-0x65,0x6e,0x70,0x41,0x2e,0x1c,0xe5,0xbc,0x36,0xe0,0xcc,0x39,0xcb,0x84,0x83,0x59,
-0x35,0xd8,0x87,0x05,0xb8,0x8e,0x4c,0x37,0x03,0xd3,0xeb,0x90,0xe9,0xb0,0x42,0xa6,
-0xba,0x50,0xc0,0xdc,0x10,0x00,0xff,0x1b,0xce,0xac,0xe1,0x9c,0x5a,0x13,0x72,0x1d,
-0xf6,0x61,0x01,0x3f,0x1c,0xab,0xbb,0x87,0x2c,0x17,0x43,0xc4,0xf3,0x26,0x9f,0x7f,
-0xe6,0xb2,0x3f,0x30,0x73,0x39,0x00,0x47,0xdf,0xec,0x15,0x1f,0x64,0xc4,0x31,0xae,
-0x53,0xdd,0x5d,0x64,0xba,0xb5,0xc5,0x87,0xde,0x37,0x61,0xc9,0x5c,0x07,0x9e,0xb7,
-0x2b,0x99,0x2e,0xe8,0x74,0xa8,0xbd,0x03,0xcf,0xa3,0xb6,0x96,0x68,0xd4,0xda,0x12,
-0x25,0xa6,0xf3,0x79,0xaf,0x1d,0x2a,0x9e,0x77,0x2b,0x98,0xbe,0xe4,0x30,0x2c,0x2d,
-0x3b,0xda,0x96,0x57,0xec,0xad,0x2b,0x70,0x24,0x8f,0xfb,0x35,0xe4,0x39,0xf3,0xb6,
-0xb3,0xe3,0x82,0xb5,0x7b,0xa1,0xff,0x56,0x45,0x3f,0xe4,0x88,0xbf,0xe2,0x23,0x27,
-0xf7,0xe4,0x6b,0xf9,0x27,0xbf,0xfa,0xcf,0x4b,0x5f,0xad,0x3b,0x0c,0xeb,0xeb,0xce,
-0xf6,0x75,0xa8,0xb3,0xc3,0x5a,0x9e,0xbb,0xb1,0x2c,0xd7,0xda,0x95,0x1a,0x9d,0xfc,
-0x70,0xd7,0x57,0xe3,0xee,0x6b,0x71,0xe4,0xb9,0x54,0x67,0x27,0x9d,0x0e,0x7d,0xf3,
-0xf8,0xfc,0x8d,0xf8,0x9a,0xe7,0x26,0xe6,0xcb,0x60,0xbd,0x7d,0xbe,0x17,0xf5,0x39,
-0xcd,0xa1,0xf7,0xae,0x6e,0xcd,0x75,0x6f,0xed,0xb8,0xda,0x77,0xb6,0xe6,0xae,0x8a,
-0xda,0x5c,0xf4,0xc1,0x31,0x6d,0x2e,0x71,0x7c,0x60,0x55,0x5d,0x67,0x97,0x78,0x8e,
-0x3a,0x7d,0x48,0xd1,0x43,0xc7,0xda,0x3a,0xb2,0x7c,0x28,0x41,0x6b,0x98,0x16,0xf0,
-0x1c,0x34,0xb9,0x6f,0x70,0x63,0x6b,0xb1,0x7f,0x6b,0xdb,0x7b,0x6b,0x7b,0xc7,0xdb,
-0xb3,0x03,0x59,0x71,0x49,0x6f,0x6f,0x12,0xea,0xed,0xa0,0xd7,0x25,0x6f,0x5c,0x90,
-0x66,0xd1,0x97,0x3c,0x03,0x4b,0xb5,0xb5,0xe5,0xb5,0xbc,0xaf,0x5d,0xfd,0xf9,0x0a,
-0x3c,0x0f,0x3b,0x06,0xc3,0x58,0x6b,0x0f,0xde,0xc5,0xfa,0xfa,0x76,0xf0,0xee,0x36,
-0x30,0x1c,0x8e,0xc4,0xf1,0x7b,0xdb,0xd4,0x47,0xbf,0x27,0xe6,0xc4,0x51,0x3f,0x1d,
-0x7d,0x6f,0x90,0xf7,0x1a,0x1c,0x26,0x96,0xfb,0xfa,0x0e,0x7e,0x58,0xec,0xfd,0xe1,
-0xc0,0x77,0xeb,0x00,0xf4,0xf9,0x6e,0x70,0x68,0x37,0x1d,0xba,0x9b,0x86,0x3c,0x58,
-0xf7,0x74,0x9f,0xbb,0xa2,0xb4,0xa0,0x02,0xf7,0x58,0x38,0x46,0x7b,0x2e,0x30,0x2f,
-0x1c,0xd4,0xde,0xb1,0x9f,0xcc,0x6a,0xec,0x2c,0xfb,0x86,0xf7,0x78,0xab,0xe7,0xd2,
-0x74,0xf6,0x77,0xe2,0xaf,0x1f,0x2f,0x2a,0x38,0xfe,0x8b,0x7f,0x7e,0xeb,0x17,0x2f,
-0x17,0x46,0x5e,0x62,0x5e,0x4c,0xec,0x91,0xc8,0xf1,0x47,0x52,0x4d,0x9d,0xed,0xb5,
-0x82,0x3c,0x17,0x16,0x6a,0xf0,0x08,0xe5,0xbe,0x49,0x47,0xf1,0xb2,0xa4,0xbf,0x39,
-0x0f,0xbc,0x5c,0x63,0x27,0x2f,0x1c,0x69,0xf8,0x87,0xfb,0xa9,0xc8,0x68,0xea,0xc9,
-0x7b,0xed,0x4f,0x8a,0x4f,0x15,0x15,0x6b,0x66,0x66,0x1c,0x52,0x79,0xfa,0x74,0xe6,
-0x9a,0xff,0xaa,0x2f,0x8d,0x7f,0xa1,0xf8,0x7d,0xe7,0x66,0xf9,0xbb,0x1c,0x25,0xab,
-0x25,0x36,0x6b,0xf1,0x4b,0x83,0x8f,0x6a,0x4f,0x3d,0xff,0x7b,0x90,0x6e,0x2b,0x57,
-0x75,0x3b,0x7a,0xf7,0xe1,0x47,0xfc,0x1b,0xf5,0xfd,0xd4,0x7c,0x1c,0xec,0xfe,0xab,
-0xef,0x57,0x8e,0xca,0x3f,0xa8,0x71,0xff,0x35,0x99,0xad,0x71,0x4e,0xa0,0xa5,0xe7,
-0xb2,0x6a,0xd9,0x1c,0xa5,0xb7,0x8e,0x1d,0xe1,0x75,0x70,0xa6,0x34,0xe7,0xcc,0x27,
-0x4f,0xf3,0xa4,0x7a,0x3b,0xf8,0xe1,0x80,0xe3,0xa6,0x31,0xd2,0xe7,0xc4,0xf2,0x23,
-0x53,0x8a,0x2c,0x99,0x09,0xca,0x92,0x61,0xbd,0x73,0xd9,0x13,0x27,0xcf,0x9f,0xab,
-0x3d,0x71,0x5f,0x7d,0x71,0xfc,0xab,0xae,0x8e,0xc3,0x5d,0xaf,0xfa,0xdd,0x6a,0xcd,
-0x4a,0xa8,0xe7,0x22,0x15,0xec,0x67,0x8f,0x9f,0xe5,0xec,0xf2,0xfb,0xc9,0x72,0xfd,
-0x24,0x4d,0xbf,0x81,0xc8,0xf5,0x0e,0x43,0x61,0xc7,0xc4,0x8b,0x33,0x13,0xb6,0xa9,
-0xb3,0x36,0x58,0xe0,0x83,0x93,0x73,0xdb,0xa9,0x8f,0xce,0x33,0xdd,0x39,0x7d,0x1e,
-0xf3,0xe1,0x80,0xe5,0x94,0xdb,0xfe,0x13,0x41,0x87,0x57,0xdb,0x70,0x3f,0x16,0x51,
-0x9b,0x83,0xaf,0x1d,0x78,0x4e,0xeb,0x82,0xd3,0x69,0xaa,0x71,0x7e,0xf4,0x44,0xd0,
-0xe7,0xa7,0xf3,0x4a,0xd8,0xe3,0x90,0xce,0xb5,0xb8,0x99,0x3a,0xf6,0xb9,0x53,0xfd,
-0x66,0x61,0xb5,0x69,0xac,0xd6,0x04,0x3c,0xc7,0x65,0x69,0x74,0xb9,0x2d,0x8d,0x98,
-0xdd,0x4e,0xc7,0x8b,0x73,0x2e,0xcb,0x45,0x17,0x1c,0x61,0x56,0x0d,0xfc,0xed,0x8b,
-0xe6,0x86,0x45,0xd0,0xe4,0x41,0x73,0xbd,0xb4,0x42,0x96,0xfa,0x50,0xd0,0xd2,0x20,
-0x5c,0x6e,0x0c,0x42,0xad,0x1d,0xe6,0xce,0x61,0x1f,0x16,0x96,0x27,0x03,0xfe,0x76,
-0xe0,0x3a,0xf4,0xd1,0x81,0xe7,0x8b,0x56,0xc8,0x71,0x6f,0x5a,0x84,0x7d,0xd5,0x82,
-0x33,0x6f,0x05,0x61,0x1f,0x96,0xe0,0xec,0xe5,0x20,0xec,0xad,0x06,0x5c,0xa7,0xec,
-0x76,0x96,0x25,0x43,0x75,0xf7,0x80,0xb5,0x19,0x99,0x0e,0xfe,0x37,0x96,0xf5,0x8a,
-0xfb,0xb0,0x60,0xde,0xab,0x01,0xf7,0x62,0x01,0x5f,0x3b,0xd4,0xdb,0x81,0xe9,0x31,
-0x6b,0x73,0x2c,0x62,0x6b,0x8d,0x04,0xed,0x94,0x29,0xc3,0x32,0xe2,0x24,0x8d,0xee,
-0x22,0xa6,0x53,0x9e,0x0c,0x65,0xc4,0xc5,0x1c,0xed,0xb1,0x65,0x7b,0xeb,0xf2,0x4b,
-0x7b,0xeb,0xcb,0x55,0x5b,0xcb,0xea,0x8a,0xa3,0x6d,0x05,0x99,0xce,0x79,0xe1,0x60,
-0xfe,0x1c,0x8e,0x8e,0xa9,0x0e,0xc7,0x95,0xa6,0x37,0xae,0x80,0xb6,0xd2,0xf9,0xc8,
-0x92,0xde,0xab,0xed,0xad,0x25,0xed,0x61,0x4b,0x7b,0x78,0xc3,0xd1,0xb6,0xb1,0xe9,
-0x68,0xdd,0x5c,0x75,0x75,0xaf,0x2e,0xcd,0xdd,0x58,0xc2,0xde,0x39,0x37,0xaf,0x46,
-0x5e,0x38,0xca,0x7a,0x5d,0xf6,0xdc,0x5c,0x86,0x2c,0x38,0x58,0xe0,0x87,0x43,0x8f,
-0x9c,0xc8,0x73,0xd6,0x37,0x67,0x2c,0x27,0x5f,0x3b,0xf0,0xbc,0x67,0x0d,0x7c,0x71,
-0xd0,0x37,0x87,0x5e,0x3a,0xf8,0xdf,0x36,0x3c,0xd7,0x36,0xb0,0xaf,0x2e,0x72,0x1c,
-0xf5,0xb9,0xaf,0x5f,0xd1,0x43,0x57,0xcc,0xac,0xf9,0x95,0xbd,0x73,0xe0,0xb8,0x94,
-0x0f,0x07,0xbd,0x73,0xd0,0xe3,0xa2,0x1f,0x0e,0x59,0x1e,0x18,0x96,0x16,0xd3,0xe4,
-0xdb,0x8b,0x7d,0xdb,0x90,0xd7,0x8e,0xfb,0xb0,0x08,0x2b,0xe9,0xed,0x4b,0x82,0x4e,
-0x97,0xf2,0xe1,0xc4,0x3c,0x19,0xe4,0x79,0xe0,0xee,0x86,0xd7,0xd2,0xe7,0x3d,0xf9,
-0x7a,0xd1,0xc9,0x6c,0x6c,0x28,0x2b,0x3f,0x5d,0x16,0x76,0x0e,0x10,0xcf,0x51,0x9b,
-0x8f,0x6c,0x2b,0x7c,0x71,0xd2,0x3e,0x2c,0x22,0xcb,0x43,0xf7,0xb6,0x19,0xc3,0xd3,
-0xfe,0xc1,0xf4,0xae,0x7f,0x60,0x77,0x37,0x30,0xb8,0x9b,0x0e,0x08,0x97,0x85,0x23,
-0xe3,0x38,0x66,0xc8,0x85,0xef,0xa6,0x80,0xe5,0xe9,0xd0,0x9d,0xb4,0x67,0xea,0xa6,
-0xa7,0xe6,0x6c,0x41,0x0d,0xec,0x39,0xcf,0xfb,0xda,0xf9,0x3d,0x12,0x15,0x3d,0x73,
-0x75,0x36,0xed,0x2b,0x7a,0xe5,0x6a,0xae,0xc3,0x7e,0x67,0x83,0x03,0xd5,0x83,0xf3,
-0xb3,0xc3,0xf3,0xa9,0xd8,0xa3,0x14,0xb1,0x5c,0x5c,0x31,0xbe,0x2f,0xce,0x8e,0x54,
-0x57,0x47,0xcd,0x1d,0xb9,0xb7,0x7f,0x10,0x19,0x39,0xa0,0x1c,0xd7,0x7b,0x07,0x70,
-0x9d,0xd8,0xfe,0x40,0x35,0xcf,0x36,0x2a,0x79,0xda,0xb1,0x1e,0x0f,0x79,0xb0,0x4b,
-0xc2,0x75,0x61,0xa5,0x23,0x0f,0x05,0x7d,0x6e,0x78,0x5a,0x7a,0xfa,0x58,0x29,0x9f,
-0x51,0x2b,0xcd,0x32,0xf1,0xf7,0x59,0x43,0xc7,0x66,0xd5,0xb0,0x6a,0x2e,0xab,0x6b,
-0xc6,0xea,0x9f,0xe0,0x35,0x76,0xae,0xf2,0xfa,0x2b,0x3f,0xd3,0x55,0xfb,0x9a,0x68,
-0xe9,0xaf,0x6c,0x6c,0x84,0xef,0xeb,0xbd,0xf6,0xd4,0x4c,0xcf,0xd0,0xb9,0x3f,0xe6,
-0xb1,0xa8,0x9f,0x2f,0xd5,0xf3,0x93,0xc1,0xfe,0x5c,0x99,0xf1,0x3c,0xd7,0xf5,0xfc,
-0xec,0x7c,0x9f,0x23,0xa3,0xd7,0xaa,0xc5,0xbf,0x2c,0xaf,0x4b,0xf5,0xf9,0x80,0xe2,
-0x77,0x20,0xac,0xd2,0x92,0x9c,0xd2,0xdf,0x3c,0xc9,0xfb,0xcd,0xf7,0xdf,0xe6,0x7f,
-0x3f,0x35,0x96,0x3f,0x05,0x59,0xaf,0x53,0x63,0x05,0x53,0x72,0x36,0x1c,0x2d,0x65,
-0x36,0x9c,0xbc,0x80,0xe9,0x2c,0xeb,0x95,0xf2,0xe1,0x18,0xdb,0xe5,0xfe,0xb9,0x71,
-0xe2,0x84,0x11,0x78,0xde,0xdd,0x71,0xb8,0x3b,0xe3,0xf7,0xa1,0x53,0xd3,0xc8,0x78,
-0x4e,0xb2,0xbc,0x07,0x33,0x98,0xce,0x31,0x5c,0x2f,0xb3,0x87,0xcf,0x5e,0x35,0xb4,
-0x1e,0x31,0x8c,0xbf,0x38,0x33,0x4e,0x3c,0x3f,0x67,0xb3,0x4f,0x9e,0x43,0x5d,0xae,
-0xf4,0xc4,0x9d,0xc7,0x25,0xcd,0xab,0x41,0x26,0x1c,0xf6,0xce,0xab,0x70,0x5f,0x35,
-0xe0,0xb9,0xd5,0x58,0x6d,0x85,0xfd,0xd5,0xe0,0x32,0xe6,0xbd,0x8a,0xbd,0x73,0xe0,
-0x39,0xf4,0xcf,0x3f,0x7e,0x52,0xfe,0x71,0x59,0xc9,0xe1,0x32,0x75,0xc6,0x15,0x7f,
-0x1f,0xd9,0x79,0xc6,0x89,0xe3,0x87,0x4e,0x7c,0xfd,0xbf,0x6f,0x7e,0xed,0x32,0xd7,
-0xbb,0x5c,0x26,0x41,0xa3,0x5b,0x1a,0xdc,0x2e,0x73,0xa3,0x8b,0x2d,0xb7,0xf9,0xa2,
-0x1b,0xb9,0x6e,0xb9,0x38,0x07,0x7b,0xa4,0xe2,0xbe,0x2c,0x1c,0xd7,0xa1,0xa7,0x1e,
-0x30,0xd7,0x07,0x42,0xe6,0xfa,0x50,0xc4,0x54,0x1f,0x09,0x9b,0xeb,0xc2,0xa0,0xd5,
-0x21,0xbf,0x9d,0xf1,0xdc,0x63,0x85,0xe3,0x15,0x91,0xeb,0xe0,0x87,0xa3,0xfd,0x52,
-0xe1,0xb8,0x68,0xbd,0x82,0x4c,0x0f,0xcd,0xbe,0x15,0x8a,0xcc,0x5c,0x8a,0xc0,0x82,
-0x7c,0x38,0xd6,0x43,0xe7,0x67,0xcf,0x69,0xee,0x5c,0xe0,0xb9,0xb5,0x39,0x18,0xb2,
-0x36,0x87,0xfc,0xf6,0x36,0x69,0x5f,0x35,0x96,0xdf,0x0e,0x4c,0x87,0xda,0x7b,0xc8,
-0xde,0x1a,0x8a,0xd9,0x5a,0x62,0x61,0x7b,0x6b,0x18,0xe6,0xd1,0x89,0xe9,0x94,0x0f,
-0x87,0x47,0x67,0x47,0x88,0xaf,0xb9,0x53,0xe6,0x6b,0x57,0x08,0x3c,0xee,0xcb,0xf6,
-0xb6,0x65,0x60,0xf9,0x9a,0xed,0xca,0x5a,0xc2,0x7a,0x25,0xb1,0xe2,0x30,0xac,0x44,
-0x5c,0xdd,0x91,0xb0,0x8b,0x74,0x39,0x5b,0xcf,0x3f,0x6b,0x7e,0x5e,0x79,0xf6,0x58,
-0xe5,0xab,0xf4,0x09,0xec,0x99,0xf6,0xec,0x5f,0xeb,0x9f,0xad,0xb8,0xae,0xae,0x24,
-0x9c,0x86,0x44,0xd2,0xde,0x9c,0x4c,0x38,0xdb,0x13,0x4b,0x9e,0x1b,0x4b,0xa8,0xcb,
-0xb5,0xe6,0xcf,0x99,0x3e,0x9f,0xbb,0x2e,0xce,0xab,0xf5,0xae,0x28,0xf4,0xb9,0xb0,
-0x90,0xe3,0xb8,0xc0,0x0f,0xd7,0x83,0x6c,0x47,0xbe,0x7b,0x89,0xe7,0xe4,0x6f,0xef,
-0x5b,0x25,0x5d,0x7e,0x5b,0xe2,0x36,0xf1,0x7c,0x20,0x83,0xe7,0xc4,0xf0,0x01,0x55,
-0xdf,0x9c,0xb2,0x5e,0xa5,0x59,0x74,0xd1,0x0b,0x47,0x35,0xf6,0xc1,0x04,0xe4,0xc4,
-0xad,0xf9,0x87,0xd7,0xb0,0xd6,0x2e,0xb0,0x1d,0x34,0x39,0xcc,0xa1,0x43,0x96,0xcc,
-0xbe,0xa7,0x7b,0x1f,0xf6,0x62,0x81,0xac,0x57,0x60,0x3c,0xe6,0xc9,0x40,0x7d,0x1d,
-0xe7,0xd0,0x99,0x3e,0xa7,0xbc,0xb8,0x3f,0xfd,0xb1,0xf3,0x4f,0x7a,0xe7,0x45,0xec,
-0xab,0xbc,0xfc,0x54,0x39,0xeb,0x9f,0x67,0xf8,0xe1,0xc4,0x19,0x35,0xca,0x71,0x27,
-0x9e,0x43,0x3f,0x7d,0xcf,0xd7,0xbf,0xb7,0xe7,0xbb,0xbd,0x07,0x2c,0x4f,0x07,0x87,
-0xd2,0x2c,0xfb,0x95,0x38,0x2f,0x30,0x3c,0x78,0x87,0x96,0xf0,0x7d,0xa8,0xb5,0xef,
-0x06,0x07,0x77,0x17,0xa6,0x6e,0x2c,0xd4,0x9e,0x2b,0xa8,0xe5,0x59,0x2e,0xd5,0xd9,
-0x0b,0xa8,0xbf,0xac,0xf6,0x7b,0xab,0xfd,0x62,0x8a,0x5e,0x79,0xb6,0x0c,0x6e,0xe1,
-0xe5,0x51,0x57,0x5b,0x56,0x67,0xfc,0xa6,0xdf,0x98,0x8a,0x3e,0x4c,0xd1,0x9e,0xa7,
-0x1c,0xbb,0x63,0x34,0xa7,0x96,0x8e,0x3e,0x4c,0xe3,0x65,0x36,0xb7,0x86,0x59,0x32,
-0x0f,0xf6,0x64,0x9e,0x8f,0xa0,0xd7,0x6d,0x2f,0x72,0x7f,0x0f,0xeb,0xea,0xa2,0xe7,
-0x8d,0x71,0x9c,0xe6,0xd3,0xc5,0x0c,0x9a,0x25,0xf9,0x88,0xfa,0x3c,0x3c,0x9a,0x02,
-0x9e,0x9f,0x3e,0x75,0xec,0xb4,0x34,0x8b,0xcc,0xcf,0x21,0x33,0x2e,0x69,0xbc,0xce,
-0xb5,0x34,0x67,0x06,0xc3,0x34,0x58,0xa6,0x66,0xa1,0xf4,0x19,0xad,0xa3,0x17,0xd5,
-0xfa,0x2b,0xe3,0xb3,0x39,0xcb,0xbe,0x26,0x19,0x9c,0xd2,0xd0,0xa1,0x3c,0xb7,0xf4,
-0x1e,0x9f,0xfa,0xbc,0x45,0xef,0xb1,0xb3,0xbf,0xd3,0x7b,0x8c,0x8a,0xda,0xbb,0xea,
-0x3c,0x45,0xfa,0xb7,0xb9,0xca,0x9f,0x57,0xf7,0x0a,0xb4,0x74,0x27,0xff,0x5a,0x53,
-0xef,0x67,0x9e,0xad,0x36,0xc4,0x5f,0x97,0xbc,0xdf,0xea,0x7d,0xd1,0x39,0x36,0x22,
-0xcf,0x4b,0x73,0x4b,0x3f,0x7a,0x7a,0xf8,0xa3,0xef,0xbe,0x2d,0xf8,0x0e,0xe6,0xd5,
-0x78,0x6f,0x3b,0xbf,0x48,0xab,0xf3,0x7b,0xa5,0xb2,0x55,0x34,0xa5,0x98,0x57,0x53,
-0x68,0xf3,0xd7,0xa4,0x79,0x35,0xe8,0x9f,0x4b,0xfa,0x5c,0xef,0x1c,0x43,0xbd,0xb4,
-0xce,0x57,0x0e,0xa9,0x7c,0x9a,0x7c,0x16,0x8f,0x6a,0x2f,0x45,0xbe,0x26,0x91,0x2d,
-0xe7,0xbd,0xad,0xb5,0xb0,0x6d,0xec,0xab,0x0a,0xec,0x9f,0xdb,0x26,0xc5,0x5a,0xfb,
-0x24,0xd5,0xda,0x99,0x56,0xe7,0xf7,0x64,0x41,0x7d,0x2e,0xb2,0x5c,0xf2,0xc2,0x4d,
-0xff,0x44,0xca,0x6e,0xa7,0x9e,0xf9,0x05,0xec,0x99,0xb3,0x3c,0x19,0xe2,0x79,0x99,
-0xc0,0xf3,0xbc,0x32,0xbe,0x8f,0xaf,0xb5,0x37,0x04,0xe3,0xfa,0xe3,0x0f,0xca,0x1f,
-0xbb,0x4d,0xf5,0x6e,0x3e,0xbb,0x1d,0x18,0xce,0x38,0xee,0x9e,0x11,0x8f,0x96,0x4b,
-0xa8,0xd7,0x81,0xeb,0x90,0xf7,0x0a,0x0b,0xe6,0xce,0x17,0x2d,0x8d,0x02,0xd7,0x1b,
-0xfc,0x61,0x53,0x5d,0x38,0x62,0xae,0x8b,0x84,0x4d,0xf5,0x61,0xd0,0xe8,0xe0,0x77,
-0x9f,0x9f,0x15,0x74,0xfa,0x0c,0xf1,0xdc,0x33,0x7b,0xc5,0x03,0x73,0x6a,0xd2,0x5e,
-0x2c,0xb3,0xcd,0xb4,0xb7,0x1a,0xec,0x97,0x6a,0x6d,0xf2,0xc1,0x9e,0x6a,0xc0,0xf5,
-0xd0,0xec,0xe5,0x10,0xec,0x97,0x2a,0xe7,0xb6,0x8b,0x79,0xaf,0xf6,0x56,0xbc,0x2e,
-0x33,0xbd,0x25,0x04,0xf3,0xe7,0xf2,0x9e,0x2c,0x1d,0x3e,0xb6,0xff,0x39,0xe8,0x74,
-0xe8,0xa1,0x87,0xed,0x6d,0x61,0xc8,0x86,0xc3,0x3c,0x19,0x76,0xc4,0x05,0x79,0x32,
-0x9d,0xe2,0x9e,0xe7,0xa2,0x46,0x87,0xfd,0x57,0x04,0xa6,0xc7,0x1c,0x1d,0x31,0xd0,
-0xe7,0x09,0x6b,0x53,0x62,0xc3,0x7a,0x79,0x63,0xdd,0x7a,0x65,0x3d,0xe6,0xec,0x88,
-0xf1,0x1a,0xdd,0xef,0xb8,0xea,0x7f,0xf7,0x97,0x35,0xef,0x9e,0x38,0x91,0x7f,0x22,
-0xdb,0x7b,0x1a,0xfe,0x28,0x2e,0x2e,0x2a,0x1e,0xfb,0xb2,0x6d,0x6c,0x79,0xee,0xda,
-0x72,0xc2,0xd9,0x91,0x48,0x39,0x9a,0x53,0x9b,0xce,0xf6,0x4d,0xaa,0xb5,0xf7,0x8a,
-0xba,0xbc,0x07,0xb3,0xe1,0xf8,0xac,0x57,0xca,0x6f,0xef,0x59,0x01,0xae,0x83,0xd7,
-0x9d,0xef,0x9b,0xaf,0x2c,0xf4,0xae,0x30,0x96,0x63,0xef,0x7c,0xfe,0x46,0x62,0xdd,
-0x73,0x7d,0x1d,0x3c,0x71,0x52,0x76,0xbb,0x38,0x7b,0x2e,0xed,0xc5,0xe2,0x15,0xb5,
-0xb9,0x94,0x0b,0xc7,0xfc,0x70,0x83,0x52,0xdd,0x5d,0xab,0xde,0xce,0xf2,0x64,0x12,
-0xfe,0x01,0x41,0x97,0xf7,0x27,0xe0,0x08,0x9c,0xc7,0xbd,0xcd,0xb1,0x06,0x4f,0xb5,
-0x76,0xc8,0x89,0x03,0x96,0x1f,0x78,0xba,0x0e,0x7e,0xf0,0x74,0xfe,0x00,0x39,0x71,
-0x3b,0xde,0xbe,0x9d,0x4d,0xff,0xc0,0x26,0xf5,0xd4,0x29,0x13,0x8e,0xe5,0xc9,0x40,
-0xcd,0x1d,0x8e,0x2b,0xf3,0x43,0x2b,0x43,0x83,0x17,0x86,0xf4,0x9e,0x47,0xf6,0x55,
-0x56,0x76,0x4a,0xd4,0xe7,0xb2,0x1f,0x8e,0xbf,0x2c,0xe7,0xcb,0x90,0x2e,0x47,0x1d,
-0xee,0xef,0x47,0x4d,0x0e,0xbc,0x96,0xbd,0xed,0x23,0x49,0x60,0x37,0xf0,0x1d,0xf5,
-0x3a,0x1c,0x83,0xc3,0xc2,0xf1,0x0e,0x1e,0xe7,0xa7,0x6f,0xce,0x5f,0x38,0x9b,0x7f,
-0x01,0xf6,0x42,0xe4,0x79,0xce,0xb2,0xe0,0x80,0xe5,0xea,0xf7,0x94,0xee,0x5e,0x24,
-0x3a,0xda,0x89,0xbd,0x3e,0x4a,0x4a,0x4e,0x96,0xfc,0xf9,0x8f,0x57,0xff,0x9c,0x8c,
-0x3c,0x4c,0xa2,0x1e,0x47,0x6e,0x93,0xaf,0x1d,0x3d,0xed,0xbc,0xc7,0x5d,0xec,0x93,
-0xd3,0x62,0x3d,0x73,0xae,0xce,0x2e,0xf5,0xc9,0xa9,0xae,0xce,0x7b,0xe3,0x88,0xe5,
-0x2c,0xeb,0xf5,0x6d,0xf4,0xd7,0xed,0x2f,0x3f,0x12,0xf4,0xf9,0xa3,0xfd,0x54,0xe4,
-0x51,0xea,0xf1,0xaf,0xdb,0x1f,0xbf,0x71,0xb2,0xe8,0x0d,0x0e,0x3e,0xfa,0x9a,0x3b,
-0x3b,0xc4,0xb4,0xcf,0x6e,0x39,0xb6,0x2b,0xf8,0xad,0x51,0xf3,0xd6,0x62,0xb1,0xf4,
-0x59,0xab,0xb1,0x47,0xb5,0xfa,0x33,0x5a,0x4b,0x93,0x65,0x68,0x39,0x4e,0x0b,0xff,
-0x35,0x0f,0xef,0x95,0xcf,0x8d,0xce,0xff,0xa7,0xe0,0xbb,0x86,0x26,0x97,0x18,0xc5,
-0xd7,0x24,0xb8,0x7b,0xa7,0x3e,0x1f,0xe0,0x2f,0x4b,0xaf,0xab,0x9c,0x9c,0x43,0x19,
-0xd9,0x7b,0xac,0x06,0xa4,0xde,0x2b,0x54,0x6b,0x4e,0xe1,0x90,0x86,0xb6,0xd5,0xf0,
-0x80,0xc3,0xb1,0xac,0x34,0xa7,0xec,0xe3,0x27,0x79,0x1f,0x93,0x3e,0x2f,0x50,0xf0,
-0x5c,0xda,0x2b,0x75,0x5c,0xb9,0xc7,0x1a,0xe6,0xbd,0x62,0x7e,0xbb,0x98,0xe3,0x2e,
-0x66,0xc9,0x90,0x1f,0x4e,0x3d,0x83,0x4e,0x4c,0xff,0xf2,0xf3,0xe3,0x5f,0x76,0x1a,
-0xf2,0x3a,0x15,0xfa,0x5b,0xe7,0x9c,0x4f,0xeb,0x1c,0x29,0x83,0xe9,0xb9,0x99,0xda,
-0x96,0x7f,0x5c,0x7a,0x3e,0x4f,0x2d,0x8d,0x6e,0x68,0x11,0xf4,0xf9,0xff,0x9d,0x19,
-0xe7,0xb3,0x5e,0xf1,0x38,0x79,0xde,0xc6,0xbc,0x70,0x94,0xf7,0x0a,0xfb,0x9d,0x8b,
-0x7b,0xac,0x89,0x99,0x32,0x90,0x27,0xc3,0xf6,0x63,0x61,0x3d,0x74,0x62,0xfb,0x05,
-0xbb,0xcc,0x74,0x5a,0xcf,0x1e,0x97,0x3f,0x2b,0x29,0x3e,0x5c,0xc2,0x7b,0x19,0xd0,
-0x97,0x27,0xee,0x83,0xce,0x3e,0x8f,0x98,0xa6,0xe8,0x6c,0x7f,0xad,0xd3,0x32,0x5e,
-0x6b,0x61,0x1e,0x38,0xf0,0xba,0xb3,0xbd,0xd5,0x28,0xe7,0x15,0x7a,0xe8,0x17,0xe7,
-0x64,0x8d,0x2e,0xf3,0x1c,0x67,0xd5,0x70,0x5f,0x96,0x4b,0x0b,0xd0,0x3f,0x0f,0x9a,
-0x1b,0x82,0xc0,0xf4,0xa8,0xb9,0x2e,0x1a,0x36,0x37,0x84,0x69,0xf6,0xfc,0xad,0x45,
-0x96,0x0f,0xe7,0xb1,0x36,0x7b,0xa4,0x19,0xf4,0x59,0x79,0x8f,0x35,0xdc,0x5f,0x6d,
-0xf6,0x8a,0x0f,0xea,0xed,0xc0,0xf5,0xf0,0xcc,0xe5,0x30,0x1c,0xfd,0x56,0x9a,0x3b,
-0x97,0x67,0xd0,0x5b,0x24,0xa6,0x83,0x46,0x0f,0x5b,0xc9,0xcf,0x4e,0xfb,0xa0,0x53,
-0xd6,0x2b,0xee,0xaf,0x06,0xbe,0x76,0x60,0xfa,0xff,0x33,0x77,0x25,0x4c,0x51,0x9d,
-0xe9,0x1a,0x10,0x1a,0x68,0x81,0xc8,0xa2,0xe0,0x82,0x22,0x9b,0x11,0x41,0xd9,0x1a,
-0x30,0x28,0x8b,0xb2,0x8a,0xa8,0xc9,0x18,0xeb,0x46,0x72,0x17,0x2b,0xb9,0x99,0x24,
-0xc6,0xe5,0xc6,0x1b,0x53,0xea,0xd4,0x4d,0xca,0xca,0x54,0xaa,0xa6,0x66,0xbc,0x93,
-0x32,0x73,0xa3,0xc6,0x4c,0x8d,0x42,0xa2,0x0d,0x28,0xdd,0xf4,0x0a,0x28,0xbd,0xb2,
-0x28,0x28,0x01,0x04,0x37,0xe2,0xfc,0x95,0x7b,0xde,0xf7,0x3d,0xdf,0x77,0xbe,0x73,
-0xfa,0x34,0x1a,0x93,0xb9,0x75,0x4f,0xf9,0xd6,0x77,0xfa,0xd0,0x36,0xdd,0x4d,0xf7,
-0x79,0xce,0xf3,0x2e,0xcf,0xd3,0x5f,0xee,0x0f,0xf4,0x97,0x05,0x60,0xf5,0xf5,0x97,
-0xfb,0xfc,0xb6,0x72,0x3f,0xcc,0x9b,0x33,0x3d,0x19,0xd0,0x85,0x43,0x4c,0x47,0xef,
-0x54,0xd2,0x7b,0x05,0x8d,0x38,0xc8,0xbb,0x03,0x9e,0x4f,0x5b,0x8a,0xa6,0x61,0x1d,
-0xb5,0x55,0x8c,0x8a,0xf3,0x6a,0x3d,0x9d,0xe5,0x3d,0x95,0xa6,0xd4,0xca,0xe7,0x71,
-0x4a,0xf8,0xbe,0x99,0x2a,0xd2,0x4d,0x76,0xf3,0x6b,0x76,0xc0,0xf3,0x49,0x47,0xc5,
-0x24,0xe0,0xf9,0xb4,0xbd,0x6c,0x7a,0xdc,0x55,0x3d,0x3e,0x3a,0x50,0x33,0xca,0xe7,
-0xcf,0xdd,0x0a,0xa6,0x8b,0x78,0xce,0xfd,0x58,0x38,0x3f,0xaf,0x1b,0x43,0x1c,0x47,
-0x1f,0x74,0xe0,0xe5,0xdb,0x27,0xa7,0x5c,0xd5,0x53,0x10,0xe0,0x9d,0x0a,0x9e,0x6a,
-0xcc,0xff,0x7c,0xfc,0x56,0xc3,0x38,0xc3,0x76,0x86,0xe3,0xbc,0x1f,0x4e,0xe0,0xe8,
-0x30,0xab,0x46,0xab,0x7e,0x0d,0x1d,0xf4,0xe2,0x60,0xee,0x9c,0xe9,0xc8,0x28,0xbd,
-0xee,0x84,0xe9,0x90,0x67,0x87,0x7e,0x77,0xe0,0xe4,0x0b,0xee,0xaa,0x05,0xe0,0xe7,
-0x50,0x3b,0x27,0x9d,0xd7,0xd6,0x29,0x45,0x53,0xa6,0x65,0x8a,0xf1,0x74,0xcc,0xb9,
-0x4b,0x5c,0xfd,0xe2,0xf9,0xea,0x8b,0x2b,0x56,0x2c,0x5d,0xf1,0xbc,0xf3,0x69,0x7a,
-0x7a,0x2a,0xd5,0xcf,0xfd,0x4c,0x43,0x46,0xc0,0x71,0xdf,0x6e,0x41,0xf3,0xb5,0x95,
-0xe6,0xd6,0xa0,0xdf,0x5d,0xc2,0x75,0xa8,0xa1,0xb3,0x99,0x35,0xec,0x87,0xf3,0x40,
-0x0d,0xbd,0x89,0x72,0xef,0x80,0xeb,0xbe,0xd6,0x79,0xc2,0x77,0x19,0xcf,0xaf,0x03,
-0x9e,0x1b,0x10,0xcf,0x51,0x0b,0x4e,0xd0,0x75,0xd5,0xce,0xe3,0xaa,0x3c,0x49,0x84,
-0x9e,0x31,0x6d,0x9d,0x99,0xad,0xe2,0x39,0xdc,0x68,0x8c,0x37,0x9e,0xfc,0xb8,0xf4,
-0xe4,0xe4,0xad,0xf6,0x49,0xe2,0xe5,0x80,0xe1,0x0a,0x56,0xb3,0x3c,0xb9,0x72,0xbc,
-0x1d,0xeb,0xe5,0xb0,0xaa,0xb1,0x9c,0xfa,0xe0,0xf0,0x98,0x06,0xcb,0x91,0xcb,0x8f,
-0xca,0x58,0x3e,0x26,0xeb,0xc5,0x8d,0xbd,0xce,0x75,0x5f,0xe1,0xd8,0x83,0xc0,0xeb,
-0x0f,0x3e,0x3e,0x6c,0xfa,0x18,0xea,0x1d,0x8b,0x61,0x91,0x8a,0x3f,0x8a,0xb7,0x23,
-0x43,0xb9,0xa5,0x1e,0x17,0xd6,0xc5,0x6c,0x8d,0x47,0x9b,0xde,0xf9,0x53,0xef,0x9c,
-0x2b,0x62,0xd4,0xa2,0x1e,0xab,0x9a,0x55,0x85,0x8d,0x9a,0xd7,0xf1,0x52,0x5b,0x64,
-0xc8,0xcd,0xb0,0xf9,0x07,0x9d,0x3b,0xea,0xe6,0x23,0x54,0xef,0xa3,0xf0,0xfe,0x2d,
-0xc6,0xeb,0xf5,0x5e,0xab,0xf8,0x3e,0xe8,0xe1,0x9a,0xf8,0x9e,0xaa,0xfc,0xc3,0x74,
-0x34,0x13,0x54,0xef,0xb1,0xb4,0x9f,0xb1,0x22,0x32,0xe3,0xf4,0x49,0xc8,0xb7,0x1b,
-0x7e,0x00,0x1c,0xc7,0x7c,0xbb,0xb4,0x2a,0xbe,0xe7,0x32,0x96,0xa3,0xff,0x39,0xf3,
-0x3d,0x17,0xfc,0xcf,0xe5,0xde,0x76,0xe2,0xe6,0x62,0x0d,0x3d,0xd1,0xdc,0xdd,0x95,
-0xd8,0xcd,0xf2,0xed,0x17,0xcf,0xcb,0xf3,0x6a,0x61,0xf2,0xeb,0xec,0xb5,0x85,0xec,
-0x6b,0x73,0x3d,0x3a,0xb9,0x78,0xdd,0x5c,0xba,0x66,0x66,0x4d,0xe5,0x4f,0xa0,0xf1,
-0x28,0x60,0xfc,0x1c,0x72,0xed,0xbc,0xbf,0xdd,0xbc,0x96,0xeb,0xb7,0xc3,0x3e,0xcd,
-0x9c,0xaf,0x55,0x69,0xc8,0xa0,0xe6,0x2b,0xd3,0x86,0x93,0x82,0xfa,0xdb,0x09,0xdb,
-0x51,0x4f,0xc6,0x9c,0xe3,0xb0,0xf5,0x64,0xdb,0x6c,0x3d,0xb9,0x36,0x5b,0x77,0x9e,
-0x8d,0xf7,0xb7,0x0b,0xd7,0x22,0xbc,0xff,0x3e,0x26,0xc2,0xc0,0xb4,0x64,0x58,0x9f,
-0x6e,0xc6,0xf2,0xe8,0x8c,0x73,0x7f,0xc8,0x3c,0x47,0xfd,0x70,0x1b,0xa9,0x1f,0xae,
-0x97,0xfc,0x52,0x99,0xd6,0x2b,0xf4,0xc3,0x31,0x1f,0x16,0xc4,0xf4,0x9b,0x84,0xe9,
-0x34,0x7b,0x2e,0x45,0x5f,0xa1,0x84,0xeb,0x45,0x03,0xa0,0x11,0x07,0x18,0x1e,0xe8,
-0xdd,0x80,0x98,0x1e,0xec,0xdd,0x10,0xf4,0xde,0x2c,0xf0,0x82,0xe7,0x39,0xe5,0xdd,
-0x99,0x9e,0x8c,0x1c,0xd6,0x92,0x81,0x6b,0x7f,0xdd,0x74,0xed,0xec,0x67,0xd9,0x67,
-0xbb,0x2e,0x15,0x74,0x11,0x57,0x07,0x4d,0xb8,0x62,0xac,0x97,0x93,0x86,0x7b,0xa9,
-0x3c,0x9f,0x26,0x61,0x7a,0x3f,0x69,0xbd,0x02,0x7e,0xe3,0xec,0xb9,0x84,0xe7,0x41,
-0xcb,0x96,0x60,0xc0,0x5a,0x1c,0x80,0x1c,0x3b,0xd3,0x90,0x41,0x3f,0x16,0x1b,0xf8,
-0xb1,0x94,0x7b,0xfd,0xd6,0x72,0x7f,0xb0,0xbf,0x2c,0x08,0x81,0xf8,0x6e,0x2b,0x0f,
-0x04,0xfa,0xa5,0x90,0xd6,0x60,0xbf,0x29,0x88,0x7a,0xaf,0xb2,0xce,0x2b,0xe1,0xf9,
-0x56,0x1f,0xf4,0xb5,0x03,0x47,0xff,0xd1,0x5a,0xf8,0xe3,0xa4,0xb5,0x78,0x12,0x7a,
-0xdd,0x59,0x7f,0xfb,0x2d,0xeb,0x6b,0xb7,0x0e,0xbf,0x97,0x77,0x38,0x39,0x39,0x36,
-0xf9,0x79,0xdf,0x75,0xf8,0xf7,0xee,0xbb,0xd9,0xef,0xde,0xee,0xdf,0x76,0x1b,0xea,
-0xe5,0xd0,0xd3,0x0e,0xf9,0xf6,0x59,0x5b,0xe9,0xec,0x84,0x63,0xeb,0x04,0x9b,0x3d,
-0x57,0x74,0x64,0x98,0xd6,0x6b,0xfd,0x18,0xd4,0xcc,0xc7,0x07,0x6a,0xe4,0x99,0xf3,
-0x3a,0x9e,0x6b,0x07,0xed,0x76,0xd0,0x94,0x01,0x1c,0x9f,0x18,0xa8,0x99,0xb8,0xef,
-0xae,0xbe,0x3f,0xed,0xac,0x9a,0x06,0x3c,0x87,0xfc,0x3a,0xf9,0xa6,0x36,0x84,0xf2,
-0x73,0x41,0xaf,0x5d,0xa9,0x99,0x0b,0x98,0x2e,0xe8,0xc8,0x28,0x7a,0x32,0x90,0x5f,
-0x6f,0xb8,0xc7,0xb0,0x5c,0xad,0xfb,0x0a,0x35,0x73,0xf2,0x54,0x83,0x7a,0x39,0xf8,
-0xaf,0x3c,0x75,0x55,0x3d,0x9d,0x77,0x57,0xcf,0x83,0x2f,0x0b,0xe0,0xb6,0x88,0xe3,
-0xd4,0xd3,0xae,0xd4,0xcf,0x21,0x02,0x8e,0xc6,0x40,0xf3,0xce,0xec,0xe6,0x45,0x67,
-0xf8,0xe5,0x0d,0xf2,0xed,0x01,0x5b,0x63,0x80,0x34,0xdb,0xb5,0x38,0x2e,0x61,0x38,
-0xcc,0x9c,0x7b,0x5b,0x67,0x67,0xbd,0x6d,0xb3,0xa8,0x0d,0x27,0xcf,0xab,0x11,0x8e,
-0xef,0x99,0x9d,0x09,0xec,0x99,0xc1,0x39,0x35,0x6f,0xeb,0x1c,0xf6,0xbf,0x61,0x7e,
-0xbd,0xe5,0x21,0xec,0x3f,0xf2,0x36,0x3f,0x7a,0xe8,0x69,0xc6,0x7d,0xc0,0xf3,0xac,
-0x95,0x86,0x2c,0xb1,0x66,0x2e,0x72,0x72,0x55,0x2f,0x7b,0xb4,0x5a,0x77,0x22,0xa4,
-0xe7,0x9b,0x71,0xc0,0xc8,0x08,0x15,0xd6,0x81,0x37,0xdf,0x81,0x03,0x1b,0x0e,0x0c,
-0xdb,0x76,0x0d,0x63,0xbd,0x5c,0xc6,0xf3,0x87,0xc1,0x3d,0xa8,0x17,0xc3,0x75,0x63,
-0x64,0x1c,0x7f,0x14,0xdc,0xfd,0x88,0xf7,0xba,0x05,0xda,0x9f,0x28,0x35,0x72,0x0d,
-0x1f,0x07,0x9d,0x19,0x41,0xeb,0x95,0xd6,0x37,0x64,0x4e,0x4e,0xf8,0x0d,0x7a,0xaf,
-0xfc,0x98,0x84,0xe9,0x0f,0x82,0x6f,0x20,0x9e,0xbf,0xb2,0x6c,0xe9,0x2b,0x21,0xe7,
-0xc1,0x70,0x3c,0x48,0x9b,0xef,0x14,0xb9,0xd3,0xf3,0xf0,0x3a,0x4a,0x99,0x89,0x0a,
-0xf1,0xa9,0xd4,0xe8,0xe3,0x6a,0x73,0x1f,0x22,0x96,0x87,0xd3,0xbd,0xd7,0x3e,0x47,
-0xf1,0xeb,0x18,0x82,0xad,0x2f,0x8f,0xe4,0x8b,0x6e,0x7a,0x18,0xae,0x8b,0xf1,0xc2,
-0xe7,0x42,0x78,0x92,0x61,0xb1,0x6b,0xd1,0xeb,0xa5,0x88,0x45,0xb0,0x2c,0x22,0xf4,
-0x7d,0x0a,0xb9,0xbe,0x12,0xbc,0xc1,0x45,0x3c,0x13,0xfd,0x51,0xd9,0xb1,0x8c,0xf4,
-0x08,0x19,0xcf,0x19,0x3f,0xa7,0x9c,0x3b,0xe9,0xca,0x10,0x27,0xbf,0x76,0x15,0xfa,
-0xda,0xd5,0xfd,0xed,0x2a,0x4c,0xef,0x54,0xea,0xe7,0x2a,0xbd,0xd7,0x4e,0x85,0x9f,
-0x5f,0x3c,0xbf,0xf4,0x62,0x45,0xf9,0x92,0x8a,0x90,0x6b,0x19,0xcd,0x75,0x4c,0x48,
-0xcd,0xe1,0x39,0xb5,0x73,0xd5,0x6b,0x17,0x72,0x10,0x7a,0x5a,0x7a,0xa2,0xcf,0x1a,
-0xd7,0xd2,0x93,0x02,0xea,0xe7,0x57,0xbe,0x5d,0x75,0x85,0xe6,0xd5,0x32,0x05,0x3f,
-0x16,0xd6,0xe3,0xbe,0xb6,0x1f,0xb0,0x9c,0x34,0x5f,0xd7,0xf6,0x43,0xbe,0x1d,0xf8,
-0x39,0x70,0x73,0xd0,0x8a,0xb3,0x98,0xd7,0x5b,0xac,0x66,0xb9,0x1f,0xce,0x0c,0xb9,
-0x75,0x59,0x4b,0x06,0xfa,0xdb,0xcd,0x34,0x83,0xce,0xfb,0xdb,0xe5,0xf9,0x73,0xdd,
-0xeb,0x5c,0xd9,0x6f,0x01,0xea,0x7f,0x70,0xbe,0x4a,0x4e,0x88,0x48,0xde,0xb9,0x2d,
-0x71,0xa7,0xf9,0xaf,0x39,0x66,0xf4,0x56,0x83,0x7c,0xbb,0x84,0xeb,0x10,0xe4,0x99,
-0x2a,0xe1,0x79,0xcf,0x06,0xac,0x97,0x03,0xae,0x53,0x0e,0x7e,0x93,0xd3,0x79,0xa3,
-0xd0,0x89,0x5c,0xfd,0xa6,0xc4,0xd5,0xd1,0xfb,0xbc,0xc8,0x05,0x01,0xfb,0x43,0x37,
-0x8a,0xd0,0x97,0x05,0x82,0xf8,0x79,0x91,0xcc,0xcf,0xb7,0xb8,0x99,0x17,0x0b,0xd3,
-0x91,0xe9,0xfb,0xbe,0xa8,0x6f,0x57,0xf3,0x8a,0x5d,0x59,0x59,0x09,0x59,0x67,0xcf,
-0x64,0x9f,0x75,0xf6,0x6c,0x71,0x0e,0x5a,0x4a,0x07,0x99,0x3e,0xdc,0x90,0xb5,0x6c,
-0x88,0xa2,0x1c,0x57,0x8f,0xa5,0xd4,0x43,0xf9,0x77,0xe8,0x81,0x2b,0x1b,0xf6,0x59,
-0x4b,0x7c,0x80,0xe9,0x23,0x7d,0x9b,0x47,0x60,0x5e,0x0d,0x7a,0xda,0x81,0xab,0x2b,
-0x5a,0xaf,0x26,0x0f,0x70,0x74,0xa8,0xa7,0x07,0xfb,0x4b,0x83,0xc0,0xcd,0x01,0xcf,
-0x47,0xfa,0xcb,0xa4,0xdb,0xe5,0xb2,0x86,0x8c,0x29,0x40,0xbe,0xe7,0x5b,0xd1,0x97,
-0x05,0xfb,0xd9,0xed,0x80,0xe9,0x65,0x77,0x00,0xd7,0x11,0xcf,0xa5,0x63,0x90,0x67,
-0xff,0xd3,0x97,0x45,0x7f,0xca,0xdf,0x90,0x94,0xff,0x22,0xdf,0x6b,0xe9,0x43,0x15,
-0xf5,0xe5,0x7f,0x6d,0xfc,0xd2,0x67,0xdf,0xee,0x1b,0x75,0x6f,0x1b,0x9d,0xb0,0x57,
-0x4e,0xcc,0xf4,0x97,0xcc,0x3c,0xb0,0x15,0x3f,0xc0,0x1a,0xba,0xab,0x46,0xee,0x87,
-0x53,0xfb,0xaa,0xa1,0x9e,0x8c,0x9b,0xf4,0xdb,0xc7,0xdd,0x35,0xc8,0xcf,0xa1,0x1f,
-0x0e,0x3c,0xd6,0x10,0xcb,0xa1,0x4f,0xce,0xbd,0x6d,0xf2,0xbe,0xab,0xfa,0xfe,0x8c,
-0xa3,0x62,0x66,0xc6,0x6e,0x9a,0xb9,0xe7,0xde,0x76,0x0f,0x3d,0x59,0x78,0xbe,0xbd,
-0x81,0xbc,0xd0,0x19,0xa6,0x0f,0x11,0xa6,0x87,0xcc,0xab,0x09,0xfd,0x70,0xa1,0x79,
-0x77,0xf2,0x68,0xb9,0x77,0xab,0xe1,0x1e,0xab,0xa5,0x8b,0xb3,0xe8,0x4c,0x23,0xee,
-0x91,0xb3,0xea,0x11,0x68,0xc4,0x81,0x6e,0x3b,0xd4,0xca,0xa1,0xc7,0x9d,0xcd,0xad,
-0xa1,0x96,0x0c,0x7a,0xab,0x91,0x8e,0x3b,0xe3,0xeb,0x41,0x67,0x53,0xf0,0xb7,0xef,
-0x14,0xfe,0x36,0x31,0x31,0x36,0xf1,0x45,0xde,0xcb,0x8c,0xf4,0x94,0x0c,0xbf,0xbd,
-0x89,0xd7,0xcf,0xa1,0xa7,0x7d,0xd6,0xd3,0x32,0x0b,0xfa,0x31,0x80,0xe3,0x33,0xbe,
-0x56,0xec,0x81,0x53,0xfa,0xe2,0xc4,0x20,0x4f,0x74,0xca,0xc3,0xb7,0xcc,0x63,0x8f,
-0x9c,0x77,0x17,0xcf,0xb9,0x33,0x2c,0xc7,0x79,0xb5,0xeb,0x35,0xae,0xcc,0x74,0x43,
-0x26,0xd6,0xca,0x0d,0x4a,0xad,0x5c,0x4f,0x2f,0x2b,0xc4,0xff,0x93,0x9d,0x27,0xc2,
-0xe5,0x04,0x23,0x41,0xff,0x37,0x2a,0xa6,0xae,0x76,0x5d,0x9d,0xf5,0xfb,0x26,0xeb,
-0x83,0xe0,0xde,0x07,0x80,0xe5,0xd4,0x07,0x07,0xba,0xae,0xaf,0x63,0x8d,0x9c,0xd5,
-0xc6,0x1f,0xfb,0xdb,0xb0,0x3e,0xfe,0xd8,0x2f,0xed,0x07,0x77,0xcb,0xfd,0xeb,0x12,
-0x1f,0x0f,0x10,0x8f,0x67,0xf5,0x75,0xa6,0x17,0xc7,0xea,0xef,0x7c,0x66,0x3d,0xc4,
-0x87,0x45,0xd6,0x70,0x67,0xf8,0x3e,0x4a,0xfc,0xfc,0xc4,0x61,0xd3,0x89,0x65,0xcb,
-0x8c,0xcb,0xc2,0x61,0x86,0x88,0x43,0xda,0x3a,0xad,0x2e,0xc7,0xd1,0xe8,0x86,0xeb,
-0xf9,0x4c,0x32,0x9d,0x0e,0x51,0xab,0x23,0x5c,0xdd,0x42,0x55,0xdb,0x8c,0xd0,0x5c,
-0x2f,0xc9,0x4f,0x4c,0x3c,0xe7,0xbf,0xc8,0xe7,0xe9,0xff,0x62,0xd3,0x7b,0x3e,0x2a,
-0x0e,0xaf,0xc1,0x29,0xdd,0xd7,0xa1,0xb9,0x16,0x0c,0xf9,0xfb,0x3c,0xe7,0x78,0xd8,
-0x6b,0x1e,0x0d,0xb6,0x87,0xe0,0x62,0xa4,0x1a,0xdf,0x45,0xed,0xf7,0xd5,0x19,0x91,
-0xab,0xcf,0x7c,0x4a,0xfd,0xed,0xcc,0x5b,0x0d,0xfa,0xdc,0xf5,0xf5,0x64,0x64,0x4f,
-0x35,0x5e,0x47,0xa7,0x1e,0x77,0xc4,0x73,0xae,0x23,0xa3,0xaf,0x27,0x73,0xe1,0xfc,
-0xd2,0x0b,0x15,0xa6,0x25,0x15,0xe2,0x7b,0x25,0xbe,0x27,0xfc,0x3d,0x15,0x5e,0xbf,
-0xca,0x3b,0x4d,0xa8,0xd7,0x84,0xe4,0x1a,0x84,0x1a,0xba,0x6a,0xd5,0xe9,0x7d,0xd3,
-0x6a,0x40,0x62,0x7f,0x7b,0x59,0x6c,0x05,0xf5,0xc3,0x29,0xfc,0xdc,0x72,0x7d,0xad,
-0x45,0xf4,0x66,0x21,0xbd,0x57,0xe6,0xb5,0xb6,0xce,0xae,0xd6,0x7a,0x65,0x7a,0x32,
-0xd9,0xa8,0x29,0x03,0xf5,0x73,0x6b,0x77,0x2e,0x9f,0x3b,0xc7,0x7c,0x7b,0x37,0xe5,
-0xdb,0x61,0x5e,0x4d,0x9b,0x5b,0x50,0xcd,0xad,0x09,0xbe,0x70,0x70,0x9e,0x5a,0xb5,
-0x7c,0xc9,0xaa,0x13,0x1f,0x66,0x9c,0xb0,0xff,0x90,0x67,0x07,0xed,0x57,0xf0,0x4b,
-0x75,0xde,0x80,0x5e,0x38,0xea,0x87,0x73,0xf7,0x32,0x1f,0x96,0x8d,0x03,0xc0,0xcd,
-0x9d,0x37,0x25,0x2c,0xbf,0x59,0xe8,0x82,0x00,0xbf,0x73,0xc2,0x71,0x69,0xed,0x03,
-0x4c,0xdf,0xec,0x82,0x15,0xfa,0xe1,0x58,0x4f,0x9c,0x0a,0xcb,0x39,0x47,0x2f,0xe1,
-0xf1,0xed,0xff,0x6c,0xfc,0xb6,0xa8,0x30,0xb1,0x28,0x29,0xc9,0x90,0x74,0xea,0xc4,
-0xba,0x53,0xbd,0xdf,0x6f,0xee,0x25,0x4c,0x97,0x70,0xbc,0x5f,0xc1,0x72,0xd4,0x86,
-0xb3,0x96,0xd3,0x1c,0x3a,0xf6,0xb6,0x93,0x67,0x2a,0xe4,0xdc,0xa1,0x9f,0x7d,0xbc,
-0xaf,0x68,0x7c,0xdc,0xb2,0x79,0x9c,0x66,0xd5,0xca,0x7d,0xa4,0x25,0x03,0x3c,0xbd,
-0xc2,0x0b,0x98,0x0e,0x81,0x5e,0x6a,0xb6,0x4a,0x2f,0x60,0x38,0xd3,0x87,0x63,0x7a,
-0x32,0xe0,0xad,0x46,0x3e,0xa9,0x32,0xa6,0x3b,0xaa,0xfc,0x23,0xf6,0xca,0x11,0xe8,
-0x71,0xbf,0x6d,0xdb,0x7a,0xfb,0xd2,0xd7,0x5b,0x2e,0x6d,0xdb,0x96,0xb6,0x2d,0x0a,
-0x3e,0x15,0x2f,0xb0,0x25,0x25,0xc5,0x25,0x9d,0xff,0xc3,0xe6,0xf3,0x01,0xe7,0xf6,
-0xc0,0x88,0x7b,0xfb,0x08,0xe0,0x39,0x70,0xf3,0x79,0x5b,0xc9,0x3c,0xaf,0xa1,0xcb,
-0x79,0x76,0x05,0xcb,0x6b,0x47,0x50,0x4b,0x46,0xc2,0x71,0xf2,0x63,0xa9,0xbd,0x03,
-0xf5,0x72,0xcc,0xb7,0x0f,0xd4,0x8d,0x4d,0xb8,0xb7,0x4f,0x00,0x8e,0x43,0xbe,0x1d,
-0x38,0x3a,0x70,0xf3,0x69,0xe7,0xd6,0x69,0xe8,0x6f,0xa7,0x1c,0x3b,0xe4,0xdb,0x1b,
-0xc6,0x99,0xaf,0x9a,0x88,0xe5,0xda,0x59,0x35,0xaa,0x9d,0x33,0x2f,0x16,0x8d,0x3e,
-0xdc,0x30,0xcb,0xb5,0x37,0x4f,0xaa,0xf5,0x64,0x9a,0x91,0x97,0x43,0xc0,0x2c,0xfa,
-0x9c,0xbb,0x7a,0x6e,0x7e,0xa0,0x7a,0x5e,0xd1,0x7b,0x25,0x2c,0x9f,0xba,0xdd,0x3c,
-0x05,0x73,0x6b,0xc0,0xcb,0xa7,0x86,0x5b,0x68,0x46,0x4d,0x0a,0xd0,0x81,0xf5,0xda,
-0x1a,0xbd,0x9f,0x9e,0x28,0xfe,0x74,0xe5,0xaa,0x84,0x95,0x2f,0x7a,0xfe,0xa5,0x7c,
-0x7b,0x23,0xe5,0xdb,0x91,0x97,0xb7,0xe2,0xec,0x39,0xe4,0xd8,0xc9,0x6b,0x4d,0xd6,
-0x97,0x91,0x70,0x9b,0x66,0xd6,0xda,0x67,0x14,0xff,0x95,0xdd,0xb3,0x4c,0xcb,0x7d,
-0xce,0xd7,0x82,0x7a,0x70,0xe0,0xc3,0x02,0x2b,0xf1,0xf4,0x66,0xac,0x9f,0xc3,0xcc,
-0x9a,0xcb,0x5c,0xe7,0x5a,0x93,0x6e,0x58,0xc3,0x7b,0xd9,0xb5,0xfd,0x6f,0xd1,0x6a,
-0xdd,0xf6,0x90,0xfa,0x6c,0x84,0xe6,0x5c,0x29,0x70,0x23,0xf0,0x79,0x29,0x2a,0xc8,
-0x28,0xfa,0xf6,0xab,0xda,0x6f,0x67,0xfd,0x7b,0x67,0x11,0xc3,0xa1,0xdf,0x6d,0x64,
-0xef,0x3c,0xc3,0x66,0xea,0x7b,0xdb,0xf3,0x10,0x39,0x78,0xa0,0x0d,0x7d,0x4f,0x59,
-0x8e,0x9d,0xd7,0xd5,0x31,0x8f,0x4e,0x18,0xce,0x3d,0x57,0xc6,0x42,0x3d,0xd4,0xf8,
-0x31,0xcc,0xb5,0x4b,0xbc,0x7c,0xec,0x75,0x5c,0xf9,0xfd,0x46,0x81,0x9f,0x4b,0x78,
-0xfe,0x91,0x8c,0xe7,0x9a,0xdc,0xb8,0x1e,0x6f,0xd1,0xd3,0xcf,0x52,0xf9,0x38,0xc6,
-0x68,0x74,0xdf,0x75,0x7c,0xda,0xb8,0x17,0x9b,0x98,0xdf,0xd0,0xc9,0xed,0x6a,0x79,
-0xbf,0x2a,0x37,0x20,0xe4,0x08,0xd8,0x39,0xfe,0x1f,0xb9,0xfd,0xa3,0xae,0x13,0x44,
-0x7c,0x0f,0x97,0xa7,0xd7,0xe3,0xa4,0xba,0x58,0xae,0x93,0x67,0xd7,0xfe,0x3d,0x19,
-0x27,0xd5,0xc3,0xef,0x10,0x9e,0x2b,0x84,0xd8,0xf7,0x0d,0xfc,0xfc,0xcc,0x27,0xe2,
-0xbc,0x1a,0x61,0x3a,0xc3,0x72,0xf5,0xbc,0x9a,0x82,0xe9,0x6c,0x66,0x8d,0xf9,0x9f,
-0x2b,0x7d,0x71,0xa4,0xf7,0xaa,0x57,0x3f,0x07,0x3c,0xd7,0xab,0x35,0xa8,0xde,0xc3,
-0xc8,0x30,0xd7,0x3e,0xec,0xf3,0x13,0xb5,0xf8,0x75,0xa8,0x5e,0x84,0xc5,0xf6,0x68,
-0xaa,0x5f,0x03,0x9e,0xc3,0xbc,0x1a,0xfa,0xb0,0x5c,0x53,0xfa,0xdb,0x89,0x8f,0x67,
-0x0a,0xfb,0xeb,0x50,0xbf,0x1d,0xb9,0xb9,0x99,0xea,0xe7,0x10,0x6c,0x6e,0x8d,0xe5,
-0xda,0xa1,0xc7,0x5d,0x55,0x3b,0xef,0x56,0xf0,0x3c,0x35,0x35,0x3a,0x95,0xbd,0x76,
-0xed,0xdf,0x88,0xcd,0xc9,0x8b,0xd7,0x1e,0xf0,0xdd,0x2b,0x7c,0x35,0xae,0xf0,0xdc,
-0x17,0x6b,0xcf,0x39,0xbb,0x37,0x60,0xce,0x9d,0x66,0xd7,0x0a,0x9c,0x8e,0x1b,0x9b,
-0x1c,0x30,0xb3,0x86,0x9c,0x1c,0x70,0xfc,0x46,0xa1,0x8b,0xef,0xcb,0x9c,0x1c,0xa3,
-0xaf,0x48,0xc6,0xf1,0x22,0x37,0xf4,0xc0,0x31,0x3c,0x07,0x1c,0x27,0x2c,0x17,0xf9,
-0x39,0xc3,0xf5,0x12,0xe4,0xe8,0xae,0x9b,0x25,0xae,0xd3,0x27,0xb3,0x4f,0xa7,0x2d,
-0x37,0xa4,0x25,0x25,0x45,0x27,0x1d,0xfa,0xd7,0xd5,0x87,0xae,0x5e,0x2e,0xba,0x3a,
-0xd0,0x57,0x3a,0x40,0x38,0x4e,0x5e,0x2c,0xa4,0x13,0x27,0xeb,0xc9,0xd8,0x98,0xa6,
-0x0c,0xf5,0xb7,0x83,0xce,0x6b,0xc0,0x52,0x1c,0xb8,0x73,0xb3,0xf0,0xce,0xc4,0xcd,
-0x82,0x89,0x51,0xcb,0x96,0x51,0xc2,0xf4,0x4a,0x8e,0xe9,0xe8,0x85,0x2e,0xe1,0x39,
-0xf5,0xc0,0x55,0x62,0xbf,0x3b,0xe8,0xbc,0x02,0x9e,0xc3,0xec,0x39,0xe8,0xc5,0x81,
-0xff,0x0a,0x68,0xbc,0x32,0xef,0x73,0xaf,0xb3,0xda,0x3b,0x70,0x73,0xeb,0xc0,0x57,
-0x7f,0xdc,0xfc,0x55,0x6d,0xed,0xf2,0xda,0xe7,0xcd,0x9b,0x8b,0xdb,0x9a,0xd5,0x49,
-0x6b,0xbe,0x3b,0x5f,0xfa,0x1d,0xe1,0x79,0xcd,0xc8,0xb8,0xb3,0x7a,0xfc,0x9e,0xcd,
-0x74,0x6f,0xc6,0x56,0x32,0x33,0x65,0x2b,0x9f,0x82,0x1a,0x3a,0xe2,0xb9,0x9b,0xf0,
-0x5c,0xd1,0x95,0xa9,0x1d,0xbd,0xe3,0xda,0x7e,0x07,0xfb,0xdb,0x51,0xeb,0x55,0xc2,
-0x73,0x09,0xcb,0x99,0x86,0x0c,0x70,0x74,0xf2,0x58,0x83,0xdb,0xd4,0x13,0x07,0x1a,
-0x32,0xac,0x76,0x8e,0x78,0x2e,0xd4,0xcf,0x95,0x5e,0x38,0xfd,0xfa,0x39,0x62,0x3a,
-0x6a,0xbe,0xea,0xcc,0x9f,0x8b,0xd8,0x8e,0x7d,0x70,0xcd,0xf7,0xa0,0xa7,0x1d,0xbd,
-0x58,0x86,0xea,0xa7,0x67,0x87,0x6a,0x67,0x7f,0xbc,0xbd,0xf3,0x47,0xc8,0xbb,0x33,
-0x3d,0x19,0xc4,0xf1,0xe1,0xa6,0x1f,0x81,0x9b,0xb3,0x5e,0x38,0x08,0xd0,0x8d,0x71,
-0x9a,0x77,0x38,0x8f,0x1d,0x2e,0x3c,0x96,0x99,0x99,0x94,0x19,0x09,0xdf,0xb8,0x17,
-0xdc,0x32,0x32,0x52,0x15,0x7e,0xee,0x6f,0x23,0x4d,0x19,0x19,0xc7,0x15,0x1f,0x16,
-0x11,0xcb,0xdb,0x54,0xfe,0xa9,0x18,0x58,0x57,0x07,0x0f,0x16,0x09,0xd7,0xfd,0x12,
-0xa6,0x23,0xbe,0x43,0x6f,0x7b,0xeb,0x3c,0x60,0x3b,0x84,0xd3,0x5c,0xe7,0x04,0x3c,
-0xe7,0x9a,0x31,0xf2,0x9c,0xb9,0xa8,0x5b,0x2e,0xe6,0x7a,0xf9,0x2c,0x91,0x4e,0x3f,
-0xb1,0x9a,0x1b,0x45,0x46,0xad,0xcd,0x4c,0x5e,0xfb,0xc5,0xef,0x2a,0xbf,0x98,0xf2,
-0xb4,0x4f,0x51,0xdf,0xfa,0x9e,0x79,0xea,0x79,0xdb,0xa3,0xf4,0xb2,0x83,0x86,0x4c,
-0x70,0xdf,0xbc,0xd8,0xfb,0xc6,0x7a,0xe2,0xc8,0xfb,0x54,0xd1,0x84,0x63,0x9e,0xe8,
-0x2a,0x6f,0x74,0xae,0xd9,0xfe,0xc6,0x23,0x45,0x47,0x8e,0x61,0x3a,0xd5,0xd1,0x19,
-0xd6,0x73,0x7e,0x2e,0xe1,0x79,0x4a,0xb2,0x31,0x45,0x9b,0x6b,0xe4,0x9a,0x58,0xd1,
-0x8a,0x0f,0x8b,0xa8,0xf1,0x2e,0xae,0x7c,0x5f,0xf6,0x87,0x60,0xd7,0x40,0xdc,0xa7,
-0x2d,0x3a,0x94,0x83,0x87,0xd3,0xba,0xd2,0xe6,0xf4,0x79,0x0f,0xd8,0xaf,0x84,0xa9,
-0x21,0x9c,0x59,0xc8,0x51,0x8b,0xf7,0x51,0xdd,0x2f,0x52,0x7d,0x5c,0xcb,0xa1,0xd9,
-0xe3,0xfc,0xdc,0xdf,0xfd,0xd2,0xcf,0x5f,0xe6,0xf2,0xe1,0x9e,0xd7,0x62,0x98,0xae,
-0xe5,0xae,0xe1,0x8e,0x85,0xe8,0x02,0xca,0xfb,0xd8,0x0f,0x77,0x52,0xee,0x87,0xeb,
-0x84,0x79,0x35,0x83,0x99,0xf2,0xee,0x4a,0x6f,0xbb,0xb9,0x33,0xce,0x8c,0xf5,0x73,
-0xa6,0x23,0x83,0xbc,0x9c,0xf4,0x64,0x60,0xfe,0x9c,0xcd,0xab,0x51,0x1d,0x7d,0xe9,
-0x75,0x11,0xcb,0xa1,0x76,0x8e,0xf5,0xf3,0xaf,0x13,0x2e,0x02,0x9e,0xb3,0x3e,0xbf,
-0x90,0x6b,0x3b,0xbd,0xfa,0x43,0x98,0x9c,0xbc,0xde,0xb5,0xaa,0x56,0x13,0x4e,0x2f,
-0x17,0xa1,0xaa,0x9d,0x0b,0x3f,0xa3,0x79,0xb5,0x55,0x9d,0xa8,0x27,0x23,0xfb,0xb1,
-0xe0,0xcc,0xf9,0x35,0xad,0x9e,0x0c,0xd4,0xd0,0x15,0x3c,0x47,0x4c,0x97,0x71,0xdc,
-0x71,0x3d,0xcb,0xe1,0x34,0x67,0x39,0x9d,0xd7,0xb3,0x9c,0xdc,0xff,0x3c,0x0c,0x9e,
-0x8b,0xbd,0x8f,0xaa,0xd7,0xa3,0xa7,0x6b,0x27,0x7d,0xd7,0x12,0x8d,0x51,0x89,0x8d,
-0xf5,0xaf,0x34,0x5e,0xfe,0x3a,0xe7,0x32,0xd6,0xd2,0xb1,0xc7,0x9d,0x71,0x74,0xc0,
-0xef,0x4d,0xb4,0xde,0x28,0x74,0x32,0x7e,0xce,0x31,0x5d,0xe4,0xe5,0x12,0x4f,0xe7,
-0x58,0xce,0xf0,0xbc,0x8f,0xf0,0x9c,0xe5,0xd9,0x59,0xb0,0x7e,0x38,0x88,0x7e,0xf3,
-0x96,0xfe,0x8e,0x7f,0x5a,0xd5,0x11,0x1d,0x1d,0x19,0x9d,0x98,0x10,0x93,0xd8,0xde,
-0x96,0xde,0x7e,0xe1,0xcf,0x05,0x17,0xdc,0x7d,0xa5,0x6e,0x05,0xd3,0x15,0x6d,0x38,
-0xc2,0x73,0x13,0xc7,0x73,0xec,0x83,0xc3,0xbe,0xf6,0x12,0xff,0x98,0x65,0xf3,0x18,
-0xf2,0xf4,0xfe,0xd2,0xa0,0xa7,0x9f,0x34,0x64,0x48,0xef,0xb5,0x4a,0xd6,0x7b,0xa5,
-0xf9,0x73,0xaf,0xad,0x0a,0x31,0x9d,0xf9,0xb1,0x90,0xa7,0x9a,0xe2,0xab,0x36,0x6c,
-0xdb,0x3a,0x7c,0xe3,0x6a,0xf9,0x8d,0x4f,0x8e,0x6f,0xf8,0xa4,0xb8,0x38,0xb9,0x18,
-0x34,0x39,0x7f,0xce,0xf7,0x6e,0xfd,0xfa,0x65,0xeb,0xaf,0x7c,0x53,0x7e,0x25,0xe8,
-0xda,0x1e,0x0c,0xba,0x6b,0x82,0x23,0xae,0x1a,0xf4,0x54,0xbb,0xeb,0xac,0xba,0x3b,
-0x69,0xaf,0x9c,0x1c,0x77,0x6d,0x23,0x3c,0x17,0xe7,0xd4,0x06,0xeb,0x64,0x9d,0xd7,
-0xea,0xbb,0x13,0x2e,0xd0,0x92,0xd9,0xce,0xf1,0xfc,0xce,0x60,0x2d,0x62,0x38,0xd7,
-0x89,0x03,0xdd,0xd7,0x21,0xd1,0x37,0x55,0xce,0xb5,0x0f,0x35,0xf0,0x00,0x2c,0xc7,
-0x3c,0xfb,0x10,0xab,0xa3,0x6b,0xb0,0xfc,0x96,0x92,0x63,0x47,0x5c,0x1f,0x6e,0xd4,
-0xf4,0xc2,0xc9,0xbe,0xe7,0xdc,0x07,0x9d,0x66,0xd3,0x60,0x6e,0x6d,0xea,0x76,0xc3,
-0x14,0x6a,0xbd,0x7a,0x14,0x3d,0x19,0xd4,0x7d,0x95,0xb0,0x9d,0xea,0xe7,0x2d,0x58,
-0x3f,0x07,0xfc,0x1f,0xee,0x6f,0x18,0xfe,0xcb,0x1f,0xab,0xfe,0xb2,0x7f,0x5f,0xce,
-0xfe,0xd4,0x54,0x63,0xea,0xcf,0x3d,0xad,0xd1,0xbc,0x1a,0xf4,0xc3,0xb5,0xa9,0xe7,
-0xd5,0xf8,0xfc,0x79,0x3b,0xd7,0x80,0x45,0x2e,0xee,0x6d,0xc5,0xd9,0x73,0x3e,0x93,
-0x26,0xcf,0xa5,0xf1,0xf9,0x34,0x1f,0x60,0x78,0xcb,0x1c,0xf1,0x72,0x0a,0xc0,0x78,
-0xd0,0x87,0x5b,0xbd,0xc2,0xb0,0x5a,0xa5,0x7b,0x2a,0xe8,0xa1,0x89,0xe7,0x3f,0xce,
-0xd1,0xa3,0x42,0xcf,0x8b,0xaa,0xfc,0xa6,0xf4,0x2f,0x25,0x25,0x3e,0xe5,0xfd,0x7f,
-0x2f,0x7a,0x3f,0xe0,0x6e,0x0b,0x20,0x66,0x03,0x27,0x0f,0xee,0x95,0x31,0x9c,0x6a,
-0xe8,0x7c,0xf6,0x1c,0xf3,0xe6,0x32,0x57,0x1f,0xdd,0x27,0x6b,0xb6,0x8b,0x33,0xe8,
-0x6f,0x28,0xfa,0xec,0x3c,0xb7,0x2e,0x6a,0xc0,0x8a,0xa1,0xf1,0x67,0x61,0xb8,0x8e,
-0xb1,0xef,0xd1,0xbc,0x7f,0xef,0xfc,0xa7,0x47,0xca,0x3e,0xcd,0x48,0x33,0x66,0x70,
-0x2d,0x5b,0xe8,0xaf,0x89,0x8b,0x48,0x60,0x3e,0xef,0x4c,0x1b,0x4f,0x0c,0xfc,0xb9,
-0xdc,0x2b,0xc8,0xb4,0x6f,0x45,0x9d,0x1d,0xad,0x5e,0x9e,0xf8,0x5e,0x89,0xf9,0x72,
-0xf1,0xfc,0xc4,0xb1,0xea,0x25,0x36,0x3d,0xec,0x55,0xfd,0x4c,0xc4,0x3d,0x96,0xab,
-0x17,0x79,0x9f,0x16,0x8b,0x23,0x75,0x9e,0x8b,0x80,0xdb,0xfc,0x31,0x74,0x7e,0x67,
-0x08,0x7f,0x0c,0xc3,0xbb,0x7f,0xc9,0xa6,0x7b,0xed,0x21,0x9f,0xf3,0xc3,0x9d,0xfb,
-0xf5,0x30,0x4d,0x9b,0xc7,0xd5,0xd6,0x69,0xb5,0xd7,0x5e,0xb0,0x4f,0xf5,0xf3,0xe8,
-0xd3,0xc8,0xcf,0x3b,0x63,0xcc,0x0c,0xcf,0x49,0xc7,0x9d,0xb8,0x39,0xe0,0xb9,0xb9,
-0x2b,0xce,0xcc,0xf4,0xdb,0x49,0xbb,0x1d,0xbc,0x58,0x64,0x0d,0x77,0xd4,0x94,0x91,
-0x7b,0xda,0x05,0xfd,0x76,0xea,0x87,0x23,0x4c,0xc7,0xfe,0x76,0x53,0x74,0xa5,0x6e,
-0x6f,0x46,0xb8,0x7a,0x78,0xc8,0x75,0xb4,0x4e,0xfd,0x2b,0x42,0xf3,0x5e,0x68,0x71,
-0x7d,0x89,0x7e,0x0d,0x9d,0xe5,0xa0,0xe0,0x98,0xa9,0x34,0xce,0x04,0xfa,0xed,0x80,
-0xe5,0xac,0x86,0xce,0xf4,0x5e,0x95,0xde,0xb8,0x75,0x56,0xe0,0xe7,0x56,0xb3,0xb4,
-0x9a,0x65,0x9e,0x2e,0xf4,0xc5,0x39,0xcc,0x59,0x0e,0x08,0xa7,0x79,0xbd,0x13,0xfc,
-0x58,0x78,0x7f,0x7b,0x8f,0xc2,0xd3,0x79,0xbe,0x3d,0xcc,0xb5,0x4b,0xb8,0x1e,0x08,
-0x78,0x8e,0xe9,0x69,0x31,0xe9,0xef,0xfd,0xdb,0xf2,0xf7,0x7a,0x3b,0xf3,0x7a,0x51,
-0x1f,0xae,0x17,0x3c,0xcf,0x37,0xa2,0x56,0x1c,0xeb,0x6f,0x27,0x6c,0x57,0x30,0x1d,
-0xa3,0x4f,0x9d,0x6f,0x57,0xf1,0x73,0x19,0xcb,0x69,0x15,0xf3,0xed,0x54,0x3f,0x17,
-0xc3,0xfc,0xb7,0x42,0x73,0x49,0xc9,0x2b,0x25,0xf0,0x79,0x34,0x1a,0xa3,0x8d,0x35,
-0xdb,0xd2,0x6a,0xce,0x7d,0xb9,0xe1,0x9c,0xb3,0xb7,0xd4,0x39,0x68,0x29,0x1b,0x1c,
-0xb0,0x96,0x0d,0x40,0xee,0x7d,0xd0,0x52,0x3e,0x38,0x68,0x2d,0x1b,0x1c,0xb2,0x40,
-0x1e,0xde,0x34,0x34,0xd4,0x5f,0x2e,0xe1,0xbd,0xe9,0x16,0x8b,0x61,0x6b,0xf9,0xb0,
-0xc7,0x52,0xe6,0xf1,0x58,0xcb,0x3d,0xb7,0xad,0x30,0xc7,0x56,0x79,0x1b,0x7a,0xe4,
-0x60,0x05,0x2d,0x77,0xf4,0x46,0xb7,0x55,0x0d,0xb3,0xf0,0xf6,0x4b,0x9c,0xdd,0x56,
-0xe5,0x81,0xfd,0x21,0x4b,0xe5,0x90,0xa3,0xa7,0xc2,0x71,0xf5,0x72,0xe9,0xd5,0xd3,
-0xff,0xf9,0xea,0xe9,0xb6,0xe6,0x15,0x6d,0x69,0x69,0xf1,0x69,0x2f,0xf3,0x2d,0xcc,
-0xcf,0x4f,0xc9,0xef,0xba,0x64,0xea,0x02,0x3c,0x87,0x7c,0x3b,0x60,0x3a,0xf8,0xa3,
-0xc2,0xec,0x39,0xf4,0xbb,0x8f,0xb9,0xb7,0x8f,0x01,0x37,0xa7,0xbe,0x76,0xc6,0xd1,
-0xeb,0x46,0x20,0xd7,0x3e,0xe9,0xdc,0x3a,0x79,0xcf,0xb9,0xf5,0x1e,0x70,0x74,0xc0,
-0x73,0x08,0xc8,0xbd,0x33,0x1c,0x57,0x74,0xdc,0x77,0x8e,0x07,0xdc,0xf5,0x01,0xaf,
-0xad,0xde,0xeb,0xb3,0xd7,0xfa,0x7c,0xf6,0x3a,0x9f,0xd7,0x5e,0xe7,0x85,0xd5,0x67,
-0xaf,0xa7,0x70,0xd4,0xfb,0xfc,0xf6,0x7a,0xbf,0xdf,0x51,0xef,0xf7,0x39,0x76,0xf8,
-0xfc,0x8e,0x1d,0xfe,0x80,0x63,0x47,0x00,0x56,0xbf,0x53,0x0a,0xb8,0xed,0xdc,0x19,
-0xc0,0x7d,0xe7,0x4e,0x7f,0xd0,0xb9,0x33,0x08,0xb7,0x61,0x55,0xf6,0x1b,0x82,0x10,
-0x23,0xce,0x86,0x91,0xa0,0x0b,0xd6,0xc6,0x91,0x11,0x97,0xbc,0x2f,0xad,0x23,0xae,
-0x46,0x8c,0x51,0x57,0xe3,0x28,0xac,0x01,0x67,0x63,0xc0,0x63,0xdd,0xe1,0x31,0x5f,
-0xa9,0x35,0x9f,0x3d,0x53,0x7e,0xf6,0xe0,0xfe,0xdc,0x83,0xf0,0x7e,0x80,0x7f,0xd8,
-0xcb,0x9c,0xbf,0xa0,0x7e,0xee,0xb3,0x29,0x7a,0xaf,0xdc,0x2b,0x95,0xfb,0xa5,0x92,
-0x96,0x3b,0xf1,0x71,0xc0,0xf2,0xe6,0xb9,0x39,0x4f,0xf3,0xdc,0xbc,0xa7,0x19,0xfb,
-0xd7,0xf9,0x3e,0xea,0xc9,0x34,0x3f,0xe4,0xc7,0x7d,0xa4,0x25,0xc3,0x56,0x87,0xb9,
-0xde,0x91,0x9e,0x6a,0x48,0x57,0xe9,0xa2,0x85,0x3b,0xbf,0x45,0x2e,0xd2,0x5f,0x2d,
-0x9c,0x4f,0xe3,0xe3,0xa3,0xe3,0xdb,0x77,0xe5,0xb6,0x3b,0xbb,0x9b,0x9d,0x34,0x67,
-0x4e,0x1c,0x9c,0x30,0x7c,0xdf,0xbc,0x0a,0xcf,0x65,0x4c,0x67,0xf3,0xe7,0xfc,0xf6,
-0x28,0x9b,0x47,0x57,0xe3,0x38,0xf4,0xae,0xb3,0x3e,0x76,0x36,0xbb,0x8e,0xc7,0xd0,
-0x3b,0xf5,0x75,0xa5,0xbf,0x7d,0x84,0xf0,0x5b,0xf4,0x4a,0x85,0x7e,0xba,0x87,0xbe,
-0xdd,0x0f,0xcf,0x1c,0x2b,0x3d,0x93,0xb5,0xd2,0x98,0x05,0x33,0xf7,0xda,0x00,0x4f,
-0x1a,0x36,0xbb,0x07,0xfe,0xef,0x0c,0xcb,0x79,0xcf,0xbf,0x80,0xdf,0xac,0x16,0x21,
-0xce,0xb1,0x8b,0xb9,0x5d,0x11,0xe7,0x7e,0x29,0xc6,0xe9,0xfd,0x1f,0xdd,0xdc,0x73,
-0x18,0x8e,0xa6,0x5d,0x21,0xc4,0xc7,0x0e,0x87,0xe5,0xec,0xf7,0xa8,0x8e,0x6b,0x7e,
-0x26,0xe2,0x6b,0xb8,0xdc,0x82,0x1e,0xc7,0xd6,0xfe,0x1e,0xf1,0xf1,0x19,0x4e,0xeb,
-0xde,0x27,0xcc,0xfb,0xa2,0xb7,0xaf,0x7a,0x2f,0x18,0x26,0x68,0xf4,0x6a,0xc2,0xf6,
-0x47,0xc8,0xd7,0xb5,0xbc,0x1f,0xee,0x6f,0x31,0x3f,0x90,0x1f,0x4b,0x8c,0x99,0xb4,
-0x64,0x0c,0x66,0xae,0x29,0x73,0x95,0xf2,0xee,0xa0,0xe5,0x0e,0x3e,0xa9,0x80,0xe5,
-0x7c,0xed,0x32,0x76,0x43,0x0d,0x9d,0xf9,0xb1,0xc0,0xda,0xd3,0x99,0xd8,0xd3,0xdd,
-0x95,0xd0,0x2d,0x72,0xf4,0x0b,0x5f,0x27,0x5c,0xa8,0x32,0x45,0x57,0x85,0xf4,0xba,
-0xe9,0xd5,0x06,0x22,0x95,0xe7,0x2c,0xe2,0xb3,0xde,0xff,0x5d,0xec,0x73,0x10,0xe2,
-0x91,0x1a,0xa5,0xae,0x9f,0xb3,0xb5,0xb2,0x2c,0xb6,0x12,0xf9,0x39,0xd4,0xcf,0xaf,
-0xad,0x51,0xea,0xe6,0xd7,0xa8,0xc7,0x9d,0x6a,0xe9,0xd2,0xbe,0x84,0xe5,0x80,0xeb,
-0xb4,0x66,0x59,0xc9,0x37,0x15,0x3c,0x58,0x00,0xd3,0xd7,0x93,0x3f,0xaa,0xc4,0xd3,
-0x31,0xe7,0x2e,0x6b,0xc4,0xa1,0xde,0x6b,0x0f,0xf3,0x63,0x01,0x3c,0x8f,0x4e,0x0b,
-0x77,0x4d,0xa6,0x77,0x8d,0xc3,0xf2,0x2a,0xf0,0xbc,0xf3,0x73,0xe3,0xf2,0xcf,0x9e,
-0x59,0x73,0xd6,0x6e,0x7e,0xd5,0x8e,0x1a,0xee,0x50,0x37,0xef,0x05,0x7f,0x16,0x58,
-0x0b,0xd0,0xfb,0x9c,0x7a,0xe0,0x36,0xb9,0xc5,0xfa,0x39,0xe5,0xdb,0x37,0x63,0x00,
-0x9e,0xe3,0x2a,0xe3,0x39,0x8b,0x50,0x7e,0x2e,0xe0,0xb9,0xb5,0x64,0x10,0xf2,0xeb,
-0xbf,0xff,0x3c,0xf7,0xf7,0xab,0x56,0xc5,0xaf,0x82,0xcf,0x5e,0x6c,0x6c,0x54,0x6c,
-0xc9,0x96,0x57,0x4a,0x0e,0xfd,0x73,0xe6,0xa1,0x23,0x1f,0xac,0x3f,0x72,0xe4,0x83,
-0xec,0x23,0x47,0x3f,0x5c,0x7f,0xf4,0xc8,0x87,0xeb,0x8f,0x1c,0x3d,0xbc,0xfe,0xe8,
-0xd1,0x0f,0xb3,0x8f,0x1e,0xfb,0x30,0xfb,0x18,0xad,0x39,0xc7,0x68,0x3f,0xe7,0xe8,
-0xb1,0xc3,0xb0,0x9f,0x7b,0xec,0xf8,0xe1,0x9c,0xe3,0x47,0x0f,0xc3,0xed,0x5c,0x3a,
-0x2e,0x1d,0x83,0x7d,0x5c,0x3f,0xca,0xa3,0xfd,0xc3,0x79,0x18,0xc7,0x0f,0xe7,0x1d,
-0xff,0xe8,0xfd,0xdc,0x8f,0x0e,0xbd,0x9d,0x75,0x68,0xcf,0xae,0x8c,0x3d,0x95,0x15,
-0xc9,0x95,0x19,0xe9,0xc6,0x8c,0xe7,0xce,0xa4,0x2d,0xb2,0x15,0x14,0xa4,0x15,0xfc,
-0xf0,0x5d,0xc5,0x0f,0x8c,0x9f,0x33,0x3c,0x07,0x6c,0x07,0x9e,0x0e,0xb8,0x4e,0x78,
-0x5e,0x37,0xca,0xeb,0xe8,0xee,0xba,0x11,0xe0,0xe4,0xf7,0x1d,0x95,0xf7,0xa7,0x1c,
-0x95,0x53,0xe8,0x97,0x0a,0x58,0x3e,0x50,0x7b,0x07,0x7d,0x59,0xe4,0xb9,0x35,0xf2,
-0x4c,0xdd,0x89,0x5c,0xfd,0xe2,0x57,0x15,0x17,0xdf,0xf9,0x97,0xfc,0x77,0xde,0xda,
-0x9f,0xf3,0xd6,0xc1,0xfd,0x39,0x07,0x21,0x3a,0xde,0xcc,0xe9,0x38,0xf8,0xa6,0xb4,
-0x8f,0x91,0x7b,0xf0,0xad,0x37,0xa5,0x9f,0xc1,0xbe,0x84,0xab,0x07,0x0f,0xe4,0xe2,
-0x31,0x8a,0x1c,0x61,0x3f,0x4f,0xb3,0x2f,0xc5,0x81,0x3c,0xe9,0xb1,0x72,0x3b,0x3a,
-0x0e,0xe4,0x75,0xc0,0xed,0x8e,0x37,0xf3,0x94,0x7d,0x69,0xed,0x78,0x33,0xbf,0x83,
-0xad,0x6f,0x1f,0xc8,0x7f,0xbb,0xe3,0x40,0x7e,0xc7,0x5b,0xfb,0xf3,0xde,0xfa,0xcd,
-0x9e,0xec,0xdf,0xb4,0x36,0xac,0x6e,0x35,0x99,0x96,0x9b,0x56,0xae,0x4c,0x5c,0x19,
-0x23,0x6d,0x2f,0xfb,0x3e,0xc2,0xc6,0xe7,0xd5,0x10,0xc7,0xdb,0x70,0xce,0x1c,0xf0,
-0x1b,0xfb,0xe2,0xb0,0xaf,0x9d,0x70,0x1c,0x7a,0xdd,0x01,0xcb,0xe7,0x3d,0x8d,0xf3,
-0xa0,0xed,0x4a,0xd1,0xf4,0x10,0xf5,0xe1,0x40,0x57,0x46,0xc2,0x73,0xac,0xa1,0x43,
-0xbe,0x9d,0x79,0x9f,0x07,0xe4,0xf0,0xb7,0x3f,0xb0,0x9b,0x77,0xd8,0x97,0xa7,0x1a,
-0x96,0x8b,0xbd,0x5b,0x21,0x39,0x37,0x19,0xaf,0xc4,0xf3,0x45,0x38,0xbc,0x80,0xde,
-0x7d,0x53,0xe9,0x6a,0xd3,0xb5,0xcb,0x3b,0xae,0x81,0xcf,0x0a,0xe1,0xf7,0x3e,0xec,
-0x81,0xe3,0x7a,0x70,0xc1,0x7d,0x1c,0xd7,0x45,0x1d,0x19,0x05,0xbf,0xb5,0xfb,0x22,
-0x57,0x17,0xf1,0x9d,0xcd,0xa7,0x81,0xde,0xcc,0x3e,0xd4,0x78,0x25,0xdd,0x57,0xe6,
-0xaf,0xb6,0x1b,0xb5,0xe4,0x9e,0x06,0xda,0x9e,0x3e,0xf5,0xb7,0x3d,0x5d,0xf0,0xef,
-0x5a,0x78,0xec,0xdd,0xf5,0xf8,0xf3,0xe3,0xc5,0x9f,0xe7,0x67,0x1a,0xf3,0xd3,0x93,
-0x22,0xd2,0xc1,0x57,0x0e,0xb4,0xf1,0xc0,0xdf,0x17,0x70,0x9c,0x63,0x38,0xf8,0xc5,
-0x0a,0xf8,0xcd,0x6b,0xdf,0x3a,0x7e,0x33,0xba,0xfc,0xf5,0x67,0x6c,0x2a,0xec,0xd1,
-0xe2,0xf1,0x62,0x3c,0x2b,0x5c,0x2e,0x39,0x4a,0xcd,0x3d,0xc3,0xf2,0x3b,0x9d,0x1c,
-0xba,0xf8,0x3c,0x54,0xcf,0x51,0x78,0x7d,0x22,0xd7,0xe7,0xf8,0xab,0x79,0xce,0x5a,
-0x6e,0xbf,0x18,0xce,0x8b,0xcf,0x41,0xf7,0x77,0x6b,0xf3,0x0d,0x7a,0xd7,0x1f,0x61,
-0x1e,0x2b,0x24,0x4f,0xa1,0xb9,0x36,0xd1,0xe5,0xf3,0x9a,0x39,0xf4,0xf4,0x15,0x91,
-0xe9,0x5c,0x1f,0xae,0x93,0xf1,0x72,0x83,0x80,0xe1,0x86,0x6e,0xe6,0xcb,0xc2,0xf0,
-0xbc,0xbb,0xd3,0xd8,0x0d,0x9e,0xa9,0x3d,0x5d,0x10,0x46,0x8a,0xce,0xa5,0x14,0x5d,
-0x10,0x09,0x3d,0x80,0xe9,0x3d,0x5d,0x89,0x3d,0x8c,0xa7,0x43,0x7f,0x3b,0xe0,0xf9,
-0x62,0xb3,0x8b,0x21,0x5e,0xe5,0x62,0xad,0x20,0x4c,0x6d,0x5c,0x4f,0x8f,0x59,0xbc,
-0x0e,0xe0,0xd7,0x32,0x1a,0x6c,0x17,0x6b,0xe8,0xc0,0xcf,0xa1,0x1f,0x0e,0xea,0xe6,
-0x94,0x6f,0x5f,0xc3,0xb5,0xe1,0xd8,0xbc,0x1a,0xf4,0xb7,0x8b,0xdc,0x9c,0xfc,0xcf,
-0xb3,0xa4,0x9f,0xd3,0x4a,0x3e,0xa9,0x84,0xeb,0x8a,0x7e,0x7b,0x8e,0x9d,0x05,0xe0,
-0x3a,0xe8,0xbd,0x32,0x3c,0x0f,0xc9,0xfd,0x2d,0xa2,0x9f,0xc4,0xde,0x07,0x43,0x4c,
-0xa4,0xe1,0xb5,0xaa,0xa4,0xd7,0xbe,0xf9,0xef,0xec,0x6f,0x9c,0x3d,0xa0,0x25,0xb3,
-0xd1,0x85,0x58,0x2e,0xe1,0x3a,0xe8,0xc2,0x81,0xf7,0xf9,0xd0,0x8d,0x8d,0x43,0x43,
-0xbd,0x1b,0xb9,0x07,0xba,0xbb,0x8f,0xfa,0xdb,0x43,0x6a,0xe7,0x7d,0x72,0xed,0xdc,
-0xa2,0xa9,0x9d,0x5b,0x58,0xed,0xbc,0x18,0x71,0x9c,0x30,0xbd,0x14,0xa3,0xdf,0x5c,
-0xdc,0xff,0xc1,0xbb,0x99,0x1f,0x18,0xe3,0x97,0x18,0xe1,0x23,0x16,0xbd,0x24,0x32,
-0x3a,0x31,0x31,0x26,0x31,0x25,0x25,0x36,0x05,0x66,0xc4,0x52,0x52,0x0c,0x29,0x29,
-0xc9,0x52,0x48,0xb7,0x95,0x80,0x63,0xb4,0x4f,0xf7,0x89,0x55,0xfd,0x3c,0xe4,0x18,
-0xde,0x37,0x2e,0x25,0x39,0x05,0x8e,0xc3,0x1a,0x87,0x3f,0x5f,0x96,0x1c,0xbb,0x2c,
-0x21,0xc1,0x90,0x00,0x35,0xf2,0x5f,0x23,0x2f,0x56,0x50,0x90,0xca,0xf1,0x7c,0xc4,
-0xb5,0x7d,0x04,0x6a,0xe8,0xd8,0xcf,0xee,0xa6,0xbc,0xfb,0x98,0x1b,0x30,0xbd,0x66,
-0x54,0xec,0x87,0x83,0xfd,0xbb,0xce,0xea,0xbb,0x33,0xb6,0xb2,0x99,0x69,0xbb,0x69,
-0x1a,0x72,0xee,0x30,0xb7,0x76,0x77,0x00,0x6a,0xe6,0x0a,0x3f,0x07,0x3c,0x87,0x75,
-0x74,0x60,0xc7,0xe8,0xc9,0xff,0x28,0x3a,0x09,0x98,0x19,0x17,0x17,0x13,0x07,0x61,
-0x8c,0x8f,0x31,0xc6,0xc7,0xc7,0xc4,0x4b,0x27,0xdf,0x78,0x3c,0x16,0x2b,0x87,0xb4,
-0x1f,0x1b,0x17,0x13,0xcb,0xee,0x27,0x46,0x6c,0xac,0x74,0x3c,0xd6,0x20,0xed,0x1b,
-0xa4,0x7d,0x03,0xee,0xb3,0x15,0x8e,0xf1,0xff,0x0f,0xc7,0xe0,0x36,0xfe,0x3f,0x03,
-0x0f,0xe5,0xb8,0x21,0xce,0x10,0x1b,0x23,0xd1,0xf0,0xe8,0x98,0x9f,0x53,0x1f,0x7f,
-0xde,0x96,0x91,0x9e,0x9a,0x11,0xb0,0x37,0x05,0x98,0x07,0x0b,0xf6,0xb6,0xa3,0xaf,
-0x5a,0x33,0xcd,0x9a,0x7b,0xc9,0x2b,0x15,0x72,0xec,0xe0,0xcf,0xc2,0xf0,0x1b,0xf0,
-0x1c,0xb8,0x38,0xe6,0xde,0x51,0x1f,0x4e,0xf6,0x3d,0xf7,0x2b,0xbe,0xe7,0x0c,0xcb,
-0x1f,0x04,0xda,0x1f,0x20,0x3f,0x4f,0x33,0xa4,0xeb,0xe5,0x8c,0xb5,0xf5,0xf3,0xb0,
-0x3c,0x41,0xf8,0x3e,0xad,0xcd,0x4c,0x59,0x7b,0xe9,0xcf,0xdb,0x2f,0xc1,0xcc,0x1c,
-0xc3,0x72,0xf2,0x59,0x61,0x9a,0x6f,0x7b,0x1f,0x82,0xcf,0x39,0x62,0x7a,0x10,0x72,
-0xf0,0xb2,0xaf,0x1a,0x9b,0x3f,0xe3,0x3d,0xec,0x32,0xff,0x56,0xf9,0xa8,0xd1,0x8c,
-0xba,0xa2,0x2f,0x43,0x3a,0xaf,0x4f,0xfc,0x6d,0x4f,0x16,0x7c,0xad,0x0b,0x0b,0xbe,
-0x96,0x85,0x9f,0x7c,0x2d,0x3f,0x41,0xc0,0xfe,0x82,0xaf,0x79,0x61,0xc1,0xdf,0x2c,
-0x1f,0x6b,0xfd,0xe9,0xa9,0x7f,0xd7,0xd3,0xc7,0xde,0xd6,0xc7,0x9f,0x1d,0x2f,0xfe,
-0x2c,0x67,0xb5,0x31,0x07,0x35,0xf1,0xe2,0x23,0x96,0x71,0xfd,0x1c,0x1d,0xed,0x9c,
-0x90,0x9e,0x35,0x2d,0x6e,0xe9,0x6c,0x7a,0x18,0x29,0xde,0xd6,0xcb,0x0d,0x87,0xf0,
-0x0d,0xa1,0x1f,0x4b,0x3b,0x3f,0xbd,0x68,0x68,0xf4,0xc0,0x16,0xc3,0x74,0xd5,0x73,
-0x8d,0x10,0x30,0x4f,0xc4,0xed,0x08,0x0d,0x86,0x0a,0x98,0x1b,0xc2,0xcd,0x85,0xc7,
-0x50,0xbd,0x5e,0x0d,0x96,0xea,0xe6,0xc6,0xc5,0xc7,0x0e,0x57,0x2f,0xd6,0x86,0x16,
-0xbf,0xf5,0x1e,0x4f,0xef,0xf7,0xea,0x5c,0x1f,0xf0,0xd7,0x1b,0xa9,0x7e,0x7e,0xf0,
-0x3e,0x81,0xde,0xeb,0xa9,0x93,0xd1,0xa7,0x54,0xf3,0x6a,0x42,0xbe,0x5d,0x89,0x38,
-0x73,0xf7,0xd5,0xb8,0x6e,0xf0,0x40,0xef,0xb9,0x1a,0x8f,0x5e,0xe8,0xe8,0x83,0x2e,
-0x61,0x3b,0x86,0xcc,0xcf,0x09,0xd3,0x13,0x30,0x78,0xbe,0xbd,0x33,0x09,0xf1,0x1c,
-0xf4,0x64,0xb4,0xf5,0x6e,0x3e,0x37,0x2f,0x5c,0x67,0xab,0xbc,0x0d,0xf5,0x3c,0x85,
-0x74,0xfc,0x85,0xc4,0x1c,0x1c,0xc7,0x6a,0xc1,0xfb,0x5c,0x9c,0xcf,0xd7,0xae,0x8a,
-0x5f,0xea,0x1a,0x0b,0xe7,0xe7,0xd7,0x32,0x79,0xbe,0xdd,0x62,0x5e,0x67,0x81,0x40,
-0x5e,0x6e,0xa6,0xbc,0x3b,0xea,0xbe,0x02,0x8e,0x5f,0x97,0x6b,0xe8,0xd7,0xd9,0xdc,
-0xf9,0x7a,0x59,0x5b,0x86,0x66,0xd6,0x70,0x76,0x4d,0xc6,0x73,0x98,0x57,0xc3,0x7e,
-0x38,0x1d,0xbe,0xc0,0xbf,0x27,0x3a,0x1e,0xb8,0x62,0x2c,0x35,0x46,0x2d,0x7d,0xfb,
-0xe0,0xf2,0xb7,0xcd,0x57,0x36,0x98,0x71,0x26,0x1d,0x74,0x65,0xa0,0xc7,0xbd,0x97,
-0x61,0xfa,0x46,0xd4,0x85,0xbb,0x75,0xe3,0xd5,0x5b,0x88,0xed,0x37,0x0a,0x86,0x60,
-0xf6,0x1c,0xfc,0x52,0xd1,0x3b,0x15,0x31,0x5d,0xae,0xa3,0x5b,0x84,0x9c,0xbb,0x85,
-0xd5,0xd1,0xc5,0xfa,0xb9,0xec,0x81,0x6e,0x2d,0x25,0x8e,0x6e,0x2d,0x19,0xe8,0xba,
-0x5c,0xd8,0xd5,0xd4,0x94,0xd6,0xf4,0x4b,0xb8,0xf1,0xff,0x87,0xad,0x60,0x13,0xe0,
-0xb9,0x09,0xf1,0x1c,0xe6,0xcf,0x01,0xd3,0xb1,0x8e,0x0e,0xbd,0x71,0xae,0xea,0x71,
-0x08,0xea,0x71,0xaf,0xe1,0x9a,0xaf,0xd0,0xdb,0x3e,0xe1,0x7c,0x6d,0x62,0xce,0x56,
-0x32,0x37,0xeb,0x28,0x9f,0x05,0x3c,0x07,0xcf,0xd4,0x09,0x77,0xf5,0x04,0xe9,0xca,
-0xc8,0x3a,0x71,0x50,0x37,0x97,0xd6,0xd1,0xc1,0x1d,0xa3,0x1f,0x1f,0x29,0xfc,0x18,
-0xea,0xb3,0x98,0x3b,0x13,0xce,0x57,0xaa,0x6b,0x6f,0x79,0x0b,0x7b,0x6e,0x5d,0x64,
-0xfb,0x35,0xae,0x6d,0x7e,0xe9,0x86,0xf5,0x73,0x7b,0x93,0x7f,0xda,0xdb,0x3a,0x3d,
-0xeb,0x69,0x46,0x4f,0x35,0xf4,0x55,0xf3,0x00,0x37,0x87,0x68,0x99,0x9d,0xf3,0x34,
-0xcd,0x51,0x34,0x23,0xa6,0x23,0xb6,0x23,0x67,0x87,0xde,0x38,0xa5,0xd7,0x1d,0x34,
-0x5f,0x21,0xb7,0x8e,0x3e,0x2d,0xfe,0x36,0x0a,0xc4,0xf9,0x36,0x89,0x9f,0xd7,0xdb,
-0x21,0xdf,0xae,0x9d,0xa1,0x52,0x5d,0xcb,0xeb,0xd4,0x19,0x43,0xfa,0x63,0xa5,0xfb,
-0xc2,0x35,0xd0,0x67,0xbf,0x33,0x7d,0x06,0xfd,0x6f,0x84,0xd7,0xfb,0x94,0xfe,0x37,
-0x6d,0x04,0xd8,0xf1,0xbd,0xa4,0xeb,0x2a,0xe3,0xba,0x7a,0x16,0x7d,0x0f,0x79,0xb0,
-0xa0,0xce,0x2b,0x70,0xed,0x5d,0x4f,0x9e,0xf8,0x77,0x3d,0x79,0xea,0x6f,0x7d,0x0a,
-0xd8,0x0c,0xb1,0xe0,0x6d,0x59,0x78,0xe6,0x69,0x7c,0xf6,0xf7,0xe1,0x1d,0x7f,0x7f,
-0x36,0xbc,0xf3,0xd9,0x33,0xcf,0xce,0x67,0x3f,0x79,0x1a,0x25,0xfc,0x6e,0xfe,0x89,
-0xf0,0xbc,0x75,0x01,0xef,0x1b,0xd8,0x8d,0x31,0xef,0xdb,0x3d,0x7f,0xea,0x68,0xd9,
-0xa9,0x8c,0xe5,0xc6,0x0c,0xd6,0xc3,0x2f,0xbe,0x6e,0x3d,0x0f,0x35,0xf6,0x99,0x78,
-0xee,0xe7,0x42,0x8b,0x47,0x3a,0x39,0x6e,0x3d,0x0e,0x24,0x9e,0xa3,0x75,0xcf,0xd5,
-0x3a,0xf9,0x12,0xed,0x39,0x37,0x04,0xd3,0x35,0x79,0x59,0xdd,0x1a,0x49,0x38,0xfc,
-0x8e,0xd4,0xc1,0x3b,0x91,0xbf,0x47,0xaa,0x31,0x94,0xaf,0xc2,0xfd,0x75,0xb1,0x57,
-0x8b,0xd3,0x11,0x3a,0xb7,0x17,0xc3,0xef,0x48,0xfd,0xd9,0xf2,0x70,0xe7,0x7e,0xed,
-0xb5,0x17,0xff,0x9b,0x08,0x8f,0xa1,0x7a,0xce,0x1a,0xee,0xcf,0x7e,0xbe,0xfc,0x7f,
-0xa9,0xbb,0x16,0xe6,0x28,0xae,0x2b,0x3d,0x42,0xe8,0x31,0x12,0x18,0x90,0x78,0xe8,
-0x2d,0x24,0x87,0x58,0x8f,0x91,0x40,0x18,0x07,0xc7,0x3c,0x05,0x48,0xe8,0x89,0x9d,
-0xec,0xa6,0x12,0x67,0x93,0x54,0xa5,0xb6,0x62,0xa0,0x6c,0x1c,0xaf,0x97,0x47,0x6c,
-0x12,0x3b,0xa9,0xb5,0x6b,0x37,0xae,0x72,0x52,0xa9,0x72,0x25,0x59,0xd7,0xda,0x65,
-0x23,0x39,0x33,0x92,0x46,0x23,0x81,0x34,0x1a,0x21,0x69,0x1e,0x1a,0x21,0x83,0x88,
-0x29,0x3b,0x80,0xb0,0x1e,0x26,0xbf,0x65,0xfb,0x3b,0xa7,0xef,0xed,0xdb,0x77,0xee,
-0x08,0xd9,0x9b,0x38,0xde,0xae,0xba,0xd5,0x3d,0xa3,0x61,0x98,0xe9,0xb9,0x7d,0xbf,
-0xfe,0xce,0x39,0xdf,0x77,0xb6,0x78,0xb6,0xfc,0xec,0x7c,0xa6,0xcb,0xef,0x95,0xb5,
-0xe7,0xd9,0x8a,0x5e,0xcd,0xce,0xa1,0xd3,0xe0,0x58,0xbb,0x1c,0xbd,0x79,0x8c,0xe3,
-0x84,0xdf,0x88,0xb7,0xaf,0xeb,0x67,0x3c,0x17,0xdc,0xfc,0xa1,0x7e,0xa1,0x3f,0xdf,
-0xfb,0x98,0x8d,0xe7,0x9a,0xa7,0x4d,0x4a,0x0e,0x4c,0x68,0xe5,0x33,0x15,0xad,0xf8,
-0x5a,0xb7,0x47,0xaa,0xcc,0x0b,0x65,0xba,0xfb,0x21,0xaa,0x9a,0x34,0xf1,0x3a,0xa1,
-0x4d,0x4d,0xd1,0x66,0xd8,0xd7,0xc7,0xde,0x3d,0x1c,0x6f,0x47,0xde,0x7c,0x28,0x50,
-0x36,0x34,0xec,0x67,0x0d,0xfa,0x70,0x5f,0xf9,0xb0,0x13,0x6f,0xaf,0xbc,0xec,0x60,
-0xfa,0x76,0x39,0x98,0xa7,0x57,0x8d,0x88,0x7e,0xa9,0xe1,0x7e,0xe4,0xd1,0xab,0x28,
-0x8f,0x4e,0xa3,0xbf,0x6a,0x2c,0xd2,0x5f,0x1d,0x01,0xa6,0x4b,0x7e,0xee,0x49,0xfd,
-0x3d,0xd3,0xe5,0x21,0x52,0x7c,0x6a,0xad,0x73,0xb3,0xb9,0x60,0xed,0xe6,0x5f,0xbd,
-0x54,0xf6,0xab,0x91,0xfe,0xda,0x11,0xd6,0x9c,0xd7,0x8d,0x91,0xa7,0x4c,0x08,0xda,
-0x35,0x8e,0xbb,0x0b,0x2c,0x9f,0x0a,0xd5,0x4d,0xc5,0x82,0x75,0xb1,0xe8,0x60,0x6d,
-0x14,0x5e,0xaf,0xd1,0xc1,0x3a,0xd2,0x9d,0xa3,0x0f,0x8b,0xc8,0x9d,0xeb,0xda,0x73,
-0x11,0x6f,0x27,0x9e,0x7e,0xd9,0x89,0xb9,0xa3,0xb7,0xda,0xf8,0x50,0xd3,0xf8,0x9b,
-0xff,0x59,0xf3,0xe6,0xd7,0xbf,0xbe,0x7e,0x55,0x3a,0xef,0xaf,0xda,0x26,0xe6,0x7f,
-0x6d,0x6d,0x61,0xad,0xff,0x7f,0xbe,0xe1,0xbf,0x36,0x0e,0x3c,0xdf,0xff,0x21,0x8d,
-0x71,0x68,0xce,0x19,0xcf,0x6f,0x8e,0x7d,0xf3,0x26,0x6a,0xe2,0xc8,0x27,0x6e,0xdc,
-0xe1,0xe7,0xb7,0xc2,0xdf,0xbc,0x75,0x77,0xa4,0xe9,0xee,0x9d,0xd1,0x3d,0x77,0xa0,
-0x35,0x47,0x3d,0x3b,0x06,0xf9,0xca,0x4c,0x3a,0xfc,0x1c,0xb9,0xf3,0xeb,0x57,0x8f,
-0x5c,0x17,0x78,0x8e,0xdf,0x52,0xfc,0x7e,0xfa,0x3d,0xb9,0xfa,0xd9,0xf4,0xf5,0xe8,
-0xf3,0x7e,0x39,0xe3,0xf1,0xdf,0x79,0x83,0xdf,0x2b,0xf7,0x4b,0xed,0xfc,0x84,0xf2,
-0xe4,0xd0,0x9c,0x53,0x7f,0x35,0xbb,0xb7,0x1a,0xfa,0xa0,0x13,0xc6,0xb7,0x51,0xef,
-0x54,0xa7,0x4f,0x6a,0xa7,0x8d,0xe1,0x1d,0x77,0x39,0x47,0xde,0x3e,0x2f,0xf6,0xdc,
-0x53,0xcd,0xce,0x9f,0x27,0xbb,0x28,0xfe,0x0e,0x7e,0x8e,0x78,0xbb,0x8b,0x03,0xa8,
-0x1e,0x1b,0x6b,0x0c,0xde,0x51,0xba,0x2f,0x0a,0xea,0x51,0xd6,0x66,0x64,0x7f,0xf7,
-0x3b,0xb5,0xdf,0xfd,0x68,0xaa,0xeb,0x23,0xe6,0xdd,0x02,0xaf,0xbb,0x2d,0xec,0xc6,
-0x38,0xf1,0x69,0x4a,0xfd,0x3a,0xf4,0x68,0xb3,0xd6,0x73,0xf0,0x61,0x4f,0x5a,0x98,
-0x9d,0x64,0xbc,0x5e,0x4a,0xb6,0x2d,0x81,0x5f,0x2f,0x4f,0x1f,0xb7,0xf0,0xba,0xf5,
-0x33,0x8c,0xfb,0x89,0xd6,0xfb,0xf7,0x13,0x16,0x46,0xe3,0x31,0x70,0x9a,0xf8,0x37,
-0x73,0xf0,0xfb,0x09,0x0b,0xbf,0x13,0x8c,0xe1,0xe0,0xe2,0x02,0xbf,0x39,0xe6,0x7e,
-0x62,0x49,0xf4,0x59,0x03,0xe7,0xa7,0xfe,0x6a,0xcf,0x3d,0x76,0xae,0x60,0x53,0x7e,
-0x41,0x8a,0xfe,0x2e,0x0d,0x77,0xd3,0xb1,0x5c,0x7d,0xbd,0x6b,0x5d,0xd1,0xd6,0x14,
-0xb9,0xd6,0x66,0xba,0xd7,0x5a,0x75,0xbd,0x75,0x69,0xda,0xd6,0x3a,0x9a,0x36,0x63,
-0xbd,0xb1,0xc1,0xcb,0x4c,0xf5,0x1d,0x37,0xd5,0x2a,0xaa,0xeb,0x60,0x0a,0xa7,0xf6,
-0x68,0x18,0x2e,0xbe,0x73,0x1a,0x4e,0x9b,0xc2,0xcf,0x0d,0x1c,0xdb,0x88,0xd5,0x69,
-0xf0,0x5d,0x78,0xb6,0xca,0xcf,0xe9,0x49,0xcd,0xef,0x8a,0xe7,0x57,0xca,0x05,0x3f,
-0x68,0xac,0xf8,0xba,0x34,0x3a,0x0d,0xf5,0xdf,0x12,0x3f,0x3f,0xb7,0xe6,0xa5,0x0f,
-0xde,0xcf,0xfa,0xc0,0x7f,0x29,0xdb,0xef,0xef,0xc9,0x62,0x2c,0xbf,0xe4,0xd4,0xb7,
-0xb3,0xe7,0xab,0xe2,0x27,0x63,0x6b,0xd0,0x65,0x3d,0x5c,0x2f,0xf7,0x58,0x03,0x37,
-0x07,0x9e,0xf7,0xf7,0xac,0xeb,0x87,0xe7,0xab,0x5a,0x0f,0x07,0x7f,0x38,0xca,0x9f,
-0x1b,0x34,0x73,0xfa,0xef,0xed,0xba,0x1f,0x54,0xf3,0xde,0xda,0x5c,0x13,0xfa,0x0c,
-0xa1,0x43,0xcd,0xcb,0x52,0x34,0x19,0xd9,0x8e,0x36,0x43,0x0e,0x5b,0xb7,0x21,0x47,
-0x0e,0xd7,0x8c,0x1e,0xda,0x97,0x7b,0x28,0xf0,0x4e,0x49,0x80,0xf4,0x6a,0x01,0x77,
-0xcf,0x54,0xa1,0x3f,0x67,0xaf,0xb8,0x4a,0xa9,0x5b,0x43,0xfe,0x1c,0x58,0x8e,0xc1,
-0xd8,0x5e,0x65,0xf7,0x57,0xab,0xba,0x82,0x7a,0xb8,0x70,0x5f,0x75,0x38,0xdc,0x5f,
-0x1d,0x66,0x3c,0xaf,0x8a,0x84,0xfb,0x1f,0x0e,0x4b,0x7e,0x6e,0x88,0x0d,0xa9,0xbf,
-0xbd,0xd1,0xb7,0x49,0xb9,0xf6,0x70,0x1d,0x3d,0xbc,0xdd,0xfb,0xf0,0xef,0x7f,0x53,
-0xfd,0x7b,0xee,0x9d,0x5a,0x47,0xbe,0xaf,0xc0,0x73,0x1c,0x5f,0x0d,0xd5,0x91,0x37,
-0x1c,0x62,0xee,0xe0,0xe6,0xec,0xe5,0x5e,0x37,0xc5,0x98,0x0e,0xef,0xd7,0xda,0x04,
-0x7a,0xae,0xc5,0x42,0xf5,0x31,0xe0,0x3a,0x3c,0x5f,0x65,0x4d,0x9c,0xf4,0x7b,0x75,
-0xe7,0xcf,0x39,0xe6,0xce,0x98,0x1e,0x0e,0x36,0x85,0xcf,0xff,0x5b,0xd5,0xf9,0x2d,
-0x5b,0x72,0xb6,0x7c,0x15,0xf8,0xe1,0x17,0xd9,0x38,0xde,0xfe,0xd8,0x9f,0x66,0x22,
-0x07,0x67,0xa8,0xb6,0x7d,0x6c,0xdf,0x75,0x60,0xfa,0xec,0x55,0xc6,0xf3,0x5b,0xe1,
-0xbd,0xb7,0x80,0xe9,0xe8,0xa5,0x26,0xfd,0x64,0xc6,0xd1,0xf7,0x7c,0xff,0xdc,0xad,
-0xf0,0xe3,0xb7,0x3e,0x09,0xef,0xfd,0xe4,0x66,0xe4,0xc0,0x4d,0xf4,0x3e,0x07,0x0f,
-0x77,0xfa,0xb1,0x1c,0x91,0x39,0x74,0xc4,0xdb,0x5f,0x3c,0xd3,0xf0,0x62,0x61,0xa1,
-0xb7,0x50,0xcc,0x5f,0xb1,0x56,0xa9,0x9f,0x45,0xe7,0x1e,0xab,0xdd,0xd4,0x75,0xed,
-0x6f,0x79,0x6e,0x3e,0xef,0x46,0xfd,0xd5,0x46,0x5a,0x92,0xd2,0xb7,0x3d,0xa9,0xfb,
-0xbd,0xda,0xfd,0xce,0x13,0xec,0x15,0x07,0x5d,0x1a,0x72,0xe9,0x77,0x92,0x1d,0xb6,
-0xf6,0x5c,0xd4,0xbb,0x23,0xee,0x6e,0x6b,0xd0,0x09,0xe3,0x1d,0x2c,0xa7,0xfc,0x79,
-0x7f,0xf3,0xe8,0xd6,0xc2,0xec,0xad,0x3a,0xde,0xc8,0xbe,0xa8,0x8a,0x47,0x9c,0xae,
-0xbb,0x16,0x7a,0xae,0xbc,0x9c,0x35,0x79,0x47,0x0f,0x6d,0x3f,0x3a,0x3d,0x7c,0x7c,
-0x1a,0x9a,0x34,0x31,0x80,0xe1,0x0e,0x27,0xe7,0x38,0xbb,0xc0,0x79,0xf2,0x88,0x99,
-0xe9,0x5a,0x58,0x9a,0x6e,0x5f,0x22,0xbc,0x8e,0x1f,0xbd,0x7f,0x3f,0x7e,0xcc,0x1e,
-0x2d,0xf7,0xf9,0xb9,0x56,0x7a,0xfc,0xd7,0xf8,0xb1,0xbf,0x62,0x2f,0xb0,0x5c,0xf0,
-0x73,0xc4,0xd9,0x91,0x1b,0x87,0x87,0x1c,0xb0,0xdb,0xf1,0x8f,0x73,0xfa,0xaa,0x71,
-0xbd,0x9c,0xe3,0x1f,0x47,0xfa,0x73,0xdb,0x4f,0x46,0xfd,0x9d,0x75,0xfc,0xd1,0xe3,
-0x9d,0x92,0x37,0x2b,0x3a,0x74,0x55,0xcf,0xa6,0x0e,0xd7,0x7a,0xa8,0xe8,0xdb,0x44,
-0x2f,0x69,0xd9,0x7b,0xd6,0xa0,0x51,0x57,0xfb,0xd0,0xca,0x38,0x6a,0xa6,0x21,0x7f,
-0xaa,0xe5,0xf0,0x53,0x72,0x8d,0x3a,0x5f,0xd5,0xf1,0x58,0xbb,0x36,0x52,0xe2,0x0f,
-0xea,0x3d,0x8d,0xce,0xe5,0xd5,0xf7,0x58,0x29,0x86,0xae,0xf3,0xf2,0x74,0x9c,0xdb,
-0xf0,0xb9,0x53,0x38,0x59,0x1a,0x5c,0x76,0xc5,0x22,0x94,0x3c,0x70,0xba,0xf8,0x84,
-0xee,0xa3,0x92,0x2e,0x67,0xa1,0x9e,0x67,0x27,0x7f,0x9e,0xed,0xe8,0xd5,0x08,0xc7,
-0x1d,0x7e,0x4e,0x1c,0xbd,0x97,0xf5,0xe7,0x42,0xaf,0x26,0x7c,0x5f,0xd9,0x17,0x4e,
-0x68,0xd4,0xb8,0xb6,0x9d,0x30,0x5d,0xc1,0x72,0xd6,0xab,0x21,0x7f,0x9e,0xf9,0xb8,
-0x49,0x33,0xa7,0xd7,0xdc,0x9b,0x62,0xea,0x6a,0x2c,0x27,0xc5,0x17,0xc6,0xba,0x5e,
-0x05,0x5e,0x43,0x9f,0x21,0x34,0x1d,0x42,0xbf,0x01,0xaf,0x67,0x93,0xae,0x43,0x8c,
-0x23,0xfb,0x73,0x8f,0xf4,0xbd,0x5b,0xd2,0x37,0xe2,0x2f,0x1d,0xa1,0x11,0x28,0x1b,
-0x19,0x0d,0x94,0x8d,0x3a,0xbd,0xd5,0x44,0x7f,0x35,0xb1,0xaf,0x24,0x8d,0x1a,0xfb,
-0xc8,0x58,0x78,0x6e,0xf7,0x57,0xe3,0xbe,0x6a,0xd5,0x16,0xbe,0x3f,0xec,0xf4,0x57,
-0x1b,0x70,0xf2,0xe8,0xf0,0x7b,0x55,0xf5,0xe7,0xae,0xfc,0x87,0x21,0xf6,0xb5,0x62,
-0xad,0xbe,0xf5,0xdd,0x5b,0x8f,0x6e,0x6c,0x0d,0xf5,0x3c,0x12,0x22,0x0c,0xb7,0xeb,
-0xe1,0xa4,0x6f,0x7b,0x88,0xf3,0xe7,0xf0,0x6f,0xc7,0x40,0x0f,0x16,0xf4,0x3f,0xc7,
-0x98,0x0a,0xd5,0x4f,0xc5,0x07,0xeb,0xe3,0xf1,0x50,0x7d,0x9c,0x7a,0xa4,0x86,0x1a,
-0xa6,0xd0,0x57,0xcd,0x55,0x0f,0x47,0x18,0xbe,0xcb,0xc1,0x72,0xec,0x29,0xee,0xce,
-0x63,0xb0,0xb7,0x71,0xf0,0xe9,0x7f,0x2e,0x7a,0xda,0x9b,0x97,0xe9,0xfd,0x12,0xa1,
-0x23,0xed,0xf6,0x79,0x31,0x4d,0xe6,0xcf,0xed,0x5a,0x38,0xaa,0x69,0xb7,0x06,0x38,
-0xfa,0xdc,0xd8,0xbe,0xb9,0x8f,0x47,0xf7,0x7c,0x0c,0x4c,0xbf,0x11,0x39,0x70,0x43,
-0x6a,0xcf,0x27,0x58,0xb7,0x06,0xcd,0x1a,0xf9,0xc3,0x5d,0x15,0xbd,0x52,0x81,0xe9,
-0xd6,0xde,0xd6,0xa8,0x09,0x9d,0x1a,0xf8,0xf9,0xd9,0xe7,0x7d,0x67,0xb7,0x6d,0xf1,
-0x6e,0x43,0x8c,0x08,0xbf,0x5b,0x0a,0xb7,0x50,0xd6,0x1c,0x57,0x9c,0xd0,0xc4,0xd3,
-0x33,0xb4,0xbd,0xe9,0x6f,0xff,0x80,0x4d,0xea,0xd5,0x52,0x7a,0xab,0x39,0xda,0x73,
-0xe4,0xd6,0x81,0xd7,0xc2,0x67,0x86,0xf9,0x39,0x62,0xec,0xdd,0xc4,0xd3,0x49,0x93,
-0x46,0x7a,0xb5,0xce,0x79,0x8e,0xb3,0x23,0x8f,0xde,0x45,0x79,0x74,0x60,0xfa,0x7c,
-0xb2,0x73,0x7e,0x2c,0x70,0x98,0xfa,0x9f,0x9b,0xf0,0x47,0x60,0x93,0xd0,0x74,0x09,
-0xdf,0x64,0xdc,0xb3,0x4b,0xed,0x75,0x4e,0x86,0xb7,0xa9,0xb1,0xb8,0x29,0xf8,0x4e,
-0x73,0xf0,0x6e,0xf2,0xc4,0x5d,0xe8,0xd2,0x44,0x6e,0x9c,0x71,0x5d,0xc4,0xdc,0x85,
-0xee,0xfc,0x49,0xdb,0x0f,0xae,0x73,0x71,0x79,0xba,0x6d,0xf9,0xb3,0x78,0xcb,0x67,
-0xf7,0x63,0x16,0x86,0x5b,0xfc,0x1b,0x78,0x0d,0xac,0x5e,0x4c,0x76,0x2c,0x72,0x2f,
-0xd4,0xae,0x45,0x8a,0xa9,0xdb,0x31,0x73,0xe0,0x37,0xf5,0x49,0x85,0x6f,0xdc,0xac,
-0xdd,0x53,0xed,0xc3,0x27,0x9d,0x3e,0x6a,0x54,0x1b,0x67,0x7b,0xb5,0x2b,0x9e,0x70,
-0xbc,0x67,0x5f,0x19,0xf4,0x63,0x21,0xfd,0xf9,0x46,0x8b,0x9f,0xaf,0x71,0x6b,0x58,
-0xe5,0xba,0xa7,0x7c,0x6f,0x7d,0xcd,0xa3,0xe1,0x55,0xf6,0xf6,0xb1,0xd4,0xb5,0xd9,
-0xbe,0xd2,0x42,0xcf,0x2f,0xcf,0xa7,0xaa,0x4f,0xcf,0x72,0xc7,0x32,0x55,0x9f,0x99,
-0x74,0x71,0xf4,0x07,0x71,0x48,0x23,0x86,0xae,0x74,0xac,0xe0,0xb0,0x3e,0xf7,0x74,
-0xee,0x9e,0xee,0x58,0xe7,0xfa,0xae,0xe7,0x94,0xf7,0x97,0x9f,0x75,0x05,0x1f,0x56,
-0xf9,0x5d,0xf4,0x9a,0xa7,0x07,0xf8,0x98,0xca,0x73,0x63,0xf2,0x82,0x49,0xe3,0xbd,
-0xab,0x63,0x62,0x5a,0x8c,0xb4,0xf1,0xa1,0x78,0x9b,0xa7,0xf8,0xe5,0x73,0x8e,0x5e,
-0x8d,0x6a,0xe2,0x2e,0xb9,0x6b,0xe2,0x38,0xce,0x6e,0xe7,0xd0,0xed,0xba,0x76,0xa1,
-0x5b,0x43,0xee,0x1c,0x1c,0x9d,0x6a,0xdb,0xc1,0xcb,0x2d,0x4c,0x47,0xdc,0x9d,0x71,
-0x7d,0x7d,0x3f,0x0f,0x5b,0xaf,0xb6,0x67,0xad,0x2b,0x7f,0xae,0xd7,0xaa,0xe9,0xb9,
-0x74,0x93,0x0f,0xa1,0xae,0x39,0xd3,0xef,0xd5,0xc5,0x7d,0xa5,0x98,0xe7,0x98,0xe3,
-0x62,0x3e,0x6f,0xc8,0xf3,0x6c,0x80,0xb6,0x03,0xb5,0x25,0x85,0xeb,0x3c,0x85,0x18,
-0x9b,0xd7,0x79,0x36,0x1f,0x3f,0x98,0x7b,0x7c,0xe0,0x9d,0xe2,0x81,0x51,0x7f,0xc9,
-0x68,0xd8,0x5f,0x1a,0xe6,0x51,0xc6,0x23,0x80,0x7d,0x39,0x1d,0x8f,0xf9,0xcb,0xc7,
-0xc6,0x02,0xe5,0x63,0x11,0x7f,0x79,0x24,0x12,0x28,0x8f,0x38,0x3e,0x71,0xdb,0x5d,
-0x7d,0x58,0x44,0x7f,0x35,0xdd,0x27,0xce,0xa8,0x57,0x5b,0x29,0x16,0xa4,0xdc,0x7f,
-0x9b,0xea,0xf4,0xf3,0x72,0x32,0xf2,0xce,0x3d,0x5f,0x72,0x6e,0x24,0x50,0x33,0x42,
-0xfe,0xaf,0x76,0xac,0x9d,0xe3,0xed,0x75,0x93,0x94,0x4f,0x27,0x7e,0xce,0xf9,0xf3,
-0x89,0x90,0x6f,0x02,0x7d,0xd5,0xe0,0xf1,0xca,0xd8,0xde,0x30,0x89,0xd8,0x7b,0x34,
-0xe4,0x8b,0xc2,0xc7,0x1d,0x3d,0x53,0x27,0x86,0x77,0x4e,0xf0,0xd8,0x35,0xa1,0x6a,
-0xd0,0x1d,0x4c,0x7f,0x54,0x62,0xfa,0x5b,0xbf,0xad,0x7d,0xeb,0x1b,0x7b,0x36,0x7d,
-0xe3,0xf3,0xf8,0xb8,0xfc,0xbd,0xb7,0xd5,0xc6,0xab,0xd5,0x7a,0x38,0xc6,0xf3,0xfd,
-0xd7,0xe7,0xc6,0xbe,0x39,0x87,0x9c,0x39,0x8e,0xd1,0x6f,0x0d,0xbe,0x32,0x73,0x91,
-0x7d,0x73,0xa2,0xce,0xdd,0x19,0xcd,0xf6,0x40,0xef,0x54,0xc1,0xcf,0x9b,0xed,0xfe,
-0xe7,0x9c,0x3b,0xa7,0xbd,0x85,0xe7,0x17,0x5e,0xa8,0xbf,0x50,0x5e,0x9c,0x5b,0x8e,
-0x79,0x89,0xf9,0xae,0xf3,0x05,0x75,0xbd,0x4a,0xc1,0x73,0x8f,0xc2,0xc1,0xb5,0x6f,
-0xf5,0x8f,0xe6,0xe4,0xea,0x46,0xfd,0xd5,0xec,0x7e,0x2c,0xe4,0x27,0x63,0x61,0xb8,
-0xec,0xcd,0x22,0xbc,0xe1,0x6c,0xbd,0x1a,0xd5,0xbe,0x27,0x55,0x0f,0xf7,0x2e,0xdb,
-0x2b,0xae,0x93,0x72,0xe7,0xc0,0x72,0xca,0xa7,0xcf,0x00,0xcb,0x19,0xd7,0x11,0x7b,
-0x87,0x07,0x2c,0xf4,0xe7,0x15,0x45,0xd9,0x15,0xea,0xb5,0xac,0x6a,0xb6,0xa8,0xe7,
-0x9a,0x7d,0xad,0xe3,0xba,0x27,0x5c,0xc2,0x7d,0x14,0xf9,0x96,0x66,0x64,0x6f,0xaf,
-0xdc,0xb8,0xfd,0xcd,0xff,0x7a,0xfc,0xcd,0x8f,0x13,0xdd,0x1f,0xcf,0x5f,0x7b,0x72,
-0x7e,0x7e,0xf6,0x29,0x1a,0x5c,0xd3,0xfe,0x94,0x5d,0xd3,0xce,0xbc,0xfc,0xde,0x4c,
-0xf7,0x3d,0xe6,0xe6,0xdd,0x0b,0x84,0xcd,0x16,0x37,0x5f,0x9a,0xe6,0x18,0x3b,0xb0,
-0x9b,0x7c,0xe1,0x10,0x7f,0x97,0x75,0x71,0xdf,0x52,0x72,0xe9,0x76,0x1d,0x9c,0xf8,
-0x9b,0xae,0x35,0xbf,0xee,0xf8,0xc3,0xa9,0xfe,0x31,0x52,0xbf,0x66,0xd7,0xc1,0xdf,
-0x4b,0x76,0xdf,0x7b,0xe9,0xf9,0xdd,0x2f,0x55,0x14,0xe5,0x55,0xe0,0x3b,0x8a,0x75,
-0x0b,0x6b,0xd6,0x96,0xf5,0x9e,0x2d,0xea,0x40,0xed,0x3b,0x06,0xfe,0x86,0x81,0xd7,
-0x15,0xac,0x63,0x4d,0xdb,0xc6,0x7c,0xeb,0xdc,0x78,0xb9,0x1f,0x9d,0xc0,0x73,0x89,
-0xe5,0x8a,0x3e,0x5d,0xd4,0xd8,0xa5,0xc4,0xd5,0x95,0xba,0x43,0xac,0x3d,0xe4,0x61,
-0xa9,0x7b,0xbe,0xae,0xc2,0x93,0x3b,0x1d,0x77,0x35,0xf2,0x5d,0x43,0xbc,0x3d,0x85,
-0xaf,0x6b,0x57,0x80,0xca,0xe3,0xf5,0xd7,0xa8,0xd7,0x8f,0xeb,0x1e,0x61,0xa5,0x78,
-0x7c,0x9a,0xc7,0xe9,0x62,0xea,0xa6,0xf8,0xb8,0x9e,0x63,0x48,0x89,0x5b,0xe8,0xf5,
-0x09,0x06,0x7f,0x7c,0x59,0x0b,0xa6,0xc4,0x40,0xd2,0xf9,0xf5,0x96,0x6c,0xf3,0x94,
-0x40,0xaf,0xe6,0x7f,0x0f,0xfe,0x70,0xac,0x3f,0x77,0x6a,0xda,0xad,0x71,0x89,0x35,
-0x6b,0xa8,0x6d,0x17,0x78,0xce,0x79,0x73,0xde,0x0f,0xf4,0xe4,0x0d,0x38,0x3a,0xb5,
-0x75,0x54,0xdf,0x1e,0xec,0x5d,0x17,0x44,0xfe,0x9c,0x75,0x6b,0x16,0x9e,0x7f,0xc0,
-0x7a,0x35,0xa1,0x3f,0x37,0xd5,0x34,0xa6,0xab,0x5d,0x77,0x61,0xfb,0x5a,0xb7,0x86,
-0x5c,0xc6,0xd2,0xd6,0xba,0x63,0x49,0x14,0x77,0x17,0xf7,0xad,0xd9,0x3c,0x67,0xd5,
-0x7b,0x57,0xe8,0x3c,0x30,0xc7,0x31,0xe7,0x71,0x2d,0xb4,0x1d,0xce,0x6d,0x0b,0xbe,
-0x5b,0x14,0x8c,0xf8,0x4b,0x22,0x18,0xe3,0x7f,0x2a,0x19,0x8f,0xf8,0x4b,0x23,0x63,
-0xfe,0xd2,0x31,0xea,0x93,0xea,0x67,0x5e,0x1e,0x0e,0x94,0x87,0x09,0xcf,0x03,0xc0,
-0xf3,0x0a,0x7b,0x54,0x46,0xc6,0xfb,0x2a,0xc6,0xc7,0xfb,0x2a,0xc7,0x23,0x7d,0xdb,
-0x23,0xc8,0x9f,0x73,0x0f,0x74,0xe1,0x27,0x63,0xeb,0xcf,0xfb,0x77,0x38,0xfe,0x70,
-0xfa,0xfc,0x58,0xc5,0xfc,0x97,0xaf,0x55,0x3d,0xea,0xad,0xf3,0xb2,0xbd,0x22,0x77,
-0xfb,0x1b,0xff,0x51,0xf9,0xc6,0xd8,0x40,0xdd,0x98,0x9a,0x3f,0xe7,0x58,0x7b,0x9d,
-0xcc,0xa1,0x13,0xbe,0x5b,0x78,0x8e,0x3a,0x38,0xf6,0x6c,0xb7,0x70,0x3d,0x04,0x5c,
-0x6f,0x98,0x44,0xcc,0x1d,0x78,0x3e,0x35,0xd4,0x38,0x15,0x1d,0x6a,0x88,0x46,0x87,
-0x1a,0xa3,0xe8,0xa9,0x86,0x1e,0x2c,0xe8,0xaf,0x36,0x39,0xdc,0x34,0x09,0xfc,0x86,
-0x6f,0x3b,0x69,0xcb,0xc9,0xb3,0x7d,0xf7,0x24,0xbc,0xe3,0x5e,0xf9,0xd9,0xd7,0x5e,
-0xa9,0xac,0xf0,0x56,0x66,0xe0,0xd3,0xfd,0x3f,0xda,0x84,0x5e,0x0d,0xf1,0x76,0xf6,
-0x93,0x39,0x30,0x7b,0x33,0x8c,0x9c,0xf9,0xbe,0x1b,0xe0,0xe8,0x1f,0x85,0x1f,0xff,
-0xe8,0xf6,0x95,0xdd,0xb7,0xa1,0x35,0x27,0x8f,0x38,0xf2,0x8a,0x53,0x7b,0xa0,0x5b,
-0x38,0x7e,0xb5,0xf9,0x43,0x77,0xef,0x73,0xc7,0x47,0x86,0x7a,0xaf,0x5c,0x6d,0x9e,
-0x7b,0xf5,0x9c,0xef,0xd5,0xaa,0x32,0x6f,0x15,0xe6,0xaa,0x31,0x76,0xa7,0xf0,0x03,
-0xd7,0xb6,0x12,0x17,0xf7,0xfc,0x0d,0xf1,0x7c,0x95,0xef,0xb2,0xd2,0xff,0xc7,0xfd,
-0x52,0x5b,0x93,0x84,0xe3,0x6a,0x9f,0x54,0xad,0x07,0xba,0xf0,0x6b,0x77,0xea,0xdf,
-0x3a,0x09,0xb3,0x25,0x96,0x4f,0xc3,0x27,0xce,0xee,0x81,0x4e,0x7e,0xaf,0xed,0xe4,
-0xf7,0x0a,0x4d,0x3a,0xfa,0xb2,0x4c,0x06,0xf6,0x4f,0xd6,0x56,0x66,0xd7,0x96,0x6c,
-0xf0,0x94,0x14,0x6d,0xf0,0x14,0x6d,0x7d,0xc8,0xb3,0x95,0x70,0xcb,0xc2,0x39,0x5c,
-0xd3,0xb8,0xce,0xa5,0x66,0xcb,0x5a,0x2f,0x24,0x1f,0xb2,0xd6,0xdf,0xcd,0x85,0xf9,
-0x9b,0x5f,0x78,0x76,0xe7,0x0b,0xd7,0x22,0x1d,0xd7,0xe6,0x67,0x81,0xe5,0x4f,0xce,
-0x3b,0xfa,0xf2,0xa7,0x52,0x87,0xe8,0x8f,0x3a,0x23,0x7a,0xa8,0x9d,0x58,0x10,0x1e,
-0x33,0xd2,0x2f,0xee,0x43,0xa5,0x27,0xba,0xec,0x8b,0xfe,0xed,0x54,0x6f,0x19,0x81,
-0xe5,0xd7,0xbf,0xad,0xf9,0xc4,0x7d,0x4b,0x0e,0xc4,0xde,0x91,0x3f,0x47,0x2c,0x7e,
-0xf9,0x5a,0xf7,0x32,0x62,0xf3,0x8b,0xf1,0xb6,0xc5,0xd7,0x5e,0xdc,0xf9,0xda,0xce,
-0x2a,0xef,0xce,0xaa,0xcd,0x9e,0xaa,0xed,0x85,0x9e,0xed,0x95,0x85,0x9e,0xca,0xca,
-0x02,0x4f,0x65,0x45,0x81,0xa7,0xa2,0x6c,0x93,0xa7,0xac,0x74,0xa3,0xa7,0x14,0xe7,
-0xa2,0xe8,0x21,0xeb,0x7c,0x00,0xcf,0xd7,0x5b,0x58,0x9e,0xcf,0xe7,0x84,0xee,0x73,
-0xbc,0x8a,0x36,0xdd,0xc6,0x70,0xdd,0x2b,0x57,0xfa,0xc4,0x65,0x7a,0xdc,0x3d,0x6d,
-0xd4,0x1a,0xe3,0x74,0xf5,0xea,0x4a,0xcc,0xd8,0x88,0xeb,0xab,0xd0,0x16,0x1b,0xb9,
-0x8d,0x86,0xe3,0x62,0x0e,0xa6,0xe3,0xe3,0xae,0xd8,0xba,0x21,0x1e,0x6f,0xe2,0xe9,
-0x2e,0x8c,0x37,0xc4,0x48,0x5d,0xf7,0x03,0xe9,0x62,0xf0,0x2b,0xac,0xe3,0xea,0x7a,
-0x6d,0xc2,0x3b,0x53,0x2d,0xb8,0x5a,0xdf,0x9d,0x0e,0xb3,0x75,0x3e,0xab,0xe2,0x61,
-0x49,0x51,0x46,0xc9,0xcf,0xcf,0x67,0xfe,0x9c,0xf9,0xb9,0x85,0xe5,0x97,0xb2,0x08,
-0xc3,0x07,0x7a,0x72,0x06,0x80,0xe7,0x62,0x2f,0x34,0x6b,0xd0,0xa8,0x81,0x93,0x07,
-0x7b,0xbc,0x41,0xd4,0xb7,0x07,0x7b,0xf3,0x82,0xac,0x51,0x03,0x8e,0xe7,0x07,0x81,
-0xe5,0xc1,0x1e,0x8c,0xf5,0xc1,0xc1,0x9e,0xf5,0x83,0xc1,0xde,0xf5,0x41,0xe0,0x3a,
-0xe2,0xed,0x29,0xf5,0x70,0x9a,0x76,0xce,0x58,0x1b,0xa7,0xc6,0xdc,0xd3,0x78,0x14,
-0xcb,0xdc,0x50,0x96,0x3b,0xee,0x46,0x1e,0x4a,0x39,0x36,0x8e,0x7b,0x19,0xc7,0x09,
-0xcb,0xbd,0x7c,0x2f,0x4f,0xf7,0xbc,0x79,0x9e,0x82,0x96,0x83,0xb9,0x2d,0xfd,0xef,
-0x16,0xf7,0x8f,0xf9,0x4b,0x2c,0xfc,0x2e,0x09,0x03,0xc7,0x19,0xcb,0xcb,0xc2,0x88,
-0xbb,0x73,0x3f,0x16,0xe4,0xcc,0x59,0xaf,0x46,0x9c,0x3c,0x50,0x39,0x12,0x0e,0x54,
-0x86,0xc7,0xfa,0x2a,0xc6,0x80,0xe9,0x57,0x03,0x95,0x57,0x81,0xe9,0xf0,0x7e,0x75,
-0xf5,0x40,0x07,0x9e,0xdb,0x1e,0x71,0xe7,0xcf,0x15,0x9d,0x2f,0x2c,0x58,0x5b,0xe8,
-0x9a,0x1f,0x9e,0x54,0x1f,0x19,0xd3,0xb5,0xe1,0x3a,0x47,0xca,0xdf,0x72,0xb2,0x33,
-0x72,0x0e,0xec,0xdb,0x70,0xe0,0xbd,0xb7,0x77,0xbc,0x17,0x09,0xd6,0x47,0x38,0xe6,
-0x5e,0x67,0xc7,0xd9,0x19,0xd3,0xf9,0xd8,0x37,0x01,0xfc,0x16,0xfc,0x5c,0x0e,0x60,
-0x3a,0xe1,0xb9,0x8d,0xe5,0xa1,0x86,0x68,0x2c,0xd4,0x10,0x8b,0x0f,0x35,0xc4,0x31,
-0x12,0x43,0x0d,0x89,0xd8,0x50,0x63,0x6c,0x6a,0xb8,0x69,0x6a,0xf2,0xb2,0x85,0xeb,
-0x76,0x3f,0x16,0xf6,0x6e,0x7f,0x74,0xf2,0x4a,0x60,0xd7,0x95,0x1f,0x7e,0xbf,0xf4,
-0x87,0xeb,0xd7,0xaf,0x5d,0x55,0xef,0x8e,0x2f,0x75,0x5b,0x01,0xab,0xea,0xeb,0x36,
-0xd7,0x33,0x3f,0xe7,0x78,0x3b,0x74,0xe7,0x5c,0xd3,0xce,0x3a,0x35,0xf0,0xf2,0x8f,
-0x47,0x1f,0xfb,0x98,0xf1,0xfc,0xe0,0x87,0x4e,0x0f,0xf4,0xe6,0x59,0x8e,0xb1,0x1f,
-0xa6,0xfe,0xa8,0xcc,0xcf,0x39,0xd6,0xae,0xe6,0xce,0xe7,0x26,0x9a,0xe7,0xd0,0xf3,
-0xfc,0xf5,0x0b,0x75,0xaf,0x57,0x96,0x78,0x2b,0x55,0x1d,0x8e,0xcb,0x8b,0x4b,0x8d,
-0xb7,0x7b,0x1c,0xee,0x40,0x6b,0x8d,0xbe,0x96,0x98,0xd6,0xb0,0xaf,0xc0,0xe6,0xf2,
-0x87,0x4b,0xaa,0x78,0x2e,0xe2,0xed,0xa2,0x5f,0xaa,0xdd,0x33,0x55,0xfa,0xc3,0x1d,
-0x9f,0xe7,0xfe,0x2b,0x6d,0xb6,0xaf,0x4c,0xdb,0xbc,0xec,0xad,0x66,0x61,0xf8,0x62,
-0xf4,0xd8,0xe2,0x52,0xf4,0xe8,0xd2,0x62,0xf4,0xe8,0xe2,0x62,0xec,0xd8,0xe2,0x54,
-0xe0,0x89,0xa9,0x9a,0x8a,0xec,0x1a,0xdc,0x83,0x83,0x77,0xe2,0xba,0x56,0x7b,0x0c,
-0xa7,0x3b,0xaf,0xf9,0x79,0x39,0xf9,0xdf,0xf9,0xd6,0x23,0xdf,0x89,0x0c,0xb4,0x46,
-0xee,0x5e,0x7b,0xea,0xae,0xca,0xcd,0x85,0x87,0x8c,0xf4,0x92,0x51,0xf0,0x5c,0x7d,
-0x2c,0x30,0x9a,0x7d,0xdd,0xed,0xfe,0x2a,0x0a,0x86,0xbb,0x1f,0x1b,0x3c,0xe0,0x54,
-0x9f,0x19,0xd9,0xfb,0xfc,0x49,0xee,0xa3,0x4a,0x5a,0xf4,0xae,0x25,0xa1,0x3b,0x47,
-0x1c,0x1f,0xf5,0x72,0xcb,0xd1,0x63,0xcb,0xbf,0xfe,0x77,0xdf,0xaf,0xf7,0xec,0xf0,
-0xee,0xd9,0xb1,0xd5,0xb3,0xa3,0x7a,0x8b,0xa7,0x1a,0x78,0x5e,0x5e,0xe0,0x29,0x2f,
-0xdd,0xe4,0x29,0xc5,0x7d,0x0d,0x74,0xe9,0x38,0x1f,0xe0,0xe4,0xc4,0xc7,0x6d,0x5d,
-0x3a,0xf5,0x86,0xcf,0x61,0x6d,0x9b,0xda,0x1f,0x5e,0xac,0x95,0x46,0xcf,0x76,0x4d,
-0xff,0xa7,0xe6,0xc3,0x53,0x30,0x3d,0xc3,0x93,0x92,0xbb,0x35,0xc5,0x9c,0x55,0x9c,
-0x4b,0x1b,0x83,0xd4,0x70,0x91,0x26,0x55,0x86,0x27,0x05,0x87,0xed,0xa7,0x53,0xae,
-0x03,0xf9,0x7c,0x86,0x3b,0x5f,0xae,0xde,0x13,0xab,0x71,0x2e,0x13,0xfe,0xab,0xef,
-0x9d,0xf6,0xb3,0xe9,0x3c,0xde,0xb0,0x86,0xeb,0xf7,0xeb,0xe9,0xce,0x85,0x7a,0xbe,
-0x74,0x1d,0x81,0x0b,0xe3,0x15,0xbc,0x73,0x79,0xa2,0x19,0xea,0x16,0x31,0xca,0x8a,
-0x3c,0x65,0xbf,0x38,0x9f,0xf9,0x8b,0xc0,0xfb,0x59,0x01,0xc2,0xf1,0x4b,0x59,0x03,
-0xe0,0xe7,0x03,0x3d,0xd9,0x03,0x3c,0x72,0xe4,0x08,0xf6,0xe4,0x06,0x81,0xe3,0x3c,
-0x72,0x83,0xe0,0xe6,0x62,0x10,0x96,0xf7,0x00,0xcf,0xf3,0x2d,0x1c,0x5f,0x37,0x08,
-0x4c,0xa7,0x3d,0xf0,0xbc,0xf7,0xa1,0x01,0xae,0x6f,0xe7,0x7e,0xa9,0x3a,0xa6,0x9b,
-0xf2,0xe9,0x7a,0xbc,0x41,0xd7,0xb2,0x49,0xae,0xae,0xf1,0x75,0xc9,0xd5,0xb3,0xdc,
-0xf9,0x34,0xca,0x29,0x59,0x73,0x5c,0x62,0xb9,0xb5,0x1e,0xe0,0x3e,0x16,0xf7,0xb3,
-0xc7,0x0f,0xe5,0x50,0xbc,0x1d,0x71,0xf6,0x11,0x7f,0x99,0xcc,0x9f,0x73,0xbe,0x9c,
-0xf1,0x5c,0xe8,0xd4,0x04,0xa6,0x8b,0x5a,0x38,0x8a,0xb1,0xdb,0x1a,0x74,0xd4,0xb7,
-0x23,0xee,0xce,0xb9,0xf4,0x87,0xe5,0x50,0xfb,0xb1,0x14,0x16,0x66,0x16,0xea,0xeb,
-0xa1,0xf1,0x7e,0x4f,0xf1,0xa9,0x97,0xbf,0x77,0xa6,0x92,0x8b,0x50,0x7c,0xde,0x37,
-0x6d,0xc8,0xdc,0xf4,0xa3,0xa7,0xb7,0xfe,0x68,0xb0,0xa7,0x66,0x50,0xf4,0x55,0x43,
-0x0e,0x1d,0x7d,0x53,0x19,0xc7,0x7d,0xa4,0x55,0xc3,0xc0,0xb1,0xca,0xcb,0x69,0x4f,
-0xc7,0x8d,0x16,0x8f,0x07,0xa6,0x37,0x12,0x3f,0x27,0x4c,0x0f,0x35,0xc4,0xa7,0x43,
-0xbe,0xe9,0xe9,0x21,0xdf,0x34,0x30,0x3d,0x7a,0x79,0x57,0x14,0x3d,0x53,0x09,0xcf,
-0x15,0x4c,0x7f,0xff,0x6d,0xdf,0xfb,0xe8,0x85,0xf2,0x55,0x8b,0xbb,0x1b,0x31,0xcf,
-0x7e,0x24,0xea,0xe1,0x04,0x9e,0x0b,0x4c,0xe7,0x3a,0xf7,0x03,0x54,0xeb,0x0e,0x6c,
-0x87,0x1f,0x1c,0xfa,0xa9,0x09,0x9f,0x38,0x91,0x43,0x87,0xc7,0x2b,0x8d,0x09,0xc1,
-0xd3,0x1d,0x8e,0x0e,0xdf,0x57,0xf4,0x63,0xf9,0x64,0xec,0x89,0x4f,0x5e,0xbb,0x50,
-0xf7,0x5a,0x49,0x91,0xb7,0x04,0xbf,0x29,0x7e,0x47,0xb9,0x2e,0x02,0x7b,0x3c,0xb6,
-0xef,0x95,0x01,0xb7,0xd5,0xb5,0x43,0xd4,0xd6,0x1a,0x79,0xfc,0x17,0x3c,0x37,0x2b,
-0x3d,0xfe,0xbc,0x1b,0xe3,0x39,0xea,0xe1,0x3a,0xff,0xc2,0x43,0xa9,0x85,0x4b,0xb4,
-0xdf,0x26,0x9d,0x5a,0xec,0xd8,0xfc,0xbd,0xe8,0xd1,0x7b,0x9f,0x46,0x8f,0x7d,0x7a,
-0x2f,0x7a,0xec,0x9e,0xcb,0x43,0x26,0x7e,0x9c,0x6b,0xdb,0xe3,0xed,0x12,0xdb,0x89,
-0x93,0xc7,0x8e,0x2d,0x60,0x50,0x3f,0xf4,0x69,0xf4,0x57,0x3b,0x14,0x29,0xd9,0x92,
-0x5d,0x42,0x5e,0x67,0x42,0x6f,0xad,0xd4,0x50,0x99,0xb8,0x91,0x05,0x58,0x39,0xcd,
-0xfb,0x2b,0x9a,0x07,0xde,0x39,0x32,0x70,0x67,0xe6,0xc4,0x1d,0xe4,0xca,0x81,0xe7,
-0x42,0x57,0xae,0x1e,0xd3,0x5e,0xf6,0x61,0xd1,0x70,0x5d,0xc1,0x77,0xf9,0x77,0xc5,
-0x2b,0x4e,0xe0,0xb4,0xca,0xdf,0x45,0xbc,0xdd,0xe9,0x77,0x6e,0xe3,0xf8,0xb5,0x27,
-0xa9,0xc7,0x2a,0xe9,0xda,0xae,0x71,0x7d,0x1c,0x7b,0xc9,0x20,0xff,0x8e,0x3a,0xf8,
-0x76,0xaa,0xa5,0x5b,0x8a,0xb5,0x2e,0xbd,0xfe,0x62,0xe3,0xeb,0x8d,0x55,0xde,0x46,
-0xf0,0x71,0x60,0xb8,0x88,0x4b,0x00,0xc3,0x11,0x9b,0xa0,0x78,0xba,0x1d,0x4b,0x97,
-0x5e,0xaf,0x2a,0x0f,0xcf,0x56,0x7a,0xd0,0x29,0x5c,0x5c,0xd7,0xf8,0xa8,0x7a,0x22,
-0x53,0x4f,0xe9,0x14,0xcd,0x9f,0x92,0x33,0x5d,0x4d,0x6c,0x5d,0x62,0x9e,0x8a,0xa5,
-0x86,0xdc,0xa2,0x8e,0x99,0x2a,0xa6,0x1b,0x27,0xb2,0xf6,0x1e,0xe6,0x97,0x18,0xe2,
-0xeb,0x1a,0xbe,0xab,0x71,0x79,0x23,0x66,0xaf,0x30,0x4c,0xb1,0x54,0x9d,0x9f,0xa7,
-0xe0,0xbb,0xee,0x95,0x92,0x61,0x88,0x77,0xe8,0x98,0xb8,0x46,0x8b,0xc1,0x6b,0x5c,
-0x9d,0xf0,0xbc,0xd8,0xc2,0xf3,0x0b,0x16,0x9e,0xbf,0x97,0x1d,0x00,0x96,0xab,0x38,
-0x1e,0xbc,0x94,0x13,0x74,0xb0,0x3c,0x87,0x30,0x7c,0xb0,0xc7,0x3b,0xc8,0x23,0x77,
-0xd0,0xf1,0x92,0xc9,0x1b,0x10,0x1c,0x1d,0x35,0xee,0xc4,0xcf,0x7b,0x99,0xa3,0x07,
-0x7b,0x1e,0x0a,0x0a,0x3f,0x19,0xf4,0x4b,0x15,0xe7,0x33,0xdd,0x75,0x68,0xca,0x33,
-0xe8,0x1c,0xdd,0xa4,0x49,0x13,0xb5,0x1b,0xc0,0x73,0x63,0x4d,0x7b,0x8e,0x27,0x4f,
-0x72,0x75,0x11,0x73,0xb7,0x73,0xe9,0xad,0x87,0x72,0x5b,0x07,0xde,0xb5,0xf1,0x3c,
-0x50,0x4a,0xbe,0xed,0xa8,0x85,0xe3,0x7a,0x38,0xd4,0xc5,0x55,0x8c,0x8c,0xf8,0xd1,
-0x57,0xad,0x42,0xd6,0xc3,0x09,0x2f,0x77,0xd4,0xb5,0x8b,0xfe,0xe7,0x9c,0x3f,0xaf,
-0xba,0xc2,0x7e,0x32,0x0f,0x8f,0xa8,0xbd,0x52,0xaf,0x0c,0xec,0xb8,0x72,0xfe,0x6c,
-0x31,0xf1,0x73,0xd3,0xba,0x6c,0x9c,0x67,0xda,0xbc,0x50,0xeb,0x24,0x5c,0xb5,0x31,
-0xd6,0xf7,0xae,0xae,0xcc,0xa9,0x7e,0xf9,0x6c,0xd9,0xcb,0xe1,0xfe,0xba,0x30,0xf7,
-0x3e,0xb7,0x6b,0xdc,0x81,0xe5,0x83,0x0e,0x96,0x5f,0x0d,0x35,0xd0,0x5e,0xe2,0x38,
-0xea,0xe3,0x86,0x90,0x43,0xb7,0x78,0xf9,0x50,0x43,0x2c,0x36,0xe4,0x8b,0x81,0xa7,
-0xc7,0x43,0x8d,0x16,0x3f,0xb7,0x86,0x8d,0xe9,0xb1,0x61,0x0b,0xcf,0xed,0xfe,0xe7,
-0xd8,0x33,0x5f,0x7f,0x74,0x12,0x7e,0xed,0xf0,0x7b,0xfd,0xdd,0x1b,0xb5,0xbf,0x2b,
-0x2b,0xcb,0x2f,0xfb,0xbf,0xe0,0xc2,0xdf,0x7c,0x4b,0x17,0x7f,0xf3,0x30,0x9e,0x93,
-0x5e,0x2d,0xc2,0x9a,0x73,0xe0,0x39,0x7a,0xa4,0x42,0xa3,0x26,0xbc,0xdb,0x85,0x2f,
-0x1c,0x06,0x61,0xba,0xf4,0x7f,0x05,0x9e,0x1f,0xba,0xae,0x62,0xba,0x2b,0xde,0x3e,
-0x71,0xf8,0xc6,0xad,0xc8,0xfe,0x5b,0xe8,0x7b,0xfe,0xcb,0x73,0xbe,0x5f,0x6e,0xdb,
-0xea,0xdd,0x26,0x74,0x09,0x02,0x8b,0xd4,0xf9,0x6f,0xba,0x97,0x77,0x0d,0x8f,0xbb,
-0x26,0xfe,0x0b,0xe3,0xba,0x72,0xdf,0xa0,0x3e,0x4e,0x3d,0x65,0x0f,0x7e,0x4e,0xdd,
-0xd4,0x78,0x3b,0xf3,0x72,0xdb,0x23,0x2e,0xd1,0x71,0xfb,0x6e,0xbc,0xe5,0xee,0xa7,
-0xd1,0xa3,0x9f,0x2e,0x4c,0x1d,0x5e,0x58,0x9c,0x6c,0x5e,0x5c,0x88,0x1e,0x59,0x20,
-0x4c,0xb7,0x70,0x9c,0xbd,0x64,0xda,0xe7,0x39,0xce,0x6e,0xf7,0x62,0x41,0x3d,0x1c,
-0x34,0xe8,0xc9,0x4e,0xf2,0x89,0xc3,0x1e,0x9e,0x32,0xc8,0xa7,0xc3,0x1f,0xae,0x70,
-0x53,0x4e,0xa1,0x1a,0xe7,0x50,0xd7,0x08,0xbd,0xde,0x26,0x27,0x2b,0x23,0xc7,0x57,
-0xb7,0xd9,0xf7,0xc7,0xdf,0xee,0xfb,0xe3,0xed,0x44,0xf7,0x6d,0x51,0xcb,0x3e,0x7f,
-0xed,0xc4,0xbc,0x83,0xe3,0xea,0x70,0x30,0x9d,0xe3,0xed,0x8a,0xd6,0x5c,0xd5,0xad,
-0xd9,0xf9,0x71,0xf6,0x96,0x39,0x41,0x5e,0x6f,0x62,0xcf,0xb5,0x6f,0x27,0x16,0x65,
-0x4f,0x74,0xaa,0x65,0xb7,0x75,0xe9,0x38,0x96,0xfa,0xf4,0x4e,0xc2,0x6f,0x70,0x72,
-0xf2,0x84,0x9b,0x61,0x6e,0xce,0xba,0xb6,0x0e,0xaa,0xa9,0x5b,0x8c,0xb7,0x93,0x3f,
-0xdc,0x8e,0xb2,0xbc,0x1d,0x22,0x37,0x4e,0xbe,0x32,0x79,0x9c,0x0f,0x97,0x3c,0xdc,
-0x80,0xe3,0x7a,0x6d,0x9b,0xc0,0x72,0xac,0x8f,0xae,0x1a,0xf5,0xb5,0x69,0x30,0x3c,
-0x4d,0x7e,0x5c,0x8d,0x33,0x3d,0x08,0xbf,0xd3,0x62,0xa2,0xc6,0x8d,0x4d,0xd7,0xa7,
-0x8a,0xb1,0xab,0xc9,0x39,0xad,0x74,0x4d,0xb8,0xde,0x5b,0xe3,0xfc,0xea,0xe7,0x13,
-0x7f,0x36,0xc5,0x0c,0x56,0x83,0xe9,0x46,0x8c,0x5f,0x93,0x8a,0xe1,0xea,0x79,0x7c,
-0x50,0x3f,0x31,0x95,0xdb,0x4a,0x4e,0x97,0xa6,0x1e,0x0e,0xbf,0x63,0x71,0x91,0xa7,
-0xf8,0xe2,0xf9,0x35,0x17,0x45,0xfe,0x9c,0xfb,0xab,0x65,0x11,0x3f,0xa7,0x78,0xfb,
-0x25,0x27,0xee,0xae,0xf2,0x73,0x60,0x7a,0xb0,0x27,0x8f,0x39,0xba,0x85,0xe9,0x38,
-0xe6,0x78,0xbb,0xcd,0xcf,0x7b,0xd7,0xc9,0x3d,0x72,0xe9,0x9c,0x3f,0xcf,0xdc,0x6b,
-0xfa,0x6d,0xd3,0xe6,0x53,0x32,0xdc,0x1c,0x35,0x6d,0xbd,0xb7,0xdd,0x27,0xcd,0xa8,
-0x61,0xcb,0x51,0x62,0xef,0x76,0x0e,0x1d,0x35,0x21,0x1b,0x72,0x39,0xf6,0x8e,0xba,
-0x9a,0x63,0x07,0x72,0x8f,0x21,0xde,0x3e,0xea,0x2f,0x1d,0x45,0x7d,0xfb,0xa8,0xdf,
-0xc2,0x70,0xf0,0x74,0xe2,0xea,0x16,0xa6,0xfb,0xb9,0xc6,0x3d,0x1c,0xa8,0x08,0x23,
-0x87,0x8e,0x3d,0xf7,0x64,0xe1,0xfe,0xe7,0x84,0xe1,0x76,0x3d,0x1c,0x63,0x39,0xfc,
-0xdb,0xab,0xe9,0x18,0xf1,0xf6,0xcb,0x03,0x5f,0xbb,0xcc,0xfe,0xed,0xc5,0x17,0x5c,
-0x78,0xae,0xcf,0x69,0x53,0x2c,0x48,0x8b,0x21,0xb9,0xd6,0x32,0x65,0x1d,0x43,0xed,
-0xee,0x13,0x7b,0xd7,0x3f,0xf1,0x87,0xdf,0x54,0xff,0x01,0xfe,0x32,0x4e,0xfe,0x1c,
-0x75,0xed,0xa8,0x89,0xf3,0x39,0xc7,0x76,0x8d,0x3b,0x6a,0xe1,0x50,0xdb,0x8e,0x7a,
-0x38,0x60,0x38,0x6a,0xdd,0xe3,0x21,0x5f,0x3c,0x11,0xf2,0x25,0x30,0x88,0x9b,0x87,
-0xea,0xa7,0x93,0x21,0x5f,0x12,0xfc,0x7c,0x72,0x78,0xd7,0x24,0xe1,0xf8,0x70,0xd3,
-0xa4,0xe4,0xe8,0x84,0xe9,0x8f,0x4e,0x45,0x42,0xbb,0x23,0x17,0xce,0x6e,0xbf,0x00,
-0x0f,0xcd,0x95,0xd6,0xfe,0x2f,0x7b,0xd3,0xd7,0x15,0xf1,0xbc,0xa8,0x87,0x9b,0x89,
-0x1c,0x98,0x71,0xf8,0x39,0xb4,0x6a,0xfb,0x6f,0x20,0x8f,0x0e,0xff,0x76,0xf2,0x91,
-0xb1,0x7b,0xac,0xdd,0x18,0x3f,0x20,0x79,0x3a,0xf5,0x4c,0xbd,0x7a,0xe8,0x06,0xe3,
-0xb9,0x1d,0x6f,0x9f,0x70,0xe2,0xed,0xa8,0x83,0x43,0xee,0x1c,0x31,0xf7,0x8b,0x67,
-0x1b,0x2f,0x82,0x9f,0x8b,0x39,0x89,0xf5,0x53,0xfa,0x66,0x7b,0xf8,0x77,0x54,0x7d,
-0x39,0x4d,0x3c,0x48,0x5f,0x6b,0x56,0xfb,0xbd,0xf5,0x7f,0xa3,0xef,0xf5,0xd7,0x7e,
-0xd1,0x0d,0x7a,0xb5,0xe9,0xd1,0x96,0x69,0xe6,0xe6,0xed,0x7f,0x11,0xda,0x73,0xf2,
-0x84,0x03,0x2f,0x8f,0xd9,0xbc,0x3c,0xd6,0x42,0x1e,0xed,0xa4,0x45,0x4f,0xb4,0x91,
-0x66,0x0d,0xd8,0x2d,0xb5,0xe8,0x22,0xaf,0x3e,0xd3,0x6d,0xd7,0xbd,0x77,0xf3,0xb1,
-0x35,0xd8,0x1f,0xee,0x48,0xb8,0x68,0x73,0x76,0x91,0xda,0x47,0xcc,0xa4,0xb7,0x12,
-0xfb,0xf2,0xe2,0xfc,0xf2,0x57,0x7f,0xb6,0xe7,0xd5,0x5b,0x53,0x9d,0xb7,0xe6,0x67,
-0xba,0x2d,0xfc,0xee,0xbe,0x77,0x6f,0x06,0xda,0xb4,0xee,0x4f,0xb1,0x27,0x7c,0x17,
-0x7b,0xe8,0xd3,0x66,0x4f,0x28,0x9e,0x70,0x27,0x5c,0xfe,0x32,0x0b,0xd7,0xba,0xa8,
-0xce,0x9d,0xfb,0xa4,0xa2,0xef,0x39,0xef,0xa9,0x56,0x6e,0xa6,0x63,0x69,0x79,0xda,
-0xc2,0xe6,0xe9,0xb6,0x65,0xc4,0xca,0x59,0x8f,0x6e,0x1d,0x4f,0xb7,0xd3,0x73,0xe0,
-0xdc,0xa4,0x5b,0xc3,0x63,0xc5,0x5f,0x86,0xea,0xe0,0x67,0x58,0xc7,0xc6,0xa3,0xcb,
-0xc1,0x77,0x6b,0xbf,0x90,0xe8,0x58,0x78,0xe5,0xa7,0xbb,0x5e,0x81,0x3f,0x9c,0xa8,
-0x71,0x13,0x75,0x7f,0x58,0xb7,0xa8,0xb6,0xcd,0xeb,0xf4,0x60,0x21,0x2c,0xcf,0x71,
-0xce,0x43,0x0a,0x1f,0xd7,0x34,0x66,0x62,0x3c,0x48,0x0f,0x65,0xc4,0x26,0x1d,0xbf,
-0xf4,0x7a,0x70,0x13,0x86,0xab,0xd7,0x64,0x9a,0xb9,0xa8,0x3e,0x5a,0xd5,0xbc,0x54,
-0x38,0xfa,0x4a,0x2f,0x51,0x0e,0x64,0x6c,0xc0,0xf5,0xff,0xa9,0x6b,0xb1,0x12,0xf7,
-0xd7,0xd7,0x65,0xb9,0x1e,0x9b,0xee,0x55,0x34,0x9e,0x9a,0x8e,0xc3,0xa7,0x60,0x7a,
-0x1a,0xbd,0x97,0xee,0xb3,0xa0,0xd6,0xc5,0xa9,0xf7,0xad,0x32,0x16,0x6f,0xad,0x2d,
-0x8c,0xe7,0xe8,0x97,0x9a,0x6d,0xf7,0x4b,0xcd,0xa6,0xfc,0xb9,0xcc,0x99,0xf7,0x8a,
-0x7d,0xae,0xcc,0x9f,0x4b,0xaf,0x57,0x11,0x6b,0xef,0xe1,0x1c,0x3a,0xe2,0xed,0x83,
-0xbd,0xc0,0x70,0xde,0x87,0x7a,0xd7,0x87,0x38,0x87,0xfe,0x50,0xf0,0xed,0xb7,0xf2,
-0xdf,0x96,0xfd,0x58,0x0c,0xdf,0x53,0xc7,0xf3,0x94,0xef,0xbf,0x82,0x8f,0xa3,0x1e,
-0xa7,0x97,0xbd,0x46,0x35,0x8c,0x17,0x9a,0x0e,0x51,0x03,0x8b,0x7b,0x5c,0xc4,0xab,
-0x5a,0x0e,0x7a,0x5b,0xc0,0xcf,0x45,0xde,0x9c,0x72,0xe7,0x01,0xe4,0xce,0xcb,0x47,
-0x05,0x9e,0x33,0x8e,0x97,0x87,0x51,0x0b,0x87,0x9a,0x38,0x70,0x74,0x19,0x6f,0x57,
-0x06,0xc5,0xda,0x85,0x5e,0xcd,0xc2,0x70,0x81,0xe5,0x22,0xde,0x5e,0x50,0xb8,0xb6,
-0xc0,0x38,0x4f,0x0c,0xf3,0x26,0x65,0xce,0x28,0xaf,0x35,0x9d,0x83,0x7c,0x6f,0x66,
-0xfe,0xf7,0xfe,0x69,0xf3,0xf7,0x82,0xef,0x3f,0x12,0x74,0x74,0x6b,0xf5,0x54,0xe3,
-0x8e,0x9a,0x38,0x78,0xc9,0xc4,0x42,0x75,0x31,0xf8,0xca,0x40,0xab,0x86,0x91,0x08,
-0xd5,0x27,0xe2,0xa1,0xba,0x78,0x7c,0xd0,0x17,0x07,0x96,0xab,0x71,0xf6,0x64,0xa8,
-0x3e,0x39,0x13,0xaa,0x9b,0x99,0x1d,0xac,0x9f,0x05,0xa6,0xc7,0x87,0x77,0xc6,0x63,
-0xc3,0x3b,0x63,0xb1,0xe1,0xa6,0x58,0xec,0xf2,0xae,0xd8,0xd4,0xe5,0xdd,0x53,0x53,
-0x57,0x76,0x53,0xbf,0x54,0xf4,0x5d,0x19,0xe9,0x6f,0x1a,0x69,0x6e,0xde,0xda,0xbc,
-0x0a,0x08,0xf8,0xd2,0x36,0xfd,0x3e,0x48,0xc6,0xdb,0xc9,0x1f,0x6e,0xef,0x9f,0x98,
-0x9f,0x1f,0x9a,0x15,0x98,0x8e,0x78,0xfb,0xdc,0xd8,0x13,0x73,0x6a,0xff,0x73,0x60,
-0x3b,0x74,0xe7,0xc0,0x71,0xd6,0xab,0x1d,0xbc,0x41,0x71,0xf8,0x89,0xc3,0x84,0xe5,
-0x42,0xb3,0xa6,0xfa,0xbd,0x52,0x3d,0x9c,0x85,0xe7,0xaf,0x9e,0xf7,0xbd,0x5a,0x5d,
-0x96,0x57,0x8d,0xf9,0x06,0x3c,0xc7,0x1c,0xc5,0xe7,0xc1,0x7c,0x75,0x79,0x6b,0x65,
-0x2a,0xf9,0x23,0xbb,0xff,0xa7,0xbc,0x36,0x0c,0x7c,0x3a,0x2d,0xa7,0xd1,0xfe,0xa6,
-0xf2,0x21,0xf5,0x35,0xfa,0x49,0x32,0x9d,0xb7,0x95,0x1e,0xab,0x9b,0x88,0xb7,0xdf,
-0x4e,0xb4,0xdd,0x66,0x5f,0xb8,0x36,0xe9,0xf9,0x3a,0x1f,0x6b,0x99,0x67,0x0c,0x6f,
-0xb5,0x3d,0xe1,0xa0,0x3d,0xef,0xb8,0xc3,0xf5,0xed,0xa8,0x6d,0xef,0x56,0xf0,0x1b,
-0xde,0x32,0x5d,0xac,0x3b,0xb7,0xfb,0xb0,0x50,0x7f,0x35,0xbb,0xcf,0xda,0x78,0xdf,
-0xc1,0xf1,0xea,0xe2,0xec,0x6a,0xe4,0x88,0xd5,0x9a,0x76,0xe2,0xa9,0x6a,0xdd,0x76,
-0xb6,0x27,0x7f,0xe3,0xba,0xcc,0x8d,0x3f,0xfe,0x97,0xfa,0x1f,0xdf,0xbc,0xda,0x71,
-0x93,0x6a,0xd5,0x09,0xc3,0x2d,0x3c,0x27,0x4c,0xb7,0xf7,0x36,0x9e,0x0b,0x0f,0x19,
-0x31,0xa8,0x76,0x7d,0x86,0xf1,0x9b,0xeb,0xda,0xdb,0x97,0x96,0x13,0xc7,0x49,0xaf,
-0x46,0x5a,0xf3,0xe9,0xd6,0xfb,0xe4,0x1f,0x23,0x70,0x3b,0x01,0x2d,0x1b,0x34,0xe8,
-0xd0,0x9f,0xdb,0x9e,0x6f,0xe4,0x29,0xd3,0xea,0x78,0xb9,0x26,0x6c,0xff,0xb7,0x69,
-0xdb,0x2b,0x6e,0xc6,0x3a,0x06,0x3f,0x27,0x5e,0xde,0xf9,0x19,0xe1,0x7a,0xb2,0xcb,
-0xc1,0xf5,0x6b,0x5d,0xcb,0x0b,0xd3,0x9d,0x0b,0xaf,0xbc,0xd0,0xf4,0x4a,0x75,0x89,
-0xb7,0x5a,0xad,0x6f,0xc3,0x77,0x95,0xf8,0x6d,0xc7,0x1e,0x25,0x17,0xb7,0xbd,0xb3,
-0x64,0x2c,0x5d,0xf5,0x7c,0xd1,0xea,0xdb,0x52,0xf2,0xe1,0x0a,0x17,0x77,0xf1,0xf0,
-0x35,0x86,0x58,0x92,0x27,0x15,0xd3,0xf5,0x39,0xe9,0xe2,0xd8,0x0f,0x98,0x6f,0x62,
-0xae,0xae,0xea,0xce,0x32,0x23,0xcd,0x7b,0x18,0x9e,0x77,0x61,0x79,0x46,0xfa,0xeb,
-0x45,0x7d,0xce,0x75,0x1d,0x29,0xd8,0xee,0x8a,0xc9,0x9b,0xbe,0x77,0x86,0xf3,0xff,
-0xe8,0x98,0x6e,0x8c,0xc5,0xa7,0xc3,0x36,0x43,0x1d,0x99,0x29,0x4e,0xad,0xe6,0xd7,
-0x45,0xac,0xa5,0xb4,0xc8,0x53,0xea,0xd4,0xc3,0xd9,0xf5,0xed,0x84,0xe7,0x8c,0xe9,
-0xaa,0x56,0x8d,0xeb,0xdb,0x2d,0x5c,0xbf,0xe4,0xf8,0xc3,0x71,0x7d,0x7b,0x5e,0x3f,
-0xf0,0x9c,0x7d,0xe2,0x18,0xd7,0x51,0xeb,0x8e,0xdc,0x39,0x86,0xf4,0x6f,0xdf,0x93,
-0xf9,0x78,0x4a,0xde,0x45,0x39,0x76,0xf5,0x3b,0x14,0x31,0x1e,0x55,0xa7,0x97,0xe1,
-0x49,0xaf,0xad,0xcf,0x4c,0xad,0x89,0x4f,0xd1,0xab,0x8b,0x1a,0x82,0x2c,0x47,0xd7,
-0x86,0x6b,0xff,0xf0,0xbe,0x9c,0xc3,0x7d,0xef,0xb0,0xfe,0x7c,0x34,0x50,0x4a,0x9a,
-0x35,0xc9,0xd1,0x03,0xe0,0xe9,0xac,0x43,0x0f,0xfb,0x6d,0x7e,0x4e,0x7b,0x8b,0xa3,
-0x93,0x4e,0x8d,0x35,0xe8,0x8c,0xe5,0x55,0x84,0xe5,0x4e,0xfe,0xfc,0x6b,0xce,0xde,
-0xc2,0xf5,0xf3,0x67,0x51,0x0f,0x67,0xe7,0xcf,0x33,0x3c,0xae,0xf9,0x97,0x72,0xff,
-0xa7,0x63,0xfa,0x83,0x62,0xb2,0xf6,0x28,0x28,0xc8,0x2a,0x38,0x73,0xb2,0xf4,0xcc,
-0xb0,0xbf,0x76,0x78,0x7c,0xd0,0x37,0x4e,0x71,0x76,0xe4,0xd0,0x51,0x13,0x67,0x61,
-0xfb,0xd4,0x60,0xfd,0x14,0xe1,0xf9,0x60,0x5d,0x3c,0x31,0x58,0x97,0x48,0x06,0x6b,
-0x93,0x33,0x83,0x35,0x33,0x18,0xb3,0xc1,0x1a,0x0b,0xb7,0x6b,0x93,0x84,0xeb,0x14,
-0x7b,0x6f,0xa4,0xba,0x38,0x8a,0xb7,0x23,0x7f,0x3e,0xdc,0x18,0x8d,0x0f,0xed,0xa4,
-0x38,0x7c,0x72,0xa8,0x31,0x29,0xc7,0x70,0xa3,0x85,0xf5,0xbb,0xe2,0xd1,0xcb,0x8f,
-0x46,0x2f,0xfd,0x77,0xc3,0xa5,0x9a,0x47,0x36,0xd4,0xf0,0x74,0xfe,0xea,0x6c,0x38,
-0x37,0xe2,0x7a,0xc0,0xb9,0x74,0xf8,0xf9,0x41,0xea,0x7f,0xee,0xf8,0xbd,0x32,0xb6,
-0x33,0x37,0x77,0x3c,0x64,0xe0,0xf3,0x4a,0xfd,0x51,0xc7,0xd1,0x2f,0x75,0xff,0x4d,
-0x1c,0x13,0x9e,0x1b,0x6a,0xdc,0xb9,0xb6,0xfd,0xf0,0xdc,0x9f,0xc7,0x0f,0xfe,0xb9,
-0xef,0xed,0x47,0xfb,0x2e,0xbe,0xf0,0xc8,0xc5,0x9f,0x9e,0xaa,0xf9,0xe9,0xb3,0x27,
-0x6b,0x9f,0x3d,0xfd,0x4c,0xdd,0xe9,0x67,0x4f,0xd5,0x3e,0xfb,0xdc,0xa9,0x9a,0xe7,
-0xce,0x9c,0xae,0x3d,0x73,0xe6,0x54,0xed,0x99,0xe7,0x4f,0xd5,0x3e,0x8f,0x81,0xe3,
-0x67,0x4f,0xd5,0xd1,0x6b,0x4e,0x3f,0x53,0x7f,0xfa,0xd4,0x33,0xbe,0x53,0xa7,0x9e,
-0xa9,0x3f,0xc5,0x7b,0x3e,0x3e,0xf9,0x4c,0xfd,0x49,0x1c,0x9f,0x7c,0xc6,0x77,0xf2,
-0xd4,0xc9,0x06,0xeb,0x39,0x6b,0x9c,0xf4,0x29,0xaf,0xe1,0xe7,0x4e,0x9f,0x6c,0x38,
-0xfd,0x93,0x7f,0xf5,0xfd,0xe4,0x07,0xdf,0xaf,0xfb,0x41,0x67,0xc7,0x8e,0xce,0xa6,
-0x9d,0x25,0x4d,0xdb,0xb6,0xe6,0x6f,0x43,0x3f,0x31,0xeb,0x22,0x5a,0xa3,0xae,0x51,
-0x46,0xfc,0xd7,0xb6,0x95,0xf0,0x1c,0xfd,0x58,0xd0,0x5f,0x0d,0xb9,0xf2,0xdb,0xf1,
-0x76,0xe2,0xe6,0xd4,0x8f,0x05,0x7e,0xee,0xf1,0xf6,0x3b,0xd8,0xdf,0x4e,0x74,0xda,
-0x9a,0xb5,0xae,0x3b,0x88,0xcb,0x3b,0x78,0xde,0x45,0xbe,0x32,0xc0,0xfa,0xc5,0x58,
-0xcb,0xe2,0x42,0xec,0xe8,0xc2,0x42,0xd4,0x1a,0xd8,0xc7,0x39,0x7f,0xbe,0x10,0x6b,
-0xa1,0x31,0x11,0xd8,0x3f,0x51,0x53,0x9e,0x5d,0x23,0x63,0xcf,0x79,0x1c,0x7b,0x16,
-0x31,0x67,0x07,0xdf,0xd6,0xe4,0x75,0xb4,0xec,0xe8,0x98,0x1b,0x6f,0x9b,0x23,0x5e,
-0x3e,0xe3,0x60,0xf8,0xfc,0x8c,0x13,0x6b,0xa7,0xfd,0xac,0xc6,0xd1,0x49,0xa3,0xd6,
-0xb9,0xb0,0x38,0xdd,0xb6,0xc8,0x7a,0xf3,0xa3,0xf7,0xe1,0xcd,0x4a,0xba,0x73,0x0b,
-0xaf,0x97,0x13,0xad,0xcb,0xc0,0x76,0xe0,0xf8,0x52,0xb2,0x9d,0x79,0x3a,0x7c,0x5d,
-0x2d,0xee,0x4d,0x98,0x6d,0x0d,0xc1,0xd3,0xd9,0x3f,0xce,0xba,0x17,0x20,0xae,0xde,
-0xb6,0x2c,0x7c,0xe2,0xa4,0xc7,0xcc,0x8c,0xf0,0x98,0x11,0x3c,0x9f,0x7b,0xb2,0x2c,
-0x5e,0xeb,0x72,0xfa,0xab,0x3d,0xbf,0xfb,0x62,0xd9,0xd6,0xbc,0x32,0x63,0x3c,0xdd,
-0x54,0xa3,0x6e,0xf0,0x7b,0x31,0xc5,0xd3,0xd3,0xe9,0xc4,0x53,0xb0,0xca,0xc0,0x53,
-0x53,0xd6,0x2d,0x9d,0x7f,0x6b,0xb8,0x6c,0xba,0x37,0xd4,0x39,0x73,0x0a,0x86,0x7a,
-0x94,0x75,0xf0,0x73,0xdc,0x5b,0xae,0x6a,0x7b,0xc0,0x7d,0xb1,0xfa,0x1d,0x5c,0x7b,
-0xe7,0x1f,0x98,0xf9,0x97,0x67,0x85,0x61,0xe2,0x66,0x06,0x4e,0x9b,0xb2,0xce,0x2b,
-0xba,0xee,0x74,0xf1,0x79,0xb5,0x36,0x9e,0xf4,0xe7,0x17,0x32,0x5f,0x06,0x3f,0x57,
-0xfd,0x64,0x84,0xcf,0x2b,0x8d,0x4b,0xd6,0xe3,0x5e,0xdb,0xef,0x95,0xfc,0x64,0x6c,
-0x7f,0x38,0xd2,0x9d,0xb3,0xdf,0x2b,0x6b,0xd6,0x84,0xd7,0x2b,0xfb,0xbd,0x62,0x08,
-0xbd,0x1a,0xfa,0x9f,0xc3,0x4f,0x26,0xad,0x16,0x5e,0xd5,0xdd,0xad,0xc2,0xc7,0x31,
-0x25,0xe6,0xa0,0xd5,0x74,0xa8,0x73,0x3a,0x9d,0x56,0x5d,0xe0,0xfa,0xc1,0x7d,0xb9,
-0x07,0xfd,0xef,0x96,0xf8,0xa9,0x1f,0x4b,0x80,0xfb,0x9f,0xc3,0x2b,0x8e,0xf7,0x3c,
-0xb8,0xff,0x79,0xc5,0x08,0x70,0x7c,0xb4,0xaf,0x62,0x94,0x7a,0xa4,0x06,0x2a,0xc3,
-0x18,0xec,0x2d,0x23,0x62,0xec,0xbc,0x77,0xfa,0xa5,0x3a,0x3d,0xd0,0x5d,0xfd,0xcf,
-0x4d,0x3c,0xfc,0x7f,0x89,0xbb,0x12,0xde,0x36,0xce,0x33,0x2d,0x59,0xb1,0x24,0xcb,
-0xf2,0x29,0x5b,0xb6,0x64,0xc7,0x77,0x64,0x5b,0xb6,0x25,0x59,0xa7,0x2d,0x59,0x12,
-0x25,0xeb,0x16,0x65,0xc7,0x0b,0xa4,0xd8,0x6d,0x81,0x6d,0xb3,0x40,0xb0,0x8b,0xac,
-0x9b,0x22,0xd8,0xba,0x69,0x81,0x6d,0x82,0x2d,0x02,0xa3,0x40,0x93,0xa2,0x68,0x83,
-0xa6,0xc9,0xc6,0x49,0x1b,0x1f,0x12,0x6d,0xdd,0xb6,0x48,0x0e,0x6f,0x51,0x87,0x25,
-0xf1,0x14,0x25,0x8a,0xa4,0xda,0xc6,0x05,0xfa,0x47,0x76,0xde,0xf7,0x9d,0x6f,0xe6,
-0x9b,0x8f,0x43,0xd9,0x4e,0xdc,0x2c,0x81,0x17,0xdf,0xf0,0xd2,0x31,0x9c,0xe1,0x33,
-0xcf,0x7b,0x3c,0x8f,0x11,0x3f,0x17,0xb9,0x38,0x97,0xab,0xc9,0x54,0x6f,0x29,0x3f,
-0x55,0x50,0xfe,0xab,0xf7,0x8f,0xfe,0x6a,0xea,0xc1,0x99,0x29,0xa8,0x97,0xb3,0x5e,
-0x38,0xc4,0x76,0x65,0xf6,0x9c,0x72,0xed,0x67,0x5d,0x94,0x5f,0x97,0x71,0x7d,0xa4,
-0xdc,0x3f,0x3b,0x7c,0x6a,0x16,0x56,0xc0,0x72,0x98,0x55,0xd3,0x69,0xc3,0x29,0x7a,
-0xaf,0x90,0x6b,0x87,0xfa,0xb9,0x67,0xbc,0xca,0xe3,0x1b,0xaf,0xf4,0xcd,0x8c,0x55,
-0xcc,0xcc,0x8d,0x9e,0x9d,0x9b,0x1f,0x3d,0x3b,0x3f,0x33,0x5e,0x39,0xe3,0x1e,0xad,
-0x72,0xdf,0x7c,0xef,0xc4,0xcd,0xbd,0x7b,0xf2,0xf6,0x7e,0xa3,0x73,0xee,0x45,0xdf,
-0xb2,0x09,0xd3,0xd9,0xb1,0x71,0xe6,0x4c,0xd1,0x99,0x7b,0x9f,0xc9,0x78,0x6e,0x6f,
-0x56,0xe7,0xd5,0xa0,0x7e,0xce,0xea,0xe6,0x80,0xe5,0x4c,0x13,0x6e,0xc9,0xda,0xb8,
-0x14,0x79,0x54,0x1f,0x01,0x9d,0x19,0xe6,0x97,0x0a,0xba,0xed,0x1a,0x96,0x6b,0xba,
-0x70,0xc0,0xcf,0x97,0xa4,0xd6,0xa5,0xb0,0xad,0x29,0xbc,0x3c,0x75,0x61,0x39,0x6a,
-0xbd,0x10,0x0d,0xd9,0x9b,0x43,0x01,0x87,0x29,0xb0,0xe4,0x30,0x2d,0x05,0x1d,0xa6,
-0x60,0xd0,0xd1,0x12,0x0c,0x39,0x4c,0xa1,0x90,0xa3,0x35,0x14,0x92,0xe4,0x90,0xb7,
-0x83,0x8e,0xb6,0x60,0xc0,0x79,0x39,0x10,0x70,0x75,0x04,0xc0,0x13,0x5d,0xf5,0x41,
-0x47,0x0f,0x74,0xe6,0x79,0xde,0x15,0xc4,0x6d,0x4f,0x27,0x6d,0x7b,0xc8,0x07,0x1d,
-0x7c,0xcd,0x83,0x1e,0x58,0xbb,0x42,0x41,0x2f,0xdd,0x57,0x7d,0xcf,0xe5,0x58,0x72,
-0x76,0x2f,0xf9,0x1f,0x75,0xf8,0x07,0xbf,0xb8,0x34,0xf8,0xd6,0x9b,0x15,0x6f,0xd5,
-0x54,0xef,0xab,0xd9,0xb1,0x23,0x6f,0x47,0xb6,0x51,0x87,0x5d,0x26,0xee,0xb4,0x21,
-0x9e,0x53,0xfd,0x1c,0xfa,0xdb,0xa1,0x6e,0x9e,0xa6,0x0f,0xa7,0xce,0xaa,0x0d,0xc4,
-0x40,0x63,0x86,0xe6,0xd3,0xfa,0x30,0xe7,0x4e,0x1a,0xaf,0x3d,0x71,0xe8,0x7f,0x4b,
-0x78,0x3a,0x12,0x29,0x4f,0x7b,0x2a,0xe5,0x6a,0x4f,0xad,0xbb,0xdb,0xd6,0x53,0xee,
-0x76,0xec,0x6b,0x07,0x2c,0x87,0x9e,0x38,0x87,0xa5,0xd9,0x71,0xfc,0x40,0xee,0x71,
-0xe0,0xa9,0x80,0xe1,0xac,0x6f,0x5b,0xef,0xcf,0x92,0xbd,0xf9,0xf4,0xa9,0x7d,0xa7,
-0x9d,0xa3,0x9d,0xce,0xd5,0x99,0x2b,0x4a,0x2f,0xfb,0x55,0xc4,0x70,0xb5,0xaf,0x7d,
-0x96,0xcd,0x9d,0x5f,0xa3,0xbe,0xf6,0x59,0x61,0x46,0x4d,0xc6,0x74,0xca,0xa7,0xcb,
-0x38,0xed,0xeb,0x41,0xfc,0x06,0x8e,0x8e,0xda,0x31,0x7e,0xb3,0xa2,0x1f,0x33,0x40,
-0x33,0xe8,0x6c,0xde,0x1c,0xe6,0xd4,0x75,0xb8,0x4c,0x3d,0x6e,0x54,0x37,0x37,0xab,
-0x75,0x73,0x7c,0xef,0x2c,0xe9,0xcb,0xe0,0x8c,0xda,0xdc,0x15,0xf5,0xb5,0x4c,0x3b,
-0x0e,0xe7,0xd6,0xe6,0x06,0xd6,0xd7,0xa6,0x07,0x50,0xbf,0xbd,0xb4,0xb8,0xa0,0x94,
-0xaf,0x27,0xa4,0xf5,0xa7,0x73,0x33,0x66,0x46,0xdc,0xdb,0xa8,0x27,0x4b,0xc4,0x17,
-0x35,0x47,0x6e,0x84,0x41,0x46,0xb8,0x65,0x94,0x63,0x35,0xc0,0xa8,0x34,0x2e,0x2a,
-0x5e,0x3f,0x6c,0xe0,0x43,0xa5,0xcb,0xab,0xbd,0xc0,0x5b,0x5a,0x0e,0xe1,0xeb,0xbe,
-0x57,0x3c,0x7b,0xb2,0x75,0x2f,0x4a,0xeb,0x85,0xda,0x88,0xab,0x65,0xe2,0x6c,0x1b,
-0xf2,0x78,0x03,0x7c,0xdf,0x57,0x9c,0x45,0xfa,0x70,0x7f,0x04,0x3f,0x16,0xd2,0x6f,
-0x27,0x4c,0x67,0xfa,0x70,0xcc,0x07,0x5d,0xd1,0x87,0x93,0x71,0x1c,0xb4,0xe1,0x98,
-0xcf,0x9a,0xe6,0x7f,0xbe,0xd5,0x02,0x7a,0x32,0xa4,0xe1,0xbe,0x4d,0xd5,0x93,0x01,
-0xed,0x76,0xa6,0x0f,0x77,0xb1,0xee,0xa5,0x8b,0x99,0x70,0xdb,0x68,0x46,0x3e,0xad,
-0xdf,0x8d,0xd7,0x8d,0x79,0x49,0x3f,0xa3,0xa6,0x6e,0x6f,0x4e,0xd7,0x32,0xe4,0xb7,
-0x45,0xfd,0x28,0x08,0x53,0x53,0xbe,0x69,0xe8,0x73,0xd2,0x7b,0x25,0x6f,0x35,0x85,
-0x97,0xeb,0xf4,0xe1,0xe4,0x18,0x3c,0xf4,0x88,0xe1,0x3a,0xe0,0x39,0xe4,0xdc,0x11,
-0xd3,0x2d,0x87,0xd1,0xfb,0x1c,0x66,0xcf,0xad,0x96,0x23,0x56,0xe6,0x83,0x0e,0xfe,
-0xa9,0xa0,0x0b,0x07,0x78,0x8e,0x7e,0xa9,0x06,0x7e,0x2c,0xcf,0xca,0xbb,0x8d,0xae,
-0xd9,0x8c,0x3c,0x8d,0x60,0x3f,0xc2,0xbe,0x32,0x77,0xef,0x32,0xdf,0xfe,0xa4,0xec,
-0x36,0xe3,0xe8,0x14,0x34,0x73,0xce,0x07,0x69,0xca,0xc0,0xec,0xf9,0x39,0x17,0xe4,
-0xda,0xa1,0x8e,0xee,0x1c,0xab,0x74,0x6a,0x5a,0x32,0xa4,0x11,0x87,0xb3,0x6a,0x30,
-0x83,0x3e,0xce,0xd5,0xcd,0x27,0xaa,0x5d,0xee,0x89,0xf3,0x6e,0xef,0xc4,0x79,0xaf,
-0x6f,0xbc,0xca,0xe7,0x1f,0xab,0xf2,0xc3,0xf6,0xe8,0x9d,0xf3,0xa3,0xdf,0xfd,0xe7,
-0x03,0xdf,0x2d,0xd8,0xfa,0x52,0xc1,0xd7,0x3f,0xeb,0xfe,0x31,0x37,0xd8,0x47,0xf9,
-0xb9,0x59,0xf9,0xd5,0x15,0x45,0xd5,0x43,0xb7,0xea,0x86,0xc8,0xff,0x1c,0xbc,0xd5,
-0x00,0xcf,0x9b,0xb1,0xb7,0x1d,0xee,0x6b,0x33,0xe7,0xad,0xf3,0x80,0xdf,0xb1,0x87,
-0xd5,0xb1,0x80,0xf5,0x62,0x00,0x6a,0xe8,0x80,0xe5,0x90,0x73,0xc7,0x3c,0x3b,0x57,
-0x3f,0x87,0xbe,0x76,0xe0,0xe4,0x31,0xfb,0xc5,0x58,0xd2,0x56,0x9f,0x5c,0x9b,0xaa,
-0x5d,0x8b,0x5a,0x2f,0x46,0x83,0x8e,0xd6,0x20,0xcc,0xae,0x85,0xed,0x4d,0xe1,0xb0,
-0xfd,0x52,0x38,0x24,0xb5,0x84,0x22,0xf6,0x4b,0x91,0xa8,0xad,0x29,0x1a,0xb1,0x37,
-0x47,0x00,0xe3,0x01,0xcb,0x97,0x9c,0x97,0x97,0x00,0xcb,0x03,0xee,0x4e,0x19,0xd7,
-0x3b,0x11,0xdb,0x71,0xdb,0x0d,0xf8,0xdd,0x11,0x0c,0xba,0x3b,0x83,0xec,0xb9,0x90,
-0xab,0x33,0x14,0x72,0x77,0xa9,0x01,0xf8,0x8e,0x78,0xee,0x51,0xf0,0x5c,0x89,0xb0,
-0xa7,0x27,0x0c,0x98,0x8e,0xab,0xb7,0x37,0x14,0x70,0xf5,0x04,0xa6,0x1e,0x98,0xa6,
-0xae,0xff,0xfb,0xb9,0xeb,0xc7,0x8e,0xed,0x3c,0x26,0x7f,0xd9,0xe7,0x88,0x7c,0x08,
-0xf6,0x93,0x51,0x2e,0xd2,0xe8,0x3e,0xdc,0x50,0xef,0xf5,0x11,0xe9,0xbd,0x82,0x5f,
-0x2a,0x3f,0x77,0x4e,0x98,0x3e,0xa0,0x60,0xba,0x99,0xf0,0x5c,0xd1,0x78,0x45,0xed,
-0xd7,0xe9,0x3e,0xac,0x9f,0x93,0xef,0x4a,0x3f,0x7a,0xa3,0x03,0x76,0x27,0xbd,0x5d,
-0x49,0xc4,0x78,0x5f,0x77,0x02,0x73,0xee,0xd3,0xfd,0x6b,0x56,0x8b,0xc9,0x5a,0xb2,
-0x27,0xb7,0x04,0xf3,0xc8,0x9b,0x04,0x3f,0x16,0x3c,0x2f,0xb2,0x37,0x1d,0x3c,0xb8,
-0xf3,0xe0,0x6f,0x3f,0x6c,0xfa,0xed,0xea,0xec,0x95,0xd5,0xd5,0xd9,0xab,0x69,0x41,
-0xb8,0x7d,0x55,0xe5,0xe3,0x6b,0x33,0x57,0xb9,0xfb,0x57,0xd6,0x78,0x1f,0x16,0xd2,
-0x79,0x55,0x72,0xef,0xb3,0x80,0xdf,0x70,0xff,0x0a,0xea,0xc8,0x68,0xfd,0x71,0xaf,
-0x26,0x34,0x0f,0x35,0xe5,0x35,0x9c,0x9e,0x8c,0x16,0xbc,0x56,0x0c,0xf3,0x47,0x67,
-0x9e,0xe7,0xbc,0x77,0x2a,0xd3,0x70,0xbf,0x9a,0x5a,0xf3,0x5f,0x5d,0x7b,0xe7,0x87,
-0xb5,0xef,0x14,0x17,0x15,0x14,0xeb,0x30,0x9b,0xfb,0xee,0x4c,0x9b,0x05,0xdf,0xa4,
-0xe5,0x35,0x45,0x4e,0x27,0xe6,0x71,0xc5,0x5a,0xa5,0x98,0xdf,0xe5,0x75,0x63,0xf8,
-0x3a,0x7b,0x5a,0x7d,0xd7,0x80,0x97,0xa5,0x69,0xce,0x88,0xf3,0xea,0xdc,0x77,0x97,
-0x61,0x9f,0xbc,0x70,0x5f,0x3c,0xe6,0xbe,0x31,0x47,0x7f,0xca,0x4d,0x97,0x2f,0x10,
-0x7f,0x97,0x98,0x7b,0xc8,0x74,0x4d,0xcc,0xe5,0x30,0x0c,0xdf,0x2b,0xe6,0x3f,0x8c,
-0x78,0x7c,0xb6,0xd2,0x9b,0x90,0x65,0x80,0x15,0x3c,0x0e,0x28,0xfb,0x71,0x7f,0xb1,
-0xe2,0x7f,0xce,0xf9,0xa5,0xa2,0xbf,0xda,0x97,0xa2,0xbf,0x5a,0x9e,0x96,0x6f,0x47,
-0x4e,0xbe,0xe5,0x3e,0xf4,0xc1,0x81,0x1f,0x0b,0xad,0x8a,0xbf,0x1a,0xf3,0x4b,0x55,
-0xf8,0x39,0xe9,0xca,0x6c,0x7f,0xf0,0xe9,0xef,0x0a,0x3f,0xbd,0x50,0xaf,0xf7,0x4b,
-0x35,0xe2,0xe5,0x69,0xf3,0x68,0x02,0x9e,0x8b,0x1a,0xc4,0x3c,0x46,0xb3,0x9c,0x94,
-0xaa,0x77,0xc8,0xeb,0x48,0x29,0x35,0x37,0xa8,0x43,0xa1,0xce,0xd2,0x56,0xd2,0x87,
-0x2b,0xda,0x96,0x55,0xd4,0xd5,0x92,0xdf,0x05,0xf3,0x6a,0x34,0x73,0xce,0xe6,0xcf,
-0x0f,0x62,0x1d,0x1d,0x74,0x65,0x6c,0x83,0x07,0x6d,0xb6,0xa1,0x83,0x36,0xeb,0xd0,
-0x21,0xab,0xda,0xe3,0x0e,0xfc,0xdc,0x42,0xfc,0x1c,0x56,0xeb,0xd0,0x61,0x2b,0x60,
-0xb9,0x6d,0xe8,0x88,0x0d,0xc2,0x6e,0x39,0x62,0xb7,0x59,0x8e,0xda,0x40,0xc7,0x1d,
-0xbc,0xd5,0x20,0xe7,0xae,0xf6,0xc3,0x19,0xe4,0x96,0xd2,0xae,0xc3,0x84,0xd9,0x7c,
-0xb1,0x37,0x22,0xcd,0x4b,0x4e,0xa8,0xa7,0x6c,0x2f,0xcc,0xd9,0xfe,0xc6,0x0f,0xf6,
-0xbf,0x31,0x76,0xb7,0x7c,0x8c,0xfa,0xda,0xcf,0x48,0x4c,0xef,0xd5,0x39,0x76,0x96,
-0x30,0x7c,0x94,0xfa,0xda,0x99,0x3e,0x1c,0xcc,0xa0,0x43,0xc0,0xec,0x9a,0x73,0xbc,
-0xd2,0x89,0x7a,0x32,0xaa,0xa6,0x4c,0x95,0x8c,0xdf,0x55,0xe9,0xbd,0x70,0x13,0x50,
-0x3b,0xa7,0x9e,0x38,0x16,0xce,0x89,0x5a,0xe7,0x67,0x1f,0x9d,0xfd,0xac,0xb9,0xb1,
-0xa8,0x59,0xfe,0xc3,0x73,0x5e,0xc4,0xf9,0xf5,0x22,0x6f,0xb0,0x8f,0xea,0xcf,0xef,
-0xae,0x1f,0xb9,0x55,0x3d,0x02,0xf5,0x72,0xd6,0x0b,0x07,0xdb,0xe4,0x95,0xaa,0xf4,
-0xc2,0x49,0x54,0x3f,0x87,0x5e,0x38,0x96,0x6f,0xd7,0x74,0x5f,0x69,0x06,0x9d,0x61,
-0xfa,0x63,0x67,0x1b,0xf2,0xf2,0xb8,0xed,0x42,0xfc,0x6f,0xde,0x4b,0x7f,0x7b,0xe2,
-0x69,0x7a,0x12,0xb7,0xd5,0xc7,0x83,0x52,0x73,0x30,0x20,0xb5,0x06,0x96,0xad,0x17,
-0x97,0x21,0x82,0x52,0x6b,0x30,0xe0,0x68,0x0b,0x40,0xef,0xfb,0xb2,0xbd,0x69,0x19,
-0x38,0x7a,0xc0,0xd9,0xae,0x61,0x39,0x60,0xb8,0xb3,0x23,0x10,0x74,0x5d,0x0e,0x52,
-0x74,0x60,0x84,0x9c,0x1d,0x21,0x75,0xdb,0xad,0x6c,0xcb,0xf8,0x1e,0x72,0x03,0xae,
-0xcb,0x21,0x63,0x39,0x06,0xe0,0x3b,0xf2,0x73,0x39,0xdc,0xdd,0xc4,0xd1,0x19,0x57,
-0xf7,0x52,0x84,0xbd,0x3d,0xe1,0x05,0xa9,0x6b,0xe1,0xc3,0x9b,0x0d,0x1f,0x56,0x55,
-0x16,0x57,0xc9,0x07,0x16,0xce,0x19,0x8a,0xfc,0x8c,0x3d,0x26,0xee,0x3f,0xf1,0x39,
-0x4d,0x1f,0x8e,0xf4,0x5e,0x55,0x6d,0x38,0x4e,0x4b,0x46,0xe5,0xe9,0xa8,0x0f,0xd7,
-0xaf,0x68,0xca,0x0c,0xa8,0xbe,0x6a,0xac,0x86,0x0e,0xb8,0x8e,0x3e,0x2c,0x7e,0x4d,
-0xf7,0x15,0x7a,0xe1,0x20,0xc0,0x5f,0x6d,0xcf,0xee,0xdc,0x3d,0x2a,0x3e,0x09,0x35,
-0xba,0xa2,0xdd,0x5b,0x8b,0x6e,0xfc,0xa8,0xfa,0x46,0xc0,0xd9,0x1f,0x58,0x9d,0x91,
-0xf1,0x7b,0xee,0x2a,0xf1,0x73,0xe0,0xe3,0xb8,0x5e,0x89,0x53,0xad,0xdc,0x9c,0x48,
-0xfa,0xfb,0x93,0x49,0xbf,0x39,0x09,0xb9,0x75,0x5c,0xe5,0x80,0xe7,0x08,0xbf,0x95,
-0x90,0xf9,0xb7,0x5a,0x4f,0xe7,0x34,0x65,0x60,0x6e,0x9c,0xf9,0xab,0x51,0x08,0xf3,
-0x69,0xb0,0xce,0xb3,0x19,0x36,0xc2,0x6e,0xda,0xfe,0xa7,0x24,0xd3,0x9b,0xd1,0x34,
-0x5f,0x09,0xd3,0x79,0xec,0x4f,0xcd,0x5d,0x4b,0xa5,0xe6,0x5f,0x4d,0xc1,0xb5,0xc6,
-0x8d,0x1f,0xd6,0xde,0xd8,0xbb,0x7b,0xeb,0x5e,0x1d,0x17,0x17,0xfd,0x51,0xd8,0xac,
-0xae,0x30,0x97,0xc6,0x78,0x3c,0x3e,0x96,0xab,0x84,0xf0,0xbc,0x18,0xe2,0x3c,0xb3,
-0x91,0xff,0x95,0x98,0x13,0xe5,0xe7,0x89,0x9f,0x45,0x7b,0x86,0xff,0xfc,0x32,0xf2,
-0x72,0x56,0x9f,0xcf,0x90,0x0f,0xff,0xa6,0xb7,0xa7,0xfe,0x4c,0xa3,0x67,0xb3,0xd3,
-0x9f,0xdb,0x08,0xeb,0x33,0xfd,0x1e,0xa3,0x73,0x4b,0xe5,0xf3,0xfc,0x35,0x40,0xa6,
-0x3c,0xee,0x06,0x79,0x92,0xe2,0x62,0xf0,0x4b,0xcd,0xf9,0x19,0xc3,0x73,0xe4,0xe8,
-0xe8,0x9b,0xca,0xf8,0x79,0xbe,0x85,0x74,0xdb,0xf3,0x74,0xfe,0x6a,0x90,0x77,0xa7,
-0xfa,0xf9,0x96,0x07,0x6a,0xed,0x5c,0xf1,0x40,0xa7,0x9e,0xf6,0x42,0x55,0x27,0x4e,
-0xd3,0x6f,0xdf,0x00,0xcf,0x33,0xf1,0x74,0x4e,0x37,0x46,0x3d,0x06,0x39,0x3d,0x38,
-0xd0,0x82,0x33,0xd2,0x8f,0x11,0xb1,0x9c,0xd7,0x49,0x84,0xf9,0x4d,0xd0,0x53,0x2a,
-0xdd,0x99,0x55,0x0a,0xfa,0x4a,0x03,0xed,0xf9,0x03,0x63,0xb7,0xf6,0x8f,0xd9,0xef,
-0x95,0xd8,0xed,0x83,0xa5,0x76,0x69,0xb0,0x44,0x72,0x0c,0x96,0x3a,0x9c,0xf7,0x4a,
-0x9c,0xce,0xc1,0x52,0xa7,0xe3,0x5e,0xa9,0xc3,0x3e,0x78,0xd0,0x0e,0x7a,0xaf,0xa4,
-0x13,0x47,0xf5,0x73,0xd4,0x93,0x91,0x71,0x9c,0x30,0xfd,0xc8,0x14,0xf1,0x72,0x19,
-0xd3,0x2d,0x32,0xa6,0xcb,0x01,0x1c,0xfd,0xd1,0xfd,0x63,0x8f,0x48,0xfb,0x55,0xc6,
-0xf3,0x1b,0x5a,0xbe,0x5d,0xfd,0x0c,0xd9,0xf5,0x9d,0xd1,0x67,0x27,0xe4,0xda,0x75,
-0xf5,0x12,0xa1,0x0f,0x82,0xed,0x13,0xbe,0xf7,0xf7,0xe8,0xcb,0x79,0x47,0x7f,0xf9,
-0x3f,0x87,0x7f,0xe9,0x18,0x56,0x34,0xdc,0x47,0xce,0x3a,0x69,0xfe,0xfc,0xac,0x03,
-0x30,0x9d,0x70,0x9d,0xf4,0x5e,0x01,0xd7,0x01,0xd3,0xdd,0x63,0x4a,0xaf,0xfb,0x18,
-0xf5,0xc5,0x91,0xae,0x4c,0x85,0xa2,0x2d,0x53,0xe1,0xa3,0xed,0x4a,0xaf,0x6b,0xbc,
-0x5a,0x9d,0x57,0x73,0x4d,0xd4,0x62,0x3f,0x1c,0xac,0x78,0x5f,0x0e,0x69,0xb4,0x46,
-0x7a,0xff,0xbd,0xb2,0xf7,0x4f,0x9c,0xd8,0x7a,0xe2,0x1f,0x7b,0x25,0x6d,0x7c,0xae,
-0x6c,0xf8,0x1a,0x79,0xdf,0x56,0x9e,0x2b,0xaa,0x1c,0xbb,0x55,0x35,0xb6,0x38,0x75,
-0x61,0x51,0xeb,0x85,0x6b,0xc6,0x5e,0x38,0xf4,0x61,0xb1,0xb5,0x70,0x98,0x6e,0x9a,
-0x57,0x3d,0x59,0x78,0x3c,0x67,0xf3,0xe7,0x32,0xa6,0x2f,0xd9,0x5b,0x97,0x96,0xad,
-0x0d,0xcb,0x7f,0x71,0x34,0xfc,0xe5,0xef,0x33,0xa6,0xbf,0xaf,0x3b,0x1a,0xd7,0x81,
-0x8b,0x2f,0x3a,0xdb,0x16,0x21,0xcf,0x1e,0x92,0x9a,0x43,0xc0,0xcb,0x01,0xcb,0x21,
-0x60,0x1b,0x72,0xed,0x01,0x07,0x61,0x39,0x60,0x3a,0x44,0xd0,0xd9,0xa6,0xe4,0xe2,
-0x4d,0xa1,0xb0,0xc3,0x14,0x0e,0x3b,0x4d,0xe1,0x88,0xc3,0x14,0x09,0x3b,0xdb,0xe4,
-0xed,0xf6,0x70,0xc8,0x79,0x39,0x14,0x72,0xb5,0x87,0xc2,0xae,0x8e,0x70,0xc8,0xd5,
-0x11,0x22,0x9e,0xce,0x71,0x75,0x19,0xd3,0xc3,0x9e,0xae,0x30,0xf1,0x73,0xd8,0xee,
-0x0e,0x23,0x86,0xcb,0x6b,0xd8,0x0b,0xd1,0x23,0x47,0x2f,0xae,0x41,0x77,0x4f,0xf0,
-0xe3,0xdf,0x5c,0xfc,0xb8,0xaa,0xaa,0xb8,0x0a,0x6a,0xea,0xea,0xfe,0xcb,0x4e,0x3f,
-0x36,0xc5,0xe7,0xf8,0xfd,0x89,0xfe,0x6a,0x0f,0xc1,0x5f,0x0d,0xb4,0x64,0xfa,0x96,
-0xa9,0x76,0xde,0xaf,0xd5,0xd0,0x41,0xe7,0xd5,0xd7,0xc7,0x69,0xca,0xf4,0x29,0xfd,
-0xec,0x42,0xa0,0x5e,0xbb,0x79,0x95,0xf9,0xa0,0x33,0x1f,0x16,0xb6,0xfd,0xd0,0xd2,
-0xfe,0x70,0xef,0xee,0xdc,0xbd,0x22,0x87,0x84,0x75,0x7b,0x61,0xde,0xf6,0xef,0xff,
-0xcb,0xa9,0xef,0xfb,0xc6,0x7b,0x7c,0x98,0x67,0x9f,0xa1,0xfc,0x3a,0xd4,0xc6,0x59,
-0xae,0x1d,0xf9,0xb7,0xbf,0x3f,0x91,0x9c,0xee,0x49,0x82,0xb7,0x78,0x6a,0x5a,0x0e,
-0x7f,0x5f,0x2a,0xe9,0xef,0x4b,0xe2,0xe3,0x33,0xe6,0x24,0x05,0xc3,0x73,0xc0,0x6f,
-0x8d,0xab,0xf3,0x1e,0xa9,0x84,0xdb,0xdc,0x2a,0xe3,0x7c,0xc8,0x65,0x0e,0xf9,0x26,
-0xe5,0xdf,0x3f,0x3d,0xb0,0xca,0xf4,0x62,0xb4,0x80,0xb9,0xf3,0x57,0x35,0xfc,0xc6,
-0x19,0x74,0xc5,0x13,0x5d,0x97,0x6f,0x37,0x2b,0xfa,0x70,0xd4,0x0f,0xf7,0xf3,0x1f,
-0x55,0xff,0xfc,0x48,0x49,0xc1,0x11,0xfc,0xfe,0xda,0xc6,0x69,0xb9,0x2a,0xbc,0x44,
-0x17,0x05,0x4a,0xcf,0x9c,0xd2,0x23,0xc8,0xe6,0xd9,0x58,0xb0,0xf9,0x1e,0xa6,0xf3,
-0xca,0x42,0xf4,0x61,0xc1,0x9e,0x3a,0xa1,0x2f,0x9e,0xf1,0x2b,0x86,0xdd,0x22,0xa7,
-0x4f,0xeb,0x89,0xdf,0xa0,0x17,0x5e,0xcd,0xef,0x1b,0xe4,0xf1,0xd9,0x71,0xf6,0xb4,
-0x6b,0xca,0xff,0x8f,0xdb,0xd7,0xf9,0x3b,0x32,0xe1,0xbd,0x2e,0x57,0x2f,0x9e,0x63,
-0x46,0x3f,0x23,0x5b,0x7b,0x8f,0xd1,0x75,0x00,0x5b,0xc1,0x5f,0xed,0xa7,0x37,0x72,
-0x7e,0x0a,0xf9,0x76,0xf0,0x49,0xd5,0xbc,0x52,0x73,0x55,0x7f,0x35,0x8a,0x7c,0xf4,
-0x5f,0x61,0xa1,0x6a,0xb8,0xdf,0x61,0xb9,0x76,0xd2,0x6f,0xc7,0x1a,0xfa,0x6d,0xcd,
-0xff,0x9c,0xe9,0xb7,0xa3,0xbf,0x5a,0x7d,0xce,0x85,0x34,0x2c,0x17,0x75,0xdf,0x72,
-0xf4,0xb5,0x70,0x51,0x0b,0x87,0xbf,0x96,0x54,0x67,0xd2,0x38,0xaf,0xb4,0x34,0x7e,
-0xbe,0x45,0xd3,0x79,0x06,0xfd,0x24,0x38,0x1f,0x50,0xeb,0x58,0xc6,0xf4,0x92,0x1d,
-0x59,0x25,0x84,0xe7,0x79,0x03,0x63,0x9f,0x03,0x9e,0x97,0xca,0x78,0x4e,0x98,0x0e,
-0x78,0x8e,0x98,0x3e,0x58,0x22,0xe3,0xf9,0x01,0x07,0x70,0x74,0x9a,0x53,0x63,0xb9,
-0x76,0x05,0xd7,0x65,0x6e,0xce,0xfa,0xe2,0xc0,0xf7,0x1c,0xbc,0x52,0xd5,0xb8,0x4f,
-0xdc,0x9c,0xd5,0xd0,0x55,0x3d,0x19,0x11,0xbb,0xb3,0x84,0xe3,0x9a,0x3f,0xee,0xb3,
-0xd2,0x67,0x3f,0xc4,0xba,0x09,0xaf,0xe9,0xce,0xb0,0x9d,0xcd,0xea,0x35,0xd6,0x15,
-0x36,0xde,0xbf,0x55,0x76,0x1f,0xe6,0xd3,0xdc,0x23,0x67,0xdc,0x80,0xe9,0x58,0x53,
-0x1f,0xab,0xc0,0x00,0x6f,0x35,0x08,0xe4,0xe4,0x72,0xa0,0x9e,0xcc,0x68,0x85,0x1b,
-0xb0,0xdc,0x37,0x7a,0x0e,0xe7,0xd6,0xa0,0xcf,0x1d,0x62,0x76,0xa4,0x7c,0x76,0x6e,
-0xf4,0xcc,0xdc,0xf4,0x58,0xc5,0x34,0xf4,0xb8,0xbb,0x27,0xaa,0xdd,0xc8,0xc9,0x55,
-0x8e,0x4e,0x58,0xee,0x9e,0xac,0x95,0x1f,0xaf,0x73,0x8d,0x0f,0x9d,0x1f,0x7f,0xe3,
-0xdf,0x0e,0xbd,0xb1,0x6b,0x57,0xee,0xae,0xe7,0x3d,0x0f,0xbe,0xce,0xed,0x79,0xce,
-0x7f,0xe8,0x87,0xb3,0xdc,0xaa,0xb5,0xcc,0x5b,0x89,0x9f,0xcf,0xda,0x5b,0x71,0xfe,
-0x1c,0xb0,0x1c,0x74,0xdb,0x41,0xef,0x15,0xfd,0x53,0x25,0xaa,0xa3,0x33,0x5c,0x47,
-0x7d,0x38,0xa5,0x6e,0xce,0xd7,0xcf,0x83,0xb6,0x4b,0x41,0xf0,0x50,0x4d,0x58,0xeb,
-0x12,0x09,0x7b,0x43,0x22,0x6a,0x6b,0x8c,0x42,0x7f,0xfb,0x82,0xb3,0x6d,0x61,0xc9,
-0xd1,0xb6,0x14,0xb2,0xb7,0x84,0x00,0xdf,0xc3,0xf6,0x66,0xcc,0xb7,0x07,0x25,0xc8,
-0xb1,0xcb,0xd8,0xee,0x24,0x6c,0x8f,0x4a,0xcd,0xd1,0xa8,0x74,0x29,0xba,0x6c,0xbf,
-0xb4,0x1c,0xb3,0x37,0xc6,0x62,0xb6,0xc6,0x18,0x6d,0x5f,0x8a,0x2d,0x4b,0xcd,0xcb,
-0xcb,0x52,0xcb,0x72,0xd4,0x61,0x8a,0x42,0x44,0x9c,0x6d,0x11,0xc0,0xf6,0xb0,0xeb,
-0x32,0x85,0xbb,0x43,0x89,0x4e,0x39,0x00,0xcb,0x15,0x1c,0x87,0x7c,0xbb,0x57,0x59,
-0xb9,0xbc,0x3b,0x60,0x39,0xe4,0xde,0x01,0xd7,0x17,0x1d,0xdd,0x8b,0x1f,0xdc,0xac,
-0xff,0xe0,0xe8,0xd1,0x5d,0x47,0x8d,0x7a,0x39,0x70,0x7f,0x0a,0xdf,0xbb,0xe2,0xde,
-0x85,0x7e,0x38,0xa6,0xdf,0xbe,0xec,0xeb,0x43,0x0d,0x99,0x15,0x1f,0x61,0x78,0x6c,
-0xba,0x37,0x86,0x75,0x72,0x5f,0x77,0x1c,0x56,0x0a,0xc8,0xb3,0x53,0xae,0x9d,0x3c,
-0xd0,0xfb,0x56,0x28,0xef,0xde,0xa7,0x6a,0xb8,0xa3,0x07,0x8b,0xd2,0xe7,0xce,0xee,
-0x4f,0x59,0x4c,0x53,0xa0,0x27,0x23,0x7a,0xb1,0x6c,0xdb,0xf2,0xd2,0xb6,0xfe,0x9e,
-0xc3,0xfd,0x93,0x77,0xda,0x27,0xb1,0x3f,0x1e,0x7a,0xe0,0xfc,0xd0,0xfb,0x36,0x80,
-0x78,0x0e,0xbd,0x70,0xc0,0xcd,0xc9,0x47,0xad,0x3f,0x91,0x9a,0x96,0x31,0x7c,0x5a,
-0xc1,0x70,0xe4,0xe9,0xfd,0x88,0xdf,0xc4,0xdd,0x95,0x98,0x65,0x5c,0xdd,0xac,0xf4,
-0xba,0x9b,0x53,0x3c,0x6f,0x47,0xdf,0xd4,0x19,0x9a,0x31,0x87,0xe7,0x62,0x9e,0xbe,
-0xd8,0x27,0xbf,0xbe,0xf0,0xc9,0x7b,0xff,0x55,0xf9,0x5e,0x58,0xea,0x0d,0x6b,0xcf,
-0x29,0x33,0xe8,0xb0,0xcd,0x63,0xb7,0xbf,0x6f,0x1d,0xe6,0xd8,0xfe,0xea,0xeb,0xf9,
-0xeb,0x57,0xbe,0xae,0xaf,0xc0,0x97,0xed,0x2b,0x5f,0xe7,0x57,0xe4,0xa7,0x4a,0xbd,
-0xf1,0xbc,0x9e,0x0c,0xe8,0xc2,0x1d,0x2a,0xca,0x3a,0xf4,0xf2,0xae,0xac,0x97,0xe1,
-0x3b,0x0b,0xbe,0xbb,0x44,0x6d,0x19,0x55,0x1f,0xae,0x40,0xc3,0x71,0x7e,0x96,0x0d,
-0xb0,0x9b,0xc7,0x6d,0x9d,0x37,0x5d,0x8e,0xd6,0x0b,0x9f,0x36,0xf3,0x0c,0xdf,0x31,
-0xd9,0xa4,0x81,0x24,0xf2,0x6a,0xa3,0x5a,0x79,0xc6,0x9a,0xbb,0xd1,0xb5,0xa2,0x72,
-0xc2,0xea,0xce,0xe1,0xe7,0x44,0x4d,0x83,0x2e,0x10,0xfd,0xcf,0x7d,0xde,0x9f,0x97,
-0xe9,0x1d,0xfc,0xb5,0xac,0xc1,0x75,0x6d,0xa6,0xb7,0x88,0xd7,0x29,0xe2,0xdf,0x67,
-0xf4,0x58,0xa6,0x1f,0xc6,0xff,0x5e,0xfe,0xff,0x66,0xfb,0x7c,0xef,0xde,0xec,0xbd,
-0x3f,0xbb,0x91,0x83,0x7e,0xa9,0x3c,0x2f,0x4f,0x8b,0x3b,0x3c,0x9e,0x93,0xbf,0x1a,
-0x62,0xb9,0x52,0x3b,0x67,0xde,0x6a,0xb8,0xde,0x86,0x75,0x9b,0xce,0x8f,0x45,0x97,
-0x6f,0xe7,0x6b,0xf8,0x39,0xe9,0x3d,0xe9,0x46,0x78,0x6e,0x58,0x37,0x37,0xd2,0x77,
-0xe5,0x67,0xcc,0x99,0xbe,0x2b,0x87,0xe7,0x4c,0xb3,0x1d,0x39,0xfa,0x0e,0xe2,0xe8,
-0xe6,0xb6,0x7c,0xf3,0xc8,0xe7,0xfb,0x47,0x50,0xb7,0xfd,0x5e,0xa9,0x4d,0x1a,0x2c,
-0x95,0xa4,0xc1,0x03,0x6a,0xd8,0x07,0x0f,0xd8,0x69,0x46,0xed,0xe5,0x47,0x0f,0x2d,
-0xa0,0x2b,0x43,0xfe,0x6a,0x88,0xeb,0x16,0x98,0x5b,0x3b,0x4a,0xba,0x32,0xf7,0x41,
-0x4f,0xe6,0xd8,0x24,0x9b,0x3d,0x27,0x2c,0x27,0x3d,0x19,0x56,0x3f,0x47,0x3f,0x96,
-0xa7,0xe1,0x35,0xcb,0x35,0x6d,0x52,0xf4,0x85,0xb8,0xfe,0x7f,0x7e,0x26,0x54,0xac,
-0x89,0x89,0xf9,0x77,0xd8,0x6f,0x05,0xf9,0xd9,0x05,0xdf,0x7b,0x6d,0xdf,0xf7,0x26,
-0x07,0x4f,0x4f,0x6a,0x5a,0x71,0xe7,0x10,0xc7,0x09,0xcf,0x2b,0x1d,0xe8,0xad,0x36,
-0x56,0xa9,0x6e,0x43,0xfd,0x1c,0xf4,0xdb,0xdd,0xe3,0x95,0x6e,0xea,0x71,0xaf,0x40,
-0xdd,0xd7,0x99,0xd1,0xb3,0x33,0xfe,0xb1,0x73,0x7e,0xe8,0x83,0x83,0xba,0x39,0xf4,
-0xc4,0x79,0x26,0xce,0x7b,0x00,0xcf,0x19,0x96,0x6b,0x51,0x27,0x63,0x7c,0x9d,0xf3,
-0xf6,0xff,0x56,0xdc,0xee,0xbc,0x5c,0xdc,0x99,0x97,0x97,0x93,0xf7,0xb4,0x63,0xff,
-0x45,0xdc,0x74,0xd7,0xae,0x06,0xd8,0xc3,0x6e,0x30,0xaf,0x36,0x78,0x8b,0xf4,0x64,
-0x00,0xcb,0x29,0x5a,0x66,0x41,0xf3,0x15,0xbc,0xd5,0xc2,0x8f,0xea,0xc2,0x90,0x77,
-0xd7,0x74,0x5e,0x65,0x3c,0x77,0x68,0x7e,0x2c,0x98,0x63,0xe7,0x7a,0xe1,0x16,0x24,
-0xd3,0x02,0x7a,0xa1,0x4b,0x2d,0x4b,0x50,0x43,0x07,0x2c,0x87,0x80,0x9a,0xf9,0x8a,
-0xad,0x61,0x25,0x3e,0x55,0x1f,0x8f,0x4d,0x35,0xc4,0xa0,0x6e,0xae,0xf1,0x74,0x99,
-0x8f,0x3b,0x4c,0xc1,0x65,0x5b,0xd3,0xf2,0xaa,0xb5,0x61,0x15,0x30,0x3c,0x66,0x6f,
-0x8a,0xad,0xda,0x2e,0xe0,0x76,0x54,0x6a,0x89,0xae,0xd8,0x9b,0x56,0x56,0x6d,0x17,
-0x57,0x61,0x8d,0x49,0xcd,0x31,0xc4,0x75,0x27,0x61,0x7a,0xc4,0xd9,0x1e,0x01,0x3c,
-0x8f,0xb8,0x3a,0x22,0x0c,0xcf,0x81,0xab,0x6b,0x98,0xde,0x15,0x56,0x71,0x1d,0xf8,
-0x39,0x62,0x79,0x77,0x38,0xe2,0xed,0x89,0x44,0x3c,0x3d,0x11,0xe2,0xea,0x3d,0x61,
-0xff,0x54,0xa7,0xff,0xed,0x37,0xcf,0xbd,0xbd,0x6d,0x5b,0xfe,0x36,0x35,0x2f,0x94,
-0xa5,0xef,0x8f,0xe2,0x39,0x84,0x78,0xdb,0xbf,0xaf,0x68,0x3f,0xf6,0xc3,0x21,0x3f,
-0x07,0x2d,0x19,0xe8,0x67,0xef,0x55,0xb8,0x79,0x2f,0xce,0xad,0xe1,0xec,0x39,0x46,
-0xd7,0x1a,0xd3,0x92,0x59,0xf3,0x81,0x9e,0x4c,0x77,0x1c,0x56,0xd4,0x85,0x93,0x1f,
-0x4f,0x78,0x3b,0x95,0xda,0x79,0x57,0x22,0xe1,0xeb,0xc2,0xfa,0x39,0x45,0x4f,0x42,
-0xb2,0x34,0x4b,0xc7,0x4b,0x73,0x8f,0x33,0x7d,0x72,0x9a,0x57,0xcb,0xde,0xd9,0x54,
-0x57,0xdc,0xf4,0xc5,0xef,0x1a,0xbf,0x88,0x79,0xfb,0x62,0x6b,0x7e,0xf3,0xda,0x9a,
-0xbf,0x1f,0x79,0x38,0x6e,0xcf,0xc0,0x7d,0xf3,0x1a,0xe4,0xd8,0x89,0x9b,0xf7,0x25,
-0x91,0x97,0x63,0x00,0xae,0xf7,0x26,0xa9,0xcf,0x0d,0xb8,0x7a,0x7f,0x0a,0xb0,0x1d,
-0x56,0x8c,0x99,0xbe,0xd4,0xfa,0x74,0xcf,0x3a,0xf5,0xc3,0xf5,0x60,0x9f,0x3a,0xf3,
-0x64,0xa1,0xe8,0xc7,0x1e,0x39,0xe0,0xd1,0x93,0x5f,0xb4,0x4c,0x76,0x99,0x0e,0x77,
-0x5d,0xff,0x41,0xf9,0xf5,0x98,0xab,0x2f,0x06,0xb8,0x8d,0xf8,0xed,0x37,0x0b,0xba,
-0x31,0x66,0x9a,0x57,0x03,0x2c,0x9f,0xee,0x46,0x2c,0x7f,0xe2,0xeb,0x7c,0x02,0x73,
-0x6e,0x4f,0xbc,0x9d,0x4f,0x10,0xcb,0x15,0x6f,0xf4,0x75,0x6f,0xf7,0xfa,0x2f,0xde,
-0xae,0xfc,0xc5,0xe9,0x43,0x5b,0x4e,0xab,0xd8,0x5d,0x98,0xb5,0x97,0xe1,0xb6,0xda,
-0xdb,0x9f,0xc7,0xf5,0xf6,0xcb,0x21,0xe6,0xcf,0xf9,0x3e,0xf7,0x4c,0x33,0x6b,0x1b,
-0xd5,0xae,0xd5,0xd9,0x72,0x91,0x47,0x1b,0xd5,0x7f,0xb3,0xf4,0x8f,0x89,0xcf,0x65,
-0x3a,0x57,0x9f,0xf7,0x24,0x37,0xc2,0x42,0xfe,0x77,0x6f,0xc4,0x77,0x0d,0x7e,0x9c,
-0xe1,0xf1,0x9d,0x96,0x27,0x10,0xf0,0x93,0x7f,0x8d,0xd1,0xeb,0x8d,0x7e,0x96,0xee,
-0x6f,0xe3,0xfb,0x56,0x84,0x7e,0xb9,0x4c,0xab,0xf8,0x7a,0x11,0x3b,0x54,0x7e,0xfe,
-0x27,0xe2,0xe7,0x80,0xe7,0xe0,0x83,0x6e,0x8c,0xeb,0x5b,0xf4,0x1c,0x1d,0x7a,0xdd,
-0xef,0x14,0x20,0xbe,0x5b,0x6e,0x83,0x6f,0x6a,0xa1,0xe2,0x9b,0xca,0x82,0xfc,0x52,
-0x2d,0xb7,0xb7,0x5b,0x70,0x5e,0xad,0x4e,0x99,0x57,0x13,0xf3,0xc7,0xc2,0xb1,0x25,
-0x72,0x76,0x9e,0x9f,0xab,0x79,0x77,0x83,0xfc,0x32,0xfa,0xa9,0x29,0x39,0x77,0x08,
-0x15,0xd3,0xe5,0xeb,0x55,0xc4,0xf3,0xad,0x1a,0x9e,0x83,0xee,0xb1,0x86,0xe7,0x79,
-0xe6,0xd1,0x5b,0xfb,0x47,0xed,0xf7,0xf6,0xdb,0xa5,0x7b,0x90,0x6b,0x2f,0x71,0x40,
-0x8e,0x5d,0xba,0x57,0x2a,0xd9,0x86,0x0e,0x60,0xed,0x9c,0x66,0xd1,0x49,0x13,0x0e,
-0x7b,0xe2,0x2c,0x87,0x91,0xa7,0xe3,0xbc,0xda,0x7d,0x65,0x5e,0x0d,0xb5,0xe2,0x58,
-0x8f,0xfb,0x71,0xd2,0x93,0x51,0xf5,0xe1,0x38,0x7f,0x35,0xb1,0x0f,0xce,0x40,0xa7,
-0xdd,0x70,0xfe,0xf0,0x59,0x7a,0x08,0x0d,0xfc,0x6a,0x0e,0x14,0x6f,0x3e,0xf0,0xee,
-0x3b,0x87,0xde,0xb5,0x0f,0x9f,0xb1,0x6b,0x7a,0xaf,0x67,0x49,0xef,0x75,0x8c,0xf9,
-0xb1,0x54,0xb8,0x40,0xef,0x15,0xeb,0xe8,0xe3,0xa0,0xfb,0x4a,0x7e,0x2c,0x4c,0x43,
-0x06,0x6a,0xe8,0x80,0xef,0x80,0xe3,0xae,0x09,0xf9,0x3e,0xcc,0x9e,0xab,0x6b,0xad,
-0x1a,0x90,0x77,0x27,0x7e,0x0e,0x3c,0xbd,0xce,0xed,0x1c,0xaf,0x75,0x7e,0xf4,0xc1,
-0xe9,0x8f,0xca,0x4f,0x15,0x96,0x67,0xc3,0x7f,0xfd,0x6d,0xdc,0xd8,0x75,0xac,0xc8,
-0x35,0xb3,0xb5,0x73,0x88,0xe6,0xcf,0xeb,0x75,0x7a,0xaf,0xac,0x8e,0x8e,0x1a,0xee,
-0xb6,0xe6,0x79,0x4d,0x23,0x4e,0xcc,0xb5,0x2b,0x1e,0x6b,0xf2,0x36,0xe9,0xb8,0xb7,
-0x6b,0xf3,0x6a,0x4e,0xad,0xcf,0x3d,0x20,0xb5,0x04,0x56,0xac,0xf5,0x2b,0xc9,0x47,
-0x35,0xc9,0xb5,0x47,0x35,0x6b,0x2b,0x53,0x0d,0x2b,0x11,0x7b,0x53,0x04,0xb8,0x3a,
-0xd4,0xd4,0x11,0xd3,0x9d,0xed,0x01,0xc8,0xbb,0x47,0xa4,0xe6,0x08,0xd4,0xd2,0x83,
-0xce,0xf6,0x20,0xf4,0xba,0x43,0xed,0x1c,0x72,0xeb,0xc0,0xd1,0x13,0xd6,0xfa,0xc4,
-0x9a,0xb5,0x61,0x6d,0xd5,0xde,0xb8,0x8a,0x7c,0xdd,0xd1,0xaa,0x60,0x7a,0x3b,0xf1,
-0x74,0x27,0xf0,0xf4,0x0e,0x25,0x3a,0x69,0x45,0xae,0xde,0x19,0x8e,0xb8,0xbb,0x22,
-0x80,0xeb,0x6c,0x0d,0x7b,0xbb,0x28,0xef,0xee,0x21,0x5c,0x47,0x4c,0x97,0x71,0xfe,
-0xfe,0x17,0xad,0xf7,0x1b,0x2f,0x96,0x36,0x1a,0xe5,0x46,0xf9,0xef,0x24,0xa3,0xdd,
-0xbd,0x7f,0xdf,0x6e,0xc4,0x73,0xa6,0x0d,0x87,0x9e,0xa8,0xde,0x6e,0xc4,0x71,0x98,
-0x43,0x8f,0x7b,0xba,0xe2,0x09,0x57,0x47,0x22,0xe9,0x6a,0x4b,0x26,0xdd,0x72,0xb8,
-0x40,0x23,0xee,0x72,0x82,0xcd,0xa2,0x01,0xc6,0x03,0x8e,0x83,0x5e,0x7b,0xca,0xd3,
-0x96,0x5a,0x77,0xb7,0xab,0x9a,0xed,0xea,0xbc,0x9a,0x8c,0xf1,0xd2,0xd0,0x25,0xe9,
-0x95,0x83,0xb9,0xaf,0xf0,0x3a,0xa7,0x65,0xc7,0xb6,0x95,0xdd,0xfc,0xef,0x9a,0x9b,
-0x21,0x47,0x6f,0x08,0x38,0x3c,0xe1,0x77,0xbf,0x82,0xe9,0x84,0xe1,0x18,0xd3,0x7d,
-0x09,0xc4,0xee,0xe9,0xee,0xd4,0xba,0xaf,0x7b,0x3d,0xe5,0xeb,0x4e,0xc1,0x4c,0xda,
-0xba,0xaf,0x6b,0xfd,0xcf,0xde,0xae,0x3f,0x03,0x76,0x02,0x66,0x03,0xce,0xa3,0x87,
-0x9a,0x8c,0xef,0xeb,0xd3,0xfd,0x38,0x6f,0x86,0xbd,0xed,0x32,0xf6,0xab,0x18,0x0e,
-0xba,0x32,0x4a,0x9f,0x3b,0xf0,0xf4,0xd9,0x89,0xae,0xd9,0x81,0xee,0xe3,0x03,0xe7,
-0x4e,0x17,0x9d,0xfb,0xc3,0xaf,0x9b,0xff,0x90,0xf0,0x0f,0x24,0x34,0x7e,0x0e,0xf3,
-0x6c,0xfd,0x4a,0x7f,0xbb,0xc2,0xcd,0x51,0x33,0x8e,0xe9,0xc4,0x29,0x5a,0x71,0x7e,
-0x05,0xeb,0xe5,0x60,0x9a,0x72,0xcc,0x5f,0x8d,0xf5,0xb7,0x8b,0x1a,0x31,0x46,0xda,
-0x30,0xec,0x7b,0x54,0xa7,0xc1,0xc5,0xf5,0x18,0xf0,0xdf,0x3b,0x86,0xf9,0x41,0x01,
-0x3b,0x44,0xee,0x68,0xc8,0x4f,0x05,0x7e,0xad,0xc3,0x21,0xf6,0x52,0x1e,0x5f,0xc5,
-0xa3,0x48,0xe0,0xd1,0x69,0x7f,0x4f,0xd6,0x06,0xef,0x15,0x8e,0xcd,0xaf,0x7b,0xdd,
-0xa0,0xfb,0x5f,0x44,0x2c,0x15,0x7f,0x87,0x51,0x9d,0x40,0xd8,0x67,0x3a,0x7c,0xde,
-0xa0,0xee,0xad,0xcb,0x6b,0x64,0xa5,0xeb,0xb1,0xf0,0xe7,0xe3,0xd3,0x7a,0xa4,0xe1,
-0x73,0xde,0xb7,0x2f,0x6b,0x1f,0xd4,0xcf,0xf5,0xf3,0x6a,0xb9,0xba,0x79,0xb5,0x74,
-0xff,0xf3,0x2d,0xc4,0xcf,0x65,0x6e,0x0e,0x78,0x0e,0x58,0xae,0xf1,0x73,0xbd,0xff,
-0xb9,0xe5,0xae,0x8c,0xe9,0x77,0x29,0xdf,0xae,0xfa,0xa5,0x6e,0x4a,0x8f,0x8d,0xea,
-0xea,0x62,0xcf,0x3b,0xab,0xa9,0xf3,0x33,0x67,0x69,0x7e,0x2c,0xb9,0x4a,0xee,0x3d,
-0x4f,0xaf,0xef,0x8a,0x1a,0xaf,0x05,0x59,0xbb,0xf7,0x6c,0xa5,0x5a,0x3a,0xe0,0x7a,
-0x5f,0x5b,0x5e,0xdf,0xc8,0xad,0x92,0x11,0xca,0xb7,0x97,0xda,0x01,0xc7,0x81,0xa3,
-0x43,0x2f,0x1c,0xea,0xb8,0x0f,0x52,0x0f,0xdc,0xa4,0x85,0x7c,0x59,0x40,0xc7,0x9d,
-0x7c,0x52,0x0f,0x2b,0xb8,0x4e,0x5e,0xe8,0x30,0xb3,0x06,0x39,0x77,0xd0,0x71,0x87,
-0x3e,0x38,0xc8,0xb7,0x43,0xfd,0x1c,0x78,0x3a,0xf2,0x73,0x65,0x5e,0x2d,0x6d,0xde,
-0x80,0xd7,0x53,0xcc,0x4e,0xef,0x13,0x14,0xf5,0xf8,0x33,0x79,0xc3,0xf2,0xd7,0x33,
-0xac,0x87,0x00,0x62,0x57,0x61,0xd6,0xae,0x86,0xaa,0x82,0x86,0xbb,0xbf,0x3f,0x71,
-0x17,0x35,0x65,0x46,0x48,0x53,0xc6,0x33,0x72,0x46,0xd1,0x95,0x29,0xf7,0x82,0x0e,
-0x1c,0xce,0xa3,0x8f,0x96,0xfb,0x21,0x66,0x46,0xca,0x67,0x68,0xee,0xbc,0xd2,0x03,
-0x38,0x0e,0xbd,0x70,0xa0,0xdf,0x4e,0xb8,0x0e,0xdc,0xfc,0x3c,0xea,0xbf,0x7a,0x27,
-0xaa,0xbd,0xd0,0xd3,0xee,0x99,0xa8,0xf1,0xb8,0x27,0x6a,0x31,0xff,0x0e,0x2b,0x60,
-0x3a,0x45,0x9d,0x5b,0x1a,0xad,0x95,0xde,0xfa,0xcf,0x63,0x6f,0xed,0xda,0xf9,0xed,
-0xe4,0xdd,0xd3,0xce,0x55,0x56,0xa3,0xe0,0xfa,0x7a,0x71,0x5e,0x8d,0xf3,0x3f,0x67,
-0x39,0xf7,0x59,0x89,0x66,0xd0,0x31,0xc7,0x6e,0x37,0xcd,0xa9,0xdc,0x5c,0x87,0xe9,
-0x0c,0xcb,0xd3,0xb5,0xe1,0xd0,0x5b,0x0d,0xf5,0x64,0x2e,0x2f,0x40,0x7f,0x1c,0xf4,
-0xbd,0xc1,0xbc,0x1a,0xe4,0xdf,0x57,0xa6,0xea,0x57,0x22,0xb6,0x4b,0x11,0xe8,0x75,
-0x07,0x2c,0x87,0xba,0xf9,0xa2,0xab,0x63,0x11,0xe7,0xd3,0xa0,0x1f,0xce,0xc9,0xe6,
-0xd4,0x68,0x0d,0x3a,0x3b,0x82,0xc0,0xd7,0x93,0xd6,0xda,0x24,0x60,0x3a,0xf4,0xda,
-0xad,0xd8,0x2f,0x21,0x4f,0x5f,0x91,0x9a,0x57,0x62,0x8e,0x16,0x19,0xdb,0x4d,0xcb,
-0x18,0xce,0xb6,0xe5,0x98,0xa3,0x15,0xb1,0x1e,0xb6,0xa3,0xae,0xf6,0x68,0xd4,0x75,
-0x39,0x1a,0xf5,0x74,0x44,0x23,0xee,0x4e,0x99,0x8f,0x03,0x9e,0xcb,0x18,0xee,0xe9,
-0x8e,0x20,0x47,0x97,0xf9,0x39,0xc3,0xf3,0x88,0xaf,0x37,0xf2,0xd8,0xde,0xfd,0xf8,
-0xc7,0xd7,0xcf,0xfd,0xb8,0x60,0x6b,0xbe,0x3a,0x93,0xf0,0xac,0xfc,0x69,0x5f,0x31,
-0x9b,0x57,0x53,0xf8,0x39,0xe4,0xdb,0x51,0x53,0x46,0xc6,0x75,0x9f,0x8c,0xe7,0xa0,
-0xdf,0xee,0xed,0x8c,0xc3,0x3c,0x1a,0xe8,0xbd,0xae,0xbb,0x60,0x16,0xad,0x8d,0x66,
-0xcd,0x51,0x9f,0xbd,0x23,0x91,0xf0,0xc8,0x5c,0x5c,0xc6,0x74,0xe4,0xe5,0xde,0xee,
-0x04,0xf2,0xf5,0x69,0xf2,0x57,0x63,0xdb,0x5f,0x7e,0xdc,0xf4,0xe5,0x81,0xe2,0xdc,
-0x03,0xe8,0x6b,0x2e,0x1f,0xeb,0xc5,0xbb,0xb7,0x14,0xbf,0xf9,0xfa,0xd9,0x37,0x17,
-0x6c,0x3d,0x0b,0x71,0xff,0x95,0x38,0xcc,0x96,0xd3,0x2c,0xf9,0x00,0xf2,0x71,0xc4,
-0x76,0x9c,0x3d,0x37,0xab,0x81,0x3c,0x5d,0x09,0xcc,0xa3,0xfb,0xfb,0x52,0x6c,0x16,
-0x8d,0x71,0x73,0xad,0x86,0xae,0x5f,0xa9,0x96,0xae,0xe9,0xbd,0x42,0x5d,0x7c,0x65,
-0xfa,0xca,0xca,0xeb,0xff,0x5a,0xf1,0xfa,0xae,0x1d,0x5b,0x76,0xbd,0x76,0xf5,0xd4,
-0x6b,0x4b,0x92,0x79,0x89,0x3c,0x56,0xae,0xa4,0x58,0x0f,0x1d,0xeb,0x57,0x67,0xa1,
-0x7a,0xa0,0xcf,0x5d,0x53,0x7a,0xe1,0xae,0xa9,0x7d,0x70,0x5a,0x9f,0xdc,0xb5,0x24,
-0xf4,0x00,0xdc,0xb8,0x5e,0x77,0x03,0xfa,0xfc,0x36,0xd2,0x6f,0xd3,0xd5,0xad,0x8d,
-0x7a,0xcb,0x32,0x68,0x8e,0x6e,0x84,0x1b,0x46,0x8f,0xf3,0xcf,0x19,0x71,0x43,0x43,
-0xae,0x9e,0x65,0x80,0x63,0x3c,0xdf,0x15,0xb8,0xaa,0xee,0x1a,0x92,0xc7,0xd6,0x4c,
-0xe7,0x76,0x26,0xec,0xce,0xce,0xfc,0x9a,0x67,0x79,0x3f,0xcf,0x95,0x33,0x5d,0xeb,
-0xf0,0xef,0x61,0x7f,0x3b,0x7f,0x5f,0xfd,0xbf,0xb2,0xf5,0xdb,0x46,0xfb,0x45,0xfc,
-0x3c,0x36,0xc4,0xef,0x4d,0x7a,0x7d,0x16,0x3e,0x6f,0xab,0xce,0xab,0xfd,0x89,0xcd,
-0xab,0x6d,0xe6,0x66,0xd4,0xf4,0xfc,0x7c,0xf0,0x76,0xfe,0xa0,0xca,0xcf,0xef,0x40,
-0x14,0x28,0xb9,0xf7,0xad,0x43,0x2c,0xcf,0x3e,0x74,0x87,0x38,0x3a,0xad,0xdb,0x2c,
-0x14,0xc4,0xcf,0xd1,0x8f,0x45,0xb8,0x7e,0x31,0xfa,0xbb,0x75,0xf9,0x64,0x03,0xce,
-0x2a,0xe6,0x8b,0xd4,0x9c,0x7c,0x8e,0x30,0xd3,0xa6,0xe0,0xbc,0xea,0x9b,0xaa,0xf8,
-0xb2,0xa8,0xfd,0x72,0x32,0xc6,0x43,0xde,0xaa,0xa3,0x25,0x0f,0xf5,0x5e,0xc9,0xf7,
-0xbc,0x74,0x8a,0x79,0xa5,0xa2,0xa6,0xcc,0xd0,0xcb,0xa8,0xe7,0x0e,0x58,0xfe,0x70,
-0xf0,0xf0,0x43,0x95,0x9b,0x0f,0x29,0xfd,0xed,0x7c,0x8f,0xbb,0xe5,0x88,0xd5,0x6a,
-0x39,0x8c,0xf3,0x6a,0x80,0xe3,0x84,0xe9,0xc7,0xa7,0x00,0xcb,0x19,0x9e,0xef,0x29,
-0x7a,0x69,0x8f,0xf8,0x19,0xea,0x3e,0x3f,0xc1,0xa7,0xc6,0x08,0xd7,0x79,0x5f,0x39,
-0xdd,0xf5,0x0b,0x68,0xdf,0x29,0x7d,0x80,0x7c,0x2e,0x02,0x7a,0xff,0x0e,0xed,0xcd,
-0x3e,0xf4,0x9d,0xde,0x9d,0xdf,0x99,0xfc,0xfc,0xc4,0xe4,0xf4,0xf0,0xa9,0xe9,0x99,
-0xe1,0x93,0x33,0xb3,0xc3,0x65,0xb3,0x73,0x0f,0xca,0xe6,0x1e,0x0f,0xbf,0xf2,0x18,
-0xe3,0xc1,0xc9,0xc7,0xf3,0xc3,0x27,0xe7,0x61,0x5d,0x18,0x2e,0x5b,0x98,0x1f,0x39,
-0x35,0x3f,0x33,0x72,0x66,0x86,0xb4,0x5e,0xcf,0x23,0x4f,0x27,0x0d,0x77,0x0a,0x96,
-0x6f,0x07,0x2d,0x19,0xd0,0x8b,0x03,0x4c,0xf7,0x4c,0x56,0xcb,0x6b,0xb5,0x87,0x70,
-0x5e,0x89,0xc9,0x1a,0xef,0xd4,0x83,0xea,0xa9,0x6b,0x57,0x0e,0x5c,0x93,0x3f,0xa4,
-0xdc,0x0d,0xc1,0xe1,0x05,0xdf,0xf8,0xf3,0x0a,0xaf,0x95,0x60,0x9e,0x4f,0x3e,0x36,
-0x6a,0x2a,0x8b,0x6a,0x1e,0xdc,0xaa,0x79,0x30,0x6f,0x6d,0x9a,0x87,0xd9,0x73,0x98,
-0x57,0x43,0x1d,0x77,0xa9,0x55,0xc1,0x73,0x65,0x0e,0x5d,0x62,0xb3,0xe8,0x7a,0x4c,
-0x67,0x58,0x4e,0x3c,0x5d,0xf0,0x63,0x91,0x34,0x0f,0xf4,0x45,0x47,0xfb,0x22,0xac,
-0xc0,0xc7,0xa1,0x7e,0x0e,0xb5,0x74,0x86,0xe3,0x14,0x97,0x17,0xd9,0xb6,0x3a,0x77,
-0xae,0xcc,0x9e,0x43,0x1f,0x5c,0xdc,0x7a,0x21,0x9e,0x98,0xaa,0x4b,0xc4,0xad,0x17,
-0xe3,0xac,0x96,0x1e,0xb7,0x5d,0x8c,0xaf,0x4d,0xd5,0xaf,0xc5,0x6d,0x8d,0xf1,0x98,
-0xa3,0x39,0x86,0x38,0xee,0x34,0x2d,0xb3,0x35,0xea,0x6c,0x8b,0xb2,0x1c,0x3c,0xf1,
-0x72,0x2d,0xe7,0x8e,0x35,0x74,0x6f,0xaf,0x5a,0x3f,0xd7,0xfa,0xe3,0x7a,0xc3,0x9f,
-0xfe,0xa6,0xe9,0xd3,0x53,0x27,0x8b,0x4e,0xa5,0xcd,0x04,0x67,0x98,0x25,0x62,0xc7,
-0x6c,0x49,0x49,0x51,0x89,0xea,0xc7,0xe2,0x27,0x4f,0x16,0xe8,0x61,0xa7,0xdc,0x7b,
-0x7f,0x0c,0xf9,0xfa,0x34,0x60,0x7b,0xf7,0x0a,0xe6,0xd4,0x65,0x6e,0x0e,0xd8,0x0e,
-0xf8,0xad,0xe9,0xb8,0x83,0xdf,0x5a,0x6f,0x1c,0xbd,0xd7,0x94,0xfe,0x76,0x5c,0xe5,
-0x80,0x9a,0x3a,0x68,0xc3,0x5c,0xed,0x3b,0x71,0xb5,0x30,0x3f,0xa7,0x10,0x3e,0xbf,
-0xed,0x5b,0x73,0xb7,0xbf,0x76,0xe5,0xc4,0x6b,0xf3,0x53,0xdd,0xf3,0xa8,0x11,0xa3,
-0x86,0x39,0xce,0xb8,0x38,0xe4,0xd6,0x61,0x4d,0xf8,0xfb,0x12,0x14,0x90,0x6f,0xef,
-0x57,0xea,0xe6,0x66,0x6d,0xc5,0x7e,0x77,0x73,0x92,0xef,0x87,0xc3,0x5e,0x77,0xbe,
-0x1f,0x0e,0xb1,0x79,0x40,0x0d,0x78,0x6c,0xc5,0x67,0x5e,0x79,0xff,0xdd,0xfa,0xf7,
-0x77,0x14,0x6e,0xde,0x51,0x5e,0xb6,0xa3,0x7c,0xf0,0x56,0xdb,0x20,0x8f,0xe3,0xea,
-0xec,0xda,0x9c,0x36,0xbb,0x06,0x7d,0xeb,0xe4,0xab,0x26,0xaf,0xe0,0xcf,0xa2,0x04,
-0xeb,0x71,0x67,0x8f,0xc3,0x1a,0xf7,0x5f,0x8d,0xff,0xe4,0x7a,0xcd,0x4f,0x60,0x5e,
-0x4d,0xec,0x37,0x17,0x75,0x63,0x32,0x6a,0xc7,0x18,0xe4,0xd6,0x9f,0xa5,0xff,0x7c,
-0x43,0x2e,0x68,0x70,0xcd,0x20,0xe6,0xc2,0x74,0xfc,0x3f,0x03,0xf6,0xeb,0xf8,0xab,
-0x80,0xf9,0x3c,0xce,0xeb,0x10,0xf7,0x29,0x57,0x98,0xcf,0xc5,0xc5,0xd9,0xcf,0xcf,
-0x4a,0xcf,0x47,0x64,0xe4,0xfb,0xd9,0xc6,0xcf,0x19,0x61,0xb4,0xe1,0xe3,0xe2,0x7e,
-0xca,0x32,0xd8,0x7f,0x99,0x30,0x7d,0x03,0xef,0x1b,0xc6,0x53,0xb4,0x79,0xb5,0x5c,
-0x65,0x5e,0x6d,0x33,0xcd,0xab,0xdd,0x16,0xe7,0xd5,0xf2,0x2d,0x62,0xbe,0x9d,0xb0,
-0xbc,0x60,0x88,0x71,0x73,0xc2,0xf5,0x74,0x2c,0x67,0xfd,0x70,0x0d,0xb5,0x39,0x0d,
-0x6c,0x1f,0xa6,0x7d,0xc6,0x19,0x70,0xde,0xf0,0x3a,0x45,0x98,0xe5,0x32,0xca,0x4f,
-0xa7,0xf9,0x33,0x70,0xde,0x25,0x62,0xfd,0xbd,0xb5,0x29,0xbf,0x75,0xe8,0xf3,0x92,
-0x21,0xf0,0x62,0x81,0x00,0x1c,0x87,0xfc,0x3a,0xe8,0xc8,0x4c,0x0c,0xbd,0x3c,0x31,
-0x31,0x74,0x48,0x89,0xc3,0x13,0xa8,0xdb,0xae,0x68,0xb7,0x63,0x0d,0x1d,0x71,0xfd,
-0x88,0x8c,0xe9,0x5a,0x7f,0x3b,0xfa,0xac,0xdd,0x3f,0xf6,0x10,0x30,0xdd,0x88,0x9f,
-0x1b,0xe6,0x5c,0xb2,0xf4,0xdf,0x91,0xea,0x75,0xf5,0xa6,0x74,0xcd,0x00,0x1e,0xdf,
-0x55,0xbe,0xae,0xfc,0x5f,0x6a,0x2f,0x81,0xa2,0x6b,0x0b,0xf9,0x08,0x86,0xeb,0x27,
-0x0f,0x6d,0x3e,0x79,0xe3,0x3f,0xf6,0xdf,0x90,0xee,0x96,0x49,0x88,0xe7,0x23,0x27,
-0x67,0xe7,0x86,0x65,0x3c,0x7f,0xf0,0xca,0xe3,0x85,0x07,0xaf,0x2c,0x00,0x86,0x3f,
-0x1e,0x3e,0xf9,0x78,0x71,0xb8,0x6c,0x71,0x69,0xb8,0x6c,0x09,0x02,0x30,0x1d,0x78,
-0x3a,0xe6,0xda,0x31,0xaa,0xdc,0x0c,0xbf,0xb5,0x7c,0x3b,0xf5,0xc4,0x61,0x8e,0x7d,
-0xa2,0xc6,0x0d,0xe1,0x99,0x04,0x6c,0xaf,0xf1,0xf8,0x26,0x6b,0x7c,0xbe,0x87,0x35,
-0x3e,0xf7,0xc3,0x3a,0xb7,0xe5,0x8f,0x55,0x96,0x8a,0x8a,0x9d,0x15,0xf4,0xef,0x7f,
-0xcb,0x37,0xe5,0x37,0xc2,0xbe,0x85,0xfd,0x56,0x5d,0xb1,0xbb,0x1a,0xe6,0xd5,0x02,
-0x8f,0xea,0x02,0x4b,0xd6,0x0b,0x4b,0x30,0xab,0x86,0xde,0xe7,0xf2,0x4a,0xf3,0xe8,
-0x1c,0x9e,0x33,0x5e,0x0e,0xb3,0x6b,0xa8,0xdb,0x4e,0x5e,0x2c,0x1a,0x4f,0x07,0x5e,
-0x6e,0x5a,0x60,0xf5,0x74,0x98,0x43,0x67,0x1e,0xe8,0x14,0x97,0x17,0xfe,0x8f,0xbd,
-0x2b,0x7f,0x6a,0xe3,0xce,0xf2,0x80,0xc1,0x5c,0x3e,0x89,0x63,0x83,0x30,0x87,0xb1,
-0xe3,0x18,0xdb,0xc4,0x98,0x43,0x9c,0x06,0x21,0x6e,0x63,0x6c,0xe3,0xaa,0x6c,0x6a,
-0x37,0x5b,0x59,0x57,0x6d,0xa6,0x5c,0xa9,0xca,0x78,0x7f,0xd8,0x8c,0xc7,0xb1,0x9d,
-0x49,0x32,0xd9,0xa9,0x9a,0x5a,0x7b,0xa6,0x26,0x47,0x65,0x92,0x4a,0x79,0x52,0xb6,
-0x71,0x10,0x98,0x43,0x9c,0x42,0x07,0x12,0x42,0xdc,0x87,0x41,0x12,0x92,0x0c,0x24,
-0xf3,0xb7,0x6c,0xbf,0xf7,0xfa,0xdb,0xfd,0xed,0x56,0x0b,0xb0,0x93,0x4c,0x6a,0x6b,
-0xb7,0xab,0x5e,0x7d,0x5b,0x8d,0x38,0x24,0x35,0xfd,0xe9,0xcf,0x7b,0x9f,0xf7,0x79,
-0x73,0xf6,0x5a,0xc2,0x6e,0x3b,0x61,0xf7,0xac,0xbd,0x6e,0x96,0x61,0xb8,0x84,0xe5,
-0x8e,0x7a,0x89,0x9f,0x43,0x9f,0xf9,0x92,0xad,0x86,0x74,0x72,0xb6,0xaa,0x95,0xa7,
-0xb6,0x1a,0x51,0xcf,0x5e,0xbb,0xe4,0xb3,0x55,0xfa,0x02,0xa3,0xe5,0x01,0xaf,0xad,
-0x0a,0xb9,0xf8,0xb2,0xa3,0x76,0x19,0x63,0x0c,0x30,0x1c,0x6a,0xe8,0x62,0xed,0x7c,
-0xac,0xf1,0xa9,0xd4,0x87,0x8e,0x1a,0x38,0xb1,0x5f,0x6d,0x5c,0xc4,0xf3,0x71,0xc2,
-0xf3,0x15,0x57,0xe3,0x8a,0xd7,0xd9,0xe0,0x1d,0x31,0x55,0x8f,0x5c,0x68,0xd4,0x5d,
-0x08,0xcb,0xeb,0x72,0x33,0xb8,0xc2,0xf4,0x52,0xc2,0xb9,0xa9,0x4b,0x4b,0xd1,0x51,
-0xff,0xb9,0x38,0x5f,0x0d,0x7a,0xd4,0xdc,0xd4,0xa3,0x26,0xfb,0xc9,0x5c,0xf0,0xe1,
-0x5c,0x73,0x9c,0x89,0xda,0x28,0xce,0x47,0x6d,0x08,0xb0,0x39,0x6b,0x50,0x2b,0x07,
-0x5c,0x0f,0xb9,0x60,0x56,0x6a,0x13,0x71,0x72,0xd1,0xe7,0x35,0x30,0x7e,0x3e,0xf0,
-0xe5,0xdd,0xd2,0x2f,0x5f,0xc9,0xde,0xf5,0x0a,0xe4,0xdb,0xf6,0x24,0xc5,0xec,0x31,
-0x54,0xa4,0x1b,0x06,0x4d,0xc6,0x41,0x96,0x63,0x97,0x7c,0xe0,0x26,0x5a,0x82,0x30,
-0x2b,0x7d,0xc3,0x55,0xbf,0xb1,0xe1,0xaa,0xdd,0xd8,0x70,0xd6,0x6e,0xac,0xbb,0xea,
-0xd6,0xd7,0x5d,0xf5,0xeb,0xe0,0xed,0x06,0xf9,0x75,0xc8,0xb5,0x53,0x6e,0xbd,0x69,
-0x8d,0xe2,0xbc,0x18,0xac,0x6e,0x2e,0xae,0x13,0xfc,0xe3,0xf3,0x6b,0xcc,0x03,0x0e,
-0xea,0xe8,0xcf,0x5c,0x4d,0xcf,0x4c,0x5f,0x95,0x99,0xf2,0x5f,0xdd,0x97,0x9f,0xf1,
-0x72,0x6c,0x06,0xd4,0xcd,0x03,0x8e,0xa6,0x00,0x78,0xd0,0x48,0x79,0xf4,0x49,0x71,
-0x7e,0x9a,0xe8,0x13,0xb3,0x36,0xd5,0x2a,0xf6,0x99,0xb7,0x4a,0xfd,0xe6,0x18,0x53,
-0x34,0xc7,0x05,0xbc,0x65,0xa4,0xaf,0x09,0x8f,0x21,0x6f,0x7f,0xf3,0x7a,0xe1,0x4d,
-0xdd,0xcb,0x49,0x3a,0x49,0x87,0xce,0xfc,0x35,0xe2,0x38,0x2d,0xba,0x46,0x7f,0x19,
-0xef,0xad,0x15,0xa9,0xaf,0x2c,0xac,0xdf,0x5c,0xdd,0xc7,0xbe,0x4d,0x2c,0xd7,0xc4,
-0x76,0x1e,0xab,0x22,0x60,0x39,0x8f,0xdd,0xfc,0x31,0x3e,0xff,0xbe,0xdd,0x1c,0xd1,
-0x56,0xff,0xf7,0xf2,0x8f,0xd3,0xfe,0x5a,0xc4,0xe7,0x44,0x78,0x5e,0x84,0x5f,0x15,
-0x5e,0x9f,0x8a,0xe6,0x8e,0x73,0xfb,0x6a,0xae,0xbf,0xd5,0x7d,0xcf,0xa6,0x7c,0x9d,
-0x0b,0x5d,0x5a,0x94,0xee,0xce,0xcd,0x1d,0x77,0x88,0x9f,0xef,0x44,0x7e,0x4e,0x2b,
-0xaf,0x6b,0xe7,0xf4,0xed,0xed,0xb2,0xbe,0x1d,0xf9,0x39,0xcb,0xb7,0x43,0xfd,0x9c,
-0xf1,0x74,0xb1,0x76,0xce,0x02,0xf0,0xfc,0xab,0xcf,0x77,0x7d,0x05,0xf3,0xd5,0x22,
-0xe5,0x50,0x34,0xf3,0x32,0x11,0xf2,0x3c,0x5b,0xe6,0x23,0x34,0x30,0x9f,0xbf,0x06,
-0xa9,0x67,0xc5,0x57,0x96,0x25,0x54,0x3e,0xbe,0xaf,0x7b,0x6c,0x36,0xa5,0x9b,0xcd,
-0xa6,0xc3,0x66,0xf0,0x88,0x43,0x1c,0xef,0xc8,0xe8,0x37,0x77,0x66,0x0a,0xc7,0xb2,
-0xcc,0x30,0x2f,0xd5,0x6c,0xca,0x36,0x9b,0x3b,0x85,0x7d,0x53,0x76,0x3f,0xcc,0x61,
-0xc1,0x59,0x2c,0x26,0xaa,0x9d,0x4b,0xf3,0x58,0x84,0x95,0xb4,0x70,0xa4,0x87,0x1b,
-0xec,0x14,0x57,0x95,0x9f,0x8c,0xd6,0xeb,0xe1,0x5f,0x53,0x24,0x0f,0x08,0x35,0x5f,
-0xd7,0xea,0x3f,0xe5,0x39,0x3b,0x5e,0xff,0x44,0x1d,0x41,0x4a,0x72,0x74,0x8a,0xfe,
-0x4c,0xa2,0xfe,0x2f,0x9f,0x64,0xfe,0xc5,0xd1,0x95,0xeb,0x70,0xf5,0xe4,0xa2,0xe7,
-0xab,0xbb,0xe7,0xa4,0xc0,0xd7,0x4f,0x08,0xf8,0x7e,0x62,0x72,0xaa,0xe7,0xd5,0x29,
-0xc0,0x74,0x86,0xe7,0x33,0xdd,0x27,0x66,0xd0,0xbb,0x5d,0xec,0x57,0x03,0x6d,0x3b,
-0x68,0xe2,0x20,0x00,0xd7,0x51,0xdb,0xde,0x4f,0x73,0x53,0x11,0xcb,0x07,0x58,0x14,
-0x09,0x98,0x5e,0xec,0x64,0x39,0x77,0x08,0xc7,0x80,0xde,0xf1,0xc7,0xff,0xca,0xfd,
-0x63,0x4a,0x4a,0x7c,0xca,0xf6,0xfe,0x43,0x7e,0xbe,0x0d,0xf2,0xed,0xa6,0xfb,0x45,
-0xa6,0xb9,0xe1,0xb2,0xb9,0xd9,0x91,0xb2,0x59,0xd0,0xb9,0xc3,0xfe,0xe2,0x90,0x7e,
-0x71,0xc6,0x52,0x31,0x03,0xb9,0x77,0xe6,0x13,0xc7,0xfa,0xd5,0xe6,0x2d,0x15,0xf3,
-0x10,0xe8,0x25,0x23,0xce,0x4c,0x5d,0x18,0xad,0x5c,0x58,0xb2,0x54,0x2c,0x81,0xbe,
-0x1d,0x75,0x70,0xd6,0xea,0x39,0x98,0xaf,0x86,0x98,0x6e,0x33,0x6a,0xe2,0x3a,0xac,
-0xb3,0x8e,0xda,0x59,0xca,0xb1,0x1b,0xc5,0x5e,0xb5,0xda,0x05,0x5a,0xeb,0x16,0x98,
-0x4f,0x5c,0x58,0xa0,0xaf,0x4c,0x3d,0xf6,0xa0,0x83,0x0e,0x4e,0xee,0x57,0x53,0xfb,
-0xc9,0x34,0x88,0xde,0x70,0x8d,0x8a,0xbe,0x73,0x39,0x9a,0xc5,0x3e,0x74,0xe2,0xe5,
-0x5e,0x67,0xbd,0xd7,0xef,0xa8,0xf5,0xcf,0x0e,0x1a,0x66,0xaf,0xfd,0x4b,0xd6,0xb5,
-0x7d,0xc9,0x31,0xfb,0x58,0x5f,0x93,0xda,0x8f,0x4c,0xcb,0xcf,0x24,0x2d,0x2d,0x25,
-0x4d,0x31,0x2f,0x75,0x82,0xe3,0xe9,0xa2,0x5f,0x1c,0xac,0xa0,0x69,0x47,0x3e,0x2e,
-0xce,0x65,0x41,0x3f,0xb8,0xb1,0x9a,0xb5,0x35,0x47,0x8d,0xe4,0x07,0x47,0x39,0x78,
-0xf0,0x83,0x13,0x31,0x5e,0xc0,0x75,0x4f,0x9f,0xd1,0xf3,0x7a,0x4b,0xf6,0xeb,0x07,
-0xf7,0xc5,0x1e,0x84,0xf3,0x38,0xef,0xc4,0xfe,0xbc,0x6f,0x3e,0xad,0xf8,0x06,0xbc,
-0xe0,0x51,0x07,0x2f,0x70,0x79,0xd2,0xbe,0x09,0x58,0x3e,0xd1,0xfc,0x6c,0xcd,0x55,
-0xbf,0xf6,0xfd,0x98,0xf1,0xfb,0x1f,0x1c,0xd5,0x3f,0xfc,0xdd,0x5e,0xf5,0xf7,0x1f,
-0xc6,0x0c,0x3f,0xc0,0xe3,0xef,0x9d,0x42,0xb8,0xea,0xbe,0x07,0x7c,0xc7,0x9a,0xb9,
-0x80,0xed,0x50,0x4b,0x5f,0x1f,0x6f,0xa2,0x00,0xff,0x56,0xd4,0xc9,0xb5,0x20,0xbe,
-0x53,0xdd,0xbc,0x59,0xf2,0x70,0x67,0x1e,0xed,0x1b,0xce,0xba,0x0d,0xeb,0xb7,0xe5,
-0xd6,0xb6,0x9a,0xb4,0xb6,0x63,0x87,0x62,0x8e,0x9d,0xcb,0xdf,0x7f,0x6e,0xf4,0xbb,
-0xaa,0x51,0x9a,0xbf,0x22,0x7a,0xb9,0x4e,0x90,0x57,0x1c,0xd4,0xc5,0x99,0x2f,0x1c,
-0x7a,0xbb,0xa2,0x7f,0x9c,0xec,0xed,0x2a,0xd7,0xd3,0x49,0x07,0x4f,0xfb,0x17,0x45,
-0xbf,0xd7,0x70,0x3c,0xe7,0xeb,0xe8,0xbc,0xd7,0xab,0xda,0xb7,0x5d,0xf2,0x6e,0x8f,
-0xd5,0xae,0xaf,0x6f,0xc5,0xd1,0xb7,0x8b,0xdf,0x9a,0xfc,0x3c,0x02,0x6e,0xab,0x79,
-0x1b,0x8f,0xe3,0x12,0x06,0x70,0xfb,0x3f,0x12,0xc9,0xff,0xe1,0x5b,0xc4,0x7b,0x8f,
-0xe8,0x4d,0xbe,0xbe,0xd5,0x6b,0x8c,0x56,0xad,0x1a,0xdf,0xc7,0xe7,0x02,0x74,0xba,
-0x28,0xdd,0x07,0xef,0xc7,0x7e,0x40,0x7a,0xb8,0x38,0xd2,0xc3,0x3d,0x8a,0xef,0x00,
-0x8f,0x57,0x5c,0x59,0x0d,0xbd,0x9d,0xe3,0xe7,0x2c,0xd7,0x8e,0x35,0x74,0x19,0xcb,
-0x19,0x3f,0xe7,0xf5,0x70,0xc0,0xcf,0x21,0xfe,0xfa,0x45,0xf2,0x5f,0xf5,0x45,0xb1,
-0x7a,0xc5,0xe7,0xc5,0xff,0x41,0x7c,0xdd,0x24,0x4a,0x95,0x07,0x51,0x9f,0x17,0x51,
-0xe1,0x38,0xaf,0x85,0x89,0x7c,0xad,0x21,0x22,0x8f,0x17,0xce,0xf1,0xf2,0xd2,0x84,
-0xf2,0xc7,0x7f,0x4b,0x7f,0x0c,0x58,0x6e,0x36,0x65,0x60,0x30,0x4e,0x6e,0x36,0x65,
-0x22,0x96,0x03,0x37,0x07,0x2c,0x37,0x77,0x66,0x9b,0x01,0xc7,0x69,0x3d,0x22,0xac,
-0x47,0x70,0xc5,0xe8,0xca,0xe9,0x57,0xeb,0xdb,0xd9,0x0a,0x3e,0x71,0x37,0xdf,0x4b,
-0xbd,0x89,0x7a,0xb8,0x4d,0xf2,0x10,0xd2,0xdf,0x1f,0x49,0x57,0x10,0xc9,0x93,0x9e,
-0xf3,0x8d,0x50,0xe4,0xdf,0x13,0xe4,0xba,0x02,0xe8,0x82,0x75,0xfb,0xa3,0x75,0x6d,
-0x0d,0x7b,0xdb,0xda,0xbf,0x38,0xda,0xee,0xec,0xa6,0x1a,0x3a,0xf4,0x9f,0x93,0xef,
-0xeb,0xa9,0x71,0x9a,0xa7,0x06,0xf5,0xf3,0x5c,0x0f,0xd4,0xd0,0x41,0xd7,0xce,0x6a,
-0xe8,0xa0,0x91,0x73,0xf6,0x91,0xcf,0x2b,0x04,0xe4,0xdb,0xa1,0x67,0x8d,0x05,0xe5,
-0xdb,0x0b,0x29,0xdf,0x3e,0x50,0xe8,0x1a,0xef,0x2f,0x1c,0x87,0x95,0x70,0xbd,0x78,
-0xcc,0x39,0x58,0xec,0xb4,0xf6,0x15,0x59,0xdf,0x7a,0x33,0xf3,0x2d,0x81,0x58,0x24,
-0x6c,0x71,0x26,0xff,0xac,0x1b,0xef,0xdf,0xce,0xeb,0xe0,0xe6,0x46,0xca,0xa4,0x59,
-0x2c,0x6c,0x1e,0x0b,0xf0,0xf3,0x19,0x6b,0xd5,0xcc,0xca,0x50,0xf1,0xca,0xd2,0x70,
-0xe9,0x12,0xe3,0xe6,0x8b,0x23,0x15,0x8b,0x6b,0xd6,0xb2,0xb5,0xf5,0x51,0xfd,0xba,
-0x6f,0x58,0xef,0x5b,0x1c,0xad,0x5c,0x84,0x9a,0x39,0xcc,0x56,0x63,0x78,0x0e,0x1a,
-0x77,0xe8,0x3f,0x87,0x3c,0x3b,0xf6,0xa2,0x0b,0xf8,0x3d,0x67,0x37,0xce,0xb1,0x1e,
-0x74,0xa8,0xab,0x83,0xaf,0xcc,0xb2,0xb5,0x6a,0x99,0xf5,0x9c,0x53,0xff,0x79,0xcd,
-0xd2,0x92,0xdd,0xb8,0xc4,0x74,0x71,0xe4,0x25,0x23,0x60,0xf9,0x58,0x1d,0x7a,0xc4,
-0x2d,0x3a,0xc8,0xfb,0x15,0xfc,0x5e,0x17,0x9d,0x0d,0x14,0x63,0x9c,0x37,0x9c,0xab,
-0x69,0x49,0xf6,0x89,0x23,0x0f,0x19,0xe4,0xe8,0x4e,0x19,0xc7,0x31,0x9c,0x4d,0x88,
-0xe7,0x3e,0x47,0x9d,0x6f,0x6e,0xa4,0x66,0xee,0xdd,0xab,0xc7,0xde,0xdd,0xbf,0x3b,
-0x6e,0x3f,0xea,0xa4,0x77,0x12,0x56,0x28,0x72,0xb9,0xe2,0x39,0xc8,0xeb,0x3e,0xd2,
-0x52,0x01,0xcf,0x65,0x7d,0xbb,0xc2,0x1f,0x0e,0xf8,0x39,0xf4,0xa1,0x83,0x57,0xbb,
-0xfb,0x3c,0xd6,0xd2,0x83,0xce,0x3a,0x01,0xcf,0x49,0xef,0x4e,0x7a,0x37,0x56,0x47,
-0xa7,0xfa,0x39,0xf0,0x77,0xd0,0xb3,0x03,0x3f,0xf7,0x3b,0x9b,0xfc,0xf7,0x3e,0x2e,
-0xbe,0x77,0xfc,0xc8,0xee,0xe3,0x70,0x3e,0xa7,0x1e,0x48,0x4c,0xfd,0xc3,0xad,0xe2,
-0x3f,0x40,0x7f,0x18,0xe4,0xd6,0x03,0x13,0xad,0x01,0xe0,0xe6,0xc8,0xd3,0x81,0x9b,
-0x63,0x8e,0xbd,0x09,0xf9,0x39,0x62,0xb8,0x88,0xe3,0x80,0xc1,0x1b,0x2e,0x21,0x9c,
-0xc0,0xdb,0xeb,0x15,0x58,0x8e,0xba,0x38,0xb7,0xac,0x7b,0xa3,0x3a,0xfa,0xf9,0x35,
-0xaa,0xad,0xcb,0x3a,0x76,0xd2,0xba,0x37,0x6c,0x4c,0x74,0x55,0x4f,0xfc,0xea,0x9f,
-0x8e,0xfc,0xea,0xb8,0x2e,0xf6,0x78,0xe6,0x4b,0x31,0x99,0xb7,0xae,0xe7,0xdd,0x0a,
-0x39,0x9b,0x42,0x0c,0xc3,0x41,0xd3,0xae,0xc4,0xea,0x8b,0xd4,0xb7,0xe6,0x91,0xb1,
-0x9c,0xe9,0xe3,0x78,0xae,0x2e,0x73,0xf6,0x4b,0x18,0x41,0xf7,0xc5,0xe0,0xcd,0x5f,
-0x17,0xde,0x4c,0x3b,0x90,0x94,0xc6,0xb8,0xb9,0x1a,0xbf,0xd5,0x9e,0xed,0x8a,0x19,
-0x3f,0xbc,0x87,0xde,0x8e,0x08,0x3d,0xe2,0x2a,0xbd,0x1c,0x7f,0xed,0xd9,0x8c,0x73,
-0x6c,0x17,0xbb,0xd5,0xd7,0xf0,0x28,0xf1,0x00,0x2e,0xdc,0x63,0x2d,0x1c,0xe7,0x7f,
-0xc6,0xff,0x6f,0xdb,0xdb,0x74,0x69,0xd1,0xba,0x3b,0xb7,0x04,0x7e,0xfe,0x70,0xe7,
-0x77,0xa0,0x6b,0x67,0x98,0x2e,0xe1,0xba,0xa2,0x5f,0x8d,0xeb,0x59,0x6b,0xa7,0x7c,
-0x3b,0xf4,0xac,0x21,0x96,0x3f,0x02,0x3c,0xdf,0x85,0x41,0xfd,0x6a,0x90,0x77,0xdf,
-0x6d,0x22,0x3c,0xdf,0xdd,0xf9,0xd5,0xe7,0xc9,0x5f,0x01,0x9e,0x2b,0x7e,0xb9,0xfa,
-0x73,0x8c,0xb0,0xf2,0x38,0x1f,0xe9,0xd3,0xdd,0x6e,0xfe,0x5e,0x0b,0xeb,0x4b,0x4b,
-0x13,0x4b,0x01,0xcf,0xfb,0x4c,0x87,0xfb,0xfa,0x4c,0x19,0x62,0x64,0xf6,0x01,0x2f,
-0x27,0x7e,0x9e,0x89,0xbc,0x1c,0xf8,0x79,0x5f,0x67,0x56,0x1f,0x60,0x39,0xc3,0x71,
-0x5a,0x73,0xc4,0x19,0x2c,0x72,0xa0,0xa6,0x1d,0x75,0xed,0xe4,0xe3,0x0e,0xfc,0xfc,
-0xc6,0x6f,0x52,0x6f,0x30,0x7f,0x38,0x45,0x0d,0x47,0x7d,0x9f,0xa2,0xbe,0x5f,0x89,
-0xd2,0xce,0x49,0xa8,0xb1,0x5e,0xad,0x73,0x57,0xfb,0xe9,0xb1,0x7e,0x3e,0xdd,0xc1,
-0x58,0xdd,0xb5,0xb7,0x0e,0x5d,0xeb,0x7d,0x70,0xa2,0x37,0x4c,0xe3,0xde,0x07,0xda,
-0x76,0xf2,0x93,0x81,0x5e,0x74,0xa8,0x9b,0x33,0xbf,0x57,0x8a,0x02,0x3b,0xe5,0xd8,
-0x0b,0xb8,0x5c,0x3b,0xad,0x8c,0x9f,0x13,0xa6,0x8b,0xd8,0x2e,0x04,0xe4,0xda,0xe5,
-0xd0,0x8f,0x99,0xbe,0xcd,0x37,0x19,0x0c,0x07,0x0c,0x31,0xd0,0x91,0xf7,0x0b,0x6d,
-0x27,0x4f,0x1e,0xe0,0xf4,0xed,0xd5,0x92,0xb6,0x9d,0x66,0xa1,0x03,0x37,0x37,0x4c,
-0x49,0xba,0x38,0xcc,0xb7,0x57,0x0b,0xfc,0xbc,0x7c,0x9e,0x3c,0xe2,0xa8,0xef,0x7c,
-0xc9,0x52,0xbe,0xb4,0x6e,0x2f,0x5f,0xdf,0xb0,0x95,0x6c,0x78,0x47,0x4a,0xbd,0xd0,
-0xaf,0x26,0x63,0x39,0xe5,0xdc,0x41,0xfb,0xb6,0x62,0x29,0x5b,0x01,0xdc,0x46,0x5d,
-0xbb,0xcd,0x80,0x3d,0x6a,0x2b,0xa3,0xe5,0x2b,0xd0,0xc3,0x16,0x1c,0x2e,0x0e,0xfa,
-0x2d,0xa5,0xfe,0x95,0xd1,0xca,0x95,0x65,0x6b,0xf5,0x32,0xac,0xfe,0xd1,0x72,0x3f,
-0xe4,0xd9,0x97,0x6d,0xd5,0xcb,0x88,0xef,0x02,0xae,0x43,0x9e,0x9d,0x82,0xf9,0xc4,
-0x01,0x7e,0xcb,0xc1,0xb8,0x39,0x61,0x7a,0x93,0xb0,0xdf,0xb4,0xc8,0xfc,0xdb,0x65,
-0x8e,0xde,0x4c,0xd8,0x3e,0xde,0xa4,0xa8,0x9f,0x83,0x46,0x0e,0x72,0xee,0xb3,0xa3,
-0x75,0xb3,0xef,0x5c,0x3d,0xfe,0x4e,0x72,0x62,0x5c,0xb2,0xc2,0xff,0x5b,0x83,0x9b,
-0xf1,0xfc,0x8a,0xe6,0xab,0x01,0x9e,0xb7,0xac,0x10,0x37,0xe7,0xbc,0xe1,0x04,0x5e,
-0x0e,0xbd,0xe8,0xd8,0x73,0x0e,0xe1,0x6a,0x5c,0x45,0x4c,0x1f,0x67,0x35,0xf3,0xc6,
-0x80,0x5c,0x3b,0xa7,0x39,0xe8,0xe0,0xe9,0x4e,0xf9,0xf6,0xa6,0xa0,0xb5,0xd3,0x68,
-0x6d,0x6b,0xce,0x6a,0x4b,0xd9,0x15,0x9b,0x92,0xb2,0x67,0x67,0xca,0xb5,0x7f,0xcb,
-0xbd,0xb6,0x64,0x6f,0x42,0x2d,0x3b,0xe2,0x39,0x46,0x2b,0xae,0x94,0x77,0xbf,0x80,
-0x5c,0x1d,0x6a,0xe8,0x6b,0xe3,0x0d,0x6b,0x18,0x98,0x53,0x27,0x5d,0x3b,0xe1,0x78,
-0xfd,0x3a,0xea,0xd9,0x99,0xb6,0x1d,0x56,0xcc,0xc5,0x37,0x49,0x1a,0x77,0xa6,0x73,
-0x47,0x7d,0xfb,0x84,0xdc,0xa3,0x36,0x3f,0x54,0x37,0x7f,0xf3,0xdd,0x93,0x37,0x4f,
-0x64,0x25,0x9e,0x80,0xfe,0xb1,0x82,0xdc,0x94,0x02,0x57,0x5f,0xad,0x8b,0xcd,0x4d,
-0x95,0xf1,0xba,0x85,0xfc,0xda,0x27,0x5b,0xa5,0x59,0xe8,0xd4,0x7f,0x7e,0x71,0x5d,
-0xc2,0xed,0x29,0xd9,0xc7,0x9d,0xe5,0xdc,0xc9,0xd3,0xfd,0xd2,0x3a,0xf9,0xbd,0x0a,
-0x78,0x2e,0xf0,0xf3,0xd4,0x97,0x93,0x53,0x79,0x6f,0x37,0xb5,0x8f,0x9b,0xd6,0x0c,
-0x16,0xf5,0xfc,0x8b,0x30,0x3f,0x56,0xee,0xda,0xa1,0x98,0xa7,0xb6,0x89,0x5e,0x4e,
-0x5d,0x17,0xdc,0xec,0x5a,0x1b,0xb1,0x66,0xac,0xc2,0x70,0xc5,0x35,0x2f,0x42,0x3d,
-0xfa,0x97,0xba,0x46,0xfc,0x6f,0xda,0xd8,0xfb,0x94,0x96,0x16,0x95,0x06,0x78,0x0e,
-0xfd,0xe7,0x92,0x9f,0xcc,0x43,0xc0,0x72,0xd8,0x8f,0x97,0x02,0xb0,0xbc,0xe3,0x51,
-0x62,0x87,0x54,0x37,0xe7,0x30,0x5d,0xc6,0xf3,0x64,0xae,0x96,0xce,0x6a,0xe8,0xc4,
-0xcf,0x59,0xbe,0x5d,0xcd,0xcb,0xd5,0xb9,0x88,0xcd,0x3e,0x4f,0x69,0x9f,0x3f,0x17,
-0xb4,0xce,0x19,0x0e,0xff,0xd8,0xd7,0x35,0x35,0x04,0xe2,0x3d,0x6a,0x59,0x69,0x62,
-0x59,0xfb,0xfd,0xf4,0x76,0xe2,0xe7,0x87,0xcd,0x80,0xe7,0xe6,0xce,0x0c,0xc2,0x71,
-0x86,0xe5,0x88,0xe7,0xb4,0xb2,0x5c,0x3b,0x72,0xf4,0x2e,0xe2,0xe5,0xe6,0xce,0x1c,
-0xb3,0xb9,0x2b,0x47,0xc4,0xf6,0xa3,0x18,0xcc,0x17,0x8e,0xcd,0x58,0xbb,0xf1,0x5e,
-0xda,0x0d,0xf4,0x87,0x53,0xbf,0x1e,0x8d,0xcf,0x45,0xeb,0x38,0xff,0xfa,0xd5,0xef,
-0x61,0xa4,0x3a,0x8c,0xfa,0xff,0x92,0xe5,0x2a,0xb2,0x32,0x12,0xb2,0x3e,0xbe,0x95,
-0xf5,0xf1,0xf0,0x93,0xbc,0x61,0xb9,0x0f,0x1d,0x3c,0xdb,0xcf,0x60,0x40,0x9f,0x1a,
-0x78,0xbe,0x92,0x87,0x3b,0xcd,0x64,0x01,0x2c,0x47,0x0f,0x77,0xc9,0xef,0x55,0x88,
-0x01,0xf2,0x7c,0xa5,0x90,0xfb,0xcf,0x31,0xbf,0x3e,0x58,0x8c,0x2b,0xc3,0x71,0xb6,
-0xda,0xcd,0x7a,0xfb,0x9f,0xfe,0x98,0xfb,0xa7,0xa3,0x47,0x77,0x1f,0x7d,0x91,0x73,
-0xf7,0xa7,0xd8,0x18,0x3f,0x07,0xff,0xf6,0x30,0x8d,0x3b,0xce,0x57,0x33,0x10,0xae,
-0x4b,0x7e,0x32,0x72,0xde,0x1d,0x7b,0xd6,0x6c,0x34,0x37,0x75,0xc9,0x52,0xb9,0xb4,
-0x68,0xa9,0x58,0x9c,0x1b,0xad,0x26,0x1c,0xb7,0xd7,0xcc,0x4a,0x3a,0x77,0x3b,0xe9,
-0xe0,0xbc,0xc3,0x25,0x5e,0xe0,0xef,0xa8,0x75,0xb7,0xd2,0x0c,0x16,0xc0,0x73,0xff,
-0x48,0x99,0xdf,0x6b,0x29,0x47,0x6e,0x4e,0xbc,0xbc,0x7a,0xc9,0x6f,0x29,0xf7,0x87,
-0x86,0xf5,0xa1,0xa0,0xa5,0x24,0x48,0x7a,0xf6,0x72,0x3f,0x68,0xe0,0x10,0xdb,0xc1,
-0x23,0xce,0x61,0x7c,0xca,0x70,0x1d,0x7a,0xcd,0x09,0xcf,0xc1,0xf7,0x15,0xf0,0x5c,
-0xe6,0xe8,0xd0,0x83,0xce,0xfc,0x65,0xa8,0xf7,0x1c,0x7c,0xe2,0xc8,0x5f,0x66,0xd9,
-0xd5,0xbc,0x8c,0xbd,0xe8,0xe3,0x14,0xa0,0x6f,0x87,0x75,0xd2,0x52,0x3f,0x79,0xf5,
-0x9f,0x8f,0x5e,0x15,0x80,0x20,0x96,0x3b,0xbd,0xc2,0xea,0x62,0xea,0xf7,0x92,0xe1,
-0x39,0xe0,0x37,0x61,0x3a,0xac,0xa2,0xe7,0x2b,0xcc,0x52,0x03,0x9f,0x18,0x01,0xc7,
-0xb1,0xf7,0x9c,0x85,0xab,0x21,0x08,0xb5,0x74,0x0c,0xc0,0x73,0x98,0xcb,0x32,0x0e,
-0xda,0xb7,0xe6,0x55,0x58,0x41,0xe3,0xee,0x77,0xd4,0xfb,0xef,0x7e,0x70,0xf6,0x6e,
-0x6e,0xce,0xae,0xdc,0x03,0xbb,0x77,0x1c,0xb8,0x72,0x21,0xeb,0x8a,0xe3,0x89,0xd1,
-0xc1,0xfa,0xd1,0x02,0x9e,0x96,0x80,0x5c,0x3f,0xbf,0x20,0xee,0xb7,0x06,0x65,0xae,
-0xde,0x8c,0x5c,0x9d,0xe9,0xe2,0xe4,0xfe,0xb4,0xba,0x0d,0xa8,0xa7,0xaf,0xbb,0x00,
-0xc7,0x05,0xae,0xee,0x22,0xae,0x4e,0xfd,0xe5,0x32,0x9e,0x33,0x8e,0x4e,0xd1,0xb2,
-0xe6,0x73,0x34,0xf9,0xfe,0xfc,0x51,0xd1,0x9f,0xf3,0x5e,0xdd,0x97,0xb7,0x3f,0x29,
-0x66,0x7f,0xca,0xee,0xd8,0x94,0xdb,0xff,0x99,0x7f,0x1b,0xe6,0xa6,0x10,0xdf,0x96,
-0xfb,0xd2,0xe4,0xfe,0x34,0xe2,0xe0,0xa4,0x73,0x27,0x0c,0x47,0x6f,0xb8,0xa9,0x4b,
-0x0a,0x2c,0x27,0xcd,0xfb,0xe5,0x67,0xec,0x18,0x68,0xe6,0xd0,0xbf,0xfd,0x7a,0xd1,
-0x6f,0x0f,0x1d,0x48,0x3a,0x14,0xc9,0xb7,0x4d,0xcd,0xcb,0x15,0x35,0x72,0x8d,0x5a,
-0x79,0x98,0xee,0x2d,0x46,0xc9,0xc7,0xb5,0x72,0xe8,0xea,0x63,0x12,0xc7,0xe0,0x7d,
-0xc5,0xa3,0xa2,0x24,0x7f,0xc1,0x4d,0xb1,0x99,0x5d,0xab,0x78,0xfe,0xae,0xce,0xac,
-0x73,0x39,0xe6,0xff,0x6b,0x78,0xbe,0xe9,0xeb,0x55,0xe3,0xa5,0x1a,0x07,0x84,0x4d,
-0xa7,0x8b,0xd6,0x7d,0xf0,0xfe,0x8e,0x0f,0x80,0x9f,0x13,0x27,0x97,0x3d,0xe2,0x78,
-0x2c,0x37,0xb5,0xc7,0x2b,0xea,0xe7,0x94,0x6b,0x87,0xde,0xb5,0x24,0x0d,0x1c,0x57,
-0xd6,0xcf,0x3b,0x1f,0x13,0x9e,0x83,0x1e,0x4e,0xeb,0x7e,0x2c,0x62,0xee,0x66,0x93,
-0x5a,0xb9,0x22,0x5f,0x14,0x41,0x0b,0xc7,0xce,0x69,0x7e,0xce,0x9a,0x5a,0xff,0x0e,
-0x39,0x2c,0x79,0xbe,0x5a,0x3a,0xce,0x57,0x63,0x33,0x52,0x41,0xdb,0xce,0x6b,0xe1,
-0x70,0xc5,0x9a,0x79,0xd6,0x00,0xc3,0x74,0x8a,0x9c,0x7e,0x09,0xc7,0x25,0xae,0x2e,
-0xce,0x40,0x67,0xfd,0xe7,0x38,0x5f,0x0d,0xfc,0xdb,0x77,0xbc,0xa4,0xfe,0x98,0x7e,
-0xd2,0xcf,0x7c,0x9b,0xcf,0x01,0x6e,0x5c,0x90,0xbf,0xa7,0xe0,0xeb,0xcf,0x8e,0x7f,
-0x3d,0xda,0x7b,0x66,0xd4,0x6a,0xce,0xb7,0xb2,0x80,0x19,0x2c,0x56,0xf3,0x59,0x2b,
-0x04,0xce,0x57,0xc3,0x90,0xf1,0x9c,0xf6,0xa9,0x66,0xce,0x07,0xef,0x25,0x23,0xf5,
-0xa0,0x0f,0x52,0xed,0x1c,0x56,0xe7,0xa0,0xde,0x09,0x78,0x0e,0xeb,0x60,0x57,0xd1,
-0xe0,0xf5,0x77,0x72,0xae,0xef,0xdd,0x17,0xbf,0xf7,0xc7,0xbe,0x1f,0x2f,0xb2,0xe5,
-0xe6,0xbe,0x94,0x0b,0xf3,0xd5,0x94,0xfd,0xe7,0xac,0x66,0x5e,0xa5,0xd2,0xb4,0xf3,
-0x3c,0x5d,0xd4,0xb4,0x6b,0x78,0xc4,0x31,0x1c,0xe7,0xfb,0xd6,0x20,0xd7,0x0e,0x33,
-0x59,0xb0,0xf7,0x1c,0xf1,0xbc,0x6a,0x89,0x66,0xac,0x41,0x54,0x2f,0xd2,0x5c,0x35,
-0xf2,0x7a,0x85,0x3c,0x3b,0xf8,0xc8,0x80,0x9e,0x7d,0x7d,0xa4,0x68,0x7d,0xc3,0xa2,
-0xdf,0x58,0xb7,0xe8,0xd7,0x43,0x96,0x92,0x10,0xc3,0xf5,0x15,0x5b,0xf5,0xca,0xb2,
-0xdd,0xb0,0xbc,0x6c,0xaf,0x5d,0x06,0x5c,0xa7,0x9e,0x73,0xf2,0x89,0x23,0x4d,0x3b,
-0x61,0x38,0xe8,0xe3,0xfc,0xb6,0x2a,0xbf,0xcf,0x5e,0xed,0xf3,0x3a,0x8c,0x5e,0xaf,
-0xa3,0xd6,0xbb,0x32,0x56,0xb7,0xb2,0x32,0x56,0x2f,0x44,0xc3,0x0a,0xf4,0xaf,0x61,
-0xef,0x1a,0xf6,0xa1,0x37,0x62,0xef,0x9a,0xcd,0x6c,0xb4,0xb5,0xb5,0x66,0xb6,0x09,
-0x44,0x2d,0xcc,0x03,0x4c,0x9d,0x0f,0x95,0x1e,0x0b,0x2b,0xf8,0xbd,0x7a,0x06,0xeb,
-0x3d,0xe8,0x0d,0xe7,0x3e,0xef,0xe3,0xfd,0x5e,0x59,0x0d,0x9d,0x38,0x7a,0xd3,0x2a,
-0xe4,0xd9,0x71,0x1e,0xaa,0x10,0xa8,0x71,0x77,0xca,0x1a,0x77,0x49,0x27,0x27,0x70,
-0x75,0xe8,0x53,0xb3,0x7e,0x57,0x65,0x7d,0xbd,0x25,0xe3,0xf5,0x43,0x7b,0x63,0x0e,
-0x55,0x95,0x1c,0xac,0x32,0x7d,0x5d,0x69,0x82,0xfc,0x3b,0xe2,0xb9,0x5b,0xc4,0xf4,
-0x89,0x0b,0x01,0xe6,0x1b,0x43,0xdc,0x1c,0xbc,0xe0,0xd8,0x8c,0x54,0xd1,0x57,0x86,
-0xeb,0x5b,0xc3,0x5c,0x3a,0xef,0x27,0x33,0x71,0xfe,0x99,0xe4,0x23,0xe3,0xa1,0x5e,
-0x35,0xd0,0xa1,0x51,0x7f,0x9a,0xec,0x15,0x07,0xbe,0x73,0x0f,0x3e,0x3f,0xf7,0x40,
-0x5f,0x90,0xaa,0x4f,0x4a,0x88,0x49,0x02,0x6c,0x2d,0xc8,0xd7,0x15,0x58,0xbb,0x1b,
-0xac,0xe4,0x01,0x7b,0x11,0xb1,0x98,0xef,0x65,0x63,0xba,0x76,0xb5,0x3f,0x3b,0x78,
-0xbb,0x23,0x76,0x4f,0x53,0x7f,0x1a,0xf4,0xa9,0xc9,0x9e,0xee,0x97,0x25,0xac,0x97,
-0xf9,0x79,0x52,0x2a,0xaf,0x81,0x53,0x60,0x3a,0x5f,0x2f,0x57,0xe7,0xda,0x23,0xe1,
-0xf9,0x56,0xbc,0x3c,0x02,0xbe,0x6f,0x8a,0xf3,0xea,0xeb,0xb9,0x16,0x5f,0x8f,0x56,
-0x62,0x7a,0x58,0x0d,0x58,0xc5,0xed,0x22,0xd6,0x8e,0x7f,0xc2,0x6d,0xdb,0xf7,0x0b,
-0x1a,0xd8,0xb9,0xc5,0x0f,0x0d,0xcb,0x29,0xab,0x73,0x17,0xec,0xa9,0xec,0xbd,0x51,
-0x3c,0x66,0xc7,0xf8,0xfb,0x9f,0x4d,0xf0,0x91,0xed,0xa7,0xeb,0xa2,0xd2,0xa1,0x7e,
-0xde,0xf1,0x30,0x8e,0xf3,0x7a,0x25,0x4d,0x1c,0xd3,0xb6,0x33,0x1f,0x77,0x9a,0xc7,
-0x22,0x7a,0xb7,0xb7,0xb3,0x19,0xe8,0x30,0x63,0x4d,0xdd,0x7f,0xbe,0xbb,0x8b,0x79,
-0xc4,0x99,0xda,0xf7,0x98,0x18,0x3f,0x87,0x7e,0xb5,0xad,0xb4,0x15,0xfc,0xb9,0xa6,
-0x95,0x57,0xd6,0xaa,0x25,0xe3,0xf9,0x1b,0xcb,0xcd,0x48,0xe5,0x71,0x3b,0x4e,0xe9,
-0x29,0xc7,0x34,0x25,0x52,0xaf,0x76,0x42,0xd4,0x2e,0x43,0x25,0xcd,0x57,0xc3,0xb9,
-0x6a,0x30,0x03,0xbd,0x23,0x5d,0x9c,0x7d,0x9e,0x31,0x38,0x60,0xca,0x1c,0x90,0xf3,
-0xed,0x59,0xa2,0x36,0x2e,0x1b,0xb5,0x71,0xac,0x6e,0x6e,0xee,0xa2,0x9c,0x3b,0xf2,
-0xf3,0xae,0x1c,0xd5,0xfc,0xf3,0x63,0xfd,0xcc,0xef,0x15,0xe7,0x9f,0x73,0xfc,0xfc,
-0x97,0xde,0xe2,0xe2,0x62,0xe2,0x2e,0xb7,0x1e,0xbc,0xdc,0xfd,0xe8,0x74,0xf7,0xa8,
-0x39,0x7f,0xd4,0xda,0x27,0xe0,0x39,0x0b,0xc4,0x75,0xe2,0xe6,0xf6,0xfe,0x7c,0x3b,
-0xcd,0x4c,0x2d,0xb0,0x91,0xa6,0x1d,0xfc,0x65,0xe4,0x9c,0x3b,0xd4,0xcb,0xc9,0xf7,
-0x55,0xe9,0x0f,0x07,0xfc,0x9c,0xb0,0x1d,0x30,0x5d,0xaf,0xc8,0xb9,0xc3,0x63,0xd0,
-0xbb,0xb7,0xb5,0xa6,0xb6,0x09,0x17,0x9c,0xd8,0xad,0xff,0xda,0x9f,0x76,0x53,0xd7,
-0xcf,0x25,0x3c,0x67,0x7d,0x6a,0x7c,0xfd,0x7c,0xd4,0xa0,0xc2,0x73,0x03,0xf9,0xc3,
-0x89,0x1e,0x71,0xd4,0xaf,0x56,0x33,0xb3,0x30,0x7a,0x6e,0x01,0x6a,0xe8,0x30,0xfb,
-0x1c,0x6b,0xe7,0xd6,0x9a,0x39,0x98,0x97,0x1a,0x18,0x2e,0x0a,0xf8,0x46,0x4a,0x7c,
-0xe0,0x15,0x07,0xdc,0x1c,0xbc,0x5e,0xe7,0xed,0x35,0xf3,0x34,0x87,0xc5,0x48,0xfd,
-0xe6,0xa0,0x69,0xb7,0xd7,0x2e,0x80,0x9f,0x0c,0xf0,0x70,0xe0,0xe3,0x7e,0x6b,0xa5,
-0x7f,0x75,0xb4,0x62,0xd5,0x67,0xad,0x24,0x5f,0x38,0x09,0xcb,0xc1,0x47,0xa6,0x56,
-0xc2,0x71,0xe8,0x39,0x87,0x5e,0x35,0xf0,0x98,0xa1,0x3e,0x74,0x83,0x2f,0x60,0xad,
-0x08,0x3c,0xb3,0x94,0x3e,0x0b,0x59,0x4a,0x43,0x41,0x6b,0x65,0x70,0xd5,0x56,0xb5,
-0xea,0xb7,0x1b,0x04,0x7c,0x37,0xfa,0x00,0xdb,0xbd,0x63,0x75,0x5e,0xc4,0x76,0x67,
-0x83,0x10,0x8d,0x2b,0x80,0xed,0xdf,0x7d,0x53,0xf9,0x9d,0xbe,0xf8,0xa0,0x9e,0xdd,
-0x0b,0x6b,0xfd,0x2f,0x6a,0xe5,0x53,0x53,0x53,0x5f,0x4a,0x9d,0x1c,0xac,0x9d,0x04,
-0x0e,0x8e,0x7d,0xe7,0xd0,0x9f,0x26,0x84,0xec,0xfb,0x0a,0xf3,0x57,0x5a,0xfc,0xac,
-0x7e,0x1e,0x72,0x18,0x43,0x6b,0x0e,0xc3,0x1a,0xf5,0xa0,0x1b,0x45,0x6c,0xaf,0x97,
-0xb0,0x1d,0xb0,0xdc,0x6b,0xaf,0xf7,0xde,0xbb,0x93,0x7f,0xef,0x58,0xc6,0xae,0x63,
-0xa7,0x8e,0xed,0x3b,0xf5,0xe9,0x27,0xc5,0x9f,0x3e,0xb5,0x37,0x3e,0x05,0x1c,0x0f,
-0x4c,0x9c,0x47,0x1f,0xd8,0xe0,0xc4,0xf9,0x20,0x3d,0x26,0x4c,0x97,0xf9,0x79,0x6b,
-0x80,0xf5,0x9a,0xcb,0xbd,0xe7,0xad,0x34,0xe7,0xdc,0x03,0x9e,0xaf,0x32,0x4e,0xe3,
-0x63,0x6e,0xa6,0x1a,0xce,0x4d,0x9b,0xa4,0xb9,0x69,0x34,0x0f,0xfd,0x72,0x08,0xfa,
-0xc0,0x07,0x1e,0xd7,0x0f,0xd4,0x19,0xb3,0xeb,0x12,0xe3,0x63,0x13,0xe1,0x3d,0x49,
-0x4a,0x8c,0x4f,0xfa,0xfd,0xed,0xa2,0xdf,0x7b,0x5d,0x97,0xbc,0xc1,0xe9,0xb6,0x60,
-0x68,0xaa,0x2d,0x24,0xc5,0x34,0xb7,0x62,0x5c,0x09,0xb1,0x39,0x2c,0xa1,0x19,0xb6,
-0x7f,0x25,0xf4,0x6c,0xe6,0xca,0x33,0x76,0x0c,0xe7,0xb6,0xcc,0xc0,0xcc,0xb5,0x2b,
-0x88,0xe9,0x90,0x73,0x0f,0xb9,0x2f,0x86,0x98,0x9f,0x8c,0x7a,0xee,0x39,0x62,0x3a,
-0xeb,0x3f,0x88,0x0b,0xc7,0x74,0xf5,0xbc,0x14,0xde,0x9f,0x4b,0xd2,0x32,0xaa,0x67,
-0xa0,0xf1,0x73,0x6e,0xb8,0x5a,0x8b,0xba,0xbe,0xae,0xbe,0x6e,0x33,0x7e,0x1e,0x11,
-0x77,0x34,0x8e,0xf3,0x39,0x56,0xf8,0x7f,0xe4,0xb9,0x3a,0x8f,0x6f,0xcf,0xb3,0x69,
-0xe6,0x72,0xd9,0x63,0x8d,0x1c,0x40,0x58,0x2e,0x81,0xc7,0x61,0x15,0x26,0xab,0xff,
-0xd6,0x30,0x5e,0xba,0x05,0x27,0xdd,0x4c,0xb3,0x1d,0x56,0x03,0xe6,0x3e,0x0f,0xc5,
-0xac,0x3b,0x95,0x97,0x18,0x5f,0x63,0x65,0x9f,0x6d,0x66,0x46,0x54,0xe6,0x87,0xb7,
-0x77,0x7c,0xd8,0xf1,0x20,0xae,0x03,0x7b,0xd4,0x1e,0xc6,0x75,0xc2,0xda,0xf5,0x70,
-0x67,0x57,0xd7,0xc3,0xf8,0xae,0x27,0xed,0xf1,0x4f,0x9e,0x3c,0x4a,0x90,0xa2,0xfb,
-0x51,0x42,0x77,0xf7,0xa3,0xc4,0xee,0x9e,0xf6,0x84,0x9e,0x9e,0x47,0x89,0x3d,0x3d,
-0xed,0x49,0x3d,0xdd,0xed,0xc9,0xdd,0x30,0x5f,0x8d,0xc7,0x74,0xe5,0xbc,0xd4,0xdd,
-0x5d,0x52,0xff,0xf9,0x56,0xaf,0x91,0xd7,0xa6,0xab,0xbc,0x12,0xd0,0x43,0x58,0xab,
-0x17,0x5d,0x95,0x5f,0x52,0x9c,0xd3,0xb1,0xaa,0xb9,0xab,0x22,0x2f,0xe7,0x7d,0x68,
-0x18,0x3f,0xef,0xef,0x38,0xdc,0x0f,0x01,0xfd,0xe6,0xa0,0x6f,0x67,0xf9,0x76,0x56,
-0x33,0xef,0xeb,0xcc,0x96,0x6a,0xe7,0x58,0x37,0xef,0x62,0x3a,0xb8,0x23,0xfd,0xca,
-0x1a,0xba,0xc8,0xcd,0x05,0x0c,0xef,0x7f,0x72,0x8c,0x6a,0xe9,0x4f,0x5e,0x21,0x3c,
-0x4f,0xf9,0x79,0xf1,0x7c,0xb3,0xfb,0xcd,0xb0,0xf3,0x4f,0x58,0x93,0x77,0xc5,0x26,
-0x7f,0x74,0x3b,0xeb,0x23,0xc2,0xf0,0x33,0x56,0xf4,0x7d,0x15,0xf8,0x39,0xd6,0xcd,
-0x01,0xcb,0x45,0x7f,0x38,0xe8,0x53,0x43,0xfd,0x9b,0xd8,0xaf,0x06,0x7a,0x38,0xb7,
-0xf9,0x8c,0xdb,0xd3,0x97,0xe7,0x99,0xec,0xcb,0x9b,0x84,0x7d,0xa8,0x99,0x33,0xff,
-0x76,0x29,0xcf,0x2e,0xea,0xe0,0x5c,0x83,0xc5,0xae,0xf1,0x81,0xa2,0x71,0xd7,0x40,
-0x91,0xcb,0x35,0xa0,0x77,0x39,0x87,0xf4,0x4e,0x47,0xbf,0xde,0xf1,0xd9,0xdd,0xd3,
-0x9f,0xe5,0x9d,0xde,0x97,0x87,0x7f,0xcd,0x3f,0x70,0x43,0x3c,0xc7,0xf9,0xe7,0xb2,
-0x1e,0x6e,0xd6,0x52,0x39,0xbb,0x30,0x5c,0xba,0x00,0xba,0x38,0x75,0xcf,0xf9,0x94,
-0x8d,0xcb,0xb7,0x8b,0x9e,0x32,0x3c,0x2f,0x5f,0xb0,0x9e,0x5b,0x00,0x0f,0xb8,0xc0,
-0x48,0x71,0x60,0x69,0xb4,0x62,0x09,0x78,0x39,0xcd,0x55,0x2b,0xf1,0xae,0x0e,0x15,
-0xae,0x4a,0xde,0x70,0x80,0xe7,0x76,0x83,0xe4,0x27,0x33,0xef,0x10,0x7d,0x64,0x44,
-0x4c,0x67,0xbd,0xe7,0xa0,0x67,0xa7,0x3a,0x39,0x9b,0xb1,0x56,0x8f,0x79,0x75,0x5e,
-0x0f,0x07,0xf9,0x75,0xc8,0xb9,0xaf,0xd8,0x8d,0x2b,0xd0,0x73,0x0e,0x1e,0x32,0x5e,
-0xbb,0xd1,0xbb,0x6a,0xad,0x5a,0x0d,0x59,0xcb,0x42,0x80,0xe7,0xc1,0xd1,0x8a,0x60,
-0xc0,0x5a,0x19,0x00,0x3c,0x5f,0xb5,0x1b,0x04,0x4c,0xaf,0xf1,0xfb,0xc7,0x6a,0xfd,
-0x3e,0x47,0xad,0xcf,0xeb,0xac,0xf3,0x82,0x16,0x0e,0x7a,0xd5,0x40,0x27,0x7f,0xf7,
-0xc3,0xc2,0xbb,0x87,0xd3,0xf6,0x1c,0x56,0x78,0x8f,0x31,0xfd,0x1b,0x8f,0xed,0xaa,
-0xeb,0x10,0xe4,0xdb,0xa7,0x06,0x6b,0xa7,0xc0,0x3b,0x86,0x82,0xf0,0x9c,0x9f,0xc3,
-0x42,0xde,0xaf,0x2d,0x58,0x47,0x47,0xec,0x76,0x11,0x37,0xa7,0x7d,0xd1,0x43,0xc6,
-0xd5,0x84,0x3a,0x38,0xc8,0xbf,0x0f,0xb7,0x1b,0x86,0x9b,0x8d,0x87,0x9b,0x0f,0x1f,
-0x4a,0x3e,0x7c,0xfb,0xfa,0x6b,0xb7,0xe7,0x2d,0x0d,0xf3,0xd8,0x93,0x2e,0x6a,0xd9,
-0x59,0x4e,0x9d,0xf1,0x74,0x39,0xa8,0x67,0x2d,0xe4,0x6e,0xa1,0x9e,0x73,0xf4,0x8e,
-0x69,0x09,0x29,0xfc,0x65,0x26,0x59,0xb0,0x19,0xa9,0x97,0x44,0xec,0x16,0xb1,0x7c,
-0x4a,0xc0,0xf2,0x29,0x9a,0x85,0x0e,0x33,0xd1,0x3d,0x43,0x2d,0x9e,0xb7,0xde,0x3c,
-0xf9,0x56,0x52,0x62,0x6c,0x12,0x7b,0x1f,0x4a,0xf4,0x99,0x25,0x23,0xa6,0xc6,0x11,
-0x7a,0x1e,0x61,0x36,0x9b,0xa5,0x86,0x98,0x2c,0x7a,0xc4,0x50,0xaf,0xf9,0x25,0xae,
-0x2f,0x8d,0x71,0x75,0x79,0x7e,0xea,0xda,0xf4,0x95,0x35,0xe0,0xec,0xb0,0x32,0xbe,
-0x0e,0x98,0x0e,0xf3,0xd5,0x6e,0xfc,0xba,0x88,0xfa,0xcf,0x35,0x7a,0x07,0xd5,0x9a,
-0xf5,0x88,0x9e,0x33,0x6a,0x4e,0xbe,0x49,0x9e,0x7d,0x2b,0x1d,0xbb,0x66,0xee,0x7d,
-0x13,0x2c,0xd3,0xe2,0xe7,0x0a,0x5c,0x8f,0x52,0x71,0x75,0x0d,0xee,0x1e,0xa5,0xf8,
-0x92,0xbc,0x1f,0x76,0x2f,0xc0,0xe3,0x6d,0xb4,0x0a,0x8b,0xb5,0xfe,0x06,0x8e,0x03,
-0xab,0xeb,0x00,0x9b,0xe5,0x90,0xb5,0xb4,0xd7,0x5b,0x61,0xda,0x56,0x5f,0xd7,0xf4,
-0x07,0x8a,0xe0,0xaf,0xa6,0xf6,0x12,0xe0,0x7b,0x4d,0x32,0xd2,0xa3,0x33,0x7e,0xf7,
-0xfe,0x8e,0xdf,0xa9,0xfb,0xd5,0x90,0x9b,0x3f,0x8c,0x17,0xf8,0x78,0x7c,0x17,0xe3,
-0xe6,0x18,0x0f,0x89,0xa3,0xcb,0x91,0x44,0x1c,0xbd,0x1d,0xfc,0x5e,0x49,0x13,0x27,
-0x61,0xfa,0x23,0xb9,0x7e,0x0e,0xf3,0xd5,0xc0,0x1f,0x6e,0x5b,0xf7,0x70,0xea,0xfd,
-0xa8,0xc8,0xef,0xa1,0xd6,0xcf,0x50,0xe7,0x87,0x22,0xdd,0x13,0xb1,0xef,0x2b,0x2d,
-0x49,0x28,0x7d,0x7c,0x5f,0xd4,0xc3,0x75,0x64,0x50,0x98,0x32,0x29,0x3a,0x61,0xcd,
-0x12,0x23,0xbb,0x0f,0xb1,0x1d,0xfb,0xd6,0x64,0x5c,0x97,0x34,0xee,0x62,0x1d,0x5d,
-0xe6,0xe7,0xac,0x8e,0x2e,0xf2,0xf3,0xdf,0xa4,0xde,0x48,0x49,0x89,0x7d,0xe1,0x5e,
-0x2d,0x75,0x0e,0x47,0xf3,0x3c,0x8e,0x70,0x8c,0xf5,0x82,0x2a,0xee,0x93,0xc4,0xf5,
-0xd0,0xc1,0x84,0x43,0xf7,0xbf,0x38,0x7e,0xdf,0xd6,0xfb,0x9a,0x80,0xdf,0xaf,0x89,
-0x73,0x52,0x41,0x17,0xf7,0xda,0x18,0x04,0xef,0xe1,0xee,0xee,0xcb,0x73,0x4f,0xf4,
-0xe6,0x4d,0x4c,0xf6,0x9e,0x9e,0x9c,0xee,0x39,0x35,0x3d,0xd3,0x7b,0x72,0x66,0xb6,
-0x27,0x77,0x76,0xba,0xf7,0xd4,0x34,0xcc,0x40,0x47,0x3d,0x9c,0xa8,0x85,0x03,0x6d,
-0xbb,0xab,0xbf,0x50,0xc0,0xf1,0x82,0x71,0x77,0x7f,0xa1,0x7b,0xa2,0xff,0xec,0xc4,
-0xa4,0xf9,0xec,0xa4,0x7b,0xa0,0xc8,0x8d,0xb9,0xf7,0xa1,0x92,0x31,0x9b,0x59,0x6f,
-0xbb,0xf5,0xde,0x2b,0xb7,0xd2,0x75,0x49,0xe9,0xdb,0xce,0x7d,0xfd,0x04,0x1b,0xe0,
-0xf9,0xe3,0xfb,0xfa,0xc7,0x9e,0x91,0x73,0x1e,0xa8,0xa1,0x03,0x86,0xcf,0x0f,0x97,
-0xce,0x2f,0x0d,0xe9,0x97,0x66,0x46,0x2a,0x66,0x78,0x5f,0x19,0xcd,0xf9,0x6a,0x36,
-0xf2,0x91,0x61,0x7e,0x32,0x0b,0x96,0x73,0x0b,0x81,0xa1,0xc2,0xc0,0xea,0x50,0xd1,
-0xea,0xf2,0x48,0xe9,0xf2,0xe2,0xe8,0xb9,0xc5,0x79,0x5b,0xf5,0xfc,0x9c,0xcd,0x30,
-0x07,0x9a,0x77,0xf0,0x7e,0x45,0x8f,0x57,0xab,0x01,0x67,0xb0,0x00,0x3f,0xa7,0x7e,
-0xb5,0x5a,0xd9,0x1b,0x0e,0xb0,0xdd,0x21,0xfa,0xc3,0xb1,0x5e,0xf4,0x31,0xc0,0xf6,
-0xfa,0x05,0x5c,0xc7,0x1a,0x16,0x48,0xd3,0xde,0xb0,0xb8,0xe0,0x84,0xfd,0xc6,0x05,
-0x49,0x03,0x27,0xe0,0x3a,0xe4,0xe0,0x59,0x2f,0x3a,0x7a,0xc3,0xb1,0x18,0x83,0xa8,
-0x13,0x78,0x78,0xbd,0xe4,0x15,0x07,0x2b,0x70,0xf3,0x65,0x17,0xe5,0xdd,0x6d,0xbd,
-0x35,0xb6,0x37,0x5e,0xcf,0x7e,0x23,0x3e,0x2e,0x5a,0xe1,0x23,0x1a,0xd6,0xc7,0xa4,
-0xce,0xc3,0x0a,0x9f,0x19,0xea,0xdb,0xa5,0xfe,0x73,0x9a,0xaf,0x26,0xf5,0xae,0x89,
-0xe1,0x1b,0x67,0x73,0x52,0x5b,0xc4,0x19,0x6b,0x2d,0x38,0x83,0x05,0x66,0xad,0xc0,
-0xec,0x54,0x9a,0xc3,0x72,0x61,0x15,0xe6,0xae,0x2d,0xda,0xce,0x2f,0x7e,0x7c,0x23,
-0xff,0xe3,0x43,0x2f,0xef,0x3d,0x74,0xf5,0x5f,0x8f,0x5f,0x75,0x0f,0x35,0xba,0x71,
-0x96,0x2a,0xce,0x4d,0xbd,0xb8,0xca,0xaf,0xb2,0x2e,0x4e,0xd4,0xb9,0xa3,0xa7,0x4c,
-0x2b,0xe7,0x2f,0x23,0x70,0xf5,0x49,0xe2,0xe6,0xd2,0xf1,0x49,0xe6,0x23,0x47,0x7c,
-0x9d,0xe6,0x9f,0x8b,0x21,0xcd,0x47,0xbf,0x8c,0xfb,0x8b,0x63,0x17,0x16,0x6f,0xfe,
-0xf6,0xec,0xcd,0xe4,0xa4,0x84,0x64,0xfe,0xbd,0x78,0xfb,0xdf,0x4f,0xbe,0x3d,0x6b,
-0x6f,0x9d,0x0d,0x4e,0xb5,0x05,0x83,0xd3,0x02,0xa6,0x0b,0x38,0x8e,0xfb,0x53,0xc4,
-0xd5,0xd9,0x3c,0x74,0xf2,0x72,0x3d,0xbf,0x81,0x2b,0x78,0xb9,0x2a,0xfa,0xd5,0x44,
-0xed,0xfb,0x54,0xab,0xa8,0x69,0x17,0xe7,0xb5,0x88,0x7d,0x6b,0x50,0x97,0xe7,0xf9,
-0x39,0xf6,0x0f,0x42,0xce,0x7d,0xa7,0x86,0x1e,0x8e,0xf5,0xa7,0x6d,0x95,0x67,0x8f,
-0xe6,0xf2,0xeb,0x1a,0x58,0xae,0xe6,0xc7,0x5a,0xd7,0x58,0x89,0x5b,0xf3,0xcf,0x51,
-0xe7,0x8d,0x35,0xb8,0x37,0x8f,0xd5,0x6a,0x5e,0xb1,0xed,0x7f,0xdc,0x68,0xc5,0xae,
-0x02,0xb3,0xf9,0x63,0x0a,0xbe,0xaf,0x71,0xdf,0x10,0xf6,0x3a,0xa3,0xc2,0xff,0x6e,
-0xc5,0xef,0x89,0x56,0x72,0x7c,0x35,0xb7,0x97,0x7e,0x0f,0xf7,0xda,0x22,0xbd,0x66,
-0xf5,0xcf,0x50,0xfc,0xec,0x68,0xf9,0x35,0x46,0xba,0xa7,0xd8,0xec,0x7d,0x80,0x7e,
-0x35,0xd4,0xb7,0x3f,0xd8,0xc9,0xf5,0xab,0x31,0x1f,0x77,0xa6,0x6f,0x4f,0x50,0xcd,
-0x63,0xe1,0x7b,0xd6,0x92,0x4d,0x72,0xef,0xb9,0xba,0x57,0x4d,0xad,0x87,0x13,0xf5,
-0xed,0x2f,0x70,0xd5,0x56,0xbc,0x76,0xee,0x35,0x6a,0x3e,0x47,0xe3,0x73,0xd1,0xba,
-0x47,0x60,0xf7,0x09,0xa0,0x6f,0x6f,0xff,0x1b,0xe8,0xe1,0x32,0x48,0x0b,0x87,0x6b,
-0x66,0x1f,0xd3,0xb6,0x53,0xdf,0x5a,0xb6,0x99,0xf5,0xab,0xb1,0xc0,0xda,0xb9,0xc8,
-0xd1,0xa1,0x47,0x4d,0xee,0x57,0x3b,0x3a,0x20,0xf5,0x9d,0x77,0xe6,0x60,0xaf,0x1a,
-0xf3,0x93,0x61,0x78,0xae,0x75,0x0e,0x6b,0x9e,0xd7,0xd1,0x1a,0xcf,0xe1,0x3e,0x6f,
-0xfe,0x7f,0x4b,0x0b,0xbb,0x79,0xbd,0x01,0x9f,0xb7,0x51,0x78,0xec,0x08,0xd7,0x84,
-0xda,0xea,0x94,0xda,0x27,0x0f,0x72,0x9f,0x30,0x1c,0x07,0x0c,0x87,0x40,0x0c,0xef,
-0x3d,0xed,0x86,0xf9,0x6a,0x9e,0xde,0x53,0x1e,0xe8,0x45,0xf7,0xf4,0xe6,0x79,0x20,
-0x80,0x97,0x43,0x00,0x96,0x4f,0xf5,0xe5,0x4d,0xb9,0xfb,0xf2,0xdd,0x90,0x7b,0x67,
-0xba,0x76,0xc0,0x75,0xf4,0x93,0xe9,0x2f,0x1c,0x77,0x0f,0x14,0xb8,0xdd,0x03,0x85,
-0x18,0xae,0xc1,0x22,0xe4,0xe7,0x80,0xe9,0xce,0xc1,0x12,0xe7,0x50,0x67,0xd1,0xd0,
-0x9b,0x6f,0x1c,0x7e,0x73,0xd7,0xae,0xb8,0x5d,0xcf,0x7f,0x66,0xbc,0xd8,0x06,0x78,
-0x4e,0xf3,0x58,0xce,0x4d,0x82,0x37,0x1c,0xf4,0x9c,0x93,0x6f,0x7b,0xd5,0x34,0x9f,
-0x73,0xe7,0x71,0x5c,0x8d,0xe7,0xf2,0x4c,0x16,0xe3,0xcc,0x8c,0xd5,0x38,0x03,0xbd,
-0xe7,0x94,0x73,0x87,0x99,0xe7,0x02,0x7e,0xdb,0x0c,0xe2,0x5c,0x16,0xe3,0x1c,0xf4,
-0xa8,0x51,0xd4,0x89,0x6b,0xed,0x1c,0xfa,0xc4,0x89,0xab,0x84,0xe5,0x0c,0xbf,0x1d,
-0x22,0x4f,0x17,0xb8,0x38,0x45,0x83,0x1c,0x4e,0xea,0x53,0x5b,0x70,0x36,0x22,0xb6,
-0x13,0x4f,0x6f,0x58,0x5a,0x1e,0x13,0x3d,0x65,0xc0,0xc3,0x1d,0x67,0xb1,0xd4,0x3f,
-0x45,0x9f,0x57,0x49,0x13,0x47,0xf3,0x58,0x68,0x7e,0x6a,0xb3,0xa8,0x8b,0x6b,0x7e,
-0x3a,0x67,0x6f,0x9c,0xbb,0xf7,0x49,0xf1,0xbd,0x74,0xdd,0xde,0x74,0xad,0x7a,0x69,
-0xd8,0xbd,0xb3,0xea,0x5a,0x4c,0xf3,0x52,0xeb,0xdd,0x34,0xff,0xbc,0x45,0x9c,0x77,
-0x2e,0xea,0xdc,0x27,0x98,0xce,0xbd,0x45,0xe6,0xe9,0x13,0x2d,0xf2,0xdc,0x73,0x01,
-0xa7,0x7d,0x13,0xad,0x3e,0x9c,0x7f,0x2e,0x84,0xcf,0xd3,0xea,0x1b,0xec,0xa8,0x1f,
-0x2c,0x2f,0xcf,0x2a,0x37,0xd6,0x64,0x1a,0xbb,0x1f,0xd5,0x76,0xfb,0x26,0x2e,0xfa,
-0x70,0x06,0xaa,0x80,0xdd,0xab,0x1e,0x71,0x86,0xaa,0xa7,0x55,0xc2,0x75,0xc0,0x67,
-0xc0,0x69,0x98,0x79,0x8e,0x73,0x52,0xa7,0x68,0x3e,0xaa,0x72,0xfe,0x39,0x1f,0xf0,
-0x9c,0xcb,0xe2,0x0c,0xd5,0xcb,0x88,0xc1,0x78,0x5c,0x38,0x06,0x8f,0x03,0x53,0x6d,
-0x01,0xc0,0xf2,0xd5,0xc9,0xcb,0xab,0x5f,0xfe,0x77,0xc5,0x97,0x07,0x0e,0xec,0x3b,
-0xa0,0x78,0xed,0xc2,0xfa,0xf6,0xdb,0xa7,0x04,0x3c,0xbf,0x38,0x0b,0xd8,0x1d,0x9c,
-0xbe,0x12,0x64,0x79,0x75,0xda,0xbf,0x12,0x92,0xe6,0xa5,0x22,0xae,0x43,0xbf,0x9a,
-0xe8,0x1d,0xc3,0x66,0xa4,0xa2,0xc6,0xfd,0x92,0xac,0x71,0x17,0x02,0x8e,0x01,0xce,
-0xb3,0xb9,0x2d,0x21,0xf7,0x85,0xd0,0x9d,0xff,0x38,0x7b,0x27,0x2b,0x2d,0x29,0x0b,
-0xbc,0xea,0xd5,0xf3,0x4f,0xd1,0xeb,0x32,0x3e,0x6a,0x37,0xd4,0x0d,0x59,0x3e,0x5e,
-0x31,0xf3,0x34,0x56,0xce,0xc9,0x6b,0xd6,0xda,0xf9,0x9c,0x7c,0x8c,0x52,0x07,0xaf,
-0xe0,0xf4,0xd1,0x5c,0x9d,0x7d,0x33,0xcd,0x5c,0x54,0xb8,0xd6,0x42,0x1d,0xd2,0x75,
-0x8b,0x5d,0xcf,0x54,0xcf,0x55,0x7f,0x1f,0x7f,0xe1,0xd3,0xdc,0x5e,0x10,0x4b,0x9e,
-0xff,0xbb,0x7e,0xe4,0xf7,0x3f,0xc7,0x77,0x28,0xee,0x49,0xa2,0x95,0xbf,0x4f,0xf1,
-0xde,0x30,0x2c,0xe4,0xce,0x4b,0xec,0x3f,0xbf,0x05,0x7a,0x38,0x71,0xfe,0x39,0xf0,
-0x73,0x95,0x7f,0xbb,0xe4,0xe1,0x2e,0xe0,0xba,0x5c,0x37,0xe7,0xb9,0xb9,0x38,0x63,
-0x8d,0x9b,0xc9,0x42,0xbd,0x6a,0x7c,0xfd,0x9c,0xfa,0xd5,0xf8,0xcf,0x72,0xbb,0xaf,
-0x4d,0xeb,0xfe,0x46,0x7d,0x6f,0xa5,0xbe,0x87,0x51,0x73,0xf3,0xcd,0x7a,0xd0,0xcb,
-0xcb,0xe4,0xfe,0x73,0xe0,0xe8,0xd4,0x7f,0x0e,0x5e,0x32,0xb4,0x02,0x9e,0x83,0xdf,
-0x2b,0x6a,0xe2,0x3a,0x59,0x64,0x0b,0xc7,0xc0,0x4b,0x26,0x7b,0x40,0xf6,0x6d,0xcf,
-0x1e,0x62,0x73,0xd0,0x87,0xbb,0x8e,0x0c,0x5b,0x3a,0x73,0x2c,0x96,0xce,0x23,0x96,
-0x91,0xae,0x9c,0x11,0xc0,0x74,0xf4,0x93,0x79,0x4e,0x3d,0x1c,0xff,0xfa,0x23,0xde,
-0xbb,0x69,0xe4,0x3b,0x78,0xad,0xa0,0xa4,0x11,0x8c,0xa1,0xff,0x5b,0x1e,0xc7,0xe1,
-0x7e,0x1f,0x7a,0xd5,0x0f,0xee,0x8f,0x39,0x78,0xfd,0x5a,0xda,0x75,0x4b,0xc7,0x29,
-0x0b,0xcc,0x4a,0x75,0xf7,0x9d,0x76,0xbb,0x7b,0x4e,0xb9,0x3d,0xbd,0x27,0x3d,0xd3,
-0x3d,0xb9,0xd3,0xb3,0x3d,0xaf,0xce,0xce,0xf6,0x9c,0x98,0x9d,0xe9,0xc9,0x9d,0x01,
-0xfc,0xf6,0xf4,0x9d,0xf6,0x80,0xb7,0x0c,0xcb,0xbb,0x53,0x08,0x78,0x0e,0xfd,0x69,
-0xa2,0x77,0xbb,0x73,0xa0,0x08,0xf7,0x21,0xdf,0x0e,0x3d,0xe8,0xb8,0x0a,0x01,0xf5,
-0x73,0xd7,0xa0,0xde,0x05,0x78,0xee,0x1a,0x82,0xb5,0xc4,0xf9,0xed,0xd7,0x67,0xbe,
-0xad,0x28,0x7b,0xa9,0x42,0xb8,0xa8,0xc4,0x3d,0xcf,0xfb,0xf3,0x22,0x1b,0xbc,0x67,
-0xa7,0x4e,0x1e,0x38,0xd5,0x71,0xbf,0x58,0xc4,0xf3,0xaa,0x29,0xbe,0x57,0x0d,0xb9,
-0xb9,0xe4,0xf7,0x6a,0x98,0x9a,0x19,0xad,0x9e,0x81,0x5c,0x3c,0xf8,0xc2,0x49,0xf3,
-0x58,0x38,0x7e,0x2e,0x61,0x3a,0xd3,0xc4,0xd9,0x6a,0x66,0xff,0x87,0xbb,0x6b,0x71,
-0x8a,0xea,0x4a,0xf3,0xdd,0x02,0x2d,0x6f,0x01,0x75,0x41,0x45,0xd0,0xa8,0x31,0x6a,
-0x4a,0x79,0x35,0x20,0x0f,0x45,0x11,0x8c,0xc8,0x33,0xb3,0x95,0x99,0x9d,0xda,0xd9,
-0xa9,0x64,0x36,0x4e,0x6a,0x13,0x2b,0xb5,0x93,0x99,0x64,0x26,0x6e,0x45,0x33,0xb5,
-0x66,0xaa,0xa6,0xac,0xda,0x54,0x92,0xa9,0x4d,0x32,0x31,0x3b,0xd2,0xa8,0xbc,0xa1,
-0xbb,0xa1,0x41,0x79,0x34,0xdd,0x34,0x4f,0x31,0x26,0x02,0xe2,0xee,0xce,0x1f,0xb3,
-0xf7,0xfb,0xbe,0x73,0xce,0x3d,0xe7,0xdc,0xdb,0x0d,0x26,0x66,0x6a,0x67,0x6e,0xd5,
-0xa9,0x7b,0xfb,0xd2,0x40,0xf7,0xed,0xdb,0xe7,0x77,0xbe,0xef,0xfb,0x7d,0xbf,0x1f,
-0xf7,0x57,0x93,0xf1,0x1c,0x38,0x72,0x0b,0x77,0x6b,0x11,0xcb,0x09,0xc7,0x99,0x36,
-0x1c,0xcb,0xb7,0x03,0xd6,0x73,0x1c,0x57,0xb0,0x9d,0xe7,0xe0,0x65,0x4c,0x37,0x62,
-0x73,0x3e,0x30,0x46,0xc7,0x1e,0x74,0x1e,0xab,0x9b,0x3e,0xe8,0x9c,0xdb,0x6e,0xe2,
-0xb9,0xe9,0x7f,0x0e,0x78,0x0e,0xfd,0x6b,0x7d,0xed,0x27,0xfb,0x6a,0x6a,0x72,0xb1,
-0x7f,0xd0,0x2e,0xae,0xb2,0x9b,0x5f,0xe5,0xf8,0x03,0xea,0xe7,0xc4,0x87,0x63,0xde,
-0x6a,0x12,0x27,0x4e,0xe8,0xc3,0xa1,0xee,0x6b,0x83,0xad,0xe7,0xb9,0x82,0xed,0xa1,
-0xc6,0x87,0xb7,0x3e,0x3b,0x79,0xab,0xae,0x76,0x7f,0xdd,0xa7,0xff,0x51,0xfd,0x29,
-0xf0,0xe4,0x01,0xe7,0x21,0x76,0x7f,0x34,0xd5,0xc0,0x38,0x70,0x2c,0xe7,0x0e,0xfc,
-0x76,0x11,0x97,0x1b,0x23,0xd2,0x64,0xe2,0x3a,0xf3,0x47,0x5d,0x89,0xd0,0xb1,0x89,
-0xeb,0x1c,0xef,0x5b,0x57,0x79,0x2c,0x4e,0x38,0xde,0x26,0x70,0x9d,0x63,0x79,0x7f,
-0x7b,0x5d,0xff,0x81,0xfd,0xd9,0x07,0xec,0xee,0x1f,0x81,0xe7,0x88,0xe1,0xf0,0xbb,
-0x2f,0x3e,0x02,0x2c,0xe7,0x78,0xae,0xd6,0xce,0xdb,0xd6,0x38,0x7f,0x5d,0xe6,0xc5,
-0x91,0xd6,0x2b,0xcf,0xbb,0x13,0x3f,0x8e,0xe3,0xba,0xdc,0xaf,0xb6,0x73,0x7b,0x8a,
-0xa2,0x27,0x83,0x23,0xc1,0xd4,0x8a,0x93,0xfb,0xd8,0x90,0x2b,0x14,0x6f,0xe2,0x39,
-0x7e,0xcf,0xe3,0x6c,0x7a,0xda,0xe2,0x55,0xfd,0x38,0xd1,0xdf,0xb6,0xc9,0xda,0xdf,
-0x66,0xcb,0x8d,0x97,0xf9,0x74,0x51,0xea,0xc0,0xb6,0x5c,0x3a,0x47,0x8c,0x5e,0x76,
-0x19,0x9b,0xec,0x62,0xd7,0xa7,0xf4,0xe5,0xff,0x4e,0x7f,0xcd,0x19,0x65,0x6f,0x77,
-0xcc,0xb1,0x98,0xbf,0x07,0x19,0x7f,0xe5,0x7c,0xb2,0xc3,0xfe,0x7a,0xe8,0x5c,0x45,
-0xdb,0xba,0x3a,0xab,0x39,0xf3,0x79,0x3d,0x2f,0xd7,0x99,0x77,0xf9,0x52,0xfc,0x65,
-0xcc,0xb1,0xb7,0xbb,0xba,0xba,0x3d,0xae,0x6e,0x1c,0xac,0x7e,0x0e,0xf9,0xf6,0x1e,
-0xcf,0x66,0xa9,0x7e,0x9e,0xd4,0xdb,0xdb,0x9e,0xd4,0x0b,0xb5,0x73,0xaa,0xa3,0x27,
-0xf7,0xf5,0x74,0xa4,0xf4,0x08,0xaf,0x54,0x1b,0xbd,0x57,0xd2,0x6f,0x4f,0xfd,0x0c,
-0xf5,0xe1,0xa4,0xf7,0xbb,0xde,0xdc,0x61,0xf9,0x8c,0xa3,0xe4,0xe7,0x95,0xfb,0x46,
-0xd2,0x3f,0x17,0x5a,0x32,0x4e,0x9b,0x5a,0x84,0xd4,0x9b,0x59,0x79,0x3c,0xa9,0xf2,
-0xd6,0xf5,0x5d,0xb7,0x54,0x3d,0x99,0xdd,0x5e,0x81,0xe5,0x9d,0x79,0xa8,0xdf,0x2e,
-0x7c,0x58,0x3a,0x4d,0x1f,0x16,0xf2,0x4c,0x25,0x1c,0x87,0x3d,0xe8,0xbd,0x02,0x96,
-0x07,0xba,0xf6,0x06,0x02,0xdd,0x7b,0xf1,0x98,0xfb,0xa0,0x63,0x7c,0xbe,0x35,0x2e,
-0xcb,0x76,0x5e,0xb4,0xde,0x36,0xca,0x1a,0xd6,0xb2,0x7e,0x89,0x52,0x5f,0x90,0xeb,
-0x31,0x32,0xd7,0x5f,0xd6,0x9c,0x41,0x0c,0x67,0x9a,0xb0,0x5b,0x12,0x49,0x6b,0x66,
-0x7b,0x9a,0x73,0x7b,0xd1,0x73,0x89,0x45,0x1f,0x5e,0xc9,0xff,0x30,0xd8,0x7d,0x28,
-0x08,0x7a,0x32,0x33,0x7d,0x87,0x66,0x10,0xcb,0x7b,0x0f,0xce,0x2f,0xf4,0x1d,0x5c,
-0x58,0xec,0x3b,0xb8,0xb8,0xd8,0x7b,0x70,0x71,0xa1,0xf7,0xb9,0x05,0xc0,0x74,0xf4,
-0x41,0xf7,0x92,0x86,0x3b,0xc6,0xe5,0xc6,0xe0,0xda,0x70,0x50,0x3b,0xc7,0x7e,0x35,
-0xc6,0x81,0x13,0x78,0xee,0xa3,0x5a,0x3a,0xc5,0xea,0x25,0xa1,0xa9,0xa1,0xd2,0x29,
-0xc0,0x74,0xe0,0xc7,0x7d,0x70,0xe5,0xd0,0x07,0xf9,0x79,0x29,0xf9,0x4e,0x78,0x57,
-0xdf,0xd7,0xe6,0xe4,0x78,0x0e,0x7e,0x2c,0xee,0x5b,0xb2,0xaf,0x1a,0xf7,0x4d,0x45,
-0x6d,0x19,0xf0,0x4a,0x1d,0x25,0x2d,0x99,0x7b,0x81,0xe3,0xf7,0x96,0x87,0x8a,0x97,
-0x97,0x02,0x15,0x4b,0xa6,0xaf,0xda,0xa9,0x39,0xbe,0x57,0xf0,0x7c,0x8c,0x71,0xdc,
-0xc7,0x24,0x6f,0x16,0xe0,0xc6,0xb1,0x98,0x9c,0x74,0x5f,0xcf,0x2c,0xa0,0x3e,0x1c,
-0xd3,0x7a,0x5d,0x18,0xaf,0x5b,0xe0,0x7b,0x9e,0x6b,0x87,0x98,0x5c,0xe4,0xdb,0xf1,
-0xb8,0x7e,0x51,0x89,0xcf,0x27,0x59,0x7c,0x8e,0x58,0x7e,0x56,0x60,0x39,0xe9,0xc3,
-0x81,0x9e,0xcc,0xd9,0xfb,0x4b,0xc1,0x17,0x96,0x20,0x16,0x17,0xbd,0xe8,0x5c,0xef,
-0x55,0xd2,0x6d,0x1f,0xeb,0x3b,0x3d,0xf6,0x93,0x1f,0x1d,0xf8,0x49,0x62,0xa2,0x2b,
-0xd1,0xf2,0x5d,0xd4,0x72,0x7b,0xd1,0xe2,0x05,0xf0,0x57,0x8b,0xf8,0xcf,0x44,0x56,
-0x82,0xf5,0x2b,0xab,0x93,0x67,0x56,0xc5,0x08,0x9e,0x5d,0x05,0x8e,0x1c,0xf4,0xa0,
-0xf1,0x7a,0xba,0x3d,0x8e,0x37,0x62,0x6c,0x0e,0x7b,0xc0,0xfe,0xb1,0xbe,0xba,0xb1,
-0xcf,0x3f,0xac,0xfe,0xfc,0xfe,0x64,0xe3,0x7d,0xc4,0x72,0x16,0x9b,0x3f,0x0a,0x35,
-0xa0,0xfe,0x2b,0xf2,0xe0,0xc2,0x0d,0xa2,0x66,0x8e,0x75,0x75,0xde,0x8b,0x1e,0x66,
-0x39,0xf6,0x68,0xf9,0x75,0xc0,0x6f,0x88,0xcb,0x79,0x5e,0x7d,0x86,0xe7,0xd8,0x29,
-0xbf,0xce,0x8f,0x47,0xfb,0xce,0x8e,0x9e,0xad,0xdb,0x77,0xd6,0x92,0xf3,0x74,0xf0,
-0xf8,0x9c,0xf2,0xed,0x14,0x9f,0xb7,0x09,0x1c,0x07,0x5c,0xe7,0x18,0xce,0x71,0xfd,
-0xf1,0xec,0x8b,0x8f,0xe5,0xc7,0xbc,0xd6,0x0e,0xe7,0x71,0xcc,0xbd,0x68,0x1e,0xf3,
-0xf3,0xc6,0xb9,0x95,0xe9,0xd6,0x95,0x5f,0xbe,0x51,0xf2,0xcb,0xac,0xcc,0x94,0x2c,
-0xdb,0x7a,0xb8,0xae,0x11,0xa3,0xfd,0x6c,0xc3,0x35,0x75,0x8d,0xff,0xa6,0xc4,0xe3,
-0xda,0x3c,0x1a,0x0d,0xab,0x63,0xd5,0x88,0xe5,0xf8,0x5d,0xe9,0x5f,0xb7,0x9b,0xe7,
-0x6d,0x72,0xa8,0xeb,0xe1,0xf9,0x46,0xe6,0xd0,0xf5,0xce,0x2b,0x31,0x93,0xc3,0x7a,
-0x8f,0x47,0x5b,0x6f,0xd8,0xbe,0x76,0x3e,0x27,0x3b,0xd4,0xb9,0xd9,0xe2,0x73,0x6d,
-0x83,0x4d,0x0a,0x27,0x4c,0xd7,0x0e,0xd3,0xbc,0xc3,0x05,0x07,0xcc,0x65,0x6a,0x8c,
-0xec,0xcb,0x77,0xee,0xfb,0xed,0xa5,0xb8,0xdf,0x76,0xdd,0x48,0xe8,0xea,0x69,0x4f,
-0x30,0x30,0xdb,0xd5,0xd3,0xdb,0x9e,0xd0,0xdb,0xeb,0x71,0xd1,0x68,0xdf,0x4c,0x03,
-0x79,0x70,0x34,0xfa,0x3c,0x8c,0x0b,0x87,0x98,0x9e,0x2c,0xb8,0x70,0x42,0x4f,0x46,
-0xe4,0xdc,0xd3,0x15,0xbd,0x57,0x59,0xbf,0x5d,0x5c,0x27,0xe9,0x9a,0xf0,0x9f,0xad,
-0x77,0x9d,0xd6,0xe3,0xd0,0x29,0xbe,0x6d,0x72,0xad,0xd8,0xa9,0x5d,0x37,0xb6,0x47,
-0x7d,0xb8,0xeb,0x4c,0x1f,0xee,0xf6,0x6e,0x55,0x23,0xae,0x2b,0xcf,0xab,0xf6,0xac,
-0xed,0xc1,0x3d,0x8f,0xcd,0x31,0x4e,0x07,0xdf,0xf3,0x2e,0xf2,0x3e,0xc7,0x3c,0x3b,
-0x1f,0xe0,0x7f,0xce,0xb4,0x64,0x38,0xbf,0x5d,0xc7,0x73,0xbb,0x7b,0x4c,0x8e,0x7d,
-0xa2,0x5d,0x8b,0x68,0xef,0xdd,0xe2,0x81,0xce,0x7d,0x5b,0x12,0x54,0x9f,0x78,0xd9,
-0x73,0x0e,0xbc,0x5b,0xb6,0xa5,0x3a,0xb6,0xed,0xcc,0xda,0xb4,0xb3,0xe1,0x64,0x7a,
-0x83,0xe7,0xe3,0xfd,0x1e,0x88,0xcd,0xc3,0x7d,0x47,0xc2,0x90,0x67,0x8f,0xf4,0x1f,
-0x8e,0xc0,0x98,0xe9,0x3f,0x3c,0x33,0xd3,0x7f,0x64,0x06,0x6a,0xe7,0xe1,0x81,0xa3,
-0x61,0xe0,0xc7,0xa1,0x8e,0x8c,0x81,0xe1,0xa4,0x27,0x43,0x3d,0x6a,0x30,0x20,0x36,
-0x17,0x35,0x74,0xe4,0xc0,0xd1,0x00,0x4e,0x1c,0xe0,0x78,0xd8,0x57,0x1c,0x0e,0x7b,
-0x4b,0xc2,0x70,0x1c,0xf2,0xb9,0x43,0xc1,0xa1,0xb2,0xe0,0x68,0x9f,0x7b,0xf4,0xf5,
-0x0b,0x7b,0x5e,0xff,0xbe,0xf2,0xee,0x32,0x1e,0x11,0x1f,0xce,0xad,0xf4,0xab,0xf1,
-0x7a,0xf9,0x42,0xa0,0x62,0x61,0x69,0xb8,0x7c,0x09,0x74,0xe2,0x80,0xdf,0xbe,0x14,
-0x28,0x5f,0x7a,0x38,0x5c,0xf2,0x90,0xf0,0x5c,0xe2,0xc3,0x29,0x1e,0xe8,0xa7,0x4c,
-0x8f,0x35,0xa6,0xf3,0x3a,0x37,0x56,0x3b,0xc7,0x75,0x5e,0x85,0x86,0xbb,0x84,0xe9,
-0x84,0xe7,0xf0,0x98,0xe3,0xf8,0x19,0xb3,0x7e,0x8e,0x58,0x5e,0xbf,0x28,0xd7,0xcd,
-0xf5,0xc1,0xf1,0x9b,0xe3,0x3a,0xe0,0xb8,0xc0,0x76,0x03,0xcb,0x39,0x9e,0x2b,0x7a,
-0x32,0x92,0xae,0xcc,0x9d,0x81,0xd3,0x77,0x7e,0xfa,0xa3,0x67,0x7f,0x9a,0x9a,0x9a,
-0x64,0xb9,0xde,0x31,0xe7,0x51,0xed,0x6c,0x76,0xf6,0xd6,0x6c,0xe0,0xc3,0x3d,0x9a,
-0xa8,0x7d,0xb4,0x36,0x7e,0x6a,0x6d,0x6d,0xbc,0x06,0xbd,0x51,0xd7,0x26,0x4e,0xaf,
-0x3d,0x9a,0x38,0x83,0x3a,0x70,0xab,0x93,0x75,0x88,0xef,0xd0,0x6f,0xbe,0x12,0x64,
-0xda,0x32,0xa1,0x73,0xa8,0x1f,0xc3,0xf1,0x9d,0xea,0xe7,0x8d,0xcb,0xdf,0x4c,0x91,
-0x1e,0x0d,0xd6,0xcc,0x21,0xb7,0x6e,0x9c,0xa7,0x98,0x1c,0xf0,0x9c,0xb0,0x1c,0xf8,
-0xed,0x76,0xbc,0x76,0xa5,0x8e,0x1e,0x31,0x63,0x76,0x8a,0xcf,0x21,0xbf,0x4e,0x18,
-0x4e,0x98,0xde,0x42,0xf1,0x78,0x44,0xc5,0xf3,0xb9,0x3b,0xe7,0xe7,0x5e,0xf9,0xa7,
-0xe7,0x5f,0x49,0x4d,0xd9,0x9c,0x1a,0x8d,0xef,0xc5,0xe3,0x73,0xaa,0x97,0x9b,0x31,
-0x3a,0xe7,0xb8,0x43,0xbc,0x4d,0xc7,0xad,0x82,0xef,0x0e,0x3c,0x39,0x11,0xb3,0xb3,
-0x81,0x58,0x8f,0xc7,0x3f,0x30,0x8f,0xe7,0x7e,0x80,0x3f,0x5b,0x9d,0x6e,0x5b,0xfd,
-0xc5,0x1b,0xee,0x5f,0x64,0x6c,0x49,0xce,0x90,0xe7,0x02,0xf3,0x03,0xb2,0x62,0x9e,
-0x7c,0x8f,0xcb,0xd8,0x68,0xfb,0x7c,0xfe,0x3c,0xbb,0x21,0xbd,0x57,0xf1,0xbb,0x36,
-0xb1,0x54,0xcc,0xd8,0x4b,0xff,0x5b,0x36,0x31,0x8a,0xf9,0x56,0xa2,0xc7,0x73,0x1b,
-0xf9,0x5e,0xeb,0x43,0xbf,0x87,0xf5,0x73,0xfa,0xf3,0x94,0xd7,0x25,0xbd,0xde,0x27,
-0xe1,0xbe,0x59,0xd6,0x3c,0xba,0x36,0xa9,0x0d,0x47,0xdd,0xce,0x63,0x44,0xc1,0xed,
-0x04,0xb5,0xbf,0x5a,0xf7,0xd5,0x44,0x6d,0xef,0xcd,0x8e,0x64,0x18,0x90,0xc3,0xd9,
-0x9f,0xef,0xd8,0x0f,0x78,0xde,0x7d,0x23,0xa1,0x5b,0x60,0x79,0xbb,0xab,0x17,0x8e,
-0x21,0x2e,0xc7,0x18,0x9d,0xc5,0xe9,0xdd,0x9e,0x44,0xca,0xb3,0x77,0xf0,0x5c,0x3b,
-0xed,0x85,0xa6,0x4c,0x07,0xe3,0xc3,0x79,0xd2,0x94,0xfa,0x39,0xf8,0xa5,0xea,0x7a,
-0x32,0xfa,0x35,0x55,0x3e,0x17,0xbb,0x7b,0xc6,0x26,0x1f,0xa1,0xe7,0x6a,0xd6,0x5b,
-0x2f,0xda,0x7d,0x0e,0x70,0xae,0xbc,0x3c,0xb1,0xbc,0xe3,0xbf,0x76,0x75,0x98,0xda,
-0x70,0x26,0x1f,0x0e,0x6a,0xe8,0x9c,0x0f,0x67,0xf2,0xe0,0x54,0x3e,0x1c,0xe7,0xb7,
-0xeb,0xfd,0x6a,0xc8,0x6f,0xef,0xde,0x2f,0xb4,0xe2,0x08,0xcf,0x4d,0x3e,0x9c,0xe5,
-0x9e,0xd5,0xbe,0x87,0xf0,0x80,0xaf,0x67,0xc5,0xeb,0xdd,0x64,0x8d,0xc3,0x75,0x9e,
-0xbf,0xee,0xc3,0xa6,0xf4,0xdb,0xbb,0xac,0x9e,0xb2,0xbc,0x6f,0x2f,0x2d,0xc9,0x91,
-0xb6,0x63,0x5b,0xfc,0x8e,0x97,0xff,0x21,0xfb,0xe5,0x41,0xcf,0xe1,0x41,0xd0,0x77,
-0xc5,0x5a,0xfa,0xe0,0x31,0xac,0xa5,0xc3,0x3e,0x38,0x70,0x2c,0x08,0xfc,0x76,0xf0,
-0x57,0xc3,0x7e,0x35,0xe8,0x53,0xf3,0x49,0xfa,0x70,0xcc,0x8b,0xc5,0xe4,0xc1,0x15,
-0x86,0x42,0xde,0xa2,0x50,0xd0,0x6b,0xe2,0xf9,0x94,0xdf,0xc0,0x74,0xbf,0x11,0x9b,
-0x03,0xb6,0xfb,0xdd,0xa1,0x29,0xbf,0x11,0xa3,0xfb,0xcb,0x82,0x93,0x43,0x65,0x93,
-0xfd,0xb7,0x8a,0xfb,0xcf,0x9c,0xce,0x3e,0xb3,0xde,0x77,0xf8,0x49,0x37,0xfd,0x3e,
-0x33,0xf5,0x64,0x54,0xef,0x73,0x18,0x80,0xe7,0x8b,0x81,0x8a,0xc5,0xd9,0xd1,0x13,
-0xb3,0x73,0xa3,0x27,0xe6,0x16,0x02,0x95,0x0b,0x4b,0x81,0xe3,0x4b,0xf3,0x23,0xd5,
-0xf3,0x32,0x9e,0x63,0xae,0xfd,0x0e,0xef,0x41,0x3f,0x3d,0xa7,0xf8,0xa6,0xde,0x3d,
-0x2d,0xe9,0xb7,0xd7,0xaa,0x63,0x5c,0xc2,0x77,0xc9,0x5b,0x0d,0xf7,0x13,0x75,0x92,
-0x2f,0x8b,0x99,0x73,0xbf,0x37,0x6e,0x8f,0xe9,0x88,0xeb,0x72,0x8c,0x6e,0xc4,0xe2,
-0x88,0xed,0x88,0xdb,0x67,0xa5,0x98,0x1c,0xb4,0x5e,0xcf,0xe1,0x7e,0xee,0x4e,0xfd,
-0xdc,0x17,0x9f,0x54,0x7e,0xd1,0xdc,0xb8,0xa7,0xd9,0x58,0xe0,0x25,0xc7,0xba,0x6e,
-0x1b,0xd9,0xa0,0x7e,0x1e,0xf1,0xd5,0x46,0x00,0xb3,0x1f,0x4d,0x9c,0x7e,0x04,0xb8,
-0x8e,0x38,0xce,0x06,0xf8,0x9f,0x13,0x96,0xd7,0xa3,0x76,0x0c,0xf4,0xa1,0x73,0xbd,
-0x38,0xd2,0x86,0x23,0x7d,0x38,0xd4,0x93,0x09,0x83,0x46,0x5c,0x23,0xe3,0xc8,0x19,
-0x38,0x1e,0xe2,0x3e,0x6b,0xe7,0x59,0x7c,0xce,0xe2,0x71,0x8e,0xe5,0xa8,0xf5,0x4a,
-0xfd,0xe6,0xdc,0x93,0x45,0x70,0xe2,0x22,0x2c,0x36,0x37,0xe2,0x72,0x9e,0x73,0xa7,
-0xfc,0x7a,0x8b,0x59,0x3b,0x97,0x79,0x70,0xc6,0x78,0x10,0x6c,0x7a,0xf0,0xde,0xdb,
-0xee,0xf7,0x76,0xe4,0xa4,0xef,0x80,0xf9,0x58,0xcc,0x35,0x9a,0xb7,0x08,0xe1,0x79,
-0xd3,0xbc,0xc0,0x66,0xb9,0x8e,0x8e,0x18,0xde,0xba,0x66,0xf2,0xd8,0x19,0xb6,0xcb,
-0xe7,0x66,0x6d,0xc6,0x9c,0x1a,0xaf,0xaf,0x4c,0xb7,0xad,0xbc,0xf5,0x86,0xfb,0xad,
-0xcc,0x8c,0x94,0xcc,0x58,0xb8,0xc9,0xef,0x69,0x31,0x6f,0x48,0xf7,0xfb,0x46,0xf0,
-0x70,0x43,0x9b,0x53,0x39,0x54,0x57,0x7a,0x4e,0xe9,0xff,0xd9,0xcc,0xeb,0xfa,0xdf,
-0x58,0xef,0x35,0xd9,0xad,0x25,0xed,0xf0,0xde,0xf6,0xf7,0x62,0xcc,0xa5,0x76,0x6b,
-0x12,0xfd,0x73,0x8d,0x89,0xd9,0x9a,0x3e,0xae,0x5c,0x73,0x58,0x8f,0x8b,0x2e,0xe7,
-0x85,0x2d,0x7d,0x58,0xfa,0x88,0x57,0xe3,0x71,0xbb,0x5e,0x44,0xb9,0x37,0x5b,0x9e,
-0xe7,0xf3,0x77,0x3b,0xf2,0x2f,0xbf,0x1b,0x7f,0xb9,0xf3,0x06,0xf9,0xa4,0x76,0x7b,
-0x12,0xba,0xc9,0x5b,0x4d,0xf3,0x57,0xeb,0x00,0x7e,0x3b,0x79,0x9f,0x63,0xbd,0xdc,
-0xc3,0x06,0xab,0x9d,0x0b,0x2c,0x17,0xb5,0xf3,0x54,0x2b,0x1f,0xce,0xad,0xe5,0xdb,
-0xf9,0xf5,0x67,0xd7,0x5a,0xdc,0x17,0xd2,0xfd,0x61,0xf9,0x99,0x76,0x4f,0xc9,0xeb,
-0xcf,0x68,0xf7,0x86,0x7c,0x2f,0xd9,0xdd,0x5f,0x65,0x65,0x49,0x65,0x1d,0x5f,0xee,
-0xec,0xe8,0xef,0xdc,0xdd,0x2f,0x63,0x39,0x70,0xd9,0xf9,0xe0,0xfd,0x6a,0xb2,0xde,
-0x2b,0xf4,0x9d,0x9b,0xfc,0x76,0x5d,0xf3,0xd5,0xec,0x59,0xa3,0x71,0x80,0xf4,0x64,
-0x78,0xff,0xb9,0xfe,0x7e,0xf4,0xfb,0x2c,0xc6,0x3a,0x50,0xd6,0x81,0x90,0xeb,0x29,
-0x76,0xf7,0x4d,0xd4,0x7b,0x86,0xfb,0x2f,0x69,0x75,0x34,0x78,0x0c,0xda,0x71,0xbf,
-0xfe,0xd7,0x3d,0xbf,0x0e,0x74,0x1f,0x0d,0x80,0xdf,0x39,0xf4,0xab,0x91,0xef,0x79,
-0xc1,0x04,0xf5,0xad,0x41,0x7e,0x1d,0x62,0xf3,0xa2,0x71,0xd4,0x6e,0xf7,0x15,0x4d,
-0x70,0xdd,0x76,0xee,0x95,0xca,0xb5,0xdb,0x69,0x0f,0x58,0xee,0x0e,0xf2,0xfa,0x39,
-0xd4,0xce,0x45,0xfd,0xdc,0xc0,0x71,0x1c,0x43,0x80,0xe7,0xe5,0xc6,0xcf,0xcb,0x27,
-0xff,0xf8,0xc9,0xd1,0x3f,0xe6,0xe6,0xa6,0xe5,0xc6,0xfa,0xce,0x7f,0xd7,0x4d,0xc5,
-0x73,0x33,0xcf,0x3e,0x3b,0x5a,0x4d,0x3e,0x6b,0x06,0x96,0xf3,0xfe,0x73,0xc0,0x76,
-0xc8,0xb9,0x83,0x86,0x3b,0xe1,0xb9,0xc9,0x6b,0x17,0x5e,0xa9,0x63,0x0c,0xcb,0xf5,
-0x7c,0xbb,0x14,0x9b,0x03,0x8e,0x93,0xbf,0x1a,0x79,0xb2,0x98,0x58,0x5e,0xb7,0xc8,
-0xf7,0x7a,0xfd,0x5c,0xc4,0xe7,0xe3,0x94,0x67,0x57,0xf8,0x70,0x51,0xb0,0x1c,0xf3,
-0xeb,0x90,0x6f,0x9f,0x34,0xe3,0xf3,0xa5,0x89,0x17,0x96,0x66,0x46,0xea,0x66,0x6e,
-0x5e,0xaf,0xbe,0x79,0xe1,0x95,0xc3,0x17,0xa0,0xde,0xb0,0xd9,0x95,0xb0,0xf9,0x69,
-0x5c,0x4b,0xc8,0xb7,0x43,0xfd,0x9c,0xfa,0xcd,0xa9,0x67,0x6d,0x25,0x08,0x98,0xad,
-0x8f,0x73,0xe6,0x00,0x6e,0x3b,0xfa,0xb3,0xbc,0xf0,0x88,0x6b,0xb6,0x03,0xae,0xa3,
-0xa7,0x9a,0x31,0x00,0xc3,0x01,0xbf,0xb9,0x67,0x2a,0xef,0x55,0x23,0x1f,0x55,0xd2,
-0x82,0x53,0x87,0xca,0x6f,0xc7,0x7c,0x3b,0xe8,0xca,0x20,0x96,0xb7,0xb0,0xc7,0xcd,
-0x66,0x7c,0xce,0x6a,0xe8,0x58,0x3b,0x67,0x58,0xbe,0x1c,0x6e,0x59,0xfe,0xf8,0xf7,
-0xd5,0x1f,0x1f,0x3a,0xb8,0xfd,0x90,0x31,0x39,0xc7,0xe9,0x7c,0x6f,0xf9,0x3b,0xfa,
-0xea,0x3f,0x1f,0x7e,0x55,0xe1,0xc3,0xb1,0x98,0x9c,0xb0,0x1b,0x70,0xbb,0x4d,0xaa,
-0x95,0xb7,0xd0,0x39,0x5e,0x2b,0x9f,0x69,0x93,0xea,0xe6,0x6d,0x66,0x9e,0x7d,0x8e,
-0x63,0x39,0x9d,0x5f,0x8d,0xb4,0xad,0x12,0x9e,0x27,0x67,0x46,0xcb,0x6f,0xdb,0xe2,
-0x92,0x36,0x37,0x2a,0xf8,0x28,0x61,0x6a,0x2c,0x6c,0xe4,0x9b,0xed,0xba,0x40,0xc3,
-0xf2,0xa7,0xb2,0xe9,0xeb,0x85,0x18,0xaf,0xc3,0x82,0x1b,0x0e,0x15,0x23,0xec,0x3e,
-0x33,0xbd,0x7e,0x6f,0x7b,0x2d,0x63,0xe5,0x7f,0x9d,0x0e,0xdb,0x7c,0xaf,0xe2,0x6f,
-0x2d,0xc5,0xe6,0x96,0xbe,0x10,0xf9,0x39,0x72,0x3d,0xdc,0xa9,0xe6,0xde,0x63,0xd5,
-0x8a,0xa3,0xf6,0x17,0x4a,0xcf,0xcd,0xdd,0xe5,0xcc,0x05,0x3e,0x1c,0xe8,0xc9,0xa0,
-0xff,0x79,0x7b,0x02,0x7a,0xa6,0x72,0x3c,0x87,0xd8,0x9c,0x7a,0xd5,0x88,0x0f,0xc7,
-0xf9,0xed,0xa0,0x29,0xc3,0x31,0xbd,0xdb,0x93,0x42,0x9a,0x32,0x1e,0x93,0xdf,0x8e,
-0xbc,0x38,0x4f,0x1a,0xf6,0x9e,0x53,0xbe,0x9d,0xf1,0xe1,0x6c,0xd6,0x50,0xe2,0x33,
-0xd3,0xee,0xb9,0xa7,0x76,0xaf,0xac,0xb3,0x95,0x96,0x25,0x96,0x82,0xde,0x6b,0x7f,
-0x67,0x6e,0x3f,0x60,0x3a,0xe1,0x7a,0xde,0x40,0x7f,0x67,0x7e,0xbf,0xe8,0x57,0x63,
-0x7d,0x6a,0x26,0x9e,0x5b,0xfb,0xd5,0xa0,0x57,0xcd,0xd7,0x05,0x7a,0x70,0x7b,0x7d,
-0x5c,0x1b,0x0e,0x7b,0xd6,0x7a,0x48,0x57,0x86,0xf3,0xe1,0xa2,0xad,0xb3,0xed,0xf2,
-0x11,0x76,0x39,0x86,0xf5,0xee,0xbb,0xf5,0xfa,0x4b,0xf1,0x6f,0xf0,0x38,0xdf,0x46,
-0xb7,0xc7,0x15,0xef,0x74,0x95,0x14,0xa4,0x97,0x7c,0xf4,0xfb,0x67,0x3f,0x1a,0xeb,
-0x3f,0x36,0x36,0x3e,0x08,0xfd,0x6b,0x05,0x12,0xa6,0x73,0x0f,0x74,0xf2,0x61,0x21,
-0xaf,0x54,0x03,0xdb,0x07,0x29,0x36,0x17,0xfe,0x6a,0x7e,0xe2,0xc3,0x51,0x1f,0x7a,
-0xe9,0x84,0x59,0x3f,0x37,0xf0,0xdd,0xef,0x0e,0x42,0xbf,0x1a,0xe0,0x37,0x61,0x79,
-0x99,0xb1,0x2f,0x0f,0xc2,0x98,0xf0,0x95,0x4d,0x5c,0x7a,0xfb,0xc0,0xa5,0xe4,0xe4,
-0x84,0xef,0x1c,0x3b,0x46,0xdb,0x00,0xcf,0xbb,0xaf,0x17,0x77,0xcf,0x0d,0x83,0x97,
-0x1a,0x8f,0xcf,0xab,0x67,0xc8,0x6f,0xad,0x72,0xde,0xec,0x55,0x3b,0x39,0x0b,0x1e,
-0x2c,0xdf,0xf8,0x8b,0xbf,0xb9,0x3f,0x7c,0xfc,0xfe,0xfc,0x28,0x8b,0xd1,0x45,0xcf,
-0x5a,0x8d,0xea,0x7f,0x3e,0x66,0x62,0x3a,0xc4,0xe7,0x93,0xde,0x13,0x93,0xde,0x9b,
-0x15,0xde,0x7e,0xcf,0xf1,0xfe,0x01,0xcf,0xf1,0x01,0xd8,0xd3,0xa8,0xc0,0xc7,0x03,
-0x9e,0x0a,0x36,0x2a,0x07,0x06,0x3a,0x2a,0x70,0x0c,0x76,0x54,0x0e,0xe2,0xf0,0xb0,
-0xc1,0x1e,0x7b,0x6f,0x56,0x79,0xbd,0x1d,0xc6,0xb8,0xc9,0x46,0x07,0x7f,0x5c,0xed,
-0xf5,0xde,0x32,0xf6,0xb7,0xaa,0xbd,0xbe,0x9b,0x55,0x3e,0x78,0xec,0xbb,0x79,0x02,
-0xf7,0xdd,0xed,0x55,0xdd,0x7f,0xf8,0xa8,0xfc,0x0f,0x6f,0x5e,0x3c,0xf6,0x66,0x7d,
-0xed,0xde,0xfa,0x7d,0xcf,0x6c,0xd9,0x97,0x9a,0xba,0x39,0x75,0x13,0x7c,0xf2,0x4f,
-0x69,0x23,0xbd,0xd7,0x3a,0xd4,0x6f,0x47,0xbd,0x57,0xe6,0xc9,0x42,0x9c,0x38,0xd6,
-0x7f,0x3e,0xd5,0xf0,0x90,0xf7,0xa0,0xcb,0x75,0x74,0xcc,0xb9,0x83,0x6e,0x3b,0x68,
-0xc7,0x21,0x8e,0x53,0x9c,0x8e,0xf1,0x3a,0xc7,0xf2,0x10,0xe1,0x38,0xf4,0xb6,0x21,
-0xc7,0x1d,0xf2,0xef,0xd3,0xb2,0x7e,0x7b,0xe3,0xaa,0xe2,0x81,0x6e,0xe0,0xf6,0x4a,
-0xa4,0x79,0x05,0xb9,0x70,0xd3,0x2d,0x66,0x7c,0x3e,0xdd,0x6c,0xe2,0xba,0xe8,0x53,
-0xa3,0x3d,0x70,0xe8,0x3a,0xbf,0x3c,0xd3,0x59,0x5d,0x99,0x5b,0x6d,0x04,0x3e,0x2e,
-0x5b,0x9e,0x96,0x1c,0x9f,0xff,0xec,0x88,0xd4,0xaf,0xd6,0xf6,0x08,0xb1,0x1c,0xb8,
-0xec,0x4c,0xa7,0x5d,0xf0,0xda,0x85,0x1f,0x3a,0xf5,0xa1,0xe3,0x5e,0xd2,0x74,0xc5,
-0x3d,0xe4,0xe6,0x67,0xd9,0x7a,0x40,0xc2,0x77,0x58,0x6f,0xbc,0xf5,0x7a,0xc9,0x5b,
-0x59,0x19,0xc9,0x59,0xb1,0xea,0xd1,0x4a,0xfe,0xd2,0x61,0xad,0x4d,0x0b,0x0c,0xd7,
-0xde,0x0b,0x9d,0x74,0x28,0xb1,0x95,0x1d,0xbe,0x47,0x9b,0xaf,0xa3,0x6e,0xdf,0xc3,
-0xbc,0x6d,0x99,0x2f,0x1d,0xd6,0x79,0xd2,0xf2,0x39,0x39,0xa4,0xbc,0xad,0xc3,0xbc,
-0x66,0x0a,0xbe,0xdb,0xcc,0xb3,0x51,0xe7,0x65,0xa7,0xcd,0xff,0x95,0xd7,0x4e,0x76,
-0x79,0x00,0x39,0x5f,0xe2,0xd4,0xde,0x47,0x8c,0x75,0x87,0x5e,0x4b,0x95,0x71,0x9e,
-0xaf,0x17,0x74,0x6e,0x33,0x8c,0xbd,0x79,0xce,0xbd,0x57,0xde,0x8d,0xbb,0x82,0xf5,
-0x73,0x4f,0x42,0x0f,0xd4,0xcc,0x81,0x0f,0xc7,0x73,0xed,0x3d,0xed,0x6c,0xdf,0x61,
-0xec,0x31,0xdf,0x4e,0x03,0x62,0x75,0xc8,0xb5,0xf7,0x78,0x92,0x7b,0x7a,0x3c,0x29,
-0x3d,0xc0,0x89,0x43,0x5c,0xd7,0xfa,0xd5,0x00,0xcb,0x15,0x7f,0xb5,0xbf,0x18,0x4a,
-0x6f,0x7c,0x83,0x7c,0xbb,0xe7,0xcb,0x5d,0x1e,0x39,0xd7,0xde,0xdf,0x99,0x27,0x62,
-0x75,0xee,0xc5,0x42,0xfa,0xed,0xac,0x57,0x0d,0x73,0xec,0x7b,0xa8,0x57,0x0d,0x6a,
-0xe7,0x5d,0xcf,0x20,0x8e,0xfb,0xbb,0xc9,0x2f,0x55,0xc6,0x73,0x8a,0xd3,0x21,0x3e,
-0x07,0x3c,0x27,0xbf,0x54,0xf9,0xff,0x5b,0x72,0x44,0xd1,0xee,0x23,0xbb,0x7b,0x5a,
-0x7f,0x9e,0xbc,0x5e,0x75,0xa8,0x6b,0x74,0xf9,0x5e,0xd3,0x63,0x7d,0x85,0x2b,0x69,
-0xdc,0x23,0xc9,0x89,0xce,0xe4,0x97,0xfe,0x7e,0xfb,0x4b,0x5d,0x37,0x8e,0x74,0x8d,
-0x0d,0x14,0x8e,0x91,0xae,0x4c,0xd1,0xf8,0xd8,0x20,0xf8,0xb1,0x14,0x8e,0x03,0x07,
-0x6e,0xc2,0x5b,0x88,0xf9,0x75,0xd2,0x86,0x2b,0x66,0xb9,0x77,0x53,0xbf,0x1d,0x70,
-0x9d,0xc7,0xe9,0x22,0xd7,0x8e,0xf5,0x73,0xc6,0x85,0xf3,0xbb,0xa7,0x30,0x56,0x67,
-0xb1,0x39,0xc7,0xf3,0xc9,0xe1,0xf2,0x49,0xef,0xed,0x12,0x6f,0x6b,0xeb,0xce,0xd6,
-0x4d,0xdf,0x93,0x67,0xcb,0xb1,0xe7,0xb3,0x8e,0x0d,0x5e,0x2f,0x18,0xbc,0xef,0x77,
-0xdf,0x9f,0x0f,0x54,0xcc,0xcf,0x8c,0x54,0xcf,0x2c,0x0d,0x95,0x2d,0x7d,0xe5,0x2f,
-0xf9,0x4a,0xe0,0xb9,0x31,0x20,0xdf,0x7e,0x6f,0xa4,0xe2,0xde,0xb2,0xbf,0x70,0x19,
-0x38,0x71,0x70,0x2c,0x38,0xee,0x0a,0xb7,0xfd,0xf4,0x9c,0xac,0xf3,0x3a,0x7f,0xb7,
-0x16,0xeb,0xe7,0x1f,0x5c,0x29,0xfa,0xe0,0xd9,0x67,0xb7,0x3c,0x9b,0x91,0xe1,0xca,
-0xc8,0xdc,0xe2,0xca,0xa4,0x91,0x90,0x99,0x91,0x91,0x90,0x91,0x99,0x61,0x1c,0xe3,
-0x48,0xd0,0x86,0x7e,0x8e,0x3d,0x6f,0x8b,0xcb,0x7a,0xce,0xf6,0x77,0x5c,0x99,0x59,
-0x19,0x09,0x59,0xfc,0x5c,0x5a,0x5a,0x42,0x5a,0x52,0x52,0x7c,0x12,0xea,0xb2,0x7f,
-0x0f,0xdf,0xbe,0xec,0xbf,0xcb,0xca,0x0e,0x0d,0xd5,0x87,0xbe,0x0e,0x83,0xbf,0x5a,
-0xa3,0xf0,0x57,0x43,0x5d,0xb8,0xe0,0x0b,0xa8,0x21,0xf3,0x30,0x04,0xb1,0xbb,0x84,
-0xe5,0x32,0xa7,0x7d,0xba,0xe9,0x21,0xec,0x71,0x4c,0x13,0x37,0x0e,0xfa,0xd2,0x78,
-0x4d,0x1d,0xc7,0xf4,0x79,0xd1,0xaf,0x26,0xf7,0x9c,0x63,0x0f,0xba,0xd2,0x7b,0xde,
-0x22,0xf2,0xec,0x82,0xd7,0x3e,0xc3,0xe2,0x72,0xa1,0x0f,0x47,0x1a,0x33,0xa0,0xf1,
-0x4a,0xc7,0x4d,0x6b,0x93,0x83,0xf5,0x93,0x3f,0x7e,0xe9,0xc0,0x8f,0xd3,0x53,0x12,
-0xd2,0xf5,0xfe,0x7b,0xbb,0xf5,0x30,0xe7,0xc3,0xa1,0x36,0x1c,0xe6,0xdb,0x8d,0xf8,
-0x1b,0xb0,0x1a,0x7c,0xd4,0xc2,0x9a,0x8f,0x5a,0x84,0x7c,0x59,0xb0,0x17,0x2d,0x4c,
-0xbd,0x68,0x66,0xff,0x79,0x13,0x61,0x3e,0x60,0x7b,0xa4,0x95,0x69,0xce,0xb4,0xa1,
-0xe6,0xcc,0x6a,0xb8,0x75,0xf5,0x57,0x17,0xdd,0xbf,0xda,0x96,0x95,0xb2,0x4d,0xd6,
-0xf5,0x51,0xb8,0x42,0xec,0x3b,0x6c,0x37,0x0f,0xac,0x37,0x87,0xc8,0x38,0xaf,0xe4,
-0x3a,0x1d,0x5a,0x1c,0xcc,0x36,0x31,0x87,0xc4,0x8a,0xeb,0xa5,0xf8,0xdf,0xe6,0x47,
-0xeb,0xe6,0x01,0x62,0x6d,0x3a,0x8e,0xeb,0xe7,0xed,0xfe,0xbf,0xfc,0x33,0x65,0x0d,
-0x13,0xed,0x7f,0x4a,0x3f,0x93,0xff,0x86,0xe5,0xff,0xcb,0x73,0x76,0x34,0x8c,0x96,
-0x5e,0xab,0x25,0x1e,0xb3,0xf1,0xfd,0xb4,0x70,0x9f,0x8c,0xfb,0x90,0x6b,0xf6,0x8b,
-0x5a,0xa9,0xc4,0x83,0x42,0x2f,0xec,0x24,0xf2,0xcf,0x04,0x1e,0x14,0x8c,0x43,0xcf,
-0x38,0x0e,0x5d,0xbd,0x14,0x77,0xb5,0xef,0x46,0x7c,0xdf,0xc0,0x8d,0x84,0x81,0xfe,
-0xf6,0x84,0x7e,0xa8,0xa1,0x43,0xfd,0x9c,0x6a,0xe6,0x66,0xed,0x9c,0xeb,0xbd,0xca,
-0xfd,0x6a,0x80,0xe7,0x54,0x4b,0x4f,0xa1,0xd1,0x01,0xfb,0x54,0x63,0x9f,0x6a,0xac,
-0x01,0xd2,0x7a,0x28,0x3e,0x4f,0x63,0xf1,0x79,0x5c,0xa9,0xe5,0xfa,0xfd,0x85,0x36,
-0xfd,0x73,0x90,0xaf,0x35,0xe0,0x39,0xf9,0xab,0x41,0xef,0x79,0xae,0xe0,0xc2,0x41,
-0x6c,0x4e,0x1a,0x71,0x4c,0xe7,0xb5,0x73,0x8f,0x57,0xf6,0x63,0x41,0x0d,0x99,0x4e,
-0xd3,0x2b,0x95,0xe7,0xdc,0xa9,0x17,0x9d,0x69,0xc9,0xf4,0x18,0x98,0xde,0x43,0x9a,
-0x32,0x5c,0xef,0x35,0xe6,0x1a,0x58,0x7e,0xcc,0xd6,0xce,0x31,0xf3,0x5b,0x7c,0x7d,
-0x2d,0x7d,0x3f,0xc5,0x3a,0x5a,0xbe,0x37,0xb5,0x5c,0x93,0xdd,0x50,0x70,0xde,0x18,
-0x29,0x29,0xf1,0x29,0x6f,0xbe,0x96,0xfb,0xa6,0xbf,0xf3,0xa8,0x1f,0xf4,0xe2,0x28,
-0xf7,0x6e,0xc4,0xe8,0x5e,0x23,0x46,0xf7,0x52,0xde,0x1d,0x6b,0xe7,0x3e,0xc2,0x72,
-0xee,0xaf,0x16,0xf4,0x15,0x06,0x43,0x83,0x85,0xa1,0xf0,0x60,0x41,0x38,0x3c,0x58,
-0x18,0xc6,0x1a,0xba,0x81,0xe1,0xd0,0x8b,0x0e,0x3c,0x38,0xd8,0x87,0xbc,0x25,0x74,
-0xce,0x5f,0x3a,0x05,0xfd,0x6a,0x30,0x10,0xcb,0x19,0xae,0x43,0xdc,0xde,0xfe,0x69,
-0x41,0x7b,0x71,0xf1,0xd6,0x62,0x7d,0xfd,0xf3,0x5d,0x37,0xf8,0xce,0x94,0x15,0x66,
-0x95,0x0d,0x5c,0x2f,0x1c,0x78,0xe0,0x2d,0x7c,0x70,0x7f,0x88,0x30,0xfd,0x81,0xaf,
-0xe8,0x01,0xf0,0xe0,0xb0,0x8e,0xce,0xfa,0xd5,0x20,0xef,0xbe,0x30,0x5a,0xb5,0xb0,
-0x34,0x6c,0x60,0xfd,0x70,0xd9,0x57,0x8b,0x23,0x55,0x8b,0x73,0x77,0x6b,0x4c,0xdd,
-0xf6,0x3b,0xa6,0xde,0xab,0xc2,0x89,0x63,0x7c,0xb8,0x2b,0x97,0x0a,0xae,0xe4,0xe4,
-0x24,0xe7,0x3c,0xcd,0xd7,0xff,0xff,0x6d,0xcb,0xc9,0xde,0x9a,0x13,0xf2,0xd7,0x87,
-0xa8,0xd7,0xdc,0xd4,0x90,0x81,0xbc,0x3b,0xd4,0xce,0x81,0xf7,0x6e,0xe6,0xdf,0xcf,
-0xad,0x2c,0x87,0x24,0xae,0x7b,0xd8,0x1c,0xa8,0xf3,0x3e,0x4d,0x1c,0xb8,0x87,0xd3,
-0xcd,0xc6,0x71,0xf3,0x32,0xef,0x4b,0xa7,0xe3,0x66,0xe4,0xba,0x2f,0x47,0x9a,0x96,
-0xb1,0x2f,0x2d,0xc2,0x74,0x65,0x8c,0x58,0x5c,0x8e,0xcb,0x01,0xd3,0xe1,0xbc,0xc8,
-0xb9,0x33,0x4d,0x38,0x9e,0x7f,0x07,0x0c,0x47,0x8f,0x96,0x70,0x03,0x7a,0xb5,0x80,
-0xf6,0xdc,0x3b,0xff,0xf2,0xfc,0x3b,0x39,0x59,0x49,0x39,0xc0,0x23,0xb1,0xeb,0xe5,
-0xe6,0xb5,0x4c,0xde,0x13,0x73,0xe1,0xd5,0xc3,0x17,0xe6,0xc7,0x1a,0xe7,0x21,0x67,
-0x0e,0x75,0x71,0x5e,0x1f,0xa7,0x7e,0x72,0xe6,0xa7,0x66,0x60,0x39,0xe8,0xc0,0x73,
-0x2c,0x07,0x7f,0x36,0xf0,0x47,0xff,0x73,0xf8,0xdc,0x9f,0xc5,0x3e,0xdc,0x60,0xe0,
-0x3b,0x8c,0xf3,0xff,0x4b,0x6b,0x00,0xae,0x27,0xd3,0xfc,0x3f,0xa0,0x75,0xf7,0x9b,
-0x8b,0x45,0xbf,0xd9,0xb1,0x9d,0xf9,0xa5,0xc2,0xeb,0x61,0xf3,0xbb,0x45,0x27,0x2e,
-0x8a,0x3e,0xaf,0x8e,0x23,0x76,0xeb,0x7e,0x05,0x0b,0x9d,0xe6,0x7c,0xc1,0x3f,0x5f,
-0x39,0xc6,0x54,0xf0,0x5d,0x9e,0x73,0x1c,0xea,0x9c,0xb3,0xa1,0x2d,0xca,0x73,0x9f,
-0x18,0xf7,0x6d,0xe6,0x47,0xbb,0xf9,0x54,0x7f,0xbd,0x76,0xbf,0xab,0xaf,0x19,0xec,
-0xd6,0x41,0xfa,0xf5,0x5c,0x2f,0x37,0x2f,0x6a,0x9f,0x9b,0xd4,0x5a,0x27,0x72,0xde,
-0x24,0x9d,0x52,0xce,0x71,0xe3,0x3d,0x89,0x5c,0x43,0x08,0xb9,0x4d,0x89,0x06,0x76,
-0x27,0x32,0xcd,0x81,0x44,0xc2,0x71,0xd0,0x24,0x00,0x0c,0x87,0xfe,0x24,0x1c,0x29,
-0x8e,0xcc,0x43,0xfb,0x9c,0x87,0xae,0xfe,0x5b,0xdc,0xd5,0x9e,0x1b,0xae,0x9e,0x7e,
-0x4f,0x42,0x7f,0x9f,0xc7,0xd5,0x07,0xf1,0xb9,0xa9,0xdb,0xbe,0x99,0x74,0xe1,0x58,
-0xfd,0x9c,0x46,0x32,0xee,0xbb,0x3b,0xa8,0xff,0x1c,0xf7,0x06,0x8e,0x43,0x8c,0x4e,
-0x23,0xd5,0x88,0xf3,0x53,0x7b,0x7b,0x3b,0xd2,0x8c,0x91,0x6e,0xac,0x0d,0xd2,0x7b,
-0x40,0x1f,0xee,0xa9,0xe2,0xb9,0x33,0xc6,0xe7,0x2e,0xdd,0x93,0xf2,0xf5,0xb6,0xac,
-0x83,0xd8,0xf5,0xad,0xac,0x48,0xac,0xbc,0xf5,0xe5,0xae,0x5b,0xe0,0xc5,0xe2,0xbd,
-0x6d,0xf6,0xa9,0xa9,0xfe,0x6a,0x7b,0x4c,0xed,0x76,0x4b,0xae,0x5d,0xad,0x9b,0x9b,
-0x5e,0x2c,0xfb,0x7d,0xa6,0x3e,0x1c,0xc5,0xe7,0x32,0x1f,0xce,0xee,0x7d,0x6c,0x64,
-0x9d,0xba,0xa1,0x4b,0x23,0x5f,0x03,0xfd,0xde,0xd4,0xce,0xe3,0xef,0x68,0x31,0x3b,
-0xbf,0x46,0xcf,0xec,0x49,0x7e,0xe6,0xda,0xbf,0x1f,0xb8,0x36,0xda,0x57,0x30,0x2a,
-0xb4,0xdb,0x35,0xaf,0x54,0xac,0x9f,0x7b,0x8b,0x26,0xa7,0xbc,0x85,0x53,0x30,0x40,
-0x07,0x8e,0xb0,0xbc,0x20,0x0c,0x9c,0x38,0xac,0x9f,0xfb,0x39,0xc7,0xdd,0x1d,0xa4,
-0xb8,0xdc,0xcd,0xfa,0xcf,0xcb,0x82,0x1c,0xcb,0xe1,0x18,0x46,0x68,0xa8,0x34,0x14,
-0xf1,0xbb,0x23,0x93,0x83,0xee,0xc9,0xdf,0x5d,0x39,0xf4,0xbb,0xdc,0xdc,0x94,0x5c,
-0x27,0xbc,0xd2,0xa7,0xb0,0xc1,0x77,0x0c,0xbe,0x3b,0x65,0x05,0x59,0x65,0xc3,0xd7,
-0x8f,0x0e,0x7f,0xe3,0x2d,0xfc,0x66,0x31,0x70,0x7c,0x71,0x21,0x50,0xbe,0x00,0xfa,
-0x70,0x73,0xa3,0x55,0x73,0x33,0x77,0xa0,0x77,0xad,0x26,0xc2,0x7d,0x52,0x29,0x46,
-0xaf,0xbc,0x07,0xb1,0x39,0xfa,0xa5,0x42,0x9f,0xda,0x9d,0x1a,0x09,0xcb,0xcd,0xde,
-0x73,0x9e,0x6f,0xe7,0xdc,0xf6,0x2b,0xef,0x02,0x9e,0xa7,0xfc,0x8d,0xe3,0x79,0x56,
-0xce,0xf4,0x50,0xdd,0x34,0x68,0xc3,0x61,0xed,0xdc,0xc0,0xed,0xd5,0x60,0x1d,0xf9,
-0x9c,0x4f,0xd6,0x32,0x7e,0x7b,0xfd,0x2a,0x7a,0xaa,0x01,0x1f,0xce,0xc0,0x76,0xc1,
-0x81,0x0b,0x81,0xa7,0xda,0x79,0xd2,0x89,0x13,0xf1,0x78,0xd3,0x0a,0xf5,0xaf,0x35,
-0x2d,0xf3,0x7e,0x35,0x8e,0xdb,0x1c,0xd3,0xe9,0x71,0xcb,0x0a,0xe4,0xc9,0x71,0xcf,
-0x06,0xea,0xc8,0xa0,0xc6,0x0c,0xe3,0xbc,0x19,0x58,0xbe,0x16,0xa6,0x18,0x1c,0x8f,
-0xa7,0x9b,0x51,0xfb,0x15,0xb0,0x1c,0xbc,0x5a,0xbe,0x1e,0x3b,0xf7,0xf5,0xb5,0xf7,
-0xdc,0xd7,0xf6,0xe5,0x6d,0xd9,0x07,0xf1,0x0e,0xce,0xa1,0x2e,0x13,0xcf,0xf5,0xfe,
-0x6e,0x8e,0xa5,0x3f,0x7f,0xf5,0xf0,0xcf,0x17,0xef,0x9e,0x5f,0x5c,0x9b,0x69,0x5e,
-0x13,0xf5,0x71,0x5e,0x2f,0x17,0x9e,0x2c,0xad,0xc2,0x93,0x85,0x7b,0xb4,0xa0,0xcf,
-0x39,0x6a,0xc6,0xf0,0x18,0x9d,0xe2,0x74,0x73,0x34,0x0a,0x4c,0x07,0x3d,0x99,0x4b,
-0x6f,0x16,0x5d,0xca,0xcb,0x49,0xce,0x43,0xfd,0x98,0x24,0x53,0x3b,0x46,0x5e,0x73,
-0xc0,0xb0,0xd3,0x83,0x95,0x35,0x61,0xed,0x7a,0xd4,0x94,0x1a,0xbc,0x3e,0x57,0x48,
-0x7b,0xf8,0x8c,0xe5,0xd8,0xd6,0x6e,0xbe,0x52,0xe2,0x55,0x9b,0xd8,0xd6,0x21,0xfd,
-0x82,0xed,0xb1,0xdd,0x66,0x33,0xc7,0xaf,0xf7,0x77,0x95,0xd7,0x2b,0xc7,0x3a,0xfa,
-0xdf,0xe0,0xcf,0x8f,0x91,0xcf,0x90,0x3d,0xe0,0x79,0x3e,0x24,0xaa,0x1e,0xab,0xe4,
-0x81,0xa3,0xf3,0x91,0x6d,0xfd,0x44,0xe2,0xcd,0x7b,0x8a,0xfb,0xec,0xc8,0x78,0x2e,
-0xf8,0xeb,0x9a,0xe7,0x08,0x9e,0xd7,0x70,0x9f,0xdf,0x03,0x30,0xf6,0xe6,0x39,0xf6,
-0xbe,0xff,0x6e,0xdc,0xfb,0xa0,0xdb,0xce,0xfb,0xce,0x51,0x57,0x46,0xf2,0x63,0x31,
-0x07,0xe1,0xb9,0xae,0x27,0xd3,0xd3,0xc1,0x72,0xee,0x2c,0xef,0xde,0xd7,0x91,0xd2,
-0xd7,0xdb,0x41,0x78,0xde,0xe3,0x81,0x18,0x9d,0xf3,0xdb,0xe3,0x9f,0x18,0xcf,0xed,
-0xf0,0x2d,0xea,0xf5,0x97,0x70,0x5b,0xc6,0xef,0xa8,0xbc,0x43,0x76,0xaf,0x63,0xbf,
-0x1a,0xf3,0x3f,0xe7,0xda,0x70,0x0a,0x27,0x0e,0xeb,0xe7,0x7b,0x34,0x7e,0xfb,0x5e,
-0xa6,0x11,0xc7,0xe2,0x73,0x29,0xef,0x0e,0xfa,0x32,0xa2,0x76,0x8e,0xfc,0x76,0xc2,
-0x76,0xaa,0x9f,0xc7,0xd0,0x6f,0x7f,0x52,0xc4,0xd2,0xd6,0x93,0xf2,0xb5,0xd1,0xd7,
-0x34,0x76,0xeb,0x52,0xcb,0xb5,0xd3,0x72,0xef,0xfc,0xba,0x9d,0xa8,0xce,0x3c,0xd1,
-0xf1,0xc5,0x91,0x0e,0xf2,0x66,0x61,0xfe,0xe7,0x83,0xc0,0x85,0x2b,0xc4,0xfa,0x39,
-0xe4,0xde,0x83,0x83,0x85,0x41,0xe0,0xc1,0x05,0xbd,0x6c,0xef,0x2b,0x0e,0x92,0x4e,
-0x5c,0x09,0x69,0xc9,0xf8,0xb8,0x96,0x8c,0xea,0xb5,0x46,0x7c,0xb8,0xd2,0x20,0xc4,
-0xe9,0xc0,0x75,0x8f,0xf8,0x8a,0x23,0x73,0xde,0xa2,0xb9,0x79,0x6f,0xe1,0x7c,0xd8,
-0x5f,0x1a,0xf6,0x75,0xbb,0x7d,0x17,0x7e,0x96,0x7f,0x21,0x3d,0xdd,0x95,0xfe,0x84,
-0x57,0xc7,0xf2,0x76,0xe1,0x3d,0xc2,0xe7,0x0d,0xdf,0x87,0xaa,0xe2,0xcc,0xaa,0x91,
-0x2f,0x8e,0x8c,0x40,0xbe,0x1d,0x74,0xe1,0x16,0x02,0xc7,0x17,0x40,0x23,0x8e,0xfa,
-0xd0,0x4f,0x90,0xa6,0x0c,0xf3,0x40,0x07,0x3c,0x87,0xba,0x39,0x60,0xf9,0xfc,0xe8,
-0x89,0x79,0xc0,0x72,0x51,0x3f,0xbf,0x53,0x63,0xc9,0xb9,0x13,0xbf,0xbd,0x76,0xde,
-0xc4,0xf3,0xbf,0xed,0xf8,0x3c,0x3b,0x27,0x2b,0x1b,0xea,0xe7,0xa8,0xd5,0x1e,0x3c,
-0xbb,0xbc,0x32,0x59,0xbf,0x82,0xbd,0x6b,0x13,0xa7,0xb0,0x6f,0xed,0xf1,0xc4,0xe9,
-0xc7,0xc8,0x79,0x47,0x7c,0x07,0x9f,0xd4,0xb3,0xc8,0x77,0xe7,0xf8,0x4e,0x9e,0xa9,
-0xe7,0x56,0x49,0xff,0x95,0x34,0x60,0xcd,0x3c,0x7b,0x93,0xc0,0x77,0x8c,0xcd,0x45,
-0x9c,0xde,0x22,0x30,0x1e,0x71,0x3e,0xd2,0xb2,0x2c,0xf0,0x9c,0xe3,0x3b,0xea,0xc5,
-0x35,0x09,0xcd,0x57,0xce,0x7f,0x47,0x2f,0x16,0x03,0xcb,0x97,0x83,0x0d,0xcb,0x37,
-0x3e,0xaa,0xbc,0x51,0x7c,0x74,0x7b,0x31,0x8f,0x7b,0x64,0xad,0x35,0x39,0x46,0xd7,
-0x75,0xd6,0x00,0xcf,0x17,0xee,0x36,0x2c,0x40,0xfc,0x4d,0xa3,0xd9,0xc0,0xeb,0x66,
-0xac,0xa1,0x0b,0x6f,0xb5,0x08,0xe0,0x7c,0x0b,0xeb,0x5d,0xd3,0x38,0x72,0xb3,0x4c,
-0xd7,0x9d,0xd5,0xd1,0x85,0x87,0x2a,0xd6,0xd3,0xe9,0x18,0x7a,0xe9,0xdf,0xb9,0x58,
-0xfc,0x0e,0xf8,0xab,0x29,0x73,0xba,0x4b,0x9b,0xcf,0xa5,0x39,0x5e,0x78,0xa3,0xdb,
-0xe8,0xc2,0xe9,0xda,0x31,0x16,0x9d,0x18,0x59,0xdf,0xdd,0xa9,0xd5,0x99,0x6d,0x62,
-0x02,0xfc,0xf0,0xf5,0x98,0x56,0x8a,0x25,0xa2,0xdd,0x2f,0xb1,0xe2,0x17,0x3d,0x07,
-0xa0,0x3f,0x4f,0xd9,0x3b,0xd5,0xdf,0xb1,0x0c,0x2d,0xbe,0xde,0x08,0x6f,0xdd,0x4e,
-0x43,0xdd,0x4e,0x2b,0x5d,0x78,0x78,0x6a,0xbc,0x63,0xbd,0x57,0x58,0xe1,0x1e,0x6b,
-0x3d,0x69,0x76,0x7c,0xf5,0x58,0xfc,0xe5,0xa8,0x83,0x69,0x00,0x91,0x9e,0x8c,0x23,
-0xef,0xf2,0xbb,0x71,0xa8,0x27,0xa3,0x73,0xe1,0x68,0x98,0xc7,0x84,0xe1,0x66,0xcf,
-0x5a,0x8f,0x27,0xa9,0x87,0xea,0xe7,0x66,0x0d,0x1d,0x63,0x73,0xc0,0x72,0x23,0x3e,
-0x87,0x7c,0x7b,0xd7,0x4d,0xaa,0xa1,0xff,0xe7,0x27,0xa9,0x58,0x3f,0xd7,0x3f,0xa9,
-0x58,0xeb,0x2f,0x65,0xed,0xe8,0xd8,0xa0,0xf6,0x7d,0x94,0x5c,0x93,0x25,0xe7,0x24,
-0xfd,0x5f,0xd0,0x6f,0x07,0xbd,0x57,0xc8,0xb7,0x13,0x1f,0x2e,0xaf,0x5f,0xf4,0xab,
-0x49,0xde,0x6a,0xd4,0x77,0x9e,0x6f,0xf6,0x9d,0x4b,0xfa,0x70,0x7c,0x90,0x3e,0xdc,
-0xde,0x61,0x33,0xe7,0xce,0xfc,0xd5,0xba,0xd7,0xf7,0x57,0xdb,0xc8,0xf7,0x41,0xc1,
-0x6d,0xe9,0x3b,0xa5,0x3f,0xc9,0xb2,0x5e,0xd5,0xef,0xf1,0x18,0xb9,0x22,0x7d,0xcd,
-0xbe,0xd9,0x15,0xb7,0xf9,0xe5,0x7f,0xdc,0xf1,0x72,0xa0,0xe7,0x58,0x80,0xf2,0xee,
-0xc0,0x7d,0x2b,0x42,0x4e,0x1c,0x72,0xda,0x07,0x8b,0x26,0x89,0xe7,0xce,0xfa,0xd0,
-0xb9,0xa6,0x0c,0xf7,0x65,0xf1,0x91,0xa7,0x1a,0x61,0x7a,0xa9,0x34,0xca,0x26,0x09,
-0xcb,0xdd,0x53,0x61,0x9f,0x3b,0x0c,0x58,0x3e,0xeb,0x2d,0x9c,0x9d,0xf5,0x15,0xce,
-0xce,0xf8,0x4a,0x66,0x42,0x43,0x65,0x21,0x88,0xdb,0xff,0xf4,0x59,0xe1,0x9f,0x6a,
-0x4f,0x65,0xd7,0xc2,0xeb,0x88,0x76,0xed,0xd6,0xdb,0xe0,0x7d,0x20,0x87,0xc4,0xb8,
-0xe7,0x61,0xbe,0xae,0x29,0xcd,0xac,0x81,0x7c,0xfb,0xec,0x48,0xd5,0x2c,0x69,0xbd,
-0x56,0xce,0x71,0x4e,0xbb,0x39,0x28,0x3e,0xe7,0x7d,0x6b,0x84,0xe5,0x27,0xe7,0xb8,
-0xbf,0x9a,0xe8,0x57,0x93,0xf3,0xed,0x63,0x6a,0x1d,0x1d,0xf0,0x3c,0x3b,0x27,0x39,
-0xfb,0xdb,0xbe,0xee,0xbf,0x86,0x0d,0xf5,0x5e,0x87,0x20,0xdf,0xce,0xb4,0xda,0x81,
-0xf7,0xc6,0x39,0xee,0xa0,0x31,0xc3,0x7a,0xd5,0x38,0x96,0x83,0x37,0x2a,0xf6,0xae,
-0xc1,0x31,0xfa,0xa3,0x72,0xff,0xf3,0x73,0x82,0xff,0x46,0xdc,0x37,0xce,0x83,0x6b,
-0x94,0xf4,0x5d,0xb9,0x76,0x3b,0x1f,0x6a,0x7c,0xce,0x31,0x9d,0xe7,0xda,0x4d,0xae,
-0x3b,0xab,0xa1,0x73,0xbe,0xbb,0x71,0x3c,0xd4,0x55,0x3b,0x74,0xea,0xe4,0xee,0x53,
-0x49,0xae,0x4d,0xc2,0xaf,0x4c,0xd1,0x5a,0xd3,0xe2,0x72,0x59,0x33,0xfd,0xb5,0x57,
-0x0f,0xbf,0xb6,0x78,0xb7,0x71,0x91,0xfb,0x9a,0x13,0xe7,0xad,0xf9,0xb1,0xca,0x83,
-0x33,0xf9,0x6e,0x1c,0xc3,0x4d,0xce,0x7b,0xdb,0x63,0x59,0x33,0x8e,0x7b,0xb5,0x88,
-0x31,0xdb,0xfa,0xdf,0x50,0x37,0xe0,0xf5,0x73,0x1d,0x13,0x2c,0xfd,0x4d,0x2c,0x1e,
-0x14,0x7b,0x2d,0xaf,0x6b,0xe7,0xb7,0x66,0xa7,0xf3,0x1a,0xcd,0x6f,0xcd,0x6e,0x6e,
-0x15,0xf3,0xaa,0x16,0x37,0xe8,0x98,0x2a,0xdf,0x2b,0x72,0x9c,0xaf,0xec,0x1d,0x2a,
-0x46,0xeb,0x9b,0x3e,0x77,0x47,0x8b,0xe7,0xe4,0xd8,0x44,0x3c,0xd6,0x39,0x65,0x36,
-0xbc,0x70,0x9d,0x47,0xae,0x7b,0x81,0x21,0x9e,0x73,0x3f,0x30,0x09,0xf7,0x75,0x2d,
-0x13,0x3d,0x8e,0xd4,0xff,0x86,0x7e,0x2e,0xd6,0x3a,0x22,0xa6,0x56,0x90,0xa4,0x87,
-0x26,0x7f,0xd6,0xf9,0xb9,0x8e,0xfc,0x2b,0x97,0xe2,0xae,0xa0,0xbf,0x5a,0xbb,0xda,
-0xaf,0xa6,0xd6,0xcf,0x59,0xff,0xb9,0x81,0xe3,0x82,0xd7,0xde,0x41,0x5a,0xaf,0xa4,
-0xf9,0xca,0x3c,0xd5,0xa0,0x76,0x8e,0xf5,0x73,0xf0,0x56,0x33,0x7b,0xd0,0x3f,0xfb,
-0x04,0xf4,0xe1,0x24,0xbd,0x57,0xa7,0x89,0x49,0x96,0x1c,0x8f,0xdd,0xe7,0x23,0xdd,
-0x37,0xb1,0xb0,0xd9,0x92,0x27,0x8a,0xb1,0xd6,0xe3,0x1b,0xc7,0x73,0xae,0x23,0xc3,
-0x35,0xdb,0x85,0x36,0x9c,0x31,0x86,0xba,0xf2,0x86,0x86,0x3b,0xf3,0x86,0x87,0x3b,
-0x77,0x0f,0x0f,0x75,0xe6,0x0d,0xa1,0x4e,0x5c,0xd7,0x1e,0x3f,0x69,0xc3,0xe5,0x93,
-0xc6,0xab,0xb1,0x0f,0x74,0xe5,0x07,0x40,0x23,0x0e,0x38,0x71,0xe8,0x97,0xca,0x6a,
-0xe7,0xe4,0x7f,0x9e,0xf3,0x4e,0x2c,0x3c,0xdf,0xc8,0x16,0x6d,0xfd,0x2a,0xde,0x97,
-0xd3,0xfe,0x39,0x76,0xeb,0x23,0x4b,0x6c,0x2f,0x7d,0x16,0xf2,0xfd,0x0e,0xf7,0xcc,
-0xb6,0x2c,0xd7,0xb6,0xab,0x97,0xf7,0x5f,0xbd,0x3b,0x50,0x78,0xd7,0x9a,0x73,0x2f,
-0x1e,0x97,0xf5,0x64,0x54,0x2c,0x27,0xdd,0x57,0x8a,0xd1,0x4d,0xff,0x73,0xf4,0x5b,
-0x63,0x31,0x79,0xd8,0x57,0x12,0x9e,0xf6,0x15,0x4f,0xc3,0x08,0xfb,0xdd,0xe1,0x90,
-0xbf,0x34,0x34,0x35,0x54,0x36,0x15,0x1c,0x2e,0x0f,0x4e,0x0d,0x97,0x4f,0x4d,0x78,
-0xcb,0x27,0xae,0x5d,0x3d,0x72,0xed,0xf0,0x73,0x5b,0x0e,0x7f,0x1b,0x7e,0x1c,0x5f,
-0x0b,0x12,0x77,0xdf,0xe1,0x82,0xba,0x53,0x45,0x51,0x56,0x45,0xd7,0xf5,0x92,0xae,
-0x99,0x91,0xaa,0x99,0xd9,0x91,0xea,0x59,0xe0,0xc3,0xc9,0x5a,0xaf,0x88,0xe1,0x23,
-0x4c,0x23,0x0e,0x71,0xdd,0x78,0xcc,0xb0,0x9c,0x6a,0xe7,0x35,0xc2,0x2b,0x75,0xfe,
-0x4e,0xcd,0x3c,0xf8,0xae,0xc8,0xfd,0x6a,0x18,0x9f,0x1b,0x78,0xfe,0xfe,0xa5,0x82,
-0xf7,0x77,0xec,0x48,0xd9,0xf1,0xed,0x3e,0xed,0xbf,0x8e,0x8d,0xe2,0xf3,0xfa,0x30,
-0xe2,0x39,0xd7,0x6c,0x97,0x79,0x71,0x5c,0xef,0x95,0x71,0xdb,0x85,0x8e,0x0c,0x7a,
-0xa2,0x9f,0x5b,0x41,0x2c,0x0f,0x9d,0xa3,0xbc,0xbb,0x71,0x9e,0xf0,0x1c,0xf6,0x0d,
-0x84,0xf3,0xe8,0x8f,0x6a,0xf6,0xa6,0x11,0x07,0xae,0x59,0xec,0x75,0x4e,0x3b,0xf1,
-0xda,0x9b,0x56,0x89,0xeb,0xd6,0xb8,0x46,0x5e,0xa9,0x34,0x78,0x3f,0xfa,0xbd,0xbb,
-0x0d,0xf7,0x7e,0xf8,0xd2,0xc1,0x1f,0x1a,0x40,0x9e,0x14,0x6d,0x2e,0xb5,0x68,0x49,
-0x4a,0xb1,0x17,0xc5,0xe7,0x8d,0x0b,0x10,0x7f,0x8b,0x5c,0x7b,0xa4,0x45,0xca,0xaf,
-0xb7,0x0a,0x7c,0xa7,0x3c,0xbb,0xcc,0x69,0x6f,0x65,0x3e,0x6b,0x26,0xa6,0x73,0x0c,
-0xe7,0x7e,0xe9,0xa0,0xfd,0xba,0x1a,0x6e,0x59,0x7d,0xfb,0x8d,0x92,0xb7,0xb7,0x67,
-0x25,0x6f,0xe7,0xf5,0x7b,0x3d,0x46,0x8c,0xaa,0x01,0x17,0x0b,0x1b,0xf4,0x9f,0xd9,
-0x68,0x94,0x29,0xb1,0xba,0x94,0xb7,0x53,0xf4,0x37,0x35,0x7c,0x94,0xf1,0xdd,0xc2,
-0x13,0xd7,0xe2,0x09,0x7e,0xef,0x58,0xe6,0x32,0x29,0x16,0x51,0x4e,0x3b,0xa3,0xcc,
-0xfd,0xda,0xb9,0x58,0x7c,0xa0,0x0d,0xc5,0x7f,0x5a,0x4f,0x90,0xa2,0xf7,0xb1,0x69,
-0xe3,0xbe,0x73,0xeb,0xc6,0x4b,0x5a,0x7d,0xd3,0xce,0x53,0x54,0xcf,0x25,0x2b,0xf9,
-0x7c,0xbe,0x56,0x93,0xf4,0x67,0x60,0x2f,0xf0,0xbc,0x9d,0xfb,0xa5,0xba,0xba,0x78,
-0xae,0x9d,0x7a,0xd5,0x78,0x6c,0x4e,0x7c,0x38,0xea,0x57,0x4b,0xee,0xc4,0xdc,0xbb,
-0x81,0xe5,0x5c,0x4b,0x86,0xfa,0xce,0x65,0x4f,0x96,0x34,0xe1,0xaf,0x26,0xfa,0xd5,
-0xdc,0x4c,0x4f,0x46,0xce,0xf5,0xea,0x9f,0xb5,0x86,0xc7,0xe2,0xb3,0x8c,0x91,0xbf,
-0x89,0xb6,0x29,0xb1,0x2c,0x1f,0xc6,0xe7,0x23,0xeb,0xc4,0xc1,0x75,0xa9,0x3a,0x9e,
-0x58,0x75,0xfb,0xfa,0xce,0xdb,0xbe,0xce,0x5d,0x06,0x76,0xe7,0xfa,0xc0,0xfb,0x7c,
-0xe8,0xf6,0x6e,0xf4,0x40,0x1f,0xee,0xcc,0x1d,0x0e,0x74,0xe6,0x06,0x00,0xc7,0x03,
-0x9d,0x79,0xb8,0x27,0x5c,0x87,0x91,0x8f,0xfb,0x40,0x27,0x60,0x78,0x7e,0x00,0x30,
-0x3d,0xd0,0x49,0x7a,0xaf,0xc2,0x2f,0x55,0xc2,0x74,0xcc,0xb7,0x6f,0x04,0xcf,0xd7,
-0x79,0xa7,0xeb,0xe5,0xb2,0x2c,0x18,0x6d,0xf7,0xfd,0x71,0x8a,0x07,0xca,0xf7,0x4c,
-0xbf,0xf7,0x64,0xef,0xe3,0xc2,0x82,0xf4,0xc2,0xf6,0xcf,0x0f,0xb7,0xa3,0x0f,0xba,
-0xaf,0x78,0x7c,0xcc,0x57,0x4c,0xb9,0x77,0xf0,0x3d,0xf7,0x9a,0xfe,0xe7,0x84,0xe1,
-0xaa,0x27,0x0b,0xd4,0xce,0x45,0xff,0x39,0xd6,0xd0,0xb9,0xae,0x8c,0x3b,0xc4,0x35,
-0x65,0xa6,0xfc,0x06,0x86,0x63,0x0d,0x1d,0x6a,0xe9,0xc7,0x71,0x00,0x9e,0x4f,0x0d,
-0x1d,0x9f,0x1a,0xed,0x2b,0x1b,0xbd,0xf8,0xda,0xbe,0x8b,0x5b,0xb7,0x26,0x6e,0x7d,
-0xd2,0x7b,0x81,0xbf,0x2f,0xf8,0xcc,0x21,0xd6,0x82,0xbc,0x6a,0xe1,0xd1,0xad,0x85,
-0xa6,0x7e,0x7b,0xb5,0xa4,0xdd,0x4e,0x3a,0x71,0xf3,0x23,0x15,0xf3,0xa8,0x11,0x67,
-0xc4,0xe5,0xb3,0xa3,0x80,0xe1,0x27,0xd9,0xa8,0x91,0xf4,0x5e,0x29,0xdf,0xbe,0x38,
-0x5a,0xbd,0x08,0xbe,0xe7,0xa0,0xdb,0xae,0x6a,0xc9,0xd4,0xfe,0x1f,0x77,0xd7,0xfe,
-0xd4,0xc6,0x75,0xef,0x57,0x88,0x87,0x40,0x3c,0x85,0xed,0x34,0x60,0x03,0x0e,0xbe,
-0x0e,0x48,0x02,0x49,0xe0,0x07,0xc6,0xc6,0x60,0x63,0x8c,0x01,0xe3,0xda,0x4d,0xd2,
-0x99,0xde,0x4c,0xdb,0x99,0x4c,0x9c,0xa6,0x93,0x1f,0x32,0xbd,0xf7,0xe6,0xde,0xdb,
-0xa4,0x75,0x73,0xeb,0x4c,0xdc,0xa4,0xcd,0xa3,0x86,0x24,0x18,0x03,0x8e,0xf5,0x40,
-0x0f,0xf4,0xb4,0x24,0xc4,0x2b,0x88,0xb7,0x41,0xe2,0x69,0xd7,0x06,0xfc,0xd7,0xdc,
-0xfd,0x9e,0xb3,0x67,0xf7,0xec,0x6a,0xa5,0x90,0xb4,0xbf,0x24,0x9a,0xf9,0xce,0x39,
-0xbb,0x7a,0x20,0x2d,0xbb,0xfb,0x39,0xdf,0xd7,0xe7,0xb3,0xfc,0xc1,0x0d,0xd3,0x07,
-0x25,0x25,0xea,0x92,0xef,0xf2,0x7d,0x7f,0x68,0x0f,0xd4,0xaf,0x16,0xba,0x38,0x07,
-0x5c,0xeb,0xa8,0xc6,0x9d,0xe0,0xb9,0x68,0xec,0xde,0x02,0xdd,0x15,0x6c,0x97,0xd1,
-0xc8,0xd7,0xb8,0xcf,0x5e,0x46,0xf5,0x70,0x38,0xce,0x0e,0x98,0x8e,0x47,0xcc,0x25,
-0xd3,0xc1,0xf5,0xa1,0x73,0xbe,0x3b,0xe2,0x7d,0xed,0xe2,0x75,0xcf,0x71,0xad,0x3b,
-0xe1,0x6d,0xe7,0xfc,0x75,0x8e,0xbf,0x9d,0xc4,0xd7,0xb1,0xbe,0x9a,0x60,0x9b,0xd1,
-0xcb,0x9b,0xef,0xfd,0x47,0xfd,0x7b,0x85,0xf9,0xd9,0x85,0xe0,0xb7,0xa2,0xd8,0xb3,
-0x52,0xc0,0xb6,0xbd,0xd4,0x8a,0x42,0x7d,0xfb,0xca,0x44,0xf7,0x0a,0xe2,0x8e,0x59,
-0xe4,0xea,0xe1,0xc8,0x7c,0x89,0xe3,0x8e,0x59,0xfa,0xa9,0xa0,0x97,0x3a,0xcf,0xd5,
-0xc4,0x71,0x79,0x72,0x54,0x37,0xc7,0xc5,0xd7,0x79,0x1d,0x55,0x0e,0xd7,0x71,0xdf,
-0xda,0xd5,0x1d,0xec,0x9f,0x1f,0x7b,0x87,0xe0,0x79,0x82,0x9e,0x39,0xcd,0x4f,0x22,
-0x53,0x13,0x27,0xa7,0x87,0x97,0xcc,0xc7,0x96,0xc6,0x31,0x09,0x96,0xf1,0xf7,0x85,
-0xef,0xa0,0xab,0x2a,0x17,0x13,0x15,0x61,0x9d,0xd4,0xbf,0x96,0xc4,0xc6,0xe5,0xce,
-0x31,0x39,0x8c,0x90,0xcd,0x05,0x48,0xd7,0x14,0xc9,0xfc,0xf9,0x54,0xdf,0x41,0xce,
-0xa4,0x7f,0x5f,0xee,0xfd,0x49,0x3e,0x53,0x7a,0xec,0x93,0xf1,0xd0,0x24,0xcd,0x0f,
-0x2b,0x93,0xcc,0x65,0xe2,0xfe,0x48,0x2f,0xf5,0x5d,0xe5,0x0d,0xfb,0xfd,0x4c,0x3b,
-0x1f,0x6b,0x37,0x73,0xfe,0x39,0xcd,0x0b,0x67,0x55,0x71,0x7d,0xe8,0xd9,0x1c,0xaf,
-0x0c,0x60,0x3a,0xe1,0x94,0x51,0x63,0x4e,0x19,0x4b,0xae,0x8c,0xc6,0x9a,0x8c,0xbe,
-0x1a,0x23,0x8e,0x03,0xd3,0x63,0xd2,0xc7,0xb7,0x61,0x1c,0x1d,0xeb,0xa1,0x8e,0x21,
-0xf2,0x2f,0x95,0x14,0x87,0xb9,0x12,0xc7,0xd5,0x48,0xbe,0x09,0x6a,0x5f,0x5a,0xce,
-0xa8,0x5a,0x1c,0x43,0x25,0x0e,0xc0,0x6f,0xc0,0xf3,0x07,0x8e,0x43,0x0f,0x1e,0xd8,
-0x01,0xd7,0x0f,0x05,0x83,0x8e,0x83,0xac,0x95,0x05,0xc3,0xf6,0x32,0xe4,0x97,0x87,
-0x9d,0x87,0x04,0x1c,0x77,0x96,0x8d,0x02,0x96,0x47,0x1c,0xe5,0x11,0xec,0xa3,0x1f,
-0x46,0x16,0x72,0xbd,0xc0,0xfa,0xef,0x95,0xd8,0x3f,0x17,0xf1,0xc3,0x3d,0xbf,0x27,
-0xfd,0xf3,0x3d,0x1f,0x13,0xea,0xb8,0xf0,0x18,0xbe,0xd7,0xb5,0x80,0x82,0x7f,0x53,
-0xd2,0xb8,0x95,0xf4,0xfa,0x51,0x65,0x29,0x55,0xd7,0xba,0x0f,0x5c,0xf3,0x0d,0x1b,
-0x7c,0x90,0x47,0x47,0x78,0xce,0xf5,0xaa,0x4d,0x06,0x8e,0x4d,0x92,0x58,0xfb,0x4c,
-0xa0,0x6e,0x06,0xea,0xdb,0xe7,0xfd,0x86,0x79,0x9a,0x1b,0x8e,0xae,0x87,0x23,0x35,
-0x71,0x84,0x1b,0x2e,0x1a,0x6c,0x88,0x92,0x7e,0x35,0xf0,0xcb,0x61,0x9c,0x09,0x61,
-0x2c,0x9f,0x09,0x63,0x1b,0xb9,0x5f,0x3f,0xd2,0x79,0xa9,0xa4,0x33,0x4b,0xb5,0xf7,
-0xb8,0x3b,0x7d,0x3e,0x90,0xdc,0x39,0xc4,0x4b,0xf5,0xba,0x62,0x3d,0xe8,0xab,0x21,
-0xbf,0x3c,0x42,0xb8,0xe1,0x9a,0x11,0xa6,0x03,0x77,0xfb,0x46,0xe8,0xc4,0xc6,0xa3,
-0x60,0xdd,0x23,0xe0,0x7a,0x45,0x3d,0xe7,0x63,0xcd,0x02,0xa6,0x4f,0x70,0x9c,0x32,
-0x1c,0xae,0xaf,0x8c,0x9f,0x5d,0x01,0x3c,0x5f,0x19,0x67,0x7d,0xf4,0x49,0x8c,0xe7,
-0x0f,0x27,0x5a,0xd1,0x78,0xeb,0xcf,0x75,0xb7,0x4a,0x0f,0xe6,0x96,0xee,0xf5,0xfb,
-0xfe,0x10,0x1f,0xc8,0x3f,0x47,0x7a,0xa9,0x9d,0x5b,0xa8,0xcf,0x7c,0xa6,0xf3,0x11,
-0xaf,0x99,0x8a,0xfc,0xf5,0x6e,0xac,0xb1,0x06,0xba,0x6b,0x68,0x24,0xb8,0x4e,0xec,
-0x0a,0xd7,0xaf,0x46,0x30,0xbd,0xfb,0x1f,0x84,0xe7,0x15,0xeb,0xb0,0x74,0xb0,0xf8,
-0x0d,0xda,0xe8,0x1d,0xdb,0x80,0xed,0x30,0x82,0x4e,0xfa,0xf6,0x2c,0x58,0x27,0xd2,
-0x39,0xc7,0x3c,0xee,0xc0,0x19,0xd7,0xcd,0xf5,0x9a,0x0b,0xfc,0xae,0x82,0x1e,0xcb,
-0x95,0x27,0xf0,0x77,0x3e,0xbf,0x75,0xe6,0xf3,0x8a,0xf2,0xc2,0x8a,0x04,0x7c,0x4c,
-0xa6,0x27,0xce,0xe1,0x22,0x7d,0x8d,0x60,0xbd,0x54,0x8e,0xef,0x75,0x09,0x73,0xb8,
-0x0b,0x5c,0xae,0x94,0x16,0x0b,0xea,0x2b,0xbf,0x86,0x72,0xeb,0xa8,0x77,0x8d,0xaf,
-0x81,0xbb,0xfc,0x8c,0xd6,0x46,0x45,0xda,0x6a,0x0b,0x3f,0x7d,0x46,0xf4,0xd6,0xc0,
-0x4f,0x7f,0x3a,0x87,0xf5,0xcf,0xf7,0x17,0xab,0xf7,0x8b,0x62,0xe3,0xca,0x44,0xbf,
-0xfc,0xdb,0xb8,0xda,0x45,0x6b,0x73,0xca,0xb7,0x4e,0x8a,0x8f,0xa9,0x30,0x90,0x91,
-0xd9,0x97,0x0a,0x07,0xf7,0xb2,0x2f,0x09,0x66,0xca,0xfa,0x1d,0x8c,0xf8,0x5e,0xcf,
-0x30,0x62,0x3f,0x46,0xb4,0x5f,0x91,0xfa,0x5e,0x2a,0x8a,0x65,0x2a,0x84,0xd7,0x4b,
-0x73,0x96,0x72,0x31,0x06,0x7a,0xed,0x20,0x87,0xdb,0xd2,0xb9,0x1c,0x8e,0x8b,0xfe,
-0x47,0x34,0x4f,0x98,0x22,0xf1,0x7f,0x26,0x9b,0xcf,0x97,0xf0,0xcc,0x09,0xf9,0xf3,
-0x0c,0xac,0xc7,0x62,0xce,0x70,0x41,0xcc,0x1d,0x63,0x39,0xd6,0x64,0xc1,0x7a,0x2c,
-0x59,0x23,0x34,0x9e,0x43,0x0e,0x9d,0xd4,0xb8,0x13,0xdd,0x54,0xc0,0x73,0x81,0xef,
-0x55,0xd0,0x58,0xa3,0xf5,0xd5,0xbe,0xeb,0xbd,0x42,0xe4,0xa7,0x4b,0x8e,0x3b,0xcd,
-0x85,0xca,0xff,0x56,0x82,0xdd,0x14,0x1f,0x1e,0xcf,0x75,0x9a,0x2e,0xd1,0x22,0xe2,
-0x7a,0x51,0x9a,0x1a,0x55,0x4d,0x7c,0x7d,0x3b,0xb2,0x43,0x01,0x84,0xe9,0x8e,0xb2,
-0x07,0x41,0xc7,0x21,0x84,0xe7,0x21,0xc7,0xa1,0x50,0xc8,0x5e,0x16,0x0a,0x39,0x0f,
-0xe1,0xb8,0x3b,0xe0,0x37,0xe0,0x3a,0x3b,0x82,0x26,0x4b,0xd8,0x81,0xf5,0x58,0xc2,
-0x2e,0x9c,0x3f,0x17,0xf5,0xa0,0x8f,0x1c,0xe1,0xfd,0xf3,0x84,0xfa,0xf6,0x14,0xbf,
-0xf7,0x5f,0xf1,0xba,0x84,0xe3,0x26,0x77,0x4d,0x52,0xe7,0x3e,0xbd,0x46,0x96,0x9b,
-0xef,0xdf,0x97,0xb5,0xff,0xed,0xb7,0x2a,0xde,0x8e,0x78,0x4c,0x91,0xc9,0x40,0x3d,
-0x8f,0xe9,0x90,0x3f,0x8f,0xfa,0xeb,0xa2,0x33,0x7e,0xd3,0xcc,0x9c,0xdf,0x30,0x37,
-0xef,0x37,0xce,0x43,0x7d,0x3b,0xf0,0xbe,0xe2,0x58,0xfb,0x31,0x14,0x63,0x47,0x75,
-0xed,0x7c,0x1e,0xfd,0xe4,0x34,0xd2,0x4d,0x0d,0xc1,0xd8,0xc0,0x1b,0x8f,0xeb,0xc8,
-0x3f,0x3f,0xc5,0x63,0x3a,0x6c,0x0f,0xf6,0x1a,0x06,0xab,0x5e,0x2c,0xa8,0x82,0xf3,
-0x3b,0xe5,0x6f,0x96,0xdc,0x1f,0xe0,0xba,0x20,0xe7,0x05,0xbc,0x57,0xa7,0x2b,0xe6,
-0xf5,0xd5,0x30,0x9f,0x4c,0x33,0x6f,0x50,0xef,0xfe,0x34,0x5c,0xff,0x74,0x3b,0x54,
-0xb7,0xfd,0x38,0x58,0xf7,0x78,0x23,0x74,0x6c,0x03,0xf1,0xc3,0x8d,0x9d,0xe5,0x73,
-0xe7,0xa2,0xbc,0x39,0x3b,0x8f,0x8d,0x9d,0x8d,0x01,0xae,0x8b,0xf8,0xdb,0xd9,0x39,
-0xc6,0x73,0xf5,0x8f,0x1c,0xcf,0x8b,0x11,0x9e,0xe3,0x7a,0xb8,0x8b,0x8f,0x41,0x83,
-0x05,0xf2,0xe7,0xc0,0x17,0x47,0x70,0x1d,0x70,0x9b,0x60,0x3a,0xb2,0x79,0x76,0x7b,
-0x9e,0xf5,0xd9,0xd9,0x11,0xf5,0xa6,0x41,0x6d,0x3b,0x8a,0xb5,0x5f,0xc2,0x35,0xef,
-0x54,0x4d,0x1c,0xc2,0xf0,0x68,0xfb,0xf6,0x6e,0xf4,0xe2,0xee,0x6e,0xb4,0x7d,0x77,
-0x7b,0xa6,0x7d,0x7b,0x27,0xda,0xbe,0xb3,0x33,0x73,0x69,0x87,0xe0,0x3a,0xcc,0xd1,
-0x36,0xc2,0xf7,0xae,0x6d,0xe0,0x82,0x25,0x9a,0x2c,0x02,0x67,0xcc,0x95,0x7f,0x0c,
-0x0f,0x9d,0x1f,0x36,0x19,0x7f,0x62,0xca,0x50,0x2a,0x32,0xa4,0x7e,0xeb,0x5e,0xe2,
-0xd4,0xe4,0xfe,0x7c,0xfd,0xba,0xf6,0xfa,0xca,0x24,0xc4,0xdb,0x01,0xcb,0xb1,0xe6,
-0x2a,0xe1,0x7e,0x45,0xd8,0xbe,0x28,0xc6,0x74,0xa2,0xb1,0x46,0xb4,0x51,0x71,0x0d,
-0xfc,0x95,0x1d,0xac,0xa7,0xd6,0x8d,0xeb,0xdd,0xd9,0x11,0x74,0x55,0xe9,0x7e,0x35,
-0xac,0xaf,0x96,0x53,0x02,0x75,0x6f,0xa4,0xd6,0x2d,0xa1,0x57,0x4d,0x99,0x44,0xdf,
-0x34,0x99,0x6f,0x2e,0xe3,0xa3,0x4b,0xb1,0x29,0x25,0xd6,0x4a,0x30,0x94,0xcc,0xd1,
-0x48,0xfc,0x2a,0xca,0xbf,0x22,0xe7,0x49,0x82,0x7f,0x4b,0xbd,0x97,0xc6,0x51,0xe9,
-0xfd,0x88,0xff,0x7c,0xfa,0x8e,0xb7,0xe7,0xbb,0x9f,0xe8,0x2d,0xa2,0x75,0x82,0xd4,
-0x07,0x4c,0xba,0x8e,0x91,0xf8,0x39,0xc9,0x62,0x10,0x22,0x4c,0xa7,0x8f,0x2f,0x43,
-0xbd,0x97,0x61,0x64,0x63,0x18,0xc9,0xb0,0x3b,0x55,0x0e,0x48,0x54,0x4b,0x4f,0xe2,
-0xed,0x65,0x38,0xde,0xee,0xb8,0x9f,0xe9,0x00,0x1c,0x07,0x4e,0x19,0xc2,0x27,0x03,
-0x5c,0x32,0x84,0xc7,0x7d,0xc4,0xaa,0x1a,0xa1,0xeb,0xe1,0xa0,0x16,0x0e,0x8f,0x39,
-0x23,0xa8,0xe7,0x9c,0xd3,0x64,0x21,0xbe,0x39,0xae,0x6b,0xcf,0x73,0x25,0xd5,0x57,
-0xdb,0xe3,0xf1,0x27,0xff,0x57,0x72,0x1c,0xc8,0x35,0x95,0x90,0x5b,0x90,0x70,0xdf,
-0x92,0x1a,0x11,0xd9,0xba,0x43,0x4a,0x37,0x10,0x8e,0x41,0x53,0x63,0x36,0xc2,0x73,
-0xf0,0xc9,0x91,0x21,0x2c,0x17,0xf0,0x1c,0x8f,0x65,0xdc,0x88,0xf5,0xd5,0x1e,0x38,
-0x2a,0x38,0xad,0xb5,0x0a,0x2e,0x8f,0x7e,0x18,0xe9,0xac,0x61,0xcd,0xd4,0xc3,0x61,
-0xac,0xc5,0xc2,0xf1,0xb7,0x8f,0x50,0xfd,0x6a,0x1a,0x65,0x4a,0x3c,0x97,0x3d,0x06,
-0xdf,0xf3,0x3c,0x16,0x5d,0x63,0x8c,0xe4,0xfa,0x93,0x59,0xb7,0xca,0xad,0x4d,0xa5,
-0x0f,0x38,0xf6,0x5a,0x6d,0xae,0xb6,0xe7,0xd3,0xea,0x1e,0xe0,0x96,0xc1,0x1c,0xaf,
-0x26,0xbe,0x57,0x0d,0x8c,0xf0,0xbd,0xa2,0xbc,0x79,0xf0,0x38,0x57,0xe3,0x8e,0xf1,
-0x9c,0xae,0x83,0x43,0xba,0x2c,0xc1,0xfa,0xb9,0xb9,0xe0,0x31,0x3e,0x67,0x8e,0xf0,
-0x1c,0xf2,0xe6,0x2c,0x86,0xe3,0xfc,0xb9,0xe0,0x9f,0xcf,0x84,0x1b,0xd9,0xcf,0x3c,
-0x35,0x7d,0xe3,0x8f,0x55,0x37,0xf2,0xf3,0x33,0x52,0xd7,0xbb,0x2b,0xc4,0xbf,0x9f,
-0x5c,0x0b,0xe4,0xfa,0xd2,0xe9,0x34,0x3a,0xa4,0x7f,0xce,0x63,0x39,0x57,0xd3,0x3e,
-0x7e,0x76,0x71,0x35,0x7c,0x62,0x15,0x61,0x79,0xa8,0xee,0xf1,0x93,0xa0,0xe9,0x09,
-0xcc,0x37,0x43,0xc7,0x36,0xd7,0x22,0x0d,0x6b,0xcb,0x63,0xcd,0xcb,0x09,0x78,0x8e,
-0x7c,0xf4,0xe6,0x15,0xb0,0xe5,0xc9,0x73,0x28,0xd6,0x4e,0xfa,0xd6,0xfe,0x72,0xd3,
-0xf4,0x97,0x1f,0x3b,0x9e,0x43,0xbc,0x1d,0xf7,0xab,0xb1,0xb8,0xcd,0x71,0xbe,0xd2,
-0x7c,0xaf,0x58,0x27,0xb5,0x13,0xf7,0x98,0x13,0x9f,0x7c,0x1e,0xfb,0xe5,0xbc,0x7f,
-0x3e,0x8f,0xb9,0x64,0x04,0x4e,0x57,0x81,0x17,0x0e,0xf2,0xe7,0x80,0xd9,0xbb,0xd3,
-0x6d,0xbb,0xbb,0xd3,0x17,0x76,0x77,0xa2,0x17,0x59,0xec,0xe6,0xf0,0x1c,0xf9,0xe8,
-0x1d,0xdb,0xb0,0xbd,0x3b,0xc3,0xe2,0xfd,0xcc,0xa5,0x5d,0xf4,0xdc,0x6c,0x07,0x8f,
-0xed,0x84,0x33,0x66,0x26,0xd8,0x3e,0x73,0xf9,0xd2,0xe1,0xcb,0xea,0xec,0x74,0x35,
-0xf2,0x71,0xa8,0x3a,0xee,0x64,0x7e,0x68,0xb2,0x7c,0x2b,0xf0,0xbd,0xae,0x4c,0x5e,
-0x59,0x21,0xbe,0x38,0x70,0xbe,0xf2,0x7a,0x2a,0x8b,0x3f,0x13,0xe9,0xa3,0xf2,0x3e,
-0xba,0x48,0x43,0x0d,0x6f,0x13,0xfd,0x35,0x21,0xd6,0x4e,0x72,0xed,0x57,0x90,0x5e,
-0xea,0xef,0xdf,0xae,0xff,0x3d,0xe0,0x39,0xd1,0x51,0x42,0xbd,0x74,0x59,0x42,0x4d,
-0xbb,0x14,0xe3,0x13,0x7c,0x77,0x49,0xcc,0x3d,0x95,0x2f,0xcd,0xeb,0x9f,0x31,0x62,
-0x2c,0x4a,0xc0,0x74,0x29,0xee,0xc9,0xdd,0x2d,0x28,0xbf,0x9a,0x61,0x12,0xef,0x33,
-0xd2,0xfb,0x4f,0x02,0xbe,0x27,0xbb,0x03,0xc9,0xed,0x55,0x08,0xa3,0xf4,0xbd,0x72,
-0xeb,0x90,0x84,0xb8,0x24,0xf5,0x9b,0x92,0xfe,0xee,0x54,0xf3,0x64,0xc7,0x85,0xc6,
-0x78,0x46,0x26,0x6f,0x4e,0xe7,0x35,0x65,0xea,0x19,0x52,0x71,0x77,0xcb,0x71,0xb7,
-0x83,0x55,0x1c,0x62,0x2a,0xde,0x7f,0x37,0xfd,0x7d,0xe0,0x6f,0x47,0x7e,0x39,0xd7,
-0xb3,0xc6,0xe3,0xb8,0x19,0xfb,0xe6,0x88,0x2f,0x8e,0xc5,0x72,0xac,0x95,0x0a,0xfa,
-0x6a,0x2a,0x8f,0xd7,0x9a,0xed,0xf5,0x5a,0xc0,0x72,0xbc,0x1e,0x8b,0xda,0x03,0xe6,
-0xb6,0xaa,0xdd,0x1e,0x6b,0x2e,0x9e,0x5b,0xf2,0xdc,0x82,0x7f,0x9e,0x18,0x6f,0x27,
-0xeb,0x23,0xfa,0xb8,0xa7,0xfa,0x9d,0xfc,0x79,0xaa,0xdc,0x5b,0x8c,0x89,0x8e,0x4b,
-0xd0,0xdc,0x78,0xd2,0x7e,0x40,0xf0,0xcf,0xf9,0xfc,0xb9,0x1d,0xe7,0xcf,0x21,0xee,
-0x0e,0xbd,0xe8,0x0f,0x9c,0x18,0xdb,0x01,0xcf,0x01,0xc7,0x51,0x8d,0xbb,0xbd,0x1c,
-0xe1,0x3a,0xaa,0x6d,0xe7,0xf0,0x1c,0x1b,0xd6,0x41,0x07,0x8e,0x38,0x9a,0x53,0x86,
-0x70,0xbe,0x02,0x7f,0xbb,0x46,0xf3,0xaf,0xf1,0xcf,0x93,0xbe,0x97,0x3a,0xb7,0x45,
-0xe7,0xb3,0xcc,0x35,0xf2,0x5d,0xff,0x16,0x39,0x17,0x55,0x99,0x0a,0xd5,0xc5,0x73,
-0x9a,0x8b,0x8e,0x01,0xad,0x03,0x6a,0xdc,0xa1,0x57,0x8d,0xd4,0xb9,0xd3,0xba,0x2c,
-0x38,0x8f,0x8e,0xf1,0x1c,0xf8,0x5e,0x71,0x9f,0xda,0xf1,0x69,0xe0,0x88,0x5b,0x08,
-0x98,0x16,0x96,0x7c,0xb5,0x4b,0x2b,0xfe,0xda,0x95,0x65,0xbf,0x61,0xf9,0x61,0xc0,
-0xf8,0x10,0xea,0xe2,0x84,0xfc,0x39,0xc9,0xa1,0x63,0x6c,0x27,0x36,0x1b,0x3e,0x35,
-0x3b,0x15,0x68,0x98,0x7a,0xf5,0xdf,0x0f,0xbf,0xca,0x9e,0xf8,0xca,0xe4,0x07,0x42,
-0xb8,0x37,0xf0,0xfe,0x0a,0x77,0x9d,0xc2,0x7e,0xf0,0xcf,0x41,0x2f,0x75,0x3e,0x72,
-0x76,0x9e,0xf0,0xbd,0x02,0xae,0x03,0x7f,0x3b,0xf0,0xc4,0x6d,0x05,0xeb,0xb6,0xd6,
-0x43,0xc7,0xd7,0xc1,0x3f,0x7f,0x1a,0x34,0x3e,0x5d,0x0f,0x9f,0x58,0xdf,0x0a,0x1e,
-0xdb,0x02,0x5d,0x16,0xb1,0x06,0x3a,0x8e,0xb9,0x2f,0x8f,0xb3,0x38,0x3e,0xde,0xb2,
-0x0c,0x39,0xf4,0xe5,0x89,0x96,0xe5,0xd8,0x38,0xf8,0xeb,0xe7,0x56,0x6e,0xfd,0x1f,
-0xeb,0x9f,0x97,0xfe,0xc8,0xe3,0xed,0xcf,0x71,0xf5,0x70,0xa8,0xfe,0xad,0x6b,0x4b,
-0x18,0xbb,0x50,0xfc,0x1d,0xe1,0xf9,0x4c,0xd7,0x63,0x8c,0xf5,0x5d,0x8f,0x51,0x1d,
-0x1c,0xd1,0x55,0xe3,0xfa,0xcc,0x31,0x47,0xdc,0x15,0x84,0xe9,0x48,0x8f,0x85,0xd3,
-0x50,0x85,0x5c,0x3a,0xc4,0xdb,0x91,0x7f,0xce,0x62,0x39,0xc6,0xf3,0x0b,0x3b,0xe0,
-0xab,0x63,0x4c,0x6f,0x67,0x71,0xbb,0x7d,0x9b,0xc4,0xe0,0x77,0x66,0x59,0x3f,0x7d,
-0x16,0xfb,0xed,0x80,0xe9,0xc0,0x17,0x03,0xf1,0xf8,0xe5,0x50,0xdb,0xf2,0x1b,0xaf,
-0x56,0xbd,0x71,0x40,0x93,0x75,0x80,0xf6,0x75,0xc9,0x9a,0x5f,0x2e,0x77,0x9e,0xf4,
-0xbe,0xad,0xe0,0xf4,0x58,0x26,0x2e,0x2f,0x63,0x7d,0x54,0xc2,0x27,0x43,0xdb,0x55,
-0x5e,0x97,0x85,0x68,0xb4,0x88,0xb8,0xdb,0x39,0x43,0x78,0xfe,0x10,0xd7,0xc5,0x91,
-0x7a,0x38,0xb4,0x9f,0xfd,0xbc,0x27,0xf3,0x57,0x9f,0x80,0x5e,0x6a,0x71,0x51,0x4e,
-0xb1,0x28,0x5f,0x48,0xfa,0xd1,0x48,0x2f,0xb3,0x44,0xf7,0x3c,0xa1,0x3f,0x8d,0xce,
-0x21,0x28,0xc4,0x3d,0x69,0x09,0x18,0x2f,0xbd,0x5f,0xd0,0xfe,0x2b,0xe5,0x7b,0xcb,
-0x1e,0x1b,0x99,0x63,0x25,0x7a,0x3d,0xb5,0x4f,0xba,0xde,0x46,0x27,0x92,0x0c,0x2e,
-0xcb,0xad,0x07,0xe4,0x1e,0xa9,0xbe,0x07,0xff,0x3c,0x23,0xf9,0x0d,0x92,0xdf,0x28,
-0xbd,0x67,0xd2,0xdf,0x89,0xff,0x2c,0x85,0xf8,0xb3,0xe8,0xbf,0x25,0xe7,0xab,0xa3,
-0x31,0x19,0xe7,0x3a,0xc1,0x6e,0x45,0x62,0x0c,0x9d,0xd7,0x6c,0x49,0x93,0xe9,0x49,
-0x48,0x51,0x0f,0x57,0x51,0xa6,0xa8,0x20,0x7c,0xaf,0x90,0x3f,0x27,0x9a,0xa9,0x04,
-0xcb,0xdd,0x16,0xd0,0x4a,0xc5,0x7a,0xa9,0x1e,0x33,0x87,0xe3,0x08,0xc3,0x55,0x5e,
-0x9f,0x25,0xdb,0xe7,0xb3,0xe4,0xf8,0xfc,0xe6,0x1c,0xbf,0xdf,0xa2,0xf6,0xfb,0x2c,
-0x6a,0x1f,0x8c,0x01,0x8b,0x3a,0xe0,0xb3,0xe4,0xfa,0xa0,0xff,0x1c,0xb4,0xd5,0x9c,
-0xd6,0x02,0x67,0x5f,0x2f,0xe8,0xb1,0xe0,0xfa,0xf6,0x84,0xdf,0x9b,0xa4,0x56,0x43,
-0x0e,0xdb,0x65,0xf9,0x6c,0x15,0x89,0xb1,0x32,0x69,0x5d,0x20,0xfd,0xfb,0x69,0xfe,
-0x3c,0x58,0xef,0x9e,0x3f,0xa3,0x3a,0xef,0x1a,0x7a,0xde,0x15,0x76,0x94,0x84,0x47,
-0xed,0x25,0xa3,0x11,0x7b,0x49,0x24,0x6c,0x2f,0x0d,0xe3,0x18,0xfb,0xc1,0x10,0xd4,
-0xc4,0x41,0x8c,0x1d,0xeb,0xa0,0x97,0x23,0xc3,0xfd,0x6a,0xe5,0xbc,0x5e,0x2a,0xea,
-0x39,0xe7,0x38,0x5f,0x31,0xbf,0x4c,0x25,0xc5,0x2d,0x43,0xea,0xdb,0xbf,0x05,0xcf,
-0xbf,0x0f,0x92,0x4b,0xf0,0x5b,0x7a,0x8e,0xef,0xf9,0x73,0x53,0xbc,0x06,0x61,0x22,
-0x17,0x13,0x21,0x3a,0x7e,0x07,0x34,0x19,0x07,0xae,0xff,0xba,0xf4,0x7a,0xc0,0x66,
-0x08,0xf0,0x1c,0xee,0xa8,0x2e,0x4e,0xa8,0x6f,0x07,0x1c,0x47,0xb9,0xf4,0x40,0x1d,
-0xc7,0x05,0x77,0x8c,0x9d,0xd7,0xcf,0x22,0x2c,0x0f,0x18,0x96,0x1e,0xfa,0x0d,0x0f,
-0xc1,0x00,0xd3,0x63,0xfe,0xda,0xd8,0x62,0xa0,0x6e,0x11,0x72,0xe6,0xd8,0x3f,0x87,
-0x11,0xc7,0xdb,0xe7,0x42,0x0d,0x73,0xf3,0xa1,0x93,0xf3,0x80,0xe5,0xc4,0x4f,0x0f,
-0x3a,0x8f,0x07,0x4d,0xc6,0x62,0x93,0x02,0xce,0xa4,0x54,0xdf,0x9b,0x11,0xce,0x11,
-0x7a,0xbf,0xb6,0xba,0x58,0x6b,0x1f,0x3c,0x69,0xa7,0xf5,0xd5,0x08,0x9e,0xc7,0x47,
-0x1b,0xe2,0xeb,0xa1,0x13,0xeb,0x30,0x6e,0x84,0x8e,0x6f,0x6c,0x06,0x8f,0x6d,0x02,
-0x8e,0x03,0x87,0x3b,0xc2,0x73,0xa2,0xc9,0xc2,0x6b,0xa6,0x62,0x3e,0x19,0xc0,0x74,
-0xa8,0x73,0x07,0x5b,0x1d,0x3b,0xbb,0x1a,0x1f,0x6f,0x8e,0x7f,0x74,0xd3,0xf4,0x11,
-0xf0,0xe1,0xec,0xe1,0x3f,0xf0,0x83,0x7d,0x20,0x3c,0x87,0xfc,0xb9,0xa4,0xae,0x9d,
-0xd4,0xc2,0x91,0xbc,0x39,0xaa,0x7b,0x63,0xfd,0x74,0xdc,0x6f,0x7e,0xe9,0x09,0xa9,
-0x73,0x07,0xcc,0x26,0xda,0xe7,0x24,0xc6,0x4e,0x6a,0xdd,0x00,0xcb,0x91,0x3f,0x3e,
-0x7d,0x61,0xe7,0xd9,0x37,0xad,0xcf,0x9e,0x4d,0x9f,0x67,0xad,0xf5,0xd9,0x6e,0x94,
-0xc5,0xf6,0x68,0x1b,0xe7,0x8b,0x03,0x7e,0x77,0x60,0x3f,0x7d,0x0e,0xe3,0x37,0x6d,
-0xab,0xe3,0xed,0xab,0xef,0xff,0x97,0xe9,0xfd,0xca,0xb2,0xdc,0x4a,0x9e,0x63,0x8b,
-0xe3,0x8e,0x11,0xc5,0xb1,0xa1,0x7e,0x9c,0xf6,0x6f,0x53,0x60,0x1e,0xe4,0xcf,0x57,
-0x26,0xbb,0x57,0x88,0x6f,0x8e,0x35,0x53,0x7f,0xf6,0x94,0xd6,0x42,0x25,0xbe,0xba,
-0x78,0x1f,0xa7,0x87,0xce,0xfb,0xe5,0xd7,0x76,0x80,0xdf,0x15,0xfc,0x71,0x9c,0x43,
-0xbf,0xf2,0x8c,0xd4,0xc8,0x81,0x7f,0x4e,0xf2,0xe7,0xa2,0x98,0xba,0xa4,0xe6,0x3c,
-0x59,0x0d,0x7e,0x32,0x93,0xcb,0xbf,0x93,0xf5,0x6e,0x42,0x1c,0x59,0xea,0x6f,0xd2,
-0xf8,0x28,0x8d,0xbd,0x13,0xff,0x4c,0xb2,0x9e,0x96,0xc5,0x78,0xe9,0x3e,0xf2,0x50,
-0x88,0xef,0x5b,0x3c,0xd6,0x53,0xcf,0xf3,0x2f,0x93,0x5b,0x17,0x48,0xf0,0x56,0xf4,
-0x1d,0x24,0xaf,0xe3,0xe7,0xf4,0xe7,0x26,0x5b,0xd3,0xc8,0xad,0x15,0x24,0x31,0x1c,
-0xfe,0xb8,0x49,0x6a,0xe2,0x45,0xb9,0x70,0xea,0xff,0x06,0x6b,0xc9,0x82,0x3c,0xa6,
-0xe0,0x60,0x29,0x73,0xf0,0xe8,0x11,0xe6,0xa8,0xb6,0x8a,0xd1,0xea,0xab,0x15,0xfa,
-0x1a,0x9d,0xa2,0xa6,0x46,0xcb,0xb0,0x46,0x46,0xd6,0x60,0x9f,0x8e,0xa9,0xa9,0xd5,
-0x29,0x6a,0x6b,0xb5,0x4c,0x2d,0x1a,0x59,0x33,0xe8,0x18,0x83,0x51,0xa7,0x30,0x1a,
-0xf5,0x0a,0xa3,0x49,0xaf,0x30,0xb5,0x9e,0x55,0xb4,0xfe,0xf5,0x83,0xf4,0xbf,0xa2,
-0xbc,0xb9,0x19,0xc7,0xdb,0x45,0xda,0xe7,0x1c,0x9e,0x7b,0x2c,0x59,0x1e,0x64,0xe6,
-0x6c,0x8f,0xc7,0x9a,0xcd,0x63,0x3a,0x8c,0x80,0xe9,0x04,0xcb,0x91,0x99,0x73,0xfd,
-0x5e,0x8b,0xda,0x0b,0x7d,0xe8,0x84,0xef,0x75,0xf0,0xab,0xdc,0xc1,0x97,0xaf,0x66,
-0xbe,0xac,0xd3,0x2a,0x75,0x7a,0xad,0x52,0x2f,0x1e,0xd3,0xf5,0x30,0x07,0xab,0xd1,
-0xa6,0xb3,0xdf,0x9b,0x35,0x76,0xd4,0xeb,0xd2,0xd9,0xed,0x8c,0x1a,0xfc,0x3c,0x36,
-0x5d,0x75,0xba,0xae,0xea,0x68,0x7a,0x55,0x59,0x99,0xb2,0x4c,0x53,0x98,0xa6,0xc9,
-0xc8,0x60,0x32,0x64,0xcf,0x6d,0x0a,0xc3,0x61,0x4d,0x4b,0xf8,0x77,0x10,0xef,0x2d,
-0x68,0x7f,0xe7,0x30,0x05,0xc5,0x6a,0xa6,0x78,0x7f,0x1e,0xb3,0xbf,0xa3,0x45,0xd5,
-0xe1,0x19,0x7a,0xde,0x03,0x38,0x0e,0x36,0x6a,0x2f,0x1d,0x05,0x0b,0x39,0x0e,0x86,
-0x00,0xd3,0x51,0x0e,0xdd,0x59,0x86,0x7c,0x73,0xcc,0xf7,0x5a,0x1e,0xe0,0x79,0xdc,
-0x11,0x5f,0x1c,0xc5,0x11,0xe7,0xe4,0xf8,0x5e,0x9d,0x98,0x23,0x0e,0xe2,0xee,0xc8,
-0x46,0x8e,0x04,0x51,0x3d,0xdc,0x3f,0xd9,0xaf,0x46,0x1e,0x99,0x19,0x69,0x99,0x1a,
-0x4d,0x86,0xa6,0xa2,0x42,0x55,0xa1,0xad,0xce,0xd6,0xd6,0xe8,0x72,0xd8,0xff,0x75,
-0x4e,0x6d,0x8d,0x3e,0x87,0x3d,0x7e,0xea,0x1a,0x18,0xf1,0xb6,0xba,0xa6,0x56,0xaf,
-0xae,0x15,0x99,0x2e,0xc9,0x9c,0x35,0x83,0x3e,0xd7,0x60,0xd0,0xab,0x0d,0x86,0x9a,
-0x5c,0x83,0xb1,0x26,0xd7,0x08,0x56,0x57,0x9b,0x5b,0x57,0x67,0x60,0xad,0x46,0x5d,
-0x07,0xda,0x6b,0x59,0x99,0x8a,0x2c,0x38,0xc6,0x47,0x2a,0xd5,0x47,0x6e,0xfe,0xf1,
-0xc8,0x4d,0xc8,0xa5,0xe3,0xba,0x38,0x82,0xe5,0xf5,0xdf,0x40,0xcc,0x1d,0x6a,0xe2,
-0x16,0x7c,0xb5,0x0b,0x4b,0xfe,0xda,0xa5,0xf9,0x80,0x69,0x9e,0xd8,0x82,0xdf,0xb4,
-0xb0,0x10,0xa8,0x5b,0x58,0x0c,0x18,0x17,0xc1,0x37,0x8f,0xfb,0x6a,0xe2,0x71,0x9f,
-0x3e,0x0e,0x78,0x4e,0xd7,0xc5,0x01,0xa6,0x63,0xae,0xb8,0x13,0x0b,0xf3,0xa1,0x13,
-0x08,0xcf,0x79,0x1b,0x6d,0x9c,0xed,0xf9,0x44,0xdf,0x53,0x5a,0x4a,0xc5,0xb2,0x15,
-0x89,0xd7,0x3b,0x7d,0x2f,0xa6,0x6f,0x19,0x5a,0xdd,0x3e,0xa4,0xaf,0x86,0xfd,0xf3,
-0x66,0x1e,0xd3,0x01,0xcf,0xb1,0x9e,0x5a,0x43,0x1c,0x46,0xd0,0x62,0x01,0x8b,0x45,
-0x1a,0x63,0x88,0xef,0x15,0x74,0x54,0xc7,0x39,0x7e,0x38,0x52,0xe3,0xce,0x71,0xc4,
-0x81,0x7f,0x1e,0x1f,0x6b,0x8a,0xc7,0xc6,0x9b,0x63,0xb1,0xf1,0x96,0x18,0xe0,0x79,
-0xdf,0xa7,0xc7,0xfa,0x5a,0x9a,0x9f,0x6b,0xa9,0xae,0x2e,0xa8,0xae,0xae,0xce,0xe7,
-0xac,0xa0,0x5a,0x5b,0x9d,0xaf,0xc5,0xfb,0x38,0xd3,0x16,0x70,0xfb,0x0b,0xb4,0xd5,
-0xda,0x7c,0x3c,0x56,0x93,0x7d,0x85,0x5a,0xbc,0x5f,0x78,0x9d,0x60,0x85,0xf8,0x35,
-0xda,0x42,0xad,0xb0,0x5d,0xc8,0xbf,0x4f,0xd8,0x66,0x4d,0x5b,0x58,0x0d,0xb5,0x07,
-0x95,0x95,0xf9,0x95,0x25,0xa5,0x79,0x25,0x45,0x85,0xd9,0x45,0xe9,0xec,0xe3,0x9f,
-0x3d,0x17,0x71,0x3d,0x1c,0xf8,0xe7,0x5d,0x82,0x7f,0x4e,0xea,0xe0,0x78,0x4c,0xc7,
-0xf9,0x73,0xc4,0xed,0x3a,0xdb,0xf1,0x18,0x69,0xb0,0xcc,0x82,0x5e,0x6a,0xc7,0x13,
-0x41,0x6f,0xad,0x4b,0xcc,0x25,0xc3,0xce,0x9f,0xce,0xb2,0x78,0x3e,0x7d,0x71,0x67,
-0x77,0xba,0x75,0x17,0xec,0xd9,0xf4,0x85,0x67,0xc8,0x4f,0x07,0xff,0x1c,0x70,0x1e,
-0x19,0x8e,0xbd,0x0b,0xf9,0x73,0x2e,0xce,0x0e,0xfc,0x6f,0xd3,0x9d,0x9b,0x5f,0x7c,
-0xdc,0xf0,0x85,0x51,0x5f,0x6c,0x54,0x67,0x2a,0xd4,0x44,0x27,0x1a,0x61,0x79,0x16,
-0xe6,0x66,0x21,0x98,0x4e,0xf7,0x99,0xd3,0xf1,0x6b,0x1a,0xef,0xc8,0xb9,0x84,0xf5,
-0xd5,0xba,0x97,0x89,0xf6,0x39,0xce,0xa3,0x63,0x6d,0x16,0x62,0x09,0xd8,0x8e,0xb4,
-0xcd,0x65,0xb4,0xcf,0x1f,0x5e,0xdb,0x06,0xdf,0x1c,0x30,0x1c,0xd7,0xc4,0x09,0x78,
-0x0e,0xf9,0x73,0xe0,0x7b,0x95,0xc6,0xd7,0xe9,0x1a,0x77,0xd9,0x5c,0x39,0xed,0x07,
-0x49,0xfb,0x9c,0x65,0xf2,0xb1,0x09,0xb8,0x9e,0x42,0xcb,0x49,0x1a,0x3f,0x96,0x8b,
-0x5f,0xd0,0xd8,0x49,0xe3,0x75,0x02,0x56,0xf2,0x17,0xab,0x0c,0x86,0x4b,0x7d,0x15,
-0x1a,0xd9,0xe5,0xb0,0x9e,0x11,0x3e,0x47,0xba,0x9e,0xa0,0xd7,0x10,0xfc,0x7b,0x25,
-0xf1,0x00,0xfa,0xfb,0x8a,0xd6,0x30,0x72,0xf1,0x73,0xb9,0x3a,0xb8,0x24,0xc7,0x5d,
-0x5a,0x9b,0x01,0xe7,0xd4,0x73,0x07,0x98,0xe7,0x4e,0x9d,0x64,0x4e,0xfd,0xfc,0x65,
-0xe6,0xe7,0xef,0xfc,0xa7,0xe2,0x9d,0x8f,0x3f,0x54,0x7c,0xdc,0xf3,0xa9,0xa2,0xe7,
-0xcb,0xbf,0x2b,0xbe,0xfc,0xea,0xb6,0xe2,0xab,0xbe,0xdb,0x8a,0x3e,0x32,0xf6,0xdd,
-0x4e,0xeb,0x23,0xe3,0x9d,0xdb,0x69,0x77,0xd0,0xd8,0x93,0x76,0xe7,0xce,0x6d,0xe5,
-0x9d,0x3b,0x3d,0xd8,0xfa,0x6f,0x2b,0xfb,0xfb,0x7b,0xd2,0xfb,0x07,0x7a,0x95,0x03,
-0xc3,0x43,0xe9,0xc3,0x80,0xe3,0xd8,0x2f,0x67,0xf1,0xdc,0x9c,0x89,0xf1,0xdb,0x9c,
-0xe5,0xc1,0xd8,0xae,0xe2,0x30,0x1d,0xfb,0xe7,0x18,0xd3,0x61,0xce,0x8e,0x96,0x1c,
-0x0f,0xc4,0xdb,0xbd,0x56,0xb5,0x17,0xe6,0x38,0xee,0x9e,0xcb,0x3e,0x9f,0xe7,0x81,
-0x1c,0x3a,0x70,0xca,0x8c,0x58,0xf3,0x47,0x1c,0xf7,0xf3,0x1c,0x43,0x7d,0x79,0x43,
-0xe0,0xa7,0xf7,0xf5,0xe6,0xf5,0xdd,0xe9,0xcd,0xbb,0xd3,0xdf,0x9b,0xd7,0xdf,0xdf,
-0x9b,0xdf,0xdf,0xff,0x45,0x3e,0x1a,0xef,0x7e,0x91,0x7f,0xf7,0x6e,0x6f,0xc1,0xdd,
-0x81,0x2f,0x0a,0x06,0x06,0x7a,0x0b,0x06,0xee,0xf6,0x16,0xde,0xed,0xef,0x2d,0x64,
-0x9f,0x2f,0x62,0x9f,0x2b,0x62,0xe7,0x45,0xfd,0x7d,0x3d,0x45,0x7d,0xb7,0x3f,0x29,
-0xbc,0xfd,0xa7,0x77,0xf3,0xff,0xf4,0xda,0xaf,0xd5,0xaf,0xb5,0xb6,0xa8,0x5a,0x2b,
-0xca,0x95,0x15,0x10,0x03,0xa6,0xeb,0xd8,0x21,0xee,0x84,0xf0,0x9b,0xd3,0xf8,0x86,
-0x75,0x39,0xf4,0x1d,0x03,0xc7,0xad,0x46,0xcd,0x68,0x8a,0x73,0x99,0x62,0x62,0x6d,
-0x67,0x55,0x6d,0xae,0xa1,0x12,0x57,0xd0,0x5e,0x1a,0x24,0x3d,0x6b,0x88,0xf3,0xd5,
-0x89,0x7b,0xd0,0x61,0xe4,0x35,0x59,0x9c,0x94,0x26,0x0b,0xd2,0x54,0xc3,0xba,0xa9,
-0xa0,0xcf,0x82,0xfc,0x73,0xe0,0x87,0x73,0xbd,0xc0,0xe2,0xff,0x0b,0xc1,0x90,0xb3,
-0x32,0x04,0xb5,0xee,0xa8,0xde,0xdd,0x05,0x78,0x2e,0xd6,0x3f,0xff,0xb6,0x87,0x5c,
-0x8c,0x29,0x27,0x5b,0x99,0x53,0x55,0x95,0x5d,0xd5,0xd1,0x5e,0xd4,0xf1,0xd6,0x9b,
-0x25,0x6f,0x7d,0xf4,0x61,0xc5,0x47,0x83,0x5f,0x1e,0x19,0x34,0xf7,0xff,0x9b,0xd9,
-0x3a,0x70,0xd4,0x8a,0xed,0x45,0xab,0x75,0xf0,0x45,0x6e,0xac,0xb2,0xda,0x06,0xab,
-0x6c,0xb4,0x0d,0x0f,0x55,0x0d,0x0f,0x0f,0x56,0x63,0x1b,0x82,0x51,0xcb,0x8e,0xda,
-0x61,0xfb,0x90,0xd6,0x8e,0x4d,0x67,0x77,0x0c,0x69,0x1d,0x8e,0x7b,0x3a,0x87,0x73,
-0x48,0xeb,0x74,0xde,0xd3,0x39,0x9d,0x5f,0xeb,0x9c,0xf6,0x01,0x9d,0xfd,0xc6,0xff,
-0x1e,0xbe,0x51,0x67,0xc8,0xab,0xcb,0xca,0x4c,0xcb,0x82,0x78,0x77,0xf3,0x69,0x4d,
-0xf3,0x40,0xaf,0x76,0x00,0x7a,0xd8,0x04,0xed,0x73,0x53,0x14,0xea,0xe1,0x16,0xfd,
-0xb5,0x8b,0xcb,0x5e,0xfd,0xf2,0xb2,0xaf,0x66,0x79,0xc1,0x6f,0x44,0xf8,0x8d,0x30,
-0xfd,0x41,0xfd,0x3c,0xcc,0xc1,0x47,0x5f,0xf6,0xd7,0x2e,0xc7,0xfc,0x35,0x31,0xc0,
-0x75,0xc8,0xa3,0xa3,0xbe,0x73,0x16,0xcb,0x67,0x43,0x0d,0x28,0x9f,0x0e,0x7e,0x39,
-0xf8,0xe7,0xb3,0xe1,0x06,0xe4,0x9b,0xcf,0x86,0x1b,0x67,0xc1,0x3f,0x87,0x71,0xcc,
-0xdb,0x30,0xf6,0x9b,0xd7,0x2b,0x7f,0x93,0x97,0x97,0x99,0x27,0xbd,0xde,0xe9,0x6b,
-0x4d,0x7a,0x2f,0x81,0xb9,0x9c,0xfe,0x39,0xf2,0xcf,0x23,0x4d,0x4b,0xa0,0x7f,0x0e,
-0x9a,0x2c,0xa0,0x9b,0x0a,0xfe,0x38,0xd4,0xc2,0x21,0x0e,0xf7,0x48,0xe3,0x2a,0xe2,
-0x6f,0xa7,0xf9,0xe1,0x44,0x7c,0xaf,0xe7,0x1e,0x02,0x9e,0xaf,0x8e,0x9d,0x5e,0xc5,
-0x98,0xde,0x1c,0x9b,0x09,0x34,0xcd,0xb8,0xee,0x9f,0x72,0x59,0x06,0x1b,0x2c,0xe6,
-0xc1,0x06,0xb3,0x65,0xe8,0x94,0xc5,0x32,0x08,0xd6,0x80,0xc7,0x21,0xc1,0xac,0x83,
-0x0d,0xec,0xff,0xeb,0x94,0xd5,0x3a,0xd4,0x68,0xb5,0x0c,0x35,0xb2,0xcf,0x73,0xc6,
-0xce,0xad,0x43,0xa7,0xad,0x60,0x96,0x7b,0xa7,0xd9,0x6d,0xd6,0xee,0x51,0xfb,0x86,
-0xce,0xb0,0xf3,0x33,0x68,0x6e,0xbd,0xc7,0x8d,0xb0,0x7d,0x0f,0x9b,0xed,0xde,0x19,
-0x1b,0x6c,0xdb,0xee,0x35,0xd9,0xee,0xdf,0x3d,0x73,0xbf,0xef,0x76,0x63,0xdf,0xad,
-0x3f,0x9f,0xb8,0xf5,0xbb,0xb7,0x0c,0xbf,0xbb,0xd2,0x59,0x71,0xa5,0xba,0xaa,0xa8,
-0x9a,0x05,0x37,0xb5,0xdc,0xf9,0xb6,0x97,0x07,0xe9,0x3f,0x87,0x5e,0x35,0xe8,0x59,
-0xe3,0x7b,0xd0,0xb9,0xba,0x76,0x8c,0xeb,0xdd,0x5b,0x8f,0x66,0x85,0x7e,0x35,0xdc,
-0xa7,0xd6,0x25,0xdb,0xa7,0x26,0xe0,0x39,0x55,0x0f,0x07,0x75,0x6f,0x33,0xed,0xdb,
-0xa4,0x2e,0x0e,0x63,0x38,0xa9,0x89,0x6b,0x47,0x71,0x76,0x9c,0x47,0xef,0xc4,0xe3,
-0x5c,0xd7,0x0e,0xac,0x19,0x3c,0x43,0x67,0x3d,0x6d,0xcd,0xa5,0x6d,0x79,0xd9,0xca,
-0x3c,0xc2,0x9f,0x49,0x38,0xd0,0x69,0x7e,0x98,0x64,0x9c,0x6a,0x3c,0x6f,0x7b,0x9a,
-0x18,0xdb,0xaf,0xbf,0xae,0xbb,0x8e,0xfb,0xd5,0xae,0x09,0xfd,0x6a,0x7c,0x6c,0x9d,
-0x8b,0xb9,0x3f,0xbc,0x26,0xa9,0x75,0x17,0x1b,0xc6,0xf3,0x97,0x30,0xc6,0xb3,0x46,
-0x6b,0xa5,0x22,0x7d,0xb5,0xf9,0xab,0xb8,0x5f,0x8d,0xf5,0xcf,0x49,0x4d,0x2f,0xcf,
-0x79,0xc3,0xc5,0xd9,0x45,0xdf,0x95,0xe3,0x9b,0x49,0xe8,0x59,0x93,0xa9,0x7b,0x93,
-0x8b,0x89,0x26,0x68,0x76,0x2a,0xc4,0xf5,0xd6,0x09,0xf5,0xf1,0xb4,0x4f,0xca,0x48,
-0xf0,0x5c,0x1a,0x63,0x67,0x52,0x60,0xad,0xe4,0x7e,0x27,0xc5,0x69,0xb9,0xcf,0x48,
-0x7a,0x9f,0xa4,0x70,0x9e,0xc6,0x71,0xe9,0xe7,0xcb,0xf9,0xd9,0x09,0xbf,0x41,0x0e,
-0xd7,0x65,0xfc,0xf1,0xa4,0x6b,0x1e,0x99,0xe3,0xac,0xca,0x62,0x54,0xa7,0x1b,0x99,
-0xd3,0xbf,0x7d,0x83,0xf9,0x6d,0xcf,0x67,0x4c,0x8f,0x79,0x90,0x31,0x0f,0x9b,0x15,
-0xc3,0x76,0xb3,0xc2,0xee,0x30,0x2b,0x1c,0xc4,0x9c,0xe6,0x34,0xa7,0xc3,0x9c,0x26,
-0x9a,0xc3,0xe8,0x34,0x2b,0x45,0xe6,0x32,0xa7,0xb3,0x7e,0xb8,0xd2,0xe5,0xb2,0xa4,
-0xbb,0x46,0xcc,0xe9,0x08,0xbf,0xd1,0x68,0x06,0x1c,0xcf,0x70,0x23,0xb3,0xc0,0x98,
-0xc9,0xfb,0xe6,0x10,0x7b,0x47,0x73,0xb3,0x0a,0x61,0x3a,0x8a,0xbd,0x23,0x6c,0xcf,
-0x61,0xe7,0x39,0x6e,0x8c,0xe3,0x39,0x1e,0xcc,0x11,0x07,0xfc,0x70,0x6a,0x37,0xcf,
-0xe1,0x6e,0xc9,0x73,0x7b,0xac,0xf9,0x1e,0x30,0xc0,0xf5,0x11,0x6b,0x01,0x32,0xb7,
-0xad,0x90,0x7d,0x4d,0x21,0xfb,0xda,0x42,0xb7,0xdb,0x56,0xe4,0x76,0x5b,0x8b,0xd0,
-0xe8,0xb1,0x6a,0x3c,0x1e,0x1b,0x36,0xf7,0x70,0xb1,0x7b,0xc4,0xb6,0x6f,0x04,0xcc,
-0x6d,0xdb,0xe7,0x76,0x0f,0xb3,0x06,0xa3,0x6d,0x3f,0x32,0xa7,0x79,0xbf,0xf3,0x7e,
-0xff,0xbe,0xfb,0xef,0xfd,0x77,0xc1,0x7b,0x1d,0x6d,0xaa,0x8e,0xd2,0xe7,0xd2,0x4a,
-0x09,0x07,0x22,0x60,0x38,0xd2,0x9f,0x61,0x71,0x9c,0xc4,0xd8,0x80,0xd7,0x1e,0x19,
-0xfb,0x1c,0xe1,0x4d,0x84,0xeb,0x03,0xfa,0xcf,0x6d,0x43,0x25,0x36,0xd0,0x62,0x21,
-0x1c,0x71,0x3e,0x3b,0xd1,0x41,0x27,0x5a,0xa9,0xe5,0x7e,0xe2,0x9b,0x63,0x9e,0x38,
-0xcc,0x0d,0x87,0xed,0x30,0x6f,0x90,0x3b,0x0f,0xb9,0xa0,0x36,0x0e,0xec,0x05,0x64,
-0x61,0x57,0x65,0x18,0xf5,0xab,0xbd,0x03,0xfc,0x70,0xca,0x3d,0xf9,0xe7,0xd2,0xf3,
-0x1c,0xb0,0xb3,0xbc,0x3c,0xab,0xfc,0x95,0x97,0xf6,0xbd,0xf2,0xf1,0x87,0x15,0x1f,
-0x3b,0xcd,0x2f,0x3a,0x83,0x23,0xda,0x60,0xd8,0xab,0x0d,0x8f,0x7a,0x75,0xa3,0xa3,
-0x1e,0xce,0xbc,0x7a,0x64,0x11,0xaf,0x3e,0x82,0xad,0x26,0x32,0xe6,0xad,0x19,0x8b,
-0xf8,0xb8,0xd1,0x5b,0x1b,0x89,0xf8,0x6a,0x23,0x63,0xbe,0xda,0xb1,0x31,0x9f,0x61,
-0x6c,0xdc,0x6b,0x18,0x1f,0xf7,0x73,0xe6,0x33,0xb2,0xa3,0x11,0x8d,0x13,0x7e,0xe3,
-0x04,0x68,0xaa,0x61,0x5d,0x35,0x41,0x2b,0x35,0x32,0x62,0x88,0x7c,0x76,0xeb,0xe8,
-0x67,0x4d,0xa7,0x35,0x4d,0xd9,0xd9,0xca,0x6c,0xd0,0xed,0xfa,0xc5,0x2b,0x25,0xbf,
-0xf0,0x58,0x6a,0x3d,0xa8,0xbe,0x3d,0x60,0x9c,0x81,0x3e,0x35,0x94,0x1b,0xf7,0xe9,
-0x56,0x56,0xbd,0xda,0xd5,0x98,0x57,0x17,0x03,0x1f,0x7d,0x21,0x60,0x5c,0xc0,0x3e,
-0x7a,0x1d,0x87,0xe7,0xc6,0xa5,0x25,0x3f,0x6b,0x01,0xd3,0x12,0xe4,0xce,0x51,0xff,
-0x79,0xf0,0x64,0x14,0x70,0x1c,0xe6,0xc0,0x0f,0x87,0xe6,0x61,0xba,0x6f,0xad,0x11,
-0xdb,0x28,0x6b,0xa1,0xc6,0x19,0xd7,0xd7,0xf5,0xae,0xce,0xf6,0xe7,0x3b,0xd3,0x33,
-0xd2,0xc4,0xda,0x61,0x0a,0xf9,0xe3,0x48,0xe6,0x55,0x55,0x9a,0x2a,0xdb,0xc0,0x71,
-0xdb,0x7c,0xa4,0x69,0x5e,0xd0,0x4b,0x6d,0xc6,0xfa,0xe7,0xa3,0x67,0x96,0x81,0x4b,
-0x06,0xb8,0xdc,0x41,0x87,0x05,0xfc,0x73,0xc4,0xf7,0x1a,0x39,0xbd,0x02,0x9c,0xaf,
-0x18,0xcf,0xa5,0x1a,0x2c,0xe7,0x1e,0x42,0xee,0x1c,0x30,0x7c,0x73,0xb4,0x61,0x73,
-0x33,0x7c,0x72,0x73,0x2d,0xd2,0xb4,0x06,0x7e,0x3a,0xd4,0xba,0xaf,0x4c,0x9e,0x47,
-0xba,0xe7,0xb1,0x89,0xf3,0xb1,0xf8,0x44,0x4b,0x7c,0x75,0xe2,0xdc,0x6a,0x7c,0xf2,
-0x7c,0x3c,0x36,0xd9,0x1a,0x23,0x3a,0xe8,0xb0,0x6f,0x6d,0xf2,0xdc,0x5a,0x7c,0xea,
-0x42,0x5c,0xac,0x81,0x7e,0x91,0x1f,0x89,0xfe,0x79,0xfc,0x9b,0x76,0x64,0xa0,0x83,
-0xbe,0xf6,0x4d,0xdb,0x1a,0xb2,0xe9,0xf6,0xb5,0xd5,0x28,0xd1,0x41,0xbf,0xb4,0x0a,
-0xba,0xe7,0xc8,0xa2,0xd8,0xd6,0xa3,0x97,0xd6,0xf1,0xbc,0x03,0x59,0x7c,0xea,0x52,
-0x3c,0xfa,0xe0,0x42,0xf4,0xce,0xdf,0x1b,0xef,0xbc,0xf6,0xcb,0xaa,0xd7,0x8e,0x1e,
-0xd5,0x1c,0xcd,0xc8,0x48,0xcf,0xd8,0xcb,0xf9,0x49,0x3f,0x70,0xfe,0xbc,0x4d,0xc0,
-0x73,0xde,0x3f,0x17,0xf8,0x64,0x78,0x5e,0x19,0xae,0x16,0x0e,0xe5,0xcc,0x49,0xad,
-0xfb,0x1c,0xa7,0xaf,0x36,0x4b,0xfa,0xd1,0xbb,0x1f,0x13,0x5c,0x87,0x6d,0x3e,0xf6,
-0x0e,0x3d,0x69,0xb3,0x5d,0xa8,0x1f,0x1d,0xfc,0x76,0xc0,0x6d,0x12,0x67,0xc7,0xd6,
-0xc9,0x1b,0xbc,0x26,0xea,0x6e,0x8d,0xfe,0xea,0xa5,0x23,0xbf,0x2a,0xce,0xcf,0x28,
-0x46,0x3a,0x2b,0x84,0x97,0x9d,0xae,0x23,0xa3,0x72,0x90,0xdf,0x16,0xa3,0xa6,0xe7,
-0xb8,0x1e,0x0e,0xf7,0x9f,0xf3,0x1c,0x32,0x50,0xfb,0xb6,0x70,0x75,0x9b,0xdf,0xc7,
-0xf3,0xcb,0x5c,0xa3,0xf8,0x5e,0x39,0x9f,0x9c,0xc2,0xf4,0x9d,0xa5,0x97,0xc4,0x75,
-0x72,0x8b,0xb8,0x56,0x0e,0xe9,0xa5,0x22,0xfd,0x73,0x75,0x91,0x28,0x6e,0x4b,0xd7,
-0x04,0x91,0xfc,0x6a,0x3a,0x23,0xaa,0x01,0xa6,0xb9,0xe4,0xe8,0xdc,0x79,0x42,0x1e,
-0x21,0x19,0x0e,0x53,0xd8,0x25,0xbb,0x0e,0x90,0xec,0x17,0xc5,0xe8,0x15,0x62,0xcc,
-0x4b,0xea,0xc7,0x4b,0xb1,0x39,0xd5,0x6a,0x92,0xe0,0x32,0xf1,0xb3,0x93,0x7d,0x06,
-0x23,0xbc,0x8e,0xbe,0xe6,0x53,0xe2,0x75,0x32,0x0c,0x4f,0xe5,0xa7,0x33,0xe2,0xe3,
-0x91,0x0c,0xc3,0xe9,0x7e,0x83,0x82,0x7c,0xa6,0xe0,0xea,0x65,0xe6,0xea,0xe7,0x9f,
-0x30,0x9f,0x5b,0xef,0x29,0xac,0x76,0x33,0x63,0x27,0x38,0x0e,0x23,0x6c,0x63,0x3c,
-0x17,0x70,0xdc,0x69,0x56,0x38,0xf9,0xd1,0x92,0xc6,0xcd,0x59,0xb3,0xb0,0x58,0x6e,
-0x01,0x1c,0x57,0x62,0x3c,0x47,0xb8,0x9e,0x8e,0x7b,0xd3,0x2c,0xdc,0x08,0xf1,0x76,
-0x33,0xeb,0xa3,0x83,0xb1,0xbe,0x3a,0xf8,0xe6,0x04,0xcb,0xc1,0x5f,0x07,0x1c,0x17,
-0xf2,0xe6,0x2a,0x1f,0x8c,0x38,0xde,0x9e,0x8d,0xe2,0xed,0x60,0xa4,0x2e,0xce,0x6b,
-0xcd,0xf5,0xfa,0xac,0xb9,0x3e,0x9f,0x35,0x8f,0xdd,0x9f,0xe7,0xf3,0x5a,0xf3,0xbd,
-0x08,0xd3,0x6d,0x80,0xe5,0x05,0x6e,0x84,0xe3,0x56,0x76,0x04,0x5c,0xb7,0x15,0x22,
-0x7c,0x07,0x3c,0x1f,0xb1,0x69,0xd8,0xb9,0x86,0x7d,0xae,0x98,0xdd,0x26,0xb6,0x0f,
-0xe1,0xba,0xc7,0xb6,0xcf,0xe3,0x19,0xe6,0xcc,0xb6,0xdf,0xe3,0xb5,0x1d,0xf0,0x7a,
-0x87,0x0f,0xb0,0x9f,0x7b,0xc0,0x33,0xd0,0xab,0x19,0x78,0xf3,0xf5,0xdc,0x37,0xb5,
-0x47,0xd3,0xb5,0x10,0x4b,0xe3,0xaf,0x59,0xa9,0x16,0x11,0x55,0x13,0x42,0xfe,0x0f,
-0x34,0xdf,0x2b,0xc6,0x73,0xcc,0xf7,0xea,0x77,0x72,0x7a,0x2c,0xac,0x91,0x1a,0x77,
-0xdc,0xbb,0x56,0xc6,0xf7,0xac,0x89,0x38,0x5f,0x5d,0x5c,0x4d,0x9c,0x0b,0x6a,0xe2,
-0xc0,0x47,0xaf,0x44,0xda,0xa9,0xc1,0x11,0x18,0x8f,0x04,0xbf,0x2f,0x3f,0x5c,0x66,
-0xa6,0x22,0xd3,0x64,0xcc,0x35,0xfd,0xe1,0x7f,0x0e,0xfe,0x61,0xf8,0xeb,0xa3,0xc3,
-0x41,0xb7,0x36,0x38,0xea,0xd1,0x8e,0x86,0x3d,0xba,0x30,0x31,0x84,0xe9,0x5e,0x9d,
-0x04,0xcb,0x29,0x3c,0xe7,0x71,0x1d,0x63,0xf9,0xb8,0xaf,0x66,0x1c,0xb0,0x1c,0x61,
-0xba,0xbf,0x16,0xe1,0xf9,0x84,0xcf,0x38,0x01,0x78,0x0e,0x23,0xe0,0x38,0x70,0xc1,
-0x49,0xf1,0x7c,0xca,0x6f,0x9a,0x1a,0xf3,0x98,0xc6,0xbe,0xfa,0xbc,0xfa,0xab,0xce,
-0xf6,0x03,0x9d,0x85,0x05,0x19,0x85,0x07,0x9f,0xcf,0x3a,0x78,0xf3,0xbd,0xc3,0x37,
-0x27,0xdd,0x86,0x49,0xe8,0x51,0x5b,0xf4,0xd5,0x2c,0x02,0x86,0xaf,0x7b,0xb5,0xeb,
-0x1b,0xbe,0xea,0x8d,0xb8,0x57,0x17,0x07,0x2c,0x9f,0x0b,0xd4,0xcd,0xa1,0x78,0x7b,
-0xc0,0xb4,0xb0,0xe8,0x37,0x2e,0x2e,0x06,0x4c,0x8b,0xe0,0xab,0x13,0x8d,0x35,0xa2,
-0xc7,0x82,0xf1,0x1c,0x30,0xbc,0x01,0xf5,0xa8,0x89,0xb1,0x1c,0xcf,0x21,0xde,0x0e,
-0x98,0x3e,0x1d,0x3c,0x35,0xdd,0xf3,0xb7,0xda,0x1e,0xbd,0xae,0x40,0x9f,0x6c,0xdd,
-0x2f,0xf7,0xa8,0xac,0x2c,0xaa,0x34,0xf7,0x1d,0x37,0x0b,0x78,0xde,0xbc,0xb0,0x18,
-0x39,0xbb,0x08,0xbd,0xe7,0x18,0xcb,0xf1,0x18,0x0f,0x37,0xc4,0xc1,0x47,0x87,0xed,
-0x95,0x08,0xcd,0xdf,0x7e,0x0e,0xe7,0xd0,0x25,0x9a,0xa9,0x80,0xe9,0x1b,0xa3,0xa7,
-0x36,0x9e,0x84,0xea,0x9f,0x3c,0x1a,0x3d,0xf9,0x08,0xf2,0xe8,0x80,0xe5,0xc0,0x2d,
-0x03,0xb6,0x3a,0xde,0xbc,0xba,0x31,0x76,0x7a,0x63,0x23,0xd2,0xb8,0xb1,0x31,0x7e,
-0x66,0x23,0x3e,0x79,0x8e,0xc5,0xf4,0x0b,0x08,0xd3,0x63,0x53,0xad,0xb1,0xf5,0x89,
-0xe6,0xf5,0xf5,0x89,0x73,0xeb,0x3c,0xa6,0xb3,0x38,0x1e,0xff,0xa6,0x2d,0x1e,0x9f,
-0x62,0x0d,0xb0,0x9c,0xc7,0xf3,0x8b,0xf1,0xb5,0xa9,0xb6,0xb5,0xf5,0xa9,0xd6,0xf5,
-0xad,0x89,0x96,0xad,0xad,0x89,0xb3,0x5b,0x1b,0x53,0xad,0x1b,0x80,0xe9,0x08,0xd7,
-0x01,0xd3,0xa3,0x2c,0xa6,0x47,0x31,0xa6,0x63,0x2c,0xc7,0x38,0xbe,0x1e,0xed,0x58,
-0xa7,0xed,0xff,0x29,0x3b,0xd3,0xa7,0xb8,0xce,0x2b,0x8d,0x77,0xb3,0xb4,0x58,0x24,
-0xb1,0x69,0x41,0xd6,0x6e,0x45,0x20,0x44,0x37,0x48,0xd6,0x82,0x0c,0x62,0x5f,0x64,
-0x09,0x61,0x59,0x71,0xca,0x53,0xe5,0xf2,0x87,0x7c,0x48,0x26,0xe3,0x71,0x8d,0xe5,
-0xd8,0x63,0xa7,0x92,0x4a,0x8d,0xa7,0xca,0x93,0x29,0x7b,0xc6,0x65,0x4d,0x95,0x92,
-0x28,0x2e,0xdb,0xb2,0xe9,0x0d,0xd1,0xdd,0x77,0x69,0x10,0xf4,0xbe,0x37,0x8b,0x80,
-0xde,0x40,0x76,0x9c,0x71,0xfe,0x98,0x79,0xcf,0x7b,0xee,0x7b,0xb7,0xbe,0x80,0x87,
-0xaa,0x53,0xef,0x6d,0x1a,0x61,0xdc,0xdd,0xf0,0xeb,0xe7,0x9c,0xe7,0x9c,0x03,0xf7,
-0x27,0xe6,0xc6,0x13,0x0f,0xfe,0xbb,0xe7,0xc1,0xc4,0xe8,0x89,0x09,0xd0,0xea,0xff,
-0x9f,0xd7,0x67,0x6b,0x6b,0x4b,0x2b,0xf3,0xc3,0x15,0xd3,0x93,0x2a,0x7d,0xce,0x6a,
-0xe8,0x53,0x72,0x60,0xde,0x9d,0x5c,0x67,0x30,0x34,0x7d,0xe8,0x99,0x97,0x91,0xf5,
-0x30,0xa3,0x3d,0x8d,0x7b,0xd6,0x70,0xdf,0xda,0x6d,0x7a,0x7e,0x9b,0x96,0xf6,0xa2,
-0xb2,0x1d,0xe8,0x69,0x65,0x66,0x1c,0xb0,0x9e,0xce,0x99,0x49,0x63,0xac,0x07,0x6e,
-0xac,0xbf,0xf3,0x4f,0xb6,0x77,0x8e,0x1c,0xa8,0x39,0x62,0x34,0x93,0x5d,0xfd,0xf7,
-0x81,0x71,0x5d,0xef,0x1d,0xa3,0x7f,0x2b,0x2a,0x75,0x33,0x3d,0x25,0x2f,0x2e,0xec,
-0x57,0x63,0xfd,0x6a,0xca,0x1c,0x19,0x35,0xcb,0xd9,0x2e,0x74,0xec,0x27,0x67,0x33,
-0x60,0xd9,0x0e,0x74,0x36,0xf3,0x15,0xfd,0x70,0xac,0x8e,0x2e,0x7d,0x9d,0x34,0x6b,
-0x86,0xce,0x87,0xfb,0x97,0xcb,0x1f,0xb4,0x34,0xd7,0xb7,0xa8,0xe7,0x89,0xea,0x59,
-0xa4,0xf7,0x17,0x19,0xe6,0xd4,0x2b,0x95,0xff,0x17,0xfd,0x6c,0x39,0x0d,0x97,0x2a,
-0x54,0x79,0x2d,0x75,0x5e,0xda,0x20,0xbf,0xad,0xcf,0x63,0x6f,0xc7,0x3d,0x23,0xbd,
-0x5e,0xc6,0x64,0x1d,0xaf,0xe9,0xf7,0xd7,0xd5,0xc3,0x8d,0xf2,0xf2,0x46,0xba,0xbd,
-0xec,0xe7,0x32,0x7a,0x1f,0xa1,0xfa,0xf7,0xdb,0xfe,0xfc,0xba,0xcf,0xab,0x73,0xec,
-0xdb,0xe6,0x39,0xb6,0xa9,0x6b,0x34,0x34,0x98,0x1a,0x5e,0xff,0x07,0xd3,0xeb,0x9f,
-0x3f,0x30,0x7d,0xee,0x9e,0x36,0xb9,0x1f,0x4f,0x2b,0x5a,0x5c,0xaf,0xcb,0x67,0x1d,
-0x66,0xa2,0xbb,0xcd,0x1e,0x60,0xb8,0xc7,0x5e,0xe1,0x61,0x81,0xf7,0x55,0xcc,0x02,
-0xbf,0x81,0xe7,0xb3,0xf6,0x2a,0x64,0x3a,0xe1,0xf8,0xac,0xa3,0x4a,0xba,0x5d,0x85,
-0x3c,0xa7,0xb5,0x73,0x8b,0xa4,0xd3,0x21,0xdf,0x6e,0xe1,0x20,0x04,0xfb,0x1e,0xc2,
-0x63,0x8b,0x20,0x3a,0xf6,0x88,0xa2,0xbd,0x46,0xf4,0x3b,0x6a,0xfc,0x7e,0x7b,0xad,
-0xdf,0xef,0xa8,0xf5,0xcf,0x39,0x6a,0xe7,0x20,0xe6,0x1d,0x75,0xf3,0x2c,0xc0,0x0b,
-0xc7,0xea,0xe8,0x7e,0xc7,0x5e,0x72,0xbd,0x57,0x04,0x9e,0xd3,0xfc,0x3b,0xd1,0xe7,
-0xe0,0x8f,0xf3,0x38,0x1b,0x69,0x00,0xc7,0xbd,0xce,0x26,0xa2,0xbf,0x9b,0xbc,0x54,
-0xa3,0x13,0x8e,0xa3,0x36,0x6f,0xe2,0x04,0x67,0xb3,0x20,0xba,0x9a,0x45,0xc1,0xd5,
-0x2c,0x70,0xee,0x16,0x0e,0x98,0x8e,0x1c,0x3f,0xc0,0xf1,0xee,0x83,0x3c,0xef,0x3a,
-0x48,0x59,0x8e,0xd7,0x84,0xe9,0xee,0xc3,0x9c,0xe3,0xcb,0x83,0x8e,0xf7,0x7f,0xdd,
-0xf0,0x7e,0x7b,0x5b,0x55,0x3b,0xbc,0x7e,0xd5,0xcc,0x66,0xcf,0x83,0xe6,0x35,0x21,
-0x3d,0xf7,0x3d,0x3d,0x35,0x3d,0xce,0xaf,0x15,0x9e,0x23,0xc3,0x71,0x67,0x2a,0x7a,
-0xdb,0x8f,0x53,0x86,0x33,0x8e,0x2f,0x3e,0x3e,0xbe,0x18,0x78,0x7c,0x82,0xce,0x90,
-0x01,0x5f,0x3b,0x78,0xe0,0x64,0x8d,0xee,0x81,0x9c,0xbb,0xb4,0xf7,0xdc,0x8b,0x7b,
-0x58,0x70,0x7e,0xfb,0xd9,0xb9,0xed,0xea,0xe7,0x3b,0xb1,0xa7,0xba,0xca,0x5c,0x7d,
-0xf9,0x85,0x7d,0x97,0x3f,0xfd,0xcf,0x53,0x9f,0x8a,0x8f,0xcf,0x89,0x0b,0xbe,0x0e,
-0xc2,0x6f,0xa2,0xc9,0x29,0xcf,0xe1,0x54,0x38,0xbe,0xc8,0x59,0x25,0x7d,0x6e,0x93,
-0xb8,0x6e,0x0b,0x80,0x2e,0x07,0x4d,0x1e,0x14,0x6c,0xc1,0x20,0x2f,0x71,0x9c,0x44,
-0x84,0xb7,0x11,0x5e,0x77,0x85,0x43,0x42,0x97,0xa4,0xcd,0x15,0x7d,0x1e,0x16,0xba,
-0xc3,0x8c,0xe1,0x10,0x8c,0xe9,0xc0,0xf3,0xb8,0x78,0x21,0x0e,0x9e,0x76,0x60,0xbe,
-0xfd,0xe1,0x79,0xfb,0x1b,0xaf,0x1d,0x79,0xe3,0x78,0xab,0xe5,0x78,0xcf,0xc5,0x7d,
-0x3d,0xee,0x3f,0xb7,0xbb,0x97,0x05,0xeb,0xf2,0x1a,0x7f,0x7e,0x2d,0xcf,0x75,0xe4,
-0xf3,0x7c,0x47,0x3e,0xc7,0x77,0xe4,0x20,0xdf,0x9e,0xf1,0x5f,0xc8,0x40,0x50,0x8e,
-0x93,0x80,0xfa,0x79,0xc6,0x4f,0x58,0xfe,0xe4,0x6a,0x52,0xe6,0xb8,0x34,0x23,0x8e,
-0xf2,0x5c,0xf2,0xc5,0xa5,0x9e,0x40,0xbd,0xbc,0x27,0x85,0x5e,0x38,0x49,0x97,0x43,
-0xbe,0x9d,0xf0,0x9c,0xc6,0x42,0x5f,0x2a,0xc8,0x5d,0x0b,0xbe,0xf7,0xf6,0xd9,0xf7,
-0x0e,0x1f,0xae,0x3b,0xac,0xfe,0x7d,0xdf,0xe9,0xe3,0xc4,0x89,0x86,0x13,0x8f,0xfe,
-0x74,0xf9,0x51,0x66,0x71,0x40,0xa5,0xcf,0x07,0xa8,0x3e,0xc7,0x39,0xaf,0x30,0xb3,
-0x9d,0xf0,0x7c,0xb1,0x97,0xd6,0xd1,0x57,0x42,0x03,0x2b,0xab,0x21,0x9c,0xdf,0xae,
-0xd6,0xe7,0xfa,0x7c,0x3b,0xf0,0x1c,0x72,0xee,0xa5,0x85,0x9e,0xd2,0xd6,0xc2,0xd5,
-0x2d,0x60,0xf7,0x5a,0x78,0x78,0x8d,0x31,0x7d,0x3d,0x3c,0xbc,0x5e,0x08,0x5e,0x2f,
-0x14,0x03,0x7d,0xc5,0x62,0xb0,0xaf,0x98,0x0f,0x0d,0xe4,0xd7,0xc3,0x23,0xeb,0x54,
-0xab,0x47,0xc7,0xd6,0x72,0xe1,0xa1,0x5c,0x31,0x34,0x50,0x44,0x9d,0x0e,0x0c,0x57,
-0x71,0x9c,0x5d,0x4b,0x3c,0x07,0x96,0x6f,0x86,0x07,0x37,0xbf,0x0d,0xf6,0x7d,0xfb,
-0x5d,0xb0,0xf7,0xbb,0x67,0xa1,0xfe,0x67,0xc5,0xe8,0x68,0x31,0x1f,0x9b,0xc8,0x33,
-0xae,0xe7,0xe3,0x37,0xf2,0xf9,0xf8,0x04,0xb2,0x5c,0xe2,0x7a,0x3e,0xa9,0xe5,0x79,
-0x21,0x79,0xb3,0x90,0x4f,0xde,0xca,0xaf,0xc5,0x5e,0x5a,0xf3,0x7e,0x33,0xe8,0xbd,
-0x3b,0x75,0xe6,0x6e,0x7d,0xfd,0x8f,0x67,0x3a,0xf4,0x9f,0x67,0xe6,0xc7,0x33,0xc0,
-0xf2,0xed,0xf4,0xb9,0xcc,0x71,0xca,0xf4,0xdb,0x32,0xbb,0xf1,0xc4,0x7e,0x35,0x65,
-0x47,0xaa,0x14,0x69,0xd5,0x35,0xdb,0x95,0xca,0xf6,0xad,0x65,0x71,0x7e,0x3b,0x9b,
-0xf7,0x8a,0xd7,0xc8,0x7b,0xf0,0xc7,0x7f,0xfc,0xef,0x57,0x3f,0x3e,0x71,0x74,0xef,
-0x09,0xcd,0x5e,0x15,0x8b,0x6e,0x26,0xbb,0x41,0x8e,0x5d,0xaf,0x69,0x69,0x98,0x25,
-0x6d,0xab,0xaa,0x43,0xff,0xf2,0x97,0x98,0x6f,0xff,0x6e,0xe9,0x15,0x65,0x9e,0x0c,
-0xf4,0x98,0x43,0xdf,0x99,0xb4,0x43,0x8d,0xed,0x3d,0xff,0xdb,0xd2,0x14,0xdd,0xa1,
-0x4a,0xfb,0xcb,0xb3,0xcc,0xf7,0x86,0xd7,0xf2,0xfc,0xd7,0xe5,0x57,0xa4,0xcf,0xdf,
-0x96,0x7b,0xd1,0x61,0xbf,0xda,0xef,0xee,0xbd,0xf0,0xbb,0xe7,0x0e,0xd5,0x3d,0xc7,
-0xde,0x83,0xb0,0xda,0xb9,0x7e,0x37,0xfb,0x76,0x9c,0x64,0x51,0x56,0x4b,0xd7,0xf5,
-0x46,0x19,0xcd,0x80,0x35,0xcc,0xa9,0x6f,0xc3,0x50,0x7a,0xdb,0xfc,0x23,0x38,0x6a,
-0x32,0xb8,0xdf,0x5c,0xfe,0x79,0x8d,0x0e,0x57,0xd5,0xd3,0xd5,0xd7,0xf2,0xfb,0x0c,
-0xf5,0xcf,0xa3,0xfa,0x9c,0xfa,0x7b,0xb3,0x9f,0xcf,0xf0,0xf1,0xd9,0x86,0xeb,0xea,
-0xc7,0x76,0x5b,0x9f,0x76,0x85,0x12,0xfa,0xda,0x04,0x7b,0x2c,0xeb,0x6b,0x4d,0xf5,
-0xaf,0xfd,0xd4,0xf4,0xda,0x5f,0x1e,0x98,0xfe,0x32,0x33,0x0d,0x1a,0xdc,0xf4,0x98,
-0xc5,0xec,0xb4,0x79,0x16,0xd8,0x8e,0x3a,0xdc,0x28,0x2a,0x28,0xd3,0x1f,0x3b,0x58,
-0xbe,0x5d,0xd2,0xe6,0x76,0xb5,0x2e,0xc7,0x13,0x6b,0xe5,0x55,0x3e,0xce,0x5e,0x45,
-0xd8,0x5d,0xcd,0x71,0x76,0x0b,0x3d,0x79,0xbb,0x85,0x87,0x10,0xec,0x16,0xc2,0x72,
-0xc2,0x73,0xc2,0x74,0x99,0xe7,0xf6,0x1a,0xff,0x9c,0xbd,0x66,0x0e,0x62,0xde,0x51,
-0x33,0x3f,0x6f,0xaf,0x9d,0x7f,0xe2,0xa8,0x7b,0xb2,0xe0,0xa8,0x5d,0x80,0x73,0xde,
-0x0e,0x5c,0xaf,0x9f,0x17,0x9c,0xa0,0xd7,0xf7,0x0a,0xa0,0xd3,0x65,0x96,0x3b,0x81,
-0xe5,0xfb,0x3d,0x2c,0xe7,0x4e,0x75,0x39,0xd1,0xe9,0x9c,0xb3,0x91,0xe8,0xf9,0x26,
-0xa2,0xe7,0x9b,0x04,0xd1,0xd9,0x24,0x02,0xc7,0xfd,0xce,0x46,0xff,0x9c,0xab,0x79,
-0xce,0xef,0x6c,0xf6,0xf3,0xae,0x16,0x9e,0xf2,0x9c,0x68,0x72,0xc8,0xb9,0x73,0xee,
-0x83,0x1c,0xc6,0x21,0x1a,0x3e,0xf7,0x21,0x1f,0xc6,0x61,0x9f,0xf3,0xeb,0x43,0xce,
-0xb7,0xde,0xdc,0xff,0xd6,0x91,0x23,0x95,0xdb,0xce,0xcc,0x56,0x3f,0x57,0xf0,0x78,
-0xd3,0xfd,0x6a,0x5f,0x1d,0x75,0x89,0x33,0x47,0x45,0x98,0x27,0x83,0x3d,0xe8,0xd8,
-0x8b,0xce,0x3c,0x71,0x10,0xc0,0x71,0xe4,0xf9,0x89,0xc5,0x27,0x8f,0x4f,0xd2,0x7e,
-0x73,0xdc,0x7d,0x7e,0x1a,0x77,0x9f,0xb3,0x3d,0xe8,0xd2,0xde,0x54,0x65,0xc7,0x9a,
-0xb4,0xff,0xfc,0x7d,0xa8,0x9f,0xff,0xf8,0xfe,0x73,0xf2,0x03,0x56,0xb4,0x9d,0xad,
-0x69,0xbb,0xff,0xf1,0xc9,0xfb,0xf3,0x9e,0x73,0xf3,0xc0,0xf2,0x27,0x5c,0xc7,0x13,
-0x35,0xd3,0x21,0x02,0x5c,0x67,0xc0,0x28,0xe7,0x0e,0x5c,0x47,0x9e,0x5b,0xa9,0x36,
-0x0f,0xf1,0xd6,0x50,0x98,0xb7,0x85,0x51,0x9b,0x03,0xd7,0xbb,0x24,0x8e,0xa3,0x4e,
-0x07,0x46,0x03,0xcb,0x23,0x62,0x77,0x24,0x2c,0x92,0x53,0x50,0xf2,0xed,0x31,0x81,
-0xb0,0x5c,0xe8,0x8a,0x27,0xc4,0xee,0x04,0x04,0xe5,0x3a,0xf9,0x1c,0xf7,0x8d,0x95,
-0x7b,0xfb,0x1f,0x8f,0xbd,0x6d,0x3b,0x63,0xb1,0xfd,0xfc,0x4e,0xcb,0xcf,0xb3,0x8f,
-0xdb,0xb2,0x1b,0xdc,0xb9,0x0d,0x60,0xfa,0xaa,0x00,0xb5,0x73,0xac,0x9f,0x2f,0x09,
-0x5d,0x4b,0x50,0x43,0xa7,0xf9,0x76,0xf1,0x62,0x06,0xb4,0x3a,0xcc,0x8a,0x63,0xbd,
-0xe8,0xc8,0x73,0x64,0xb9,0xc6,0x0f,0x37,0x7f,0x35,0x95,0x99,0xbf,0x9a,0xa1,0xf5,
-0x74,0x29,0xd7,0x0e,0xb5,0x73,0x1a,0x8b,0x7d,0x18,0x84,0xe9,0xbc,0xf3,0x0a,0xff,
-0xea,0x9d,0x63,0xaf,0x12,0xc1,0x55,0xf3,0x63,0x1e,0xdb,0x96,0x03,0x7b,0x5b,0x1e,
-0x7e,0x76,0xe1,0x61,0x7a,0xb1,0x3f,0xcd,0x58,0x4e,0x79,0x1e,0xe8,0x5f,0xa6,0xf3,
-0xdc,0x29,0xdb,0x07,0x96,0x69,0x8e,0x3d,0x70,0xfd,0x29,0xee,0x4d,0x25,0x2c,0x87,
-0x99,0x32,0xe1,0x41,0xc9,0xdb,0x3e,0xb4,0xa2,0xdd,0xaf,0x36,0x2c,0x69,0xf4,0xa1,
-0xd5,0x5c,0xa0,0x2f,0xb7,0xb9,0x70,0x75,0x93,0x6a,0xf4,0x10,0x68,0xf4,0x61,0xca,
-0xf3,0xa7,0x91,0xd1,0xa7,0xc0,0xf4,0x5c,0xb0,0x3f,0x57,0x08,0xf5,0x17,0x80,0xe7,
-0x34,0x88,0x2e,0x07,0xa6,0x83,0x2e,0xcf,0x87,0x86,0xe8,0xed,0x8d,0xc8,0xc8,0x06,
-0x6a,0xf4,0x09,0xd4,0xe8,0xf1,0x09,0x99,0xed,0xb9,0xd8,0x58,0x2e,0x17,0x1d,0xcd,
-0x15,0x23,0xc3,0xc5,0x67,0xc1,0xeb,0xcf,0xbe,0x0b,0x10,0x9e,0x93,0x73,0x2b,0x34,
-0xb0,0x55,0x8c,0x8e,0x14,0x0b,0xd1,0xb1,0x02,0xe8,0xf5,0x52,0x74,0xa4,0x54,0x8c,
-0x8e,0x15,0x81,0xeb,0x2c,0xd7,0x9e,0x4f,0x12,0xa6,0x13,0xae,0x17,0x12,0x37,0x0a,
-0xb9,0x24,0xdc,0xbe,0x99,0x67,0xb1,0x11,0xbb,0xb9,0xe1,0x77,0x0d,0xfb,0x27,0x46,
-0x4f,0x4d,0x58,0x2c,0x55,0x96,0x1f,0xf3,0x58,0xb2,0x79,0xaf,0x54,0x9f,0x4b,0x3c,
-0x67,0x75,0x74,0x9c,0x15,0x07,0x33,0xe3,0x26,0x8d,0x67,0xc3,0x65,0xd4,0x33,0xe2,
-0xa4,0x7d,0xe7,0xe4,0x94,0x59,0x9f,0x9d,0xd2,0x32,0x1e,0x22,0xfb,0xb2,0x86,0xe9,
-0xea,0x3d,0x6b,0x10,0xfc,0xe3,0x11,0xfe,0xf9,0x53,0x2d,0xcf,0xab,0xf7,0x55,0x94,
-0xf5,0xa9,0xb2,0xba,0xb3,0x3e,0xdf,0x5e,0xa5,0xeb,0xf1,0xaa,0x54,0x74,0xba,0xda,
-0x5b,0x4e,0xeb,0xe7,0x44,0x9f,0xc3,0x1c,0x19,0x64,0xf9,0x4f,0xe5,0xbe,0x34,0x99,
-0xe7,0x24,0xfe,0x96,0x99,0xc4,0x5d,0xe8,0x59,0x7d,0xbc,0xac,0x09,0x36,0xe3,0x1d,
-0x59,0x8e,0xff,0xf6,0xfb,0xd4,0xe4,0xf7,0xbf,0xbf,0x77,0xf1,0xf7,0x27,0x5b,0xeb,
-0x4e,0x36,0xd4,0x9a,0x1a,0xa0,0x6e,0xc8,0x72,0x0d,0xea,0x5d,0x6a,0x65,0x75,0x73,
-0xb5,0x86,0x31,0x62,0x97,0x9e,0xbb,0x06,0x0c,0x33,0xf4,0xc4,0x19,0xcd,0xa1,0xd1,
-0xf1,0x90,0xfe,0x7d,0x35,0xc8,0x8f,0x19,0x6a,0x6c,0xdd,0x7d,0x7a,0xee,0xcb,0x77,
-0x1a,0xbc,0x3f,0xd0,0xde,0x2d,0x5d,0xeb,0xef,0x53,0xbf,0x37,0x30,0xfa,0x7f,0x56,
-0xbd,0xd7,0xd1,0x6b,0x70,0x7d,0x0d,0x61,0xa7,0x7a,0xb9,0xcc,0xee,0x4a,0x65,0x86,
-0x38,0x7b,0x0d,0xc1,0xeb,0x6a,0x6c,0xc8,0x34,0xf6,0xe0,0x33,0xd3,0x03,0xca,0x72,
-0x59,0x97,0x13,0x9e,0xc3,0xb5,0x4a,0xa7,0xab,0x6b,0xe8,0x0a,0xcb,0xcd,0x84,0xd3,
-0x15,0x5e,0x08,0x9f,0xbd,0x92,0xb0,0xba,0x92,0xe3,0xa6,0x49,0x90,0x93,0xb7,0x57,
-0x11,0x4e,0x57,0xf2,0xf4,0x73,0xc0,0x70,0x12,0x50,0x2b,0xe7,0xec,0xc0,0xf2,0x6a,
-0x99,0xe5,0x54,0x97,0x13,0x4d,0xce,0x3b,0x08,0xd3,0x41,0x9b,0xdb,0x2d,0x22,0xf0,
-0x9c,0xb2,0xdc,0x81,0x2c,0xa7,0x27,0xd5,0xe6,0xb5,0xf3,0x10,0x73,0x8e,0xba,0x39,
-0xd0,0xe6,0x4c,0x9f,0x83,0xb7,0x5d,0xf6,0xc3,0xb9,0xf6,0xd3,0xa0,0xf9,0x75,0x12,
-0x9c,0xb3,0x81,0x83,0x10,0x9c,0x0d,0x82,0xe0,0x22,0xe1,0x6c,0x24,0x1c,0x6f,0x14,
-0x81,0xe5,0xc0,0x6f,0x76,0xfa,0x5d,0x4d,0x7e,0xc1,0xd5,0x22,0x60,0xcd,0xfc,0x80,
-0xcf,0xeb,0x3e,0x48,0xbe,0xcf,0x41,0xaf,0x9a,0xdf,0x5e,0xf7,0x21,0x2f,0x9c,0xbe,
-0x19,0x12,0xee,0x56,0x1a,0xf6,0xaf,0x0e,0xd9,0x5f,0xbd,0x5b,0xff,0xea,0xde,0x7a,
-0xf3,0x5e,0x39,0xaf,0x62,0x56,0xed,0xb0,0x95,0x3c,0x86,0xca,0x3c,0x19,0x98,0x0f,
-0xf7,0x9c,0x1b,0x19,0x7e,0x14,0xfb,0xcd,0xe5,0x59,0xaf,0x10,0xa8,0xcf,0xc1,0xe3,
-0xae,0xde,0xaf,0x46,0xfd,0x70,0x1e,0xf5,0x0e,0xf4,0x33,0x7e,0x75,0xaf,0x1a,0x9b,
-0xe1,0xae,0xde,0xc7,0xb2,0x5b,0xff,0x39,0xfb,0x80,0x9f,0xb5,0xb9,0xa9,0xb2,0xf9,
-0x0f,0x1f,0x1e,0xfd,0xc3,0xbc,0xa7,0x7d,0x7e,0xd1,0x77,0x8e,0xb0,0xba,0x83,0x68,
-0x72,0x64,0x79,0x80,0xeb,0x08,0x40,0x04,0x7d,0x1d,0xc1,0x20,0x77,0x3e,0x48,0xd9,
-0xae,0xcf,0xb7,0x73,0xc0,0x71,0x6b,0x30,0xcc,0x59,0xc3,0xc0,0xf2,0x10,0x87,0x1c,
-0x07,0xad,0x0e,0x2c,0x47,0x86,0xa3,0x46,0x8f,0xf0,0x5d,0x91,0x88,0x80,0x1c,0x87,
-0xda,0x39,0xab,0x9f,0x33,0x96,0xc7,0xc4,0xee,0x18,0x70,0x3c,0x29,0x76,0x25,0x93,
-0x62,0x77,0x32,0x29,0x74,0x25,0x53,0x62,0x77,0x2a,0x29,0x5c,0x48,0x86,0x1f,0x5b,
-0xc3,0x0f,0x3e,0x3a,0xf1,0xe0,0x67,0xc3,0x7b,0x7f,0xe6,0xf8,0xaf,0xe3,0x8e,0x75,
-0xae,0x63,0x7d,0x59,0xb0,0x2d,0x2f,0x89,0xb6,0x25,0x5a,0x37,0x17,0xba,0xb3,0x74,
-0x5e,0xdc,0xdc,0x0b,0x69,0xd8,0x8d,0x0e,0xda,0x1c,0x7a,0xd7,0x60,0x36,0x5c,0xe2,
-0xc9,0xd5,0x04,0xe3,0xb9,0x3c,0x1b,0x8e,0xe9,0xf2,0x27,0xc8,0x72,0xf0,0xc3,0xa1,
-0x17,0x0e,0x7c,0xed,0x2f,0xaa,0xb8,0xde,0x27,0x33,0x1d,0x6a,0xe9,0x7f,0xfc,0xac,
-0xfb,0x8f,0x98,0x77,0x37,0xef,0xa2,0xce,0x4d,0x20,0xcc,0xf6,0x7c,0xfa,0x91,0xed,
-0xd3,0xf4,0xe2,0x00,0xe5,0x39,0xcc,0x89,0x83,0xbd,0xa9,0xa0,0xcf,0x81,0xe3,0x30,
-0xdf,0x15,0xd8,0x0d,0x2c,0x87,0xcf,0x03,0xcb,0xe9,0xe7,0x98,0x17,0x2e,0xa4,0xd4,
-0xcf,0x95,0x5a,0x3a,0xdb,0xc5,0x82,0x75,0xf4,0xc2,0x62,0x6f,0x01,0x6a,0xe9,0xc0,
-0xee,0xb5,0x08,0xd1,0xe8,0xd1,0xd1,0xa7,0x4f,0x23,0x63,0x4f,0x81,0xe9,0x1b,0xa1,
-0xa1,0x8d,0x5c,0x68,0x30,0x07,0x01,0xfc,0xce,0x85,0xc9,0x75,0x18,0x6b,0xe7,0x10,
-0xb9,0xc8,0x48,0x2e,0x1f,0x19,0x21,0x7c,0x1d,0xdb,0xd0,0x6a,0x74,0xd4,0xe7,0x85,
-0xc8,0x70,0x01,0x22,0x1f,0x1b,0xcb,0x03,0xb7,0x37,0xc3,0x03,0x9b,0x5b,0xa1,0xfe,
-0xad,0x67,0xa1,0x81,0x67,0x9b,0xe1,0xa1,0xcd,0x52,0x64,0xa8,0xb4,0x15,0x1e,0xdc,
-0x7a,0x16,0x1e,0x7c,0xb6,0x15,0x19,0xda,0x2a,0xc5,0x46,0x4b,0x85,0xf8,0x44,0x81,
-0xea,0x75,0xd0,0xe4,0xf1,0x1b,0x85,0x52,0x6c,0xbc,0x54,0x8c,0x8d,0x17,0x0b,0x89,
-0x97,0x0a,0x0a,0xd3,0x6f,0xd1,0xfb,0x3d,0xd3,0xfd,0x9e,0x8e,0xf6,0x03,0x1d,0x15,
-0xe6,0xdd,0xf7,0xdf,0xb0,0xfe,0x73,0x9c,0xdd,0x3e,0xa9,0xe8,0xf2,0x14,0xf4,0xa9,
-0x4d,0x96,0xa0,0x47,0x8d,0xee,0x5c,0xa3,0xfe,0xb7,0xdb,0x5b,0x72,0x1d,0x5d,0xe2,
-0x38,0xeb,0x3d,0x2f,0xd3,0xe7,0x06,0x0c,0xa7,0x67,0xf6,0x8e,0x7c,0x22,0xd3,0xd9,
-0x5e,0xb5,0x97,0xbf,0xcd,0x3c,0x79,0x29,0xd3,0x77,0xed,0x54,0x1f,0xf9,0x25,0x2f,
-0x9b,0xc3,0xae,0x9f,0x21,0xa9,0x9f,0x39,0xa5,0xd9,0x39,0xa6,0x9b,0xfd,0xaa,0xf7,
-0x80,0x23,0xcf,0x89,0x3e,0x5f,0x7e,0xe5,0xbb,0xb2,0xf9,0xae,0xd2,0x9e,0x73,0xca,
-0xed,0xcc,0xcb,0xa8,0xcf,0x33,0xe5,0x0c,0xc7,0xfc,0x3a,0x04,0xe8,0x73,0xe9,0x04,
-0x8f,0xfb,0x12,0xce,0x7d,0xfd,0x6b,0x6a,0x8a,0xee,0x3f,0x3f,0xde,0x5a,0x77,0x1c,
-0x78,0xce,0x82,0xee,0x42,0x97,0xfc,0x40,0xf2,0x1e,0x74,0xe6,0xf3,0x63,0x7c,0xaf,
-0x28,0xf7,0xbe,0xeb,0x73,0xc9,0x3b,0x3d,0xa7,0x7a,0xfe,0x6f,0xab,0x4f,0x8d,0xea,
-0xe4,0xaa,0x60,0xdf,0x4b,0x9f,0x2b,0x37,0xfa,0xef,0xed,0xf4,0xc3,0xec,0x96,0x6f,
-0x2b,0xfb,0x6f,0xed,0x96,0x4b,0x37,0x1b,0xd7,0xf8,0x8d,0x6e,0xeb,0xfd,0x81,0x9a,
-0xd9,0x26,0xaa,0xf9,0xf9,0xea,0xf7,0x8f,0xec,0x36,0xcc,0x6b,0xfb,0xcd,0x7b,0xa6,
-0xdf,0xb8,0xbe,0x31,0xb9,0x80,0xe7,0x58,0x33,0x57,0x82,0xb1,0x1d,0x73,0xeb,0x66,
-0x0f,0xe5,0xb7,0x9d,0xb0,0x7b,0xda,0x4c,0xb8,0x6c,0x26,0x5c,0xae,0x20,0x4c,0xae,
-0xe0,0x95,0xa8,0x94,0x4f,0x64,0x7a,0x25,0x0f,0x9c,0x07,0x5d,0xce,0x82,0xb1,0x9d,
-0x9b,0xb6,0x70,0xbc,0xa3,0x9a,0x7c,0x6d,0x35,0xd5,0xe6,0xbc,0x63,0x8f,0x46,0xa3,
-0x63,0xd4,0x08,0xac,0x07,0x9d,0xf9,0xdb,0xc1,0x13,0xe7,0x73,0x92,0x70,0xd4,0xfb,
-0x14,0x8e,0xef,0xa5,0x2c,0x47,0x3f,0xdc,0x3e,0xea,0x77,0x87,0x1a,0x3a,0x0b,0xca,
-0x72,0x27,0x63,0x79,0x83,0x08,0x3c,0x17,0x5c,0x4d,0x02,0x68,0x74,0xde,0xd5,0xcc,
-0x73,0xae,0x16,0x0e,0xc2,0xeb,0x6a,0xf1,0xa2,0x27,0xee,0xa0,0x97,0x79,0xe3,0xbc,
-0xae,0x43,0x34,0xca,0x98,0x2e,0xf1,0xdc,0x37,0xd3,0xea,0xfb,0xfc,0xc1,0xc1,0xcf,
-0x2f,0x5d,0xb4,0x5c,0x82,0xdf,0x57,0x7d,0x8f,0xa6,0xbc,0x57,0x5e,0xca,0xbb,0x0d,
-0xf4,0xd6,0x0c,0xcc,0x3c,0x7a,0x6e,0xc6,0x3f,0x73,0xcc,0x0f,0xc1,0x66,0xb8,0x2b,
-0x1e,0xf7,0x93,0x7e,0xb6,0x33,0x95,0x7a,0xe3,0x66,0x4f,0x91,0xf3,0xb4,0x80,0x3b,
-0xd0,0x25,0x7f,0x3b,0xeb,0x57,0x53,0xe9,0x73,0x3d,0xd3,0x0d,0xf7,0xb1,0xb0,0xfc,
-0x10,0x7b,0xfd,0x90,0xd7,0x0d,0xd3,0x13,0x77,0xa7,0x5a,0xee,0x8a,0x33,0xed,0xe2,
-0x82,0xb7,0x9d,0x68,0x71,0xc2,0x73,0x5f,0x07,0xd1,0xe2,0xe7,0x64,0x8e,0x87,0x7c,
-0x1d,0xa1,0x90,0xef,0x5c,0x28,0xec,0x3b,0x17,0x0e,0x71,0xe4,0x9a,0x3b,0x4f,0x03,
-0xf5,0xb8,0x35,0x18,0xe4,0x3b,0x09,0xeb,0xe1,0xb4,0x06,0x31,0xe7,0xde,0x45,0x73,
-0xee,0x50,0x43,0x07,0x86,0x03,0xcb,0xc3,0x82,0x2d,0x1c,0xe5,0x6d,0x84,0xd9,0xd6,
-0x58,0x54,0xe8,0x8a,0xd2,0xda,0x39,0xe1,0x3a,0x8b,0xa8,0xd0,0x4d,0xee,0x23,0x2c,
-0x17,0xba,0x12,0x69,0xc1,0x9a,0xce,0xf2,0x9d,0xd9,0x94,0xd0,0x95,0x4a,0x89,0x24,
-0xc8,0x99,0x11,0x6c,0x99,0x65,0xbe,0x73,0x79,0x95,0x3f,0xbf,0x9a,0x72,0xb6,0xa5,
-0xe2,0xd3,0x67,0xe3,0x2b,0xbc,0x75,0x25,0x23,0x74,0x67,0xc0,0x17,0x07,0xfc,0x86,
-0x1e,0x74,0xd8,0xc9,0x92,0x9a,0x83,0x3e,0xf4,0x17,0x52,0x38,0xf7,0xf5,0x6a,0x02,
-0xf6,0xad,0xd1,0x99,0xaf,0x52,0x00,0xcb,0x81,0xe9,0xa0,0xd1,0xc1,0x0b,0x07,0xfb,
-0xcf,0x51,0x97,0x4b,0x35,0x73,0x96,0x73,0x67,0x3e,0xf7,0xc5,0x3e,0x29,0xef,0x8e,
-0x4c,0x8f,0xf9,0x5f,0x8c,0xbd,0xf9,0x8b,0xb3,0x6f,0x36,0x36,0xee,0x69,0x2c,0x7b,
-0x8c,0x0d,0x3e,0xde,0xbd,0xf7,0x93,0x77,0x13,0xf3,0xfd,0x09,0xda,0xa7,0x16,0xb8,
-0xbe,0xbc,0xbe,0xd0,0xb3,0x0e,0xde,0x76,0xc6,0x73,0x9a,0x7b,0x0f,0x12,0x96,0x07,
-0x60,0xce,0xeb,0xe0,0x32,0xe6,0xda,0x49,0x84,0x87,0xe4,0x3e,0x35,0xad,0xc7,0x5d,
-0xa9,0xa1,0x3f,0x0d,0x0f,0xd3,0x1e,0xf4,0x7c,0xa0,0x2f,0x9f,0x0f,0x5e,0xcf,0x63,
-0xce,0x7d,0x14,0x35,0x3a,0xe5,0xfa,0x08,0xd5,0xe9,0x1b,0x91,0xa1,0x8d,0x8d,0x30,
-0x89,0xc8,0xb0,0x74,0x8e,0x10,0x7e,0x23,0xd3,0xe1,0x1a,0xb8,0xbe,0x11,0x1d,0xdb,
-0xd8,0x88,0x8e,0xcb,0x5c,0x87,0xdb,0xc0,0xf2,0x52,0x78,0xb0,0x54,0x8c,0x8c,0x14,
-0x41,0xab,0xe7,0x63,0xe3,0x79,0xb8,0x06,0x96,0x6f,0x46,0x48,0x84,0x87,0x25,0xa6,
-0x0f,0x6d,0x01,0xcf,0x37,0x23,0xe4,0x76,0x94,0x30,0x3d,0x36,0x51,0x00,0x96,0xe7,
-0xe3,0x37,0xf3,0xc5,0xf8,0x44,0x71,0x33,0x3a,0xba,0x59,0x8a,0x8d,0x95,0x8a,0xf1,
-0x1b,0x84,0xeb,0x37,0x0b,0x90,0x7b,0x2f,0x24,0x6f,0x15,0x72,0xf1,0x9b,0xb9,0xdf,
-0xfe,0xeb,0xa5,0xdf,0xd6,0xd7,0x5b,0x76,0xcd,0xbb,0xb7,0x1e,0x86,0xfa,0x39,0xf6,
-0x9f,0xd3,0xfa,0xb9,0x3a,0xdf,0x9e,0x56,0xf9,0xe0,0xa4,0x1d,0x6b,0x94,0xed,0x74,
-0x56,0xdc,0x6d,0xc9,0xeb,0x3e,0x25,0xeb,0x71,0x9c,0x13,0xa7,0x63,0x7b,0x16,0xe2,
-0x0e,0xb9,0xbe,0xa3,0x30,0x5d,0xde,0x7f,0x7e,0x47,0xde,0xc1,0x92,0x5d,0xb8,0x99,
-0xbd,0x33,0x75,0xee,0x0e,0x11,0xdd,0x16,0x23,0x1d,0x26,0xff,0x8e,0x99,0x94,0x39,
-0x1f,0x6a,0xc6,0xeb,0x67,0xa3,0xab,0x39,0xae,0xe7,0x39,0xad,0x9f,0x87,0xd9,0xbc,
-0x57,0x36,0xdf,0x55,0xed,0x6f,0x7f,0x45,0xd9,0xbb,0xc6,0x76,0xaf,0x49,0xfe,0x38,
-0xa5,0x9e,0xae,0xae,0xaf,0x97,0xef,0x65,0x61,0xfb,0xd5,0x0e,0xb7,0xd4,0x1d,0x66,
-0xfd,0xb6,0xb4,0xbf,0x4e,0xd5,0x73,0x47,0x4f,0x8b,0xce,0x1b,0x60,0xd1,0x7a,0x87,
-0xe4,0xde,0x3b,0xf5,0x4c,0x19,0x03,0x16,0x6b,0x7e,0x57,0xf4,0x79,0x6c,0x93,0x96,
-0xf1,0x9a,0xdb,0x3b,0x30,0xb3,0x2c,0xd8,0xf7,0xd2,0xbf,0xa7,0xd8,0x8d,0xd7,0xea,
-0xf7,0x04,0x6a,0xbd,0xad,0x7f,0x7e,0x0d,0x72,0xfc,0x9a,0xd7,0xc1,0x0e,0xb5,0x70,
-0xa3,0xfc,0xc4,0x4e,0xf3,0xca,0xd4,0x7e,0x04,0xa3,0x9a,0xc5,0x1e,0x8b,0x69,0xcf,
-0xe4,0x4b,0xa6,0xc9,0x2f,0xfe,0x64,0xfa,0x82,0xb2,0x9b,0xe6,0xd5,0x4d,0xb3,0x90,
-0x63,0x87,0xd3,0x6b,0x37,0x79,0x31,0xcc,0x84,0xdf,0x26,0xc2,0x4f,0x33,0xe1,0x71,
-0x05,0x09,0xdd,0xe9,0xa8,0xa0,0x27,0x70,0xde,0x6b,0xaf,0x94,0x43,0xcf,0x6f,0xd4,
-0xeb,0x24,0x08,0xc3,0x41,0x9f,0x63,0x9e,0xbd,0x9a,0x67,0xfd,0x6a,0xe0,0x87,0xc3,
-0x93,0xf9,0xdc,0x6b,0xbc,0xd8,0xbb,0x56,0xeb,0x83,0x7e,0x35,0x38,0xbd,0xce,0x3a,
-0x79,0xef,0x39,0x9c,0xe0,0x6d,0xa7,0xbe,0x76,0xc2,0x75,0xce,0xc1,0x38,0xbe,0x8f,
-0x07,0x5f,0x9c,0xe8,0xdc,0x2f,0x62,0x34,0x88,0xa8,0xcb,0x15,0x6d,0x0e,0x1c,0x87,
-0xba,0x39,0xd4,0xd0,0xc1,0x13,0xe7,0x71,0xb5,0x78,0x3c,0xee,0x16,0x0f,0xe5,0xb9,
-0x1b,0xfc,0xed,0x07,0x7d,0xe8,0x73,0x47,0x6f,0xbb,0xcf,0x7d,0xd0,0x87,0x0c,0x47,
-0xa6,0x43,0xfd,0x9c,0xc6,0x4c,0x2b,0x39,0x5b,0x39,0xaf,0xb3,0xd5,0xfb,0xab,0x5f,
-0xec,0xfb,0x55,0x73,0xa3,0xb9,0x59,0xce,0xb7,0x55,0xe2,0x2c,0x19,0xda,0xfb,0x51,
-0xa5,0xd4,0xd1,0xae,0xf7,0xd6,0x5c,0x07,0x7d,0x0e,0xb9,0x76,0xf0,0xb8,0xe3,0xce,
-0xf3,0x13,0x22,0xf5,0xb7,0xcb,0xde,0x76,0x60,0xf8,0x29,0x41,0xe9,0x57,0x63,0x1c,
-0x3f,0xad,0xe5,0xb8,0x66,0x96,0xcc,0x4f,0xe8,0x5c,0x38,0x5a,0x47,0xf7,0xe2,0xfe,
-0x73,0x75,0xbf,0x1a,0xcb,0xeb,0xb0,0xf9,0x40,0xf2,0x4c,0x20,0xf2,0xf3,0x36,0xee,
-0xaf,0x6c,0xfc,0xe2,0xc1,0xe9,0x2f,0x16,0x7c,0xed,0x0b,0x0b,0xbe,0x73,0x0b,0xa0,
-0xcf,0x83,0xbe,0x73,0x41,0xe0,0x39,0x63,0x78,0xc4,0xd7,0x1e,0x89,0xf9,0xda,0x63,
-0x71,0x5f,0x5b,0x3c,0xee,0x6d,0x8f,0xc7,0x7c,0xe7,0x62,0x61,0xee,0x7c,0x98,0x72,
-0x9c,0x04,0xd5,0xe8,0xac,0x7e,0xce,0xb3,0xfa,0xb9,0xc4,0x71,0xbe,0x8b,0x70,0xdb,
-0x16,0x89,0x09,0xb6,0x58,0x94,0xb7,0x46,0x63,0xbc,0x2d,0xc6,0xf4,0x39,0xe4,0xdb,
-0xa3,0x62,0x77,0x14,0x58,0x1e,0x17,0x6c,0xf1,0x24,0x6f,0x4b,0xa6,0xf9,0x4e,0xc2,
-0xf2,0xf3,0xd9,0x8c,0x60,0xcd,0x80,0x46,0x07,0x9e,0xa7,0x85,0xae,0xf4,0x92,0x60,
-0x5d,0x5a,0xe2,0x3b,0x97,0x56,0xf8,0xce,0x95,0x55,0xbe,0x73,0xf5,0x29,0xdf,0xf9,
-0x74,0x45,0xb0,0xae,0x2c,0x09,0xdd,0x4b,0x38,0xff,0x15,0x59,0x0e,0x33,0xe1,0x20,
-0x70,0xc7,0x1a,0xcc,0x6b,0xbf,0x22,0xcd,0x7d,0x45,0x86,0xc7,0xe7,0x51,0x9b,0x63,
-0xed,0xfc,0x6a,0x32,0x3d,0xdf,0x43,0x34,0x79,0x4f,0x52,0x3b,0xef,0xf5,0x45,0x25,
-0xd7,0xbe,0x80,0xb5,0xf3,0xf4,0x62,0x6f,0x3a,0xbd,0xd8,0x97,0xc6,0xeb,0xeb,0x69,
-0xe7,0xa3,0x4b,0xce,0x8b,0x17,0x1b,0x2f,0xee,0x36,0xdf,0x1d,0x3e,0xc6,0xc6,0x8e,
-0x8e,0x05,0xb9,0xde,0x60,0x36,0x30,0x98,0x85,0xfd,0xe7,0x30,0x17,0x6e,0x75,0xb1,
-0x77,0x95,0xed,0x3f,0x67,0x35,0x74,0xb6,0x57,0x4d,0xae,0x9d,0xab,0x66,0xc3,0xe1,
-0x39,0xb2,0xbc,0x12,0x61,0xf5,0x73,0x9c,0xdd,0x0e,0xe7,0x5a,0x78,0x68,0x6d,0x23,
-0xd8,0xbf,0x01,0xfa,0x7c,0x23,0x3c,0xb8,0x01,0x3c,0x07,0x7d,0xce,0xf2,0xee,0xe0,
-0x6d,0x07,0x4f,0x3b,0x65,0x39,0x8d,0x11,0xe4,0x79,0x64,0x14,0xfd,0x6f,0xc0,0xf4,
-0xe8,0x28,0x61,0xfa,0x68,0x8e,0xea,0xf5,0x28,0xd1,0xeb,0x84,0xeb,0xa0,0xd9,0x0b,
-0x91,0x11,0xaa,0xcf,0x0b,0x51,0x88,0x91,0x02,0xf0,0x3c,0x17,0x9b,0xc8,0x15,0x62,
-0x63,0x85,0x52,0x64,0xa4,0x54,0x8a,0x0e,0x97,0xa0,0x96,0x0e,0xf9,0x76,0x08,0xe0,
-0xf9,0x66,0x74,0x84,0xb2,0xbb,0x14,0x07,0x7e,0xa3,0x2e,0x07,0x8e,0x97,0xe2,0xe3,
-0xa5,0xcd,0xd8,0xf8,0x26,0xf0,0xbd,0x98,0x78,0xa9,0x08,0x3c,0x87,0x00,0x46,0x5f,
-0xbc,0x70,0xf4,0xe2,0xee,0x3c,0x6f,0x56,0x78,0xce,0xea,0xe7,0x2a,0x1f,0x9c,0x32,
-0xbb,0x5d,0xbd,0x5f,0x0d,0x19,0x8f,0x1e,0xf6,0xa9,0x2d,0xb9,0x7e,0x9e,0x9e,0xd2,
-0xe8,0xf2,0xcd,0xac,0x5a,0xb3,0xdf,0x41,0xb6,0x67,0x90,0xef,0x4c,0x97,0xc3,0xf5,
-0x6a,0x78,0x72,0xf5,0xde,0x3f,0x5f,0xbc,0xd7,0xd8,0x58,0xd7,0xa8,0xd6,0x81,0x1a,
-0x86,0xe8,0xff,0xe6,0x6f,0xa3,0xd7,0xd4,0x9e,0x64,0x75,0x0e,0x5b,0xdd,0x07,0xc6,
-0xfc,0xed,0x6c,0x1f,0x4b,0xd9,0x1e,0x96,0x25,0xd6,0x6b,0xae,0xcc,0x8d,0x51,0xe6,
-0xbe,0x4a,0xfb,0xce,0x25,0x86,0xd3,0x9e,0xf3,0xac,0x32,0xb7,0xfd,0x7f,0x97,0x70,
-0xa6,0x8c,0xb2,0x8f,0x45,0xd9,0x97,0xaa,0xdf,0x4b,0xa1,0xd7,0x26,0x2c,0xe4,0x5d,
-0x15,0x92,0x66,0x57,0xd7,0x17,0xf4,0xbd,0xeb,0xfa,0xfe,0x75,0x3d,0x0b,0x77,0x7b,
-0xfe,0x95,0x87,0xba,0xbc,0xce,0xad,0xc9,0x73,0x6f,0x97,0xfb,0x37,0x29,0x5f,0xaf,
-0xff,0xa6,0x9a,0x9b,0xdb,0xd4,0xd6,0xcb,0xbe,0xe7,0x0e,0x0c,0xdf,0x2e,0x6f,0xae,
-0xe9,0xc5,0xd3,0xf9,0x0b,0xca,0x66,0xc2,0xa8,0x5f,0x0b,0xaa,0xd7,0x0c,0xfb,0x1b,
-0xce,0x66,0x6e,0x1d,0x3b,0x62,0x3a,0x76,0xef,0x2d,0xd3,0x3d,0xf7,0x23,0x93,0xdb,
-0x63,0x37,0x79,0x68,0x4c,0x4b,0x61,0x57,0x4e,0xe0,0x39,0xd5,0xe6,0xd3,0x52,0x48,
-0x1a,0x9d,0xfa,0xe0,0xa6,0x2b,0x3c,0xa8,0xdb,0x2b,0x3c,0x8c,0xe7,0xa8,0xc7,0x2b,
-0x30,0xf7,0xae,0xca,0xbb,0x0b,0xf6,0x6a,0x81,0x31,0x1d,0xfa,0xd4,0xa0,0x7e,0x0e,
-0xf9,0x77,0xf0,0xb7,0xd3,0x19,0xee,0xd4,0xeb,0x5e,0xe3,0x45,0x8e,0x13,0x9e,0x93,
-0x6b,0xec,0x53,0xab,0xe5,0xd8,0x09,0xda,0x1c,0x66,0xb8,0x43,0xaf,0x1a,0xea,0xf3,
-0x7a,0x1f,0xf5,0xb8,0x3b,0xf7,0x72,0xb4,0x7e,0xee,0x60,0x2c,0xdf,0x27,0x8a,0x0e,
-0x12,0xe4,0x14,0x9c,0xfb,0x05,0xde,0xd9,0xc0,0x43,0x40,0xed,0x1c,0x82,0x79,0xdb,
-0x51,0x8f,0x43,0x34,0x7b,0xd9,0x6d,0x96,0x6f,0xa7,0x0c,0x77,0x49,0xf5,0x73,0x97,
-0xba,0x6e,0x7e,0x88,0xf2,0x9c,0x71,0x9d,0x77,0xb7,0xf2,0xc0,0xf5,0x87,0xff,0x73,
-0xe0,0x61,0xdb,0x99,0xaa,0x36,0x7d,0x9d,0x8c,0xbe,0x5f,0x55,0xe5,0xd9,0xfa,0xae,
-0xd5,0xf4,0xb9,0xbf,0x3a,0xea,0x66,0xfd,0x6a,0xcc,0xe3,0x2e,0xce,0x1e,0x97,0xfd,
-0xed,0xac,0xff,0x9c,0xe9,0x73,0x1a,0x72,0xae,0x5d,0xaa,0x9f,0x53,0x9e,0x9f,0xd1,
-0xe8,0x73,0x56,0x3b,0x07,0xb6,0x03,0xcf,0x61,0xbf,0x9a,0xfe,0x6f,0x87,0xfa,0xfd,
-0x3f,0x7b,0x3d,0x0d,0xf4,0x37,0x0c,0x88,0x33,0x6d,0xe2,0xa2,0xaf,0x7d,0x31,0xe0,
-0x6d,0x0f,0x84,0xbc,0xed,0xa1,0xb0,0xb7,0x8d,0x30,0xbc,0x2d,0x12,0xf5,0x9e,0x8d,
-0xc6,0xbd,0x67,0xe3,0x10,0x31,0x6f,0x5b,0x2c,0xe6,0x6d,0x8f,0x45,0xbd,0xed,0xd1,
-0x30,0xd7,0x11,0x86,0xdc,0x3b,0xe4,0xd9,0x81,0xe5,0xb2,0x27,0x4e,0x0a,0x5a,0x33,
-0x27,0x11,0xe6,0xad,0xe1,0x08,0x6f,0x8d,0x80,0x27,0x0e,0xb4,0x39,0x70,0x1d,0x18,
-0x4f,0x35,0xb9,0xd8,0x45,0x35,0x79,0x82,0xef,0x4a,0x24,0x79,0x6b,0x32,0xc5,0x77,
-0x12,0x6e,0x77,0xa6,0xd3,0xbc,0x35,0x9d,0x14,0x6c,0x34,0xcf,0x9e,0x14,0xba,0x93,
-0x4c,0x9b,0x67,0x05,0x6b,0x36,0xcb,0xdb,0xb2,0xc0,0x75,0x60,0xfa,0x3a,0xdf,0xb1,
-0x0e,0xb5,0x73,0xf0,0xb8,0xa7,0xfc,0x17,0x53,0x89,0xb9,0x4b,0x09,0xe0,0xb8,0xb2,
-0x2f,0xf5,0x2a,0xee,0x4c,0x05,0x7d,0x2e,0xef,0x64,0x01,0xae,0xf7,0xc8,0xfb,0xd0,
-0xa9,0x47,0x6e,0x5e,0x9a,0xe1,0x2e,0xf9,0xdb,0xe5,0xdd,0x2c,0xaa,0x9e,0x35,0xf4,
-0xc3,0xf5,0xca,0x35,0x74,0x38,0xa3,0x73,0x2f,0x46,0xdf,0x78,0xfd,0xf4,0x1b,0xf5,
-0x75,0xd5,0xbb,0xea,0x4a,0xf0,0xc4,0xcd,0x7e,0x7d,0x65,0x16,0xf4,0xf9,0x4a,0xa0,
-0x77,0x65,0x6d,0xe1,0xda,0xda,0xca,0xe2,0xf5,0x15,0x5a,0x4b,0xa7,0x3b,0xd0,0x07,
-0x69,0xee,0x5d,0xde,0x7b,0x2e,0xed,0x4d,0x55,0x98,0xce,0xf6,0xa6,0x8e,0xc8,0x33,
-0x5f,0x61,0x2f,0x0b,0xe4,0xda,0x71,0x67,0x2a,0xe6,0xdd,0xd9,0xac,0x38,0xe8,0x55,
-0x7b,0x1a,0x26,0x1a,0x3d,0x3a,0xb6,0x8a,0x3d,0x6a,0xc8,0xf4,0xb5,0xc8,0xc8,0x1a,
-0xf8,0xdc,0xb1,0x7e,0x3e,0x42,0x75,0xb9,0xd2,0xb3,0x36,0xb6,0x06,0xde,0xb8,0x52,
-0xa8,0xbf,0x04,0x81,0x39,0x78,0x60,0xfa,0xf8,0x06,0xf8,0xe1,0x94,0x18,0xcb,0x63,
-0xdf,0xda,0x04,0xed,0x5d,0x03,0xae,0x03,0xe7,0x81,0xe9,0xc8,0xf5,0xd1,0x12,0xe4,
-0xdc,0xd9,0xc9,0xd8,0x8e,0xba,0x1c,0xb8,0x3e,0x41,0xb9,0x8e,0x4c,0x27,0x9f,0x03,
-0x8f,0x5c,0xe2,0x66,0xfe,0xdd,0x77,0x2e,0xbc,0xbb,0x5b,0xfd,0x42,0xce,0xb7,0xab,
-0xbc,0x70,0x65,0x7b,0x53,0x55,0x1e,0x77,0x85,0xed,0x8a,0x3e,0x87,0x39,0xaf,0xda,
-0xd3,0x40,0xa7,0x4b,0x4c,0xd7,0xd4,0xcc,0x09,0xd3,0x73,0xf1,0xdb,0xb9,0x4f,0xfe,
-0xe3,0xda,0x27,0xa7,0x4e,0x35,0x9d,0x32,0x9b,0x77,0xa9,0xb5,0xe8,0x58,0xa0,0x61,
-0x8f,0x41,0x8e,0x59,0xfe,0x5d,0xad,0xd0,0x06,0xf8,0xe1,0x60,0x9e,0x8c,0xc2,0xf3,
-0xbb,0xda,0xde,0x73,0xdd,0x7e,0x35,0xf4,0xc1,0xdf,0xfd,0x2b,0xf6,0xae,0xa9,0x4f,
-0x69,0xff,0x39,0xec,0x65,0xc9,0x80,0x17,0xee,0xd6,0x0f,0x7f,0xcf,0xdc,0xfa,0x3b,
-0xd4,0xd1,0xa9,0x1f,0xee,0x6d,0xc9,0x0f,0x27,0xf9,0xf1,0x2d,0xd5,0xca,0xdf,0x2e,
-0x7d,0x4e,0x41,0xed,0x15,0x90,0xf7,0x74,0x54,0x99,0xca,0xe6,0x7c,0x97,0xed,0xb6,
-0xd0,0xe5,0x25,0x0c,0x73,0xe9,0x3b,0xd5,0xb8,0xcb,0x1e,0xde,0x9d,0x3f,0xf4,0x8f,
-0xb7,0xfc,0xef,0x54,0xff,0x52,0xf3,0x5e,0xc2,0xac,0xfd,0x5a,0xf5,0xf7,0x29,0xcb,
-0xaf,0x1b,0xe4,0x03,0x8c,0xf8,0xbd,0x53,0xdd,0x60,0xbb,0x1a,0x39,0xe3,0xbc,0xba,
-0x46,0xce,0xd8,0x2d,0xef,0xfc,0x22,0xcf,0x53,0x5d,0x35,0xe6,0x4a,0x2e,0x5f,0x30,
-0x5d,0xbe,0xff,0xb1,0xe9,0x3e,0xd5,0xe4,0x92,0x2e,0x07,0x7e,0xd3,0xda,0xf8,0xb4,
-0x69,0x56,0x9b,0x63,0x37,0x7b,0x59,0x80,0x2e,0x87,0x3c,0x3b,0xd5,0xe4,0xd3,0xc0,
-0x70,0xa8,0x9d,0x93,0x6b,0xa8,0xa1,0x4b,0x5a,0x5d,0xcd,0x71,0xcc,0xbd,0xb3,0xfa,
-0x79,0x95,0x4f,0xee,0x43,0x77,0x28,0xbd,0x6a,0x50,0x43,0xc7,0x3e,0x35,0x0b,0xce,
-0x85,0xa3,0x73,0x64,0x20,0xcf,0xce,0x66,0xc2,0x61,0xcf,0x9a,0x3c,0x43,0xc6,0xc9,
-0xfa,0xd4,0xea,0x79,0x98,0x0d,0x07,0x3e,0x38,0xde,0x41,0x82,0x68,0x73,0x60,0x3a,
-0x3d,0x69,0xae,0x1d,0x39,0x8e,0xfd,0x6a,0x2c,0x9a,0x7c,0x1e,0x57,0x93,0xc7,0xe3,
-0x6a,0xf6,0x30,0x96,0xd3,0x3e,0x35,0x37,0xf6,0xab,0x41,0xde,0x9d,0x77,0xb7,0xf0,
-0xbc,0xfb,0x00,0x4f,0x7b,0xd0,0x09,0xd7,0x99,0x1f,0xce,0xe7,0x42,0x9e,0xf3,0xee,
-0xc3,0x3c,0xb2,0xfc,0x30,0x0f,0x3c,0xe7,0x67,0x5a,0xf9,0x99,0x6f,0x0e,0xcf,0x8c,
-0x0c,0xd6,0x8e,0x80,0xaf,0xd5,0xa8,0x57,0x83,0xfd,0x4e,0xf4,0xbd,0x58,0xd3,0xe7,
-0x7a,0x74,0xd4,0x25,0xcc,0x1c,0x13,0xa0,0xef,0x9c,0x79,0xdb,0x71,0xcf,0xda,0x89,
-0x39,0xbc,0x3e,0xe9,0x67,0x3a,0x5d,0xd6,0xe7,0x72,0x3c,0x8f,0x5c,0x37,0xc8,0xb5,
-0xb3,0x93,0xf5,0xab,0x1d,0x68,0xa9,0x3a,0x60,0xe8,0x35,0x51,0xd5,0xf6,0xe1,0x77,
-0xed,0x83,0x5f,0xb7,0x7e,0x10,0xf0,0xb5,0x11,0x2d,0xde,0x16,0x02,0x7e,0x27,0x3c,
-0x67,0x12,0xe9,0xd9,0xe7,0xd3,0x69,0xcf,0xf3,0xe9,0xa4,0xe7,0x4c,0x32,0xe1,0x3d,
-0x9b,0x00,0x7d,0x0e,0x39,0xf7,0x20,0x87,0x35,0xf4,0x00,0xdf,0x49,0x6b,0xe6,0xe0,
-0x73,0x67,0x35,0x74,0xf4,0xb5,0x5b,0x83,0xc8,0x72,0x2b,0x65,0x79,0x58,0x20,0xc1,
-0xdb,0x68,0xae,0x9d,0x6a,0x75,0xb1,0x0b,0x7d,0x70,0x42,0x57,0x04,0x74,0x7a,0x82,
-0xb7,0x26,0x80,0xe3,0x29,0x8e,0x84,0x60,0x4b,0x41,0xae,0x3d,0x2e,0x76,0xc7,0xe3,
-0x42,0x77,0x9c,0xf1,0x1c,0xb4,0x39,0x44,0x46,0xe8,0x22,0x4c,0xb7,0x65,0x31,0xe7,
-0x0e,0xfa,0xfc,0xfc,0x53,0xf0,0xb8,0x83,0xe7,0x0d,0x76,0xb2,0x00,0xcf,0x61,0xde,
-0x2b,0x68,0x74,0xe0,0x78,0x6c,0xfe,0x6a,0x0c,0x38,0x0e,0x75,0x73,0x39,0xcf,0x4e,
-0x58,0x9e,0x9a,0xbb,0x92,0xca,0xce,0x5d,0xca,0x66,0xe6,0xaf,0x64,0xd0,0xef,0xce,
-0x76,0x9f,0x5f,0xd3,0x68,0x73,0x39,0xdf,0x2e,0x79,0xdb,0x91,0xe7,0xbd,0x29,0xd0,
-0xe8,0xe9,0x00,0xc6,0xfd,0x4f,0x6c,0xf7,0x8f,0xb4,0xd6,0x6c,0xeb,0x87,0x64,0x1f,
-0xe4,0xc9,0xaf,0xfe,0xe8,0xdf,0xce,0x7f,0x94,0x0d,0xf6,0x67,0x57,0x16,0xfb,0x56,
-0x68,0xae,0x3d,0x30,0xb0,0x4c,0x59,0x1e,0x42,0x6d,0x0e,0x81,0xb7,0x99,0x1f,0x6e,
-0x70,0x05,0x76,0xb2,0xac,0x05,0xfa,0xd7,0x60,0x1e,0x9c,0xc2,0xf3,0x11,0xca,0xf3,
-0x7c,0xa0,0x37,0x0f,0x35,0x73,0xc6,0x74,0xc8,0xb3,0xaf,0x87,0x86,0xd6,0x29,0xcf,
-0xa1,0x86,0x1e,0x41,0x8e,0xc3,0x09,0xac,0x86,0x1e,0xb5,0xb5,0x28,0xf0,0x1c,0x59,
-0xbe,0x1e,0x1d,0x25,0x3c,0x1f,0xdd,0x00,0x5d,0x8e,0xf7,0x8f,0xaf,0x81,0x36,0x2f,
-0x85,0xae,0x97,0xb6,0x82,0xd7,0xb7,0x4a,0xa1,0x81,0x12,0xf8,0xe0,0x36,0x62,0x13,
-0xd8,0x77,0x1e,0x1d,0x23,0xba,0x7d,0x3c,0x0f,0x75,0x74,0x60,0x3a,0x78,0xdb,0x99,
-0xa7,0x1d,0x34,0x3b,0xf8,0xe2,0x40,0x9b,0xd3,0x9c,0x3b,0x61,0x38,0xd4,0xcb,0x8b,
-0xb1,0xb1,0x22,0xd3,0xe9,0xb4,0x86,0x2e,0x31,0xbc,0x14,0x9f,0x28,0x61,0xdc,0x28,
-0x81,0x4e,0x2f,0x26,0x6e,0x16,0x05,0xf7,0x80,0x50,0x57,0xbb,0xa7,0x6e,0xa7,0xc7,
-0x11,0xf5,0xf9,0x44,0x9a,0xd6,0xce,0x53,0x93,0x25,0x0d,0xc7,0xcb,0x74,0xba,0xd4,
-0xa3,0x96,0x51,0x05,0xeb,0x3f,0x67,0x61,0x58,0x43,0x97,0x72,0xed,0xb2,0xcf,0x1d,
-0xf3,0xef,0xc5,0xe4,0x54,0x71,0xfa,0xe1,0xe0,0xf4,0x95,0xcb,0xcf,0x5d,0xa9,0x84,
-0x0c,0xe8,0x6e,0x2c,0x51,0x31,0x61,0x5b,0xae,0xe8,0xbe,0x5e,0x1d,0xec,0x6f,0x3e,
-0xd5,0xe7,0xe1,0x29,0xd5,0x3e,0x16,0xdd,0xde,0x54,0xc6,0xf5,0x25,0x9c,0xff,0x86,
-0xbd,0xe7,0x98,0x77,0xa7,0x39,0x75,0x36,0xa7,0x5d,0xee,0x41,0xbf,0xfb,0x3d,0xee,
-0x59,0x9b,0xfc,0xe1,0x87,0xf4,0x2d,0x12,0x93,0x3f,0xc0,0x6c,0x9c,0x0f,0xdf,0xb9,
-0xf0,0xe1,0x99,0xa3,0x75,0x67,0x60,0x06,0x16,0xcc,0xb4,0x64,0x7d,0xf4,0x72,0x3e,
-0xbd,0x52,0x9b,0x4b,0x37,0x9a,0xe3,0xba,0xdd,0x5e,0x0f,0xfd,0xb5,0x7e,0x97,0xfa,
-0x76,0x7c,0xd7,0xe4,0xe8,0xcd,0x5a,0xb6,0xea,0x73,0xf3,0xbb,0x3d,0x1f,0xba,0x27,
-0xc6,0xf8,0xb1,0x37,0xca,0xad,0x9b,0xb4,0xac,0xd6,0x73,0x58,0xcf,0x71,0x23,0xc6,
-0xef,0xc4,0x79,0xf5,0x4e,0x14,0xcd,0xcc,0x74,0xb5,0xaf,0x52,0xca,0x8b,0xa8,0x3d,
-0x96,0x6c,0x56,0x51,0xed,0x1e,0x53,0xed,0x70,0xbf,0x69,0xf8,0xcb,0x3f,0x9b,0xbe,
-0x64,0x3e,0x76,0xaa,0xc7,0x1d,0x4c,0x97,0x9b,0x3d,0xc0,0x6d,0xc8,0xb7,0x23,0xbf,
-0xcd,0x1c,0xe3,0x38,0x8d,0x69,0xbc,0x8d,0x7c,0xc7,0x5c,0x3b,0xe6,0xe0,0xb5,0xda,
-0x9c,0x05,0x70,0x1c,0x72,0xef,0x38,0x4b,0xa6,0xca,0x8b,0xbe,0x38,0x0b,0x27,0xd7,
-0xce,0x21,0xf7,0xee,0x90,0x82,0xe6,0xe1,0xf7,0x90,0x80,0xde,0xf3,0x1a,0x41,0x74,
-0xd4,0x62,0xdf,0x1a,0x09,0xd1,0x51,0x27,0xd2,0x19,0xee,0x4e,0x3c,0xd9,0x4e,0x16,
-0x9c,0x25,0x03,0x79,0xf7,0x7d,0x52,0xec,0x57,0x45,0x83,0x14,0xc8,0x73,0xd6,0xaf,
-0x26,0xf7,0x9e,0xd3,0xbe,0xb5,0x16,0x3a,0x53,0x06,0xbc,0xed,0xff,0xc7,0xda,0x95,
-0x3f,0xb5,0x75,0x9e,0xeb,0xc3,0xbe,0x98,0x4d,0x66,0x0b,0xb6,0x31,0x60,0xe2,0x38,
-0x20,0x1b,0x6c,0x0c,0x18,0x03,0xc6,0x6c,0xc6,0x0e,0xde,0x12,0x37,0x9e,0xc9,0xb4,
-0xb7,0x69,0xc7,0xe9,0xb4,0x3f,0x74,0x6e,0xda,0x24,0x75,0x73,0x33,0x19,0x67,0x26,
-0x3f,0xdc,0xb9,0xd3,0x66,0xee,0x34,0x4d,0x73,0x7d,0x6f,0x9b,0xa4,0x29,0x08,0x19,
-0x04,0x48,0x02,0x09,0x21,0x40,0xbb,0x58,0x6c,0x8c,0xd9,0xb4,0x80,0xdd,0xbf,0xa6,
-0xe7,0x79,0xbf,0xf3,0x9d,0xf3,0xe9,0x20,0x6c,0xdf,0x99,0x68,0xfa,0xcd,0x41,0xd8,
-0x64,0x5c,0x10,0xe7,0xd1,0xf3,0xbe,0xcf,0xc2,0x4e,0x09,0x1d,0x6d,0xde,0x0e,0x4e,
-0xce,0xf4,0xed,0x56,0x33,0xe6,0xec,0xe5,0x34,0x67,0x07,0x8e,0xf3,0x99,0xbb,0xd5,
-0xfc,0x8a,0xf5,0xe7,0xef,0xe6,0xff,0x3c,0x37,0x27,0x25,0x37,0x41,0xbb,0xc0,0xfd,
-0x98,0xca,0xe7,0x38,0x9e,0xd3,0xac,0x7d,0xf4,0xc8,0x14,0xf6,0xe7,0xac,0x27,0x15,
-0xdd,0x6a,0x95,0x0e,0x8d,0x9f,0xf3,0x4c,0x19,0x96,0xf1,0xca,0x0f,0xf4,0xed,0x53,
-0xe3,0x32,0xa6,0xcb,0x07,0x78,0xae,0xe2,0x38,0xcd,0xd9,0x79,0xe6,0xab,0x8c,0xe7,
-0x77,0x65,0x3c,0x2f,0x49,0x2f,0xd1,0xbf,0x06,0x55,0x1c,0xc7,0x6e,0x5f,0x7e,0x2d,
-0x14,0x17,0xa6,0x16,0xdf,0xff,0xe3,0x91,0xfb,0xde,0x89,0x57,0xbd,0xfe,0xf1,0x5a,
-0x7f,0xd8,0x52,0x13,0x5e,0xb6,0xd4,0x2c,0xaf,0x8c,0x55,0xaf,0x2c,0x8e,0xd7,0x2c,
-0x82,0x97,0x63,0xde,0xee,0x9e,0x84,0x26,0xae,0x9e,0x0e,0xe3,0xe5,0x32,0x9e,0x03,
-0xd3,0xc5,0xfd,0x39,0x61,0xf9,0xc9,0x79,0xce,0xcd,0x99,0xae,0x1d,0x57,0x4d,0xdb,
-0x0e,0x1c,0xf7,0xda,0x1a,0x68,0xb6,0x0e,0x2c,0xc7,0x01,0x17,0x87,0x9e,0xdd,0x37,
-0xd5,0xe0,0xc3,0xfe,0x1c,0x58,0x1e,0x98,0x92,0x39,0xbb,0xbd,0x91,0xf0,0x9c,0x66,
-0xee,0x02,0x47,0x07,0x9e,0x43,0x03,0x87,0x9d,0x39,0xeb,0x58,0x3b,0x1b,0x00,0x96,
-0xb3,0x9c,0xb8,0xc6,0x65,0xbe,0x37,0x07,0x9e,0x13,0xa6,0xcf,0xb0,0xae,0x54,0x15,
-0xcb,0xa7,0xcf,0x2e,0x2d,0x39,0x9a,0x96,0xa0,0x67,0x17,0xbb,0x52,0x13,0x79,0xb9,
-0xa2,0x89,0x73,0xb5,0x69,0x33,0x77,0x61,0x7f,0xce,0xcf,0xf4,0x68,0xeb,0xf4,0x29,
-0x63,0xd1,0xa9,0x97,0xd1,0x72,0xf5,0xf6,0x1d,0xee,0x0d,0x38,0x3b,0x02,0xc8,0x82,
-0x53,0xb9,0xf9,0xdc,0x45,0xf2,0xa1,0xaf,0xb9,0xce,0x93,0x57,0x8d,0xf1,0xf4,0x8b,
-0x2b,0xc8,0x86,0x43,0x9e,0x0c,0xce,0xba,0xfb,0xfc,0x3a,0xb8,0x38,0xcb,0x6f,0xef,
-0x51,0xf7,0xe6,0x1b,0xb3,0xed,0x1b,0xd1,0x99,0xe6,0xe8,0xfa,0x5c,0xc7,0x3a,0xcf,
-0x91,0x21,0x4c,0x5f,0xe8,0x5e,0xc3,0xfc,0x9d,0xcf,0xd9,0xd9,0x1e,0x5d,0xc6,0x74,
-0x8f,0x8c,0xd9,0xf2,0xc1,0x8c,0x9d,0xe6,0xed,0x32,0x8e,0x03,0xd3,0xd7,0x3c,0x6c,
-0x87,0x8e,0x5d,0x3a,0x3e,0xb7,0xe9,0xe9,0xde,0xdc,0x5a,0xe8,0xda,0x02,0x9e,0xe3,
-0x63,0xe0,0x38,0x30,0x9d,0xe3,0x3a,0xb0,0x9b,0xe1,0xfa,0xc0,0x86,0xe8,0x57,0xdb,
-0xf4,0x5d,0xda,0x8c,0x7a,0x2e,0x46,0x77,0xe7,0xda,0x77,0xe3,0xf3,0x9d,0x71,0xda,
-0xa3,0xcb,0x38,0xbe,0xe9,0xbf,0xb4,0x89,0x99,0x3b,0xf0,0x1c,0xcf,0x31,0x6f,0x07,
-0xde,0x47,0x7d,0x7d,0xd1,0x88,0x7f,0x20,0x02,0x4c,0xc7,0x59,0x72,0xf5,0x2f,0x1d,
-0xab,0x29,0x3d,0xb6,0x67,0xdf,0x29,0x3c,0x34,0x7d,0xfb,0xd5,0xed,0xad,0x90,0x6e,
-0x7f,0x1e,0xba,0xae,0xe4,0xb7,0x6b,0x59,0x71,0x8c,0x97,0xdf,0x10,0x72,0x65,0x98,
-0x86,0x5d,0xdc,0x9f,0xb3,0x2b,0xbc,0x69,0xd7,0x63,0x89,0x38,0xae,0xed,0xd3,0xf1,
-0xf7,0xa7,0x46,0xfa,0xa7,0x06,0x2f,0xd7,0x0e,0x66,0x67,0x67,0xbe,0x94,0xaf,0x21,
-0x29,0x94,0xe8,0xfe,0xbf,0x25,0x9b,0x35,0x27,0xcc,0x79,0x53,0x94,0x3e,0x16,0xca,
-0x7b,0x55,0x72,0x5e,0xa9,0x97,0x45,0xe1,0xdd,0x7c,0x77,0xbe,0xc2,0xba,0xd5,0xf8,
-0xe7,0xa9,0x6f,0x8d,0x3a,0x52,0x6f,0xa8,0x3e,0x73,0x31,0x8b,0x86,0x32,0x5f,0x89,
-0xa7,0xb3,0x4e,0x74,0xf0,0xf3,0xcf,0x7e,0x7b,0xe6,0xb3,0xda,0xc3,0x39,0xb5,0xa5,
-0x79,0x52,0x69,0x49,0x9e,0x54,0x82,0x8c,0x6a,0x43,0xae,0x64,0x80,0x2e,0x0e,0x9a,
-0x38,0xbd,0xd6,0x7d,0xbf,0x7c,0x76,0x7d,0xee,0xa8,0x7e,0x9f,0xa0,0xf7,0xaa,0xef,
-0x97,0x03,0x9b,0x90,0x13,0xa7,0xc3,0x4e,0x91,0x2f,0x6b,0x10,0xfd,0xb2,0x3f,0x84,
-0x84,0x0f,0xf7,0x7c,0x5d,0x32,0x2c,0xde,0xb3,0x2f,0x7f,0xc1,0xee,0x9e,0xfe,0xbd,
-0x49,0x7a,0xce,0x54,0x8d,0xa4,0xd0,0x2f,0xbf,0xa7,0x8b,0x33,0x7d,0x6f,0xee,0x10,
-0xbd,0x97,0x12,0xf2,0x7b,0xc4,0x6e,0xee,0x82,0x03,0x52,0xc1,0xcd,0x41,0xe9,0xe6,
-0xf0,0x37,0xd2,0xb0,0x3a,0x63,0x1f,0x02,0x0f,0x97,0x68,0x57,0x4e,0x7b,0xf3,0x21,
-0x1c,0x8d,0x97,0xd3,0x11,0x9e,0x73,0xdf,0x39,0x9f,0xbd,0x8b,0xf3,0x76,0x6d,0xd6,
-0xce,0x75,0x71,0xe2,0x9c,0x9d,0xeb,0xdb,0x19,0x9e,0x27,0x62,0x79,0x96,0x8d,0xf4,
-0x70,0x84,0xe3,0xd9,0x53,0x38,0xcc,0x7f,0x0e,0x2c,0xcf,0x99,0xe2,0x9d,0x2c,0xe0,
-0xe5,0x84,0xe3,0xc8,0x86,0x53,0x73,0xe2,0xf2,0x27,0x59,0x26,0x1c,0xcb,0x7c,0x55,
-0xf3,0xe1,0xcc,0xcc,0xab,0xc6,0xfc,0x6a,0x86,0x49,0x7e,0xb5,0x8e,0x18,0x14,0x0c,
-0x3f,0x28,0x73,0x78,0xf9,0xc8,0x57,0xf8,0xcf,0xa1,0x71,0xb7,0x8f,0x94,0xd8,0x29,
-0x4f,0x06,0x9e,0x35,0x01,0xcf,0xf5,0xfb,0x73,0xe2,0xe6,0xf2,0xb1,0x3f,0x28,0xb7,
-0xe3,0x7a,0xef,0x3f,0x8a,0xee,0x15,0xe4,0xa7,0x16,0x70,0xcc,0xe4,0xaf,0x69,0xfe,
-0x33,0x41,0xb6,0x3b,0xe9,0xdb,0xbf,0x3b,0xf4,0x00,0xda,0x76,0xcd,0xaf,0xa6,0x75,
-0xa6,0x62,0x97,0x8e,0x5c,0x38,0xc7,0x58,0x95,0x83,0x8e,0xa5,0xca,0xb1,0x97,0xa3,
-0xd7,0x30,0x3c,0xe7,0xf9,0xed,0xc2,0x0e,0x9d,0x7b,0xd0,0x69,0xde,0x5e,0x9c,0xa6,
-0xce,0xdb,0xd5,0xf7,0x7f,0xf2,0x6b,0x02,0xaf,0x01,0xbc,0xf7,0x3e,0x98,0x2b,0x1d,
-0x6c,0x3c,0x9e,0xd1,0xf8,0xe0,0x2f,0x95,0x0f,0x42,0x96,0x9a,0x50,0xd8,0x52,0x1d,
-0x5e,0xb2,0x54,0x2f,0x2d,0x5a,0x6a,0x16,0x83,0x96,0xda,0x20,0xb8,0xfa,0xfc,0xe4,
-0x89,0x79,0xe8,0xe1,0x80,0xe7,0x2a,0x37,0x27,0x5c,0x37,0x2a,0x47,0xc1,0x73,0x45,
-0x0b,0x37,0x6f,0xd5,0xf0,0x9c,0xe5,0xc2,0x9d,0x52,0xf6,0xe8,0x8a,0x16,0xce,0x76,
-0xd2,0x87,0xe3,0xb7,0x9d,0xf4,0xe3,0xf8,0xec,0x0d,0x3e,0xcc,0xdc,0xb1,0x43,0xe7,
-0x58,0x0e,0x6c,0xf7,0x4f,0xe1,0x9c,0x26,0xcf,0x5a,0xc8,0xde,0x18,0x0a,0xdb,0x4f,
-0x85,0x19,0x9e,0x37,0x2c,0x85,0xa7,0x1a,0xc2,0xe8,0x3e,0xf7,0x3b,0x9a,0xfc,0x38,
-0xe0,0xe4,0xc0,0x71,0xf8,0xd5,0xa0,0x71,0x0f,0x4e,0x37,0xab,0xfc,0x5c,0xe5,0xe8,
-0xce,0xd6,0x40,0xd8,0x71,0x36,0x8c,0x5c,0x99,0x65,0xc7,0x99,0x65,0xb1,0x5f,0x8d,
-0x78,0x39,0xe5,0xb7,0x9f,0x0b,0x81,0xa7,0xa3,0x9b,0x05,0x58,0xbe,0xe8,0x6a,0x5b,
-0x5c,0x9c,0x69,0x5b,0x64,0x5c,0xbd,0x23,0x28,0xfa,0xd6,0xf8,0x1e,0x7d,0xc1,0x7e,
-0x7e,0xa1,0xa7,0xfb,0x50,0x8f,0x7c,0x33,0x7a,0x61,0x36,0x79,0x61,0x61,0x76,0xe1,
-0xf0,0x37,0x4d,0xc3,0xd8,0x9f,0x73,0x9f,0x1a,0xe1,0xb9,0x3b,0x11,0xcf,0xa1,0x75,
-0xdf,0x70,0xb5,0x6d,0x3c,0x99,0x65,0x99,0xaf,0xeb,0xb3,0xe7,0xd7,0xf5,0x59,0x71,
-0xe0,0xe7,0xe4,0x53,0x9b,0x69,0x8e,0x80,0xa7,0xa3,0x97,0x85,0x30,0x7d,0x81,0x63,
-0x7a,0xcf,0x1a,0xe6,0xed,0x4c,0x17,0xd7,0xff,0x88,0x69,0xdd,0x19,0xa6,0x53,0x36,
-0xdc,0x42,0xf7,0x3a,0xb8,0x39,0xf0,0x9e,0xeb,0xdc,0x39,0x96,0xaf,0x7b,0xb1,0x3f,
-0xef,0xd9,0xd8,0x5a,0xb8,0xb8,0xb5,0xb5,0xd0,0xbd,0x85,0xfd,0x39,0x61,0xba,0x5f,
-0xc1,0x74,0xff,0x00,0xcd,0xda,0x09,0xd7,0x15,0x8e,0x4e,0xcf,0xe5,0xeb,0xb6,0xa7,
-0x67,0x7b,0xd7,0xdd,0xbe,0xfb,0xcc,0x7d,0xee,0xd9,0xee,0x7c,0xfb,0x2e,0xd3,0xbb,
-0x5f,0x62,0xb3,0x76,0xff,0xc0,0x26,0xb8,0x7a,0xcc,0xdb,0x1b,0x8b,0x7b,0x2e,0xc6,
-0x63,0x9e,0x9e,0x58,0xd4,0xd7,0x4f,0x98,0x0e,0x8e,0xbe,0xe6,0x19,0x58,0x6b,0x6d,
-0xae,0x6c,0xc5,0xef,0x0a,0x5e,0xb3,0xc9,0xbe,0x87,0x84,0xe7,0x34,0x6f,0x07,0x96,
-0x5f,0xdd,0x16,0x73,0x5f,0x23,0xe1,0xab,0x11,0xe8,0xdc,0x39,0xa6,0x27,0x70,0x74,
-0x21,0x47,0x86,0xef,0xcf,0x45,0xde,0xce,0x74,0x72,0xe2,0xbc,0xfd,0x3a,0xd3,0xb9,
-0x2b,0x3e,0x35,0xdf,0xf4,0x15,0xdf,0x9d,0x77,0x8d,0x77,0x0a,0x0a,0x73,0x9e,0xdf,
-0x9d,0xfb,0x12,0x8f,0x3d,0x18,0xa2,0x47,0x14,0x1d,0x7f,0xe4,0x78,0x8e,0x0e,0x16,
-0xee,0x57,0xa3,0xd9,0xbb,0x92,0x2f,0xc3,0xbb,0x52,0xd1,0x7f,0x4a,0xb9,0x71,0xcb,
-0xa2,0x3e,0x2e,0x51,0x13,0x87,0x7d,0x39,0x3e,0x47,0x7b,0x73,0x74,0xa3,0x2b,0x9e,
-0x74,0xf4,0xb7,0x7f,0xfc,0xfe,0xd9,0x8f,0x31,0x6f,0x07,0x76,0x43,0xd7,0x8e,0xcc,
-0xea,0xa2,0x5c,0xed,0x80,0xb3,0xf3,0xfc,0x4b,0x11,0xdb,0xc5,0x9d,0xa2,0xea,0xb5,
-0x13,0xb9,0xf6,0x3e,0xbd,0x56,0x49,0x77,0xc8,0x3a,0x5f,0xfa,0x9e,0xf7,0x09,0xcf,
-0xd3,0xb8,0xeb,0x77,0xf0,0x29,0x49,0xbe,0xbf,0x2f,0x89,0xfa,0xfb,0xed,0xc9,0xf7,
-0xec,0xd3,0x93,0xed,0xc7,0xc5,0xf7,0x2c,0x69,0x89,0x7a,0xc7,0x04,0x3f,0x03,0xc7,
-0xf2,0x54,0x5d,0xb6,0x90,0x1e,0xe3,0x05,0xfd,0x02,0xd7,0x62,0xd1,0xac,0x5d,0xd1,
-0x25,0x96,0x1a,0xa4,0xd2,0x1f,0xff,0x48,0xfa,0xb1,0xf9,0x5b,0xc9,0xcc,0x70,0x5b,
-0xc1,0xf1,0x21,0x49,0xc1,0x6a,0x69,0x9c,0xcf,0xda,0xb5,0xec,0x18,0xed,0x4a,0x58,
-0x6e,0xe2,0x18,0xae,0x70,0xf3,0xa1,0x54,0x81,0x9b,0xa7,0x5a,0xf9,0xac,0x1d,0x38,
-0x6e,0x1f,0x4e,0xb7,0x8b,0x3e,0x35,0xd1,0x7b,0x4e,0xda,0x38,0x93,0xe2,0x3f,0x1f,
-0x66,0x59,0x32,0x1c,0xd3,0x71,0x30,0x73,0x67,0xbb,0xf3,0x1c,0x65,0x77,0xce,0x34,
-0x71,0xe3,0x23,0x79,0xe3,0xc0,0x72,0xd6,0x87,0x9e,0x37,0xce,0xba,0x58,0xe0,0x37,
-0x87,0xf7,0xbc,0x90,0xf9,0xce,0x55,0xdf,0x1a,0xf3,0x9d,0x5b,0xcd,0xd8,0x9f,0x1b,
-0x28,0x43,0xc6,0x66,0x36,0xd8,0xe0,0x43,0xc7,0x15,0x79,0x32,0x1c,0xcb,0x31,0x67,
-0x07,0x5f,0x57,0x77,0xe8,0x34,0x6f,0x2f,0xb3,0x6a,0xfc,0xbc,0x8c,0xf8,0xb9,0xcd,
-0x8c,0x39,0x3b,0xe6,0xed,0xda,0xcc,0xfd,0x8b,0xff,0x3c,0xf8,0x45,0x61,0x7e,0x6a,
-0x21,0xd7,0x9c,0xa9,0xfa,0xf6,0x74,0x4d,0x43,0x72,0xe1,0x3c,0xfc,0x6a,0x15,0x0f,
-0x58,0x47,0xea,0x91,0x69,0xae,0x6d,0xe7,0x78,0xce,0x4e,0x95,0x43,0xed,0x57,0x1b,
-0x4b,0xc4,0x73,0x75,0x7f,0x2e,0xec,0xce,0x49,0xd7,0x4e,0x38,0xae,0xe8,0xdb,0x27,
-0x8e,0x13,0x9e,0x97,0x96,0xa4,0x97,0xf2,0xd7,0x12,0x5e,0x17,0xf8,0xfd,0xc3,0xef,
-0x22,0xde,0x77,0x1f,0x2a,0x92,0x0e,0x55,0x17,0x4b,0xd5,0x3d,0x4d,0xd9,0x3d,0xd6,
-0xff,0xad,0xb4,0x06,0xc6,0x8f,0x05,0x70,0x7c,0xe3,0xb5,0x3e,0xcf,0xc4,0x71,0x0f,
-0xf6,0xe7,0xa4,0x89,0x03,0x2f,0x97,0x0f,0xfc,0x6b,0xee,0xc9,0x7a,0x37,0xf7,0xa0,
-0x13,0xa6,0x73,0x6e,0x6e,0x65,0xdc,0x9c,0xe9,0xe0,0x4e,0x12,0x86,0xab,0x58,0x2e,
-0xf3,0x75,0x68,0xe0,0xfc,0x56,0xa3,0x3f,0x68,0xad,0x0f,0x06,0x6c,0xc6,0x00,0xe6,
-0xec,0xe0,0xe7,0x38,0xf8,0x18,0x98,0x4e,0x7c,0xdd,0xde,0xa0,0x72,0x75,0xcc,0xdc,
-0xc9,0xb3,0xa6,0xec,0xcf,0x81,0xe1,0xf0,0xac,0x05,0xa6,0x4e,0x07,0xd0,0x81,0xce,
-0x3a,0x52,0xcf,0xfa,0x42,0xd3,0xa7,0x43,0xe0,0xea,0xc8,0x7b,0x85,0xef,0x1c,0xb3,
-0x76,0x9f,0xa3,0xc5,0xc7,0xb1,0x1c,0x07,0x5c,0x1d,0xb9,0xaf,0xab,0x76,0xd6,0xad,
-0xc6,0x32,0x5f,0x5b,0xc2,0xdc,0xaf,0x46,0xdd,0xa8,0x32,0x96,0xa3,0x87,0x25,0x3c,
-0x73,0x2e,0xac,0xf6,0xac,0xb9,0xe4,0xe7,0x2e,0xe4,0xb9,0x73,0x1c,0xd7,0xe1,0x39,
-0x74,0xee,0x8e,0x76,0xdf,0x8d,0x6b,0x55,0x37,0xe4,0x5f,0xbe,0x17,0x66,0x97,0x62,
-0xdf,0xfa,0xce,0xed,0xea,0x77,0xc2,0x8e,0xf3,0xe1,0x65,0xf7,0x85,0x65,0xf4,0x9f,
-0x73,0x7e,0x0e,0x2c,0xd7,0xbc,0xe7,0x5d,0x0f,0xd1,0x81,0xbe,0x39,0xd3,0xba,0x89,
-0x1c,0x77,0xe0,0xfa,0xea,0x5c,0xd7,0xea,0xa3,0xf9,0x8b,0x8f,0xf8,0xdc,0x1d,0xfc,
-0x1c,0xfa,0xb7,0x2d,0x57,0xdb,0xd6,0xa6,0xfb,0xfc,0xe6,0xea,0x3c,0xc3,0x73,0x1c,
-0xcc,0xda,0xe9,0x60,0x87,0x0e,0xce,0xee,0xe9,0xa5,0x59,0x3b,0xcb,0x85,0xbb,0xf4,
-0x98,0x69,0xe3,0x98,0xce,0x9d,0xe9,0xe1,0xfa,0x49,0xc7,0xbe,0xb1,0xd0,0xbd,0x11,
-0x99,0xbf,0x10,0x61,0x98,0xde,0x47,0x9e,0xf3,0x0d,0x4f,0xf7,0x06,0xf0,0x1c,0x7b,
-0x73,0x70,0xf3,0x27,0x7e,0x64,0xbc,0x0e,0x3c,0x21,0x5e,0x4e,0x18,0x3e,0xc0,0xe6,
-0xed,0xc0,0x74,0x70,0x74,0x99,0x8b,0xc3,0xb7,0xf6,0x74,0xae,0xfd,0xe9,0x33,0x77,
-0x1b,0x61,0x7a,0xcc,0xd3,0x1d,0xc3,0xbe,0x1c,0x5a,0x77,0xe0,0x7a,0xd4,0xdb,0x1f,
-0x05,0x96,0xc7,0x3d,0xdd,0xf1,0x98,0x97,0x63,0xfa,0xe5,0x08,0xfe,0xac,0xab,0xb3,
-0xba,0x2b,0x21,0x5b,0x31,0x45,0xeb,0x9d,0xc5,0xa3,0xb4,0xec,0x60,0x69,0xc8,0x39,
-0x10,0x62,0x7a,0x38,0x81,0x9f,0x93,0x2e,0x6e,0x70,0x1b,0x7d,0x2b,0xd1,0xe0,0x1b,
-0x51,0xc2,0xf6,0x45,0x9d,0xef,0x5c,0xc9,0x93,0xa1,0x13,0xd6,0x30,0x7c,0x7f,0xef,
-0x1a,0x9b,0xbb,0xaf,0x7a,0xae,0xae,0xde,0xfb,0xe4,0xec,0xbd,0xf2,0xf2,0xfc,0xf2,
-0xff,0x0f,0x0d,0xfc,0x21,0x1e,0xc0,0x8b,0xf7,0xde,0x33,0xbe,0xc7,0xfc,0x6a,0xac,
-0x53,0x0d,0xfc,0x9c,0x61,0x3b,0xef,0x58,0xd3,0xed,0xd2,0x95,0xfc,0x38,0x86,0xed,
-0x8a,0x2e,0x8e,0xef,0xce,0x97,0xb9,0x5f,0x8d,0x6b,0xdc,0x79,0x1f,0xcb,0xcd,0x9d,
-0x8f,0xff,0xbd,0xf9,0x63,0xe8,0xdb,0xc5,0x99,0x2e,0xd7,0xb9,0x93,0xbe,0x5d,0xe9,
-0x97,0x52,0x4f,0x96,0x94,0xaf,0xf6,0xa4,0x2b,0x3e,0xb6,0x84,0xfc,0x3b,0x51,0x03,
-0x27,0x60,0xb7,0x38,0x33,0xd4,0xcf,0x0f,0x13,0xf0,0x51,0xc8,0x3f,0x4b,0xd0,0x14,
-0xe8,0xdf,0x23,0x3c,0xc7,0xcf,0xa6,0x7a,0x7a,0xf4,0x58,0xbf,0xdf,0xf7,0x3b,0xd9,
-0x1c,0x5e,0xb7,0x1b,0x4f,0xe0,0xdb,0x49,0xf2,0xd9,0xf4,0x7e,0x85,0x64,0xcf,0x93,
-0xce,0x29,0xd2,0x18,0xdf,0x12,0x67,0xec,0x34,0x4f,0x57,0xfa,0x71,0x38,0x7e,0xf3,
-0x7e,0x7a,0x7c,0xff,0xf1,0x73,0x28,0x33,0x48,0x65,0x3f,0xb9,0x2d,0xfd,0xc4,0xfc,
-0x9d,0x82,0xe7,0x0a,0x1f,0xe7,0x3a,0x38,0xae,0x71,0x17,0x77,0xe8,0x5c,0x0b,0xc7,
-0x78,0x39,0xe6,0xf1,0xa9,0x93,0xfc,0x58,0x87,0xd8,0x1c,0x9e,0xeb,0xdd,0x69,0xc6,
-0x8e,0xd9,0xfb,0x50,0xfa,0xa4,0xe8,0x57,0x53,0xbd,0x6a,0xc0,0xf0,0xa1,0x4c,0x05,
-0xeb,0xe1,0x55,0xcb,0x20,0xef,0x39,0x3c,0x6a,0xc0,0x78,0xae,0x6f,0x9f,0x30,0xe5,
-0x4c,0x58,0x46,0x72,0x2c,0x16,0x93,0x7c,0x46,0x72,0xd9,0x31,0x1d,0xa0,0x03,0x0c,
-0xb7,0x8c,0xe4,0x59,0xc6,0x4d,0x32,0x8e,0x9b,0x14,0x3c,0x37,0x69,0x98,0xae,0xf9,
-0xcf,0x0b,0xac,0x4c,0x07,0x57,0x68,0x65,0x59,0x32,0x45,0x36,0x76,0x0c,0x36,0xc2,
-0x75,0x99,0x9b,0x23,0xc7,0x9d,0xe7,0xbd,0x26,0x64,0xb8,0x2b,0x98,0x0e,0x9e,0x9e,
-0x80,0xe7,0x5c,0xdf,0xfe,0x80,0xcd,0xdd,0xad,0xa3,0x15,0x32,0x57,0xaf,0x90,0xf1,
-0xdc,0xf0,0x85,0xa1,0x30,0xc5,0xa0,0xf6,0x07,0x27,0xe9,0x5e,0x68,0x6d,0xca,0x6a,
-0x1d,0xfe,0xf6,0xd0,0x30,0x66,0xed,0xe4,0x59,0x1b,0x3b,0x42,0xbb,0x73,0x76,0x94,
-0x3e,0x16,0xd2,0xc5,0x55,0x09,0x7a,0x38,0x0d,0xcb,0x59,0x1f,0xcb,0xb1,0x69,0xec,
-0xd1,0x45,0x0f,0xba,0x86,0xe9,0xcc,0xaf,0xf6,0xe1,0x6f,0xca,0x3f,0x2c,0x2d,0x4e,
-0x23,0xad,0x2a,0x5e,0x03,0x78,0xbf,0x0d,0x1c,0xaf,0x28,0x94,0x2a,0x2a,0x0d,0x52,
-0x65,0x55,0xb1,0x54,0x05,0x3c,0xef,0x3c,0x9d,0xdd,0x69,0xf9,0xbf,0x2a,0xcb,0xc2,
-0xc4,0xf1,0x85,0xb9,0x89,0xd7,0xe6,0xe6,0x26,0x4f,0xcc,0x91,0xff,0x7c,0xb2,0x8e,
-0x3c,0xe8,0x94,0x0d,0x37,0xa9,0xe5,0xc9,0xb0,0x2c,0x19,0x86,0xe9,0x5c,0xd7,0xce,
-0x3c,0x6a,0x8a,0x0f,0xdd,0xce,0x72,0xe2,0x80,0xed,0xd0,0xc1,0x79,0x6d,0x46,0x6f,
-0xd0,0x5a,0x17,0xa4,0x63,0x63,0x78,0x0e,0x9e,0x0e,0x6e,0x4e,0xb3,0x76,0xdb,0x49,
-0xd2,0xb3,0x2f,0x5a,0xeb,0x16,0x17,0x6d,0xf5,0x8b,0x21,0xfb,0xc9,0x10,0x71,0x74,
-0xe0,0xb9,0xbd,0x31,0x80,0x03,0x4c,0xe7,0x38,0xce,0xba,0x52,0x9b,0xbc,0xbe,0x29,
-0x19,0xcb,0xa7,0x80,0xe5,0x27,0x57,0x1e,0xda,0x4e,0x3d,0xc4,0xec,0x1d,0xfd,0x2c,
-0x2a,0x2f,0x57,0x30,0x1d,0x58,0x0e,0x2f,0xfa,0xaa,0xfd,0xd4,0xea,0xba,0xcd,0xb8,
-0xfe,0xd8,0x7e,0xea,0x31,0x76,0xe7,0x94,0xdf,0xae,0x64,0xc9,0x84,0x9c,0x6d,0x4a,
-0x8e,0x4c,0x2b,0xeb,0x53,0x9b,0x91,0x9f,0x53,0x67,0x6a,0x9b,0xd2,0xb1,0xc6,0xf2,
-0x5e,0xb9,0xc6,0x9d,0xe3,0x39,0x8e,0xdf,0xd1,0xee,0x7f,0xf3,0x46,0xd5,0x9b,0x99,
-0x99,0xa9,0x2f,0xcc,0x43,0xc1,0x3d,0xa1,0xf2,0x70,0x6e,0xe5,0x5f,0xff,0xdc,0xf8,
-0x57,0xea,0x66,0x99,0xbf,0xb8,0x04,0x4c,0x87,0x4f,0x0d,0x59,0x32,0x8f,0xdc,0x9d,
-0x8f,0x38,0xbe,0x47,0x9c,0x67,0x23,0x11,0x67,0x73,0x04,0xb3,0x76,0xe2,0xe9,0xd0,
-0xbe,0xcd,0x5d,0x78,0xbc,0xee,0x6e,0x5f,0x47,0xdf,0x39,0x70,0xfd,0xf1,0xdc,0xc5,
-0xc7,0xe4,0x51,0x9b,0x6d,0xdf,0x40,0x76,0x3b,0xcf,0x85,0x63,0x1c,0x1d,0x7a,0x38,
-0x5c,0xfb,0x68,0xfe,0x4e,0x7c,0x1d,0xbb,0x74,0x2f,0xdb,0xa5,0x63,0x87,0xce,0x72,
-0xe1,0xfa,0x28,0x2b,0x0e,0x5c,0x7d,0x6b,0xee,0xc2,0x56,0xcc,0xdd,0x1e,0x8b,0xcc,
-0x77,0x46,0xa0,0x67,0x07,0x27,0x67,0x98,0xde,0xab,0x60,0x7a,0xbf,0x8a,0xe9,0x7c,
-0xc6,0xce,0x73,0xe1,0xc0,0xd9,0x37,0x7c,0x0a,0xa6,0xfb,0x2e,0xd1,0x1e,0x3d,0xbe,
-0x70,0x21,0xbe,0x3b,0xd7,0xb1,0xbb,0x33,0xdf,0xb9,0x43,0x98,0x2e,0xf3,0x74,0xe4,
-0xca,0xe0,0x00,0xdf,0x31,0x6f,0x8f,0x7b,0x7a,0xe2,0x0c,0xd7,0x7b,0x63,0xdb,0x9e,
-0xbe,0xed,0xae,0x8e,0xa3,0x5d,0x62,0xdf,0x18,0xee,0x75,0x22,0xa6,0x17,0x16,0xe6,
-0x17,0x06,0xa6,0xfa,0x03,0x2c,0xef,0x55,0xd4,0xb7,0x23,0x4f,0xe6,0x6a,0x24,0x16,
-0xb8,0x12,0x8b,0x07,0x06,0xe2,0xb1,0xe0,0xe5,0x18,0x79,0xd1,0xc3,0x57,0xd5,0xcc,
-0x57,0x31,0x57,0x06,0xde,0x74,0xf4,0xac,0xc5,0xc3,0x83,0x94,0xe7,0x8a,0x59,0xbb,
-0xaa,0x6b,0x5f,0xe4,0x7e,0xb5,0x9b,0x31,0x7c,0xed,0x3f,0xbe,0xbe,0xf0,0x8f,0x9a,
-0x9a,0xe2,0x1a,0x64,0x2e,0x89,0x1c,0x8d,0xff,0x50,0x7f,0xc8,0x47,0xb2,0xf9,0xef,
-0x4f,0xff,0xad,0xee,0xa7,0x2b,0xf3,0xd7,0x57,0x54,0xbf,0x9a,0x82,0xe1,0xac,0x5b,
-0x4d,0xc3,0x75,0x76,0x4d,0xd4,0xc6,0x25,0xeb,0x41,0x47,0x67,0xaa,0xd6,0x9d,0x8a,
-0xfd,0xfa,0x5b,0x4f,0xe1,0x57,0xfb,0xdd,0xaf,0x9b,0x7e,0x57,0x56,0x9c,0x53,0xa6,
-0xe2,0xb2,0x3e,0x67,0x5e,0xc0,0x1a,0x55,0xdb,0xae,0x74,0xc6,0xc1,0xd7,0xa6,0xfa,
-0xd8,0x84,0x7e,0xb6,0xfd,0xba,0x5b,0x12,0xb4,0x6f,0x82,0xa7,0x6b,0xbf,0xfd,0xf3,
-0xcb,0x68,0xcb,0xf6,0x3d,0x49,0x78,0xf6,0x0b,0x75,0x0c,0x49,0xb8,0xb7,0x3a,0x73,
-0x4d,0xd9,0x3b,0x3b,0x10,0x35,0x6c,0xe2,0x7b,0x11,0xfd,0xdf,0xdf,0xa3,0x2d,0x48,
-0x4f,0x9e,0x3f,0xa4,0xe7,0xe0,0xaa,0x67,0x30,0x4b,0xf0,0x0e,0x2a,0x57,0x43,0xbe,
-0x64,0x78,0xeb,0xba,0xf4,0x16,0xe6,0xed,0x09,0xd8,0x6d,0x92,0x14,0xfd,0x9b,0xa4,
-0x78,0xcc,0x25,0x2b,0xdf,0x9d,0x33,0xef,0x5a,0xea,0x84,0xba,0x5b,0x37,0x31,0x6e,
-0x2e,0x72,0xf4,0x09,0x93,0xe2,0x57,0x33,0x89,0x7e,0xb5,0x34,0x99,0x7f,0xa7,0xab,
-0x3c,0x9d,0x74,0xee,0xe4,0x59,0xcb,0x24,0x5e,0x2e,0xfa,0xd4,0x30,0x83,0x47,0x86,
-0xfb,0xb8,0x29,0x7b,0x9c,0x61,0x78,0x8e,0x65,0xcc,0x94,0x3b,0x66,0x31,0xe5,0xca,
-0xff,0xb6,0x1c,0x19,0xaf,0xc1,0xc5,0x0f,0x8c,0x93,0x57,0x4d,0xf1,0x9f,0x93,0x36,
-0x6e,0x24,0xcf,0x4a,0x7b,0x73,0xde,0xc7,0x62,0x2e,0xb0,0xf2,0x0c,0x77,0xab,0x89,
-0xe1,0x38,0xb8,0x39,0xcd,0xd9,0xcd,0x4c,0xdf,0xce,0xf3,0x5e,0xb9,0x1e,0x8e,0x7b,
-0xcf,0x39,0x8e,0xf3,0x79,0x3b,0xb4,0x70,0x22,0x47,0xe7,0x79,0x32,0x6c,0x7f,0x5e,
-0x61,0xe3,0x7b,0x74,0xfb,0x83,0x57,0xec,0x9f,0xdf,0x2b,0xfa,0xbc,0xa8,0x20,0xb5,
-0x48,0xec,0x28,0x10,0xaf,0x38,0xf5,0x27,0x32,0xeb,0xbf,0xbb,0x5f,0xf1,0x1d,0xc3,
-0x72,0x19,0xc3,0x47,0x2b,0xa7,0xd5,0x9d,0xb9,0x7c,0xd0,0xc9,0x42,0x57,0x4b,0xb5,
-0x5d,0xeb,0x4a,0xc5,0x7c,0xbd,0x5a,0xf3,0xac,0x29,0xfa,0x76,0x36,0x6b,0x3f,0xa6,
-0xea,0xda,0xf9,0xfe,0x1c,0x19,0xb0,0xbf,0xba,0x53,0xfa,0xab,0xb2,0xe2,0xb4,0x32,
-0xcc,0xc7,0xd0,0xeb,0x56,0x56,0x20,0x95,0x55,0x14,0x49,0x15,0xe0,0xe5,0xc0,0x74,
-0x3c,0x3f,0x98,0x27,0x1d,0x3c,0x71,0x2c,0xeb,0xc4,0xf7,0xff,0x53,0xfd,0x3d,0x30,
-0x1c,0x7e,0x35,0xe0,0x38,0x32,0xe1,0xe8,0x6a,0xe5,0xd9,0x70,0x46,0xc2,0x76,0xc6,
-0xc9,0x95,0x39,0xbb,0x4d,0xdb,0x9f,0x8b,0x07,0x38,0x0e,0x1d,0x9c,0xd7,0x6a,0x94,
-0x39,0x79,0xbd,0x3f,0x60,0xad,0x0f,0xe0,0xf8,0x6d,0x46,0x36,0x5f,0xb7,0x19,0x7d,
-0x1c,0xc7,0xa1,0x81,0x5b,0xb2,0xd6,0x2d,0xad,0x58,0x5f,0x5f,0xc1,0x81,0x47,0x0d,
-0x1a,0x38,0xec,0xd1,0x09,0xcb,0x95,0x7c,0xb8,0xc0,0xf4,0xe9,0x80,0x6f,0xfa,0x8c,
-0x0f,0x38,0x4e,0x58,0x3e,0xdd,0xe4,0x83,0x36,0x0e,0x58,0x8e,0xfc,0x18,0xf8,0xd4,
-0xfc,0x0e,0x19,0xc7,0x09,0xc3,0x5b,0xd4,0x19,0x3b,0x0e,0x32,0xdb,0xd1,0xab,0x86,
-0x8e,0x54,0x74,0x9f,0xa3,0x27,0x15,0xba,0x76,0x75,0xd6,0xee,0x3a,0x47,0x7e,0x35,
-0x60,0x39,0xdb,0x99,0xb7,0x85,0xc0,0xd1,0x59,0xae,0x8c,0x92,0x0f,0x37,0x7b,0x5e,
-0xe5,0xe6,0x8c,0x97,0x77,0xaa,0x78,0x0e,0x7e,0x3e,0x78,0xa5,0x72,0x50,0x26,0x23,
-0x2f,0xe6,0xe7,0xf2,0xff,0x72,0xb3,0x53,0x73,0x7b,0xbb,0x5e,0xe9,0x9d,0x9d,0x38,
-0x3f,0xcb,0xb3,0xe2,0x30,0x6f,0x07,0x37,0x47,0x0f,0x0b,0xd3,0xb4,0x77,0x3d,0xdc,
-0x9e,0x69,0xde,0xde,0x76,0x36,0x6f,0x83,0x9f,0xaf,0xb9,0x3b,0xd7,0x56,0xe7,0xbb,
-0x56,0xd7,0xe6,0x3a,0xd7,0xd0,0xbd,0xb2,0x39,0xdb,0xb6,0x09,0x7c,0x7f,0xe4,0xe9,
-0x7e,0xc4,0x3c,0x6a,0x9d,0xeb,0xd0,0xc0,0x3d,0xf2,0xf4,0x3c,0x62,0xfe,0xb4,0x5e,
-0xe2,0xea,0xc0,0x72,0xd2,0xb3,0xc3,0x7b,0xbe,0xc0,0xb8,0x38,0xd3,0xba,0x5f,0x22,
-0x9e,0xce,0x3c,0x6b,0x7d,0x4f,0x78,0xa6,0x4c,0x74,0xae,0x23,0xba,0x3b,0xdb,0xba,
-0x1b,0x9f,0x6d,0x8b,0xc3,0x6f,0xce,0xf6,0xe6,0x97,0x9e,0x6c,0x78,0xfa,0x37,0xb6,
-0x3c,0xdd,0x5b,0xc8,0x92,0x61,0x98,0x3e,0xc0,0x32,0xdb,0xa9,0x9f,0x85,0xe1,0xb7,
-0xa6,0x8d,0xd3,0x0e,0xb4,0x70,0xe0,0xdf,0xf1,0x85,0xae,0xf8,0xce,0x42,0xd7,0x0e,
-0x38,0x39,0xe9,0xda,0x03,0x97,0xb7,0xc0,0xc5,0x31,0x67,0x07,0x8e,0xef,0x2e,0x5c,
-0xd8,0x7d,0x36,0xdf,0xf1,0x6c,0xdb,0xd5,0xb9,0x7d,0xa1,0xa5,0xe2,0x02,0xee,0x53,
-0xb8,0xa7,0xed,0xe1,0x77,0xf2,0x91,0x6f,0x84,0xe9,0xee,0xf1,0x1e,0x37,0xb8,0xb9,
-0xda,0xaf,0x26,0xec,0xd0,0xe1,0x3b,0x8f,0x05,0x81,0xe9,0x97,0xe3,0x38,0xc4,0xd7,
-0xc3,0x2c,0x5b,0x86,0xcd,0xd9,0x79,0x06,0xdc,0xf5,0x28,0xfa,0x56,0xa8,0x4b,0x2d,
-0x70,0x79,0x77,0x27,0x78,0x65,0x27,0x1e,0x1a,0x8c,0x6b,0x79,0x32,0x2c,0x47,0xc6,
-0x3d,0x7e,0xc9,0x7d,0xe6,0x74,0xe5,0x19,0x60,0x39,0xfd,0x0c,0x75,0x38,0xf1,0x3c,
-0x1c,0xfe,0xa1,0x1e,0x83,0x83,0xaf,0x0e,0x86,0x66,0xae,0x85,0x38,0x96,0x27,0xed,
-0x3e,0xd7,0xf7,0xaa,0x3d,0xfc,0x91,0xd0,0xc3,0xc2,0x3a,0x58,0x12,0x7a,0xd0,0x1f,
-0xde,0x7a,0xc6,0xf0,0x5d,0x7e,0xfe,0xf0,0xd6,0xd3,0x48,0xf0,0x46,0xe4,0x97,0x3f,
-0x6b,0xf8,0x65,0x61,0x5e,0x76,0x61,0x82,0x06,0x2b,0x3d,0x31,0x17,0x6e,0x8f,0x8e,
-0x4d,0xe8,0x99,0xd4,0xcf,0x22,0xf9,0x3c,0x5e,0xd4,0x71,0xed,0xc9,0x9f,0x49,0xa2,
-0x6d,0x4f,0xd8,0x93,0xbf,0xe8,0xfa,0x1c,0x9f,0xd8,0x7e,0xf3,0xf8,0xfd,0xf0,0x9e,
-0xff,0x7c,0x55,0x3c,0xd6,0xcd,0xf8,0xf7,0xcc,0x08,0x92,0x68,0xd5,0xf5,0x7a,0x01,
-0x11,0xbf,0xc5,0x5c,0xb1,0x3d,0x18,0xae,0x7c,0xaf,0xf9,0x7b,0x21,0xfe,0x7e,0x88,
-0x67,0xef,0xf2,0xe7,0xa2,0x27,0x90,0x7f,0x1d,0xfe,0x4e,0x5f,0x97,0xd4,0xf7,0xf7,
-0xfb,0xd2,0xdf,0xc1,0xc7,0xf9,0xcc,0xdd,0x3a,0x24,0xc9,0xd8,0x2d,0x4d,0xe2,0x6a,
-0x1b,0x96,0x6c,0x4c,0xf7,0x26,0x4d,0xaa,0x9e,0x35,0x3e,0x73,0xd7,0xf9,0xd4,0xf8,
-0x95,0xeb,0xdc,0x29,0x23,0xce,0x94,0x96,0x30,0x73,0x57,0x35,0xee,0xa4,0x8b,0xcb,
-0x90,0xbf,0x26,0x93,0x32,0x60,0x2d,0xc3,0x99,0x16,0xf8,0xd5,0xc6,0x4d,0x59,0x32,
-0x86,0x67,0xc9,0xdc,0x3b,0x5b,0x3d,0x0c,0xc3,0x71,0xb2,0xc7,0xc1,0xd5,0xd9,0xc9,
-0x9d,0x60,0x3d,0x6b,0x07,0x54,0xad,0x3b,0xf3,0xad,0xe5,0x5b,0x71,0xc8,0xb3,0x66,
-0xca,0xa7,0x6e,0x16,0xc2,0x74,0x73,0x01,0x71,0x73,0xc6,0xd5,0x0d,0x1a,0x47,0x37,
-0xcb,0xfc,0x7c,0x44,0xf3,0xa0,0x73,0xef,0x1a,0xef,0x64,0x51,0xb5,0x70,0x82,0x07,
-0x9d,0x32,0xdc,0xcd,0xa5,0x36,0xbb,0xb9,0xdc,0x0e,0x6c,0x27,0xaf,0xda,0x03,0x45,
-0x0f,0xf7,0xa0,0xc2,0xfa,0x8b,0x3b,0xf9,0xbf,0xc8,0xcb,0x4d,0xc9,0x4b,0xf0,0x76,
-0xf0,0x9f,0xa1,0xf2,0xfb,0x80,0x1e,0xf5,0x2f,0xff,0x50,0xf6,0xa5,0x7d,0xec,0x88,
-0x9d,0xfb,0xd5,0x58,0xb7,0x1a,0xfc,0xe7,0xcc,0x83,0xce,0x7c,0xe8,0xd5,0x6c,0x8f,
-0xae,0xe4,0xc3,0xa9,0xfc,0x9c,0xcf,0xdc,0x95,0xdc,0x57,0xca,0x70,0x1f,0x67,0xdd,
-0xa9,0xe0,0xe8,0xe8,0x4d,0xb5,0x99,0xaa,0x6d,0xb7,0xae,0x15,0xdc,0x2a,0x2f,0x4a,
-0x29,0x87,0xae,0x85,0xeb,0x5b,0x48,0xb7,0x9a,0x23,0x15,0xd2,0xfd,0x32,0x83,0xdd,
-0x2f,0xf3,0x0f,0xa4,0xe6,0x7f,0xf5,0x87,0xaa,0xaf,0x90,0x23,0x03,0xef,0xf9,0xcc,
-0x44,0xdd,0x0c,0xc3,0x71,0xf9,0x4c,0xb2,0xc3,0xf8,0x38,0x9f,0xb5,0xe3,0x6a,0x9c,
-0x05,0x96,0x83,0xab,0xd3,0xac,0xdd,0x6a,0x24,0xbd,0xfb,0xbc,0xcd,0x38,0xbf,0x60,
-0x35,0xca,0x58,0x5e,0xef,0xf5,0x59,0xeb,0x7d,0x38,0x98,0xb5,0x83,0xa3,0xb3,0xeb,
-0x49,0x2f,0xdb,0x9d,0x1b,0xfd,0xc0,0xf2,0x45,0x5b,0xdd,0xe2,0x92,0xf5,0xf5,0xa5,
-0x45,0xab,0xcc,0xcb,0x6d,0xc6,0x50,0xc0,0x76,0x2a,0x40,0xba,0x38,0xec,0xd1,0x89,
-0x9f,0x9f,0x26,0xad,0x3b,0xf8,0x39,0x72,0xdc,0x81,0xe5,0x81,0x29,0xf4,0xa3,0x36,
-0x2c,0x3e,0xb4,0x9e,0x7c,0x18,0x9e,0x6a,0x0c,0x63,0xee,0xee,0x75,0xa0,0x0b,0xbd,
-0xc5,0xc7,0xf1,0x9c,0xb2,0x63,0x1c,0xcd,0xda,0x5e,0x5d,0xc6,0x73,0x74,0xab,0x2d,
-0x3a,0x9a,0x16,0x69,0x6f,0xee,0x94,0xb1,0xdc,0xc9,0xfc,0xe7,0xd0,0xc4,0x85,0x9c,
-0xe7,0x42,0x0c,0xdb,0xdb,0x68,0xce,0xce,0xce,0xb9,0x30,0xdf,0x9d,0x27,0xcb,0x93,
-0x21,0x6c,0x77,0x77,0x84,0x5d,0x13,0xe7,0x5c,0xcd,0x4d,0x25,0xcd,0xfc,0x7e,0xff,
-0xbc,0x07,0x7e,0xcf,0xc9,0xef,0x5f,0x98,0x51,0x74,0xe7,0xdd,0x57,0xef,0x78,0xec,
-0x9d,0x1e,0xf4,0xb2,0x20,0x4b,0x46,0xcb,0x7a,0xed,0x26,0x3d,0x1c,0xfa,0xcf,0x37,
-0x5c,0xad,0x1b,0x6b,0xee,0x8e,0x35,0xec,0xce,0xd1,0xcd,0x02,0x9d,0xfb,0xc6,0xec,
-0xf9,0x0d,0xec,0xcb,0xc1,0xd5,0x91,0xf5,0x0a,0x6d,0x3b,0x3c,0xe7,0x6b,0x73,0x5d,
-0x6b,0x2c,0xe7,0x95,0xcd,0xdc,0xa9,0x63,0x4d,0xe1,0xe7,0xa4,0x69,0x5f,0x60,0x1e,
-0x35,0xf2,0xad,0x91,0x96,0x9d,0x1d,0xae,0x8b,0x03,0xae,0x6f,0xcf,0x75,0x6e,0x03,
-0xcf,0x77,0x5d,0xad,0xbb,0xd1,0xb9,0xf6,0x28,0x76,0xe7,0x94,0x2f,0xe3,0xeb,0x7f,
-0x82,0x5d,0x3a,0x30,0x9e,0x7a,0x58,0x88,0xa3,0x0f,0x3c,0x61,0x5d,0x2c,0x97,0x69,
-0xf6,0x4e,0x58,0x8f,0x19,0x7c,0x40,0xe1,0xeb,0xd4,0xcd,0x82,0xf9,0x3b,0x76,0xe6,
-0x7d,0xdb,0xc0,0x72,0x70,0xf4,0xa8,0xa7,0x37,0x1a,0xf1,0xf5,0x33,0x6f,0xba,0x8f,
-0x69,0xdc,0xa3,0xbe,0xde,0x28,0x30,0x7d,0x75,0xa2,0x65,0xb5,0xf5,0x44,0x5e,0x2b,
-0xde,0x73,0x62,0x9e,0x84,0xfb,0x17,0xe7,0x75,0x22,0xf7,0xf9,0xd3,0x7f,0xb7,0xfd,
-0x69,0x2b,0x88,0xbd,0xf9,0x55,0x8d,0x9f,0x87,0x12,0x75,0xee,0x0c,0xd7,0x07,0x69,
-0xf6,0x1e,0x0f,0x5e,0x89,0xd3,0xc7,0xa1,0x6b,0x51,0xea,0x51,0x55,0x33,0xe2,0xae,
-0x47,0x90,0xbf,0xbe,0x13,0xbc,0xbc,0xf3,0xd4,0xdf,0xff,0xf4,0x99,0xaf,0xef,0xd9,
-0xd3,0xc0,0xa5,0xa7,0x3b,0xc1,0x37,0x76,0xc0,0xd9,0x57,0xdc,0x6f,0xac,0xf4,0x74,
-0xd7,0xf6,0xe8,0x7f,0x8e,0xc9,0xf8,0x5c,0xb2,0xcf,0xff,0x50,0x8f,0xba,0xba,0x43,
-0x75,0xce,0xd1,0xcb,0xce,0xf8,0xf2,0xad,0xb8,0xa8,0x6d,0x4f,0xe8,0x3f,0x5f,0xd6,
-0x30,0x7d,0xdf,0x3e,0xf4,0x04,0xbc,0xe7,0xfe,0x74,0x76,0x1e,0xb9,0xaf,0x3e,0xba,
-0xf9,0x46,0xf5,0x4d,0xbc,0x2f,0x4d,0xd8,0x01,0xa7,0xb1,0x1d,0x70,0x6e,0x56,0x6a,
-0x6e,0x61,0x7e,0x46,0x21,0xae,0x9a,0xaf,0x3c,0x25,0x23,0xff,0x40,0x46,0x7e,0x6e,
-0x4e,0x7a,0x6e,0x7a,0x6a,0x4a,0x7a,0x76,0x56,0x5a,0x76,0x41,0x5e,0x66,0x81,0x4c,
-0xee,0x73,0xf0,0xe7,0x79,0xb9,0x69,0x79,0xf8,0x9a,0xec,0x8c,0x14,0xe2,0xe9,0x09,
-0xf9,0xf5,0xca,0x3d,0x51,0x7c,0x6f,0x90,0x0c,0xdf,0xf7,0xd5,0x8c,0xeb,0xb0,0x59,
-0x3f,0x57,0x57,0x79,0xbd,0x94,0xa4,0xd7,0x2d,0xc9,0xd7,0xef,0xf7,0x9e,0x40,0xbd,
-0x4a,0xfb,0xcf,0x06,0xf4,0xfb,0x72,0x31,0xdb,0x43,0xcc,0x23,0xd9,0xe3,0xe7,0x4f,
-0xa2,0x59,0xe7,0x7f,0x26,0xfe,0x7d,0x7d,0xa6,0x09,0xc7,0x79,0xcc,0xdc,0xa1,0x83,
-0xc2,0xef,0x4a,0x47,0xb3,0xd4,0xf1,0xf5,0x1f,0xa5,0xaf,0x69,0x77,0x2e,0x63,0x36,
-0xc3,0x6d,0x9e,0x1f,0x23,0xf3,0xef,0x21,0xae,0x7b,0x4b,0x49,0xd8,0xa5,0x8f,0x9b,
-0x52,0x14,0xed,0x5c,0xaa,0x4e,0xdb,0xce,0xf7,0xe7,0xa9,0x0c,0xcb,0x87,0xd2,0x14,
-0xdf,0x39,0x76,0xe7,0xe9,0x56,0xe8,0xda,0x79,0xb7,0x9a,0xc5,0x94,0x21,0xf3,0xee,
-0x0c,0x99,0x77,0x67,0xca,0xd7,0xcc,0x31,0x86,0xe3,0x59,0x16,0x60,0x3a,0xce,0xc4,
-0x48,0xd6,0x84,0xd6,0x93,0x9a,0x6d,0x9d,0x18,0xc9,0x99,0xc0,0xfe,0x9c,0xb2,0xe1,
-0x14,0x2c,0x67,0xba,0x76,0xcd,0x7f,0x8e,0x43,0x5e,0x35,0x13,0xcb,0x84,0x13,0xf3,
-0x64,0x70,0xa6,0x4d,0x05,0xd3,0xc8,0x95,0x51,0xb1,0x5c,0xc8,0x93,0x61,0x57,0x0d,
-0xcf,0x39,0x4f,0x47,0xff,0x8a,0xdd,0x5c,0x62,0x9f,0x36,0x97,0x4c,0x3b,0xcc,0xa5,
-0x0e,0xa7,0xb9,0xc4,0xe9,0x34,0x97,0x3a,0xa7,0xcd,0xa5,0xd3,0x5c,0x03,0x47,0xfa,
-0x76,0xf9,0x8c,0x7e,0x5f,0x3e,0x8a,0x7e,0x74,0xde,0x8d,0x9e,0xf0,0xbe,0x2c,0xe1,
-0xb5,0x9a,0x92,0xfa,0xc1,0x6f,0x0c,0x1f,0xa0,0x27,0x95,0xba,0x52,0x15,0x2c,0xe7,
-0xb9,0x32,0xe0,0xe6,0x7c,0x7f,0xce,0x3b,0x59,0x9c,0x63,0x55,0xce,0xc4,0x6e,0xb5,
-0x1a,0xd6,0xcb,0x32,0xce,0x3a,0x59,0x78,0xff,0xb9,0x6b,0xfc,0x98,0xcb,0x65,0x39,
-0xe6,0x1a,0xbe,0x5f,0x39,0xdc,0xd1,0x9c,0xdd,0x81,0xfe,0x75,0xae,0x4d,0xc5,0x3c,
-0x8c,0xee,0x8f,0xa9,0xda,0xfd,0x91,0xdd,0x23,0x53,0xd2,0x3e,0xb9,0x7b,0xe8,0x93,
-0x99,0xc9,0xd7,0x67,0x66,0x26,0x95,0xbc,0x76,0x8e,0xe3,0x93,0x6c,0xde,0xce,0xb2,
-0x5f,0x79,0x2f,0x0b,0xeb,0x57,0x73,0xdb,0xea,0xdd,0x2c,0x23,0x0e,0x18,0x5e,0xbf,
-0x00,0x1c,0xf7,0xd8,0xea,0x3d,0xe0,0xe5,0x1e,0xab,0xd1,0xe3,0xb1,0xc2,0x73,0xce,
-0x0e,0xc7,0x72,0xd2,0xc0,0xd9,0x81,0xe5,0xf5,0xa1,0xb0,0xad,0x3e,0x8c,0x03,0x1c,
-0xa7,0x3d,0xba,0xbd,0x81,0x72,0x5e,0xd1,0xc3,0x82,0x2b,0xd3,0xb8,0x23,0xf3,0xb5,
-0x31,0xe8,0xb7,0x9f,0xf6,0xfb,0xa7,0x9b,0xfc,0xe0,0xe9,0xd0,0xc3,0xad,0xd8,0x4e,
-0x92,0xb6,0x1d,0xfb,0x73,0xaf,0xa3,0x45,0xc6,0xf2,0x66,0x9f,0xd7,0xd9,0xe2,0xe5,
-0x78,0x8e,0xac,0x76,0x64,0xb6,0x23,0xc3,0x7d,0x65,0xaa,0x71,0x05,0x1d,0x6b,0xd0,
-0xc2,0xa1,0xf3,0x9c,0xb0,0x5c,0xe9,0x55,0x03,0x96,0xe3,0x73,0xc8,0x86,0x63,0x7a,
-0xb8,0xb6,0x10,0xe7,0xe7,0xcb,0xce,0x96,0xe5,0xa5,0x99,0xd6,0x25,0xca,0x89,0x9b,
-0xe5,0x79,0xaf,0x1a,0x47,0xe7,0xc7,0xf4,0x4d,0x93,0xa9,0xea,0xe8,0x81,0xaa,0x17,
-0xdd,0xcb,0x39,0xef,0x60,0xf8,0x94,0x92,0x56,0x79,0xe4,0x40,0xe5,0x67,0x9f,0x9e,
-0xfc,0x2c,0xe0,0xec,0x0c,0xf0,0xec,0xf6,0xc7,0x6e,0xe8,0xe1,0xba,0xc9,0xab,0x86,
-0x9e,0x35,0x74,0xa7,0xa2,0x0b,0x1d,0xbb,0x73,0x1c,0x70,0x72,0x68,0xe0,0x30,0x73,
-0x07,0x7e,0x03,0xcb,0x71,0x5d,0x9b,0x67,0x07,0x3a,0x38,0x35,0xb7,0xdd,0x83,0xdc,
-0xf6,0xae,0xf5,0xf5,0xf9,0xae,0x75,0xec,0xca,0xc9,0xa3,0x86,0x7e,0x35,0xf2,0xac,
-0x29,0x1d,0x6b,0xe8,0x53,0xa3,0x6c,0xb8,0x7e,0xc2,0xf3,0xcd,0x85,0xee,0xcd,0xc8,
-0x5c,0x47,0x64,0x67,0xb6,0x75,0x67,0x67,0xf6,0xdc,0x0e,0x76,0xe9,0x98,0xb5,0xb3,
-0x6e,0xb5,0xde,0x0d,0x9e,0xed,0xaa,0x62,0x37,0x74,0x71,0x32,0x7e,0xe3,0x80,0xa3,
-0xc3,0x87,0xae,0xf1,0x74,0x96,0xdb,0x4e,0xd9,0xed,0xc8,0x7b,0x85,0xae,0xdd,0xdb,
-0x17,0x89,0x7a,0x7b,0xa3,0x31,0x6f,0x5f,0x2c,0xe2,0xeb,0x8b,0x80,0xab,0x73,0xcf,
-0x1a,0x34,0xef,0x43,0x5f,0x35,0x0d,0xd5,0x55,0xa4,0xd4,0xbd,0x56,0x2e,0xbd,0x76,
-0xc4,0x20,0x1d,0x81,0xb6,0x1a,0xb3,0x46,0x9e,0xbb,0xc8,0xe6,0x97,0x29,0xa9,0xb7,
-0x6f,0xd5,0xdd,0x5e,0xf7,0x0f,0xae,0x27,0xfa,0xd4,0xae,0x25,0x68,0xda,0x35,0xef,
-0xf9,0x35,0xca,0x87,0xc3,0x6c,0x1d,0x98,0x1e,0x0b,0x03,0xd7,0xaf,0x2a,0x3c,0x5d,
-0xcb,0x95,0x01,0x37,0xdf,0x0d,0x0e,0xec,0xfe,0xd3,0xdf,0xff,0xcf,0x67,0xfe,0xfe,
-0x67,0x9b,0x73,0x7d,0x9b,0x1f,0xfd,0xda,0xf8,0x51,0x6e,0x76,0x5a,0x2e,0xdf,0xf9,
-0x26,0xfb,0x99,0x26,0x7d,0xfe,0x03,0xa3,0x7a,0x61,0x41,0x5e,0xe1,0xdf,0xbe,0xbc,
-0xf0,0xb7,0xd8,0xd2,0x9b,0x31,0x6d,0xd6,0x2e,0xee,0xcf,0x45,0x9c,0xd6,0x71,0x75,
-0xe2,0xe9,0x42,0xef,0xb9,0xcc,0xd5,0x35,0xce,0xae,0xcd,0xe2,0x47,0xbf,0xed,0x1b,
-0x3d,0xd3,0x58,0x76,0x26,0xd9,0x4c,0x04,0xda,0x90,0xd6,0xe6,0x23,0xad,0x1f,0xbe,
-0x7f,0xee,0xc3,0xa6,0xd3,0xaf,0x34,0x65,0xa6,0xa7,0x12,0x0e,0xe7,0xe7,0x65,0xe7,
-0xdf,0xfd,0x6d,0xeb,0xdd,0x77,0xde,0xae,0x7b,0x27,0xff,0x40,0x56,0xfe,0x40,0xdf,
-0xab,0x03,0x9f,0xdf,0x6b,0xff,0x7c,0xf0,0xca,0xeb,0x83,0x78,0xfe,0xf6,0xad,0xba,
-0xb7,0x7f,0xff,0xd1,0xb9,0xdf,0x1b,0x8a,0x0a,0x0c,0xe2,0x7b,0x03,0x51,0xef,0x25,
-0xe6,0xd8,0xeb,0xf5,0xf2,0x7a,0x2e,0xbc,0x07,0x7b,0xc5,0xef,0xb7,0x88,0xe7,0xc2,
-0xfb,0x2b,0xbd,0x7f,0x20,0x29,0x47,0xd7,0xf1,0xf3,0x64,0x98,0x9e,0x6c,0x57,0xae,
-0xd7,0xaf,0xed,0xd1,0xb9,0xe9,0x75,0xeb,0x69,0x89,0x19,0x3b,0x7b,0x7a,0x72,0xf5,
-0x5a,0x38,0x05,0xdb,0xf9,0xdc,0x5d,0xd4,0x30,0xf0,0x6e,0x6e,0x9e,0xc7,0x5b,0x5b,
-0x25,0xd5,0xde,0x7d,0x5f,0xba,0x3b,0xfa,0xbd,0x34,0xca,0xb3,0x63,0x30,0x77,0x67,
-0xbb,0x72,0x89,0x66,0xee,0x8c,0xbb,0x33,0x7c,0xe7,0xfe,0x34,0xae,0x6d,0xa7,0xcf,
-0x0d,0x29,0x78,0x3e,0xa4,0x61,0x39,0xc3,0xf0,0x34,0x3b,0xce,0xd4,0x70,0xda,0x14,
-0xae,0x2a,0x9e,0x0f,0xa7,0x8f,0x03,0xc7,0x39,0x96,0x5b,0x86,0x33,0x88,0x9b,0x53,
-0x5f,0x2a,0x3a,0xd0,0x85,0x1e,0x74,0xf8,0xcf,0x49,0x07,0x37,0x02,0x1d,0x1c,0xc3,
-0x73,0xce,0xcd,0x55,0x1c,0xa7,0x93,0x47,0x87,0x77,0xb1,0xf0,0x7c,0x38,0xe4,0xc8,
-0x4c,0x99,0x38,0xa6,0x17,0x50,0x46,0x9c,0xcd,0x5c,0x64,0x83,0x5f,0x0d,0x47,0xf3,
-0xa0,0x1f,0x14,0x78,0xb9,0xe6,0x3f,0x9f,0x36,0x17,0x4f,0x3b,0x47,0x8a,0x9d,0x2e,
-0x73,0xb1,0x6b,0x76,0xa4,0x78,0x96,0x9d,0x92,0x59,0xe0,0xf9,0xd4,0x83,0x52,0xf9,
-0xbf,0x57,0x66,0x17,0x33,0xe2,0xee,0xff,0xb9,0xe4,0xfe,0xf1,0xda,0xf4,0xe3,0xb4,
-0xef,0xd3,0xcd,0x6a,0xc4,0xd7,0x12,0xae,0x2d,0x2d,0xd9,0x2d,0xa3,0xc3,0x87,0x47,
-0x19,0x9e,0x57,0xaa,0x5d,0xa9,0x2c,0xbb,0xbd,0x52,0xc6,0xf0,0x4a,0xd7,0xec,0xe8,
-0xd1,0x59,0xba,0x8e,0xe1,0x5a,0xe5,0x42,0x1f,0x0b,0xae,0xfc,0x63,0x8e,0xeb,0xbc,
-0x33,0x15,0x38,0x0e,0x3c,0x77,0x8e,0xd5,0x38,0x3f,0xfd,0xa8,0xfc,0xd3,0x63,0x47,
-0x33,0x8e,0x21,0x6b,0x80,0xe6,0x96,0x8a,0xc6,0x32,0xa9,0x0e,0x45,0xfe,0x37,0xf5,
-0xf5,0x16,0xf6,0x4d,0x8f,0x9e,0x98,0x06,0xa6,0xb3,0xfe,0x15,0xed,0xf0,0x6e,0x35,
-0xc2,0x71,0x85,0x9f,0xe3,0x00,0xcb,0x19,0x8e,0xcb,0xc7,0x26,0x63,0xb9,0xb5,0x5e,
-0xc6,0x6e,0xa3,0x07,0x1f,0x93,0xef,0x5c,0xcd,0x91,0x61,0x78,0x8e,0x39,0x3b,0x4e,
-0xd0,0x6a,0x0c,0x06,0x6d,0xc6,0x20,0x66,0xee,0xd0,0xc2,0x21,0xf7,0x95,0xf4,0xed,
-0xf6,0xd3,0xa4,0x71,0x57,0xfb,0x58,0xe0,0x41,0x57,0xfa,0xd5,0xb0,0x37,0x07,0xae,
-0xf3,0x8c,0x38,0x78,0xd6,0xc0,0xd3,0xc1,0xcb,0xf7,0x72,0xf3,0x16,0xe2,0xe5,0xf0,
-0xa4,0x03,0xc7,0xa1,0x83,0x0b,0x39,0x9a,0x43,0x41,0x47,0x4b,0x90,0xcd,0xe0,0xdb,
-0x28,0x53,0x06,0x39,0x32,0x98,0xbb,0x2f,0x3b,0x9a,0x96,0x97,0x1d,0x67,0x97,0x29,
-0xef,0x95,0xb0,0xbc,0x2d,0xbc,0x3c,0xd3,0xb2,0xbc,0xec,0x6c,0x5e,0xc6,0x73,0x3e,
-0x73,0x67,0xfa,0xf6,0x44,0x2c,0x0f,0xb8,0xda,0x03,0x77,0x3f,0x78,0xfd,0xae,0xc1,
-0x90,0x65,0x78,0xe1,0x4d,0x39,0x85,0xf1,0x73,0xbc,0x3e,0xe8,0x7b,0x2f,0x3f,0x1a,
-0x1a,0x0c,0x0d,0x5f,0x7e,0xd1,0xf8,0x65,0xc8,0xd9,0x19,0x82,0x87,0x0d,0x98,0x4e,
-0xf9,0x70,0x32,0x3f,0x5f,0x73,0xb7,0x53,0x77,0x2a,0xf3,0xac,0xc9,0x58,0x2e,0x73,
-0xf3,0xf5,0xd9,0xf6,0xf5,0x4d,0xd7,0xb9,0x4d,0x70,0x74,0xf4,0xaa,0x61,0xd6,0x4e,
-0x38,0x2e,0xe3,0x3a,0x1d,0xc2,0xf3,0x5e,0x96,0x07,0x37,0xdf,0xfd,0x18,0x7d,0x6b,
-0x11,0x77,0x5b,0x04,0xfd,0x6a,0xc0,0x74,0xfc,0x39,0x65,0xca,0x78,0x2f,0x3d,0xe6,
-0x33,0x77,0x1c,0xae,0x6d,0xc7,0x81,0x26,0x2e,0xe6,0x3e,0x1f,0x7b,0xea,0x6a,0x7d,
-0x1a,0x77,0xb7,0xc7,0x81,0xf1,0x7c,0x6f,0xae,0xf5,0xa5,0x02,0xd3,0xfb,0x37,0x29,
-0x4f,0xc6,0x7f,0x59,0xc0,0x74,0xe4,0xbb,0xca,0xb8,0x2e,0x73,0x72,0xea,0x57,0x53,
-0xf2,0xdb,0x81,0xe9,0xe4,0x3b,0x57,0x72,0x64,0xc0,0xcf,0x23,0x5e,0xf9,0xf8,0x65,
-0x9e,0xae,0xe0,0xf9,0xda,0xfc,0xa5,0xb5,0xdb,0x6f,0xbe,0x7a,0xbb,0x34,0x5f,0x2a,
-0x3d,0x7a,0x50,0x3a,0x5a,0x5d,0x22,0x55,0x1f,0x36,0x48,0x87,0xa1,0xf9,0xc0,0x3d,
-0x0c,0xf7,0x36,0x8e,0x31,0xb5,0x35,0xc5,0xb5,0xce,0xb1,0x5e,0x27,0xe6,0xed,0x94,
-0xdb,0xce,0x7d,0xe7,0x21,0x3d,0x96,0xf3,0x7d,0x39,0xcf,0x92,0x51,0x70,0x9d,0x0e,
-0x7a,0x51,0xaf,0x25,0x78,0xd0,0xd1,0x99,0x8a,0x19,0x7c,0xc4,0x3b,0x10,0xf9,0xfa,
-0xbf,0x9a,0xbe,0x3e,0x55,0x7b,0xe0,0xd4,0xbf,0x68,0xbb,0x12,0xa7,0xa8,0xee,0x74,
-0xdb,0xcd,0xd2,0x28,0x6b,0xb3,0x35,0x28,0x22,0xd8,0xce,0x40,0x23,0x2e,0x11,0x59,
-0x55,0x76,0x10,0x10,0x62,0x54,0xf2,0x26,0x31,0x9b,0x93,0x89,0x93,0x31,0x71,0x62,
-0xf2,0xf2,0x32,0xa9,0x4a,0x39,0x79,0x49,0x8c,0x59,0x8c,0x29,0x9d,0x24,0xae,0x89,
-0x89,0x02,0xcd,0xd2,0xd0,0x74,0x4b,0xd3,0x1b,0x3b,0xbd,0x80,0x20,0x3b,0x9a,0x57,
-0xf3,0xe7,0xbc,0x7b,0xbe,0xdf,0xfd,0xdd,0xbe,0x7d,0x69,0x1c,0x5e,0xa6,0x5e,0x57,
-0xfd,0xea,0x36,0x34,0x60,0xdb,0x77,0x39,0xf7,0x7c,0xdf,0xf9,0xce,0x49,0x4f,0x50,
-0xa5,0xe3,0x9e,0x18,0xd7,0x54,0x9c,0x47,0x4f,0xd3,0x54,0xfd,0x7f,0xf1,0x73,0xe8,
-0x28,0x4f,0xff,0x31,0xff,0xf4,0xdc,0xe8,0xb1,0x39,0xc2,0xf2,0xa9,0x40,0x9f,0x5c,
-0x8e,0xe9,0xf4,0xfc,0x61,0x30,0xbe,0xb3,0x3a,0xbb,0xac,0xfe,0x2e,0x6e,0xe5,0x59,
-0xe8,0xab,0x9e,0xe7,0x56,0x3f,0xfe,0xa0,0xe8,0x63,0x5d,0x6a,0xac,0x4e,0xe9,0x29,
-0x8a,0xcf,0x1b,0xf9,0x03,0x2f,0xb5,0x1a,0x5e,0xf2,0xda,0x9a,0xbc,0xad,0x2d,0xfa,
-0x56,0xe1,0xe6,0x8a,0x38,0x7c,0x52,0x62,0x42,0x92,0x6f,0xb0,0xc9,0x77,0xeb,0x9b,
-0xd2,0x5b,0xd9,0xdb,0x13,0xb2,0xaf,0x7d,0x55,0x7e,0xed,0x57,0xdf,0xf1,0x5f,0xaf,
-0x7f,0x5b,0x79,0x7d,0xc7,0x0e,0xed,0x8e,0x2b,0x5f,0x16,0x5f,0xf1,0xdb,0x8f,0xfa,
-0xb7,0xa4,0xa7,0x6c,0x51,0xce,0x5b,0x2b,0xe7,0xae,0x83,0xb0,0x51,0xa6,0x01,0x0f,
-0xf2,0xbf,0x7a,0x5a,0xcf,0x5c,0xa1,0x3f,0x97,0xf6,0x87,0x7a,0xed,0xbe,0x59,0x4f,
-0xbb,0xce,0xf7,0xad,0x52,0x8f,0x17,0x12,0xcb,0x15,0x7a,0x74,0x65,0x5d,0x3d,0x54,
-0x5f,0x42,0xe9,0xe7,0x1b,0x8a,0xc7,0xcb,0x35,0x88,0x72,0x0c,0x97,0x9e,0x6b,0x02,
-0x5f,0xcb,0x6b,0xf1,0x98,0x59,0x3b,0xd9,0xa2,0x3a,0x89,0x9a,0x3b,0xf9,0xbb,0x8a,
-0xba,0x38,0xe6,0x09,0x27,0x9b,0x5b,0x0b,0x39,0xaf,0x86,0x0c,0x96,0x80,0xb7,0x8c,
-0xe4,0xe3,0x2e,0x71,0xf2,0x70,0xab,0xb4,0x6d,0xc3,0x9c,0x5a,0x84,0x80,0xc5,0x8c,
-0x9f,0x13,0x86,0x53,0x5e,0xaa,0xcc,0x53,0xa6,0x5d,0xc4,0x73,0xa9,0x97,0xbe,0x49,
-0xc2,0xf3,0xfe,0x76,0xa6,0x6d,0xe7,0x8b,0x3c,0x65,0x44,0x3f,0x19,0xc2,0x75,0xe2,
-0xe5,0xcc,0x4b,0x06,0x19,0xe8,0xb4,0x15,0xeb,0xed,0xc0,0x74,0xb9,0x3f,0x5c,0x9f,
-0x51,0x2b,0xe2,0x38,0x5b,0x52,0x66,0xaa,0x31,0x49,0xc0,0xf0,0x24,0x0b,0xb2,0xd6,
-0x06,0x3b,0x93,0x06,0x81,0xe3,0x76,0x63,0x92,0x9d,0x56,0x67,0xb2,0xb0,0x52,0xec,
-0xe0,0xe6,0xc4,0xcb,0x05,0x1c,0xe7,0x7e,0x32,0xa4,0x73,0xef,0x4e,0xb3,0x98,0x3a,
-0xd2,0x4d,0x6f,0x9f,0x8d,0x7f,0x3b,0x31,0x31,0x2c,0x51,0xea,0xfd,0x3c,0xa5,0x26,
-0x17,0x1d,0xad,0x8e,0xbe,0xf4,0x49,0xca,0x25,0x6b,0xd7,0x36,0x2b,0x7a,0xe8,0xc8,
-0x63,0x71,0xf4,0x6c,0x13,0xb0,0x7b,0x9b,0x13,0xcb,0xd5,0x93,0xe9,0x02,0x96,0x53,
-0xee,0x39,0x5f,0xa6,0x6c,0xca,0x40,0x07,0x96,0xdb,0x4d,0x3b,0xec,0x0c,0xc3,0x77,
-0x38,0xe8,0xb9,0x49,0x4f,0xdc,0x1c,0xdb,0xf6,0x3b,0xdb,0xdb,0x1b,0xeb,0xe2,0x1b,
-0xa3,0x37,0xb1,0x39,0xf8,0x50,0x3a,0x52,0xe9,0xde,0x56,0x3c,0xf6,0x13,0x13,0x23,
-0x12,0xef,0xde,0xd0,0xdf,0x45,0xff,0x1c,0x1c,0x9d,0x78,0x3a,0xaf,0xb7,0x83,0x97,
-0x9b,0x03,0x38,0x8e,0x79,0x35,0xb7,0x79,0x97,0x1b,0x1e,0xee,0x1c,0xcf,0xc1,0xd1,
-0x69,0xd1,0xec,0x39,0x7c,0x64,0x04,0x4c,0xef,0xdf,0x3d,0xcc,0x6b,0xed,0x1c,0xcb,
-0x51,0x67,0x67,0xcf,0xe1,0xf7,0x8a,0x4c,0x16,0x96,0xcb,0x82,0x2c,0x16,0xf2,0x7d,
-0x15,0xfd,0xdb,0x89,0xa7,0x0f,0x3c,0x33,0x36,0x3a,0xb0,0x7f,0x14,0x78,0xce,0x66,
-0xd6,0xf8,0xfc,0xf9,0x1e,0x3f,0x74,0xee,0xe8,0xa1,0x13,0x9e,0x0f,0x32,0x4c,0x07,
-0x4f,0x47,0x8d,0x1d,0xbd,0x74,0x9e,0x7d,0xee,0x19,0x38,0xe0,0x21,0x2c,0x1f,0x64,
-0x58,0x4e,0x79,0x2c,0x62,0x26,0x0b,0xb0,0xdc,0x67,0x2b,0xf4,0x4d,0xdb,0x0a,0xa6,
-0xa7,0x6c,0x85,0x53,0x5e,0x3b,0xf3,0x6f,0x87,0xc6,0xdd,0x3f,0x58,0xe4,0x07,0x47,
-0xe7,0x79,0x2c,0xdc,0x5b,0x46,0x9e,0xc9,0x02,0x3c,0xb7,0x99,0x8a,0x6d,0x75,0xd5,
-0xe9,0x75,0x91,0x91,0x1b,0xeb,0x9d,0xf3,0x6b,0x02,0x3f,0x16,0xd0,0x0b,0x2e,0x2d,
-0x4e,0x29,0xbd,0x7e,0x65,0xef,0x75,0xcf,0xc0,0x41,0x01,0xd3,0xcb,0x67,0x38,0x3f,
-0x7f,0xe4,0x3a,0xf4,0x48,0xaa,0xb5,0x0f,0x55,0xcc,0xcc,0xbb,0x0e,0xcd,0xaf,0xd8,
-0x8b,0x56,0x1e,0x0f,0x16,0x3e,0x86,0x87,0x0c,0xbe,0x9e,0x77,0x1d,0x9e,0x67,0x38,
-0x0e,0x3c,0xaf,0x7a,0x44,0x1a,0xf7,0x61,0xe8,0xe1,0x6a,0x67,0xe1,0xe9,0xbe,0xe0,
-0xae,0x5c,0x58,0x71,0x95,0xad,0xac,0x3a,0x05,0x4c,0x77,0x1f,0x5e,0xe6,0x3d,0x74,
-0xee,0x1d,0x03,0x7e,0x4e,0x78,0x3e,0xc6,0xf4,0xed,0xd4,0x47,0x1f,0xad,0x59,0x58,
-0x75,0x1f,0x5e,0xfd,0xa7,0xb3,0xf8,0x9f,0xa8,0xbd,0x93,0xde,0x7d,0xb4,0x66,0x89,
-0xf9,0xc1,0xd5,0x2f,0x30,0xdf,0xf6,0xca,0xd5,0x95,0xe1,0xea,0x15,0xf2,0x95,0xa1,
-0xda,0x7a,0x43,0x00,0xd7,0xc7,0x8f,0x2c,0x04,0x7a,0xe8,0x8d,0x0c,0xcf,0x85,0xad,
-0xe4,0x07,0x37,0xce,0xbd,0x64,0x98,0xef,0x2b,0xf7,0x95,0x31,0xde,0x3a,0x68,0xcc,
-0xce,0x8c,0xcf,0x46,0x7f,0x10,0x7c,0x03,0xb8,0x8e,0xba,0x3b,0xf0,0x14,0x98,0x8e,
-0xda,0x22,0xea,0x4b,0xb8,0xfe,0xc5,0xc6,0x44,0xc4,0xbe,0xf7,0xd7,0x7d,0xef,0xcd,
-0x8f,0x36,0xcd,0xaf,0xe5,0xe7,0x2d,0x12,0x96,0x07,0xcf,0xaa,0x89,0x73,0x6a,0x02,
-0xae,0x93,0xef,0xab,0xa7,0x85,0xb2,0xce,0x25,0x2d,0x9c,0x88,0xeb,0xcb,0x9e,0x67,
-0x97,0x7f,0xf9,0xbe,0xfc,0x97,0x7d,0xf9,0xba,0x7d,0xda,0x68,0xb5,0x16,0xef,0x03,
-0x5a,0x13,0xf4,0xab,0x30,0xbf,0x85,0x6b,0x28,0x9f,0xa7,0x7b,0x1a,0x7e,0x4b,0x35,
-0x60,0xf9,0xf9,0xff,0x6f,0xa0,0x7d,0x66,0x66,0x4a,0xa6,0xe9,0x7e,0xad,0x49,0xc2,
-0xf3,0x29,0xd1,0x3f,0x86,0xf7,0xce,0x1f,0x72,0x6e,0xce,0x31,0x5e,0xc6,0xc9,0x1f,
-0x0a,0x98,0x2e,0xbe,0x46,0xcf,0x45,0x5c,0xe7,0xcf,0x1d,0xa6,0x46,0x07,0x32,0xee,
-0x78,0xae,0x8c,0x52,0x7f,0x8d,0x1c,0xc1,0x97,0x5b,0x0d,0x2f,0xfb,0x6c,0x4d,0x3e,
-0xc2,0xf3,0x88,0x70,0xfa,0xff,0x27,0x6a,0x13,0x12,0x81,0xe7,0xb7,0xbf,0x3d,0x78,
-0xfb,0x50,0x69,0xc6,0x21,0x7b,0xef,0x11,0xbb,0xcf,0xd5,0xec,0x73,0x59,0x1b,0x5d,
-0xd5,0x15,0x99,0xd5,0x57,0x2f,0x97,0x5d,0xf5,0x3b,0x80,0xe7,0xa9,0x5b,0x94,0x58,
-0x1c,0xb2,0xa6,0x1d,0x42,0x3b,0x26,0xdf,0x2a,0xe7,0xd3,0xe5,0xfc,0x3d,0xa8,0x8e,
-0x1e,0x02,0xab,0x83,0x70,0x5e,0x86,0xdd,0x4a,0xae,0x45,0xe7,0xa9,0xac,0xbf,0x13,
-0x0a,0xc3,0xd7,0xe0,0xf9,0x53,0xb4,0xeb,0xa1,0x74,0xec,0x6b,0x66,0xc8,0x31,0x83,
-0xa6,0x11,0xf5,0x06,0x1a,0xd6,0x43,0xe7,0x79,0xbb,0x52,0x4d,0x3e,0x32,0x58,0x57,
-0x2d,0x69,0x11,0xa3,0x54,0xd1,0xa8,0xb9,0xe3,0x9c,0xd9,0x97,0xa7,0xda,0x77,0xf1,
-0x23,0xd5,0x45,0xd3,0x3d,0x95,0x89,0xe3,0x37,0xbc,0xe1,0xb8,0xa7,0x0c,0x9f,0x5d,
-0x93,0xea,0xf0,0xa4,0x83,0x53,0x07,0xf8,0x78,0x5b,0x70,0x26,0x0b,0xc3,0xf6,0x80,
-0x8f,0x0c,0xcb,0x63,0x61,0x3e,0x32,0x94,0x9d,0x4a,0xd9,0xe7,0x11,0xbd,0xd4,0x3f,
-0xef,0x88,0xec,0x05,0x86,0x73,0x8f,0x38,0xc6,0xd1,0x45,0x6e,0x4e,0x75,0xf6,0x28,
-0xca,0x61,0xe1,0x73,0xe7,0x84,0xed,0x46,0xd1,0x1f,0x4e,0xd6,0x3b,0x0f,0x78,0xc5,
-0xc5,0x59,0x38,0x47,0x27,0x2c,0xef,0x88,0x67,0x1e,0xee,0x02,0x47,0x87,0x77,0x3b,
-0xe9,0xdd,0x3b,0xb5,0x66,0x60,0x3a,0x74,0x71,0x94,0x99,0xda,0x99,0x68,0x1d,0x30,
-0x26,0x0e,0x60,0x0d,0x76,0x26,0x0a,0x38,0x2e,0x60,0x39,0xe1,0x79,0xd2,0xa0,0xad,
-0x33,0xd9,0xf6,0xa0,0x33,0x59,0xe0,0xe1,0xa9,0x56,0x6b,0x57,0xaa,0x15,0xbd,0x73,
-0xf2,0x92,0xe9,0xd2,0x89,0x7e,0x32,0xa2,0xb6,0x1d,0xdc,0xfc,0xfb,0x94,0x9b,0x45,
-0x85,0x51,0x45,0xe1,0x11,0x6a,0xc9,0x33,0x4a,0xd9,0x53,0xa3,0x7a,0xab,0x70,0x8c,
-0x60,0x7f,0x62,0x5f,0x54,0x97,0x6f,0xae,0x36,0xde,0xd9,0x62,0xb4,0x77,0x67,0xd8,
-0xed,0xdd,0xdb,0xec,0x8e,0xee,0x0c,0x07,0x30,0x1d,0x38,0xce,0xf3,0xcf,0x29,0x67,
-0xad,0x27,0x4b,0xe0,0xe0,0x59,0x83,0x76,0x53,0x96,0x9d,0x72,0x53,0x85,0xe5,0xe8,
-0xc9,0x76,0x38,0x4d,0xd9,0x02,0xf6,0x67,0x3b,0x81,0xeb,0xa8,0xb7,0x0f,0xf6,0xea,
-0x07,0xcd,0x46,0xbd,0xf9,0xfd,0x77,0x74,0xef,0x67,0x6c,0x8d,0xcc,0x50,0x6a,0x4c,
-0x82,0x78,0x85,0xa2,0x36,0x85,0x9f,0x7b,0xe5,0x54,0xca,0x2b,0x96,0xae,0x1c,0x8b,
-0x54,0x77,0xef,0x37,0x38,0x94,0xf9,0x6a,0x98,0x57,0x03,0x9e,0x0f,0x99,0x77,0x0d,
-0xb9,0x2d,0xbb,0xdc,0xbc,0x77,0xce,0xb2,0x58,0xf2,0xdd,0x92,0x27,0x9c,0x85,0xf5,
-0xd0,0x27,0xcc,0x79,0x13,0x13,0xfd,0x79,0x13,0xd0,0xc5,0xf1,0x9a,0x3b,0x30,0x3c,
-0xe0,0xf7,0x2a,0x66,0xb1,0x70,0x0f,0x77,0x69,0xb1,0x2c,0x74,0xd4,0xde,0xa1,0x8b,
-0xa3,0x79,0x35,0x2b,0x9f,0x57,0xdb,0x3f,0xc1,0x7b,0xe6,0x23,0xb6,0xc2,0x11,0xc6,
-0xcf,0x0b,0xc7,0xa0,0x6d,0x87,0x47,0x1c,0xb8,0x39,0xf7,0x88,0x23,0x1f,0x77,0x8e,
-0xe5,0xc0,0x70,0x5b,0x11,0xf1,0x74,0xaa,0xb3,0xdb,0x8a,0xbc,0xd0,0xb9,0xfb,0x6d,
-0x85,0x7e,0xaa,0xb7,0x53,0xef,0xbc,0xc4,0x0b,0x9d,0x3b,0xd3,0xb6,0x97,0x05,0x67,
-0xa6,0x3a,0x83,0xbd,0x5e,0xc7,0x07,0x0f,0x8e,0x5f,0xfc,0x78,0xd7,0xc5,0xcc,0x6d,
-0xd1,0x99,0x1b,0xb9,0x4e,0x2b,0x6b,0x78,0xfc,0xfb,0x9a,0xc8,0x70,0x4d,0x71,0x61,
-0x52,0xf1,0xe5,0x4f,0xf3,0x2f,0x8f,0x59,0xca,0xc6,0x98,0x3f,0x5c,0xd5,0x34,0x7a,
-0xe9,0x98,0x3d,0x47,0xdf,0x1c,0xfc,0x1c,0x33,0xe8,0x8f,0x07,0x0f,0x3c,0xc6,0xbc,
-0xf9,0x92,0xb3,0x6c,0x09,0x35,0xf7,0x79,0xb7,0x88,0xe7,0x02,0x96,0xd3,0x82,0x87,
-0xcc,0x30,0xeb,0x9b,0xf3,0xac,0xd4,0xc5,0xa1,0xf2,0xc5,0x15,0x67,0xd9,0x0a,0x16,
-0xf2,0xd5,0x98,0xe7,0x2b,0xaf,0xb9,0xd7,0x33,0xad,0xbb,0xe8,0xdf,0xce,0x78,0x7a,
-0xcd,0x3c,0xbc,0x5e,0xff,0xc7,0x59,0x4a,0x35,0xf7,0x27,0xee,0xb2,0x27,0xa8,0xb1,
-0x4b,0x1c,0x7d,0xa4,0x76,0x11,0xb9,0xa9,0xc0,0x74,0x6c,0xc9,0xcb,0x9d,0xfa,0xe8,
-0x8d,0xf3,0xac,0x67,0xde,0x18,0xc0,0xf3,0x89,0x06,0xa9,0xe6,0x4e,0xdc,0x9c,0x3c,
-0x5f,0x19,0xa6,0x33,0x8d,0x7b,0x03,0x61,0xb9,0x77,0xa0,0xca,0xfb,0x87,0xe3,0x3b,
-0xfe,0x10,0x1f,0x1d,0x1e,0xcf,0x7b,0x87,0x38,0x47,0x68,0xb6,0x32,0x56,0x95,0x0c,
-0x4c,0x05,0xa6,0xc7,0x6d,0x56,0xc5,0x31,0xcd,0xb4,0x5a,0x93,0x6f,0x48,0xcd,0xbf,
-0x77,0xa3,0xfc,0xde,0xd2,0x64,0xf3,0x12,0xc3,0x74,0xee,0x17,0x17,0xf0,0x79,0x85,
-0xa6,0x7d,0xed,0xfc,0x39,0xeb,0x9d,0x03,0xbf,0x99,0x9f,0x7b,0x0b,0x69,0xe5,0xf0,
-0x1c,0x58,0x6f,0xbe,0x5f,0x6b,0xae,0xae,0xd8,0x5e,0x8d,0xfc,0x56,0xde,0x1f,0xc1,
-0x75,0x13,0x75,0x4d,0xe8,0x4f,0xb8,0x06,0x05,0xb5,0x2f,0xde,0xdb,0x5f,0x77,0x9f,
-0xcb,0x39,0x21,0xdf,0xe7,0xbc,0x36,0xfc,0x7f,0x7c,0xa0,0x9e,0xd3,0xda,0x9a,0xd7,
-0xba,0x30,0x7e,0x6c,0x81,0xe6,0xcf,0xa7,0xf9,0xcc,0x9a,0xdc,0xd3,0x9d,0xe1,0x77,
-0x50,0x1d,0x9e,0x70,0xbc,0x95,0xd5,0xd9,0x25,0x6c,0x6f,0x95,0xf0,0x7c,0x76,0xe4,
-0xb9,0xd9,0xbf,0xbd,0x77,0xe0,0x6f,0x49,0x49,0xb1,0x41,0x59,0x8c,0x72,0xee,0xbb,
-0x86,0x9f,0x73,0x3c,0x4f,0xd4,0x12,0x9e,0xdf,0xbf,0x5e,0x79,0xff,0x4f,0xaf,0xec,
-0xfb,0xd3,0x40,0xe7,0x91,0x81,0xcf,0x3e,0x39,0xf8,0x99,0xc5,0x58,0x6f,0x39,0xfb,
-0x46,0xc1,0xd9,0x9b,0xdf,0x57,0xdc,0xf4,0x39,0x9a,0x7d,0x5b,0xd2,0x04,0x3c,0x97,
-0xd5,0x2c,0xd7,0xed,0x93,0xab,0x64,0x3a,0x38,0xa5,0xa6,0x5d,0xee,0x4f,0x23,0xcb,
-0x1f,0xdb,0xf0,0xdc,0x1a,0xdf,0x1f,0xb2,0xeb,0x9e,0xb2,0xd6,0xc2,0xf7,0x57,0x28,
-0xed,0x7a,0x28,0xbf,0x9c,0x35,0xfc,0x5d,0x5c,0xf2,0xfb,0x10,0xa5,0x4f,0x8c,0x84,
-0xdf,0x11,0x6b,0x31,0x1a,0xfe,0x24,0x92,0xf7,0x3d,0xef,0x97,0xcb,0xfa,0xec,0x9c,
-0x8f,0x4b,0xf3,0x6a,0xbc,0xee,0x2e,0x1c,0x9b,0x38,0x26,0x53,0xe2,0x55,0x29,0xc7,
-0x1a,0x54,0xc7,0x6e,0x5f,0x55,0xdd,0x66,0xdc,0x5b,0x56,0x63,0x07,0xf7,0x6e,0x63,
-0xfa,0x76,0xd2,0xc5,0xc9,0x6a,0xee,0xf2,0x7e,0x39,0x9b,0x3d,0x0f,0x97,0x7d,0x1d,
-0x1e,0xb4,0x24,0x2c,0x17,0x38,0x39,0xcb,0x41,0x8f,0x20,0x2c,0x07,0xa6,0x13,0x47,
-0x07,0x37,0xa7,0xfa,0xba,0xa6,0x9f,0x6b,0xde,0x29,0x5b,0x0d,0x9e,0x32,0xed,0xcc,
-0x53,0x06,0x39,0x6b,0xc0,0x76,0xde,0x3f,0x0f,0xe4,0xb0,0xa0,0xee,0xce,0x7a,0xe7,
-0xbc,0xe6,0x4e,0x3a,0x38,0xf2,0x71,0x0f,0xe6,0xe6,0xd0,0xc4,0xa1,0x77,0x8e,0x4c,
-0x16,0x9e,0xcb,0x02,0x1c,0xb7,0x19,0x13,0x6d,0x7c,0x0d,0x74,0x22,0x37,0x35,0x99,
-0x72,0x53,0x99,0xbe,0x9d,0x7b,0xca,0xe8,0xcc,0xdc,0xeb,0x95,0xfc,0x64,0xba,0xe1,
-0xdf,0xce,0xf2,0xd5,0x8c,0xf7,0xd2,0x8c,0xa7,0x5f,0x89,0x3d,0x9d,0xa8,0x0d,0x4b,
-0x0c,0xa5,0x8b,0xe1,0x35,0x56,0xec,0x1f,0xec,0x0b,0xec,0x07,0x7c,0xf6,0x5b,0x93,
-0xc3,0xb6,0x9e,0x79,0x25,0xee,0x4c,0xef,0x2f,0x5b,0x7b,0x79,0x56,0x2a,0x65,0xa7,
-0xf6,0x6c,0x1f,0x0c,0xcc,0xa0,0x67,0xd9,0x80,0xe5,0xc0,0x74,0xbb,0x69,0xbb,0xdd,
-0xd9,0x93,0xe5,0x74,0x9a,0xb2,0x08,0xc7,0x5d,0xa6,0x6c,0x17,0x30,0x1d,0x78,0x0e,
-0x1d,0x9c,0xb5,0x5b,0x6f,0xfd,0xf2,0xb3,0x8c,0x2f,0xf7,0xee,0xde,0xbc,0x97,0xd7,
-0x05,0x83,0xea,0x4d,0x0a,0x5c,0x0f,0xba,0x57,0x15,0x36,0xe9,0xe9,0x9a,0xf4,0xcf,
-0x3f,0xc9,0xfc,0x9c,0x67,0x9f,0xb3,0x5a,0x7b,0x1e,0xcb,0x59,0x33,0xe7,0xb9,0xc8,
-0xeb,0x15,0xbe,0x32,0xa2,0x97,0x0c,0xf3,0x83,0xdb,0xe5,0xe6,0xf3,0xe7,0xcc,0x47,
-0x66,0xf7,0x10,0x6a,0xee,0xd0,0xc1,0x79,0xcc,0x06,0x8f,0xbf,0x2f,0xc7,0xef,0x33,
-0x1b,0x7c,0xc0,0x74,0x86,0xe5,0xf0,0x6e,0xdf,0xc7,0x3c,0x5f,0x91,0x95,0x2a,0x3c,
-0x47,0xbd,0x1d,0x9c,0x9c,0x7b,0xca,0x8c,0x3e,0xd8,0x4f,0x58,0x8e,0xfe,0x39,0x65,
-0xab,0x09,0x0b,0x9a,0x77,0x70,0x74,0x49,0xe3,0x6e,0x2b,0x0c,0x5a,0xe8,0xa3,0xc3,
-0x23,0x0e,0xdc,0x9c,0xb0,0x5c,0xf4,0x7e,0x65,0x99,0xe7,0x22,0x96,0x0b,0x7c,0x9c,
-0x96,0x80,0xe9,0xc0,0x72,0xdf,0x60,0xa1,0x0f,0x8b,0x74,0xed,0x62,0x16,0x3a,0xcb,
-0x4b,0x2d,0xf1,0xb2,0x39,0xb5,0x40,0xd6,0x1a,0xe1,0xba,0xf3,0x90,0xc4,0xcf,0xf1,
-0xbc,0xe3,0xa7,0x03,0x1d,0x55,0x95,0xba,0xaa,0x8d,0xcc,0x9d,0xf3,0xcf,0x99,0xf7,
-0x3c,0x82,0xee,0xf1,0x50,0xcf,0xd4,0x84,0x45,0xe5,0x1b,0xe2,0xf2,0xcf,0xbf,0x99,
-0x73,0xde,0xde,0x53,0x66,0x47,0xcd,0x9d,0xea,0xec,0xd0,0xbc,0x0f,0x31,0x1d,0x1c,
-0xea,0xec,0xc0,0xf2,0x65,0x47,0xf1,0x32,0xea,0xed,0xe0,0xe6,0xa8,0xb9,0xa3,0xde,
-0x0e,0x2e,0x8e,0xc5,0x67,0xd6,0xc8,0x43,0x66,0x94,0xe9,0xdc,0x31,0xab,0x46,0x75,
-0x77,0x81,0xa3,0x2f,0x0d,0x1d,0x5e,0x42,0x1f,0x9d,0xe3,0x79,0x30,0x47,0x47,0x9e,
-0x5a,0xbd,0x38,0x87,0x5e,0xbd,0x08,0x8e,0x8e,0xd9,0x35,0xd4,0xde,0x57,0xdd,0x15,
-0xab,0xc0,0x71,0xca,0x56,0x1b,0xad,0x23,0x3c,0x47,0xf6,0x39,0xe5,0x9f,0x0b,0x7c,
-0x9d,0x63,0x3a,0x70,0x1b,0x98,0x4e,0x18,0x2e,0x62,0x3a,0xe5,0xa3,0x52,0xfe,0x79,
-0xe3,0xd2,0xf2,0xd8,0x91,0x65,0xee,0xf9,0xba,0x34,0x2e,0x7c,0x3d,0xd1,0xb8,0x3c,
-0xe3,0xae,0x9b,0xf9,0xfb,0x7f,0xed,0xfd,0x7b,0x56,0x46,0x4c,0x16,0x6a,0x88,0x5c,
-0xbf,0xcb,0x6b,0x90,0x54,0x4b,0x14,0xae,0x59,0xf0,0x3e,0x82,0x1e,0x04,0xd7,0x2e,
-0xf2,0x51,0x88,0x89,0x88,0x6b,0x39,0xba,0xa3,0xc5,0xd6,0x53,0x63,0x83,0x2e,0x8e,
-0xea,0xec,0x1e,0x9e,0xaf,0x16,0xec,0x29,0xa3,0xe4,0xea,0xcc,0x27,0x4e,0x36,0x73,
-0x2e,0x7a,0xbf,0xba,0xfb,0xea,0xdd,0xa7,0xfe,0x23,0xe7,0x94,0x36,0x21,0x4a,0x2b,
-0xe7,0x6f,0xd8,0x4f,0x38,0x87,0x71,0x5d,0xc5,0xb5,0x94,0x5f,0x3f,0xf1,0xbe,0xf0,
-0x9e,0x71,0xdd,0x95,0xd7,0x5d,0x7e,0xd3,0x63,0x03,0xbf,0x19,0x1b,0x1b,0x13,0xfb,
-0xe9,0x47,0x65,0x9f,0xae,0x4c,0x3e,0xb7,0x12,0x9c,0xcb,0x12,0xe8,0xa9,0xff,0x4b,
-0x1d,0x1c,0xaf,0xb5,0x43,0xd3,0xee,0x3d,0xb1,0x7a,0xe7,0xbb,0x8a,0x3b,0x79,0x86,
-0xb4,0x3c,0x35,0x8e,0xc4,0x75,0xde,0x93,0x26,0x32,0x52,0x73,0xaa,0xd5,0x70,0x0a,
-0x78,0x7e,0xb2,0x45,0x7f,0x12,0xde,0x49,0x54,0x6f,0xd7,0x26,0x24,0x79,0x07,0x9b,
-0xbc,0xd6,0xf6,0x3a,0xeb,0x8d,0x6b,0x15,0x37,0x7e,0xf8,0xba,0xe2,0x87,0xe2,0x62,
-0x7d,0xf1,0xb5,0x2f,0x0e,0x5f,0xbb,0x7b,0xa3,0xfa,0x6e,0xd7,0xfd,0xda,0x2e,0xbf,
-0xa3,0xd9,0x9f,0x9e,0x96,0x9a,0x2e,0xef,0xef,0xfd,0xcb,0xd9,0x33,0x79,0x8f,0x3b,
-0x94,0x76,0x4d,0x89,0xf7,0x32,0x4f,0x9a,0xa7,0xf1,0x7f,0x39,0xb6,0x3f,0xed,0x33,
-0x0f,0x75,0xdf,0xa1,0xbc,0xbf,0x08,0x55,0x87,0xe7,0xbd,0x82,0x20,0x0d,0x5c,0x88,
-0x3c,0x0f,0x65,0x4e,0x8d,0x52,0x4b,0xa0,0x9c,0x59,0x53,0xce,0xaa,0x81,0x8f,0x73,
-0x3c,0xe7,0xdc,0x9c,0xfc,0x7f,0xa2,0x55,0xda,0x1d,0x5b,0x54,0x3b,0xce,0x9f,0x51,
-0x9d,0xef,0xba,0xa3,0xee,0x82,0xa6,0xdd,0xd2,0xa6,0x16,0xb8,0xb6,0x5a,0xc0,0x54,
-0x95,0x15,0x0b,0x5f,0x03,0xcf,0x79,0xbd,0x1d,0x7a,0x38,0x7a,0xde,0x21,0xab,0xbd,
-0x4b,0x2b,0x5c,0xf4,0x8d,0x0b,0xef,0x65,0x18,0x1e,0xc1,0x9e,0x0b,0xf8,0x0d,0x6e,
-0x0e,0xfc,0x86,0x47,0x1c,0xb0,0x9c,0x72,0xd5,0x28,0x93,0x45,0x63,0xe6,0xfe,0x70,
-0x2c,0x2b,0x95,0x65,0xa6,0x92,0xe7,0xab,0x71,0xb3,0xe4,0x25,0x83,0x2d,0xf3,0x92,
-0x89,0xee,0x93,0x72,0x58,0x64,0xbd,0x73,0x60,0x38,0x9b,0x35,0x8f,0x13,0x57,0xbc,
-0xb4,0x82,0xb3,0xcf,0x59,0x5e,0x2a,0xad,0xce,0x44,0x96,0x9b,0xda,0x99,0x64,0x65,
-0xfe,0x70,0x01,0x1c,0xe7,0x9e,0xaf,0xd0,0xc4,0x61,0x29,0xe7,0xd5,0x80,0xe5,0xdd,
-0x1d,0x69,0xdd,0x1f,0xfc,0x67,0xc2,0x07,0x59,0x59,0x11,0x59,0xa4,0x99,0x91,0x1d,
-0x77,0xdc,0xc3,0x05,0xfb,0x04,0xfb,0x83,0xdf,0x4b,0x81,0x63,0x70,0x3f,0x86,0xac,
-0xad,0xe1,0x59,0x67,0xdf,0x48,0x38,0x6b,0xba,0x97,0x61,0x92,0xe6,0xcf,0x85,0xc5,
-0x7d,0xe1,0x80,0xed,0xa4,0x89,0x33,0x65,0x51,0xad,0x9d,0xe3,0x39,0xab,0xbd,0xb3,
-0x85,0x7a,0xfb,0x83,0x1e,0xfd,0x83,0xab,0x5f,0x6f,0xbb,0x5a,0x56,0x12,0x53,0x16,
-0x15,0x15,0x16,0xa5,0x3c,0x4e,0x43,0xd5,0x94,0x94,0xfd,0x24,0xe1,0xc6,0x32,0xbc,
-0xa4,0x28,0xae,0xe4,0xa7,0x1b,0xfa,0x9f,0x98,0xa6,0x9d,0xe1,0x38,0x3c,0x65,0xe0,
-0xdd,0x8e,0xc5,0xf3,0xcf,0x49,0xcf,0x2e,0xe1,0x3a,0xc7,0xf3,0xfc,0x21,0xf4,0xd0,
-0xc7,0xcd,0x79,0xe3,0x5e,0x73,0x8e,0x77,0xca,0x9c,0x33,0x35,0xdd,0xf7,0xfb,0x69,
-0xbf,0x39,0xd7,0xef,0xe9,0xcf,0xf3,0xa0,0xd6,0x0e,0x4c,0x67,0x5e,0x71,0xfb,0x86,
-0x59,0x3e,0x2a,0xb0,0x1c,0x3a,0xb8,0xbd,0x63,0x23,0x56,0xd4,0xdc,0xf7,0x53,0xed,
-0x1d,0x58,0x8e,0xbc,0x54,0xaf,0x65,0x8f,0x17,0xda,0x76,0xd6,0x47,0x2f,0x18,0x1b,
-0xb1,0x15,0x8c,0x8c,0x0c,0x1c,0x18,0x09,0x60,0xf9,0x81,0x51,0x70,0x75,0xee,0xf7,
-0x3a,0x69,0x2b,0x20,0x1c,0x47,0xdd,0x9d,0xfb,0xbd,0x42,0xeb,0x8e,0xfc,0x73,0xf0,
-0x74,0x96,0xc1,0x02,0x6e,0x0e,0x0d,0x5c,0x91,0x97,0x65,0xa4,0x0a,0x78,0x6e,0x17,
-0xb9,0xb9,0x1d,0x33,0xe8,0x4c,0x0f,0xc7,0x39,0x3a,0x96,0xd7,0x59,0xe6,0x65,0x78,
-0xce,0xbc,0xdb,0x07,0x4c,0xc5,0x03,0xa7,0x5f,0xcb,0x3a,0x1d,0x9f,0xa0,0xd9,0xb0,
-0x57,0x98,0xfc,0xba,0x22,0xbf,0x9e,0xf0,0x63,0x05,0xe7,0xad,0x2e,0x25,0x4a,0x57,
-0x5f,0x9d,0x51,0xff,0xf3,0xad,0xc2,0x9f,0xfd,0x83,0x87,0xfd,0xe0,0xe6,0xf0,0x6f,
-0x67,0x73,0x6a,0xc5,0xcb,0xcb,0x8e,0xa2,0xe5,0x25,0x67,0xc9,0x12,0xd3,0xc3,0x95,
-0xcf,0x61,0x0e,0x1d,0x33,0xe8,0xf0,0x86,0x23,0x3c,0xa7,0x9c,0x54,0x11,0xcf,0xb9,
-0x2e,0x4e,0xe0,0xe8,0xe0,0xe5,0x2b,0xee,0x83,0x2b,0xcb,0xee,0x43,0x54,0x73,0x97,
-0xf0,0x5c,0xc4,0x72,0x9a,0x5d,0x43,0xbd,0x9d,0xea,0xee,0xf5,0xf3,0xcc,0xa7,0x5d,
-0xc0,0xf4,0xa1,0x8a,0x55,0xcc,0xb0,0x3d,0x76,0x97,0x93,0xd6,0x9d,0xea,0xeb,0xe4,
-0xf5,0x5a,0x27,0x71,0x74,0xe2,0xe9,0xa3,0xb5,0xcb,0xdc,0xf7,0x15,0xde,0x32,0xe0,
-0xe8,0xc8,0x40,0x45,0x9d,0x9d,0xcd,0x9b,0x23,0xf3,0x5c,0xc4,0xf4,0x09,0xd6,0x47,
-0x07,0x47,0x9f,0x71,0xd7,0xcf,0x5c,0xba,0x50,0x70,0x29,0xf7,0x77,0x89,0xb9,0xd1,
-0x51,0xea,0x68,0xb9,0xdf,0x18,0x96,0x7c,0x3e,0x84,0xe3,0x3a,0xd7,0x77,0xe2,0x67,
-0x53,0x92,0x36,0xa5,0xbc,0xf6,0x52,0xee,0x6b,0xae,0xfe,0x3a,0x97,0x34,0x83,0xee,
-0x79,0x36,0xd8,0x1b,0xce,0xc7,0xfc,0x5e,0xd9,0xfc,0x79,0x70,0x46,0x2a,0x9f,0x5d,
-0xc3,0xf3,0x31,0x5b,0xe3,0xd8,0xd9,0x33,0xf9,0x67,0x75,0xa9,0x31,0xba,0x88,0x70,
-0x75,0x90,0x26,0x4c,0x8e,0xed,0x74,0x7f,0x2e,0xd6,0xd8,0x48,0x9b,0xb4,0x99,0x79,
-0xaa,0xe0,0xfd,0x11,0xae,0xab,0x7f,0x03,0xae,0x87,0xe8,0xf1,0xae,0xf7,0xc8,0xce,
-0x4a,0xca,0xfe,0xfa,0xd3,0x43,0x5f,0xaf,0x4e,0x3e,0xb7,0xaa,0xe4,0xe5,0x6b,0x75,
-0x71,0xbc,0xae,0xde,0xba,0xa6,0xc6,0xfe,0xc4,0x7f,0xf2,0x49,0xf7,0x2f,0xb5,0xdd,
-0xf0,0xe3,0x8b,0x10,0x1e,0x4f,0xfb,0x37,0x23,0x85,0xc7,0xa9,0x93,0x86,0x53,0x1e,
-0x5b,0x93,0xe7,0x64,0xb3,0xfe,0x24,0xea,0xf2,0xd4,0xa7,0xd3,0x6a,0x13,0xfd,0xf6,
-0x66,0xbf,0x6f,0xf0,0xa8,0xcf,0xd1,0x77,0xc4,0x71,0xee,0x2f,0x7b,0xce,0xc5,0xc6,
-0x6c,0x8e,0x7d,0xf3,0x8d,0xfc,0x37,0x87,0x2c,0x4d,0x43,0x93,0x83,0x47,0x27,0xa7,
-0x9d,0xcd,0xd3,0xc0,0x73,0xf9,0x79,0x20,0xf1,0x64,0xb9,0x0e,0x3d,0x44,0x5f,0x30,
-0x24,0xbe,0xaf,0x33,0x77,0x16,0x0a,0x73,0xd7,0xe5,0xec,0xca,0x9a,0xbc,0x42,0x13,
-0xb7,0xe6,0x6f,0x29,0x66,0xd6,0x42,0x69,0xe1,0x42,0xea,0xdb,0x44,0x7c,0x0f,0xa5,
-0x9f,0x0b,0x55,0x77,0x97,0x78,0xb8,0x6c,0xee,0x3c,0xd4,0xe2,0x9a,0x38,0xf8,0xf5,
-0xe1,0x1e,0x17,0xb5,0x2b,0xcc,0x30,0xe9,0xe2,0x54,0x3a,0xcc,0x22,0xef,0xd6,0xab,
-0x76,0x5f,0x78,0x57,0x75,0xc1,0x74,0x57,0x65,0xb2,0xb4,0xa9,0x2c,0x98,0x3b,0x67,
-0x9a,0x77,0x68,0xde,0x54,0xa4,0x75,0x67,0x3a,0xb9,0x30,0xc9,0x57,0x06,0x73,0x6b,
-0x1c,0xc7,0x81,0xe1,0xa6,0xf6,0x30,0x93,0xa9,0x3d,0xdc,0x64,0xea,0x08,0x67,0x5b,
-0x61,0x71,0x4c,0x27,0xcf,0x76,0xf2,0x7a,0x15,0xbd,0x64,0xe0,0xdb,0xde,0x26,0xce,
-0xa1,0xb7,0x69,0xfa,0x79,0x0e,0x0b,0xaf,0xb7,0xb3,0x19,0xf4,0x28,0xe1,0xf7,0xd8,
-0x8c,0x5a,0x20,0x67,0x6d,0x73,0x70,0xfe,0xb9,0xb8,0xfa,0x3a,0x62,0xa5,0xec,0x73,
-0xee,0xe1,0xce,0x31,0x9d,0xe7,0x9f,0x83,0xa3,0x03,0xcf,0x25,0x3f,0x99,0x4e,0xe6,
-0x0d,0xc7,0x3d,0xdc,0x25,0x2d,0x1c,0xfc,0xdb,0x8d,0xc9,0xa4,0x6b,0xc7,0x02,0xa6,
-0x07,0xe7,0xab,0xa5,0xd1,0xea,0x6e,0xd7,0x75,0x7f,0xfc,0x51,0xe2,0xc7,0x79,0x86,
-0xc8,0x3c,0xe1,0x6c,0x88,0xe0,0xf5,0x1f,0x3a,0xd7,0x05,0x8e,0x81,0x7a,0x1c,0xaf,
-0x8b,0x90,0x7e,0x21,0x2a,0xa0,0x5f,0x90,0xfa,0x22,0x1a,0xd5,0xa6,0x8c,0x2d,0xe1,
-0x19,0xa7,0x5f,0x4e,0x38,0xdd,0xfe,0xd3,0xd6,0x76,0xcc,0xa2,0x73,0x8e,0x4e,0x58,
-0x6e,0x62,0x35,0x77,0x87,0x69,0xbb,0x03,0x75,0x76,0xaa,0xbd,0x0b,0x0b,0xf5,0x76,
-0x60,0xb9,0xab,0x67,0x87,0xcb,0xd6,0x99,0x6d,0xfb,0xe6,0xf3,0x2d,0xdf,0xec,0x7f,
-0x26,0x7a,0xbf,0x26,0x4a,0xad,0x59,0xa3,0xfb,0x90,0xf5,0xf1,0xe4,0xf5,0x26,0x55,
-0xd0,0x0f,0xb1,0x63,0x37,0x26,0x3a,0x2c,0xa6,0xa1,0x36,0xa1,0xa1,0xed,0xb6,0xbe,
-0xcd,0xd9,0x97,0xeb,0x1c,0xea,0xcb,0x19,0x62,0x19,0x6b,0x39,0xa3,0xc3,0xe6,0xdc,
-0x61,0xca,0x4e,0x45,0xae,0x9a,0x59,0xf4,0x7c,0xb5,0x08,0x78,0x2e,0x60,0x39,0x69,
-0xdb,0xfb,0xf3,0x46,0xc6,0xfb,0x0d,0x84,0xe5,0xbe,0xbe,0x1c,0x9f,0xdf,0x0c,0x6e,
-0x9e,0xeb,0xf3,0x9a,0x73,0xbd,0xf0,0x92,0x01,0x9e,0x23,0x63,0x0d,0x1c,0x7d,0xd4,
-0xba,0x67,0x14,0x1e,0xee,0xd8,0x22,0x63,0x6d,0xf8,0xc1,0x33,0xc3,0xc8,0x42,0x07,
-0x3f,0xa7,0xec,0x73,0x0b,0xb0,0x3c,0xdf,0xcb,0x66,0xd1,0x05,0x4e,0xfe,0x00,0x73,
-0xe7,0x07,0x46,0x81,0xe5,0x23,0x36,0xac,0xc2,0x11,0x7c,0x0d,0x5e,0x3e,0x3e,0x70,
-0x60,0x1c,0x8b,0x32,0xd5,0x06,0x80,0xe3,0x2c,0x5b,0x8d,0x69,0xe4,0x98,0x9f,0x0c,
-0x65,0xae,0x61,0x2b,0xe0,0x39,0xb8,0x39,0x7a,0xea,0x1e,0x9b,0xa8,0x6d,0xa7,0xbe,
-0x79,0x09,0xcd,0xac,0x79,0x1c,0x25,0xe4,0x25,0x03,0x9c,0x67,0x33,0x6b,0x65,0x34,
-0xb3,0xe6,0xb7,0x97,0xfa,0xf9,0xdc,0x9a,0xbd,0xaf,0xc4,0xfe,0xce,0x5b,0xfa,0x77,
-0x52,0x53,0x37,0xa5,0x42,0xa7,0xb4,0xc1,0xcb,0xb5,0x5a,0xb9,0x2f,0xe4,0xd7,0x37,
-0xee,0x23,0x48,0xf7,0x80,0x9a,0x70,0xcd,0x4e,0x7d,0xdc,0xce,0x33,0xa7,0x77,0x9e,
-0x31,0xb7,0x15,0x9a,0xfd,0xf6,0x72,0x3f,0x9b,0x53,0x2b,0x5d,0xe4,0x5a,0x38,0x68,
-0xdc,0x31,0xaf,0x46,0x78,0x3e,0x04,0x3c,0x67,0xfc,0x9c,0x2d,0xcc,0x9e,0x57,0xb3,
-0x1c,0x55,0x01,0xd3,0xc9,0xcf,0x55,0xe0,0xe8,0xa8,0xbb,0x2f,0xbb,0x0e,0x2f,0x03,
-0xdb,0x89,0xa3,0x8f,0xd6,0x52,0x9d,0x9d,0xcf,0xad,0x61,0xfe,0x5c,0xca,0x4e,0x15,
-0x78,0x3a,0x30,0x9d,0xe5,0x9e,0x97,0xaf,0xac,0x0e,0x97,0xaf,0x62,0x5e,0x8d,0x3c,
-0x66,0xc6,0xe0,0x31,0x53,0xcf,0x78,0xfa,0x28,0xcf,0x40,0xaf,0x5e,0x05,0x4f,0x67,
-0xf9,0x6a,0x35,0xcb,0xa4,0x73,0xa7,0xbe,0xba,0x80,0xe9,0xa2,0x1e,0x8e,0xf1,0xf4,
-0x26,0x49,0xef,0x3e,0x6d,0xaf,0x99,0xfe,0xec,0xc3,0x7d,0x9f,0xe5,0xec,0x4c,0xcc,
-0x41,0x7d,0x82,0x73,0x1a,0x3e,0xbf,0xa3,0xcc,0xd1,0xe6,0x3c,0x06,0xd7,0x33,0x9a,
-0xd3,0x11,0x16,0xee,0x01,0x74,0x49,0x9b,0x74,0x2f,0xb4,0xfe,0xee,0x05,0xab,0xb1,
-0xc6,0xba,0x34,0xc1,0x6b,0xef,0x2d,0xc1,0x7a,0x38,0x79,0x26,0x0b,0xe7,0xe5,0xe2,
-0xbc,0x1a,0x5e,0x1b,0x79,0xd0,0x30,0xf2,0xe7,0x37,0x76,0xff,0x39,0x25,0x25,0x26,
-0x45,0x5e,0xcb,0x55,0xfa,0x9f,0x28,0xfb,0xe1,0x78,0x8d,0xfb,0x27,0x73,0xee,0x44,
-0xf7,0x23,0x32,0xbe,0xfe,0x6f,0x71,0xf6,0x10,0x0f,0x01,0x49,0xc3,0xb2,0xb3,0x12,
-0xb3,0x2f,0x7c,0x50,0x72,0x61,0x7e,0xe4,0xd9,0xf9,0xc0,0x7c,0x5a,0x00,0xdb,0x03,
-0x3c,0xbd,0x55,0xc1,0xcd,0x59,0x4f,0xfd,0x89,0xff,0xc4,0x93,0x5b,0x3f,0x54,0xde,
-0xda,0xbb,0x27,0x63,0xef,0x46,0xea,0x4b,0x84,0xe7,0x22,0x3f,0x3f,0xd1,0xac,0x3f,
-0x21,0xc0,0x39,0xf5,0x18,0xb4,0xc2,0x63,0xca,0x71,0x74,0xea,0xb1,0xf7,0xc4,0x63,
-0xab,0xb1,0xc1,0x7a,0xf0,0xe0,0xf6,0x83,0xf8,0x9c,0x8a,0x8a,0x32,0x8b,0x2c,0x6d,
-0x0d,0x96,0x55,0xcf,0xf1,0xd5,0x19,0x77,0xcb,0x4c,0x7a,0x5a,0x4a,0xba,0x1c,0x43,
-0x83,0xb0,0x5c,0xd6,0xe7,0x96,0x3e,0xd8,0x50,0x7c,0x3c,0x14,0xa6,0x2b,0x7e,0x37,
-0xa8,0x9e,0xbe,0x0e,0x9f,0x57,0xde,0x27,0x48,0x75,0x7e,0xf9,0xcf,0x85,0x29,0x78,
-0xb7,0x02,0x87,0xd7,0x68,0xe0,0x64,0x19,0x1d,0xeb,0xf9,0xc4,0xad,0xd1,0xbd,0x85,
-0xca,0x9d,0x55,0xcc,0x9d,0xcb,0xb1,0x1d,0xc7,0x3b,0xdd,0xcf,0x0a,0x18,0x0e,0x1e,
-0x8e,0x3e,0x54,0x4a,0x9c,0x2a,0x05,0x18,0x0e,0x7d,0x07,0x7a,0x52,0x7c,0x26,0x19,
-0xaf,0x67,0xe8,0x54,0x19,0x6f,0xbd,0xa1,0x7a,0xcb,0xf8,0x93,0xda,0x18,0xc8,0x4c,
-0x0d,0x60,0x77,0x90,0x57,0x1c,0xcd,0xad,0x85,0x49,0x1e,0x71,0x0c,0xd3,0xc3,0x7b,
-0x19,0xae,0x0b,0x38,0xde,0x11,0xce,0x30,0xbc,0x43,0xee,0x09,0x27,0xac,0x8e,0x08,
-0xc2,0x72,0xb9,0xf7,0x2b,0x9b,0x43,0x17,0xf1,0x5b,0xd8,0x32,0x5f,0x38,0x36,0xaf,
-0x06,0x6d,0x3b,0xe9,0xe2,0x8c,0xc0,0xf3,0x68,0x5a,0x94,0x99,0x8a,0xfc,0x73,0xf2,
-0x6d,0x17,0x33,0xd0,0x25,0x0c,0x87,0x7f,0x0c,0xc7,0xf0,0x78,0x2b,0xcf,0x58,0x63,
-0xde,0x70,0x09,0xfd,0xe6,0xce,0x04,0xe6,0xdf,0x2e,0xcd,0x9c,0x27,0x09,0xbf,0xcf,
-0xf3,0x58,0x92,0x65,0x79,0x2c,0xc9,0x16,0xe2,0xe9,0xa2,0x97,0x4c,0x5f,0x97,0x4e,
-0xf8,0x9d,0x34,0xb6,0x15,0x30,0xbd,0xeb,0xbe,0xae,0xeb,0xc3,0xf7,0x13,0x3e,0xd4,
-0xef,0x88,0xd0,0x47,0x46,0xa8,0xe9,0x3e,0x8c,0x5f,0x8b,0x24,0x8f,0x24,0x4d,0x00,
-0xb7,0xe5,0xb3,0x85,0xca,0xcc,0x40,0x7c,0x3f,0x29,0x21,0x2c,0xa9,0xa1,0x26,0xba,
-0xe1,0xea,0x97,0xba,0xab,0x96,0x8e,0x6d,0x16,0x8e,0xe7,0xbc,0xd6,0xce,0xe6,0xd4,
-0x58,0x1f,0x1d,0xfa,0x76,0x57,0x4f,0x96,0x0b,0x35,0xf7,0xde,0x7b,0xdb,0x7b,0xcf,
-0x9f,0x4b,0x3e,0x9f,0x9e,0x1e,0x99,0x0e,0x7e,0x2d,0xe7,0x7e,0x6b,0x70,0x5c,0xf1,
-0xe0,0xc7,0xbe,0x54,0x3f,0x12,0xef,0x45,0xe2,0x63,0xc3,0xe2,0x1b,0xaa,0xe2,0x1a,
-0x7e,0xbc,0xb6,0xfd,0x47,0xb7,0x29,0xc7,0x0d,0x1c,0x67,0xd9,0x6a,0x06,0x01,0xdb,
-0x0d,0x23,0xd0,0xc1,0x11,0x9e,0x03,0xcb,0x2d,0xbb,0xdc,0xc0,0xf7,0xb1,0x7e,0xc3,
-0xd8,0x84,0x39,0x77,0x62,0xd2,0x9c,0x3b,0xe9,0xed,0xcb,0xf5,0x7a,0xcc,0xb9,0x1e,
-0xd4,0xdb,0x27,0xcd,0x79,0x93,0xa8,0xb5,0x43,0x03,0xc7,0xf2,0x52,0xd9,0xcc,0x1a,
-0xd7,0xb5,0xa3,0x6f,0x0e,0x2c,0x07,0x27,0xa7,0xdc,0x54,0xeb,0x9e,0x09,0x9f,0x25,
-0xdf,0x07,0x3c,0x47,0xdf,0x1c,0x7a,0xb8,0xd1,0x07,0x72,0x1c,0x07,0x37,0x3f,0x20,
-0xd5,0xd8,0x79,0x9d,0x9d,0x71,0xf2,0x03,0x34,0x73,0x4e,0xbe,0x32,0xd0,0xb9,0x53,
-0x5e,0x6a,0xd1,0xb8,0x1c,0xcb,0x59,0xcd,0xbd,0xd0,0x03,0x6e,0x8e,0xbe,0x39,0xf2,
-0xd5,0xc0,0xcf,0x99,0xc7,0x6b,0x09,0xf3,0x70,0x17,0x35,0xee,0x3c,0x8b,0xc5,0x6f,
-0x2f,0xf1,0xc3,0xf3,0x75,0xd2,0x7e,0x70,0xd2,0xda,0x55,0x64,0x7d,0xfd,0x8f,0xd9,
-0xaf,0x6b,0xb5,0x1a,0xad,0x6a,0x63,0x50,0x1e,0xf8,0xb0,0x95,0xb5,0x3e,0xd9,0x7e,
-0xe2,0xc7,0x8f,0x84,0x01,0x02,0x72,0xc4,0xc7,0x46,0xc4,0xe7,0xee,0x8c,0xcb,0x7d,
-0xf5,0x94,0xfe,0xd5,0xb6,0x5b,0x05,0x6d,0x7e,0x4b,0x89,0x7f,0xc1,0x51,0xb6,0xb0,
-0xe0,0x3c,0xb4,0x40,0x3a,0x38,0x77,0x25,0xe1,0x39,0x34,0x70,0xb3,0x43,0x0c,0xc7,
-0x39,0x9e,0x93,0x9f,0x0c,0xd5,0xdb,0x59,0xbe,0xda,0xdc,0x70,0xcd,0x1c,0x32,0xd1,
-0x97,0xdc,0xe5,0x4b,0x8b,0x43,0x15,0x8b,0x6c,0x76,0xad,0x6e,0xee,0xd1,0x58,0x5d,
-0xa0,0xd6,0x3e,0x02,0x2d,0x1c,0xf3,0x78,0xa5,0x4c,0x35,0x81,0xaf,0x13,0x4f,0x1f,
-0xa9,0x26,0x4d,0x3b,0xf8,0x39,0xeb,0x97,0xd7,0x32,0x8e,0x4e,0x79,0x6a,0xb5,0x94,
-0x91,0x0a,0xcf,0xf6,0x5f,0x87,0xca,0x7f,0x7d,0x32,0x5c,0xfe,0x84,0x38,0xfb,0x68,
-0xcd,0x2a,0x34,0xee,0xac,0x77,0xde,0x24,0x5b,0x8d,0x8b,0x73,0x63,0x0d,0x73,0xe6,
-0xf6,0x0a,0xf3,0x4b,0x2f,0xfc,0xfe,0xa5,0xad,0xba,0x98,0xad,0xc0,0x64,0xea,0x43,
-0xcb,0x3c,0x92,0xe5,0x59,0x14,0x41,0x33,0x9f,0xe2,0x35,0x96,0xf3,0x75,0x7e,0x9e,
-0xc5,0xc7,0x44,0xc4,0x17,0x15,0x6c,0x2d,0xfa,0xe1,0x4a,0xe9,0x0f,0xb3,0xc3,0x8d,
-0xb3,0x7c,0x4e,0x8d,0xb6,0x6b,0x3c,0x5f,0xc5,0xfe,0xb9,0xc0,0xd3,0x97,0x26,0x5a,
-0x96,0x7a,0xef,0x55,0xf7,0xd6,0xd7,0xed,0xac,0x17,0x6e,0xb8,0x63,0xd4,0xb2,0x9d,
-0x2a,0xc7,0x80,0x20,0x0d,0x96,0x2a,0x18,0xd7,0xa5,0x7d,0x28,0x9e,0xcb,0xf2,0x73,
-0x5f,0xda,0xa7,0x72,0xbc,0xda,0xe0,0xe1,0xf2,0xd4,0xd7,0x05,0xf4,0x41,0xbf,0xfb,
-0xf9,0x93,0xbb,0x9e,0xb7,0x74,0x1e,0xb1,0x00,0x4f,0xd7,0xe7,0xe9,0xad,0x41,0x3a,
-0x38,0xe0,0xeb,0x7b,0x7f,0x2d,0x7a,0x2f,0x55,0x17,0x9f,0x8a,0x9e,0xfc,0x46,0xde,
-0x0f,0xc7,0x73,0x8f,0xed,0xa8,0xe7,0x64,0xcb,0x4e,0xe2,0xe7,0xf8,0xbe,0x56,0x9b,
-0x20,0xe0,0x79,0xf3,0xd4,0x13,0xdf,0xc9,0x27,0x37,0xbf,0x39,0x7c,0x33,0x39,0x39,
-0x21,0x99,0xbe,0x9f,0x10,0xa7,0xfd,0xee,0xab,0x43,0xdf,0x3d,0xf6,0x9d,0x78,0xcc,
-0xf0,0x9c,0xd5,0xdb,0xe5,0x58,0xcc,0xff,0x9f,0x41,0x3d,0x41,0x05,0xcf,0x90,0xe3,
-0x7e,0x10,0x4e,0x87,0xe2,0xd5,0x0a,0x9e,0xf2,0x54,0xfc,0x0f,0x71,0x3f,0x20,0xff,
-0xd9,0x35,0xf8,0x1c,0xae,0xd0,0xe6,0xa9,0x43,0xf4,0xed,0x15,0xf7,0x00,0xbc,0xee,
-0x2e,0xe7,0xe0,0x41,0x3e,0xae,0x11,0x6b,0x97,0xdc,0x87,0x47,0xea,0x8f,0x8b,0x75,
-0x74,0x2c,0x70,0x71,0xe0,0x35,0xb6,0x98,0xe5,0xe4,0xb3,0x6a,0x74,0x6f,0xab,0xd0,
-0xbb,0x73,0x2c,0x3a,0x54,0xaa,0x3a,0x74,0xe9,0xbf,0xd5,0x97,0x7e,0xbe,0xa5,0xfe,
-0xb9,0xeb,0x9e,0xba,0xab,0xa7,0x8d,0xe5,0xaf,0x31,0x1f,0x19,0xb5,0xe8,0xd9,0xae,
-0xee,0xe3,0xba,0x76,0xae,0x8d,0x93,0xfc,0xe2,0xe0,0x27,0x23,0xfa,0xbd,0x32,0x1c,
-0x0f,0xef,0x97,0xb2,0xd5,0x3a,0x22,0x45,0x5d,0x1c,0x7a,0xe9,0x1a,0xda,0x4a,0x3d,
-0x74,0x69,0x56,0x0d,0x5b,0x01,0xcb,0x89,0xab,0x33,0x4c,0xe7,0x3e,0x32,0xbd,0xc6,
-0x68,0xe1,0x77,0xa2,0xc9,0xb7,0x9d,0x2d,0xf0,0x72,0x96,0xad,0xc6,0x72,0x52,0x63,
-0x2d,0x3c,0xfb,0x7c,0xc0,0x18,0x37,0x00,0x3d,0x1c,0xfc,0x64,0xe0,0xdf,0xde,0xdb,
-0xa9,0xed,0x85,0x16,0x8e,0xe1,0x39,0x7c,0xe2,0x12,0x99,0xae,0x9d,0x3c,0xdc,0x59,
-0x1e,0x8b,0xe4,0xf9,0xda,0x95,0xda,0xc7,0x70,0x3c,0x55,0xf8,0xf9,0x54,0xe1,0xdf,
-0xd5,0xf5,0xf6,0x74,0xe8,0x7a,0x8c,0xf7,0x52,0x8d,0xdf,0x7e,0x9d,0xf4,0xed,0x89,
-0xe3,0x9b,0x4e,0xc4,0xc6,0xa8,0x62,0x69,0x5f,0x45,0x32,0x1c,0x97,0xbc,0x7b,0x22,
-0x45,0x3d,0x83,0x98,0x87,0x23,0xcd,0x26,0x86,0x05,0x1f,0x1f,0xbc,0x4f,0x02,0x8e,
-0xce,0x33,0x6c,0xd3,0x92,0xc3,0xd2,0x9a,0x1b,0x62,0x9a,0x2f,0x5e,0x48,0xb9,0xf8,
-0xe3,0xf7,0x5b,0x7f,0xec,0xfa,0x25,0xb3,0xcb,0xdc,0xbe,0xdd,0xdc,0xdf,0xb1,0x5d,
-0xb8,0x0f,0xca,0xb4,0x98,0xef,0x67,0x9a,0x3b,0x6e,0x6f,0xeb,0xb8,0x7e,0x79,0xcb,
-0xf5,0x73,0x7f,0x49,0x3a,0xb7,0x53,0xaf,0xd9,0x29,0xe7,0x00,0xeb,0x9e,0x1b,0xeb,
-0x5c,0x33,0xf8,0x71,0x88,0xf7,0xc8,0xaf,0x45,0xa8,0x67,0xe2,0x78,0x31,0xe8,0x35,
-0x86,0x77,0xdf,0xd4,0xbd,0xdb,0x7e,0x6b,0x67,0xbb,0xad,0x3b,0xd7,0xe6,0xea,0x35,
-0xb8,0x5c,0x66,0x83,0x8b,0xd7,0xdc,0x31,0xaf,0x36,0x6a,0x36,0x8c,0x8e,0x99,0x0d,
-0x63,0xe3,0x66,0xc3,0x38,0xf0,0x7c,0xc2,0x6c,0xa0,0x85,0x9a,0x3b,0x7a,0xe8,0xe8,
-0xa5,0x07,0x66,0xd6,0x04,0x4e,0x6e,0xc5,0xdc,0xda,0x9e,0x31,0xca,0x4d,0xb5,0xee,
-0x1b,0x1e,0xb2,0x3e,0x33,0x84,0xba,0x3b,0x6a,0xee,0xcc,0xf7,0x75,0xb7,0x17,0x99,
-0xa9,0x98,0x57,0x63,0x9a,0xf7,0x82,0x91,0xe1,0x81,0x82,0xe1,0x91,0x01,0xd4,0xd9,
-0x0b,0x18,0x9e,0xc3,0xef,0xd5,0x56,0x40,0x75,0x76,0x68,0xdc,0x31,0x97,0x0e,0x2c,
-0x1f,0x1b,0x28,0x64,0x33,0x6b,0xa4,0x8d,0xc3,0x5c,0x5a,0xe1,0x38,0xcd,0xa8,0x09,
-0xcf,0x27,0x6c,0xc5,0x13,0x5c,0x1b,0x87,0xef,0x41,0xd7,0x8e,0xc5,0x30,0xbe,0x44,
-0xec,0x9f,0x23,0x2b,0xb5,0x84,0xcd,0xa0,0xdb,0xc5,0x5c,0x35,0xe1,0xb5,0xf1,0x81,
-0xd2,0xf1,0xc1,0x9e,0xe2,0xc1,0x2b,0x9f,0xef,0xba,0xb2,0x77,0x6f,0xf2,0xde,0x8d,
-0xf8,0xc6,0x84,0xfc,0xbc,0x15,0x35,0x3d,0xf9,0x35,0x87,0x9f,0xff,0xb8,0x1e,0xf0,
-0xeb,0x12,0xd7,0xc2,0x90,0xff,0x4c,0x6c,0xa4,0xb6,0xf4,0x99,0xa4,0xd2,0x73,0xaf,
-0x67,0x9f,0xbb,0x73,0x79,0xd7,0x9d,0xbe,0x1f,0x0b,0xfa,0x1c,0x9d,0xa5,0x8e,0xb1,
-0xfe,0xf2,0xb1,0x49,0x5b,0x85,0xf0,0x9e,0x2b,0x84,0xf7,0x5b,0x29,0xdc,0x87,0x54,
-0x79,0xbd,0xf6,0x4a,0xaf,0xd7,0x51,0x25,0xdc,0x8f,0x54,0x7b,0xb0,0xbc,0x8e,0x6a,
-0x2f,0x96,0xdf,0x5e,0xe9,0x9f,0xb6,0x97,0x4f,0x3f,0xb4,0x1f,0x7e,0x38,0xed,0xa8,
-0x9c,0xf6,0x39,0xab,0x7d,0x3e,0x67,0xad,0x6c,0xd5,0xf8,0xa6,0x1c,0xd5,0x53,0xd3,
-0x8e,0xaa,0xe9,0x87,0x8e,0xaa,0x87,0x53,0xce,0xea,0xa9,0x29,0x57,0xed,0xd4,0x94,
-0xb3,0x66,0x6a,0xc6,0x51,0x35,0x33,0x6b,0xaf,0x9c,0x9d,0x71,0x54,0xce,0xe0,0xf9,
-0x43,0x67,0xcd,0xc3,0x69,0x67,0xcd,0xf4,0x8c,0xb3,0x66,0x66,0xc6,0x55,0x33,0x33,
-0xeb,0xac,0x9e,0x9d,0x73,0x94,0xcf,0x2d,0xda,0x0f,0x2f,0x2e,0x38,0xca,0x17,0xe6,
-0x9c,0x95,0x73,0x8f,0x9c,0x55,0x8f,0x1e,0xba,0xeb,0x1e,0x4e,0xb9,0xea,0xa7,0xbc,
-0xf6,0x7a,0xaf,0xbb,0xb7,0xc6,0x7d,0xef,0x7a,0xe9,0xbd,0x53,0x2f,0xe6,0x9c,0x4a,
-0x4b,0x8d,0x4f,0xe3,0x38,0x29,0xe5,0x64,0x87,0x07,0x66,0xcc,0xf9,0x9c,0xb2,0xbc,
-0xc7,0xa8,0xe4,0xca,0x72,0x5c,0xe7,0xf7,0xcd,0xc2,0x45,0x2d,0xb6,0xb8,0x38,0xb3,
-0xf8,0x8b,0x4b,0x85,0x5f,0xd8,0x3a,0xab,0x6d,0xa8,0x0f,0x4f,0xbb,0x9b,0xa6,0xe1,
-0xbf,0x3e,0x3b,0x72,0x74,0x76,0x66,0xf8,0xe8,0x8c,0xdf,0xd1,0xe4,0x1f,0xea,0xab,
-0x1f,0x6a,0xbb,0x79,0xb8,0xed,0xd8,0xb1,0xdc,0x63,0x5a,0x6d,0xbc,0xf6,0xa9,0x27,
-0x89,0xbc,0x57,0x2b,0xd3,0x41,0x29,0x31,0x9a,0xef,0x5b,0xbc,0xc6,0xeb,0x2d,0x3c,
-0x3b,0x43,0x8e,0xeb,0xbf,0xe5,0xd8,0xe1,0x7f,0x7f,0xed,0x31,0xa5,0x56,0xa7,0xa6,
-0x6a,0x53,0x9f,0x7f,0x7e,0xd7,0xf3,0x77,0xbf,0x2f,0xbf,0x3b,0xda,0xdf,0x34,0x3a,
-0x33,0x74,0x6c,0x66,0x61,0xec,0xb9,0x85,0xc5,0x89,0xe3,0x8b,0x0b,0xe3,0xc7,0x17,
-0x1e,0x8d,0x1c,0x7b,0xe4,0xb1,0x35,0x7b,0xcc,0x6d,0xb5,0xe6,0x77,0xde,0x2e,0x78,
-0x47,0xaf,0x4f,0xd7,0x6f,0x14,0xc7,0xf7,0xec,0xce,0xda,0x73,0xe5,0x72,0xf9,0x95,
-0xef,0xfe,0x51,0xf1,0x9d,0xb9,0xeb,0x88,0x19,0x7f,0xd7,0xd4,0x5e,0x6f,0xba,0x76,
-0xb5,0xe2,0xda,0x57,0x5f,0x1c,0xfe,0xaa,0xb4,0x64,0x67,0xa9,0xd7,0x7e,0xd4,0x3b,
-0xe5,0x7e,0x76,0xea,0xb5,0x57,0xf3,0x5e,0x93,0xbf,0xc3,0x17,0x5f,0x34,0xbc,0xe8,
-0x77,0x3e,0xeb,0x9f,0xfa,0xdf,0xee,0x8e,0xb4,0xb7,0x89,0x24,0xeb,0x6e,0x1f,0x09,
-0x24,0x71,0x12,0x87,0x1c,0xc3,0x8a,0x89,0x12,0x62,0x27,0x40,0x08,0x31,0xa0,0x65,
-0x76,0x87,0x4c,0x06,0xb0,0xdb,0x57,0x0e,0x42,0x58,0xb4,0xbb,0x59,0xc1,0x20,0x90,
-0xed,0x1c,0x90,0x39,0x96,0x91,0xf8,0xb6,0x68,0xa5,0xd5,0x80,0x10,0xbb,0x62,0x94,
-0x03,0x12,0x1f,0x39,0x90,0x72,0x27,0x9a,0x0f,0xfb,0x0f,0xf6,0x7f,0x6d,0x55,0xbb,
-0x5f,0xf9,0xd5,0xeb,0x6a,0x67,0x02,0x68,0xb5,0xa2,0xe5,0x52,0xdb,0xee,0xae,0xae,
-0xaa,0x7e,0x55,0xf5,0xee,0xf7,0xfe,0x3d,0xf4,0x9f,0x96,0x96,0x13,0x2d,0xa5,0xfe,
-0x3a,0xf0,0xd9,0x9a,0x33,0xcf,0x8e,0xaf,0xe1,0xf7,0x60,0xe3,0xf5,0x35,0x52,0x0f,
-0xcb,0xc4,0x70,0x3d,0x7a,0x5d,0x21,0x7b,0x77,0xd2,0xc5,0x0b,0x1b,0x3c,0x85,0x0f,
-0x80,0x24,0x7b,0xf7,0x94,0xf5,0xe7,0x98,0x3e,0xa5,0xba,0x74,0xc0,0xe1,0x58,0x96,
-0x0b,0x7a,0x59,0xbe,0x0f,0x43,0x31,0xf5,0xb4,0x55,0xa5,0x1c,0x38,0x5c,0x77,0x8b,
-0x73,0xdc,0x29,0x63,0xd1,0x20,0x5b,0x3a,0x8e,0x5f,0x9a,0x03,0xae,0xe6,0xd8,0x75,
-0x57,0xec,0xc9,0x23,0xd7,0x93,0x9f,0x9e,0x69,0x3f,0xcd,0xbd,0xd4,0xe6,0x96,0x7e,
-0xd6,0x96,0x72,0xaf,0xb5,0x1c,0x3f,0xe7,0xe7,0xb4,0x7c,0x61,0x41,0x2b,0x14,0xe6,
-0x58,0x99,0xd7,0xe5,0x32,0xe7,0x2e,0x14,0xe7,0xf5,0x62,0x7e,0xde,0x93,0xcf,0xcd,
-0xbb,0x73,0xb9,0x79,0x4f,0x6e,0x79,0xde,0xb3,0x0c,0x25,0x37,0xef,0x65,0xbf,0xbd,
-0xcb,0xf9,0x79,0x2f,0x7b,0x86,0xb7,0x60,0x9e,0xe7,0x7d,0xec,0xec,0xcb,0xe7,0x17,
-0x7c,0xac,0x8e,0x8f,0xd5,0xa9,0xca,0xe5,0x16,0xaa,0x72,0xcb,0x0b,0xd5,0xac,0x4e,
-0xf5,0x72,0x6e,0xa1,0x9a,0xfd,0x3e,0x26,0x4a,0x7e,0xe1,0x18,0xab,0x7b,0xbc,0xc0,
-0x4b,0x71,0xe1,0x78,0x71,0x75,0xa1,0x66,0x75,0x75,0xb1,0x66,0x75,0x7d,0xa1,0x76,
-0x7d,0x7d,0xb1,0x66,0xfd,0xdd,0x62,0xcd,0xbb,0xb5,0x85,0xda,0xb5,0xe2,0x62,0x6d,
-0x31,0xbf,0x50,0x97,0xcf,0x2d,0xf8,0x59,0xbd,0xfa,0x5c,0x7e,0xd1,0xcf,0xea,0xd5,
-0x17,0x8a,0x8b,0xfe,0x62,0x71,0xb1,0xbe,0xb8,0xb2,0xd8,0xb0,0x52,0x7c,0x53,0xcf,
-0xbe,0x37,0x14,0x73,0x6f,0x1a,0x73,0xcb,0x8b,0x81,0xe5,0xdc,0x62,0x80,0xdd,0xdb,
-0xc4,0xda,0x0e,0x2c,0xbf,0x9d,0x6b,0x7a,0x3b,0xf7,0xaf,0xc0,0xdc,0x8b,0x7f,0x34,
-0xbc,0x78,0xfa,0x57,0xff,0xd3,0xdb,0xe3,0xd5,0xb7,0xdb,0x5a,0xf4,0x36,0x0c,0x0f,
-0x1b,0x2f,0x41,0x7c,0x0d,0xf1,0xfe,0x03,0x3a,0x75,0x6c,0xe3,0x88,0x79,0x78,0x80,
-0x43,0x4d,0xb5,0x56,0xd3,0xd9,0xee,0xed,0xbc,0xfe,0xd5,0xf1,0xeb,0x13,0x7f,0xa8,
-0x9b,0x78,0x70,0xb7,0xfe,0xc1,0xdd,0x3f,0xf9,0xef,0x26,0x8c,0xda,0x44,0xef,0xd9,
-0xea,0x5e,0xbf,0x5f,0xf7,0x3b,0xed,0x0d,0x36,0x59,0x3a,0xc1,0xf5,0x10,0xe7,0x88,
-0xf2,0x3a,0x10,0x67,0xc8,0xcc,0x9d,0x64,0xe5,0x57,0xa8,0xaf,0xd1,0xea,0xc3,0xe7,
-0x8f,0x87,0xa7,0x1f,0xb4,0x4c,0x3f,0x7f,0xf6,0xf9,0xf3,0xa5,0xd7,0xa7,0x97,0xd6,
-0xde,0x86,0xd6,0x36,0x73,0xa1,0xcd,0x9d,0x42,0xd7,0xce,0x6e,0xa1,0x6b,0x77,0x2f,
-0x1f,0xdc,0xdb,0xcb,0x77,0xed,0xed,0xe7,0x83,0xfb,0x7b,0x85,0xe0,0xde,0x4e,0xbe,
-0x7b,0x67,0xbb,0xd0,0xbd,0xbd,0x55,0xe8,0xd9,0xda,0x2c,0x9c,0xd9,0xdc,0x2a,0x9c,
-0xd9,0xda,0x2e,0xf6,0x6c,0x6f,0x17,0x78,0x39,0xbb,0xbd,0x51,0x3c,0xb7,0xb1,0x51,
-0xec,0xdd,0xe0,0xe7,0xcd,0xe2,0xb9,0xcd,0x9d,0xe2,0xd9,0x9d,0xfd,0x95,0x33,0xfb,
-0x07,0xc5,0x9e,0x83,0xbd,0x95,0xb3,0x7b,0x5b,0xc5,0xde,0xad,0xcd,0x95,0xf3,0x9b,
-0xbc,0x6c,0xac,0xf4,0x6d,0x6c,0xae,0xf6,0x6d,0xf2,0xb2,0xb5,0x72,0x61,0x6b,0x6b,
-0xa5,0x8f,0xd1,0x81,0x7d,0x8c,0xa6,0xec,0x63,0xf4,0x5f,0x1f,0xa3,0xf9,0x2e,0x30,
-0x5a,0xef,0x02,0xa3,0x07,0xfb,0x4b,0x65,0x2d,0xcc,0xe8,0xbb,0xf0,0x0e,0x2f,0xbb,
-0x6b,0xfd,0xbb,0xe6,0x79,0xf5,0xe2,0xee,0xee,0x5a,0x78,0x77,0x6f,0x2d,0xbc,0xb7,
-0xbf,0x1e,0xde,0x3f,0x58,0xeb,0x3f,0xf8,0x65,0xbd,0xff,0x97,0x83,0xb5,0xf0,0xc1,
-0xde,0xda,0x45,0x46,0x03,0xf2,0x72,0x79,0x6f,0x77,0xfd,0xd2,0xee,0xfe,0xfa,0xa5,
-0x7d,0xfe,0x7d,0x7b,0xe5,0xf2,0xf6,0xbb,0xa5,0xf0,0xbb,0x37,0xaf,0xce,0xbf,0x79,
-0xf6,0x34,0xf4,0xec,0xeb,0xc1,0xb6,0xaf,0x19,0xa0,0xde,0x2f,0x47,0x26,0xe2,0x2b,
-0x94,0xd7,0x2c,0x7c,0xce,0xe7,0x8c,0x29,0xd3,0xb5,0x0e,0xe0,0xd9,0xc1,0x96,0x92,
-0xd3,0x58,0x5c,0xb6,0xd6,0x5a,0xaf,0xb5,0x76,0x9c,0x3c,0xde,0x11,0xee,0x6d,0x0a,
-0x47,0xae,0xfd,0x26,0x32,0xf1,0xc7,0x8e,0x89,0xf4,0x83,0xae,0x74,0x36,0x1d,0xcc,
-0x66,0x33,0xe5,0x92,0x4e,0x07,0xd3,0xe9,0x4c,0x28,0x9d,0x4e,0x87,0xd2,0x99,0x4c,
-0x30,0x33,0x99,0x09,0x4e,0x3e,0x9a,0x0c,0x3e,0xfa,0x6e,0xea,0xf4,0x77,0xb3,0x93,
-0x5d,0xb3,0x53,0xd9,0xd0,0x54,0x26,0x1d,0xca,0x64,0xd2,0xdd,0x19,0xf3,0x1e,0x76,
-0xce,0x66,0x42,0xd9,0xe9,0x6c,0x68,0x7a,0x66,0x32,0x38,0x33,0x93,0x0d,0xcd,0x4c,
-0x66,0x42,0x93,0xd9,0x4c,0x77,0x76,0x66,0x32,0x34,0x33,0x3b,0x15,0x9c,0xfd,0x7e,
-0x2a,0xf8,0xfd,0xb7,0x53,0xc1,0x6f,0x1f,0x65,0x43,0x8f,0xa6,0xb2,0xdd,0x53,0xd3,
-0xd9,0xee,0xe9,0xc7,0x93,0xa1,0xc7,0xfc,0xf7,0xec,0x54,0xf7,0xec,0x93,0x99,0xae,
-0x27,0x4f,0x1f,0x9d,0x7e,0xfa,0xe3,0x4c,0xf0,0xc7,0x1f,0xa6,0x83,0x3f,0x3c,0xce,
-0x86,0x1e,0x7f,0xf3,0x97,0xe0,0x37,0xd1,0x48,0x47,0xb4,0xa7,0xbb,0xad,0xe7,0x58,
-0x75,0xd5,0x31,0xd8,0x2f,0xb1,0xbc,0x13,0xf0,0x1f,0xf0,0xe9,0x82,0xcf,0x71,0xcb,
-0x3e,0x42,0x22,0x7f,0x26,0xca,0xe9,0x01,0xb4,0x28,0x94,0xd2,0x7e,0xaa,0x7b,0x4f,
-0x7e,0xd6,0x74,0xf2,0xca,0x6f,0x3f,0xbf,0x32,0x76,0x33,0x34,0x76,0xff,0xfe,0xd9,
-0xfb,0x3c,0xa7,0xc9,0x9d,0x3b,0x3d,0x77,0x06,0x06,0x3a,0x06,0x4e,0x77,0xb6,0x9d,
-0x36,0x73,0x9e,0x1e,0x55,0xc4,0xa2,0xd0,0xcf,0x2a,0x65,0xea,0x08,0xae,0xd8,0xbe,
-0x49,0xc4,0xba,0xc3,0xbe,0x6e,0xef,0x8d,0xe1,0xe5,0xa3,0x9a,0x1d,0x1d,0x9d,0x9f,
-0x75,0x0c,0x0e,0x76,0x0d,0x4e,0xfc,0xf9,0xdc,0xc4,0xc3,0x87,0x7d,0x0f,0xef,0xdd,
-0xeb,0xbd,0x97,0x4c,0x76,0x27,0x7b,0x7b,0x4f,0xf5,0x72,0x9e,0x59,0xd3,0x15,0x36,
-0x6f,0x15,0x8e,0x4b,0x17,0xdb,0x2f,0xe5,0x5f,0x7f,0x95,0x2f,0xfe,0x3c,0x58,0xa4,
-0x65,0xe9,0x9f,0x03,0x4b,0x5f,0x5c,0xe9,0xfc,0xe2,0xd5,0x8b,0x2f,0x5f,0xbd,0xfc,
-0xfb,0xef,0x5f,0x76,0x75,0xb5,0x75,0xe1,0xba,0xed,0xed,0xcd,0xed,0xcf,0xff,0xf6,
-0xbb,0xe7,0xaf,0x5f,0x7e,0xf9,0x9a,0xcb,0xe5,0xa5,0x07,0x93,0x7d,0x49,0x89,0x57,
-0x29,0xde,0x46,0xf5,0xa4,0xeb,0x58,0x26,0x89,0xf1,0x37,0x96,0x05,0x68,0xf6,0x36,
-0xa5,0x3a,0x2e,0xf9,0x79,0xd8,0x7f,0x4e,0xb2,0x5d,0x77,0x90,0xa1,0x57,0xd2,0xa1,
-0xab,0x72,0xa4,0xe1,0x98,0xf7,0x34,0xb7,0x8a,0xf0,0x37,0xaf,0x42,0x32,0x5e,0x8f,
-0x1c,0x57,0xcf,0xa4,0x17,0xdc,0x24,0x97,0x2a,0xf5,0x61,0x47,0x6d,0x40,0x1c,0xb9,
-0xc6,0x5a,0x57,0x63,0xe7,0x29,0x57,0xe7,0xe5,0x7e,0xd7,0xe5,0x6b,0x57,0xb5,0x6b,
-0x91,0x41,0x57,0x84,0x97,0x94,0xe1,0x4a,0x8d,0x24,0x5c,0x23,0x23,0x09,0x6d,0x64,
-0x34,0xa1,0x8d,0xf2,0xf3,0x50,0x5c,0x1b,0x4a,0xc5,0xb5,0x54,0x32,0xa6,0x25,0x13,
-0x86,0x96,0x88,0x1b,0x5a,0x3c,0x11,0xd3,0x12,0xfc,0x37,0x2f,0xa9,0x98,0x96,0xe2,
-0xf7,0x40,0x19,0x8e,0x6b,0xc3,0xfc,0x6c,0xde,0x6f,0xdd,0x97,0x88,0xe9,0xac,0x9e,
-0x1e,0xe7,0x25,0x61,0xb8,0x13,0x09,0x43,0x4f,0x24,0x0d,0x9d,0xd5,0x77,0x27,0x53,
-0x71,0x77,0x2a,0x15,0xd7,0x53,0xc3,0x71,0xf7,0xf0,0x68,0x42,0x1f,0xbd,0x99,0x74,
-0xdf,0x1c,0x4b,0xea,0x63,0xe3,0x29,0xf7,0xf8,0x78,0xca,0x33,0x3e,0x96,0xf4,0x8c,
-0xf1,0xff,0x46,0x13,0x1e,0xd6,0x1f,0x37,0xeb,0x8f,0x87,0x3d,0xdb,0x93,0xe4,0x25,
-0x15,0xf3,0xa4,0x78,0x19,0x8a,0x7b,0x59,0xbb,0xde,0x61,0x7e,0x4e,0xc5,0xbc,0xac,
-0xaf,0x5e,0xd6,0x57,0x5f,0xc2,0x88,0x7a,0x8d,0x68,0xc4,0x17,0x8d,0x46,0x59,0x61,
-0xe7,0x48,0xa4,0x2a,0x72,0xe3,0x86,0xef,0xc6,0xc0,0x55,0xdf,0x40,0xff,0x05,0x4f,
-0x7f,0xfb,0x29,0x77,0x7b,0xcd,0x31,0x57,0x0d,0x8d,0xed,0xe3,0xe8,0x7b,0xa8,0xc9,
-0x67,0x1c,0xe3,0x18,0xc3,0x95,0xc6,0x0b,0xc2,0x32,0x7b,0x41,0x87,0x79,0x4a,0x31,
-0x2f,0x41,0x7f,0x77,0x18,0xdf,0xad,0x3a,0xa8,0x0e,0x09,0xfa,0xc4,0xe9,0x08,0x1c,
-0xa7,0x40,0xc4,0x08,0xb6,0xf4,0x36,0xa6,0xac,0xc1,0xea,0x5f,0x53,0x83,0xa7,0xa9,
-0xef,0x6c,0x4d,0xdf,0xb5,0xab,0x75,0xd7,0x86,0x8d,0xfa,0xe1,0xf1,0xa1,0x86,0xf1,
-0xdb,0x43,0x0d,0xb7,0xc7,0x53,0x0d,0xe3,0xfc,0xfb,0xad,0x54,0xc3,0xad,0xd1,0x44,
-0xe3,0x68,0x2a,0xd6,0xc8,0xde,0x6b,0x80,0xc1,0x32,0xc0,0x60,0xda,0x98,0x1c,0x8a,
-0x07,0xd8,0xbc,0x08,0xa4,0xe2,0x46,0x53,0xdc,0x88,0x06,0x0c,0x5e,0x62,0x46,0x53,
-0x2c,0x19,0x6b,0x4a,0x8e,0x26,0x02,0xa3,0xb7,0x52,0x81,0x5b,0x63,0xa9,0xc0,0xd8,
-0x70,0xbc,0x69,0x38,0x6e,0x9c,0x88,0x1b,0x91,0x26,0x23,0x1a,0x3d,0xc1,0x60,0xd0,
-0x14,0x31,0xcf,0xd1,0x13,0x11,0x5e,0xf8,0xf7,0x98,0xd1,0x1c,0x2b,0x95,0x13,0x31,
-0x7e,0x6f,0x2c,0xda,0x1c,0x33,0xa2,0xcd,0x0c,0x76,0xcd,0x0c,0x76,0xcd,0x51,0x23,
-0xd2,0x6c,0xf0,0xdf,0xfc,0x1e,0x7e,0x36,0x8c,0x16,0x23,0x1e,0x6d,0x61,0xf3,0xb0,
-0x25,0xc1,0xcb,0x50,0xbc,0x79,0x68,0x24,0xd1,0x32,0x92,0x8a,0xb7,0xa4,0xe2,0xb1,
-0x56,0x36,0xcf,0x5a,0x58,0x9f,0x5a,0x58,0x9d,0x56,0x23,0x6e,0xb0,0xdf,0xd1,0xd6,
-0x78,0x24,0xd2,0x1a,0x19,0xb8,0xda,0x3c,0x10,0xee,0x6b,0x0c,0x9f,0x6c,0xab,0x39,
-0xf9,0x6b,0xe2,0xb2,0x1f,0xfa,0xfe,0x1d,0xf0,0x39,0xe6,0xcf,0x61,0x9f,0x87,0x6b,
-0x30,0x67,0x4c,0x9c,0xc0,0xce,0x7c,0xad,0x83,0xbf,0x14,0xa7,0xd7,0x21,0x66,0x2f,
-0x8e,0x17,0x84,0xfd,0x67,0xa8,0xee,0xc5,0xf4,0x23,0xb6,0x7c,0xbb,0x4d,0x3f,0x6a,
-0x06,0x5f,0xc1,0x33,0x22,0x99,0x0e,0xd8,0x94,0xf3,0xf9,0xc0,0xe7,0x81,0x29,0x07,
-0xe7,0xf1,0x3e,0x2d,0xd9,0x8d,0xc9,0x2f,0x1c,0xb3,0xec,0xba,0xad,0xf9,0x0a,0xfb,
-0x0f,0xff,0xbf,0xd5,0xef,0x6a,0x35,0xf3,0x03,0x30,0xda,0x83,0xf7,0x95,0xb7,0xc7,
-0xfb,0x88,0xc7,0x86,0xf7,0x4c,0xc0,0xe9,0x62,0x6f,0xb4,0xe4,0x99,0x5c,0xe7,0x80,
-0x7d,0x80,0x6d,0x31,0x45,0x74,0xd9,0x56,0x1a,0xe8,0x1e,0x9c,0xdb,0x4b,0xc8,0xc7,
-0x3f,0xf2,0x61,0xf6,0xdf,0xa5,0xb6,0x9f,0x56,0xc1,0xd7,0x94,0x81,0x11,0x3b,0x66,
-0x88,0x3b,0x75,0x54,0x59,0xfc,0xff,0xf2,0xe0,0x76,0x72,0xb5,0x0e,0x47,0x0d,0x3b,
-0xf8,0xf5,0x7a,0xbf,0x9f,0x7d,0xea,0xfc,0x3a,0x87,0x14,0x3a,0xb8,0x0c,0xa0,0xae,
-0xb6,0xb6,0x8e,0x5f,0xff,0x55,0x76,0x26,0x18,0xe7,0x62,0xdc,0x4b,0xf5,0xe3,0xe5,
-0xdb,0x25,0x1c,0x4f,0xff,0x57,0xc9,0xc1,0xc4,0x77,0x2c,0x23,0x20,0xf8,0xdc,0xec,
-0x3b,0xe2,0xc5,0x6d,0xb4,0x25,0xf5,0x3b,0x27,0x71,0xec,0x95,0x39,0x4e,0x41,0x37,
-0x0e,0x31,0x62,0x7c,0xa5,0xf5,0x82,0xf3,0xd7,0xd8,0x62,0xdc,0x5b,0x38,0x9b,0xe6,
-0x55,0x95,0x6c,0xed,0x90,0x3d,0xbc,0xc8,0xa3,0xea,0x53,0xe4,0x70,0xf1,0xd9,0xf3,
-0xb8,0x80,0x5d,0x17,0xc4,0xa6,0xc1,0xb1,0xe1,0x81,0x3f,0x15,0xe3,0xf0,0xda,0x63,
-0xf2,0x9b,0x7d,0xf6,0xa0,0x3a,0x28,0xbe,0xbf,0xa4,0x6b,0xc0,0x71,0x6a,0x3d,0x16,
-0x6e,0xb3,0xda,0x17,0x32,0x08,0xcb,0x26,0x80,0x9f,0x81,0x9f,0xe4,0xed,0xa8,0x74,
-0x13,0x12,0x7e,0xb2,0xda,0xc5,0x6b,0x49,0x82,0x39,0xec,0xaf,0x84,0x16,0x93,0x62,
-0x11,0xba,0xed,0xf8,0xdb,0x26,0x93,0xa1,0x78,0x1c,0xf9,0x1f,0x8a,0xd8,0x86,0x7a,
-0x19,0x3e,0x52,0x5c,0x20,0x94,0xdb,0x08,0xcb,0xe8,0x94,0x7c,0x80,0xf3,0xd2,0x90,
-0x65,0x4b,0x88,0xaf,0xa0,0xba,0x7e,0x80,0x0b,0x8e,0xef,0x0f,0x30,0x80,0xfe,0x83,
-0x2c,0x1e,0x74,0x39,0xa6,0xfe,0xc6,0x2a,0x00,0x03,0xfe,0xfe,0xb9,0xee,0x01,0xc6,
-0x09,0x31,0x11,0xcc,0x71,0x68,0xe5,0xd8,0x74,0x26,0x5e,0x61,0x6d,0xf3,0x67,0x99,
-0x3a,0x20,0x86,0x9b,0xf8,0xf3,0x1d,0xfd,0x7d,0x30,0x0f,0xab,0x88,0x5d,0x05,0x78,
-0xc2,0xdc,0xdb,0x71,0x5c,0x3e,0x92,0x7b,0xde,0xcc,0xf9,0xce,0xf5,0x4c,0x96,0xdf,
-0x30,0xce,0xdb,0x05,0xf7,0xc1,0x6f,0xb8,0xfe,0x21,0xf2,0x51,0xa9,0xfb,0x4e,0xcf,
-0xb1,0xc6,0x26,0xfa,0xed,0x2a,0x8f,0x45,0xc8,0xe0,0xad,0x71,0xf3,0x35,0x00,0xf3,
-0x9f,0xd3,0xda,0xa6,0x3d,0x35,0x92,0x0d,0xd9,0x70,0x1d,0x99,0xdb,0x26,0x1f,0xac,
-0x97,0x7c,0xa9,0x81,0x0f,0x80,0x31,0xe2,0xbd,0x91,0xdf,0x07,0xf3,0x83,0xb7,0x01,
-0xef,0x05,0xfc,0xb0,0x41,0x26,0x08,0xf4,0x84,0xf9,0x6e,0x3d,0xe5,0x75,0xce,0xf9,
-0x0c,0x6e,0x97,0x03,0xf8,0x1c,0xf2,0x05,0xf0,0xfb,0xe8,0x5c,0xb6,0xd9,0x8e,0x5b,
-0xba,0x1f,0x58,0x57,0x62,0xce,0x10,0xfe,0xc8,0x29,0x0f,0x36,0x5e,0x73,0x12,0x4e,
-0x47,0x36,0xd2,0xd2,0x1a,0xd1,0x8e,0xb6,0xae,0x6c,0xe0,0x23,0x76,0x56,0x98,0x36,
-0x72,0x9a,0x07,0xd8,0xaf,0x49,0xd0,0x61,0xc0,0xaf,0xbf,0x07,0xbd,0xfe,0xff,0x4a,
-0x0b,0x7c,0xe8,0xa1,0xe2,0xdf,0xe1,0x82,0xf8,0xbf,0xd2,0xfa,0x24,0x57,0x30,0xee,
-0xa6,0x70,0x17,0x3c,0xbc,0x75,0xa8,0xec,0xd9,0xa8,0x2e,0x1d,0xc7,0x95,0x51,0xe1,
-0x71,0xc9,0xd6,0x0d,0x62,0xc4,0x60,0x9c,0x4d,0xfc,0xd6,0x00,0x27,0x50,0x7a,0x41,
-0x65,0x4b,0x2f,0xf8,0x42,0x6f,0x19,0x8f,0x0b,0xff,0x74,0xd0,0xa1,0xfb,0x50,0x8e,
-0x55,0x6f,0xd9,0xa6,0x4b,0xec,0xf7,0x16,0x9e,0x04,0x7c,0xa4,0xca,0xf9,0xa6,0xca,
-0x0f,0x2a,0xc9,0xa3,0x75,0x42,0xdf,0x60,0x39,0x05,0xf1,0xbb,0x03,0x3a,0x02,0x7c,
-0xbb,0x4c,0x1d,0x82,0xb5,0x8f,0x98,0xb2,0x08,0x94,0x8f,0xaf,0x52,0xfb,0x58,0xff,
-0x86,0xd7,0x8d,0x34,0x57,0x34,0x19,0x8f,0x53,0x7c,0xad,0x8c,0x27,0xac,0x13,0x9b,
-0x48,0x82,0xc7,0x29,0x4d,0x45,0xe1,0x63,0xb3,0x75,0xf4,0x94,0xec,0x62,0x61,0x0f,
-0xc2,0xfd,0xa3,0xf3,0xb3,0xd2,0x1e,0x64,0xa3,0x3f,0x11,0xbe,0xc0,0x7a,0x3d,0x29,
-0x6e,0x01,0xd2,0xed,0x60,0xf8,0x08,0xfe,0xcb,0xf2,0xb7,0x03,0xde,0x0c,0x74,0x3a,
-0xa6,0x9f,0x8e,0xaf,0x84,0x57,0xa8,0xbc,0x07,0x64,0xc5,0xb0,0xe6,0x00,0x9f,0x40,
-0x9c,0x10,0xee,0xe7,0x63,0xc6,0xe6,0x06,0xd9,0x83,0x6a,0x2c,0xc0,0xbf,0xe9,0xc4,
-0x26,0x09,0xef,0xe3,0xae,0xf2,0xf3,0x31,0x8e,0x97,0xe2,0x39,0x78,0x4a,0xb9,0xdf,
-0x79,0xc1,0xf4,0x00,0xe6,0x0d,0xa1,0x0f,0x42,0xf6,0xad,0x7f,0x7c,0xbe,0x8e,0x02,
-0x0a,0xf6,0x15,0x8c,0x73,0x00,0x86,0x74,0x1e,0x82,0xbf,0x96,0x14,0x8b,0xdf,0x5a,
-0x37,0x18,0x2f,0xe0,0x42,0xe7,0x0c,0xcc,0x01,0xb0,0x97,0xe5,0x75,0xf1,0x1e,0x07,
-0x07,0xe8,0x61,0x60,0x2d,0xc1,0x9c,0x07,0x9c,0x0e,0x6b,0xd3,0x8c,0x95,0x66,0xb5,
-0x0f,0xeb,0x96,0x9f,0xf9,0x35,0x4e,0xab,0xf1,0xfc,0x7d,0x82,0xfe,0xb0,0xde,0xbd,
-0x4a,0x3e,0x8a,0x71,0xa1,0x64,0x7f,0xa6,0x97,0xe5,0xd9,0x94,0x56,0x76,0xf2,0x41,
-0x82,0xfa,0xd2,0x9a,0xa3,0x32,0x0b,0xcc,0x0b,0x52,0x98,0x1c,0x1d,0x8c,0x4a,0xbe,
-0xcf,0xf1,0xf9,0x40,0xc3,0xa1,0x39,0x8a,0xf7,0x17,0x09,0xef,0x7c,0xe2,0x47,0xa5,
-0x31,0xd2,0x6b,0xe2,0xdd,0x2a,0xf8,0xe9,0xa3,0xd0,0x41,0xb4,0x9e,0x54,0x17,0x78,
-0x07,0x22,0x5f,0xa5,0x78,0x9c,0xf2,0x69,0x38,0x57,0x39,0xd5,0x69,0x63,0x79,0x38,
-0x8d,0xf9,0xea,0x14,0x53,0x4e,0x5c,0x73,0x97,0x68,0x7a,0xa9,0x1d,0x92,0x5b,0x0d,
-0xeb,0x6c,0xa9,0xbd,0x3c,0xa5,0x1f,0x00,0x1f,0xf1,0xe7,0x8a,0xb6,0x08,0x3d,0x62,
-0xc3,0x0b,0x6e,0xd9,0xcf,0x44,0xa5,0x73,0xa0,0xfe,0x77,0x22,0x67,0xbb,0xaf,0x14,
-0xfb,0x86,0xca,0x09,0x20,0xce,0x04,0xa6,0x0d,0x54,0xb6,0x83,0xf8,0x1a,0xdd,0x0f,
-0x24,0x7a,0x8c,0xf0,0xad,0xca,0x9c,0xf4,0x48,0x57,0x67,0xd3,0x99,0x61,0x9e,0x80,
-0xea,0x55,0x14,0x71,0x7d,0x25,0x58,0x91,0x9c,0xf5,0x80,0xc3,0xdf,0xcb,0x6f,0x15,
-0xe6,0xa4,0xcb,0x3e,0x27,0xe9,0x9e,0x81,0xf1,0x2c,0x7d,0x7f,0xd4,0xe6,0x08,0xf6,
-0x67,0x93,0xbe,0x43,0xfa,0x17,0x88,0x63,0x60,0xee,0xe5,0x16,0x7f,0x28,0x62,0x2c,
-0x5b,0x7c,0x3f,0xfc,0x87,0x69,0x27,0x81,0x0b,0x2c,0x3d,0x3d,0x8e,0xc7,0xed,0x38,
-0x62,0x0d,0xc5,0x51,0x56,0xf9,0x91,0xba,0x64,0x1c,0x40,0xe1,0x84,0xe9,0x67,0x98,
-0xdb,0xd0,0x2f,0x1c,0x2b,0x00,0xc6,0x0c,0xf3,0x42,0xc4,0xba,0xff,0x88,0xfb,0xa9,
-0xf2,0x59,0xc0,0x23,0x60,0x1e,0x0f,0xc1,0x10,0xd3,0x19,0xbc,0xbf,0x80,0x27,0xb1,
-0x7c,0x0c,0xe8,0x2f,0x58,0x9f,0x58,0x27,0x8d,0x69,0x42,0x68,0x12,0x9e,0x09,0xf2,
-0x16,0xbe,0xa6,0x54,0x3a,0x60,0xfe,0x1d,0x6c,0x3d,0x60,0xbe,0xc0,0x5c,0x07,0xff,
-0x2c,0xa0,0x8f,0x20,0x4f,0x9f,0x49,0x03,0x58,0xb4,0x29,0x3f,0x83,0x3c,0x07,0xf0,
-0x39,0xf4,0xd9,0xc4,0xe9,0xa4,0x2d,0xca,0xd7,0x0a,0x1a,0x54,0x2b,0x8f,0x89,0xd2,
-0xce,0x4e,0x3c,0x3a,0xa5,0x61,0xb1,0x2e,0x82,0xde,0x83,0xdb,0x73,0x84,0xd3,0x51,
-0xe1,0x8c,0xd6,0x1f,0xde,0x6f,0x9c,0xee,0xc7,0xf4,0x0b,0x96,0x3d,0x7c,0xac,0x3e,
-0x7d,0x6a,0x07,0xa6,0x9f,0x54,0xff,0x2b,0xdf,0x16,0xfd,0xef,0x10,0xde,0xc8,0x86,
-0xb3,0x48,0x8e,0x94,0x8a,0xf1,0x61,0x68,0xdc,0xf6,0x4a,0xba,0x58,0x55,0x6e,0x55,
-0x9d,0xf0,0xfb,0x38,0xb6,0x9c,0x5b,0xb6,0x79,0x53,0xd9,0xc8,0x03,0xcf,0x5d,0xd1,
-0x87,0xae,0x42,0x3e,0x1c,0x9c,0xcb,0x56,0xe8,0xf0,0x48,0xdf,0x9d,0x7c,0xf0,0x44,
-0xbe,0x57,0x24,0xf3,0xc7,0x36,0x00,0x36,0x9f,0x15,0x12,0xbf,0x1e,0xf7,0x81,0xef,
-0x69,0x12,0x9f,0xa3,0xb9,0x28,0xd0,0xca,0x74,0x3e,0xe2,0xb1,0x71,0xcc,0x60,0x47,
-0xbc,0x8d,0x68,0x7f,0x2c,0xbb,0xb6,0xf1,0xf0,0xc8,0xaf,0x41,0xc5,0x2b,0x0a,0xbd,
-0x08,0xc2,0x83,0x92,0xbc,0xd3,0x61,0xbe,0x39,0x4d,0x6c,0x69,0x7e,0x6b,0xe5,0xbd,
-0x04,0xb7,0x2b,0x70,0x36,0x82,0x31,0x2e,0x78,0x0f,0x11,0xf7,0x7b,0xca,0xfe,0x40,
-0x26,0x4d,0x65,0xd9,0xc7,0xc1,0x9e,0x0c,0x3a,0x5b,0x18,0x2b,0x9e,0x13,0x20,0x5b,
-0xc7,0x32,0x50,0xec,0x5f,0x04,0x7c,0xa5,0x84,0xbf,0xe8,0xd0,0xf0,0xbe,0xad,0x28,
-0xf4,0x5e,0x0c,0x2b,0x01,0x17,0xb0,0xf7,0xb3,0x64,0x0c,0x92,0x6c,0x13,0xc9,0x0c,
-0x44,0x7f,0x5d,0x6a,0x3d,0xf6,0x87,0x1e,0x87,0xf1,0x20,0x12,0xae,0x42,0x7b,0x15,
-0x8c,0x03,0xc6,0x0c,0x38,0x92,0xcb,0xce,0x84,0x5c,0x8a,0xd0,0xfc,0x2a,0xbc,0x46,
-0xdb,0x03,0x7d,0x38,0xc8,0xd3,0x71,0x2c,0x41,0x15,0xee,0xc7,0x7a,0x7c,0x78,0x5f,
-0x40,0x83,0x63,0x99,0x1d,0xd8,0xa5,0xe3,0xf5,0x6d,0xca,0xe7,0xad,0xf8,0x55,0x58,
-0x27,0x46,0xe9,0x25,0x1b,0xbd,0xed,0x92,0x61,0x29,0xf1,0xad,0x04,0x67,0x4b,0xfc,
-0x39,0x19,0x37,0xa5,0xb7,0x6d,0xf4,0xa0,0x62,0xdd,0x55,0xc4,0x0b,0x47,0x80,0xb7,
-0xe8,0x8f,0xaa,0x1d,0x55,0x3d,0x18,0x8f,0x22,0x2e,0x19,0x5c,0x7f,0xbf,0x1e,0x7d,
-0xfa,0x87,0xe3,0x3e,0x82,0xf1,0x80,0xe2,0x0e,0xa7,0x7a,0x36,0x7e,0x91,0xea,0x4a,
-0xdd,0xb2,0x5c,0x9c,0xf2,0x80,0xaa,0xf9,0x26,0xc5,0xa9,0xc5,0x78,0xd1,0x2d,0xf3,
-0xb7,0x36,0xfc,0x8a,0x79,0x56,0x07,0xfe,0xd9,0x66,0x7f,0x8d,0x6d,0xb0,0x35,0x24,
-0x13,0xd6,0x91,0xbf,0x95,0xca,0xef,0x8a,0xf2,0xaf,0x24,0xae,0x2e,0x95,0x3d,0x43,
-0xbf,0xa8,0xef,0x3c,0xc8,0x0b,0x84,0x2e,0xd0,0x4d,0xf0,0xa4,0x5e,0xde,0x27,0xa0,
-0x2f,0x70,0xdd,0x51,0x06,0xe3,0x22,0x6b,0x0a,0xad,0x17,0x1b,0x3f,0xa7,0xcb,0xf8,
-0xdb,0xb6,0x47,0x20,0x7c,0x2e,0xe0,0xa4,0x88,0xd7,0x4f,0x9f,0x4b,0x69,0x21,0xb3,
-0xdf,0x88,0xe7,0xf8,0xd0,0x39,0x5c,0x69,0x0f,0x74,0xa2,0xb7,0x30,0xdd,0x86,0xe7,
-0x1a,0xc4,0xe1,0xc2,0xba,0x1f,0x8e,0x3b,0x40,0xe7,0x02,0xf0,0x81,0x31,0xe0,0x67,
-0x01,0x1e,0xc7,0x78,0x10,0xfa,0x61,0xe2,0x72,0x8b,0x97,0x13,0x71,0x36,0x54,0x34,
-0x0c,0x1e,0x1b,0xc6,0xe5,0x64,0xcf,0xc6,0xf7,0xa9,0xf8,0x33,0x0c,0x23,0x90,0x33,
-0x00,0x5f,0x0e,0x78,0x04,0xde,0x15,0x96,0x89,0x00,0xed,0xf1,0xb1,0xe5,0xec,0x87,
-0xe2,0x73,0xc4,0x9b,0x4b,0xf8,0xd4,0x25,0xcb,0x11,0xf8,0xbb,0xc6,0x72,0x34,0xc1,
-0x9b,0x5b,0x70,0x50,0xf2,0xaa,0x8a,0x35,0x81,0xe7,0x07,0xb5,0xb5,0x94,0xfa,0xab,
-0x95,0xef,0x85,0xfd,0x02,0xd3,0x68,0x92,0x6e,0x85,0xf4,0x05,0xdb,0xc4,0xd0,0x58,
-0x2b,0xd0,0xa6,0x4a,0x06,0x22,0x60,0xac,0xc1,0xcb,0x51,0xd8,0x93,0x53,0x3e,0x9c,
-0xd2,0xdd,0x64,0x9e,0x98,0xeb,0xd6,0x85,0x7c,0xcd,0x14,0x38,0xfd,0x43,0x71,0x78,
-0x25,0xf8,0x96,0x01,0x8d,0xe8,0x8c,0x0a,0x3c,0x26,0xde,0xab,0x28,0x5e,0x3f,0x6c,
-0xdd,0xbc,0x57,0xdf,0x3e,0xc1,0x43,0xc2,0xe3,0xe4,0xc2,0x61,0x15,0xf9,0xf1,0x5f,
-0x69,0xd7,0x24,0x79,0xb6,0xa9,0x03,0x00,0x00
-};
-
-#endif	/* _TIZEN_HD_LOGO_H_ */
diff --git a/lib/tizen/tizen_hd_logo_data.h b/lib/tizen/tizen_hd_logo_data.h
deleted file mode 100644
index 95e5f827eb..0000000000
--- a/lib/tizen/tizen_hd_logo_data.h
+++ /dev/null
@@ -1,15 +0,0 @@
-/*
- * (C) Copyright 2012 Samsung Electronics
- * Donghwa Lee <dh09.lee@samsung.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef _TIZEN_HD_LOGO_DATA_H_
-#define _TIZEN_HD_LOGO_DATA_H_
-
-#define TIZEN_HD_LOGO_WIDTH		520
-#define	TIZEN_HD_LOGO_HEIGHT		120
-#define	TIZEN_HD_LOGO_BPP		32
-
-#endif	/* _TIZEN_HD_LOGO_DATA_H_ */
diff --git a/lib/tizen/tizen_logo_16bpp.h b/lib/tizen/tizen_logo_16bpp.h
new file mode 100644
index 0000000000..0057c11f0b
--- /dev/null
+++ b/lib/tizen/tizen_logo_16bpp.h
@@ -0,0 +1,7935 @@
+/*
+ * (C) Copyright 2013 Samsung Electronics
+ * Przemyslaw Marczak <p.marczak@samsung.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+*/
+
+#ifndef __TIZEN_LOGO_16BPP__
+#define __TIZEN_LOGO_16BPP__
+
+#define TIZEN_LOGO_16BPP_WIDTH		452
+#define TIZEN_LOGO_16BPP_HEIGHT		140
+
+/* Center align offsets for word "TIZEN" */
+#define TIZEN_LOGO_16BPP_X_OFFSET	(16)
+#define TIZEN_LOGO_16BPP_Y_OFFSET	(-20)
+
+/* Format: BMP RGB565 16BPP 452x140 */
+unsigned char tizen_logo_16bpp[] = {
+0x42,0x4d,0xa6,0xee,0x01,0x00,0x00,0x00,0x00,0x00,0x46,0x00,0x00,0x00,0x38,0x00,
+0x00,0x00,0xc4,0x01,0x00,0x00,0x8c,0x00,0x00,0x00,0x01,0x00,0x10,0x00,0x03,0x00,
+0x00,0x00,0x60,0xee,0x01,0x00,0x01,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xf8,0x00,0x00,0xe0,0x07,0x00,0x00,0x1f,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x21,0x08,0x86,0x31,0x65,0x29,0x41,0x08,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x21,0x08,0x20,0x00,0x20,0x08,0x20,0x00,
+0x20,0x00,0x20,0x00,0x20,0x00,0x20,0x00,0x20,0x08,0x20,0x00,0x20,0x00,0x20,0x00,
+0x20,0x00,0x21,0x00,0x20,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xaa,0x52,0x34,0xa5,0xb6,0xb5,
+0x96,0xb5,0x34,0xa5,0xd2,0x94,0xef,0x7b,0xeb,0x5a,0x08,0x42,0x04,0x21,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x20,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x61,0x08,
+0x6e,0x6b,0x71,0x8c,0x51,0x8c,0x51,0x8c,0x51,0x8c,0x71,0x8c,0x51,0x8c,0x71,0x8c,
+0x71,0x8c,0x71,0x8c,0x51,0x8c,0x51,0x8c,0x71,0x8c,0x51,0x8c,0x51,0x8c,0x71,0x8c,
+0x71,0x8c,0x51,0x8c,0x8a,0x52,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x28,0x42,
+0x10,0x84,0xb2,0x94,0xb2,0x94,0xd2,0x94,0xb2,0x94,0xd2,0x94,0xb2,0x94,0xb2,0x94,
+0xb2,0x94,0xb2,0x94,0xb2,0x94,0xb2,0x94,0xb2,0x94,0xb2,0x94,0xb2,0x94,0xd2,0x94,
+0xb2,0x94,0xb2,0x94,0xb2,0x94,0xb2,0x94,0xb2,0x94,0xb2,0x94,0xd2,0x94,0xb2,0x94,
+0xb2,0x94,0xb2,0x94,0xb2,0x94,0xb2,0x94,0xb2,0x94,0xb2,0x94,0xd2,0x94,0xd2,0x94,
+0xb2,0x94,0xd2,0x94,0xb2,0x94,0xd2,0x94,0xb2,0x94,0xd2,0x94,0xd2,0x9c,0xd2,0x94,
+0xb2,0x94,0xd2,0x94,0xb2,0x9c,0xd2,0x94,0xd2,0x94,0xd2,0x94,0xb3,0x94,0xd2,0x94,
+0xb3,0x94,0xd2,0x94,0xb3,0x94,0xf3,0x9c,0xf3,0x9c,0xf3,0x9c,0xf3,0x9c,0xf3,0x9c,
+0x92,0x94,0x08,0x42,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xe3,0x18,0x30,0x84,
+0xf3,0x9c,0xf3,0x9c,0xf3,0x9c,0xf3,0x9c,0xf3,0x9c,0xf3,0x9c,0xf3,0x9c,0xf3,0x9c,
+0xf3,0x9c,0xf3,0x9c,0xf3,0x9c,0xf3,0x9c,0xf3,0x9c,0xf3,0x9c,0xf3,0x9c,0xf3,0x9c,
+0xf3,0x9c,0xf3,0x9c,0xf3,0x9c,0xf3,0x9c,0xf3,0x9c,0xf3,0x9c,0xf3,0x9c,0xf3,0x9c,
+0xf3,0x9c,0xf3,0x9c,0x14,0xa5,0x14,0xa5,0x14,0xa5,0x14,0xa5,0x14,0xa5,0x14,0xa5,
+0x14,0xa5,0x14,0xa5,0x14,0xa5,0x14,0xa5,0x14,0xa5,0x14,0xa5,0x14,0xa5,0x14,0xa5,
+0x14,0xa5,0x14,0x9d,0x14,0xa5,0x14,0xa5,0x14,0xa5,0x14,0xa5,0x14,0xa5,0x14,0x9d,
+0x14,0xa5,0x14,0xa5,0x14,0xa5,0x14,0xa5,0x14,0xa5,0x14,0xa5,0x14,0xa5,0x14,0x9d,
+0x14,0xa5,0x14,0xa5,0x14,0xa5,0x14,0xa5,0x14,0xa5,0x14,0xa5,0x14,0xa5,0x34,0xa5,
+0x30,0x84,0x62,0x10,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x21,0x08,0x10,0x84,0x34,0xa5,
+0x34,0xa5,0x34,0xa5,0x34,0xa5,0x34,0xa5,0x34,0xa5,0x34,0xa5,0x34,0xa5,0x34,0xa5,
+0x34,0xa5,0x34,0xa5,0x34,0xa5,0x34,0xa5,0x34,0xa5,0x34,0xa5,0x34,0xa5,0x34,0xa5,
+0x30,0x8c,0x62,0x10,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0xe7,0x39,0x14,0xa5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xd6,0xb5,0xd6,0xb5,
+0xb6,0xb5,0xb6,0xb5,0x75,0xad,0x13,0x9d,0x72,0x94,0x8e,0x73,0x8a,0x52,0xa6,0x31,
+0xa2,0x10,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x08,0x42,0xb2,0x94,0xf3,0x9c,
+0xf3,0x9c,0xf3,0x9c,0xf3,0x9c,0xf3,0x9c,0xf3,0x9c,0xf3,0x9c,0xf3,0x9c,0xf3,0x9c,
+0xf3,0x9c,0xf3,0x9c,0xf3,0x9c,0xf3,0x9c,0xf3,0x9c,0x14,0xa5,0x14,0xa5,0xf3,0x9c,
+0x2c,0x6b,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x92,0x94,0xd7,0xbd,0xd6,0xb5,0xd7,0xb5,0xd7,0xbd,
+0xd7,0xb5,0xd7,0xbd,0xd6,0xb5,0xd6,0xb5,0xd7,0xbd,0xd7,0xb5,0xd7,0xbd,0xd7,0xbd,
+0xd6,0xb5,0xd7,0xbd,0xd6,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xab,0x5a,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0xef,0x7b,0xd7,0xb5,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,
+0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,
+0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,
+0xd7,0xbd,0xd7,0xbd,0xf7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xf7,0xbd,0xd7,0xbd,
+0xf7,0xbd,0xd7,0xbd,0xf7,0xbd,0xd7,0xbd,0xf7,0xbd,0xd7,0xbd,0xf7,0xbd,0xd7,0xbd,
+0xf7,0xbd,0xd7,0xbd,0xf7,0xbd,0xd7,0xbd,0xf7,0xbd,0xd7,0xbd,0xf7,0xbd,0xd7,0xbd,
+0xf7,0xbd,0xd7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xd7,0xbd,0xf7,0xbd,0xd7,0xbd,
+0xf7,0xbd,0xd7,0xbd,0xf7,0xbd,0xd7,0xbd,0xf7,0xbd,0xb6,0xb5,0xc7,0x39,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0xd3,0x9c,0xf7,0xbd,0xf7,0xbd,0xd7,0xbd,0xf7,0xbd,0xd7,0xbd,
+0xf7,0xbd,0xd7,0xbd,0xf7,0xbd,0xd7,0xbd,0xf7,0xbd,0xd7,0xbd,0xf7,0xbd,0xd7,0xbd,
+0xf7,0xbd,0xd7,0xbd,0xf7,0xbd,0xd7,0xbd,0xf7,0xbd,0xd7,0xbd,0xf7,0xbd,0xd7,0xbd,
+0xf7,0xbd,0xd7,0xbd,0xf7,0xbd,0xd7,0xbd,0xf7,0xbd,0xd7,0xbd,0xf7,0xbd,0xd7,0xbd,
+0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,
+0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,
+0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,
+0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,
+0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xf7,0xbd,0x51,0x8c,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x30,0x84,0xf7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,
+0xd6,0xb5,0xd7,0xbd,0xd6,0xb5,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd6,0xbd,0xd7,0xbd,
+0xd7,0xb5,0xd7,0xbd,0xd6,0xbd,0xd6,0xbd,0xf7,0xbd,0x51,0x8c,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0xc3,0x18,0x92,0x94,0x14,0xa5,0xb6,0xb5,0xb6,0xb5,
+0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,
+0xd6,0xb5,0xd6,0xb5,0xd6,0xb5,0xb6,0xb5,0x55,0xa5,0xd3,0x9c,0x30,0x84,0x2c,0x63,
+0x28,0x42,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0xc3,0x18,0x55,0xad,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,
+0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,
+0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0x8a,0x52,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x65,0x31,0xb6,0xb5,
+0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,
+0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,
+0xb6,0xb5,0xb6,0xb5,0xd7,0xbd,0x92,0x94,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x2c,0x63,0xd7,0xbd,0xb6,0xb5,
+0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xd6,0xb5,0xb6,0xb5,0xd6,0xb5,0xb6,0xb5,0xb6,0xb5,
+0xb6,0xb5,0xd6,0xb5,0xb6,0xb5,0xd6,0xb5,0xb6,0xb5,0xd6,0xb5,0xb6,0xb5,0xd6,0xb5,
+0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xd6,0xb5,0xd6,0xb5,0xd6,0xb5,0xd6,0xb5,
+0xd6,0xb5,0xd6,0xb5,0xd6,0xb5,0xb6,0xb5,0xd6,0xb5,0xb6,0xb5,0xb6,0xb5,0xd6,0xb5,
+0xd6,0xb5,0xd6,0xb5,0xd6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xd6,0xb5,0xd6,0xb5,
+0xd7,0xb5,0xd6,0xb5,0xd6,0xbd,0xd6,0xb5,0xd7,0xb5,0xd6,0xb5,0xd7,0xbd,0xd6,0xb5,
+0xd6,0xbd,0xd6,0xb5,0xb6,0xbd,0xd6,0xb5,0xb7,0xb5,0xd6,0xb5,0xb7,0xbd,0xd6,0xb5,
+0xd7,0xb5,0xf7,0xbd,0xae,0x73,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x45,0x29,0x96,0xb5,0xd7,0xbd,
+0xd6,0xb5,0xd6,0xb5,0xd7,0xbd,0xd6,0xb5,0xd7,0xbd,0xd6,0xb5,0xb7,0xbd,0xd6,0xb5,
+0xd7,0xbd,0xd6,0xb5,0xb7,0xb5,0xd6,0xb5,0xb7,0xb5,0xd6,0xb5,0xd6,0xbd,0xd6,0xb5,
+0xb6,0xbd,0xd6,0xb5,0xb7,0xbd,0xd6,0xb5,0xb7,0xbd,0xd6,0xb5,0xb7,0xb5,0xd6,0xb5,
+0xb6,0xbd,0xd6,0xb5,0xd7,0xbd,0xd6,0xb5,0xd7,0xbd,0xd6,0xb5,0xd7,0xbd,0xd6,0xb5,
+0xb7,0xb5,0xd6,0xb5,0xd7,0xbd,0xd6,0xb5,0xb7,0xbd,0xd6,0xb5,0xd6,0xbd,0xd6,0xb5,
+0xb7,0xbd,0xd6,0xb5,0xb7,0xb5,0xd6,0xb5,0xb6,0xb5,0xd6,0xb5,0xd6,0xb5,0xb6,0xb5,
+0xd7,0xb5,0xd6,0xb5,0xd6,0xbd,0xb6,0xb5,0xd7,0xb5,0xb6,0xb5,0xd6,0xb5,0xd6,0xb5,
+0xd6,0xb5,0xd6,0xb5,0xd6,0xb5,0xd6,0xb5,0xd6,0xb5,0xb6,0xb5,0xb6,0xb5,0xd6,0xb5,
+0xd7,0xbd,0x54,0xa5,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x34,0xa5,0xd7,0xbd,0xd6,0xb5,
+0xb6,0xb5,0xd6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,
+0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,
+0xd7,0xbd,0x55,0xad,0x62,0x10,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x10,0x84,
+0xf3,0x9c,0xf3,0x9c,0x96,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,
+0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0x96,0xb5,0xb6,0xb5,
+0xb6,0xb5,0xd6,0xb5,0xb6,0xb5,0xb6,0xb5,0xd6,0xb5,0x91,0x94,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x49,0x4a,0xb6,0xb5,0x96,0xb5,0x96,0xb5,
+0x96,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,
+0x96,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,
+0xd6,0xb5,0x10,0x84,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0xa6,0x31,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,
+0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,
+0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xd6,0xbd,0xb2,0x94,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x21,0x08,0x54,0xad,0xd6,0xbd,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xd6,0xb5,0xb6,0xb5,
+0xb6,0xb5,0xd6,0xb5,0xd6,0xb5,0xd6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xd6,0xb5,
+0xd6,0xb5,0xb6,0xb5,0xd6,0xb5,0xd6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,
+0xd6,0xb5,0xb6,0xb5,0xd6,0xb5,0xd6,0xb5,0xd6,0xb5,0xd6,0xbd,0xb6,0xb5,0xb7,0xb5,
+0xd6,0xb5,0xb6,0xb5,0xd6,0xb5,0xb7,0xb5,0xd6,0xb5,0xd6,0xb5,0xd6,0xb5,0xb6,0xbd,
+0xd6,0xb5,0xd6,0xb5,0xd6,0xb5,0xb6,0xbd,0xd6,0xb5,0xb7,0xbd,0xd6,0xb5,0xb7,0xbd,
+0xd6,0xb5,0xd7,0xb5,0xd6,0xb5,0xd6,0xbd,0xd6,0xb5,0xd7,0xbd,0xd6,0xb5,0xd7,0xbd,
+0xd7,0xb5,0xd7,0xbd,0xd6,0xb5,0xd7,0xbd,0xd6,0xbd,0xf7,0xbd,0xcf,0x7b,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x65,0x29,0xb6,0xb5,0xd7,0xbd,0xd7,0xb5,0xd7,0xbd,0xd6,0xbd,0xd7,0xb5,
+0xd7,0xb5,0xd6,0xb5,0xd6,0xbd,0xd7,0xb5,0xd7,0xbd,0xd7,0xb5,0xd7,0xbd,0xd6,0xbd,
+0xd7,0xbd,0xd6,0xb5,0xd7,0xbd,0xd7,0xb5,0xd7,0xbd,0xd7,0xbd,0xd6,0xb5,0xd7,0xbd,
+0xd6,0xbd,0xd6,0xb5,0xd7,0xbd,0xd7,0xbd,0xd7,0xb5,0xd7,0xbd,0xd6,0xbd,0xd6,0xbd,
+0xd7,0xb5,0xd7,0xbd,0xd6,0xb5,0xd6,0xb5,0xd7,0xb5,0xd6,0xb5,0xd7,0xbd,0xb6,0xbd,
+0xd7,0xb5,0xd7,0xbd,0xd6,0xbd,0xb6,0xbd,0xd7,0xb5,0xd7,0xb5,0xd6,0xbd,0xd7,0xbd,
+0xd7,0xb5,0xb6,0xb5,0xd6,0xb5,0xb7,0xbd,0xd6,0xb5,0xd7,0xb5,0xd6,0xb5,0xb7,0xb5,
+0xd6,0xb5,0xb7,0xbd,0xd6,0xb5,0xd6,0xb5,0xd6,0xb5,0xb7,0xb5,0xd6,0xb5,0xd6,0xbd,
+0xd6,0xb5,0xd6,0xbd,0xd6,0xb5,0xb6,0xb5,0xd7,0xbd,0x54,0xad,0x41,0x08,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x21,0x00,0x34,0xa5,0xd7,0xbd,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,
+0xd6,0xb5,0xb6,0xb5,0xd6,0xb5,0xb6,0xb5,0xd6,0xb5,0xb6,0xb5,0xd6,0xb5,0xb6,0xb5,
+0xd6,0xb5,0xb6,0xb5,0xd6,0xb5,0xb6,0xb5,0xd7,0xbd,0x55,0xad,0xa2,0x10,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x4d,0x6b,0x14,0xa5,0xd3,0x9c,0xf3,0x9c,0x96,0xb5,0xb6,0xb5,
+0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,
+0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,
+0xb6,0xb5,0xd7,0xbd,0xae,0x73,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x49,0x4a,0xb6,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,
+0x96,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,
+0x96,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,0xb6,0xb5,0x10,0x84,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xa6,0x31,0xb6,0xb5,
+0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,
+0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,
+0xb6,0xb5,0xb6,0xb5,0xd7,0xbd,0xb2,0x94,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x4d,0x6b,0xd7,0xbd,0xb6,0xb5,0xb6,0xb5,
+0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,
+0xb6,0xb5,0xb6,0xb5,0xd6,0xb5,0xb6,0xb5,0xd6,0xb5,0xb6,0xb5,0xd6,0xb5,0xb6,0xb5,
+0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xd6,0xb5,0xd6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,
+0xb6,0xbd,0xd6,0xb5,0xd7,0xb5,0xd6,0xb5,0xb6,0xbd,0xb6,0xb5,0xd7,0xb5,0xd6,0xb5,
+0xd6,0xbd,0xd6,0xb5,0xb7,0xb5,0xd6,0xb5,0xb7,0xbd,0xd6,0xb5,0xd7,0xbd,0xd6,0xb5,
+0xd7,0xbd,0xd6,0xb5,0xb6,0xbd,0xd6,0xb5,0xd7,0xbd,0xd6,0xb5,0xd6,0xbd,0xd6,0xb5,
+0xb6,0xbd,0xd6,0xb5,0xb7,0xbd,0xd6,0xb5,0xb6,0xbd,0xd6,0xb5,0xd6,0xb5,0xd6,0xb5,
+0xb7,0xb5,0xf7,0xbd,0xcf,0x7b,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x65,0x29,0xb6,0xb5,0xd7,0xbd,
+0xd6,0xb5,0xd7,0xbd,0xd6,0xbd,0xd7,0xb5,0xd6,0xbd,0xd7,0xbd,0xd6,0xb5,0xd7,0xb5,
+0xd7,0xbd,0xd7,0xb5,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xb5,0xd6,0xbd,0xd7,0xbd,
+0xd7,0xbd,0xd7,0xb5,0xd7,0xbd,0xd6,0xbd,0xd7,0xb5,0xd7,0xbd,0xd6,0xbd,0xd6,0xb5,
+0xd7,0xbd,0xd6,0xbd,0xd6,0xb5,0xd6,0xb5,0xd6,0xb5,0xd7,0xb5,0xd7,0xbd,0xd6,0xb5,
+0xd6,0xb5,0xd7,0xb5,0xd7,0xb5,0xd6,0xbd,0xd7,0xb5,0xd6,0xb5,0xd7,0xbd,0xd6,0xbd,
+0xb6,0xb5,0xd6,0xb5,0xd7,0xbd,0xd6,0xb5,0xb6,0xbd,0xd6,0xb5,0xd7,0xb5,0xd6,0xb5,
+0xd7,0xbd,0xd6,0xb5,0xd6,0xb5,0xd6,0xb5,0xb7,0xbd,0xd6,0xb5,0xb7,0xbd,0xd6,0xb5,
+0xd6,0xb5,0xd6,0xb5,0xb6,0xb5,0xd6,0xb5,0xb7,0xb5,0xd6,0xb5,0xd7,0xb5,0xd6,0xb5,
+0xd7,0xbd,0x55,0xad,0xa2,0x10,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x20,0x00,0x34,0xa5,0xd7,0xbd,0xb6,0xb5,
+0xb6,0xb5,0xd6,0xb5,0xb6,0xb5,0xd6,0xb5,0xb6,0xb5,0xd6,0xb5,0xb6,0xb5,0xd6,0xb5,
+0xb6,0xb5,0xd6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,
+0xd7,0xb5,0x55,0xad,0x82,0x10,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x69,0x4a,0x14,0xa5,0xf3,0x9c,
+0xd2,0x94,0xd3,0x9c,0x96,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,
+0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,
+0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0x96,0xb5,0xb6,0xb5,0xf3,0x9c,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x49,0x4a,0xb6,0xb5,0x96,0xb5,0x96,0xb5,
+0x96,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,
+0x96,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,
+0xb6,0xb5,0x30,0x84,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0xa6,0x31,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,
+0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,
+0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xd7,0xbd,0xb2,0x94,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x41,0x08,
+0x55,0xad,0xd7,0xbd,0xd6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xd6,0xb5,0xb6,0xb5,
+0xd6,0xb5,0xb6,0xb5,0xd6,0xb5,0xb6,0xb5,0xd6,0xb5,0xb6,0xb5,0xd6,0xb5,0xb6,0xbd,
+0xd6,0xb5,0xd7,0xb5,0xd6,0xb5,0xb7,0xbd,0xd6,0xb5,0xd7,0xb5,0xd6,0xb5,0xd6,0xb5,
+0xd6,0xb5,0xb6,0xb5,0xd6,0xb5,0xb6,0xbd,0xd6,0xb5,0xb7,0xb5,0xd6,0xb5,0xb6,0xbd,
+0xd6,0xb5,0xd7,0xb5,0xd7,0xb5,0xd6,0xbd,0xd6,0xb5,0xd6,0xbd,0xd6,0xb5,0xd7,0xbd,
+0xd6,0xbd,0xd7,0xb5,0xd7,0xb5,0xd6,0xbd,0xd6,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xb5,
+0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xb5,0xd6,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xb5,
+0xd7,0xb5,0xd6,0xb5,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xf7,0xbd,0xcf,0x7b,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x65,0x29,0xb6,0xb5,0xd7,0xbd,0xd6,0xbd,0xd7,0xbd,0xd6,0xb5,0xd7,0xbd,
+0xd7,0xbd,0xd7,0xb5,0xd6,0xbd,0xd6,0xbd,0xd6,0xb5,0xd7,0xbd,0xd7,0xb5,0xd6,0xbd,
+0xd6,0xb5,0xd7,0xbd,0xd6,0xb5,0xd6,0xbd,0xd6,0xb5,0xd7,0xb5,0xd6,0xbd,0xd7,0xbd,
+0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd6,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xb5,0xd6,0xbd,
+0xd6,0xb5,0xd7,0xb5,0xd6,0xbd,0xd7,0xbd,0xd7,0xb5,0xd7,0xbd,0xd7,0xb5,0xd7,0xb5,
+0xd6,0xbd,0xd6,0xbd,0xd7,0xbd,0xd6,0xb5,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,
+0xd7,0xbd,0xd7,0xb5,0xd7,0xbd,0xd7,0xb5,0xd6,0xb5,0xd7,0xb5,0xd7,0xbd,0xd6,0xb5,
+0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd6,0xbd,0xd6,0xbd,0xd7,0xbd,0xd7,0xb5,0xd7,0xb5,
+0xd6,0xb5,0xb6,0xbd,0xd6,0xb5,0xd7,0xb5,0xd7,0xbd,0x55,0xad,0xa2,0x10,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x20,0x00,0x34,0xa5,0xd7,0xbd,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,
+0xb6,0xb5,0xd6,0xb5,0xb6,0xb5,0xd6,0xb5,0xb6,0xb5,0xb6,0xb5,0xd6,0xb5,0xd6,0xb5,
+0xd6,0xb5,0xb6,0xb5,0xd6,0xb5,0xb6,0xb5,0xd7,0xb5,0x55,0xad,0xa2,0x10,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x45,0x29,0xf3,0x9c,0x13,0x9d,0xd3,0x9c,0xd2,0x94,0xd3,0x9c,0x96,0xb5,0xb6,0xb5,
+0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,
+0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,
+0xb6,0xb5,0xb6,0xb5,0xf3,0x9c,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x49,0x4a,0xb6,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,
+0x96,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,
+0x96,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,0xb6,0xb5,0x10,0x84,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xa6,0x31,0xb6,0xb5,
+0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,
+0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,
+0xb6,0xb5,0xb6,0xb5,0xd7,0xbd,0xb2,0x94,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x6d,0x6b,0xd7,0xbd,0xd6,0xb5,0xb6,0xb5,0xd6,0xb5,
+0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xd6,0xb5,0xb6,0xb5,0xd6,0xb5,0xd6,0xb5,0xb6,0xb5,
+0xb6,0xb5,0xd6,0xb5,0xd6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xd6,0xb5,
+0xb6,0xb5,0xb6,0xb5,0xd6,0xb5,0xd6,0xb5,0xd6,0xb5,0xd6,0xb5,0xb6,0xbd,0xd6,0xb5,
+0xd7,0xbd,0xd6,0xb5,0xd7,0xbd,0xd6,0xb5,0xb6,0xbd,0xd6,0xb5,0xd6,0xbd,0xd6,0xb5,
+0xd6,0xb5,0xd6,0xb5,0xb7,0xbd,0xd6,0xb5,0xb6,0xbd,0xd6,0xb5,0xb7,0xbd,0xd6,0xb5,
+0xb7,0xb5,0xd6,0xbd,0xb6,0xbd,0xd7,0xb5,0xd6,0xbd,0xd6,0xb5,0xb7,0xbd,0xd7,0xb5,
+0xd7,0xb5,0xd6,0xbd,0xd6,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xb5,0xd7,0xbd,0xd7,0xbd,
+0xd7,0xbd,0xf7,0xbd,0xcf,0x7b,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x65,0x29,0xb6,0xb5,0xd7,0xbd,
+0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xb5,0xd7,0xbd,0xd6,0xbd,0xd7,0xbd,
+0xd6,0xbd,0xd7,0xb5,0xd6,0xb5,0xd7,0xb5,0xd7,0xb5,0xd6,0xb5,0xd6,0xb5,0xd7,0xbd,
+0xd7,0xb5,0xd7,0xbd,0xd6,0xb5,0xd6,0xb5,0xd7,0xbd,0xd7,0xbd,0xd7,0xb5,0xd6,0xbd,
+0xd6,0xb5,0xd7,0xbd,0xd7,0xbd,0xd6,0xbd,0xd6,0xbd,0xd7,0xbd,0xd6,0xb5,0xd7,0xb5,
+0xd7,0xb5,0xd7,0xbd,0xd7,0xb5,0xd6,0xb5,0xd7,0xb5,0xd6,0xbd,0xd7,0xbd,0xd6,0xbd,
+0xd7,0xbd,0xd6,0xbd,0xd6,0xb5,0xd7,0xbd,0xd7,0xb5,0xd6,0xbd,0xd6,0xbd,0xd7,0xb5,
+0xd7,0xbd,0xd6,0xbd,0xd6,0xbd,0xd7,0xb5,0xd6,0xbd,0xd6,0xb5,0xb6,0xb5,0xd6,0xb5,
+0xd7,0xb5,0xd6,0xb5,0xb7,0xb5,0xd6,0xb5,0xd6,0xb5,0xd6,0xb5,0xd6,0xbd,0xd6,0xb5,
+0xd7,0xbd,0x55,0xad,0x82,0x10,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x20,0x00,0x34,0xa5,0xd7,0xbd,0xb6,0xb5,
+0xd6,0xb5,0xd6,0xb5,0xb6,0xb5,0xb6,0xb5,0xd6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,
+0xb6,0xb5,0xd6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xd6,0xb5,
+0xd6,0xbd,0x55,0xad,0x82,0x10,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x71,0x8c,0x34,0xa5,0xf3,0x9c,0xd3,0x9c,
+0xb2,0x94,0xd2,0x94,0x96,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,
+0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,
+0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xf3,0x9c,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x49,0x4a,0xb6,0xb5,0x96,0xb5,0x96,0xb5,
+0x96,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,
+0x96,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,
+0xb6,0xb5,0x10,0x84,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0xa6,0x31,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,
+0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,
+0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xd7,0xbd,0xb2,0x94,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x61,0x08,0x55,0xad,
+0xd7,0xb5,0xd6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xd6,0xb5,0xb6,0xb5,0xd6,0xb5,
+0xd6,0xb5,0xd6,0xb5,0xb6,0xb5,0xd6,0xb5,0xd6,0xb5,0xd6,0xb5,0xd6,0xb5,0xd7,0xbd,
+0xd6,0xb5,0xb7,0xbd,0xd6,0xb5,0xb7,0xb5,0xd6,0xb5,0xd6,0xbd,0xd6,0xb5,0xb6,0xbd,
+0xd6,0xb5,0xd6,0xb5,0xd6,0xbd,0xb6,0xb5,0xd7,0xb5,0xd6,0xbd,0xd6,0xbd,0xd7,0xb5,
+0xd6,0xb5,0xd6,0xb5,0xd7,0xbd,0xd7,0xbd,0xd7,0xb5,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,
+0xd7,0xbd,0xd6,0xbd,0xd6,0xbd,0xd6,0xbd,0xd6,0xbd,0xd7,0xb5,0xd6,0xbd,0xd7,0xb5,
+0xd7,0xbd,0xd7,0xb5,0xd6,0xbd,0xd6,0xb5,0xd7,0xb5,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,
+0xd6,0xb5,0xd7,0xbd,0xd7,0xb5,0xd7,0xbd,0xd6,0xbd,0xf7,0xbd,0xcf,0x7b,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x65,0x29,0xb6,0xb5,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,
+0xd7,0xbd,0xd7,0xbd,0xd7,0xb5,0xd7,0xbd,0xd6,0xb5,0xd7,0xbd,0xd6,0xb5,0xd7,0xbd,
+0xd6,0xb5,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd6,0xbd,0xd7,0xbd,0xd6,0xbd,0xd7,0xbd,
+0xd7,0xbd,0xd7,0xbd,0xd6,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd6,0xbd,0xd7,0xbd,
+0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xb5,0xd7,0xbd,
+0xd6,0xb5,0xd6,0xbd,0xd6,0xb5,0xd7,0xb5,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xb5,
+0xd6,0xb5,0xd7,0xbd,0xd7,0xb5,0xd6,0xb5,0xd6,0xbd,0xd7,0xbd,0xd6,0xbd,0xd6,0xb5,
+0xd6,0xb5,0xd6,0xbd,0xd7,0xb5,0xd6,0xbd,0xd7,0xbd,0xd7,0xb5,0xd7,0xb5,0xd6,0xbd,
+0xd7,0xbd,0xd7,0xb5,0xd6,0xbd,0xd7,0xbd,0xd7,0xbd,0x55,0xad,0xa2,0x10,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x20,0x00,0x34,0xa5,0xd7,0xbd,0xb6,0xb5,0xd6,0xb5,0xd6,0xb5,0xb6,0xb5,0xd6,0xb5,
+0xd6,0xb5,0xd6,0xb5,0xd6,0xb5,0xd6,0xb5,0xd6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,
+0xd6,0xb5,0xd6,0xb5,0xd6,0xb5,0xb6,0xb5,0xd7,0xbd,0x55,0xad,0x82,0x10,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xcf,0x7b,
+0x55,0xa5,0x14,0xa5,0xf3,0x9c,0xd3,0x9c,0xb2,0x94,0xd2,0x94,0x96,0xb5,0xb6,0xb5,
+0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,
+0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,
+0xb6,0xb5,0xb6,0xb5,0xf3,0x9c,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x49,0x4a,0xb6,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,
+0x96,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,
+0x96,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,0xb6,0xb5,0x10,0x84,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xa6,0x31,0xb6,0xb5,
+0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,
+0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,
+0xb6,0xb5,0xb6,0xb5,0xd7,0xbd,0xd2,0x94,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x8e,0x73,0xf7,0xbd,0xb6,0xb5,0xd6,0xb5,0xb6,0xb5,0xb6,0xb5,
+0xd6,0xb5,0xd6,0xb5,0xb6,0xb5,0xd6,0xb5,0xd6,0xb5,0xb6,0xb5,0xb6,0xb5,0xd6,0xb5,
+0xd6,0xb5,0xb6,0xb5,0xb7,0xb5,0xd6,0xb5,0xd7,0xbd,0xd6,0xb5,0xd7,0xbd,0xd6,0xb5,
+0xd7,0xbd,0xd6,0xb5,0xb7,0xbd,0xd6,0xb5,0xb6,0xbd,0xd6,0xb5,0xb7,0xbd,0xd6,0xb5,
+0xd7,0xb5,0xd7,0xb5,0xd7,0xb5,0xd6,0xbd,0xd7,0xbd,0xd7,0xb5,0xd7,0xbd,0xd6,0xbd,
+0xd7,0xbd,0xd7,0xbd,0xd6,0xb5,0xd7,0xb5,0xd7,0xbd,0xd7,0xb5,0xd6,0xbd,0xd6,0xbd,
+0xd7,0xbd,0xd6,0xb5,0xd7,0xb5,0xd6,0xbd,0xd6,0xb5,0xd6,0xbd,0xd7,0xbd,0xd7,0xb5,
+0xd6,0xbd,0xd7,0xb5,0xd7,0xbd,0xd7,0xbd,0xd6,0xbd,0xd7,0xb5,0xd7,0xbd,0xd6,0xb5,
+0xd7,0xbd,0xf7,0xbd,0xcf,0x7b,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x65,0x29,0xb6,0xb5,0xd7,0xbd,
+0xd7,0xbd,0xd6,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd6,0xbd,
+0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xb5,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,
+0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd6,0xbd,0xd7,0xbd,0xd7,0xbd,
+0xd7,0xbd,0xd6,0xbd,0xd7,0xbd,0xd7,0xb5,0xd7,0xbd,0xd7,0xb5,0xd7,0xbd,0xd7,0xbd,
+0xd6,0xbd,0xd7,0xbd,0xd7,0xbd,0xd6,0xb5,0xd7,0xbd,0xd7,0xbd,0xd7,0xb5,0xd6,0xb5,
+0xd6,0xbd,0xd7,0xbd,0xd7,0xb5,0xd7,0xbd,0xd7,0xbd,0xd6,0xbd,0xd7,0xb5,0xd7,0xbd,
+0xd7,0xbd,0xd6,0xbd,0xd6,0xbd,0xd7,0xbd,0xd6,0xbd,0xd6,0xb5,0xd6,0xb5,0xd7,0xb5,
+0xd7,0xb5,0xd6,0xb5,0xd6,0xb5,0xd7,0xbd,0xd7,0xbd,0xd6,0xb5,0xd6,0xb5,0xd6,0xbd,
+0xd7,0xbd,0x55,0xad,0x82,0x10,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x20,0x00,0x34,0xa5,0xd7,0xbd,0xd6,0xb5,
+0xd6,0xb5,0xd6,0xb5,0xd6,0xb5,0xb6,0xb5,0xd6,0xb5,0xb6,0xb5,0xd6,0xb5,0xd6,0xb5,
+0xd6,0xb5,0xb6,0xb5,0xb6,0xb5,0xd6,0xb5,0xb6,0xb5,0xd6,0xb5,0xb6,0xb5,0xd6,0xb5,
+0xd6,0xbd,0x55,0xad,0x82,0x10,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0xeb,0x5a,0x54,0xad,0x34,0xa5,0x13,0x9d,0xf3,0x9c,0xd3,0x9c,
+0xb2,0x94,0xb2,0x94,0x96,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,
+0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,
+0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xd6,0xb5,0xf3,0x9c,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x49,0x4a,0xb6,0xb5,0x96,0xb5,0x96,0xb5,
+0x96,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,
+0x96,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,0xb6,0xb5,0x96,0xb5,
+0xd6,0xb5,0x10,0x84,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0xa6,0x31,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,
+0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,
+0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xd7,0xbd,0xb2,0x94,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x82,0x10,0x75,0xad,0xd7,0xbd,
+0xd6,0xb5,0xd6,0xb5,0xd6,0xb5,0xd7,0xbd,0xd6,0xb5,0xd7,0xbd,0xd6,0xb5,0xd7,0xb5,
+0xd6,0xb5,0xb7,0xbd,0xd6,0xb5,0xd6,0xb5,0xd6,0xb5,0xb7,0xb5,0xd7,0xb5,0xd7,0xb5,
+0xd6,0xbd,0xb7,0xbd,0xd6,0xb5,0xd6,0xbd,0xd7,0xb5,0xd6,0xb5,0xd7,0xbd,0xd6,0xb5,
+0xd6,0xb5,0xd7,0xb5,0xd7,0xbd,0xd7,0xbd,0xd6,0xb5,0xd6,0xbd,0xd6,0xb5,0xd6,0xb5,
+0xd7,0xb5,0xd7,0xb5,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xb5,0xd6,0xbd,0xd6,0xbd,
+0xd7,0xb5,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd6,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,
+0xd7,0xb5,0xd7,0xbd,0xd7,0xb5,0xd7,0xbd,0xd7,0xb5,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,
+0xd6,0xbd,0xd7,0xbd,0xd6,0xbd,0xd7,0xbd,0xd7,0xbd,0xf7,0xbd,0xcf,0x7b,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x65,0x29,0xb6,0xb5,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,
+0xd7,0xbd,0xd7,0xbd,0xd7,0xb5,0xd7,0xbd,0xd6,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,
+0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xb5,0xd7,0xbd,
+0xd6,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd6,0xbd,0xd7,0xbd,0xd7,0xb5,0xd7,0xbd,
+0xd7,0xbd,0xd7,0xbd,0xd7,0xb5,0xd7,0xbd,0xd7,0xb5,0xd7,0xbd,0xd7,0xb5,0xd7,0xbd,
+0xd7,0xb5,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd6,0xb5,0xd7,0xbd,
+0xd7,0xbd,0xd7,0xbd,0xd6,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,
+0xd7,0xb5,0xd7,0xbd,0xd7,0xb5,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd6,0xbd,0xd7,0xbd,
+0xd7,0xbd,0xd7,0xbd,0xd7,0xb5,0xd7,0xb5,0xd7,0xbd,0x55,0xad,0xa2,0x10,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x20,0x00,0x34,0xa5,0xd7,0xbd,0xd7,0xbd,0xd6,0xb5,0xb7,0xbd,0xd6,0xb5,0xd6,0xbd,
+0xd6,0xb5,0xb7,0xbd,0xd6,0xb5,0xb6,0xb5,0xb6,0xb5,0xd7,0xb5,0xd6,0xb5,0xd6,0xb5,
+0xd6,0xb5,0xb6,0xb5,0xd6,0xb5,0xd6,0xb5,0xd7,0xb5,0x55,0xad,0x82,0x10,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xc7,0x39,0x34,0xa5,0x54,0xa5,
+0x34,0xa5,0x14,0xa5,0xf3,0x9c,0xd3,0x9c,0xb2,0x94,0xb2,0x94,0x96,0xb5,0xb6,0xb5,
+0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,
+0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,
+0xb6,0xb5,0xb6,0xb5,0xf3,0x9c,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x8a,0x52,0xb6,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,
+0x96,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,
+0x96,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,0xb6,0xb5,0xef,0x7b,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xa6,0x31,0xb6,0xb5,
+0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,
+0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,
+0xb6,0xb5,0xb6,0xb5,0xd7,0xbd,0xb2,0x94,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x8e,0x73,0xd7,0xbd,0xd6,0xb5,0xd6,0xb5,0xb6,0xb5,0xd6,0xb5,0xd6,0xb5,
+0xb7,0xb5,0xd6,0xb5,0xd6,0xb5,0xb6,0xb5,0xd7,0xb5,0xd6,0xb5,0xb6,0xbd,0xd6,0xb5,
+0xd6,0xb5,0xd6,0xb5,0xb7,0xbd,0xd6,0xb5,0xb7,0xbd,0xd6,0xb5,0xd6,0xb5,0xd6,0xb5,
+0xb7,0xbd,0xd6,0xbd,0xd7,0xbd,0xd7,0xb5,0xd7,0xbd,0xd6,0xb5,0xd7,0xbd,0xd6,0xbd,
+0xd7,0xbd,0xd7,0xbd,0xd7,0xb5,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd6,0xbd,0xd6,0xb5,
+0xd7,0xbd,0xd6,0xbd,0xd6,0xb5,0xd6,0xb5,0xd6,0xb5,0xd6,0xb5,0xd7,0xbd,0xd7,0xb5,
+0xd7,0xb5,0xd7,0xb5,0xd7,0xbd,0xd7,0xbd,0xd7,0xb5,0xd7,0xb5,0xd7,0xbd,0xd7,0xbd,
+0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd6,0xbd,0xd7,0xbd,0xd6,0xbd,0xd7,0xbd,0xd7,0xb5,
+0xd7,0xbd,0xf7,0xbd,0xcf,0x7b,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x65,0x29,0xb6,0xb5,0xd7,0xbd,
+0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd6,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,
+0xd7,0xbd,0xd7,0xb5,0xd7,0xbd,0xd6,0xbd,0xd7,0xbd,0xd7,0xb5,0xd7,0xbd,0xd6,0xbd,
+0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xb5,0xd7,0xbd,0xd6,0xbd,0xd7,0xbd,0xd7,0xbd,
+0xd7,0xbd,0xd6,0xb5,0xd7,0xbd,0xd6,0xbd,0xd7,0xbd,0xd6,0xbd,0xd7,0xbd,0xd7,0xbd,
+0xd7,0xbd,0xd6,0xb5,0xd7,0xbd,0xd6,0xbd,0xd7,0xbd,0xd6,0xb5,0xd7,0xbd,0xd7,0xbd,
+0xd7,0xbd,0xd7,0xb5,0xd7,0xbd,0xd7,0xb5,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,
+0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xb5,0xd7,0xbd,0xd7,0xb5,0xd6,0xbd,0xd7,0xb5,
+0xd6,0xbd,0xd7,0xb5,0xd7,0xbd,0xd7,0xb5,0xd6,0xb5,0xd6,0xbd,0xd6,0xb5,0xd7,0xb5,
+0xd7,0xbd,0x75,0xad,0xa2,0x10,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x20,0x00,0x54,0xa5,0xd7,0xbd,0xd6,0xb5,
+0xb7,0xbd,0xd6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb7,0xb5,0xb6,0xb5,0xd6,0xb5,0xb6,0xb5,
+0xb6,0xb5,0xd6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xd6,0xb5,0xb6,0xb5,0xb6,0xb5,
+0xd7,0xbd,0x55,0xad,0x82,0x10,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x82,0x10,0xf3,0x9c,0x55,0xad,0x34,0xa5,0x14,0xa5,0x13,0x9d,0xf3,0x9c,0xd3,0x94,
+0x92,0x94,0xb2,0x94,0x96,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,
+0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,
+0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xf3,0x9c,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xca,0x5a,0xb6,0xb5,0x96,0xb5,0x96,0xb5,
+0x96,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,
+0x96,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,0xb6,0xb5,0x96,0xb5,0xb6,0xb5,0x96,0xb5,
+0xd6,0xb5,0x10,0x84,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0xa6,0x31,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,
+0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,
+0xd6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xd6,0xb5,0xb6,0xb5,0xd7,0xbd,0xd2,0x94,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x82,0x10,0x75,0xad,0xd7,0xbd,0xb6,0xb5,
+0xd6,0xb5,0xd6,0xbd,0xd6,0xb5,0xd6,0xbd,0xd6,0xb5,0xb7,0xbd,0xd6,0xb5,0xb7,0xb5,
+0xd6,0xb5,0xd6,0xbd,0xd6,0xbd,0xd6,0xb5,0xd7,0xbd,0xd7,0xbd,0xd7,0xb5,0xd7,0xbd,
+0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xb5,0xd7,0xbd,0xd7,0xb5,0xd6,0xbd,0xd7,0xbd,
+0xd6,0xbd,0xd7,0xb5,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xb5,
+0xd7,0xb5,0xd7,0xbd,0xd6,0xbd,0xd7,0xbd,0xd6,0xb5,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,
+0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,
+0xd7,0xb5,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd6,0xbd,0xd7,0xbd,
+0xd7,0xbd,0xd7,0xbd,0xd6,0xbd,0xd7,0xbd,0xd7,0xbd,0xf7,0xbd,0xcf,0x7b,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x65,0x29,0xb6,0xb5,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,
+0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,
+0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,
+0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,
+0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,
+0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,
+0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd6,0xbd,0xd7,0xbd,0xd6,0xbd,0xd7,0xbd,
+0xd6,0xbd,0xd7,0xbd,0xd7,0xb5,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,
+0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0x75,0xad,0xa2,0x10,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x20,0x00,0x34,0xa5,0xd7,0xbd,0xd7,0xbd,0xd6,0xb5,0xd7,0xb5,0xd6,0xb5,0xd7,0xbd,
+0xd6,0xb5,0xb7,0xbd,0xd6,0xb5,0xb6,0xbd,0xd6,0xb5,0xb7,0xb5,0xd6,0xb5,0xd7,0xb5,
+0xd6,0xb5,0xd6,0xb5,0xb6,0xb5,0xb6,0xb5,0xd7,0xbd,0x55,0xad,0xa2,0x10,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x51,0x8c,0x75,0xad,0x55,0xad,0x34,0xa5,
+0x34,0xa5,0x13,0x9d,0xf3,0x9c,0xd2,0x9c,0xb2,0x94,0xb2,0x94,0x96,0xb5,0xb6,0xb5,
+0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,
+0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,
+0xb6,0xb5,0xd6,0xb5,0x13,0x9d,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0xab,0x5a,0xb6,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,
+0x96,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,0xb6,0xb5,
+0x96,0xb5,0x96,0xb5,0x96,0xb5,0xb6,0xb5,0xb6,0xb5,0x0f,0x7c,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xa6,0x31,0xb6,0xb5,
+0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,
+0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xd6,0xb5,
+0xb6,0xb5,0xd6,0xb5,0xd7,0xbd,0xd2,0x94,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0xae,0x73,0xf7,0xbd,0xb7,0xb5,0xd6,0xb5,0xb6,0xbd,0xd6,0xb5,0xd6,0xb5,0xd6,0xb5,
+0xd7,0xbd,0xd6,0xb5,0xd7,0xb5,0xd6,0xb5,0xb6,0xb5,0xd6,0xb5,0xd7,0xb5,0xd6,0xbd,
+0xd6,0xbd,0xd6,0xb5,0xd6,0xbd,0xd7,0xb5,0xd6,0xb5,0xd6,0xbd,0xd7,0xbd,0xd7,0xbd,
+0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd6,0xb5,0xd7,0xb5,0xd6,0xbd,0xd7,0xb5,0xd6,0xbd,
+0xd7,0xbd,0xd6,0xbd,0xd7,0xbd,0xd6,0xbd,0xd7,0xbd,0xd6,0xb5,0xd7,0xbd,0xd7,0xbd,
+0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd6,0xbd,0xd7,0xbd,0xd7,0xb5,0xd7,0xbd,0xd6,0xb5,
+0xd7,0xbd,0xd7,0xb5,0xd7,0xbd,0xd6,0xb5,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,
+0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,
+0xd7,0xbd,0xf7,0xbd,0xcf,0x7b,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x65,0x29,0xb6,0xb5,0xd7,0xbd,
+0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,
+0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,
+0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,
+0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,
+0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,
+0xd7,0xbd,0xd7,0xb5,0xd7,0xbd,0xd6,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,
+0xd7,0xbd,0xd6,0xb5,0xd7,0xbd,0xd7,0xb5,0xd7,0xbd,0xd6,0xb5,0xd7,0xbd,0xd7,0xbd,
+0xd7,0xbd,0xd6,0xbd,0xd7,0xbd,0xd6,0xb5,0xd7,0xbd,0xd6,0xb5,0xd7,0xbd,0xd7,0xbd,
+0xd7,0xbd,0x75,0xad,0x82,0x10,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x20,0x08,0x34,0xa5,0xd7,0xbd,0xd6,0xb5,
+0xd7,0xb5,0xd6,0xb5,0xd6,0xbd,0xd6,0xb5,0xb7,0xbd,0xd6,0xb5,0xb7,0xb5,0xd6,0xb5,
+0xb7,0xbd,0xd6,0xb5,0xb6,0xbd,0xd6,0xb5,0xd6,0xbd,0xb6,0xb5,0xd7,0xb5,0xb6,0xb5,
+0xd7,0xbd,0x75,0xad,0xc3,0x18,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x6d,0x6b,
+0x96,0xb5,0x55,0xad,0x55,0xa5,0x34,0xa5,0x34,0xa5,0x13,0x9d,0xf3,0x9c,0xd2,0x94,
+0x92,0x94,0xb2,0x94,0x96,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,
+0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,
+0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xd6,0xb5,0xf3,0x9c,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xab,0x5a,0xb6,0xb5,0x96,0xb5,0x96,0xb5,
+0x96,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,0xb6,0xb5,0x96,0xb5,
+0xb6,0xb5,0x96,0xb5,0xb6,0xb5,0x96,0xb5,0xb6,0xb5,0x96,0xb5,0xb6,0xb5,0xb6,0xb5,
+0xb6,0xb5,0x10,0x84,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0xa6,0x31,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,
+0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,
+0xd6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xd7,0xbd,0xb2,0x94,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0xc3,0x18,0x75,0xad,0xd7,0xbd,0xd6,0xb5,0xd7,0xbd,
+0xd6,0xbd,0xd6,0xbd,0xd6,0xb5,0xd6,0xbd,0xd7,0xbd,0xd7,0xbd,0xd6,0xb5,0xd7,0xbd,
+0xd7,0xb5,0xd6,0xbd,0xd6,0xb5,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xb5,0xd6,0xbd,
+0xd6,0xbd,0xd7,0xb5,0xd6,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,
+0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd6,0xb5,0xd7,0xbd,
+0xd6,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,
+0xd6,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,
+0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,
+0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xf7,0xbd,0xcf,0x7b,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x65,0x29,0xb6,0xb5,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,
+0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,
+0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,
+0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,
+0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,
+0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,
+0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,
+0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,
+0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0x75,0xad,0xa2,0x10,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x20,0x00,0x54,0xa5,0xd7,0xbd,0xd7,0xb5,0xd6,0xbd,0xd7,0xbd,0xd7,0xb5,0xd7,0xb5,
+0xd7,0xb5,0xd6,0xbd,0xd6,0xb5,0xd7,0xbd,0xd6,0xb5,0xb6,0xbd,0xd6,0xb5,0xb7,0xbd,
+0xd6,0xb5,0xd7,0xbd,0xd6,0xb5,0xb7,0xbd,0xd7,0xbd,0x76,0xad,0x04,0x21,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x69,0x4a,0x76,0xad,0x75,0xad,0x55,0xad,0x54,0xad,0x34,0xa5,
+0x14,0xa5,0xf3,0x9c,0xf3,0x9c,0xb2,0x94,0x92,0x94,0xb2,0x94,0x96,0xb5,0xb6,0xb5,
+0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,
+0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,
+0xb6,0xb5,0xd7,0xbd,0xf3,0x9c,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0xab,0x5a,0xb6,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,
+0x96,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,0xb6,0xb5,0x96,0xb5,0x96,0xb5,
+0x96,0xb5,0xb6,0xb5,0x96,0xb5,0xb6,0xb5,0xd6,0xb5,0x0f,0x7c,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xa6,0x31,0xb6,0xb5,
+0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,
+0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xd6,0xb5,0xb6,0xb5,0xd6,0xb5,
+0xb6,0xb5,0xb6,0xb5,0xd7,0xbd,0xb2,0x94,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xae,0x73,
+0xf7,0xbd,0xd6,0xb5,0xb7,0xb5,0xd6,0xb5,0xd7,0xbd,0xd6,0xb5,0xd6,0xbd,0xd6,0xb5,
+0xb6,0xb5,0xd6,0xb5,0xd7,0xb5,0xd6,0xb5,0xd7,0xbd,0xd6,0xbd,0xd7,0xbd,0xd7,0xbd,
+0xd7,0xbd,0xd7,0xbd,0xd6,0xb5,0xd7,0xbd,0xd6,0xbd,0xd7,0xb5,0xd6,0xb5,0xd7,0xbd,
+0xd6,0xbd,0xd6,0xb5,0xd7,0xb5,0xd7,0xb5,0xd7,0xbd,0xd6,0xb5,0xd7,0xbd,0xd7,0xbd,
+0xd7,0xbd,0xd7,0xb5,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xb5,
+0xd7,0xbd,0xd6,0xbd,0xd7,0xbd,0xd6,0xbd,0xd7,0xbd,0xd7,0xb5,0xd7,0xbd,0xd6,0xbd,
+0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,
+0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,
+0xd7,0xbd,0xf7,0xbd,0xcf,0x7b,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x65,0x29,0xb6,0xb5,0xd7,0xbd,
+0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,
+0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,
+0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,
+0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,
+0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,
+0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,
+0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,
+0xd7,0xbd,0xd7,0xb5,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd6,0xbd,0xd7,0xbd,0xd7,0xb5,
+0xd7,0xbd,0x75,0xad,0x82,0x10,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x21,0x00,0x54,0xa5,0xd7,0xbd,0xd7,0xbd,
+0xd7,0xb5,0xd6,0xbd,0xd7,0xbd,0xd6,0xb5,0xd6,0xbd,0xd6,0xb5,0xb7,0xbd,0xd6,0xb5,
+0xb7,0xb5,0xd6,0xb5,0xb7,0xb5,0xd6,0xb5,0xb6,0xbd,0xd6,0xb5,0xd7,0xbd,0xd6,0xb5,
+0xd7,0xbd,0x75,0xad,0xe4,0x20,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x04,0x21,0x34,0xa5,0x96,0xad,
+0x75,0xad,0x55,0xad,0x35,0xad,0x34,0xa5,0x14,0xa5,0xf3,0x9c,0xd3,0x9c,0xb2,0x94,
+0x92,0x94,0xb2,0x94,0x96,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,
+0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,
+0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0x14,0xa5,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xab,0x52,0xb6,0xb5,0x96,0xb5,0x96,0xb5,
+0x96,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,0xb6,0xb5,0x96,0xb5,0xb6,0xb5,0x96,0xb5,
+0xb6,0xb5,0x96,0xb5,0xb6,0xb5,0x96,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,
+0xb6,0xb5,0x10,0x84,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0xa6,0x31,0xb6,0xb5,0xd6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,
+0xd6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xd6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,
+0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xd7,0xbd,0xd3,0x9c,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0xc3,0x18,0x75,0xad,0xd7,0xbd,0xd6,0xb5,0xd6,0xbd,0xd7,0xb5,
+0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd6,0xb5,0xd7,0xbd,0xd6,0xbd,0xd7,0xbd,
+0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xb5,0xd6,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,
+0xd7,0xbd,0xd7,0xbd,0xd7,0xb5,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd6,0xbd,0xd7,0xbd,
+0xd7,0xb5,0xd7,0xbd,0xd6,0xb5,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd6,0xbd,0xd7,0xbd,
+0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,
+0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,
+0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,
+0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xf7,0xbd,0xef,0x7b,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x65,0x29,0xb6,0xb5,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,
+0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,
+0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,
+0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,
+0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,
+0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,
+0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,
+0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,
+0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xf7,0xbd,0x75,0xad,0xa3,0x18,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x20,0x00,0x34,0xad,0xd7,0xbd,0xd7,0xb5,0xd6,0xb5,0xd7,0xbd,0xd7,0xb5,0xd7,0xbd,
+0xd7,0xbd,0xd7,0xbd,0xd6,0xbd,0xd7,0xbd,0xd6,0xbd,0xd7,0xbd,0xd6,0xbd,0xd6,0xbd,
+0xd6,0xb5,0xd7,0xb5,0xd6,0xbd,0xd7,0xbd,0xd7,0xbd,0x76,0xb5,0x04,0x21,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0xb2,0x94,0xb6,0xb5,0x76,0xad,0x75,0xad,0x55,0xad,0x54,0xad,0x34,0xa5,
+0x34,0xa5,0xf3,0x9c,0xf3,0x9c,0xd2,0x94,0x92,0x94,0xb2,0x94,0x96,0xb5,0xb6,0xb5,
+0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,
+0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,
+0xb6,0xb5,0xb6,0xb5,0x34,0xa5,0x20,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0xab,0x5a,0xb6,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,
+0x96,0xb5,0x96,0xb5,0x96,0xb5,0xb6,0xb5,0x96,0xb5,0xb6,0xb5,0x96,0xb5,0xb6,0xb5,
+0x96,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0x10,0x7c,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xa7,0x31,0xb6,0xb5,
+0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xd6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,
+0xb6,0xb5,0xd6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xd6,0xb5,
+0xb6,0xb5,0xd6,0xb5,0xd7,0xbd,0xd2,0x94,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x8e,0x73,0xf7,0xbd,
+0xb7,0xbd,0xd7,0xb5,0xd6,0xb5,0xd6,0xb5,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd6,0xbd,
+0xd7,0xb5,0xd7,0xb5,0xd6,0xbd,0xd6,0xbd,0xd6,0xbd,0xd7,0xb5,0xd6,0xbd,0xd7,0xbd,
+0xd6,0xbd,0xd7,0xbd,0xd7,0xbd,0xd6,0xb5,0xd7,0xbd,0xd6,0xb5,0xd7,0xbd,0xd7,0xbd,
+0xd7,0xbd,0xd6,0xbd,0xd7,0xbd,0xd6,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,
+0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,
+0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,
+0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,
+0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,
+0xd7,0xbd,0x17,0xbe,0x4d,0x6b,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x65,0x29,0xb6,0xb5,0xf7,0xbd,
+0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,
+0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,
+0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,
+0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,
+0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,
+0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,
+0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,
+0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,
+0xf7,0xbd,0x54,0xa5,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x21,0x08,0x54,0xa5,0xd7,0xbd,0xd7,0xbd,
+0xd7,0xb5,0xd7,0xbd,0xd6,0xb5,0xd7,0xbd,0xd6,0xb5,0xd7,0xbd,0xd6,0xbd,0xd6,0xbd,
+0xd7,0xbd,0xd7,0xb5,0xd7,0xb5,0xd6,0xbd,0xb7,0xb5,0xd6,0xb5,0xd7,0xb5,0xd6,0xb5,
+0xd7,0xbd,0x75,0xad,0x04,0x21,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xcf,0x7b,0xb6,0xb5,0x96,0xb5,0x75,0xad,
+0x75,0xad,0x55,0xad,0x54,0xad,0x34,0xa5,0x14,0xa5,0xf3,0x9c,0xd3,0x9c,0xd2,0x94,
+0x92,0x94,0xb2,0x94,0x96,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,
+0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,
+0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xd6,0xb5,0x34,0xa5,0x20,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xab,0x5a,0xb6,0xb5,0xb6,0xb5,0x96,0xb5,
+0x96,0xb5,0x96,0xb5,0xb6,0xb5,0x96,0xb5,0xb6,0xb5,0x96,0xb5,0xb6,0xb5,0xb6,0xb5,
+0xb6,0xb5,0x96,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,
+0xd6,0xb5,0xf0,0x7b,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0xa6,0x31,0xb6,0xb5,0xd6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,
+0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xd6,0xb5,0xd6,0xb5,
+0xd6,0xb5,0xd6,0xb5,0xd6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xf7,0xbd,0xd2,0x9c,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0xd2,0x9c,0xf7,0xbd,0xd7,0xb5,0xd7,0xb5,0xd7,0xbd,0xd7,0xbd,
+0xd6,0xbd,0xd7,0xbd,0xd7,0xb5,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xb5,0xd7,0xbd,
+0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,
+0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,
+0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,
+0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,
+0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,
+0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,
+0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0x17,0xbe,0x14,0x9d,0x62,0x08,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x66,0x29,0xb6,0xb5,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,
+0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,
+0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xf7,0xbd,0xf7,0xbd,
+0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,
+0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,
+0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,
+0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,
+0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,
+0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xb6,0xb5,0xab,0x5a,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x34,0xa5,0xf7,0xbd,0xd7,0xbd,0xd7,0xb5,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,
+0xd7,0xb5,0xd7,0xbd,0xd6,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xb5,
+0xd7,0xbd,0xd7,0xbd,0xd6,0xbd,0xd7,0xbd,0xd7,0xbd,0x76,0xb5,0x04,0x21,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xcb,0x5a,
+0xb6,0xb5,0x96,0xb5,0x96,0xb5,0x75,0xb5,0x75,0xad,0x55,0xad,0x55,0xad,0x34,0xa5,
+0x14,0xa5,0xf3,0x9c,0xd3,0x9c,0xb2,0x94,0x92,0x94,0x92,0x94,0x96,0xb5,0xd6,0xb5,
+0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,
+0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,
+0xb6,0xb5,0xb6,0xbd,0x34,0xa5,0x20,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0xab,0x5a,0xb6,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,
+0x96,0xb5,0xb6,0xb5,0x96,0xb5,0xb6,0xb5,0x96,0xb5,0xb6,0xb5,0x96,0xb5,0xb6,0xb5,
+0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xd6,0xb5,0xcf,0x7b,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xa6,0x31,0xd6,0xb5,
+0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xd6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xd6,0xb5,
+0xb6,0xb5,0xd6,0xb5,0xb6,0xb5,0xd6,0xb5,0xb6,0xb5,0xd6,0xb5,0xd6,0xb5,0xb6,0xb5,
+0xd6,0xb5,0xb6,0xb5,0xd7,0xbd,0xd2,0x94,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xef,0x83,0xf7,0xbd,
+0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,
+0x96,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,
+0x96,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,0x76,0xb5,0x96,0xb5,
+0xf3,0x9c,0x2c,0x63,0x2c,0x6b,0x4d,0x6b,0x2d,0x6b,0x4d,0x6b,0x2d,0x6b,0x4d,0x6b,
+0x2d,0x6b,0x4d,0x6b,0x2d,0x6b,0x4d,0x6b,0x2d,0x6b,0x4d,0x6b,0x2d,0x6b,0x4d,0x6b,
+0x4d,0x6b,0x4d,0x6b,0x2d,0x6b,0x4d,0x6b,0x4d,0x6b,0x4d,0x6b,0x2d,0x6b,0x4d,0x6b,
+0x4d,0x6b,0x4d,0x6b,0x4d,0x6b,0x4d,0x6b,0x2d,0x6b,0x4d,0x6b,0x4d,0x6b,0x4d,0x6b,
+0x2d,0x6b,0x4d,0x6b,0x4d,0x6b,0x4d,0x6b,0x4d,0x6b,0x4d,0x6b,0x4d,0x6b,0x0c,0x63,
+0x8a,0x52,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x65,0x29,0xb6,0xb5,0xf7,0xbd,
+0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,
+0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,
+0xf7,0xbd,0x75,0xad,0x0c,0x63,0xcb,0x5a,0xeb,0x5a,0xeb,0x5a,0xeb,0x5a,0xeb,0x5a,
+0xeb,0x5a,0xeb,0x5a,0xeb,0x5a,0xeb,0x5a,0xcb,0x5a,0xeb,0x5a,0xaa,0x52,0x6a,0x4a,
+0x8a,0x52,0x69,0x52,0x8a,0x4a,0x8a,0x52,0x6a,0x4a,0x8a,0x52,0x8a,0x52,0x8a,0x52,
+0x8a,0x52,0x6a,0x52,0x89,0x4a,0x8a,0x52,0x8a,0x52,0x6a,0x4a,0x8a,0x52,0x89,0x52,
+0x6a,0x52,0x6a,0x52,0x8a,0x52,0x6a,0x52,0x89,0x52,0x89,0x4a,0x8a,0x52,0x89,0x4a,
+0x8a,0x4a,0x8a,0x52,0x8a,0x52,0x89,0x52,0x8a,0x4a,0x8a,0x4a,0x8a,0x52,0x69,0x4a,
+0x24,0x21,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x34,0xa5,0xf7,0xbd,0xd7,0xbd,
+0xd7,0xbd,0xd7,0xbd,0xd6,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,
+0xd7,0xb5,0xd7,0xb5,0xd7,0xb5,0xd6,0xb5,0xd7,0xbd,0xd7,0xb5,0xd7,0xb5,0xd6,0xbd,
+0xd7,0xbd,0x95,0xad,0x04,0x21,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0xa6,0x31,0x95,0xad,0xb6,0xb5,0x96,0xb5,0x96,0xb5,0x75,0xad,
+0x75,0xad,0x55,0xad,0x55,0xad,0x34,0xa5,0x34,0xa5,0x13,0x9d,0xd3,0x9c,0xb2,0x94,
+0x92,0x94,0x92,0x94,0x96,0xb5,0xd6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,
+0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,
+0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0x34,0xa5,0x20,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xcb,0x52,0xb6,0xb5,0xb6,0xb5,0x96,0xb5,
+0xb6,0xb5,0x96,0xb5,0xb6,0xb5,0x96,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,
+0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,
+0xd6,0xb5,0xcf,0x7b,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0xa6,0x39,0xb6,0xb5,0xd6,0xb5,0xb6,0xb5,0xd6,0xb5,0xb6,0xb5,
+0xd6,0xb5,0xd6,0xb5,0xd6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,
+0xd6,0xb5,0xd6,0xb5,0xd6,0xb5,0xb7,0xb5,0xd6,0xb5,0xd7,0xbd,0xf7,0xbd,0xd3,0x9c,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x92,0x94,0xd6,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,
+0x96,0xb5,0x96,0xb5,0x76,0xb5,0x76,0xad,0x95,0xad,0x75,0xad,0x75,0xad,0x75,0xad,
+0x75,0xad,0x75,0xad,0x75,0xad,0x55,0xad,0x75,0xad,0x55,0xad,0x55,0xad,0x55,0xad,
+0x55,0xad,0x55,0xad,0x55,0xad,0x55,0xad,0x55,0xad,0x8a,0x52,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x45,0x29,0xb6,0xb5,0xf7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,
+0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,
+0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xf7,0xbd,0x34,0xa5,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x34,0xa5,0xf7,0xbd,0xd7,0xbd,0xd7,0xb5,0xd7,0xbd,0xd6,0xbd,0xd7,0xbd,
+0xd7,0xbd,0xd7,0xbd,0xd7,0xb5,0xd7,0xbd,0xd6,0xb5,0xd7,0xbd,0xd6,0xbd,0xd7,0xb5,
+0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0x96,0xb5,0x04,0x21,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x41,0x08,0x14,0xa5,0xd7,0xbd,
+0xb6,0xb5,0x96,0xb5,0x96,0xb5,0x76,0xad,0x75,0xad,0x55,0xad,0x55,0xad,0x34,0xa5,
+0x34,0xa5,0x13,0x9d,0xf3,0x9c,0xb2,0x94,0xb2,0x94,0x92,0x94,0x96,0xb5,0xb6,0xb5,
+0xd6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,
+0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,
+0xb6,0xb5,0xb7,0xbd,0x34,0xa5,0x20,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0xab,0x5a,0xd6,0xb5,0x96,0xb5,0xb6,0xb5,0x96,0xb5,0xb6,0xb5,0x96,0xb5,0xb6,0xb5,
+0x96,0xb5,0xb6,0xb5,0x96,0xb5,0xb6,0xb5,0x96,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,
+0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xd6,0xbd,0xcf,0x7b,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xa7,0x31,0xb6,0xb5,
+0xb6,0xb5,0xd6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xd6,0xb5,0xd6,0xb5,
+0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xd6,0xb5,0xd6,0xb5,0xb6,0xb5,0xd6,0xb5,0xd6,0xb5,
+0xd6,0xbd,0xb6,0xb5,0xd7,0xbd,0xd2,0x94,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x41,0x08,
+0xf3,0x9c,0xb6,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,
+0x75,0xad,0x95,0xad,0x75,0xad,0x75,0xad,0x75,0xad,0x75,0xad,0x75,0xad,0x75,0xad,
+0x75,0xad,0x75,0xad,0x55,0xad,0x75,0xad,0x55,0xad,0x75,0xad,0x55,0xad,0x55,0xad,
+0x55,0xad,0x55,0xad,0x49,0x4a,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x04,0x21,0x96,0xb5,0xf7,0xbd,
+0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,
+0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,
+0xf7,0xbd,0x34,0xa5,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x14,0xa5,0xf7,0xbd,0xd7,0xbd,
+0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd6,0xbd,0xd7,0xbd,0xd7,0xb5,0xd7,0xbd,0xd6,0xb5,
+0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xb5,0xd7,0xbd,0xd7,0xb5,0xd7,0xb5,0xd7,0xb5,
+0xd7,0xbd,0x96,0xad,0x04,0x21,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x51,0x8c,0xd7,0xbd,0xb6,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,0x95,0xb5,
+0x75,0xad,0x55,0xad,0x55,0xad,0x34,0xa5,0x14,0xa5,0x13,0x9d,0xd3,0x9c,0xd2,0x94,
+0x92,0x94,0x92,0x94,0x96,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,
+0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,
+0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xd6,0xb5,0x34,0xa5,0x20,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xcb,0x5a,0xb6,0xb5,0xb6,0xb5,0x96,0xb5,
+0xb6,0xb5,0x96,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,
+0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,
+0xd6,0xb5,0xcf,0x7b,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0xa6,0x31,0xd6,0xb5,0xb6,0xb5,0xd6,0xb5,0xb6,0xb5,0xd6,0xb5,
+0xd6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xd6,0xb5,0xd6,0xb5,0xb6,0xbd,
+0xd6,0xb5,0xd6,0xb5,0xd6,0xb5,0xb7,0xbd,0xd6,0xb5,0xb7,0xbd,0xf7,0xbd,0xd2,0x94,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xe4,0x18,0x34,0xa5,0xb6,0xb5,0x96,0xb5,
+0x96,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,0x95,0xb5,0x96,0xb5,0x75,0xad,0x75,0xad,
+0x75,0xad,0x75,0xad,0x75,0xad,0x75,0xad,0x75,0xad,0x75,0xad,0x75,0xad,0x75,0xad,
+0x75,0xad,0x55,0xad,0x75,0xad,0x55,0xad,0x55,0xad,0x75,0xad,0x54,0xa5,0xc7,0x39,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x04,0x21,0x96,0xb5,0xf7,0xbd,0xf7,0xbd,0xd7,0xbd,0xf7,0xbd,0xd7,0xbd,
+0xf7,0xbd,0xd7,0xbd,0xf7,0xbd,0xd7,0xbd,0xf7,0xbd,0xd7,0xbd,0xf7,0xbd,0xd7,0xbd,
+0xf7,0xbd,0xd7,0xbd,0xf7,0xbd,0xd7,0xbd,0xf7,0xbd,0x34,0xa5,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x34,0xa5,0xf7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,
+0xd7,0xbd,0xd7,0xbd,0xd7,0xb5,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,
+0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0x96,0xb5,0x04,0x21,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x6d,0x6b,0xd7,0xbd,0xb6,0xb5,0xb6,0xb5,
+0xb6,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,0x75,0xad,0x55,0xad,0x55,0xad,0x34,0xa5,
+0x34,0xa5,0x13,0x9d,0xf3,0x9c,0xd3,0x9c,0x92,0x94,0x92,0x94,0x96,0xb5,0xb6,0xb5,
+0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,
+0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,
+0xb6,0xb5,0xd6,0xbd,0x34,0xa5,0x20,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0xab,0x5a,0xb6,0xb5,0x96,0xb5,0xb6,0xb5,0x96,0xb5,0xb6,0xb5,0x96,0xb5,0xb6,0xb5,
+0x96,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,
+0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb7,0xbd,0xcf,0x7b,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xa7,0x39,0xb6,0xb5,
+0xd6,0xb5,0xd6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xd6,0xb5,0xd6,0xb5,0xd6,0xb5,
+0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xd6,0xb5,0xb7,0xb5,0xd6,0xb5,0xb6,0xbd,0xd6,0xb5,
+0xb7,0xb5,0xd6,0xb5,0xd7,0xbd,0xd3,0x9c,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x86,0x29,0x55,0xad,0xb6,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xad,
+0x76,0xb5,0x95,0xb5,0x76,0xb5,0x75,0xad,0x75,0xad,0x75,0xad,0x75,0xad,0x75,0xad,
+0x75,0xad,0x75,0xad,0x75,0xad,0x75,0xad,0x75,0xad,0x75,0xad,0x55,0xad,0x75,0xad,
+0x55,0xad,0x55,0xad,0x75,0xad,0x14,0xa5,0x45,0x29,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x04,0x21,0x96,0xb5,0xf7,0xbd,
+0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,
+0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,
+0xf7,0xbd,0x34,0xa5,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x34,0xa5,0xf7,0xbd,0xd7,0xbd,
+0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xb5,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd6,0xbd,
+0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xb5,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd6,0xbd,
+0xd7,0xbd,0x96,0xb5,0x04,0x21,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x28,0x42,
+0xb6,0xb5,0xd6,0xb5,0xb6,0xb5,0xb6,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xad,
+0x75,0xad,0x55,0xad,0x55,0xad,0x34,0xa5,0x14,0xa5,0x13,0x9d,0xd3,0x9c,0xd2,0x94,
+0x92,0x94,0xb2,0x94,0x96,0xb5,0xb6,0xb5,0xb6,0xb5,0xd6,0xb5,0xb6,0xb5,0xb6,0xb5,
+0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,
+0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xd6,0xb5,0x34,0xa5,0x20,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xcb,0x5a,0xd6,0xb5,0xb6,0xb5,0x96,0xb5,
+0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,
+0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,
+0xd7,0xb5,0xcf,0x7b,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0xa6,0x31,0xd6,0xb5,0xd6,0xb5,0xd6,0xb5,0xd6,0xb5,0xd6,0xb5,
+0xd6,0xb5,0xd6,0xb5,0xd6,0xb5,0xd6,0xb5,0xd6,0xb5,0xb6,0xbd,0xd6,0xb5,0xd6,0xb5,
+0xd6,0xb5,0xb7,0xbd,0xd6,0xb5,0xd7,0xbd,0xd6,0xb5,0xd6,0xb5,0xf7,0xbd,0xd3,0x9c,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x08,0x42,0x75,0xad,
+0xb6,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,0x75,0xb5,0x75,0xb5,
+0x95,0xad,0x75,0xb5,0x75,0xad,0x75,0xad,0x75,0xad,0x75,0xad,0x75,0xad,0x75,0xad,
+0x75,0xad,0x75,0xad,0x75,0xad,0x75,0xad,0x75,0xad,0x75,0xad,0x75,0xad,0x76,0xad,
+0xf3,0x9c,0xa2,0x10,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x04,0x21,0x96,0xb5,0xf7,0xbd,0xf7,0xbd,0xd7,0xbd,0xf7,0xbd,0xd7,0xbd,
+0xf7,0xbd,0xd7,0xbd,0xf7,0xbd,0xd7,0xbd,0xf7,0xbd,0xd7,0xbd,0xf7,0xbd,0xd7,0xbd,
+0xf7,0xbd,0xd7,0xbd,0xf7,0xbd,0xd7,0xbd,0xf7,0xbd,0x34,0xa5,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x14,0xa5,0xf7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,
+0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,
+0xd7,0xbd,0xd7,0xbd,0xd6,0xbd,0xd7,0xbd,0xd7,0xbd,0x96,0xb5,0x04,0x21,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0xc3,0x18,0x55,0xad,0xd7,0xbd,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,
+0xb6,0xb5,0x96,0xb5,0x96,0xb5,0x76,0xad,0x75,0xad,0x55,0xad,0x55,0xad,0x34,0xa5,
+0x34,0xa5,0x14,0x9d,0xf3,0x9c,0xb2,0x9c,0x92,0x94,0x92,0x94,0x96,0xb5,0xd7,0xbd,
+0xb6,0xb5,0xd6,0xb5,0xb6,0xb5,0xb6,0xb5,0xd6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,
+0xd6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,
+0xb6,0xb5,0xd6,0xbd,0x34,0xa5,0x20,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0xab,0x5a,0xd6,0xb5,0x96,0xb5,0xb6,0xb5,0x96,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,
+0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,
+0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xd6,0xb5,0xcf,0x7b,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xa7,0x31,0xd6,0xb5,
+0xd6,0xbd,0xd6,0xb5,0xb6,0xb5,0xd6,0xb5,0xd6,0xb5,0xb6,0xb5,0xd7,0xb5,0xd6,0xb5,
+0xb6,0xbd,0xd6,0xb5,0xd7,0xb5,0xd6,0xb5,0xd6,0xb5,0xd6,0xb5,0xd7,0xb5,0xd6,0xb5,
+0xd6,0xb5,0xd7,0xb5,0xf7,0xbd,0xd3,0x9c,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x8a,0x52,0x96,0xb5,0xb6,0xb5,0x96,0xb5,0x96,0xb5,
+0x96,0xb5,0x96,0xb5,0x76,0xb5,0x95,0xb5,0x96,0xad,0x76,0xad,0x76,0xad,0x75,0xad,
+0x75,0xad,0x75,0xad,0x75,0xad,0x75,0xad,0x75,0xad,0x75,0xad,0x75,0xad,0x75,0xad,
+0x75,0xad,0x75,0xad,0x75,0xad,0x75,0xad,0x96,0xb5,0x92,0x94,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x04,0x21,0x96,0xb5,0xf7,0xbd,
+0xd7,0xbd,0xf7,0xbd,0xd7,0xbd,0xf7,0xbd,0xd7,0xbd,0xf7,0xbd,0xd7,0xbd,0xf7,0xbd,
+0xd7,0xbd,0xf7,0xbd,0xd7,0xbd,0xf7,0xbd,0xd7,0xbd,0xf7,0xbd,0xd7,0xbd,0xf7,0xbd,
+0xf7,0xbd,0x34,0xa5,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x34,0xa5,0xf7,0xbd,0xd7,0xbd,
+0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,
+0xd7,0xbd,0xd7,0xb5,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd6,0xb5,0xd7,0xbd,0xd7,0xb5,
+0xd7,0xbd,0x96,0xb5,0x04,0x21,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xb2,0x94,0xf7,0xbd,
+0xb6,0xb5,0xd6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0x96,0xb5,0x96,0xb5,0x75,0xb5,
+0x75,0xad,0x75,0xad,0x55,0xad,0x54,0xa5,0x34,0xa5,0x13,0x9d,0xd3,0x9c,0xd2,0x94,
+0x92,0x94,0x92,0x94,0x96,0xb5,0xd6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xd6,0xb5,
+0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xd6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,
+0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xd7,0xb5,0x34,0xa5,0x20,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xcb,0x5a,0xd6,0xb5,0xb6,0xb5,0xb6,0xb5,
+0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,
+0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,
+0xd7,0xbd,0xcf,0x7b,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0xa6,0x31,0xd7,0xbd,0xd6,0xbd,0xd7,0xbd,0xd6,0xb5,0xb6,0xbd,
+0xd6,0xb5,0xb6,0xbd,0xd6,0xb5,0xb6,0xbd,0xd6,0xb5,0xd7,0xbd,0xd6,0xb5,0xd7,0xb5,
+0xd6,0xbd,0xd6,0xbd,0xd7,0xbd,0xd7,0xbd,0xd6,0xbd,0xd7,0xb5,0xf7,0xbd,0xd3,0x9c,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x0c,0x63,0xb6,0xb5,0xb6,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,
+0x96,0xb5,0x96,0xb5,0x95,0xb5,0x96,0xb5,0x96,0xad,0x75,0xb5,0x76,0xad,0x96,0xb5,
+0x75,0xad,0x75,0xb5,0x95,0xad,0x75,0xad,0x75,0xad,0x75,0xad,0x75,0xad,0x75,0xad,
+0x75,0xad,0x96,0xb5,0x51,0x84,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x04,0x21,0xb6,0xb5,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,
+0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,
+0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0x34,0xa5,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x34,0xa5,0xf7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,
+0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,
+0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0x96,0xb5,0x04,0x21,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0xcf,0x7b,0xf7,0xbd,0xb7,0xbd,0xd6,0xb5,0xd7,0xb5,0xd6,0xb5,0xb6,0xb5,
+0xb6,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,0x75,0xad,0x55,0xad,0x55,0xad,0x54,0xa5,
+0x34,0xa5,0x14,0xa5,0xf3,0x9c,0xd3,0x94,0x92,0x94,0x92,0x94,0x96,0xb5,0xd7,0xb5,
+0xd6,0xb5,0xb6,0xb5,0xd6,0xb5,0xd6,0xb5,0xd6,0xb5,0xb6,0xb5,0xd6,0xb5,0xb6,0xb5,
+0xd6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,
+0xb6,0xb5,0xd7,0xbd,0x34,0xa5,0x20,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0xab,0x5a,0xd6,0xb5,0x96,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,
+0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,
+0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xd6,0xbd,0xcf,0x7b,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xa7,0x39,0xd6,0xb5,
+0xd6,0xbd,0xd6,0xb5,0xd6,0xbd,0xb6,0xb5,0xd6,0xb5,0xd6,0xb5,0xd6,0xb5,0xd6,0xb5,
+0xd7,0xbd,0xd6,0xb5,0xd7,0xbd,0xd6,0xb5,0xd7,0xb5,0xd6,0xbd,0xb7,0xbd,0xd7,0xbd,
+0xd6,0xb5,0xd7,0xbd,0xf7,0xbd,0xd3,0x94,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x8e,0x6b,0xb6,0xb5,0x96,0xb5,
+0x96,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,
+0x96,0xb5,0x96,0xad,0x96,0xb5,0x96,0xb5,0x76,0xad,0x95,0xb5,0x75,0xb5,0x75,0xb5,
+0x96,0xb5,0x95,0xb5,0x75,0xad,0x75,0xad,0x75,0xb5,0x75,0xad,0x96,0xb5,0xcf,0x7b,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x04,0x21,0x96,0xb5,0xf7,0xbd,
+0xf7,0xbd,0xf7,0xbd,0xd7,0xbd,0xf7,0xbd,0xd7,0xbd,0xf7,0xbd,0xd7,0xbd,0xf7,0xbd,
+0xf7,0xbd,0xf7,0xbd,0xd7,0xbd,0xf7,0xbd,0xd7,0xbd,0xf7,0xbd,0xd7,0xbd,0xf7,0xbd,
+0xf7,0xbd,0x34,0xa5,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x34,0xa5,0xf7,0xbd,0xd7,0xbd,
+0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,
+0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xb5,
+0xd7,0xbd,0x96,0xb5,0x04,0x21,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xaa,0x52,0xd7,0xb5,0xd7,0xbd,0xb6,0xb5,
+0xd6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xad,
+0x75,0xad,0x55,0xad,0x55,0xad,0x34,0xa5,0x34,0xa5,0x13,0x9d,0xf3,0x9c,0xd2,0x94,
+0x92,0x94,0x92,0x94,0x96,0xb5,0xd6,0xb5,0xd6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,
+0xb6,0xb5,0xd6,0xb5,0xb6,0xb5,0xd6,0xb5,0xb6,0xb5,0xd6,0xb5,0xb6,0xb5,0xb6,0xb5,
+0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xd7,0xbd,0x34,0xa5,0x41,0x08,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xcb,0x5a,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,
+0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,
+0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,
+0xd6,0xbd,0xcf,0x7b,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0xa6,0x31,0xd7,0xbd,0xd6,0xbd,0xb6,0xb5,0xd6,0xb5,0xb7,0xb5,
+0xd6,0xb5,0xd7,0xb5,0xd6,0xbd,0xd7,0xbd,0xd7,0xb5,0xd7,0xbd,0xd7,0xb5,0xd7,0xb5,
+0xd6,0xbd,0xd7,0xb5,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd6,0xbd,0xf7,0xbd,0xd3,0x9c,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0xef,0x7b,0xd6,0xb5,0xb6,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,
+0x96,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,
+0x96,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,
+0x96,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,0x4d,0x6b,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x04,0x21,0x96,0xb5,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,
+0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,
+0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0x34,0xa5,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x34,0xa5,0xf7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,
+0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,
+0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xf7,0xbd,0x96,0xb5,0x04,0x21,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x45,0x29,
+0x95,0xad,0xd7,0xbd,0xd6,0xb5,0xd7,0xb5,0xd6,0xb5,0xb7,0xbd,0xb6,0xb5,0xb6,0xb5,
+0xb6,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,0x75,0xad,0x55,0xad,0x55,0xad,0x54,0xa5,
+0x34,0xa5,0x14,0xa5,0xf3,0x9c,0xd3,0x9c,0x92,0x94,0xb2,0x94,0x96,0xb5,0xd6,0xbd,
+0xd6,0xb5,0xb6,0xb5,0xb6,0xb5,0xd6,0xb5,0xd6,0xb5,0xb6,0xb5,0xd6,0xb5,0xd6,0xb5,
+0xb6,0xb5,0xd6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xd6,0xb5,0xb6,0xb5,
+0xb6,0xb5,0xd6,0xbd,0x55,0xad,0x82,0x10,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0xab,0x5a,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,
+0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,
+0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xd6,0xbd,0xcf,0x7b,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xc7,0x39,0xd7,0xbd,
+0xb7,0xbd,0xd6,0xb5,0xb7,0xbd,0xd6,0xb5,0xb6,0xb5,0xd6,0xb5,0xd6,0xbd,0xd6,0xbd,
+0xd6,0xbd,0xd6,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xb5,0xd7,0xbd,0xd6,0xbd,0xd7,0xbd,
+0xd6,0xb5,0xd7,0xbd,0xf7,0xbd,0xd2,0x94,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x51,0x8c,
+0xd7,0xbd,0xb6,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,
+0x96,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,
+0x96,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,
+0x96,0xb5,0xab,0x5a,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x04,0x21,0x96,0xb5,0xf7,0xbd,
+0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,
+0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,
+0xf7,0xbd,0x34,0xa5,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x34,0xa5,0xf7,0xbd,0xd7,0xbd,
+0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,
+0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,
+0xd7,0xbd,0x96,0xb5,0x04,0x21,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0xf3,0x9c,0xd7,0xbd,0xd6,0xb5,0xd7,0xbd,0xd6,0xb5,
+0xd6,0xb5,0xd6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0x96,0xb5,0x95,0xb5,
+0x75,0xad,0x75,0xad,0x55,0xad,0x34,0xa5,0x34,0xa5,0x13,0x9d,0xf3,0x9c,0xd3,0x9c,
+0xb2,0x94,0xb2,0x94,0x96,0xb5,0xd6,0xbd,0xd6,0xb5,0xd6,0xb5,0xb6,0xb5,0xb6,0xb5,
+0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xd6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xd6,0xb5,
+0xb6,0xb5,0xd6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xd6,0xb5,0x55,0xad,0x82,0x10,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xcb,0x5a,0xb6,0xbd,0xb6,0xb5,0xb6,0xb5,
+0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,
+0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,
+0xd7,0xbd,0xcf,0x7b,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x08,0x42,0xf7,0xbd,0xd7,0xbd,0xd6,0xb5,0xd7,0xbd,0xd7,0xb5,
+0xd7,0xbd,0xd6,0xbd,0xd7,0xbd,0xd6,0xb5,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,
+0xd7,0xb5,0xd7,0xbd,0xd6,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xf7,0xbd,0xd3,0x9c,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xb2,0x94,0xd7,0xbd,0xb6,0xb5,0xb6,0xb5,
+0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,
+0xb6,0xb5,0x96,0xb5,0xb6,0xb5,0x96,0xb5,0xb6,0xb5,0x96,0xb5,0xb6,0xb5,0x96,0xb5,
+0xb6,0xb5,0x96,0xb5,0xb6,0xb5,0x96,0xb5,0xb6,0xb5,0x96,0xb5,0x28,0x42,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x04,0x21,0x96,0xb5,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,
+0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,
+0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0x17,0xbe,0x34,0xa5,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x34,0xa5,0xf7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,
+0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,
+0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xb6,0xb5,0x65,0x29,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x10,0x84,0xf7,0xbd,
+0xd6,0xb5,0xd6,0xbd,0xd6,0xb5,0xd6,0xbd,0xd6,0xbd,0xd7,0xbd,0xb6,0xb5,0xb6,0xb5,
+0xb6,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,0x75,0xad,0x55,0xad,0x55,0xad,0x54,0xad,
+0x34,0xa5,0x14,0xa5,0xf3,0x9c,0xd3,0x9c,0xb2,0x94,0xb2,0x94,0x96,0xb5,0xd7,0xbd,
+0xd6,0xb5,0xb6,0xbd,0xd6,0xb5,0xb7,0xb5,0xd6,0xb5,0xd7,0xb5,0xb6,0xb5,0xb6,0xb5,
+0xd6,0xb5,0xb6,0xb5,0xd6,0xb5,0xb6,0xb5,0xd6,0xb5,0xd6,0xb5,0xd6,0xb5,0xd6,0xb5,
+0xd6,0xb5,0xd7,0xbd,0x55,0xad,0xa2,0x10,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0xcb,0x5a,0xd6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,
+0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,
+0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xd7,0xbd,0xcf,0x7b,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xe8,0x41,0xf7,0xbd,
+0xd6,0xbd,0xd6,0xb5,0xb7,0xb5,0xd6,0xb5,0xd7,0xbd,0xd6,0xbd,0xd6,0xbd,0xd6,0xbd,
+0xd6,0xbd,0xd7,0xbd,0xd7,0xbd,0xd6,0xb5,0xd7,0xbd,0xd7,0xb5,0xd6,0xbd,0xd6,0xb5,
+0xd7,0xbd,0xd7,0xbd,0xf7,0xbd,0xd3,0x94,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x41,0x08,0x13,0x9d,0xd7,0xbd,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,
+0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,
+0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,
+0xb6,0xb5,0xb6,0xb5,0x75,0xad,0xa7,0x39,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x04,0x21,0x96,0xb5,0xf7,0xbd,
+0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,
+0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,
+0xf7,0xbd,0x34,0xa5,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x34,0xa5,0xf7,0xbd,0xd7,0xbd,
+0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,
+0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,
+0xd7,0xbd,0xb6,0xb5,0x65,0x29,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0xec,0x62,0xd7,0xbd,0xb6,0xb5,0xb6,0xbd,0xd6,0xb5,0xd7,0xbd,0xd6,0xb5,
+0xd7,0xbd,0xd6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0x96,0xb5,0x96,0xad,
+0x75,0xad,0x75,0xad,0x55,0xad,0x34,0xa5,0x34,0xa5,0x13,0xa5,0xf3,0x9c,0xd3,0x9c,
+0x92,0x94,0x92,0x94,0x96,0xb5,0xd6,0xbd,0xb6,0xb5,0xd6,0xb5,0xb6,0xb5,0xd6,0xb5,
+0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xd6,0xb5,0xd6,0xb5,0xd6,0xb5,0xb6,0xb5,0xb6,0xb5,
+0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xd6,0xb5,0xb6,0xb5,0xd7,0xbd,0x55,0xad,0x82,0x10,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xcb,0x5a,0xb7,0xb5,0xb6,0xb5,0xb6,0xb5,
+0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,
+0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,
+0xd7,0xb5,0xcf,0x7b,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x08,0x42,0xf7,0xbd,0xd7,0xb5,0xd6,0xb5,0xd6,0xbd,0xd7,0xb5,
+0xd7,0xbd,0xd7,0xbd,0xd6,0xbd,0xd7,0xbd,0xd6,0xb5,0xd7,0xbd,0xd7,0xb5,0xd7,0xbd,
+0xd6,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xf7,0xbd,0xd3,0x9c,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x04,0x21,0x54,0xa5,0xd7,0xbd,
+0xd6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,
+0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,
+0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xd6,0xbd,0x55,0xad,
+0x25,0x21,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x24,0x21,0x96,0xb5,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,
+0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,
+0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0x17,0xbe,0x34,0xa5,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x34,0xa5,0xf7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,
+0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,
+0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xf7,0xbd,0xb6,0xb5,0x65,0x29,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xc7,0x39,0x96,0xb5,0xd6,0xb5,0xb6,0xb5,
+0xd7,0xbd,0xd6,0xb5,0xd7,0xbd,0xd6,0xb5,0xd6,0xbd,0xd6,0xbd,0xb6,0xb5,0xb6,0xb5,
+0xb6,0xb5,0xb6,0xb5,0x96,0xb5,0x96,0xb5,0x75,0xad,0x75,0xad,0x55,0xad,0x55,0xad,
+0x34,0xa5,0x14,0xa5,0xf3,0x9c,0xd3,0x9c,0xb2,0x94,0x92,0x94,0x96,0xb5,0xd7,0xbd,
+0xd6,0xb5,0xb6,0xb5,0xd6,0xb5,0xb6,0xbd,0xd6,0xb5,0xb6,0xbd,0xd6,0xb5,0xd7,0xb5,
+0xd6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xd6,0xb5,0xb6,0xb5,0xb6,0xb5,
+0xd6,0xb5,0xd7,0xbd,0x55,0xad,0x82,0x10,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0xcb,0x5a,0xd6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,
+0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,
+0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xd7,0xbd,0xcf,0x7b,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xe8,0x41,0xf7,0xbd,
+0xd7,0xbd,0xd6,0xb5,0xd6,0xb5,0xd6,0xbd,0xd7,0xb5,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,
+0xd7,0xbd,0xd6,0xb5,0xd7,0xbd,0xd6,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,
+0xd7,0xbd,0xd6,0xbd,0xf7,0xbd,0xd3,0x9c,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0xa6,0x31,0x75,0xad,0xd7,0xbd,0xb6,0xb5,0xb6,0xb5,0xd6,0xb5,
+0xb6,0xb5,0xd6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,
+0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xd6,0xb5,0xb6,0xb5,0xb6,0xb5,
+0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xd7,0xbd,0x14,0xa5,0x62,0x10,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x04,0x21,0xb6,0xb5,0xf7,0xbd,
+0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,
+0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,
+0x17,0xbe,0x34,0xa5,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x34,0xa5,0xf7,0xbd,0xd7,0xbd,
+0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,
+0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,
+0xd7,0xbd,0xb6,0xb5,0x65,0x29,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x41,0x08,
+0x14,0xa5,0xd7,0xb5,0xb6,0xb5,0xb6,0xb5,0xd7,0xb5,0xd6,0xb5,0xd7,0xbd,0xd6,0xb5,
+0xb6,0xb5,0xd7,0xb5,0xd6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0x96,0xb5,0x96,0xb5,
+0x75,0xad,0x75,0xad,0x55,0xad,0x54,0xa5,0x34,0xa5,0x14,0xa5,0xf3,0x9c,0xd2,0x94,
+0xb2,0x94,0x91,0x8c,0x76,0xad,0xd6,0xbd,0xd6,0xbd,0xd6,0xb5,0xb7,0xbd,0xd6,0xb5,
+0xd7,0xb5,0xb6,0xb5,0xd7,0xb5,0xd6,0xb5,0xb6,0xb5,0xd6,0xb5,0xb6,0xb5,0xb6,0xb5,
+0xd6,0xb5,0xb6,0xb5,0xb6,0xb5,0xd6,0xb5,0xb6,0xb5,0xd6,0xb5,0x55,0xad,0xa2,0x10,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xcb,0x5a,0xd7,0xb5,0xb6,0xb5,0xb6,0xb5,
+0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,
+0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,
+0xd7,0xbd,0xcf,0x7b,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x08,0x42,0xf7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xb5,0xd7,0xbd,
+0xd6,0xb5,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd6,0xbd,0xd7,0xbd,0xd7,0xb5,0xd7,0xbd,
+0xd6,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xf7,0xbd,0xd3,0x9c,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x29,0x4a,
+0xb6,0xb5,0xd7,0xbd,0xd7,0xb5,0xd7,0xb5,0xd6,0xb5,0xd7,0xbd,0xd6,0xb5,0xd7,0xbd,
+0xd6,0xb5,0xd7,0xb5,0xd6,0xb5,0xd6,0xbd,0xd6,0xbd,0xd7,0xbd,0xd7,0xb5,0xd7,0xbd,
+0xd6,0xbd,0xd6,0xbd,0xd7,0xb5,0xd6,0xbd,0xd6,0xb5,0xd7,0xbd,0xd6,0xb5,0xb7,0xb5,
+0xf7,0xbd,0xd3,0x9c,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x04,0x21,0xb6,0xb5,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,
+0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,
+0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0x17,0xbe,0x34,0xa5,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x34,0xa5,0xf7,0xbd,0xd7,0xbd,0xf7,0xbd,0xd7,0xbd,0xf7,0xbd,0xd7,0xbd,
+0xf7,0xbd,0xd7,0xbd,0xf7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,
+0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xf7,0xbd,0xb6,0xb5,0x65,0x29,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x51,0x8c,0xd7,0xbd,0xb6,0xb5,0xd6,0xb5,0xb6,0xbd,
+0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xb5,0xd7,0xbd,0xd7,0xb5,0xd6,0xb5,0xb6,0xb5,
+0xb6,0xb5,0xb6,0xb5,0x96,0xb5,0x96,0xb5,0x75,0xad,0x75,0xad,0x55,0xad,0x54,0xa5,
+0x34,0xa5,0x14,0xa5,0xf3,0x9c,0xd3,0x9c,0xb2,0x94,0xab,0x5a,0x34,0xa5,0xd7,0xbd,
+0xd7,0xb5,0xd7,0xb5,0xd7,0xb5,0xd7,0xbd,0xd6,0xb5,0xb7,0xb5,0xd6,0xb5,0xd7,0xbd,
+0xd6,0xb5,0xb7,0xbd,0xd6,0xb5,0xd6,0xbd,0xd6,0xb5,0xd6,0xb5,0xd6,0xb5,0xd6,0xb5,
+0xd6,0xb5,0xd7,0xbd,0x55,0xad,0x82,0x10,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0xeb,0x5a,0xd6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,
+0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,
+0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xd7,0xbd,0xcf,0x7b,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xe8,0x41,0xf7,0xbd,
+0xd7,0xb5,0xd7,0xb5,0xd6,0xb5,0xd7,0xbd,0xd7,0xbd,0xd6,0xbd,0xd7,0xbd,0xd7,0xb5,
+0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xb5,0xd7,0xbd,0xd6,0xb5,0xd7,0xbd,0xd7,0xbd,
+0xd7,0xbd,0xd7,0xbd,0xf7,0xbd,0xd3,0x9c,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xab,0x5a,0xd7,0xbd,0xd7,0xbd,0xd7,0xb5,
+0xd7,0xbd,0xd7,0xb5,0xd7,0xbd,0xd6,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,
+0xd7,0xbd,0xd6,0xbd,0xd7,0xbd,0xd7,0xb5,0xd7,0xb5,0xd6,0xbd,0xd7,0xbd,0xd7,0xb5,
+0xd7,0xbd,0xd7,0xbd,0xd6,0xbd,0xd7,0xbd,0xd7,0xbd,0xf7,0xbd,0x51,0x8c,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x04,0x21,0x96,0xb5,0xf7,0xbd,
+0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,
+0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,
+0xf7,0xbd,0x95,0xb5,0x4d,0x6b,0x0c,0x63,0x2c,0x63,0x2c,0x63,0x2c,0x63,0x2c,0x63,
+0x2c,0x63,0x2c,0x63,0x2c,0x63,0x2c,0x63,0x2c,0x63,0x2c,0x63,0x2c,0x63,0x2c,0x63,
+0x2c,0x63,0x2c,0x63,0x2c,0x63,0x2c,0x63,0x2c,0x63,0x2c,0x63,0x2c,0x63,0x2c,0x63,
+0x2c,0x63,0x2c,0x63,0x2c,0x63,0x2c,0x63,0x2c,0x63,0x2c,0x63,0x2c,0x63,0x2c,0x63,
+0x2c,0x63,0x2c,0x63,0x2c,0x63,0x6d,0x6b,0x6e,0x73,0x8e,0x73,0x4d,0x6b,0xe7,0x39,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x34,0xa5,0xf7,0xbd,0xf7,0xbd,
+0xd7,0xbd,0xf7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,
+0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,
+0xd7,0xbd,0xb6,0xb5,0x65,0x29,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x4d,0x6b,0xb6,0xb5,
+0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xd6,0xb5,0xd7,0xbd,0xd7,0xb5,0xd6,0xbd,0xd7,0xbd,
+0xd6,0xbd,0xd7,0xb5,0xd6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0x96,0xb5,0x96,0xb5,
+0x75,0xad,0x75,0xad,0x55,0xad,0x54,0xa5,0x34,0xa5,0x14,0xa5,0xf3,0x9c,0xf3,0x9c,
+0x2d,0x6b,0x00,0x00,0x34,0xa5,0xd7,0xbd,0xd7,0xbd,0xd6,0xb5,0xd7,0xbd,0xd6,0xb5,
+0xb7,0xb5,0xd6,0xb5,0xd7,0xbd,0xd6,0xb5,0xb7,0xb5,0xd6,0xb5,0xd6,0xb5,0xd6,0xb5,
+0xd6,0xb5,0xd6,0xb5,0xb6,0xb5,0xd6,0xb5,0xd6,0xb5,0xd6,0xbd,0x55,0xad,0x82,0x10,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x2c,0x63,0xd7,0xb5,0xb6,0xb5,0xb6,0xb5,
+0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,
+0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,
+0xd7,0xbd,0xcf,0x7b,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x08,0x42,0xf7,0xbd,0xd6,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,
+0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,
+0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xf7,0xbd,0xd3,0x9c,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x2d,0x6b,0xf7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,
+0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,
+0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,
+0xd7,0xbd,0xd7,0xbd,0xf7,0xbd,0xef,0x7b,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x04,0x21,0xb6,0xb5,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,
+0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,
+0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0x18,0xc6,0x18,0xc6,
+0x17,0xc6,0x18,0xc6,0x18,0xbe,0x18,0xc6,0x17,0xc6,0x17,0xc6,0x17,0xc6,0x18,0xbe,
+0x17,0xc6,0x17,0xc6,0x17,0xc6,0x18,0xbe,0x18,0xbe,0x17,0xc6,0x18,0xc6,0x18,0xc6,
+0x17,0xc6,0x18,0xbe,0x18,0xc6,0x18,0xbe,0x18,0xc6,0x18,0xbe,0x17,0xc6,0x18,0xc6,
+0x18,0xc6,0x18,0xc6,0x18,0xbe,0x18,0xbe,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x17,0xc6,
+0x18,0xc6,0x18,0xc6,0x18,0xc6,0xf7,0xbd,0x0c,0x63,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x34,0xa5,0xf7,0xbd,0xd7,0xbd,0xf7,0xbd,0xd7,0xbd,0xf7,0xbd,0xd7,0xbd,
+0xf7,0xbd,0xd7,0xbd,0xf7,0xbd,0xd7,0xbd,0xf7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,
+0xf7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xf7,0xbd,0xb6,0xb5,0x65,0x29,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x28,0x42,0x96,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xd6,0xb5,0xb7,0xbd,
+0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xb5,0xd6,0xbd,0xd6,0xb5,0xb6,0xb5,
+0xb6,0xb5,0xb6,0xb5,0x96,0xb5,0x96,0xb5,0x95,0xad,0x75,0xad,0x55,0xad,0x55,0xad,
+0x34,0xa5,0x14,0xa5,0x14,0x9d,0x30,0x84,0x00,0x00,0x00,0x00,0x54,0xa5,0xd7,0xbd,
+0xd7,0xbd,0xd7,0xb5,0xd7,0xbd,0xd6,0xb5,0xd6,0xbd,0xd7,0xbd,0xd6,0xbd,0xd7,0xbd,
+0xd6,0xb5,0xd7,0xbd,0xd6,0xb5,0xd7,0xbd,0xd6,0xb5,0xd6,0xbd,0xd6,0xb5,0xb7,0xb5,
+0xd6,0xb5,0xd7,0xbd,0x55,0xad,0x82,0x10,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x2c,0x63,0xd7,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,
+0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,
+0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xd7,0xbd,0xcf,0x7b,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x08,0x42,0xf7,0xbd,
+0xd7,0xbd,0xd6,0xbd,0xd7,0xbd,0xd7,0xb5,0xd7,0xbd,0xd7,0xb5,0xd7,0xbd,0xd7,0xbd,
+0xd7,0xbd,0xd7,0xb5,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,
+0xd7,0xbd,0xd7,0xbd,0xf7,0xbd,0xd3,0x9c,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xaf,0x7b,0xf7,0xbd,
+0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,
+0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,
+0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xf7,0xbd,
+0x4d,0x6b,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x04,0x21,0x96,0xb5,0xf7,0xbd,
+0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,
+0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,
+0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,
+0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,
+0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,
+0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,
+0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0x17,0xbe,
+0x55,0xad,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x14,0xa5,0xf7,0xbd,0xf7,0xbd,
+0xd7,0xbd,0xf7,0xbd,0xd7,0xbd,0xf7,0xbd,0xd7,0xbd,0xf7,0xbd,0xd7,0xbd,0xf7,0xbd,
+0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,
+0xf7,0xbd,0xb6,0xb5,0x65,0x29,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xc3,0x18,0x34,0xa5,0xb6,0xb5,0x96,0xb5,
+0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xd6,0xb5,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd6,0xb5,
+0xd7,0xbd,0xd7,0xbd,0xb7,0xbd,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0x96,0xb5,0x96,0xb5,
+0x75,0xb5,0x75,0xad,0x55,0xad,0x54,0xad,0x34,0xa5,0x14,0xa5,0xd3,0x9c,0x45,0x29,
+0x00,0x00,0x21,0x00,0x54,0xa5,0xd7,0xbd,0xd7,0xbd,0xd6,0xbd,0xd7,0xbd,0xd7,0xb5,
+0xd7,0xbd,0xd7,0xb5,0xb6,0xbd,0xd6,0xb5,0xd7,0xb5,0xd6,0xb5,0xb6,0xbd,0xd6,0xb5,
+0xd7,0xbd,0xd6,0xb5,0xb6,0xb5,0xd6,0xb5,0xb6,0xb5,0xd7,0xb5,0x55,0xad,0xa2,0x10,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x2c,0x63,0xd7,0xbd,0xb6,0xb5,0xb6,0xb5,
+0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,
+0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,
+0xd7,0xbd,0xcf,0x7b,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x08,0x42,0xf7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,
+0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,
+0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xf7,0xbd,0xd3,0x9c,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x30,0x84,0xf7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,
+0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,
+0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,
+0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xf7,0xbd,0xf7,0xbd,0xaa,0x52,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x24,0x21,0xb6,0xb5,0x17,0xbe,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,
+0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,
+0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,
+0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,
+0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,
+0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,
+0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,
+0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0x55,0xad,0x41,0x08,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x14,0xa5,0x17,0xbe,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,
+0xf7,0xbd,0xd7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xd7,0xbd,0xf7,0xbd,0xd7,0xbd,
+0xf7,0xbd,0xd7,0xbd,0xf7,0xbd,0xd7,0xbd,0xf7,0xbd,0xb6,0xb5,0x65,0x29,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x71,0x8c,0x96,0xb5,0x96,0xb5,0x96,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb7,0xbd,
+0xd6,0xbd,0xd7,0xbd,0xd7,0xb5,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xb6,0xb5,
+0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0x96,0xb5,0x95,0xb5,0x75,0xad,0x55,0xad,0x55,0xa5,
+0x34,0xa5,0x14,0xa5,0x8a,0x52,0x00,0x00,0x00,0x00,0x21,0x08,0x54,0xa5,0xd7,0xbd,
+0xd7,0xbd,0xd7,0xb5,0xd6,0xbd,0xd6,0xbd,0xd6,0xb5,0xd7,0xbd,0xd6,0xbd,0xd7,0xbd,
+0xd7,0xbd,0xd7,0xb5,0xd6,0xb5,0xd7,0xb5,0xd6,0xbd,0xd7,0xbd,0xd6,0xb5,0xb6,0xbd,
+0xd6,0xb5,0xd7,0xbd,0x55,0xad,0x82,0x10,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x0c,0x63,0xd7,0xbd,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,
+0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,
+0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xd7,0xbd,0xcf,0x73,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x08,0x42,0xf7,0xbd,
+0xd7,0xbd,0xd7,0xb5,0xd7,0xbd,0xd6,0xb5,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xb5,
+0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,
+0xd7,0xbd,0xd7,0xbd,0xf7,0xbd,0xd3,0x9c,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x92,0x94,0xf7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,
+0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,
+0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,
+0xf7,0xbd,0xd6,0xb5,0x28,0x42,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x24,0x21,0x96,0xb5,0xf7,0xbd,
+0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,
+0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,
+0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,
+0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,
+0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,
+0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,
+0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,
+0x55,0xad,0x21,0x08,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x14,0x9d,0xf7,0xbd,0xf7,0xbd,
+0xf7,0xbd,0xf7,0xbd,0xd7,0xbd,0xf7,0xbd,0xd7,0xbd,0xf7,0xbd,0xd7,0xbd,0xf7,0xbd,
+0xd7,0xbd,0xf7,0xbd,0xd7,0xbd,0xf7,0xbd,0xd7,0xbd,0xf7,0xbd,0xd7,0xbd,0xd7,0xbd,
+0xf7,0xbd,0xb6,0xb5,0x65,0x31,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x6d,0x6b,0x96,0xb5,0x95,0xad,0x96,0xb5,0xb6,0xb5,
+0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xd6,0xb5,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd6,0xb5,
+0xd7,0xbd,0xd6,0xbd,0xb6,0xb5,0xd6,0xb5,0xb6,0xb5,0xb6,0xb5,0x96,0xb5,0x96,0xb5,
+0x76,0xb5,0x75,0xad,0x55,0xad,0x55,0xa5,0x55,0xad,0xae,0x73,0x00,0x00,0x00,0x00,
+0x00,0x00,0x20,0x00,0x54,0xa5,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd6,0xb5,0xd7,0xbd,
+0xd6,0xbd,0xd7,0xbd,0xd6,0xbd,0xd7,0xb5,0xd7,0xb5,0xd6,0xb5,0xb7,0xbd,0xd6,0xb5,
+0xb6,0xbd,0xd6,0xb5,0xb7,0xbd,0xd6,0xb5,0xb7,0xb5,0xd7,0xbd,0x55,0xad,0xa2,0x10,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x2c,0x63,0xd7,0xbd,0xb6,0xb5,0xb6,0xb5,
+0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,
+0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,
+0xd7,0xbd,0xaf,0x7b,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x08,0x42,0xf7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,
+0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,
+0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xf7,0xbd,0xd3,0x9c,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xf3,0x9c,0xf7,0xbd,0xd7,0xbd,
+0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,
+0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,
+0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xf7,0xbd,0x96,0xb5,0xa6,0x31,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x24,0x21,0xb6,0xb5,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,
+0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,
+0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,
+0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,
+0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,
+0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,
+0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,
+0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0x17,0xbe,0x55,0xad,0x21,0x08,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x14,0xa5,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,
+0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xd7,0xbd,
+0xf7,0xbd,0xd7,0xbd,0xf7,0xbd,0xd7,0xbd,0xf7,0xbd,0xb6,0xb5,0x65,0x29,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x69,0x4a,0x75,0xad,
+0x75,0xad,0x96,0xb5,0x96,0xb5,0x96,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xd7,0xbd,
+0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd6,0xb5,
+0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0x96,0xb5,0x75,0xb5,0x75,0xad,0x55,0xad,0x55,0xad,
+0x92,0x94,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x21,0x08,0x54,0xa5,0xd7,0xbd,
+0xd7,0xb5,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xb5,0xd7,0xb5,
+0xd7,0xbd,0xd6,0xb5,0xd7,0xbd,0xd6,0xb5,0xd7,0xb5,0xd6,0xbd,0xd6,0xbd,0xb7,0xbd,
+0xd6,0xb5,0xd7,0xbd,0x75,0xad,0xe4,0x20,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x0c,0x63,0xd7,0xbd,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,
+0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,
+0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xd7,0xbd,0xaf,0x73,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x08,0x42,0xf7,0xbd,
+0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,
+0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,
+0xd7,0xbd,0xd7,0xbd,0xf7,0xbd,0xd3,0x9c,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x82,0x10,0x34,0xa5,0xf7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,
+0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,
+0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,
+0xd7,0xbd,0xd7,0xbd,0xf7,0xbd,0x55,0xad,0xe4,0x20,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x04,0x21,0xb6,0xb5,0x17,0xbe,
+0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,
+0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,
+0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,
+0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,
+0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,
+0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,
+0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,
+0x55,0xad,0x21,0x08,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x14,0xa5,0x17,0xbe,0xf7,0xbd,
+0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,
+0xd7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xd7,0xbd,0xf7,0xbd,0xd7,0xbd,0xf7,0xbd,
+0xf7,0xbd,0xb6,0xb5,0x66,0x29,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x24,0x21,0x14,0xa5,0x75,0xad,0x75,0xad,0x96,0xad,0x96,0xb5,0xb6,0xb5,
+0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xd6,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd6,0xbd,
+0xd7,0xbd,0xd7,0xb5,0xd7,0xb5,0xd6,0xb5,0xb6,0xb5,0xb6,0xb5,0x96,0xb5,0x96,0xb5,
+0x76,0xb5,0x75,0xad,0x55,0xad,0x34,0xa5,0x66,0x31,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x20,0x08,0x35,0xa5,0xf7,0xbd,0xd7,0xbd,0xd6,0xb5,0xd7,0xbd,0xd6,0xbd,
+0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xb5,0xd7,0xb5,0xd7,0xbd,0xd6,0xbd,0xd6,0xbd,
+0xb7,0xbd,0xd7,0xb5,0xd7,0xbd,0xd6,0xb5,0xd6,0xbd,0xd7,0xbd,0x76,0xad,0x04,0x21,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x2c,0x63,0xd7,0xbd,0xb6,0xb5,0xb6,0xb5,
+0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,
+0xb6,0xb5,0xb6,0xb5,0xd6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,
+0xd7,0xbd,0xaf,0x7b,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x08,0x42,0xf7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,
+0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,
+0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0x17,0xbe,0xd3,0x9c,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x24,0x21,0x75,0xad,
+0xf7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,
+0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,
+0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xf7,0xbd,
+0x14,0xa5,0x41,0x08,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x04,0x21,0xb6,0xb5,0xf7,0xc5,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,
+0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,
+0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,
+0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,
+0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,
+0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,
+0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,
+0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0x75,0xad,0x82,0x10,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x14,0xa5,0x17,0xbe,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,
+0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,
+0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xb6,0xb5,0x65,0x29,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x71,0x94,0x75,0xad,0x55,0xad,
+0x75,0xad,0x75,0xad,0x96,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xd7,0xb5,
+0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xb5,0xb6,0xb5,
+0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0x96,0xb5,0x95,0xb5,0x75,0xad,0x75,0xad,0xcb,0x5a,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x21,0x08,0x55,0xa5,0xf7,0xbd,
+0xd7,0xbd,0xd7,0xbd,0xd6,0xb5,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,
+0xd7,0xbd,0xd7,0xbd,0xd7,0xb5,0xd7,0xb5,0xd6,0xb5,0xd7,0xbd,0xd7,0xbd,0xd6,0xbd,
+0xd7,0xbd,0xd7,0xbd,0x95,0xad,0x04,0x21,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x2c,0x63,0xd6,0xbd,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,
+0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,
+0xb6,0xb5,0xd6,0xb5,0xb6,0xb5,0xd6,0xb5,0xd7,0xbd,0xae,0x73,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x08,0x42,0xf7,0xbd,
+0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,
+0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,
+0xd7,0xbd,0xd7,0xbd,0xf7,0xbd,0xd3,0x9c,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0xc7,0x39,0x96,0xb5,0xf7,0xbd,0xd7,0xbd,0xd7,0xbd,
+0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,
+0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,
+0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xf7,0xbd,0xb2,0x94,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x04,0x21,0xb6,0xb5,0x17,0xbe,
+0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,
+0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,
+0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,
+0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,
+0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,
+0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,
+0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,
+0x76,0xb5,0xa3,0x10,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x14,0xa5,0xf7,0xc5,0xf7,0xbd,
+0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,
+0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xd7,0xbd,0xf7,0xbd,
+0xf7,0xbd,0xd6,0xb5,0x66,0x31,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x8e,0x73,0x55,0xad,0x55,0xad,0x55,0xad,0x75,0xad,0x95,0xb5,0x96,0xb5,0xb6,0xb5,
+0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,
+0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0x96,0xb5,
+0x96,0xad,0x96,0xb5,0xcf,0x7b,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x21,0x08,0x55,0xad,0xf7,0xbd,0xd7,0xbd,0xd6,0xb5,0xd7,0xbd,0xd7,0xbd,
+0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd6,0xbd,0xd7,0xb5,
+0xd6,0xbd,0xd7,0xb5,0xd7,0xbd,0xd6,0xb5,0xd6,0xbd,0xd7,0xbd,0x76,0xb5,0x04,0x21,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x2c,0x63,0xd7,0xbd,0xb6,0xb5,0xb6,0xb5,
+0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,
+0xd6,0xb5,0xb6,0xb5,0xd6,0xb5,0xb6,0xb5,0xd6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,
+0xd7,0xbd,0xaf,0x7b,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x08,0x42,0xf7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,
+0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,
+0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xf7,0xbd,0xd3,0x9c,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x49,0x4a,0xd6,0xb5,0xf7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,
+0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,
+0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,
+0xd7,0xbd,0xf7,0xbd,0x30,0x84,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x24,0x21,0xb6,0xb5,0xf8,0xc5,0x17,0xbe,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,
+0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,
+0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,
+0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,
+0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,
+0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,
+0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,
+0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0x18,0xbe,0x96,0xb5,0xa3,0x18,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x14,0xa5,0x17,0xbe,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,
+0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,
+0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xd6,0xb5,0x65,0x29,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0xaa,0x52,0x34,0xa5,0x34,0xa5,0x55,0xad,0x55,0xad,
+0x75,0xad,0x75,0xb5,0x96,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xd7,0xb5,
+0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd6,0xb5,0xb6,0xbd,
+0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0x96,0xb5,0x96,0xb5,0xd3,0x9c,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x34,0xa5,0xf7,0xbd,
+0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xb5,0xd7,0xbd,0xd6,0xb5,0xd7,0xbd,
+0xd7,0xb5,0xd7,0xbd,0xd7,0xb5,0xd7,0xbd,0xd6,0xbd,0xd7,0xbd,0xd6,0xb5,0xd7,0xbd,
+0xd7,0xb5,0xd7,0xbd,0x95,0xad,0x04,0x21,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x2c,0x63,0xd7,0xbd,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,
+0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xd6,0xb5,
+0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xd7,0xbd,0xae,0x73,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x08,0x42,0xf7,0xbd,
+0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,
+0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,
+0xd7,0xbd,0xd7,0xbd,0xf7,0xbd,0xd3,0x9c,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xeb,0x5a,0xd7,0xbd,0xf7,0xbd,
+0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,
+0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,
+0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xf7,0xbd,0xae,0x73,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x24,0x21,0xb6,0xb5,0x17,0xbe,
+0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,
+0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,
+0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,
+0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,
+0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,
+0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,
+0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0x17,0xbe,
+0x96,0xb5,0xa3,0x18,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x14,0xa5,0xf7,0xbd,0xf7,0xbd,
+0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,
+0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,
+0xf7,0xbd,0xd6,0xb5,0x65,0x29,0x00,0x00,0x00,0x00,0x00,0x00,0x65,0x29,0xf3,0x9c,
+0x34,0xa5,0x34,0xa5,0x55,0xad,0x55,0xad,0x75,0xad,0x95,0xb5,0x96,0xb5,0xb6,0xb5,
+0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xd6,0xb5,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,
+0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,
+0x55,0xad,0x86,0x31,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x14,0xa5,0xf7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd6,0xbd,
+0xd7,0xbd,0xd6,0xbd,0xd7,0xbd,0xd6,0xb5,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,
+0xd7,0xbd,0xd7,0xbd,0xd7,0xb5,0xd6,0xbd,0xd7,0xbd,0xd7,0xbd,0x76,0xb5,0x04,0x21,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x2c,0x63,0xd7,0xbd,0xb6,0xb5,0xb6,0xb5,
+0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,
+0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xd6,0xb5,0xb6,0xb5,0xb6,0xb5,0xd6,0xb5,
+0xd7,0xbd,0xaf,0x7b,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x08,0x42,0xf7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,
+0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,
+0xd7,0xbd,0xd7,0xbd,0xf7,0xbd,0xd7,0xbd,0xf7,0xbd,0xd7,0xbd,0xf7,0xbd,0xd3,0x9c,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x4d,0x6b,0xf7,0xbd,0xf7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,
+0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,
+0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,
+0xd7,0xbd,0xd7,0xbd,0xf7,0xbd,0xf7,0xbd,0x0c,0x63,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x04,0x21,0xb6,0xb5,0x17,0xbe,0xf7,0xbd,0xf7,0xbd,0x17,0xbe,0xf7,0xbd,
+0x17,0xbe,0xf7,0xbd,0x17,0xbe,0xf7,0xbd,0x17,0xbe,0xf7,0xbd,0x17,0xbe,0xf7,0xbd,
+0x17,0xbe,0xf7,0xbd,0x17,0xbe,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0x17,0xbe,0xf7,0xbd,
+0x17,0xbe,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,
+0x17,0xbe,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,
+0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0x17,0xbe,0xf7,0xbd,
+0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,
+0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0x18,0xc6,0x96,0xb5,0xa3,0x18,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x14,0xa5,0x18,0xbe,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,
+0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,
+0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xd7,0xbd,0x86,0x31,0x00,0x00,
+0x00,0x00,0x20,0x00,0x71,0x8c,0x14,0xa5,0x14,0xa5,0x34,0xa5,0x55,0xad,0x55,0xad,
+0x75,0xad,0x76,0xb5,0x96,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xd6,0xb5,0xd7,0xbd,
+0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,
+0xd6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xeb,0x5a,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x34,0xa5,0xf7,0xbd,
+0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,
+0xd6,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd6,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,
+0xd6,0xbd,0xd7,0xbd,0x96,0xb5,0x04,0x21,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x2c,0x63,0xd7,0xbd,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,
+0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xd6,0xb5,0xb6,0xb5,0xb6,0xb5,
+0xb6,0xb5,0xd6,0xb5,0xb6,0xb5,0xd6,0xb5,0xd7,0xbd,0xce,0x73,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x08,0x42,0xf7,0xbd,
+0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,
+0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,
+0xd7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf3,0x9c,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xcf,0x7b,
+0xf7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,
+0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,
+0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xf7,0xbd,
+0xd7,0xbd,0x89,0x52,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x24,0x21,0xb6,0xb5,0x17,0xbe,
+0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0x17,0xbe,
+0xf7,0xbd,0x17,0xbe,0xf7,0xbd,0x17,0xbe,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,
+0xf7,0xbd,0x17,0xbe,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,
+0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0x17,0xbe,0xf7,0xbd,0xf7,0xbd,
+0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,
+0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,
+0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0x17,0xbe,
+0x96,0xb5,0xa3,0x10,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x14,0xa5,0xf7,0xc5,0xf7,0xbd,
+0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,
+0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,
+0xf7,0xbd,0xf7,0xbd,0xc7,0x39,0x00,0x00,0x00,0x00,0x8e,0x73,0xf3,0x9c,0xf3,0x9c,
+0x14,0xa5,0x34,0xa5,0x55,0xad,0x55,0xad,0x75,0xad,0x96,0xad,0x96,0xb5,0xb6,0xb5,
+0xb6,0xb5,0xd6,0xb5,0xd7,0xb5,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,
+0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd6,0xb5,0xb6,0xb5,0xb6,0xb5,0xd6,0xbd,0x10,0x84,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x14,0xa5,0xf7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,
+0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd6,0xbd,0xd7,0xbd,0xd6,0xbd,0xd7,0xbd,0xd6,0xb5,
+0xd7,0xbd,0xd7,0xb5,0xd6,0xbd,0xd6,0xb5,0xd7,0xbd,0xd7,0xbd,0x76,0xb5,0x04,0x21,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x2c,0x63,0xd7,0xbd,0xb6,0xb5,0xb6,0xb5,
+0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xd6,0xb5,0xb6,0xb5,
+0xd6,0xb5,0xd6,0xb5,0xb6,0xb5,0xd6,0xb5,0xb6,0xb5,0xd6,0xb5,0xd6,0xb5,0xb6,0xb5,
+0xf7,0xbd,0x8e,0x73,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x08,0x42,0xf7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,
+0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,
+0xf7,0xbd,0xd7,0xbd,0xf7,0xbd,0xd7,0xbd,0xf7,0xbd,0xd7,0xbd,0x17,0xbe,0xd3,0x9c,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x50,0x84,0xf7,0xbd,0xd7,0xbd,0xd7,0xbd,
+0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,
+0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,
+0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xf7,0xbd,0xb6,0xb5,0xe8,0x41,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x24,0x21,0xb6,0xb5,0x17,0xc6,0xf7,0xbd,0x17,0xbe,0x17,0xbe,0xf7,0xbd,
+0xf7,0xbd,0x17,0xbe,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0x17,0xbe,0xf7,0xbd,0xf7,0xbd,
+0x17,0xbe,0x17,0xbe,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,
+0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0x17,0xbe,0xf7,0xbd,
+0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0x17,0xbe,0xf7,0xbd,0x17,0xbe,0xf7,0xbd,
+0xf7,0xbd,0xf7,0xbd,0x17,0xbe,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,
+0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0x17,0xbe,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,
+0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0x18,0xc6,0x96,0xb5,0xa3,0x18,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x14,0xa5,0x17,0xc6,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,
+0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,
+0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xa7,0x39,0x00,0x00,
+0xaa,0x52,0xd3,0x9c,0xf3,0x9c,0xf3,0xa4,0x14,0xa5,0x34,0xa5,0x55,0xad,0x55,0xad,
+0x75,0xad,0x96,0xb5,0x96,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xd6,0xb5,0xd7,0xbd,
+0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd6,0xb5,
+0xb6,0xb5,0xd7,0xbd,0xf3,0x9c,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x34,0xa5,0xf7,0xbd,
+0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,
+0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,
+0xd7,0xb5,0xd7,0xbd,0x96,0xb5,0x04,0x21,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x2c,0x63,0xd7,0xbd,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,
+0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xd6,0xb5,0xb6,0xb5,0xd6,0xb5,
+0xd6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xd7,0xbd,0x8e,0x73,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x08,0x42,0xf7,0xbd,
+0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,
+0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xf7,0xbd,0xd7,0xbd,0xf7,0xbd,0xd7,0xbd,0xf7,0xbd,
+0xd7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf3,0x9c,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x92,0x94,0xf7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,
+0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,
+0xd7,0xbd,0xd7,0xb5,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,
+0xd7,0xbd,0xf7,0xbd,0x75,0xad,0x65,0x29,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x24,0x21,0xb6,0xb5,0x17,0xbe,
+0xf7,0xbd,0x17,0xbe,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0x17,0xbe,
+0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0x17,0xbe,0xf7,0xbd,0xf7,0xbd,
+0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,
+0xf7,0xbd,0x17,0xbe,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0x17,0xbe,0xf7,0xbd,0x17,0xbe,
+0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0x17,0xbe,
+0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0x17,0xbe,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0x17,0xbe,
+0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0x17,0xbe,
+0x96,0xb5,0xa3,0x10,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x14,0xa5,0x17,0xbe,0xf7,0xbd,
+0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,
+0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,
+0xf7,0xbd,0xf7,0xbd,0x65,0x29,0x45,0x29,0x92,0x94,0xd2,0x9c,0xd3,0x9c,0x13,0x9d,
+0x14,0xa5,0x54,0xa5,0x55,0xad,0x75,0xad,0x75,0xad,0x96,0xb5,0x96,0xb5,0xb6,0xb5,
+0xb6,0xb5,0xb6,0xb5,0xd7,0xb5,0xd6,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,
+0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd6,0xb5,0xd6,0xbd,0x96,0xb5,0x86,0x31,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x34,0xa5,0xf7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,
+0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,
+0xd7,0xbd,0xd6,0xb5,0xd7,0xbd,0xd7,0xb5,0xd7,0xbd,0xd7,0xbd,0x96,0xb5,0x04,0x21,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x2c,0x63,0xd7,0xbd,0xb6,0xb5,0xb6,0xb5,
+0xd6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xd6,0xb5,0xb6,0xb5,0xb6,0xb5,0xd6,0xb5,
+0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xd6,0xb5,0xd6,0xbd,
+0xf7,0xbd,0x8e,0x73,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x08,0x42,0xf7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,
+0xd7,0xbd,0xd7,0xbd,0xf7,0xbd,0xd7,0xbd,0xf7,0xbd,0xd7,0xbd,0xf7,0xbd,0xd7,0xbd,
+0xf7,0xbd,0xd7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0x17,0xbe,0xf3,0x9c,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xf3,0x9c,0xf7,0xbd,
+0xd6,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd6,0xb5,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,
+0xd7,0xb5,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xb5,0xd7,0xbd,0xd7,0xb5,0xd7,0xbd,
+0xd7,0xbd,0xd7,0xbd,0xd6,0xbd,0xd7,0xbd,0xd7,0xb5,0xd7,0xbd,0xf7,0xbd,0x34,0xa5,
+0xa3,0x10,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x24,0x21,0xb6,0xb5,0x18,0xc6,0x17,0xbe,0x17,0xbe,0x17,0xbe,0x17,0xbe,
+0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0x17,0xbe,0xf7,0xbd,0x17,0xbe,
+0x17,0xbe,0x17,0xbe,0x17,0xbe,0xf7,0xbd,0x17,0xbe,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,
+0x17,0xbe,0x17,0xbe,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0x17,0xbe,0x17,0xbe,0xf7,0xbd,
+0x17,0xbe,0x17,0xbe,0x17,0xbe,0xf7,0xbd,0xf7,0xbd,0x17,0xbe,0x17,0xbe,0x17,0xbe,
+0x17,0xbe,0x17,0xbe,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0x17,0xbe,0xf7,0xbd,
+0x17,0xbe,0xf7,0xbd,0x17,0xbe,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,
+0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0x18,0xc6,0x96,0xb5,0xa3,0x18,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x14,0xa5,0x17,0xbe,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,
+0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,
+0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xd7,0xbd,0x89,0x4a,0xef,0x83,
+0xb2,0x94,0xd2,0x94,0xf3,0x9c,0x13,0x9d,0x34,0xa5,0x34,0xa5,0x55,0xad,0x75,0xad,
+0x75,0xad,0x96,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xd6,0xb5,0xd6,0xbd,0xd7,0xbd,
+0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,
+0xd7,0xbd,0xec,0x62,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x34,0xa5,0xf7,0xbd,
+0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,
+0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,
+0xd7,0xbd,0xd7,0xbd,0x96,0xb5,0x04,0x21,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x2c,0x63,0xd7,0xbd,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xd6,0xb5,
+0xb6,0xb5,0xd6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xd6,0xb5,0xd6,0xb5,0xb6,0xb5,
+0xd6,0xb5,0xb6,0xb5,0xb6,0xb5,0xd6,0xb5,0xd7,0xbd,0x8e,0x73,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x08,0x42,0xf7,0xbd,
+0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,
+0xd7,0xbd,0xf7,0xbd,0xd7,0xbd,0xf7,0xbd,0xd7,0xbd,0xf7,0xbd,0xd7,0xbd,0xf7,0xbd,
+0xf7,0xbd,0xf7,0xbd,0x17,0xbe,0xf3,0x9c,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0xa2,0x10,0x34,0xa5,0xd7,0xbd,0xd6,0xb5,0xd6,0xb5,0xd6,0xb5,
+0xd7,0xbd,0xd6,0xb5,0xb7,0xbd,0xd6,0xb5,0xd6,0xbd,0xd6,0xb5,0xb7,0xb5,0xd6,0xb5,
+0xb7,0xbd,0xd6,0xb5,0xd7,0xb5,0xd6,0xb5,0xd7,0xbd,0xd6,0xb5,0xb7,0xb5,0xd6,0xb5,
+0xd7,0xbd,0xd6,0xb5,0xd7,0xb5,0xf7,0xbd,0xd3,0x9c,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x24,0x21,0xb6,0xb5,0x18,0xc6,
+0x17,0xbe,0xf7,0xbd,0x17,0xbe,0xf7,0xbd,0x17,0xbe,0x17,0xbe,0x17,0xbe,0x17,0xbe,
+0x17,0xbe,0x17,0xbe,0xf7,0xbd,0x17,0xbe,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,
+0xf7,0xbd,0xf7,0xbd,0xf7,0xc5,0xf7,0xbd,0x18,0xbe,0x17,0xbe,0xf7,0xbd,0x17,0xbe,
+0x18,0xbe,0x17,0xbe,0xf8,0xc5,0x17,0xbe,0xf7,0xbd,0x17,0xbe,0xf8,0xc5,0x17,0xbe,
+0xf8,0xbd,0x17,0xbe,0xf8,0xc5,0x17,0xbe,0x18,0xc6,0x17,0xbe,0xf8,0xc5,0x17,0xbe,
+0xf8,0xc5,0x17,0xbe,0x17,0xc6,0x17,0xbe,0xf7,0xc5,0x17,0xbe,0x17,0xbe,0x17,0xbe,
+0x18,0xbe,0x17,0xbe,0x17,0xc6,0xf7,0xbd,0xf8,0xbd,0xf7,0xbd,0xf7,0xbd,0x38,0xc6,
+0x34,0xa5,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x14,0xa5,0x17,0xc6,0xf7,0xbd,
+0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,
+0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,
+0xf7,0xbd,0xf7,0xbd,0x51,0x8c,0x71,0x8c,0x92,0x94,0xd2,0x94,0xf3,0x9c,0x13,0x9d,
+0x14,0xa5,0x54,0xa5,0x55,0xad,0x75,0xad,0x75,0xad,0x96,0xb5,0x96,0xb5,0xb6,0xb5,
+0xb6,0xb5,0xd6,0xb5,0xd6,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,
+0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xf7,0xbd,0x10,0x84,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x34,0xa5,0xf7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,
+0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,
+0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0x76,0xb5,0x04,0x21,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x2c,0x63,0xd7,0xbd,0xb6,0xb5,0xb6,0xb5,
+0xb6,0xb5,0xb6,0xb5,0xd6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xd6,0xb5,0xb6,0xb5,
+0xd6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb7,0xb5,0xd6,0xb5,0xd6,0xb5,0xd6,0xb5,0xd7,0xbd,
+0xf7,0xbd,0x8e,0x73,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x08,0x42,0xf7,0xbd,0xf7,0xbd,0xd7,0xbd,0xf7,0xbd,0xd7,0xbd,
+0xf7,0xbd,0xd7,0xbd,0xf7,0xbd,0xd7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xd7,0xbd,
+0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0x17,0xbe,0xb2,0x94,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x25,0x29,
+0x55,0xad,0xd7,0xbd,0xb6,0xb5,0xd6,0xb5,0xb6,0xb5,0xd6,0xb5,0xd6,0xb5,0xb6,0xb5,
+0xd6,0xb5,0xd6,0xb5,0xd6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xd6,0xb5,
+0xd6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xd6,0xb5,0xb6,0xbd,0xb6,0xb5,0xd7,0xb5,
+0xf7,0xbd,0x71,0x8c,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x24,0x21,0xb6,0xb5,0x18,0xc6,0x17,0xbe,0x17,0xc6,0xf7,0xbd,0xf8,0xbd,
+0x17,0xbe,0xf7,0xc5,0xf7,0xbd,0x18,0xbe,0x17,0xbe,0xf7,0xc5,0xf7,0xbd,0xf8,0xbd,
+0x17,0xbe,0xf7,0xc5,0x17,0xbe,0x17,0xbe,0x17,0xbe,0xf7,0xc5,0x17,0xbe,0x18,0xc6,
+0x17,0xbe,0xf8,0xbd,0x17,0xbe,0x18,0xc6,0x17,0xbe,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,
+0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xf7,0xbd,0xd7,0xbd,0xf7,0xbd,0xf7,0xbd,0xd7,0xbd,
+0xd7,0xbd,0xf7,0xbd,0xd7,0xbd,0xd7,0xbd,0xf7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,
+0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,
+0xd7,0xbd,0xd7,0xbd,0xf7,0xbd,0x55,0xad,0xc7,0x39,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x14,0xa5,0x18,0xbe,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,
+0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,
+0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xb2,0x94,0x51,0x8c,
+0xb2,0x94,0xd3,0x9c,0xf3,0x9c,0x14,0xa5,0x34,0xa5,0x34,0xa5,0x55,0xad,0x75,0xad,
+0x75,0xad,0x96,0xb5,0xb6,0xb5,0xb6,0xb5,0xd6,0xb5,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,
+0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xf7,0xbd,0x14,0xa5,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x34,0xa5,0xf7,0xbd,
+0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,
+0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,
+0xd7,0xbd,0xd7,0xbd,0x96,0xb5,0x25,0x29,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x2c,0x63,0xd7,0xbd,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xd6,0xb5,0xb6,0xb5,0xd6,0xb5,
+0xb6,0xb5,0xd6,0xb5,0xd6,0xb5,0xd6,0xb5,0xb6,0xb5,0xd6,0xb5,0xb6,0xb5,0xd6,0xb5,
+0xd6,0xbd,0xd6,0xb5,0xd6,0xb5,0xd6,0xb5,0xd7,0xbd,0x8e,0x73,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x08,0x42,0x17,0xbe,
+0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xf7,0xbd,0xd7,0xbd,0xf7,0xbd,0xd7,0xbd,0xf7,0xbd,
+0xd7,0xbd,0xf7,0xbd,0xd7,0xbd,0xf7,0xbd,0xd7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,
+0xf7,0xbd,0xf7,0xbd,0xf8,0xc5,0x92,0x94,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xc7,0x39,0x75,0xad,0xd7,0xb5,0xb6,0xb5,
+0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,
+0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,
+0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xf7,0xbd,0xef,0x7b,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x24,0x21,0xb6,0xb5,0x18,0xc6,
+0x17,0xbe,0xf7,0xbd,0x18,0xbe,0x17,0xbe,0x17,0xc6,0xf7,0xbd,0x18,0xbe,0x17,0xbe,
+0x17,0xbe,0x17,0xbe,0x18,0xbe,0x17,0xbe,0xf7,0xc5,0xf7,0xbd,0xf8,0xbd,0x17,0xbe,
+0x18,0xc6,0x96,0xb5,0x28,0x42,0xa6,0x31,0xc7,0x39,0xa7,0x39,0xc7,0x39,0xc7,0x39,
+0xa6,0x31,0x65,0x29,0x66,0x31,0x65,0x29,0x66,0x31,0x65,0x29,0x66,0x31,0x65,0x29,
+0x66,0x31,0x65,0x29,0x66,0x31,0x65,0x29,0x66,0x31,0x65,0x29,0x66,0x31,0x65,0x29,
+0x66,0x31,0x65,0x29,0x66,0x31,0x65,0x29,0x66,0x31,0x65,0x29,0x66,0x31,0x65,0x29,
+0x66,0x31,0x65,0x29,0x66,0x31,0x65,0x31,0x66,0x31,0x65,0x29,0x65,0x29,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x14,0xa5,0x18,0xc6,0xf7,0xbd,
+0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,
+0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,
+0xf7,0xbd,0xf7,0xbd,0xb2,0x94,0x71,0x8c,0x92,0x94,0xd3,0x9c,0xf3,0x9c,0x13,0xa5,
+0x34,0xa5,0x54,0xa5,0x55,0xad,0x75,0xad,0x76,0xb5,0x96,0xb5,0x96,0xb5,0xb6,0xb5,
+0xb6,0xb5,0xd6,0xb5,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,
+0xd7,0xbd,0xf7,0xbd,0x96,0xb5,0x86,0x31,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x34,0xa5,0xf7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,
+0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,
+0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xb6,0xb5,0x65,0x29,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x2c,0x6b,0xd7,0xbd,0xb6,0xb5,0xd6,0xb5,
+0xd6,0xb5,0xd6,0xb5,0xd6,0xb5,0xd6,0xb5,0xd6,0xb5,0xb6,0xb5,0xd6,0xb5,0xb6,0xbd,
+0xd6,0xb5,0xd7,0xb5,0xd6,0xb5,0xd7,0xbd,0xd6,0xb5,0xd7,0xb5,0xd7,0xb5,0xd7,0xbd,
+0xf7,0xbd,0x8e,0x73,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x08,0x42,0x17,0xbe,0xf7,0xbd,0xd7,0xbd,0xf7,0xbd,0xd7,0xbd,
+0xf7,0xbd,0xd7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,
+0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0x18,0xbe,0x92,0x94,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x49,0x4a,0x96,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,
+0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,
+0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,
+0xb6,0xb5,0xb6,0xb5,0xd7,0xbd,0x4d,0x6b,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x24,0x21,0xb6,0xb5,0x18,0xc6,0x17,0xbe,0xf7,0xc5,0x17,0xbe,0x18,0xc6,
+0x17,0xbe,0xf8,0xc5,0x17,0xbe,0x17,0xbe,0x17,0xbe,0xf8,0xbd,0x17,0xbe,0xf8,0xc5,
+0x17,0xbe,0xf8,0xc5,0x17,0xbe,0x18,0xbe,0x18,0xc6,0x75,0xad,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x14,0xa5,0x18,0xc6,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,
+0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,
+0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xb2,0x94,0x71,0x8c,
+0xb2,0x94,0xd3,0x9c,0xf3,0x9c,0x14,0xa5,0x34,0xa5,0x55,0xad,0x55,0xad,0x75,0xad,
+0x95,0xb5,0x96,0xb5,0xb6,0xb5,0xb6,0xb5,0xd6,0xb5,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,
+0xf7,0xbd,0xd7,0xbd,0xf7,0xbd,0xd7,0xbd,0xf7,0xbd,0xf7,0xbd,0xec,0x62,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x34,0xa5,0xf7,0xbd,
+0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,
+0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,
+0xd7,0xbd,0xd7,0xbd,0xb6,0xb5,0x65,0x29,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x2c,0x63,0xd7,0xbd,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xd6,0xb5,
+0xb6,0xb5,0xd6,0xb5,0xd6,0xb5,0xb6,0xb5,0xb6,0xb5,0xd6,0xb5,0xb6,0xb5,0xd6,0xb5,
+0xb6,0xb5,0xd6,0xb5,0xd6,0xbd,0xd6,0xb5,0xf7,0xbd,0x8e,0x73,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x08,0x42,0xf7,0xbd,
+0xd7,0xbd,0xf7,0xbd,0xd7,0xbd,0xf7,0xbd,0xd7,0xbd,0xf7,0xbd,0xd7,0xbd,0xf7,0xbd,
+0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,
+0xf7,0xbd,0xf7,0xbd,0x18,0xbe,0x92,0x94,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xab,0x5a,0x96,0xb5,
+0x96,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,
+0x96,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,
+0x96,0xb5,0x96,0xb5,0x96,0xb5,0xb6,0xb5,0x96,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,
+0xaa,0x52,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x24,0x21,0xb6,0xb5,0x18,0xbe,
+0xf8,0xc5,0x17,0xbe,0xf7,0xc5,0x17,0xbe,0xf8,0xc5,0x17,0xbe,0x18,0xbe,0x17,0xbe,
+0x17,0xc6,0x17,0xbe,0xf8,0xc5,0x17,0xbe,0xf8,0xbd,0x17,0xbe,0xf7,0xc5,0x17,0xbe,
+0x18,0xc6,0x75,0xad,0x21,0x08,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x14,0xa5,0x18,0xc6,0xf7,0xbd,
+0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,
+0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,
+0xf7,0xbd,0xf7,0xbd,0xb2,0x94,0x71,0x8c,0xb2,0x94,0xd3,0x9c,0xf3,0x9c,0x14,0xa5,
+0x34,0xa5,0x54,0xa5,0x55,0xad,0x75,0xad,0x96,0xb5,0x96,0xb5,0x96,0xb5,0xb6,0xb5,
+0xb6,0xb5,0xd6,0xb5,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xf7,0xbd,0xd7,0xbd,0xd7,0xbd,
+0xf7,0xbd,0x30,0x84,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x34,0xa5,0xf7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,
+0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,
+0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xb5,0xd7,0xbd,0xd7,0xbd,0xb6,0xb5,0x65,0x29,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x2c,0x63,0xd7,0xbd,0xb6,0xb5,0xb6,0xb5,
+0xb6,0xb5,0xd6,0xb5,0xb6,0xb5,0xd6,0xb5,0xd6,0xb5,0xd6,0xb5,0xd6,0xb5,0xb7,0xbd,
+0xd6,0xb5,0xb6,0xb5,0xd6,0xb5,0xd6,0xb5,0xd7,0xb5,0xd7,0xb5,0xd6,0xbd,0xd6,0xbd,
+0xf7,0xbd,0x8e,0x73,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x08,0x42,0x17,0xbe,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,
+0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,
+0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0x18,0xbe,0x92,0x94,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x2d,0x63,0x96,0xb5,0x96,0xb5,0x76,0xb5,0x96,0xad,
+0x96,0xb5,0x95,0xb5,0x96,0xad,0x76,0xb5,0x96,0xad,0x76,0xb5,0x96,0xb5,0x96,0xb5,
+0x96,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,
+0x96,0xb5,0x96,0xb5,0x96,0xb5,0xb6,0xb5,0x96,0xb5,0x28,0x42,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x24,0x21,0xd6,0xb5,0x18,0xc6,0x18,0xbe,0x18,0xc6,0x18,0xc6,0x18,0xc6,
+0x17,0xc6,0x17,0xc6,0x17,0xc6,0x17,0xc6,0x18,0xbe,0x18,0xc6,0x18,0xc6,0x18,0xc6,
+0x17,0xbe,0x17,0xbe,0x17,0xbe,0x18,0xbe,0x18,0xc6,0x75,0xad,0x41,0x08,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0xf3,0x9c,0x18,0xc6,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,
+0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,
+0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xd2,0x94,0x71,0x8c,
+0xb2,0x94,0xd3,0x9c,0xf3,0x9c,0x14,0xa5,0x34,0xa5,0x55,0xad,0x55,0xad,0x75,0xad,
+0x96,0xb5,0x96,0xb5,0xb6,0xb5,0xb6,0xb5,0xd6,0xb5,0xd6,0xbd,0xd7,0xbd,0xd7,0xbd,
+0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0x14,0xa5,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x34,0xa5,0xf7,0xbd,
+0xf7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,
+0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,
+0xd7,0xbd,0xd7,0xbd,0xb6,0xb5,0x65,0x29,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x2c,0x63,0xd7,0xbd,0xb6,0xb5,0xd6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xd6,0xb5,
+0xd6,0xb5,0xb6,0xb5,0xb7,0xb5,0xd6,0xb5,0xd7,0xb5,0xd6,0xb5,0xd6,0xb5,0xd6,0xb5,
+0xb6,0xb5,0xd6,0xb5,0xd6,0xbd,0xd6,0xb5,0xf7,0xbd,0x8e,0x73,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x08,0x42,0xf7,0xbd,
+0xd7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,
+0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,
+0xf7,0xbd,0xf7,0xbd,0x17,0xc6,0x92,0x94,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x8e,0x73,0x95,0xb5,0x75,0xad,0x75,0xad,0x75,0xad,0x75,0xad,0x75,0xad,0x75,0xad,
+0x75,0xad,0x75,0xad,0x75,0xad,0x75,0xad,0x75,0xad,0x75,0xad,0x75,0xad,0x75,0xad,
+0x75,0xad,0x75,0xad,0x76,0xad,0x75,0xad,0x76,0xad,0x95,0xad,0x76,0xb5,0x95,0xad,
+0x96,0xb5,0x55,0xad,0xa6,0x31,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x24,0x21,0xb6,0xb5,0x18,0xc6,
+0xf8,0xc5,0x17,0xbe,0x18,0xc6,0x17,0xc6,0xf8,0xc5,0x18,0xbe,0x17,0xbe,0x17,0xc6,
+0xf7,0xbd,0x18,0xbe,0x18,0xc6,0x17,0xbe,0xf8,0xbd,0x17,0xbe,0x18,0xc6,0x17,0xc6,
+0x18,0xc6,0x75,0xad,0x21,0x08,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xf3,0x9c,0x18,0xc6,0xf7,0xbd,
+0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,
+0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,
+0xf7,0xbd,0xf7,0xbd,0xb2,0x94,0x71,0x8c,0xb2,0x94,0xd3,0x9c,0xf3,0x9c,0x14,0xa5,
+0x34,0xa5,0x55,0xad,0x55,0xad,0x75,0xad,0x96,0xb5,0x96,0xb5,0xb6,0xb5,0xb6,0xb5,
+0xb6,0xb5,0xd7,0xb5,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xf7,0xbd,0xf7,0xbd,0xb6,0xb5,
+0x86,0x31,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x34,0xa5,0xf7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,
+0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,
+0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xb6,0xb5,0x65,0x29,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x2c,0x63,0xd7,0xbd,0xb6,0xb5,0xb6,0xb5,
+0xd6,0xb5,0xd7,0xb5,0xd6,0xb5,0xb7,0xb5,0xd6,0xb5,0xb7,0xb5,0xd6,0xb5,0xd7,0xbd,
+0xd6,0xbd,0xd6,0xb5,0xd6,0xbd,0xd6,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,
+0xf7,0xbd,0x8e,0x73,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x08,0x42,0x17,0xbe,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,
+0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,
+0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0x18,0xc6,0x92,0x94,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xcf,0x7b,0x75,0xad,0x55,0xad,
+0x55,0xad,0x55,0xad,0x55,0xad,0x55,0xad,0x55,0xad,0x55,0xad,0x75,0xad,0x55,0xad,
+0x55,0xad,0x55,0xad,0x55,0xad,0x55,0xad,0x75,0xad,0x55,0xad,0x75,0xad,0x75,0xad,
+0x75,0xad,0x75,0xad,0x75,0xad,0x75,0xad,0x75,0xad,0x96,0xb5,0x14,0xa5,0x04,0x21,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x24,0x21,0xd6,0xb5,0x18,0xc6,0x17,0xc6,0x17,0xc6,0x18,0xbe,0x17,0xbe,
+0x18,0xc6,0x17,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xbe,0x17,0xc6,0x18,0xbe,0x17,0xc6,
+0x18,0xc6,0x18,0xc6,0x17,0xc6,0x18,0xbe,0x18,0xc6,0x75,0xad,0x41,0x08,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0xf3,0x9c,0x18,0xc6,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0x17,0xbe,0xf7,0xbd,
+0x17,0xbe,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,
+0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xd2,0x94,0x71,0x8c,
+0xb2,0x94,0xd3,0x9c,0xf3,0x9c,0x14,0xa5,0x34,0xa5,0x55,0xad,0x75,0xad,0x75,0xad,
+0x96,0xb5,0x96,0xb5,0xb6,0xb5,0xb6,0xb5,0xd6,0xb5,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,
+0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xeb,0x5a,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x14,0xa5,0xf7,0xbd,
+0xf7,0xbd,0xd7,0xbd,0xf7,0xbd,0xd7,0xbd,0xf7,0xbd,0xd7,0xbd,0xf7,0xbd,0xd7,0xbd,
+0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,
+0xd7,0xbd,0xd7,0xbd,0xb6,0xb5,0x65,0x29,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x4d,0x6b,0xd7,0xbd,0xd6,0xb5,0xd6,0xb5,0xd6,0xb5,0xb6,0xb5,0xd6,0xb5,0xb6,0xb5,
+0xb7,0xb5,0xd6,0xb5,0xb7,0xb5,0xd6,0xb5,0xd6,0xbd,0xd6,0xb5,0xb6,0xbd,0xd7,0xb5,
+0xd6,0xb5,0xd7,0xbd,0xd6,0xb5,0xd7,0xbd,0xf7,0xbd,0x8e,0x73,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x08,0x42,0xf7,0xbd,
+0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,
+0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,
+0xf7,0xbd,0xf7,0xbd,0x18,0xc6,0x92,0x94,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x10,0x84,0x55,0xad,0x34,0xa5,0x34,0xa5,0x34,0xa5,0x34,0xa5,
+0x34,0xa5,0x34,0xa5,0x34,0xa5,0x54,0xa5,0x34,0xa5,0x54,0xa5,0x54,0xa5,0x54,0xa5,
+0x35,0xad,0x54,0xad,0x55,0xad,0x55,0xad,0x55,0xad,0x55,0xad,0x55,0xad,0x55,0xad,
+0x75,0xad,0x75,0xad,0x96,0xb5,0xd2,0x94,0x41,0x08,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x24,0x21,0xb6,0xb5,0x18,0xc6,
+0x18,0xc6,0x18,0xbe,0x17,0xc6,0x17,0xbe,0x18,0xc6,0x17,0xc6,0x18,0xc6,0x18,0xc6,
+0x18,0xc6,0x17,0xc6,0x18,0xc6,0x18,0xbe,0x18,0xc6,0x17,0xc6,0x18,0xc6,0x18,0xc6,
+0x18,0xc6,0x75,0xad,0x21,0x08,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xf3,0x9c,0x18,0xc6,0x17,0xbe,
+0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,
+0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,
+0xf7,0xbd,0xf7,0xbd,0xd3,0x9c,0x71,0x8c,0xb2,0x94,0xd3,0x9c,0xf3,0x9c,0x14,0xa5,
+0x34,0xa5,0x55,0xad,0x55,0xad,0x75,0xad,0x96,0xb5,0x96,0xb5,0xb6,0xb5,0xb6,0xb5,
+0xd6,0xb5,0xd6,0xb5,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0x17,0xc6,0x10,0x84,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x13,0x9d,0xf7,0xbd,0xd7,0xbd,0xf7,0xbd,0xd7,0xbd,0xd7,0xbd,
+0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,
+0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0x96,0xb5,0x65,0x29,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x8e,0x73,0xd7,0xbd,0xd6,0xb5,0xd7,0xb5,
+0xd6,0xb5,0xb7,0xbd,0xd6,0xb5,0xd7,0xbd,0xd6,0xb5,0xd7,0xbd,0xd6,0xb5,0xd7,0xbd,
+0xd6,0xb5,0xd7,0xbd,0xd6,0xb5,0xd6,0xbd,0xd6,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,
+0xf7,0xbd,0x8e,0x73,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x08,0x42,0xf8,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,
+0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,
+0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0x17,0xc6,0x92,0x94,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x51,0x8c,
+0x34,0xa5,0x14,0xa5,0x14,0xa5,0x14,0xa5,0x14,0xa5,0x14,0xa5,0x14,0xa5,0x14,0xa5,
+0x34,0xa5,0x14,0xa5,0x34,0xa5,0x14,0xa5,0x34,0xa5,0x34,0xa5,0x34,0xa5,0x34,0xa5,
+0x34,0xa5,0x34,0xa5,0x54,0xa5,0x54,0xad,0x55,0xad,0x55,0xad,0x55,0xad,0x76,0xb5,
+0x71,0x8c,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x24,0x21,0xd6,0xb5,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,
+0x17,0xbe,0x18,0xc6,0x17,0xc6,0x18,0xc6,0x17,0xbe,0x18,0xc6,0x17,0xc6,0x18,0xc6,
+0x17,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x38,0xc6,0x75,0xad,0x41,0x08,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0xf3,0x9c,0x18,0xc6,0xf7,0xbd,0x17,0xbe,0xf7,0xbd,0x17,0xbe,0xf7,0xbd,
+0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,
+0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0x17,0xbe,0xf7,0xbd,0xd2,0x9c,0x71,0x94,
+0xd2,0x94,0xd3,0x9c,0x13,0x9d,0x34,0xa5,0x54,0xa5,0x55,0xad,0x75,0xad,0x76,0xad,
+0x96,0xb5,0x96,0xb5,0xb6,0xb5,0xb6,0xb5,0xd6,0xb5,0xd6,0xbd,0xd7,0xbd,0xd7,0xbd,
+0x17,0xbe,0x14,0xa5,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x13,0xa5,0xf7,0xbd,
+0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xd7,0xbd,0xf7,0xbd,0xd7,0xbd,0xf7,0xbd,0xd7,0xbd,
+0xf7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,
+0xd6,0xb5,0xd7,0xbd,0xb6,0xb5,0x65,0x29,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x8e,0x73,0xf7,0xbd,0xd6,0xb5,0xd6,0xb5,0xb6,0xb5,0xd6,0xb5,0xd7,0xb5,0xd6,0xb5,
+0xb7,0xbd,0xd6,0xb5,0xb6,0xbd,0xd6,0xb5,0xd6,0xb5,0xd7,0xbd,0xd6,0xb5,0xd6,0xb5,
+0xd7,0xb5,0xd7,0xbd,0xd7,0xbd,0xd6,0xb5,0xf7,0xbd,0x8e,0x73,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x08,0x42,0x17,0xbe,
+0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,
+0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,
+0xf7,0xbd,0xf7,0xbd,0x18,0xc6,0xb2,0x94,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x62,0x08,0x71,0x8c,0x14,0xa5,0xf3,0x9c,0xf3,0x9c,
+0xf3,0x9c,0xf3,0x9c,0xf3,0x9c,0x13,0x9d,0xf3,0xa4,0x13,0x9d,0xf3,0x9c,0x13,0x9d,
+0x14,0xa5,0x14,0x9d,0x14,0xa5,0x14,0xa5,0x14,0xa5,0x34,0xa5,0x14,0xa5,0x34,0xa5,
+0x34,0xa5,0x34,0xa5,0x34,0xa5,0x54,0xa5,0x75,0xad,0xef,0x7b,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x24,0x21,0xd6,0xb5,0x18,0xc6,
+0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xbe,0x18,0xc6,0x17,0xbe,0x18,0xc6,0x17,0xbe,
+0x18,0xc6,0x17,0xc6,0x18,0xc6,0x18,0xbe,0x17,0xc6,0x18,0xc6,0x18,0xc6,0x17,0xbe,
+0x18,0xc6,0x75,0xad,0x41,0x08,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xf3,0x9c,0x18,0xc6,0x17,0xbe,
+0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0x17,0xbe,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,
+0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,
+0xf7,0xbd,0xf7,0xbd,0xd3,0x9c,0x91,0x8c,0xb2,0x94,0xf3,0x9c,0xf3,0x9c,0x14,0xa5,
+0x34,0xa5,0x55,0xad,0x75,0xad,0x75,0xad,0x96,0xb5,0x96,0xb5,0xb6,0xb5,0xb6,0xb5,
+0xb7,0xbd,0xd6,0xbd,0xd7,0xbd,0xf7,0xbd,0xb6,0xb5,0x66,0x31,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x14,0xa5,0xf7,0xbd,0xd7,0xbd,0xf7,0xbd,0xd7,0xbd,0xf7,0xbd,
+0xd7,0xbd,0xf7,0xbd,0xd7,0xbd,0xf7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,
+0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd6,0xb5,0x96,0xb5,0x65,0x29,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x8e,0x73,0xd7,0xbd,0xd6,0xb5,0xd6,0xb5,
+0xd6,0xb5,0xb7,0xbd,0xd6,0xb5,0xd7,0xbd,0xd7,0xb5,0xd6,0xb5,0xd6,0xbd,0xd7,0xbd,
+0xd6,0xbd,0xd7,0xbd,0xd7,0xb5,0xd7,0xbd,0xd7,0xb5,0xd7,0xbd,0xd6,0xbd,0xd7,0xbd,
+0xf7,0xbd,0x8e,0x73,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x08,0x42,0x17,0xc6,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,
+0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,
+0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0x18,0xc6,0x92,0x94,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0xe3,0x18,0x72,0x94,0xf3,0x9c,0xd3,0x9c,0xd3,0x9c,0xd3,0x9c,0xd3,0x9c,0xd3,0x9c,
+0xf3,0x9c,0xd3,0x9c,0xf3,0x9c,0xd3,0x9c,0xf3,0x9c,0xf3,0x9c,0xf3,0x9c,0xf3,0x9c,
+0xf3,0x9c,0xf3,0x9c,0x13,0x9d,0x14,0xa5,0x14,0xa5,0x34,0xa5,0x34,0xa5,0x34,0xa5,
+0x54,0xa5,0x55,0xad,0x4d,0x6b,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x24,0x21,0xd6,0xb5,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x17,0xc6,0x18,0xc6,
+0x17,0xc6,0x18,0xc6,0x18,0xbe,0x18,0xc6,0x17,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,
+0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x38,0xc6,0x75,0xad,0x41,0x08,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0xf3,0x9c,0x38,0xc6,0x17,0xbe,0xf7,0xbd,0xf7,0xbd,0x17,0xbe,0x17,0xbe,
+0x17,0xbe,0xf7,0xbd,0x17,0xbe,0x17,0xbe,0x17,0xbe,0xf7,0xbd,0x17,0xbe,0xf7,0xbd,
+0xf7,0xbd,0xf7,0xbd,0x17,0xbe,0xf7,0xbd,0x17,0xbe,0xf7,0xbd,0xd3,0x9c,0x92,0x94,
+0xd2,0x94,0xf3,0x9c,0x13,0x9d,0x34,0xa5,0x54,0xa5,0x55,0xad,0x75,0xad,0x96,0xb5,
+0x96,0xb5,0x96,0xb5,0xb6,0xb5,0xd6,0xb5,0xd6,0xbd,0xd7,0xbd,0xd7,0xbd,0xf7,0xbd,
+0xeb,0x5a,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x14,0xa5,0x17,0xbe,
+0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xd7,0xbd,0xf7,0xbd,0xd7,0xbd,
+0xf7,0xbd,0xd7,0xbd,0xf7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,
+0xd7,0xbd,0xd7,0xbd,0x96,0xb5,0x45,0x29,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x8e,0x73,0xf7,0xbd,0xd6,0xb5,0xd6,0xb5,0xd7,0xbd,0xd6,0xb5,0xb7,0xbd,0xd6,0xb5,
+0xd7,0xbd,0xd6,0xbd,0xd7,0xb5,0xd7,0xbd,0xd7,0xb5,0xd6,0xbd,0xd7,0xbd,0xd6,0xbd,
+0xd7,0xb5,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xf7,0xbd,0x8e,0x73,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x08,0x42,0x17,0xbe,
+0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,
+0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,
+0xf7,0xbd,0xf7,0xbd,0x18,0xc6,0xb2,0x94,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x45,0x29,0x72,0x94,0xb2,0x94,
+0xb2,0x94,0xb2,0x94,0xb2,0x94,0xb2,0x94,0xb2,0x94,0xb2,0x94,0xb2,0x94,0xb2,0x94,
+0xb2,0x94,0xb2,0x94,0xb3,0x94,0xd2,0x9c,0xd3,0x9c,0xd3,0x9c,0xd3,0x9c,0xf3,0x9c,
+0xf3,0x9c,0xf3,0x9c,0x14,0xa5,0x14,0xa5,0x34,0xa5,0x34,0xa5,0x55,0xad,0xcb,0x5a,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x04,0x21,0xb6,0xb5,0x18,0xc6,
+0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x17,0xc6,
+0x18,0xc6,0x18,0xbe,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xbe,
+0x18,0xc6,0x75,0xad,0x21,0x08,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xf3,0x9c,0x18,0xc6,0x17,0xbe,
+0x17,0xbe,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0x17,0xbe,0xf7,0xbd,0xf7,0xbd,
+0xf7,0xbd,0x17,0xbe,0xf7,0xbd,0x17,0xbe,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,
+0xf7,0xbd,0x17,0xbe,0xd3,0x9c,0x92,0x94,0xb3,0x94,0xf3,0x9c,0x14,0xa5,0x34,0xa5,
+0x54,0xa5,0x55,0xad,0x75,0xad,0x96,0xad,0x96,0xb5,0xb6,0xb5,0xb6,0xb5,0xd6,0xb5,
+0xd7,0xb5,0xd6,0xbd,0xf7,0xbd,0xef,0x7b,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x14,0xa5,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xd7,0xbd,0xf7,0xbd,
+0xd7,0xbd,0xf7,0xbd,0xd7,0xbd,0xf7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,
+0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd6,0xbd,0x96,0xb5,0x45,0x29,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x8e,0x73,0xf7,0xbd,0xd6,0xb5,0xd6,0xbd,
+0xd6,0xb5,0xd6,0xbd,0xd7,0xb5,0xd6,0xb5,0xd6,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,
+0xd7,0xbd,0xd7,0xbd,0xd6,0xb5,0xd7,0xbd,0xd6,0xbd,0xd7,0xbd,0xd6,0xbd,0xd7,0xbd,
+0xf7,0xbd,0x8e,0x73,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x08,0x42,0x18,0xc6,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,
+0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,
+0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0x18,0xc6,0x92,0x94,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0xa6,0x31,0x71,0x8c,0x92,0x94,0x71,0x94,0x71,0x8c,0x72,0x94,
+0x91,0x8c,0x92,0x94,0x92,0x94,0x92,0x94,0x92,0x94,0x92,0x94,0x92,0x94,0x92,0x94,
+0xb2,0x94,0xb2,0x94,0xb2,0x94,0xb2,0x9c,0xd3,0x9c,0xd3,0x9c,0xf3,0x9c,0xf3,0x9c,
+0x13,0x9d,0x14,0xa5,0x34,0xa5,0x34,0xa5,0x28,0x42,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0xa3,0x18,0xb6,0xb5,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,
+0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,
+0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x38,0xc6,0x76,0xb5,0x41,0x08,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x13,0x9d,0x38,0xc6,0x18,0xbe,0xf7,0xbd,0x17,0xbe,0x17,0xbe,0xf7,0xbd,
+0x17,0xbe,0xf7,0xbd,0xf7,0xbd,0x17,0xbe,0xf7,0xbd,0x17,0xbe,0x17,0xbe,0xf7,0xbd,
+0x17,0xbe,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0x17,0xbe,0x18,0xc6,0xf3,0x9c,0x92,0x94,
+0xd3,0x9c,0xf3,0x9c,0x14,0xa5,0x34,0xa5,0x54,0xa5,0x55,0xad,0x75,0xad,0x96,0xb5,
+0x96,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xd6,0xb5,0xf7,0xbd,0x13,0x9d,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x14,0xa5,0x17,0xbe,
+0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xd7,0xbd,
+0xf7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd6,0xbd,0xd7,0xb5,
+0xd6,0xb5,0xd7,0xb5,0x96,0xb5,0x65,0x29,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x8e,0x73,0xf7,0xbd,0xd7,0xbd,0xd6,0xb5,0xd7,0xbd,0xd7,0xb5,0xd6,0xbd,0xd6,0xbd,
+0xd6,0xb5,0xd6,0xbd,0xd6,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,
+0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xf7,0xbd,0x8e,0x73,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x08,0x42,0x17,0xc6,
+0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,
+0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,
+0xf7,0xbd,0xf7,0xbd,0x18,0xc6,0xb2,0x94,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xe7,0x39,
+0x51,0x8c,0x51,0x8c,0x51,0x8c,0x51,0x8c,0x51,0x8c,0x51,0x8c,0x51,0x8c,0x51,0x8c,
+0x51,0x8c,0x51,0x8c,0x71,0x8c,0x71,0x8c,0x71,0x8c,0x92,0x94,0x92,0x94,0x92,0x94,
+0x92,0x94,0xb2,0x94,0xd2,0x94,0xd2,0x9c,0xd3,0x9c,0xf3,0x9c,0xf3,0x9c,0x14,0xa5,
+0x14,0xa5,0xa6,0x31,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xc3,0x18,0xb6,0xb5,0x38,0xc6,
+0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,
+0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x17,0xc6,
+0x38,0xc6,0x75,0xad,0x41,0x08,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x13,0x9d,0x18,0xc6,0xf7,0xbd,
+0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,
+0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0x17,0xbe,0xf7,0xbd,0x17,0xbe,0xf7,0xbd,0x17,0xbe,
+0xf7,0xbd,0x18,0xbe,0xf3,0x9c,0x92,0x94,0xd3,0x9c,0xf3,0x9c,0x14,0xa5,0x34,0xa5,
+0x55,0xad,0x55,0xad,0x75,0xad,0x96,0xb5,0x96,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,
+0xd7,0xbd,0x96,0xb5,0x45,0x29,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x14,0xa5,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,
+0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,
+0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd6,0xbd,0xb6,0xb5,0xd6,0xb5,0xb6,0xb5,0xa6,0x31,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x8e,0x73,0xf7,0xbd,0xd7,0xbd,0xd7,0xbd,
+0xd7,0xbd,0xd6,0xb5,0xd7,0xbd,0xd6,0xbd,0xd7,0xb5,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,
+0xd6,0xb5,0xd7,0xbd,0xd7,0xb5,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,
+0xf7,0xbd,0x8e,0x73,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x08,0x42,0x18,0xc6,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,
+0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,
+0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0x18,0xc6,0xb2,0x94,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xe8,0x41,0x10,0x84,0x10,0x84,0x10,0x84,
+0x10,0x84,0x10,0x84,0x10,0x84,0x10,0x84,0x10,0x84,0x10,0x84,0x30,0x84,0x30,0x84,
+0x30,0x84,0x51,0x8c,0x51,0x8c,0x51,0x8c,0x71,0x8c,0x71,0x8c,0x92,0x94,0x92,0x94,
+0xb2,0x94,0xd2,0x94,0xd3,0x9c,0xf3,0x9c,0x14,0xa5,0xd3,0x9c,0x24,0x21,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0xa3,0x18,0xb6,0xb5,0x38,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,
+0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,
+0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x38,0xc6,0x75,0xad,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0xf3,0x9c,0x38,0xc6,0x18,0xc6,0x17,0xbe,0xf8,0xc5,0x17,0xbe,0x18,0xc6,
+0x17,0xbe,0x17,0xc6,0x17,0xbe,0xf7,0xc5,0xf7,0xbd,0x17,0xbe,0xf7,0xbd,0xf7,0xbd,
+0x17,0xbe,0xf7,0xbd,0x17,0xbe,0x17,0xbe,0x17,0xbe,0x17,0xc6,0xf3,0x9c,0x92,0x94,
+0xd3,0x9c,0xf3,0x9c,0x14,0xa5,0x34,0xa5,0x55,0xad,0x55,0xad,0x75,0xad,0x96,0xb5,
+0x96,0xb5,0xb6,0xb5,0xb6,0xb5,0xd7,0xbd,0xd7,0xbd,0xcb,0x5a,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x14,0xa5,0x18,0xc6,
+0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,
+0xf7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd6,0xbd,0xb6,0xb5,
+0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xa6,0x31,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x6d,0x6b,0xf7,0xbd,0xb7,0xb5,0xd6,0xb5,0xd7,0xb5,0xd7,0xbd,0xd6,0xbd,0xd7,0xbd,
+0xd7,0xbd,0xd7,0xb5,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd6,0xbd,0xd7,0xbd,0xd7,0xb5,
+0xd7,0xbd,0xd6,0xbd,0xd7,0xbd,0xd7,0xbd,0xf7,0xbd,0x6d,0x6b,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x08,0x42,0x17,0xc6,
+0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,
+0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,
+0xf7,0xbd,0xf7,0xbd,0x18,0xc6,0x92,0x94,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x45,0x29,0x66,0x31,0x65,0x29,0x65,0x29,0x65,0x29,0x66,0x31,0x65,0x29,
+0x65,0x29,0x65,0x29,0x66,0x31,0x65,0x29,0x65,0x29,0x65,0x29,0x66,0x31,0x65,0x29,
+0x65,0x29,0x65,0x29,0x66,0x31,0x65,0x29,0x65,0x31,0x65,0x29,0x66,0x31,0x65,0x29,
+0x65,0x29,0x65,0x29,0x66,0x31,0x65,0x29,0x65,0x29,0x65,0x29,0x66,0x31,0x65,0x29,
+0x65,0x29,0x65,0x29,0x66,0x31,0x65,0x29,0x65,0x29,0x65,0x29,0x66,0x31,0x65,0x29,
+0x45,0x29,0x8d,0x6b,0x51,0x8c,0x51,0x8c,0x51,0x8c,0x71,0x8c,0x72,0x8c,0x71,0x8c,
+0x72,0x94,0x92,0x94,0x92,0x94,0x92,0x94,0x92,0x94,0xb2,0x94,0xb2,0x94,0xb2,0x94,
+0xb2,0x94,0xd2,0x9c,0xd3,0x9c,0xf3,0x9c,0xf3,0x9c,0x13,0x9d,0x14,0xa5,0x34,0xa5,
+0x34,0xa5,0x75,0xad,0xd3,0x9c,0xc3,0x18,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xc3,0x18,0xb6,0xb5,0x38,0xc6,
+0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,
+0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,
+0x18,0xc6,0xb6,0xb5,0x69,0x4a,0xe7,0x39,0x08,0x42,0x08,0x42,0x08,0x42,0x08,0x42,
+0x08,0x42,0x08,0x42,0x08,0x42,0x08,0x42,0x08,0x42,0x08,0x42,0x08,0x42,0x08,0x42,
+0x08,0x42,0x08,0x42,0x08,0x42,0x08,0x42,0x08,0x42,0x08,0x42,0x08,0x42,0x08,0x42,
+0x08,0x42,0x08,0x42,0x08,0x42,0x08,0x42,0x08,0x42,0x08,0x42,0x08,0x42,0x08,0x42,
+0x08,0x42,0x08,0x42,0x08,0x42,0x08,0x42,0x08,0x42,0x08,0x42,0x08,0x42,0x08,0x42,
+0x08,0x42,0x08,0x42,0x08,0x42,0x08,0x42,0x08,0x42,0x08,0x42,0x08,0x42,0x08,0x42,
+0x45,0x29,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x13,0x9d,0x18,0xc6,0x17,0xbe,
+0xf8,0xc5,0x17,0xbe,0xf7,0xc5,0x17,0xbe,0xf7,0xbd,0x17,0xbe,0xf7,0xbd,0xf7,0xbd,
+0x17,0xbe,0x17,0xbe,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0x17,0xbe,
+0xf7,0xbd,0x18,0xc6,0xf3,0x9c,0x92,0x94,0xd3,0x9c,0xf3,0x9c,0x14,0xa5,0x34,0xa5,
+0x55,0xad,0x75,0xad,0x75,0xad,0x96,0xb5,0x96,0xb5,0xb6,0xb5,0xb6,0xb5,0xf7,0xbd,
+0xcf,0x7b,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x14,0xa5,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,
+0xf7,0xbd,0xf7,0xbd,0xd7,0xbd,0xf7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,
+0xd7,0xbd,0xd6,0xb5,0xd7,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xa6,0x31,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xa7,0x31,0x08,0x42,0xe8,0x41,0xe8,0x41,
+0xe8,0x41,0xe8,0x41,0xe8,0x41,0xe8,0x41,0x08,0x42,0xe8,0x41,0x08,0x42,0xe8,0x41,
+0x08,0x42,0xe8,0x41,0x08,0x42,0xe8,0x41,0x08,0x42,0x08,0x42,0x08,0x42,0xe8,0x41,
+0x08,0x42,0x08,0x42,0x08,0x42,0xc7,0x39,0x30,0x84,0xd7,0xbd,0xd7,0xbd,0xd6,0xbd,
+0xd7,0xbd,0xd7,0xbd,0xd6,0xb5,0xd7,0xbd,0xd6,0xb5,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,
+0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,
+0xf7,0xbd,0x51,0x8c,0x29,0x4a,0x69,0x4a,0x69,0x4a,0x69,0x4a,0x69,0x4a,0x69,0x4a,
+0x69,0x4a,0x69,0x4a,0x69,0x4a,0x69,0x4a,0x69,0x4a,0x69,0x4a,0x69,0x4a,0x69,0x4a,
+0x69,0x4a,0x69,0x4a,0x69,0x4a,0x69,0x4a,0x69,0x4a,0x69,0x4a,0x69,0x4a,0x69,0x4a,
+0x49,0x4a,0xc3,0x18,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x08,0x42,0x18,0xc6,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,
+0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,
+0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0x18,0xc6,0xb2,0x94,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x45,0x29,0x14,0xa5,0xd7,0xbd,0xf7,0xbd,0xf7,0xbd,
+0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xd7,0xbd,0xf7,0xbd,0xd7,0xbd,0xf7,0xbd,0xf7,0xbd,
+0xf7,0xbd,0xd7,0xbd,0xf7,0xbd,0xd7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,
+0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,
+0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,
+0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,
+0xf7,0xbd,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,
+0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,
+0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x38,0xc6,0x2c,0x63,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0xc3,0x18,0xb6,0xb5,0x38,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,
+0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,
+0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x38,0xc6,0x38,0xc6,
+0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,
+0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,
+0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,
+0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,
+0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,
+0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0xf7,0xbd,0x2c,0x63,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x14,0x9d,0x38,0xc6,0x17,0xc6,0x17,0xbe,0x18,0xc6,0x17,0xbe,0xf8,0xbd,
+0x17,0xbe,0xf8,0xc5,0x17,0xbe,0xf8,0xc5,0x17,0xbe,0xf8,0xbd,0xf7,0xbd,0xf8,0xbd,
+0x17,0xbe,0xf7,0xbd,0x17,0xbe,0xf7,0xbd,0xf7,0xbd,0x18,0xc6,0xf3,0x9c,0xb2,0x94,
+0xd3,0x9c,0xf3,0x9c,0x14,0xa5,0x34,0xa5,0x55,0xad,0x75,0xad,0x75,0xad,0x96,0xb5,
+0x96,0xb5,0xb6,0xb5,0xd7,0xbd,0xd3,0x9c,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x14,0xa5,0xf7,0xbd,
+0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,
+0xf7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd6,0xbd,0xd6,0xb5,
+0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xa6,0x31,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x21,0x08,0x92,0x94,
+0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,
+0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xf7,0xbd,
+0xd7,0xbd,0xf7,0xbd,0xd7,0xbd,0xf7,0xbd,0xd7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,
+0xd7,0xbd,0xd7,0xb5,0xd7,0xb5,0xd6,0xb5,0xd7,0xb5,0xd7,0xbd,0xd7,0xb5,0xd6,0xbd,
+0xd7,0xbd,0xd6,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,
+0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,
+0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,
+0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,
+0xf7,0xbd,0xf7,0xbd,0x17,0xbe,0x17,0xbe,0x18,0xc6,0x96,0xb5,0xe7,0x39,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x08,0x42,0x17,0xc6,
+0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,
+0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,
+0xf7,0xbd,0xf7,0xbd,0x18,0xc6,0xb2,0x94,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xd3,0x9c,
+0x38,0xc6,0x18,0xc6,0x18,0xbe,0x17,0xbe,0x17,0xbe,0x17,0xbe,0x18,0xc6,0x18,0xc6,
+0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xbe,
+0x18,0xc6,0x18,0xbe,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,
+0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,
+0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,
+0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,
+0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,
+0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,
+0x18,0xc6,0x18,0xc6,0x38,0xc6,0x8a,0x52,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xc3,0x18,0xb6,0xb5,0x38,0xc6,
+0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,
+0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,
+0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,
+0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,
+0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,
+0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,
+0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,
+0x18,0xc6,0x18,0xbe,0x18,0xc6,0x17,0xc6,0x18,0xc6,0x18,0xbe,0x18,0xc6,0x18,0xbe,
+0x38,0xc6,0xd7,0xb5,0xe3,0x18,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x13,0x9d,0x38,0xc6,0x17,0xc6,
+0x18,0xbe,0x17,0xbe,0xf8,0xc5,0x17,0xbe,0xf7,0xbd,0x17,0xbe,0x17,0xbe,0x17,0xbe,
+0x18,0xc6,0x17,0xbe,0x18,0xbe,0x17,0xbe,0xf7,0xbd,0x17,0xbe,0x17,0xbe,0xf7,0xbd,
+0x17,0xbe,0x18,0xc6,0xf3,0x9c,0xb2,0x94,0xf3,0x9c,0x13,0x9d,0x34,0xa5,0x54,0xa5,
+0x55,0xad,0x75,0xad,0x76,0xb5,0x96,0xb5,0x96,0xb5,0xb6,0xb5,0x75,0xad,0x45,0x29,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x14,0xa5,0x17,0xbe,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,
+0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,
+0xd7,0xbd,0xd7,0xb5,0xd6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0x96,0xb5,0xa6,0x31,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x6d,0x6b,0xf7,0xbd,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,
+0xd6,0xb5,0xb6,0xb5,0xd6,0xb5,0xb6,0xb5,0xb6,0xb5,0xd6,0xb5,0xb6,0xb5,0xd6,0xbd,
+0xd6,0xb5,0xb6,0xb5,0xd6,0xb5,0xd6,0xbd,0xd6,0xb5,0xd7,0xbd,0xd7,0xb5,0xd7,0xbd,
+0xd6,0xb5,0xd7,0xbd,0xd6,0xb5,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xb5,0xd7,0xbd,
+0xd6,0xb5,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,
+0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,
+0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,
+0xd7,0xbd,0xd7,0xbd,0xf7,0xbd,0xd7,0xbd,0xf7,0xbd,0xd7,0xbd,0xf7,0xbd,0xd7,0xbd,
+0xf7,0xbd,0xd7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,
+0xf7,0xbd,0x18,0xc6,0xd3,0x9c,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x08,0x42,0x18,0xc6,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,
+0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,
+0xf7,0xbd,0xf7,0xbd,0x17,0xbe,0xf7,0xbd,0x17,0xbe,0xf7,0xbd,0x18,0xc6,0xb2,0x94,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x21,0x00,0x75,0xad,0x18,0xc6,0x18,0xc6,0x17,0xbe,0x18,0xc6,
+0x17,0xc6,0xf8,0xbd,0x18,0xbe,0x18,0xbe,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x17,0xc6,
+0x18,0xc6,0x17,0xbe,0x18,0xc6,0x18,0xc6,0x18,0xbe,0x18,0xc6,0x17,0xc6,0x18,0xc6,
+0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x17,0xbe,0x18,0xc6,0x17,0xbe,0x18,0xc6,
+0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,
+0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,
+0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,
+0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,
+0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x38,0xc6,0x75,0xad,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0xc3,0x18,0xb6,0xb5,0x38,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,
+0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,
+0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,
+0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,
+0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,
+0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,
+0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,
+0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,
+0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0xa7,0x39,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0xf4,0x9c,0x38,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xbe,
+0x18,0xc6,0xf8,0xbd,0x18,0xbe,0x18,0xbe,0x17,0xbe,0xf7,0xbd,0x17,0xbe,0xf8,0xc5,
+0x17,0xbe,0xf8,0xc5,0x17,0xbe,0x17,0xbe,0x17,0xbe,0x18,0xc6,0x13,0x9d,0xb2,0x94,
+0xf3,0x9c,0x14,0xa5,0x34,0xa5,0x55,0xad,0x55,0xad,0x75,0xad,0x96,0xad,0x96,0xb5,
+0xb6,0xb5,0xb6,0xb5,0xaa,0x52,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x14,0xa5,0x18,0xc6,
+0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,
+0xf7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd6,0xbd,0xd7,0xb5,0xd6,0xb5,0xb6,0xb5,
+0xb6,0xb5,0xb6,0xb5,0x96,0xb5,0x86,0x31,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x30,0x84,0xd7,0xbd,
+0xb6,0xb5,0xd6,0xb5,0xb6,0xb5,0xd6,0xb5,0xb6,0xb5,0xd6,0xb5,0xb6,0xb5,0xb6,0xb5,
+0xd6,0xb5,0xb6,0xb5,0xb6,0xb5,0xd6,0xb5,0xd6,0xb5,0xd6,0xb5,0xd6,0xb5,0xb6,0xb5,
+0xb7,0xbd,0xd6,0xb5,0xd7,0xb5,0xd6,0xb5,0xd7,0xb5,0xd6,0xbd,0xd7,0xbd,0xd7,0xb5,
+0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd6,0xbd,0xd7,0xbd,0xd7,0xb5,0xd7,0xbd,0xd7,0xb5,
+0xd7,0xbd,0xd7,0xb5,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,
+0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,
+0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,
+0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xf7,0xbd,0xd7,0xbd,0xf7,0xbd,0xd7,0xbd,0xf7,0xbd,
+0xd7,0xbd,0xf7,0xbd,0xd7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0x14,0xa5,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x08,0x42,0x17,0xc6,
+0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,
+0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,
+0xf7,0xbd,0xf7,0xbd,0x18,0xc6,0x92,0x94,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x21,0x08,0x75,0xad,
+0x18,0xc6,0x17,0xbe,0xf8,0xc5,0x17,0xbe,0xf7,0xbd,0x17,0xbe,0xf8,0xc5,0x17,0xbe,
+0xf8,0xbd,0x17,0xbe,0x18,0xc6,0x18,0xbe,0x18,0xc6,0x18,0xbe,0x18,0xc6,0x17,0xc6,
+0x18,0xbe,0x17,0xc6,0x18,0xbe,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x17,0xc6,0x18,0xc6,
+0x18,0xbe,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xbe,0x18,0xc6,0x18,0xc6,
+0x18,0xc6,0x18,0xbe,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x17,0xc6,0x18,0xc6,0x18,0xc6,
+0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,
+0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,
+0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,
+0x18,0xc6,0x38,0xc6,0x2c,0x63,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xc3,0x18,0xb6,0xb5,0x38,0xc6,
+0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,
+0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,
+0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,
+0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,
+0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,
+0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,
+0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,
+0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x17,0xc6,0x18,0xc6,0x18,0xbe,
+0x18,0xc6,0x18,0xc6,0xc7,0x39,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x13,0x9d,0x38,0xc6,0x18,0xbe,
+0x17,0xc6,0x17,0xc6,0x18,0xc6,0x18,0xbe,0x18,0xbe,0x17,0xbe,0xf7,0xc5,0x17,0xbe,
+0xf7,0xc5,0x17,0xbe,0xf7,0xc5,0x17,0xbe,0xf8,0xc5,0x17,0xbe,0x17,0xbe,0x17,0xbe,
+0xf7,0xbd,0x18,0xc6,0x14,0xa5,0xd2,0x94,0xf3,0x9c,0x14,0xa5,0x34,0xa5,0x55,0xa5,
+0x55,0xad,0x75,0xad,0x96,0xb5,0x96,0xb5,0xd6,0xb5,0xaf,0x73,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0xf3,0xa4,0x17,0xbe,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,
+0xf7,0xbd,0xf7,0xbd,0xd7,0xbd,0xf7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xb5,
+0xd7,0xbd,0xd6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0x96,0xb5,0x86,0x31,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x30,0x84,0xd7,0xbd,0xd6,0xb5,0xb6,0xb5,0xd6,0xb5,0xb6,0xb5,
+0xd6,0xb5,0xd6,0xb5,0xb6,0xb5,0xb6,0xb5,0xd6,0xb5,0xb6,0xb5,0xd6,0xb5,0xb7,0xb5,
+0xd6,0xb5,0xd6,0xb5,0xd6,0xb5,0xb6,0xbd,0xd6,0xb5,0xd6,0xb5,0xd7,0xbd,0xd6,0xbd,
+0xd7,0xbd,0xd7,0xbd,0xd7,0xb5,0xd7,0xbd,0xd6,0xb5,0xd7,0xbd,0xd6,0xb5,0xd7,0xbd,
+0xd6,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,
+0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,
+0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,
+0xf7,0xbd,0xd7,0xbd,0xf7,0xbd,0xd7,0xbd,0xf7,0xbd,0xd7,0xbd,0xf7,0xbd,0xd7,0xbd,
+0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,
+0xf7,0xbd,0xf7,0xbd,0x14,0xa5,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x08,0x42,0x18,0xc6,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,
+0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,
+0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0x17,0xbe,0xf7,0xbd,0x18,0xc6,0xb2,0x94,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x41,0x08,0x75,0xad,0x18,0xc6,0x17,0xbe,0x17,0xbe,0x18,0xc6,
+0x18,0xbe,0x17,0xc6,0x17,0xc6,0x18,0xc6,0x17,0xc6,0x17,0xbe,0x18,0xbe,0x18,0xc6,
+0x17,0xc6,0x17,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xbe,0x18,0xc6,
+0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xbe,0x18,0xc6,0x17,0xc6,0x18,0xc6,
+0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,
+0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,
+0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,
+0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,
+0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x38,0xc6,0x55,0xad,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0xc3,0x18,0xb6,0xb5,0x38,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,
+0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,
+0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,
+0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,
+0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,
+0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,
+0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,
+0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,
+0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0xa7,0x39,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x13,0xa5,0x38,0xc6,0x18,0xc6,0x17,0xbe,0x17,0xc6,0x18,0xbe,0x18,0xbe,
+0x18,0xc6,0x18,0xc6,0x18,0xc6,0x17,0xc6,0x18,0xc6,0x18,0xc6,0x17,0xc6,0x18,0xbe,
+0x18,0xbe,0xf8,0xbd,0x17,0xbe,0xf7,0xc5,0x17,0xbe,0x18,0xc6,0x14,0xa5,0xd3,0x9c,
+0x13,0x9d,0x14,0xa5,0x34,0xa5,0x55,0xad,0x75,0xad,0x75,0xad,0x96,0xb5,0xb6,0xb5,
+0xb2,0x94,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xf3,0x9c,0x18,0xc6,
+0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xd7,0xbd,
+0xf7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd6,0xbd,0xd6,0xb5,0xb6,0xb5,0xb6,0xb5,
+0xb6,0xb5,0x96,0xb5,0x96,0xb5,0x86,0x31,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x30,0x84,0xd7,0xbd,
+0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xd6,0xb5,0xd6,0xb5,0xd6,0xb5,
+0xb6,0xb5,0xb6,0xb5,0xd7,0xb5,0xd6,0xb5,0xd6,0xbd,0xd6,0xb5,0xb7,0xb5,0xd6,0xb5,
+0xb7,0xbd,0xd7,0xb5,0xd7,0xbd,0xd6,0xbd,0xd7,0xbd,0xd7,0xbd,0xd6,0xbd,0xd7,0xb5,
+0xd7,0xbd,0xd6,0xb5,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd6,0xb5,0xd7,0xbd,0xd6,0xbd,
+0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,
+0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,
+0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xf7,0xbd,
+0xd7,0xbd,0xf7,0xbd,0xd7,0xbd,0xf7,0xbd,0xd7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,
+0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0x17,0xbe,0x34,0xa5,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x08,0x42,0x17,0xc6,
+0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,
+0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0x17,0xbe,
+0xf7,0xbd,0x17,0xbe,0x18,0xc6,0xb2,0x94,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x21,0x08,0x75,0xad,
+0x18,0xc6,0x18,0xbe,0x18,0xc6,0x17,0xc6,0x18,0xc6,0x17,0xc6,0x18,0xbe,0x18,0xc6,
+0x18,0xbe,0x18,0xc6,0x18,0xc6,0x17,0xbe,0x18,0xc6,0x17,0xc6,0x18,0xbe,0x18,0xc6,
+0x18,0xc6,0x18,0xc6,0x18,0xc6,0x17,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,
+0x18,0xc6,0x18,0xc6,0x18,0xc6,0x17,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,
+0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,
+0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,
+0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,
+0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,
+0x38,0xc6,0x0c,0x63,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xc3,0x18,0xb6,0xb5,0x38,0xc6,
+0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,
+0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,
+0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,
+0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,
+0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,
+0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,
+0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,
+0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,
+0x18,0xc6,0x18,0xc6,0xc7,0x39,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x14,0x9d,0x38,0xc6,0x18,0xbe,
+0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x17,0xc6,0x17,0xc6,0x17,0xc6,0x17,0xc6,
+0xf8,0xbd,0x17,0xbe,0x17,0xc6,0x17,0xc6,0xf8,0xbd,0x17,0xbe,0x17,0xbe,0x17,0xbe,
+0xf8,0xc5,0x18,0xbe,0x14,0xa5,0xd3,0x9c,0x13,0x9d,0x34,0xa5,0x34,0xa5,0x55,0xad,
+0x75,0xad,0x75,0xad,0x96,0xb5,0x55,0xad,0x04,0x21,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0xf3,0x9c,0x17,0xc6,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,
+0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,
+0xd6,0xbd,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,0x86,0x31,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x30,0x84,0xd7,0xbd,0xd6,0xb5,0xb6,0xb5,0xd6,0xb5,0xb6,0xb5,
+0xd6,0xb5,0xb6,0xb5,0xd6,0xb5,0xb6,0xbd,0xd6,0xb5,0xd7,0xb5,0xd6,0xb5,0xb6,0xbd,
+0xd6,0xb5,0xd6,0xbd,0xd6,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xb5,0xd7,0xb5,0xd6,0xbd,
+0xd6,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,
+0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,
+0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,
+0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xf7,0xbd,0xd7,0xbd,
+0xf7,0xbd,0xd7,0xbd,0xf7,0xbd,0xd7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,
+0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,
+0xf7,0xbd,0x18,0xc6,0x14,0xa5,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x08,0x42,0x18,0xc6,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,
+0xf7,0xbd,0xf7,0xbd,0x17,0xbe,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0x17,0xbe,0xf7,0xbd,
+0x17,0xbe,0xf7,0xbd,0xf7,0xbd,0x17,0xbe,0xf7,0xbd,0x17,0xbe,0x38,0xc6,0xb2,0x94,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x41,0x08,0x75,0xad,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x17,0xc6,
+0x17,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x17,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,
+0x18,0xc6,0x18,0xc6,0x17,0xbe,0x18,0xc6,0x17,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,
+0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,
+0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,
+0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,
+0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,
+0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,
+0x18,0xc6,0x18,0xc6,0x18,0xc6,0x38,0xc6,0x75,0xad,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0xc3,0x18,0xb6,0xb5,0x38,0xc6,0x38,0xc6,0x18,0xc6,0x38,0xc6,0x18,0xc6,
+0x38,0xc6,0x18,0xc6,0x38,0xc6,0x18,0xc6,0x38,0xc6,0x18,0xc6,0x38,0xc6,0x18,0xc6,
+0x38,0xc6,0x18,0xc6,0x38,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x38,0xc6,0x18,0xc6,
+0x18,0xc6,0x18,0xc6,0x38,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x38,0xc6,0x18,0xc6,
+0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,
+0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,
+0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,
+0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,
+0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0xa7,0x39,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x14,0xa5,0x38,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x17,0xc6,0x18,0xc6,
+0x17,0xc6,0x18,0xc6,0x18,0xc6,0x17,0xc6,0x18,0xbe,0x18,0xc6,0x18,0xc6,0x18,0xc6,
+0x18,0xc6,0x17,0xc6,0x17,0xc6,0x17,0xc6,0x17,0xbe,0x18,0xc6,0x34,0xa5,0xd3,0x9c,
+0x14,0xa5,0x34,0xa5,0x54,0xa5,0x55,0xad,0x75,0xad,0x95,0xb5,0x96,0xb5,0x8a,0x52,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xf3,0x9c,0x18,0xc6,
+0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xd7,0xbd,
+0xd7,0xbd,0xd7,0xbd,0xd7,0xb5,0xb7,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0x96,0xb5,
+0x96,0xb5,0x96,0xb5,0x75,0xad,0x86,0x31,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x30,0x84,0xd7,0xbd,
+0xb6,0xb5,0xd6,0xb5,0xb6,0xb5,0xb6,0xb5,0xd6,0xb5,0xb6,0xb5,0xd6,0xb5,0xd6,0xb5,
+0xb6,0xb5,0xd6,0xb5,0xd6,0xbd,0xd6,0xb5,0xd6,0xb5,0xd6,0xb5,0xb7,0xbd,0xd7,0xb5,
+0xd6,0xbd,0xd6,0xb5,0xd7,0xbd,0xd7,0xb5,0xd7,0xb5,0xd6,0xbd,0xd6,0xbd,0xd7,0xb5,
+0xd7,0xbd,0xd7,0xb5,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd6,0xbd,0xd7,0xbd,0xd7,0xbd,
+0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,
+0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,
+0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xf7,0xbd,0xd7,0xbd,0xf7,0xbd,
+0xd7,0xbd,0xf7,0xbd,0xd7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,
+0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0x17,0xbe,0x34,0xa5,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x08,0x42,0x18,0xc6,
+0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,
+0xf7,0xbd,0x17,0xbe,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0x17,0xbe,
+0xf7,0xbd,0xf7,0xbd,0x18,0xc6,0xb2,0x94,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x21,0x08,0x75,0xad,
+0x18,0xc6,0x18,0xbe,0x17,0xbe,0x18,0xbe,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x17,0xc6,
+0x18,0xc6,0x17,0xc6,0x17,0xc6,0x17,0xc6,0x18,0xc6,0x18,0xbe,0x18,0xc6,0x17,0xc6,
+0x18,0xc6,0x18,0xc6,0x18,0xc6,0x17,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,
+0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,
+0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,
+0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,
+0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,
+0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x38,0xc6,
+0x0c,0x63,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xc3,0x18,0xb6,0xb5,0x38,0xc6,
+0x18,0xc6,0x38,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,
+0x18,0xc6,0x38,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,
+0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,
+0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,
+0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,
+0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,
+0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,
+0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,
+0x18,0xc6,0x18,0xc6,0xc7,0x39,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xd3,0x9c,0x38,0xc6,0x18,0xc6,
+0x18,0xc6,0x17,0xbe,0x17,0xc6,0x17,0xc6,0x18,0xbe,0x18,0xc6,0x18,0xc6,0x17,0xc6,
+0x18,0xc6,0x17,0xc6,0x17,0xc6,0x17,0xc6,0x18,0xc6,0x17,0xbe,0xf8,0xc5,0x18,0xbe,
+0x17,0xbe,0x18,0xc6,0x34,0xa5,0xf3,0x9c,0x14,0xa5,0x34,0xa5,0x55,0xad,0x55,0xad,
+0x75,0xad,0xb6,0xb5,0x8e,0x73,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0xf3,0x9c,0x18,0xbe,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,
+0xf7,0xbd,0xf7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd6,0xbd,0xd7,0xb5,0xb6,0xb5,
+0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xad,0x75,0xad,0x86,0x31,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x30,0x84,0xd7,0xbd,0xd6,0xb5,0xd6,0xb5,0xb6,0xb5,0xb6,0xb5,
+0xd6,0xb5,0xd6,0xbd,0xd6,0xb5,0xb7,0xb5,0xd6,0xb5,0xb6,0xb5,0xd6,0xb5,0xb7,0xbd,
+0xd7,0xb5,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd6,0xbd,0xd6,0xbd,0xd7,0xbd,
+0xd6,0xbd,0xd7,0xbd,0xd6,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd6,0xbd,0xd7,0xbd,
+0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,
+0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,
+0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xf7,0xbd,0xd7,0xbd,0xf7,0xbd,0xd7,0xbd,
+0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,
+0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,
+0xf7,0xbd,0xf7,0xc5,0x14,0xa5,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x08,0x42,0x18,0xc6,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,
+0x17,0xbe,0xf7,0xbd,0x17,0xbe,0xf7,0xbd,0x17,0xbe,0xf7,0xbd,0x17,0xbe,0xf7,0xbd,
+0xf7,0xbd,0x17,0xbe,0x17,0xbe,0x17,0xbe,0x17,0xbe,0xf7,0xbd,0x38,0xc6,0xb2,0x94,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x41,0x08,0x75,0xad,0x38,0xc6,0x18,0xc6,0x17,0xc6,0x18,0xc6,
+0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x17,0xbe,0x18,0xc6,0x17,0xc6,0x18,0xc6,
+0x18,0xbe,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,
+0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,
+0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,
+0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,
+0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,
+0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x38,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,
+0x38,0xc6,0x18,0xc6,0x38,0xc6,0x75,0xad,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0xc3,0x18,0xb6,0xb5,0x38,0xc6,0x38,0xc6,0x18,0xc6,0x38,0xc6,0x18,0xc6,
+0x38,0xc6,0x18,0xc6,0x38,0xc6,0x18,0xc6,0x38,0xc6,0x18,0xc6,0x38,0xc6,0x18,0xc6,
+0x38,0xc6,0x18,0xc6,0x38,0xc6,0x18,0xc6,0x38,0xc6,0x18,0xc6,0x38,0xc6,0x18,0xc6,
+0x38,0xc6,0x18,0xc6,0x38,0xc6,0x18,0xc6,0x38,0xc6,0x18,0xc6,0x38,0xc6,0x18,0xc6,
+0x38,0xc6,0x18,0xc6,0x38,0xc6,0x18,0xc6,0x38,0xc6,0x18,0xc6,0x38,0xc6,0x18,0xc6,
+0x38,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x38,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,
+0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,
+0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,
+0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0xc7,0x39,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0xb2,0x94,0x38,0xc6,0x18,0xc6,0x18,0xbe,0x18,0xc6,0x17,0xc6,0x18,0xc6,
+0x17,0xbe,0x18,0xc6,0x18,0xbe,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xbe,0x18,0xc6,
+0x18,0xbe,0x17,0xbe,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x54,0xa5,0xf3,0x9c,
+0x34,0xa5,0x54,0xa5,0x55,0xad,0x55,0xad,0x96,0xb5,0x92,0x94,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xf3,0x9c,0x18,0xc6,
+0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xd7,0xbd,
+0xd7,0xbd,0xd7,0xbd,0xd6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0x96,0xb5,
+0x95,0xb5,0x75,0xad,0x75,0xad,0x66,0x31,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x30,0x84,0xd7,0xbd,
+0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xd6,0xb5,0xb6,0xb5,0xd7,0xb5,0xd6,0xb5,
+0xd7,0xbd,0xd6,0xb5,0xd7,0xbd,0xd6,0xb5,0xb7,0xbd,0xd7,0xb5,0xd6,0xb5,0xd7,0xb5,
+0xd7,0xbd,0xd7,0xb5,0xd6,0xbd,0xd6,0xbd,0xd7,0xbd,0xd6,0xb5,0xd7,0xbd,0xd6,0xbd,
+0xd7,0xbd,0xd6,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,
+0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,
+0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xf7,0xbd,
+0xd7,0xbd,0xf7,0xbd,0xd7,0xbd,0xf7,0xbd,0xd7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,
+0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,
+0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0x17,0xbe,0x14,0xa5,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x08,0x42,0x18,0xc6,
+0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,
+0xf7,0xbd,0x17,0xbe,0xf7,0xbd,0x17,0xbe,0xf7,0xbd,0xf7,0xbd,0x17,0xbe,0x17,0xbe,
+0xf7,0xbd,0x17,0xbe,0x18,0xc6,0xb2,0x94,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x21,0x08,0x75,0xad,
+0x18,0xc6,0x18,0xc6,0x18,0xc6,0x17,0xc6,0x18,0xc6,0x18,0xbe,0x18,0xc6,0x18,0xc6,
+0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,
+0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,
+0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,
+0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,
+0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,
+0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,
+0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x38,0xc6,0x38,0xc6,0xeb,0x5a,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xc3,0x18,0xb6,0xb5,0x38,0xc6,
+0x18,0xc6,0x38,0xc6,0x18,0xc6,0x38,0xc6,0x18,0xc6,0x38,0xc6,0x18,0xc6,0x38,0xc6,
+0x18,0xc6,0x38,0xc6,0x18,0xc6,0x38,0xc6,0x18,0xc6,0x38,0xc6,0x18,0xc6,0x38,0xc6,
+0x18,0xc6,0x38,0xc6,0x18,0xc6,0x38,0xc6,0x18,0xc6,0x38,0xc6,0x18,0xc6,0x38,0xc6,
+0x18,0xc6,0x38,0xc6,0x18,0xc6,0x38,0xc6,0x18,0xc6,0x38,0xc6,0x18,0xc6,0x38,0xc6,
+0x18,0xc6,0x38,0xc6,0x18,0xc6,0x38,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x38,0xc6,
+0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,
+0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,
+0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,
+0x18,0xc6,0x18,0xc6,0xc7,0x39,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xb2,0x94,0x38,0xc6,0x17,0xc6,
+0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xbe,0x18,0xc6,0x17,0xc6,
+0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x17,0xbe,0x18,0xc6,0x18,0xc6,0x18,0xbe,
+0x18,0xbe,0x18,0xc6,0x54,0xad,0x13,0xa5,0x34,0xa5,0x54,0xa5,0x55,0xad,0x75,0xad,
+0x34,0xa5,0xe4,0x20,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0xf3,0x9c,0x18,0xc6,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,
+0xf7,0xbd,0xf7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xb5,0xd6,0xb5,0xb6,0xb5,
+0xb6,0xb5,0xb6,0xb5,0x96,0xb5,0x96,0xb5,0x76,0xb5,0x75,0xad,0x75,0xad,0xa6,0x31,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x30,0x84,0xd7,0xbd,0xb6,0xb5,0xd7,0xb5,0xd6,0xb5,0xd7,0xbd,
+0xd6,0xb5,0xd6,0xbd,0xd6,0xb5,0xd6,0xb5,0xd6,0xb5,0xd7,0xb5,0xd7,0xbd,0xd7,0xbd,
+0xd7,0xbd,0xd6,0xb5,0xd6,0xbd,0xd6,0xbd,0xd7,0xb5,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,
+0xd6,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,
+0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,
+0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xf7,0xbd,0xd7,0xbd,
+0xf7,0xbd,0xd7,0xbd,0xf7,0xbd,0xd7,0xbd,0xf7,0xbd,0xd7,0xbd,0xf7,0xbd,0xf7,0xbd,
+0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,
+0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,
+0xf7,0xbd,0x17,0xc6,0x34,0xa5,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x08,0x42,0x18,0xc6,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,
+0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0x17,0xbe,0xf7,0xbd,0xf7,0xbd,0x17,0xbe,0xf7,0xbd,
+0xf7,0xbd,0x17,0xbe,0xf7,0xbd,0xf7,0xc5,0x17,0xbe,0xf7,0xc5,0x38,0xc6,0xb2,0x94,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x41,0x08,0x75,0xad,0x38,0xc6,0x18,0xc6,0x17,0xbe,0x18,0xc6,
+0x17,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,
+0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,
+0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,
+0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,
+0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,
+0x18,0xc6,0x18,0xc6,0x38,0xc6,0x18,0xc6,0x38,0xc6,0x18,0xc6,0x38,0xc6,0x18,0xc6,
+0x38,0xc6,0x18,0xc6,0x38,0xc6,0x18,0xc6,0x38,0xc6,0x18,0xc6,0x38,0xc6,0x18,0xc6,
+0x38,0xc6,0x38,0xc6,0x55,0xad,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0xc3,0x18,0xb6,0xb5,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,
+0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,
+0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,
+0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,
+0x38,0xc6,0x18,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x18,0xc6,0x38,0xc6,0x18,0xc6,
+0x38,0xc6,0x18,0xc6,0x38,0xc6,0x18,0xc6,0x38,0xc6,0x18,0xc6,0x38,0xc6,0x18,0xc6,
+0x38,0xc6,0x18,0xc6,0x38,0xc6,0x18,0xc6,0x38,0xc6,0x18,0xc6,0x38,0xc6,0x18,0xc6,
+0x18,0xc6,0x18,0xc6,0x38,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,
+0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x38,0xc6,0x18,0xc6,0xa7,0x39,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0xb3,0x9c,0x38,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,
+0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x17,0xc6,0x18,0xc6,
+0x18,0xc6,0x18,0xc6,0x17,0xbe,0x18,0xc6,0x17,0xbe,0x18,0xc6,0x54,0xad,0x14,0xa5,
+0x34,0xa5,0x55,0xad,0x75,0xad,0x75,0xad,0x49,0x4a,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xf3,0x9c,0x18,0xc6,
+0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,
+0xd6,0xbd,0xd7,0xb5,0xd6,0xb5,0xb6,0xb5,0xb6,0xb5,0x96,0xb5,0x96,0xb5,0x96,0xb5,
+0x75,0xad,0x75,0xad,0x75,0xad,0xa7,0x39,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x30,0x84,0xd7,0xbd,
+0xd6,0xb5,0xd6,0xb5,0xb6,0xb5,0xd6,0xb5,0xb7,0xb5,0xd6,0xb5,0xb7,0xb5,0xd6,0xb5,
+0xd7,0xbd,0xd6,0xb5,0xb6,0xbd,0xd6,0xb5,0xd7,0xbd,0xd6,0xbd,0xd6,0xb5,0xd6,0xb5,
+0xd6,0xb5,0xd6,0xb5,0xd7,0xbd,0xd7,0xb5,0xd7,0xbd,0xd7,0xb5,0xd7,0xbd,0xd7,0xbd,
+0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,
+0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,
+0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xf7,0xbd,0xd7,0xbd,0xf7,0xbd,
+0xd7,0xbd,0xf7,0xbd,0xd7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,
+0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,
+0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0x17,0xbe,0x14,0xa5,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x28,0x42,0x18,0xc6,
+0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0x17,0xbe,0xf7,0xbd,0x17,0xbe,0xf7,0xbd,0xf7,0xbd,
+0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0x17,0xbe,0x17,0xbe,0x17,0xbe,0xf7,0xbd,0xf7,0xbd,
+0xf7,0xbd,0x17,0xbe,0x18,0xc6,0xb2,0x94,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x21,0x08,0x75,0xad,
+0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xbe,0x18,0xc6,0x18,0xbe,0x18,0xc6,0x18,0xc6,
+0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,
+0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,
+0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,
+0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,
+0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,
+0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x38,0xc6,0x18,0xc6,0x18,0xc6,
+0x18,0xc6,0x38,0xc6,0x18,0xc6,0x38,0xc6,0x18,0xc6,0x38,0xc6,0xcb,0x5a,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xc3,0x18,0xb6,0xb5,0x38,0xc6,
+0x38,0xc6,0x38,0xc6,0x18,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x18,0xc6,0x38,0xc6,
+0x38,0xc6,0x38,0xc6,0x18,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x18,0xc6,0x38,0xc6,
+0x18,0xc6,0x38,0xc6,0x18,0xc6,0x38,0xc6,0x18,0xc6,0x38,0xc6,0x18,0xc6,0x38,0xc6,
+0x18,0xc6,0x38,0xc6,0x18,0xc6,0x38,0xc6,0x18,0xc6,0x38,0xc6,0x18,0xc6,0x38,0xc6,
+0x18,0xc6,0x38,0xc6,0x18,0xc6,0x38,0xc6,0x18,0xc6,0x38,0xc6,0x18,0xc6,0x38,0xc6,
+0x18,0xc6,0x38,0xc6,0x18,0xc6,0x38,0xc6,0x18,0xc6,0x38,0xc6,0x18,0xc6,0x18,0xc6,
+0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,
+0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,
+0x18,0xc6,0x18,0xc6,0xc7,0x39,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xd2,0x94,0x38,0xc6,0x18,0xc6,
+0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xbe,0x18,0xc6,0x17,0xc6,0x18,0xc6,0x18,0xc6,
+0x18,0xc6,0x17,0xbe,0x18,0xc6,0x17,0xbe,0x18,0xc6,0x18,0xc6,0x17,0xc6,0x17,0xbe,
+0x18,0xc6,0x18,0xc6,0x55,0xad,0x34,0xa5,0x54,0xa5,0x55,0xad,0x96,0xb5,0x6d,0x6b,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0xf3,0x9c,0x18,0xc6,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,
+0xf7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd6,0xb5,0xb6,0xb5,0xb6,0xb5,
+0xb6,0xb5,0x96,0xb5,0x96,0xb5,0x95,0xad,0x75,0xad,0x55,0xad,0x75,0xad,0xa6,0x31,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x30,0x84,0xd7,0xbd,0xd6,0xb5,0xd7,0xb5,0xd6,0xb5,0xb6,0xbd,
+0xd6,0xb5,0xd7,0xbd,0xd6,0xbd,0xb7,0xb5,0xd7,0xb5,0xd6,0xbd,0xd6,0xbd,0xd7,0xb5,
+0xd6,0xb5,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,
+0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,
+0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,
+0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xf7,0xbd,0xd7,0xbd,0xf7,0xbd,0xd7,0xbd,
+0xf7,0xbd,0xd7,0xbd,0xf7,0xbd,0xd7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,
+0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,
+0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,
+0xf7,0xbd,0x18,0xc6,0x34,0xa5,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x8a,0x52,0x18,0xc6,0x17,0xbe,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,
+0xf7,0xbd,0x17,0xbe,0xf7,0xbd,0x17,0xbe,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0x17,0xbe,
+0x17,0xbe,0x17,0xbe,0x17,0xbe,0xf8,0xbd,0x17,0xbe,0xf8,0xbd,0x38,0xc6,0xb2,0x94,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x41,0x08,0x76,0xad,0x38,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,
+0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,
+0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,
+0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,
+0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,
+0x38,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x38,0xc6,0x18,0xc6,0x38,0xc6,0x18,0xc6,
+0x38,0xc6,0x18,0xc6,0x38,0xc6,0x18,0xc6,0x38,0xc6,0x18,0xc6,0x38,0xc6,0x18,0xc6,
+0x38,0xc6,0x18,0xc6,0x38,0xc6,0x18,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x18,0xc6,
+0x38,0xc6,0x55,0xad,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0xc3,0x18,0xb6,0xb5,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,
+0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,
+0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,
+0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,
+0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,
+0x38,0xc6,0x38,0xc6,0x38,0xc6,0x18,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x18,0xc6,
+0x38,0xc6,0x18,0xc6,0x38,0xc6,0x18,0xc6,0x38,0xc6,0x18,0xc6,0x38,0xc6,0x18,0xc6,
+0x38,0xc6,0x18,0xc6,0x38,0xc6,0x18,0xc6,0x38,0xc6,0x18,0xc6,0x38,0xc6,0x18,0xc6,
+0x38,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x38,0xc6,0x18,0xc6,0xa7,0x39,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0xd2,0x9c,0x38,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,
+0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,
+0x18,0xbe,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x75,0xad,0x34,0xa5,
+0x55,0xad,0x76,0xb5,0x71,0x8c,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xf3,0x9c,0x18,0xc6,
+0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,
+0xd6,0xbd,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0x96,0xb5,0x96,0xad,0x75,0xad,
+0x75,0xad,0x55,0xad,0x55,0xad,0xa6,0x31,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x30,0x84,0xf7,0xbd,
+0xb6,0xb5,0xd6,0xb5,0xb7,0xb5,0xd6,0xb5,0xd7,0xbd,0xd6,0xb5,0xd6,0xbd,0xd6,0xbd,
+0xd7,0xb5,0xd6,0xb5,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xb5,0xd6,0xbd,
+0xd7,0xbd,0xd7,0xb5,0xd7,0xbd,0xd6,0xb5,0xd7,0xbd,0xd7,0xb5,0xd7,0xbd,0xd7,0xbd,
+0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,
+0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,
+0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xf7,0xbd,0xd7,0xbd,0xf7,0xbd,0xd7,0xbd,0xf7,0xbd,
+0xd7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,
+0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,
+0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0x17,0xc6,0x14,0xa5,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x8a,0x52,0x18,0xc6,
+0xf7,0xbd,0x17,0xbe,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0x17,0xbe,0xf7,0xbd,
+0x17,0xbe,0xf7,0xbd,0x17,0xbe,0x17,0xbe,0xf7,0xbd,0x17,0xbe,0xf7,0xbd,0x17,0xbe,
+0x17,0xc6,0x17,0xbe,0x38,0xc6,0xb2,0x94,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x41,0x08,0x75,0xad,
+0x18,0xc6,0x18,0xbe,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,
+0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,
+0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,
+0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,
+0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x38,0xc6,
+0x18,0xc6,0x18,0xc6,0x18,0xc6,0x38,0xc6,0x18,0xc6,0x38,0xc6,0x18,0xc6,0x38,0xc6,
+0x18,0xc6,0x38,0xc6,0x18,0xc6,0x38,0xc6,0x18,0xc6,0x38,0xc6,0x18,0xc6,0x38,0xc6,
+0x18,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0xcb,0x5a,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xc3,0x18,0xb6,0xb5,0x38,0xc6,
+0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,
+0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,
+0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,
+0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,
+0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x18,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,
+0x18,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x18,0xc6,0x38,0xc6,0x18,0xc6,0x38,0xc6,
+0x18,0xc6,0x38,0xc6,0x18,0xc6,0x38,0xc6,0x18,0xc6,0x38,0xc6,0x18,0xc6,0x38,0xc6,
+0x18,0xc6,0x18,0xc6,0x18,0xc6,0x38,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,
+0x18,0xc6,0x18,0xc6,0xc7,0x39,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xb2,0x94,0x38,0xc6,0x18,0xc6,
+0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,
+0x18,0xc6,0x18,0xc6,0x18,0xc6,0x17,0xc6,0x18,0xc6,0x17,0xbe,0x18,0xc6,0x18,0xbe,
+0x18,0xc6,0x18,0xc6,0x75,0xad,0x34,0xa5,0x75,0xad,0x14,0xa5,0xe3,0x18,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0xf3,0x9c,0x18,0xc6,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,
+0xf7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xb7,0xbd,0xd6,0xb5,0xb6,0xb5,0xb6,0xb5,
+0x96,0xb5,0x96,0xb5,0x76,0xb5,0x75,0xad,0x55,0xad,0x55,0xad,0x55,0xad,0xa6,0x31,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x30,0x84,0xd7,0xbd,0xd6,0xb5,0xb7,0xbd,0xd7,0xb5,0xd7,0xb5,
+0xd7,0xbd,0xd7,0xb5,0xd6,0xb5,0xd6,0xbd,0xd6,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,
+0xd7,0xb5,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd6,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,
+0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,
+0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,
+0xd7,0xbd,0xd7,0xbd,0xf7,0xbd,0xd7,0xbd,0xf7,0xbd,0xd7,0xbd,0xf7,0xbd,0xf7,0xbd,
+0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,
+0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,
+0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,
+0xf7,0xbd,0x18,0xc6,0x34,0xa5,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x8a,0x52,0x18,0xc6,0xf7,0xbd,0x17,0xbe,0x17,0xbe,0xf7,0xbd,
+0x17,0xbe,0xf7,0xbd,0xf7,0xbd,0xf7,0xc5,0xf7,0xbd,0xf7,0xbd,0x17,0xbe,0xf8,0xc5,
+0x17,0xbe,0xf7,0xc5,0x17,0xbe,0x18,0xc6,0x17,0xc6,0x18,0xbe,0x38,0xc6,0xb2,0x94,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x41,0x08,0x76,0xad,0x38,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,
+0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,
+0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,
+0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,
+0x18,0xc6,0x18,0xc6,0x38,0xc6,0x18,0xc6,0x38,0xc6,0x18,0xc6,0x38,0xc6,0x18,0xc6,
+0x38,0xc6,0x18,0xc6,0x38,0xc6,0x18,0xc6,0x38,0xc6,0x18,0xc6,0x38,0xc6,0x38,0xc6,
+0x38,0xc6,0x18,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,
+0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x58,0xc6,
+0x55,0xad,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0xc3,0x18,0xd6,0xb5,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,
+0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,
+0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,
+0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,
+0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,
+0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,
+0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,
+0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x18,0xc6,0x38,0xc6,0x18,0xc6,
+0x38,0xc6,0x18,0xc6,0x38,0xc6,0x18,0xc6,0x38,0xc6,0x18,0xc6,0xc7,0x39,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x0c,0x63,0x38,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,
+0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,
+0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x96,0xad,0x55,0xad,
+0x75,0xad,0x29,0x4a,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x13,0x9d,0x18,0xc6,
+0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,
+0xd7,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0x96,0xb5,0x96,0xb5,0x95,0xad,0x75,0xad,
+0x55,0xad,0x55,0xad,0x55,0xad,0xa6,0x31,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x30,0x84,0xf7,0xbd,
+0xb7,0xbd,0xd6,0xb5,0xb7,0xbd,0xd6,0xb5,0xd7,0xbd,0xd6,0xb5,0xb6,0xbd,0xd7,0xbd,
+0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xb5,0xd7,0xb5,0xd6,0xbd,0xd7,0xbd,0xd6,0xbd,
+0xd7,0xbd,0xd7,0xb5,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,
+0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,
+0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,
+0xd7,0xbd,0xf7,0xbd,0xd7,0xbd,0xf7,0xbd,0xd7,0xbd,0xf7,0xbd,0xd7,0xbd,0xf7,0xbd,
+0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,
+0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,
+0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0x17,0xc6,0x34,0xa5,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x69,0x4a,0x38,0xc6,
+0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0x17,0xbe,0xf7,0xbd,0xf7,0xbd,0x17,0xbe,0xf7,0xbd,
+0x17,0xbe,0xf7,0xbd,0x17,0xc6,0xf7,0xbd,0xf7,0xc5,0x17,0xbe,0x18,0xc6,0x17,0xbe,
+0xf8,0xc5,0x17,0xbe,0x38,0xc6,0xd2,0x94,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x41,0x08,0x96,0xb5,
+0x38,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,
+0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,
+0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,
+0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,
+0x18,0xc6,0x38,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x38,0xc6,0x18,0xc6,0x38,0xc6,
+0x18,0xc6,0x38,0xc6,0x18,0xc6,0x38,0xc6,0x18,0xc6,0x38,0xc6,0x18,0xc6,0x38,0xc6,
+0x38,0xc6,0x38,0xc6,0x18,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,
+0x38,0xc6,0x38,0xc6,0x38,0xc6,0x58,0xc6,0xcb,0x5a,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xc3,0x18,0xd6,0xb5,0x38,0xc6,
+0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,
+0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,
+0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,
+0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,
+0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,
+0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,
+0x38,0xc6,0x38,0xc6,0x18,0xc6,0x38,0xc6,0x18,0xc6,0x38,0xc6,0x18,0xc6,0x38,0xc6,
+0x18,0xc6,0x38,0xc6,0x18,0xc6,0x38,0xc6,0x18,0xc6,0x38,0xc6,0x18,0xc6,0x38,0xc6,
+0x38,0xc6,0x38,0xc6,0xc7,0x39,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x30,0x8c,0x18,0xc6,
+0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,
+0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,
+0x18,0xc6,0x18,0xc6,0x96,0xb5,0x75,0xad,0x4d,0x6b,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0xd3,0x9c,0x18,0xc6,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,
+0xf7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd6,0xbd,0xb6,0xbd,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,
+0x96,0xb5,0x95,0xb5,0x75,0xad,0x75,0xad,0x55,0xad,0x55,0xad,0x55,0xad,0x86,0x31,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x50,0x84,0xf7,0xbd,0xd6,0xb5,0xd6,0xbd,0xd6,0xb5,0xd7,0xbd,
+0xd7,0xbd,0xd7,0xbd,0xd6,0xb5,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xb5,0xd7,0xbd,
+0xd6,0xb5,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,
+0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,
+0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,
+0xf7,0xbd,0xd7,0xbd,0xf7,0xbd,0xd7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,
+0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,
+0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,
+0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,
+0xf7,0xbd,0x18,0xc6,0x34,0xa5,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x65,0x29,0xf7,0xbd,0x18,0xc6,0xf8,0xc5,0x17,0xbe,0x17,0xc6,
+0x17,0xbe,0x18,0xc6,0x17,0xc6,0x17,0xc6,0x17,0xc6,0x17,0xc6,0x18,0xbe,0x17,0xbe,
+0x18,0xc6,0x18,0xc6,0x18,0xbe,0x18,0xc6,0x17,0xbe,0x18,0xc6,0x58,0xc6,0xcf,0x7b,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0xf3,0x9c,0x59,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,
+0x38,0xc6,0x18,0xc6,0x38,0xc6,0x18,0xc6,0x38,0xc6,0x18,0xc6,0x38,0xc6,0x18,0xc6,
+0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,
+0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,
+0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,
+0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,
+0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,
+0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x58,0xc6,0x58,0xce,0x71,0x8c,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x34,0xa5,0x59,0xce,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,
+0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x58,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,
+0x58,0xc6,0x38,0xc6,0x58,0xc6,0x38,0xc6,0x58,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,
+0x58,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,
+0x58,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,
+0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,
+0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,
+0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,
+0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x59,0xc6,0xb6,0xb5,0x82,0x10,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x86,0x31,0x0c,0x63,0x30,0x84,0xf3,0x9c,0x75,0xad,
+0xf7,0xbd,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x18,0xc6,0x18,0xc6,
+0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0xb6,0xb5,0x51,0x8c,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x0c,0x63,0x18,0xc6,
+0x18,0xc6,0x17,0xbe,0x18,0xc6,0x18,0xbe,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,
+0xd7,0xbd,0xd7,0xbd,0xd6,0xb5,0xb6,0xb5,0xb6,0xb5,0x96,0xb5,0x95,0xb5,0x75,0xad,
+0x75,0xad,0x75,0xad,0x92,0x94,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x2d,0x6b,0xf7,0xbd,
+0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,
+0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xf7,0xbd,
+0xd7,0xbd,0xf7,0xbd,0xd7,0xbd,0xf7,0xbd,0xd7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,
+0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,
+0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,
+0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,
+0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0x17,0xbe,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,
+0xf7,0xbd,0xf7,0xbd,0x17,0xbe,0x17,0xbe,0xf7,0xbd,0xf7,0xbd,0xf8,0xbd,0x17,0xbe,
+0xf7,0xc5,0x17,0xbe,0x17,0xc6,0x17,0xbe,0x17,0xc6,0x38,0xc6,0x10,0x84,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xae,0x73,
+0xd7,0xbd,0x17,0xbe,0xf7,0xbd,0x17,0xbe,0x17,0xbe,0x17,0xbe,0x18,0xc6,0x17,0xbe,
+0xf8,0xbd,0x17,0xbe,0x18,0xc6,0x17,0xbe,0x18,0xbe,0x18,0xc6,0x18,0xc6,0x17,0xc6,
+0x18,0xc6,0xf7,0xbd,0xf3,0x9c,0x62,0x10,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x65,0x29,
+0x35,0xad,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,
+0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,
+0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,
+0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0x17,0xbe,
+0xf7,0xbd,0x17,0xbe,0xf7,0xbd,0x17,0xbe,0xf7,0xbd,0x17,0xbe,0xf7,0xbd,0x17,0xbe,
+0xf7,0xbd,0xd7,0xbd,0xd7,0xbd,0xf7,0xbd,0xd7,0xbd,0xf7,0xbd,0xd7,0xbd,0xd7,0xbd,
+0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xf7,0xbd,0xd7,0xbd,0xf7,0xbd,
+0xd7,0xbd,0x76,0xad,0x8e,0x73,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x86,0x31,0x54,0xa5,
+0xd7,0xbd,0xd7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xd7,0xbd,0xd6,0xb5,
+0xb6,0xb5,0xd6,0xb5,0xb6,0xb5,0xd6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,
+0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xd6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xd6,0xb5,
+0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xd6,0xb5,0xb6,0xb5,0xd6,0xb5,
+0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xd6,0xb5,
+0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,
+0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,
+0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0xb6,0xb5,0x96,0xb5,0x96,0xb5,
+0x54,0xa5,0x08,0x42,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x45,0x29,0x29,0x4a,0x8e,0x73,0x71,0x8c,
+0x34,0xa5,0x96,0xb5,0x17,0xbe,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,0x38,0xc6,
+0x18,0xc6,0x38,0xc6,0x55,0xad,0xa2,0x18,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x6d,0x6b,0x34,0xa5,0x34,0xa5,0x34,0xa5,0x34,0xa5,
+0x34,0xa5,0x34,0xa5,0x14,0xa5,0x14,0xa5,0x14,0xa5,0x13,0x9d,0xf3,0x9c,0xf3,0x9c,
+0xf3,0x9c,0xd3,0x9c,0xd3,0x9c,0xb2,0x94,0xb2,0x94,0xef,0x7b,0x04,0x21,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x10,0x84,0x55,0xad,0x55,0xad,0x75,0xad,0x55,0xad,
+0x75,0xad,0x55,0xad,0x75,0xad,0x75,0xad,0x75,0xad,0x55,0xad,0x75,0xad,0x75,0xad,
+0x75,0xad,0x75,0xad,0x75,0xad,0x75,0xad,0x75,0xad,0x55,0xad,0x75,0xad,0x55,0xad,
+0x75,0xad,0x75,0xad,0x75,0xad,0x75,0xad,0x75,0xad,0x75,0xad,0x75,0xad,0x75,0xad,
+0x75,0xad,0x75,0xad,0x75,0xad,0x75,0xad,0x75,0xad,0x75,0xad,0x75,0xad,0x75,0xad,
+0x75,0xad,0x55,0xad,0x55,0xad,0x55,0xad,0x55,0xad,0x55,0xad,0x55,0xad,0x55,0xad,
+0x55,0xad,0x55,0xad,0x55,0xad,0x55,0xad,0x55,0xad,0x55,0xad,0x55,0xad,0x55,0xad,
+0x55,0xad,0x55,0xad,0x75,0xad,0x55,0xad,0x55,0xad,0x55,0xad,0x55,0xad,0x75,0xad,
+0x55,0xad,0x55,0xad,0x75,0xad,0x55,0xad,0x75,0xad,0x55,0xad,0x75,0xad,0x75,0xad,
+0x75,0xad,0x31,0x8c,0x20,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x24,0x21,0xc7,0x39,0xc7,0x39,0xc7,0x39,
+0xc7,0x39,0xc7,0x39,0xa7,0x39,0xc7,0x39,0xc7,0x39,0xc7,0x39,0xa7,0x39,0xc7,0x39,
+0xc7,0x39,0xc7,0x39,0xa7,0x39,0xc7,0x39,0xc7,0x39,0x86,0x31,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x65,0x29,0x66,0x31,0x66,0x31,
+0x65,0x29,0x66,0x31,0x65,0x29,0x66,0x31,0x65,0x29,0x66,0x31,0x65,0x29,0x66,0x31,
+0x65,0x29,0x66,0x31,0x65,0x29,0x66,0x31,0x65,0x29,0x66,0x31,0x65,0x29,0x66,0x31,
+0x65,0x29,0x66,0x31,0x65,0x29,0x66,0x31,0x65,0x29,0x66,0x31,0x65,0x29,0x66,0x31,
+0x65,0x29,0x66,0x31,0x65,0x29,0x66,0x31,0x65,0x29,0x66,0x31,0x65,0x29,0x66,0x31,
+0x65,0x29,0x66,0x31,0x65,0x29,0x66,0x31,0x45,0x29,0x24,0x21,0x24,0x21,0x24,0x21,
+0x24,0x21,0x24,0x21,0x24,0x21,0x24,0x21,0x24,0x21,0x24,0x21,0x24,0x21,0x24,0x21,
+0x24,0x21,0x24,0x21,0x24,0x21,0x24,0x21,0x24,0x21,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x04,0x21,0x24,0x21,0x24,0x21,0x24,0x21,
+0x24,0x21,0x24,0x29,0x24,0x21,0xe3,0x18,0xc3,0x18,0xc3,0x18,0xc3,0x18,0xc3,0x18,
+0xc3,0x18,0xc3,0x18,0xc3,0x18,0xc3,0x18,0xc3,0x18,0xc3,0x18,0xc3,0x18,0xc3,0x18,
+0xc3,0x18,0xc3,0x18,0xc3,0x18,0xc3,0x18,0xc3,0x18,0xc3,0x18,0xc3,0x18,0xc3,0x18,
+0xc3,0x18,0xc3,0x18,0xc3,0x18,0xc3,0x18,0xc3,0x18,0xc3,0x18,0xc3,0x18,0xc3,0x18,
+0xc3,0x18,0xc3,0x18,0xc3,0x18,0xc3,0x18,0xc3,0x18,0xc3,0x18,0xc3,0x18,0xc3,0x18,
+0xc3,0x18,0xc3,0x18,0xc3,0x18,0xc3,0x18,0xc3,0x18,0xc3,0x18,0xc3,0x18,0xc3,0x18,
+0xc3,0x18,0xc3,0x18,0xc3,0x18,0xc3,0x18,0xc3,0x18,0xc3,0x18,0xc3,0x18,0xc3,0x18,
+0xc3,0x18,0xc3,0x18,0x61,0x08,0x41,0x08,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x82,0x10,0x86,0x31,0xaa,0x52,
+0xef,0x7b,0xd3,0x9c,0x75,0xad,0xd6,0xb5,0xf7,0xbd,0xb6,0xb5,0x8a,0x52,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x64,0x00,0xc6,0x00,0xc5,0x00,0xc6,0x00,
+0xc5,0x00,0x85,0x00,0x84,0x00,0x43,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x41,0x08,0xa2,0x10,0x82,0x10,0xa2,0x10,0x82,0x10,0xa2,0x10,0x82,0x10,0xa2,0x10,
+0x82,0x10,0xa2,0x10,0x82,0x10,0xa2,0x10,0xa2,0x10,0xa2,0x10,0x82,0x10,0xa2,0x10,
+0xa2,0x10,0xa2,0x10,0x82,0x10,0xa2,0x10,0xa2,0x10,0xa2,0x10,0xa2,0x10,0xa2,0x10,
+0xa2,0x10,0xa2,0x10,0xa2,0x10,0xa2,0x10,0xa2,0x10,0xa2,0x10,0xa2,0x10,0xa2,0x10,
+0xa3,0x10,0xa2,0x10,0xa2,0x18,0xa3,0x10,0x82,0x10,0x21,0x08,0x21,0x08,0x20,0x08,
+0x21,0x08,0x21,0x08,0x21,0x08,0x21,0x08,0x21,0x08,0x21,0x08,0x21,0x08,0x21,0x08,
+0x21,0x08,0x21,0x08,0x21,0x08,0x20,0x08,0x21,0x08,0x21,0x08,0x21,0x08,0x21,0x08,
+0x21,0x08,0x21,0x08,0x21,0x08,0x21,0x08,0x21,0x08,0x21,0x08,0x21,0x08,0x21,0x08,
+0x21,0x08,0x21,0x08,0x21,0x08,0x41,0x08,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x04,0x21,
+0x66,0x31,0x61,0x08,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0xd6,0x33,0x99,0x44,0x78,0x44,0x78,0x44,0x58,0x44,0x58,0x44,0x98,0x4c,0x99,0x54,
+0x78,0x54,0xb5,0x3b,0x6f,0x1a,0x28,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x00,
+0x69,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x2d,0x12,0x99,0x44,0x99,0x44,0x99,0x44,
+0x99,0x44,0x79,0x44,0x99,0x44,0xda,0x4c,0x1b,0x5d,0x3c,0x65,0xfb,0x4c,0x79,0x34,
+0xb5,0x23,0xcb,0x11,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x12,0x23,0x79,0x3c,0xc6,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x12,0x23,0xb9,0x44,0x79,0x44,0x79,0x44,0x78,0x44,0x79,0x44,0x78,0x44,
+0x99,0x4c,0xfa,0x5c,0x1b,0x65,0xfb,0x54,0x9a,0x3c,0x59,0x24,0xd1,0x22,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x0d,0x0a,0x79,0x3c,
+0x79,0x3c,0x4e,0x12,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0xf6,0x33,0x99,0x44,
+0x78,0x44,0x79,0x44,0x78,0x44,0x78,0x44,0x78,0x44,0x99,0x44,0xda,0x54,0x1b,0x5d,
+0xfb,0x54,0x9a,0x3c,0x59,0x24,0x72,0x3b,0x20,0x08,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0xa6,0x00,0x37,0x34,0x79,0x3c,0x79,0x3c,0xb5,0x2b,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x07,0x01,0x58,0x44,0x79,0x44,0x78,0x44,0x78,0x44,0x78,0x44,
+0x58,0x44,0x58,0x3c,0x78,0x44,0xb9,0x4c,0x1b,0x5d,0x1b,0x5d,0xba,0x44,0x79,0x2c,
+0xb2,0x5b,0xa1,0x18,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x95,0x2b,0x79,0x3c,0x58,0x3c,
+0x79,0x3c,0x58,0x3c,0xc6,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x2d,0x12,
+0x99,0x44,0x78,0x44,0x78,0x44,0x78,0x44,0x78,0x44,0x58,0x44,0x58,0x3c,0x58,0x44,
+0x99,0x4c,0xfa,0x5c,0x1b,0x5d,0xba,0x44,0x78,0x4c,0xf0,0x7b,0x24,0x29,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0xb0,0x1a,0x79,0x3c,0x58,0x3c,0x58,0x3c,0x78,0x3c,0x99,0x3c,0x6f,0x12,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x12,0x23,0x99,0x44,0x58,0x44,0x78,0x44,
+0x58,0x44,0x58,0x3c,0x58,0x3c,0x58,0x3c,0x58,0x3c,0x79,0x44,0xda,0x54,0x1b,0x5d,
+0xda,0x4c,0xd5,0x84,0x50,0x8c,0xc7,0x39,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x8a,0x01,0x58,0x3c,0x58,0x3c,0x58,0x3c,0x58,0x3c,
+0x58,0x3c,0x79,0x3c,0xb5,0x2b,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x01,0x00,0xd6,0x33,0x79,0x44,0x58,0x44,0x58,0x44,0x58,0x44,0x58,0x3c,0x58,0x3c,
+0x58,0x3c,0x58,0x3c,0x79,0x44,0xda,0x54,0x1b,0x5d,0x18,0x85,0x13,0xa5,0x71,0x8c,
+0x69,0x4a,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x44,0x00,0xf6,0x33,
+0x58,0x3c,0x58,0x3c,0x58,0x3c,0x58,0x3c,0x78,0x3c,0x79,0x3c,0x58,0x34,0xa6,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x07,0x01,0x37,0x3c,0x58,0x44,
+0x58,0x44,0x58,0x3c,0x58,0x3c,0x58,0x3c,0x58,0x3c,0x58,0x3c,0x58,0x3c,0x78,0x44,
+0xba,0x4c,0x59,0x8d,0x96,0xb5,0x14,0xa5,0x92,0x94,0xeb,0x5a,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x33,0x23,0x58,0x3c,0x58,0x3c,0x58,0x3c,0x58,0x3c,0x58,0x3c,
+0x58,0x3c,0x58,0x3c,0x58,0x34,0xed,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x2d,0x12,0x78,0x44,0x78,0x44,0x58,0x44,0x58,0x3c,0x58,0x3c,
+0x58,0x3c,0x58,0x44,0x58,0x3c,0x58,0x3c,0x79,0x34,0x59,0x85,0x58,0xce,0xd6,0xb5,
+0x34,0xa5,0xb2,0x94,0x6d,0x6b,0x20,0x00,0x00,0x00,0x2e,0x12,0x58,0x3c,0x58,0x3c,
+0x58,0x3c,0x58,0x3c,0x58,0x3c,0x58,0x3c,0x78,0x3c,0x58,0x34,0x38,0x2c,0xf2,0x12,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x8f,0x1a,
+0x74,0x2b,0x94,0x2b,0xb5,0x33,0xb5,0x33,0xd5,0x33,0xd6,0x33,0xf6,0x33,0xf6,0x33,
+0xd6,0x23,0xf7,0x7c,0x9a,0xd6,0x59,0xce,0xd7,0xbd,0x55,0xad,0xd3,0x9c,0xae,0x73,
+0xa8,0x21,0xf7,0x33,0x38,0x3c,0x58,0x3c,0x58,0x3c,0x58,0x3c,0x58,0x3c,0x58,0x3c,
+0x58,0x3c,0x38,0x34,0xf7,0x23,0x74,0x1b,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x82,0x10,0x00,0x00,0x00,0x00,0x00,0x00,
+0x01,0x00,0x02,0x00,0x23,0x00,0x23,0x00,0x01,0x00,0xec,0x5a,0xba,0xd6,0x9a,0xd6,
+0x79,0xce,0xf7,0xbd,0x75,0xad,0xd3,0x9c,0x51,0x84,0x36,0x4c,0x38,0x34,0x58,0x3c,
+0x58,0x3c,0x58,0x3c,0x58,0x3c,0x58,0x3c,0x58,0x3c,0x17,0x2c,0xf7,0x1b,0x95,0x23,
+0x64,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x82,0x10,0xec,0x5a,
+0x30,0x84,0x8e,0x73,0x20,0x08,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0xe7,0x39,0xba,0xd6,0x9a,0xd6,0x9a,0xd6,0x99,0xce,0x18,0xc6,0x96,0xb5,
+0xd2,0x9c,0xd4,0x43,0x38,0x34,0x38,0x3c,0x38,0x3c,0x58,0x3c,0x58,0x3c,0x58,0x3c,
+0x58,0x34,0x17,0x24,0xd6,0x1b,0xb5,0x23,0x85,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x69,0x4a,0x0f,0x7c,0x71,0x8c,0xd3,0x9c,0x55,0xad,0xb2,0x94,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x08,0x42,0xba,0xd6,0x9a,0xd6,
+0x9a,0xd6,0x9a,0xd6,0x99,0xd6,0x59,0xce,0x0f,0x84,0xcc,0x01,0x58,0x3c,0x38,0x3c,
+0x58,0x3c,0x58,0x3c,0x58,0x3c,0x58,0x3c,0x37,0x2c,0xf6,0x23,0xb5,0x13,0x53,0x23,
+0x43,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0xa7,0x39,0xae,0x73,0x51,0x8c,0xb2,0x94,0x14,0xa5,
+0x75,0xad,0xf7,0xbd,0x79,0xce,0xd2,0x94,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0xe7,0x39,0xba,0xd6,0x9a,0xd6,0x9a,0xd6,0x9a,0xd6,0xba,0xd6,0x38,0xc6,
+0xc3,0x18,0x24,0x00,0x17,0x34,0x58,0x34,0x58,0x3c,0x58,0x3c,0x58,0x3c,0x58,0x34,
+0x17,0x2c,0xd6,0x1b,0x95,0x13,0xd0,0x22,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x25,0x29,0x6d,0x6b,0x51,0x8c,
+0x92,0x94,0xf3,0x9c,0x55,0xad,0xd6,0xb5,0x38,0xc6,0x79,0xce,0x9a,0xd6,0xba,0xd6,
+0x0c,0x63,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xc7,0x39,0x9a,0xd6,0x9a,0xd6,
+0x99,0xd6,0x9a,0xd6,0x9a,0xd6,0x8a,0x52,0x00,0x00,0x00,0x00,0x74,0x23,0x58,0x3c,
+0x58,0x3c,0x58,0x3c,0x58,0x3c,0x38,0x34,0xf7,0x23,0xd6,0x13,0x94,0x1b,0xa9,0x21,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x81,0x10,
+0xeb,0x5a,0x30,0x84,0x71,0x94,0xd3,0x9c,0x34,0xa5,0x96,0xb5,0xf7,0xbd,0x79,0xce,
+0x9a,0xd6,0x9a,0xd6,0x9a,0xd6,0xba,0xd6,0x79,0xce,0xa6,0x31,0x00,0x00,0x00,0x00,
+0x00,0x00,0xc7,0x39,0x9a,0xd6,0x9a,0xd6,0x9a,0xd6,0xba,0xd6,0x51,0x8c,0x00,0x00,
+0x00,0x00,0x00,0x00,0x0d,0x12,0x58,0x3c,0x58,0x34,0x58,0x3c,0x58,0x3c,0x37,0x2c,
+0xd6,0x0b,0x95,0x03,0xd2,0x5b,0x41,0x08,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x08,0x8a,0x4a,0x11,0x74,0x72,0x84,0xb3,0x8c,0x14,0x9d,0x75,0xb5,
+0xf7,0xbd,0x58,0xce,0x99,0xce,0x9a,0xd6,0xba,0xd6,0x9a,0xd6,0x9a,0xd6,0x9a,0xd6,
+0xba,0xd6,0xd7,0xbd,0x41,0x08,0x00,0x00,0x00,0x00,0x86,0x31,0x79,0xce,0x9a,0xd6,
+0xba,0xd6,0x96,0xb5,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x85,0x00,0x17,0x34,
+0x58,0x3c,0x58,0x34,0x38,0x24,0xd7,0x03,0x16,0x3c,0xb5,0x84,0x6d,0x6b,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x2c,0x22,0x15,0x4c,0x78,0x4c,0xb9,0x4c,
+0xfa,0x54,0xfa,0x64,0xf9,0x64,0x39,0x85,0xd9,0xad,0x39,0xc6,0xba,0xd6,0xda,0xd6,
+0xba,0xd6,0x9a,0xd6,0x9a,0xd6,0xba,0xd6,0x9a,0xd6,0xda,0xd6,0xd3,0x9c,0x00,0x00,
+0x00,0x00,0x86,0x31,0x79,0xce,0xba,0xd6,0x59,0xce,0x65,0x29,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x13,0x13,0x58,0x2c,0x78,0x4c,0xf8,0x74,0x78,0x95,
+0xb7,0xb5,0x54,0xad,0x24,0x21,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xa5,0x00,0xb5,0x33,
+0x79,0x2c,0x9a,0x2c,0xdb,0x44,0xfb,0x54,0xfb,0x54,0xda,0x54,0xda,0x4c,0xba,0x4c,
+0x99,0x44,0xc8,0x21,0xe8,0x41,0x92,0x94,0xd7,0xbd,0x9a,0xd6,0xda,0xd6,0xba,0xd6,
+0xba,0xd6,0x9a,0xd6,0xba,0xd6,0x2c,0x63,0x00,0x00,0xe4,0x20,0xf7,0xbd,0xba,0xd6,
+0x0c,0x63,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x91,0x5b,
+0xb9,0x9d,0x59,0xbe,0x9a,0xd6,0x59,0xce,0xd7,0xbd,0x10,0x84,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x85,0x00,0xf7,0x2b,0x9a,0x2c,0xba,0x44,0xfb,0x54,0xfb,0x5c,0xfa,0x54,
+0xda,0x54,0xda,0x54,0xba,0x54,0xda,0x54,0xf6,0x3b,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0xa7,0x39,0xcf,0x7b,0x96,0xb5,0x59,0xce,0xba,0xd6,0xdb,0xde,0x96,0xb5,
+0x00,0x00,0x00,0x00,0xe3,0x18,0xc7,0x39,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x29,0x4a,0x92,0x94,0xf7,0xbd,0x9a,0xd6,0x9a,0xd6,0x9a,0xd6,0x79,0xce,0x18,0xbe,
+0x75,0xad,0xe7,0x39,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xb5,0x2b,0xbb,0x3c,0xdb,0x4c,
+0x1b,0x5d,0xfb,0x5c,0xfa,0x54,0xda,0x54,0xda,0x54,0xda,0x54,0xda,0x54,0xda,0x54,
+0x8e,0x1a,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x45,0x29,0x4d,0x6b,0x34,0xa5,0x08,0x42,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x08,0x42,0x92,0x94,0xf7,0xbd,0xba,0xd6,0xba,0xd6,0xba,0xd6,0x9a,0xd6,
+0x9a,0xd6,0x9a,0xd6,0x59,0xce,0xf7,0xbd,0x92,0x94,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x8f,0x1a,0xfb,0x4c,0x1b,0x5d,0x1b,0x5d,0xfa,0x5c,0xfa,0x54,0xda,0x54,0xda,0x54,
+0xda,0x54,0xda,0x54,0xda,0x54,0x99,0x4c,0xa5,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x86,0x31,0x9a,0xd6,0xba,0xd6,0xba,0xd6,
+0x9a,0xd6,0x9a,0xd6,0x9a,0xd6,0x9a,0xd6,0x9a,0xd6,0x99,0xce,0x38,0xc6,0xb6,0xb5,
+0xab,0x5a,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x22,0x00,0xb9,0x54,0x3b,0x5d,0x1b,0x5d,0xfa,0x54,
+0xfa,0x54,0xda,0x54,0xda,0x54,0xda,0x54,0xda,0x54,0xda,0x54,0xda,0x54,0xb5,0x3b,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x24,0x21,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x45,0x29,0x38,0xc6,0xda,0xd6,0xba,0xd6,0xba,0xd6,0x9a,0xd6,0x9a,0xd6,0x9a,0xd6,
+0x9a,0xd6,0x79,0xce,0xf7,0xbd,0x14,0xa5,0x61,0x08,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xad,0x22,
+0x3c,0x5d,0x1b,0x5d,0xfa,0x54,0xfa,0x54,0xda,0x54,0xda,0x54,0xda,0x54,0xda,0x54,
+0xda,0x54,0xda,0x54,0xda,0x54,0x0b,0x12,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0xa6,0x31,0xae,0x73,0xb6,0xb5,0x79,0xce,0x8e,0x73,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xe4,0x20,0xeb,0x5a,0x34,0xa5,
+0x38,0xc6,0xba,0xd6,0xba,0xd6,0xba,0xd6,0x9a,0xd6,0x58,0xc6,0xb6,0xb5,0x8d,0x6b,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x37,0x4c,0x1b,0x5d,0xfb,0x54,0xfa,0x54,0xda,0x54,
+0xfa,0x54,0xda,0x54,0xda,0x54,0xda,0x54,0xda,0x54,0xda,0x54,0x78,0x4c,0x02,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xe8,0x41,0x30,0x84,0xd7,0xb5,0x9a,0xd6,
+0xda,0xd6,0xba,0xd6,0xdb,0xde,0x75,0xad,0x00,0x00,0x00,0x00,0x8a,0x52,0x8e,0x73,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xc3,0x18,0xaa,0x52,0xf3,0x9c,0x18,0xc6,
+0x9a,0xd6,0x38,0xc6,0x55,0xad,0x24,0x29,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x26,0x01,0xfb,0x5c,
+0xfb,0x5c,0xfb,0x54,0xfb,0x54,0xfa,0x54,0xfa,0x54,0xfa,0x54,0xda,0x54,0xfa,0x54,
+0xfb,0x54,0xba,0x54,0xaf,0x22,0x00,0x00,0x00,0x00,0x49,0x4a,0x92,0x94,0x38,0xc6,
+0xba,0xd6,0xda,0xd6,0xba,0xd6,0xba,0xd6,0x9a,0xd6,0xba,0xd6,0x79,0xce,0x86,0x31,
+0x00,0x00,0x45,0x29,0x9a,0xd6,0xdb,0xde,0x10,0x84,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x82,0x10,0x08,0x42,0x10,0x7c,0x32,0x74,0x01,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x10,0x2b,0x1b,0x5d,0xfb,0x5c,0xfb,0x5c,0xfb,0x5c,0xfb,0x5c,
+0x1b,0x55,0xfb,0x54,0x98,0x4c,0xb5,0x3b,0x4d,0x1a,0xc5,0x00,0x00,0x00,0x00,0x00,
+0x10,0x84,0xf7,0xbd,0xba,0xd6,0xfb,0xde,0xdb,0xde,0xba,0xd6,0x9a,0xd6,0x9a,0xd6,
+0xba,0xd6,0xba,0xd6,0x6d,0x6b,0x00,0x00,0x00,0x00,0x66,0x31,0x79,0xce,0xba,0xd6,
+0xba,0xd6,0x69,0x4a,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x45,0x00,0x54,0x23,0x58,0x34,0xf6,0x33,0xf2,0x22,0x69,0x01,0x02,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x57,0x4c,0x1b,0x5d,
+0x1b,0x5d,0x1b,0x5d,0xfb,0x5c,0x58,0x4c,0x53,0x33,0xea,0x11,0x43,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xcf,0x7b,0x96,0xb5,0x59,0xce,0xdb,0xde,
+0xdb,0xde,0xba,0xd6,0x9a,0xd6,0x9a,0xd6,0xdb,0xd6,0x34,0xa5,0x00,0x00,0x00,0x00,
+0x00,0x00,0x65,0x29,0x79,0xce,0xba,0xd6,0xba,0xd6,0x58,0xc6,0x45,0x29,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x4e,0x12,0x38,0x3c,0x99,0x44,0x79,0x44,0x99,0x44,
+0x99,0x44,0x99,0x44,0x17,0x3c,0x12,0x23,0x89,0x01,0x02,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x26,0x01,0x1b,0x5d,0xda,0x54,0x16,0x44,0xef,0x2a,0x47,0x09,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0xaa,0x52,0x75,0xad,0x38,0xc6,0xda,0xd6,0xfb,0xde,0xba,0xd6,0xba,0xd6,0xba,0xd6,
+0x18,0xc6,0xe3,0x18,0x00,0x00,0x00,0x00,0x00,0x00,0x66,0x31,0x79,0xce,0xba,0xd6,
+0x9a,0xd6,0xba,0xd6,0xb6,0xb5,0x00,0x00,0x00,0x00,0x85,0x00,0x74,0x2b,0x99,0x44,
+0x79,0x44,0x79,0x44,0x79,0x44,0x79,0x44,0x79,0x44,0x79,0x44,0x99,0x44,0xba,0x44,
+0xb9,0x44,0x17,0x3c,0x12,0x23,0x89,0x01,0x02,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0xea,0x11,0xc5,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x65,0x29,0x54,0xa5,0xf7,0xbd,0xba,0xd6,
+0xfb,0xde,0xda,0xd6,0xba,0xd6,0xba,0xd6,0x69,0x4a,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x65,0x29,0x79,0xce,0xba,0xd6,0x9a,0xd6,0x9a,0xd6,0xda,0xd6,0x92,0x94,
+0xab,0x01,0x37,0x3c,0x99,0x44,0x78,0x44,0x79,0x44,0x79,0x44,0x79,0x44,0x79,0x44,
+0x79,0x44,0x99,0x44,0x99,0x44,0x99,0x44,0x99,0x44,0x9a,0x44,0xba,0x44,0xba,0x44,
+0x38,0x3c,0x53,0x23,0x84,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x41,0x08,0xb2,0x94,0xd7,0xb5,0x79,0xce,0xfb,0xde,0xdb,0xde,0xda,0xde,0x10,0x84,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x66,0x31,0x79,0xce,0xba,0xd6,
+0x9a,0xd6,0x9a,0xd6,0x9a,0xd6,0xba,0xd6,0x59,0x85,0x79,0x34,0x79,0x44,0x79,0x44,
+0x99,0x44,0x79,0x44,0x99,0x44,0x99,0x44,0x99,0x44,0x99,0x44,0x99,0x44,0x99,0x44,
+0x99,0x44,0x99,0x44,0x99,0x44,0x9a,0x44,0xda,0x44,0x79,0x44,0x07,0x01,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x10,0x84,0x96,0xb5,0x59,0xce,
+0xdb,0xde,0xfb,0xde,0x3a,0xbe,0xc9,0x19,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x65,0x29,0x79,0xce,0xda,0xd6,0xba,0xd6,0xba,0xd6,0xba,0xd6,0xba,0xd6,
+0x9a,0xce,0xf9,0x6c,0x59,0x34,0x79,0x44,0x79,0x44,0x99,0x44,0x99,0x44,0x99,0x44,
+0x99,0x44,0x99,0x44,0x99,0x44,0x99,0x44,0x99,0x44,0x99,0x44,0xba,0x44,0xba,0x44,
+0xb5,0x2b,0xa5,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x2c,0x63,0x75,0xad,0x18,0xc6,0xda,0xde,0xdb,0xd6,0x3a,0x75,0x99,0x44,
+0x6d,0x1a,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x45,0x29,0xba,0xd6,0x1c,0xe7,
+0xfb,0xde,0xfb,0xde,0xfb,0xde,0xdb,0xde,0xfb,0xde,0x7a,0xc6,0x98,0x4c,0x38,0x2c,
+0x58,0x34,0x58,0x34,0x58,0x34,0x79,0x3c,0x79,0x3c,0x79,0x3c,0x79,0x3c,0x79,0x3c,
+0x99,0x3c,0x9a,0x44,0x79,0x44,0xb0,0x1a,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xe7,0x39,0x55,0xad,0xf7,0xbd,
+0xba,0xd6,0xda,0x9d,0xba,0x44,0xda,0x54,0xda,0x54,0x73,0x33,0x02,0x00,0x00,0x00,
+0x00,0x00,0x65,0x29,0xda,0xde,0x1c,0xe7,0x1b,0xdf,0x1c,0xe7,0x1b,0xdf,0x1c,0xdf,
+0x1c,0xe7,0x3c,0xe7,0x1a,0xb6,0xd6,0x13,0xd6,0x13,0xf6,0x23,0xf7,0x23,0x17,0x24,
+0x17,0x24,0x17,0x24,0x17,0x24,0x38,0x2c,0x38,0x2c,0xb5,0x23,0x28,0x01,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0xa3,0x18,0xf3,0x9c,0xd7,0xbd,0xd9,0xa5,0xba,0x4c,0xda,0x4c,0xda,0x54,
+0xda,0x54,0xda,0x54,0x37,0x44,0x07,0x01,0x00,0x00,0xa7,0x39,0x59,0xce,0x79,0xce,
+0x99,0xce,0x9a,0xd6,0xba,0xd6,0xba,0xd6,0xba,0xd6,0xdb,0xde,0xfb,0xde,0x58,0x95,
+0x74,0x03,0x95,0x03,0x95,0x1b,0x95,0x1b,0xb5,0x1b,0xb5,0x1b,0xd6,0x1b,0xd6,0x1b,
+0x6f,0x0a,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x51,0x8c,0x96,0xad,
+0x98,0x54,0x99,0x3c,0xda,0x54,0xda,0x54,0xda,0x54,0xda,0x54,0xda,0x54,0x99,0x4c,
+0x48,0x01,0x00,0x00,0x0c,0x63,0x8e,0x73,0x30,0x84,0x92,0x94,0xf3,0x9c,0x34,0xa5,
+0x75,0xad,0xb6,0xb5,0x18,0xbe,0x58,0xc6,0x16,0x95,0x93,0x3b,0x33,0x0b,0x53,0x13,
+0x53,0x13,0x73,0x1b,0xd0,0x1a,0xe7,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x8d,0x73,0xf6,0x8c,0x17,0x0c,0x99,0x44,0xda,0x54,0xda,0x54,
+0xda,0x54,0xda,0x54,0xda,0x54,0xfb,0x54,0xcf,0x22,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x41,0x08,0xe4,0x20,0x86,0x31,0x08,0x42,
+0xeb,0x5a,0xcc,0x52,0x4c,0x32,0x4d,0x1a,0x0c,0x1a,0xe6,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x69,0x52,0x55,0x64,
+0xf7,0x03,0x79,0x3c,0xda,0x4c,0xfa,0x54,0xda,0x54,0xda,0x54,0xda,0x54,0xfa,0x54,
+0xaf,0x22,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x45,0x29,0xf5,0x4b,0xf7,0x03,0x58,0x34,0xda,0x4c,0xda,0x54,
+0xda,0x54,0xda,0x54,0xfa,0x54,0xfb,0x54,0xcf,0x22,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x41,0x08,0x52,0x33,
+0xd6,0x0b,0x38,0x2c,0xba,0x4c,0xfa,0x54,0xfa,0x54,0xfa,0x54,0xda,0x54,0xfb,0x54,
+0xaf,0x22,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0xd0,0x2a,0xd6,0x13,0x18,0x24,0x99,0x44,0xfb,0x54,
+0xfb,0x54,0xfb,0x54,0xfa,0x54,0xfb,0x54,0xcf,0x22,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x89,0x11,
+0xd6,0x23,0x17,0x1c,0x79,0x3c,0xfa,0x54,0xfb,0x54,0xfb,0x54,0xfb,0x54,0x1b,0x55,
+0x8e,0x22,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xb0,0x22,0x18,0x1c,0x79,0x34,0xda,0x54,
+0xfb,0x54,0xfb,0x54,0xfb,0x54,0x1b,0x5d,0x8d,0x1a,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x12,0x1b,0x59,0x2c,0xda,0x4c,0xfb,0x54,0xfb,0x54,0xfb,0x54,0x1b,0x55,
+0x8d,0x1a,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xd1,0x1a,0xda,0x4c,
+0x1b,0x55,0xfb,0x5c,0xfb,0x54,0x1b,0x5d,0x6c,0x1a,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x6d,0x1a,0xda,0x54,0x1b,0x5d,0xfb,0x54,0x1b,0x5d,
+0x2b,0x1a,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x67,0x09,0x78,0x4c,0x3c,0x5d,0x1c,0x5d,0x2b,0x1a,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x73,0x33,0x3c,0x5d,
+0x2b,0x1a,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00};
+#endif
diff --git a/lib/tizen/tizen_logo_16bpp_gzip.h b/lib/tizen/tizen_logo_16bpp_gzip.h
new file mode 100644
index 0000000000..b05498df4e
--- /dev/null
+++ b/lib/tizen/tizen_logo_16bpp_gzip.h
@@ -0,0 +1,648 @@
+/*
+ * (C) Copyright 2013 Samsung Electronics
+ * Przemyslaw Marczak <p.marczak@samsung.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+*/
+
+#ifndef __TIZEN_LOGO_16BPP_GZIP__
+#define __TIZEN_LOGO_16BPP_GZIP__
+
+/* Format: GZIP: BMP RGB565 16BPP 452x140 */
+unsigned char tizen_logo_16bpp_gzip[] = {
+0x1f,0x8b,0x08,0x08,0xd9,0x76,0x29,0x53,0x00,0x03,0x74,0x69,0x7a,0x65,0x6e,0x5f,
+0x6c,0x6f,0x67,0x6f,0x2e,0x62,0x6d,0x70,0x00,0xed,0x9d,0x6f,0x6c,0x1b,0x67,0x7e,
+0xe7,0xa9,0x4d,0x80,0x65,0xbb,0x2e,0x56,0xb1,0xd8,0x25,0xcf,0x0a,0x70,0x52,0xa4,
+0x2d,0xc2,0x5a,0x39,0x58,0x35,0xf7,0x42,0x35,0x7a,0x63,0xd5,0x6a,0x1b,0x9d,0x5c,
+0xd4,0x0a,0x85,0xca,0xde,0x35,0x70,0x1b,0xc7,0x29,0xbc,0xaa,0xbb,0x50,0x14,0x0a,
+0xd6,0x79,0xdf,0x9c,0x2b,0x07,0x88,0xa1,0xb8,0x88,0x4a,0x11,0x2b,0x83,0x7a,0x71,
+0xc9,0xd2,0x6e,0x1d,0x4c,0x76,0xa1,0x60,0x28,0x44,0xc5,0xe8,0x8d,0x6b,0xba,0xbd,
+0x14,0xca,0x56,0xba,0x0e,0x51,0x05,0x70,0x0b,0x24,0xa8,0x83,0x7a,0xef,0x5c,0x54,
+0x77,0x61,0x6a,0xbf,0xb9,0x79,0xe6,0x99,0xe7,0x79,0x7e,0xf3,0x87,0x9c,0x67,0x86,
+0xc3,0x7f,0xca,0xf3,0x7d,0x30,0x1a,0x92,0xe2,0x9f,0x21,0x39,0x1f,0x7e,0x7f,0xcf,
+0xbf,0xdf,0x33,0x72,0xe2,0xc6,0xff,0xe9,0x08,0x21,0xfd,0xb6,0xb6,0x25,0xb5,0xed,
+0xaf,0xb4,0xab,0x8b,0xda,0xbe,0x23,0xd4,0x19,0x7a,0x42,0xdb,0xff,0x57,0xed,0xff,
+0x1d,0xfa,0x75,0xa0,0x2f,0x43,0xa1,0x7f,0xfa,0x7a,0x28,0xf4,0x1f,0x43,0x42,0x42,
+0x42,0x42,0x42,0x42,0x42,0x42,0x42,0x5f,0x3d,0xf5,0x86,0xdf,0x18,0x3c,0x17,0x3f,
+0x16,0x6e,0xf6,0x71,0x08,0x09,0xb5,0x8a,0x7a,0xc3,0x3d,0xa1,0x1e,0xb4,0x91,0x42,
+0x2f,0xf7,0x6a,0x5b,0x3d,0x74,0x6b,0x22,0x91,0x2f,0xc8,0x59,0x39,0x91,0xdf,0xce,
+0x3c,0xbc,0xf4,0xe0,0x74,0x78,0xe4,0xc9,0xde,0xba,0xbc,0x50,0xcb,0xab,0xa7,0x6e,
+0xcf,0xfc,0xfd,0xf0,0x1f,0x4f,0xcf,0x2c,0x9e,0xd4,0xcb,0x8c,0xbe,0xcd,0x2c,0xce,
+0xd0,0x6b,0x27,0x8d,0x6b,0x57,0x27,0xfc,0x3e,0xff,0xb3,0x23,0x9d,0x0b,0x6b,0x99,
+0xb5,0xcc,0xb6,0xb1,0x59,0xcb,0x76,0x95,0x6b,0xe8,0xfa,0x36,0x78,0xac,0x76,0x2d,
+0x67,0x5c,0xce,0x6d,0xeb,0xff,0xfb,0x80,0x6e,0x7b,0x39,0x52,0x96,0x32,0xe1,0x11,
+0xde,0xa3,0xfb,0x34,0x76,0x64,0x81,0x3d,0x92,0xbf,0x44,0xf2,0x55,0xcb,0x6a,0x85,
+0xcb,0x0e,0xd7,0x13,0xf9,0x23,0x0b,0x2f,0x77,0xf2,0x1d,0x6d,0x6f,0xb8,0x73,0x21,
+0x91,0x77,0x2b,0x47,0x16,0x79,0x9f,0x8f,0x4f,0xf7,0x87,0x22,0x1a,0x85,0xb8,0xa8,
+0x5a,0x41,0xfb,0xb4,0xd4,0xb5,0xfa,0x5a,0xe6,0xda,0xec,0xd5,0x89,0x1b,0x83,0xef,
+0x04,0xfa,0x6a,0xcd,0x54,0x78,0x64,0x2d,0xe3,0xf6,0xad,0xef,0xe5,0x06,0xa6,0xeb,
+0xf1,0xda,0x4b,0x99,0x92,0xa2,0xca,0x25,0xb9,0xa4,0xa0,0x0d,0x7d,0xce,0xf8,0x92,
+0x7e,0xab,0xa2,0x2a,0x25,0xa3,0xbc,0x77,0xda,0xcf,0xb3,0x3f,0xbc,0x84,0x9f,0x8b,
+0xb7,0x94,0xc1,0x9e,0x6f,0x2b,0x3b,0xdc,0x56,0x90,0xef,0x0e,0xf1,0x1d,0xdf,0x4e,
+0xce,0xe9,0xf1,0x7c,0x5b,0x50,0xa5,0xac,0x9c,0x5c,0xe4,0x3b,0xda,0x23,0x0b,0xf0,
+0x75,0xf5,0xef,0xc7,0xf8,0x74,0xf5,0xef,0x49,0xff,0xbe,0x54,0x0f,0xcf,0xc7,0xa3,
+0xdb,0xb1,0xa5,0x0c,0xe3,0x10,0x16,0xd5,0xa0,0x72,0x32,0xbf,0x93,0x3b,0xb2,0x30,
+0x70,0xf6,0x59,0xee,0x5f,0xbf,0xd6,0xd4,0xed,0xd8,0xa4,0xe4,0xf4,0x3e,0xed,0xc5,
+0xbf,0x2b,0x55,0xd2,0xb9,0x41,0xbe,0x57,0x2e,0x29,0x4b,0x19,0xef,0xcf,0x3e,0x70,
+0xb6,0xa4,0xb0,0x6f,0xad,0x60,0xfc,0x96,0xb2,0xcb,0xf0,0x36,0xf2,0xbd,0xaa,0xf4,
+0xfb,0x55,0x4d,0xb7,0xb2,0xfb,0x94,0xd0,0x5f,0x05,0xef,0xf5,0x5f,0x0e,0x6d,0x2b,
+0x68,0xdb,0xba,0x76,0x7d,0x5d,0xbf,0xbd,0xac,0xbc,0x3f,0xcb,0x73,0x7c,0xa3,0xf1,
+0x2c,0xfd,0xed,0xc1,0xdb,0x3a,0xd9,0xcb,0x78,0xa3,0xcf,0x4d,0x36,0x19,0x5f,0x2f,
+0x81,0x6d,0x5d,0x66,0x8f,0x55,0xe1,0xfd,0x8c,0xe3,0xc6,0xc7,0x8b,0xf6,0xf6,0xf7,
+0x58,0xd0,0x1f,0x9b,0xca,0xf3,0x7d,0x9e,0x89,0x3c,0x7a,0x1d,0xf8,0x99,0x39,0x7f,
+0x57,0x93,0x52,0x70,0x8e,0xd8,0xa9,0xc7,0x0b,0xd9,0x0a,0xaf,0x95,0xa5,0xdf,0x27,
+0xfa,0xfb,0xb6,0x8f,0x73,0xa4,0x75,0xf4,0xe2,0x18,0x7a,0x3f,0xee,0x45,0x95,0x3b,
+0x17,0x82,0x7e,0xed,0x1b,0x9c,0x1c,0xaa,0xca,0x9a,0xe7,0xcf,0xb8,0x37,0x9c,0x92,
+0x54,0xa5,0x60,0xfa,0xa6,0xcc,0x44,0x15,0xc0,0xf5,0x02,0xbd,0x8e,0xcf,0x5a,0x72,
+0x26,0xaf,0x93,0x47,0x29,0x6c,0x4f,0xa8,0xa0,0x44,0x2a,0x2a,0xf5,0xf3,0x92,0xee,
+0x08,0x1f,0x5f,0xe2,0x39,0xc2,0x73,0xf1,0x02,0x79,0x1c,0xfa,0xab,0x3f,0x5b,0x89,
+0xdd,0xa2,0x58,0x63,0x03,0xc3,0x7d,0x0c,0xdf,0xa1,0xf1,0x83,0xce,0x52,0xc1,0xb8,
+0xbd,0x80,0x9f,0x49,0xbf,0x5f,0x41,0x66,0xc7,0x49,0x7e,0x25,0x54,0x40,0xb8,0x4e,
+0x39,0xe2,0x50,0xe2,0x69,0x01,0xe9,0xd5,0x39,0x2c,0x58,0x3e,0x2f,0xfb,0x86,0x38,
+0x0c,0x2a,0x56,0x3c,0x31,0x1d,0xd1,0xdc,0xae,0x32,0x87,0xd6,0x5f,0x00,0xbe,0xdf,
+0xbf,0xd6,0x14,0x2f,0x87,0x85,0x26,0x72,0x58,0xf2,0xc1,0xe1,0x89,0x69,0x78,0xd6,
+0x58,0xb8,0x06,0x1b,0xe4,0x52,0x2f,0xc6,0x99,0x5b,0x50,0x0a,0x94,0x34,0xea,0x75,
+0xc6,0x46,0x3c,0x09,0xfa,0x55,0x81,0x9e,0xe5,0xde,0x38,0x34,0xe2,0x6f,0xd9,0x20,
+0x8f,0xb2,0x57,0x32,0x6e,0x03,0xa4,0x1a,0x2c,0xaa,0xc6,0x2b,0x31,0x12,0xf5,0x7b,
+0x62,0x5f,0x54,0x0a,0x32,0x38,0x46,0xe2,0xd9,0x32,0xfb,0xf5,0x20,0xbf,0x40,0xeb,
+0x94,0x61,0x3e,0x6e,0x7a,0x28,0x87,0x4e,0xf4,0x81,0xef,0x4a,0x9e,0x94,0x2e,0x07,
+0xc2,0xe1,0xf9,0x31,0x54,0x1f,0xda,0xce,0xec,0x70,0x71,0x88,0xee,0xb3,0x97,0x0b,
+0xe2,0x75,0x9b,0x23,0x7e,0x0e,0x8f,0xb4,0x11,0x87,0xc7,0xc2,0x93,0x12,0x8e,0xa2,
+0x2a,0x9c,0x39,0xc4,0x27,0x88,0xaf,0x81,0xdb,0x69,0xf4,0xa7,0x9f,0xdf,0xd4,0xf3,
+0x0c,0xa7,0x61,0x6c,0x58,0x58,0x91,0x49,0x6d,0xc9,0x23,0x87,0xc4,0xf9,0x14,0xfc,
+0xec,0xd8,0x05,0x55,0x40,0x3a,0x7d,0x0d,0x52,0x13,0x23,0xff,0x97,0x49,0xbd,0x8c,
+0x1d,0x19,0x39,0x06,0x7a,0x8c,0x94,0x57,0xf2,0x78,0x95,0x1e,0xad,0xf1,0x1e,0x3d,
+0x73,0x68,0xfd,0x35,0x2b,0xc0,0xcf,0x4f,0xe7,0x30,0x08,0x3f,0x1c,0x8d,0xef,0xe5,
+0xba,0x56,0x77,0xb8,0x39,0x2c,0x7c,0x65,0x38,0x6c,0x27,0x3f,0xbc,0x30,0x6d,0xae,
+0xcb,0xa8,0xc0,0xf3,0xac,0xd1,0x28,0xa8,0x05,0x5a,0x3c,0x4f,0x05,0x5e,0x42,0x23,
+0x52,0x19,0x47,0x7f,0xb8,0x2e,0xe6,0xc4,0xa6,0xc7,0xb8,0x14,0x50,0xa3,0x2a,0x86,
+0x37,0xca,0x46,0x9c,0x6a,0x6e,0xbf,0xa2,0x7c,0x12,0x9e,0xf0,0xfd,0x08,0x6d,0xc6,
+0xa3,0x21,0xcb,0x20,0x8a,0x55,0x8d,0xcf,0x83,0x44,0xa9,0x2a,0x8d,0xaa,0xf9,0xfc,
+0x8b,0x70,0xc8,0x3e,0x45,0xf3,0x67,0x48,0x2e,0xab,0x9c,0xcf,0xe7,0xa6,0x99,0xc5,
+0x84,0xe6,0x86,0x3b,0x39,0xd4,0x3e,0x2d,0x38,0x6c,0x4f,0x0e,0xbf,0x8f,0xdc,0xd0,
+0xc6,0x20,0xdb,0xb3,0x96,0x0d,0xd8,0x1a,0x42,0xda,0x33,0x8c,0xf3,0x96,0x9e,0xfb,
+0xcc,0x8b,0x54,0x7a,0x4e,0x97,0x98,0x6b,0x11,0xa7,0xa1,0x35,0x3b,0x9f,0x1c,0x12,
+0x16,0xc1,0x56,0xa2,0x64,0x99,0xdc,0x10,0xb4,0x23,0xc3,0xc7,0xc1,0xa3,0x31,0xdc,
+0x19,0xd7,0x39,0x49,0x24,0xab,0x50,0x07,0x35,0xf6,0xf8,0x79,0xbc,0xf9,0xa1,0xf9,
+0x73,0x34,0xd7,0xb8,0x75,0x3f,0x0c,0x84,0xc3,0x8f,0x2f,0x4d,0xea,0xad,0xf4,0x82,
+0xc3,0xd6,0xe2,0x70,0xdb,0x13,0x87,0xd7,0x66,0xcb,0x0a,0xf4,0x3a,0xab,0x17,0x92,
+0x36,0x46,0xd8,0x4e,0x49,0xfc,0xae,0x24,0x97,0x40,0xc4,0xa7,0x12,0xc6,0x98,0xc3,
+0x18,0x11,0xa1,0xca,0xce,0x65,0xc3,0xa1,0x08,0x45,0x5e,0x39,0x84,0x54,0xa9,0x80,
+0x2c,0x6b,0x31,0x51,0xc8,0xda,0x70,0xd8,0xaf,0x00,0xe5,0x0e,0x1e,0x11,0xf5,0x4e,
+0x56,0x97,0x34,0x7e,0x61,0x0c,0x36,0x3d,0xf9,0x21,0x63,0x0f,0xfe,0xba,0xc1,0x88,
+0x3f,0x08,0x3f,0x7c,0x70,0x3a,0x25,0x25,0xf2,0x5d,0xab,0x98,0xc3,0x35,0x4e,0x0e,
+0xd5,0x7d,0xcf,0x61,0xa1,0xc9,0xed,0xa5,0xde,0xfc,0xf0,0x72,0x67,0x5a,0x22,0x67,
+0x0c,0xa5,0x4d,0x86,0xed,0x85,0x98,0x34,0xdc,0xd2,0xcf,0xda,0x32,0x48,0xdb,0x24,
+0x3b,0x63,0x59,0x1d,0x50,0xa5,0x64,0x98,0x48,0x01,0xad,0x2a,0xcc,0xb7,0x6a,0xf4,
+0x43,0x1b,0x7f,0xe6,0xdb,0x19,0x67,0x96,0x63,0x00,0xcf,0xa5,0x5a,0x8f,0x55,0x29,
+0xd9,0x8e,0xd5,0xb8,0xcd,0x63,0xfd,0xd0,0xda,0x43,0xa2,0x7f,0x3b,0xa6,0x68,0xa3,
+0xf6,0x76,0x9a,0xbb,0x43,0x89,0x7c,0x2a,0x9f,0xa0,0x7e,0xc8,0xcb,0x61,0x7b,0xfb,
+0xe1,0xd5,0x09,0x5e,0x3f,0x7c,0xc8,0x75,0x76,0x79,0x51,0x7d,0x38,0xbc,0x36,0x8b,
+0xb9,0x2a,0x18,0xd4,0x19,0xf1,0x92,0x51,0xff,0xb3,0xb6,0x1d,0xae,0xb3,0x5e,0x68,
+0x76,0xb6,0xb3,0x56,0x0d,0xd0,0x3e,0x69,0x44,0x9e,0x84,0x4f,0xd9,0x74,0xe6,0x03,
+0x42,0xfc,0x70,0x68,0x25,0xc6,0xec,0xc7,0x16,0x12,0x65,0x48,0x3d,0xb8,0x6e,0xa5,
+0xd3,0x46,0xa1,0x29,0xa6,0xa6,0x71,0x6c,0x9a,0x93,0xc3,0x54,0xbe,0x04,0xe8,0x5b,
+0x97,0x59,0xc4,0x51,0x00,0xfb,0x5a,0xe3,0xd2,0xcb,0x9d,0x7b,0xb9,0x49,0x09,0x51,
+0xa8,0xfb,0x61,0x66,0xe9,0x2b,0xc2,0xe1,0xff,0x3c,0x5d,0x9d,0xc3,0x42,0x93,0xfc,
+0x10,0x7e,0xbb,0x5e,0xe2,0x52,0xec,0x86,0x05,0xe3,0x3c,0x83,0x3d,0xdb,0xb4,0x35,
+0x12,0x9e,0xa5,0xe4,0xfc,0x04,0x8e,0xc7,0x28,0xb3,0xb5,0x40,0x5a,0xcf,0x6c,0x0b,
+0x45,0x35,0xfb,0x61,0x1d,0x8a,0xaa,0x98,0x7f,0x25,0xec,0x85,0x97,0x43,0xe2,0x87,
+0x24,0x82,0xa0,0xd1,0xbc,0x4c,0xda,0x9c,0x09,0x87,0xb5,0xb4,0x97,0x9e,0x5c,0x4c,
+0x4b,0x88,0x43,0x1c,0x97,0x6e,0x7b,0x8a,0x4b,0xbb,0x56,0xfd,0xbf,0x6e,0xb3,0xf5,
+0x5e,0x55,0x0e,0x0b,0x74,0x5f,0x90,0xbf,0xf9,0xa3,0xa0,0x5f,0xdb,0xdd,0x0f,0xb1,
+0xab,0x79,0xe1,0xf0,0x7d,0xad,0x6e,0xb8,0x0e,0xbc,0x8f,0x9c,0x39,0x46,0x5b,0xa1,
+0xa2,0xd2,0x68,0xd4,0x54,0x2f,0x93,0xa9,0x5b,0xb0,0x33,0xd7,0x4a,0x1a,0x69,0x3d,
+0x91,0xab,0xd0,0xd9,0x0a,0x1c,0x5a,0xa2,0x5b,0xeb,0x31,0x93,0xf7,0x46,0xae,0xa7,
+0xf9,0xea,0x87,0x61,0x5c,0x3f,0xa4,0x7d,0xaa,0xa0,0x5f,0x15,0xb7,0x2d,0x17,0xf4,
+0x31,0x3b,0xe8,0xf9,0x6e,0xc7,0x78,0xbf,0x2d,0xab,0x2e,0x4c,0x67,0xb5,0xb8,0x76,
+0x32,0x4f,0x39,0xf4,0xe0,0x87,0xed,0x5d,0x3f,0x74,0xe2,0xb0,0x60,0xdb,0x50,0x69,
+0x8e,0x1f,0xe2,0xdf,0x58,0xde,0xb8,0xf4,0x76,0x0c,0xd7,0x0d,0x8d,0xd6,0x4d,0x19,
+0xb4,0x62,0xd0,0x36,0xff,0x12,0xad,0xf1,0x39,0xd6,0xc5,0xc8,0x59,0xea,0xe0,0x2b,
+0x7c,0xa5,0xe9,0x1c,0x7a,0x2c,0x5e,0xe2,0x52,0xd6,0xe2,0xca,0xfa,0x38,0x69,0x0b,
+0x17,0xee,0xc9,0x51,0xe6,0x24,0xbf,0xf3,0x21,0xce,0x8f,0xcd,0x49,0xc8,0x0d,0x53,
+0x12,0xae,0x1d,0xee,0x69,0x6e,0xc8,0xcf,0x61,0x49,0xd9,0x6f,0x1c,0x5a,0xbd,0x30,
+0xab,0x73,0xd1,0x68,0x3f,0x54,0x65,0x56,0xe7,0xe0,0xe5,0x10,0xb9,0x21,0x1b,0x73,
+0x09,0xfb,0xcc,0x20,0x49,0x74,0x0c,0x8b,0x51,0xfb,0x2b,0x99,0xfa,0xba,0x2d,0xf1,
+0xa9,0x29,0xaa,0xe3,0xa1,0xb1,0xe5,0x39,0x84,0xad,0x35,0x32,0xaf,0x1f,0xf6,0x62,
+0x0e,0xe9,0xc8,0x1f,0x93,0x27,0x1a,0xf1,0x07,0xfe,0x0c,0xd3,0xd2,0x67,0x3d,0x7c,
+0xdf,0x96,0x59,0x4f,0xf6,0x26,0xf2,0x59,0x9d,0xc3,0xef,0x48,0xac,0x95,0xc6,0x4b,
+0xfd,0x30,0xc2,0x39,0x52,0xb6,0x15,0xf5,0x9e,0xa5,0x9d,0xc6,0xd9,0x0b,0xeb,0xe7,
+0x87,0xc4,0xf7,0xac,0x7b,0xf3,0x2f,0xdd,0x0e,0xd7,0x2f,0x1d,0x71,0x43,0x58,0xd7,
+0xb3,0x78,0x9b,0xd9,0x03,0x2d,0x67,0xa4,0x63,0x3b,0xa3,0xe7,0x52,0x56,0xf8,0x5a,
+0xb4,0x5a,0xc3,0x0f,0xcb,0x1a,0x37,0xef,0x72,0xc4,0x91,0x5a,0xfd,0x50,0x2a,0xd1,
+0x7e,0x49,0xf6,0x39,0x19,0x7d,0x22,0x60,0xdc,0xcf,0x9c,0xec,0xcf,0x0f,0xd7,0x32,
+0x05,0x99,0xf9,0x61,0x42,0xf7,0x43,0x2f,0x71,0x69,0x41,0x4e,0xe4,0x7b,0xfc,0xbc,
+0x70,0x4b,0xc8,0xd9,0x0f,0x9d,0x48,0xec,0x0c,0xdc,0x0f,0x6f,0x52,0x3f,0x84,0xf4,
+0x59,0x2f,0xf3,0xd7,0x0f,0x51,0xbf,0xe1,0x3a,0xec,0x83,0x07,0xa3,0xd1,0x60,0xed,
+0xcf,0x5c,0x3f,0x82,0x6d,0x8f,0x41,0x94,0xe8,0xe6,0x09,0xae,0x39,0x62,0x88,0xc3,
+0x72,0x0b,0x70,0xc8,0x37,0xdf,0xa2,0x37,0x4c,0xfc,0x90,0x7d,0x7a,0x60,0x94,0x9c,
+0xc2,0xc6,0xab,0xa6,0x7d,0xc5,0xa5,0x1f,0x5f,0x42,0xe7,0x5a,0xda,0x14,0x97,0xee,
+0x78,0xac,0x1f,0xb6,0x3b,0x87,0x05,0x1b,0x7d,0x05,0x8b,0x17,0xa2,0x77,0xf9,0xaf,
+0x75,0xe9,0xb7,0x70,0xf2,0x3f,0xeb,0x58,0x8d,0xb2,0xb2,0xcd,0xe5,0x87,0xdb,0xb9,
+0x32,0xed,0x4f,0xb0,0xf5,0xb3,0x55,0x39,0x13,0x83,0x2c,0xd1,0xcd,0xc8,0xea,0xcb,
+0x5c,0x19,0x1c,0x5e,0xe5,0xf6,0xc3,0x60,0x8f,0xd0,0x5c,0x0a,0x32,0xef,0xdc,0xce,
+0x44,0xbe,0x6c,0xf9,0x4c,0x61,0x9c,0x41,0x3f,0x73,0x5f,0x7e,0xf8,0x91,0xe1,0x06,
+0x69,0x19,0x71,0x38,0x69,0x8a,0x4b,0x97,0x32,0x59,0xc7,0xb3,0xc4,0x56,0x94,0x76,
+0xe7,0xd0,0xdd,0x0b,0x11,0x1b,0x7c,0xb5,0x1e,0x2f,0xba,0x31,0xe8,0x14,0x95,0xb2,
+0x8d,0x5c,0xe2,0xf5,0xc3,0x87,0x7f,0x52,0xb6,0xcd,0xb1,0xa8,0xd6,0x27,0x33,0xa7,
+0x6d,0x7b,0xb9,0x81,0xb3,0x03,0xd3,0x27,0xa6,0x9f,0xab,0xb0,0x9d,0x70,0xd8,0x57,
+0xba,0xed,0xc4,0xf4,0x81,0xb3,0xfc,0xb3,0x34,0xf9,0xfc,0x10,0xc5,0x8d,0x07,0xce,
+0x7e,0x74,0xfa,0x81,0xa5,0xa0,0x5b,0x6e,0x4d,0xfc,0x60,0xec,0xea,0xc4,0xf9,0x89,
+0xab,0xda,0x5f,0x74,0x09,0x97,0x1f,0x4c,0xbc,0xa9,0x5f,0x46,0xb7,0xbc,0xa9,0x5d,
+0xfb,0x01,0xbe,0x4d,0xbf,0x55,0xdb,0xf4,0xff,0xbd,0x89,0x1e,0x83,0x1e,0x3b,0xd6,
+0xcf,0xcd,0x8c,0xc1,0xa1,0x62,0x89,0x1e,0x64,0x3a,0xc6,0xdd,0x88,0x4c,0x97,0x3d,
+0xfb,0xe1,0x8d,0xc1,0x65,0xc9,0xe0,0x50,0x22,0x1c,0xa2,0xf6,0x52,0x8f,0x1c,0xb6,
+0xb5,0x1f,0x7e,0x34,0x41,0xbc,0xcf,0x4a,0x9e,0xd5,0xa3,0xea,0xc0,0xe1,0x90,0x99,
+0x3a,0x73,0x44,0x4a,0x7a,0xe1,0xd1,0xb9,0xc8,0x57,0x3f,0x44,0xf3,0xfb,0x55,0x13,
+0x67,0x73,0xd2,0xb2,0x94,0x06,0x65,0xd2,0xf8,0x9e,0x61,0x09,0x7e,0x7e,0x33,0x9f,
+0x46,0x39,0x39,0x4c,0xb4,0x48,0xeb,0x03,0xf3,0x43,0xd3,0xe8,0x02,0xd9,0xda,0xf7,
+0x9a,0xf5,0xe8,0x87,0xc7,0xc2,0x11,0x7d,0xe4,0xaa,0xfe,0x8d,0x99,0x38,0xdc,0xd3,
+0x7b,0x0f,0x97,0xf4,0xb8,0xd4,0x9d,0xc4,0xf5,0x36,0xf7,0x43,0xd5,0xb1,0x75,0xc6,
+0x4a,0xa4,0xca,0xd9,0x0a,0xe8,0x45,0xb8,0x7e,0xc8,0x3e,0x61,0xf3,0xa8,0x61,0x83,
+0x45,0xc5,0x4b,0x3f,0xfe,0xb1,0xf0,0x5e,0xce,0xec,0x81,0x69,0x0b,0x89,0x8c,0x46,
+0x46,0xe4,0x8b,0x63,0x41,0xbf,0x33,0x1e,0x3d,0xd9,0x9b,0x6d,0x2b,0x0e,0x23,0x79,
+0x76,0xb4,0xd6,0x96,0x2d,0x32,0xfb,0x0a,0xed,0xb3,0x1e,0xfd,0xf0,0xe4,0x22,0xa1,
+0x30,0x2b,0x2f,0x83,0xb8,0x14,0xcf,0x7a,0x5a,0x32,0x38,0x74,0x2f,0xed,0x5d,0x3f,
+0xfc,0xe8,0x34,0xf4,0xc3,0x6a,0xef,0xb2,0x5e,0x71,0x29,0x8b,0x41,0x01,0x83,0xa6,
+0x11,0x68,0x65,0x0f,0xfd,0xf8,0x9f,0xc5,0x70,0x76,0xaf,0x2c,0xfd,0x66,0x71,0xb4,
+0x63,0x2f,0x84,0xc4,0xb4,0x94,0xca,0xf3,0x66,0x94,0x09,0x52,0x98,0xc3,0xb2,0xe2,
+0x96,0x8b,0xa6,0x55,0x38,0x4c,0x00,0x0e,0x61,0xad,0xd0,0x5a,0xbc,0xf9,0xe1,0x05,
+0x3a,0x5f,0x9b,0xfc,0x6e,0x42,0x3f,0xdc,0xc9,0x79,0xe0,0xb0,0xcd,0xfd,0xb0,0xba,
+0x0f,0x32,0xd7,0xaf,0x83,0x1f,0x0e,0x59,0x3d,0x90,0x5d,0x26,0x7d,0x52,0x38,0x32,
+0xe5,0x8d,0x4b,0x91,0xde,0x88,0x4f,0x4a,0x94,0x44,0x69,0x4e,0x23,0x71,0xce,0x95,
+0xc4,0x48,0x7e,0x34,0x1e,0xf4,0xbb,0x73,0x53,0xbb,0xf9,0xa1,0x89,0x43,0xa7,0x51,
+0xef,0xc6,0x75,0x2f,0x1c,0x3e,0x3b,0x42,0xe2,0x21,0xf2,0x7d,0xd9,0xfd,0x90,0xb4,
+0x97,0xba,0x45,0xa6,0xed,0xee,0x87,0xaa,0xab,0x17,0xa2,0x52,0xaa,0x93,0x1f,0xda,
+0x0b,0xf4,0x42,0x3c,0x62,0x9b,0xbf,0x7e,0x88,0x15,0x1e,0x49,0x4b,0xd0,0x13,0xd3,
+0x5a,0xd1,0xa2,0xd3,0x0a,0x34,0xa2,0x32,0x27,0xed,0xe5,0x1a,0x9d,0x81,0xaf,0xdd,
+0xfc,0x30,0x62,0xf7,0x43,0x4b,0x51,0x3d,0xfa,0x21,0xca,0x51,0xc6,0xe6,0xf8,0x5b,
+0xeb,0x87,0x11,0x54,0x3f,0x34,0xfc,0xb0,0x04,0xe6,0xb1,0x15,0x4c,0xfb,0xfd,0xe3,
+0x87,0x2a,0x47,0x54,0x5a,0x9f,0xb8,0xf4,0xe6,0x20,0x1b,0xf3,0xa2,0xca,0x6c,0x4e,
+0x04,0x99,0x49,0x63,0xf4,0x04,0x7a,0xe6,0x10,0xcd,0x22,0xc9,0xb2,0xdf,0x58,0x19,
+0x79,0xa2,0xe6,0x8c,0xd2,0x5c,0x45,0x0e,0xd3,0x52,0x56,0xf6,0x93,0x13,0xae,0x16,
+0x11,0x3f,0xac,0xbe,0xb5,0x0e,0x87,0x0e,0x71,0xa9,0xd9,0x0b,0x8d,0x1e,0x7e,0x7e,
+0x0e,0xd7,0x32,0x6c,0x9e,0x28,0xeb,0xb7,0xd0,0x7b,0x10,0x8d,0xf6,0xd2,0x6d,0x4b,
+0x7b,0x69,0x65,0x0a,0xd1,0xd9,0xd3,0xce,0x1c,0x62,0x3f,0x74,0x2f,0xa5,0x3a,0xc4,
+0xa5,0x37,0x06,0xc9,0xa8,0xe3,0x02,0xd8,0xc8,0xa8,0x6b,0x95,0xfc,0xc6,0xfa,0xe0,
+0x30,0x14,0x3a,0x70,0x16,0x44,0x3b,0xa0,0xae,0xa8,0x45,0x3e,0xda,0xaf,0xae,0x5e,
+0x67,0x94,0x97,0x2d,0x24,0x9e,0x0c,0x7c,0xc4,0x50,0x35,0x3d,0xd9,0x5b,0x90,0x79,
+0x7a,0xf8,0x5a,0x9e,0x43,0x9f,0xf5,0xc3,0x8f,0x2f,0x95,0xf5,0x39,0xa0,0x25,0x53,
+0x64,0x8a,0xfd,0x90,0xce,0x3f,0x34,0x38,0x24,0x23,0xf5,0x59,0x5f,0x96,0xfd,0xac,
+0x2d,0xed,0x0b,0x3f,0x74,0x2b,0x75,0x69,0x2f,0x1d,0x22,0xb3,0x93,0x58,0xdf,0x7d,
+0x09,0x90,0xb8,0x6e,0xfc,0xca,0x6a,0x1c,0xfa,0xf0,0xaa,0x6b,0xd3,0x15,0x7a,0x0f,
+0x25,0x1c,0x01,0x2d,0xeb,0xf1,0x2a,0x6e,0xa3,0x4b,0xeb,0x51,0x6b,0xb6,0x0e,0x9e,
+0x5f,0x59,0x24,0x2e,0xb5,0xfa,0x5f,0xdb,0xf9,0xa1,0xc5,0x1b,0xf9,0x38,0xbc,0x35,
+0x51,0x02,0xd1,0x26,0xe5,0xd0,0xd2,0x6f,0xc1,0xfc,0x90,0xdd,0xaf,0x12,0x89,0x88,
+0xc3,0xf6,0x5d,0x03,0x03,0xb7,0x97,0x36,0x87,0x43,0xec,0x87,0xa4,0x55,0xc6,0x9a,
+0x7f,0x8c,0xd5,0xfd,0xfd,0xf8,0x21,0xd2,0xc3,0x4b,0xaa,0xcd,0x13,0xdd,0x0a,0xdf,
+0x98,0xb4,0x20,0xc4,0x38,0xdc,0x4f,0x7e,0x58,0xe6,0xe2,0x70,0x34,0xbe,0x2c,0x91,
+0x59,0x54,0xeb,0x0e,0xed,0xa5,0x6c,0x3e,0x3e,0x6e,0xa7,0x51,0x8d,0xd9,0xc7,0xac,
+0x3f,0xab,0x60,0x21,0xb3,0x10,0x58,0x86,0xaa,0xe6,0xe8,0xbd,0x26,0x72,0x78,0x77,
+0xa8,0xa4,0x90,0xb9,0xf1,0xfa,0xa7,0x4b,0x32,0x31,0x19,0x3c,0x92,0x99,0x72,0x5e,
+0xfa,0x2d,0xcc,0x82,0x7d,0x53,0xbc,0xc5,0x5f,0x0e,0x7f,0xef,0xda,0x9f,0x1c,0xf2,
+0xf9,0xe1,0x5e,0xae,0x44,0x5b,0xe1,0xa0,0x23,0x2e,0x1b,0xf5,0x43,0xd6,0x6f,0xb1,
+0x46,0x39,0x84,0xfe,0xa7,0x82,0x3d,0xbb,0xdc,0xce,0x1c,0x6a,0x7e,0x58,0x31,0xdf,
+0xae,0xd9,0xf5,0x83,0xe7,0x30,0x3c,0x52,0x06,0xf5,0x7b,0xcb,0xdc,0x5b,0x30,0x6e,
+0xc3,0xaf,0x1f,0x22,0xad,0x65,0x2a,0xe5,0x13,0xce,0x56,0xdc,0x1a,0xb3,0x56,0x02,
+0x1f,0x87,0xd1,0xcd,0x76,0xe3,0xb0,0x20,0x9f,0x73,0xe9,0x03,0xea,0x5c,0x28,0x93,
+0x3c,0x40,0xfa,0x77,0xec,0xe0,0x87,0x92,0x39,0x3f,0x0d,0x9d,0xe7,0xa8,0xc7,0x4d,
+0xe6,0xe8,0x94,0xd5,0x68,0x82,0xcb,0x24,0xde,0x78,0x35,0xb3,0x9d,0xe6,0xf3,0x63,
+0x65,0x45,0xa5,0x7d,0x84,0xd0,0x0d,0xcd,0x33,0x77,0xfd,0xd5,0x0f,0xb1,0x8e,0x85,
+0xbb,0x56,0x2b,0x67,0xf6,0x76,0x2e,0x69,0xe9,0x66,0x03,0xfa,0xf5,0xf7,0xab,0x1f,
+0xba,0x71,0xf8,0x8b,0x97,0xf5,0xef,0x83,0xcd,0xda,0x00,0xbf,0x8c,0x59,0x09,0xf8,
+0x61,0x9e,0xf5,0xe3,0xab,0x8a,0xd5,0xfb,0xec,0xfe,0x18,0x4c,0xc6,0xc6,0x66,0xe9,
+0xa3,0xd3,0xeb,0x7c,0x1c,0xd6,0xa1,0x0d,0x43,0xf7,0x43,0x3d,0x1e,0x65,0xe3,0xf5,
+0xa1,0x3b,0xb2,0x3a,0x87,0x7f,0x3f,0x44,0xe7,0x7b,0x2a,0x0f,0xbf,0x6d,0xf7,0x82,
+0x6a,0x1a,0xdf,0xae,0xfb,0x1a,0x7b,0xfd,0xfb,0xd2,0x0f,0xcb,0x2e,0x1c,0xde,0x1d,
+0xca,0x1a,0xd4,0xd0,0xb9,0xda,0xa6,0x1e,0x44,0x36,0xd2,0x9b,0xcd,0xb8,0x30,0xfc,
+0xd0,0xe8,0xd5,0x2a,0x80,0x36,0x56,0xc2,0x60,0xc1,0xf0,0xc3,0x76,0xe6,0xb0,0xb9,
+0x7e,0x68,0xd4,0x11,0x2a,0xcf,0xdc,0xad,0xa1,0x9d,0x86,0xe8,0xc6,0x60,0x5a,0x32,
+0xaf,0xcd,0xe0,0x48,0x9f,0xe9,0xdd,0x46,0xf2,0xc1,0xae,0xe3,0x67,0x17,0x5f,0xbf,
+0x45,0xbb,0x71,0x58,0xdd,0x0f,0xf5,0x31,0xdd,0xc6,0xef,0x3a,0xf1,0x42,0xc6,0x14,
+0xe3,0x90,0xb4,0xd3,0xa0,0xf5,0x26,0xdf,0x5e,0x9c,0x93,0xf0,0x4c,0x63,0xdc,0xcb,
+0x51,0xa0,0xbd,0x18,0x05,0xd3,0x5f,0x35,0xa0,0x8c,0xfe,0xcd,0xd1,0x47,0xa7,0x4b,
+0x4d,0xe3,0x10,0xd7,0x0f,0x4b,0xf6,0xb9,0xf0,0x81,0xfa,0x21,0x52,0x7c,0xac,0x40,
+0xda,0x61,0x61,0xcf,0x88,0xac,0x82,0xd7,0x53,0x69,0x24,0x8c,0x57,0x8b,0xa9,0xf5,
+0x35,0xdd,0xd4,0x9e,0x1c,0x5a,0x37,0x6f,0x7e,0x88,0xdb,0xcd,0x90,0xa7,0xb1,0x56,
+0x80,0x6a,0x1c,0x22,0x3f,0x7c,0xef,0xb4,0x9e,0x29,0x8e,0x66,0x2f,0x21,0x59,0x4f,
+0xd6,0x49,0x1d,0x13,0xd4,0x0f,0xdb,0xd7,0x0f,0x1f,0x34,0xdb,0x0f,0xe9,0x0a,0x2d,
+0xd6,0x99,0xbb,0xac,0xcd,0x26,0x08,0x26,0xde,0x3b,0xcd,0xbe,0x77,0xab,0xdf,0x96,
+0x40,0xae,0x79,0x7a,0x8b,0x12,0xec,0x8a,0x9a,0x76,0xf1,0xd6,0x0f,0x97,0x65,0x34,
+0xaf,0x71,0xa0,0xa6,0x72,0x61,0xfa,0x8f,0x67,0xaf,0xcd,0x9e,0x98,0xbe,0x5f,0x43,
+0xbd,0x17,0x71,0x58,0x89,0x3e,0x3e,0x3f,0x3c,0x31,0xcd,0x62,0x8f,0x12,0xc8,0x57,
+0x59,0x99,0xc3,0xbd,0xdc,0x73,0xd3,0x21,0x96,0xb1,0x11,0x52,0x08,0x47,0x42,0xe2,
+0x7d,0x5b,0x73,0x38,0x70,0xb6,0xb9,0x7e,0xc8,0x97,0x79,0x29,0x08,0x6f,0x7a,0x6e,
+0x9a,0x2f,0xae,0x82,0xaf,0x1b,0x7c,0xee,0x64,0x26,0xde,0xf1,0x34,0x65,0x25,0x56,
+0x8c,0x15,0xa3,0xda,0x16,0xdb,0x44,0x7b,0x54,0x62,0x9b,0x64,0x8f,0x2e,0x19,0xff,
+0xdf,0x8c,0x19,0x1b,0xbe,0x45,0xbf,0xb6,0x19,0x2b,0xd2,0x47,0x6b,0xa5,0xac,0x1c,
+0x38,0xeb,0xf7,0x78,0x9d,0xfd,0xb0,0x4c,0x3f,0x2b,0x37,0x3f,0x7c,0x76,0x24,0x4b,
+0x29,0x5c,0x67,0x9f,0x32,0xed,0x1b,0xc4,0x1c,0x2e,0x83,0xfa,0x61,0x64,0x15,0xaf,
+0x31,0x06,0x33,0x72,0xc0,0xac,0x96,0x2c,0x1b,0xd8,0x7a,0xdb,0xfb,0x61,0xb3,0x39,
+0x04,0x3e,0x58,0x31,0x8b,0x45,0x50,0x31,0xe2,0x4f,0x2f,0x79,0x27,0xb1,0x7e,0xfd,
+0xfa,0xbc,0x7e,0x18,0x64,0x89,0x6e,0x4e,0x4a,0x7e,0x8f,0x37,0x02,0xfc,0xd0,0x4a,
+0x21,0xfc,0xc4,0x9c,0x39,0xbc,0x6d,0xcc,0x47,0x03,0x7e,0xa8,0x90,0x98,0x07,0xf6,
+0xe4,0xe3,0xcc,0x18,0xb8,0xdf,0x62,0x27,0x87,0x66,0xc1,0x90,0x4c,0x71,0xec,0x3c,
+0x61,0x6b,0x54,0x92,0x3a,0x26,0xae,0x67,0xb6,0x73,0xfd,0x10,0xae,0x5e,0xdd,0xb4,
+0xfa,0x61,0x43,0xfc,0x10,0xc9,0xbc,0xc6,0x3b,0xcf,0x2b,0x97,0x95,0x5b,0x75,0x9a,
+0xaf,0xdf,0xaf,0xf9,0x61,0x74,0xb3,0xd1,0x24,0x4e,0x72,0xad,0xfe,0xeb,0xa4,0x48,
+0xde,0x7c,0xb4,0x25,0xb0,0x87,0x9b,0x33,0x87,0x33,0x8b,0xb8,0x7f,0x10,0x9f,0x4d,
+0xeb,0x96,0xfc,0xe2,0xe4,0x2c,0xa3,0x33,0x81,0xf5,0xb8,0x14,0x67,0x4a,0x60,0x19,
+0xaa,0x48,0x46,0x76,0x32,0xd2,0x83,0x8c,0xc1,0x22,0x44,0xb6,0xb3,0x1f,0x1e,0xe0,
+0xe7,0x30,0xf0,0x55,0x8f,0x0d,0x0e,0xad,0xf3,0xba,0xeb,0xc8,0x21,0xca,0x9c,0xe1,
+0x95,0x44,0xb5,0x4e,0xfd,0xfa,0x7c,0xfd,0x16,0xc1,0x73,0xd8,0xeb,0x97,0xc3,0x55,
+0x48,0xa0,0xf3,0x66,0x70,0x38,0x68,0x7d,0x2c,0xca,0xd3,0xbd,0x2c,0x65,0xe9,0xd9,
+0x04,0xfd,0x50,0xa5,0xa3,0x4c,0xf1,0xdc,0x18,0xcc,0xe1,0xa4,0x44,0x56,0xd9,0xee,
+0x21,0x71,0x29,0x65,0xd0,0xc8,0xc2,0x67,0x59,0x97,0xb2,0xbd,0xfb,0xf1,0xf9,0xfd,
+0xf0,0xa7,0xfb,0xc0,0x0f,0x91,0xf6,0x72,0x5e,0x49,0xcc,0xca,0x37,0x6c,0x67,0x56,
+0xed,0xea,0xe7,0xae,0x1f,0x06,0x57,0x50,0x5c,0xea,0x9b,0xc3,0x7c,0xe5,0xe7,0x85,
+0x34,0xda,0xfd,0xf0,0xfc,0x18,0x9e,0xcf,0xc2,0xfc,0xd0,0xfa,0x19,0xb3,0x1a,0x22,
+0xc9,0xd8,0xc6,0x66,0xa1,0x19,0x7e,0x08,0x1f,0x43,0xf3,0x3e,0x93,0x99,0x39,0xeb,
+0x35,0x65,0x30,0x6e,0x05,0xf1,0xfb,0xe1,0x4f,0xeb,0xe5,0x87,0x0d,0xe6,0xf0,0x72,
+0x27,0x6f,0x4f,0x18,0x7b,0xfd,0xc9,0x3a,0x7c,0xc3,0x4f,0x36,0x29,0x2e,0xf5,0xcf,
+0xa1,0xd3,0xd1,0x96,0x2c,0x24,0x22,0x0e,0x5f,0x35,0x71,0xd8,0xdf,0x1b,0xc9,0xeb,
+0x1c,0x42,0x3f,0x24,0xfc,0x19,0x54,0x59,0xfd,0x30,0x91,0x7f,0x95,0xfe,0xf2,0xf5,
+0x84,0xbf,0xa3,0x7f,0x5f,0xa6,0x7e,0x65,0x99,0xf4,0x35,0xad,0x83,0xf6,0x1b,0xff,
+0x19,0xfd,0x9b,0xaf,0x6a,0x7e,0xa8,0x9a,0x39,0x6c,0x9a,0x1f,0x46,0x37,0x83,0xed,
+0xcb,0xeb,0xef,0x4d,0x4b,0x5e,0x49,0x8c,0x04,0x3e,0xa7,0x46,0x6f,0x2f,0xbd,0xd3,
+0x68,0x0e,0xf9,0xb2,0xe8,0x3b,0xc9,0x99,0x43,0x7b,0xb1,0xfa,0xe1,0x4c,0x06,0x67,
+0x20,0x49,0x03,0x0e,0x2d,0xf5,0x0f,0x7a,0x3b,0x19,0xe9,0xfd,0x11,0x18,0x6b,0xdf,
+0x1b,0x9e,0x34,0x7e,0x37,0x55,0xab,0x8f,0x9a,0xfb,0xbc,0x7c,0x64,0x6c,0x6c,0x1d,
+0x0d,0x9c,0x55,0x5d,0xfc,0x50,0x35,0xe2,0xf9,0xf7,0xf7,0x89,0x1f,0x22,0xa1,0xd1,
+0x55,0x5e,0x49,0xf4,0xb6,0x36,0xb8,0xbb,0x9a,0xe3,0x87,0x73,0xf2,0xbb,0xbe,0x39,
+0x74,0xfb,0xd5,0x28,0xe9,0x7f,0x55,0xf9,0x55,0x10,0xc5,0x5f,0x9b,0x9d,0x34,0x72,
+0x00,0x2d,0x83,0x79,0xae,0xd6,0x4f,0x97,0x71,0x98,0xb5,0xcd,0x02,0xd5,0x38,0x94,
+0x88,0x1f,0x9a,0x0b,0x5b,0xcf,0xd1,0xf0,0x43,0x9f,0x19,0xfd,0x5b,0x41,0x95,0xfc,
+0x50,0x05,0x5b,0xb3,0xfd,0xb0,0x1e,0x63,0x5b,0x5e,0x1c,0x53,0x3d,0x93,0x78,0x24,
+0xd0,0xf9,0xfa,0xa8,0x7e,0xf8,0xe5,0x9d,0xc6,0x92,0x18,0xdb,0xcc,0xca,0x3c,0xab,
+0x59,0x38,0x89,0xd7,0x0f,0x55,0xe0,0x87,0xb7,0x26,0xd0,0x88,0x6d,0xcc,0x61,0x1a,
+0x72,0x68,0x62,0x0a,0xb5,0xb6,0x50,0x0e,0x65,0xfb,0x77,0x6d,0xcd,0x50,0x45,0xd7,
+0xd8,0x80,0xb3,0x74,0xe4,0x76,0xf7,0xc3,0x6a,0xf5,0x43,0x16,0x99,0xee,0x2f,0x3f,
+0x44,0x7a,0x70,0xba,0xa4,0x78,0x25,0x31,0xc8,0xcf,0xa0,0x19,0xfd,0x16,0xd1,0x9a,
+0x38,0xe4,0x7b,0x0d,0xc6,0xe1,0xb9,0xf8,0x5e,0x8e,0x71,0x08,0xfd,0xd0,0xea,0x6d,
+0xec,0x3c,0x9b,0x94,0xde,0xb0,0xb5,0x89,0x45,0x4c,0x99,0xc4,0x1d,0x56,0x87,0xad,
+0x71,0x85,0x9b,0x56,0x90,0x5b,0x7b,0xa9,0x4a,0x3f,0xb7,0xc6,0xfb,0x61,0x99,0x6e,
+0xf5,0x19,0xeb,0x79,0x62,0xba,0xec,0x89,0x44,0x74,0x6f,0xff,0xe3,0x51,0xac,0x62,
+0x71,0x29,0xfa,0x5b,0x69,0x83,0xff,0x37,0x13,0x55,0x8d,0xb6,0x4a,0xff,0x89,0x15,
+0x6b,0xe1,0x30,0xc6,0xf5,0xab,0x51,0x52,0x30,0x49,0x3d,0xa1,0x99,0xc5,0x48,0x3e,
+0x42,0x39,0x9c,0xb3,0xf5,0xe2,0x3b,0x91,0xf8,0xc0,0x61,0x16,0xb6,0x53,0xbb,0x9a,
+0xea,0xb0,0xf7,0x9a,0x49,0xbc,0x95,0x54,0x99,0x43,0x15,0xec,0xd1,0x27,0xb7,0xd5,
+0x24,0x3f,0x44,0xdf,0x6d,0xbd,0x56,0x98,0xfc,0xd8,0xe3,0x08,0x1b,0x74,0xef,0x37,
+0x03,0xea,0xd7,0x77,0xf2,0x43,0x2b,0x81,0xd5,0xa8,0xf2,0xe3,0xa5,0xba,0x1f,0xd6,
+0xad,0x7e,0x48,0x0a,0xce,0xca,0x7c,0x6d,0x16,0x8d,0x0f,0x65,0x1c,0x92,0xf6,0x52,
+0xd5,0xda,0x4a,0x43,0x29,0x54,0x15,0xe7,0xb5,0xfd,0xec,0x19,0x1b,0x4d,0xbe,0x48,
+0xe7,0xa9,0xee,0x37,0x3f,0xc4,0xe4,0xa9,0xa6,0x4b,0x65,0xe5,0x5a,0x43,0x39,0x2c,
+0x83,0x2d,0xe8,0xf6,0x52,0xa8,0xdf,0xf7,0x3c,0xc2,0xa6,0x20,0x7f,0x7e,0x2c,0x88,
+0x57,0xd6,0x39,0x2c,0x22,0x36,0x98,0x2b,0xb2,0x3d,0xb9,0xd5,0x8d,0x40,0xab,0x6f,
+0x56,0xa7,0xb5,0x36,0x3f,0x44,0x47,0xcb,0x53,0xd0,0x2c,0xea,0x5b,0x13,0x3b,0x1a,
+0x85,0x7b,0x3f,0x01,0x1c,0x56,0xf1,0x43,0x55,0xaf,0xf9,0x54,0xfa,0xb5,0x0d,0x36,
+0x43,0x55,0x6b,0xaa,0xba,0x1f,0xaa,0xa0,0x9d,0xa6,0x91,0x1c,0x96,0x4d,0x5b,0xfd,
+0xfc,0x10,0xc9,0x75,0x84,0x8d,0x6c,0x3d,0xb6,0xb4,0xe4,0x96,0xf9,0x81,0x47,0xc4,
+0x0f,0x2b,0x79,0x9f,0x9b,0x0f,0x56,0x8b,0x56,0x2b,0x91,0x59,0x9b,0x1f,0xf2,0x3a,
+0xf0,0xb9,0xf8,0x68,0x7c,0x29,0xb3,0x9d,0xdb,0xc9,0x75,0xad,0x46,0xf2,0xa9,0x3c,
+0xe9,0xb5,0x20,0x1c,0xda,0x57,0x44,0x47,0xed,0x9d,0x59,0xd9,0x5e,0x33,0xc4,0xaa,
+0xce,0x21,0x6d,0xb5,0xd9,0x17,0x1c,0xc2,0x28,0xd4,0x3a,0x57,0x16,0x7d,0x4a,0x8d,
+0xf0,0xc3,0xb2,0x6d,0x23,0x67,0x4f,0x7d,0x57,0x3e,0x47,0x23,0x6c,0x54,0xf8,0xad,
+0x42,0xfa,0xc0,0x08,0x74,0x32,0x26,0x12,0xe5,0xaa,0xf0,0x7b,0x36,0x33,0x21,0x0e,
+0x63,0x45,0xe4,0x7b,0x66,0xef,0xc3,0x7c,0x91,0x5b,0x19,0x51,0xe6,0x4b,0xec,0x51,
+0xe4,0xbe,0xec,0x39,0x9c,0xa2,0xdb,0x40,0xfc,0x90,0xb3,0x7e,0xf8,0xe6,0xd8,0xc3,
+0x3f,0x59,0xcb,0x6c,0x67,0xf6,0x34,0x0e,0x71,0x3b,0x0d,0xec,0x3d,0x54,0x6d,0x14,
+0xe2,0xf2,0x8b,0x97,0x2b,0xbd,0x72,0xd0,0x99,0x53,0x5b,0x51,0x66,0x3f,0x54,0x4d,
+0x44,0xaa,0x32,0x6c,0xa7,0x69,0x94,0x1f,0xda,0x49,0xac,0x37,0x87,0xef,0x74,0x26,
+0xf2,0x24,0x77,0x18,0x9c,0x61,0xba,0x2e,0x93,0x39,0xe0,0xe6,0xb9,0x6f,0xfe,0x32,
+0x1b,0x5b,0x45,0x38,0x34,0x93,0x67,0xa6,0xcf,0x28,0x77,0x50,0x8f,0x03,0xbe,0x1d,
+0xed,0x71,0x6f,0x07,0xde,0x7f,0x69,0xec,0xd1,0x33,0xe9,0xd7,0xb5,0x2d,0x8a,0x9e,
+0xf5,0x0e,0x7e,0x2e,0x74,0x7f,0x14,0x4f,0x7e,0xa9,0x3f,0x53,0xb2,0xe8,0x7f,0x56,
+0x31,0x7f,0x5c,0x7a,0x72,0x71,0x66,0x71,0xc9,0xe0,0xd0,0xee,0x87,0x4e,0x1c,0x96,
+0x2b,0xd4,0x0c,0xb1,0x78,0x39,0xdc,0x2f,0xf5,0x43,0xd5,0x46,0x23,0x99,0x6d,0x59,
+0xaa,0x9b,0x1f,0x3a,0x7b,0x60,0xc9,0xf4,0xbd,0x46,0x37,0x83,0xee,0x43,0xb7,0xea,
+0xdb,0x71,0xbc,0xd2,0x02,0xac,0x19,0xc3,0x4c,0x44,0x2a,0xfc,0x6c,0xd0,0x4a,0x70,
+0x1a,0x89,0x33,0x35,0xce,0x12,0xa6,0x7e,0xa8,0x53,0x82,0xc8,0x31,0x68,0xbb,0x43,
+0xae,0x1b,0x54,0x12,0xca,0x14,0xbc,0xb7,0xff,0x66,0x95,0xe9,0x65,0xf2,0xd7,0xb9,
+0xa0,0x51,0x6d,0xfe,0x57,0xb6,0xe2,0x6d,0x2f,0x45,0x23,0x1e,0x4e,0x2e,0xae,0x65,
+0x76,0x8c,0x56,0x1a,0xb3,0x1f,0x3a,0xb5,0x95,0xa2,0xd1,0x4a,0xd5,0x5e,0x99,0xdf,
+0x0f,0xbf,0xdd,0xf0,0xd5,0x82,0x82,0x12,0xe3,0x10,0xb6,0xcb,0x80,0xcb,0xd4,0x27,
+0xea,0xc1,0x21,0x39,0xab,0xec,0x34,0x42,0x12,0xbf,0xbc,0x53,0xff,0xb5,0x27,0xee,
+0x0e,0xa5,0x25,0xbe,0x99,0x98,0xa4,0xd4,0x3a,0x4b,0x98,0xf9,0x21,0xf1,0xac,0xd8,
+0x26,0xf3,0x30,0x42,0x23,0x8a,0x24,0x9f,0x1d,0xb9,0x31,0x78,0x77,0xe8,0xe6,0xd0,
+0x5d,0xad,0xdc,0x18,0x3c,0x17,0x7f,0xd5,0xfb,0x36,0x88,0xf6,0xb5,0xd5,0x6a,0x35,
+0x0e,0x39,0xfd,0x70,0x2d,0x83,0xfc,0x10,0x71,0xd8,0xa5,0x51,0x88,0xfd,0x70,0x4e,
+0x66,0x7e,0x68,0xa5,0xb0,0x72,0xcd,0x10,0x2b,0xb8,0x8c,0x8d,0xad,0xab,0x81,0xe9,
+0x12,0xc8,0x6a,0x4f,0x09,0x04,0xd1,0x18,0x1e,0x53,0x5b,0x1f,0x3f,0x44,0x67,0xa1,
+0x13,0x79,0xe6,0x12,0xdb,0x6c,0xc4,0x1a,0x30,0x2f,0x8e,0x65,0x3d,0x71,0x88,0xda,
+0xae,0x6a,0x99,0x25,0x4c,0x39,0x04,0x51,0x25,0x2a,0x24,0xd2,0xd4,0xa3,0x4d,0xed,
+0x3f,0x69,0xdf,0x33,0x77,0x83,0x95,0x37,0x0e,0x99,0x1f,0x9a,0x7b,0xf1,0x09,0x85,
+0xf0,0x3b,0xaf,0x5c,0x33,0xc4,0xfa,0x4a,0x70,0xe8,0x50,0x3f,0x54,0xc1,0x65,0xe2,
+0x89,0xf5,0x6b,0xa7,0x71,0x27,0xb1,0x31,0x1c,0xa2,0x1c,0x36,0xbc,0x39,0xbf,0xd9,
+0xcc,0x72,0xff,0xb3,0x84,0x75,0x0e,0x71,0x5d,0x8f,0x52,0x87,0xeb,0x76,0xa4,0xde,
+0x87,0x09,0x4d,0xfb,0x9e,0x21,0x11,0xac,0xfc,0x72,0x88,0xfd,0x30,0x6b,0xf3,0x43,
+0x12,0x47,0xbb,0x8f,0x16,0xe4,0xe0,0x50,0xde,0x3f,0x1c,0xb2,0x98,0x14,0x64,0xba,
+0x97,0x4b,0xc6,0x0c,0xaf,0xfa,0xf9,0xa1,0x7b,0x69,0x14,0x87,0xa1,0xd0,0x73,0x67,
+0xf1,0xdc,0x1b,0xd4,0xe7,0xac,0xaf,0xd5,0x86,0xb7,0xaa,0x3c,0xfa,0x9d,0x25,0xdc,
+0xdf,0xab,0xca,0x46,0x46,0x99,0x22,0xc9,0x3b,0x13,0x65,0xd7,0x8d,0x08,0x15,0x71,
+0xd8,0x1a,0xab,0xa7,0xec,0xe5,0x78,0x39,0xdc,0x76,0xf0,0x43,0x6b,0x2b,0x0d,0xb9,
+0x6f,0xf5,0x9a,0x21,0x16,0xc9,0x50,0xb5,0xff,0xfd,0xd0,0xdc,0x46,0x6a,0xac,0xfa,
+0xc2,0x5a,0x2c,0xea,0xec,0x87,0x6e,0x25,0x5a,0x6c,0xdc,0xda,0x84,0xd7,0x66,0x97,
+0xab,0xac,0x57,0x4a,0x56,0x2d,0x45,0xdb,0x32,0x5a,0x6b,0x58,0x3b,0xbf,0x26,0x25,
+0x7f,0xb3,0x84,0x71,0x5c,0x6a,0xb4,0x75,0x6a,0x7b,0x56,0x4b,0x04,0xad,0x32,0xc5,
+0xd6,0xf1,0x43,0x7e,0x0e,0x9d,0xe2,0x52,0xd8,0x7b,0x58,0xa2,0x24,0x16,0x5c,0x6a,
+0x86,0x58,0x5f,0xa5,0xb8,0xd4,0x58,0x7b,0x47,0x06,0x59,0xee,0xe9,0x1a,0x84,0xf8,
+0x53,0x6b,0xa2,0x1f,0x36,0x90,0x43,0x34,0xd6,0x0d,0xcf,0x08,0x67,0x25,0x6d,0xb9,
+0x6c,0x5d,0xc1,0x34,0x92,0xf7,0xd3,0x5e,0x8e,0xfd,0xd0,0xc8,0xbe,0xb6,0x49,0x73,
+0xaa,0x6d,0x46,0x8b,0xe6,0x1c,0x6c,0xad,0xe7,0x87,0xce,0x7d,0x93,0x95,0xfd,0xd0,
+0xdc,0x6b,0xc1,0x28,0x2c,0x2b,0x4e,0xa3,0x49,0xed,0x72,0xca,0x50,0xb5,0xdf,0x38,
+0x3c,0x31,0xcd,0x56,0xdd,0x21,0x5e,0xb8,0x6e,0x78,0x60,0x41,0x61,0x79,0x77,0xeb,
+0xd7,0x6f,0xd1,0x6a,0x1c,0xa2,0x75,0x50,0xf0,0x0a,0x0b,0xac,0xa4,0xf4,0x0d,0x95,
+0xef,0x48,0x29,0x0b,0xa3,0xe8,0x1c,0xdb,0xce,0x78,0x67,0x05,0xfb,0x21,0x26,0x0f,
+0x70,0x08,0x32,0x24,0xe2,0xeb,0xad,0xe4,0x87,0x7c,0xbf,0x9b,0x3b,0xb9,0xaa,0x71,
+0xa9,0x41,0x62,0xb4,0x58,0xad,0xcf,0x10,0xaa,0x6b,0xb5,0x1a,0x7d,0xac,0x64,0xdb,
+0x98,0xc3,0x6b,0xb3,0x6c,0x1d,0x3a,0x90,0xeb,0x1a,0xac,0x3e,0x50,0x4f,0x3f,0xfc,
+0x92,0x8b,0xc3,0x46,0xc6,0xa5,0x58,0x27,0x17,0xf5,0xfc,0x99,0xa0,0x24,0xe8,0x06,
+0xe9,0x24,0x4c,0xce,0xc9,0xde,0x7b,0x13,0x8d,0xfa,0x21,0xa1,0xcf,0x20,0x8f,0xee,
+0x8d,0xdb,0x93,0x2d,0xe6,0x87,0x6e,0x5e,0x88,0xfe,0xb7,0x9d,0x9b,0xc9,0x6c,0x67,
+0x76,0xf4,0xd1,0x34,0x46,0xaf,0x85,0xad,0x7e,0x18,0xdd,0xe4,0xa9,0x19,0x62,0x75,
+0xd1,0x19,0x57,0x95,0x3d,0x11,0x9d,0xaf,0xed,0xec,0x87,0xd7,0x66,0xcb,0x0a,0x71,
+0x43,0x98,0x03,0xcb,0xe0,0xd0,0x88,0xe6,0xeb,0x55,0x3f,0xe4,0x8d,0x4b,0xeb,0xdd,
+0x8f,0x6f,0xd5,0xcb,0x61,0x34,0x67,0x07,0xcd,0x17,0xc0,0xa5,0x6b,0x75,0xef,0x27,
+0x68,0x3d,0x3e,0x34,0x3e,0x24,0xb2,0x0a,0xc9,0x24,0x44,0xa6,0x25,0xaf,0xbd,0x89,
+0x26,0x0e,0x37,0x0d,0x02,0x89,0x0f,0x92,0xc8,0xb4,0xc5,0xe2,0xd2,0x6a,0x23,0xca,
+0xa1,0x1f,0xbe,0xad,0xf9,0xe1,0x9e,0x63,0x5c,0x8a,0x33,0x26,0xea,0x59,0x6c,0xb8,
+0x6b,0xd5,0x11,0xae,0x8c,0xfe,0xaa,0xdc,0xfe,0x7e,0xa8,0x52,0x3f,0x34,0xd6,0x5f,
+0x32,0x65,0xf7,0x55,0xeb,0x57,0x3f,0xe4,0xaa,0xf9,0x37,0x3a,0x2e,0x45,0xfa,0x34,
+0xf6,0x5a,0x06,0xad,0xaf,0x40,0xca,0x1e,0xdd,0x20,0x9d,0x11,0xca,0x22,0xfa,0xdd,
+0xf7,0xd6,0x9b,0xc8,0x38,0x8c,0x3a,0x44,0xa3,0xb1,0x16,0xf4,0xc3,0x64,0x11,0x8e,
+0x68,0x85,0x7b,0x46,0x27,0xda,0xd0,0x6a,0x69,0x64,0x74,0xa9,0xb9,0xd7,0x82,0xb5,
+0x96,0xf2,0xd5,0x0c,0xb1,0xcc,0x23,0x5b,0x2b,0xd3,0x98,0x95,0x47,0xdb,0x98,0xc3,
+0x32,0x75,0xbf,0x75,0x92,0x13,0xcb,0xb4,0xfa,0x40,0x2b,0xb4,0xd3,0x34,0xda,0x0f,
+0x91,0x46,0xe3,0xaf,0x65,0xd6,0x1c,0xcb,0x07,0xfa,0x5c,0x82,0x1d,0x4a,0x25,0xa1,
+0x71,0xd2,0x94,0xdf,0xc8,0x4d,0x4f,0x92,0xfa,0x21,0x28,0x84,0x46,0xe8,0x93,0xad,
+0x55,0x3f,0x34,0x8f,0x26,0x87,0xf4,0xb1,0xdb,0x11,0x87,0x1f,0x64,0x4c,0xbd,0x87,
+0x60,0xee,0x21,0xea,0x03,0xf3,0x16,0x3b,0x90,0x4c,0x00,0x2e,0x7e,0xb8,0x1f,0x38,
+0xc4,0x99,0x76,0x2c,0x63,0x70,0x41,0xde,0xd6,0x3a,0x71,0xc8,0xd7,0x12,0xde,0x0c,
+0x3f,0x44,0xba,0x31,0x88,0xc6,0x67,0xcd,0x64,0x66,0x16,0x5f,0xcb,0xbc,0xbd,0x88,
+0x56,0xc4,0x64,0xc5,0x60,0x92,0xd2,0x88,0xbc,0x11,0xb1,0xc8,0xdf,0x9b,0xf8,0x6e,
+0xcc,0xce,0xa1,0xbd,0x24,0x8b,0x73,0x72,0x6b,0xf8,0x61,0xd7,0x6a,0xb2,0x18,0xdb,
+0x64,0xf3,0x3d,0x18,0x83,0x66,0x4f,0x8c,0x15,0xf7,0x72,0x4b,0x0e,0xbd,0xf8,0xa4,
+0x67,0xac,0xac,0x74,0xad,0x7a,0x7b,0x65,0xfb,0x4c,0x0f,0x33,0x89,0xaa,0x91,0xdb,
+0xbb,0xbd,0xe3,0xd2,0xb2,0x02,0xe6,0x35,0x5b,0x7a,0x2b,0x58,0x69,0x6e,0x5c,0xda,
+0x0c,0x3f,0x44,0xba,0x3f,0x74,0x72,0xd1,0x5e,0x66,0xf4,0xc2,0x88,0xdc,0xd6,0xfd,
+0x91,0x38,0x23,0x6f,0x6f,0xe2,0x6d,0x8d,0xc3,0xa4,0x0b,0x85,0xd1,0x16,0x8a,0x4b,
+0xbb,0x56,0x2b,0xff,0x6a,0xc2,0x99,0x56,0xb1,0x4d,0xc8,0xa1,0xad,0xf7,0xd0,0x87,
+0x6b,0x39,0x65,0xc6,0xb1,0x7a,0x21,0x6e,0xed,0xaf,0x47,0xbe,0xe7,0xc6,0x08,0x73,
+0x08,0xdc,0x0f,0xae,0x00,0x22,0xd7,0x9b,0x43,0x5e,0x3f,0x6c,0x16,0x87,0x68,0x6d,
+0xb8,0xce,0x05,0x6b,0x39,0xa2,0x17,0xc6,0x24,0xa1,0x11,0x9f,0x7b,0x3b,0xb9,0x7e,
+0xae,0xde,0xc4,0x77,0x39,0x38,0xc4,0xf5,0xc3,0x7a,0xbf,0x47,0x3e,0xa1,0xfa,0x21,
+0x19,0x07,0x8b,0xe7,0x89,0xe0,0xd1,0xe8,0x66,0x67,0x44,0xb7,0x57,0xe6,0x10,0x9d,
+0x49,0x5e,0x62,0x77,0x2c,0xe7,0x11,0x75,0x66,0x0a,0x71,0x69,0x5f,0x0e,0x2f,0x4c,
+0x97,0x95,0x75,0xa3,0x5d,0x94,0xac,0xdf,0x41,0xdd,0x1e,0xac,0x15,0x58,0x56,0x2e,
+0x04,0xbe,0xf2,0x51,0x7d,0xda,0x69,0x46,0xe3,0x78,0x6e,0xc1,0xb9,0xea,0xfb,0x41,
+0x97,0xff,0x1b,0xfb,0xd1,0xf8,0x5b,0xd3,0x84,0xb8,0xd7,0xd0,0x66,0x8d,0x4c,0xa9,
+0x17,0x92,0xc8,0x34,0x2d,0xed,0xe4,0x6e,0x73,0xcc,0xb5,0xe5,0xf1,0x43,0x54,0x0a,
+0xf2,0xf9,0xb1,0xfb,0x43,0xe1,0x91,0xfa,0x14,0x7e,0x6f,0x42,0x7e,0x18,0xa5,0xe3,
+0x61,0x9d,0xf3,0x77,0xe8,0x7e,0x68,0xe1,0x10,0xb6,0x96,0x96,0x7d,0xad,0x56,0x64,
+0xf5,0x43,0x4b,0x54,0x2a,0xb3,0x79,0x32,0xad,0xc3,0xe1,0xcd,0xc1,0xf0,0xc8,0xe7,
+0xc7,0x58,0x41,0xd7,0xcc,0x1b,0x2a,0x64,0x7f,0x77,0xe8,0xc8,0x02,0x65,0x8e,0xf6,
+0x1b,0x3a,0x15,0x34,0xbb,0x33,0x3e,0x76,0x9e,0xbb,0xbc,0x38,0xe6,0x7e,0x2e,0x06,
+0xef,0x87,0xa3,0xf1,0x48,0xbe,0x64,0xfb,0xc6,0xec,0x97,0xfd,0x14,0x77,0x62,0x98,
+0x87,0x0d,0x70,0x64,0x75,0xe3,0xe5,0x10,0x3d,0x5f,0xfd,0x4a,0x59,0xe1,0x39,0x56,
+0xa4,0x88,0x56,0x3f,0x34,0x46,0x1c,0x98,0xe6,0x84,0xa0,0x3e,0xe0,0x2f,0x41,0x6b,
+0x0d,0xe2,0xd0,0x79,0x34,0x4d,0xc9,0xe7,0xec,0x69,0xe7,0x8c,0x8d,0xd0,0x0f,0xd5,
+0x96,0xe2,0xb0,0x37,0xbc,0x94,0x71,0xa6,0x88,0xd1,0x04,0x37,0xe3,0xdd,0xe0,0x19,
+0x4e,0xb0,0x8d,0xb4,0xc2,0x63,0x79,0x8b,0x3e,0x42,0xb9,0x98,0x95,0xdd,0x56,0x9f,
+0x0d,0xbe,0x7e,0xb8,0xa3,0xc7,0x4e,0x74,0x1e,0x9f,0xfd,0x9c,0x26,0x6b,0x75,0xd6,
+0xb5,0x24,0x8b,0x57,0x39,0x66,0x61,0xf0,0x73,0x18,0x70,0xd9,0x04,0xed,0xb2,0x9b,
+0xc9,0x62,0x49,0xfe,0x94,0x2b,0x53,0x46,0x97,0xce,0x21,0xcc,0x07,0x80,0x3f,0x63,
+0x63,0xbe,0x24,0x6d,0xaf,0xc1,0x1c,0xc2,0x5e,0x0b,0x32,0xf7,0x30,0x2d,0xf9,0x6b,
+0xcf,0x74,0xca,0xc8,0x01,0xce,0x4c,0x3a,0x3a,0xba,0x3e,0xeb,0x01,0x79,0x17,0x8a,
+0x31,0xcd,0x33,0x98,0xe8,0x25,0x32,0x7f,0x82,0xd6,0xfb,0x4c,0xde,0x57,0xc5,0x07,
+0xf9,0xa9,0xb6,0x92,0x1a,0x2b,0xba,0xfd,0xfa,0xb9,0xf9,0x21,0xad,0xf9,0x73,0x72,
+0xd8,0x1b,0x4a,0x4b,0xe8,0x4c,0x33,0x46,0x4e,0x2b,0xe6,0xf5,0x70,0x0d,0x2e,0x2d,
+0x7d,0x74,0xa4,0xf7,0x3c,0x48,0x0a,0xf9,0x6a,0x74,0x4d,0xe3,0xd0,0x56,0x6e,0x72,
+0xcd,0xd1,0xff,0xbf,0x39,0x70,0xb4,0xda,0x27,0x86,0x3f,0x5f,0x90,0xa1,0x83,0x64,
+0xe2,0x28,0x76,0xad,0xae,0x65,0x9c,0x32,0x26,0xfa,0x9d,0x23,0x56,0xad,0x7e,0x68,
+0x5e,0xd7,0x9b,0x67,0xd4,0x78,0xfd,0x85,0x62,0x4c,0x38,0x6f,0xb0,0x00,0xfe,0x92,
+0x31,0xa4,0x34,0xdf,0x0a,0x58,0x0f,0xde,0xb2,0x26,0x6f,0x60,0x44,0xba,0x8d,0x5c,
+0x0a,0xba,0x7e,0xd8,0x1b,0x46,0x1c,0xda,0xf3,0xb7,0xc4,0xa8,0x0f,0x1a,0x63,0xa8,
+0xe1,0x6a,0xd5,0x9b,0xf0,0xdc,0x82,0x7b,0x6b,0x8f,0x3a,0x3f,0x87,0x7c,0x91,0x5e,
+0xb3,0x39,0x64,0xef,0x9e,0x2f,0x57,0x06,0xee,0xb7,0x88,0x92,0xc7,0x19,0x19,0x3b,
+0xca,0x60,0xfe,0x24,0x76,0xc4,0x58,0x31,0x92,0xdf,0x26,0x1c,0xd2,0x5e,0x0b,0x55,
+0xf6,0xbf,0x5e,0xd8,0xde,0x4f,0xcc,0x7e,0x58,0x62,0x7e,0x28,0xc3,0x5c,0xe0,0xad,
+0xc4,0x21,0x98,0xbd,0x0b,0x7c,0x91,0xe4,0x99,0xa1,0x23,0xd6,0x4c,0x3e,0x68,0x5a,
+0xd1,0x2a,0x10,0x2f,0xe4,0xe5,0xd0,0xbd,0x7e,0xe8,0xc5,0x0f,0x8f,0x19,0x1c,0x46,
+0x8d,0x55,0xe2,0xf1,0x38,0x15,0x3c,0x8b,0x2f,0x0a,0xb9,0xb2,0xf4,0x94,0xfb,0x25,
+0xce,0x99,0x42,0xde,0x95,0xaf,0x9b,0xcd,0x21,0x2b,0x7c,0x7e,0xd8,0x95,0x47,0x47,
+0x1b,0xc5,0xbf,0x63,0xa6,0xdf,0x2a,0x7c,0x0b,0x9b,0xb9,0x8c,0xda,0x8c,0x71,0xab,
+0x15,0xcb,0x4c,0x53,0x4b,0x8b,0xb7,0x7d,0xc6,0x15,0x23,0x91,0xd5,0x0d,0xb3,0x2d,
+0xc5,0x21,0x9c,0x5b,0x4f,0x58,0x2c,0xc9,0x30,0xff,0x18,0x6b,0x03,0x55,0x4d,0x11,
+0x69,0xed,0x34,0x5a,0x09,0x72,0xcb,0x0d,0xe6,0xee,0x87,0xa4,0xc6,0xc1,0x19,0x97,
+0xea,0x1c,0x12,0xb2,0xa2,0xa0,0x36,0x68,0x8c,0xdb,0xa4,0xfc,0x59,0xc9,0x0b,0x8e,
+0xc4,0x64,0x91,0x37,0xf3,0x7e,0xeb,0x70,0xc8,0xe7,0x87,0x11,0xdd,0x0f,0xd9,0x27,
+0x86,0x0b,0xa2,0x8f,0xee,0xf5,0xba,0x63,0x6c,0x13,0x73,0x08,0x33,0x44,0x4d,0xd6,
+0xb4,0x02,0xcc,0x5e,0xce,0x7e,0x9e,0x90,0x33,0x50,0x05,0x2b,0xd4,0xb4,0x12,0x87,
+0x30,0x2a,0x55,0x69,0x9e,0x99,0x02,0xec,0x9f,0x37,0x66,0xd8,0x7b,0x8f,0x3e,0x79,
+0xe8,0x83,0xd1,0xa4,0x57,0x3f,0xb4,0x8f,0x94,0xc2,0x97,0x92,0x9e,0xfc,0x90,0x9c,
+0x25,0x76,0xc2,0xa2,0x01,0x7b,0x9f,0x13,0x85,0xfc,0xbd,0x7d,0x98,0xc3,0xa4,0xfe,
+0xa8,0xca,0x5b,0xac,0xca,0x3e,0xa8,0xc2,0xe7,0x87,0x91,0x3c,0x79,0x5d,0x36,0x1f,
+0x24,0x6a,0x27,0x53,0xbb,0x9e,0xd0,0x38,0x64,0x63,0x69,0x50,0x66,0x1a,0x9e,0x76,
+0xab,0xca,0x72,0xf2,0x43,0x7c,0x26,0xaf,0xcb,0x90,0xc2,0xb4,0xc3,0x1a,0x35,0xcd,
+0x10,0xab,0x1f,0x5a,0x32,0x00,0xd2,0x91,0xdc,0x25,0xd6,0x52,0x83,0x59,0xb4,0x66,
+0xc9,0x0d,0x90,0x46,0x1e,0x3f,0x74,0x8a,0x4b,0xed,0x39,0xad,0xbd,0xfa,0x61,0xd4,
+0xdc,0x3e,0x53,0xa4,0x75,0x1a,0x47,0x3a,0x83,0xe5,0x90,0x7f,0x1d,0x1a,0xe2,0x87,
+0x56,0xaa,0x82,0xa6,0xcc,0xbd,0xf0,0xf9,0xa1,0xd1,0x16,0x8d,0x7b,0xf0,0x49,0x9c,
+0x01,0x3e,0x5f,0xec,0x85,0x98,0x43,0xd8,0x4a,0x53,0x90,0x6b,0x1d,0x01,0xa2,0x71,
+0xb8,0x69,0xa7,0x50,0x35,0xad,0x5f,0x8a,0x56,0x4e,0x6c,0x25,0x0e,0x59,0xbd,0x90,
+0x44,0xa2,0x05,0x1a,0x8d,0xd2,0x88,0x5a,0x61,0xe3,0x46,0xbd,0x12,0xe8,0xee,0x83,
+0xb4,0xdc,0xf1,0xe2,0x87,0xf6,0x75,0x8e,0x58,0x56,0x5d,0x2f,0x7e,0x98,0x2c,0x56,
+0xf0,0xc0,0x3a,0xf5,0x56,0x24,0xc1,0xde,0xdb,0xd8,0x17,0x3e,0x3f,0xf4,0xb2,0xc1,
+0xe3,0x09,0x9e,0xc3,0xb5,0x4c,0xd2,0xf8,0x1c,0x69,0xeb,0x33,0x6c,0xd9,0x02,0xfd,
+0x44,0xa9,0x3c,0x5a,0x6f,0x2d,0xa5,0x73,0x98,0x95,0x6b,0x1f,0x1b,0x5c,0xc9,0x0f,
+0x61,0x0b,0x0d,0xce,0x66,0xc2,0x3f,0x97,0xaa,0x9e,0x82,0xf5,0x43,0xd5,0xa8,0x17,
+0x92,0x96,0x98,0x75,0x05,0xf6,0x12,0x92,0xb5,0x72,0xaa,0xf5,0x17,0xfa,0x8f,0x48,
+0x09,0x59,0xfe,0xda,0x69,0xac,0x63,0x35,0x3c,0xd7,0x0f,0x8b,0xf5,0x25,0xaf,0x32,
+0x91,0xc9,0xa2,0x97,0xd9,0x3c,0xd0,0x0f,0x9b,0x49,0xa1,0x17,0x0e,0x4d,0x71,0x84,
+0x29,0xca,0xa7,0xbd,0x42,0xda,0x3e,0x25,0xb1,0xbc,0xa5,0x89,0xfc,0x67,0x3d,0xfc,
+0x9f,0x89,0xb3,0xac,0x1c,0x92,0xa8,0x14,0xb6,0xd0,0xcc,0xe9,0x1c,0xb6,0x46,0xff,
+0x21,0xe6,0x90,0xd0,0x47,0x33,0x00,0xd3,0x76,0x18,0x15,0x8e,0x1f,0xf5,0x4d,0x1f,
+0x97,0x17,0x22,0x8a,0x5c,0x73,0xb8,0xdb,0x39,0x84,0x2b,0x1f,0xe9,0x7f,0xf5,0x56,
+0x71,0xcf,0x7e,0x58,0xa7,0x7a,0x60,0x75,0x12,0xf8,0x5b,0x4a,0xb1,0x88,0x1f,0xfa,
+0x2d,0x31,0xb0,0xf7,0x4f,0x29,0xba,0x8d,0xaf,0x7e,0xf8,0x41,0xce,0xe9,0xf1,0x3a,
+0x83,0x80,0xc5,0xa8,0xce,0x21,0x6b,0x2b,0x7d,0x71,0xcc,0xcb,0x67,0xe2,0x2c,0x33,
+0x87,0x2c,0x2a,0x55,0x4d,0x75,0x43,0x54,0xf8,0xde,0x49,0xbd,0xc5,0xe2,0x52,0x53,
+0xc6,0x27,0xdc,0x5a,0xa3,0x10,0x2e,0x55,0x9f,0xfd,0x84,0x5e,0x49,0x74,0xf7,0xc3,
+0x67,0x47,0x2a,0x65,0x1e,0x82,0xeb,0xa6,0xf8,0xf1,0xc3,0x46,0x8c,0x9b,0x81,0x67,
+0x37,0xde,0xbc,0x8d,0x60,0x66,0x1c,0xc6,0x1c,0xc8,0x0a,0x26,0x62,0xe5,0x2b,0x7c,
+0x7e,0xb8,0x9d,0x01,0xcf,0xb8,0x69,0xa7,0xcf,0xe8,0x23,0xd2,0xf6,0x28,0xbb,0x0f,
+0x72,0xc3,0xac,0x1c,0xcc,0x98,0x64,0x27,0x0e,0x4b,0xa6,0xfe,0x8a,0x65,0x23,0x7f,
+0x57,0xeb,0xf8,0x21,0x6b,0x1f,0x45,0xe4,0xad,0xd3,0xf6,0x18,0x3f,0xe3,0x65,0xfc,
+0x7b,0x21,0x2a,0x31,0x57,0x3f,0xbc,0x3a,0x01,0x33,0x0f,0x59,0x57,0x37,0xa2,0xb9,
+0xad,0x3d,0xd4,0x0f,0xe7,0x24,0xfe,0xb3,0xcf,0x2b,0x65,0x95,0x7d,0x10,0xef,0xbd,
+0xb9,0x61,0xed,0x7e,0x18,0x9c,0x47,0xf2,0xb9,0xc8,0x76,0x45,0x3f,0x24,0x64,0x92,
+0x82,0xa2,0x51,0x7f,0x39,0x7b,0x9c,0xe5,0xec,0x87,0xa0,0x8d,0x46,0xf7,0x42,0x54,
+0x1b,0x6d,0x15,0x0e,0xcb,0x4a,0x01,0xf8,0xa0,0x8d,0x40,0x3a,0x86,0xc6,0x3a,0xab,
+0x29,0x68,0x2f,0xc4,0x71,0xa9,0x9b,0x1f,0x22,0x0e,0xa1,0x0f,0xc2,0xb5,0x8f,0xe8,
+0xa5,0xa2,0xe7,0x7e,0x8b,0x00,0x7d,0x90,0x8f,0x46,0x5c,0xbc,0xce,0xe7,0x09,0x96,
+0xc3,0x98,0xc3,0xbe,0x3a,0x7d,0xac,0x78,0x6a,0xa7,0x71,0x2c,0xe6,0x96,0x1b,0xc4,
+0x61,0x5a,0x8b,0x4d,0xf9,0xc6,0xad,0xba,0xcb,0x89,0xc3,0x75,0x45,0x35,0xd5,0x0d,
+0x27,0x5b,0x8a,0x43,0xd2,0x22,0x53,0xa2,0x99,0x66,0x68,0x3d,0xb0,0xa6,0x7a,0xa1,
+0x9f,0xc2,0xe7,0x87,0x96,0xf9,0xdc,0x77,0x30,0x8f,0x64,0x76,0x0d,0xee,0xa1,0x6a,
+0x94,0x1f,0x56,0x27,0x2d,0xe6,0x78,0xfe,0xe3,0x32,0xe5,0xd9,0x0d,0x11,0x87,0x6a,
+0xe0,0x7e,0xc8,0x4b,0xac,0x79,0xe3,0xe3,0xf0,0xc0,0x59,0xde,0xcf,0x36,0xab,0xc7,
+0x88,0xf1,0x00,0x6a,0x86,0x58,0xe6,0x19,0xc8,0xe4,0x7c,0xb6,0x46,0xa5,0xad,0xc4,
+0x61,0x59,0xff,0x9d,0x20,0x19,0x10,0x0b,0x8c,0x29,0xb9,0x64,0xce,0xfe,0xe4,0x3b,
+0x32,0xe5,0x2f,0xee,0xed,0x34,0xe7,0xc7,0x92,0xa0,0x7e,0x08,0xfc,0x10,0xdd,0x0a,
+0x56,0x5f,0x49,0x16,0xb7,0x39,0x39,0xcc,0x06,0x30,0x42,0x05,0x7a,0x06,0x2f,0x91,
+0x53,0x9e,0xdd,0xb0,0x91,0x1c,0x56,0x7a,0x2f,0xe4,0x7d,0xf0,0xae,0xc5,0x76,0x64,
+0x31,0x06,0x9e,0xb3,0x0a,0x87,0x9a,0x3f,0xd5,0xb2,0x02,0x8f,0x55,0x3b,0x36,0x3f,
+0xd4,0xa2,0x52,0xc5,0xdc,0x63,0x81,0x39,0x6c,0x8d,0xfe,0x43,0xb4,0xd6,0x3b,0x9d,
+0x53,0xa1,0xd4,0x36,0x9f,0xa2,0x36,0x2f,0xe4,0xf3,0xc3,0x73,0x71,0x74,0x2f,0xb2,
+0x72,0x26,0x5c,0xe3,0x01,0xcc,0x8d,0xd0,0xb6,0xa9,0x22,0xef,0xec,0xd1,0xbd,0xdc,
+0xa9,0x8a,0x14,0xd5,0xab,0x4c,0x15,0xa7,0xb6,0xfc,0xd5,0x84,0x12,0xf9,0x53,0x5b,
+0xf6,0x67,0x63,0xfb,0x29,0xcb,0x75,0xa7,0xfb,0xd5,0x5a,0x4e,0x15,0x0b,0xf2,0x65,
+0xee,0xb5,0x8d,0xdf,0x18,0x3c,0x70,0xf6,0xc8,0xc2,0x5e,0x2e,0x2d,0xa1,0x5e,0xdd,
+0x4a,0x4c,0x16,0xe4,0x93,0x01,0xd5,0x0c,0xb1,0x0e,0x9c,0x45,0xcf,0x8a,0xe3,0x5e,
+0x13,0x8d,0x26,0x12,0xd3,0x52,0x73,0xb2,0x18,0xd9,0xf5,0xdc,0x74,0x99,0x9b,0xae,
+0x5a,0x08,0xb3,0xe6,0xaf,0x24,0x6d,0x9b,0x74,0xf5,0x4c,0x7d,0xcc,0x45,0x92,0x23,
+0x5f,0xf3,0xfb,0xb3,0x25,0x90,0x51,0x01,0xae,0xb6,0xc9,0xc6,0x6b,0x94,0x95,0xbd,
+0xdc,0xcb,0x9c,0x67,0xca,0xb9,0xf8,0x77,0xa4,0x5a,0xdf,0x97,0x75,0x83,0x9f,0x9b,
+0xd3,0x67,0x39,0x27,0xf9,0x1d,0x2f,0xf2,0xc6,0x60,0x2a,0x5f,0x02,0xdf,0x84,0x79,
+0x54,0x22,0x2c,0xaa,0x65,0x5f,0x70,0xb9,0x1f,0x5f,0x41,0x31,0x5d,0x2a,0x1f,0xf6,
+0xb5,0x4e,0xce,0x68,0x3c,0x3e,0x76,0x6d,0x76,0x66,0x31,0x91,0xcf,0xca,0x28,0x62,
+0x81,0xde,0x3b,0x29,0xbd,0x13,0x50,0xcd,0x90,0xe8,0xc2,0x34,0xcc,0xdf,0x8c,0xf3,
+0xc7,0xa2,0x7c,0xb2,0x7b,0x39,0x9c,0xdb,0x12,0xe5,0x45,0x78,0x78,0xa9,0x75,0x56,
+0x03,0x46,0x19,0xe1,0xc9,0x1a,0x0c,0x64,0x1d,0x06,0xeb,0x7a,0x0c,0x4e,0x6b,0x34,
+0x38,0x95,0x49,0xd7,0x92,0xb6,0x5c,0x32,0x3f,0xf7,0xe0,0x62,0x0f,0xc7,0x11,0xf7,
+0xf7,0xde,0x1d,0x22,0xe5,0xa6,0xe3,0xde,0x6b,0xac,0x81,0xf2,0x59,0xf8,0x58,0xa9,
+0xb3,0xc2,0x36,0x1a,0xef,0xef,0xad,0x5e,0xfc,0x7c,0x4f,0x4c,0x4f,0xb2,0x67,0xd2,
+0x5e,0xe9,0xd3,0xd8,0xed,0x06,0x96,0xef,0x87,0x83,0xc8,0x40,0x75,0xb9,0xf3,0x8d,
+0xc1,0x5b,0x13,0x0f,0x2f,0xed,0x68,0x2e,0x89,0xb2,0xb1,0x15,0x6a,0x1c,0x4d,0x1a,
+0xac,0x5e,0x09,0x15,0x43,0x77,0xf4,0xed,0x4a,0x68,0x21,0xf4,0x5b,0x0d,0x7b,0xdd,
+0x63,0xe1,0x77,0x3a,0x2f,0x77,0xda,0xb7,0x77,0x1c,0xf6,0x4e,0xe5,0x5d,0xf4,0x37,
+0xf6,0xae,0x76,0x9f,0xde,0x70,0x6f,0xb8,0x27,0xdc,0xeb,0x58,0x2a,0xdd,0x4e,0x4a,
+0x6b,0x64,0x18,0x13,0x6a,0xb4,0x9e,0xec,0x7d,0x75,0xf0,0xfb,0x2d,0xf5,0xdd,0xab,
+0x47,0x57,0x8e,0x5f,0xd4,0xca,0x94,0x56,0x7e,0x3c,0xbe,0x92,0xba,0x98,0x92,0x5f,
+0xf8,0xe1,0xa1,0x67,0x3b,0xf8,0x1e,0xdd,0x11,0x3a,0xcf,0x79,0x4f,0x21,0x21,0xa1,
+0xca,0x7a,0xee,0xe0,0xca,0x71,0x5c,0xe6,0xb5,0x6d,0x77,0xbc,0xfb,0xcc,0xf0,0xb9,
+0xc7,0xe3,0xf3,0x09,0xb9,0xef,0xa3,0xa7,0xdc,0x1f,0x7d,0xb0,0x6f,0x7e,0xb8,0x58,
+0xff,0x83,0x14,0x12,0xda,0xf7,0x3a,0xd8,0xf7,0xa1,0xc6,0xe0,0xbc,0xe6,0x89,0x68,
+0x5b,0x19,0x7f,0xf4,0xbd,0xee,0x73,0x8f,0x53,0xd7,0x87,0x4f,0xf5,0xff,0xdd,0x33,
+0xd5,0x1f,0xf9,0x2b,0xbf,0x3c,0x3f,0x3c,0x3f,0xfc,0x7b,0x07,0x1b,0x73,0x9c,0x42,
+0x42,0xfb,0x59,0x1d,0xa1,0x2f,0xf4,0xd8,0x74,0x5e,0x8f,0x4f,0x2f,0x22,0x57,0x4c,
+0x75,0x9f,0xc1,0x24,0xbe,0xf6,0x42,0x4f,0xc5,0x28,0xfa,0x46,0xe8,0xf9,0x04,0xe2,
+0x50,0x3e,0xdc,0xc8,0xa3,0x15,0x12,0xda,0xaf,0xfa,0x7a,0xc7,0x14,0xa5,0x50,0xab,
+0x27,0x0e,0x5f,0x3c,0xfe,0xa1,0x16,0x9f,0x76,0x9f,0xd9,0x38,0x3e,0x3f,0xb0,0xf6,
+0xdd,0xff,0x51,0xa1,0x6d,0x77,0xf9,0xf0,0xfc,0xf0,0xd4,0x30,0xda,0x44,0x64,0x2a,
+0x24,0x14,0x84,0x50,0x2d,0xf1,0x22,0x20,0x71,0x0a,0xc7,0xa7,0x1a,0x89,0x17,0xc7,
+0xff,0xf5,0x52,0xbf,0x43,0x36,0xc7,0x9f,0x1d,0x42,0x04,0x6a,0xcc,0x0e,0xaf,0x0c,
+0xff,0x50,0x44,0xa6,0x42,0x42,0x81,0xe8,0x60,0xdf,0x8a,0x46,0xa0,0x41,0xa1,0x5e,
+0xe6,0xf5,0xf8,0x74,0x77,0xfc,0xef,0x17,0x7e,0x7f,0xd1,0x3a,0xa2,0xe8,0x6a,0x07,
+0xb9,0xd7,0x94,0x88,0x4c,0x85,0x84,0x02,0x53,0x47,0x48,0x3d,0x3a,0xaf,0xf7,0x5e,
+0x58,0x49,0x8c,0x5d,0xe9,0xca,0xcf,0x2c,0x9e,0x07,0xa3,0x61,0x8f,0x6b,0x35,0x4a,
+0x72,0x9f,0x8b,0x28,0x32,0x4d,0xdc,0x68,0xde,0x81,0x0b,0x09,0xed,0x2b,0x7d,0xbd,
+0xe3,0xf9,0x61,0x48,0xa1,0x4e,0xd9,0xf1,0x8d,0xf1,0x53,0x6f,0x65,0xe5,0x48,0x7e,
+0x29,0xc3,0x72,0x29,0x1c,0xed,0x83,0xf7,0xd1,0x4a,0xe2,0x7f,0x8b,0x5e,0x44,0x21,
+0xa1,0x80,0xf4,0xdc,0xc1,0x8b,0x30,0x32,0xd5,0xf7,0xf3,0x89,0x53,0x57,0xa6,0xb6,
+0x54,0x39,0x91,0x5f,0xcb,0x5c,0x98,0xee,0xd1,0xee,0xf5,0x9f,0x0e,0x9a,0x48,0xd5,
+0x28,0x4c,0x0e,0xfc,0x9b,0xa8,0x21,0x0a,0x09,0x05,0xa6,0x3f,0x3d,0xf4,0xfa,0xe1,
+0xcc,0x61,0xf9,0xa8,0x7c,0xf4,0xef,0x8f,0xaa,0x47,0xbf,0xd0,0x8a,0xda,0x57,0xfe,
+0xd1,0x75,0xf5,0xd4,0x56,0x49,0x99,0x94,0x76,0x72,0xef,0xcf,0xfe,0x79,0x6f,0xf9,
+0x68,0xd2,0xe4,0x86,0xc9,0x44,0xb9,0xef,0xf5,0xee,0x66,0x1f,0xb9,0x90,0xd0,0x7e,
+0x12,0x99,0x5b,0xd2,0x11,0xfa,0x5a,0xa8,0x4f,0x2b,0x1d,0xa1,0x5f,0x9c,0xde,0x50,
+0xaf,0xab,0xf3,0x5b,0x65,0x05,0xad,0x98,0x77,0x72,0xe1,0x3f,0x8f,0x27,0x13,0x90,
+0xc3,0xe8,0x40,0xb9,0x7b,0xb9,0xef,0x95,0xe6,0x1e,0xb6,0x90,0xd0,0xbe,0xd1,0xe5,
+0xce,0x5f,0x9c,0x3e,0xb2,0x70,0x6d,0xd6,0xdc,0x77,0x7f,0x7f,0x08,0x71,0x78,0x5d,
+0x5d,0xd9,0x42,0x33,0x27,0xb7,0x73,0xff,0xeb,0xb7,0x92,0x89,0xe4,0x30,0xf5,0xc4,
+0x44,0xb4,0x5f,0xed,0x96,0xfb,0xae,0x34,0xeb,0xa0,0x85,0x84,0xf6,0x95,0xce,0x8f,
+0x7d,0xf3,0x47,0x33,0x8b,0x3b,0xb9,0x49,0xc9,0x9c,0xdd,0x21,0x3c,0x82,0x39,0xd4,
+0x48,0xd4,0xe2,0xd3,0x6f,0x2e,0xfc,0x6d,0xc7,0x14,0xa3,0x70,0xf8,0xf9,0x81,0x2f,
+0xfa,0xe4,0xae,0x97,0xfa,0x1a,0x37,0x53,0x43,0x48,0x68,0xbf,0xea,0xe6,0xd0,0xfb,
+0xb3,0x27,0x17,0xd7,0x32,0x91,0x3c,0x9a,0xc1,0x3c,0xbf,0x05,0xf3,0x3b,0x10,0x3f,
+0xbc,0xae,0x6e,0xa8,0xc9,0xe2,0xed,0x58,0x7f,0x28,0x9a,0x98,0x4a,0x50,0x37,0x1c,
+0x50,0xbb,0x97,0xbb,0x7e,0xee,0x32,0x12,0x55,0x48,0x48,0xa8,0xba,0xbe,0x1d,0xbf,
+0x30,0x7d,0x72,0x71,0x29,0xb3,0xa7,0x39,0x21,0xca,0x44,0x32,0xbf,0x85,0x88,0x63,
+0xeb,0x1f,0xdc,0x1d,0xc2,0x5e,0x88,0xfe,0xe2,0x99,0x93,0xaf,0xf7,0xc1,0x36,0x1a,
+0xb5,0x2b,0xd3,0xfd,0x17,0x2d,0x33,0xc3,0x58,0x48,0xa8,0xfd,0xf4,0xdf,0x3b,0x1f,
+0x68,0x35,0xc2,0x99,0xcc,0x4e,0x0e,0xe5,0x0d,0x40,0x4e,0x48,0x9c,0x6f,0x7e,0x8b,
+0xe4,0x94,0xc2,0x1c,0xa2,0xdb,0x48,0x36,0x8f,0x5f,0x41,0x3d,0x17,0x09,0x1c,0x95,
+0xaa,0xdf,0x58,0x7e,0x62,0xfb,0xbb,0x62,0x3e,0xad,0x90,0x90,0x4f,0x85,0xaf,0x8e,
+0x3d,0xf5,0xfa,0x6b,0x0b,0x1f,0x2c,0x46,0x56,0xd3,0x1a,0x83,0x53,0x5b,0x2b,0xba,
+0x13,0x12,0xea,0x4a,0x0a,0xa6,0xeb,0x8d,0x41,0xec,0x90,0x59,0x99,0x3c,0xf0,0x0a,
+0x8a,0x4c,0x51,0xbf,0x61,0x7f,0xe9,0x89,0x6f,0x0d,0xcb,0x0b,0xc1,0x64,0x43,0x16,
+0x12,0xfa,0xea,0x69,0xe0,0x99,0x5f,0x1d,0xbf,0x38,0xfe,0xe1,0xf8,0xa3,0xd4,0xa3,
+0x57,0xfe,0xfd,0x95,0xa1,0x2b,0xff,0x20,0x0d,0x15,0x37,0xd4,0x5d,0x83,0x43,0xf4,
+0x77,0x57,0xc5,0xeb,0xc6,0x23,0x0e,0x37,0xd4,0x53,0x5b,0xe7,0xc0,0x68,0xef,0xae,
+0xae,0xa9,0x81,0x8b,0xe3,0x5f,0xbe,0x7e,0x71,0x79,0x5d,0x4e,0x49,0xb5,0xe6,0x3e,
+0x11,0x12,0xfa,0x2a,0x2a,0x1f,0x92,0x8f,0xce,0x0f,0x5c,0x1f,0xf8,0xe4,0xf8,0xe3,
+0xd4,0xe3,0xd4,0x6e,0x6a,0x77,0x7c,0x63,0x7c,0xe5,0xf8,0x5f,0xf7,0x7e,0x7e,0x6c,
+0x29,0x53,0x52,0xae,0xeb,0x34,0x6e,0xe8,0x34,0xa2,0x15,0xd4,0x3f,0xeb,0x29,0x2b,
+0xb0,0xbe,0x88,0xf4,0xf6,0x77,0x3f,0x5c,0x3d,0xb5,0x89,0xfb,0xf7,0xdd,0xb3,0x9d,
+0x09,0x09,0x09,0x59,0x75,0x25,0x54,0x3e,0x7c,0x7d,0x60,0x03,0x31,0xf8,0xbd,0x47,
+0x88,0xc2,0xd4,0x86,0xb6,0x7d,0xf1,0x02,0xf9,0xff,0xcd,0xa1,0x8f,0x2f,0x65,0xe5,
+0x53,0x9a,0x07,0x7e,0x72,0x0f,0xc7,0xa2,0x9f,0xc6,0xd8,0x7c,0x8b,0xf8,0xd8,0x52,
+0xa6,0xac,0xe0,0xd8,0x75,0x7e,0x2b,0xb6,0x99,0x96,0xee,0xb7,0xc4,0xda,0x35,0x42,
+0x42,0xed,0x25,0xf9,0xf0,0x5f,0x0e,0x7f,0x32,0xde,0x7d,0x86,0x50,0x88,0xcb,0xb5,
+0x43,0xe6,0x7b,0x8d,0xc6,0x4f,0x4c,0x27,0x4c,0x39,0x23,0xc3,0x23,0x88,0xc0,0x0d,
+0xc3,0x2b,0x51,0x39,0xb5,0x55,0x56,0x5a,0x25,0x27,0xaa,0x90,0x50,0x3b,0xe9,0x4f,
+0x0f,0x3d,0xd6,0xe7,0xda,0x3f,0x32,0x51,0xb8,0x32,0xee,0x92,0xd2,0x5a,0xab,0x25,
+0x5e,0x07,0x04,0xe2,0xf1,0x35,0xc9,0x62,0x41,0x7e,0xcf,0x73,0x9e,0x76,0x21,0xa1,
+0xaf,0xba,0x9e,0x09,0x7d,0x98,0x7a,0x01,0x51,0x98,0x82,0x14,0xee,0xa6,0xe4,0x17,
+0x9c,0xee,0x0d,0xdb,0x5f,0x46,0xe3,0xc9,0xe2,0xae,0x89,0x44,0x34,0xe2,0x34,0x92,
+0x6f,0xad,0x2c,0x90,0x42,0x42,0xed,0x20,0xe9,0x99,0x61,0x07,0x0a,0x77,0x53,0xdf,
+0xb0,0xcc,0x5b,0xba,0x31,0xf8,0xfe,0x6c,0x41,0x9e,0xdf,0x82,0x99,0xd8,0x3f,0xeb,
+0x79,0x70,0x3a,0x91,0x4f,0x16,0x49,0x64,0x3a,0xa5,0xb9,0xe1,0x5b,0xa2,0xc7,0x42,
+0x48,0xc8,0xb3,0x9e,0x47,0xf5,0x42,0x9d,0x42,0x48,0xe2,0xc5,0xf1,0xaf,0xd1,0x7b,
+0x7c,0x7e,0xec,0xc8,0x42,0x49,0xc6,0x6d,0xa6,0x9f,0xdc,0x4b,0xeb,0xab,0x74,0x5d,
+0x9d,0x60,0x3c,0xde,0x8e,0xdd,0x9a,0x40,0xeb,0xbc,0x5d,0x57,0xd1,0xfa,0x00,0x4e,
+0x99,0x6b,0x84,0x84,0x84,0xaa,0xe9,0xd7,0x3a,0x1e,0x7f,0x4f,0x2b,0x29,0x44,0xe2,
+0x23,0x83,0xc6,0xc7,0xa9,0x8d,0xd4,0x4f,0xf5,0xd1,0xa1,0x2f,0x8e,0x2d,0x65,0x92,
+0x46,0x1f,0xe2,0x86,0x31,0xa6,0x06,0xad,0xd9,0x30,0x1a,0xbf,0xae,0x11,0x69,0xee,
+0x9d,0xb8,0xdc,0x19,0x1e,0xe9,0xfc,0xd1,0x6f,0xbc,0x2e,0xa6,0xe1,0x0b,0x09,0x79,
+0x55,0xe7,0x61,0xd4,0x4a,0x8a,0x4b,0xf7,0xe4,0xe3,0xd4,0x8f,0xc7,0xe5,0x17,0x4e,
+0x1c,0xba,0x83,0xff,0xb7,0x80,0xda,0x42,0x1f,0xdf,0xfb,0xe4,0x1e,0xe9,0xc9,0xdf,
+0x50,0xf1,0x38,0x99,0x57,0xf5,0x7e,0xfc,0x0d,0xf5,0xbc,0x69,0xbd,0xc6,0xd1,0x50,
+0xaa,0x6f,0x2a,0xf1,0xc5,0xd1,0x7f,0x7b,0xe6,0x7c,0xc7,0xd7,0x1c,0x5e,0x4b,0x48,
+0x48,0xc8,0x59,0x7f,0xa0,0xb7,0x94,0x22,0x16,0xa7,0xc6,0x5f,0x3a,0xfa,0x2f,0x4f,
+0xc1,0xb9,0x4a,0xb8,0xcf,0xf0,0x13,0xca,0xe1,0x27,0x2a,0x59,0x15,0xf0,0x5c,0x1c,
+0x73,0x38,0x55,0x1c,0xa5,0x51,0xe8,0xef,0x1d,0x4c,0x0e,0xe3,0x4c,0xfc,0xa8,0x44,
+0x87,0x0f,0xf6,0xbd,0x29,0x68,0x14,0x12,0xe2,0xd0,0xaf,0x75,0x74,0x9f,0xd9,0x4d,
+0x7d,0xeb,0xf8,0xc3,0x5f,0xff,0x9d,0x5f,0xb2,0xff,0xf7,0xd6,0x44,0x5a,0x42,0x2d,
+0xa2,0x8f,0xef,0xe1,0x76,0x98,0x58,0x91,0xac,0x1a,0x8e,0xfd,0x10,0x39,0x64,0x41,
+0xef,0xd5,0xbf,0x12,0x7a,0xfd,0xf0,0x8a,0x9e,0x89,0x9f,0x94,0x95,0xe3,0x1b,0xc7,
+0x3f,0x14,0x34,0x0a,0x09,0x71,0xa8,0x23,0xf4,0x2f,0x4f,0xdd,0xa9,0xf8,0xdf,0x73,
+0xf1,0x54,0x1e,0x47,0xa6,0xb8,0x7e,0xc8,0xa2,0x50,0xec,0x87,0xd7,0xf5,0x11,0xa7,
+0x4b,0x99,0xf7,0x3a,0x9e,0x1f,0xc6,0x59,0xf8,0x19,0x85,0xb8,0x5c,0xd7,0x68,0xdc,
+0x38,0x9e,0x1c,0x7e,0xa9,0x4f,0x0c,0x74,0x13,0x12,0xf2,0xa7,0x63,0xe1,0xb5,0x4c,
+0x49,0x9e,0xdf,0x42,0x35,0xc4,0x5d,0x53,0xab,0x0c,0xf1,0x43,0x5c,0x6b,0x3c,0x75,
+0x65,0x3e,0x81,0xe9,0x63,0x04,0xae,0x00,0x16,0x77,0xb5,0xdb,0xbf,0x2e,0x9a,0x6f,
+0x84,0x84,0x7c,0xaa,0x73,0x01,0xd7,0x10,0x1f,0xdf,0xfb,0xcd,0xcd,0xbf,0xf9,0x0f,
+0xec,0x76,0xe4,0x87,0xd8,0x23,0xf5,0x76,0xd4,0xad,0x7f,0xff,0xa3,0x53,0x89,0x79,
+0x47,0x0a,0x91,0x1f,0xca,0x87,0xdd,0x46,0xe6,0x08,0x09,0x09,0x55,0xd6,0xc0,0xd9,
+0xb4,0x14,0x2b,0xee,0xde,0xfb,0x44,0xfd,0xcd,0xf4,0xca,0xf1,0x0b,0x74,0xbc,0xe9,
+0x68,0x7c,0x43,0x7d,0xfa,0xfe,0xe3,0x7b,0xa8,0x20,0x4a,0xff,0x5b,0xf1,0xc7,0xe3,
+0xc9,0x81,0x29,0x94,0x1b,0x43,0x5f,0xef,0x09,0x97,0x95,0xe1,0xeb,0x1a,0x9b,0x3f,
+0x3b,0x54,0xed,0x15,0x84,0x84,0x84,0xdc,0x74,0x7f,0x68,0x52,0x42,0x35,0xc4,0xdd,
+0xd5,0x8d,0xe3,0xa8,0x77,0x7f,0xf6,0x28,0x6e,0x73,0x39,0x17,0xdf,0xbd,0xf7,0xf4,
+0xfd,0xee,0x7f,0xd4,0x37,0xed,0xef,0xf0,0xfd,0x43,0x05,0xb5,0x4b,0xed,0xfa,0xa2,
+0xaf,0xdc,0x17,0xed,0xc7,0x25,0x39,0x90,0x1c,0x90,0xfb,0x78,0x57,0x11,0x16,0x12,
+0x12,0xaa,0xa4,0x77,0x63,0x7b,0xb9,0x92,0xf2,0x0f,0xf9,0x8d,0xf1,0xdd,0x71,0x3c,
+0xce,0xe6,0x79,0xbd,0xa6,0x77,0x73,0xe8,0xd4,0xd6,0xbc,0x31,0x57,0x7f,0x43,0x1f,
+0x65,0xf3,0xf8,0xde,0xd4,0xf2,0xeb,0x4f,0x2c,0x3f,0xb1,0xdc,0xbd,0xdc,0x2d,0x6b,
+0x45,0xd5,0xca,0x0f,0x7f,0xb9,0xd9,0xc7,0x2f,0x24,0xb4,0x3f,0x74,0x72,0x31,0x2b,
+0xfd,0x38,0xb5,0x32,0x0c,0xe7,0x61,0xfc,0xae,0x46,0xe2,0x81,0xb3,0xd7,0x66,0x8f,
+0x2c,0xa0,0x4c,0x52,0x89,0x7c,0x5a,0x2a,0xc8,0xb1,0xcd,0xa9,0xe2,0xb7,0x96,0xff,
+0xec,0x85,0xa3,0xdf,0x78,0xa9,0xeb,0xa5,0xae,0xd9,0xee,0x9f,0x1f,0xba,0xdf,0xec,
+0x43,0x17,0x12,0xda,0x37,0x7a,0x6b,0xf6,0x8b,0xc5,0xe8,0x81,0x95,0xe3,0x8c,0xc3,
+0xc7,0xa9,0x8f,0x2d,0x19,0x11,0x8f,0x85,0x3f,0xeb,0x79,0x63,0x30,0x3c,0xf2,0xe0,
+0xf4,0xdf,0x4e,0x8c,0xff,0xc6,0x89,0x43,0x07,0x0e,0xfd,0x73,0x73,0x0e,0x56,0x48,
+0x68,0x9f,0xea,0xfc,0xc4,0xe4,0x2b,0xe5,0x27,0xe6,0x87,0x77,0xc7,0xc9,0x28,0xf0,
+0x47,0xc6,0xd8,0x53,0x21,0x21,0xa1,0x46,0x69,0x34,0xfe,0xff,0xfe,0x4b,0xf9,0x89,
+0xa9,0x04,0xa9,0x1f,0x3e,0x72,0xf0,0x43,0x21,0x21,0xa1,0xfa,0xea,0x58,0x78,0xe2,
+0xa8,0xfa,0x8d,0xe4,0xc0,0xc6,0x38,0x99,0x8f,0xf1,0x58,0xf8,0xa1,0x90,0x50,0xc3,
+0xf5,0xf3,0x5f,0x57,0xbb,0x62,0xfd,0x2b,0x7a,0x1e,0xb7,0xc7,0xc2,0x0f,0x85,0x84,
+0x9a,0xa2,0x37,0x9f,0x52,0xfb,0xa2,0x4f,0xcf,0x0f,0x3f,0x4a,0x61,0x12,0xbb,0x27,
+0xaf,0x09,0x0e,0x85,0x84,0x1a,0xae,0x9f,0x3d,0x13,0x7b,0x7a,0x3e,0xb1,0x4b,0x38,
+0x3c,0xf3,0x96,0x18,0x21,0x23,0x24,0xd4,0x04,0x1d,0xec,0x3e,0x35,0xb0,0x3b,0x4e,
+0xfc,0x50,0x70,0x28,0x24,0xd4,0x1c,0xfd,0xdd,0xa1,0xdd,0xf1,0xee,0x49,0x94,0x41,
+0xa3,0xfb,0xcc,0x1f,0x09,0x0e,0x85,0x84,0x9a,0xa4,0x0b,0x87,0x76,0x53,0x28,0xa3,
+0x54,0xf7,0x99,0xc3,0x82,0x43,0x21,0xa1,0xa6,0xe9,0x0f,0x7f,0xe9,0xe2,0xf8,0xf0,
+0x99,0xa7,0x05,0x87,0x42,0x42,0x4d,0x55,0x47,0x68,0xf6,0xe8,0xb0,0xe0,0x50,0x48,
+0xa8,0xed,0xf5,0xff,0x01,0xd1,0x0a,0xff,0xc9,0xa6,0xee,0x01,0x00};
+#endif
diff --git a/lib/uuid.c b/lib/uuid.c
index c48bf38362..f6b4423551 100644
--- a/lib/uuid.c
+++ b/lib/uuid.c
@@ -4,21 +4,58 @@
  * SPDX-License-Identifier:	GPL-2.0+
  */
 
+#include <common.h>
 #include <linux/ctype.h>
-#include "common.h"
+#include <errno.h>
+#include <common.h>
+#include <asm/io.h>
+#include <part_efi.h>
+#include <malloc.h>
 
 /*
- * This is what a UUID string looks like.
+ * UUID - Universally Unique IDentifier - 128 bits unique number.
+ *        There are 5 versions and one variant of UUID defined by RFC4122
+ *        specification. A UUID contains a set of fields. The set varies
+ *        depending on the version of the UUID, as shown below:
+ *        - time, MAC address(v1),
+ *        - user ID(v2),
+ *        - MD5 of name or URL(v3),
+ *        - random data(v4),
+ *        - SHA-1 of name or URL(v5),
  *
- * x is a hexadecimal character. fields are separated by '-'s. When converting
- * to a binary UUID, le means the field should be converted to little endian,
- * and be means it should be converted to big endian.
+ * Layout of UUID:
+ * timestamp - 60-bit: time_low, time_mid, time_hi_and_version
+ * version   - 4 bit (bit 4 through 7 of the time_hi_and_version)
+ * clock seq - 14 bit: clock_seq_hi_and_reserved, clock_seq_low
+ * variant:  - bit 6 and 7 of clock_seq_hi_and_reserved
+ * node      - 48 bit
+ *
+ * source: https://www.ietf.org/rfc/rfc4122.txt
+ *
+ * UUID binary format (16 bytes):
+ *
+ * 4B-2B-2B-2B-6B (big endian - network byte order)
+ *
+ * UUID string is 36 length of characters (36 bytes):
  *
  * 0        9    14   19   24
  * xxxxxxxx-xxxx-xxxx-xxxx-xxxxxxxxxxxx
+ *    be     be   be   be       be
+ *
+ * where x is a hexadecimal character. Fields are separated by '-'s.
+ * When converting to a binary UUID, le means the field should be converted
+ * to little endian and be means it should be converted to big endian.
+ *
+ * UUID is also used as GUID (Globally Unique Identifier) with the same binary
+ * format but it differs in string format like below.
+ *
+ * GUID:
+ * 0        9    14   19   24
+ * xxxxxxxx-xxxx-xxxx-xxxx-xxxxxxxxxxxx
  *    le     le   le   be       be
+ *
+ * GUID is used e.g. in GPT (GUID Partition Table) as a partiions unique id.
  */
-
 int uuid_str_valid(const char *uuid)
 {
 	int i, valid;
@@ -37,33 +74,182 @@ int uuid_str_valid(const char *uuid)
 		}
 	}
 
-	if (i != 36 || !valid)
+	if (i != UUID_STR_LEN || !valid)
 		return 0;
 
 	return 1;
 }
 
-void uuid_str_to_bin(const char *uuid, unsigned char *out)
+/*
+ * uuid_str_to_bin() - convert string UUID or GUID to big endian binary data.
+ *
+ * @param uuid_str - pointer to UUID or GUID string [37B]
+ * @param uuid_bin - pointer to allocated array for big endian output [16B]
+ * @str_format     - UUID string format: 0 - UUID; 1 - GUID
+ */
+int uuid_str_to_bin(char *uuid_str, unsigned char *uuid_bin, int str_format)
 {
 	uint16_t tmp16;
 	uint32_t tmp32;
 	uint64_t tmp64;
 
-	if (!uuid || !out)
-		return;
+	if (!uuid_str_valid(uuid_str))
+		return -EINVAL;
 
-	tmp32 = cpu_to_le32(simple_strtoul(uuid, NULL, 16));
-	memcpy(out, &tmp32, 4);
+	if (str_format == UUID_STR_FORMAT_STD) {
+		tmp32 = cpu_to_be32(simple_strtoul(uuid_str, NULL, 16));
+		memcpy(uuid_bin, &tmp32, 4);
 
-	tmp16 = cpu_to_le16(simple_strtoul(uuid + 9, NULL, 16));
-	memcpy(out + 4, &tmp16, 2);
+		tmp16 = cpu_to_be16(simple_strtoul(uuid_str + 9, NULL, 16));
+		memcpy(uuid_bin + 4, &tmp16, 2);
 
-	tmp16 = cpu_to_le16(simple_strtoul(uuid + 14, NULL, 16));
-	memcpy(out + 6, &tmp16, 2);
+		tmp16 = cpu_to_be16(simple_strtoul(uuid_str + 14, NULL, 16));
+		memcpy(uuid_bin + 6, &tmp16, 2);
+	} else {
+		tmp32 = cpu_to_le32(simple_strtoul(uuid_str, NULL, 16));
+		memcpy(uuid_bin, &tmp32, 4);
 
-	tmp16 = cpu_to_be16(simple_strtoul(uuid + 19, NULL, 16));
-	memcpy(out + 8, &tmp16, 2);
+		tmp16 = cpu_to_le16(simple_strtoul(uuid_str + 9, NULL, 16));
+		memcpy(uuid_bin + 4, &tmp16, 2);
 
-	tmp64 = cpu_to_be64(simple_strtoull(uuid + 24, NULL, 16));
-	memcpy(out + 10, (char *)&tmp64 + 2, 6);
+		tmp16 = cpu_to_le16(simple_strtoul(uuid_str + 14, NULL, 16));
+		memcpy(uuid_bin + 6, &tmp16, 2);
+	}
+
+	tmp16 = cpu_to_be16(simple_strtoul(uuid_str + 19, NULL, 16));
+	memcpy(uuid_bin + 8, &tmp16, 2);
+
+	tmp64 = cpu_to_be64(simple_strtoull(uuid_str + 24, NULL, 16));
+	memcpy(uuid_bin + 10, (char *)&tmp64 + 2, 6);
+
+	return 0;
 }
+
+/*
+ * uuid_bin_to_str() - convert big endian binary data to string UUID or GUID.
+ *
+ * @param uuid_bin - pointer to binary data of UUID (big endian) [16B]
+ * @param uuid_str - pointer to allocated array for output string [37B]
+ * @str_format     - UUID string format: 0 - UUID; 1 - GUID
+ */
+void uuid_bin_to_str(unsigned char *uuid_bin, char *uuid_str, int str_format)
+{
+	const u8 uuid_char_order[UUID_BIN_LEN] = {0, 1, 2, 3, 4, 5, 6, 7, 8,
+						  9, 10, 11, 12, 13, 14, 15};
+	const u8 guid_char_order[UUID_BIN_LEN] = {3, 2, 1, 0, 5, 4, 7, 6, 8,
+						  9, 10, 11, 12, 13, 14, 15};
+	const u8 *char_order;
+	int i;
+
+	/*
+	 * UUID and GUID bin data - always in big endian:
+	 * 4B-2B-2B-2B-6B
+	 * be be be be be
+	 */
+	if (str_format == UUID_STR_FORMAT_STD)
+		char_order = uuid_char_order;
+	else
+		char_order = guid_char_order;
+
+	for (i = 0; i < 16; i++) {
+		sprintf(uuid_str, "%02x", uuid_bin[char_order[i]]);
+		uuid_str += 2;
+		switch (i) {
+		case 3:
+		case 5:
+		case 7:
+		case 9:
+			*uuid_str++ = '-';
+			break;
+		}
+	}
+}
+
+/*
+ * gen_rand_uuid() - this function generates a random binary UUID version 4.
+ *                   In this version all fields beside 4 bits of version and
+ *                   2 bits of variant are randomly generated.
+ *
+ * @param uuid_bin - pointer to allocated array [16B]. Output is in big endian.
+*/
+#if defined(CONFIG_RANDOM_UUID) || defined(CONFIG_CMD_UUID)
+void gen_rand_uuid(unsigned char *uuid_bin)
+{
+	struct uuid uuid;
+	unsigned int *ptr = (unsigned int *)&uuid;
+	int i;
+
+	/* Set all fields randomly */
+	for (i = 0; i < sizeof(struct uuid) / sizeof(*ptr); i++)
+		*(ptr + i) = cpu_to_be32(rand());
+
+	clrsetbits_be16(&uuid.time_hi_and_version,
+			UUID_VERSION_MASK,
+			UUID_VERSION << UUID_VERSION_SHIFT);
+
+	clrsetbits_8(&uuid.clock_seq_hi_and_reserved,
+		     UUID_VARIANT_MASK,
+		     UUID_VARIANT << UUID_VARIANT_SHIFT);
+
+	memcpy(uuid_bin, &uuid, sizeof(struct uuid));
+}
+
+/*
+ * gen_rand_uuid_str() - this function generates UUID v4 (random) in two string
+ *                       formats UUID or GUID.
+ *
+ * @param uuid_str - pointer to allocated array [37B].
+ * @param          - uuid output type: UUID - 0, GUID - 1
+ */
+void gen_rand_uuid_str(char *uuid_str, int str_format)
+{
+	unsigned char uuid_bin[UUID_BIN_LEN];
+
+	/* Generate UUID (big endian) */
+	gen_rand_uuid(uuid_bin);
+
+	/* Convert UUID bin to UUID or GUID formated STRING  */
+	uuid_bin_to_str(uuid_bin, uuid_str, str_format);
+}
+
+#ifdef CONFIG_CMD_UUID
+int do_uuid(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	char uuid[UUID_STR_LEN + 1];
+	int str_format;
+
+	if (!strcmp(argv[0], "uuid"))
+		str_format = UUID_STR_FORMAT_STD;
+	else
+		str_format = UUID_STR_FORMAT_GUID;
+
+	if (argc > 2)
+		return CMD_RET_USAGE;
+
+	gen_rand_uuid_str(uuid, str_format);
+
+	if (argc == 1)
+		printf("%s\n", uuid);
+	else
+		setenv(argv[1], uuid);
+
+	return CMD_RET_SUCCESS;
+}
+
+U_BOOT_CMD(uuid, CONFIG_SYS_MAXARGS, 1, do_uuid,
+	   "UUID - generate random Universally Unique Identifier",
+	   "[<varname>]\n"
+	   "Argument:\n"
+	   "varname: for set result in a environment variable\n"
+	   "e.g. uuid uuid_env"
+);
+
+U_BOOT_CMD(guid, CONFIG_SYS_MAXARGS, 1, do_uuid,
+	   "GUID - generate Globally Unique Identifier based on random UUID",
+	   "[<varname>]\n"
+	   "Argument:\n"
+	   "varname: for set result in a environment variable\n"
+	   "e.g. guid guid_env"
+);
+#endif /* CONFIG_CMD_UUID */
+#endif /* CONFIG_RANDOM_UUID || CONFIG_CMD_UUID */
diff --git a/lib/vsprintf.c b/lib/vsprintf.c
index 82e5c13653..60874dae3e 100644
--- a/lib/vsprintf.c
+++ b/lib/vsprintf.c
@@ -750,6 +750,7 @@ repeat:
 		ADDCH(str, '\0');
 		if (str > end)
 			end[-1] = '\0';
+		--str;
 	}
 #else
 	*str = '\0';
diff --git a/lib/zlib/Makefile b/lib/zlib/Makefile
index b69e2348f2..2fba95f438 100644
--- a/lib/zlib/Makefile
+++ b/lib/zlib/Makefile
@@ -5,24 +5,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)libz.o
-
-COBJS-$(CONFIG_ZLIB) += zlib.o
-
-COBJS	:= $(COBJS-y)
-SRCS	:= $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y += zlib.o
diff --git a/mkconfig b/mkconfig
index 1d06c8ebfe..cd911a9dc7 100755
--- a/mkconfig
+++ b/mkconfig
@@ -23,7 +23,7 @@ options=""
 
 if [ \( $# -eq 2 \) -a \( "$1" = "-A" \) ] ; then
 	# Automatic mode
-	line=`awk '($0 !~ /^#/ && $7 ~ /^'"$2"'$/) { print $1, $2, $3, $4, $5, $6, $7, $8 }' boards.cfg`
+	line=`awk '($0 !~ /^#/ && $7 ~ /^'"$2"'$/) { print $1, $2, $3, $4, $5, $6, $7, $8 }' $srctree/boards.cfg`
 	if [ -z "$line" ] ; then
 		echo "make: *** No rule to make target \`$2_config'.  Stop." >&2
 		exit 1
@@ -55,7 +55,9 @@ CONFIG_NAME="${7%_config}"
 arch="$2"
 cpu=`echo $3 | awk 'BEGIN {FS = ":"} ; {print $1}'`
 spl_cpu=`echo $3 | awk 'BEGIN {FS = ":"} ; {print $2}'`
-if [ "$6" = "-" ] ; then
+if [ "$6" = "<none>" ] ; then
+	board=
+elif [ "$6" = "-" ] ; then
 	board=${BOARD_NAME}
 else
 	board="$6"
@@ -85,6 +87,13 @@ if [ "${ARCH}" -a "${ARCH}" != "${arch}" ]; then
 	exit 1
 fi
 
+#
+# Test above needed aarch64, now we need arm
+#
+if [ "${arch}" = "aarch64" ]; then
+	arch="arm"
+fi
+
 if [ "$options" ] ; then
 	echo "Configuring for ${BOARD_NAME} - Board: ${CONFIG_NAME}, Options: ${options}"
 else
@@ -94,19 +103,13 @@ fi
 #
 # Create link to architecture specific headers
 #
-if [ "$SRCTREE" != "$OBJTREE" ] ; then
-	mkdir -p ${OBJTREE}/include
-	mkdir -p ${OBJTREE}/include2
-	cd ${OBJTREE}/include2
-	rm -f asm
-	ln -s ${SRCTREE}/arch/${arch}/include/asm asm
-	LNPREFIX=${SRCTREE}/arch/${arch}/include/asm/
-	cd ../include
+if [ -n "$KBUILD_SRC" ] ; then
+	mkdir -p ${objtree}/include
+	LNPREFIX=${srctree}/arch/${arch}/include/asm/
+	cd ${objtree}/include
 	mkdir -p asm
 else
-	cd ./include
-	rm -f asm
-	ln -s ../arch/${arch}/include/asm asm
+	cd arch/${arch}/include
 fi
 
 rm -f asm/arch
@@ -122,6 +125,10 @@ if [ "${arch}" = "arm" ] ; then
 	ln -s ${LNPREFIX}proc-armv asm/proc
 fi
 
+if [ -z "$KBUILD_SRC" ] ; then
+	cd ${srctree}/include
+fi
+
 #
 # Create include file for Make
 #
@@ -172,8 +179,8 @@ echo "#define CONFIG_SYS_BOARD \"${board}\"" >> config.h
 
 [ "${soc}"    ] && echo "#define CONFIG_SYS_SOC    \"${soc}\""    >> config.h
 
+[ "${board}"  ] && echo "#define CONFIG_BOARDDIR board/$BOARDDIR" >> config.h
 cat << EOF >> config.h
-#define CONFIG_BOARDDIR board/$BOARDDIR
 #include <config_cmd_defaults.h>
 #include <config_defaults.h>
 #include <configs/${CONFIG_NAME}.h>
diff --git a/nand_spl/board/amcc/acadia/Makefile b/nand_spl/board/amcc/acadia/Makefile
deleted file mode 100644
index 20459c92e2..0000000000
--- a/nand_spl/board/amcc/acadia/Makefile
+++ /dev/null
@@ -1,106 +0,0 @@
-#
-# (C) Copyright 2007
-# Stefan Roese, DENX Software Engineering, sr@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-include $(TOPDIR)/config.mk
-include $(TOPDIR)/nand_spl/board/$(BOARDDIR)/config.mk
-
-nandobj	:= $(OBJTREE)/nand_spl/
-
-LDSCRIPT= $(TOPDIR)/nand_spl/board/$(BOARDDIR)/u-boot.lds
-LDFLAGS := -T $(nandobj)u-boot.lds -Ttext $(CONFIG_SYS_TEXT_BASE) $(LDFLAGS) \
-	   $(LDFLAGS_FINAL)
-AFLAGS	+= -DCONFIG_NAND_SPL
-CFLAGS	+= -DCONFIG_NAND_SPL
-
-SOBJS	= start.o resetvec.o cache.o
-COBJS	= gpio.o nand_boot.o nand_ecc.o memory.o ndfc.o pll.o
-
-SRCS	:= $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c))
-OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS))
-__OBJS	:= $(SOBJS) $(COBJS)
-LNDIR	:= $(nandobj)board/$(BOARDDIR)
-
-ALL	= $(nandobj)u-boot-spl $(nandobj)u-boot-spl.bin $(nandobj)u-boot-spl-16k.bin \
-	$(nandobj)System.map
-
-all:	$(obj).depend $(ALL)
-
-$(nandobj)u-boot-spl-16k.bin: $(nandobj)u-boot-spl
-	$(OBJCOPY) ${OBJCFLAGS} --pad-to=$(PAD_TO) -O binary $< $@
-
-$(nandobj)u-boot-spl.bin:	$(nandobj)u-boot-spl
-	$(OBJCOPY) ${OBJCFLAGS} -O binary $< $@
-
-$(nandobj)u-boot-spl:	$(OBJS) $(nandobj)u-boot.lds
-	cd $(LNDIR) && $(LD) $(LDFLAGS) $(__OBJS) $(PLATFORM_LIBS) \
-		-Map $(nandobj)u-boot-spl.map \
-		-o $(nandobj)u-boot-spl
-
-$(nandobj)System.map:	$(nandobj)u-boot-spl
-		@$(NM) $< | \
-		grep -v '\(compiled\)\|\(\.o$$\)\|\( [aUw] \)\|\(\.\.ng$$\)\|\(LASH[RL]DI\)' | \
-		sort > $(nandobj)System.map
-
-$(nandobj)u-boot.lds: $(LDSCRIPT)
-	$(CPP) $(CPPFLAGS) $(LDPPFLAGS) -ansi -D__ASSEMBLY__ -P - <$^ >$@
-
-# create symbolic links for common files
-
-# from cpu directory
-$(obj)cache.S:
-	@rm -f $(obj)cache.S
-	ln -s $(SRCTREE)/arch/powerpc/cpu/ppc4xx/cache.S $(obj)cache.S
-
-$(obj)gpio.c:
-	@rm -f $(obj)gpio.c
-	ln -s $(SRCTREE)/arch/powerpc/cpu/ppc4xx/gpio.c $(obj)gpio.c
-
-$(obj)ndfc.c:
-	@rm -f $(obj)ndfc.c
-	ln -s $(SRCTREE)/drivers/mtd/nand/ndfc.c $(obj)ndfc.c
-
-$(obj)resetvec.S:
-	@rm -f $(obj)resetvec.S
-	ln -s $(SRCTREE)/arch/powerpc/cpu/ppc4xx/resetvec.S $(obj)resetvec.S
-
-$(obj)start.S:
-	@rm -f $(obj)start.S
-	ln -s $(SRCTREE)/arch/powerpc/cpu/ppc4xx/start.S $(obj)start.S
-
-# from board directory
-$(obj)memory.c:
-	@rm -f $(obj)memory.c
-	ln -s $(SRCTREE)/board/amcc/acadia/memory.c $(obj)memory.c
-
-$(obj)pll.c:
-	@rm -f $(obj)pll.c
-	ln -s $(SRCTREE)/board/amcc/acadia/pll.c $(obj)pll.c
-
-# from nand_spl directory
-$(obj)nand_boot.c:
-	@rm -f $(obj)nand_boot.c
-	ln -s $(SRCTREE)/nand_spl/nand_boot.c $(obj)nand_boot.c
-
-# from drivers/mtd/nand directory
-$(obj)nand_ecc.c:
-	@rm -f $(obj)nand_ecc.c
-	ln -s $(SRCTREE)/drivers/mtd/nand/nand_ecc.c $(obj)nand_ecc.c
-
-#########################################################################
-
-$(obj)%.o:	$(obj)%.S
-	$(CC) $(AFLAGS) -c -o $@ $<
-
-$(obj)%.o:	$(obj)%.c
-	$(CC) $(CFLAGS) -c -o $@ $<
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
diff --git a/nand_spl/board/amcc/acadia/config.mk b/nand_spl/board/amcc/acadia/config.mk
deleted file mode 100644
index d9ff10d5c2..0000000000
--- a/nand_spl/board/amcc/acadia/config.mk
+++ /dev/null
@@ -1,31 +0,0 @@
-#
-# (C) Copyright 2007
-# Stefan Roese, DENX Software Engineering, sr@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-#
-# AMCC 405EZ Reference Platform (Acadia) board
-#
-
-#
-# CONFIG_SYS_TEXT_BASE for SPL:
-#
-# On 4xx platforms the SPL is located at 0xfffff000...0xffffffff,
-# in the last 4kBytes of memory space in cache.
-# We will copy this SPL into internal SRAM in start.S. So we set
-# CONFIG_SYS_TEXT_BASE to starting address in internal SRAM here.
-#
-CONFIG_SYS_TEXT_BASE = 0xf8004000
-
-# PAD_TO used to generate a 16kByte binary needed for the combined image
-# -> PAD_TO = CONFIG_SYS_TEXT_BASE + 0x4000
-PAD_TO	= 0xf8008000
-
-ifeq ($(debug),1)
-PLATFORM_CPPFLAGS += -DDEBUG
-endif
-
-ifeq ($(dbcr),1)
-PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8cff0000
-endif
diff --git a/nand_spl/board/amcc/acadia/u-boot.lds b/nand_spl/board/amcc/acadia/u-boot.lds
deleted file mode 100644
index a7dac121d3..0000000000
--- a/nand_spl/board/amcc/acadia/u-boot.lds
+++ /dev/null
@@ -1,48 +0,0 @@
-/*
- * (C) Copyright 2007
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-OUTPUT_ARCH(powerpc:common)
-SECTIONS
-{
-  .resetvec 0xf8004ffc :
-  {
-    KEEP(*(.resetvec))
-  } = 0xffff
-
-  .text      :
-  {
-    start.o	(.text)
-    nand_boot.o	(.text)
-    ndfc.o	(.text)
-
-    *(.text)
-    *(.fixup)
-  }
-  _etext = .;
-
-  .data    :
-  {
-    *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
-    *(.data*)
-    *(.sdata*)
-    __got2_start = .;
-    *(.got2)
-    __got2_end = .;
-  }
-
-  _edata  =  .;
-
-  __bss_start = .;
-  .bss (NOLOAD)       :
-  {
-   *(.sbss)
-   *(.bss)
-   . = ALIGN(4);
-  }
-
-  __bss_end = . ;
-}
diff --git a/nand_spl/board/amcc/bamboo/Makefile b/nand_spl/board/amcc/bamboo/Makefile
deleted file mode 100644
index ca3dab4f25..0000000000
--- a/nand_spl/board/amcc/bamboo/Makefile
+++ /dev/null
@@ -1,94 +0,0 @@
-#
-# (C) Copyright 2007
-# Stefan Roese, DENX Software Engineering, sr@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-include $(TOPDIR)/config.mk
-include $(TOPDIR)/nand_spl/board/$(BOARDDIR)/config.mk
-
-nandobj	:= $(OBJTREE)/nand_spl/
-
-LDSCRIPT= $(TOPDIR)/nand_spl/board/$(BOARDDIR)/u-boot.lds
-LDFLAGS := -T $(nandobj)u-boot.lds -Ttext $(CONFIG_SYS_TEXT_BASE) $(LDFLAGS) \
-	   $(LDFLAGS_FINAL)
-AFLAGS	+= -DCONFIG_NAND_SPL
-CFLAGS	+= -DCONFIG_NAND_SPL
-
-SOBJS	= start.o init.o resetvec.o
-COBJS	= nand_boot.o nand_ecc.o ndfc.o sdram.o
-
-SRCS	:= $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c))
-OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS))
-__OBJS	:= $(SOBJS) $(COBJS)
-LNDIR	:= $(nandobj)board/$(BOARDDIR)
-
-ALL	= $(nandobj)u-boot-spl $(nandobj)u-boot-spl.bin $(nandobj)u-boot-spl-16k.bin
-
-all:	$(obj).depend $(ALL)
-
-$(nandobj)u-boot-spl-16k.bin: $(nandobj)u-boot-spl
-	$(OBJCOPY) ${OBJCFLAGS} --pad-to=$(PAD_TO) -O binary $< $@
-
-$(nandobj)u-boot-spl.bin:	$(nandobj)u-boot-spl
-	$(OBJCOPY) ${OBJCFLAGS} -O binary $< $@
-
-$(nandobj)u-boot-spl:	$(OBJS) $(nandobj)u-boot.lds
-	cd $(LNDIR) && $(LD) $(LDFLAGS) $(__OBJS) $(PLATFORM_LIBS) \
-		-Map $(nandobj)u-boot-spl.map \
-		-o $(nandobj)u-boot-spl
-
-$(nandobj)u-boot.lds: $(LDSCRIPT)
-	$(CPP) $(CPPFLAGS) $(LDPPFLAGS) -ansi -D__ASSEMBLY__ -P - <$^ >$@
-
-# create symbolic links for common files
-
-# from cpu directory
-$(obj)ndfc.c:
-	@rm -f $(obj)ndfc.c
-	ln -s $(SRCTREE)/drivers/mtd/nand/ndfc.c $(obj)ndfc.c
-
-$(obj)resetvec.S:
-	@rm -f $(obj)resetvec.S
-	ln -s $(SRCTREE)/arch/powerpc/cpu/ppc4xx/resetvec.S $(obj)resetvec.S
-
-$(obj)start.S:
-	@rm -f $(obj)start.S
-	ln -s $(SRCTREE)/arch/powerpc/cpu/ppc4xx/start.S $(obj)start.S
-
-# from board directory
-$(obj)init.S:
-	@rm -f $(obj)init.S
-	ln -s $(SRCTREE)/board/amcc/bamboo/init.S $(obj)init.S
-
-# from nand_spl directory
-$(obj)nand_boot.c:
-	@rm -f $(obj)nand_boot.c
-	ln -s $(SRCTREE)/nand_spl/nand_boot.c $(obj)nand_boot.c
-
-# from drivers/mtd/nand directory
-$(obj)nand_ecc.c:
-	@rm -f $(obj)nand_ecc.c
-	ln -s $(SRCTREE)/drivers/mtd/nand/nand_ecc.c $(obj)nand_ecc.c
-
-ifneq ($(OBJTREE), $(SRCTREE))
-$(obj)sdram.c:
-	@rm -f $(obj)sdram.c
-	ln -s $(SRCTREE)/nand_spl/board/$(BOARDDIR)/sdram.c $(obj)sdram.c
-endif
-
-#########################################################################
-
-$(obj)%.o:	$(obj)%.S
-	$(CC) $(AFLAGS) -c -o $@ $<
-
-$(obj)%.o:	$(obj)%.c
-	$(CC) $(CFLAGS) -c -o $@ $<
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
diff --git a/nand_spl/board/amcc/bamboo/config.mk b/nand_spl/board/amcc/bamboo/config.mk
deleted file mode 100644
index 6cc8fa30f3..0000000000
--- a/nand_spl/board/amcc/bamboo/config.mk
+++ /dev/null
@@ -1,33 +0,0 @@
-#
-# (C) Copyright 2007
-# Stefan Roese, DENX Software Engineering, sr@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-#
-# AMCC 440EP Reference Platform (Bamboo) board
-#
-
-#
-# CONFIG_SYS_TEXT_BASE for SPL:
-#
-# On 440EP(x) platforms the SPL is located at 0xfffff000...0xffffffff,
-# in the last 4kBytes of memory space in cache.
-# We will copy this SPL into instruction-cache in start.S. So we set
-# CONFIG_SYS_TEXT_BASE to starting address in i-cache here.
-#
-CONFIG_SYS_TEXT_BASE = 0x00800000
-
-# PAD_TO used to generate a 16kByte binary needed for the combined image
-# -> PAD_TO = CONFIG_SYS_TEXT_BASE + 0x4000
-PAD_TO	= 0x00804000
-
-PLATFORM_CPPFLAGS += -DCONFIG_440=1
-
-ifeq ($(debug),1)
-PLATFORM_CPPFLAGS += -DDEBUG
-endif
-
-ifeq ($(dbcr),1)
-PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8cff0000
-endif
diff --git a/nand_spl/board/amcc/bamboo/sdram.c b/nand_spl/board/amcc/bamboo/sdram.c
deleted file mode 100644
index df0dfc1a0d..0000000000
--- a/nand_spl/board/amcc/bamboo/sdram.c
+++ /dev/null
@@ -1,76 +0,0 @@
-/*
- * (C) Copyright 2007
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/ppc4xx.h>
-#include <asm/processor.h>
-#include <asm/io.h>
-
-static void wait_init_complete(void)
-{
-	u32 val;
-
-	do {
-		mfsdram(SDRAM0_MCSTS, val);
-	} while (!(val & 0x80000000));
-}
-
-/*
- * phys_size_t initdram(int board_type)
- *
- * As the name already indicates, this function is called very early
- * from start.S and configures the SDRAM with fixed values. This is needed,
- * since the 440EP has no internal SRAM and the 4kB NAND_SPL loader has
- * not enough free space to implement the complete I2C SPD DDR autodetection
- * routines. Therefore the Bamboo only supports the onboard 64MBytes of SDRAM
- * when booting from NAND flash.
- *
- * Note:
- * As found out by Eugene O'Brien <eugene.obrien@advantechamt.com>, the fixed
- * DDR setup has problems (U-Boot crashes randomly upon TFTP), when the DIMM
- * modules are still plugged in. So it is recommended to remove the DIMM
- * modules while using the NAND booting code with the fixed SDRAM setup!
- */
-phys_size_t initdram(int board_type)
-{
-	/*
-	 * Soft-reset SDRAM controller.
-	 */
-	mtsdr(SDR0_SRST, SDR0_SRST_DMC);
-	mtsdr(SDR0_SRST, 0x00000000);
-
-	/*
-	 * Disable memory controller.
-	 */
-	mtsdram(SDRAM0_CFG0, 0x00000000);
-
-	/*
-	 * Setup some default
-	 */
-	mtsdram(SDRAM0_UABBA, 0x00000000); /* ubba=0 (default)		*/
-	mtsdram(SDRAM0_SLIO, 0x00000000);	/* rdre=0 wrre=0 rarw=0		*/
-	mtsdram(SDRAM0_DEVOPT, 0x00000000); /* dll=0 ds=0 (normal)		*/
-	mtsdram(SDRAM0_WDDCTR, 0x00000000); /* wrcp=0 dcd=0		*/
-	mtsdram(SDRAM0_CLKTR, 0x40000000); /* clkp=1 (90 deg wr) dcdt=0	*/
-
-	/*
-	 * Following for CAS Latency = 2.5 @ 133 MHz PLB
-	 */
-	mtsdram(SDRAM0_B0CR, 0x00082001);
-	mtsdram(SDRAM0_TR0, 0x41094012);
-	mtsdram(SDRAM0_TR1, 0x8080083d);	/* SS=T2 SL=STAGE 3 CD=1 CT=0x00*/
-	mtsdram(SDRAM0_RTR, 0x04100000);	/* Interval 7.8µs @ 133MHz PLB	*/
-	mtsdram(SDRAM0_CFG1, 0x00000000);	/* Self-refresh exit, disable PM*/
-
-	/*
-	 * Enable the controller, then wait for DCEN to complete
-	 */
-	mtsdram(SDRAM0_CFG0, 0x80000000); /* DCEN=1, PMUD=0*/
-	wait_init_complete();
-
-	return CONFIG_SYS_MBYTES_SDRAM << 20;
-}
diff --git a/nand_spl/board/amcc/bamboo/u-boot.lds b/nand_spl/board/amcc/bamboo/u-boot.lds
deleted file mode 100644
index c432368175..0000000000
--- a/nand_spl/board/amcc/bamboo/u-boot.lds
+++ /dev/null
@@ -1,50 +0,0 @@
-/*
- * (C) Copyright 2007
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-OUTPUT_ARCH(powerpc:common)
-SECTIONS
-{
-  .resetvec 0x00800FFC :
-  {
-    KEEP(*(.resetvec))
-  } = 0xffff
-
-  .text      :
-  {
-    start.o	(.text)
-    init.o	(.text)
-    nand_boot.o	(.text)
-    sdram.o	(.text)
-    ndfc.o	(.text)
-
-    *(.text)
-    *(.fixup)
-  }
-  _etext = .;
-
-  .data    :
-  {
-    *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
-    *(.data*)
-    *(.sdata*)
-    __got2_start = .;
-    *(.got2)
-    __got2_end = .;
-  }
-
-  _edata  =  .;
-
-  __bss_start = .;
-  .bss (NOLOAD)       :
-  {
-   *(.sbss)
-   *(.bss)
-   . = ALIGN(4);
-  }
-
-  __bss_end = . ;
-}
diff --git a/nand_spl/board/amcc/canyonlands/Makefile b/nand_spl/board/amcc/canyonlands/Makefile
deleted file mode 100644
index f50d84b8c9..0000000000
--- a/nand_spl/board/amcc/canyonlands/Makefile
+++ /dev/null
@@ -1,99 +0,0 @@
-#
-# (C) Copyright 2008
-# Stefan Roese, DENX Software Engineering, sr@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-include $(TOPDIR)/config.mk
-include $(TOPDIR)/nand_spl/board/$(BOARDDIR)/config.mk
-
-nandobj	:= $(OBJTREE)/nand_spl/
-
-LDSCRIPT= $(TOPDIR)/nand_spl/board/$(BOARDDIR)/u-boot.lds
-LDFLAGS := -T $(nandobj)u-boot.lds -Ttext $(CONFIG_SYS_TEXT_BASE) $(LDFLAGS) \
-	   $(LDFLAGS_FINAL)
-AFLAGS	+= -DCONFIG_NAND_SPL
-CFLAGS	+= -DCONFIG_NAND_SPL
-
-SOBJS	:= start.o
-SOBJS	+= init.o
-SOBJS	+= resetvec.o
-COBJS	:= ddr2_fixed.o
-COBJS	+= nand_boot.o
-COBJS	+= nand_ecc.o
-COBJS	+= ndfc.o
-
-SRCS	:= $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c))
-OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS))
-__OBJS	:= $(SOBJS) $(COBJS)
-LNDIR	:= $(nandobj)board/$(BOARDDIR)
-
-ALL	= $(nandobj)u-boot-spl $(nandobj)u-boot-spl.bin $(nandobj)u-boot-spl-16k.bin
-
-all:	$(obj).depend $(ALL)
-
-$(nandobj)u-boot-spl-16k.bin: $(nandobj)u-boot-spl
-	$(OBJCOPY) ${OBJCFLAGS} --pad-to=$(PAD_TO) -O binary $< $@
-
-$(nandobj)u-boot-spl.bin:	$(nandobj)u-boot-spl
-	$(OBJCOPY) ${OBJCFLAGS} -O binary $< $@
-
-$(nandobj)u-boot-spl:	$(OBJS) $(nandobj)u-boot.lds
-	cd $(LNDIR) && $(LD) $(LDFLAGS) $(__OBJS) $(PLATFORM_LIBS) \
-		-Map $(nandobj)u-boot-spl.map \
-		-o $(nandobj)u-boot-spl
-
-$(nandobj)u-boot.lds: $(LDSCRIPT)
-	$(CPP) $(CPPFLAGS) $(LDPPFLAGS) -ansi -D__ASSEMBLY__ -P - <$^ >$@
-
-# create symbolic links for common files
-
-# from cpu directory
-$(obj)ndfc.c:
-	@rm -f $(obj)ndfc.c
-	ln -s $(SRCTREE)/drivers/mtd/nand/ndfc.c $(obj)ndfc.c
-
-$(obj)resetvec.S:
-	@rm -f $(obj)resetvec.S
-	ln -s $(SRCTREE)/arch/powerpc/cpu/ppc4xx/resetvec.S $(obj)resetvec.S
-
-$(obj)start.S:
-	@rm -f $(obj)start.S
-	ln -s $(SRCTREE)/arch/powerpc/cpu/ppc4xx/start.S $(obj)start.S
-
-# from board directory
-$(obj)init.S:
-	@rm -f $(obj)init.S
-	ln -s $(SRCTREE)/board/amcc/canyonlands/init.S $(obj)init.S
-
-# from nand_spl directory
-$(obj)nand_boot.c:
-	@rm -f $(obj)nand_boot.c
-	ln -s $(SRCTREE)/nand_spl/nand_boot.c $(obj)nand_boot.c
-
-# from drivers/mtd/nand directory
-$(obj)nand_ecc.c:
-	@rm -f $(obj)nand_ecc.c
-	ln -s $(SRCTREE)/drivers/mtd/nand/nand_ecc.c $(obj)nand_ecc.c
-
-ifneq ($(OBJTREE), $(SRCTREE))
-$(obj)ddr2_fixed.c:
-	@rm -f $(obj)ddr2_fixed.c
-	ln -s $(SRCTREE)/nand_spl/board/$(BOARDDIR)/ddr2_fixed.c $(obj)ddr2_fixed.c
-endif
-
-#########################################################################
-
-$(obj)%.o:	$(obj)%.S
-	$(CC) $(AFLAGS) -c -o $@ $<
-
-$(obj)%.o:	$(obj)%.c
-	$(CC) $(CFLAGS) -c -o $@ $<
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
diff --git a/nand_spl/board/amcc/canyonlands/config.mk b/nand_spl/board/amcc/canyonlands/config.mk
deleted file mode 100644
index 780b7ae375..0000000000
--- a/nand_spl/board/amcc/canyonlands/config.mk
+++ /dev/null
@@ -1,33 +0,0 @@
-#
-# (C) Copyright 2008
-# Stefan Roese, DENX Software Engineering, sr@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-#
-# AMCC 460EX Reference Platform (Canyonlands) board
-#
-
-#
-# CONFIG_SYS_TEXT_BASE for SPL:
-#
-# On 460EX platforms the SPL is located at 0xfffff000...0xffffffff,
-# in the last 4kBytes of memory space in cache.
-# We will copy this SPL into internal SRAM in start.S. So we set
-# CONFIG_SYS_TEXT_BASE to starting address in internal SRAM here.
-#
-CONFIG_SYS_TEXT_BASE = 0xE3003000
-
-# PAD_TO used to generate a 128kByte binary needed for the combined image
-# -> PAD_TO = CONFIG_SYS_TEXT_BASE + 0x20000
-PAD_TO	= 0xE3023000
-
-PLATFORM_CPPFLAGS += -DCONFIG_440=1
-
-ifeq ($(debug),1)
-PLATFORM_CPPFLAGS += -DDEBUG
-endif
-
-ifeq ($(dbcr),1)
-PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8cff0000
-endif
diff --git a/nand_spl/board/amcc/canyonlands/ddr2_fixed.c b/nand_spl/board/amcc/canyonlands/ddr2_fixed.c
deleted file mode 100644
index ce8515d513..0000000000
--- a/nand_spl/board/amcc/canyonlands/ddr2_fixed.c
+++ /dev/null
@@ -1,130 +0,0 @@
-/*
- * (C) Copyright 2008-2009
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/ppc4xx.h>
-#include <asm/io.h>
-#include <asm/processor.h>
-
-/*
- * This code can configure those two Crucial SODIMM's:
- *
- * Crucial CT6464AC667.4FE - 512MB SO-DIMM (single rank)
- * Crucial CT6464AC667.8FB - 512MB SO-DIMM (dual rank)
- *
- */
-
-#define TEST_ADDR	0x10000000
-#define TEST_MAGIC	0x11223344
-
-static void wait_init_complete(void)
-{
-	u32 val;
-
-	do {
-		mfsdram(SDRAM_MCSTAT, val);
-	} while (!(val & 0x80000000));
-}
-
-static void ddr_start(void)
-{
-	mtsdram(SDRAM_MCOPT2, 0x28000000);
-	wait_init_complete();
-}
-
-static void ddr_init_common(void)
-{
-	/*
-	 * Reset the DDR-SDRAM controller.
-	 */
-	mtsdr(SDR0_SRST, SDR0_SRST0_DMC);
-	mtsdr(SDR0_SRST, 0x00000000);
-
-	/*
-	 * These values are cloned from a running NOR booting
-	 * Canyonlands with SPD-DDR2 detection and calibration
-	 * enabled. This will only work for the same memory
-	 * configuration as used here:
-	 *
-	 */
-	mtsdram(SDRAM_MCOPT2, 0x00000000);
-	mtsdram(SDRAM_MODT0, 0x01000000);
-	mtsdram(SDRAM_WRDTR, 0x82000823);
-	mtsdram(SDRAM_CLKTR, 0x40000000);
-	mtsdram(SDRAM_MB0CF, 0x00000201);
-	mtsdram(SDRAM_RTR, 0x06180000);
-	mtsdram(SDRAM_SDTR1, 0x80201000);
-	mtsdram(SDRAM_SDTR2, 0x42103243);
-	mtsdram(SDRAM_SDTR3, 0x0A0D0D16);
-	mtsdram(SDRAM_MMODE, 0x00000632);
-	mtsdram(SDRAM_MEMODE, 0x00000040);
-	mtsdram(SDRAM_INITPLR0, 0xB5380000);
-	mtsdram(SDRAM_INITPLR1, 0x82100400);
-	mtsdram(SDRAM_INITPLR2, 0x80820000);
-	mtsdram(SDRAM_INITPLR3, 0x80830000);
-	mtsdram(SDRAM_INITPLR4, 0x80810040);
-	mtsdram(SDRAM_INITPLR5, 0x80800532);
-	mtsdram(SDRAM_INITPLR6, 0x82100400);
-	mtsdram(SDRAM_INITPLR7, 0x8A080000);
-	mtsdram(SDRAM_INITPLR8, 0x8A080000);
-	mtsdram(SDRAM_INITPLR9, 0x8A080000);
-	mtsdram(SDRAM_INITPLR10, 0x8A080000);
-	mtsdram(SDRAM_INITPLR11, 0x80000432);
-	mtsdram(SDRAM_INITPLR12, 0x808103C0);
-	mtsdram(SDRAM_INITPLR13, 0x80810040);
-	mtsdram(SDRAM_RDCC, 0x40000000);
-	mtsdram(SDRAM_RQDC, 0x80000038);
-	mtsdram(SDRAM_RFDC, 0x00000257);
-
-	mtdcr(SDRAM_R0BAS, 0x0000F800);		/* MQ0_B0BAS */
-}
-
-phys_size_t initdram(int board_type)
-{
-	/*
-	 * First try init for this module:
-	 *
-	 * Crucial CT6464AC667.8FB - 512MB SO-DIMM (dual rank)
-	 */
-
-	ddr_init_common();
-
-	/*
-	 * Crucial CT6464AC667.8FB - 512MB SO-DIMM
-	 */
-	mtdcr(SDRAM_R0BAS, 0x0000F800);
-	mtdcr(SDRAM_R1BAS, 0x0400F800);
-	mtsdram(SDRAM_MCOPT1, 0x05122000);
-	mtsdram(SDRAM_CODT, 0x02800021);
-	mtsdram(SDRAM_MB1CF, 0x00000201);
-
-	ddr_start();
-
-	/*
-	 * Now test if the dual-ranked module is really installed
-	 * by checking an address in the upper 256MByte region
-	 */
-	out_be32((void *)TEST_ADDR, TEST_MAGIC);
-	if (in_be32((void *)TEST_ADDR) != TEST_MAGIC) {
-		/*
-		 * The test failed, so we assume that the single
-		 * ranked module is installed:
-		 *
-		 * Crucial CT6464AC667.4FE - 512MB SO-DIMM (single rank)
-		 */
-
-		ddr_init_common();
-
-		mtdcr(SDRAM_R0BAS, 0x0000F000);
-		mtsdram(SDRAM_MCOPT1, 0x05322000);
-		mtsdram(SDRAM_CODT, 0x00800021);
-
-		ddr_start();
-	}
-
-	return CONFIG_SYS_MBYTES_SDRAM << 20;
-}
diff --git a/nand_spl/board/amcc/canyonlands/u-boot.lds b/nand_spl/board/amcc/canyonlands/u-boot.lds
deleted file mode 100644
index 6383b1a38f..0000000000
--- a/nand_spl/board/amcc/canyonlands/u-boot.lds
+++ /dev/null
@@ -1,50 +0,0 @@
-/*
- * (C) Copyright 2008
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-OUTPUT_ARCH(powerpc:common)
-SECTIONS
-{
-  .resetvec 0xE3003FFC :
-  {
-    KEEP(*(.resetvec))
-  } = 0xffff
-
-  .text      :
-  {
-    start.o	(.text)
-    init.o	(.text)
-    nand_boot.o	(.text)
-    ddr2_fixed.o (.text)
-    ndfc.o	(.text)
-
-    *(.text)
-    *(.fixup)
-  }
-  _etext = .;
-
-  .data    :
-  {
-    *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
-    *(.data*)
-    *(.sdata*)
-    __got2_start = .;
-    *(.got2)
-    __got2_end = .;
-  }
-
-  _edata  =  .;
-
-  __bss_start = .;
-  .bss (NOLOAD)       :
-  {
-   *(.sbss)
-   *(.bss)
-   . = ALIGN(4);
-  }
-
-  __bss_end = . ;
-}
diff --git a/nand_spl/board/amcc/kilauea/Makefile b/nand_spl/board/amcc/kilauea/Makefile
deleted file mode 100644
index 8b4206f57b..0000000000
--- a/nand_spl/board/amcc/kilauea/Makefile
+++ /dev/null
@@ -1,95 +0,0 @@
-#
-# (C) Copyright 2007
-# Stefan Roese, DENX Software Engineering, sr@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-include $(TOPDIR)/config.mk
-include $(TOPDIR)/nand_spl/board/$(BOARDDIR)/config.mk
-
-nandobj	:= $(OBJTREE)/nand_spl/
-
-LDSCRIPT= $(TOPDIR)/nand_spl/board/$(BOARDDIR)/u-boot.lds
-LDFLAGS := -T $(nandobj)u-boot.lds -Ttext $(CONFIG_SYS_TEXT_BASE) $(LDFLAGS) \
-	   $(LDFLAGS_FINAL)
-AFLAGS	+= -DCONFIG_NAND_SPL
-CFLAGS	+= -DCONFIG_NAND_SPL
-
-SOBJS	= start.o resetvec.o cache.o
-COBJS	= 44x_spd_ddr2.o nand_boot.o nand_ecc.o ndfc.o
-
-SRCS	:= $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c))
-OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS))
-__OBJS	:= $(SOBJS) $(COBJS)
-LNDIR	:= $(nandobj)board/$(BOARDDIR)
-
-ALL	= $(nandobj)u-boot-spl $(nandobj)u-boot-spl.bin $(nandobj)u-boot-spl-16k.bin
-
-all:	$(obj).depend $(ALL)
-
-$(nandobj)u-boot-spl-16k.bin: $(nandobj)u-boot-spl
-	$(OBJCOPY) ${OBJCFLAGS} --pad-to=$(PAD_TO) -O binary $< $@
-
-$(nandobj)u-boot-spl.bin:	$(nandobj)u-boot-spl
-	$(OBJCOPY) ${OBJCFLAGS} -O binary $< $@
-
-$(nandobj)u-boot-spl:	$(OBJS) $(nandobj)u-boot.lds
-	cd $(LNDIR) && $(LD) $(LDFLAGS) $(__OBJS) $(PLATFORM_LIBS) \
-		-Map $(nandobj)u-boot-spl.map \
-		-o $(nandobj)u-boot-spl
-
-$(nandobj)u-boot.lds: $(LDSCRIPT)
-	$(CPP) $(CPPFLAGS) $(LDPPFLAGS) -ansi -D__ASSEMBLY__ -P - <$^ >$@
-
-# create symbolic links for common files
-
-# from cpu directory
-$(obj)44x_spd_ddr2.c: $(obj)ecc.h
-	@rm -f $(obj)44x_spd_ddr2.c
-	ln -s $(SRCTREE)/arch/powerpc/cpu/ppc4xx/44x_spd_ddr2.c $(obj)44x_spd_ddr2.c
-
-$(obj)cache.S:
-	@rm -f $(obj)cache.S
-	ln -s $(SRCTREE)/arch/powerpc/cpu/ppc4xx/cache.S $(obj)cache.S
-
-$(obj)ecc.h:
-	@rm -f $(obj)ecc.h
-	ln -s $(SRCTREE)/arch/powerpc/cpu/ppc4xx/ecc.h $(obj)ecc.h
-
-$(obj)ndfc.c:
-	@rm -f $(obj)ndfc.c
-	ln -s $(SRCTREE)/drivers/mtd/nand/ndfc.c $(obj)ndfc.c
-
-$(obj)resetvec.S:
-	@rm -f $(obj)resetvec.S
-	ln -s $(SRCTREE)/arch/powerpc/cpu/ppc4xx/resetvec.S $(obj)resetvec.S
-
-$(obj)start.S:
-	@rm -f $(obj)start.S
-	ln -s $(SRCTREE)/arch/powerpc/cpu/ppc4xx/start.S $(obj)start.S
-
-# from nand_spl directory
-$(obj)nand_boot.c:
-	@rm -f $(obj)nand_boot.c
-	ln -s $(SRCTREE)/nand_spl/nand_boot.c $(obj)nand_boot.c
-
-# from drivers/nand directory
-$(obj)nand_ecc.c:
-	@rm -f $(obj)nand_ecc.c
-	ln -s $(SRCTREE)/drivers/mtd/nand/nand_ecc.c $(obj)nand_ecc.c
-
-#########################################################################
-
-$(obj)%.o:	$(obj)%.S
-	$(CC) $(AFLAGS) -c -o $@ $<
-
-$(obj)%.o:	$(obj)%.c
-	$(CC) $(CFLAGS) -c -o $@ $<
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
diff --git a/nand_spl/board/amcc/kilauea/config.mk b/nand_spl/board/amcc/kilauea/config.mk
deleted file mode 100644
index b596b1406c..0000000000
--- a/nand_spl/board/amcc/kilauea/config.mk
+++ /dev/null
@@ -1,32 +0,0 @@
-#
-# (C) Copyright 2007
-# Stefan Roese, DENX Software Engineering, sr@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-#
-# AMCC 405EX Reference Platform (Kilauea) board
-#
-
-#
-# CONFIG_SYS_TEXT_BASE for SPL:
-#
-# On 4xx platforms the SPL is located at 0xfffff000...0xffffffff,
-# in the last 4kBytes of memory space in cache.
-# We will copy this SPL into SDRAM since we can't access the NAND
-# controller at CS0 while running from this location. So we set
-# CONFIG_SYS_TEXT_BASE to starting address in SDRAM here.
-#
-CONFIG_SYS_TEXT_BASE = 0x00800000
-
-# PAD_TO used to generate a 16kByte binary needed for the combined image
-# -> PAD_TO = CONFIG_SYS_TEXT_BASE + 0x4000
-PAD_TO	= 0x00804000
-
-ifeq ($(debug),1)
-PLATFORM_CPPFLAGS += -DDEBUG
-endif
-
-ifeq ($(dbcr),1)
-PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8cff0000
-endif
diff --git a/nand_spl/board/amcc/kilauea/u-boot.lds b/nand_spl/board/amcc/kilauea/u-boot.lds
deleted file mode 100644
index d7262e6c53..0000000000
--- a/nand_spl/board/amcc/kilauea/u-boot.lds
+++ /dev/null
@@ -1,48 +0,0 @@
-/*
- * (C) Copyright 2007
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-OUTPUT_ARCH(powerpc:common)
-SECTIONS
-{
-  .resetvec 0x00800FFC :
-  {
-    KEEP(*(.resetvec))
-  } = 0xffff
-
-  .text      :
-  {
-    start.o	(.text)
-    nand_boot.o	(.text)
-    ndfc.o	(.text)
-
-    *(.text)
-    *(.fixup)
-  }
-  _etext = .;
-
-  .data    :
-  {
-    *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
-    *(.data*)
-    *(.sdata*)
-    __got2_start = .;
-    *(.got2)
-    __got2_end = .;
-  }
-
-  _edata  =  .;
-
-  __bss_start = .;
-  .bss (NOLOAD)       :
-  {
-   *(.sbss)
-   *(.bss)
-   . = ALIGN(4);
-  }
-
-  __bss_end = . ;
-}
diff --git a/nand_spl/board/amcc/sequoia/Makefile b/nand_spl/board/amcc/sequoia/Makefile
deleted file mode 100644
index 0fcf030d43..0000000000
--- a/nand_spl/board/amcc/sequoia/Makefile
+++ /dev/null
@@ -1,98 +0,0 @@
-#
-# (C) Copyright 2006-2007
-# Stefan Roese, DENX Software Engineering, sr@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-include $(TOPDIR)/config.mk
-include $(TOPDIR)/nand_spl/board/$(BOARDDIR)/config.mk
-
-nandobj	:= $(OBJTREE)/nand_spl/
-
-LDSCRIPT= $(TOPDIR)/nand_spl/board/$(BOARDDIR)/u-boot.lds
-LDFLAGS := -T $(nandobj)u-boot.lds -Ttext $(CONFIG_SYS_TEXT_BASE) $(LDFLAGS) \
-	   $(LDFLAGS_FINAL)
-AFLAGS	+= -DCONFIG_NAND_SPL
-CFLAGS	+= -DCONFIG_NAND_SPL
-
-SOBJS	= start.o init.o resetvec.o
-COBJS	= denali_data_eye.o nand_boot.o nand_ecc.o ndfc.o sdram.o
-
-SRCS	:= $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c))
-OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS))
-__OBJS	:= $(SOBJS) $(COBJS)
-LNDIR	:= $(nandobj)board/$(BOARDDIR)
-
-ALL	= $(nandobj)u-boot-spl $(nandobj)u-boot-spl.bin $(nandobj)u-boot-spl-16k.bin
-
-all:	$(obj).depend $(ALL)
-
-$(nandobj)u-boot-spl-16k.bin: $(nandobj)u-boot-spl
-	$(OBJCOPY) ${OBJCFLAGS} --pad-to=$(PAD_TO) -O binary $< $@
-
-$(nandobj)u-boot-spl.bin:	$(nandobj)u-boot-spl
-	$(OBJCOPY) ${OBJCFLAGS} -O binary $< $@
-
-$(nandobj)u-boot-spl:	$(OBJS) $(nandobj)u-boot.lds
-	cd $(LNDIR) && $(LD) $(LDFLAGS) $(__OBJS) $(PLATFORM_LIBS) \
-		-Map $(nandobj)u-boot-spl.map \
-		-o $(nandobj)u-boot-spl
-
-$(nandobj)u-boot.lds: $(LDSCRIPT)
-	$(CPP) $(CPPFLAGS) $(LDPPFLAGS) -ansi -D__ASSEMBLY__ -P - <$^ >$@
-
-# create symbolic links for common files
-
-# from cpu directory
-$(obj)denali_data_eye.c:
-	@rm -f $(obj)denali_data_eye.c
-	ln -s $(SRCTREE)/arch/powerpc/cpu/ppc4xx/denali_data_eye.c $(obj)denali_data_eye.c
-
-$(obj)ndfc.c:
-	@rm -f $(obj)ndfc.c
-	ln -s $(SRCTREE)/drivers/mtd/nand/ndfc.c $(obj)ndfc.c
-
-$(obj)resetvec.S:
-	@rm -f $(obj)resetvec.S
-	ln -s $(SRCTREE)/arch/powerpc/cpu/ppc4xx/resetvec.S $(obj)resetvec.S
-
-$(obj)start.S:
-	@rm -f $(obj)start.S
-	ln -s $(SRCTREE)/arch/powerpc/cpu/ppc4xx/start.S $(obj)start.S
-
-# from board directory
-$(obj)init.S:
-	@rm -f $(obj)init.S
-	ln -s $(SRCTREE)/board/amcc/sequoia/init.S $(obj)init.S
-
-$(obj)sdram.c:
-	@rm -f $(obj)sdram.c
-	@rm -f $(obj)sdram.h
-	ln -s $(SRCTREE)/board/amcc/sequoia/sdram.c $(obj)sdram.c
-	ln -s $(SRCTREE)/board/amcc/sequoia/sdram.h $(obj)sdram.h
-
-# from nand_spl directory
-$(obj)nand_boot.c:
-	@rm -f $(obj)nand_boot.c
-	ln -s $(SRCTREE)/nand_spl/nand_boot.c $(obj)nand_boot.c
-
-# from drivers/mtd/nand directory
-$(obj)nand_ecc.c:
-	@rm -f $(obj)nand_ecc.c
-	ln -s $(SRCTREE)/drivers/mtd/nand/nand_ecc.c $(obj)nand_ecc.c
-
-#########################################################################
-
-$(obj)%.o:	$(obj)%.S
-	$(CC) $(AFLAGS) -c -o $@ $<
-
-$(obj)%.o:	$(obj)%.c
-	$(CC) $(CFLAGS) -c -o $@ $<
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
diff --git a/nand_spl/board/amcc/sequoia/config.mk b/nand_spl/board/amcc/sequoia/config.mk
deleted file mode 100644
index ede7964d9f..0000000000
--- a/nand_spl/board/amcc/sequoia/config.mk
+++ /dev/null
@@ -1,33 +0,0 @@
-#
-# (C) Copyright 2006
-# Stefan Roese, DENX Software Engineering, sr@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-#
-# AMCC 440EPx Reference Platform (Sequoia) board
-#
-
-#
-# CONFIG_SYS_TEXT_BASE for SPL:
-#
-# On 440EP(x) platforms the SPL is located at 0xfffff000...0xffffffff,
-# in the last 4kBytes of memory space in cache.
-# We will copy this SPL into internal SRAM in start.S. So we set
-# CONFIG_SYS_TEXT_BASE to starting address in internal SRAM here.
-#
-CONFIG_SYS_TEXT_BASE = 0xE0013000
-
-# PAD_TO used to generate a 16kByte binary needed for the combined image
-# -> PAD_TO = CONFIG_SYS_TEXT_BASE + 0x4000
-PAD_TO	= 0xE0017000
-
-PLATFORM_CPPFLAGS += -DCONFIG_440=1
-
-ifeq ($(debug),1)
-PLATFORM_CPPFLAGS += -DDEBUG
-endif
-
-ifeq ($(dbcr),1)
-PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8cff0000
-endif
diff --git a/nand_spl/board/amcc/sequoia/u-boot.lds b/nand_spl/board/amcc/sequoia/u-boot.lds
deleted file mode 100644
index 45c0162af6..0000000000
--- a/nand_spl/board/amcc/sequoia/u-boot.lds
+++ /dev/null
@@ -1,50 +0,0 @@
-/*
- * (C) Copyright 2006-2010
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-OUTPUT_ARCH(powerpc:common)
-SECTIONS
-{
-  .resetvec 0xE0013FFC :
-  {
-    KEEP(*(.resetvec))
-  } = 0xffff
-
-  .text      :
-  {
-    start.o	(.text)
-    init.o	(.text)
-    nand_boot.o	(.text)
-    sdram.o	(.text)
-    ndfc.o	(.text)
-
-    *(.text)
-    *(.fixup)
-  }
-  _etext = .;
-
-  .data    :
-  {
-    *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
-    *(.data*)
-    *(.sdata*)
-    __got2_start = .;
-    *(.got2)
-    __got2_end = .;
-  }
-
-  _edata  =  .;
-
-  __bss_start = .;
-  .bss (NOLOAD)       :
-  {
-   *(.sbss)
-   *(.bss)
-   . = ALIGN(4);
-  }
-
-  __bss_end = . ;
-}
diff --git a/nand_spl/board/freescale/mpc8315erdb/Makefile b/nand_spl/board/freescale/mpc8315erdb/Makefile
index 5b11d1067e..f4e7854d50 100644
--- a/nand_spl/board/freescale/mpc8315erdb/Makefile
+++ b/nand_spl/board/freescale/mpc8315erdb/Makefile
@@ -6,87 +6,66 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-NAND_SPL := y
 PAD_TO := 0xfff04000
 
-include $(TOPDIR)/config.mk
+nandobj	:= $(objtree)/nand_spl/
 
-nandobj	:= $(OBJTREE)/nand_spl/
-
-LDSCRIPT= $(TOPDIR)/nand_spl/board/$(BOARDDIR)/u-boot.lds
+LDSCRIPT= $(srctree)/nand_spl/board/$(BOARDDIR)/u-boot.lds
 LDFLAGS := -T $(nandobj)u-boot.lds -Ttext $(CONFIG_SYS_TEXT_BASE_SPL) \
 	   $(LDFLAGS) $(LDFLAGS_FINAL)
-AFLAGS	+= -DCONFIG_NAND_SPL
-CFLAGS	+= -DCONFIG_NAND_SPL
+asflags-y += -DCONFIG_NAND_SPL
+ccflags-y += -DCONFIG_NAND_SPL
 
 SOBJS	= start.o ticks.o
 COBJS	= nand_boot_fsl_elbc.o $(BOARD).o sdram.o ns16550.o spl_minimal.o \
 	  time.o cache.o
 
-SRCS	:= $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c))
-OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS))
+OBJS	:= $(addprefix $(obj)/,$(SOBJS) $(COBJS))
 __OBJS	:= $(SOBJS) $(COBJS)
 LNDIR	:= $(nandobj)board/$(BOARDDIR)
 
-ALL	= $(nandobj)u-boot-spl $(nandobj)u-boot-spl.bin $(nandobj)u-boot-spl-16k.bin
+targets += $(__OBJS)
 
-all:	$(obj).depend $(ALL)
+all: $(nandobj)u-boot-spl.bin $(nandobj)u-boot-spl-16k.bin
 
 $(nandobj)u-boot-spl-16k.bin: $(nandobj)u-boot-spl
-	$(OBJCOPY) ${OBJCFLAGS} --pad-to=$(PAD_TO) -O binary $< $@
+	$(OBJCOPY) $(OBJCOPYFLAGS) --pad-to=$(PAD_TO) -O binary $< $@
 
 $(nandobj)u-boot-spl.bin:	$(nandobj)u-boot-spl
-	$(OBJCOPY) ${OBJCFLAGS} -O binary $< $@
+	$(OBJCOPY) $(OBJCOPYFLAGS) -O binary $< $@
 
 $(nandobj)u-boot-spl:	$(OBJS) $(nandobj)u-boot.lds
 	cd $(LNDIR) && $(LD) $(LDFLAGS) $(__OBJS) $(PLATFORM_LIBS) \
-		-Map $(nandobj)u-boot-spl.map \
-		-o $(nandobj)u-boot-spl
+		-Map $(nandobj)u-boot-spl.map -o $@
 
 $(nandobj)u-boot.lds: $(LDSCRIPT)
-	$(CPP) $(CPPFLAGS) $(LDPPFLAGS) -ansi -D__ASSEMBLY__ -P - <$^ >$@
+	$(CPP) $(cpp_flags) $(LDPPFLAGS) -ansi -D__ASSEMBLY__ -P - <$^ >$@
 
 # create symbolic links for common files
 
-$(obj)start.S:
-	ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc83xx/start.S $(obj)start.S
-
-$(obj)nand_boot_fsl_elbc.c:
-	ln -sf $(SRCTREE)/nand_spl/nand_boot_fsl_elbc.c \
-	       $(obj)nand_boot_fsl_elbc.c
-
-$(obj)sdram.c:
-	ln -sf $(SRCTREE)/board/$(BOARDDIR)/sdram.c $(obj)sdram.c
-
-$(obj)$(BOARD).c:
-	ln -sf $(SRCTREE)/board/$(BOARDDIR)/$(BOARD).c $(obj)$(BOARD).c
-
-$(obj)ns16550.c:
-	ln -sf $(SRCTREE)/drivers/serial/ns16550.c $(obj)ns16550.c
-
-$(obj)spl_minimal.c:
-	ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc83xx/spl_minimal.c $(obj)spl_minimal.c
-
-$(obj)cache.c:
-	ln -sf $(SRCTREE)/arch/powerpc/lib/cache.c $(obj)cache.c
+$(obj)/start.S:
+	ln -sf $(srctree)/arch/powerpc/cpu/mpc83xx/start.S $@
 
-$(obj)time.c:
-	ln -sf $(SRCTREE)/arch/powerpc/lib/time.c $(obj)time.c
+$(obj)/nand_boot_fsl_elbc.c:
+	ln -sf $(srctree)/nand_spl/nand_boot_fsl_elbc.c $@
 
-$(obj)ticks.S:
-	ln -sf $(SRCTREE)/arch/powerpc/lib/ticks.S $(obj)ticks.S
+$(obj)/sdram.c:
+	ln -sf $(srctree)/board/$(BOARDDIR)/sdram.c $@
 
-#########################################################################
+$(obj)/$(BOARD).c:
+	ln -sf $(srctree)/board/$(BOARDDIR)/$(BOARD).c $@
 
-$(obj)%.o:	$(obj)%.S
-	$(CC) $(AFLAGS) -c -o $@ $<
+$(obj)/ns16550.c:
+	ln -sf $(srctree)/drivers/serial/ns16550.c $@
 
-$(obj)%.o:	$(obj)%.c
-	$(CC) $(CFLAGS) -c -o $@ $<
+$(obj)/spl_minimal.c:
+	ln -sf $(srctree)/arch/powerpc/cpu/mpc83xx/spl_minimal.c $@
 
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
+$(obj)/cache.c:
+	ln -sf $(srctree)/arch/powerpc/lib/cache.c $@
 
-sinclude $(obj).depend
+$(obj)/time.c:
+	ln -sf $(srctree)/arch/powerpc/lib/time.c $@
 
-#########################################################################
+$(obj)/ticks.S:
+	ln -sf $(srctree)/arch/powerpc/lib/ticks.S $@
diff --git a/nand_spl/board/freescale/mpc8536ds/Makefile b/nand_spl/board/freescale/mpc8536ds/Makefile
index d3dac2074c..c639b126fd 100644
--- a/nand_spl/board/freescale/mpc8536ds/Makefile
+++ b/nand_spl/board/freescale/mpc8536ds/Makefile
@@ -7,116 +7,89 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-NAND_SPL := y
 CONFIG_SYS_TEXT_BASE_SPL := 0xfff00000
 PAD_TO := 0xfff01000
 
-include $(TOPDIR)/config.mk
+nandobj	:= $(objtree)/nand_spl/
 
-nandobj	:= $(OBJTREE)/nand_spl/
-
-LDSCRIPT= $(TOPDIR)/$(CPUDIR)/u-boot-nand_spl.lds
+LDSCRIPT= $(srctree)/$(CPUDIR)/u-boot-nand_spl.lds
 LDFLAGS := -T $(nandobj)u-boot-nand_spl.lds -Ttext $(CONFIG_SYS_TEXT_BASE_SPL) \
 		$(LDFLAGS) $(LDFLAGS_FINAL)
-AFLAGS	+= -DCONFIG_NAND_SPL
-CFLAGS	+= -DCONFIG_NAND_SPL
+asflags-y += -DCONFIG_NAND_SPL
+ccflags-y += -DCONFIG_NAND_SPL
 
 SOBJS	= start.o resetvec.o
 COBJS	= cache.o cpu_init_early.o spl_minimal.o fsl_law.o law.o \
 	  nand_boot.o nand_boot_fsl_elbc.o ns16550.o tlb.o tlb_table.o
 
-SRCS	:= $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c))
-OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS))
+OBJS	:= $(addprefix $(obj)/,$(SOBJS) $(COBJS))
 __OBJS	:= $(SOBJS) $(COBJS)
 LNDIR	:= $(nandobj)board/$(BOARDDIR)
 
-ALL	= $(nandobj)u-boot-spl $(nandobj)u-boot-spl.bin $(nandobj)u-boot-spl-16k.bin
+targets += $(__OBJS)
 
-all:	$(obj).depend $(ALL)
+all: $(nandobj)u-boot-spl.bin $(nandobj)u-boot-spl-16k.bin
 
 $(nandobj)u-boot-spl-16k.bin: $(nandobj)u-boot-spl
-	$(OBJCOPY) ${OBJCFLAGS} --pad-to=$(PAD_TO) -O binary $< $@
+	$(OBJCOPY) $(OBJCOPYFLAGS) --pad-to=$(PAD_TO) -O binary $< $@
 
 $(nandobj)u-boot-spl.bin:	$(nandobj)u-boot-spl
-	$(OBJCOPY) ${OBJCFLAGS} -O binary $< $@
+	$(OBJCOPY) $(OBJCOPYFLAGS) -O binary $< $@
 
 $(nandobj)u-boot-spl:	$(OBJS) $(nandobj)u-boot-nand_spl.lds
 	cd $(LNDIR) && $(LD) $(LDFLAGS) $(__OBJS) $(PLATFORM_LIBS) \
-		-Map $(nandobj)u-boot-spl.map \
-		-o $(nandobj)u-boot-spl
+		-Map $(nandobj)u-boot-spl.map -o $@
 
 $(nandobj)u-boot-nand_spl.lds: $(LDSCRIPT)
-	$(CPP) $(CPPFLAGS) $(LDPPFLAGS) -I$(nandobj)/board/$(BOARDDIR) \
+	$(CPP) $(cpp_flags) $(LDPPFLAGS) -I$(nandobj)/board/$(BOARDDIR) \
 		-ansi -D__ASSEMBLY__ -P - <$< >$@
 
 # create symbolic links for common files
 
-$(obj)cache.c:
-	@rm -f $(obj)cache.c
-	ln -sf $(SRCTREE)/arch/powerpc/lib/cache.c $(obj)cache.c
-
-$(obj)cpu_init_early.c:
-	@rm -f $(obj)cpu_init_early.c
-	ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/cpu_init_early.c $(obj)cpu_init_early.c
-
-$(obj)spl_minimal.c:
-	@rm -f $(obj)spl_minimal.c
-	ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/spl_minimal.c $(obj)spl_minimal.c
-
-$(obj)fsl_law.c:
-	@rm -f $(obj)fsl_law.c
-	ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc8xxx/law.c $(obj)fsl_law.c
-
-$(obj)law.c:
-	@rm -f $(obj)law.c
-	ln -sf $(SRCTREE)/board/$(BOARDDIR)/law.c $(obj)law.c
-
-$(obj)nand_boot_fsl_elbc.c:
-	@rm -f $(obj)nand_boot_fsl_elbc.c
-	ln -sf $(SRCTREE)/nand_spl/nand_boot_fsl_elbc.c \
-	       $(obj)nand_boot_fsl_elbc.c
-
-$(obj)ns16550.c:
-	@rm -f $(obj)ns16550.c
-	ln -sf $(SRCTREE)/drivers/serial/ns16550.c $(obj)ns16550.c
-
-$(obj)resetvec.S:
-	@rm -f $(obj)resetvec.S
-	ln -s $(SRCTREE)/$(CPUDIR)/resetvec.S $(obj)resetvec.S
+$(obj)/cache.c:
+	@rm -f $@
+	ln -sf $(srctree)/arch/powerpc/lib/cache.c $@
 
-$(obj)fixed_ivor.S:
-	@rm -f $(obj)fixed_ivor.S
-	ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/fixed_ivor.S $(obj)fixed_ivor.S
+$(obj)/cpu_init_early.c:
+	@rm -f $@
+	ln -sf $(srctree)/arch/powerpc/cpu/mpc85xx/cpu_init_early.c $@
 
-$(obj)start.S: $(obj)fixed_ivor.S
-	@rm -f $(obj)start.S
-	ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/start.S $(obj)start.S
+$(obj)/spl_minimal.c:
+	@rm -f $@
+	ln -sf $(srctree)/arch/powerpc/cpu/mpc85xx/spl_minimal.c $@
 
-$(obj)tlb.c:
-	@rm -f $(obj)tlb.c
-	ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/tlb.c $(obj)tlb.c
+$(obj)/fsl_law.c:
+	@rm -f $@
+	ln -sf $(srctree)/arch/powerpc/cpu/mpc8xxx/law.c $@
 
-$(obj)tlb_table.c:
-	@rm -f $(obj)tlb_table.c
-	ln -sf $(SRCTREE)/board/$(BOARDDIR)/tlb.c $(obj)tlb_table.c
+$(obj)/law.c:
+	@rm -f $@
+	ln -sf $(srctree)/board/$(BOARDDIR)/law.c $@
 
-ifneq ($(OBJTREE), $(SRCTREE))
-$(obj)nand_boot.c:
-	@rm -f $(obj)nand_boot.c
-	ln -s $(SRCTREE)/nand_spl/board/$(BOARDDIR)/nand_boot.c $(obj)nand_boot.c
-endif
+$(obj)/nand_boot_fsl_elbc.c:
+	@rm -f $@
+	ln -sf $(srctree)/nand_spl/nand_boot_fsl_elbc.c $@
 
-#########################################################################
+$(obj)/ns16550.c:
+	@rm -f $@
+	ln -sf $(srctree)/drivers/serial/ns16550.c $@
 
-$(obj)%.o:	$(obj)%.S
-	$(CC) $(AFLAGS) -c -o $@ $<
+$(obj)/resetvec.S:
+	@rm -f $@
+	ln -s $(srctree)/$(CPUDIR)/resetvec.S $@
 
-$(obj)%.o:	$(obj)%.c
-	$(CC) $(CFLAGS) -c -o $@ $<
+$(obj)/fixed_ivor.S:
+	@rm -f $@
+	ln -sf $(srctree)/arch/powerpc/cpu/mpc85xx/fixed_ivor.S $@
 
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
+$(obj)/start.S: $(obj)/fixed_ivor.S
+	@rm -f $@
+	ln -sf $(srctree)/arch/powerpc/cpu/mpc85xx/start.S $@
 
-sinclude $(obj).depend
+$(obj)/tlb.c:
+	@rm -f $@
+	ln -sf $(srctree)/arch/powerpc/cpu/mpc85xx/tlb.c $@
 
-#########################################################################
+$(obj)/tlb_table.c:
+	@rm -f $@
+	ln -sf $(srctree)/board/$(BOARDDIR)/tlb.c $@
diff --git a/nand_spl/board/freescale/mpc8569mds/Makefile b/nand_spl/board/freescale/mpc8569mds/Makefile
index d3dac2074c..c639b126fd 100644
--- a/nand_spl/board/freescale/mpc8569mds/Makefile
+++ b/nand_spl/board/freescale/mpc8569mds/Makefile
@@ -7,116 +7,89 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-NAND_SPL := y
 CONFIG_SYS_TEXT_BASE_SPL := 0xfff00000
 PAD_TO := 0xfff01000
 
-include $(TOPDIR)/config.mk
+nandobj	:= $(objtree)/nand_spl/
 
-nandobj	:= $(OBJTREE)/nand_spl/
-
-LDSCRIPT= $(TOPDIR)/$(CPUDIR)/u-boot-nand_spl.lds
+LDSCRIPT= $(srctree)/$(CPUDIR)/u-boot-nand_spl.lds
 LDFLAGS := -T $(nandobj)u-boot-nand_spl.lds -Ttext $(CONFIG_SYS_TEXT_BASE_SPL) \
 		$(LDFLAGS) $(LDFLAGS_FINAL)
-AFLAGS	+= -DCONFIG_NAND_SPL
-CFLAGS	+= -DCONFIG_NAND_SPL
+asflags-y += -DCONFIG_NAND_SPL
+ccflags-y += -DCONFIG_NAND_SPL
 
 SOBJS	= start.o resetvec.o
 COBJS	= cache.o cpu_init_early.o spl_minimal.o fsl_law.o law.o \
 	  nand_boot.o nand_boot_fsl_elbc.o ns16550.o tlb.o tlb_table.o
 
-SRCS	:= $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c))
-OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS))
+OBJS	:= $(addprefix $(obj)/,$(SOBJS) $(COBJS))
 __OBJS	:= $(SOBJS) $(COBJS)
 LNDIR	:= $(nandobj)board/$(BOARDDIR)
 
-ALL	= $(nandobj)u-boot-spl $(nandobj)u-boot-spl.bin $(nandobj)u-boot-spl-16k.bin
+targets += $(__OBJS)
 
-all:	$(obj).depend $(ALL)
+all: $(nandobj)u-boot-spl.bin $(nandobj)u-boot-spl-16k.bin
 
 $(nandobj)u-boot-spl-16k.bin: $(nandobj)u-boot-spl
-	$(OBJCOPY) ${OBJCFLAGS} --pad-to=$(PAD_TO) -O binary $< $@
+	$(OBJCOPY) $(OBJCOPYFLAGS) --pad-to=$(PAD_TO) -O binary $< $@
 
 $(nandobj)u-boot-spl.bin:	$(nandobj)u-boot-spl
-	$(OBJCOPY) ${OBJCFLAGS} -O binary $< $@
+	$(OBJCOPY) $(OBJCOPYFLAGS) -O binary $< $@
 
 $(nandobj)u-boot-spl:	$(OBJS) $(nandobj)u-boot-nand_spl.lds
 	cd $(LNDIR) && $(LD) $(LDFLAGS) $(__OBJS) $(PLATFORM_LIBS) \
-		-Map $(nandobj)u-boot-spl.map \
-		-o $(nandobj)u-boot-spl
+		-Map $(nandobj)u-boot-spl.map -o $@
 
 $(nandobj)u-boot-nand_spl.lds: $(LDSCRIPT)
-	$(CPP) $(CPPFLAGS) $(LDPPFLAGS) -I$(nandobj)/board/$(BOARDDIR) \
+	$(CPP) $(cpp_flags) $(LDPPFLAGS) -I$(nandobj)/board/$(BOARDDIR) \
 		-ansi -D__ASSEMBLY__ -P - <$< >$@
 
 # create symbolic links for common files
 
-$(obj)cache.c:
-	@rm -f $(obj)cache.c
-	ln -sf $(SRCTREE)/arch/powerpc/lib/cache.c $(obj)cache.c
-
-$(obj)cpu_init_early.c:
-	@rm -f $(obj)cpu_init_early.c
-	ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/cpu_init_early.c $(obj)cpu_init_early.c
-
-$(obj)spl_minimal.c:
-	@rm -f $(obj)spl_minimal.c
-	ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/spl_minimal.c $(obj)spl_minimal.c
-
-$(obj)fsl_law.c:
-	@rm -f $(obj)fsl_law.c
-	ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc8xxx/law.c $(obj)fsl_law.c
-
-$(obj)law.c:
-	@rm -f $(obj)law.c
-	ln -sf $(SRCTREE)/board/$(BOARDDIR)/law.c $(obj)law.c
-
-$(obj)nand_boot_fsl_elbc.c:
-	@rm -f $(obj)nand_boot_fsl_elbc.c
-	ln -sf $(SRCTREE)/nand_spl/nand_boot_fsl_elbc.c \
-	       $(obj)nand_boot_fsl_elbc.c
-
-$(obj)ns16550.c:
-	@rm -f $(obj)ns16550.c
-	ln -sf $(SRCTREE)/drivers/serial/ns16550.c $(obj)ns16550.c
-
-$(obj)resetvec.S:
-	@rm -f $(obj)resetvec.S
-	ln -s $(SRCTREE)/$(CPUDIR)/resetvec.S $(obj)resetvec.S
+$(obj)/cache.c:
+	@rm -f $@
+	ln -sf $(srctree)/arch/powerpc/lib/cache.c $@
 
-$(obj)fixed_ivor.S:
-	@rm -f $(obj)fixed_ivor.S
-	ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/fixed_ivor.S $(obj)fixed_ivor.S
+$(obj)/cpu_init_early.c:
+	@rm -f $@
+	ln -sf $(srctree)/arch/powerpc/cpu/mpc85xx/cpu_init_early.c $@
 
-$(obj)start.S: $(obj)fixed_ivor.S
-	@rm -f $(obj)start.S
-	ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/start.S $(obj)start.S
+$(obj)/spl_minimal.c:
+	@rm -f $@
+	ln -sf $(srctree)/arch/powerpc/cpu/mpc85xx/spl_minimal.c $@
 
-$(obj)tlb.c:
-	@rm -f $(obj)tlb.c
-	ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/tlb.c $(obj)tlb.c
+$(obj)/fsl_law.c:
+	@rm -f $@
+	ln -sf $(srctree)/arch/powerpc/cpu/mpc8xxx/law.c $@
 
-$(obj)tlb_table.c:
-	@rm -f $(obj)tlb_table.c
-	ln -sf $(SRCTREE)/board/$(BOARDDIR)/tlb.c $(obj)tlb_table.c
+$(obj)/law.c:
+	@rm -f $@
+	ln -sf $(srctree)/board/$(BOARDDIR)/law.c $@
 
-ifneq ($(OBJTREE), $(SRCTREE))
-$(obj)nand_boot.c:
-	@rm -f $(obj)nand_boot.c
-	ln -s $(SRCTREE)/nand_spl/board/$(BOARDDIR)/nand_boot.c $(obj)nand_boot.c
-endif
+$(obj)/nand_boot_fsl_elbc.c:
+	@rm -f $@
+	ln -sf $(srctree)/nand_spl/nand_boot_fsl_elbc.c $@
 
-#########################################################################
+$(obj)/ns16550.c:
+	@rm -f $@
+	ln -sf $(srctree)/drivers/serial/ns16550.c $@
 
-$(obj)%.o:	$(obj)%.S
-	$(CC) $(AFLAGS) -c -o $@ $<
+$(obj)/resetvec.S:
+	@rm -f $@
+	ln -s $(srctree)/$(CPUDIR)/resetvec.S $@
 
-$(obj)%.o:	$(obj)%.c
-	$(CC) $(CFLAGS) -c -o $@ $<
+$(obj)/fixed_ivor.S:
+	@rm -f $@
+	ln -sf $(srctree)/arch/powerpc/cpu/mpc85xx/fixed_ivor.S $@
 
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
+$(obj)/start.S: $(obj)/fixed_ivor.S
+	@rm -f $@
+	ln -sf $(srctree)/arch/powerpc/cpu/mpc85xx/start.S $@
 
-sinclude $(obj).depend
+$(obj)/tlb.c:
+	@rm -f $@
+	ln -sf $(srctree)/arch/powerpc/cpu/mpc85xx/tlb.c $@
 
-#########################################################################
+$(obj)/tlb_table.c:
+	@rm -f $@
+	ln -sf $(srctree)/board/$(BOARDDIR)/tlb.c $@
diff --git a/nand_spl/board/freescale/mpc8569mds/nand_boot.c b/nand_spl/board/freescale/mpc8569mds/nand_boot.c
index 716b737ad2..ce7f6191ca 100644
--- a/nand_spl/board/freescale/mpc8569mds/nand_boot.c
+++ b/nand_spl/board/freescale/mpc8569mds/nand_boot.c
@@ -10,7 +10,7 @@
 #include <nand.h>
 #include <asm/mmu.h>
 #include <asm/immap_85xx.h>
-#include <asm/fsl_ddr_sdram.h>
+#include <fsl_ddr_sdram.h>
 #include <asm/fsl_law.h>
 
 #define SYSCLK_66       66666666
diff --git a/nand_spl/board/freescale/mpc8572ds/Makefile b/nand_spl/board/freescale/mpc8572ds/Makefile
index d3dac2074c..c639b126fd 100644
--- a/nand_spl/board/freescale/mpc8572ds/Makefile
+++ b/nand_spl/board/freescale/mpc8572ds/Makefile
@@ -7,116 +7,89 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-NAND_SPL := y
 CONFIG_SYS_TEXT_BASE_SPL := 0xfff00000
 PAD_TO := 0xfff01000
 
-include $(TOPDIR)/config.mk
+nandobj	:= $(objtree)/nand_spl/
 
-nandobj	:= $(OBJTREE)/nand_spl/
-
-LDSCRIPT= $(TOPDIR)/$(CPUDIR)/u-boot-nand_spl.lds
+LDSCRIPT= $(srctree)/$(CPUDIR)/u-boot-nand_spl.lds
 LDFLAGS := -T $(nandobj)u-boot-nand_spl.lds -Ttext $(CONFIG_SYS_TEXT_BASE_SPL) \
 		$(LDFLAGS) $(LDFLAGS_FINAL)
-AFLAGS	+= -DCONFIG_NAND_SPL
-CFLAGS	+= -DCONFIG_NAND_SPL
+asflags-y += -DCONFIG_NAND_SPL
+ccflags-y += -DCONFIG_NAND_SPL
 
 SOBJS	= start.o resetvec.o
 COBJS	= cache.o cpu_init_early.o spl_minimal.o fsl_law.o law.o \
 	  nand_boot.o nand_boot_fsl_elbc.o ns16550.o tlb.o tlb_table.o
 
-SRCS	:= $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c))
-OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS))
+OBJS	:= $(addprefix $(obj)/,$(SOBJS) $(COBJS))
 __OBJS	:= $(SOBJS) $(COBJS)
 LNDIR	:= $(nandobj)board/$(BOARDDIR)
 
-ALL	= $(nandobj)u-boot-spl $(nandobj)u-boot-spl.bin $(nandobj)u-boot-spl-16k.bin
+targets += $(__OBJS)
 
-all:	$(obj).depend $(ALL)
+all: $(nandobj)u-boot-spl.bin $(nandobj)u-boot-spl-16k.bin
 
 $(nandobj)u-boot-spl-16k.bin: $(nandobj)u-boot-spl
-	$(OBJCOPY) ${OBJCFLAGS} --pad-to=$(PAD_TO) -O binary $< $@
+	$(OBJCOPY) $(OBJCOPYFLAGS) --pad-to=$(PAD_TO) -O binary $< $@
 
 $(nandobj)u-boot-spl.bin:	$(nandobj)u-boot-spl
-	$(OBJCOPY) ${OBJCFLAGS} -O binary $< $@
+	$(OBJCOPY) $(OBJCOPYFLAGS) -O binary $< $@
 
 $(nandobj)u-boot-spl:	$(OBJS) $(nandobj)u-boot-nand_spl.lds
 	cd $(LNDIR) && $(LD) $(LDFLAGS) $(__OBJS) $(PLATFORM_LIBS) \
-		-Map $(nandobj)u-boot-spl.map \
-		-o $(nandobj)u-boot-spl
+		-Map $(nandobj)u-boot-spl.map -o $@
 
 $(nandobj)u-boot-nand_spl.lds: $(LDSCRIPT)
-	$(CPP) $(CPPFLAGS) $(LDPPFLAGS) -I$(nandobj)/board/$(BOARDDIR) \
+	$(CPP) $(cpp_flags) $(LDPPFLAGS) -I$(nandobj)/board/$(BOARDDIR) \
 		-ansi -D__ASSEMBLY__ -P - <$< >$@
 
 # create symbolic links for common files
 
-$(obj)cache.c:
-	@rm -f $(obj)cache.c
-	ln -sf $(SRCTREE)/arch/powerpc/lib/cache.c $(obj)cache.c
-
-$(obj)cpu_init_early.c:
-	@rm -f $(obj)cpu_init_early.c
-	ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/cpu_init_early.c $(obj)cpu_init_early.c
-
-$(obj)spl_minimal.c:
-	@rm -f $(obj)spl_minimal.c
-	ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/spl_minimal.c $(obj)spl_minimal.c
-
-$(obj)fsl_law.c:
-	@rm -f $(obj)fsl_law.c
-	ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc8xxx/law.c $(obj)fsl_law.c
-
-$(obj)law.c:
-	@rm -f $(obj)law.c
-	ln -sf $(SRCTREE)/board/$(BOARDDIR)/law.c $(obj)law.c
-
-$(obj)nand_boot_fsl_elbc.c:
-	@rm -f $(obj)nand_boot_fsl_elbc.c
-	ln -sf $(SRCTREE)/nand_spl/nand_boot_fsl_elbc.c \
-	       $(obj)nand_boot_fsl_elbc.c
-
-$(obj)ns16550.c:
-	@rm -f $(obj)ns16550.c
-	ln -sf $(SRCTREE)/drivers/serial/ns16550.c $(obj)ns16550.c
-
-$(obj)resetvec.S:
-	@rm -f $(obj)resetvec.S
-	ln -s $(SRCTREE)/$(CPUDIR)/resetvec.S $(obj)resetvec.S
+$(obj)/cache.c:
+	@rm -f $@
+	ln -sf $(srctree)/arch/powerpc/lib/cache.c $@
 
-$(obj)fixed_ivor.S:
-	@rm -f $(obj)fixed_ivor.S
-	ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/fixed_ivor.S $(obj)fixed_ivor.S
+$(obj)/cpu_init_early.c:
+	@rm -f $@
+	ln -sf $(srctree)/arch/powerpc/cpu/mpc85xx/cpu_init_early.c $@
 
-$(obj)start.S: $(obj)fixed_ivor.S
-	@rm -f $(obj)start.S
-	ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/start.S $(obj)start.S
+$(obj)/spl_minimal.c:
+	@rm -f $@
+	ln -sf $(srctree)/arch/powerpc/cpu/mpc85xx/spl_minimal.c $@
 
-$(obj)tlb.c:
-	@rm -f $(obj)tlb.c
-	ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/tlb.c $(obj)tlb.c
+$(obj)/fsl_law.c:
+	@rm -f $@
+	ln -sf $(srctree)/arch/powerpc/cpu/mpc8xxx/law.c $@
 
-$(obj)tlb_table.c:
-	@rm -f $(obj)tlb_table.c
-	ln -sf $(SRCTREE)/board/$(BOARDDIR)/tlb.c $(obj)tlb_table.c
+$(obj)/law.c:
+	@rm -f $@
+	ln -sf $(srctree)/board/$(BOARDDIR)/law.c $@
 
-ifneq ($(OBJTREE), $(SRCTREE))
-$(obj)nand_boot.c:
-	@rm -f $(obj)nand_boot.c
-	ln -s $(SRCTREE)/nand_spl/board/$(BOARDDIR)/nand_boot.c $(obj)nand_boot.c
-endif
+$(obj)/nand_boot_fsl_elbc.c:
+	@rm -f $@
+	ln -sf $(srctree)/nand_spl/nand_boot_fsl_elbc.c $@
 
-#########################################################################
+$(obj)/ns16550.c:
+	@rm -f $@
+	ln -sf $(srctree)/drivers/serial/ns16550.c $@
 
-$(obj)%.o:	$(obj)%.S
-	$(CC) $(AFLAGS) -c -o $@ $<
+$(obj)/resetvec.S:
+	@rm -f $@
+	ln -s $(srctree)/$(CPUDIR)/resetvec.S $@
 
-$(obj)%.o:	$(obj)%.c
-	$(CC) $(CFLAGS) -c -o $@ $<
+$(obj)/fixed_ivor.S:
+	@rm -f $@
+	ln -sf $(srctree)/arch/powerpc/cpu/mpc85xx/fixed_ivor.S $@
 
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
+$(obj)/start.S: $(obj)/fixed_ivor.S
+	@rm -f $@
+	ln -sf $(srctree)/arch/powerpc/cpu/mpc85xx/start.S $@
 
-sinclude $(obj).depend
+$(obj)/tlb.c:
+	@rm -f $@
+	ln -sf $(srctree)/arch/powerpc/cpu/mpc85xx/tlb.c $@
 
-#########################################################################
+$(obj)/tlb_table.c:
+	@rm -f $@
+	ln -sf $(srctree)/board/$(BOARDDIR)/tlb.c $@
diff --git a/nand_spl/board/freescale/p1023rds/Makefile b/nand_spl/board/freescale/p1023rds/Makefile
index e89d4054ab..38f6726449 100644
--- a/nand_spl/board/freescale/p1023rds/Makefile
+++ b/nand_spl/board/freescale/p1023rds/Makefile
@@ -3,115 +3,89 @@
 #
 # SPDX-License-Identifier:	GPL-2.0+
 #
-NAND_SPL := y
-PAD_TO := 0xfff01000
 
-include $(TOPDIR)/config.mk
+PAD_TO := 0xfff01000
 
-nandobj	:= $(OBJTREE)/nand_spl/
+nandobj	:= $(objtree)/nand_spl/
 
-LDSCRIPT= $(TOPDIR)/$(CPUDIR)/u-boot-nand_spl.lds
+LDSCRIPT= $(srctree)/$(CPUDIR)/u-boot-nand_spl.lds
 LDFLAGS := -T $(nandobj)u-boot-nand_spl.lds -Ttext $(CONFIG_SYS_TEXT_BASE_SPL) \
 		$(LDFLAGS) $(LDFLAGS_FINAL)
-AFLAGS	+= -DCONFIG_NAND_SPL
-CFLAGS	+= -DCONFIG_NAND_SPL
+asflags-y += -DCONFIG_NAND_SPL
+ccflags-y += -DCONFIG_NAND_SPL
 
 SOBJS	= start.o resetvec.o
 COBJS	= cache.o cpu_init_early.o spl_minimal.o fsl_law.o law.o \
 	  nand_boot.o nand_boot_fsl_elbc.o ns16550.o tlb.o tlb_table.o
 
-SRCS	:= $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c))
-OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS))
+OBJS	:= $(addprefix $(obj)/,$(SOBJS) $(COBJS))
 __OBJS	:= $(SOBJS) $(COBJS)
 LNDIR	:= $(nandobj)board/$(BOARDDIR)
 
-ALL	= $(nandobj)u-boot-spl $(nandobj)u-boot-spl.bin $(nandobj)u-boot-spl-16k.bin
+targets += $(__OBJS)
 
-all:	$(obj).depend $(ALL)
+all: $(nandobj)u-boot-spl.bin $(nandobj)u-boot-spl-16k.bin
 
 $(nandobj)u-boot-spl-16k.bin: $(nandobj)u-boot-spl
-	$(OBJCOPY) ${OBJCFLAGS} --pad-to=$(PAD_TO) -O binary $< $@
+	$(OBJCOPY) $(OBJCOPYFLAGS) --pad-to=$(PAD_TO) -O binary $< $@
 
 $(nandobj)u-boot-spl.bin:	$(nandobj)u-boot-spl
-	$(OBJCOPY) ${OBJCFLAGS} -O binary $< $@
+	$(OBJCOPY) $(OBJCOPYFLAGS) -O binary $< $@
 
 $(nandobj)u-boot-spl:	$(OBJS) $(nandobj)u-boot-nand_spl.lds
 	cd $(LNDIR) && $(LD) $(LDFLAGS) $(__OBJS) $(PLATFORM_LIBS) \
-		-Map $(nandobj)u-boot-spl.map \
-		-o $(nandobj)u-boot-spl
+		-Map $(nandobj)u-boot-spl.map -o $@
 
 $(nandobj)u-boot-nand_spl.lds: $(LDSCRIPT)
-	$(CPP) $(CPPFLAGS) $(LDPPFLAGS) -I$(nandobj)/board/$(BOARDDIR) \
+	$(CPP) $(cpp_flags) $(LDPPFLAGS) -I$(nandobj)/board/$(BOARDDIR) \
 		-ansi -D__ASSEMBLY__ -P - <$< >$@
 
 # create symbolic links for common files
 
-$(obj)cache.c:
-	@rm -f $(obj)cache.c
-	ln -sf $(SRCTREE)/arch/powerpc/lib/cache.c $(obj)cache.c
-
-$(obj)cpu_init_early.c:
-	@rm -f $(obj)cpu_init_early.c
-	ln -sf $(SRCTREE)/$(CPUDIR)/cpu_init_early.c $(obj)cpu_init_early.c
-
-$(obj)spl_minimal.c:
-	@rm -f $(obj)spl_minimal.c
-	ln -sf $(SRCTREE)/$(CPUDIR)/spl_minimal.c $(obj)spl_minimal.c
-
-$(obj)fsl_law.c:
-	@rm -f $(obj)fsl_law.c
-	ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc8xxx/law.c $(obj)fsl_law.c
-
-$(obj)law.c:
-	@rm -f $(obj)law.c
-	ln -sf $(SRCTREE)/board/$(BOARDDIR)/law.c $(obj)law.c
-
-$(obj)nand_boot_fsl_elbc.c:
-	@rm -f $(obj)nand_boot_fsl_elbc.c
-	ln -sf $(SRCTREE)/nand_spl/nand_boot_fsl_elbc.c \
-	       $(obj)nand_boot_fsl_elbc.c
-
-$(obj)ns16550.c:
-	@rm -f $(obj)ns16550.c
-	ln -sf $(SRCTREE)/drivers/serial/ns16550.c $(obj)ns16550.c
-
-$(obj)resetvec.S:
-	@rm -f $(obj)resetvec.S
-	ln -s $(SRCTREE)/$(CPUDIR)/resetvec.S $(obj)resetvec.S
+$(obj)/cache.c:
+	@rm -f $@
+	ln -sf $(srctree)/arch/powerpc/lib/cache.c $@
 
-$(obj)fixed_ivor.S:
-	@rm -f $(obj)fixed_ivor.S
-	ln -sf $(SRCTREE)/$(CPUDIR)/fixed_ivor.S $(obj)fixed_ivor.S
+$(obj)/cpu_init_early.c:
+	@rm -f $@
+	ln -sf $(srctree)/$(CPUDIR)/cpu_init_early.c $@
 
-$(obj)start.S: $(obj)fixed_ivor.S
-	@rm -f $(obj)start.S
-	ln -sf $(SRCTREE)/$(CPUDIR)/start.S $(obj)start.S
+$(obj)/spl_minimal.c:
+	@rm -f $@
+	ln -sf $(srctree)/$(CPUDIR)/spl_minimal.c $@
 
-$(obj)tlb.c:
-	@rm -f $(obj)tlb.c
-	ln -sf $(SRCTREE)/$(CPUDIR)/tlb.c $(obj)tlb.c
+$(obj)/fsl_law.c:
+	@rm -f $@
+	ln -sf $(srctree)/arch/powerpc/cpu/mpc8xxx/law.c $@
 
-$(obj)tlb_table.c:
-	@rm -f $(obj)tlb_table.c
-	ln -sf $(SRCTREE)/board/$(BOARDDIR)/tlb.c $(obj)tlb_table.c
+$(obj)/law.c:
+	@rm -f $@
+	ln -sf $(srctree)/board/$(BOARDDIR)/law.c $@
 
-ifneq ($(OBJTREE), $(SRCTREE))
-$(obj)nand_boot.c:
-	@rm -f $(obj)nand_boot.c
-	ln -s $(SRCTREE)/nand_spl/board/$(BOARDDIR)/nand_boot.c $(obj)nand_boot.c
-endif
+$(obj)/nand_boot_fsl_elbc.c:
+	@rm -f $@
+	ln -sf $(srctree)/nand_spl/nand_boot_fsl_elbc.c $@
 
-#########################################################################
+$(obj)/ns16550.c:
+	@rm -f $@
+	ln -sf $(srctree)/drivers/serial/ns16550.c $@
 
-$(obj)%.o:	$(obj)%.S
-	$(CC) $(AFLAGS) -c -o $@ $<
+$(obj)/resetvec.S:
+	@rm -f $@
+	ln -s $(srctree)/$(CPUDIR)/resetvec.S $@
 
-$(obj)%.o:	$(obj)%.c
-	$(CC) $(CFLAGS) -c -o $@ $<
+$(obj)/fixed_ivor.S:
+	@rm -f $@
+	ln -sf $(srctree)/$(CPUDIR)/fixed_ivor.S $@
 
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
+$(obj)/start.S: $(obj)/fixed_ivor.S
+	@rm -f $@
+	ln -sf $(srctree)/$(CPUDIR)/start.S $@
 
-sinclude $(obj).depend
+$(obj)/tlb.c:
+	@rm -f $@
+	ln -sf $(srctree)/$(CPUDIR)/tlb.c $@
 
-#########################################################################
+$(obj)/tlb_table.c:
+	@rm -f $@
+	ln -sf $(srctree)/board/$(BOARDDIR)/tlb.c $@
diff --git a/nand_spl/board/freescale/p1023rds/nand_boot.c b/nand_spl/board/freescale/p1023rds/nand_boot.c
index 94680004f7..d9afa6d024 100644
--- a/nand_spl/board/freescale/p1023rds/nand_boot.c
+++ b/nand_spl/board/freescale/p1023rds/nand_boot.c
@@ -10,7 +10,7 @@
 #include <asm/io.h>
 #include <nand.h>
 #include <asm/fsl_law.h>
-#include <asm/fsl_ddr_sdram.h>
+#include <fsl_ddr_sdram.h>
 #include <asm/global_data.h>
 
 DECLARE_GLOBAL_DATA_PTR;
@@ -18,7 +18,8 @@ DECLARE_GLOBAL_DATA_PTR;
 /* Fixed sdram init -- doesn't use serial presence detect. */
 void sdram_init(void)
 {
-	ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_MPC8xxx_DDR_ADDR;
+	struct ccsr_ddr __iomem *ddr =
+		(struct ccsr_ddr __iomem *)CONFIG_SYS_FSL_DDR_ADDR;
 
 	set_next_law(0, LAW_SIZE_2G, LAW_TRGT_IF_DDR_1);
 
diff --git a/nand_spl/board/freescale/p1_p2_rdb/Makefile b/nand_spl/board/freescale/p1_p2_rdb/Makefile
index d3dac2074c..c639b126fd 100644
--- a/nand_spl/board/freescale/p1_p2_rdb/Makefile
+++ b/nand_spl/board/freescale/p1_p2_rdb/Makefile
@@ -7,116 +7,89 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-NAND_SPL := y
 CONFIG_SYS_TEXT_BASE_SPL := 0xfff00000
 PAD_TO := 0xfff01000
 
-include $(TOPDIR)/config.mk
+nandobj	:= $(objtree)/nand_spl/
 
-nandobj	:= $(OBJTREE)/nand_spl/
-
-LDSCRIPT= $(TOPDIR)/$(CPUDIR)/u-boot-nand_spl.lds
+LDSCRIPT= $(srctree)/$(CPUDIR)/u-boot-nand_spl.lds
 LDFLAGS := -T $(nandobj)u-boot-nand_spl.lds -Ttext $(CONFIG_SYS_TEXT_BASE_SPL) \
 		$(LDFLAGS) $(LDFLAGS_FINAL)
-AFLAGS	+= -DCONFIG_NAND_SPL
-CFLAGS	+= -DCONFIG_NAND_SPL
+asflags-y += -DCONFIG_NAND_SPL
+ccflags-y += -DCONFIG_NAND_SPL
 
 SOBJS	= start.o resetvec.o
 COBJS	= cache.o cpu_init_early.o spl_minimal.o fsl_law.o law.o \
 	  nand_boot.o nand_boot_fsl_elbc.o ns16550.o tlb.o tlb_table.o
 
-SRCS	:= $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c))
-OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS))
+OBJS	:= $(addprefix $(obj)/,$(SOBJS) $(COBJS))
 __OBJS	:= $(SOBJS) $(COBJS)
 LNDIR	:= $(nandobj)board/$(BOARDDIR)
 
-ALL	= $(nandobj)u-boot-spl $(nandobj)u-boot-spl.bin $(nandobj)u-boot-spl-16k.bin
+targets += $(__OBJS)
 
-all:	$(obj).depend $(ALL)
+all: $(nandobj)u-boot-spl.bin $(nandobj)u-boot-spl-16k.bin
 
 $(nandobj)u-boot-spl-16k.bin: $(nandobj)u-boot-spl
-	$(OBJCOPY) ${OBJCFLAGS} --pad-to=$(PAD_TO) -O binary $< $@
+	$(OBJCOPY) $(OBJCOPYFLAGS) --pad-to=$(PAD_TO) -O binary $< $@
 
 $(nandobj)u-boot-spl.bin:	$(nandobj)u-boot-spl
-	$(OBJCOPY) ${OBJCFLAGS} -O binary $< $@
+	$(OBJCOPY) $(OBJCOPYFLAGS) -O binary $< $@
 
 $(nandobj)u-boot-spl:	$(OBJS) $(nandobj)u-boot-nand_spl.lds
 	cd $(LNDIR) && $(LD) $(LDFLAGS) $(__OBJS) $(PLATFORM_LIBS) \
-		-Map $(nandobj)u-boot-spl.map \
-		-o $(nandobj)u-boot-spl
+		-Map $(nandobj)u-boot-spl.map -o $@
 
 $(nandobj)u-boot-nand_spl.lds: $(LDSCRIPT)
-	$(CPP) $(CPPFLAGS) $(LDPPFLAGS) -I$(nandobj)/board/$(BOARDDIR) \
+	$(CPP) $(cpp_flags) $(LDPPFLAGS) -I$(nandobj)/board/$(BOARDDIR) \
 		-ansi -D__ASSEMBLY__ -P - <$< >$@
 
 # create symbolic links for common files
 
-$(obj)cache.c:
-	@rm -f $(obj)cache.c
-	ln -sf $(SRCTREE)/arch/powerpc/lib/cache.c $(obj)cache.c
-
-$(obj)cpu_init_early.c:
-	@rm -f $(obj)cpu_init_early.c
-	ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/cpu_init_early.c $(obj)cpu_init_early.c
-
-$(obj)spl_minimal.c:
-	@rm -f $(obj)spl_minimal.c
-	ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/spl_minimal.c $(obj)spl_minimal.c
-
-$(obj)fsl_law.c:
-	@rm -f $(obj)fsl_law.c
-	ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc8xxx/law.c $(obj)fsl_law.c
-
-$(obj)law.c:
-	@rm -f $(obj)law.c
-	ln -sf $(SRCTREE)/board/$(BOARDDIR)/law.c $(obj)law.c
-
-$(obj)nand_boot_fsl_elbc.c:
-	@rm -f $(obj)nand_boot_fsl_elbc.c
-	ln -sf $(SRCTREE)/nand_spl/nand_boot_fsl_elbc.c \
-	       $(obj)nand_boot_fsl_elbc.c
-
-$(obj)ns16550.c:
-	@rm -f $(obj)ns16550.c
-	ln -sf $(SRCTREE)/drivers/serial/ns16550.c $(obj)ns16550.c
-
-$(obj)resetvec.S:
-	@rm -f $(obj)resetvec.S
-	ln -s $(SRCTREE)/$(CPUDIR)/resetvec.S $(obj)resetvec.S
+$(obj)/cache.c:
+	@rm -f $@
+	ln -sf $(srctree)/arch/powerpc/lib/cache.c $@
 
-$(obj)fixed_ivor.S:
-	@rm -f $(obj)fixed_ivor.S
-	ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/fixed_ivor.S $(obj)fixed_ivor.S
+$(obj)/cpu_init_early.c:
+	@rm -f $@
+	ln -sf $(srctree)/arch/powerpc/cpu/mpc85xx/cpu_init_early.c $@
 
-$(obj)start.S: $(obj)fixed_ivor.S
-	@rm -f $(obj)start.S
-	ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/start.S $(obj)start.S
+$(obj)/spl_minimal.c:
+	@rm -f $@
+	ln -sf $(srctree)/arch/powerpc/cpu/mpc85xx/spl_minimal.c $@
 
-$(obj)tlb.c:
-	@rm -f $(obj)tlb.c
-	ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/tlb.c $(obj)tlb.c
+$(obj)/fsl_law.c:
+	@rm -f $@
+	ln -sf $(srctree)/arch/powerpc/cpu/mpc8xxx/law.c $@
 
-$(obj)tlb_table.c:
-	@rm -f $(obj)tlb_table.c
-	ln -sf $(SRCTREE)/board/$(BOARDDIR)/tlb.c $(obj)tlb_table.c
+$(obj)/law.c:
+	@rm -f $@
+	ln -sf $(srctree)/board/$(BOARDDIR)/law.c $@
 
-ifneq ($(OBJTREE), $(SRCTREE))
-$(obj)nand_boot.c:
-	@rm -f $(obj)nand_boot.c
-	ln -s $(SRCTREE)/nand_spl/board/$(BOARDDIR)/nand_boot.c $(obj)nand_boot.c
-endif
+$(obj)/nand_boot_fsl_elbc.c:
+	@rm -f $@
+	ln -sf $(srctree)/nand_spl/nand_boot_fsl_elbc.c $@
 
-#########################################################################
+$(obj)/ns16550.c:
+	@rm -f $@
+	ln -sf $(srctree)/drivers/serial/ns16550.c $@
 
-$(obj)%.o:	$(obj)%.S
-	$(CC) $(AFLAGS) -c -o $@ $<
+$(obj)/resetvec.S:
+	@rm -f $@
+	ln -s $(srctree)/$(CPUDIR)/resetvec.S $@
 
-$(obj)%.o:	$(obj)%.c
-	$(CC) $(CFLAGS) -c -o $@ $<
+$(obj)/fixed_ivor.S:
+	@rm -f $@
+	ln -sf $(srctree)/arch/powerpc/cpu/mpc85xx/fixed_ivor.S $@
 
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
+$(obj)/start.S: $(obj)/fixed_ivor.S
+	@rm -f $@
+	ln -sf $(srctree)/arch/powerpc/cpu/mpc85xx/start.S $@
 
-sinclude $(obj).depend
+$(obj)/tlb.c:
+	@rm -f $@
+	ln -sf $(srctree)/arch/powerpc/cpu/mpc85xx/tlb.c $@
 
-#########################################################################
+$(obj)/tlb_table.c:
+	@rm -f $@
+	ln -sf $(srctree)/board/$(BOARDDIR)/tlb.c $@
diff --git a/nand_spl/board/freescale/p1_p2_rdb/nand_boot.c b/nand_spl/board/freescale/p1_p2_rdb/nand_boot.c
index 3244c8f6d9..f7e8438438 100644
--- a/nand_spl/board/freescale/p1_p2_rdb/nand_boot.c
+++ b/nand_spl/board/freescale/p1_p2_rdb/nand_boot.c
@@ -10,7 +10,7 @@
 #include <nand.h>
 #include <asm/mmu.h>
 #include <asm/immap_85xx.h>
-#include <asm/fsl_ddr_sdram.h>
+#include <fsl_ddr_sdram.h>
 #include <asm/fsl_law.h>
 
 #define SYSCLK_MASK     0x00200000
diff --git a/nand_spl/board/sheldon/simpc8313/Makefile b/nand_spl/board/sheldon/simpc8313/Makefile
index 08739edc4e..657f65fd22 100644
--- a/nand_spl/board/sheldon/simpc8313/Makefile
+++ b/nand_spl/board/sheldon/simpc8313/Makefile
@@ -7,94 +7,75 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-NAND_SPL := y
+include $(srctree)/$(src)/config.mk
 
-include $(TOPDIR)/config.mk
+nandobj	:= $(objtree)/nand_spl/
 
-nandobj	:= $(OBJTREE)/nand_spl/
-
-LDSCRIPT= $(TOPDIR)/nand_spl/board/$(BOARDDIR)/u-boot.lds
+LDSCRIPT= $(srctree)/nand_spl/board/$(BOARDDIR)/u-boot.lds
 LDFLAGS := -T $(nandobj)u-boot.lds -Ttext $(CONFIG_SYS_TEXT_BASE_SPL) \
 	   $(LDFLAGS) $(LDFLAGS_FINAL)
-AFLAGS	+= -DCONFIG_NAND_SPL
-CFLAGS	+= -DCONFIG_NAND_SPL
+asflags-y += -DCONFIG_NAND_SPL
+ccflags-y += -DCONFIG_NAND_SPL
 
 SOBJS	= start.o ticks.o
 COBJS	= nand_boot_fsl_elbc.o $(BOARD).o sdram.o ns16550.o spl_minimal.o \
 	  time.o cache.o
 
-SRCS	:= $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c))
-OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS))
+OBJS	:= $(addprefix $(obj)/,$(SOBJS) $(COBJS))
 __OBJS	:= $(SOBJS) $(COBJS)
 LNDIR	:= $(nandobj)board/$(BOARDDIR)
 
-ALL	= $(nandobj)u-boot-spl $(nandobj)u-boot-spl.bin $(nandobj)u-boot-spl-16k.bin
+targets += $(__OBJS)
 
-all:	$(obj).depend $(ALL)
+all: $(nandobj)u-boot-spl.bin $(nandobj)u-boot-spl-16k.bin
 
 $(nandobj)u-boot-spl-16k.bin:	$(nandobj)u-boot-spl
-	$(OBJCOPY) ${OBJCFLAGS} --pad-to=$(PAD_TO) -O binary $< $@
+	$(OBJCOPY) $(OBJCOPYFLAGS) --pad-to=$(PAD_TO) -O binary $< $@
 
 $(nandobj)u-boot-spl.bin:	$(nandobj)u-boot-spl
-	$(OBJCOPY) ${OBJCFLAGS} -O binary $< $@
+	$(OBJCOPY) $(OBJCOPYFLAGS) -O binary $< $@
 
 $(nandobj)u-boot-spl:	$(OBJS) $(nandobj)u-boot.lds
 	cd $(LNDIR) && $(LD) $(LDFLAGS) $(__OBJS) $(PLATFORM_LIBS) \
-		-Map $(nandobj)u-boot-spl.map \
-		-o $(nandobj)u-boot-spl
+		-Map $(nandobj)u-boot-spl.map -o $@
 
 $(nandobj)u-boot.lds: $(LDSCRIPT)
-	$(CPP) $(CPPFLAGS) $(LDPPFLAGS) -ansi -D__ASSEMBLY__ -P - <$^ >$@
+	$(CPP) $(cpp_flags) $(LDPPFLAGS) -ansi -D__ASSEMBLY__ -P - <$^ >$@
 
 # create symbolic links for common files
 
-$(obj)start.S:
+$(obj)/start.S:
 	@rm -f $@
-	ln -s $(SRCTREE)/arch/powerpc/cpu/mpc83xx/start.S $@
+	ln -s $(srctree)/arch/powerpc/cpu/mpc83xx/start.S $@
 
-$(obj)nand_boot_fsl_elbc.c:
+$(obj)/nand_boot_fsl_elbc.c:
 	@rm -f $@
-	ln -s $(SRCTREE)/nand_spl/nand_boot_fsl_elbc.c $@
+	ln -s $(srctree)/nand_spl/nand_boot_fsl_elbc.c $@
 
-$(obj)sdram.c:
+$(obj)/sdram.c:
 	@rm -f $@
-	ln -s $(SRCTREE)/board/$(BOARDDIR)/sdram.c $@
+	ln -s $(srctree)/board/$(BOARDDIR)/sdram.c $@
 
-$(obj)$(BOARD).c:
+$(obj)/$(BOARD).c:
 	@rm -f $@
-	ln -s $(SRCTREE)/board/$(BOARDDIR)/$(BOARD).c $@
+	ln -s $(srctree)/board/$(BOARDDIR)/$(BOARD).c $@
 
-$(obj)ns16550.c:
+$(obj)/ns16550.c:
 	@rm -f $@
-	ln -s $(SRCTREE)/drivers/serial/ns16550.c $@
+	ln -s $(srctree)/drivers/serial/ns16550.c $@
 
-$(obj)spl_minimal.c:
+$(obj)/spl_minimal.c:
 	@rm -f $@
-	ln -s $(SRCTREE)/arch/powerpc/cpu/mpc83xx/spl_minimal.c $@
+	ln -s $(srctree)/arch/powerpc/cpu/mpc83xx/spl_minimal.c $@
 
-$(obj)cache.c:
+$(obj)/cache.c:
 	@rm -f $@
-	ln -s $(SRCTREE)/arch/powerpc/lib/cache.c $@
+	ln -s $(srctree)/arch/powerpc/lib/cache.c $@
 
-$(obj)time.c:
+$(obj)/time.c:
 	@rm -f $@
-	ln -s $(SRCTREE)/arch/powerpc/lib/time.c $@
+	ln -s $(srctree)/arch/powerpc/lib/time.c $@
 
-$(obj)ticks.S:
+$(obj)/ticks.S:
 	@rm -f $@
-	ln -s $(SRCTREE)/arch/powerpc/lib/ticks.S $@
-
-#########################################################################
-
-$(obj)%.o:	$(obj)%.S
-	$(CC) $(AFLAGS) -c -o $@ $<
-
-$(obj)%.o:	$(obj)%.c
-	$(CC) $(CFLAGS) -c -o $@ $<
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+	ln -s $(srctree)/arch/powerpc/lib/ticks.S $@
diff --git a/board/sheldon/simpc8313/config.mk b/nand_spl/board/sheldon/simpc8313/config.mk
index d1b4e2eeb6..d1b4e2eeb6 100644
--- a/board/sheldon/simpc8313/config.mk
+++ b/nand_spl/board/sheldon/simpc8313/config.mk
diff --git a/net/Makefile b/net/Makefile
index 4c9a97f04d..942595021d 100644
--- a/net/Makefile
+++ b/net/Makefile
@@ -5,39 +5,17 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-# CFLAGS += -DDEBUG
-
-LIB	= $(obj)libnet.o
-
-COBJS-$(CONFIG_CMD_NET)  += arp.o
-COBJS-$(CONFIG_CMD_NET)  += bootp.o
-COBJS-$(CONFIG_CMD_CDP)  += cdp.o
-COBJS-$(CONFIG_CMD_DNS)  += dns.o
-COBJS-$(CONFIG_CMD_NET)  += eth.o
-COBJS-$(CONFIG_CMD_LINK_LOCAL) += link_local.o
-COBJS-$(CONFIG_CMD_NET)  += net.o
-COBJS-$(CONFIG_CMD_NFS)  += nfs.o
-COBJS-$(CONFIG_CMD_PING) += ping.o
-COBJS-$(CONFIG_CMD_RARP) += rarp.o
-COBJS-$(CONFIG_CMD_SNTP) += sntp.o
-COBJS-$(CONFIG_CMD_NET)  += tftp.o
-
-COBJS	:= $(sort $(COBJS-y))
-SRCS	:= $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-
-all:	$(LIB)
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+#ccflags-y += -DDEBUG
+
+obj-$(CONFIG_CMD_NET)  += arp.o
+obj-$(CONFIG_CMD_NET)  += bootp.o
+obj-$(CONFIG_CMD_CDP)  += cdp.o
+obj-$(CONFIG_CMD_DNS)  += dns.o
+obj-$(CONFIG_CMD_NET)  += eth.o
+obj-$(CONFIG_CMD_LINK_LOCAL) += link_local.o
+obj-$(CONFIG_CMD_NET)  += net.o
+obj-$(CONFIG_CMD_NFS)  += nfs.o
+obj-$(CONFIG_CMD_PING) += ping.o
+obj-$(CONFIG_CMD_RARP) += rarp.o
+obj-$(CONFIG_CMD_SNTP) += sntp.o
+obj-$(CONFIG_CMD_NET)  += tftp.o
diff --git a/net/bootp.c b/net/bootp.c
index 4300f1c2f1..189a003835 100644
--- a/net/bootp.c
+++ b/net/bootp.c
@@ -439,7 +439,7 @@ static int DhcpExtended(u8 *e, int message_type, IPaddr_t ServerID,
 			*e++ = 17;
 			*e++ = 0;	/* type 0 - UUID */
 
-			uuid_str_to_bin(uuid, e);
+			uuid_str_to_bin(uuid, e, UUID_STR_FORMAT_STD);
 			e += 16;
 		} else {
 			printf("Invalid pxeuuid: %s\n", uuid);
diff --git a/net/eth.c b/net/eth.c
index c96e767e8e..32bd10c829 100644
--- a/net/eth.c
+++ b/net/eth.c
@@ -279,7 +279,7 @@ int eth_initialize(bd_t *bis)
 	eth_current = NULL;
 
 	bootstage_mark(BOOTSTAGE_ID_NET_ETH_START);
-#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
+#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) || defined(CONFIG_PHYLIB)
 	miiphy_init();
 #endif
 
diff --git a/net/tftp.c b/net/tftp.c
index 6d333d559c..966d1cfba3 100644
--- a/net/tftp.c
+++ b/net/tftp.c
@@ -281,7 +281,7 @@ static void update_block_number(void)
 	 * number of 0 this means that there was a wrap
 	 * around of the (16 bit) counter.
 	 */
-	if (TftpBlock == 0) {
+	if (TftpBlock == 0 && TftpLastBlock != 0) {
 		TftpBlockWrap++;
 		TftpBlockWrapOffset += TftpBlkSize * TFTP_SEQUENCE_SIZE;
 		TftpTimeoutCount = 0; /* we've done well, reset thhe timeout */
@@ -849,6 +849,9 @@ TftpStartServer(void)
 
 	TftpState = STATE_RECV_WRQ;
 	net_set_udp_handler(TftpHandler);
+
+	/* zero out server ether in case the server ip has changed */
+	memset(NetServerEther, 0, 6);
 }
 #endif /* CONFIG_CMD_TFTPSRV */
 
diff --git a/post/Makefile b/post/Makefile
index 0ecae5bd64..2fa6f8a295 100644
--- a/post/Makefile
+++ b/post/Makefile
@@ -5,55 +5,14 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-include $(OBJTREE)/include/autoconf.mk
-
-LIB				= libpost.o
-GPLIB-$(CONFIG_HAS_POST)	+= libgenpost.o
-COBJS-$(CONFIG_HAS_POST)	+= post.o
-COBJS-$(CONFIG_POST_STD_LIST)	+= tests.o
-
-SPLIB-$(CONFIG_HAS_POST) = drivers/libpostdrivers.o
-SPLIB-$(CONFIG_HAS_POST) += $(shell if [ -d lib_$(ARCH) ]; then echo \
-			    "lib_$(ARCH)/libpost$(ARCH).o"; fi)
-SPLIB-$(CONFIG_HAS_POST) += $(shell if [ -d lib_$(ARCH)/fpu ]; then echo \
-			    "lib_$(ARCH)/fpu/libpost$(ARCH)fpu.o"; fi)
-SPLIB-$(CONFIG_HAS_POST) += $(shell if [ -d cpu/$(CPU) ]; then echo \
-			    "cpu/$(CPU)/libpost$(CPU).o"; fi)
-SPLIB-$(CONFIG_HAS_POST) += $(shell if [ -d board/$(BOARD) ]; then echo \
-			    "board/$(BOARD)/libpost$(BOARD).o"; fi)
-
-GPLIB	:= $(addprefix $(obj),$(GPLIB-y))
-SPLIB	:= $(addprefix $(obj),$(SPLIB-y))
-COBJS	:= $(COBJS-y)
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-LIB	:= $(obj)$(LIB)
-
-all:	$(LIB)
-
-postdeps:
-	@for lib in $(SPLIB-y) ; do \
-		$(MAKE) -C `dirname $$lib` all ; \
-	done
-
-# generic POST library
-$(GPLIB): $(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-# specific POST libraries
-$(SPLIB): $(obj).depend postdeps
-	$(MAKE) -C $(dir $(subst $(obj),,$@))
-
-# the POST lib archive
-$(LIB): $(GPLIB) $(SPLIB)
-	$(call cmd_link_o_target, $^)
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-y	+= post.o
+obj-$(CONFIG_POST_STD_LIST)	+= tests.o
+
+obj-y += drivers/
+obj-$(CONFIG_PPC) += lib_powerpc/
+obj-$(CONFIG_MPC83xx) += cpu/mpc83xx/
+obj-$(CONFIG_8xx) += cpu/mpc8xx/
+obj-$(CONFIG_4xx) += cpu/ppc4xx/
+ifneq ($(filter lwmon lwmon5 netta pdm360ng,$(BOARD)),)
+obj-y += board/$(BOARD)/
+endif
diff --git a/post/board/lwmon/Makefile b/post/board/lwmon/Makefile
index d38498bc47..7f6d5a084e 100644
--- a/post/board/lwmon/Makefile
+++ b/post/board/lwmon/Makefile
@@ -4,10 +4,5 @@
 #
 # SPDX-License-Identifier:	GPL-2.0+
 #
-include $(OBJTREE)/include/autoconf.mk
 
-LIB	= libpostlwmon.o
-
-COBJS-$(CONFIG_HAS_POST)	+= sysmon.o
-
-include $(TOPDIR)/post/rules.mk
+obj-y += sysmon.o
diff --git a/post/board/lwmon5/Makefile b/post/board/lwmon5/Makefile
index b410dbb399..76262c76bc 100644
--- a/post/board/lwmon5/Makefile
+++ b/post/board/lwmon5/Makefile
@@ -4,10 +4,5 @@
 # Developed for DENX Software Engineering GmbH
 #
 # SPDX-License-Identifier:	GPL-2.0+
-include $(OBJTREE)/include/autoconf.mk
 
-LIB	= libpostlwmon5.o
-
-COBJS-$(CONFIG_HAS_POST)	+= sysmon.o watchdog.o dspic.o fpga.o dsp.o gdc.o
-
-include $(TOPDIR)/post/rules.mk
+obj-y += sysmon.o watchdog.o dspic.o fpga.o dsp.o gdc.o
diff --git a/post/board/netta/Makefile b/post/board/netta/Makefile
index 2d73f55f25..8fc1945b07 100644
--- a/post/board/netta/Makefile
+++ b/post/board/netta/Makefile
@@ -4,10 +4,5 @@
 #
 # SPDX-License-Identifier:	GPL-2.0+
 #
-include $(OBJTREE)/include/autoconf.mk
 
-LIB	= libpostnetta.o
-
-COBJS-$(CONFIG_HAS_POST)	+= codec.o dsp.o
-
-include $(TOPDIR)/post/rules.mk
+obj-y += codec.o dsp.o
diff --git a/post/board/pdm360ng/Makefile b/post/board/pdm360ng/Makefile
index cb03e5896d..9aa96a1f6a 100644
--- a/post/board/pdm360ng/Makefile
+++ b/post/board/pdm360ng/Makefile
@@ -4,10 +4,5 @@
 #
 # SPDX-License-Identifier:	GPL-2.0+
 #
-include $(OBJTREE)/include/autoconf.mk
 
-LIB	= libpostpdm360ng.o
-
-COBJS-$(CONFIG_HAS_POST)	+= coproc_com.o
-
-include $(TOPDIR)/post/rules.mk
+obj-y += coproc_com.o
diff --git a/post/cpu/mpc83xx/Makefile b/post/cpu/mpc83xx/Makefile
index 6ac56dc2e8..d57b66757e 100644
--- a/post/cpu/mpc83xx/Makefile
+++ b/post/cpu/mpc83xx/Makefile
@@ -4,11 +4,5 @@
 #
 # SPDX-License-Identifier:	GPL-2.0+
 #
-include $(OBJTREE)/include/autoconf.mk
 
-LIB	= libpostmpc83xx.o
-
-AOBJS-$(CONFIG_HAS_POST)	+=
-COBJS-$(CONFIG_HAS_POST)	+= ecc.o
-
-include $(TOPDIR)/post/rules.mk
+obj-y += ecc.o
diff --git a/post/cpu/mpc8xx/Makefile b/post/cpu/mpc8xx/Makefile
index efde1fb3dc..f8bb6c9343 100644
--- a/post/cpu/mpc8xx/Makefile
+++ b/post/cpu/mpc8xx/Makefile
@@ -4,11 +4,6 @@
 #
 # SPDX-License-Identifier:	GPL-2.0+
 #
-include $(OBJTREE)/include/autoconf.mk
 
-LIB	= libpostmpc8xx.o
-
-AOBJS-$(CONFIG_HAS_POST)	+= cache_8xx.o
-COBJS-$(CONFIG_HAS_POST)	+= cache.o ether.o spr.o uart.o usb.o watchdog.o
-
-include $(TOPDIR)/post/rules.mk
+obj-$(CONFIG_HAS_POST)	+= cache_8xx.o
+obj-$(CONFIG_HAS_POST)	+= cache.o ether.o spr.o uart.o usb.o watchdog.o
diff --git a/post/cpu/ppc4xx/Makefile b/post/cpu/ppc4xx/Makefile
index 614cef03fc..e9ec286c7c 100644
--- a/post/cpu/ppc4xx/Makefile
+++ b/post/cpu/ppc4xx/Makefile
@@ -4,18 +4,13 @@
 #
 # SPDX-License-Identifier:	GPL-2.0+
 #
-include $(OBJTREE)/include/autoconf.mk
 
-LIB	= libpostppc4xx.o
-
-AOBJS-$(CONFIG_HAS_POST)	+= cache_4xx.o
-COBJS-$(CONFIG_HAS_POST)	+= cache.o
-COBJS-$(CONFIG_HAS_POST)	+= denali_ecc.o
-COBJS-$(CONFIG_HAS_POST)	+= ether.o
-COBJS-$(CONFIG_HAS_POST)	+= fpu.o
-COBJS-$(CONFIG_HAS_POST)	+= ocm.o
-COBJS-$(CONFIG_HAS_POST)	+= spr.o
-COBJS-$(CONFIG_HAS_POST)	+= uart.o
-COBJS-$(CONFIG_HAS_POST)	+= watchdog.o
-
-include $(TOPDIR)/post/rules.mk
+obj-y += cache_4xx.o
+obj-y += cache.o
+obj-y += denali_ecc.o
+obj-y += ether.o
+obj-y += fpu.o
+obj-y += ocm.o
+obj-y += spr.o
+obj-y += uart.o
+obj-y += watchdog.o
diff --git a/post/drivers/Makefile b/post/drivers/Makefile
index 6720f85139..1abfb1ffe6 100644
--- a/post/drivers/Makefile
+++ b/post/drivers/Makefile
@@ -4,10 +4,5 @@
 #
 # SPDX-License-Identifier:	GPL-2.0+
 #
-include $(TOPDIR)/config.mk
 
-LIB	= libpostdrivers.o
-
-COBJS-$(CONFIG_HAS_POST)	+= flash.o i2c.o memory.o rtc.o
-
-include $(TOPDIR)/post/rules.mk
+obj-y += flash.o i2c.o memory.o rtc.o
diff --git a/post/lib_powerpc/Makefile b/post/lib_powerpc/Makefile
index efa1fb2261..0cbb6b6bd2 100644
--- a/post/lib_powerpc/Makefile
+++ b/post/lib_powerpc/Makefile
@@ -4,13 +4,10 @@
 #
 # SPDX-License-Identifier:	GPL-2.0+
 #
-include $(TOPDIR)/config.mk
 
-LIB	= libpost$(ARCH).o
+obj-y += asm.o
+obj-y += cpu.o cmp.o cmpi.o two.o twox.o three.o threex.o
+obj-y += threei.o andi.o srawi.o rlwnm.o rlwinm.o rlwimi.o
+obj-y += store.o load.o cr.o b.o multi.o string.o complex.o
 
-AOBJS-$(CONFIG_HAS_POST)	+= asm.o
-COBJS-$(CONFIG_HAS_POST)	+= cpu.o cmp.o cmpi.o two.o twox.o three.o threex.o
-COBJS-$(CONFIG_HAS_POST)   += threei.o andi.o srawi.o rlwnm.o rlwinm.o rlwimi.o
-COBJS-$(CONFIG_HAS_POST)	+= store.o load.o cr.o b.o multi.o string.o complex.o
-
-include $(TOPDIR)/post/rules.mk
+obj-y += fpu/
diff --git a/post/lib_powerpc/fpu/Makefile b/post/lib_powerpc/fpu/Makefile
index eff7e6b402..5c2e804d90 100644
--- a/post/lib_powerpc/fpu/Makefile
+++ b/post/lib_powerpc/fpu/Makefile
@@ -4,27 +4,20 @@
 #
 # SPDX-License-Identifier:	GPL-2.0+
 #
-include $(TOPDIR)/config.mk
 
-LIB	= libpost$(ARCH)fpu.o
+objs-before-objcopy := 20001122-1.o 20010114-2.o 20010226-1.o 980619-1.o \
+	acc1.o compare-fp-1.o fpu.o mul-subnormal-single-1.o darwin-ldouble.o
+targets += $(objs-before-objcopy)
 
-COBJS-$(CONFIG_HAS_POST)	+= 20001122-1.o
-COBJS-$(CONFIG_HAS_POST)	+= 20010114-2.o
-COBJS-$(CONFIG_HAS_POST)	+= 20010226-1.o
-COBJS-$(CONFIG_HAS_POST)	+= 980619-1.o
-COBJS-$(CONFIG_HAS_POST)	+= acc1.o
-COBJS-$(CONFIG_HAS_POST)	+= compare-fp-1.o
-COBJS-$(CONFIG_HAS_POST)	+= fpu.o
-COBJS-$(CONFIG_HAS_POST)	+= mul-subnormal-single-1.o
+# remove -msoft-float flag
+$(foreach m, $(objs-before-objcopy), $(eval CFLAGS_REMOVE_$m := -msoft-float))
+ccflags-y := -mhard-float -fkeep-inline-functions
 
-COBJS-$(CONFIG_HAS_POST)	+= darwin-ldouble.o
+# Do not delete intermidiate files (*.o)
+.SECONDARY: $(call objectify, $(objs-before-objcopy))
 
-include $(TOPDIR)/post/rules.mk
+obj-y := $(objs-before-objcopy:.o=_.o)
 
-CFLAGS := $(shell echo $(CFLAGS) | sed s/-msoft-float//)
-CFLAGS += -mhard-float -fkeep-inline-functions
-
-$(obj)%.o:	%.c
-	$(CC)  $(ALL_CFLAGS) -o $@.fp $< -c
-	$(OBJCOPY) -R .gnu.attributes $@.fp $@
-	rm -f $@.fp
+OBJCOPYFLAGS := -R .gnu.attributes
+$(obj)/%_.o: $(obj)/%.o FORCE
+	$(call if_changed,objcopy)
diff --git a/post/rules.mk b/post/rules.mk
deleted file mode 100644
index b25ebbf1cb..0000000000
--- a/post/rules.mk
+++ /dev/null
@@ -1,30 +0,0 @@
-#
-# (C) Copyright 2002-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-include $(TOPDIR)/config.mk
-
-COBJS	:= $(COBJS-y)
-AOBJS	:= $(AOBJS-y)
-SRCS	:= $(AOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(AOBJS) $(COBJS))
-LIB	:= $(obj)$(LIB)
-
-CPPFLAGS += -I$(TOPDIR)
-
-all:	$(LIB)
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
diff --git a/rules.mk b/rules.mk
deleted file mode 100644
index f4510b7cb6..0000000000
--- a/rules.mk
+++ /dev/null
@@ -1,51 +0,0 @@
-#
-# (C) Copyright 2006-2013
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-#########################################################################
-
-_depend:	$(obj).depend
-
-# Split the source files into two camps: those in the current directory, and
-# those somewhere else. For the first camp we want to support CPPFLAGS_<fname>
-# and for the second we don't / can't.
-PWD_SRCS := $(filter $(notdir $(SRCS)),$(SRCS))
-OTHER_SRCS := $(filter-out $(notdir $(SRCS)),$(SRCS))
-
-# This is a list of dependency files to generate
-DEPS := $(basename $(patsubst %,$(obj).depend.%,$(PWD_SRCS)))
-
-# Join all the dependencies into a single file, in three parts
-#	1 .Concatenate all the generated depend files together
-#	2. Add in the deps from OTHER_SRCS which we couldn't process
-#	3. Add in the HOSTSRCS
-$(obj).depend:	$(src)Makefile $(TOPDIR)/config.mk $(DEPS) $(OTHER_SRCS) \
-		$(HOSTSRCS)
-	cat /dev/null $(DEPS) >$@
-	@for f in $(OTHER_SRCS); do \
-		g=`basename $$f | sed -e 's/\(.*\)\.[[:alnum:]_]/\1.o/'`; \
-		$(CC) -M $(CPPFLAGS) -MQ $(obj)$$g $$f >> $@ ; \
-	done
-	@for f in $(HOSTSRCS); do \
-		g=`basename $$f | sed -e 's/\(.*\)\.[[:alnum:]_]/\1.o/'`; \
-		$(HOSTCC) -M $(HOSTCPPFLAGS) -MQ $(obj)$$g $$f >> $@ ; \
-	done
-
-MAKE_DEPEND = $(CC) -M $(CPPFLAGS) $(EXTRA_CPPFLAGS_DEP) \
-		-MQ $(addsuffix .o,$(obj)$(basename $<)) $< >$@
-
-
-$(obj).depend.%:	%.c
-	$(MAKE_DEPEND)
-
-$(obj).depend.%:	%.S
-	$(MAKE_DEPEND)
-
-$(HOSTOBJS): $(obj)%.o: %.c
-	$(HOSTCC) $(HOSTCFLAGS) $(HOSTCFLAGS_$(@F)) $(HOSTCFLAGS_$(BCURDIR)) -o $@ $< -c
-$(NOPEDOBJS): $(obj)%.o: %.c
-	$(HOSTCC) $(HOSTCFLAGS_NOPED) $(HOSTCFLAGS_$(@F)) $(HOSTCFLAGS_$(BCURDIR)) -o $@ $< -c
-
-#########################################################################
diff --git a/scripts/.gitignore b/scripts/.gitignore
new file mode 100644
index 0000000000..82bc06ef98
--- /dev/null
+++ b/scripts/.gitignore
@@ -0,0 +1,4 @@
+#
+# Generated files
+#
+docproc
diff --git a/scripts/Kbuild.include b/scripts/Kbuild.include
new file mode 100644
index 0000000000..650457191a
--- /dev/null
+++ b/scripts/Kbuild.include
@@ -0,0 +1,284 @@
+####
+# kbuild: Generic definitions
+
+# Convenient variables
+comma   := ,
+squote  := '
+empty   :=
+space   := $(empty) $(empty)
+
+###
+# Name of target with a '.' as filename prefix. foo/bar.o => foo/.bar.o
+dot-target = $(dir $@).$(notdir $@)
+
+###
+# The temporary file to save gcc -MD generated dependencies must not
+# contain a comma
+depfile = $(subst $(comma),_,$(dot-target).d)
+
+###
+# filename of target with directory and extension stripped
+basetarget = $(basename $(notdir $@))
+
+###
+# filename of first prerequisite with directory and extension stripped
+baseprereq = $(basename $(notdir $<))
+
+###
+# Escape single quote for use in echo statements
+escsq = $(subst $(squote),'\$(squote)',$1)
+
+###
+# Easy method for doing a status message
+       kecho := :
+ quiet_kecho := echo
+silent_kecho := :
+kecho := $($(quiet)kecho)
+
+###
+# filechk is used to check if the content of a generated file is updated.
+# Sample usage:
+# define filechk_sample
+#	echo $KERNELRELEASE
+# endef
+# version.h : Makefile
+#	$(call filechk,sample)
+# The rule defined shall write to stdout the content of the new file.
+# The existing file will be compared with the new one.
+# - If no file exist it is created
+# - If the content differ the new file is used
+# - If they are equal no change, and no timestamp update
+# - stdin is piped in from the first prerequisite ($<) so one has
+#   to specify a valid file as first prerequisite (often the kbuild file)
+define filechk
+	$(Q)set -e;				\
+	$(kecho) '  CHK     $@';		\
+	mkdir -p $(dir $@);			\
+	$(filechk_$(1)) < $< > $@.tmp;		\
+	if [ -r $@ ] && cmp -s $@ $@.tmp; then	\
+		rm -f $@.tmp;			\
+	else					\
+		$(kecho) '  UPD     $@';	\
+		mv -f $@.tmp $@;		\
+	fi
+endef
+
+######
+# gcc support functions
+# See documentation in Documentation/kbuild/makefiles.txt
+
+# cc-cross-prefix
+# Usage: CROSS_COMPILE := $(call cc-cross-prefix, m68k-linux-gnu- m68k-linux-)
+# Return first prefix where a prefix$(CC) is found in PATH.
+# If no $(CC) found in PATH with listed prefixes return nothing
+cc-cross-prefix =  \
+	$(word 1, $(foreach c,$(1),                                   \
+		$(shell set -e;                                       \
+		if (which $(strip $(c))$(CC)) > /dev/null 2>&1 ; then \
+			echo $(c);                                    \
+		fi)))
+
+# output directory for tests below
+TMPOUT := $(if $(KBUILD_EXTMOD),$(firstword $(KBUILD_EXTMOD))/)
+
+# try-run
+# Usage: option = $(call try-run, $(CC)...-o "$$TMP",option-ok,otherwise)
+# Exit code chooses option. "$$TMP" is can be used as temporary file and
+# is automatically cleaned up.
+# modifed for U-Boot: prevent cc-option from leaving .*.su files
+try-run = $(shell set -e;		\
+	TMP="$(TMPOUT).$$$$.tmp";	\
+	TMPO="$(TMPOUT).$$$$.o";	\
+	TMPSU="$(TMPOUT).$$$$.su";	\
+	if ($(1)) >/dev/null 2>&1;	\
+	then echo "$(2)";		\
+	else echo "$(3)";		\
+	fi;				\
+	rm -f "$$TMP" "$$TMPO" "$$TMPSU")
+
+# as-option
+# Usage: cflags-y += $(call as-option,-Wa$(comma)-isa=foo,)
+
+as-option = $(call try-run,\
+	$(CC) $(KBUILD_CFLAGS) $(1) -c -x assembler /dev/null -o "$$TMP",$(1),$(2))
+
+# as-instr
+# Usage: cflags-y += $(call as-instr,instr,option1,option2)
+
+as-instr = $(call try-run,\
+	printf "%b\n" "$(1)" | $(CC) $(KBUILD_AFLAGS) -c -x assembler -o "$$TMP" -,$(2),$(3))
+
+# cc-option
+# Usage: cflags-y += $(call cc-option,-march=winchip-c6,-march=i586)
+
+cc-option = $(call try-run,\
+	$(CC) $(KBUILD_CPPFLAGS) $(KBUILD_CFLAGS) $(1) -c -x c /dev/null -o "$$TMP",$(1),$(2))
+
+# cc-option-yn
+# Usage: flag := $(call cc-option-yn,-march=winchip-c6)
+cc-option-yn = $(call try-run,\
+	$(CC) $(KBUILD_CPPFLAGS) $(KBUILD_CFLAGS) $(1) -c -x c /dev/null -o "$$TMP",y,n)
+
+# cc-option-align
+# Prefix align with either -falign or -malign
+cc-option-align = $(subst -functions=0,,\
+	$(call cc-option,-falign-functions=0,-malign-functions=0))
+
+# cc-disable-warning
+# Usage: cflags-y += $(call cc-disable-warning,unused-but-set-variable)
+cc-disable-warning = $(call try-run,\
+	$(CC) $(KBUILD_CPPFLAGS) $(KBUILD_CFLAGS) -W$(strip $(1)) -c -x c /dev/null -o "$$TMP",-Wno-$(strip $(1)))
+
+# cc-version
+# Usage gcc-ver := $(call cc-version)
+cc-version = $(shell $(CONFIG_SHELL) $(srctree)/scripts/gcc-version.sh $(CC))
+
+# cc-fullversion
+# Usage gcc-ver := $(call cc-fullversion)
+cc-fullversion = $(shell $(CONFIG_SHELL) \
+	$(srctree)/scripts/gcc-version.sh -p $(CC))
+
+# cc-ifversion
+# Usage:  EXTRA_CFLAGS += $(call cc-ifversion, -lt, 0402, -O1)
+cc-ifversion = $(shell [ $(call cc-version, $(CC)) $(1) $(2) ] && echo $(3))
+
+# added for U-Boot
+binutils-version = $(shell $(CONFIG_SHELL) $(srctree)/scripts/binutils-version.sh $(AS))
+dtc-version = $(shell $(CONFIG_SHELL) $(srctree)/scripts/dtc-version.sh $(DTC))
+
+# cc-ldoption
+# Usage: ldflags += $(call cc-ldoption, -Wl$(comma)--hash-style=both)
+cc-ldoption = $(call try-run,\
+	$(CC) $(1) -nostdlib -x c /dev/null -o "$$TMP",$(1),$(2))
+
+# ld-option
+# Usage: LDFLAGS += $(call ld-option, -X)
+ld-option = $(call try-run,\
+	$(CC) -x c /dev/null -c -o "$$TMPO" ; $(LD) $(1) "$$TMPO" -o "$$TMP",$(1),$(2))
+
+# ar-option
+# Usage: KBUILD_ARFLAGS := $(call ar-option,D)
+# Important: no spaces around options
+ar-option = $(call try-run, $(AR) rc$(1) "$$TMP",$(1),$(2))
+
+######
+
+###
+# Shorthand for $(Q)$(MAKE) -f scripts/Makefile.build obj=
+# Usage:
+# $(Q)$(MAKE) $(build)=dir
+build := -f $(if $(KBUILD_SRC),$(srctree)/)scripts/Makefile.build obj
+
+###
+# Shorthand for $(Q)$(MAKE) -f scripts/Makefile.modbuiltin obj=
+# Usage:
+# $(Q)$(MAKE) $(modbuiltin)=dir
+modbuiltin := -f $(if $(KBUILD_SRC),$(srctree)/)scripts/Makefile.modbuiltin obj
+
+# Prefix -I with $(srctree) if it is not an absolute path.
+# skip if -I has no parameter
+addtree = $(if $(patsubst -I%,%,$(1)), \
+$(if $(filter-out -I/%,$(1)),$(patsubst -I%,-I$(srctree)/%,$(1))) $(1))
+
+# Find all -I options and call addtree
+flags = $(foreach o,$($(1)),$(if $(filter -I%,$(o)),$(call addtree,$(o)),$(o)))
+
+# echo command.
+# Short version is used, if $(quiet) equals `quiet_', otherwise full one.
+echo-cmd = $(if $($(quiet)cmd_$(1)),\
+	echo '  $(call escsq,$($(quiet)cmd_$(1)))$(echo-why)';)
+
+# printing commands
+cmd = @$(echo-cmd) $(cmd_$(1))
+
+# Add $(obj)/ for paths that are not absolute
+objectify = $(foreach o,$(1),$(if $(filter /%,$(o)),$(o),$(obj)/$(o)))
+
+###
+# if_changed      - execute command if any prerequisite is newer than
+#                   target, or command line has changed
+# if_changed_dep  - as if_changed, but uses fixdep to reveal dependencies
+#                   including used config symbols
+# if_changed_rule - as if_changed but execute rule instead
+# See Documentation/kbuild/makefiles.txt for more info
+
+ifneq ($(KBUILD_NOCMDDEP),1)
+# Check if both arguments has same arguments. Result is empty string if equal.
+# User may override this check using make KBUILD_NOCMDDEP=1
+arg-check = $(strip $(filter-out $(cmd_$(1)), $(cmd_$@)) \
+                    $(filter-out $(cmd_$@),   $(cmd_$(1))) )
+else
+arg-check = $(if $(strip $(cmd_$@)),,1)
+endif
+
+# >'< substitution is for echo to work,
+# >$< substitution to preserve $ when reloading .cmd file
+# note: when using inline perl scripts [perl -e '...$$t=1;...']
+# in $(cmd_xxx) double $$ your perl vars
+make-cmd = $(subst \\,\\\\,$(subst \#,\\\#,$(subst $$,$$$$,$(call escsq,$(cmd_$(1))))))
+
+# Find any prerequisites that is newer than target or that does not exist.
+# PHONY targets skipped in both cases.
+any-prereq = $(filter-out $(PHONY),$?) $(filter-out $(PHONY) $(wildcard $^),$^)
+
+# Execute command if command has changed or prerequisite(s) are updated.
+#
+if_changed = $(if $(strip $(any-prereq) $(arg-check)),                       \
+	@set -e;                                                             \
+	$(echo-cmd) $(cmd_$(1));                                             \
+	echo 'cmd_$@ := $(make-cmd)' > $(dot-target).cmd)
+
+# Execute the command and also postprocess generated .d dependencies file.
+if_changed_dep = $(if $(strip $(any-prereq) $(arg-check) ),                  \
+	@set -e;                                                             \
+	$(echo-cmd) $(cmd_$(1));                                             \
+	scripts/basic/fixdep $(depfile) $@ '$(make-cmd)' > $(dot-target).tmp;\
+	rm -f $(depfile);                                                    \
+	mv -f $(dot-target).tmp $(dot-target).cmd)
+
+# Usage: $(call if_changed_rule,foo)
+# Will check if $(cmd_foo) or any of the prerequisites changed,
+# and if so will execute $(rule_foo).
+if_changed_rule = $(if $(strip $(any-prereq) $(arg-check) ),                 \
+	@set -e;                                                             \
+	$(rule_$(1)))
+
+###
+# why - tell why a a target got build
+#       enabled by make V=2
+#       Output (listed in the order they are checked):
+#          (1) - due to target is PHONY
+#          (2) - due to target missing
+#          (3) - due to: file1.h file2.h
+#          (4) - due to command line change
+#          (5) - due to missing .cmd file
+#          (6) - due to target not in $(targets)
+# (1) PHONY targets are always build
+# (2) No target, so we better build it
+# (3) Prerequisite is newer than target
+# (4) The command line stored in the file named dir/.target.cmd
+#     differed from actual command line. This happens when compiler
+#     options changes
+# (5) No dir/.target.cmd file (used to store command line)
+# (6) No dir/.target.cmd file and target not listed in $(targets)
+#     This is a good hint that there is a bug in the kbuild file
+ifeq ($(KBUILD_VERBOSE),2)
+why =                                                                        \
+    $(if $(filter $@, $(PHONY)),- due to target is PHONY,                    \
+        $(if $(wildcard $@),                                                 \
+            $(if $(strip $(any-prereq)),- due to: $(any-prereq),             \
+                $(if $(arg-check),                                           \
+                    $(if $(cmd_$@),- due to command line change,             \
+                        $(if $(filter $@, $(targets)),                       \
+                            - due to missing .cmd file,                      \
+                            - due to $(notdir $@) not in $$(targets)         \
+                         )                                                   \
+                     )                                                       \
+                 )                                                           \
+             ),                                                              \
+             - due to target missing                                         \
+         )                                                                   \
+     )
+
+echo-why = $(call escsq, $(strip $(why)))
+endif
diff --git a/scripts/Makefile b/scripts/Makefile
new file mode 100644
index 0000000000..242e3a06fc
--- /dev/null
+++ b/scripts/Makefile
@@ -0,0 +1,16 @@
+###
+# scripts contains sources for various helper programs used throughout
+# the kernel for the build process.
+# ---------------------------------------------------------------------------
+# docproc:       Used in Documentation/DocBook
+
+# The following hostprogs-y programs are only build on demand
+hostprogs-y += docproc
+
+# These targets are used internally to avoid "is up to date" messages
+PHONY += build_docproc
+build_docproc: scripts/docproc
+	@:
+
+# Let clean descend into subdirs
+subdir-	+= basic
diff --git a/scripts/Makefile.build b/scripts/Makefile.build
new file mode 100644
index 0000000000..36346fd161
--- /dev/null
+++ b/scripts/Makefile.build
@@ -0,0 +1,506 @@
+# ==========================================================================
+# Building
+# ==========================================================================
+
+# Modified for U-Boot
+ifeq ($(CONFIG_TPL_BUILD),y)
+  src := $(patsubst tpl/%,%,$(obj))
+else
+  ifeq ($(CONFIG_SPL_BUILD),y)
+    src := $(patsubst spl/%,%,$(obj))
+  else
+    src := $(obj)
+  endif
+endif
+
+PHONY := __build
+__build:
+
+# Init all relevant variables used in kbuild files so
+# 1) they have correct type
+# 2) they do not inherit any value from the environment
+obj-y :=
+obj-m :=
+lib-y :=
+lib-m :=
+always :=
+targets :=
+subdir-y :=
+subdir-m :=
+EXTRA_AFLAGS   :=
+EXTRA_CFLAGS   :=
+EXTRA_CPPFLAGS :=
+EXTRA_LDFLAGS  :=
+asflags-y  :=
+ccflags-y  :=
+cppflags-y :=
+ldflags-y  :=
+
+subdir-asflags-y :=
+subdir-ccflags-y :=
+
+# Read auto.conf if it exists, otherwise ignore
+-include include/config/auto.conf
+
+# Added for U-Boot: Load U-Boot configuration
+ifeq ($(CONFIG_TPL_BUILD),y)
+  -include include/tpl-autoconf.mk
+else
+  ifeq ($(CONFIG_SPL_BUILD),y)
+    -include include/spl-autoconf.mk
+  else
+    -include include/autoconf.mk
+  endif
+endif
+
+include scripts/Kbuild.include
+
+# For backward compatibility check that these variables do not change
+save-cflags := $(CFLAGS)
+
+# The filename Kbuild has precedence over Makefile
+kbuild-dir := $(if $(filter /%,$(src)),$(src),$(srctree)/$(src))
+kbuild-file := $(if $(wildcard $(kbuild-dir)/Kbuild),$(kbuild-dir)/Kbuild,$(kbuild-dir)/Makefile)
+include $(kbuild-file)
+
+# Added for U-Boot
+asflags-y  += $(PLATFORM_CPPFLAGS)
+ccflags-y  += $(PLATFORM_CPPFLAGS)
+cppflags-y += $(PLATFORM_CPPFLAGS)
+
+# If the save-* variables changed error out
+ifeq ($(KBUILD_NOPEDANTIC),)
+        ifneq ("$(save-cflags)","$(CFLAGS)")
+                $(error CFLAGS was changed in "$(kbuild-file)". Fix it to use ccflags-y)
+        endif
+endif
+
+#
+# make W=... settings
+#
+# W=1 - warnings that may be relevant and does not occur too often
+# W=2 - warnings that occur quite often but may still be relevant
+# W=3 - the more obscure warnings, can most likely be ignored
+#
+# $(call cc-option, -W...) handles gcc -W.. options which
+# are not supported by all versions of the compiler
+ifdef KBUILD_ENABLE_EXTRA_GCC_CHECKS
+warning-  := $(empty)
+
+warning-1 := -Wextra -Wunused -Wno-unused-parameter
+warning-1 += -Wmissing-declarations
+warning-1 += -Wmissing-format-attribute
+warning-1 += -Wmissing-prototypes
+warning-1 += -Wold-style-definition
+warning-1 += $(call cc-option, -Wmissing-include-dirs)
+warning-1 += $(call cc-option, -Wunused-but-set-variable)
+warning-1 += $(call cc-disable-warning, missing-field-initializers)
+
+warning-2 := -Waggregate-return
+warning-2 += -Wcast-align
+warning-2 += -Wdisabled-optimization
+warning-2 += -Wnested-externs
+warning-2 += -Wshadow
+warning-2 += $(call cc-option, -Wlogical-op)
+warning-2 += $(call cc-option, -Wmissing-field-initializers)
+
+warning-3 := -Wbad-function-cast
+warning-3 += -Wcast-qual
+warning-3 += -Wconversion
+warning-3 += -Wpacked
+warning-3 += -Wpadded
+warning-3 += -Wpointer-arith
+warning-3 += -Wredundant-decls
+warning-3 += -Wswitch-default
+warning-3 += $(call cc-option, -Wpacked-bitfield-compat)
+warning-3 += $(call cc-option, -Wvla)
+
+warning := $(warning-$(findstring 1, $(KBUILD_ENABLE_EXTRA_GCC_CHECKS)))
+warning += $(warning-$(findstring 2, $(KBUILD_ENABLE_EXTRA_GCC_CHECKS)))
+warning += $(warning-$(findstring 3, $(KBUILD_ENABLE_EXTRA_GCC_CHECKS)))
+
+ifeq ("$(strip $(warning))","")
+        $(error W=$(KBUILD_ENABLE_EXTRA_GCC_CHECKS) is unknown)
+endif
+
+KBUILD_CFLAGS += $(warning)
+endif
+
+include scripts/Makefile.lib
+
+ifdef host-progs
+ifneq ($(hostprogs-y),$(host-progs))
+$(warning kbuild: $(obj)/Makefile - Usage of host-progs is deprecated. Please replace with hostprogs-y!)
+hostprogs-y += $(host-progs)
+endif
+endif
+
+# Do not include host rules unless needed
+ifneq ($(hostprogs-y)$(hostprogs-m),)
+include scripts/Makefile.host
+endif
+
+# Uncommented for U-Boot
+#  We need to create output dicrectory for SPL and TPL even for in-tree build
+#ifneq ($(KBUILD_SRC),)
+# Create output directory if not already present
+_dummy := $(shell [ -d $(obj) ] || mkdir -p $(obj))
+
+# Create directories for object files if directory does not exist
+# Needed when obj-y := dir/file.o syntax is used
+_dummy := $(foreach d,$(obj-dirs), $(shell [ -d $(d) ] || mkdir -p $(d)))
+#endif
+
+ifndef obj
+$(warning kbuild: Makefile.build is included improperly)
+endif
+
+# ===========================================================================
+
+ifneq ($(strip $(lib-y) $(lib-m) $(lib-n) $(lib-)),)
+lib-target := $(obj)/lib.a
+endif
+
+ifneq ($(strip $(obj-y) $(obj-m) $(obj-n) $(obj-) $(subdir-m) $(lib-target)),)
+builtin-target := $(obj)/built-in.o
+endif
+
+modorder-target := $(obj)/modules.order
+
+# We keep a list of all modules in $(MODVERDIR)
+
+__build: $(if $(KBUILD_BUILTIN),$(builtin-target) $(lib-target) $(extra-y)) \
+	 $(if $(KBUILD_MODULES),$(obj-m) $(modorder-target)) \
+	 $(subdir-ym) $(always)
+	@:
+
+# Linus' kernel sanity checking tool
+ifneq ($(KBUILD_CHECKSRC),0)
+  ifeq ($(KBUILD_CHECKSRC),2)
+    quiet_cmd_force_checksrc = CHECK   $<
+          cmd_force_checksrc = $(CHECK) $(CHECKFLAGS) $(c_flags) $< ;
+  else
+      quiet_cmd_checksrc     = CHECK   $<
+            cmd_checksrc     = $(CHECK) $(CHECKFLAGS) $(c_flags) $< ;
+  endif
+endif
+
+# Do section mismatch analysis for each module/built-in.o
+ifdef CONFIG_DEBUG_SECTION_MISMATCH
+  cmd_secanalysis = ; scripts/mod/modpost $@
+endif
+
+# Compile C sources (.c)
+# ---------------------------------------------------------------------------
+
+# Default is built-in, unless we know otherwise
+modkern_cflags =                                          \
+	$(if $(part-of-module),                           \
+		$(KBUILD_CFLAGS_MODULE) $(CFLAGS_MODULE), \
+		$(KBUILD_CFLAGS_KERNEL) $(CFLAGS_KERNEL))
+quiet_modtag := $(empty)   $(empty)
+
+$(real-objs-m)        : part-of-module := y
+$(real-objs-m:.o=.i)  : part-of-module := y
+$(real-objs-m:.o=.s)  : part-of-module := y
+$(real-objs-m:.o=.lst): part-of-module := y
+
+$(real-objs-m)        : quiet_modtag := [M]
+$(real-objs-m:.o=.i)  : quiet_modtag := [M]
+$(real-objs-m:.o=.s)  : quiet_modtag := [M]
+$(real-objs-m:.o=.lst): quiet_modtag := [M]
+
+$(obj-m)              : quiet_modtag := [M]
+
+# Default for not multi-part modules
+modname = $(basetarget)
+
+$(multi-objs-m)         : modname = $(modname-multi)
+$(multi-objs-m:.o=.i)   : modname = $(modname-multi)
+$(multi-objs-m:.o=.s)   : modname = $(modname-multi)
+$(multi-objs-m:.o=.lst) : modname = $(modname-multi)
+$(multi-objs-y)         : modname = $(modname-multi)
+$(multi-objs-y:.o=.i)   : modname = $(modname-multi)
+$(multi-objs-y:.o=.s)   : modname = $(modname-multi)
+$(multi-objs-y:.o=.lst) : modname = $(modname-multi)
+
+quiet_cmd_cc_s_c = CC $(quiet_modtag)  $@
+cmd_cc_s_c       = $(CC) $(c_flags) -fverbose-asm -S -o $@ $<
+
+$(obj)/%.s: $(src)/%.c FORCE
+	$(call if_changed_dep,cc_s_c)
+
+quiet_cmd_cc_i_c = CPP $(quiet_modtag) $@
+cmd_cc_i_c       = $(CPP) $(c_flags)   -o $@ $<
+
+$(obj)/%.i: $(src)/%.c FORCE
+	$(call if_changed_dep,cc_i_c)
+
+cmd_gensymtypes =                                                           \
+    $(CPP) -D__GENKSYMS__ $(c_flags) $< |                                   \
+    $(GENKSYMS) $(if $(1), -T $(2))                                         \
+     $(patsubst y,-s _,$(CONFIG_HAVE_UNDERSCORE_SYMBOL_PREFIX))             \
+     $(if $(KBUILD_PRESERVE),-p)                                            \
+     -r $(firstword $(wildcard $(2:.symtypes=.symref) /dev/null))
+
+quiet_cmd_cc_symtypes_c = SYM $(quiet_modtag) $@
+cmd_cc_symtypes_c =                                                         \
+    set -e;                                                                 \
+    $(call cmd_gensymtypes,true,$@) >/dev/null;                             \
+    test -s $@ || rm -f $@
+
+$(obj)/%.symtypes : $(src)/%.c FORCE
+	$(call cmd,cc_symtypes_c)
+
+# C (.c) files
+# The C file is compiled and updated dependency information is generated.
+# (See cmd_cc_o_c + relevant part of rule_cc_o_c)
+
+quiet_cmd_cc_o_c = CC $(quiet_modtag)  $@
+
+ifndef CONFIG_MODVERSIONS
+cmd_cc_o_c = $(CC) $(c_flags) -c -o $@ $<
+
+else
+# When module versioning is enabled the following steps are executed:
+# o compile a .tmp_<file>.o from <file>.c
+# o if .tmp_<file>.o doesn't contain a __ksymtab version, i.e. does
+#   not export symbols, we just rename .tmp_<file>.o to <file>.o and
+#   are done.
+# o otherwise, we calculate symbol versions using the good old
+#   genksyms on the preprocessed source and postprocess them in a way
+#   that they are usable as a linker script
+# o generate <file>.o from .tmp_<file>.o using the linker to
+#   replace the unresolved symbols __crc_exported_symbol with
+#   the actual value of the checksum generated by genksyms
+
+cmd_cc_o_c = $(CC) $(c_flags) -c -o $(@D)/.tmp_$(@F) $<
+cmd_modversions =								\
+	if $(OBJDUMP) -h $(@D)/.tmp_$(@F) | grep -q __ksymtab; then		\
+		$(call cmd_gensymtypes,$(KBUILD_SYMTYPES),$(@:.o=.symtypes))	\
+		    > $(@D)/.tmp_$(@F:.o=.ver);					\
+										\
+		$(LD) $(LDFLAGS) -r -o $@ $(@D)/.tmp_$(@F) 			\
+			-T $(@D)/.tmp_$(@F:.o=.ver);				\
+		rm -f $(@D)/.tmp_$(@F) $(@D)/.tmp_$(@F:.o=.ver);		\
+	else									\
+		mv -f $(@D)/.tmp_$(@F) $@;					\
+	fi;
+endif
+
+ifdef CONFIG_FTRACE_MCOUNT_RECORD
+ifdef BUILD_C_RECORDMCOUNT
+ifeq ("$(origin RECORDMCOUNT_WARN)", "command line")
+  RECORDMCOUNT_FLAGS = -w
+endif
+# Due to recursion, we must skip empty.o.
+# The empty.o file is created in the make process in order to determine
+#  the target endianness and word size. It is made before all other C
+#  files, including recordmcount.
+sub_cmd_record_mcount =					\
+	if [ $(@) != "scripts/mod/empty.o" ]; then	\
+		$(objtree)/scripts/recordmcount $(RECORDMCOUNT_FLAGS) "$(@)";	\
+	fi;
+recordmcount_source := $(srctree)/scripts/recordmcount.c \
+		    $(srctree)/scripts/recordmcount.h
+else
+sub_cmd_record_mcount = set -e ; perl $(srctree)/scripts/recordmcount.pl "$(ARCH)" \
+	"$(if $(CONFIG_CPU_BIG_ENDIAN),big,little)" \
+	"$(if $(CONFIG_64BIT),64,32)" \
+	"$(OBJDUMP)" "$(OBJCOPY)" "$(CC) $(KBUILD_CFLAGS)" \
+	"$(LD)" "$(NM)" "$(RM)" "$(MV)" \
+	"$(if $(part-of-module),1,0)" "$(@)";
+recordmcount_source := $(srctree)/scripts/recordmcount.pl
+endif
+cmd_record_mcount = 						\
+	if [ "$(findstring -pg,$(_c_flags))" = "-pg" ]; then	\
+		$(sub_cmd_record_mcount)			\
+	fi;
+endif
+
+define rule_cc_o_c
+	$(call echo-cmd,checksrc) $(cmd_checksrc)			  \
+	$(call echo-cmd,cc_o_c) $(cmd_cc_o_c);				  \
+	$(cmd_modversions)						  \
+	$(call echo-cmd,record_mcount)					  \
+	$(cmd_record_mcount)						  \
+	scripts/basic/fixdep $(depfile) $@ '$(call make-cmd,cc_o_c)' >    \
+	                                              $(dot-target).tmp;  \
+	rm -f $(depfile);						  \
+	mv -f $(dot-target).tmp $(dot-target).cmd
+endef
+
+# Built-in and composite module parts
+$(obj)/%.o: $(src)/%.c $(recordmcount_source) FORCE
+	$(call cmd,force_checksrc)
+	$(call if_changed_rule,cc_o_c)
+
+# Single-part modules are special since we need to mark them in $(MODVERDIR)
+
+$(single-used-m): $(obj)/%.o: $(src)/%.c $(recordmcount_source) FORCE
+	$(call cmd,force_checksrc)
+	$(call if_changed_rule,cc_o_c)
+	@{ echo $(@:.o=.ko); echo $@; } > $(MODVERDIR)/$(@F:.o=.mod)
+
+quiet_cmd_cc_lst_c = MKLST   $@
+      cmd_cc_lst_c = $(CC) $(c_flags) -g -c -o $*.o $< && \
+		     $(CONFIG_SHELL) $(srctree)/scripts/makelst $*.o \
+				     System.map $(OBJDUMP) > $@
+
+$(obj)/%.lst: $(src)/%.c FORCE
+	$(call if_changed_dep,cc_lst_c)
+
+# Compile assembler sources (.S)
+# ---------------------------------------------------------------------------
+
+modkern_aflags := $(KBUILD_AFLAGS_KERNEL) $(AFLAGS_KERNEL)
+
+$(real-objs-m)      : modkern_aflags := $(KBUILD_AFLAGS_MODULE) $(AFLAGS_MODULE)
+$(real-objs-m:.o=.s): modkern_aflags := $(KBUILD_AFLAGS_MODULE) $(AFLAGS_MODULE)
+
+quiet_cmd_as_s_S = CPP $(quiet_modtag) $@
+cmd_as_s_S       = $(CPP) $(a_flags)   -o $@ $< 
+
+$(obj)/%.s: $(src)/%.S FORCE
+	$(call if_changed_dep,as_s_S)
+
+quiet_cmd_as_o_S = AS $(quiet_modtag)  $@
+cmd_as_o_S       = $(CC) $(a_flags) -c -o $@ $<
+
+$(obj)/%.o: $(src)/%.S FORCE
+	$(call if_changed_dep,as_o_S)
+
+targets += $(real-objs-y) $(real-objs-m) $(lib-y)
+targets += $(extra-y) $(MAKECMDGOALS) $(always)
+
+# Linker scripts preprocessor (.lds.S -> .lds)
+# ---------------------------------------------------------------------------
+quiet_cmd_cpp_lds_S = LDS     $@
+      cmd_cpp_lds_S = $(CPP) $(cpp_flags) -P -C -U$(ARCH) \
+	                     -D__ASSEMBLY__ -DLINKER_SCRIPT -o $@ $<
+
+$(obj)/%.lds: $(src)/%.lds.S FORCE
+	$(call if_changed_dep,cpp_lds_S)
+
+# ASN.1 grammar
+# ---------------------------------------------------------------------------
+quiet_cmd_asn1_compiler = ASN.1   $@
+      cmd_asn1_compiler = $(objtree)/scripts/asn1_compiler $< \
+				$(subst .h,.c,$@) $(subst .c,.h,$@)
+
+.PRECIOUS: $(objtree)/$(obj)/%-asn1.c $(objtree)/$(obj)/%-asn1.h
+
+$(obj)/%-asn1.c $(obj)/%-asn1.h: $(src)/%.asn1 $(objtree)/scripts/asn1_compiler
+	$(call cmd,asn1_compiler)
+
+# Build the compiled-in targets
+# ---------------------------------------------------------------------------
+
+# To build objects in subdirs, we need to descend into the directories
+$(sort $(subdir-obj-y)): $(subdir-ym) ;
+
+#
+# Rule to compile a set of .o files into one .o file
+#
+ifdef builtin-target
+quiet_cmd_link_o_target = LD      $@
+# If the list of objects to link is empty, just create an empty built-in.o
+cmd_link_o_target = $(if $(strip $(obj-y)),\
+		      $(LD) $(ld_flags) -r -o $@ $(filter $(obj-y), $^) \
+		      $(cmd_secanalysis),\
+		      rm -f $@; $(AR) rcs$(KBUILD_ARFLAGS) $@)
+
+$(builtin-target): $(obj-y) FORCE
+	$(call if_changed,link_o_target)
+
+targets += $(builtin-target)
+endif # builtin-target
+
+#
+# Rule to create modules.order file
+#
+# Create commands to either record .ko file or cat modules.order from
+# a subdirectory
+modorder-cmds =						\
+	$(foreach m, $(modorder),			\
+		$(if $(filter %/modules.order, $m),	\
+			cat $m;, echo kernel/$m;))
+
+$(modorder-target): $(subdir-ym) FORCE
+	$(Q)(cat /dev/null; $(modorder-cmds)) > $@
+
+#
+# Rule to compile a set of .o files into one .a file
+#
+ifdef lib-target
+quiet_cmd_link_l_target = AR      $@
+cmd_link_l_target = rm -f $@; $(AR) rcs$(KBUILD_ARFLAGS) $@ $(lib-y)
+
+$(lib-target): $(lib-y) FORCE
+	$(call if_changed,link_l_target)
+
+targets += $(lib-target)
+endif
+
+#
+# Rule to link composite objects
+#
+#  Composite objects are specified in kbuild makefile as follows:
+#    <composite-object>-objs := <list of .o files>
+#  or
+#    <composite-object>-y    := <list of .o files>
+link_multi_deps =                     \
+$(filter $(addprefix $(obj)/,         \
+$($(subst $(obj)/,,$(@:.o=-objs)))    \
+$($(subst $(obj)/,,$(@:.o=-y)))), $^)
+ 
+quiet_cmd_link_multi-y = LD      $@
+cmd_link_multi-y = $(LD) $(ld_flags) -r -o $@ $(link_multi_deps) $(cmd_secanalysis)
+
+quiet_cmd_link_multi-m = LD [M]  $@
+cmd_link_multi-m = $(cmd_link_multi-y)
+
+# We would rather have a list of rules like
+# 	foo.o: $(foo-objs)
+# but that's not so easy, so we rather make all composite objects depend
+# on the set of all their parts
+$(multi-used-y) : %.o: $(multi-objs-y) FORCE
+	$(call if_changed,link_multi-y)
+
+$(multi-used-m) : %.o: $(multi-objs-m) FORCE
+	$(call if_changed,link_multi-m)
+	@{ echo $(@:.o=.ko); echo $(link_multi_deps); } > $(MODVERDIR)/$(@F:.o=.mod)
+
+targets += $(multi-used-y) $(multi-used-m)
+
+
+# Descending
+# ---------------------------------------------------------------------------
+
+PHONY += $(subdir-ym)
+$(subdir-ym):
+	$(Q)$(MAKE) $(build)=$@
+
+# Add FORCE to the prequisites of a target to force it to be always rebuilt.
+# ---------------------------------------------------------------------------
+
+PHONY += FORCE
+
+FORCE:
+
+# Read all saved command lines and dependencies for the $(targets) we
+# may be building above, using $(if_changed{,_dep}). As an
+# optimization, we don't need to read them if the target does not
+# exist, we will rebuild anyway in that case.
+
+targets := $(wildcard $(sort $(targets)))
+cmd_files := $(wildcard $(foreach f,$(targets),$(dir $(f)).$(notdir $(f)).cmd))
+
+ifneq ($(cmd_files),)
+  include $(cmd_files)
+endif
+
+# Declare the contents of the .PHONY variable as phony.  We keep that
+# information in a variable se we can use it in if_changed and friends.
+
+.PHONY: $(PHONY)
diff --git a/scripts/Makefile.clean b/scripts/Makefile.clean
new file mode 100644
index 0000000000..d6dcd47f6f
--- /dev/null
+++ b/scripts/Makefile.clean
@@ -0,0 +1,109 @@
+# ==========================================================================
+# Cleaning up
+# ==========================================================================
+
+src := $(obj)
+
+PHONY := __clean
+__clean:
+
+# Shorthand for $(Q)$(MAKE) scripts/Makefile.clean obj=dir
+# Usage:
+# $(Q)$(MAKE) $(clean)=dir
+clean := -f $(if $(KBUILD_SRC),$(srctree)/)scripts/Makefile.clean obj
+
+# The filename Kbuild has precedence over Makefile
+kbuild-dir := $(if $(filter /%,$(src)),$(src),$(srctree)/$(src))
+include $(if $(wildcard $(kbuild-dir)/Kbuild), $(kbuild-dir)/Kbuild, $(kbuild-dir)/Makefile)
+
+# Figure out what we need to build from the various variables
+# ==========================================================================
+
+__subdir-y	:= $(patsubst %/,%,$(filter %/, $(obj-y)))
+subdir-y	+= $(__subdir-y)
+__subdir-m	:= $(patsubst %/,%,$(filter %/, $(obj-m)))
+subdir-m	+= $(__subdir-m)
+__subdir-n	:= $(patsubst %/,%,$(filter %/, $(obj-n)))
+subdir-n	+= $(__subdir-n)
+__subdir-	:= $(patsubst %/,%,$(filter %/, $(obj-)))
+subdir-		+= $(__subdir-)
+
+# Subdirectories we need to descend into
+
+subdir-ym	:= $(sort $(subdir-y) $(subdir-m))
+subdir-ymn      := $(sort $(subdir-ym) $(subdir-n) $(subdir-))
+
+# Add subdir path
+
+subdir-ymn	:= $(addprefix $(obj)/,$(subdir-ymn))
+
+# Temporal work-around for U-Boot
+
+subdir-ymn	:= $(foreach f, $(subdir-ymn), \
+				$(if $(wildcard $(srctree)/$f/Makefile),$f))
+
+# build a list of files to remove, usually relative to the current
+# directory
+
+__clean-files	:= $(extra-y) $(always)                  \
+		   $(targets) $(clean-files)             \
+		   $(host-progs)                         \
+		   $(hostprogs-y) $(hostprogs-m) $(hostprogs-)
+
+__clean-files   := $(filter-out $(no-clean-files), $(__clean-files))
+
+# as clean-files is given relative to the current directory, this adds
+# a $(obj) prefix, except for absolute paths
+
+__clean-files   := $(wildcard                                               \
+                   $(addprefix $(obj)/, $(filter-out /%, $(__clean-files))) \
+		   $(filter /%, $(__clean-files)))
+
+# as clean-dirs is given relative to the current directory, this adds
+# a $(obj) prefix, except for absolute paths
+
+__clean-dirs    := $(wildcard                                               \
+                   $(addprefix $(obj)/, $(filter-out /%, $(clean-dirs)))    \
+		   $(filter /%, $(clean-dirs)))
+
+# ==========================================================================
+
+quiet_cmd_clean    = CLEAN   $(obj)
+      cmd_clean    = rm -f $(__clean-files)
+quiet_cmd_cleandir = CLEAN   $(__clean-dirs)
+      cmd_cleandir = rm -rf $(__clean-dirs)
+
+
+__clean: $(subdir-ymn)
+ifneq ($(strip $(__clean-files)),)
+	+$(call cmd,clean)
+endif
+ifneq ($(strip $(__clean-dirs)),)
+	+$(call cmd,cleandir)
+endif
+ifneq ($(strip $(clean-rule)),)
+	+$(clean-rule)
+endif
+	@:
+
+
+# ===========================================================================
+# Generic stuff
+# ===========================================================================
+
+# Descending
+# ---------------------------------------------------------------------------
+
+PHONY += $(subdir-ymn)
+$(subdir-ymn):
+	$(Q)$(MAKE) $(clean)=$@
+
+# If quiet is set, only print short version of command
+
+cmd = @$(if $($(quiet)cmd_$(1)),echo '  $($(quiet)cmd_$(1))' &&) $(cmd_$(1))
+
+
+# Declare the contents of the .PHONY variable as phony.  We keep that
+# information in a variable se we can use it in if_changed and friends.
+
+.PHONY: $(PHONY)
diff --git a/scripts/Makefile.host b/scripts/Makefile.host
new file mode 100644
index 0000000000..1ac414fd50
--- /dev/null
+++ b/scripts/Makefile.host
@@ -0,0 +1,170 @@
+# ==========================================================================
+# Building binaries on the host system
+# Binaries are used during the compilation of the kernel, for example
+# to preprocess a data file.
+#
+# Both C and C++ are supported, but preferred language is C for such utilities.
+#
+# Sample syntax (see Documentation/kbuild/makefiles.txt for reference)
+# hostprogs-y := bin2hex
+# Will compile bin2hex.c and create an executable named bin2hex
+#
+# hostprogs-y    := lxdialog
+# lxdialog-objs := checklist.o lxdialog.o
+# Will compile lxdialog.c and checklist.c, and then link the executable
+# lxdialog, based on checklist.o and lxdialog.o
+#
+# hostprogs-y      := qconf
+# qconf-cxxobjs   := qconf.o
+# qconf-objs      := menu.o
+# Will compile qconf as a C++ program, and menu as a C program.
+# They are linked as C++ code to the executable qconf
+
+# hostprogs-y := conf
+# conf-objs  := conf.o libkconfig.so
+# libkconfig-objs := expr.o type.o
+# Will create a shared library named libkconfig.so that consists of
+# expr.o and type.o (they are both compiled as C code and the object files
+# are made as position independent code).
+# conf.c is compiled as a C program, and conf.o is linked together with
+# libkconfig.so as the executable conf.
+# Note: Shared libraries consisting of C++ files are not supported
+
+__hostprogs := $(sort $(hostprogs-y) $(hostprogs-m))
+
+# C code
+# Executables compiled from a single .c file
+host-csingle	:= $(foreach m,$(__hostprogs),$(if $($(m)-objs),,$(m)))
+
+# C executables linked based on several .o files
+host-cmulti	:= $(foreach m,$(__hostprogs),\
+		   $(if $($(m)-cxxobjs),,$(if $($(m)-objs),$(m))))
+
+# Object (.o) files compiled from .c files
+host-cobjs	:= $(sort $(foreach m,$(__hostprogs),$($(m)-objs)))
+
+# C++ code
+# C++ executables compiled from at least on .cc file
+# and zero or more .c files
+host-cxxmulti	:= $(foreach m,$(__hostprogs),$(if $($(m)-cxxobjs),$(m)))
+
+# C++ Object (.o) files compiled from .cc files
+host-cxxobjs	:= $(sort $(foreach m,$(host-cxxmulti),$($(m)-cxxobjs)))
+
+# Shared libaries (only .c supported)
+# Shared libraries (.so) - all .so files referenced in "xxx-objs"
+host-cshlib	:= $(sort $(filter %.so, $(host-cobjs)))
+# Remove .so files from "xxx-objs"
+host-cobjs	:= $(filter-out %.so,$(host-cobjs))
+
+#Object (.o) files used by the shared libaries
+host-cshobjs	:= $(sort $(foreach m,$(host-cshlib),$($(m:.so=-objs))))
+
+# output directory for programs/.o files
+# hostprogs-y := tools/build may have been specified. Retrieve directory
+host-objdirs := $(foreach f,$(__hostprogs), $(if $(dir $(f)),$(dir $(f))))
+# directory of .o files from prog-objs notation
+host-objdirs += $(foreach f,$(host-cmulti),                  \
+                    $(foreach m,$($(f)-objs),                \
+                        $(if $(dir $(m)),$(dir $(m)))))
+# directory of .o files from prog-cxxobjs notation
+host-objdirs += $(foreach f,$(host-cxxmulti),                  \
+                    $(foreach m,$($(f)-cxxobjs),                \
+                        $(if $(dir $(m)),$(dir $(m)))))
+
+host-objdirs := $(strip $(sort $(filter-out ./,$(host-objdirs))))
+
+
+__hostprogs     := $(addprefix $(obj)/,$(__hostprogs))
+host-csingle	:= $(addprefix $(obj)/,$(host-csingle))
+host-cmulti	:= $(addprefix $(obj)/,$(host-cmulti))
+host-cobjs	:= $(addprefix $(obj)/,$(host-cobjs))
+host-cxxmulti	:= $(addprefix $(obj)/,$(host-cxxmulti))
+host-cxxobjs	:= $(addprefix $(obj)/,$(host-cxxobjs))
+host-cshlib	:= $(addprefix $(obj)/,$(host-cshlib))
+host-cshobjs	:= $(addprefix $(obj)/,$(host-cshobjs))
+host-objdirs    := $(addprefix $(obj)/,$(host-objdirs))
+
+obj-dirs += $(host-objdirs)
+
+#####
+# Handle options to gcc. Support building with separate output directory
+
+_hostc_flags   = $(HOSTCFLAGS)   $(HOST_EXTRACFLAGS)   \
+                 $(HOSTCFLAGS_$(basetarget).o)
+_hostcxx_flags = $(HOSTCXXFLAGS) $(HOST_EXTRACXXFLAGS) \
+                 $(HOSTCXXFLAGS_$(basetarget).o)
+
+ifeq ($(KBUILD_SRC),)
+__hostc_flags	= $(_hostc_flags)
+__hostcxx_flags	= $(_hostcxx_flags)
+else
+__hostc_flags	= -I$(obj) $(call flags,_hostc_flags)
+__hostcxx_flags	= -I$(obj) $(call flags,_hostcxx_flags)
+endif
+
+hostc_flags    = -Wp,-MD,$(depfile) $(__hostc_flags)
+hostcxx_flags  = -Wp,-MD,$(depfile) $(__hostcxx_flags)
+
+#####
+# Compile programs on the host
+
+# Create executable from a single .c file
+# host-csingle -> Executable
+quiet_cmd_host-csingle 	= HOSTCC  $@
+      cmd_host-csingle	= $(HOSTCC) $(hostc_flags) -o $@ $< \
+	  	$(HOST_LOADLIBES) $(HOSTLOADLIBES_$(@F))
+$(host-csingle): $(obj)/%: $(src)/%.c FORCE
+	$(call if_changed_dep,host-csingle)
+
+# Link an executable based on list of .o files, all plain c
+# host-cmulti -> executable
+quiet_cmd_host-cmulti	= HOSTLD  $@
+      cmd_host-cmulti	= $(HOSTCC) $(HOSTLDFLAGS) -o $@ \
+			  $(addprefix $(obj)/,$($(@F)-objs)) \
+			  $(HOST_LOADLIBES) $(HOSTLOADLIBES_$(@F))
+$(host-cmulti): $(obj)/%: $(host-cobjs) $(host-cshlib) FORCE
+	$(call if_changed,host-cmulti)
+
+# Create .o file from a single .c file
+# host-cobjs -> .o
+quiet_cmd_host-cobjs	= HOSTCC  $@
+      cmd_host-cobjs	= $(HOSTCC) $(hostc_flags) -c -o $@ $<
+$(host-cobjs): $(obj)/%.o: $(src)/%.c FORCE
+	$(call if_changed_dep,host-cobjs)
+
+# Link an executable based on list of .o files, a mixture of .c and .cc
+# host-cxxmulti -> executable
+quiet_cmd_host-cxxmulti	= HOSTLD  $@
+      cmd_host-cxxmulti	= $(HOSTCXX) $(HOSTLDFLAGS) -o $@ \
+			  $(foreach o,objs cxxobjs,\
+			  $(addprefix $(obj)/,$($(@F)-$(o)))) \
+			  $(HOST_LOADLIBES) $(HOSTLOADLIBES_$(@F))
+$(host-cxxmulti): $(obj)/%: $(host-cobjs) $(host-cxxobjs) $(host-cshlib) FORCE
+	$(call if_changed,host-cxxmulti)
+
+# Create .o file from a single .cc (C++) file
+quiet_cmd_host-cxxobjs	= HOSTCXX $@
+      cmd_host-cxxobjs	= $(HOSTCXX) $(hostcxx_flags) -c -o $@ $<
+$(host-cxxobjs): $(obj)/%.o: $(src)/%.cc FORCE
+	$(call if_changed_dep,host-cxxobjs)
+
+# Compile .c file, create position independent .o file
+# host-cshobjs -> .o
+quiet_cmd_host-cshobjs	= HOSTCC  -fPIC $@
+      cmd_host-cshobjs	= $(HOSTCC) $(hostc_flags) -fPIC -c -o $@ $<
+$(host-cshobjs): $(obj)/%.o: $(src)/%.c FORCE
+	$(call if_changed_dep,host-cshobjs)
+
+# Link a shared library, based on position independent .o files
+# *.o -> .so shared library (host-cshlib)
+quiet_cmd_host-cshlib	= HOSTLLD -shared $@
+      cmd_host-cshlib	= $(HOSTCC) $(HOSTLDFLAGS) -shared -o $@ \
+			  $(addprefix $(obj)/,$($(@F:.so=-objs))) \
+			  $(HOST_LOADLIBES) $(HOSTLOADLIBES_$(@F))
+$(host-cshlib): $(obj)/%: $(host-cshobjs) FORCE
+	$(call if_changed,host-cshlib)
+
+targets += $(host-csingle)  $(host-cmulti) $(host-cobjs)\
+	   $(host-cxxmulti) $(host-cxxobjs) $(host-cshlib) $(host-cshobjs) 
+
diff --git a/scripts/Makefile.lib b/scripts/Makefile.lib
new file mode 100644
index 0000000000..d568fde2cc
--- /dev/null
+++ b/scripts/Makefile.lib
@@ -0,0 +1,373 @@
+# Backward compatibility
+asflags-y  += $(EXTRA_AFLAGS)
+ccflags-y  += $(EXTRA_CFLAGS)
+cppflags-y += $(EXTRA_CPPFLAGS)
+ldflags-y  += $(EXTRA_LDFLAGS)
+
+#
+# flags that take effect in sub directories
+export KBUILD_SUBDIR_ASFLAGS := $(KBUILD_SUBDIR_ASFLAGS) $(subdir-asflags-y)
+export KBUILD_SUBDIR_CCFLAGS := $(KBUILD_SUBDIR_CCFLAGS) $(subdir-ccflags-y)
+
+# Figure out what we need to build from the various variables
+# ===========================================================================
+
+# When an object is listed to be built compiled-in and modular,
+# only build the compiled-in version
+
+obj-m := $(filter-out $(obj-y),$(obj-m))
+
+# Libraries are always collected in one lib file.
+# Filter out objects already built-in
+
+lib-y := $(filter-out $(obj-y), $(sort $(lib-y) $(lib-m)))
+
+
+# Handle objects in subdirs
+# ---------------------------------------------------------------------------
+# o if we encounter foo/ in $(obj-y), replace it by foo/built-in.o
+#   and add the directory to the list of dirs to descend into: $(subdir-y)
+# o if we encounter foo/ in $(obj-m), remove it from $(obj-m) 
+#   and add the directory to the list of dirs to descend into: $(subdir-m)
+
+# Determine modorder.
+# Unfortunately, we don't have information about ordering between -y
+# and -m subdirs.  Just put -y's first.
+modorder	:= $(patsubst %/,%/modules.order, $(filter %/, $(obj-y)) $(obj-m:.o=.ko))
+
+__subdir-y	:= $(patsubst %/,%,$(filter %/, $(obj-y)))
+subdir-y	+= $(__subdir-y)
+__subdir-m	:= $(patsubst %/,%,$(filter %/, $(obj-m)))
+subdir-m	+= $(__subdir-m)
+obj-y		:= $(patsubst %/, %/built-in.o, $(obj-y))
+obj-m		:= $(filter-out %/, $(obj-m))
+
+# Subdirectories we need to descend into
+
+subdir-ym	:= $(sort $(subdir-y) $(subdir-m))
+
+# if $(foo-objs) exists, foo.o is a composite object 
+multi-used-y := $(sort $(foreach m,$(obj-y), $(if $(strip $($(m:.o=-objs)) $($(m:.o=-y))), $(m))))
+multi-used-m := $(sort $(foreach m,$(obj-m), $(if $(strip $($(m:.o=-objs)) $($(m:.o=-y))), $(m))))
+multi-used   := $(multi-used-y) $(multi-used-m)
+single-used-m := $(sort $(filter-out $(multi-used-m),$(obj-m)))
+
+# Build list of the parts of our composite objects, our composite
+# objects depend on those (obviously)
+multi-objs-y := $(foreach m, $(multi-used-y), $($(m:.o=-objs)) $($(m:.o=-y)))
+multi-objs-m := $(foreach m, $(multi-used-m), $($(m:.o=-objs)) $($(m:.o=-y)))
+multi-objs   := $(multi-objs-y) $(multi-objs-m)
+
+# $(subdir-obj-y) is the list of objects in $(obj-y) which uses dir/ to
+# tell kbuild to descend
+subdir-obj-y := $(filter %/built-in.o, $(obj-y))
+
+# $(obj-dirs) is a list of directories that contain object files
+obj-dirs := $(dir $(multi-objs) $(obj-y))
+
+# Replace multi-part objects by their individual parts, look at local dir only
+real-objs-y := $(foreach m, $(filter-out $(subdir-obj-y), $(obj-y)), $(if $(strip $($(m:.o=-objs)) $($(m:.o=-y))),$($(m:.o=-objs)) $($(m:.o=-y)),$(m))) $(extra-y)
+real-objs-m := $(foreach m, $(obj-m), $(if $(strip $($(m:.o=-objs)) $($(m:.o=-y))),$($(m:.o=-objs)) $($(m:.o=-y)),$(m)))
+
+# Add subdir path
+
+extra-y		:= $(addprefix $(obj)/,$(extra-y))
+always		:= $(addprefix $(obj)/,$(always))
+targets		:= $(addprefix $(obj)/,$(targets))
+modorder	:= $(addprefix $(obj)/,$(modorder))
+obj-y		:= $(addprefix $(obj)/,$(obj-y))
+obj-m		:= $(addprefix $(obj)/,$(obj-m))
+lib-y		:= $(addprefix $(obj)/,$(lib-y))
+subdir-obj-y	:= $(addprefix $(obj)/,$(subdir-obj-y))
+real-objs-y	:= $(addprefix $(obj)/,$(real-objs-y))
+real-objs-m	:= $(addprefix $(obj)/,$(real-objs-m))
+single-used-m	:= $(addprefix $(obj)/,$(single-used-m))
+multi-used-y	:= $(addprefix $(obj)/,$(multi-used-y))
+multi-used-m	:= $(addprefix $(obj)/,$(multi-used-m))
+multi-objs-y	:= $(addprefix $(obj)/,$(multi-objs-y))
+multi-objs-m	:= $(addprefix $(obj)/,$(multi-objs-m))
+subdir-ym	:= $(addprefix $(obj)/,$(subdir-ym))
+obj-dirs	:= $(addprefix $(obj)/,$(obj-dirs))
+
+# These flags are needed for modversions and compiling, so we define them here
+# already
+# $(modname_flags) #defines KBUILD_MODNAME as the name of the module it will 
+# end up in (or would, if it gets compiled in)
+# Note: Files that end up in two or more modules are compiled without the
+#       KBUILD_MODNAME definition. The reason is that any made-up name would
+#       differ in different configs.
+name-fix = $(subst $(comma),_,$(subst -,_,$1))
+basename_flags = -D"KBUILD_BASENAME=KBUILD_STR($(call name-fix,$(basetarget)))"
+modname_flags  = $(if $(filter 1,$(words $(modname))),\
+                 -D"KBUILD_MODNAME=KBUILD_STR($(call name-fix,$(modname)))")
+
+orig_c_flags   = $(KBUILD_CPPFLAGS) $(KBUILD_CFLAGS) $(KBUILD_SUBDIR_CCFLAGS) \
+                 $(ccflags-y) $(CFLAGS_$(basetarget).o)
+_c_flags       = $(filter-out $(CFLAGS_REMOVE_$(basetarget).o), $(orig_c_flags))
+_a_flags       = $(KBUILD_CPPFLAGS) $(KBUILD_AFLAGS) $(KBUILD_SUBDIR_ASFLAGS) \
+                 $(asflags-y) $(AFLAGS_$(basetarget).o)
+_cpp_flags     = $(KBUILD_CPPFLAGS) $(cppflags-y) $(CPPFLAGS_$(@F))
+
+#
+# Enable gcov profiling flags for a file, directory or for all files depending
+# on variables GCOV_PROFILE_obj.o, GCOV_PROFILE and CONFIG_GCOV_PROFILE_ALL
+# (in this order)
+#
+ifeq ($(CONFIG_GCOV_KERNEL),y)
+_c_flags += $(if $(patsubst n%,, \
+		$(GCOV_PROFILE_$(basetarget).o)$(GCOV_PROFILE)$(CONFIG_GCOV_PROFILE_ALL)), \
+		$(CFLAGS_GCOV))
+endif
+
+# If building the kernel in a separate objtree expand all occurrences
+# of -Idir to -I$(srctree)/dir except for absolute paths (starting with '/').
+
+ifeq ($(KBUILD_SRC),)
+__c_flags	= $(_c_flags)
+__a_flags	= $(_a_flags)
+__cpp_flags     = $(_cpp_flags)
+else
+
+# -I$(obj) locates generated .h files
+# $(call addtree,-I$(obj)) locates .h files in srctree, from generated .c files
+#   and locates generated .h files
+# FIXME: Replace both with specific CFLAGS* statements in the makefiles
+__c_flags	= $(call addtree,-I$(obj)) $(call flags,_c_flags)
+__a_flags	=                          $(call flags,_a_flags)
+__cpp_flags     =                          $(call flags,_cpp_flags)
+endif
+
+# Modified for U-Boot: LINUXINCLUDE -> UBOOTINCLUDE
+c_flags        = -Wp,-MD,$(depfile) $(NOSTDINC_FLAGS) $(UBOOTINCLUDE)     \
+		 $(__c_flags) $(modkern_cflags)                           \
+		 -D"KBUILD_STR(s)=\#s" $(basename_flags) $(modname_flags)
+
+a_flags        = -Wp,-MD,$(depfile) $(NOSTDINC_FLAGS) $(UBOOTINCLUDE)     \
+		 $(__a_flags) $(modkern_aflags)
+
+cpp_flags      = -Wp,-MD,$(depfile) $(NOSTDINC_FLAGS) $(UBOOTINCLUDE)     \
+		 $(__cpp_flags)
+
+ld_flags       = $(LDFLAGS) $(ldflags-y)
+
+# Modified for U-Boot
+dtc_cpp_flags  = -Wp,-MD,$(depfile).pre.tmp -nostdinc                    \
+		 -I$(srctree)/arch/$(ARCH)/dts                           \
+		 -undef -D__DTS__
+
+# Finds the multi-part object the current object will be linked into
+modname-multi = $(sort $(foreach m,$(multi-used),\
+		$(if $(filter $(subst $(obj)/,,$*.o), $($(m:.o=-objs)) $($(m:.o=-y))),$(m:.o=))))
+
+ifdef REGENERATE_PARSERS
+
+# GPERF
+# ---------------------------------------------------------------------------
+quiet_cmd_gperf = GPERF $@
+      cmd_gperf = gperf -t --output-file $@ -a -C -E -g -k 1,3,$$ -p -t $<
+
+.PRECIOUS: $(src)/%.hash.c_shipped
+$(src)/%.hash.c_shipped: $(src)/%.gperf
+	$(call cmd,gperf)
+
+# LEX
+# ---------------------------------------------------------------------------
+LEX_PREFIX = $(if $(LEX_PREFIX_${baseprereq}),$(LEX_PREFIX_${baseprereq}),yy)
+
+quiet_cmd_flex = LEX     $@
+      cmd_flex = flex -o$@ -L -P $(LEX_PREFIX) $<
+
+.PRECIOUS: $(src)/%.lex.c_shipped
+$(src)/%.lex.c_shipped: $(src)/%.l
+	$(call cmd,flex)
+
+# YACC
+# ---------------------------------------------------------------------------
+YACC_PREFIX = $(if $(YACC_PREFIX_${baseprereq}),$(YACC_PREFIX_${baseprereq}),yy)
+
+quiet_cmd_bison = YACC    $@
+      cmd_bison = bison -o$@ -t -l -p $(YACC_PREFIX) $<
+
+.PRECIOUS: $(src)/%.tab.c_shipped
+$(src)/%.tab.c_shipped: $(src)/%.y
+	$(call cmd,bison)
+
+quiet_cmd_bison_h = YACC    $@
+      cmd_bison_h = bison -o/dev/null --defines=$@ -t -l -p $(YACC_PREFIX) $<
+
+.PRECIOUS: $(src)/%.tab.h_shipped
+$(src)/%.tab.h_shipped: $(src)/%.y
+	$(call cmd,bison_h)
+
+endif
+
+# Shipped files
+# ===========================================================================
+
+quiet_cmd_shipped = SHIPPED $@
+cmd_shipped = cat $< > $@
+
+$(obj)/%: $(src)/%_shipped
+	$(call cmd,shipped)
+
+# Commands useful for building a boot image
+# ===========================================================================
+# 
+#	Use as following:
+#
+#	target: source(s) FORCE
+#		$(if_changed,ld/objcopy/gzip)
+#
+#	and add target to extra-y so that we know we have to
+#	read in the saved command line
+
+# Linking
+# ---------------------------------------------------------------------------
+
+quiet_cmd_ld = LD      $@
+cmd_ld = $(LD) $(LDFLAGS) $(ldflags-y) $(LDFLAGS_$(@F)) \
+	       $(filter-out FORCE,$^) -o $@ 
+
+# Objcopy
+# ---------------------------------------------------------------------------
+
+quiet_cmd_objcopy = OBJCOPY $@
+cmd_objcopy = $(OBJCOPY) $(OBJCOPYFLAGS) $(OBJCOPYFLAGS_$(@F)) $< $@
+
+# Gzip
+# ---------------------------------------------------------------------------
+
+quiet_cmd_gzip = GZIP    $@
+cmd_gzip = (cat $(filter-out FORCE,$^) | gzip -n -f -9 > $@) || \
+	(rm -f $@ ; false)
+
+# DTC
+# ---------------------------------------------------------------------------
+
+# Generate an assembly file to wrap the output of the device tree compiler
+quiet_cmd_dt_S_dtb= DTB     $@
+# Modified for U-Boot
+cmd_dt_S_dtb=						\
+(							\
+	echo '.section .dtb.init.rodata,"a"';		\
+	echo '.global __dtb_$(*F)_begin';		\
+	echo '__dtb_$(*F)_begin:';			\
+	echo '.incbin "$<" ';				\
+	echo '__dtb_$(*F)_end:';			\
+	echo '.global __dtb_$(*F)_end';			\
+) > $@
+
+$(obj)/%.dtb.S: $(obj)/%.dtb
+	$(call cmd,dt_S_dtb)
+
+quiet_cmd_dtc = DTC     $@
+# Modified for U-Boot
+cmd_dtc = $(CPP) $(dtc_cpp_flags) -x assembler-with-cpp -o $(dtc-tmp) $< ; \
+	dtc -O dtb -o $@ -b 0 \
+		-i $(dir $<) $(DTC_FLAGS) \
+		-d $(depfile).dtc.tmp $(dtc-tmp) ; \
+	cat $(depfile).pre.tmp $(depfile).dtc.tmp > $(depfile)
+
+$(obj)/%.dtb: $(src)/%.dts FORCE
+	$(call if_changed_dep,dtc)
+
+dtc-tmp = $(subst $(comma),_,$(dot-target).dts.tmp)
+
+# Bzip2
+# ---------------------------------------------------------------------------
+
+# Bzip2 and LZMA do not include size in file... so we have to fake that;
+# append the size as a 32-bit littleendian number as gzip does.
+size_append = printf $(shell						\
+dec_size=0;								\
+for F in $1; do								\
+	fsize=$$(stat -c "%s" $$F);					\
+	dec_size=$$(expr $$dec_size + $$fsize);				\
+done;									\
+printf "%08x\n" $$dec_size |						\
+	sed 's/\(..\)/\1 /g' | {					\
+		read ch0 ch1 ch2 ch3;					\
+		for ch in $$ch3 $$ch2 $$ch1 $$ch0; do			\
+			printf '%s%03o' '\\' $$((0x$$ch)); 		\
+		done;							\
+	}								\
+)
+
+quiet_cmd_bzip2 = BZIP2   $@
+cmd_bzip2 = (cat $(filter-out FORCE,$^) | \
+	bzip2 -9 && $(call size_append, $(filter-out FORCE,$^))) > $@ || \
+	(rm -f $@ ; false)
+
+# Lzma
+# ---------------------------------------------------------------------------
+
+quiet_cmd_lzma = LZMA    $@
+cmd_lzma = (cat $(filter-out FORCE,$^) | \
+	lzma -9 && $(call size_append, $(filter-out FORCE,$^))) > $@ || \
+	(rm -f $@ ; false)
+
+quiet_cmd_lzo = LZO     $@
+cmd_lzo = (cat $(filter-out FORCE,$^) | \
+	lzop -9 && $(call size_append, $(filter-out FORCE,$^))) > $@ || \
+	(rm -f $@ ; false)
+
+quiet_cmd_lz4 = LZ4     $@
+cmd_lz4 = (cat $(filter-out FORCE,$^) | \
+	lz4c -l -c1 stdin stdout && $(call size_append, $(filter-out FORCE,$^))) > $@ || \
+	(rm -f $@ ; false)
+
+# U-Boot mkimage
+# ---------------------------------------------------------------------------
+
+MKIMAGE := $(srctree)/scripts/mkuboot.sh
+
+# SRCARCH just happens to match slightly more than ARCH (on sparc), so reduces
+# the number of overrides in arch makefiles
+UIMAGE_ARCH ?= $(SRCARCH)
+UIMAGE_COMPRESSION ?= $(if $(2),$(2),none)
+UIMAGE_OPTS-y ?=
+UIMAGE_TYPE ?= kernel
+UIMAGE_LOADADDR ?= arch_must_set_this
+UIMAGE_ENTRYADDR ?= $(UIMAGE_LOADADDR)
+UIMAGE_NAME ?= 'Linux-$(KERNELRELEASE)'
+UIMAGE_IN ?= $<
+UIMAGE_OUT ?= $@
+
+quiet_cmd_uimage = UIMAGE  $(UIMAGE_OUT)
+      cmd_uimage = $(CONFIG_SHELL) $(MKIMAGE) -A $(UIMAGE_ARCH) -O linux \
+			-C $(UIMAGE_COMPRESSION) $(UIMAGE_OPTS-y) \
+			-T $(UIMAGE_TYPE) \
+			-a $(UIMAGE_LOADADDR) -e $(UIMAGE_ENTRYADDR) \
+			-n $(UIMAGE_NAME) -d $(UIMAGE_IN) $(UIMAGE_OUT)
+
+# XZ
+# ---------------------------------------------------------------------------
+# Use xzkern to compress the kernel image and xzmisc to compress other things.
+#
+# xzkern uses a big LZMA2 dictionary since it doesn't increase memory usage
+# of the kernel decompressor. A BCJ filter is used if it is available for
+# the target architecture. xzkern also appends uncompressed size of the data
+# using size_append. The .xz format has the size information available at
+# the end of the file too, but it's in more complex format and it's good to
+# avoid changing the part of the boot code that reads the uncompressed size.
+# Note that the bytes added by size_append will make the xz tool think that
+# the file is corrupt. This is expected.
+#
+# xzmisc doesn't use size_append, so it can be used to create normal .xz
+# files. xzmisc uses smaller LZMA2 dictionary than xzkern, because a very
+# big dictionary would increase the memory usage too much in the multi-call
+# decompression mode. A BCJ filter isn't used either.
+quiet_cmd_xzkern = XZKERN  $@
+cmd_xzkern = (cat $(filter-out FORCE,$^) | \
+	sh $(srctree)/scripts/xz_wrap.sh && \
+	$(call size_append, $(filter-out FORCE,$^))) > $@ || \
+	(rm -f $@ ; false)
+
+quiet_cmd_xzmisc = XZMISC  $@
+cmd_xzmisc = (cat $(filter-out FORCE,$^) | \
+	xz --check=crc32 --lzma2=dict=1MiB) > $@ || \
+	(rm -f $@ ; false)
+
+# misc stuff
+# ---------------------------------------------------------------------------
+quote:="
diff --git a/scripts/basic/.gitignore b/scripts/basic/.gitignore
new file mode 100644
index 0000000000..a776371a35
--- /dev/null
+++ b/scripts/basic/.gitignore
@@ -0,0 +1 @@
+fixdep
diff --git a/scripts/basic/Makefile b/scripts/basic/Makefile
new file mode 100644
index 0000000000..4fcef87bb8
--- /dev/null
+++ b/scripts/basic/Makefile
@@ -0,0 +1,15 @@
+###
+# Makefile.basic lists the most basic programs used during the build process.
+# The programs listed herein are what are needed to do the basic stuff,
+# such as fix file dependencies.
+# This initial step is needed to avoid files to be recompiled
+# when kernel configuration changes (which is what happens when
+# .config is included by main Makefile.
+# ---------------------------------------------------------------------------
+# fixdep: 	 Used to generate dependency information during build process
+
+hostprogs-y	:= fixdep
+always		:= $(hostprogs-y)
+
+# fixdep is needed to compile other host programs
+$(addprefix $(obj)/,$(filter-out fixdep,$(always))): $(obj)/fixdep
diff --git a/scripts/basic/fixdep.c b/scripts/basic/fixdep.c
new file mode 100644
index 0000000000..078fe1d64e
--- /dev/null
+++ b/scripts/basic/fixdep.c
@@ -0,0 +1,462 @@
+/*
+ * "Optimize" a list of dependencies as spit out by gcc -MD
+ * for the kernel build
+ * ===========================================================================
+ *
+ * Author       Kai Germaschewski
+ * Copyright    2002 by Kai Germaschewski  <kai.germaschewski@gmx.de>
+ *
+ * This software may be used and distributed according to the terms
+ * of the GNU General Public License, incorporated herein by reference.
+ *
+ *
+ * Introduction:
+ *
+ * gcc produces a very nice and correct list of dependencies which
+ * tells make when to remake a file.
+ *
+ * To use this list as-is however has the drawback that virtually
+ * every file in the kernel includes autoconf.h.
+ *
+ * If the user re-runs make *config, autoconf.h will be
+ * regenerated.  make notices that and will rebuild every file which
+ * includes autoconf.h, i.e. basically all files. This is extremely
+ * annoying if the user just changed CONFIG_HIS_DRIVER from n to m.
+ *
+ * So we play the same trick that "mkdep" played before. We replace
+ * the dependency on autoconf.h by a dependency on every config
+ * option which is mentioned in any of the listed prequisites.
+ *
+ * kconfig populates a tree in include/config/ with an empty file
+ * for each config symbol and when the configuration is updated
+ * the files representing changed config options are touched
+ * which then let make pick up the changes and the files that use
+ * the config symbols are rebuilt.
+ *
+ * So if the user changes his CONFIG_HIS_DRIVER option, only the objects
+ * which depend on "include/linux/config/his/driver.h" will be rebuilt,
+ * so most likely only his driver ;-)
+ *
+ * The idea above dates, by the way, back to Michael E Chastain, AFAIK.
+ *
+ * So to get dependencies right, there are two issues:
+ * o if any of the files the compiler read changed, we need to rebuild
+ * o if the command line given to the compile the file changed, we
+ *   better rebuild as well.
+ *
+ * The former is handled by using the -MD output, the later by saving
+ * the command line used to compile the old object and comparing it
+ * to the one we would now use.
+ *
+ * Again, also this idea is pretty old and has been discussed on
+ * kbuild-devel a long time ago. I don't have a sensibly working
+ * internet connection right now, so I rather don't mention names
+ * without double checking.
+ *
+ * This code here has been based partially based on mkdep.c, which
+ * says the following about its history:
+ *
+ *   Copyright abandoned, Michael Chastain, <mailto:mec@shout.net>.
+ *   This is a C version of syncdep.pl by Werner Almesberger.
+ *
+ *
+ * It is invoked as
+ *
+ *   fixdep <depfile> <target> <cmdline>
+ *
+ * and will read the dependency file <depfile>
+ *
+ * The transformed dependency snipped is written to stdout.
+ *
+ * It first generates a line
+ *
+ *   cmd_<target> = <cmdline>
+ *
+ * and then basically copies the .<target>.d file to stdout, in the
+ * process filtering out the dependency on autoconf.h and adding
+ * dependencies on include/config/my/option.h for every
+ * CONFIG_MY_OPTION encountered in any of the prequisites.
+ *
+ * It will also filter out all the dependencies on *.ver. We need
+ * to make sure that the generated version checksum are globally up
+ * to date before even starting the recursive build, so it's too late
+ * at this point anyway.
+ *
+ * The algorithm to grep for "CONFIG_..." is bit unusual, but should
+ * be fast ;-) We don't even try to really parse the header files, but
+ * merely grep, i.e. if CONFIG_FOO is mentioned in a comment, it will
+ * be picked up as well. It's not a problem with respect to
+ * correctness, since that can only give too many dependencies, thus
+ * we cannot miss a rebuild. Since people tend to not mention totally
+ * unrelated CONFIG_ options all over the place, it's not an
+ * efficiency problem either.
+ *
+ * (Note: it'd be easy to port over the complete mkdep state machine,
+ *  but I don't think the added complexity is worth it)
+ */
+/*
+ * Note 2: if somebody writes HELLO_CONFIG_BOOM in a file, it will depend onto
+ * CONFIG_BOOM. This could seem a bug (not too hard to fix), but please do not
+ * fix it! Some UserModeLinux files (look at arch/um/) call CONFIG_BOOM as
+ * UML_CONFIG_BOOM, to avoid conflicts with /usr/include/linux/autoconf.h,
+ * through arch/um/include/uml-config.h; this fixdep "bug" makes sure that
+ * those files will have correct dependencies.
+ */
+
+#include <sys/types.h>
+#include <sys/stat.h>
+#include <sys/mman.h>
+#include <unistd.h>
+#include <fcntl.h>
+#include <string.h>
+#include <stdlib.h>
+#include <stdio.h>
+#include <limits.h>
+#include <ctype.h>
+#include <arpa/inet.h>
+
+#define INT_CONF ntohl(0x434f4e46)
+#define INT_ONFI ntohl(0x4f4e4649)
+#define INT_NFIG ntohl(0x4e464947)
+#define INT_FIG_ ntohl(0x4649475f)
+
+char *target;
+char *depfile;
+char *cmdline;
+
+static void usage(void)
+{
+	fprintf(stderr, "Usage: fixdep <depfile> <target> <cmdline>\n");
+	exit(1);
+}
+
+/*
+ * Print out the commandline prefixed with cmd_<target filename> :=
+ */
+static void print_cmdline(void)
+{
+	printf("cmd_%s := %s\n\n", target, cmdline);
+}
+
+struct item {
+	struct item	*next;
+	unsigned int	len;
+	unsigned int	hash;
+	char		name[0];
+};
+
+#define HASHSZ 256
+static struct item *hashtab[HASHSZ];
+
+static unsigned int strhash(const char *str, unsigned int sz)
+{
+	/* fnv32 hash */
+	unsigned int i, hash = 2166136261U;
+
+	for (i = 0; i < sz; i++)
+		hash = (hash ^ str[i]) * 0x01000193;
+	return hash;
+}
+
+/*
+ * Lookup a value in the configuration string.
+ */
+static int is_defined_config(const char *name, int len, unsigned int hash)
+{
+	struct item *aux;
+
+	for (aux = hashtab[hash % HASHSZ]; aux; aux = aux->next) {
+		if (aux->hash == hash && aux->len == len &&
+		    memcmp(aux->name, name, len) == 0)
+			return 1;
+	}
+	return 0;
+}
+
+/*
+ * Add a new value to the configuration string.
+ */
+static void define_config(const char *name, int len, unsigned int hash)
+{
+	struct item *aux = malloc(sizeof(*aux) + len);
+
+	if (!aux) {
+		perror("fixdep:malloc");
+		exit(1);
+	}
+	memcpy(aux->name, name, len);
+	aux->len = len;
+	aux->hash = hash;
+	aux->next = hashtab[hash % HASHSZ];
+	hashtab[hash % HASHSZ] = aux;
+}
+
+/*
+ * Clear the set of configuration strings.
+ */
+static void clear_config(void)
+{
+	struct item *aux, *next;
+	unsigned int i;
+
+	for (i = 0; i < HASHSZ; i++) {
+		for (aux = hashtab[i]; aux; aux = next) {
+			next = aux->next;
+			free(aux);
+		}
+		hashtab[i] = NULL;
+	}
+}
+
+/*
+ * Record the use of a CONFIG_* word.
+ */
+static void use_config(const char *m, int slen)
+{
+	unsigned int hash = strhash(m, slen);
+	int c, i;
+
+	if (is_defined_config(m, slen, hash))
+	    return;
+
+	define_config(m, slen, hash);
+
+	printf("    $(wildcard include/config/");
+	for (i = 0; i < slen; i++) {
+		c = m[i];
+		if (c == '_')
+			c = '/';
+		else
+			c = tolower(c);
+		putchar(c);
+	}
+	printf(".h) \\\n");
+}
+
+static void parse_config_file(const char *map, size_t len)
+{
+	const int *end = (const int *) (map + len);
+	/* start at +1, so that p can never be < map */
+	const int *m   = (const int *) map + 1;
+	const char *p, *q;
+
+	for (; m < end; m++) {
+		if (*m == INT_CONF) { p = (char *) m  ; goto conf; }
+		if (*m == INT_ONFI) { p = (char *) m-1; goto conf; }
+		if (*m == INT_NFIG) { p = (char *) m-2; goto conf; }
+		if (*m == INT_FIG_) { p = (char *) m-3; goto conf; }
+		continue;
+	conf:
+		if (p > map + len - 7)
+			continue;
+		if (memcmp(p, "CONFIG_", 7))
+			continue;
+		for (q = p + 7; q < map + len; q++) {
+			if (!(isalnum(*q) || *q == '_'))
+				goto found;
+		}
+		continue;
+
+	found:
+		if (!memcmp(q - 7, "_MODULE", 7))
+			q -= 7;
+		if( (q-p-7) < 0 )
+			continue;
+		use_config(p+7, q-p-7);
+	}
+}
+
+/* test is s ends in sub */
+static int strrcmp(char *s, char *sub)
+{
+	int slen = strlen(s);
+	int sublen = strlen(sub);
+
+	if (sublen > slen)
+		return 1;
+
+	return memcmp(s + slen - sublen, sub, sublen);
+}
+
+static void do_config_file(const char *filename)
+{
+	struct stat st;
+	int fd;
+	void *map;
+
+	fd = open(filename, O_RDONLY);
+	if (fd < 0) {
+		fprintf(stderr, "fixdep: error opening config file: ");
+		perror(filename);
+		exit(2);
+	}
+	fstat(fd, &st);
+	if (st.st_size == 0) {
+		close(fd);
+		return;
+	}
+	map = mmap(NULL, st.st_size, PROT_READ, MAP_PRIVATE, fd, 0);
+	if ((long) map == -1) {
+		perror("fixdep: mmap");
+		close(fd);
+		return;
+	}
+
+	parse_config_file(map, st.st_size);
+
+	munmap(map, st.st_size);
+
+	close(fd);
+}
+
+/*
+ * Important: The below generated source_foo.o and deps_foo.o variable
+ * assignments are parsed not only by make, but also by the rather simple
+ * parser in scripts/mod/sumversion.c.
+ */
+static void parse_dep_file(void *map, size_t len)
+{
+	char *m = map;
+	char *end = m + len;
+	char *p;
+	char s[PATH_MAX];
+	int is_target;
+	int saw_any_target = 0;
+	int is_first_dep = 0;
+
+	clear_config();
+
+	while (m < end) {
+		/* Skip any "white space" */
+		while (m < end && (*m == ' ' || *m == '\\' || *m == '\n'))
+			m++;
+		/* Find next "white space" */
+		p = m;
+		while (p < end && *p != ' ' && *p != '\\' && *p != '\n')
+			p++;
+		/* Is the token we found a target name? */
+		is_target = (*(p-1) == ':');
+		/* Don't write any target names into the dependency file */
+		if (is_target) {
+			/* The /next/ file is the first dependency */
+			is_first_dep = 1;
+		} else {
+			/* Save this token/filename */
+			memcpy(s, m, p-m);
+			s[p - m] = 0;
+
+			/* Ignore certain dependencies */
+			if (strrcmp(s, "include/generated/autoconf.h") &&
+			    strrcmp(s, "arch/um/include/uml-config.h") &&
+			    strrcmp(s, "include/linux/kconfig.h") &&
+			    strrcmp(s, ".ver")) {
+				/*
+				 * Do not list the source file as dependency,
+				 * so that kbuild is not confused if a .c file
+				 * is rewritten into .S or vice versa. Storing
+				 * it in source_* is needed for modpost to
+				 * compute srcversions.
+				 */
+				if (is_first_dep) {
+					/*
+					 * If processing the concatenation of
+					 * multiple dependency files, only
+					 * process the first target name, which
+					 * will be the original source name,
+					 * and ignore any other target names,
+					 * which will be intermediate temporary
+					 * files.
+					 */
+					if (!saw_any_target) {
+						saw_any_target = 1;
+						printf("source_%s := %s\n\n",
+							target, s);
+						printf("deps_%s := \\\n",
+							target);
+					}
+					is_first_dep = 0;
+				} else
+					printf("  %s \\\n", s);
+				do_config_file(s);
+			}
+		}
+		/*
+		 * Start searching for next token immediately after the first
+		 * "whitespace" character that follows this token.
+		 */
+		m = p + 1;
+	}
+
+	if (!saw_any_target) {
+		fprintf(stderr, "fixdep: parse error; no targets found\n");
+		exit(1);
+	}
+
+	printf("\n%s: $(deps_%s)\n\n", target, target);
+	printf("$(deps_%s):\n", target);
+}
+
+static void print_deps(void)
+{
+	struct stat st;
+	int fd;
+	void *map;
+
+	fd = open(depfile, O_RDONLY);
+	if (fd < 0) {
+		fprintf(stderr, "fixdep: error opening depfile: ");
+		perror(depfile);
+		exit(2);
+	}
+	if (fstat(fd, &st) < 0) {
+                fprintf(stderr, "fixdep: error fstat'ing depfile: ");
+                perror(depfile);
+                exit(2);
+        }
+	if (st.st_size == 0) {
+		fprintf(stderr,"fixdep: %s is empty\n",depfile);
+		close(fd);
+		return;
+	}
+	map = mmap(NULL, st.st_size, PROT_READ, MAP_PRIVATE, fd, 0);
+	if ((long) map == -1) {
+		perror("fixdep: mmap");
+		close(fd);
+		return;
+	}
+
+	parse_dep_file(map, st.st_size);
+
+	munmap(map, st.st_size);
+
+	close(fd);
+}
+
+static void traps(void)
+{
+	static char test[] __attribute__((aligned(sizeof(int)))) = "CONF";
+	int *p = (int *)test;
+
+	if (*p != INT_CONF) {
+		fprintf(stderr, "fixdep: sizeof(int) != 4 or wrong endianness? %#x\n",
+			*p);
+		exit(2);
+	}
+}
+
+int main(int argc, char *argv[])
+{
+	traps();
+
+	if (argc != 4)
+		usage();
+
+	depfile = argv[1];
+	target = argv[2];
+	cmdline = argv[3];
+
+	print_cmdline();
+	print_deps();
+
+	return 0;
+}
diff --git a/tools/binutils-version.sh b/scripts/binutils-version.sh
index d4d9eb4361..d4d9eb4361 100755..100644
--- a/tools/binutils-version.sh
+++ b/scripts/binutils-version.sh
diff --git a/scripts/checkpatch.pl b/scripts/checkpatch.pl
new file mode 100755
index 0000000000..3fed5e4694
--- /dev/null
+++ b/scripts/checkpatch.pl
@@ -0,0 +1,4573 @@
+#!/usr/bin/perl -w
+# (c) 2001, Dave Jones. (the file handling bit)
+# (c) 2005, Joel Schopp <jschopp@austin.ibm.com> (the ugly bit)
+# (c) 2007,2008, Andy Whitcroft <apw@uk.ibm.com> (new conditions, test suite)
+# (c) 2008-2010 Andy Whitcroft <apw@canonical.com>
+# Licensed under the terms of the GNU GPL License version 2
+
+use strict;
+use POSIX;
+
+my $P = $0;
+$P =~ s@.*/@@g;
+
+my $V = '0.32';
+
+use Getopt::Long qw(:config no_auto_abbrev);
+
+my $quiet = 0;
+my $tree = 1;
+my $chk_signoff = 1;
+my $chk_patch = 1;
+my $tst_only;
+my $emacs = 0;
+my $terse = 0;
+my $file = 0;
+my $check = 0;
+my $summary = 1;
+my $mailback = 0;
+my $summary_file = 0;
+my $show_types = 0;
+my $fix = 0;
+my $fix_inplace = 0;
+my $root;
+my %debug;
+my %camelcase = ();
+my %use_type = ();
+my @use = ();
+my %ignore_type = ();
+my @ignore = ();
+my $help = 0;
+my $configuration_file = ".checkpatch.conf";
+my $max_line_length = 80;
+my $ignore_perl_version = 0;
+my $minimum_perl_version = 5.10.0;
+
+sub help {
+	my ($exitcode) = @_;
+
+	print << "EOM";
+Usage: $P [OPTION]... [FILE]...
+Version: $V
+
+Options:
+  -q, --quiet                quiet
+  --no-tree                  run without a kernel tree
+  --no-signoff               do not check for 'Signed-off-by' line
+  --patch                    treat FILE as patchfile (default)
+  --emacs                    emacs compile window format
+  --terse                    one line per report
+  -f, --file                 treat FILE as regular source file
+  --subjective, --strict     enable more subjective tests
+  --types TYPE(,TYPE2...)    show only these comma separated message types
+  --ignore TYPE(,TYPE2...)   ignore various comma separated message types
+  --max-line-length=n        set the maximum line length, if exceeded, warn
+  --show-types               show the message "types" in the output
+  --root=PATH                PATH to the kernel tree root
+  --no-summary               suppress the per-file summary
+  --mailback                 only produce a report in case of warnings/errors
+  --summary-file             include the filename in summary
+  --debug KEY=[0|1]          turn on/off debugging of KEY, where KEY is one of
+                             'values', 'possible', 'type', and 'attr' (default
+                             is all off)
+  --test-only=WORD           report only warnings/errors containing WORD
+                             literally
+  --fix                      EXPERIMENTAL - may create horrible results
+                             If correctable single-line errors exist, create
+                             "<inputfile>.EXPERIMENTAL-checkpatch-fixes"
+                             with potential errors corrected to the preferred
+                             checkpatch style
+  --fix-inplace              EXPERIMENTAL - may create horrible results
+                             Is the same as --fix, but overwrites the input
+                             file.  It's your fault if there's no backup or git
+  --ignore-perl-version      override checking of perl version.  expect
+                             runtime errors.
+  -h, --help, --version      display this help and exit
+
+When FILE is - read standard input.
+EOM
+
+	exit($exitcode);
+}
+
+my $conf = which_conf($configuration_file);
+if (-f $conf) {
+	my @conf_args;
+	open(my $conffile, '<', "$conf")
+	    or warn "$P: Can't find a readable $configuration_file file $!\n";
+
+	while (<$conffile>) {
+		my $line = $_;
+
+		$line =~ s/\s*\n?$//g;
+		$line =~ s/^\s*//g;
+		$line =~ s/\s+/ /g;
+
+		next if ($line =~ m/^\s*#/);
+		next if ($line =~ m/^\s*$/);
+
+		my @words = split(" ", $line);
+		foreach my $word (@words) {
+			last if ($word =~ m/^#/);
+			push (@conf_args, $word);
+		}
+	}
+	close($conffile);
+	unshift(@ARGV, @conf_args) if @conf_args;
+}
+
+GetOptions(
+	'q|quiet+'	=> \$quiet,
+	'tree!'		=> \$tree,
+	'signoff!'	=> \$chk_signoff,
+	'patch!'	=> \$chk_patch,
+	'emacs!'	=> \$emacs,
+	'terse!'	=> \$terse,
+	'f|file!'	=> \$file,
+	'subjective!'	=> \$check,
+	'strict!'	=> \$check,
+	'ignore=s'	=> \@ignore,
+	'types=s'	=> \@use,
+	'show-types!'	=> \$show_types,
+	'max-line-length=i' => \$max_line_length,
+	'root=s'	=> \$root,
+	'summary!'	=> \$summary,
+	'mailback!'	=> \$mailback,
+	'summary-file!'	=> \$summary_file,
+	'fix!'		=> \$fix,
+	'fix-inplace!'	=> \$fix_inplace,
+	'ignore-perl-version!' => \$ignore_perl_version,
+	'debug=s'	=> \%debug,
+	'test-only=s'	=> \$tst_only,
+	'h|help'	=> \$help,
+	'version'	=> \$help
+) or help(1);
+
+help(0) if ($help);
+
+$fix = 1 if ($fix_inplace);
+
+my $exit = 0;
+
+if ($^V && $^V lt $minimum_perl_version) {
+	printf "$P: requires at least perl version %vd\n", $minimum_perl_version;
+	if (!$ignore_perl_version) {
+		exit(1);
+	}
+}
+
+if ($#ARGV < 0) {
+	print "$P: no input files\n";
+	exit(1);
+}
+
+sub hash_save_array_words {
+	my ($hashRef, $arrayRef) = @_;
+
+	my @array = split(/,/, join(',', @$arrayRef));
+	foreach my $word (@array) {
+		$word =~ s/\s*\n?$//g;
+		$word =~ s/^\s*//g;
+		$word =~ s/\s+/ /g;
+		$word =~ tr/[a-z]/[A-Z]/;
+
+		next if ($word =~ m/^\s*#/);
+		next if ($word =~ m/^\s*$/);
+
+		$hashRef->{$word}++;
+	}
+}
+
+sub hash_show_words {
+	my ($hashRef, $prefix) = @_;
+
+	if ($quiet == 0 && keys %$hashRef) {
+		print "NOTE: $prefix message types:";
+		foreach my $word (sort keys %$hashRef) {
+			print " $word";
+		}
+		print "\n\n";
+	}
+}
+
+hash_save_array_words(\%ignore_type, \@ignore);
+hash_save_array_words(\%use_type, \@use);
+
+my $dbg_values = 0;
+my $dbg_possible = 0;
+my $dbg_type = 0;
+my $dbg_attr = 0;
+for my $key (keys %debug) {
+	## no critic
+	eval "\${dbg_$key} = '$debug{$key}';";
+	die "$@" if ($@);
+}
+
+my $rpt_cleaners = 0;
+
+if ($terse) {
+	$emacs = 1;
+	$quiet++;
+}
+
+if ($tree) {
+	if (defined $root) {
+		if (!top_of_kernel_tree($root)) {
+			die "$P: $root: --root does not point at a valid tree\n";
+		}
+	} else {
+		if (top_of_kernel_tree('.')) {
+			$root = '.';
+		} elsif ($0 =~ m@(.*)/scripts/[^/]*$@ &&
+						top_of_kernel_tree($1)) {
+			$root = $1;
+		}
+	}
+
+	if (!defined $root) {
+		print "Must be run from the top-level dir. of a kernel tree\n";
+		exit(2);
+	}
+}
+
+my $emitted_corrupt = 0;
+
+our $Ident	= qr{
+			[A-Za-z_][A-Za-z\d_]*
+			(?:\s*\#\#\s*[A-Za-z_][A-Za-z\d_]*)*
+		}x;
+our $Storage	= qr{extern|static|asmlinkage};
+our $Sparse	= qr{
+			__user|
+			__kernel|
+			__force|
+			__iomem|
+			__must_check|
+			__init_refok|
+			__kprobes|
+			__ref|
+			__rcu
+		}x;
+our $InitAttributePrefix = qr{__(?:mem|cpu|dev|net_|)};
+our $InitAttributeData = qr{$InitAttributePrefix(?:initdata\b)};
+our $InitAttributeConst = qr{$InitAttributePrefix(?:initconst\b)};
+our $InitAttributeInit = qr{$InitAttributePrefix(?:init\b)};
+our $InitAttribute = qr{$InitAttributeData|$InitAttributeConst|$InitAttributeInit};
+
+# Notes to $Attribute:
+# We need \b after 'init' otherwise 'initconst' will cause a false positive in a check
+our $Attribute	= qr{
+			const|
+			__percpu|
+			__nocast|
+			__safe|
+			__bitwise__|
+			__packed__|
+			__packed2__|
+			__naked|
+			__maybe_unused|
+			__always_unused|
+			__noreturn|
+			__used|
+			__cold|
+			__noclone|
+			__deprecated|
+			__read_mostly|
+			__kprobes|
+			$InitAttribute|
+			____cacheline_aligned|
+			____cacheline_aligned_in_smp|
+			____cacheline_internodealigned_in_smp|
+			__weak
+		  }x;
+our $Modifier;
+our $Inline	= qr{inline|__always_inline|noinline};
+our $Member	= qr{->$Ident|\.$Ident|\[[^]]*\]};
+our $Lval	= qr{$Ident(?:$Member)*};
+
+our $Int_type	= qr{(?i)llu|ull|ll|lu|ul|l|u};
+our $Binary	= qr{(?i)0b[01]+$Int_type?};
+our $Hex	= qr{(?i)0x[0-9a-f]+$Int_type?};
+our $Int	= qr{[0-9]+$Int_type?};
+our $Float_hex	= qr{(?i)0x[0-9a-f]+p-?[0-9]+[fl]?};
+our $Float_dec	= qr{(?i)(?:[0-9]+\.[0-9]*|[0-9]*\.[0-9]+)(?:e-?[0-9]+)?[fl]?};
+our $Float_int	= qr{(?i)[0-9]+e-?[0-9]+[fl]?};
+our $Float	= qr{$Float_hex|$Float_dec|$Float_int};
+our $Constant	= qr{$Float|$Binary|$Hex|$Int};
+our $Assignment	= qr{\*\=|/=|%=|\+=|-=|<<=|>>=|&=|\^=|\|=|=};
+our $Compare    = qr{<=|>=|==|!=|<|>};
+our $Arithmetic = qr{\+|-|\*|\/|%};
+our $Operators	= qr{
+			<=|>=|==|!=|
+			=>|->|<<|>>|<|>|!|~|
+			&&|\|\||,|\^|\+\+|--|&|\||$Arithmetic
+		  }x;
+
+our $NonptrType;
+our $NonptrTypeWithAttr;
+our $Type;
+our $Declare;
+
+our $NON_ASCII_UTF8	= qr{
+	[\xC2-\xDF][\x80-\xBF]               # non-overlong 2-byte
+	|  \xE0[\xA0-\xBF][\x80-\xBF]        # excluding overlongs
+	| [\xE1-\xEC\xEE\xEF][\x80-\xBF]{2}  # straight 3-byte
+	|  \xED[\x80-\x9F][\x80-\xBF]        # excluding surrogates
+	|  \xF0[\x90-\xBF][\x80-\xBF]{2}     # planes 1-3
+	| [\xF1-\xF3][\x80-\xBF]{3}          # planes 4-15
+	|  \xF4[\x80-\x8F][\x80-\xBF]{2}     # plane 16
+}x;
+
+our $UTF8	= qr{
+	[\x09\x0A\x0D\x20-\x7E]              # ASCII
+	| $NON_ASCII_UTF8
+}x;
+
+our $typeTypedefs = qr{(?x:
+	(?:__)?(?:u|s|be|le)(?:8|16|32|64)|
+	atomic_t
+)};
+
+our $logFunctions = qr{(?x:
+	printk(?:_ratelimited|_once|)|
+	(?:[a-z0-9]+_){1,2}(?:printk|emerg|alert|crit|err|warning|warn|notice|info|debug|dbg|vdbg|devel|cont|WARN)(?:_ratelimited|_once|)|
+	WARN(?:_RATELIMIT|_ONCE|)|
+	panic|
+	debug|
+	printf|
+	puts|
+	MODULE_[A-Z_]+|
+	seq_vprintf|seq_printf|seq_puts
+)};
+
+our $signature_tags = qr{(?xi:
+	Signed-off-by:|
+	Acked-by:|
+	Tested-by:|
+	Reviewed-by:|
+	Reported-by:|
+	Suggested-by:|
+	To:|
+	Cc:
+)};
+
+our @typeList = (
+	qr{void},
+	qr{(?:unsigned\s+)?char},
+	qr{(?:unsigned\s+)?short},
+	qr{(?:unsigned\s+)?int},
+	qr{(?:unsigned\s+)?long},
+	qr{(?:unsigned\s+)?long\s+int},
+	qr{(?:unsigned\s+)?long\s+long},
+	qr{(?:unsigned\s+)?long\s+long\s+int},
+	qr{unsigned},
+	qr{float},
+	qr{double},
+	qr{bool},
+	qr{struct\s+$Ident},
+	qr{union\s+$Ident},
+	qr{enum\s+$Ident},
+	qr{${Ident}_t},
+	qr{${Ident}_handler},
+	qr{${Ident}_handler_fn},
+);
+our @typeListWithAttr = (
+	@typeList,
+	qr{struct\s+$InitAttribute\s+$Ident},
+	qr{union\s+$InitAttribute\s+$Ident},
+);
+
+our @modifierList = (
+	qr{fastcall},
+);
+
+our $allowed_asm_includes = qr{(?x:
+	irq|
+	memory
+)};
+# memory.h: ARM has a custom one
+
+sub build_types {
+	my $mods = "(?x:  \n" . join("|\n  ", @modifierList) . "\n)";
+	my $all = "(?x:  \n" . join("|\n  ", @typeList) . "\n)";
+	my $allWithAttr = "(?x:  \n" . join("|\n  ", @typeListWithAttr) . "\n)";
+	$Modifier	= qr{(?:$Attribute|$Sparse|$mods)};
+	$NonptrType	= qr{
+			(?:$Modifier\s+|const\s+)*
+			(?:
+				(?:typeof|__typeof__)\s*\([^\)]*\)|
+				(?:$typeTypedefs\b)|
+				(?:${all}\b)
+			)
+			(?:\s+$Modifier|\s+const)*
+		  }x;
+	$NonptrTypeWithAttr	= qr{
+			(?:$Modifier\s+|const\s+)*
+			(?:
+				(?:typeof|__typeof__)\s*\([^\)]*\)|
+				(?:$typeTypedefs\b)|
+				(?:${allWithAttr}\b)
+			)
+			(?:\s+$Modifier|\s+const)*
+		  }x;
+	$Type	= qr{
+			$NonptrType
+			(?:(?:\s|\*|\[\])+\s*const|(?:\s|\*|\[\])+|(?:\s*\[\s*\])+)?
+			(?:\s+$Inline|\s+$Modifier)*
+		  }x;
+	$Declare	= qr{(?:$Storage\s+)?$Type};
+}
+build_types();
+
+our $Typecast	= qr{\s*(\(\s*$NonptrType\s*\)){0,1}\s*};
+
+# Using $balanced_parens, $LvalOrFunc, or $FuncArg
+# requires at least perl version v5.10.0
+# Any use must be runtime checked with $^V
+
+our $balanced_parens = qr/(\((?:[^\(\)]++|(?-1))*\))/;
+our $LvalOrFunc	= qr{($Lval)\s*($balanced_parens{0,1})\s*};
+our $FuncArg = qr{$Typecast{0,1}($LvalOrFunc|$Constant)};
+
+sub deparenthesize {
+	my ($string) = @_;
+	return "" if (!defined($string));
+	$string =~ s@^\s*\(\s*@@g;
+	$string =~ s@\s*\)\s*$@@g;
+	$string =~ s@\s+@ @g;
+	return $string;
+}
+
+sub seed_camelcase_file {
+	my ($file) = @_;
+
+	return if (!(-f $file));
+
+	local $/;
+
+	open(my $include_file, '<', "$file")
+	    or warn "$P: Can't read '$file' $!\n";
+	my $text = <$include_file>;
+	close($include_file);
+
+	my @lines = split('\n', $text);
+
+	foreach my $line (@lines) {
+		next if ($line !~ /(?:[A-Z][a-z]|[a-z][A-Z])/);
+		if ($line =~ /^[ \t]*(?:#[ \t]*define|typedef\s+$Type)\s+(\w*(?:[A-Z][a-z]|[a-z][A-Z])\w*)/) {
+			$camelcase{$1} = 1;
+		} elsif ($line =~ /^\s*$Declare\s+(\w*(?:[A-Z][a-z]|[a-z][A-Z])\w*)\s*[\(\[,;]/) {
+			$camelcase{$1} = 1;
+		} elsif ($line =~ /^\s*(?:union|struct|enum)\s+(\w*(?:[A-Z][a-z]|[a-z][A-Z])\w*)\s*[;\{]/) {
+			$camelcase{$1} = 1;
+		}
+	}
+}
+
+my $camelcase_seeded = 0;
+sub seed_camelcase_includes {
+	return if ($camelcase_seeded);
+
+	my $files;
+	my $camelcase_cache = "";
+	my @include_files = ();
+
+	$camelcase_seeded = 1;
+
+	if (-e ".git") {
+		my $git_last_include_commit = `git log --no-merges --pretty=format:"%h%n" -1 -- include`;
+		chomp $git_last_include_commit;
+		$camelcase_cache = ".checkpatch-camelcase.git.$git_last_include_commit";
+	} else {
+		my $last_mod_date = 0;
+		$files = `find $root/include -name "*.h"`;
+		@include_files = split('\n', $files);
+		foreach my $file (@include_files) {
+			my $date = POSIX::strftime("%Y%m%d%H%M",
+						   localtime((stat $file)[9]));
+			$last_mod_date = $date if ($last_mod_date < $date);
+		}
+		$camelcase_cache = ".checkpatch-camelcase.date.$last_mod_date";
+	}
+
+	if ($camelcase_cache ne "" && -f $camelcase_cache) {
+		open(my $camelcase_file, '<', "$camelcase_cache")
+		    or warn "$P: Can't read '$camelcase_cache' $!\n";
+		while (<$camelcase_file>) {
+			chomp;
+			$camelcase{$_} = 1;
+		}
+		close($camelcase_file);
+
+		return;
+	}
+
+	if (-e ".git") {
+		$files = `git ls-files "include/*.h"`;
+		@include_files = split('\n', $files);
+	}
+
+	foreach my $file (@include_files) {
+		seed_camelcase_file($file);
+	}
+
+	if ($camelcase_cache ne "") {
+		unlink glob ".checkpatch-camelcase.*";
+		open(my $camelcase_file, '>', "$camelcase_cache")
+		    or warn "$P: Can't write '$camelcase_cache' $!\n";
+		foreach (sort { lc($a) cmp lc($b) } keys(%camelcase)) {
+			print $camelcase_file ("$_\n");
+		}
+		close($camelcase_file);
+	}
+}
+
+$chk_signoff = 0 if ($file);
+
+my @rawlines = ();
+my @lines = ();
+my @fixed = ();
+my $vname;
+for my $filename (@ARGV) {
+	my $FILE;
+	if ($file) {
+		open($FILE, '-|', "diff -u /dev/null $filename") ||
+			die "$P: $filename: diff failed - $!\n";
+	} elsif ($filename eq '-') {
+		open($FILE, '<&STDIN');
+	} else {
+		open($FILE, '<', "$filename") ||
+			die "$P: $filename: open failed - $!\n";
+	}
+	if ($filename eq '-') {
+		$vname = 'Your patch';
+	} else {
+		$vname = $filename;
+	}
+	while (<$FILE>) {
+		chomp;
+		push(@rawlines, $_);
+	}
+	close($FILE);
+	if (!process($filename)) {
+		$exit = 1;
+	}
+	@rawlines = ();
+	@lines = ();
+	@fixed = ();
+}
+
+exit($exit);
+
+sub top_of_kernel_tree {
+	my ($root) = @_;
+
+	my @tree_check = (
+		"COPYING", "CREDITS", "Kbuild", "MAINTAINERS", "Makefile",
+		"README", "Documentation", "arch", "include", "drivers",
+		"fs", "init", "ipc", "kernel", "lib", "scripts",
+	);
+
+	foreach my $check (@tree_check) {
+		if (! -e $root . '/' . $check) {
+			return 0;
+		}
+	}
+	return 1;
+}
+
+sub parse_email {
+	my ($formatted_email) = @_;
+
+	my $name = "";
+	my $address = "";
+	my $comment = "";
+
+	if ($formatted_email =~ /^(.*)<(\S+\@\S+)>(.*)$/) {
+		$name = $1;
+		$address = $2;
+		$comment = $3 if defined $3;
+	} elsif ($formatted_email =~ /^\s*<(\S+\@\S+)>(.*)$/) {
+		$address = $1;
+		$comment = $2 if defined $2;
+	} elsif ($formatted_email =~ /(\S+\@\S+)(.*)$/) {
+		$address = $1;
+		$comment = $2 if defined $2;
+		$formatted_email =~ s/$address.*$//;
+		$name = $formatted_email;
+		$name = trim($name);
+		$name =~ s/^\"|\"$//g;
+		# If there's a name left after stripping spaces and
+		# leading quotes, and the address doesn't have both
+		# leading and trailing angle brackets, the address
+		# is invalid. ie:
+		#   "joe smith joe@smith.com" bad
+		#   "joe smith <joe@smith.com" bad
+		if ($name ne "" && $address !~ /^<[^>]+>$/) {
+			$name = "";
+			$address = "";
+			$comment = "";
+		}
+	}
+
+	$name = trim($name);
+	$name =~ s/^\"|\"$//g;
+	$address = trim($address);
+	$address =~ s/^\<|\>$//g;
+
+	if ($name =~ /[^\w \-]/i) { ##has "must quote" chars
+		$name =~ s/(?<!\\)"/\\"/g; ##escape quotes
+		$name = "\"$name\"";
+	}
+
+	return ($name, $address, $comment);
+}
+
+sub format_email {
+	my ($name, $address) = @_;
+
+	my $formatted_email;
+
+	$name = trim($name);
+	$name =~ s/^\"|\"$//g;
+	$address = trim($address);
+
+	if ($name =~ /[^\w \-]/i) { ##has "must quote" chars
+		$name =~ s/(?<!\\)"/\\"/g; ##escape quotes
+		$name = "\"$name\"";
+	}
+
+	if ("$name" eq "") {
+		$formatted_email = "$address";
+	} else {
+		$formatted_email = "$name <$address>";
+	}
+
+	return $formatted_email;
+}
+
+sub which_conf {
+	my ($conf) = @_;
+
+	foreach my $path (split(/:/, ".:$ENV{HOME}:.scripts")) {
+		if (-e "$path/$conf") {
+			return "$path/$conf";
+		}
+	}
+
+	return "";
+}
+
+sub expand_tabs {
+	my ($str) = @_;
+
+	my $res = '';
+	my $n = 0;
+	for my $c (split(//, $str)) {
+		if ($c eq "\t") {
+			$res .= ' ';
+			$n++;
+			for (; ($n % 8) != 0; $n++) {
+				$res .= ' ';
+			}
+			next;
+		}
+		$res .= $c;
+		$n++;
+	}
+
+	return $res;
+}
+sub copy_spacing {
+	(my $res = shift) =~ tr/\t/ /c;
+	return $res;
+}
+
+sub line_stats {
+	my ($line) = @_;
+
+	# Drop the diff line leader and expand tabs
+	$line =~ s/^.//;
+	$line = expand_tabs($line);
+
+	# Pick the indent from the front of the line.
+	my ($white) = ($line =~ /^(\s*)/);
+
+	return (length($line), length($white));
+}
+
+my $sanitise_quote = '';
+
+sub sanitise_line_reset {
+	my ($in_comment) = @_;
+
+	if ($in_comment) {
+		$sanitise_quote = '*/';
+	} else {
+		$sanitise_quote = '';
+	}
+}
+sub sanitise_line {
+	my ($line) = @_;
+
+	my $res = '';
+	my $l = '';
+
+	my $qlen = 0;
+	my $off = 0;
+	my $c;
+
+	# Always copy over the diff marker.
+	$res = substr($line, 0, 1);
+
+	for ($off = 1; $off < length($line); $off++) {
+		$c = substr($line, $off, 1);
+
+		# Comments we are wacking completly including the begin
+		# and end, all to $;.
+		if ($sanitise_quote eq '' && substr($line, $off, 2) eq '/*') {
+			$sanitise_quote = '*/';
+
+			substr($res, $off, 2, "$;$;");
+			$off++;
+			next;
+		}
+		if ($sanitise_quote eq '*/' && substr($line, $off, 2) eq '*/') {
+			$sanitise_quote = '';
+			substr($res, $off, 2, "$;$;");
+			$off++;
+			next;
+		}
+		if ($sanitise_quote eq '' && substr($line, $off, 2) eq '//') {
+			$sanitise_quote = '//';
+
+			substr($res, $off, 2, $sanitise_quote);
+			$off++;
+			next;
+		}
+
+		# A \ in a string means ignore the next character.
+		if (($sanitise_quote eq "'" || $sanitise_quote eq '"') &&
+		    $c eq "\\") {
+			substr($res, $off, 2, 'XX');
+			$off++;
+			next;
+		}
+		# Regular quotes.
+		if ($c eq "'" || $c eq '"') {
+			if ($sanitise_quote eq '') {
+				$sanitise_quote = $c;
+
+				substr($res, $off, 1, $c);
+				next;
+			} elsif ($sanitise_quote eq $c) {
+				$sanitise_quote = '';
+			}
+		}
+
+		#print "c<$c> SQ<$sanitise_quote>\n";
+		if ($off != 0 && $sanitise_quote eq '*/' && $c ne "\t") {
+			substr($res, $off, 1, $;);
+		} elsif ($off != 0 && $sanitise_quote eq '//' && $c ne "\t") {
+			substr($res, $off, 1, $;);
+		} elsif ($off != 0 && $sanitise_quote && $c ne "\t") {
+			substr($res, $off, 1, 'X');
+		} else {
+			substr($res, $off, 1, $c);
+		}
+	}
+
+	if ($sanitise_quote eq '//') {
+		$sanitise_quote = '';
+	}
+
+	# The pathname on a #include may be surrounded by '<' and '>'.
+	if ($res =~ /^.\s*\#\s*include\s+\<(.*)\>/) {
+		my $clean = 'X' x length($1);
+		$res =~ s@\<.*\>@<$clean>@;
+
+	# The whole of a #error is a string.
+	} elsif ($res =~ /^.\s*\#\s*(?:error|warning)\s+(.*)\b/) {
+		my $clean = 'X' x length($1);
+		$res =~ s@(\#\s*(?:error|warning)\s+).*@$1$clean@;
+	}
+
+	return $res;
+}
+
+sub get_quoted_string {
+	my ($line, $rawline) = @_;
+
+	return "" if ($line !~ m/(\"[X]+\")/g);
+	return substr($rawline, $-[0], $+[0] - $-[0]);
+}
+
+sub ctx_statement_block {
+	my ($linenr, $remain, $off) = @_;
+	my $line = $linenr - 1;
+	my $blk = '';
+	my $soff = $off;
+	my $coff = $off - 1;
+	my $coff_set = 0;
+
+	my $loff = 0;
+
+	my $type = '';
+	my $level = 0;
+	my @stack = ();
+	my $p;
+	my $c;
+	my $len = 0;
+
+	my $remainder;
+	while (1) {
+		@stack = (['', 0]) if ($#stack == -1);
+
+		#warn "CSB: blk<$blk> remain<$remain>\n";
+		# If we are about to drop off the end, pull in more
+		# context.
+		if ($off >= $len) {
+			for (; $remain > 0; $line++) {
+				last if (!defined $lines[$line]);
+				next if ($lines[$line] =~ /^-/);
+				$remain--;
+				$loff = $len;
+				$blk .= $lines[$line] . "\n";
+				$len = length($blk);
+				$line++;
+				last;
+			}
+			# Bail if there is no further context.
+			#warn "CSB: blk<$blk> off<$off> len<$len>\n";
+			if ($off >= $len) {
+				last;
+			}
+			if ($level == 0 && substr($blk, $off) =~ /^.\s*#\s*define/) {
+				$level++;
+				$type = '#';
+			}
+		}
+		$p = $c;
+		$c = substr($blk, $off, 1);
+		$remainder = substr($blk, $off);
+
+		#warn "CSB: c<$c> type<$type> level<$level> remainder<$remainder> coff_set<$coff_set>\n";
+
+		# Handle nested #if/#else.
+		if ($remainder =~ /^#\s*(?:ifndef|ifdef|if)\s/) {
+			push(@stack, [ $type, $level ]);
+		} elsif ($remainder =~ /^#\s*(?:else|elif)\b/) {
+			($type, $level) = @{$stack[$#stack - 1]};
+		} elsif ($remainder =~ /^#\s*endif\b/) {
+			($type, $level) = @{pop(@stack)};
+		}
+
+		# Statement ends at the ';' or a close '}' at the
+		# outermost level.
+		if ($level == 0 && $c eq ';') {
+			last;
+		}
+
+		# An else is really a conditional as long as its not else if
+		if ($level == 0 && $coff_set == 0 &&
+				(!defined($p) || $p =~ /(?:\s|\}|\+)/) &&
+				$remainder =~ /^(else)(?:\s|{)/ &&
+				$remainder !~ /^else\s+if\b/) {
+			$coff = $off + length($1) - 1;
+			$coff_set = 1;
+			#warn "CSB: mark coff<$coff> soff<$soff> 1<$1>\n";
+			#warn "[" . substr($blk, $soff, $coff - $soff + 1) . "]\n";
+		}
+
+		if (($type eq '' || $type eq '(') && $c eq '(') {
+			$level++;
+			$type = '(';
+		}
+		if ($type eq '(' && $c eq ')') {
+			$level--;
+			$type = ($level != 0)? '(' : '';
+
+			if ($level == 0 && $coff < $soff) {
+				$coff = $off;
+				$coff_set = 1;
+				#warn "CSB: mark coff<$coff>\n";
+			}
+		}
+		if (($type eq '' || $type eq '{') && $c eq '{') {
+			$level++;
+			$type = '{';
+		}
+		if ($type eq '{' && $c eq '}') {
+			$level--;
+			$type = ($level != 0)? '{' : '';
+
+			if ($level == 0) {
+				if (substr($blk, $off + 1, 1) eq ';') {
+					$off++;
+				}
+				last;
+			}
+		}
+		# Preprocessor commands end at the newline unless escaped.
+		if ($type eq '#' && $c eq "\n" && $p ne "\\") {
+			$level--;
+			$type = '';
+			$off++;
+			last;
+		}
+		$off++;
+	}
+	# We are truly at the end, so shuffle to the next line.
+	if ($off == $len) {
+		$loff = $len + 1;
+		$line++;
+		$remain--;
+	}
+
+	my $statement = substr($blk, $soff, $off - $soff + 1);
+	my $condition = substr($blk, $soff, $coff - $soff + 1);
+
+	#warn "STATEMENT<$statement>\n";
+	#warn "CONDITION<$condition>\n";
+
+	#print "coff<$coff> soff<$off> loff<$loff>\n";
+
+	return ($statement, $condition,
+			$line, $remain + 1, $off - $loff + 1, $level);
+}
+
+sub statement_lines {
+	my ($stmt) = @_;
+
+	# Strip the diff line prefixes and rip blank lines at start and end.
+	$stmt =~ s/(^|\n)./$1/g;
+	$stmt =~ s/^\s*//;
+	$stmt =~ s/\s*$//;
+
+	my @stmt_lines = ($stmt =~ /\n/g);
+
+	return $#stmt_lines + 2;
+}
+
+sub statement_rawlines {
+	my ($stmt) = @_;
+
+	my @stmt_lines = ($stmt =~ /\n/g);
+
+	return $#stmt_lines + 2;
+}
+
+sub statement_block_size {
+	my ($stmt) = @_;
+
+	$stmt =~ s/(^|\n)./$1/g;
+	$stmt =~ s/^\s*{//;
+	$stmt =~ s/}\s*$//;
+	$stmt =~ s/^\s*//;
+	$stmt =~ s/\s*$//;
+
+	my @stmt_lines = ($stmt =~ /\n/g);
+	my @stmt_statements = ($stmt =~ /;/g);
+
+	my $stmt_lines = $#stmt_lines + 2;
+	my $stmt_statements = $#stmt_statements + 1;
+
+	if ($stmt_lines > $stmt_statements) {
+		return $stmt_lines;
+	} else {
+		return $stmt_statements;
+	}
+}
+
+sub ctx_statement_full {
+	my ($linenr, $remain, $off) = @_;
+	my ($statement, $condition, $level);
+
+	my (@chunks);
+
+	# Grab the first conditional/block pair.
+	($statement, $condition, $linenr, $remain, $off, $level) =
+				ctx_statement_block($linenr, $remain, $off);
+	#print "F: c<$condition> s<$statement> remain<$remain>\n";
+	push(@chunks, [ $condition, $statement ]);
+	if (!($remain > 0 && $condition =~ /^\s*(?:\n[+-])?\s*(?:if|else|do)\b/s)) {
+		return ($level, $linenr, @chunks);
+	}
+
+	# Pull in the following conditional/block pairs and see if they
+	# could continue the statement.
+	for (;;) {
+		($statement, $condition, $linenr, $remain, $off, $level) =
+				ctx_statement_block($linenr, $remain, $off);
+		#print "C: c<$condition> s<$statement> remain<$remain>\n";
+		last if (!($remain > 0 && $condition =~ /^(?:\s*\n[+-])*\s*(?:else|do)\b/s));
+		#print "C: push\n";
+		push(@chunks, [ $condition, $statement ]);
+	}
+
+	return ($level, $linenr, @chunks);
+}
+
+sub ctx_block_get {
+	my ($linenr, $remain, $outer, $open, $close, $off) = @_;
+	my $line;
+	my $start = $linenr - 1;
+	my $blk = '';
+	my @o;
+	my @c;
+	my @res = ();
+
+	my $level = 0;
+	my @stack = ($level);
+	for ($line = $start; $remain > 0; $line++) {
+		next if ($rawlines[$line] =~ /^-/);
+		$remain--;
+
+		$blk .= $rawlines[$line];
+
+		# Handle nested #if/#else.
+		if ($lines[$line] =~ /^.\s*#\s*(?:ifndef|ifdef|if)\s/) {
+			push(@stack, $level);
+		} elsif ($lines[$line] =~ /^.\s*#\s*(?:else|elif)\b/) {
+			$level = $stack[$#stack - 1];
+		} elsif ($lines[$line] =~ /^.\s*#\s*endif\b/) {
+			$level = pop(@stack);
+		}
+
+		foreach my $c (split(//, $lines[$line])) {
+			##print "C<$c>L<$level><$open$close>O<$off>\n";
+			if ($off > 0) {
+				$off--;
+				next;
+			}
+
+			if ($c eq $close && $level > 0) {
+				$level--;
+				last if ($level == 0);
+			} elsif ($c eq $open) {
+				$level++;
+			}
+		}
+
+		if (!$outer || $level <= 1) {
+			push(@res, $rawlines[$line]);
+		}
+
+		last if ($level == 0);
+	}
+
+	return ($level, @res);
+}
+sub ctx_block_outer {
+	my ($linenr, $remain) = @_;
+
+	my ($level, @r) = ctx_block_get($linenr, $remain, 1, '{', '}', 0);
+	return @r;
+}
+sub ctx_block {
+	my ($linenr, $remain) = @_;
+
+	my ($level, @r) = ctx_block_get($linenr, $remain, 0, '{', '}', 0);
+	return @r;
+}
+sub ctx_statement {
+	my ($linenr, $remain, $off) = @_;
+
+	my ($level, @r) = ctx_block_get($linenr, $remain, 0, '(', ')', $off);
+	return @r;
+}
+sub ctx_block_level {
+	my ($linenr, $remain) = @_;
+
+	return ctx_block_get($linenr, $remain, 0, '{', '}', 0);
+}
+sub ctx_statement_level {
+	my ($linenr, $remain, $off) = @_;
+
+	return ctx_block_get($linenr, $remain, 0, '(', ')', $off);
+}
+
+sub ctx_locate_comment {
+	my ($first_line, $end_line) = @_;
+
+	# Catch a comment on the end of the line itself.
+	my ($current_comment) = ($rawlines[$end_line - 1] =~ m@.*(/\*.*\*/)\s*(?:\\\s*)?$@);
+	return $current_comment if (defined $current_comment);
+
+	# Look through the context and try and figure out if there is a
+	# comment.
+	my $in_comment = 0;
+	$current_comment = '';
+	for (my $linenr = $first_line; $linenr < $end_line; $linenr++) {
+		my $line = $rawlines[$linenr - 1];
+		#warn "           $line\n";
+		if ($linenr == $first_line and $line =~ m@^.\s*\*@) {
+			$in_comment = 1;
+		}
+		if ($line =~ m@/\*@) {
+			$in_comment = 1;
+		}
+		if (!$in_comment && $current_comment ne '') {
+			$current_comment = '';
+		}
+		$current_comment .= $line . "\n" if ($in_comment);
+		if ($line =~ m@\*/@) {
+			$in_comment = 0;
+		}
+	}
+
+	chomp($current_comment);
+	return($current_comment);
+}
+sub ctx_has_comment {
+	my ($first_line, $end_line) = @_;
+	my $cmt = ctx_locate_comment($first_line, $end_line);
+
+	##print "LINE: $rawlines[$end_line - 1 ]\n";
+	##print "CMMT: $cmt\n";
+
+	return ($cmt ne '');
+}
+
+sub raw_line {
+	my ($linenr, $cnt) = @_;
+
+	my $offset = $linenr - 1;
+	$cnt++;
+
+	my $line;
+	while ($cnt) {
+		$line = $rawlines[$offset++];
+		next if (defined($line) && $line =~ /^-/);
+		$cnt--;
+	}
+
+	return $line;
+}
+
+sub cat_vet {
+	my ($vet) = @_;
+	my ($res, $coded);
+
+	$res = '';
+	while ($vet =~ /([^[:cntrl:]]*)([[:cntrl:]]|$)/g) {
+		$res .= $1;
+		if ($2 ne '') {
+			$coded = sprintf("^%c", unpack('C', $2) + 64);
+			$res .= $coded;
+		}
+	}
+	$res =~ s/$/\$/;
+
+	return $res;
+}
+
+my $av_preprocessor = 0;
+my $av_pending;
+my @av_paren_type;
+my $av_pend_colon;
+
+sub annotate_reset {
+	$av_preprocessor = 0;
+	$av_pending = '_';
+	@av_paren_type = ('E');
+	$av_pend_colon = 'O';
+}
+
+sub annotate_values {
+	my ($stream, $type) = @_;
+
+	my $res;
+	my $var = '_' x length($stream);
+	my $cur = $stream;
+
+	print "$stream\n" if ($dbg_values > 1);
+
+	while (length($cur)) {
+		@av_paren_type = ('E') if ($#av_paren_type < 0);
+		print " <" . join('', @av_paren_type) .
+				"> <$type> <$av_pending>" if ($dbg_values > 1);
+		if ($cur =~ /^(\s+)/o) {
+			print "WS($1)\n" if ($dbg_values > 1);
+			if ($1 =~ /\n/ && $av_preprocessor) {
+				$type = pop(@av_paren_type);
+				$av_preprocessor = 0;
+			}
+
+		} elsif ($cur =~ /^(\(\s*$Type\s*)\)/ && $av_pending eq '_') {
+			print "CAST($1)\n" if ($dbg_values > 1);
+			push(@av_paren_type, $type);
+			$type = 'c';
+
+		} elsif ($cur =~ /^($Type)\s*(?:$Ident|,|\)|\(|\s*$)/) {
+			print "DECLARE($1)\n" if ($dbg_values > 1);
+			$type = 'T';
+
+		} elsif ($cur =~ /^($Modifier)\s*/) {
+			print "MODIFIER($1)\n" if ($dbg_values > 1);
+			$type = 'T';
+
+		} elsif ($cur =~ /^(\#\s*define\s*$Ident)(\(?)/o) {
+			print "DEFINE($1,$2)\n" if ($dbg_values > 1);
+			$av_preprocessor = 1;
+			push(@av_paren_type, $type);
+			if ($2 ne '') {
+				$av_pending = 'N';
+			}
+			$type = 'E';
+
+		} elsif ($cur =~ /^(\#\s*(?:undef\s*$Ident|include\b))/o) {
+			print "UNDEF($1)\n" if ($dbg_values > 1);
+			$av_preprocessor = 1;
+			push(@av_paren_type, $type);
+
+		} elsif ($cur =~ /^(\#\s*(?:ifdef|ifndef|if))/o) {
+			print "PRE_START($1)\n" if ($dbg_values > 1);
+			$av_preprocessor = 1;
+
+			push(@av_paren_type, $type);
+			push(@av_paren_type, $type);
+			$type = 'E';
+
+		} elsif ($cur =~ /^(\#\s*(?:else|elif))/o) {
+			print "PRE_RESTART($1)\n" if ($dbg_values > 1);
+			$av_preprocessor = 1;
+
+			push(@av_paren_type, $av_paren_type[$#av_paren_type]);
+
+			$type = 'E';
+
+		} elsif ($cur =~ /^(\#\s*(?:endif))/o) {
+			print "PRE_END($1)\n" if ($dbg_values > 1);
+
+			$av_preprocessor = 1;
+
+			# Assume all arms of the conditional end as this
+			# one does, and continue as if the #endif was not here.
+			pop(@av_paren_type);
+			push(@av_paren_type, $type);
+			$type = 'E';
+
+		} elsif ($cur =~ /^(\\\n)/o) {
+			print "PRECONT($1)\n" if ($dbg_values > 1);
+
+		} elsif ($cur =~ /^(__attribute__)\s*\(?/o) {
+			print "ATTR($1)\n" if ($dbg_values > 1);
+			$av_pending = $type;
+			$type = 'N';
+
+		} elsif ($cur =~ /^(sizeof)\s*(\()?/o) {
+			print "SIZEOF($1)\n" if ($dbg_values > 1);
+			if (defined $2) {
+				$av_pending = 'V';
+			}
+			$type = 'N';
+
+		} elsif ($cur =~ /^(if|while|for)\b/o) {
+			print "COND($1)\n" if ($dbg_values > 1);
+			$av_pending = 'E';
+			$type = 'N';
+
+		} elsif ($cur =~/^(case)/o) {
+			print "CASE($1)\n" if ($dbg_values > 1);
+			$av_pend_colon = 'C';
+			$type = 'N';
+
+		} elsif ($cur =~/^(return|else|goto|typeof|__typeof__)\b/o) {
+			print "KEYWORD($1)\n" if ($dbg_values > 1);
+			$type = 'N';
+
+		} elsif ($cur =~ /^(\()/o) {
+			print "PAREN('$1')\n" if ($dbg_values > 1);
+			push(@av_paren_type, $av_pending);
+			$av_pending = '_';
+			$type = 'N';
+
+		} elsif ($cur =~ /^(\))/o) {
+			my $new_type = pop(@av_paren_type);
+			if ($new_type ne '_') {
+				$type = $new_type;
+				print "PAREN('$1') -> $type\n"
+							if ($dbg_values > 1);
+			} else {
+				print "PAREN('$1')\n" if ($dbg_values > 1);
+			}
+
+		} elsif ($cur =~ /^($Ident)\s*\(/o) {
+			print "FUNC($1)\n" if ($dbg_values > 1);
+			$type = 'V';
+			$av_pending = 'V';
+
+		} elsif ($cur =~ /^($Ident\s*):(?:\s*\d+\s*(,|=|;))?/) {
+			if (defined $2 && $type eq 'C' || $type eq 'T') {
+				$av_pend_colon = 'B';
+			} elsif ($type eq 'E') {
+				$av_pend_colon = 'L';
+			}
+			print "IDENT_COLON($1,$type>$av_pend_colon)\n" if ($dbg_values > 1);
+			$type = 'V';
+
+		} elsif ($cur =~ /^($Ident|$Constant)/o) {
+			print "IDENT($1)\n" if ($dbg_values > 1);
+			$type = 'V';
+
+		} elsif ($cur =~ /^($Assignment)/o) {
+			print "ASSIGN($1)\n" if ($dbg_values > 1);
+			$type = 'N';
+
+		} elsif ($cur =~/^(;|{|})/) {
+			print "END($1)\n" if ($dbg_values > 1);
+			$type = 'E';
+			$av_pend_colon = 'O';
+
+		} elsif ($cur =~/^(,)/) {
+			print "COMMA($1)\n" if ($dbg_values > 1);
+			$type = 'C';
+
+		} elsif ($cur =~ /^(\?)/o) {
+			print "QUESTION($1)\n" if ($dbg_values > 1);
+			$type = 'N';
+
+		} elsif ($cur =~ /^(:)/o) {
+			print "COLON($1,$av_pend_colon)\n" if ($dbg_values > 1);
+
+			substr($var, length($res), 1, $av_pend_colon);
+			if ($av_pend_colon eq 'C' || $av_pend_colon eq 'L') {
+				$type = 'E';
+			} else {
+				$type = 'N';
+			}
+			$av_pend_colon = 'O';
+
+		} elsif ($cur =~ /^(\[)/o) {
+			print "CLOSE($1)\n" if ($dbg_values > 1);
+			$type = 'N';
+
+		} elsif ($cur =~ /^(-(?![->])|\+(?!\+)|\*|\&\&|\&)/o) {
+			my $variant;
+
+			print "OPV($1)\n" if ($dbg_values > 1);
+			if ($type eq 'V') {
+				$variant = 'B';
+			} else {
+				$variant = 'U';
+			}
+
+			substr($var, length($res), 1, $variant);
+			$type = 'N';
+
+		} elsif ($cur =~ /^($Operators)/o) {
+			print "OP($1)\n" if ($dbg_values > 1);
+			if ($1 ne '++' && $1 ne '--') {
+				$type = 'N';
+			}
+
+		} elsif ($cur =~ /(^.)/o) {
+			print "C($1)\n" if ($dbg_values > 1);
+		}
+		if (defined $1) {
+			$cur = substr($cur, length($1));
+			$res .= $type x length($1);
+		}
+	}
+
+	return ($res, $var);
+}
+
+sub possible {
+	my ($possible, $line) = @_;
+	my $notPermitted = qr{(?:
+		^(?:
+			$Modifier|
+			$Storage|
+			$Type|
+			DEFINE_\S+
+		)$|
+		^(?:
+			goto|
+			return|
+			case|
+			else|
+			asm|__asm__|
+			do|
+			\#|
+			\#\#|
+		)(?:\s|$)|
+		^(?:typedef|struct|enum)\b
+	    )}x;
+	warn "CHECK<$possible> ($line)\n" if ($dbg_possible > 2);
+	if ($possible !~ $notPermitted) {
+		# Check for modifiers.
+		$possible =~ s/\s*$Storage\s*//g;
+		$possible =~ s/\s*$Sparse\s*//g;
+		if ($possible =~ /^\s*$/) {
+
+		} elsif ($possible =~ /\s/) {
+			$possible =~ s/\s*$Type\s*//g;
+			for my $modifier (split(' ', $possible)) {
+				if ($modifier !~ $notPermitted) {
+					warn "MODIFIER: $modifier ($possible) ($line)\n" if ($dbg_possible);
+					push(@modifierList, $modifier);
+				}
+			}
+
+		} else {
+			warn "POSSIBLE: $possible ($line)\n" if ($dbg_possible);
+			push(@typeList, $possible);
+		}
+		build_types();
+	} else {
+		warn "NOTPOSS: $possible ($line)\n" if ($dbg_possible > 1);
+	}
+}
+
+my $prefix = '';
+
+sub show_type {
+	return defined $use_type{$_[0]} if (scalar keys %use_type > 0);
+
+	return !defined $ignore_type{$_[0]};
+}
+
+sub report {
+	if (!show_type($_[1]) ||
+	    (defined $tst_only && $_[2] !~ /\Q$tst_only\E/)) {
+		return 0;
+	}
+	my $line;
+	if ($show_types) {
+		$line = "$prefix$_[0]:$_[1]: $_[2]\n";
+	} else {
+		$line = "$prefix$_[0]: $_[2]\n";
+	}
+	$line = (split('\n', $line))[0] . "\n" if ($terse);
+
+	push(our @report, $line);
+
+	return 1;
+}
+sub report_dump {
+	our @report;
+}
+
+sub ERROR {
+	if (report("ERROR", $_[0], $_[1])) {
+		our $clean = 0;
+		our $cnt_error++;
+		return 1;
+	}
+	return 0;
+}
+sub WARN {
+	if (report("WARNING", $_[0], $_[1])) {
+		our $clean = 0;
+		our $cnt_warn++;
+		return 1;
+	}
+	return 0;
+}
+sub CHK {
+	if ($check && report("CHECK", $_[0], $_[1])) {
+		our $clean = 0;
+		our $cnt_chk++;
+		return 1;
+	}
+	return 0;
+}
+
+sub check_absolute_file {
+	my ($absolute, $herecurr) = @_;
+	my $file = $absolute;
+
+	##print "absolute<$absolute>\n";
+
+	# See if any suffix of this path is a path within the tree.
+	while ($file =~ s@^[^/]*/@@) {
+		if (-f "$root/$file") {
+			##print "file<$file>\n";
+			last;
+		}
+	}
+	if (! -f _)  {
+		return 0;
+	}
+
+	# It is, so see if the prefix is acceptable.
+	my $prefix = $absolute;
+	substr($prefix, -length($file)) = '';
+
+	##print "prefix<$prefix>\n";
+	if ($prefix ne ".../") {
+		WARN("USE_RELATIVE_PATH",
+		     "use relative pathname instead of absolute in changelog text\n" . $herecurr);
+	}
+}
+
+sub trim {
+	my ($string) = @_;
+
+	$string =~ s/^\s+|\s+$//g;
+
+	return $string;
+}
+
+sub ltrim {
+	my ($string) = @_;
+
+	$string =~ s/^\s+//;
+
+	return $string;
+}
+
+sub rtrim {
+	my ($string) = @_;
+
+	$string =~ s/\s+$//;
+
+	return $string;
+}
+
+sub string_find_replace {
+	my ($string, $find, $replace) = @_;
+
+	$string =~ s/$find/$replace/g;
+
+	return $string;
+}
+
+sub tabify {
+	my ($leading) = @_;
+
+	my $source_indent = 8;
+	my $max_spaces_before_tab = $source_indent - 1;
+	my $spaces_to_tab = " " x $source_indent;
+
+	#convert leading spaces to tabs
+	1 while $leading =~ s@^([\t]*)$spaces_to_tab@$1\t@g;
+	#Remove spaces before a tab
+	1 while $leading =~ s@^([\t]*)( {1,$max_spaces_before_tab})\t@$1\t@g;
+
+	return "$leading";
+}
+
+sub pos_last_openparen {
+	my ($line) = @_;
+
+	my $pos = 0;
+
+	my $opens = $line =~ tr/\(/\(/;
+	my $closes = $line =~ tr/\)/\)/;
+
+	my $last_openparen = 0;
+
+	if (($opens == 0) || ($closes >= $opens)) {
+		return -1;
+	}
+
+	my $len = length($line);
+
+	for ($pos = 0; $pos < $len; $pos++) {
+		my $string = substr($line, $pos);
+		if ($string =~ /^($FuncArg|$balanced_parens)/) {
+			$pos += length($1) - 1;
+		} elsif (substr($line, $pos, 1) eq '(') {
+			$last_openparen = $pos;
+		} elsif (index($string, '(') == -1) {
+			last;
+		}
+	}
+
+	return $last_openparen + 1;
+}
+
+sub process {
+	my $filename = shift;
+
+	my $linenr=0;
+	my $prevline="";
+	my $prevrawline="";
+	my $stashline="";
+	my $stashrawline="";
+
+	my $length;
+	my $indent;
+	my $previndent=0;
+	my $stashindent=0;
+
+	our $clean = 1;
+	my $signoff = 0;
+	my $is_patch = 0;
+
+	my $in_header_lines = 1;
+	my $in_commit_log = 0;		#Scanning lines before patch
+
+	my $non_utf8_charset = 0;
+
+	our @report = ();
+	our $cnt_lines = 0;
+	our $cnt_error = 0;
+	our $cnt_warn = 0;
+	our $cnt_chk = 0;
+
+	# Trace the real file/line as we go.
+	my $realfile = '';
+	my $realline = 0;
+	my $realcnt = 0;
+	my $here = '';
+	my $in_comment = 0;
+	my $comment_edge = 0;
+	my $first_line = 0;
+	my $p1_prefix = '';
+
+	my $prev_values = 'E';
+
+	# suppression flags
+	my %suppress_ifbraces;
+	my %suppress_whiletrailers;
+	my %suppress_export;
+	my $suppress_statement = 0;
+
+	my %signatures = ();
+
+	# Pre-scan the patch sanitizing the lines.
+	# Pre-scan the patch looking for any __setup documentation.
+	#
+	my @setup_docs = ();
+	my $setup_docs = 0;
+
+	my $camelcase_file_seeded = 0;
+
+	sanitise_line_reset();
+	my $line;
+	foreach my $rawline (@rawlines) {
+		$linenr++;
+		$line = $rawline;
+
+		push(@fixed, $rawline) if ($fix);
+
+		if ($rawline=~/^\+\+\+\s+(\S+)/) {
+			$setup_docs = 0;
+			if ($1 =~ m@Documentation/kernel-parameters.txt$@) {
+				$setup_docs = 1;
+			}
+			#next;
+		}
+		if ($rawline=~/^\@\@ -\d+(?:,\d+)? \+(\d+)(,(\d+))? \@\@/) {
+			$realline=$1-1;
+			if (defined $2) {
+				$realcnt=$3+1;
+			} else {
+				$realcnt=1+1;
+			}
+			$in_comment = 0;
+
+			# Guestimate if this is a continuing comment.  Run
+			# the context looking for a comment "edge".  If this
+			# edge is a close comment then we must be in a comment
+			# at context start.
+			my $edge;
+			my $cnt = $realcnt;
+			for (my $ln = $linenr + 1; $cnt > 0; $ln++) {
+				next if (defined $rawlines[$ln - 1] &&
+					 $rawlines[$ln - 1] =~ /^-/);
+				$cnt--;
+				#print "RAW<$rawlines[$ln - 1]>\n";
+				last if (!defined $rawlines[$ln - 1]);
+				if ($rawlines[$ln - 1] =~ m@(/\*|\*/)@ &&
+				    $rawlines[$ln - 1] !~ m@"[^"]*(?:/\*|\*/)[^"]*"@) {
+					($edge) = $1;
+					last;
+				}
+			}
+			if (defined $edge && $edge eq '*/') {
+				$in_comment = 1;
+			}
+
+			# Guestimate if this is a continuing comment.  If this
+			# is the start of a diff block and this line starts
+			# ' *' then it is very likely a comment.
+			if (!defined $edge &&
+			    $rawlines[$linenr] =~ m@^.\s*(?:\*\*+| \*)(?:\s|$)@)
+			{
+				$in_comment = 1;
+			}
+
+			##print "COMMENT:$in_comment edge<$edge> $rawline\n";
+			sanitise_line_reset($in_comment);
+
+		} elsif ($realcnt && $rawline =~ /^(?:\+| |$)/) {
+			# Standardise the strings and chars within the input to
+			# simplify matching -- only bother with positive lines.
+			$line = sanitise_line($rawline);
+		}
+		push(@lines, $line);
+
+		if ($realcnt > 1) {
+			$realcnt-- if ($line =~ /^(?:\+| |$)/);
+		} else {
+			$realcnt = 0;
+		}
+
+		#print "==>$rawline\n";
+		#print "-->$line\n";
+
+		if ($setup_docs && $line =~ /^\+/) {
+			push(@setup_docs, $line);
+		}
+	}
+
+	$prefix = '';
+
+	$realcnt = 0;
+	$linenr = 0;
+	foreach my $line (@lines) {
+		$linenr++;
+		my $sline = $line;	#copy of $line
+		$sline =~ s/$;/ /g;	#with comments as spaces
+
+		my $rawline = $rawlines[$linenr - 1];
+
+#extract the line range in the file after the patch is applied
+		if ($line=~/^\@\@ -\d+(?:,\d+)? \+(\d+)(,(\d+))? \@\@/) {
+			$is_patch = 1;
+			$first_line = $linenr + 1;
+			$realline=$1-1;
+			if (defined $2) {
+				$realcnt=$3+1;
+			} else {
+				$realcnt=1+1;
+			}
+			annotate_reset();
+			$prev_values = 'E';
+
+			%suppress_ifbraces = ();
+			%suppress_whiletrailers = ();
+			%suppress_export = ();
+			$suppress_statement = 0;
+			next;
+
+# track the line number as we move through the hunk, note that
+# new versions of GNU diff omit the leading space on completely
+# blank context lines so we need to count that too.
+		} elsif ($line =~ /^( |\+|$)/) {
+			$realline++;
+			$realcnt-- if ($realcnt != 0);
+
+			# Measure the line length and indent.
+			($length, $indent) = line_stats($rawline);
+
+			# Track the previous line.
+			($prevline, $stashline) = ($stashline, $line);
+			($previndent, $stashindent) = ($stashindent, $indent);
+			($prevrawline, $stashrawline) = ($stashrawline, $rawline);
+
+			#warn "line<$line>\n";
+
+		} elsif ($realcnt == 1) {
+			$realcnt--;
+		}
+
+		my $hunk_line = ($realcnt != 0);
+
+#make up the handle for any error we report on this line
+		$prefix = "$filename:$realline: " if ($emacs && $file);
+		$prefix = "$filename:$linenr: " if ($emacs && !$file);
+
+		$here = "#$linenr: " if (!$file);
+		$here = "#$realline: " if ($file);
+
+		# extract the filename as it passes
+		if ($line =~ /^diff --git.*?(\S+)$/) {
+			$realfile = $1;
+			$realfile =~ s@^([^/]*)/@@ if (!$file);
+			$in_commit_log = 0;
+		} elsif ($line =~ /^\+\+\+\s+(\S+)/) {
+			$realfile = $1;
+			$realfile =~ s@^([^/]*)/@@ if (!$file);
+			$in_commit_log = 0;
+
+			$p1_prefix = $1;
+			if (!$file && $tree && $p1_prefix ne '' &&
+			    -e "$root/$p1_prefix") {
+				WARN("PATCH_PREFIX",
+				     "patch prefix '$p1_prefix' exists, appears to be a -p0 patch\n");
+			}
+
+			if ($realfile =~ m@^include/asm/@) {
+				ERROR("MODIFIED_INCLUDE_ASM",
+				      "do not modify files in include/asm, change architecture specific files in include/asm-<architecture>\n" . "$here$rawline\n");
+			}
+			next;
+		}
+
+		$here .= "FILE: $realfile:$realline:" if ($realcnt != 0);
+
+		my $hereline = "$here\n$rawline\n";
+		my $herecurr = "$here\n$rawline\n";
+		my $hereprev = "$here\n$prevrawline\n$rawline\n";
+
+		$cnt_lines++ if ($realcnt != 0);
+
+# Check for incorrect file permissions
+		if ($line =~ /^new (file )?mode.*[7531]\d{0,2}$/) {
+			my $permhere = $here . "FILE: $realfile\n";
+			if ($realfile !~ m@scripts/@ &&
+			    $realfile !~ /\.(py|pl|awk|sh)$/) {
+				ERROR("EXECUTE_PERMISSIONS",
+				      "do not set execute permissions for source files\n" . $permhere);
+			}
+		}
+
+# Check the patch for a signoff:
+		if ($line =~ /^\s*signed-off-by:/i) {
+			$signoff++;
+			$in_commit_log = 0;
+		}
+
+# Check signature styles
+		if (!$in_header_lines &&
+		    $line =~ /^(\s*)([a-z0-9_-]+by:|$signature_tags)(\s*)(.*)/i) {
+			my $space_before = $1;
+			my $sign_off = $2;
+			my $space_after = $3;
+			my $email = $4;
+			my $ucfirst_sign_off = ucfirst(lc($sign_off));
+
+			if ($sign_off !~ /$signature_tags/) {
+				WARN("BAD_SIGN_OFF",
+				     "Non-standard signature: $sign_off\n" . $herecurr);
+			}
+			if (defined $space_before && $space_before ne "") {
+				if (WARN("BAD_SIGN_OFF",
+					 "Do not use whitespace before $ucfirst_sign_off\n" . $herecurr) &&
+				    $fix) {
+					$fixed[$linenr - 1] =
+					    "$ucfirst_sign_off $email";
+				}
+			}
+			if ($sign_off =~ /-by:$/i && $sign_off ne $ucfirst_sign_off) {
+				if (WARN("BAD_SIGN_OFF",
+					 "'$ucfirst_sign_off' is the preferred signature form\n" . $herecurr) &&
+				    $fix) {
+					$fixed[$linenr - 1] =
+					    "$ucfirst_sign_off $email";
+				}
+
+			}
+			if (!defined $space_after || $space_after ne " ") {
+				if (WARN("BAD_SIGN_OFF",
+					 "Use a single space after $ucfirst_sign_off\n" . $herecurr) &&
+				    $fix) {
+					$fixed[$linenr - 1] =
+					    "$ucfirst_sign_off $email";
+				}
+			}
+
+			my ($email_name, $email_address, $comment) = parse_email($email);
+			my $suggested_email = format_email(($email_name, $email_address));
+			if ($suggested_email eq "") {
+				ERROR("BAD_SIGN_OFF",
+				      "Unrecognized email address: '$email'\n" . $herecurr);
+			} else {
+				my $dequoted = $suggested_email;
+				$dequoted =~ s/^"//;
+				$dequoted =~ s/" </ </;
+				# Don't force email to have quotes
+				# Allow just an angle bracketed address
+				if ("$dequoted$comment" ne $email &&
+				    "<$email_address>$comment" ne $email &&
+				    "$suggested_email$comment" ne $email) {
+					WARN("BAD_SIGN_OFF",
+					     "email address '$email' might be better as '$suggested_email$comment'\n" . $herecurr);
+				}
+			}
+
+# Check for duplicate signatures
+			my $sig_nospace = $line;
+			$sig_nospace =~ s/\s//g;
+			$sig_nospace = lc($sig_nospace);
+			if (defined $signatures{$sig_nospace}) {
+				WARN("BAD_SIGN_OFF",
+				     "Duplicate signature\n" . $herecurr);
+			} else {
+				$signatures{$sig_nospace} = 1;
+			}
+		}
+
+# Check for wrappage within a valid hunk of the file
+		if ($realcnt != 0 && $line !~ m{^(?:\+|-| |\\ No newline|$)}) {
+			ERROR("CORRUPTED_PATCH",
+			      "patch seems to be corrupt (line wrapped?)\n" .
+				$herecurr) if (!$emitted_corrupt++);
+		}
+
+# Check for absolute kernel paths.
+		if ($tree) {
+			while ($line =~ m{(?:^|\s)(/\S*)}g) {
+				my $file = $1;
+
+				if ($file =~ m{^(.*?)(?::\d+)+:?$} &&
+				    check_absolute_file($1, $herecurr)) {
+					#
+				} else {
+					check_absolute_file($file, $herecurr);
+				}
+			}
+		}
+
+# UTF-8 regex found at http://www.w3.org/International/questions/qa-forms-utf-8.en.php
+		if (($realfile =~ /^$/ || $line =~ /^\+/) &&
+		    $rawline !~ m/^$UTF8*$/) {
+			my ($utf8_prefix) = ($rawline =~ /^($UTF8*)/);
+
+			my $blank = copy_spacing($rawline);
+			my $ptr = substr($blank, 0, length($utf8_prefix)) . "^";
+			my $hereptr = "$hereline$ptr\n";
+
+			CHK("INVALID_UTF8",
+			    "Invalid UTF-8, patch and commit message should be encoded in UTF-8\n" . $hereptr);
+		}
+
+# Check if it's the start of a commit log
+# (not a header line and we haven't seen the patch filename)
+		if ($in_header_lines && $realfile =~ /^$/ &&
+		    $rawline !~ /^(commit\b|from\b|[\w-]+:).+$/i) {
+			$in_header_lines = 0;
+			$in_commit_log = 1;
+		}
+
+# Check if there is UTF-8 in a commit log when a mail header has explicitly
+# declined it, i.e defined some charset where it is missing.
+		if ($in_header_lines &&
+		    $rawline =~ /^Content-Type:.+charset="(.+)".*$/ &&
+		    $1 !~ /utf-8/i) {
+			$non_utf8_charset = 1;
+		}
+
+		if ($in_commit_log && $non_utf8_charset && $realfile =~ /^$/ &&
+		    $rawline =~ /$NON_ASCII_UTF8/) {
+			WARN("UTF8_BEFORE_PATCH",
+			    "8-bit UTF-8 used in possible commit log\n" . $herecurr);
+		}
+
+# ignore non-hunk lines and lines being removed
+		next if (!$hunk_line || $line =~ /^-/);
+
+#trailing whitespace
+		if ($line =~ /^\+.*\015/) {
+			my $herevet = "$here\n" . cat_vet($rawline) . "\n";
+			if (ERROR("DOS_LINE_ENDINGS",
+				  "DOS line endings\n" . $herevet) &&
+			    $fix) {
+				$fixed[$linenr - 1] =~ s/[\s\015]+$//;
+			}
+		} elsif ($rawline =~ /^\+.*\S\s+$/ || $rawline =~ /^\+\s+$/) {
+			my $herevet = "$here\n" . cat_vet($rawline) . "\n";
+			if (ERROR("TRAILING_WHITESPACE",
+				  "trailing whitespace\n" . $herevet) &&
+			    $fix) {
+				$fixed[$linenr - 1] =~ s/\s+$//;
+			}
+
+			$rpt_cleaners = 1;
+		}
+
+# Check for FSF mailing addresses.
+		if ($rawline =~ /\bwrite to the Free/i ||
+		    $rawline =~ /\b59\s+Temple\s+Pl/i ||
+		    $rawline =~ /\b51\s+Franklin\s+St/i) {
+			my $herevet = "$here\n" . cat_vet($rawline) . "\n";
+			my $msg_type = \&ERROR;
+			$msg_type = \&CHK if ($file);
+			&{$msg_type}("FSF_MAILING_ADDRESS",
+				     "Do not include the paragraph about writing to the Free Software Foundation's mailing address from the sample GPL notice. The FSF has changed addresses in the past, and may do so again. Linux already includes a copy of the GPL.\n" . $herevet)
+		}
+
+# check for Kconfig help text having a real description
+# Only applies when adding the entry originally, after that we do not have
+# sufficient context to determine whether it is indeed long enough.
+		if ($realfile =~ /Kconfig/ &&
+		    $line =~ /.\s*config\s+/) {
+			my $length = 0;
+			my $cnt = $realcnt;
+			my $ln = $linenr + 1;
+			my $f;
+			my $is_start = 0;
+			my $is_end = 0;
+			for (; $cnt > 0 && defined $lines[$ln - 1]; $ln++) {
+				$f = $lines[$ln - 1];
+				$cnt-- if ($lines[$ln - 1] !~ /^-/);
+				$is_end = $lines[$ln - 1] =~ /^\+/;
+
+				next if ($f =~ /^-/);
+
+				if ($lines[$ln - 1] =~ /.\s*(?:bool|tristate)\s*\"/) {
+					$is_start = 1;
+				} elsif ($lines[$ln - 1] =~ /.\s*(?:---)?help(?:---)?$/) {
+					$length = -1;
+				}
+
+				$f =~ s/^.//;
+				$f =~ s/#.*//;
+				$f =~ s/^\s+//;
+				next if ($f =~ /^$/);
+				if ($f =~ /^\s*config\s/) {
+					$is_end = 1;
+					last;
+				}
+				$length++;
+			}
+			WARN("CONFIG_DESCRIPTION",
+			     "please write a paragraph that describes the config symbol fully\n" . $herecurr) if ($is_start && $is_end && $length < 4);
+			#print "is_start<$is_start> is_end<$is_end> length<$length>\n";
+		}
+
+# discourage the addition of CONFIG_EXPERIMENTAL in Kconfig.
+		if ($realfile =~ /Kconfig/ &&
+		    $line =~ /.\s*depends on\s+.*\bEXPERIMENTAL\b/) {
+			WARN("CONFIG_EXPERIMENTAL",
+			     "Use of CONFIG_EXPERIMENTAL is deprecated. For alternatives, see https://lkml.org/lkml/2012/10/23/580\n");
+		}
+
+		if (($realfile =~ /Makefile.*/ || $realfile =~ /Kbuild.*/) &&
+		    ($line =~ /\+(EXTRA_[A-Z]+FLAGS).*/)) {
+			my $flag = $1;
+			my $replacement = {
+				'EXTRA_AFLAGS' =>   'asflags-y',
+				'EXTRA_CFLAGS' =>   'ccflags-y',
+				'EXTRA_CPPFLAGS' => 'cppflags-y',
+				'EXTRA_LDFLAGS' =>  'ldflags-y',
+			};
+
+			WARN("DEPRECATED_VARIABLE",
+			     "Use of $flag is deprecated, please use \`$replacement->{$flag} instead.\n" . $herecurr) if ($replacement->{$flag});
+		}
+
+# check for DT compatible documentation
+		if (defined $root && $realfile =~ /\.dts/ &&
+		    $rawline =~ /^\+\s*compatible\s*=/) {
+			my @compats = $rawline =~ /\"([a-zA-Z0-9\-\,\.\+_]+)\"/g;
+
+			foreach my $compat (@compats) {
+				my $compat2 = $compat;
+				my $dt_path =  $root . "/Documentation/devicetree/bindings/";
+				$compat2 =~ s/\,[a-z]*\-/\,<\.\*>\-/;
+				`grep -Erq "$compat|$compat2" $dt_path`;
+				if ( $? >> 8 ) {
+					WARN("UNDOCUMENTED_DT_STRING",
+					     "DT compatible string \"$compat\" appears un-documented -- check $dt_path\n" . $herecurr);
+				}
+
+				my $vendor = $compat;
+				my $vendor_path = $dt_path . "vendor-prefixes.txt";
+				next if (! -f $vendor_path);
+				$vendor =~ s/^([a-zA-Z0-9]+)\,.*/$1/;
+				`grep -Eq "$vendor" $vendor_path`;
+				if ( $? >> 8 ) {
+					WARN("UNDOCUMENTED_DT_STRING",
+					     "DT compatible string vendor \"$vendor\" appears un-documented -- check $vendor_path\n" . $herecurr);
+				}
+			}
+		}
+
+# check we are in a valid source file if not then ignore this hunk
+		next if ($realfile !~ /\.(h|c|s|S|pl|sh)$/);
+
+#line length limit
+		if ($line =~ /^\+/ && $prevrawline !~ /\/\*\*/ &&
+		    $rawline !~ /^.\s*\*\s*\@$Ident\s/ &&
+		    !($line =~ /^\+\s*$logFunctions\s*\(\s*(?:(KERN_\S+\s*|[^"]*))?"[X\t]*"\s*(?:|,|\)\s*;)\s*$/ ||
+		    $line =~ /^\+\s*"[^"]*"\s*(?:\s*|,|\)\s*;)\s*$/) &&
+		    $length > $max_line_length)
+		{
+			WARN("LONG_LINE",
+			     "line over $max_line_length characters\n" . $herecurr);
+		}
+
+# Check for user-visible strings broken across lines, which breaks the ability
+# to grep for the string.  Make exceptions when the previous string ends in a
+# newline (multiple lines in one string constant) or '\t', '\r', ';', or '{'
+# (common in inline assembly) or is a octal \123 or hexadecimal \xaf value
+		if ($line =~ /^\+\s*"/ &&
+		    $prevline =~ /"\s*$/ &&
+		    $prevrawline !~ /(?:\\(?:[ntr]|[0-7]{1,3}|x[0-9a-fA-F]{1,2})|;\s*|\{\s*)"\s*$/) {
+			WARN("SPLIT_STRING",
+			     "quoted string split across lines\n" . $hereprev);
+		}
+
+# check for spaces before a quoted newline
+		if ($rawline =~ /^.*\".*\s\\n/) {
+			if (WARN("QUOTED_WHITESPACE_BEFORE_NEWLINE",
+				 "unnecessary whitespace before a quoted newline\n" . $herecurr) &&
+			    $fix) {
+				$fixed[$linenr - 1] =~ s/^(\+.*\".*)\s+\\n/$1\\n/;
+			}
+
+		}
+
+# check for adding lines without a newline.
+		if ($line =~ /^\+/ && defined $lines[$linenr] && $lines[$linenr] =~ /^\\ No newline at end of file/) {
+			WARN("MISSING_EOF_NEWLINE",
+			     "adding a line without newline at end of file\n" . $herecurr);
+		}
+
+# Blackfin: use hi/lo macros
+		if ($realfile =~ m@arch/blackfin/.*\.S$@) {
+			if ($line =~ /\.[lL][[:space:]]*=.*&[[:space:]]*0x[fF][fF][fF][fF]/) {
+				my $herevet = "$here\n" . cat_vet($line) . "\n";
+				ERROR("LO_MACRO",
+				      "use the LO() macro, not (... & 0xFFFF)\n" . $herevet);
+			}
+			if ($line =~ /\.[hH][[:space:]]*=.*>>[[:space:]]*16/) {
+				my $herevet = "$here\n" . cat_vet($line) . "\n";
+				ERROR("HI_MACRO",
+				      "use the HI() macro, not (... >> 16)\n" . $herevet);
+			}
+		}
+
+# check we are in a valid source file C or perl if not then ignore this hunk
+		next if ($realfile !~ /\.(h|c|pl)$/);
+
+# at the beginning of a line any tabs must come first and anything
+# more than 8 must use tabs.
+		if ($rawline =~ /^\+\s* \t\s*\S/ ||
+		    $rawline =~ /^\+\s*        \s*/) {
+			my $herevet = "$here\n" . cat_vet($rawline) . "\n";
+			$rpt_cleaners = 1;
+			if (ERROR("CODE_INDENT",
+				  "code indent should use tabs where possible\n" . $herevet) &&
+			    $fix) {
+				$fixed[$linenr - 1] =~ s/^\+([ \t]+)/"\+" . tabify($1)/e;
+			}
+		}
+
+# check for space before tabs.
+		if ($rawline =~ /^\+/ && $rawline =~ / \t/) {
+			my $herevet = "$here\n" . cat_vet($rawline) . "\n";
+			if (WARN("SPACE_BEFORE_TAB",
+				"please, no space before tabs\n" . $herevet) &&
+			    $fix) {
+				while ($fixed[$linenr - 1] =~
+					   s/(^\+.*) {8,8}+\t/$1\t\t/) {}
+				while ($fixed[$linenr - 1] =~
+					   s/(^\+.*) +\t/$1\t/) {}
+			}
+		}
+
+# check for && or || at the start of a line
+		if ($rawline =~ /^\+\s*(&&|\|\|)/) {
+			CHK("LOGICAL_CONTINUATIONS",
+			    "Logical continuations should be on the previous line\n" . $hereprev);
+		}
+
+# check multi-line statement indentation matches previous line
+		if ($^V && $^V ge 5.10.0 &&
+		    $prevline =~ /^\+(\t*)(if \(|$Ident\().*(\&\&|\|\||,)\s*$/) {
+			$prevline =~ /^\+(\t*)(.*)$/;
+			my $oldindent = $1;
+			my $rest = $2;
+
+			my $pos = pos_last_openparen($rest);
+			if ($pos >= 0) {
+				$line =~ /^(\+| )([ \t]*)/;
+				my $newindent = $2;
+
+				my $goodtabindent = $oldindent .
+					"\t" x ($pos / 8) .
+					" "  x ($pos % 8);
+				my $goodspaceindent = $oldindent . " "  x $pos;
+
+				if ($newindent ne $goodtabindent &&
+				    $newindent ne $goodspaceindent) {
+
+					if (CHK("PARENTHESIS_ALIGNMENT",
+						"Alignment should match open parenthesis\n" . $hereprev) &&
+					    $fix && $line =~ /^\+/) {
+						$fixed[$linenr - 1] =~
+						    s/^\+[ \t]*/\+$goodtabindent/;
+					}
+				}
+			}
+		}
+
+		if ($line =~ /^\+.*\*[ \t]*\)[ \t]+(?!$Assignment|$Arithmetic)/) {
+			if (CHK("SPACING",
+				"No space is necessary after a cast\n" . $hereprev) &&
+			    $fix) {
+				$fixed[$linenr - 1] =~
+				    s/^(\+.*\*[ \t]*\))[ \t]+/$1/;
+			}
+		}
+
+		if ($realfile =~ m@^(drivers/net/|net/)@ &&
+		    $prevrawline =~ /^\+[ \t]*\/\*[ \t]*$/ &&
+		    $rawline =~ /^\+[ \t]*\*/) {
+			WARN("NETWORKING_BLOCK_COMMENT_STYLE",
+			     "networking block comments don't use an empty /* line, use /* Comment...\n" . $hereprev);
+		}
+
+		if ($realfile =~ m@^(drivers/net/|net/)@ &&
+		    $prevrawline =~ /^\+[ \t]*\/\*/ &&		#starting /*
+		    $prevrawline !~ /\*\/[ \t]*$/ &&		#no trailing */
+		    $rawline =~ /^\+/ &&			#line is new
+		    $rawline !~ /^\+[ \t]*\*/) {		#no leading *
+			WARN("NETWORKING_BLOCK_COMMENT_STYLE",
+			     "networking block comments start with * on subsequent lines\n" . $hereprev);
+		}
+
+		if ($realfile =~ m@^(drivers/net/|net/)@ &&
+		    $rawline !~ m@^\+[ \t]*\*/[ \t]*$@ &&	#trailing */
+		    $rawline !~ m@^\+.*/\*.*\*/[ \t]*$@ &&	#inline /*...*/
+		    $rawline !~ m@^\+.*\*{2,}/[ \t]*$@ &&	#trailing **/
+		    $rawline =~ m@^\+[ \t]*.+\*\/[ \t]*$@) {	#non blank */
+			WARN("NETWORKING_BLOCK_COMMENT_STYLE",
+			     "networking block comments put the trailing */ on a separate line\n" . $herecurr);
+		}
+
+# check for spaces at the beginning of a line.
+# Exceptions:
+#  1) within comments
+#  2) indented preprocessor commands
+#  3) hanging labels
+		if ($rawline =~ /^\+ / && $line !~ /^\+ *(?:$;|#|$Ident:)/)  {
+			my $herevet = "$here\n" . cat_vet($rawline) . "\n";
+			if (WARN("LEADING_SPACE",
+				 "please, no spaces at the start of a line\n" . $herevet) &&
+			    $fix) {
+				$fixed[$linenr - 1] =~ s/^\+([ \t]+)/"\+" . tabify($1)/e;
+			}
+		}
+
+# check we are in a valid C source file if not then ignore this hunk
+		next if ($realfile !~ /\.(h|c)$/);
+
+# discourage the addition of CONFIG_EXPERIMENTAL in #if(def).
+		if ($line =~ /^\+\s*\#\s*if.*\bCONFIG_EXPERIMENTAL\b/) {
+			WARN("CONFIG_EXPERIMENTAL",
+			     "Use of CONFIG_EXPERIMENTAL is deprecated. For alternatives, see https://lkml.org/lkml/2012/10/23/580\n");
+		}
+
+# check for RCS/CVS revision markers
+		if ($rawline =~ /^\+.*\$(Revision|Log|Id)(?:\$|)/) {
+			WARN("CVS_KEYWORD",
+			     "CVS style keyword markers, these will _not_ be updated\n". $herecurr);
+		}
+
+# Blackfin: don't use __builtin_bfin_[cs]sync
+		if ($line =~ /__builtin_bfin_csync/) {
+			my $herevet = "$here\n" . cat_vet($line) . "\n";
+			ERROR("CSYNC",
+			      "use the CSYNC() macro in asm/blackfin.h\n" . $herevet);
+		}
+		if ($line =~ /__builtin_bfin_ssync/) {
+			my $herevet = "$here\n" . cat_vet($line) . "\n";
+			ERROR("SSYNC",
+			      "use the SSYNC() macro in asm/blackfin.h\n" . $herevet);
+		}
+
+# check for old HOTPLUG __dev<foo> section markings
+		if ($line =~ /\b(__dev(init|exit)(data|const|))\b/) {
+			WARN("HOTPLUG_SECTION",
+			     "Using $1 is unnecessary\n" . $herecurr);
+		}
+
+# Check for potential 'bare' types
+		my ($stat, $cond, $line_nr_next, $remain_next, $off_next,
+		    $realline_next);
+#print "LINE<$line>\n";
+		if ($linenr >= $suppress_statement &&
+		    $realcnt && $sline =~ /.\s*\S/) {
+			($stat, $cond, $line_nr_next, $remain_next, $off_next) =
+				ctx_statement_block($linenr, $realcnt, 0);
+			$stat =~ s/\n./\n /g;
+			$cond =~ s/\n./\n /g;
+
+#print "linenr<$linenr> <$stat>\n";
+			# If this statement has no statement boundaries within
+			# it there is no point in retrying a statement scan
+			# until we hit end of it.
+			my $frag = $stat; $frag =~ s/;+\s*$//;
+			if ($frag !~ /(?:{|;)/) {
+#print "skip<$line_nr_next>\n";
+				$suppress_statement = $line_nr_next;
+			}
+
+			# Find the real next line.
+			$realline_next = $line_nr_next;
+			if (defined $realline_next &&
+			    (!defined $lines[$realline_next - 1] ||
+			     substr($lines[$realline_next - 1], $off_next) =~ /^\s*$/)) {
+				$realline_next++;
+			}
+
+			my $s = $stat;
+			$s =~ s/{.*$//s;
+
+			# Ignore goto labels.
+			if ($s =~ /$Ident:\*$/s) {
+
+			# Ignore functions being called
+			} elsif ($s =~ /^.\s*$Ident\s*\(/s) {
+
+			} elsif ($s =~ /^.\s*else\b/s) {
+
+			# declarations always start with types
+			} elsif ($prev_values eq 'E' && $s =~ /^.\s*(?:$Storage\s+)?(?:$Inline\s+)?(?:const\s+)?((?:\s*$Ident)+?)\b(?:\s+$Sparse)?\s*\**\s*(?:$Ident|\(\*[^\)]*\))(?:\s*$Modifier)?\s*(?:;|=|,|\()/s) {
+				my $type = $1;
+				$type =~ s/\s+/ /g;
+				possible($type, "A:" . $s);
+
+			# definitions in global scope can only start with types
+			} elsif ($s =~ /^.(?:$Storage\s+)?(?:$Inline\s+)?(?:const\s+)?($Ident)\b\s*(?!:)/s) {
+				possible($1, "B:" . $s);
+			}
+
+			# any (foo ... *) is a pointer cast, and foo is a type
+			while ($s =~ /\(($Ident)(?:\s+$Sparse)*[\s\*]+\s*\)/sg) {
+				possible($1, "C:" . $s);
+			}
+
+			# Check for any sort of function declaration.
+			# int foo(something bar, other baz);
+			# void (*store_gdt)(x86_descr_ptr *);
+			if ($prev_values eq 'E' && $s =~ /^(.(?:typedef\s*)?(?:(?:$Storage|$Inline)\s*)*\s*$Type\s*(?:\b$Ident|\(\*\s*$Ident\))\s*)\(/s) {
+				my ($name_len) = length($1);
+
+				my $ctx = $s;
+				substr($ctx, 0, $name_len + 1, '');
+				$ctx =~ s/\)[^\)]*$//;
+
+				for my $arg (split(/\s*,\s*/, $ctx)) {
+					if ($arg =~ /^(?:const\s+)?($Ident)(?:\s+$Sparse)*\s*\**\s*(:?\b$Ident)?$/s || $arg =~ /^($Ident)$/s) {
+
+						possible($1, "D:" . $s);
+					}
+				}
+			}
+
+		}
+
+#
+# Checks which may be anchored in the context.
+#
+
+# Check for switch () and associated case and default
+# statements should be at the same indent.
+		if ($line=~/\bswitch\s*\(.*\)/) {
+			my $err = '';
+			my $sep = '';
+			my @ctx = ctx_block_outer($linenr, $realcnt);
+			shift(@ctx);
+			for my $ctx (@ctx) {
+				my ($clen, $cindent) = line_stats($ctx);
+				if ($ctx =~ /^\+\s*(case\s+|default:)/ &&
+							$indent != $cindent) {
+					$err .= "$sep$ctx\n";
+					$sep = '';
+				} else {
+					$sep = "[...]\n";
+				}
+			}
+			if ($err ne '') {
+				ERROR("SWITCH_CASE_INDENT_LEVEL",
+				      "switch and case should be at the same indent\n$hereline$err");
+			}
+		}
+
+# if/while/etc brace do not go on next line, unless defining a do while loop,
+# or if that brace on the next line is for something else
+		if ($line =~ /(.*)\b((?:if|while|for|switch)\s*\(|do\b|else\b)/ && $line !~ /^.\s*\#/) {
+			my $pre_ctx = "$1$2";
+
+			my ($level, @ctx) = ctx_statement_level($linenr, $realcnt, 0);
+
+			if ($line =~ /^\+\t{6,}/) {
+				WARN("DEEP_INDENTATION",
+				     "Too many leading tabs - consider code refactoring\n" . $herecurr);
+			}
+
+			my $ctx_cnt = $realcnt - $#ctx - 1;
+			my $ctx = join("\n", @ctx);
+
+			my $ctx_ln = $linenr;
+			my $ctx_skip = $realcnt;
+
+			while ($ctx_skip > $ctx_cnt || ($ctx_skip == $ctx_cnt &&
+					defined $lines[$ctx_ln - 1] &&
+					$lines[$ctx_ln - 1] =~ /^-/)) {
+				##print "SKIP<$ctx_skip> CNT<$ctx_cnt>\n";
+				$ctx_skip-- if (!defined $lines[$ctx_ln - 1] || $lines[$ctx_ln - 1] !~ /^-/);
+				$ctx_ln++;
+			}
+
+			#print "realcnt<$realcnt> ctx_cnt<$ctx_cnt>\n";
+			#print "pre<$pre_ctx>\nline<$line>\nctx<$ctx>\nnext<$lines[$ctx_ln - 1]>\n";
+
+			if ($ctx !~ /{\s*/ && defined($lines[$ctx_ln -1]) && $lines[$ctx_ln - 1] =~ /^\+\s*{/) {
+				ERROR("OPEN_BRACE",
+				      "that open brace { should be on the previous line\n" .
+					"$here\n$ctx\n$rawlines[$ctx_ln - 1]\n");
+			}
+			if ($level == 0 && $pre_ctx !~ /}\s*while\s*\($/ &&
+			    $ctx =~ /\)\s*\;\s*$/ &&
+			    defined $lines[$ctx_ln - 1])
+			{
+				my ($nlength, $nindent) = line_stats($lines[$ctx_ln - 1]);
+				if ($nindent > $indent) {
+					WARN("TRAILING_SEMICOLON",
+					     "trailing semicolon indicates no statements, indent implies otherwise\n" .
+						"$here\n$ctx\n$rawlines[$ctx_ln - 1]\n");
+				}
+			}
+		}
+
+# Check relative indent for conditionals and blocks.
+		if ($line =~ /\b(?:(?:if|while|for)\s*\(|do\b)/ && $line !~ /^.\s*#/ && $line !~ /\}\s*while\s*/) {
+			($stat, $cond, $line_nr_next, $remain_next, $off_next) =
+				ctx_statement_block($linenr, $realcnt, 0)
+					if (!defined $stat);
+			my ($s, $c) = ($stat, $cond);
+
+			substr($s, 0, length($c), '');
+
+			# Make sure we remove the line prefixes as we have
+			# none on the first line, and are going to readd them
+			# where necessary.
+			$s =~ s/\n./\n/gs;
+
+			# Find out how long the conditional actually is.
+			my @newlines = ($c =~ /\n/gs);
+			my $cond_lines = 1 + $#newlines;
+
+			# We want to check the first line inside the block
+			# starting at the end of the conditional, so remove:
+			#  1) any blank line termination
+			#  2) any opening brace { on end of the line
+			#  3) any do (...) {
+			my $continuation = 0;
+			my $check = 0;
+			$s =~ s/^.*\bdo\b//;
+			$s =~ s/^\s*{//;
+			if ($s =~ s/^\s*\\//) {
+				$continuation = 1;
+			}
+			if ($s =~ s/^\s*?\n//) {
+				$check = 1;
+				$cond_lines++;
+			}
+
+			# Also ignore a loop construct at the end of a
+			# preprocessor statement.
+			if (($prevline =~ /^.\s*#\s*define\s/ ||
+			    $prevline =~ /\\\s*$/) && $continuation == 0) {
+				$check = 0;
+			}
+
+			my $cond_ptr = -1;
+			$continuation = 0;
+			while ($cond_ptr != $cond_lines) {
+				$cond_ptr = $cond_lines;
+
+				# If we see an #else/#elif then the code
+				# is not linear.
+				if ($s =~ /^\s*\#\s*(?:else|elif)/) {
+					$check = 0;
+				}
+
+				# Ignore:
+				#  1) blank lines, they should be at 0,
+				#  2) preprocessor lines, and
+				#  3) labels.
+				if ($continuation ||
+				    $s =~ /^\s*?\n/ ||
+				    $s =~ /^\s*#\s*?/ ||
+				    $s =~ /^\s*$Ident\s*:/) {
+					$continuation = ($s =~ /^.*?\\\n/) ? 1 : 0;
+					if ($s =~ s/^.*?\n//) {
+						$cond_lines++;
+					}
+				}
+			}
+
+			my (undef, $sindent) = line_stats("+" . $s);
+			my $stat_real = raw_line($linenr, $cond_lines);
+
+			# Check if either of these lines are modified, else
+			# this is not this patch's fault.
+			if (!defined($stat_real) ||
+			    $stat !~ /^\+/ && $stat_real !~ /^\+/) {
+				$check = 0;
+			}
+			if (defined($stat_real) && $cond_lines > 1) {
+				$stat_real = "[...]\n$stat_real";
+			}
+
+			#print "line<$line> prevline<$prevline> indent<$indent> sindent<$sindent> check<$check> continuation<$continuation> s<$s> cond_lines<$cond_lines> stat_real<$stat_real> stat<$stat>\n";
+
+			if ($check && (($sindent % 8) != 0 ||
+			    ($sindent <= $indent && $s ne ''))) {
+				WARN("SUSPECT_CODE_INDENT",
+				     "suspect code indent for conditional statements ($indent, $sindent)\n" . $herecurr . "$stat_real\n");
+			}
+		}
+
+		# Track the 'values' across context and added lines.
+		my $opline = $line; $opline =~ s/^./ /;
+		my ($curr_values, $curr_vars) =
+				annotate_values($opline . "\n", $prev_values);
+		$curr_values = $prev_values . $curr_values;
+		if ($dbg_values) {
+			my $outline = $opline; $outline =~ s/\t/ /g;
+			print "$linenr > .$outline\n";
+			print "$linenr > $curr_values\n";
+			print "$linenr >  $curr_vars\n";
+		}
+		$prev_values = substr($curr_values, -1);
+
+#ignore lines not being added
+		next if ($line =~ /^[^\+]/);
+
+# TEST: allow direct testing of the type matcher.
+		if ($dbg_type) {
+			if ($line =~ /^.\s*$Declare\s*$/) {
+				ERROR("TEST_TYPE",
+				      "TEST: is type\n" . $herecurr);
+			} elsif ($dbg_type > 1 && $line =~ /^.+($Declare)/) {
+				ERROR("TEST_NOT_TYPE",
+				      "TEST: is not type ($1 is)\n". $herecurr);
+			}
+			next;
+		}
+# TEST: allow direct testing of the attribute matcher.
+		if ($dbg_attr) {
+			if ($line =~ /^.\s*$Modifier\s*$/) {
+				ERROR("TEST_ATTR",
+				      "TEST: is attr\n" . $herecurr);
+			} elsif ($dbg_attr > 1 && $line =~ /^.+($Modifier)/) {
+				ERROR("TEST_NOT_ATTR",
+				      "TEST: is not attr ($1 is)\n". $herecurr);
+			}
+			next;
+		}
+
+# check for initialisation to aggregates open brace on the next line
+		if ($line =~ /^.\s*{/ &&
+		    $prevline =~ /(?:^|[^=])=\s*$/) {
+			ERROR("OPEN_BRACE",
+			      "that open brace { should be on the previous line\n" . $hereprev);
+		}
+
+#
+# Checks which are anchored on the added line.
+#
+
+# check for malformed paths in #include statements (uses RAW line)
+		if ($rawline =~ m{^.\s*\#\s*include\s+[<"](.*)[">]}) {
+			my $path = $1;
+			if ($path =~ m{//}) {
+				ERROR("MALFORMED_INCLUDE",
+				      "malformed #include filename\n" . $herecurr);
+			}
+			if ($path =~ "^uapi/" && $realfile =~ m@\binclude/uapi/@) {
+				ERROR("UAPI_INCLUDE",
+				      "No #include in ...include/uapi/... should use a uapi/ path prefix\n" . $herecurr);
+			}
+		}
+
+# no C99 // comments
+		if ($line =~ m{//}) {
+			if (ERROR("C99_COMMENTS",
+				  "do not use C99 // comments\n" . $herecurr) &&
+			    $fix) {
+				my $line = $fixed[$linenr - 1];
+				if ($line =~ /\/\/(.*)$/) {
+					my $comment = trim($1);
+					$fixed[$linenr - 1] =~ s@\/\/(.*)$@/\* $comment \*/@;
+				}
+			}
+		}
+		# Remove C99 comments.
+		$line =~ s@//.*@@;
+		$opline =~ s@//.*@@;
+
+# EXPORT_SYMBOL should immediately follow the thing it is exporting, consider
+# the whole statement.
+#print "APW <$lines[$realline_next - 1]>\n";
+		if (defined $realline_next &&
+		    exists $lines[$realline_next - 1] &&
+		    !defined $suppress_export{$realline_next} &&
+		    ($lines[$realline_next - 1] =~ /EXPORT_SYMBOL.*\((.*)\)/ ||
+		     $lines[$realline_next - 1] =~ /EXPORT_UNUSED_SYMBOL.*\((.*)\)/)) {
+			# Handle definitions which produce identifiers with
+			# a prefix:
+			#   XXX(foo);
+			#   EXPORT_SYMBOL(something_foo);
+			my $name = $1;
+			if ($stat =~ /^(?:.\s*}\s*\n)?.([A-Z_]+)\s*\(\s*($Ident)/ &&
+			    $name =~ /^${Ident}_$2/) {
+#print "FOO C name<$name>\n";
+				$suppress_export{$realline_next} = 1;
+
+			} elsif ($stat !~ /(?:
+				\n.}\s*$|
+				^.DEFINE_$Ident\(\Q$name\E\)|
+				^.DECLARE_$Ident\(\Q$name\E\)|
+				^.LIST_HEAD\(\Q$name\E\)|
+				^.(?:$Storage\s+)?$Type\s*\(\s*\*\s*\Q$name\E\s*\)\s*\(|
+				\b\Q$name\E(?:\s+$Attribute)*\s*(?:;|=|\[|\()
+			    )/x) {
+#print "FOO A<$lines[$realline_next - 1]> stat<$stat> name<$name>\n";
+				$suppress_export{$realline_next} = 2;
+			} else {
+				$suppress_export{$realline_next} = 1;
+			}
+		}
+		if (!defined $suppress_export{$linenr} &&
+		    $prevline =~ /^.\s*$/ &&
+		    ($line =~ /EXPORT_SYMBOL.*\((.*)\)/ ||
+		     $line =~ /EXPORT_UNUSED_SYMBOL.*\((.*)\)/)) {
+#print "FOO B <$lines[$linenr - 1]>\n";
+			$suppress_export{$linenr} = 2;
+		}
+		if (defined $suppress_export{$linenr} &&
+		    $suppress_export{$linenr} == 2) {
+			WARN("EXPORT_SYMBOL",
+			     "EXPORT_SYMBOL(foo); should immediately follow its function/variable\n" . $herecurr);
+		}
+
+# check for global initialisers.
+		if ($line =~ /^\+(\s*$Type\s*$Ident\s*(?:\s+$Modifier))*\s*=\s*(0|NULL|false)\s*;/) {
+			if (ERROR("GLOBAL_INITIALISERS",
+				  "do not initialise globals to 0 or NULL\n" .
+				      $herecurr) &&
+			    $fix) {
+				$fixed[$linenr - 1] =~ s/($Type\s*$Ident\s*(?:\s+$Modifier))*\s*=\s*(0|NULL|false)\s*;/$1;/;
+			}
+		}
+# check for static initialisers.
+		if ($line =~ /^\+.*\bstatic\s.*=\s*(0|NULL|false)\s*;/) {
+			if (ERROR("INITIALISED_STATIC",
+				  "do not initialise statics to 0 or NULL\n" .
+				      $herecurr) &&
+			    $fix) {
+				$fixed[$linenr - 1] =~ s/(\bstatic\s.*?)\s*=\s*(0|NULL|false)\s*;/$1;/;
+			}
+		}
+
+# check for static const char * arrays.
+		if ($line =~ /\bstatic\s+const\s+char\s*\*\s*(\w+)\s*\[\s*\]\s*=\s*/) {
+			WARN("STATIC_CONST_CHAR_ARRAY",
+			     "static const char * array should probably be static const char * const\n" .
+				$herecurr);
+               }
+
+# check for static char foo[] = "bar" declarations.
+		if ($line =~ /\bstatic\s+char\s+(\w+)\s*\[\s*\]\s*=\s*"/) {
+			WARN("STATIC_CONST_CHAR_ARRAY",
+			     "static char array declaration should probably be static const char\n" .
+				$herecurr);
+               }
+
+# check for function declarations without arguments like "int foo()"
+		if ($line =~ /(\b$Type\s+$Ident)\s*\(\s*\)/) {
+			if (ERROR("FUNCTION_WITHOUT_ARGS",
+				  "Bad function definition - $1() should probably be $1(void)\n" . $herecurr) &&
+			    $fix) {
+				$fixed[$linenr - 1] =~ s/(\b($Type)\s+($Ident))\s*\(\s*\)/$2 $3(void)/;
+			}
+		}
+
+# check for uses of DEFINE_PCI_DEVICE_TABLE
+		if ($line =~ /\bDEFINE_PCI_DEVICE_TABLE\s*\(\s*(\w+)\s*\)\s*=/) {
+			if (WARN("DEFINE_PCI_DEVICE_TABLE",
+				 "Prefer struct pci_device_id over deprecated DEFINE_PCI_DEVICE_TABLE\n" . $herecurr) &&
+			    $fix) {
+				$fixed[$linenr - 1] =~ s/\b(?:static\s+|)DEFINE_PCI_DEVICE_TABLE\s*\(\s*(\w+)\s*\)\s*=\s*/static const struct pci_device_id $1\[\] = /;
+			}
+		}
+
+# check for new typedefs, only function parameters and sparse annotations
+# make sense.
+		if ($line =~ /\btypedef\s/ &&
+		    $line !~ /\btypedef\s+$Type\s*\(\s*\*?$Ident\s*\)\s*\(/ &&
+		    $line !~ /\btypedef\s+$Type\s+$Ident\s*\(/ &&
+		    $line !~ /\b$typeTypedefs\b/ &&
+		    $line !~ /\b__bitwise(?:__|)\b/) {
+			WARN("NEW_TYPEDEFS",
+			     "do not add new typedefs\n" . $herecurr);
+		}
+
+# * goes on variable not on type
+		# (char*[ const])
+		while ($line =~ m{(\($NonptrType(\s*(?:$Modifier\b\s*|\*\s*)+)\))}g) {
+			#print "AA<$1>\n";
+			my ($ident, $from, $to) = ($1, $2, $2);
+
+			# Should start with a space.
+			$to =~ s/^(\S)/ $1/;
+			# Should not end with a space.
+			$to =~ s/\s+$//;
+			# '*'s should not have spaces between.
+			while ($to =~ s/\*\s+\*/\*\*/) {
+			}
+
+##			print "1: from<$from> to<$to> ident<$ident>\n";
+			if ($from ne $to) {
+				if (ERROR("POINTER_LOCATION",
+					  "\"(foo$from)\" should be \"(foo$to)\"\n" .  $herecurr) &&
+				    $fix) {
+					my $sub_from = $ident;
+					my $sub_to = $ident;
+					$sub_to =~ s/\Q$from\E/$to/;
+					$fixed[$linenr - 1] =~
+					    s@\Q$sub_from\E@$sub_to@;
+				}
+			}
+		}
+		while ($line =~ m{(\b$NonptrType(\s*(?:$Modifier\b\s*|\*\s*)+)($Ident))}g) {
+			#print "BB<$1>\n";
+			my ($match, $from, $to, $ident) = ($1, $2, $2, $3);
+
+			# Should start with a space.
+			$to =~ s/^(\S)/ $1/;
+			# Should not end with a space.
+			$to =~ s/\s+$//;
+			# '*'s should not have spaces between.
+			while ($to =~ s/\*\s+\*/\*\*/) {
+			}
+			# Modifiers should have spaces.
+			$to =~ s/(\b$Modifier$)/$1 /;
+
+##			print "2: from<$from> to<$to> ident<$ident>\n";
+			if ($from ne $to && $ident !~ /^$Modifier$/) {
+				if (ERROR("POINTER_LOCATION",
+					  "\"foo${from}bar\" should be \"foo${to}bar\"\n" .  $herecurr) &&
+				    $fix) {
+
+					my $sub_from = $match;
+					my $sub_to = $match;
+					$sub_to =~ s/\Q$from\E/$to/;
+					$fixed[$linenr - 1] =~
+					    s@\Q$sub_from\E@$sub_to@;
+				}
+			}
+		}
+
+# # no BUG() or BUG_ON()
+# 		if ($line =~ /\b(BUG|BUG_ON)\b/) {
+# 			print "Try to use WARN_ON & Recovery code rather than BUG() or BUG_ON()\n";
+# 			print "$herecurr";
+# 			$clean = 0;
+# 		}
+
+		if ($line =~ /\bLINUX_VERSION_CODE\b/) {
+			WARN("LINUX_VERSION_CODE",
+			     "LINUX_VERSION_CODE should be avoided, code should be for the version to which it is merged\n" . $herecurr);
+		}
+
+# check for uses of printk_ratelimit
+		if ($line =~ /\bprintk_ratelimit\s*\(/) {
+			WARN("PRINTK_RATELIMITED",
+"Prefer printk_ratelimited or pr_<level>_ratelimited to printk_ratelimit\n" . $herecurr);
+		}
+
+# printk should use KERN_* levels.  Note that follow on printk's on the
+# same line do not need a level, so we use the current block context
+# to try and find and validate the current printk.  In summary the current
+# printk includes all preceding printk's which have no newline on the end.
+# we assume the first bad printk is the one to report.
+		if ($line =~ /\bprintk\((?!KERN_)\s*"/) {
+			my $ok = 0;
+			for (my $ln = $linenr - 1; $ln >= $first_line; $ln--) {
+				#print "CHECK<$lines[$ln - 1]\n";
+				# we have a preceding printk if it ends
+				# with "\n" ignore it, else it is to blame
+				if ($lines[$ln - 1] =~ m{\bprintk\(}) {
+					if ($rawlines[$ln - 1] !~ m{\\n"}) {
+						$ok = 1;
+					}
+					last;
+				}
+			}
+			if ($ok == 0) {
+				WARN("PRINTK_WITHOUT_KERN_LEVEL",
+				     "printk() should include KERN_ facility level\n" . $herecurr);
+			}
+		}
+
+		if ($line =~ /\bprintk\s*\(\s*KERN_([A-Z]+)/) {
+			my $orig = $1;
+			my $level = lc($orig);
+			$level = "warn" if ($level eq "warning");
+			my $level2 = $level;
+			$level2 = "dbg" if ($level eq "debug");
+			WARN("PREFER_PR_LEVEL",
+			     "Prefer netdev_$level2(netdev, ... then dev_$level2(dev, ... then pr_$level(...  to printk(KERN_$orig ...\n" . $herecurr);
+		}
+
+		if ($line =~ /\bpr_warning\s*\(/) {
+			if (WARN("PREFER_PR_LEVEL",
+				 "Prefer pr_warn(... to pr_warning(...\n" . $herecurr) &&
+			    $fix) {
+				$fixed[$linenr - 1] =~
+				    s/\bpr_warning\b/pr_warn/;
+			}
+		}
+
+		if ($line =~ /\bdev_printk\s*\(\s*KERN_([A-Z]+)/) {
+			my $orig = $1;
+			my $level = lc($orig);
+			$level = "warn" if ($level eq "warning");
+			$level = "dbg" if ($level eq "debug");
+			WARN("PREFER_DEV_LEVEL",
+			     "Prefer dev_$level(... to dev_printk(KERN_$orig, ...\n" . $herecurr);
+		}
+
+# function brace can't be on same line, except for #defines of do while,
+# or if closed on same line
+		if (($line=~/$Type\s*$Ident\(.*\).*\s{/) and
+		    !($line=~/\#\s*define.*do\s{/) and !($line=~/}/)) {
+			ERROR("OPEN_BRACE",
+			      "open brace '{' following function declarations go on the next line\n" . $herecurr);
+		}
+
+# open braces for enum, union and struct go on the same line.
+		if ($line =~ /^.\s*{/ &&
+		    $prevline =~ /^.\s*(?:typedef\s+)?(enum|union|struct)(?:\s+$Ident)?\s*$/) {
+			ERROR("OPEN_BRACE",
+			      "open brace '{' following $1 go on the same line\n" . $hereprev);
+		}
+
+# missing space after union, struct or enum definition
+		if ($line =~ /^.\s*(?:typedef\s+)?(enum|union|struct)(?:\s+$Ident){1,2}[=\{]/) {
+			if (WARN("SPACING",
+				 "missing space after $1 definition\n" . $herecurr) &&
+			    $fix) {
+				$fixed[$linenr - 1] =~
+				    s/^(.\s*(?:typedef\s+)?(?:enum|union|struct)(?:\s+$Ident){1,2})([=\{])/$1 $2/;
+			}
+		}
+
+# Function pointer declarations
+# check spacing between type, funcptr, and args
+# canonical declaration is "type (*funcptr)(args...)"
+#
+# the $Declare variable will capture all spaces after the type
+# so check it for trailing missing spaces or multiple spaces
+		if ($line =~ /^.\s*($Declare)\((\s*)\*(\s*)$Ident(\s*)\)(\s*)\(/) {
+			my $declare = $1;
+			my $pre_pointer_space = $2;
+			my $post_pointer_space = $3;
+			my $funcname = $4;
+			my $post_funcname_space = $5;
+			my $pre_args_space = $6;
+
+			if ($declare !~ /\s$/) {
+				WARN("SPACING",
+				     "missing space after return type\n" . $herecurr);
+			}
+
+# unnecessary space "type  (*funcptr)(args...)"
+			elsif ($declare =~ /\s{2,}$/) {
+				WARN("SPACING",
+				     "Multiple spaces after return type\n" . $herecurr);
+			}
+
+# unnecessary space "type ( *funcptr)(args...)"
+			if (defined $pre_pointer_space &&
+			    $pre_pointer_space =~ /^\s/) {
+				WARN("SPACING",
+				     "Unnecessary space after function pointer open parenthesis\n" . $herecurr);
+			}
+
+# unnecessary space "type (* funcptr)(args...)"
+			if (defined $post_pointer_space &&
+			    $post_pointer_space =~ /^\s/) {
+				WARN("SPACING",
+				     "Unnecessary space before function pointer name\n" . $herecurr);
+			}
+
+# unnecessary space "type (*funcptr )(args...)"
+			if (defined $post_funcname_space &&
+			    $post_funcname_space =~ /^\s/) {
+				WARN("SPACING",
+				     "Unnecessary space after function pointer name\n" . $herecurr);
+			}
+
+# unnecessary space "type (*funcptr) (args...)"
+			if (defined $pre_args_space &&
+			    $pre_args_space =~ /^\s/) {
+				WARN("SPACING",
+				     "Unnecessary space before function pointer arguments\n" . $herecurr);
+			}
+
+			if (show_type("SPACING") && $fix) {
+				$fixed[$linenr - 1] =~
+				    s/^(.\s*$Declare)\(\s*\*\s*($Ident)\s*\)\s*\(/rtrim($1) . " " . "\(\*$2\)\("/ex;
+			}
+		}
+
+# check for spacing round square brackets; allowed:
+#  1. with a type on the left -- int [] a;
+#  2. at the beginning of a line for slice initialisers -- [0...10] = 5,
+#  3. inside a curly brace -- = { [0...10] = 5 }
+		while ($line =~ /(.*?\s)\[/g) {
+			my ($where, $prefix) = ($-[1], $1);
+			if ($prefix !~ /$Type\s+$/ &&
+			    ($where != 0 || $prefix !~ /^.\s+$/) &&
+			    $prefix !~ /[{,]\s+$/) {
+				if (ERROR("BRACKET_SPACE",
+					  "space prohibited before open square bracket '['\n" . $herecurr) &&
+				    $fix) {
+				    $fixed[$linenr - 1] =~
+					s/^(\+.*?)\s+\[/$1\[/;
+				}
+			}
+		}
+
+# check for spaces between functions and their parentheses.
+		while ($line =~ /($Ident)\s+\(/g) {
+			my $name = $1;
+			my $ctx_before = substr($line, 0, $-[1]);
+			my $ctx = "$ctx_before$name";
+
+			# Ignore those directives where spaces _are_ permitted.
+			if ($name =~ /^(?:
+				if|for|while|switch|return|case|
+				volatile|__volatile__|
+				__attribute__|format|__extension__|
+				asm|__asm__)$/x)
+			{
+			# cpp #define statements have non-optional spaces, ie
+			# if there is a space between the name and the open
+			# parenthesis it is simply not a parameter group.
+			} elsif ($ctx_before =~ /^.\s*\#\s*define\s*$/) {
+
+			# cpp #elif statement condition may start with a (
+			} elsif ($ctx =~ /^.\s*\#\s*elif\s*$/) {
+
+			# If this whole things ends with a type its most
+			# likely a typedef for a function.
+			} elsif ($ctx =~ /$Type$/) {
+
+			} else {
+				if (WARN("SPACING",
+					 "space prohibited between function name and open parenthesis '('\n" . $herecurr) &&
+					     $fix) {
+					$fixed[$linenr - 1] =~
+					    s/\b$name\s+\(/$name\(/;
+				}
+			}
+		}
+
+# Check operator spacing.
+		if (!($line=~/\#\s*include/)) {
+			my $fixed_line = "";
+			my $line_fixed = 0;
+
+			my $ops = qr{
+				<<=|>>=|<=|>=|==|!=|
+				\+=|-=|\*=|\/=|%=|\^=|\|=|&=|
+				=>|->|<<|>>|<|>|=|!|~|
+				&&|\|\||,|\^|\+\+|--|&|\||\+|-|\*|\/|%|
+				\?:|\?|:
+			}x;
+			my @elements = split(/($ops|;)/, $opline);
+
+##			print("element count: <" . $#elements . ">\n");
+##			foreach my $el (@elements) {
+##				print("el: <$el>\n");
+##			}
+
+			my @fix_elements = ();
+			my $off = 0;
+
+			foreach my $el (@elements) {
+				push(@fix_elements, substr($rawline, $off, length($el)));
+				$off += length($el);
+			}
+
+			$off = 0;
+
+			my $blank = copy_spacing($opline);
+			my $last_after = -1;
+
+			for (my $n = 0; $n < $#elements; $n += 2) {
+
+				my $good = $fix_elements[$n] . $fix_elements[$n + 1];
+
+##				print("n: <$n> good: <$good>\n");
+
+				$off += length($elements[$n]);
+
+				# Pick up the preceding and succeeding characters.
+				my $ca = substr($opline, 0, $off);
+				my $cc = '';
+				if (length($opline) >= ($off + length($elements[$n + 1]))) {
+					$cc = substr($opline, $off + length($elements[$n + 1]));
+				}
+				my $cb = "$ca$;$cc";
+
+				my $a = '';
+				$a = 'V' if ($elements[$n] ne '');
+				$a = 'W' if ($elements[$n] =~ /\s$/);
+				$a = 'C' if ($elements[$n] =~ /$;$/);
+				$a = 'B' if ($elements[$n] =~ /(\[|\()$/);
+				$a = 'O' if ($elements[$n] eq '');
+				$a = 'E' if ($ca =~ /^\s*$/);
+
+				my $op = $elements[$n + 1];
+
+				my $c = '';
+				if (defined $elements[$n + 2]) {
+					$c = 'V' if ($elements[$n + 2] ne '');
+					$c = 'W' if ($elements[$n + 2] =~ /^\s/);
+					$c = 'C' if ($elements[$n + 2] =~ /^$;/);
+					$c = 'B' if ($elements[$n + 2] =~ /^(\)|\]|;)/);
+					$c = 'O' if ($elements[$n + 2] eq '');
+					$c = 'E' if ($elements[$n + 2] =~ /^\s*\\$/);
+				} else {
+					$c = 'E';
+				}
+
+				my $ctx = "${a}x${c}";
+
+				my $at = "(ctx:$ctx)";
+
+				my $ptr = substr($blank, 0, $off) . "^";
+				my $hereptr = "$hereline$ptr\n";
+
+				# Pull out the value of this operator.
+				my $op_type = substr($curr_values, $off + 1, 1);
+
+				# Get the full operator variant.
+				my $opv = $op . substr($curr_vars, $off, 1);
+
+				# Ignore operators passed as parameters.
+				if ($op_type ne 'V' &&
+				    $ca =~ /\s$/ && $cc =~ /^\s*,/) {
+
+#				# Ignore comments
+#				} elsif ($op =~ /^$;+$/) {
+
+				# ; should have either the end of line or a space or \ after it
+				} elsif ($op eq ';') {
+					if ($ctx !~ /.x[WEBC]/ &&
+					    $cc !~ /^\\/ && $cc !~ /^;/) {
+						if (ERROR("SPACING",
+							  "space required after that '$op' $at\n" . $hereptr)) {
+							$good = $fix_elements[$n] . trim($fix_elements[$n + 1]) . " ";
+							$line_fixed = 1;
+						}
+					}
+
+				# // is a comment
+				} elsif ($op eq '//') {
+
+				# No spaces for:
+				#   ->
+				#   :   when part of a bitfield
+				} elsif ($op eq '->' || $opv eq ':B') {
+					if ($ctx =~ /Wx.|.xW/) {
+						if (ERROR("SPACING",
+							  "spaces prohibited around that '$op' $at\n" . $hereptr)) {
+							$good = rtrim($fix_elements[$n]) . trim($fix_elements[$n + 1]);
+							if (defined $fix_elements[$n + 2]) {
+								$fix_elements[$n + 2] =~ s/^\s+//;
+							}
+							$line_fixed = 1;
+						}
+					}
+
+				# , must have a space on the right.
+				} elsif ($op eq ',') {
+					if ($ctx !~ /.x[WEC]/ && $cc !~ /^}/) {
+						if (ERROR("SPACING",
+							  "space required after that '$op' $at\n" . $hereptr)) {
+							$good = $fix_elements[$n] . trim($fix_elements[$n + 1]) . " ";
+							$line_fixed = 1;
+							$last_after = $n;
+						}
+					}
+
+				# '*' as part of a type definition -- reported already.
+				} elsif ($opv eq '*_') {
+					#warn "'*' is part of type\n";
+
+				# unary operators should have a space before and
+				# none after.  May be left adjacent to another
+				# unary operator, or a cast
+				} elsif ($op eq '!' || $op eq '~' ||
+					 $opv eq '*U' || $opv eq '-U' ||
+					 $opv eq '&U' || $opv eq '&&U') {
+					if ($ctx !~ /[WEBC]x./ && $ca !~ /(?:\)|!|~|\*|-|\&|\||\+\+|\-\-|\{)$/) {
+						if (ERROR("SPACING",
+							  "space required before that '$op' $at\n" . $hereptr)) {
+							if ($n != $last_after + 2) {
+								$good = $fix_elements[$n] . " " . ltrim($fix_elements[$n + 1]);
+								$line_fixed = 1;
+							}
+						}
+					}
+					if ($op eq '*' && $cc =~/\s*$Modifier\b/) {
+						# A unary '*' may be const
+
+					} elsif ($ctx =~ /.xW/) {
+						if (ERROR("SPACING",
+							  "space prohibited after that '$op' $at\n" . $hereptr)) {
+							$good = $fix_elements[$n] . rtrim($fix_elements[$n + 1]);
+							if (defined $fix_elements[$n + 2]) {
+								$fix_elements[$n + 2] =~ s/^\s+//;
+							}
+							$line_fixed = 1;
+						}
+					}
+
+				# unary ++ and unary -- are allowed no space on one side.
+				} elsif ($op eq '++' or $op eq '--') {
+					if ($ctx !~ /[WEOBC]x[^W]/ && $ctx !~ /[^W]x[WOBEC]/) {
+						if (ERROR("SPACING",
+							  "space required one side of that '$op' $at\n" . $hereptr)) {
+							$good = $fix_elements[$n] . trim($fix_elements[$n + 1]) . " ";
+							$line_fixed = 1;
+						}
+					}
+					if ($ctx =~ /Wx[BE]/ ||
+					    ($ctx =~ /Wx./ && $cc =~ /^;/)) {
+						if (ERROR("SPACING",
+							  "space prohibited before that '$op' $at\n" . $hereptr)) {
+							$good = rtrim($fix_elements[$n]) . trim($fix_elements[$n + 1]);
+							$line_fixed = 1;
+						}
+					}
+					if ($ctx =~ /ExW/) {
+						if (ERROR("SPACING",
+							  "space prohibited after that '$op' $at\n" . $hereptr)) {
+							$good = $fix_elements[$n] . trim($fix_elements[$n + 1]);
+							if (defined $fix_elements[$n + 2]) {
+								$fix_elements[$n + 2] =~ s/^\s+//;
+							}
+							$line_fixed = 1;
+						}
+					}
+
+				# << and >> may either have or not have spaces both sides
+				} elsif ($op eq '<<' or $op eq '>>' or
+					 $op eq '&' or $op eq '^' or $op eq '|' or
+					 $op eq '+' or $op eq '-' or
+					 $op eq '*' or $op eq '/' or
+					 $op eq '%')
+				{
+					if ($ctx =~ /Wx[^WCE]|[^WCE]xW/) {
+						if (ERROR("SPACING",
+							  "need consistent spacing around '$op' $at\n" . $hereptr)) {
+							$good = rtrim($fix_elements[$n]) . " " . trim($fix_elements[$n + 1]) . " ";
+							if (defined $fix_elements[$n + 2]) {
+								$fix_elements[$n + 2] =~ s/^\s+//;
+							}
+							$line_fixed = 1;
+						}
+					}
+
+				# A colon needs no spaces before when it is
+				# terminating a case value or a label.
+				} elsif ($opv eq ':C' || $opv eq ':L') {
+					if ($ctx =~ /Wx./) {
+						if (ERROR("SPACING",
+							  "space prohibited before that '$op' $at\n" . $hereptr)) {
+							$good = rtrim($fix_elements[$n]) . trim($fix_elements[$n + 1]);
+							$line_fixed = 1;
+						}
+					}
+
+				# All the others need spaces both sides.
+				} elsif ($ctx !~ /[EWC]x[CWE]/) {
+					my $ok = 0;
+
+					# Ignore email addresses <foo@bar>
+					if (($op eq '<' &&
+					     $cc =~ /^\S+\@\S+>/) ||
+					    ($op eq '>' &&
+					     $ca =~ /<\S+\@\S+$/))
+					{
+					    	$ok = 1;
+					}
+
+					# messages are ERROR, but ?: are CHK
+					if ($ok == 0) {
+						my $msg_type = \&ERROR;
+						$msg_type = \&CHK if (($op eq '?:' || $op eq '?' || $op eq ':') && $ctx =~ /VxV/);
+
+						if (&{$msg_type}("SPACING",
+								 "spaces required around that '$op' $at\n" . $hereptr)) {
+							$good = rtrim($fix_elements[$n]) . " " . trim($fix_elements[$n + 1]) . " ";
+							if (defined $fix_elements[$n + 2]) {
+								$fix_elements[$n + 2] =~ s/^\s+//;
+							}
+							$line_fixed = 1;
+						}
+					}
+				}
+				$off += length($elements[$n + 1]);
+
+##				print("n: <$n> GOOD: <$good>\n");
+
+				$fixed_line = $fixed_line . $good;
+			}
+
+			if (($#elements % 2) == 0) {
+				$fixed_line = $fixed_line . $fix_elements[$#elements];
+			}
+
+			if ($fix && $line_fixed && $fixed_line ne $fixed[$linenr - 1]) {
+				$fixed[$linenr - 1] = $fixed_line;
+			}
+
+
+		}
+
+# check for whitespace before a non-naked semicolon
+		if ($line =~ /^\+.*\S\s+;\s*$/) {
+			if (WARN("SPACING",
+				 "space prohibited before semicolon\n" . $herecurr) &&
+			    $fix) {
+				1 while $fixed[$linenr - 1] =~
+				    s/^(\+.*\S)\s+;/$1;/;
+			}
+		}
+
+# check for multiple assignments
+		if ($line =~ /^.\s*$Lval\s*=\s*$Lval\s*=(?!=)/) {
+			CHK("MULTIPLE_ASSIGNMENTS",
+			    "multiple assignments should be avoided\n" . $herecurr);
+		}
+
+## # check for multiple declarations, allowing for a function declaration
+## # continuation.
+## 		if ($line =~ /^.\s*$Type\s+$Ident(?:\s*=[^,{]*)?\s*,\s*$Ident.*/ &&
+## 		    $line !~ /^.\s*$Type\s+$Ident(?:\s*=[^,{]*)?\s*,\s*$Type\s*$Ident.*/) {
+##
+## 			# Remove any bracketed sections to ensure we do not
+## 			# falsly report the parameters of functions.
+## 			my $ln = $line;
+## 			while ($ln =~ s/\([^\(\)]*\)//g) {
+## 			}
+## 			if ($ln =~ /,/) {
+## 				WARN("MULTIPLE_DECLARATION",
+##				     "declaring multiple variables together should be avoided\n" . $herecurr);
+## 			}
+## 		}
+
+#need space before brace following if, while, etc
+		if (($line =~ /\(.*\){/ && $line !~ /\($Type\){/) ||
+		    $line =~ /do{/) {
+			if (ERROR("SPACING",
+				  "space required before the open brace '{'\n" . $herecurr) &&
+			    $fix) {
+				$fixed[$linenr - 1] =~ s/^(\+.*(?:do|\))){/$1 {/;
+			}
+		}
+
+## # check for blank lines before declarations
+##		if ($line =~ /^.\t+$Type\s+$Ident(?:\s*=.*)?;/ &&
+##		    $prevrawline =~ /^.\s*$/) {
+##			WARN("SPACING",
+##			     "No blank lines before declarations\n" . $hereprev);
+##		}
+##
+
+# closing brace should have a space following it when it has anything
+# on the line
+		if ($line =~ /}(?!(?:,|;|\)))\S/) {
+			if (ERROR("SPACING",
+				  "space required after that close brace '}'\n" . $herecurr) &&
+			    $fix) {
+				$fixed[$linenr - 1] =~
+				    s/}((?!(?:,|;|\)))\S)/} $1/;
+			}
+		}
+
+# check spacing on square brackets
+		if ($line =~ /\[\s/ && $line !~ /\[\s*$/) {
+			if (ERROR("SPACING",
+				  "space prohibited after that open square bracket '['\n" . $herecurr) &&
+			    $fix) {
+				$fixed[$linenr - 1] =~
+				    s/\[\s+/\[/;
+			}
+		}
+		if ($line =~ /\s\]/) {
+			if (ERROR("SPACING",
+				  "space prohibited before that close square bracket ']'\n" . $herecurr) &&
+			    $fix) {
+				$fixed[$linenr - 1] =~
+				    s/\s+\]/\]/;
+			}
+		}
+
+# check spacing on parentheses
+		if ($line =~ /\(\s/ && $line !~ /\(\s*(?:\\)?$/ &&
+		    $line !~ /for\s*\(\s+;/) {
+			if (ERROR("SPACING",
+				  "space prohibited after that open parenthesis '('\n" . $herecurr) &&
+			    $fix) {
+				$fixed[$linenr - 1] =~
+				    s/\(\s+/\(/;
+			}
+		}
+		if ($line =~ /(\s+)\)/ && $line !~ /^.\s*\)/ &&
+		    $line !~ /for\s*\(.*;\s+\)/ &&
+		    $line !~ /:\s+\)/) {
+			if (ERROR("SPACING",
+				  "space prohibited before that close parenthesis ')'\n" . $herecurr) &&
+			    $fix) {
+				$fixed[$linenr - 1] =~
+				    s/\s+\)/\)/;
+			}
+		}
+
+#goto labels aren't indented, allow a single space however
+		if ($line=~/^.\s+[A-Za-z\d_]+:(?![0-9]+)/ and
+		   !($line=~/^. [A-Za-z\d_]+:/) and !($line=~/^.\s+default:/)) {
+			if (WARN("INDENTED_LABEL",
+				 "labels should not be indented\n" . $herecurr) &&
+			    $fix) {
+				$fixed[$linenr - 1] =~
+				    s/^(.)\s+/$1/;
+			}
+		}
+
+# Return is not a function.
+		if (defined($stat) && $stat =~ /^.\s*return(\s*)\(/s) {
+			my $spacing = $1;
+			if ($^V && $^V ge 5.10.0 &&
+			    $stat =~ /^.\s*return\s*$balanced_parens\s*;\s*$/) {
+				ERROR("RETURN_PARENTHESES",
+				      "return is not a function, parentheses are not required\n" . $herecurr);
+
+			} elsif ($spacing !~ /\s+/) {
+				ERROR("SPACING",
+				      "space required before the open parenthesis '('\n" . $herecurr);
+			}
+		}
+
+# if statements using unnecessary parentheses - ie: if ((foo == bar))
+		if ($^V && $^V ge 5.10.0 &&
+		    $line =~ /\bif\s*((?:\(\s*){2,})/) {
+			my $openparens = $1;
+			my $count = $openparens =~ tr@\(@\(@;
+			my $msg = "";
+			if ($line =~ /\bif\s*(?:\(\s*){$count,$count}$LvalOrFunc\s*($Compare)\s*$LvalOrFunc(?:\s*\)){$count,$count}/) {
+				my $comp = $4;	#Not $1 because of $LvalOrFunc
+				$msg = " - maybe == should be = ?" if ($comp eq "==");
+				WARN("UNNECESSARY_PARENTHESES",
+				     "Unnecessary parentheses$msg\n" . $herecurr);
+			}
+		}
+
+# Return of what appears to be an errno should normally be -'ve
+		if ($line =~ /^.\s*return\s*(E[A-Z]*)\s*;/) {
+			my $name = $1;
+			if ($name ne 'EOF' && $name ne 'ERROR') {
+				WARN("USE_NEGATIVE_ERRNO",
+				     "return of an errno should typically be -ve (return -$1)\n" . $herecurr);
+			}
+		}
+
+# Need a space before open parenthesis after if, while etc
+		if ($line =~ /\b(if|while|for|switch)\(/) {
+			if (ERROR("SPACING",
+				  "space required before the open parenthesis '('\n" . $herecurr) &&
+			    $fix) {
+				$fixed[$linenr - 1] =~
+				    s/\b(if|while|for|switch)\(/$1 \(/;
+			}
+		}
+
+# Check for illegal assignment in if conditional -- and check for trailing
+# statements after the conditional.
+		if ($line =~ /do\s*(?!{)/) {
+			($stat, $cond, $line_nr_next, $remain_next, $off_next) =
+				ctx_statement_block($linenr, $realcnt, 0)
+					if (!defined $stat);
+			my ($stat_next) = ctx_statement_block($line_nr_next,
+						$remain_next, $off_next);
+			$stat_next =~ s/\n./\n /g;
+			##print "stat<$stat> stat_next<$stat_next>\n";
+
+			if ($stat_next =~ /^\s*while\b/) {
+				# If the statement carries leading newlines,
+				# then count those as offsets.
+				my ($whitespace) =
+					($stat_next =~ /^((?:\s*\n[+-])*\s*)/s);
+				my $offset =
+					statement_rawlines($whitespace) - 1;
+
+				$suppress_whiletrailers{$line_nr_next +
+								$offset} = 1;
+			}
+		}
+		if (!defined $suppress_whiletrailers{$linenr} &&
+		    defined($stat) && defined($cond) &&
+		    $line =~ /\b(?:if|while|for)\s*\(/ && $line !~ /^.\s*#/) {
+			my ($s, $c) = ($stat, $cond);
+
+			if ($c =~ /\bif\s*\(.*[^<>!=]=[^=].*/s) {
+				ERROR("ASSIGN_IN_IF",
+				      "do not use assignment in if condition\n" . $herecurr);
+			}
+
+			# Find out what is on the end of the line after the
+			# conditional.
+			substr($s, 0, length($c), '');
+			$s =~ s/\n.*//g;
+			$s =~ s/$;//g; 	# Remove any comments
+			if (length($c) && $s !~ /^\s*{?\s*\\*\s*$/ &&
+			    $c !~ /}\s*while\s*/)
+			{
+				# Find out how long the conditional actually is.
+				my @newlines = ($c =~ /\n/gs);
+				my $cond_lines = 1 + $#newlines;
+				my $stat_real = '';
+
+				$stat_real = raw_line($linenr, $cond_lines)
+							. "\n" if ($cond_lines);
+				if (defined($stat_real) && $cond_lines > 1) {
+					$stat_real = "[...]\n$stat_real";
+				}
+
+				ERROR("TRAILING_STATEMENTS",
+				      "trailing statements should be on next line\n" . $herecurr . $stat_real);
+			}
+		}
+
+# Check for bitwise tests written as boolean
+		if ($line =~ /
+			(?:
+				(?:\[|\(|\&\&|\|\|)
+				\s*0[xX][0-9]+\s*
+				(?:\&\&|\|\|)
+			|
+				(?:\&\&|\|\|)
+				\s*0[xX][0-9]+\s*
+				(?:\&\&|\|\||\)|\])
+			)/x)
+		{
+			WARN("HEXADECIMAL_BOOLEAN_TEST",
+			     "boolean test with hexadecimal, perhaps just 1 \& or \|?\n" . $herecurr);
+		}
+
+# if and else should not have general statements after it
+		if ($line =~ /^.\s*(?:}\s*)?else\b(.*)/) {
+			my $s = $1;
+			$s =~ s/$;//g; 	# Remove any comments
+			if ($s !~ /^\s*(?:\sif|(?:{|)\s*\\?\s*$)/) {
+				ERROR("TRAILING_STATEMENTS",
+				      "trailing statements should be on next line\n" . $herecurr);
+			}
+		}
+# if should not continue a brace
+		if ($line =~ /}\s*if\b/) {
+			ERROR("TRAILING_STATEMENTS",
+			      "trailing statements should be on next line\n" .
+				$herecurr);
+		}
+# case and default should not have general statements after them
+		if ($line =~ /^.\s*(?:case\s*.*|default\s*):/g &&
+		    $line !~ /\G(?:
+			(?:\s*$;*)(?:\s*{)?(?:\s*$;*)(?:\s*\\)?\s*$|
+			\s*return\s+
+		    )/xg)
+		{
+			ERROR("TRAILING_STATEMENTS",
+			      "trailing statements should be on next line\n" . $herecurr);
+		}
+
+		# Check for }<nl>else {, these must be at the same
+		# indent level to be relevant to each other.
+		if ($prevline=~/}\s*$/ and $line=~/^.\s*else\s*/ and
+						$previndent == $indent) {
+			ERROR("ELSE_AFTER_BRACE",
+			      "else should follow close brace '}'\n" . $hereprev);
+		}
+
+		if ($prevline=~/}\s*$/ and $line=~/^.\s*while\s*/ and
+						$previndent == $indent) {
+			my ($s, $c) = ctx_statement_block($linenr, $realcnt, 0);
+
+			# Find out what is on the end of the line after the
+			# conditional.
+			substr($s, 0, length($c), '');
+			$s =~ s/\n.*//g;
+
+			if ($s =~ /^\s*;/) {
+				ERROR("WHILE_AFTER_BRACE",
+				      "while should follow close brace '}'\n" . $hereprev);
+			}
+		}
+
+#Specific variable tests
+		while ($line =~ m{($Constant|$Lval)}g) {
+			my $var = $1;
+
+#gcc binary extension
+			if ($var =~ /^$Binary$/) {
+				if (WARN("GCC_BINARY_CONSTANT",
+					 "Avoid gcc v4.3+ binary constant extension: <$var>\n" . $herecurr) &&
+				    $fix) {
+					my $hexval = sprintf("0x%x", oct($var));
+					$fixed[$linenr - 1] =~
+					    s/\b$var\b/$hexval/;
+				}
+			}
+
+#CamelCase
+			if ($var !~ /^$Constant$/ &&
+			    $var =~ /[A-Z][a-z]|[a-z][A-Z]/ &&
+#Ignore Page<foo> variants
+			    $var !~ /^(?:Clear|Set|TestClear|TestSet|)Page[A-Z]/ &&
+#Ignore SI style variants like nS, mV and dB (ie: max_uV, regulator_min_uA_show)
+			    $var !~ /^(?:[a-z_]*?)_?[a-z][A-Z](?:_[a-z_]+)?$/) {
+				while ($var =~ m{($Ident)}g) {
+					my $word = $1;
+					next if ($word !~ /[A-Z][a-z]|[a-z][A-Z]/);
+					if ($check) {
+						seed_camelcase_includes();
+						if (!$file && !$camelcase_file_seeded) {
+							seed_camelcase_file($realfile);
+							$camelcase_file_seeded = 1;
+						}
+					}
+					if (!defined $camelcase{$word}) {
+						$camelcase{$word} = 1;
+						CHK("CAMELCASE",
+						    "Avoid CamelCase: <$word>\n" . $herecurr);
+					}
+				}
+			}
+		}
+
+#no spaces allowed after \ in define
+		if ($line =~ /\#\s*define.*\\\s+$/) {
+			if (WARN("WHITESPACE_AFTER_LINE_CONTINUATION",
+				 "Whitespace after \\ makes next lines useless\n" . $herecurr) &&
+			    $fix) {
+				$fixed[$linenr - 1] =~ s/\s+$//;
+			}
+		}
+
+#warn if <asm/foo.h> is #included and <linux/foo.h> is available (uses RAW line)
+		if ($tree && $rawline =~ m{^.\s*\#\s*include\s*\<asm\/(.*)\.h\>}) {
+			my $file = "$1.h";
+			my $checkfile = "include/linux/$file";
+			if (-f "$root/$checkfile" &&
+			    $realfile ne $checkfile &&
+			    $1 !~ /$allowed_asm_includes/)
+			{
+				if ($realfile =~ m{^arch/}) {
+					CHK("ARCH_INCLUDE_LINUX",
+					    "Consider using #include <linux/$file> instead of <asm/$file>\n" . $herecurr);
+				} else {
+					WARN("INCLUDE_LINUX",
+					     "Use #include <linux/$file> instead of <asm/$file>\n" . $herecurr);
+				}
+			}
+		}
+
+# multi-statement macros should be enclosed in a do while loop, grab the
+# first statement and ensure its the whole macro if its not enclosed
+# in a known good container
+		if ($realfile !~ m@/vmlinux.lds.h$@ &&
+		    $line =~ /^.\s*\#\s*define\s*$Ident(\()?/) {
+			my $ln = $linenr;
+			my $cnt = $realcnt;
+			my ($off, $dstat, $dcond, $rest);
+			my $ctx = '';
+			($dstat, $dcond, $ln, $cnt, $off) =
+				ctx_statement_block($linenr, $realcnt, 0);
+			$ctx = $dstat;
+			#print "dstat<$dstat> dcond<$dcond> cnt<$cnt> off<$off>\n";
+			#print "LINE<$lines[$ln-1]> len<" . length($lines[$ln-1]) . "\n";
+
+			$dstat =~ s/^.\s*\#\s*define\s+$Ident(?:\([^\)]*\))?\s*//;
+			$dstat =~ s/$;//g;
+			$dstat =~ s/\\\n.//g;
+			$dstat =~ s/^\s*//s;
+			$dstat =~ s/\s*$//s;
+
+			# Flatten any parentheses and braces
+			while ($dstat =~ s/\([^\(\)]*\)/1/ ||
+			       $dstat =~ s/\{[^\{\}]*\}/1/ ||
+			       $dstat =~ s/\[[^\[\]]*\]/1/)
+			{
+			}
+
+			# Flatten any obvious string concatentation.
+			while ($dstat =~ s/("X*")\s*$Ident/$1/ ||
+			       $dstat =~ s/$Ident\s*("X*")/$1/)
+			{
+			}
+
+			my $exceptions = qr{
+				$Declare|
+				module_param_named|
+				MODULE_PARM_DESC|
+				DECLARE_PER_CPU|
+				DEFINE_PER_CPU|
+				__typeof__\(|
+				union|
+				struct|
+				\.$Ident\s*=\s*|
+				^\"|\"$
+			}x;
+			#print "REST<$rest> dstat<$dstat> ctx<$ctx>\n";
+			if ($dstat ne '' &&
+			    $dstat !~ /^(?:$Ident|-?$Constant),$/ &&			# 10, // foo(),
+			    $dstat !~ /^(?:$Ident|-?$Constant);$/ &&			# foo();
+			    $dstat !~ /^[!~-]?(?:$Lval|$Constant)$/ &&		# 10 // foo() // !foo // ~foo // -foo // foo->bar // foo.bar->baz
+			    $dstat !~ /^'X'$/ &&					# character constants
+			    $dstat !~ /$exceptions/ &&
+			    $dstat !~ /^\.$Ident\s*=/ &&				# .foo =
+			    $dstat !~ /^(?:\#\s*$Ident|\#\s*$Constant)\s*$/ &&		# stringification #foo
+			    $dstat !~ /^do\s*$Constant\s*while\s*$Constant;?$/ &&	# do {...} while (...); // do {...} while (...)
+			    $dstat !~ /^for\s*$Constant$/ &&				# for (...)
+			    $dstat !~ /^for\s*$Constant\s+(?:$Ident|-?$Constant)$/ &&	# for (...) bar()
+			    $dstat !~ /^do\s*{/ &&					# do {...
+			    $dstat !~ /^\({/ &&						# ({...
+			    $ctx !~ /^.\s*#\s*define\s+TRACE_(?:SYSTEM|INCLUDE_FILE|INCLUDE_PATH)\b/)
+			{
+				$ctx =~ s/\n*$//;
+				my $herectx = $here . "\n";
+				my $cnt = statement_rawlines($ctx);
+
+				for (my $n = 0; $n < $cnt; $n++) {
+					$herectx .= raw_line($linenr, $n) . "\n";
+				}
+
+				if ($dstat =~ /;/) {
+					ERROR("MULTISTATEMENT_MACRO_USE_DO_WHILE",
+					      "Macros with multiple statements should be enclosed in a do - while loop\n" . "$herectx");
+				} else {
+					ERROR("COMPLEX_MACRO",
+					      "Macros with complex values should be enclosed in parenthesis\n" . "$herectx");
+				}
+			}
+
+# check for line continuations outside of #defines, preprocessor #, and asm
+
+		} else {
+			if ($prevline !~ /^..*\\$/ &&
+			    $line !~ /^\+\s*\#.*\\$/ &&		# preprocessor
+			    $line !~ /^\+.*\b(__asm__|asm)\b.*\\$/ &&	# asm
+			    $line =~ /^\+.*\\$/) {
+				WARN("LINE_CONTINUATIONS",
+				     "Avoid unnecessary line continuations\n" . $herecurr);
+			}
+		}
+
+# do {} while (0) macro tests:
+# single-statement macros do not need to be enclosed in do while (0) loop,
+# macro should not end with a semicolon
+		if ($^V && $^V ge 5.10.0 &&
+		    $realfile !~ m@/vmlinux.lds.h$@ &&
+		    $line =~ /^.\s*\#\s*define\s+$Ident(\()?/) {
+			my $ln = $linenr;
+			my $cnt = $realcnt;
+			my ($off, $dstat, $dcond, $rest);
+			my $ctx = '';
+			($dstat, $dcond, $ln, $cnt, $off) =
+				ctx_statement_block($linenr, $realcnt, 0);
+			$ctx = $dstat;
+
+			$dstat =~ s/\\\n.//g;
+
+			if ($dstat =~ /^\+\s*#\s*define\s+$Ident\s*${balanced_parens}\s*do\s*{(.*)\s*}\s*while\s*\(\s*0\s*\)\s*([;\s]*)\s*$/) {
+				my $stmts = $2;
+				my $semis = $3;
+
+				$ctx =~ s/\n*$//;
+				my $cnt = statement_rawlines($ctx);
+				my $herectx = $here . "\n";
+
+				for (my $n = 0; $n < $cnt; $n++) {
+					$herectx .= raw_line($linenr, $n) . "\n";
+				}
+
+				if (($stmts =~ tr/;/;/) == 1 &&
+				    $stmts !~ /^\s*(if|while|for|switch)\b/) {
+					WARN("SINGLE_STATEMENT_DO_WHILE_MACRO",
+					     "Single statement macros should not use a do {} while (0) loop\n" . "$herectx");
+				}
+				if (defined $semis && $semis ne "") {
+					WARN("DO_WHILE_MACRO_WITH_TRAILING_SEMICOLON",
+					     "do {} while (0) macros should not be semicolon terminated\n" . "$herectx");
+				}
+			}
+		}
+
+# make sure symbols are always wrapped with VMLINUX_SYMBOL() ...
+# all assignments may have only one of the following with an assignment:
+#	.
+#	ALIGN(...)
+#	VMLINUX_SYMBOL(...)
+		if ($realfile eq 'vmlinux.lds.h' && $line =~ /(?:(?:^|\s)$Ident\s*=|=\s*$Ident(?:\s|$))/) {
+			WARN("MISSING_VMLINUX_SYMBOL",
+			     "vmlinux.lds.h needs VMLINUX_SYMBOL() around C-visible symbols\n" . $herecurr);
+		}
+
+# check for redundant bracing round if etc
+		if ($line =~ /(^.*)\bif\b/ && $1 !~ /else\s*$/) {
+			my ($level, $endln, @chunks) =
+				ctx_statement_full($linenr, $realcnt, 1);
+			#print "chunks<$#chunks> linenr<$linenr> endln<$endln> level<$level>\n";
+			#print "APW: <<$chunks[1][0]>><<$chunks[1][1]>>\n";
+			if ($#chunks > 0 && $level == 0) {
+				my @allowed = ();
+				my $allow = 0;
+				my $seen = 0;
+				my $herectx = $here . "\n";
+				my $ln = $linenr - 1;
+				for my $chunk (@chunks) {
+					my ($cond, $block) = @{$chunk};
+
+					# If the condition carries leading newlines, then count those as offsets.
+					my ($whitespace) = ($cond =~ /^((?:\s*\n[+-])*\s*)/s);
+					my $offset = statement_rawlines($whitespace) - 1;
+
+					$allowed[$allow] = 0;
+					#print "COND<$cond> whitespace<$whitespace> offset<$offset>\n";
+
+					# We have looked at and allowed this specific line.
+					$suppress_ifbraces{$ln + $offset} = 1;
+
+					$herectx .= "$rawlines[$ln + $offset]\n[...]\n";
+					$ln += statement_rawlines($block) - 1;
+
+					substr($block, 0, length($cond), '');
+
+					$seen++ if ($block =~ /^\s*{/);
+
+					#print "cond<$cond> block<$block> allowed<$allowed[$allow]>\n";
+					if (statement_lines($cond) > 1) {
+						#print "APW: ALLOWED: cond<$cond>\n";
+						$allowed[$allow] = 1;
+					}
+					if ($block =~/\b(?:if|for|while)\b/) {
+						#print "APW: ALLOWED: block<$block>\n";
+						$allowed[$allow] = 1;
+					}
+					if (statement_block_size($block) > 1) {
+						#print "APW: ALLOWED: lines block<$block>\n";
+						$allowed[$allow] = 1;
+					}
+					$allow++;
+				}
+				if ($seen) {
+					my $sum_allowed = 0;
+					foreach (@allowed) {
+						$sum_allowed += $_;
+					}
+					if ($sum_allowed == 0) {
+						WARN("BRACES",
+						     "braces {} are not necessary for any arm of this statement\n" . $herectx);
+					} elsif ($sum_allowed != $allow &&
+						 $seen != $allow) {
+						CHK("BRACES",
+						    "braces {} should be used on all arms of this statement\n" . $herectx);
+					}
+				}
+			}
+		}
+		if (!defined $suppress_ifbraces{$linenr - 1} &&
+					$line =~ /\b(if|while|for|else)\b/) {
+			my $allowed = 0;
+
+			# Check the pre-context.
+			if (substr($line, 0, $-[0]) =~ /(\}\s*)$/) {
+				#print "APW: ALLOWED: pre<$1>\n";
+				$allowed = 1;
+			}
+
+			my ($level, $endln, @chunks) =
+				ctx_statement_full($linenr, $realcnt, $-[0]);
+
+			# Check the condition.
+			my ($cond, $block) = @{$chunks[0]};
+			#print "CHECKING<$linenr> cond<$cond> block<$block>\n";
+			if (defined $cond) {
+				substr($block, 0, length($cond), '');
+			}
+			if (statement_lines($cond) > 1) {
+				#print "APW: ALLOWED: cond<$cond>\n";
+				$allowed = 1;
+			}
+			if ($block =~/\b(?:if|for|while)\b/) {
+				#print "APW: ALLOWED: block<$block>\n";
+				$allowed = 1;
+			}
+			if (statement_block_size($block) > 1) {
+				#print "APW: ALLOWED: lines block<$block>\n";
+				$allowed = 1;
+			}
+			# Check the post-context.
+			if (defined $chunks[1]) {
+				my ($cond, $block) = @{$chunks[1]};
+				if (defined $cond) {
+					substr($block, 0, length($cond), '');
+				}
+				if ($block =~ /^\s*\{/) {
+					#print "APW: ALLOWED: chunk-1 block<$block>\n";
+					$allowed = 1;
+				}
+			}
+			if ($level == 0 && $block =~ /^\s*\{/ && !$allowed) {
+				my $herectx = $here . "\n";
+				my $cnt = statement_rawlines($block);
+
+				for (my $n = 0; $n < $cnt; $n++) {
+					$herectx .= raw_line($linenr, $n) . "\n";
+				}
+
+				WARN("BRACES",
+				     "braces {} are not necessary for single statement blocks\n" . $herectx);
+			}
+		}
+
+# check for unnecessary blank lines around braces
+		if (($line =~ /^.\s*}\s*$/ && $prevrawline =~ /^.\s*$/)) {
+			CHK("BRACES",
+			    "Blank lines aren't necessary before a close brace '}'\n" . $hereprev);
+		}
+		if (($rawline =~ /^.\s*$/ && $prevline =~ /^..*{\s*$/)) {
+			CHK("BRACES",
+			    "Blank lines aren't necessary after an open brace '{'\n" . $hereprev);
+		}
+
+# no volatiles please
+		my $asm_volatile = qr{\b(__asm__|asm)\s+(__volatile__|volatile)\b};
+		if ($line =~ /\bvolatile\b/ && $line !~ /$asm_volatile/) {
+			WARN("VOLATILE",
+			     "Use of volatile is usually wrong: see Documentation/volatile-considered-harmful.txt\n" . $herecurr);
+		}
+
+# warn about #if 0
+		if ($line =~ /^.\s*\#\s*if\s+0\b/) {
+			CHK("REDUNDANT_CODE",
+			    "if this code is redundant consider removing it\n" .
+				$herecurr);
+		}
+
+# check for needless "if (<foo>) fn(<foo>)" uses
+		if ($prevline =~ /\bif\s*\(\s*($Lval)\s*\)/) {
+			my $expr = '\s*\(\s*' . quotemeta($1) . '\s*\)\s*;';
+			if ($line =~ /\b(kfree|usb_free_urb|debugfs_remove(?:_recursive)?)$expr/) {
+				WARN('NEEDLESS_IF',
+				     "$1(NULL) is safe this check is probably not required\n" . $hereprev);
+			}
+		}
+
+# check for bad placement of section $InitAttribute (e.g.: __initdata)
+		if ($line =~ /(\b$InitAttribute\b)/) {
+			my $attr = $1;
+			if ($line =~ /^\+\s*static\s+(?:const\s+)?(?:$attr\s+)?($NonptrTypeWithAttr)\s+(?:$attr\s+)?($Ident(?:\[[^]]*\])?)\s*[=;]/) {
+				my $ptr = $1;
+				my $var = $2;
+				if ((($ptr =~ /\b(union|struct)\s+$attr\b/ &&
+				      ERROR("MISPLACED_INIT",
+					    "$attr should be placed after $var\n" . $herecurr)) ||
+				     ($ptr !~ /\b(union|struct)\s+$attr\b/ &&
+				      WARN("MISPLACED_INIT",
+					   "$attr should be placed after $var\n" . $herecurr))) &&
+				    $fix) {
+					$fixed[$linenr - 1] =~ s/(\bstatic\s+(?:const\s+)?)(?:$attr\s+)?($NonptrTypeWithAttr)\s+(?:$attr\s+)?($Ident(?:\[[^]]*\])?)\s*([=;])\s*/"$1" . trim(string_find_replace($2, "\\s*$attr\\s*", " ")) . " " . trim(string_find_replace($3, "\\s*$attr\\s*", "")) . " $attr" . ("$4" eq ";" ? ";" : " = ")/e;
+				}
+			}
+		}
+
+# check for $InitAttributeData (ie: __initdata) with const
+		if ($line =~ /\bconst\b/ && $line =~ /($InitAttributeData)/) {
+			my $attr = $1;
+			$attr =~ /($InitAttributePrefix)(.*)/;
+			my $attr_prefix = $1;
+			my $attr_type = $2;
+			if (ERROR("INIT_ATTRIBUTE",
+				  "Use of const init definition must use ${attr_prefix}initconst\n" . $herecurr) &&
+			    $fix) {
+				$fixed[$linenr - 1] =~
+				    s/$InitAttributeData/${attr_prefix}initconst/;
+			}
+		}
+
+# check for $InitAttributeConst (ie: __initconst) without const
+		if ($line !~ /\bconst\b/ && $line =~ /($InitAttributeConst)/) {
+			my $attr = $1;
+			if (ERROR("INIT_ATTRIBUTE",
+				  "Use of $attr requires a separate use of const\n" . $herecurr) &&
+			    $fix) {
+				my $lead = $fixed[$linenr - 1] =~
+				    /(^\+\s*(?:static\s+))/;
+				$lead = rtrim($1);
+				$lead = "$lead " if ($lead !~ /^\+$/);
+				$lead = "${lead}const ";
+				$fixed[$linenr - 1] =~ s/(^\+\s*(?:static\s+))/$lead/;
+			}
+		}
+
+# prefer usleep_range over udelay
+		if ($line =~ /\budelay\s*\(\s*(\d+)\s*\)/) {
+			# ignore udelay's < 10, however
+			if (! ($1 < 10) ) {
+				CHK("USLEEP_RANGE",
+				    "usleep_range is preferred over udelay; see Documentation/timers/timers-howto.txt\n" . $line);
+			}
+		}
+
+# warn about unexpectedly long msleep's
+		if ($line =~ /\bmsleep\s*\((\d+)\);/) {
+			if ($1 < 20) {
+				WARN("MSLEEP",
+				     "msleep < 20ms can sleep for up to 20ms; see Documentation/timers/timers-howto.txt\n" . $line);
+			}
+		}
+
+# check for comparisons of jiffies
+		if ($line =~ /\bjiffies\s*$Compare|$Compare\s*jiffies\b/) {
+			WARN("JIFFIES_COMPARISON",
+			     "Comparing jiffies is almost always wrong; prefer time_after, time_before and friends\n" . $herecurr);
+		}
+
+# check for comparisons of get_jiffies_64()
+		if ($line =~ /\bget_jiffies_64\s*\(\s*\)\s*$Compare|$Compare\s*get_jiffies_64\s*\(\s*\)/) {
+			WARN("JIFFIES_COMPARISON",
+			     "Comparing get_jiffies_64() is almost always wrong; prefer time_after64, time_before64 and friends\n" . $herecurr);
+		}
+
+# warn about #ifdefs in C files
+#		if ($line =~ /^.\s*\#\s*if(|n)def/ && ($realfile =~ /\.c$/)) {
+#			print "#ifdef in C files should be avoided\n";
+#			print "$herecurr";
+#			$clean = 0;
+#		}
+
+# warn about spacing in #ifdefs
+		if ($line =~ /^.\s*\#\s*(ifdef|ifndef|elif)\s\s+/) {
+			if (ERROR("SPACING",
+				  "exactly one space required after that #$1\n" . $herecurr) &&
+			    $fix) {
+				$fixed[$linenr - 1] =~
+				    s/^(.\s*\#\s*(ifdef|ifndef|elif))\s{2,}/$1 /;
+			}
+
+		}
+
+# check for spinlock_t definitions without a comment.
+		if ($line =~ /^.\s*(struct\s+mutex|spinlock_t)\s+\S+;/ ||
+		    $line =~ /^.\s*(DEFINE_MUTEX)\s*\(/) {
+			my $which = $1;
+			if (!ctx_has_comment($first_line, $linenr)) {
+				CHK("UNCOMMENTED_DEFINITION",
+				    "$1 definition without comment\n" . $herecurr);
+			}
+		}
+# check for memory barriers without a comment.
+		if ($line =~ /\b(mb|rmb|wmb|read_barrier_depends|smp_mb|smp_rmb|smp_wmb|smp_read_barrier_depends)\(/) {
+			if (!ctx_has_comment($first_line, $linenr)) {
+				WARN("MEMORY_BARRIER",
+				     "memory barrier without comment\n" . $herecurr);
+			}
+		}
+# check of hardware specific defines
+		if ($line =~ m@^.\s*\#\s*if.*\b(__i386__|__powerpc64__|__sun__|__s390x__)\b@ && $realfile !~ m@include/asm-@) {
+			CHK("ARCH_DEFINES",
+			    "architecture specific defines should be avoided\n" .  $herecurr);
+		}
+
+# Check that the storage class is at the beginning of a declaration
+		if ($line =~ /\b$Storage\b/ && $line !~ /^.\s*$Storage\b/) {
+			WARN("STORAGE_CLASS",
+			     "storage class should be at the beginning of the declaration\n" . $herecurr)
+		}
+
+# check the location of the inline attribute, that it is between
+# storage class and type.
+		if ($line =~ /\b$Type\s+$Inline\b/ ||
+		    $line =~ /\b$Inline\s+$Storage\b/) {
+			ERROR("INLINE_LOCATION",
+			      "inline keyword should sit between storage class and type\n" . $herecurr);
+		}
+
+# Check for __inline__ and __inline, prefer inline
+		if ($realfile !~ m@\binclude/uapi/@ &&
+		    $line =~ /\b(__inline__|__inline)\b/) {
+			if (WARN("INLINE",
+				 "plain inline is preferred over $1\n" . $herecurr) &&
+			    $fix) {
+				$fixed[$linenr - 1] =~ s/\b(__inline__|__inline)\b/inline/;
+
+			}
+		}
+
+# Check for __attribute__ packed, prefer __packed
+		if ($realfile !~ m@\binclude/uapi/@ &&
+		    $line =~ /\b__attribute__\s*\(\s*\(.*\bpacked\b/) {
+			WARN("PREFER_PACKED",
+			     "__packed is preferred over __attribute__((packed))\n" . $herecurr);
+		}
+# Check for new packed members, warn to use care
+		if ($line =~ /\b(__attribute__\s*\(\s*\(.*\bpacked|__packed)\b/) {
+			WARN("NEW_PACKED",
+			     "Adding new packed members is to be done with care\n" . $herecurr);
+		}
+
+# Check for __attribute__ aligned, prefer __aligned
+		if ($realfile !~ m@\binclude/uapi/@ &&
+		    $line =~ /\b__attribute__\s*\(\s*\(.*aligned/) {
+			WARN("PREFER_ALIGNED",
+			     "__aligned(size) is preferred over __attribute__((aligned(size)))\n" . $herecurr);
+		}
+
+# Check for __attribute__ format(printf, prefer __printf
+		if ($realfile !~ m@\binclude/uapi/@ &&
+		    $line =~ /\b__attribute__\s*\(\s*\(\s*format\s*\(\s*printf/) {
+			if (WARN("PREFER_PRINTF",
+				 "__printf(string-index, first-to-check) is preferred over __attribute__((format(printf, string-index, first-to-check)))\n" . $herecurr) &&
+			    $fix) {
+				$fixed[$linenr - 1] =~ s/\b__attribute__\s*\(\s*\(\s*format\s*\(\s*printf\s*,\s*(.*)\)\s*\)\s*\)/"__printf(" . trim($1) . ")"/ex;
+
+			}
+		}
+
+# Check for __attribute__ format(scanf, prefer __scanf
+		if ($realfile !~ m@\binclude/uapi/@ &&
+		    $line =~ /\b__attribute__\s*\(\s*\(\s*format\s*\(\s*scanf\b/) {
+			if (WARN("PREFER_SCANF",
+				 "__scanf(string-index, first-to-check) is preferred over __attribute__((format(scanf, string-index, first-to-check)))\n" . $herecurr) &&
+			    $fix) {
+				$fixed[$linenr - 1] =~ s/\b__attribute__\s*\(\s*\(\s*format\s*\(\s*scanf\s*,\s*(.*)\)\s*\)\s*\)/"__scanf(" . trim($1) . ")"/ex;
+			}
+		}
+
+# check for sizeof(&)
+		if ($line =~ /\bsizeof\s*\(\s*\&/) {
+			WARN("SIZEOF_ADDRESS",
+			     "sizeof(& should be avoided\n" . $herecurr);
+		}
+
+# check for sizeof without parenthesis
+		if ($line =~ /\bsizeof\s+((?:\*\s*|)$Lval|$Type(?:\s+$Lval|))/) {
+			if (WARN("SIZEOF_PARENTHESIS",
+				 "sizeof $1 should be sizeof($1)\n" . $herecurr) &&
+			    $fix) {
+				$fixed[$linenr - 1] =~ s/\bsizeof\s+((?:\*\s*|)$Lval|$Type(?:\s+$Lval|))/"sizeof(" . trim($1) . ")"/ex;
+			}
+		}
+
+# check for line continuations in quoted strings with odd counts of "
+		if ($rawline =~ /\\$/ && $rawline =~ tr/"/"/ % 2) {
+			WARN("LINE_CONTINUATIONS",
+			     "Avoid line continuations in quoted strings\n" . $herecurr);
+		}
+
+# check for struct spinlock declarations
+		if ($line =~ /^.\s*\bstruct\s+spinlock\s+\w+\s*;/) {
+			WARN("USE_SPINLOCK_T",
+			     "struct spinlock should be spinlock_t\n" . $herecurr);
+		}
+
+# check for seq_printf uses that could be seq_puts
+		if ($sline =~ /\bseq_printf\s*\(.*"\s*\)\s*;\s*$/) {
+			my $fmt = get_quoted_string($line, $rawline);
+			if ($fmt ne "" && $fmt !~ /[^\\]\%/) {
+				if (WARN("PREFER_SEQ_PUTS",
+					 "Prefer seq_puts to seq_printf\n" . $herecurr) &&
+				    $fix) {
+					$fixed[$linenr - 1] =~ s/\bseq_printf\b/seq_puts/;
+				}
+			}
+		}
+
+# Check for misused memsets
+		if ($^V && $^V ge 5.10.0 &&
+		    defined $stat &&
+		    $stat =~ /^\+(?:.*?)\bmemset\s*\(\s*$FuncArg\s*,\s*$FuncArg\s*\,\s*$FuncArg\s*\)/s) {
+
+			my $ms_addr = $2;
+			my $ms_val = $7;
+			my $ms_size = $12;
+
+			if ($ms_size =~ /^(0x|)0$/i) {
+				ERROR("MEMSET",
+				      "memset to 0's uses 0 as the 2nd argument, not the 3rd\n" . "$here\n$stat\n");
+			} elsif ($ms_size =~ /^(0x|)1$/i) {
+				WARN("MEMSET",
+				     "single byte memset is suspicious. Swapped 2nd/3rd argument?\n" . "$here\n$stat\n");
+			}
+		}
+
+# Check for memcpy(foo, bar, ETH_ALEN) that could be ether_addr_copy(foo, bar)
+		if ($^V && $^V ge 5.10.0 &&
+		    $line =~ /^\+(?:.*?)\bmemcpy\s*\(\s*$FuncArg\s*,\s*$FuncArg\s*\,\s*ETH_ALEN\s*\)/s) {
+			if (WARN("PREFER_ETHER_ADDR_COPY",
+				 "Prefer ether_addr_copy() over memcpy() if the Ethernet addresses are __aligned(2)\n" . $herecurr) &&
+			    $fix) {
+				$fixed[$linenr - 1] =~ s/\bmemcpy\s*\(\s*$FuncArg\s*,\s*$FuncArg\s*\,\s*ETH_ALEN\s*\)/ether_addr_copy($2, $7)/;
+			}
+		}
+
+# typecasts on min/max could be min_t/max_t
+		if ($^V && $^V ge 5.10.0 &&
+		    defined $stat &&
+		    $stat =~ /^\+(?:.*?)\b(min|max)\s*\(\s*$FuncArg\s*,\s*$FuncArg\s*\)/) {
+			if (defined $2 || defined $7) {
+				my $call = $1;
+				my $cast1 = deparenthesize($2);
+				my $arg1 = $3;
+				my $cast2 = deparenthesize($7);
+				my $arg2 = $8;
+				my $cast;
+
+				if ($cast1 ne "" && $cast2 ne "" && $cast1 ne $cast2) {
+					$cast = "$cast1 or $cast2";
+				} elsif ($cast1 ne "") {
+					$cast = $cast1;
+				} else {
+					$cast = $cast2;
+				}
+				WARN("MINMAX",
+				     "$call() should probably be ${call}_t($cast, $arg1, $arg2)\n" . "$here\n$stat\n");
+			}
+		}
+
+# check usleep_range arguments
+		if ($^V && $^V ge 5.10.0 &&
+		    defined $stat &&
+		    $stat =~ /^\+(?:.*?)\busleep_range\s*\(\s*($FuncArg)\s*,\s*($FuncArg)\s*\)/) {
+			my $min = $1;
+			my $max = $7;
+			if ($min eq $max) {
+				WARN("USLEEP_RANGE",
+				     "usleep_range should not use min == max args; see Documentation/timers/timers-howto.txt\n" . "$here\n$stat\n");
+			} elsif ($min =~ /^\d+$/ && $max =~ /^\d+$/ &&
+				 $min > $max) {
+				WARN("USLEEP_RANGE",
+				     "usleep_range args reversed, use min then max; see Documentation/timers/timers-howto.txt\n" . "$here\n$stat\n");
+			}
+		}
+
+# check for naked sscanf
+		if ($^V && $^V ge 5.10.0 &&
+		    defined $stat &&
+		    $stat =~ /\bsscanf\b/ &&
+		    ($stat !~ /$Ident\s*=\s*sscanf\s*$balanced_parens/ &&
+		     $stat !~ /\bsscanf\s*$balanced_parens\s*(?:$Compare)/ &&
+		     $stat !~ /(?:$Compare)\s*\bsscanf\s*$balanced_parens/)) {
+			my $lc = $stat =~ tr@\n@@;
+			$lc = $lc + $linenr;
+			my $stat_real = raw_line($linenr, 0);
+		        for (my $count = $linenr + 1; $count <= $lc; $count++) {
+				$stat_real = $stat_real . "\n" . raw_line($count, 0);
+			}
+			WARN("NAKED_SSCANF",
+			     "unchecked sscanf return value\n" . "$here\n$stat_real\n");
+		}
+
+# check for new externs in .h files.
+		if ($realfile =~ /\.h$/ &&
+		    $line =~ /^\+\s*(extern\s+)$Type\s*$Ident\s*\(/s) {
+			if (CHK("AVOID_EXTERNS",
+				"extern prototypes should be avoided in .h files\n" . $herecurr) &&
+			    $fix) {
+				$fixed[$linenr - 1] =~ s/(.*)\bextern\b\s*(.*)/$1$2/;
+			}
+		}
+
+# check for new externs in .c files.
+		if ($realfile =~ /\.c$/ && defined $stat &&
+		    $stat =~ /^.\s*(?:extern\s+)?$Type\s+($Ident)(\s*)\(/s)
+		{
+			my $function_name = $1;
+			my $paren_space = $2;
+
+			my $s = $stat;
+			if (defined $cond) {
+				substr($s, 0, length($cond), '');
+			}
+			if ($s =~ /^\s*;/ &&
+			    $function_name ne 'uninitialized_var')
+			{
+				WARN("AVOID_EXTERNS",
+				     "externs should be avoided in .c files\n" .  $herecurr);
+			}
+
+			if ($paren_space =~ /\n/) {
+				WARN("FUNCTION_ARGUMENTS",
+				     "arguments for function declarations should follow identifier\n" . $herecurr);
+			}
+
+		} elsif ($realfile =~ /\.c$/ && defined $stat &&
+		    $stat =~ /^.\s*extern\s+/)
+		{
+			WARN("AVOID_EXTERNS",
+			     "externs should be avoided in .c files\n" .  $herecurr);
+		}
+
+# checks for new __setup's
+		if ($rawline =~ /\b__setup\("([^"]*)"/) {
+			my $name = $1;
+
+			if (!grep(/$name/, @setup_docs)) {
+				CHK("UNDOCUMENTED_SETUP",
+				    "__setup appears un-documented -- check Documentation/kernel-parameters.txt\n" . $herecurr);
+			}
+		}
+
+# check for pointless casting of kmalloc return
+		if ($line =~ /\*\s*\)\s*[kv][czm]alloc(_node){0,1}\b/) {
+			WARN("UNNECESSARY_CASTS",
+			     "unnecessary cast may hide bugs, see http://c-faq.com/malloc/mallocnocast.html\n" . $herecurr);
+		}
+
+# alloc style
+# p = alloc(sizeof(struct foo), ...) should be p = alloc(sizeof(*p), ...)
+		if ($^V && $^V ge 5.10.0 &&
+		    $line =~ /\b($Lval)\s*\=\s*(?:$balanced_parens)?\s*([kv][mz]alloc(?:_node)?)\s*\(\s*(sizeof\s*\(\s*struct\s+$Lval\s*\))/) {
+			CHK("ALLOC_SIZEOF_STRUCT",
+			    "Prefer $3(sizeof(*$1)...) over $3($4...)\n" . $herecurr);
+		}
+
+# check for krealloc arg reuse
+		if ($^V && $^V ge 5.10.0 &&
+		    $line =~ /\b($Lval)\s*\=\s*(?:$balanced_parens)?\s*krealloc\s*\(\s*\1\s*,/) {
+			WARN("KREALLOC_ARG_REUSE",
+			     "Reusing the krealloc arg is almost always a bug\n" . $herecurr);
+		}
+
+# check for alloc argument mismatch
+		if ($line =~ /\b(kcalloc|kmalloc_array)\s*\(\s*sizeof\b/) {
+			WARN("ALLOC_ARRAY_ARGS",
+			     "$1 uses number as first arg, sizeof is generally wrong\n" . $herecurr);
+		}
+
+# check for GFP_NOWAIT use
+		if ($line =~ /\b__GFP_NOFAIL\b/) {
+			WARN("__GFP_NOFAIL",
+			     "Use of __GFP_NOFAIL is deprecated, no new users should be added\n" . $herecurr);
+		}
+
+# check for multiple semicolons
+		if ($line =~ /;\s*;\s*$/) {
+			if (WARN("ONE_SEMICOLON",
+				 "Statements terminations use 1 semicolon\n" . $herecurr) &&
+			    $fix) {
+				$fixed[$linenr - 1] =~ s/(\s*;\s*){2,}$/;/g;
+			}
+		}
+
+# check for case / default statements not preceeded by break/fallthrough/switch
+		if ($line =~ /^.\s*(?:case\s+(?:$Ident|$Constant)\s*|default):/) {
+			my $has_break = 0;
+			my $has_statement = 0;
+			my $count = 0;
+			my $prevline = $linenr;
+			while ($prevline > 1 && $count < 3 && !$has_break) {
+				$prevline--;
+				my $rline = $rawlines[$prevline - 1];
+				my $fline = $lines[$prevline - 1];
+				last if ($fline =~ /^\@\@/);
+				next if ($fline =~ /^\-/);
+				next if ($fline =~ /^.(?:\s*(?:case\s+(?:$Ident|$Constant)[\s$;]*|default):[\s$;]*)*$/);
+				$has_break = 1 if ($rline =~ /fall[\s_-]*(through|thru)/i);
+				next if ($fline =~ /^.[\s$;]*$/);
+				$has_statement = 1;
+				$count++;
+				$has_break = 1 if ($fline =~ /\bswitch\b|\b(?:break\s*;[\s$;]*$|return\b|goto\b|continue\b)/);
+			}
+			if (!$has_break && $has_statement) {
+				WARN("MISSING_BREAK",
+				     "Possible switch case/default not preceeded by break or fallthrough comment\n" . $herecurr);
+			}
+		}
+
+# check for switch/default statements without a break;
+		if ($^V && $^V ge 5.10.0 &&
+		    defined $stat &&
+		    $stat =~ /^\+[$;\s]*(?:case[$;\s]+\w+[$;\s]*:[$;\s]*|)*[$;\s]*\bdefault[$;\s]*:[$;\s]*;/g) {
+			my $ctx = '';
+			my $herectx = $here . "\n";
+			my $cnt = statement_rawlines($stat);
+			for (my $n = 0; $n < $cnt; $n++) {
+				$herectx .= raw_line($linenr, $n) . "\n";
+			}
+			WARN("DEFAULT_NO_BREAK",
+			     "switch default: should use break\n" . $herectx);
+		}
+
+# check for gcc specific __FUNCTION__
+		if ($line =~ /\b__FUNCTION__\b/) {
+			if (WARN("USE_FUNC",
+				 "__func__ should be used instead of gcc specific __FUNCTION__\n"  . $herecurr) &&
+			    $fix) {
+				$fixed[$linenr - 1] =~ s/\b__FUNCTION__\b/__func__/g;
+			}
+		}
+
+# check for use of yield()
+		if ($line =~ /\byield\s*\(\s*\)/) {
+			WARN("YIELD",
+			     "Using yield() is generally wrong. See yield() kernel-doc (sched/core.c)\n"  . $herecurr);
+		}
+
+# check for comparisons against true and false
+		if ($line =~ /\+\s*(.*?)\b(true|false|$Lval)\s*(==|\!=)\s*(true|false|$Lval)\b(.*)$/i) {
+			my $lead = $1;
+			my $arg = $2;
+			my $test = $3;
+			my $otype = $4;
+			my $trail = $5;
+			my $op = "!";
+
+			($arg, $otype) = ($otype, $arg) if ($arg =~ /^(?:true|false)$/i);
+
+			my $type = lc($otype);
+			if ($type =~ /^(?:true|false)$/) {
+				if (("$test" eq "==" && "$type" eq "true") ||
+				    ("$test" eq "!=" && "$type" eq "false")) {
+					$op = "";
+				}
+
+				CHK("BOOL_COMPARISON",
+				    "Using comparison to $otype is error prone\n" . $herecurr);
+
+## maybe suggesting a correct construct would better
+##				    "Using comparison to $otype is error prone.  Perhaps use '${lead}${op}${arg}${trail}'\n" . $herecurr);
+
+			}
+		}
+
+# check for semaphores initialized locked
+		if ($line =~ /^.\s*sema_init.+,\W?0\W?\)/) {
+			WARN("CONSIDER_COMPLETION",
+			     "consider using a completion\n" . $herecurr);
+		}
+
+# recommend kstrto* over simple_strto* and strict_strto*
+		if ($line =~ /\b((simple|strict)_(strto(l|ll|ul|ull)))\s*\(/) {
+			WARN("CONSIDER_KSTRTO",
+			     "$1 is obsolete, use k$3 instead\n" . $herecurr);
+		}
+
+# check for __initcall(), use device_initcall() explicitly please
+		if ($line =~ /^.\s*__initcall\s*\(/) {
+			WARN("USE_DEVICE_INITCALL",
+			     "please use device_initcall() instead of __initcall()\n" . $herecurr);
+		}
+
+# check for various ops structs, ensure they are const.
+		my $struct_ops = qr{acpi_dock_ops|
+				address_space_operations|
+				backlight_ops|
+				block_device_operations|
+				dentry_operations|
+				dev_pm_ops|
+				dma_map_ops|
+				extent_io_ops|
+				file_lock_operations|
+				file_operations|
+				hv_ops|
+				ide_dma_ops|
+				intel_dvo_dev_ops|
+				item_operations|
+				iwl_ops|
+				kgdb_arch|
+				kgdb_io|
+				kset_uevent_ops|
+				lock_manager_operations|
+				microcode_ops|
+				mtrr_ops|
+				neigh_ops|
+				nlmsvc_binding|
+				pci_raw_ops|
+				pipe_buf_operations|
+				platform_hibernation_ops|
+				platform_suspend_ops|
+				proto_ops|
+				rpc_pipe_ops|
+				seq_operations|
+				snd_ac97_build_ops|
+				soc_pcmcia_socket_ops|
+				stacktrace_ops|
+				sysfs_ops|
+				tty_operations|
+				usb_mon_operations|
+				wd_ops}x;
+		if ($line !~ /\bconst\b/ &&
+		    $line =~ /\bstruct\s+($struct_ops)\b/) {
+			WARN("CONST_STRUCT",
+			     "struct $1 should normally be const\n" .
+				$herecurr);
+		}
+
+# use of NR_CPUS is usually wrong
+# ignore definitions of NR_CPUS and usage to define arrays as likely right
+		if ($line =~ /\bNR_CPUS\b/ &&
+		    $line !~ /^.\s*\s*#\s*if\b.*\bNR_CPUS\b/ &&
+		    $line !~ /^.\s*\s*#\s*define\b.*\bNR_CPUS\b/ &&
+		    $line !~ /^.\s*$Declare\s.*\[[^\]]*NR_CPUS[^\]]*\]/ &&
+		    $line !~ /\[[^\]]*\.\.\.[^\]]*NR_CPUS[^\]]*\]/ &&
+		    $line !~ /\[[^\]]*NR_CPUS[^\]]*\.\.\.[^\]]*\]/)
+		{
+			WARN("NR_CPUS",
+			     "usage of NR_CPUS is often wrong - consider using cpu_possible(), num_possible_cpus(), for_each_possible_cpu(), etc\n" . $herecurr);
+		}
+
+# Use of __ARCH_HAS_<FOO> or ARCH_HAVE_<BAR> is wrong.
+		if ($line =~ /\+\s*#\s*define\s+((?:__)?ARCH_(?:HAS|HAVE)\w*)\b/) {
+			ERROR("DEFINE_ARCH_HAS",
+			      "#define of '$1' is wrong - use Kconfig variables or standard guards instead\n" . $herecurr);
+		}
+
+# check for %L{u,d,i} in strings
+		my $string;
+		while ($line =~ /(?:^|")([X\t]*)(?:"|$)/g) {
+			$string = substr($rawline, $-[1], $+[1] - $-[1]);
+			$string =~ s/%%/__/g;
+			if ($string =~ /(?<!%)%L[udi]/) {
+				WARN("PRINTF_L",
+				     "\%Ld/%Lu are not-standard C, use %lld/%llu\n" . $herecurr);
+				last;
+			}
+		}
+
+# whine mightly about in_atomic
+		if ($line =~ /\bin_atomic\s*\(/) {
+			if ($realfile =~ m@^drivers/@) {
+				ERROR("IN_ATOMIC",
+				      "do not use in_atomic in drivers\n" . $herecurr);
+			} elsif ($realfile !~ m@^kernel/@) {
+				WARN("IN_ATOMIC",
+				     "use of in_atomic() is incorrect outside core kernel code\n" . $herecurr);
+			}
+		}
+
+# check for lockdep_set_novalidate_class
+		if ($line =~ /^.\s*lockdep_set_novalidate_class\s*\(/ ||
+		    $line =~ /__lockdep_no_validate__\s*\)/ ) {
+			if ($realfile !~ m@^kernel/lockdep@ &&
+			    $realfile !~ m@^include/linux/lockdep@ &&
+			    $realfile !~ m@^drivers/base/core@) {
+				ERROR("LOCKDEP",
+				      "lockdep_no_validate class is reserved for device->mutex.\n" . $herecurr);
+			}
+		}
+
+		if ($line =~ /debugfs_create_file.*S_IWUGO/ ||
+		    $line =~ /DEVICE_ATTR.*S_IWUGO/ ) {
+			WARN("EXPORTED_WORLD_WRITABLE",
+			     "Exporting world writable files is usually an error. Consider more restrictive permissions.\n" . $herecurr);
+		}
+	}
+
+	# If we have no input at all, then there is nothing to report on
+	# so just keep quiet.
+	if ($#rawlines == -1) {
+		exit(0);
+	}
+
+	# In mailback mode only produce a report in the negative, for
+	# things that appear to be patches.
+	if ($mailback && ($clean == 1 || !$is_patch)) {
+		exit(0);
+	}
+
+	# This is not a patch, and we are are in 'no-patch' mode so
+	# just keep quiet.
+	if (!$chk_patch && !$is_patch) {
+		exit(0);
+	}
+
+	if (!$is_patch) {
+		ERROR("NOT_UNIFIED_DIFF",
+		      "Does not appear to be a unified-diff format patch\n");
+	}
+	if ($is_patch && $chk_signoff && $signoff == 0) {
+		ERROR("MISSING_SIGN_OFF",
+		      "Missing Signed-off-by: line(s)\n");
+	}
+
+	print report_dump();
+	if ($summary && !($clean == 1 && $quiet == 1)) {
+		print "$filename " if ($summary_file);
+		print "total: $cnt_error errors, $cnt_warn warnings, " .
+			(($check)? "$cnt_chk checks, " : "") .
+			"$cnt_lines lines checked\n";
+		print "\n" if ($quiet == 0);
+	}
+
+	if ($quiet == 0) {
+
+		if ($^V lt 5.10.0) {
+			print("NOTE: perl $^V is not modern enough to detect all possible issues.\n");
+			print("An upgrade to at least perl v5.10.0 is suggested.\n\n");
+		}
+
+		# If there were whitespace errors which cleanpatch can fix
+		# then suggest that.
+		if ($rpt_cleaners) {
+			print "NOTE: whitespace errors detected, you may wish to use scripts/cleanpatch or\n";
+			print "      scripts/cleanfile\n\n";
+			$rpt_cleaners = 0;
+		}
+	}
+
+	hash_show_words(\%use_type, "Used");
+	hash_show_words(\%ignore_type, "Ignored");
+
+	if ($clean == 0 && $fix && "@rawlines" ne "@fixed") {
+		my $newfile = $filename;
+		$newfile .= ".EXPERIMENTAL-checkpatch-fixes" if (!$fix_inplace);
+		my $linecount = 0;
+		my $f;
+
+		open($f, '>', $newfile)
+		    or die "$P: Can't open $newfile for write\n";
+		foreach my $fixed_line (@fixed) {
+			$linecount++;
+			if ($file) {
+				if ($linecount > 3) {
+					$fixed_line =~ s/^\+//;
+					print $f $fixed_line. "\n";
+				}
+			} else {
+				print $f $fixed_line . "\n";
+			}
+		}
+		close($f);
+
+		if (!$quiet) {
+			print << "EOM";
+Wrote EXPERIMENTAL --fix correction(s) to '$newfile'
+
+Do _NOT_ trust the results written to this file.
+Do _NOT_ submit these changes without inspecting them for correctness.
+
+This EXPERIMENTAL file is simply a convenience to help rewrite patches.
+No warranties, expressed or implied...
+
+EOM
+		}
+	}
+
+	if ($clean == 1 && $quiet == 0) {
+		print "$vname has no obvious style problems and is ready for submission.\n"
+	}
+	if ($clean == 0 && $quiet == 0) {
+		print << "EOM";
+$vname has style problems, please review.
+
+If any of these errors are false positives, please report
+them to the maintainer, see CHECKPATCH in MAINTAINERS.
+EOM
+	}
+
+	return $clean;
+}
diff --git a/tools/checkstack.pl b/scripts/checkstack.pl
index c1cdc0a92a..c1cdc0a92a 100755
--- a/tools/checkstack.pl
+++ b/scripts/checkstack.pl
diff --git a/tools/cleanpatch b/scripts/cleanpatch
index 9680d03ad2..9680d03ad2 100755
--- a/tools/cleanpatch
+++ b/scripts/cleanpatch
diff --git a/scripts/docproc.c b/scripts/docproc.c
new file mode 100644
index 0000000000..2b69eaf5b6
--- /dev/null
+++ b/scripts/docproc.c
@@ -0,0 +1,580 @@
+/*
+ *	docproc is a simple preprocessor for the template files
+ *      used as placeholders for the kernel internal documentation.
+ *	docproc is used for documentation-frontend and
+ *      dependency-generator.
+ *	The two usages have in common that they require
+ *	some knowledge of the .tmpl syntax, therefore they
+ *	are kept together.
+ *
+ *	documentation-frontend
+ *		Scans the template file and call kernel-doc for
+ *		all occurrences of ![EIF]file
+ *		Beforehand each referenced file is scanned for
+ *		any symbols that are exported via these macros:
+ *			EXPORT_SYMBOL(), EXPORT_SYMBOL_GPL(), &
+ *			EXPORT_SYMBOL_GPL_FUTURE()
+ *		This is used to create proper -function and
+ *		-nofunction arguments in calls to kernel-doc.
+ *		Usage: docproc doc file.tmpl
+ *
+ *	dependency-generator:
+ *		Scans the template file and list all files
+ *		referenced in a format recognized by make.
+ *		Usage:	docproc depend file.tmpl
+ *		Writes dependency information to stdout
+ *		in the following format:
+ *		file.tmpl src.c	src2.c
+ *		The filenames are obtained from the following constructs:
+ *		!Efilename
+ *		!Ifilename
+ *		!Dfilename
+ *		!Ffilename
+ *		!Pfilename
+ *
+ */
+
+#define _GNU_SOURCE
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+#include <ctype.h>
+#include <unistd.h>
+#include <limits.h>
+#include <errno.h>
+#include <sys/types.h>
+#include <sys/wait.h>
+
+/* exitstatus is used to keep track of any failing calls to kernel-doc,
+ * but execution continues. */
+int exitstatus = 0;
+
+typedef void DFL(char *);
+DFL *defaultline;
+
+typedef void FILEONLY(char * file);
+FILEONLY *internalfunctions;
+FILEONLY *externalfunctions;
+FILEONLY *symbolsonly;
+FILEONLY *findall;
+
+typedef void FILELINE(char * file, char * line);
+FILELINE * singlefunctions;
+FILELINE * entity_system;
+FILELINE * docsection;
+
+#define MAXLINESZ     2048
+#define MAXFILES      250
+#define KERNELDOCPATH "scripts/"
+#define KERNELDOC     "kernel-doc"
+#define DOCBOOK       "-docbook"
+#define LIST          "-list"
+#define FUNCTION      "-function"
+#define NOFUNCTION    "-nofunction"
+#define NODOCSECTIONS "-no-doc-sections"
+#define SHOWNOTFOUND  "-show-not-found"
+
+static char *srctree, *kernsrctree;
+
+static char **all_list = NULL;
+static int all_list_len = 0;
+
+static void consume_symbol(const char *sym)
+{
+	int i;
+
+	for (i = 0; i < all_list_len; i++) {
+		if (!all_list[i])
+			continue;
+		if (strcmp(sym, all_list[i]))
+			continue;
+		all_list[i] = NULL;
+		break;
+	}
+}
+
+static void usage (void)
+{
+	fprintf(stderr, "Usage: docproc {doc|depend} file\n");
+	fprintf(stderr, "Input is read from file.tmpl. Output is sent to stdout\n");
+	fprintf(stderr, "doc: frontend when generating kernel documentation\n");
+	fprintf(stderr, "depend: generate list of files referenced within file\n");
+	fprintf(stderr, "Environment variable SRCTREE: absolute path to sources.\n");
+	fprintf(stderr, "                     KBUILD_SRC: absolute path to kernel source tree.\n");
+}
+
+/*
+ * Execute kernel-doc with parameters given in svec
+ */
+static void exec_kernel_doc(char **svec)
+{
+	pid_t pid;
+	int ret;
+	char real_filename[PATH_MAX + 1];
+	/* Make sure output generated so far are flushed */
+	fflush(stdout);
+	switch (pid=fork()) {
+		case -1:
+			perror("fork");
+			exit(1);
+		case  0:
+			memset(real_filename, 0, sizeof(real_filename));
+			strncat(real_filename, kernsrctree, PATH_MAX);
+			strncat(real_filename, "/" KERNELDOCPATH KERNELDOC,
+					PATH_MAX - strlen(real_filename));
+			execvp(real_filename, svec);
+			fprintf(stderr, "exec ");
+			perror(real_filename);
+			exit(1);
+		default:
+			waitpid(pid, &ret ,0);
+	}
+	if (WIFEXITED(ret))
+		exitstatus |= WEXITSTATUS(ret);
+	else
+		exitstatus = 0xff;
+}
+
+/* Types used to create list of all exported symbols in a number of files */
+struct symbols
+{
+	char *name;
+};
+
+struct symfile
+{
+	char *filename;
+	struct symbols *symbollist;
+	int symbolcnt;
+};
+
+struct symfile symfilelist[MAXFILES];
+int symfilecnt = 0;
+
+static void add_new_symbol(struct symfile *sym, char * symname)
+{
+	sym->symbollist =
+          realloc(sym->symbollist, (sym->symbolcnt + 1) * sizeof(char *));
+	sym->symbollist[sym->symbolcnt++].name = strdup(symname);
+}
+
+/* Add a filename to the list */
+static struct symfile * add_new_file(char * filename)
+{
+	symfilelist[symfilecnt++].filename = strdup(filename);
+	return &symfilelist[symfilecnt - 1];
+}
+
+/* Check if file already are present in the list */
+static struct symfile * filename_exist(char * filename)
+{
+	int i;
+	for (i=0; i < symfilecnt; i++)
+		if (strcmp(symfilelist[i].filename, filename) == 0)
+			return &symfilelist[i];
+	return NULL;
+}
+
+/*
+ * List all files referenced within the template file.
+ * Files are separated by tabs.
+ */
+static void adddep(char * file)		   { printf("\t%s", file); }
+static void adddep2(char * file, char * line)     { line = line; adddep(file); }
+static void noaction(char * line)		   { line = line; }
+static void noaction2(char * file, char * line)   { file = file; line = line; }
+
+/* Echo the line without further action */
+static void printline(char * line)               { printf("%s", line); }
+
+/*
+ * Find all symbols in filename that are exported with EXPORT_SYMBOL &
+ * EXPORT_SYMBOL_GPL (& EXPORT_SYMBOL_GPL_FUTURE implicitly).
+ * All symbols located are stored in symfilelist.
+ */
+static void find_export_symbols(char * filename)
+{
+	FILE * fp;
+	struct symfile *sym;
+	char line[MAXLINESZ];
+	if (filename_exist(filename) == NULL) {
+		char real_filename[PATH_MAX + 1];
+		memset(real_filename, 0, sizeof(real_filename));
+		strncat(real_filename, srctree, PATH_MAX);
+		strncat(real_filename, "/", PATH_MAX - strlen(real_filename));
+		strncat(real_filename, filename,
+				PATH_MAX - strlen(real_filename));
+		sym = add_new_file(filename);
+		fp = fopen(real_filename, "r");
+		if (fp == NULL)	{
+			fprintf(stderr, "docproc: ");
+			perror(real_filename);
+			exit(1);
+		}
+		while (fgets(line, MAXLINESZ, fp)) {
+			char *p;
+			char *e;
+			if (((p = strstr(line, "EXPORT_SYMBOL_GPL")) != NULL) ||
+                            ((p = strstr(line, "EXPORT_SYMBOL")) != NULL)) {
+				/* Skip EXPORT_SYMBOL{_GPL} */
+				while (isalnum(*p) || *p == '_')
+					p++;
+				/* Remove parentheses & additional whitespace */
+				while (isspace(*p))
+					p++;
+				if (*p != '(')
+					continue; /* Syntax error? */
+				else
+					p++;
+				while (isspace(*p))
+					p++;
+				e = p;
+				while (isalnum(*e) || *e == '_')
+					e++;
+				*e = '\0';
+				add_new_symbol(sym, p);
+			}
+		}
+		fclose(fp);
+	}
+}
+
+/*
+ * Document all external or internal functions in a file.
+ * Call kernel-doc with following parameters:
+ * kernel-doc -docbook -nofunction function_name1 filename
+ * Function names are obtained from all the src files
+ * by find_export_symbols.
+ * intfunc uses -nofunction
+ * extfunc uses -function
+ */
+static void docfunctions(char * filename, char * type)
+{
+	int i,j;
+	int symcnt = 0;
+	int idx = 0;
+	char **vec;
+
+	for (i=0; i <= symfilecnt; i++)
+		symcnt += symfilelist[i].symbolcnt;
+	vec = malloc((2 + 2 * symcnt + 3) * sizeof(char *));
+	if (vec == NULL) {
+		perror("docproc: ");
+		exit(1);
+	}
+	vec[idx++] = KERNELDOC;
+	vec[idx++] = DOCBOOK;
+	vec[idx++] = NODOCSECTIONS;
+	for (i=0; i < symfilecnt; i++) {
+		struct symfile * sym = &symfilelist[i];
+		for (j=0; j < sym->symbolcnt; j++) {
+			vec[idx++]     = type;
+			consume_symbol(sym->symbollist[j].name);
+			vec[idx++] = sym->symbollist[j].name;
+		}
+	}
+	vec[idx++]     = filename;
+	vec[idx] = NULL;
+	printf("<!-- %s -->\n", filename);
+	exec_kernel_doc(vec);
+	fflush(stdout);
+	free(vec);
+}
+static void intfunc(char * filename) {	docfunctions(filename, NOFUNCTION); }
+static void extfunc(char * filename) { docfunctions(filename, FUNCTION);   }
+
+/*
+ * Document specific function(s) in a file.
+ * Call kernel-doc with the following parameters:
+ * kernel-doc -docbook -function function1 [-function function2]
+ */
+static void singfunc(char * filename, char * line)
+{
+	char *vec[200]; /* Enough for specific functions */
+        int i, idx = 0;
+        int startofsym = 1;
+	vec[idx++] = KERNELDOC;
+	vec[idx++] = DOCBOOK;
+	vec[idx++] = SHOWNOTFOUND;
+
+        /* Split line up in individual parameters preceded by FUNCTION */
+        for (i=0; line[i]; i++) {
+                if (isspace(line[i])) {
+                        line[i] = '\0';
+                        startofsym = 1;
+                        continue;
+                }
+                if (startofsym) {
+                        startofsym = 0;
+                        vec[idx++] = FUNCTION;
+                        vec[idx++] = &line[i];
+                }
+        }
+	for (i = 0; i < idx; i++) {
+        	if (strcmp(vec[i], FUNCTION))
+        		continue;
+		consume_symbol(vec[i + 1]);
+	}
+	vec[idx++] = filename;
+	vec[idx] = NULL;
+	exec_kernel_doc(vec);
+}
+
+/*
+ * Insert specific documentation section from a file.
+ * Call kernel-doc with the following parameters:
+ * kernel-doc -docbook -function "doc section" filename
+ */
+static void docsect(char *filename, char *line)
+{
+	/* kerneldoc -docbook -show-not-found -function "section" file NULL */
+	char *vec[7];
+	char *s;
+
+	for (s = line; *s; s++)
+		if (*s == '\n')
+			*s = '\0';
+
+	if (asprintf(&s, "DOC: %s", line) < 0) {
+		perror("asprintf");
+		exit(1);
+	}
+	consume_symbol(s);
+	free(s);
+
+	vec[0] = KERNELDOC;
+	vec[1] = DOCBOOK;
+	vec[2] = SHOWNOTFOUND;
+	vec[3] = FUNCTION;
+	vec[4] = line;
+	vec[5] = filename;
+	vec[6] = NULL;
+	exec_kernel_doc(vec);
+}
+
+static void find_all_symbols(char *filename)
+{
+	char *vec[4]; /* kerneldoc -list file NULL */
+	pid_t pid;
+	int ret, i, count, start;
+	char real_filename[PATH_MAX + 1];
+	int pipefd[2];
+	char *data, *str;
+	size_t data_len = 0;
+
+	vec[0] = KERNELDOC;
+	vec[1] = LIST;
+	vec[2] = filename;
+	vec[3] = NULL;
+
+	if (pipe(pipefd)) {
+		perror("pipe");
+		exit(1);
+	}
+
+	switch (pid=fork()) {
+		case -1:
+			perror("fork");
+			exit(1);
+		case  0:
+			close(pipefd[0]);
+			dup2(pipefd[1], 1);
+			memset(real_filename, 0, sizeof(real_filename));
+			strncat(real_filename, kernsrctree, PATH_MAX);
+			strncat(real_filename, "/" KERNELDOCPATH KERNELDOC,
+					PATH_MAX - strlen(real_filename));
+			execvp(real_filename, vec);
+			fprintf(stderr, "exec ");
+			perror(real_filename);
+			exit(1);
+		default:
+			close(pipefd[1]);
+			data = malloc(4096);
+			do {
+				while ((ret = read(pipefd[0],
+						   data + data_len,
+						   4096)) > 0) {
+					data_len += ret;
+					data = realloc(data, data_len + 4096);
+				}
+			} while (ret == -EAGAIN);
+			if (ret != 0) {
+				perror("read");
+				exit(1);
+			}
+			waitpid(pid, &ret ,0);
+	}
+	if (WIFEXITED(ret))
+		exitstatus |= WEXITSTATUS(ret);
+	else
+		exitstatus = 0xff;
+
+	count = 0;
+	/* poor man's strtok, but with counting */
+	for (i = 0; i < data_len; i++) {
+		if (data[i] == '\n') {
+			count++;
+			data[i] = '\0';
+		}
+	}
+	start = all_list_len;
+	all_list_len += count;
+	all_list = realloc(all_list, sizeof(char *) * all_list_len);
+	str = data;
+	for (i = 0; i < data_len && start != all_list_len; i++) {
+		if (data[i] == '\0') {
+			all_list[start] = str;
+			str = data + i + 1;
+			start++;
+		}
+	}
+}
+
+/*
+ * Parse file, calling action specific functions for:
+ * 1) Lines containing !E
+ * 2) Lines containing !I
+ * 3) Lines containing !D
+ * 4) Lines containing !F
+ * 5) Lines containing !P
+ * 6) Lines containing !C
+ * 7) Default lines - lines not matching the above
+ */
+static void parse_file(FILE *infile)
+{
+	char line[MAXLINESZ];
+	char * s;
+	while (fgets(line, MAXLINESZ, infile)) {
+		if (line[0] == '!') {
+			s = line + 2;
+			switch (line[1]) {
+				case 'E':
+					while (*s && !isspace(*s)) s++;
+					*s = '\0';
+					externalfunctions(line+2);
+					break;
+				case 'I':
+					while (*s && !isspace(*s)) s++;
+					*s = '\0';
+					internalfunctions(line+2);
+					break;
+				case 'D':
+					while (*s && !isspace(*s)) s++;
+                                        *s = '\0';
+                                        symbolsonly(line+2);
+                                        break;
+				case 'F':
+					/* filename */
+					while (*s && !isspace(*s)) s++;
+					*s++ = '\0';
+                                        /* function names */
+					while (isspace(*s))
+						s++;
+					singlefunctions(line +2, s);
+					break;
+				case 'P':
+					/* filename */
+					while (*s && !isspace(*s)) s++;
+					*s++ = '\0';
+					/* DOC: section name */
+					while (isspace(*s))
+						s++;
+					docsection(line + 2, s);
+					break;
+				case 'C':
+					while (*s && !isspace(*s)) s++;
+					*s = '\0';
+					if (findall)
+						findall(line+2);
+					break;
+				default:
+					defaultline(line);
+			}
+		} else {
+			defaultline(line);
+		}
+	}
+	fflush(stdout);
+}
+
+
+int main(int argc, char *argv[])
+{
+	FILE * infile;
+	int i;
+
+	srctree = getenv("SRCTREE");
+	if (!srctree)
+		srctree = getcwd(NULL, 0);
+	kernsrctree = getenv("KBUILD_SRC");
+	if (!kernsrctree || !*kernsrctree)
+		kernsrctree = srctree;
+	if (argc != 3) {
+		usage();
+		exit(1);
+	}
+	/* Open file, exit on error */
+	infile = fopen(argv[2], "r");
+        if (infile == NULL) {
+                fprintf(stderr, "docproc: ");
+                perror(argv[2]);
+                exit(2);
+        }
+
+	if (strcmp("doc", argv[1]) == 0) {
+		/* Need to do this in two passes.
+		 * First pass is used to collect all symbols exported
+		 * in the various files;
+		 * Second pass generate the documentation.
+		 * This is required because some functions are declared
+		 * and exported in different files :-((
+		 */
+		/* Collect symbols */
+		defaultline       = noaction;
+		internalfunctions = find_export_symbols;
+		externalfunctions = find_export_symbols;
+		symbolsonly       = find_export_symbols;
+		singlefunctions   = noaction2;
+		docsection        = noaction2;
+		findall           = find_all_symbols;
+		parse_file(infile);
+
+		/* Rewind to start from beginning of file again */
+		fseek(infile, 0, SEEK_SET);
+		defaultline       = printline;
+		internalfunctions = intfunc;
+		externalfunctions = extfunc;
+		symbolsonly       = printline;
+		singlefunctions   = singfunc;
+		docsection        = docsect;
+		findall           = NULL;
+
+		parse_file(infile);
+
+		for (i = 0; i < all_list_len; i++) {
+			if (!all_list[i])
+				continue;
+			fprintf(stderr, "Warning: didn't use docs for %s\n",
+				all_list[i]);
+		}
+	} else if (strcmp("depend", argv[1]) == 0) {
+		/* Create first part of dependency chain
+		 * file.tmpl */
+		printf("%s\t", argv[2]);
+		defaultline       = noaction;
+		internalfunctions = adddep;
+		externalfunctions = adddep;
+		symbolsonly       = adddep;
+		singlefunctions   = adddep2;
+		docsection        = adddep2;
+		findall           = adddep;
+		parse_file(infile);
+		printf("\n");
+	} else {
+		fprintf(stderr, "Unknown option: %s\n", argv[1]);
+		exit(1);
+	}
+	fclose(infile);
+	fflush(stdout);
+	return exitstatus;
+}
diff --git a/tools/dtc-version.sh b/scripts/dtc-version.sh
index e8c94d390b..e8c94d390b 100755..100644
--- a/tools/dtc-version.sh
+++ b/scripts/dtc-version.sh
diff --git a/scripts/gcc-stack-usage.sh b/scripts/gcc-stack-usage.sh
new file mode 100644
index 0000000000..27ac928969
--- /dev/null
+++ b/scripts/gcc-stack-usage.sh
@@ -0,0 +1,18 @@
+#!/bin/sh
+# Test for gcc '-fstack-usage' support
+# Copyright (C) 2013, Masahiro Yamada <yamada.m@jp.panasonic.com>
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+TMP="$$"
+
+cat <<END | $@ -Werror -fstack-usage -x c - -c -o $TMP >/dev/null 2>&1 \
+							&& echo "y"
+int main(void)
+{
+	return 0;
+}
+END
+
+rm -f $TMP $TMP.su
diff --git a/tools/gcc-version.sh b/scripts/gcc-version.sh
index debecb5561..debecb5561 100755..100644
--- a/tools/gcc-version.sh
+++ b/scripts/gcc-version.sh
diff --git a/scripts/kernel-doc b/scripts/kernel-doc
new file mode 100755
index 0000000000..c881b8cb3e
--- /dev/null
+++ b/scripts/kernel-doc
@@ -0,0 +1,2609 @@
+#!/usr/bin/perl -w
+
+use strict;
+
+## Copyright (c) 1998 Michael Zucchi, All Rights Reserved        ##
+## Copyright (C) 2000, 1  Tim Waugh <twaugh@redhat.com>          ##
+## Copyright (C) 2001  Simon Huggins                             ##
+## Copyright (C) 2005-2012  Randy Dunlap                         ##
+## Copyright (C) 2012  Dan Luedtke                               ##
+## 								 ##
+## #define enhancements by Armin Kuster <akuster@mvista.com>	 ##
+## Copyright (c) 2000 MontaVista Software, Inc.			 ##
+## 								 ##
+## This software falls under the GNU General Public License.     ##
+## Please read the COPYING file for more information             ##
+
+# 18/01/2001 - 	Cleanups
+# 		Functions prototyped as foo(void) same as foo()
+# 		Stop eval'ing where we don't need to.
+# -- huggie@earth.li
+
+# 27/06/2001 -  Allowed whitespace after initial "/**" and
+#               allowed comments before function declarations.
+# -- Christian Kreibich <ck@whoop.org>
+
+# Still to do:
+# 	- add perldoc documentation
+# 	- Look more closely at some of the scarier bits :)
+
+# 26/05/2001 - 	Support for separate source and object trees.
+#		Return error code.
+# 		Keith Owens <kaos@ocs.com.au>
+
+# 23/09/2001 - Added support for typedefs, structs, enums and unions
+#              Support for Context section; can be terminated using empty line
+#              Small fixes (like spaces vs. \s in regex)
+# -- Tim Jansen <tim@tjansen.de>
+
+# 25/07/2012 - Added support for HTML5
+# -- Dan Luedtke <mail@danrl.de>
+
+#
+# This will read a 'c' file and scan for embedded comments in the
+# style of gnome comments (+minor extensions - see below).
+#
+
+# Note: This only supports 'c'.
+
+# usage:
+# kernel-doc [ -docbook | -html | -html5 | -text | -man | -list ]
+#            [ -no-doc-sections ]
+#            [ -function funcname [ -function funcname ...] ]
+#            c file(s)s > outputfile
+# or
+#            [ -nofunction funcname [ -function funcname ...] ]
+#            c file(s)s > outputfile
+#
+#  Set output format using one of -docbook -html -html5 -text or -man.
+#  Default is man.
+#  The -list format is for internal use by docproc.
+#
+#  -no-doc-sections
+#	Do not output DOC: sections
+#
+#  -function funcname
+#	If set, then only generate documentation for the given function(s) or
+#	DOC: section titles.  All other functions and DOC: sections are ignored.
+#
+#  -nofunction funcname
+#	If set, then only generate documentation for the other function(s)/DOC:
+#	sections. Cannot be used together with -function (yes, that's a bug --
+#	perl hackers can fix it 8))
+#
+#  c files - list of 'c' files to process
+#
+#  All output goes to stdout, with errors to stderr.
+
+#
+# format of comments.
+# In the following table, (...)? signifies optional structure.
+#                         (...)* signifies 0 or more structure elements
+# /**
+#  * function_name(:)? (- short description)?
+# (* @parameterx: (description of parameter x)?)*
+# (* a blank line)?
+#  * (Description:)? (Description of function)?
+#  * (section header: (section description)? )*
+#  (*)?*/
+#
+# So .. the trivial example would be:
+#
+# /**
+#  * my_function
+#  */
+#
+# If the Description: header tag is omitted, then there must be a blank line
+# after the last parameter specification.
+# e.g.
+# /**
+#  * my_function - does my stuff
+#  * @my_arg: its mine damnit
+#  *
+#  * Does my stuff explained.
+#  */
+#
+#  or, could also use:
+# /**
+#  * my_function - does my stuff
+#  * @my_arg: its mine damnit
+#  * Description: Does my stuff explained.
+#  */
+# etc.
+#
+# Besides functions you can also write documentation for structs, unions,
+# enums and typedefs. Instead of the function name you must write the name
+# of the declaration;  the struct/union/enum/typedef must always precede
+# the name. Nesting of declarations is not supported.
+# Use the argument mechanism to document members or constants.
+# e.g.
+# /**
+#  * struct my_struct - short description
+#  * @a: first member
+#  * @b: second member
+#  *
+#  * Longer description
+#  */
+# struct my_struct {
+#     int a;
+#     int b;
+# /* private: */
+#     int c;
+# };
+#
+# All descriptions can be multiline, except the short function description.
+#
+# You can also add additional sections. When documenting kernel functions you
+# should document the "Context:" of the function, e.g. whether the functions
+# can be called form interrupts. Unlike other sections you can end it with an
+# empty line.
+# A non-void function should have a "Return:" section describing the return
+# value(s).
+# Example-sections should contain the string EXAMPLE so that they are marked
+# appropriately in DocBook.
+#
+# Example:
+# /**
+#  * user_function - function that can only be called in user context
+#  * @a: some argument
+#  * Context: !in_interrupt()
+#  *
+#  * Some description
+#  * Example:
+#  *    user_function(22);
+#  */
+# ...
+#
+#
+# All descriptive text is further processed, scanning for the following special
+# patterns, which are highlighted appropriately.
+#
+# 'funcname()' - function
+# '$ENVVAR' - environmental variable
+# '&struct_name' - name of a structure (up to two words including 'struct')
+# '@parameter' - name of a parameter
+# '%CONST' - name of a constant.
+
+## init lots of data
+
+my $errors = 0;
+my $warnings = 0;
+my $anon_struct_union = 0;
+
+# match expressions used to find embedded type information
+my $type_constant = '\%([-_\w]+)';
+my $type_func = '(\w+)\(\)';
+my $type_param = '\@(\w+)';
+my $type_struct = '\&((struct\s*)*[_\w]+)';
+my $type_struct_xml = '\\&amp;((struct\s*)*[_\w]+)';
+my $type_env = '(\$\w+)';
+
+# Output conversion substitutions.
+#  One for each output format
+
+# these work fairly well
+my %highlights_html = ( $type_constant, "<i>\$1</i>",
+			$type_func, "<b>\$1</b>",
+			$type_struct_xml, "<i>\$1</i>",
+			$type_env, "<b><i>\$1</i></b>",
+			$type_param, "<tt><b>\$1</b></tt>" );
+my $local_lt = "\\\\\\\\lt:";
+my $local_gt = "\\\\\\\\gt:";
+my $blankline_html = $local_lt . "p" . $local_gt;	# was "<p>"
+
+# html version 5
+my %highlights_html5 = ( $type_constant, "<span class=\"const\">\$1</span>",
+			$type_func, "<span class=\"func\">\$1</span>",
+			$type_struct_xml, "<span class=\"struct\">\$1</span>",
+			$type_env, "<span class=\"env\">\$1</span>",
+			$type_param, "<span class=\"param\">\$1</span>" );
+my $blankline_html5 = $local_lt . "br /" . $local_gt;
+
+# XML, docbook format
+my %highlights_xml = ( "([^=])\\\"([^\\\"<]+)\\\"", "\$1<quote>\$2</quote>",
+			$type_constant, "<constant>\$1</constant>",
+			$type_func, "<function>\$1</function>",
+			$type_struct_xml, "<structname>\$1</structname>",
+			$type_env, "<envar>\$1</envar>",
+			$type_param, "<parameter>\$1</parameter>" );
+my $blankline_xml = $local_lt . "/para" . $local_gt . $local_lt . "para" . $local_gt . "\n";
+
+# gnome, docbook format
+my %highlights_gnome = ( $type_constant, "<replaceable class=\"option\">\$1</replaceable>",
+			 $type_func, "<function>\$1</function>",
+			 $type_struct, "<structname>\$1</structname>",
+			 $type_env, "<envar>\$1</envar>",
+			 $type_param, "<parameter>\$1</parameter>" );
+my $blankline_gnome = "</para><para>\n";
+
+# these are pretty rough
+my %highlights_man = ( $type_constant, "\$1",
+		       $type_func, "\\\\fB\$1\\\\fP",
+		       $type_struct, "\\\\fI\$1\\\\fP",
+		       $type_param, "\\\\fI\$1\\\\fP" );
+my $blankline_man = "";
+
+# text-mode
+my %highlights_text = ( $type_constant, "\$1",
+			$type_func, "\$1",
+			$type_struct, "\$1",
+			$type_param, "\$1" );
+my $blankline_text = "";
+
+# list mode
+my %highlights_list = ( $type_constant, "\$1",
+			$type_func, "\$1",
+			$type_struct, "\$1",
+			$type_param, "\$1" );
+my $blankline_list = "";
+
+# read arguments
+if ($#ARGV == -1) {
+    usage();
+}
+
+my $kernelversion;
+my $dohighlight = "";
+
+my $verbose = 0;
+my $output_mode = "man";
+my $output_preformatted = 0;
+my $no_doc_sections = 0;
+my %highlights = %highlights_man;
+my $blankline = $blankline_man;
+my $modulename = "Bootloader API";
+my $function_only = 0;
+my $man_date = ('January', 'February', 'March', 'April', 'May', 'June',
+		'July', 'August', 'September', 'October',
+		'November', 'December')[(localtime)[4]] .
+  " " . ((localtime)[5]+1900);
+my $show_not_found = 0;
+
+# Essentially these are globals.
+# They probably want to be tidied up, made more localised or something.
+# CAVEAT EMPTOR!  Some of the others I localised may not want to be, which
+# could cause "use of undefined value" or other bugs.
+my ($function, %function_table, %parametertypes, $declaration_purpose);
+my ($type, $declaration_name, $return_type);
+my ($newsection, $newcontents, $prototype, $brcount, %source_map);
+
+if (defined($ENV{'KBUILD_VERBOSE'})) {
+	$verbose = "$ENV{'KBUILD_VERBOSE'}";
+}
+
+# Generated docbook code is inserted in a template at a point where
+# docbook v3.1 requires a non-zero sequence of RefEntry's; see:
+# http://www.oasis-open.org/docbook/documentation/reference/html/refentry.html
+# We keep track of number of generated entries and generate a dummy
+# if needs be to ensure the expanded template can be postprocessed
+# into html.
+my $section_counter = 0;
+
+my $lineprefix="";
+
+# states
+# 0 - normal code
+# 1 - looking for function name
+# 2 - scanning field start.
+# 3 - scanning prototype.
+# 4 - documentation block
+my $state;
+my $in_doc_sect;
+
+#declaration types: can be
+# 'function', 'struct', 'union', 'enum', 'typedef'
+my $decl_type;
+
+my $doc_special = "\@\%\$\&";
+
+my $doc_start = '^/\*\*\s*$'; # Allow whitespace at end of comment start.
+my $doc_end = '\*/';
+my $doc_com = '\s*\*\s*';
+my $doc_com_body = '\s*\* ?';
+my $doc_decl = $doc_com . '(\w+)';
+my $doc_sect = $doc_com . '([' . $doc_special . ']?[\w\s]+):(.*)';
+my $doc_content = $doc_com_body . '(.*)';
+my $doc_block = $doc_com . 'DOC:\s*(.*)?';
+
+my %constants;
+my %parameterdescs;
+my @parameterlist;
+my %sections;
+my @sectionlist;
+my $sectcheck;
+my $struct_actual;
+
+my $contents = "";
+my $section_default = "Description";	# default section
+my $section_intro = "Introduction";
+my $section = $section_default;
+my $section_context = "Context";
+my $section_return = "Return";
+
+my $undescribed = "-- undescribed --";
+
+reset_state();
+
+while ($ARGV[0] =~ m/^-(.*)/) {
+    my $cmd = shift @ARGV;
+    if ($cmd eq "-html") {
+	$output_mode = "html";
+	%highlights = %highlights_html;
+	$blankline = $blankline_html;
+    } elsif ($cmd eq "-html5") {
+	$output_mode = "html5";
+	%highlights = %highlights_html5;
+	$blankline = $blankline_html5;
+    } elsif ($cmd eq "-man") {
+	$output_mode = "man";
+	%highlights = %highlights_man;
+	$blankline = $blankline_man;
+    } elsif ($cmd eq "-text") {
+	$output_mode = "text";
+	%highlights = %highlights_text;
+	$blankline = $blankline_text;
+    } elsif ($cmd eq "-docbook") {
+	$output_mode = "xml";
+	%highlights = %highlights_xml;
+	$blankline = $blankline_xml;
+    } elsif ($cmd eq "-list") {
+	$output_mode = "list";
+	%highlights = %highlights_list;
+	$blankline = $blankline_list;
+    } elsif ($cmd eq "-gnome") {
+	$output_mode = "gnome";
+	%highlights = %highlights_gnome;
+	$blankline = $blankline_gnome;
+    } elsif ($cmd eq "-module") { # not needed for XML, inherits from calling document
+	$modulename = shift @ARGV;
+    } elsif ($cmd eq "-function") { # to only output specific functions
+	$function_only = 1;
+	$function = shift @ARGV;
+	$function_table{$function} = 1;
+    } elsif ($cmd eq "-nofunction") { # to only output specific functions
+	$function_only = 2;
+	$function = shift @ARGV;
+	$function_table{$function} = 1;
+    } elsif ($cmd eq "-v") {
+	$verbose = 1;
+    } elsif (($cmd eq "-h") || ($cmd eq "--help")) {
+	usage();
+    } elsif ($cmd eq '-no-doc-sections') {
+	    $no_doc_sections = 1;
+    } elsif ($cmd eq '-show-not-found') {
+	$show_not_found = 1;
+    }
+}
+
+# continue execution near EOF;
+
+sub usage {
+    print "Usage: $0 [ -docbook | -html | -html5 | -text | -man | -list ]\n";
+    print "         [ -no-doc-sections ]\n";
+    print "         [ -function funcname [ -function funcname ...] ]\n";
+    print "         [ -nofunction funcname [ -nofunction funcname ...] ]\n";
+    print "         [ -v ]\n";
+    print "         c source file(s) > outputfile\n";
+    print "         -v : verbose output, more warnings & other info listed\n";
+    exit 1;
+}
+
+# get kernel version from env
+sub get_kernel_version() {
+    my $version = 'unknown kernel version';
+
+    if (defined($ENV{'UBOOTVERSION'})) {
+	$version = $ENV{'UBOOTVERSION'};
+    }
+    return $version;
+}
+
+##
+# dumps section contents to arrays/hashes intended for that purpose.
+#
+sub dump_section {
+    my $file = shift;
+    my $name = shift;
+    my $contents = join "\n", @_;
+
+    if ($name =~ m/$type_constant/) {
+	$name = $1;
+#	print STDERR "constant section '$1' = '$contents'\n";
+	$constants{$name} = $contents;
+    } elsif ($name =~ m/$type_param/) {
+#	print STDERR "parameter def '$1' = '$contents'\n";
+	$name = $1;
+	$parameterdescs{$name} = $contents;
+	$sectcheck = $sectcheck . $name . " ";
+    } elsif ($name eq "@\.\.\.") {
+#	print STDERR "parameter def '...' = '$contents'\n";
+	$name = "...";
+	$parameterdescs{$name} = $contents;
+	$sectcheck = $sectcheck . $name . " ";
+    } else {
+#	print STDERR "other section '$name' = '$contents'\n";
+	if (defined($sections{$name}) && ($sections{$name} ne "")) {
+		print STDERR "Error(${file}:$.): duplicate section name '$name'\n";
+		++$errors;
+	}
+	$sections{$name} = $contents;
+	push @sectionlist, $name;
+    }
+}
+
+##
+# dump DOC: section after checking that it should go out
+#
+sub dump_doc_section {
+    my $file = shift;
+    my $name = shift;
+    my $contents = join "\n", @_;
+
+    if ($no_doc_sections) {
+        return;
+    }
+
+    if (($function_only == 0) ||
+	( $function_only == 1 && defined($function_table{$name})) ||
+	( $function_only == 2 && !defined($function_table{$name})))
+    {
+	dump_section($file, $name, $contents);
+	output_blockhead({'sectionlist' => \@sectionlist,
+			  'sections' => \%sections,
+			  'module' => $modulename,
+			  'content-only' => ($function_only != 0), });
+    }
+}
+
+##
+# output function
+#
+# parameterdescs, a hash.
+#  function => "function name"
+#  parameterlist => @list of parameters
+#  parameterdescs => %parameter descriptions
+#  sectionlist => @list of sections
+#  sections => %section descriptions
+#
+
+sub output_highlight {
+    my $contents = join "\n",@_;
+    my $line;
+
+#   DEBUG
+#   if (!defined $contents) {
+#	use Carp;
+#	confess "output_highlight got called with no args?\n";
+#   }
+
+    if ($output_mode eq "html" || $output_mode eq "html5" ||
+	$output_mode eq "xml") {
+	$contents = local_unescape($contents);
+	# convert data read & converted thru xml_escape() into &xyz; format:
+	$contents =~ s/\\\\\\/\&/g;
+    }
+#   print STDERR "contents b4:$contents\n";
+    eval $dohighlight;
+    die $@ if $@;
+#   print STDERR "contents af:$contents\n";
+
+#   strip whitespaces when generating html5
+    if ($output_mode eq "html5") {
+	$contents =~ s/^\s+//;
+	$contents =~ s/\s+$//;
+    }
+    foreach $line (split "\n", $contents) {
+	if (! $output_preformatted) {
+	    $line =~ s/^\s*//;
+	}
+	if ($line eq ""){
+	    if (! $output_preformatted) {
+		print $lineprefix, local_unescape($blankline);
+	    }
+	} else {
+	    $line =~ s/\\\\\\/\&/g;
+	    if ($output_mode eq "man" && substr($line, 0, 1) eq ".") {
+		print "\\&$line";
+	    } else {
+		print $lineprefix, $line;
+	    }
+	}
+	print "\n";
+    }
+}
+
+# output sections in html
+sub output_section_html(%) {
+    my %args = %{$_[0]};
+    my $section;
+
+    foreach $section (@{$args{'sectionlist'}}) {
+	print "<h3>$section</h3>\n";
+	print "<blockquote>\n";
+	output_highlight($args{'sections'}{$section});
+	print "</blockquote>\n";
+    }
+}
+
+# output enum in html
+sub output_enum_html(%) {
+    my %args = %{$_[0]};
+    my ($parameter);
+    my $count;
+    print "<h2>enum " . $args{'enum'} . "</h2>\n";
+
+    print "<b>enum " . $args{'enum'} . "</b> {<br>\n";
+    $count = 0;
+    foreach $parameter (@{$args{'parameterlist'}}) {
+	print " <b>" . $parameter . "</b>";
+	if ($count != $#{$args{'parameterlist'}}) {
+	    $count++;
+	    print ",\n";
+	}
+	print "<br>";
+    }
+    print "};<br>\n";
+
+    print "<h3>Constants</h3>\n";
+    print "<dl>\n";
+    foreach $parameter (@{$args{'parameterlist'}}) {
+	print "<dt><b>" . $parameter . "</b>\n";
+	print "<dd>";
+	output_highlight($args{'parameterdescs'}{$parameter});
+    }
+    print "</dl>\n";
+    output_section_html(@_);
+    print "<hr>\n";
+}
+
+# output typedef in html
+sub output_typedef_html(%) {
+    my %args = %{$_[0]};
+    my ($parameter);
+    my $count;
+    print "<h2>typedef " . $args{'typedef'} . "</h2>\n";
+
+    print "<b>typedef " . $args{'typedef'} . "</b>\n";
+    output_section_html(@_);
+    print "<hr>\n";
+}
+
+# output struct in html
+sub output_struct_html(%) {
+    my %args = %{$_[0]};
+    my ($parameter);
+
+    print "<h2>" . $args{'type'} . " " . $args{'struct'} . " - " . $args{'purpose'} . "</h2>\n";
+    print "<b>" . $args{'type'} . " " . $args{'struct'} . "</b> {<br>\n";
+    foreach $parameter (@{$args{'parameterlist'}}) {
+	if ($parameter =~ /^#/) {
+		print "$parameter<br>\n";
+		next;
+	}
+	my $parameter_name = $parameter;
+	$parameter_name =~ s/\[.*//;
+
+	($args{'parameterdescs'}{$parameter_name} ne $undescribed) || next;
+	$type = $args{'parametertypes'}{$parameter};
+	if ($type =~ m/([^\(]*\(\*)\s*\)\s*\(([^\)]*)\)/) {
+	    # pointer-to-function
+	    print "&nbsp; &nbsp; <i>$1</i><b>$parameter</b>) <i>($2)</i>;<br>\n";
+	} elsif ($type =~ m/^(.*?)\s*(:.*)/) {
+	    # bitfield
+	    print "&nbsp; &nbsp; <i>$1</i> <b>$parameter</b>$2;<br>\n";
+	} else {
+	    print "&nbsp; &nbsp; <i>$type</i> <b>$parameter</b>;<br>\n";
+	}
+    }
+    print "};<br>\n";
+
+    print "<h3>Members</h3>\n";
+    print "<dl>\n";
+    foreach $parameter (@{$args{'parameterlist'}}) {
+	($parameter =~ /^#/) && next;
+
+	my $parameter_name = $parameter;
+	$parameter_name =~ s/\[.*//;
+
+	($args{'parameterdescs'}{$parameter_name} ne $undescribed) || next;
+	print "<dt><b>" . $parameter . "</b>\n";
+	print "<dd>";
+	output_highlight($args{'parameterdescs'}{$parameter_name});
+    }
+    print "</dl>\n";
+    output_section_html(@_);
+    print "<hr>\n";
+}
+
+# output function in html
+sub output_function_html(%) {
+    my %args = %{$_[0]};
+    my ($parameter, $section);
+    my $count;
+
+    print "<h2>" . $args{'function'} . " - " . $args{'purpose'} . "</h2>\n";
+    print "<i>" . $args{'functiontype'} . "</i>\n";
+    print "<b>" . $args{'function'} . "</b>\n";
+    print "(";
+    $count = 0;
+    foreach $parameter (@{$args{'parameterlist'}}) {
+	$type = $args{'parametertypes'}{$parameter};
+	if ($type =~ m/([^\(]*\(\*)\s*\)\s*\(([^\)]*)\)/) {
+	    # pointer-to-function
+	    print "<i>$1</i><b>$parameter</b>) <i>($2)</i>";
+	} else {
+	    print "<i>" . $type . "</i> <b>" . $parameter . "</b>";
+	}
+	if ($count != $#{$args{'parameterlist'}}) {
+	    $count++;
+	    print ",\n";
+	}
+    }
+    print ")\n";
+
+    print "<h3>Arguments</h3>\n";
+    print "<dl>\n";
+    foreach $parameter (@{$args{'parameterlist'}}) {
+	my $parameter_name = $parameter;
+	$parameter_name =~ s/\[.*//;
+
+	($args{'parameterdescs'}{$parameter_name} ne $undescribed) || next;
+	print "<dt><b>" . $parameter . "</b>\n";
+	print "<dd>";
+	output_highlight($args{'parameterdescs'}{$parameter_name});
+    }
+    print "</dl>\n";
+    output_section_html(@_);
+    print "<hr>\n";
+}
+
+# output DOC: block header in html
+sub output_blockhead_html(%) {
+    my %args = %{$_[0]};
+    my ($parameter, $section);
+    my $count;
+
+    foreach $section (@{$args{'sectionlist'}}) {
+	print "<h3>$section</h3>\n";
+	print "<ul>\n";
+	output_highlight($args{'sections'}{$section});
+	print "</ul>\n";
+    }
+    print "<hr>\n";
+}
+
+# output sections in html5
+sub output_section_html5(%) {
+    my %args = %{$_[0]};
+    my $section;
+
+    foreach $section (@{$args{'sectionlist'}}) {
+	print "<section>\n";
+	print "<h1>$section</h1>\n";
+	print "<p>\n";
+	output_highlight($args{'sections'}{$section});
+	print "</p>\n";
+	print "</section>\n";
+    }
+}
+
+# output enum in html5
+sub output_enum_html5(%) {
+    my %args = %{$_[0]};
+    my ($parameter);
+    my $count;
+    my $html5id;
+
+    $html5id = $args{'enum'};
+    $html5id =~ s/[^a-zA-Z0-9\-]+/_/g;
+    print "<article class=\"enum\" id=\"enum:". $html5id . "\">";
+    print "<h1>enum " . $args{'enum'} . "</h1>\n";
+    print "<ol class=\"code\">\n";
+    print "<li>";
+    print "<span class=\"keyword\">enum</span> ";
+    print "<span class=\"identifier\">" . $args{'enum'} . "</span> {";
+    print "</li>\n";
+    $count = 0;
+    foreach $parameter (@{$args{'parameterlist'}}) {
+	print "<li class=\"indent\">";
+	print "<span class=\"param\">" . $parameter . "</span>";
+	if ($count != $#{$args{'parameterlist'}}) {
+	    $count++;
+	    print ",";
+	}
+	print "</li>\n";
+    }
+    print "<li>};</li>\n";
+    print "</ol>\n";
+
+    print "<section>\n";
+    print "<h1>Constants</h1>\n";
+    print "<dl>\n";
+    foreach $parameter (@{$args{'parameterlist'}}) {
+	print "<dt>" . $parameter . "</dt>\n";
+	print "<dd>";
+	output_highlight($args{'parameterdescs'}{$parameter});
+	print "</dd>\n";
+    }
+    print "</dl>\n";
+    print "</section>\n";
+    output_section_html5(@_);
+    print "</article>\n";
+}
+
+# output typedef in html5
+sub output_typedef_html5(%) {
+    my %args = %{$_[0]};
+    my ($parameter);
+    my $count;
+    my $html5id;
+
+    $html5id = $args{'typedef'};
+    $html5id =~ s/[^a-zA-Z0-9\-]+/_/g;
+    print "<article class=\"typedef\" id=\"typedef:" . $html5id . "\">\n";
+    print "<h1>typedef " . $args{'typedef'} . "</h1>\n";
+
+    print "<ol class=\"code\">\n";
+    print "<li>";
+    print "<span class=\"keyword\">typedef</span> ";
+    print "<span class=\"identifier\">" . $args{'typedef'} . "</span>";
+    print "</li>\n";
+    print "</ol>\n";
+    output_section_html5(@_);
+    print "</article>\n";
+}
+
+# output struct in html5
+sub output_struct_html5(%) {
+    my %args = %{$_[0]};
+    my ($parameter);
+    my $html5id;
+
+    $html5id = $args{'struct'};
+    $html5id =~ s/[^a-zA-Z0-9\-]+/_/g;
+    print "<article class=\"struct\" id=\"struct:" . $html5id . "\">\n";
+    print "<hgroup>\n";
+    print "<h1>" . $args{'type'} . " " . $args{'struct'} . "</h1>";
+    print "<h2>". $args{'purpose'} . "</h2>\n";
+    print "</hgroup>\n";
+    print "<ol class=\"code\">\n";
+    print "<li>";
+    print "<span class=\"type\">" . $args{'type'} . "</span> ";
+    print "<span class=\"identifier\">" . $args{'struct'} . "</span> {";
+    print "</li>\n";
+    foreach $parameter (@{$args{'parameterlist'}}) {
+	print "<li class=\"indent\">";
+	if ($parameter =~ /^#/) {
+		print "<span class=\"param\">" . $parameter ."</span>\n";
+		print "</li>\n";
+		next;
+	}
+	my $parameter_name = $parameter;
+	$parameter_name =~ s/\[.*//;
+
+	($args{'parameterdescs'}{$parameter_name} ne $undescribed) || next;
+	$type = $args{'parametertypes'}{$parameter};
+	if ($type =~ m/([^\(]*\(\*)\s*\)\s*\(([^\)]*)\)/) {
+	    # pointer-to-function
+	    print "<span class=\"type\">$1</span> ";
+	    print "<span class=\"param\">$parameter</span>";
+	    print "<span class=\"type\">)</span> ";
+	    print "(<span class=\"args\">$2</span>);";
+	} elsif ($type =~ m/^(.*?)\s*(:.*)/) {
+	    # bitfield
+	    print "<span class=\"type\">$1</span> ";
+	    print "<span class=\"param\">$parameter</span>";
+	    print "<span class=\"bits\">$2</span>;";
+	} else {
+	    print "<span class=\"type\">$type</span> ";
+	    print "<span class=\"param\">$parameter</span>;";
+	}
+	print "</li>\n";
+    }
+    print "<li>};</li>\n";
+    print "</ol>\n";
+
+    print "<section>\n";
+    print "<h1>Members</h1>\n";
+    print "<dl>\n";
+    foreach $parameter (@{$args{'parameterlist'}}) {
+	($parameter =~ /^#/) && next;
+
+	my $parameter_name = $parameter;
+	$parameter_name =~ s/\[.*//;
+
+	($args{'parameterdescs'}{$parameter_name} ne $undescribed) || next;
+	print "<dt>" . $parameter . "</dt>\n";
+	print "<dd>";
+	output_highlight($args{'parameterdescs'}{$parameter_name});
+	print "</dd>\n";
+    }
+    print "</dl>\n";
+    print "</section>\n";
+    output_section_html5(@_);
+    print "</article>\n";
+}
+
+# output function in html5
+sub output_function_html5(%) {
+    my %args = %{$_[0]};
+    my ($parameter, $section);
+    my $count;
+    my $html5id;
+
+    $html5id = $args{'function'};
+    $html5id =~ s/[^a-zA-Z0-9\-]+/_/g;
+    print "<article class=\"function\" id=\"func:". $html5id . "\">\n";
+    print "<hgroup>\n";
+    print "<h1>" . $args{'function'} . "</h1>";
+    print "<h2>" . $args{'purpose'} . "</h2>\n";
+    print "</hgroup>\n";
+    print "<ol class=\"code\">\n";
+    print "<li>";
+    print "<span class=\"type\">" . $args{'functiontype'} . "</span> ";
+    print "<span class=\"identifier\">" . $args{'function'} . "</span> (";
+    print "</li>";
+    $count = 0;
+    foreach $parameter (@{$args{'parameterlist'}}) {
+	print "<li class=\"indent\">";
+	$type = $args{'parametertypes'}{$parameter};
+	if ($type =~ m/([^\(]*\(\*)\s*\)\s*\(([^\)]*)\)/) {
+	    # pointer-to-function
+	    print "<span class=\"type\">$1</span> ";
+	    print "<span class=\"param\">$parameter</span>";
+	    print "<span class=\"type\">)</span> ";
+	    print "(<span class=\"args\">$2</span>)";
+	} else {
+	    print "<span class=\"type\">$type</span> ";
+	    print "<span class=\"param\">$parameter</span>";
+	}
+	if ($count != $#{$args{'parameterlist'}}) {
+	    $count++;
+	    print ",";
+	}
+	print "</li>\n";
+    }
+    print "<li>)</li>\n";
+    print "</ol>\n";
+
+    print "<section>\n";
+    print "<h1>Arguments</h1>\n";
+    print "<p>\n";
+    print "<dl>\n";
+    foreach $parameter (@{$args{'parameterlist'}}) {
+	my $parameter_name = $parameter;
+	$parameter_name =~ s/\[.*//;
+
+	($args{'parameterdescs'}{$parameter_name} ne $undescribed) || next;
+	print "<dt>" . $parameter . "</dt>\n";
+	print "<dd>";
+	output_highlight($args{'parameterdescs'}{$parameter_name});
+	print "</dd>\n";
+    }
+    print "</dl>\n";
+    print "</section>\n";
+    output_section_html5(@_);
+    print "</article>\n";
+}
+
+# output DOC: block header in html5
+sub output_blockhead_html5(%) {
+    my %args = %{$_[0]};
+    my ($parameter, $section);
+    my $count;
+    my $html5id;
+
+    foreach $section (@{$args{'sectionlist'}}) {
+	$html5id = $section;
+	$html5id =~ s/[^a-zA-Z0-9\-]+/_/g;
+	print "<article class=\"doc\" id=\"doc:". $html5id . "\">\n";
+	print "<h1>$section</h1>\n";
+	print "<p>\n";
+	output_highlight($args{'sections'}{$section});
+	print "</p>\n";
+    }
+    print "</article>\n";
+}
+
+sub output_section_xml(%) {
+    my %args = %{$_[0]};
+    my $section;
+    # print out each section
+    $lineprefix="   ";
+    foreach $section (@{$args{'sectionlist'}}) {
+	print "<refsect1>\n";
+	print "<title>$section</title>\n";
+	if ($section =~ m/EXAMPLE/i) {
+	    print "<informalexample><programlisting>\n";
+	    $output_preformatted = 1;
+	} else {
+	    print "<para>\n";
+	}
+	output_highlight($args{'sections'}{$section});
+	$output_preformatted = 0;
+	if ($section =~ m/EXAMPLE/i) {
+	    print "</programlisting></informalexample>\n";
+	} else {
+	    print "</para>\n";
+	}
+	print "</refsect1>\n";
+    }
+}
+
+# output function in XML DocBook
+sub output_function_xml(%) {
+    my %args = %{$_[0]};
+    my ($parameter, $section);
+    my $count;
+    my $id;
+
+    $id = "API-" . $args{'function'};
+    $id =~ s/[^A-Za-z0-9]/-/g;
+
+    print "<refentry id=\"$id\">\n";
+    print "<refentryinfo>\n";
+    print " <title>U-BOOT</title>\n";
+    print " <productname>Bootloader Hackers Manual</productname>\n";
+    print " <date>$man_date</date>\n";
+    print "</refentryinfo>\n";
+    print "<refmeta>\n";
+    print " <refentrytitle><phrase>" . $args{'function'} . "</phrase></refentrytitle>\n";
+    print " <manvolnum>9</manvolnum>\n";
+    print " <refmiscinfo class=\"version\">" . $kernelversion . "</refmiscinfo>\n";
+    print "</refmeta>\n";
+    print "<refnamediv>\n";
+    print " <refname>" . $args{'function'} . "</refname>\n";
+    print " <refpurpose>\n";
+    print "  ";
+    output_highlight ($args{'purpose'});
+    print " </refpurpose>\n";
+    print "</refnamediv>\n";
+
+    print "<refsynopsisdiv>\n";
+    print " <title>Synopsis</title>\n";
+    print "  <funcsynopsis><funcprototype>\n";
+    print "   <funcdef>" . $args{'functiontype'} . " ";
+    print "<function>" . $args{'function'} . " </function></funcdef>\n";
+
+    $count = 0;
+    if ($#{$args{'parameterlist'}} >= 0) {
+	foreach $parameter (@{$args{'parameterlist'}}) {
+	    $type = $args{'parametertypes'}{$parameter};
+	    if ($type =~ m/([^\(]*\(\*)\s*\)\s*\(([^\)]*)\)/) {
+		# pointer-to-function
+		print "   <paramdef>$1<parameter>$parameter</parameter>)\n";
+		print "     <funcparams>$2</funcparams></paramdef>\n";
+	    } else {
+		print "   <paramdef>" . $type;
+		print " <parameter>$parameter</parameter></paramdef>\n";
+	    }
+	}
+    } else {
+	print "  <void/>\n";
+    }
+    print "  </funcprototype></funcsynopsis>\n";
+    print "</refsynopsisdiv>\n";
+
+    # print parameters
+    print "<refsect1>\n <title>Arguments</title>\n";
+    if ($#{$args{'parameterlist'}} >= 0) {
+	print " <variablelist>\n";
+	foreach $parameter (@{$args{'parameterlist'}}) {
+	    my $parameter_name = $parameter;
+	    $parameter_name =~ s/\[.*//;
+
+	    print "  <varlistentry>\n   <term><parameter>$parameter</parameter></term>\n";
+	    print "   <listitem>\n    <para>\n";
+	    $lineprefix="     ";
+	    output_highlight($args{'parameterdescs'}{$parameter_name});
+	    print "    </para>\n   </listitem>\n  </varlistentry>\n";
+	}
+	print " </variablelist>\n";
+    } else {
+	print " <para>\n  None\n </para>\n";
+    }
+    print "</refsect1>\n";
+
+    output_section_xml(@_);
+    print "</refentry>\n\n";
+}
+
+# output struct in XML DocBook
+sub output_struct_xml(%) {
+    my %args = %{$_[0]};
+    my ($parameter, $section);
+    my $id;
+
+    $id = "API-struct-" . $args{'struct'};
+    $id =~ s/[^A-Za-z0-9]/-/g;
+
+    print "<refentry id=\"$id\">\n";
+    print "<refentryinfo>\n";
+    print " <title>U-BOOT</title>\n";
+    print " <productname>Bootloader Hackers Manual</productname>\n";
+    print " <date>$man_date</date>\n";
+    print "</refentryinfo>\n";
+    print "<refmeta>\n";
+    print " <refentrytitle><phrase>" . $args{'type'} . " " . $args{'struct'} . "</phrase></refentrytitle>\n";
+    print " <manvolnum>9</manvolnum>\n";
+    print " <refmiscinfo class=\"version\">" . $kernelversion . "</refmiscinfo>\n";
+    print "</refmeta>\n";
+    print "<refnamediv>\n";
+    print " <refname>" . $args{'type'} . " " . $args{'struct'} . "</refname>\n";
+    print " <refpurpose>\n";
+    print "  ";
+    output_highlight ($args{'purpose'});
+    print " </refpurpose>\n";
+    print "</refnamediv>\n";
+
+    print "<refsynopsisdiv>\n";
+    print " <title>Synopsis</title>\n";
+    print "  <programlisting>\n";
+    print $args{'type'} . " " . $args{'struct'} . " {\n";
+    foreach $parameter (@{$args{'parameterlist'}}) {
+	if ($parameter =~ /^#/) {
+	    my $prm = $parameter;
+	    # convert data read & converted thru xml_escape() into &xyz; format:
+	    # This allows us to have #define macros interspersed in a struct.
+	    $prm =~ s/\\\\\\/\&/g;
+	    print "$prm\n";
+	    next;
+	}
+
+	my $parameter_name = $parameter;
+	$parameter_name =~ s/\[.*//;
+
+	defined($args{'parameterdescs'}{$parameter_name}) || next;
+	($args{'parameterdescs'}{$parameter_name} ne $undescribed) || next;
+	$type = $args{'parametertypes'}{$parameter};
+	if ($type =~ m/([^\(]*\(\*)\s*\)\s*\(([^\)]*)\)/) {
+	    # pointer-to-function
+	    print "  $1 $parameter) ($2);\n";
+	} elsif ($type =~ m/^(.*?)\s*(:.*)/) {
+	    # bitfield
+	    print "  $1 $parameter$2;\n";
+	} else {
+	    print "  " . $type . " " . $parameter . ";\n";
+	}
+    }
+    print "};";
+    print "  </programlisting>\n";
+    print "</refsynopsisdiv>\n";
+
+    print " <refsect1>\n";
+    print "  <title>Members</title>\n";
+
+    if ($#{$args{'parameterlist'}} >= 0) {
+    print "  <variablelist>\n";
+    foreach $parameter (@{$args{'parameterlist'}}) {
+      ($parameter =~ /^#/) && next;
+
+      my $parameter_name = $parameter;
+      $parameter_name =~ s/\[.*//;
+
+      defined($args{'parameterdescs'}{$parameter_name}) || next;
+      ($args{'parameterdescs'}{$parameter_name} ne $undescribed) || next;
+      print "    <varlistentry>";
+      print "      <term>$parameter</term>\n";
+      print "      <listitem><para>\n";
+      output_highlight($args{'parameterdescs'}{$parameter_name});
+      print "      </para></listitem>\n";
+      print "    </varlistentry>\n";
+    }
+    print "  </variablelist>\n";
+    } else {
+	print " <para>\n  None\n </para>\n";
+    }
+    print " </refsect1>\n";
+
+    output_section_xml(@_);
+
+    print "</refentry>\n\n";
+}
+
+# output enum in XML DocBook
+sub output_enum_xml(%) {
+    my %args = %{$_[0]};
+    my ($parameter, $section);
+    my $count;
+    my $id;
+
+    $id = "API-enum-" . $args{'enum'};
+    $id =~ s/[^A-Za-z0-9]/-/g;
+
+    print "<refentry id=\"$id\">\n";
+    print "<refentryinfo>\n";
+    print " <title>U-BOOT</title>\n";
+    print " <productname>Bootloader Hackers Manual</productname>\n";
+    print " <date>$man_date</date>\n";
+    print "</refentryinfo>\n";
+    print "<refmeta>\n";
+    print " <refentrytitle><phrase>enum " . $args{'enum'} . "</phrase></refentrytitle>\n";
+    print " <manvolnum>9</manvolnum>\n";
+    print " <refmiscinfo class=\"version\">" . $kernelversion . "</refmiscinfo>\n";
+    print "</refmeta>\n";
+    print "<refnamediv>\n";
+    print " <refname>enum " . $args{'enum'} . "</refname>\n";
+    print " <refpurpose>\n";
+    print "  ";
+    output_highlight ($args{'purpose'});
+    print " </refpurpose>\n";
+    print "</refnamediv>\n";
+
+    print "<refsynopsisdiv>\n";
+    print " <title>Synopsis</title>\n";
+    print "  <programlisting>\n";
+    print "enum " . $args{'enum'} . " {\n";
+    $count = 0;
+    foreach $parameter (@{$args{'parameterlist'}}) {
+	print "  $parameter";
+	if ($count != $#{$args{'parameterlist'}}) {
+	    $count++;
+	    print ",";
+	}
+	print "\n";
+    }
+    print "};";
+    print "  </programlisting>\n";
+    print "</refsynopsisdiv>\n";
+
+    print "<refsect1>\n";
+    print " <title>Constants</title>\n";
+    print "  <variablelist>\n";
+    foreach $parameter (@{$args{'parameterlist'}}) {
+      my $parameter_name = $parameter;
+      $parameter_name =~ s/\[.*//;
+
+      print "    <varlistentry>";
+      print "      <term>$parameter</term>\n";
+      print "      <listitem><para>\n";
+      output_highlight($args{'parameterdescs'}{$parameter_name});
+      print "      </para></listitem>\n";
+      print "    </varlistentry>\n";
+    }
+    print "  </variablelist>\n";
+    print "</refsect1>\n";
+
+    output_section_xml(@_);
+
+    print "</refentry>\n\n";
+}
+
+# output typedef in XML DocBook
+sub output_typedef_xml(%) {
+    my %args = %{$_[0]};
+    my ($parameter, $section);
+    my $id;
+
+    $id = "API-typedef-" . $args{'typedef'};
+    $id =~ s/[^A-Za-z0-9]/-/g;
+
+    print "<refentry id=\"$id\">\n";
+    print "<refentryinfo>\n";
+    print " <title>U-BOOT</title>\n";
+    print " <productname>Bootloader Hackers Manual</productname>\n";
+    print " <date>$man_date</date>\n";
+    print "</refentryinfo>\n";
+    print "<refmeta>\n";
+    print " <refentrytitle><phrase>typedef " . $args{'typedef'} . "</phrase></refentrytitle>\n";
+    print " <manvolnum>9</manvolnum>\n";
+    print "</refmeta>\n";
+    print "<refnamediv>\n";
+    print " <refname>typedef " . $args{'typedef'} . "</refname>\n";
+    print " <refpurpose>\n";
+    print "  ";
+    output_highlight ($args{'purpose'});
+    print " </refpurpose>\n";
+    print "</refnamediv>\n";
+
+    print "<refsynopsisdiv>\n";
+    print " <title>Synopsis</title>\n";
+    print "  <synopsis>typedef " . $args{'typedef'} . ";</synopsis>\n";
+    print "</refsynopsisdiv>\n";
+
+    output_section_xml(@_);
+
+    print "</refentry>\n\n";
+}
+
+# output in XML DocBook
+sub output_blockhead_xml(%) {
+    my %args = %{$_[0]};
+    my ($parameter, $section);
+    my $count;
+
+    my $id = $args{'module'};
+    $id =~ s/[^A-Za-z0-9]/-/g;
+
+    # print out each section
+    $lineprefix="   ";
+    foreach $section (@{$args{'sectionlist'}}) {
+	if (!$args{'content-only'}) {
+		print "<refsect1>\n <title>$section</title>\n";
+	}
+	if ($section =~ m/EXAMPLE/i) {
+	    print "<example><para>\n";
+	    $output_preformatted = 1;
+	} else {
+	    print "<para>\n";
+	}
+	output_highlight($args{'sections'}{$section});
+	$output_preformatted = 0;
+	if ($section =~ m/EXAMPLE/i) {
+	    print "</para></example>\n";
+	} else {
+	    print "</para>";
+	}
+	if (!$args{'content-only'}) {
+		print "\n</refsect1>\n";
+	}
+    }
+
+    print "\n\n";
+}
+
+# output in XML DocBook
+sub output_function_gnome {
+    my %args = %{$_[0]};
+    my ($parameter, $section);
+    my $count;
+    my $id;
+
+    $id = $args{'module'} . "-" . $args{'function'};
+    $id =~ s/[^A-Za-z0-9]/-/g;
+
+    print "<sect2>\n";
+    print " <title id=\"$id\">" . $args{'function'} . "</title>\n";
+
+    print "  <funcsynopsis>\n";
+    print "   <funcdef>" . $args{'functiontype'} . " ";
+    print "<function>" . $args{'function'} . " ";
+    print "</function></funcdef>\n";
+
+    $count = 0;
+    if ($#{$args{'parameterlist'}} >= 0) {
+	foreach $parameter (@{$args{'parameterlist'}}) {
+	    $type = $args{'parametertypes'}{$parameter};
+	    if ($type =~ m/([^\(]*\(\*)\s*\)\s*\(([^\)]*)\)/) {
+		# pointer-to-function
+		print "   <paramdef>$1 <parameter>$parameter</parameter>)\n";
+		print "     <funcparams>$2</funcparams></paramdef>\n";
+	    } else {
+		print "   <paramdef>" . $type;
+		print " <parameter>$parameter</parameter></paramdef>\n";
+	    }
+	}
+    } else {
+	print "  <void>\n";
+    }
+    print "  </funcsynopsis>\n";
+    if ($#{$args{'parameterlist'}} >= 0) {
+	print " <informaltable pgwide=\"1\" frame=\"none\" role=\"params\">\n";
+	print "<tgroup cols=\"2\">\n";
+	print "<colspec colwidth=\"2*\">\n";
+	print "<colspec colwidth=\"8*\">\n";
+	print "<tbody>\n";
+	foreach $parameter (@{$args{'parameterlist'}}) {
+	    my $parameter_name = $parameter;
+	    $parameter_name =~ s/\[.*//;
+
+	    print "  <row><entry align=\"right\"><parameter>$parameter</parameter></entry>\n";
+	    print "   <entry>\n";
+	    $lineprefix="     ";
+	    output_highlight($args{'parameterdescs'}{$parameter_name});
+	    print "    </entry></row>\n";
+	}
+	print " </tbody></tgroup></informaltable>\n";
+    } else {
+	print " <para>\n  None\n </para>\n";
+    }
+
+    # print out each section
+    $lineprefix="   ";
+    foreach $section (@{$args{'sectionlist'}}) {
+	print "<simplesect>\n <title>$section</title>\n";
+	if ($section =~ m/EXAMPLE/i) {
+	    print "<example><programlisting>\n";
+	    $output_preformatted = 1;
+	} else {
+	}
+	print "<para>\n";
+	output_highlight($args{'sections'}{$section});
+	$output_preformatted = 0;
+	print "</para>\n";
+	if ($section =~ m/EXAMPLE/i) {
+	    print "</programlisting></example>\n";
+	} else {
+	}
+	print " </simplesect>\n";
+    }
+
+    print "</sect2>\n\n";
+}
+
+##
+# output function in man
+sub output_function_man(%) {
+    my %args = %{$_[0]};
+    my ($parameter, $section);
+    my $count;
+
+    print ".TH \"$args{'function'}\" 9 \"$args{'function'}\" \"$man_date\" \"Bootloader Hacker's Manual\" U-BOOT\n";
+
+    print ".SH NAME\n";
+    print $args{'function'} . " \\- " . $args{'purpose'} . "\n";
+
+    print ".SH SYNOPSIS\n";
+    if ($args{'functiontype'} ne "") {
+	print ".B \"" . $args{'functiontype'} . "\" " . $args{'function'} . "\n";
+    } else {
+	print ".B \"" . $args{'function'} . "\n";
+    }
+    $count = 0;
+    my $parenth = "(";
+    my $post = ",";
+    foreach my $parameter (@{$args{'parameterlist'}}) {
+	if ($count == $#{$args{'parameterlist'}}) {
+	    $post = ");";
+	}
+	$type = $args{'parametertypes'}{$parameter};
+	if ($type =~ m/([^\(]*\(\*)\s*\)\s*\(([^\)]*)\)/) {
+	    # pointer-to-function
+	    print ".BI \"" . $parenth . $1 . "\" " . $parameter . " \") (" . $2 . ")" . $post . "\"\n";
+	} else {
+	    $type =~ s/([^\*])$/$1 /;
+	    print ".BI \"" . $parenth . $type . "\" " . $parameter . " \"" . $post . "\"\n";
+	}
+	$count++;
+	$parenth = "";
+    }
+
+    print ".SH ARGUMENTS\n";
+    foreach $parameter (@{$args{'parameterlist'}}) {
+	my $parameter_name = $parameter;
+	$parameter_name =~ s/\[.*//;
+
+	print ".IP \"" . $parameter . "\" 12\n";
+	output_highlight($args{'parameterdescs'}{$parameter_name});
+    }
+    foreach $section (@{$args{'sectionlist'}}) {
+	print ".SH \"", uc $section, "\"\n";
+	output_highlight($args{'sections'}{$section});
+    }
+}
+
+##
+# output enum in man
+sub output_enum_man(%) {
+    my %args = %{$_[0]};
+    my ($parameter, $section);
+    my $count;
+
+    print ".TH \"$args{'module'}\" 9 \"enum $args{'enum'}\" \"$man_date\" \"API Manual\" U-BOOT\n";
+
+    print ".SH NAME\n";
+    print "enum " . $args{'enum'} . " \\- " . $args{'purpose'} . "\n";
+
+    print ".SH SYNOPSIS\n";
+    print "enum " . $args{'enum'} . " {\n";
+    $count = 0;
+    foreach my $parameter (@{$args{'parameterlist'}}) {
+	print ".br\n.BI \"    $parameter\"\n";
+	if ($count == $#{$args{'parameterlist'}}) {
+	    print "\n};\n";
+	    last;
+	}
+	else {
+	    print ", \n.br\n";
+	}
+	$count++;
+    }
+
+    print ".SH Constants\n";
+    foreach $parameter (@{$args{'parameterlist'}}) {
+	my $parameter_name = $parameter;
+	$parameter_name =~ s/\[.*//;
+
+	print ".IP \"" . $parameter . "\" 12\n";
+	output_highlight($args{'parameterdescs'}{$parameter_name});
+    }
+    foreach $section (@{$args{'sectionlist'}}) {
+	print ".SH \"$section\"\n";
+	output_highlight($args{'sections'}{$section});
+    }
+}
+
+##
+# output struct in man
+sub output_struct_man(%) {
+    my %args = %{$_[0]};
+    my ($parameter, $section);
+
+    print ".TH \"$args{'module'}\" 9 \"" . $args{'type'} . " " . $args{'struct'} . "\" \"$man_date\" \"API Manual\" U-BOOT\n";
+
+    print ".SH NAME\n";
+    print $args{'type'} . " " . $args{'struct'} . " \\- " . $args{'purpose'} . "\n";
+
+    print ".SH SYNOPSIS\n";
+    print $args{'type'} . " " . $args{'struct'} . " {\n.br\n";
+
+    foreach my $parameter (@{$args{'parameterlist'}}) {
+	if ($parameter =~ /^#/) {
+	    print ".BI \"$parameter\"\n.br\n";
+	    next;
+	}
+	my $parameter_name = $parameter;
+	$parameter_name =~ s/\[.*//;
+
+	($args{'parameterdescs'}{$parameter_name} ne $undescribed) || next;
+	$type = $args{'parametertypes'}{$parameter};
+	if ($type =~ m/([^\(]*\(\*)\s*\)\s*\(([^\)]*)\)/) {
+	    # pointer-to-function
+	    print ".BI \"    " . $1 . "\" " . $parameter . " \") (" . $2 . ")" . "\"\n;\n";
+	} elsif ($type =~ m/^(.*?)\s*(:.*)/) {
+	    # bitfield
+	    print ".BI \"    " . $1 . "\ \" " . $parameter . $2 . " \"" . "\"\n;\n";
+	} else {
+	    $type =~ s/([^\*])$/$1 /;
+	    print ".BI \"    " . $type . "\" " . $parameter . " \"" . "\"\n;\n";
+	}
+	print "\n.br\n";
+    }
+    print "};\n.br\n";
+
+    print ".SH Members\n";
+    foreach $parameter (@{$args{'parameterlist'}}) {
+	($parameter =~ /^#/) && next;
+
+	my $parameter_name = $parameter;
+	$parameter_name =~ s/\[.*//;
+
+	($args{'parameterdescs'}{$parameter_name} ne $undescribed) || next;
+	print ".IP \"" . $parameter . "\" 12\n";
+	output_highlight($args{'parameterdescs'}{$parameter_name});
+    }
+    foreach $section (@{$args{'sectionlist'}}) {
+	print ".SH \"$section\"\n";
+	output_highlight($args{'sections'}{$section});
+    }
+}
+
+##
+# output typedef in man
+sub output_typedef_man(%) {
+    my %args = %{$_[0]};
+    my ($parameter, $section);
+
+    print ".TH \"$args{'module'}\" 9 \"$args{'typedef'}\" \"$man_date\" \"API Manual\" U-BOOT\n";
+
+    print ".SH NAME\n";
+    print "typedef " . $args{'typedef'} . " \\- " . $args{'purpose'} . "\n";
+
+    foreach $section (@{$args{'sectionlist'}}) {
+	print ".SH \"$section\"\n";
+	output_highlight($args{'sections'}{$section});
+    }
+}
+
+sub output_blockhead_man(%) {
+    my %args = %{$_[0]};
+    my ($parameter, $section);
+    my $count;
+
+    print ".TH \"$args{'module'}\" 9 \"$args{'module'}\" \"$man_date\" \"API Manual\" U-BOOT\n";
+
+    foreach $section (@{$args{'sectionlist'}}) {
+	print ".SH \"$section\"\n";
+	output_highlight($args{'sections'}{$section});
+    }
+}
+
+##
+# output in text
+sub output_function_text(%) {
+    my %args = %{$_[0]};
+    my ($parameter, $section);
+    my $start;
+
+    print "Name:\n\n";
+    print $args{'function'} . " - " . $args{'purpose'} . "\n";
+
+    print "\nSynopsis:\n\n";
+    if ($args{'functiontype'} ne "") {
+	$start = $args{'functiontype'} . " " . $args{'function'} . " (";
+    } else {
+	$start = $args{'function'} . " (";
+    }
+    print $start;
+
+    my $count = 0;
+    foreach my $parameter (@{$args{'parameterlist'}}) {
+	$type = $args{'parametertypes'}{$parameter};
+	if ($type =~ m/([^\(]*\(\*)\s*\)\s*\(([^\)]*)\)/) {
+	    # pointer-to-function
+	    print $1 . $parameter . ") (" . $2;
+	} else {
+	    print $type . " " . $parameter;
+	}
+	if ($count != $#{$args{'parameterlist'}}) {
+	    $count++;
+	    print ",\n";
+	    print " " x length($start);
+	} else {
+	    print ");\n\n";
+	}
+    }
+
+    print "Arguments:\n\n";
+    foreach $parameter (@{$args{'parameterlist'}}) {
+	my $parameter_name = $parameter;
+	$parameter_name =~ s/\[.*//;
+
+	print $parameter . "\n\t" . $args{'parameterdescs'}{$parameter_name} . "\n";
+    }
+    output_section_text(@_);
+}
+
+#output sections in text
+sub output_section_text(%) {
+    my %args = %{$_[0]};
+    my $section;
+
+    print "\n";
+    foreach $section (@{$args{'sectionlist'}}) {
+	print "$section:\n\n";
+	output_highlight($args{'sections'}{$section});
+    }
+    print "\n\n";
+}
+
+# output enum in text
+sub output_enum_text(%) {
+    my %args = %{$_[0]};
+    my ($parameter);
+    my $count;
+    print "Enum:\n\n";
+
+    print "enum " . $args{'enum'} . " - " . $args{'purpose'} . "\n\n";
+    print "enum " . $args{'enum'} . " {\n";
+    $count = 0;
+    foreach $parameter (@{$args{'parameterlist'}}) {
+	print "\t$parameter";
+	if ($count != $#{$args{'parameterlist'}}) {
+	    $count++;
+	    print ",";
+	}
+	print "\n";
+    }
+    print "};\n\n";
+
+    print "Constants:\n\n";
+    foreach $parameter (@{$args{'parameterlist'}}) {
+	print "$parameter\n\t";
+	print $args{'parameterdescs'}{$parameter} . "\n";
+    }
+
+    output_section_text(@_);
+}
+
+# output typedef in text
+sub output_typedef_text(%) {
+    my %args = %{$_[0]};
+    my ($parameter);
+    my $count;
+    print "Typedef:\n\n";
+
+    print "typedef " . $args{'typedef'} . " - " . $args{'purpose'} . "\n";
+    output_section_text(@_);
+}
+
+# output struct as text
+sub output_struct_text(%) {
+    my %args = %{$_[0]};
+    my ($parameter);
+
+    print $args{'type'} . " " . $args{'struct'} . " - " . $args{'purpose'} . "\n\n";
+    print $args{'type'} . " " . $args{'struct'} . " {\n";
+    foreach $parameter (@{$args{'parameterlist'}}) {
+	if ($parameter =~ /^#/) {
+	    print "$parameter\n";
+	    next;
+	}
+
+	my $parameter_name = $parameter;
+	$parameter_name =~ s/\[.*//;
+
+	($args{'parameterdescs'}{$parameter_name} ne $undescribed) || next;
+	$type = $args{'parametertypes'}{$parameter};
+	if ($type =~ m/([^\(]*\(\*)\s*\)\s*\(([^\)]*)\)/) {
+	    # pointer-to-function
+	    print "\t$1 $parameter) ($2);\n";
+	} elsif ($type =~ m/^(.*?)\s*(:.*)/) {
+	    # bitfield
+	    print "\t$1 $parameter$2;\n";
+	} else {
+	    print "\t" . $type . " " . $parameter . ";\n";
+	}
+    }
+    print "};\n\n";
+
+    print "Members:\n\n";
+    foreach $parameter (@{$args{'parameterlist'}}) {
+	($parameter =~ /^#/) && next;
+
+	my $parameter_name = $parameter;
+	$parameter_name =~ s/\[.*//;
+
+	($args{'parameterdescs'}{$parameter_name} ne $undescribed) || next;
+	print "$parameter\n\t";
+	print $args{'parameterdescs'}{$parameter_name} . "\n";
+    }
+    print "\n";
+    output_section_text(@_);
+}
+
+sub output_blockhead_text(%) {
+    my %args = %{$_[0]};
+    my ($parameter, $section);
+
+    foreach $section (@{$args{'sectionlist'}}) {
+	print " $section:\n";
+	print "    -> ";
+	output_highlight($args{'sections'}{$section});
+    }
+}
+
+## list mode output functions
+
+sub output_function_list(%) {
+    my %args = %{$_[0]};
+
+    print $args{'function'} . "\n";
+}
+
+# output enum in list
+sub output_enum_list(%) {
+    my %args = %{$_[0]};
+    print $args{'enum'} . "\n";
+}
+
+# output typedef in list
+sub output_typedef_list(%) {
+    my %args = %{$_[0]};
+    print $args{'typedef'} . "\n";
+}
+
+# output struct as list
+sub output_struct_list(%) {
+    my %args = %{$_[0]};
+
+    print $args{'struct'} . "\n";
+}
+
+sub output_blockhead_list(%) {
+    my %args = %{$_[0]};
+    my ($parameter, $section);
+
+    foreach $section (@{$args{'sectionlist'}}) {
+	print "DOC: $section\n";
+    }
+}
+
+##
+# generic output function for all types (function, struct/union, typedef, enum);
+# calls the generated, variable output_ function name based on
+# functype and output_mode
+sub output_declaration {
+    no strict 'refs';
+    my $name = shift;
+    my $functype = shift;
+    my $func = "output_${functype}_$output_mode";
+    if (($function_only==0) ||
+	( $function_only == 1 && defined($function_table{$name})) ||
+	( $function_only == 2 && !defined($function_table{$name})))
+    {
+	&$func(@_);
+	$section_counter++;
+    }
+}
+
+##
+# generic output function - calls the right one based on current output mode.
+sub output_blockhead {
+    no strict 'refs';
+    my $func = "output_blockhead_" . $output_mode;
+    &$func(@_);
+    $section_counter++;
+}
+
+##
+# takes a declaration (struct, union, enum, typedef) and
+# invokes the right handler. NOT called for functions.
+sub dump_declaration($$) {
+    no strict 'refs';
+    my ($prototype, $file) = @_;
+    my $func = "dump_" . $decl_type;
+    &$func(@_);
+}
+
+sub dump_union($$) {
+    dump_struct(@_);
+}
+
+sub dump_struct($$) {
+    my $x = shift;
+    my $file = shift;
+    my $nested;
+
+    if ($x =~ /(struct|union)\s+(\w+)\s*{(.*)}/) {
+	#my $decl_type = $1;
+	$declaration_name = $2;
+	my $members = $3;
+
+	# ignore embedded structs or unions
+	$members =~ s/({.*})//g;
+	$nested = $1;
+
+	# ignore members marked private:
+	$members =~ s/\/\*\s*private:.*?\/\*\s*public:.*?\*\///gos;
+	$members =~ s/\/\*\s*private:.*//gos;
+	# strip comments:
+	$members =~ s/\/\*.*?\*\///gos;
+	$nested =~ s/\/\*.*?\*\///gos;
+	# strip kmemcheck_bitfield_{begin,end}.*;
+	$members =~ s/kmemcheck_bitfield_.*?;//gos;
+	# strip attributes
+	$members =~ s/__aligned\s*\(.+\)//gos;
+
+	create_parameterlist($members, ';', $file);
+	check_sections($file, $declaration_name, "struct", $sectcheck, $struct_actual, $nested);
+
+	output_declaration($declaration_name,
+			   'struct',
+			   {'struct' => $declaration_name,
+			    'module' => $modulename,
+			    'parameterlist' => \@parameterlist,
+			    'parameterdescs' => \%parameterdescs,
+			    'parametertypes' => \%parametertypes,
+			    'sectionlist' => \@sectionlist,
+			    'sections' => \%sections,
+			    'purpose' => $declaration_purpose,
+			    'type' => $decl_type
+			   });
+    }
+    else {
+	print STDERR "Error(${file}:$.): Cannot parse struct or union!\n";
+	++$errors;
+    }
+}
+
+sub dump_enum($$) {
+    my $x = shift;
+    my $file = shift;
+
+    $x =~ s@/\*.*?\*/@@gos;	# strip comments.
+    $x =~ s/^#\s*define\s+.*$//; # strip #define macros inside enums
+
+    if ($x =~ /enum\s+(\w+)\s*{(.*)}/) {
+	$declaration_name = $1;
+	my $members = $2;
+
+	foreach my $arg (split ',', $members) {
+	    $arg =~ s/^\s*(\w+).*/$1/;
+	    push @parameterlist, $arg;
+	    if (!$parameterdescs{$arg}) {
+		$parameterdescs{$arg} = $undescribed;
+		print STDERR "Warning(${file}:$.): Enum value '$arg' ".
+		    "not described in enum '$declaration_name'\n";
+	    }
+
+	}
+
+	output_declaration($declaration_name,
+			   'enum',
+			   {'enum' => $declaration_name,
+			    'module' => $modulename,
+			    'parameterlist' => \@parameterlist,
+			    'parameterdescs' => \%parameterdescs,
+			    'sectionlist' => \@sectionlist,
+			    'sections' => \%sections,
+			    'purpose' => $declaration_purpose
+			   });
+    }
+    else {
+	print STDERR "Error(${file}:$.): Cannot parse enum!\n";
+	++$errors;
+    }
+}
+
+sub dump_typedef($$) {
+    my $x = shift;
+    my $file = shift;
+
+    $x =~ s@/\*.*?\*/@@gos;	# strip comments.
+    while (($x =~ /\(*.\)\s*;$/) || ($x =~ /\[*.\]\s*;$/)) {
+	$x =~ s/\(*.\)\s*;$/;/;
+	$x =~ s/\[*.\]\s*;$/;/;
+    }
+
+    if ($x =~ /typedef.*\s+(\w+)\s*;/) {
+	$declaration_name = $1;
+
+	output_declaration($declaration_name,
+			   'typedef',
+			   {'typedef' => $declaration_name,
+			    'module' => $modulename,
+			    'sectionlist' => \@sectionlist,
+			    'sections' => \%sections,
+			    'purpose' => $declaration_purpose
+			   });
+    }
+    else {
+	print STDERR "Error(${file}:$.): Cannot parse typedef!\n";
+	++$errors;
+    }
+}
+
+sub save_struct_actual($) {
+    my $actual = shift;
+
+    # strip all spaces from the actual param so that it looks like one string item
+    $actual =~ s/\s*//g;
+    $struct_actual = $struct_actual . $actual . " ";
+}
+
+sub create_parameterlist($$$) {
+    my $args = shift;
+    my $splitter = shift;
+    my $file = shift;
+    my $type;
+    my $param;
+
+    # temporarily replace commas inside function pointer definition
+    while ($args =~ /(\([^\),]+),/) {
+	$args =~ s/(\([^\),]+),/$1#/g;
+    }
+
+    foreach my $arg (split($splitter, $args)) {
+	# strip comments
+	$arg =~ s/\/\*.*\*\///;
+	# strip leading/trailing spaces
+	$arg =~ s/^\s*//;
+	$arg =~ s/\s*$//;
+	$arg =~ s/\s+/ /;
+
+	if ($arg =~ /^#/) {
+	    # Treat preprocessor directive as a typeless variable just to fill
+	    # corresponding data structures "correctly". Catch it later in
+	    # output_* subs.
+	    push_parameter($arg, "", $file);
+	} elsif ($arg =~ m/\(.+\)\s*\(/) {
+	    # pointer-to-function
+	    $arg =~ tr/#/,/;
+	    $arg =~ m/[^\(]+\(\*?\s*(\w*)\s*\)/;
+	    $param = $1;
+	    $type = $arg;
+	    $type =~ s/([^\(]+\(\*?)\s*$param/$1/;
+	    save_struct_actual($param);
+	    push_parameter($param, $type, $file);
+	} elsif ($arg) {
+	    $arg =~ s/\s*:\s*/:/g;
+	    $arg =~ s/\s*\[/\[/g;
+
+	    my @args = split('\s*,\s*', $arg);
+	    if ($args[0] =~ m/\*/) {
+		$args[0] =~ s/(\*+)\s*/ $1/;
+	    }
+
+	    my @first_arg;
+	    if ($args[0] =~ /^(.*\s+)(.*?\[.*\].*)$/) {
+		    shift @args;
+		    push(@first_arg, split('\s+', $1));
+		    push(@first_arg, $2);
+	    } else {
+		    @first_arg = split('\s+', shift @args);
+	    }
+
+	    unshift(@args, pop @first_arg);
+	    $type = join " ", @first_arg;
+
+	    foreach $param (@args) {
+		if ($param =~ m/^(\*+)\s*(.*)/) {
+		    save_struct_actual($2);
+		    push_parameter($2, "$type $1", $file);
+		}
+		elsif ($param =~ m/(.*?):(\d+)/) {
+		    if ($type ne "") { # skip unnamed bit-fields
+			save_struct_actual($1);
+			push_parameter($1, "$type:$2", $file)
+		    }
+		}
+		else {
+		    save_struct_actual($param);
+		    push_parameter($param, $type, $file);
+		}
+	    }
+	}
+    }
+}
+
+sub push_parameter($$$) {
+	my $param = shift;
+	my $type = shift;
+	my $file = shift;
+
+	if (($anon_struct_union == 1) && ($type eq "") &&
+	    ($param eq "}")) {
+		return;		# ignore the ending }; from anon. struct/union
+	}
+
+	$anon_struct_union = 0;
+	my $param_name = $param;
+	$param_name =~ s/\[.*//;
+
+	if ($type eq "" && $param =~ /\.\.\.$/)
+	{
+	    if (!defined $parameterdescs{$param} || $parameterdescs{$param} eq "") {
+		$parameterdescs{$param} = "variable arguments";
+	    }
+	}
+	elsif ($type eq "" && ($param eq "" or $param eq "void"))
+	{
+	    $param="void";
+	    $parameterdescs{void} = "no arguments";
+	}
+	elsif ($type eq "" && ($param eq "struct" or $param eq "union"))
+	# handle unnamed (anonymous) union or struct:
+	{
+		$type = $param;
+		$param = "{unnamed_" . $param . "}";
+		$parameterdescs{$param} = "anonymous\n";
+		$anon_struct_union = 1;
+	}
+
+	# warn if parameter has no description
+	# (but ignore ones starting with # as these are not parameters
+	# but inline preprocessor statements);
+	# also ignore unnamed structs/unions;
+	if (!$anon_struct_union) {
+	if (!defined $parameterdescs{$param_name} && $param_name !~ /^#/) {
+
+	    $parameterdescs{$param_name} = $undescribed;
+
+	    if (($type eq 'function') || ($type eq 'enum')) {
+		print STDERR "Warning(${file}:$.): Function parameter ".
+		    "or member '$param' not " .
+		    "described in '$declaration_name'\n";
+	    }
+	    print STDERR "Warning(${file}:$.):" .
+			 " No description found for parameter '$param'\n";
+	    ++$warnings;
+	}
+	}
+
+	$param = xml_escape($param);
+
+	# strip spaces from $param so that it is one continuous string
+	# on @parameterlist;
+	# this fixes a problem where check_sections() cannot find
+	# a parameter like "addr[6 + 2]" because it actually appears
+	# as "addr[6", "+", "2]" on the parameter list;
+	# but it's better to maintain the param string unchanged for output,
+	# so just weaken the string compare in check_sections() to ignore
+	# "[blah" in a parameter string;
+	###$param =~ s/\s*//g;
+	push @parameterlist, $param;
+	$parametertypes{$param} = $type;
+}
+
+sub check_sections($$$$$$) {
+	my ($file, $decl_name, $decl_type, $sectcheck, $prmscheck, $nested) = @_;
+	my @sects = split ' ', $sectcheck;
+	my @prms = split ' ', $prmscheck;
+	my $err;
+	my ($px, $sx);
+	my $prm_clean;		# strip trailing "[array size]" and/or beginning "*"
+
+	foreach $sx (0 .. $#sects) {
+		$err = 1;
+		foreach $px (0 .. $#prms) {
+			$prm_clean = $prms[$px];
+			$prm_clean =~ s/\[.*\]//;
+			$prm_clean =~ s/__attribute__\s*\(\([a-z,_\*\s\(\)]*\)\)//i;
+			# ignore array size in a parameter string;
+			# however, the original param string may contain
+			# spaces, e.g.:  addr[6 + 2]
+			# and this appears in @prms as "addr[6" since the
+			# parameter list is split at spaces;
+			# hence just ignore "[..." for the sections check;
+			$prm_clean =~ s/\[.*//;
+
+			##$prm_clean =~ s/^\**//;
+			if ($prm_clean eq $sects[$sx]) {
+				$err = 0;
+				last;
+			}
+		}
+		if ($err) {
+			if ($decl_type eq "function") {
+				print STDERR "Warning(${file}:$.): " .
+					"Excess function parameter " .
+					"'$sects[$sx]' " .
+					"description in '$decl_name'\n";
+				++$warnings;
+			} else {
+				if ($nested !~ m/\Q$sects[$sx]\E/) {
+				    print STDERR "Warning(${file}:$.): " .
+					"Excess struct/union/enum/typedef member " .
+					"'$sects[$sx]' " .
+					"description in '$decl_name'\n";
+				    ++$warnings;
+				}
+			}
+		}
+	}
+}
+
+##
+# Checks the section describing the return value of a function.
+sub check_return_section {
+        my $file = shift;
+        my $declaration_name = shift;
+        my $return_type = shift;
+
+        # Ignore an empty return type (It's a macro)
+        # Ignore functions with a "void" return type. (But don't ignore "void *")
+        if (($return_type eq "") || ($return_type =~ /void\s*\w*\s*$/)) {
+                return;
+        }
+
+        if (!defined($sections{$section_return}) ||
+            $sections{$section_return} eq "") {
+                print STDERR "Warning(${file}:$.): " .
+                        "No description found for return value of " .
+                        "'$declaration_name'\n";
+                ++$warnings;
+        }
+}
+
+##
+# takes a function prototype and the name of the current file being
+# processed and spits out all the details stored in the global
+# arrays/hashes.
+sub dump_function($$) {
+    my $prototype = shift;
+    my $file = shift;
+
+    $prototype =~ s/^static +//;
+    $prototype =~ s/^extern +//;
+    $prototype =~ s/^asmlinkage +//;
+    $prototype =~ s/^inline +//;
+    $prototype =~ s/^__inline__ +//;
+    $prototype =~ s/^__inline +//;
+    $prototype =~ s/^__always_inline +//;
+    $prototype =~ s/^noinline +//;
+    $prototype =~ s/__init +//;
+    $prototype =~ s/__init_or_module +//;
+    $prototype =~ s/__must_check +//;
+    $prototype =~ s/__weak +//;
+    $prototype =~ s/^#\s*define\s+//; #ak added
+    $prototype =~ s/__attribute__\s*\(\([a-z,]*\)\)//;
+
+    # Yes, this truly is vile.  We are looking for:
+    # 1. Return type (may be nothing if we're looking at a macro)
+    # 2. Function name
+    # 3. Function parameters.
+    #
+    # All the while we have to watch out for function pointer parameters
+    # (which IIRC is what the two sections are for), C types (these
+    # regexps don't even start to express all the possibilities), and
+    # so on.
+    #
+    # If you mess with these regexps, it's a good idea to check that
+    # the following functions' documentation still comes out right:
+    # - parport_register_device (function pointer parameters)
+    # - atomic_set (macro)
+    # - pci_match_device, __copy_to_user (long return type)
+
+    if ($prototype =~ m/^()([a-zA-Z0-9_~:]+)\s*\(([^\(]*)\)/ ||
+	$prototype =~ m/^(\w+)\s+([a-zA-Z0-9_~:]+)\s*\(([^\(]*)\)/ ||
+	$prototype =~ m/^(\w+\s*\*)\s*([a-zA-Z0-9_~:]+)\s*\(([^\(]*)\)/ ||
+	$prototype =~ m/^(\w+\s+\w+)\s+([a-zA-Z0-9_~:]+)\s*\(([^\(]*)\)/ ||
+	$prototype =~ m/^(\w+\s+\w+\s*\*+)\s*([a-zA-Z0-9_~:]+)\s*\(([^\(]*)\)/ ||
+	$prototype =~ m/^(\w+\s+\w+\s+\w+)\s+([a-zA-Z0-9_~:]+)\s*\(([^\(]*)\)/ ||
+	$prototype =~ m/^(\w+\s+\w+\s+\w+\s*\*)\s*([a-zA-Z0-9_~:]+)\s*\(([^\(]*)\)/ ||
+	$prototype =~ m/^()([a-zA-Z0-9_~:]+)\s*\(([^\{]*)\)/ ||
+	$prototype =~ m/^(\w+)\s+([a-zA-Z0-9_~:]+)\s*\(([^\{]*)\)/ ||
+	$prototype =~ m/^(\w+\s*\*)\s*([a-zA-Z0-9_~:]+)\s*\(([^\{]*)\)/ ||
+	$prototype =~ m/^(\w+\s+\w+)\s+([a-zA-Z0-9_~:]+)\s*\(([^\{]*)\)/ ||
+	$prototype =~ m/^(\w+\s+\w+\s*\*)\s*([a-zA-Z0-9_~:]+)\s*\(([^\{]*)\)/ ||
+	$prototype =~ m/^(\w+\s+\w+\s+\w+)\s+([a-zA-Z0-9_~:]+)\s*\(([^\{]*)\)/ ||
+	$prototype =~ m/^(\w+\s+\w+\s+\w+\s*\*)\s*([a-zA-Z0-9_~:]+)\s*\(([^\{]*)\)/ ||
+	$prototype =~ m/^(\w+\s+\w+\s+\w+\s+\w+)\s+([a-zA-Z0-9_~:]+)\s*\(([^\{]*)\)/ ||
+	$prototype =~ m/^(\w+\s+\w+\s+\w+\s+\w+\s*\*)\s*([a-zA-Z0-9_~:]+)\s*\(([^\{]*)\)/ ||
+	$prototype =~ m/^(\w+\s+\w+\s*\*\s*\w+\s*\*\s*)\s*([a-zA-Z0-9_~:]+)\s*\(([^\{]*)\)/)  {
+	$return_type = $1;
+	$declaration_name = $2;
+	my $args = $3;
+
+	create_parameterlist($args, ',', $file);
+    } else {
+	print STDERR "Warning(${file}:$.): cannot understand function prototype: '$prototype'\n";
+	return;
+    }
+
+	my $prms = join " ", @parameterlist;
+	check_sections($file, $declaration_name, "function", $sectcheck, $prms, "");
+
+        # This check emits a lot of warnings at the moment, because many
+        # functions don't have a 'Return' doc section. So until the number
+        # of warnings goes sufficiently down, the check is only performed in
+        # verbose mode.
+        # TODO: always perform the check.
+        if ($verbose) {
+                check_return_section($file, $declaration_name, $return_type);
+        }
+
+    output_declaration($declaration_name,
+		       'function',
+		       {'function' => $declaration_name,
+			'module' => $modulename,
+			'functiontype' => $return_type,
+			'parameterlist' => \@parameterlist,
+			'parameterdescs' => \%parameterdescs,
+			'parametertypes' => \%parametertypes,
+			'sectionlist' => \@sectionlist,
+			'sections' => \%sections,
+			'purpose' => $declaration_purpose
+		       });
+}
+
+sub reset_state {
+    $function = "";
+    %constants = ();
+    %parameterdescs = ();
+    %parametertypes = ();
+    @parameterlist = ();
+    %sections = ();
+    @sectionlist = ();
+    $sectcheck = "";
+    $struct_actual = "";
+    $prototype = "";
+
+    $state = 0;
+}
+
+sub tracepoint_munge($) {
+	my $file = shift;
+	my $tracepointname = 0;
+	my $tracepointargs = 0;
+
+	if ($prototype =~ m/TRACE_EVENT\((.*?),/) {
+		$tracepointname = $1;
+	}
+	if ($prototype =~ m/DEFINE_SINGLE_EVENT\((.*?),/) {
+		$tracepointname = $1;
+	}
+	if ($prototype =~ m/DEFINE_EVENT\((.*?),(.*?),/) {
+		$tracepointname = $2;
+	}
+	$tracepointname =~ s/^\s+//; #strip leading whitespace
+	if ($prototype =~ m/TP_PROTO\((.*?)\)/) {
+		$tracepointargs = $1;
+	}
+	if (($tracepointname eq 0) || ($tracepointargs eq 0)) {
+		print STDERR "Warning(${file}:$.): Unrecognized tracepoint format: \n".
+			     "$prototype\n";
+	} else {
+		$prototype = "static inline void trace_$tracepointname($tracepointargs)";
+	}
+}
+
+sub syscall_munge() {
+	my $void = 0;
+
+	$prototype =~ s@[\r\n\t]+@ @gos; # strip newlines/CR's/tabs
+##	if ($prototype =~ m/SYSCALL_DEFINE0\s*\(\s*(a-zA-Z0-9_)*\s*\)/) {
+	if ($prototype =~ m/SYSCALL_DEFINE0/) {
+		$void = 1;
+##		$prototype = "long sys_$1(void)";
+	}
+
+	$prototype =~ s/SYSCALL_DEFINE.*\(/long sys_/; # fix return type & func name
+	if ($prototype =~ m/long (sys_.*?),/) {
+		$prototype =~ s/,/\(/;
+	} elsif ($void) {
+		$prototype =~ s/\)/\(void\)/;
+	}
+
+	# now delete all of the odd-number commas in $prototype
+	# so that arg types & arg names don't have a comma between them
+	my $count = 0;
+	my $len = length($prototype);
+	if ($void) {
+		$len = 0;	# skip the for-loop
+	}
+	for (my $ix = 0; $ix < $len; $ix++) {
+		if (substr($prototype, $ix, 1) eq ',') {
+			$count++;
+			if ($count % 2 == 1) {
+				substr($prototype, $ix, 1) = ' ';
+			}
+		}
+	}
+}
+
+sub process_state3_function($$) {
+    my $x = shift;
+    my $file = shift;
+
+    $x =~ s@\/\/.*$@@gos; # strip C99-style comments to end of line
+
+    if ($x =~ m#\s*/\*\s+MACDOC\s*#io || ($x =~ /^#/ && $x !~ /^#\s*define/)) {
+	# do nothing
+    }
+    elsif ($x =~ /([^\{]*)/) {
+	$prototype .= $1;
+    }
+
+    if (($x =~ /\{/) || ($x =~ /\#\s*define/) || ($x =~ /;/)) {
+	$prototype =~ s@/\*.*?\*/@@gos;	# strip comments.
+	$prototype =~ s@[\r\n]+@ @gos; # strip newlines/cr's.
+	$prototype =~ s@^\s+@@gos; # strip leading spaces
+	if ($prototype =~ /SYSCALL_DEFINE/) {
+		syscall_munge();
+	}
+	if ($prototype =~ /TRACE_EVENT/ || $prototype =~ /DEFINE_EVENT/ ||
+	    $prototype =~ /DEFINE_SINGLE_EVENT/)
+	{
+		tracepoint_munge($file);
+	}
+	dump_function($prototype, $file);
+	reset_state();
+    }
+}
+
+sub process_state3_type($$) {
+    my $x = shift;
+    my $file = shift;
+
+    $x =~ s@[\r\n]+@ @gos; # strip newlines/cr's.
+    $x =~ s@^\s+@@gos; # strip leading spaces
+    $x =~ s@\s+$@@gos; # strip trailing spaces
+    $x =~ s@\/\/.*$@@gos; # strip C99-style comments to end of line
+
+    if ($x =~ /^#/) {
+	# To distinguish preprocessor directive from regular declaration later.
+	$x .= ";";
+    }
+
+    while (1) {
+	if ( $x =~ /([^{};]*)([{};])(.*)/ ) {
+	    $prototype .= $1 . $2;
+	    ($2 eq '{') && $brcount++;
+	    ($2 eq '}') && $brcount--;
+	    if (($2 eq ';') && ($brcount == 0)) {
+		dump_declaration($prototype, $file);
+		reset_state();
+		last;
+	    }
+	    $x = $3;
+	} else {
+	    $prototype .= $x;
+	    last;
+	}
+    }
+}
+
+# xml_escape: replace <, >, and & in the text stream;
+#
+# however, formatting controls that are generated internally/locally in the
+# kernel-doc script are not escaped here; instead, they begin life like
+# $blankline_html (4 of '\' followed by a mnemonic + ':'), then these strings
+# are converted to their mnemonic-expected output, without the 4 * '\' & ':',
+# just before actual output; (this is done by local_unescape())
+sub xml_escape($) {
+	my $text = shift;
+	if (($output_mode eq "text") || ($output_mode eq "man")) {
+		return $text;
+	}
+	$text =~ s/\&/\\\\\\amp;/g;
+	$text =~ s/\</\\\\\\lt;/g;
+	$text =~ s/\>/\\\\\\gt;/g;
+	return $text;
+}
+
+# convert local escape strings to html
+# local escape strings look like:  '\\\\menmonic:' (that's 4 backslashes)
+sub local_unescape($) {
+	my $text = shift;
+	if (($output_mode eq "text") || ($output_mode eq "man")) {
+		return $text;
+	}
+	$text =~ s/\\\\\\\\lt:/</g;
+	$text =~ s/\\\\\\\\gt:/>/g;
+	return $text;
+}
+
+sub process_file($) {
+    my $file;
+    my $identifier;
+    my $func;
+    my $descr;
+    my $in_purpose = 0;
+    my $initial_section_counter = $section_counter;
+
+    if (defined($ENV{'SRCTREE'})) {
+	$file = "$ENV{'SRCTREE'}" . "/" . "@_";
+    }
+    else {
+	$file = "@_";
+    }
+    if (defined($source_map{$file})) {
+	$file = $source_map{$file};
+    }
+
+    if (!open(IN,"<$file")) {
+	print STDERR "Error: Cannot open file $file\n";
+	++$errors;
+	return;
+    }
+
+    $. = 1;
+
+    $section_counter = 0;
+    while (<IN>) {
+	while (s/\\\s*$//) {
+	    $_ .= <IN>;
+	}
+	if ($state == 0) {
+	    if (/$doc_start/o) {
+		$state = 1;		# next line is always the function name
+		$in_doc_sect = 0;
+	    }
+	} elsif ($state == 1) {	# this line is the function name (always)
+	    if (/$doc_block/o) {
+		$state = 4;
+		$contents = "";
+		if ( $1 eq "" ) {
+			$section = $section_intro;
+		} else {
+			$section = $1;
+		}
+	    }
+	    elsif (/$doc_decl/o) {
+		$identifier = $1;
+		if (/\s*([\w\s]+?)\s*-/) {
+		    $identifier = $1;
+		}
+
+		$state = 2;
+		if (/-(.*)/) {
+		    # strip leading/trailing/multiple spaces
+		    $descr= $1;
+		    $descr =~ s/^\s*//;
+		    $descr =~ s/\s*$//;
+		    $descr =~ s/\s+/ /g;
+		    $declaration_purpose = xml_escape($descr);
+		    $in_purpose = 1;
+		} else {
+		    $declaration_purpose = "";
+		}
+
+		if (($declaration_purpose eq "") && $verbose) {
+			print STDERR "Warning(${file}:$.): missing initial short description on line:\n";
+			print STDERR $_;
+			++$warnings;
+		}
+
+		if ($identifier =~ m/^struct/) {
+		    $decl_type = 'struct';
+		} elsif ($identifier =~ m/^union/) {
+		    $decl_type = 'union';
+		} elsif ($identifier =~ m/^enum/) {
+		    $decl_type = 'enum';
+		} elsif ($identifier =~ m/^typedef/) {
+		    $decl_type = 'typedef';
+		} else {
+		    $decl_type = 'function';
+		}
+
+		if ($verbose) {
+		    print STDERR "Info(${file}:$.): Scanning doc for $identifier\n";
+		}
+	    } else {
+		print STDERR "Warning(${file}:$.): Cannot understand $_ on line $.",
+		" - I thought it was a doc line\n";
+		++$warnings;
+		$state = 0;
+	    }
+	} elsif ($state == 2) {	# look for head: lines, and include content
+	    if (/$doc_sect/o) {
+		$newsection = $1;
+		$newcontents = $2;
+
+		if (($contents ne "") && ($contents ne "\n")) {
+		    if (!$in_doc_sect && $verbose) {
+			print STDERR "Warning(${file}:$.): contents before sections\n";
+			++$warnings;
+		    }
+		    dump_section($file, $section, xml_escape($contents));
+		    $section = $section_default;
+		}
+
+		$in_doc_sect = 1;
+		$in_purpose = 0;
+		$contents = $newcontents;
+		if ($contents ne "") {
+		    while ((substr($contents, 0, 1) eq " ") ||
+			substr($contents, 0, 1) eq "\t") {
+			    $contents = substr($contents, 1);
+		    }
+		    $contents .= "\n";
+		}
+		$section = $newsection;
+	    } elsif (/$doc_end/) {
+
+		if (($contents ne "") && ($contents ne "\n")) {
+		    dump_section($file, $section, xml_escape($contents));
+		    $section = $section_default;
+		    $contents = "";
+		}
+		# look for doc_com + <text> + doc_end:
+		if ($_ =~ m'\s*\*\s*[a-zA-Z_0-9:\.]+\*/') {
+		    print STDERR "Warning(${file}:$.): suspicious ending line: $_";
+		    ++$warnings;
+		}
+
+		$prototype = "";
+		$state = 3;
+		$brcount = 0;
+#		print STDERR "end of doc comment, looking for prototype\n";
+	    } elsif (/$doc_content/) {
+		# miguel-style comment kludge, look for blank lines after
+		# @parameter line to signify start of description
+		if ($1 eq "") {
+		    if ($section =~ m/^@/ || $section eq $section_context) {
+			dump_section($file, $section, xml_escape($contents));
+			$section = $section_default;
+			$contents = "";
+		    } else {
+			$contents .= "\n";
+		    }
+		    $in_purpose = 0;
+		} elsif ($in_purpose == 1) {
+		    # Continued declaration purpose
+		    chomp($declaration_purpose);
+		    $declaration_purpose .= " " . xml_escape($1);
+		    $declaration_purpose =~ s/\s+/ /g;
+		} else {
+		    $contents .= $1 . "\n";
+		}
+	    } else {
+		# i dont know - bad line?  ignore.
+		print STDERR "Warning(${file}:$.): bad line: $_";
+		++$warnings;
+	    }
+	} elsif ($state == 3) {	# scanning for function '{' (end of prototype)
+	    if ($decl_type eq 'function') {
+		process_state3_function($_, $file);
+	    } else {
+		process_state3_type($_, $file);
+	    }
+	} elsif ($state == 4) {
+		# Documentation block
+		if (/$doc_block/) {
+			dump_doc_section($file, $section, xml_escape($contents));
+			$contents = "";
+			$function = "";
+			%constants = ();
+			%parameterdescs = ();
+			%parametertypes = ();
+			@parameterlist = ();
+			%sections = ();
+			@sectionlist = ();
+			$prototype = "";
+			if ( $1 eq "" ) {
+				$section = $section_intro;
+			} else {
+				$section = $1;
+			}
+		}
+		elsif (/$doc_end/)
+		{
+			dump_doc_section($file, $section, xml_escape($contents));
+			$contents = "";
+			$function = "";
+			%constants = ();
+			%parameterdescs = ();
+			%parametertypes = ();
+			@parameterlist = ();
+			%sections = ();
+			@sectionlist = ();
+			$prototype = "";
+			$state = 0;
+		}
+		elsif (/$doc_content/)
+		{
+			if ( $1 eq "" )
+			{
+				$contents .= $blankline;
+			}
+			else
+			{
+				$contents .= $1 . "\n";
+			}
+		}
+	}
+    }
+    if ($initial_section_counter == $section_counter) {
+	print STDERR "Warning(${file}): no structured comments found\n";
+	if (($function_only == 1) && ($show_not_found == 1)) {
+	    print STDERR "    Was looking for '$_'.\n" for keys %function_table;
+	}
+	if ($output_mode eq "xml") {
+	    # The template wants at least one RefEntry here; make one.
+	    print "<refentry>\n";
+	    print " <refnamediv>\n";
+	    print "  <refname>\n";
+	    print "   ${file}\n";
+	    print "  </refname>\n";
+	    print "  <refpurpose>\n";
+	    print "   Document generation inconsistency\n";
+	    print "  </refpurpose>\n";
+	    print " </refnamediv>\n";
+	    print " <refsect1>\n";
+	    print "  <title>\n";
+	    print "   Oops\n";
+	    print "  </title>\n";
+	    print "  <warning>\n";
+	    print "   <para>\n";
+	    print "    The template for this document tried to insert\n";
+	    print "    the structured comment from the file\n";
+	    print "    <filename>${file}</filename> at this point,\n";
+	    print "    but none was found.\n";
+	    print "    This dummy section is inserted to allow\n";
+	    print "    generation to continue.\n";
+	    print "   </para>\n";
+	    print "  </warning>\n";
+	    print " </refsect1>\n";
+	    print "</refentry>\n";
+	}
+    }
+}
+
+
+$kernelversion = get_kernel_version();
+
+# generate a sequence of code that will splice in highlighting information
+# using the s// operator.
+foreach my $pattern (keys %highlights) {
+#   print STDERR "scanning pattern:$pattern, highlight:($highlights{$pattern})\n";
+    $dohighlight .=  "\$contents =~ s:$pattern:$highlights{$pattern}:gs;\n";
+}
+
+# Read the file that maps relative names to absolute names for
+# separate source and object directories and for shadow trees.
+if (open(SOURCE_MAP, "<.tmp_filelist.txt")) {
+	my ($relname, $absname);
+	while(<SOURCE_MAP>) {
+		chop();
+		($relname, $absname) = (split())[0..1];
+		$relname =~ s:^/+::;
+		$source_map{$relname} = $absname;
+	}
+	close(SOURCE_MAP);
+}
+
+foreach (@ARGV) {
+    chomp;
+    process_file($_);
+}
+if ($verbose && $errors) {
+  print STDERR "$errors errors\n";
+}
+if ($verbose && $warnings) {
+  print STDERR "$warnings warnings\n";
+}
+
+exit($errors);
diff --git a/scripts/mkmakefile b/scripts/mkmakefile
new file mode 100644
index 0000000000..0cc0442607
--- /dev/null
+++ b/scripts/mkmakefile
@@ -0,0 +1,59 @@
+#!/bin/sh
+# Generates a small Makefile used in the root of the output
+# directory, to allow make to be started from there.
+# The Makefile also allow for more convinient build of external modules
+
+# Usage
+# $1 - Kernel src directory
+# $2 - Output directory
+# $3 - version
+# $4 - patchlevel
+
+
+test ! -r $2/Makefile -o -O $2/Makefile || exit 0
+# Only overwrite automatically generated Makefiles
+# (so we do not overwrite kernel Makefile)
+if test -e $2/Makefile && ! grep -q Automatically $2/Makefile
+then
+	exit 0
+fi
+if [ "${quiet}" != "silent_" ]; then
+	echo "  GEN     $2/Makefile"
+fi
+
+cat << EOF > $2/Makefile
+# Automatically generated by $0: don't edit
+
+VERSION = $3
+PATCHLEVEL = $4
+
+lastword = \$(word \$(words \$(1)),\$(1))
+makedir := \$(dir \$(call lastword,\$(MAKEFILE_LIST)))
+
+ifeq ("\$(origin V)", "command line")
+VERBOSE := \$(V)
+endif
+ifneq (\$(VERBOSE),1)
+Q := @
+endif
+
+MAKEARGS := -C $1
+MAKEARGS += O=\$(if \$(patsubst /%,,\$(makedir)),\$(CURDIR)/)\$(patsubst %/,%,\$(makedir))
+
+MAKEFLAGS += --no-print-directory
+
+.PHONY: all \$(MAKECMDGOALS)
+
+all	:= \$(filter-out all Makefile,\$(MAKECMDGOALS))
+
+all:
+	\$(Q)\$(MAKE) \$(MAKEARGS) \$(all)
+
+Makefile:;
+
+\$(all): all
+	@:
+
+%/: all
+	@:
+EOF
diff --git a/tools/setlocalversion b/scripts/setlocalversion
index f551b4c4f4..f551b4c4f4 100755
--- a/tools/setlocalversion
+++ b/scripts/setlocalversion
diff --git a/spl/.gitignore b/spl/.gitignore
deleted file mode 100644
index 7c8814709f..0000000000
--- a/spl/.gitignore
+++ /dev/null
@@ -1,4 +0,0 @@
-u-boot-spl
-u-boot-spl.bin
-u-boot-spl.lds
-u-boot-spl.map
diff --git a/spl/Makefile b/spl/Makefile
index b366ac2bb7..6fec2522a8 100644
--- a/spl/Makefile
+++ b/spl/Makefile
@@ -14,9 +14,21 @@
 # Based on top-level Makefile.
 #
 
+src := $(obj)
+
+# Create output directory if not already present
+_dummy := $(shell [ -d $(obj) ] || mkdir -p $(obj))
+
+include $(srctree)/scripts/Kbuild.include
+
 CONFIG_SPL_BUILD := y
 export CONFIG_SPL_BUILD
 
+KBUILD_CPPFLAGS += -DCONFIG_SPL_BUILD
+ifeq ($(CONFIG_TPL_BUILD),y)
+KBUILD_CPPFLAGS += -DCONFIG_TPL_BUILD
+endif
+
 ifeq ($(CONFIG_TPL_BUILD),y)
 export CONFIG_TPL_BUILD
 SPL_BIN := u-boot-tpl
@@ -24,131 +36,126 @@ else
 SPL_BIN := u-boot-spl
 endif
 
-include $(TOPDIR)/config.mk
+include include/config.mk
 
-# We want the final binaries in this directory
 ifeq ($(CONFIG_TPL_BUILD),y)
-obj := $(OBJTREE)/tpl/
-SPLTREE := $(TPLTREE)
+  -include include/tpl-autoconf.mk
 else
-obj := $(OBJTREE)/spl/
+  -include include/spl-autoconf.mk
 endif
 
-HAVE_VENDOR_COMMON_LIB = $(if $(wildcard $(SRCTREE)/board/$(VENDOR)/common/Makefile),y,n)
+include $(srctree)/config.mk
 
-ifdef	CONFIG_SPL_START_S_PATH
-START_PATH := $(subst ",,$(CONFIG_SPL_START_S_PATH))
-else
-START_PATH := $(CPUDIR)
-endif
+# Enable garbage collection of un-used sections for SPL
+KBUILD_CFLAGS += -ffunction-sections -fdata-sections
+LDFLAGS_FINAL += --gc-sections
 
-START := $(START_PATH)/start.o
-ifeq ($(CPU),x86)
-START += $(START_PATH)/start16.o
-START += $(START_PATH)/resetvec.o
-endif
-ifeq ($(CPU),ppc4xx)
-START += $(START_PATH)/resetvec.o
-endif
-ifeq ($(CPU),mpc85xx)
-START += $(START_PATH)/resetvec.o
-endif
+# FIX ME
+cpp_flags := $(KBUILD_CPPFLAGS) $(PLATFORM_CPPFLAGS) $(UBOOTINCLUDE) \
+							$(NOSTDINC_FLAGS)
+c_flags := $(KBUILD_CFLAGS) $(cpp_flags)
 
-LIBS-y += arch/$(ARCH)/lib/lib$(ARCH).o
+# Auto-generate the spl-autoconf.mk file (which is included by all makefiles for SPL)
+quiet_cmd_autoconf = GEN     $@
+      cmd_autoconf = \
+	$(CPP) $(c_flags) -DDO_DEPS_ONLY -dM $(srctree)/include/common.h > $@.tmp && \
+		sed -n -f $(srctree)/tools/scripts/define2mk.sed $@.tmp > $@; \
+	rm $@.tmp
 
-LIBS-y += $(CPUDIR)/lib$(CPU).o
-ifeq ($(CPU),mpc83xx)
-LIBS-y += arch/powerpc/cpu/mpc8xxx/lib8xxx.o
-endif
-ifeq ($(CPU),mpc85xx)
-LIBS-y += arch/powerpc/cpu/mpc8xxx/lib8xxx.o
-ifdef CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
-LIBS-y += arch/powerpc/cpu/mpc8xxx/ddr/libddr.o
-endif
-endif
-ifeq ($(CPU),mpc86xx)
-LIBS-y += arch/powerpc/cpu/mpc8xxx/lib8xxx.o
-endif
+include/tpl-autoconf.mk: include/config.h
+	$(call cmd,autoconf)
 
-ifdef SOC
-LIBS-y += $(CPUDIR)/$(SOC)/lib$(SOC).o
-endif
-LIBS-y += board/$(BOARDDIR)/lib$(BOARD).o
-LIBS-$(HAVE_VENDOR_COMMON_LIB) += board/$(VENDOR)/common/lib$(VENDOR).o
+include/spl-autoconf.mk: include/config.h
+	$(call cmd,autoconf)
 
-LIBS-$(CONFIG_SPL_FRAMEWORK) += common/spl/libspl.o
-LIBS-$(CONFIG_SPL_LIBCOMMON_SUPPORT) += common/libcommon.o
-LIBS-$(CONFIG_SPL_LIBDISK_SUPPORT) += disk/libdisk.o
-LIBS-$(CONFIG_SPL_I2C_SUPPORT) += drivers/i2c/libi2c.o
-LIBS-$(CONFIG_SPL_GPIO_SUPPORT) += drivers/gpio/libgpio.o
-LIBS-$(CONFIG_SPL_MMC_SUPPORT) += drivers/mmc/libmmc.o
-LIBS-$(CONFIG_SPL_SERIAL_SUPPORT) += drivers/serial/libserial.o
-LIBS-$(CONFIG_SPL_SPI_FLASH_SUPPORT) += drivers/mtd/spi/libspi_flash.o
-LIBS-$(CONFIG_SPL_SPI_SUPPORT) += drivers/spi/libspi.o
-LIBS-$(CONFIG_SPL_FAT_SUPPORT) += fs/fat/libfat.o
-LIBS-$(CONFIG_SPL_LIBGENERIC_SUPPORT) += lib/libgeneric.o
-LIBS-$(CONFIG_SPL_POWER_SUPPORT) += drivers/power/libpower.o \
-	drivers/power/pmic/libpmic.o
-LIBS-$(CONFIG_SPL_NAND_SUPPORT) += drivers/mtd/nand/libnand.o
-LIBS-$(CONFIG_SPL_ONENAND_SUPPORT) += drivers/mtd/onenand/libonenand.o
-LIBS-$(CONFIG_SPL_DMA_SUPPORT) += drivers/dma/libdma.o
-LIBS-$(CONFIG_SPL_POST_MEM_SUPPORT) += post/drivers/memory.o
-LIBS-$(CONFIG_SPL_NET_SUPPORT) += net/libnet.o
-LIBS-$(CONFIG_SPL_ETH_SUPPORT) += drivers/net/libnet.o
-LIBS-$(CONFIG_SPL_ETH_SUPPORT) += drivers/net/phy/libphy.o
-LIBS-$(CONFIG_SPL_USBETH_SUPPORT) += drivers/net/phy/libphy.o
-LIBS-$(CONFIG_SPL_MUSB_NEW_SUPPORT) += drivers/usb/musb-new/libusb_musb-new.o
-LIBS-$(CONFIG_SPL_USBETH_SUPPORT) += drivers/usb/gadget/libusb_gadget.o
-LIBS-$(CONFIG_SPL_WATCHDOG_SUPPORT) += drivers/watchdog/libwatchdog.o
+HAVE_VENDOR_COMMON_LIB = $(if $(wildcard $(srctree)/board/$(VENDOR)/common/Makefile),y,n)
 
-ifneq ($(CONFIG_OMAP_COMMON),)
-LIBS-y += $(CPUDIR)/omap-common/libomap-common.o
+ifdef	CONFIG_SPL_START_S_PATH
+START_PATH := $(CONFIG_SPL_START_S_PATH:"%"=%)
+else
+START_PATH := $(CPUDIR)
 endif
 
-ifneq (,$(CONFIG_MX23)$(filter $(SOC), mx25 mx27 mx5 mx6 mx31 mx35))
-LIBS-y += arch/$(ARCH)/imx-common/libimx-common.o
-endif
+head-y := $(START_PATH)/start.o
+head-$(CONFIG_X86) += $(START_PATH)/start16.o $(START_PATH)/resetvec.o
+head-$(CONFIG_4xx) += $(START_PATH)/resetvec.o
+head-$(CONFIG_MPC85xx) += $(START_PATH)/resetvec.o
 
-ifneq ($(CONFIG_TEGRA),)
-LIBS-y += arch/$(ARCH)/cpu/$(SOC)-common/lib$(SOC)-common.o
-LIBS-y += arch/$(ARCH)/cpu/tegra-common/libcputegra-common.o
-LIBS-y += $(CPUDIR)/tegra-common/libtegra-common.o
-endif
+libs-y += arch/$(ARCH)/lib/
 
-ifneq ($(CONFIG_MX23)$(CONFIG_MX35),)
-LIBS-y += arch/$(ARCH)/imx-common/libimx-common.o
-endif
+libs-y += $(CPUDIR)/
 
-ifeq ($(SOC),exynos)
-LIBS-y += $(CPUDIR)/s5p-common/libs5p-common.o
-endif
+ifdef SOC
+libs-y += $(CPUDIR)/$(SOC)/
+endif
+libs-y += board/$(BOARDDIR)/
+libs-$(HAVE_VENDOR_COMMON_LIB) += board/$(VENDOR)/common/
+
+libs-$(CONFIG_SPL_FRAMEWORK) += common/spl/
+libs-$(CONFIG_SPL_LIBCOMMON_SUPPORT) += common/
+libs-$(CONFIG_SPL_LIBDISK_SUPPORT) += disk/
+libs-$(CONFIG_SPL_I2C_SUPPORT) += drivers/i2c/
+libs-$(CONFIG_SPL_GPIO_SUPPORT) += drivers/gpio/
+libs-$(CONFIG_SPL_MMC_SUPPORT) += drivers/mmc/
+libs-$(CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT) += drivers/ddr/fsl/
+libs-$(CONFIG_SPL_SERIAL_SUPPORT) += drivers/serial/
+libs-$(CONFIG_SPL_SPI_FLASH_SUPPORT) += drivers/mtd/spi/
+libs-$(CONFIG_SPL_SPI_SUPPORT) += drivers/spi/
+libs-y += fs/
+libs-$(CONFIG_SPL_LIBGENERIC_SUPPORT) += lib/
+libs-$(CONFIG_SPL_POWER_SUPPORT) += drivers/power/ drivers/power/pmic/
+libs-$(if $(CONFIG_CMD_NAND),$(CONFIG_SPL_NAND_SUPPORT)) += drivers/mtd/nand/
+libs-$(CONFIG_SPL_DRIVERS_MISC_SUPPORT) += drivers/misc/
+libs-$(CONFIG_SPL_ONENAND_SUPPORT) += drivers/mtd/onenand/
+libs-$(CONFIG_SPL_DMA_SUPPORT) += drivers/dma/
+libs-$(CONFIG_SPL_POST_MEM_SUPPORT) += post/drivers/
+libs-$(CONFIG_SPL_NET_SUPPORT) += net/
+libs-$(CONFIG_SPL_ETH_SUPPORT) += drivers/net/
+libs-$(CONFIG_SPL_ETH_SUPPORT) += drivers/net/phy/
+libs-$(CONFIG_SPL_USBETH_SUPPORT) += drivers/net/phy/
+libs-$(CONFIG_SPL_MUSB_NEW_SUPPORT) += drivers/usb/musb-new/
+libs-$(CONFIG_SPL_USBETH_SUPPORT) += drivers/usb/gadget/
+libs-$(CONFIG_SPL_WATCHDOG_SUPPORT) += drivers/watchdog/
+libs-$(CONFIG_SPL_USB_HOST_SUPPORT) += drivers/usb/host/
+libs-$(CONFIG_OMAP_USB_PHY) += drivers/usb/phy/
+libs-$(CONFIG_SPL_SATA_SUPPORT) += drivers/block/
+
+ifneq (,$(CONFIG_MX23)$(CONFIG_MX35)$(filter $(SOC), mx25 mx27 mx5 mx6 mx31 mx35))
+libs-y += arch/$(ARCH)/imx-common/
+endif
+
+libs-$(CONFIG_ARM) += arch/arm/cpu/
+libs-$(CONFIG_PPC) += arch/powerpc/cpu/
+
+head-y		:= $(addprefix $(obj)/,$(head-y))
+libs-y		:= $(addprefix $(obj)/,$(libs-y))
+u-boot-spl-dirs	:= $(patsubst %/,%,$(filter %/, $(libs-y)))
+
+libs-y := $(patsubst %/, %/built-in.o, $(libs-y))
 
 # Add GCC lib
-ifeq ("$(USE_PRIVATE_LIBGCC)", "yes")
-PLATFORM_LIBGCC = $(SPLTREE)/arch/$(ARCH)/lib/libgcc.o
-PLATFORM_LIBS := $(filter-out %/libgcc.o, $(filter-out -lgcc, $(PLATFORM_LIBS))) $(PLATFORM_LIBGCC)
+ifeq ($(CONFIG_USE_PRIVATE_LIBGCC),y)
+PLATFORM_LIBGCC = arch/$(ARCH)/lib/lib.a
+PLATFORM_LIBS := $(filter-out %/lib.a, $(filter-out -lgcc, $(PLATFORM_LIBS))) $(PLATFORM_LIBGCC)
 endif
 
-START := $(addprefix $(SPLTREE)/,$(START))
-LIBS := $(addprefix $(SPLTREE)/,$(sort $(LIBS-y)))
-
-__START := $(subst $(obj),,$(START))
-__LIBS := $(subst $(obj),,$(LIBS))
+u-boot-spl-init := $(head-y)
+u-boot-spl-main := $(libs-y)
 
 # Linker Script
 ifdef CONFIG_SPL_LDSCRIPT
 # need to strip off double quotes
-LDSCRIPT := $(addprefix $(SRCTREE)/,$(subst ",,$(CONFIG_SPL_LDSCRIPT)))
+LDSCRIPT := $(addprefix $(srctree)/,$(CONFIG_SPL_LDSCRIPT:"%"=%))
 endif
 
 ifeq ($(wildcard $(LDSCRIPT)),)
-	LDSCRIPT := $(TOPDIR)/board/$(BOARDDIR)/u-boot-spl.lds
+	LDSCRIPT := $(srctree)/board/$(BOARDDIR)/u-boot-spl.lds
 endif
 ifeq ($(wildcard $(LDSCRIPT)),)
-	LDSCRIPT := $(TOPDIR)/$(CPUDIR)/u-boot-spl.lds
+	LDSCRIPT := $(srctree)/$(CPUDIR)/u-boot-spl.lds
 endif
 ifeq ($(wildcard $(LDSCRIPT)),)
-	LDSCRIPT := $(TOPDIR)/arch/$(ARCH)/cpu/u-boot-spl.lds
+	LDSCRIPT := $(srctree)/arch/$(ARCH)/cpu/u-boot-spl.lds
 endif
 ifeq ($(wildcard $(LDSCRIPT)),)
 $(error could not find linker script)
@@ -158,59 +165,91 @@ endif
 # Pass the version down so we can handle backwards compatibility
 # on the fly.
 LDPPFLAGS += \
-	-include $(TOPDIR)/include/u-boot/u-boot.lds.h \
-	-include $(OBJTREE)/include/config.h \
+	-include $(srctree)/include/u-boot/u-boot.lds.h \
+	-include $(objtree)/include/config.h \
 	-DCPUDIR=$(CPUDIR) \
 	$(shell $(LD) --version | \
 	  sed -ne 's/GNU ld version \([0-9][0-9]*\)\.\([0-9][0-9]*\).*/-DLD_MAJOR=\1 -DLD_MINOR=\2/p')
 
-$(OBJTREE)/MLO:	$(obj)u-boot-spl.bin
-	$(OBJTREE)/tools/mkimage -T omapimage \
-		-a $(CONFIG_SPL_TEXT_BASE) -d $< $@
+quiet_cmd_mkimage = MKIMAGE $@
+cmd_mkimage = $(objtree)/tools/mkimage $(MKIMAGEFLAGS_$(@F)) -d $< $@ \
+	$(if $(KBUILD_VERBOSE:1=), >/dev/null)
 
-$(OBJTREE)/MLO.byteswap: $(obj)u-boot-spl.bin
-	$(OBJTREE)/tools/mkimage -T omapimage -n byteswap \
-		-a $(CONFIG_SPL_TEXT_BASE) -d $< $@
+MKIMAGEFLAGS_MLO = -T omapimage -a $(CONFIG_SPL_TEXT_BASE)
 
-$(OBJTREE)/SPL : $(obj)u-boot-spl.bin depend
-		$(MAKE) -C $(SRCTREE)/arch/arm/imx-common $@
+MKIMAGEFLAGS_MLO.byteswap = -T omapimage -n byteswap -a $(CONFIG_SPL_TEXT_BASE)
 
-ALL-y	+= $(obj)$(SPL_BIN).bin
+MLO MLO.byteswap: $(obj)/u-boot-spl.bin
+	$(call if_changed,mkimage)
+
+ALL-y	+= $(obj)/$(SPL_BIN).bin
 
 ifdef CONFIG_SAMSUNG
-ALL-y	+= $(obj)$(BOARD)-spl.bin
+ALL-y	+= $(obj)/$(BOARD)-spl.bin
 endif
 
 all:	$(ALL-y)
 
 ifdef CONFIG_SAMSUNG
-$(obj)$(BOARD)-spl.bin: $(obj)u-boot-spl.bin
-	$(OBJTREE)/tools/mk$(BOARD)spl \
-		$(obj)u-boot-spl.bin $(obj)$(BOARD)-spl.bin
+ifdef CONFIG_VAR_SIZE_SPL
+VAR_SIZE_PARAM = --vs
+else
+VAR_SIZE_PARAM =
 endif
+$(obj)/$(BOARD)-spl.bin: $(obj)/u-boot-spl.bin
+	$(if $(wildcard $(objtree)/spl/board/samsung/$(BOARD)/tools/mk$(BOARD)spl),\
+	$(objtree)/spl/board/samsung/$(BOARD)/tools/mk$(BOARD)spl,\
+	$(objtree)/tools/mkexynosspl) $(VAR_SIZE_PARAM) $< $@
+endif
+
+quiet_cmd_objcopy = OBJCOPY $@
+cmd_objcopy = $(OBJCOPY) $(OBJCOPYFLAGS) $(OBJCOPYFLAGS_$(@F)) $< $@
+
+OBJCOPYFLAGS_$(SPL_BIN).bin = $(SPL_OBJCFLAGS) -O binary
+
+$(obj)/$(SPL_BIN).bin: $(obj)/$(SPL_BIN) FORCE
+	$(call if_changed,objcopy)
+
+LDFLAGS_$(SPL_BIN) += -T u-boot-spl.lds $(LDFLAGS_FINAL)
+ifneq ($(CONFIG_SPL_TEXT_BASE),)
+LDFLAGS_$(SPL_BIN) += -Ttext $(CONFIG_SPL_TEXT_BASE)
+endif
+
+quiet_cmd_u-boot-spl = LD      $@
+      cmd_u-boot-spl = cd $(obj) && $(LD) $(LDFLAGS) $(LDFLAGS_$(@F)) \
+		       $(patsubst $(obj)/%,%,$(u-boot-spl-init)) --start-group \
+		       $(patsubst $(obj)/%,%,$(u-boot-spl-main)) --end-group \
+		       $(PLATFORM_LIBS) -Map $(SPL_BIN).map -o $(SPL_BIN)
+
+$(obj)/$(SPL_BIN): $(u-boot-spl-init) $(u-boot-spl-main) $(obj)/u-boot-spl.lds
+	$(call cmd,u-boot-spl)
 
-$(obj)$(SPL_BIN).bin:	$(obj)$(SPL_BIN)
-	$(OBJCOPY) $(OBJCFLAGS) -O binary $< $@
+$(sort $(u-boot-spl-init) $(u-boot-spl-main)): $(u-boot-spl-dirs) ;
 
-GEN_UBOOT = \
-	cd $(obj) && $(LD) $(LDFLAGS) $(LDFLAGS_$(@F)) $(__START) \
-		--start-group $(__LIBS) --end-group $(PLATFORM_LIBS) \
-		-Map $(SPL_BIN).map -o $(SPL_BIN)
+PHONY += $(u-boot-spl-dirs)
+$(u-boot-spl-dirs):
+	$(Q)$(MAKE) $(build)=$@
 
-$(obj)$(SPL_BIN):	depend $(START) $(LIBS) $(obj)u-boot-spl.lds
-	$(GEN_UBOOT)
+quiet_cmd_cpp_lds = LDS     $@
+cmd_cpp_lds = $(CPP) -Wp,-MD,$(depfile) $(cpp_flags) $(LDPPFLAGS) -ansi \
+		-D__ASSEMBLY__ -x assembler-with-cpp -P -o $@ $<
 
-$(START):	depend
-	$(MAKE) -C $(SRCTREE)/$(START_PATH) $@
+$(obj)/u-boot-spl.lds: $(LDSCRIPT) FORCE
+	$(call if_changed_dep,cpp_lds)
 
-$(LIBS):	depend
-	$(MAKE) -C $(SRCTREE)$(dir $(subst $(SPLTREE),,$@))
+# read all saved command lines
 
-$(obj)u-boot-spl.lds: $(LDSCRIPT) depend
-	$(CPP) $(CPPFLAGS) $(LDPPFLAGS) -I$(obj). -ansi -D__ASSEMBLY__ -P - < $< > $@
+targets := $(wildcard $(sort $(targets)))
+cmd_files := $(wildcard $(obj)/.*.cmd $(foreach f,$(targets),$(dir $(f)).$(notdir $(f)).cmd))
+
+ifneq ($(cmd_files),)
+  $(cmd_files): ;	# Do not try to update included dependency files
+  include $(cmd_files)
+endif
 
-depend:	$(obj).depend
-.PHONY: depend
+PHONY += FORCE
+FORCE:
 
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
+# Declare the contents of the .PHONY variable as phony.  We keep that
+# information in a variable so we can use it in if_changed and friends.
+.PHONY: $(PHONY)
diff --git a/test/Makefile b/test/Makefile
index a68613df72..9c95805c44 100644
--- a/test/Makefile
+++ b/test/Makefile
@@ -4,27 +4,5 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)libtest.o
-
-COBJS-$(CONFIG_SANDBOX) += command_ut.o
-COBJS-$(CONFIG_SANDBOX) += compression.o
-
-COBJS	:= $(sort $(COBJS-y))
-SRCS	:= $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-
-all:	$(LIB) $(XOBJS)
-
-$(LIB): $(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+obj-$(CONFIG_SANDBOX) += command_ut.o
+obj-$(CONFIG_SANDBOX) += compression.o
diff --git a/test/command_ut.c b/test/command_ut.c
index 0e83db0cca..aaa1ee25d0 100644
--- a/test/command_ut.c
+++ b/test/command_ut.c
@@ -7,6 +7,9 @@
 #define DEBUG
 
 #include <common.h>
+#ifdef CONFIG_SANDBOX
+#include <os.h>
+#endif
 
 static const char test_cmd[] = "setenv list 1\n setenv list ${list}2; "
 		"setenv list ${list}3\0"
@@ -15,7 +18,7 @@ static const char test_cmd[] = "setenv list 1\n setenv list ${list}2; "
 static int do_ut_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 {
 	printf("%s: Testing commands\n", __func__);
-	run_command("env default -f", 0);
+	run_command("env default -f -a", 0);
 
 	/* run a single command */
 	run_command("setenv single 1", 0);
@@ -58,6 +61,114 @@ static int do_ut_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 		"setenv list ${list}3", strlen("setenv list 1"), 0);
 	assert(!strcmp("1", getenv("list")));
 
+#ifdef CONFIG_SYS_HUSH_PARSER
+	/* Test the 'test' command */
+
+#define HUSH_TEST(name, expr, expected_result) \
+	run_command("if test " expr " ; then " \
+			"setenv " #name "_" #expected_result " y; else " \
+			"setenv " #name "_" #expected_result " n; fi", 0); \
+	assert(!strcmp(#expected_result, getenv(#name "_" #expected_result))); \
+	setenv(#name "_" #expected_result, NULL);
+
+	/* Basic operators */
+	HUSH_TEST(streq, "aaa = aaa", y);
+	HUSH_TEST(streq, "aaa = bbb", n);
+
+	HUSH_TEST(strneq, "aaa != bbb", y);
+	HUSH_TEST(strneq, "aaa != aaa", n);
+
+	HUSH_TEST(strlt, "aaa < bbb", y);
+	HUSH_TEST(strlt, "bbb < aaa", n);
+
+	HUSH_TEST(strgt, "bbb > aaa", y);
+	HUSH_TEST(strgt, "aaa > bbb", n);
+
+	HUSH_TEST(eq, "123 -eq 123", y);
+	HUSH_TEST(eq, "123 -eq 456", n);
+
+	HUSH_TEST(ne, "123 -ne 456", y);
+	HUSH_TEST(ne, "123 -ne 123", n);
+
+	HUSH_TEST(lt, "123 -lt 456", y);
+	HUSH_TEST(lt_eq, "123 -lt 123", n);
+	HUSH_TEST(lt, "456 -lt 123", n);
+
+	HUSH_TEST(le, "123 -le 456", y);
+	HUSH_TEST(le_eq, "123 -le 123", y);
+	HUSH_TEST(le, "456 -le 123", n);
+
+	HUSH_TEST(gt, "456 -gt 123", y);
+	HUSH_TEST(gt_eq, "123 -gt 123", n);
+	HUSH_TEST(gt, "123 -gt 456", n);
+
+	HUSH_TEST(ge, "456 -ge 123", y);
+	HUSH_TEST(ge_eq, "123 -ge 123", y);
+	HUSH_TEST(ge, "123 -ge 456", n);
+
+	HUSH_TEST(z, "-z \"\"", y);
+	HUSH_TEST(z, "-z \"aaa\"", n);
+
+	HUSH_TEST(n, "-n \"aaa\"", y);
+	HUSH_TEST(n, "-n \"\"", n);
+
+	/* Inversion of simple tests */
+	HUSH_TEST(streq_inv, "! aaa = aaa", n);
+	HUSH_TEST(streq_inv, "! aaa = bbb", y);
+
+	HUSH_TEST(streq_inv_inv, "! ! aaa = aaa", y);
+	HUSH_TEST(streq_inv_inv, "! ! aaa = bbb", n);
+
+	/* Binary operators */
+	HUSH_TEST(or_0_0, "aaa != aaa -o bbb != bbb", n);
+	HUSH_TEST(or_0_1, "aaa != aaa -o bbb = bbb", y);
+	HUSH_TEST(or_1_0, "aaa = aaa -o bbb != bbb", y);
+	HUSH_TEST(or_1_1, "aaa = aaa -o bbb = bbb", y);
+
+	HUSH_TEST(and_0_0, "aaa != aaa -a bbb != bbb", n);
+	HUSH_TEST(and_0_1, "aaa != aaa -a bbb = bbb", n);
+	HUSH_TEST(and_1_0, "aaa = aaa -a bbb != bbb", n);
+	HUSH_TEST(and_1_1, "aaa = aaa -a bbb = bbb", y);
+
+	/* Inversion within binary operators */
+	HUSH_TEST(or_0_0_inv, "! aaa != aaa -o ! bbb != bbb", y);
+	HUSH_TEST(or_0_1_inv, "! aaa != aaa -o ! bbb = bbb", y);
+	HUSH_TEST(or_1_0_inv, "! aaa = aaa -o ! bbb != bbb", y);
+	HUSH_TEST(or_1_1_inv, "! aaa = aaa -o ! bbb = bbb", n);
+
+	HUSH_TEST(or_0_0_inv_inv, "! ! aaa != aaa -o ! ! bbb != bbb", n);
+	HUSH_TEST(or_0_1_inv_inv, "! ! aaa != aaa -o ! ! bbb = bbb", y);
+	HUSH_TEST(or_1_0_inv_inv, "! ! aaa = aaa -o ! ! bbb != bbb", y);
+	HUSH_TEST(or_1_1_inv_inv, "! ! aaa = aaa -o ! ! bbb = bbb", y);
+
+	setenv("ut_var_nonexistent", NULL);
+	setenv("ut_var_exists", "1");
+	HUSH_TEST(z_varexp_quoted, "-z \"$ut_var_nonexistent\"", y);
+	HUSH_TEST(z_varexp_quoted, "-z \"$ut_var_exists\"", n);
+	setenv("ut_var_exists", NULL);
+
+	run_command("setenv ut_var_space \" \"", 0);
+	assert(!strcmp(getenv("ut_var_space"), " "));
+	run_command("setenv ut_var_test $ut_var_space", 0);
+	assert(!getenv("ut_var_test"));
+	run_command("setenv ut_var_test \"$ut_var_space\"", 0);
+	assert(!strcmp(getenv("ut_var_test"), " "));
+	run_command("setenv ut_var_test \" 1${ut_var_space}${ut_var_space} 2 \"", 0);
+	assert(!strcmp(getenv("ut_var_test"), " 1   2 "));
+	setenv("ut_var_space", NULL);
+	setenv("ut_var_test", NULL);
+
+#ifdef CONFIG_SANDBOX
+	/* File existence */
+	HUSH_TEST(e, "-e host - creating_this_file_breaks_uboot_unit_test", n);
+	run_command("sb save host - creating_this_file_breaks_uboot_unit_test 0 1", 0);
+	HUSH_TEST(e, "-e host - creating_this_file_breaks_uboot_unit_test", y);
+	/* Perhaps this could be replaced by an "rm" shell command one day */
+	assert(!os_unlink("creating_this_file_breaks_uboot_unit_test"));
+	HUSH_TEST(e, "-e host - creating_this_file_breaks_uboot_unit_test", n);
+#endif
+#endif
+
 	printf("%s: Everything went swimmingly\n", __func__);
 	return 0;
 }
diff --git a/test/dm/.gitignore b/test/dm/.gitignore
new file mode 100644
index 0000000000..b741b8ab00
--- /dev/null
+++ b/test/dm/.gitignore
@@ -0,0 +1 @@
+/test.dtb
diff --git a/test/dm/Makefile b/test/dm/Makefile
new file mode 100644
index 0000000000..4e9afe6c9c
--- /dev/null
+++ b/test/dm/Makefile
@@ -0,0 +1,18 @@
+#
+# Copyright (c) 2013 Google, Inc
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-$(CONFIG_CMD_DM) += cmd_dm.o
+obj-$(CONFIG_DM_TEST) += test-driver.o
+obj-$(CONFIG_DM_TEST) += test-fdt.o
+obj-$(CONFIG_DM_TEST) += test-main.o
+obj-$(CONFIG_DM_TEST) += test-uclass.o
+obj-$(CONFIG_DM_TEST) += ut.o
+
+# Tests for particular subsystems - when enabling driver model for a new
+# subsystem you must add sandbox tests here.
+obj-$(CONFIG_DM_TEST) += core.o
+obj-$(CONFIG_DM_TEST) += ut.o
+obj-$(CONFIG_DM_GPIO) += gpio.o
diff --git a/test/dm/cmd_dm.c b/test/dm/cmd_dm.c
new file mode 100644
index 0000000000..a03fe20f0d
--- /dev/null
+++ b/test/dm/cmd_dm.c
@@ -0,0 +1,133 @@
+/*
+ * Copyright (c) 2013 Google, Inc
+ *
+ * (C) Copyright 2012
+ * Marek Vasut <marex@denx.de>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <malloc.h>
+#include <errno.h>
+#include <asm/io.h>
+#include <dm/root.h>
+#include <dm/test.h>
+#include <dm/uclass-internal.h>
+
+static int display_succ(struct device *in, char *buf)
+{
+	int len;
+	int ip = 0;
+	char local[16];
+	struct device *pos, *n, *prev = NULL;
+
+	printf("%s- %s @ %08x", buf, in->name, map_to_sysmem(in));
+	if (in->flags & DM_FLAG_ACTIVATED)
+		puts(" - activated");
+	puts("\n");
+
+	if (list_empty(&in->child_head))
+		return 0;
+
+	len = strlen(buf);
+	strncpy(local, buf, sizeof(local));
+	snprintf(local + len, 2, "|");
+	if (len && local[len - 1] == '`')
+		local[len - 1] = ' ';
+
+	list_for_each_entry_safe(pos, n, &in->child_head, sibling_node) {
+		if (ip++)
+			display_succ(prev, local);
+		prev = pos;
+	}
+
+	snprintf(local + len, 2, "`");
+	display_succ(prev, local);
+
+	return 0;
+}
+
+static int dm_dump(struct device *dev)
+{
+	if (!dev)
+		return -EINVAL;
+	return display_succ(dev, "");
+}
+
+static int do_dm_dump_all(cmd_tbl_t *cmdtp, int flag, int argc,
+			  char * const argv[])
+{
+	struct device *root;
+
+	root = dm_root();
+	printf("ROOT %08x\n", map_to_sysmem(root));
+	return dm_dump(root);
+}
+
+static int do_dm_dump_uclass(cmd_tbl_t *cmdtp, int flag, int argc,
+			     char * const argv[])
+{
+	struct uclass *uc;
+	int ret;
+	int id;
+
+	for (id = 0; id < UCLASS_COUNT; id++) {
+		struct device *dev;
+
+		ret = uclass_get(id, &uc);
+		if (ret)
+			continue;
+
+		printf("uclass %d: %s\n", id, uc->uc_drv->name);
+		for (ret = uclass_first_device(id, &dev);
+		     dev;
+		     ret = uclass_next_device(&dev)) {
+			printf("  %s @  %08x:\n", dev->name,
+			       map_to_sysmem(dev));
+		}
+		puts("\n");
+	}
+
+	return 0;
+}
+
+static int do_dm_test(cmd_tbl_t *cmdtp, int flag, int argc,
+			  char * const argv[])
+{
+	return dm_test_main();
+}
+
+static cmd_tbl_t test_commands[] = {
+	U_BOOT_CMD_MKENT(tree, 0, 1, do_dm_dump_all, "", ""),
+	U_BOOT_CMD_MKENT(uclass, 1, 1, do_dm_dump_uclass, "", ""),
+	U_BOOT_CMD_MKENT(test, 1, 1, do_dm_test, "", ""),
+};
+
+static int do_dm(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	cmd_tbl_t *test_cmd;
+	int ret;
+
+	if (argc != 2)
+		return CMD_RET_USAGE;
+	test_cmd = find_cmd_tbl(argv[1], test_commands,
+				ARRAY_SIZE(test_commands));
+	argc -= 2;
+	argv += 2;
+	if (!test_cmd || argc > test_cmd->maxargs)
+		return CMD_RET_USAGE;
+
+	ret = test_cmd->cmd(test_cmd, flag, argc, argv);
+
+	return cmd_process_error(test_cmd, ret);
+}
+
+U_BOOT_CMD(
+	dm,	2,	1,	do_dm,
+	"Driver model low level access",
+	"tree         Dump driver model tree\n"
+	"dm uclass        Dump list of instances for each uclass\n"
+	"dm test         Run tests"
+);
diff --git a/test/dm/core.c b/test/dm/core.c
new file mode 100644
index 0000000000..14a57c3106
--- /dev/null
+++ b/test/dm/core.c
@@ -0,0 +1,544 @@
+/*
+ * Tests for the core driver model code
+ *
+ * Copyright (c) 2013 Google, Inc
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <errno.h>
+#include <dm.h>
+#include <fdtdec.h>
+#include <malloc.h>
+#include <dm/device-internal.h>
+#include <dm/root.h>
+#include <dm/ut.h>
+#include <dm/util.h>
+#include <dm/test.h>
+#include <dm/uclass-internal.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+enum {
+	TEST_INTVAL1		= 0,
+	TEST_INTVAL2		= 3,
+	TEST_INTVAL3		= 6,
+	TEST_INTVAL_MANUAL	= 101112,
+};
+
+static const struct dm_test_pdata test_pdata[] = {
+	{ .ping_add		= TEST_INTVAL1, },
+	{ .ping_add		= TEST_INTVAL2, },
+	{ .ping_add		= TEST_INTVAL3, },
+};
+
+static const struct dm_test_pdata test_pdata_manual = {
+	.ping_add		= TEST_INTVAL_MANUAL,
+};
+
+U_BOOT_DEVICE(dm_test_info1) = {
+	.name = "test_drv",
+	.platdata = &test_pdata[0],
+};
+
+U_BOOT_DEVICE(dm_test_info2) = {
+	.name = "test_drv",
+	.platdata = &test_pdata[1],
+};
+
+U_BOOT_DEVICE(dm_test_info3) = {
+	.name = "test_drv",
+	.platdata = &test_pdata[2],
+};
+
+static struct driver_info driver_info_manual = {
+	.name = "test_manual_drv",
+	.platdata = &test_pdata_manual,
+};
+
+/* Test that binding with platdata occurs correctly */
+static int dm_test_autobind(struct dm_test_state *dms)
+{
+	struct device *dev;
+
+	/*
+	 * We should have a single class (UCLASS_ROOT) and a single root
+	 * device with no children.
+	 */
+	ut_assert(dms->root);
+	ut_asserteq(1, list_count_items(&gd->uclass_root));
+	ut_asserteq(0, list_count_items(&gd->dm_root->child_head));
+	ut_asserteq(0, dm_testdrv_op_count[DM_TEST_OP_POST_BIND]);
+
+	ut_assertok(dm_scan_platdata());
+
+	/* We should have our test class now at least, plus more children */
+	ut_assert(1 < list_count_items(&gd->uclass_root));
+	ut_assert(0 < list_count_items(&gd->dm_root->child_head));
+
+	/* Our 3 dm_test_infox children should be bound to the test uclass */
+	ut_asserteq(3, dm_testdrv_op_count[DM_TEST_OP_POST_BIND]);
+
+	/* No devices should be probed */
+	list_for_each_entry(dev, &gd->dm_root->child_head, sibling_node)
+		ut_assert(!(dev->flags & DM_FLAG_ACTIVATED));
+
+	/* Our test driver should have been bound 3 times */
+	ut_assert(dm_testdrv_op_count[DM_TEST_OP_BIND] == 3);
+
+	return 0;
+}
+DM_TEST(dm_test_autobind, 0);
+
+/* Test that autoprobe finds all the expected devices */
+static int dm_test_autoprobe(struct dm_test_state *dms)
+{
+	int expected_base_add;
+	struct device *dev;
+	struct uclass *uc;
+	int i;
+
+	ut_assertok(uclass_get(UCLASS_TEST, &uc));
+	ut_assert(uc);
+
+	ut_asserteq(1, dm_testdrv_op_count[DM_TEST_OP_INIT]);
+	ut_asserteq(0, dm_testdrv_op_count[DM_TEST_OP_POST_PROBE]);
+
+	/* The root device should not be activated until needed */
+	ut_assert(!(dms->root->flags & DM_FLAG_ACTIVATED));
+
+	/*
+	 * We should be able to find the three test devices, and they should
+	 * all be activated as they are used (lazy activation, required by
+	 * U-Boot)
+	 */
+	for (i = 0; i < 3; i++) {
+		ut_assertok(uclass_find_device(UCLASS_TEST, i, &dev));
+		ut_assert(dev);
+		ut_assertf(!(dev->flags & DM_FLAG_ACTIVATED),
+			   "Driver %d/%s already activated", i, dev->name);
+
+		/* This should activate it */
+		ut_assertok(uclass_get_device(UCLASS_TEST, i, &dev));
+		ut_assert(dev);
+		ut_assert(dev->flags & DM_FLAG_ACTIVATED);
+
+		/* Activating a device should activate the root device */
+		if (!i)
+			ut_assert(dms->root->flags & DM_FLAG_ACTIVATED);
+	}
+
+	/* Our 3 dm_test_infox children should be passed to post_probe */
+	ut_asserteq(3, dm_testdrv_op_count[DM_TEST_OP_POST_PROBE]);
+
+	/* Also we can check the per-device data */
+	expected_base_add = 0;
+	for (i = 0; i < 3; i++) {
+		struct dm_test_uclass_perdev_priv *priv;
+		struct dm_test_pdata *pdata;
+
+		ut_assertok(uclass_find_device(UCLASS_TEST, i, &dev));
+		ut_assert(dev);
+
+		priv = dev->uclass_priv;
+		ut_assert(priv);
+		ut_asserteq(expected_base_add, priv->base_add);
+
+		pdata = dev->platdata;
+		expected_base_add += pdata->ping_add;
+	}
+
+	return 0;
+}
+DM_TEST(dm_test_autoprobe, DM_TESTF_SCAN_PDATA);
+
+/* Check that we see the correct platdata in each device */
+static int dm_test_platdata(struct dm_test_state *dms)
+{
+	const struct dm_test_pdata *pdata;
+	struct device *dev;
+	int i;
+
+	for (i = 0; i < 3; i++) {
+		ut_assertok(uclass_find_device(UCLASS_TEST, i, &dev));
+		ut_assert(dev);
+		pdata = dev->platdata;
+		ut_assert(pdata->ping_add == test_pdata[i].ping_add);
+	}
+
+	return 0;
+}
+DM_TEST(dm_test_platdata, DM_TESTF_SCAN_PDATA);
+
+/* Test that we can bind, probe, remove, unbind a driver */
+static int dm_test_lifecycle(struct dm_test_state *dms)
+{
+	int op_count[DM_TEST_OP_COUNT];
+	struct device *dev, *test_dev;
+	int pingret;
+	int ret;
+
+	memcpy(op_count, dm_testdrv_op_count, sizeof(op_count));
+
+	ut_assertok(device_bind_by_name(dms->root, &driver_info_manual,
+					&dev));
+	ut_assert(dev);
+	ut_assert(dm_testdrv_op_count[DM_TEST_OP_BIND]
+			== op_count[DM_TEST_OP_BIND] + 1);
+	ut_assert(!dev->priv);
+
+	/* Probe the device - it should fail allocating private data */
+	dms->force_fail_alloc = 1;
+	ret = device_probe(dev);
+	ut_assert(ret == -ENOMEM);
+	ut_assert(dm_testdrv_op_count[DM_TEST_OP_PROBE]
+			== op_count[DM_TEST_OP_PROBE] + 1);
+	ut_assert(!dev->priv);
+
+	/* Try again without the alloc failure */
+	dms->force_fail_alloc = 0;
+	ut_assertok(device_probe(dev));
+	ut_assert(dm_testdrv_op_count[DM_TEST_OP_PROBE]
+			== op_count[DM_TEST_OP_PROBE] + 2);
+	ut_assert(dev->priv);
+
+	/* This should be device 3 in the uclass */
+	ut_assertok(uclass_find_device(UCLASS_TEST, 3, &test_dev));
+	ut_assert(dev == test_dev);
+
+	/* Try ping */
+	ut_assertok(test_ping(dev, 100, &pingret));
+	ut_assert(pingret == 102);
+
+	/* Now remove device 3 */
+	ut_asserteq(0, dm_testdrv_op_count[DM_TEST_OP_PRE_REMOVE]);
+	ut_assertok(device_remove(dev));
+	ut_asserteq(1, dm_testdrv_op_count[DM_TEST_OP_PRE_REMOVE]);
+
+	ut_asserteq(0, dm_testdrv_op_count[DM_TEST_OP_UNBIND]);
+	ut_asserteq(0, dm_testdrv_op_count[DM_TEST_OP_PRE_UNBIND]);
+	ut_assertok(device_unbind(dev));
+	ut_asserteq(1, dm_testdrv_op_count[DM_TEST_OP_UNBIND]);
+	ut_asserteq(1, dm_testdrv_op_count[DM_TEST_OP_PRE_UNBIND]);
+
+	return 0;
+}
+DM_TEST(dm_test_lifecycle, DM_TESTF_SCAN_PDATA | DM_TESTF_PROBE_TEST);
+
+/* Test that we can bind/unbind and the lists update correctly */
+static int dm_test_ordering(struct dm_test_state *dms)
+{
+	struct device *dev, *dev_penultimate, *dev_last, *test_dev;
+	int pingret;
+
+	ut_assertok(device_bind_by_name(dms->root, &driver_info_manual,
+					&dev));
+	ut_assert(dev);
+
+	/* Bind two new devices (numbers 4 and 5) */
+	ut_assertok(device_bind_by_name(dms->root, &driver_info_manual,
+					&dev_penultimate));
+	ut_assert(dev_penultimate);
+	ut_assertok(device_bind_by_name(dms->root, &driver_info_manual,
+					&dev_last));
+	ut_assert(dev_last);
+
+	/* Now remove device 3 */
+	ut_assertok(device_remove(dev));
+	ut_assertok(device_unbind(dev));
+
+	/* The device numbering should have shifted down one */
+	ut_assertok(uclass_find_device(UCLASS_TEST, 3, &test_dev));
+	ut_assert(dev_penultimate == test_dev);
+	ut_assertok(uclass_find_device(UCLASS_TEST, 4, &test_dev));
+	ut_assert(dev_last == test_dev);
+
+	/* Add back the original device 3, now in position 5 */
+	ut_assertok(device_bind_by_name(dms->root, &driver_info_manual, &dev));
+	ut_assert(dev);
+
+	/* Try ping */
+	ut_assertok(test_ping(dev, 100, &pingret));
+	ut_assert(pingret == 102);
+
+	/* Remove 3 and 4 */
+	ut_assertok(device_remove(dev_penultimate));
+	ut_assertok(device_unbind(dev_penultimate));
+	ut_assertok(device_remove(dev_last));
+	ut_assertok(device_unbind(dev_last));
+
+	/* Our device should now be in position 3 */
+	ut_assertok(uclass_find_device(UCLASS_TEST, 3, &test_dev));
+	ut_assert(dev == test_dev);
+
+	/* Now remove device 3 */
+	ut_assertok(device_remove(dev));
+	ut_assertok(device_unbind(dev));
+
+	return 0;
+}
+DM_TEST(dm_test_ordering, DM_TESTF_SCAN_PDATA);
+
+/* Check that we can perform operations on a device (do a ping) */
+int dm_check_operations(struct dm_test_state *dms, struct device *dev,
+			uint32_t base, struct dm_test_priv *priv)
+{
+	int expected;
+	int pingret;
+
+	/* Getting the child device should allocate platdata / priv */
+	ut_assertok(testfdt_ping(dev, 10, &pingret));
+	ut_assert(dev->priv);
+	ut_assert(dev->platdata);
+
+	expected = 10 + base;
+	ut_asserteq(expected, pingret);
+
+	/* Do another ping */
+	ut_assertok(testfdt_ping(dev, 20, &pingret));
+	expected = 20 + base;
+	ut_asserteq(expected, pingret);
+
+	/* Now check the ping_total */
+	priv = dev->priv;
+	ut_asserteq(DM_TEST_START_TOTAL + 10 + 20 + base * 2,
+		    priv->ping_total);
+
+	return 0;
+}
+
+/* Check that we can perform operations on devices */
+static int dm_test_operations(struct dm_test_state *dms)
+{
+	struct device *dev;
+	int i;
+
+	/*
+	 * Now check that the ping adds are what we expect. This is using the
+	 * ping-add property in each node.
+	 */
+	for (i = 0; i < ARRAY_SIZE(test_pdata); i++) {
+		uint32_t base;
+
+		ut_assertok(uclass_get_device(UCLASS_TEST, i, &dev));
+
+		/*
+		 * Get the 'reg' property, which tells us what the ping add
+		 * should be. We don't use the platdata because we want
+		 * to test the code that sets that up (testfdt_drv_probe()).
+		 */
+		base = test_pdata[i].ping_add;
+		debug("dev=%d, base=%d\n", i, base);
+
+		ut_assert(!dm_check_operations(dms, dev, base, dev->priv));
+	}
+
+	return 0;
+}
+DM_TEST(dm_test_operations, DM_TESTF_SCAN_PDATA);
+
+/* Remove all drivers and check that things work */
+static int dm_test_remove(struct dm_test_state *dms)
+{
+	struct device *dev;
+	int i;
+
+	for (i = 0; i < 3; i++) {
+		ut_assertok(uclass_find_device(UCLASS_TEST, i, &dev));
+		ut_assert(dev);
+		ut_assertf(dev->flags & DM_FLAG_ACTIVATED,
+			   "Driver %d/%s not activated", i, dev->name);
+		ut_assertok(device_remove(dev));
+		ut_assertf(!(dev->flags & DM_FLAG_ACTIVATED),
+			   "Driver %d/%s should have deactivated", i,
+			   dev->name);
+		ut_assert(!dev->priv);
+	}
+
+	return 0;
+}
+DM_TEST(dm_test_remove, DM_TESTF_SCAN_PDATA | DM_TESTF_PROBE_TEST);
+
+/* Remove and recreate everything, check for memory leaks */
+static int dm_test_leak(struct dm_test_state *dms)
+{
+	int i;
+
+	for (i = 0; i < 2; i++) {
+		struct mallinfo start, end;
+		struct device *dev;
+		int ret;
+		int id;
+
+		start = mallinfo();
+		if (!start.uordblks)
+			puts("Warning: Please add '#define DEBUG' to the top of common/dlmalloc.c\n");
+
+		ut_assertok(dm_scan_platdata());
+		ut_assertok(dm_scan_fdt(gd->fdt_blob));
+
+		/* Scanning the uclass is enough to probe all the devices */
+		for (id = UCLASS_ROOT; id < UCLASS_COUNT; id++) {
+			for (ret = uclass_first_device(UCLASS_TEST, &dev);
+			     dev;
+			     ret = uclass_next_device(&dev))
+				;
+			ut_assertok(ret);
+		}
+
+		/* Don't delete the root class, since we started with that */
+		for (id = UCLASS_ROOT + 1; id < UCLASS_COUNT; id++) {
+			struct uclass *uc;
+
+			uc = uclass_find(id);
+			if (!uc)
+				continue;
+			ut_assertok(uclass_destroy(uc));
+		}
+
+		end = mallinfo();
+		ut_asserteq(start.uordblks, end.uordblks);
+	}
+
+	return 0;
+}
+DM_TEST(dm_test_leak, 0);
+
+/* Test uclass init/destroy methods */
+static int dm_test_uclass(struct dm_test_state *dms)
+{
+	struct uclass *uc;
+
+	ut_assertok(uclass_get(UCLASS_TEST, &uc));
+	ut_asserteq(1, dm_testdrv_op_count[DM_TEST_OP_INIT]);
+	ut_asserteq(0, dm_testdrv_op_count[DM_TEST_OP_DESTROY]);
+	ut_assert(uc->priv);
+
+	ut_assertok(uclass_destroy(uc));
+	ut_asserteq(1, dm_testdrv_op_count[DM_TEST_OP_INIT]);
+	ut_asserteq(1, dm_testdrv_op_count[DM_TEST_OP_DESTROY]);
+
+	return 0;
+}
+DM_TEST(dm_test_uclass, 0);
+
+/**
+ * create_children() - Create children of a parent node
+ *
+ * @dms:	Test system state
+ * @parent:	Parent device
+ * @count:	Number of children to create
+ * @key:	Key value to put in first child. Subsequence children
+ *		receive an incrementing value
+ * @child:	If not NULL, then the child device pointers are written into
+ *		this array.
+ * @return 0 if OK, -ve on error
+ */
+static int create_children(struct dm_test_state *dms, struct device *parent,
+			   int count, int key, struct device *child[])
+{
+	struct device *dev;
+	int i;
+
+	for (i = 0; i < count; i++) {
+		struct dm_test_pdata *pdata;
+
+		ut_assertok(device_bind_by_name(parent, &driver_info_manual,
+						&dev));
+		pdata = calloc(1, sizeof(*pdata));
+		pdata->ping_add = key + i;
+		dev->platdata = pdata;
+		if (child)
+			child[i] = dev;
+	}
+
+	return 0;
+}
+
+#define NODE_COUNT	10
+
+static int dm_test_children(struct dm_test_state *dms)
+{
+	struct device *top[NODE_COUNT];
+	struct device *child[NODE_COUNT];
+	struct device *grandchild[NODE_COUNT];
+	struct device *dev;
+	int total;
+	int ret;
+	int i;
+
+	/* We don't care about the numbering for this test */
+	dms->skip_post_probe = 1;
+
+	ut_assert(NODE_COUNT > 5);
+
+	/* First create 10 top-level children */
+	ut_assertok(create_children(dms, dms->root, NODE_COUNT, 0, top));
+
+	/* Now a few have their own children */
+	ut_assertok(create_children(dms, top[2], NODE_COUNT, 2, NULL));
+	ut_assertok(create_children(dms, top[5], NODE_COUNT, 5, child));
+
+	/* And grandchildren */
+	for (i = 0; i < NODE_COUNT; i++)
+		ut_assertok(create_children(dms, child[i], NODE_COUNT, 50 * i,
+					    i == 2 ? grandchild : NULL));
+
+	/* Check total number of devices */
+	total = NODE_COUNT * (3 + NODE_COUNT);
+	ut_asserteq(total, dm_testdrv_op_count[DM_TEST_OP_BIND]);
+
+	/* Try probing one of the grandchildren */
+	ut_assertok(uclass_get_device(UCLASS_TEST,
+				      NODE_COUNT * 3 + 2 * NODE_COUNT, &dev));
+	ut_asserteq_ptr(grandchild[0], dev);
+
+	/*
+	 * This should have probed the child and top node also, for a total
+	 * of 3 nodes.
+	 */
+	ut_asserteq(3, dm_testdrv_op_count[DM_TEST_OP_PROBE]);
+
+	/* Probe the other grandchildren */
+	for (i = 1; i < NODE_COUNT; i++)
+		ut_assertok(device_probe(grandchild[i]));
+
+	ut_asserteq(2 + NODE_COUNT, dm_testdrv_op_count[DM_TEST_OP_PROBE]);
+
+	/* Probe everything */
+	for (ret = uclass_first_device(UCLASS_TEST, &dev);
+	     dev;
+	     ret = uclass_next_device(&dev))
+		;
+	ut_assertok(ret);
+
+	ut_asserteq(total, dm_testdrv_op_count[DM_TEST_OP_PROBE]);
+
+	/* Remove a top-level child and check that the children are removed */
+	ut_assertok(device_remove(top[2]));
+	ut_asserteq(NODE_COUNT + 1, dm_testdrv_op_count[DM_TEST_OP_REMOVE]);
+	dm_testdrv_op_count[DM_TEST_OP_REMOVE] = 0;
+
+	/* Try one with grandchildren */
+	ut_assertok(uclass_get_device(UCLASS_TEST, 5, &dev));
+	ut_asserteq_ptr(dev, top[5]);
+	ut_assertok(device_remove(dev));
+	ut_asserteq(1 + NODE_COUNT * (1 + NODE_COUNT),
+		    dm_testdrv_op_count[DM_TEST_OP_REMOVE]);
+
+	/* Try the same with unbind */
+	ut_assertok(device_unbind(top[2]));
+	ut_asserteq(NODE_COUNT + 1, dm_testdrv_op_count[DM_TEST_OP_UNBIND]);
+	dm_testdrv_op_count[DM_TEST_OP_UNBIND] = 0;
+
+	/* Try one with grandchildren */
+	ut_assertok(uclass_get_device(UCLASS_TEST, 5, &dev));
+	ut_asserteq_ptr(dev, top[6]);
+	ut_assertok(device_unbind(top[5]));
+	ut_asserteq(1 + NODE_COUNT * (1 + NODE_COUNT),
+		    dm_testdrv_op_count[DM_TEST_OP_UNBIND]);
+
+	return 0;
+}
+DM_TEST(dm_test_children, 0);
diff --git a/test/dm/gpio.c b/test/dm/gpio.c
new file mode 100644
index 0000000000..bf632bca54
--- /dev/null
+++ b/test/dm/gpio.c
@@ -0,0 +1,111 @@
+/*
+ * Copyright (C) 2013 Google, Inc
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <fdtdec.h>
+#include <dm.h>
+#include <dm/ut.h>
+#include <dm/test.h>
+#include <dm/util.h>
+#include <asm/gpio.h>
+
+/* Test that sandbox GPIOs work correctly */
+static int dm_test_gpio(struct dm_test_state *dms)
+{
+	unsigned int offset, gpio;
+	struct dm_gpio_ops *ops;
+	struct device *dev;
+	const char *name;
+	int offset_count;
+	char buf[80];
+
+	/*
+	 * We expect to get 3 banks. One is anonymous (just numbered) and
+	 * comes from platdata. The other two are named a (20 gpios)
+	 * and b (10 gpios) and come from the device tree. See
+	 * test/dm/test.dts.
+	 */
+	ut_assertok(gpio_lookup_name("b4", &dev, &offset, &gpio));
+	ut_asserteq_str(dev->name, "extra-gpios");
+	ut_asserteq(4, offset);
+	ut_asserteq(CONFIG_SANDBOX_GPIO_COUNT + 20 + 4, gpio);
+
+	name = gpio_get_bank_info(dev, &offset_count);
+	ut_asserteq_str("b", name);
+	ut_asserteq(10, offset_count);
+
+	/* Get the operations for this device */
+	ops = gpio_get_ops(dev);
+	ut_assert(ops->get_state);
+
+	/* Cannot get a value until it is reserved */
+	ut_asserteq(-1, ops->get_value(dev, offset));
+
+	/*
+	 * Now some tests that use the 'sandbox' back door. All GPIOs
+	 * should default to input, include b4 that we are using here.
+	 */
+	ut_assertok(ops->get_state(dev, offset, buf, sizeof(buf)));
+	ut_asserteq_str("b4:  in: 0 [ ]", buf);
+
+	/* Change it to an output */
+	sandbox_gpio_set_direction(dev, offset, 1);
+	ut_assertok(ops->get_state(dev, offset, buf, sizeof(buf)));
+	ut_asserteq_str("b4: out: 0 [ ]", buf);
+
+	sandbox_gpio_set_value(dev, offset, 1);
+	ut_assertok(ops->get_state(dev, offset, buf, sizeof(buf)));
+	ut_asserteq_str("b4: out: 1 [ ]", buf);
+
+	ut_assertok(ops->request(dev, offset, "testing"));
+	ut_assertok(ops->get_state(dev, offset, buf, sizeof(buf)));
+	ut_asserteq_str("b4: out: 1 [x] testing", buf);
+
+	/* Change the value a bit */
+	ut_asserteq(1, ops->get_value(dev, offset));
+	ut_assertok(ops->set_value(dev, offset, 0));
+	ut_asserteq(0, ops->get_value(dev, offset));
+	ut_assertok(ops->get_state(dev, offset, buf, sizeof(buf)));
+	ut_asserteq_str("b4: out: 0 [x] testing", buf);
+	ut_assertok(ops->set_value(dev, offset, 1));
+	ut_asserteq(1, ops->get_value(dev, offset));
+
+	/* Make it an input */
+	ut_assertok(ops->direction_input(dev, offset));
+	ut_assertok(ops->get_state(dev, offset, buf, sizeof(buf)));
+	ut_asserteq_str("b4:  in: 1 [x] testing", buf);
+	sandbox_gpio_set_value(dev, offset, 0);
+	ut_asserteq(0, sandbox_gpio_get_value(dev, offset));
+	ut_assertok(ops->get_state(dev, offset, buf, sizeof(buf)));
+	ut_asserteq_str("b4:  in: 0 [x] testing", buf);
+
+	ut_assertok(ops->free(dev, offset));
+	ut_assertok(ops->get_state(dev, offset, buf, sizeof(buf)));
+	ut_asserteq_str("b4:  in: 0 [ ]", buf);
+
+	/* Check the 'a' bank also */
+	ut_assertok(gpio_lookup_name("a15", &dev, &offset, &gpio));
+	ut_asserteq_str(dev->name, "base-gpios");
+	ut_asserteq(15, offset);
+	ut_asserteq(CONFIG_SANDBOX_GPIO_COUNT + 15, gpio);
+
+	name = gpio_get_bank_info(dev, &offset_count);
+	ut_asserteq_str("a", name);
+	ut_asserteq(20, offset_count);
+
+	/* And the anonymous bank */
+	ut_assertok(gpio_lookup_name("14", &dev, &offset, &gpio));
+	ut_asserteq_str(dev->name, "gpio_sandbox");
+	ut_asserteq(14, offset);
+	ut_asserteq(14, gpio);
+
+	name = gpio_get_bank_info(dev, &offset_count);
+	ut_asserteq_ptr(NULL, name);
+	ut_asserteq(CONFIG_SANDBOX_GPIO_COUNT, offset_count);
+
+	return 0;
+}
+DM_TEST(dm_test_gpio, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT);
diff --git a/test/dm/test-dm.sh b/test/dm/test-dm.sh
new file mode 100755
index 0000000000..ef5aca5ac3
--- /dev/null
+++ b/test/dm/test-dm.sh
@@ -0,0 +1,7 @@
+#!/bin/sh
+
+NUM_CPUS=$(cat /proc/cpuinfo |grep -c processor)
+dtc -I dts -O dtb test/dm/test.dts -o test/dm/test.dtb
+make O=sandbox sandbox_config
+make O=sandbox -s -j${NUM_CPUS}
+./sandbox/u-boot -d test/dm/test.dtb -c "dm test"
diff --git a/test/dm/test-driver.c b/test/dm/test-driver.c
new file mode 100644
index 0000000000..c4be8a12d7
--- /dev/null
+++ b/test/dm/test-driver.c
@@ -0,0 +1,146 @@
+/*
+ * Copyright (c) 2013 Google, Inc
+ *
+ * (C) Copyright 2012
+ * Pavel Herrmann <morpheus.ibis@gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <errno.h>
+#include <malloc.h>
+#include <dm/test.h>
+#include <dm/ut.h>
+#include <asm/io.h>
+
+int dm_testdrv_op_count[DM_TEST_OP_COUNT];
+static struct dm_test_state *dms = &global_test_state;
+
+static int testdrv_ping(struct device *dev, int pingval, int *pingret)
+{
+	const struct dm_test_pdata *pdata = dev_get_platdata(dev);
+	struct dm_test_priv *priv = dev_get_priv(dev);
+
+	*pingret = pingval + pdata->ping_add;
+	priv->ping_total += *pingret;
+
+	return 0;
+}
+
+static const struct test_ops test_ops = {
+	.ping = testdrv_ping,
+};
+
+static int test_bind(struct device *dev)
+{
+	/* Private data should not be allocated */
+	ut_assert(!dev_get_priv(dev));
+
+	dm_testdrv_op_count[DM_TEST_OP_BIND]++;
+	return 0;
+}
+
+static int test_probe(struct device *dev)
+{
+	struct dm_test_priv *priv = dev_get_priv(dev);
+
+	/* Private data should be allocated */
+	ut_assert(priv);
+
+	dm_testdrv_op_count[DM_TEST_OP_PROBE]++;
+	priv->ping_total += DM_TEST_START_TOTAL;
+	return 0;
+}
+
+static int test_remove(struct device *dev)
+{
+	/* Private data should still be allocated */
+	ut_assert(dev_get_priv(dev));
+
+	dm_testdrv_op_count[DM_TEST_OP_REMOVE]++;
+	return 0;
+}
+
+static int test_unbind(struct device *dev)
+{
+	/* Private data should not be allocated */
+	ut_assert(!dev->priv);
+
+	dm_testdrv_op_count[DM_TEST_OP_UNBIND]++;
+	return 0;
+}
+
+U_BOOT_DRIVER(test_drv) = {
+	.name	= "test_drv",
+	.id	= UCLASS_TEST,
+	.ops	= &test_ops,
+	.bind	= test_bind,
+	.probe	= test_probe,
+	.remove	= test_remove,
+	.unbind	= test_unbind,
+	.priv_auto_alloc_size = sizeof(struct dm_test_priv),
+};
+
+U_BOOT_DRIVER(test2_drv) = {
+	.name	= "test2_drv",
+	.id	= UCLASS_TEST,
+	.ops	= &test_ops,
+	.bind	= test_bind,
+	.probe	= test_probe,
+	.remove	= test_remove,
+	.unbind	= test_unbind,
+	.priv_auto_alloc_size = sizeof(struct dm_test_priv),
+};
+
+static int test_manual_drv_ping(struct device *dev, int pingval, int *pingret)
+{
+	*pingret = pingval + 2;
+
+	return 0;
+}
+
+static const struct test_ops test_manual_ops = {
+	.ping = test_manual_drv_ping,
+};
+
+static int test_manual_bind(struct device *dev)
+{
+	dm_testdrv_op_count[DM_TEST_OP_BIND]++;
+
+	return 0;
+}
+
+static int test_manual_probe(struct device *dev)
+{
+	dm_testdrv_op_count[DM_TEST_OP_PROBE]++;
+	if (!dms->force_fail_alloc)
+		dev->priv = calloc(1, sizeof(struct dm_test_priv));
+	if (!dev->priv)
+		return -ENOMEM;
+
+	return 0;
+}
+
+static int test_manual_remove(struct device *dev)
+{
+	dm_testdrv_op_count[DM_TEST_OP_REMOVE]++;
+	return 0;
+}
+
+static int test_manual_unbind(struct device *dev)
+{
+	dm_testdrv_op_count[DM_TEST_OP_UNBIND]++;
+	return 0;
+}
+
+U_BOOT_DRIVER(test_manual_drv) = {
+	.name	= "test_manual_drv",
+	.id	= UCLASS_TEST,
+	.ops	= &test_manual_ops,
+	.bind	= test_manual_bind,
+	.probe	= test_manual_probe,
+	.remove	= test_manual_remove,
+	.unbind	= test_manual_unbind,
+};
diff --git a/test/dm/test-fdt.c b/test/dm/test-fdt.c
new file mode 100644
index 0000000000..e1d982fd7d
--- /dev/null
+++ b/test/dm/test-fdt.c
@@ -0,0 +1,144 @@
+/*
+ * Copyright (c) 2013 Google, Inc
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <errno.h>
+#include <fdtdec.h>
+#include <malloc.h>
+#include <asm/io.h>
+#include <dm/test.h>
+#include <dm/root.h>
+#include <dm/ut.h>
+#include <dm/uclass-internal.h>
+#include <dm/util.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static int testfdt_drv_ping(struct device *dev, int pingval, int *pingret)
+{
+	const struct dm_test_pdata *pdata = dev->platdata;
+	struct dm_test_priv *priv = dev_get_priv(dev);
+
+	*pingret = pingval + pdata->ping_add;
+	priv->ping_total += *pingret;
+
+	return 0;
+}
+
+static const struct test_ops test_ops = {
+	.ping = testfdt_drv_ping,
+};
+
+static int testfdt_ofdata_to_platdata(struct device *dev)
+{
+	struct dm_test_pdata *pdata = dev_get_platdata(dev);
+
+	pdata->ping_add = fdtdec_get_int(gd->fdt_blob, dev->of_offset,
+					"ping-add", -1);
+	pdata->base = fdtdec_get_addr(gd->fdt_blob, dev->of_offset, "reg");
+
+	return 0;
+}
+
+static int testfdt_drv_probe(struct device *dev)
+{
+	struct dm_test_priv *priv = dev_get_priv(dev);
+
+	priv->ping_total += DM_TEST_START_TOTAL;
+
+	return 0;
+}
+
+static const struct device_id testfdt_ids[] = {
+	{
+		.compatible = "denx,u-boot-fdt-test",
+		.data = DM_TEST_TYPE_FIRST },
+	{
+		.compatible = "google,another-fdt-test",
+		.data = DM_TEST_TYPE_SECOND },
+	{ }
+};
+
+U_BOOT_DRIVER(testfdt_drv) = {
+	.name	= "testfdt_drv",
+	.of_match	= testfdt_ids,
+	.id	= UCLASS_TEST_FDT,
+	.ofdata_to_platdata = testfdt_ofdata_to_platdata,
+	.probe	= testfdt_drv_probe,
+	.ops	= &test_ops,
+	.priv_auto_alloc_size = sizeof(struct dm_test_priv),
+	.platdata_auto_alloc_size = sizeof(struct dm_test_pdata),
+};
+
+/* From here is the testfdt uclass code */
+int testfdt_ping(struct device *dev, int pingval, int *pingret)
+{
+	const struct test_ops *ops = device_get_ops(dev);
+
+	if (!ops->ping)
+		return -ENOSYS;
+
+	return ops->ping(dev, pingval, pingret);
+}
+
+UCLASS_DRIVER(testfdt) = {
+	.name		= "testfdt",
+	.id		= UCLASS_TEST_FDT,
+};
+
+/* Test that FDT-based binding works correctly */
+static int dm_test_fdt(struct dm_test_state *dms)
+{
+	const int num_drivers = 3;
+	struct device *dev;
+	struct uclass *uc;
+	int ret;
+	int i;
+
+	ret = dm_scan_fdt(gd->fdt_blob);
+	ut_assert(!ret);
+
+	ret = uclass_get(UCLASS_TEST_FDT, &uc);
+	ut_assert(!ret);
+
+	/* These are num_drivers compatible root-level device tree nodes */
+	ut_asserteq(num_drivers, list_count_items(&uc->dev_head));
+
+	/* Each should have no platdata / priv */
+	for (i = 0; i < num_drivers; i++) {
+		ret = uclass_find_device(UCLASS_TEST_FDT, i, &dev);
+		ut_assert(!ret);
+		ut_assert(!dev_get_priv(dev));
+		ut_assert(!dev->platdata);
+	}
+
+	/*
+	 * Now check that the ping adds are what we expect. This is using the
+	 * ping-add property in each node.
+	 */
+	for (i = 0; i < num_drivers; i++) {
+		uint32_t base;
+
+		ret = uclass_get_device(UCLASS_TEST_FDT, i, &dev);
+		ut_assert(!ret);
+
+		/*
+		 * Get the 'reg' property, which tells us what the ping add
+		 * should be. We don't use the platdata because we want
+		 * to test the code that sets that up (testfdt_drv_probe()).
+		 */
+		base = fdtdec_get_addr(gd->fdt_blob, dev->of_offset, "reg");
+		debug("dev=%d, base=%d: %s\n", i, base,
+		      fdt_get_name(gd->fdt_blob, dev->of_offset, NULL));
+
+		ut_assert(!dm_check_operations(dms, dev, base,
+					       dev_get_priv(dev)));
+	}
+
+	return 0;
+}
+DM_TEST(dm_test_fdt, 0);
diff --git a/test/dm/test-main.c b/test/dm/test-main.c
new file mode 100644
index 0000000000..828ed46f8e
--- /dev/null
+++ b/test/dm/test-main.c
@@ -0,0 +1,107 @@
+/*
+ * Copyright (c) 2013 Google, Inc
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <errno.h>
+#include <dm/test.h>
+#include <dm/root.h>
+#include <dm/uclass-internal.h>
+#include <dm/ut.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct dm_test_state global_test_state;
+
+/* Get ready for testing */
+static int dm_test_init(struct dm_test_state *dms)
+{
+	memset(dms, '\0', sizeof(*dms));
+	gd->dm_root = NULL;
+	memset(dm_testdrv_op_count, '\0', sizeof(dm_testdrv_op_count));
+
+	ut_assertok(dm_init());
+	dms->root = dm_root();
+
+	return 0;
+}
+
+/* Ensure all the test devices are probed */
+static int do_autoprobe(struct dm_test_state *dms)
+{
+	struct device *dev;
+	int ret;
+
+	/* Scanning the uclass is enough to probe all the devices */
+	for (ret = uclass_first_device(UCLASS_TEST, &dev);
+	     dev;
+	     ret = uclass_next_device(&dev))
+		;
+
+	return ret;
+}
+
+static int dm_test_destroy(struct dm_test_state *dms)
+{
+	int id;
+
+	for (id = 0; id < UCLASS_COUNT; id++) {
+		struct uclass *uc;
+
+		/*
+		 * If the uclass doesn't exist we don't want to create it. So
+		 * check that here before we call uclass_find_device()/
+		 */
+		uc = uclass_find(id);
+		if (!uc)
+			continue;
+		ut_assertok(uclass_destroy(uc));
+	}
+
+	return 0;
+}
+
+int dm_test_main(void)
+{
+	struct dm_test *tests = ll_entry_start(struct dm_test, dm_test);
+	const int n_ents = ll_entry_count(struct dm_test, dm_test);
+	struct dm_test_state *dms = &global_test_state;
+	struct dm_test *test;
+
+	/*
+	 * If we have no device tree, or it only has a root node, then these
+	 * tests clearly aren't going to work...
+	 */
+	if (!gd->fdt_blob || fdt_next_node(gd->fdt_blob, 0, NULL) < 0) {
+		puts("Please run with test device tree:\n"
+		     "     dtc -I dts -O dtb test/dm/test.dts  -o test/dm/test.dtb\n"
+		     "    ./u-boot -d test/dm/test.dtb\n");
+		ut_assert(gd->fdt_blob);
+	}
+
+	printf("Running %d driver model tests\n", n_ents);
+
+	for (test = tests; test < tests + n_ents; test++) {
+		printf("Test: %s\n", test->name);
+		ut_assertok(dm_test_init(dms));
+
+		if (test->flags & DM_TESTF_SCAN_PDATA)
+			ut_assertok(dm_scan_platdata());
+		if (test->flags & DM_TESTF_PROBE_TEST)
+			ut_assertok(do_autoprobe(dms));
+		if (test->flags & DM_TESTF_SCAN_FDT)
+			ut_assertok(dm_scan_fdt(gd->fdt_blob));
+
+		if (test->func(dms))
+			break;
+
+		ut_assertok(dm_test_destroy(dms));
+	}
+
+	printf("Failures: %d\n", dms->fail_count);
+
+	return 0;
+}
diff --git a/test/dm/test-uclass.c b/test/dm/test-uclass.c
new file mode 100644
index 0000000000..8b564b89d9
--- /dev/null
+++ b/test/dm/test-uclass.c
@@ -0,0 +1,104 @@
+/*
+ * Copyright (c) 2013 Google, Inc
+ *
+ * (C) Copyright 2012
+ * Pavel Herrmann <morpheus.ibis@gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <malloc.h>
+#include <dm.h>
+#include <errno.h>
+#include <dm/test.h>
+#include <dm/ut.h>
+#include <asm/io.h>
+#include <linux/list.h>
+
+static struct dm_test_state *dms = &global_test_state;
+
+int test_ping(struct device *dev, int pingval, int *pingret)
+{
+	const struct test_ops *ops = device_get_ops(dev);
+
+	if (!ops->ping)
+		return -ENOSYS;
+
+	return ops->ping(dev, pingval, pingret);
+}
+
+static int test_post_bind(struct device *dev)
+{
+	dm_testdrv_op_count[DM_TEST_OP_POST_BIND]++;
+
+	return 0;
+}
+
+static int test_pre_unbind(struct device *dev)
+{
+	dm_testdrv_op_count[DM_TEST_OP_PRE_UNBIND]++;
+
+	return 0;
+}
+
+static int test_post_probe(struct device *dev)
+{
+	struct device *prev = list_entry(dev->uclass_node.prev, struct device,
+					 uclass_node);
+	struct dm_test_uclass_perdev_priv *priv = dev->uclass_priv;
+	struct uclass *uc = dev->uclass;
+
+	dm_testdrv_op_count[DM_TEST_OP_POST_PROBE]++;
+	ut_assert(priv);
+	ut_assert(device_active(dev));
+	priv->base_add = 0;
+	if (dms->skip_post_probe)
+		return 0;
+	if (&prev->uclass_node != &uc->dev_head) {
+		struct dm_test_uclass_perdev_priv *prev_uc_priv
+				= prev->uclass_priv;
+		struct dm_test_pdata *pdata = prev->platdata;
+
+		ut_assert(pdata);
+		ut_assert(prev_uc_priv);
+		priv->base_add = prev_uc_priv->base_add + pdata->ping_add;
+	}
+
+	return 0;
+}
+
+static int test_pre_remove(struct device *dev)
+{
+	dm_testdrv_op_count[DM_TEST_OP_PRE_REMOVE]++;
+
+	return 0;
+}
+
+static int test_init(struct uclass *uc)
+{
+	dm_testdrv_op_count[DM_TEST_OP_INIT]++;
+	ut_assert(uc->priv);
+
+	return 0;
+}
+
+static int test_destroy(struct uclass *uc)
+{
+	dm_testdrv_op_count[DM_TEST_OP_DESTROY]++;
+
+	return 0;
+}
+
+UCLASS_DRIVER(test) = {
+	.name		= "test",
+	.id		= UCLASS_TEST,
+	.post_bind	= test_post_bind,
+	.pre_unbind	= test_pre_unbind,
+	.post_probe	= test_post_probe,
+	.pre_remove	= test_pre_remove,
+	.init		= test_init,
+	.destroy	= test_destroy,
+	.priv_auto_alloc_size	= sizeof(struct dm_test_uclass_priv),
+	.per_device_auto_alloc_size = sizeof(struct dm_test_uclass_perdev_priv),
+};
diff --git a/test/dm/test.dts b/test/dm/test.dts
new file mode 100644
index 0000000000..ec5364f7c7
--- /dev/null
+++ b/test/dm/test.dts
@@ -0,0 +1,59 @@
+/dts-v1/;
+
+/ {
+	model = "sandbox";
+	compatible = "sandbox";
+	#address-cells = <1>;
+	#size-cells = <0>;
+
+	a-test {
+		reg = <0>;
+		compatible = "denx,u-boot-fdt-test";
+		ping-add = <0>;
+	};
+
+	junk {
+		reg = <1>;
+		compatible = "not,compatible";
+	};
+
+	no-compatible {
+		reg = <2>;
+	};
+
+	b-test {
+		reg = <3>;
+		compatible = "denx,u-boot-fdt-test";
+		ping-add = <3>;
+	};
+
+	some-bus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		reg = <4>;
+		ping-add = <4>;
+		c-test {
+			compatible = "denx,u-boot-fdt-test";
+			reg = <5>;
+			ping-add = <5>;
+		};
+	};
+
+	d-test {
+		reg = <6>;
+		ping-add = <6>;
+		compatible = "google,another-fdt-test";
+	};
+
+	base-gpios {
+		compatible = "sandbox,gpio";
+		gpio-bank-name = "a";
+		num-gpios = <20>;
+	};
+
+	extra-gpios {
+		compatible = "sandbox,gpio";
+		gpio-bank-name = "b";
+		num-gpios = <10>;
+	};
+};
diff --git a/test/dm/ut.c b/test/dm/ut.c
new file mode 100644
index 0000000000..8b69bc2ab1
--- /dev/null
+++ b/test/dm/ut.c
@@ -0,0 +1,33 @@
+/*
+ * Simple unit test library for driver model
+ *
+ * Copyright (c) 2013 Google, Inc
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm/test.h>
+#include <dm/ut.h>
+
+struct dm_test_state;
+
+void ut_fail(struct dm_test_state *dms, const char *fname, int line,
+	     const char *func, const char *cond)
+{
+	printf("%s:%d, %s(): %s\n", fname, line, func, cond);
+	dms->fail_count++;
+}
+
+void ut_failf(struct dm_test_state *dms, const char *fname, int line,
+	      const char *func, const char *cond, const char *fmt, ...)
+{
+	va_list args;
+
+	printf("%s:%d, %s(): %s: ", fname, line, func, cond);
+	va_start(args, fmt);
+	vprintf(fmt, args);
+	va_end(args);
+	putc('\n');
+	dms->fail_count++;
+}
diff --git a/test/image/test-imagetools.sh b/test/image/test-imagetools.sh
new file mode 100755
index 0000000000..9e299e1e57
--- /dev/null
+++ b/test/image/test-imagetools.sh
@@ -0,0 +1,141 @@
+#!/bin/bash
+#
+# Written by Guilherme Maciel Ferreira <guilherme.maciel.ferreira@gmail.com>
+#
+# Sanity check for mkimage and dumpimage tools
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+# To run this:
+#
+# make O=sandbox sandbox_config
+# make O=sandbox
+# ./test/image/test-imagetools.sh
+
+BASEDIR=sandbox
+SRCDIR=sandbox/boot
+IMAGE_NAME="v1.0-test"
+IMAGE=linux.img
+DATAFILE0=vmlinuz
+DATAFILE1=initrd.img
+DATAFILE2=System.map
+DATAFILES="${DATAFILE0} ${DATAFILE1} ${DATAFILE2}"
+TEST_OUT=test_output
+MKIMAGE=${BASEDIR}/tools/mkimage
+DUMPIMAGE=${BASEDIR}/tools/dumpimage
+MKIMAGE_LIST=mkimage.list
+DUMPIMAGE_LIST=dumpimage.list
+
+# Remove all the files we created
+cleanup()
+{
+	local file
+
+	for file in ${DATAFILES}; do
+		rm -f ${file} ${SRCDIR}/${file}
+	done
+	rm -f ${IMAGE} ${DUMPIMAGE_LIST} ${MKIMAGE_LIST} ${TEST_OUT}
+	rmdir ${SRCDIR}
+}
+
+# Check that two files are the same
+assert_equal()
+{
+	if ! diff $1 $2; then
+		echo "Failed."
+		cleanup
+		exit 1
+	fi
+}
+
+# Create some test files
+create_files()
+{
+	local file
+
+	mkdir -p ${SRCDIR}
+	for file in ${DATAFILES}; do
+		head -c $RANDOM /dev/urandom >${SRCDIR}/${file}
+	done
+}
+
+# Run a command, echoing it first
+do_cmd()
+{
+	local cmd="$@"
+
+	echo "# ${cmd}"
+	${cmd} 2>&1
+}
+
+# Run a command, redirecting output
+# Args:
+#    redirect_file
+#    command...
+do_cmd_redir()
+{
+	local redir="$1"
+	shift
+	local cmd="$@"
+
+	echo "# ${cmd}"
+	${cmd} >${redir}
+}
+
+# Write files into an image
+create_image()
+{
+	local files="${SRCDIR}/${DATAFILE0}:${SRCDIR}/${DATAFILE1}"
+	files+=":${SRCDIR}/${DATAFILE2}"
+
+	echo -e "\nBuilding image..."
+	do_cmd ${MKIMAGE} -A x86 -O linux -T multi -n \"${IMAGE_NAME}\" \
+		-d ${files} ${IMAGE}
+	echo "done."
+}
+
+# Extract files from an image
+extract_image()
+{
+	echo -e "\nExtracting image contents..."
+	do_cmd ${DUMPIMAGE} -i ${IMAGE} -p 0 ${DATAFILE0}
+	do_cmd ${DUMPIMAGE} -i ${IMAGE} -p 1 ${DATAFILE1}
+	do_cmd ${DUMPIMAGE} -i ${IMAGE} -p 2 ${DATAFILE2}
+	do_cmd ${DUMPIMAGE} -i ${IMAGE} -p 2 ${DATAFILE2} -o ${TEST_OUT}
+	echo "done."
+}
+
+# List the contents of a file
+list_image()
+{
+	echo -e "\nListing image contents..."
+	do_cmd_redir ${MKIMAGE_LIST} ${MKIMAGE} -l ${IMAGE}
+	do_cmd_redir ${DUMPIMAGE_LIST} ${DUMPIMAGE} -l ${IMAGE}
+	echo "done."
+}
+
+main()
+{
+	local file
+
+	create_files
+
+	# Compress and extract multifile images, compare the result
+	create_image
+	extract_image
+	for file in ${DATAFILES}; do
+		assert_equal ${file} ${SRCDIR}/${file}
+	done
+	assert_equal ${TEST_OUT} ${DATAFILE2}
+
+	# List contents and compares output fro tools
+	list_image
+	assert_equal ${DUMPIMAGE_LIST} ${MKIMAGE_LIST}
+
+	# Remove files created
+	cleanup
+
+	echo "Tests passed."
+}
+
+main
diff --git a/tools/.gitignore b/tools/.gitignore
index a7fee26cdd..2a90dfe83a 100644
--- a/tools/.gitignore
+++ b/tools/.gitignore
@@ -3,19 +3,18 @@
 /gen_eth_addr
 /img2srec
 /kwboot
+/dumpimage
 /mkenvimage
 /mkimage
+/mkexynosspl
 /mpc86x_clk
 /mxsboot
 /ncb
-/ncp
 /proftool
+/relocate-rela
 /ubsha1
 /xway-swap-bytes
 /*.exe
 /easylogo/easylogo
-/env/crc32.c
-/env/fw_printenv
 /gdb/gdbcont
 /gdb/gdbsend
-/kernel-doc/docproc
diff --git a/tools/Makefile b/tools/Makefile
index ca76f947e5..097cc1df17 100644
--- a/tools/Makefile
+++ b/tools/Makefile
@@ -5,14 +5,6 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-TOOLSUBDIRS = kernel-doc
-
-#
-# Include this after HOSTOS HOSTARCH check
-# so that we can act intelligently.
-#
-include $(TOPDIR)/config.mk
-
 #
 # toolchains targeting win32 generate .exe files
 #
@@ -32,6 +24,9 @@ CONFIG_NETCONSOLE = y
 CONFIG_SHA1_CHECK_UB_IMG = y
 endif
 
+subdir-$(HOST_TOOLS_ALL) += easylogo
+subdir-$(HOST_TOOLS_ALL) += gdb
+
 # Merge all the different vars for envcrc into one
 ENVCRC-$(CONFIG_ENV_IS_EMBEDDED) = y
 ENVCRC-$(CONFIG_ENV_IS_IN_DATAFLASH) = y
@@ -43,80 +38,115 @@ ENVCRC-$(CONFIG_ENV_IS_IN_NVRAM) = y
 ENVCRC-$(CONFIG_ENV_IS_IN_SPI_FLASH) = y
 CONFIG_BUILD_ENVCRC ?= $(ENVCRC-y)
 
-# Generated executable files
-BIN_FILES-$(CONFIG_LCD_LOGO) += bmp_logo$(SFX)
-BIN_FILES-$(CONFIG_VIDEO_LOGO) += bmp_logo$(SFX)
-BIN_FILES-$(CONFIG_BUILD_ENVCRC) += envcrc$(SFX)
-BIN_FILES-$(CONFIG_CMD_NET) += gen_eth_addr$(SFX)
-BIN_FILES-$(CONFIG_CMD_LOADS) += img2srec$(SFX)
-BIN_FILES-$(CONFIG_XWAY_SWAP_BYTES) += xway-swap-bytes$(SFX)
-BIN_FILES-y += mkenvimage$(SFX)
-BIN_FILES-y += mkimage$(SFX)
-BIN_FILES-$(CONFIG_EXYNOS5250) += mk$(BOARD)spl$(SFX)
-BIN_FILES-$(CONFIG_MX23) += mxsboot$(SFX)
-BIN_FILES-$(CONFIG_MX28) += mxsboot$(SFX)
-BIN_FILES-$(CONFIG_NETCONSOLE) += ncb$(SFX)
-BIN_FILES-$(CONFIG_SHA1_CHECK_UB_IMG) += ubsha1$(SFX)
-BIN_FILES-$(CONFIG_KIRKWOOD) += kwboot$(SFX)
-BIN_FILES-y += proftool(SFX)
-
-# Source files which exist outside the tools directory
-EXT_OBJ_FILES-$(CONFIG_BUILD_ENVCRC) += common/env_embedded.o
-EXT_OBJ_FILES-y += common/image.o
-EXT_OBJ_FILES-$(CONFIG_FIT) += common/image-fit.o
-EXT_OBJ_FILES-y += common/image-sig.o
-EXT_OBJ_FILES-y += lib/crc32.o
-EXT_OBJ_FILES-y += lib/md5.o
-EXT_OBJ_FILES-y += lib/sha1.o
-
-# Source files located in the tools directory
-NOPED_OBJ_FILES-y += aisimage.o
-NOPED_OBJ_FILES-y += default_image.o
-NOPED_OBJ_FILES-y += fit_image.o
-NOPED_OBJ_FILES-y += image-host.o
-NOPED_OBJ_FILES-y += imximage.o
-NOPED_OBJ_FILES-y += kwbimage.o
-NOPED_OBJ_FILES-y += mkenvimage.o
-NOPED_OBJ_FILES-y += mkimage.o
-NOPED_OBJ_FILES-y += mxsimage.o
-NOPED_OBJ_FILES-y += omapimage.o
-NOPED_OBJ_FILES-y += os_support.o
-NOPED_OBJ_FILES-y += pblimage.o
-NOPED_OBJ_FILES-y += proftool.o
-NOPED_OBJ_FILES-y += ublimage.o
-OBJ_FILES-$(CONFIG_BUILD_ENVCRC) += envcrc.o
-OBJ_FILES-$(CONFIG_CMD_LOADS) += img2srec.o
-OBJ_FILES-$(CONFIG_CMD_NET) += gen_eth_addr.o
-OBJ_FILES-$(CONFIG_EXYNOS5250) += mkexynosspl.o
-OBJ_FILES-$(CONFIG_KIRKWOOD) += kwboot.o
-OBJ_FILES-$(CONFIG_LCD_LOGO) += bmp_logo.o
-OBJ_FILES-$(CONFIG_MX23) += mxsboot.o
-OBJ_FILES-$(CONFIG_MX28) += mxsboot.o
-OBJ_FILES-$(CONFIG_NETCONSOLE) += ncb.o
-OBJ_FILES-$(CONFIG_SHA1_CHECK_UB_IMG) += ubsha1.o
-OBJ_FILES-$(CONFIG_SMDK5250) += mkexynosspl.o
-OBJ_FILES-$(CONFIG_VIDEO_LOGO) += bmp_logo.o
-OBJ_FILES-$(CONFIG_XWAY_SWAP_BYTES) += xway-swap-bytes.o
+# TODO: CONFIG_CMD_LICENSE does not work
+hostprogs-$(CONFIG_CMD_LICENSE) += bin2header$(SFX)
 
-# Don't build by default
-#ifeq ($(ARCH),ppc)
-#BIN_FILES-y += mpc86x_clk$(SFX)
-#OBJ_FILES-y += mpc86x_clk.o
-#endif
+hostprogs-$(CONFIG_LCD_LOGO) += bmp_logo$(SFX)
+hostprogs-$(CONFIG_VIDEO_LOGO) += bmp_logo$(SFX)
+HOSTCFLAGS_bmp_logo$(SFX).o := -pedantic
+
+hostprogs-$(CONFIG_BUILD_ENVCRC) += envcrc$(SFX)
+envcrc$(SFX)-objs := crc32.o env_embedded.o envcrc.o sha1.o
+
+hostprogs-$(CONFIG_CMD_NET) += gen_eth_addr$(SFX)
+HOSTCFLAGS_gen_eth_addr$(SFX).o := -pedantic
+
+hostprogs-$(CONFIG_CMD_LOADS) += img2srec$(SFX)
+HOSTCFLAGS_img2srec$(SFX).o := -pedantic
+
+hostprogs-$(CONFIG_XWAY_SWAP_BYTES) += xway-swap-bytes$(SFX)
+HOSTCFLAGS_xway-swap-bytes$(SFX).o := -pedantic
+
+hostprogs-y += mkenvimage$(SFX)
+mkenvimage$(SFX)-objs := crc32.o mkenvimage.o os_support.o
+
+hostprogs-y += dumpimage$(SFX) mkimage$(SFX)
 
+FIT_SIG_OBJS-$(CONFIG_FIT_SIGNATURE) := image-sig.o
 # Flattened device tree objects
-LIBFDT_OBJ_FILES-y += fdt.o
-LIBFDT_OBJ_FILES-y += fdt_ro.o
-LIBFDT_OBJ_FILES-y += fdt_rw.o
-LIBFDT_OBJ_FILES-y += fdt_strerror.o
-LIBFDT_OBJ_FILES-y += fdt_wip.o
+LIBFDT_OBJS := fdt.o fdt_ro.o fdt_rw.o fdt_strerror.o fdt_wip.o
+RSA_OBJS-$(CONFIG_FIT_SIGNATURE) := rsa-sign.o
+
+# common objs for dumpimage and mkimage
+dumpimage-mkimage-objs := aisimage.o \
+			$(FIT_SIG_OBJS-y) \
+			crc32.o \
+			default_image.o \
+			fit_image.o \
+			image-fit.o \
+			image-host.o \
+			image.o \
+			imagetool.o \
+			imximage.o \
+			kwbimage.o \
+			md5.o \
+			mxsimage.o \
+			omapimage.o \
+			os_support.o \
+			pblimage.o \
+			sha1.o \
+			ublimage.o \
+			$(LIBFDT_OBJS) \
+			$(RSA_OBJS-y)
+
+dumpimage$(SFX)-objs := $(dumpimage-mkimage-objs) dumpimage.o
+mkimage$(SFX)-objs   := $(dumpimage-mkimage-objs) mkimage.o
+
+# TODO(sjg@chromium.org): Is this correct on Mac OS?
+
+# MXSImage needs LibSSL
+ifneq ($(CONFIG_MX23)$(CONFIG_MX28),)
+HOSTLOADLIBES_dumpimage$(SFX) := -lssl -lcrypto
+HOSTLOADLIBES_mkimage$(SFX) := -lssl -lcrypto
+# Add CONFIG_MXS into host CFLAGS, so we can check whether or not register
+# the mxsimage support within tools/mxsimage.c .
+HOSTCFLAGS_mxsimage.o += -DCONFIG_MXS
+endif
+
+ifdef CONFIG_FIT_SIGNATURE
+HOSTLOADLIBES_dumpimage$(SFX) := -lssl -lcrypto
+HOSTLOADLIBES_mkimage$(SFX) := -lssl -lcrypto
+
+# This affects include/image.h, but including the board config file
+# is tricky, so manually define this options here.
+HOST_EXTRACFLAGS	+= -DCONFIG_FIT_SIGNATURE
+endif
+
+hostprogs-$(CONFIG_EXYNOS5250) += mkexynosspl$(SFX)
+hostprogs-$(CONFIG_EXYNOS5420) += mkexynosspl$(SFX)
+HOSTCFLAGS_mkexynosspl$(SFX).o := -pedantic
+
+hostprogs-$(CONFIG_MX23) += mxsboot$(SFX)
+hostprogs-$(CONFIG_MX28) += mxsboot$(SFX)
+HOSTCFLAGS_mxsboot$(SFX).o := -pedantic
+
+hostprogs-$(CONFIG_NETCONSOLE) += ncb$(SFX)
+hostprogs-$(CONFIG_SHA1_CHECK_UB_IMG) += ubsha1$(SFX)
 
-# RSA objects
-RSA_OBJ_FILES-$(CONFIG_FIT_SIGNATURE) += rsa-sign.o
+ubsha1$(SFX)-objs := os_support.o sha1.o ubsha1.o
+
+HOSTCFLAGS_ubsha1.o := -pedantic
+
+hostprogs-$(CONFIG_KIRKWOOD) += kwboot$(SFX)
+hostprogs-y += proftool$(SFX)
+hostprogs-$(CONFIG_STATIC_RELA) += relocate-rela$(SFX)
+
+# We build some files with extra pedantic flags to try to minimize things
+# that won't build on some weird host compiler -- though there are lots of
+# exceptions for files that aren't complaint.
+HOSTCFLAGS_crc32.o := -pedantic
+HOSTCFLAGS_md5.o := -pedantic
+HOSTCFLAGS_sha1.o := -pedantic
+
+# Don't build by default
+#hostprogs-$(CONFIG_PPC) += mpc86x_clk$(SFX)
+#HOSTCFLAGS_mpc86x_clk$(SFX).o := -pedantic
+
+always := $(hostprogs-y)
 
 # Generated LCD/video logo
-LOGO_H = $(OBJTREE)/include/bmp_logo.h
-LOGO_DATA_H = $(OBJTREE)/include/bmp_logo_data.h
+LOGO_H = $(objtree)/include/bmp_logo.h
+LOGO_DATA_H = $(objtree)/include/bmp_logo_data.h
 LOGO-$(CONFIG_LCD_LOGO) += $(LOGO_H)
 LOGO-$(CONFIG_LCD_LOGO) += $(LOGO_DATA_H)
 LOGO-$(CONFIG_VIDEO_LOGO) += $(LOGO_H)
@@ -124,168 +154,52 @@ LOGO-$(CONFIG_VIDEO_LOGO) += $(LOGO_DATA_H)
 
 # Generic logo
 ifeq ($(LOGO_BMP),)
-LOGO_BMP= logos/denx.bmp
+LOGO_BMP= $(srctree)/$(src)/logos/denx.bmp
 
 # Use board logo and fallback to vendor
-ifneq ($(wildcard logos/$(BOARD).bmp),)
-LOGO_BMP= logos/$(BOARD).bmp
+ifneq ($(wildcard $(srctree)/$(src)/logos/$(BOARD).bmp),)
+LOGO_BMP= $(srctree)/$(src)/logos/$(BOARD).bmp
 else
-ifneq ($(wildcard logos/$(VENDOR).bmp),)
-LOGO_BMP= logos/$(VENDOR).bmp
+ifneq ($(wildcard $(srctree)/$(src)/logos/$(VENDOR).bmp),)
+LOGO_BMP= $(srctree)/$(src)/logos/$(VENDOR).bmp
 endif
 endif
 
 endif # !LOGO_BMP
 
-# now $(obj) is defined
-HOSTSRCS += $(addprefix $(SRCTREE)/,$(EXT_OBJ_FILES-y:.o=.c))
-HOSTSRCS += $(addprefix $(SRCTREE)/tools/,$(OBJ_FILES-y:.o=.c))
-HOSTSRCS += $(addprefix $(SRCTREE)/lib/libfdt/,$(LIBFDT_OBJ_FILES-y:.o=.c))
-HOSTSRCS += $(addprefix $(SRCTREE)/lib/rsa/,$(RSA_OBJ_FILES-y:.o=.c))
-BINS	:= $(addprefix $(obj),$(sort $(BIN_FILES-y)))
-LIBFDT_OBJS	:= $(addprefix $(obj),$(LIBFDT_OBJ_FILES-y))
-RSA_OBJS	:= $(addprefix $(obj),$(RSA_OBJ_FILES-y))
-
-# We cannot check CONFIG_FIT_SIGNATURE here since it is not set on the host
-FIT_SIG_OBJ_FILES	:= image-sig.o
-FIT_SIG_OBJS		:= $(addprefix $(obj),$(FIT_SIG_OBJ_FILES))
-
-HOSTOBJS := $(addprefix $(obj),$(OBJ_FILES-y))
-NOPEDOBJS := $(addprefix $(obj),$(NOPED_OBJ_FILES-y))
-
 #
 # Use native tools and options
 # Define __KERNEL_STRICT_NAMES to prevent typedef overlaps
 # Define _GNU_SOURCE to obtain the getline prototype from stdio.h
 #
-HOSTCPPFLAGS =	-include $(SRCTREE)/include/libfdt_env.h \
-		-idirafter $(SRCTREE)/include \
-		-idirafter $(OBJTREE)/include2 \
-		-idirafter $(OBJTREE)/include \
-		-I $(SRCTREE)/lib/libfdt \
-		-I $(SRCTREE)/tools \
+HOST_EXTRACFLAGS += -include $(srctree)/include/libfdt_env.h \
+		$(patsubst -I%,-idirafter%, $(UBOOTINCLUDE)) \
+		-I$(srctree)/lib/libfdt \
+		-I$(srctree)/tools \
 		-DCONFIG_SYS_TEXT_BASE=$(CONFIG_SYS_TEXT_BASE) \
 		-DUSE_HOSTCC \
 		-D__KERNEL_STRICT_NAMES \
 		-D_GNU_SOURCE
 
+__build:	$(LOGO-y)
 
-all:	$(obj).depend $(BINS) $(LOGO-y) subdirs
-
-$(obj)bin2header$(SFX): $(obj)bin2header.o
-	$(HOSTCC) $(HOSTCFLAGS) $(HOSTLDFLAGS) -o $@ $^
-	$(HOSTSTRIP) $@
-
-$(obj)bmp_logo$(SFX):	$(obj)bmp_logo.o
-	$(HOSTCC) $(HOSTCFLAGS) $(HOSTLDFLAGS) -o $@ $^
-	$(HOSTSTRIP) $@
-
-$(obj)proftool(SFX):	$(obj)proftool.o
-	$(HOSTCC) $(HOSTCFLAGS) $(HOSTLDFLAGS) -o $@ $^
-	$(HOSTSTRIP) $@
-
-$(obj)envcrc$(SFX):	$(obj)crc32.o $(obj)env_embedded.o $(obj)envcrc.o $(obj)sha1.o
-	$(HOSTCC) $(HOSTCFLAGS) $(HOSTLDFLAGS) -o $@ $^
-
-$(obj)gen_eth_addr$(SFX):	$(obj)gen_eth_addr.o
-	$(HOSTCC) $(HOSTCFLAGS) $(HOSTLDFLAGS) -o $@ $^
-	$(HOSTSTRIP) $@
-
-$(obj)img2srec$(SFX):	$(obj)img2srec.o
-	$(HOSTCC) $(HOSTCFLAGS) $(HOSTLDFLAGS) -o $@ $^
-	$(HOSTSTRIP) $@
-
-$(obj)xway-swap-bytes$(SFX):	$(obj)xway-swap-bytes.o
-	$(HOSTCC) $(HOSTCFLAGS) $(HOSTLDFLAGS) -o $@ $^
-	$(HOSTSTRIP) $@
-
-$(obj)mkenvimage$(SFX):	$(obj)crc32.o $(obj)mkenvimage.o \
-	$(obj)os_support.o
-	$(HOSTCC) $(HOSTCFLAGS) $(HOSTLDFLAGS) -o $@ $^
-	$(HOSTSTRIP) $@
-
-$(obj)mkimage$(SFX):	$(obj)aisimage.o \
-			$(FIT_SIG_OBJS) \
-			$(obj)crc32.o \
-			$(obj)default_image.o \
-			$(obj)fit_image.o \
-			$(obj)image-fit.o \
-			$(obj)image-host.o \
-			$(obj)image.o \
-			$(obj)imximage.o \
-			$(obj)kwbimage.o \
-			$(obj)md5.o \
-			$(obj)mkimage.o \
-			$(obj)mxsimage.o \
-			$(obj)omapimage.o \
-			$(obj)os_support.o \
-			$(obj)pblimage.o \
-			$(obj)sha1.o \
-			$(obj)ublimage.o \
-			$(LIBFDT_OBJS) \
-			$(RSA_OBJS)
-	$(HOSTCC) $(HOSTCFLAGS) $(HOSTLDFLAGS) -o $@ $^ $(HOSTLIBS)
-	$(HOSTSTRIP) $@
-
-$(obj)mk$(BOARD)spl$(SFX):	$(obj)mkexynosspl.o
-	$(HOSTCC) $(HOSTCFLAGS) $(HOSTLDFLAGS) -o $@ $^
-	$(HOSTSTRIP) $@
-
-$(obj)mpc86x_clk$(SFX):	$(obj)mpc86x_clk.o
-	$(HOSTCC) $(HOSTCFLAGS) $(HOSTLDFLAGS) -o $@ $^
-	$(HOSTSTRIP) $@
+$(LOGO_H):	$(obj)/bmp_logo $(LOGO_BMP)
+	$(obj)/bmp_logo --gen-info $(LOGO_BMP) > $@
 
-$(obj)mxsboot$(SFX):	$(obj)mxsboot.o
-	$(HOSTCC) $(HOSTCFLAGS) $(HOSTLDFLAGS) -o $@ $^
-	$(HOSTSTRIP) $@
+$(LOGO_DATA_H):	$(obj)/bmp_logo $(LOGO_BMP)
+	$(obj)/bmp_logo --gen-data $(LOGO_BMP) > $@
 
-$(obj)ncb$(SFX):	$(obj)ncb.o
-	$(HOSTCC) $(HOSTCFLAGS) $(HOSTLDFLAGS) -o $@ $^
-	$(HOSTSTRIP) $@
+# Let clean descend into subdirs
+subdir- += env
 
-$(obj)ubsha1$(SFX):	$(obj)os_support.o $(obj)sha1.o $(obj)ubsha1.o
-	$(HOSTCC) $(HOSTCFLAGS) $(HOSTLDFLAGS) -o $@ $^
+ifneq ($(CROSS_BUILD_TOOLS),)
+HOSTCC = $(CC)
 
-$(obj)kwboot$(SFX): $(obj)kwboot.o
-	$(HOSTCC) $(HOSTCFLAGS) $(HOSTLDFLAGS) -o $@ $^
-	$(HOSTSTRIP) $@
+quiet_cmd_crosstools_strip = STRIP   $^
+      cmd_crosstools_strip = $(STRIP) $^; touch $@
+$(obj)/.strip: $(call objectify,$(filter $(always),$(hostprogs-y)))
+	$(call cmd,crosstools_strip)
 
-# Some of the tool objects need to be accessed from outside the tools directory
-$(obj)%.o: $(SRCTREE)/common/%.c
-	$(HOSTCC) -g $(HOSTCFLAGS_NOPED) -c -o $@ $<
-
-$(obj)%.o: $(SRCTREE)/lib/%.c
-	$(HOSTCC) -g $(HOSTCFLAGS) -c -o $@ $<
-
-$(obj)%.o: $(SRCTREE)/lib/libfdt/%.c
-	$(HOSTCC) -g $(HOSTCFLAGS_NOPED) -c -o $@ $<
-
-$(obj)%.o: $(SRCTREE)/lib/rsa/%.c
-	$(HOSTCC) -g $(HOSTCFLAGS_NOPED) -c -o $@ $<
-
-subdirs:
-ifeq ($(TOOLSUBDIRS),)
-	@:
-else
-	@for dir in $(TOOLSUBDIRS) ; do \
-	    $(MAKE) \
-		HOSTOS=$(HOSTOS) \
-		HOSTARCH=$(HOSTARCH) \
-		-C $$dir || exit 1 ; \
-	done
+always += .strip
 endif
-
-$(LOGO_H):	$(obj)bmp_logo $(LOGO_BMP)
-	$(obj)./bmp_logo --gen-info $(LOGO_BMP) > $@
-
-$(LOGO_DATA_H):	$(obj)bmp_logo $(LOGO_BMP)
-	$(obj)./bmp_logo --gen-data $(LOGO_BMP) > $@
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+clean-files += .strip
diff --git a/tools/aisimage.c b/tools/aisimage.c
index 04fb649899..8de370a2e0 100644
--- a/tools/aisimage.c
+++ b/tools/aisimage.c
@@ -5,7 +5,7 @@
  * SPDX-License-Identifier:	GPL-2.0+
  */
 
-#include "mkimage.h"
+#include "imagetool.h"
 #include "aisimage.h"
 #include <image.h>
 
@@ -176,7 +176,7 @@ static uint32_t *ais_insert_cmd_header(uint32_t cmd, uint32_t nargs,
 
 }
 
-static uint32_t *ais_alloc_buffer(struct mkimage_params *params)
+static uint32_t *ais_alloc_buffer(struct image_tool_params *params)
 {
 	int dfd;
 	struct stat sbuf;
@@ -216,7 +216,7 @@ static uint32_t *ais_alloc_buffer(struct mkimage_params *params)
 	return ptr;
 }
 
-static uint32_t *ais_copy_image(struct mkimage_params *params,
+static uint32_t *ais_copy_image(struct image_tool_params *params,
 	uint32_t *aisptr)
 
 {
@@ -252,7 +252,7 @@ static uint32_t *ais_copy_image(struct mkimage_params *params,
 
 }
 
-static int aisimage_generate(struct mkimage_params *params,
+static int aisimage_generate(struct image_tool_params *params,
 	struct image_type_params *tparams)
 {
 	FILE *fd = NULL;
@@ -370,7 +370,7 @@ static int aisimage_check_image_types(uint8_t type)
 }
 
 static int aisimage_verify_header(unsigned char *ptr, int image_size,
-			struct mkimage_params *params)
+			struct image_tool_params *params)
 {
 	struct ais_header *ais_hdr = (struct ais_header *)ptr;
 
@@ -384,11 +384,11 @@ static int aisimage_verify_header(unsigned char *ptr, int image_size,
 }
 
 static void aisimage_set_header(void *ptr, struct stat *sbuf, int ifd,
-				struct mkimage_params *params)
+				struct image_tool_params *params)
 {
 }
 
-int aisimage_check_params(struct mkimage_params *params)
+int aisimage_check_params(struct image_tool_params *params)
 {
 	if (!params)
 		return CFG_INVALID;
@@ -427,5 +427,5 @@ static struct image_type_params aisimage_params = {
 
 void init_ais_image_type(void)
 {
-	mkimage_register(&aisimage_params);
+	register_image_type(&aisimage_params);
 }
diff --git a/tools/buildman/README b/tools/buildman/README
index 090b653116..c30c1d4114 100644
--- a/tools/buildman/README
+++ b/tools/buildman/README
@@ -89,10 +89,16 @@ a few commits or boards, it will be pretty slow. As a tip, if you don't
 plan to use your machine for anything else, you can use -T to increase the
 number of threads beyond the default.
 
-Buildman lets you build all boards, or a subset. Specify the subset using
-the board name, architecture name, SOC name, or anything else in the
-boards.cfg file. So 'at91' will build all AT91 boards (arm), powerpc will
-build all PowerPC boards.
+Buildman lets you build all boards, or a subset. Specify the subset by passing
+command-line arguments that list the desired board name, architecture name,
+SOC name, or anything else in the boards.cfg file. Multiple arguments are
+allowed. Each argument will be interpreted as a regular expression, so
+behaviour is a superset of exact or substring matching. Examples are:
+
+* 'tegra20'      All boards with a Tegra20 SoC
+* 'tegra'        All boards with any Tegra Soc (Tegra20, Tegra30, Tegra114...)
+* '^tegra[23]0$' All boards with either Tegra20 or Tegra30 SoC
+* 'powerpc'      All PowerPC boards
 
 Buildman does not store intermediate object files. It optionally copies
 the binary output into a directory when a build is successful. Size
@@ -643,7 +649,7 @@ snapper9260=${at91-boards} BUILD_TAG=442
 snapper9g45=${at91-boards} BUILD_TAG=443
 
 This will use 'make ENABLE_AT91_TEST=1 BUILD_TAG=442' for snapper9260
-and 'make ENABLE_AT91_TEST=1 BUILD_TAG=442' for snapper9g45. A special
+and 'make ENABLE_AT91_TEST=1 BUILD_TAG=443' for snapper9g45. A special
 variable ${target} is available to access the target name (snapper9260 and
 snapper9g20 in this case). Variables are resolved recursively.
 
diff --git a/tools/buildman/board.py b/tools/buildman/board.py
index 1d3db206bd..5172a473e3 100644
--- a/tools/buildman/board.py
+++ b/tools/buildman/board.py
@@ -3,6 +3,8 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
+import re
+
 class Board:
     """A particular board that we can build"""
     def __init__(self, status, arch, cpu, soc, vendor, board_name, target, options):
@@ -135,14 +137,22 @@ class Boards:
             due to each argument, arranged by argument.
         """
         result = {}
+        argres = {}
         for arg in args:
             result[arg] = 0
+            argres[arg] = re.compile(arg)
         result['all'] = 0
 
         for board in self._boards:
             if args:
                 for arg in args:
-                    if arg in board.props:
+                    argre = argres[arg]
+                    match = False
+                    for prop in board.props:
+                        match = argre.match(prop)
+                        if match:
+                            break
+                    if match:
                         if not board.build_it:
                             board.build_it = True
                             result[arg] += 1
diff --git a/tools/checkpatch.pl b/tools/checkpatch.pl
deleted file mode 100755
index 88c5bc7735..0000000000
--- a/tools/checkpatch.pl
+++ /dev/null
@@ -1,3709 +0,0 @@
-#!/usr/bin/perl -w
-# (c) 2001, Dave Jones. (the file handling bit)
-# (c) 2005, Joel Schopp <jschopp@austin.ibm.com> (the ugly bit)
-# (c) 2007,2008, Andy Whitcroft <apw@uk.ibm.com> (new conditions, test suite)
-# (c) 2008-2010 Andy Whitcroft <apw@canonical.com>
-# Licensed under the terms of the GNU GPL License version 2
-
-use strict;
-
-my $P = $0;
-$P =~ s@.*/@@g;
-
-my $V = '0.32';
-
-use Getopt::Long qw(:config no_auto_abbrev);
-
-my $quiet = 0;
-my $tree = 1;
-my $chk_signoff = 1;
-my $chk_patch = 1;
-my $tst_only;
-my $emacs = 0;
-my $terse = 0;
-my $file = 0;
-my $check = 0;
-my $summary = 1;
-my $mailback = 0;
-my $summary_file = 0;
-my $show_types = 0;
-my $root;
-my %debug;
-my %ignore_type = ();
-my @ignore = ();
-my $help = 0;
-my $configuration_file = ".checkpatch.conf";
-my $max_line_length = 80;
-
-sub help {
-	my ($exitcode) = @_;
-
-	print << "EOM";
-Usage: $P [OPTION]... [FILE]...
-Version: $V
-
-Options:
-  -q, --quiet                quiet
-  --no-tree                  run without a kernel tree
-  --no-signoff               do not check for 'Signed-off-by' line
-  --patch                    treat FILE as patchfile (default)
-  --emacs                    emacs compile window format
-  --terse                    one line per report
-  -f, --file                 treat FILE as regular source file
-  --subjective, --strict     enable more subjective tests
-  --ignore TYPE(,TYPE2...)   ignore various comma separated message types
-  --max-line-length=n        set the maximum line length, if exceeded, warn
-  --show-types               show the message "types" in the output
-  --root=PATH                PATH to the kernel tree root
-  --no-summary               suppress the per-file summary
-  --mailback                 only produce a report in case of warnings/errors
-  --summary-file             include the filename in summary
-  --debug KEY=[0|1]          turn on/off debugging of KEY, where KEY is one of
-                             'values', 'possible', 'type', and 'attr' (default
-                             is all off)
-  --test-only=WORD           report only warnings/errors containing WORD
-                             literally
-  -h, --help, --version      display this help and exit
-
-When FILE is - read standard input.
-EOM
-
-	exit($exitcode);
-}
-
-my $conf = which_conf($configuration_file);
-if (-f $conf) {
-	my @conf_args;
-	open(my $conffile, '<', "$conf")
-	    or warn "$P: Can't find a readable $configuration_file file $!\n";
-
-	while (<$conffile>) {
-		my $line = $_;
-
-		$line =~ s/\s*\n?$//g;
-		$line =~ s/^\s*//g;
-		$line =~ s/\s+/ /g;
-
-		next if ($line =~ m/^\s*#/);
-		next if ($line =~ m/^\s*$/);
-
-		my @words = split(" ", $line);
-		foreach my $word (@words) {
-			last if ($word =~ m/^#/);
-			push (@conf_args, $word);
-		}
-	}
-	close($conffile);
-	unshift(@ARGV, @conf_args) if @conf_args;
-}
-
-GetOptions(
-	'q|quiet+'	=> \$quiet,
-	'tree!'		=> \$tree,
-	'signoff!'	=> \$chk_signoff,
-	'patch!'	=> \$chk_patch,
-	'emacs!'	=> \$emacs,
-	'terse!'	=> \$terse,
-	'f|file!'	=> \$file,
-	'subjective!'	=> \$check,
-	'strict!'	=> \$check,
-	'ignore=s'	=> \@ignore,
-	'show-types!'	=> \$show_types,
-	'max-line-length=i' => \$max_line_length,
-	'root=s'	=> \$root,
-	'summary!'	=> \$summary,
-	'mailback!'	=> \$mailback,
-	'summary-file!'	=> \$summary_file,
-
-	'debug=s'	=> \%debug,
-	'test-only=s'	=> \$tst_only,
-	'h|help'	=> \$help,
-	'version'	=> \$help
-) or help(1);
-
-help(0) if ($help);
-
-my $exit = 0;
-
-if ($#ARGV < 0) {
-	print "$P: no input files\n";
-	exit(1);
-}
-
-@ignore = split(/,/, join(',',@ignore));
-foreach my $word (@ignore) {
-	$word =~ s/\s*\n?$//g;
-	$word =~ s/^\s*//g;
-	$word =~ s/\s+/ /g;
-	$word =~ tr/[a-z]/[A-Z]/;
-
-	next if ($word =~ m/^\s*#/);
-	next if ($word =~ m/^\s*$/);
-
-	$ignore_type{$word}++;
-}
-
-my $dbg_values = 0;
-my $dbg_possible = 0;
-my $dbg_type = 0;
-my $dbg_attr = 0;
-for my $key (keys %debug) {
-	## no critic
-	eval "\${dbg_$key} = '$debug{$key}';";
-	die "$@" if ($@);
-}
-
-my $rpt_cleaners = 0;
-
-if ($terse) {
-	$emacs = 1;
-	$quiet++;
-}
-
-if ($tree) {
-	if (defined $root) {
-		if (!top_of_kernel_tree($root)) {
-			die "$P: $root: --root does not point at a valid tree\n";
-		}
-	} else {
-		if (top_of_kernel_tree('.')) {
-			$root = '.';
-		} elsif ($0 =~ m@(.*)/scripts/[^/]*$@ &&
-						top_of_kernel_tree($1)) {
-			$root = $1;
-		}
-	}
-
-	if (!defined $root) {
-		print "Must be run from the top-level dir. of a kernel tree\n";
-		exit(2);
-	}
-}
-
-my $emitted_corrupt = 0;
-
-our $Ident	= qr{
-			[A-Za-z_][A-Za-z\d_]*
-			(?:\s*\#\#\s*[A-Za-z_][A-Za-z\d_]*)*
-		}x;
-our $Storage	= qr{extern|static|asmlinkage};
-our $Sparse	= qr{
-			__user|
-			__kernel|
-			__force|
-			__iomem|
-			__must_check|
-			__init_refok|
-			__kprobes|
-			__ref|
-			__rcu
-		}x;
-
-# Notes to $Attribute:
-# We need \b after 'init' otherwise 'initconst' will cause a false positive in a check
-our $Attribute	= qr{
-			const|
-			__percpu|
-			__nocast|
-			__safe|
-			__bitwise__|
-			__packed__|
-			__packed2__|
-			__naked|
-			__maybe_unused|
-			__always_unused|
-			__noreturn|
-			__used|
-			__cold|
-			__noclone|
-			__deprecated|
-			__read_mostly|
-			__kprobes|
-			__(?:mem|cpu|dev|)(?:initdata|initconst|init\b)|
-			____cacheline_aligned|
-			____cacheline_aligned_in_smp|
-			____cacheline_internodealigned_in_smp|
-			__weak
-		  }x;
-our $Modifier;
-our $Inline	= qr{inline|__always_inline|noinline};
-our $Member	= qr{->$Ident|\.$Ident|\[[^]]*\]};
-our $Lval	= qr{$Ident(?:$Member)*};
-
-our $Float_hex	= qr{(?i)0x[0-9a-f]+p-?[0-9]+[fl]?};
-our $Float_dec	= qr{(?i)(?:[0-9]+\.[0-9]*|[0-9]*\.[0-9]+)(?:e-?[0-9]+)?[fl]?};
-our $Float_int	= qr{(?i)[0-9]+e-?[0-9]+[fl]?};
-our $Float	= qr{$Float_hex|$Float_dec|$Float_int};
-our $Constant	= qr{$Float|(?i)(?:0x[0-9a-f]+|[0-9]+)[ul]*};
-our $Assignment	= qr{\*\=|/=|%=|\+=|-=|<<=|>>=|&=|\^=|\|=|=};
-our $Compare    = qr{<=|>=|==|!=|<|>};
-our $Operators	= qr{
-			<=|>=|==|!=|
-			=>|->|<<|>>|<|>|!|~|
-			&&|\|\||,|\^|\+\+|--|&|\||\+|-|\*|\/|%
-		  }x;
-
-our $NonptrType;
-our $Type;
-our $Declare;
-
-our $NON_ASCII_UTF8	= qr{
-	[\xC2-\xDF][\x80-\xBF]               # non-overlong 2-byte
-	|  \xE0[\xA0-\xBF][\x80-\xBF]        # excluding overlongs
-	| [\xE1-\xEC\xEE\xEF][\x80-\xBF]{2}  # straight 3-byte
-	|  \xED[\x80-\x9F][\x80-\xBF]        # excluding surrogates
-	|  \xF0[\x90-\xBF][\x80-\xBF]{2}     # planes 1-3
-	| [\xF1-\xF3][\x80-\xBF]{3}          # planes 4-15
-	|  \xF4[\x80-\x8F][\x80-\xBF]{2}     # plane 16
-}x;
-
-our $UTF8	= qr{
-	[\x09\x0A\x0D\x20-\x7E]              # ASCII
-	| $NON_ASCII_UTF8
-}x;
-
-our $typeTypedefs = qr{(?x:
-	(?:__)?(?:u|s|be|le)(?:8|16|32|64)|
-	atomic_t
-)};
-
-our $logFunctions = qr{(?x:
-	printk(?:_ratelimited|_once|)|
-	[a-z0-9]+_(?:printk|emerg|alert|crit|err|warning|warn|notice|info|debug|dbg|vdbg|devel|cont|WARN)(?:_ratelimited|_once|)|
-	WARN(?:_RATELIMIT|_ONCE|)|
-	panic|
-	debug|
-	printf|
-	MODULE_[A-Z_]+
-)};
-
-our $signature_tags = qr{(?xi:
-	Signed-off-by:|
-	Acked-by:|
-	Tested-by:|
-	Reviewed-by:|
-	Reported-by:|
-	To:|
-	Cc:
-)};
-
-our @typeList = (
-	qr{void},
-	qr{(?:unsigned\s+)?char},
-	qr{(?:unsigned\s+)?short},
-	qr{(?:unsigned\s+)?int},
-	qr{(?:unsigned\s+)?long},
-	qr{(?:unsigned\s+)?long\s+int},
-	qr{(?:unsigned\s+)?long\s+long},
-	qr{(?:unsigned\s+)?long\s+long\s+int},
-	qr{unsigned},
-	qr{float},
-	qr{double},
-	qr{bool},
-	qr{struct\s+$Ident},
-	qr{union\s+$Ident},
-	qr{enum\s+$Ident},
-	qr{${Ident}_t},
-	qr{${Ident}_handler},
-	qr{${Ident}_handler_fn},
-);
-our @modifierList = (
-	qr{fastcall},
-);
-
-our $allowed_asm_includes = qr{(?x:
-	irq|
-	memory
-)};
-# memory.h: ARM has a custom one
-
-sub build_types {
-	my $mods = "(?x:  \n" . join("|\n  ", @modifierList) . "\n)";
-	my $all = "(?x:  \n" . join("|\n  ", @typeList) . "\n)";
-	$Modifier	= qr{(?:$Attribute|$Sparse|$mods)};
-	$NonptrType	= qr{
-			(?:$Modifier\s+|const\s+)*
-			(?:
-				(?:typeof|__typeof__)\s*\([^\)]*\)|
-				(?:$typeTypedefs\b)|
-				(?:${all}\b)
-			)
-			(?:\s+$Modifier|\s+const)*
-		  }x;
-	$Type	= qr{
-			$NonptrType
-			(?:(?:\s|\*|\[\])+\s*const|(?:\s|\*|\[\])+|(?:\s*\[\s*\])+)?
-			(?:\s+$Inline|\s+$Modifier)*
-		  }x;
-	$Declare	= qr{(?:$Storage\s+)?$Type};
-}
-build_types();
-
-
-our $Typecast	= qr{\s*(\(\s*$NonptrType\s*\)){0,1}\s*};
-
-# Using $balanced_parens, $LvalOrFunc, or $FuncArg
-# requires at least perl version v5.10.0
-# Any use must be runtime checked with $^V
-
-our $balanced_parens = qr/(\((?:[^\(\)]++|(?-1))*\))/;
-our $LvalOrFunc	= qr{($Lval)\s*($balanced_parens{0,1})\s*};
-our $FuncArg = qr{$Typecast{0,1}($LvalOrFunc|$Constant)};
-
-sub deparenthesize {
-	my ($string) = @_;
-	return "" if (!defined($string));
-	$string =~ s@^\s*\(\s*@@g;
-	$string =~ s@\s*\)\s*$@@g;
-	$string =~ s@\s+@ @g;
-	return $string;
-}
-
-$chk_signoff = 0 if ($file);
-
-my @rawlines = ();
-my @lines = ();
-my $vname;
-for my $filename (@ARGV) {
-	my $FILE;
-	if ($file) {
-		open($FILE, '-|', "diff -u /dev/null $filename") ||
-			die "$P: $filename: diff failed - $!\n";
-	} elsif ($filename eq '-') {
-		open($FILE, '<&STDIN');
-	} else {
-		open($FILE, '<', "$filename") ||
-			die "$P: $filename: open failed - $!\n";
-	}
-	if ($filename eq '-') {
-		$vname = 'Your patch';
-	} else {
-		$vname = $filename;
-	}
-	while (<$FILE>) {
-		chomp;
-		push(@rawlines, $_);
-	}
-	close($FILE);
-	if (!process($filename)) {
-		$exit = 1;
-	}
-	@rawlines = ();
-	@lines = ();
-}
-
-exit($exit);
-
-sub top_of_kernel_tree {
-	my ($root) = @_;
-
-	my @tree_check = (
-		"COPYING", "CREDITS", "Kbuild", "Makefile",
-		"README", "Documentation", "arch", "include", "drivers",
-		"fs", "init", "ipc", "kernel", "lib", "scripts",
-	);
-
-	foreach my $check (@tree_check) {
-		if (! -e $root . '/' . $check) {
-			return 0;
-		}
-	}
-	return 1;
-}
-
-sub parse_email {
-	my ($formatted_email) = @_;
-
-	my $name = "";
-	my $address = "";
-	my $comment = "";
-
-	if ($formatted_email =~ /^(.*)<(\S+\@\S+)>(.*)$/) {
-		$name = $1;
-		$address = $2;
-		$comment = $3 if defined $3;
-	} elsif ($formatted_email =~ /^\s*<(\S+\@\S+)>(.*)$/) {
-		$address = $1;
-		$comment = $2 if defined $2;
-	} elsif ($formatted_email =~ /(\S+\@\S+)(.*)$/) {
-		$address = $1;
-		$comment = $2 if defined $2;
-		$formatted_email =~ s/$address.*$//;
-		$name = $formatted_email;
-		$name =~ s/^\s+|\s+$//g;
-		$name =~ s/^\"|\"$//g;
-		# If there's a name left after stripping spaces and
-		# leading quotes, and the address doesn't have both
-		# leading and trailing angle brackets, the address
-		# is invalid. ie:
-		#   "joe smith joe@smith.com" bad
-		#   "joe smith <joe@smith.com" bad
-		if ($name ne "" && $address !~ /^<[^>]+>$/) {
-			$name = "";
-			$address = "";
-			$comment = "";
-		}
-	}
-
-	$name =~ s/^\s+|\s+$//g;
-	$name =~ s/^\"|\"$//g;
-	$address =~ s/^\s+|\s+$//g;
-	$address =~ s/^\<|\>$//g;
-
-	if ($name =~ /[^\w \-]/i) { ##has "must quote" chars
-		$name =~ s/(?<!\\)"/\\"/g; ##escape quotes
-		$name = "\"$name\"";
-	}
-
-	return ($name, $address, $comment);
-}
-
-sub format_email {
-	my ($name, $address) = @_;
-
-	my $formatted_email;
-
-	$name =~ s/^\s+|\s+$//g;
-	$name =~ s/^\"|\"$//g;
-	$address =~ s/^\s+|\s+$//g;
-
-	if ($name =~ /[^\w \-]/i) { ##has "must quote" chars
-		$name =~ s/(?<!\\)"/\\"/g; ##escape quotes
-		$name = "\"$name\"";
-	}
-
-	if ("$name" eq "") {
-		$formatted_email = "$address";
-	} else {
-		$formatted_email = "$name <$address>";
-	}
-
-	return $formatted_email;
-}
-
-sub which_conf {
-	my ($conf) = @_;
-
-	foreach my $path (split(/:/, ".:$ENV{HOME}:.scripts")) {
-		if (-e "$path/$conf") {
-			return "$path/$conf";
-		}
-	}
-
-	return "";
-}
-
-sub expand_tabs {
-	my ($str) = @_;
-
-	my $res = '';
-	my $n = 0;
-	for my $c (split(//, $str)) {
-		if ($c eq "\t") {
-			$res .= ' ';
-			$n++;
-			for (; ($n % 8) != 0; $n++) {
-				$res .= ' ';
-			}
-			next;
-		}
-		$res .= $c;
-		$n++;
-	}
-
-	return $res;
-}
-sub copy_spacing {
-	(my $res = shift) =~ tr/\t/ /c;
-	return $res;
-}
-
-sub line_stats {
-	my ($line) = @_;
-
-	# Drop the diff line leader and expand tabs
-	$line =~ s/^.//;
-	$line = expand_tabs($line);
-
-	# Pick the indent from the front of the line.
-	my ($white) = ($line =~ /^(\s*)/);
-
-	return (length($line), length($white));
-}
-
-my $sanitise_quote = '';
-
-sub sanitise_line_reset {
-	my ($in_comment) = @_;
-
-	if ($in_comment) {
-		$sanitise_quote = '*/';
-	} else {
-		$sanitise_quote = '';
-	}
-}
-sub sanitise_line {
-	my ($line) = @_;
-
-	my $res = '';
-	my $l = '';
-
-	my $qlen = 0;
-	my $off = 0;
-	my $c;
-
-	# Always copy over the diff marker.
-	$res = substr($line, 0, 1);
-
-	for ($off = 1; $off < length($line); $off++) {
-		$c = substr($line, $off, 1);
-
-		# Comments we are wacking completly including the begin
-		# and end, all to $;.
-		if ($sanitise_quote eq '' && substr($line, $off, 2) eq '/*') {
-			$sanitise_quote = '*/';
-
-			substr($res, $off, 2, "$;$;");
-			$off++;
-			next;
-		}
-		if ($sanitise_quote eq '*/' && substr($line, $off, 2) eq '*/') {
-			$sanitise_quote = '';
-			substr($res, $off, 2, "$;$;");
-			$off++;
-			next;
-		}
-		if ($sanitise_quote eq '' && substr($line, $off, 2) eq '//') {
-			$sanitise_quote = '//';
-
-			substr($res, $off, 2, $sanitise_quote);
-			$off++;
-			next;
-		}
-
-		# A \ in a string means ignore the next character.
-		if (($sanitise_quote eq "'" || $sanitise_quote eq '"') &&
-		    $c eq "\\") {
-			substr($res, $off, 2, 'XX');
-			$off++;
-			next;
-		}
-		# Regular quotes.
-		if ($c eq "'" || $c eq '"') {
-			if ($sanitise_quote eq '') {
-				$sanitise_quote = $c;
-
-				substr($res, $off, 1, $c);
-				next;
-			} elsif ($sanitise_quote eq $c) {
-				$sanitise_quote = '';
-			}
-		}
-
-		#print "c<$c> SQ<$sanitise_quote>\n";
-		if ($off != 0 && $sanitise_quote eq '*/' && $c ne "\t") {
-			substr($res, $off, 1, $;);
-		} elsif ($off != 0 && $sanitise_quote eq '//' && $c ne "\t") {
-			substr($res, $off, 1, $;);
-		} elsif ($off != 0 && $sanitise_quote && $c ne "\t") {
-			substr($res, $off, 1, 'X');
-		} else {
-			substr($res, $off, 1, $c);
-		}
-	}
-
-	if ($sanitise_quote eq '//') {
-		$sanitise_quote = '';
-	}
-
-	# The pathname on a #include may be surrounded by '<' and '>'.
-	if ($res =~ /^.\s*\#\s*include\s+\<(.*)\>/) {
-		my $clean = 'X' x length($1);
-		$res =~ s@\<.*\>@<$clean>@;
-
-	# The whole of a #error is a string.
-	} elsif ($res =~ /^.\s*\#\s*(?:error|warning)\s+(.*)\b/) {
-		my $clean = 'X' x length($1);
-		$res =~ s@(\#\s*(?:error|warning)\s+).*@$1$clean@;
-	}
-
-	return $res;
-}
-
-sub ctx_statement_block {
-	my ($linenr, $remain, $off) = @_;
-	my $line = $linenr - 1;
-	my $blk = '';
-	my $soff = $off;
-	my $coff = $off - 1;
-	my $coff_set = 0;
-
-	my $loff = 0;
-
-	my $type = '';
-	my $level = 0;
-	my @stack = ();
-	my $p;
-	my $c;
-	my $len = 0;
-
-	my $remainder;
-	while (1) {
-		@stack = (['', 0]) if ($#stack == -1);
-
-		#warn "CSB: blk<$blk> remain<$remain>\n";
-		# If we are about to drop off the end, pull in more
-		# context.
-		if ($off >= $len) {
-			for (; $remain > 0; $line++) {
-				last if (!defined $lines[$line]);
-				next if ($lines[$line] =~ /^-/);
-				$remain--;
-				$loff = $len;
-				$blk .= $lines[$line] . "\n";
-				$len = length($blk);
-				$line++;
-				last;
-			}
-			# Bail if there is no further context.
-			#warn "CSB: blk<$blk> off<$off> len<$len>\n";
-			if ($off >= $len) {
-				last;
-			}
-			if ($level == 0 && substr($blk, $off) =~ /^.\s*#\s*define/) {
-				$level++;
-				$type = '#';
-			}
-		}
-		$p = $c;
-		$c = substr($blk, $off, 1);
-		$remainder = substr($blk, $off);
-
-		#warn "CSB: c<$c> type<$type> level<$level> remainder<$remainder> coff_set<$coff_set>\n";
-
-		# Handle nested #if/#else.
-		if ($remainder =~ /^#\s*(?:ifndef|ifdef|if)\s/) {
-			push(@stack, [ $type, $level ]);
-		} elsif ($remainder =~ /^#\s*(?:else|elif)\b/) {
-			($type, $level) = @{$stack[$#stack - 1]};
-		} elsif ($remainder =~ /^#\s*endif\b/) {
-			($type, $level) = @{pop(@stack)};
-		}
-
-		# Statement ends at the ';' or a close '}' at the
-		# outermost level.
-		if ($level == 0 && $c eq ';') {
-			last;
-		}
-
-		# An else is really a conditional as long as its not else if
-		if ($level == 0 && $coff_set == 0 &&
-				(!defined($p) || $p =~ /(?:\s|\}|\+)/) &&
-				$remainder =~ /^(else)(?:\s|{)/ &&
-				$remainder !~ /^else\s+if\b/) {
-			$coff = $off + length($1) - 1;
-			$coff_set = 1;
-			#warn "CSB: mark coff<$coff> soff<$soff> 1<$1>\n";
-			#warn "[" . substr($blk, $soff, $coff - $soff + 1) . "]\n";
-		}
-
-		if (($type eq '' || $type eq '(') && $c eq '(') {
-			$level++;
-			$type = '(';
-		}
-		if ($type eq '(' && $c eq ')') {
-			$level--;
-			$type = ($level != 0)? '(' : '';
-
-			if ($level == 0 && $coff < $soff) {
-				$coff = $off;
-				$coff_set = 1;
-				#warn "CSB: mark coff<$coff>\n";
-			}
-		}
-		if (($type eq '' || $type eq '{') && $c eq '{') {
-			$level++;
-			$type = '{';
-		}
-		if ($type eq '{' && $c eq '}') {
-			$level--;
-			$type = ($level != 0)? '{' : '';
-
-			if ($level == 0) {
-				if (substr($blk, $off + 1, 1) eq ';') {
-					$off++;
-				}
-				last;
-			}
-		}
-		# Preprocessor commands end at the newline unless escaped.
-		if ($type eq '#' && $c eq "\n" && $p ne "\\") {
-			$level--;
-			$type = '';
-			$off++;
-			last;
-		}
-		$off++;
-	}
-	# We are truly at the end, so shuffle to the next line.
-	if ($off == $len) {
-		$loff = $len + 1;
-		$line++;
-		$remain--;
-	}
-
-	my $statement = substr($blk, $soff, $off - $soff + 1);
-	my $condition = substr($blk, $soff, $coff - $soff + 1);
-
-	#warn "STATEMENT<$statement>\n";
-	#warn "CONDITION<$condition>\n";
-
-	#print "coff<$coff> soff<$off> loff<$loff>\n";
-
-	return ($statement, $condition,
-			$line, $remain + 1, $off - $loff + 1, $level);
-}
-
-sub statement_lines {
-	my ($stmt) = @_;
-
-	# Strip the diff line prefixes and rip blank lines at start and end.
-	$stmt =~ s/(^|\n)./$1/g;
-	$stmt =~ s/^\s*//;
-	$stmt =~ s/\s*$//;
-
-	my @stmt_lines = ($stmt =~ /\n/g);
-
-	return $#stmt_lines + 2;
-}
-
-sub statement_rawlines {
-	my ($stmt) = @_;
-
-	my @stmt_lines = ($stmt =~ /\n/g);
-
-	return $#stmt_lines + 2;
-}
-
-sub statement_block_size {
-	my ($stmt) = @_;
-
-	$stmt =~ s/(^|\n)./$1/g;
-	$stmt =~ s/^\s*{//;
-	$stmt =~ s/}\s*$//;
-	$stmt =~ s/^\s*//;
-	$stmt =~ s/\s*$//;
-
-	my @stmt_lines = ($stmt =~ /\n/g);
-	my @stmt_statements = ($stmt =~ /;/g);
-
-	my $stmt_lines = $#stmt_lines + 2;
-	my $stmt_statements = $#stmt_statements + 1;
-
-	if ($stmt_lines > $stmt_statements) {
-		return $stmt_lines;
-	} else {
-		return $stmt_statements;
-	}
-}
-
-sub ctx_statement_full {
-	my ($linenr, $remain, $off) = @_;
-	my ($statement, $condition, $level);
-
-	my (@chunks);
-
-	# Grab the first conditional/block pair.
-	($statement, $condition, $linenr, $remain, $off, $level) =
-				ctx_statement_block($linenr, $remain, $off);
-	#print "F: c<$condition> s<$statement> remain<$remain>\n";
-	push(@chunks, [ $condition, $statement ]);
-	if (!($remain > 0 && $condition =~ /^\s*(?:\n[+-])?\s*(?:if|else|do)\b/s)) {
-		return ($level, $linenr, @chunks);
-	}
-
-	# Pull in the following conditional/block pairs and see if they
-	# could continue the statement.
-	for (;;) {
-		($statement, $condition, $linenr, $remain, $off, $level) =
-				ctx_statement_block($linenr, $remain, $off);
-		#print "C: c<$condition> s<$statement> remain<$remain>\n";
-		last if (!($remain > 0 && $condition =~ /^(?:\s*\n[+-])*\s*(?:else|do)\b/s));
-		#print "C: push\n";
-		push(@chunks, [ $condition, $statement ]);
-	}
-
-	return ($level, $linenr, @chunks);
-}
-
-sub ctx_block_get {
-	my ($linenr, $remain, $outer, $open, $close, $off) = @_;
-	my $line;
-	my $start = $linenr - 1;
-	my $blk = '';
-	my @o;
-	my @c;
-	my @res = ();
-
-	my $level = 0;
-	my @stack = ($level);
-	for ($line = $start; $remain > 0; $line++) {
-		next if ($rawlines[$line] =~ /^-/);
-		$remain--;
-
-		$blk .= $rawlines[$line];
-
-		# Handle nested #if/#else.
-		if ($lines[$line] =~ /^.\s*#\s*(?:ifndef|ifdef|if)\s/) {
-			push(@stack, $level);
-		} elsif ($lines[$line] =~ /^.\s*#\s*(?:else|elif)\b/) {
-			$level = $stack[$#stack - 1];
-		} elsif ($lines[$line] =~ /^.\s*#\s*endif\b/) {
-			$level = pop(@stack);
-		}
-
-		foreach my $c (split(//, $lines[$line])) {
-			##print "C<$c>L<$level><$open$close>O<$off>\n";
-			if ($off > 0) {
-				$off--;
-				next;
-			}
-
-			if ($c eq $close && $level > 0) {
-				$level--;
-				last if ($level == 0);
-			} elsif ($c eq $open) {
-				$level++;
-			}
-		}
-
-		if (!$outer || $level <= 1) {
-			push(@res, $rawlines[$line]);
-		}
-
-		last if ($level == 0);
-	}
-
-	return ($level, @res);
-}
-sub ctx_block_outer {
-	my ($linenr, $remain) = @_;
-
-	my ($level, @r) = ctx_block_get($linenr, $remain, 1, '{', '}', 0);
-	return @r;
-}
-sub ctx_block {
-	my ($linenr, $remain) = @_;
-
-	my ($level, @r) = ctx_block_get($linenr, $remain, 0, '{', '}', 0);
-	return @r;
-}
-sub ctx_statement {
-	my ($linenr, $remain, $off) = @_;
-
-	my ($level, @r) = ctx_block_get($linenr, $remain, 0, '(', ')', $off);
-	return @r;
-}
-sub ctx_block_level {
-	my ($linenr, $remain) = @_;
-
-	return ctx_block_get($linenr, $remain, 0, '{', '}', 0);
-}
-sub ctx_statement_level {
-	my ($linenr, $remain, $off) = @_;
-
-	return ctx_block_get($linenr, $remain, 0, '(', ')', $off);
-}
-
-sub ctx_locate_comment {
-	my ($first_line, $end_line) = @_;
-
-	# Catch a comment on the end of the line itself.
-	my ($current_comment) = ($rawlines[$end_line - 1] =~ m@.*(/\*.*\*/)\s*(?:\\\s*)?$@);
-	return $current_comment if (defined $current_comment);
-
-	# Look through the context and try and figure out if there is a
-	# comment.
-	my $in_comment = 0;
-	$current_comment = '';
-	for (my $linenr = $first_line; $linenr < $end_line; $linenr++) {
-		my $line = $rawlines[$linenr - 1];
-		#warn "           $line\n";
-		if ($linenr == $first_line and $line =~ m@^.\s*\*@) {
-			$in_comment = 1;
-		}
-		if ($line =~ m@/\*@) {
-			$in_comment = 1;
-		}
-		if (!$in_comment && $current_comment ne '') {
-			$current_comment = '';
-		}
-		$current_comment .= $line . "\n" if ($in_comment);
-		if ($line =~ m@\*/@) {
-			$in_comment = 0;
-		}
-	}
-
-	chomp($current_comment);
-	return($current_comment);
-}
-sub ctx_has_comment {
-	my ($first_line, $end_line) = @_;
-	my $cmt = ctx_locate_comment($first_line, $end_line);
-
-	##print "LINE: $rawlines[$end_line - 1 ]\n";
-	##print "CMMT: $cmt\n";
-
-	return ($cmt ne '');
-}
-
-sub raw_line {
-	my ($linenr, $cnt) = @_;
-
-	my $offset = $linenr - 1;
-	$cnt++;
-
-	my $line;
-	while ($cnt) {
-		$line = $rawlines[$offset++];
-		next if (defined($line) && $line =~ /^-/);
-		$cnt--;
-	}
-
-	return $line;
-}
-
-sub cat_vet {
-	my ($vet) = @_;
-	my ($res, $coded);
-
-	$res = '';
-	while ($vet =~ /([^[:cntrl:]]*)([[:cntrl:]]|$)/g) {
-		$res .= $1;
-		if ($2 ne '') {
-			$coded = sprintf("^%c", unpack('C', $2) + 64);
-			$res .= $coded;
-		}
-	}
-	$res =~ s/$/\$/;
-
-	return $res;
-}
-
-my $av_preprocessor = 0;
-my $av_pending;
-my @av_paren_type;
-my $av_pend_colon;
-
-sub annotate_reset {
-	$av_preprocessor = 0;
-	$av_pending = '_';
-	@av_paren_type = ('E');
-	$av_pend_colon = 'O';
-}
-
-sub annotate_values {
-	my ($stream, $type) = @_;
-
-	my $res;
-	my $var = '_' x length($stream);
-	my $cur = $stream;
-
-	print "$stream\n" if ($dbg_values > 1);
-
-	while (length($cur)) {
-		@av_paren_type = ('E') if ($#av_paren_type < 0);
-		print " <" . join('', @av_paren_type) .
-				"> <$type> <$av_pending>" if ($dbg_values > 1);
-		if ($cur =~ /^(\s+)/o) {
-			print "WS($1)\n" if ($dbg_values > 1);
-			if ($1 =~ /\n/ && $av_preprocessor) {
-				$type = pop(@av_paren_type);
-				$av_preprocessor = 0;
-			}
-
-		} elsif ($cur =~ /^(\(\s*$Type\s*)\)/ && $av_pending eq '_') {
-			print "CAST($1)\n" if ($dbg_values > 1);
-			push(@av_paren_type, $type);
-			$type = 'c';
-
-		} elsif ($cur =~ /^($Type)\s*(?:$Ident|,|\)|\(|\s*$)/) {
-			print "DECLARE($1)\n" if ($dbg_values > 1);
-			$type = 'T';
-
-		} elsif ($cur =~ /^($Modifier)\s*/) {
-			print "MODIFIER($1)\n" if ($dbg_values > 1);
-			$type = 'T';
-
-		} elsif ($cur =~ /^(\#\s*define\s*$Ident)(\(?)/o) {
-			print "DEFINE($1,$2)\n" if ($dbg_values > 1);
-			$av_preprocessor = 1;
-			push(@av_paren_type, $type);
-			if ($2 ne '') {
-				$av_pending = 'N';
-			}
-			$type = 'E';
-
-		} elsif ($cur =~ /^(\#\s*(?:undef\s*$Ident|include\b))/o) {
-			print "UNDEF($1)\n" if ($dbg_values > 1);
-			$av_preprocessor = 1;
-			push(@av_paren_type, $type);
-
-		} elsif ($cur =~ /^(\#\s*(?:ifdef|ifndef|if))/o) {
-			print "PRE_START($1)\n" if ($dbg_values > 1);
-			$av_preprocessor = 1;
-
-			push(@av_paren_type, $type);
-			push(@av_paren_type, $type);
-			$type = 'E';
-
-		} elsif ($cur =~ /^(\#\s*(?:else|elif))/o) {
-			print "PRE_RESTART($1)\n" if ($dbg_values > 1);
-			$av_preprocessor = 1;
-
-			push(@av_paren_type, $av_paren_type[$#av_paren_type]);
-
-			$type = 'E';
-
-		} elsif ($cur =~ /^(\#\s*(?:endif))/o) {
-			print "PRE_END($1)\n" if ($dbg_values > 1);
-
-			$av_preprocessor = 1;
-
-			# Assume all arms of the conditional end as this
-			# one does, and continue as if the #endif was not here.
-			pop(@av_paren_type);
-			push(@av_paren_type, $type);
-			$type = 'E';
-
-		} elsif ($cur =~ /^(\\\n)/o) {
-			print "PRECONT($1)\n" if ($dbg_values > 1);
-
-		} elsif ($cur =~ /^(__attribute__)\s*\(?/o) {
-			print "ATTR($1)\n" if ($dbg_values > 1);
-			$av_pending = $type;
-			$type = 'N';
-
-		} elsif ($cur =~ /^(sizeof)\s*(\()?/o) {
-			print "SIZEOF($1)\n" if ($dbg_values > 1);
-			if (defined $2) {
-				$av_pending = 'V';
-			}
-			$type = 'N';
-
-		} elsif ($cur =~ /^(if|while|for)\b/o) {
-			print "COND($1)\n" if ($dbg_values > 1);
-			$av_pending = 'E';
-			$type = 'N';
-
-		} elsif ($cur =~/^(case)/o) {
-			print "CASE($1)\n" if ($dbg_values > 1);
-			$av_pend_colon = 'C';
-			$type = 'N';
-
-		} elsif ($cur =~/^(return|else|goto|typeof|__typeof__)\b/o) {
-			print "KEYWORD($1)\n" if ($dbg_values > 1);
-			$type = 'N';
-
-		} elsif ($cur =~ /^(\()/o) {
-			print "PAREN('$1')\n" if ($dbg_values > 1);
-			push(@av_paren_type, $av_pending);
-			$av_pending = '_';
-			$type = 'N';
-
-		} elsif ($cur =~ /^(\))/o) {
-			my $new_type = pop(@av_paren_type);
-			if ($new_type ne '_') {
-				$type = $new_type;
-				print "PAREN('$1') -> $type\n"
-							if ($dbg_values > 1);
-			} else {
-				print "PAREN('$1')\n" if ($dbg_values > 1);
-			}
-
-		} elsif ($cur =~ /^($Ident)\s*\(/o) {
-			print "FUNC($1)\n" if ($dbg_values > 1);
-			$type = 'V';
-			$av_pending = 'V';
-
-		} elsif ($cur =~ /^($Ident\s*):(?:\s*\d+\s*(,|=|;))?/) {
-			if (defined $2 && $type eq 'C' || $type eq 'T') {
-				$av_pend_colon = 'B';
-			} elsif ($type eq 'E') {
-				$av_pend_colon = 'L';
-			}
-			print "IDENT_COLON($1,$type>$av_pend_colon)\n" if ($dbg_values > 1);
-			$type = 'V';
-
-		} elsif ($cur =~ /^($Ident|$Constant)/o) {
-			print "IDENT($1)\n" if ($dbg_values > 1);
-			$type = 'V';
-
-		} elsif ($cur =~ /^($Assignment)/o) {
-			print "ASSIGN($1)\n" if ($dbg_values > 1);
-			$type = 'N';
-
-		} elsif ($cur =~/^(;|{|})/) {
-			print "END($1)\n" if ($dbg_values > 1);
-			$type = 'E';
-			$av_pend_colon = 'O';
-
-		} elsif ($cur =~/^(,)/) {
-			print "COMMA($1)\n" if ($dbg_values > 1);
-			$type = 'C';
-
-		} elsif ($cur =~ /^(\?)/o) {
-			print "QUESTION($1)\n" if ($dbg_values > 1);
-			$type = 'N';
-
-		} elsif ($cur =~ /^(:)/o) {
-			print "COLON($1,$av_pend_colon)\n" if ($dbg_values > 1);
-
-			substr($var, length($res), 1, $av_pend_colon);
-			if ($av_pend_colon eq 'C' || $av_pend_colon eq 'L') {
-				$type = 'E';
-			} else {
-				$type = 'N';
-			}
-			$av_pend_colon = 'O';
-
-		} elsif ($cur =~ /^(\[)/o) {
-			print "CLOSE($1)\n" if ($dbg_values > 1);
-			$type = 'N';
-
-		} elsif ($cur =~ /^(-(?![->])|\+(?!\+)|\*|\&\&|\&)/o) {
-			my $variant;
-
-			print "OPV($1)\n" if ($dbg_values > 1);
-			if ($type eq 'V') {
-				$variant = 'B';
-			} else {
-				$variant = 'U';
-			}
-
-			substr($var, length($res), 1, $variant);
-			$type = 'N';
-
-		} elsif ($cur =~ /^($Operators)/o) {
-			print "OP($1)\n" if ($dbg_values > 1);
-			if ($1 ne '++' && $1 ne '--') {
-				$type = 'N';
-			}
-
-		} elsif ($cur =~ /(^.)/o) {
-			print "C($1)\n" if ($dbg_values > 1);
-		}
-		if (defined $1) {
-			$cur = substr($cur, length($1));
-			$res .= $type x length($1);
-		}
-	}
-
-	return ($res, $var);
-}
-
-sub possible {
-	my ($possible, $line) = @_;
-	my $notPermitted = qr{(?:
-		^(?:
-			$Modifier|
-			$Storage|
-			$Type|
-			DEFINE_\S+
-		)$|
-		^(?:
-			goto|
-			return|
-			case|
-			else|
-			asm|__asm__|
-			do|
-			\#|
-			\#\#|
-		)(?:\s|$)|
-		^(?:typedef|struct|enum)\b
-	    )}x;
-	warn "CHECK<$possible> ($line)\n" if ($dbg_possible > 2);
-	if ($possible !~ $notPermitted) {
-		# Check for modifiers.
-		$possible =~ s/\s*$Storage\s*//g;
-		$possible =~ s/\s*$Sparse\s*//g;
-		if ($possible =~ /^\s*$/) {
-
-		} elsif ($possible =~ /\s/) {
-			$possible =~ s/\s*$Type\s*//g;
-			for my $modifier (split(' ', $possible)) {
-				if ($modifier !~ $notPermitted) {
-					warn "MODIFIER: $modifier ($possible) ($line)\n" if ($dbg_possible);
-					push(@modifierList, $modifier);
-				}
-			}
-
-		} else {
-			warn "POSSIBLE: $possible ($line)\n" if ($dbg_possible);
-			push(@typeList, $possible);
-		}
-		build_types();
-	} else {
-		warn "NOTPOSS: $possible ($line)\n" if ($dbg_possible > 1);
-	}
-}
-
-my $prefix = '';
-
-sub show_type {
-       return !defined $ignore_type{$_[0]};
-}
-
-sub report {
-	if (!show_type($_[1]) ||
-	    (defined $tst_only && $_[2] !~ /\Q$tst_only\E/)) {
-		return 0;
-	}
-	my $line;
-	if ($show_types) {
-		$line = "$prefix$_[0]:$_[1]: $_[2]\n";
-	} else {
-		$line = "$prefix$_[0]: $_[2]\n";
-	}
-	$line = (split('\n', $line))[0] . "\n" if ($terse);
-
-	push(our @report, $line);
-
-	return 1;
-}
-sub report_dump {
-	our @report;
-}
-
-sub ERROR {
-	if (report("ERROR", $_[0], $_[1])) {
-		our $clean = 0;
-		our $cnt_error++;
-	}
-}
-sub WARN {
-	if (report("WARNING", $_[0], $_[1])) {
-		our $clean = 0;
-		our $cnt_warn++;
-	}
-}
-sub CHK {
-	if ($check && report("CHECK", $_[0], $_[1])) {
-		our $clean = 0;
-		our $cnt_chk++;
-	}
-}
-
-sub check_absolute_file {
-	my ($absolute, $herecurr) = @_;
-	my $file = $absolute;
-
-	##print "absolute<$absolute>\n";
-
-	# See if any suffix of this path is a path within the tree.
-	while ($file =~ s@^[^/]*/@@) {
-		if (-f "$root/$file") {
-			##print "file<$file>\n";
-			last;
-		}
-	}
-	if (! -f _)  {
-		return 0;
-	}
-
-	# It is, so see if the prefix is acceptable.
-	my $prefix = $absolute;
-	substr($prefix, -length($file)) = '';
-
-	##print "prefix<$prefix>\n";
-	if ($prefix ne ".../") {
-		WARN("USE_RELATIVE_PATH",
-		     "use relative pathname instead of absolute in changelog text\n" . $herecurr);
-	}
-}
-
-sub pos_last_openparen {
-	my ($line) = @_;
-
-	my $pos = 0;
-
-	my $opens = $line =~ tr/\(/\(/;
-	my $closes = $line =~ tr/\)/\)/;
-
-	my $last_openparen = 0;
-
-	if (($opens == 0) || ($closes >= $opens)) {
-		return -1;
-	}
-
-	my $len = length($line);
-
-	for ($pos = 0; $pos < $len; $pos++) {
-		my $string = substr($line, $pos);
-		if ($string =~ /^($FuncArg|$balanced_parens)/) {
-			$pos += length($1) - 1;
-		} elsif (substr($line, $pos, 1) eq '(') {
-			$last_openparen = $pos;
-		} elsif (index($string, '(') == -1) {
-			last;
-		}
-	}
-
-	return $last_openparen + 1;
-}
-
-sub process {
-	my $filename = shift;
-
-	my $linenr=0;
-	my $prevline="";
-	my $prevrawline="";
-	my $stashline="";
-	my $stashrawline="";
-
-	my $length;
-	my $indent;
-	my $previndent=0;
-	my $stashindent=0;
-
-	our $clean = 1;
-	my $signoff = 0;
-	my $is_patch = 0;
-
-	my $in_header_lines = 1;
-	my $in_commit_log = 0;		#Scanning lines before patch
-
-	my $non_utf8_charset = 0;
-
-	our @report = ();
-	our $cnt_lines = 0;
-	our $cnt_error = 0;
-	our $cnt_warn = 0;
-	our $cnt_chk = 0;
-
-	# Trace the real file/line as we go.
-	my $realfile = '';
-	my $realline = 0;
-	my $realcnt = 0;
-	my $here = '';
-	my $in_comment = 0;
-	my $comment_edge = 0;
-	my $first_line = 0;
-	my $p1_prefix = '';
-
-	my $prev_values = 'E';
-
-	# suppression flags
-	my %suppress_ifbraces;
-	my %suppress_whiletrailers;
-	my %suppress_export;
-	my $suppress_statement = 0;
-
-	my %camelcase = ();
-
-	# Pre-scan the patch sanitizing the lines.
-	# Pre-scan the patch looking for any __setup documentation.
-	#
-	my @setup_docs = ();
-	my $setup_docs = 0;
-
-	sanitise_line_reset();
-	my $line;
-	foreach my $rawline (@rawlines) {
-		$linenr++;
-		$line = $rawline;
-
-		if ($rawline=~/^\+\+\+\s+(\S+)/) {
-			$setup_docs = 0;
-			if ($1 =~ m@Documentation/kernel-parameters.txt$@) {
-				$setup_docs = 1;
-			}
-			#next;
-		}
-		if ($rawline=~/^\@\@ -\d+(?:,\d+)? \+(\d+)(,(\d+))? \@\@/) {
-			$realline=$1-1;
-			if (defined $2) {
-				$realcnt=$3+1;
-			} else {
-				$realcnt=1+1;
-			}
-			$in_comment = 0;
-
-			# Guestimate if this is a continuing comment.  Run
-			# the context looking for a comment "edge".  If this
-			# edge is a close comment then we must be in a comment
-			# at context start.
-			my $edge;
-			my $cnt = $realcnt;
-			for (my $ln = $linenr + 1; $cnt > 0; $ln++) {
-				next if (defined $rawlines[$ln - 1] &&
-					 $rawlines[$ln - 1] =~ /^-/);
-				$cnt--;
-				#print "RAW<$rawlines[$ln - 1]>\n";
-				last if (!defined $rawlines[$ln - 1]);
-				if ($rawlines[$ln - 1] =~ m@(/\*|\*/)@ &&
-				    $rawlines[$ln - 1] !~ m@"[^"]*(?:/\*|\*/)[^"]*"@) {
-					($edge) = $1;
-					last;
-				}
-			}
-			if (defined $edge && $edge eq '*/') {
-				$in_comment = 1;
-			}
-
-			# Guestimate if this is a continuing comment.  If this
-			# is the start of a diff block and this line starts
-			# ' *' then it is very likely a comment.
-			if (!defined $edge &&
-			    $rawlines[$linenr] =~ m@^.\s*(?:\*\*+| \*)(?:\s|$)@)
-			{
-				$in_comment = 1;
-			}
-
-			##print "COMMENT:$in_comment edge<$edge> $rawline\n";
-			sanitise_line_reset($in_comment);
-
-		} elsif ($realcnt && $rawline =~ /^(?:\+| |$)/) {
-			# Standardise the strings and chars within the input to
-			# simplify matching -- only bother with positive lines.
-			$line = sanitise_line($rawline);
-		}
-		push(@lines, $line);
-
-		if ($realcnt > 1) {
-			$realcnt-- if ($line =~ /^(?:\+| |$)/);
-		} else {
-			$realcnt = 0;
-		}
-
-		#print "==>$rawline\n";
-		#print "-->$line\n";
-
-		if ($setup_docs && $line =~ /^\+/) {
-			push(@setup_docs, $line);
-		}
-	}
-
-	$prefix = '';
-
-	$realcnt = 0;
-	$linenr = 0;
-	foreach my $line (@lines) {
-		$linenr++;
-
-		my $rawline = $rawlines[$linenr - 1];
-
-#extract the line range in the file after the patch is applied
-		if ($line=~/^\@\@ -\d+(?:,\d+)? \+(\d+)(,(\d+))? \@\@/) {
-			$is_patch = 1;
-			$first_line = $linenr + 1;
-			$realline=$1-1;
-			if (defined $2) {
-				$realcnt=$3+1;
-			} else {
-				$realcnt=1+1;
-			}
-			annotate_reset();
-			$prev_values = 'E';
-
-			%suppress_ifbraces = ();
-			%suppress_whiletrailers = ();
-			%suppress_export = ();
-			$suppress_statement = 0;
-			next;
-
-# track the line number as we move through the hunk, note that
-# new versions of GNU diff omit the leading space on completely
-# blank context lines so we need to count that too.
-		} elsif ($line =~ /^( |\+|$)/) {
-			$realline++;
-			$realcnt-- if ($realcnt != 0);
-
-			# Measure the line length and indent.
-			($length, $indent) = line_stats($rawline);
-
-			# Track the previous line.
-			($prevline, $stashline) = ($stashline, $line);
-			($previndent, $stashindent) = ($stashindent, $indent);
-			($prevrawline, $stashrawline) = ($stashrawline, $rawline);
-
-			#warn "line<$line>\n";
-
-		} elsif ($realcnt == 1) {
-			$realcnt--;
-		}
-
-		my $hunk_line = ($realcnt != 0);
-
-#make up the handle for any error we report on this line
-		$prefix = "$filename:$realline: " if ($emacs && $file);
-		$prefix = "$filename:$linenr: " if ($emacs && !$file);
-
-		$here = "#$linenr: " if (!$file);
-		$here = "#$realline: " if ($file);
-
-		# extract the filename as it passes
-		if ($line =~ /^diff --git.*?(\S+)$/) {
-			$realfile = $1;
-			$realfile =~ s@^([^/]*)/@@;
-			$in_commit_log = 0;
-		} elsif ($line =~ /^\+\+\+\s+(\S+)/) {
-			$realfile = $1;
-			$realfile =~ s@^([^/]*)/@@;
-			$in_commit_log = 0;
-
-			$p1_prefix = $1;
-			if (!$file && $tree && $p1_prefix ne '' &&
-			    -e "$root/$p1_prefix") {
-				WARN("PATCH_PREFIX",
-				     "patch prefix '$p1_prefix' exists, appears to be a -p0 patch\n");
-			}
-
-			if ($realfile =~ m@^include/asm/@) {
-				ERROR("MODIFIED_INCLUDE_ASM",
-				      "do not modify files in include/asm, change architecture specific files in include/asm-<architecture>\n" . "$here$rawline\n");
-			}
-			next;
-		}
-
-		$here .= "FILE: $realfile:$realline:" if ($realcnt != 0);
-
-		my $hereline = "$here\n$rawline\n";
-		my $herecurr = "$here\n$rawline\n";
-		my $hereprev = "$here\n$prevrawline\n$rawline\n";
-
-		$cnt_lines++ if ($realcnt != 0);
-
-# Check for incorrect file permissions
-		if ($line =~ /^new (file )?mode.*[7531]\d{0,2}$/) {
-			my $permhere = $here . "FILE: $realfile\n";
-			if ($realfile =~ /(Makefile|Kconfig|\.c|\.h|\.S|\.tmpl)$/) {
-				ERROR("EXECUTE_PERMISSIONS",
-				      "do not set execute permissions for source files\n" . $permhere);
-			}
-		}
-
-# Check the patch for a signoff:
-		if ($line =~ /^\s*signed-off-by:/i) {
-			$signoff++;
-			$in_commit_log = 0;
-		}
-
-# Check signature styles
-		if (!$in_header_lines &&
-		    $line =~ /^(\s*)([a-z0-9_-]+by:|$signature_tags)(\s*)(.*)/i) {
-			my $space_before = $1;
-			my $sign_off = $2;
-			my $space_after = $3;
-			my $email = $4;
-			my $ucfirst_sign_off = ucfirst(lc($sign_off));
-
-			if ($sign_off !~ /$signature_tags/) {
-				WARN("BAD_SIGN_OFF",
-				     "Non-standard signature: $sign_off\n" . $herecurr);
-			}
-			if (defined $space_before && $space_before ne "") {
-				WARN("BAD_SIGN_OFF",
-				     "Do not use whitespace before $ucfirst_sign_off\n" . $herecurr);
-			}
-			if ($sign_off =~ /-by:$/i && $sign_off ne $ucfirst_sign_off) {
-				WARN("BAD_SIGN_OFF",
-				     "'$ucfirst_sign_off' is the preferred signature form\n" . $herecurr);
-			}
-			if (!defined $space_after || $space_after ne " ") {
-				WARN("BAD_SIGN_OFF",
-				     "Use a single space after $ucfirst_sign_off\n" . $herecurr);
-			}
-
-			my ($email_name, $email_address, $comment) = parse_email($email);
-			my $suggested_email = format_email(($email_name, $email_address));
-			if ($suggested_email eq "") {
-				ERROR("BAD_SIGN_OFF",
-				      "Unrecognized email address: '$email'\n" . $herecurr);
-			} else {
-				my $dequoted = $suggested_email;
-				$dequoted =~ s/^"//;
-				$dequoted =~ s/" </ </;
-				# Don't force email to have quotes
-				# Allow just an angle bracketed address
-				if ("$dequoted$comment" ne $email &&
-				    "<$email_address>$comment" ne $email &&
-				    "$suggested_email$comment" ne $email) {
-					WARN("BAD_SIGN_OFF",
-					     "email address '$email' might be better as '$suggested_email$comment'\n" . $herecurr);
-				}
-			}
-		}
-
-# Check for wrappage within a valid hunk of the file
-		if ($realcnt != 0 && $line !~ m{^(?:\+|-| |\\ No newline|$)}) {
-			ERROR("CORRUPTED_PATCH",
-			      "patch seems to be corrupt (line wrapped?)\n" .
-				$herecurr) if (!$emitted_corrupt++);
-		}
-
-# Check for absolute kernel paths.
-		if ($tree) {
-			while ($line =~ m{(?:^|\s)(/\S*)}g) {
-				my $file = $1;
-
-				if ($file =~ m{^(.*?)(?::\d+)+:?$} &&
-				    check_absolute_file($1, $herecurr)) {
-					#
-				} else {
-					check_absolute_file($file, $herecurr);
-				}
-			}
-		}
-
-# UTF-8 regex found at http://www.w3.org/International/questions/qa-forms-utf-8.en.php
-		if (($realfile =~ /^$/ || $line =~ /^\+/) &&
-		    $rawline !~ m/^$UTF8*$/) {
-			my ($utf8_prefix) = ($rawline =~ /^($UTF8*)/);
-
-			my $blank = copy_spacing($rawline);
-			my $ptr = substr($blank, 0, length($utf8_prefix)) . "^";
-			my $hereptr = "$hereline$ptr\n";
-
-			CHK("INVALID_UTF8",
-			    "Invalid UTF-8, patch and commit message should be encoded in UTF-8\n" . $hereptr);
-		}
-
-# Check if it's the start of a commit log
-# (not a header line and we haven't seen the patch filename)
-		if ($in_header_lines && $realfile =~ /^$/ &&
-		    $rawline !~ /^(commit\b|from\b|[\w-]+:).+$/i) {
-			$in_header_lines = 0;
-			$in_commit_log = 1;
-		}
-
-# Check if there is UTF-8 in a commit log when a mail header has explicitly
-# declined it, i.e defined some charset where it is missing.
-		if ($in_header_lines &&
-		    $rawline =~ /^Content-Type:.+charset="(.+)".*$/ &&
-		    $1 !~ /utf-8/i) {
-			$non_utf8_charset = 1;
-		}
-
-		if ($in_commit_log && $non_utf8_charset && $realfile =~ /^$/ &&
-		    $rawline =~ /$NON_ASCII_UTF8/) {
-			WARN("UTF8_BEFORE_PATCH",
-			    "8-bit UTF-8 used in possible commit log\n" . $herecurr);
-		}
-
-# ignore non-hunk lines and lines being removed
-		next if (!$hunk_line || $line =~ /^-/);
-
-#trailing whitespace
-		if ($line =~ /^\+.*\015/) {
-			my $herevet = "$here\n" . cat_vet($rawline) . "\n";
-			ERROR("DOS_LINE_ENDINGS",
-			      "DOS line endings\n" . $herevet);
-
-		} elsif ($rawline =~ /^\+.*\S\s+$/ || $rawline =~ /^\+\s+$/) {
-			my $herevet = "$here\n" . cat_vet($rawline) . "\n";
-			ERROR("TRAILING_WHITESPACE",
-			      "trailing whitespace\n" . $herevet);
-			$rpt_cleaners = 1;
-		}
-
-# check for Kconfig help text having a real description
-# Only applies when adding the entry originally, after that we do not have
-# sufficient context to determine whether it is indeed long enough.
-		if ($realfile =~ /Kconfig/ &&
-		    $line =~ /.\s*config\s+/) {
-			my $length = 0;
-			my $cnt = $realcnt;
-			my $ln = $linenr + 1;
-			my $f;
-			my $is_start = 0;
-			my $is_end = 0;
-			for (; $cnt > 0 && defined $lines[$ln - 1]; $ln++) {
-				$f = $lines[$ln - 1];
-				$cnt-- if ($lines[$ln - 1] !~ /^-/);
-				$is_end = $lines[$ln - 1] =~ /^\+/;
-
-				next if ($f =~ /^-/);
-
-				if ($lines[$ln - 1] =~ /.\s*(?:bool|tristate)\s*\"/) {
-					$is_start = 1;
-				} elsif ($lines[$ln - 1] =~ /.\s*(?:---)?help(?:---)?$/) {
-					$length = -1;
-				}
-
-				$f =~ s/^.//;
-				$f =~ s/#.*//;
-				$f =~ s/^\s+//;
-				next if ($f =~ /^$/);
-				if ($f =~ /^\s*config\s/) {
-					$is_end = 1;
-					last;
-				}
-				$length++;
-			}
-			WARN("CONFIG_DESCRIPTION",
-			     "please write a paragraph that describes the config symbol fully\n" . $herecurr) if ($is_start && $is_end && $length < 4);
-			#print "is_start<$is_start> is_end<$is_end> length<$length>\n";
-		}
-
-# discourage the addition of CONFIG_EXPERIMENTAL in Kconfig.
-		if ($realfile =~ /Kconfig/ &&
-		    $line =~ /.\s*depends on\s+.*\bEXPERIMENTAL\b/) {
-			WARN("CONFIG_EXPERIMENTAL",
-			     "Use of CONFIG_EXPERIMENTAL is deprecated. For alternatives, see https://lkml.org/lkml/2012/10/23/580\n");
-		}
-
-		if (($realfile =~ /Makefile.*/ || $realfile =~ /Kbuild.*/) &&
-		    ($line =~ /\+(EXTRA_[A-Z]+FLAGS).*/)) {
-			my $flag = $1;
-			my $replacement = {
-				'EXTRA_AFLAGS' =>   'asflags-y',
-				'EXTRA_CFLAGS' =>   'ccflags-y',
-				'EXTRA_CPPFLAGS' => 'cppflags-y',
-				'EXTRA_LDFLAGS' =>  'ldflags-y',
-			};
-
-			WARN("DEPRECATED_VARIABLE",
-			     "Use of $flag is deprecated, please use \`$replacement->{$flag} instead.\n" . $herecurr) if ($replacement->{$flag});
-		}
-
-# check we are in a valid source file if not then ignore this hunk
-		next if ($realfile !~ /\.(h|c|s|S|pl|sh)$/);
-
-#line length limit
-		if ($line =~ /^\+/ && $prevrawline !~ /\/\*\*/ &&
-		    $rawline !~ /^.\s*\*\s*\@$Ident\s/ &&
-		    !($line =~ /^\+\s*$logFunctions\s*\(\s*(?:(KERN_\S+\s*|[^"]*))?"[X\t]*"\s*(?:|,|\)\s*;)\s*$/ ||
-		    $line =~ /^\+\s*"[^"]*"\s*(?:\s*|,|\)\s*;)\s*$/) &&
-		    $length > $max_line_length)
-		{
-			WARN("LONG_LINE",
-			     "line over $max_line_length characters\n" . $herecurr);
-		}
-
-# Check for user-visible strings broken across lines, which breaks the ability
-# to grep for the string.  Limited to strings used as parameters (those
-# following an open parenthesis), which almost completely eliminates false
-# positives, as well as warning only once per parameter rather than once per
-# line of the string.  Make an exception when the previous string ends in a
-# newline (multiple lines in one string constant) or \n\t (common in inline
-# assembly to indent the instruction on the following line).
-		if ($line =~ /^\+\s*"/ &&
-		    $prevline =~ /"\s*$/ &&
-		    $prevline =~ /\(/ &&
-		    $prevrawline !~ /\\n(?:\\t)*"\s*$/) {
-			WARN("SPLIT_STRING",
-			     "quoted string split across lines\n" . $hereprev);
-		}
-
-# check for spaces before a quoted newline
-		if ($rawline =~ /^.*\".*\s\\n/) {
-			WARN("QUOTED_WHITESPACE_BEFORE_NEWLINE",
-			     "unnecessary whitespace before a quoted newline\n" . $herecurr);
-		}
-
-# check for adding lines without a newline.
-		if ($line =~ /^\+/ && defined $lines[$linenr] && $lines[$linenr] =~ /^\\ No newline at end of file/) {
-			WARN("MISSING_EOF_NEWLINE",
-			     "adding a line without newline at end of file\n" . $herecurr);
-		}
-
-# Blackfin: use hi/lo macros
-		if ($realfile =~ m@arch/blackfin/.*\.S$@) {
-			if ($line =~ /\.[lL][[:space:]]*=.*&[[:space:]]*0x[fF][fF][fF][fF]/) {
-				my $herevet = "$here\n" . cat_vet($line) . "\n";
-				ERROR("LO_MACRO",
-				      "use the LO() macro, not (... & 0xFFFF)\n" . $herevet);
-			}
-			if ($line =~ /\.[hH][[:space:]]*=.*>>[[:space:]]*16/) {
-				my $herevet = "$here\n" . cat_vet($line) . "\n";
-				ERROR("HI_MACRO",
-				      "use the HI() macro, not (... >> 16)\n" . $herevet);
-			}
-		}
-
-# check we are in a valid source file C or perl if not then ignore this hunk
-		next if ($realfile !~ /\.(h|c|pl)$/);
-
-# at the beginning of a line any tabs must come first and anything
-# more than 8 must use tabs.
-		if ($rawline =~ /^\+\s* \t\s*\S/ ||
-		    $rawline =~ /^\+\s*        \s*/) {
-			my $herevet = "$here\n" . cat_vet($rawline) . "\n";
-			ERROR("CODE_INDENT",
-			      "code indent should use tabs where possible\n" . $herevet);
-			$rpt_cleaners = 1;
-		}
-
-# check for space before tabs.
-		if ($rawline =~ /^\+/ && $rawline =~ / \t/) {
-			my $herevet = "$here\n" . cat_vet($rawline) . "\n";
-			WARN("SPACE_BEFORE_TAB",
-			     "please, no space before tabs\n" . $herevet);
-		}
-
-# check for && or || at the start of a line
-		if ($rawline =~ /^\+\s*(&&|\|\|)/) {
-			CHK("LOGICAL_CONTINUATIONS",
-			    "Logical continuations should be on the previous line\n" . $hereprev);
-		}
-
-# check multi-line statement indentation matches previous line
-		if ($^V && $^V ge 5.10.0 &&
-		    $prevline =~ /^\+(\t*)(if \(|$Ident\().*(\&\&|\|\||,)\s*$/) {
-			$prevline =~ /^\+(\t*)(.*)$/;
-			my $oldindent = $1;
-			my $rest = $2;
-
-			my $pos = pos_last_openparen($rest);
-			if ($pos >= 0) {
-				$line =~ /^(\+| )([ \t]*)/;
-				my $newindent = $2;
-
-				my $goodtabindent = $oldindent .
-					"\t" x ($pos / 8) .
-					" "  x ($pos % 8);
-				my $goodspaceindent = $oldindent . " "  x $pos;
-
-				if ($newindent ne $goodtabindent &&
-				    $newindent ne $goodspaceindent) {
-					CHK("PARENTHESIS_ALIGNMENT",
-					    "Alignment should match open parenthesis\n" . $hereprev);
-				}
-			}
-		}
-
-		if ($line =~ /^\+.*\*[ \t]*\)[ \t]+/) {
-			CHK("SPACING",
-			    "No space is necessary after a cast\n" . $hereprev);
-		}
-
-		if ($realfile =~ m@^(drivers/net/|net/)@ &&
-		    $rawline =~ /^\+[ \t]*\/\*[ \t]*$/ &&
-		    $prevrawline =~ /^\+[ \t]*$/) {
-			WARN("NETWORKING_BLOCK_COMMENT_STYLE",
-			     "networking block comments don't use an empty /* line, use /* Comment...\n" . $hereprev);
-		}
-
-		if ($realfile =~ m@^(drivers/net/|net/)@ &&
-		    $rawline !~ m@^\+[ \t]*\*/[ \t]*$@ &&	#trailing */
-		    $rawline !~ m@^\+.*/\*.*\*/[ \t]*$@ &&	#inline /*...*/
-		    $rawline !~ m@^\+.*\*{2,}/[ \t]*$@ &&	#trailing **/
-		    $rawline =~ m@^\+[ \t]*.+\*\/[ \t]*$@) {	#non blank */
-			WARN("NETWORKING_BLOCK_COMMENT_STYLE",
-			     "networking block comments put the trailing */ on a separate line\n" . $herecurr);
-		}
-
-# check for spaces at the beginning of a line.
-# Exceptions:
-#  1) within comments
-#  2) indented preprocessor commands
-#  3) hanging labels
-		if ($rawline =~ /^\+ / && $line !~ /\+ *(?:$;|#|$Ident:)/)  {
-			my $herevet = "$here\n" . cat_vet($rawline) . "\n";
-			WARN("LEADING_SPACE",
-			     "please, no spaces at the start of a line\n" . $herevet);
-		}
-
-# check we are in a valid C source file if not then ignore this hunk
-		next if ($realfile !~ /\.(h|c)$/);
-
-# discourage the addition of CONFIG_EXPERIMENTAL in #if(def).
-		if ($line =~ /^\+\s*\#\s*if.*\bCONFIG_EXPERIMENTAL\b/) {
-			WARN("CONFIG_EXPERIMENTAL",
-			     "Use of CONFIG_EXPERIMENTAL is deprecated. For alternatives, see https://lkml.org/lkml/2012/10/23/580\n");
-		}
-
-# check for RCS/CVS revision markers
-		if ($rawline =~ /^\+.*\$(Revision|Log|Id)(?:\$|)/) {
-			WARN("CVS_KEYWORD",
-			     "CVS style keyword markers, these will _not_ be updated\n". $herecurr);
-		}
-
-# Blackfin: don't use __builtin_bfin_[cs]sync
-		if ($line =~ /__builtin_bfin_csync/) {
-			my $herevet = "$here\n" . cat_vet($line) . "\n";
-			ERROR("CSYNC",
-			      "use the CSYNC() macro in asm/blackfin.h\n" . $herevet);
-		}
-		if ($line =~ /__builtin_bfin_ssync/) {
-			my $herevet = "$here\n" . cat_vet($line) . "\n";
-			ERROR("SSYNC",
-			      "use the SSYNC() macro in asm/blackfin.h\n" . $herevet);
-		}
-
-# check for old HOTPLUG __dev<foo> section markings
-		if ($line =~ /\b(__dev(init|exit)(data|const|))\b/) {
-			WARN("HOTPLUG_SECTION",
-			     "Using $1 is unnecessary\n" . $herecurr);
-		}
-
-# Check for potential 'bare' types
-		my ($stat, $cond, $line_nr_next, $remain_next, $off_next,
-		    $realline_next);
-#print "LINE<$line>\n";
-		if ($linenr >= $suppress_statement &&
-		    $realcnt && $line =~ /.\s*\S/) {
-			($stat, $cond, $line_nr_next, $remain_next, $off_next) =
-				ctx_statement_block($linenr, $realcnt, 0);
-			$stat =~ s/\n./\n /g;
-			$cond =~ s/\n./\n /g;
-
-#print "linenr<$linenr> <$stat>\n";
-			# If this statement has no statement boundaries within
-			# it there is no point in retrying a statement scan
-			# until we hit end of it.
-			my $frag = $stat; $frag =~ s/;+\s*$//;
-			if ($frag !~ /(?:{|;)/) {
-#print "skip<$line_nr_next>\n";
-				$suppress_statement = $line_nr_next;
-			}
-
-			# Find the real next line.
-			$realline_next = $line_nr_next;
-			if (defined $realline_next &&
-			    (!defined $lines[$realline_next - 1] ||
-			     substr($lines[$realline_next - 1], $off_next) =~ /^\s*$/)) {
-				$realline_next++;
-			}
-
-			my $s = $stat;
-			$s =~ s/{.*$//s;
-
-			# Ignore goto labels.
-			if ($s =~ /$Ident:\*$/s) {
-
-			# Ignore functions being called
-			} elsif ($s =~ /^.\s*$Ident\s*\(/s) {
-
-			} elsif ($s =~ /^.\s*else\b/s) {
-
-			# declarations always start with types
-			} elsif ($prev_values eq 'E' && $s =~ /^.\s*(?:$Storage\s+)?(?:$Inline\s+)?(?:const\s+)?((?:\s*$Ident)+?)\b(?:\s+$Sparse)?\s*\**\s*(?:$Ident|\(\*[^\)]*\))(?:\s*$Modifier)?\s*(?:;|=|,|\()/s) {
-				my $type = $1;
-				$type =~ s/\s+/ /g;
-				possible($type, "A:" . $s);
-
-			# definitions in global scope can only start with types
-			} elsif ($s =~ /^.(?:$Storage\s+)?(?:$Inline\s+)?(?:const\s+)?($Ident)\b\s*(?!:)/s) {
-				possible($1, "B:" . $s);
-			}
-
-			# any (foo ... *) is a pointer cast, and foo is a type
-			while ($s =~ /\(($Ident)(?:\s+$Sparse)*[\s\*]+\s*\)/sg) {
-				possible($1, "C:" . $s);
-			}
-
-			# Check for any sort of function declaration.
-			# int foo(something bar, other baz);
-			# void (*store_gdt)(x86_descr_ptr *);
-			if ($prev_values eq 'E' && $s =~ /^(.(?:typedef\s*)?(?:(?:$Storage|$Inline)\s*)*\s*$Type\s*(?:\b$Ident|\(\*\s*$Ident\))\s*)\(/s) {
-				my ($name_len) = length($1);
-
-				my $ctx = $s;
-				substr($ctx, 0, $name_len + 1, '');
-				$ctx =~ s/\)[^\)]*$//;
-
-				for my $arg (split(/\s*,\s*/, $ctx)) {
-					if ($arg =~ /^(?:const\s+)?($Ident)(?:\s+$Sparse)*\s*\**\s*(:?\b$Ident)?$/s || $arg =~ /^($Ident)$/s) {
-
-						possible($1, "D:" . $s);
-					}
-				}
-			}
-
-		}
-
-#
-# Checks which may be anchored in the context.
-#
-
-# Check for switch () and associated case and default
-# statements should be at the same indent.
-		if ($line=~/\bswitch\s*\(.*\)/) {
-			my $err = '';
-			my $sep = '';
-			my @ctx = ctx_block_outer($linenr, $realcnt);
-			shift(@ctx);
-			for my $ctx (@ctx) {
-				my ($clen, $cindent) = line_stats($ctx);
-				if ($ctx =~ /^\+\s*(case\s+|default:)/ &&
-							$indent != $cindent) {
-					$err .= "$sep$ctx\n";
-					$sep = '';
-				} else {
-					$sep = "[...]\n";
-				}
-			}
-			if ($err ne '') {
-				ERROR("SWITCH_CASE_INDENT_LEVEL",
-				      "switch and case should be at the same indent\n$hereline$err");
-			}
-		}
-
-# if/while/etc brace do not go on next line, unless defining a do while loop,
-# or if that brace on the next line is for something else
-		if ($line =~ /(.*)\b((?:if|while|for|switch)\s*\(|do\b|else\b)/ && $line !~ /^.\s*\#/) {
-			my $pre_ctx = "$1$2";
-
-			my ($level, @ctx) = ctx_statement_level($linenr, $realcnt, 0);
-
-			if ($line =~ /^\+\t{6,}/) {
-				WARN("DEEP_INDENTATION",
-				     "Too many leading tabs - consider code refactoring\n" . $herecurr);
-			}
-
-			my $ctx_cnt = $realcnt - $#ctx - 1;
-			my $ctx = join("\n", @ctx);
-
-			my $ctx_ln = $linenr;
-			my $ctx_skip = $realcnt;
-
-			while ($ctx_skip > $ctx_cnt || ($ctx_skip == $ctx_cnt &&
-					defined $lines[$ctx_ln - 1] &&
-					$lines[$ctx_ln - 1] =~ /^-/)) {
-				##print "SKIP<$ctx_skip> CNT<$ctx_cnt>\n";
-				$ctx_skip-- if (!defined $lines[$ctx_ln - 1] || $lines[$ctx_ln - 1] !~ /^-/);
-				$ctx_ln++;
-			}
-
-			#print "realcnt<$realcnt> ctx_cnt<$ctx_cnt>\n";
-			#print "pre<$pre_ctx>\nline<$line>\nctx<$ctx>\nnext<$lines[$ctx_ln - 1]>\n";
-
-			if ($ctx !~ /{\s*/ && defined($lines[$ctx_ln -1]) && $lines[$ctx_ln - 1] =~ /^\+\s*{/) {
-				ERROR("OPEN_BRACE",
-				      "that open brace { should be on the previous line\n" .
-					"$here\n$ctx\n$rawlines[$ctx_ln - 1]\n");
-			}
-			if ($level == 0 && $pre_ctx !~ /}\s*while\s*\($/ &&
-			    $ctx =~ /\)\s*\;\s*$/ &&
-			    defined $lines[$ctx_ln - 1])
-			{
-				my ($nlength, $nindent) = line_stats($lines[$ctx_ln - 1]);
-				if ($nindent > $indent) {
-					WARN("TRAILING_SEMICOLON",
-					     "trailing semicolon indicates no statements, indent implies otherwise\n" .
-						"$here\n$ctx\n$rawlines[$ctx_ln - 1]\n");
-				}
-			}
-		}
-
-# Check relative indent for conditionals and blocks.
-		if ($line =~ /\b(?:(?:if|while|for)\s*\(|do\b)/ && $line !~ /^.\s*#/ && $line !~ /\}\s*while\s*/) {
-			($stat, $cond, $line_nr_next, $remain_next, $off_next) =
-				ctx_statement_block($linenr, $realcnt, 0)
-					if (!defined $stat);
-			my ($s, $c) = ($stat, $cond);
-
-			substr($s, 0, length($c), '');
-
-			# Make sure we remove the line prefixes as we have
-			# none on the first line, and are going to readd them
-			# where necessary.
-			$s =~ s/\n./\n/gs;
-
-			# Find out how long the conditional actually is.
-			my @newlines = ($c =~ /\n/gs);
-			my $cond_lines = 1 + $#newlines;
-
-			# We want to check the first line inside the block
-			# starting at the end of the conditional, so remove:
-			#  1) any blank line termination
-			#  2) any opening brace { on end of the line
-			#  3) any do (...) {
-			my $continuation = 0;
-			my $check = 0;
-			$s =~ s/^.*\bdo\b//;
-			$s =~ s/^\s*{//;
-			if ($s =~ s/^\s*\\//) {
-				$continuation = 1;
-			}
-			if ($s =~ s/^\s*?\n//) {
-				$check = 1;
-				$cond_lines++;
-			}
-
-			# Also ignore a loop construct at the end of a
-			# preprocessor statement.
-			if (($prevline =~ /^.\s*#\s*define\s/ ||
-			    $prevline =~ /\\\s*$/) && $continuation == 0) {
-				$check = 0;
-			}
-
-			my $cond_ptr = -1;
-			$continuation = 0;
-			while ($cond_ptr != $cond_lines) {
-				$cond_ptr = $cond_lines;
-
-				# If we see an #else/#elif then the code
-				# is not linear.
-				if ($s =~ /^\s*\#\s*(?:else|elif)/) {
-					$check = 0;
-				}
-
-				# Ignore:
-				#  1) blank lines, they should be at 0,
-				#  2) preprocessor lines, and
-				#  3) labels.
-				if ($continuation ||
-				    $s =~ /^\s*?\n/ ||
-				    $s =~ /^\s*#\s*?/ ||
-				    $s =~ /^\s*$Ident\s*:/) {
-					$continuation = ($s =~ /^.*?\\\n/) ? 1 : 0;
-					if ($s =~ s/^.*?\n//) {
-						$cond_lines++;
-					}
-				}
-			}
-
-			my (undef, $sindent) = line_stats("+" . $s);
-			my $stat_real = raw_line($linenr, $cond_lines);
-
-			# Check if either of these lines are modified, else
-			# this is not this patch's fault.
-			if (!defined($stat_real) ||
-			    $stat !~ /^\+/ && $stat_real !~ /^\+/) {
-				$check = 0;
-			}
-			if (defined($stat_real) && $cond_lines > 1) {
-				$stat_real = "[...]\n$stat_real";
-			}
-
-			#print "line<$line> prevline<$prevline> indent<$indent> sindent<$sindent> check<$check> continuation<$continuation> s<$s> cond_lines<$cond_lines> stat_real<$stat_real> stat<$stat>\n";
-
-			if ($check && (($sindent % 8) != 0 ||
-			    ($sindent <= $indent && $s ne ''))) {
-				WARN("SUSPECT_CODE_INDENT",
-				     "suspect code indent for conditional statements ($indent, $sindent)\n" . $herecurr . "$stat_real\n");
-			}
-		}
-
-		# Track the 'values' across context and added lines.
-		my $opline = $line; $opline =~ s/^./ /;
-		my ($curr_values, $curr_vars) =
-				annotate_values($opline . "\n", $prev_values);
-		$curr_values = $prev_values . $curr_values;
-		if ($dbg_values) {
-			my $outline = $opline; $outline =~ s/\t/ /g;
-			print "$linenr > .$outline\n";
-			print "$linenr > $curr_values\n";
-			print "$linenr >  $curr_vars\n";
-		}
-		$prev_values = substr($curr_values, -1);
-
-#ignore lines not being added
-		if ($line=~/^[^\+]/) {next;}
-
-# TEST: allow direct testing of the type matcher.
-		if ($dbg_type) {
-			if ($line =~ /^.\s*$Declare\s*$/) {
-				ERROR("TEST_TYPE",
-				      "TEST: is type\n" . $herecurr);
-			} elsif ($dbg_type > 1 && $line =~ /^.+($Declare)/) {
-				ERROR("TEST_NOT_TYPE",
-				      "TEST: is not type ($1 is)\n". $herecurr);
-			}
-			next;
-		}
-# TEST: allow direct testing of the attribute matcher.
-		if ($dbg_attr) {
-			if ($line =~ /^.\s*$Modifier\s*$/) {
-				ERROR("TEST_ATTR",
-				      "TEST: is attr\n" . $herecurr);
-			} elsif ($dbg_attr > 1 && $line =~ /^.+($Modifier)/) {
-				ERROR("TEST_NOT_ATTR",
-				      "TEST: is not attr ($1 is)\n". $herecurr);
-			}
-			next;
-		}
-
-# check for initialisation to aggregates open brace on the next line
-		if ($line =~ /^.\s*{/ &&
-		    $prevline =~ /(?:^|[^=])=\s*$/) {
-			ERROR("OPEN_BRACE",
-			      "that open brace { should be on the previous line\n" . $hereprev);
-		}
-
-#
-# Checks which are anchored on the added line.
-#
-
-# check for malformed paths in #include statements (uses RAW line)
-		if ($rawline =~ m{^.\s*\#\s*include\s+[<"](.*)[">]}) {
-			my $path = $1;
-			if ($path =~ m{//}) {
-				ERROR("MALFORMED_INCLUDE",
-				      "malformed #include filename\n" . $herecurr);
-			}
-			if ($path =~ "^uapi/" && $realfile =~ m@\binclude/uapi/@) {
-				ERROR("UAPI_INCLUDE",
-				      "No #include in ...include/uapi/... should use a uapi/ path prefix\n" . $herecurr);
-			}
-		}
-
-# no C99 // comments
-		if ($line =~ m{//}) {
-			ERROR("C99_COMMENTS",
-			      "do not use C99 // comments\n" . $herecurr);
-		}
-		# Remove C99 comments.
-		$line =~ s@//.*@@;
-		$opline =~ s@//.*@@;
-
-# EXPORT_SYMBOL should immediately follow the thing it is exporting, consider
-# the whole statement.
-#print "APW <$lines[$realline_next - 1]>\n";
-		if (defined $realline_next &&
-		    exists $lines[$realline_next - 1] &&
-		    !defined $suppress_export{$realline_next} &&
-		    ($lines[$realline_next - 1] =~ /EXPORT_SYMBOL.*\((.*)\)/ ||
-		     $lines[$realline_next - 1] =~ /EXPORT_UNUSED_SYMBOL.*\((.*)\)/)) {
-			# Handle definitions which produce identifiers with
-			# a prefix:
-			#   XXX(foo);
-			#   EXPORT_SYMBOL(something_foo);
-			my $name = $1;
-			if ($stat =~ /^(?:.\s*}\s*\n)?.([A-Z_]+)\s*\(\s*($Ident)/ &&
-			    $name =~ /^${Ident}_$2/) {
-#print "FOO C name<$name>\n";
-				$suppress_export{$realline_next} = 1;
-
-			} elsif ($stat !~ /(?:
-				\n.}\s*$|
-				^.DEFINE_$Ident\(\Q$name\E\)|
-				^.DECLARE_$Ident\(\Q$name\E\)|
-				^.LIST_HEAD\(\Q$name\E\)|
-				^.(?:$Storage\s+)?$Type\s*\(\s*\*\s*\Q$name\E\s*\)\s*\(|
-				\b\Q$name\E(?:\s+$Attribute)*\s*(?:;|=|\[|\()
-			    )/x) {
-#print "FOO A<$lines[$realline_next - 1]> stat<$stat> name<$name>\n";
-				$suppress_export{$realline_next} = 2;
-			} else {
-				$suppress_export{$realline_next} = 1;
-			}
-		}
-		if (!defined $suppress_export{$linenr} &&
-		    $prevline =~ /^.\s*$/ &&
-		    ($line =~ /EXPORT_SYMBOL.*\((.*)\)/ ||
-		     $line =~ /EXPORT_UNUSED_SYMBOL.*\((.*)\)/)) {
-#print "FOO B <$lines[$linenr - 1]>\n";
-			$suppress_export{$linenr} = 2;
-		}
-		if (defined $suppress_export{$linenr} &&
-		    $suppress_export{$linenr} == 2) {
-			WARN("EXPORT_SYMBOL",
-			     "EXPORT_SYMBOL(foo); should immediately follow its function/variable\n" . $herecurr);
-		}
-
-# check for global initialisers.
-		if ($line =~ /^.$Type\s*$Ident\s*(?:\s+$Modifier)*\s*=\s*(0|NULL|false)\s*;/) {
-			ERROR("GLOBAL_INITIALISERS",
-			      "do not initialise globals to 0 or NULL\n" .
-				$herecurr);
-		}
-# check for static initialisers.
-		if ($line =~ /\bstatic\s.*=\s*(0|NULL|false)\s*;/) {
-			ERROR("INITIALISED_STATIC",
-			      "do not initialise statics to 0 or NULL\n" .
-				$herecurr);
-		}
-
-# check for static const char * arrays.
-		if ($line =~ /\bstatic\s+const\s+char\s*\*\s*(\w+)\s*\[\s*\]\s*=\s*/) {
-			WARN("STATIC_CONST_CHAR_ARRAY",
-			     "static const char * array should probably be static const char * const\n" .
-				$herecurr);
-               }
-
-# check for static char foo[] = "bar" declarations.
-		if ($line =~ /\bstatic\s+char\s+(\w+)\s*\[\s*\]\s*=\s*"/) {
-			WARN("STATIC_CONST_CHAR_ARRAY",
-			     "static char array declaration should probably be static const char\n" .
-				$herecurr);
-               }
-
-# check for declarations of struct pci_device_id
-		if ($line =~ /\bstruct\s+pci_device_id\s+\w+\s*\[\s*\]\s*\=\s*\{/) {
-			WARN("DEFINE_PCI_DEVICE_TABLE",
-			     "Use DEFINE_PCI_DEVICE_TABLE for struct pci_device_id\n" . $herecurr);
-		}
-
-# check for new typedefs, only function parameters and sparse annotations
-# make sense.
-		if ($line =~ /\btypedef\s/ &&
-		    $line !~ /\btypedef\s+$Type\s*\(\s*\*?$Ident\s*\)\s*\(/ &&
-		    $line !~ /\btypedef\s+$Type\s+$Ident\s*\(/ &&
-		    $line !~ /\b$typeTypedefs\b/ &&
-		    $line !~ /\b__bitwise(?:__|)\b/) {
-			WARN("NEW_TYPEDEFS",
-			     "do not add new typedefs\n" . $herecurr);
-		}
-
-# * goes on variable not on type
-		# (char*[ const])
-		while ($line =~ m{(\($NonptrType(\s*(?:$Modifier\b\s*|\*\s*)+)\))}g) {
-			#print "AA<$1>\n";
-			my ($from, $to) = ($2, $2);
-
-			# Should start with a space.
-			$to =~ s/^(\S)/ $1/;
-			# Should not end with a space.
-			$to =~ s/\s+$//;
-			# '*'s should not have spaces between.
-			while ($to =~ s/\*\s+\*/\*\*/) {
-			}
-
-			#print "from<$from> to<$to>\n";
-			if ($from ne $to) {
-				ERROR("POINTER_LOCATION",
-				      "\"(foo$from)\" should be \"(foo$to)\"\n" .  $herecurr);
-			}
-		}
-		while ($line =~ m{(\b$NonptrType(\s*(?:$Modifier\b\s*|\*\s*)+)($Ident))}g) {
-			#print "BB<$1>\n";
-			my ($from, $to, $ident) = ($2, $2, $3);
-
-			# Should start with a space.
-			$to =~ s/^(\S)/ $1/;
-			# Should not end with a space.
-			$to =~ s/\s+$//;
-			# '*'s should not have spaces between.
-			while ($to =~ s/\*\s+\*/\*\*/) {
-			}
-			# Modifiers should have spaces.
-			$to =~ s/(\b$Modifier$)/$1 /;
-
-			#print "from<$from> to<$to> ident<$ident>\n";
-			if ($from ne $to && $ident !~ /^$Modifier$/) {
-				ERROR("POINTER_LOCATION",
-				      "\"foo${from}bar\" should be \"foo${to}bar\"\n" .  $herecurr);
-			}
-		}
-
-# # no BUG() or BUG_ON()
-# 		if ($line =~ /\b(BUG|BUG_ON)\b/) {
-# 			print "Try to use WARN_ON & Recovery code rather than BUG() or BUG_ON()\n";
-# 			print "$herecurr";
-# 			$clean = 0;
-# 		}
-
-		if ($line =~ /\bLINUX_VERSION_CODE\b/) {
-			WARN("LINUX_VERSION_CODE",
-			     "LINUX_VERSION_CODE should be avoided, code should be for the version to which it is merged\n" . $herecurr);
-		}
-
-# check for uses of printk_ratelimit
-		if ($line =~ /\bprintk_ratelimit\s*\(/) {
-			WARN("PRINTK_RATELIMITED",
-"Prefer printk_ratelimited or pr_<level>_ratelimited to printk_ratelimit\n" . $herecurr);
-		}
-
-# printk should use KERN_* levels.  Note that follow on printk's on the
-# same line do not need a level, so we use the current block context
-# to try and find and validate the current printk.  In summary the current
-# printk includes all preceding printk's which have no newline on the end.
-# we assume the first bad printk is the one to report.
-		if ($line =~ /\bprintk\((?!KERN_)\s*"/) {
-			my $ok = 0;
-			for (my $ln = $linenr - 1; $ln >= $first_line; $ln--) {
-				#print "CHECK<$lines[$ln - 1]\n";
-				# we have a preceding printk if it ends
-				# with "\n" ignore it, else it is to blame
-				if ($lines[$ln - 1] =~ m{\bprintk\(}) {
-					if ($rawlines[$ln - 1] !~ m{\\n"}) {
-						$ok = 1;
-					}
-					last;
-				}
-			}
-			if ($ok == 0) {
-				WARN("PRINTK_WITHOUT_KERN_LEVEL",
-				     "printk() should include KERN_ facility level\n" . $herecurr);
-			}
-		}
-
-		if ($line =~ /\bprintk\s*\(\s*KERN_([A-Z]+)/) {
-			my $orig = $1;
-			my $level = lc($orig);
-			$level = "warn" if ($level eq "warning");
-			my $level2 = $level;
-			$level2 = "dbg" if ($level eq "debug");
-			WARN("PREFER_PR_LEVEL",
-			     "Prefer netdev_$level2(netdev, ... then dev_$level2(dev, ... then pr_$level(...  to printk(KERN_$orig ...\n" . $herecurr);
-		}
-
-		if ($line =~ /\bpr_warning\s*\(/) {
-			WARN("PREFER_PR_LEVEL",
-			     "Prefer pr_warn(... to pr_warning(...\n" . $herecurr);
-		}
-
-		if ($line =~ /\bdev_printk\s*\(\s*KERN_([A-Z]+)/) {
-			my $orig = $1;
-			my $level = lc($orig);
-			$level = "warn" if ($level eq "warning");
-			$level = "dbg" if ($level eq "debug");
-			WARN("PREFER_DEV_LEVEL",
-			     "Prefer dev_$level(... to dev_printk(KERN_$orig, ...\n" . $herecurr);
-		}
-
-# function brace can't be on same line, except for #defines of do while,
-# or if closed on same line
-		if (($line=~/$Type\s*$Ident\(.*\).*\s{/) and
-		    !($line=~/\#\s*define.*do\s{/) and !($line=~/}/)) {
-			ERROR("OPEN_BRACE",
-			      "open brace '{' following function declarations go on the next line\n" . $herecurr);
-		}
-
-# open braces for enum, union and struct go on the same line.
-		if ($line =~ /^.\s*{/ &&
-		    $prevline =~ /^.\s*(?:typedef\s+)?(enum|union|struct)(?:\s+$Ident)?\s*$/) {
-			ERROR("OPEN_BRACE",
-			      "open brace '{' following $1 go on the same line\n" . $hereprev);
-		}
-
-# missing space after union, struct or enum definition
-		if ($line =~ /^.\s*(?:typedef\s+)?(enum|union|struct)(?:\s+$Ident)?(?:\s+$Ident)?[=\{]/) {
-		    WARN("SPACING",
-			 "missing space after $1 definition\n" . $herecurr);
-		}
-
-# check for spacing round square brackets; allowed:
-#  1. with a type on the left -- int [] a;
-#  2. at the beginning of a line for slice initialisers -- [0...10] = 5,
-#  3. inside a curly brace -- = { [0...10] = 5 }
-		while ($line =~ /(.*?\s)\[/g) {
-			my ($where, $prefix) = ($-[1], $1);
-			if ($prefix !~ /$Type\s+$/ &&
-			    ($where != 0 || $prefix !~ /^.\s+$/) &&
-			    $prefix !~ /[{,]\s+$/) {
-				ERROR("BRACKET_SPACE",
-				      "space prohibited before open square bracket '['\n" . $herecurr);
-			}
-		}
-
-# check for spaces between functions and their parentheses.
-		while ($line =~ /($Ident)\s+\(/g) {
-			my $name = $1;
-			my $ctx_before = substr($line, 0, $-[1]);
-			my $ctx = "$ctx_before$name";
-
-			# Ignore those directives where spaces _are_ permitted.
-			if ($name =~ /^(?:
-				if|for|while|switch|return|case|
-				volatile|__volatile__|
-				__attribute__|format|__extension__|
-				asm|__asm__)$/x)
-			{
-
-			# cpp #define statements have non-optional spaces, ie
-			# if there is a space between the name and the open
-			# parenthesis it is simply not a parameter group.
-			} elsif ($ctx_before =~ /^.\s*\#\s*define\s*$/) {
-
-			# cpp #elif statement condition may start with a (
-			} elsif ($ctx =~ /^.\s*\#\s*elif\s*$/) {
-
-			# If this whole things ends with a type its most
-			# likely a typedef for a function.
-			} elsif ($ctx =~ /$Type$/) {
-
-			} else {
-				WARN("SPACING",
-				     "space prohibited between function name and open parenthesis '('\n" . $herecurr);
-			}
-		}
-
-# check for whitespace before a non-naked semicolon
-		if ($line =~ /^\+.*\S\s+;/) {
-			CHK("SPACING",
-			    "space prohibited before semicolon\n" . $herecurr);
-		}
-
-# Check operator spacing.
-		if (!($line=~/\#\s*include/)) {
-			my $ops = qr{
-				<<=|>>=|<=|>=|==|!=|
-				\+=|-=|\*=|\/=|%=|\^=|\|=|&=|
-				=>|->|<<|>>|<|>|=|!|~|
-				&&|\|\||,|\^|\+\+|--|&|\||\+|-|\*|\/|%|
-				\?|:
-			}x;
-			my @elements = split(/($ops|;)/, $opline);
-			my $off = 0;
-
-			my $blank = copy_spacing($opline);
-
-			for (my $n = 0; $n < $#elements; $n += 2) {
-				$off += length($elements[$n]);
-
-				# Pick up the preceding and succeeding characters.
-				my $ca = substr($opline, 0, $off);
-				my $cc = '';
-				if (length($opline) >= ($off + length($elements[$n + 1]))) {
-					$cc = substr($opline, $off + length($elements[$n + 1]));
-				}
-				my $cb = "$ca$;$cc";
-
-				my $a = '';
-				$a = 'V' if ($elements[$n] ne '');
-				$a = 'W' if ($elements[$n] =~ /\s$/);
-				$a = 'C' if ($elements[$n] =~ /$;$/);
-				$a = 'B' if ($elements[$n] =~ /(\[|\()$/);
-				$a = 'O' if ($elements[$n] eq '');
-				$a = 'E' if ($ca =~ /^\s*$/);
-
-				my $op = $elements[$n + 1];
-
-				my $c = '';
-				if (defined $elements[$n + 2]) {
-					$c = 'V' if ($elements[$n + 2] ne '');
-					$c = 'W' if ($elements[$n + 2] =~ /^\s/);
-					$c = 'C' if ($elements[$n + 2] =~ /^$;/);
-					$c = 'B' if ($elements[$n + 2] =~ /^(\)|\]|;)/);
-					$c = 'O' if ($elements[$n + 2] eq '');
-					$c = 'E' if ($elements[$n + 2] =~ /^\s*\\$/);
-				} else {
-					$c = 'E';
-				}
-
-				my $ctx = "${a}x${c}";
-
-				my $at = "(ctx:$ctx)";
-
-				my $ptr = substr($blank, 0, $off) . "^";
-				my $hereptr = "$hereline$ptr\n";
-
-				# Pull out the value of this operator.
-				my $op_type = substr($curr_values, $off + 1, 1);
-
-				# Get the full operator variant.
-				my $opv = $op . substr($curr_vars, $off, 1);
-
-				# Ignore operators passed as parameters.
-				if ($op_type ne 'V' &&
-				    $ca =~ /\s$/ && $cc =~ /^\s*,/) {
-
-#				# Ignore comments
-#				} elsif ($op =~ /^$;+$/) {
-
-				# ; should have either the end of line or a space or \ after it
-				} elsif ($op eq ';') {
-					if ($ctx !~ /.x[WEBC]/ &&
-					    $cc !~ /^\\/ && $cc !~ /^;/) {
-						ERROR("SPACING",
-						      "space required after that '$op' $at\n" . $hereptr);
-					}
-
-				# // is a comment
-				} elsif ($op eq '//') {
-
-				# No spaces for:
-				#   ->
-				#   :   when part of a bitfield
-				} elsif ($op eq '->' || $opv eq ':B') {
-					if ($ctx =~ /Wx.|.xW/) {
-						ERROR("SPACING",
-						      "spaces prohibited around that '$op' $at\n" . $hereptr);
-					}
-
-				# , must have a space on the right.
-				} elsif ($op eq ',') {
-					if ($ctx !~ /.x[WEC]/ && $cc !~ /^}/) {
-						ERROR("SPACING",
-						      "space required after that '$op' $at\n" . $hereptr);
-					}
-
-				# '*' as part of a type definition -- reported already.
-				} elsif ($opv eq '*_') {
-					#warn "'*' is part of type\n";
-
-				# unary operators should have a space before and
-				# none after.  May be left adjacent to another
-				# unary operator, or a cast
-				} elsif ($op eq '!' || $op eq '~' ||
-					 $opv eq '*U' || $opv eq '-U' ||
-					 $opv eq '&U' || $opv eq '&&U') {
-					if ($ctx !~ /[WEBC]x./ && $ca !~ /(?:\)|!|~|\*|-|\&|\||\+\+|\-\-|\{)$/) {
-						ERROR("SPACING",
-						      "space required before that '$op' $at\n" . $hereptr);
-					}
-					if ($op eq '*' && $cc =~/\s*$Modifier\b/) {
-						# A unary '*' may be const
-
-					} elsif ($ctx =~ /.xW/) {
-						ERROR("SPACING",
-						      "space prohibited after that '$op' $at\n" . $hereptr);
-					}
-
-				# unary ++ and unary -- are allowed no space on one side.
-				} elsif ($op eq '++' or $op eq '--') {
-					if ($ctx !~ /[WEOBC]x[^W]/ && $ctx !~ /[^W]x[WOBEC]/) {
-						ERROR("SPACING",
-						      "space required one side of that '$op' $at\n" . $hereptr);
-					}
-					if ($ctx =~ /Wx[BE]/ ||
-					    ($ctx =~ /Wx./ && $cc =~ /^;/)) {
-						ERROR("SPACING",
-						      "space prohibited before that '$op' $at\n" . $hereptr);
-					}
-					if ($ctx =~ /ExW/) {
-						ERROR("SPACING",
-						      "space prohibited after that '$op' $at\n" . $hereptr);
-					}
-
-
-				# << and >> may either have or not have spaces both sides
-				} elsif ($op eq '<<' or $op eq '>>' or
-					 $op eq '&' or $op eq '^' or $op eq '|' or
-					 $op eq '+' or $op eq '-' or
-					 $op eq '*' or $op eq '/' or
-					 $op eq '%')
-				{
-					if ($ctx =~ /Wx[^WCE]|[^WCE]xW/) {
-						ERROR("SPACING",
-						      "need consistent spacing around '$op' $at\n" .
-							$hereptr);
-					}
-
-				# A colon needs no spaces before when it is
-				# terminating a case value or a label.
-				} elsif ($opv eq ':C' || $opv eq ':L') {
-					if ($ctx =~ /Wx./) {
-						ERROR("SPACING",
-						      "space prohibited before that '$op' $at\n" . $hereptr);
-					}
-
-				# All the others need spaces both sides.
-				} elsif ($ctx !~ /[EWC]x[CWE]/) {
-					my $ok = 0;
-
-					# Ignore email addresses <foo@bar>
-					if (($op eq '<' &&
-					     $cc =~ /^\S+\@\S+>/) ||
-					    ($op eq '>' &&
-					     $ca =~ /<\S+\@\S+$/))
-					{
-						$ok = 1;
-					}
-
-					# Ignore ?:
-					if (($opv eq ':O' && $ca =~ /\?$/) ||
-					    ($op eq '?' && $cc =~ /^:/)) {
-						$ok = 1;
-					}
-
-					if ($ok == 0) {
-						ERROR("SPACING",
-						      "spaces required around that '$op' $at\n" . $hereptr);
-					}
-				}
-				$off += length($elements[$n + 1]);
-			}
-		}
-
-# check for multiple assignments
-		if ($line =~ /^.\s*$Lval\s*=\s*$Lval\s*=(?!=)/) {
-			CHK("MULTIPLE_ASSIGNMENTS",
-			    "multiple assignments should be avoided\n" . $herecurr);
-		}
-
-## # check for multiple declarations, allowing for a function declaration
-## # continuation.
-## 		if ($line =~ /^.\s*$Type\s+$Ident(?:\s*=[^,{]*)?\s*,\s*$Ident.*/ &&
-## 		    $line !~ /^.\s*$Type\s+$Ident(?:\s*=[^,{]*)?\s*,\s*$Type\s*$Ident.*/) {
-##
-## 			# Remove any bracketed sections to ensure we do not
-## 			# falsly report the parameters of functions.
-## 			my $ln = $line;
-## 			while ($ln =~ s/\([^\(\)]*\)//g) {
-## 			}
-## 			if ($ln =~ /,/) {
-## 				WARN("MULTIPLE_DECLARATION",
-##				     "declaring multiple variables together should be avoided\n" . $herecurr);
-## 			}
-## 		}
-
-#need space before brace following if, while, etc
-		if (($line =~ /\(.*\){/ && $line !~ /\($Type\){/) ||
-		    $line =~ /do{/) {
-			ERROR("SPACING",
-			      "space required before the open brace '{'\n" . $herecurr);
-		}
-
-# closing brace should have a space following it when it has anything
-# on the line
-		if ($line =~ /}(?!(?:,|;|\)))\S/) {
-			ERROR("SPACING",
-			      "space required after that close brace '}'\n" . $herecurr);
-		}
-
-# check spacing on square brackets
-		if ($line =~ /\[\s/ && $line !~ /\[\s*$/) {
-			ERROR("SPACING",
-			      "space prohibited after that open square bracket '['\n" . $herecurr);
-		}
-		if ($line =~ /\s\]/) {
-			ERROR("SPACING",
-			      "space prohibited before that close square bracket ']'\n" . $herecurr);
-		}
-
-# check spacing on parentheses
-		if ($line =~ /\(\s/ && $line !~ /\(\s*(?:\\)?$/ &&
-		    $line !~ /for\s*\(\s+;/) {
-			ERROR("SPACING",
-			      "space prohibited after that open parenthesis '('\n" . $herecurr);
-		}
-		if ($line =~ /(\s+)\)/ && $line !~ /^.\s*\)/ &&
-		    $line !~ /for\s*\(.*;\s+\)/ &&
-		    $line !~ /:\s+\)/) {
-			ERROR("SPACING",
-			      "space prohibited before that close parenthesis ')'\n" . $herecurr);
-		}
-
-#goto labels aren't indented, allow a single space however
-		if ($line=~/^.\s+[A-Za-z\d_]+:(?![0-9]+)/ and
-		   !($line=~/^. [A-Za-z\d_]+:/) and !($line=~/^.\s+default:/)) {
-			WARN("INDENTED_LABEL",
-			     "labels should not be indented\n" . $herecurr);
-		}
-
-# Return is not a function.
-		if (defined($stat) && $stat =~ /^.\s*return(\s*)(\(.*);/s) {
-			my $spacing = $1;
-			my $value = $2;
-
-			# Flatten any parentheses
-			$value =~ s/\(/ \(/g;
-			$value =~ s/\)/\) /g;
-			while ($value =~ s/\[[^\[\]]*\]/1/ ||
-			       $value !~ /(?:$Ident|-?$Constant)\s*
-					     $Compare\s*
-					     (?:$Ident|-?$Constant)/x &&
-			       $value =~ s/\([^\(\)]*\)/1/) {
-			}
-#print "value<$value>\n";
-			if ($value =~ /^\s*(?:$Ident|-?$Constant)\s*$/) {
-				ERROR("RETURN_PARENTHESES",
-				      "return is not a function, parentheses are not required\n" . $herecurr);
-
-			} elsif ($spacing !~ /\s+/) {
-				ERROR("SPACING",
-				      "space required before the open parenthesis '('\n" . $herecurr);
-			}
-		}
-# Return of what appears to be an errno should normally be -'ve
-		if ($line =~ /^.\s*return\s*(E[A-Z]*)\s*;/) {
-			my $name = $1;
-			if ($name ne 'EOF' && $name ne 'ERROR') {
-				WARN("USE_NEGATIVE_ERRNO",
-				     "return of an errno should typically be -ve (return -$1)\n" . $herecurr);
-			}
-		}
-
-# Need a space before open parenthesis after if, while etc
-		if ($line=~/\b(if|while|for|switch)\(/) {
-			ERROR("SPACING", "space required before the open parenthesis '('\n" . $herecurr);
-		}
-
-# Check for illegal assignment in if conditional -- and check for trailing
-# statements after the conditional.
-		if ($line =~ /do\s*(?!{)/) {
-			($stat, $cond, $line_nr_next, $remain_next, $off_next) =
-				ctx_statement_block($linenr, $realcnt, 0)
-					if (!defined $stat);
-			my ($stat_next) = ctx_statement_block($line_nr_next,
-						$remain_next, $off_next);
-			$stat_next =~ s/\n./\n /g;
-			##print "stat<$stat> stat_next<$stat_next>\n";
-
-			if ($stat_next =~ /^\s*while\b/) {
-				# If the statement carries leading newlines,
-				# then count those as offsets.
-				my ($whitespace) =
-					($stat_next =~ /^((?:\s*\n[+-])*\s*)/s);
-				my $offset =
-					statement_rawlines($whitespace) - 1;
-
-				$suppress_whiletrailers{$line_nr_next +
-								$offset} = 1;
-			}
-		}
-		if (!defined $suppress_whiletrailers{$linenr} &&
-		    $line =~ /\b(?:if|while|for)\s*\(/ && $line !~ /^.\s*#/) {
-			my ($s, $c) = ($stat, $cond);
-
-			if ($c =~ /\bif\s*\(.*[^<>!=]=[^=].*/s) {
-				ERROR("ASSIGN_IN_IF",
-				      "do not use assignment in if condition\n" . $herecurr);
-			}
-
-			# Find out what is on the end of the line after the
-			# conditional.
-			substr($s, 0, length($c), '');
-			$s =~ s/\n.*//g;
-			$s =~ s/$;//g; 	# Remove any comments
-			if (length($c) && $s !~ /^\s*{?\s*\\*\s*$/ &&
-			    $c !~ /}\s*while\s*/)
-			{
-				# Find out how long the conditional actually is.
-				my @newlines = ($c =~ /\n/gs);
-				my $cond_lines = 1 + $#newlines;
-				my $stat_real = '';
-
-				$stat_real = raw_line($linenr, $cond_lines)
-							. "\n" if ($cond_lines);
-				if (defined($stat_real) && $cond_lines > 1) {
-					$stat_real = "[...]\n$stat_real";
-				}
-
-				ERROR("TRAILING_STATEMENTS",
-				      "trailing statements should be on next line\n" . $herecurr . $stat_real);
-			}
-		}
-
-# Check for bitwise tests written as boolean
-		if ($line =~ /
-			(?:
-				(?:\[|\(|\&\&|\|\|)
-				\s*0[xX][0-9]+\s*
-				(?:\&\&|\|\|)
-			|
-				(?:\&\&|\|\|)
-				\s*0[xX][0-9]+\s*
-				(?:\&\&|\|\||\)|\])
-			)/x)
-		{
-			WARN("HEXADECIMAL_BOOLEAN_TEST",
-			     "boolean test with hexadecimal, perhaps just 1 \& or \|?\n" . $herecurr);
-		}
-
-# if and else should not have general statements after it
-		if ($line =~ /^.\s*(?:}\s*)?else\b(.*)/) {
-			my $s = $1;
-			$s =~ s/$;//g; 	# Remove any comments
-			if ($s !~ /^\s*(?:\sif|(?:{|)\s*\\?\s*$)/) {
-				ERROR("TRAILING_STATEMENTS",
-				      "trailing statements should be on next line\n" . $herecurr);
-			}
-		}
-# if should not continue a brace
-		if ($line =~ /}\s*if\b/) {
-			ERROR("TRAILING_STATEMENTS",
-			      "trailing statements should be on next line\n" .
-				$herecurr);
-		}
-# case and default should not have general statements after them
-		if ($line =~ /^.\s*(?:case\s*.*|default\s*):/g &&
-		    $line !~ /\G(?:
-			(?:\s*$;*)(?:\s*{)?(?:\s*$;*)(?:\s*\\)?\s*$|
-			\s*return\s+
-		    )/xg)
-		{
-			ERROR("TRAILING_STATEMENTS",
-			      "trailing statements should be on next line\n" . $herecurr);
-		}
-
-		# Check for }<nl>else {, these must be at the same
-		# indent level to be relevant to each other.
-		if ($prevline=~/}\s*$/ and $line=~/^.\s*else\s*/ and
-						$previndent == $indent) {
-			ERROR("ELSE_AFTER_BRACE",
-			      "else should follow close brace '}'\n" . $hereprev);
-		}
-
-		if ($prevline=~/}\s*$/ and $line=~/^.\s*while\s*/ and
-						$previndent == $indent) {
-			my ($s, $c) = ctx_statement_block($linenr, $realcnt, 0);
-
-			# Find out what is on the end of the line after the
-			# conditional.
-			substr($s, 0, length($c), '');
-			$s =~ s/\n.*//g;
-
-			if ($s =~ /^\s*;/) {
-				ERROR("WHILE_AFTER_BRACE",
-				      "while should follow close brace '}'\n" . $hereprev);
-			}
-		}
-
-#CamelCase
-		while ($line =~ m{($Constant|$Lval)}g) {
-			my $var = $1;
-			if ($var !~ /$Constant/ &&
-			    $var =~ /[A-Z]\w*[a-z]|[a-z]\w*[A-Z]/ &&
-			    $var !~ /"^(?:Clear|Set|TestClear|TestSet|)Page[A-Z]/ &&
-			    !defined $camelcase{$var}) {
-				$camelcase{$var} = 1;
-				WARN("CAMELCASE",
-				     "Avoid CamelCase: <$var>\n" . $herecurr);
-			}
-		}
-
-#no spaces allowed after \ in define
-		if ($line=~/\#\s*define.*\\\s$/) {
-			WARN("WHITESPACE_AFTER_LINE_CONTINUATION",
-			     "Whitepspace after \\ makes next lines useless\n" . $herecurr);
-		}
-
-#warn if <asm/foo.h> is #included and <linux/foo.h> is available (uses RAW line)
-		if ($tree && $rawline =~ m{^.\s*\#\s*include\s*\<asm\/(.*)\.h\>}) {
-			my $file = "$1.h";
-			my $checkfile = "include/linux/$file";
-			if (-f "$root/$checkfile" &&
-			    $realfile ne $checkfile &&
-			    $1 !~ /$allowed_asm_includes/)
-			{
-				if ($realfile =~ m{^arch/}) {
-					CHK("ARCH_INCLUDE_LINUX",
-					    "Consider using #include <linux/$file> instead of <asm/$file>\n" . $herecurr);
-				} else {
-					WARN("INCLUDE_LINUX",
-					     "Use #include <linux/$file> instead of <asm/$file>\n" . $herecurr);
-				}
-			}
-		}
-
-# multi-statement macros should be enclosed in a do while loop, grab the
-# first statement and ensure its the whole macro if its not enclosed
-# in a known good container
-		if ($realfile !~ m@/vmlinux.lds.h$@ &&
-		    $line =~ /^.\s*\#\s*define\s*$Ident(\()?/) {
-			my $ln = $linenr;
-			my $cnt = $realcnt;
-			my ($off, $dstat, $dcond, $rest);
-			my $ctx = '';
-			($dstat, $dcond, $ln, $cnt, $off) =
-				ctx_statement_block($linenr, $realcnt, 0);
-			$ctx = $dstat;
-			#print "dstat<$dstat> dcond<$dcond> cnt<$cnt> off<$off>\n";
-			#print "LINE<$lines[$ln-1]> len<" . length($lines[$ln-1]) . "\n";
-
-			$dstat =~ s/^.\s*\#\s*define\s+$Ident(?:\([^\)]*\))?\s*//;
-			$dstat =~ s/$;//g;
-			$dstat =~ s/\\\n.//g;
-			$dstat =~ s/^\s*//s;
-			$dstat =~ s/\s*$//s;
-
-			# Flatten any parentheses and braces
-			while ($dstat =~ s/\([^\(\)]*\)/1/ ||
-			       $dstat =~ s/\{[^\{\}]*\}/1/ ||
-			       $dstat =~ s/\[[^\[\]]*\]/1/)
-			{
-			}
-
-			# Flatten any obvious string concatentation.
-			while ($dstat =~ s/("X*")\s*$Ident/$1/ ||
-			       $dstat =~ s/$Ident\s*("X*")/$1/)
-			{
-			}
-
-			my $exceptions = qr{
-				$Declare|
-				module_param_named|
-				MODULE_PARM_DESC|
-				DECLARE_PER_CPU|
-				DEFINE_PER_CPU|
-				__typeof__\(|
-				union|
-				struct|
-				\.$Ident\s*=\s*|
-				^\"|\"$
-			}x;
-			#print "REST<$rest> dstat<$dstat> ctx<$ctx>\n";
-			if ($dstat ne '' &&
-			    $dstat !~ /^(?:$Ident|-?$Constant),$/ &&			# 10, // foo(),
-			    $dstat !~ /^(?:$Ident|-?$Constant);$/ &&			# foo();
-			    $dstat !~ /^[!~-]?(?:$Ident|$Constant)$/ &&		# 10 // foo() // !foo // ~foo // -foo
-			    $dstat !~ /^'X'$/ &&					# character constants
-			    $dstat !~ /$exceptions/ &&
-			    $dstat !~ /^\.$Ident\s*=/ &&				# .foo =
-			    $dstat !~ /^do\s*$Constant\s*while\s*$Constant;?$/ &&	# do {...} while (...); // do {...} while (...)
-			    $dstat !~ /^for\s*$Constant$/ &&				# for (...)
-			    $dstat !~ /^for\s*$Constant\s+(?:$Ident|-?$Constant)$/ &&	# for (...) bar()
-			    $dstat !~ /^do\s*{/ &&					# do {...
-			    $dstat !~ /^\({/)						# ({...
-			{
-				$ctx =~ s/\n*$//;
-				my $herectx = $here . "\n";
-				my $cnt = statement_rawlines($ctx);
-
-				for (my $n = 0; $n < $cnt; $n++) {
-					$herectx .= raw_line($linenr, $n) . "\n";
-				}
-
-				if ($dstat =~ /;/) {
-					ERROR("MULTISTATEMENT_MACRO_USE_DO_WHILE",
-					      "Macros with multiple statements should be enclosed in a do - while loop\n" . "$herectx");
-				} else {
-					ERROR("COMPLEX_MACRO",
-					      "Macros with complex values should be enclosed in parenthesis\n" . "$herectx");
-				}
-			}
-
-# check for line continuations outside of #defines, preprocessor #, and asm
-
-		} else {
-			if ($prevline !~ /^..*\\$/ &&
-			    $line !~ /^\+\s*\#.*\\$/ &&		# preprocessor
-			    $line !~ /^\+.*\b(__asm__|asm)\b.*\\$/ &&	# asm
-			    $line =~ /^\+.*\\$/) {
-				WARN("LINE_CONTINUATIONS",
-				     "Avoid unnecessary line continuations\n" . $herecurr);
-			}
-		}
-
-# do {} while (0) macro tests:
-# single-statement macros do not need to be enclosed in do while (0) loop,
-# macro should not end with a semicolon
-		if ($^V && $^V ge 5.10.0 &&
-		    $realfile !~ m@/vmlinux.lds.h$@ &&
-		    $line =~ /^.\s*\#\s*define\s+$Ident(\()?/) {
-			my $ln = $linenr;
-			my $cnt = $realcnt;
-			my ($off, $dstat, $dcond, $rest);
-			my $ctx = '';
-			($dstat, $dcond, $ln, $cnt, $off) =
-				ctx_statement_block($linenr, $realcnt, 0);
-			$ctx = $dstat;
-
-			$dstat =~ s/\\\n.//g;
-
-			if ($dstat =~ /^\+\s*#\s*define\s+$Ident\s*${balanced_parens}\s*do\s*{(.*)\s*}\s*while\s*\(\s*0\s*\)\s*([;\s]*)\s*$/) {
-				my $stmts = $2;
-				my $semis = $3;
-
-				$ctx =~ s/\n*$//;
-				my $cnt = statement_rawlines($ctx);
-				my $herectx = $here . "\n";
-
-				for (my $n = 0; $n < $cnt; $n++) {
-					$herectx .= raw_line($linenr, $n) . "\n";
-				}
-
-				if (($stmts =~ tr/;/;/) == 1 &&
-				    $stmts !~ /^\s*(if|while|for|switch)\b/) {
-					WARN("SINGLE_STATEMENT_DO_WHILE_MACRO",
-					     "Single statement macros should not use a do {} while (0) loop\n" . "$herectx");
-				}
-				if (defined $semis && $semis ne "") {
-					WARN("DO_WHILE_MACRO_WITH_TRAILING_SEMICOLON",
-					     "do {} while (0) macros should not be semicolon terminated\n" . "$herectx");
-				}
-			}
-		}
-
-# make sure symbols are always wrapped with VMLINUX_SYMBOL() ...
-# all assignments may have only one of the following with an assignment:
-#	.
-#	ALIGN(...)
-#	VMLINUX_SYMBOL(...)
-		if ($realfile eq 'vmlinux.lds.h' && $line =~ /(?:(?:^|\s)$Ident\s*=|=\s*$Ident(?:\s|$))/) {
-			WARN("MISSING_VMLINUX_SYMBOL",
-			     "vmlinux.lds.h needs VMLINUX_SYMBOL() around C-visible symbols\n" . $herecurr);
-		}
-
-# check for redundant bracing round if etc
-		if ($line =~ /(^.*)\bif\b/ && $1 !~ /else\s*$/) {
-			my ($level, $endln, @chunks) =
-				ctx_statement_full($linenr, $realcnt, 1);
-			#print "chunks<$#chunks> linenr<$linenr> endln<$endln> level<$level>\n";
-			#print "APW: <<$chunks[1][0]>><<$chunks[1][1]>>\n";
-			if ($#chunks > 0 && $level == 0) {
-				my @allowed = ();
-				my $allow = 0;
-				my $seen = 0;
-				my $herectx = $here . "\n";
-				my $ln = $linenr - 1;
-				for my $chunk (@chunks) {
-					my ($cond, $block) = @{$chunk};
-
-					# If the condition carries leading newlines, then count those as offsets.
-					my ($whitespace) = ($cond =~ /^((?:\s*\n[+-])*\s*)/s);
-					my $offset = statement_rawlines($whitespace) - 1;
-
-					$allowed[$allow] = 0;
-					#print "COND<$cond> whitespace<$whitespace> offset<$offset>\n";
-
-					# We have looked at and allowed this specific line.
-					$suppress_ifbraces{$ln + $offset} = 1;
-
-					$herectx .= "$rawlines[$ln + $offset]\n[...]\n";
-					$ln += statement_rawlines($block) - 1;
-
-					substr($block, 0, length($cond), '');
-
-					$seen++ if ($block =~ /^\s*{/);
-
-					#print "cond<$cond> block<$block> allowed<$allowed[$allow]>\n";
-					if (statement_lines($cond) > 1) {
-						#print "APW: ALLOWED: cond<$cond>\n";
-						$allowed[$allow] = 1;
-					}
-					if ($block =~/\b(?:if|for|while)\b/) {
-						#print "APW: ALLOWED: block<$block>\n";
-						$allowed[$allow] = 1;
-					}
-					if (statement_block_size($block) > 1) {
-						#print "APW: ALLOWED: lines block<$block>\n";
-						$allowed[$allow] = 1;
-					}
-					$allow++;
-				}
-				if ($seen) {
-					my $sum_allowed = 0;
-					foreach (@allowed) {
-						$sum_allowed += $_;
-					}
-					if ($sum_allowed == 0) {
-						WARN("BRACES",
-						     "braces {} are not necessary for any arm of this statement\n" . $herectx);
-					} elsif ($sum_allowed != $allow &&
-						 $seen != $allow) {
-						CHK("BRACES",
-						    "braces {} should be used on all arms of this statement\n" . $herectx);
-					}
-				}
-			}
-		}
-		if (!defined $suppress_ifbraces{$linenr - 1} &&
-					$line =~ /\b(if|while|for|else)\b/) {
-			my $allowed = 0;
-
-			# Check the pre-context.
-			if (substr($line, 0, $-[0]) =~ /(\}\s*)$/) {
-				#print "APW: ALLOWED: pre<$1>\n";
-				$allowed = 1;
-			}
-
-			my ($level, $endln, @chunks) =
-				ctx_statement_full($linenr, $realcnt, $-[0]);
-
-			# Check the condition.
-			my ($cond, $block) = @{$chunks[0]};
-			#print "CHECKING<$linenr> cond<$cond> block<$block>\n";
-			if (defined $cond) {
-				substr($block, 0, length($cond), '');
-			}
-			if (statement_lines($cond) > 1) {
-				#print "APW: ALLOWED: cond<$cond>\n";
-				$allowed = 1;
-			}
-			if ($block =~/\b(?:if|for|while)\b/) {
-				#print "APW: ALLOWED: block<$block>\n";
-				$allowed = 1;
-			}
-			if (statement_block_size($block) > 1) {
-				#print "APW: ALLOWED: lines block<$block>\n";
-				$allowed = 1;
-			}
-			# Check the post-context.
-			if (defined $chunks[1]) {
-				my ($cond, $block) = @{$chunks[1]};
-				if (defined $cond) {
-					substr($block, 0, length($cond), '');
-				}
-				if ($block =~ /^\s*\{/) {
-					#print "APW: ALLOWED: chunk-1 block<$block>\n";
-					$allowed = 1;
-				}
-			}
-			if ($level == 0 && $block =~ /^\s*\{/ && !$allowed) {
-				my $herectx = $here . "\n";
-				my $cnt = statement_rawlines($block);
-
-				for (my $n = 0; $n < $cnt; $n++) {
-					$herectx .= raw_line($linenr, $n) . "\n";
-				}
-
-				WARN("BRACES",
-				     "braces {} are not necessary for single statement blocks\n" . $herectx);
-			}
-		}
-
-# check for unnecessary blank lines around braces
-		if (($line =~ /^..*}\s*$/ && $prevline =~ /^.\s*$/)) {
-			CHK("BRACES",
-			    "Blank lines aren't necessary before a close brace '}'\n" . $hereprev);
-		}
-		if (($line =~ /^.\s*$/ && $prevline =~ /^..*{\s*$/)) {
-			CHK("BRACES",
-			    "Blank lines aren't necessary after an open brace '{'\n" . $hereprev);
-		}
-
-# no volatiles please
-		my $asm_volatile = qr{\b(__asm__|asm)\s+(__volatile__|volatile)\b};
-		if ($line =~ /\bvolatile\b/ && $line !~ /$asm_volatile/) {
-			WARN("VOLATILE",
-			     "Use of volatile is usually wrong: see Documentation/volatile-considered-harmful.txt\n" . $herecurr);
-		}
-
-# warn about #if 0
-		if ($line =~ /^.\s*\#\s*if\s+0\b/) {
-			CHK("REDUNDANT_CODE",
-			    "if this code is redundant consider removing it\n" .
-				$herecurr);
-		}
-
-# check for needless "if (<foo>) fn(<foo>)" uses
-		if ($prevline =~ /\bif\s*\(\s*($Lval)\s*\)/) {
-			my $expr = '\s*\(\s*' . quotemeta($1) . '\s*\)\s*;';
-			if ($line =~ /\b(kfree|usb_free_urb|debugfs_remove(?:_recursive)?)$expr/) {
-				WARN('NEEDLESS_IF',
-				     "$1(NULL) is safe this check is probably not required\n" . $hereprev);
-			}
-		}
-
-# prefer usleep_range over udelay
-		if ($line =~ /\budelay\s*\(\s*(\d+)\s*\)/) {
-			# ignore udelay's < 10, however
-			if (! ($1 < 10) ) {
-				CHK("USLEEP_RANGE",
-				    "usleep_range is preferred over udelay; see Documentation/timers/timers-howto.txt\n" . $line);
-			}
-		}
-
-# warn about unexpectedly long msleep's
-		if ($line =~ /\bmsleep\s*\((\d+)\);/) {
-			if ($1 < 20) {
-				WARN("MSLEEP",
-				     "msleep < 20ms can sleep for up to 20ms; see Documentation/timers/timers-howto.txt\n" . $line);
-			}
-		}
-
-# warn about #ifdefs in C files
-#		if ($line =~ /^.\s*\#\s*if(|n)def/ && ($realfile =~ /\.c$/)) {
-#			print "#ifdef in C files should be avoided\n";
-#			print "$herecurr";
-#			$clean = 0;
-#		}
-
-# warn about spacing in #ifdefs
-		if ($line =~ /^.\s*\#\s*(ifdef|ifndef|elif)\s\s+/) {
-			ERROR("SPACING",
-			      "exactly one space required after that #$1\n" . $herecurr);
-		}
-
-# check for spinlock_t definitions without a comment.
-		if ($line =~ /^.\s*(struct\s+mutex|spinlock_t)\s+\S+;/ ||
-		    $line =~ /^.\s*(DEFINE_MUTEX)\s*\(/) {
-			my $which = $1;
-			if (!ctx_has_comment($first_line, $linenr)) {
-				CHK("UNCOMMENTED_DEFINITION",
-				    "$1 definition without comment\n" . $herecurr);
-			}
-		}
-# check for memory barriers without a comment.
-		if ($line =~ /\b(mb|rmb|wmb|read_barrier_depends|smp_mb|smp_rmb|smp_wmb|smp_read_barrier_depends)\(/) {
-			if (!ctx_has_comment($first_line, $linenr)) {
-				CHK("MEMORY_BARRIER",
-				    "memory barrier without comment\n" . $herecurr);
-			}
-		}
-# check of hardware specific defines
-		if ($line =~ m@^.\s*\#\s*if.*\b(__i386__|__powerpc64__|__sun__|__s390x__)\b@ && $realfile !~ m@include/asm-@) {
-			CHK("ARCH_DEFINES",
-			    "architecture specific defines should be avoided\n" .  $herecurr);
-		}
-
-# Check that the storage class is at the beginning of a declaration
-		if ($line =~ /\b$Storage\b/ && $line !~ /^.\s*$Storage\b/) {
-			WARN("STORAGE_CLASS",
-			     "storage class should be at the beginning of the declaration\n" . $herecurr)
-		}
-
-# check the location of the inline attribute, that it is between
-# storage class and type.
-		if ($line =~ /\b$Type\s+$Inline\b/ ||
-		    $line =~ /\b$Inline\s+$Storage\b/) {
-			ERROR("INLINE_LOCATION",
-			      "inline keyword should sit between storage class and type\n" . $herecurr);
-		}
-
-# Check for __inline__ and __inline, prefer inline
-		if ($line =~ /\b(__inline__|__inline)\b/) {
-			WARN("INLINE",
-			     "plain inline is preferred over $1\n" . $herecurr);
-		}
-
-# Check for __attribute__ packed, prefer __packed
-		if ($line =~ /\b__attribute__\s*\(\s*\(.*\bpacked\b/) {
-			WARN("PREFER_PACKED",
-			     "__packed is preferred over __attribute__((packed))\n" . $herecurr);
-		}
-
-# Check for __attribute__ aligned, prefer __aligned
-		if ($line =~ /\b__attribute__\s*\(\s*\(.*aligned/) {
-			WARN("PREFER_ALIGNED",
-			     "__aligned(size) is preferred over __attribute__((aligned(size)))\n" . $herecurr);
-		}
-
-# Check for __attribute__ format(printf, prefer __printf
-		if ($line =~ /\b__attribute__\s*\(\s*\(\s*format\s*\(\s*printf/) {
-			WARN("PREFER_PRINTF",
-			     "__printf(string-index, first-to-check) is preferred over __attribute__((format(printf, string-index, first-to-check)))\n" . $herecurr);
-		}
-
-# Check for __attribute__ format(scanf, prefer __scanf
-		if ($line =~ /\b__attribute__\s*\(\s*\(\s*format\s*\(\s*scanf\b/) {
-			WARN("PREFER_SCANF",
-			     "__scanf(string-index, first-to-check) is preferred over __attribute__((format(scanf, string-index, first-to-check)))\n" . $herecurr);
-		}
-
-# check for sizeof(&)
-		if ($line =~ /\bsizeof\s*\(\s*\&/) {
-			WARN("SIZEOF_ADDRESS",
-			     "sizeof(& should be avoided\n" . $herecurr);
-		}
-
-# check for sizeof without parenthesis
-		if ($line =~ /\bsizeof\s+((?:\*\s*|)$Lval|$Type(?:\s+$Lval|))/) {
-			WARN("SIZEOF_PARENTHESIS",
-			     "sizeof $1 should be sizeof($1)\n" . $herecurr);
-		}
-
-# check for line continuations in quoted strings with odd counts of "
-		if ($rawline =~ /\\$/ && $rawline =~ tr/"/"/ % 2) {
-			WARN("LINE_CONTINUATIONS",
-			     "Avoid line continuations in quoted strings\n" . $herecurr);
-		}
-
-# check for struct spinlock declarations
-		if ($line =~ /^.\s*\bstruct\s+spinlock\s+\w+\s*;/) {
-			WARN("USE_SPINLOCK_T",
-			     "struct spinlock should be spinlock_t\n" . $herecurr);
-		}
-
-# Check for misused memsets
-		if ($^V && $^V ge 5.10.0 &&
-		    defined $stat &&
-		    $stat =~ /^\+(?:.*?)\bmemset\s*\(\s*$FuncArg\s*,\s*$FuncArg\s*\,\s*$FuncArg\s*\)/s) {
-
-			my $ms_addr = $2;
-			my $ms_val = $7;
-			my $ms_size = $12;
-
-			if ($ms_size =~ /^(0x|)0$/i) {
-				ERROR("MEMSET",
-				      "memset to 0's uses 0 as the 2nd argument, not the 3rd\n" . "$here\n$stat\n");
-			} elsif ($ms_size =~ /^(0x|)1$/i) {
-				WARN("MEMSET",
-				     "single byte memset is suspicious. Swapped 2nd/3rd argument?\n" . "$here\n$stat\n");
-			}
-		}
-
-# typecasts on min/max could be min_t/max_t
-		if ($^V && $^V ge 5.10.0 &&
-		    defined $stat &&
-		    $stat =~ /^\+(?:.*?)\b(min|max)\s*\(\s*$FuncArg\s*,\s*$FuncArg\s*\)/) {
-			if (defined $2 || defined $7) {
-				my $call = $1;
-				my $cast1 = deparenthesize($2);
-				my $arg1 = $3;
-				my $cast2 = deparenthesize($7);
-				my $arg2 = $8;
-				my $cast;
-
-				if ($cast1 ne "" && $cast2 ne "" && $cast1 ne $cast2) {
-					$cast = "$cast1 or $cast2";
-				} elsif ($cast1 ne "") {
-					$cast = $cast1;
-				} else {
-					$cast = $cast2;
-				}
-				WARN("MINMAX",
-				     "$call() should probably be ${call}_t($cast, $arg1, $arg2)\n" . "$here\n$stat\n");
-			}
-		}
-
-# check usleep_range arguments
-		if ($^V && $^V ge 5.10.0 &&
-		    defined $stat &&
-		    $stat =~ /^\+(?:.*?)\busleep_range\s*\(\s*($FuncArg)\s*,\s*($FuncArg)\s*\)/) {
-			my $min = $1;
-			my $max = $7;
-			if ($min eq $max) {
-				WARN("USLEEP_RANGE",
-				     "usleep_range should not use min == max args; see Documentation/timers/timers-howto.txt\n" . "$here\n$stat\n");
-			} elsif ($min =~ /^\d+$/ && $max =~ /^\d+$/ &&
-				 $min > $max) {
-				WARN("USLEEP_RANGE",
-				     "usleep_range args reversed, use min then max; see Documentation/timers/timers-howto.txt\n" . "$here\n$stat\n");
-			}
-		}
-
-# check for new externs in .c files.
-		if ($realfile =~ /\.c$/ && defined $stat &&
-		    $stat =~ /^.\s*(?:extern\s+)?$Type\s+($Ident)(\s*)\(/s)
-		{
-			my $function_name = $1;
-			my $paren_space = $2;
-
-			my $s = $stat;
-			if (defined $cond) {
-				substr($s, 0, length($cond), '');
-			}
-			if ($s =~ /^\s*;/ &&
-			    $function_name ne 'uninitialized_var')
-			{
-				WARN("AVOID_EXTERNS",
-				     "externs should be avoided in .c files\n" .  $herecurr);
-			}
-
-			if ($paren_space =~ /\n/) {
-				WARN("FUNCTION_ARGUMENTS",
-				     "arguments for function declarations should follow identifier\n" . $herecurr);
-			}
-
-		} elsif ($realfile =~ /\.c$/ && defined $stat &&
-		    $stat =~ /^.\s*extern\s+/)
-		{
-			WARN("AVOID_EXTERNS",
-			     "externs should be avoided in .c files\n" .  $herecurr);
-		}
-
-# checks for new __setup's
-		if ($rawline =~ /\b__setup\("([^"]*)"/) {
-			my $name = $1;
-
-			if (!grep(/$name/, @setup_docs)) {
-				CHK("UNDOCUMENTED_SETUP",
-				    "__setup appears un-documented -- check Documentation/kernel-parameters.txt\n" . $herecurr);
-			}
-		}
-
-# check for pointless casting of kmalloc return
-		if ($line =~ /\*\s*\)\s*[kv][czm]alloc(_node){0,1}\b/) {
-			WARN("UNNECESSARY_CASTS",
-			     "unnecessary cast may hide bugs, see http://c-faq.com/malloc/mallocnocast.html\n" . $herecurr);
-		}
-
-# check for alloc argument mismatch
-		if ($line =~ /\b(kcalloc|kmalloc_array)\s*\(\s*sizeof\b/) {
-			WARN("ALLOC_ARRAY_ARGS",
-			     "$1 uses number as first arg, sizeof is generally wrong\n" . $herecurr);
-		}
-
-# check for multiple semicolons
-		if ($line =~ /;\s*;\s*$/) {
-			WARN("ONE_SEMICOLON",
-			     "Statements terminations use 1 semicolon\n" . $herecurr);
-		}
-
-# check for switch/default statements without a break;
-		if ($^V && $^V ge 5.10.0 &&
-		    defined $stat &&
-		    $stat =~ /^\+[$;\s]*(?:case[$;\s]+\w+[$;\s]*:[$;\s]*|)*[$;\s]*\bdefault[$;\s]*:[$;\s]*;/g) {
-			my $ctx = '';
-			my $herectx = $here . "\n";
-			my $cnt = statement_rawlines($stat);
-			for (my $n = 0; $n < $cnt; $n++) {
-				$herectx .= raw_line($linenr, $n) . "\n";
-			}
-			WARN("DEFAULT_NO_BREAK",
-			     "switch default: should use break\n" . $herectx);
-		}
-
-# check for gcc specific __FUNCTION__
-		if ($line =~ /__FUNCTION__/) {
-			WARN("USE_FUNC",
-			     "__func__ should be used instead of gcc specific __FUNCTION__\n"  . $herecurr);
-		}
-
-# check for use of yield()
-		if ($line =~ /\byield\s*\(\s*\)/) {
-			WARN("YIELD",
-			     "Using yield() is generally wrong. See yield() kernel-doc (sched/core.c)\n"  . $herecurr);
-		}
-
-# check for semaphores initialized locked
-		if ($line =~ /^.\s*sema_init.+,\W?0\W?\)/) {
-			WARN("CONSIDER_COMPLETION",
-			     "consider using a completion\n" . $herecurr);
-		}
-
-# recommend kstrto* over simple_strto* and strict_strto*
-		if ($line =~ /\b((simple|strict)_(strto(l|ll|ul|ull)))\s*\(/) {
-			WARN("CONSIDER_KSTRTO",
-			     "$1 is obsolete, use k$3 instead\n" . $herecurr);
-		}
-
-# check for __initcall(), use device_initcall() explicitly please
-		if ($line =~ /^.\s*__initcall\s*\(/) {
-			WARN("USE_DEVICE_INITCALL",
-			     "please use device_initcall() instead of __initcall()\n" . $herecurr);
-		}
-
-# check for various ops structs, ensure they are const.
-		my $struct_ops = qr{acpi_dock_ops|
-				address_space_operations|
-				backlight_ops|
-				block_device_operations|
-				dentry_operations|
-				dev_pm_ops|
-				dma_map_ops|
-				extent_io_ops|
-				file_lock_operations|
-				file_operations|
-				hv_ops|
-				ide_dma_ops|
-				intel_dvo_dev_ops|
-				item_operations|
-				iwl_ops|
-				kgdb_arch|
-				kgdb_io|
-				kset_uevent_ops|
-				lock_manager_operations|
-				microcode_ops|
-				mtrr_ops|
-				neigh_ops|
-				nlmsvc_binding|
-				pci_raw_ops|
-				pipe_buf_operations|
-				platform_hibernation_ops|
-				platform_suspend_ops|
-				proto_ops|
-				rpc_pipe_ops|
-				seq_operations|
-				snd_ac97_build_ops|
-				soc_pcmcia_socket_ops|
-				stacktrace_ops|
-				sysfs_ops|
-				tty_operations|
-				usb_mon_operations|
-				wd_ops}x;
-		if ($line !~ /\bconst\b/ &&
-		    $line =~ /\bstruct\s+($struct_ops)\b/) {
-			WARN("CONST_STRUCT",
-			     "struct $1 should normally be const\n" .
-				$herecurr);
-		}
-
-# use of NR_CPUS is usually wrong
-# ignore definitions of NR_CPUS and usage to define arrays as likely right
-		if ($line =~ /\bNR_CPUS\b/ &&
-		    $line !~ /^.\s*\s*#\s*if\b.*\bNR_CPUS\b/ &&
-		    $line !~ /^.\s*\s*#\s*define\b.*\bNR_CPUS\b/ &&
-		    $line !~ /^.\s*$Declare\s.*\[[^\]]*NR_CPUS[^\]]*\]/ &&
-		    $line !~ /\[[^\]]*\.\.\.[^\]]*NR_CPUS[^\]]*\]/ &&
-		    $line !~ /\[[^\]]*NR_CPUS[^\]]*\.\.\.[^\]]*\]/)
-		{
-			WARN("NR_CPUS",
-			     "usage of NR_CPUS is often wrong - consider using cpu_possible(), num_possible_cpus(), for_each_possible_cpu(), etc\n" . $herecurr);
-		}
-
-# check for %L{u,d,i} in strings
-		my $string;
-		while ($line =~ /(?:^|")([X\t]*)(?:"|$)/g) {
-			$string = substr($rawline, $-[1], $+[1] - $-[1]);
-			$string =~ s/%%/__/g;
-			if ($string =~ /(?<!%)%L[udi]/) {
-				WARN("PRINTF_L",
-				     "\%Ld/%Lu are not-standard C, use %lld/%llu\n" . $herecurr);
-				last;
-			}
-		}
-
-# whine mightly about in_atomic
-		if ($line =~ /\bin_atomic\s*\(/) {
-			if ($realfile =~ m@^drivers/@) {
-				ERROR("IN_ATOMIC",
-				      "do not use in_atomic in drivers\n" . $herecurr);
-			} elsif ($realfile !~ m@^kernel/@) {
-				WARN("IN_ATOMIC",
-				     "use of in_atomic() is incorrect outside core kernel code\n" . $herecurr);
-			}
-		}
-
-# check for lockdep_set_novalidate_class
-		if ($line =~ /^.\s*lockdep_set_novalidate_class\s*\(/ ||
-		    $line =~ /__lockdep_no_validate__\s*\)/ ) {
-			if ($realfile !~ m@^kernel/lockdep@ &&
-			    $realfile !~ m@^include/linux/lockdep@ &&
-			    $realfile !~ m@^drivers/base/core@) {
-				ERROR("LOCKDEP",
-				      "lockdep_no_validate class is reserved for device->mutex.\n" . $herecurr);
-			}
-		}
-
-		if ($line =~ /debugfs_create_file.*S_IWUGO/ ||
-		    $line =~ /DEVICE_ATTR.*S_IWUGO/ ) {
-			WARN("EXPORTED_WORLD_WRITABLE",
-			     "Exporting world writable files is usually an error. Consider more restrictive permissions.\n" . $herecurr);
-		}
-	}
-
-	# If we have no input at all, then there is nothing to report on
-	# so just keep quiet.
-	if ($#rawlines == -1) {
-		exit(0);
-	}
-
-	# In mailback mode only produce a report in the negative, for
-	# things that appear to be patches.
-	if ($mailback && ($clean == 1 || !$is_patch)) {
-		exit(0);
-	}
-
-	# This is not a patch, and we are are in 'no-patch' mode so
-	# just keep quiet.
-	if (!$chk_patch && !$is_patch) {
-		exit(0);
-	}
-
-	if (!$is_patch) {
-		ERROR("NOT_UNIFIED_DIFF",
-		      "Does not appear to be a unified-diff format patch\n");
-	}
-	if ($is_patch && $chk_signoff && $signoff == 0) {
-		ERROR("MISSING_SIGN_OFF",
-		      "Missing Signed-off-by: line(s)\n");
-	}
-
-	print report_dump();
-	if ($summary && !($clean == 1 && $quiet == 1)) {
-		print "$filename " if ($summary_file);
-		print "total: $cnt_error errors, $cnt_warn warnings, " .
-			(($check)? "$cnt_chk checks, " : "") .
-			"$cnt_lines lines checked\n";
-		print "\n" if ($quiet == 0);
-	}
-
-	if ($quiet == 0) {
-
-		if ($^V lt 5.10.0) {
-			print("NOTE: perl $^V is not modern enough to detect all possible issues.\n");
-			print("An upgrade to at least perl v5.10.0 is suggested.\n\n");
-		}
-
-		# If there were whitespace errors which cleanpatch can fix
-		# then suggest that.
-		if ($rpt_cleaners) {
-			print "NOTE: whitespace errors detected, you may wish to use scripts/cleanpatch or\n";
-			print "      scripts/cleanfile\n\n";
-			$rpt_cleaners = 0;
-		}
-	}
-
-	if ($quiet == 0 && keys %ignore_type) {
-	    print "NOTE: Ignored message types:";
-	    foreach my $ignore (sort keys %ignore_type) {
-		print " $ignore";
-	    }
-	    print "\n\n";
-	}
-
-	if ($clean == 1 && $quiet == 0) {
-		print "$vname has no obvious style problems and is ready for submission.\n"
-	}
-	if ($clean == 0 && $quiet == 0) {
-		print << "EOM";
-$vname has style problems, please review.
-
-If any of these errors are false positives, please report
-them to the maintainer, see boards.cfg.
-EOM
-	}
-
-	return $clean;
-}
diff --git a/tools/crc32.c b/tools/crc32.c
new file mode 100644
index 0000000000..aed7112f6a
--- /dev/null
+++ b/tools/crc32.c
@@ -0,0 +1 @@
+#include "../lib/crc32.c"
diff --git a/tools/default_image.c b/tools/default_image.c
index fd8b9f5f15..0a0792e503 100644
--- a/tools/default_image.c
+++ b/tools/default_image.c
@@ -14,7 +14,7 @@
  * SPDX-License-Identifier:	GPL-2.0+
  */
 
-#include "mkimage.h"
+#include "imagetool.h"
 #include <image.h>
 #include <u-boot/crc.h>
 
@@ -29,7 +29,7 @@ static int image_check_image_types(uint8_t type)
 		return EXIT_FAILURE;
 }
 
-static int image_check_params(struct mkimage_params *params)
+static int image_check_params(struct image_tool_params *params)
 {
 	return	((params->dflag && (params->fflag || params->lflag)) ||
 		(params->fflag && (params->dflag || params->lflag)) ||
@@ -37,7 +37,7 @@ static int image_check_params(struct mkimage_params *params)
 }
 
 static int image_verify_header(unsigned char *ptr, int image_size,
-			struct mkimage_params *params)
+			struct image_tool_params *params)
 {
 	uint32_t len;
 	const unsigned char *data;
@@ -86,7 +86,7 @@ static int image_verify_header(unsigned char *ptr, int image_size,
 }
 
 static void image_set_header(void *ptr, struct stat *sbuf, int ifd,
-				struct mkimage_params *params)
+				struct image_tool_params *params)
 {
 	uint32_t checksum;
 
@@ -117,6 +117,62 @@ static void image_set_header(void *ptr, struct stat *sbuf, int ifd,
 	image_set_hcrc(hdr, checksum);
 }
 
+static int image_save_datafile(struct image_tool_params *params,
+			       ulong file_data, ulong file_len)
+{
+	int dfd;
+	const char *datafile = params->outfile;
+
+	dfd = open(datafile, O_RDWR | O_CREAT | O_TRUNC | O_BINARY,
+		   S_IRUSR | S_IWUSR);
+	if (dfd < 0) {
+		fprintf(stderr, "%s: Can't open \"%s\": %s\n",
+			params->cmdname, datafile, strerror(errno));
+		return -1;
+	}
+
+	if (write(dfd, (void *)file_data, file_len) != (ssize_t)file_len) {
+		fprintf(stderr, "%s: Write error on \"%s\": %s\n",
+			params->cmdname, datafile, strerror(errno));
+		close(dfd);
+		return -1;
+	}
+
+	close(dfd);
+
+	return 0;
+}
+
+static int image_extract_datafile(void *ptr, struct image_tool_params *params)
+{
+	const image_header_t *hdr = (const image_header_t *)ptr;
+	ulong file_data;
+	ulong file_len;
+
+	if (image_check_type(hdr, IH_TYPE_MULTI)) {
+		ulong idx = params->pflag;
+		ulong count;
+
+		/* get the number of data files present in the image */
+		count = image_multi_count(hdr);
+
+		/* retrieve the "data file" at the idx position */
+		image_multi_getimg(hdr, idx, &file_data, &file_len);
+
+		if ((file_len == 0) || (idx >= count)) {
+			fprintf(stderr, "%s: No such data file %ld in \"%s\"\n",
+				params->cmdname, idx, params->imagefile);
+			return -1;
+		}
+	} else {
+		file_data = image_get_data(hdr);
+		file_len = image_get_size(hdr);
+	}
+
+	/* save the "data file" into the file system */
+	return image_save_datafile(params, file_data, file_len);
+}
+
 /*
  * Default image type parameters definition
  */
@@ -128,10 +184,11 @@ static struct image_type_params defimage_params = {
 	.verify_header = image_verify_header,
 	.print_header = image_print_contents,
 	.set_header = image_set_header,
+	.extract_datafile = image_extract_datafile,
 	.check_params = image_check_params,
 };
 
 void init_default_image_type(void)
 {
-	mkimage_register(&defimage_params);
+	register_image_type(&defimage_params);
 }
diff --git a/tools/dumpimage.c b/tools/dumpimage.c
new file mode 100644
index 0000000000..542ee28210
--- /dev/null
+++ b/tools/dumpimage.c
@@ -0,0 +1,305 @@
+/*
+ * Based on mkimage.c.
+ *
+ * Written by Guilherme Maciel Ferreira <guilherme.maciel.ferreira@gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include "dumpimage.h"
+#include <image.h>
+#include <version.h>
+
+static void usage(void);
+
+/* image_type_params linked list to maintain registered image types supports */
+static struct image_type_params *dumpimage_tparams;
+
+/* parameters initialized by core will be used by the image type code */
+static struct image_tool_params params = {
+	.type = IH_TYPE_KERNEL,
+};
+
+/**
+ * dumpimage_register() - register respective image generation/list support
+ *
+ * the input struct image_type_params is checked and appended to the link
+ * list, if the input structure is already registered, issue an error
+ *
+ * @tparams: Image type parameters
+ */
+static void dumpimage_register(struct image_type_params *tparams)
+{
+	struct image_type_params **tp;
+
+	if (!tparams) {
+		fprintf(stderr, "%s: %s: Null input\n", params.cmdname,
+			__func__);
+		exit(EXIT_FAILURE);
+	}
+
+	/* scan the linked list, check for registry and point the last one */
+	for (tp = &dumpimage_tparams; *tp != NULL; tp = &(*tp)->next) {
+		if (!strcmp((*tp)->name, tparams->name)) {
+			fprintf(stderr, "%s: %s already registered\n",
+				params.cmdname, tparams->name);
+			return;
+		}
+	}
+
+	/* add input struct entry at the end of link list */
+	*tp = tparams;
+	/* mark input entry as last entry in the link list */
+	tparams->next = NULL;
+
+	debug("Registered %s\n", tparams->name);
+}
+
+/**
+ * dumpimage_get_type() - find the image type params for a given image type
+ *
+ * Scan all registered image types and check the input type_id for each
+ * supported image type
+ *
+ * @return respective image_type_params pointer. If the input type is not
+ * supported by any of registered image types, returns NULL
+ */
+static struct image_type_params *dumpimage_get_type(int type)
+{
+	struct image_type_params *curr;
+
+	for (curr = dumpimage_tparams; curr != NULL; curr = curr->next) {
+		if (curr->check_image_type) {
+			if (!curr->check_image_type(type))
+				return curr;
+		}
+	}
+	return NULL;
+}
+
+/*
+ * dumpimage_verify_print_header() - verifies the image header
+ *
+ * Scan registered image types and verify the image_header for each
+ * supported image type. If verification is successful, this prints
+ * the respective header.
+ *
+ * @return 0 on success, negative if input image format does not match with
+ * any of supported image types
+ */
+static int dumpimage_verify_print_header(void *ptr, struct stat *sbuf)
+{
+	int retval = -1;
+	struct image_type_params *curr;
+
+	for (curr = dumpimage_tparams; curr != NULL; curr = curr->next) {
+		if (curr->verify_header) {
+			retval = curr->verify_header((unsigned char *)ptr,
+						     sbuf->st_size, &params);
+			if (retval != 0)
+				continue;
+			/*
+			 * Print the image information  if verify is
+			 * successful
+			 */
+			if (curr->print_header) {
+				curr->print_header(ptr);
+			} else {
+				fprintf(stderr,
+					"%s: print_header undefined for %s\n",
+					params.cmdname, curr->name);
+			}
+			break;
+		}
+	}
+
+	return retval;
+}
+
+/*
+ * dumpimage_extract_datafile -
+ *
+ * It scans all registered image types,
+ * verifies image_header for each supported image type
+ * if verification is successful, it extracts the desired file,
+ * indexed by pflag, from the image
+ *
+ * returns negative if input image format does not match with any of
+ * supported image types
+ */
+static int dumpimage_extract_datafile(void *ptr, struct stat *sbuf)
+{
+	int retval = -1;
+	struct image_type_params *curr;
+
+	for (curr = dumpimage_tparams; curr != NULL; curr = curr->next) {
+		if (curr->verify_header) {
+			retval = curr->verify_header((unsigned char *)ptr,
+						     sbuf->st_size, &params);
+			if (retval != 0)
+				continue;
+			/*
+			 * Extract the file from the image
+			 * if verify is successful
+			 */
+			if (curr->extract_datafile) {
+				curr->extract_datafile(ptr, &params);
+			} else {
+				fprintf(stderr,
+					"%s: extract_datafile undefined for %s\n",
+					params.cmdname, curr->name);
+			break;
+			}
+		}
+	}
+
+	return retval;
+}
+
+int main(int argc, char **argv)
+{
+	int opt;
+	int ifd = -1;
+	struct stat sbuf;
+	char *ptr;
+	int retval = 0;
+	struct image_type_params *tparams = NULL;
+
+	/* Init all image generation/list support */
+	register_image_tool(dumpimage_register);
+
+	params.cmdname = *argv;
+
+	while ((opt = getopt(argc, argv, "li:o:p:V")) != -1) {
+		switch (opt) {
+		case 'l':
+			params.lflag = 1;
+			break;
+		case 'i':
+			params.imagefile = optarg;
+			params.iflag = 1;
+			break;
+		case 'o':
+			params.outfile = optarg;
+			break;
+		case 'p':
+			params.pflag = strtoul(optarg, &ptr, 10);
+			if (*ptr) {
+				fprintf(stderr,
+					"%s: invalid file position %s\n",
+					params.cmdname, *argv);
+				exit(EXIT_FAILURE);
+			}
+			break;
+		case 'V':
+			printf("dumpimage version %s\n", PLAIN_VERSION);
+			exit(EXIT_SUCCESS);
+		default:
+			usage();
+		}
+	}
+
+	if (optind >= argc)
+		usage();
+
+	/* set tparams as per input type_id */
+	tparams = dumpimage_get_type(params.type);
+	if (tparams == NULL) {
+		fprintf(stderr, "%s: unsupported type %s\n",
+			params.cmdname, genimg_get_type_name(params.type));
+		exit(EXIT_FAILURE);
+	}
+
+	/*
+	 * check the passed arguments parameters meets the requirements
+	 * as per image type to be generated/listed
+	 */
+	if (tparams->check_params) {
+		if (tparams->check_params(&params))
+			usage();
+	}
+
+	if (params.iflag)
+		params.datafile = argv[optind];
+	else
+		params.imagefile = argv[optind];
+	if (!params.outfile)
+		params.outfile = params.datafile;
+
+	ifd = open(params.imagefile, O_RDONLY|O_BINARY);
+	if (ifd < 0) {
+		fprintf(stderr, "%s: Can't open \"%s\": %s\n",
+			params.cmdname, params.imagefile,
+			strerror(errno));
+		exit(EXIT_FAILURE);
+	}
+
+	if (params.lflag || params.iflag) {
+		if (fstat(ifd, &sbuf) < 0) {
+			fprintf(stderr, "%s: Can't stat \"%s\": %s\n",
+				params.cmdname, params.imagefile,
+				strerror(errno));
+			exit(EXIT_FAILURE);
+		}
+
+		if ((unsigned)sbuf.st_size < tparams->header_size) {
+			fprintf(stderr,
+				"%s: Bad size: \"%s\" is not valid image\n",
+				params.cmdname, params.imagefile);
+			exit(EXIT_FAILURE);
+		}
+
+		ptr = mmap(0, sbuf.st_size, PROT_READ, MAP_SHARED, ifd, 0);
+		if (ptr == MAP_FAILED) {
+			fprintf(stderr, "%s: Can't read \"%s\": %s\n",
+				params.cmdname, params.imagefile,
+				strerror(errno));
+			exit(EXIT_FAILURE);
+		}
+
+		/*
+		 * Both calls bellow scan through dumpimage registry for all
+		 * supported image types and verify the input image file
+		 * header for match
+		 */
+		if (params.iflag) {
+			/*
+			 * Extract the data files from within the matched
+			 * image type. Returns the error code if not matched
+			 */
+			retval = dumpimage_extract_datafile(ptr, &sbuf);
+		} else {
+			/*
+			 * Print the image information for matched image type
+			 * Returns the error code if not matched
+			 */
+			retval = dumpimage_verify_print_header(ptr, &sbuf);
+		}
+
+		(void)munmap((void *)ptr, sbuf.st_size);
+		(void)close(ifd);
+
+		return retval;
+	}
+
+	(void)close(ifd);
+
+	return EXIT_SUCCESS;
+}
+
+static void usage(void)
+{
+	fprintf(stderr, "Usage: %s -l image\n"
+		"          -l ==> list image header information\n",
+		params.cmdname);
+	fprintf(stderr,
+		"       %s -i image [-p position] [-o outfile] data_file\n"
+		"          -i ==> extract from the 'image' a specific 'data_file'"
+		", indexed by 'position' (starting at 0)\n",
+		params.cmdname);
+	fprintf(stderr,
+		"       %s -V ==> print version information and exit\n",
+		params.cmdname);
+
+	exit(EXIT_FAILURE);
+}
diff --git a/tools/dumpimage.h b/tools/dumpimage.h
new file mode 100644
index 0000000000..d78523ded7
--- /dev/null
+++ b/tools/dumpimage.h
@@ -0,0 +1,33 @@
+/*
+ * Based on mkimage.c.
+ *
+ * Written by Guilherme Maciel Ferreira <guilherme.maciel.ferreira@gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _DUMPIMAGE_H_
+#define _DUMPIMAGE_H_
+
+#include "os_support.h"
+#include <errno.h>
+#include <fcntl.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+#include <sys/stat.h>
+#include <time.h>
+#include <unistd.h>
+#include <sha1.h>
+#include "fdt_host.h"
+#include "imagetool.h"
+
+#undef DUMPIMAGE_DEBUG
+
+#ifdef DUMPIMAGE_DEBUG
+#define debug(fmt, args...)	printf(fmt, ##args)
+#else
+#define debug(fmt, args...)
+#endif /* DUMPIMAGE_DEBUG */
+
+#endif /* _DUMPIMAGE_H_ */
diff --git a/tools/easylogo/Makefile b/tools/easylogo/Makefile
index d8e28b0e12..10aba2ba66 100644
--- a/tools/easylogo/Makefile
+++ b/tools/easylogo/Makefile
@@ -1,11 +1,3 @@
-include $(TOPDIR)/config.mk
+hostprogs-y := easylogo
 
-all: $(obj)easylogo
-
-$(obj)easylogo: $(SRCTREE)/tools/easylogo/easylogo.c
-	$(HOSTCC) $(HOSTCFLAGS_NOPED) $(HOSTLDFLAGS) -o $@ $^
-
-clean:
-	rm -f $(obj)easylogo
-
-.PHONY: all clean
+always := $(hostprogs-y)
diff --git a/tools/env/.gitignore b/tools/env/.gitignore
new file mode 100644
index 0000000000..804abacc6e
--- /dev/null
+++ b/tools/env/.gitignore
@@ -0,0 +1,2 @@
+fw_printenv
+fw_printenv_unstripped
diff --git a/tools/env/Makefile b/tools/env/Makefile
index 14d131b7b8..fcb752ddb4 100644
--- a/tools/env/Makefile
+++ b/tools/env/Makefile
@@ -5,39 +5,30 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-HOSTSRCS := $(SRCTREE)/lib/crc32.c  fw_env.c  fw_env_main.c
-HOSTSRCS += $(SRCTREE)/lib/ctype.c $(SRCTREE)/lib/linux_string.c
-HOSTSRCS += $(SRCTREE)/common/env_attr.c $(SRCTREE)/common/env_flags.c
-HEADERS	:= fw_env.h $(OBJTREE)/include/config.h
+# fw_printenv is supposed to run on the target system, which means it should be
+# built with cross tools. Although it may look weird, we only replace "HOSTCC"
+# with "CC" here for the maximum code reuse of scripts/Makefile.host.
+HOSTCC = $(CC)
 
 # Compile for a hosted environment on the target
-HOSTCPPFLAGS  = -idirafter $(SRCTREE)/include \
-		-idirafter $(OBJTREE)/include2 \
-		-idirafter $(OBJTREE)/include \
-		-idirafter $(SRCTREE)/tools/env \
+HOST_EXTRACFLAGS  = $(patsubst -I%,-idirafter%, $(UBOOTINCLUDE)) \
+		-idirafter $(srctree)/tools/env \
 		-DUSE_HOSTCC \
 		-DTEXT_BASE=$(TEXT_BASE)
 
 ifeq ($(MTD_VERSION),old)
-HOSTCPPFLAGS += -DMTD_OLD
+HOST_EXTRACFLAGS += -DMTD_OLD
 endif
 
-all:	$(obj)fw_printenv
-
-# Some files complain if compiled with -pedantic, use HOSTCFLAGS_NOPED
-$(obj)fw_printenv:	$(HOSTSRCS) $(HEADERS)
-	$(HOSTCC) $(HOSTCFLAGS_NOPED) $(HOSTLDFLAGS) -o $@ $(HOSTSRCS)
-	$(HOSTSTRIP) $@
-
-clean:
-	rm -f $(obj)fw_printenv
-
-#########################################################################
+always := fw_printenv
+hostprogs-y := fw_printenv_unstripped
 
-include $(TOPDIR)/rules.mk
+fw_printenv_unstripped-objs := fw_env.o fw_env_main.o \
+	crc32.o ctype.o linux_string.o \
+	env_attr.o env_flags.o
 
-sinclude $(obj).depend
+quiet_cmd_strip = STRIP   $@
+      cmd_strip = $(STRIP) -o $@ $<
 
-#########################################################################
+$(obj)/fw_printenv: $(obj)/fw_printenv_unstripped FORCE
+	$(call if_changed,strip)
diff --git a/tools/env/README b/tools/env/README
index 1020b57b05..24e31bc9f8 100644
--- a/tools/env/README
+++ b/tools/env/README
@@ -2,11 +2,10 @@
 This is a demo implementation of a Linux command line tool to access
 the U-Boot's environment variables.
 
-In the current version, there is an issue in cross-compilation.
 In order to cross-compile fw_printenv, run
-    make HOSTCC=<your CC cross-compiler> env
+    make CROSS_COMPILE=<your cross-compiler prefix> env
 in the root directory of the U-Boot distribution. For example,
-    make HOSTCC=arm-linux-gcc env
+    make CROSS_COMPILE=arm-linux- env
 
 For the run-time utility configuration uncomment the line
 #define CONFIG_FILE  "/etc/fw_env.config"
diff --git a/tools/env/crc32.c b/tools/env/crc32.c
new file mode 100644
index 0000000000..34f8178e33
--- /dev/null
+++ b/tools/env/crc32.c
@@ -0,0 +1 @@
+#include "../../lib/crc32.c"
diff --git a/tools/env/ctype.c b/tools/env/ctype.c
new file mode 100644
index 0000000000..21050e9373
--- /dev/null
+++ b/tools/env/ctype.c
@@ -0,0 +1 @@
+#include "../../lib/ctype.c"
diff --git a/tools/env/env_attr.c b/tools/env/env_attr.c
new file mode 100644
index 0000000000..502d4c900b
--- /dev/null
+++ b/tools/env/env_attr.c
@@ -0,0 +1 @@
+#include "../../common/env_attr.c"
diff --git a/tools/env/env_flags.c b/tools/env/env_flags.c
new file mode 100644
index 0000000000..b261cb8e39
--- /dev/null
+++ b/tools/env/env_flags.c
@@ -0,0 +1 @@
+#include "../../common/env_flags.c"
diff --git a/tools/env/fw_env.c b/tools/env/fw_env.c
index 577ce2de47..d228cc34da 100644
--- a/tools/env/fw_env.c
+++ b/tools/env/fw_env.c
@@ -863,9 +863,9 @@ static int flash_write_buf (int dev, int fd, void *buf, size_t count,
 		if (mtd_type != MTD_ABSENT)
 			ioctl(fd, MEMLOCK, &erase);
 
-		processed  += blocklen;
+		processed  += erasesize;
 		block_seek = 0;
-		blockstart += blocklen;
+		blockstart += erasesize;
 	}
 
 	if (write_total > count)
@@ -1246,9 +1246,10 @@ static int parse_config ()
 	strcpy (DEVNAME (0), DEVICE1_NAME);
 	DEVOFFSET (0) = DEVICE1_OFFSET;
 	ENVSIZE (0) = ENV1_SIZE;
-	/* Default values are: erase-size=env-size, #sectors=1 */
+	/* Default values are: erase-size=env-size */
 	DEVESIZE (0) = ENVSIZE (0);
-	ENVSECTORS (0) = 1;
+	/* #sectors=env-size/erase-size (rounded up) */
+	ENVSECTORS (0) = (ENVSIZE(0) + DEVESIZE(0) - 1) / DEVESIZE(0);
 #ifdef DEVICE1_ESIZE
 	DEVESIZE (0) = DEVICE1_ESIZE;
 #endif
@@ -1260,9 +1261,10 @@ static int parse_config ()
 	strcpy (DEVNAME (1), DEVICE2_NAME);
 	DEVOFFSET (1) = DEVICE2_OFFSET;
 	ENVSIZE (1) = ENV2_SIZE;
-	/* Default values are: erase-size=env-size, #sectors=1 */
+	/* Default values are: erase-size=env-size */
 	DEVESIZE (1) = ENVSIZE (1);
-	ENVSECTORS (1) = 1;
+	/* #sectors=env-size/erase-size (rounded up) */
+	ENVSECTORS (1) = (ENVSIZE(1) + DEVESIZE(1) - 1) / DEVESIZE(1);
 #ifdef DEVICE2_ESIZE
 	DEVESIZE (1) = DEVICE2_ESIZE;
 #endif
@@ -1320,8 +1322,8 @@ static int get_config (char *fname)
 			DEVESIZE(i) = ENVSIZE(i);
 
 		if (rc < 5)
-			/* Default - 1 sector */
-			ENVSECTORS (i) = 1;
+			/* Assume enough env sectors to cover the environment */
+			ENVSECTORS (i) = (ENVSIZE(i) + DEVESIZE(i) - 1) / DEVESIZE(i);
 
 		i++;
 	}
diff --git a/tools/env/fw_env.config b/tools/env/fw_env.config
index 90e499da1e..c9b9f6a160 100644
--- a/tools/env/fw_env.config
+++ b/tools/env/fw_env.config
@@ -1,7 +1,7 @@
 # Configuration file for fw_(printenv/setenv) utility.
 # Up to two entries are valid, in this case the redundant
 # environment sector is assumed present.
-# Notice, that the "Number of sectors" is ignored on NOR and SPI-dataflash.
+# Notice, that the "Number of sectors" is not required on NOR and SPI-dataflash.
 # Futhermore, if the Flash sector size is ommitted, this value is assumed to
 # be the same as the Environment size, which is valid for NOR and SPI-dataflash
 
diff --git a/tools/env/linux_string.c b/tools/env/linux_string.c
new file mode 100644
index 0000000000..6c01addadf
--- /dev/null
+++ b/tools/env/linux_string.c
@@ -0,0 +1 @@
+#include "../../lib/linux_string.c"
diff --git a/tools/env_embedded.c b/tools/env_embedded.c
new file mode 100644
index 0000000000..59a6357195
--- /dev/null
+++ b/tools/env_embedded.c
@@ -0,0 +1 @@
+#include "../common/env_embedded.c"
diff --git a/tools/fdt.c b/tools/fdt.c
new file mode 100644
index 0000000000..1eafc56d76
--- /dev/null
+++ b/tools/fdt.c
@@ -0,0 +1 @@
+#include "../lib/libfdt/fdt.c"
diff --git a/tools/fdt_ro.c b/tools/fdt_ro.c
new file mode 100644
index 0000000000..9005fe3ca3
--- /dev/null
+++ b/tools/fdt_ro.c
@@ -0,0 +1 @@
+#include "../lib/libfdt/fdt_ro.c"
diff --git a/tools/fdt_rw.c b/tools/fdt_rw.c
new file mode 100644
index 0000000000..adc3fdfbea
--- /dev/null
+++ b/tools/fdt_rw.c
@@ -0,0 +1 @@
+#include "../lib/libfdt/fdt_rw.c"
diff --git a/tools/fdt_strerror.c b/tools/fdt_strerror.c
new file mode 100644
index 0000000000..d0b58220a4
--- /dev/null
+++ b/tools/fdt_strerror.c
@@ -0,0 +1 @@
+#include "../lib/libfdt/fdt_strerror.c"
diff --git a/tools/fdt_wip.c b/tools/fdt_wip.c
new file mode 100644
index 0000000000..7810f07079
--- /dev/null
+++ b/tools/fdt_wip.c
@@ -0,0 +1 @@
+#include "../lib/libfdt/fdt_wip.c"
diff --git a/tools/fit_image.c b/tools/fit_image.c
index 0400a60678..1466164f0a 100644
--- a/tools/fit_image.c
+++ b/tools/fit_image.c
@@ -14,6 +14,7 @@
  * SPDX-License-Identifier:	GPL-2.0+
  */
 
+#include "imagetool.h"
 #include "mkimage.h"
 #include <image.h>
 #include <u-boot/crc.h>
@@ -21,7 +22,7 @@
 static image_header_t header;
 
 static int fit_verify_header (unsigned char *ptr, int image_size,
-			struct mkimage_params *params)
+			struct image_tool_params *params)
 {
 	return fdt_check_header(ptr);
 }
@@ -34,7 +35,7 @@ static int fit_check_image_types (uint8_t type)
 		return EXIT_FAILURE;
 }
 
-int mmap_fdt(struct mkimage_params *params, const char *fname, void **blobp,
+int mmap_fdt(struct image_tool_params *params, const char *fname, void **blobp,
 		struct stat *sbuf)
 {
 	void *ptr;
@@ -88,7 +89,7 @@ int mmap_fdt(struct mkimage_params *params, const char *fname, void **blobp,
  * returns:
  *     only on success, otherwise calls exit (EXIT_FAILURE);
  */
-static int fit_handle_file (struct mkimage_params *params)
+static int fit_handle_file(struct image_tool_params *params)
 {
 	char tmpfile[MKIMAGE_MAX_TMPFILE_LEN];
 	char cmd[MKIMAGE_MAX_DTC_CMDLINE_LEN];
@@ -184,7 +185,7 @@ err_system:
 	return -1;
 }
 
-static int fit_check_params (struct mkimage_params *params)
+static int fit_check_params(struct image_tool_params *params)
 {
 	return	((params->dflag && (params->fflag || params->lflag)) ||
 		(params->fflag && (params->dflag || params->lflag)) ||
@@ -205,5 +206,5 @@ static struct image_type_params fitimage_params = {
 
 void init_fit_image_type (void)
 {
-	mkimage_register (&fitimage_params);
+	register_image_type(&fitimage_params);
 }
diff --git a/tools/gdb/Makefile b/tools/gdb/Makefile
index dee91fccc0..451332031e 100644
--- a/tools/gdb/Makefile
+++ b/tools/gdb/Makefile
@@ -8,51 +8,39 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-BINS	= gdbsend gdbcont
-
-COBJS	= gdbsend.o gdbcont.o error.o remote.o serial.o
-
-HOSTOBJS := $(addprefix $(obj),$(COBJS))
-HOSTSRCS := $(COBJS:.o=.c)
-BINS	:= $(addprefix $(obj),$(BINS))
+ifneq ($(HOSTOS),cygwin)
+
+# Location of a usable BFD library, where we define "usable" as
+# "built for ${HOST}, supports ${TARGET}".  Sensible values are
+# - When cross-compiling: the root of the cross-environment
+# - Linux/ppc (native): /usr
+# - NetBSD/ppc (native): you lose ... (must extract these from the
+#   binutils build directory, plus the native and U-Boot include
+#   files don't like each other)
+
+ifeq ($(HOSTOS),darwin)
+BFD_ROOT_DIR =		/usr/local/tools
+else
+ifeq ($(HOSTARCH),$(ARCH))
+# native
+BFD_ROOT_DIR =		/usr
+else
+#BFD_ROOT_DIR =		/LinuxPPC/CDK		# Linux/i386
+#BFD_ROOT_DIR =		/usr/pkg/cross		# NetBSD/i386
+BFD_ROOT_DIR =		/opt/powerpc
+endif
+endif
 
 #
 # Use native tools and options
 #
-HOSTCPPFLAGS = -I$(BFD_ROOT_DIR)/include
-
-HOSTOS := $(shell uname -s | sed -e 's/\([Cc][Yy][Gg][Ww][Ii][Nn]\).*/cygwin/')
-
-ifeq ($(HOSTOS),cygwin)
-
-all:
-$(obj).depend:
-
-else	# ! CYGWIN
-
-all:	$(obj).depend $(BINS)
-
-$(obj)gdbsend:	$(obj)gdbsend.o $(obj)error.o $(obj)remote.o $(obj)serial.o
-		$(HOSTCC) $(HOSTCFLAGS) $(HOSTLDFLAGS) -o $@ $^
-
-$(obj)gdbcont:	$(obj)gdbcont.o $(obj)error.o $(obj)remote.o $(obj)serial.o
-		$(HOSTCC) $(HOSTCFLAGS) $(HOSTLDFLAGS) -o $@ $^
-
-clean:
-	rm -f $(HOSTOBJS)
-
-distclean:	clean
-	rm -f $(BINS) $(obj)core $(obj)*.bak $(obj).depend
-
-#########################################################################
+HOST_EXTRACFLAGS := -I$(BFD_ROOT_DIR)/include -pedantic
 
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
+hostprogs-y := gdbsend gdbcont
 
-sinclude $(obj).depend
+gdbsend-objs := gdbsend.o error.o remote.o serial.o
+gdbcont-objs := gdbcont.o error.o remote.o serial.o
 
-#########################################################################
+always := $(hostprogs-y)
 
 endif	# cygwin
diff --git a/tools/image-fit.c b/tools/image-fit.c
new file mode 100644
index 0000000000..037e5cc8d7
--- /dev/null
+++ b/tools/image-fit.c
@@ -0,0 +1 @@
+#include "../common/image-fit.c"
diff --git a/tools/image-sig.c b/tools/image-sig.c
new file mode 100644
index 0000000000..e45419f321
--- /dev/null
+++ b/tools/image-sig.c
@@ -0,0 +1 @@
+#include "../common/image-sig.c"
diff --git a/tools/image.c b/tools/image.c
new file mode 100644
index 0000000000..0f9bacc702
--- /dev/null
+++ b/tools/image.c
@@ -0,0 +1 @@
+#include "../common/image.c"
diff --git a/tools/imagetool.c b/tools/imagetool.c
new file mode 100644
index 0000000000..29d2189097
--- /dev/null
+++ b/tools/imagetool.c
@@ -0,0 +1,58 @@
+/*
+ * (C) Copyright 2013
+ *
+ * Written by Guilherme Maciel Ferreira <guilherme.maciel.ferreira@gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include "imagetool.h"
+
+/*
+ * Callback function to register a image type within a tool
+ */
+static imagetool_register_t register_func;
+
+/*
+ * register_image_tool -
+ *
+ * The tool provides its own registration function in order to all image
+ * types initialize themselves.
+ */
+void register_image_tool(imagetool_register_t image_register)
+{
+	/*
+	 * Save the image tool callback function. It will be used to register
+	 * image types within that tool
+	 */
+	register_func = image_register;
+
+	/* Init Freescale PBL Boot image generation/list support */
+	init_pbl_image_type();
+	/* Init Kirkwood Boot image generation/list support */
+	init_kwb_image_type();
+	/* Init Freescale imx Boot image generation/list support */
+	init_imx_image_type();
+	/* Init Freescale mxs Boot image generation/list support */
+	init_mxs_image_type();
+	/* Init FIT image generation/list support */
+	init_fit_image_type();
+	/* Init TI OMAP Boot image generation/list support */
+	init_omap_image_type();
+	/* Init Default image generation/list support */
+	init_default_image_type();
+	/* Init Davinci UBL support */
+	init_ubl_image_type();
+	/* Init Davinci AIS support */
+	init_ais_image_type();
+}
+
+/*
+ * register_image_type -
+ *
+ * Register a image type within a tool
+ */
+void register_image_type(struct image_type_params *tparams)
+{
+	register_func(tparams);
+}
diff --git a/tools/imagetool.h b/tools/imagetool.h
new file mode 100644
index 0000000000..c2c9aea60e
--- /dev/null
+++ b/tools/imagetool.h
@@ -0,0 +1,173 @@
+/*
+ * (C) Copyright 2013
+ *
+ * Written by Guilherme Maciel Ferreira <guilherme.maciel.ferreira@gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _IMAGETOOL_H_
+#define _IMAGETOOL_H_
+
+#include "os_support.h"
+#include <errno.h>
+#include <fcntl.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+#include <sys/stat.h>
+#include <time.h>
+#include <unistd.h>
+#include <sha1.h>
+#include "fdt_host.h"
+
+#define ARRAY_SIZE(x)		(sizeof(x) / sizeof((x)[0]))
+
+#define IH_ARCH_DEFAULT		IH_ARCH_INVALID
+
+/*
+ * This structure defines all such variables those are initialized by
+ * mkimage and dumpimage main core and need to be referred by image
+ * type specific functions
+ */
+struct image_tool_params {
+	int dflag;
+	int eflag;
+	int fflag;
+	int iflag;
+	int lflag;
+	int pflag;
+	int vflag;
+	int xflag;
+	int skipcpy;
+	int os;
+	int arch;
+	int type;
+	int comp;
+	char *dtc;
+	unsigned int addr;
+	unsigned int ep;
+	char *imagename;
+	char *imagename2;
+	char *datafile;
+	char *imagefile;
+	char *cmdname;
+	const char *outfile;	/* Output filename */
+	const char *keydir;	/* Directory holding private keys */
+	const char *keydest;	/* Destination .dtb for public key */
+	const char *comment;	/* Comment to add to signature node */
+	int require_keys;	/* 1 to mark signing keys as 'required' */
+};
+
+/*
+ * image type specific variables and callback functions
+ */
+struct image_type_params {
+	/* name is an identification tag string for added support */
+	char *name;
+	/*
+	 * header size is local to the specific image type to be supported,
+	 * mkimage core treats this as number of bytes
+	 */
+	uint32_t header_size;
+	/* Image type header pointer */
+	void *hdr;
+	/*
+	 * There are several arguments that are passed on the command line
+	 * and are registered as flags in image_tool_params structure.
+	 * This callback function can be used to check the passed arguments
+	 * are in-lined with the image type to be supported
+	 *
+	 * Returns 1 if parameter check is successful
+	 */
+	int (*check_params) (struct image_tool_params *);
+	/*
+	 * This function is used by list command (i.e. mkimage -l <filename>)
+	 * image type verification code must be put here
+	 *
+	 * Returns 0 if image header verification is successful
+	 * otherwise, returns respective negative error codes
+	 */
+	int (*verify_header) (unsigned char *, int, struct image_tool_params *);
+	/* Prints image information abstracting from image header */
+	void (*print_header) (const void *);
+	/*
+	 * The header or image contents need to be set as per image type to
+	 * be generated using this callback function.
+	 * further output file post processing (for ex. checksum calculation,
+	 * padding bytes etc..) can also be done in this callback function.
+	 */
+	void (*set_header) (void *, struct stat *, int,
+					struct image_tool_params *);
+	/*
+	 * This function is used by the command to retrieve a data file from
+	 * the image (i.e. dumpimage -i <image> -p <position> <data_file>).
+	 * Thus the code to extract a file from an image must be put here.
+	 *
+	 * Returns 0 if the file was successfully retrieved from the image,
+	 * or a negative value on error.
+	 */
+	int (*extract_datafile) (void *, struct image_tool_params *);
+	/*
+	 * Some image generation support for ex (default image type) supports
+	 * more than one type_ids, this callback function is used to check
+	 * whether input (-T <image_type>) is supported by registered image
+	 * generation/list low level code
+	 */
+	int (*check_image_type) (uint8_t);
+	/* This callback function will be executed if fflag is defined */
+	int (*fflag_handle) (struct image_tool_params *);
+	/*
+	 * This callback function will be executed for variable size record
+	 * It is expected to build this header in memory and return its length
+	 * and a pointer to it by using image_type_params.header_size and
+	 * image_type_params.hdr. The return value shall indicate if an
+	 * additional padding should be used when copying the data image
+	 * by returning the padding length.
+	 */
+	int (*vrec_header) (struct image_tool_params *,
+		struct image_type_params *);
+	/* pointer to the next registered entry in linked list */
+	struct image_type_params *next;
+};
+
+/*
+ * Tool registration function.
+ */
+typedef void (*imagetool_register_t)(struct image_type_params *);
+
+/*
+ * Initializes all image types with the given registration callback
+ * function.
+ * An image tool uses this function to initialize all image types.
+ */
+void register_image_tool(imagetool_register_t image_register);
+
+/*
+ * Register a image type within a tool.
+ * An image type uses this function to register itself within
+ * all tools.
+ */
+void register_image_type(struct image_type_params *tparams);
+
+/*
+ * There is a c file associated with supported image type low level code
+ * for ex. default_image.c, fit_image.c
+ * init_xxx_type() is the only function referred by image tool core to avoid
+ * a single lined header file, you can define them here
+ *
+ * Supported image types init functions
+ */
+void init_default_image_type(void);
+void init_pbl_image_type(void);
+void init_ais_image_type(void);
+void init_kwb_image_type(void);
+void init_imx_image_type(void);
+void init_mxs_image_type(void);
+void init_fit_image_type(void);
+void init_ubl_image_type(void);
+void init_omap_image_type(void);
+
+void pbl_load_uboot(int fd, struct image_tool_params *mparams);
+
+#endif /* _IMAGETOOL_H_ */
diff --git a/tools/imls/Makefile b/tools/imls/Makefile
deleted file mode 100644
index e371983275..0000000000
--- a/tools/imls/Makefile
+++ /dev/null
@@ -1,84 +0,0 @@
-#
-# (C) Copyright 2009 Marco Stornelli <marco.stornelli@gmail.com>
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-include $(TOPDIR)/config.mk
-
-# Generated executable files
-BIN_FILES-y += imls
-
-# Source files which exist outside the tools/imls directory
-EXT_OBJ_FILES-y += lib/crc32.o
-EXT_OBJ_FILES-y += lib/md5.o
-EXT_OBJ_FILES-y += lib/sha1.o
-EXT_OBJ_FILES-y += common/image.o
-
-# Source files located in the tools/imls directory
-OBJ_FILES-y += imls.o
-
-# Flattened device tree objects
-LIBFDT_OBJ_FILES-y += fdt.o
-LIBFDT_OBJ_FILES-y += fdt_ro.o
-LIBFDT_OBJ_FILES-y += fdt_rw.o
-LIBFDT_OBJ_FILES-y += fdt_strerror.o
-LIBFDT_OBJ_FILES-y += fdt_wip.o
-
-# now $(obj) is defined
-SRCS	+= $(addprefix $(SRCTREE)/,$(EXT_OBJ_FILES-y:.o=.c))
-SRCS	+= $(addprefix $(SRCTREE)/tools/,$(OBJ_FILES-y:.o=.c))
-SRCS	+= $(addprefix $(SRCTREE)/lib/libfdt/,$(LIBFDT_OBJ_FILES-y:.o=.c))
-BINS	:= $(addprefix $(obj),$(sort $(BIN_FILES-y)))
-LIBFDT_OBJS	:= $(addprefix $(obj),$(LIBFDT_OBJ_FILES-y))
-
-#
-# Compile for a hosted environment on the target
-# Define __KERNEL_STRICT_NAMES to prevent typedef overlaps
-#
-HOSTCPPFLAGS  = -idirafter $(SRCTREE)/include \
-		-idirafter $(OBJTREE)/include2 \
-		-idirafter $(OBJTREE)/include \
-		-I $(SRCTREE)/lib/libfdt \
-		-I $(SRCTREE)/tools \
-		-DUSE_HOSTCC -D__KERNEL_STRICT_NAMES
-
-ifeq ($(MTD_VERSION),old)
-HOSTCPPFLAGS += -DMTD_OLD
-endif
-
-all:	$(BINS)
-
-$(obj)imls:	$(obj)imls.o $(obj)crc32.o $(obj)image.o $(obj)md5.o \
-		$(obj)sha1.o $(LIBFDT_OBJS)
-	$(CC) $(HOSTCFLAGS) $(HOSTLDFLAGS) -o $@ $^
-	$(STRIP) $@
-
-# Some files complain if compiled with -pedantic, use HOSTCFLAGS_NOPED
-$(obj)image.o: $(SRCTREE)/common/image.c
-	$(CC) -g $(HOSTCFLAGS_NOPED) -c -o $@ $<
-
-$(obj)imls.o: $(SRCTREE)/tools/imls/imls.c
-	$(CC) -g $(HOSTCFLAGS_NOPED) -c -o $@ $<
-
-# Some of the tool objects need to be accessed from outside the tools/imls directory
-$(obj)%.o: $(SRCTREE)/common/%.c
-	$(CC) -g $(HOSTCFLAGS_NOPED) -c -o $@ $<
-
-$(obj)%.o: $(SRCTREE)/lib/%.c
-	$(CC) -g $(HOSTCFLAGS) -c -o $@ $<
-
-$(obj)%.o: $(SRCTREE)/lib/libfdt/%.c
-	$(CC) -g $(HOSTCFLAGS_NOPED) -c -o $@ $<
-
-clean:
-	rm -rf *.o imls
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
diff --git a/tools/imls/README b/tools/imls/README
deleted file mode 100644
index 9adf92305d..0000000000
--- a/tools/imls/README
+++ /dev/null
@@ -1,41 +0,0 @@
-#
-# (C) Copyright 2009 Marco Stornelli <marco.stornelli@gmail.com>
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-IMLS
--------------
-
-imls is an implementation of a Linux command line tool to access
-to raw flash partitions and list images made with mkimage command.
-
-For building against older versions of the MTD headers (meaning before
-v2.6.8-rc1) it is required to pass the argument "MTD_VERSION=old" to
-make.
-
-Usage examples
---------------
-
-1) Flash with sectors of 128KiB and 32 sectors:
-
-> imls -c 32 -s 131072 /dev/mtd0
-Searching...
-Image Name:   foo
-Created:      Fri Apr 10 18:11:30 2009
-Image Type:   Intel x86 Linux Standalone Program (uncompressed)
-Data Size:    10716 Bytes = 10.46 kB = 0.01 MB
-Load Address: 00000000
-Entry Point:  00000000
-
-2) Flash with sectors of 64KiB and 128 sectors and with a search offset of one
-sector:
-
-> imls -o 1 -c 128 -s 65536 /dev/mtd0
-Searching...
-Image Name:   foo
-Created:      Fri Apr 10 18:11:30 2009
-Image Type:   Intel x86 Linux Standalone Program (uncompressed)
-Data Size:    10716 Bytes = 10.46 kB = 0.01 MB
-Load Address: 00000000
-Entry Point:  00000000
diff --git a/tools/imls/imls.c b/tools/imls/imls.c
deleted file mode 100644
index 95043b450b..0000000000
--- a/tools/imls/imls.c
+++ /dev/null
@@ -1,256 +0,0 @@
-/*
- * (C) Copyright 2009 Marco Stornelli
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <errno.h>
-#include <fcntl.h>
-#include <stdio.h>
-#include <stdlib.h>
-#include <stddef.h>
-#include <string.h>
-#include <sys/types.h>
-#include <sys/ioctl.h>
-#include <sys/stat.h>
-#include <unistd.h>
-#include <asm/page.h>
-
-#ifdef MTD_OLD
-#include <stdint.h>
-#include <linux/mtd/mtd.h>
-#else
-#define  __user	/* nothing */
-#include <mtd/mtd-user.h>
-#endif
-
-#include <sha1.h>
-#include <libfdt.h>
-#include <fdt_support.h>
-#include <image.h>
-
-#define MIN(a, b) (((a) < (b)) ? (a) : (b))
-
-extern unsigned long crc32(unsigned long crc, const char *buf, unsigned int len);
-static void usage(void);
-static int image_verify_header(char *ptr, int fd);
-static int flash_bad_block(int fd, uint8_t mtd_type, loff_t start);
-
-char	*cmdname;
-char	*devicefile;
-
-unsigned int sectorcount = 0;
-int sflag = 0;
-unsigned int sectoroffset = 0;
-unsigned int sectorsize = 0;
-int cflag = 0;
-
-int main (int argc, char **argv)
-{
-	int fd = -1, err = 0, readbyte = 0, j;
-	struct mtd_info_user mtdinfo;
-	char buf[sizeof(image_header_t)];
-	int found = 0;
-
-	cmdname = *argv;
-
-	while (--argc > 0 && **++argv == '-') {
-		while (*++*argv) {
-			switch (**argv) {
-			case 'c':
-				if (--argc <= 0)
-					usage ();
-				sectorcount = (unsigned int)atoi(*++argv);
-				cflag = 1;
-				goto NXTARG;
-			case 'o':
-				if (--argc <= 0)
-					usage ();
-				sectoroffset = (unsigned int)atoi(*++argv);
-				goto NXTARG;
-
-			case 's':
-				if (--argc <= 0)
-					usage ();
-				sectorsize = (unsigned int)atoi(*++argv);
-				sflag = 1;
-				goto NXTARG;
-			default:
-				usage ();
-			}
-		}
-NXTARG:		;
-	}
-
-	if (argc != 1 || cflag == 0 || sflag == 0)
-		usage();
-
-	devicefile = *argv;
-
-	fd = open(devicefile, O_RDONLY);
-	if (fd < 0) {
-		fprintf (stderr, "%s: Can't open %s: %s\n",
-			 cmdname, devicefile, strerror(errno));
-		exit(EXIT_FAILURE);
-	}
-
-	err = ioctl(fd, MEMGETINFO, &mtdinfo);
-	if (err < 0) {
-		fprintf(stderr, "%s: Cannot get MTD information: %s\n",cmdname,
-			strerror(errno));
-		exit(EXIT_FAILURE);
-	}
-
-	if (mtdinfo.type != MTD_NORFLASH && mtdinfo.type != MTD_NANDFLASH) {
-		fprintf(stderr, "%s: Unsupported flash type %u\n",
-			cmdname, mtdinfo.type);
-		exit(EXIT_FAILURE);
-	}
-
-	if (sectorsize * sectorcount != mtdinfo.size) {
-		fprintf(stderr, "%s: Partition size (%d) incompatible with "
-			"sector size and count\n", cmdname, mtdinfo.size);
-		exit(EXIT_FAILURE);
-	}
-
-	if (sectorsize * sectoroffset >= mtdinfo.size) {
-		fprintf(stderr, "%s: Partition size (%d) incompatible with "
-			"sector offset given\n", cmdname, mtdinfo.size);
-		exit(EXIT_FAILURE);
-	}
-
-	if (sectoroffset > sectorcount - 1) {
-		fprintf(stderr, "%s: Sector offset cannot be grater than "
-			"sector count minus one\n", cmdname);
-		exit(EXIT_FAILURE);
-	}
-
-	printf("Searching....\n");
-
-	for (j = sectoroffset; j < sectorcount; ++j) {
-
-		if (lseek(fd, j*sectorsize, SEEK_SET) != j*sectorsize) {
-			fprintf(stderr, "%s: lseek failure: %s\n",
-			cmdname, strerror(errno));
-			exit(EXIT_FAILURE);
-		}
-
-		err = flash_bad_block(fd, mtdinfo.type, j*sectorsize);
-		if (err < 0)
-			exit(EXIT_FAILURE);
-		if (err)
-			continue; /* Skip and jump to next */
-
-		readbyte = read(fd, buf, sizeof(image_header_t));
-		if (readbyte != sizeof(image_header_t)) {
-			fprintf(stderr, "%s: Can't read from device: %s\n",
-			cmdname, strerror(errno));
-			exit(EXIT_FAILURE);
-		}
-
-		if (fdt_check_header(buf)) {
-			/* old-style image */
-			if (image_verify_header(buf, fd)) {
-				found = 1;
-				image_print_contents((image_header_t *)buf);
-			}
-		} else {
-			/* FIT image */
-			fit_print_contents(buf);
-		}
-
-	}
-
-	close(fd);
-
-	if(!found)
-		printf("No images found\n");
-
-	exit(EXIT_SUCCESS);
-}
-
-void usage()
-{
-	fprintf (stderr, "Usage:\n"
-			 "       %s [-o offset] -s size -c count device\n"
-			 "          -o ==> number of sectors to use as offset\n"
-			 "          -c ==> number of sectors\n"
-			 "          -s ==> size of sectors (byte)\n",
-		cmdname);
-
-	exit(EXIT_FAILURE);
-}
-
-static int image_verify_header(char *ptr, int fd)
-{
-	int len, nread;
-	char *data;
-	uint32_t checksum;
-	image_header_t *hdr = (image_header_t *)ptr;
-	char buf[PAGE_SIZE];
-
-	if (image_get_magic(hdr) != IH_MAGIC)
-		return 0;
-
-	data = (char *)hdr;
-	len  = image_get_header_size();
-
-	checksum = image_get_hcrc(hdr);
-	hdr->ih_hcrc = htonl(0);	/* clear for re-calculation */
-
-	if (crc32(0, data, len) != checksum) {
-		fprintf(stderr,
-		      "%s: Maybe image found but it has bad header checksum!\n",
-		      cmdname);
-		return 0;
-	}
-
-	len = image_get_size(hdr);
-	checksum = 0;
-
-	while (len > 0) {
-		nread = read(fd, buf, MIN(len,PAGE_SIZE));
-		if (nread != MIN(len,PAGE_SIZE)) {
-			fprintf(stderr,
-				"%s: Error while reading: %s\n",
-				cmdname, strerror(errno));
-			exit(EXIT_FAILURE);
-		}
-		checksum = crc32(checksum, buf, nread);
-		len -= nread;
-	}
-
-	if (checksum != image_get_dcrc(hdr)) {
-		fprintf (stderr,
-			"%s: Maybe image found but it has corrupted data!\n",
-			cmdname);
-		return 0;
-	}
-
-	return 1;
-}
-
-/*
- * Test for bad block on NAND, just returns 0 on NOR, on NAND:
- * 0	- block is good
- * > 0	- block is bad
- * < 0	- failed to test
- */
-static int flash_bad_block(int fd, uint8_t mtd_type, loff_t start)
-{
-	if (mtd_type == MTD_NANDFLASH) {
-		int badblock = ioctl(fd, MEMGETBADBLOCK, &start);
-
-		if (badblock < 0) {
-			fprintf(stderr,"%s: Cannot read bad block mark: %s\n",
-				cmdname, strerror(errno));
-			return badblock;
-		}
-
-		if (badblock) {
-			return badblock;
-		}
-	}
-
-	return 0;
-}
diff --git a/tools/imximage.c b/tools/imximage.c
index 511e3f2038..18dc051c5e 100644
--- a/tools/imximage.c
+++ b/tools/imximage.c
@@ -9,7 +9,7 @@
  * SPDX-License-Identifier:	GPL-2.0+
  */
 
-#include "mkimage.h"
+#include "imagetool.h"
 #include <image.h>
 #include "imximage.h"
 
@@ -520,7 +520,7 @@ static int imximage_check_image_types(uint8_t type)
 }
 
 static int imximage_verify_header(unsigned char *ptr, int image_size,
-			struct mkimage_params *params)
+			struct image_tool_params *params)
 {
 	struct imx_header *imx_hdr = (struct imx_header *) ptr;
 
@@ -549,7 +549,7 @@ static void imximage_print_header(const void *ptr)
 }
 
 static void imximage_set_header(void *ptr, struct stat *sbuf, int ifd,
-				struct mkimage_params *params)
+				struct image_tool_params *params)
 {
 	struct imx_header *imxhdr = (struct imx_header *)ptr;
 	uint32_t dcd_len;
@@ -589,7 +589,7 @@ static void imximage_set_header(void *ptr, struct stat *sbuf, int ifd,
 	}
 }
 
-int imximage_check_params(struct mkimage_params *params)
+int imximage_check_params(struct image_tool_params *params)
 {
 	if (!params)
 		return CFG_INVALID;
@@ -611,7 +611,7 @@ int imximage_check_params(struct mkimage_params *params)
 		(params->xflag) || !(strlen(params->imagename));
 }
 
-static int imximage_generate(struct mkimage_params *params,
+static int imximage_generate(struct image_tool_params *params,
 	struct image_type_params *tparams)
 {
 	struct imx_header *imxhdr;
@@ -701,5 +701,5 @@ static struct image_type_params imximage_params = {
 
 void init_imx_image_type(void)
 {
-	mkimage_register(&imximage_params);
+	register_image_type(&imximage_params);
 }
diff --git a/tools/imximage.h b/tools/imximage.h
index 01f861e7a5..b596fb1398 100644
--- a/tools/imximage.h
+++ b/tools/imximage.h
@@ -149,6 +149,7 @@ typedef struct {
 typedef struct {
 	flash_header_v2_t fhdr;
 	boot_data_t boot_data;
+	uint32_t reserved1;
 	dcd_v2_t dcd_table;
 } imx_header_v2_t;
 
diff --git a/tools/kermit/README b/tools/kermit/README
new file mode 100644
index 0000000000..c3b491aa55
--- /dev/null
+++ b/tools/kermit/README
@@ -0,0 +1,51 @@
+#
+# (C) Copyright 2001
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+This directory contains scripts that help to perform certain actions
+that need to be done frequently when working with U-Boot.
+
+They are meant as EXAMPLE code, so it is very likely that you will
+have to modify them before use.
+
+
+Short description:
+==================
+
+dot.kermrc:
+
+	Example for "~/.kermrc" Kermit init file for use with U-Boot
+
+	by Wolfgang Denk, 24 Jun 2001
+
+flash_param:
+
+	"kermit" script to automatically initialize the environment
+	variables on your target. This is most useful during
+	development when your environment variables are stored in an
+	embedded flash sector which is erased whenever you install a
+	new U-Boot image.
+
+	by Swen Anderson, 10 May 2001
+
+send_cmd:
+
+	send_cmd U_BOOT_COMMAND
+
+	"kermit" script to send a U-Boot command and print the
+	results. When used from a shell with history (like the bash)
+	this indirectly adds kind of history to U-Boot ;-)
+
+	by Swen Anderson, 10 May 2001
+
+send_image:
+
+	send_image FILE_NAME OFFSET
+
+	"kermit" script to automatically download a file to the
+	target using the "loadb" command (kermit binary protocol)
+
+	by Swen Anderson, 10 May 2001
diff --git a/tools/scripts/dot.kermrc b/tools/kermit/dot.kermrc
index 0fc6c15d35..0fc6c15d35 100644
--- a/tools/scripts/dot.kermrc
+++ b/tools/kermit/dot.kermrc
diff --git a/tools/scripts/flash_param b/tools/kermit/flash_param
index 847f99e1eb..847f99e1eb 100644
--- a/tools/scripts/flash_param
+++ b/tools/kermit/flash_param
diff --git a/tools/scripts/send_cmd b/tools/kermit/send_cmd
index 4131331f03..4131331f03 100644
--- a/tools/scripts/send_cmd
+++ b/tools/kermit/send_cmd
diff --git a/tools/scripts/send_image b/tools/kermit/send_image
index 9b89d6b059..9b89d6b059 100644
--- a/tools/scripts/send_image
+++ b/tools/kermit/send_image
diff --git a/tools/kernel-doc/Makefile b/tools/kernel-doc/Makefile
deleted file mode 100644
index eb56e2e753..0000000000
--- a/tools/kernel-doc/Makefile
+++ /dev/null
@@ -1,25 +0,0 @@
-#
-# Copyright (C) 2012 Marek Vasut <marex@denx.de>
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-include $(TOPDIR)/config.mk
-
-all:	$(obj)docproc
-
-$(obj)docproc:	docproc.c
-	$(HOSTCC) $(HOSTCFLAGS) $(HOSTLDFLAGS) -o $@ $^
-	$(HOSTSTRIP) $@
-
-clean:
-	rm -rf docproc
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
diff --git a/tools/kernel-doc/docproc.c b/tools/kernel-doc/docproc.c
deleted file mode 100644
index a9b49c59a0..0000000000
--- a/tools/kernel-doc/docproc.c
+++ /dev/null
@@ -1,576 +0,0 @@
-/*
- *	docproc is a simple preprocessor for the template files
- *      used as placeholders for the kernel internal documentation.
- *	docproc is used for documentation-frontend and
- *      dependency-generator.
- *	The two usages have in common that they require
- *	some knowledge of the .tmpl syntax, therefore they
- *	are kept together.
- *
- *	documentation-frontend
- *		Scans the template file and call kernel-doc for
- *		all occurrences of ![EIF]file
- *		Beforehand each referenced file is scanned for
- *		any symbols that are exported via these macros:
- *			EXPORT_SYMBOL(), EXPORT_SYMBOL_GPL(), &
- *			EXPORT_SYMBOL_GPL_FUTURE()
- *		This is used to create proper -function and
- *		-nofunction arguments in calls to kernel-doc.
- *		Usage: docproc doc file.tmpl
- *
- *	dependency-generator:
- *		Scans the template file and list all files
- *		referenced in a format recognized by make.
- *		Usage:	docproc depend file.tmpl
- *		Writes dependency information to stdout
- *		in the following format:
- *		file.tmpl src.c	src2.c
- *		The filenames are obtained from the following constructs:
- *		!Efilename
- *		!Ifilename
- *		!Dfilename
- *		!Ffilename
- *		!Pfilename
- *
- */
-
-#define _GNU_SOURCE
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-#include <ctype.h>
-#include <unistd.h>
-#include <limits.h>
-#include <errno.h>
-#include <sys/types.h>
-#include <sys/wait.h>
-
-/* exitstatus is used to keep track of any failing calls to kernel-doc,
- * but execution continues. */
-int exitstatus = 0;
-
-typedef void DFL(char *);
-DFL *defaultline;
-
-typedef void FILEONLY(char * file);
-FILEONLY *internalfunctions;
-FILEONLY *externalfunctions;
-FILEONLY *symbolsonly;
-FILEONLY *findall;
-
-typedef void FILELINE(char * file, char * line);
-FILELINE * singlefunctions;
-FILELINE * entity_system;
-FILELINE * docsection;
-
-#define MAXLINESZ     2048
-#define MAXFILES      250
-#define KERNELDOCPATH "tools/kernel-doc/"
-#define KERNELDOC     "kernel-doc"
-#define DOCBOOK       "-docbook"
-#define LIST          "-list"
-#define FUNCTION      "-function"
-#define NOFUNCTION    "-nofunction"
-#define NODOCSECTIONS "-no-doc-sections"
-
-static char *srctree, *kernsrctree;
-
-static char **all_list = NULL;
-static int all_list_len = 0;
-
-static void consume_symbol(const char *sym)
-{
-	int i;
-
-	for (i = 0; i < all_list_len; i++) {
-		if (!all_list[i])
-			continue;
-		if (strcmp(sym, all_list[i]))
-			continue;
-		all_list[i] = NULL;
-		break;
-	}
-}
-
-static void usage (void)
-{
-	fprintf(stderr, "Usage: docproc {doc|depend} file\n");
-	fprintf(stderr, "Input is read from file.tmpl. Output is sent to stdout\n");
-	fprintf(stderr, "doc: frontend when generating kernel documentation\n");
-	fprintf(stderr, "depend: generate list of files referenced within file\n");
-	fprintf(stderr, "Environment variable SRCTREE: absolute path to sources.\n");
-	fprintf(stderr, "                     KBUILD_SRC: absolute path to kernel source tree.\n");
-}
-
-/*
- * Execute kernel-doc with parameters given in svec
- */
-static void exec_kernel_doc(char **svec)
-{
-	pid_t pid;
-	int ret;
-	char real_filename[PATH_MAX + 1];
-	/* Make sure output generated so far are flushed */
-	fflush(stdout);
-	switch (pid=fork()) {
-		case -1:
-			perror("fork");
-			exit(1);
-		case  0:
-			memset(real_filename, 0, sizeof(real_filename));
-			strncat(real_filename, kernsrctree, PATH_MAX);
-			strncat(real_filename, "/" KERNELDOCPATH KERNELDOC,
-					PATH_MAX - strlen(real_filename));
-			execvp(real_filename, svec);
-			fprintf(stderr, "exec ");
-			perror(real_filename);
-			exit(1);
-		default:
-			waitpid(pid, &ret ,0);
-	}
-	if (WIFEXITED(ret))
-		exitstatus |= WEXITSTATUS(ret);
-	else
-		exitstatus = 0xff;
-}
-
-/* Types used to create list of all exported symbols in a number of files */
-struct symbols
-{
-	char *name;
-};
-
-struct symfile
-{
-	char *filename;
-	struct symbols *symbollist;
-	int symbolcnt;
-};
-
-struct symfile symfilelist[MAXFILES];
-int symfilecnt = 0;
-
-static void add_new_symbol(struct symfile *sym, char * symname)
-{
-	sym->symbollist =
-	  realloc(sym->symbollist, (sym->symbolcnt + 1) * sizeof(char *));
-	sym->symbollist[sym->symbolcnt++].name = strdup(symname);
-}
-
-/* Add a filename to the list */
-static struct symfile * add_new_file(char * filename)
-{
-	symfilelist[symfilecnt++].filename = strdup(filename);
-	return &symfilelist[symfilecnt - 1];
-}
-
-/* Check if file already are present in the list */
-static struct symfile * filename_exist(char * filename)
-{
-	int i;
-	for (i=0; i < symfilecnt; i++)
-		if (strcmp(symfilelist[i].filename, filename) == 0)
-			return &symfilelist[i];
-	return NULL;
-}
-
-/*
- * List all files referenced within the template file.
- * Files are separated by tabs.
- */
-static void adddep(char * file)		   { printf("\t%s", file); }
-static void adddep2(char * file, char * line)     { line = line; adddep(file); }
-static void noaction(char * line)		   { line = line; }
-static void noaction2(char * file, char * line)   { file = file; line = line; }
-
-/* Echo the line without further action */
-static void printline(char * line)               { printf("%s", line); }
-
-/*
- * Find all symbols in filename that are exported with EXPORT_SYMBOL &
- * EXPORT_SYMBOL_GPL (& EXPORT_SYMBOL_GPL_FUTURE implicitly).
- * All symbols located are stored in symfilelist.
- */
-static void find_export_symbols(char * filename)
-{
-	FILE * fp;
-	struct symfile *sym;
-	char line[MAXLINESZ];
-	if (filename_exist(filename) == NULL) {
-		char real_filename[PATH_MAX + 1];
-		memset(real_filename, 0, sizeof(real_filename));
-		strncat(real_filename, srctree, PATH_MAX);
-		strncat(real_filename, "/", PATH_MAX - strlen(real_filename));
-		strncat(real_filename, filename,
-				PATH_MAX - strlen(real_filename));
-		sym = add_new_file(filename);
-		fp = fopen(real_filename, "r");
-		if (fp == NULL)	{
-			fprintf(stderr, "docproc: ");
-			perror(real_filename);
-			exit(1);
-		}
-		while (fgets(line, MAXLINESZ, fp)) {
-			char *p;
-			char *e;
-			if (((p = strstr(line, "EXPORT_SYMBOL_GPL")) != NULL) ||
-			    ((p = strstr(line, "EXPORT_SYMBOL")) != NULL)) {
-				/* Skip EXPORT_SYMBOL{_GPL} */
-				while (isalnum(*p) || *p == '_')
-					p++;
-				/* Remove parentheses & additional whitespace */
-				while (isspace(*p))
-					p++;
-				if (*p != '(')
-					continue; /* Syntax error? */
-				else
-					p++;
-				while (isspace(*p))
-					p++;
-				e = p;
-				while (isalnum(*e) || *e == '_')
-					e++;
-				*e = '\0';
-				add_new_symbol(sym, p);
-			}
-		}
-		fclose(fp);
-	}
-}
-
-/*
- * Document all external or internal functions in a file.
- * Call kernel-doc with following parameters:
- * kernel-doc -docbook -nofunction function_name1 filename
- * Function names are obtained from all the src files
- * by find_export_symbols.
- * intfunc uses -nofunction
- * extfunc uses -function
- */
-static void docfunctions(char * filename, char * type)
-{
-	int i,j;
-	int symcnt = 0;
-	int idx = 0;
-	char **vec;
-
-	for (i=0; i <= symfilecnt; i++)
-		symcnt += symfilelist[i].symbolcnt;
-	vec = malloc((2 + 2 * symcnt + 3) * sizeof(char *));
-	if (vec == NULL) {
-		perror("docproc: ");
-		exit(1);
-	}
-	vec[idx++] = KERNELDOC;
-	vec[idx++] = DOCBOOK;
-	vec[idx++] = NODOCSECTIONS;
-	for (i=0; i < symfilecnt; i++) {
-		struct symfile * sym = &symfilelist[i];
-		for (j=0; j < sym->symbolcnt; j++) {
-			vec[idx++]     = type;
-			consume_symbol(sym->symbollist[j].name);
-			vec[idx++] = sym->symbollist[j].name;
-		}
-	}
-	vec[idx++]     = filename;
-	vec[idx] = NULL;
-	printf("<!-- %s -->\n", filename);
-	exec_kernel_doc(vec);
-	fflush(stdout);
-	free(vec);
-}
-static void intfunc(char * filename) {	docfunctions(filename, NOFUNCTION); }
-static void extfunc(char * filename) { docfunctions(filename, FUNCTION);   }
-
-/*
- * Document specific function(s) in a file.
- * Call kernel-doc with the following parameters:
- * kernel-doc -docbook -function function1 [-function function2]
- */
-static void singfunc(char * filename, char * line)
-{
-	char *vec[200]; /* Enough for specific functions */
-	int i, idx = 0;
-	int startofsym = 1;
-	vec[idx++] = KERNELDOC;
-	vec[idx++] = DOCBOOK;
-
-	/* Split line up in individual parameters preceded by FUNCTION */
-	for (i=0; line[i]; i++) {
-		if (isspace(line[i])) {
-			line[i] = '\0';
-			startofsym = 1;
-			continue;
-		}
-		if (startofsym) {
-			startofsym = 0;
-			vec[idx++] = FUNCTION;
-			vec[idx++] = &line[i];
-		}
-	}
-	for (i = 0; i < idx; i++) {
-		if (strcmp(vec[i], FUNCTION))
-			continue;
-		consume_symbol(vec[i + 1]);
-	}
-	vec[idx++] = filename;
-	vec[idx] = NULL;
-	exec_kernel_doc(vec);
-}
-
-/*
- * Insert specific documentation section from a file.
- * Call kernel-doc with the following parameters:
- * kernel-doc -docbook -function "doc section" filename
- */
-static void docsect(char *filename, char *line)
-{
-	char *vec[6]; /* kerneldoc -docbook -function "section" file NULL */
-	char *s;
-
-	for (s = line; *s; s++)
-		if (*s == '\n')
-			*s = '\0';
-
-	if (asprintf(&s, "DOC: %s", line) < 0) {
-		perror("asprintf");
-		exit(1);
-	}
-	consume_symbol(s);
-	free(s);
-
-	vec[0] = KERNELDOC;
-	vec[1] = DOCBOOK;
-	vec[2] = FUNCTION;
-	vec[3] = line;
-	vec[4] = filename;
-	vec[5] = NULL;
-	exec_kernel_doc(vec);
-}
-
-static void find_all_symbols(char *filename)
-{
-	char *vec[4]; /* kerneldoc -list file NULL */
-	pid_t pid;
-	int ret, i, count, start;
-	char real_filename[PATH_MAX + 1];
-	int pipefd[2];
-	char *data, *str;
-	size_t data_len = 0;
-
-	vec[0] = KERNELDOC;
-	vec[1] = LIST;
-	vec[2] = filename;
-	vec[3] = NULL;
-
-	if (pipe(pipefd)) {
-		perror("pipe");
-		exit(1);
-	}
-
-	switch (pid=fork()) {
-		case -1:
-			perror("fork");
-			exit(1);
-		case  0:
-			close(pipefd[0]);
-			dup2(pipefd[1], 1);
-			memset(real_filename, 0, sizeof(real_filename));
-			strncat(real_filename, kernsrctree, PATH_MAX);
-			strncat(real_filename, "/" KERNELDOCPATH KERNELDOC,
-					PATH_MAX - strlen(real_filename));
-			execvp(real_filename, vec);
-			fprintf(stderr, "exec ");
-			perror(real_filename);
-			exit(1);
-		default:
-			close(pipefd[1]);
-			data = malloc(4096);
-			do {
-				while ((ret = read(pipefd[0],
-						   data + data_len,
-						   4096)) > 0) {
-					data_len += ret;
-					data = realloc(data, data_len + 4096);
-				}
-			} while (ret == -EAGAIN);
-			if (ret != 0) {
-				perror("read");
-				exit(1);
-			}
-			waitpid(pid, &ret ,0);
-	}
-	if (WIFEXITED(ret))
-		exitstatus |= WEXITSTATUS(ret);
-	else
-		exitstatus = 0xff;
-
-	count = 0;
-	/* poor man's strtok, but with counting */
-	for (i = 0; i < data_len; i++) {
-		if (data[i] == '\n') {
-			count++;
-			data[i] = '\0';
-		}
-	}
-	start = all_list_len;
-	all_list_len += count;
-	all_list = realloc(all_list, sizeof(char *) * all_list_len);
-	str = data;
-	for (i = 0; i < data_len && start != all_list_len; i++) {
-		if (data[i] == '\0') {
-			all_list[start] = str;
-			str = data + i + 1;
-			start++;
-		}
-	}
-}
-
-/*
- * Parse file, calling action specific functions for:
- * 1) Lines containing !E
- * 2) Lines containing !I
- * 3) Lines containing !D
- * 4) Lines containing !F
- * 5) Lines containing !P
- * 6) Lines containing !C
- * 7) Default lines - lines not matching the above
- */
-static void parse_file(FILE *infile)
-{
-	char line[MAXLINESZ];
-	char * s;
-	while (fgets(line, MAXLINESZ, infile)) {
-		if (line[0] == '!') {
-			s = line + 2;
-			switch (line[1]) {
-				case 'E':
-					while (*s && !isspace(*s)) s++;
-					*s = '\0';
-					externalfunctions(line+2);
-					break;
-				case 'I':
-					while (*s && !isspace(*s)) s++;
-					*s = '\0';
-					internalfunctions(line+2);
-					break;
-				case 'D':
-					while (*s && !isspace(*s)) s++;
-					*s = '\0';
-					symbolsonly(line+2);
-					break;
-				case 'F':
-					/* filename */
-					while (*s && !isspace(*s)) s++;
-					*s++ = '\0';
-					/* function names */
-					while (isspace(*s))
-						s++;
-					singlefunctions(line +2, s);
-					break;
-				case 'P':
-					/* filename */
-					while (*s && !isspace(*s)) s++;
-					*s++ = '\0';
-					/* DOC: section name */
-					while (isspace(*s))
-						s++;
-					docsection(line + 2, s);
-					break;
-				case 'C':
-					while (*s && !isspace(*s)) s++;
-					*s = '\0';
-					if (findall)
-						findall(line+2);
-					break;
-				default:
-					defaultline(line);
-			}
-		} else {
-			defaultline(line);
-		}
-	}
-	fflush(stdout);
-}
-
-
-int main(int argc, char *argv[])
-{
-	FILE * infile;
-	int i;
-
-	srctree = getenv("SRCTREE");
-	if (!srctree)
-		srctree = getcwd(NULL, 0);
-	kernsrctree = getenv("KBUILD_SRC");
-	if (!kernsrctree || !*kernsrctree)
-		kernsrctree = srctree;
-	if (argc != 3) {
-		usage();
-		exit(1);
-	}
-	/* Open file, exit on error */
-	infile = fopen(argv[2], "r");
-	if (infile == NULL) {
-		fprintf(stderr, "docproc: ");
-		perror(argv[2]);
-		exit(2);
-	}
-
-	if (strcmp("doc", argv[1]) == 0) {
-		/* Need to do this in two passes.
-		 * First pass is used to collect all symbols exported
-		 * in the various files;
-		 * Second pass generate the documentation.
-		 * This is required because some functions are declared
-		 * and exported in different files :-((
-		 */
-		/* Collect symbols */
-		defaultline       = noaction;
-		internalfunctions = find_export_symbols;
-		externalfunctions = find_export_symbols;
-		symbolsonly       = find_export_symbols;
-		singlefunctions   = noaction2;
-		docsection        = noaction2;
-		findall           = find_all_symbols;
-		parse_file(infile);
-
-		/* Rewind to start from beginning of file again */
-		fseek(infile, 0, SEEK_SET);
-		defaultline       = printline;
-		internalfunctions = intfunc;
-		externalfunctions = extfunc;
-		symbolsonly       = printline;
-		singlefunctions   = singfunc;
-		docsection        = docsect;
-		findall           = NULL;
-
-		parse_file(infile);
-
-		for (i = 0; i < all_list_len; i++) {
-			if (!all_list[i])
-				continue;
-			fprintf(stderr, "Warning: didn't use docs for %s\n",
-				all_list[i]);
-		}
-	} else if (strcmp("depend", argv[1]) == 0) {
-		/* Create first part of dependency chain
-		 * file.tmpl */
-		printf("%s\t", argv[2]);
-		defaultline       = noaction;
-		internalfunctions = adddep;
-		externalfunctions = adddep;
-		symbolsonly       = adddep;
-		singlefunctions   = adddep2;
-		docsection        = adddep2;
-		findall           = adddep;
-		parse_file(infile);
-		printf("\n");
-	} else {
-		fprintf(stderr, "Unknown option: %s\n", argv[1]);
-		exit(1);
-	}
-	fclose(infile);
-	fflush(stdout);
-	return exitstatus;
-}
diff --git a/tools/kernel-doc/kernel-doc b/tools/kernel-doc/kernel-doc
deleted file mode 100755
index cbbf34c27c..0000000000
--- a/tools/kernel-doc/kernel-doc
+++ /dev/null
@@ -1,2557 +0,0 @@
-#!/usr/bin/perl -w
-
-use strict;
-
-## Copyright (c) 1998 Michael Zucchi, All Rights Reserved        ##
-## Copyright (C) 2000, 1  Tim Waugh <twaugh@redhat.com>          ##
-## Copyright (C) 2001  Simon Huggins                             ##
-## Copyright (C) 2005-2012  Randy Dunlap                         ##
-## Copyright (C) 2012  Dan Luedtke                               ##
-## 								 ##
-## #define enhancements by Armin Kuster <akuster@mvista.com>	 ##
-## Copyright (c) 2000 MontaVista Software, Inc.			 ##
-## 								 ##
-## This software falls under the GNU General Public License.     ##
-## Please read the COPYING file for more information             ##
-
-# 18/01/2001 - 	Cleanups
-# 		Functions prototyped as foo(void) same as foo()
-# 		Stop eval'ing where we don't need to.
-# -- huggie@earth.li
-
-# 27/06/2001 -  Allowed whitespace after initial "/**" and
-#               allowed comments before function declarations.
-# -- Christian Kreibich <ck@whoop.org>
-
-# Still to do:
-# 	- add perldoc documentation
-# 	- Look more closely at some of the scarier bits :)
-
-# 26/05/2001 - 	Support for separate source and object trees.
-#		Return error code.
-# 		Keith Owens <kaos@ocs.com.au>
-
-# 23/09/2001 - Added support for typedefs, structs, enums and unions
-#              Support for Context section; can be terminated using empty line
-#              Small fixes (like spaces vs. \s in regex)
-# -- Tim Jansen <tim@tjansen.de>
-
-# 25/07/2012 - Added support for HTML5
-# -- Dan Luedtke <mail@danrl.de>
-
-#
-# This will read a 'c' file and scan for embedded comments in the
-# style of gnome comments (+minor extensions - see below).
-#
-
-# Note: This only supports 'c'.
-
-# usage:
-# kernel-doc [ -docbook | -html | -html5 | -text | -man | -list ]
-#            [ -no-doc-sections ]
-#            [ -function funcname [ -function funcname ...] ]
-#            c file(s)s > outputfile
-# or
-#            [ -nofunction funcname [ -function funcname ...] ]
-#            c file(s)s > outputfile
-#
-#  Set output format using one of -docbook -html -html5 -text or -man.
-#  Default is man.
-#  The -list format is for internal use by docproc.
-#
-#  -no-doc-sections
-#	Do not output DOC: sections
-#
-#  -function funcname
-#	If set, then only generate documentation for the given function(s) or
-#	DOC: section titles.  All other functions and DOC: sections are ignored.
-#
-#  -nofunction funcname
-#	If set, then only generate documentation for the other function(s)/DOC:
-#	sections. Cannot be used together with -function (yes, that's a bug --
-#	perl hackers can fix it 8))
-#
-#  c files - list of 'c' files to process
-#
-#  All output goes to stdout, with errors to stderr.
-
-#
-# format of comments.
-# In the following table, (...)? signifies optional structure.
-#                         (...)* signifies 0 or more structure elements
-# /**
-#  * function_name(:)? (- short description)?
-# (* @parameterx: (description of parameter x)?)*
-# (* a blank line)?
-#  * (Description:)? (Description of function)?
-#  * (section header: (section description)? )*
-#  (*)?*/
-#
-# So .. the trivial example would be:
-#
-# /**
-#  * my_function
-#  */
-#
-# If the Description: header tag is omitted, then there must be a blank line
-# after the last parameter specification.
-# e.g.
-# /**
-#  * my_function - does my stuff
-#  * @my_arg: its mine damnit
-#  *
-#  * Does my stuff explained.
-#  */
-#
-#  or, could also use:
-# /**
-#  * my_function - does my stuff
-#  * @my_arg: its mine damnit
-#  * Description: Does my stuff explained.
-#  */
-# etc.
-#
-# Besides functions you can also write documentation for structs, unions,
-# enums and typedefs. Instead of the function name you must write the name
-# of the declaration;  the struct/union/enum/typedef must always precede
-# the name. Nesting of declarations is not supported.
-# Use the argument mechanism to document members or constants.
-# e.g.
-# /**
-#  * struct my_struct - short description
-#  * @a: first member
-#  * @b: second member
-#  *
-#  * Longer description
-#  */
-# struct my_struct {
-#     int a;
-#     int b;
-# /* private: */
-#     int c;
-# };
-#
-# All descriptions can be multiline, except the short function description.
-#
-# You can also add additional sections. When documenting kernel functions you
-# should document the "Context:" of the function, e.g. whether the functions
-# can be called form interrupts. Unlike other sections you can end it with an
-# empty line.
-# Example-sections should contain the string EXAMPLE so that they are marked
-# appropriately in DocBook.
-#
-# Example:
-# /**
-#  * user_function - function that can only be called in user context
-#  * @a: some argument
-#  * Context: !in_interrupt()
-#  *
-#  * Some description
-#  * Example:
-#  *    user_function(22);
-#  */
-# ...
-#
-#
-# All descriptive text is further processed, scanning for the following special
-# patterns, which are highlighted appropriately.
-#
-# 'funcname()' - function
-# '$ENVVAR' - environmental variable
-# '&struct_name' - name of a structure (up to two words including 'struct')
-# '@parameter' - name of a parameter
-# '%CONST' - name of a constant.
-
-## init lots of data
-
-my $errors = 0;
-my $warnings = 0;
-my $anon_struct_union = 0;
-
-# match expressions used to find embedded type information
-my $type_constant = '\%([-_\w]+)';
-my $type_func = '(\w+)\(\)';
-my $type_param = '\@(\w+)';
-my $type_struct = '\&((struct\s*)*[_\w]+)';
-my $type_struct_xml = '\\&amp;((struct\s*)*[_\w]+)';
-my $type_env = '(\$\w+)';
-
-# Output conversion substitutions.
-#  One for each output format
-
-# these work fairly well
-my %highlights_html = ( $type_constant, "<i>\$1</i>",
-			$type_func, "<b>\$1</b>",
-			$type_struct_xml, "<i>\$1</i>",
-			$type_env, "<b><i>\$1</i></b>",
-			$type_param, "<tt><b>\$1</b></tt>" );
-my $local_lt = "\\\\\\\\lt:";
-my $local_gt = "\\\\\\\\gt:";
-my $blankline_html = $local_lt . "p" . $local_gt;	# was "<p>"
-
-# html version 5
-my %highlights_html5 = ( $type_constant, "<span class=\"const\">\$1</span>",
-			$type_func, "<span class=\"func\">\$1</span>",
-			$type_struct_xml, "<span class=\"struct\">\$1</span>",
-			$type_env, "<span class=\"env\">\$1</span>",
-			$type_param, "<span class=\"param\">\$1</span>" );
-my $blankline_html5 = $local_lt . "br /" . $local_gt;
-
-# XML, docbook format
-my %highlights_xml = ( "([^=])\\\"([^\\\"<]+)\\\"", "\$1<quote>\$2</quote>",
-			$type_constant, "<constant>\$1</constant>",
-			$type_func, "<function>\$1</function>",
-			$type_struct_xml, "<structname>\$1</structname>",
-			$type_env, "<envar>\$1</envar>",
-			$type_param, "<parameter>\$1</parameter>" );
-my $blankline_xml = $local_lt . "/para" . $local_gt . $local_lt . "para" . $local_gt . "\n";
-
-# gnome, docbook format
-my %highlights_gnome = ( $type_constant, "<replaceable class=\"option\">\$1</replaceable>",
-			 $type_func, "<function>\$1</function>",
-			 $type_struct, "<structname>\$1</structname>",
-			 $type_env, "<envar>\$1</envar>",
-			 $type_param, "<parameter>\$1</parameter>" );
-my $blankline_gnome = "</para><para>\n";
-
-# these are pretty rough
-my %highlights_man = ( $type_constant, "\$1",
-		       $type_func, "\\\\fB\$1\\\\fP",
-		       $type_struct, "\\\\fI\$1\\\\fP",
-		       $type_param, "\\\\fI\$1\\\\fP" );
-my $blankline_man = "";
-
-# text-mode
-my %highlights_text = ( $type_constant, "\$1",
-			$type_func, "\$1",
-			$type_struct, "\$1",
-			$type_param, "\$1" );
-my $blankline_text = "";
-
-# list mode
-my %highlights_list = ( $type_constant, "\$1",
-			$type_func, "\$1",
-			$type_struct, "\$1",
-			$type_param, "\$1" );
-my $blankline_list = "";
-
-# read arguments
-if ($#ARGV == -1) {
-    usage();
-}
-
-my $kernelversion;
-my $dohighlight = "";
-
-my $verbose = 0;
-my $output_mode = "man";
-my $no_doc_sections = 0;
-my %highlights = %highlights_man;
-my $blankline = $blankline_man;
-my $modulename = "Bootloader API";
-my $function_only = 0;
-my $man_date = ('January', 'February', 'March', 'April', 'May', 'June',
-		'July', 'August', 'September', 'October',
-		'November', 'December')[(localtime)[4]] .
-  " " . ((localtime)[5]+1900);
-
-# Essentially these are globals.
-# They probably want to be tidied up, made more localised or something.
-# CAVEAT EMPTOR!  Some of the others I localised may not want to be, which
-# could cause "use of undefined value" or other bugs.
-my ($function, %function_table, %parametertypes, $declaration_purpose);
-my ($type, $declaration_name, $return_type);
-my ($newsection, $newcontents, $prototype, $brcount, %source_map);
-
-if (defined($ENV{'KBUILD_VERBOSE'})) {
-	$verbose = "$ENV{'KBUILD_VERBOSE'}";
-}
-
-# Generated docbook code is inserted in a template at a point where
-# docbook v3.1 requires a non-zero sequence of RefEntry's; see:
-# http://www.oasis-open.org/docbook/documentation/reference/html/refentry.html
-# We keep track of number of generated entries and generate a dummy
-# if needs be to ensure the expanded template can be postprocessed
-# into html.
-my $section_counter = 0;
-
-my $lineprefix="";
-
-# states
-# 0 - normal code
-# 1 - looking for function name
-# 2 - scanning field start.
-# 3 - scanning prototype.
-# 4 - documentation block
-my $state;
-my $in_doc_sect;
-
-#declaration types: can be
-# 'function', 'struct', 'union', 'enum', 'typedef'
-my $decl_type;
-
-my $doc_special = "\@\%\$\&";
-
-my $doc_start = '^/\*\*\s*$'; # Allow whitespace at end of comment start.
-my $doc_end = '\*/';
-my $doc_com = '\s*\*\s*';
-my $doc_decl = $doc_com . '(\w+)';
-my $doc_sect = $doc_com . '([' . $doc_special . ']?[\w\s]+):(.*)';
-my $doc_content = $doc_com . '(.*)';
-my $doc_block = $doc_com . 'DOC:\s*(.*)?';
-
-my %constants;
-my %parameterdescs;
-my @parameterlist;
-my %sections;
-my @sectionlist;
-my $sectcheck;
-my $struct_actual;
-
-my $contents = "";
-my $section_default = "Description";	# default section
-my $section_intro = "Introduction";
-my $section = $section_default;
-my $section_context = "Context";
-
-my $undescribed = "-- undescribed --";
-
-reset_state();
-
-while ($ARGV[0] =~ m/^-(.*)/) {
-    my $cmd = shift @ARGV;
-    if ($cmd eq "-html") {
-	$output_mode = "html";
-	%highlights = %highlights_html;
-	$blankline = $blankline_html;
-    } elsif ($cmd eq "-html5") {
-	$output_mode = "html5";
-	%highlights = %highlights_html5;
-	$blankline = $blankline_html5;
-    } elsif ($cmd eq "-man") {
-	$output_mode = "man";
-	%highlights = %highlights_man;
-	$blankline = $blankline_man;
-    } elsif ($cmd eq "-text") {
-	$output_mode = "text";
-	%highlights = %highlights_text;
-	$blankline = $blankline_text;
-    } elsif ($cmd eq "-docbook") {
-	$output_mode = "xml";
-	%highlights = %highlights_xml;
-	$blankline = $blankline_xml;
-    } elsif ($cmd eq "-list") {
-	$output_mode = "list";
-	%highlights = %highlights_list;
-	$blankline = $blankline_list;
-    } elsif ($cmd eq "-gnome") {
-	$output_mode = "gnome";
-	%highlights = %highlights_gnome;
-	$blankline = $blankline_gnome;
-    } elsif ($cmd eq "-module") { # not needed for XML, inherits from calling document
-	$modulename = shift @ARGV;
-    } elsif ($cmd eq "-function") { # to only output specific functions
-	$function_only = 1;
-	$function = shift @ARGV;
-	$function_table{$function} = 1;
-    } elsif ($cmd eq "-nofunction") { # to only output specific functions
-	$function_only = 2;
-	$function = shift @ARGV;
-	$function_table{$function} = 1;
-    } elsif ($cmd eq "-v") {
-	$verbose = 1;
-    } elsif (($cmd eq "-h") || ($cmd eq "--help")) {
-	usage();
-    } elsif ($cmd eq '-no-doc-sections') {
-	    $no_doc_sections = 1;
-    }
-}
-
-# continue execution near EOF;
-
-sub usage {
-    print "Usage: $0 [ -docbook | -html | -html5 | -text | -man | -list ]\n";
-    print "         [ -no-doc-sections ]\n";
-    print "         [ -function funcname [ -function funcname ...] ]\n";
-    print "         [ -nofunction funcname [ -nofunction funcname ...] ]\n";
-    print "         [ -v ]\n";
-    print "         c source file(s) > outputfile\n";
-    print "         -v : verbose output, more warnings & other info listed\n";
-    exit 1;
-}
-
-# get kernel version from env
-sub get_kernel_version() {
-    my $version = 'unknown kernel version';
-
-    if (defined($ENV{'U_BOOT_VERSION'})) {
-	$version = $ENV{'U_BOOT_VERSION'};
-    }
-    return $version;
-}
-
-##
-# dumps section contents to arrays/hashes intended for that purpose.
-#
-sub dump_section {
-    my $file = shift;
-    my $name = shift;
-    my $contents = join "\n", @_;
-
-    if ($name =~ m/$type_constant/) {
-	$name = $1;
-#	print STDERR "constant section '$1' = '$contents'\n";
-	$constants{$name} = $contents;
-    } elsif ($name =~ m/$type_param/) {
-#	print STDERR "parameter def '$1' = '$contents'\n";
-	$name = $1;
-	$parameterdescs{$name} = $contents;
-	$sectcheck = $sectcheck . $name . " ";
-    } elsif ($name eq "@\.\.\.") {
-#	print STDERR "parameter def '...' = '$contents'\n";
-	$name = "...";
-	$parameterdescs{$name} = $contents;
-	$sectcheck = $sectcheck . $name . " ";
-    } else {
-#	print STDERR "other section '$name' = '$contents'\n";
-	if (defined($sections{$name}) && ($sections{$name} ne "")) {
-		print STDERR "Error(${file}:$.): duplicate section name '$name'\n";
-		++$errors;
-	}
-	$sections{$name} = $contents;
-	push @sectionlist, $name;
-    }
-}
-
-##
-# dump DOC: section after checking that it should go out
-#
-sub dump_doc_section {
-    my $file = shift;
-    my $name = shift;
-    my $contents = join "\n", @_;
-
-    if ($no_doc_sections) {
-	return;
-    }
-
-    if (($function_only == 0) ||
-	( $function_only == 1 && defined($function_table{$name})) ||
-	( $function_only == 2 && !defined($function_table{$name})))
-    {
-	dump_section($file, $name, $contents);
-	output_blockhead({'sectionlist' => \@sectionlist,
-			  'sections' => \%sections,
-			  'module' => $modulename,
-			  'content-only' => ($function_only != 0), });
-    }
-}
-
-##
-# output function
-#
-# parameterdescs, a hash.
-#  function => "function name"
-#  parameterlist => @list of parameters
-#  parameterdescs => %parameter descriptions
-#  sectionlist => @list of sections
-#  sections => %section descriptions
-#
-
-sub output_highlight {
-    my $contents = join "\n",@_;
-    my $line;
-
-#   DEBUG
-#   if (!defined $contents) {
-#	use Carp;
-#	confess "output_highlight got called with no args?\n";
-#   }
-
-    if ($output_mode eq "html" || $output_mode eq "html5" ||
-	$output_mode eq "xml") {
-	$contents = local_unescape($contents);
-	# convert data read & converted thru xml_escape() into &xyz; format:
-	$contents =~ s/\\\\\\/\&/g;
-    }
-#   print STDERR "contents b4:$contents\n";
-    eval $dohighlight;
-    die $@ if $@;
-#   print STDERR "contents af:$contents\n";
-
-#   strip whitespaces when generating html5
-    if ($output_mode eq "html5") {
-	$contents =~ s/^\s+//;
-	$contents =~ s/\s+$//;
-    }
-    foreach $line (split "\n", $contents) {
-	if ($line eq ""){
-	    print $lineprefix, local_unescape($blankline);
-	} else {
-	    $line =~ s/\\\\\\/\&/g;
-	    if ($output_mode eq "man" && substr($line, 0, 1) eq ".") {
-		print "\\&$line";
-	    } else {
-		print $lineprefix, $line;
-	    }
-	}
-	print "\n";
-    }
-}
-
-# output sections in html
-sub output_section_html(%) {
-    my %args = %{$_[0]};
-    my $section;
-
-    foreach $section (@{$args{'sectionlist'}}) {
-	print "<h3>$section</h3>\n";
-	print "<blockquote>\n";
-	output_highlight($args{'sections'}{$section});
-	print "</blockquote>\n";
-    }
-}
-
-# output enum in html
-sub output_enum_html(%) {
-    my %args = %{$_[0]};
-    my ($parameter);
-    my $count;
-    print "<h2>enum " . $args{'enum'} . "</h2>\n";
-
-    print "<b>enum " . $args{'enum'} . "</b> {<br>\n";
-    $count = 0;
-    foreach $parameter (@{$args{'parameterlist'}}) {
-	print " <b>" . $parameter . "</b>";
-	if ($count != $#{$args{'parameterlist'}}) {
-	    $count++;
-	    print ",\n";
-	}
-	print "<br>";
-    }
-    print "};<br>\n";
-
-    print "<h3>Constants</h3>\n";
-    print "<dl>\n";
-    foreach $parameter (@{$args{'parameterlist'}}) {
-	print "<dt><b>" . $parameter . "</b>\n";
-	print "<dd>";
-	output_highlight($args{'parameterdescs'}{$parameter});
-    }
-    print "</dl>\n";
-    output_section_html(@_);
-    print "<hr>\n";
-}
-
-# output typedef in html
-sub output_typedef_html(%) {
-    my %args = %{$_[0]};
-    my ($parameter);
-    my $count;
-    print "<h2>typedef " . $args{'typedef'} . "</h2>\n";
-
-    print "<b>typedef " . $args{'typedef'} . "</b>\n";
-    output_section_html(@_);
-    print "<hr>\n";
-}
-
-# output struct in html
-sub output_struct_html(%) {
-    my %args = %{$_[0]};
-    my ($parameter);
-
-    print "<h2>" . $args{'type'} . " " . $args{'struct'} . " - " . $args{'purpose'} . "</h2>\n";
-    print "<b>" . $args{'type'} . " " . $args{'struct'} . "</b> {<br>\n";
-    foreach $parameter (@{$args{'parameterlist'}}) {
-	if ($parameter =~ /^#/) {
-		print "$parameter<br>\n";
-		next;
-	}
-	my $parameter_name = $parameter;
-	$parameter_name =~ s/\[.*//;
-
-	($args{'parameterdescs'}{$parameter_name} ne $undescribed) || next;
-	$type = $args{'parametertypes'}{$parameter};
-	if ($type =~ m/([^\(]*\(\*)\s*\)\s*\(([^\)]*)\)/) {
-	    # pointer-to-function
-	    print "&nbsp; &nbsp; <i>$1</i><b>$parameter</b>) <i>($2)</i>;<br>\n";
-	} elsif ($type =~ m/^(.*?)\s*(:.*)/) {
-	    # bitfield
-	    print "&nbsp; &nbsp; <i>$1</i> <b>$parameter</b>$2;<br>\n";
-	} else {
-	    print "&nbsp; &nbsp; <i>$type</i> <b>$parameter</b>;<br>\n";
-	}
-    }
-    print "};<br>\n";
-
-    print "<h3>Members</h3>\n";
-    print "<dl>\n";
-    foreach $parameter (@{$args{'parameterlist'}}) {
-	($parameter =~ /^#/) && next;
-
-	my $parameter_name = $parameter;
-	$parameter_name =~ s/\[.*//;
-
-	($args{'parameterdescs'}{$parameter_name} ne $undescribed) || next;
-	print "<dt><b>" . $parameter . "</b>\n";
-	print "<dd>";
-	output_highlight($args{'parameterdescs'}{$parameter_name});
-    }
-    print "</dl>\n";
-    output_section_html(@_);
-    print "<hr>\n";
-}
-
-# output function in html
-sub output_function_html(%) {
-    my %args = %{$_[0]};
-    my ($parameter, $section);
-    my $count;
-
-    print "<h2>" . $args{'function'} . " - " . $args{'purpose'} . "</h2>\n";
-    print "<i>" . $args{'functiontype'} . "</i>\n";
-    print "<b>" . $args{'function'} . "</b>\n";
-    print "(";
-    $count = 0;
-    foreach $parameter (@{$args{'parameterlist'}}) {
-	$type = $args{'parametertypes'}{$parameter};
-	if ($type =~ m/([^\(]*\(\*)\s*\)\s*\(([^\)]*)\)/) {
-	    # pointer-to-function
-	    print "<i>$1</i><b>$parameter</b>) <i>($2)</i>";
-	} else {
-	    print "<i>" . $type . "</i> <b>" . $parameter . "</b>";
-	}
-	if ($count != $#{$args{'parameterlist'}}) {
-	    $count++;
-	    print ",\n";
-	}
-    }
-    print ")\n";
-
-    print "<h3>Arguments</h3>\n";
-    print "<dl>\n";
-    foreach $parameter (@{$args{'parameterlist'}}) {
-	my $parameter_name = $parameter;
-	$parameter_name =~ s/\[.*//;
-
-	($args{'parameterdescs'}{$parameter_name} ne $undescribed) || next;
-	print "<dt><b>" . $parameter . "</b>\n";
-	print "<dd>";
-	output_highlight($args{'parameterdescs'}{$parameter_name});
-    }
-    print "</dl>\n";
-    output_section_html(@_);
-    print "<hr>\n";
-}
-
-# output DOC: block header in html
-sub output_blockhead_html(%) {
-    my %args = %{$_[0]};
-    my ($parameter, $section);
-    my $count;
-
-    foreach $section (@{$args{'sectionlist'}}) {
-	print "<h3>$section</h3>\n";
-	print "<ul>\n";
-	output_highlight($args{'sections'}{$section});
-	print "</ul>\n";
-    }
-    print "<hr>\n";
-}
-
-# output sections in html5
-sub output_section_html5(%) {
-    my %args = %{$_[0]};
-    my $section;
-
-    foreach $section (@{$args{'sectionlist'}}) {
-	print "<section>\n";
-	print "<h1>$section</h1>\n";
-	print "<p>\n";
-	output_highlight($args{'sections'}{$section});
-	print "</p>\n";
-	print "</section>\n";
-    }
-}
-
-# output enum in html5
-sub output_enum_html5(%) {
-    my %args = %{$_[0]};
-    my ($parameter);
-    my $count;
-    my $html5id;
-
-    $html5id = $args{'enum'};
-    $html5id =~ s/[^a-zA-Z0-9\-]+/_/g;
-    print "<article class=\"enum\" id=\"enum:". $html5id . "\">";
-    print "<h1>enum " . $args{'enum'} . "</h1>\n";
-    print "<ol class=\"code\">\n";
-    print "<li>";
-    print "<span class=\"keyword\">enum</span> ";
-    print "<span class=\"identifier\">" . $args{'enum'} . "</span> {";
-    print "</li>\n";
-    $count = 0;
-    foreach $parameter (@{$args{'parameterlist'}}) {
-	print "<li class=\"indent\">";
-	print "<span class=\"param\">" . $parameter . "</span>";
-	if ($count != $#{$args{'parameterlist'}}) {
-	    $count++;
-	    print ",";
-	}
-	print "</li>\n";
-    }
-    print "<li>};</li>\n";
-    print "</ol>\n";
-
-    print "<section>\n";
-    print "<h1>Constants</h1>\n";
-    print "<dl>\n";
-    foreach $parameter (@{$args{'parameterlist'}}) {
-	print "<dt>" . $parameter . "</dt>\n";
-	print "<dd>";
-	output_highlight($args{'parameterdescs'}{$parameter});
-	print "</dd>\n";
-    }
-    print "</dl>\n";
-    print "</section>\n";
-    output_section_html5(@_);
-    print "</article>\n";
-}
-
-# output typedef in html5
-sub output_typedef_html5(%) {
-    my %args = %{$_[0]};
-    my ($parameter);
-    my $count;
-    my $html5id;
-
-    $html5id = $args{'typedef'};
-    $html5id =~ s/[^a-zA-Z0-9\-]+/_/g;
-    print "<article class=\"typedef\" id=\"typedef:" . $html5id . "\">\n";
-    print "<h1>typedef " . $args{'typedef'} . "</h1>\n";
-
-    print "<ol class=\"code\">\n";
-    print "<li>";
-    print "<span class=\"keyword\">typedef</span> ";
-    print "<span class=\"identifier\">" . $args{'typedef'} . "</span>";
-    print "</li>\n";
-    print "</ol>\n";
-    output_section_html5(@_);
-    print "</article>\n";
-}
-
-# output struct in html5
-sub output_struct_html5(%) {
-    my %args = %{$_[0]};
-    my ($parameter);
-    my $html5id;
-
-    $html5id = $args{'struct'};
-    $html5id =~ s/[^a-zA-Z0-9\-]+/_/g;
-    print "<article class=\"struct\" id=\"struct:" . $html5id . "\">\n";
-    print "<hgroup>\n";
-    print "<h1>" . $args{'type'} . " " . $args{'struct'} . "</h1>";
-    print "<h2>". $args{'purpose'} . "</h2>\n";
-    print "</hgroup>\n";
-    print "<ol class=\"code\">\n";
-    print "<li>";
-    print "<span class=\"type\">" . $args{'type'} . "</span> ";
-    print "<span class=\"identifier\">" . $args{'struct'} . "</span> {";
-    print "</li>\n";
-    foreach $parameter (@{$args{'parameterlist'}}) {
-	print "<li class=\"indent\">";
-	if ($parameter =~ /^#/) {
-		print "<span class=\"param\">" . $parameter ."</span>\n";
-		print "</li>\n";
-		next;
-	}
-	my $parameter_name = $parameter;
-	$parameter_name =~ s/\[.*//;
-
-	($args{'parameterdescs'}{$parameter_name} ne $undescribed) || next;
-	$type = $args{'parametertypes'}{$parameter};
-	if ($type =~ m/([^\(]*\(\*)\s*\)\s*\(([^\)]*)\)/) {
-	    # pointer-to-function
-	    print "<span class=\"type\">$1</span> ";
-	    print "<span class=\"param\">$parameter</span>";
-	    print "<span class=\"type\">)</span> ";
-	    print "(<span class=\"args\">$2</span>);";
-	} elsif ($type =~ m/^(.*?)\s*(:.*)/) {
-	    # bitfield
-	    print "<span class=\"type\">$1</span> ";
-	    print "<span class=\"param\">$parameter</span>";
-	    print "<span class=\"bits\">$2</span>;";
-	} else {
-	    print "<span class=\"type\">$type</span> ";
-	    print "<span class=\"param\">$parameter</span>;";
-	}
-	print "</li>\n";
-    }
-    print "<li>};</li>\n";
-    print "</ol>\n";
-
-    print "<section>\n";
-    print "<h1>Members</h1>\n";
-    print "<dl>\n";
-    foreach $parameter (@{$args{'parameterlist'}}) {
-	($parameter =~ /^#/) && next;
-
-	my $parameter_name = $parameter;
-	$parameter_name =~ s/\[.*//;
-
-	($args{'parameterdescs'}{$parameter_name} ne $undescribed) || next;
-	print "<dt>" . $parameter . "</dt>\n";
-	print "<dd>";
-	output_highlight($args{'parameterdescs'}{$parameter_name});
-	print "</dd>\n";
-    }
-    print "</dl>\n";
-    print "</section>\n";
-    output_section_html5(@_);
-    print "</article>\n";
-}
-
-# output function in html5
-sub output_function_html5(%) {
-    my %args = %{$_[0]};
-    my ($parameter, $section);
-    my $count;
-    my $html5id;
-
-    $html5id = $args{'function'};
-    $html5id =~ s/[^a-zA-Z0-9\-]+/_/g;
-    print "<article class=\"function\" id=\"func:". $html5id . "\">\n";
-    print "<hgroup>\n";
-    print "<h1>" . $args{'function'} . "</h1>";
-    print "<h2>" . $args{'purpose'} . "</h2>\n";
-    print "</hgroup>\n";
-    print "<ol class=\"code\">\n";
-    print "<li>";
-    print "<span class=\"type\">" . $args{'functiontype'} . "</span> ";
-    print "<span class=\"identifier\">" . $args{'function'} . "</span> (";
-    print "</li>";
-    $count = 0;
-    foreach $parameter (@{$args{'parameterlist'}}) {
-	print "<li class=\"indent\">";
-	$type = $args{'parametertypes'}{$parameter};
-	if ($type =~ m/([^\(]*\(\*)\s*\)\s*\(([^\)]*)\)/) {
-	    # pointer-to-function
-	    print "<span class=\"type\">$1</span> ";
-	    print "<span class=\"param\">$parameter</span>";
-	    print "<span class=\"type\">)</span> ";
-	    print "(<span class=\"args\">$2</span>)";
-	} else {
-	    print "<span class=\"type\">$type</span> ";
-	    print "<span class=\"param\">$parameter</span>";
-	}
-	if ($count != $#{$args{'parameterlist'}}) {
-	    $count++;
-	    print ",";
-	}
-	print "</li>\n";
-    }
-    print "<li>)</li>\n";
-    print "</ol>\n";
-
-    print "<section>\n";
-    print "<h1>Arguments</h1>\n";
-    print "<p>\n";
-    print "<dl>\n";
-    foreach $parameter (@{$args{'parameterlist'}}) {
-	my $parameter_name = $parameter;
-	$parameter_name =~ s/\[.*//;
-
-	($args{'parameterdescs'}{$parameter_name} ne $undescribed) || next;
-	print "<dt>" . $parameter . "</dt>\n";
-	print "<dd>";
-	output_highlight($args{'parameterdescs'}{$parameter_name});
-	print "</dd>\n";
-    }
-    print "</dl>\n";
-    print "</section>\n";
-    output_section_html5(@_);
-    print "</article>\n";
-}
-
-# output DOC: block header in html5
-sub output_blockhead_html5(%) {
-    my %args = %{$_[0]};
-    my ($parameter, $section);
-    my $count;
-    my $html5id;
-
-    foreach $section (@{$args{'sectionlist'}}) {
-	$html5id = $section;
-	$html5id =~ s/[^a-zA-Z0-9\-]+/_/g;
-	print "<article class=\"doc\" id=\"doc:". $html5id . "\">\n";
-	print "<h1>$section</h1>\n";
-	print "<p>\n";
-	output_highlight($args{'sections'}{$section});
-	print "</p>\n";
-    }
-    print "</article>\n";
-}
-
-sub output_section_xml(%) {
-    my %args = %{$_[0]};
-    my $section;
-    # print out each section
-    $lineprefix="   ";
-    foreach $section (@{$args{'sectionlist'}}) {
-	print "<refsect1>\n";
-	print "<title>$section</title>\n";
-	if ($section =~ m/EXAMPLE/i) {
-	    print "<informalexample><programlisting>\n";
-	} else {
-	    print "<para>\n";
-	}
-	output_highlight($args{'sections'}{$section});
-	if ($section =~ m/EXAMPLE/i) {
-	    print "</programlisting></informalexample>\n";
-	} else {
-	    print "</para>\n";
-	}
-	print "</refsect1>\n";
-    }
-}
-
-# output function in XML DocBook
-sub output_function_xml(%) {
-    my %args = %{$_[0]};
-    my ($parameter, $section);
-    my $count;
-    my $id;
-
-    $id = "API-" . $args{'function'};
-    $id =~ s/[^A-Za-z0-9]/-/g;
-
-    print "<refentry id=\"$id\">\n";
-    print "<refentryinfo>\n";
-    print " <title>U-BOOT</title>\n";
-    print " <productname>Bootloader Hackers Manual</productname>\n";
-    print " <date>$man_date</date>\n";
-    print "</refentryinfo>\n";
-    print "<refmeta>\n";
-    print " <refentrytitle><phrase>" . $args{'function'} . "</phrase></refentrytitle>\n";
-    print " <manvolnum>9</manvolnum>\n";
-    print " <refmiscinfo class=\"version\">" . $kernelversion . "</refmiscinfo>\n";
-    print "</refmeta>\n";
-    print "<refnamediv>\n";
-    print " <refname>" . $args{'function'} . "</refname>\n";
-    print " <refpurpose>\n";
-    print "  ";
-    output_highlight ($args{'purpose'});
-    print " </refpurpose>\n";
-    print "</refnamediv>\n";
-
-    print "<refsynopsisdiv>\n";
-    print " <title>Synopsis</title>\n";
-    print "  <funcsynopsis><funcprototype>\n";
-    print "   <funcdef>" . $args{'functiontype'} . " ";
-    print "<function>" . $args{'function'} . " </function></funcdef>\n";
-
-    $count = 0;
-    if ($#{$args{'parameterlist'}} >= 0) {
-	foreach $parameter (@{$args{'parameterlist'}}) {
-	    $type = $args{'parametertypes'}{$parameter};
-	    if ($type =~ m/([^\(]*\(\*)\s*\)\s*\(([^\)]*)\)/) {
-		# pointer-to-function
-		print "   <paramdef>$1<parameter>$parameter</parameter>)\n";
-		print "     <funcparams>$2</funcparams></paramdef>\n";
-	    } else {
-		print "   <paramdef>" . $type;
-		print " <parameter>$parameter</parameter></paramdef>\n";
-	    }
-	}
-    } else {
-	print "  <void/>\n";
-    }
-    print "  </funcprototype></funcsynopsis>\n";
-    print "</refsynopsisdiv>\n";
-
-    # print parameters
-    print "<refsect1>\n <title>Arguments</title>\n";
-    if ($#{$args{'parameterlist'}} >= 0) {
-	print " <variablelist>\n";
-	foreach $parameter (@{$args{'parameterlist'}}) {
-	    my $parameter_name = $parameter;
-	    $parameter_name =~ s/\[.*//;
-
-	    print "  <varlistentry>\n   <term><parameter>$parameter</parameter></term>\n";
-	    print "   <listitem>\n    <para>\n";
-	    $lineprefix="     ";
-	    output_highlight($args{'parameterdescs'}{$parameter_name});
-	    print "    </para>\n   </listitem>\n  </varlistentry>\n";
-	}
-	print " </variablelist>\n";
-    } else {
-	print " <para>\n  None\n </para>\n";
-    }
-    print "</refsect1>\n";
-
-    output_section_xml(@_);
-    print "</refentry>\n\n";
-}
-
-# output struct in XML DocBook
-sub output_struct_xml(%) {
-    my %args = %{$_[0]};
-    my ($parameter, $section);
-    my $id;
-
-    $id = "API-struct-" . $args{'struct'};
-    $id =~ s/[^A-Za-z0-9]/-/g;
-
-    print "<refentry id=\"$id\">\n";
-    print "<refentryinfo>\n";
-    print " <title>U-BOOT</title>\n";
-    print " <productname>Bootloader Hackers Manual</productname>\n";
-    print " <date>$man_date</date>\n";
-    print "</refentryinfo>\n";
-    print "<refmeta>\n";
-    print " <refentrytitle><phrase>" . $args{'type'} . " " . $args{'struct'} . "</phrase></refentrytitle>\n";
-    print " <manvolnum>9</manvolnum>\n";
-    print " <refmiscinfo class=\"version\">" . $kernelversion . "</refmiscinfo>\n";
-    print "</refmeta>\n";
-    print "<refnamediv>\n";
-    print " <refname>" . $args{'type'} . " " . $args{'struct'} . "</refname>\n";
-    print " <refpurpose>\n";
-    print "  ";
-    output_highlight ($args{'purpose'});
-    print " </refpurpose>\n";
-    print "</refnamediv>\n";
-
-    print "<refsynopsisdiv>\n";
-    print " <title>Synopsis</title>\n";
-    print "  <programlisting>\n";
-    print $args{'type'} . " " . $args{'struct'} . " {\n";
-    foreach $parameter (@{$args{'parameterlist'}}) {
-	if ($parameter =~ /^#/) {
-	    my $prm = $parameter;
-	    # convert data read & converted thru xml_escape() into &xyz; format:
-	    # This allows us to have #define macros interspersed in a struct.
-	    $prm =~ s/\\\\\\/\&/g;
-	    print "$prm\n";
-	    next;
-	}
-
-	my $parameter_name = $parameter;
-	$parameter_name =~ s/\[.*//;
-
-	defined($args{'parameterdescs'}{$parameter_name}) || next;
-	($args{'parameterdescs'}{$parameter_name} ne $undescribed) || next;
-	$type = $args{'parametertypes'}{$parameter};
-	if ($type =~ m/([^\(]*\(\*)\s*\)\s*\(([^\)]*)\)/) {
-	    # pointer-to-function
-	    print "  $1 $parameter) ($2);\n";
-	} elsif ($type =~ m/^(.*?)\s*(:.*)/) {
-	    # bitfield
-	    print "  $1 $parameter$2;\n";
-	} else {
-	    print "  " . $type . " " . $parameter . ";\n";
-	}
-    }
-    print "};";
-    print "  </programlisting>\n";
-    print "</refsynopsisdiv>\n";
-
-    print " <refsect1>\n";
-    print "  <title>Members</title>\n";
-
-    if ($#{$args{'parameterlist'}} >= 0) {
-    print "  <variablelist>\n";
-    foreach $parameter (@{$args{'parameterlist'}}) {
-      ($parameter =~ /^#/) && next;
-
-      my $parameter_name = $parameter;
-      $parameter_name =~ s/\[.*//;
-
-      defined($args{'parameterdescs'}{$parameter_name}) || next;
-      ($args{'parameterdescs'}{$parameter_name} ne $undescribed) || next;
-      print "    <varlistentry>";
-      print "      <term>$parameter</term>\n";
-      print "      <listitem><para>\n";
-      output_highlight($args{'parameterdescs'}{$parameter_name});
-      print "      </para></listitem>\n";
-      print "    </varlistentry>\n";
-    }
-    print "  </variablelist>\n";
-    } else {
-	print " <para>\n  None\n </para>\n";
-    }
-    print " </refsect1>\n";
-
-    output_section_xml(@_);
-
-    print "</refentry>\n\n";
-}
-
-# output enum in XML DocBook
-sub output_enum_xml(%) {
-    my %args = %{$_[0]};
-    my ($parameter, $section);
-    my $count;
-    my $id;
-
-    $id = "API-enum-" . $args{'enum'};
-    $id =~ s/[^A-Za-z0-9]/-/g;
-
-    print "<refentry id=\"$id\">\n";
-    print "<refentryinfo>\n";
-    print " <title>U-BOOT</title>\n";
-    print " <productname>Bootloader Hackers Manual</productname>\n";
-    print " <date>$man_date</date>\n";
-    print "</refentryinfo>\n";
-    print "<refmeta>\n";
-    print " <refentrytitle><phrase>enum " . $args{'enum'} . "</phrase></refentrytitle>\n";
-    print " <manvolnum>9</manvolnum>\n";
-    print " <refmiscinfo class=\"version\">" . $kernelversion . "</refmiscinfo>\n";
-    print "</refmeta>\n";
-    print "<refnamediv>\n";
-    print " <refname>enum " . $args{'enum'} . "</refname>\n";
-    print " <refpurpose>\n";
-    print "  ";
-    output_highlight ($args{'purpose'});
-    print " </refpurpose>\n";
-    print "</refnamediv>\n";
-
-    print "<refsynopsisdiv>\n";
-    print " <title>Synopsis</title>\n";
-    print "  <programlisting>\n";
-    print "enum " . $args{'enum'} . " {\n";
-    $count = 0;
-    foreach $parameter (@{$args{'parameterlist'}}) {
-	print "  $parameter";
-	if ($count != $#{$args{'parameterlist'}}) {
-	    $count++;
-	    print ",";
-	}
-	print "\n";
-    }
-    print "};";
-    print "  </programlisting>\n";
-    print "</refsynopsisdiv>\n";
-
-    print "<refsect1>\n";
-    print " <title>Constants</title>\n";
-    print "  <variablelist>\n";
-    foreach $parameter (@{$args{'parameterlist'}}) {
-      my $parameter_name = $parameter;
-      $parameter_name =~ s/\[.*//;
-
-      print "    <varlistentry>";
-      print "      <term>$parameter</term>\n";
-      print "      <listitem><para>\n";
-      output_highlight($args{'parameterdescs'}{$parameter_name});
-      print "      </para></listitem>\n";
-      print "    </varlistentry>\n";
-    }
-    print "  </variablelist>\n";
-    print "</refsect1>\n";
-
-    output_section_xml(@_);
-
-    print "</refentry>\n\n";
-}
-
-# output typedef in XML DocBook
-sub output_typedef_xml(%) {
-    my %args = %{$_[0]};
-    my ($parameter, $section);
-    my $id;
-
-    $id = "API-typedef-" . $args{'typedef'};
-    $id =~ s/[^A-Za-z0-9]/-/g;
-
-    print "<refentry id=\"$id\">\n";
-    print "<refentryinfo>\n";
-    print " <title>U-BOOT</title>\n";
-    print " <productname>Bootloader Hackers Manual</productname>\n";
-    print " <date>$man_date</date>\n";
-    print "</refentryinfo>\n";
-    print "<refmeta>\n";
-    print " <refentrytitle><phrase>typedef " . $args{'typedef'} . "</phrase></refentrytitle>\n";
-    print " <manvolnum>9</manvolnum>\n";
-    print "</refmeta>\n";
-    print "<refnamediv>\n";
-    print " <refname>typedef " . $args{'typedef'} . "</refname>\n";
-    print " <refpurpose>\n";
-    print "  ";
-    output_highlight ($args{'purpose'});
-    print " </refpurpose>\n";
-    print "</refnamediv>\n";
-
-    print "<refsynopsisdiv>\n";
-    print " <title>Synopsis</title>\n";
-    print "  <synopsis>typedef " . $args{'typedef'} . ";</synopsis>\n";
-    print "</refsynopsisdiv>\n";
-
-    output_section_xml(@_);
-
-    print "</refentry>\n\n";
-}
-
-# output in XML DocBook
-sub output_blockhead_xml(%) {
-    my %args = %{$_[0]};
-    my ($parameter, $section);
-    my $count;
-
-    my $id = $args{'module'};
-    $id =~ s/[^A-Za-z0-9]/-/g;
-
-    # print out each section
-    $lineprefix="   ";
-    foreach $section (@{$args{'sectionlist'}}) {
-	if (!$args{'content-only'}) {
-		print "<refsect1>\n <title>$section</title>\n";
-	}
-	if ($section =~ m/EXAMPLE/i) {
-	    print "<example><para>\n";
-	} else {
-	    print "<para>\n";
-	}
-	output_highlight($args{'sections'}{$section});
-	if ($section =~ m/EXAMPLE/i) {
-	    print "</para></example>\n";
-	} else {
-	    print "</para>";
-	}
-	if (!$args{'content-only'}) {
-		print "\n</refsect1>\n";
-	}
-    }
-
-    print "\n\n";
-}
-
-# output in XML DocBook
-sub output_function_gnome {
-    my %args = %{$_[0]};
-    my ($parameter, $section);
-    my $count;
-    my $id;
-
-    $id = $args{'module'} . "-" . $args{'function'};
-    $id =~ s/[^A-Za-z0-9]/-/g;
-
-    print "<sect2>\n";
-    print " <title id=\"$id\">" . $args{'function'} . "</title>\n";
-
-    print "  <funcsynopsis>\n";
-    print "   <funcdef>" . $args{'functiontype'} . " ";
-    print "<function>" . $args{'function'} . " ";
-    print "</function></funcdef>\n";
-
-    $count = 0;
-    if ($#{$args{'parameterlist'}} >= 0) {
-	foreach $parameter (@{$args{'parameterlist'}}) {
-	    $type = $args{'parametertypes'}{$parameter};
-	    if ($type =~ m/([^\(]*\(\*)\s*\)\s*\(([^\)]*)\)/) {
-		# pointer-to-function
-		print "   <paramdef>$1 <parameter>$parameter</parameter>)\n";
-		print "     <funcparams>$2</funcparams></paramdef>\n";
-	    } else {
-		print "   <paramdef>" . $type;
-		print " <parameter>$parameter</parameter></paramdef>\n";
-	    }
-	}
-    } else {
-	print "  <void>\n";
-    }
-    print "  </funcsynopsis>\n";
-    if ($#{$args{'parameterlist'}} >= 0) {
-	print " <informaltable pgwide=\"1\" frame=\"none\" role=\"params\">\n";
-	print "<tgroup cols=\"2\">\n";
-	print "<colspec colwidth=\"2*\">\n";
-	print "<colspec colwidth=\"8*\">\n";
-	print "<tbody>\n";
-	foreach $parameter (@{$args{'parameterlist'}}) {
-	    my $parameter_name = $parameter;
-	    $parameter_name =~ s/\[.*//;
-
-	    print "  <row><entry align=\"right\"><parameter>$parameter</parameter></entry>\n";
-	    print "   <entry>\n";
-	    $lineprefix="     ";
-	    output_highlight($args{'parameterdescs'}{$parameter_name});
-	    print "    </entry></row>\n";
-	}
-	print " </tbody></tgroup></informaltable>\n";
-    } else {
-	print " <para>\n  None\n </para>\n";
-    }
-
-    # print out each section
-    $lineprefix="   ";
-    foreach $section (@{$args{'sectionlist'}}) {
-	print "<simplesect>\n <title>$section</title>\n";
-	if ($section =~ m/EXAMPLE/i) {
-	    print "<example><programlisting>\n";
-	} else {
-	}
-	print "<para>\n";
-	output_highlight($args{'sections'}{$section});
-	print "</para>\n";
-	if ($section =~ m/EXAMPLE/i) {
-	    print "</programlisting></example>\n";
-	} else {
-	}
-	print " </simplesect>\n";
-    }
-
-    print "</sect2>\n\n";
-}
-
-##
-# output function in man
-sub output_function_man(%) {
-    my %args = %{$_[0]};
-    my ($parameter, $section);
-    my $count;
-
-    print ".TH \"$args{'function'}\" 9 \"$args{'function'}\" \"$man_date\" \"Bootloader Hacker's Manual\" U-BOOT\n";
-
-    print ".SH NAME\n";
-    print $args{'function'} . " \\- " . $args{'purpose'} . "\n";
-
-    print ".SH SYNOPSIS\n";
-    if ($args{'functiontype'} ne "") {
-	print ".B \"" . $args{'functiontype'} . "\" " . $args{'function'} . "\n";
-    } else {
-	print ".B \"" . $args{'function'} . "\n";
-    }
-    $count = 0;
-    my $parenth = "(";
-    my $post = ",";
-    foreach my $parameter (@{$args{'parameterlist'}}) {
-	if ($count == $#{$args{'parameterlist'}}) {
-	    $post = ");";
-	}
-	$type = $args{'parametertypes'}{$parameter};
-	if ($type =~ m/([^\(]*\(\*)\s*\)\s*\(([^\)]*)\)/) {
-	    # pointer-to-function
-	    print ".BI \"" . $parenth . $1 . "\" " . $parameter . " \") (" . $2 . ")" . $post . "\"\n";
-	} else {
-	    $type =~ s/([^\*])$/$1 /;
-	    print ".BI \"" . $parenth . $type . "\" " . $parameter . " \"" . $post . "\"\n";
-	}
-	$count++;
-	$parenth = "";
-    }
-
-    print ".SH ARGUMENTS\n";
-    foreach $parameter (@{$args{'parameterlist'}}) {
-	my $parameter_name = $parameter;
-	$parameter_name =~ s/\[.*//;
-
-	print ".IP \"" . $parameter . "\" 12\n";
-	output_highlight($args{'parameterdescs'}{$parameter_name});
-    }
-    foreach $section (@{$args{'sectionlist'}}) {
-	print ".SH \"", uc $section, "\"\n";
-	output_highlight($args{'sections'}{$section});
-    }
-}
-
-##
-# output enum in man
-sub output_enum_man(%) {
-    my %args = %{$_[0]};
-    my ($parameter, $section);
-    my $count;
-
-    print ".TH \"$args{'module'}\" 9 \"enum $args{'enum'}\" \"$man_date\" \"API Manual\" U-BOOT\n";
-
-    print ".SH NAME\n";
-    print "enum " . $args{'enum'} . " \\- " . $args{'purpose'} . "\n";
-
-    print ".SH SYNOPSIS\n";
-    print "enum " . $args{'enum'} . " {\n";
-    $count = 0;
-    foreach my $parameter (@{$args{'parameterlist'}}) {
-	print ".br\n.BI \"    $parameter\"\n";
-	if ($count == $#{$args{'parameterlist'}}) {
-	    print "\n};\n";
-	    last;
-	}
-	else {
-	    print ", \n.br\n";
-	}
-	$count++;
-    }
-
-    print ".SH Constants\n";
-    foreach $parameter (@{$args{'parameterlist'}}) {
-	my $parameter_name = $parameter;
-	$parameter_name =~ s/\[.*//;
-
-	print ".IP \"" . $parameter . "\" 12\n";
-	output_highlight($args{'parameterdescs'}{$parameter_name});
-    }
-    foreach $section (@{$args{'sectionlist'}}) {
-	print ".SH \"$section\"\n";
-	output_highlight($args{'sections'}{$section});
-    }
-}
-
-##
-# output struct in man
-sub output_struct_man(%) {
-    my %args = %{$_[0]};
-    my ($parameter, $section);
-
-    print ".TH \"$args{'module'}\" 9 \"" . $args{'type'} . " " . $args{'struct'} . "\" \"$man_date\" \"API Manual\" U-BOOT\n";
-
-    print ".SH NAME\n";
-    print $args{'type'} . " " . $args{'struct'} . " \\- " . $args{'purpose'} . "\n";
-
-    print ".SH SYNOPSIS\n";
-    print $args{'type'} . " " . $args{'struct'} . " {\n.br\n";
-
-    foreach my $parameter (@{$args{'parameterlist'}}) {
-	if ($parameter =~ /^#/) {
-	    print ".BI \"$parameter\"\n.br\n";
-	    next;
-	}
-	my $parameter_name = $parameter;
-	$parameter_name =~ s/\[.*//;
-
-	($args{'parameterdescs'}{$parameter_name} ne $undescribed) || next;
-	$type = $args{'parametertypes'}{$parameter};
-	if ($type =~ m/([^\(]*\(\*)\s*\)\s*\(([^\)]*)\)/) {
-	    # pointer-to-function
-	    print ".BI \"    " . $1 . "\" " . $parameter . " \") (" . $2 . ")" . "\"\n;\n";
-	} elsif ($type =~ m/^(.*?)\s*(:.*)/) {
-	    # bitfield
-	    print ".BI \"    " . $1 . "\ \" " . $parameter . $2 . " \"" . "\"\n;\n";
-	} else {
-	    $type =~ s/([^\*])$/$1 /;
-	    print ".BI \"    " . $type . "\" " . $parameter . " \"" . "\"\n;\n";
-	}
-	print "\n.br\n";
-    }
-    print "};\n.br\n";
-
-    print ".SH Members\n";
-    foreach $parameter (@{$args{'parameterlist'}}) {
-	($parameter =~ /^#/) && next;
-
-	my $parameter_name = $parameter;
-	$parameter_name =~ s/\[.*//;
-
-	($args{'parameterdescs'}{$parameter_name} ne $undescribed) || next;
-	print ".IP \"" . $parameter . "\" 12\n";
-	output_highlight($args{'parameterdescs'}{$parameter_name});
-    }
-    foreach $section (@{$args{'sectionlist'}}) {
-	print ".SH \"$section\"\n";
-	output_highlight($args{'sections'}{$section});
-    }
-}
-
-##
-# output typedef in man
-sub output_typedef_man(%) {
-    my %args = %{$_[0]};
-    my ($parameter, $section);
-
-    print ".TH \"$args{'module'}\" 9 \"$args{'typedef'}\" \"$man_date\" \"API Manual\" U-BOOT\n";
-
-    print ".SH NAME\n";
-    print "typedef " . $args{'typedef'} . " \\- " . $args{'purpose'} . "\n";
-
-    foreach $section (@{$args{'sectionlist'}}) {
-	print ".SH \"$section\"\n";
-	output_highlight($args{'sections'}{$section});
-    }
-}
-
-sub output_blockhead_man(%) {
-    my %args = %{$_[0]};
-    my ($parameter, $section);
-    my $count;
-
-    print ".TH \"$args{'module'}\" 9 \"$args{'module'}\" \"$man_date\" \"API Manual\" U-BOOT\n";
-
-    foreach $section (@{$args{'sectionlist'}}) {
-	print ".SH \"$section\"\n";
-	output_highlight($args{'sections'}{$section});
-    }
-}
-
-##
-# output in text
-sub output_function_text(%) {
-    my %args = %{$_[0]};
-    my ($parameter, $section);
-    my $start;
-
-    print "Name:\n\n";
-    print $args{'function'} . " - " . $args{'purpose'} . "\n";
-
-    print "\nSynopsis:\n\n";
-    if ($args{'functiontype'} ne "") {
-	$start = $args{'functiontype'} . " " . $args{'function'} . " (";
-    } else {
-	$start = $args{'function'} . " (";
-    }
-    print $start;
-
-    my $count = 0;
-    foreach my $parameter (@{$args{'parameterlist'}}) {
-	$type = $args{'parametertypes'}{$parameter};
-	if ($type =~ m/([^\(]*\(\*)\s*\)\s*\(([^\)]*)\)/) {
-	    # pointer-to-function
-	    print $1 . $parameter . ") (" . $2;
-	} else {
-	    print $type . " " . $parameter;
-	}
-	if ($count != $#{$args{'parameterlist'}}) {
-	    $count++;
-	    print ",\n";
-	    print " " x length($start);
-	} else {
-	    print ");\n\n";
-	}
-    }
-
-    print "Arguments:\n\n";
-    foreach $parameter (@{$args{'parameterlist'}}) {
-	my $parameter_name = $parameter;
-	$parameter_name =~ s/\[.*//;
-
-	print $parameter . "\n\t" . $args{'parameterdescs'}{$parameter_name} . "\n";
-    }
-    output_section_text(@_);
-}
-
-#output sections in text
-sub output_section_text(%) {
-    my %args = %{$_[0]};
-    my $section;
-
-    print "\n";
-    foreach $section (@{$args{'sectionlist'}}) {
-	print "$section:\n\n";
-	output_highlight($args{'sections'}{$section});
-    }
-    print "\n\n";
-}
-
-# output enum in text
-sub output_enum_text(%) {
-    my %args = %{$_[0]};
-    my ($parameter);
-    my $count;
-    print "Enum:\n\n";
-
-    print "enum " . $args{'enum'} . " - " . $args{'purpose'} . "\n\n";
-    print "enum " . $args{'enum'} . " {\n";
-    $count = 0;
-    foreach $parameter (@{$args{'parameterlist'}}) {
-	print "\t$parameter";
-	if ($count != $#{$args{'parameterlist'}}) {
-	    $count++;
-	    print ",";
-	}
-	print "\n";
-    }
-    print "};\n\n";
-
-    print "Constants:\n\n";
-    foreach $parameter (@{$args{'parameterlist'}}) {
-	print "$parameter\n\t";
-	print $args{'parameterdescs'}{$parameter} . "\n";
-    }
-
-    output_section_text(@_);
-}
-
-# output typedef in text
-sub output_typedef_text(%) {
-    my %args = %{$_[0]};
-    my ($parameter);
-    my $count;
-    print "Typedef:\n\n";
-
-    print "typedef " . $args{'typedef'} . " - " . $args{'purpose'} . "\n";
-    output_section_text(@_);
-}
-
-# output struct as text
-sub output_struct_text(%) {
-    my %args = %{$_[0]};
-    my ($parameter);
-
-    print $args{'type'} . " " . $args{'struct'} . " - " . $args{'purpose'} . "\n\n";
-    print $args{'type'} . " " . $args{'struct'} . " {\n";
-    foreach $parameter (@{$args{'parameterlist'}}) {
-	if ($parameter =~ /^#/) {
-	    print "$parameter\n";
-	    next;
-	}
-
-	my $parameter_name = $parameter;
-	$parameter_name =~ s/\[.*//;
-
-	($args{'parameterdescs'}{$parameter_name} ne $undescribed) || next;
-	$type = $args{'parametertypes'}{$parameter};
-	if ($type =~ m/([^\(]*\(\*)\s*\)\s*\(([^\)]*)\)/) {
-	    # pointer-to-function
-	    print "\t$1 $parameter) ($2);\n";
-	} elsif ($type =~ m/^(.*?)\s*(:.*)/) {
-	    # bitfield
-	    print "\t$1 $parameter$2;\n";
-	} else {
-	    print "\t" . $type . " " . $parameter . ";\n";
-	}
-    }
-    print "};\n\n";
-
-    print "Members:\n\n";
-    foreach $parameter (@{$args{'parameterlist'}}) {
-	($parameter =~ /^#/) && next;
-
-	my $parameter_name = $parameter;
-	$parameter_name =~ s/\[.*//;
-
-	($args{'parameterdescs'}{$parameter_name} ne $undescribed) || next;
-	print "$parameter\n\t";
-	print $args{'parameterdescs'}{$parameter_name} . "\n";
-    }
-    print "\n";
-    output_section_text(@_);
-}
-
-sub output_blockhead_text(%) {
-    my %args = %{$_[0]};
-    my ($parameter, $section);
-
-    foreach $section (@{$args{'sectionlist'}}) {
-	print " $section:\n";
-	print "    -> ";
-	output_highlight($args{'sections'}{$section});
-    }
-}
-
-## list mode output functions
-
-sub output_function_list(%) {
-    my %args = %{$_[0]};
-
-    print $args{'function'} . "\n";
-}
-
-# output enum in list
-sub output_enum_list(%) {
-    my %args = %{$_[0]};
-    print $args{'enum'} . "\n";
-}
-
-# output typedef in list
-sub output_typedef_list(%) {
-    my %args = %{$_[0]};
-    print $args{'typedef'} . "\n";
-}
-
-# output struct as list
-sub output_struct_list(%) {
-    my %args = %{$_[0]};
-
-    print $args{'struct'} . "\n";
-}
-
-sub output_blockhead_list(%) {
-    my %args = %{$_[0]};
-    my ($parameter, $section);
-
-    foreach $section (@{$args{'sectionlist'}}) {
-	print "DOC: $section\n";
-    }
-}
-
-##
-# generic output function for all types (function, struct/union, typedef, enum);
-# calls the generated, variable output_ function name based on
-# functype and output_mode
-sub output_declaration {
-    no strict 'refs';
-    my $name = shift;
-    my $functype = shift;
-    my $func = "output_${functype}_$output_mode";
-    if (($function_only==0) ||
-	( $function_only == 1 && defined($function_table{$name})) ||
-	( $function_only == 2 && !defined($function_table{$name})))
-    {
-	&$func(@_);
-	$section_counter++;
-    }
-}
-
-##
-# generic output function - calls the right one based on current output mode.
-sub output_blockhead {
-    no strict 'refs';
-    my $func = "output_blockhead_" . $output_mode;
-    &$func(@_);
-    $section_counter++;
-}
-
-##
-# takes a declaration (struct, union, enum, typedef) and
-# invokes the right handler. NOT called for functions.
-sub dump_declaration($$) {
-    no strict 'refs';
-    my ($prototype, $file) = @_;
-    my $func = "dump_" . $decl_type;
-    &$func(@_);
-}
-
-sub dump_union($$) {
-    dump_struct(@_);
-}
-
-sub dump_struct($$) {
-    my $x = shift;
-    my $file = shift;
-    my $nested;
-
-    if ($x =~ /(struct|union)\s+(\w+)\s*{(.*)}/) {
-	#my $decl_type = $1;
-	$declaration_name = $2;
-	my $members = $3;
-
-	# ignore embedded structs or unions
-	$members =~ s/({.*})//g;
-	$nested = $1;
-
-	# ignore members marked private:
-	$members =~ s/\/\*\s*private:.*?\/\*\s*public:.*?\*\///gos;
-	$members =~ s/\/\*\s*private:.*//gos;
-	# strip comments:
-	$members =~ s/\/\*.*?\*\///gos;
-	$nested =~ s/\/\*.*?\*\///gos;
-	# strip kmemcheck_bitfield_{begin,end}.*;
-	$members =~ s/kmemcheck_bitfield_.*?;//gos;
-	# strip attributes
-	$members =~ s/__aligned\s*\(\d+\)//gos;
-
-	create_parameterlist($members, ';', $file);
-	check_sections($file, $declaration_name, "struct", $sectcheck, $struct_actual, $nested);
-
-	output_declaration($declaration_name,
-			   'struct',
-			   {'struct' => $declaration_name,
-			    'module' => $modulename,
-			    'parameterlist' => \@parameterlist,
-			    'parameterdescs' => \%parameterdescs,
-			    'parametertypes' => \%parametertypes,
-			    'sectionlist' => \@sectionlist,
-			    'sections' => \%sections,
-			    'purpose' => $declaration_purpose,
-			    'type' => $decl_type
-			   });
-    }
-    else {
-	print STDERR "Error(${file}:$.): Cannot parse struct or union!\n";
-	++$errors;
-    }
-}
-
-sub dump_enum($$) {
-    my $x = shift;
-    my $file = shift;
-
-    $x =~ s@/\*.*?\*/@@gos;	# strip comments.
-    $x =~ s/^#\s*define\s+.*$//; # strip #define macros inside enums
-
-    if ($x =~ /enum\s+(\w+)\s*{(.*)}/) {
-	$declaration_name = $1;
-	my $members = $2;
-
-	foreach my $arg (split ',', $members) {
-	    $arg =~ s/^\s*(\w+).*/$1/;
-	    push @parameterlist, $arg;
-	    if (!$parameterdescs{$arg}) {
-		$parameterdescs{$arg} = $undescribed;
-		print STDERR "Warning(${file}:$.): Enum value '$arg' ".
-		    "not described in enum '$declaration_name'\n";
-	    }
-
-	}
-
-	output_declaration($declaration_name,
-			   'enum',
-			   {'enum' => $declaration_name,
-			    'module' => $modulename,
-			    'parameterlist' => \@parameterlist,
-			    'parameterdescs' => \%parameterdescs,
-			    'sectionlist' => \@sectionlist,
-			    'sections' => \%sections,
-			    'purpose' => $declaration_purpose
-			   });
-    }
-    else {
-	print STDERR "Error(${file}:$.): Cannot parse enum!\n";
-	++$errors;
-    }
-}
-
-sub dump_typedef($$) {
-    my $x = shift;
-    my $file = shift;
-
-    $x =~ s@/\*.*?\*/@@gos;	# strip comments.
-    while (($x =~ /\(*.\)\s*;$/) || ($x =~ /\[*.\]\s*;$/)) {
-	$x =~ s/\(*.\)\s*;$/;/;
-	$x =~ s/\[*.\]\s*;$/;/;
-    }
-
-    if ($x =~ /typedef.*\s+(\w+)\s*;/) {
-	$declaration_name = $1;
-
-	output_declaration($declaration_name,
-			   'typedef',
-			   {'typedef' => $declaration_name,
-			    'module' => $modulename,
-			    'sectionlist' => \@sectionlist,
-			    'sections' => \%sections,
-			    'purpose' => $declaration_purpose
-			   });
-    }
-    else {
-	print STDERR "Error(${file}:$.): Cannot parse typedef!\n";
-	++$errors;
-    }
-}
-
-sub save_struct_actual($) {
-    my $actual = shift;
-
-    # strip all spaces from the actual param so that it looks like one string item
-    $actual =~ s/\s*//g;
-    $struct_actual = $struct_actual . $actual . " ";
-}
-
-sub create_parameterlist($$$) {
-    my $args = shift;
-    my $splitter = shift;
-    my $file = shift;
-    my $type;
-    my $param;
-
-    # temporarily replace commas inside function pointer definition
-    while ($args =~ /(\([^\),]+),/) {
-	$args =~ s/(\([^\),]+),/$1#/g;
-    }
-
-    foreach my $arg (split($splitter, $args)) {
-	# strip comments
-	$arg =~ s/\/\*.*\*\///;
-	# strip leading/trailing spaces
-	$arg =~ s/^\s*//;
-	$arg =~ s/\s*$//;
-	$arg =~ s/\s+/ /;
-
-	if ($arg =~ /^#/) {
-	    # Treat preprocessor directive as a typeless variable just to fill
-	    # corresponding data structures "correctly". Catch it later in
-	    # output_* subs.
-	    push_parameter($arg, "", $file);
-	} elsif ($arg =~ m/\(.+\)\s*\(/) {
-	    # pointer-to-function
-	    $arg =~ tr/#/,/;
-	    $arg =~ m/[^\(]+\(\*?\s*(\w*)\s*\)/;
-	    $param = $1;
-	    $type = $arg;
-	    $type =~ s/([^\(]+\(\*?)\s*$param/$1/;
-	    save_struct_actual($param);
-	    push_parameter($param, $type, $file);
-	} elsif ($arg) {
-	    $arg =~ s/\s*:\s*/:/g;
-	    $arg =~ s/\s*\[/\[/g;
-
-	    my @args = split('\s*,\s*', $arg);
-	    if ($args[0] =~ m/\*/) {
-		$args[0] =~ s/(\*+)\s*/ $1/;
-	    }
-
-	    my @first_arg;
-	    if ($args[0] =~ /^(.*\s+)(.*?\[.*\].*)$/) {
-		    shift @args;
-		    push(@first_arg, split('\s+', $1));
-		    push(@first_arg, $2);
-	    } else {
-		    @first_arg = split('\s+', shift @args);
-	    }
-
-	    unshift(@args, pop @first_arg);
-	    $type = join " ", @first_arg;
-
-	    foreach $param (@args) {
-		if ($param =~ m/^(\*+)\s*(.*)/) {
-		    save_struct_actual($2);
-		    push_parameter($2, "$type $1", $file);
-		}
-		elsif ($param =~ m/(.*?):(\d+)/) {
-		    if ($type ne "") { # skip unnamed bit-fields
-			save_struct_actual($1);
-			push_parameter($1, "$type:$2", $file)
-		    }
-		}
-		else {
-		    save_struct_actual($param);
-		    push_parameter($param, $type, $file);
-		}
-	    }
-	}
-    }
-}
-
-sub push_parameter($$$) {
-	my $param = shift;
-	my $type = shift;
-	my $file = shift;
-
-	if (($anon_struct_union == 1) && ($type eq "") &&
-	    ($param eq "}")) {
-		return;		# ignore the ending }; from anon. struct/union
-	}
-
-	$anon_struct_union = 0;
-	my $param_name = $param;
-	$param_name =~ s/\[.*//;
-
-	if ($type eq "" && $param =~ /\.\.\.$/)
-	{
-	    if (!defined $parameterdescs{$param} || $parameterdescs{$param} eq "") {
-		$parameterdescs{$param} = "variable arguments";
-	    }
-	}
-	elsif ($type eq "" && ($param eq "" or $param eq "void"))
-	{
-	    $param="void";
-	    $parameterdescs{void} = "no arguments";
-	}
-	elsif ($type eq "" && ($param eq "struct" or $param eq "union"))
-	# handle unnamed (anonymous) union or struct:
-	{
-		$type = $param;
-		$param = "{unnamed_" . $param . "}";
-		$parameterdescs{$param} = "anonymous\n";
-		$anon_struct_union = 1;
-	}
-
-	# warn if parameter has no description
-	# (but ignore ones starting with # as these are not parameters
-	# but inline preprocessor statements);
-	# also ignore unnamed structs/unions;
-	if (!$anon_struct_union) {
-	if (!defined $parameterdescs{$param_name} && $param_name !~ /^#/) {
-
-	    $parameterdescs{$param_name} = $undescribed;
-
-	    if (($type eq 'function') || ($type eq 'enum')) {
-		print STDERR "Warning(${file}:$.): Function parameter ".
-		    "or member '$param' not " .
-		    "described in '$declaration_name'\n";
-	    }
-	    print STDERR "Warning(${file}:$.):" .
-			 " No description found for parameter '$param'\n";
-	    ++$warnings;
-	}
-	}
-
-	$param = xml_escape($param);
-
-	# strip spaces from $param so that it is one continuous string
-	# on @parameterlist;
-	# this fixes a problem where check_sections() cannot find
-	# a parameter like "addr[6 + 2]" because it actually appears
-	# as "addr[6", "+", "2]" on the parameter list;
-	# but it's better to maintain the param string unchanged for output,
-	# so just weaken the string compare in check_sections() to ignore
-	# "[blah" in a parameter string;
-	###$param =~ s/\s*//g;
-	push @parameterlist, $param;
-	$parametertypes{$param} = $type;
-}
-
-sub check_sections($$$$$$) {
-	my ($file, $decl_name, $decl_type, $sectcheck, $prmscheck, $nested) = @_;
-	my @sects = split ' ', $sectcheck;
-	my @prms = split ' ', $prmscheck;
-	my $err;
-	my ($px, $sx);
-	my $prm_clean;		# strip trailing "[array size]" and/or beginning "*"
-
-	foreach $sx (0 .. $#sects) {
-		$err = 1;
-		foreach $px (0 .. $#prms) {
-			$prm_clean = $prms[$px];
-			$prm_clean =~ s/\[.*\]//;
-			$prm_clean =~ s/__attribute__\s*\(\([a-z,_\*\s\(\)]*\)\)//i;
-			# ignore array size in a parameter string;
-			# however, the original param string may contain
-			# spaces, e.g.:  addr[6 + 2]
-			# and this appears in @prms as "addr[6" since the
-			# parameter list is split at spaces;
-			# hence just ignore "[..." for the sections check;
-			$prm_clean =~ s/\[.*//;
-
-			##$prm_clean =~ s/^\**//;
-			if ($prm_clean eq $sects[$sx]) {
-				$err = 0;
-				last;
-			}
-		}
-		if ($err) {
-			if ($decl_type eq "function") {
-				print STDERR "Warning(${file}:$.): " .
-					"Excess function parameter " .
-					"'$sects[$sx]' " .
-					"description in '$decl_name'\n";
-				++$warnings;
-			} else {
-				if ($nested !~ m/\Q$sects[$sx]\E/) {
-				    print STDERR "Warning(${file}:$.): " .
-					"Excess struct/union/enum/typedef member " .
-					"'$sects[$sx]' " .
-					"description in '$decl_name'\n";
-				    ++$warnings;
-				}
-			}
-		}
-	}
-}
-
-##
-# takes a function prototype and the name of the current file being
-# processed and spits out all the details stored in the global
-# arrays/hashes.
-sub dump_function($$) {
-    my $prototype = shift;
-    my $file = shift;
-
-    $prototype =~ s/^static +//;
-    $prototype =~ s/^extern +//;
-    $prototype =~ s/^asmlinkage +//;
-    $prototype =~ s/^inline +//;
-    $prototype =~ s/^__inline__ +//;
-    $prototype =~ s/^__inline +//;
-    $prototype =~ s/^__always_inline +//;
-    $prototype =~ s/^noinline +//;
-    $prototype =~ s/__devinit +//;
-    $prototype =~ s/__init +//;
-    $prototype =~ s/__init_or_module +//;
-    $prototype =~ s/__must_check +//;
-    $prototype =~ s/__weak +//;
-    $prototype =~ s/^#\s*define\s+//; #ak added
-    $prototype =~ s/__attribute__\s*\(\([a-z,]*\)\)//;
-
-    # Yes, this truly is vile.  We are looking for:
-    # 1. Return type (may be nothing if we're looking at a macro)
-    # 2. Function name
-    # 3. Function parameters.
-    #
-    # All the while we have to watch out for function pointer parameters
-    # (which IIRC is what the two sections are for), C types (these
-    # regexps don't even start to express all the possibilities), and
-    # so on.
-    #
-    # If you mess with these regexps, it's a good idea to check that
-    # the following functions' documentation still comes out right:
-    # - parport_register_device (function pointer parameters)
-    # - atomic_set (macro)
-    # - pci_match_device, __copy_to_user (long return type)
-
-    if ($prototype =~ m/^()([a-zA-Z0-9_~:]+)\s*\(([^\(]*)\)/ ||
-	$prototype =~ m/^(\w+)\s+([a-zA-Z0-9_~:]+)\s*\(([^\(]*)\)/ ||
-	$prototype =~ m/^(\w+\s*\*)\s*([a-zA-Z0-9_~:]+)\s*\(([^\(]*)\)/ ||
-	$prototype =~ m/^(\w+\s+\w+)\s+([a-zA-Z0-9_~:]+)\s*\(([^\(]*)\)/ ||
-	$prototype =~ m/^(\w+\s+\w+\s*\*+)\s*([a-zA-Z0-9_~:]+)\s*\(([^\(]*)\)/ ||
-	$prototype =~ m/^(\w+\s+\w+\s+\w+)\s+([a-zA-Z0-9_~:]+)\s*\(([^\(]*)\)/ ||
-	$prototype =~ m/^(\w+\s+\w+\s+\w+\s*\*)\s*([a-zA-Z0-9_~:]+)\s*\(([^\(]*)\)/ ||
-	$prototype =~ m/^()([a-zA-Z0-9_~:]+)\s*\(([^\{]*)\)/ ||
-	$prototype =~ m/^(\w+)\s+([a-zA-Z0-9_~:]+)\s*\(([^\{]*)\)/ ||
-	$prototype =~ m/^(\w+\s*\*)\s*([a-zA-Z0-9_~:]+)\s*\(([^\{]*)\)/ ||
-	$prototype =~ m/^(\w+\s+\w+)\s+([a-zA-Z0-9_~:]+)\s*\(([^\{]*)\)/ ||
-	$prototype =~ m/^(\w+\s+\w+\s*\*)\s*([a-zA-Z0-9_~:]+)\s*\(([^\{]*)\)/ ||
-	$prototype =~ m/^(\w+\s+\w+\s+\w+)\s+([a-zA-Z0-9_~:]+)\s*\(([^\{]*)\)/ ||
-	$prototype =~ m/^(\w+\s+\w+\s+\w+\s*\*)\s*([a-zA-Z0-9_~:]+)\s*\(([^\{]*)\)/ ||
-	$prototype =~ m/^(\w+\s+\w+\s+\w+\s+\w+)\s+([a-zA-Z0-9_~:]+)\s*\(([^\{]*)\)/ ||
-	$prototype =~ m/^(\w+\s+\w+\s+\w+\s+\w+\s*\*)\s*([a-zA-Z0-9_~:]+)\s*\(([^\{]*)\)/ ||
-	$prototype =~ m/^(\w+\s+\w+\s*\*\s*\w+\s*\*\s*)\s*([a-zA-Z0-9_~:]+)\s*\(([^\{]*)\)/)  {
-	$return_type = $1;
-	$declaration_name = $2;
-	my $args = $3;
-
-	create_parameterlist($args, ',', $file);
-    } else {
-	print STDERR "Error(${file}:$.): cannot understand prototype: '$prototype'\n";
-	++$errors;
-	return;
-    }
-
-	my $prms = join " ", @parameterlist;
-	check_sections($file, $declaration_name, "function", $sectcheck, $prms, "");
-
-    output_declaration($declaration_name,
-		       'function',
-		       {'function' => $declaration_name,
-			'module' => $modulename,
-			'functiontype' => $return_type,
-			'parameterlist' => \@parameterlist,
-			'parameterdescs' => \%parameterdescs,
-			'parametertypes' => \%parametertypes,
-			'sectionlist' => \@sectionlist,
-			'sections' => \%sections,
-			'purpose' => $declaration_purpose
-		       });
-}
-
-sub reset_state {
-    $function = "";
-    %constants = ();
-    %parameterdescs = ();
-    %parametertypes = ();
-    @parameterlist = ();
-    %sections = ();
-    @sectionlist = ();
-    $sectcheck = "";
-    $struct_actual = "";
-    $prototype = "";
-
-    $state = 0;
-}
-
-sub tracepoint_munge($) {
-	my $file = shift;
-	my $tracepointname = 0;
-	my $tracepointargs = 0;
-
-	if ($prototype =~ m/TRACE_EVENT\((.*?),/) {
-		$tracepointname = $1;
-	}
-	if ($prototype =~ m/DEFINE_SINGLE_EVENT\((.*?),/) {
-		$tracepointname = $1;
-	}
-	if ($prototype =~ m/DEFINE_EVENT\((.*?),(.*?),/) {
-		$tracepointname = $2;
-	}
-	$tracepointname =~ s/^\s+//; #strip leading whitespace
-	if ($prototype =~ m/TP_PROTO\((.*?)\)/) {
-		$tracepointargs = $1;
-	}
-	if (($tracepointname eq 0) || ($tracepointargs eq 0)) {
-		print STDERR "Warning(${file}:$.): Unrecognized tracepoint format: \n".
-			     "$prototype\n";
-	} else {
-		$prototype = "static inline void trace_$tracepointname($tracepointargs)";
-	}
-}
-
-sub syscall_munge() {
-	my $void = 0;
-
-	$prototype =~ s@[\r\n\t]+@ @gos; # strip newlines/CR's/tabs
-##	if ($prototype =~ m/SYSCALL_DEFINE0\s*\(\s*(a-zA-Z0-9_)*\s*\)/) {
-	if ($prototype =~ m/SYSCALL_DEFINE0/) {
-		$void = 1;
-##		$prototype = "long sys_$1(void)";
-	}
-
-	$prototype =~ s/SYSCALL_DEFINE.*\(/long sys_/; # fix return type & func name
-	if ($prototype =~ m/long (sys_.*?),/) {
-		$prototype =~ s/,/\(/;
-	} elsif ($void) {
-		$prototype =~ s/\)/\(void\)/;
-	}
-
-	# now delete all of the odd-number commas in $prototype
-	# so that arg types & arg names don't have a comma between them
-	my $count = 0;
-	my $len = length($prototype);
-	if ($void) {
-		$len = 0;	# skip the for-loop
-	}
-	for (my $ix = 0; $ix < $len; $ix++) {
-		if (substr($prototype, $ix, 1) eq ',') {
-			$count++;
-			if ($count % 2 == 1) {
-				substr($prototype, $ix, 1) = ' ';
-			}
-		}
-	}
-}
-
-sub process_state3_function($$) {
-    my $x = shift;
-    my $file = shift;
-
-    $x =~ s@\/\/.*$@@gos; # strip C99-style comments to end of line
-
-    if ($x =~ m#\s*/\*\s+MACDOC\s*#io || ($x =~ /^#/ && $x !~ /^#\s*define/)) {
-	# do nothing
-    }
-    elsif ($x =~ /([^\{]*)/) {
-	$prototype .= $1;
-    }
-
-    if (($x =~ /\{/) || ($x =~ /\#\s*define/) || ($x =~ /;/)) {
-	$prototype =~ s@/\*.*?\*/@@gos;	# strip comments.
-	$prototype =~ s@[\r\n]+@ @gos; # strip newlines/cr's.
-	$prototype =~ s@^\s+@@gos; # strip leading spaces
-	if ($prototype =~ /SYSCALL_DEFINE/) {
-		syscall_munge();
-	}
-	if ($prototype =~ /TRACE_EVENT/ || $prototype =~ /DEFINE_EVENT/ ||
-	    $prototype =~ /DEFINE_SINGLE_EVENT/)
-	{
-		tracepoint_munge($file);
-	}
-	dump_function($prototype, $file);
-	reset_state();
-    }
-}
-
-sub process_state3_type($$) {
-    my $x = shift;
-    my $file = shift;
-
-    $x =~ s@[\r\n]+@ @gos; # strip newlines/cr's.
-    $x =~ s@^\s+@@gos; # strip leading spaces
-    $x =~ s@\s+$@@gos; # strip trailing spaces
-    $x =~ s@\/\/.*$@@gos; # strip C99-style comments to end of line
-
-    if ($x =~ /^#/) {
-	# To distinguish preprocessor directive from regular declaration later.
-	$x .= ";";
-    }
-
-    while (1) {
-	if ( $x =~ /([^{};]*)([{};])(.*)/ ) {
-	    $prototype .= $1 . $2;
-	    ($2 eq '{') && $brcount++;
-	    ($2 eq '}') && $brcount--;
-	    if (($2 eq ';') && ($brcount == 0)) {
-		dump_declaration($prototype, $file);
-		reset_state();
-		last;
-	    }
-	    $x = $3;
-	} else {
-	    $prototype .= $x;
-	    last;
-	}
-    }
-}
-
-# xml_escape: replace <, >, and & in the text stream;
-#
-# however, formatting controls that are generated internally/locally in the
-# kernel-doc script are not escaped here; instead, they begin life like
-# $blankline_html (4 of '\' followed by a mnemonic + ':'), then these strings
-# are converted to their mnemonic-expected output, without the 4 * '\' & ':',
-# just before actual output; (this is done by local_unescape())
-sub xml_escape($) {
-	my $text = shift;
-	if (($output_mode eq "text") || ($output_mode eq "man")) {
-		return $text;
-	}
-	$text =~ s/\&/\\\\\\amp;/g;
-	$text =~ s/\</\\\\\\lt;/g;
-	$text =~ s/\>/\\\\\\gt;/g;
-	return $text;
-}
-
-# convert local escape strings to html
-# local escape strings look like:  '\\\\menmonic:' (that's 4 backslashes)
-sub local_unescape($) {
-	my $text = shift;
-	if (($output_mode eq "text") || ($output_mode eq "man")) {
-		return $text;
-	}
-	$text =~ s/\\\\\\\\lt:/</g;
-	$text =~ s/\\\\\\\\gt:/>/g;
-	return $text;
-}
-
-sub process_file($) {
-    my $file;
-    my $identifier;
-    my $func;
-    my $descr;
-    my $in_purpose = 0;
-    my $initial_section_counter = $section_counter;
-
-    if (defined($ENV{'SRCTREE'})) {
-	$file = "$ENV{'SRCTREE'}" . "/" . "@_";
-    }
-    else {
-	$file = "@_";
-    }
-    if (defined($source_map{$file})) {
-	$file = $source_map{$file};
-    }
-
-    if (!open(IN,"<$file")) {
-	print STDERR "Error: Cannot open file $file\n";
-	++$errors;
-	return;
-    }
-
-    $. = 1;
-
-    $section_counter = 0;
-    while (<IN>) {
-	if ($state == 0) {
-	    if (/$doc_start/o) {
-		$state = 1;		# next line is always the function name
-		$in_doc_sect = 0;
-	    }
-	} elsif ($state == 1) {	# this line is the function name (always)
-	    if (/$doc_block/o) {
-		$state = 4;
-		$contents = "";
-		if ( $1 eq "" ) {
-			$section = $section_intro;
-		} else {
-			$section = $1;
-		}
-	    }
-	    elsif (/$doc_decl/o) {
-		$identifier = $1;
-		if (/\s*([\w\s]+?)\s*-/) {
-		    $identifier = $1;
-		}
-
-		$state = 2;
-		if (/-(.*)/) {
-		    # strip leading/trailing/multiple spaces
-		    $descr= $1;
-		    $descr =~ s/^\s*//;
-		    $descr =~ s/\s*$//;
-		    $descr =~ s/\s+/ /;
-		    $declaration_purpose = xml_escape($descr);
-		    $in_purpose = 1;
-		} else {
-		    $declaration_purpose = "";
-		}
-
-		if (($declaration_purpose eq "") && $verbose) {
-			print STDERR "Warning(${file}:$.): missing initial short description on line:\n";
-			print STDERR $_;
-			++$warnings;
-		}
-
-		if ($identifier =~ m/^struct/) {
-		    $decl_type = 'struct';
-		} elsif ($identifier =~ m/^union/) {
-		    $decl_type = 'union';
-		} elsif ($identifier =~ m/^enum/) {
-		    $decl_type = 'enum';
-		} elsif ($identifier =~ m/^typedef/) {
-		    $decl_type = 'typedef';
-		} else {
-		    $decl_type = 'function';
-		}
-
-		if ($verbose) {
-		    print STDERR "Info(${file}:$.): Scanning doc for $identifier\n";
-		}
-	    } else {
-		print STDERR "Warning(${file}:$.): Cannot understand $_ on line $.",
-		" - I thought it was a doc line\n";
-		++$warnings;
-		$state = 0;
-	    }
-	} elsif ($state == 2) {	# look for head: lines, and include content
-	    if (/$doc_sect/o) {
-		$newsection = $1;
-		$newcontents = $2;
-
-		if (($contents ne "") && ($contents ne "\n")) {
-		    if (!$in_doc_sect && $verbose) {
-			print STDERR "Warning(${file}:$.): contents before sections\n";
-			++$warnings;
-		    }
-		    dump_section($file, $section, xml_escape($contents));
-		    $section = $section_default;
-		}
-
-		$in_doc_sect = 1;
-		$in_purpose = 0;
-		$contents = $newcontents;
-		if ($contents ne "") {
-		    while ((substr($contents, 0, 1) eq " ") ||
-			substr($contents, 0, 1) eq "\t") {
-			    $contents = substr($contents, 1);
-		    }
-		    $contents .= "\n";
-		}
-		$section = $newsection;
-	    } elsif (/$doc_end/) {
-
-		if (($contents ne "") && ($contents ne "\n")) {
-		    dump_section($file, $section, xml_escape($contents));
-		    $section = $section_default;
-		    $contents = "";
-		}
-		# look for doc_com + <text> + doc_end:
-		if ($_ =~ m'\s*\*\s*[a-zA-Z_0-9:\.]+\*/') {
-		    print STDERR "Warning(${file}:$.): suspicious ending line: $_";
-		    ++$warnings;
-		}
-
-		$prototype = "";
-		$state = 3;
-		$brcount = 0;
-#		print STDERR "end of doc comment, looking for prototype\n";
-	    } elsif (/$doc_content/) {
-		# miguel-style comment kludge, look for blank lines after
-		# @parameter line to signify start of description
-		if ($1 eq "") {
-		    if ($section =~ m/^@/ || $section eq $section_context) {
-			dump_section($file, $section, xml_escape($contents));
-			$section = $section_default;
-			$contents = "";
-		    } else {
-			$contents .= "\n";
-		    }
-		    $in_purpose = 0;
-		} elsif ($in_purpose == 1) {
-		    # Continued declaration purpose
-		    chomp($declaration_purpose);
-		    $declaration_purpose .= " " . xml_escape($1);
-		} elsif ($section =~ m/^Example/) {
-		    $_ =~ s/^\s*\*//;
-		    $contents .= $_;
-		} else {
-		    $contents .= $1 . "\n";
-		}
-	    } else {
-		# i dont know - bad line?  ignore.
-		print STDERR "Warning(${file}:$.): bad line: $_";
-		++$warnings;
-	    }
-	} elsif ($state == 3) {	# scanning for function '{' (end of prototype)
-	    if ($decl_type eq 'function') {
-		process_state3_function($_, $file);
-	    } else {
-		process_state3_type($_, $file);
-	    }
-	} elsif ($state == 4) {
-		# Documentation block
-		if (/$doc_block/) {
-			dump_doc_section($file, $section, xml_escape($contents));
-			$contents = "";
-			$function = "";
-			%constants = ();
-			%parameterdescs = ();
-			%parametertypes = ();
-			@parameterlist = ();
-			%sections = ();
-			@sectionlist = ();
-			$prototype = "";
-			if ( $1 eq "" ) {
-				$section = $section_intro;
-			} else {
-				$section = $1;
-			}
-		}
-		elsif (/$doc_end/)
-		{
-			dump_doc_section($file, $section, xml_escape($contents));
-			$contents = "";
-			$function = "";
-			%constants = ();
-			%parameterdescs = ();
-			%parametertypes = ();
-			@parameterlist = ();
-			%sections = ();
-			@sectionlist = ();
-			$prototype = "";
-			$state = 0;
-		}
-		elsif (/$doc_content/)
-		{
-			if ( $1 eq "" )
-			{
-				$contents .= $blankline;
-			}
-			else
-			{
-				$contents .= $1 . "\n";
-			}
-		}
-	}
-    }
-    if ($initial_section_counter == $section_counter) {
-	print STDERR "Warning(${file}): no structured comments found\n";
-	if ($output_mode eq "xml") {
-	    # The template wants at least one RefEntry here; make one.
-	    print "<refentry>\n";
-	    print " <refnamediv>\n";
-	    print "  <refname>\n";
-	    print "   ${file}\n";
-	    print "  </refname>\n";
-	    print "  <refpurpose>\n";
-	    print "   Document generation inconsistency\n";
-	    print "  </refpurpose>\n";
-	    print " </refnamediv>\n";
-	    print " <refsect1>\n";
-	    print "  <title>\n";
-	    print "   Oops\n";
-	    print "  </title>\n";
-	    print "  <warning>\n";
-	    print "   <para>\n";
-	    print "    The template for this document tried to insert\n";
-	    print "    the structured comment from the file\n";
-	    print "    <filename>${file}</filename> at this point,\n";
-	    print "    but none was found.\n";
-	    print "    This dummy section is inserted to allow\n";
-	    print "    generation to continue.\n";
-	    print "   </para>\n";
-	    print "  </warning>\n";
-	    print " </refsect1>\n";
-	    print "</refentry>\n";
-	}
-    }
-}
-
-
-$kernelversion = get_kernel_version();
-
-# generate a sequence of code that will splice in highlighting information
-# using the s// operator.
-foreach my $pattern (keys %highlights) {
-#   print STDERR "scanning pattern:$pattern, highlight:($highlights{$pattern})\n";
-    $dohighlight .=  "\$contents =~ s:$pattern:$highlights{$pattern}:gs;\n";
-}
-
-# Read the file that maps relative names to absolute names for
-# separate source and object directories and for shadow trees.
-if (open(SOURCE_MAP, "<.tmp_filelist.txt")) {
-	my ($relname, $absname);
-	while(<SOURCE_MAP>) {
-		chop();
-		($relname, $absname) = (split())[0..1];
-		$relname =~ s:^/+::;
-		$source_map{$relname} = $absname;
-	}
-	close(SOURCE_MAP);
-}
-
-foreach (@ARGV) {
-    chomp;
-    process_file($_);
-}
-if ($verbose && $errors) {
-  print STDERR "$errors errors\n";
-}
-if ($verbose && $warnings) {
-  print STDERR "$warnings warnings\n";
-}
-
-exit($errors);
diff --git a/tools/kwbimage.c b/tools/kwbimage.c
index 1df6b2051e..109d61686e 100644
--- a/tools/kwbimage.c
+++ b/tools/kwbimage.c
@@ -6,7 +6,7 @@
  * SPDX-License-Identifier:	GPL-2.0+
  */
 
-#include "mkimage.h"
+#include "imagetool.h"
 #include <image.h>
 #include "kwbimage.h"
 
@@ -54,7 +54,7 @@ static int lineno = -1;
 /*
  * Report Error if xflag is set in addition to default
  */
-static int kwbimage_check_params (struct mkimage_params *params)
+static int kwbimage_check_params(struct image_tool_params *params)
 {
 	if (!strlen (params->imagename)) {
 		printf ("Error:%s - Configuration file not specified, "
@@ -288,7 +288,7 @@ INVL_CMD:
 }
 
 static void kwbimage_set_header (void *ptr, struct stat *sbuf, int ifd,
-				struct mkimage_params *params)
+				struct image_tool_params *params)
 {
 	struct kwb_header *hdr = (struct kwb_header *)ptr;
 	bhr_t *mhdr = &hdr->kwb_hdr;
@@ -322,7 +322,7 @@ static void kwbimage_set_header (void *ptr, struct stat *sbuf, int ifd,
 }
 
 static int kwbimage_verify_header (unsigned char *ptr, int image_size,
-			struct mkimage_params *params)
+			struct image_tool_params *params)
 {
 	struct kwb_header *hdr = (struct kwb_header *)ptr;
 	bhr_t *mhdr = &hdr->kwb_hdr;
@@ -382,5 +382,5 @@ static struct image_type_params kwbimage_params = {
 
 void init_kwb_image_type (void)
 {
-	mkimage_register (&kwbimage_params);
+	register_image_type(&kwbimage_params);
 }
diff --git a/tools/md5.c b/tools/md5.c
new file mode 100644
index 0000000000..befaa321c7
--- /dev/null
+++ b/tools/md5.c
@@ -0,0 +1 @@
+#include "../lib/md5.c"
diff --git a/tools/mkexynosspl.c b/tools/mkexynosspl.c
index ef685b77ab..32b786c724 100644
--- a/tools/mkexynosspl.c
+++ b/tools/mkexynosspl.c
@@ -14,93 +14,174 @@
 #include <compiler.h>
 
 #define CHECKSUM_OFFSET		(14*1024-4)
-#define BUFSIZE			(14*1024)
 #define FILE_PERM		(S_IRUSR | S_IWUSR | S_IRGRP \
 				| S_IWGRP | S_IROTH | S_IWOTH)
 /*
-* Requirement:
-* IROM code reads first 14K bytes from boot device.
-* It then calculates the checksum of 14K-4 bytes and compare with data at
-* 14K-4 offset.
-*
-* This function takes two filenames:
-* IN  "u-boot-spl.bin" and
-* OUT "$(BOARD)-spl.bin as filenames.
-* It reads the "u-boot-spl.bin" in 16K buffer.
-* It calculates checksum of 14K-4 Bytes and stores at 14K-4 offset in buffer.
-* It writes the buffer to "$(BOARD)-spl.bin" file.
-*/
+ * Requirement for the fixed size SPL header:
+ * IROM code reads first (CHECKSUM_OFFSET + 4) bytes from boot device. It then
+ * calculates the checksum of CHECKSUM_OFFSET bytes and compares with data at
+ * CHECKSUM_OFFSET location.
+ *
+ * Requirement for the variable size SPL header:
+
+ * IROM code reads the below header to find out the size of the blob (total
+ * size, header size included) and its checksum. Then it reads the rest of the
+ * blob [i.e size - sizeof(struct var_size_header) bytes], calculates the
+ * checksum and compares it with value read from the header.
+ */
+struct var_size_header {
+	uint32_t spl_size;
+	uint32_t spl_checksum;
+	uint32_t reserved[2];
+};
+
+static const char *prog_name;
+
+static void write_to_file(int ofd, void *buffer, int size)
+{
+	if (write(ofd, buffer, size) == size)
+		return;
+
+	fprintf(stderr, "%s: Failed to write to output file: %s\n",
+		prog_name, strerror(errno));
+	exit(EXIT_FAILURE);
+}
 
+/*
+ * The argv is expected to include one optional parameter and two filenames:
+ * [--vs] IN OUT
+ *
+ * --vs - turns on the variable size SPL mode
+ * IN  - the u-boot SPL binary, usually u-boot-spl.bin
+ * OUT - the prepared SPL blob, usually ${BOARD}-spl.bin
+ *
+ * This utility first reads the "u-boot-spl.bin" into a buffer. In case of
+ * fixed size SPL the buffer size is exactly CHECKSUM_OFFSET (such that
+ * smaller u-boot-spl.bin gets padded with 0xff bytes, the larger than limit
+ * u-boot-spl.bin causes an error). For variable size SPL the buffer size is
+ * eqaul to size of the IN file.
+ *
+ * Then it calculates checksum of the buffer by just summing up all bytes.
+ * Then
+ *
+ * - for fixed size SPL the buffer is written into the output file and the
+ *   checksum is appended to the file in little endian format, which results
+ *   in checksum added exactly at CHECKSUM_OFFSET.
+ *
+ * - for variable size SPL the checksum and file size are stored in the
+ *   var_size_header structure (again, in little endian format) and the
+ *   structure is written into the output file. Then the buffer is written
+ *   into the output file.
+ */
 int main(int argc, char **argv)
 {
-	unsigned char buffer[BUFSIZE];
+	unsigned char *buffer;
 	int i, ifd, ofd;
 	uint32_t checksum = 0;
 	off_t	len;
-	ssize_t count;
+	int	var_size_flag, read_size, count;
 	struct stat stat;
-
-	if (argc != 3) {
-		fprintf(stderr, "Usage: %s <infile> <outfile>\n", argv[0]);
+	const int if_index = argc - 2; /* Input file name index in argv. */
+	const int of_index = argc - 1; /* Output file name index in argv. */
+
+	/* Strip path off the program name. */
+	prog_name = strrchr(argv[0], '/');
+	if (prog_name)
+		prog_name++;
+	else
+		prog_name = argv[0];
+
+	if ((argc < 3) ||
+	    (argc > 4) ||
+	    ((argc == 4) && strcmp(argv[1], "--vs"))) {
+		fprintf(stderr, "Usage: %s [--vs] <infile> <outfile>\n",
+			prog_name);
 		exit(EXIT_FAILURE);
 	}
 
-	ifd = open(argv[1], O_RDONLY);
+	/* four args mean variable size SPL wrapper is required */
+	var_size_flag = (argc == 4);
+
+	ifd = open(argv[if_index], O_RDONLY);
 	if (ifd < 0) {
 		fprintf(stderr, "%s: Can't open %s: %s\n",
-			argv[0], argv[1], strerror(errno));
+			prog_name, argv[if_index], strerror(errno));
 		exit(EXIT_FAILURE);
 	}
 
-	ofd = open(argv[2], O_WRONLY | O_CREAT | O_TRUNC, FILE_PERM);
+	ofd = open(argv[of_index], O_WRONLY | O_CREAT | O_TRUNC, FILE_PERM);
 	if (ifd < 0) {
 		fprintf(stderr, "%s: Can't open %s: %s\n",
-			argv[0], argv[2], strerror(errno));
-		close(ifd);
+			prog_name, argv[of_index], strerror(errno));
 		exit(EXIT_FAILURE);
 	}
 
 	if (fstat(ifd, &stat)) {
 		fprintf(stderr, "%s: Unable to get size of %s: %s\n",
-			argv[0], argv[1], strerror(errno));
-		close(ifd);
-		close(ofd);
+			prog_name, argv[if_index], strerror(errno));
 		exit(EXIT_FAILURE);
 	}
 
 	len = stat.st_size;
 
-	count = (len < CHECKSUM_OFFSET) ? len : CHECKSUM_OFFSET;
-
-	if (read(ifd, buffer, count) != count) {
-		fprintf(stderr, "%s: Can't read %s: %s\n",
-			argv[0], argv[1], strerror(errno));
+	if (var_size_flag) {
+		read_size = len;
+		count = len;
+	} else {
+		if (len > CHECKSUM_OFFSET) {
+			fprintf(stderr,
+				"%s: %s is too big (exceeds %d bytes)\n",
+				prog_name, argv[if_index], CHECKSUM_OFFSET);
+			exit(EXIT_FAILURE);
+		}
+		count = CHECKSUM_OFFSET;
+		read_size = len;
+	}
 
-		close(ifd);
-		close(ofd);
+	buffer = malloc(count);
+	if (!buffer) {
+		fprintf(stderr,
+			"%s: Failed to allocate %d bytes to store %s\n",
+			prog_name, count, argv[if_index]);
+		exit(EXIT_FAILURE);
+	}
 
+	if (read(ifd, buffer, read_size) != read_size) {
+		fprintf(stderr, "%s: Can't read %s: %s\n",
+			prog_name, argv[if_index], strerror(errno));
 		exit(EXIT_FAILURE);
 	}
 
-	for (i = 0, checksum = 0; i < CHECKSUM_OFFSET; i++)
-		checksum += buffer[i];
+	/* Pad if needed with 0xff to make flashing faster. */
+	if (read_size < count)
+		memset((char *)buffer + read_size, 0xff, count - read_size);
 
+	for (i = 0, checksum = 0; i < count; i++)
+		checksum += buffer[i];
 	checksum = cpu_to_le32(checksum);
 
-	memcpy(&buffer[CHECKSUM_OFFSET], &checksum, sizeof(checksum));
-
-	if (write(ofd, buffer, BUFSIZE) != BUFSIZE) {
-		fprintf(stderr, "%s: Can't write %s: %s\n",
-			argv[0], argv[2], strerror(errno));
+	if (var_size_flag) {
+		/* Prepare and write out the variable size SPL header. */
+		struct var_size_header vsh;
+		uint32_t spl_size;
 
-		close(ifd);
-		close(ofd);
+		memset(&vsh, 0, sizeof(vsh));
+		memcpy(&vsh.spl_checksum, &checksum, sizeof(checksum));
 
-		exit(EXIT_FAILURE);
+		spl_size = cpu_to_le32(count + sizeof(struct var_size_header));
+		memcpy(&vsh.spl_size, &spl_size, sizeof(spl_size));
+		write_to_file(ofd, &vsh, sizeof(vsh));
 	}
 
+	write_to_file(ofd, buffer, count);
+
+	/* For fixed size SPL checksum is appended in the end. */
+	if (!var_size_flag)
+		write_to_file(ofd, &checksum, sizeof(checksum));
+
 	close(ifd);
 	close(ofd);
+	free(buffer);
 
 	return EXIT_SUCCESS;
 }
diff --git a/tools/mkimage.c b/tools/mkimage.c
index 7f221013e3..123d0c7d93 100644
--- a/tools/mkimage.c
+++ b/tools/mkimage.c
@@ -19,7 +19,7 @@ static void usage(void);
 struct image_type_params *mkimage_tparams = NULL;
 
 /* parameters initialized by core will be used by the image type code */
-struct mkimage_params params = {
+struct image_tool_params params = {
 	.os = IH_OS_LINUX,
 	.arch = IH_ARCH_PPC,
 	.type = IH_TYPE_KERNEL,
@@ -139,24 +139,8 @@ main (int argc, char **argv)
 	struct image_type_params *tparams = NULL;
 	int pad_len = 0;
 
-	/* Init Freescale PBL Boot image generation/list support */
-	init_pbl_image_type();
-	/* Init Kirkwood Boot image generation/list support */
-	init_kwb_image_type ();
-	/* Init Freescale imx Boot image generation/list support */
-	init_imx_image_type ();
-	/* Init Freescale mxs Boot image generation/list support */
-	init_mxs_image_type();
-	/* Init FIT image generation/list support */
-	init_fit_image_type ();
-	/* Init TI OMAP Boot image generation/list support */
-	init_omap_image_type();
-	/* Init Default image generation/list support */
-	init_default_image_type ();
-	/* Init Davinci UBL support */
-	init_ubl_image_type();
-	/* Init Davinci AIS support */
-	init_ais_image_type();
+	/* Init all image generation/list support */
+	register_image_tool(mkimage_register);
 
 	params.cmdname = *argv;
 	params.addr = params.ep = 0;
@@ -632,8 +616,7 @@ copy_file (int ifd, const char *datafile, int pad)
 	(void) close (dfd);
 }
 
-void
-usage ()
+static void usage(void)
 {
 	fprintf (stderr, "Usage: %s -l image\n"
 			 "          -l ==> list image header information\n",
diff --git a/tools/mkimage.h b/tools/mkimage.h
index af491544e4..d5491b6e60 100644
--- a/tools/mkimage.h
+++ b/tools/mkimage.h
@@ -20,6 +20,7 @@
 #include <unistd.h>
 #include <sha1.h>
 #include "fdt_host.h"
+#include "imagetool.h"
 
 #undef MKIMAGE_DEBUG
 
@@ -29,8 +30,6 @@
 #define debug(fmt,args...)
 #endif /* MKIMAGE_DEBUG */
 
-#define ARRAY_SIZE(x)		(sizeof(x) / sizeof((x)[0]))
-
 static inline void *map_sysmem(ulong paddr, unsigned long len)
 {
 	return (void *)(uintptr_t)paddr;
@@ -47,124 +46,4 @@ static inline ulong map_to_sysmem(void *ptr)
 #define MKIMAGE_MAX_DTC_CMDLINE_LEN	512
 #define MKIMAGE_DTC			"dtc"   /* assume dtc is in $PATH */
 
-#define IH_ARCH_DEFAULT		IH_ARCH_INVALID
-
-/*
- * This structure defines all such variables those are initialized by
- * mkimage main core and need to be referred by image type specific
- * functions
- */
-struct mkimage_params {
-	int dflag;
-	int eflag;
-	int fflag;
-	int lflag;
-	int vflag;
-	int xflag;
-	int skipcpy;
-	int os;
-	int arch;
-	int type;
-	int comp;
-	char *dtc;
-	unsigned int addr;
-	unsigned int ep;
-	char *imagename;
-	char *imagename2;
-	char *datafile;
-	char *imagefile;
-	char *cmdname;
-	const char *keydir;	/* Directory holding private keys */
-	const char *keydest;	/* Destination .dtb for public key */
-	const char *comment;	/* Comment to add to signature node */
-	int require_keys;	/* 1 to mark signing keys as 'required' */
-};
-
-/*
- * image type specific variables and callback functions
- */
-struct image_type_params {
-	/* name is an identification tag string for added support */
-	char *name;
-	/*
-	 * header size is local to the specific image type to be supported,
-	 * mkimage core treats this as number of bytes
-	 */
-	uint32_t header_size;
-	/* Image type header pointer */
-	void *hdr;
-	/*
-	 * There are several arguments that are passed on the command line
-	 * and are registered as flags in mkimage_params structure.
-	 * This callback function can be used to check the passed arguments
-	 * are in-lined with the image type to be supported
-	 *
-	 * Returns 1 if parameter check is successful
-	 */
-	int (*check_params) (struct mkimage_params *);
-	/*
-	 * This function is used by list command (i.e. mkimage -l <filename>)
-	 * image type verification code must be put here
-	 *
-	 * Returns 0 if image header verification is successful
-	 * otherwise, returns respective negative error codes
-	 */
-	int (*verify_header) (unsigned char *, int, struct mkimage_params *);
-	/* Prints image information abstracting from image header */
-	void (*print_header) (const void *);
-	/*
-	 * The header or image contents need to be set as per image type to
-	 * be generated using this callback function.
-	 * further output file post processing (for ex. checksum calculation,
-	 * padding bytes etc..) can also be done in this callback function.
-	 */
-	void (*set_header) (void *, struct stat *, int,
-					struct mkimage_params *);
-	/*
-	 * Some image generation support for ex (default image type) supports
-	 * more than one type_ids, this callback function is used to check
-	 * whether input (-T <image_type>) is supported by registered image
-	 * generation/list low level code
-	 */
-	int (*check_image_type) (uint8_t);
-	/* This callback function will be executed if fflag is defined */
-	int (*fflag_handle) (struct mkimage_params *);
-	/*
-	 * This callback function will be executed for variable size record
-	 * It is expected to build this header in memory and return its length
-	 * and a pointer to it by using image_type_params.header_size and
-	 * image_type_params.hdr. The return value shall indicate if an
-	 * additional padding should be used when copying the data image
-	 * by returning the padding length.
-	 */
-	int (*vrec_header) (struct mkimage_params *,
-		struct image_type_params *);
-	/* pointer to the next registered entry in linked list */
-	struct image_type_params *next;
-};
-
-/*
- * Exported functions
- */
-void mkimage_register (struct image_type_params *tparams);
-
-/*
- * There is a c file associated with supported image type low level code
- * for ex. default_image.c, fit_image.c
- * init is the only function referred by mkimage core.
- * to avoid a single lined header file, you can define them here
- *
- * Supported image types init functions
- */
-void pbl_load_uboot(int fd, struct mkimage_params *mparams);
-void init_pbl_image_type(void);
-void init_ais_image_type(void);
-void init_kwb_image_type (void);
-void init_imx_image_type (void);
-void init_mxs_image_type(void);
-void init_default_image_type (void);
-void init_fit_image_type (void);
-void init_ubl_image_type(void);
-void init_omap_image_type(void);
-
 #endif /* _MKIIMAGE_H_ */
diff --git a/tools/mxsimage.c b/tools/mxsimage.c
index 5db19b216f..045b35a39b 100644
--- a/tools/mxsimage.c
+++ b/tools/mxsimage.c
@@ -17,7 +17,7 @@
 
 #include <openssl/evp.h>
 
-#include "mkimage.h"
+#include "imagetool.h"
 #include "mxsimage.h"
 #include <image.h>
 
@@ -502,6 +502,7 @@ static int sb_token_to_long(char *tok, uint32_t *rid)
 
 	tok += 2;
 
+	errno = 0;
 	id = strtoul(tok, &endptr, 16);
 	if ((errno == ERANGE && id == ULONG_MAX) || (errno != 0 && id == 0)) {
 		fprintf(stderr, "ERR: Value can't be decoded!\n");
@@ -2148,11 +2149,11 @@ static int mxsimage_check_image_types(uint8_t type)
 }
 
 static void mxsimage_set_header(void *ptr, struct stat *sbuf, int ifd,
-				struct mkimage_params *params)
+				struct image_tool_params *params)
 {
 }
 
-int mxsimage_check_params(struct mkimage_params *params)
+int mxsimage_check_params(struct image_tool_params *params)
 {
 	if (!params)
 		return -1;
@@ -2193,7 +2194,7 @@ static int mxsimage_verify_print_header(char *file, int silent)
 
 char *imagefile;
 static int mxsimage_verify_header(unsigned char *ptr, int image_size,
-			struct mkimage_params *params)
+			struct image_tool_params *params)
 {
 	struct sb_boot_image_header *hdr;
 
@@ -2291,7 +2292,7 @@ static int sb_build_image(struct sb_image_ctx *ictx,
 	return 0;
 }
 
-static int mxsimage_generate(struct mkimage_params *params,
+static int mxsimage_generate(struct image_tool_params *params,
 	struct image_type_params *tparams)
 {
 	int ret;
@@ -2337,7 +2338,7 @@ static struct image_type_params mxsimage_params = {
 
 void init_mxs_image_type(void)
 {
-	mkimage_register(&mxsimage_params);
+	register_image_type(&mxsimage_params);
 }
 
 #else
diff --git a/tools/omapimage.c b/tools/omapimage.c
index 8774a7e3ac..d59bc4d40d 100644
--- a/tools/omapimage.c
+++ b/tools/omapimage.c
@@ -14,7 +14,7 @@
  * SPDX-License-Identifier:	GPL-2.0+
  */
 
-#include "mkimage.h"
+#include "imagetool.h"
 #include <image.h>
 #include "omapimage.h"
 
@@ -69,7 +69,7 @@ static int valid_gph_load_addr(uint32_t load_addr)
 }
 
 static int omapimage_verify_header(unsigned char *ptr, int image_size,
-			struct mkimage_params *params)
+			struct image_tool_params *params)
 {
 	struct ch_toc *toc = (struct ch_toc *)ptr;
 	struct gp_header *gph = (struct gp_header *)(ptr+OMAP_CH_HDR_SIZE);
@@ -188,7 +188,7 @@ static int toc_offset(void *hdr, void *member)
 }
 
 static void omapimage_set_header(void *ptr, struct stat *sbuf, int ifd,
-				struct mkimage_params *params)
+				struct image_tool_params *params)
 {
 	struct ch_toc *toc = (struct ch_toc *)ptr;
 	struct ch_settings *chs = (struct ch_settings *)
@@ -224,7 +224,7 @@ static void omapimage_set_header(void *ptr, struct stat *sbuf, int ifd,
 	}
 }
 
-int omapimage_check_params(struct mkimage_params *params)
+int omapimage_check_params(struct image_tool_params *params)
 {
 	return	(params->dflag && (params->fflag || params->lflag)) ||
 		(params->fflag && (params->dflag || params->lflag)) ||
@@ -247,5 +247,5 @@ static struct image_type_params omapimage_params = {
 
 void init_omap_image_type(void)
 {
-	mkimage_register(&omapimage_params);
+	register_image_type(&omapimage_params);
 }
diff --git a/tools/patman/README b/tools/patman/README
index e6d3070621..b3aba136b8 100644
--- a/tools/patman/README
+++ b/tools/patman/README
@@ -180,6 +180,14 @@ END
 	together and put after the cover letter. Can appear multiple
 	times.
 
+Commit-notes:
+blah blah
+blah blah
+more blah blah
+END
+	Similar, but for a single commit (patch). These notes will appear
+	immediately below the --- cut in the patch file.
+
  Signed-off-by: Their Name <email>
 	A sign-off is added automatically to your patches (this is
 	probably a bug). If you put this tag in your patches, it will
@@ -209,8 +217,10 @@ Series-changes: n
 	to update the log there and then, knowing that the script will
 	do the rest.
 
- Cc: Their Name <email>
-	This copies a single patch to another email address.
+Patch-cc: Their Name <email>
+	This copies a single patch to another email address. Note that the
+	Cc: used by git send-email is ignored by patman, but will be
+	interpreted by git send-email if you use it.
 
 Series-process-log: sort, uniq
 	This tells patman to sort and/or uniq the change logs. It is
@@ -227,7 +237,7 @@ TEST=...
 Change-Id:
 Review URL:
 Reviewed-on:
-
+Commit-xxxx: (except Commit-notes)
 
 Exercise for the reader: Try adding some tags to one of your current
 patch series and see how the patches turn out.
@@ -238,8 +248,9 @@ Where Patches Are Sent
 
 Once the patches are created, patman sends them using git send-email. The
 whole series is sent to the recipients in Series-to: and Series-cc.
-You can Cc individual patches to other people with the Cc: tag. Tags in the
-subject are also picked up to Cc patches. For example, a commit like this:
+You can Cc individual patches to other people with the Patch-cc: tag. Tags
+in the subject are also picked up to Cc patches. For example, a commit like
+this:
 
 >>>>
 commit 10212537b85ff9b6e09c82045127522c0f0db981
@@ -250,16 +261,16 @@ Date:	Mon Nov 7 23:18:44 2011 -0500
 
     This should make sending out e-mails to the right people easier.
 
-    Cc: sandbox, mikef, ag
-    Cc: afleming
+    Patch-cc: sandbox, mikef, ag
+    Patch-cc: afleming
 <<<<
 
 will create a patch which is copied to x86, arm, sandbox, mikef, ag and
 afleming.
 
-If you have a cover letter it will get sent to the union of the CC lists of
-all of the other patches. If you want to sent it to additional people you
-can add a tag:
+If you have a cover letter it will get sent to the union of the Patch-cc
+lists of all of the other patches. If you want to sent it to additional
+people you can add a tag:
 
 Cover-letter-cc: <list of addresses>
 
diff --git a/tools/patman/commit.py b/tools/patman/commit.py
index 900cfb3a5a..89cce7f88a 100644
--- a/tools/patman/commit.py
+++ b/tools/patman/commit.py
@@ -21,6 +21,7 @@ class Commit:
         changes: Dict containing a list of changes (single line strings).
             The dict is indexed by change version (an integer)
         cc_list: List of people to aliases/emails to cc on this commit
+        notes: List of lines in the commit (not series) notes
     """
     def __init__(self, hash):
         self.hash = hash
@@ -28,6 +29,7 @@ class Commit:
         self.tags = []
         self.changes = {}
         self.cc_list = []
+        self.notes = []
 
     def AddChange(self, version, info):
         """Add a new change line to the change list for a version.
diff --git a/tools/patman/patchstream.py b/tools/patman/patchstream.py
index c2045230af..c4017e0e6d 100644
--- a/tools/patman/patchstream.py
+++ b/tools/patman/patchstream.py
@@ -30,10 +30,13 @@ re_cover = re.compile('^Cover-letter:')
 re_cover_cc = re.compile('^Cover-letter-cc: *(.*)')
 
 # Patch series tag
-re_series = re.compile('^Series-([a-z-]*): *(.*)')
+re_series_tag = re.compile('^Series-([a-z-]*): *(.*)')
+
+# Commit series tag
+re_commit_tag = re.compile('^Commit-([a-z-]*): *(.*)')
 
 # Commit tags that we want to collect and keep
-re_tag = re.compile('^(Tested-by|Acked-by|Reviewed-by|Cc): (.*)')
+re_tag = re.compile('^(Tested-by|Acked-by|Reviewed-by|Patch-cc): (.*)')
 
 # The start of a new commit in the git log
 re_commit = re.compile('^commit ([0-9a-f]*)$')
@@ -90,6 +93,20 @@ class PatchStream:
         if self.is_log:
             self.series.AddTag(self.commit, line, name, value)
 
+    def AddToCommit(self, line, name, value):
+        """Add a new Commit-xxx tag.
+
+        When a Commit-xxx tag is detected, we come here to record it.
+
+        Args:
+            line: Source line containing tag (useful for debug/error messages)
+            name: Tag name (part after 'Commit-')
+            value: Tag value (part after 'Commit-xxx: ')
+        """
+        if name == 'notes':
+            self.in_section = 'commit-' + name
+            self.skip_blank = False
+
     def CloseCommit(self):
         """Save the current commit into our commit list, and reset our state"""
         if self.commit and self.is_log:
@@ -138,7 +155,8 @@ class PatchStream:
                 line = line[4:]
 
         # Handle state transition and skipping blank lines
-        series_match = re_series.match(line)
+        series_tag_match = re_series_tag.match(line)
+        commit_tag_match = re_commit_tag.match(line)
         commit_match = re_commit.match(line) if self.is_log else None
         cover_cc_match = re_cover_cc.match(line)
         tag_match = None
@@ -165,6 +183,9 @@ class PatchStream:
                 elif self.in_section == 'notes':
                     if self.is_log:
                         self.series.notes += self.section
+                elif self.in_section == 'commit-notes':
+                    if self.is_log:
+                        self.commit.notes += self.section
                 else:
                     self.warn.append("Unknown section '%s'" % self.in_section)
                 self.in_section = None
@@ -178,7 +199,7 @@ class PatchStream:
             self.commit.subject = line
 
         # Detect the tags we want to remove, and skip blank lines
-        elif re_remove.match(line):
+        elif re_remove.match(line) and not commit_tag_match:
             self.skip_blank = True
 
             # TEST= should be the last thing in the commit, so remove
@@ -211,9 +232,9 @@ class PatchStream:
             self.skip_blank = False
 
         # Detect Series-xxx tags
-        elif series_match:
-            name = series_match.group(1)
-            value = series_match.group(2)
+        elif series_tag_match:
+            name = series_tag_match.group(1)
+            value = series_tag_match.group(2)
             if name == 'changes':
                 # value is the version number: e.g. 1, or 2
                 try:
@@ -226,6 +247,14 @@ class PatchStream:
                 self.AddToSeries(line, name, value)
                 self.skip_blank = True
 
+        # Detect Commit-xxx tags
+        elif commit_tag_match:
+            name = commit_tag_match.group(1)
+            value = commit_tag_match.group(2)
+            if name == 'notes':
+                self.AddToCommit(line, name, value)
+                self.skip_blank = True
+
         # Detect the start of a new commit
         elif commit_match:
             self.CloseCommit()
@@ -238,7 +267,7 @@ class PatchStream:
             if (tag_match.group(1) == 'Tested-by' and
                     tag_match.group(2).find(os.getenv('USER') + '@') != -1):
                 self.warn.append("Ignoring %s" % line)
-            elif tag_match.group(1) == 'Cc':
+            elif tag_match.group(1) == 'Patch-cc':
                 self.commit.AddCc(tag_match.group(2).split(','))
             else:
                 self.tags.append(line);
@@ -276,7 +305,7 @@ class PatchStream:
                 out = []
                 log = self.series.MakeChangeLog(self.commit)
                 out += self.FormatTags(self.tags)
-                out += [line] + log
+                out += [line] + self.commit.notes + [''] + log
             elif self.found_test:
                 if not re_allowed_after_test.match(line):
                     self.lines_after_test += 1
diff --git a/tools/pblimage.c b/tools/pblimage.c
index bac5faff98..ef3d7f6296 100644
--- a/tools/pblimage.c
+++ b/tools/pblimage.c
@@ -3,7 +3,7 @@
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */
-#include "mkimage.h"
+#include "imagetool.h"
 #include <image.h>
 #include "pblimage.h"
 
@@ -242,7 +242,7 @@ static void add_end_cmd(void)
 	}
 }
 
-void pbl_load_uboot(int ifd, struct mkimage_params *params)
+void pbl_load_uboot(int ifd, struct image_tool_params *params)
 {
 	FILE *fp_uboot;
 	int size;
@@ -281,7 +281,7 @@ static int pblimage_check_image_types(uint8_t type)
 }
 
 static int pblimage_verify_header(unsigned char *ptr, int image_size,
-			struct mkimage_params *params)
+			struct image_tool_params *params)
 {
 	struct pbl_header *pbl_hdr = (struct pbl_header *) ptr;
 
@@ -308,7 +308,7 @@ static void pblimage_print_header(const void *ptr)
 }
 
 static void pblimage_set_header(void *ptr, struct stat *sbuf, int ifd,
-				struct mkimage_params *params)
+				struct image_tool_params *params)
 {
 	/*nothing need to do, pbl_load_uboot takes care of whole file. */
 }
@@ -327,5 +327,5 @@ static struct image_type_params pblimage_params = {
 void init_pbl_image_type(void)
 {
 	pbl_size = 0;
-	mkimage_register(&pblimage_params);
+	register_image_type(&pblimage_params);
 }
diff --git a/tools/relocate-rela.c b/tools/relocate-rela.c
new file mode 100644
index 0000000000..670b9fd73a
--- /dev/null
+++ b/tools/relocate-rela.c
@@ -0,0 +1,189 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+ BSD-2-Clause
+ *
+ * 64-bit and little-endian target only until we need to support a different
+ * arch that needs this.
+ */
+
+#include <elf.h>
+#include <errno.h>
+#include <inttypes.h>
+#include <stdarg.h>
+#include <stdbool.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+
+#ifndef R_AARCH64_RELATIVE
+#define R_AARCH64_RELATIVE	1027
+#endif
+
+static const bool debug_en;
+
+static void debug(const char *fmt, ...)
+{
+	va_list args;
+
+	va_start(args, fmt);
+	if (debug_en)
+		vprintf(fmt, args);
+}
+
+static bool supported_rela(Elf64_Rela *rela)
+{
+	uint64_t mask = 0xffffffffULL; /* would be different on 32-bit */
+	uint32_t type = rela->r_info & mask;
+
+	switch (type) {
+#ifdef R_AARCH64_RELATIVE
+	case R_AARCH64_RELATIVE:
+		return true;
+#endif
+	default:
+		fprintf(stderr, "warning: unsupported relocation type %"
+				PRIu32 " at %" PRIx64 "\n",
+			type, rela->r_offset);
+
+		return false;
+	}
+}
+
+static inline uint64_t swap64(uint64_t val)
+{
+	return ((val >> 56) & 0x00000000000000ffULL) |
+	       ((val >> 40) & 0x000000000000ff00ULL) |
+	       ((val >> 24) & 0x0000000000ff0000ULL) |
+	       ((val >>  8) & 0x00000000ff000000ULL) |
+	       ((val <<  8) & 0x000000ff00000000ULL) |
+	       ((val << 24) & 0x0000ff0000000000ULL) |
+	       ((val << 40) & 0x00ff000000000000ULL) |
+	       ((val << 56) & 0xff00000000000000ULL);
+}
+
+#if __BYTE_ORDER == __LITTLE_ENDIAN
+static inline uint64_t be64(uint64_t val)
+{
+	return swap64(val);
+}
+
+static inline uint64_t le64(uint64_t val)
+{
+	return val;
+}
+#else
+static inline uint64_t le64(uint64_t val)
+{
+	return swap64(val);
+}
+
+static inline uint64_t be64(uint64_t val)
+{
+	return val;
+}
+#endif
+
+static bool read_num(const char *str, uint64_t *num)
+{
+	char *endptr;
+	*num = strtoull(str, &endptr, 16);
+	return str[0] && !endptr[0];
+}
+
+int main(int argc, char **argv)
+{
+	FILE *f;
+	int i, num;
+	uint64_t rela_start, rela_end, text_base;
+
+	if (argc != 5) {
+		fprintf(stderr, "Statically apply ELF rela relocations\n");
+		fprintf(stderr, "Usage: %s <bin file> <text base> " \
+				"<rela start> <rela end>\n", argv[0]);
+		fprintf(stderr, "All numbers in hex.\n");
+		return 1;
+	}
+
+	f = fopen(argv[1], "r+b");
+	if (!f) {
+		fprintf(stderr, "%s: Cannot open %s: %s\n",
+			argv[0], argv[1], strerror(errno));
+		return 2;
+	}
+
+	if (!read_num(argv[2], &text_base) ||
+	    !read_num(argv[3], &rela_start) ||
+	    !read_num(argv[4], &rela_end)) {
+		fprintf(stderr, "%s: bad number\n", argv[0]);
+		return 3;
+	}
+
+	if (rela_start > rela_end || rela_start < text_base ||
+	    (rela_end - rela_start) % sizeof(Elf64_Rela)) {
+		fprintf(stderr, "%s: bad rela bounds\n", argv[0]);
+		return 3;
+	}
+
+	rela_start -= text_base;
+	rela_end -= text_base;
+
+	num = (rela_end - rela_start) / sizeof(Elf64_Rela);
+
+	for (i = 0; i < num; i++) {
+		Elf64_Rela rela, swrela;
+		uint64_t pos = rela_start + sizeof(Elf64_Rela) * i;
+		uint64_t addr;
+
+		if (fseek(f, pos, SEEK_SET) < 0) {
+			fprintf(stderr, "%s: %s: seek to %" PRIx64
+					" failed: %s\n",
+				argv[0], argv[1], pos, strerror(errno));
+		}
+
+		if (fread(&rela, sizeof(rela), 1, f) != 1) {
+			fprintf(stderr, "%s: %s: read rela failed at %"
+					PRIx64 "\n",
+				argv[0], argv[1], pos);
+			return 4;
+		}
+
+		swrela.r_offset = le64(rela.r_offset);
+		swrela.r_info = le64(rela.r_info);
+		swrela.r_addend = le64(rela.r_addend);
+
+		if (!supported_rela(&swrela))
+			continue;
+
+		debug("Rela %" PRIx64 " %" PRIu64 " %" PRIx64 "\n",
+		      swrela.r_offset, swrela.r_info, swrela.r_addend);
+
+		if (swrela.r_offset < text_base) {
+			fprintf(stderr, "%s: %s: bad rela at %" PRIx64 "\n",
+				argv[0], argv[1], pos);
+			return 4;
+		}
+
+		addr = swrela.r_offset - text_base;
+
+		if (fseek(f, addr, SEEK_SET) < 0) {
+			fprintf(stderr, "%s: %s: seek to %"
+					PRIx64 " failed: %s\n",
+				argv[0], argv[1], addr, strerror(errno));
+		}
+
+		if (fwrite(&rela.r_addend, sizeof(rela.r_addend), 1, f) != 1) {
+			fprintf(stderr, "%s: %s: write failed at %" PRIx64 "\n",
+				argv[0], argv[1], addr);
+			return 4;
+		}
+	}
+
+	if (fclose(f) < 0) {
+		fprintf(stderr, "%s: %s: close failed: %s\n",
+			argv[0], argv[1], strerror(errno));
+		return 4;
+	}
+
+	return 0;
+}
diff --git a/tools/rsa-sign.c b/tools/rsa-sign.c
new file mode 100644
index 0000000000..150bbe151e
--- /dev/null
+++ b/tools/rsa-sign.c
@@ -0,0 +1 @@
+#include "../lib/rsa/rsa-sign.c"
diff --git a/tools/scripts/README b/tools/scripts/README
deleted file mode 100644
index dbc4425afd..0000000000
--- a/tools/scripts/README
+++ /dev/null
@@ -1,51 +0,0 @@
-#
-# (C) Copyright 2001
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-This directory contains scripts that help to perform certain actions
-that need to be done frequently when working with U-Boot.
-
-They are meant as EXAMPLE code, so it is very likely  that  you  will
-have to modify them before use.
-
-
-Short description:
-==================
-
-dot.kermrc:
-
-	Example for "~/.kermrc" Kermit init file for use with U-Boot
-
-	by Wolfgang Denk, 24 Jun 2001
-
-flash_param:
-
-	"kermit" script to automatically initialize the environment
-	variables on your target. This is most useful during
-	development when your environment variables are stored in an
-	embedded flash sector which is erased whenever you install a
-	new U-Boot image.
-
-	by Swen Anderson, 10 May 2001
-
-send_cmd:
-
-	send_cmd U_BOOT_COMMAND
-
-	"kermit" script to send a U-Boot command and print the
-	results. When used from a shell with history (like the bash)
-	this indirectly adds kind of history to U-Boot ;-)
-
-	by Swen Anderson, 10 May 2001
-
-send_image:
-
-	send_image FILE_NAME OFFSET
-
-	"kermit" script to automatically download a file to the
-	target using the "loadb" command (kermit binary protocol)
-
-	by Swen Anderson, 10 May 2001
diff --git a/tools/scripts/make-asm-offsets b/tools/scripts/make-asm-offsets
deleted file mode 100755
index 4c33756d66..0000000000
--- a/tools/scripts/make-asm-offsets
+++ /dev/null
@@ -1,27 +0,0 @@
-#!/bin/sh
-
-# Adapted from Linux kernel's "Kbuild":
-# commit 1cdf25d704f7951d02a04064c97db547d6021872
-# Author: Christoph Lameter <clameter@sgi.com>
-
-mkdir -p $(dirname $2)
-
-# Default sed regexp - multiline due to syntax constraints
-SED_CMD="/^->/{s:->#\(.*\):/* \1 */:; \
-	s:^->\([^ ]*\) [\$#]*\([-0-9]*\) \(.*\):#define \1 (\2) /* \3 */:; \
-	s:^->\([^ ]*\) [\$#]*\([^ ]*\) \(.*\):#define \1 \2 /* \3 */:; \
-	s:->::; p;}"
-
-(set -e
- echo "#ifndef __ASM_OFFSETS_H__"
- echo "#define __ASM_OFFSETS_H__"
- echo "/*"
- echo " * DO NOT MODIFY."
- echo " *"
- echo " * This file was generated by $(basename $0)"
- echo " *"
- echo " */"
- echo ""
- sed -ne "${SED_CMD}" $1 
- echo ""
- echo "#endif" ) > $2
diff --git a/tools/sha1.c b/tools/sha1.c
new file mode 100644
index 0000000000..0d717dfa44
--- /dev/null
+++ b/tools/sha1.c
@@ -0,0 +1 @@
+#include "../lib/sha1.c"
diff --git a/tools/ublimage.c b/tools/ublimage.c
index aafe248758..cbbbe205da 100644
--- a/tools/ublimage.c
+++ b/tools/ublimage.c
@@ -13,7 +13,7 @@
  * SPDX-License-Identifier:	GPL-2.0+
  */
 
-#include "mkimage.h"
+#include "imagetool.h"
 #include <image.h>
 #include "ublimage.h"
 
@@ -193,7 +193,7 @@ static int ublimage_check_image_types(uint8_t type)
 }
 
 static int ublimage_verify_header(unsigned char *ptr, int image_size,
-			struct mkimage_params *params)
+			struct image_tool_params *params)
 {
 	struct ubl_header *ubl_hdr = (struct ubl_header *)ptr;
 
@@ -211,7 +211,7 @@ static void ublimage_print_header(const void *ptr)
 }
 
 static void ublimage_set_header(void *ptr, struct stat *sbuf, int ifd,
-				struct mkimage_params *params)
+				struct image_tool_params *params)
 {
 	struct ubl_header *ublhdr = (struct ubl_header *)ptr;
 
@@ -219,7 +219,7 @@ static void ublimage_set_header(void *ptr, struct stat *sbuf, int ifd,
 	parse_cfg_file(ublhdr, params->imagename);
 }
 
-int ublimage_check_params(struct mkimage_params *params)
+int ublimage_check_params(struct image_tool_params *params)
 {
 	if (!params)
 		return CFG_INVALID;
@@ -257,5 +257,5 @@ static struct image_type_params ublimage_params = {
 
 void init_ubl_image_type(void)
 {
-	mkimage_register(&ublimage_params);
+	register_image_type(&ublimage_params);
 }
diff --git a/tools/updater/Makefile b/tools/updater/Makefile
deleted file mode 100644
index 19dd5eb6f4..0000000000
--- a/tools/updater/Makefile
+++ /dev/null
@@ -1,89 +0,0 @@
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-LOAD_ADDR = 0x40000
-
-include $(TOPDIR)/config.mk
-
-PROG		= $(obj)updater
-IMAGE		= $(obj)updater.image
-
-COBJS		= update.o flash.o flash_hw.o utils.o cmd_flash.o string.o ctype.o dummy.o
-COBJS_LINKS	= stubs.o
-AOBJS		= ppcstring.o
-AOBJS_LINKS	= memio.o
-
-OBJS	:= $(addprefix $(obj),$(COBJS) $(COBJS_LINKS) $(AOBJS) $(AOBJS_LINKS))
-SRCS	:= $(COBJS:.o=.c) $(AOBJS:.o=.S) $(addprefix $(obj), $(COBJS_LINKS:.o:.c) $(AOBJS_LINKS:.o:.S))
-
-CPPFLAGS += -I$(TOPDIR) -I$(TOPDIR)/board/MAI/AmigaOneG3SE
-CFLAGS   += -I$(TOPDIR)/board/MAI/AmigaOneG3SE
-AFLAGS   += -I$(TOPDIR)/board/MAI/AmigaOneG3SE
-
-DEPS = $(OBJTREE)/u-boot.bin $(OBJTREE)/tools/mkimage
-ifneq ($(DEPS),$(wildcard $(DEPS)))
-$(error "updater: Missing required objects, please run regular build first")
-endif
-
-all:	$(obj).depend $(PROG) $(IMAGE)
-
-#########################################################################
-
-$(obj)%.srec:	%.o $(LIB)
-	$(LD) -g -Ttext $(LOAD_ADDR) -o $(<:.o=) -e $(<:.o=) $< $(LIB)
-	$(OBJCOPY) -O srec $(<:.o=) $@
-
-$(obj)%.o: %.c
-	$(CC) $(CFLAGS) -c -o $@ $<
-
-$(obj)%.o: %.S
-	$(CC) $(AFLAGS) -c -o $@ $<
-
-$(obj)memio.o: $(obj)memio.S
-	$(CC) $(AFLAGS) -c -o $@ $<
-
-$(obj)memio.S:
-	rm -f $(obj)memio.c
-	ln -s $(SRCTREE)/board/MAI/AmigaOneG3SE/memio.S $(obj)memio.S
-
-$(obj)stubs.o: $(obj)stubs.c
-	$(CC) $(CFLAGS) -c -o $@ $<
-
-$(obj)stubs.c:
-	rm -f $(obj)stubs.c
-	ln -s $(SRCTREE)/examples/stubs.c $(obj)stubs.c
-
-#########################################################################
-
-$(obj)updater: $(OBJS)
-	$(LD) -g -Ttext $(LOAD_ADDR) -o $(obj)updater -e _main $(OBJS)
-	$(OBJCOPY) -O binary $(obj)updater $(obj)updater.bin
-
-$(obj)updater.image: $(obj)updater $(OBJTREE)/u-boot.bin
-	cat >/tmp/tempimage $(obj)updater.bin junk $(OBJTREE)/u-boot.bin
-	$(OBJTREE)/tools/mkimage -A ppc -O u-boot -T standalone -C none -a $(LOAD_ADDR) \
-	-e `$(NM) $(obj)updater | grep _main | cut --bytes=0-8` \
-	-n "Firmware Updater" -d /tmp/tempimage $(obj)updater.image
-	rm /tmp/tempimage
-	cp $(obj)updater.image /tftpboot
-
-(obj)updater.image2: $(obj)updater $(OBJTREE)/u-boot.bin
-	cat >/tmp/tempimage $(obj)updater.bin junk ../../create_image/image
-	$(OBJTREE)/tools/mkimage -A ppc -O u-boot -T standalone -C none -a $(LOAD_ADDR) \
-	-e `$(NM) $(obj)updater | grep _main | cut --bytes=0-8` \
-	-n "Firmware Updater" -d /tmp/tempimage $(obj)updater.image
-	rm /tmp/tempimage
-	cp $(obj)updater.image /tftpboot
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
diff --git a/tools/updater/cmd_flash.c b/tools/updater/cmd_flash.c
deleted file mode 100644
index 3a604d00d5..0000000000
--- a/tools/updater/cmd_flash.c
+++ /dev/null
@@ -1,401 +0,0 @@
-/*
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-/*
- * FLASH support
- */
-#include <common.h>
-#include <command.h>
-#include <flash.h>
-
-#if defined(CONFIG_CMD_FLASH)
-
-extern flash_info_t flash_info[];	/* info for FLASH chips */
-
-/*
- * The user interface starts numbering for Flash banks with 1
- * for historical reasons.
- */
-
-/*
- * this routine looks for an abbreviated flash range specification.
- * the syntax is B:SF[-SL], where B is the bank number, SF is the first
- * sector to erase, and SL is the last sector to erase (defaults to SF).
- * bank numbers start at 1 to be consistent with other specs, sector numbers
- * start at zero.
- *
- * returns:	1	- correct spec; *pinfo, *psf and *psl are
- *			  set appropriately
- *		0	- doesn't look like an abbreviated spec
- *		-1	- looks like an abbreviated spec, but got
- *			  a parsing error, a number out of range,
- *			  or an invalid flash bank.
- */
-static int
-abbrev_spec(char *str, flash_info_t **pinfo, int *psf, int *psl)
-{
-    flash_info_t *fp;
-    int bank, first, last;
-    char *p, *ep;
-
-    if ((p = strchr(str, ':')) == NULL)
-	return 0;
-    *p++ = '\0';
-
-    bank = simple_strtoul(str, &ep, 10);
-    if (ep == str || *ep != '\0' ||
-      bank < 1 || bank > CONFIG_SYS_MAX_FLASH_BANKS ||
-      (fp = &flash_info[bank - 1])->flash_id == FLASH_UNKNOWN)
-	return -1;
-
-    str = p;
-    if ((p = strchr(str, '-')) != NULL)
-	*p++ = '\0';
-
-    first = simple_strtoul(str, &ep, 10);
-    if (ep == str || *ep != '\0' || first >= fp->sector_count)
-	return -1;
-
-    if (p != NULL) {
-	last = simple_strtoul(p, &ep, 10);
-	if (ep == p || *ep != '\0' ||
-	  last < first || last >= fp->sector_count)
-	    return -1;
-    }
-    else
-	last = first;
-
-    *pinfo = fp;
-    *psf = first;
-    *psl = last;
-
-    return 1;
-}
-int do_flinfo (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[])
-{
-	ulong bank;
-
-	if (argc == 1) {	/* print info for all FLASH banks */
-		for (bank=0; bank <CONFIG_SYS_MAX_FLASH_BANKS; ++bank) {
-			printf ("\nBank # %ld: ", bank+1);
-
-			flash_print_info (&flash_info[bank]);
-		}
-		return 0;
-	}
-
-	bank = simple_strtoul(argv[1], NULL, 16);
-	if ((bank < 1) || (bank > CONFIG_SYS_MAX_FLASH_BANKS)) {
-		printf ("Only FLASH Banks # 1 ... # %d supported\n",
-			CONFIG_SYS_MAX_FLASH_BANKS);
-		return 1;
-	}
-	printf ("\nBank # %ld: ", bank);
-	flash_print_info (&flash_info[bank-1]);
-	return 0;
-}
-int do_flerase(cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[])
-{
-	flash_info_t *info;
-	ulong bank, addr_first, addr_last;
-	int n, sect_first, sect_last;
-	int rcode = 0;
-
-	if (argc < 2)
-		return cmd_usage(cmdtp);
-
-	if (strcmp(argv[1], "all") == 0) {
-		for (bank=1; bank<=CONFIG_SYS_MAX_FLASH_BANKS; ++bank) {
-			printf ("Erase Flash Bank # %ld ", bank);
-			info = &flash_info[bank-1];
-			rcode = flash_erase (info, 0, info->sector_count-1);
-		}
-		return rcode;
-	}
-
-	if ((n = abbrev_spec(argv[1], &info, &sect_first, &sect_last)) != 0) {
-		if (n < 0) {
-			printf("Bad sector specification\n");
-			return 1;
-		}
-		printf ("Erase Flash Sectors %d-%d in Bank # %d ",
-			sect_first, sect_last, (info-flash_info)+1);
-		rcode = flash_erase(info, sect_first, sect_last);
-		return rcode;
-	}
-
-	if (argc != 3)
-		return cmd_usage(cmdtp);
-
-	if (strcmp(argv[1], "bank") == 0) {
-		bank = simple_strtoul(argv[2], NULL, 16);
-		if ((bank < 1) || (bank > CONFIG_SYS_MAX_FLASH_BANKS)) {
-			printf ("Only FLASH Banks # 1 ... # %d supported\n",
-				CONFIG_SYS_MAX_FLASH_BANKS);
-			return 1;
-		}
-		printf ("Erase Flash Bank # %ld ", bank);
-		info = &flash_info[bank-1];
-		rcode = flash_erase (info, 0, info->sector_count-1);
-		return rcode;
-	}
-
-	addr_first = simple_strtoul(argv[1], NULL, 16);
-	addr_last  = simple_strtoul(argv[2], NULL, 16);
-
-	if (addr_first >= addr_last)
-		return cmd_usage(cmdtp);
-
-	printf ("Erase Flash from 0x%08lx to 0x%08lx ", addr_first, addr_last);
-	rcode = flash_sect_erase(addr_first, addr_last);
-	return rcode;
-}
-
-int flash_sect_erase (ulong addr_first, ulong addr_last)
-{
-	flash_info_t *info;
-	ulong bank;
-	int s_first, s_last;
-	int erased;
-	int rcode = 0;
-
-	erased = 0;
-
-	for (bank=0,info = &flash_info[0]; bank < CONFIG_SYS_MAX_FLASH_BANKS; ++bank, ++info) {
-		ulong b_end;
-		int sect;
-
-		if (info->flash_id == FLASH_UNKNOWN) {
-			continue;
-		}
-
-		b_end = info->start[0] + info->size - 1; /* bank end addr */
-
-		s_first = -1;		/* first sector to erase	*/
-		s_last  = -1;		/* last  sector to erase	*/
-
-		for (sect=0; sect < info->sector_count; ++sect) {
-			ulong end;		/* last address in current sect	*/
-			short s_end;
-
-			s_end = info->sector_count - 1;
-
-			end = (sect == s_end) ? b_end : info->start[sect + 1] - 1;
-
-			if (addr_first > end)
-				continue;
-			if (addr_last < info->start[sect])
-				continue;
-
-			if (addr_first == info->start[sect]) {
-				s_first = sect;
-			}
-			if (addr_last  == end) {
-				s_last  = sect;
-			}
-		}
-		if (s_first>=0 && s_first<=s_last) {
-			erased += s_last - s_first + 1;
-			rcode = flash_erase (info, s_first, s_last);
-		}
-	}
-	if (erased) {
-	    /*	printf ("Erased %d sectors\n", erased); */
-	} else {
-		printf ("Error: start and/or end address"
-			" not on sector boundary\n");
-		rcode = 1;
-	}
-	return rcode;
-}
-
-
-int do_protect(cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[])
-{
-	flash_info_t *info;
-	ulong bank, addr_first, addr_last;
-	int i, p, n, sect_first, sect_last;
-	int rcode = 0;
-
-	if (argc < 3)
-		return cmd_usage(cmdtp);
-
-	if (strcmp(argv[1], "off") == 0)
-		p = 0;
-	else if (strcmp(argv[1], "on") == 0)
-		p = 1;
-	else
-		return cmd_usage(cmdtp);
-
-	if (strcmp(argv[2], "all") == 0) {
-		for (bank=1; bank<=CONFIG_SYS_MAX_FLASH_BANKS; ++bank) {
-			info = &flash_info[bank-1];
-			if (info->flash_id == FLASH_UNKNOWN) {
-				continue;
-			}
-			/*printf ("%sProtect Flash Bank # %ld\n", */
-			/*	p ? "" : "Un-", bank); */
-
-			for (i=0; i<info->sector_count; ++i) {
-#if defined(CONFIG_SYS_FLASH_PROTECTION)
-				if (flash_real_protect(info, i, p))
-					rcode = 1;
-				putc ('.');
-#else
-				info->protect[i] = p;
-#endif	/* CONFIG_SYS_FLASH_PROTECTION */
-			}
-		}
-
-#if defined(CONFIG_SYS_FLASH_PROTECTION)
-		if (!rcode) puts (" done\n");
-#endif	/* CONFIG_SYS_FLASH_PROTECTION */
-
-		return rcode;
-	}
-
-	if ((n = abbrev_spec(argv[2], &info, &sect_first, &sect_last)) != 0) {
-		if (n < 0) {
-			printf("Bad sector specification\n");
-			return 1;
-		}
-		/*printf("%sProtect Flash Sectors %d-%d in Bank # %d\n", */
-		/*	p ? "" : "Un-", sect_first, sect_last, */
-		/*	(info-flash_info)+1); */
-		for (i = sect_first; i <= sect_last; i++) {
-#if defined(CONFIG_SYS_FLASH_PROTECTION)
-			if (flash_real_protect(info, i, p))
-				rcode =  1;
-			putc ('.');
-#else
-			info->protect[i] = p;
-#endif	/* CONFIG_SYS_FLASH_PROTECTION */
-		}
-
-#if defined(CONFIG_SYS_FLASH_PROTECTION)
-		if (!rcode) puts (" done\n");
-#endif	/* CONFIG_SYS_FLASH_PROTECTION */
-
-		return rcode;
-	}
-
-	if (argc != 4)
-		return cmd_usage(cmdtp);
-
-	if (strcmp(argv[2], "bank") == 0) {
-		bank = simple_strtoul(argv[3], NULL, 16);
-		if ((bank < 1) || (bank > CONFIG_SYS_MAX_FLASH_BANKS)) {
-			printf ("Only FLASH Banks # 1 ... # %d supported\n",
-				CONFIG_SYS_MAX_FLASH_BANKS);
-			return 1;
-		}
-		printf ("%sProtect Flash Bank # %ld\n",
-			p ? "" : "Un-", bank);
-		info = &flash_info[bank-1];
-
-		if (info->flash_id == FLASH_UNKNOWN) {
-			printf ("missing or unknown FLASH type\n");
-			return 1;
-		}
-		for (i=0; i<info->sector_count; ++i) {
-#if defined(CONFIG_SYS_FLASH_PROTECTION)
-			if (flash_real_protect(info, i, p))
-				rcode =  1;
-			putc ('.');
-#else
-			info->protect[i] = p;
-#endif	/* CONFIG_SYS_FLASH_PROTECTION */
-		}
-
-#if defined(CONFIG_SYS_FLASH_PROTECTION)
-		if (!rcode)
-			puts(" done\n");
-#endif	/* CONFIG_SYS_FLASH_PROTECTION */
-
-		return rcode;
-	}
-
-	addr_first = simple_strtoul(argv[2], NULL, 16);
-	addr_last  = simple_strtoul(argv[3], NULL, 16);
-
-	if (addr_first >= addr_last)
-		return cmd_usage(cmdtp);
-
-	return flash_sect_protect (p, addr_first, addr_last);
-}
-int flash_sect_protect (int p, ulong addr_first, ulong addr_last)
-{
-	flash_info_t *info;
-	ulong bank;
-	int s_first, s_last;
-	int protected, i;
-	int rcode = 0;
-
-	protected = 0;
-
-	for (bank=0,info = &flash_info[0]; bank < CONFIG_SYS_MAX_FLASH_BANKS; ++bank, ++info) {
-		ulong b_end;
-		int sect;
-
-		if (info->flash_id == FLASH_UNKNOWN) {
-			continue;
-		}
-
-		b_end = info->start[0] + info->size - 1; /* bank end addr */
-
-		s_first = -1;		/* first sector to erase	*/
-		s_last  = -1;		/* last  sector to erase	*/
-
-		for (sect=0; sect < info->sector_count; ++sect) {
-			ulong end;		/* last address in current sect	*/
-			short s_end;
-
-			s_end = info->sector_count - 1;
-
-			end = (sect == s_end) ? b_end : info->start[sect + 1] - 1;
-
-			if (addr_first > end)
-				continue;
-			if (addr_last < info->start[sect])
-				continue;
-
-			if (addr_first == info->start[sect]) {
-				s_first = sect;
-			}
-			if (addr_last  == end) {
-				s_last  = sect;
-			}
-		}
-		if (s_first>=0 && s_first<=s_last) {
-			protected += s_last - s_first + 1;
-			for (i=s_first; i<=s_last; ++i) {
-#if defined(CONFIG_SYS_FLASH_PROTECTION)
-				if (flash_real_protect(info, i, p))
-					rcode = 1;
-				putc ('.');
-#else
-				info->protect[i] = p;
-#endif	/* CONFIG_SYS_FLASH_PROTECTION */
-			}
-		}
-#if defined(CONFIG_SYS_FLASH_PROTECTION)
-		if (!rcode) putc ('\n');
-#endif	/* CONFIG_SYS_FLASH_PROTECTION */
-
-	}
-	if (protected) {
-	    /*	printf ("%sProtected %d sectors\n", */
-	    /*	p ? "" : "Un-", protected); */
-	} else {
-	    printf ("Error: start and/or end address"
-			" not on sector boundary\n");
-		rcode = 1;
-	}
-	return rcode;
-}
-
-#endif
diff --git a/tools/updater/ctype.c b/tools/updater/ctype.c
deleted file mode 100644
index 96fa9ed114..0000000000
--- a/tools/updater/ctype.c
+++ /dev/null
@@ -1,40 +0,0 @@
-/*
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-/*
- *  linux/lib/ctype.c
- *
- *  Copyright (C) 1991, 1992  Linus Torvalds
- */
-
-#include <linux/ctype.h>
-
-unsigned char _ctype[] = {
-_C,_C,_C,_C,_C,_C,_C,_C,			/* 0-7 */
-_C,_C|_S,_C|_S,_C|_S,_C|_S,_C|_S,_C,_C,		/* 8-15 */
-_C,_C,_C,_C,_C,_C,_C,_C,			/* 16-23 */
-_C,_C,_C,_C,_C,_C,_C,_C,			/* 24-31 */
-_S|_SP,_P,_P,_P,_P,_P,_P,_P,			/* 32-39 */
-_P,_P,_P,_P,_P,_P,_P,_P,			/* 40-47 */
-_D,_D,_D,_D,_D,_D,_D,_D,			/* 48-55 */
-_D,_D,_P,_P,_P,_P,_P,_P,			/* 56-63 */
-_P,_U|_X,_U|_X,_U|_X,_U|_X,_U|_X,_U|_X,_U,	/* 64-71 */
-_U,_U,_U,_U,_U,_U,_U,_U,			/* 72-79 */
-_U,_U,_U,_U,_U,_U,_U,_U,			/* 80-87 */
-_U,_U,_U,_P,_P,_P,_P,_P,			/* 88-95 */
-_P,_L|_X,_L|_X,_L|_X,_L|_X,_L|_X,_L|_X,_L,	/* 96-103 */
-_L,_L,_L,_L,_L,_L,_L,_L,			/* 104-111 */
-_L,_L,_L,_L,_L,_L,_L,_L,			/* 112-119 */
-_L,_L,_L,_P,_P,_P,_P,_C,			/* 120-127 */
-0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,		/* 128-143 */
-0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,		/* 144-159 */
-_S|_SP,_P,_P,_P,_P,_P,_P,_P,_P,_P,_P,_P,_P,_P,_P,_P,   /* 160-175 */
-_P,_P,_P,_P,_P,_P,_P,_P,_P,_P,_P,_P,_P,_P,_P,_P,       /* 176-191 */
-_U,_U,_U,_U,_U,_U,_U,_U,_U,_U,_U,_U,_U,_U,_U,_U,       /* 192-207 */
-_U,_U,_U,_U,_U,_U,_U,_P,_U,_U,_U,_U,_U,_U,_U,_L,       /* 208-223 */
-_L,_L,_L,_L,_L,_L,_L,_L,_L,_L,_L,_L,_L,_L,_L,_L,       /* 224-239 */
-_L,_L,_L,_L,_L,_L,_L,_P,_L,_L,_L,_L,_L,_L,_L,_L};      /* 240-255 */
diff --git a/tools/updater/dummy.c b/tools/updater/dummy.c
deleted file mode 100644
index 9fe5ac1b1e..0000000000
--- a/tools/updater/dummy.c
+++ /dev/null
@@ -1 +0,0 @@
-volatile int __dummy = 0xDEADBEEF;
diff --git a/tools/updater/flash.c b/tools/updater/flash.c
deleted file mode 100644
index 5388872074..0000000000
--- a/tools/updater/flash.c
+++ /dev/null
@@ -1,168 +0,0 @@
-/*
- * (C) Copyright 2000-2006
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <flash.h>
-
-extern flash_info_t  flash_info[]; /* info for FLASH chips */
-
-/*-----------------------------------------------------------------------
- * Functions
- */
-
-/*-----------------------------------------------------------------------
- * Set protection status for monitor sectors
- *
- * The monitor is always located in the _first_ Flash bank.
- * If necessary you have to map the second bank at lower addresses.
- */
-void
-flash_protect (int flag, ulong from, ulong to, flash_info_t *info)
-{
-	ulong b_end = info->start[0] + info->size - 1;	/* bank end address */
-	short s_end = info->sector_count - 1;	/* index of last sector */
-	int i;
-
-	/* Do nothing if input data is bad. */
-	if (info->sector_count == 0 || info->size == 0 || to < from) {
-		return;
-	}
-
-	/* There is nothing to do if we have no data about the flash
-	 * or the protect range and flash range don't overlap.
-	 */
-	if (info->flash_id == FLASH_UNKNOWN ||
-	    to < info->start[0] || from > b_end) {
-		return;
-	}
-
-	for (i=0; i<info->sector_count; ++i) {
-		ulong end;		/* last address in current sect	*/
-
-		end = (i == s_end) ? b_end : info->start[i + 1] - 1;
-
-		/* Update protection if any part of the sector
-		 * is in the specified range.
-		 */
-		if (from <= end && to >= info->start[i]) {
-			if (flag & FLAG_PROTECT_CLEAR) {
-#if defined(CONFIG_SYS_FLASH_PROTECTION)
-				flash_real_protect(info, i, 0);
-#else
-				info->protect[i] = 0;
-#endif	/* CONFIG_SYS_FLASH_PROTECTION */
-			}
-			else if (flag & FLAG_PROTECT_SET) {
-#if defined(CONFIG_SYS_FLASH_PROTECTION)
-				flash_real_protect(info, i, 1);
-#else
-				info->protect[i] = 1;
-#endif	/* CONFIG_SYS_FLASH_PROTECTION */
-			}
-		}
-	}
-}
-
-/*-----------------------------------------------------------------------
- */
-
-flash_info_t *
-addr2info (ulong addr)
-{
-#ifndef CONFIG_SPD823TS
-	flash_info_t *info;
-	int i;
-
-	for (i=0, info = &flash_info[0]; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i, ++info) {
-		if (info->flash_id != FLASH_UNKNOWN &&
-		    addr >= info->start[0] &&
-		    /* WARNING - The '- 1' is needed if the flash
-		     * is at the end of the address space, since
-		     * info->start[0] + info->size wraps back to 0.
-		     * Please don't change this unless you understand this.
-		     */
-		    addr <= info->start[0] + info->size - 1) {
-			return (info);
-		}
-	}
-#endif /* CONFIG_SPD823TS */
-
-	return (NULL);
-}
-
-/*-----------------------------------------------------------------------
- * Copy memory to flash.
- * Make sure all target addresses are within Flash bounds,
- * and no protected sectors are hit.
- * Returns:
- * ERR_OK          0 - OK
- * ERR_TIMOUT      1 - write timeout
- * ERR_NOT_ERASED  2 - Flash not erased
- * ERR_PROTECTED   4 - target range includes protected sectors
- * ERR_INVAL       8 - target address not in Flash memory
- * ERR_ALIGN       16 - target address not aligned on boundary
- *			(only some targets require alignment)
- */
-int
-flash_write (char *src, ulong addr, ulong cnt)
-{
-#ifdef CONFIG_SPD823TS
-	return (ERR_TIMOUT);	/* any other error codes are possible as well */
-#else
-	int i;
-	ulong         end        = addr + cnt - 1;
-	flash_info_t *info_first = addr2info (addr);
-	flash_info_t *info_last  = addr2info (end );
-	flash_info_t *info;
-	int j;
-
-	if (cnt == 0) {
-		return (ERR_OK);
-	}
-
-	if (!info_first || !info_last) {
-		return (ERR_INVAL);
-	}
-
-	for (info = info_first; info <= info_last; ++info) {
-		ulong b_end = info->start[0] + info->size;	/* bank end addr */
-		short s_end = info->sector_count - 1;
-		for (i=0; i<info->sector_count; ++i) {
-			ulong e_addr = (i == s_end) ? b_end : info->start[i + 1];
-
-			if ((end >= info->start[i]) && (addr < e_addr) &&
-			    (info->protect[i] != 0) ) {
-				return (ERR_PROTECTED);
-			}
-		}
-	}
-
-	printf("\rWriting ");
-	for (j=0; j<20; j++) putc(177);
-	printf("\rWriting ");
-
-	/* finally write data to flash */
-	for (info = info_first; info <= info_last && cnt>0; ++info) {
-		ulong len;
-
-		len = info->start[0] + info->size - addr;
-		if (len > cnt)
-			len = cnt;
-
-		if ((i = write_buff(info, src, addr, len)) != 0) {
-			return (i);
-		}
-		cnt  -= len;
-		addr += len;
-		src  += len;
-	}
-	return (ERR_OK);
-#endif /* CONFIG_SPD823TS */
-}
-
-/*-----------------------------------------------------------------------
- */
diff --git a/tools/updater/flash_hw.c b/tools/updater/flash_hw.c
deleted file mode 100644
index 54a910b178..0000000000
--- a/tools/updater/flash_hw.c
+++ /dev/null
@@ -1,643 +0,0 @@
-/*
- * (C) Copyright 2001
- * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
- *
- * (C) Copyright 2002
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <flash.h>
-#include <asm/io.h>
-#include <memio.h>
-
-/*---------------------------------------------------------------------*/
-#undef DEBUG_FLASH
-
-#ifdef DEBUG_FLASH
-#define DEBUGF(fmt,args...) printf(fmt ,##args)
-#else
-#define DEBUGF(fmt,args...)
-#endif
-/*---------------------------------------------------------------------*/
-
-flash_info_t	flash_info[];
-
-static ulong flash_get_size (ulong addr, flash_info_t *info);
-static int flash_get_offsets (ulong base, flash_info_t *info);
-static int write_word (flash_info_t *info, ulong dest, ulong data);
-static void flash_reset (ulong addr);
-
-int flash_xd_nest;
-
-static void flash_to_xd(void)
-{
-    unsigned char x;
-
-    flash_xd_nest ++;
-
-    if (flash_xd_nest == 1)
-    {
-	DEBUGF("Flash on XD\n");
-	x = pci_read_cfg_byte(0, 0, 0x74);
-	pci_write_cfg_byte(0, 0, 0x74, x|1);
-    }
-}
-
-static void flash_to_mem(void)
-{
-    unsigned char x;
-
-    flash_xd_nest --;
-
-    if (flash_xd_nest == 0)
-    {
-	DEBUGF("Flash on memory bus\n");
-	x = pci_read_cfg_byte(0, 0, 0x74);
-	pci_write_cfg_byte(0, 0, 0x74, x&0xFE);
-    }
-}
-
-unsigned long flash_init_old(void)
-{
-    int i;
-
-    for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++)
-    {
-	flash_info[i].flash_id = FLASH_UNKNOWN;
-	flash_info[i].sector_count = 0;
-	flash_info[i].size = 0;
-    }
-
-
-    return 1;
-}
-
-unsigned long flash_init (void)
-{
-	unsigned int i;
-	unsigned long flash_size = 0;
-
-	flash_xd_nest = 0;
-
-	flash_to_xd();
-
-	/* Init: no FLASHes known */
-	for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
-		flash_info[i].flash_id = FLASH_UNKNOWN;
-		flash_info[i].sector_count = 0;
-		flash_info[i].size = 0;
-	}
-
-	DEBUGF("\n## Get flash size @ 0x%08x\n", CONFIG_SYS_FLASH_BASE);
-
-	flash_size = flash_get_size (CONFIG_SYS_FLASH_BASE, flash_info);
-
-	DEBUGF("## Flash bank size: %08lx\n", flash_size);
-
-	if (flash_size) {
-#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE && \
-    CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE + CONFIG_SYS_FLASH_MAX_SIZE
-		/* monitor protection ON by default */
-		flash_protect(FLAG_PROTECT_SET,
-			      CONFIG_SYS_MONITOR_BASE,
-			      CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN - 1,
-			      &flash_info[0]);
-#endif
-
-#ifdef CONFIG_ENV_IS_IN_FLASH
-		/* ENV protection ON by default */
-		flash_protect(FLAG_PROTECT_SET,
-			      CONFIG_ENV_ADDR,
-			      CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE - 1,
-			      &flash_info[0]);
-#endif
-
-	} else {
-		printf ("Warning: the BOOT Flash is not initialised !");
-	}
-
-	flash_to_mem();
-
-	return flash_size;
-}
-
-/*
- * The following code cannot be run from FLASH!
- */
-static ulong flash_get_size (ulong addr, flash_info_t *info)
-{
-	short i;
-	uchar value;
-	uchar *x = (uchar *)addr;
-
-	flash_to_xd();
-
-	/* Write auto select command: read Manufacturer ID */
-	x[0x0555] =  0xAA;
-	__asm__ volatile ("sync\n eieio");
-	x[0x02AA] =  0x55;
-	__asm__ volatile ("sync\n eieio");
-	x[0x0555] =  0x90;
-	__asm__ volatile ("sync\n eieio");
-
-	value = x[0];
-	__asm__ volatile ("sync\n eieio");
-
-	DEBUGF("Manuf. ID @ 0x%08lx: 0x%08x\n", (ulong)addr, value);
-
-	switch (value | (value << 16)) {
-		case AMD_MANUFACT:
-			info->flash_id = FLASH_MAN_AMD;
-			break;
-
-		case FUJ_MANUFACT:
-			info->flash_id = FLASH_MAN_FUJ;
-			break;
-
-		case STM_MANUFACT:
-			info->flash_id = FLASH_MAN_STM;
-			break;
-
-		default:
-			info->flash_id = FLASH_UNKNOWN;
-			info->sector_count = 0;
-			info->size = 0;
-			flash_reset (addr);
-			return 0;
-	}
-
-	value = x[1];
-	__asm__ volatile ("sync\n eieio");
-
-	DEBUGF("Device ID @ 0x%08lx: 0x%08x\n", addr+1, value);
-
-	switch (value) {
-		case AMD_ID_F040B:
-			DEBUGF("Am29F040B\n");
-			info->flash_id += FLASH_AM040;
-			info->sector_count = 8;
-			info->size = 0x00080000;
-			break;			/* => 512 kB		*/
-
-		case AMD_ID_LV040B:
-			DEBUGF("Am29LV040B\n");
-			info->flash_id += FLASH_AM040;
-			info->sector_count = 8;
-			info->size = 0x00080000;
-			break;			/* => 512 kB		*/
-
-		case AMD_ID_LV400T:
-			DEBUGF("Am29LV400T\n");
-			info->flash_id += FLASH_AM400T;
-			info->sector_count = 11;
-			info->size = 0x00100000;
-			break;			/* => 1 MB		*/
-
-		case AMD_ID_LV400B:
-			DEBUGF("Am29LV400B\n");
-			info->flash_id += FLASH_AM400B;
-			info->sector_count = 11;
-			info->size = 0x00100000;
-			break;			/* => 1 MB		*/
-
-		case AMD_ID_LV800T:
-			DEBUGF("Am29LV800T\n");
-			info->flash_id += FLASH_AM800T;
-			info->sector_count = 19;
-			info->size = 0x00200000;
-			break;			/* => 2 MB		*/
-
-		case AMD_ID_LV800B:
-			DEBUGF("Am29LV400B\n");
-			info->flash_id += FLASH_AM800B;
-			info->sector_count = 19;
-			info->size = 0x00200000;
-			break;			/* => 2 MB		*/
-
-		case AMD_ID_LV160T:
-			DEBUGF("Am29LV160T\n");
-			info->flash_id += FLASH_AM160T;
-			info->sector_count = 35;
-			info->size = 0x00400000;
-			break;			/* => 4 MB		*/
-
-		case AMD_ID_LV160B:
-			DEBUGF("Am29LV160B\n");
-			info->flash_id += FLASH_AM160B;
-			info->sector_count = 35;
-			info->size = 0x00400000;
-			break;			/* => 4 MB		*/
-
-		case AMD_ID_LV320T:
-			DEBUGF("Am29LV320T\n");
-			info->flash_id += FLASH_AM320T;
-			info->sector_count = 67;
-			info->size = 0x00800000;
-			break;			/* => 8 MB		*/
-
-#if 0
-		/* Has the same ID as AMD_ID_LV320T, to be fixed */
-		case AMD_ID_LV320B:
-			DEBUGF("Am29LV320B\n");
-			info->flash_id += FLASH_AM320B;
-			info->sector_count = 67;
-			info->size = 0x00800000;
-			break;			/* => 8 MB		*/
-#endif
-
-		case AMD_ID_LV033C:
-			DEBUGF("Am29LV033C\n");
-			info->flash_id += FLASH_AM033C;
-			info->sector_count = 64;
-			info->size = 0x01000000;
-			break;			/* => 16Mb		*/
-
-		case STM_ID_F040B:
-			DEBUGF("M29F040B\n");
-			info->flash_id += FLASH_AM040;
-			info->sector_count = 8;
-			info->size = 0x00080000;
-			break;			/* => 512 kB		*/
-
-		default:
-			info->flash_id = FLASH_UNKNOWN;
-			flash_reset (addr);
-			flash_to_mem();
-			return (0);		/* => no or unknown flash */
-
-	}
-
-	if (info->sector_count > CONFIG_SYS_MAX_FLASH_SECT) {
-		printf ("** ERROR: sector count %d > max (%d) **\n",
-			info->sector_count, CONFIG_SYS_MAX_FLASH_SECT);
-		info->sector_count = CONFIG_SYS_MAX_FLASH_SECT;
-	}
-
-	if (! flash_get_offsets (addr, info)) {
-		flash_reset (addr);
-		flash_to_mem();
-		return 0;
-	}
-
-	/* check for protected sectors */
-	for (i = 0; i < info->sector_count; i++) {
-		/* read sector protection at sector address, (A7 .. A0) = 0x02 */
-		/* D0 = 1 if protected */
-		value = in8(info->start[i] + 2);
-		iobarrier_rw();
-		info->protect[i] = (value & 1) != 0;
-	}
-
-	/*
-	 * Reset bank to read mode
-	 */
-	flash_reset (addr);
-
-	flash_to_mem();
-
-	return (info->size);
-}
-
-static int flash_get_offsets (ulong base, flash_info_t *info)
-{
-	unsigned int i;
-
-	switch (info->flash_id & FLASH_TYPEMASK) {
-		case FLASH_AM040:
-			/* set sector offsets for uniform sector type	*/
-			for (i = 0; i < info->sector_count; i++) {
-				info->start[i] = base + i * info->size /
-							    info->sector_count;
-			}
-			break;
-		default:
-			return 0;
-	}
-
-	return 1;
-}
-
-int flash_erase (flash_info_t *info, int s_first, int s_last)
-{
-	volatile ulong addr = info->start[0];
-	int flag, prot, sect, l_sect;
-	ulong start, now, last;
-
-	flash_to_xd();
-
-	if (s_first < 0 || s_first > s_last) {
-		if (info->flash_id == FLASH_UNKNOWN) {
-			printf ("- missing\n");
-		} else {
-			printf ("- no sectors to erase\n");
-		}
-		flash_to_mem();
-		return 1;
-	}
-
-	if (info->flash_id == FLASH_UNKNOWN) {
-		printf ("Can't erase unknown flash type %08lx - aborted\n",
-			info->flash_id);
-		flash_to_mem();
-		return 1;
-	}
-
-	prot = 0;
-	for (sect=s_first; sect<=s_last; ++sect) {
-		if (info->protect[sect]) {
-			prot++;
-		}
-	}
-
-	if (prot) {
-		printf ("- Warning: %d protected sectors will not be erased!\n",
-			prot);
-	} else {
-		printf ("");
-	}
-
-	l_sect = -1;
-
-	/* Disable interrupts which might cause a timeout here */
-	flag = disable_interrupts();
-
-	out8(addr + 0x555, 0xAA);
-	iobarrier_rw();
-	out8(addr + 0x2AA, 0x55);
-	iobarrier_rw();
-	out8(addr + 0x555, 0x80);
-	iobarrier_rw();
-	out8(addr + 0x555, 0xAA);
-	iobarrier_rw();
-	out8(addr + 0x2AA, 0x55);
-	iobarrier_rw();
-
-	/* Start erase on unprotected sectors */
-	for (sect = s_first; sect<=s_last; sect++) {
-		if (info->protect[sect] == 0) {	/* not protected */
-			addr = info->start[sect];
-			out8(addr, 0x30);
-			iobarrier_rw();
-			l_sect = sect;
-		}
-	}
-
-	/* re-enable interrupts if necessary */
-	if (flag)
-		enable_interrupts();
-
-	/* wait at least 80us - let's wait 1 ms */
-	udelay (1000);
-
-	/*
-	 * We wait for the last triggered sector
-	 */
-	if (l_sect < 0)
-		goto DONE;
-
-	start = get_timer (0);
-	last  = start;
-	addr = info->start[l_sect];
-
-	DEBUGF ("Start erase timeout: %d\n", CONFIG_SYS_FLASH_ERASE_TOUT);
-
-	while ((in8(addr) & 0x80) != 0x80) {
-		if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
-			printf ("Timeout\n");
-			flash_reset (info->start[0]);
-			flash_to_mem();
-			return 1;
-		}
-		/* show that we're waiting */
-		if ((now - last) > 1000) {	/* every second */
-			putc ('.');
-			last = now;
-		}
-		iobarrier_rw();
-	}
-
-DONE:
-	/* reset to read mode */
-	flash_reset (info->start[0]);
-	flash_to_mem();
-
-	printf (" done\n");
-	return 0;
-}
-
-/*
- * Copy memory to flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
-{
-	ulong cp, wp, data;
-	int i, l, rc;
-	ulong out_cnt = 0;
-
-	flash_to_xd();
-
-	wp = (addr & ~3);	/* get lower word aligned address */
-
-	/*
-	 * handle unaligned start bytes
-	 */
-	if ((l = addr - wp) != 0) {
-		data = 0;
-		for (i=0, cp=wp; i<l; ++i, ++cp) {
-			data = (data << 8) | (*(uchar *)cp);
-		}
-		for (; i<4 && cnt>0; ++i) {
-			data = (data << 8) | *src++;
-			--cnt;
-			++cp;
-		}
-		for (; cnt==0 && i<4; ++i, ++cp) {
-			data = (data << 8) | (*(uchar *)cp);
-		}
-
-		if ((rc = write_word(info, wp, data)) != 0) {
-			flash_to_mem();
-			return (rc);
-		}
-		wp += 4;
-	}
-
-	putc(219);
-
-	/*
-	 * handle word aligned part
-	 */
-	while (cnt >= 4) {
-	    if (out_cnt>26214)
-	    {
-		putc(219);
-		out_cnt = 0;
-	    }
-	    data = 0;
-	    for (i=0; i<4; ++i) {
-		data = (data << 8) | *src++;
-	    }
-	    if ((rc = write_word(info, wp, data)) != 0) {
-		flash_to_mem();
-		return (rc);
-	    }
-	    wp  += 4;
-	    cnt -= 4;
-	    out_cnt += 4;
-	}
-
-	if (cnt == 0) {
-		flash_to_mem();
-		return (0);
-	}
-
-	/*
-	 * handle unaligned tail bytes
-	 */
-	data = 0;
-	for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) {
-		data = (data << 8) | *src++;
-		--cnt;
-	}
-	for (; i<4; ++i, ++cp) {
-		data = (data << 8) | (*(uchar *)cp);
-	}
-
-	flash_to_mem();
-	return (write_word(info, wp, data));
-}
-
-/*
- * Write a word to Flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-static int write_word (flash_info_t *info, ulong dest, ulong data)
-{
-	volatile ulong addr = info->start[0];
-	ulong start;
-	int i;
-
-	flash_to_xd();
-
-	/* Check if Flash is (sufficiently) erased */
-	if ((in32(dest) & data) != data) {
-		flash_to_mem();
-		return (2);
-	}
-
-	/* write each byte out */
-	for (i = 0; i < 4; i++) {
-		char *data_ch = (char *)&data;
-		int flag = disable_interrupts();
-
-		out8(addr + 0x555, 0xAA);
-		iobarrier_rw();
-		out8(addr + 0x2AA, 0x55);
-		iobarrier_rw();
-		out8(addr + 0x555, 0xA0);
-		iobarrier_rw();
-		out8(dest+i, data_ch[i]);
-		iobarrier_rw();
-
-		/* re-enable interrupts if necessary */
-		if (flag)
-			enable_interrupts();
-
-		/* data polling for D7 */
-		start = get_timer (0);
-		while ((in8(dest+i) & 0x80) != (data_ch[i] & 0x80)) {
-			if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
-				flash_reset (addr);
-				flash_to_mem();
-				return (1);
-			}
-			iobarrier_rw();
-		}
-	}
-
-	flash_reset (addr);
-	flash_to_mem();
-	return (0);
-}
-
-/*
- * Reset bank to read mode
- */
-static void flash_reset (ulong addr)
-{
-	flash_to_xd();
-	out8(addr, 0xF0);	/* reset bank */
-	iobarrier_rw();
-	flash_to_mem();
-}
-
-void flash_print_info (flash_info_t *info)
-{
-	int i;
-
-	if (info->flash_id == FLASH_UNKNOWN) {
-		printf ("missing or unknown FLASH type\n");
-		return;
-	}
-
-	switch (info->flash_id & FLASH_VENDMASK) {
-	case FLASH_MAN_AMD:	printf ("AMD ");		break;
-	case FLASH_MAN_FUJ:	printf ("FUJITSU ");		break;
-	case FLASH_MAN_BM:	printf ("BRIGHT MICRO ");	break;
-	case FLASH_MAN_STM:	printf ("SGS THOMSON ");	break;
-	default:		printf ("Unknown Vendor ");	break;
-	}
-
-	switch (info->flash_id & FLASH_TYPEMASK) {
-	case FLASH_AM040:	printf ("29F040 or 29LV040 (4 Mbit, uniform sectors)\n");
-				break;
-	case FLASH_AM400B:	printf ("AM29LV400B (4 Mbit, bottom boot sect)\n");
-				break;
-	case FLASH_AM400T:	printf ("AM29LV400T (4 Mbit, top boot sector)\n");
-				break;
-	case FLASH_AM800B:	printf ("AM29LV800B (8 Mbit, bottom boot sect)\n");
-				break;
-	case FLASH_AM800T:	printf ("AM29LV800T (8 Mbit, top boot sector)\n");
-				break;
-	case FLASH_AM160B:	printf ("AM29LV160B (16 Mbit, bottom boot sect)\n");
-				break;
-	case FLASH_AM160T:	printf ("AM29LV160T (16 Mbit, top boot sector)\n");
-				break;
-	case FLASH_AM320B:	printf ("AM29LV320B (32 Mbit, bottom boot sect)\n");
-				break;
-	case FLASH_AM320T:	printf ("AM29LV320T (32 Mbit, top boot sector)\n");
-				break;
-	default:		printf ("Unknown Chip Type\n");
-				break;
-	}
-
-	if (info->size % 0x100000 == 0) {
-		printf ("  Size: %ld MB in %d Sectors\n",
-			info->size / 0x100000, info->sector_count);
-	} else if (info->size % 0x400 == 0) {
-		printf ("  Size: %ld KB in %d Sectors\n",
-			info->size / 0x400, info->sector_count);
-	} else {
-		printf ("  Size: %ld B in %d Sectors\n",
-			info->size, info->sector_count);
-	}
-
-	printf ("  Sector Start Addresses:");
-	for (i=0; i<info->sector_count; ++i) {
-		if ((i % 5) == 0)
-			printf ("\n   ");
-		printf (" %08lX%s",
-			info->start[i],
-			info->protect[i] ? " (RO)" : "     "
-		);
-	}
-	printf ("\n");
-}
diff --git a/tools/updater/junk b/tools/updater/junk
deleted file mode 100644
index f73285a832..0000000000
--- a/tools/updater/junk
+++ /dev/null
@@ -1 +0,0 @@
-................................................................................................................................................................................................................................................................
\ No newline at end of file
diff --git a/tools/updater/ppcstring.S b/tools/updater/ppcstring.S
deleted file mode 100644
index 8152ac9b0f..0000000000
--- a/tools/updater/ppcstring.S
+++ /dev/null
@@ -1,213 +0,0 @@
-/*
- * String handling functions for PowerPC.
- *
- * Copyright (C) 1996 Paul Mackerras.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-#include <ppc_asm.tmpl>
-#include <asm/errno.h>
-
-	.globl	strcpy
-strcpy:
-	addi	r5,r3,-1
-	addi	r4,r4,-1
-1:	lbzu	r0,1(r4)
-	cmpwi	0,r0,0
-	stbu	r0,1(r5)
-	bne	1b
-	blr
-
-	.globl	strncpy
-strncpy:
-	cmpwi	0,r5,0
-	beqlr
-	mtctr	r5
-	addi	r6,r3,-1
-	addi	r4,r4,-1
-1:	lbzu	r0,1(r4)
-	cmpwi	0,r0,0
-	stbu	r0,1(r6)
-	bdnzf	2,1b		/* dec ctr, branch if ctr != 0 && !cr0.eq */
-	blr
-
-	.globl	strcat
-strcat:
-	addi	r5,r3,-1
-	addi	r4,r4,-1
-1:	lbzu	r0,1(r5)
-	cmpwi	0,r0,0
-	bne	1b
-	addi	r5,r5,-1
-1:	lbzu	r0,1(r4)
-	cmpwi	0,r0,0
-	stbu	r0,1(r5)
-	bne	1b
-	blr
-
-	.globl	strcmp
-strcmp:
-	addi	r5,r3,-1
-	addi	r4,r4,-1
-1:	lbzu	r3,1(r5)
-	cmpwi	1,r3,0
-	lbzu	r0,1(r4)
-	subf.	r3,r0,r3
-	beqlr	1
-	beq	1b
-	blr
-
-	.globl	strlen
-strlen:
-	addi	r4,r3,-1
-1:	lbzu	r0,1(r4)
-	cmpwi	0,r0,0
-	bne	1b
-	subf	r3,r3,r4
-	blr
-
-	.globl	memset
-memset:
-	rlwimi	r4,r4,8,16,23
-	rlwimi	r4,r4,16,0,15
-	addi	r6,r3,-4
-	cmplwi	0,r5,4
-	blt	7f
-	stwu	r4,4(r6)
-	beqlr
-	andi.	r0,r6,3
-	add	r5,r0,r5
-	subf	r6,r0,r6
-	rlwinm	r0,r5,32-2,2,31
-	mtctr	r0
-	bdz	6f
-1:	stwu	r4,4(r6)
-	bdnz	1b
-6:	andi.	r5,r5,3
-7:	cmpwi	0,r5,0
-	beqlr
-	mtctr	r5
-	addi	r6,r6,3
-8:	stbu	r4,1(r6)
-	bdnz	8b
-	blr
-
-	.globl	bcopy
-bcopy:
-	mr	r6,r3
-	mr	r3,r4
-	mr	r4,r6
-	b	memcpy
-
-	.globl	memmove
-memmove:
-	cmplw	0,r3,r4
-	bgt	backwards_memcpy
-	/* fall through */
-
-	.globl	memcpy
-memcpy:
-	rlwinm.	r7,r5,32-3,3,31		/* r0 = r5 >> 3 */
-	addi	r6,r3,-4
-	addi	r4,r4,-4
-	beq	2f			/* if less than 8 bytes to do */
-	andi.	r0,r6,3			/* get dest word aligned */
-	mtctr	r7
-	bne	5f
-1:	lwz	r7,4(r4)
-	lwzu	r8,8(r4)
-	stw	r7,4(r6)
-	stwu	r8,8(r6)
-	bdnz	1b
-	andi.	r5,r5,7
-2:	cmplwi	0,r5,4
-	blt	3f
-	lwzu	r0,4(r4)
-	addi	r5,r5,-4
-	stwu	r0,4(r6)
-3:	cmpwi	0,r5,0
-	beqlr
-	mtctr	r5
-	addi	r4,r4,3
-	addi	r6,r6,3
-4:	lbzu	r0,1(r4)
-	stbu	r0,1(r6)
-	bdnz	4b
-	blr
-5:	subfic	r0,r0,4
-	mtctr	r0
-6:	lbz	r7,4(r4)
-	addi	r4,r4,1
-	stb	r7,4(r6)
-	addi	r6,r6,1
-	bdnz	6b
-	subf	r5,r0,r5
-	rlwinm.	r7,r5,32-3,3,31
-	beq	2b
-	mtctr	r7
-	b	1b
-
-	.globl	backwards_memcpy
-backwards_memcpy:
-	rlwinm.	r7,r5,32-3,3,31		/* r0 = r5 >> 3 */
-	add	r6,r3,r5
-	add	r4,r4,r5
-	beq	2f
-	andi.	r0,r6,3
-	mtctr	r7
-	bne	5f
-1:	lwz	r7,-4(r4)
-	lwzu	r8,-8(r4)
-	stw	r7,-4(r6)
-	stwu	r8,-8(r6)
-	bdnz	1b
-	andi.	r5,r5,7
-2:	cmplwi	0,r5,4
-	blt	3f
-	lwzu	r0,-4(r4)
-	subi	r5,r5,4
-	stwu	r0,-4(r6)
-3:	cmpwi	0,r5,0
-	beqlr
-	mtctr	r5
-4:	lbzu	r0,-1(r4)
-	stbu	r0,-1(r6)
-	bdnz	4b
-	blr
-5:	mtctr	r0
-6:	lbzu	r7,-1(r4)
-	stbu	r7,-1(r6)
-	bdnz	6b
-	subf	r5,r0,r5
-	rlwinm.	r7,r5,32-3,3,31
-	beq	2b
-	mtctr	r7
-	b	1b
-
-	.globl	memcmp
-memcmp:
-	cmpwi	0,r5,0
-	ble-	2f
-	mtctr	r5
-	addi	r6,r3,-1
-	addi	r4,r4,-1
-1:	lbzu	r3,1(r6)
-	lbzu	r0,1(r4)
-	subf.	r3,r0,r3
-	bdnzt	2,1b
-	blr
-2:	li	r3,0
-	blr
-
-	.global	memchr
-memchr:
-	cmpwi	0,r5,0
-	ble-	2f
-	mtctr	r5
-	addi	r3,r3,-1
-1:	lbzu	r0,1(r3)
-	cmpw	0,r0,r4
-	bdnzf	2,1b
-	beqlr
-2:	li	r3,0
-	blr
diff --git a/tools/updater/string.c b/tools/updater/string.c
deleted file mode 100644
index 954fb01e20..0000000000
--- a/tools/updater/string.c
+++ /dev/null
@@ -1,340 +0,0 @@
-/*
- *  linux/lib/string.c
- *
- *  Copyright (C) 1991, 1992  Linus Torvalds
- */
-
-/*
- * stupid library routines.. The optimized versions should generally be found
- * as inline code in <asm-xx/string.h>
- *
- * These are buggy as well..
- */
-
-#include <linux/types.h>
-#include <linux/string.h>
-#include <malloc.h>
-
-#define __HAVE_ARCH_BCOPY
-#define __HAVE_ARCH_MEMCMP
-#define __HAVE_ARCH_MEMCPY
-#define __HAVE_ARCH_MEMMOVE
-#define __HAVE_ARCH_MEMSET
-#define __HAVE_ARCH_STRCAT
-#define __HAVE_ARCH_STRCMP
-#define __HAVE_ARCH_STRCPY
-#define __HAVE_ARCH_STRLEN
-#define __HAVE_ARCH_STRNCPY
-
-char * ___strtok = NULL;
-
-#ifndef __HAVE_ARCH_STRCPY
-char * strcpy(char * dest,const char *src)
-{
-	char *tmp = dest;
-
-	while ((*dest++ = *src++) != '\0')
-		/* nothing */;
-	return tmp;
-}
-#endif
-
-#ifndef __HAVE_ARCH_STRNCPY
-char * strncpy(char * dest,const char *src,size_t count)
-{
-	char *tmp = dest;
-
-	while (count-- && (*dest++ = *src++) != '\0')
-		/* nothing */;
-
-	return tmp;
-}
-#endif
-
-#ifndef __HAVE_ARCH_STRCAT
-char * strcat(char * dest, const char * src)
-{
-	char *tmp = dest;
-
-	while (*dest)
-		dest++;
-	while ((*dest++ = *src++) != '\0')
-		;
-
-	return tmp;
-}
-#endif
-
-#ifndef __HAVE_ARCH_STRNCAT
-char * strncat(char *dest, const char *src, size_t count)
-{
-	char *tmp = dest;
-
-	if (count) {
-		while (*dest)
-			dest++;
-		while ((*dest++ = *src++)) {
-			if (--count == 0) {
-				*dest = '\0';
-				break;
-			}
-		}
-	}
-
-	return tmp;
-}
-#endif
-
-#ifndef __HAVE_ARCH_STRCMP
-int strcmp(const char * cs,const char * ct)
-{
-	register signed char __res;
-
-	while (1) {
-		if ((__res = *cs - *ct++) != 0 || !*cs++)
-			break;
-	}
-
-	return __res;
-}
-#endif
-
-#ifndef __HAVE_ARCH_STRNCMP
-int strncmp(const char * cs,const char * ct,size_t count)
-{
-	register signed char __res = 0;
-
-	while (count) {
-		if ((__res = *cs - *ct++) != 0 || !*cs++)
-			break;
-		count--;
-	}
-
-	return __res;
-}
-#endif
-
-#ifndef __HAVE_ARCH_STRCHR
-char * strchr(const char * s, int c)
-{
-	for(; *s != (char) c; ++s)
-		if (*s == '\0')
-			return NULL;
-	return (char *) s;
-}
-#endif
-
-#ifndef __HAVE_ARCH_STRRCHR
-char * strrchr(const char * s, int c)
-{
-       const char *p = s + strlen(s);
-       do {
-	   if (*p == (char)c)
-	       return (char *)p;
-       } while (--p >= s);
-       return NULL;
-}
-#endif
-
-#ifndef __HAVE_ARCH_STRLEN
-size_t strlen(const char * s)
-{
-	const char *sc;
-
-	for (sc = s; *sc != '\0'; ++sc)
-		/* nothing */;
-	return sc - s;
-}
-#endif
-
-#ifndef __HAVE_ARCH_STRNLEN
-size_t strnlen(const char * s, size_t count)
-{
-	const char *sc;
-
-	for (sc = s; count-- && *sc != '\0'; ++sc)
-		/* nothing */;
-	return sc - s;
-}
-#endif
-
-#ifndef __HAVE_ARCH_STRDUP
-char * strdup(const char *s)
-{
-	char *new;
-
-	if ((s == NULL)	||
-	    ((new = malloc (strlen(s) + 1)) == NULL) ) {
-		return NULL;
-	}
-
-	strcpy (new, s);
-	return new;
-}
-#endif
-
-#ifndef __HAVE_ARCH_STRSPN
-size_t strspn(const char *s, const char *accept)
-{
-	const char *p;
-	const char *a;
-	size_t count = 0;
-
-	for (p = s; *p != '\0'; ++p) {
-		for (a = accept; *a != '\0'; ++a) {
-			if (*p == *a)
-				break;
-		}
-		if (*a == '\0')
-			return count;
-		++count;
-	}
-
-	return count;
-}
-#endif
-
-#ifndef __HAVE_ARCH_STRPBRK
-char * strpbrk(const char * cs,const char * ct)
-{
-	const char *sc1,*sc2;
-
-	for( sc1 = cs; *sc1 != '\0'; ++sc1) {
-		for( sc2 = ct; *sc2 != '\0'; ++sc2) {
-			if (*sc1 == *sc2)
-				return (char *) sc1;
-		}
-	}
-	return NULL;
-}
-#endif
-
-#ifndef __HAVE_ARCH_STRTOK
-char * strtok(char * s,const char * ct)
-{
-	char *sbegin, *send;
-
-	sbegin  = s ? s : ___strtok;
-	if (!sbegin) {
-		return NULL;
-	}
-	sbegin += strspn(sbegin,ct);
-	if (*sbegin == '\0') {
-		___strtok = NULL;
-		return( NULL );
-	}
-	send = strpbrk( sbegin, ct);
-	if (send && *send != '\0')
-		*send++ = '\0';
-	___strtok = send;
-	return (sbegin);
-}
-#endif
-
-#ifndef __HAVE_ARCH_MEMSET
-void * memset(void * s,char c,size_t count)
-{
-	char *xs = (char *) s;
-
-	while (count--)
-		*xs++ = c;
-
-	return s;
-}
-#endif
-
-#ifndef __HAVE_ARCH_BCOPY
-char * bcopy(const char * src, char * dest, int count)
-{
-	char *tmp = dest;
-
-	while (count--)
-		*tmp++ = *src++;
-
-	return dest;
-}
-#endif
-
-#ifndef __HAVE_ARCH_MEMCPY
-void * memcpy(void * dest,const void *src,size_t count)
-{
-	char *tmp = (char *) dest, *s = (char *) src;
-
-	while (count--)
-		*tmp++ = *s++;
-
-	return dest;
-}
-#endif
-
-#ifndef __HAVE_ARCH_MEMMOVE
-void * memmove(void * dest,const void *src,size_t count)
-{
-	char *tmp, *s;
-
-	if (dest <= src) {
-		tmp = (char *) dest;
-		s = (char *) src;
-		while (count--)
-			*tmp++ = *s++;
-		}
-	else {
-		tmp = (char *) dest + count;
-		s = (char *) src + count;
-		while (count--)
-			*--tmp = *--s;
-		}
-
-	return dest;
-}
-#endif
-
-#ifndef __HAVE_ARCH_MEMCMP
-int memcmp(const void * cs,const void * ct,size_t count)
-{
-	const unsigned char *su1, *su2;
-	signed char res = 0;
-
-	for( su1 = cs, su2 = ct; 0 < count; ++su1, ++su2, count--)
-		if ((res = *su1 - *su2) != 0)
-			break;
-	return res;
-}
-#endif
-
-/*
- * find the first occurrence of byte 'c', or 1 past the area if none
- */
-#ifndef __HAVE_ARCH_MEMSCAN
-void * memscan(void * addr, int c, size_t size)
-{
-	unsigned char * p = (unsigned char *) addr;
-
-	while (size) {
-		if (*p == c)
-			return (void *) p;
-		p++;
-		size--;
-	}
-	return (void *) p;
-}
-#endif
-
-#ifndef __HAVE_ARCH_STRSTR
-char * strstr(const char * s1,const char * s2)
-{
-	int l1, l2;
-
-	l2 = strlen(s2);
-	if (!l2)
-		return (char *) s1;
-	l1 = strlen(s1);
-	while (l1 >= l2) {
-		l1--;
-		if (!memcmp(s1,s2,l2))
-			return (char *) s1;
-		s1++;
-	}
-	return NULL;
-}
-#endif
diff --git a/tools/updater/update.c b/tools/updater/update.c
deleted file mode 100644
index 18f122ad23..0000000000
--- a/tools/updater/update.c
+++ /dev/null
@@ -1,63 +0,0 @@
-#include <common.h>
-#include <exports.h>
-
-extern unsigned long __dummy;
-void do_reset (void);
-void do_updater(void);
-
-void _main(void)
-{
-    int i;
-    printf("U-Boot Firmware Updater\n\n\n");
-    printf("****************************************************\n"
-	       "*  ATTENTION!! PLEASE READ THIS NOTICE CAREFULLY!  *\n"
-	       "****************************************************\n\n"
-	       "This program  will update your computer's  firmware.\n"
-	       "Do NOT  remove the disk,  reset the  machine,  or do\n"
-	       "anything that  might disrupt functionality.  If this\n");
-    printf("Program fails, your computer  might be unusable, and\n"
-	       "you will  need to return your  board for reflashing.\n"
-	       "If you find this too risky,  remove the diskette and\n"
-	       "switch off your  machine now.  Otherwise  press the \n"
-	       "SPACE key now to start the process\n\n");
-    do
-    {
-	char x;
-	while (!tstc());
-	x = getc();
-	if (x == ' ') break;
-    } while (1);
-
-    do_updater();
-
-    i = 5;
-
-    printf("\nUpdate done. Please remove diskette.\n");
-    printf("The machine will automatically reset in %d seconds\n", i);
-    printf("You can switch off/reset now when the floppy is removed\n\n");
-
-    while (i)
-    {
-	printf("Resetting in %d\r", i);
-	udelay(1000000);
-	i--;
-    }
-    do_reset();
-    while (1);
-}
-
-void do_updater(void)
-{
-    unsigned long *addr = &__dummy + 65;
-    unsigned long flash_size = flash_init();
-    int rc;
-
-    flash_sect_protect(0, 0xFFF00000, 0xFFF7FFFF);
-    printf("Erasing ");
-    flash_sect_erase(0xFFF00000, 0xFFF7FFFF);
-    printf("Writing ");
-    rc = flash_write((uchar *)addr, 0xFFF00000, 0x7FFFF);
-    if (rc != 0) printf("\nFlashing failed due to error %d\n", rc);
-    else printf("\ndone\n");
-    flash_sect_protect(1, 0xFFF00000, 0xFFF7FFFF);
-}
diff --git a/tools/updater/utils.c b/tools/updater/utils.c
deleted file mode 100644
index 61a611876c..0000000000
--- a/tools/updater/utils.c
+++ /dev/null
@@ -1,148 +0,0 @@
-#include <common.h>
-#include <asm/processor.h>
-#include <memio.h>
-#include <linux/ctype.h>
-
-static __inline__ unsigned long
-get_msr(void)
-{
-	unsigned long msr;
-
-	asm volatile("mfmsr %0" : "=r" (msr) :);
-	return msr;
-}
-
-static __inline__ void
-set_msr(unsigned long msr)
-{
-	asm volatile("mtmsr %0" : : "r" (msr));
-}
-
-static __inline__ unsigned long
-get_dec(void)
-{
-	unsigned long val;
-
-	asm volatile("mfdec %0" : "=r" (val) :);
-	return val;
-}
-
-
-static __inline__ void
-set_dec(unsigned long val)
-{
-	asm volatile("mtdec %0" : : "r" (val));
-}
-
-
-void
-enable_interrupts(void)
-{
-    set_msr (get_msr() | MSR_EE);
-}
-
-/* returns flag if MSR_EE was set before */
-int
-disable_interrupts(void)
-{
-    ulong msr;
-
-    msr = get_msr();
-    set_msr (msr & ~MSR_EE);
-    return ((msr & MSR_EE) != 0);
-}
-
-u8 in8(u32 port)
-{
-    return in_byte(port);
-}
-
-void out8(u32 port, u8 val)
-{
-    out_byte(port, val);
-}
-
-unsigned long in32(u32 port)
-{
-    return in_long(port);
-}
-
-unsigned long simple_strtoul(const char *cp,char **endp,unsigned int base)
-{
-	unsigned long result = 0,value;
-
-	if (*cp == '0') {
-		cp++;
-		if ((*cp == 'x') && isxdigit(cp[1])) {
-			base = 16;
-			cp++;
-		}
-		if (!base) {
-			base = 8;
-		}
-	}
-	if (!base) {
-		base = 10;
-	}
-	while (isxdigit(*cp) && (value = isdigit(*cp) ? *cp-'0' : (islower(*cp)
-	    ? toupper(*cp) : *cp)-'A'+10) < base) {
-		result = result*base + value;
-		cp++;
-	}
-	if (endp)
-		*endp = (char *)cp;
-	return result;
-}
-
-long simple_strtol(const char *cp,char **endp,unsigned int base)
-{
-	if(*cp=='-')
-		return -simple_strtoul(cp+1,endp,base);
-	return simple_strtoul(cp,endp,base);
-}
-
-static inline void
-soft_restart(unsigned long addr)
-{
-	/* SRR0 has system reset vector, SRR1 has default MSR value */
-	/* rfi restores MSR from SRR1 and sets the PC to the SRR0 value */
-
-	__asm__ __volatile__ ("mtspr    26, %0"         :: "r" (addr));
-	__asm__ __volatile__ ("li       4, (1 << 6)"    ::: "r4");
-	__asm__ __volatile__ ("mtspr    27, 4");
-	__asm__ __volatile__ ("rfi");
-
-	while(1);       /* not reached */
-}
-
-void
-do_reset (void)
-{
-	ulong addr;
-	/* flush and disable I/D cache */
-	__asm__ __volatile__ ("mfspr    3, 1008"        ::: "r3");
-	__asm__ __volatile__ ("ori      5, 5, 0xcc00"   ::: "r5");
-	__asm__ __volatile__ ("ori      4, 3, 0xc00"    ::: "r4");
-	__asm__ __volatile__ ("andc     5, 3, 5"        ::: "r5");
-	__asm__ __volatile__ ("sync");
-	__asm__ __volatile__ ("mtspr    1008, 4");
-	__asm__ __volatile__ ("isync");
-	__asm__ __volatile__ ("sync");
-	__asm__ __volatile__ ("mtspr    1008, 5");
-	__asm__ __volatile__ ("isync");
-	__asm__ __volatile__ ("sync");
-
-#ifdef CONFIG_SYS_RESET_ADDRESS
-	addr = CONFIG_SYS_RESET_ADDRESS;
-#else
-	/*
-	 * note: when CONFIG_SYS_MONITOR_BASE points to a RAM address,
-	 * CONFIG_SYS_MONITOR_BASE - sizeof (ulong) is usually a valid
-	 * address. Better pick an address known to be invalid on your
-	 * system and assign it to CONFIG_SYS_RESET_ADDRESS.
-	 */
-	addr = CONFIG_SYS_MONITOR_BASE - sizeof (ulong);
-#endif
-	soft_restart(addr);
-	while(1);       /* not reached */
-}